diff --git a/drivers/net/wireless/ssv6x5x/Kconfig b/drivers/net/wireless/ssv6x5x/Kconfig
new file mode 100755
index 000000000..ebfe6153f
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/Kconfig
@@ -0,0 +1,8 @@
+#menu "iComm-semi 6X5X WLAN support"
+config SSV6X5X
+	tristate "SSV6X5X Wireless driver"
+	depends on MAC80211 && MMC
+	---help---
+		Enable iComm-semi SSV6X5X WLAN kernel driver.
+
+#endmenu
diff --git a/drivers/net/wireless/ssv6x5x/Makefile b/drivers/net/wireless/ssv6x5x/Makefile
new file mode 100755
index 000000000..d3821b37f
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/Makefile
@@ -0,0 +1,142 @@
+KMODULE_NAME = ssv6x5x
+
+KBUILD_TOP := drivers/net/wireless/ssv6x5x
+ifeq ($(MAKELEVEL),0)
+KBUILD_TOP := .
+endif
+
+include $(KBUILD_TOP)/$(KMODULE_NAME).cfg
+include $(KBUILD_TOP)/platform-config.mak
+
+# Generate version strings
+# GEN_VER := $(shell cd $(KBUILD_TOP); ./ver_info.pl include/ssv_version.h)
+# Generate include/ssv_conf_parser.h
+# GEN_CONF_PARSER := $(shell cd $(KBUILD_TOP); env ccflags="$(ccflags-y)" ./parser-conf.sh include/ssv_conf_parser.h)
+# Generate $(KMODULE_NAME)-wifi.cfg
+BKP_CFG := $(shell cp $(KBUILD_TOP)/$(KMODULE_NAME)-wifi.cfg $(KBUILD_TOP)/image/$(KMODULE_NAME)-wifi.cfg)
+
+MODDESTDIR = /lib/modules/$(shell uname -r)/kernel/drivers/net/wireless
+
+EXTRA_CFLAGS := -I$(KBUILD_TOP) -I$(KBUILD_TOP)/include
+
+DEF_PARSER_H = $(KBUILD_TOP)/include/ssv_conf_parser.h
+$(shell env ccflags="$(ccflags-y)" $(KBUILD_TOP)/parser-conf.sh $(DEF_PARSER_H))
+
+KERN_SRCS := ssvdevice/ssvdevice.c
+KERN_SRCS += ssvdevice/ssv_cmd.c
+
+KERN_SRCS += hci/ssv_hci.c
+
+KERN_SRCS += smac/init.c
+KERN_SRCS += smac/ssv_skb.c
+KERN_SRCS += smac/dev.c
+KERN_SRCS += smac/ssv_rc_minstrel.c
+KERN_SRCS += smac/ssv_rc_minstrel_ht.c
+KERN_SRCS += smac/ap.c
+KERN_SRCS += smac/ampdu.c
+KERN_SRCS += smac/efuse.c
+KERN_SRCS += smac/ssv_pm.c
+KERN_SRCS += smac/ssv_skb.c
+
+ifeq ($(findstring -DCONFIG_SSV6XXX_DEBUGFS, $(ccflags-y)), -DCONFIG_SSV6XXX_DEBUGFS)
+KERN_SRCS += smac/ssv6xxx_debugfs.c
+endif
+
+ifeq ($(findstring -DUSE_LOCAL_CRYPTO, $(ccflags-y)), -DUSE_LOCAL_CRYPTO)
+KERN_SRCS += smac/sec_ccmp.c
+KERN_SRCS += smac/sec_tkip.c
+KERN_SRCS += smac/sec_wep.c
+KERN_SRCS += smac/wapi_sms4.c
+KERN_SRCS += smac/sec_wpi.c
+endif
+
+
+ifeq ($(findstring -DCONFIG_SMARTLINK, $(ccflags-y)), -DCONFIG_SMARTLINK)
+KERN_SRCS += smac/ksmartlink.c
+endif
+ifeq ($(findstring -DCONFIG_SSV_SMARTLINK, $(ccflags-y)), -DCONFIG_SSV_SMARTLINK)
+KERN_SRCS += smac/kssvsmart.c
+endif
+
+ifeq ($(findstring -DSSV_SUPPORT_HAL, $(ccflags-y)), -DSSV_SUPPORT_HAL)
+KERN_SRCS += smac/hal/hal.c
+
+ifeq ($(findstring -DSSV_SUPPORT_SSV6051, $(ccflags-y)), -DSSV_SUPPORT_SSV6051)
+KERN_SRCS += smac/ssv_rc.c
+KERN_SRCS += smac/ssv_ht_rc.c
+KERN_SRCS += smac/hal/ssv6051/ssv6051_mac.c
+KERN_SRCS += smac/hal/ssv6051/ssv6051_phy.c
+KERN_SRCS += smac/hal/ssv6051/ssv6051_cabrioA.c
+KERN_SRCS += smac/hal/ssv6051/ssv6051_cabrioE.c
+endif
+
+ifeq ($(findstring -DSSV_SUPPORT_SSV6006, $(ccflags-y)), -DSSV_SUPPORT_SSV6006)
+
+KERN_SRCS += hwif/usb/usb.c
+KERN_SRCS += smac/hal/ssv6006c/ssv6006_common.c
+KERN_SRCS += smac/hal/ssv6006c/ssv6006C_mac.c
+KERN_SRCS += smac/hal/ssv6006c/ssv6006_phy.c
+KERN_SRCS += smac/hal/ssv6006c/ssv6006_turismoC.c
+ifeq ($(findstring -DSSV_SUPPORT_SSV6006AB, $(ccflags-y)), -DSSV_SUPPORT_SSV6006AB)
+KERN_SRCS += smac/hal/ssv6006/ssv6006_mac.c
+KERN_SRCS += smac/hal/ssv6006/ssv6006_cabrioA.c
+KERN_SRCS += smac/hal/ssv6006/ssv6006_geminiA.c
+KERN_SRCS += smac/hal/ssv6006/ssv6006_turismoA.c
+KERN_SRCS += smac/hal/ssv6006/ssv6006_turismoB.c
+endif
+endif
+else
+KERN_SRCS += smac/ssv_rc.c
+KERN_SRCS += smac/ssv_ht_rc.c
+endif
+
+KERN_SRCS += hwif/sdio/sdio.c
+
+ifeq ($(findstring -DCONFIG_SSV_SUPPORT_AES_ASM, $(ccflags-y)), -DCONFIG_SSV_SUPPORT_AES_ASM)
+KERN_SRCS += crypto/aes_glue.c
+KERN_SRCS += crypto/sha1_glue.c
+KERN_SRCS_S := crypto/aes-armv4.S
+KERN_SRCS_S += crypto/sha1-armv4-large.S
+endif
+
+KERN_SRCS += $(KMODULE_NAME)-generic-wlan.c
+
+$(KMODULE_NAME)-y += $(KERN_SRCS_S:.S=.o)
+$(KMODULE_NAME)-y += $(KERN_SRCS:.c=.o)
+
+obj-$(CONFIG_SSV6X5X) += $(KMODULE_NAME).o
+
+#export CONFIG_SSV6X5X=m
+
+.PHONY: all ver modules clean
+
+all: modules
+	
+modules:
+	$(MAKE) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) -C $(KSRC) M=$(shell pwd) modules
+
+strip:
+	$(CROSS_COMPILE)strip $(MODULE_NAME).ko --strip-unneeded
+
+install:
+	install -p -m 644 $(KMODULE_NAME).ko  $(MODDESTDIR)
+	/sbin/depmod -a ${KVER}
+
+uninstall:
+	rm -f $(MODDESTDIR)/$(KMODULE_NAME).ko
+	/sbin/depmod -a ${KVER}
+
+clean:
+	rm -fr *.mod.c *.mod *.o .*.cmd *.ko *~
+	rm -fr .tmp_versions
+	rm -fr Module.symvers
+	rm -fr Module.markers
+	rm -fr modules.order
+	rm -fr image/$(KMODULE_NAME)-wifi.cfg
+	cd ssvdevice/; 		rm -fr *.mod.c *.mod *.o .*.cmd *.ko
+	cd hci/; 			rm -fr *.mod.c *.mod *.o .*.cmd *.ko
+	cd smac/; 	rm -fr *.mod.c *.mod *.o .*.cmd *.ko
+	cd hwif/; 			rm -fr *.mod.c *.mod *.o .*.cmd *.ko
+	cd hwif/sdio/; 			rm -fr *.mod.c *.mod *.o .*.cmd *.ko
+	cd crypto/; 		rm -fr *.mod.c *.mod *.o .*.cmd *.ko
+
diff --git a/drivers/net/wireless/ssv6x5x/Makefile.android b/drivers/net/wireless/ssv6x5x/Makefile.android
new file mode 100755
index 000000000..77988a340
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/Makefile.android
@@ -0,0 +1,142 @@
+PLATFORMS =
+
+KBUILD_TOP := $(PWD)
+include $(KBUILD_TOP)/platforms/$(PLATFORMS).cfg
+include $(KBUILD_TOP)/platforms/platform-config.mak
+
+PWD := $(shell pwd)
+
+ifeq ($(KERNELRELEASE),)
+# current directory is driver
+CFGDIR = $(PWD)/../../../../config
+
+-include $(CFGDIR)/build_config.cfg
+-include $(CFGDIR)/rules.make
+
+endif
+
+ifeq ($(findstring -DSSV_SUPPORT_HAL, $(ccflags-y)), -DSSV_SUPPORT_HAL)
+KMODULE_NAME=ssv6xxx
+else
+KMODULE_NAME=ssv6051
+endif
+EXTRA_CFLAGS := -I$(KBUILD_TOP) -I$(KBUILD_TOP)/include
+
+DEF_PARSER_H = $(KBUILD_TOP)/include/ssv_conf_parser.h
+$(shell env ccflags="$(ccflags-y)" $(KBUILD_TOP)/parser-conf.sh $(DEF_PARSER_H))
+
+KERN_SRCS := ssvdevice/ssvdevice.c
+KERN_SRCS += ssvdevice/ssv_cmd.c
+
+KERN_SRCS += hci/ssv_hci.c
+
+KERN_SRCS += smac/init.c
+KERN_SRCS += smac/ssv_skb.c
+KERN_SRCS += smac/dev.c
+KERN_SRCS += smac/ssv_rc_minstrel.c
+KERN_SRCS += smac/ssv_rc_minstrel_ht.c
+KERN_SRCS += smac/ap.c
+KERN_SRCS += smac/ampdu.c
+KERN_SRCS += smac/efuse.c
+KERN_SRCS += smac/ssv_pm.c
+KERN_SRCS += smac/ssv_skb.c
+
+ifeq ($(findstring -DCONFIG_SSV6XXX_DEBUGFS, $(ccflags-y)), -DCONFIG_SSV6XXX_DEBUGFS)
+KERN_SRCS += smac/ssv6xxx_debugfs.c
+endif
+
+ifeq ($(findstring -DUSE_LOCAL_CRYPTO, $(ccflags-y)), -DUSE_LOCAL_CRYPTO)
+KERN_SRCS += smac/sec_ccmp.c
+KERN_SRCS += smac/sec_tkip.c
+KERN_SRCS += smac/sec_wep.c
+KERN_SRCS += smac/wapi_sms4.c
+KERN_SRCS += smac/sec_wpi.c
+endif
+
+
+ifeq ($(findstring -DCONFIG_SMARTLINK, $(ccflags-y)), -DCONFIG_SMARTLINK)
+KERN_SRCS += smac/ksmartlink.c
+endif
+ifeq ($(findstring -DCONFIG_SSV_SMARTLINK, $(ccflags-y)), -DCONFIG_SSV_SMARTLINK)
+KERN_SRCS += smac/kssvsmart.c
+endif
+
+ifeq ($(findstring -DSSV_SUPPORT_HAL, $(ccflags-y)), -DSSV_SUPPORT_HAL)
+KERN_SRCS += smac/hal/hal.c
+
+ifeq ($(findstring -DSSV_SUPPORT_SSV6051, $(ccflags-y)), -DSSV_SUPPORT_SSV6051)
+KERN_SRCS += smac/ssv_rc.c
+KERN_SRCS += smac/ssv_ht_rc.c
+KERN_SRCS += smac/hal/ssv6051/ssv6051_mac.c
+KERN_SRCS += smac/hal/ssv6051/ssv6051_phy.c
+KERN_SRCS += smac/hal/ssv6051/ssv6051_cabrioA.c
+KERN_SRCS += smac/hal/ssv6051/ssv6051_cabrioE.c
+endif
+
+ifeq ($(findstring -DSSV_SUPPORT_SSV6006, $(ccflags-y)), -DSSV_SUPPORT_SSV6006)
+
+KERN_SRCS += hwif/usb/usb.c
+KERN_SRCS += smac/hal/ssv6006c/ssv6006_common.c
+KERN_SRCS += smac/hal/ssv6006c/ssv6006C_mac.c
+KERN_SRCS += smac/hal/ssv6006c/ssv6006_phy.c
+KERN_SRCS += smac/hal/ssv6006c/ssv6006_turismoC.c
+ifeq ($(findstring -DSSV_SUPPORT_SSV6006AB, $(ccflags-y)), -DSSV_SUPPORT_SSV6006AB)
+KERN_SRCS += smac/hal/ssv6006/ssv6006_mac.c
+KERN_SRCS += smac/hal/ssv6006/ssv6006_cabrioA.c
+KERN_SRCS += smac/hal/ssv6006/ssv6006_geminiA.c
+KERN_SRCS += smac/hal/ssv6006/ssv6006_turismoA.c
+KERN_SRCS += smac/hal/ssv6006/ssv6006_turismoB.c
+endif
+endif
+else
+KERN_SRCS += smac/ssv_rc.c
+KERN_SRCS += smac/ssv_ht_rc.c
+endif
+
+KERN_SRCS += hwif/sdio/sdio.c
+#KERNEL_MODULES += crypto
+
+ifeq ($(findstring -DCONFIG_SSV_SUPPORT_AES_ASM, $(ccflags-y)), -DCONFIG_SSV_SUPPORT_AES_ASM)
+KERN_SRCS += crypto/aes_glue.c
+KERN_SRCS += crypto/sha1_glue.c
+KERN_SRCS_S := crypto/aes-armv4.S
+KERN_SRCS_S += crypto/sha1-armv4-large.S
+endif
+
+
+KERN_SRCS += platforms/$(PLATFORMS)-generic-wlan.c
+
+$(KMODULE_NAME)-y += $(KERN_SRCS_S:.S=.o)
+$(KMODULE_NAME)-y += $(KERN_SRCS:.c=.o)
+
+obj-$(CONFIG_SSV6X5X) += $(KMODULE_NAME).o
+
+all:module strip
+
+module:
+	make  -C $(SSV_KERNEL_PATH) ARCH=$(SSV_ARCH) CROSS_COMPILE=$(SSV_CROSS) \
+	EXTRA_CFLAGS="$(EXTRA_CFLAGS)" M=$(PWD) modules
+
+install:
+	install -p -m 644 $(KMODULE_NAME).ko $(KMODDESTDIR)
+
+uninstall:
+	rm -f $(KMODDESTDIR)/$(KMODULE_NAME).ko
+    
+strip:
+	#cp eagle.ko $(KO_NAME).ko
+	#cp $(KO_NAME).ko $(DEFAULT_MODULES_DIR)
+	#cp ssv6200.ko $(DEFAULT_MODULES_DIR)
+	cp platforms/$(PLATFORMS)-wifi.cfg image/$(KMODULE_NAME)-wifi.cfg
+	cp $(KMODULE_NAME).ko image/$(KMODULE_NAME).ko
+	cp platforms/cli image
+ifneq ($(SSV_STRIP),)
+	cp $(KMODULE_NAME).ko image/$(KMODULE_NAME)_ori.ko
+	$(SSV_STRIP) --strip-unneeded image/$(KMODULE_NAME).ko
+	#$(SSV_STRIP) --strip-debug image/$(KMODULE_NAME).ko
+endif
+
+clean:
+	make -C $(SSV_KERNEL_PATH) ARCH=$(SSV_ARCH) CROSS_COMPILE=$(SSV_CROSS) \
+	M=$(PWD) clean
+
diff --git a/drivers/net/wireless/ssv6x5x/Makefile.cross_linux b/drivers/net/wireless/ssv6x5x/Makefile.cross_linux
new file mode 100755
index 000000000..16148bf63
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/Makefile.cross_linux
@@ -0,0 +1,140 @@
+KMODULE_NAME = ssv6x5x
+
+KBUILD_TOP := drivers/net/wireless/ssv6x5x
+ifeq ($(MAKELEVEL),0)
+KBUILD_TOP := .
+endif
+
+include $(KBUILD_TOP)/$(KMODULE_NAME).cfg
+include $(KBUILD_TOP)/platform-config.mak
+
+# Generate version strings
+# GEN_VER := $(shell cd $(KBUILD_TOP); ./ver_info.pl include/ssv_version.h)
+# Generate include/ssv_conf_parser.h
+# GEN_CONF_PARSER := $(shell cd $(KBUILD_TOP); env ccflags="$(ccflags-y)" ./parser-conf.sh include/ssv_conf_parser.h)
+# Generate $(KMODULE_NAME)-wifi.cfg
+BKP_CFG := $(shell cp $(KBUILD_TOP)/$(KMODULE_NAME)-wifi.cfg $(KBUILD_TOP)/image/$(KMODULE_NAME)-wifi.cfg)
+
+EXTRA_CFLAGS := -I$(KBUILD_TOP) -I$(KBUILD_TOP)/include
+
+DEF_PARSER_H = $(KBUILD_TOP)/include/ssv_conf_parser.h
+$(shell env ccflags="$(ccflags-y)" $(KBUILD_TOP)/parser-conf.sh $(DEF_PARSER_H))
+
+KERN_SRCS := ssvdevice/ssvdevice.c
+KERN_SRCS += ssvdevice/ssv_cmd.c
+
+KERN_SRCS += hci/ssv_hci.c
+
+KERN_SRCS += smac/init.c
+KERN_SRCS += smac/ssv_skb.c
+KERN_SRCS += smac/dev.c
+KERN_SRCS += smac/ssv_rc_minstrel.c
+KERN_SRCS += smac/ssv_rc_minstrel_ht.c
+KERN_SRCS += smac/ap.c
+KERN_SRCS += smac/ampdu.c
+KERN_SRCS += smac/efuse.c
+KERN_SRCS += smac/ssv_pm.c
+KERN_SRCS += smac/ssv_skb.c
+
+ifeq ($(findstring -DCONFIG_SSV6XXX_DEBUGFS, $(ccflags-y)), -DCONFIG_SSV6XXX_DEBUGFS)
+KERN_SRCS += smac/ssv6xxx_debugfs.c
+endif
+
+ifeq ($(findstring -DUSE_LOCAL_CRYPTO, $(ccflags-y)), -DUSE_LOCAL_CRYPTO)
+KERN_SRCS += smac/sec_ccmp.c
+KERN_SRCS += smac/sec_tkip.c
+KERN_SRCS += smac/sec_wep.c
+KERN_SRCS += smac/wapi_sms4.c
+KERN_SRCS += smac/sec_wpi.c
+endif
+
+
+ifeq ($(findstring -DCONFIG_SMARTLINK, $(ccflags-y)), -DCONFIG_SMARTLINK)
+KERN_SRCS += smac/ksmartlink.c
+endif
+ifeq ($(findstring -DCONFIG_SSV_SMARTLINK, $(ccflags-y)), -DCONFIG_SSV_SMARTLINK)
+KERN_SRCS += smac/kssvsmart.c
+endif
+
+ifeq ($(findstring -DSSV_SUPPORT_HAL, $(ccflags-y)), -DSSV_SUPPORT_HAL)
+KERN_SRCS += smac/hal/hal.c
+
+ifeq ($(findstring -DSSV_SUPPORT_SSV6051, $(ccflags-y)), -DSSV_SUPPORT_SSV6051)
+KERN_SRCS += smac/ssv_rc.c
+KERN_SRCS += smac/ssv_ht_rc.c
+KERN_SRCS += smac/hal/ssv6051/ssv6051_mac.c
+KERN_SRCS += smac/hal/ssv6051/ssv6051_phy.c
+KERN_SRCS += smac/hal/ssv6051/ssv6051_cabrioA.c
+KERN_SRCS += smac/hal/ssv6051/ssv6051_cabrioE.c
+endif
+
+ifeq ($(findstring -DSSV_SUPPORT_SSV6006, $(ccflags-y)), -DSSV_SUPPORT_SSV6006)
+
+KERN_SRCS += hwif/usb/usb.c
+KERN_SRCS += smac/hal/ssv6006c/ssv6006_common.c
+KERN_SRCS += smac/hal/ssv6006c/ssv6006C_mac.c
+KERN_SRCS += smac/hal/ssv6006c/ssv6006_phy.c
+KERN_SRCS += smac/hal/ssv6006c/ssv6006_turismoC.c
+ifeq ($(findstring -DSSV_SUPPORT_SSV6006AB, $(ccflags-y)), -DSSV_SUPPORT_SSV6006AB)
+KERN_SRCS += smac/hal/ssv6006/ssv6006_mac.c
+KERN_SRCS += smac/hal/ssv6006/ssv6006_cabrioA.c
+KERN_SRCS += smac/hal/ssv6006/ssv6006_geminiA.c
+KERN_SRCS += smac/hal/ssv6006/ssv6006_turismoA.c
+KERN_SRCS += smac/hal/ssv6006/ssv6006_turismoB.c
+endif
+endif
+else
+KERN_SRCS += smac/ssv_rc.c
+KERN_SRCS += smac/ssv_ht_rc.c
+endif
+
+KERN_SRCS += hwif/sdio/sdio.c
+
+ifeq ($(findstring -DCONFIG_SSV_SUPPORT_AES_ASM, $(ccflags-y)), -DCONFIG_SSV_SUPPORT_AES_ASM)
+KERN_SRCS += crypto/aes_glue.c
+KERN_SRCS += crypto/sha1_glue.c
+KERN_SRCS_S := crypto/aes-armv4.S
+KERN_SRCS_S += crypto/sha1-armv4-large.S
+endif
+
+KERN_SRCS += $(KMODULE_NAME)-generic-wlan.c
+
+$(KMODULE_NAME)-y += $(KERN_SRCS_S:.S=.o)
+$(KMODULE_NAME)-y += $(KERN_SRCS:.c=.o)
+
+obj-$(CONFIG_SSV6X5X) += $(KMODULE_NAME).o
+
+#export CONFIG_SSV6X5X=m
+
+.PHONY: all ver modules clean
+
+all: modules
+	
+modules:
+	$(MAKE) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) -C $(KSRC) M=$(shell pwd) modules
+
+strip:
+	$(CROSS_COMPILE)strip $(MODULE_NAME).ko --strip-unneeded
+
+#install:
+#	install -p -m 644 $(MODULE_NAME).ko  $(MODDESTDIR)
+#	/sbin/depmod -a ${KVER}
+#
+#uninstall:
+#	rm -f $(MODDESTDIR)/$(MODULE_NAME).ko
+#	/sbin/depmod -a ${KVER}
+
+clean:
+	rm -fr *.mod.c *.mod *.o .*.cmd *.ko *~
+	rm -fr .tmp_versions
+	rm -fr Module.symvers
+	rm -fr Module.markers
+	rm -fr modules.order
+	rm -fr image/$(KMODULE_NAME)-wifi.cfg
+	cd ssvdevice/; 		rm -fr *.mod.c *.mod *.o .*.cmd *.ko
+	cd hci/; 			rm -fr *.mod.c *.mod *.o .*.cmd *.ko
+	cd smac/; 	rm -fr *.mod.c *.mod *.o .*.cmd *.ko
+	cd hwif/; 			rm -fr *.mod.c *.mod *.o .*.cmd *.ko
+	cd hwif/sdio/; 			rm -fr *.mod.c *.mod *.o .*.cmd *.ko
+	cd crypto/; 		rm -fr *.mod.c *.mod *.o .*.cmd *.ko
+
diff --git a/drivers/net/wireless/ssv6x5x/Makefile.lib.cross_linux b/drivers/net/wireless/ssv6x5x/Makefile.lib.cross_linux
new file mode 100755
index 000000000..e35ffa532
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/Makefile.lib.cross_linux
@@ -0,0 +1,57 @@
+KMODULE_NAME = ssv6x5x
+
+KBUILD_TOP := drivers/net/wireless/ssv6x5x
+ifeq ($(MAKELEVEL),0)
+KBUILD_TOP := .
+endif
+
+include $(KBUILD_TOP)/$(KMODULE_NAME).cfg
+include $(KBUILD_TOP)/platform-config.mak
+
+# Generate version strings
+# GEN_VER := $(shell cd $(KBUILD_TOP); ./ver_info.pl include/ssv_version.h)
+# Generate -wifi.cfg
+BKP_CFG := $(shell cp $(KBUILD_TOP)/$(KMODULE_NAME)-wifi.cfg $(KBUILD_TOP)/image/$(KMODULE_NAME)-wifi.cfg)
+
+EXTRA_CFLAGS := -I$(KBUILD_TOP) -I$(KBUILD_TOP)/include
+
+DEF_PARSER_H = $(KBUILD_TOP)/include/ssv_conf_parser.h
+$(shell touch $(DEF_PARSER_H))
+$(shell env ccflags="$(ccflags-y)" $(KBUILD_TOP)/parser-conf.sh $(DEF_PARSER_H))
+
+obj-$(CONFIG_SSV6XXX) := $(KMODULE_NAME).o
+$(KMODULE_NAME)-objs := $(KMODULE_NAME)-generic-wlan.o lib.a
+
+.PHONY: all modules clean
+
+all: modules
+	
+modules:
+	$(MAKE) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) -C $(KSRC) M=$(shell pwd) modules
+
+strip:
+	$(CROSS_COMPILE)strip $(MODULE_NAME).ko --strip-unneeded
+
+#install:
+#	install -p -m 644 $(MODULE_NAME).ko  $(MODDESTDIR)
+#	/sbin/depmod -a ${KVER}
+#
+#uninstall:
+#	rm -f $(MODDESTDIR)/$(MODULE_NAME).ko
+#	/sbin/depmod -a ${KVER}
+
+clean:
+	rm -fr *.mod.c *.mod *.o .*.cmd *.ko *~
+	rm -fr .tmp_versions
+	rm -fr Module.symvers
+	rm -fr Module.markers
+	rm -fr modules.order
+	rm -fr image/$(KMODULE_NAME)-wifi.cfg
+	cd ssvdevice/; 		rm -fr *.mod.c *.mod *.o .*.cmd *.ko
+	cd hci/; 			rm -fr *.mod.c *.mod *.o .*.cmd *.ko
+	cd smac/; 	rm -fr *.mod.c *.mod *.o .*.cmd *.ko
+	cd hwif/; 			rm -fr *.mod.c *.mod *.o .*.cmd *.ko
+	cd hwif/sdio/; 			rm -fr *.mod.c *.mod *.o .*.cmd *.ko
+	cd crypto/; 		rm -fr *.mod.c *.mod *.o .*.cmd *.ko
+	rm -fr lib.a
+	rm $(DEF_PARSER_H)
diff --git a/drivers/net/wireless/ssv6x5x/README.md b/drivers/net/wireless/ssv6x5x/README.md
new file mode 100644
index 000000000..992cf0101
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/README.md
@@ -0,0 +1,10 @@
+ssv6x5x driver adapter to compile and work in rockchip linux 4.4 kernel, mainly for rk322x SoCs
+
+To compile on the board:
+
+source ./vars
+make -j4
+make install
+
+Otherwise put this in kernel tree in /driver/net/wireless/ssv6x5x, adapt the Kconfig and Makefile
+and then compile the kernel as usual
diff --git a/drivers/net/wireless/ssv6x5x/android-build.sh b/drivers/net/wireless/ssv6x5x/android-build.sh
new file mode 100755
index 000000000..4a8bed51a
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/android-build.sh
@@ -0,0 +1,57 @@
+#!/bin/bash
+prompt="Pick the target platform:"
+chip_options=("a33" \
+              "h8" \
+              "h3" \
+              "rk3036" \              
+              "rk3126" \
+              "rk3128" \
+              "rk322x" \
+              "atm7039-action" \
+              "aml-s905" \
+              "aml-s805" \
+              "x1000" \
+              "t10" \
+              "xml-hi3518")
+PLATFORM=""
+
+select opt in "${chip_options[@]}" "Quit"; do 
+    case "$REPLY" in
+
+    1 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+    2 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+    3 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+    4 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+    5 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+    6 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+    7 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+    8 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+    9 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+    10 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+    11 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+    12 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+    13 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+
+    $(( ${#chip_options[@]}+1 )) ) echo "Goodbye!"; break;;
+    *) echo "Invalid option. Try another one.";continue;;
+    esac
+done
+
+if [ "$PLATFORM" != "" ]; then
+./ver_info.pl include/ssv_version.h
+
+if [ $? -eq 0 ]; then
+    echo "Please check SVN first !!"
+else
+mv Makefile Makefile.org
+cp Makefile.android Makefile
+sed -i 's,PLATFORMS =,PLATFORMS = '"$PLATFORM"',g' Makefile
+make clean
+make
+mv -f Makefile.org Makefile
+echo "Done ko!"
+fi
+else
+echo "Fail!"
+fi
+
diff --git a/drivers/net/wireless/ssv6x5x/ap.cfg b/drivers/net/wireless/ssv6x5x/ap.cfg
new file mode 100755
index 000000000..9901ae0fd
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/ap.cfg
@@ -0,0 +1,52 @@
+ssid=testMssyAP
+channel=40
+
+#5G mode
+hw_mode=a
+ht_capab=[SHORT-GI-20][RX-STBC1][HT40-][SHORT-GI-40]
+#ht_capab=[SHORT-GI-20][RX-STBC1]
+#[40-INTOLERANT]
+
+#DFS
+country_code=US
+ieee80211d=1
+
+#2G mode
+#ht_capab=[SHORT-GI-20][RX-STBC1]
+
+#OPEN
+ieee80211n=1
+
+##WEP
+#wep_default_key=0
+##5 characters
+#wep_key0="aaaaa"
+##13 characters
+##wep_key0="aaaaaaaaaaaaa"
+
+
+##WPA
+#wpa=1
+#wpa_key_mgmt=WPA-PSK
+#rsn_pairwise=TKIP
+#wpa_passphrase=12345678
+
+
+
+##WPA2
+#ieee80211n=1
+#ht_capab=[SHORT-GI-20][RX-STBC1]
+#wpa=2
+#wpa_key_mgmt=WPA-PSK
+#rsn_pairwise=CCMP
+## WPA pre-shared keys for WPA-PSK. This can be either entered as a 256-bit   
+## secret in hex format (64 hex digits), wpa_psk, or as an ASCII passphrase   
+## (8..63 characters) that will be converted to PSK. This conversion uses SSID
+## so the PSK changes when ASCII passphrase is used and the SSID is changed.  
+## wpa_psk (dot11RSNAConfigPSKValue)                                          
+## wpa_passphrase (dot11RSNAConfigPSKPassPhrase)                              
+##wpa_psk=0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef   
+#wpa_passphrase=12345678
+
+
+                                                     
\ No newline at end of file
diff --git a/drivers/net/wireless/ssv6x5x/ap_check.sh b/drivers/net/wireless/ssv6x5x/ap_check.sh
new file mode 100755
index 000000000..a5de18076
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/ap_check.sh
@@ -0,0 +1,97 @@
+#! /bin/bash
+
+
+
+HOSTPAD_DIR=../hostapd/hostapd/
+BLUE='\e[1;34m'
+GREEN='\e[1;32m'
+CYAN='\e[1;36m'
+RED='\e[1;31m'
+PURPLE='\e[1;35m'
+YELLOW='\e[1;33m'
+# No Color
+NC='\e[0m'
+
+
+check_package(){	
+	for i in {1..5}
+	do
+		echo -en "${GREEN}Check package - $1...${NC}"
+		status=$(dpkg -s $1 | grep "Status: install ok installed")
+		if [ "$status" == "" ]; then
+				echo -e "${PURPLE}Try to intall package $1...${NC}"
+				apt-get install -y $1
+				retval=2
+		else
+				echo -e "${GREEN}OK${NC}"
+				retval=1
+				break;
+		fi
+	done
+	return "$retval"		
+}
+
+check_dhcp_server_config(){
+
+	dhcp_config_file="/etc/dhcp/dhcpd.conf"
+	echo -en "${YELLOW}Check DHCPD config...${NC}"
+	dhcp_config=$(grep "subnet 192.168.0.0 netmask 255.255.255.0" $dhcp_config_file)
+
+	if [ "$dhcp_config" == "" ]; then
+		echo -en "${YELLOW}Config $dhcp_config_file.....${NC}"
+		echo "subnet 192.168.0.0 netmask 255.255.255.0" >> $dhcp_config_file
+		echo "{" >> $dhcp_config_file
+		echo "	range 192.168.0.2 192.168.0.10;" >> $dhcp_config_file
+		echo "	option routers 192.168.0.1;" >> $dhcp_config_file
+		echo "	option domain-name-servers 168.95.1.1;" >> $dhcp_config_file
+		echo "}" >> $dhcp_config_file
+		
+		echo -e "${YELLOW}OK${NC}"
+	else
+		echo -e "${YELLOW}OK${NC}"
+	fi
+}
+
+
+
+
+check()
+{
+	check_package $1
+	ret=$? 
+	if test $ret -eq 2 
+	then
+		echo -e "${RED}#############FAIL to CHECK PACKAGE for AP MODE#############${NC}"
+		exit 0;
+	fi
+}
+
+#############################################==MAIN==#############################################
+#
+if [ ! -d "$HOSTPAD_DIR" ]; then
+  echo -e "${RED}#############HOSTPAD needs to be put at the same level of the wireless driver#############${NC}"
+  exit 0;
+fi
+
+
+#
+echo -e "${YELLOW}Check internet access...${NC}"
+wget --spider http://www.google.com
+
+if [ "$?" != 0 ]; then
+  	echo -e "${RED}Please connect to internet firstly......${NC}"
+  	exit 0;
+fi
+
+#
+echo -e "${YELLOW}Check necessary packages to run AP mode${NC}"
+check libnl1
+check libnl-dev
+check libssl-dev
+check isc-dhcp-server
+check_dhcp_server_config
+
+#
+cd $HOSTPAD_DIR
+make
+
diff --git a/drivers/net/wireless/ssv6x5x/ap_launch.sh b/drivers/net/wireless/ssv6x5x/ap_launch.sh
new file mode 100755
index 000000000..a34897c90
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/ap_launch.sh
@@ -0,0 +1,124 @@
+#! /bin/bash
+
+BLUE='\e[1;34m'
+GREEN='\e[1;32m'
+CYAN='\e[1;36m'
+RED='\e[1;31m'
+PURPLE='\e[1;35m'
+YELLOW='\e[1;33m'
+# No Color
+NC='\e[0m'
+
+
+HOSTPAD_DIR=../hostapd/hostapd
+
+./ap_shutdown.sh
+
+dir=$(pwd)
+chmod 777 -R $HOSTPAD_DIR
+cd $HOSTPAD_DIR
+
+PID=$!
+wait $PID
+sleep 2
+
+
+cd $dir
+echo -e "${YELLOW}Load wireless driver...${NC}"
+./load.sh
+PID=$!
+wait $PID
+
+echo -e "${YELLOW}Detect wireless device...${NC}"
+sleep 2
+#get driver mac address
+macAddr=$(cat sta.cfg| grep "hw_mac"|sed 1q |tr -d ' '|tail -c 18)
+echo "device macaddr=[$macAddr]" 
+
+#get driver name(wlan??)
+#devName=$(ifconfig | grep $macAddr)
+devName=$(ifconfig -a | grep -i $macAddr)
+devName=`echo $devName| cut -d ' ' -f 1`
+
+ifconfig $devName > /dev/null
+
+if [ $? -ne 0 ]; then
+    echo -e "${RED}Device $devName does not exist.${NC}"
+    exit 1;
+else
+    echo -e "${YELLOW}Device is $devName.${NC}"
+fi
+
+echo -e "${YELLOW}Config wireless AP...${NC}"
+#rm -rf load_dhcp.sh
+#rm -rf hostapd.conf
+#relpace wlan@@ to real device name
+cp script/template/load_dhcp.sh load_dhcp.sh
+#cp script/template/hostapd.conf hostapd.conf
+awk 'NF' script/template/hostapd.conf | grep -v '#' > hostapd.conf
+awk 'NF' ap.cfg | grep -v '#' >> hostapd.conf
+
+sed -i "s/wlan@@/$devName/" load_dhcp.sh
+sed -i "s/wlan@@/$devName/" hostapd.conf
+
+chmod 777 load_dhcp.sh
+
+#move to right position
+#mv load_dhcp.sh $HOSTPAD_DIR
+#mv hostapd.conf $HOSTPAD_DIR/hostapd/
+
+dhcp_config_file="/etc/default/isc-dhcp-server"
+dhcp_config=$(grep "$devName" $dhcp_config_file)
+if [ "$dhcp_config" != "$devName" ]; then
+	echo -en "${YELLOW}Config $dhcp_config_file.....${NC}"
+	
+	rm -rf tmp
+	sed '/INTERFACE/d' /etc/default/isc-dhcp-server >>tmp
+	echo "INTERFACES=\"$devName\"" >>tmp	
+	rm -rf $dhcp_config_file	
+	mv tmp /etc/default/isc-dhcp-server
+	
+	echo -e "${YELLOW}OK${NC}"
+fi
+	
+	
+dir=$(pwd)
+echo -e "${YELLOW}Wireless Done. ${NC}"
+trap handle_stop INT
+
+function version_great() { test "$(printf '%s\n' "$@" | sort -V | head -n 1)" != "$1"; }
+nmcli_version=$(nmcli -v | cut -d ' ' -f 4)
+chk_nmcli_version=0.9.8.999
+
+function handle_stop() {
+#    popd
+    if version_great $nmcli_version $chk_nmcli_version; then
+        nmcli radio wifi on
+    else
+        nmcli nm wifi on
+    fi
+    
+    echo -e "${YELLOW}Shutting down AP.${NC}"
+    ./ap_shutdown.sh
+}
+        
+if version_great $nmcli_version $chk_nmcli_version; then
+    nmcli radio wifi off
+else
+    nmcli nm wifi off
+fi
+
+sudo rfkill unblock wlan
+
+#pushd $HOSTPAD_DIR
+#. ./load_ap.sh
+#$HOSTPAD_DIR/load_dhcp.sh &
+./load_dhcp.sh &
+PID=$!
+wait $PID
+
+echo -e "${YELLOW}Load AP...${NC}"
+echo -e "${GREEN}Launch hostapd.${NC}"
+#run hostapd2.0
+$HOSTPAD_DIR/hostapd -t hostapd.conf
+#hostapd -t hostapd.conf
diff --git a/drivers/net/wireless/ssv6x5x/ap_shutdown.sh b/drivers/net/wireless/ssv6x5x/ap_shutdown.sh
new file mode 100755
index 000000000..376f45f91
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/ap_shutdown.sh
@@ -0,0 +1,17 @@
+#! /bin/bash
+
+echo "@@Unload hostapd..."
+dir=$(pwd)
+
+HOSTPAD_DIR=../hostapd
+
+$HOSTPAD_DIR/unload_ap.sh
+
+echo "@@Unload wireless driver..."
+sleep 1
+
+./unload.sh
+
+
+
+
diff --git a/drivers/net/wireless/ssv6x5x/bridge/Kconfig b/drivers/net/wireless/ssv6x5x/bridge/Kconfig
new file mode 100755
index 000000000..f685f75e9
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/bridge/Kconfig
@@ -0,0 +1,17 @@
+config SSV_SDIO_BRIDGE_HW
+	tristate
+	default m
+	depends on MMC
+	---help---
+	  This option enables the SDIO bus support in ssvcabrio.
+
+	  Say Y, if you have a ssv SDIO device.
+
+config SSV_SDIO_BRIDGE_DEBUGFS
+	bool "SSV ssvsdiobridge debugging"
+	depends on DEBUG_FS
+	---help---
+	  Say Y, if you need access to ssvsdiobridge's statistics.
+
+	  Also required for changing debug message flags at run time.
+
diff --git a/drivers/net/wireless/ssv6x5x/bridge/Makefile b/drivers/net/wireless/ssv6x5x/bridge/Makefile
new file mode 100755
index 000000000..e6d3026aa
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/bridge/Makefile
@@ -0,0 +1,22 @@
+ifeq ($(KBUILD_TOP),)
+    ifneq ($(KBUILD_EXTMOD),)
+    KBUILD_DIR := $(KBUILD_EXTMOD)
+    else
+    KBUILD_DIR := $(PWD)
+    endif
+KBUILD_TOP := $(KBUILD_DIR)/../
+endif
+
+include $(KBUILD_TOP)/config.mak
+
+KBUILD_EXTRA_SYMBOLS += $(KBUILD_TOP)/ssvdevice/Module.symvers
+
+#Define CONFIG_CABRIO_DEBUG to show debug messages
+ccflags-y += -DCONFIG_CABRIO_DEBUG
+
+KMODULE_NAME=ssv6200_sdiobridge
+KERN_SRCS := sdiobridge.c
+KERN_SRCS += debug.c
+
+
+include $(KBUILD_TOP)/rules.mak
diff --git a/drivers/net/wireless/ssv6x5x/bridge/aaa.mk b/drivers/net/wireless/ssv6x5x/bridge/aaa.mk
new file mode 100755
index 000000000..0284a5148
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/bridge/aaa.mk
@@ -0,0 +1,27 @@
+#aaa.mk - what is this used for?
+
+obj-m     += ssvsdiobridge.o
+
+ssvsdiobridge-y +=	sdiobridge.o
+ssvsdiobridge-y +=	debug.o
+
+
+
+#Define CONFIG_CABRIO_DEBUG to show debug messages
+ccflags-y += -DCONFIG_CABRIO_DEBUG
+
+ifndef ($(KBUILD_EXTMOD),)
+KDIR=/lib/modules/`uname -r`/build
+
+_all:
+	$(MAKE) -C $(KDIR) M=$(PWD) KBUILD_EXTRA_SYMBOLS=$(PWD)/../ssvdevice/Module.symvers modules 2>&1 | tee make.log
+clean:
+	$(MAKE) -C $(KDIR) M=$(PWD) clean
+	rm -f make.log
+	
+install:
+	@-rmmod ssvsdiobridge
+	$(MAKE) INSTALL_MOD_DIR=kernel/drivers/net/wireless/ssv6200 -C $(KDIR) M=$(PWD) modules_install
+	modprobe ssvsdiobridge
+
+endif
diff --git a/drivers/net/wireless/ssv6x5x/bridge/debug.c b/drivers/net/wireless/ssv6x5x/bridge/debug.c
new file mode 100644
index 000000000..3f3b95507
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/bridge/debug.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/slab.h>
+#include <linux/vmalloc.h>
+#include <linux/export.h>
+#include <asm/unaligned.h>
+#include "debug.h"
+int ssv_sdiobridge_init_debug(struct ssv_sdiobridge_glue *glue)
+{
+    glue->debugfs = debugfs_create_dir("tu_ssv",
+                                       NULL);
+    if (!glue->debugfs)
+        return -ENOMEM;
+    glue->dump_entry = debugfs_create_bool("sdiobridge_dump", S_IRUSR, glue->debugfs, &glue->dump);
+    return 0;
+}
+void ssv_sdiobridge_deinit_debug(struct ssv_sdiobridge_glue *glue)
+{
+    if (!glue->dump_entry)
+        debugfs_remove(glue->dump_entry);
+}
diff --git a/drivers/net/wireless/ssv6x5x/bridge/debug.h b/drivers/net/wireless/ssv6x5x/bridge/debug.h
new file mode 100644
index 000000000..9c1b2badd
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/bridge/debug.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef DEBUG_H
+#define DEBUG_H
+#include "sdiobridge.h"
+#include <linux/debugfs.h>
+int ssv_sdiobridge_init_debug(struct ssv_sdiobridge_glue *glue);
+void ssv_sdiobridge_deinit_debug(struct ssv_sdiobridge_glue *glue);
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/bridge/make.log b/drivers/net/wireless/ssv6x5x/bridge/make.log
new file mode 100755
index 000000000..acdaa681e
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/bridge/make.log
@@ -0,0 +1,7 @@
+make[1]: Entering directory `/usr/src/linux-headers-3.2.0-48-generic'
+  CC [M]  /root/felix/1015-Release/final/host_drivers/Linux/ssv/bridge/sdiobridge.o
+/root/felix/1015-Release/final/host_drivers/Linux/ssv/bridge/sdiobridge.c:44:33: fatal error: ../include/sdio_def.h: No such file or directory
+compilation terminated.
+make[2]: *** [/root/felix/1015-Release/final/host_drivers/Linux/ssv/bridge/sdiobridge.o] Error 1
+make[1]: *** [_module_/root/felix/1015-Release/final/host_drivers/Linux/ssv/bridge] Error 2
+make[1]: Leaving directory `/usr/src/linux-headers-3.2.0-48-generic'
diff --git a/drivers/net/wireless/ssv6x5x/bridge/sdiobridge.c b/drivers/net/wireless/ssv6x5x/bridge/sdiobridge.c
new file mode 100644
index 000000000..937699541
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/bridge/sdiobridge.c
@@ -0,0 +1,982 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/irq.h>
+#include <linux/module.h>
+#include <linux/vmalloc.h>
+#include <linux/platform_device.h>
+#include <linux/mmc/core.h>
+#include <linux/mmc/sdio.h>
+#include <linux/mmc/sdio_func.h>
+#include <linux/mmc/sdio_ids.h>
+#include <linux/mmc/card.h>
+#include <linux/mmc/host.h>
+#include <linux/gpio.h>
+#include <linux/pm_runtime.h>
+#include <linux/printk.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/fs.h>
+#include <linux/cdev.h>
+#include <linux/slab.h>
+#include <asm/uaccess.h>
+#include <linux/version.h>
+#include <hwif/sdio/sdio_def.h>
+#include "sdiobridge.h"
+#include "debug.h"
+#define BLOCKSIZE 0x40
+#define RXBUFLENGTH 1024*3
+#define RXBUFSIZE 512
+enum ssvcabrio_int {
+    SSVCABRIO_INT_RX = 0x00000001,
+    SSVCABRIO_INT_TX = 0x00000002,
+    SSVCABRIO_INT_GPIO = 0x00000004,
+    SSVCABRIO_INT_SYS = 0x00000008,
+};
+#define CHECK_RET(_fun) \
+ do { \
+  if (0 != _fun) \
+   printk("File = %s\nLine = %d\nFunc=%s\nDate=%s\nTime=%s\n", __FILE__, __LINE__, __FUNCTION__, __DATE__, __TIME__); \
+ } while (0)
+static unsigned int ssv_sdiobridge_ioctl_major = 0;
+static unsigned int num_of_dev = 1;
+static struct cdev ssv_sdiobridge_ioctl_cdev;
+static struct class *fc;
+static struct ssv_sdiobridge_glue *glue;
+struct ssv_rxbuf {
+    struct list_head list;
+    u32 rxsize;
+    u8 rxdata[RXBUFLENGTH];
+};
+static const struct sdio_device_id ssv_sdiobridge_devices[] = {
+    {SDIO_DEVICE(MANUFACTURER_SSV_CODE, (MANUFACTURER_ID_CABRIO_BASE | 0x0))},
+    {}
+};
+MODULE_DEVICE_TABLE(sdio, ssv_sdiobridge_devices);
+static long ssv_sdiobridge_ioctl_getFuncfocus(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+{
+    long retval =0;
+    if ( pcmd_data->out_data_len < 1) {
+        retval = -1;
+    } else {
+        u8 out_data = glue->funcFocus;
+        if ( isCompat ) {
+            CHECK_RET(copy_to_user((int __user *)compat_ptr((unsigned long)pucmd_data->out_data),&out_data,sizeof(out_data)));
+        } else {
+            CHECK_RET(copy_to_user((int __user *)pucmd_data->out_data, &out_data, sizeof(out_data)));
+        }
+    }
+    return retval;
+}
+static long ssv_sdiobridge_ioctl_setFuncfocus(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+{
+    int retval =0;
+    if ( pcmd_data->out_data_len < 0) {
+        retval = -EFAULT;
+        dev_err(glue->dev, "%s : input length must < 0",__FUNCTION__);
+    } else {
+        if ( isCompat ) {
+            CHECK_RET(copy_from_user(&glue->funcFocus,(int __user *)compat_ptr((unsigned long)pcmd_data->in_data),sizeof(glue->funcFocus)));
+        } else {
+            CHECK_RET(copy_from_user(&glue->funcFocus,(int __user *)pcmd_data->in_data,sizeof(glue->funcFocus)));
+        }
+    }
+    return retval;
+}
+static long ssv_sdiobridge_ioctl_getBusWidth(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+{
+    struct sdio_func *func = dev_to_sdio_func(glue->dev);
+    long retval =0;
+    if ( pcmd_data->out_data_len < 1) {
+        retval = -1;
+    } else {
+        u8 out_data = 1;
+        if ( func->card->host->ios.bus_width != MMC_BUS_WIDTH_1 ) {
+            out_data = 4;
+        }
+        if ( isCompat ) {
+            CHECK_RET(copy_to_user((int __user *)compat_ptr((unsigned long)pucmd_data->out_data),&out_data,sizeof(out_data)));
+        } else {
+            CHECK_RET(copy_to_user((int __user *)pucmd_data->out_data,&out_data,sizeof(out_data)));
+        }
+    }
+    return retval;
+}
+#if 0
+static long ssv_sdiobridge_ioctl_setBusWidth(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+{
+    struct sdio_func *func = dev_to_sdio_func(glue->dev);
+    int retval =0;
+    struct ssv_sdiobridge_cmd *pData;
+    u8 inData[1];
+    copy_from_user(pData,(int __user *)arg,sizeof(*pData));
+    if ( isCompat ) {
+        copy_from_user(&cmd_data,(int __user *)compat_ptr((unsigned long)pucmd_data),sizeof(*pucmd_data));
+    } else {
+        copy_from_user(&cmd_data,(int __user *)pucmd_data,sizeof(*pucmd_data));
+    }
+    if ( pData->in_data_len < 0) {
+        retval = -EFAULT;
+        dev_err(glue->dev, "%s : input length must > 1",__FUNCTION__);
+    } else {
+        if ( pData->in_data == 1 ) {
+            if ( (func->card->host->caps & MMC_CAP_4_BIT_DATA) && !(func->card->cccr.low_speed && !func->card->cccr.wide_bus) ) {
+                u8 ctrl = sdio_f0_readb(func,SDIO_CCCR_IF,&retval);
+                if (retval)
+                    return retval;
+                if (!(ctrl & SDIO_BUS_WIDTH_4BIT))
+                    return 0;
+                ctrl &= ~SDIO_BUS_WIDTH_4BIT;
+                ctrl |= SDIO_BUS_ASYNC_INT;
+                sdio_f0_writeb(func,ctrl,SDIO_CCCR_IF,&retval);
+                if (retval)
+                    return retval;
+                mmc_set_bus_width(func->card->host, MMC_BUS_WIDTH_1);
+            }
+        } else {
+            if ( func->card->host->ios.bus_width != MMC_BUS_WIDTH_4 ) {
+            }
+        }
+    }
+    return retval;
+}
+static long ssv_sdiobridge_ioctl_getBlockMode(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+{
+    long retval =0;
+    if ( pcmd_data->out_data_len < 1) {
+        retval = -1;
+    } else {
+        if ( isCompat ) {
+            copy_to_user((int __user *)compat_ptr((unsigned long)pucmd_data->out_data),&out_data,sizeof(out_data));
+        } else {
+            copy_to_user((int __user *)pucmd_data->out_data,&out_data,sizeof(out_data));
+        }
+    }
+    return retval;
+}
+static long ssv_sdiobridge_ioctl_setBlockMode(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+{
+    long retval =0;
+    if ( pcmd_data->in_data_len < 1) {
+        retval = -1;
+    } else {
+        if ( isCompat ) {
+            copy_from_user(&glue->blockMode,(int __user *)pucmd_data->in_data,sizeof(glue->blockMode));
+        }
+    }
+    return retval;
+}
+#endif
+static long ssv_sdiobridge_ioctl_getBlockSize(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+{
+    long retval =0;
+    if ( pcmd_data->out_data_len < 2) {
+        retval = -1;
+    } else {
+        if ( isCompat ) {
+            CHECK_RET(copy_to_user((int __user *)compat_ptr((unsigned long)pucmd_data->out_data),&glue->blockSize,sizeof(glue->blockSize)));
+        } else {
+            CHECK_RET(copy_to_user((int __user *)pucmd_data->out_data,&glue->blockSize,sizeof(glue->blockSize)));
+        }
+    }
+    return retval;
+}
+static long ssv_sdiobridge_ioctl_setBlockSize(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+{
+    struct sdio_func *func = dev_to_sdio_func(glue->dev);
+    long retval =0;
+    if ( pcmd_data->in_data_len < 2) {
+        retval = -1;
+    } else {
+        if ( isCompat ) {
+            CHECK_RET(copy_from_user(&glue->blockSize,(int __user *)compat_ptr((unsigned long)pucmd_data->in_data),sizeof(glue->blockSize)));
+        } else {
+            CHECK_RET(copy_from_user(&glue->blockSize,(int __user *)pucmd_data->in_data,sizeof(glue->blockSize)));
+        }
+        dev_err(glue->dev,"%s: blockSize [%d]\n",__FUNCTION__,glue->blockSize);
+        sdio_claim_host(func);
+        sdio_set_block_size(func,glue->blockSize);
+        sdio_release_host(func);
+    }
+    return retval;
+}
+static long ssv_sdiobridge_ioctl_readByte(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+{
+    struct sdio_func *func = dev_to_sdio_func(glue->dev);
+    long retval =0;
+    if ( pcmd_data->out_data_len < 4) {
+        retval = -1;
+    } else {
+        u32 address;
+        u8 out_data;
+        int ret = 0;
+        if ( isCompat ) {
+            CHECK_RET(copy_from_user(&address,(int __user *)compat_ptr((unsigned long)pucmd_data->in_data),sizeof(address)));
+        } else {
+            CHECK_RET(copy_from_user(&address,(int __user *)pucmd_data->in_data,sizeof(address)));
+        }
+        sdio_claim_host(func);
+        if ( glue->funcFocus == 0 ) {
+            out_data = sdio_f0_readb(func, address, &ret);
+        } else {
+            out_data = sdio_readb(func, address, &ret);
+        }
+        sdio_release_host(func);
+        dev_err(glue->dev,"%s: [%X] [%02X] ret:[%d]\n",__FUNCTION__,address,out_data,ret);
+        if ( !ret ) {
+            if ( isCompat ) {
+                CHECK_RET(copy_to_user((void *)compat_ptr((unsigned long)pucmd_data->out_data),&out_data,sizeof(out_data)));
+            } else {
+                CHECK_RET(copy_to_user((int __user *)pucmd_data->out_data,&out_data,sizeof(out_data)));
+            }
+        } else {
+            dev_err(glue->dev,"%s: error : %d",__FUNCTION__,ret);
+            retval = -1;
+        }
+    }
+    return retval;
+}
+static long ssv_sdiobridge_ioctl_writeByte(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+{
+    struct sdio_func *func = dev_to_sdio_func(glue->dev);
+    long retval =0;
+    if ( pcmd_data->in_data_len < 5) {
+        retval = -1;
+    } else {
+        u8 tmp[5];
+        u32 address;
+        u8 data;
+        int ret = 0;
+        if ( isCompat ) {
+            CHECK_RET(copy_from_user(tmp,(int __user *)compat_ptr((unsigned long)pucmd_data->in_data),sizeof(tmp)));
+        } else {
+            CHECK_RET(copy_from_user(tmp,(int __user *)pucmd_data->in_data,sizeof(tmp)));
+        }
+        address = *((u32 *)tmp);
+        data = tmp[4];
+        sdio_claim_host(func);
+        if ( glue->funcFocus == 0 ) {
+            sdio_f0_writeb(func,data, address, &ret);
+        } else {
+            sdio_writeb(func,data, address, &ret);
+        }
+        sdio_release_host(func);
+        if ( ret ) {
+            dev_err(glue->dev,"%s: error : %d",__FUNCTION__,ret);
+            retval = -1;
+        }
+    }
+    return retval;
+}
+static long ssv_sdiobridge_ioctl_getMultiByteIOPort(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+{
+    long retval =0;
+    if ( pcmd_data->out_data_len < 4) {
+        retval = -1;
+    } else {
+        if ( isCompat ) {
+            CHECK_RET(copy_to_user((int __user *)compat_ptr((unsigned long)pucmd_data->out_data),&glue->dataIOPort,sizeof(glue->dataIOPort)));
+        } else {
+            CHECK_RET(copy_to_user((int __user *)pucmd_data->out_data,&glue->dataIOPort,sizeof(glue->dataIOPort)));
+        }
+    }
+    return retval;
+}
+static long ssv_sdiobridge_ioctl_setMultiByteIOPort(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+{
+    long retval =0;
+    if ( pcmd_data->in_data_len < 4) {
+        retval = -1;
+    } else {
+        if ( isCompat ) {
+            CHECK_RET(copy_from_user(&glue->dataIOPort,(int __user *)compat_ptr((unsigned long)pucmd_data->in_data),sizeof(glue->dataIOPort)));
+        } else {
+            CHECK_RET(copy_from_user(&glue->dataIOPort,(int __user *)pucmd_data->in_data,sizeof(glue->dataIOPort)));
+        }
+    }
+    return retval;
+}
+static long ssv_sdiobridge_ioctl_readMultiByte(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+{
+    struct sdio_func *func = dev_to_sdio_func(glue->dev);
+    long retval =0;
+    u8 *tmpdata;
+    int ret;
+    int readsize;
+    tmpdata = kzalloc(pcmd_data->out_data_len, GFP_KERNEL);
+    if ( tmpdata == NULL ) {
+        dev_err(glue->dev,"%s: error : alloc buf error size:%d",__FUNCTION__,pcmd_data->out_data_len);
+        return -1;
+    }
+    readsize = sdio_align_size(func,pcmd_data->out_data_len);
+    sdio_claim_host(func);
+    ret = sdio_memcpy_fromio(func, tmpdata,glue->dataIOPort, readsize );
+    sdio_release_host(func);
+    if (unlikely(glue->dump)) {
+        printk(KERN_DEBUG "%s: READ data address[%08x] len[%d] readsize[%d]\n",__FUNCTION__,glue->dataIOPort,(int)pcmd_data->out_data_len,readsize);
+        print_hex_dump(KERN_DEBUG, "ssv_sdio: READ ",
+                       DUMP_PREFIX_OFFSET, 16, 1,
+                       tmpdata, pcmd_data->out_data_len, false);
+    }
+    if ( !ret ) {
+        if ( isCompat ) {
+            CHECK_RET(copy_to_user((int __user *)compat_ptr((unsigned long)pucmd_data->out_data),tmpdata,pcmd_data->out_data_len));
+        } else {
+            CHECK_RET(copy_to_user((int __user *)pucmd_data->out_data,tmpdata,pcmd_data->out_data_len));
+        }
+    } else {
+        dev_err(glue->dev,"%s: error : %d",__FUNCTION__,ret);
+        retval = -1;
+    }
+    kfree(tmpdata);
+    dev_err(glue->dev,"%s(): %d\n", __FUNCTION__, ret);
+    return retval;
+}
+static long ssv_sdiobridge_ioctl_writeMultiByte(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+{
+    struct sdio_func *func = dev_to_sdio_func(glue->dev);
+    long retval =0;
+    u8 *tmpdata;
+    int ret;
+    int readsize ;
+    tmpdata = kzalloc(pcmd_data->in_data_len, GFP_KERNEL);
+    if ( tmpdata == NULL ) {
+        dev_err(glue->dev,"%s: error : alloc buf error size:%d",__FUNCTION__,pcmd_data->out_data_len);
+        return -1;
+    }
+    if ( isCompat ) {
+        CHECK_RET(copy_from_user(tmpdata,(int __user *)compat_ptr((unsigned long)pucmd_data->in_data),pcmd_data->in_data_len));
+    } else {
+        CHECK_RET(copy_from_user(tmpdata,(int __user *)pucmd_data->in_data,pcmd_data->in_data_len));
+    }
+    readsize = sdio_align_size(func,pcmd_data->in_data_len);
+    if (unlikely(glue->dump)) {
+        printk(KERN_DEBUG "%s: READ data address[%08x] len[%d] readsize[%d]\n",__FUNCTION__,glue->dataIOPort,(int)pcmd_data->in_data_len,readsize);
+        print_hex_dump(KERN_DEBUG, "ssv_sdio: WRITE ",
+                       DUMP_PREFIX_OFFSET, 16, 1,
+                       tmpdata, pcmd_data->in_data_len, false);
+    }
+    sdio_claim_host(func);
+    ret = sdio_memcpy_toio(func, glue->dataIOPort,tmpdata, readsize);
+    sdio_release_host(func);
+    if ( ret ) {
+        dev_err(glue->dev,"%s: error : %d",__FUNCTION__,ret);
+        retval = -1;
+    }
+    kfree(tmpdata);
+    return retval;
+}
+static long ssv_sdiobridge_ioctl_getMultiByteRegIOPort(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+{
+    long retval =0;
+    if ( pcmd_data->out_data_len < 4) {
+        retval = -1;
+    } else {
+        if ( isCompat ) {
+            CHECK_RET(copy_to_user((int __user *)compat_ptr((unsigned long)pucmd_data->out_data),&glue->regIOPort,sizeof(glue->regIOPort)));
+        } else {
+            CHECK_RET(copy_to_user((int __user *)pucmd_data->out_data,&glue->regIOPort,sizeof(glue->regIOPort)));
+        }
+    }
+    return retval;
+}
+static long ssv_sdiobridge_ioctl_setMultiByteRegIOPort(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+{
+    long retval =0;
+    if ( pcmd_data->in_data_len < 4) {
+        retval = -1;
+    } else {
+        if ( isCompat ) {
+            CHECK_RET(copy_from_user(&glue->regIOPort,(int __user *)compat_ptr((unsigned long)pucmd_data->in_data),sizeof(glue->regIOPort)));
+        } else {
+            CHECK_RET(copy_from_user(&glue->regIOPort,(int __user *)pucmd_data->in_data,sizeof(glue->regIOPort)));
+        }
+    }
+    return retval;
+}
+static long ssv_sdiobridge_ioctl_readReg(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+{
+    struct sdio_func *func = dev_to_sdio_func(glue->dev);
+    long retval =0;
+    if ( pcmd_data->in_data_len < 4 || pcmd_data->out_data_len < 4) {
+        retval = -1;
+    } else {
+        u8 tmpdata[4];
+        int ret = 0;
+        if ( isCompat ) {
+            CHECK_RET(copy_from_user(tmpdata,(int __user *)compat_ptr((unsigned long)pucmd_data->in_data),sizeof(tmpdata)));
+        } else {
+            CHECK_RET(copy_from_user(tmpdata,(int __user *)pucmd_data->in_data,sizeof(tmpdata)));
+        }
+        sdio_claim_host(func);
+        dev_err(glue->dev,"%s: read reg 1 [%02X][%02X][%02X][%02X]\n",__FUNCTION__,tmpdata[0],tmpdata[1],tmpdata[2],tmpdata[3]);
+        ret = sdio_memcpy_toio(func, glue->regIOPort, tmpdata, 4);
+        ret = sdio_memcpy_fromio(func, tmpdata, glue->regIOPort, 4);
+        sdio_release_host(func);
+        dev_err(glue->dev,"%s: read reg 2 [%02X][%02X][%02X][%02X] ret:%d\n",__FUNCTION__,tmpdata[0],tmpdata[1],tmpdata[2],tmpdata[3],ret);
+        if ( !ret ) {
+            if ( isCompat ) {
+                CHECK_RET(copy_to_user((int __user *)compat_ptr((unsigned long)pucmd_data->out_data),tmpdata,sizeof(tmpdata)));
+            } else {
+                CHECK_RET(copy_to_user((int __user *)pucmd_data->out_data,tmpdata,sizeof(tmpdata)));
+            }
+        } else {
+            dev_err(glue->dev,"%s: error : %d",__FUNCTION__,ret);
+            retval = -1;
+        }
+    }
+    return retval;
+}
+static long ssv_sdiobridge_ioctl_writeReg(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+{
+    struct sdio_func *func = dev_to_sdio_func(glue->dev);
+    long retval =0;
+    if ( pcmd_data->in_data_len < 8) {
+        retval = -1;
+    } else {
+        u8 tmpdata[8];
+        int ret = 0;
+        if ( isCompat ) {
+            CHECK_RET(copy_from_user(tmpdata,(int __user *)compat_ptr((unsigned long)pucmd_data->in_data),sizeof(tmpdata)));
+        } else {
+            CHECK_RET(copy_from_user(tmpdata,(int __user *)pucmd_data->in_data,sizeof(tmpdata)));
+        }
+        dev_err(glue->dev,"%s: write reg ADR[%02X%02X%02X%02X] [%02X][%02X][%02X][%02X]\n",__FUNCTION__,tmpdata[3],tmpdata[2],tmpdata[1],tmpdata[0],
+                tmpdata[7], tmpdata[6], tmpdata[5], tmpdata[4]);
+        sdio_claim_host(func);
+        ret = sdio_memcpy_toio(func, glue->regIOPort, tmpdata, 8);
+        sdio_release_host(func);
+        if ( ret ) {
+            dev_err(glue->dev,"%s: error : %d",__FUNCTION__,ret);
+            retval = -1;
+        }
+    }
+    return retval;
+}
+static int ssv_sdiobridge_device_open(struct inode *inode, struct file *filp)
+{
+    dev_err(glue->dev,"%s():\n", __FUNCTION__);
+    filp->private_data = glue;
+    return 0;
+}
+static int ssv_sdiobridge_device_close(struct inode *inode, struct file *filp)
+{
+    dev_err(glue->dev,"%s():\n", __FUNCTION__);
+    return 0;
+}
+static long ssv_sdiobridge_device_ioctl_process(struct ssv_sdiobridge_glue *glue, unsigned int cmd, struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+{
+    struct ssv_sdiobridge_cmd cmd_data;
+    long retval=0;
+    if ( isCompat ) {
+        CHECK_RET(copy_from_user(&cmd_data,(int __user *)pucmd_data,sizeof(*pucmd_data)));
+    } else {
+        CHECK_RET(copy_from_user(&cmd_data,(int __user *)pucmd_data,sizeof(*pucmd_data)));
+    }
+#if 0
+#ifdef __x86_64
+    dev_err(glue->dev,"%s: isCompat[%d] [%lX] [%lX] [%X] \n",__FUNCTION__,isCompat,IOCTL_SSVSDIO_GET_FUNCTION_FOCUS,IOCTL_SSVSDIO_READ_DATA,cmd);
+#else
+    dev_err(glue->dev,"%s: isCompat[%d] [%X] [%X] [%X] \n",__FUNCTION__,isCompat,IOCTL_SSVSDIO_GET_FUNCTION_FOCUS,IOCTL_SSVSDIO_READ_DATA,cmd);
+#endif
+#endif
+    switch (cmd) {
+    case IOCTL_SSVSDIO_GET_FUNCTION_FOCUS:
+        retval = ssv_sdiobridge_ioctl_getFuncfocus(glue,cmd,&cmd_data,pucmd_data,isCompat);
+        break;
+    case IOCTL_SSVSDIO_SET_FUNCTION_FOCUS:
+        retval = ssv_sdiobridge_ioctl_setFuncfocus(glue,cmd,&cmd_data,pucmd_data,isCompat);
+        break;
+    case IOCTL_SSVSDIO_GET_BUS_WIDTH:
+        retval = ssv_sdiobridge_ioctl_getBusWidth(glue,cmd,&cmd_data,pucmd_data,isCompat);
+        break;
+#if 0
+    case IOCTL_SSVSDIO_SET_BUS_WIDTH:
+        retval = ssv_sdiobridge_ioctl_setBusWidth(glue,cmd,&cmd_data,pucmd_data,isCompat);
+        break;
+    case IOCTL_SSVSDIO_GET_BUS_CLOCK:
+        break;
+    case IOCTL_SSVSDIO_SET_BUS_CLOCK:
+        break;
+    case IOCTL_SSVSDIO_GET_BLOCK_MODE:
+        retval = ssv_sdiobridge_ioctl_getBlockMode(glue,cmd,&cmd_data,pucmd_data,isCompat);
+        break;
+    case IOCTL_SSVSDIO_SET_BLOCK_MODE:
+        retval = ssv_sdiobridge_ioctl_setBlockMode(glue,cmd,&cmd_data,pucmd_data,isCompat);
+        break;
+#endif
+    case IOCTL_SSVSDIO_GET_BLOCKLEN:
+        retval = ssv_sdiobridge_ioctl_getBlockSize(glue,cmd,&cmd_data,pucmd_data,isCompat);
+        break;
+    case IOCTL_SSVSDIO_SET_BLOCKLEN:
+        retval = ssv_sdiobridge_ioctl_setBlockSize(glue,cmd,&cmd_data,pucmd_data,isCompat);
+        break;
+    case IOCTL_SSVSDIO_READ_BYTE:
+        retval = ssv_sdiobridge_ioctl_readByte(glue,cmd,&cmd_data,pucmd_data,isCompat);
+        break;
+    case IOCTL_SSVSDIO_WRITE_BYTE:
+        retval = ssv_sdiobridge_ioctl_writeByte(glue,cmd,&cmd_data,pucmd_data,isCompat);
+        break;
+    case IOCTL_SSVSDIO_GET_MULTI_BYTE_IO_PORT:
+        retval = ssv_sdiobridge_ioctl_getMultiByteIOPort(glue,cmd,&cmd_data,pucmd_data,isCompat);
+        break;
+    case IOCTL_SSVSDIO_SET_MULTI_BYTE_IO_PORT:
+        retval = ssv_sdiobridge_ioctl_setMultiByteIOPort(glue,cmd,&cmd_data,pucmd_data,isCompat);
+        break;
+    case IOCTL_SSVSDIO_READ_MULTI_BYTE:
+        retval = ssv_sdiobridge_ioctl_readMultiByte(glue,cmd,&cmd_data,pucmd_data,isCompat);
+        break;
+    case IOCTL_SSVSDIO_WRITE_MULTI_BYTE:
+        retval = ssv_sdiobridge_ioctl_writeMultiByte(glue,cmd,&cmd_data,pucmd_data,isCompat);
+        break;
+    case IOCTL_SSVSDIO_GET_MULTI_BYTE_REG_IO_PORT:
+        retval = ssv_sdiobridge_ioctl_getMultiByteRegIOPort(glue,cmd,&cmd_data,pucmd_data,isCompat);
+        break;
+    case IOCTL_SSVSDIO_SET_MULTI_BYTE_REG_IO_PORT:
+        retval = ssv_sdiobridge_ioctl_setMultiByteRegIOPort(glue,cmd,&cmd_data,pucmd_data,isCompat);
+        break;
+    case IOCTL_SSVSDIO_READ_REG:
+        retval = ssv_sdiobridge_ioctl_readReg(glue,cmd,&cmd_data,pucmd_data,isCompat);
+        break;
+    case IOCTL_SSVSDIO_WRITE_REG:
+        retval = ssv_sdiobridge_ioctl_writeReg(glue,cmd,&cmd_data,pucmd_data,isCompat);
+        break;
+    }
+    return retval;
+}
+static long ssv_sdiobridge_device_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
+{
+    struct ssv_sdiobridge_glue *glue =filp->private_data;
+    long retval=0;
+    struct ssv_sdiobridge_cmd *pucmd_data;
+    pucmd_data = (struct ssv_sdiobridge_cmd *)arg;
+    retval = ssv_sdiobridge_device_ioctl_process( glue,cmd,pucmd_data,true);
+    return retval;
+}
+static long ssv_sdiobridge_device_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
+{
+    struct ssv_sdiobridge_glue *glue =filp->private_data;
+    long retval=0;
+    struct ssv_sdiobridge_cmd *pucmd_data;
+    pucmd_data = (struct ssv_sdiobridge_cmd *)arg;
+    retval = ssv_sdiobridge_device_ioctl_process( glue,cmd,pucmd_data,false);
+    return retval;
+}
+static bool ssv_sdiobridge_have_data(struct ssv_sdiobridge_glue *glue)
+{
+    dev_err(glue->dev,"%s(): !list_empty(&glue->rxreadybuf)[%d]\n", __FUNCTION__,!list_empty(&glue->rxreadybuf));
+    return !list_empty(&glue->rxreadybuf);
+}
+static ssize_t ssv_sdiobridge_device_read(struct file *filp,
+        char *buffer,
+        size_t length,
+        loff_t *offset)
+{
+    struct ssv_sdiobridge_glue *glue =filp->private_data;
+    struct ssv_rxbuf *bf;
+    int copylength;
+    dev_err(glue->dev,"%s():\n", __FUNCTION__);
+    spin_lock_bh(&glue->rxbuflock);
+    if (list_empty(&glue->rxreadybuf)) {
+        spin_unlock_bh(&glue->rxbuflock);
+        dev_err(glue->dev,"%s():no data for read \n", __FUNCTION__);
+#if 1
+        if ( wait_event_interruptible(glue->read_wq, ssv_sdiobridge_have_data(glue))!=0) {
+            dev_err(glue->dev,"%s():not get data ?? \n", __FUNCTION__);
+            return -1;
+        }
+#else
+        wait_event(glue->read_wq,ssv_sdiobridge_have_data(glue));
+#endif
+        spin_lock_bh(&glue->rxbuflock);
+        if (list_empty(&glue->rxreadybuf)) {
+            spin_unlock_bh(&glue->rxbuflock);
+            dev_err(glue->dev,"%s():stop ?? \n", __FUNCTION__);
+            return -1;
+        }
+    }
+    bf = list_first_entry(&glue->rxreadybuf, struct ssv_rxbuf, list);
+    list_del(&bf->list);
+    spin_unlock_bh(&glue->rxbuflock);
+    copylength = min(bf->rxsize,(u32)length);
+    CHECK_RET(copy_to_user((int __user *)buffer,bf->rxdata,copylength));
+    dev_err(glue->dev,"%s():get rx data : data len:[%d], user read len:[%d],real read len:[%d] \n", __FUNCTION__,bf->rxsize,(u32)length,copylength);
+    spin_lock_bh(&glue->rxbuflock);
+    list_add_tail(&bf->list, &glue->rxbuf);
+    spin_unlock_bh(&glue->rxbuflock);
+    return copylength;
+}
+static ssize_t ssv_sdiobridge_device_write(struct file *filp,
+        const char *buff,
+        size_t len,
+        loff_t *off)
+{
+    struct ssv_sdiobridge_glue *glue =filp->private_data;
+    struct sdio_func *func = dev_to_sdio_func(glue->dev);
+    u8 *tmpdata;
+    int ret;
+    dev_err(glue->dev,"%s():\n", __FUNCTION__);
+    tmpdata = kzalloc(len, GFP_KERNEL);
+    if ( tmpdata == NULL ) {
+        dev_err(glue->dev,"%s: error : alloc buf error size:%d",__FUNCTION__,(u32)len);
+        return -1;
+    }
+    CHECK_RET(copy_from_user(tmpdata,(int __user *)buff,len));
+    if (unlikely(glue->dump)) {
+        printk(KERN_DEBUG "%s: WRITE data address[%08x] len[%d] readsize[%d]\n",__FUNCTION__,glue->dataIOPort,(int)len,sdio_align_size(func,len));
+        print_hex_dump(KERN_DEBUG, "ssv_sdio: WRITE ",
+                       DUMP_PREFIX_OFFSET, 16, 1,
+                       tmpdata, len, false);
+    }
+    sdio_claim_host(func);
+    ret = sdio_memcpy_toio(func, glue->dataIOPort,tmpdata, sdio_align_size(func,len));
+    sdio_release_host(func);
+    kfree(tmpdata);
+    if ( ret ) {
+        dev_err(glue->dev,"%s: error : %d",__FUNCTION__,ret);
+        return -1;
+    }
+    return len;
+}
+struct file_operations fops = {
+    .owner = THIS_MODULE,
+    .read = ssv_sdiobridge_device_read,
+    .write = ssv_sdiobridge_device_write,
+    .open = ssv_sdiobridge_device_open,
+    .release = ssv_sdiobridge_device_close,
+    .compat_ioctl = ssv_sdiobridge_device_compat_ioctl,
+    .unlocked_ioctl = ssv_sdiobridge_device_ioctl
+};
+static void ssv_sdiobridge_irq_process(struct sdio_func *func,
+                                       struct ssv_sdiobridge_glue *glue)
+{
+    int err_ret;
+    u8 status;
+    sdio_claim_host(func);
+    status = sdio_readb(func, REG_INT_STATUS, &err_ret);
+    if ( status & SSVCABRIO_INT_RX ) {
+        struct ssv_rxbuf *bf;
+        int readsize;
+        spin_lock_bh(&glue->rxbuflock);
+        if (list_empty(&glue->rxbuf)) {
+            spin_unlock_bh(&glue->rxbuflock);
+            sdio_release_host(func);
+            dev_err(glue->dev, "ssv_sdiobridge_irq_process no avaible rx buf list??\n");
+            return;
+        } else {
+            bf = list_first_entry(&glue->rxbuf, struct ssv_rxbuf, list);
+            list_del(&bf->list);
+        }
+        spin_unlock_bh(&glue->rxbuflock);
+        bf->rxsize = (int)(sdio_readb(func, REG_CARD_PKT_LEN_0, &err_ret)&0xff);
+        dev_err(glue->dev, "sdio read rx size[%08x] 0x10[%02x]\n",bf->rxsize, sdio_readb(func, REG_CARD_PKT_LEN_0, &err_ret)&0xff);
+        bf->rxsize = bf->rxsize | ((sdio_readb(func, REG_CARD_PKT_LEN_1, &err_ret)&0xff)<<0x8);
+        readsize = sdio_align_size(func,bf->rxsize);
+        dev_err(glue->dev, "sdio read rx size[%08x] 0x11[%02x] readsize[%d]\n",bf->rxsize, sdio_readb(func, REG_CARD_PKT_LEN_1, &err_ret)&0xff,readsize);
+        err_ret = sdio_memcpy_fromio(func, bf->rxdata, glue->dataIOPort, readsize);
+        sdio_release_host(func);
+        dev_err(glue->dev, "ssv_sdiobridge_irq_process read 53, %d bytes  ret:[%d]\n", readsize,err_ret );
+        if (unlikely(glue->dump)) {
+            printk(KERN_DEBUG "ssv_sdiobridge_irq_process: READ data address[%08x] len[%d] readsize[%d]\n",glue->dataIOPort,(int)bf->rxsize,readsize);
+            print_hex_dump(KERN_DEBUG, "ssv_sdio: READ ",
+                           DUMP_PREFIX_OFFSET, 16, 1,
+                           bf->rxdata, bf->rxsize, false);
+        }
+        if (WARN_ON(err_ret)) {
+            dev_err(glue->dev, "ssv_sdiobridge_irq_process read failed (%d)\n", err_ret);
+            spin_lock_bh(&glue->rxbuflock);
+            list_add_tail(&bf->list, &glue->rxbuf);
+            spin_unlock_bh(&glue->rxbuflock);
+        } else {
+            spin_lock_bh(&glue->rxbuflock);
+            list_add_tail(&bf->list, &glue->rxreadybuf);
+            wake_up(&glue->read_wq);
+            spin_unlock_bh(&glue->rxbuflock);
+        }
+    } else {
+        sdio_release_host(func);
+    }
+}
+static void ssv_sdiobridge_irq_handler(struct sdio_func *func)
+{
+    struct ssv_sdiobridge_glue *glue = sdio_get_drvdata(func);
+    dev_err(&func->dev, "ssv_sdiobridge_irq_handler\n");
+    WARN_ON(glue == NULL);
+    if ( glue != NULL ) {
+        atomic_set(&glue->irq_handling, 1);
+        ssv_sdiobridge_irq_process(func,glue);
+        atomic_set(&glue->irq_handling, 0);
+        wake_up(&glue->irq_wq);
+    }
+}
+static void ssv_sdiobridge_irq_enable(struct sdio_func *func,
+                                      struct ssv_sdiobridge_glue *glue)
+{
+    int ret;
+    func = dev_to_sdio_func(glue->dev);
+    sdio_claim_host(func);
+    dev_err(glue->dev, "ssv_sdiobridge_irq_enable\n");
+    ret = sdio_claim_irq(func, ssv_sdiobridge_irq_handler);
+    if (ret)
+        dev_err(glue->dev, "Failed to claim sdio irq: %d\n", ret);
+    sdio_release_host(func);
+}
+static bool ssv_sdiobridge_is_on_irq(struct ssv_sdiobridge_glue *glue)
+{
+    return !atomic_read(&glue->irq_handling);
+}
+static void ssv_sdiobridge_irq_disable(struct ssv_sdiobridge_glue *glue,bool iswaitirq)
+{
+    struct sdio_func *func;
+    int ret;
+    dev_err(glue->dev, "ssv_sdiobridge_irq_disable1\n");
+    if ( glue != NULL ) {
+        func = dev_to_sdio_func(glue->dev);
+        sdio_claim_host(func);
+        dev_err(glue->dev, "ssv_sdiobridge_irq_disable2 [%d]\n",atomic_read(&glue->irq_handling));
+        if (atomic_read(&glue->irq_handling)&&iswaitirq) {
+            dev_err(glue->dev, "ssv_sdiobridge_irq_disable3\n");
+            sdio_release_host(func);
+            ret = wait_event_interruptible(glue->irq_wq,
+                                           ssv_sdiobridge_is_on_irq(glue));
+            dev_err(glue->dev, "ssv_sdiobridge_irq_disable4 ret[%d]\n",ret);
+            if (ret)
+                return;
+            sdio_claim_host(func);
+        }
+        dev_err(glue->dev, "ssv_sdiobridge_irq_disable5\n");
+        ret = sdio_release_irq(func);
+        if (ret)
+            dev_err(glue->dev, "Failed to release sdio irq: %d\n", ret);
+        dev_err(glue->dev, "ssv_sdiobridge_irq_disable6\n");
+        sdio_release_host(func);
+    }
+}
+#if 0
+static void ssv_sdiobridge_irq_sync(struct device *child)
+{
+    struct ssv_sdiobridge_glue *glue = dev_get_drvdata(child->parent);
+    struct sdio_func *func;
+    int ret;
+    if ( glue != NULL ) {
+        func = dev_to_sdio_func(glue->dev);
+        sdio_claim_host(func);
+        if (atomic_read(&glue->irq_handling)) {
+            sdio_release_host(func);
+            ret = wait_event_interruptible(glue->irq_wq,
+                                           ssv_sdiobridge_is_on_irq(glue));
+            if (ret)
+                return;
+            sdio_claim_host(func);
+        }
+        sdio_release_host(func);
+    }
+}
+#endif
+static void ssv_sdiobridge_read_parameter(struct sdio_func *func,
+        struct ssv_sdiobridge_glue *glue)
+{
+    int err_ret;
+    sdio_claim_host(func);
+    glue->dataIOPort = 0;
+    glue->dataIOPort = glue->dataIOPort | (sdio_readb(func, REG_DATA_IO_PORT_0, &err_ret) << ( 8*0 ));
+    glue->dataIOPort = glue->dataIOPort | (sdio_readb(func, REG_DATA_IO_PORT_1, &err_ret) << ( 8*1 ));
+    glue->dataIOPort = glue->dataIOPort | (sdio_readb(func, REG_DATA_IO_PORT_2, &err_ret) << ( 8*2 ));
+    glue->regIOPort = 0;
+    glue->regIOPort = glue->regIOPort | (sdio_readb(func, REG_REG_IO_PORT_0, &err_ret) << ( 8*0 ));
+    glue->regIOPort = glue->regIOPort | (sdio_readb(func, REG_REG_IO_PORT_1, &err_ret) << ( 8*1 ));
+    glue->regIOPort = glue->regIOPort | (sdio_readb(func, REG_REG_IO_PORT_2, &err_ret) << ( 8*2 ));
+    dev_err(&func->dev, "dataIOPort 0x%x regIOPort 0x%x [%lx]\n",
+            glue->dataIOPort,glue->regIOPort,(long unsigned int)IOCTL_SSVSDIO_GET_BLOCKLEN);
+    sdio_set_block_size(func,glue->blockSize);
+    sdio_release_host(func);
+}
+static int ssv_sdiobridge_init_buf(struct ssv_sdiobridge_glue *glue)
+{
+    u32 bsize,i,error;
+    struct ssv_rxbuf *bf;
+    init_waitqueue_head(&glue->read_wq);
+    spin_lock_init(&glue->rxbuflock);
+    INIT_LIST_HEAD(&glue->rxbuf);
+    INIT_LIST_HEAD(&glue->rxreadybuf);
+    bsize = sizeof(struct ssv_rxbuf) * RXBUFSIZE;
+    glue->bufaddr = kzalloc(bsize, GFP_KERNEL);
+    if (glue->bufaddr == NULL) {
+        error = -ENOMEM;
+        goto fail;
+    }
+    bf = glue->bufaddr;
+    for (i = 0; i < RXBUFSIZE; i++, bf++) {
+        list_add_tail(&bf->list, &glue->rxbuf);
+    }
+    return 0;
+fail:
+    return error;
+}
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,4,0)
+static char *ssv_sdiobridge_devnode(struct device *dev, umode_t *mode)
+#else
+static char *ssv_sdiobridge_devnode(struct device *dev, mode_t *mode)
+#endif
+{
+    if (!mode)
+        return NULL;
+    *mode = 0644;
+    return NULL;
+}
+extern int ssv_devicetype;
+static int __devinit ssv_sdiobridge_probe(struct sdio_func *func,
+        const struct sdio_device_id *id)
+{
+    mmc_pm_flag_t mmcflags;
+    int ret = -ENOMEM;
+    dev_t dev;
+    int alloc_ret = 0;
+    int cdev_ret = 0;
+    int err_ret;
+    if (ssv_devicetype != 1) {
+        printk(KERN_INFO "Not using SSV6200 bridge SDIO driver.\n");
+        return -ENODEV;
+    }
+    printk(KERN_INFO "=======================================\n");
+    printk(KERN_INFO "==           RUN SDIO BRIDGE         ==\n");
+    printk(KERN_INFO "=======================================\n");
+    printk(KERN_INFO "ssv_sdiobridge_probe func->num:%d",func->num);
+    if (func->num != 0x01)
+        return -ENODEV;
+    glue = kzalloc(sizeof(*glue), GFP_KERNEL);
+    if (!glue) {
+        dev_err(&func->dev, "can't allocate glue\n");
+        goto out;
+    }
+    glue->blockMode = false;
+    glue->blockSize = BLOCKSIZE;
+    glue->autoAckInt = true;
+    glue->dump = false;
+    glue->funcFocus = 1;
+    ssv_sdiobridge_init_buf(glue);
+    glue->dev = &func->dev;
+    func->card->quirks |= MMC_QUIRK_LENIENT_FN0;
+    func->card->quirks |= MMC_QUIRK_BLKSZ_FOR_BYTE_MODE;
+    mmcflags = sdio_get_host_pm_caps(func);
+    dev_err(glue->dev, "sdio PM caps = 0x%x\n", mmcflags);
+    sdio_set_drvdata(func, glue);
+    pm_runtime_put_noidle(&func->dev);
+    ssv_sdiobridge_read_parameter(func,glue);
+    dev = MKDEV(ssv_sdiobridge_ioctl_major, 0);
+    alloc_ret = alloc_chrdev_region(&dev, 0, num_of_dev, FILE_DEVICE_SSVSDIO_NAME);
+    if (alloc_ret)
+        goto error;
+    ssv_sdiobridge_ioctl_major = MAJOR(dev);
+    cdev_init(&ssv_sdiobridge_ioctl_cdev, &fops);
+    cdev_ret = cdev_add(&ssv_sdiobridge_ioctl_cdev, dev, num_of_dev);
+    if (cdev_ret)
+        goto error;
+    fc=class_create(THIS_MODULE, FILE_DEVICE_SSVSDIO_NAME);
+    fc->devnode = ssv_sdiobridge_devnode;
+    device_create(fc, NULL, dev, NULL, "%s", FILE_DEVICE_SSVSDIO_NAME);
+    dev_err(glue->dev, "%s driver(major: %d) installed.\n", FILE_DEVICE_SSVSDIO_NAME, ssv_sdiobridge_ioctl_major);
+    init_waitqueue_head(&glue->irq_wq);
+    ssv_sdiobridge_irq_enable(func,glue);
+    sdio_claim_host(func);
+#ifdef CONFIG_SSV_SDIO_EXT_INT
+    sdio_writeb(func,(~(SSVCABRIO_INT_RX)|SSVCABRIO_INT_GPIO)&0x7, 0x04, &err_ret);
+#else
+    sdio_writeb(func,(~(SSVCABRIO_INT_RX|SSVCABRIO_INT_GPIO))&0x7, 0x04, &err_ret);
+#endif
+    sdio_release_host(func);
+    return 0;
+error:
+    if (cdev_ret == 0)
+        cdev_del(&ssv_sdiobridge_ioctl_cdev);
+    if (alloc_ret == 0)
+        unregister_chrdev_region(dev, num_of_dev);
+    kfree(glue);
+out:
+    return ret;
+}
+static void __devexit ssv_sdiobridge_remove(struct sdio_func *func)
+{
+    struct ssv_sdiobridge_glue *glue = sdio_get_drvdata(func);
+    dev_t dev;
+    int err_ret;
+    sdio_claim_host(func);
+#ifdef CONFIG_SSV_SDIO_EXT_INT
+    sdio_writeb(func,0, 0x04, &err_ret);
+#else
+    sdio_writeb(func,SSVCABRIO_INT_GPIO, 0x04, &err_ret);
+#endif
+    sdio_release_host(func);
+    ssv_sdiobridge_irq_disable(glue,false);
+    dev = MKDEV(ssv_sdiobridge_ioctl_major, 0);
+    device_destroy(fc,dev);
+    class_destroy(fc);
+    cdev_del(&ssv_sdiobridge_ioctl_cdev);
+    unregister_chrdev_region(dev, num_of_dev);
+    pm_runtime_get_noresume(&func->dev);
+    if ( glue ) {
+        dev_err(glue->dev, "ssv_sdiobridge_remove");
+        if (glue->bufaddr) {
+            kfree(glue->bufaddr);
+        }
+        kfree(glue);
+        glue = NULL;
+    }
+    sdio_set_drvdata(func, NULL);
+}
+#ifdef CONFIG_PM
+static int ssv_sdiobridge_suspend(struct device *dev)
+{
+    int ret = 0;
+    return ret;
+}
+static int ssv_sdiobridge_resume(struct device *dev)
+{
+    dev_dbg(dev, "ssvcabrio resume\n");
+    return 0;
+}
+static const struct dev_pm_ops ssv_sdiobridge_pm_ops = {
+    .suspend = ssv_sdiobridge_suspend,
+    .resume = ssv_sdiobridge_resume,
+};
+#endif
+static struct sdio_driver ssv_sdio_bridge_driver = {
+    .name = "ssv_sdio_bridge",
+    .id_table = ssv_sdiobridge_devices,
+    .probe = ssv_sdiobridge_probe,
+    .remove = __devexit_p(ssv_sdiobridge_remove),
+#ifdef CONFIG_PM
+    .drv = {
+        .pm = &ssv_sdiobridge_pm_ops,
+    },
+#endif
+};
+EXPORT_SYMBOL(ssv_sdio_bridge_driver);
+#if 1
+static int __init ssv_sdiobridge_init(void)
+{
+    printk(KERN_INFO "ssv_sdiobridge_init\n");
+    return sdio_register_driver(&ssv_sdio_bridge_driver);
+}
+static void __exit ssv_sdiobridge_exit(void)
+{
+    printk(KERN_INFO "ssv_sdiobridge_exit\n");
+    sdio_unregister_driver(&ssv_sdio_bridge_driver);
+}
+module_init(ssv_sdiobridge_init);
+module_exit(ssv_sdiobridge_exit);
+#endif
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("iComm-semi, Ltd");
diff --git a/drivers/net/wireless/ssv6x5x/bridge/sdiobridge.h b/drivers/net/wireless/ssv6x5x/bridge/sdiobridge.h
new file mode 100644
index 000000000..2a80c923f
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/bridge/sdiobridge.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef SSVSDIOBRIDGE_H
+#define SSVSDIOBRIDGE_H
+#include <linux/etherdevice.h>
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <linux/leds.h>
+#include <linux/completion.h>
+#include <linux/ioctl.h>
+#include <linux/types.h>
+#include "sdiobridge_pub.h"
+struct ssv_sdiobridge_glue {
+    struct device *dev;
+    u8 blockMode;
+    u16 blockSize;
+    u8 autoAckInt;
+    unsigned int dataIOPort;
+    unsigned int regIOPort;
+    u8 funcFocus;
+    atomic_t irq_handling;
+    wait_queue_head_t irq_wq;
+    wait_queue_head_t read_wq;
+    spinlock_t rxbuflock;
+    void *bufaddr;
+    struct list_head rxbuf;
+    struct list_head rxreadybuf;
+    struct dentry *debugfs;
+    struct dentry *dump_entry;
+    u32 dump;
+};
+#define MANUFACTURER_SSV_CODE 0x3030
+#define MANUFACTURER_ID_CABRIO_BASE 0x3030
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/bridge/sdiobridge_pub.h b/drivers/net/wireless/ssv6x5x/bridge/sdiobridge_pub.h
new file mode 100644
index 000000000..a644f277a
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/bridge/sdiobridge_pub.h
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef SSVSDIOBRIDGE_PUB_H
+#define SSVSDIOBRIDGE_PUB_H
+#include <linux/etherdevice.h>
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <linux/leds.h>
+#include <linux/completion.h>
+#include <linux/ioctl.h>
+#include <linux/types.h>
+struct ssv_sdiobridge_cmd {
+    __u32 in_data_len;
+    u8* in_data;
+#ifndef __x86_64
+    __u32 padding1;
+#endif
+    __u32 out_data_len;
+    u8* out_data;
+#ifndef __x86_64
+    __u32 padding2;
+#endif
+    __u32 response;
+} __attribute__((packed));
+#define FILE_DEVICE_SSVSDIO MMC_BLOCK_MAJOR
+#define FILE_DEVICE_SSVSDIO_SEQ 0x50
+#define FILE_DEVICE_SSVSDIO_NAME "ssvsdiobridge"
+#if 0
+#define IOCTL_SSVSDIO_GET_DRIVER_VERSION \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x01, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_GET_FUNCTION_NUMBER \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x02, struct ssv_sdiobridge_cmd)
+#endif
+#define IOCTL_SSVSDIO_GET_FUNCTION_FOCUS \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x03, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_SET_FUNCTION_FOCUS \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x04, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_GET_BUS_WIDTH \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x05, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_SET_BUS_WIDTH \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x06, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_GET_BUS_CLOCK \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x07, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_SET_BUS_CLOCK \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x08, struct ssv_sdiobridge_cmd)
+#if 0
+#define IOCTL_SSVSDIO_GET_BLOCK_MODE \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x09, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_SET_BLOCK_MODE \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x0a, struct ssv_sdiobridge_cmd)
+#endif
+#define IOCTL_SSVSDIO_GET_BLOCKLEN \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x0b, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_SET_BLOCKLEN \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x0c, struct ssv_sdiobridge_cmd)
+#if 0
+#define IOCTL_SSVSDIO_GET_FN0_BLOCKLEN \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x0d, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_SET_FN0_BLOCKLEN \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x0e, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_GET_BUS_INTERFACE_CONTROL \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x0f, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_SET_BUS_INTERFACE_CONTROL \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x10, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_GET_INT_ENABLE \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x11, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_SET_INT_ENABLE \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x12, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_GET_AUTO_ACK_INT \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x13, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_SET_AUTO_ACK_INT \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x14, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_ACK_INT \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x15, struct ssv_sdiobridge_cmd)
+#endif
+#define IOCTL_SSVSDIO_READ_BYTE \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x16, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_WRITE_BYTE \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x17, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_GET_MULTI_BYTE_IO_PORT \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x18, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_SET_MULTI_BYTE_IO_PORT \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x19, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_READ_MULTI_BYTE \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x1a, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_WRITE_MULTI_BYTE \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x1b, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_GET_MULTI_BYTE_REG_IO_PORT \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x1c, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_SET_MULTI_BYTE_REG_IO_PORT \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x1d, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_READ_REG \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x1e, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_WRITE_REG \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x1f, struct ssv_sdiobridge_cmd)
+#define IOCTL_SSVSDIO_READ_DATA \
+    _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x20, struct ssv_sdiobridge_cmd)
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/build.sh b/drivers/net/wireless/ssv6x5x/build.sh
new file mode 100755
index 000000000..10fbc693f
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/build.sh
@@ -0,0 +1,14 @@
+#/bin/bash
+
+# generate version information header
+./ver_info.pl include/ssv_version.h
+
+if [ $? -eq 0 ]; then
+    echo "Please check SVN first !!"
+else
+if hash colormake 2>/dev/null; then
+    colormake;colormake install
+else
+    make;make install
+fi
+fi
diff --git a/drivers/net/wireless/ssv6x5x/cab_tu_coex.sh b/drivers/net/wireless/ssv6x5x/cab_tu_coex.sh
new file mode 100755
index 000000000..5d510da58
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/cab_tu_coex.sh
@@ -0,0 +1,61 @@
+#!/bin/sh
+
+syms="\
+ssv_initmac \
+ssv6xxx_sdio_driver \
+stacfgpath \
+cfgfirmwarepath \
+ssv_cfg \
+ssv6xxx_exit \
+ssv6xxx_init \
+ssv6xxx_hci_deregister \
+ssv6xxx_dev_remove \
+ssv6xxx_sdio_exit \
+ssv6xxx_sdio_init \
+ssvdevice_init \
+ssvdevice_exit \
+ssv6xxx_hci_exit \
+ssv6xxx_hci_init \
+cfg_cmds \
+ssv6xxx_dev_probe \
+ssv6xxx_hci_register \
+generic_wifi_exit_module \
+generic_wifi_init_module \
+ssv\" \
+"
+syms2="\
+ssv6xxx_sdio_probe \
+ssv6xxx_sdio_remove \
+ssv6xxx_sdio_suspend \
+ssv6xxx_sdio_resume \
+"
+
+syms3="\
+SSV6XXX_SDIO \
+"
+
+for i in $syms;
+do
+echo "Replacing $i to tu_$i\n"
+find . -name "*.[ch]"| xargs sed -i "s/$i/tu_$i/g"
+done
+
+echo "Restoring tu_ssv_cfg.h to ssv_cfg.h\n"
+find . -name "*.[ch]"| xargs sed -i "s/\"tu_ssv_cfg\.h\"/\"ssv_cfg\.h\"/g"
+find . -name "*.[ch]"| xargs sed -i "s/<tu_ssv_cfg\.h>/\"ssv_cfg\.h\"/g"
+
+for i in $syms2;
+do
+echo "Replacing $i to tu_$i\n"
+find . -name "*.[ch]"| xargs sed -i "s/$i/tu_$i/g"
+done
+
+echo "Replacing SSV WLAN driver to TU SSV WLAN driver\n"
+find . -name "*.[ch]"| xargs sed -i "s/SSV WLAN driver/TU SSV WLAN driver/g"
+
+for i in $syms3;
+do
+echo "Replacing $i to TU_$i\n"
+find . -name "*.[ch]"| xargs sed -i "s/$i/TU_$i/g"
+done
+
diff --git a/drivers/net/wireless/ssv6x5x/clean_log.sh b/drivers/net/wireless/ssv6x5x/clean_log.sh
new file mode 100755
index 000000000..a9eeac927
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/clean_log.sh
@@ -0,0 +1,4 @@
+#/bin/bash
+dmesg -C
+rm -fr /var/log
+service rsyslog restart
diff --git a/drivers/net/wireless/ssv6x5x/cli b/drivers/net/wireless/ssv6x5x/cli
new file mode 100755
index 000000000..8d8579aca
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/cli
@@ -0,0 +1,40 @@
+#!/bin/bash
+
+ssv_phy=""
+if [[ ${1} =~ "wlan" ]]; then
+	wlan_dirs=/sys/class/net/${1}/device/ieee80211/
+	if [ ! -e ${wlan_dirs} ]; then
+		echo "Could not find the ${1}."
+		exit 1;
+	fi
+	# shift wlanX
+	shift 1
+	ssv_phy=`ls ${wlan_dirs}`
+else
+	phy_dirs="/sys/class/ieee80211/*"
+
+	for phy_dir in $phy_dirs; do
+		if [ ! -d ${phy_dir}/device/driver ]; then
+			exit 1;
+		fi
+		drv_name=`ls ${phy_dir}/device/driver | grep SV6`
+
+    	if [ ${drv_name} ]; then
+    		ssv_phy=`basename $phy_dir`;
+    		break;
+    	fi
+	done
+fi
+
+
+# excute CLI
+if [ ${ssv_phy} ]; then
+	SSV_CMD_FILE=/proc/ssv/${ssv_phy}/ssv_cmd
+	if [ -f $SSV_CMD_FILE ]; then
+		echo "$*" > $SSV_CMD_FILE
+		cat $SSV_CMD_FILE
+	fi
+else 
+	echo "./cli [wlanX] [CMD]"
+fi
+
diff --git a/drivers/net/wireless/ssv6x5x/config.mak b/drivers/net/wireless/ssv6x5x/config.mak
new file mode 100755
index 000000000..af7c90918
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/config.mak
@@ -0,0 +1,64 @@
+
+KVERSION="`uname -r`"
+#DRVPATH=/lib/modules/$(KVERSION)/kernel/drivers/net/wireless/ssv6200
+DRVPATH=kernel/drivers/net/wireless/ssv6200
+KCFLAG += -Werror
+#EXTRA_CFLAGS := -I$(KBUILD_TOP) -I$(KBUILD_TOP)/include
+EXTRA_CFLAGS := -I$(KBUILD_TOP) 
+EXTRA_CFLAGS += -I$(KBUILD_TOP)/include 
+
+
+include $(KBUILD_TOP)/config_common.mak
+
+
+ccflags-y += -DREPORT_TX_STATUS_DIRECTLY
+
+########################################################
+## The following definition move from common mak
+
+# use for debug
+ccflags-y += -DCONFIG_IRQ_DEBUG_COUNT
+ccflags-y += -DCONFIG_SSV6XXX_DEBUGFS
+#### end of move from  common mak
+
+
+## Use crypto in SSV driver for ssv6051
+#ccflags-y += -DMULTI_THREAD_ENCRYPT
+#ccflags-y += -DKTHREAD_BIND
+#ccflags-y += -DUSE_LOCAL_CRYPTO
+#ccflags-y += -DUSE_LOCAL_WEP_CRYPTO
+#ccflags-y += -DUSE_LOCAL_TKIP_CRYPTO
+#ccflags-y += -DUSE_LOCAL_CCMP_CRYPTO
+#ccflags-y += -DUSE_LOCAL_SMS4_CRYPTO
+#ccflags-y += -DCONFIG_SSV_WAPI
+#ccflags-y += -DHAS_CRYPTO_LOCK
+#ccflags-y += -DFW_WSID_WATCH_LIST
+#endif
+
+
+###########################################################
+# option to :qswitch driver between relay device and sw mac device
+# Enable ->Relay device	(CHAR)
+# Disable->SW MAC device(NET)
+
+#DRV_OPT = HUW_DRV
+#For HUW to define some resources
+ifeq ($(DRV_OPT), HUW_DRV)
+ccflags-y += -DHUW_DRV
+endif
+#
+
+####################################################################
+# mac80211 option for use local ssv_mac80211 or kernel mac80211
+# if set SSV means our smac driver use local ssv_mac80211.ko
+# otherwise use kernel mac80211 build-in sub-sys
+####################################################################
+#MAC80211_OPT = SSV
+#For HUW to define some resources
+ifeq ($(MAC80211_OPT), SSV)
+EXTRA_CFLAGS += -I$(KBUILD_TOP)/mac80211 
+EXTRA_CFLAGS += -I$(KBUILD_TOP)/mac80211/include
+
+ccflags-y += -DSSV_MAC80211
+endif
+#
diff --git a/drivers/net/wireless/ssv6x5x/config_common.mak b/drivers/net/wireless/ssv6x5x/config_common.mak
new file mode 100755
index 000000000..b29847713
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/config_common.mak
@@ -0,0 +1,142 @@
+
+CONFIG_SSV6X5X=m
+#ccflags-y += -DCONFIG_SSV6200_CORE
+#CONFIG_MAC80211_LEDS=y
+#CONFIG_MAC80211_DEBUGFS=y
+#CONFIG_MAC80211_MESH=y
+#CONFIG_PM=y
+#CONFIG_MAC80211_RC_MINSTREL=y
+#CONFIG_MAC80211_RC_MINSTREL_HT=y
+
+#ccflags-y += -D_ICOMM_MAC80211_
+
+ccflags-y += -D__CHECK_ENDIAN__
+###########################################################################
+# Compiler options                                                        #
+###########################################################################
+ccflags-y += -Werror
+
+# Enable -g to help debug. Deassembly from .o to .S would help to track to 
+# the problomatic line from call stack dump.
+#ccflags-y += -DDEBUG -g
+ccflags-y += -Os
+
+#########################################################
+# option enable shal
+# if it is enable 
+# DCONFIG_SSV_CABRIO_A/DCONFIG_SSV_CABRIO_A is not valid in driver.
+ccflags-y += -DSSV_SUPPORT_HAL
+ccflags-y += -DSSV_SUPPORT_SSV6006
+
+############################################################
+# If you change the settings, please change the file synchronization
+# smac\firmware\include\config.h & compiler firmware
+############################################################
+#ccflags-y += -DCONFIG_SSV_CABRIO_A
+#ccflags-y += -DSDIO_USE_SLOW_CLOCK
+ccflags-y += -DCONFIG_SSV_CABRIO_E
+
+#CONFIG_SSV_SUPPORT_BTCX=y
+
+ccflags-y += -DCONFIG_SSV6200_CLI_ENABLE
+
+#ccflags-y += -DCONFIG_SSV_BUILD_AS_ONE_KO
+
+
+############################################################
+# Options should be able to set as parameters.             #
+############################################################
+
+#PADPD
+#ccflags-y += -DCONFIG_SSV_DPD
+
+#ccflags-y += -DCONFIG_SSV_CABRIO_MB_DEBUG
+
+#ccflags-y += -DCONFIG_SSV6XXX_HW_DEBUG
+
+#SDIO
+ccflags-y += -DCONFIG_SSV_TX_LOWTHRESHOLD
+
+#HCI AGGREGATION
+#ccflags-y += -DCONFIG_SSV_HCI_RX_AGGREGATION
+
+############################################################
+# Rate control update for MPDU.
+############################################################
+ccflags-y += -DRATE_CONTROL_REALTIME_UPDATE
+
+#workaround
+#ccflags-y += -DCONFIG_SSV_CABRIO_EXT_PA
+
+############################################################
+# NOTE:
+#    Only one of the following flags could be turned on.
+# It also turned off the following flags. In this case, 
+# pure software security or pure hardware security is used.
+#
+############################################################
+#ccflags-y += -DCONFIG_SSV_SW_ENCRYPT_HW_DECRYPT
+#ccflags-y += -DCONFIG_SSV_HW_ENCRYPT_SW_DECRYPT
+
+# FOR WFA
+#ccflags-y += -DWIFI_CERTIFIED
+
+#ccflags-y += -DCONFIG_SSV_SDIO_EXT_INT
+
+#######################################################
+ccflags-y += -DCONFIG_SSV6200_HAS_RX_WORKQUEUE
+ccflags-y += -DUSE_THREAD_RX
+ccflags-y += -DUSE_THREAD_TX
+ccflags-y += -DENABLE_AGGREGATE_IN_TIME
+ccflags-y += -DENABLE_INCREMENTAL_AGGREGATION
+
+# Generic decision table applicable to both AP and STA modes.
+ccflags-y += -DUSE_GENERIC_DECI_TBL
+
+########################################################
+## The following definition move to indivdual platform
+## should not enable again here. 
+
+# Use crypto in SSV driver.
+ccflags-y += -DUSE_LOCAL_CRYPTO
+ccflags-y += -DUSE_LOCAL_WEP_CRYPTO
+ccflags-y += -DUSE_LOCAL_TKIP_CRYPTO
+ccflags-y += -DUSE_LOCAL_CCMP_CRYPTO
+ccflags-y += -DUSE_LOCAL_SMS4_CRYPTO
+ccflags-y += -DCONFIG_SSV_WAPI
+ccflags-y += -DHAS_CRYPTO_LOCK
+
+#ccflags-y += -DCONFIG_IRQ_DEBUG_COUNT
+#ccflags-y += -DCONFIG_SSV6XXX_DEBUGFS
+#### end of move to individual platform
+
+
+
+#ccflags-y += -DFW_WSID_WATCH_LIST
+#ccflags-y += -DUSE_BATCH_RX
+#ccflags-y += -DCONFIG_SSV_SUPPORT_AES_ASM
+
+
+ccflags-y += -DSSV6200_ECO
+#ccflags-y += -DENABLE_WAKE_IO_ISR_WHEN_HCI_ENQUEUE
+#ccflags-y += -DENABLE_TX_Q_FLOW_CONTROL
+
+#ccflags-y += -DCONFIG_DEBUG_SKB_TIMESTAMP
+
+
+#enable p2p client to parse GO broadcast noa
+#ccflags-y += -DCONFIG_P2P_NOA
+
+#enable rx management frame check
+#ccflags-y += -DCONFIG_RX_MGMT_CHECK
+
+#enable smart icomm
+
+#ccflags-y += -DCONFIG_SMARTLINK
+#ccflags-y += -DCONFIG_SSV_SMARTLINK
+
+ccflags-y += -DCONFIG_SSV_CCI_IMPROVEMENT
+
+#enable USB LPM function
+#ccflags-y += -DSSV_SUPPORT_USB_LPM
+
diff --git a/drivers/net/wireless/ssv6x5x/cross-android-release.sh b/drivers/net/wireless/ssv6x5x/cross-android-release.sh
new file mode 100755
index 000000000..8cf12a3ff
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/cross-android-release.sh
@@ -0,0 +1,83 @@
+#!/bin/bash
+prompt="Pick the target platform:"
+chip_options=("a33" \
+              "h8" \
+              "h3" \
+              "rk3036" \
+              "rk3126" \
+              "rk3128" \
+              "rk322x" \              
+              "atm7039-action" \
+              "aml-s805" \
+              "aml-s905" \
+              "aml-t950" \
+              "xm-hi3518" \
+              "v66")
+PLATFORM=""
+
+select opt in "${chip_options[@]}" "Quit"; do 
+    case "$REPLY" in
+
+    1 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+    2 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+    3 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+    4 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+    5 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+    6 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+    7 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+    8 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+    9 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+    10 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+    11 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+    12 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+    13 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+
+    $(( ${#chip_options[@]}+1 )) ) echo "Goodbye!"; break;;
+    *) echo "Invalid option. Try another one.";continue;;
+    esac
+done
+
+if [ "$PLATFORM" != "" ]; then
+./ver_info.pl include/ssv_version.h
+
+if [ $? -eq 0 ]; then
+    echo "Please check SVN first !!"
+else
+cp platforms/platform-config.mak .
+cp platforms/$PLATFORM.cfg ssv6x5x.cfg
+cp platforms/$PLATFORM-generic-wlan.c ssv6x5x-generic-wlan.c
+cp platforms/$PLATFORM-wifi.cfg image/ssv6x5x-wifi.cfg
+cp platforms/$PLATFORM-wifi.cfg ssv6x5x-wifi.cfg
+cp Makefile.android Makefile
+
+# Remove garbage
+svn rm wpa_supplicant.conf
+svn rm unload.sh
+svn rm sta.cfg
+svn rm ssvcfg.sh
+svn rm rules.mak
+svn rm remove_old_driver.sh
+svn rm load.sh
+svn rm launch_sta_ap.sh
+svn rm launch_ap_sta.sh
+svn rm config.mak
+svn rm cli
+svn rm clean_log.sh
+svn rm ap_shutdown.sh
+svn rm ap_launch.sh
+svn rm ap_check.sh
+svn rm ap.cfg
+svn rm build.sh
+svn rm linux-build.sh
+svn rm android-build.sh
+svn rm cross-linux-release.sh
+svn rm Makefile.*
+svn rm platforms/* --force
+svn rm platforms --force
+
+echo "Done ko!"
+fi
+else
+echo "Fail!"
+fi
+
diff --git a/drivers/net/wireless/ssv6x5x/cross-linux-release.sh b/drivers/net/wireless/ssv6x5x/cross-linux-release.sh
new file mode 100755
index 000000000..f73df0927
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/cross-linux-release.sh
@@ -0,0 +1,68 @@
+#!/bin/bash
+prompt="Pick the target platform:"
+chip_options=("ak3916" \
+              "x1000" \
+              "t10" \
+              "t20" \
+              "sc6138")
+PLATFORM=""
+
+select opt in "${chip_options[@]}" "Quit"; do 
+    case "$REPLY" in
+
+    1 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+    2 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+    3 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+    4 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+
+    $(( ${#chip_options[@]}+1 )) ) echo "Goodbye!"; break;;
+    *) echo "Invalid option. Try another one.";continue;;
+    esac
+done
+
+if [ "$PLATFORM" != "" ]; then
+./ver_info.pl include/ssv_version.h
+
+if [ $? -eq 0 ]; then
+    echo "Please check SVN first !!"
+else
+cp platforms/platform-config.mak .
+cp platforms/$PLATFORM.cfg ssv6x5x.cfg
+cp platforms/$PLATFORM-wifi.cfg ssv6x5x-wifi.cfg
+cp platforms/$PLATFORM-wifi.cfg image/ssv6x5x-wifi.cfg
+cp platforms/$PLATFORM-generic-wlan.c ssv6x5x-generic-wlan.c
+cp Makefile.cross_linux Makefile
+#sed -i 's,PLATFORMS =,PLATFORMS = '"$PLATFORM"',g' Makefile
+make clean
+
+# Remove garbage
+svn rm wpa_supplicant.conf
+svn rm unload.sh
+svn rm sta.cfg
+svn rm ssvcfg.sh
+svn rm rules.mak
+svn rm remove_old_driver.sh
+svn rm load.sh
+svn rm launch_sta_ap.sh
+svn rm launch_ap_sta.sh
+svn rm config.mak
+svn rm cli
+svn rm clean_log.sh
+svn rm ap_shutdown.sh
+svn rm ap_launch.sh
+svn rm ap_check.sh
+svn rm ap.cfg
+svn rm build.sh
+svn rm linux-build.sh
+svn rm android-build.sh
+svn rm cross-android-release.sh
+svn rm Makefile.* --force
+svn rm platforms/* --force
+svn rm platforms --force
+
+echo "Done ko!"
+fi
+else
+echo "Fail!"
+fi
+
diff --git a/drivers/net/wireless/ssv6x5x/crypto/aes-armv4.S b/drivers/net/wireless/ssv6x5x/crypto/aes-armv4.S
new file mode 100755
index 000000000..e59b1d505
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/crypto/aes-armv4.S
@@ -0,0 +1,1112 @@
+#define __ARM_ARCH__ __LINUX_ARM_ARCH__
+@ ====================================================================
+@ Written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL
+@ project. The module is, however, dual licensed under OpenSSL and
+@ CRYPTOGAMS licenses depending on where you obtain it. For further
+@ details see http://www.openssl.org/~appro/cryptogams/.
+@ ====================================================================
+
+@ AES for ARMv4
+
+@ January 2007.
+@
+@ Code uses single 1K S-box and is >2 times faster than code generated
+@ by gcc-3.4.1. This is thanks to unique feature of ARMv4 ISA, which
+@ allows to merge logical or arithmetic operation with shift or rotate
+@ in one instruction and emit combined result every cycle. The module
+@ is endian-neutral. The performance is ~42 cycles/byte for 128-bit
+@ key [on single-issue Xscale PXA250 core].
+
+@ May 2007.
+@
+@ AES_set_[en|de]crypt_key is added.
+
+@ July 2010.
+@
+@ Rescheduling for dual-issue pipeline resulted in 12% improvement on
+@ Cortex A8 core and ~25 cycles per byte processed with 128-bit key.
+
+@ February 2011.
+@
+@ Profiler-assisted and platform-specific optimization resulted in 16%
+@ improvement on Cortex A8 core and ~21.5 cycles per byte.
+
+@ A little glue here to select the correct code below for the ARM CPU
+@ that is being targetted.
+
+.text
+.code	32
+
+.type	AES_Te,%object
+.align	5
+AES_Te:
+.word	0xc66363a5, 0xf87c7c84, 0xee777799, 0xf67b7b8d
+.word	0xfff2f20d, 0xd66b6bbd, 0xde6f6fb1, 0x91c5c554
+.word	0x60303050, 0x02010103, 0xce6767a9, 0x562b2b7d
+.word	0xe7fefe19, 0xb5d7d762, 0x4dababe6, 0xec76769a
+.word	0x8fcaca45, 0x1f82829d, 0x89c9c940, 0xfa7d7d87
+.word	0xeffafa15, 0xb25959eb, 0x8e4747c9, 0xfbf0f00b
+.word	0x41adadec, 0xb3d4d467, 0x5fa2a2fd, 0x45afafea
+.word	0x239c9cbf, 0x53a4a4f7, 0xe4727296, 0x9bc0c05b
+.word	0x75b7b7c2, 0xe1fdfd1c, 0x3d9393ae, 0x4c26266a
+.word	0x6c36365a, 0x7e3f3f41, 0xf5f7f702, 0x83cccc4f
+.word	0x6834345c, 0x51a5a5f4, 0xd1e5e534, 0xf9f1f108
+.word	0xe2717193, 0xabd8d873, 0x62313153, 0x2a15153f
+.word	0x0804040c, 0x95c7c752, 0x46232365, 0x9dc3c35e
+.word	0x30181828, 0x379696a1, 0x0a05050f, 0x2f9a9ab5
+.word	0x0e070709, 0x24121236, 0x1b80809b, 0xdfe2e23d
+.word	0xcdebeb26, 0x4e272769, 0x7fb2b2cd, 0xea75759f
+.word	0x1209091b, 0x1d83839e, 0x582c2c74, 0x341a1a2e
+.word	0x361b1b2d, 0xdc6e6eb2, 0xb45a5aee, 0x5ba0a0fb
+.word	0xa45252f6, 0x763b3b4d, 0xb7d6d661, 0x7db3b3ce
+.word	0x5229297b, 0xdde3e33e, 0x5e2f2f71, 0x13848497
+.word	0xa65353f5, 0xb9d1d168, 0x00000000, 0xc1eded2c
+.word	0x40202060, 0xe3fcfc1f, 0x79b1b1c8, 0xb65b5bed
+.word	0xd46a6abe, 0x8dcbcb46, 0x67bebed9, 0x7239394b
+.word	0x944a4ade, 0x984c4cd4, 0xb05858e8, 0x85cfcf4a
+.word	0xbbd0d06b, 0xc5efef2a, 0x4faaaae5, 0xedfbfb16
+.word	0x864343c5, 0x9a4d4dd7, 0x66333355, 0x11858594
+.word	0x8a4545cf, 0xe9f9f910, 0x04020206, 0xfe7f7f81
+.word	0xa05050f0, 0x783c3c44, 0x259f9fba, 0x4ba8a8e3
+.word	0xa25151f3, 0x5da3a3fe, 0x804040c0, 0x058f8f8a
+.word	0x3f9292ad, 0x219d9dbc, 0x70383848, 0xf1f5f504
+.word	0x63bcbcdf, 0x77b6b6c1, 0xafdada75, 0x42212163
+.word	0x20101030, 0xe5ffff1a, 0xfdf3f30e, 0xbfd2d26d
+.word	0x81cdcd4c, 0x180c0c14, 0x26131335, 0xc3ecec2f
+.word	0xbe5f5fe1, 0x359797a2, 0x884444cc, 0x2e171739
+.word	0x93c4c457, 0x55a7a7f2, 0xfc7e7e82, 0x7a3d3d47
+.word	0xc86464ac, 0xba5d5de7, 0x3219192b, 0xe6737395
+.word	0xc06060a0, 0x19818198, 0x9e4f4fd1, 0xa3dcdc7f
+.word	0x44222266, 0x542a2a7e, 0x3b9090ab, 0x0b888883
+.word	0x8c4646ca, 0xc7eeee29, 0x6bb8b8d3, 0x2814143c
+.word	0xa7dede79, 0xbc5e5ee2, 0x160b0b1d, 0xaddbdb76
+.word	0xdbe0e03b, 0x64323256, 0x743a3a4e, 0x140a0a1e
+.word	0x924949db, 0x0c06060a, 0x4824246c, 0xb85c5ce4
+.word	0x9fc2c25d, 0xbdd3d36e, 0x43acacef, 0xc46262a6
+.word	0x399191a8, 0x319595a4, 0xd3e4e437, 0xf279798b
+.word	0xd5e7e732, 0x8bc8c843, 0x6e373759, 0xda6d6db7
+.word	0x018d8d8c, 0xb1d5d564, 0x9c4e4ed2, 0x49a9a9e0
+.word	0xd86c6cb4, 0xac5656fa, 0xf3f4f407, 0xcfeaea25
+.word	0xca6565af, 0xf47a7a8e, 0x47aeaee9, 0x10080818
+.word	0x6fbabad5, 0xf0787888, 0x4a25256f, 0x5c2e2e72
+.word	0x381c1c24, 0x57a6a6f1, 0x73b4b4c7, 0x97c6c651
+.word	0xcbe8e823, 0xa1dddd7c, 0xe874749c, 0x3e1f1f21
+.word	0x964b4bdd, 0x61bdbddc, 0x0d8b8b86, 0x0f8a8a85
+.word	0xe0707090, 0x7c3e3e42, 0x71b5b5c4, 0xcc6666aa
+.word	0x904848d8, 0x06030305, 0xf7f6f601, 0x1c0e0e12
+.word	0xc26161a3, 0x6a35355f, 0xae5757f9, 0x69b9b9d0
+.word	0x17868691, 0x99c1c158, 0x3a1d1d27, 0x279e9eb9
+.word	0xd9e1e138, 0xebf8f813, 0x2b9898b3, 0x22111133
+.word	0xd26969bb, 0xa9d9d970, 0x078e8e89, 0x339494a7
+.word	0x2d9b9bb6, 0x3c1e1e22, 0x15878792, 0xc9e9e920
+.word	0x87cece49, 0xaa5555ff, 0x50282878, 0xa5dfdf7a
+.word	0x038c8c8f, 0x59a1a1f8, 0x09898980, 0x1a0d0d17
+.word	0x65bfbfda, 0xd7e6e631, 0x844242c6, 0xd06868b8
+.word	0x824141c3, 0x299999b0, 0x5a2d2d77, 0x1e0f0f11
+.word	0x7bb0b0cb, 0xa85454fc, 0x6dbbbbd6, 0x2c16163a
+@ Te4[256]
+.byte	0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5
+.byte	0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76
+.byte	0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0
+.byte	0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0
+.byte	0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc
+.byte	0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15
+.byte	0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a
+.byte	0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75
+.byte	0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0
+.byte	0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84
+.byte	0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b
+.byte	0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf
+.byte	0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85
+.byte	0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8
+.byte	0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5
+.byte	0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2
+.byte	0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17
+.byte	0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73
+.byte	0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88
+.byte	0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb
+.byte	0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c
+.byte	0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79
+.byte	0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9
+.byte	0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08
+.byte	0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6
+.byte	0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a
+.byte	0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e
+.byte	0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e
+.byte	0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94
+.byte	0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf
+.byte	0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68
+.byte	0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16
+@ rcon[]
+.word	0x01000000, 0x02000000, 0x04000000, 0x08000000
+.word	0x10000000, 0x20000000, 0x40000000, 0x80000000
+.word	0x1B000000, 0x36000000, 0, 0, 0, 0, 0, 0
+.size	AES_Te,.-AES_Te
+
+@ void AES_encrypt(const unsigned char *in, unsigned char *out,
+@ 		 const AES_KEY *key) {
+.global AES_encrypt
+.type   AES_encrypt,%function
+.align	5
+AES_encrypt:
+	sub	r3,pc,#8		@ AES_encrypt
+	stmdb   sp!,{r1,r4-r12,lr}
+	mov	r12,r0		@ inp
+	mov	r11,r2
+	sub	r10,r3,#AES_encrypt-AES_Te	@ Te
+#if __ARM_ARCH__<7
+	ldrb	r0,[r12,#3]	@ load input data in endian-neutral
+	ldrb	r4,[r12,#2]	@ manner...
+	ldrb	r5,[r12,#1]
+	ldrb	r6,[r12,#0]
+	orr	r0,r0,r4,lsl#8
+	ldrb	r1,[r12,#7]
+	orr	r0,r0,r5,lsl#16
+	ldrb	r4,[r12,#6]
+	orr	r0,r0,r6,lsl#24
+	ldrb	r5,[r12,#5]
+	ldrb	r6,[r12,#4]
+	orr	r1,r1,r4,lsl#8
+	ldrb	r2,[r12,#11]
+	orr	r1,r1,r5,lsl#16
+	ldrb	r4,[r12,#10]
+	orr	r1,r1,r6,lsl#24
+	ldrb	r5,[r12,#9]
+	ldrb	r6,[r12,#8]
+	orr	r2,r2,r4,lsl#8
+	ldrb	r3,[r12,#15]
+	orr	r2,r2,r5,lsl#16
+	ldrb	r4,[r12,#14]
+	orr	r2,r2,r6,lsl#24
+	ldrb	r5,[r12,#13]
+	ldrb	r6,[r12,#12]
+	orr	r3,r3,r4,lsl#8
+	orr	r3,r3,r5,lsl#16
+	orr	r3,r3,r6,lsl#24
+#else
+	ldr	r0,[r12,#0]
+	ldr	r1,[r12,#4]
+	ldr	r2,[r12,#8]
+	ldr	r3,[r12,#12]
+#ifdef __ARMEL__
+	rev	r0,r0
+	rev	r1,r1
+	rev	r2,r2
+	rev	r3,r3
+#endif
+#endif
+	bl	_armv4_AES_encrypt
+
+	ldr	r12,[sp],#4		@ pop out
+#if __ARM_ARCH__>=7
+#ifdef __ARMEL__
+	rev	r0,r0
+	rev	r1,r1
+	rev	r2,r2
+	rev	r3,r3
+#endif
+	str	r0,[r12,#0]
+	str	r1,[r12,#4]
+	str	r2,[r12,#8]
+	str	r3,[r12,#12]
+#else
+	mov	r4,r0,lsr#24		@ write output in endian-neutral
+	mov	r5,r0,lsr#16		@ manner...
+	mov	r6,r0,lsr#8
+	strb	r4,[r12,#0]
+	strb	r5,[r12,#1]
+	mov	r4,r1,lsr#24
+	strb	r6,[r12,#2]
+	mov	r5,r1,lsr#16
+	strb	r0,[r12,#3]
+	mov	r6,r1,lsr#8
+	strb	r4,[r12,#4]
+	strb	r5,[r12,#5]
+	mov	r4,r2,lsr#24
+	strb	r6,[r12,#6]
+	mov	r5,r2,lsr#16
+	strb	r1,[r12,#7]
+	mov	r6,r2,lsr#8
+	strb	r4,[r12,#8]
+	strb	r5,[r12,#9]
+	mov	r4,r3,lsr#24
+	strb	r6,[r12,#10]
+	mov	r5,r3,lsr#16
+	strb	r2,[r12,#11]
+	mov	r6,r3,lsr#8
+	strb	r4,[r12,#12]
+	strb	r5,[r12,#13]
+	strb	r6,[r12,#14]
+	strb	r3,[r12,#15]
+#endif
+#if __ARM_ARCH__>=5
+	ldmia	sp!,{r4-r12,pc}
+#else
+	ldmia   sp!,{r4-r12,lr}
+	tst	lr,#1
+	moveq	pc,lr			@ be binary compatible with V4, yet
+	.word	0xe12fff1e			@ interoperable with Thumb ISA:-)
+#endif
+.size	AES_encrypt,.-AES_encrypt
+
+.type   _armv4_AES_encrypt,%function
+.align	2
+_armv4_AES_encrypt:
+	str	lr,[sp,#-4]!		@ push lr
+	ldmia	r11!,{r4-r7}
+	eor	r0,r0,r4
+	ldr	r12,[r11,#240-16]
+	eor	r1,r1,r5
+	eor	r2,r2,r6
+	eor	r3,r3,r7
+	sub	r12,r12,#1
+	mov	lr,#255
+
+	and	r7,lr,r0
+	and	r8,lr,r0,lsr#8
+	and	r9,lr,r0,lsr#16
+	mov	r0,r0,lsr#24
+.Lenc_loop:
+	ldr	r4,[r10,r7,lsl#2]	@ Te3[s0>>0]
+	and	r7,lr,r1,lsr#16	@ i0
+	ldr	r5,[r10,r8,lsl#2]	@ Te2[s0>>8]
+	and	r8,lr,r1
+	ldr	r6,[r10,r9,lsl#2]	@ Te1[s0>>16]
+	and	r9,lr,r1,lsr#8
+	ldr	r0,[r10,r0,lsl#2]	@ Te0[s0>>24]
+	mov	r1,r1,lsr#24
+
+	ldr	r7,[r10,r7,lsl#2]	@ Te1[s1>>16]
+	ldr	r8,[r10,r8,lsl#2]	@ Te3[s1>>0]
+	ldr	r9,[r10,r9,lsl#2]	@ Te2[s1>>8]
+	eor	r0,r0,r7,ror#8
+	ldr	r1,[r10,r1,lsl#2]	@ Te0[s1>>24]
+	and	r7,lr,r2,lsr#8	@ i0
+	eor	r5,r5,r8,ror#8
+	and	r8,lr,r2,lsr#16	@ i1
+	eor	r6,r6,r9,ror#8
+	and	r9,lr,r2
+	ldr	r7,[r10,r7,lsl#2]	@ Te2[s2>>8]
+	eor	r1,r1,r4,ror#24
+	ldr	r8,[r10,r8,lsl#2]	@ Te1[s2>>16]
+	mov	r2,r2,lsr#24
+
+	ldr	r9,[r10,r9,lsl#2]	@ Te3[s2>>0]
+	eor	r0,r0,r7,ror#16
+	ldr	r2,[r10,r2,lsl#2]	@ Te0[s2>>24]
+	and	r7,lr,r3		@ i0
+	eor	r1,r1,r8,ror#8
+	and	r8,lr,r3,lsr#8	@ i1
+	eor	r6,r6,r9,ror#16
+	and	r9,lr,r3,lsr#16	@ i2
+	ldr	r7,[r10,r7,lsl#2]	@ Te3[s3>>0]
+	eor	r2,r2,r5,ror#16
+	ldr	r8,[r10,r8,lsl#2]	@ Te2[s3>>8]
+	mov	r3,r3,lsr#24
+
+	ldr	r9,[r10,r9,lsl#2]	@ Te1[s3>>16]
+	eor	r0,r0,r7,ror#24
+	ldr	r7,[r11],#16
+	eor	r1,r1,r8,ror#16
+	ldr	r3,[r10,r3,lsl#2]	@ Te0[s3>>24]
+	eor	r2,r2,r9,ror#8
+	ldr	r4,[r11,#-12]
+	eor	r3,r3,r6,ror#8
+
+	ldr	r5,[r11,#-8]
+	eor	r0,r0,r7
+	ldr	r6,[r11,#-4]
+	and	r7,lr,r0
+	eor	r1,r1,r4
+	and	r8,lr,r0,lsr#8
+	eor	r2,r2,r5
+	and	r9,lr,r0,lsr#16
+	eor	r3,r3,r6
+	mov	r0,r0,lsr#24
+
+	subs	r12,r12,#1
+	bne	.Lenc_loop
+
+	add	r10,r10,#2
+
+	ldrb	r4,[r10,r7,lsl#2]	@ Te4[s0>>0]
+	and	r7,lr,r1,lsr#16	@ i0
+	ldrb	r5,[r10,r8,lsl#2]	@ Te4[s0>>8]
+	and	r8,lr,r1
+	ldrb	r6,[r10,r9,lsl#2]	@ Te4[s0>>16]
+	and	r9,lr,r1,lsr#8
+	ldrb	r0,[r10,r0,lsl#2]	@ Te4[s0>>24]
+	mov	r1,r1,lsr#24
+
+	ldrb	r7,[r10,r7,lsl#2]	@ Te4[s1>>16]
+	ldrb	r8,[r10,r8,lsl#2]	@ Te4[s1>>0]
+	ldrb	r9,[r10,r9,lsl#2]	@ Te4[s1>>8]
+	eor	r0,r7,r0,lsl#8
+	ldrb	r1,[r10,r1,lsl#2]	@ Te4[s1>>24]
+	and	r7,lr,r2,lsr#8	@ i0
+	eor	r5,r8,r5,lsl#8
+	and	r8,lr,r2,lsr#16	@ i1
+	eor	r6,r9,r6,lsl#8
+	and	r9,lr,r2
+	ldrb	r7,[r10,r7,lsl#2]	@ Te4[s2>>8]
+	eor	r1,r4,r1,lsl#24
+	ldrb	r8,[r10,r8,lsl#2]	@ Te4[s2>>16]
+	mov	r2,r2,lsr#24
+
+	ldrb	r9,[r10,r9,lsl#2]	@ Te4[s2>>0]
+	eor	r0,r7,r0,lsl#8
+	ldrb	r2,[r10,r2,lsl#2]	@ Te4[s2>>24]
+	and	r7,lr,r3		@ i0
+	eor	r1,r1,r8,lsl#16
+	and	r8,lr,r3,lsr#8	@ i1
+	eor	r6,r9,r6,lsl#8
+	and	r9,lr,r3,lsr#16	@ i2
+	ldrb	r7,[r10,r7,lsl#2]	@ Te4[s3>>0]
+	eor	r2,r5,r2,lsl#24
+	ldrb	r8,[r10,r8,lsl#2]	@ Te4[s3>>8]
+	mov	r3,r3,lsr#24
+
+	ldrb	r9,[r10,r9,lsl#2]	@ Te4[s3>>16]
+	eor	r0,r7,r0,lsl#8
+	ldr	r7,[r11,#0]
+	ldrb	r3,[r10,r3,lsl#2]	@ Te4[s3>>24]
+	eor	r1,r1,r8,lsl#8
+	ldr	r4,[r11,#4]
+	eor	r2,r2,r9,lsl#16
+	ldr	r5,[r11,#8]
+	eor	r3,r6,r3,lsl#24
+	ldr	r6,[r11,#12]
+
+	eor	r0,r0,r7
+	eor	r1,r1,r4
+	eor	r2,r2,r5
+	eor	r3,r3,r6
+
+	sub	r10,r10,#2
+	ldr	pc,[sp],#4		@ pop and return
+.size	_armv4_AES_encrypt,.-_armv4_AES_encrypt
+
+.global private_AES_set_encrypt_key
+.type   private_AES_set_encrypt_key,%function
+.align	5
+private_AES_set_encrypt_key:
+_armv4_AES_set_encrypt_key:
+	sub	r3,pc,#8		@ AES_set_encrypt_key
+	teq	r0,#0
+	moveq	r0,#-1
+	beq	.Labrt
+	teq	r2,#0
+	moveq	r0,#-1
+	beq	.Labrt
+
+	teq	r1,#128
+	beq	.Lok
+	teq	r1,#192
+	beq	.Lok
+	teq	r1,#256
+	movne	r0,#-1
+	bne	.Labrt
+
+.Lok:	stmdb   sp!,{r4-r12,lr}
+	sub	r10,r3,#_armv4_AES_set_encrypt_key-AES_Te-1024	@ Te4
+
+	mov	r12,r0		@ inp
+	mov	lr,r1			@ bits
+	mov	r11,r2			@ key
+
+#if __ARM_ARCH__<7
+	ldrb	r0,[r12,#3]	@ load input data in endian-neutral
+	ldrb	r4,[r12,#2]	@ manner...
+	ldrb	r5,[r12,#1]
+	ldrb	r6,[r12,#0]
+	orr	r0,r0,r4,lsl#8
+	ldrb	r1,[r12,#7]
+	orr	r0,r0,r5,lsl#16
+	ldrb	r4,[r12,#6]
+	orr	r0,r0,r6,lsl#24
+	ldrb	r5,[r12,#5]
+	ldrb	r6,[r12,#4]
+	orr	r1,r1,r4,lsl#8
+	ldrb	r2,[r12,#11]
+	orr	r1,r1,r5,lsl#16
+	ldrb	r4,[r12,#10]
+	orr	r1,r1,r6,lsl#24
+	ldrb	r5,[r12,#9]
+	ldrb	r6,[r12,#8]
+	orr	r2,r2,r4,lsl#8
+	ldrb	r3,[r12,#15]
+	orr	r2,r2,r5,lsl#16
+	ldrb	r4,[r12,#14]
+	orr	r2,r2,r6,lsl#24
+	ldrb	r5,[r12,#13]
+	ldrb	r6,[r12,#12]
+	orr	r3,r3,r4,lsl#8
+	str	r0,[r11],#16
+	orr	r3,r3,r5,lsl#16
+	str	r1,[r11,#-12]
+	orr	r3,r3,r6,lsl#24
+	str	r2,[r11,#-8]
+	str	r3,[r11,#-4]
+#else
+	ldr	r0,[r12,#0]
+	ldr	r1,[r12,#4]
+	ldr	r2,[r12,#8]
+	ldr	r3,[r12,#12]
+#ifdef __ARMEL__
+	rev	r0,r0
+	rev	r1,r1
+	rev	r2,r2
+	rev	r3,r3
+#endif
+	str	r0,[r11],#16
+	str	r1,[r11,#-12]
+	str	r2,[r11,#-8]
+	str	r3,[r11,#-4]
+#endif
+
+	teq	lr,#128
+	bne	.Lnot128
+	mov	r12,#10
+	str	r12,[r11,#240-16]
+	add	r6,r10,#256			@ rcon
+	mov	lr,#255
+
+.L128_loop:
+	and	r5,lr,r3,lsr#24
+	and	r7,lr,r3,lsr#16
+	ldrb	r5,[r10,r5]
+	and	r8,lr,r3,lsr#8
+	ldrb	r7,[r10,r7]
+	and	r9,lr,r3
+	ldrb	r8,[r10,r8]
+	orr	r5,r5,r7,lsl#24
+	ldrb	r9,[r10,r9]
+	orr	r5,r5,r8,lsl#16
+	ldr	r4,[r6],#4			@ rcon[i++]
+	orr	r5,r5,r9,lsl#8
+	eor	r5,r5,r4
+	eor	r0,r0,r5			@ rk[4]=rk[0]^...
+	eor	r1,r1,r0			@ rk[5]=rk[1]^rk[4]
+	str	r0,[r11],#16
+	eor	r2,r2,r1			@ rk[6]=rk[2]^rk[5]
+	str	r1,[r11,#-12]
+	eor	r3,r3,r2			@ rk[7]=rk[3]^rk[6]
+	str	r2,[r11,#-8]
+	subs	r12,r12,#1
+	str	r3,[r11,#-4]
+	bne	.L128_loop
+	sub	r2,r11,#176
+	b	.Ldone
+
+.Lnot128:
+#if __ARM_ARCH__<7
+	ldrb	r8,[r12,#19]
+	ldrb	r4,[r12,#18]
+	ldrb	r5,[r12,#17]
+	ldrb	r6,[r12,#16]
+	orr	r8,r8,r4,lsl#8
+	ldrb	r9,[r12,#23]
+	orr	r8,r8,r5,lsl#16
+	ldrb	r4,[r12,#22]
+	orr	r8,r8,r6,lsl#24
+	ldrb	r5,[r12,#21]
+	ldrb	r6,[r12,#20]
+	orr	r9,r9,r4,lsl#8
+	orr	r9,r9,r5,lsl#16
+	str	r8,[r11],#8
+	orr	r9,r9,r6,lsl#24
+	str	r9,[r11,#-4]
+#else
+	ldr	r8,[r12,#16]
+	ldr	r9,[r12,#20]
+#ifdef __ARMEL__
+	rev	r8,r8
+	rev	r9,r9
+#endif
+	str	r8,[r11],#8
+	str	r9,[r11,#-4]
+#endif
+
+	teq	lr,#192
+	bne	.Lnot192
+	mov	r12,#12
+	str	r12,[r11,#240-24]
+	add	r6,r10,#256			@ rcon
+	mov	lr,#255
+	mov	r12,#8
+
+.L192_loop:
+	and	r5,lr,r9,lsr#24
+	and	r7,lr,r9,lsr#16
+	ldrb	r5,[r10,r5]
+	and	r8,lr,r9,lsr#8
+	ldrb	r7,[r10,r7]
+	and	r9,lr,r9
+	ldrb	r8,[r10,r8]
+	orr	r5,r5,r7,lsl#24
+	ldrb	r9,[r10,r9]
+	orr	r5,r5,r8,lsl#16
+	ldr	r4,[r6],#4			@ rcon[i++]
+	orr	r5,r5,r9,lsl#8
+	eor	r9,r5,r4
+	eor	r0,r0,r9			@ rk[6]=rk[0]^...
+	eor	r1,r1,r0			@ rk[7]=rk[1]^rk[6]
+	str	r0,[r11],#24
+	eor	r2,r2,r1			@ rk[8]=rk[2]^rk[7]
+	str	r1,[r11,#-20]
+	eor	r3,r3,r2			@ rk[9]=rk[3]^rk[8]
+	str	r2,[r11,#-16]
+	subs	r12,r12,#1
+	str	r3,[r11,#-12]
+	subeq	r2,r11,#216
+	beq	.Ldone
+
+	ldr	r7,[r11,#-32]
+	ldr	r8,[r11,#-28]
+	eor	r7,r7,r3			@ rk[10]=rk[4]^rk[9]
+	eor	r9,r8,r7			@ rk[11]=rk[5]^rk[10]
+	str	r7,[r11,#-8]
+	str	r9,[r11,#-4]
+	b	.L192_loop
+
+.Lnot192:
+#if __ARM_ARCH__<7
+	ldrb	r8,[r12,#27]
+	ldrb	r4,[r12,#26]
+	ldrb	r5,[r12,#25]
+	ldrb	r6,[r12,#24]
+	orr	r8,r8,r4,lsl#8
+	ldrb	r9,[r12,#31]
+	orr	r8,r8,r5,lsl#16
+	ldrb	r4,[r12,#30]
+	orr	r8,r8,r6,lsl#24
+	ldrb	r5,[r12,#29]
+	ldrb	r6,[r12,#28]
+	orr	r9,r9,r4,lsl#8
+	orr	r9,r9,r5,lsl#16
+	str	r8,[r11],#8
+	orr	r9,r9,r6,lsl#24
+	str	r9,[r11,#-4]
+#else
+	ldr	r8,[r12,#24]
+	ldr	r9,[r12,#28]
+#ifdef __ARMEL__
+	rev	r8,r8
+	rev	r9,r9
+#endif
+	str	r8,[r11],#8
+	str	r9,[r11,#-4]
+#endif
+
+	mov	r12,#14
+	str	r12,[r11,#240-32]
+	add	r6,r10,#256			@ rcon
+	mov	lr,#255
+	mov	r12,#7
+
+.L256_loop:
+	and	r5,lr,r9,lsr#24
+	and	r7,lr,r9,lsr#16
+	ldrb	r5,[r10,r5]
+	and	r8,lr,r9,lsr#8
+	ldrb	r7,[r10,r7]
+	and	r9,lr,r9
+	ldrb	r8,[r10,r8]
+	orr	r5,r5,r7,lsl#24
+	ldrb	r9,[r10,r9]
+	orr	r5,r5,r8,lsl#16
+	ldr	r4,[r6],#4			@ rcon[i++]
+	orr	r5,r5,r9,lsl#8
+	eor	r9,r5,r4
+	eor	r0,r0,r9			@ rk[8]=rk[0]^...
+	eor	r1,r1,r0			@ rk[9]=rk[1]^rk[8]
+	str	r0,[r11],#32
+	eor	r2,r2,r1			@ rk[10]=rk[2]^rk[9]
+	str	r1,[r11,#-28]
+	eor	r3,r3,r2			@ rk[11]=rk[3]^rk[10]
+	str	r2,[r11,#-24]
+	subs	r12,r12,#1
+	str	r3,[r11,#-20]
+	subeq	r2,r11,#256
+	beq	.Ldone
+
+	and	r5,lr,r3
+	and	r7,lr,r3,lsr#8
+	ldrb	r5,[r10,r5]
+	and	r8,lr,r3,lsr#16
+	ldrb	r7,[r10,r7]
+	and	r9,lr,r3,lsr#24
+	ldrb	r8,[r10,r8]
+	orr	r5,r5,r7,lsl#8
+	ldrb	r9,[r10,r9]
+	orr	r5,r5,r8,lsl#16
+	ldr	r4,[r11,#-48]
+	orr	r5,r5,r9,lsl#24
+
+	ldr	r7,[r11,#-44]
+	ldr	r8,[r11,#-40]
+	eor	r4,r4,r5			@ rk[12]=rk[4]^...
+	ldr	r9,[r11,#-36]
+	eor	r7,r7,r4			@ rk[13]=rk[5]^rk[12]
+	str	r4,[r11,#-16]
+	eor	r8,r8,r7			@ rk[14]=rk[6]^rk[13]
+	str	r7,[r11,#-12]
+	eor	r9,r9,r8			@ rk[15]=rk[7]^rk[14]
+	str	r8,[r11,#-8]
+	str	r9,[r11,#-4]
+	b	.L256_loop
+
+.Ldone:	mov	r0,#0
+	ldmia   sp!,{r4-r12,lr}
+.Labrt:	tst	lr,#1
+	moveq	pc,lr			@ be binary compatible with V4, yet
+	.word	0xe12fff1e			@ interoperable with Thumb ISA:-)
+.size	private_AES_set_encrypt_key,.-private_AES_set_encrypt_key
+
+.global private_AES_set_decrypt_key
+.type   private_AES_set_decrypt_key,%function
+.align	5
+private_AES_set_decrypt_key:
+	str	lr,[sp,#-4]!            @ push lr
+#if 0
+	@ kernel does both of these in setkey so optimise this bit out by
+	@ expecting the key to already have the enc_key work done (see aes_glue.c)
+	bl	_armv4_AES_set_encrypt_key
+#else
+	mov	r0,#0
+#endif
+	teq	r0,#0
+	ldrne	lr,[sp],#4              @ pop lr
+	bne	.Labrt
+
+	stmdb   sp!,{r4-r12}
+
+	ldr	r12,[r2,#240]	@ AES_set_encrypt_key preserves r2,
+	mov	r11,r2			@ which is AES_KEY *key
+	mov	r7,r2
+	add	r8,r2,r12,lsl#4
+
+.Linv:	ldr	r0,[r7]
+	ldr	r1,[r7,#4]
+	ldr	r2,[r7,#8]
+	ldr	r3,[r7,#12]
+	ldr	r4,[r8]
+	ldr	r5,[r8,#4]
+	ldr	r6,[r8,#8]
+	ldr	r9,[r8,#12]
+	str	r0,[r8],#-16
+	str	r1,[r8,#16+4]
+	str	r2,[r8,#16+8]
+	str	r3,[r8,#16+12]
+	str	r4,[r7],#16
+	str	r5,[r7,#-12]
+	str	r6,[r7,#-8]
+	str	r9,[r7,#-4]
+	teq	r7,r8
+	bne	.Linv
+	ldr	r0,[r11,#16]!		@ prefetch tp1
+	mov	r7,#0x80
+	mov	r8,#0x1b
+	orr	r7,r7,#0x8000
+	orr	r8,r8,#0x1b00
+	orr	r7,r7,r7,lsl#16
+	orr	r8,r8,r8,lsl#16
+	sub	r12,r12,#1
+	mvn	r9,r7
+	mov	r12,r12,lsl#2	@ (rounds-1)*4
+
+.Lmix:	and	r4,r0,r7
+	and	r1,r0,r9
+	sub	r4,r4,r4,lsr#7
+	and	r4,r4,r8
+	eor	r1,r4,r1,lsl#1	@ tp2
+
+	and	r4,r1,r7
+	and	r2,r1,r9
+	sub	r4,r4,r4,lsr#7
+	and	r4,r4,r8
+	eor	r2,r4,r2,lsl#1	@ tp4
+
+	and	r4,r2,r7
+	and	r3,r2,r9
+	sub	r4,r4,r4,lsr#7
+	and	r4,r4,r8
+	eor	r3,r4,r3,lsl#1	@ tp8
+
+	eor	r4,r1,r2
+	eor	r5,r0,r3		@ tp9
+	eor	r4,r4,r3		@ tpe
+	eor	r4,r4,r1,ror#24
+	eor	r4,r4,r5,ror#24	@ ^= ROTATE(tpb=tp9^tp2,8)
+	eor	r4,r4,r2,ror#16
+	eor	r4,r4,r5,ror#16	@ ^= ROTATE(tpd=tp9^tp4,16)
+	eor	r4,r4,r5,ror#8	@ ^= ROTATE(tp9,24)
+
+	ldr	r0,[r11,#4]		@ prefetch tp1
+	str	r4,[r11],#4
+	subs	r12,r12,#1
+	bne	.Lmix
+
+	mov	r0,#0
+#if __ARM_ARCH__>=5
+	ldmia	sp!,{r4-r12,pc}
+#else
+	ldmia   sp!,{r4-r12,lr}
+	tst	lr,#1
+	moveq	pc,lr			@ be binary compatible with V4, yet
+	.word	0xe12fff1e			@ interoperable with Thumb ISA:-)
+#endif
+.size	private_AES_set_decrypt_key,.-private_AES_set_decrypt_key
+
+.type	AES_Td,%object
+.align	5
+AES_Td:
+.word	0x51f4a750, 0x7e416553, 0x1a17a4c3, 0x3a275e96
+.word	0x3bab6bcb, 0x1f9d45f1, 0xacfa58ab, 0x4be30393
+.word	0x2030fa55, 0xad766df6, 0x88cc7691, 0xf5024c25
+.word	0x4fe5d7fc, 0xc52acbd7, 0x26354480, 0xb562a38f
+.word	0xdeb15a49, 0x25ba1b67, 0x45ea0e98, 0x5dfec0e1
+.word	0xc32f7502, 0x814cf012, 0x8d4697a3, 0x6bd3f9c6
+.word	0x038f5fe7, 0x15929c95, 0xbf6d7aeb, 0x955259da
+.word	0xd4be832d, 0x587421d3, 0x49e06929, 0x8ec9c844
+.word	0x75c2896a, 0xf48e7978, 0x99583e6b, 0x27b971dd
+.word	0xbee14fb6, 0xf088ad17, 0xc920ac66, 0x7dce3ab4
+.word	0x63df4a18, 0xe51a3182, 0x97513360, 0x62537f45
+.word	0xb16477e0, 0xbb6bae84, 0xfe81a01c, 0xf9082b94
+.word	0x70486858, 0x8f45fd19, 0x94de6c87, 0x527bf8b7
+.word	0xab73d323, 0x724b02e2, 0xe31f8f57, 0x6655ab2a
+.word	0xb2eb2807, 0x2fb5c203, 0x86c57b9a, 0xd33708a5
+.word	0x302887f2, 0x23bfa5b2, 0x02036aba, 0xed16825c
+.word	0x8acf1c2b, 0xa779b492, 0xf307f2f0, 0x4e69e2a1
+.word	0x65daf4cd, 0x0605bed5, 0xd134621f, 0xc4a6fe8a
+.word	0x342e539d, 0xa2f355a0, 0x058ae132, 0xa4f6eb75
+.word	0x0b83ec39, 0x4060efaa, 0x5e719f06, 0xbd6e1051
+.word	0x3e218af9, 0x96dd063d, 0xdd3e05ae, 0x4de6bd46
+.word	0x91548db5, 0x71c45d05, 0x0406d46f, 0x605015ff
+.word	0x1998fb24, 0xd6bde997, 0x894043cc, 0x67d99e77
+.word	0xb0e842bd, 0x07898b88, 0xe7195b38, 0x79c8eedb
+.word	0xa17c0a47, 0x7c420fe9, 0xf8841ec9, 0x00000000
+.word	0x09808683, 0x322bed48, 0x1e1170ac, 0x6c5a724e
+.word	0xfd0efffb, 0x0f853856, 0x3daed51e, 0x362d3927
+.word	0x0a0fd964, 0x685ca621, 0x9b5b54d1, 0x24362e3a
+.word	0x0c0a67b1, 0x9357e70f, 0xb4ee96d2, 0x1b9b919e
+.word	0x80c0c54f, 0x61dc20a2, 0x5a774b69, 0x1c121a16
+.word	0xe293ba0a, 0xc0a02ae5, 0x3c22e043, 0x121b171d
+.word	0x0e090d0b, 0xf28bc7ad, 0x2db6a8b9, 0x141ea9c8
+.word	0x57f11985, 0xaf75074c, 0xee99ddbb, 0xa37f60fd
+.word	0xf701269f, 0x5c72f5bc, 0x44663bc5, 0x5bfb7e34
+.word	0x8b432976, 0xcb23c6dc, 0xb6edfc68, 0xb8e4f163
+.word	0xd731dcca, 0x42638510, 0x13972240, 0x84c61120
+.word	0x854a247d, 0xd2bb3df8, 0xaef93211, 0xc729a16d
+.word	0x1d9e2f4b, 0xdcb230f3, 0x0d8652ec, 0x77c1e3d0
+.word	0x2bb3166c, 0xa970b999, 0x119448fa, 0x47e96422
+.word	0xa8fc8cc4, 0xa0f03f1a, 0x567d2cd8, 0x223390ef
+.word	0x87494ec7, 0xd938d1c1, 0x8ccaa2fe, 0x98d40b36
+.word	0xa6f581cf, 0xa57ade28, 0xdab78e26, 0x3fadbfa4
+.word	0x2c3a9de4, 0x5078920d, 0x6a5fcc9b, 0x547e4662
+.word	0xf68d13c2, 0x90d8b8e8, 0x2e39f75e, 0x82c3aff5
+.word	0x9f5d80be, 0x69d0937c, 0x6fd52da9, 0xcf2512b3
+.word	0xc8ac993b, 0x10187da7, 0xe89c636e, 0xdb3bbb7b
+.word	0xcd267809, 0x6e5918f4, 0xec9ab701, 0x834f9aa8
+.word	0xe6956e65, 0xaaffe67e, 0x21bccf08, 0xef15e8e6
+.word	0xbae79bd9, 0x4a6f36ce, 0xea9f09d4, 0x29b07cd6
+.word	0x31a4b2af, 0x2a3f2331, 0xc6a59430, 0x35a266c0
+.word	0x744ebc37, 0xfc82caa6, 0xe090d0b0, 0x33a7d815
+.word	0xf104984a, 0x41ecdaf7, 0x7fcd500e, 0x1791f62f
+.word	0x764dd68d, 0x43efb04d, 0xccaa4d54, 0xe49604df
+.word	0x9ed1b5e3, 0x4c6a881b, 0xc12c1fb8, 0x4665517f
+.word	0x9d5eea04, 0x018c355d, 0xfa877473, 0xfb0b412e
+.word	0xb3671d5a, 0x92dbd252, 0xe9105633, 0x6dd64713
+.word	0x9ad7618c, 0x37a10c7a, 0x59f8148e, 0xeb133c89
+.word	0xcea927ee, 0xb761c935, 0xe11ce5ed, 0x7a47b13c
+.word	0x9cd2df59, 0x55f2733f, 0x1814ce79, 0x73c737bf
+.word	0x53f7cdea, 0x5ffdaa5b, 0xdf3d6f14, 0x7844db86
+.word	0xcaaff381, 0xb968c43e, 0x3824342c, 0xc2a3405f
+.word	0x161dc372, 0xbce2250c, 0x283c498b, 0xff0d9541
+.word	0x39a80171, 0x080cb3de, 0xd8b4e49c, 0x6456c190
+.word	0x7bcb8461, 0xd532b670, 0x486c5c74, 0xd0b85742
+@ Td4[256]
+.byte	0x52, 0x09, 0x6a, 0xd5, 0x30, 0x36, 0xa5, 0x38
+.byte	0xbf, 0x40, 0xa3, 0x9e, 0x81, 0xf3, 0xd7, 0xfb
+.byte	0x7c, 0xe3, 0x39, 0x82, 0x9b, 0x2f, 0xff, 0x87
+.byte	0x34, 0x8e, 0x43, 0x44, 0xc4, 0xde, 0xe9, 0xcb
+.byte	0x54, 0x7b, 0x94, 0x32, 0xa6, 0xc2, 0x23, 0x3d
+.byte	0xee, 0x4c, 0x95, 0x0b, 0x42, 0xfa, 0xc3, 0x4e
+.byte	0x08, 0x2e, 0xa1, 0x66, 0x28, 0xd9, 0x24, 0xb2
+.byte	0x76, 0x5b, 0xa2, 0x49, 0x6d, 0x8b, 0xd1, 0x25
+.byte	0x72, 0xf8, 0xf6, 0x64, 0x86, 0x68, 0x98, 0x16
+.byte	0xd4, 0xa4, 0x5c, 0xcc, 0x5d, 0x65, 0xb6, 0x92
+.byte	0x6c, 0x70, 0x48, 0x50, 0xfd, 0xed, 0xb9, 0xda
+.byte	0x5e, 0x15, 0x46, 0x57, 0xa7, 0x8d, 0x9d, 0x84
+.byte	0x90, 0xd8, 0xab, 0x00, 0x8c, 0xbc, 0xd3, 0x0a
+.byte	0xf7, 0xe4, 0x58, 0x05, 0xb8, 0xb3, 0x45, 0x06
+.byte	0xd0, 0x2c, 0x1e, 0x8f, 0xca, 0x3f, 0x0f, 0x02
+.byte	0xc1, 0xaf, 0xbd, 0x03, 0x01, 0x13, 0x8a, 0x6b
+.byte	0x3a, 0x91, 0x11, 0x41, 0x4f, 0x67, 0xdc, 0xea
+.byte	0x97, 0xf2, 0xcf, 0xce, 0xf0, 0xb4, 0xe6, 0x73
+.byte	0x96, 0xac, 0x74, 0x22, 0xe7, 0xad, 0x35, 0x85
+.byte	0xe2, 0xf9, 0x37, 0xe8, 0x1c, 0x75, 0xdf, 0x6e
+.byte	0x47, 0xf1, 0x1a, 0x71, 0x1d, 0x29, 0xc5, 0x89
+.byte	0x6f, 0xb7, 0x62, 0x0e, 0xaa, 0x18, 0xbe, 0x1b
+.byte	0xfc, 0x56, 0x3e, 0x4b, 0xc6, 0xd2, 0x79, 0x20
+.byte	0x9a, 0xdb, 0xc0, 0xfe, 0x78, 0xcd, 0x5a, 0xf4
+.byte	0x1f, 0xdd, 0xa8, 0x33, 0x88, 0x07, 0xc7, 0x31
+.byte	0xb1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xec, 0x5f
+.byte	0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d
+.byte	0x2d, 0xe5, 0x7a, 0x9f, 0x93, 0xc9, 0x9c, 0xef
+.byte	0xa0, 0xe0, 0x3b, 0x4d, 0xae, 0x2a, 0xf5, 0xb0
+.byte	0xc8, 0xeb, 0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61
+.byte	0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26
+.byte	0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d
+.size	AES_Td,.-AES_Td
+
+@ void AES_decrypt(const unsigned char *in, unsigned char *out,
+@ 		 const AES_KEY *key) {
+.global AES_decrypt
+.type   AES_decrypt,%function
+.align	5
+AES_decrypt:
+	sub	r3,pc,#8		@ AES_decrypt
+	stmdb   sp!,{r1,r4-r12,lr}
+	mov	r12,r0		@ inp
+	mov	r11,r2
+	sub	r10,r3,#AES_decrypt-AES_Td		@ Td
+#if __ARM_ARCH__<7
+	ldrb	r0,[r12,#3]	@ load input data in endian-neutral
+	ldrb	r4,[r12,#2]	@ manner...
+	ldrb	r5,[r12,#1]
+	ldrb	r6,[r12,#0]
+	orr	r0,r0,r4,lsl#8
+	ldrb	r1,[r12,#7]
+	orr	r0,r0,r5,lsl#16
+	ldrb	r4,[r12,#6]
+	orr	r0,r0,r6,lsl#24
+	ldrb	r5,[r12,#5]
+	ldrb	r6,[r12,#4]
+	orr	r1,r1,r4,lsl#8
+	ldrb	r2,[r12,#11]
+	orr	r1,r1,r5,lsl#16
+	ldrb	r4,[r12,#10]
+	orr	r1,r1,r6,lsl#24
+	ldrb	r5,[r12,#9]
+	ldrb	r6,[r12,#8]
+	orr	r2,r2,r4,lsl#8
+	ldrb	r3,[r12,#15]
+	orr	r2,r2,r5,lsl#16
+	ldrb	r4,[r12,#14]
+	orr	r2,r2,r6,lsl#24
+	ldrb	r5,[r12,#13]
+	ldrb	r6,[r12,#12]
+	orr	r3,r3,r4,lsl#8
+	orr	r3,r3,r5,lsl#16
+	orr	r3,r3,r6,lsl#24
+#else
+	ldr	r0,[r12,#0]
+	ldr	r1,[r12,#4]
+	ldr	r2,[r12,#8]
+	ldr	r3,[r12,#12]
+#ifdef __ARMEL__
+	rev	r0,r0
+	rev	r1,r1
+	rev	r2,r2
+	rev	r3,r3
+#endif
+#endif
+	bl	_armv4_AES_decrypt
+
+	ldr	r12,[sp],#4		@ pop out
+#if __ARM_ARCH__>=7
+#ifdef __ARMEL__
+	rev	r0,r0
+	rev	r1,r1
+	rev	r2,r2
+	rev	r3,r3
+#endif
+	str	r0,[r12,#0]
+	str	r1,[r12,#4]
+	str	r2,[r12,#8]
+	str	r3,[r12,#12]
+#else
+	mov	r4,r0,lsr#24		@ write output in endian-neutral
+	mov	r5,r0,lsr#16		@ manner...
+	mov	r6,r0,lsr#8
+	strb	r4,[r12,#0]
+	strb	r5,[r12,#1]
+	mov	r4,r1,lsr#24
+	strb	r6,[r12,#2]
+	mov	r5,r1,lsr#16
+	strb	r0,[r12,#3]
+	mov	r6,r1,lsr#8
+	strb	r4,[r12,#4]
+	strb	r5,[r12,#5]
+	mov	r4,r2,lsr#24
+	strb	r6,[r12,#6]
+	mov	r5,r2,lsr#16
+	strb	r1,[r12,#7]
+	mov	r6,r2,lsr#8
+	strb	r4,[r12,#8]
+	strb	r5,[r12,#9]
+	mov	r4,r3,lsr#24
+	strb	r6,[r12,#10]
+	mov	r5,r3,lsr#16
+	strb	r2,[r12,#11]
+	mov	r6,r3,lsr#8
+	strb	r4,[r12,#12]
+	strb	r5,[r12,#13]
+	strb	r6,[r12,#14]
+	strb	r3,[r12,#15]
+#endif
+#if __ARM_ARCH__>=5
+	ldmia	sp!,{r4-r12,pc}
+#else
+	ldmia   sp!,{r4-r12,lr}
+	tst	lr,#1
+	moveq	pc,lr			@ be binary compatible with V4, yet
+	.word	0xe12fff1e			@ interoperable with Thumb ISA:-)
+#endif
+.size	AES_decrypt,.-AES_decrypt
+
+.type   _armv4_AES_decrypt,%function
+.align	2
+_armv4_AES_decrypt:
+	str	lr,[sp,#-4]!		@ push lr
+	ldmia	r11!,{r4-r7}
+	eor	r0,r0,r4
+	ldr	r12,[r11,#240-16]
+	eor	r1,r1,r5
+	eor	r2,r2,r6
+	eor	r3,r3,r7
+	sub	r12,r12,#1
+	mov	lr,#255
+
+	and	r7,lr,r0,lsr#16
+	and	r8,lr,r0,lsr#8
+	and	r9,lr,r0
+	mov	r0,r0,lsr#24
+.Ldec_loop:
+	ldr	r4,[r10,r7,lsl#2]	@ Td1[s0>>16]
+	and	r7,lr,r1		@ i0
+	ldr	r5,[r10,r8,lsl#2]	@ Td2[s0>>8]
+	and	r8,lr,r1,lsr#16
+	ldr	r6,[r10,r9,lsl#2]	@ Td3[s0>>0]
+	and	r9,lr,r1,lsr#8
+	ldr	r0,[r10,r0,lsl#2]	@ Td0[s0>>24]
+	mov	r1,r1,lsr#24
+
+	ldr	r7,[r10,r7,lsl#2]	@ Td3[s1>>0]
+	ldr	r8,[r10,r8,lsl#2]	@ Td1[s1>>16]
+	ldr	r9,[r10,r9,lsl#2]	@ Td2[s1>>8]
+	eor	r0,r0,r7,ror#24
+	ldr	r1,[r10,r1,lsl#2]	@ Td0[s1>>24]
+	and	r7,lr,r2,lsr#8	@ i0
+	eor	r5,r8,r5,ror#8
+	and	r8,lr,r2		@ i1
+	eor	r6,r9,r6,ror#8
+	and	r9,lr,r2,lsr#16
+	ldr	r7,[r10,r7,lsl#2]	@ Td2[s2>>8]
+	eor	r1,r1,r4,ror#8
+	ldr	r8,[r10,r8,lsl#2]	@ Td3[s2>>0]
+	mov	r2,r2,lsr#24
+
+	ldr	r9,[r10,r9,lsl#2]	@ Td1[s2>>16]
+	eor	r0,r0,r7,ror#16
+	ldr	r2,[r10,r2,lsl#2]	@ Td0[s2>>24]
+	and	r7,lr,r3,lsr#16	@ i0
+	eor	r1,r1,r8,ror#24
+	and	r8,lr,r3,lsr#8	@ i1
+	eor	r6,r9,r6,ror#8
+	and	r9,lr,r3		@ i2
+	ldr	r7,[r10,r7,lsl#2]	@ Td1[s3>>16]
+	eor	r2,r2,r5,ror#8
+	ldr	r8,[r10,r8,lsl#2]	@ Td2[s3>>8]
+	mov	r3,r3,lsr#24
+
+	ldr	r9,[r10,r9,lsl#2]	@ Td3[s3>>0]
+	eor	r0,r0,r7,ror#8
+	ldr	r7,[r11],#16
+	eor	r1,r1,r8,ror#16
+	ldr	r3,[r10,r3,lsl#2]	@ Td0[s3>>24]
+	eor	r2,r2,r9,ror#24
+
+	ldr	r4,[r11,#-12]
+	eor	r0,r0,r7
+	ldr	r5,[r11,#-8]
+	eor	r3,r3,r6,ror#8
+	ldr	r6,[r11,#-4]
+	and	r7,lr,r0,lsr#16
+	eor	r1,r1,r4
+	and	r8,lr,r0,lsr#8
+	eor	r2,r2,r5
+	and	r9,lr,r0
+	eor	r3,r3,r6
+	mov	r0,r0,lsr#24
+
+	subs	r12,r12,#1
+	bne	.Ldec_loop
+
+	add	r10,r10,#1024
+
+	ldr	r5,[r10,#0]		@ prefetch Td4
+	ldr	r6,[r10,#32]
+	ldr	r4,[r10,#64]
+	ldr	r5,[r10,#96]
+	ldr	r6,[r10,#128]
+	ldr	r4,[r10,#160]
+	ldr	r5,[r10,#192]
+	ldr	r6,[r10,#224]
+
+	ldrb	r0,[r10,r0]		@ Td4[s0>>24]
+	ldrb	r4,[r10,r7]		@ Td4[s0>>16]
+	and	r7,lr,r1		@ i0
+	ldrb	r5,[r10,r8]		@ Td4[s0>>8]
+	and	r8,lr,r1,lsr#16
+	ldrb	r6,[r10,r9]		@ Td4[s0>>0]
+	and	r9,lr,r1,lsr#8
+
+	ldrb	r7,[r10,r7]		@ Td4[s1>>0]
+	ldrb	r1,[r10,r1,lsr#24]	@ Td4[s1>>24]
+	ldrb	r8,[r10,r8]		@ Td4[s1>>16]
+	eor	r0,r7,r0,lsl#24
+	ldrb	r9,[r10,r9]		@ Td4[s1>>8]
+	eor	r1,r4,r1,lsl#8
+	and	r7,lr,r2,lsr#8	@ i0
+	eor	r5,r5,r8,lsl#8
+	and	r8,lr,r2		@ i1
+	ldrb	r7,[r10,r7]		@ Td4[s2>>8]
+	eor	r6,r6,r9,lsl#8
+	ldrb	r8,[r10,r8]		@ Td4[s2>>0]
+	and	r9,lr,r2,lsr#16
+
+	ldrb	r2,[r10,r2,lsr#24]	@ Td4[s2>>24]
+	eor	r0,r0,r7,lsl#8
+	ldrb	r9,[r10,r9]		@ Td4[s2>>16]
+	eor	r1,r8,r1,lsl#16
+	and	r7,lr,r3,lsr#16	@ i0
+	eor	r2,r5,r2,lsl#16
+	and	r8,lr,r3,lsr#8	@ i1
+	ldrb	r7,[r10,r7]		@ Td4[s3>>16]
+	eor	r6,r6,r9,lsl#16
+	ldrb	r8,[r10,r8]		@ Td4[s3>>8]
+	and	r9,lr,r3		@ i2
+
+	ldrb	r9,[r10,r9]		@ Td4[s3>>0]
+	ldrb	r3,[r10,r3,lsr#24]	@ Td4[s3>>24]
+	eor	r0,r0,r7,lsl#16
+	ldr	r7,[r11,#0]
+	eor	r1,r1,r8,lsl#8
+	ldr	r4,[r11,#4]
+	eor	r2,r9,r2,lsl#8
+	ldr	r5,[r11,#8]
+	eor	r3,r6,r3,lsl#24
+	ldr	r6,[r11,#12]
+
+	eor	r0,r0,r7
+	eor	r1,r1,r4
+	eor	r2,r2,r5
+	eor	r3,r3,r6
+
+	sub	r10,r10,#1024
+	ldr	pc,[sp],#4		@ pop and return
+.size	_armv4_AES_decrypt,.-_armv4_AES_decrypt
+.asciz	"AES for ARMv4, CRYPTOGAMS by <appro@openssl.org>"
+.align	2
diff --git a/drivers/net/wireless/ssv6x5x/crypto/aes_glue.c b/drivers/net/wireless/ssv6x5x/crypto/aes_glue.c
new file mode 100644
index 000000000..3c510e618
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/crypto/aes_glue.c
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/module.h>
+#include <linux/crypto.h>
+#include <crypto/aes.h>
+#define AES_MAXNR 14
+typedef struct {
+    unsigned int rd_key[4 *(AES_MAXNR + 1)];
+    int rounds;
+} AES_KEY;
+struct AES_CTX {
+    AES_KEY enc_key;
+    AES_KEY dec_key;
+};
+asmlinkage void AES_encrypt(const u8 *in, u8 *out, AES_KEY *ctx);
+asmlinkage void AES_decrypt(const u8 *in, u8 *out, AES_KEY *ctx);
+asmlinkage int private_AES_set_decrypt_key(const unsigned char *userKey, const int bits, AES_KEY *key);
+asmlinkage int private_AES_set_encrypt_key(const unsigned char *userKey, const int bits, AES_KEY *key);
+static void aes_encrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
+{
+    struct AES_CTX *ctx = crypto_tfm_ctx(tfm);
+    AES_encrypt(src, dst, &ctx->enc_key);
+}
+static void aes_decrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
+{
+    struct AES_CTX *ctx = crypto_tfm_ctx(tfm);
+    AES_decrypt(src, dst, &ctx->dec_key);
+}
+static int aes_set_key(struct crypto_tfm *tfm, const u8 *in_key,
+                       unsigned int key_len)
+{
+    struct AES_CTX *ctx = crypto_tfm_ctx(tfm);
+    switch (key_len) {
+    case AES_KEYSIZE_128:
+        key_len = 128;
+        break;
+    case AES_KEYSIZE_192:
+        key_len = 192;
+        break;
+    case AES_KEYSIZE_256:
+        key_len = 256;
+        break;
+    default:
+        tfm->crt_flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
+        return -EINVAL;
+    }
+    if (private_AES_set_encrypt_key(in_key, key_len, &ctx->enc_key) == -1) {
+        tfm->crt_flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
+        return -EINVAL;
+    }
+    ctx->dec_key = ctx->enc_key;
+    if (private_AES_set_decrypt_key(in_key, key_len, &ctx->dec_key) == -1) {
+        tfm->crt_flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
+        return -EINVAL;
+    }
+    return 0;
+}
+static struct crypto_alg aes_alg = {
+    .cra_name = "aes",
+    .cra_driver_name = "aes-asm",
+    .cra_priority = 200,
+    .cra_flags = CRYPTO_ALG_TYPE_CIPHER,
+    .cra_blocksize = AES_BLOCK_SIZE,
+    .cra_ctxsize = sizeof(struct AES_CTX),
+    .cra_module = THIS_MODULE,
+    .cra_list = LIST_HEAD_INIT(aes_alg.cra_list),
+    .cra_u = {
+        .cipher = {
+            .cia_min_keysize = AES_MIN_KEY_SIZE,
+            .cia_max_keysize = AES_MAX_KEY_SIZE,
+            .cia_setkey = aes_set_key,
+            .cia_encrypt = aes_encrypt,
+            .cia_decrypt = aes_decrypt
+        }
+    }
+};
+int aes_init(void)
+{
+    return crypto_register_alg(&aes_alg);
+}
+void aes_fini(void)
+{
+    crypto_unregister_alg(&aes_alg);
+}
diff --git a/drivers/net/wireless/ssv6x5x/crypto/sha1-armv4-large.S b/drivers/net/wireless/ssv6x5x/crypto/sha1-armv4-large.S
new file mode 100755
index 000000000..7050ab133
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/crypto/sha1-armv4-large.S
@@ -0,0 +1,503 @@
+#define __ARM_ARCH__ __LINUX_ARM_ARCH__
+@ ====================================================================
+@ Written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL
+@ project. The module is, however, dual licensed under OpenSSL and
+@ CRYPTOGAMS licenses depending on where you obtain it. For further
+@ details see http://www.openssl.org/~appro/cryptogams/.
+@ ====================================================================
+
+@ sha1_block procedure for ARMv4.
+@
+@ January 2007.
+
+@ Size/performance trade-off
+@ ====================================================================
+@ impl		size in bytes	comp cycles[*]	measured performance
+@ ====================================================================
+@ thumb		304		3212		4420
+@ armv4-small	392/+29%	1958/+64%	2250/+96%
+@ armv4-compact	740/+89%	1552/+26%	1840/+22%
+@ armv4-large	1420/+92%	1307/+19%	1370/+34%[***]
+@ full unroll	~5100/+260%	~1260/+4%	~1300/+5%
+@ ====================================================================
+@ thumb		= same as 'small' but in Thumb instructions[**] and
+@		  with recurring code in two private functions;
+@ small		= detached Xload/update, loops are folded;
+@ compact	= detached Xload/update, 5x unroll;
+@ large		= interleaved Xload/update, 5x unroll;
+@ full unroll	= interleaved Xload/update, full unroll, estimated[!];
+@
+@ [*]	Manually counted instructions in "grand" loop body. Measured
+@	performance is affected by prologue and epilogue overhead,
+@	i-cache availability, branch penalties, etc.
+@ [**]	While each Thumb instruction is twice smaller, they are not as
+@	diverse as ARM ones: e.g., there are only two arithmetic
+@	instructions with 3 arguments, no [fixed] rotate, addressing
+@	modes are limited. As result it takes more instructions to do
+@	the same job in Thumb, therefore the code is never twice as
+@	small and always slower.
+@ [***]	which is also ~35% better than compiler generated code. Dual-
+@	issue Cortex A8 core was measured to process input block in
+@	~990 cycles.
+
+@ August 2010.
+@
+@ Rescheduling for dual-issue pipeline resulted in 13% improvement on
+@ Cortex A8 core and in absolute terms ~870 cycles per input block
+@ [or 13.6 cycles per byte].
+
+@ February 2011.
+@
+@ Profiler-assisted and platform-specific optimization resulted in 10%
+@ improvement on Cortex A8 core and 12.2 cycles per byte.
+
+.text
+
+.global	sha1_block_data_order
+.type	sha1_block_data_order,%function
+
+.align	2
+sha1_block_data_order:
+	stmdb	sp!,{r4-r12,lr}
+	add	r2,r1,r2,lsl#6	@ r2 to point at the end of r1
+	ldmia	r0,{r3,r4,r5,r6,r7}
+.Lloop:
+	ldr	r8,.LK_00_19
+	mov	r14,sp
+	sub	sp,sp,#15*4
+	mov	r5,r5,ror#30
+	mov	r6,r6,ror#30
+	mov	r7,r7,ror#30		@ [6]
+.L_00_15:
+#if __ARM_ARCH__<7
+	ldrb	r10,[r1,#2]
+	ldrb	r9,[r1,#3]
+	ldrb	r11,[r1,#1]
+	add	r7,r8,r7,ror#2			@ E+=K_00_19
+	ldrb	r12,[r1],#4
+	orr	r9,r9,r10,lsl#8
+	eor	r10,r5,r6			@ F_xx_xx
+	orr	r9,r9,r11,lsl#16
+	add	r7,r7,r3,ror#27			@ E+=ROR(A,27)
+	orr	r9,r9,r12,lsl#24
+#else
+	ldr	r9,[r1],#4			@ handles unaligned
+	add	r7,r8,r7,ror#2			@ E+=K_00_19
+	eor	r10,r5,r6			@ F_xx_xx
+	add	r7,r7,r3,ror#27			@ E+=ROR(A,27)
+#ifdef __ARMEL__
+	rev	r9,r9				@ byte swap
+#endif
+#endif
+	and	r10,r4,r10,ror#2
+	add	r7,r7,r9			@ E+=X[i]
+	eor	r10,r10,r6,ror#2		@ F_00_19(B,C,D)
+	str	r9,[r14,#-4]!
+	add	r7,r7,r10			@ E+=F_00_19(B,C,D)
+#if __ARM_ARCH__<7
+	ldrb	r10,[r1,#2]
+	ldrb	r9,[r1,#3]
+	ldrb	r11,[r1,#1]
+	add	r6,r8,r6,ror#2			@ E+=K_00_19
+	ldrb	r12,[r1],#4
+	orr	r9,r9,r10,lsl#8
+	eor	r10,r4,r5			@ F_xx_xx
+	orr	r9,r9,r11,lsl#16
+	add	r6,r6,r7,ror#27			@ E+=ROR(A,27)
+	orr	r9,r9,r12,lsl#24
+#else
+	ldr	r9,[r1],#4			@ handles unaligned
+	add	r6,r8,r6,ror#2			@ E+=K_00_19
+	eor	r10,r4,r5			@ F_xx_xx
+	add	r6,r6,r7,ror#27			@ E+=ROR(A,27)
+#ifdef __ARMEL__
+	rev	r9,r9				@ byte swap
+#endif
+#endif
+	and	r10,r3,r10,ror#2
+	add	r6,r6,r9			@ E+=X[i]
+	eor	r10,r10,r5,ror#2		@ F_00_19(B,C,D)
+	str	r9,[r14,#-4]!
+	add	r6,r6,r10			@ E+=F_00_19(B,C,D)
+#if __ARM_ARCH__<7
+	ldrb	r10,[r1,#2]
+	ldrb	r9,[r1,#3]
+	ldrb	r11,[r1,#1]
+	add	r5,r8,r5,ror#2			@ E+=K_00_19
+	ldrb	r12,[r1],#4
+	orr	r9,r9,r10,lsl#8
+	eor	r10,r3,r4			@ F_xx_xx
+	orr	r9,r9,r11,lsl#16
+	add	r5,r5,r6,ror#27			@ E+=ROR(A,27)
+	orr	r9,r9,r12,lsl#24
+#else
+	ldr	r9,[r1],#4			@ handles unaligned
+	add	r5,r8,r5,ror#2			@ E+=K_00_19
+	eor	r10,r3,r4			@ F_xx_xx
+	add	r5,r5,r6,ror#27			@ E+=ROR(A,27)
+#ifdef __ARMEL__
+	rev	r9,r9				@ byte swap
+#endif
+#endif
+	and	r10,r7,r10,ror#2
+	add	r5,r5,r9			@ E+=X[i]
+	eor	r10,r10,r4,ror#2		@ F_00_19(B,C,D)
+	str	r9,[r14,#-4]!
+	add	r5,r5,r10			@ E+=F_00_19(B,C,D)
+#if __ARM_ARCH__<7
+	ldrb	r10,[r1,#2]
+	ldrb	r9,[r1,#3]
+	ldrb	r11,[r1,#1]
+	add	r4,r8,r4,ror#2			@ E+=K_00_19
+	ldrb	r12,[r1],#4
+	orr	r9,r9,r10,lsl#8
+	eor	r10,r7,r3			@ F_xx_xx
+	orr	r9,r9,r11,lsl#16
+	add	r4,r4,r5,ror#27			@ E+=ROR(A,27)
+	orr	r9,r9,r12,lsl#24
+#else
+	ldr	r9,[r1],#4			@ handles unaligned
+	add	r4,r8,r4,ror#2			@ E+=K_00_19
+	eor	r10,r7,r3			@ F_xx_xx
+	add	r4,r4,r5,ror#27			@ E+=ROR(A,27)
+#ifdef __ARMEL__
+	rev	r9,r9				@ byte swap
+#endif
+#endif
+	and	r10,r6,r10,ror#2
+	add	r4,r4,r9			@ E+=X[i]
+	eor	r10,r10,r3,ror#2		@ F_00_19(B,C,D)
+	str	r9,[r14,#-4]!
+	add	r4,r4,r10			@ E+=F_00_19(B,C,D)
+#if __ARM_ARCH__<7
+	ldrb	r10,[r1,#2]
+	ldrb	r9,[r1,#3]
+	ldrb	r11,[r1,#1]
+	add	r3,r8,r3,ror#2			@ E+=K_00_19
+	ldrb	r12,[r1],#4
+	orr	r9,r9,r10,lsl#8
+	eor	r10,r6,r7			@ F_xx_xx
+	orr	r9,r9,r11,lsl#16
+	add	r3,r3,r4,ror#27			@ E+=ROR(A,27)
+	orr	r9,r9,r12,lsl#24
+#else
+	ldr	r9,[r1],#4			@ handles unaligned
+	add	r3,r8,r3,ror#2			@ E+=K_00_19
+	eor	r10,r6,r7			@ F_xx_xx
+	add	r3,r3,r4,ror#27			@ E+=ROR(A,27)
+#ifdef __ARMEL__
+	rev	r9,r9				@ byte swap
+#endif
+#endif
+	and	r10,r5,r10,ror#2
+	add	r3,r3,r9			@ E+=X[i]
+	eor	r10,r10,r7,ror#2		@ F_00_19(B,C,D)
+	str	r9,[r14,#-4]!
+	add	r3,r3,r10			@ E+=F_00_19(B,C,D)
+	teq	r14,sp
+	bne	.L_00_15		@ [((11+4)*5+2)*3]
+#if __ARM_ARCH__<7
+	ldrb	r10,[r1,#2]
+	ldrb	r9,[r1,#3]
+	ldrb	r11,[r1,#1]
+	add	r7,r8,r7,ror#2			@ E+=K_00_19
+	ldrb	r12,[r1],#4
+	orr	r9,r9,r10,lsl#8
+	eor	r10,r5,r6			@ F_xx_xx
+	orr	r9,r9,r11,lsl#16
+	add	r7,r7,r3,ror#27			@ E+=ROR(A,27)
+	orr	r9,r9,r12,lsl#24
+#else
+	ldr	r9,[r1],#4			@ handles unaligned
+	add	r7,r8,r7,ror#2			@ E+=K_00_19
+	eor	r10,r5,r6			@ F_xx_xx
+	add	r7,r7,r3,ror#27			@ E+=ROR(A,27)
+#ifdef __ARMEL__
+	rev	r9,r9				@ byte swap
+#endif
+#endif
+	and	r10,r4,r10,ror#2
+	add	r7,r7,r9			@ E+=X[i]
+	eor	r10,r10,r6,ror#2		@ F_00_19(B,C,D)
+	str	r9,[r14,#-4]!
+	add	r7,r7,r10			@ E+=F_00_19(B,C,D)
+	ldr	r9,[r14,#15*4]
+	ldr	r10,[r14,#13*4]
+	ldr	r11,[r14,#7*4]
+	add	r6,r8,r6,ror#2			@ E+=K_xx_xx
+	ldr	r12,[r14,#2*4]
+	eor	r9,r9,r10
+	eor	r11,r11,r12			@ 1 cycle stall
+	eor	r10,r4,r5			@ F_xx_xx
+	mov	r9,r9,ror#31
+	add	r6,r6,r7,ror#27			@ E+=ROR(A,27)
+	eor	r9,r9,r11,ror#31
+	str	r9,[r14,#-4]!
+	and r10,r3,r10,ror#2					@ F_xx_xx
+						@ F_xx_xx
+	add	r6,r6,r9			@ E+=X[i]
+	eor	r10,r10,r5,ror#2		@ F_00_19(B,C,D)
+	add	r6,r6,r10			@ E+=F_00_19(B,C,D)
+	ldr	r9,[r14,#15*4]
+	ldr	r10,[r14,#13*4]
+	ldr	r11,[r14,#7*4]
+	add	r5,r8,r5,ror#2			@ E+=K_xx_xx
+	ldr	r12,[r14,#2*4]
+	eor	r9,r9,r10
+	eor	r11,r11,r12			@ 1 cycle stall
+	eor	r10,r3,r4			@ F_xx_xx
+	mov	r9,r9,ror#31
+	add	r5,r5,r6,ror#27			@ E+=ROR(A,27)
+	eor	r9,r9,r11,ror#31
+	str	r9,[r14,#-4]!
+	and r10,r7,r10,ror#2					@ F_xx_xx
+						@ F_xx_xx
+	add	r5,r5,r9			@ E+=X[i]
+	eor	r10,r10,r4,ror#2		@ F_00_19(B,C,D)
+	add	r5,r5,r10			@ E+=F_00_19(B,C,D)
+	ldr	r9,[r14,#15*4]
+	ldr	r10,[r14,#13*4]
+	ldr	r11,[r14,#7*4]
+	add	r4,r8,r4,ror#2			@ E+=K_xx_xx
+	ldr	r12,[r14,#2*4]
+	eor	r9,r9,r10
+	eor	r11,r11,r12			@ 1 cycle stall
+	eor	r10,r7,r3			@ F_xx_xx
+	mov	r9,r9,ror#31
+	add	r4,r4,r5,ror#27			@ E+=ROR(A,27)
+	eor	r9,r9,r11,ror#31
+	str	r9,[r14,#-4]!
+	and r10,r6,r10,ror#2					@ F_xx_xx
+						@ F_xx_xx
+	add	r4,r4,r9			@ E+=X[i]
+	eor	r10,r10,r3,ror#2		@ F_00_19(B,C,D)
+	add	r4,r4,r10			@ E+=F_00_19(B,C,D)
+	ldr	r9,[r14,#15*4]
+	ldr	r10,[r14,#13*4]
+	ldr	r11,[r14,#7*4]
+	add	r3,r8,r3,ror#2			@ E+=K_xx_xx
+	ldr	r12,[r14,#2*4]
+	eor	r9,r9,r10
+	eor	r11,r11,r12			@ 1 cycle stall
+	eor	r10,r6,r7			@ F_xx_xx
+	mov	r9,r9,ror#31
+	add	r3,r3,r4,ror#27			@ E+=ROR(A,27)
+	eor	r9,r9,r11,ror#31
+	str	r9,[r14,#-4]!
+	and r10,r5,r10,ror#2					@ F_xx_xx
+						@ F_xx_xx
+	add	r3,r3,r9			@ E+=X[i]
+	eor	r10,r10,r7,ror#2		@ F_00_19(B,C,D)
+	add	r3,r3,r10			@ E+=F_00_19(B,C,D)
+
+	ldr	r8,.LK_20_39		@ [+15+16*4]
+	sub	sp,sp,#25*4
+	cmn	sp,#0			@ [+3], clear carry to denote 20_39
+.L_20_39_or_60_79:
+	ldr	r9,[r14,#15*4]
+	ldr	r10,[r14,#13*4]
+	ldr	r11,[r14,#7*4]
+	add	r7,r8,r7,ror#2			@ E+=K_xx_xx
+	ldr	r12,[r14,#2*4]
+	eor	r9,r9,r10
+	eor	r11,r11,r12			@ 1 cycle stall
+	eor	r10,r5,r6			@ F_xx_xx
+	mov	r9,r9,ror#31
+	add	r7,r7,r3,ror#27			@ E+=ROR(A,27)
+	eor	r9,r9,r11,ror#31
+	str	r9,[r14,#-4]!
+	eor r10,r4,r10,ror#2					@ F_xx_xx
+						@ F_xx_xx
+	add	r7,r7,r9			@ E+=X[i]
+	add	r7,r7,r10			@ E+=F_20_39(B,C,D)
+	ldr	r9,[r14,#15*4]
+	ldr	r10,[r14,#13*4]
+	ldr	r11,[r14,#7*4]
+	add	r6,r8,r6,ror#2			@ E+=K_xx_xx
+	ldr	r12,[r14,#2*4]
+	eor	r9,r9,r10
+	eor	r11,r11,r12			@ 1 cycle stall
+	eor	r10,r4,r5			@ F_xx_xx
+	mov	r9,r9,ror#31
+	add	r6,r6,r7,ror#27			@ E+=ROR(A,27)
+	eor	r9,r9,r11,ror#31
+	str	r9,[r14,#-4]!
+	eor r10,r3,r10,ror#2					@ F_xx_xx
+						@ F_xx_xx
+	add	r6,r6,r9			@ E+=X[i]
+	add	r6,r6,r10			@ E+=F_20_39(B,C,D)
+	ldr	r9,[r14,#15*4]
+	ldr	r10,[r14,#13*4]
+	ldr	r11,[r14,#7*4]
+	add	r5,r8,r5,ror#2			@ E+=K_xx_xx
+	ldr	r12,[r14,#2*4]
+	eor	r9,r9,r10
+	eor	r11,r11,r12			@ 1 cycle stall
+	eor	r10,r3,r4			@ F_xx_xx
+	mov	r9,r9,ror#31
+	add	r5,r5,r6,ror#27			@ E+=ROR(A,27)
+	eor	r9,r9,r11,ror#31
+	str	r9,[r14,#-4]!
+	eor r10,r7,r10,ror#2					@ F_xx_xx
+						@ F_xx_xx
+	add	r5,r5,r9			@ E+=X[i]
+	add	r5,r5,r10			@ E+=F_20_39(B,C,D)
+	ldr	r9,[r14,#15*4]
+	ldr	r10,[r14,#13*4]
+	ldr	r11,[r14,#7*4]
+	add	r4,r8,r4,ror#2			@ E+=K_xx_xx
+	ldr	r12,[r14,#2*4]
+	eor	r9,r9,r10
+	eor	r11,r11,r12			@ 1 cycle stall
+	eor	r10,r7,r3			@ F_xx_xx
+	mov	r9,r9,ror#31
+	add	r4,r4,r5,ror#27			@ E+=ROR(A,27)
+	eor	r9,r9,r11,ror#31
+	str	r9,[r14,#-4]!
+	eor r10,r6,r10,ror#2					@ F_xx_xx
+						@ F_xx_xx
+	add	r4,r4,r9			@ E+=X[i]
+	add	r4,r4,r10			@ E+=F_20_39(B,C,D)
+	ldr	r9,[r14,#15*4]
+	ldr	r10,[r14,#13*4]
+	ldr	r11,[r14,#7*4]
+	add	r3,r8,r3,ror#2			@ E+=K_xx_xx
+	ldr	r12,[r14,#2*4]
+	eor	r9,r9,r10
+	eor	r11,r11,r12			@ 1 cycle stall
+	eor	r10,r6,r7			@ F_xx_xx
+	mov	r9,r9,ror#31
+	add	r3,r3,r4,ror#27			@ E+=ROR(A,27)
+	eor	r9,r9,r11,ror#31
+	str	r9,[r14,#-4]!
+	eor r10,r5,r10,ror#2					@ F_xx_xx
+						@ F_xx_xx
+	add	r3,r3,r9			@ E+=X[i]
+	add	r3,r3,r10			@ E+=F_20_39(B,C,D)
+	teq	r14,sp			@ preserve carry
+	bne	.L_20_39_or_60_79	@ [+((12+3)*5+2)*4]
+	bcs	.L_done			@ [+((12+3)*5+2)*4], spare 300 bytes
+
+	ldr	r8,.LK_40_59
+	sub	sp,sp,#20*4		@ [+2]
+.L_40_59:
+	ldr	r9,[r14,#15*4]
+	ldr	r10,[r14,#13*4]
+	ldr	r11,[r14,#7*4]
+	add	r7,r8,r7,ror#2			@ E+=K_xx_xx
+	ldr	r12,[r14,#2*4]
+	eor	r9,r9,r10
+	eor	r11,r11,r12			@ 1 cycle stall
+	eor	r10,r5,r6			@ F_xx_xx
+	mov	r9,r9,ror#31
+	add	r7,r7,r3,ror#27			@ E+=ROR(A,27)
+	eor	r9,r9,r11,ror#31
+	str	r9,[r14,#-4]!
+	and r10,r4,r10,ror#2					@ F_xx_xx
+	and r11,r5,r6					@ F_xx_xx
+	add	r7,r7,r9			@ E+=X[i]
+	add	r7,r7,r10			@ E+=F_40_59(B,C,D)
+	add	r7,r7,r11,ror#2
+	ldr	r9,[r14,#15*4]
+	ldr	r10,[r14,#13*4]
+	ldr	r11,[r14,#7*4]
+	add	r6,r8,r6,ror#2			@ E+=K_xx_xx
+	ldr	r12,[r14,#2*4]
+	eor	r9,r9,r10
+	eor	r11,r11,r12			@ 1 cycle stall
+	eor	r10,r4,r5			@ F_xx_xx
+	mov	r9,r9,ror#31
+	add	r6,r6,r7,ror#27			@ E+=ROR(A,27)
+	eor	r9,r9,r11,ror#31
+	str	r9,[r14,#-4]!
+	and r10,r3,r10,ror#2					@ F_xx_xx
+	and r11,r4,r5					@ F_xx_xx
+	add	r6,r6,r9			@ E+=X[i]
+	add	r6,r6,r10			@ E+=F_40_59(B,C,D)
+	add	r6,r6,r11,ror#2
+	ldr	r9,[r14,#15*4]
+	ldr	r10,[r14,#13*4]
+	ldr	r11,[r14,#7*4]
+	add	r5,r8,r5,ror#2			@ E+=K_xx_xx
+	ldr	r12,[r14,#2*4]
+	eor	r9,r9,r10
+	eor	r11,r11,r12			@ 1 cycle stall
+	eor	r10,r3,r4			@ F_xx_xx
+	mov	r9,r9,ror#31
+	add	r5,r5,r6,ror#27			@ E+=ROR(A,27)
+	eor	r9,r9,r11,ror#31
+	str	r9,[r14,#-4]!
+	and r10,r7,r10,ror#2					@ F_xx_xx
+	and r11,r3,r4					@ F_xx_xx
+	add	r5,r5,r9			@ E+=X[i]
+	add	r5,r5,r10			@ E+=F_40_59(B,C,D)
+	add	r5,r5,r11,ror#2
+	ldr	r9,[r14,#15*4]
+	ldr	r10,[r14,#13*4]
+	ldr	r11,[r14,#7*4]
+	add	r4,r8,r4,ror#2			@ E+=K_xx_xx
+	ldr	r12,[r14,#2*4]
+	eor	r9,r9,r10
+	eor	r11,r11,r12			@ 1 cycle stall
+	eor	r10,r7,r3			@ F_xx_xx
+	mov	r9,r9,ror#31
+	add	r4,r4,r5,ror#27			@ E+=ROR(A,27)
+	eor	r9,r9,r11,ror#31
+	str	r9,[r14,#-4]!
+	and r10,r6,r10,ror#2					@ F_xx_xx
+	and r11,r7,r3					@ F_xx_xx
+	add	r4,r4,r9			@ E+=X[i]
+	add	r4,r4,r10			@ E+=F_40_59(B,C,D)
+	add	r4,r4,r11,ror#2
+	ldr	r9,[r14,#15*4]
+	ldr	r10,[r14,#13*4]
+	ldr	r11,[r14,#7*4]
+	add	r3,r8,r3,ror#2			@ E+=K_xx_xx
+	ldr	r12,[r14,#2*4]
+	eor	r9,r9,r10
+	eor	r11,r11,r12			@ 1 cycle stall
+	eor	r10,r6,r7			@ F_xx_xx
+	mov	r9,r9,ror#31
+	add	r3,r3,r4,ror#27			@ E+=ROR(A,27)
+	eor	r9,r9,r11,ror#31
+	str	r9,[r14,#-4]!
+	and r10,r5,r10,ror#2					@ F_xx_xx
+	and r11,r6,r7					@ F_xx_xx
+	add	r3,r3,r9			@ E+=X[i]
+	add	r3,r3,r10			@ E+=F_40_59(B,C,D)
+	add	r3,r3,r11,ror#2
+	teq	r14,sp
+	bne	.L_40_59		@ [+((12+5)*5+2)*4]
+
+	ldr	r8,.LK_60_79
+	sub	sp,sp,#20*4
+	cmp	sp,#0			@ set carry to denote 60_79
+	b	.L_20_39_or_60_79	@ [+4], spare 300 bytes
+.L_done:
+	add	sp,sp,#80*4		@ "deallocate" stack frame
+	ldmia	r0,{r8,r9,r10,r11,r12}
+	add	r3,r8,r3
+	add	r4,r9,r4
+	add	r5,r10,r5,ror#2
+	add	r6,r11,r6,ror#2
+	add	r7,r12,r7,ror#2
+	stmia	r0,{r3,r4,r5,r6,r7}
+	teq	r1,r2
+	bne	.Lloop			@ [+18], total 1307
+
+#if __ARM_ARCH__>=5
+	ldmia	sp!,{r4-r12,pc}
+#else
+	ldmia	sp!,{r4-r12,lr}
+	tst	lr,#1
+	moveq	pc,lr			@ be binary compatible with V4, yet
+	.word	0xe12fff1e			@ interoperable with Thumb ISA:-)
+#endif
+.align	2
+.LK_00_19:	.word	0x5a827999
+.LK_20_39:	.word	0x6ed9eba1
+.LK_40_59:	.word	0x8f1bbcdc
+.LK_60_79:	.word	0xca62c1d6
+.size	sha1_block_data_order,.-sha1_block_data_order
+.asciz	"SHA1 block transform for ARMv4, CRYPTOGAMS by <appro@openssl.org>"
+.align	2
diff --git a/drivers/net/wireless/ssv6x5x/crypto/sha1_glue.c b/drivers/net/wireless/ssv6x5x/crypto/sha1_glue.c
new file mode 100644
index 000000000..abea12444
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/crypto/sha1_glue.c
@@ -0,0 +1,140 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <crypto/internal/hash.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/cryptohash.h>
+#include <linux/types.h>
+#include <crypto/sha.h>
+#include <asm/byteorder.h>
+struct SHA1_CTX {
+    uint32_t h0,h1,h2,h3,h4;
+    u64 count;
+    u8 data[SHA1_BLOCK_SIZE];
+};
+asmlinkage void sha1_block_data_order(struct SHA1_CTX *digest,
+                                      const unsigned char *data, unsigned int rounds);
+static int sha1_init(struct shash_desc *desc)
+{
+    struct SHA1_CTX *sctx = shash_desc_ctx(desc);
+    memset(sctx, 0, sizeof(*sctx));
+    sctx->h0 = SHA1_H0;
+    sctx->h1 = SHA1_H1;
+    sctx->h2 = SHA1_H2;
+    sctx->h3 = SHA1_H3;
+    sctx->h4 = SHA1_H4;
+    return 0;
+}
+static int __sha1_update(struct SHA1_CTX *sctx, const u8 *data,
+                         unsigned int len, unsigned int partial)
+{
+    unsigned int done = 0;
+    sctx->count += len;
+    if (partial) {
+        done = SHA1_BLOCK_SIZE - partial;
+        memcpy(sctx->data + partial, data, done);
+        sha1_block_data_order(sctx, sctx->data, 1);
+    }
+    if (len - done >= SHA1_BLOCK_SIZE) {
+        const unsigned int rounds = (len - done) / SHA1_BLOCK_SIZE;
+        sha1_block_data_order(sctx, data + done, rounds);
+        done += rounds * SHA1_BLOCK_SIZE;
+    }
+    memcpy(sctx->data, data + done, len - done);
+    return 0;
+}
+static int sha1_update(struct shash_desc *desc, const u8 *data,
+                       unsigned int len)
+{
+    struct SHA1_CTX *sctx = shash_desc_ctx(desc);
+    unsigned int partial = sctx->count % SHA1_BLOCK_SIZE;
+    int res;
+    if (partial + len < SHA1_BLOCK_SIZE) {
+        sctx->count += len;
+        memcpy(sctx->data + partial, data, len);
+        return 0;
+    }
+    res = __sha1_update(sctx, data, len, partial);
+    return res;
+}
+static int sha1_final(struct shash_desc *desc, u8 *out)
+{
+    struct SHA1_CTX *sctx = shash_desc_ctx(desc);
+    unsigned int i, index, padlen;
+    __be32 *dst = (__be32 *)out;
+    __be64 bits;
+    static const u8 padding[SHA1_BLOCK_SIZE] = { 0x80, };
+    bits = cpu_to_be64(sctx->count << 3);
+    index = sctx->count % SHA1_BLOCK_SIZE;
+    padlen = (index < 56) ? (56 - index) : ((SHA1_BLOCK_SIZE+56) - index);
+    if (padlen <= 56) {
+        sctx->count += padlen;
+        memcpy(sctx->data + index, padding, padlen);
+    } else {
+        __sha1_update(sctx, padding, padlen, index);
+    }
+    __sha1_update(sctx, (const u8 *)&bits, sizeof(bits), 56);
+    for (i = 0; i < 5; i++)
+        dst[i] = cpu_to_be32(((u32 *)sctx)[i]);
+    memset(sctx, 0, sizeof(*sctx));
+    return 0;
+}
+static int sha1_export(struct shash_desc *desc, void *out)
+{
+    struct SHA1_CTX *sctx = shash_desc_ctx(desc);
+    memcpy(out, sctx, sizeof(*sctx));
+    return 0;
+}
+static int sha1_import(struct shash_desc *desc, const void *in)
+{
+    struct SHA1_CTX *sctx = shash_desc_ctx(desc);
+    memcpy(sctx, in, sizeof(*sctx));
+    return 0;
+}
+static struct shash_alg alg = {
+    .digestsize = SHA1_DIGEST_SIZE,
+    .init = sha1_init,
+    .update = sha1_update,
+    .final = sha1_final,
+    .export = sha1_export,
+    .import = sha1_import,
+    .descsize = sizeof(struct SHA1_CTX),
+    .statesize = sizeof(struct SHA1_CTX),
+    .base = {
+        .cra_name = "sha1",
+        .cra_driver_name= "sha1-asm",
+        .cra_priority = 150,
+        .cra_flags = CRYPTO_ALG_TYPE_SHASH,
+        .cra_blocksize = SHA1_BLOCK_SIZE,
+        .cra_module = THIS_MODULE,
+    }
+};
+int sha1_mod_init(void)
+{
+    return crypto_register_shash(&alg);
+}
+void sha1_mod_fini(void)
+{
+    crypto_unregister_shash(&alg);
+}
+#if 0
+module_init(sha1_mod_init);
+module_exit(sha1_mod_fini);
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("SHA1 Secure Hash Algorithm (ARM)");
+MODULE_ALIAS("sha1");
+MODULE_AUTHOR("David McCullough <ucdevel@gmail.com>");
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/gen-version.sh b/drivers/net/wireless/ssv6x5x/gen-version.sh
new file mode 100755
index 000000000..51fbb6487
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/gen-version.sh
@@ -0,0 +1,4 @@
+#!/bin/bash
+
+./ver_info.pl include/ssv_version.h
+
diff --git a/drivers/net/wireless/ssv6x5x/genconf.sh b/drivers/net/wireless/ssv6x5x/genconf.sh
new file mode 100755
index 000000000..e98ee029a
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/genconf.sh
@@ -0,0 +1,25 @@
+#!/bin/bash
+# Script to convert defines in compiler option in to C's defines
+# Should be executed in make file and it take ccflags-y as the
+# compiler options. The content will be redirected to the first arguement.
+
+echo "#ifndef __SSV_MOD_CONF_H__" > $1
+echo "#define __SSV_MOD_CONF_H__" >> $1
+
+for flag in ${ccflags-y}; do
+	if [[ "$flag" =~ ^-D.* ]]; then
+		#def=${flag//-D/}
+		def=${flag:2}
+		echo "#ifndef $def" >> $1
+		echo "#define $def" >> $1
+		echo "#endif" >> $1
+	fi
+done
+
+echo "#define __must_check" >> $1
+echo "#define __devinit" >> $1
+echo "#define __devexit" >> $1
+echo "#define __init" >> $1
+echo "#define __exit" >> $1
+
+echo "#endif // __SSV_MOD_CONF_H__" >> $1
diff --git a/drivers/net/wireless/ssv6x5x/hci/Makefile b/drivers/net/wireless/ssv6x5x/hci/Makefile
new file mode 100755
index 000000000..8b872d665
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/hci/Makefile
@@ -0,0 +1,19 @@
+ifeq ($(KBUILD_TOP),)
+    ifneq ($(KBUILD_EXTMOD),)
+    KBUILD_DIR := $(KBUILD_EXTMOD)
+    else
+    KBUILD_DIR := $(PWD)
+    endif
+KBUILD_TOP := $(KBUILD_DIR)/../
+endif
+
+include $(KBUILD_TOP)/config.mak
+
+KBUILD_EXTRA_SYMBOLS += $(KBUILD_TOP)/ssvdevice/Module.symvers
+
+
+KMODULE_NAME=ssv6200_hci
+KERN_SRCS += ssv_hci.c
+
+
+include $(KBUILD_TOP)/rules.mak
diff --git a/drivers/net/wireless/ssv6x5x/hci/hctrl.h b/drivers/net/wireless/ssv6x5x/hci/hctrl.h
new file mode 100644
index 000000000..806646a4f
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/hci/hctrl.h
@@ -0,0 +1,254 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _HCTRL_H_
+#define _HCTRL_H_
+#define SSV6XXX_HCI_OP_INVALID 0x00000001
+#define SSV6XXX_HCI_OP_IFERR 0x00000002
+#define SSV6XXX_INT_RX 0x00000001
+#define SSV6XXX_INT_TX 0x00000002
+#define SSV6XXX_INT_SOC 0x00000004
+#define SSV6XXX_INT_LOW_EDCA_0 0x00000008
+#define SSV6XXX_INT_LOW_EDCA_1 0x00000010
+#define SSV6XXX_INT_LOW_EDCA_2 0x00000020
+#define SSV6XXX_INT_LOW_EDCA_3 0x00000040
+#define SSV6XXX_INT_RESOURCE_LOW 0x00000080
+#define IFDEV(_ct) ((_ct)->shi->dev)
+#define IFOPS(_ct) ((_ct)->shi->if_ops)
+#define HCI_REG_READ(_ct,_adr,_val) IFOPS(_ct)->readreg(IFDEV(_ct), _adr, _val)
+#define HCI_REG_WRITE(_ct,_adr,_val) IFOPS(_ct)->writereg(IFDEV(_ct), _adr, _val)
+#define HCI_REG_SAFE_READ(_ct,_adr,_val) IFOPS(_ct)->safe_readreg(IFDEV(_ct), _adr, _val)
+#define HCI_REG_SAFE_WRITE(_ct,_adr,_val) IFOPS(_ct)->safe_writereg(IFDEV(_ct), _adr, _val)
+#define HCI_BURST_REG_READ(_ct,_adr,_val,_num) IFOPS(_ct)->burst_readreg(IFDEV(_ct), _adr, _val, _num)
+#define HCI_BURST_REG_WRITE(_ct,_adr,_val,_num) IFOPS(_ct)->burst_writereg(IFDEV(_ct), _adr, _val, _num)
+#define HCI_BURST_REG_SAFE_READ(_ct,_adr,_val,_num) IFOPS(_ct)->burst_safe_readreg(IFDEV(_ct), _adr, _val, _num)
+#define HCI_BURST_REG_SAFE_WRITE(_ct,_adr,_val,_num) IFOPS(_ct)->burst_safe_writereg(IFDEV(_ct), _adr, _val, _num)
+#define HCI_REG_SET_BITS(_ct,_reg,_set,_clr) \
+{ \
+    u32 _regval; \
+    if(HCI_REG_READ(_ct, _reg, &_regval)); \
+    _regval &= ~(_clr); \
+    _regval |= (_set); \
+    if(HCI_REG_WRITE(_ct, _reg, _regval)); \
+}
+#define IF_SEND(_ct,_bf,_len,_qid) IFOPS(_ct)->write(IFDEV(_ct), _bf, _len, _qid)
+#define IF_RECV(_ct,_bf,_len,_mode) IFOPS(_ct)->read(IFDEV(_ct), _bf, _len, _mode)
+#define HCI_LOAD_FW(_ct,_addr,_data,_size) IFOPS(_ct)->load_fw(IFDEV(_ct), _addr, _data, _size)
+struct ssv6xxx_hci_ctrl {
+    struct ssv6xxx_hci_info *shi;
+    u32 hci_flags;
+    int write_hw_config;
+    spinlock_t int_lock;
+    u32 int_status;
+    u32 int_mask;
+    struct mutex txq_mask_lock;
+    u32 txq_mask;
+    struct ssv_hw_txq hw_txq[SSV_HW_TXQ_NUM];
+    struct mutex hci_mutex;
+    bool hci_start;
+    bool redownload;
+    struct sk_buff *rx_buf;
+    u32 rx_pkt;
+    struct workqueue_struct *hci_work_queue;
+    struct work_struct hci_rx_work;
+#ifdef CONFIG_SSV_TX_LOWTHRESHOLD
+    struct work_struct hci_tx_work;
+#else
+    struct work_struct hci_tx_work[SSV_HW_TXQ_NUM];
+#endif
+    wait_queue_head_t tx_wait_q;
+    struct task_struct *hci_tx_task;
+    u32 read_rs0_info_fail;
+    u32 read_rs1_info_fail;
+    u32 rx_work_running;
+    u32 isr_running;
+    u32 xmit_running;
+    u32 isr_disable;
+    u32 isr_summary_eable;
+    u32 isr_routine_time;
+    u32 isr_tx_time;
+    u32 isr_rx_time;
+    u32 isr_idle_time;
+    u32 isr_rx_idle_time;
+    u32 isr_miss_cnt;
+    unsigned long prev_isr_jiffes;
+    unsigned long prev_rx_isr_jiffes;
+    struct work_struct isr_reset_work;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+    struct dentry *debugfs_dir;
+    u32 isr_mib_enable;
+    u32 isr_mib_reset;
+    long long isr_total_time;
+    long long isr_tx_io_time;
+    long long isr_rx_io_time;
+    u32 isr_rx_io_count;
+    u32 isr_tx_io_count;
+    long long isr_rx_proc_time;
+#endif
+#ifdef CONFIG_IRQ_DEBUG_COUNT
+    bool irq_enable;
+    u32 irq_count;
+    u32 invalid_irq_count;
+    u32 tx_irq_count;
+    u32 real_tx_irq_count;
+    u32 rx_irq_count;
+    u32 irq_rx_pkt_count;
+    u32 irq_tx_pkt_count;
+#endif
+    struct ssv6xxx_tx_hw_info tx_info;
+    struct ssv6xxx_rx_hw_info rx_info;
+};
+struct ssv6xxx_hci_txq_info {
+    u32 tx_use_page:8;
+    u32 tx_use_id:6;
+    u32 txq0_size:4;
+    u32 txq1_size:4;
+    u32 txq2_size:5;
+    u32 txq3_size:5;
+};
+struct ssv6xxx_hci_txq_info2 {
+    u32 tx_use_page:9;
+    u32 tx_use_id:8;
+    u32 txq4_size:4;
+    u32 rsvd:11;
+};
+struct ssv6xxx_hw_resource {
+    int free_tx_page;
+    int free_tx_id;
+    int max_tx_frame[SSV_HW_TXQ_NUM];
+};
+static inline void ssv6xxx_hwif_irq_request(struct ssv6xxx_hci_ctrl *hctrl, irq_handler_t irq_handler)
+{
+    if(hctrl->shi->if_ops->irq_request)
+        hctrl->shi->if_ops->irq_request(IFDEV(hctrl), irq_handler, hctrl);
+}
+static inline void ssv6xxx_hwif_irq_enable(struct ssv6xxx_hci_ctrl *hctrl)
+{
+    if(hctrl->shi->if_ops->irq_enable)
+        hctrl->shi->if_ops->irq_enable(IFDEV(hctrl));
+}
+static inline void ssv6xxx_hwif_irq_disable(struct ssv6xxx_hci_ctrl *hctrl)
+{
+    if(hctrl->shi->if_ops->irq_disable)
+        hctrl->shi->if_ops->irq_disable(IFDEV(hctrl), false);
+}
+static inline int ssv6xxx_hwif_irq_getstatus(struct ssv6xxx_hci_ctrl *hctrl, int *status)
+{
+    if(hctrl->shi->if_ops->irq_getstatus)
+        return hctrl->shi->if_ops->irq_getstatus(IFDEV(hctrl), status);
+    return 0;
+}
+static inline void ssv6xxx_hwif_irq_setmask(struct ssv6xxx_hci_ctrl *hctrl, int mask)
+{
+    if(hctrl->shi->if_ops->irq_setmask)
+        hctrl->shi->if_ops->irq_setmask(IFDEV(hctrl), mask);
+}
+static inline void ssv6xxx_hwif_irq_trigger(struct ssv6xxx_hci_ctrl *hctrl)
+{
+    if(hctrl->shi->if_ops->irq_trigger)
+        hctrl->shi->if_ops->irq_trigger(IFDEV(hctrl));
+}
+static inline void ssv6xxx_hwif_pmu_wakeup(struct ssv6xxx_hci_ctrl *hctrl)
+{
+    if(hctrl->shi->if_ops->pmu_wakeup)
+        hctrl->shi->if_ops->pmu_wakeup(IFDEV(hctrl));
+}
+static inline int ssv6xxx_hwif_write_sram(struct ssv6xxx_hci_ctrl *hctrl, u32 addr, u8 *data, u32 size)
+{
+    if(hctrl->shi->if_ops->write_sram)
+        return hctrl->shi->if_ops->write_sram(IFDEV(hctrl), addr, data, size);
+    return 0;
+}
+static inline bool ssv6xxx_hwif_ready(struct ssv6xxx_hci_ctrl *hctrl)
+{
+    if(hctrl->shi->if_ops->property)
+        return hctrl->shi->if_ops->is_ready(IFDEV(hctrl));
+    return false;
+}
+static inline int ssv6xxx_hwif_property(struct ssv6xxx_hci_ctrl *hctrl)
+{
+    if(hctrl->shi->if_ops->property)
+        return hctrl->shi->if_ops->property(IFDEV(hctrl));
+    return 0;
+}
+static inline void ssv6xxx_hwif_load_fw_pre_config_device(struct ssv6xxx_hci_ctrl *hctrl)
+{
+    if(hctrl->shi->if_ops->load_fw_pre_config_device)
+        hctrl->shi->if_ops->load_fw_pre_config_device(IFDEV(hctrl));
+}
+static inline void ssv6xxx_hwif_load_fw_post_config_device(struct ssv6xxx_hci_ctrl *hctrl)
+{
+    if(hctrl->shi->if_ops->load_fw_post_config_device)
+        hctrl->shi->if_ops->load_fw_post_config_device(IFDEV(hctrl));
+}
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+static inline void ssv6xxx_hwif_rx_task(struct ssv6xxx_hci_ctrl *hctrl, int (*rx_cb)(struct sk_buff_head *rxq, void *args),
+                                        int (*is_rx_q_full)(void *args), void *args, u32 *pkt)
+#else
+static inline void ssv6xxx_hwif_rx_task(struct ssv6xxx_hci_ctrl *hctrl, int (*rx_cb)(struct sk_buff *rx_skb, void *args),
+                                        int (*is_rx_q_full)(void *args), void *args, u32 *pkt)
+#endif
+{
+    if(hctrl->shi->if_ops->hwif_rx_task)
+        hctrl->shi->if_ops->hwif_rx_task(IFDEV(hctrl), rx_cb, is_rx_q_full, args, pkt);
+}
+static inline void ssv6xxx_hwif_interface_reset(struct ssv6xxx_hci_ctrl *hctrl)
+{
+    if(hctrl->shi->if_ops->interface_reset)
+        hctrl->shi->if_ops->interface_reset(IFDEV(hctrl));
+}
+static inline int ssv6xxx_hwif_start_usb_acc(struct ssv6xxx_hci_ctrl *hctrl, u8 epnum)
+{
+    if(hctrl->shi->if_ops->start_usb_acc)
+        return hctrl->shi->if_ops->start_usb_acc(IFDEV(hctrl), epnum);
+    return 0;
+}
+static inline int ssv6xxx_hwif_stop_usb_acc(struct ssv6xxx_hci_ctrl *hctrl, u8 epnum)
+{
+    if(hctrl->shi->if_ops->stop_usb_acc)
+        return hctrl->shi->if_ops->stop_usb_acc(IFDEV(hctrl), epnum);
+    return 0;
+}
+static inline int ssv6xxx_hwif_jump_to_rom(struct ssv6xxx_hci_ctrl *hctrl)
+{
+    if(hctrl->shi->if_ops->jump_to_rom)
+        return hctrl->shi->if_ops->jump_to_rom(IFDEV(hctrl));
+    return 0;
+}
+static inline void ssv6xxx_hwif_sysplf_reset(struct ssv6xxx_hci_ctrl *hctrl, u32 addr, u32 value)
+{
+    if(hctrl->shi->if_ops->sysplf_reset)
+        hctrl->shi->if_ops->sysplf_reset(IFDEV(hctrl), addr, value);
+}
+#define HCI_IRQ_REQUEST(ct,hdle) ssv6xxx_hwif_irq_request(ct, hdle)
+#define HCI_IRQ_ENABLE(ct) ssv6xxx_hwif_irq_enable(ct)
+#define HCI_IRQ_DISABLE(ct) ssv6xxx_hwif_irq_disable(ct)
+#define HCI_IRQ_STATUS(ct,sts) ssv6xxx_hwif_irq_getstatus(ct, sts)
+#define HCI_IRQ_SET_MASK(ct,mk) ssv6xxx_hwif_irq_setmask(ct, mk)
+#define HCI_IRQ_TRIGGER(ct) ssv6xxx_hwif_irq_trigger(ct)
+#define HCI_PMU_WAKEUP(ct) ssv6xxx_hwif_pmu_wakeup(ct)
+#define HCI_SRAM_WRITE(ct,adr,dat,size) ssv6xxx_hwif_write_sram(ct, adr, dat, size)
+#define HCI_HWIF_READY(ct) ssv6xxx_hwif_ready(ct)
+#define HCI_HWIF_PROPERTY(ct) ssv6xxx_hwif_property(ct)
+#define HCI_LOAD_FW_PRE_CONFIG_DEVICE(ct) ssv6xxx_hwif_load_fw_pre_config_device(ct)
+#define HCI_LOAD_FW_POST_CONFIG_DEVICE(ct) ssv6xxx_hwif_load_fw_post_config_device(ct)
+#define HCI_RX_TASK(ct,rx_cb,is_rx_q_full,args,pkt) ssv6xxx_hwif_rx_task(ct, rx_cb, is_rx_q_full, args, pkt)
+#define HCI_IFC_RESET(ct) ssv6xxx_hwif_interface_reset(ct)
+#define HCI_START_USB_ACC(ct,epnum) ssv6xxx_hwif_start_usb_acc(ct, epnum)
+#define HCI_STOP_USB_ACC(ct,epnum) ssv6xxx_hwif_stop_usb_acc(ct, epnum)
+#define HCI_JUMP_TO_ROM(ct) ssv6xxx_hwif_jump_to_rom(ct)
+#define HCI_SYSPLF_RESET(ct,addr,value) ssv6xxx_hwif_sysplf_reset(ct, addr, value)
+#define HCI_DEVICE_TYPE(_hci_ctrl) (HCI_HWIF_PROPERTY(_hci_ctrl) & SSV_HWIF_INTERFACE_MASK)
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/hci/ssv_hci.c b/drivers/net/wireless/ssv6x5x/hci/ssv_hci.c
new file mode 100644
index 000000000..f4a126ebc
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/hci/ssv_hci.c
@@ -0,0 +1,1924 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/jiffies.h>
+#include <linux/kthread.h>
+#include <linux/firmware.h>
+#include <ssv6200.h>
+#include <smac/dev.h>
+#include <hal.h>
+#include "hctrl.h"
+MODULE_AUTHOR("iComm-semi, Ltd");
+MODULE_DESCRIPTION("HCI driver for SSV6xxx 802.11n wireless LAN cards.");
+MODULE_SUPPORTED_DEVICE("SSV6xxx WLAN cards");
+MODULE_LICENSE("Dual BSD/GPL");
+static void ssv6xxx_hci_trigger_tx(struct ssv6xxx_hci_ctrl *ctrl_hci)
+{
+    unsigned long flags;
+    u32 status;
+    if (ctrl_hci->isr_disable == true) {
+        wake_up_interruptible(&ctrl_hci->tx_wait_q);
+    } else {
+#ifdef CONFIG_SSV_TX_LOWTHRESHOLD
+        mutex_lock(&ctrl_hci->hci_mutex);
+#endif
+        spin_lock_irqsave(&ctrl_hci->int_lock, flags);
+        status = ctrl_hci->int_mask ;
+#ifdef CONFIG_SSV_TX_LOWTHRESHOLD
+        if ((ctrl_hci->int_mask & SSV6XXX_INT_RESOURCE_LOW) == 0) {
+            if (ctrl_hci->shi->if_ops->trigger_tx_rx == NULL) {
+                u32 regval;
+                ctrl_hci->int_mask |= SSV6XXX_INT_RESOURCE_LOW;
+                regval = ~ctrl_hci->int_mask;
+                spin_unlock_irqrestore(&ctrl_hci->int_lock, flags);
+                HCI_IRQ_SET_MASK(ctrl_hci, regval);
+                mutex_unlock(&ctrl_hci->hci_mutex);
+            } else {
+                ctrl_hci->int_status |= SSV6XXX_INT_RESOURCE_LOW;
+                smp_mb();
+                spin_unlock_irqrestore(&ctrl_hci->int_lock, flags);
+                mutex_unlock(&ctrl_hci->hci_mutex);
+                ctrl_hci->shi->if_ops->trigger_tx_rx(ctrl_hci->shi->dev);
+            }
+        } else {
+            spin_unlock_irqrestore(&ctrl_hci->int_lock, flags);
+            mutex_unlock(&ctrl_hci->hci_mutex);
+        }
+#else
+        {
+            u32 bitno;
+            bitno = ssv6xxx_hci_get_int_bitno(txqid);
+            if ((ctrl_hci->int_mask & BIT(bitno)) == 0) {
+                if (ctrl_hci->shi->if_ops->trigger_tx_rx == NULL) {
+                    queue_work(ctrl_hci->hci_work_queue,&ctrl_hci->hci_tx_work[txqid]);
+                } else {
+                    ctrl_hci->int_status |= BIT(bitno);
+                    smp_mb();
+                    ctrl_hci->shi->if_ops->trigger_tx_rx(ctrl_hci->shi->dev);
+                }
+            }
+        }
+        spin_unlock_irqrestore(&ctrl_hci->int_lock, flags);
+#endif
+    }
+}
+static int ssv6xxx_hci_usb_tx_handler(struct ssv6xxx_hci_ctrl *ctrl_hci, void *dev, int max_count, int *err);
+static int ssv6xxx_hci_irq_enable(struct ssv6xxx_hci_ctrl *ctrl_hci)
+{
+    HCI_IRQ_SET_MASK(ctrl_hci, ~(ctrl_hci->int_mask));
+    HCI_IRQ_ENABLE(ctrl_hci);
+    return 0;
+}
+static int ssv6xxx_hci_irq_disable(struct ssv6xxx_hci_ctrl *ctrl_hci)
+{
+    HCI_IRQ_SET_MASK(ctrl_hci, 0xffffffff);
+    HCI_IRQ_DISABLE(ctrl_hci);
+    return 0;
+}
+static void ssv6xxx_hci_irq_register(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 irq_mask)
+{
+    unsigned long flags;
+    u32 regval;
+    mutex_lock(&ctrl_hci->hci_mutex);
+    spin_lock_irqsave(&ctrl_hci->int_lock, flags);
+    ctrl_hci->int_mask |= irq_mask;
+    regval = ~ctrl_hci->int_mask;
+    spin_unlock_irqrestore(&ctrl_hci->int_lock, flags);
+    smp_mb();
+    HCI_IRQ_SET_MASK(ctrl_hci, regval);
+    mutex_unlock(&ctrl_hci->hci_mutex);
+}
+static inline u32 ssv6xxx_hci_get_int_bitno(struct ssv6xxx_hci_ctrl *ctrl_hci, int txqid)
+{
+    if(txqid == SSV_HW_TXQ_NUM-1)
+        return 1;
+    else
+        return txqid+3;
+}
+#ifndef SSV_SUPPORT_HAL
+void ssv6xxx_hci_hci_inq_info(struct ssv6xxx_hci_ctrl *ctrl_hci, int *used_id)
+{
+    return;
+}
+void ssv6xxx_hci_load_fw_enable_mcu(struct ssv6xxx_hci_ctrl *ctrl_hci)
+{
+    if (HCI_REG_WRITE(ctrl_hci, ADR_BRG_SW_RST, 0x1));
+}
+int ssv6xxx_hci_load_fw_disable_mcu(struct ssv6xxx_hci_ctrl *ctrl_hci)
+{
+    u32 clk_en;
+    if (HCI_REG_WRITE(ctrl_hci, ADR_BRG_SW_RST, 0x0));
+    if (HCI_REG_WRITE(ctrl_hci, ADR_BOOT, 0x0));
+    if (HCI_REG_READ(ctrl_hci, ADR_PLATFORM_CLOCK_ENABLE, &clk_en));
+    if (HCI_REG_WRITE(ctrl_hci, ADR_PLATFORM_CLOCK_ENABLE, (clk_en | (1 << 2))));
+    return 0;
+}
+int ssv6xxx_hci_load_fw_set_status(struct ssv6xxx_hci_ctrl *ctrl_hci, int status)
+{
+    return HCI_REG_WRITE(ctrl_hci, ADR_TX_SEG, status);
+}
+int ssv6xxx_hci_load_fw_get_status(struct ssv6xxx_hci_ctrl *ctrl_hci, int *status)
+{
+    return HCI_REG_READ(ctrl_hci, ADR_TX_SEG, status);
+}
+int ssv6xxx_hci_reset_cpu(struct ssv6xxx_hci_ctrl *ctrl_hci)
+{
+    u32 reset;
+    if (HCI_REG_READ(ctrl_hci, ADR_PLATFORM_CLOCK_ENABLE, &reset));
+    if (HCI_REG_WRITE(ctrl_hci, ADR_PLATFORM_CLOCK_ENABLE, reset & ~(1 << 24)));
+    return 0;
+}
+void ssv6xxx_hci_load_fw_pre_config_device(struct ssv6xxx_hci_ctrl *ctrl_hci)
+{
+    HCI_LOAD_FW_PRE_CONFIG_DEVICE(ctrl_hci);
+}
+void ssv6xxx_hci_load_fw_post_config_device(struct ssv6xxx_hci_ctrl *ctrl_hci)
+{
+    HCI_LOAD_FW_POST_CONFIG_DEVICE(ctrl_hci);
+}
+#endif
+static void *ssv6xxx_hci_open_firmware(char *user_mainfw)
+{
+    struct file *fp;
+    fp = filp_open(user_mainfw, O_RDONLY, 0);
+    if (IS_ERR(fp))
+        fp = NULL;
+    return fp;
+}
+static int ssv6xxx_hci_read_fw_block(char *buf, int len, void *image)
+{
+    struct file *fp = (struct file *)image;
+    int rdlen;
+    if (!image)
+        return 0;
+    rdlen = kernel_read(fp, fp->f_pos, buf, len);
+    if (rdlen > 0)
+        fp->f_pos += rdlen;
+    return rdlen;
+}
+static void ssv6xxx_hci_close_firmware(void *image)
+{
+    if (image)
+        filp_close((struct file *)image, NULL);
+}
+static int ssv6xxx_hci_load_firmware_openfile(struct ssv6xxx_hci_ctrl *hci_ctrl, u8 *firmware_name)
+{
+    int ret = 0;
+    u8 *fw_buffer = NULL;
+    u32 sram_addr = FW_START_SRAM_ADDR;
+    u32 block_count = 0;
+    u32 res_size=0, len=0, tolen=0;
+    void *fw_fp = NULL;
+    u8 interface = HCI_DEVICE_TYPE(hci_ctrl);
+#ifdef ENABLE_FW_SELF_CHECK
+    u32 checksum = FW_CHECKSUM_INIT;
+    u32 fw_checksum, fw_clkcnt;
+    u32 retry_count = 3;
+    u32 *fw_data32;
+#else
+    int writesize = 0;
+    u32 retry_count = 1;
+#endif
+    u32 word_count, i;
+    if (hci_ctrl->redownload == 1) {
+        HCI_DBG_PRINT(hci_ctrl, "Re-download FW\n");
+        HCI_JUMP_TO_ROM(hci_ctrl);
+    }
+    fw_fp = ssv6xxx_hci_open_firmware(firmware_name);
+    if (!fw_fp) {
+        HCI_DBG_PRINT(hci_ctrl, "failed to find firmware (%s)\n", firmware_name);
+        ret = -1;
+        goto out;
+    }
+    fw_buffer = (u8 *)kzalloc(FW_BLOCK_SIZE, GFP_KERNEL);
+    if (fw_buffer == NULL) {
+        HCI_DBG_PRINT(hci_ctrl, "Failed to allocate buffer for firmware.\n");
+        goto out;
+    }
+    do {
+        if (!(interface == SSV_HWIF_INTERFACE_USB)) {
+            ret = SSV_LOAD_FW_DISABLE_MCU(hci_ctrl);
+            if (ret == -1)
+                goto out;
+        }
+        HCI_DBG_PRINT(hci_ctrl, "Writing firmware to SSV6XXX...\n");
+        memset(fw_buffer, 0xA5, FW_BLOCK_SIZE);
+        while ((len = ssv6xxx_hci_read_fw_block((char*)fw_buffer, FW_BLOCK_SIZE, fw_fp))) {
+            tolen += len;
+            if (len < FW_BLOCK_SIZE) {
+                res_size = len;
+                break;
+            }
+            if ((ret = HCI_LOAD_FW(hci_ctrl, sram_addr, (u8 *)fw_buffer, FW_BLOCK_SIZE)) != 0)
+                break;
+            sram_addr += FW_BLOCK_SIZE;
+            word_count = (len / sizeof(u32));
+            fw_data32 = (u32 *)fw_buffer;
+            for (i = 0; i < word_count; i++) {
+                checksum += fw_data32[i];
+            }
+            memset(fw_buffer, 0xA5, FW_BLOCK_SIZE);
+        }
+        if(res_size) {
+            u32 cks_blk_cnt,cks_blk_res;
+            cks_blk_cnt = res_size / CHECKSUM_BLOCK_SIZE;
+            cks_blk_res = res_size % CHECKSUM_BLOCK_SIZE;
+            ret = HCI_LOAD_FW(hci_ctrl, sram_addr, (u8 *)fw_buffer, (cks_blk_cnt+1)*CHECKSUM_BLOCK_SIZE);
+            word_count = (cks_blk_cnt * CHECKSUM_BLOCK_SIZE / sizeof(u32));
+            fw_data32 = (u32 *)fw_buffer;
+            for (i = 0; i < word_count; i++)
+                checksum += *fw_data32++;
+            if(cks_blk_res) {
+                word_count = (CHECKSUM_BLOCK_SIZE / sizeof(u32));
+                for (i = 0; i < word_count; i++) {
+                    checksum += *fw_data32++;
+                }
+            }
+        }
+        checksum = ((checksum >> 24) + (checksum >> 16) + (checksum >> 8) + checksum) & 0x0FF;
+        checksum <<= 16;
+        if (ret == 0) {
+            if (interface == SSV_HWIF_INTERFACE_USB) {
+                ret = SSV_RESET_CPU(hci_ctrl);
+                if (ret == -1)
+                    goto out;
+            }
+            SSV_SET_SRAM_MODE(hci_ctrl, SRAM_MODE_ILM_160K_DLM_32K);
+            block_count = tolen / CHECKSUM_BLOCK_SIZE;
+            res_size = tolen % CHECKSUM_BLOCK_SIZE;
+            if(res_size)
+                block_count++;
+            SSV_LOAD_FW_SET_STATUS(hci_ctrl, (block_count << 16));
+            SSV_LOAD_FW_GET_STATUS(hci_ctrl, &fw_clkcnt);
+            HCI_DBG_PRINT(hci_ctrl, "(block_count << 16) = %x,reg =%x\n", (block_count << 16),fw_clkcnt);
+            SSV_LOAD_FW_ENABLE_MCU(hci_ctrl);
+            HCI_DBG_PRINT(hci_ctrl, "Firmware \"%s\" loaded\n", firmware_name);
+            msleep(50);
+            SSV_LOAD_FW_GET_STATUS(hci_ctrl, &fw_checksum);
+            fw_checksum = fw_checksum & FW_STATUS_MASK;
+            if (fw_checksum == checksum) {
+                SSV_LOAD_FW_SET_STATUS(hci_ctrl, (~checksum & FW_STATUS_MASK));
+                ret = 0;
+                HCI_DBG_PRINT(hci_ctrl, "Firmware check OK.%04x = %04x\n", fw_checksum, checksum);
+                break;
+            } else {
+                HCI_DBG_PRINT(hci_ctrl, "FW checksum error: %04x != %04x\n", fw_checksum, checksum);
+                ret = -1;
+            }
+        } else {
+            HCI_DBG_PRINT(hci_ctrl, "Firmware \"%s\" download failed. (%d)\n", firmware_name, ret);
+            ret = -1;
+        }
+    } while (--retry_count);
+    if (ret)
+        goto out;
+    hci_ctrl->redownload = 1;
+    ret = 0;
+out:
+    if(fw_fp)
+        ssv6xxx_hci_close_firmware(fw_fp);
+    if (fw_buffer != NULL)
+        kfree(fw_buffer);
+    return ret;
+}
+static int ssv6xxx_hci_get_firmware(struct device *dev, char *user_mainfw, const struct firmware **mainfw)
+{
+    int ret;
+    BUG_ON(mainfw == NULL);
+    if (*user_mainfw) {
+        ret = request_firmware(mainfw, user_mainfw, dev);
+        if (ret) {
+            goto fail;
+        }
+        if (*mainfw)
+            return 0;
+    }
+fail:
+    if (*mainfw) {
+        release_firmware(*mainfw);
+        *mainfw = NULL;
+    }
+    return -ENOENT;
+}
+static int ssv6xxx_hci_load_firmware_request(struct ssv6xxx_hci_ctrl *hci_ctrl, u8 *firmware_name)
+{
+    int ret = 0;
+    const struct firmware *ssv6xxx_fw = NULL;
+    u8 *fw_buffer = NULL;
+    u32 sram_addr = FW_START_SRAM_ADDR;
+    u32 block_count = 0;
+    u32 block_idx = 0;
+    u32 res_size;
+    u8 *fw_data;
+    u8 interface = HCI_DEVICE_TYPE(hci_ctrl);
+#ifdef ENABLE_FW_SELF_CHECK
+    u32 checksum = FW_CHECKSUM_INIT;
+    u32 fw_checksum;
+    u32 retry_count = 3;
+    u32 *fw_data32;
+#else
+    int writesize = 0;
+    u32 retry_count = 1;
+#endif
+    if (hci_ctrl->redownload == 1) {
+        HCI_DBG_PRINT(hci_ctrl, "Re-download FW\n");
+        HCI_JUMP_TO_ROM(hci_ctrl);
+    }
+    ret = ssv6xxx_hci_get_firmware(hci_ctrl->shi->dev, firmware_name, &ssv6xxx_fw);
+    if (ret) {
+        HCI_DBG_PRINT(hci_ctrl, "failed to find firmware (%d)\n", ret);
+        goto out;
+    }
+    fw_buffer = (u8 *)kzalloc(FW_BLOCK_SIZE, GFP_KERNEL);
+    if (fw_buffer == NULL) {
+        HCI_DBG_PRINT(hci_ctrl, "Failed to allocate buffer for firmware.\n");
+        goto out;
+    }
+#ifdef ENABLE_FW_SELF_CHECK
+    block_count = ssv6xxx_fw->size / CHECKSUM_BLOCK_SIZE;
+    res_size = ssv6xxx_fw->size % CHECKSUM_BLOCK_SIZE;
+    {
+        int word_count = (int)(block_count * CHECKSUM_BLOCK_SIZE / sizeof(u32));
+        int i;
+        fw_data32 = (u32 *)ssv6xxx_fw->data;
+        for (i = 0; i < word_count; i++)
+            checksum += fw_data32[i];
+        if (res_size) {
+            memset(fw_buffer, 0xA5, CHECKSUM_BLOCK_SIZE);
+            memcpy(fw_buffer, &ssv6xxx_fw->data[block_count * CHECKSUM_BLOCK_SIZE], res_size);
+            word_count = (int)(CHECKSUM_BLOCK_SIZE / sizeof(u32));
+            fw_data32 = (u32 *)fw_buffer;
+            for (i = 0; i < word_count; i++) {
+                checksum += fw_data32[i];
+            }
+        }
+    }
+    checksum = ((checksum >> 24) + (checksum >> 16) + (checksum >> 8) + checksum) & 0x0FF;
+    checksum <<= 16;
+#endif
+    do {
+        if (!(interface == SSV_HWIF_INTERFACE_USB)) {
+            ret = SSV_LOAD_FW_DISABLE_MCU(hci_ctrl);
+            if (ret == -1)
+                goto out;
+        }
+#ifdef ENABLE_FW_SELF_CHECK
+        block_count = ssv6xxx_fw->size / FW_BLOCK_SIZE;
+        res_size = ssv6xxx_fw->size % FW_BLOCK_SIZE;
+        HCI_DBG_PRINT(hci_ctrl, "Writing %d blocks to SSV6XXX...", block_count);
+        for (block_idx = 0, fw_data = (u8 *)ssv6xxx_fw->data, sram_addr = 0; block_idx < block_count;
+             block_idx++, fw_data += FW_BLOCK_SIZE, sram_addr += FW_BLOCK_SIZE) {
+            memcpy(fw_buffer, fw_data, FW_BLOCK_SIZE);
+            if ((ret = HCI_LOAD_FW(hci_ctrl, sram_addr, (u8 *)fw_buffer, FW_BLOCK_SIZE)) != 0)
+                break;
+        }
+        if(res_size) {
+            memset(fw_buffer, 0xA5, FW_BLOCK_SIZE);
+            memcpy(fw_buffer, &ssv6xxx_fw->data[block_count * FW_BLOCK_SIZE], res_size);
+            if ((ret = HCI_LOAD_FW(hci_ctrl, sram_addr, (u8 *)fw_buffer,
+                                   ((res_size/CHECKSUM_BLOCK_SIZE)+1)*CHECKSUM_BLOCK_SIZE)) != 0)
+                break;
+        }
+#else
+        block_count = ssv6xxx_fw->size / FW_BLOCK_SIZE;
+        res_size = ssv6xxx_fw->size % FW_BLOCK_SIZE;
+        writesize = sdio_align_size(func,res_size);
+        HCI_DBG_PRINT(hci_ctrl, "Writing %d blocks to SSV6XXX...", block_count);
+        for (block_idx = 0, fw_data = (u8 *)ssv6xxx_fw->data, sram_addr = 0; block_idx < block_count;
+             block_idx++, fw_data += FW_BLOCK_SIZE, sram_addr += FW_BLOCK_SIZE) {
+            memcpy(fw_buffer, fw_data, FW_BLOCK_SIZE);
+            if ((ret = HCI_LOAD_FW(hci_ctrl, sram_addr, (u8 *)fw_buffer, FW_BLOCK_SIZE)) != 0)
+                break;
+        }
+        if(res_size) {
+            memcpy(fw_buffer, &ssv6xxx_fw->data[block_count * FW_BLOCK_SIZE], res_size);
+            if ((ret = HCI_LOAD_FW(hci_ctrl, sram_addr, (u8 *)fw_buffer, writesize)) != 0)
+                break;
+        }
+#endif
+        if (ret == 0) {
+            if (interface == SSV_HWIF_INTERFACE_USB) {
+                ret = SSV_RESET_CPU(hci_ctrl);
+                if (ret == -1)
+                    goto out;
+            }
+            SSV_SET_SRAM_MODE(hci_ctrl, SRAM_MODE_ILM_160K_DLM_32K);
+#ifdef ENABLE_FW_SELF_CHECK
+            block_count = ssv6xxx_fw->size / CHECKSUM_BLOCK_SIZE;
+            res_size = ssv6xxx_fw->size % CHECKSUM_BLOCK_SIZE;
+            if(res_size)
+                block_count++;
+            SSV_LOAD_FW_SET_STATUS(hci_ctrl, (block_count << 16));
+#endif
+            SSV_LOAD_FW_ENABLE_MCU(hci_ctrl);
+            HCI_DBG_PRINT(hci_ctrl, "Firmware \"%s\" loaded\n", firmware_name);
+#ifdef ENABLE_FW_SELF_CHECK
+            msleep(50);
+            SSV_LOAD_FW_GET_STATUS(hci_ctrl, &fw_checksum);
+            fw_checksum = fw_checksum & FW_STATUS_MASK;
+            if (fw_checksum == checksum) {
+                SSV_LOAD_FW_SET_STATUS(hci_ctrl, (~checksum & FW_STATUS_MASK));
+                ret = 0;
+                HCI_DBG_PRINT(hci_ctrl, "Firmware check OK.\n");
+                break;
+            } else {
+                HCI_DBG_PRINT(hci_ctrl, "FW checksum error: %04x != %04x\n", fw_checksum, checksum);
+                ret = -1;
+            }
+#endif
+        } else {
+            HCI_DBG_PRINT(hci_ctrl, "Firmware \"%s\" download failed. (%d)\n", firmware_name, ret);
+            ret = -1;
+        }
+    } while (--retry_count);
+    if (ret)
+        goto out;
+    hci_ctrl->redownload = 1;
+    ret = 0;
+out:
+    if (ssv6xxx_fw)
+        release_firmware(ssv6xxx_fw);
+    if (fw_buffer != NULL)
+        kfree(fw_buffer);
+    return ret;
+}
+static int ssv6xxx_hci_start_acc(struct ssv6xxx_hci_ctrl *ctrl_hci)
+{
+    HCI_START_USB_ACC(ctrl_hci, 4);
+    return 0;
+}
+static int ssv6xxx_hci_stop_acc(struct ssv6xxx_hci_ctrl *ctrl_hci)
+{
+    HCI_STOP_USB_ACC(ctrl_hci, 4);
+    return 0;
+}
+static int ssv6xxx_hci_start(struct ssv6xxx_hci_ctrl *ctrl_hci)
+{
+    ssv6xxx_hci_irq_enable(ctrl_hci);
+    ssv6xxx_hci_start_acc(ctrl_hci);
+    ctrl_hci->hci_start = true;
+    HCI_IRQ_TRIGGER(ctrl_hci);
+    return 0;
+}
+static int ssv6xxx_hci_stop(struct ssv6xxx_hci_ctrl *ctrl_hci)
+{
+    ssv6xxx_hci_irq_disable(ctrl_hci);
+    ssv6xxx_hci_stop_acc(ctrl_hci);
+    ctrl_hci->hci_start = false;
+    return 0;
+}
+static void ssv6xxx_hci_write_hw_config(struct ssv6xxx_hci_ctrl *ctrl_hci, int val)
+{
+    ctrl_hci->write_hw_config = val;
+}
+static int ssv6xxx_hci_read_word(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 addr, u32 *regval)
+{
+    int ret = HCI_REG_READ(ctrl_hci, addr, regval);
+    return ret;
+}
+static int ssv6xxx_hci_safe_read_word(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 addr, u32 *regval)
+{
+    int ret = HCI_REG_SAFE_READ(ctrl_hci, addr, regval);
+    return ret;
+}
+static int ssv6xxx_hci_write_word(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 addr, u32 regval)
+{
+    if (ctrl_hci->write_hw_config && (ctrl_hci->shi->write_hw_config_cb != NULL))
+        ctrl_hci->shi->write_hw_config_cb((void *)SSV_SC(ctrl_hci), addr, regval);
+    return HCI_REG_WRITE(ctrl_hci, addr, regval);
+}
+static int ssv6xxx_hci_safe_write_word(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 addr, u32 regval)
+{
+    if (ctrl_hci->write_hw_config && (ctrl_hci->shi->write_hw_config_cb != NULL))
+        ctrl_hci->shi->write_hw_config_cb((void *)SSV_SC(ctrl_hci), addr, regval);
+    return HCI_REG_SAFE_WRITE(ctrl_hci, addr, regval);
+}
+static int ssv6xxx_hci_burst_read_word(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 *addr, u32 *regval, u8 reg_amount)
+{
+    int ret = HCI_BURST_REG_READ(ctrl_hci, addr, regval, reg_amount);
+    return ret;
+}
+static int ssv6xxx_hci_burst_write_word(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 *addr, u32 *regval, u8 reg_amount)
+{
+    return HCI_BURST_REG_WRITE(ctrl_hci, addr, regval, reg_amount);
+}
+static int ssv6xxx_hci_burst_safe_read_word(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 *addr, u32 *regval, u8 reg_amount)
+{
+    int ret = HCI_BURST_REG_SAFE_READ(ctrl_hci, addr, regval, reg_amount);
+    return ret;
+}
+static int ssv6xxx_hci_burst_safe_write_word(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 *addr, u32 *regval, u8 reg_amount)
+{
+    return HCI_BURST_REG_SAFE_WRITE(ctrl_hci, addr, regval, reg_amount);
+}
+static int ssv6xxx_hci_load_fw(struct ssv6xxx_hci_ctrl *hci_ctrl, u8 *firmware_name, u8 openfile)
+{
+    int ret = 0;
+    SSV_LOAD_FW_PRE_CONFIG_DEVICE(hci_ctrl);
+    if (openfile)
+        ret = ssv6xxx_hci_load_firmware_openfile(hci_ctrl, firmware_name);
+    else
+        ret = ssv6xxx_hci_load_firmware_request(hci_ctrl, firmware_name);
+    msleep(50);
+    if (ret == 0)
+        SSV_LOAD_FW_POST_CONFIG_DEVICE(hci_ctrl);
+    return ret;
+}
+static int ssv6xxx_hci_write_sram(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 addr, u8 *data, u32 size)
+{
+    return HCI_SRAM_WRITE(ctrl_hci, addr, data, size);
+}
+static int ssv6xxx_hci_pmu_wakeup(struct ssv6xxx_hci_ctrl *ctrl_hci)
+{
+    HCI_PMU_WAKEUP(ctrl_hci);
+    return 0;
+}
+static int ssv6xxx_hci_interface_reset(struct ssv6xxx_hci_ctrl *ctrl_hci)
+{
+    HCI_IFC_RESET(ctrl_hci);
+    return 0;
+}
+static int ssv6xxx_hci_sysplf_reset(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 addr, u32 value)
+{
+    HCI_SYSPLF_RESET(ctrl_hci, addr, value);
+    return 0;
+}
+static int ssv6xxx_hci_send_cmd(struct ssv6xxx_hci_ctrl *ctrl_hci, struct sk_buff *skb)
+{
+    int ret;
+    ret = IF_SEND(ctrl_hci, (void *)skb, skb->len, 0);
+    if (ret < 0) {
+        HCI_DBG_PRINT(ctrl_hci, "ssv6xxx_hci_send_cmd fail......\n");
+    }
+    return ret;
+}
+static int ssv6xxx_hci_enqueue(struct ssv6xxx_hci_ctrl *ctrl_hci, struct sk_buff *skb, int txqid, u32 tx_flags)
+{
+    struct ssv_hw_txq *hw_txq;
+    int qlen = 0;
+    BUG_ON(txqid >= SSV_HW_TXQ_NUM || txqid < 0);
+    if (txqid >= SSV_HW_TXQ_NUM || txqid < 0)
+        return -1;
+    hw_txq = &ctrl_hci->hw_txq[txqid];
+    hw_txq->tx_flags = tx_flags;
+    if (tx_flags & HCI_FLAGS_ENQUEUE_HEAD)
+        skb_queue_head(&hw_txq->qhead, skb);
+    else
+        skb_queue_tail(&hw_txq->qhead, skb);
+    qlen = (int)skb_queue_len(&hw_txq->qhead);
+    if (!(tx_flags & HCI_FLAGS_NO_FLOWCTRL)) {
+        if (skb_queue_len(&hw_txq->qhead) >= hw_txq->max_qsize) {
+            ctrl_hci->shi->hci_tx_flow_ctrl_cb(
+                (void *)SSV_SC(ctrl_hci),
+                hw_txq->txq_no,
+                true,2000
+            );
+        }
+    }
+    ssv6xxx_hci_trigger_tx(ctrl_hci);
+    return qlen;
+}
+static bool ssv6xxx_hci_is_txq_empty(struct ssv6xxx_hci_ctrl *ctrl_hci, int txqid)
+{
+    struct ssv_hw_txq *hw_txq;
+    BUG_ON(txqid >= SSV_HW_TXQ_NUM);
+    if (txqid >= SSV_HW_TXQ_NUM)
+        return false;
+    hw_txq = &ctrl_hci->hw_txq[txqid];
+    if (skb_queue_len(&hw_txq->qhead) <= 0)
+        return true;
+    return false;
+}
+static int ssv6xxx_hci_txq_flush(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 txq_mask)
+{
+    struct ssv_hw_txq *hw_txq;
+    struct sk_buff *skb = NULL;
+    int txqid;
+    for(txqid=0; txqid<SSV_HW_TXQ_NUM; txqid++) {
+        if ((txq_mask & (1<<txqid)) != 0)
+            continue;
+        hw_txq = &ctrl_hci->hw_txq[txqid];
+        while((skb = skb_dequeue(&hw_txq->qhead))) {
+            ctrl_hci->shi->hci_tx_buf_free_cb (skb, (void *)SSV_SC(ctrl_hci));
+        }
+    }
+    return 0;
+}
+static int ssv6xxx_hci_txq_flush_by_sta(struct ssv6xxx_hci_ctrl *ctrl_hci, int aid)
+{
+    return 0;
+}
+static int ssv6xxx_hci_txq_pause(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 txq_mask)
+{
+    struct ssv_hw_txq *hw_txq;
+    int txqid;
+#ifdef SSV_SUPPORT_HAL
+    struct ssv_hw *sh;
+    if (SSV_SC(ctrl_hci) == NULL) {
+        HCI_DBG_PRINT(ctrl_hci, "%s: can't pause due to software structure not initialized !!\n", __func__);
+        return 1;
+    }
+    sh = ctrl_hci->shi->sh;
+#endif
+    mutex_lock(&ctrl_hci->txq_mask_lock);
+    ctrl_hci->txq_mask |= (txq_mask & 0x1F);
+    for(txqid=0; txqid<SSV_HW_TXQ_NUM; txqid++) {
+        if ((ctrl_hci->txq_mask&(1<<txqid)) == 0)
+            continue;
+        hw_txq = &ctrl_hci->hw_txq[txqid];
+        hw_txq->paused = true;
+    }
+#ifdef SSV_SUPPORT_HAL
+    HAL_UPDATE_TXQ_MASK(sh, ctrl_hci->txq_mask);
+#else
+    HCI_REG_SET_BITS(ctrl_hci, ADR_MTX_MISC_EN,
+                     (ctrl_hci->txq_mask << MTX_HALT_Q_MB_SFT), MTX_HALT_Q_MB_MSK);
+#endif
+    mutex_unlock(&ctrl_hci->txq_mask_lock);
+    return 0;
+}
+static int ssv6xxx_hci_txq_resume(struct ssv6xxx_hci_ctrl *hci_ctrl, u32 txq_mask)
+{
+    struct ssv_hw_txq *hw_txq;
+    int txqid;
+#ifdef SSV_SUPPORT_HAL
+    struct ssv_hw *sh;
+    if (SSV_SC(hci_ctrl) == NULL) {
+        HCI_DBG_PRINT(hci_ctrl, "%s: can't resume due to software structure not initialized !!\n", __func__);
+        return 1;
+    }
+    sh = hci_ctrl->shi->sh;
+#endif
+    mutex_lock(&hci_ctrl->txq_mask_lock);
+    hci_ctrl->txq_mask &= ~(txq_mask & 0x1F);
+#ifdef SSV_SUPPORT_HAL
+    HAL_UPDATE_TXQ_MASK(sh, hci_ctrl->txq_mask);
+#else
+    HCI_REG_SET_BITS(hci_ctrl, ADR_MTX_MISC_EN,
+                     (hci_ctrl->txq_mask << MTX_HALT_Q_MB_SFT), MTX_HALT_Q_MB_MSK);
+#endif
+    for(txqid=0; txqid<SSV_HW_TXQ_NUM; txqid++) {
+        if ((hci_ctrl->txq_mask&(1<<txqid)) != 0)
+            continue;
+        hw_txq = &hci_ctrl->hw_txq[txqid];
+        hw_txq->paused = false;
+    }
+    mutex_unlock(&hci_ctrl->txq_mask_lock);
+    ssv6xxx_hci_trigger_tx(hci_ctrl);
+    return 0;
+}
+static int ssv6xxx_hci_force_xmit(struct ssv6xxx_hci_ctrl *hci_ctrl, struct ssv_hw_txq *hw_txq,
+                                  int max_count, int *err, int free_tx_page)
+{
+    struct sk_buff_head tx_cb_list;
+    struct sk_buff *skb = NULL;
+    int tx_count, ret;
+    int reason = -1, page_count;
+    struct ssv6xxx_hci_info *shi = hci_ctrl->shi;
+#ifdef SSV_SUPPORT_HAL
+    struct ssv_hw *sh;
+#else
+    struct ssv6200_tx_desc *tx_desc = NULL;
+#endif
+    hci_ctrl->xmit_running = 1;
+    skb_queue_head_init(&tx_cb_list);
+    for (tx_count=0; tx_count<max_count; tx_count++) {
+        if ((hci_ctrl->hci_start == false) || (hw_txq->paused)) {
+            HCI_DBG_PRINT(hci_ctrl, "ssv6xxx_hci_force_xmit - hci_start = false\n");
+            *err = 1;
+            goto xmit_out;
+        }
+        skb = skb_dequeue(&hw_txq->qhead);
+        if (!skb) {
+            goto xmit_out;
+        }
+        if (free_tx_page != TX_PAGE_NOT_LIMITED ) {
+            page_count = (skb->len + SSV6200_ALLOC_RSVD);
+            if (page_count & HW_MMU_PAGE_MASK)
+                page_count = (page_count >> HW_MMU_PAGE_SHIFT) + 1;
+            else
+                page_count = page_count >> HW_MMU_PAGE_SHIFT;
+            if (page_count > (SSV6XXX_PAGE_TX_THRESHOLD(hci_ctrl) / 2))
+                HCI_DBG_PRINT(hci_ctrl, "Asking page %d(%d) exceeds resource limit %d.\n",
+                              page_count, skb->len,(SSV6XXX_PAGE_TX_THRESHOLD(hci_ctrl) / 2));
+            if (free_tx_page < page_count) {
+                skb_queue_head(&hw_txq->qhead, skb);
+                break;
+            }
+            free_tx_page -= page_count;
+        }
+#ifdef SSV_SUPPORT_HAL
+        sh = shi->sh;
+        reason = HAL_GET_TX_DESC_REASON(sh, skb);
+#else
+        tx_desc = (struct ssv6200_tx_desc *)skb->data;
+        reason = tx_desc->reason;
+#endif
+#if 1
+        if (shi->hci_skb_update_cb != NULL && reason != ID_TRAP_SW_TXTPUT) {
+            shi->hci_skb_update_cb(skb, (void *)(SSV_SC(hci_ctrl)));
+        }
+#endif
+        if (shi->hci_pre_tx_cb)
+            shi->hci_pre_tx_cb(skb, (void *)(SSV_SC(hci_ctrl)));
+        ret = IF_SEND(hci_ctrl, (void *)skb, skb->len, hw_txq->txq_no);
+        if (ret < 0) {
+            HCI_DBG_PRINT(hci_ctrl, "ssv6xxx_hci_force_xmit fail[%d]......\n", ret);
+            *err = ret;
+            skb_queue_head(&hw_txq->qhead, skb);
+            break;
+        }
+        if (reason != ID_TRAP_SW_TXTPUT)
+            skb_queue_tail(&tx_cb_list, skb);
+        else
+            shi->skb_free((void *)(SSV_SC(hci_ctrl)), skb);
+        hw_txq->tx_pkt ++;
+        if (skb_queue_len(&hw_txq->qhead) < hw_txq->resum_thres) {
+            shi->hci_tx_flow_ctrl_cb(
+                (void *)(SSV_SC(hci_ctrl)),
+                hw_txq->txq_no, false, 2000);
+        }
+    }
+xmit_out:
+    if (shi->hci_post_tx_cb && reason != -1 && reason != ID_TRAP_SW_TXTPUT) {
+        shi->hci_post_tx_cb (&tx_cb_list, (void *)(SSV_SC(hci_ctrl)));
+    }
+    hci_ctrl->xmit_running = 0;
+    return tx_count;
+}
+static int ssv6xxx_hci_force_tx_handler(struct ssv6xxx_hci_ctrl *hci_ctrl, void *dev,
+                                        int max_count, int *err)
+{
+    struct ssv_hw_txq *hw_txq=dev;
+    int tx_count=0;
+    struct ssv6xxx_hci_info *shi = hci_ctrl->shi;
+    int hci_free_id = 0, hci_used_id = -1;
+    int free_tx_page = TX_PAGE_NOT_LIMITED, tx_use_page = -1;
+    max_count = skb_queue_len(&hw_txq->qhead);
+    if (max_count == 0)
+        return 0;
+    if ((hci_ctrl->hci_start == false) || (hw_txq->paused)) {
+        *err = 1;
+        return 0;
+    }
+    if (shi->sh->cfg.usb_hw_resource != USB_HW_RESOURCE_CHK_NONE ) {
+        SSV_READRG_HCI_INQ_INFO(hci_ctrl, &hci_used_id, & tx_use_page);
+        if ((hci_used_id == -1) || (tx_use_page == -1)) {
+            *err = -EIO;
+            return 0;
+        }
+        if (shi->sh->cfg.usb_hw_resource & USB_HW_RESOURCE_CHK_TXID ) {
+            if (hci_used_id != -1) {
+                hci_free_id = SSV6XXX_ID_HCI_INPUT_QUEUE - hci_used_id;
+                if (hci_free_id == 0) {
+                    *err = 2;
+                    return 0;
+                }
+                if (max_count > hci_free_id)
+                    max_count = hci_free_id;
+            }
+        }
+        if ((shi->sh->cfg.usb_hw_resource & USB_HW_RESOURCE_CHK_TXPAGE) ||
+            (shi->sh->cfg.usb_hw_resource & USB_HW_RESOURCE_CHK_SCAN)) {
+            free_tx_page = SSV6XXX_PAGE_TX_THRESHOLD(hci_ctrl) - tx_use_page;
+            if (free_tx_page < 0) {
+                *err = 2;
+                return 0;
+            }
+        }
+    }
+    tx_count = ssv6xxx_hci_force_xmit(hci_ctrl, hw_txq, max_count, err, free_tx_page);
+    if ( (shi->hci_tx_q_empty_cb != NULL)
+         && (skb_queue_len(&hw_txq->qhead) == 0)) {
+        shi->hci_tx_q_empty_cb(hw_txq->txq_no, (void *)(SSV_SC(hci_ctrl)));
+    }
+    return tx_count;
+}
+static int _do_force_tx (struct ssv6xxx_hci_ctrl *hctl, int *err)
+{
+    int q_num;
+    int tx_count = 0;
+    struct ssv_hw_txq *hw_txq;
+    u32 dev_type = HCI_DEVICE_TYPE(hctl);
+    int (*handler)(struct ssv6xxx_hci_ctrl *, void *, int, int *);
+    if ((dev_type == SSV_HWIF_INTERFACE_USB) &&
+        ( (hctl->shi->sh->cfg.usb_hw_resource & USB_HW_RESOURCE_CHK_TXID ) == 0)) {
+        handler = ssv6xxx_hci_force_tx_handler;
+    } else {
+        handler = ssv6xxx_hci_usb_tx_handler;
+    }
+    for (q_num = (SSV_HW_TXQ_NUM - 1); q_num >= 0; q_num--) {
+        hw_txq = &hctl->hw_txq[q_num];
+        tx_count += handler(hctl, hw_txq, 999, err);
+        if (*err < 0)
+            break;
+    }
+    return tx_count;
+}
+static int ssv6xxx_hci_xmit(struct ssv6xxx_hci_ctrl *hci_ctrl, struct ssv_hw_txq *hw_txq, int max_count, struct ssv6xxx_hw_resource *phw_resource)
+{
+    struct sk_buff_head tx_cb_list;
+    struct sk_buff *skb = NULL;
+    int tx_count = 0, ret = 0, page_count;
+    int reason = -1;
+#ifdef SSV_SUPPORT_HAL
+    struct ssv_hw *sh;
+#else
+    struct ssv6200_tx_desc *tx_desc = NULL;
+#endif
+    hci_ctrl->xmit_running = 1;
+    skb_queue_head_init(&tx_cb_list);
+    for(tx_count=0; tx_count<max_count; tx_count++) {
+        if ((hci_ctrl->hci_start == false) || (hw_txq->paused)) {
+            HCI_DBG_PRINT(hci_ctrl, "ssv6xxx_hci_xmit - hci_start = false\n");
+            goto xmit_out;
+        }
+        skb = skb_dequeue(&hw_txq->qhead);
+        if (!skb) {
+            HCI_DBG_PRINT(hci_ctrl, "ssv6xxx_hci_xmit - queue empty\n");
+            goto xmit_out;
+        }
+        page_count = (skb->len + SSV6200_ALLOC_RSVD);
+        if (page_count & HW_MMU_PAGE_MASK)
+            page_count = (page_count >> HW_MMU_PAGE_SHIFT) + 1;
+        else
+            page_count = page_count >> HW_MMU_PAGE_SHIFT;
+        if (page_count > (SSV6XXX_PAGE_TX_THRESHOLD(hci_ctrl) / 2))
+            HCI_DBG_PRINT(hci_ctrl, "Asking page %d(%d) exceeds resource limit %d.\n",
+                          page_count, skb->len,(SSV6XXX_PAGE_TX_THRESHOLD(hci_ctrl) / 2));
+        if (page_count > SSV6XXX_PAGE_TX_THRESHOLD(hci_ctrl)) {
+            printk("Asking page %d(%d) > %d is impossible to send. Drop it!\n", page_count, skb->len, SSV6XXX_PAGE_TX_THRESHOLD(hci_ctrl));
+            hci_ctrl->shi->skb_free((void *)(SSV_SC(hci_ctrl)), skb);
+            break;
+        }
+        if ((phw_resource->free_tx_page < page_count) || (phw_resource->free_tx_id <= 0) || (phw_resource->max_tx_frame[hw_txq->txq_no] <= 0)) {
+            skb_queue_head(&hw_txq->qhead, skb);
+            udelay(1);
+            break;
+        }
+        phw_resource->free_tx_page -= page_count;
+        phw_resource->free_tx_id--;
+        phw_resource->max_tx_frame[hw_txq->txq_no]--;
+#ifdef SSV_SUPPORT_HAL
+        sh = hci_ctrl->shi->sh;
+        reason = HAL_GET_TX_DESC_REASON(sh, skb);
+#else
+        tx_desc = (struct ssv6200_tx_desc *)skb->data;
+        reason = tx_desc->reason;
+#endif
+#if 1
+        if (hci_ctrl->shi->hci_skb_update_cb != NULL && reason != ID_TRAP_SW_TXTPUT) {
+            hci_ctrl->shi->hci_skb_update_cb(skb, (void *)(SSV_SC(hci_ctrl)));
+        }
+#endif
+        if (hci_ctrl->shi->hci_pre_tx_cb)
+            hci_ctrl->shi->hci_pre_tx_cb(skb, (void *)(SSV_SC(hci_ctrl)));
+        ret = IF_SEND(hci_ctrl, (void *)skb, skb->len, hw_txq->txq_no);
+        if (ret < 0) {
+            HCI_DBG_PRINT(hci_ctrl, "ssv6xxx_hci_xmit fail......\n");
+            skb_queue_head(&hw_txq->qhead, skb);
+            break;
+        }
+        if (reason != ID_TRAP_SW_TXTPUT)
+            skb_queue_tail(&tx_cb_list, skb);
+        else
+            hci_ctrl->shi->skb_free((void *)(SSV_SC(hci_ctrl)), skb);
+        hw_txq->tx_pkt ++;
+#ifdef CONFIG_IRQ_DEBUG_COUNT
+        if (hci_ctrl->irq_enable)
+            hci_ctrl->irq_tx_pkt_count++;
+#endif
+        if (skb_queue_len(&hw_txq->qhead) < hw_txq->resum_thres) {
+            hci_ctrl->shi->hci_tx_flow_ctrl_cb(
+                (void *)(SSV_SC(hci_ctrl)),
+                hw_txq->txq_no, false, 2000);
+        }
+    }
+xmit_out:
+    if (hci_ctrl->shi->hci_post_tx_cb && reason != -1 && reason != ID_TRAP_SW_TXTPUT) {
+        hci_ctrl->shi->hci_post_tx_cb (&tx_cb_list, (void *)(SSV_SC(hci_ctrl)));
+    }
+    hci_ctrl->xmit_running = 0;
+    return (ret == 0) ? tx_count : ret;
+}
+static int ssv6xxx_hci_tx_handler(struct ssv6xxx_hci_ctrl *ctrl_hci, void *dev, int max_count)
+{
+    struct ssv6xxx_hci_txq_info txq_info;
+    struct ssv6xxx_hci_txq_info2 txq_info2;
+    struct ssv6xxx_hw_resource hw_resource;
+    struct ssv_hw_txq *hw_txq=dev;
+    int hci_used_id = -1;
+    int ret, tx_count=0;
+    max_count = skb_queue_len(&hw_txq->qhead);
+    if ((max_count == 0) || (hw_txq->paused))
+        return 0;
+    if (hw_txq->txq_no == 4) {
+#ifndef _x86_64
+retry_read:
+#endif
+#ifdef SSV_SUPPORT_HAL
+        if (SSV_SC(ctrl_hci) != NULL)
+            ret = HAL_READRG_TXQ_INFO2(ctrl_hci->shi->sh,(u32 *)&txq_info2, &hci_used_id);
+        else {
+            HCI_DBG_PRINT(ctrl_hci, "%s: can't read txq_info2 due to software structure not initialized !!\n", __func__);
+            return 0;
+        }
+#else
+        ret = HCI_REG_READ(ctrl_hci, ADR_TX_ID_ALL_INFO2, (u32 *)&txq_info2);
+#endif
+        if (ret < 0) {
+            ctrl_hci->read_rs1_info_fail++;
+            return 0;
+        }
+#ifdef _x86_64
+        BUG_ON(SSV6XXX_PAGE_TX_THRESHOLD(ctrl_hci) < txq_info2.tx_use_page);
+        BUG_ON(SSV6XXX_ID_TX_THRESHOLD(ctrl_hci) < txq_info2.tx_use_id);
+#else
+        if(SSV6XXX_PAGE_TX_THRESHOLD(ctrl_hci) < txq_info2.tx_use_page)
+            goto retry_read;
+        if(SSV6XXX_ID_TX_THRESHOLD(ctrl_hci) < txq_info2.tx_use_id)
+            goto retry_read;
+        if (hci_used_id == SSV6XXX_ID_HCI_INPUT_QUEUE)
+            goto retry_read;
+#endif
+        hw_resource.free_tx_page =(int)
+                                  SSV6XXX_PAGE_TX_THRESHOLD(ctrl_hci) - (int)txq_info2.tx_use_page;
+        hw_resource.free_tx_id = (int) SSV6XXX_ID_TX_THRESHOLD(ctrl_hci) - (int)txq_info2.tx_use_id;
+        hw_resource.max_tx_frame[4] = (int)SSV6XXX_ID_MANAGER_QUEUE(ctrl_hci) - (int)txq_info2.txq4_size;
+        if (hci_used_id != -1)
+            max_count = (int) SSV6XXX_ID_HCI_INPUT_QUEUE - (int)hci_used_id;
+    } else {
+#ifdef SSV_SUPPORT_HAL
+        if (SSV_SC(ctrl_hci) != NULL)
+            ret = HAL_READRG_TXQ_INFO(ctrl_hci->shi->sh,(u32 *)&txq_info, &hci_used_id);
+        else {
+            HCI_DBG_PRINT(ctrl_hci, "%s: can't read txq_info due to software structure not initialized !!\n", __func__);
+            return 0;
+        }
+#else
+        ret = HCI_REG_READ(ctrl_hci, ADR_TX_ID_ALL_INFO, (u32 *)&txq_info);
+#endif
+        if (ret < 0) {
+            ctrl_hci->read_rs0_info_fail++;
+            return 0;
+        }
+        if (hci_used_id == SSV6XXX_ID_HCI_INPUT_QUEUE)
+            return 0;
+        BUG_ON(SSV6XXX_PAGE_TX_THRESHOLD(ctrl_hci) < txq_info.tx_use_page);
+        BUG_ON(SSV6XXX_ID_TX_THRESHOLD(ctrl_hci) < txq_info.tx_use_id);
+        hw_resource.free_tx_page = (int) SSV6XXX_PAGE_TX_THRESHOLD(ctrl_hci) - (int) txq_info.tx_use_page;
+        hw_resource.free_tx_id = (int) SSV6XXX_ID_TX_THRESHOLD(ctrl_hci) - (int) txq_info.tx_use_id;
+        hw_resource.max_tx_frame[0] =
+            (int) SSV6XXX_ID_AC_BK_OUT_QUEUE(ctrl_hci) - (int)txq_info.txq0_size;
+        hw_resource.max_tx_frame[1] =
+            (int)SSV6XXX_ID_AC_BE_OUT_QUEUE(ctrl_hci) - (int)txq_info.txq1_size;
+        hw_resource.max_tx_frame[2] =
+            (int)SSV6XXX_ID_AC_VI_OUT_QUEUE(ctrl_hci) - (int)txq_info.txq2_size;
+        hw_resource.max_tx_frame[3] =
+            (int)SSV6XXX_ID_AC_VO_OUT_QUEUE(ctrl_hci) - (int)txq_info.txq3_size;
+        if (hci_used_id != -1)
+            max_count = (int)SSV6XXX_ID_HCI_INPUT_QUEUE - (int)hci_used_id;
+    }
+    {
+#ifdef CONFIG_IRQ_DEBUG_COUNT
+        if(ctrl_hci->irq_enable)
+            ctrl_hci->real_tx_irq_count++;
+#endif
+        tx_count = ssv6xxx_hci_xmit(ctrl_hci, hw_txq, max_count, &hw_resource);
+    }
+    if ( (ctrl_hci->shi->hci_tx_q_empty_cb != NULL)
+         && (skb_queue_len(&hw_txq->qhead) == 0)) {
+        ctrl_hci->shi->hci_tx_q_empty_cb(hw_txq->txq_no, SSV_SC(ctrl_hci));
+    }
+    return tx_count;
+}
+static int ssv6xxx_hci_usb_tx_handler(struct ssv6xxx_hci_ctrl *ctrl_hci, void *dev, int max_count, int *err)
+{
+    struct ssv6xxx_hci_txq_info txq_info;
+    struct ssv6xxx_hci_txq_info2 txq_info2;
+    struct ssv6xxx_hw_resource hw_resource;
+    struct ssv_hw_txq *hw_txq=dev;
+    int hci_used_id = -1;
+    int ret, tx_count=0;
+    max_count = skb_queue_len(&hw_txq->qhead);
+    if (max_count == 0)
+        return 0;
+    if ((ctrl_hci->hci_start == false) || (hw_txq->paused)) {
+        *err = 1;
+        return 0;
+    }
+    if (hw_txq->txq_no == 4) {
+#ifndef _x86_64
+retry_read:
+#endif
+#ifdef SSV_SUPPORT_HAL
+        if (SSV_SC(ctrl_hci) != NULL)
+            ret = HAL_READRG_TXQ_INFO2(ctrl_hci->shi->sh,(u32 *)&txq_info2, &hci_used_id);
+        else {
+            HCI_DBG_PRINT(ctrl_hci, "%s: can't read txq_info2 due to software structure not initialized !!\n", __func__);
+            *err = -EIO;
+            return 0;
+        }
+#else
+        ret = HCI_REG_READ(ctrl_hci, ADR_TX_ID_ALL_INFO2, (u32 *)&txq_info2);
+#endif
+        if (ret < 0) {
+            ctrl_hci->read_rs1_info_fail++;
+            *err = -EIO;
+            return 0;
+        }
+#ifdef _x86_64
+        BUG_ON(SSV6XXX_PAGE_TX_THRESHOLD(ctrl_hci) < txq_info2.tx_use_page);
+        BUG_ON(SSV6XXX_ID_TX_THRESHOLD(ctrl_hci) < txq_info2.tx_use_id);
+#else
+        if(SSV6XXX_PAGE_TX_THRESHOLD(ctrl_hci) < txq_info2.tx_use_page)
+            goto retry_read;
+        if(SSV6XXX_ID_TX_THRESHOLD(ctrl_hci) < txq_info2.tx_use_id)
+            goto retry_read;
+        if (hci_used_id == SSV6XXX_ID_HCI_INPUT_QUEUE)
+            goto retry_read;
+#endif
+        hw_resource.free_tx_page =
+            SSV6XXX_PAGE_TX_THRESHOLD(ctrl_hci) - txq_info2.tx_use_page;
+        hw_resource.free_tx_id = SSV6XXX_ID_TX_THRESHOLD(ctrl_hci) - txq_info2.tx_use_id;
+        hw_resource.max_tx_frame[4] = SSV6XXX_ID_USB_MANAGER_QUEUE(ctrl_hci) - txq_info2.txq4_size;
+        if (hci_used_id != -1)
+            max_count = SSV6XXX_ID_HCI_INPUT_QUEUE - hci_used_id;
+    } else {
+#ifdef SSV_SUPPORT_HAL
+        if (SSV_SC(ctrl_hci) != NULL)
+            ret = HAL_READRG_TXQ_INFO(ctrl_hci->shi->sh,(u32 *)&txq_info, &hci_used_id);
+        else {
+            HCI_DBG_PRINT(ctrl_hci, "%s: can't read txq_info due to software structure not initialized !!\n", __func__);
+            *err = -EIO;
+            return 0;
+        }
+#else
+        ret = HCI_REG_READ(ctrl_hci, ADR_TX_ID_ALL_INFO, (u32 *)&txq_info);
+#endif
+        if (ret < 0) {
+            ctrl_hci->read_rs0_info_fail++;
+            *err = -EIO;
+            return 0;
+        }
+        if (hci_used_id == SSV6XXX_ID_HCI_INPUT_QUEUE) {
+            *err = 2;
+            return 0;
+        }
+        if (SSV6XXX_PAGE_TX_THRESHOLD(ctrl_hci) < txq_info.tx_use_page) {
+            *err = -EIO;
+            return 0;
+        }
+        if (SSV6XXX_ID_TX_THRESHOLD(ctrl_hci) < txq_info.tx_use_id) {
+            *err = -EIO;
+            return 0;
+        }
+        hw_resource.free_tx_page = (int) SSV6XXX_PAGE_TX_THRESHOLD(ctrl_hci) - (int)txq_info.tx_use_page;
+        hw_resource.free_tx_id = (int) SSV6XXX_ID_TX_THRESHOLD(ctrl_hci) - (int) txq_info.tx_use_id;
+        hw_resource.max_tx_frame[0] =(int)
+                                     SSV6XXX_ID_USB_AC_BK_OUT_QUEUE(ctrl_hci) - (int)txq_info.txq0_size;
+        hw_resource.max_tx_frame[1] =(int)
+                                     SSV6XXX_ID_USB_AC_BE_OUT_QUEUE(ctrl_hci) - (int)txq_info.txq1_size;
+        hw_resource.max_tx_frame[2] =(int)
+                                     SSV6XXX_ID_USB_AC_VI_OUT_QUEUE(ctrl_hci) - (int)txq_info.txq2_size;
+        hw_resource.max_tx_frame[3] =(int)
+                                     SSV6XXX_ID_USB_AC_VO_OUT_QUEUE(ctrl_hci) - (int)txq_info.txq3_size;
+        if (hci_used_id != -1) {
+            max_count = (int)SSV6XXX_ID_HCI_INPUT_QUEUE - (int)hci_used_id;
+        }
+        if (hw_resource.max_tx_frame[3] < 0) {
+            *err = -EIO;
+            return 0;
+        }
+        if (hw_resource.max_tx_frame[2] < 0) {
+            *err = -EIO;
+            return 0;
+        }
+        if (hw_resource.max_tx_frame[1] < 0) {
+            *err = -EIO;
+            return 0;
+        }
+        if (hw_resource.max_tx_frame[0] < 0) {
+            *err = -EIO;
+            return 0;
+        }
+    }
+    {
+#ifdef CONFIG_IRQ_DEBUG_COUNT
+        if(ctrl_hci->irq_enable)
+            ctrl_hci->real_tx_irq_count++;
+#endif
+        tx_count = ssv6xxx_hci_xmit(ctrl_hci, hw_txq, max_count, &hw_resource);
+    }
+    if ( (ctrl_hci->shi->hci_tx_q_empty_cb != NULL)
+         && (skb_queue_len(&hw_txq->qhead) == 0)) {
+        ctrl_hci->shi->hci_tx_q_empty_cb(hw_txq->txq_no, SSV_SC(ctrl_hci));
+    }
+    return tx_count;
+}
+void ssv6xxx_hci_tx_work(struct work_struct *work)
+{
+    struct ssv6xxx_hci_ctrl *ctrl_hci;
+    ctrl_hci = container_of(work, struct ssv6xxx_hci_ctrl, hci_tx_work);
+#ifdef CONFIG_SSV_TX_LOWTHRESHOLD
+    ssv6xxx_hci_irq_register(ctrl_hci, SSV6XXX_INT_RESOURCE_LOW);
+#else
+    int txqid;
+    for(txqid = SSV_HW_TXQ_NUM - 1; txqid >= 0; txqid--) {
+        u32 bitno;
+        if (&ctrl_hci->hci_tx_work[txqid] != work)
+            continue;
+        bitno = ssv6xxx_hci_get_int_bitno(txqid);
+        ssv6xxx_hci_irq_register(1<<(bitno));
+        break;
+    }
+#endif
+}
+static int _do_rx (struct ssv6xxx_hci_ctrl *hctl, u32 isr_status)
+{
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+    struct sk_buff_head rx_list;
+#endif
+    struct sk_buff *rx_mpdu;
+    int ret = 0;
+    int rx_cnt, next_pkt_len;
+    size_t dlen;
+    u32 status = isr_status;
+    u32 rx_mode, frame_size;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+    struct timespec rx_io_start_time, rx_io_end_time, rx_io_diff_time;
+    struct timespec rx_proc_start_time, rx_proc_end_time, rx_proc_diff_time;
+#endif
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+    memset(&rx_io_end_time, 0, sizeof(struct timespec));
+    memset(&rx_io_start_time, 0, sizeof(struct timespec));
+    memset(&rx_proc_start_time, 0, sizeof(struct timespec));
+#endif
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+    skb_queue_head_init(&rx_list);
+#endif
+    rx_mode = hctl->shi->hci_rx_mode_cb((void *)(SSV_SC(hctl)));
+    frame_size = (rx_mode & RX_HW_AGG_MODE) ? MAX_HCI_RX_AGGR_SIZE : MAX_FRAME_SIZE_DMG;
+    frame_size += MAX_RX_PKT_RSVD;
+    next_pkt_len = 0;
+    for (rx_cnt = 0; (status & SSV6XXX_INT_RX) && (rx_cnt < 32 ); rx_cnt++) {
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+        if (hctl->isr_mib_enable)
+            getnstimeofday(&rx_io_start_time);
+#endif
+        dlen = next_pkt_len;
+        ret = IF_RECV(hctl, hctl->rx_buf->data, &dlen, rx_mode);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+        if (hctl->isr_mib_enable)
+            getnstimeofday(&rx_io_end_time);
+#endif
+        if (ret < 0 || dlen<=0) {
+            HCI_DBG_PRINT(hctl, "%s(): IF_RECV() retruns %d (dlen=%d)\n", __FUNCTION__, ret, (int)dlen);
+            if (ret != -84 || dlen>frame_size)
+                break;
+        }
+        rx_mpdu = hctl->rx_buf;
+        hctl->rx_buf = hctl->shi->skb_alloc((void *)(SSV_SC(hctl)), frame_size);
+        if (hctl->rx_buf == NULL) {
+            HCI_DBG_PRINT(hctl, "RX buffer allocation failure!\n");
+            hctl->rx_buf = rx_mpdu;
+            break;
+        }
+        hctl->rx_pkt++;
+#ifdef CONFIG_IRQ_DEBUG_COUNT
+        if (hctl->irq_enable) {
+            hctl->irq_rx_pkt_count ++;
+        }
+#endif
+        skb_put(rx_mpdu, dlen);
+        next_pkt_len = hctl->shi->hci_peek_next_pkt_len_cb(rx_mpdu, (void *)(SSV_SC(hctl)));
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+        if (hctl->isr_mib_enable)
+            getnstimeofday(&rx_proc_start_time);
+#endif
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+        __skb_queue_tail(&rx_list, rx_mpdu);
+#else
+        hctl->shi->hci_rx_cb(rx_mpdu, (void *)(SSV_SC(hctl)));
+#endif
+        if (next_pkt_len == 0)
+            HCI_IRQ_STATUS(hctl, &status);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+        if (hctl->isr_mib_enable) {
+            getnstimeofday(&rx_proc_end_time);
+            hctl->isr_rx_io_count++;
+            rx_io_diff_time = timespec_sub(rx_io_end_time, rx_io_start_time);
+            hctl->isr_rx_io_time += timespec_to_ns(&rx_io_diff_time);
+            rx_proc_diff_time = timespec_sub(rx_proc_end_time, rx_proc_start_time);
+            hctl->isr_rx_proc_time += timespec_to_ns(&rx_proc_diff_time);
+        }
+#endif
+    }
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+    if (hctl->isr_mib_enable)
+        getnstimeofday(&rx_proc_start_time);
+#endif
+    hctl->shi->hci_rx_cb(&rx_list, (void *)(SSV_SC(hctl)));
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+    if (hctl->isr_mib_enable) {
+        getnstimeofday(&rx_proc_end_time);
+        rx_proc_diff_time = timespec_sub(rx_proc_end_time, rx_proc_start_time);
+        hctl->isr_rx_proc_time += timespec_to_ns(&rx_proc_diff_time);
+    }
+#endif
+#endif
+    return ret;
+}
+static void ssv6xxx_hci_rx_work(struct work_struct *work)
+{
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+    struct sk_buff_head rx_list;
+#endif
+    struct sk_buff *rx_mpdu;
+    int rx_cnt, ret, next_pkt_len;
+    size_t dlen;
+    int status;
+    u32 rx_mode, frame_size;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+    struct timespec rx_io_start_time, rx_io_end_time, rx_io_diff_time;
+    struct timespec rx_proc_start_time, rx_proc_end_time, rx_proc_diff_time;
+#endif
+    struct ssv6xxx_hci_ctrl *ctrl_hci;
+    struct ssv6xxx_hci_info *shi;
+    ctrl_hci = container_of(work, struct ssv6xxx_hci_ctrl, hci_rx_work);
+    shi = ctrl_hci->shi;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+    memset(&rx_io_end_time, 0, sizeof(struct timespec));
+    memset(&rx_io_start_time, 0, sizeof(struct timespec));
+    memset(&rx_proc_start_time, 0, sizeof(struct timespec));
+#endif
+    ctrl_hci->rx_work_running = 1;
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+    skb_queue_head_init(&rx_list);
+#endif
+    rx_mode = shi->hci_rx_mode_cb((void *)(SSV_SC(ctrl_hci)));
+    frame_size = (rx_mode & RX_HW_AGG_MODE) ? MAX_HCI_RX_AGGR_SIZE : MAX_FRAME_SIZE_DMG;
+    frame_size += MAX_RX_PKT_RSVD;
+    next_pkt_len = 0;
+    status = SSV6XXX_INT_RX;
+    for (rx_cnt = 0; (status & SSV6XXX_INT_RX) && (rx_cnt < 32 ); rx_cnt++) {
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+        if (ctrl_hci->isr_mib_enable)
+            getnstimeofday(&rx_io_start_time);
+#endif
+        dlen = next_pkt_len;
+        ret = IF_RECV(ctrl_hci, ctrl_hci->rx_buf->data, &dlen, rx_mode);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+        if (ctrl_hci->isr_mib_enable)
+            getnstimeofday(&rx_io_end_time);
+#endif
+        if (ret < 0 || dlen<=0) {
+            HCI_DBG_PRINT(ctrl_hci, "%s(): IF_RECV() retruns %d (dlen=%d)\n", __FUNCTION__, ret, (int)dlen);
+            if (ret != -84 || dlen>frame_size)
+                break;
+        }
+        rx_mpdu = ctrl_hci->rx_buf;
+        ctrl_hci->rx_buf = shi->skb_alloc((void *)(SSV_SC(ctrl_hci)), frame_size);
+        if (ctrl_hci->rx_buf == NULL) {
+            HCI_DBG_PRINT(ctrl_hci, "RX buffer allocation failure!\n");
+            ctrl_hci->rx_buf = rx_mpdu;
+            break;
+        }
+        ctrl_hci->rx_pkt ++;
+#ifdef CONFIG_IRQ_DEBUG_COUNT
+        if(ctrl_hci->irq_enable) {
+            ctrl_hci->irq_rx_pkt_count ++;
+        }
+#endif
+        skb_put(rx_mpdu, dlen);
+        next_pkt_len = shi->hci_peek_next_pkt_len_cb(rx_mpdu, (void *)(SSV_SC(ctrl_hci)));
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+        if (ctrl_hci->isr_mib_enable)
+            getnstimeofday(&rx_proc_start_time);
+#endif
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+        __skb_queue_tail(&rx_list, rx_mpdu);
+#else
+        shi->hci_rx_cb(rx_mpdu, (void *)(SSV_SC(ctrl_hci)));
+#endif
+        if (next_pkt_len == 0)
+            HCI_IRQ_STATUS(ctrl_hci, &status);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+        if (ctrl_hci->isr_mib_enable) {
+            getnstimeofday(&rx_proc_end_time);
+            ctrl_hci->isr_rx_io_count++;
+            rx_io_diff_time = timespec_sub(rx_io_end_time, rx_io_start_time);
+            ctrl_hci->isr_rx_io_time += timespec_to_ns(&rx_io_diff_time);
+            rx_proc_diff_time = timespec_sub(rx_proc_end_time, rx_proc_start_time);
+            ctrl_hci->isr_rx_proc_time += timespec_to_ns(&rx_proc_diff_time);
+        }
+#endif
+    }
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+    if (ctrl_hci->isr_mib_enable)
+        getnstimeofday(&rx_proc_start_time);
+#endif
+    shi->hci_rx_cb(&rx_list, (void *)(SSV_SC(ctrl_hci)));
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+    if (ctrl_hci->isr_mib_enable) {
+        getnstimeofday(&rx_proc_end_time);
+        rx_proc_diff_time = timespec_sub(rx_proc_end_time, rx_proc_start_time);
+        ctrl_hci->isr_rx_proc_time += timespec_to_ns(&rx_proc_diff_time);
+    }
+#endif
+#endif
+    ctrl_hci->rx_work_running = 0;
+}
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+static void ssv6xxx_isr_mib_reset (struct ssv6xxx_hci_ctrl *ctrl_hci)
+{
+    ctrl_hci->isr_mib_reset = 0;
+    ctrl_hci->isr_total_time = 0;
+    ctrl_hci->isr_rx_io_time = 0;
+    ctrl_hci->isr_tx_io_time = 0;
+    ctrl_hci->isr_rx_io_count = 0;
+    ctrl_hci->isr_tx_io_count = 0;
+    ctrl_hci->isr_rx_proc_time =0;
+}
+static int hw_txq_len_open(struct inode *inode, struct file *filp)
+{
+    filp->private_data = inode->i_private;
+    return 0;
+}
+static ssize_t hw_txq_len_read(struct file *filp, char __user *buffer, size_t count, loff_t *ppos)
+{
+    ssize_t ret;
+    struct ssv6xxx_hci_ctrl *hctl = (struct ssv6xxx_hci_ctrl *)filp->private_data;
+    char *summary_buf = kzalloc(1024, GFP_KERNEL);
+    char *prn_ptr = summary_buf;
+    int prt_size;
+    int buf_size = 1024;
+    int i=0;
+    if (!summary_buf)
+        return -ENOMEM;
+    for (i=0; i<SSV_HW_TXQ_NUM; i++) {
+        prt_size = snprintf(prn_ptr, buf_size, "\n\rhw_txq%d_len: %d", i,
+                            skb_queue_len(&hctl->hw_txq[i].qhead));
+        prn_ptr += prt_size;
+        buf_size -= prt_size;
+    }
+    buf_size = 1024 - buf_size;
+    ret = simple_read_from_buffer(buffer, count, ppos, summary_buf, buf_size);
+    kfree(summary_buf);
+    return ret;
+}
+#if 0
+static ssize_t hw_txq_len_write(struct file *filp, const char __user *buffer, size_t count, loff_t *ppos)
+{
+    return 0;
+}
+#endif
+struct file_operations hw_txq_len_fops = {
+    .owner = THIS_MODULE,
+    .open = hw_txq_len_open,
+    .read = hw_txq_len_read,
+};
+bool tu_ssv6xxx_hci_init_debugfs(struct ssv6xxx_hci_ctrl *ctrl_hci, struct dentry *dev_deugfs_dir)
+{
+    ctrl_hci->debugfs_dir = debugfs_create_dir("hci", dev_deugfs_dir);
+    if (ctrl_hci->debugfs_dir == NULL) {
+        HCI_DBG_PRINT(ctrl_hci, "Failed to create HCI debugfs directory.\n");
+        return false;
+    }
+    debugfs_create_u32("TXQ_mask", 00444, ctrl_hci->debugfs_dir, &ctrl_hci->txq_mask);
+    debugfs_create_u32("hci_isr_mib_enable", 00644, ctrl_hci->debugfs_dir, &ctrl_hci->isr_mib_enable);
+    debugfs_create_u32("hci_isr_mib_reset", 00644, ctrl_hci->debugfs_dir, &ctrl_hci->isr_mib_reset);
+    debugfs_create_u64("isr_total_time", 00444, ctrl_hci->debugfs_dir, &ctrl_hci->isr_total_time);
+    debugfs_create_u64("tx_io_time", 00444, ctrl_hci->debugfs_dir, &ctrl_hci->isr_tx_io_time);
+    debugfs_create_u64("rx_io_time", 00444, ctrl_hci->debugfs_dir, &ctrl_hci->isr_rx_io_time);
+    debugfs_create_u32("tx_io_count", 00444, ctrl_hci->debugfs_dir, &ctrl_hci->isr_tx_io_count);
+    debugfs_create_u32("rx_io_count", 00444, ctrl_hci->debugfs_dir, &ctrl_hci->isr_rx_io_count);
+    debugfs_create_u64("rx_proc_time", 00444, ctrl_hci->debugfs_dir, &ctrl_hci->isr_rx_proc_time);
+    debugfs_create_file("hw_txq_len", 00444, ctrl_hci->debugfs_dir, ctrl_hci, &hw_txq_len_fops);
+    return true;
+}
+void ssv6xxx_hci_deinit_debugfs(struct ssv6xxx_hci_ctrl *ctrl_hci)
+{
+    if (ctrl_hci->debugfs_dir == NULL)
+        return;
+    ctrl_hci->debugfs_dir = NULL;
+}
+#endif
+static int _isr_do_rx (struct ssv6xxx_hci_ctrl *hctl, u32 isr_status)
+{
+    int retval;
+    u32 before = jiffies;
+#ifdef CONFIG_IRQ_DEBUG_COUNT
+    if (hctl->irq_enable)
+        hctl->rx_irq_count++;
+#endif
+    if (hctl->isr_summary_eable
+        && hctl->prev_rx_isr_jiffes) {
+        if (hctl->isr_rx_idle_time) {
+            hctl->isr_rx_idle_time += (jiffies - hctl->prev_rx_isr_jiffes);
+            hctl->isr_rx_idle_time = hctl->isr_rx_idle_time >>1;
+        } else {
+            hctl->isr_rx_idle_time += (jiffies - hctl->prev_rx_isr_jiffes);
+        }
+    }
+    retval = _do_rx(hctl, isr_status);
+    if(hctl->isr_summary_eable) {
+        if(hctl->isr_rx_time) {
+            hctl->isr_rx_time += (jiffies-before);
+            hctl->isr_rx_time = hctl->isr_rx_time >>1;
+        } else {
+            hctl->isr_rx_time += (jiffies-before);
+        }
+        hctl->prev_rx_isr_jiffes = jiffies;
+    }
+    return retval;
+}
+static bool ssv6xxx_hci_is_frame_send(struct ssv6xxx_hci_ctrl *hci_ctrl)
+{
+    int q_num;
+    struct ssv_hw_txq *hw_txq;
+    for (q_num = (SSV_HW_TXQ_NUM - 1); q_num >= 0; q_num--) {
+        hw_txq = &hci_ctrl->hw_txq[q_num];
+        if (!hw_txq->paused && !ssv6xxx_hci_is_txq_empty(hci_ctrl, q_num))
+            return true;
+    }
+    return false;
+}
+#ifdef CONFIG_SSV_TX_LOWTHRESHOLD
+static int _do_tx (struct ssv6xxx_hci_ctrl *hctl, u32 status)
+{
+    int q_num;
+    int tx_count = 0;
+    unsigned long flags;
+    struct ssv_hw_txq *hw_txq;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+    struct timespec tx_io_start_time, tx_io_end_time, tx_io_diff_time;
+#endif
+    int ret;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+    memset(&tx_io_start_time, 0, sizeof(struct timespec));
+#endif
+#ifdef CONFIG_IRQ_DEBUG_COUNT
+    if ((!(status & SSV6XXX_INT_RX)) && hctl->irq_enable)
+        hctl->tx_irq_count++;
+#endif
+    if ((status & SSV6XXX_INT_RESOURCE_LOW) == 0)
+        return 0;
+    for (q_num = (SSV_HW_TXQ_NUM - 1); q_num >= 0; q_num--) {
+        u32 before = jiffies;
+        hw_txq = &hctl->hw_txq[q_num];
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+        if (hctl->isr_mib_enable)
+            getnstimeofday(&tx_io_start_time);
+#endif
+        ret = ssv6xxx_hci_tx_handler(hctl, hw_txq, 999);
+        if (ret < 0) {
+            HCI_DBG_PRINT(hctl, "TX Handler failed.\n");
+            break;
+        } else
+            tx_count += ret;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+        if (hctl->isr_mib_enable) {
+            getnstimeofday(&tx_io_end_time);
+            tx_io_diff_time = timespec_sub(tx_io_end_time, tx_io_start_time);
+            hctl->isr_tx_io_time += timespec_to_ns(&tx_io_diff_time);
+        }
+#endif
+        if (hctl->isr_summary_eable) {
+            if (hctl->isr_tx_time) {
+                hctl->isr_tx_time += (jiffies-before);
+                hctl->isr_tx_time = hctl->isr_tx_time >>1;
+            } else {
+                hctl->isr_tx_time += (jiffies-before);
+            }
+        }
+    }
+    mutex_lock(&hctl->hci_mutex);
+    spin_lock_irqsave(&hctl->int_lock, flags);
+    if (!ssv6xxx_hci_is_frame_send(hctl)) {
+        u32 reg_val;
+        hctl->int_mask &= ~SSV6XXX_INT_RESOURCE_LOW;
+        reg_val = ~hctl->int_mask;
+        spin_unlock_irqrestore(&hctl->int_lock, flags);
+        HCI_IRQ_SET_MASK(hctl, reg_val);
+    } else {
+        spin_unlock_irqrestore(&hctl->int_lock, flags);
+    }
+    mutex_unlock(&hctl->hci_mutex);
+    return ((ret < 0) ? ret : tx_count);
+}
+#else
+static int _do_tx (struct ssv6xxx_hci_ctrl *hctl, u32 status)
+{
+    int q_num;
+    int tx_count = 0;
+    int ret;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+    struct timespec tx_io_start_time, tx_io_end_time, tx_io_diff_time;
+#endif
+#ifdef CONFIG_IRQ_DEBUG_COUNT
+    if ((!(status & SSV6XXX_INT_RX)) && hctl->irq_enable)
+        htcl->tx_irq_count++;
+#endif
+    for (q_num = (SSV_HW_TXQ_NUM - 1); q_num >= 0; q_num--) {
+        int bitno;
+        struct ssv_hw_txq *hw_txq;
+        unsigned long flags;
+        u32 before = jiffies;
+        hw_txq = &hctl->hw_txq[q_num];
+        bitno = ssv6xxx_hci_get_int_bitno(hw_txq->txq_no);
+        if ((status & BIT(bitno)) == 0)
+            continue;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+        if (htcl->isr_mib_enable) {
+            getnstimeofday(&tx_io_start_time);
+        }
+#endif
+        ret = ssv6xxx_hci_tx_handler(hctl, hw_txq, 999);
+        if (ret < 0) {
+            HCI_DBG_PRINT(hci_ctrl, "TX handler failed.\n");
+            break;
+        } else
+            tx_count += ret;
+        mutex_lock(&hctl->hci_mutex);
+        spin_lock_irqsave(&hctl->int_lock, flags);
+        if (skb_queue_len(&hw_txq->qhead) <= 0) {
+            u32 reg_val;
+            hctl->int_mask &= ~(1<<bitno);
+            reg_val = ~hctl->int_mask;
+            spin_unlock_irqrestore(&hctl->int_lock, flags);
+            HCI_IRQ_SET_MASK(hctl, reg_val);
+        } else {
+            spin_unlock_irqrestore(&hctl->int_lock, flags);
+        }
+        mutex_unlock(&hctl->hci_mutex);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+        if (htcl->isr_mib_enable) {
+            getnstimeofday(&tx_io_end_time);
+            tx_io_diff_time = timespec_sub(tx_io_end_time, tx_io_start_time);
+            htcl->isr_tx_io_time += timespec_to_ns(&tx_io_diff_time);
+        }
+#endif
+        if (htcl->isr_summary_eable) {
+            if (htcl->isr_tx_time) {
+                htcl->isr_tx_time += (jiffies - before);
+                htcl->isr_tx_time = htcl->isr_tx_time >>1;
+            } else {
+                htcl->isr_tx_time += (jiffies - before);
+            }
+        }
+    }
+    return ((ret < 0) ? ret : tx_count);
+}
+#endif
+static void ssv6xxx_hci_isr_reset(struct work_struct *work)
+{
+    struct ssv6xxx_hci_ctrl *ctrl_hci;
+    ctrl_hci = container_of(work, struct ssv6xxx_hci_ctrl, isr_reset_work);
+    HCI_DBG_PRINT(ctrl_hci, "ISR Reset!!!");
+    ssv6xxx_hci_irq_disable(ctrl_hci);
+    ssv6xxx_hci_irq_enable(ctrl_hci);
+}
+irqreturn_t ssv6xxx_hci_isr(int irq, void *args)
+{
+    struct ssv6xxx_hci_ctrl *hctl = args;
+    u32 status;
+    unsigned long flags;
+    int ret = IRQ_HANDLED;
+    bool dbg_isr_miss = true;
+    bool isr_reset = false;
+    bool first_time_check = true;
+    if (hctl->isr_summary_eable
+        && hctl->prev_isr_jiffes) {
+        if(hctl->isr_idle_time) {
+            hctl->isr_idle_time += (jiffies - hctl->prev_isr_jiffes);
+            hctl->isr_idle_time = hctl->isr_idle_time >>1;
+        } else {
+            hctl->isr_idle_time += (jiffies - hctl->prev_isr_jiffes);
+        }
+    }
+    BUG_ON(!args);
+#ifdef CONFIG_IRQ_DEBUG_COUNT
+    if(hctl->irq_enable)
+        hctl->irq_count++;
+#endif
+    do {
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+        struct timespec start_time, end_time, diff_time;
+        memset(&start_time, 0, sizeof(struct timespec));
+        if (hctl->isr_mib_reset)
+            ssv6xxx_isr_mib_reset(hctl);
+        if (hctl->isr_mib_enable)
+            getnstimeofday(&start_time);
+#endif
+        mutex_lock(&hctl->hci_mutex);
+        if (hctl->int_status) {
+            u32 regval;
+            spin_lock_irqsave(&hctl->int_lock, flags);
+            hctl->int_mask |= hctl->int_status;
+            hctl->int_status = 0;
+            regval = ~hctl->int_mask;
+            smp_mb();
+            spin_unlock_irqrestore(&hctl->int_lock, flags);
+            HCI_IRQ_SET_MASK(hctl, regval);
+        }
+        ret = HCI_IRQ_STATUS(hctl, &status);
+        if ((ret < 0) || ((status & hctl->int_mask) == 0)) {
+            if (first_time_check) {
+#ifdef CONFIG_IRQ_DEBUG_COUNT
+                if (hctl->irq_enable)
+                    hctl->invalid_irq_count++;
+#endif
+                ret = IRQ_NONE;
+            }
+            mutex_unlock(&hctl->hci_mutex);
+            break;
+        }
+        spin_lock_irqsave(&hctl->int_lock, flags);
+        status &= hctl->int_mask;
+        spin_unlock_irqrestore(&hctl->int_lock, flags);
+        mutex_unlock(&hctl->hci_mutex);
+        hctl->isr_running = 1;
+#ifdef CONFIG_SSV_TX_LOWTHRESHOLD
+        if (status & SSV6XXX_INT_RESOURCE_LOW) {
+#else
+        if (status & (SSV6XXX_INT_TX|SSV6XXX_INT_LOW_EDCA_0|SSV6XXX_INT_LOW_EDCA_1|SSV6XXX_INT_LOW_EDCA_2|SSV6XXX_INT_LOW_EDCA_3)) {
+#endif
+            ret = _do_tx(hctl, status);
+            if (ret > 0) {
+                dbg_isr_miss = false;
+            } else if (ret < 0) {
+                isr_reset = true;
+                hctl->isr_running = 0;
+                break;
+            }
+        }
+        if (status & SSV6XXX_INT_RX) {
+            ret = _isr_do_rx(hctl, status);
+            if (ret < 0) {
+                isr_reset = true;
+                hctl->isr_running = 0;
+                HCI_DBG_PRINT(hctl, "do_rx failed\n");
+                break;
+            }
+            dbg_isr_miss = false;
+        } else {
+            hctl->isr_running = 0;
+            break;
+        }
+        hctl->isr_running = 0;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+        if (hctl->isr_mib_enable) {
+            getnstimeofday(&end_time);
+            diff_time = timespec_sub(end_time, start_time);
+            hctl->isr_total_time += timespec_to_ns(&diff_time);
+        }
+#endif
+        first_time_check = false;
+    }
+    while (1);
+    if (hctl->isr_summary_eable ) {
+        if(dbg_isr_miss)
+            hctl->isr_miss_cnt++;
+        hctl->prev_isr_jiffes = jiffies;
+    }
+    if (isr_reset == true)
+        queue_work(hctl->hci_work_queue, &hctl->isr_reset_work);
+    return ret;
+}
+static int ssv6xxx_hci_tx_task (void *data)
+{
+#define MAX_HCI_TX_TASK_SEND_FAIL 3
+    struct ssv6xxx_hci_ctrl *hctl = (struct ssv6xxx_hci_ctrl *)data;
+    unsigned long wait_period = msecs_to_jiffies(200);
+    int err = 0, err_cnt = 0;
+    txrxboost_init();
+    printk("SSV6XXX HCI TX Task started.\n");
+    while (!kthread_should_stop()) {
+        wait_event_interruptible_timeout(hctl->tx_wait_q,
+                                         ( kthread_should_stop()
+                                           || ssv6xxx_hci_is_frame_send(hctl)),
+                                         wait_period);
+        if (kthread_should_stop()) {
+            hctl->hci_tx_task = NULL;
+            HCI_DBG_PRINT(hctl, "Quit HCI TX task loop...\n");
+            break;
+        }
+        txrxboost_change((u32)atomic_read(&SSV_SC(hctl)->ampdu_tx_frame),
+                         SSV_SC(hctl)->sh->cfg.txrxboost_low_threshold,
+                         SSV_SC(hctl)->sh->cfg.txrxboost_high_threshold,
+                         SSV_SC(hctl)->sh->cfg.txrxboost_prio);
+        if ((hctl->hci_flags & SSV6XXX_HCI_OP_INVALID) ||
+            (hctl->hci_flags & SSV6XXX_HCI_OP_IFERR) ||
+            (err_cnt > MAX_HCI_TX_TASK_SEND_FAIL)) {
+            ssv6xxx_hci_txq_flush(hctl, (TXQ_EDCA_0|TXQ_EDCA_1|TXQ_EDCA_2|TXQ_EDCA_3|TXQ_MGMT));
+            //ssv6xxx_hci_txq_flush(hctl, (TXQ_EDCA_0|TXQ_EDCA_1|TXQ_EDCA_2|TXQ_EDCA_3|TXQ_MGMT));
+            err_cnt = 0;
+        } else {
+            if (ssv6xxx_hci_is_frame_send(hctl)) {
+                err = 0;
+                _do_force_tx(hctl, &err);
+                if ((err < 0) && (err != -1)) {
+                    err_cnt++;
+                } else if (err == -1) {
+                    hctl->hci_flags |= SSV6XXX_HCI_OP_IFERR;
+                }
+            }
+        }
+    }
+    return 0;
+}
+static struct ssv6xxx_hci_ops hci_ops = {
+    .hci_start = ssv6xxx_hci_start,
+    .hci_stop = ssv6xxx_hci_stop,
+    .hci_write_hw_config = ssv6xxx_hci_write_hw_config,
+    .hci_read_word = ssv6xxx_hci_read_word,
+    .hci_write_word = ssv6xxx_hci_write_word,
+    .hci_safe_read_word = ssv6xxx_hci_safe_read_word,
+    .hci_safe_write_word = ssv6xxx_hci_safe_write_word,
+    .hci_burst_read_word = ssv6xxx_hci_burst_read_word,
+    .hci_burst_write_word = ssv6xxx_hci_burst_write_word,
+    .hci_burst_safe_read_word = ssv6xxx_hci_burst_safe_read_word,
+    .hci_burst_safe_write_word = ssv6xxx_hci_burst_safe_write_word,
+    .hci_tx = ssv6xxx_hci_enqueue,
+    .hci_tx_pause = ssv6xxx_hci_txq_pause,
+    .hci_tx_resume = ssv6xxx_hci_txq_resume,
+    .hci_txq_flush = ssv6xxx_hci_txq_flush,
+    .hci_txq_flush_by_sta = ssv6xxx_hci_txq_flush_by_sta,
+    .hci_txq_empty = ssv6xxx_hci_is_txq_empty,
+    .hci_load_fw = ssv6xxx_hci_load_fw,
+    .hci_pmu_wakeup = ssv6xxx_hci_pmu_wakeup,
+    .hci_send_cmd = ssv6xxx_hci_send_cmd,
+    .hci_write_sram = ssv6xxx_hci_write_sram,
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+    .hci_init_debugfs = tu_ssv6xxx_hci_init_debugfs,
+    .hci_deinit_debugfs = ssv6xxx_hci_deinit_debugfs,
+#endif
+    .hci_interface_reset = ssv6xxx_hci_interface_reset,
+    .hci_sysplf_reset = ssv6xxx_hci_sysplf_reset,
+};
+int tu_ssv6xxx_hci_deregister(struct ssv6xxx_hci_info *shi)
+{
+    u32 regval;
+    struct ssv6xxx_hci_ctrl *hci_ctrl;
+    printk("%s(): \n", __FUNCTION__);
+    if (shi->hci_ctrl == NULL)
+        return -1;
+    hci_ctrl = shi->hci_ctrl;
+    hci_ctrl->hci_flags |= SSV6XXX_HCI_OP_INVALID;
+    regval = 1;
+    ssv6xxx_hci_txq_flush(hci_ctrl, (TXQ_EDCA_0|TXQ_EDCA_1|TXQ_EDCA_2|TXQ_EDCA_3|TXQ_MGMT));
+    ssv6xxx_hci_irq_disable(hci_ctrl);
+    flush_workqueue(hci_ctrl->hci_work_queue);
+    destroy_workqueue(hci_ctrl->hci_work_queue);
+    if (hci_ctrl->hci_tx_task != NULL) {
+        printk("Stopping HCI TX task...\n");
+        kthread_stop(hci_ctrl->hci_tx_task);
+        hci_ctrl->hci_tx_task = NULL;
+        printk("Stopped HCI TX task.\n");
+    }
+    if (hci_ctrl->rx_buf != NULL) {
+        dev_kfree_skb_any(hci_ctrl->rx_buf);
+    }
+    shi->hci_ctrl = NULL;
+    kfree(hci_ctrl);
+    return 0;
+}
+EXPORT_SYMBOL(tu_ssv6xxx_hci_deregister);
+int tu_ssv6xxx_hci_register(struct ssv6xxx_hci_info *shi)
+{
+    int i, capability;
+    struct ssv6xxx_hci_ctrl *hci_ctrl;
+    if (shi == NULL ) {
+        printk(KERN_ERR "NULL sh when register HCI.\n");
+        return -1;
+    }
+    hci_ctrl = kzalloc(sizeof(*hci_ctrl), GFP_KERNEL);
+    if (hci_ctrl == NULL)
+        return -ENOMEM;
+    memset((void *)hci_ctrl, 0, sizeof(*hci_ctrl));
+    shi->hci_ctrl = hci_ctrl;
+    shi->hci_ops = &hci_ops;
+    hci_ctrl->shi = shi;
+    hci_ctrl->rx_buf = shi->skb_alloc((void *)(SSV_SC(hci_ctrl)), MAX_HCI_RX_AGGR_SIZE);
+    if (hci_ctrl->rx_buf == NULL) {
+        kfree(hci_ctrl);
+        return -ENOMEM;
+    }
+    hci_ctrl->txq_mask = 0;
+    mutex_init(&hci_ctrl->txq_mask_lock);
+    mutex_init(&hci_ctrl->hci_mutex);
+    spin_lock_init(&hci_ctrl->int_lock);
+#ifdef CONFIG_IRQ_DEBUG_COUNT
+    hci_ctrl->irq_enable = false;
+    hci_ctrl->irq_count = 0;
+    hci_ctrl->invalid_irq_count = 0;
+    hci_ctrl->tx_irq_count = 0;
+    hci_ctrl->real_tx_irq_count = 0;
+    hci_ctrl->rx_irq_count = 0;
+    hci_ctrl->irq_rx_pkt_count = 0;
+    hci_ctrl->irq_tx_pkt_count = 0;
+#endif
+    for (i=0; i < SSV_HW_TXQ_NUM; i++) {
+        memset(&hci_ctrl->hw_txq[i], 0, sizeof(struct ssv_hw_txq));
+        skb_queue_head_init(&hci_ctrl->hw_txq[i].qhead);
+        hci_ctrl->hw_txq[i].txq_no = (u32)i;
+        hci_ctrl->hw_txq[i].max_qsize = SSV_HW_TXQ_MAX_SIZE;
+        hci_ctrl->hw_txq[i].resum_thres = SSV_HW_TXQ_RESUME_THRES;
+    }
+    hci_ctrl->hci_work_queue = create_singlethread_workqueue("ssv6xxx_hci_wq");
+    INIT_WORK(&hci_ctrl->isr_reset_work, ssv6xxx_hci_isr_reset);
+    INIT_WORK(&hci_ctrl->hci_rx_work, ssv6xxx_hci_rx_work);
+#ifdef CONFIG_SSV_TX_LOWTHRESHOLD
+    INIT_WORK(&hci_ctrl->hci_tx_work, ssv6xxx_hci_tx_work);
+#else
+    for(i=0; i<SSV_HW_TXQ_NUM; i++)
+        INIT_WORK(&hci_ctrl->hci_tx_work[i], ssv6xxx_hci_tx_work);
+#endif
+    capability = (HCI_HWIF_PROPERTY(hci_ctrl) & SSV_HWIF_CAPABILITY_MASK);
+    switch (capability) {
+    case SSV_HWIF_CAPABILITY_INTERRUPT:
+#ifdef CONFIG_SSV_TX_LOWTHRESHOLD
+        hci_ctrl->int_mask = SSV6XXX_INT_RX|SSV6XXX_INT_RESOURCE_LOW;
+#else
+        hci_ctrl->int_mask = SSV6XXX_INT_RX|SSV6XXX_INT_TX|SSV6XXX_INT_LOW_EDCA_0|
+                             SSV6XXX_INT_LOW_EDCA_1|SSV6XXX_INT_LOW_EDCA_2|SSV6XXX_INT_LOW_EDCA_3;
+#endif
+        hci_ctrl->isr_disable = false;
+        hci_ctrl->int_status= 0;
+        HCI_IRQ_SET_MASK(hci_ctrl, 0xFFFFFFFF);
+        ssv6xxx_hci_irq_disable(hci_ctrl);
+        HCI_IRQ_REQUEST(hci_ctrl, ssv6xxx_hci_isr);
+        break;
+    case SSV_HWIF_CAPABILITY_POLLING:
+        hci_ctrl->isr_disable = true;
+        init_waitqueue_head(&hci_ctrl->tx_wait_q);
+        hci_ctrl->hci_tx_task = kthread_run(ssv6xxx_hci_tx_task, hci_ctrl, "ssv6xxx_hci_tx_task");
+        HCI_RX_TASK(hci_ctrl, hci_ctrl->shi->hci_rx_cb, hci_ctrl->shi->hci_is_rx_q_full, (void *)(SSV_SC(hci_ctrl)), &hci_ctrl->rx_pkt);
+        break;
+    default:
+        printk("Detect unknown hardware capability\n");
+        return -1;
+    }
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+    hci_ctrl->debugfs_dir = NULL;
+    hci_ctrl->isr_mib_enable = false;
+    hci_ctrl->isr_mib_reset = 0;
+    hci_ctrl->isr_total_time = 0;
+    hci_ctrl->isr_rx_io_time = 0;
+    hci_ctrl->isr_tx_io_time = 0;
+    hci_ctrl->isr_rx_io_count = 0;
+    hci_ctrl->isr_tx_io_count = 0;
+    hci_ctrl->isr_rx_proc_time =0;
+#endif
+    return 0;
+}
+EXPORT_SYMBOL(tu_ssv6xxx_hci_register);
+#if (defined(CONFIG_SSV_SUPPORT_ANDROID)||defined(CONFIG_SSV_BUILD_AS_ONE_KO))
+int tu_ssv6xxx_hci_init(void)
+#else
+int __init tu_ssv6xxx_hci_init(void)
+#endif
+{
+#ifdef CONFIG_SSV6200_CLI_ENABLE
+#endif
+#ifdef CONFIG_SSV6200_CLI_ENABLE
+#endif
+    return 0;
+}
+#if (defined(CONFIG_SSV_SUPPORT_ANDROID)||defined(CONFIG_SSV_BUILD_AS_ONE_KO))
+void tu_ssv6xxx_hci_exit(void)
+#else
+void __exit tu_ssv6xxx_hci_exit(void)
+#endif
+{
+#ifdef CONFIG_SSV6200_CLI_ENABLE
+#endif
+#ifdef CONFIG_SSV6200_CLI_ENABLE
+#endif
+}
+#if (defined(CONFIG_SSV_SUPPORT_ANDROID)||defined(CONFIG_SSV_BUILD_AS_ONE_KO))
+EXPORT_SYMBOL(tu_ssv6xxx_hci_init);
+EXPORT_SYMBOL(tu_ssv6xxx_hci_exit);
+#else
+module_init(tu_ssv6xxx_hci_init);
+module_exit(tu_ssv6xxx_hci_exit);
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/hci/ssv_hci.h b/drivers/net/wireless/ssv6x5x/hci/ssv_hci.h
new file mode 100644
index 000000000..9a2617a1b
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/hci/ssv_hci.h
@@ -0,0 +1,148 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV_HCI_H_
+#define _SSV_HCI_H_
+#define SSV_SC(_ctrl_hci) (_ctrl_hci->shi->sc)
+#define TX_PAGE_NOT_LIMITED 255
+#define SSV_HW_TXQ_NUM 5
+#define SSV_HW_TXQ_MAX_SIZE 64
+#define SSV_HW_TXQ_RESUME_THRES ((SSV_HW_TXQ_MAX_SIZE >> 2) *3)
+#define SSV6XXX_ID_TX_THRESHOLD(_hctl) ((_hctl)->tx_info.tx_id_threshold)
+#define SSV6XXX_PAGE_TX_THRESHOLD(_hctl) ((_hctl)->tx_info.tx_page_threshold)
+#define SSV6XXX_TX_LOWTHRESHOLD_ID_TRIGGER(_hctl) ((_hctl)->tx_info.tx_lowthreshold_id_trigger)
+#define SSV6XXX_TX_LOWTHRESHOLD_PAGE_TRIGGER(_hctl) ((_hctl)->tx_info.tx_lowthreshold_page_trigger)
+#define SSV6XXX_ID_AC_BK_OUT_QUEUE(_hctl) ((_hctl)->tx_info.bk_txq_size)
+#define SSV6XXX_ID_AC_BE_OUT_QUEUE(_hctl) ((_hctl)->tx_info.be_txq_size)
+#define SSV6XXX_ID_AC_VI_OUT_QUEUE(_hctl) ((_hctl)->tx_info.vi_txq_size)
+#define SSV6XXX_ID_AC_VO_OUT_QUEUE(_hctl) ((_hctl)->tx_info.vo_txq_size)
+#define SSV6XXX_ID_MANAGER_QUEUE(_hctl) ((_hctl)->tx_info.manage_txq_size)
+#define SSV6XXX_ID_USB_AC_BK_OUT_QUEUE(_hctl) ((_hctl)->shi->sh->cfg.bk_txq_size)
+#define SSV6XXX_ID_USB_AC_BE_OUT_QUEUE(_hctl) ((_hctl)->shi->sh->cfg.be_txq_size)
+#define SSV6XXX_ID_USB_AC_VI_OUT_QUEUE(_hctl) ((_hctl)->shi->sh->cfg.vi_txq_size)
+#define SSV6XXX_ID_USB_AC_VO_OUT_QUEUE(_hctl) ((_hctl)->shi->sh->cfg.vo_txq_size)
+#define SSV6XXX_ID_USB_MANAGER_QUEUE(_hctl) ((_hctl)->shi->sh->cfg.manage_txq_size)
+#define SSV6XXX_ID_HCI_INPUT_QUEUE 8
+#define HCI_FLAGS_ENQUEUE_HEAD 0x00000001
+#define HCI_FLAGS_NO_FLOWCTRL 0x00000002
+#define HCI_DBG_PRINT(_hci_ctrl,fmt,...) \
+    do { \
+        (_hci_ctrl)->shi->dbgprint((_hci_ctrl)->shi->sc, LOG_HCI, fmt, ##__VA_ARGS__); \
+    } while (0)
+struct ssv_hw_txq {
+    u32 txq_no;
+    struct sk_buff_head qhead;
+    int max_qsize;
+    int resum_thres;
+    bool paused;
+    u32 tx_pkt;
+    u32 tx_flags;
+};
+struct ssv6xxx_hci_ctrl;
+struct ssv6xxx_hci_ops {
+    int (*hci_start)(struct ssv6xxx_hci_ctrl *hctrl);
+    int (*hci_stop)(struct ssv6xxx_hci_ctrl *hctrl);
+    void (*hci_write_hw_config)(struct ssv6xxx_hci_ctrl *hctrl, int val);
+    int (*hci_read_word)(struct ssv6xxx_hci_ctrl *hctrl, u32 addr, u32 *regval);
+    int (*hci_write_word)(struct ssv6xxx_hci_ctrl *hctrl, u32 addr, u32 regval);
+    int (*hci_safe_read_word)(struct ssv6xxx_hci_ctrl *hctrl, u32 addr, u32 *regval);
+    int (*hci_safe_write_word)(struct ssv6xxx_hci_ctrl *hctrl, u32 addr, u32 regval);
+    int (*hci_burst_read_word)(struct ssv6xxx_hci_ctrl *hctrl, u32 *addr, u32 *regval, u8 reg_amount);
+    int (*hci_burst_write_word)(struct ssv6xxx_hci_ctrl *hctrl, u32 *addr, u32 *regval, u8 reg_amount);
+    int (*hci_burst_safe_read_word)(struct ssv6xxx_hci_ctrl *hctrl, u32 *addr, u32 *regval, u8 reg_amount);
+    int (*hci_burst_safe_write_word)(struct ssv6xxx_hci_ctrl *hctrl, u32 *addr, u32 *regval, u8 reg_amount);
+    int (*hci_load_fw)(struct ssv6xxx_hci_ctrl *hctrl, u8 *firmware_name, u8 openfile);
+    int (*hci_tx)(struct ssv6xxx_hci_ctrl *hctrl, struct sk_buff *, int, u32);
+#if 0
+    int (*hci_rx)(struct ssv6xxx_hci_ctrl *hctrl, struct sk_buff *);
+#endif
+    int (*hci_tx_pause)(struct ssv6xxx_hci_ctrl *hctrl, u32 txq_mask);
+    int (*hci_tx_resume)(struct ssv6xxx_hci_ctrl *hctrl, u32 txq_mask);
+    int (*hci_txq_flush)(struct ssv6xxx_hci_ctrl *hctrl, u32 txq_mask);
+    int (*hci_txq_flush_by_sta)(struct ssv6xxx_hci_ctrl *hctrl, int aid);
+    bool (*hci_txq_empty)(struct ssv6xxx_hci_ctrl *hctrl, int txqid);
+    int (*hci_pmu_wakeup)(struct ssv6xxx_hci_ctrl *hctrl);
+    int (*hci_send_cmd)(struct ssv6xxx_hci_ctrl *hctrl, struct sk_buff *);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+    bool (*hci_init_debugfs)(struct ssv6xxx_hci_ctrl *hctrl, struct dentry *dev_deugfs_dir);
+    void (*hci_deinit_debugfs)(struct ssv6xxx_hci_ctrl *hctrl);
+#endif
+    int (*hci_write_sram)(struct ssv6xxx_hci_ctrl *hctrl, u32 addr, u8* data, u32 size);
+    int (*hci_interface_reset)(struct ssv6xxx_hci_ctrl *hctrl);
+    int (*hci_sysplf_reset)(struct ssv6xxx_hci_ctrl *hctrl, u32 addr, u32 value);
+};
+struct ssv6xxx_hci_info {
+    struct device *dev;
+    struct ssv6xxx_hwif_ops *if_ops;
+    struct ssv6xxx_hci_ops *hci_ops;
+    struct ssv6xxx_hci_ctrl *hci_ctrl;
+    struct ssv_softc *sc;
+    struct ssv_hw *sh;
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+    int (*hci_rx_cb)(struct sk_buff_head *, void *);
+#else
+    int (*hci_rx_cb)(struct sk_buff *, void *);
+#endif
+    int (*hci_is_rx_q_full)(void *);
+    void (*hci_pre_tx_cb)(struct sk_buff *, void *);
+    void (*hci_post_tx_cb)(struct sk_buff_head *, void *);
+    int (*hci_tx_flow_ctrl_cb)(void *, int, bool, int debug);
+    void (*hci_tx_buf_free_cb)(struct sk_buff *, void *);
+    void (*hci_skb_update_cb)(struct sk_buff *, void *);
+    void (*hci_tx_q_empty_cb)(u32 txq_no, void *);
+    int (*hci_rx_mode_cb)(void *);
+    int (*hci_peek_next_pkt_len_cb)(struct sk_buff *, void *);
+    void (*dbgprint)(void *, u32 log_id, const char *fmt,...);
+    struct sk_buff *(*skb_alloc) (void *app_param, s32 len);
+    void (*skb_free) (void *app_param, struct sk_buff *skb);
+    void (*write_hw_config_cb)(void *param, u32 addr, u32 value);
+};
+int tu_ssv6xxx_hci_deregister(struct ssv6xxx_hci_info *);
+int tu_ssv6xxx_hci_register(struct ssv6xxx_hci_info *);
+#if (defined(CONFIG_SSV_SUPPORT_ANDROID)||defined(CONFIG_SSV_BUILD_AS_ONE_KO))
+int tu_ssv6xxx_hci_init(void);
+void tu_ssv6xxx_hci_exit(void);
+#endif
+#ifdef SSV_SUPPORT_HAL
+#define SSV_READRG_HCI_INQ_INFO(_hci_ctrl,_used_id,_tx_use_page) \
+                                                      HAL_READRG_HCI_INQ_INFO((_hci_ctrl)->shi->sh, _used_id, _tx_use_page)
+#define SSV_LOAD_FW_ENABLE_MCU(_hci_ctrl) HAL_LOAD_FW_ENABLE_MCU((_hci_ctrl)->shi->sh)
+#define SSV_LOAD_FW_DISABLE_MCU(_hci_ctrl) HAL_LOAD_FW_DISABLE_MCU((_hci_ctrl)->shi->sh)
+#define SSV_LOAD_FW_SET_STATUS(_hci_ctrl,_status) HAL_LOAD_FW_SET_STATUS((_hci_ctrl)->shi->sh, (_status))
+#define SSV_LOAD_FW_GET_STATUS(_hci_ctrl,_status) HAL_LOAD_FW_GET_STATUS((_hci_ctrl)->shi->sh, (_status))
+#define SSV_RESET_CPU(_hci_ctrl) HAL_RESET_CPU((_hci_ctrl)->shi->sh)
+#define SSV_SET_SRAM_MODE(_hci_ctrl,_mode) HAL_SET_SRAM_MODE((_hci_ctrl)->shi->sh, _mode)
+#define SSV_LOAD_FW_PRE_CONFIG_DEVICE(_hci_ctrl) HAL_LOAD_FW_PRE_CONFIG_DEVICE((_hci_ctrl)->shi->sh)
+#define SSV_LOAD_FW_POST_CONFIG_DEVICE(_hci_ctrl) HAL_LOAD_FW_POST_CONFIG_DEVICE((_hci_ctrl)->shi->sh)
+#else
+void ssv6xxx_hci_hci_inq_info(struct ssv6xxx_hci_ctrl *ctrl_hci, int *used_id);
+void ssv6xxx_hci_load_fw_enable_mcu(struct ssv6xxx_hci_ctrl *ctrl_hci);
+int ssv6xxx_hci_load_fw_disable_mcu(struct ssv6xxx_hci_ctrl *ctrl_hci);
+int ssv6xxx_hci_load_fw_set_status(struct ssv6xxx_hci_ctrl *ctrl_hci, int status);
+int ssv6xxx_hci_load_fw_get_status(struct ssv6xxx_hci_ctrl *ctrl_hci, int *status);
+void ssv6xxx_hci_load_fw_pre_config_device(struct ssv6xxx_hci_ctrl *ctrl_hci);
+void ssv6xxx_hci_load_fw_post_config_device(struct ssv6xxx_hci_ctrl *ctrl_hci);
+#define SSV_READRG_HCI_INQ_INFO(_hci_ctrl,_used_id,_tx_use_page) \
+                                                       ssv6xxx_hci_hci_inq_info(_hci_ctrl, _used_id)
+#define SSV_LOAD_FW_ENABLE_MCU(_hci_ctrl) ssv6xxx_hci_load_fw_enable_mcu((_hci_ctrl))
+#define SSV_LOAD_FW_DISABLE_MCU(_hci_ctrl) ssv6xxx_hci_load_fw_disable_mcu((_hci_ctrl))
+#define SSV_LOAD_FW_SET_STATUS(_hci_ctrl,_status) ssv6xxx_hci_load_fw_set_status((_hci_ctrl), (_status))
+#define SSV_LOAD_FW_GET_STATUS(_hci_ctrl,_status) ssv6xxx_hci_load_fw_get_status((_hci_ctrl), (_status))
+#define SSV_RESET_CPU(_hci_ctrl) ssv6xxx_hci_reset_cpu((_hci_ctrl))
+#define SSV_SET_SRAM_MODE(_hci_ctrl,_mode)
+#define SSV_LOAD_FW_PRE_CONFIG_DEVICE(_hci_ctrl) ssv6xxx_hci_load_fw_pre_config_device(_hci_ctrl)
+#define SSV_LOAD_FW_POST_CONFIG_DEVICE(_hci_ctrl) ssv6xxx_hci_load_fw_post_config_device(_hci_ctrl)
+#endif
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/hci_wrapper/Makefile b/drivers/net/wireless/ssv6x5x/hci_wrapper/Makefile
new file mode 100755
index 000000000..e8e017859
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/hci_wrapper/Makefile
@@ -0,0 +1,19 @@
+ifeq ($(KBUILD_TOP),)
+    ifneq ($(KBUILD_EXTMOD),)
+    KBUILD_DIR := $(KBUILD_EXTMOD)
+    else
+    KBUILD_DIR := $(PWD)
+    endif
+KBUILD_TOP := $(KBUILD_DIR)/../
+endif
+
+include $(KBUILD_TOP)/config.mak
+
+KBUILD_EXTRA_SYMBOLS += $(KBUILD_TOP)/hci/Module.symvers
+
+
+KMODULE_NAME=hci_wrapper
+KERN_SRCS := ssv_huw.c
+
+
+include $(KBUILD_TOP)/rules.mak
diff --git a/drivers/net/wireless/ssv6x5x/hci_wrapper/ssv_huw.c b/drivers/net/wireless/ssv6x5x/hci_wrapper/ssv_huw.c
new file mode 100644
index 000000000..e1a254d22
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/hci_wrapper/ssv_huw.c
@@ -0,0 +1,461 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/version.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/fs.h>
+#include <linux/cdev.h>
+#include <linux/slab.h>
+#include <linux/skbuff.h>
+#include <linux/wait.h>
+#include <linux/netdevice.h>
+#include <hci/ssv_hci.h>
+#include <hwif/hwif.h>
+#include "ssv_huw.h"
+#define SSV6200_ID_NUMBER (128)
+#define BLOCKSIZE 0x40
+#define RXBUFLENGTH 1024*3
+#define RXBUFSIZE 512
+#define CHECK_RET(_fun) \
+ do { \
+  if (0 != _fun) \
+   printk("File = %s\nLine = %d\nFunc=%s\nDate=%s\nTime=%s\n", __FILE__, __LINE__, __FUNCTION__, __DATE__, __TIME__); \
+ } while (0)
+#define SMAC_SRAM_WRITE(_s,_r,_v,_sz) \
+    (_s)->hci.hci_ops->hci_write_sram(_r, _v, _sz)
+#define SMAC_REG_WRITE(_s,_r,_v) \
+    (_s)->hci.hci_ops->hci_write_word(_r, _v)
+#define SMAC_REG_READ(_s,_r,_v) \
+    (_s)->hci.hci_ops->hci_read_word(_r, _v)
+#define HCI_START(_sh) \
+    (_sh)->hci.hci_ops->hci_start()
+#define HCI_STOP(_sh) \
+    (_sh)->hci.hci_ops->hci_stop()
+#define HCI_SEND(_sh,_sk,_q) \
+    (_sh)->hci.hci_ops->hci_tx(_sk, _q, HCI_FLAGS_NO_FLOWCTRL)
+#define HCI_PAUSE(_sh,_mk) \
+    (_sh)->hci.hci_ops->hci_tx_pause(_mk)
+#define HCI_RESUME(_sh,_mk) \
+    (_sh)->hci.hci_ops->hci_tx_resume(_mk)
+#define HCI_TXQ_FLUSH(_sh,_mk) \
+    (_sh)->hci.hci_ops->hci_txq_flush(_mk)
+#define HCI_TXQ_FLUSH_BY_STA(_sh,_aid) \
+  (_sh)->hci.hci_ops->hci_txq_flush_by_sta(_aid)
+#define HCI_TXQ_EMPTY(_sh,_txqid) \
+  (_sh)->hci.hci_ops->hci_txq_empty(_txqid)
+#define HCI_WAKEUP_PMU(_sh) \
+    (_sh)->hci.hci_ops->hci_pmu_wakeup()
+#define HCI_SEND_CMD(_sh,_sk) \
+        (_sh)->hci.hci_ops->hci_send_cmd(_sk)
+struct ssv_huw_dev {
+    struct device *dev;
+    struct ssv6xxx_platform_data *priv;
+    struct ssv6xxx_hci_info hci;
+    char chip_id[24];
+    u64 chip_tag;
+    u8 funcFocus;
+    wait_queue_head_t read_wq;
+    spinlock_t rxlock;
+    void *bufaddr;
+    struct sk_buff_head rx_skb_q;
+};
+struct ssv_rxbuf {
+    struct list_head list;
+    u32 rxsize;
+    u8 rxdata[RXBUFLENGTH];
+};
+struct ssv_huw_dev g_huw_dev;
+static unsigned int ssv_sdiobridge_ioctl_major = 0;
+static unsigned int num_of_dev = 1;
+static struct cdev ssv_sdiobridge_ioctl_cdev;
+static struct class *fc;
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+int ssv_huw_rx(struct sk_buff_head *rx_skb_q, void *args)
+#else
+int ssv_huw_rx(struct sk_buff *rx_skb, void *args)
+#endif
+{
+    struct ssv_huw_dev *phuw_dev = (struct ssv_huw_dev *)args;
+    unsigned long flags;
+    spin_lock_irqsave(&phuw_dev->rxlock, flags);
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+    while (skb_queue_len(rx_skb_q))
+        __skb_queue_tail(&phuw_dev->rx_skb_q, __skb_dequeue(rx_skb_q));
+#else
+    __skb_queue_tail(&phuw_dev->rx_skb_q, rx_skb);
+#endif
+    spin_unlock_irqrestore(&phuw_dev->rxlock, flags);
+    wake_up_interruptible(&phuw_dev->read_wq);
+    return 0;
+}
+void ssv_huw_txbuf_free_skb(struct sk_buff *skb, void *args)
+{
+    if (!skb)
+        return;
+    dev_kfree_skb_any(skb);
+}
+unsigned int skb_queue_len_bhsafe(struct sk_buff_head *head, spinlock_t *plock)
+{
+    unsigned int len = 0;
+    spin_lock_bh(plock);
+    len = skb_queue_len(head);
+    spin_unlock_bh(plock);
+    return len;
+}
+static long ssv_huw_ioctl_readReg(struct ssv_huw_dev *phuw_dev,unsigned int cmd, struct ssv_huw_cmd *pcmd_data,struct ssv_huw_cmd *pucmd_data,bool isCompat)
+{
+    long retval =0;
+    if ( pcmd_data->in_data_len < 4 || pcmd_data->out_data_len < 4) {
+        retval = -1;
+    } else {
+        u32 tmpdata;
+        u32 regval;
+        int ret = 0;
+#ifdef CONFIG_COMPAT
+        if ( isCompat ) {
+            CHECK_RET(copy_from_user(&tmpdata,(int __user *)compat_ptr((unsigned long)pucmd_data->in_data),sizeof(tmpdata)));
+        } else
+#endif
+        {
+            CHECK_RET(copy_from_user(&tmpdata,(int __user *)pucmd_data->in_data,sizeof(tmpdata)));
+        }
+        ret = SMAC_REG_READ(phuw_dev, tmpdata, &regval);
+        if ( !ret ) {
+#ifdef CONFIG_COMPAT
+            if ( isCompat ) {
+                CHECK_RET(copy_to_user((int __user *)compat_ptr((unsigned long)pucmd_data->out_data),&regval,sizeof(regval)));
+            } else
+#endif
+            {
+                CHECK_RET(copy_to_user((int __user *)pucmd_data->out_data,&regval,sizeof(regval)));
+            }
+        } else {
+            dev_err(phuw_dev->dev,"%s: error : %d",__FUNCTION__,ret);
+            retval = -1;
+        }
+    }
+    return retval;
+}
+static long ssv_huw_ioctl_writeReg(struct ssv_huw_dev *phuw_dev,unsigned int cmd, struct ssv_huw_cmd *pcmd_data,struct ssv_huw_cmd *pucmd_data,bool isCompat)
+{
+    long retval =0;
+    if ( pcmd_data->in_data_len < 8) {
+        retval = -1;
+    } else {
+        u32 tmpdata[2];
+        int ret = 0;
+#ifdef CONFIG_COMPAT
+        if ( isCompat ) {
+            CHECK_RET(copy_from_user(&tmpdata,(int __user *)compat_ptr((unsigned long)pucmd_data->in_data),sizeof(tmpdata)));
+        } else
+#endif
+        {
+            CHECK_RET(copy_from_user(&tmpdata,(int __user *)pucmd_data->in_data,sizeof(tmpdata)));
+        }
+        SMAC_REG_WRITE(phuw_dev, tmpdata[0], tmpdata[1]);
+        if ( ret ) {
+            dev_err(phuw_dev->dev,"%s: error : %d",__FUNCTION__,ret);
+            retval = -1;
+        }
+    }
+    return retval;
+}
+static long ssv_huw_ioctl_writeSram(struct ssv_huw_dev *phuw_dev,unsigned int cmd, struct ssv_huw_cmd *pcmd_data,struct ssv_huw_cmd *pucmd_data,bool isCompat)
+{
+    long retval =0;
+    unsigned char *ptr = NULL;
+    unsigned int addr;
+    if (( pcmd_data->in_data_len != 4) || ( pcmd_data->out_data_len <= 0)) {
+        retval = -1;
+    } else {
+        int ret = 0;
+        ptr = kzalloc(pcmd_data->out_data_len, GFP_KERNEL);
+        if(ptr == NULL)
+            return -ENOMEM;
+#ifdef CONFIG_COMPAT
+        if ( isCompat ) {
+            CHECK_RET(copy_from_user(&addr, (int __user *)compat_ptr((unsigned long)pucmd_data->in_data), sizeof(addr)));
+            CHECK_RET(copy_from_user(ptr, (int __user *)compat_ptr((unsigned long)pucmd_data->out_data), pcmd_data->out_data_len));
+        } else
+#endif
+        {
+            CHECK_RET(copy_from_user(&addr, (int __user *)pucmd_data->in_data, sizeof(addr)));
+            CHECK_RET(copy_from_user(ptr, (int __user *)pucmd_data->out_data, pcmd_data->out_data_len));
+        }
+        SMAC_SRAM_WRITE(phuw_dev, addr, ptr, pcmd_data->out_data_len);
+        if ( ret ) {
+            dev_err(phuw_dev->dev,"%s: error : %d",__FUNCTION__,ret);
+            retval = -1;
+        }
+        kfree(ptr);
+    }
+    return retval;
+}
+static long ssv_huw_ioctl_process(struct ssv_huw_dev *glue, unsigned int cmd, struct ssv_huw_cmd *pucmd_data, bool isCompat)
+{
+    struct ssv_huw_cmd cmd_data;
+    long retval=0;
+    if ( isCompat ) {
+        CHECK_RET(copy_from_user(&cmd_data,(int __user *)pucmd_data,sizeof(*pucmd_data)));
+    } else {
+        CHECK_RET(copy_from_user(&cmd_data,(int __user *)pucmd_data,sizeof(*pucmd_data)));
+    }
+    switch (cmd) {
+    case IOCTL_SSVSDIO_READ_REG:
+        retval = ssv_huw_ioctl_readReg(glue,cmd,&cmd_data,pucmd_data,isCompat);
+        break;
+    case IOCTL_SSVSDIO_WRITE_REG:
+        retval = ssv_huw_ioctl_writeReg(glue,cmd,&cmd_data,pucmd_data,isCompat);
+        break;
+    case IOCTL_SSVSDIO_WRITE_SRAM:
+        retval = ssv_huw_ioctl_writeSram(glue,cmd,&cmd_data,pucmd_data,isCompat);
+        break;
+    case IOCTL_SSVSDIO_START:
+        retval = HCI_START(glue);
+        break;
+    case IOCTL_SSVSDIO_STOP:
+        retval = HCI_STOP(glue);
+        break;
+    default:
+        return -EINVAL;
+    }
+    return retval;
+}
+#ifdef CONFIG_COMPAT
+static long ssv_huw_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
+{
+    long retval=0;
+    struct ssv_huw_cmd *pucmd_data;
+    pucmd_data = (struct ssv_huw_cmd *)arg;
+    retval = ssv_huw_ioctl_process(&g_huw_dev, cmd, pucmd_data, true);
+    return retval;
+}
+#endif
+static long ssv_huw_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
+{
+    long retval=0;
+    struct ssv_huw_cmd *pucmd_data;
+    pucmd_data = (struct ssv_huw_cmd *)arg;
+    retval = ssv_huw_ioctl_process( &g_huw_dev,cmd,pucmd_data,false);
+    return retval;
+}
+static int ssv_huw_open(struct inode *inode, struct file *fp)
+{
+    fp->private_data = &g_huw_dev;
+    return 0;
+}
+static int ssv_huw_release(struct inode *inode, struct file *fp)
+{
+    struct sk_buff *skb = NULL;
+    while((skb = skb_dequeue(&(g_huw_dev.rx_skb_q))) != NULL) {
+        dev_kfree_skb_any(skb);
+        skb = NULL;
+    }
+    return 0;
+}
+static ssize_t ssv_huw_read(struct file *fp, char __user * buf, size_t length, loff_t * offset)
+{
+    int ret = 0, copy_length = 0;
+    struct sk_buff *skb = NULL;
+    if (skb_queue_len_bhsafe(&(g_huw_dev.rx_skb_q), &(g_huw_dev.rxlock)) == 0) {
+        ret = wait_event_interruptible((g_huw_dev.read_wq), (skb_queue_len_bhsafe(&(g_huw_dev.rx_skb_q), &(g_huw_dev.rxlock)) != 0));
+        if (ret != 0)
+            return -1;
+    }
+    spin_lock_bh(&(g_huw_dev.rxlock));
+    if (skb_queue_len(&(g_huw_dev.rx_skb_q)) > 0)
+        skb = skb_dequeue(&(g_huw_dev.rx_skb_q));
+    spin_unlock_bh(&(g_huw_dev.rxlock));
+    if (skb != NULL) {
+        copy_length = min(skb->len,(u32)length);
+        CHECK_RET(copy_to_user((int __user *)buf, skb->data, copy_length));
+        dev_kfree_skb_any(skb);
+    }
+    return copy_length;
+}
+static ssize_t ssv_huw_write(struct file *fp, const char __user * buf, size_t length, loff_t * offset)
+{
+    struct sk_buff *skb;
+    unsigned int len = (unsigned int)length;
+    len = (len & 0x1f)?(((len>>5) + 1)<<5):len;
+    skb = __dev_alloc_skb(len, GFP_KERNEL);
+    if (skb == NULL) {
+        dev_err(g_huw_dev.dev,"%s: error : alloc buf error size:%d",__FUNCTION__,(u32)len);
+        return -ENOMEM;
+    }
+    CHECK_RET(copy_from_user(skb->data, (int __user *)buf, length));
+    skb_put(skb, length);
+    HCI_SEND(&g_huw_dev, skb, 1);
+    return length;
+}
+void ssv_huw_tx_cb(struct sk_buff_head *skb_head, void *args)
+{
+    struct sk_buff *skb = NULL;
+    while ((skb=skb_dequeue(skb_head))) {
+        dev_kfree_skb_any(skb);
+        skb = NULL;
+    }
+}
+int ssv_huw_read_hci_info(struct ssv_huw_dev *phuw_dev)
+{
+    struct ssv6xxx_hci_info *pinfo = &(phuw_dev->hci);
+    pinfo->hci_ops = NULL;
+    pinfo->dev = phuw_dev->dev;
+    pinfo->hci_rx_cb = ssv_huw_rx;
+    pinfo->rx_cb_args = (void *)phuw_dev;
+    pinfo->hci_post_tx_cb= ssv_huw_tx_cb;
+    pinfo->post_tx_cb_args = NULL;
+    pinfo->hci_skb_update_cb = NULL;
+    pinfo->skb_update_args = NULL;
+    pinfo->hci_tx_flow_ctrl_cb = NULL;
+    pinfo->tx_fctrl_cb_args = NULL;
+    pinfo->hci_tx_q_empty_cb = NULL;
+    pinfo->tx_q_empty_args = NULL;
+    pinfo->hci_tx_buf_free_cb = ssv_huw_txbuf_free_skb;
+    pinfo->tx_buf_free_args = NULL;
+    pinfo->if_ops = phuw_dev->priv->ops;
+    return 0;
+}
+struct file_operations s_huw_ops = {
+    .read = ssv_huw_read,
+    .write = ssv_huw_write,
+    .unlocked_ioctl = ssv_huw_ioctl,
+#ifdef CONFIG_COMPAT
+    .compat_ioctl = ssv_huw_compat_ioctl,
+#endif
+    .open = ssv_huw_open,
+    .release = ssv_huw_release,
+};
+static int ssv_huw_init_buf(struct ssv_huw_dev *hdev)
+{
+    init_waitqueue_head(&hdev->read_wq);
+    spin_lock_init(&hdev->rxlock);
+    skb_queue_head_init(&(hdev->rx_skb_q));
+    return 0;
+}
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,4,0)
+static char *ssv_huw_devnode(struct device *dev, umode_t *mode)
+#else
+static char *ssv_huw_devnode(struct device *dev, mode_t *mode)
+#endif
+{
+    if (!mode)
+        return NULL;
+    *mode = 0644;
+    return NULL;
+}
+int ssv_huw_probe(struct platform_device *pdev)
+{
+    dev_t dev;
+    int alloc_ret = 0;
+    int cdev_ret = 0;
+    if (!pdev->dev.platform_data) {
+        dev_err(&pdev->dev, "no platform data specified!\n");
+        return -EINVAL;
+    }
+    ssv_huw_init_buf(&g_huw_dev);
+    g_huw_dev.priv = (pdev->dev.platform_data);
+    g_huw_dev.dev = &(pdev->dev);
+    ssv_huw_read_hci_info(&g_huw_dev);
+    tu_ssv6xxx_hci_register(&(g_huw_dev.hci));
+    dev = MKDEV(ssv_sdiobridge_ioctl_major, 0);
+    alloc_ret = alloc_chrdev_region(&dev, 0, num_of_dev, FILE_DEVICE_SSVSDIO_NAME);
+    if (alloc_ret)
+        goto error;
+    ssv_sdiobridge_ioctl_major = MAJOR(dev);
+    cdev_init(&ssv_sdiobridge_ioctl_cdev, &s_huw_ops);
+    cdev_ret = cdev_add(&ssv_sdiobridge_ioctl_cdev, dev, num_of_dev);
+    if (cdev_ret)
+        goto error;
+    fc=class_create(THIS_MODULE, FILE_DEVICE_SSVSDIO_NAME);
+    fc->devnode = ssv_huw_devnode;
+    device_create(fc,NULL,dev,NULL,"%s",FILE_DEVICE_SSVSDIO_NAME);
+    dev_err(&pdev->dev, "%s driver(major: %d) installed.\n", FILE_DEVICE_SSVSDIO_NAME, ssv_sdiobridge_ioctl_major);
+    return 0;
+error:
+    if (cdev_ret == 0)
+        cdev_del(&ssv_sdiobridge_ioctl_cdev);
+    if (alloc_ret == 0)
+        unregister_chrdev_region(dev, num_of_dev);
+    return -ENODEV;
+}
+EXPORT_SYMBOL(ssv_huw_probe);
+int ssv_huw_remove(struct platform_device *pdev)
+{
+    dev_t dev;
+    int ret = 0;
+    tu_ssv6xxx_hci_deregister();
+    memset(&g_huw_dev, 0, sizeof(g_huw_dev));
+    dev = MKDEV(ssv_sdiobridge_ioctl_major, 0);
+    device_destroy(fc,dev);
+    class_destroy(fc);
+    cdev_del(&ssv_sdiobridge_ioctl_cdev);
+    unregister_chrdev_region(dev, num_of_dev);
+    return ret;
+}
+EXPORT_SYMBOL(ssv_huw_remove);
+static const struct platform_device_id huw_id_table[] = {
+    {
+        .name = "ssv6200",
+        .driver_data = 0x00,
+    },
+    {},
+};
+MODULE_DEVICE_TABLE(platform, huw_id_table);
+static struct platform_driver ssv_huw_driver = {
+    .probe = ssv_huw_probe,
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0)
+    .remove = __devexit_p(ssv_huw_remove),
+#else
+    .remove = ssv_huw_remove,
+#endif
+    .id_table = huw_id_table,
+    .driver = {
+        .name = "TU SSV WLAN driver",
+        .owner = THIS_MODULE,
+    }
+};
+#if (defined(CONFIG_SSV_SUPPORT_ANDROID)||defined(CONFIG_SSV_BUILD_AS_ONE_KO))
+int ssv_huw_init(void)
+#else
+static int __init ssv_huw_init(void)
+#endif
+{
+    int ret;
+    memset(&g_huw_dev, 0, sizeof(g_huw_dev));
+    ret = platform_driver_register(&ssv_huw_driver);
+    if (ret < 0) {
+        printk(KERN_ALERT "[HCI user-space wrapper]: Fail to register huw\n");
+    }
+    return ret;
+}
+#if (defined(CONFIG_SSV_SUPPORT_ANDROID)||defined(CONFIG_SSV_BUILD_AS_ONE_KO))
+void ssv_huw_exit(void)
+#else
+static void __exit ssv_huw_exit(void)
+#endif
+{
+    platform_driver_unregister(&ssv_huw_driver);
+}
+#if (defined(CONFIG_SSV_SUPPORT_ANDROID)||defined(CONFIG_SSV_BUILD_AS_ONE_KO))
+EXPORT_SYMBOL(ssv_huw_init);
+EXPORT_SYMBOL(ssv_huw_exit);
+#else
+module_init(ssv_huw_init);
+module_exit(ssv_huw_exit);
+#endif
+MODULE_LICENSE("GPL");
diff --git a/drivers/net/wireless/ssv6x5x/hci_wrapper/ssv_huw.h b/drivers/net/wireless/ssv6x5x/hci_wrapper/ssv_huw.h
new file mode 100644
index 000000000..42bb30932
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/hci_wrapper/ssv_huw.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV_HUW_H_
+#define _SSV_HUW_H_
+#include <linux/ioctl.h>
+struct ssv_huw_cmd {
+    __u32 in_data_len;
+    u8* in_data;
+#ifndef __x86_64
+    __u32 padding1;
+#endif
+    __u32 out_data_len;
+    u8* out_data;
+#ifndef __x86_64
+    __u32 padding2;
+#endif
+    __u32 response;
+} __attribute__((packed));
+#define FILE_DEVICE_SSVSDIO MMC_BLOCK_MAJOR
+#define FILE_DEVICE_SSVSDIO_SEQ 0x50
+#define FILE_DEVICE_SSVSDIO_NAME "ssvhuwdev"
+#if 0
+#define IOCTL_SSVSDIO_GET_DRIVER_VERSION \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x01, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_GET_FUNCTION_NUMBER \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x02, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_GET_FUNCTION_FOCUS \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x03, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_SET_FUNCTION_FOCUS \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x04, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_GET_BUS_WIDTH \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x05, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_SET_BUS_WIDTH \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x06, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_GET_BUS_CLOCK \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x07, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_SET_BUS_CLOCK \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x08, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_GET_BLOCK_MODE \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x09, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_SET_BLOCK_MODE \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x0a, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_GET_BLOCKLEN \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x0b, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_SET_BLOCKLEN \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x0c, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_GET_FN0_BLOCKLEN \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x0d, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_SET_FN0_BLOCKLEN \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x0e, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_GET_BUS_INTERFACE_CONTROL \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x0f, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_SET_BUS_INTERFACE_CONTROL \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x10, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_GET_INT_ENABLE \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x11, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_SET_INT_ENABLE \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x12, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_GET_AUTO_ACK_INT \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x13, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_SET_AUTO_ACK_INT \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x14, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_ACK_INT \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x15, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_READ_BYTE \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x16, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_WRITE_BYTE \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x17, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_GET_MULTI_BYTE_IO_PORT \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x18, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_SET_MULTI_BYTE_IO_PORT \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x19, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_READ_MULTI_BYTE \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x1a, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_WRITE_MULTI_BYTE \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x1b, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_GET_MULTI_BYTE_REG_IO_PORT \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x1c, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_SET_MULTI_BYTE_REG_IO_PORT \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x1d, struct ssv_huw_cmd)
+#endif
+#define IOCTL_SSVSDIO_READ_REG \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x1e, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_WRITE_REG \
+ _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x1f, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_READ_DATA \
+    _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x20, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_WRITE_SRAM \
+    _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x21, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_START \
+    _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x22, struct ssv_huw_cmd)
+#define IOCTL_SSVSDIO_STOP \
+    _IOWR( FILE_DEVICE_SSVSDIO, FILE_DEVICE_SSVSDIO_SEQ+0x23, struct ssv_huw_cmd)
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/hwif/hwif.h b/drivers/net/wireless/ssv6x5x/hwif/hwif.h
new file mode 100644
index 000000000..d4c6141cc
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/hwif/hwif.h
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __HWIF_H__
+#define __HWIF_H__
+#include <linux/mmc/host.h>
+#include <ssv6xxx_common.h>
+#define SYS_REG_BASE 0xc0000000
+#define ADR_CHIP_ID_0 (SYS_REG_BASE+0x00000008)
+#define ADR_CHIP_ID_1 (SYS_REG_BASE+0x0000000c)
+#define ADR_CHIP_ID_2 (SYS_REG_BASE+0x00000010)
+#define ADR_CHIP_ID_3 (SYS_REG_BASE+0x00000014)
+#define SSVCABRIO_PLAT_EEP_MAX_WORDS 2048
+#define SSV_HWIF_CAPABILITY_MASK 0x00000001
+#define SSV_HWIF_INTERFACE_MASK 0x00000002
+#define SSV_HWIF_CAPABILITY_SFT 0
+#define SSV_HWIF_INTERFACE_SFT 1
+#define SSV_HWIF_CAPABILITY_INTERRUPT (0 << SSV_HWIF_CAPABILITY_SFT)
+#define SSV_HWIF_CAPABILITY_POLLING (1 << SSV_HWIF_CAPABILITY_SFT)
+#define SSV_HWIF_INTERFACE_SDIO (0 << SSV_HWIF_INTERFACE_SFT)
+#define SSV_HWIF_INTERFACE_USB (1 << SSV_HWIF_INTERFACE_SFT)
+#define SSV_REG_WRITE(dev,reg,val) \
+        (sh)->priv->ops->writereg((sh)->sc->dev, (reg), (val))
+#define SSV_REG_READ(dev,reg,buf) \
+        (sh)->priv->ops->readreg((sh)->sc->dev, (reg), (buf))
+#define HWIF_DBG_PRINT(_pdata,format,args...) \
+    do { \
+  if ((_pdata != NULL) && ((_pdata)->dbg_control)) \
+   printk(format, ##args); \
+    } while (0)
+#if 0
+#define SSV_REG_WRITE(sh,reg,val) \
+        (sh)->priv->ops->writereg((sh)->sc->dev, (reg), (val))
+#define SSV_REG_READ(sh,reg,buf) \
+        (sh)->priv->ops->readreg((sh)->sc->dev, (reg), (buf))
+#define SSV_REG_CONFIRM(sh,reg,val) \
+{ \
+    u32 regval; \
+    SSV_REG_READ(sh, reg, &regval); \
+    if (regval != (val)) { \
+        printk("[0x%08x]: 0x%08x!=0x%08x\n",\
+        (reg), (val), regval); \
+        return -1; \
+    } \
+}
+#define SSV_REG_SET_BITS(sh,reg,set,clr) \
+{ \
+    u32 reg_val; \
+    SSV_REG_READ(sh, reg, &reg_val); \
+    reg_val &= ~(clr); \
+    reg_val |= (set); \
+    SSV_REG_WRITE(sh, reg, reg_val); \
+}
+#endif
+struct sdio_scatter_req;
+struct ssv6xxx_hwif_ops {
+    int __must_check (*read)(struct device *child, void *buf,size_t *size, int mode);
+    int __must_check (*write)(struct device *child, void *buf, size_t len,u8 queue_num);
+    int __must_check (*readreg)(struct device *child, u32 addr, u32 *buf);
+    int __must_check (*writereg)(struct device *child, u32 addr, u32 buf);
+    int __must_check (*safe_readreg)(struct device *child, u32 addr, u32 *buf);
+    int __must_check (*safe_writereg)(struct device *child, u32 addr, u32 buf);
+    int __must_check (*burst_readreg)(struct device *child, u32 *addr, u32 *buf, u8 reg_amount);
+    int __must_check (*burst_writereg)(struct device *child, u32 *addr, u32 *buf, u8 reg_amount);
+    int __must_check (*burst_safe_readreg)(struct device *child, u32 *addr, u32 *buf, u8 reg_amount);
+    int __must_check (*burst_safe_writereg)(struct device *child, u32 *addr, u32 *buf, u8 reg_amount);
+    int (*trigger_tx_rx)(struct device *child);
+    int (*irq_getmask)(struct device *child, u32 *mask);
+    void (*irq_setmask)(struct device *child,int mask);
+    void (*irq_enable)(struct device *child);
+    void (*irq_disable)(struct device *child,bool iswaitirq);
+    int (*irq_getstatus)(struct device *child,int *status);
+    void (*irq_request)(struct device *child,irq_handler_t irq_handler,void *irq_dev);
+    void (*irq_trigger)(struct device *child);
+    void (*pmu_wakeup)(struct device *child);
+    int __must_check (*load_fw)(struct device *child, u32 start_addr, u8 *data, int data_length);
+    void (*load_fw_pre_config_device)(struct device *child);
+    void (*load_fw_post_config_device)(struct device *child);
+    int (*cmd52_read)(struct device *child, u32 addr, u32 *value);
+    int (*cmd52_write)(struct device *child, u32 addr, u32 value);
+    bool (*support_scatter)(struct device *child);
+    int (*rw_scatter)(struct device *child, struct sdio_scatter_req *scat_req);
+    bool (*is_ready)(struct device *child);
+    int (*write_sram)(struct device *child, u32 addr, u8 *data, u32 size);
+    void (*interface_reset)(struct device *child);
+    int (*start_usb_acc)(struct device *child, u8 epnum);
+    int (*stop_usb_acc)(struct device *child, u8 epnum);
+    int (*jump_to_rom)(struct device *child);
+    int (*property)(struct device *child);
+    void (*sysplf_reset)(struct device *child, u32 addr, u32 value);
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+    void (*hwif_rx_task)(struct device *child, int (*rx_cb)(struct sk_buff_head *rxq, void *args), int (*is_rx_q_full)(void *args), void *args, u32 *pkt);
+#else
+    void (*hwif_rx_task)(struct device *child, int (*rx_cb)(struct sk_buff *rx_skb, void *args), int (*is_rx_q_full)(void *args), void *args, u32 *pkt);
+#endif
+};
+struct ssv6xxx_platform_data {
+    atomic_t irq_handling;
+    bool is_enabled;
+    u8 chip_id[SSV6XXX_CHIP_ID_LENGTH];
+    u8 short_chip_id[SSV6XXX_CHIP_ID_SHORT_LENGTH+1];
+    unsigned short vendor;
+    unsigned short device;
+    struct ssv6xxx_hwif_ops *ops;
+    bool dbg_control;
+    struct sk_buff *(*skb_alloc) (void *param, s32 len, gfp_t gfp_mask);
+    void (*skb_free) (void *param, struct sk_buff *skb);
+    void *skb_param;
+#ifdef CONFIG_PM
+    void (*suspend)(void *param);
+    void (*resume)(void *param);
+    void *pm_param;
+#endif
+    void (*enable_usb_acc)(void *param, u8 epnum);
+    void (*disable_usb_acc)(void *param, u8 epnum);
+    void (*jump_to_rom)(void *param);
+    void *usb_param;
+    int (*rx_burstread_size)(void *param);
+    void *rx_burstread_param;
+};
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/hwif/sdio/Makefile b/drivers/net/wireless/ssv6x5x/hwif/sdio/Makefile
new file mode 100755
index 000000000..0f10136ce
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/hwif/sdio/Makefile
@@ -0,0 +1,21 @@
+ifeq ($(KBUILD_TOP),)
+    ifneq ($(KBUILD_EXTMOD),)
+    KBUILD_DIR := $(KBUILD_EXTMOD)
+    else
+    KBUILD_DIR := $(PWD)
+    endif
+KBUILD_TOP := $(KBUILD_DIR)/../../
+endif
+
+include $(KBUILD_TOP)/config.mak
+
+KBUILD_EXTRA_SYMBOLS += $(KBUILD_TOP)/smac/Module.symvers
+ifeq ($(DRV_OPT), HUW_DRV)
+KBUILD_EXTRA_SYMBOLS += $(KBUILD_TOP)/hci_wrapper/Module.symvers
+endif
+KBUILD_EXTRA_SYMBOLS += $(KBUILD_TOP)/ssvdevice/Module.symvers
+
+KMODULE_NAME=ssv6200_sdio
+KERN_SRCS := sdio.c
+
+include $(KBUILD_TOP)/rules.mak
diff --git a/drivers/net/wireless/ssv6x5x/hwif/sdio/sdio.c b/drivers/net/wireless/ssv6x5x/hwif/sdio/sdio.c
new file mode 100644
index 000000000..349514054
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/hwif/sdio/sdio.c
@@ -0,0 +1,1921 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/version.h>
+#include <linux/irq.h>
+#include <linux/module.h>
+#include <linux/vmalloc.h>
+#include <linux/platform_device.h>
+#include <linux/mmc/mmc.h>
+#include <linux/mmc/sd.h>
+#include <linux/mmc/sdio.h>
+#include <linux/mmc/sdio_func.h>
+#include <linux/mmc/sdio_ids.h>
+#include <linux/mmc/card.h>
+#include <linux/mmc/host.h>
+#include <linux/skbuff.h>
+#include <linux/delay.h>
+#include <linux/pm_runtime.h>
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0)
+#include <linux/printk.h>
+#else
+#include <linux/kernel.h>
+#endif
+#include <hwif/hwif.h>
+#include "sdio_def.h"
+#if (defined(CONFIG_SSV_SUPPORT_ANDROID)||defined(CONFIG_SSV_BUILD_AS_ONE_KO))
+#include "sdio.h"
+#endif
+#define LOW_SPEED_SDIO_CLOCK (25000000)
+#define HIGH_SPEED_SDIO_CLOCK (50000000)
+#define MAX_RX_FRAME_SIZE 0x900
+#define MAX_REG_RETRY_CNT (3)
+#define SSV_VENDOR_ID 0x3030
+#define SSV_CABRIO_DEVID 0x3030
+#define CHECK_IO_RET(GLUE,RET) \
+    do { \
+        if (RET) { \
+            if ((++((GLUE)->err_count)) > MAX_ERR_COUNT) \
+                printk(KERN_ERR "MAX SDIO Error\n"); \
+        } else \
+            (GLUE)->err_count = 0; \
+    } while (0)
+#define MAX_ERR_COUNT (10)
+struct ssv6xxx_sdio_glue {
+    struct device *dev;
+    struct platform_device *core;
+    struct ssv6xxx_platform_data *p_wlan_data;
+    struct ssv6xxx_platform_data  tmp_data;
+#ifdef CONFIG_MMC_DISALLOW_STACK
+    PLATFORM_DMA_ALIGNED u8 rreg_data[4];
+    PLATFORM_DMA_ALIGNED u8 wreg_data[8];
+    PLATFORM_DMA_ALIGNED u32 brreg_data[MAX_BURST_READ_REG_AMOUNT];
+    PLATFORM_DMA_ALIGNED u8 bwreg_data[MAX_BURST_WRITE_REG_AMOUNT][8];
+    PLATFORM_DMA_ALIGNED u32 aggr_readsz;
+#endif
+#ifdef CONFIG_FW_ALIGNMENT_CHECK
+    struct sk_buff *dmaSkb;
+#endif
+
+
+    /* for ssv SDIO */
+    unsigned int                dataIOPort;
+    unsigned int                regIOPort;
+
+    irq_handler_t               irq_handler;
+    void *irq_dev;
+    bool                        dev_ready;
+    unsigned int                err_count;
+};
+static void ssv6xxx_high_sdio_clk(struct sdio_func *func);
+static void ssv6xxx_low_sdio_clk(struct sdio_func *func);
+static void ssv6xxx_do_sdio_reset_reinit(struct ssv6xxx_platform_data *pwlan_data,
+        struct sdio_func *func, struct ssv6xxx_sdio_glue *glue);
+#define IS_GLUE_INVALID(glue) \
+      ( (glue == NULL) \
+       || (glue->dev_ready == false) \
+       || ( (glue->p_wlan_data != NULL) \
+           && (glue->p_wlan_data->is_enabled == false)) \
+       || (glue->err_count > MAX_ERR_COUNT))
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0)
+static const struct sdio_device_id ssv6xxx_sdio_devices[] __devinitconst =
+#else
+static const struct sdio_device_id ssv6xxx_sdio_devices[] =
+#endif
+{
+    { SDIO_DEVICE(SSV_VENDOR_ID, SSV_CABRIO_DEVID) },
+    {}
+};
+MODULE_DEVICE_TABLE(sdio, ssv6xxx_sdio_devices);
+static bool ssv6xxx_is_ready (struct device *child)
+{
+    struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+    if (IS_GLUE_INVALID(glue))
+        return false;
+    return glue->dev_ready;
+}
+static int ssv6xxx_sdio_cmd52_read(struct device *child, u32 addr,
+                                   u32 *value)
+{
+    int ret = -1;
+    struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+    struct sdio_func *func;
+    if (IS_GLUE_INVALID(glue))
+        return ret;
+    if ( glue != NULL ) {
+        func = dev_to_sdio_func(glue->dev);
+        sdio_claim_host(func);
+        *value = sdio_readb(func, addr, &ret);
+        sdio_release_host(func);
+        CHECK_IO_RET(glue, ret);
+    }
+    return ret;
+}
+static int ssv6xxx_sdio_cmd52_write(struct device *child, u32 addr,
+                                    u32 value)
+{
+    int ret = -1;
+    struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+    struct sdio_func *func;
+    if (IS_GLUE_INVALID(glue)) {
+        return ret;
+    }
+    if ( glue != NULL ) {
+        func = dev_to_sdio_func(glue->dev);
+        sdio_claim_host(func);
+        sdio_writeb(func, value, addr, &ret);
+        sdio_release_host(func);
+        CHECK_IO_RET(glue, ret);
+    }
+    return ret;
+}
+static int __must_check __ssv6xxx_sdio_read_reg (struct ssv6xxx_sdio_glue *glue, u32 addr,
+        u32 *buf)
+{
+    int ret = (-1);
+    struct sdio_func *func ;
+#if !defined(CONFIG_MMC_DISALLOW_STACK) && defined(CONFIG_FW_ALIGNMENT_CHECK)
+    PLATFORM_DMA_ALIGNED u8 data[4];
+#elif !defined(CONFIG_MMC_DISALLOW_STACK)
+    u8 data[4];
+#endif
+
+    if (IS_GLUE_INVALID(glue)) {
+        return ret;
+    }
+
+    //dev_err(&func->dev, "sdio read reg device[%08x] parent[%08x]\n",child,child->parent);
+
+    if ( glue != NULL ) {
+        func = dev_to_sdio_func(glue->dev);
+        sdio_claim_host(func);
+
+        // 4 bytes address
+#ifdef CONFIG_MMC_DISALLOW_STACK
+        glue->rreg_data[0] = (addr >> ( 0 )) &0xff;
+        glue->rreg_data[1] = (addr >> ( 8 )) &0xff;
+        glue->rreg_data[2] = (addr >> ( 16 )) &0xff;
+        glue->rreg_data[3] = (addr >> ( 24 )) &0xff;
+#else
+        data[0] = (addr >> ( 0 )) &0xff;
+        data[1] = (addr >> ( 8 )) &0xff;
+        data[2] = (addr >> ( 16 )) &0xff;
+        data[3] = (addr >> ( 24 )) &0xff;
+#endif
+#ifdef CONFIG_MMC_DISALLOW_STACK
+        ret = sdio_memcpy_toio(func, glue->regIOPort, glue->rreg_data, 4);
+#else
+        ret = sdio_memcpy_toio(func, glue->regIOPort, data, 4);
+#endif
+        if (WARN_ON(ret)) {
+            dev_err(&func->dev, "sdio read reg write address failed (%d)\n", ret);
+            goto io_err;
+        }
+
+#ifdef CONFIG_MMC_DISALLOW_STACK
+        ret = sdio_memcpy_fromio(func, glue->rreg_data, glue->regIOPort, 4);
+#else
+        ret = sdio_memcpy_fromio(func, data, glue->regIOPort, 4);
+#endif
+        if (WARN_ON(ret)) {
+            dev_err(&func->dev, "sdio read reg from I/O failed (%d)\n",ret);
+            goto io_err;
+        }
+        if(ret == 0) {
+#ifdef CONFIG_MMC_DISALLOW_STACK
+            *buf = (glue->rreg_data[0]&0xff);
+            *buf = *buf | ((glue->rreg_data[1]&0xff)<<( 8 ));
+            *buf = *buf | ((glue->rreg_data[2]&0xff)<<( 16 ));
+            *buf = *buf | ((glue->rreg_data[3]&0xff)<<( 24 ));
+#else
+            *buf = (data[0]&0xff);
+            *buf = *buf | ((data[1]&0xff)<<( 8 ));
+            *buf = *buf | ((data[2]&0xff)<<( 16 ));
+            *buf = *buf | ((data[3]&0xff)<<( 24 ));
+#endif
+        } else
+            *buf = 0xffffffff;
+io_err:
+        sdio_release_host(func);
+        CHECK_IO_RET(glue, ret);
+    } else {
+        dev_err(&func->dev, "sdio read reg glue == NULL!!!\n");
+    }
+    return ret;
+}
+static int __must_check __ssv6xxx_sdio_safe_read_reg (struct ssv6xxx_sdio_glue *glue, u32 addr,
+        u32 *buf)
+{
+    int ret = (-1), rdy_flag_cnt = 0;
+    struct sdio_func *func ;
+#if !defined(CONFIG_MMC_DISALLOW_STACK) && defined(CONFIG_FW_ALIGNMENT_CHECK)
+    PLATFORM_DMA_ALIGNED u8 data[4];
+#elif !defined(CONFIG_MMC_DISALLOW_STACK)
+    u8 data[4];
+#endif
+
+    if (IS_GLUE_INVALID(glue)) {
+        return ret;
+    }
+
+    //dev_err(&func->dev, "sdio read reg device[%08x] parent[%08x]\n",child,child->parent);
+
+    if ( glue != NULL ) {
+        func = dev_to_sdio_func(glue->dev);
+        sdio_claim_host(func);
+
+        // 4 bytes address
+#ifdef CONFIG_MMC_DISALLOW_STACK
+        glue->rreg_data[0] = (addr >> ( 0 )) &0xff;
+        glue->rreg_data[1] = (addr >> ( 8 )) &0xff;
+        glue->rreg_data[2] = (addr >> ( 16 )) &0xff;
+        glue->rreg_data[3] = (addr >> ( 24 )) &0xff;
+#else
+        data[0] = (addr >> ( 0 )) &0xff;
+        data[1] = (addr >> ( 8 )) &0xff;
+        data[2] = (addr >> ( 16 )) &0xff;
+        data[3] = (addr >> ( 24 )) &0xff;
+#endif
+
+        //8 byte ( 4 bytes address , 4 bytes data )
+#if (defined(SSV_SUPPORT_SSV6006))
+        while(sdio_readb(func, REG_SD_READY_FLAG, &ret) != SDIO_READY_FLAG_IDLE) {
+            if (ret != 0) {
+                printk("%s: ret=%d", __func__, ret);
+                goto io_err;
+            } else if (++rdy_flag_cnt > SDIO_READY_FLAG_BUSY_THRESHOLD) {
+                ret = -EBUSY;
+                dev_err(&func->dev, "%s: bus is busy\n", __func__);
+                goto io_err;
+            }
+            udelay(SDIO_READY_FLAG_BUSY_DELAY);
+        }
+#endif
+#ifdef CONFIG_MMC_DISALLOW_STACK
+        ret = sdio_memcpy_toio(func, glue->regIOPort, glue->rreg_data, 4);
+#else
+        ret = sdio_memcpy_toio(func, glue->regIOPort, data, 4);
+#endif
+        if (WARN_ON(ret)) {
+            dev_err(&func->dev, "%s: sdio write to I/O failed (%d)\n", __func__, ret);
+            goto io_err;
+        }
+        rdy_flag_cnt = 0;
+#if (defined(SSV_SUPPORT_SSV6006))
+        while(sdio_readb(func, REG_SD_READY_FLAG, &ret) != SDIO_READY_FLAG_IDLE) {
+            if (ret != 0) {
+                printk("%s: ret=%d", __func__, ret);
+                goto io_err;
+            } else if (++rdy_flag_cnt > SDIO_READY_FLAG_BUSY_THRESHOLD) {
+                ret = -EBUSY;
+                dev_err(&func->dev, "%s: bus is busy\n", __func__);
+                goto io_err;
+            }
+            udelay(SDIO_READY_FLAG_BUSY_DELAY);
+        }
+#endif
+
+#ifdef CONFIG_MMC_DISALLOW_STACK
+        ret = sdio_memcpy_fromio(func, glue->rreg_data, glue->regIOPort, 4);
+#else
+        ret = sdio_memcpy_fromio(func, data, glue->regIOPort, 4);
+#endif
+        if (WARN_ON(ret)) {
+            dev_err(&func->dev, "%s: sdio read from I/O failed (%d)\n", __func__,ret);
+            goto io_err;
+        }
+        if(ret == 0) {
+#ifdef CONFIG_MMC_DISALLOW_STACK
+            *buf = (glue->rreg_data[0]&0xff);
+            *buf = *buf | ((glue->rreg_data[1]&0xff)<<( 8 ));
+            *buf = *buf | ((glue->rreg_data[2]&0xff)<<( 16 ));
+            *buf = *buf | ((glue->rreg_data[3]&0xff)<<( 24 ));
+#else
+            *buf = (data[0]&0xff);
+            *buf = *buf | ((data[1]&0xff)<<( 8 ));
+            *buf = *buf | ((data[2]&0xff)<<( 16 ));
+            *buf = *buf | ((data[3]&0xff)<<( 24 ));
+#endif
+        } else
+            *buf = 0xffffffff;
+io_err:
+        sdio_release_host(func);
+        CHECK_IO_RET(glue, ret);
+    } else {
+        dev_err(&func->dev, "sdio read reg glue == NULL!!!\n");
+    }
+    return ret;
+}
+static int __must_check ssv6xxx_sdio_read_reg(struct device *child, u32 addr,
+        u32 *buf)
+{
+    struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+    int i, ret;
+    for (i = 0; i < MAX_REG_RETRY_CNT; i++) {
+        ret = __ssv6xxx_sdio_read_reg(glue, addr, buf);
+        if (!ret)
+            return ret;
+    }
+    HWIF_DBG_PRINT(glue->p_wlan_data, "%s: Fail to read register, addr 0x%08x\n", __FUNCTION__, addr);
+    return ret;
+}
+static int __must_check ssv6xxx_sdio_safe_read_reg(struct device *child, u32 addr,
+        u32 *buf)
+{
+    struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+    int i, ret;
+    for (i = 0; i < MAX_REG_RETRY_CNT; i++) {
+        ret = __ssv6xxx_sdio_safe_read_reg(glue, addr, buf);
+        if (!ret)
+            return ret;
+    }
+    HWIF_DBG_PRINT(glue->p_wlan_data, "%s: Fail to read register, addr 0x%08x\n", __FUNCTION__, addr);
+    return ret;
+}
+#ifdef ENABLE_WAKE_IO_ISR_WHEN_HCI_ENQUEUE
+static int ssv6xxx_sdio_trigger_tx_rx (struct device *child)
+{
+    int ret = (-1);
+    struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+    struct sdio_func *func;
+    struct mmc_host *host;
+    if (IS_GLUE_INVALID(glue))
+        return ret;
+    func = dev_to_sdio_func(glue->dev);
+    host = func->card->host;
+    mmc_signal_sdio_irq(host);
+    return 0;
+}
+#endif
+static int __must_check __ssv6xxx_sdio_write_reg (struct ssv6xxx_sdio_glue *glue, u32 addr,
+        u32 buf)
+{
+    int ret = (-1);
+    struct sdio_func *func;
+#if !defined(CONFIG_MMC_DISALLOW_STACK) && defined(CONFIG_FW_ALIGNMENT_CHECK)
+    PLATFORM_DMA_ALIGNED u8 data[8];
+#elif !defined(CONFIG_MMC_DISALLOW_STACK)
+    u8 data[8];
+#endif
+
+    if (IS_GLUE_INVALID(glue)) {
+        return ret;
+    }
+
+    if ( glue != NULL ) {
+        func = dev_to_sdio_func(glue->dev);
+        sdio_claim_host(func);
+
+        // 4 bytes address
+#ifdef CONFIG_MMC_DISALLOW_STACK
+        glue->wreg_data[0] = (addr >> ( 0 )) &0xff;
+        glue->wreg_data[1] = (addr >> ( 8 )) &0xff;
+        glue->wreg_data[2] = (addr >> ( 16 )) &0xff;
+        glue->wreg_data[3] = (addr >> ( 24 )) &0xff;
+#else
+        data[0] = (addr >> ( 0 )) &0xff;
+        data[1] = (addr >> ( 8 )) &0xff;
+        data[2] = (addr >> ( 16 )) &0xff;
+        data[3] = (addr >> ( 24 )) &0xff;
+#endif
+
+        // 4 bytes data
+#ifdef CONFIG_MMC_DISALLOW_STACK
+        glue->wreg_data[4] = (buf >> ( 0 )) &0xff;
+        glue->wreg_data[5] = (buf >> ( 8 )) &0xff;
+        glue->wreg_data[6] = (buf >> ( 16 )) &0xff;
+        glue->wreg_data[7] = (buf >> ( 24 )) &0xff;
+#else
+        data[4] = (buf >> ( 0 )) &0xff;
+        data[5] = (buf >> ( 8 )) &0xff;
+        data[6] = (buf >> ( 16 )) &0xff;
+        data[7] = (buf >> ( 24 )) &0xff;
+#endif
+
+        //8 byte ( 4 bytes address , 4 bytes data )
+#ifdef CONFIG_MMC_DISALLOW_STACK
+        ret = sdio_memcpy_toio(func, glue->regIOPort, glue->wreg_data, 8);
+#else
+        ret = sdio_memcpy_toio(func, glue->regIOPort, data, 8);
+#endif
+
+        sdio_release_host(func);
+        CHECK_IO_RET(glue, ret);
+    } else {
+        dev_err(&func->dev, "sdio write reg glue == NULL!!!\n");
+    }
+    return ret;
+}
+static int __must_check __ssv6xxx_sdio_safe_write_reg (struct ssv6xxx_sdio_glue *glue, u32 addr,
+        u32 buf)
+{
+    int ret = (-1);
+    struct sdio_func *func;
+#if !defined(CONFIG_MMC_DISALLOW_STACK) && defined(CONFIG_FW_ALIGNMENT_CHECK)
+    PLATFORM_DMA_ALIGNED u8 data[8];
+#elif !defined(CONFIG_MMC_DISALLOW_STACK)
+    u8 data[8];
+#endif
+#if (defined(SSV_SUPPORT_SSV6006))
+    int rdy_flag_cnt = 0;
+#endif
+    if (IS_GLUE_INVALID(glue))
+        return ret;
+    if ( glue != NULL ) {
+        func = dev_to_sdio_func(glue->dev);
+        sdio_claim_host(func);
+#ifdef CONFIG_MMC_DISALLOW_STACK
+        glue->wreg_data[0] = (addr >> ( 0 )) &0xff;
+        glue->wreg_data[1] = (addr >> ( 8 )) &0xff;
+        glue->wreg_data[2] = (addr >> ( 16 )) &0xff;
+        glue->wreg_data[3] = (addr >> ( 24 )) &0xff;
+#else
+        data[0] = (addr >> ( 0 )) &0xff;
+        data[1] = (addr >> ( 8 )) &0xff;
+        data[2] = (addr >> ( 16 )) &0xff;
+        data[3] = (addr >> ( 24 )) &0xff;
+#endif
+#ifdef CONFIG_MMC_DISALLOW_STACK
+        glue->wreg_data[4] = (buf >> ( 0 )) &0xff;
+        glue->wreg_data[5] = (buf >> ( 8 )) &0xff;
+        glue->wreg_data[6] = (buf >> ( 16 )) &0xff;
+        glue->wreg_data[7] = (buf >> ( 24 )) &0xff;
+#else
+        data[4] = (buf >> ( 0 )) &0xff;
+        data[5] = (buf >> ( 8 )) &0xff;
+        data[6] = (buf >> ( 16 )) &0xff;
+        data[7] = (buf >> ( 24 )) &0xff;
+#endif
+
+#if (defined(SSV_SUPPORT_SSV6006))
+        while(sdio_readb(func, REG_SD_READY_FLAG, &ret) != SDIO_READY_FLAG_IDLE) {
+            if (ret != 0) {
+                printk("%s: ret=%d", __func__, ret);
+                goto io_err;
+            } else if (++rdy_flag_cnt > SDIO_READY_FLAG_BUSY_THRESHOLD) {
+                ret = -EBUSY;
+                dev_err(&func->dev, "%s: bus is busy\n", __func__);
+                goto io_err;
+            }
+            udelay(SDIO_READY_FLAG_BUSY_DELAY);
+        }
+#endif
+#ifdef CONFIG_MMC_DISALLOW_STACK
+        ret = sdio_memcpy_toio(func, glue->regIOPort, glue->wreg_data, 8);
+#else
+        ret = sdio_memcpy_toio(func, glue->regIOPort, data, 8);
+#endif
+        if (WARN_ON(ret)) {
+            dev_err(&func->dev, "%s: sdio write to I/O failed (%d)\n", __func__, ret);
+            goto io_err;
+        }
+#if (defined(SSV_SUPPORT_SSV6006))
+        while(sdio_readb(func, REG_SD_READY_FLAG, &ret) != SDIO_READY_FLAG_IDLE) {
+            if (ret != 0) {
+                printk("%s: ret=%d", __func__, ret);
+                goto io_err;
+            } else if (++rdy_flag_cnt > SDIO_READY_FLAG_BUSY_THRESHOLD) {
+                ret = -EBUSY;
+                dev_err(&func->dev, "%s: bus is busy\n", __func__);
+                goto io_err;
+            }
+            udelay(SDIO_READY_FLAG_BUSY_DELAY);
+        }
+#endif
+io_err:
+        sdio_release_host(func);
+        CHECK_IO_RET(glue, ret);
+    } else {
+        dev_err(&func->dev, "sdio write reg glue == NULL!!!\n");
+    }
+    return ret;
+}
+static int __must_check ssv6xxx_sdio_write_reg(struct device *child, u32 addr,
+        u32 buf)
+{
+    struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+    int i, ret;
+    for (i = 0; i < MAX_REG_RETRY_CNT; i++) {
+        ret = __ssv6xxx_sdio_write_reg(glue, addr, buf);
+        if (!ret) {
+#ifdef __x86_64
+            udelay(50);
+#endif
+            return ret;
+        }
+    }
+    HWIF_DBG_PRINT(glue->p_wlan_data, "%s: Fail to write register, addr 0x%08x, value 0x%08x\n", __FUNCTION__, addr, buf);
+    return ret;
+}
+static int __must_check ssv6xxx_sdio_safe_write_reg(struct device *child, u32 addr,
+        u32 buf)
+{
+    struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+    int i, ret;
+    for (i = 0; i < MAX_REG_RETRY_CNT; i++) {
+        ret = __ssv6xxx_sdio_safe_write_reg(glue, addr, buf);
+        if (!ret) {
+#ifdef __x86_64
+            udelay(50);
+#endif
+            return ret;
+        }
+    }
+    HWIF_DBG_PRINT(glue->p_wlan_data, "%s: Fail to write register, addr 0x%08x, value 0x%08x\n", __FUNCTION__, addr, buf);
+    return ret;
+}
+static int __must_check ssv6xxx_sdio_burst_read_reg(struct device *child, u32 *addr,
+        u32 *buf, u8 reg_amount)
+{
+    int ret = (-1);
+    struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+    struct sdio_func *func ;
+#if !defined(CONFIG_MMC_DISALLOW_STACK) && defined(CONFIG_FW_ALIGNMENT_CHECK)
+    PLATFORM_DMA_ALIGNED u32 data[MAX_BURST_READ_REG_AMOUNT]= {0};
+#elif !defined(CONFIG_MMC_DISALLOW_STACK)
+    u32 data[MAX_BURST_READ_REG_AMOUNT]= {0};
+#endif
+    u8 i = 0;
+
+    if (IS_GLUE_INVALID(glue)) {
+        return ret;
+    }
+
+    if (reg_amount > MAX_BURST_READ_REG_AMOUNT) {
+        HWIF_DBG_PRINT(glue->p_wlan_data, "The amount of sdio burst-read register must <= %d\n",
+                       MAX_BURST_READ_REG_AMOUNT);
+        return ret;
+    }
+    if ( glue != NULL ) {
+        func = dev_to_sdio_func(glue->dev);
+        sdio_claim_host(func);
+        for (i=0; i<reg_amount; i++) {
+#ifdef CONFIG_MMC_DISALLOW_STACK
+            memcpy(&glue->brreg_data[i], &addr[i], 4);
+#else
+            memcpy(&data[i], &addr[i], 4);
+#endif
+        }
+
+#ifdef CONFIG_MMC_DISALLOW_STACK
+        ret = sdio_memcpy_toio(func, IO_REG_BURST_RD_PORT_REG, glue->brreg_data, reg_amount*4);
+#else
+        ret = sdio_memcpy_toio(func, IO_REG_BURST_RD_PORT_REG, data, reg_amount*4);
+#endif
+
+        if (WARN_ON(ret)) {
+            dev_err(child->parent, "sdio burst-read reg write address failed (%d)\n", ret);
+            goto io_err;
+        }
+
+#ifdef CONFIG_MMC_DISALLOW_STACK
+        ret = sdio_memcpy_fromio(func, glue->brreg_data, IO_REG_BURST_RD_PORT_REG, reg_amount*4);
+#else
+        ret = sdio_memcpy_fromio(func, data, IO_REG_BURST_RD_PORT_REG, reg_amount*4);
+#endif
+        if (WARN_ON(ret)) {
+            dev_err(child->parent, "sdio burst-read reg from I/O failed (%d)\n",ret);
+            goto io_err;
+        }
+        if(ret == 0)
+#ifdef CONFIG_MMC_DISALLOW_STACK
+            memcpy(buf, glue->brreg_data, reg_amount*4);
+#else
+            memcpy(buf, data, reg_amount*4);
+#endif
+        else
+            memset(buf, 0xffffffff, reg_amount*4);
+io_err:
+        sdio_release_host(func);
+        CHECK_IO_RET(glue, ret);
+    } else {
+        dev_err(child->parent, "sdio burst-read reg glue == NULL!!!\n");
+    }
+    return ret;
+}
+static int __must_check ssv6xxx_sdio_burst_safe_read_reg(struct device *child, u32 *addr,
+        u32 *buf, u8 reg_amount)
+{
+    int ret = (-1);
+    struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+    struct sdio_func *func ;
+#if !defined(CONFIG_MMC_DISALLOW_STACK) && defined(CONFIG_FW_ALIGNMENT_CHECK)
+    PLATFORM_DMA_ALIGNED u32 data[MAX_BURST_READ_REG_AMOUNT]= {0};
+#elif !defined(CONFIG_MMC_DISALLOW_STACK)
+    u32 data[MAX_BURST_READ_REG_AMOUNT]= {0};
+#endif
+    u8 i = 0;
+#if (defined(SSV_SUPPORT_SSV6006))
+    int rdy_flag_cnt = 0;
+#endif
+    if (IS_GLUE_INVALID(glue)) {
+        return ret;
+    }
+
+    if (reg_amount > MAX_BURST_READ_REG_AMOUNT) {
+        HWIF_DBG_PRINT(glue->p_wlan_data, "The amount of sdio burst-read register must <= %d\n",
+                       MAX_BURST_READ_REG_AMOUNT);
+        return ret;
+    }
+    if ( glue != NULL ) {
+        func = dev_to_sdio_func(glue->dev);
+        sdio_claim_host(func);
+        for (i=0; i<reg_amount; i++) {
+#ifdef CONFIG_MMC_DISALLOW_STACK
+            memcpy(&glue->brreg_data[i], &addr[i], 4);
+#else
+            memcpy(&data[i], &addr[i], 4);
+#endif
+        }
+
+#if (defined(SSV_SUPPORT_SSV6006))
+        while(sdio_readb(func, REG_SD_READY_FLAG, &ret) != SDIO_READY_FLAG_IDLE) {
+            if (ret != 0) {
+                printk("%s: ret=%d", __func__, ret);
+                goto io_err;
+            } else if (++rdy_flag_cnt > SDIO_READY_FLAG_BUSY_THRESHOLD) {
+                ret = -EBUSY;
+                dev_err(&func->dev, "%s: bus is busy\n", __func__);
+                goto io_err;
+            }
+            udelay(SDIO_READY_FLAG_BUSY_DELAY);
+        }
+#endif
+
+#ifdef CONFIG_MMC_DISALLOW_STACK
+        ret = sdio_memcpy_toio(func, IO_REG_BURST_RD_PORT_REG, glue->brreg_data, reg_amount*4);
+#else
+        ret = sdio_memcpy_toio(func, IO_REG_BURST_RD_PORT_REG, data, reg_amount*4);
+#endif
+
+        if (WARN_ON(ret)) {
+            dev_err(child->parent, "%s: sdio write to I/O failed (%d)\n", __func__, ret);
+            goto io_err;
+        }
+#if (defined(SSV_SUPPORT_SSV6006))
+        while(sdio_readb(func, REG_SD_READY_FLAG, &ret) != SDIO_READY_FLAG_IDLE) {
+            if (ret != 0) {
+                printk("%s: ret=%d", __func__, ret);
+                goto io_err;
+            } else if (++rdy_flag_cnt > SDIO_READY_FLAG_BUSY_THRESHOLD) {
+                ret = -EBUSY;
+                dev_err(&func->dev, "%s: bus is busy\n", __func__);
+                goto io_err;
+            }
+            udelay(SDIO_READY_FLAG_BUSY_DELAY);
+        }
+#endif
+
+#ifdef CONFIG_MMC_DISALLOW_STACK
+        ret = sdio_memcpy_fromio(func, glue->brreg_data, IO_REG_BURST_RD_PORT_REG, reg_amount*4);
+#else
+        ret = sdio_memcpy_fromio(func, data, IO_REG_BURST_RD_PORT_REG, reg_amount*4);
+#endif
+        if (WARN_ON(ret)) {
+            dev_err(child->parent, "%s: sdio read from I/O failed (%d)\n", __func__, ret);
+            goto io_err;
+        }
+        if(ret == 0)
+#ifdef CONFIG_MMC_DISALLOW_STACK
+            memcpy(buf, glue->brreg_data, reg_amount*4);
+#else
+            memcpy(buf, data, reg_amount*4);
+#endif
+        else
+            memset(buf, 0xffffffff, reg_amount*4);
+io_err:
+        sdio_release_host(func);
+        CHECK_IO_RET(glue, ret);
+    } else {
+        dev_err(child->parent, "sdio burst-read reg glue == NULL!!!\n");
+    }
+    return ret;
+}
+static int __must_check ssv6xxx_sdio_burst_write_reg(struct device *child, u32 *addr,
+        u32 *buf, u8 reg_amount)
+{
+    int ret = (-1);
+    struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+    struct sdio_func *func ;
+#if !defined(CONFIG_MMC_DISALLOW_STACK) && defined(CONFIG_FW_ALIGNMENT_CHECK)
+    PLATFORM_DMA_ALIGNED u8 data[MAX_BURST_WRITE_REG_AMOUNT][8]= {{0},{0}};
+#elif !defined(CONFIG_MMC_DISALLOW_STACK)
+    u8 data[MAX_BURST_WRITE_REG_AMOUNT][8]= {{0},{0}};
+#endif
+    u8 i = 0;
+    if (IS_GLUE_INVALID(glue)) {
+        return ret;
+    }
+
+    if (reg_amount > MAX_BURST_WRITE_REG_AMOUNT) {
+        HWIF_DBG_PRINT(glue->p_wlan_data, "The amount of sdio burst-read register must <= %d\n",
+                       MAX_BURST_WRITE_REG_AMOUNT);
+        return ret;
+    }
+    if ( glue != NULL ) {
+        func = dev_to_sdio_func(glue->dev);
+        sdio_claim_host(func);
+        for (i=0; i<reg_amount; i++) {
+#ifdef CONFIG_MMC_DISALLOW_STACK
+            glue->bwreg_data[i][0] = (addr[i] >> ( 0 )) &0xff;
+            glue->bwreg_data[i][1] = (addr[i] >> ( 8 )) &0xff;
+            glue->bwreg_data[i][2] = (addr[i] >> ( 16 )) &0xff;
+            glue->bwreg_data[i][3] = (addr[i] >> ( 24 )) &0xff;
+#else
+            data[i][0] = (addr[i] >> ( 0 )) &0xff;
+            data[i][1] = (addr[i] >> ( 8 )) &0xff;
+            data[i][2] = (addr[i] >> ( 16 )) &0xff;
+            data[i][3] = (addr[i] >> ( 24 )) &0xff;
+#endif
+
+            // 4 bytes data
+#ifdef CONFIG_MMC_DISALLOW_STACK
+            glue->bwreg_data[i][4] = (buf[i] >> ( 0 )) &0xff;
+            glue->bwreg_data[i][5] = (buf[i] >> ( 8 )) &0xff;
+            glue->bwreg_data[i][6] = (buf[i] >> ( 16 )) &0xff;
+            glue->bwreg_data[i][7] = (buf[i] >> ( 24 )) &0xff;
+#else
+            data[i][4] = (buf[i] >> ( 0 )) &0xff;
+            data[i][5] = (buf[i] >> ( 8 )) &0xff;
+            data[i][6] = (buf[i] >> ( 16 )) &0xff;
+            data[i][7] = (buf[i] >> ( 24 )) &0xff;
+#endif
+        }
+
+#ifdef CONFIG_MMC_DISALLOW_STACK
+        ret = sdio_memcpy_toio(func, IO_REG_BURST_WR_PORT_REG, glue->bwreg_data, reg_amount*8);
+#else
+        ret = sdio_memcpy_toio(func, IO_REG_BURST_WR_PORT_REG, data, reg_amount*8);
+#endif
+        sdio_release_host(func);
+        CHECK_IO_RET(glue, ret);
+    } else {
+        dev_err(child->parent, "sdio burst-write reg glue == NULL!!!\n");
+    }
+    return ret;
+}
+static int __must_check ssv6xxx_sdio_burst_safe_write_reg(struct device *child, u32 *addr,
+        u32 *buf, u8 reg_amount)
+{
+    int ret = (-1);
+    struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+    struct sdio_func *func ;
+#if !defined(CONFIG_MMC_DISALLOW_STACK) && defined(CONFIG_FW_ALIGNMENT_CHECK)
+    PLATFORM_DMA_ALIGNED u8 data[MAX_BURST_WRITE_REG_AMOUNT][8]= {{0},{0}};
+#elif !defined(CONFIG_MMC_DISALLOW_STACK)
+    u8 data[MAX_BURST_WRITE_REG_AMOUNT][8]= {{0},{0}};
+#endif
+    u8 i = 0;
+#if (defined(SSV_SUPPORT_SSV6006))
+    int rdy_flag_cnt = 0;
+#endif
+    if (IS_GLUE_INVALID(glue)) {
+        return ret;
+    }
+    if (reg_amount > MAX_BURST_WRITE_REG_AMOUNT) {
+        HWIF_DBG_PRINT(glue->p_wlan_data, "The amount of sdio burst-read register must <= %d\n",
+                       MAX_BURST_WRITE_REG_AMOUNT);
+        return ret;
+    }
+    if ( glue != NULL ) {
+        func = dev_to_sdio_func(glue->dev);
+        sdio_claim_host(func);
+        for (i=0; i<reg_amount; i++) {
+            // 4 bytes address
+#ifdef CONFIG_MMC_DISALLOW_STACK
+            glue->bwreg_data[i][0] = (addr[i] >> ( 0 )) &0xff;
+            glue->bwreg_data[i][1] = (addr[i] >> ( 8 )) &0xff;
+            glue->bwreg_data[i][2] = (addr[i] >> ( 16 )) &0xff;
+            glue->bwreg_data[i][3] = (addr[i] >> ( 24 )) &0xff;
+#else
+            data[i][0] = (addr[i] >> ( 0 )) &0xff;
+            data[i][1] = (addr[i] >> ( 8 )) &0xff;
+            data[i][2] = (addr[i] >> ( 16 )) &0xff;
+            data[i][3] = (addr[i] >> ( 24 )) &0xff;
+#endif
+
+            // 4 bytes data
+#ifdef CONFIG_MMC_DISALLOW_STACK
+            glue->bwreg_data[i][4] = (buf[i] >> ( 0 )) &0xff;
+            glue->bwreg_data[i][5] = (buf[i] >> ( 8 )) &0xff;
+            glue->bwreg_data[i][6] = (buf[i] >> ( 16 )) &0xff;
+            glue->bwreg_data[i][7] = (buf[i] >> ( 24 )) &0xff;
+#else
+            data[i][4] = (buf[i] >> ( 0 )) &0xff;
+            data[i][5] = (buf[i] >> ( 8 )) &0xff;
+            data[i][6] = (buf[i] >> ( 16 )) &0xff;
+            data[i][7] = (buf[i] >> ( 24 )) &0xff;
+#endif
+        }
+
+#if (defined(SSV_SUPPORT_SSV6006))
+        while(sdio_readb(func, REG_SD_READY_FLAG, &ret) != SDIO_READY_FLAG_IDLE) {
+            if (ret != 0) {
+                printk("%s: ret=%d", __func__, ret);
+                goto io_err;
+            } else if (++rdy_flag_cnt > SDIO_READY_FLAG_BUSY_THRESHOLD) {
+                ret = -EBUSY;
+                dev_err(&func->dev, "%s: bus is busy\n", __func__);
+                goto io_err;
+            }
+            udelay(SDIO_READY_FLAG_BUSY_DELAY);
+        }
+#endif
+
+#ifdef CONFIG_MMC_DISALLOW_STACK
+        ret = sdio_memcpy_toio(func, IO_REG_BURST_WR_PORT_REG, glue->bwreg_data, reg_amount*8);
+#else
+        ret = sdio_memcpy_toio(func, IO_REG_BURST_WR_PORT_REG, data, reg_amount*8);
+#endif
+        if (WARN_ON(ret)) {
+            dev_err(child->parent, "%s: sdio write to I/O failed (%d)\n", __func__, ret);
+            goto io_err;
+        }
+#if (defined(SSV_SUPPORT_SSV6006))
+        while(sdio_readb(func, REG_SD_READY_FLAG, &ret) != SDIO_READY_FLAG_IDLE) {
+            if (ret != 0) {
+                printk("%s: ret=%d", __func__, ret);
+                goto io_err;
+            } else if (++rdy_flag_cnt > SDIO_READY_FLAG_BUSY_THRESHOLD) {
+                ret = -EBUSY;
+                dev_err(&func->dev, "%s: bus is busy\n", __func__);
+                goto io_err;
+            }
+            udelay(SDIO_READY_FLAG_BUSY_DELAY);
+        }
+#endif
+io_err:
+        sdio_release_host(func);
+        CHECK_IO_RET(glue, ret);
+    } else {
+        dev_err(child->parent, "sdio burst-write reg glue == NULL!!!\n");
+    }
+    return ret;
+}
+static int ssv6xxx_sdio_write_sram(struct device *child, u32 addr, u8 *data, u32 size)
+{
+    int ret = -1;
+    struct ssv6xxx_sdio_glue *glue;
+    struct sdio_func *func=NULL;
+    glue = dev_get_drvdata(child->parent);
+    if (IS_GLUE_INVALID(glue))
+        return ret;
+    func = dev_to_sdio_func(glue->dev);
+    sdio_claim_host(func);
+    do {
+        if (ssv6xxx_sdio_write_reg(child,0xc0000860,addr)) ;
+        sdio_writeb(func, 0x2, REG_Fn1_STATUS, &ret);
+        if (unlikely(ret)) break;
+        ret = sdio_memcpy_toio(func, glue->dataIOPort, data, size);
+        if (unlikely(ret)) break;
+        sdio_writeb(func, 0, REG_Fn1_STATUS, &ret);
+        if (unlikely(ret)) break;
+    } while (0);
+    sdio_release_host(func);
+    CHECK_IO_RET(glue, ret);
+    return ret;
+}
+static int ssv6xxx_sdio_load_firmware(struct device *child, u32 start_addr, u8 *data, int data_length)
+{
+    return ssv6xxx_sdio_write_sram(child, start_addr, data, data_length);
+}
+static void ssv6xxx_sdio_load_fw_pre_config_hwif(struct device *child)
+{
+    struct ssv6xxx_sdio_glue *glue;
+    struct sdio_func *func=NULL;
+    glue = dev_get_drvdata(child->parent);
+    if (!IS_GLUE_INVALID(glue)) {
+        func = dev_to_sdio_func(glue->dev);
+        ssv6xxx_low_sdio_clk(func);
+    }
+}
+static void ssv6xxx_sdio_load_fw_post_config_hwif(struct device *child)
+{
+#ifndef SDIO_USE_SLOW_CLOCK
+    struct ssv6xxx_sdio_glue *glue;
+    struct sdio_func *func=NULL;
+    glue = dev_get_drvdata(child->parent);
+    if (!IS_GLUE_INVALID(glue)) {
+        func = dev_to_sdio_func(glue->dev);
+        ssv6xxx_high_sdio_clk(func);
+    }
+#endif
+}
+static int ssv6xxx_sdio_irq_getstatus(struct device *child,int *status)
+{
+    int ret = (-1);
+    struct ssv6xxx_sdio_glue *glue;
+    struct sdio_func *func;
+    glue = dev_get_drvdata(child->parent);
+    if (IS_GLUE_INVALID(glue))
+        return ret;
+    if ( glue != NULL ) {
+        func = dev_to_sdio_func(glue->dev);
+        sdio_claim_host(func);
+        *status = sdio_readb(func, REG_INT_STATUS, &ret);
+        sdio_release_host(func);
+        CHECK_IO_RET(glue, ret);
+    }
+    return ret;
+}
+#if 0
+static void _sdio_hexdump(const u8 *buf,
+                          size_t len)
+{
+    size_t i;
+    printk("\n-----------------------------\n");
+    printk("hexdump(len=%lu):\n", (unsigned long) len);
+    {
+        for (i = 0; i < len; i++) {
+            printk(" %02x", buf[i]);
+            if((i+1)%40 ==0)
+                printk("\n");
+        }
+    }
+    printk("\n-----------------------------\n");
+}
+#endif
+static size_t ssv6xxx_sdio_get_readsz(struct device *child)
+{
+    struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+    struct sdio_func *func ;
+    size_t size = 0;
+    int ret = -1;
+    u32 addr = SD_REG_BASE+REG_CARD_PKT_LEN_0;
+    u32 buf;
+    func = dev_to_sdio_func(glue->dev);
+    sdio_claim_host(func);
+    ret = ssv6xxx_sdio_safe_read_reg(child, addr, &buf);
+    if (ret) {
+        dev_err(child->parent, "sdio read len failed ret[%d]\n",ret);
+        size = 0;
+    } else {
+        size = (size_t)(buf&0xffff);
+    }
+    sdio_release_host(func);
+    return size;
+}
+static size_t ssv6xxx_sdio_get_aggr_readsz(struct device *child, int mode)
+{
+    struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+    struct sdio_func *func ;
+#if !defined(CONFIG_MMC_DISALLOW_STACK) && defined(CONFIG_FW_ALIGNMENT_CHECK)
+    PLATFORM_DMA_ALIGNED u32 size = 0;
+#else
+    u32 size = 0;
+#endif
+    int ret = -1;
+    func = dev_to_sdio_func(glue->dev);
+    sdio_claim_host(func);
+
+#ifdef CONFIG_MMC_DISALLOW_STACK
+    ret = sdio_memcpy_fromio(func, &glue->aggr_readsz, glue->dataIOPort, sizeof(u32)/* jmp_mpdu_len + accu_rx_len, total 4 bytes */);
+#else
+    ret = sdio_memcpy_fromio(func, &size, glue->dataIOPort, sizeof(u32)/* jmp_mpdu_len + accu_rx_len, total 4 bytes */);
+#endif
+    if (ret) {
+        dev_err(child->parent, "%s(): sdio read failed size ret[%d]\n", __func__, ret);
+#ifdef CONFIG_MMC_DISALLOW_STACK
+        glue->aggr_readsz = 0;
+#else
+        size = 0;
+#endif
+    }
+
+#ifdef CONFIG_MMC_DISALLOW_STACK
+    size = sdio_align_size(func, (glue->aggr_readsz >> 16));// accu_rx_len
+#else
+    size = sdio_align_size(func, (size >> 16));// accu_rx_len
+#endif
+
+    sdio_release_host(func);
+    return (size_t)size;
+}
+static int __must_check ssv6xxx_sdio_read(struct device *child,
+        void *buf, size_t *size, int mode)
+{
+    int ret = (-1), readsize = 0;
+    struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+    struct sdio_func *func ;
+    int readtype = 0;
+    if (IS_GLUE_INVALID(glue))
+        return ret;
+    if (mode == RX_NORMAL_MODE) {
+        *size = ssv6xxx_sdio_get_readsz(child);
+        if (*size == 0)
+            return ret;
+    } else if ((mode == RX_HW_AGG_MODE) || (mode == RX_HW_AGG_MODE_METH3)) {
+        if (*size == 0) {
+            *size = ssv6xxx_sdio_get_aggr_readsz(child, mode);
+            if (*size == 0)
+                return ret;
+        }
+    } else {
+        readtype = glue->p_wlan_data->rx_burstread_size(glue->p_wlan_data->rx_burstread_param);
+        if (readtype == RX_BURSTREAD_SZ_FROM_CMD) {
+            *size = ssv6xxx_sdio_get_readsz(child);
+            if (*size == 0)
+                return ret;
+        } else if (readtype == RX_BURSTREAD_SZ_MAX_FRAME) {
+            *size = MAX_FRAME_SIZE;
+        } else {
+            *size = MAX_FRAME_SIZE_DMG;
+        }
+    }
+    func = dev_to_sdio_func(glue->dev);
+    sdio_claim_host(func);
+    readsize = sdio_align_size(func,*size);
+    *size = readsize;
+    ret = sdio_memcpy_fromio(func, buf, glue->dataIOPort, readsize);
+    if (ret)
+        dev_err(child->parent, "sdio read failed size ret[%d]\n",ret);
+    sdio_release_host(func);
+    CHECK_IO_RET(glue, ret);
+#if 0
+    if(*size > 1500)
+        _sdio_hexdump(buf,*size);
+#endif
+    return ret;
+}
+static int __must_check ssv6xxx_sdio_write(struct device *child,
+        void *buf, size_t len,u8 queue_num)
+{
+    int ret = (-1);
+    struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+    struct sdio_func *func;
+    int writesize;
+    void *tempPointer;
+    struct sk_buff *skb = (struct sk_buff *)buf;
+    if (IS_GLUE_INVALID(glue))
+        return ret;
+    if ( glue != NULL ) {
+#ifdef CONFIG_FW_ALIGNMENT_CHECK
+#ifdef CONFIG_ARM64
+        if (((u64)(skb->data)) & 3) {
+#else
+        if (((u32)(skb->data)) & 3) {
+#endif
+            memcpy(glue->dmaSkb->data,skb->data,len);
+            tempPointer = glue->dmaSkb->data;
+        } else
+#endif
+            tempPointer = skb->data;
+#if 0
+        if(len > 1500)
+            _sdio_hexdump(skb->data,len);
+#endif
+        func = dev_to_sdio_func(glue->dev);
+        sdio_claim_host(func);
+        writesize = sdio_align_size(func,len);
+        do {
+            ret = sdio_memcpy_toio(func, glue->dataIOPort, tempPointer, writesize);
+            if ( ret == -EILSEQ || ret == -ETIMEDOUT ) {
+                ret = -1;
+                break;
+            } else {
+                if(ret)
+                    dev_err(&func->dev,"Unexpected return value ret=[%d]\n",ret);
+            }
+        } while( ret == -EILSEQ || ret == -ETIMEDOUT);
+        sdio_release_host(func);
+        CHECK_IO_RET(glue, ret);
+        if (ret)
+            dev_err(&func->dev, "sdio write failed (%d)\n", ret);
+    }
+    return ret;
+}
+static void ssv6xxx_sdio_irq_handler(struct sdio_func *func)
+{
+    int status;
+    struct ssv6xxx_sdio_glue *glue = sdio_get_drvdata(func);
+    struct ssv6xxx_platform_data *pwlan_data;
+    if (IS_GLUE_INVALID(glue))
+        return;
+    pwlan_data = glue->p_wlan_data;
+    if (glue != NULL && glue->irq_handler != NULL) {
+        atomic_set(&pwlan_data->irq_handling, 1);
+        sdio_release_host(func);
+        if ( glue->irq_handler != NULL )
+            status = glue->irq_handler(0, glue->irq_dev);
+        sdio_claim_host(func);
+        atomic_set(&pwlan_data->irq_handling, 0);
+    }
+}
+static void ssv6xxx_sdio_irq_setmask(struct device *child,int mask)
+{
+    int err_ret;
+    struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+    struct sdio_func *func;
+    if (IS_GLUE_INVALID(glue))
+        return;
+    if ( glue != NULL ) {
+        func = dev_to_sdio_func(glue->dev);
+        sdio_claim_host(func);
+        sdio_writeb(func,mask, REG_INT_MASK, &err_ret);
+        sdio_release_host(func);
+        CHECK_IO_RET(glue, err_ret);
+    }
+}
+static void ssv6xxx_sdio_irq_trigger(struct device *child)
+{
+    int err_ret;
+    struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+    struct sdio_func *func;
+    if (IS_GLUE_INVALID(glue))
+        return;
+    if ( glue != NULL ) {
+        func = dev_to_sdio_func(glue->dev);
+        sdio_claim_host(func);
+        sdio_writeb(func,0x2, REG_INT_TRIGGER, &err_ret);
+        sdio_release_host(func);
+        CHECK_IO_RET(glue, err_ret);
+    }
+}
+static int ssv6xxx_sdio_irq_getmask(struct device *child, u32 *mask)
+{
+    u8 imask = 0;
+    int ret = (-1);
+    struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+    struct sdio_func *func;
+    if (IS_GLUE_INVALID(glue))
+        return ret;
+    if ( glue != NULL ) {
+        func = dev_to_sdio_func(glue->dev);
+        sdio_claim_host(func);
+        imask = sdio_readb(func,REG_INT_MASK, &ret);
+        *mask = imask;
+        sdio_release_host(func);
+    }
+    return ret;
+}
+static void ssv6xxx_sdio_irq_enable(struct device *child)
+{
+    struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+    struct sdio_func *func;
+    int ret;
+    struct ssv6xxx_platform_data *pwlan_data;
+    if (IS_GLUE_INVALID(glue))
+        return;
+    pwlan_data = glue->p_wlan_data;
+    func = dev_to_sdio_func(glue->dev);
+    sdio_claim_host(func);
+    ret = sdio_claim_irq(func, ssv6xxx_sdio_irq_handler);
+    if (ret)
+        dev_err(&func->dev, "Failed to claim sdio irq: %d\n", ret);
+    sdio_release_host(func);
+    CHECK_IO_RET(glue, ret);
+}
+static void ssv6xxx_sdio_irq_disable(struct device *child, bool iswaitirq)
+{
+    struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+    struct sdio_func *func;
+    struct ssv6xxx_platform_data *pwlan_data;
+    int ret;
+    if (IS_GLUE_INVALID(glue))
+        return;
+    HWIF_DBG_PRINT(glue->p_wlan_data, "ssv6xxx_sdio_irq_disable\n");
+    pwlan_data = glue->p_wlan_data;
+    func = dev_to_sdio_func(glue->dev);
+    if (func == NULL) {
+        HWIF_DBG_PRINT(glue->p_wlan_data, "func == NULL\n");
+        return;
+    }
+    sdio_claim_host(func);
+    while (atomic_read(&pwlan_data->irq_handling)) {
+        sdio_release_host(func);
+        schedule_timeout(HZ / 10);
+        sdio_claim_host(func);
+    }
+    ret = sdio_release_irq(func);
+    if (ret)
+        dev_err(&func->dev, "Failed to release sdio irq: %d\n", ret);
+    sdio_release_host(func);
+}
+static void ssv6xxx_sdio_irq_request(struct device *child,irq_handler_t irq_handler,void *irq_dev)
+{
+    struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+    struct sdio_func *func;
+    bool isIrqEn = false;
+    if (IS_GLUE_INVALID(glue))
+        return;
+    func = dev_to_sdio_func(glue->dev);
+    glue->irq_handler = irq_handler;
+    glue->irq_dev = irq_dev;
+    if (isIrqEn) {
+        ssv6xxx_sdio_irq_enable(child);
+    }
+}
+static void ssv6xxx_sdio_read_parameter(struct sdio_func *func,
+                                        struct ssv6xxx_sdio_glue *glue)
+{
+    int err_ret;
+    sdio_claim_host(func);
+    glue->dataIOPort = 0;
+    glue->dataIOPort = glue->dataIOPort | (sdio_readb(func, REG_DATA_IO_PORT_0, &err_ret) << ( 8*0 ));
+    glue->dataIOPort = glue->dataIOPort | (sdio_readb(func, REG_DATA_IO_PORT_1, &err_ret) << ( 8*1 ));
+    glue->dataIOPort = glue->dataIOPort | (sdio_readb(func, REG_DATA_IO_PORT_2, &err_ret) << ( 8*2 ));
+    glue->regIOPort = 0;
+    glue->regIOPort = glue->regIOPort | (sdio_readb(func, REG_REG_IO_PORT_0, &err_ret) << ( 8*0 ));
+    glue->regIOPort = glue->regIOPort | (sdio_readb(func, REG_REG_IO_PORT_1, &err_ret) << ( 8*1 ));
+    glue->regIOPort = glue->regIOPort | (sdio_readb(func, REG_REG_IO_PORT_2, &err_ret) << ( 8*2 ));
+    dev_err(&func->dev, "dataIOPort 0x%x regIOPort 0x%x\n",glue->dataIOPort,glue->regIOPort);
+#ifdef CONFIG_PLATFORM_SDIO_BLOCK_SIZE
+    err_ret = sdio_set_block_size(func,CONFIG_PLATFORM_SDIO_BLOCK_SIZE);
+#else
+    err_ret = sdio_set_block_size(func,SDIO_DEF_BLOCK_SIZE);
+#endif
+    if (err_ret != 0) {
+        printk("SDIO setting SDIO_DEF_BLOCK_SIZE fail!!\n");
+    }
+#ifdef CONFIG_PLATFORM_SDIO_OUTPUT_TIMING
+    sdio_writeb(func, CONFIG_PLATFORM_SDIO_OUTPUT_TIMING,REG_OUTPUT_TIMING_REG, &err_ret);
+#else
+    sdio_writeb(func, SDIO_DEF_OUTPUT_TIMING,REG_OUTPUT_TIMING_REG, &err_ret);
+#endif
+    sdio_writeb(func, 0x00,REG_Fn1_STATUS, &err_ret);
+#if 0
+    sdio_writeb(func,SDIO_TX_ALLOC_SIZE_SHIFT|SDIO_TX_ALLOC_ENABLE,REG_SDIO_TX_ALLOC_SHIFT, &err_ret);
+#endif
+    sdio_release_host(func);
+}
+static void ssv6xxx_do_sdio_wakeup(struct sdio_func *func)
+{
+    int err_ret;
+    if(func != NULL) {
+        sdio_claim_host(func);
+        sdio_writeb(func, 0x01, REG_PMU_WAKEUP, &err_ret);
+        mdelay(10);
+        sdio_writeb(func, 0x00, REG_PMU_WAKEUP, &err_ret);
+        sdio_release_host(func);
+    }
+}
+static void ssv6xxx_sdio_pmu_wakeup(struct device *child)
+{
+    struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+    struct sdio_func *func;
+    if (glue != NULL) {
+        func = dev_to_sdio_func(glue->dev);
+        ssv6xxx_do_sdio_wakeup(func);
+    }
+}
+static bool ssv6xxx_sdio_support_scatter(struct device *child)
+{
+    bool support = false;
+#if LINUX_VERSION_CODE > KERNEL_VERSION(3,0,0)
+    struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+    struct sdio_func *func;
+    do {
+        if (IS_GLUE_INVALID(glue)) {
+            dev_err(child, "ssv6xxx_sdio_enable_scatter glue == NULL!!!\n");
+            break;
+        }
+        func = dev_to_sdio_func(glue->dev);
+        if (func->card->host->max_segs < MAX_SCATTER_ENTRIES_PER_REQ) {
+            dev_err(&func->dev, "host controller only supports scatter of :%d entries, driver need: %d\n",
+                    func->card->host->max_segs,
+                    MAX_SCATTER_ENTRIES_PER_REQ);
+            break;
+        }
+        support = true;
+    } while (0);
+#endif
+    return support;
+}
+static void ssv6xxx_sdio_setup_scat_data(struct sdio_scatter_req *scat_req,
+        struct mmc_data *data)
+{
+    struct scatterlist *sg;
+    int i;
+    data->blksz = SDIO_DEF_BLOCK_SIZE;
+    data->blocks = scat_req->len / SDIO_DEF_BLOCK_SIZE;
+    printk("scatter: (%s)  (block len: %d, block count: %d) , (tot:%d,sg:%d)\n",
+           (scat_req->req & SDIO_WRITE) ? "WR" : "RD",
+           data->blksz, data->blocks, scat_req->len,
+           scat_req->scat_entries);
+    data->flags = (scat_req->req & SDIO_WRITE) ? MMC_DATA_WRITE :
+                  MMC_DATA_READ;
+    sg = scat_req->sgentries;
+    sg_init_table(sg, scat_req->scat_entries);
+    for (i = 0; i < scat_req->scat_entries; i++, sg++) {
+        printk("%d: addr:0x%p, len:%d\n",
+               i, scat_req->scat_list[i].buf,
+               scat_req->scat_list[i].len);
+        sg_set_buf(sg, scat_req->scat_list[i].buf,
+                   scat_req->scat_list[i].len);
+    }
+    data->sg = scat_req->sgentries;
+    data->sg_len = scat_req->scat_entries;
+}
+static inline void ssv6xxx_sdio_set_cmd53_arg(u32 *arg, u8 rw, u8 func,
+        u8 mode, u8 opcode, u32 addr,
+        u16 blksz)
+{
+    *arg = (((rw & 1) << 31) |
+            ((func & 0x7) << 28) |
+            ((mode & 1) << 27) |
+            ((opcode & 1) << 26) |
+            ((addr & 0x1FFFF) << 9) |
+            (blksz & 0x1FF));
+}
+static int ssv6xxx_sdio_rw_scatter(struct device *child,
+                                   struct sdio_scatter_req *scat_req)
+{
+    struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+    struct sdio_func *func;
+    struct mmc_request mmc_req;
+    struct mmc_command cmd;
+    struct mmc_data data;
+    u8 opcode, rw;
+    int status = 1;
+    do {
+        if(!glue) {
+            dev_err(child, "ssv6xxx_sdio_enable_scatter glue == NULL!!!\n");
+            break;
+        }
+        func = dev_to_sdio_func(glue->dev);
+        memset(&mmc_req, 0, sizeof(struct mmc_request));
+        memset(&cmd, 0, sizeof(struct mmc_command));
+        memset(&data, 0, sizeof(struct mmc_data));
+        ssv6xxx_sdio_setup_scat_data(scat_req, &data);
+        opcode = 0;
+        rw = (scat_req->req & SDIO_WRITE) ? CMD53_ARG_WRITE : CMD53_ARG_READ;
+        ssv6xxx_sdio_set_cmd53_arg(&cmd.arg, rw, func->num,
+                                   CMD53_ARG_BLOCK_BASIS, opcode, glue->dataIOPort,
+                                   data.blocks);
+        cmd.opcode = SD_IO_RW_EXTENDED;
+        cmd.flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_ADTC;
+        mmc_req.cmd = &cmd;
+        mmc_req.data = &data;
+        mmc_set_data_timeout(&data, func->card);
+        mmc_wait_for_req(func->card->host, &mmc_req);
+        status = cmd.error ? cmd.error : data.error;
+        if (cmd.error)
+            return cmd.error;
+        if (data.error)
+            return data.error;
+    } while(0);
+    return status;
+}
+static void ssv6xxx_set_sdio_clk(struct sdio_func *func, u32 sdio_hz)
+{
+    struct mmc_host *host;
+    host = func->card->host;
+    if (sdio_hz < host->f_min)
+        sdio_hz = host->f_min;
+    else if (sdio_hz > host->f_max)
+        sdio_hz = host->f_max;
+    printk("%s: set sdio clk %dHz\n", __FUNCTION__, sdio_hz);
+    sdio_claim_host(func);
+    host->ios.clock = sdio_hz;
+    host->ops->set_ios(host, &host->ios);
+    mdelay(20);
+    sdio_release_host(func);
+}
+static void ssv6xxx_low_sdio_clk(struct sdio_func *func)
+{
+    ssv6xxx_set_sdio_clk(func, LOW_SPEED_SDIO_CLOCK);
+}
+static void ssv6xxx_high_sdio_clk(struct sdio_func *func)
+{
+#ifndef SDIO_USE_SLOW_CLOCK
+    ssv6xxx_set_sdio_clk(func, HIGH_SPEED_SDIO_CLOCK);
+#endif
+}
+static void ssv6xxx_sdio_reset(struct device *child)
+{
+    struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+    struct sdio_func *func = dev_to_sdio_func(glue->dev);
+    if (IS_GLUE_INVALID(glue))
+        return;
+    HWIF_DBG_PRINT(glue->p_wlan_data, "%s\n", __FUNCTION__);
+    ssv6xxx_do_sdio_reset_reinit(glue->p_wlan_data, func, glue);
+}
+static int ssv6xxx_sdio_property(struct device *child)
+{
+    return SSV_HWIF_CAPABILITY_INTERRUPT | SSV_HWIF_INTERFACE_SDIO;
+}
+static void ssv6xxx_sdio_sysplf_reset(struct device *child, u32 addr, u32 value)
+{
+    int retval = 0;
+    retval = ssv6xxx_sdio_write_reg(child, addr, value);
+    if (retval)
+        printk("Fail to reset sysplf.\n");
+}
+static struct ssv6xxx_hwif_ops sdio_ops = {
+    .read = ssv6xxx_sdio_read,
+    .write = ssv6xxx_sdio_write,
+    .readreg = ssv6xxx_sdio_read_reg,
+    .writereg = ssv6xxx_sdio_write_reg,
+    .safe_readreg = ssv6xxx_sdio_safe_read_reg,
+    .safe_writereg = ssv6xxx_sdio_safe_write_reg,
+    .burst_readreg = ssv6xxx_sdio_burst_read_reg,
+    .burst_writereg = ssv6xxx_sdio_burst_write_reg,
+    .burst_safe_readreg = ssv6xxx_sdio_burst_safe_read_reg,
+    .burst_safe_writereg = ssv6xxx_sdio_burst_safe_write_reg,
+#ifdef ENABLE_WAKE_IO_ISR_WHEN_HCI_ENQUEUE
+    .trigger_tx_rx = ssv6xxx_sdio_trigger_tx_rx,
+#endif
+    .irq_getmask = ssv6xxx_sdio_irq_getmask,
+    .irq_setmask = ssv6xxx_sdio_irq_setmask,
+    .irq_enable = ssv6xxx_sdio_irq_enable,
+    .irq_disable = ssv6xxx_sdio_irq_disable,
+    .irq_getstatus = ssv6xxx_sdio_irq_getstatus,
+    .irq_request = ssv6xxx_sdio_irq_request,
+    .irq_trigger = ssv6xxx_sdio_irq_trigger,
+    .pmu_wakeup = ssv6xxx_sdio_pmu_wakeup,
+    .load_fw = ssv6xxx_sdio_load_firmware,
+    .load_fw_pre_config_device = ssv6xxx_sdio_load_fw_pre_config_hwif,
+    .load_fw_post_config_device = ssv6xxx_sdio_load_fw_post_config_hwif,
+    .cmd52_read = ssv6xxx_sdio_cmd52_read,
+    .cmd52_write = ssv6xxx_sdio_cmd52_write,
+    .support_scatter = ssv6xxx_sdio_support_scatter,
+    .rw_scatter = ssv6xxx_sdio_rw_scatter,
+    .is_ready = ssv6xxx_is_ready,
+    .write_sram = ssv6xxx_sdio_write_sram,
+    .interface_reset = ssv6xxx_sdio_reset,
+    .property = ssv6xxx_sdio_property,
+    .sysplf_reset = ssv6xxx_sdio_sysplf_reset,
+};
+#ifdef CONFIG_PCIEASPM
+#include <linux/pci.h>
+#include <linux/pci-aspm.h>
+static int cabrio_sdio_pm_check(struct sdio_func *func)
+{
+    struct pci_dev *pci_dev = NULL;
+    struct mmc_card *card = func->card;
+    struct mmc_host *host = card->host;
+    if (strcmp(host->parent->bus->name, "pci")) {
+        dev_info(&func->dev, "SDIO host is not PCI device, but \"%s\".", host->parent->bus->name);
+        return 0;
+    }
+    for_each_pci_dev(pci_dev) {
+        if ( ((pci_dev->class >> 8) != PCI_CLASS_SYSTEM_SDHCI)
+             && ( (pci_dev->driver == NULL)
+                  || (strcmp(pci_dev->driver->name, "sdhci-pci") != 0)))
+            continue;
+        if (pci_is_pcie(pci_dev)) {
+            u8 aspm;
+            int pos;
+            pos = pci_pcie_cap(pci_dev);
+            if (pos) {
+                struct pci_dev *parent = pci_dev->bus->self;
+                pci_read_config_byte(pci_dev, pos + PCI_EXP_LNKCTL, &aspm);
+                aspm &= ~(PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
+                pci_write_config_byte(pci_dev, pos + PCI_EXP_LNKCTL, aspm);
+                pos = pci_pcie_cap(parent);
+                pci_read_config_byte(parent, pos + PCI_EXP_LNKCTL, &aspm);
+                aspm &= ~(PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
+                pci_write_config_byte(parent, pos + PCI_EXP_LNKCTL, aspm);
+                dev_info(&pci_dev->dev, "Clear PCI-E device and its parent link state L0S and L1 and CLKPM.\n");
+            }
+        }
+    }
+    return 0;
+}
+#endif
+static int ssv6xxx_sdio_power_on(struct ssv6xxx_platform_data * pdata, struct sdio_func *func)
+{
+    int ret = 0;
+    if (pdata->is_enabled == true)
+        return 0;
+
+    sdio_claim_host(func);
+    ret = sdio_enable_func(func);
+    sdio_release_host(func);
+    if (ret) {
+        printk("Unable to enable sdio func: %d)\n", ret);
+        return ret;
+    }
+    msleep(10);
+    pdata->is_enabled = true;
+    return ret;
+}
+static int ssv6xxx_do_sdio_init_seq_5537(struct sdio_func *func)
+{
+    int status = 1;
+    struct mmc_command cmd = {0};
+    cmd.opcode = SD_IO_SEND_OP_COND;
+    cmd.arg = 0;
+    cmd.flags = MMC_RSP_SPI_R4 | MMC_RSP_R4 | MMC_CMD_BCR;
+    sdio_claim_host(func);
+    status = mmc_wait_for_cmd(func->card->host, &cmd, 0);
+    sdio_release_host(func);
+    if (status != 0) {
+        printk("%s(): The 1st CMD5 failed.", __func__);
+        return -1;
+    }
+    cmd.opcode = SD_IO_SEND_OP_COND;
+    cmd.arg = MMC_VDD_30_31|MMC_VDD_31_32|MMC_VDD_32_33|MMC_VDD_33_34|MMC_VDD_34_35;
+    cmd.flags = MMC_RSP_SPI_R4 | MMC_RSP_R4 | MMC_CMD_BCR;
+    sdio_claim_host(func);
+    status = mmc_wait_for_cmd(func->card->host, &cmd, 0);
+    sdio_release_host(func);
+    if (status != 0) {
+        printk("%s(): The 2nd CMD5 failed.", __func__);
+        return -1;
+    }
+    cmd.opcode = SD_SEND_RELATIVE_ADDR;
+    cmd.arg = 0;
+    cmd.flags = MMC_RSP_R6 | MMC_CMD_BCR;
+    sdio_claim_host(func);
+    status = mmc_wait_for_cmd(func->card->host, &cmd, 0);
+    sdio_release_host(func);
+    if (status == 0) {
+        func->card->rca = cmd.resp[0] >> 16;
+    } else {
+        printk("%s(): CMD3 failed.", __func__);
+        return -1;
+    }
+    cmd.opcode = MMC_SELECT_CARD;
+    cmd.arg = func->card->rca << 16;
+    cmd.flags = MMC_RSP_R1 | MMC_CMD_AC;
+    sdio_claim_host(func);
+    status = mmc_wait_for_cmd(func->card->host, &cmd, 0);
+    sdio_release_host(func);
+    if (status != 0) {
+        printk("%s(): CMD7 failed.", __func__);
+        return -1;
+    }
+    return 0;
+}
+static void ssv6xxx_do_sdio_reset_reinit(struct ssv6xxx_platform_data *pwlan_data,
+        struct sdio_func *func, struct ssv6xxx_sdio_glue *glue)
+{
+    int err_ret;
+    struct mmc_host *host;
+    if (IS_GLUE_INVALID(glue)) {
+        printk("%s(): glue is invalid.\n", __func__);
+        return;
+    }
+    sdio_claim_host(func);
+    sdio_f0_writeb(func, 0x08, SDIO_CCCR_ABORT, &err_ret);
+    sdio_release_host(func);
+    CHECK_IO_RET(glue, err_ret);
+    err_ret = ssv6xxx_do_sdio_init_seq_5537(func);
+    CHECK_IO_RET(glue, err_ret);
+    sdio_claim_host(func);
+    host = func->card->host;
+    host->ios.bus_width = MMC_BUS_WIDTH_4;
+    host->ops->set_ios(host, &host->ios);
+    mdelay(20);
+    sdio_release_host(func);
+    sdio_claim_host(func);
+    sdio_f0_writeb(func, SDIO_BUS_WIDTH_4BIT, SDIO_CCCR_IF, &err_ret);
+    sdio_release_host(func);
+    CHECK_IO_RET(glue, err_ret);
+    ssv6xxx_sdio_power_on(pwlan_data, func);
+    ssv6xxx_sdio_read_parameter(func, glue);
+}
+static void ssv6xxx_sdio_direct_int_mux_mode(struct ssv6xxx_sdio_glue *glue, bool enable)
+{
+    int err_ret = (-1);
+    struct sdio_func *func;
+    u8 host_cfg;
+    if (IS_GLUE_INVALID(glue))
+        return;
+    if (glue != NULL) {
+        func = dev_to_sdio_func(glue->dev);
+        sdio_claim_host(func);
+        host_cfg = sdio_readb(func, MCU_NOTIFY_HOST_CFG, &err_ret);
+        if (err_ret == 0) {
+            if (!enable) {
+                host_cfg &= ~(0x04);
+                sdio_writeb(func, host_cfg, MCU_NOTIFY_HOST_CFG, &err_ret);
+            } else {
+                host_cfg |= (0x04);
+                sdio_writeb(func, host_cfg, MCU_NOTIFY_HOST_CFG, &err_ret);
+            }
+        }
+        sdio_release_host(func);
+        CHECK_IO_RET(glue, err_ret);
+    }
+}
+static int ssv6xxx_sdio_power_off(struct ssv6xxx_platform_data * pdata, struct sdio_func *func)
+{
+    int ret;
+    if (pdata->is_enabled == false)
+        return 0;
+    printk("ssv6xxx_sdio_power_off\n");
+    sdio_claim_host(func);
+    ret = sdio_disable_func(func);
+    sdio_release_host(func);
+    if (ret)
+        return ret;
+    pdata->is_enabled = false;
+    return ret;
+}
+static void _read_chip_id (struct ssv6xxx_sdio_glue *glue)
+{
+    u32 regval;
+    int ret;
+    u8 _chip_id[SSV6XXX_CHIP_ID_LENGTH];
+    u8 *c = _chip_id;
+    int i = 0;
+    ret = __ssv6xxx_sdio_read_reg(glue, ADR_CHIP_ID_3, &regval);
+    *((u32 *)&_chip_id[0]) = __be32_to_cpu(regval);
+    if (ret == 0)
+        ret = __ssv6xxx_sdio_read_reg(glue, ADR_CHIP_ID_2, &regval);
+    *((u32 *)&_chip_id[4]) = __be32_to_cpu(regval);
+    if (ret == 0)
+        ret = __ssv6xxx_sdio_read_reg(glue, ADR_CHIP_ID_1, &regval);
+    *((u32 *)&_chip_id[8]) = __be32_to_cpu(regval);
+    if (ret == 0)
+        ret = __ssv6xxx_sdio_read_reg(glue, ADR_CHIP_ID_0, &regval);
+    *((u32 *)&_chip_id[12]) = __be32_to_cpu(regval);
+    _chip_id[12+sizeof(u32)] = 0;
+    while (*c == 0) {
+        i++;
+        c++;
+        if (i == 16) {
+            c = _chip_id;
+            break;
+        }
+    }
+    if (*c != 0) {
+        strncpy(glue->tmp_data.chip_id, c, SSV6XXX_CHIP_ID_LENGTH);
+        dev_info(glue->dev, "CHIP ID: %s \n", glue->tmp_data.chip_id);
+        strncpy(glue->tmp_data.short_chip_id, c, SSV6XXX_CHIP_ID_SHORT_LENGTH);
+        glue->tmp_data.short_chip_id[SSV6XXX_CHIP_ID_SHORT_LENGTH] = 0;
+    } else {
+        dev_err(glue->dev, "Failed to read chip ID");
+        glue->tmp_data.chip_id[0] = 0;
+    }
+    if ( strstr(glue->tmp_data.chip_id, SSV6051_CHIP)
+         || strstr(glue->tmp_data.chip_id, SSV6051_CHIP_ECO3)) {
+        struct ssv6xxx_platform_data *pwlan_data;
+        pwlan_data = &glue->tmp_data;
+        pwlan_data->ops->safe_readreg = ssv6xxx_sdio_read_reg;
+        pwlan_data->ops->safe_writereg = ssv6xxx_sdio_write_reg;
+        printk("SWAP ops for 6051\n");
+    }
+}
+#if (defined(CONFIG_SSV_SDIO_INPUT_DELAY) && defined(CONFIG_SSV_SDIO_OUTPUT_DELAY))
+static void ssv6xxx_sdio_delay_chain(struct sdio_func *func, u32 input_delay, u32 output_delay)
+{
+    u8 in_delay, out_delay;
+    u8 delay[4];
+    int ret = 0, i = 0;
+    if ((input_delay == 0) && (output_delay == 0))
+        return;
+    for (i = 0; i < 4; i++) {
+        delay[i] = 0;
+        in_delay = (input_delay >> ( i * 8 )) & 0xff;
+        out_delay = (output_delay >> ( i * 8 )) & 0xff;
+        if (in_delay == SDIO_DELAY_LEVEL_OFF)
+            delay[i] |= (1 << SDIO_INPUT_DELAY_SFT);
+        else
+            delay[i] |= ((in_delay-1) << SDIO_INPUT_DELAY_LEVEL_SFT);
+        if (out_delay == SDIO_DELAY_LEVEL_OFF)
+            delay[i] |= (1 << SDIO_OUTPUT_DELAY_SFT);
+        else
+            delay[i] |= ((out_delay-1) << SDIO_OUTPUT_DELAY_LEVEL_SFT);
+    }
+    printk("%s: delay chain data0[%02x], data1[%02x], data2[%02x], data3[%02x]\n",
+           __FUNCTION__, delay[0], delay[1], delay[2], delay[3]);
+    sdio_claim_host(func);
+    sdio_writeb(func, delay[0], REG_SDIO_DAT0_DELAY, &ret);
+    sdio_writeb(func, delay[1], REG_SDIO_DAT1_DELAY, &ret);
+    sdio_writeb(func, delay[2], REG_SDIO_DAT2_DELAY, &ret);
+    sdio_writeb(func, delay[3], REG_SDIO_DAT3_DELAY, &ret);
+    sdio_release_host(func);
+}
+#endif
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0)
+int __devinit tu_ssv6xxx_sdio_probe(struct sdio_func *func,
+                                    const struct sdio_device_id *id)
+#else
+int tu_ssv6xxx_sdio_probe(struct sdio_func *func,
+                          const struct sdio_device_id *id)
+#endif
+{
+    struct ssv6xxx_platform_data *pwlan_data;
+    struct ssv6xxx_sdio_glue *glue;
+    int ret = -ENOMEM;
+    dev_info(&func->dev, "Probing SDIO bus");
+    if (func->num != 0x01)
+        return -ENODEV;
+    glue = kzalloc(sizeof(*glue), GFP_KERNEL);
+    if (!glue) {
+        dev_err(&func->dev, "can't allocate glue");
+        goto out;
+    }
+#if (defined(CONFIG_SSV_SDIO_INPUT_DELAY) && defined(CONFIG_SSV_SDIO_OUTPUT_DELAY))
+    ssv6xxx_sdio_delay_chain(func, CONFIG_SSV_SDIO_INPUT_DELAY, CONFIG_SSV_SDIO_OUTPUT_DELAY);
+#endif
+    ssv6xxx_low_sdio_clk(func);
+#ifdef CONFIG_FW_ALIGNMENT_CHECK
+    glue->dmaSkb=__dev_alloc_skb(SDIO_DMA_BUFFER_LEN, GFP_KERNEL);
+#endif
+    pwlan_data = &glue->tmp_data;
+    memset(pwlan_data, 0, sizeof(struct ssv6xxx_platform_data));
+    atomic_set(&pwlan_data->irq_handling, 0);
+    glue->dev = &func->dev;
+    func->card->quirks |= MMC_QUIRK_LENIENT_FN0;
+    func->card->quirks |= MMC_QUIRK_BLKSZ_FOR_BYTE_MODE;
+    glue->dev_ready = true;
+    pwlan_data->vendor = func->vendor;
+    pwlan_data->device = func->device;
+    dev_info(glue->dev, "vendor = 0x%x device = 0x%x",
+            pwlan_data->vendor, pwlan_data->device);
+#ifdef CONFIG_PCIEASPM
+    cabrio_sdio_pm_check(func);
+#endif
+    pwlan_data->ops = &sdio_ops;
+    sdio_set_drvdata(func, glue);
+#ifdef CONFIG_PM
+    ssv6xxx_do_sdio_wakeup(func);
+#endif
+    ssv6xxx_sdio_power_on(pwlan_data, func);
+    ssv6xxx_sdio_read_parameter(func, glue);
+    ssv6xxx_do_sdio_reset_reinit(pwlan_data, func, glue);
+    ssv6xxx_sdio_direct_int_mux_mode(glue, false);
+    _read_chip_id(glue);
+    glue->core = platform_device_alloc(pwlan_data->short_chip_id, -1);
+    if (!glue->core) {
+        dev_err(glue->dev, "can't allocate platform_device");
+        ret = -ENOMEM;
+        goto out_free_glue;
+    }
+    glue->core->dev.parent = &func->dev;
+    ret = platform_device_add_data(glue->core, pwlan_data,
+                                   sizeof(*pwlan_data));
+    if (ret) {
+        dev_err(glue->dev, "can't add platform data\n");
+        goto out_dev_put;
+    }
+    glue->p_wlan_data = glue->core->dev.platform_data;
+    ret = platform_device_add(glue->core);
+    if (ret) {
+        dev_err(glue->dev, "can't add platform device\n");
+        goto out_dev_put;
+    }
+    ssv6xxx_sdio_irq_setmask(&glue->core->dev,0xff);
+#if 0
+    ssv6xxx_sdio_irq_enable(&glue->core->dev);
+#else
+#endif
+#if 0
+    glue->dev->platform_data = (void *)pwlan_data;
+    ret = tu_ssv6xxx_dev_probe(glue->dev);
+    if (ret) {
+        dev_err(glue->dev, "failed to initial ssv6xxx device !!\n");
+        platform_device_del(glue->core);
+        goto out_dev_put;
+    }
+#endif
+    return 0;
+out_dev_put:
+    platform_device_put(glue->core);
+out_free_glue:
+    if (glue != NULL)
+        kfree(glue);
+out:
+    return ret;
+}
+EXPORT_SYMBOL(tu_ssv6xxx_sdio_probe);
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0)
+void __devexit tu_ssv6xxx_sdio_remove(struct sdio_func *func)
+#else
+void tu_ssv6xxx_sdio_remove(struct sdio_func *func)
+#endif
+{
+    struct ssv6xxx_sdio_glue *glue = sdio_get_drvdata(func);
+    printk("tu_ssv6xxx_sdio_remove..........\n");
+    if ( glue ) {
+        printk("tu_ssv6xxx_sdio_remove - ssv6xxx_sdio_irq_disable\n");
+        ssv6xxx_sdio_irq_disable(&glue->core->dev,false);
+        glue->dev_ready = false;
+#if 0
+        tu_ssv6xxx_dev_remove(glue->dev);
+#endif
+        ssv6xxx_low_sdio_clk(func);
+#ifdef CONFIG_FW_ALIGNMENT_CHECK
+        if(glue->dmaSkb != NULL)
+            dev_kfree_skb(glue->dmaSkb);
+#endif
+        printk("tu_ssv6xxx_sdio_remove - disable mask\n");
+        ssv6xxx_sdio_irq_setmask(&glue->core->dev,0xff);
+        ssv6xxx_sdio_power_off(glue->p_wlan_data, func);
+        printk("platform_device_del \n");
+        platform_device_del(glue->core);
+        printk("platform_device_put \n");
+        platform_device_put(glue->core);
+        kfree(glue);
+    }
+    sdio_set_drvdata(func, NULL);
+    printk("tu_ssv6xxx_sdio_remove leave..........\n");
+}
+EXPORT_SYMBOL(tu_ssv6xxx_sdio_remove);
+
+#ifdef CONFIG_PM
+int tu_ssv6xxx_sdio_suspend(struct device *dev)
+{
+    struct sdio_func *func = dev_to_sdio_func(dev);
+    struct ssv6xxx_sdio_glue *glue = sdio_get_drvdata(func);
+    mmc_pm_flag_t flags = sdio_get_host_pm_caps(func);
+    int ret = 0;
+    dev_info(dev, "%s: suspend: PM flags = 0x%x\n",
+             sdio_func_id(func), flags);
+    ssv6xxx_low_sdio_clk(func);
+    glue->p_wlan_data->suspend(glue->p_wlan_data->pm_param);
+    if (!(flags & MMC_PM_KEEP_POWER)) {
+        dev_err(dev, "%s: cannot remain alive while host is suspended\n",
+                sdio_func_id(func));
+    }
+    ret = sdio_set_host_pm_flags(func, MMC_PM_KEEP_POWER);
+    if (ret)
+        return ret;
+#if 0
+    if (softc->wow_enabled) {
+        sdio_flags = sdio_get_host_pm_caps(func);
+        if (!(sdio_flags & MMC_PM_KEEP_POWER)) {
+            dev_err(dev, "can't keep power while host "
+                    "is suspended\n");
+            ret = -EINVAL;
+            goto out;
+        }
+        ret = sdio_set_host_pm_flags(func, MMC_PM_KEEP_POWER);
+        if (ret) {
+            dev_err(dev, "error while trying to keep power\n");
+            goto out;
+        }
+    } else {
+        ssv6xxx_sdio_irq_disable(&glue->core->dev,true);
+    }
+#endif
+    return ret;
+}
+EXPORT_SYMBOL(tu_ssv6xxx_sdio_suspend);
+
+int tu_ssv6xxx_sdio_resume(struct device *dev)
+{
+    struct sdio_func *func = dev_to_sdio_func(dev);
+    struct ssv6xxx_sdio_glue *glue = sdio_get_drvdata(func);
+    dev_info(dev, "%s: resume.\n", __FUNCTION__);
+    if (!glue)
+        return 0;
+    glue->p_wlan_data->resume(glue->p_wlan_data->pm_param);
+    return 0;
+}
+EXPORT_SYMBOL(tu_ssv6xxx_sdio_resume);
+
+static const struct dev_pm_ops ssv6xxx_sdio_pm_ops = {
+    .suspend = tu_ssv6xxx_sdio_suspend,
+    .resume = tu_ssv6xxx_sdio_resume,
+};
+#endif
+struct sdio_driver tu_ssv6xxx_sdio_driver = {
+    .name = "TU_SSV6XXX_SDIO",
+    .id_table = ssv6xxx_sdio_devices,
+    .probe = tu_ssv6xxx_sdio_probe,
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0)
+    .remove = __devexit_p(tu_ssv6xxx_sdio_remove),
+#else
+    .remove = tu_ssv6xxx_sdio_remove,
+#endif
+#ifdef CONFIG_PM
+    .drv = {
+        .pm = &ssv6xxx_sdio_pm_ops,
+    },
+#endif
+};
+EXPORT_SYMBOL(tu_ssv6xxx_sdio_driver);
+#if (defined(CONFIG_SSV_SUPPORT_ANDROID)||defined(CONFIG_SSV_BUILD_AS_ONE_KO))
+int tu_ssv6xxx_sdio_init(void)
+#else
+static int __init tu_ssv6xxx_sdio_init(void)
+#endif
+{
+    printk(KERN_INFO "tu_ssv6xxx_sdio_init, probe @%p\n", tu_ssv6xxx_sdio_driver.probe);
+    return sdio_register_driver(&tu_ssv6xxx_sdio_driver);
+}
+#if (defined(CONFIG_SSV_SUPPORT_ANDROID)||defined(CONFIG_SSV_BUILD_AS_ONE_KO))
+void tu_ssv6xxx_sdio_exit(void)
+#else
+static void __exit tu_ssv6xxx_sdio_exit(void)
+#endif
+{
+    printk(KERN_INFO "tu_ssv6xxx_sdio_exit\n");
+    sdio_unregister_driver(&tu_ssv6xxx_sdio_driver);
+}
+#if (defined(CONFIG_SSV_SUPPORT_ANDROID)||defined(CONFIG_SSV_BUILD_AS_ONE_KO))
+EXPORT_SYMBOL(tu_ssv6xxx_sdio_init);
+EXPORT_SYMBOL(tu_ssv6xxx_sdio_exit);
+#else
+module_init(tu_ssv6xxx_sdio_init);
+module_exit(tu_ssv6xxx_sdio_exit);
+#endif
+MODULE_LICENSE("GPL");
diff --git a/drivers/net/wireless/ssv6x5x/hwif/sdio/sdio.h b/drivers/net/wireless/ssv6x5x/hwif/sdio/sdio.h
new file mode 100644
index 000000000..907c6ace1
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/hwif/sdio/sdio.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SDIO_H_
+#define _SDIO_H_
+int tu_ssv6xxx_sdio_init(void);
+void tu_ssv6xxx_sdio_exit(void);
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/hwif/sdio/sdio_def.h b/drivers/net/wireless/ssv6x5x/hwif/sdio/sdio_def.h
new file mode 100644
index 000000000..ade196765
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/hwif/sdio/sdio_def.h
@@ -0,0 +1,125 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SDIO_DEF_H_
+#define _SDIO_DEF_H_
+#include <linux/scatterlist.h>
+#define BASE_SDIO 0
+#define SD_REG_BASE 0xc0000800
+#define REG_DATA_IO_PORT_0 (BASE_SDIO + 0x00)
+#define REG_DATA_IO_PORT_1 (BASE_SDIO + 0x01)
+#define REG_DATA_IO_PORT_2 (BASE_SDIO + 0x02)
+#define REG_INT_MASK (BASE_SDIO + 0x04)
+#define REG_INT_STATUS (BASE_SDIO + 0x08)
+#define REG_INT_TRIGGER (BASE_SDIO + 0x09)
+#define REG_Fn1_STATUS (BASE_SDIO + 0x0c)
+#define REG_SD_READY_FLAG (BASE_SDIO + 0x0f)
+#define REG_CARD_PKT_LEN_0 (BASE_SDIO + 0x10)
+#define REG_CARD_PKT_LEN_1 (BASE_SDIO + 0x11)
+#define REG_CARD_FW_DL_STATUS (BASE_SDIO + 0x12)
+#define REG_CARD_SELF_TEST (BASE_SDIO + 0x13)
+#define REG_CARD_RCA_0 (BASE_SDIO + 0x20)
+#define REG_CARD_RCA_1 (BASE_SDIO + 0x21)
+#define REG_SDIO_FIFO_WR_THLD_0 (BASE_SDIO + 0x24)
+#define REG_SDIO_FIFO_WR_THLD_1 (BASE_SDIO + 0x25)
+#define REG_OUTPUT_TIMING_REG (BASE_SDIO + 0x55)
+#define MCU_NOTIFY_HOST_CFG (BASE_SDIO + 0x56)
+#define REG_SDIO_DAT3_DELAY (BASE_SDIO + 0x59)
+#define REG_SDIO_DAT2_DELAY (BASE_SDIO + 0x5a)
+#define REG_SDIO_DAT1_DELAY (BASE_SDIO + 0x5b)
+#define REG_SDIO_DAT0_DELAY (BASE_SDIO + 0x5c)
+#define REG_PMU_WAKEUP (BASE_SDIO + 0x67)
+#define REG_REG_IO_PORT_0 (BASE_SDIO + 0x70)
+#define REG_REG_IO_PORT_1 (BASE_SDIO + 0x71)
+#define REG_REG_IO_PORT_2 (BASE_SDIO + 0x72)
+#define REG_SDIO_TX_ALLOC_SIZE (BASE_SDIO + 0x98)
+#define REG_SDIO_TX_ALLOC_SHIFT (BASE_SDIO + 0x99)
+#define REG_SDIO_TX_ALLOC_STATE (BASE_SDIO + 0x9a)
+#define REG_SDIO_TX_INFORM_0 (BASE_SDIO + 0x9c)
+#define REG_SDIO_TX_INFORM_1 (BASE_SDIO + 0x9d)
+#define REG_SDIO_TX_INFORM_2 (BASE_SDIO + 0x9e)
+#if 0
+#define SDIO_TX_ALLOC_SUCCESS 0x01
+#define SDIO_TX_NO_ALLOC 0x02
+#define SDIO_TX_DULPICATE_ALLOC 0x04
+#define SDIO_TX_TX_DONE 0x08
+#define SDIO_TX_AHB_HANG 0x10
+#define SDIO_TX_MB_FULL 0x80
+#define SDIO_HCI_IN_QUEUE_EMPTY 0x04
+#define SDIO_EDCA0_SHIFT 4
+#define SDIO_TX_ALLOC_SIZE_SHIFT 0x07
+#define SDIO_TX_ALLOC_ENABLE 0x10
+#endif
+#define SDIO_DEF_BLOCK_SIZE 0x80
+#if (SDIO_DEF_BLOCK_SIZE % 8)
+#error Wrong SDIO_DEF_BLOCK_SIZE value!! Should be the multiple of 8 bytes!!!!!!!!!!!!!!!!!!!!!!
+#endif
+#define SDIO_DEF_OUTPUT_TIMING 0
+#define SDIO_DEF_BLOCK_MODE_THRD 128
+#if (SDIO_DEF_BLOCK_MODE_THRD % 8)
+#error Wrong SDIO_DEF_BLOCK_MODE_THRD value!! Should be the multiple of 8 bytes!!!!!!!!!!!!!!!!!!!!!!
+#endif
+#define SDIO_DEF_FORCE_BLOCK_MODE 0
+#define MAX_SCATTER_ENTRIES_PER_REQ 8
+struct sdio_scatter_item {
+    u8 *buf;
+    int len;
+};
+struct sdio_scatter_req {
+    u32 req;
+    u32 len;
+    int scat_entries;
+    struct sdio_scatter_item scat_list[MAX_SCATTER_ENTRIES_PER_REQ];
+    struct scatterlist sgentries[MAX_SCATTER_ENTRIES_PER_REQ];
+};
+#define SDIO_READ 0x00000001
+#define SDIO_WRITE 0x00000002
+#define CMD53_ARG_READ 0
+#define CMD53_ARG_WRITE 1
+#define CMD53_ARG_BLOCK_BASIS 1
+#define CMD53_ARG_FIXED_ADDRESS 0
+#define CMD53_ARG_INCR_ADDRESS  1
+
+
+#if defined(CONFIG_FW_ALIGNMENT_CHECK)
+#define SDIO_DMA_BUFFER_LEN			2048
+#endif
+#ifdef CONFIG_PM
+#define SDIO_COMMAND_BUFFER_LEN 256
+#endif
+#define IO_REG_BURST_RD_PORT_REG 0x10080
+#define IO_REG_BURST_WR_PORT_REG 0x10040
+#define MAX_BURST_READ_REG_AMOUNT 2
+#define MAX_BURST_WRITE_REG_AMOUNT 2
+#define SDIO_INPUT_DELAY_MSK 0x04
+#define SDIO_INPUT_DELAY_SFT 2
+#define SDIO_INPUT_DELAY_LEVEL_MSK 0x03
+#define SDIO_INPUT_DELAY_LEVEL_SFT 0
+#define SDIO_OUTPUT_DELAY_MSK 0x40
+#define SDIO_OUTPUT_DELAY_SFT 6
+#define SDIO_OUTPUT_DELAY_LEVEL_MSK 0x30
+#define SDIO_OUTPUT_DELAY_LEVEL_SFT 4
+#define SDIO_DELAY_LEVEL_OFF 0
+#define SDIO_DELAY_LEVEL_0 1
+#define SDIO_DELAY_LEVEL_1 2
+#define SDIO_DELAY_LEVEL_2 3
+#define SDIO_DELAY_LEVEL_3 4
+#define SDIO_READY_FLAG_BUSY 0x0
+#define SDIO_READY_FLAG_IDLE 0x2
+#define SDIO_READY_FLAG_BUSY_THRESHOLD 10000
+#define SDIO_READY_FLAG_BUSY_DELAY 5
+#define PLATFORM_DEF_DMA_ALIGN_SIZE 32
+#define PLATFORM_DMA_ALIGNED __attribute__ ((aligned(PLATFORM_DEF_DMA_ALIGN_SIZE)))
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/hwif/usb/Makefile b/drivers/net/wireless/ssv6x5x/hwif/usb/Makefile
new file mode 100755
index 000000000..36a3019c8
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/hwif/usb/Makefile
@@ -0,0 +1,21 @@
+ifeq ($(KBUILD_TOP),)
+    ifneq ($(KBUILD_EXTMOD),)
+    KBUILD_DIR := $(KBUILD_EXTMOD)
+    else
+    KBUILD_DIR := $(PWD)
+    endif
+KBUILD_TOP := $(KBUILD_DIR)/../../
+endif
+
+include $(KBUILD_TOP)/config.mak
+
+KBUILD_EXTRA_SYMBOLS += $(KBUILD_TOP)/ssv6200smac/Module.symvers
+ifeq ($(DRV_OPT), HUW_DRV)
+KBUILD_EXTRA_SYMBOLS += $(KBUILD_TOP)/hci_wrapper/Module.symvers
+endif
+KBUILD_EXTRA_SYMBOLS += $(KBUILD_TOP)/ssvdevice/Module.symvers
+
+KMODULE_NAME=ssv6200_usb
+KERN_SRCS := usb.c
+
+include $(KBUILD_TOP)/rules.mak
diff --git a/drivers/net/wireless/ssv6x5x/hwif/usb/usb.c b/drivers/net/wireless/ssv6x5x/hwif/usb/usb.c
new file mode 100644
index 000000000..d61118d0b
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/hwif/usb/usb.c
@@ -0,0 +1,926 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/kref.h>
+#include <linux/uaccess.h>
+#include <linux/usb.h>
+#include <linux/mutex.h>
+#include <linux/platform_device.h>
+#include <linux/version.h>
+#include <linux/skbuff.h>
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0)
+#include <linux/printk.h>
+#else
+#include <linux/kernel.h>
+#endif
+#include <ssv6200.h>
+#include <hwif/hwif.h>
+#include "usb.h"
+#include <ssv_data_struct.h>
+#define USB_SSV_VENDOR_ID 0x8065
+#define USB_SSV_PRODUCT_ID 0x6000
+#define TRANSACTION_TIMEOUT (3000)
+#define SSV6XXX_MAX_TXCMDSZ (sizeof(struct ssv6xxx_cmd_hdr))
+#define SSV6XXX_MAX_RXCMDSZ (sizeof(struct ssv6xxx_cmd_hdr))
+#define SSV6XXX_CMD_HEADER_SIZE (sizeof(struct ssv6xxx_cmd_hdr) - sizeof(union ssv6xxx_payload))
+#define USB_CMD_SEQUENCE 255
+#define MAX_RETRY_SSV6XXX_ALLOC_BUF 3
+#define IS_GLUE_INVALID(glue) \
+      ( (glue == NULL) \
+       || (glue->dev_ready == false) \
+       || ( (glue->p_wlan_data != NULL) \
+           && (glue->p_wlan_data->is_enabled == false)) \
+      )
+static const struct usb_device_id ssv_usb_table[] = {
+    { USB_DEVICE(USB_SSV_VENDOR_ID, USB_SSV_PRODUCT_ID) },
+    { }
+};
+MODULE_DEVICE_TABLE(usb, ssv_usb_table);
+extern int ssv_rx_nr_recvbuff;
+extern int ssv_rx_use_wq;
+struct ssv6xxx_usb_glue {
+    struct device *dev;
+    struct platform_device *core;
+    struct usb_device *udev;
+    struct usb_interface *interface;
+    struct ssv6xxx_platform_data *p_wlan_data;
+    struct ssv6xxx_platform_data tmp_data;
+    struct ssv6xxx_cmd_endpoint cmd_endpoint;
+    struct ssv6xxx_cmd_endpoint rsp_endpoint;
+    struct ssv6xxx_tx_endpoint tx_endpoint;
+    struct ssv6xxx_rx_endpoint rx_endpoint;
+    struct ssv6xxx_rx_buf ssv_rx_buf[MAX_NR_RECVBUFF];
+    struct ssv6xxx_queue ssv_rx_queue;
+    struct kref kref;
+    struct mutex io_mutex;
+    struct mutex cmd_mutex;
+    u16 sequence;
+    u16 err_cnt;
+    bool dev_ready;
+    struct workqueue_struct *wq;
+    struct ssv6xxx_usb_work_struct rx_work;
+    struct tasklet_struct rx_tasklet;
+    u32 *rx_pkt;
+    void *rx_cb_args;
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+    int (*rx_cb)(struct sk_buff_head *rxq, void *args);
+#else
+    int (*rx_cb)(struct sk_buff *rx_skb, void *args);
+#endif
+    int (*is_rx_q_full)(void *);
+};
+static void ssv6xxx_usb_recv_rx(struct ssv6xxx_usb_glue *glue, struct ssv6xxx_rx_buf *ssv_rx_buf);
+#define to_ssv6xxx_usb_dev(d) container_of(d, struct ssv6xxx_usb_glue, kref)
+static struct usb_driver ssv_usb_driver;
+#if 0
+static void ssv6xxx_dump_tx_desc(const u8 *buf)
+{
+    struct ssv6200_tx_desc *tx_desc;
+    tx_desc = (struct ssv6200_tx_desc *)buf;
+    printk(">> Tx Frame:\n");
+    printk("length: %d, c_type=%d, f80211=%d, qos=%d, ht=%d, use_4addr=%d, sec=%d\n",
+           tx_desc->len, tx_desc->c_type, tx_desc->f80211, tx_desc->qos, tx_desc->ht,
+           tx_desc->use_4addr, tx_desc->security);
+    printk("more_data=%d, sub_type=%x, extra_info=%d\n", tx_desc->more_data,
+           tx_desc->stype_b5b4, tx_desc->extra_info);
+    printk("fcmd=0x%08x, hdr_offset=%d, frag=%d, unicast=%d, hdr_len=%d\n",
+           tx_desc->fCmd, tx_desc->hdr_offset, tx_desc->frag, tx_desc->unicast,
+           tx_desc->hdr_len);
+    printk("tx_burst=%d, ack_policy=%d, do_rts_cts=%d, reason=%d, payload_offset=%d\n",
+           tx_desc->tx_burst, tx_desc->ack_policy, tx_desc->do_rts_cts,
+           tx_desc->reason, tx_desc->payload_offset);
+    printk("fcmdidx=%d, wsid=%d, txq_idx=%d\n",
+           tx_desc->fCmdIdx, tx_desc->wsid, tx_desc->txq_idx);
+    printk("RTS/CTS Nav=%d, frame_time=%d, crate_idx=%d, drate_idx=%d, dl_len=%d\n",
+           tx_desc->rts_cts_nav, tx_desc->frame_consume_time, tx_desc->crate_idx, tx_desc->drate_idx,
+           tx_desc->dl_length);
+    printk("\n\n\n");
+}
+#endif
+#if 0
+static void ssv6xxx_dump_rx_desc(const u8 *buf)
+{
+    struct ssv6200_rx_desc *rx_desc;
+    rx_desc = (struct ssv6200_rx_desc *)buf;
+    printk(">> RX Descriptor:\n");
+    printk("len=%d, c_type=%d, f80211=%d, qos=%d, ht=%d, use_4addr=%d, l3cs_err=%d, l4_cs_err=%d\n",
+           rx_desc->len, rx_desc->c_type, rx_desc->f80211, rx_desc->qos, rx_desc->ht, rx_desc->use_4addr,
+           rx_desc->l3cs_err, rx_desc->l4cs_err);
+    printk("align2=%d, psm=%d, stype_b5b4=%d, extra_info=%d\n",
+           rx_desc->align2, rx_desc->psm, rx_desc->stype_b5b4, rx_desc->extra_info);
+    printk("hdr_offset=%d, reason=%d, rx_result=%d\n", rx_desc->hdr_offset,
+           rx_desc->reason, rx_desc->RxResult);
+    printk("\n\n\n");
+}
+#endif
+static u16 ssv6xxx_get_cmd_sequence(struct ssv6xxx_usb_glue *glue)
+{
+    glue->sequence = glue->sequence % USB_CMD_SEQUENCE;
+    (glue->sequence)++;
+    return glue->sequence;
+}
+static void ssv6xxx_usb_delete(struct kref *kref)
+{
+    struct ssv6xxx_usb_glue *glue = to_ssv6xxx_usb_dev(kref);
+    int i;
+    for (i = 0 ; i < MAX_NR_RECVBUFF ; ++i) {
+        usb_kill_urb(glue->ssv_rx_buf[i].rx_urb);
+    }
+    if (glue->cmd_endpoint.buff)
+        kfree(glue->cmd_endpoint.buff);
+    if (glue->rsp_endpoint.buff)
+        kfree(glue->rsp_endpoint.buff);
+    if (glue->ssv_rx_buf[0].rx_buf) {
+        for (i = 0 ; i < MAX_NR_RECVBUFF ; ++i) {
+            usb_free_coherent(glue->udev, MAX_HCI_RX_AGGR_SIZE,
+                              glue->ssv_rx_buf[i].rx_buf,
+                              glue->ssv_rx_buf[i].rx_urb->transfer_dma);
+            usb_free_urb(glue->ssv_rx_buf[i].rx_urb);
+        }
+    }
+    if (ssv_rx_use_wq) {
+        destroy_workqueue(glue->wq);
+    } else {
+        tasklet_kill(&glue->rx_tasklet);
+    }
+    usb_put_dev(glue->udev);
+    kfree(glue);
+}
+static int ssv6xxx_usb_recv_rsp(struct ssv6xxx_usb_glue *glue, int size, int *rsp_len)
+{
+    int retval = 0, foolen = 0;
+    if (!glue || !glue->interface) {
+        retval = -ENODEV;
+        return retval;
+    }
+    retval = usb_bulk_msg(glue->udev,
+                          usb_rcvbulkpipe(glue->udev, glue->rsp_endpoint.address),
+                          glue->rsp_endpoint.buff, size,
+                          &foolen, TRANSACTION_TIMEOUT);
+    if (retval) {
+        *rsp_len = 0;
+        HWIF_DBG_PRINT(glue->p_wlan_data, "Cannot receive response, error=%d\n", retval);
+    } else {
+        *rsp_len = foolen;
+        glue->err_cnt = 0;
+    }
+    return retval;
+}
+static int ssv6xxx_usb_send_cmd(struct ssv6xxx_usb_glue *glue, u8 cmd, u16 seq, const void *data, u32 data_len)
+{
+    int retval = 0, foolen = 0;
+    struct ssv6xxx_cmd_hdr *hdr;
+    if (!glue || !glue->interface) {
+        retval = -ENODEV;
+        return retval;
+    }
+    hdr = (struct ssv6xxx_cmd_hdr *)glue->cmd_endpoint.buff;
+    memset(hdr, 0, sizeof(struct ssv6xxx_cmd_hdr));
+    hdr->plen = (data_len >> (0))& 0xff;
+    hdr->cmd = cmd;
+    hdr->seq = cpu_to_le16(seq);
+    memcpy(&hdr->payload, data, data_len);
+    retval = usb_bulk_msg(glue->udev,
+                          usb_sndbulkpipe(glue->udev, glue->cmd_endpoint.address),
+                          glue->cmd_endpoint.buff, (data_len+SSV6XXX_CMD_HEADER_SIZE),
+                          &foolen, TRANSACTION_TIMEOUT);
+    if (retval) {
+        HWIF_DBG_PRINT(glue->p_wlan_data, "Cannot send cmd data, error=%d\n", retval);
+    } else {
+        glue->err_cnt = 0;
+    }
+    return retval;
+}
+static int ssv6xxx_usb_cmd(struct ssv6xxx_usb_glue *glue, u8 cmd, void *data, u32 data_len, void *result)
+{
+    int retval = (-1), rsp_len = 0, i = 0;
+    struct ssv6xxx_cmd_hdr *rsphdr;
+    u16 sequence;
+    mutex_lock(&glue->cmd_mutex);
+    sequence = ssv6xxx_get_cmd_sequence(glue);
+    retval = ssv6xxx_usb_send_cmd(glue, cmd, sequence, data, data_len);
+    if (retval) {
+        HWIF_DBG_PRINT(glue->p_wlan_data, "%s: Fail to send cmd, sequence=%d, retval=%d\n",
+                       __FUNCTION__, sequence, retval);
+        goto exit;
+    }
+    for (i = 0; i < USB_CMD_SEQUENCE; i++) {
+        retval = ssv6xxx_usb_recv_rsp(glue, SSV6XXX_MAX_RXCMDSZ, &rsp_len);
+        if (retval) {
+            HWIF_DBG_PRINT(glue->p_wlan_data, "%s: Fail to receive response, sequence=%d, retval=%d\n",
+                           __FUNCTION__, sequence, retval);
+            goto exit;
+        }
+        if (rsp_len < SSV6XXX_CMD_HEADER_SIZE) {
+            HWIF_DBG_PRINT(glue->p_wlan_data, "Receviced abnormal response length[%d]\n", rsp_len);
+            goto exit;
+        }
+        rsphdr = (struct ssv6xxx_cmd_hdr *)glue->rsp_endpoint.buff;
+        if (sequence == rsphdr->seq)
+            break;
+        else
+            HWIF_DBG_PRINT(glue->p_wlan_data, "received incorrect sequence=%d[%d]\n", sequence, rsphdr->seq);
+    }
+    switch (rsphdr->cmd) {
+    case SSV6200_CMD_WRITE_REG:
+        break;
+    case SSV6200_CMD_READ_REG:
+        if (result)
+            memcpy(result, &rsphdr->payload, sizeof(struct ssv6xxx_read_reg_result));
+        break;
+    default:
+        retval = -1;
+        HWIF_DBG_PRINT(glue->p_wlan_data, "%s: unknown response cmd[%d]\n", __FUNCTION__, rsphdr->cmd);
+        break;
+    }
+exit:
+    mutex_unlock(&glue->cmd_mutex);
+    return retval;
+}
+static void ssv6xxx_usb_recv_rx_work(struct work_struct *work)
+{
+    struct ssv6xxx_usb_glue *glue = ((struct ssv6xxx_usb_work_struct *)work)->glue;
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+    struct sk_buff_head rx_list;
+#endif
+    struct sk_buff *rx_mpdu;
+    struct ssv6xxx_rx_buf *ssv_rx_buf;
+    unsigned char *data;
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+    skb_queue_head_init(&rx_list);
+#endif
+    while (NULL != (ssv_rx_buf = (struct ssv6xxx_rx_buf *)ssv6xxx_dequeue_list_node(&glue->ssv_rx_queue))) {
+        if (glue->is_rx_q_full(glue->rx_cb_args)) {
+            ssv6xxx_enqueue_list_node((struct ssv6xxx_list_node *)ssv_rx_buf, &glue->ssv_rx_queue);
+            queue_work(glue->wq, (struct work_struct *)&glue->rx_work);
+            break;
+        }
+        (*glue->rx_pkt)++;
+        rx_mpdu = glue->p_wlan_data->skb_alloc(glue->p_wlan_data->skb_param, ssv_rx_buf->rx_filled,
+                                               GFP_KERNEL
+                                              );
+        if (rx_mpdu == NULL) {
+            ssv6xxx_enqueue_list_node((struct ssv6xxx_list_node *)ssv_rx_buf, &glue->ssv_rx_queue);
+            queue_work(glue->wq, (struct work_struct *)&glue->rx_work);
+            break;
+        }
+        data = skb_put(rx_mpdu, ssv_rx_buf->rx_filled);
+        memcpy(data, ssv_rx_buf->rx_buf, ssv_rx_buf->rx_filled);
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+        skb_queue_tail(&rx_list, rx_mpdu);
+#else
+        glue->rx_cb(rx_mpdu, glue->rx_cb_args);
+#endif
+        ssv6xxx_usb_recv_rx(glue, ssv_rx_buf);
+    }
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+    if (skb_queue_len(&rx_list)) {
+        glue->rx_cb(&rx_list, glue->rx_cb_args);
+    }
+#endif
+}
+static void ssv6xxx_usb_recv_rx_tasklet(unsigned long priv)
+{
+    struct ssv6xxx_usb_glue *glue = (struct ssv6xxx_usb_glue *)priv;
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+    struct sk_buff_head rx_list;
+#endif
+    struct sk_buff *rx_mpdu;
+    struct ssv6xxx_rx_buf *ssv_rx_buf;
+    unsigned char *data;
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+    skb_queue_head_init(&rx_list);
+#endif
+    while (NULL != (ssv_rx_buf = (struct ssv6xxx_rx_buf *)ssv6xxx_dequeue_list_node(&glue->ssv_rx_queue))) {
+        if (glue->is_rx_q_full(glue->rx_cb_args)) {
+            ssv6xxx_enqueue_list_node((struct ssv6xxx_list_node *)ssv_rx_buf, &glue->ssv_rx_queue);
+            tasklet_schedule(&glue->rx_tasklet);
+            break;
+        }
+        (*glue->rx_pkt)++;
+        rx_mpdu = glue->p_wlan_data->skb_alloc(glue->p_wlan_data->skb_param, ssv_rx_buf->rx_filled,
+                                               GFP_ATOMIC
+                                              );
+        if (rx_mpdu == NULL) {
+            ssv6xxx_enqueue_list_node((struct ssv6xxx_list_node *)ssv_rx_buf, &glue->ssv_rx_queue);
+            tasklet_schedule(&glue->rx_tasklet);
+            break;
+        }
+        data = skb_put(rx_mpdu, ssv_rx_buf->rx_filled);
+        memcpy(data, ssv_rx_buf->rx_buf, ssv_rx_buf->rx_filled);
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+        skb_queue_tail(&rx_list, rx_mpdu);
+#else
+        glue->rx_cb(rx_mpdu, glue->rx_cb_args);
+#endif
+        ssv6xxx_usb_recv_rx(glue, ssv_rx_buf);
+    }
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+    if (skb_queue_len(&rx_list)) {
+        glue->rx_cb(&rx_list, glue->rx_cb_args);
+    }
+#endif
+}
+static void ssv6xxx_usb_recv_rx_complete(struct urb *urb)
+{
+    struct ssv6xxx_rx_buf *ssv_rx_buf = (struct ssv6xxx_rx_buf *)urb->context;
+    struct ssv6xxx_usb_glue *glue = ssv_rx_buf->glue;
+    ssv_rx_buf->rx_res = urb->status;
+    if (urb->status) {
+        HWIF_DBG_PRINT(glue->p_wlan_data, "fail rx status received:%d\n", urb->status);
+        goto skip;
+    }
+    glue->err_cnt = 0;
+    ssv_rx_buf->rx_filled = urb->actual_length;
+    if (ssv_rx_buf->rx_filled > MAX_HCI_RX_AGGR_SIZE) {
+        HWIF_DBG_PRINT(glue->p_wlan_data, "recv invalid data length %d\n", ssv_rx_buf->rx_filled);
+        goto skip;
+    }
+    ssv6xxx_enqueue_list_node((struct ssv6xxx_list_node *)ssv_rx_buf, &glue->ssv_rx_queue);
+    if (ssv_rx_use_wq) {
+        queue_work(glue->wq, (struct work_struct *)&glue->rx_work);
+    } else {
+        tasklet_schedule(&glue->rx_tasklet);
+    }
+    return;
+skip:
+    ssv6xxx_usb_recv_rx(glue, ssv_rx_buf);
+}
+static void ssv6xxx_usb_recv_rx(struct ssv6xxx_usb_glue *glue, struct ssv6xxx_rx_buf *ssv_rx_buf)
+{
+    int size = MAX_HCI_RX_AGGR_SIZE;
+    int retval;
+    usb_fill_bulk_urb(ssv_rx_buf->rx_urb,
+                      glue->udev, usb_rcvbulkpipe(glue->udev, glue->rx_endpoint.address),
+                      ssv_rx_buf->rx_buf, size,
+                      ssv6xxx_usb_recv_rx_complete, ssv_rx_buf);
+    ssv_rx_buf->rx_urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP;
+    ssv_rx_buf->rx_filled = 0;
+    retval = usb_submit_urb(ssv_rx_buf->rx_urb, GFP_ATOMIC);
+    if (retval) {
+        HWIF_DBG_PRINT(glue->p_wlan_data, "Fail to submit rx urb, error=%d\n", retval);
+    }
+}
+static int __must_check ssv6xxx_usb_read(struct device *child,
+        void *buf, size_t *size, int mode)
+{
+    *size = 0;
+    return 0;
+}
+static int ssv6xxx_usb_send_tx(struct ssv6xxx_usb_glue *glue, struct sk_buff *skb, size_t size)
+{
+    int foolen = 0, retval = 0;
+    int tx_len = size;
+    if ((tx_len % glue->tx_endpoint.packet_size) == 0) {
+        skb_put(skb, 1);
+        tx_len++;
+    }
+    retval = usb_bulk_msg(glue->udev,
+                          usb_sndbulkpipe(glue->udev, glue->tx_endpoint.address),
+                          skb->data, tx_len, &foolen, TRANSACTION_TIMEOUT);
+    if (retval)
+        HWIF_DBG_PRINT(glue->p_wlan_data, "Cannot send tx data, retval=%d\n", retval);
+    return retval;
+}
+static int __must_check ssv6xxx_usb_write(struct device *child,
+        void *buf, size_t len, u8 queue_num)
+{
+    int retval = (-1);
+    struct ssv6xxx_usb_glue *glue = dev_get_drvdata(child->parent);
+    if (IS_GLUE_INVALID(glue))
+        return retval;
+    if ((retval = ssv6xxx_usb_send_tx(glue, (struct sk_buff *)buf, len)) < 0) {
+        HWIF_DBG_PRINT(glue->p_wlan_data, "%s: Fail to send tx data\n", __FUNCTION__);
+    } else {
+        glue->err_cnt = 0;
+    }
+    return retval;
+}
+static int __must_check __ssv6xxx_usb_read_reg(struct ssv6xxx_usb_glue *glue, u32 addr,
+        u32 *buf)
+{
+    int retval = (-1);
+    struct ssv6xxx_read_reg read_reg;
+    struct ssv6xxx_read_reg_result result;
+    if (IS_GLUE_INVALID(glue))
+        return retval;
+    memset(&read_reg, 0, sizeof(struct ssv6xxx_read_reg));
+    memset(&result, 0, sizeof(struct ssv6xxx_read_reg_result));
+    read_reg.addr = cpu_to_le32(addr);
+    retval = ssv6xxx_usb_cmd(glue, SSV6200_CMD_READ_REG, &read_reg, sizeof(struct ssv6xxx_read_reg), &result);
+    if (!retval)
+        *buf = le32_to_cpu(result.value);
+    else {
+        *buf = 0xffffffff;
+        HWIF_DBG_PRINT(glue->p_wlan_data, "%s: Fail to read register address %x\n", __FUNCTION__, addr);
+    }
+    return retval;
+}
+static int __must_check ssv6xxx_usb_read_reg(struct device *child, u32 addr,
+        u32 *buf)
+{
+    struct ssv6xxx_usb_glue *glue = dev_get_drvdata(child->parent);
+    return __ssv6xxx_usb_read_reg(glue, addr, buf);
+}
+static int __must_check __ssv6xxx_usb_write_reg(struct ssv6xxx_usb_glue *glue, u32 addr,
+        u32 buf)
+{
+    int retval = (-1);
+    struct ssv6xxx_write_reg write_reg;
+    if (IS_GLUE_INVALID(glue))
+        return retval;
+    memset(&write_reg, 0, sizeof(struct ssv6xxx_write_reg));
+    write_reg.addr = cpu_to_le32(addr);
+    write_reg.value = cpu_to_le32(buf);
+    retval = ssv6xxx_usb_cmd(glue, SSV6200_CMD_WRITE_REG, &write_reg, sizeof(struct ssv6xxx_write_reg), NULL);
+    if (retval)
+        HWIF_DBG_PRINT(glue->p_wlan_data, "%s: Fail to write register address %x, value %x\n", __FUNCTION__, addr, buf);
+    return retval;
+}
+static int __must_check ssv6xxx_usb_write_reg(struct device *child, u32 addr,
+        u32 buf)
+{
+    struct ssv6xxx_usb_glue *glue = dev_get_drvdata(child->parent);
+    return __ssv6xxx_usb_write_reg(glue, addr, buf);
+}
+static int __must_check ssv6xxx_usb_burst_read_reg(struct device *child, u32 *addr,
+        u32 *buf, u8 reg_amount)
+{
+    int ret = -1, i;
+    printk("%s(): Not support atomic burst register reading!\n", __func__);
+    WARN_ON(1);
+    for (i = 0 ; i < reg_amount ; i++) {
+        ret = ssv6xxx_usb_read_reg(child, addr[i], &buf[i]);
+        if (ret != 0) {
+            printk("%s(): read 0x%08x failed.\n", __func__, addr[i]);
+        }
+    }
+    return -EOPNOTSUPP;
+}
+static int __must_check ssv6xxx_usb_burst_write_reg(struct device *child, u32 *addr,
+        u32 *buf, u8 reg_amount)
+{
+    int ret = -1, i;
+    printk("%s(): Not support atomic burst register writing!\n", __func__);
+    WARN_ON(1);
+    for (i = 0 ; i < reg_amount ; i++) {
+        ret = ssv6xxx_usb_write_reg(child, addr[i], buf[i]);
+        if (ret != 0) {
+            printk("%s(): write 0x%08x failed.\n", __func__, addr[i]);
+        }
+    }
+    return -EOPNOTSUPP;
+}
+static int ssv6xxx_usb_load_firmware(struct device *child, u32 start_addr, u8 *data, int data_length)
+{
+    struct ssv6xxx_usb_glue *glue = dev_get_drvdata(child->parent);
+    u16 laddr, haddr;
+    u32 addr;
+    int retval = 0, max_usb_block = 512;
+    u8 *pdata;
+    int res_length, offset, send_length;
+    if (IS_GLUE_INVALID(glue))
+        return -1;
+    offset = 0;
+    pdata = data;
+    addr = start_addr;
+    res_length = data_length;
+    while (offset < data_length) {
+        int transfer = min_t(int, res_length, max_usb_block);
+        laddr = (addr & 0x0000ffff);
+        haddr = (addr >> 16);
+        send_length = usb_control_msg(glue->udev, usb_sndctrlpipe(glue->udev, 0),
+                                      FIRMWARE_DOWNLOAD, (USB_DIR_OUT | USB_TYPE_VENDOR),
+                                      laddr, haddr, pdata, transfer, TRANSACTION_TIMEOUT);
+        if (send_length < 0) {
+            retval = send_length;
+            HWIF_DBG_PRINT(glue->p_wlan_data, "Load Firmware Fail, retval=%d, sram=0x%08x\n", retval, (laddr|haddr));
+            break;
+        }
+        addr += transfer;
+        pdata += transfer;
+        offset += transfer;
+        res_length -= transfer;
+    }
+    return retval;
+}
+static int ssv6xxx_usb_property(struct device *child)
+{
+    return SSV_HWIF_CAPABILITY_POLLING | SSV_HWIF_INTERFACE_USB;
+}
+static int ssv6xxx_chk_usb_speed(struct ssv6xxx_usb_glue *glue)
+{
+    if (IS_GLUE_INVALID(glue)) {
+        return -1;
+    }
+    return glue->udev->speed;
+}
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+static void ssv6xxx_usb_rx_task(struct device *child,
+                                int (*rx_cb)(struct sk_buff_head *rxq, void *args),
+                                int (*is_rx_q_full)(void *args), void *args, u32 *pkt)
+#else
+static void ssv6xxx_usb_rx_task(struct device *child,
+                                int (*rx_cb)(struct sk_buff *rx_skb, void *args),
+                                int (*is_rx_q_full)(void *args), void *args, u32 *pkt)
+#endif
+{
+    struct ssv6xxx_usb_glue *glue = dev_get_drvdata(child->parent);
+    int i;
+    int nr_recvbuff = (ssv_rx_nr_recvbuff > MAX_NR_RECVBUFF)?MAX_NR_RECVBUFF:((ssv_rx_nr_recvbuff < MIN_NR_RECVBUFF)?MIN_NR_RECVBUFF:ssv_rx_nr_recvbuff);
+    printk("%s: nr_recvbuff=%d\n", __func__, nr_recvbuff);
+    glue->rx_cb = rx_cb;
+    glue->rx_cb_args = args;
+    glue->is_rx_q_full = is_rx_q_full;
+    glue->rx_pkt = pkt;
+    for (i = 0 ; i < nr_recvbuff ; ++i) {
+        ssv6xxx_usb_recv_rx(glue, &(glue->ssv_rx_buf[i]));
+    }
+}
+static int ssv6xxx_usb_start_acc(struct device *child, u8 epnum)
+{
+    struct ssv6xxx_usb_glue *glue = dev_get_drvdata(child->parent);
+    if (IS_GLUE_INVALID(glue)) {
+        printk("failed to start usb acc of ep%d\n", epnum);
+        return -1;
+    }
+    if (ssv6xxx_chk_usb_speed(glue) == USB_SPEED_HIGH)
+        glue->p_wlan_data->enable_usb_acc(glue->p_wlan_data->usb_param, epnum);
+    return 0;
+}
+static int ssv6xxx_usb_stop_acc(struct device *child, u8 epnum)
+{
+    struct ssv6xxx_usb_glue *glue = dev_get_drvdata(child->parent);
+    if (IS_GLUE_INVALID(glue)) {
+        printk("failed to stop usb acc of ep%d\n", epnum);
+        return -1;
+    }
+    if (ssv6xxx_chk_usb_speed(glue) == USB_SPEED_HIGH)
+        glue->p_wlan_data->disable_usb_acc(glue->p_wlan_data->usb_param, epnum);
+    return 0;
+}
+static int ssv6xxx_usb_jump_to_rom(struct device *child)
+{
+    struct ssv6xxx_usb_glue *glue = dev_get_drvdata(child->parent);
+    if (IS_GLUE_INVALID(glue)) {
+        printk("failed to jump to ROM\n");
+        return -1;
+    }
+    glue->p_wlan_data->jump_to_rom(glue->p_wlan_data->usb_param);
+    return 0;
+}
+static void ssv6xxx_usb_sysplf_reset(struct device *child, u32 addr, u32 value)
+{
+    struct ssv6xxx_usb_glue *glue = dev_get_drvdata(child->parent);
+    int retval = (-1), rsp_len = 0;
+    u16 sequence;
+    struct ssv6xxx_write_reg write_reg;
+    if (IS_GLUE_INVALID(glue))
+        return;
+    mutex_lock(&glue->cmd_mutex);
+    sequence = ssv6xxx_get_cmd_sequence(glue);
+    memset(&write_reg, 0, sizeof(struct ssv6xxx_write_reg));
+    write_reg.addr = cpu_to_le32(addr);
+    write_reg.value = cpu_to_le32(value);
+    retval = ssv6xxx_usb_send_cmd(glue, SSV6200_CMD_WRITE_REG, sequence, &write_reg, sizeof(struct ssv6xxx_write_reg));
+    if (retval)
+        HWIF_DBG_PRINT(glue->p_wlan_data, "%s: Fail to reset sysplf\n", __FUNCTION__);
+    retval = ssv6xxx_usb_recv_rsp(glue, SSV6XXX_MAX_RXCMDSZ, &rsp_len);
+    mutex_unlock(&glue->cmd_mutex);
+}
+static struct ssv6xxx_hwif_ops usb_ops = {
+    .read = ssv6xxx_usb_read,
+    .write = ssv6xxx_usb_write,
+    .readreg = ssv6xxx_usb_read_reg,
+    .writereg = ssv6xxx_usb_write_reg,
+    .safe_readreg = ssv6xxx_usb_read_reg,
+    .safe_writereg = ssv6xxx_usb_write_reg,
+    .burst_readreg = ssv6xxx_usb_burst_read_reg,
+    .burst_writereg = ssv6xxx_usb_burst_write_reg,
+    .burst_safe_readreg = ssv6xxx_usb_burst_read_reg,
+    .burst_safe_writereg = ssv6xxx_usb_burst_write_reg,
+    .load_fw = ssv6xxx_usb_load_firmware,
+    .property = ssv6xxx_usb_property,
+    .hwif_rx_task = ssv6xxx_usb_rx_task,
+    .start_usb_acc = ssv6xxx_usb_start_acc,
+    .stop_usb_acc = ssv6xxx_usb_stop_acc,
+    .jump_to_rom = ssv6xxx_usb_jump_to_rom,
+    .sysplf_reset = ssv6xxx_usb_sysplf_reset,
+};
+static void ssv6xxx_usb_power_on(struct ssv6xxx_platform_data * pdata, struct usb_interface *interface)
+{
+    if (pdata->is_enabled == true)
+        return;
+    pdata->is_enabled = true;
+}
+static void ssv6xxx_usb_power_off(struct ssv6xxx_platform_data * pdata, struct usb_interface *interface)
+{
+    if (pdata->is_enabled == false)
+        return;
+    pdata->is_enabled = false;
+}
+static void _read_chip_id (struct ssv6xxx_usb_glue *glue)
+{
+    u32 regval;
+    int ret;
+    u8 _chip_id[SSV6XXX_CHIP_ID_LENGTH];
+    u8 *c = _chip_id;
+    int i = 0;
+    ret = __ssv6xxx_usb_read_reg(glue, ADR_CHIP_ID_3, &regval);
+    *((u32 *)&_chip_id[0]) = __be32_to_cpu(regval);
+    if (ret == 0)
+        ret = __ssv6xxx_usb_read_reg(glue, ADR_CHIP_ID_2, &regval);
+    *((u32 *)&_chip_id[4]) = __be32_to_cpu(regval);
+    if (ret == 0)
+        ret = __ssv6xxx_usb_read_reg(glue, ADR_CHIP_ID_1, &regval);
+    *((u32 *)&_chip_id[8]) = __be32_to_cpu(regval);
+    if (ret == 0)
+        ret = __ssv6xxx_usb_read_reg(glue, ADR_CHIP_ID_0, &regval);
+    *((u32 *)&_chip_id[12]) = __be32_to_cpu(regval);
+    _chip_id[12+sizeof(u32)] = 0;
+    while (*c == 0) {
+        i++;
+        c++;
+        if (i == 16) {
+            c = _chip_id;
+            break;
+        }
+    }
+    if (*c != 0) {
+        strncpy(glue->tmp_data.chip_id, c, SSV6XXX_CHIP_ID_LENGTH);
+        dev_info(glue->dev, "CHIP ID: %s \n", glue->tmp_data.chip_id);
+        strncpy(glue->tmp_data.short_chip_id, c, SSV6XXX_CHIP_ID_SHORT_LENGTH);
+        glue->tmp_data.short_chip_id[SSV6XXX_CHIP_ID_SHORT_LENGTH] = 0;
+    } else {
+        dev_err(glue->dev, "Failed to read chip ID");
+        glue->tmp_data.chip_id[0] = 0;
+    }
+}
+static int ssv_usb_probe(struct usb_interface *interface,
+                         const struct usb_device_id *id)
+{
+    struct ssv6xxx_platform_data *pwlan_data;
+    struct ssv6xxx_usb_glue *glue;
+    struct usb_host_interface *iface_desc;
+    struct usb_endpoint_descriptor *endpoint;
+    int i, j;
+    int retval = -ENOMEM;
+    unsigned int epnum;
+    printk(KERN_INFO "=======================================\n");
+    printk(KERN_INFO "==          TURISMO - USB            ==\n");
+    printk(KERN_INFO "=======================================\n");
+    glue = kzalloc(sizeof(*glue), GFP_KERNEL);
+    if (!glue) {
+        dev_err(&interface->dev, "Out of memory\n");
+        goto error;
+    }
+    glue->sequence = 0;
+    glue->err_cnt = 0;
+    kref_init(&glue->kref);
+    mutex_init(&glue->io_mutex);
+    mutex_init(&glue->cmd_mutex);
+    tu_ssv6xxx_init_queue(&glue->ssv_rx_queue);
+    if (ssv_rx_use_wq) {
+        glue->rx_work.glue = glue;
+        INIT_WORK((struct work_struct *)&glue->rx_work, ssv6xxx_usb_recv_rx_work);
+        glue->wq = create_singlethread_workqueue("ssv6xxx_usb_wq");
+        if (!glue->wq) {
+            dev_err(&interface->dev, "Could not allocate Work Queue\n");
+            goto error;
+        }
+    } else {
+        tasklet_init(&glue->rx_tasklet, ssv6xxx_usb_recv_rx_tasklet, (unsigned long)glue);
+    }
+    pwlan_data = &glue->tmp_data;
+    memset(pwlan_data, 0, sizeof(struct ssv6xxx_platform_data));
+    atomic_set(&pwlan_data->irq_handling, 0);
+    glue->dev = &interface->dev;
+    glue->udev = usb_get_dev(interface_to_usbdev(interface));
+    glue->interface = interface;
+    glue->dev_ready = true;
+    pwlan_data->vendor = id->idVendor;
+    pwlan_data->device = id->idProduct;
+    pwlan_data->ops = &usb_ops;
+    iface_desc = interface->cur_altsetting;
+    for (i = 0; i < iface_desc->desc.bNumEndpoints; ++i) {
+        endpoint = &iface_desc->endpoint[i].desc;
+        epnum = endpoint->bEndpointAddress & 0x0f;
+        if (epnum == SSV_EP_CMD) {
+            glue->cmd_endpoint.address = endpoint->bEndpointAddress;
+            glue->cmd_endpoint.packet_size = le16_to_cpu(endpoint->wMaxPacketSize);
+            glue->cmd_endpoint.buff = kmalloc(SSV6XXX_MAX_TXCMDSZ, GFP_ATOMIC);
+            if (!glue->cmd_endpoint.buff) {
+                dev_err(&interface->dev, "Could not allocate cmd buffer\n");
+                goto error;
+            }
+        }
+        if (epnum == SSV_EP_RSP) {
+            glue->rsp_endpoint.address = endpoint->bEndpointAddress;
+            glue->rsp_endpoint.packet_size = le16_to_cpu(endpoint->wMaxPacketSize);
+            glue->rsp_endpoint.buff = kmalloc(SSV6XXX_MAX_RXCMDSZ, GFP_ATOMIC);
+            if (!glue->rsp_endpoint.buff) {
+                dev_err(&interface->dev, "Could not allocate rsp buffer\n");
+                goto error;
+            }
+        }
+        if (epnum == SSV_EP_TX) {
+            glue->tx_endpoint.address = endpoint->bEndpointAddress;
+            glue->tx_endpoint.packet_size = le16_to_cpu(endpoint->wMaxPacketSize);
+        }
+        if (epnum == SSV_EP_RX) {
+            glue->rx_endpoint.address = endpoint->bEndpointAddress;
+            glue->rx_endpoint.packet_size = le16_to_cpu(endpoint->wMaxPacketSize);
+            for (j = 0 ; j < MAX_NR_RECVBUFF ; ++j) {
+                glue->ssv_rx_buf[j].rx_urb = usb_alloc_urb(0, GFP_ATOMIC);
+                if (!glue->ssv_rx_buf[j].rx_urb) {
+                    dev_err(&interface->dev, "Could not allocate rx urb\n");
+                    goto error;
+                }
+                glue->ssv_rx_buf[j].rx_buf = usb_alloc_coherent(
+                                                 glue->udev, MAX_HCI_RX_AGGR_SIZE,
+                                                 GFP_ATOMIC, &glue->ssv_rx_buf[j].rx_urb->transfer_dma);
+                if (!glue->ssv_rx_buf[j].rx_buf) {
+                    dev_err(&interface->dev, "Could not allocate rx buffer\n");
+                    goto error;
+                }
+                glue->ssv_rx_buf[j].glue = glue;
+                tu_ssv6xxx_init_list_node((struct ssv6xxx_list_node *)&glue->ssv_rx_buf[j]);
+            }
+        }
+    }
+    if (!(glue->cmd_endpoint.address &&
+          glue->rsp_endpoint.address &&
+          glue->tx_endpoint.address &&
+          glue->rx_endpoint.address)) {
+        dev_err(&interface->dev, "Could not find all endpoints\n");
+        goto error;
+    }
+    usb_set_intfdata(interface, glue);
+    ssv6xxx_usb_power_on(pwlan_data, interface);
+    _read_chip_id(glue);
+    glue->core = platform_device_alloc(pwlan_data->short_chip_id, -1);
+    if (!glue->core) {
+        dev_err(glue->dev, "can't allocate platform_device");
+        retval = -ENOMEM;
+        goto error;
+    }
+    glue->core->dev.parent = &interface->dev;
+    retval = platform_device_add_data(glue->core, pwlan_data, sizeof(*pwlan_data));
+    if (retval) {
+        dev_err(glue->dev, "can't add platform data\n");
+        goto out_dev_put;
+    }
+    glue->p_wlan_data = glue->core->dev.platform_data;
+    retval = platform_device_add(glue->core);
+    if (retval) {
+        dev_err(glue->dev, "can't add platform device\n");
+        goto out_dev_put;
+    }
+#ifdef SSV_SUPPORT_USB_LPM
+    printk("---------- USB LPM capability ---------- \n");
+    printk("device supports LPM: %d\n", glue->udev->lpm_capable);
+    printk("device can perform USB2 hardware LPM: %d\n", glue->udev->usb2_hw_lpm_capable);
+    printk("USB2 (Host) hardware LPM is enabled: %d\n", glue->udev->usb2_hw_lpm_enabled);
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,12,2)
+    printk("Userspace allows USB 2.0 LPM to be enabled: %d\n", glue->udev->usb2_hw_lpm_allowed);
+#endif
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,11,0)
+    printk("device can perform USB2 hardware BESL LPM: %d\n", glue->udev->usb2_hw_lpm_besl_capable);
+#endif
+    printk("----------------------------------------\n");
+#endif
+    return 0;
+out_dev_put:
+    platform_device_put(glue->core);
+error:
+    if (glue)
+        kref_put(&glue->kref, ssv6xxx_usb_delete);
+    return retval;
+}
+static void ssv_usb_disconnect(struct usb_interface *interface)
+{
+    struct ssv6xxx_usb_glue *glue;
+    glue = usb_get_intfdata(interface);
+    usb_set_intfdata(interface, NULL);
+    if (glue) {
+        glue->dev_ready = false;
+        ssv6xxx_usb_power_off(glue->p_wlan_data, interface);
+        printk("platform_device_del \n");
+        platform_device_del(glue->core);
+        printk("platform_device_put \n");
+        platform_device_put(glue->core);
+    }
+    mutex_lock(&glue->io_mutex);
+    glue->interface = NULL;
+    mutex_unlock(&glue->io_mutex);
+    kref_put(&glue->kref, ssv6xxx_usb_delete);
+    dev_info(&interface->dev, "SSV USB is disconnected");
+}
+#ifdef CONFIG_PM
+static int ssv_usb_suspend(struct usb_interface *interface, pm_message_t message)
+{
+    struct ssv6xxx_usb_glue *glue = usb_get_intfdata(interface);
+    int i;
+    dev_info(glue->dev, "%s(): suspend.\n", __FUNCTION__);
+    if (!glue)
+        return 0;
+    glue->p_wlan_data->suspend(glue->p_wlan_data->pm_param);
+    for (i = 0 ; i < MAX_NR_RECVBUFF ; ++i) {
+        usb_kill_urb(glue->ssv_rx_buf[i].rx_urb);
+    }
+    return 0;
+}
+static int ssv_usb_resume(struct usb_interface *interface)
+{
+    struct ssv6xxx_usb_glue *glue = usb_get_intfdata(interface);
+    int i;
+    int nr_recvbuff = (ssv_rx_nr_recvbuff > MAX_NR_RECVBUFF)?MAX_NR_RECVBUFF:((ssv_rx_nr_recvbuff < MIN_NR_RECVBUFF)?MIN_NR_RECVBUFF:ssv_rx_nr_recvbuff);
+    dev_info(glue->dev, "%s(): resume.\n", __FUNCTION__);
+    if (!glue)
+        return 0;
+    for (i = 0 ; i < nr_recvbuff ; ++i) {
+        ssv6xxx_usb_recv_rx(glue, &(glue->ssv_rx_buf[i]));
+    }
+    glue->p_wlan_data->resume(glue->p_wlan_data->pm_param);
+    return 0;
+}
+#endif
+static struct usb_driver ssv_usb_driver = {
+    .name = "SSV6XXX_USB",
+    .probe = ssv_usb_probe,
+    .disconnect = ssv_usb_disconnect,
+#ifdef CONFIG_PM
+    .suspend = ssv_usb_suspend,
+    .resume = ssv_usb_resume,
+#endif
+    .id_table = ssv_usb_table,
+    .supports_autosuspend = 1,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
+    .disable_hub_initiated_lpm = 0,
+#endif
+};
+#if (defined(CONFIG_SSV_SUPPORT_ANDROID)||defined(CONFIG_SSV_BUILD_AS_ONE_KO))
+int ssv6xxx_usb_init(void)
+#else
+static int __init ssv6xxx_usb_init(void)
+#endif
+{
+    printk(KERN_INFO "ssv6xxx_usb_init\n");
+    return usb_register(&ssv_usb_driver);
+}
+static int ssv_usb_do_device_exit(struct device *d, void *arg)
+{
+    struct usb_interface *intf = to_usb_interface(d);
+    struct ssv6xxx_usb_glue *glue = usb_get_intfdata(intf);
+    u32 regval;
+    int ret;
+    if (glue != NULL) {
+        printk(KERN_INFO "ssv_usb_do_device_exit: JUMP to ROM\n");
+        ret = __ssv6xxx_usb_read_reg(glue, 0xc000001c, &regval);
+        if (__ssv6xxx_usb_write_reg(glue, 0xc000001c, (regval & 0xfeffffff)));
+        ret = __ssv6xxx_usb_read_reg(glue, 0xc00000ec, &regval);
+        if (__ssv6xxx_usb_write_reg(glue, 0xc00000ec, (regval & 0xffffefff)));
+        ret = __ssv6xxx_usb_read_reg(glue, 0xc00000e8, &regval);
+        if (__ssv6xxx_usb_write_reg(glue, 0xc00000e8, (regval | 0x00000004)));
+        ret = __ssv6xxx_usb_read_reg(glue, 0xc000001c, &regval);
+        if (__ssv6xxx_usb_write_reg(glue, 0xc000001c, (regval | 0x01000000)));
+    }
+    msleep(50);
+    return 0;
+}
+#if (defined(CONFIG_SSV_SUPPORT_ANDROID)||defined(CONFIG_SSV_BUILD_AS_ONE_KO))
+void ssv6xxx_usb_exit(void)
+#else
+static void __exit ssv6xxx_usb_exit(void)
+#endif
+{
+    if (driver_for_each_device(&ssv_usb_driver.drvwrap.driver, NULL,
+                               NULL, ssv_usb_do_device_exit)) {};
+    printk(KERN_INFO "ssv6xxx_usb_exit\n");
+    usb_deregister(&ssv_usb_driver);
+}
+#if (defined(CONFIG_SSV_SUPPORT_ANDROID)||defined(CONFIG_SSV_BUILD_AS_ONE_KO))
+EXPORT_SYMBOL(ssv6xxx_usb_init);
+EXPORT_SYMBOL(ssv6xxx_usb_exit);
+#else
+module_init(ssv6xxx_usb_init);
+module_exit(ssv6xxx_usb_exit);
+#endif
+MODULE_LICENSE("GPL");
diff --git a/drivers/net/wireless/ssv6x5x/hwif/usb/usb.h b/drivers/net/wireless/ssv6x5x/hwif/usb/usb.h
new file mode 100644
index 000000000..14fccf1c3
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/hwif/usb/usb.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _USB_DEF_H_
+#define _USB_DEF_H_
+#include <ssv_data_struct.h>
+#define USB_DBG(fmt,...) pr_debug(fmt "\n", ##__VA_ARGS__)
+#define FW_START_ADDR 0x00
+#define FIRMWARE_DOWNLOAD 0xf0
+#define SSV_EP_CMD 0x01
+#define SSV_EP_RSP 0x02
+#define SSV_EP_TX 0x03
+#define SSV_EP_RX 0x04
+#define SSV6200_CMD_WRITE_REG 0x01
+#define SSV6200_CMD_READ_REG 0x02
+struct ssv6xxx_read_reg_result {
+    u32 value;
+} __attribute__ ((packed));
+struct ssv6xxx_read_reg {
+    u32 addr;
+    u32 value;
+} __attribute__ ((packed));
+struct ssv6xxx_write_reg {
+    u32 addr;
+    u32 value;
+} __attribute__ ((packed));
+union ssv6xxx_payload {
+    struct ssv6xxx_read_reg rreg;
+    struct ssv6xxx_read_reg_result rreg_res;
+    struct ssv6xxx_write_reg wreg;
+};
+struct ssv6xxx_cmd_hdr {
+    u8 plen;
+    u8 cmd;
+    u16 seq;
+    union ssv6xxx_payload payload;
+} __attribute__ ((packed));
+struct ssv6xxx_cmd_endpoint {
+    u8 address;
+    u16 packet_size;
+    void *buff;
+};
+struct ssv6xxx_tx_endpoint {
+    u8 address;
+    u16 packet_size;
+    int tx_res;
+};
+struct ssv6xxx_rx_endpoint {
+    u8 address;
+    u16 packet_size;
+};
+#define MAX_NR_RECVBUFF (8)
+#define MIN_NR_RECVBUFF (1)
+struct ssv6xxx_rx_buf {
+    struct ssv6xxx_list_node node;
+    struct ssv6xxx_usb_glue *glue;
+    struct urb *rx_urb;
+    void *rx_buf;
+    unsigned int rx_filled;
+    int rx_res;
+};
+struct ssv6xxx_usb_work_struct {
+    struct work_struct work;
+    struct ssv6xxx_usb_glue *glue;
+};
+#if (defined(CONFIG_SSV_SUPPORT_ANDROID)||defined(CONFIG_SSV_BUILD_AS_ONE_KO))
+int ssv6xxx_usb_init(void);
+void ssv6xxx_usb_exit(void);
+#endif
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/include/cabrio.h b/drivers/net/wireless/ssv6x5x/include/cabrio.h
new file mode 100644
index 000000000..092c5fe16
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/include/cabrio.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef CABRIO_H
+#define CABRIO_H
+#define SSV_VENDOR_ID 0x3030
+#define SSV_CABRIO_DEVID 0x3030
+#define SSV_SUBVENDOR_ID_NOG 0x0e11
+#define SSV_SUBVENDOR_ID_NEW_A 0x7065
+#define SSV_CABRIO_MAGIC 0x19641014
+#define SSV_AMPDU_LIMIT_MAX (64 * 1024 - 1)
+#define SSV_DEFAULT_NOISE_FLOOR -95
+#define SSVCABRIO_RSSI_BAD -128
+#define SSVCABRIO_NUM_CHANNELS 38
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/include/hal.h b/drivers/net/wireless/ssv6x5x/include/hal.h
new file mode 100644
index 000000000..931c6c4b5
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/include/hal.h
@@ -0,0 +1,342 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _HAL_H_
+#define _HAL_H_
+#ifdef SSV_SUPPORT_HAL
+extern u32 phy_info_tbl[];
+extern size_t phy_info_tbl_size;
+#include <smac/ssv_reg_acc.h>
+enum ssv6xxx_beacon_type {
+    SSV6xxx_BEACON_0,
+    SSV6xxx_BEACON_1,
+};
+#define EFUSE_HWSET_MAX_SIZE (256-32)
+#define EFUSE_MAX_SECTION_MAP (EFUSE_HWSET_MAX_SIZE>>5)
+#define BEACON_WAITING_ENABLED 1<<0
+#define BEACON_ENABLED 1<<1
+#define MAX_FAIL_COUNT 100
+#define MAX_RETRY_COUNT 20
+#define HW_ID_OFFSET 7
+#define ADDRESS_OFFSET 16
+int tu_ssv6xxx_init_hal(struct ssv_softc *sc);
+int ssvxxx_get_sta_assco_cnt(struct ssv_softc *sc);
+#define HAL_ADJ_CONFIG(_sh) _sh->hal_ops.adj_config(_sh)
+#define HAL_NEED_SW_CIPHER(_sh) _sh->hal_ops.need_sw_cipher(_sh)
+#define HAL_INIT_MAC(_sh) _sh->hal_ops.init_mac(_sh)
+#define HAL_RESET_SYSPLF(_sh) _sh->hal_ops.reset_sysplf(_sh)
+#define HAL_INI_HW_SEC_PHY_TABLE(_sc) _sc->sh->hal_ops.init_hw_sec_phy_table(_sc)
+#define HAL_INIT_IQK(_sh) _sh->hal_ops.init_iqk(_sh)
+#define HAL_WRITE_MAC_INI(_sh) _sh->hal_ops.write_mac_ini(_sh)
+#define HAL_USE_HW_ENCRYPT(_cipher,_sc,_sta_priv,_vif_priv) \
+                _sc->sh->hal_ops.use_hw_encrypt(_cipher, _sc, _sta_priv, _vif_priv)
+#define HAL_SET_RX_FLOW(_sh,_type,_rxflow) \
+                _sh->hal_ops.set_rx_flow(_sh, _type, _rxflow)
+#define HAL_SET_RX_CTRL_FLOW(_sh) _sh->hal_ops.set_rx_ctrl_flow(_sh)
+#define HAL_SET_MACADDR(_sh,_vif_idx) _sh->hal_ops.set_macaddr(_sh, _vif_idx)
+#define HAL_SET_BSSID(_sh,_bssid,_vif_idx) \
+                _sh->hal_ops.set_bssid(_sh, _bssid, _vif_idx)
+#define HAL_GET_IC_TIME_TAG(_sh) _sh->hal_ops.get_ic_time_tag(_sh)
+#define HAL_GET_CHIP_ID(_sh) _sh->hal_ops.get_chip_id(_sh)
+#define HAL_IF_CHK_MAC2(_sh) _sh->hal_ops.if_chk_mac2(_sh)
+#define HAL_SAVE_HW_STATUS(_sc) _sc->sh->hal_ops.save_hw_status( _sc)
+#define HAL_PLL_CHK(_sh) _sh->hal_ops.pll_chk(_sh)
+#define HAL_GET_WSID(_sc,_vif,_sta) _sc->sh->hal_ops.get_wsid( _sc, _vif, _sta)
+#define HAL_SET_HW_WSID(_sc,_vif,_sta,_wsid) \
+                _sc->sh->hal_ops.set_hw_wsid( _sc, _vif, _sta, _wsid)
+#define HAL_DEL_HW_WSID(_sc,_hw_wsid) _sc->sh->hal_ops.del_hw_wsid( _sc, _hw_wsid)
+#define HAL_ADD_FW_WSID(_sc,_vif_priv,_sta,_sta_info) \
+                _sc->sh->hal_ops.add_fw_wsid( _sc, _vif_priv, _sta, _sta_info)
+#define HAL_DEL_FW_WSID(_sc,_sta,_sta_info) \
+                _sc->sh->hal_ops.del_fw_wsid( _sc, _sta, _sta_info)
+#define HAL_SET_FW_HWWSID_SEC_TYPE(_sc,_sta,_sta_info,_vif_priv) \
+                _sc->sh->hal_ops.set_fw_hwwsid_sec_type( _sc, _sta, _sta_info, _vif_priv)
+#define HAL_ENABLE_FW_WSID(_sc,_sta,_sta_info,_key_type) \
+                _sc->sh->hal_ops.enable_fw_wsid( _sc, _sta, _sta_info, _key_type)
+#define HAL_DISABLE_FW_WSID(_sc,_key_idx,_sta_priv,_vif_priv) \
+                _sc->sh->hal_ops.disable_fw_wsid( _sc, _key_idx, _sta_priv, _vif_priv)
+#define HAL_WEP_USE_HW_CIPHER(_sc,_vif_priv) \
+                 _sc->sh->hal_ops.wep_use_hw_cipher( _sc, _vif_priv)
+#define HAL_PAIRWISE_WPA_USE_HW_CIPHER(_sc,_vif_priv,_cipher,_sta_priv) \
+                _sc->sh->hal_ops.pairwise_wpa_use_hw_cipher( _sc, _vif_priv, _cipher, _sta_priv)
+#define HAL_GROUP_WPA_USE_HW_CIPHER(_sc,_vif_priv,_cipher) \
+                _sc->sh->hal_ops.group_wpa_use_hw_cipher( _sc, _vif_priv, _cipher)
+#define HAL_SET_AES_TKIP_HW_CRYPTO_GROUP_KEY(_sc,_vif_info,_sta_info,_param) \
+                _sc->sh->hal_ops.set_aes_tkip_hw_crypto_group_key(_sc, _vif_info, _sta_info, _param)
+#define HAL_WRITE_PAIRWISE_KEYIDX_TO_HW(_sh,_key_idx,_wsid) \
+                _sh->hal_ops.write_pairwise_keyidx_to_hw(_sh, _key_idx, _wsid)
+#define HAL_WRITE_GROUP_KEYIDX_TO_HW(_sh,_vif_priv,_key_idx) \
+                _sh->hal_ops.write_group_keyidx_to_hw(_sh, _vif_priv, _key_idx)
+#define HAL_WRITE_PAIRWISE_KEY_TO_HW(_sc,_key_idx,_alg,_key,_key_len,_keyconf,_vif_priv,_sta_priv) \
+                _sc->sh->hal_ops.write_pairwise_key_to_hw(_sc, _key_idx, _alg, _key, _key_len, _keyconf, _vif_priv, _sta_priv)
+#define HAL_WRITE_GROUP_KEY_TO_HW(_sc,_key_idx,_alg,_key,_key_len,_keyconf,_vif_priv,_sta_priv) \
+                _sc->sh->hal_ops.write_group_key_to_hw(_sc, _key_idx, _alg, _key, _key_len, _keyconf, _vif_priv, _sta_priv)
+#define HAL_WRITE_KEY_TO_HW(_sc,_vif_priv,_sram_ptr,_wsid,_key_idx,_key_type) \
+                _sc->sh->hal_ops.write_key_to_hw(_sc, _vif_priv, _sram_ptr, _wsid, _key_idx, _key_type)
+#define HAL_SET_GROUP_CIPHER_TYPE(_sh,_vif_priv,_cipher) \
+                _sh->hal_ops.set_group_cipher_type( _sh, _vif_priv, _cipher)
+#define HAL_SET_PAIRWISE_CIPHER_TYPE(_sh,_cipher,_wsid) \
+                _sh->hal_ops.set_pairwise_cipher_type( _sh, _cipher, _wsid)
+#define HAL_CHK_IF_SUPPORT_HW_BSSID(_sc,_vif_idx) \
+                _sc->sh->hal_ops.chk_if_support_hw_bssid( _sc, _vif_idx)
+#define HAL_CHK_DUAL_VIF_CHG_RX_FLOW(_sc,_vif_priv) \
+                _sc->sh->hal_ops.chk_dual_vif_chg_rx_flow( _sc, _vif_priv)
+#define HAL_RESTORE_RX_FLOW(_sc,_vif_priv,_sta) \
+                _sc->sh->hal_ops.restore_rx_flow( _sc, _vif_priv, _sta)
+#define HAL_HW_CRYPTO_KEY_WRITE_WEP(_sc,_keyconf,_alg,_vif_info) \
+                _sc->sh->hal_ops.hw_crypto_key_write_wep( _sc, _keyconf, _alg, _vif_info)
+#define HAL_SET_WEP_HW_CRYPTO_KEY(_sc,_sta_info,_vif_priv) \
+                _sc->sh->hal_ops.set_wep_hw_crypto_key( _sc, _sta_info, _vif_priv)
+#define HAL_STORE_WEP_KEY(_sc,_vif_priv,_sta_priv,_cipher,_key) \
+                _sc->sh->hal_ops.store_wep_key( _sc, _vif_priv, _sta_priv, _cipher, _key)
+#define HAL_PUT_MIC_SPACE_FOR_HW_CCMP_ENCRYPT(_sc,_skb) \
+                _sc->sh->hal_ops.put_mic_space_for_hw_ccmp_encrypt( _sc, _skb)
+#ifdef CONFIG_PM
+#define HAL_SAVE_CLEAR_TRAP_REASON(_sc) \
+                _sc->sh->hal_ops.save_clear_trap_reason(_sc)
+#define HAL_RESTORE_TRAP_REASON(_sc) \
+                _sc->sh->hal_ops.restore_trap_reason(_sc)
+#define HAL_PMU_AWAKE(_sc) \
+                _sc->sh->hal_ops.pmu_awake(_sc)
+#endif
+#define HAL_SET_REPLAY_IGNORE(_sh,_ignore) \
+                _sh->hal_ops.set_replay_ignore(_sh, _ignore)
+#define HAL_UPDATE_DECISION_TABLE_6(_sh,_val) \
+                _sh->hal_ops.update_decision_table_6(_sh, _val)
+#define HAL_UPDATE_DECISION_TABLE(_sc) _sc->sh->hal_ops.update_decision_table(_sc)
+#define HAL_GET_FW_VERSION(_sh,_regval) \
+                _sh->hal_ops.get_fw_version(_sh, _regval)
+#define HAL_SET_MRX_MODE(_sh,_regval) _sh->hal_ops.set_mrx_mode(_sh, _regval)
+#define HAL_GET_MRX_MODE(_sh,_regval) _sh->hal_ops.get_mrx_mode(_sh, _regval)
+#define HAL_SET_OP_MODE(_sh,_op_mode,_vif_idx) _sh->hal_ops.set_op_mode(_sh, _op_mode, _vif_idx)
+#define HAL_HALT_MNGQ_UNTIL_DTIM(_sh,_val) \
+                _sh->hal_ops.set_halt_mngq_util_dtim(_sh,_val)
+#define HAL_SET_DUR_BURST_SIFS_G(_sh,_val) \
+                _sh->hal_ops.set_dur_burst_sifs_g(_sh, _val)
+#define HAL_SET_DUR_SLOT(_sh,_val) _sh->hal_ops.set_dur_slot(_sh, _val)
+#define HAL_SET_SIFS(_sh,_band) _sh->hal_ops.set_sifs(_sh, _band)
+#define HAL_SET_QOS_ENABLE(_sh,_val) _sh->hal_ops.set_qos_enable(_sh, _val)
+#define HAL_SET_WMM_PARAM(_sc,_params,_queue) \
+                _sc->sh->hal_ops.set_wmm_param(_sc, _params, _queue)
+#define HAL_UPDATE_PAGE_ID(_sh) _sh->hal_ops.update_page_id(_sh)
+#define HAL_INIT_TX_CFG(_sh) _sh->hal_ops.init_tx_cfg(_sh)
+#define HAL_INIT_RX_CFG(_sh) _sh->hal_ops.init_rx_cfg(_sh)
+#define HAL_ALLOC_PBUF(_sc,_size,_type) \
+                _sc->sh->hal_ops.alloc_pbuf(_sc, _size, _type)
+#define HAL_FREE_PBUF(_sc,_addr) _sc->sh->hal_ops.free_pbuf(_sc, _addr)
+#define HAL_AMPDU_AUTO_CRC_EN(_sh) _sh->hal_ops.ampdu_auto_crc_en(_sh)
+#define HAL_SET_RX_BA(_sh,_on,_ta,_tid,_ssn,_buf_size) \
+                _sh->hal_ops.set_rx_ba(_sh, _on, _ta, _tid, _ssn, _buf_size)
+#define HAL_READ_EFUSE(_sh,_pbuf) _sh->hal_ops.read_efuse(_sh, _pbuf)
+#define HAL_WRITE_EFUSE(_sh,_data,_len) _sh->hal_ops.write_efuse(_sh, _data, _len)
+#define HAL_BEACON_GET_VALID_CFG(_sh) _sh->hal_ops.beacon_get_valid_cfg(_sh)
+#define HAL_SET_BEACON_REG_LOCK(_sh,_val) \
+                                       _sh->hal_ops.set_beacon_reg_lock(_sh, _val)
+#define HAL_SET_BCN_ID_DTIM(_sc,_bcntype,_dtim) \
+                _sc->sh->hal_ops.set_beacon_id_dtim(_sc, _bcntype, _dtim)
+#define HAL_FILL_BCN(_sc,_regaddr,_skb) \
+                _sc->sh->hal_ops.fill_beacon(_sc, _regaddr, _skb)
+#define HAL_BEACON_ENABLE(_sc,_val) _sc->sh->hal_ops.beacon_enable(_sc, _val)
+#define HAL_SET_BCN_IFNO(_sh,_interval,_cnt) \
+                _sh->hal_ops.set_beacon_info(_sh, _interval, _cnt)
+#define HAL_GET_BCN_ONGOING(_sh) _sh->hal_ops.get_bcn_ongoing(_sh)
+#define HAL_BEACON_LOSS_ENABLE(_sh) _sh->hal_ops.beacon_loss_enable(_sh)
+#define HAL_BEACON_LOSS_DISABLE(_sh) _sh->hal_ops.beacon_loss_disable(_sh)
+#define HAL_BEACON_LOSS_CONFIG(_sh,_beacon_int,_bssid) \
+    _sh->hal_ops.beacon_loss_config(_sh, _beacon_int, _bssid)
+#define HAL_UPDATE_TXQ_MASK(_sh,_txq_mask) \
+                _sh->hal_ops.update_txq_mask(_sh, _txq_mask)
+#define HAL_READRG_HCI_INQ_INFO(_sh,_hci_used_id,_tx_use_page) \
+                _sh->hal_ops.readrg_hci_inq_info(_sh, _hci_used_id, _tx_use_page)
+#define HAL_READRG_TXQ_INFO(_sh,_txq_info,_hci_used_id) \
+                _sh->hal_ops.readrg_txq_info(_sh, _txq_info, _hci_used_id)
+#define HAL_READRG_TXQ_INFO2(_sh,_txq_info2,_hci_used_id) \
+                _sh->hal_ops.readrg_txq_info2(_sh, _txq_info2, _hci_used_id)
+#define HAL_DUMP_WSID(_sh) \
+                _sh->hal_ops.dump_wsid(_sh)
+#define HAL_DUMP_DECISION(_sh) \
+                _sh->hal_ops.dump_decision(_sh)
+#define HAL_DUMP_PHY_REG(_sh) \
+                _sh->hal_ops.dump_phy_reg(_sh)
+#define HAL_DUMP_RF_REG(_sh) \
+                _sh->hal_ops.dump_rf_reg(_sh)
+#define HAL_GET_FFOUT_CNT(_sh,_value,_tag) \
+    _sh->hal_ops.get_ffout_cnt(_value, _tag)
+#define HAL_GET_IN_FFCNT(_sh,_value,_tag) \
+    _sh->hal_ops.get_in_ffcnt(_value, _tag)
+#define HAL_READ_FFOUT_CNT(_sh,_value,_value1,_value2) \
+                _sh->hal_ops.read_ffout_cnt(_sh, _value, _value1, _value2)
+#define HAL_READ_IN_FFCNT(_sh,_value,_value1) \
+                _sh->hal_ops.read_in_ffcnt(_sh, _value, _value1)
+#define HAL_READ_ID_LEN_THRESHOLD(_sh,_tx_len,_rx_len) \
+                _sh->hal_ops.read_id_len_threshold(_sh, _tx_len, _rx_len)
+#define HAL_READ_TAG_STATUS(_sh,_ava_status) \
+                _sh->hal_ops.read_tag_status(_sh, _ava_status)
+#define HAL_CMD_MIB(_sc,_argc,_argv) _sc->sh->hal_ops.cmd_mib(_sc, _argc, _argv)
+#define HAL_CMD_POWER_SAVING(_sc,_argc,_argv) _sc->sh->hal_ops.cmd_power_saving(_sc, _argc, _argv)
+#define HAL_SUPPORT_IQK_CMD(_sh) _sh->hal_ops.support_iqk_cmd(_sh)
+#define HAL_GET_RD_ID_ADR(_sh,_id_adr) \
+                _sh->hal_ops.get_rd_id_adr(_id_adr)
+#define HAL_CMD_CALI(_sh,_argc,_argv) \
+                _sh->hal_ops.cmd_cali(_sh, _argc, _argv)
+#define HAL_BURST_READ_REG(_sh,_reg,_val,_num) \
+                _sh->hal_ops.burst_read_reg(_sh, _reg, _val, _num)
+#define HAL_BURST_WRITE_REG(_sh,_reg,_val,_num) \
+                _sh->hal_ops.burst_write_reg(_sh, _reg, _val, _num)
+#define HAL_AUTO_GEN_NULLPKT(_sh,_hwq) \
+    _sh->hal_ops.auto_gen_nullpkt(_sh, _hwq)
+#define HAL_RC_ALGORITHM(_sc) _sc->sh->hal_ops.rc_algorithm(_sc)
+#define HAL_SET_80211HW_RATE_CONFIG(_sc) \
+     _sc->sh->hal_ops.set_80211_hw_rate_config(_sc)
+#define HAL_RC_LEGACY_BITRATE_TO_RATE_DESC(_sc,_bitrate,_drate) \
+     _sc->sh->hal_ops.rc_legacy_bitrate_to_rate_desc(_bitrate, _drate)
+#define HAL_RC_RX_DATA_HANDLER(_sc,_skb,rate_idx) \
+     _sc->sh->hal_ops.rc_rx_data_handler(_sc, _skb, rate_idx)
+#define HAL_RATE_REPORT_HANDLER(_sc,_skb,_no_ba_result) \
+     _sc->sh->hal_ops.rate_report_handler(_sc, _skb, _no_ba_result)
+#define HAL_RC_PROCESS_RATE_REPORT(_sc,_skb) \
+     _sc->sh->hal_ops.rc_process_rate_report(_sc, _skb)
+#define HAL_RC_UPDATE_BASIC_RATE(_sc,_basic_rates) \
+     _sc->sh->hal_ops.rc_update_basic_rate(_sc, _basic_rates)
+#define HAL_HT_RATE_UPDATE(_sc,_skb,_rates) \
+     _sc->sh->hal_ops.rc_ht_update_rate(_skb, _sc, _rates)
+#define HAL_RC_HT_STA_CURRENT_RATE_IS_CCK(_sc,_sta) \
+     _sc->sh->hal_ops.rc_ht_sta_current_rate_is_cck(_sta)
+#define HAL_LOAD_FW_ENABLE_MCU(_sh) _sh->hal_ops.load_fw_enable_mcu(_sh)
+#define HAL_LOAD_FW_DISABLE_MCU(_sh) _sh->hal_ops.load_fw_disable_mcu(_sh)
+#define HAL_LOAD_FW_SET_STATUS(_sh,_status) \
+           _sh->hal_ops.load_fw_set_status(_sh, _status)
+#define HAL_LOAD_FW_GET_STATUS(_sh,_status) \
+           _sh->hal_ops.load_fw_get_status(_sh, _status)
+#define HAL_LOAD_FW_PRE_CONFIG_DEVICE(_sh) \
+           _sh->hal_ops.load_fw_pre_config_device(_sh)
+#define HAL_LOAD_FW_POST_CONFIG_DEVICE(_sh) \
+           _sh->hal_ops.load_fw_post_config_device(_sh)
+#define HAL_RESET_CPU(_sh) _sh->hal_ops.reset_cpu(_sh)
+#define HAL_SET_SRAM_MODE(_sh,_mode) _sh->hal_ops.set_sram_mode(_sh, _mode)
+#define HAL_ENABLE_USB_ACC(_sc,_epnum) _sc->sh->hal_ops.enable_usb_acc(_sc, _epnum)
+#define HAL_DISABLE_USB_ACC(_sc,_epnum) _sc->sh->hal_ops.disable_usb_acc(_sc, _epnum)
+#define HAL_SET_USB_LPM(_sc,_enable) _sc->sh->hal_ops.set_usb_lpm(_sc, _enable)
+#define HAL_JUMP_TO_ROM(_sc) _sc->sh->hal_ops.jump_to_rom(_sc)
+#define HAL_GET_FW_NAME(_sh,_name) _sh->hal_ops.get_fw_name(_name)
+#define HAL_SEND_TX_POLL_CMD(_sh,_type) _sh->hal_ops.send_tx_poll_cmd(_sh, _type)
+#define HAL_FLASH_READ_ALL_MAP(_sh) _sh->hal_ops.flash_read_all_map(_sh)
+#define HAL_WAIT_USB_ROM_READY(_sh) _sh->hal_ops.wait_usb_rom_ready(_sh)
+#define HAL_DETACH_USB_HCI(_sh) _sh->hal_ops.detach_usb_hci(_sh)
+#define HAL_ADD_TXINFO(_sc,_skb) _sc->sh->hal_ops.add_txinfo( _sc, _skb)
+#define HAL_UPDATE_TXINFO(_sc,_skb) _sc->sh->hal_ops.update_txinfo( _sc, _skb)
+#define HAL_UPDATE_AMPDU_TXINFO(_sc,_skb) \
+                                       _sc->sh->hal_ops.update_ampdu_txinfo( _sc, _skb)
+#define HAL_ADD_AMPDU_TXINFO(_sc,_skb) \
+                                       _sc->sh->hal_ops.add_ampdu_txinfo( _sc, _skb)
+#define HAL_UPDATE_NULL_FUNC_TXINFO(_sc,_sta,_skb) \
+                                       _sc->sh->hal_ops.update_null_func_txinfo( _sc, _sta, _skb)
+#define HAL_GET_TX_DESC_SIZE(_sh) _sh->hal_ops.get_tx_desc_size(_sh)
+#define HAL_GET_TX_DESC_CTYPE(_sh,_skb) \
+                                       _sh->hal_ops.get_tx_desc_ctype(_skb)
+#define HAL_GET_TX_DESC_REASON(_sh,_skb) \
+                                       _sh->hal_ops.get_tx_desc_reason(_skb)
+#define HAL_GET_TX_DESC_TXQ_IDX(_sh,_skb) \
+                                       _sh->hal_ops.get_tx_desc_txq_idx(_skb)
+#define HAL_TX_RATE_UPDATE(_sc,_skb) _sc->sh->hal_ops.tx_rate_update( _sc, _skb)
+#define HAL_TXTPUT_SET_DESC(_sh,_skb) _sh->hal_ops.txtput_set_desc( _sh, _skb)
+#define HAL_FILL_BEACON_TX_DESC(_sc,_skb) \
+                _sc->sh->hal_ops.fill_beacon_tx_desc(_sc, _skb)
+#define HAL_FILL_LPBK_TX_DESC(_sc,_skb,_sec,_rate) \
+                _sc->sh->hal_ops.fill_lpbk_tx_desc(_skb, _sec, _rate)
+#define HAL_CHK_LPBK_RX_RATE_DESC(_sh,_skb) \
+                                       _sh->hal_ops.chk_lpbk_rx_rate_desc(_sh, _skb)
+#define HAL_GET_SEC_DECODE_ERR(_sh,_skb,_mic_err,_decode_err) \
+                                       _sh->hal_ops.get_sec_decode_err(_skb, _mic_err, _decode_err)
+#define HAL_GET_RX_DESC_SIZE(_sh) _sh->hal_ops.get_rx_desc_size(_sh)
+#define HAL_GET_RX_DESC_LENGTH(_sh) _sh->hal_ops.get_rx_desc_length(_sh)
+#define HAL_GET_RX_DESC_WSID(_sh,_skb) \
+                                       _sh->hal_ops.get_rx_desc_wsid( _skb)
+#define HAL_GET_RX_DESC_RATE_IDX(_sh,_skb) \
+                                       _sh->hal_ops.get_rx_desc_rate_idx( _skb)
+#define HAL_GET_RX_DESC_MNG_USED(_sh,_skb) \
+                                       _sh->hal_ops.get_rx_desc_mng_used( _skb)
+#define HAL_IS_RX_AGGR(_sh,_skb) _sh->hal_ops.is_rx_aggr( _skb)
+#define HAL_GET_RX_DESC_CTYPE(_sh,_skb) \
+                                       _sh->hal_ops.get_rx_desc_ctype( _skb)
+#define HAL_GET_RX_DESC_HDR_OFFSET(_sh,_skb) \
+                                       _sh->hal_ops.get_rx_desc_hdr_offset( _skb)
+#define HAL_GET_RX_DESC_INFO(_sh,_skb,_packet_len,_c_type,_tx_pkt_run_no) \
+                _sh->hal_ops.get_rx_desc_info( _skb, _packet_len, _c_type, _tx_pkt_run_no)
+#define HAL_NULLFUN_FRAME_FILTER(_sh,_skb) \
+                _sh->hal_ops.nullfun_frame_filter(_skb)
+#define HAL_SET_PHY_MODE(_sh,_val) _sh->hal_ops.set_phy_mode(_sh, _val)
+#define HAL_PHY_ENABLE(_sh,_val) _sh->hal_ops.phy_enable(_sh, _val)
+#define HAL_EDCA_ENABLE(_sh,_val) _sh->hal_ops.edca_enable(_sh, _val)
+#define HAL_EDCA_STAT(_sh) _sh->hal_ops.edca_stat(_sh)
+#define HAL_RESET_MIB_PHY(_sh) _sh->hal_ops.reset_mib_phy(_sh)
+#define HAL_DUMP_MIB_RX_PHY(_sh) \
+                _sh->hal_ops.dump_mib_rx_phy(_sh)
+#define HAL_RC_MAC80211_RATE_IDX(_sc,_rate_idx,_rxs) \
+                _sc->sh->hal_ops.rc_mac80211_rate_idx(_sc, _rate_idx, _rxs)
+#define HAL_UPDATE_RXSTATUS(_sc,_skb,_rxs) \
+                _sc->sh->hal_ops.update_rxstatus(_sc, _skb, _rxs)
+#ifdef CONFIG_SSV_CCI_IMPROVEMENT
+#define HAL_UPDATE_SCAN_CCI_SETTING(_sc) _sc->sh->hal_ops.update_scan_cci_setting(_sc)
+#define HAL_RECOVERY_SCAN_CCI_SETTING(_sc) _sc->sh->hal_ops.recover_scan_cci_setting(_sc)
+#endif
+#define HAL_CMD_RC(_sh,_argc,_argv) _sh->hal_ops.cmd_rc(_sh, _argc, _argv)
+#define HAL_CMD_EFUSE(_sh,_argc,_argv) _sh->hal_ops.cmd_efuse(_sh, _argc, _argv)
+#define HAL_CMD_SPECTRUM(_sh) _sh->hal_ops.cmd_spectrum(_sh)
+#define HAL_CMD_LOOPBACK(_sh,_argc,_argv) _sh->hal_ops.cmd_loopback(_sh, _argc, _argv)
+#define HAL_CMD_LOOPBACK_START(_sh) _sh->hal_ops.cmd_loopback_start(_sh)
+#define HAL_CMD_LOOPBACK_SETUP_ENV(_sh) _sh->hal_ops.cmd_loopback_setup_env(_sh)
+#define HAL_CMD_HWINFO(_sh,_argc,_argv) _sh->hal_ops.cmd_hwinfo(_sh, _argc, _argv)
+#define HAL_CMD_CCI(_sh,_argc,_argv) _sh->hal_ops.cmd_cci(_sh, _argc, _argv)
+#define HAL_CMD_TXGEN(_sh) _sh->hal_ops.cmd_txgen(_sh)
+#define HAL_CMD_RF(_sh,_argc,_argv) _sh->hal_ops.cmd_rf(_sh, _argc, _argv)
+#define HAL_UPDATE_RF_PWR(_sc) _sc->sh->hal_ops.update_rf_pwr(_sc)
+#define HAL_CMD_HWQ_LIMIT(_sh,_argc,_argv) _sh->hal_ops.cmd_hwq_limit(_sh, _argc, _argv)
+#define HAL_AMPDU_RX_START(_sc,_hw,_vif,_sta,_tid,_ssn,_buf_size) \
+                _sc->sh->hal_ops.ampdu_rx_start(_hw, _vif, _sta, _tid, _ssn, _buf_size)
+#define HAL_AMPDU_BA_HANDLER(_sc,_hw,_skb,_tx_pkt_run_no) \
+                _sc->sh->hal_ops.ampdu_ba_handler( _hw, _skb, _tx_pkt_run_no)
+#define HAL_IS_LEGACY_RATE(_sc,_skb) _sc->sh->hal_ops.is_legacy_rate(_sc, _skb)
+#define HAL_AMPDU_MAX_TRANSMIT_LENGTH(_sc,_skb,_rate_idx) \
+    _sc->sh->hal_ops.ampdu_max_transmit_length(_sc, _skb, _rate_idx)
+#define HAL_LOAD_PHY_TABLE(_sh,_tbl) _sh->hal_ops.load_phy_table(_tbl)
+#define HAL_GET_PHY_TABLE_SIZE(_sh) _sh->hal_ops.get_phy_table_size(_sh)
+#define HAL_LOAD_RF_TABLE(_sh,_tbl) _sh->hal_ops.load_rf_table(_tbl)
+#define HAL_GET_RF_TABLE_SIZE(_sh) _sh->hal_ops.get_rf_table_size(_sh)
+#define HAL_INIT_PLL(_sh) _sh->hal_ops.init_pll(_sh)
+#define HAL_UPDATE_CFG_HW_PATCH(_sh,_rftbl,_phytbl) \
+                                       _sh->hal_ops.update_cfg_hw_patch(_sh, _rftbl, _phytbl)
+#define HAL_UPDATE_HW_CONFIG(_sh,_rftbl,_phytbl) \
+                                       _sh->hal_ops.update_hw_config(_sh, _rftbl, _phytbl)
+#define HAL_CHG_PAD_SETTING(_sh) _sh->hal_ops.chg_pad_setting(_sh)
+#define HAL_CHG_CLK_SRC(_sh) _sh->hal_ops.chg_clk_src(_sh)
+#define HAL_UPDATE_EFUSE_SETTING(_sh) _sh->hal_ops.update_efuse_setting(_sh)
+#define HAL_DO_TEMPERATURE_COMPENSATION(_sh) \
+                                       _sh->hal_ops.do_temperature_compensation(_sh)
+#define HAL_UPDATE_PRODUCT_HW_SETTING(_sh) _sh->hal_ops.update_product_hw_setting(_sh)
+#define HAL_SET_CHANNEL(_sc,_ch,_type) _sc->sh->hal_ops.set_channel(_sc, _ch, _type)
+#define HAL_DO_IQ_CAL(_sh,_pcfg) _sh->hal_ops.do_iq_cal(_sh,_pcfg)
+#define HAL_SET_PLL_PHY_RF(_sh,_rf_tbl,_phy_tbl) \
+                                       _sh->hal_ops.set_pll_phy_rf(_sh, _rf_tbl, _phy_tbl)
+#define HAL_DPD_ENABLE(_sh,_val) _sh->hal_ops.dpd_enable(_sh, _val)
+#define HAL_INIT_CH_CFG(_sh) _sh->hal_ops.init_ch_cfg(_sh)
+#define HAL_SAVE_DEFAULT_IPD_CHCFG(_sh) \
+                                       _sh->hal_ops.save_default_ipd_chcfg(_sh)
+#define HAL_CHG_IPD_PHYINFO(_sh) _sh->hal_ops.chg_ipd_phyinfo(_sh)
+#define HAL_SET_RF_ENABLE(_sh,_val) _sh->hal_ops.set_rf_enable(_sh, _val)
+#define HAL_SET_ON3_ENABLE(_sh,_val) _sh->hal_ops.set_on3_enable(_sh, _val)
+#define HAL_INIT_GPIO_CFG(_sh) _sh->hal_ops.init_gpio_cfg(_sh)
+#endif
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/include/linux_80211.h b/drivers/net/wireless/ssv6x5x/include/linux_80211.h
new file mode 100644
index 000000000..2207d6fc6
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/include/linux_80211.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _LINUX_80211_H_
+#define _LINUX_80211_H_
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,7,0)
+#define INDEX_80211_BAND_2GHZ NL80211_BAND_2GHZ
+#define INDEX_80211_BAND_5GHZ NL80211_BAND_5GHZ
+#define INDEX_80211_BAND_60GHZ NL80211_BAND_60GHZ
+#else
+#define INDEX_80211_BAND_2GHZ IEEE80211_BAND_2GHZ
+#define INDEX_80211_BAND_5GHZ IEEE80211_BAND_5GHZ
+#define INDEX_80211_BAND_60GHZ IEEE80211_BAND_60GHZ
+#endif
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/include/ssv6200.h b/drivers/net/wireless/ssv6x5x/include/ssv6200.h
new file mode 100644
index 000000000..613bee90a
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/include/ssv6200.h
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV6200_H_
+#define _SSV6200_H_
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#ifdef SSV_MAC80211
+#include "ssv_mac80211.h"
+#else
+#include <net/mac80211.h>
+#endif
+#ifdef ECLIPSE
+#include <ssv_mod_conf.h>
+#endif
+#ifndef SSV_SUPPORT_HAL
+#include <ssv6200_reg.h>
+#include <ssv6200_aux.h>
+#endif
+#include <hwif/hwif.h>
+#include <hci/ssv_hci.h>
+#include "ssv6200_common.h"
+#ifdef SSV6200_ECO
+#define SSV6200_TOTAL_PAGE (256)
+#define SSV6200_TOTAL_ID (128)
+#ifndef HUW_DRV
+#define SSV6200_ID_TX_THRESHOLD 19
+#define SSV6200_ID_RX_THRESHOLD 60
+#define SSV6200_RESERVED_PAGE (26)
+#define SSV6200_PAGE_TX_THRESHOLD 115
+#define SSV6200_PAGE_RX_THRESHOLD (SSV6200_TOTAL_PAGE - SSV6200_PAGE_TX_THRESHOLD - SSV6200_RESERVED_PAGE)
+#define SSV6200_AMPDU_DIVIDER (2)
+#define SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER (SSV6200_PAGE_TX_THRESHOLD - (SSV6200_PAGE_TX_THRESHOLD/SSV6200_AMPDU_DIVIDER))
+#define SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER 2
+#else
+#undef SSV6200_ID_TX_THRESHOLD
+#undef SSV6200_ID_RX_THRESHOLD
+#undef SSV6200_PAGE_TX_THRESHOLD
+#undef SSV6200_PAGE_RX_THRESHOLD
+#undef SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER
+#undef SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER
+#define SSV6200_ID_TX_THRESHOLD 31
+#define SSV6200_ID_RX_THRESHOLD 31
+#define SSV6200_PAGE_TX_THRESHOLD 61
+#define SSV6200_PAGE_RX_THRESHOLD 61
+#define SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER 45
+#define SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER 2
+#endif
+#else
+#undef SSV6200_ID_TX_THRESHOLD
+#undef SSV6200_ID_RX_THRESHOLD
+#undef SSV6200_PAGE_TX_THRESHOLD
+#undef SSV6200_PAGE_RX_THRESHOLD
+#undef SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER
+#undef SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER
+#define SSV6200_ID_TX_THRESHOLD 63
+#define SSV6200_ID_RX_THRESHOLD 63
+#ifdef PREFER_RX
+#define SSV6200_PAGE_TX_THRESHOLD (126-24)
+#define SSV6200_PAGE_RX_THRESHOLD (126+24)
+#else
+#undef SSV6200_PAGE_TX_THRESHOLD
+#undef SSV6200_PAGE_RX_THRESHOLD
+#define SSV6200_PAGE_TX_THRESHOLD 126
+#define SSV6200_PAGE_RX_THRESHOLD 126
+#endif
+#define SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER (SSV6200_PAGE_TX_THRESHOLD/2)
+#define SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER 2
+#endif
+#define SSV6200_ID_NUMBER (SSV6200_TOTAL_ID)
+#define PACKET_ADDR_2_ID(addr) ((addr >> 16) & 0x7F)
+#define SSV6200_ID_AC_RESERVED 1
+#define SSV6200_ID_AC_BK_OUT_QUEUE 8
+#define SSV6200_ID_AC_BE_OUT_QUEUE 15
+#define SSV6200_ID_AC_VI_OUT_QUEUE 16
+#define SSV6200_ID_AC_VO_OUT_QUEUE 16
+#define SSV6200_ID_MANAGER_QUEUE 8
+#define HW_MMU_PAGE_SHIFT 0x8
+#define HW_MMU_PAGE_MASK 0xff
+#define SSV6200_BT_PRI_SMP_TIME 0
+#define SSV6200_BT_STA_SMP_TIME (SSV6200_BT_PRI_SMP_TIME+0)
+#define SSV6200_WLAN_REMAIN_TIME 0
+#define BT_2WIRE_EN_MSK 0x00000400
+struct txResourceControl {
+    u32 txUsePage:8;
+    u32 txUseID:6;
+    u32 edca0:4;
+    u32 edca1:4;
+    u32 edca2:5;
+    u32 edca3:5;
+};
+#define SSV_SKB_info_size (sizeof(struct SKB_info_st))
+#include "ssv_cfg.h"
+static inline void txrxboost_init(void)
+{
+    struct sched_param param = { .sched_priority = 0 };
+    sched_setscheduler(current, SCHED_NORMAL, &param);
+}
+static inline void txrxboost_change(u32 tx_frame_qlen, u32 low_threshold, u32 high_threshold, u32 prio)
+{
+    struct sched_param param;
+    if (tx_frame_qlen > high_threshold) {
+        param.sched_priority = (int)prio;
+        sched_setscheduler(current, (prio != 0)?SCHED_RR:SCHED_NORMAL, &param);
+    } else if (tx_frame_qlen < low_threshold) {
+        param.sched_priority = 0;
+        sched_setscheduler(current, SCHED_NORMAL, &param);
+    }
+}
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/include/ssv6200_aux.h b/drivers/net/wireless/ssv6x5x/include/ssv6200_aux.h
new file mode 100644
index 000000000..30ed7e97c
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/include/ssv6200_aux.h
@@ -0,0 +1,18220 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define MCU_ENABLE_MSK 0x00000001
+#define MCU_ENABLE_I_MSK 0xfffffffe
+#define MCU_ENABLE_SFT 0
+#define MCU_ENABLE_HI 0
+#define MCU_ENABLE_SZ 1
+#define MAC_SW_RST_MSK 0x00000002
+#define MAC_SW_RST_I_MSK 0xfffffffd
+#define MAC_SW_RST_SFT 1
+#define MAC_SW_RST_HI 1
+#define MAC_SW_RST_SZ 1
+#define MCU_SW_RST_MSK 0x00000004
+#define MCU_SW_RST_I_MSK 0xfffffffb
+#define MCU_SW_RST_SFT 2
+#define MCU_SW_RST_HI 2
+#define MCU_SW_RST_SZ 1
+#define SDIO_SW_RST_MSK 0x00000008
+#define SDIO_SW_RST_I_MSK 0xfffffff7
+#define SDIO_SW_RST_SFT 3
+#define SDIO_SW_RST_HI 3
+#define SDIO_SW_RST_SZ 1
+#define SPI_SLV_SW_RST_MSK 0x00000010
+#define SPI_SLV_SW_RST_I_MSK 0xffffffef
+#define SPI_SLV_SW_RST_SFT 4
+#define SPI_SLV_SW_RST_HI 4
+#define SPI_SLV_SW_RST_SZ 1
+#define UART_SW_RST_MSK 0x00000020
+#define UART_SW_RST_I_MSK 0xffffffdf
+#define UART_SW_RST_SFT 5
+#define UART_SW_RST_HI 5
+#define UART_SW_RST_SZ 1
+#define DMA_SW_RST_MSK 0x00000040
+#define DMA_SW_RST_I_MSK 0xffffffbf
+#define DMA_SW_RST_SFT 6
+#define DMA_SW_RST_HI 6
+#define DMA_SW_RST_SZ 1
+#define WDT_SW_RST_MSK 0x00000080
+#define WDT_SW_RST_I_MSK 0xffffff7f
+#define WDT_SW_RST_SFT 7
+#define WDT_SW_RST_HI 7
+#define WDT_SW_RST_SZ 1
+#define I2C_SLV_SW_RST_MSK 0x00000100
+#define I2C_SLV_SW_RST_I_MSK 0xfffffeff
+#define I2C_SLV_SW_RST_SFT 8
+#define I2C_SLV_SW_RST_HI 8
+#define I2C_SLV_SW_RST_SZ 1
+#define INT_CTL_SW_RST_MSK 0x00000200
+#define INT_CTL_SW_RST_I_MSK 0xfffffdff
+#define INT_CTL_SW_RST_SFT 9
+#define INT_CTL_SW_RST_HI 9
+#define INT_CTL_SW_RST_SZ 1
+#define BTCX_SW_RST_MSK 0x00000400
+#define BTCX_SW_RST_I_MSK 0xfffffbff
+#define BTCX_SW_RST_SFT 10
+#define BTCX_SW_RST_HI 10
+#define BTCX_SW_RST_SZ 1
+#define GPIO_SW_RST_MSK 0x00000800
+#define GPIO_SW_RST_I_MSK 0xfffff7ff
+#define GPIO_SW_RST_SFT 11
+#define GPIO_SW_RST_HI 11
+#define GPIO_SW_RST_SZ 1
+#define US0TMR_SW_RST_MSK 0x00001000
+#define US0TMR_SW_RST_I_MSK 0xffffefff
+#define US0TMR_SW_RST_SFT 12
+#define US0TMR_SW_RST_HI 12
+#define US0TMR_SW_RST_SZ 1
+#define US1TMR_SW_RST_MSK 0x00002000
+#define US1TMR_SW_RST_I_MSK 0xffffdfff
+#define US1TMR_SW_RST_SFT 13
+#define US1TMR_SW_RST_HI 13
+#define US1TMR_SW_RST_SZ 1
+#define US2TMR_SW_RST_MSK 0x00004000
+#define US2TMR_SW_RST_I_MSK 0xffffbfff
+#define US2TMR_SW_RST_SFT 14
+#define US2TMR_SW_RST_HI 14
+#define US2TMR_SW_RST_SZ 1
+#define US3TMR_SW_RST_MSK 0x00008000
+#define US3TMR_SW_RST_I_MSK 0xffff7fff
+#define US3TMR_SW_RST_SFT 15
+#define US3TMR_SW_RST_HI 15
+#define US3TMR_SW_RST_SZ 1
+#define MS0TMR_SW_RST_MSK 0x00010000
+#define MS0TMR_SW_RST_I_MSK 0xfffeffff
+#define MS0TMR_SW_RST_SFT 16
+#define MS0TMR_SW_RST_HI 16
+#define MS0TMR_SW_RST_SZ 1
+#define MS1TMR_SW_RST_MSK 0x00020000
+#define MS1TMR_SW_RST_I_MSK 0xfffdffff
+#define MS1TMR_SW_RST_SFT 17
+#define MS1TMR_SW_RST_HI 17
+#define MS1TMR_SW_RST_SZ 1
+#define MS2TMR_SW_RST_MSK 0x00040000
+#define MS2TMR_SW_RST_I_MSK 0xfffbffff
+#define MS2TMR_SW_RST_SFT 18
+#define MS2TMR_SW_RST_HI 18
+#define MS2TMR_SW_RST_SZ 1
+#define MS3TMR_SW_RST_MSK 0x00080000
+#define MS3TMR_SW_RST_I_MSK 0xfff7ffff
+#define MS3TMR_SW_RST_SFT 19
+#define MS3TMR_SW_RST_HI 19
+#define MS3TMR_SW_RST_SZ 1
+#define RF_BB_SW_RST_MSK 0x00100000
+#define RF_BB_SW_RST_I_MSK 0xffefffff
+#define RF_BB_SW_RST_SFT 20
+#define RF_BB_SW_RST_HI 20
+#define RF_BB_SW_RST_SZ 1
+#define SYS_ALL_RST_MSK 0x00200000
+#define SYS_ALL_RST_I_MSK 0xffdfffff
+#define SYS_ALL_RST_SFT 21
+#define SYS_ALL_RST_HI 21
+#define SYS_ALL_RST_SZ 1
+#define DAT_UART_SW_RST_MSK 0x00400000
+#define DAT_UART_SW_RST_I_MSK 0xffbfffff
+#define DAT_UART_SW_RST_SFT 22
+#define DAT_UART_SW_RST_HI 22
+#define DAT_UART_SW_RST_SZ 1
+#define I2C_MST_SW_RST_MSK 0x00800000
+#define I2C_MST_SW_RST_I_MSK 0xff7fffff
+#define I2C_MST_SW_RST_SFT 23
+#define I2C_MST_SW_RST_HI 23
+#define I2C_MST_SW_RST_SZ 1
+#define RG_REBOOT_MSK 0x00000001
+#define RG_REBOOT_I_MSK 0xfffffffe
+#define RG_REBOOT_SFT 0
+#define RG_REBOOT_HI 0
+#define RG_REBOOT_SZ 1
+#define TRAP_IMG_FLS_MSK 0x00010000
+#define TRAP_IMG_FLS_I_MSK 0xfffeffff
+#define TRAP_IMG_FLS_SFT 16
+#define TRAP_IMG_FLS_HI 16
+#define TRAP_IMG_FLS_SZ 1
+#define TRAP_REBOOT_MSK 0x00020000
+#define TRAP_REBOOT_I_MSK 0xfffdffff
+#define TRAP_REBOOT_SFT 17
+#define TRAP_REBOOT_HI 17
+#define TRAP_REBOOT_SZ 1
+#define TRAP_BOOT_FLS_MSK 0x00040000
+#define TRAP_BOOT_FLS_I_MSK 0xfffbffff
+#define TRAP_BOOT_FLS_SFT 18
+#define TRAP_BOOT_FLS_HI 18
+#define TRAP_BOOT_FLS_SZ 1
+#define CHIP_ID_31_0_MSK 0xffffffff
+#define CHIP_ID_31_0_I_MSK 0x00000000
+#define CHIP_ID_31_0_SFT 0
+#define CHIP_ID_31_0_HI 31
+#define CHIP_ID_31_0_SZ 32
+#define CHIP_ID_63_32_MSK 0xffffffff
+#define CHIP_ID_63_32_I_MSK 0x00000000
+#define CHIP_ID_63_32_SFT 0
+#define CHIP_ID_63_32_HI 31
+#define CHIP_ID_63_32_SZ 32
+#define CHIP_ID_95_64_MSK 0xffffffff
+#define CHIP_ID_95_64_I_MSK 0x00000000
+#define CHIP_ID_95_64_SFT 0
+#define CHIP_ID_95_64_HI 31
+#define CHIP_ID_95_64_SZ 32
+#define CHIP_ID_127_96_MSK 0xffffffff
+#define CHIP_ID_127_96_I_MSK 0x00000000
+#define CHIP_ID_127_96_SFT 0
+#define CHIP_ID_127_96_HI 31
+#define CHIP_ID_127_96_SZ 32
+#define CK_SEL_1_0_MSK 0x00000003
+#define CK_SEL_1_0_I_MSK 0xfffffffc
+#define CK_SEL_1_0_SFT 0
+#define CK_SEL_1_0_HI 1
+#define CK_SEL_1_0_SZ 2
+#define CK_SEL_2_MSK 0x00000004
+#define CK_SEL_2_I_MSK 0xfffffffb
+#define CK_SEL_2_SFT 2
+#define CK_SEL_2_HI 2
+#define CK_SEL_2_SZ 1
+#define SYS_CLK_EN_MSK 0x00000001
+#define SYS_CLK_EN_I_MSK 0xfffffffe
+#define SYS_CLK_EN_SFT 0
+#define SYS_CLK_EN_HI 0
+#define SYS_CLK_EN_SZ 1
+#define MAC_CLK_EN_MSK 0x00000002
+#define MAC_CLK_EN_I_MSK 0xfffffffd
+#define MAC_CLK_EN_SFT 1
+#define MAC_CLK_EN_HI 1
+#define MAC_CLK_EN_SZ 1
+#define MCU_CLK_EN_MSK 0x00000004
+#define MCU_CLK_EN_I_MSK 0xfffffffb
+#define MCU_CLK_EN_SFT 2
+#define MCU_CLK_EN_HI 2
+#define MCU_CLK_EN_SZ 1
+#define SDIO_CLK_EN_MSK 0x00000008
+#define SDIO_CLK_EN_I_MSK 0xfffffff7
+#define SDIO_CLK_EN_SFT 3
+#define SDIO_CLK_EN_HI 3
+#define SDIO_CLK_EN_SZ 1
+#define SPI_SLV_CLK_EN_MSK 0x00000010
+#define SPI_SLV_CLK_EN_I_MSK 0xffffffef
+#define SPI_SLV_CLK_EN_SFT 4
+#define SPI_SLV_CLK_EN_HI 4
+#define SPI_SLV_CLK_EN_SZ 1
+#define UART_CLK_EN_MSK 0x00000020
+#define UART_CLK_EN_I_MSK 0xffffffdf
+#define UART_CLK_EN_SFT 5
+#define UART_CLK_EN_HI 5
+#define UART_CLK_EN_SZ 1
+#define DMA_CLK_EN_MSK 0x00000040
+#define DMA_CLK_EN_I_MSK 0xffffffbf
+#define DMA_CLK_EN_SFT 6
+#define DMA_CLK_EN_HI 6
+#define DMA_CLK_EN_SZ 1
+#define WDT_CLK_EN_MSK 0x00000080
+#define WDT_CLK_EN_I_MSK 0xffffff7f
+#define WDT_CLK_EN_SFT 7
+#define WDT_CLK_EN_HI 7
+#define WDT_CLK_EN_SZ 1
+#define I2C_SLV_CLK_EN_MSK 0x00000100
+#define I2C_SLV_CLK_EN_I_MSK 0xfffffeff
+#define I2C_SLV_CLK_EN_SFT 8
+#define I2C_SLV_CLK_EN_HI 8
+#define I2C_SLV_CLK_EN_SZ 1
+#define INT_CTL_CLK_EN_MSK 0x00000200
+#define INT_CTL_CLK_EN_I_MSK 0xfffffdff
+#define INT_CTL_CLK_EN_SFT 9
+#define INT_CTL_CLK_EN_HI 9
+#define INT_CTL_CLK_EN_SZ 1
+#define BTCX_CLK_EN_MSK 0x00000400
+#define BTCX_CLK_EN_I_MSK 0xfffffbff
+#define BTCX_CLK_EN_SFT 10
+#define BTCX_CLK_EN_HI 10
+#define BTCX_CLK_EN_SZ 1
+#define GPIO_CLK_EN_MSK 0x00000800
+#define GPIO_CLK_EN_I_MSK 0xfffff7ff
+#define GPIO_CLK_EN_SFT 11
+#define GPIO_CLK_EN_HI 11
+#define GPIO_CLK_EN_SZ 1
+#define US0TMR_CLK_EN_MSK 0x00001000
+#define US0TMR_CLK_EN_I_MSK 0xffffefff
+#define US0TMR_CLK_EN_SFT 12
+#define US0TMR_CLK_EN_HI 12
+#define US0TMR_CLK_EN_SZ 1
+#define US1TMR_CLK_EN_MSK 0x00002000
+#define US1TMR_CLK_EN_I_MSK 0xffffdfff
+#define US1TMR_CLK_EN_SFT 13
+#define US1TMR_CLK_EN_HI 13
+#define US1TMR_CLK_EN_SZ 1
+#define US2TMR_CLK_EN_MSK 0x00004000
+#define US2TMR_CLK_EN_I_MSK 0xffffbfff
+#define US2TMR_CLK_EN_SFT 14
+#define US2TMR_CLK_EN_HI 14
+#define US2TMR_CLK_EN_SZ 1
+#define US3TMR_CLK_EN_MSK 0x00008000
+#define US3TMR_CLK_EN_I_MSK 0xffff7fff
+#define US3TMR_CLK_EN_SFT 15
+#define US3TMR_CLK_EN_HI 15
+#define US3TMR_CLK_EN_SZ 1
+#define MS0TMR_CLK_EN_MSK 0x00010000
+#define MS0TMR_CLK_EN_I_MSK 0xfffeffff
+#define MS0TMR_CLK_EN_SFT 16
+#define MS0TMR_CLK_EN_HI 16
+#define MS0TMR_CLK_EN_SZ 1
+#define MS1TMR_CLK_EN_MSK 0x00020000
+#define MS1TMR_CLK_EN_I_MSK 0xfffdffff
+#define MS1TMR_CLK_EN_SFT 17
+#define MS1TMR_CLK_EN_HI 17
+#define MS1TMR_CLK_EN_SZ 1
+#define MS2TMR_CLK_EN_MSK 0x00040000
+#define MS2TMR_CLK_EN_I_MSK 0xfffbffff
+#define MS2TMR_CLK_EN_SFT 18
+#define MS2TMR_CLK_EN_HI 18
+#define MS2TMR_CLK_EN_SZ 1
+#define MS3TMR_CLK_EN_MSK 0x00080000
+#define MS3TMR_CLK_EN_I_MSK 0xfff7ffff
+#define MS3TMR_CLK_EN_SFT 19
+#define MS3TMR_CLK_EN_HI 19
+#define MS3TMR_CLK_EN_SZ 1
+#define BIST_CLK_EN_MSK 0x00100000
+#define BIST_CLK_EN_I_MSK 0xffefffff
+#define BIST_CLK_EN_SFT 20
+#define BIST_CLK_EN_HI 20
+#define BIST_CLK_EN_SZ 1
+#define I2C_MST_CLK_EN_MSK 0x00800000
+#define I2C_MST_CLK_EN_I_MSK 0xff7fffff
+#define I2C_MST_CLK_EN_SFT 23
+#define I2C_MST_CLK_EN_HI 23
+#define I2C_MST_CLK_EN_SZ 1
+#define BTCX_CSR_CLK_EN_MSK 0x00000400
+#define BTCX_CSR_CLK_EN_I_MSK 0xfffffbff
+#define BTCX_CSR_CLK_EN_SFT 10
+#define BTCX_CSR_CLK_EN_HI 10
+#define BTCX_CSR_CLK_EN_SZ 1
+#define MCU_DBG_SEL_MSK 0x0000003f
+#define MCU_DBG_SEL_I_MSK 0xffffffc0
+#define MCU_DBG_SEL_SFT 0
+#define MCU_DBG_SEL_HI 5
+#define MCU_DBG_SEL_SZ 6
+#define MCU_STOP_NOGRANT_MSK 0x00000100
+#define MCU_STOP_NOGRANT_I_MSK 0xfffffeff
+#define MCU_STOP_NOGRANT_SFT 8
+#define MCU_STOP_NOGRANT_HI 8
+#define MCU_STOP_NOGRANT_SZ 1
+#define MCU_STOP_ANYTIME_MSK 0x00000200
+#define MCU_STOP_ANYTIME_I_MSK 0xfffffdff
+#define MCU_STOP_ANYTIME_SFT 9
+#define MCU_STOP_ANYTIME_HI 9
+#define MCU_STOP_ANYTIME_SZ 1
+#define MCU_DBG_DATA_MSK 0xffffffff
+#define MCU_DBG_DATA_I_MSK 0x00000000
+#define MCU_DBG_DATA_SFT 0
+#define MCU_DBG_DATA_HI 31
+#define MCU_DBG_DATA_SZ 32
+#define AHB_SW_RST_MSK 0x00000001
+#define AHB_SW_RST_I_MSK 0xfffffffe
+#define AHB_SW_RST_SFT 0
+#define AHB_SW_RST_HI 0
+#define AHB_SW_RST_SZ 1
+#define AHB_ERR_RST_MSK 0x00000002
+#define AHB_ERR_RST_I_MSK 0xfffffffd
+#define AHB_ERR_RST_SFT 1
+#define AHB_ERR_RST_HI 1
+#define AHB_ERR_RST_SZ 1
+#define REG_AHB_DEBUG_MX_MSK 0x00000030
+#define REG_AHB_DEBUG_MX_I_MSK 0xffffffcf
+#define REG_AHB_DEBUG_MX_SFT 4
+#define REG_AHB_DEBUG_MX_HI 5
+#define REG_AHB_DEBUG_MX_SZ 2
+#define REG_PKT_W_NBRT_MSK 0x00000100
+#define REG_PKT_W_NBRT_I_MSK 0xfffffeff
+#define REG_PKT_W_NBRT_SFT 8
+#define REG_PKT_W_NBRT_HI 8
+#define REG_PKT_W_NBRT_SZ 1
+#define REG_PKT_R_NBRT_MSK 0x00000200
+#define REG_PKT_R_NBRT_I_MSK 0xfffffdff
+#define REG_PKT_R_NBRT_SFT 9
+#define REG_PKT_R_NBRT_HI 9
+#define REG_PKT_R_NBRT_SZ 1
+#define IQ_SRAM_SEL_0_MSK 0x00001000
+#define IQ_SRAM_SEL_0_I_MSK 0xffffefff
+#define IQ_SRAM_SEL_0_SFT 12
+#define IQ_SRAM_SEL_0_HI 12
+#define IQ_SRAM_SEL_0_SZ 1
+#define IQ_SRAM_SEL_1_MSK 0x00002000
+#define IQ_SRAM_SEL_1_I_MSK 0xffffdfff
+#define IQ_SRAM_SEL_1_SFT 13
+#define IQ_SRAM_SEL_1_HI 13
+#define IQ_SRAM_SEL_1_SZ 1
+#define IQ_SRAM_SEL_2_MSK 0x00004000
+#define IQ_SRAM_SEL_2_I_MSK 0xffffbfff
+#define IQ_SRAM_SEL_2_SFT 14
+#define IQ_SRAM_SEL_2_HI 14
+#define IQ_SRAM_SEL_2_SZ 1
+#define AHB_STATUS_MSK 0xffff0000
+#define AHB_STATUS_I_MSK 0x0000ffff
+#define AHB_STATUS_SFT 16
+#define AHB_STATUS_HI 31
+#define AHB_STATUS_SZ 16
+#define PARALLEL_DR_MSK 0x00000001
+#define PARALLEL_DR_I_MSK 0xfffffffe
+#define PARALLEL_DR_SFT 0
+#define PARALLEL_DR_HI 0
+#define PARALLEL_DR_SZ 1
+#define MBRUN_MSK 0x00000010
+#define MBRUN_I_MSK 0xffffffef
+#define MBRUN_SFT 4
+#define MBRUN_HI 4
+#define MBRUN_SZ 1
+#define SHIFT_DR_MSK 0x00000100
+#define SHIFT_DR_I_MSK 0xfffffeff
+#define SHIFT_DR_SFT 8
+#define SHIFT_DR_HI 8
+#define SHIFT_DR_SZ 1
+#define MODE_REG_SI_MSK 0x00000200
+#define MODE_REG_SI_I_MSK 0xfffffdff
+#define MODE_REG_SI_SFT 9
+#define MODE_REG_SI_HI 9
+#define MODE_REG_SI_SZ 1
+#define SIMULATION_MODE_MSK 0x00000400
+#define SIMULATION_MODE_I_MSK 0xfffffbff
+#define SIMULATION_MODE_SFT 10
+#define SIMULATION_MODE_HI 10
+#define SIMULATION_MODE_SZ 1
+#define DBIST_MODE_MSK 0x00000800
+#define DBIST_MODE_I_MSK 0xfffff7ff
+#define DBIST_MODE_SFT 11
+#define DBIST_MODE_HI 11
+#define DBIST_MODE_SZ 1
+#define MODE_REG_IN_MSK 0x001fffff
+#define MODE_REG_IN_I_MSK 0xffe00000
+#define MODE_REG_IN_SFT 0
+#define MODE_REG_IN_HI 20
+#define MODE_REG_IN_SZ 21
+#define MODE_REG_OUT_MCU_MSK 0x001fffff
+#define MODE_REG_OUT_MCU_I_MSK 0xffe00000
+#define MODE_REG_OUT_MCU_SFT 0
+#define MODE_REG_OUT_MCU_HI 20
+#define MODE_REG_OUT_MCU_SZ 21
+#define MODE_REG_SO_MCU_MSK 0x80000000
+#define MODE_REG_SO_MCU_I_MSK 0x7fffffff
+#define MODE_REG_SO_MCU_SFT 31
+#define MODE_REG_SO_MCU_HI 31
+#define MODE_REG_SO_MCU_SZ 1
+#define MONITOR_BUS_MCU_31_0_MSK 0xffffffff
+#define MONITOR_BUS_MCU_31_0_I_MSK 0x00000000
+#define MONITOR_BUS_MCU_31_0_SFT 0
+#define MONITOR_BUS_MCU_31_0_HI 31
+#define MONITOR_BUS_MCU_31_0_SZ 32
+#define MONITOR_BUS_MCU_33_32_MSK 0x00000003
+#define MONITOR_BUS_MCU_33_32_I_MSK 0xfffffffc
+#define MONITOR_BUS_MCU_33_32_SFT 0
+#define MONITOR_BUS_MCU_33_32_HI 1
+#define MONITOR_BUS_MCU_33_32_SZ 2
+#define TB_ADR_SEL_MSK 0x0000ffff
+#define TB_ADR_SEL_I_MSK 0xffff0000
+#define TB_ADR_SEL_SFT 0
+#define TB_ADR_SEL_HI 15
+#define TB_ADR_SEL_SZ 16
+#define TB_CS_MSK 0x80000000
+#define TB_CS_I_MSK 0x7fffffff
+#define TB_CS_SFT 31
+#define TB_CS_HI 31
+#define TB_CS_SZ 1
+#define TB_RDATA_MSK 0xffffffff
+#define TB_RDATA_I_MSK 0x00000000
+#define TB_RDATA_SFT 0
+#define TB_RDATA_HI 31
+#define TB_RDATA_SZ 32
+#define UART_W2B_EN_MSK 0x00000001
+#define UART_W2B_EN_I_MSK 0xfffffffe
+#define UART_W2B_EN_SFT 0
+#define UART_W2B_EN_HI 0
+#define UART_W2B_EN_SZ 1
+#define DATA_UART_W2B_EN_MSK 0x00000010
+#define DATA_UART_W2B_EN_I_MSK 0xffffffef
+#define DATA_UART_W2B_EN_SFT 4
+#define DATA_UART_W2B_EN_HI 4
+#define DATA_UART_W2B_EN_SZ 1
+#define AHB_ILL_ADDR_MSK 0xffffffff
+#define AHB_ILL_ADDR_I_MSK 0x00000000
+#define AHB_ILL_ADDR_SFT 0
+#define AHB_ILL_ADDR_HI 31
+#define AHB_ILL_ADDR_SZ 32
+#define AHB_FEN_ADDR_MSK 0xffffffff
+#define AHB_FEN_ADDR_I_MSK 0x00000000
+#define AHB_FEN_ADDR_SFT 0
+#define AHB_FEN_ADDR_HI 31
+#define AHB_FEN_ADDR_SZ 32
+#define ILL_ADDR_CLR_MSK 0x00000001
+#define ILL_ADDR_CLR_I_MSK 0xfffffffe
+#define ILL_ADDR_CLR_SFT 0
+#define ILL_ADDR_CLR_HI 0
+#define ILL_ADDR_CLR_SZ 1
+#define FENCE_HIT_CLR_MSK 0x00000002
+#define FENCE_HIT_CLR_I_MSK 0xfffffffd
+#define FENCE_HIT_CLR_SFT 1
+#define FENCE_HIT_CLR_HI 1
+#define FENCE_HIT_CLR_SZ 1
+#define ILL_ADDR_INT_MSK 0x00000010
+#define ILL_ADDR_INT_I_MSK 0xffffffef
+#define ILL_ADDR_INT_SFT 4
+#define ILL_ADDR_INT_HI 4
+#define ILL_ADDR_INT_SZ 1
+#define FENCE_HIT_INT_MSK 0x00000020
+#define FENCE_HIT_INT_I_MSK 0xffffffdf
+#define FENCE_HIT_INT_SFT 5
+#define FENCE_HIT_INT_HI 5
+#define FENCE_HIT_INT_SZ 1
+#define PWM_INI_VALUE_P_A_MSK 0x000000ff
+#define PWM_INI_VALUE_P_A_I_MSK 0xffffff00
+#define PWM_INI_VALUE_P_A_SFT 0
+#define PWM_INI_VALUE_P_A_HI 7
+#define PWM_INI_VALUE_P_A_SZ 8
+#define PWM_INI_VALUE_N_A_MSK 0x0000ff00
+#define PWM_INI_VALUE_N_A_I_MSK 0xffff00ff
+#define PWM_INI_VALUE_N_A_SFT 8
+#define PWM_INI_VALUE_N_A_HI 15
+#define PWM_INI_VALUE_N_A_SZ 8
+#define PWM_POST_SCALER_A_MSK 0x000f0000
+#define PWM_POST_SCALER_A_I_MSK 0xfff0ffff
+#define PWM_POST_SCALER_A_SFT 16
+#define PWM_POST_SCALER_A_HI 19
+#define PWM_POST_SCALER_A_SZ 4
+#define PWM_ALWAYSON_A_MSK 0x20000000
+#define PWM_ALWAYSON_A_I_MSK 0xdfffffff
+#define PWM_ALWAYSON_A_SFT 29
+#define PWM_ALWAYSON_A_HI 29
+#define PWM_ALWAYSON_A_SZ 1
+#define PWM_INVERT_A_MSK 0x40000000
+#define PWM_INVERT_A_I_MSK 0xbfffffff
+#define PWM_INVERT_A_SFT 30
+#define PWM_INVERT_A_HI 30
+#define PWM_INVERT_A_SZ 1
+#define PWM_ENABLE_A_MSK 0x80000000
+#define PWM_ENABLE_A_I_MSK 0x7fffffff
+#define PWM_ENABLE_A_SFT 31
+#define PWM_ENABLE_A_HI 31
+#define PWM_ENABLE_A_SZ 1
+#define PWM_INI_VALUE_P_B_MSK 0x000000ff
+#define PWM_INI_VALUE_P_B_I_MSK 0xffffff00
+#define PWM_INI_VALUE_P_B_SFT 0
+#define PWM_INI_VALUE_P_B_HI 7
+#define PWM_INI_VALUE_P_B_SZ 8
+#define PWM_INI_VALUE_N_B_MSK 0x0000ff00
+#define PWM_INI_VALUE_N_B_I_MSK 0xffff00ff
+#define PWM_INI_VALUE_N_B_SFT 8
+#define PWM_INI_VALUE_N_B_HI 15
+#define PWM_INI_VALUE_N_B_SZ 8
+#define PWM_POST_SCALER_B_MSK 0x000f0000
+#define PWM_POST_SCALER_B_I_MSK 0xfff0ffff
+#define PWM_POST_SCALER_B_SFT 16
+#define PWM_POST_SCALER_B_HI 19
+#define PWM_POST_SCALER_B_SZ 4
+#define PWM_ALWAYSON_B_MSK 0x20000000
+#define PWM_ALWAYSON_B_I_MSK 0xdfffffff
+#define PWM_ALWAYSON_B_SFT 29
+#define PWM_ALWAYSON_B_HI 29
+#define PWM_ALWAYSON_B_SZ 1
+#define PWM_INVERT_B_MSK 0x40000000
+#define PWM_INVERT_B_I_MSK 0xbfffffff
+#define PWM_INVERT_B_SFT 30
+#define PWM_INVERT_B_HI 30
+#define PWM_INVERT_B_SZ 1
+#define PWM_ENABLE_B_MSK 0x80000000
+#define PWM_ENABLE_B_I_MSK 0x7fffffff
+#define PWM_ENABLE_B_SFT 31
+#define PWM_ENABLE_B_HI 31
+#define PWM_ENABLE_B_SZ 1
+#define HBUSREQ_LOCK_MSK 0x00001fff
+#define HBUSREQ_LOCK_I_MSK 0xffffe000
+#define HBUSREQ_LOCK_SFT 0
+#define HBUSREQ_LOCK_HI 12
+#define HBUSREQ_LOCK_SZ 13
+#define HBURST_LOCK_MSK 0x00001fff
+#define HBURST_LOCK_I_MSK 0xffffe000
+#define HBURST_LOCK_SFT 0
+#define HBURST_LOCK_HI 12
+#define HBURST_LOCK_SZ 13
+#define PRESCALER_USTIMER_MSK 0x000001ff
+#define PRESCALER_USTIMER_I_MSK 0xfffffe00
+#define PRESCALER_USTIMER_SFT 0
+#define PRESCALER_USTIMER_HI 8
+#define PRESCALER_USTIMER_SZ 9
+#define MODE_REG_IN_MMU_MSK 0x0000ffff
+#define MODE_REG_IN_MMU_I_MSK 0xffff0000
+#define MODE_REG_IN_MMU_SFT 0
+#define MODE_REG_IN_MMU_HI 15
+#define MODE_REG_IN_MMU_SZ 16
+#define MODE_REG_OUT_MMU_MSK 0x0000ffff
+#define MODE_REG_OUT_MMU_I_MSK 0xffff0000
+#define MODE_REG_OUT_MMU_SFT 0
+#define MODE_REG_OUT_MMU_HI 15
+#define MODE_REG_OUT_MMU_SZ 16
+#define MODE_REG_SO_MMU_MSK 0x80000000
+#define MODE_REG_SO_MMU_I_MSK 0x7fffffff
+#define MODE_REG_SO_MMU_SFT 31
+#define MODE_REG_SO_MMU_HI 31
+#define MODE_REG_SO_MMU_SZ 1
+#define MONITOR_BUS_MMU_MSK 0x0007ffff
+#define MONITOR_BUS_MMU_I_MSK 0xfff80000
+#define MONITOR_BUS_MMU_SFT 0
+#define MONITOR_BUS_MMU_HI 18
+#define MONITOR_BUS_MMU_SZ 19
+#define TEST_MODE0_MSK 0x00000001
+#define TEST_MODE0_I_MSK 0xfffffffe
+#define TEST_MODE0_SFT 0
+#define TEST_MODE0_HI 0
+#define TEST_MODE0_SZ 1
+#define TEST_MODE1_MSK 0x00000002
+#define TEST_MODE1_I_MSK 0xfffffffd
+#define TEST_MODE1_SFT 1
+#define TEST_MODE1_HI 1
+#define TEST_MODE1_SZ 1
+#define TEST_MODE2_MSK 0x00000004
+#define TEST_MODE2_I_MSK 0xfffffffb
+#define TEST_MODE2_SFT 2
+#define TEST_MODE2_HI 2
+#define TEST_MODE2_SZ 1
+#define TEST_MODE3_MSK 0x00000008
+#define TEST_MODE3_I_MSK 0xfffffff7
+#define TEST_MODE3_SFT 3
+#define TEST_MODE3_HI 3
+#define TEST_MODE3_SZ 1
+#define TEST_MODE4_MSK 0x00000010
+#define TEST_MODE4_I_MSK 0xffffffef
+#define TEST_MODE4_SFT 4
+#define TEST_MODE4_HI 4
+#define TEST_MODE4_SZ 1
+#define TEST_MODE_ALL_MSK 0x00000020
+#define TEST_MODE_ALL_I_MSK 0xffffffdf
+#define TEST_MODE_ALL_SFT 5
+#define TEST_MODE_ALL_HI 5
+#define TEST_MODE_ALL_SZ 1
+#define WDT_INIT_MSK 0x00000001
+#define WDT_INIT_I_MSK 0xfffffffe
+#define WDT_INIT_SFT 0
+#define WDT_INIT_HI 0
+#define WDT_INIT_SZ 1
+#define SD_HOST_INIT_MSK 0x00000002
+#define SD_HOST_INIT_I_MSK 0xfffffffd
+#define SD_HOST_INIT_SFT 1
+#define SD_HOST_INIT_HI 1
+#define SD_HOST_INIT_SZ 1
+#define ALLOW_SD_RESET_MSK 0x00000001
+#define ALLOW_SD_RESET_I_MSK 0xfffffffe
+#define ALLOW_SD_RESET_SFT 0
+#define ALLOW_SD_RESET_HI 0
+#define ALLOW_SD_RESET_SZ 1
+#define UART_NRTS_MSK 0x00000001
+#define UART_NRTS_I_MSK 0xfffffffe
+#define UART_NRTS_SFT 0
+#define UART_NRTS_HI 0
+#define UART_NRTS_SZ 1
+#define UART_NCTS_MSK 0x00000002
+#define UART_NCTS_I_MSK 0xfffffffd
+#define UART_NCTS_SFT 1
+#define UART_NCTS_HI 1
+#define UART_NCTS_SZ 1
+#define TU0_TM_INIT_VALUE_MSK 0x0000ffff
+#define TU0_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TU0_TM_INIT_VALUE_SFT 0
+#define TU0_TM_INIT_VALUE_HI 15
+#define TU0_TM_INIT_VALUE_SZ 16
+#define TU0_TM_MODE_MSK 0x00010000
+#define TU0_TM_MODE_I_MSK 0xfffeffff
+#define TU0_TM_MODE_SFT 16
+#define TU0_TM_MODE_HI 16
+#define TU0_TM_MODE_SZ 1
+#define TU0_TM_INT_STS_DONE_MSK 0x00020000
+#define TU0_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TU0_TM_INT_STS_DONE_SFT 17
+#define TU0_TM_INT_STS_DONE_HI 17
+#define TU0_TM_INT_STS_DONE_SZ 1
+#define TU0_TM_INT_MASK_MSK 0x00040000
+#define TU0_TM_INT_MASK_I_MSK 0xfffbffff
+#define TU0_TM_INT_MASK_SFT 18
+#define TU0_TM_INT_MASK_HI 18
+#define TU0_TM_INT_MASK_SZ 1
+#define TU0_TM_CUR_VALUE_MSK 0x0000ffff
+#define TU0_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TU0_TM_CUR_VALUE_SFT 0
+#define TU0_TM_CUR_VALUE_HI 15
+#define TU0_TM_CUR_VALUE_SZ 16
+#define TU1_TM_INIT_VALUE_MSK 0x0000ffff
+#define TU1_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TU1_TM_INIT_VALUE_SFT 0
+#define TU1_TM_INIT_VALUE_HI 15
+#define TU1_TM_INIT_VALUE_SZ 16
+#define TU1_TM_MODE_MSK 0x00010000
+#define TU1_TM_MODE_I_MSK 0xfffeffff
+#define TU1_TM_MODE_SFT 16
+#define TU1_TM_MODE_HI 16
+#define TU1_TM_MODE_SZ 1
+#define TU1_TM_INT_STS_DONE_MSK 0x00020000
+#define TU1_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TU1_TM_INT_STS_DONE_SFT 17
+#define TU1_TM_INT_STS_DONE_HI 17
+#define TU1_TM_INT_STS_DONE_SZ 1
+#define TU1_TM_INT_MASK_MSK 0x00040000
+#define TU1_TM_INT_MASK_I_MSK 0xfffbffff
+#define TU1_TM_INT_MASK_SFT 18
+#define TU1_TM_INT_MASK_HI 18
+#define TU1_TM_INT_MASK_SZ 1
+#define TU1_TM_CUR_VALUE_MSK 0x0000ffff
+#define TU1_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TU1_TM_CUR_VALUE_SFT 0
+#define TU1_TM_CUR_VALUE_HI 15
+#define TU1_TM_CUR_VALUE_SZ 16
+#define TU2_TM_INIT_VALUE_MSK 0x0000ffff
+#define TU2_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TU2_TM_INIT_VALUE_SFT 0
+#define TU2_TM_INIT_VALUE_HI 15
+#define TU2_TM_INIT_VALUE_SZ 16
+#define TU2_TM_MODE_MSK 0x00010000
+#define TU2_TM_MODE_I_MSK 0xfffeffff
+#define TU2_TM_MODE_SFT 16
+#define TU2_TM_MODE_HI 16
+#define TU2_TM_MODE_SZ 1
+#define TU2_TM_INT_STS_DONE_MSK 0x00020000
+#define TU2_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TU2_TM_INT_STS_DONE_SFT 17
+#define TU2_TM_INT_STS_DONE_HI 17
+#define TU2_TM_INT_STS_DONE_SZ 1
+#define TU2_TM_INT_MASK_MSK 0x00040000
+#define TU2_TM_INT_MASK_I_MSK 0xfffbffff
+#define TU2_TM_INT_MASK_SFT 18
+#define TU2_TM_INT_MASK_HI 18
+#define TU2_TM_INT_MASK_SZ 1
+#define TU2_TM_CUR_VALUE_MSK 0x0000ffff
+#define TU2_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TU2_TM_CUR_VALUE_SFT 0
+#define TU2_TM_CUR_VALUE_HI 15
+#define TU2_TM_CUR_VALUE_SZ 16
+#define TU3_TM_INIT_VALUE_MSK 0x0000ffff
+#define TU3_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TU3_TM_INIT_VALUE_SFT 0
+#define TU3_TM_INIT_VALUE_HI 15
+#define TU3_TM_INIT_VALUE_SZ 16
+#define TU3_TM_MODE_MSK 0x00010000
+#define TU3_TM_MODE_I_MSK 0xfffeffff
+#define TU3_TM_MODE_SFT 16
+#define TU3_TM_MODE_HI 16
+#define TU3_TM_MODE_SZ 1
+#define TU3_TM_INT_STS_DONE_MSK 0x00020000
+#define TU3_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TU3_TM_INT_STS_DONE_SFT 17
+#define TU3_TM_INT_STS_DONE_HI 17
+#define TU3_TM_INT_STS_DONE_SZ 1
+#define TU3_TM_INT_MASK_MSK 0x00040000
+#define TU3_TM_INT_MASK_I_MSK 0xfffbffff
+#define TU3_TM_INT_MASK_SFT 18
+#define TU3_TM_INT_MASK_HI 18
+#define TU3_TM_INT_MASK_SZ 1
+#define TU3_TM_CUR_VALUE_MSK 0x0000ffff
+#define TU3_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TU3_TM_CUR_VALUE_SFT 0
+#define TU3_TM_CUR_VALUE_HI 15
+#define TU3_TM_CUR_VALUE_SZ 16
+#define TM0_TM_INIT_VALUE_MSK 0x0000ffff
+#define TM0_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TM0_TM_INIT_VALUE_SFT 0
+#define TM0_TM_INIT_VALUE_HI 15
+#define TM0_TM_INIT_VALUE_SZ 16
+#define TM0_TM_MODE_MSK 0x00010000
+#define TM0_TM_MODE_I_MSK 0xfffeffff
+#define TM0_TM_MODE_SFT 16
+#define TM0_TM_MODE_HI 16
+#define TM0_TM_MODE_SZ 1
+#define TM0_TM_INT_STS_DONE_MSK 0x00020000
+#define TM0_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TM0_TM_INT_STS_DONE_SFT 17
+#define TM0_TM_INT_STS_DONE_HI 17
+#define TM0_TM_INT_STS_DONE_SZ 1
+#define TM0_TM_INT_MASK_MSK 0x00040000
+#define TM0_TM_INT_MASK_I_MSK 0xfffbffff
+#define TM0_TM_INT_MASK_SFT 18
+#define TM0_TM_INT_MASK_HI 18
+#define TM0_TM_INT_MASK_SZ 1
+#define TM0_TM_CUR_VALUE_MSK 0x0000ffff
+#define TM0_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TM0_TM_CUR_VALUE_SFT 0
+#define TM0_TM_CUR_VALUE_HI 15
+#define TM0_TM_CUR_VALUE_SZ 16
+#define TM1_TM_INIT_VALUE_MSK 0x0000ffff
+#define TM1_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TM1_TM_INIT_VALUE_SFT 0
+#define TM1_TM_INIT_VALUE_HI 15
+#define TM1_TM_INIT_VALUE_SZ 16
+#define TM1_TM_MODE_MSK 0x00010000
+#define TM1_TM_MODE_I_MSK 0xfffeffff
+#define TM1_TM_MODE_SFT 16
+#define TM1_TM_MODE_HI 16
+#define TM1_TM_MODE_SZ 1
+#define TM1_TM_INT_STS_DONE_MSK 0x00020000
+#define TM1_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TM1_TM_INT_STS_DONE_SFT 17
+#define TM1_TM_INT_STS_DONE_HI 17
+#define TM1_TM_INT_STS_DONE_SZ 1
+#define TM1_TM_INT_MASK_MSK 0x00040000
+#define TM1_TM_INT_MASK_I_MSK 0xfffbffff
+#define TM1_TM_INT_MASK_SFT 18
+#define TM1_TM_INT_MASK_HI 18
+#define TM1_TM_INT_MASK_SZ 1
+#define TM1_TM_CUR_VALUE_MSK 0x0000ffff
+#define TM1_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TM1_TM_CUR_VALUE_SFT 0
+#define TM1_TM_CUR_VALUE_HI 15
+#define TM1_TM_CUR_VALUE_SZ 16
+#define TM2_TM_INIT_VALUE_MSK 0x0000ffff
+#define TM2_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TM2_TM_INIT_VALUE_SFT 0
+#define TM2_TM_INIT_VALUE_HI 15
+#define TM2_TM_INIT_VALUE_SZ 16
+#define TM2_TM_MODE_MSK 0x00010000
+#define TM2_TM_MODE_I_MSK 0xfffeffff
+#define TM2_TM_MODE_SFT 16
+#define TM2_TM_MODE_HI 16
+#define TM2_TM_MODE_SZ 1
+#define TM2_TM_INT_STS_DONE_MSK 0x00020000
+#define TM2_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TM2_TM_INT_STS_DONE_SFT 17
+#define TM2_TM_INT_STS_DONE_HI 17
+#define TM2_TM_INT_STS_DONE_SZ 1
+#define TM2_TM_INT_MASK_MSK 0x00040000
+#define TM2_TM_INT_MASK_I_MSK 0xfffbffff
+#define TM2_TM_INT_MASK_SFT 18
+#define TM2_TM_INT_MASK_HI 18
+#define TM2_TM_INT_MASK_SZ 1
+#define TM2_TM_CUR_VALUE_MSK 0x0000ffff
+#define TM2_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TM2_TM_CUR_VALUE_SFT 0
+#define TM2_TM_CUR_VALUE_HI 15
+#define TM2_TM_CUR_VALUE_SZ 16
+#define TM3_TM_INIT_VALUE_MSK 0x0000ffff
+#define TM3_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TM3_TM_INIT_VALUE_SFT 0
+#define TM3_TM_INIT_VALUE_HI 15
+#define TM3_TM_INIT_VALUE_SZ 16
+#define TM3_TM_MODE_MSK 0x00010000
+#define TM3_TM_MODE_I_MSK 0xfffeffff
+#define TM3_TM_MODE_SFT 16
+#define TM3_TM_MODE_HI 16
+#define TM3_TM_MODE_SZ 1
+#define TM3_TM_INT_STS_DONE_MSK 0x00020000
+#define TM3_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TM3_TM_INT_STS_DONE_SFT 17
+#define TM3_TM_INT_STS_DONE_HI 17
+#define TM3_TM_INT_STS_DONE_SZ 1
+#define TM3_TM_INT_MASK_MSK 0x00040000
+#define TM3_TM_INT_MASK_I_MSK 0xfffbffff
+#define TM3_TM_INT_MASK_SFT 18
+#define TM3_TM_INT_MASK_HI 18
+#define TM3_TM_INT_MASK_SZ 1
+#define TM3_TM_CUR_VALUE_MSK 0x0000ffff
+#define TM3_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TM3_TM_CUR_VALUE_SFT 0
+#define TM3_TM_CUR_VALUE_HI 15
+#define TM3_TM_CUR_VALUE_SZ 16
+#define MCU_WDT_TIME_CNT_MSK 0x0000ffff
+#define MCU_WDT_TIME_CNT_I_MSK 0xffff0000
+#define MCU_WDT_TIME_CNT_SFT 0
+#define MCU_WDT_TIME_CNT_HI 15
+#define MCU_WDT_TIME_CNT_SZ 16
+#define MCU_WDT_STATUS_MSK 0x00020000
+#define MCU_WDT_STATUS_I_MSK 0xfffdffff
+#define MCU_WDT_STATUS_SFT 17
+#define MCU_WDT_STATUS_HI 17
+#define MCU_WDT_STATUS_SZ 1
+#define MCU_WDOG_ENA_MSK 0x80000000
+#define MCU_WDOG_ENA_I_MSK 0x7fffffff
+#define MCU_WDOG_ENA_SFT 31
+#define MCU_WDOG_ENA_HI 31
+#define MCU_WDOG_ENA_SZ 1
+#define SYS_WDT_TIME_CNT_MSK 0x0000ffff
+#define SYS_WDT_TIME_CNT_I_MSK 0xffff0000
+#define SYS_WDT_TIME_CNT_SFT 0
+#define SYS_WDT_TIME_CNT_HI 15
+#define SYS_WDT_TIME_CNT_SZ 16
+#define SYS_WDT_STATUS_MSK 0x00020000
+#define SYS_WDT_STATUS_I_MSK 0xfffdffff
+#define SYS_WDT_STATUS_SFT 17
+#define SYS_WDT_STATUS_HI 17
+#define SYS_WDT_STATUS_SZ 1
+#define SYS_WDOG_ENA_MSK 0x80000000
+#define SYS_WDOG_ENA_I_MSK 0x7fffffff
+#define SYS_WDOG_ENA_SFT 31
+#define SYS_WDOG_ENA_HI 31
+#define SYS_WDOG_ENA_SZ 1
+#define XLNA_EN_O_OE_MSK 0x00000001
+#define XLNA_EN_O_OE_I_MSK 0xfffffffe
+#define XLNA_EN_O_OE_SFT 0
+#define XLNA_EN_O_OE_HI 0
+#define XLNA_EN_O_OE_SZ 1
+#define XLNA_EN_O_PE_MSK 0x00000002
+#define XLNA_EN_O_PE_I_MSK 0xfffffffd
+#define XLNA_EN_O_PE_SFT 1
+#define XLNA_EN_O_PE_HI 1
+#define XLNA_EN_O_PE_SZ 1
+#define PAD6_IE_MSK 0x00000008
+#define PAD6_IE_I_MSK 0xfffffff7
+#define PAD6_IE_SFT 3
+#define PAD6_IE_HI 3
+#define PAD6_IE_SZ 1
+#define PAD6_SEL_I_MSK 0x00000030
+#define PAD6_SEL_I_I_MSK 0xffffffcf
+#define PAD6_SEL_I_SFT 4
+#define PAD6_SEL_I_HI 5
+#define PAD6_SEL_I_SZ 2
+#define PAD6_OD_MSK 0x00000100
+#define PAD6_OD_I_MSK 0xfffffeff
+#define PAD6_OD_SFT 8
+#define PAD6_OD_HI 8
+#define PAD6_OD_SZ 1
+#define PAD6_SEL_O_MSK 0x00001000
+#define PAD6_SEL_O_I_MSK 0xffffefff
+#define PAD6_SEL_O_SFT 12
+#define PAD6_SEL_O_HI 12
+#define PAD6_SEL_O_SZ 1
+#define XLNA_EN_O_C_MSK 0x10000000
+#define XLNA_EN_O_C_I_MSK 0xefffffff
+#define XLNA_EN_O_C_SFT 28
+#define XLNA_EN_O_C_HI 28
+#define XLNA_EN_O_C_SZ 1
+#define WIFI_TX_SW_O_OE_MSK 0x00000001
+#define WIFI_TX_SW_O_OE_I_MSK 0xfffffffe
+#define WIFI_TX_SW_O_OE_SFT 0
+#define WIFI_TX_SW_O_OE_HI 0
+#define WIFI_TX_SW_O_OE_SZ 1
+#define WIFI_TX_SW_O_PE_MSK 0x00000002
+#define WIFI_TX_SW_O_PE_I_MSK 0xfffffffd
+#define WIFI_TX_SW_O_PE_SFT 1
+#define WIFI_TX_SW_O_PE_HI 1
+#define WIFI_TX_SW_O_PE_SZ 1
+#define PAD7_IE_MSK 0x00000008
+#define PAD7_IE_I_MSK 0xfffffff7
+#define PAD7_IE_SFT 3
+#define PAD7_IE_HI 3
+#define PAD7_IE_SZ 1
+#define PAD7_SEL_I_MSK 0x00000030
+#define PAD7_SEL_I_I_MSK 0xffffffcf
+#define PAD7_SEL_I_SFT 4
+#define PAD7_SEL_I_HI 5
+#define PAD7_SEL_I_SZ 2
+#define PAD7_OD_MSK 0x00000100
+#define PAD7_OD_I_MSK 0xfffffeff
+#define PAD7_OD_SFT 8
+#define PAD7_OD_HI 8
+#define PAD7_OD_SZ 1
+#define PAD7_SEL_O_MSK 0x00001000
+#define PAD7_SEL_O_I_MSK 0xffffefff
+#define PAD7_SEL_O_SFT 12
+#define PAD7_SEL_O_HI 12
+#define PAD7_SEL_O_SZ 1
+#define WIFI_TX_SW_O_C_MSK 0x10000000
+#define WIFI_TX_SW_O_C_I_MSK 0xefffffff
+#define WIFI_TX_SW_O_C_SFT 28
+#define WIFI_TX_SW_O_C_HI 28
+#define WIFI_TX_SW_O_C_SZ 1
+#define WIFI_RX_SW_O_OE_MSK 0x00000001
+#define WIFI_RX_SW_O_OE_I_MSK 0xfffffffe
+#define WIFI_RX_SW_O_OE_SFT 0
+#define WIFI_RX_SW_O_OE_HI 0
+#define WIFI_RX_SW_O_OE_SZ 1
+#define WIFI_RX_SW_O_PE_MSK 0x00000002
+#define WIFI_RX_SW_O_PE_I_MSK 0xfffffffd
+#define WIFI_RX_SW_O_PE_SFT 1
+#define WIFI_RX_SW_O_PE_HI 1
+#define WIFI_RX_SW_O_PE_SZ 1
+#define PAD8_IE_MSK 0x00000008
+#define PAD8_IE_I_MSK 0xfffffff7
+#define PAD8_IE_SFT 3
+#define PAD8_IE_HI 3
+#define PAD8_IE_SZ 1
+#define PAD8_SEL_I_MSK 0x00000030
+#define PAD8_SEL_I_I_MSK 0xffffffcf
+#define PAD8_SEL_I_SFT 4
+#define PAD8_SEL_I_HI 5
+#define PAD8_SEL_I_SZ 2
+#define PAD8_OD_MSK 0x00000100
+#define PAD8_OD_I_MSK 0xfffffeff
+#define PAD8_OD_SFT 8
+#define PAD8_OD_HI 8
+#define PAD8_OD_SZ 1
+#define WIFI_RX_SW_O_C_MSK 0x10000000
+#define WIFI_RX_SW_O_C_I_MSK 0xefffffff
+#define WIFI_RX_SW_O_C_SFT 28
+#define WIFI_RX_SW_O_C_HI 28
+#define WIFI_RX_SW_O_C_SZ 1
+#define BT_SW_O_OE_MSK 0x00000001
+#define BT_SW_O_OE_I_MSK 0xfffffffe
+#define BT_SW_O_OE_SFT 0
+#define BT_SW_O_OE_HI 0
+#define BT_SW_O_OE_SZ 1
+#define BT_SW_O_PE_MSK 0x00000002
+#define BT_SW_O_PE_I_MSK 0xfffffffd
+#define BT_SW_O_PE_SFT 1
+#define BT_SW_O_PE_HI 1
+#define BT_SW_O_PE_SZ 1
+#define PAD9_IE_MSK 0x00000008
+#define PAD9_IE_I_MSK 0xfffffff7
+#define PAD9_IE_SFT 3
+#define PAD9_IE_HI 3
+#define PAD9_IE_SZ 1
+#define PAD9_SEL_I_MSK 0x00000030
+#define PAD9_SEL_I_I_MSK 0xffffffcf
+#define PAD9_SEL_I_SFT 4
+#define PAD9_SEL_I_HI 5
+#define PAD9_SEL_I_SZ 2
+#define PAD9_OD_MSK 0x00000100
+#define PAD9_OD_I_MSK 0xfffffeff
+#define PAD9_OD_SFT 8
+#define PAD9_OD_HI 8
+#define PAD9_OD_SZ 1
+#define PAD9_SEL_O_MSK 0x00001000
+#define PAD9_SEL_O_I_MSK 0xffffefff
+#define PAD9_SEL_O_SFT 12
+#define PAD9_SEL_O_HI 12
+#define PAD9_SEL_O_SZ 1
+#define BT_SW_O_C_MSK 0x10000000
+#define BT_SW_O_C_I_MSK 0xefffffff
+#define BT_SW_O_C_SFT 28
+#define BT_SW_O_C_HI 28
+#define BT_SW_O_C_SZ 1
+#define XPA_EN_O_OE_MSK 0x00000001
+#define XPA_EN_O_OE_I_MSK 0xfffffffe
+#define XPA_EN_O_OE_SFT 0
+#define XPA_EN_O_OE_HI 0
+#define XPA_EN_O_OE_SZ 1
+#define XPA_EN_O_PE_MSK 0x00000002
+#define XPA_EN_O_PE_I_MSK 0xfffffffd
+#define XPA_EN_O_PE_SFT 1
+#define XPA_EN_O_PE_HI 1
+#define XPA_EN_O_PE_SZ 1
+#define PAD11_IE_MSK 0x00000008
+#define PAD11_IE_I_MSK 0xfffffff7
+#define PAD11_IE_SFT 3
+#define PAD11_IE_HI 3
+#define PAD11_IE_SZ 1
+#define PAD11_SEL_I_MSK 0x00000030
+#define PAD11_SEL_I_I_MSK 0xffffffcf
+#define PAD11_SEL_I_SFT 4
+#define PAD11_SEL_I_HI 5
+#define PAD11_SEL_I_SZ 2
+#define PAD11_OD_MSK 0x00000100
+#define PAD11_OD_I_MSK 0xfffffeff
+#define PAD11_OD_SFT 8
+#define PAD11_OD_HI 8
+#define PAD11_OD_SZ 1
+#define PAD11_SEL_O_MSK 0x00001000
+#define PAD11_SEL_O_I_MSK 0xffffefff
+#define PAD11_SEL_O_SFT 12
+#define PAD11_SEL_O_HI 12
+#define PAD11_SEL_O_SZ 1
+#define XPA_EN_O_C_MSK 0x10000000
+#define XPA_EN_O_C_I_MSK 0xefffffff
+#define XPA_EN_O_C_SFT 28
+#define XPA_EN_O_C_HI 28
+#define XPA_EN_O_C_SZ 1
+#define PAD15_OE_MSK 0x00000001
+#define PAD15_OE_I_MSK 0xfffffffe
+#define PAD15_OE_SFT 0
+#define PAD15_OE_HI 0
+#define PAD15_OE_SZ 1
+#define PAD15_PE_MSK 0x00000002
+#define PAD15_PE_I_MSK 0xfffffffd
+#define PAD15_PE_SFT 1
+#define PAD15_PE_HI 1
+#define PAD15_PE_SZ 1
+#define PAD15_DS_MSK 0x00000004
+#define PAD15_DS_I_MSK 0xfffffffb
+#define PAD15_DS_SFT 2
+#define PAD15_DS_HI 2
+#define PAD15_DS_SZ 1
+#define PAD15_IE_MSK 0x00000008
+#define PAD15_IE_I_MSK 0xfffffff7
+#define PAD15_IE_SFT 3
+#define PAD15_IE_HI 3
+#define PAD15_IE_SZ 1
+#define PAD15_SEL_I_MSK 0x00000030
+#define PAD15_SEL_I_I_MSK 0xffffffcf
+#define PAD15_SEL_I_SFT 4
+#define PAD15_SEL_I_HI 5
+#define PAD15_SEL_I_SZ 2
+#define PAD15_OD_MSK 0x00000100
+#define PAD15_OD_I_MSK 0xfffffeff
+#define PAD15_OD_SFT 8
+#define PAD15_OD_HI 8
+#define PAD15_OD_SZ 1
+#define PAD15_SEL_O_MSK 0x00001000
+#define PAD15_SEL_O_I_MSK 0xffffefff
+#define PAD15_SEL_O_SFT 12
+#define PAD15_SEL_O_HI 12
+#define PAD15_SEL_O_SZ 1
+#define TEST_1_ID_MSK 0x10000000
+#define TEST_1_ID_I_MSK 0xefffffff
+#define TEST_1_ID_SFT 28
+#define TEST_1_ID_HI 28
+#define TEST_1_ID_SZ 1
+#define PAD16_OE_MSK 0x00000001
+#define PAD16_OE_I_MSK 0xfffffffe
+#define PAD16_OE_SFT 0
+#define PAD16_OE_HI 0
+#define PAD16_OE_SZ 1
+#define PAD16_PE_MSK 0x00000002
+#define PAD16_PE_I_MSK 0xfffffffd
+#define PAD16_PE_SFT 1
+#define PAD16_PE_HI 1
+#define PAD16_PE_SZ 1
+#define PAD16_DS_MSK 0x00000004
+#define PAD16_DS_I_MSK 0xfffffffb
+#define PAD16_DS_SFT 2
+#define PAD16_DS_HI 2
+#define PAD16_DS_SZ 1
+#define PAD16_IE_MSK 0x00000008
+#define PAD16_IE_I_MSK 0xfffffff7
+#define PAD16_IE_SFT 3
+#define PAD16_IE_HI 3
+#define PAD16_IE_SZ 1
+#define PAD16_SEL_I_MSK 0x00000030
+#define PAD16_SEL_I_I_MSK 0xffffffcf
+#define PAD16_SEL_I_SFT 4
+#define PAD16_SEL_I_HI 5
+#define PAD16_SEL_I_SZ 2
+#define PAD16_OD_MSK 0x00000100
+#define PAD16_OD_I_MSK 0xfffffeff
+#define PAD16_OD_SFT 8
+#define PAD16_OD_HI 8
+#define PAD16_OD_SZ 1
+#define PAD16_SEL_O_MSK 0x00001000
+#define PAD16_SEL_O_I_MSK 0xffffefff
+#define PAD16_SEL_O_SFT 12
+#define PAD16_SEL_O_HI 12
+#define PAD16_SEL_O_SZ 1
+#define TEST_2_ID_MSK 0x10000000
+#define TEST_2_ID_I_MSK 0xefffffff
+#define TEST_2_ID_SFT 28
+#define TEST_2_ID_HI 28
+#define TEST_2_ID_SZ 1
+#define PAD17_OE_MSK 0x00000001
+#define PAD17_OE_I_MSK 0xfffffffe
+#define PAD17_OE_SFT 0
+#define PAD17_OE_HI 0
+#define PAD17_OE_SZ 1
+#define PAD17_PE_MSK 0x00000002
+#define PAD17_PE_I_MSK 0xfffffffd
+#define PAD17_PE_SFT 1
+#define PAD17_PE_HI 1
+#define PAD17_PE_SZ 1
+#define PAD17_DS_MSK 0x00000004
+#define PAD17_DS_I_MSK 0xfffffffb
+#define PAD17_DS_SFT 2
+#define PAD17_DS_HI 2
+#define PAD17_DS_SZ 1
+#define PAD17_IE_MSK 0x00000008
+#define PAD17_IE_I_MSK 0xfffffff7
+#define PAD17_IE_SFT 3
+#define PAD17_IE_HI 3
+#define PAD17_IE_SZ 1
+#define PAD17_SEL_I_MSK 0x00000030
+#define PAD17_SEL_I_I_MSK 0xffffffcf
+#define PAD17_SEL_I_SFT 4
+#define PAD17_SEL_I_HI 5
+#define PAD17_SEL_I_SZ 2
+#define PAD17_OD_MSK 0x00000100
+#define PAD17_OD_I_MSK 0xfffffeff
+#define PAD17_OD_SFT 8
+#define PAD17_OD_HI 8
+#define PAD17_OD_SZ 1
+#define PAD17_SEL_O_MSK 0x00001000
+#define PAD17_SEL_O_I_MSK 0xffffefff
+#define PAD17_SEL_O_SFT 12
+#define PAD17_SEL_O_HI 12
+#define PAD17_SEL_O_SZ 1
+#define TEST_3_ID_MSK 0x10000000
+#define TEST_3_ID_I_MSK 0xefffffff
+#define TEST_3_ID_SFT 28
+#define TEST_3_ID_HI 28
+#define TEST_3_ID_SZ 1
+#define PAD18_OE_MSK 0x00000001
+#define PAD18_OE_I_MSK 0xfffffffe
+#define PAD18_OE_SFT 0
+#define PAD18_OE_HI 0
+#define PAD18_OE_SZ 1
+#define PAD18_PE_MSK 0x00000002
+#define PAD18_PE_I_MSK 0xfffffffd
+#define PAD18_PE_SFT 1
+#define PAD18_PE_HI 1
+#define PAD18_PE_SZ 1
+#define PAD18_DS_MSK 0x00000004
+#define PAD18_DS_I_MSK 0xfffffffb
+#define PAD18_DS_SFT 2
+#define PAD18_DS_HI 2
+#define PAD18_DS_SZ 1
+#define PAD18_IE_MSK 0x00000008
+#define PAD18_IE_I_MSK 0xfffffff7
+#define PAD18_IE_SFT 3
+#define PAD18_IE_HI 3
+#define PAD18_IE_SZ 1
+#define PAD18_SEL_I_MSK 0x00000030
+#define PAD18_SEL_I_I_MSK 0xffffffcf
+#define PAD18_SEL_I_SFT 4
+#define PAD18_SEL_I_HI 5
+#define PAD18_SEL_I_SZ 2
+#define PAD18_OD_MSK 0x00000100
+#define PAD18_OD_I_MSK 0xfffffeff
+#define PAD18_OD_SFT 8
+#define PAD18_OD_HI 8
+#define PAD18_OD_SZ 1
+#define PAD18_SEL_O_MSK 0x00003000
+#define PAD18_SEL_O_I_MSK 0xffffcfff
+#define PAD18_SEL_O_SFT 12
+#define PAD18_SEL_O_HI 13
+#define PAD18_SEL_O_SZ 2
+#define TEST_4_ID_MSK 0x10000000
+#define TEST_4_ID_I_MSK 0xefffffff
+#define TEST_4_ID_SFT 28
+#define TEST_4_ID_HI 28
+#define TEST_4_ID_SZ 1
+#define PAD19_OE_MSK 0x00000001
+#define PAD19_OE_I_MSK 0xfffffffe
+#define PAD19_OE_SFT 0
+#define PAD19_OE_HI 0
+#define PAD19_OE_SZ 1
+#define PAD19_PE_MSK 0x00000002
+#define PAD19_PE_I_MSK 0xfffffffd
+#define PAD19_PE_SFT 1
+#define PAD19_PE_HI 1
+#define PAD19_PE_SZ 1
+#define PAD19_DS_MSK 0x00000004
+#define PAD19_DS_I_MSK 0xfffffffb
+#define PAD19_DS_SFT 2
+#define PAD19_DS_HI 2
+#define PAD19_DS_SZ 1
+#define PAD19_IE_MSK 0x00000008
+#define PAD19_IE_I_MSK 0xfffffff7
+#define PAD19_IE_SFT 3
+#define PAD19_IE_HI 3
+#define PAD19_IE_SZ 1
+#define PAD19_SEL_I_MSK 0x00000030
+#define PAD19_SEL_I_I_MSK 0xffffffcf
+#define PAD19_SEL_I_SFT 4
+#define PAD19_SEL_I_HI 5
+#define PAD19_SEL_I_SZ 2
+#define PAD19_OD_MSK 0x00000100
+#define PAD19_OD_I_MSK 0xfffffeff
+#define PAD19_OD_SFT 8
+#define PAD19_OD_HI 8
+#define PAD19_OD_SZ 1
+#define PAD19_SEL_O_MSK 0x00007000
+#define PAD19_SEL_O_I_MSK 0xffff8fff
+#define PAD19_SEL_O_SFT 12
+#define PAD19_SEL_O_HI 14
+#define PAD19_SEL_O_SZ 3
+#define SHORT_TO_20_ID_MSK 0x10000000
+#define SHORT_TO_20_ID_I_MSK 0xefffffff
+#define SHORT_TO_20_ID_SFT 28
+#define SHORT_TO_20_ID_HI 28
+#define SHORT_TO_20_ID_SZ 1
+#define PAD20_OE_MSK 0x00000001
+#define PAD20_OE_I_MSK 0xfffffffe
+#define PAD20_OE_SFT 0
+#define PAD20_OE_HI 0
+#define PAD20_OE_SZ 1
+#define PAD20_PE_MSK 0x00000002
+#define PAD20_PE_I_MSK 0xfffffffd
+#define PAD20_PE_SFT 1
+#define PAD20_PE_HI 1
+#define PAD20_PE_SZ 1
+#define PAD20_DS_MSK 0x00000004
+#define PAD20_DS_I_MSK 0xfffffffb
+#define PAD20_DS_SFT 2
+#define PAD20_DS_HI 2
+#define PAD20_DS_SZ 1
+#define PAD20_IE_MSK 0x00000008
+#define PAD20_IE_I_MSK 0xfffffff7
+#define PAD20_IE_SFT 3
+#define PAD20_IE_HI 3
+#define PAD20_IE_SZ 1
+#define PAD20_SEL_I_MSK 0x000000f0
+#define PAD20_SEL_I_I_MSK 0xffffff0f
+#define PAD20_SEL_I_SFT 4
+#define PAD20_SEL_I_HI 7
+#define PAD20_SEL_I_SZ 4
+#define PAD20_OD_MSK 0x00000100
+#define PAD20_OD_I_MSK 0xfffffeff
+#define PAD20_OD_SFT 8
+#define PAD20_OD_HI 8
+#define PAD20_OD_SZ 1
+#define PAD20_SEL_O_MSK 0x00003000
+#define PAD20_SEL_O_I_MSK 0xffffcfff
+#define PAD20_SEL_O_SFT 12
+#define PAD20_SEL_O_HI 13
+#define PAD20_SEL_O_SZ 2
+#define STRAP0_MSK 0x08000000
+#define STRAP0_I_MSK 0xf7ffffff
+#define STRAP0_SFT 27
+#define STRAP0_HI 27
+#define STRAP0_SZ 1
+#define GPIO_TEST_1_ID_MSK 0x10000000
+#define GPIO_TEST_1_ID_I_MSK 0xefffffff
+#define GPIO_TEST_1_ID_SFT 28
+#define GPIO_TEST_1_ID_HI 28
+#define GPIO_TEST_1_ID_SZ 1
+#define PAD21_OE_MSK 0x00000001
+#define PAD21_OE_I_MSK 0xfffffffe
+#define PAD21_OE_SFT 0
+#define PAD21_OE_HI 0
+#define PAD21_OE_SZ 1
+#define PAD21_PE_MSK 0x00000002
+#define PAD21_PE_I_MSK 0xfffffffd
+#define PAD21_PE_SFT 1
+#define PAD21_PE_HI 1
+#define PAD21_PE_SZ 1
+#define PAD21_DS_MSK 0x00000004
+#define PAD21_DS_I_MSK 0xfffffffb
+#define PAD21_DS_SFT 2
+#define PAD21_DS_HI 2
+#define PAD21_DS_SZ 1
+#define PAD21_IE_MSK 0x00000008
+#define PAD21_IE_I_MSK 0xfffffff7
+#define PAD21_IE_SFT 3
+#define PAD21_IE_HI 3
+#define PAD21_IE_SZ 1
+#define PAD21_SEL_I_MSK 0x00000070
+#define PAD21_SEL_I_I_MSK 0xffffff8f
+#define PAD21_SEL_I_SFT 4
+#define PAD21_SEL_I_HI 6
+#define PAD21_SEL_I_SZ 3
+#define PAD21_OD_MSK 0x00000100
+#define PAD21_OD_I_MSK 0xfffffeff
+#define PAD21_OD_SFT 8
+#define PAD21_OD_HI 8
+#define PAD21_OD_SZ 1
+#define PAD21_SEL_O_MSK 0x00003000
+#define PAD21_SEL_O_I_MSK 0xffffcfff
+#define PAD21_SEL_O_SFT 12
+#define PAD21_SEL_O_HI 13
+#define PAD21_SEL_O_SZ 2
+#define STRAP3_MSK 0x08000000
+#define STRAP3_I_MSK 0xf7ffffff
+#define STRAP3_SFT 27
+#define STRAP3_HI 27
+#define STRAP3_SZ 1
+#define GPIO_TEST_2_ID_MSK 0x10000000
+#define GPIO_TEST_2_ID_I_MSK 0xefffffff
+#define GPIO_TEST_2_ID_SFT 28
+#define GPIO_TEST_2_ID_HI 28
+#define GPIO_TEST_2_ID_SZ 1
+#define PAD22_OE_MSK 0x00000001
+#define PAD22_OE_I_MSK 0xfffffffe
+#define PAD22_OE_SFT 0
+#define PAD22_OE_HI 0
+#define PAD22_OE_SZ 1
+#define PAD22_PE_MSK 0x00000002
+#define PAD22_PE_I_MSK 0xfffffffd
+#define PAD22_PE_SFT 1
+#define PAD22_PE_HI 1
+#define PAD22_PE_SZ 1
+#define PAD22_DS_MSK 0x00000004
+#define PAD22_DS_I_MSK 0xfffffffb
+#define PAD22_DS_SFT 2
+#define PAD22_DS_HI 2
+#define PAD22_DS_SZ 1
+#define PAD22_IE_MSK 0x00000008
+#define PAD22_IE_I_MSK 0xfffffff7
+#define PAD22_IE_SFT 3
+#define PAD22_IE_HI 3
+#define PAD22_IE_SZ 1
+#define PAD22_SEL_I_MSK 0x00000070
+#define PAD22_SEL_I_I_MSK 0xffffff8f
+#define PAD22_SEL_I_SFT 4
+#define PAD22_SEL_I_HI 6
+#define PAD22_SEL_I_SZ 3
+#define PAD22_OD_MSK 0x00000100
+#define PAD22_OD_I_MSK 0xfffffeff
+#define PAD22_OD_SFT 8
+#define PAD22_OD_HI 8
+#define PAD22_OD_SZ 1
+#define PAD22_SEL_O_MSK 0x00007000
+#define PAD22_SEL_O_I_MSK 0xffff8fff
+#define PAD22_SEL_O_SFT 12
+#define PAD22_SEL_O_HI 14
+#define PAD22_SEL_O_SZ 3
+#define PAD22_SEL_OE_MSK 0x00100000
+#define PAD22_SEL_OE_I_MSK 0xffefffff
+#define PAD22_SEL_OE_SFT 20
+#define PAD22_SEL_OE_HI 20
+#define PAD22_SEL_OE_SZ 1
+#define GPIO_TEST_3_ID_MSK 0x10000000
+#define GPIO_TEST_3_ID_I_MSK 0xefffffff
+#define GPIO_TEST_3_ID_SFT 28
+#define GPIO_TEST_3_ID_HI 28
+#define GPIO_TEST_3_ID_SZ 1
+#define PAD24_OE_MSK 0x00000001
+#define PAD24_OE_I_MSK 0xfffffffe
+#define PAD24_OE_SFT 0
+#define PAD24_OE_HI 0
+#define PAD24_OE_SZ 1
+#define PAD24_PE_MSK 0x00000002
+#define PAD24_PE_I_MSK 0xfffffffd
+#define PAD24_PE_SFT 1
+#define PAD24_PE_HI 1
+#define PAD24_PE_SZ 1
+#define PAD24_DS_MSK 0x00000004
+#define PAD24_DS_I_MSK 0xfffffffb
+#define PAD24_DS_SFT 2
+#define PAD24_DS_HI 2
+#define PAD24_DS_SZ 1
+#define PAD24_IE_MSK 0x00000008
+#define PAD24_IE_I_MSK 0xfffffff7
+#define PAD24_IE_SFT 3
+#define PAD24_IE_HI 3
+#define PAD24_IE_SZ 1
+#define PAD24_SEL_I_MSK 0x00000030
+#define PAD24_SEL_I_I_MSK 0xffffffcf
+#define PAD24_SEL_I_SFT 4
+#define PAD24_SEL_I_HI 5
+#define PAD24_SEL_I_SZ 2
+#define PAD24_OD_MSK 0x00000100
+#define PAD24_OD_I_MSK 0xfffffeff
+#define PAD24_OD_SFT 8
+#define PAD24_OD_HI 8
+#define PAD24_OD_SZ 1
+#define PAD24_SEL_O_MSK 0x00007000
+#define PAD24_SEL_O_I_MSK 0xffff8fff
+#define PAD24_SEL_O_SFT 12
+#define PAD24_SEL_O_HI 14
+#define PAD24_SEL_O_SZ 3
+#define GPIO_TEST_4_ID_MSK 0x10000000
+#define GPIO_TEST_4_ID_I_MSK 0xefffffff
+#define GPIO_TEST_4_ID_SFT 28
+#define GPIO_TEST_4_ID_HI 28
+#define GPIO_TEST_4_ID_SZ 1
+#define PAD25_OE_MSK 0x00000001
+#define PAD25_OE_I_MSK 0xfffffffe
+#define PAD25_OE_SFT 0
+#define PAD25_OE_HI 0
+#define PAD25_OE_SZ 1
+#define PAD25_PE_MSK 0x00000002
+#define PAD25_PE_I_MSK 0xfffffffd
+#define PAD25_PE_SFT 1
+#define PAD25_PE_HI 1
+#define PAD25_PE_SZ 1
+#define PAD25_DS_MSK 0x00000004
+#define PAD25_DS_I_MSK 0xfffffffb
+#define PAD25_DS_SFT 2
+#define PAD25_DS_HI 2
+#define PAD25_DS_SZ 1
+#define PAD25_IE_MSK 0x00000008
+#define PAD25_IE_I_MSK 0xfffffff7
+#define PAD25_IE_SFT 3
+#define PAD25_IE_HI 3
+#define PAD25_IE_SZ 1
+#define PAD25_SEL_I_MSK 0x00000070
+#define PAD25_SEL_I_I_MSK 0xffffff8f
+#define PAD25_SEL_I_SFT 4
+#define PAD25_SEL_I_HI 6
+#define PAD25_SEL_I_SZ 3
+#define PAD25_OD_MSK 0x00000100
+#define PAD25_OD_I_MSK 0xfffffeff
+#define PAD25_OD_SFT 8
+#define PAD25_OD_HI 8
+#define PAD25_OD_SZ 1
+#define PAD25_SEL_O_MSK 0x00007000
+#define PAD25_SEL_O_I_MSK 0xffff8fff
+#define PAD25_SEL_O_SFT 12
+#define PAD25_SEL_O_HI 14
+#define PAD25_SEL_O_SZ 3
+#define PAD25_SEL_OE_MSK 0x00100000
+#define PAD25_SEL_OE_I_MSK 0xffefffff
+#define PAD25_SEL_OE_SFT 20
+#define PAD25_SEL_OE_HI 20
+#define PAD25_SEL_OE_SZ 1
+#define STRAP1_MSK 0x08000000
+#define STRAP1_I_MSK 0xf7ffffff
+#define STRAP1_SFT 27
+#define STRAP1_HI 27
+#define STRAP1_SZ 1
+#define GPIO_1_ID_MSK 0x10000000
+#define GPIO_1_ID_I_MSK 0xefffffff
+#define GPIO_1_ID_SFT 28
+#define GPIO_1_ID_HI 28
+#define GPIO_1_ID_SZ 1
+#define PAD27_OE_MSK 0x00000001
+#define PAD27_OE_I_MSK 0xfffffffe
+#define PAD27_OE_SFT 0
+#define PAD27_OE_HI 0
+#define PAD27_OE_SZ 1
+#define PAD27_PE_MSK 0x00000002
+#define PAD27_PE_I_MSK 0xfffffffd
+#define PAD27_PE_SFT 1
+#define PAD27_PE_HI 1
+#define PAD27_PE_SZ 1
+#define PAD27_DS_MSK 0x00000004
+#define PAD27_DS_I_MSK 0xfffffffb
+#define PAD27_DS_SFT 2
+#define PAD27_DS_HI 2
+#define PAD27_DS_SZ 1
+#define PAD27_IE_MSK 0x00000008
+#define PAD27_IE_I_MSK 0xfffffff7
+#define PAD27_IE_SFT 3
+#define PAD27_IE_HI 3
+#define PAD27_IE_SZ 1
+#define PAD27_SEL_I_MSK 0x00000070
+#define PAD27_SEL_I_I_MSK 0xffffff8f
+#define PAD27_SEL_I_SFT 4
+#define PAD27_SEL_I_HI 6
+#define PAD27_SEL_I_SZ 3
+#define PAD27_OD_MSK 0x00000100
+#define PAD27_OD_I_MSK 0xfffffeff
+#define PAD27_OD_SFT 8
+#define PAD27_OD_HI 8
+#define PAD27_OD_SZ 1
+#define PAD27_SEL_O_MSK 0x00007000
+#define PAD27_SEL_O_I_MSK 0xffff8fff
+#define PAD27_SEL_O_SFT 12
+#define PAD27_SEL_O_HI 14
+#define PAD27_SEL_O_SZ 3
+#define GPIO_2_ID_MSK 0x10000000
+#define GPIO_2_ID_I_MSK 0xefffffff
+#define GPIO_2_ID_SFT 28
+#define GPIO_2_ID_HI 28
+#define GPIO_2_ID_SZ 1
+#define PAD28_OE_MSK 0x00000001
+#define PAD28_OE_I_MSK 0xfffffffe
+#define PAD28_OE_SFT 0
+#define PAD28_OE_HI 0
+#define PAD28_OE_SZ 1
+#define PAD28_PE_MSK 0x00000002
+#define PAD28_PE_I_MSK 0xfffffffd
+#define PAD28_PE_SFT 1
+#define PAD28_PE_HI 1
+#define PAD28_PE_SZ 1
+#define PAD28_DS_MSK 0x00000004
+#define PAD28_DS_I_MSK 0xfffffffb
+#define PAD28_DS_SFT 2
+#define PAD28_DS_HI 2
+#define PAD28_DS_SZ 1
+#define PAD28_IE_MSK 0x00000008
+#define PAD28_IE_I_MSK 0xfffffff7
+#define PAD28_IE_SFT 3
+#define PAD28_IE_HI 3
+#define PAD28_IE_SZ 1
+#define PAD28_SEL_I_MSK 0x00000070
+#define PAD28_SEL_I_I_MSK 0xffffff8f
+#define PAD28_SEL_I_SFT 4
+#define PAD28_SEL_I_HI 6
+#define PAD28_SEL_I_SZ 3
+#define PAD28_OD_MSK 0x00000100
+#define PAD28_OD_I_MSK 0xfffffeff
+#define PAD28_OD_SFT 8
+#define PAD28_OD_HI 8
+#define PAD28_OD_SZ 1
+#define PAD28_SEL_O_MSK 0x0000f000
+#define PAD28_SEL_O_I_MSK 0xffff0fff
+#define PAD28_SEL_O_SFT 12
+#define PAD28_SEL_O_HI 15
+#define PAD28_SEL_O_SZ 4
+#define PAD28_SEL_OE_MSK 0x00100000
+#define PAD28_SEL_OE_I_MSK 0xffefffff
+#define PAD28_SEL_OE_SFT 20
+#define PAD28_SEL_OE_HI 20
+#define PAD28_SEL_OE_SZ 1
+#define GPIO_3_ID_MSK 0x10000000
+#define GPIO_3_ID_I_MSK 0xefffffff
+#define GPIO_3_ID_SFT 28
+#define GPIO_3_ID_HI 28
+#define GPIO_3_ID_SZ 1
+#define PAD29_OE_MSK 0x00000001
+#define PAD29_OE_I_MSK 0xfffffffe
+#define PAD29_OE_SFT 0
+#define PAD29_OE_HI 0
+#define PAD29_OE_SZ 1
+#define PAD29_PE_MSK 0x00000002
+#define PAD29_PE_I_MSK 0xfffffffd
+#define PAD29_PE_SFT 1
+#define PAD29_PE_HI 1
+#define PAD29_PE_SZ 1
+#define PAD29_DS_MSK 0x00000004
+#define PAD29_DS_I_MSK 0xfffffffb
+#define PAD29_DS_SFT 2
+#define PAD29_DS_HI 2
+#define PAD29_DS_SZ 1
+#define PAD29_IE_MSK 0x00000008
+#define PAD29_IE_I_MSK 0xfffffff7
+#define PAD29_IE_SFT 3
+#define PAD29_IE_HI 3
+#define PAD29_IE_SZ 1
+#define PAD29_SEL_I_MSK 0x00000070
+#define PAD29_SEL_I_I_MSK 0xffffff8f
+#define PAD29_SEL_I_SFT 4
+#define PAD29_SEL_I_HI 6
+#define PAD29_SEL_I_SZ 3
+#define PAD29_OD_MSK 0x00000100
+#define PAD29_OD_I_MSK 0xfffffeff
+#define PAD29_OD_SFT 8
+#define PAD29_OD_HI 8
+#define PAD29_OD_SZ 1
+#define PAD29_SEL_O_MSK 0x00007000
+#define PAD29_SEL_O_I_MSK 0xffff8fff
+#define PAD29_SEL_O_SFT 12
+#define PAD29_SEL_O_HI 14
+#define PAD29_SEL_O_SZ 3
+#define GPIO_TEST_5_ID_MSK 0x10000000
+#define GPIO_TEST_5_ID_I_MSK 0xefffffff
+#define GPIO_TEST_5_ID_SFT 28
+#define GPIO_TEST_5_ID_HI 28
+#define GPIO_TEST_5_ID_SZ 1
+#define PAD30_OE_MSK 0x00000001
+#define PAD30_OE_I_MSK 0xfffffffe
+#define PAD30_OE_SFT 0
+#define PAD30_OE_HI 0
+#define PAD30_OE_SZ 1
+#define PAD30_PE_MSK 0x00000002
+#define PAD30_PE_I_MSK 0xfffffffd
+#define PAD30_PE_SFT 1
+#define PAD30_PE_HI 1
+#define PAD30_PE_SZ 1
+#define PAD30_DS_MSK 0x00000004
+#define PAD30_DS_I_MSK 0xfffffffb
+#define PAD30_DS_SFT 2
+#define PAD30_DS_HI 2
+#define PAD30_DS_SZ 1
+#define PAD30_IE_MSK 0x00000008
+#define PAD30_IE_I_MSK 0xfffffff7
+#define PAD30_IE_SFT 3
+#define PAD30_IE_HI 3
+#define PAD30_IE_SZ 1
+#define PAD30_SEL_I_MSK 0x00000030
+#define PAD30_SEL_I_I_MSK 0xffffffcf
+#define PAD30_SEL_I_SFT 4
+#define PAD30_SEL_I_HI 5
+#define PAD30_SEL_I_SZ 2
+#define PAD30_OD_MSK 0x00000100
+#define PAD30_OD_I_MSK 0xfffffeff
+#define PAD30_OD_SFT 8
+#define PAD30_OD_HI 8
+#define PAD30_OD_SZ 1
+#define PAD30_SEL_O_MSK 0x00003000
+#define PAD30_SEL_O_I_MSK 0xffffcfff
+#define PAD30_SEL_O_SFT 12
+#define PAD30_SEL_O_HI 13
+#define PAD30_SEL_O_SZ 2
+#define TEST_6_ID_MSK 0x10000000
+#define TEST_6_ID_I_MSK 0xefffffff
+#define TEST_6_ID_SFT 28
+#define TEST_6_ID_HI 28
+#define TEST_6_ID_SZ 1
+#define PAD31_OE_MSK 0x00000001
+#define PAD31_OE_I_MSK 0xfffffffe
+#define PAD31_OE_SFT 0
+#define PAD31_OE_HI 0
+#define PAD31_OE_SZ 1
+#define PAD31_PE_MSK 0x00000002
+#define PAD31_PE_I_MSK 0xfffffffd
+#define PAD31_PE_SFT 1
+#define PAD31_PE_HI 1
+#define PAD31_PE_SZ 1
+#define PAD31_DS_MSK 0x00000004
+#define PAD31_DS_I_MSK 0xfffffffb
+#define PAD31_DS_SFT 2
+#define PAD31_DS_HI 2
+#define PAD31_DS_SZ 1
+#define PAD31_IE_MSK 0x00000008
+#define PAD31_IE_I_MSK 0xfffffff7
+#define PAD31_IE_SFT 3
+#define PAD31_IE_HI 3
+#define PAD31_IE_SZ 1
+#define PAD31_SEL_I_MSK 0x00000030
+#define PAD31_SEL_I_I_MSK 0xffffffcf
+#define PAD31_SEL_I_SFT 4
+#define PAD31_SEL_I_HI 5
+#define PAD31_SEL_I_SZ 2
+#define PAD31_OD_MSK 0x00000100
+#define PAD31_OD_I_MSK 0xfffffeff
+#define PAD31_OD_SFT 8
+#define PAD31_OD_HI 8
+#define PAD31_OD_SZ 1
+#define PAD31_SEL_O_MSK 0x00003000
+#define PAD31_SEL_O_I_MSK 0xffffcfff
+#define PAD31_SEL_O_SFT 12
+#define PAD31_SEL_O_HI 13
+#define PAD31_SEL_O_SZ 2
+#define TEST_7_ID_MSK 0x10000000
+#define TEST_7_ID_I_MSK 0xefffffff
+#define TEST_7_ID_SFT 28
+#define TEST_7_ID_HI 28
+#define TEST_7_ID_SZ 1
+#define PAD32_OE_MSK 0x00000001
+#define PAD32_OE_I_MSK 0xfffffffe
+#define PAD32_OE_SFT 0
+#define PAD32_OE_HI 0
+#define PAD32_OE_SZ 1
+#define PAD32_PE_MSK 0x00000002
+#define PAD32_PE_I_MSK 0xfffffffd
+#define PAD32_PE_SFT 1
+#define PAD32_PE_HI 1
+#define PAD32_PE_SZ 1
+#define PAD32_DS_MSK 0x00000004
+#define PAD32_DS_I_MSK 0xfffffffb
+#define PAD32_DS_SFT 2
+#define PAD32_DS_HI 2
+#define PAD32_DS_SZ 1
+#define PAD32_IE_MSK 0x00000008
+#define PAD32_IE_I_MSK 0xfffffff7
+#define PAD32_IE_SFT 3
+#define PAD32_IE_HI 3
+#define PAD32_IE_SZ 1
+#define PAD32_SEL_I_MSK 0x00000030
+#define PAD32_SEL_I_I_MSK 0xffffffcf
+#define PAD32_SEL_I_SFT 4
+#define PAD32_SEL_I_HI 5
+#define PAD32_SEL_I_SZ 2
+#define PAD32_OD_MSK 0x00000100
+#define PAD32_OD_I_MSK 0xfffffeff
+#define PAD32_OD_SFT 8
+#define PAD32_OD_HI 8
+#define PAD32_OD_SZ 1
+#define PAD32_SEL_O_MSK 0x00003000
+#define PAD32_SEL_O_I_MSK 0xffffcfff
+#define PAD32_SEL_O_SFT 12
+#define PAD32_SEL_O_HI 13
+#define PAD32_SEL_O_SZ 2
+#define TEST_8_ID_MSK 0x10000000
+#define TEST_8_ID_I_MSK 0xefffffff
+#define TEST_8_ID_SFT 28
+#define TEST_8_ID_HI 28
+#define TEST_8_ID_SZ 1
+#define PAD33_OE_MSK 0x00000001
+#define PAD33_OE_I_MSK 0xfffffffe
+#define PAD33_OE_SFT 0
+#define PAD33_OE_HI 0
+#define PAD33_OE_SZ 1
+#define PAD33_PE_MSK 0x00000002
+#define PAD33_PE_I_MSK 0xfffffffd
+#define PAD33_PE_SFT 1
+#define PAD33_PE_HI 1
+#define PAD33_PE_SZ 1
+#define PAD33_DS_MSK 0x00000004
+#define PAD33_DS_I_MSK 0xfffffffb
+#define PAD33_DS_SFT 2
+#define PAD33_DS_HI 2
+#define PAD33_DS_SZ 1
+#define PAD33_IE_MSK 0x00000008
+#define PAD33_IE_I_MSK 0xfffffff7
+#define PAD33_IE_SFT 3
+#define PAD33_IE_HI 3
+#define PAD33_IE_SZ 1
+#define PAD33_SEL_I_MSK 0x00000030
+#define PAD33_SEL_I_I_MSK 0xffffffcf
+#define PAD33_SEL_I_SFT 4
+#define PAD33_SEL_I_HI 5
+#define PAD33_SEL_I_SZ 2
+#define PAD33_OD_MSK 0x00000100
+#define PAD33_OD_I_MSK 0xfffffeff
+#define PAD33_OD_SFT 8
+#define PAD33_OD_HI 8
+#define PAD33_OD_SZ 1
+#define PAD33_SEL_O_MSK 0x00003000
+#define PAD33_SEL_O_I_MSK 0xffffcfff
+#define PAD33_SEL_O_SFT 12
+#define PAD33_SEL_O_HI 13
+#define PAD33_SEL_O_SZ 2
+#define TEST_9_ID_MSK 0x10000000
+#define TEST_9_ID_I_MSK 0xefffffff
+#define TEST_9_ID_SFT 28
+#define TEST_9_ID_HI 28
+#define TEST_9_ID_SZ 1
+#define PAD34_OE_MSK 0x00000001
+#define PAD34_OE_I_MSK 0xfffffffe
+#define PAD34_OE_SFT 0
+#define PAD34_OE_HI 0
+#define PAD34_OE_SZ 1
+#define PAD34_PE_MSK 0x00000002
+#define PAD34_PE_I_MSK 0xfffffffd
+#define PAD34_PE_SFT 1
+#define PAD34_PE_HI 1
+#define PAD34_PE_SZ 1
+#define PAD34_DS_MSK 0x00000004
+#define PAD34_DS_I_MSK 0xfffffffb
+#define PAD34_DS_SFT 2
+#define PAD34_DS_HI 2
+#define PAD34_DS_SZ 1
+#define PAD34_IE_MSK 0x00000008
+#define PAD34_IE_I_MSK 0xfffffff7
+#define PAD34_IE_SFT 3
+#define PAD34_IE_HI 3
+#define PAD34_IE_SZ 1
+#define PAD34_SEL_I_MSK 0x00000030
+#define PAD34_SEL_I_I_MSK 0xffffffcf
+#define PAD34_SEL_I_SFT 4
+#define PAD34_SEL_I_HI 5
+#define PAD34_SEL_I_SZ 2
+#define PAD34_OD_MSK 0x00000100
+#define PAD34_OD_I_MSK 0xfffffeff
+#define PAD34_OD_SFT 8
+#define PAD34_OD_HI 8
+#define PAD34_OD_SZ 1
+#define PAD34_SEL_O_MSK 0x00003000
+#define PAD34_SEL_O_I_MSK 0xffffcfff
+#define PAD34_SEL_O_SFT 12
+#define PAD34_SEL_O_HI 13
+#define PAD34_SEL_O_SZ 2
+#define TEST_10_ID_MSK 0x10000000
+#define TEST_10_ID_I_MSK 0xefffffff
+#define TEST_10_ID_SFT 28
+#define TEST_10_ID_HI 28
+#define TEST_10_ID_SZ 1
+#define PAD42_OE_MSK 0x00000001
+#define PAD42_OE_I_MSK 0xfffffffe
+#define PAD42_OE_SFT 0
+#define PAD42_OE_HI 0
+#define PAD42_OE_SZ 1
+#define PAD42_PE_MSK 0x00000002
+#define PAD42_PE_I_MSK 0xfffffffd
+#define PAD42_PE_SFT 1
+#define PAD42_PE_HI 1
+#define PAD42_PE_SZ 1
+#define PAD42_DS_MSK 0x00000004
+#define PAD42_DS_I_MSK 0xfffffffb
+#define PAD42_DS_SFT 2
+#define PAD42_DS_HI 2
+#define PAD42_DS_SZ 1
+#define PAD42_IE_MSK 0x00000008
+#define PAD42_IE_I_MSK 0xfffffff7
+#define PAD42_IE_SFT 3
+#define PAD42_IE_HI 3
+#define PAD42_IE_SZ 1
+#define PAD42_SEL_I_MSK 0x00000030
+#define PAD42_SEL_I_I_MSK 0xffffffcf
+#define PAD42_SEL_I_SFT 4
+#define PAD42_SEL_I_HI 5
+#define PAD42_SEL_I_SZ 2
+#define PAD42_OD_MSK 0x00000100
+#define PAD42_OD_I_MSK 0xfffffeff
+#define PAD42_OD_SFT 8
+#define PAD42_OD_HI 8
+#define PAD42_OD_SZ 1
+#define PAD42_SEL_O_MSK 0x00001000
+#define PAD42_SEL_O_I_MSK 0xffffefff
+#define PAD42_SEL_O_SFT 12
+#define PAD42_SEL_O_HI 12
+#define PAD42_SEL_O_SZ 1
+#define TEST_11_ID_MSK 0x10000000
+#define TEST_11_ID_I_MSK 0xefffffff
+#define TEST_11_ID_SFT 28
+#define TEST_11_ID_HI 28
+#define TEST_11_ID_SZ 1
+#define PAD43_OE_MSK 0x00000001
+#define PAD43_OE_I_MSK 0xfffffffe
+#define PAD43_OE_SFT 0
+#define PAD43_OE_HI 0
+#define PAD43_OE_SZ 1
+#define PAD43_PE_MSK 0x00000002
+#define PAD43_PE_I_MSK 0xfffffffd
+#define PAD43_PE_SFT 1
+#define PAD43_PE_HI 1
+#define PAD43_PE_SZ 1
+#define PAD43_DS_MSK 0x00000004
+#define PAD43_DS_I_MSK 0xfffffffb
+#define PAD43_DS_SFT 2
+#define PAD43_DS_HI 2
+#define PAD43_DS_SZ 1
+#define PAD43_IE_MSK 0x00000008
+#define PAD43_IE_I_MSK 0xfffffff7
+#define PAD43_IE_SFT 3
+#define PAD43_IE_HI 3
+#define PAD43_IE_SZ 1
+#define PAD43_SEL_I_MSK 0x00000030
+#define PAD43_SEL_I_I_MSK 0xffffffcf
+#define PAD43_SEL_I_SFT 4
+#define PAD43_SEL_I_HI 5
+#define PAD43_SEL_I_SZ 2
+#define PAD43_OD_MSK 0x00000100
+#define PAD43_OD_I_MSK 0xfffffeff
+#define PAD43_OD_SFT 8
+#define PAD43_OD_HI 8
+#define PAD43_OD_SZ 1
+#define PAD43_SEL_O_MSK 0x00001000
+#define PAD43_SEL_O_I_MSK 0xffffefff
+#define PAD43_SEL_O_SFT 12
+#define PAD43_SEL_O_HI 12
+#define PAD43_SEL_O_SZ 1
+#define TEST_12_ID_MSK 0x10000000
+#define TEST_12_ID_I_MSK 0xefffffff
+#define TEST_12_ID_SFT 28
+#define TEST_12_ID_HI 28
+#define TEST_12_ID_SZ 1
+#define PAD44_OE_MSK 0x00000001
+#define PAD44_OE_I_MSK 0xfffffffe
+#define PAD44_OE_SFT 0
+#define PAD44_OE_HI 0
+#define PAD44_OE_SZ 1
+#define PAD44_PE_MSK 0x00000002
+#define PAD44_PE_I_MSK 0xfffffffd
+#define PAD44_PE_SFT 1
+#define PAD44_PE_HI 1
+#define PAD44_PE_SZ 1
+#define PAD44_DS_MSK 0x00000004
+#define PAD44_DS_I_MSK 0xfffffffb
+#define PAD44_DS_SFT 2
+#define PAD44_DS_HI 2
+#define PAD44_DS_SZ 1
+#define PAD44_IE_MSK 0x00000008
+#define PAD44_IE_I_MSK 0xfffffff7
+#define PAD44_IE_SFT 3
+#define PAD44_IE_HI 3
+#define PAD44_IE_SZ 1
+#define PAD44_SEL_I_MSK 0x00000030
+#define PAD44_SEL_I_I_MSK 0xffffffcf
+#define PAD44_SEL_I_SFT 4
+#define PAD44_SEL_I_HI 5
+#define PAD44_SEL_I_SZ 2
+#define PAD44_OD_MSK 0x00000100
+#define PAD44_OD_I_MSK 0xfffffeff
+#define PAD44_OD_SFT 8
+#define PAD44_OD_HI 8
+#define PAD44_OD_SZ 1
+#define PAD44_SEL_O_MSK 0x00003000
+#define PAD44_SEL_O_I_MSK 0xffffcfff
+#define PAD44_SEL_O_SFT 12
+#define PAD44_SEL_O_HI 13
+#define PAD44_SEL_O_SZ 2
+#define TEST_13_ID_MSK 0x10000000
+#define TEST_13_ID_I_MSK 0xefffffff
+#define TEST_13_ID_SFT 28
+#define TEST_13_ID_HI 28
+#define TEST_13_ID_SZ 1
+#define PAD45_OE_MSK 0x00000001
+#define PAD45_OE_I_MSK 0xfffffffe
+#define PAD45_OE_SFT 0
+#define PAD45_OE_HI 0
+#define PAD45_OE_SZ 1
+#define PAD45_PE_MSK 0x00000002
+#define PAD45_PE_I_MSK 0xfffffffd
+#define PAD45_PE_SFT 1
+#define PAD45_PE_HI 1
+#define PAD45_PE_SZ 1
+#define PAD45_DS_MSK 0x00000004
+#define PAD45_DS_I_MSK 0xfffffffb
+#define PAD45_DS_SFT 2
+#define PAD45_DS_HI 2
+#define PAD45_DS_SZ 1
+#define PAD45_IE_MSK 0x00000008
+#define PAD45_IE_I_MSK 0xfffffff7
+#define PAD45_IE_SFT 3
+#define PAD45_IE_HI 3
+#define PAD45_IE_SZ 1
+#define PAD45_SEL_I_MSK 0x00000030
+#define PAD45_SEL_I_I_MSK 0xffffffcf
+#define PAD45_SEL_I_SFT 4
+#define PAD45_SEL_I_HI 5
+#define PAD45_SEL_I_SZ 2
+#define PAD45_OD_MSK 0x00000100
+#define PAD45_OD_I_MSK 0xfffffeff
+#define PAD45_OD_SFT 8
+#define PAD45_OD_HI 8
+#define PAD45_OD_SZ 1
+#define PAD45_SEL_O_MSK 0x00003000
+#define PAD45_SEL_O_I_MSK 0xffffcfff
+#define PAD45_SEL_O_SFT 12
+#define PAD45_SEL_O_HI 13
+#define PAD45_SEL_O_SZ 2
+#define TEST_14_ID_MSK 0x10000000
+#define TEST_14_ID_I_MSK 0xefffffff
+#define TEST_14_ID_SFT 28
+#define TEST_14_ID_HI 28
+#define TEST_14_ID_SZ 1
+#define PAD46_OE_MSK 0x00000001
+#define PAD46_OE_I_MSK 0xfffffffe
+#define PAD46_OE_SFT 0
+#define PAD46_OE_HI 0
+#define PAD46_OE_SZ 1
+#define PAD46_PE_MSK 0x00000002
+#define PAD46_PE_I_MSK 0xfffffffd
+#define PAD46_PE_SFT 1
+#define PAD46_PE_HI 1
+#define PAD46_PE_SZ 1
+#define PAD46_DS_MSK 0x00000004
+#define PAD46_DS_I_MSK 0xfffffffb
+#define PAD46_DS_SFT 2
+#define PAD46_DS_HI 2
+#define PAD46_DS_SZ 1
+#define PAD46_IE_MSK 0x00000008
+#define PAD46_IE_I_MSK 0xfffffff7
+#define PAD46_IE_SFT 3
+#define PAD46_IE_HI 3
+#define PAD46_IE_SZ 1
+#define PAD46_SEL_I_MSK 0x00000030
+#define PAD46_SEL_I_I_MSK 0xffffffcf
+#define PAD46_SEL_I_SFT 4
+#define PAD46_SEL_I_HI 5
+#define PAD46_SEL_I_SZ 2
+#define PAD46_OD_MSK 0x00000100
+#define PAD46_OD_I_MSK 0xfffffeff
+#define PAD46_OD_SFT 8
+#define PAD46_OD_HI 8
+#define PAD46_OD_SZ 1
+#define PAD46_SEL_O_MSK 0x00003000
+#define PAD46_SEL_O_I_MSK 0xffffcfff
+#define PAD46_SEL_O_SFT 12
+#define PAD46_SEL_O_HI 13
+#define PAD46_SEL_O_SZ 2
+#define TEST_15_ID_MSK 0x10000000
+#define TEST_15_ID_I_MSK 0xefffffff
+#define TEST_15_ID_SFT 28
+#define TEST_15_ID_HI 28
+#define TEST_15_ID_SZ 1
+#define PAD47_OE_MSK 0x00000001
+#define PAD47_OE_I_MSK 0xfffffffe
+#define PAD47_OE_SFT 0
+#define PAD47_OE_HI 0
+#define PAD47_OE_SZ 1
+#define PAD47_PE_MSK 0x00000002
+#define PAD47_PE_I_MSK 0xfffffffd
+#define PAD47_PE_SFT 1
+#define PAD47_PE_HI 1
+#define PAD47_PE_SZ 1
+#define PAD47_DS_MSK 0x00000004
+#define PAD47_DS_I_MSK 0xfffffffb
+#define PAD47_DS_SFT 2
+#define PAD47_DS_HI 2
+#define PAD47_DS_SZ 1
+#define PAD47_SEL_I_MSK 0x00000030
+#define PAD47_SEL_I_I_MSK 0xffffffcf
+#define PAD47_SEL_I_SFT 4
+#define PAD47_SEL_I_HI 5
+#define PAD47_SEL_I_SZ 2
+#define PAD47_OD_MSK 0x00000100
+#define PAD47_OD_I_MSK 0xfffffeff
+#define PAD47_OD_SFT 8
+#define PAD47_OD_HI 8
+#define PAD47_OD_SZ 1
+#define PAD47_SEL_O_MSK 0x00003000
+#define PAD47_SEL_O_I_MSK 0xffffcfff
+#define PAD47_SEL_O_SFT 12
+#define PAD47_SEL_O_HI 13
+#define PAD47_SEL_O_SZ 2
+#define PAD47_SEL_OE_MSK 0x00100000
+#define PAD47_SEL_OE_I_MSK 0xffefffff
+#define PAD47_SEL_OE_SFT 20
+#define PAD47_SEL_OE_HI 20
+#define PAD47_SEL_OE_SZ 1
+#define GPIO_9_ID_MSK 0x10000000
+#define GPIO_9_ID_I_MSK 0xefffffff
+#define GPIO_9_ID_SFT 28
+#define GPIO_9_ID_HI 28
+#define GPIO_9_ID_SZ 1
+#define PAD48_OE_MSK 0x00000001
+#define PAD48_OE_I_MSK 0xfffffffe
+#define PAD48_OE_SFT 0
+#define PAD48_OE_HI 0
+#define PAD48_OE_SZ 1
+#define PAD48_PE_MSK 0x00000002
+#define PAD48_PE_I_MSK 0xfffffffd
+#define PAD48_PE_SFT 1
+#define PAD48_PE_HI 1
+#define PAD48_PE_SZ 1
+#define PAD48_DS_MSK 0x00000004
+#define PAD48_DS_I_MSK 0xfffffffb
+#define PAD48_DS_SFT 2
+#define PAD48_DS_HI 2
+#define PAD48_DS_SZ 1
+#define PAD48_IE_MSK 0x00000008
+#define PAD48_IE_I_MSK 0xfffffff7
+#define PAD48_IE_SFT 3
+#define PAD48_IE_HI 3
+#define PAD48_IE_SZ 1
+#define PAD48_SEL_I_MSK 0x00000070
+#define PAD48_SEL_I_I_MSK 0xffffff8f
+#define PAD48_SEL_I_SFT 4
+#define PAD48_SEL_I_HI 6
+#define PAD48_SEL_I_SZ 3
+#define PAD48_OD_MSK 0x00000100
+#define PAD48_OD_I_MSK 0xfffffeff
+#define PAD48_OD_SFT 8
+#define PAD48_OD_HI 8
+#define PAD48_OD_SZ 1
+#define PAD48_PE_SEL_MSK 0x00000800
+#define PAD48_PE_SEL_I_MSK 0xfffff7ff
+#define PAD48_PE_SEL_SFT 11
+#define PAD48_PE_SEL_HI 11
+#define PAD48_PE_SEL_SZ 1
+#define PAD48_SEL_O_MSK 0x00003000
+#define PAD48_SEL_O_I_MSK 0xffffcfff
+#define PAD48_SEL_O_SFT 12
+#define PAD48_SEL_O_HI 13
+#define PAD48_SEL_O_SZ 2
+#define PAD48_SEL_OE_MSK 0x00100000
+#define PAD48_SEL_OE_I_MSK 0xffefffff
+#define PAD48_SEL_OE_SFT 20
+#define PAD48_SEL_OE_HI 20
+#define PAD48_SEL_OE_SZ 1
+#define GPIO_10_ID_MSK 0x10000000
+#define GPIO_10_ID_I_MSK 0xefffffff
+#define GPIO_10_ID_SFT 28
+#define GPIO_10_ID_HI 28
+#define GPIO_10_ID_SZ 1
+#define PAD49_OE_MSK 0x00000001
+#define PAD49_OE_I_MSK 0xfffffffe
+#define PAD49_OE_SFT 0
+#define PAD49_OE_HI 0
+#define PAD49_OE_SZ 1
+#define PAD49_PE_MSK 0x00000002
+#define PAD49_PE_I_MSK 0xfffffffd
+#define PAD49_PE_SFT 1
+#define PAD49_PE_HI 1
+#define PAD49_PE_SZ 1
+#define PAD49_DS_MSK 0x00000004
+#define PAD49_DS_I_MSK 0xfffffffb
+#define PAD49_DS_SFT 2
+#define PAD49_DS_HI 2
+#define PAD49_DS_SZ 1
+#define PAD49_IE_MSK 0x00000008
+#define PAD49_IE_I_MSK 0xfffffff7
+#define PAD49_IE_SFT 3
+#define PAD49_IE_HI 3
+#define PAD49_IE_SZ 1
+#define PAD49_SEL_I_MSK 0x00000070
+#define PAD49_SEL_I_I_MSK 0xffffff8f
+#define PAD49_SEL_I_SFT 4
+#define PAD49_SEL_I_HI 6
+#define PAD49_SEL_I_SZ 3
+#define PAD49_OD_MSK 0x00000100
+#define PAD49_OD_I_MSK 0xfffffeff
+#define PAD49_OD_SFT 8
+#define PAD49_OD_HI 8
+#define PAD49_OD_SZ 1
+#define PAD49_SEL_O_MSK 0x00003000
+#define PAD49_SEL_O_I_MSK 0xffffcfff
+#define PAD49_SEL_O_SFT 12
+#define PAD49_SEL_O_HI 13
+#define PAD49_SEL_O_SZ 2
+#define PAD49_SEL_OE_MSK 0x00100000
+#define PAD49_SEL_OE_I_MSK 0xffefffff
+#define PAD49_SEL_OE_SFT 20
+#define PAD49_SEL_OE_HI 20
+#define PAD49_SEL_OE_SZ 1
+#define GPIO_11_ID_MSK 0x10000000
+#define GPIO_11_ID_I_MSK 0xefffffff
+#define GPIO_11_ID_SFT 28
+#define GPIO_11_ID_HI 28
+#define GPIO_11_ID_SZ 1
+#define PAD50_OE_MSK 0x00000001
+#define PAD50_OE_I_MSK 0xfffffffe
+#define PAD50_OE_SFT 0
+#define PAD50_OE_HI 0
+#define PAD50_OE_SZ 1
+#define PAD50_PE_MSK 0x00000002
+#define PAD50_PE_I_MSK 0xfffffffd
+#define PAD50_PE_SFT 1
+#define PAD50_PE_HI 1
+#define PAD50_PE_SZ 1
+#define PAD50_DS_MSK 0x00000004
+#define PAD50_DS_I_MSK 0xfffffffb
+#define PAD50_DS_SFT 2
+#define PAD50_DS_HI 2
+#define PAD50_DS_SZ 1
+#define PAD50_IE_MSK 0x00000008
+#define PAD50_IE_I_MSK 0xfffffff7
+#define PAD50_IE_SFT 3
+#define PAD50_IE_HI 3
+#define PAD50_IE_SZ 1
+#define PAD50_SEL_I_MSK 0x00000070
+#define PAD50_SEL_I_I_MSK 0xffffff8f
+#define PAD50_SEL_I_SFT 4
+#define PAD50_SEL_I_HI 6
+#define PAD50_SEL_I_SZ 3
+#define PAD50_OD_MSK 0x00000100
+#define PAD50_OD_I_MSK 0xfffffeff
+#define PAD50_OD_SFT 8
+#define PAD50_OD_HI 8
+#define PAD50_OD_SZ 1
+#define PAD50_SEL_O_MSK 0x00003000
+#define PAD50_SEL_O_I_MSK 0xffffcfff
+#define PAD50_SEL_O_SFT 12
+#define PAD50_SEL_O_HI 13
+#define PAD50_SEL_O_SZ 2
+#define PAD50_SEL_OE_MSK 0x00100000
+#define PAD50_SEL_OE_I_MSK 0xffefffff
+#define PAD50_SEL_OE_SFT 20
+#define PAD50_SEL_OE_HI 20
+#define PAD50_SEL_OE_SZ 1
+#define GPIO_12_ID_MSK 0x10000000
+#define GPIO_12_ID_I_MSK 0xefffffff
+#define GPIO_12_ID_SFT 28
+#define GPIO_12_ID_HI 28
+#define GPIO_12_ID_SZ 1
+#define PAD51_OE_MSK 0x00000001
+#define PAD51_OE_I_MSK 0xfffffffe
+#define PAD51_OE_SFT 0
+#define PAD51_OE_HI 0
+#define PAD51_OE_SZ 1
+#define PAD51_PE_MSK 0x00000002
+#define PAD51_PE_I_MSK 0xfffffffd
+#define PAD51_PE_SFT 1
+#define PAD51_PE_HI 1
+#define PAD51_PE_SZ 1
+#define PAD51_DS_MSK 0x00000004
+#define PAD51_DS_I_MSK 0xfffffffb
+#define PAD51_DS_SFT 2
+#define PAD51_DS_HI 2
+#define PAD51_DS_SZ 1
+#define PAD51_IE_MSK 0x00000008
+#define PAD51_IE_I_MSK 0xfffffff7
+#define PAD51_IE_SFT 3
+#define PAD51_IE_HI 3
+#define PAD51_IE_SZ 1
+#define PAD51_SEL_I_MSK 0x00000030
+#define PAD51_SEL_I_I_MSK 0xffffffcf
+#define PAD51_SEL_I_SFT 4
+#define PAD51_SEL_I_HI 5
+#define PAD51_SEL_I_SZ 2
+#define PAD51_OD_MSK 0x00000100
+#define PAD51_OD_I_MSK 0xfffffeff
+#define PAD51_OD_SFT 8
+#define PAD51_OD_HI 8
+#define PAD51_OD_SZ 1
+#define PAD51_SEL_O_MSK 0x00001000
+#define PAD51_SEL_O_I_MSK 0xffffefff
+#define PAD51_SEL_O_SFT 12
+#define PAD51_SEL_O_HI 12
+#define PAD51_SEL_O_SZ 1
+#define PAD51_SEL_OE_MSK 0x00100000
+#define PAD51_SEL_OE_I_MSK 0xffefffff
+#define PAD51_SEL_OE_SFT 20
+#define PAD51_SEL_OE_HI 20
+#define PAD51_SEL_OE_SZ 1
+#define GPIO_13_ID_MSK 0x10000000
+#define GPIO_13_ID_I_MSK 0xefffffff
+#define GPIO_13_ID_SFT 28
+#define GPIO_13_ID_HI 28
+#define GPIO_13_ID_SZ 1
+#define PAD52_OE_MSK 0x00000001
+#define PAD52_OE_I_MSK 0xfffffffe
+#define PAD52_OE_SFT 0
+#define PAD52_OE_HI 0
+#define PAD52_OE_SZ 1
+#define PAD52_PE_MSK 0x00000002
+#define PAD52_PE_I_MSK 0xfffffffd
+#define PAD52_PE_SFT 1
+#define PAD52_PE_HI 1
+#define PAD52_PE_SZ 1
+#define PAD52_DS_MSK 0x00000004
+#define PAD52_DS_I_MSK 0xfffffffb
+#define PAD52_DS_SFT 2
+#define PAD52_DS_HI 2
+#define PAD52_DS_SZ 1
+#define PAD52_SEL_I_MSK 0x00000030
+#define PAD52_SEL_I_I_MSK 0xffffffcf
+#define PAD52_SEL_I_SFT 4
+#define PAD52_SEL_I_HI 5
+#define PAD52_SEL_I_SZ 2
+#define PAD52_OD_MSK 0x00000100
+#define PAD52_OD_I_MSK 0xfffffeff
+#define PAD52_OD_SFT 8
+#define PAD52_OD_HI 8
+#define PAD52_OD_SZ 1
+#define PAD52_SEL_O_MSK 0x00001000
+#define PAD52_SEL_O_I_MSK 0xffffefff
+#define PAD52_SEL_O_SFT 12
+#define PAD52_SEL_O_HI 12
+#define PAD52_SEL_O_SZ 1
+#define PAD52_SEL_OE_MSK 0x00100000
+#define PAD52_SEL_OE_I_MSK 0xffefffff
+#define PAD52_SEL_OE_SFT 20
+#define PAD52_SEL_OE_HI 20
+#define PAD52_SEL_OE_SZ 1
+#define GPIO_14_ID_MSK 0x10000000
+#define GPIO_14_ID_I_MSK 0xefffffff
+#define GPIO_14_ID_SFT 28
+#define GPIO_14_ID_HI 28
+#define GPIO_14_ID_SZ 1
+#define PAD53_OE_MSK 0x00000001
+#define PAD53_OE_I_MSK 0xfffffffe
+#define PAD53_OE_SFT 0
+#define PAD53_OE_HI 0
+#define PAD53_OE_SZ 1
+#define PAD53_PE_MSK 0x00000002
+#define PAD53_PE_I_MSK 0xfffffffd
+#define PAD53_PE_SFT 1
+#define PAD53_PE_HI 1
+#define PAD53_PE_SZ 1
+#define PAD53_DS_MSK 0x00000004
+#define PAD53_DS_I_MSK 0xfffffffb
+#define PAD53_DS_SFT 2
+#define PAD53_DS_HI 2
+#define PAD53_DS_SZ 1
+#define PAD53_IE_MSK 0x00000008
+#define PAD53_IE_I_MSK 0xfffffff7
+#define PAD53_IE_SFT 3
+#define PAD53_IE_HI 3
+#define PAD53_IE_SZ 1
+#define PAD53_SEL_I_MSK 0x00000030
+#define PAD53_SEL_I_I_MSK 0xffffffcf
+#define PAD53_SEL_I_SFT 4
+#define PAD53_SEL_I_HI 5
+#define PAD53_SEL_I_SZ 2
+#define PAD53_OD_MSK 0x00000100
+#define PAD53_OD_I_MSK 0xfffffeff
+#define PAD53_OD_SFT 8
+#define PAD53_OD_HI 8
+#define PAD53_OD_SZ 1
+#define PAD53_SEL_O_MSK 0x00001000
+#define PAD53_SEL_O_I_MSK 0xffffefff
+#define PAD53_SEL_O_SFT 12
+#define PAD53_SEL_O_HI 12
+#define PAD53_SEL_O_SZ 1
+#define JTAG_TMS_ID_MSK 0x10000000
+#define JTAG_TMS_ID_I_MSK 0xefffffff
+#define JTAG_TMS_ID_SFT 28
+#define JTAG_TMS_ID_HI 28
+#define JTAG_TMS_ID_SZ 1
+#define PAD54_OE_MSK 0x00000001
+#define PAD54_OE_I_MSK 0xfffffffe
+#define PAD54_OE_SFT 0
+#define PAD54_OE_HI 0
+#define PAD54_OE_SZ 1
+#define PAD54_PE_MSK 0x00000002
+#define PAD54_PE_I_MSK 0xfffffffd
+#define PAD54_PE_SFT 1
+#define PAD54_PE_HI 1
+#define PAD54_PE_SZ 1
+#define PAD54_DS_MSK 0x00000004
+#define PAD54_DS_I_MSK 0xfffffffb
+#define PAD54_DS_SFT 2
+#define PAD54_DS_HI 2
+#define PAD54_DS_SZ 1
+#define PAD54_OD_MSK 0x00000100
+#define PAD54_OD_I_MSK 0xfffffeff
+#define PAD54_OD_SFT 8
+#define PAD54_OD_HI 8
+#define PAD54_OD_SZ 1
+#define PAD54_SEL_O_MSK 0x00003000
+#define PAD54_SEL_O_I_MSK 0xffffcfff
+#define PAD54_SEL_O_SFT 12
+#define PAD54_SEL_O_HI 13
+#define PAD54_SEL_O_SZ 2
+#define JTAG_TCK_ID_MSK 0x10000000
+#define JTAG_TCK_ID_I_MSK 0xefffffff
+#define JTAG_TCK_ID_SFT 28
+#define JTAG_TCK_ID_HI 28
+#define JTAG_TCK_ID_SZ 1
+#define PAD56_PE_MSK 0x00000002
+#define PAD56_PE_I_MSK 0xfffffffd
+#define PAD56_PE_SFT 1
+#define PAD56_PE_HI 1
+#define PAD56_PE_SZ 1
+#define PAD56_DS_MSK 0x00000004
+#define PAD56_DS_I_MSK 0xfffffffb
+#define PAD56_DS_SFT 2
+#define PAD56_DS_HI 2
+#define PAD56_DS_SZ 1
+#define PAD56_SEL_I_MSK 0x00000010
+#define PAD56_SEL_I_I_MSK 0xffffffef
+#define PAD56_SEL_I_SFT 4
+#define PAD56_SEL_I_HI 4
+#define PAD56_SEL_I_SZ 1
+#define PAD56_OD_MSK 0x00000100
+#define PAD56_OD_I_MSK 0xfffffeff
+#define PAD56_OD_SFT 8
+#define PAD56_OD_HI 8
+#define PAD56_OD_SZ 1
+#define JTAG_TDI_ID_MSK 0x10000000
+#define JTAG_TDI_ID_I_MSK 0xefffffff
+#define JTAG_TDI_ID_SFT 28
+#define JTAG_TDI_ID_HI 28
+#define JTAG_TDI_ID_SZ 1
+#define PAD57_OE_MSK 0x00000001
+#define PAD57_OE_I_MSK 0xfffffffe
+#define PAD57_OE_SFT 0
+#define PAD57_OE_HI 0
+#define PAD57_OE_SZ 1
+#define PAD57_PE_MSK 0x00000002
+#define PAD57_PE_I_MSK 0xfffffffd
+#define PAD57_PE_SFT 1
+#define PAD57_PE_HI 1
+#define PAD57_PE_SZ 1
+#define PAD57_DS_MSK 0x00000004
+#define PAD57_DS_I_MSK 0xfffffffb
+#define PAD57_DS_SFT 2
+#define PAD57_DS_HI 2
+#define PAD57_DS_SZ 1
+#define PAD57_IE_MSK 0x00000008
+#define PAD57_IE_I_MSK 0xfffffff7
+#define PAD57_IE_SFT 3
+#define PAD57_IE_HI 3
+#define PAD57_IE_SZ 1
+#define PAD57_SEL_I_MSK 0x00000030
+#define PAD57_SEL_I_I_MSK 0xffffffcf
+#define PAD57_SEL_I_SFT 4
+#define PAD57_SEL_I_HI 5
+#define PAD57_SEL_I_SZ 2
+#define PAD57_OD_MSK 0x00000100
+#define PAD57_OD_I_MSK 0xfffffeff
+#define PAD57_OD_SFT 8
+#define PAD57_OD_HI 8
+#define PAD57_OD_SZ 1
+#define PAD57_SEL_O_MSK 0x00003000
+#define PAD57_SEL_O_I_MSK 0xffffcfff
+#define PAD57_SEL_O_SFT 12
+#define PAD57_SEL_O_HI 13
+#define PAD57_SEL_O_SZ 2
+#define PAD57_SEL_OE_MSK 0x00100000
+#define PAD57_SEL_OE_I_MSK 0xffefffff
+#define PAD57_SEL_OE_SFT 20
+#define PAD57_SEL_OE_HI 20
+#define PAD57_SEL_OE_SZ 1
+#define JTAG_TDO_ID_MSK 0x10000000
+#define JTAG_TDO_ID_I_MSK 0xefffffff
+#define JTAG_TDO_ID_SFT 28
+#define JTAG_TDO_ID_HI 28
+#define JTAG_TDO_ID_SZ 1
+#define PAD58_OE_MSK 0x00000001
+#define PAD58_OE_I_MSK 0xfffffffe
+#define PAD58_OE_SFT 0
+#define PAD58_OE_HI 0
+#define PAD58_OE_SZ 1
+#define PAD58_PE_MSK 0x00000002
+#define PAD58_PE_I_MSK 0xfffffffd
+#define PAD58_PE_SFT 1
+#define PAD58_PE_HI 1
+#define PAD58_PE_SZ 1
+#define PAD58_DS_MSK 0x00000004
+#define PAD58_DS_I_MSK 0xfffffffb
+#define PAD58_DS_SFT 2
+#define PAD58_DS_HI 2
+#define PAD58_DS_SZ 1
+#define PAD58_IE_MSK 0x00000008
+#define PAD58_IE_I_MSK 0xfffffff7
+#define PAD58_IE_SFT 3
+#define PAD58_IE_HI 3
+#define PAD58_IE_SZ 1
+#define PAD58_SEL_I_MSK 0x00000030
+#define PAD58_SEL_I_I_MSK 0xffffffcf
+#define PAD58_SEL_I_SFT 4
+#define PAD58_SEL_I_HI 5
+#define PAD58_SEL_I_SZ 2
+#define PAD58_OD_MSK 0x00000100
+#define PAD58_OD_I_MSK 0xfffffeff
+#define PAD58_OD_SFT 8
+#define PAD58_OD_HI 8
+#define PAD58_OD_SZ 1
+#define PAD58_SEL_O_MSK 0x00001000
+#define PAD58_SEL_O_I_MSK 0xffffefff
+#define PAD58_SEL_O_SFT 12
+#define PAD58_SEL_O_HI 12
+#define PAD58_SEL_O_SZ 1
+#define TEST_16_ID_MSK 0x10000000
+#define TEST_16_ID_I_MSK 0xefffffff
+#define TEST_16_ID_SFT 28
+#define TEST_16_ID_HI 28
+#define TEST_16_ID_SZ 1
+#define PAD59_OE_MSK 0x00000001
+#define PAD59_OE_I_MSK 0xfffffffe
+#define PAD59_OE_SFT 0
+#define PAD59_OE_HI 0
+#define PAD59_OE_SZ 1
+#define PAD59_PE_MSK 0x00000002
+#define PAD59_PE_I_MSK 0xfffffffd
+#define PAD59_PE_SFT 1
+#define PAD59_PE_HI 1
+#define PAD59_PE_SZ 1
+#define PAD59_DS_MSK 0x00000004
+#define PAD59_DS_I_MSK 0xfffffffb
+#define PAD59_DS_SFT 2
+#define PAD59_DS_HI 2
+#define PAD59_DS_SZ 1
+#define PAD59_IE_MSK 0x00000008
+#define PAD59_IE_I_MSK 0xfffffff7
+#define PAD59_IE_SFT 3
+#define PAD59_IE_HI 3
+#define PAD59_IE_SZ 1
+#define PAD59_SEL_I_MSK 0x00000030
+#define PAD59_SEL_I_I_MSK 0xffffffcf
+#define PAD59_SEL_I_SFT 4
+#define PAD59_SEL_I_HI 5
+#define PAD59_SEL_I_SZ 2
+#define PAD59_OD_MSK 0x00000100
+#define PAD59_OD_I_MSK 0xfffffeff
+#define PAD59_OD_SFT 8
+#define PAD59_OD_HI 8
+#define PAD59_OD_SZ 1
+#define PAD59_SEL_O_MSK 0x00001000
+#define PAD59_SEL_O_I_MSK 0xffffefff
+#define PAD59_SEL_O_SFT 12
+#define PAD59_SEL_O_HI 12
+#define PAD59_SEL_O_SZ 1
+#define TEST_17_ID_MSK 0x10000000
+#define TEST_17_ID_I_MSK 0xefffffff
+#define TEST_17_ID_SFT 28
+#define TEST_17_ID_HI 28
+#define TEST_17_ID_SZ 1
+#define PAD60_OE_MSK 0x00000001
+#define PAD60_OE_I_MSK 0xfffffffe
+#define PAD60_OE_SFT 0
+#define PAD60_OE_HI 0
+#define PAD60_OE_SZ 1
+#define PAD60_PE_MSK 0x00000002
+#define PAD60_PE_I_MSK 0xfffffffd
+#define PAD60_PE_SFT 1
+#define PAD60_PE_HI 1
+#define PAD60_PE_SZ 1
+#define PAD60_DS_MSK 0x00000004
+#define PAD60_DS_I_MSK 0xfffffffb
+#define PAD60_DS_SFT 2
+#define PAD60_DS_HI 2
+#define PAD60_DS_SZ 1
+#define PAD60_IE_MSK 0x00000008
+#define PAD60_IE_I_MSK 0xfffffff7
+#define PAD60_IE_SFT 3
+#define PAD60_IE_HI 3
+#define PAD60_IE_SZ 1
+#define PAD60_SEL_I_MSK 0x00000030
+#define PAD60_SEL_I_I_MSK 0xffffffcf
+#define PAD60_SEL_I_SFT 4
+#define PAD60_SEL_I_HI 5
+#define PAD60_SEL_I_SZ 2
+#define PAD60_OD_MSK 0x00000100
+#define PAD60_OD_I_MSK 0xfffffeff
+#define PAD60_OD_SFT 8
+#define PAD60_OD_HI 8
+#define PAD60_OD_SZ 1
+#define PAD60_SEL_O_MSK 0x00001000
+#define PAD60_SEL_O_I_MSK 0xffffefff
+#define PAD60_SEL_O_SFT 12
+#define PAD60_SEL_O_HI 12
+#define PAD60_SEL_O_SZ 1
+#define TEST_18_ID_MSK 0x10000000
+#define TEST_18_ID_I_MSK 0xefffffff
+#define TEST_18_ID_SFT 28
+#define TEST_18_ID_HI 28
+#define TEST_18_ID_SZ 1
+#define PAD61_OE_MSK 0x00000001
+#define PAD61_OE_I_MSK 0xfffffffe
+#define PAD61_OE_SFT 0
+#define PAD61_OE_HI 0
+#define PAD61_OE_SZ 1
+#define PAD61_PE_MSK 0x00000002
+#define PAD61_PE_I_MSK 0xfffffffd
+#define PAD61_PE_SFT 1
+#define PAD61_PE_HI 1
+#define PAD61_PE_SZ 1
+#define PAD61_DS_MSK 0x00000004
+#define PAD61_DS_I_MSK 0xfffffffb
+#define PAD61_DS_SFT 2
+#define PAD61_DS_HI 2
+#define PAD61_DS_SZ 1
+#define PAD61_IE_MSK 0x00000008
+#define PAD61_IE_I_MSK 0xfffffff7
+#define PAD61_IE_SFT 3
+#define PAD61_IE_HI 3
+#define PAD61_IE_SZ 1
+#define PAD61_SEL_I_MSK 0x00000010
+#define PAD61_SEL_I_I_MSK 0xffffffef
+#define PAD61_SEL_I_SFT 4
+#define PAD61_SEL_I_HI 4
+#define PAD61_SEL_I_SZ 1
+#define PAD61_OD_MSK 0x00000100
+#define PAD61_OD_I_MSK 0xfffffeff
+#define PAD61_OD_SFT 8
+#define PAD61_OD_HI 8
+#define PAD61_OD_SZ 1
+#define PAD61_SEL_O_MSK 0x00003000
+#define PAD61_SEL_O_I_MSK 0xffffcfff
+#define PAD61_SEL_O_SFT 12
+#define PAD61_SEL_O_HI 13
+#define PAD61_SEL_O_SZ 2
+#define TEST_19_ID_MSK 0x10000000
+#define TEST_19_ID_I_MSK 0xefffffff
+#define TEST_19_ID_SFT 28
+#define TEST_19_ID_HI 28
+#define TEST_19_ID_SZ 1
+#define PAD62_OE_MSK 0x00000001
+#define PAD62_OE_I_MSK 0xfffffffe
+#define PAD62_OE_SFT 0
+#define PAD62_OE_HI 0
+#define PAD62_OE_SZ 1
+#define PAD62_PE_MSK 0x00000002
+#define PAD62_PE_I_MSK 0xfffffffd
+#define PAD62_PE_SFT 1
+#define PAD62_PE_HI 1
+#define PAD62_PE_SZ 1
+#define PAD62_DS_MSK 0x00000004
+#define PAD62_DS_I_MSK 0xfffffffb
+#define PAD62_DS_SFT 2
+#define PAD62_DS_HI 2
+#define PAD62_DS_SZ 1
+#define PAD62_IE_MSK 0x00000008
+#define PAD62_IE_I_MSK 0xfffffff7
+#define PAD62_IE_SFT 3
+#define PAD62_IE_HI 3
+#define PAD62_IE_SZ 1
+#define PAD62_SEL_I_MSK 0x00000010
+#define PAD62_SEL_I_I_MSK 0xffffffef
+#define PAD62_SEL_I_SFT 4
+#define PAD62_SEL_I_HI 4
+#define PAD62_SEL_I_SZ 1
+#define PAD62_OD_MSK 0x00000100
+#define PAD62_OD_I_MSK 0xfffffeff
+#define PAD62_OD_SFT 8
+#define PAD62_OD_HI 8
+#define PAD62_OD_SZ 1
+#define PAD62_SEL_O_MSK 0x00001000
+#define PAD62_SEL_O_I_MSK 0xffffefff
+#define PAD62_SEL_O_SFT 12
+#define PAD62_SEL_O_HI 12
+#define PAD62_SEL_O_SZ 1
+#define TEST_20_ID_MSK 0x10000000
+#define TEST_20_ID_I_MSK 0xefffffff
+#define TEST_20_ID_SFT 28
+#define TEST_20_ID_HI 28
+#define TEST_20_ID_SZ 1
+#define PAD64_OE_MSK 0x00000001
+#define PAD64_OE_I_MSK 0xfffffffe
+#define PAD64_OE_SFT 0
+#define PAD64_OE_HI 0
+#define PAD64_OE_SZ 1
+#define PAD64_PE_MSK 0x00000002
+#define PAD64_PE_I_MSK 0xfffffffd
+#define PAD64_PE_SFT 1
+#define PAD64_PE_HI 1
+#define PAD64_PE_SZ 1
+#define PAD64_DS_MSK 0x00000004
+#define PAD64_DS_I_MSK 0xfffffffb
+#define PAD64_DS_SFT 2
+#define PAD64_DS_HI 2
+#define PAD64_DS_SZ 1
+#define PAD64_IE_MSK 0x00000008
+#define PAD64_IE_I_MSK 0xfffffff7
+#define PAD64_IE_SFT 3
+#define PAD64_IE_HI 3
+#define PAD64_IE_SZ 1
+#define PAD64_SEL_I_MSK 0x00000070
+#define PAD64_SEL_I_I_MSK 0xffffff8f
+#define PAD64_SEL_I_SFT 4
+#define PAD64_SEL_I_HI 6
+#define PAD64_SEL_I_SZ 3
+#define PAD64_OD_MSK 0x00000100
+#define PAD64_OD_I_MSK 0xfffffeff
+#define PAD64_OD_SFT 8
+#define PAD64_OD_HI 8
+#define PAD64_OD_SZ 1
+#define PAD64_SEL_O_MSK 0x00003000
+#define PAD64_SEL_O_I_MSK 0xffffcfff
+#define PAD64_SEL_O_SFT 12
+#define PAD64_SEL_O_HI 13
+#define PAD64_SEL_O_SZ 2
+#define PAD64_SEL_OE_MSK 0x00100000
+#define PAD64_SEL_OE_I_MSK 0xffefffff
+#define PAD64_SEL_OE_SFT 20
+#define PAD64_SEL_OE_HI 20
+#define PAD64_SEL_OE_SZ 1
+#define GPIO_15_IP_ID_MSK 0x10000000
+#define GPIO_15_IP_ID_I_MSK 0xefffffff
+#define GPIO_15_IP_ID_SFT 28
+#define GPIO_15_IP_ID_HI 28
+#define GPIO_15_IP_ID_SZ 1
+#define PAD65_OE_MSK 0x00000001
+#define PAD65_OE_I_MSK 0xfffffffe
+#define PAD65_OE_SFT 0
+#define PAD65_OE_HI 0
+#define PAD65_OE_SZ 1
+#define PAD65_PE_MSK 0x00000002
+#define PAD65_PE_I_MSK 0xfffffffd
+#define PAD65_PE_SFT 1
+#define PAD65_PE_HI 1
+#define PAD65_PE_SZ 1
+#define PAD65_DS_MSK 0x00000004
+#define PAD65_DS_I_MSK 0xfffffffb
+#define PAD65_DS_SFT 2
+#define PAD65_DS_HI 2
+#define PAD65_DS_SZ 1
+#define PAD65_IE_MSK 0x00000008
+#define PAD65_IE_I_MSK 0xfffffff7
+#define PAD65_IE_SFT 3
+#define PAD65_IE_HI 3
+#define PAD65_IE_SZ 1
+#define PAD65_SEL_I_MSK 0x00000070
+#define PAD65_SEL_I_I_MSK 0xffffff8f
+#define PAD65_SEL_I_SFT 4
+#define PAD65_SEL_I_HI 6
+#define PAD65_SEL_I_SZ 3
+#define PAD65_OD_MSK 0x00000100
+#define PAD65_OD_I_MSK 0xfffffeff
+#define PAD65_OD_SFT 8
+#define PAD65_OD_HI 8
+#define PAD65_OD_SZ 1
+#define PAD65_SEL_O_MSK 0x00001000
+#define PAD65_SEL_O_I_MSK 0xffffefff
+#define PAD65_SEL_O_SFT 12
+#define PAD65_SEL_O_HI 12
+#define PAD65_SEL_O_SZ 1
+#define GPIO_TEST_7_IN_ID_MSK 0x10000000
+#define GPIO_TEST_7_IN_ID_I_MSK 0xefffffff
+#define GPIO_TEST_7_IN_ID_SFT 28
+#define GPIO_TEST_7_IN_ID_HI 28
+#define GPIO_TEST_7_IN_ID_SZ 1
+#define PAD66_OE_MSK 0x00000001
+#define PAD66_OE_I_MSK 0xfffffffe
+#define PAD66_OE_SFT 0
+#define PAD66_OE_HI 0
+#define PAD66_OE_SZ 1
+#define PAD66_PE_MSK 0x00000002
+#define PAD66_PE_I_MSK 0xfffffffd
+#define PAD66_PE_SFT 1
+#define PAD66_PE_HI 1
+#define PAD66_PE_SZ 1
+#define PAD66_DS_MSK 0x00000004
+#define PAD66_DS_I_MSK 0xfffffffb
+#define PAD66_DS_SFT 2
+#define PAD66_DS_HI 2
+#define PAD66_DS_SZ 1
+#define PAD66_IE_MSK 0x00000008
+#define PAD66_IE_I_MSK 0xfffffff7
+#define PAD66_IE_SFT 3
+#define PAD66_IE_HI 3
+#define PAD66_IE_SZ 1
+#define PAD66_SEL_I_MSK 0x00000030
+#define PAD66_SEL_I_I_MSK 0xffffffcf
+#define PAD66_SEL_I_SFT 4
+#define PAD66_SEL_I_HI 5
+#define PAD66_SEL_I_SZ 2
+#define PAD66_OD_MSK 0x00000100
+#define PAD66_OD_I_MSK 0xfffffeff
+#define PAD66_OD_SFT 8
+#define PAD66_OD_HI 8
+#define PAD66_OD_SZ 1
+#define PAD66_SEL_O_MSK 0x00003000
+#define PAD66_SEL_O_I_MSK 0xffffcfff
+#define PAD66_SEL_O_SFT 12
+#define PAD66_SEL_O_HI 13
+#define PAD66_SEL_O_SZ 2
+#define GPIO_17_QP_ID_MSK 0x10000000
+#define GPIO_17_QP_ID_I_MSK 0xefffffff
+#define GPIO_17_QP_ID_SFT 28
+#define GPIO_17_QP_ID_HI 28
+#define GPIO_17_QP_ID_SZ 1
+#define PAD68_OE_MSK 0x00000001
+#define PAD68_OE_I_MSK 0xfffffffe
+#define PAD68_OE_SFT 0
+#define PAD68_OE_HI 0
+#define PAD68_OE_SZ 1
+#define PAD68_PE_MSK 0x00000002
+#define PAD68_PE_I_MSK 0xfffffffd
+#define PAD68_PE_SFT 1
+#define PAD68_PE_HI 1
+#define PAD68_PE_SZ 1
+#define PAD68_DS_MSK 0x00000004
+#define PAD68_DS_I_MSK 0xfffffffb
+#define PAD68_DS_SFT 2
+#define PAD68_DS_HI 2
+#define PAD68_DS_SZ 1
+#define PAD68_IE_MSK 0x00000008
+#define PAD68_IE_I_MSK 0xfffffff7
+#define PAD68_IE_SFT 3
+#define PAD68_IE_HI 3
+#define PAD68_IE_SZ 1
+#define PAD68_OD_MSK 0x00000100
+#define PAD68_OD_I_MSK 0xfffffeff
+#define PAD68_OD_SFT 8
+#define PAD68_OD_HI 8
+#define PAD68_OD_SZ 1
+#define PAD68_SEL_O_MSK 0x00001000
+#define PAD68_SEL_O_I_MSK 0xffffefff
+#define PAD68_SEL_O_SFT 12
+#define PAD68_SEL_O_HI 12
+#define PAD68_SEL_O_SZ 1
+#define GPIO_19_ID_MSK 0x10000000
+#define GPIO_19_ID_I_MSK 0xefffffff
+#define GPIO_19_ID_SFT 28
+#define GPIO_19_ID_HI 28
+#define GPIO_19_ID_SZ 1
+#define PAD67_OE_MSK 0x00000001
+#define PAD67_OE_I_MSK 0xfffffffe
+#define PAD67_OE_SFT 0
+#define PAD67_OE_HI 0
+#define PAD67_OE_SZ 1
+#define PAD67_PE_MSK 0x00000002
+#define PAD67_PE_I_MSK 0xfffffffd
+#define PAD67_PE_SFT 1
+#define PAD67_PE_HI 1
+#define PAD67_PE_SZ 1
+#define PAD67_DS_MSK 0x00000004
+#define PAD67_DS_I_MSK 0xfffffffb
+#define PAD67_DS_SFT 2
+#define PAD67_DS_HI 2
+#define PAD67_DS_SZ 1
+#define PAD67_IE_MSK 0x00000008
+#define PAD67_IE_I_MSK 0xfffffff7
+#define PAD67_IE_SFT 3
+#define PAD67_IE_HI 3
+#define PAD67_IE_SZ 1
+#define PAD67_SEL_I_MSK 0x00000070
+#define PAD67_SEL_I_I_MSK 0xffffff8f
+#define PAD67_SEL_I_SFT 4
+#define PAD67_SEL_I_HI 6
+#define PAD67_SEL_I_SZ 3
+#define PAD67_OD_MSK 0x00000100
+#define PAD67_OD_I_MSK 0xfffffeff
+#define PAD67_OD_SFT 8
+#define PAD67_OD_HI 8
+#define PAD67_OD_SZ 1
+#define PAD67_SEL_O_MSK 0x00003000
+#define PAD67_SEL_O_I_MSK 0xffffcfff
+#define PAD67_SEL_O_SFT 12
+#define PAD67_SEL_O_HI 13
+#define PAD67_SEL_O_SZ 2
+#define GPIO_TEST_8_QN_ID_MSK 0x10000000
+#define GPIO_TEST_8_QN_ID_I_MSK 0xefffffff
+#define GPIO_TEST_8_QN_ID_SFT 28
+#define GPIO_TEST_8_QN_ID_HI 28
+#define GPIO_TEST_8_QN_ID_SZ 1
+#define PAD69_OE_MSK 0x00000001
+#define PAD69_OE_I_MSK 0xfffffffe
+#define PAD69_OE_SFT 0
+#define PAD69_OE_HI 0
+#define PAD69_OE_SZ 1
+#define PAD69_PE_MSK 0x00000002
+#define PAD69_PE_I_MSK 0xfffffffd
+#define PAD69_PE_SFT 1
+#define PAD69_PE_HI 1
+#define PAD69_PE_SZ 1
+#define PAD69_DS_MSK 0x00000004
+#define PAD69_DS_I_MSK 0xfffffffb
+#define PAD69_DS_SFT 2
+#define PAD69_DS_HI 2
+#define PAD69_DS_SZ 1
+#define PAD69_IE_MSK 0x00000008
+#define PAD69_IE_I_MSK 0xfffffff7
+#define PAD69_IE_SFT 3
+#define PAD69_IE_HI 3
+#define PAD69_IE_SZ 1
+#define PAD69_SEL_I_MSK 0x00000030
+#define PAD69_SEL_I_I_MSK 0xffffffcf
+#define PAD69_SEL_I_SFT 4
+#define PAD69_SEL_I_HI 5
+#define PAD69_SEL_I_SZ 2
+#define PAD69_OD_MSK 0x00000100
+#define PAD69_OD_I_MSK 0xfffffeff
+#define PAD69_OD_SFT 8
+#define PAD69_OD_HI 8
+#define PAD69_OD_SZ 1
+#define PAD69_SEL_O_MSK 0x00001000
+#define PAD69_SEL_O_I_MSK 0xffffefff
+#define PAD69_SEL_O_SFT 12
+#define PAD69_SEL_O_HI 12
+#define PAD69_SEL_O_SZ 1
+#define STRAP2_MSK 0x08000000
+#define STRAP2_I_MSK 0xf7ffffff
+#define STRAP2_SFT 27
+#define STRAP2_HI 27
+#define STRAP2_SZ 1
+#define GPIO_20_ID_MSK 0x10000000
+#define GPIO_20_ID_I_MSK 0xefffffff
+#define GPIO_20_ID_SFT 28
+#define GPIO_20_ID_HI 28
+#define GPIO_20_ID_SZ 1
+#define PAD70_OE_MSK 0x00000001
+#define PAD70_OE_I_MSK 0xfffffffe
+#define PAD70_OE_SFT 0
+#define PAD70_OE_HI 0
+#define PAD70_OE_SZ 1
+#define PAD70_PE_MSK 0x00000002
+#define PAD70_PE_I_MSK 0xfffffffd
+#define PAD70_PE_SFT 1
+#define PAD70_PE_HI 1
+#define PAD70_PE_SZ 1
+#define PAD70_DS_MSK 0x00000004
+#define PAD70_DS_I_MSK 0xfffffffb
+#define PAD70_DS_SFT 2
+#define PAD70_DS_HI 2
+#define PAD70_DS_SZ 1
+#define PAD70_IE_MSK 0x00000008
+#define PAD70_IE_I_MSK 0xfffffff7
+#define PAD70_IE_SFT 3
+#define PAD70_IE_HI 3
+#define PAD70_IE_SZ 1
+#define PAD70_SEL_I_MSK 0x00000030
+#define PAD70_SEL_I_I_MSK 0xffffffcf
+#define PAD70_SEL_I_SFT 4
+#define PAD70_SEL_I_HI 5
+#define PAD70_SEL_I_SZ 2
+#define PAD70_OD_MSK 0x00000100
+#define PAD70_OD_I_MSK 0xfffffeff
+#define PAD70_OD_SFT 8
+#define PAD70_OD_HI 8
+#define PAD70_OD_SZ 1
+#define PAD70_SEL_O_MSK 0x00007000
+#define PAD70_SEL_O_I_MSK 0xffff8fff
+#define PAD70_SEL_O_SFT 12
+#define PAD70_SEL_O_HI 14
+#define PAD70_SEL_O_SZ 3
+#define GPIO_21_ID_MSK 0x10000000
+#define GPIO_21_ID_I_MSK 0xefffffff
+#define GPIO_21_ID_SFT 28
+#define GPIO_21_ID_HI 28
+#define GPIO_21_ID_SZ 1
+#define PAD231_OE_MSK 0x00000001
+#define PAD231_OE_I_MSK 0xfffffffe
+#define PAD231_OE_SFT 0
+#define PAD231_OE_HI 0
+#define PAD231_OE_SZ 1
+#define PAD231_PE_MSK 0x00000002
+#define PAD231_PE_I_MSK 0xfffffffd
+#define PAD231_PE_SFT 1
+#define PAD231_PE_HI 1
+#define PAD231_PE_SZ 1
+#define PAD231_DS_MSK 0x00000004
+#define PAD231_DS_I_MSK 0xfffffffb
+#define PAD231_DS_SFT 2
+#define PAD231_DS_HI 2
+#define PAD231_DS_SZ 1
+#define PAD231_IE_MSK 0x00000008
+#define PAD231_IE_I_MSK 0xfffffff7
+#define PAD231_IE_SFT 3
+#define PAD231_IE_HI 3
+#define PAD231_IE_SZ 1
+#define PAD231_OD_MSK 0x00000100
+#define PAD231_OD_I_MSK 0xfffffeff
+#define PAD231_OD_SFT 8
+#define PAD231_OD_HI 8
+#define PAD231_OD_SZ 1
+#define PIN_40_OR_56_ID_MSK 0x10000000
+#define PIN_40_OR_56_ID_I_MSK 0xefffffff
+#define PIN_40_OR_56_ID_SFT 28
+#define PIN_40_OR_56_ID_HI 28
+#define PIN_40_OR_56_ID_SZ 1
+#define MP_PHY2RX_DATA__0_SEL_MSK 0x00000001
+#define MP_PHY2RX_DATA__0_SEL_I_MSK 0xfffffffe
+#define MP_PHY2RX_DATA__0_SEL_SFT 0
+#define MP_PHY2RX_DATA__0_SEL_HI 0
+#define MP_PHY2RX_DATA__0_SEL_SZ 1
+#define MP_PHY2RX_DATA__1_SEL_MSK 0x00000002
+#define MP_PHY2RX_DATA__1_SEL_I_MSK 0xfffffffd
+#define MP_PHY2RX_DATA__1_SEL_SFT 1
+#define MP_PHY2RX_DATA__1_SEL_HI 1
+#define MP_PHY2RX_DATA__1_SEL_SZ 1
+#define MP_TX_FF_RPTR__1_SEL_MSK 0x00000004
+#define MP_TX_FF_RPTR__1_SEL_I_MSK 0xfffffffb
+#define MP_TX_FF_RPTR__1_SEL_SFT 2
+#define MP_TX_FF_RPTR__1_SEL_HI 2
+#define MP_TX_FF_RPTR__1_SEL_SZ 1
+#define MP_RX_FF_WPTR__2_SEL_MSK 0x00000008
+#define MP_RX_FF_WPTR__2_SEL_I_MSK 0xfffffff7
+#define MP_RX_FF_WPTR__2_SEL_SFT 3
+#define MP_RX_FF_WPTR__2_SEL_HI 3
+#define MP_RX_FF_WPTR__2_SEL_SZ 1
+#define MP_RX_FF_WPTR__1_SEL_MSK 0x00000010
+#define MP_RX_FF_WPTR__1_SEL_I_MSK 0xffffffef
+#define MP_RX_FF_WPTR__1_SEL_SFT 4
+#define MP_RX_FF_WPTR__1_SEL_HI 4
+#define MP_RX_FF_WPTR__1_SEL_SZ 1
+#define MP_RX_FF_WPTR__0_SEL_MSK 0x00000020
+#define MP_RX_FF_WPTR__0_SEL_I_MSK 0xffffffdf
+#define MP_RX_FF_WPTR__0_SEL_SFT 5
+#define MP_RX_FF_WPTR__0_SEL_HI 5
+#define MP_RX_FF_WPTR__0_SEL_SZ 1
+#define MP_PHY2RX_DATA__2_SEL_MSK 0x00000040
+#define MP_PHY2RX_DATA__2_SEL_I_MSK 0xffffffbf
+#define MP_PHY2RX_DATA__2_SEL_SFT 6
+#define MP_PHY2RX_DATA__2_SEL_HI 6
+#define MP_PHY2RX_DATA__2_SEL_SZ 1
+#define MP_PHY2RX_DATA__4_SEL_MSK 0x00000080
+#define MP_PHY2RX_DATA__4_SEL_I_MSK 0xffffff7f
+#define MP_PHY2RX_DATA__4_SEL_SFT 7
+#define MP_PHY2RX_DATA__4_SEL_HI 7
+#define MP_PHY2RX_DATA__4_SEL_SZ 1
+#define I2CM_SDA_ID_SEL_MSK 0x00000300
+#define I2CM_SDA_ID_SEL_I_MSK 0xfffffcff
+#define I2CM_SDA_ID_SEL_SFT 8
+#define I2CM_SDA_ID_SEL_HI 9
+#define I2CM_SDA_ID_SEL_SZ 2
+#define CRYSTAL_OUT_REQ_SEL_MSK 0x00000400
+#define CRYSTAL_OUT_REQ_SEL_I_MSK 0xfffffbff
+#define CRYSTAL_OUT_REQ_SEL_SFT 10
+#define CRYSTAL_OUT_REQ_SEL_HI 10
+#define CRYSTAL_OUT_REQ_SEL_SZ 1
+#define MP_PHY2RX_DATA__5_SEL_MSK 0x00000800
+#define MP_PHY2RX_DATA__5_SEL_I_MSK 0xfffff7ff
+#define MP_PHY2RX_DATA__5_SEL_SFT 11
+#define MP_PHY2RX_DATA__5_SEL_HI 11
+#define MP_PHY2RX_DATA__5_SEL_SZ 1
+#define MP_PHY2RX_DATA__3_SEL_MSK 0x00001000
+#define MP_PHY2RX_DATA__3_SEL_I_MSK 0xffffefff
+#define MP_PHY2RX_DATA__3_SEL_SFT 12
+#define MP_PHY2RX_DATA__3_SEL_HI 12
+#define MP_PHY2RX_DATA__3_SEL_SZ 1
+#define UART_RXD_SEL_MSK 0x00006000
+#define UART_RXD_SEL_I_MSK 0xffff9fff
+#define UART_RXD_SEL_SFT 13
+#define UART_RXD_SEL_HI 14
+#define UART_RXD_SEL_SZ 2
+#define MP_PHY2RX_DATA__6_SEL_MSK 0x00008000
+#define MP_PHY2RX_DATA__6_SEL_I_MSK 0xffff7fff
+#define MP_PHY2RX_DATA__6_SEL_SFT 15
+#define MP_PHY2RX_DATA__6_SEL_HI 15
+#define MP_PHY2RX_DATA__6_SEL_SZ 1
+#define DAT_UART_NCTS_SEL_MSK 0x00010000
+#define DAT_UART_NCTS_SEL_I_MSK 0xfffeffff
+#define DAT_UART_NCTS_SEL_SFT 16
+#define DAT_UART_NCTS_SEL_HI 16
+#define DAT_UART_NCTS_SEL_SZ 1
+#define GPIO_LOG_STOP_SEL_MSK 0x000e0000
+#define GPIO_LOG_STOP_SEL_I_MSK 0xfff1ffff
+#define GPIO_LOG_STOP_SEL_SFT 17
+#define GPIO_LOG_STOP_SEL_HI 19
+#define GPIO_LOG_STOP_SEL_SZ 3
+#define MP_TX_FF_RPTR__0_SEL_MSK 0x00100000
+#define MP_TX_FF_RPTR__0_SEL_I_MSK 0xffefffff
+#define MP_TX_FF_RPTR__0_SEL_SFT 20
+#define MP_TX_FF_RPTR__0_SEL_HI 20
+#define MP_TX_FF_RPTR__0_SEL_SZ 1
+#define MP_PHY_RX_WRST_N_SEL_MSK 0x00200000
+#define MP_PHY_RX_WRST_N_SEL_I_MSK 0xffdfffff
+#define MP_PHY_RX_WRST_N_SEL_SFT 21
+#define MP_PHY_RX_WRST_N_SEL_HI 21
+#define MP_PHY_RX_WRST_N_SEL_SZ 1
+#define EXT_32K_SEL_MSK 0x00c00000
+#define EXT_32K_SEL_I_MSK 0xff3fffff
+#define EXT_32K_SEL_SFT 22
+#define EXT_32K_SEL_HI 23
+#define EXT_32K_SEL_SZ 2
+#define MP_PHY2RX_DATA__7_SEL_MSK 0x01000000
+#define MP_PHY2RX_DATA__7_SEL_I_MSK 0xfeffffff
+#define MP_PHY2RX_DATA__7_SEL_SFT 24
+#define MP_PHY2RX_DATA__7_SEL_HI 24
+#define MP_PHY2RX_DATA__7_SEL_SZ 1
+#define MP_TX_FF_RPTR__2_SEL_MSK 0x02000000
+#define MP_TX_FF_RPTR__2_SEL_I_MSK 0xfdffffff
+#define MP_TX_FF_RPTR__2_SEL_SFT 25
+#define MP_TX_FF_RPTR__2_SEL_HI 25
+#define MP_TX_FF_RPTR__2_SEL_SZ 1
+#define PMUINT_WAKE_SEL_MSK 0x1c000000
+#define PMUINT_WAKE_SEL_I_MSK 0xe3ffffff
+#define PMUINT_WAKE_SEL_SFT 26
+#define PMUINT_WAKE_SEL_HI 28
+#define PMUINT_WAKE_SEL_SZ 3
+#define I2CM_SCL_ID_SEL_MSK 0x20000000
+#define I2CM_SCL_ID_SEL_I_MSK 0xdfffffff
+#define I2CM_SCL_ID_SEL_SFT 29
+#define I2CM_SCL_ID_SEL_HI 29
+#define I2CM_SCL_ID_SEL_SZ 1
+#define MP_MRX_RX_EN_SEL_MSK 0x40000000
+#define MP_MRX_RX_EN_SEL_I_MSK 0xbfffffff
+#define MP_MRX_RX_EN_SEL_SFT 30
+#define MP_MRX_RX_EN_SEL_HI 30
+#define MP_MRX_RX_EN_SEL_SZ 1
+#define DAT_UART_RXD_SEL_0_MSK 0x80000000
+#define DAT_UART_RXD_SEL_0_I_MSK 0x7fffffff
+#define DAT_UART_RXD_SEL_0_SFT 31
+#define DAT_UART_RXD_SEL_0_HI 31
+#define DAT_UART_RXD_SEL_0_SZ 1
+#define DAT_UART_RXD_SEL_1_MSK 0x00000001
+#define DAT_UART_RXD_SEL_1_I_MSK 0xfffffffe
+#define DAT_UART_RXD_SEL_1_SFT 0
+#define DAT_UART_RXD_SEL_1_HI 0
+#define DAT_UART_RXD_SEL_1_SZ 1
+#define SPI_DI_SEL_MSK 0x00000002
+#define SPI_DI_SEL_I_MSK 0xfffffffd
+#define SPI_DI_SEL_SFT 1
+#define SPI_DI_SEL_HI 1
+#define SPI_DI_SEL_SZ 1
+#define IO_PORT_REG_MSK 0x0001ffff
+#define IO_PORT_REG_I_MSK 0xfffe0000
+#define IO_PORT_REG_SFT 0
+#define IO_PORT_REG_HI 16
+#define IO_PORT_REG_SZ 17
+#define MASK_RX_INT_MSK 0x00000001
+#define MASK_RX_INT_I_MSK 0xfffffffe
+#define MASK_RX_INT_SFT 0
+#define MASK_RX_INT_HI 0
+#define MASK_RX_INT_SZ 1
+#define MASK_TX_INT_MSK 0x00000002
+#define MASK_TX_INT_I_MSK 0xfffffffd
+#define MASK_TX_INT_SFT 1
+#define MASK_TX_INT_HI 1
+#define MASK_TX_INT_SZ 1
+#define MASK_SOC_SYSTEM_INT_MSK 0x00000004
+#define MASK_SOC_SYSTEM_INT_I_MSK 0xfffffffb
+#define MASK_SOC_SYSTEM_INT_SFT 2
+#define MASK_SOC_SYSTEM_INT_HI 2
+#define MASK_SOC_SYSTEM_INT_SZ 1
+#define EDCA0_LOW_THR_INT_MASK_MSK 0x00000008
+#define EDCA0_LOW_THR_INT_MASK_I_MSK 0xfffffff7
+#define EDCA0_LOW_THR_INT_MASK_SFT 3
+#define EDCA0_LOW_THR_INT_MASK_HI 3
+#define EDCA0_LOW_THR_INT_MASK_SZ 1
+#define EDCA1_LOW_THR_INT_MASK_MSK 0x00000010
+#define EDCA1_LOW_THR_INT_MASK_I_MSK 0xffffffef
+#define EDCA1_LOW_THR_INT_MASK_SFT 4
+#define EDCA1_LOW_THR_INT_MASK_HI 4
+#define EDCA1_LOW_THR_INT_MASK_SZ 1
+#define EDCA2_LOW_THR_INT_MASK_MSK 0x00000020
+#define EDCA2_LOW_THR_INT_MASK_I_MSK 0xffffffdf
+#define EDCA2_LOW_THR_INT_MASK_SFT 5
+#define EDCA2_LOW_THR_INT_MASK_HI 5
+#define EDCA2_LOW_THR_INT_MASK_SZ 1
+#define EDCA3_LOW_THR_INT_MASK_MSK 0x00000040
+#define EDCA3_LOW_THR_INT_MASK_I_MSK 0xffffffbf
+#define EDCA3_LOW_THR_INT_MASK_SFT 6
+#define EDCA3_LOW_THR_INT_MASK_HI 6
+#define EDCA3_LOW_THR_INT_MASK_SZ 1
+#define TX_LIMIT_INT_MASK_MSK 0x00000080
+#define TX_LIMIT_INT_MASK_I_MSK 0xffffff7f
+#define TX_LIMIT_INT_MASK_SFT 7
+#define TX_LIMIT_INT_MASK_HI 7
+#define TX_LIMIT_INT_MASK_SZ 1
+#define RX_INT_MSK 0x00000001
+#define RX_INT_I_MSK 0xfffffffe
+#define RX_INT_SFT 0
+#define RX_INT_HI 0
+#define RX_INT_SZ 1
+#define TX_COMPLETE_INT_MSK 0x00000002
+#define TX_COMPLETE_INT_I_MSK 0xfffffffd
+#define TX_COMPLETE_INT_SFT 1
+#define TX_COMPLETE_INT_HI 1
+#define TX_COMPLETE_INT_SZ 1
+#define SOC_SYSTEM_INT_STATUS_MSK 0x00000004
+#define SOC_SYSTEM_INT_STATUS_I_MSK 0xfffffffb
+#define SOC_SYSTEM_INT_STATUS_SFT 2
+#define SOC_SYSTEM_INT_STATUS_HI 2
+#define SOC_SYSTEM_INT_STATUS_SZ 1
+#define EDCA0_LOW_THR_INT_STS_MSK 0x00000008
+#define EDCA0_LOW_THR_INT_STS_I_MSK 0xfffffff7
+#define EDCA0_LOW_THR_INT_STS_SFT 3
+#define EDCA0_LOW_THR_INT_STS_HI 3
+#define EDCA0_LOW_THR_INT_STS_SZ 1
+#define EDCA1_LOW_THR_INT_STS_MSK 0x00000010
+#define EDCA1_LOW_THR_INT_STS_I_MSK 0xffffffef
+#define EDCA1_LOW_THR_INT_STS_SFT 4
+#define EDCA1_LOW_THR_INT_STS_HI 4
+#define EDCA1_LOW_THR_INT_STS_SZ 1
+#define EDCA2_LOW_THR_INT_STS_MSK 0x00000020
+#define EDCA2_LOW_THR_INT_STS_I_MSK 0xffffffdf
+#define EDCA2_LOW_THR_INT_STS_SFT 5
+#define EDCA2_LOW_THR_INT_STS_HI 5
+#define EDCA2_LOW_THR_INT_STS_SZ 1
+#define EDCA3_LOW_THR_INT_STS_MSK 0x00000040
+#define EDCA3_LOW_THR_INT_STS_I_MSK 0xffffffbf
+#define EDCA3_LOW_THR_INT_STS_SFT 6
+#define EDCA3_LOW_THR_INT_STS_HI 6
+#define EDCA3_LOW_THR_INT_STS_SZ 1
+#define TX_LIMIT_INT_STS_MSK 0x00000080
+#define TX_LIMIT_INT_STS_I_MSK 0xffffff7f
+#define TX_LIMIT_INT_STS_SFT 7
+#define TX_LIMIT_INT_STS_HI 7
+#define TX_LIMIT_INT_STS_SZ 1
+#define HOST_TRIGGERED_RX_INT_MSK 0x00000100
+#define HOST_TRIGGERED_RX_INT_I_MSK 0xfffffeff
+#define HOST_TRIGGERED_RX_INT_SFT 8
+#define HOST_TRIGGERED_RX_INT_HI 8
+#define HOST_TRIGGERED_RX_INT_SZ 1
+#define HOST_TRIGGERED_TX_INT_MSK 0x00000200
+#define HOST_TRIGGERED_TX_INT_I_MSK 0xfffffdff
+#define HOST_TRIGGERED_TX_INT_SFT 9
+#define HOST_TRIGGERED_TX_INT_HI 9
+#define HOST_TRIGGERED_TX_INT_SZ 1
+#define SOC_TRIGGER_RX_INT_MSK 0x00000400
+#define SOC_TRIGGER_RX_INT_I_MSK 0xfffffbff
+#define SOC_TRIGGER_RX_INT_SFT 10
+#define SOC_TRIGGER_RX_INT_HI 10
+#define SOC_TRIGGER_RX_INT_SZ 1
+#define SOC_TRIGGER_TX_INT_MSK 0x00000800
+#define SOC_TRIGGER_TX_INT_I_MSK 0xfffff7ff
+#define SOC_TRIGGER_TX_INT_SFT 11
+#define SOC_TRIGGER_TX_INT_HI 11
+#define SOC_TRIGGER_TX_INT_SZ 1
+#define RDY_FOR_TX_RX_MSK 0x00000001
+#define RDY_FOR_TX_RX_I_MSK 0xfffffffe
+#define RDY_FOR_TX_RX_SFT 0
+#define RDY_FOR_TX_RX_HI 0
+#define RDY_FOR_TX_RX_SZ 1
+#define RDY_FOR_FW_DOWNLOAD_MSK 0x00000002
+#define RDY_FOR_FW_DOWNLOAD_I_MSK 0xfffffffd
+#define RDY_FOR_FW_DOWNLOAD_SFT 1
+#define RDY_FOR_FW_DOWNLOAD_HI 1
+#define RDY_FOR_FW_DOWNLOAD_SZ 1
+#define ILLEGAL_CMD_RESP_OPTION_MSK 0x00000004
+#define ILLEGAL_CMD_RESP_OPTION_I_MSK 0xfffffffb
+#define ILLEGAL_CMD_RESP_OPTION_SFT 2
+#define ILLEGAL_CMD_RESP_OPTION_HI 2
+#define ILLEGAL_CMD_RESP_OPTION_SZ 1
+#define SDIO_TRX_DATA_SEQUENCE_MSK 0x00000008
+#define SDIO_TRX_DATA_SEQUENCE_I_MSK 0xfffffff7
+#define SDIO_TRX_DATA_SEQUENCE_SFT 3
+#define SDIO_TRX_DATA_SEQUENCE_HI 3
+#define SDIO_TRX_DATA_SEQUENCE_SZ 1
+#define GPIO_INT_TRIGGER_OPTION_MSK 0x00000010
+#define GPIO_INT_TRIGGER_OPTION_I_MSK 0xffffffef
+#define GPIO_INT_TRIGGER_OPTION_SFT 4
+#define GPIO_INT_TRIGGER_OPTION_HI 4
+#define GPIO_INT_TRIGGER_OPTION_SZ 1
+#define TRIGGER_FUNCTION_SETTING_MSK 0x00000060
+#define TRIGGER_FUNCTION_SETTING_I_MSK 0xffffff9f
+#define TRIGGER_FUNCTION_SETTING_SFT 5
+#define TRIGGER_FUNCTION_SETTING_HI 6
+#define TRIGGER_FUNCTION_SETTING_SZ 2
+#define CMD52_ABORT_RESPONSE_MSK 0x00000080
+#define CMD52_ABORT_RESPONSE_I_MSK 0xffffff7f
+#define CMD52_ABORT_RESPONSE_SFT 7
+#define CMD52_ABORT_RESPONSE_HI 7
+#define CMD52_ABORT_RESPONSE_SZ 1
+#define RX_PACKET_LENGTH_MSK 0x0000ffff
+#define RX_PACKET_LENGTH_I_MSK 0xffff0000
+#define RX_PACKET_LENGTH_SFT 0
+#define RX_PACKET_LENGTH_HI 15
+#define RX_PACKET_LENGTH_SZ 16
+#define CARD_FW_DL_STATUS_MSK 0x00ff0000
+#define CARD_FW_DL_STATUS_I_MSK 0xff00ffff
+#define CARD_FW_DL_STATUS_SFT 16
+#define CARD_FW_DL_STATUS_HI 23
+#define CARD_FW_DL_STATUS_SZ 8
+#define TX_RX_LOOP_BACK_TEST_MSK 0x01000000
+#define TX_RX_LOOP_BACK_TEST_I_MSK 0xfeffffff
+#define TX_RX_LOOP_BACK_TEST_SFT 24
+#define TX_RX_LOOP_BACK_TEST_HI 24
+#define TX_RX_LOOP_BACK_TEST_SZ 1
+#define SDIO_LOOP_BACK_TEST_MSK 0x02000000
+#define SDIO_LOOP_BACK_TEST_I_MSK 0xfdffffff
+#define SDIO_LOOP_BACK_TEST_SFT 25
+#define SDIO_LOOP_BACK_TEST_HI 25
+#define SDIO_LOOP_BACK_TEST_SZ 1
+#define CMD52_ABORT_ACTIVE_MSK 0x10000000
+#define CMD52_ABORT_ACTIVE_I_MSK 0xefffffff
+#define CMD52_ABORT_ACTIVE_SFT 28
+#define CMD52_ABORT_ACTIVE_HI 28
+#define CMD52_ABORT_ACTIVE_SZ 1
+#define CMD52_RESET_ACTIVE_MSK 0x20000000
+#define CMD52_RESET_ACTIVE_I_MSK 0xdfffffff
+#define CMD52_RESET_ACTIVE_SFT 29
+#define CMD52_RESET_ACTIVE_HI 29
+#define CMD52_RESET_ACTIVE_SZ 1
+#define SDIO_PARTIAL_RESET_ACTIVE_MSK 0x40000000
+#define SDIO_PARTIAL_RESET_ACTIVE_I_MSK 0xbfffffff
+#define SDIO_PARTIAL_RESET_ACTIVE_SFT 30
+#define SDIO_PARTIAL_RESET_ACTIVE_HI 30
+#define SDIO_PARTIAL_RESET_ACTIVE_SZ 1
+#define SDIO_ALL_RESE_ACTIVE_MSK 0x80000000
+#define SDIO_ALL_RESE_ACTIVE_I_MSK 0x7fffffff
+#define SDIO_ALL_RESE_ACTIVE_SFT 31
+#define SDIO_ALL_RESE_ACTIVE_HI 31
+#define SDIO_ALL_RESE_ACTIVE_SZ 1
+#define RX_PACKET_LENGTH2_MSK 0x0000ffff
+#define RX_PACKET_LENGTH2_I_MSK 0xffff0000
+#define RX_PACKET_LENGTH2_SFT 0
+#define RX_PACKET_LENGTH2_HI 15
+#define RX_PACKET_LENGTH2_SZ 16
+#define RX_INT1_MSK 0x00010000
+#define RX_INT1_I_MSK 0xfffeffff
+#define RX_INT1_SFT 16
+#define RX_INT1_HI 16
+#define RX_INT1_SZ 1
+#define TX_DONE_MSK 0x00020000
+#define TX_DONE_I_MSK 0xfffdffff
+#define TX_DONE_SFT 17
+#define TX_DONE_HI 17
+#define TX_DONE_SZ 1
+#define HCI_TRX_FINISH_MSK 0x00040000
+#define HCI_TRX_FINISH_I_MSK 0xfffbffff
+#define HCI_TRX_FINISH_SFT 18
+#define HCI_TRX_FINISH_HI 18
+#define HCI_TRX_FINISH_SZ 1
+#define ALLOCATE_STATUS_MSK 0x00080000
+#define ALLOCATE_STATUS_I_MSK 0xfff7ffff
+#define ALLOCATE_STATUS_SFT 19
+#define ALLOCATE_STATUS_HI 19
+#define ALLOCATE_STATUS_SZ 1
+#define HCI_INPUT_FF_CNT_MSK 0x00f00000
+#define HCI_INPUT_FF_CNT_I_MSK 0xff0fffff
+#define HCI_INPUT_FF_CNT_SFT 20
+#define HCI_INPUT_FF_CNT_HI 23
+#define HCI_INPUT_FF_CNT_SZ 4
+#define HCI_OUTPUT_FF_CNT_MSK 0x1f000000
+#define HCI_OUTPUT_FF_CNT_I_MSK 0xe0ffffff
+#define HCI_OUTPUT_FF_CNT_SFT 24
+#define HCI_OUTPUT_FF_CNT_HI 28
+#define HCI_OUTPUT_FF_CNT_SZ 5
+#define AHB_HANG4_MSK 0x20000000
+#define AHB_HANG4_I_MSK 0xdfffffff
+#define AHB_HANG4_SFT 29
+#define AHB_HANG4_HI 29
+#define AHB_HANG4_SZ 1
+#define HCI_IN_QUE_EMPTY_MSK 0x40000000
+#define HCI_IN_QUE_EMPTY_I_MSK 0xbfffffff
+#define HCI_IN_QUE_EMPTY_SFT 30
+#define HCI_IN_QUE_EMPTY_HI 30
+#define HCI_IN_QUE_EMPTY_SZ 1
+#define SYSTEM_INT_MSK 0x80000000
+#define SYSTEM_INT_I_MSK 0x7fffffff
+#define SYSTEM_INT_SFT 31
+#define SYSTEM_INT_HI 31
+#define SYSTEM_INT_SZ 1
+#define CARD_RCA_REG_MSK 0x0000ffff
+#define CARD_RCA_REG_I_MSK 0xffff0000
+#define CARD_RCA_REG_SFT 0
+#define CARD_RCA_REG_HI 15
+#define CARD_RCA_REG_SZ 16
+#define SDIO_FIFO_WR_THLD_REG_MSK 0x000001ff
+#define SDIO_FIFO_WR_THLD_REG_I_MSK 0xfffffe00
+#define SDIO_FIFO_WR_THLD_REG_SFT 0
+#define SDIO_FIFO_WR_THLD_REG_HI 8
+#define SDIO_FIFO_WR_THLD_REG_SZ 9
+#define SDIO_FIFO_WR_LIMIT_REG_MSK 0x000001ff
+#define SDIO_FIFO_WR_LIMIT_REG_I_MSK 0xfffffe00
+#define SDIO_FIFO_WR_LIMIT_REG_SFT 0
+#define SDIO_FIFO_WR_LIMIT_REG_HI 8
+#define SDIO_FIFO_WR_LIMIT_REG_SZ 9
+#define SDIO_TX_DATA_BATCH_SIZE_REG_MSK 0x000001ff
+#define SDIO_TX_DATA_BATCH_SIZE_REG_I_MSK 0xfffffe00
+#define SDIO_TX_DATA_BATCH_SIZE_REG_SFT 0
+#define SDIO_TX_DATA_BATCH_SIZE_REG_HI 8
+#define SDIO_TX_DATA_BATCH_SIZE_REG_SZ 9
+#define SDIO_THLD_FOR_CMD53RD_REG_MSK 0x000001ff
+#define SDIO_THLD_FOR_CMD53RD_REG_I_MSK 0xfffffe00
+#define SDIO_THLD_FOR_CMD53RD_REG_SFT 0
+#define SDIO_THLD_FOR_CMD53RD_REG_HI 8
+#define SDIO_THLD_FOR_CMD53RD_REG_SZ 9
+#define SDIO_RX_DATA_BATCH_SIZE_REG_MSK 0x000001ff
+#define SDIO_RX_DATA_BATCH_SIZE_REG_I_MSK 0xfffffe00
+#define SDIO_RX_DATA_BATCH_SIZE_REG_SFT 0
+#define SDIO_RX_DATA_BATCH_SIZE_REG_HI 8
+#define SDIO_RX_DATA_BATCH_SIZE_REG_SZ 9
+#define START_BYTE_VALUE_MSK 0x000000ff
+#define START_BYTE_VALUE_I_MSK 0xffffff00
+#define START_BYTE_VALUE_SFT 0
+#define START_BYTE_VALUE_HI 7
+#define START_BYTE_VALUE_SZ 8
+#define END_BYTE_VALUE_MSK 0x0000ff00
+#define END_BYTE_VALUE_I_MSK 0xffff00ff
+#define END_BYTE_VALUE_SFT 8
+#define END_BYTE_VALUE_HI 15
+#define END_BYTE_VALUE_SZ 8
+#define SDIO_BYTE_MODE_BATCH_SIZE_REG_MSK 0x000000ff
+#define SDIO_BYTE_MODE_BATCH_SIZE_REG_I_MSK 0xffffff00
+#define SDIO_BYTE_MODE_BATCH_SIZE_REG_SFT 0
+#define SDIO_BYTE_MODE_BATCH_SIZE_REG_HI 7
+#define SDIO_BYTE_MODE_BATCH_SIZE_REG_SZ 8
+#define SDIO_LAST_CMD_INDEX_REG_MSK 0x0000003f
+#define SDIO_LAST_CMD_INDEX_REG_I_MSK 0xffffffc0
+#define SDIO_LAST_CMD_INDEX_REG_SFT 0
+#define SDIO_LAST_CMD_INDEX_REG_HI 5
+#define SDIO_LAST_CMD_INDEX_REG_SZ 6
+#define SDIO_LAST_CMD_CRC_REG_MSK 0x00007f00
+#define SDIO_LAST_CMD_CRC_REG_I_MSK 0xffff80ff
+#define SDIO_LAST_CMD_CRC_REG_SFT 8
+#define SDIO_LAST_CMD_CRC_REG_HI 14
+#define SDIO_LAST_CMD_CRC_REG_SZ 7
+#define SDIO_LAST_CMD_ARG_REG_MSK 0xffffffff
+#define SDIO_LAST_CMD_ARG_REG_I_MSK 0x00000000
+#define SDIO_LAST_CMD_ARG_REG_SFT 0
+#define SDIO_LAST_CMD_ARG_REG_HI 31
+#define SDIO_LAST_CMD_ARG_REG_SZ 32
+#define SDIO_BUS_STATE_REG_MSK 0x0000001f
+#define SDIO_BUS_STATE_REG_I_MSK 0xffffffe0
+#define SDIO_BUS_STATE_REG_SFT 0
+#define SDIO_BUS_STATE_REG_HI 4
+#define SDIO_BUS_STATE_REG_SZ 5
+#define SDIO_BUSY_LONG_CNT_MSK 0xffff0000
+#define SDIO_BUSY_LONG_CNT_I_MSK 0x0000ffff
+#define SDIO_BUSY_LONG_CNT_SFT 16
+#define SDIO_BUSY_LONG_CNT_HI 31
+#define SDIO_BUSY_LONG_CNT_SZ 16
+#define SDIO_CARD_STATUS_REG_MSK 0xffffffff
+#define SDIO_CARD_STATUS_REG_I_MSK 0x00000000
+#define SDIO_CARD_STATUS_REG_SFT 0
+#define SDIO_CARD_STATUS_REG_HI 31
+#define SDIO_CARD_STATUS_REG_SZ 32
+#define R5_RESPONSE_FLAG_MSK 0x000000ff
+#define R5_RESPONSE_FLAG_I_MSK 0xffffff00
+#define R5_RESPONSE_FLAG_SFT 0
+#define R5_RESPONSE_FLAG_HI 7
+#define R5_RESPONSE_FLAG_SZ 8
+#define RESP_OUT_EDGE_MSK 0x00000100
+#define RESP_OUT_EDGE_I_MSK 0xfffffeff
+#define RESP_OUT_EDGE_SFT 8
+#define RESP_OUT_EDGE_HI 8
+#define RESP_OUT_EDGE_SZ 1
+#define DAT_OUT_EDGE_MSK 0x00000200
+#define DAT_OUT_EDGE_I_MSK 0xfffffdff
+#define DAT_OUT_EDGE_SFT 9
+#define DAT_OUT_EDGE_HI 9
+#define DAT_OUT_EDGE_SZ 1
+#define MCU_TO_SDIO_INFO_MASK_MSK 0x00010000
+#define MCU_TO_SDIO_INFO_MASK_I_MSK 0xfffeffff
+#define MCU_TO_SDIO_INFO_MASK_SFT 16
+#define MCU_TO_SDIO_INFO_MASK_HI 16
+#define MCU_TO_SDIO_INFO_MASK_SZ 1
+#define INT_THROUGH_PIN_MSK 0x00020000
+#define INT_THROUGH_PIN_I_MSK 0xfffdffff
+#define INT_THROUGH_PIN_SFT 17
+#define INT_THROUGH_PIN_HI 17
+#define INT_THROUGH_PIN_SZ 1
+#define WRITE_DATA_MSK 0x000000ff
+#define WRITE_DATA_I_MSK 0xffffff00
+#define WRITE_DATA_SFT 0
+#define WRITE_DATA_HI 7
+#define WRITE_DATA_SZ 8
+#define WRITE_ADDRESS_MSK 0x0000ff00
+#define WRITE_ADDRESS_I_MSK 0xffff00ff
+#define WRITE_ADDRESS_SFT 8
+#define WRITE_ADDRESS_HI 15
+#define WRITE_ADDRESS_SZ 8
+#define READ_DATA_MSK 0x00ff0000
+#define READ_DATA_I_MSK 0xff00ffff
+#define READ_DATA_SFT 16
+#define READ_DATA_HI 23
+#define READ_DATA_SZ 8
+#define READ_ADDRESS_MSK 0xff000000
+#define READ_ADDRESS_I_MSK 0x00ffffff
+#define READ_ADDRESS_SFT 24
+#define READ_ADDRESS_HI 31
+#define READ_ADDRESS_SZ 8
+#define FN1_DMA_START_ADDR_REG_MSK 0xffffffff
+#define FN1_DMA_START_ADDR_REG_I_MSK 0x00000000
+#define FN1_DMA_START_ADDR_REG_SFT 0
+#define FN1_DMA_START_ADDR_REG_HI 31
+#define FN1_DMA_START_ADDR_REG_SZ 32
+#define SDIO_TO_MCU_INFO_MSK 0x000000ff
+#define SDIO_TO_MCU_INFO_I_MSK 0xffffff00
+#define SDIO_TO_MCU_INFO_SFT 0
+#define SDIO_TO_MCU_INFO_HI 7
+#define SDIO_TO_MCU_INFO_SZ 8
+#define SDIO_PARTIAL_RESET_MSK 0x00000100
+#define SDIO_PARTIAL_RESET_I_MSK 0xfffffeff
+#define SDIO_PARTIAL_RESET_SFT 8
+#define SDIO_PARTIAL_RESET_HI 8
+#define SDIO_PARTIAL_RESET_SZ 1
+#define SDIO_ALL_RESET_MSK 0x00000200
+#define SDIO_ALL_RESET_I_MSK 0xfffffdff
+#define SDIO_ALL_RESET_SFT 9
+#define SDIO_ALL_RESET_HI 9
+#define SDIO_ALL_RESET_SZ 1
+#define PERI_MAC_ALL_RESET_MSK 0x00000400
+#define PERI_MAC_ALL_RESET_I_MSK 0xfffffbff
+#define PERI_MAC_ALL_RESET_SFT 10
+#define PERI_MAC_ALL_RESET_HI 10
+#define PERI_MAC_ALL_RESET_SZ 1
+#define MAC_ALL_RESET_MSK 0x00000800
+#define MAC_ALL_RESET_I_MSK 0xfffff7ff
+#define MAC_ALL_RESET_SFT 11
+#define MAC_ALL_RESET_HI 11
+#define MAC_ALL_RESET_SZ 1
+#define AHB_BRIDGE_RESET_MSK 0x00001000
+#define AHB_BRIDGE_RESET_I_MSK 0xffffefff
+#define AHB_BRIDGE_RESET_SFT 12
+#define AHB_BRIDGE_RESET_HI 12
+#define AHB_BRIDGE_RESET_SZ 1
+#define IO_REG_PORT_REG_MSK 0x0001ffff
+#define IO_REG_PORT_REG_I_MSK 0xfffe0000
+#define IO_REG_PORT_REG_SFT 0
+#define IO_REG_PORT_REG_HI 16
+#define IO_REG_PORT_REG_SZ 17
+#define SDIO_FIFO_EMPTY_CNT_MSK 0x0000ffff
+#define SDIO_FIFO_EMPTY_CNT_I_MSK 0xffff0000
+#define SDIO_FIFO_EMPTY_CNT_SFT 0
+#define SDIO_FIFO_EMPTY_CNT_HI 15
+#define SDIO_FIFO_EMPTY_CNT_SZ 16
+#define SDIO_FIFO_FULL_CNT_MSK 0xffff0000
+#define SDIO_FIFO_FULL_CNT_I_MSK 0x0000ffff
+#define SDIO_FIFO_FULL_CNT_SFT 16
+#define SDIO_FIFO_FULL_CNT_HI 31
+#define SDIO_FIFO_FULL_CNT_SZ 16
+#define SDIO_CRC7_ERROR_CNT_MSK 0x0000ffff
+#define SDIO_CRC7_ERROR_CNT_I_MSK 0xffff0000
+#define SDIO_CRC7_ERROR_CNT_SFT 0
+#define SDIO_CRC7_ERROR_CNT_HI 15
+#define SDIO_CRC7_ERROR_CNT_SZ 16
+#define SDIO_CRC16_ERROR_CNT_MSK 0xffff0000
+#define SDIO_CRC16_ERROR_CNT_I_MSK 0x0000ffff
+#define SDIO_CRC16_ERROR_CNT_SFT 16
+#define SDIO_CRC16_ERROR_CNT_HI 31
+#define SDIO_CRC16_ERROR_CNT_SZ 16
+#define SDIO_RD_BLOCK_CNT_MSK 0x000001ff
+#define SDIO_RD_BLOCK_CNT_I_MSK 0xfffffe00
+#define SDIO_RD_BLOCK_CNT_SFT 0
+#define SDIO_RD_BLOCK_CNT_HI 8
+#define SDIO_RD_BLOCK_CNT_SZ 9
+#define SDIO_WR_BLOCK_CNT_MSK 0x01ff0000
+#define SDIO_WR_BLOCK_CNT_I_MSK 0xfe00ffff
+#define SDIO_WR_BLOCK_CNT_SFT 16
+#define SDIO_WR_BLOCK_CNT_HI 24
+#define SDIO_WR_BLOCK_CNT_SZ 9
+#define CMD52_RD_ABORT_CNT_MSK 0x000f0000
+#define CMD52_RD_ABORT_CNT_I_MSK 0xfff0ffff
+#define CMD52_RD_ABORT_CNT_SFT 16
+#define CMD52_RD_ABORT_CNT_HI 19
+#define CMD52_RD_ABORT_CNT_SZ 4
+#define CMD52_WR_ABORT_CNT_MSK 0x00f00000
+#define CMD52_WR_ABORT_CNT_I_MSK 0xff0fffff
+#define CMD52_WR_ABORT_CNT_SFT 20
+#define CMD52_WR_ABORT_CNT_HI 23
+#define CMD52_WR_ABORT_CNT_SZ 4
+#define SDIO_FIFO_WR_PTR_REG_MSK 0x000000ff
+#define SDIO_FIFO_WR_PTR_REG_I_MSK 0xffffff00
+#define SDIO_FIFO_WR_PTR_REG_SFT 0
+#define SDIO_FIFO_WR_PTR_REG_HI 7
+#define SDIO_FIFO_WR_PTR_REG_SZ 8
+#define SDIO_FIFO_RD_PTR_REG_MSK 0x0000ff00
+#define SDIO_FIFO_RD_PTR_REG_I_MSK 0xffff00ff
+#define SDIO_FIFO_RD_PTR_REG_SFT 8
+#define SDIO_FIFO_RD_PTR_REG_HI 15
+#define SDIO_FIFO_RD_PTR_REG_SZ 8
+#define SDIO_READ_DATA_CTRL_MSK 0x00010000
+#define SDIO_READ_DATA_CTRL_I_MSK 0xfffeffff
+#define SDIO_READ_DATA_CTRL_SFT 16
+#define SDIO_READ_DATA_CTRL_HI 16
+#define SDIO_READ_DATA_CTRL_SZ 1
+#define TX_SIZE_BEFORE_SHIFT_MSK 0x000000ff
+#define TX_SIZE_BEFORE_SHIFT_I_MSK 0xffffff00
+#define TX_SIZE_BEFORE_SHIFT_SFT 0
+#define TX_SIZE_BEFORE_SHIFT_HI 7
+#define TX_SIZE_BEFORE_SHIFT_SZ 8
+#define TX_SIZE_SHIFT_BITS_MSK 0x00000700
+#define TX_SIZE_SHIFT_BITS_I_MSK 0xfffff8ff
+#define TX_SIZE_SHIFT_BITS_SFT 8
+#define TX_SIZE_SHIFT_BITS_HI 10
+#define TX_SIZE_SHIFT_BITS_SZ 3
+#define SDIO_TX_ALLOC_STATE_MSK 0x00001000
+#define SDIO_TX_ALLOC_STATE_I_MSK 0xffffefff
+#define SDIO_TX_ALLOC_STATE_SFT 12
+#define SDIO_TX_ALLOC_STATE_HI 12
+#define SDIO_TX_ALLOC_STATE_SZ 1
+#define ALLOCATE_STATUS2_MSK 0x00010000
+#define ALLOCATE_STATUS2_I_MSK 0xfffeffff
+#define ALLOCATE_STATUS2_SFT 16
+#define ALLOCATE_STATUS2_HI 16
+#define ALLOCATE_STATUS2_SZ 1
+#define NO_ALLOCATE_SEND_ERROR_MSK 0x00020000
+#define NO_ALLOCATE_SEND_ERROR_I_MSK 0xfffdffff
+#define NO_ALLOCATE_SEND_ERROR_SFT 17
+#define NO_ALLOCATE_SEND_ERROR_HI 17
+#define NO_ALLOCATE_SEND_ERROR_SZ 1
+#define DOUBLE_ALLOCATE_ERROR_MSK 0x00040000
+#define DOUBLE_ALLOCATE_ERROR_I_MSK 0xfffbffff
+#define DOUBLE_ALLOCATE_ERROR_SFT 18
+#define DOUBLE_ALLOCATE_ERROR_HI 18
+#define DOUBLE_ALLOCATE_ERROR_SZ 1
+#define TX_DONE_STATUS_MSK 0x00080000
+#define TX_DONE_STATUS_I_MSK 0xfff7ffff
+#define TX_DONE_STATUS_SFT 19
+#define TX_DONE_STATUS_HI 19
+#define TX_DONE_STATUS_SZ 1
+#define AHB_HANG2_MSK 0x00100000
+#define AHB_HANG2_I_MSK 0xffefffff
+#define AHB_HANG2_SFT 20
+#define AHB_HANG2_HI 20
+#define AHB_HANG2_SZ 1
+#define HCI_TRX_FINISH2_MSK 0x00200000
+#define HCI_TRX_FINISH2_I_MSK 0xffdfffff
+#define HCI_TRX_FINISH2_SFT 21
+#define HCI_TRX_FINISH2_HI 21
+#define HCI_TRX_FINISH2_SZ 1
+#define INTR_RX_MSK 0x00400000
+#define INTR_RX_I_MSK 0xffbfffff
+#define INTR_RX_SFT 22
+#define INTR_RX_HI 22
+#define INTR_RX_SZ 1
+#define HCI_INPUT_QUEUE_FULL_MSK 0x00800000
+#define HCI_INPUT_QUEUE_FULL_I_MSK 0xff7fffff
+#define HCI_INPUT_QUEUE_FULL_SFT 23
+#define HCI_INPUT_QUEUE_FULL_HI 23
+#define HCI_INPUT_QUEUE_FULL_SZ 1
+#define ALLOCATESTATUS_MSK 0x00000001
+#define ALLOCATESTATUS_I_MSK 0xfffffffe
+#define ALLOCATESTATUS_SFT 0
+#define ALLOCATESTATUS_HI 0
+#define ALLOCATESTATUS_SZ 1
+#define HCI_TRX_FINISH3_MSK 0x00000002
+#define HCI_TRX_FINISH3_I_MSK 0xfffffffd
+#define HCI_TRX_FINISH3_SFT 1
+#define HCI_TRX_FINISH3_HI 1
+#define HCI_TRX_FINISH3_SZ 1
+#define HCI_IN_QUE_EMPTY2_MSK 0x00000004
+#define HCI_IN_QUE_EMPTY2_I_MSK 0xfffffffb
+#define HCI_IN_QUE_EMPTY2_SFT 2
+#define HCI_IN_QUE_EMPTY2_HI 2
+#define HCI_IN_QUE_EMPTY2_SZ 1
+#define MTX_MNG_UPTHOLD_INT_MSK 0x00000008
+#define MTX_MNG_UPTHOLD_INT_I_MSK 0xfffffff7
+#define MTX_MNG_UPTHOLD_INT_SFT 3
+#define MTX_MNG_UPTHOLD_INT_HI 3
+#define MTX_MNG_UPTHOLD_INT_SZ 1
+#define EDCA0_UPTHOLD_INT_MSK 0x00000010
+#define EDCA0_UPTHOLD_INT_I_MSK 0xffffffef
+#define EDCA0_UPTHOLD_INT_SFT 4
+#define EDCA0_UPTHOLD_INT_HI 4
+#define EDCA0_UPTHOLD_INT_SZ 1
+#define EDCA1_UPTHOLD_INT_MSK 0x00000020
+#define EDCA1_UPTHOLD_INT_I_MSK 0xffffffdf
+#define EDCA1_UPTHOLD_INT_SFT 5
+#define EDCA1_UPTHOLD_INT_HI 5
+#define EDCA1_UPTHOLD_INT_SZ 1
+#define EDCA2_UPTHOLD_INT_MSK 0x00000040
+#define EDCA2_UPTHOLD_INT_I_MSK 0xffffffbf
+#define EDCA2_UPTHOLD_INT_SFT 6
+#define EDCA2_UPTHOLD_INT_HI 6
+#define EDCA2_UPTHOLD_INT_SZ 1
+#define EDCA3_UPTHOLD_INT_MSK 0x00000080
+#define EDCA3_UPTHOLD_INT_I_MSK 0xffffff7f
+#define EDCA3_UPTHOLD_INT_SFT 7
+#define EDCA3_UPTHOLD_INT_HI 7
+#define EDCA3_UPTHOLD_INT_SZ 1
+#define TX_PAGE_REMAIN2_MSK 0x0000ff00
+#define TX_PAGE_REMAIN2_I_MSK 0xffff00ff
+#define TX_PAGE_REMAIN2_SFT 8
+#define TX_PAGE_REMAIN2_HI 15
+#define TX_PAGE_REMAIN2_SZ 8
+#define TX_ID_REMAIN3_MSK 0x007f0000
+#define TX_ID_REMAIN3_I_MSK 0xff80ffff
+#define TX_ID_REMAIN3_SFT 16
+#define TX_ID_REMAIN3_HI 22
+#define TX_ID_REMAIN3_SZ 7
+#define HCI_OUTPUT_FF_CNT_0_MSK 0x00800000
+#define HCI_OUTPUT_FF_CNT_0_I_MSK 0xff7fffff
+#define HCI_OUTPUT_FF_CNT_0_SFT 23
+#define HCI_OUTPUT_FF_CNT_0_HI 23
+#define HCI_OUTPUT_FF_CNT_0_SZ 1
+#define HCI_OUTPUT_FF_CNT2_MSK 0x0f000000
+#define HCI_OUTPUT_FF_CNT2_I_MSK 0xf0ffffff
+#define HCI_OUTPUT_FF_CNT2_SFT 24
+#define HCI_OUTPUT_FF_CNT2_HI 27
+#define HCI_OUTPUT_FF_CNT2_SZ 4
+#define HCI_INPUT_FF_CNT2_MSK 0xf0000000
+#define HCI_INPUT_FF_CNT2_I_MSK 0x0fffffff
+#define HCI_INPUT_FF_CNT2_SFT 28
+#define HCI_INPUT_FF_CNT2_HI 31
+#define HCI_INPUT_FF_CNT2_SZ 4
+#define F1_BLOCK_SIZE_0_REG_MSK 0x00000fff
+#define F1_BLOCK_SIZE_0_REG_I_MSK 0xfffff000
+#define F1_BLOCK_SIZE_0_REG_SFT 0
+#define F1_BLOCK_SIZE_0_REG_HI 11
+#define F1_BLOCK_SIZE_0_REG_SZ 12
+#define START_BYTE_VALUE2_MSK 0x000000ff
+#define START_BYTE_VALUE2_I_MSK 0xffffff00
+#define START_BYTE_VALUE2_SFT 0
+#define START_BYTE_VALUE2_HI 7
+#define START_BYTE_VALUE2_SZ 8
+#define COMMAND_COUNTER_MSK 0x0000ff00
+#define COMMAND_COUNTER_I_MSK 0xffff00ff
+#define COMMAND_COUNTER_SFT 8
+#define COMMAND_COUNTER_HI 15
+#define COMMAND_COUNTER_SZ 8
+#define CMD_LOG_PART1_MSK 0xffff0000
+#define CMD_LOG_PART1_I_MSK 0x0000ffff
+#define CMD_LOG_PART1_SFT 16
+#define CMD_LOG_PART1_HI 31
+#define CMD_LOG_PART1_SZ 16
+#define CMD_LOG_PART2_MSK 0x00ffffff
+#define CMD_LOG_PART2_I_MSK 0xff000000
+#define CMD_LOG_PART2_SFT 0
+#define CMD_LOG_PART2_HI 23
+#define CMD_LOG_PART2_SZ 24
+#define END_BYTE_VALUE2_MSK 0xff000000
+#define END_BYTE_VALUE2_I_MSK 0x00ffffff
+#define END_BYTE_VALUE2_SFT 24
+#define END_BYTE_VALUE2_HI 31
+#define END_BYTE_VALUE2_SZ 8
+#define RX_PACKET_LENGTH3_MSK 0x0000ffff
+#define RX_PACKET_LENGTH3_I_MSK 0xffff0000
+#define RX_PACKET_LENGTH3_SFT 0
+#define RX_PACKET_LENGTH3_HI 15
+#define RX_PACKET_LENGTH3_SZ 16
+#define RX_INT3_MSK 0x00010000
+#define RX_INT3_I_MSK 0xfffeffff
+#define RX_INT3_SFT 16
+#define RX_INT3_HI 16
+#define RX_INT3_SZ 1
+#define TX_ID_REMAIN2_MSK 0x00fe0000
+#define TX_ID_REMAIN2_I_MSK 0xff01ffff
+#define TX_ID_REMAIN2_SFT 17
+#define TX_ID_REMAIN2_HI 23
+#define TX_ID_REMAIN2_SZ 7
+#define TX_PAGE_REMAIN3_MSK 0xff000000
+#define TX_PAGE_REMAIN3_I_MSK 0x00ffffff
+#define TX_PAGE_REMAIN3_SFT 24
+#define TX_PAGE_REMAIN3_HI 31
+#define TX_PAGE_REMAIN3_SZ 8
+#define CCCR_00H_REG_MSK 0x000000ff
+#define CCCR_00H_REG_I_MSK 0xffffff00
+#define CCCR_00H_REG_SFT 0
+#define CCCR_00H_REG_HI 7
+#define CCCR_00H_REG_SZ 8
+#define CCCR_02H_REG_MSK 0x00ff0000
+#define CCCR_02H_REG_I_MSK 0xff00ffff
+#define CCCR_02H_REG_SFT 16
+#define CCCR_02H_REG_HI 23
+#define CCCR_02H_REG_SZ 8
+#define CCCR_03H_REG_MSK 0xff000000
+#define CCCR_03H_REG_I_MSK 0x00ffffff
+#define CCCR_03H_REG_SFT 24
+#define CCCR_03H_REG_HI 31
+#define CCCR_03H_REG_SZ 8
+#define CCCR_04H_REG_MSK 0x000000ff
+#define CCCR_04H_REG_I_MSK 0xffffff00
+#define CCCR_04H_REG_SFT 0
+#define CCCR_04H_REG_HI 7
+#define CCCR_04H_REG_SZ 8
+#define CCCR_05H_REG_MSK 0x0000ff00
+#define CCCR_05H_REG_I_MSK 0xffff00ff
+#define CCCR_05H_REG_SFT 8
+#define CCCR_05H_REG_HI 15
+#define CCCR_05H_REG_SZ 8
+#define CCCR_06H_REG_MSK 0x000f0000
+#define CCCR_06H_REG_I_MSK 0xfff0ffff
+#define CCCR_06H_REG_SFT 16
+#define CCCR_06H_REG_HI 19
+#define CCCR_06H_REG_SZ 4
+#define CCCR_07H_REG_MSK 0xff000000
+#define CCCR_07H_REG_I_MSK 0x00ffffff
+#define CCCR_07H_REG_SFT 24
+#define CCCR_07H_REG_HI 31
+#define CCCR_07H_REG_SZ 8
+#define SUPPORT_DIRECT_COMMAND_SDIO_MSK 0x00000001
+#define SUPPORT_DIRECT_COMMAND_SDIO_I_MSK 0xfffffffe
+#define SUPPORT_DIRECT_COMMAND_SDIO_SFT 0
+#define SUPPORT_DIRECT_COMMAND_SDIO_HI 0
+#define SUPPORT_DIRECT_COMMAND_SDIO_SZ 1
+#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_MSK 0x00000002
+#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_I_MSK 0xfffffffd
+#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_SFT 1
+#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_HI 1
+#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_SZ 1
+#define SUPPORT_READ_WAIT_MSK 0x00000004
+#define SUPPORT_READ_WAIT_I_MSK 0xfffffffb
+#define SUPPORT_READ_WAIT_SFT 2
+#define SUPPORT_READ_WAIT_HI 2
+#define SUPPORT_READ_WAIT_SZ 1
+#define SUPPORT_BUS_CONTROL_MSK 0x00000008
+#define SUPPORT_BUS_CONTROL_I_MSK 0xfffffff7
+#define SUPPORT_BUS_CONTROL_SFT 3
+#define SUPPORT_BUS_CONTROL_HI 3
+#define SUPPORT_BUS_CONTROL_SZ 1
+#define SUPPORT_BLOCK_GAP_INTERRUPT_MSK 0x00000010
+#define SUPPORT_BLOCK_GAP_INTERRUPT_I_MSK 0xffffffef
+#define SUPPORT_BLOCK_GAP_INTERRUPT_SFT 4
+#define SUPPORT_BLOCK_GAP_INTERRUPT_HI 4
+#define SUPPORT_BLOCK_GAP_INTERRUPT_SZ 1
+#define ENABLE_BLOCK_GAP_INTERRUPT_MSK 0x00000020
+#define ENABLE_BLOCK_GAP_INTERRUPT_I_MSK 0xffffffdf
+#define ENABLE_BLOCK_GAP_INTERRUPT_SFT 5
+#define ENABLE_BLOCK_GAP_INTERRUPT_HI 5
+#define ENABLE_BLOCK_GAP_INTERRUPT_SZ 1
+#define LOW_SPEED_CARD_MSK 0x00000040
+#define LOW_SPEED_CARD_I_MSK 0xffffffbf
+#define LOW_SPEED_CARD_SFT 6
+#define LOW_SPEED_CARD_HI 6
+#define LOW_SPEED_CARD_SZ 1
+#define LOW_SPEED_CARD_4BIT_MSK 0x00000080
+#define LOW_SPEED_CARD_4BIT_I_MSK 0xffffff7f
+#define LOW_SPEED_CARD_4BIT_SFT 7
+#define LOW_SPEED_CARD_4BIT_HI 7
+#define LOW_SPEED_CARD_4BIT_SZ 1
+#define COMMON_CIS_PONTER_MSK 0x01ffff00
+#define COMMON_CIS_PONTER_I_MSK 0xfe0000ff
+#define COMMON_CIS_PONTER_SFT 8
+#define COMMON_CIS_PONTER_HI 24
+#define COMMON_CIS_PONTER_SZ 17
+#define SUPPORT_HIGH_SPEED_MSK 0x01000000
+#define SUPPORT_HIGH_SPEED_I_MSK 0xfeffffff
+#define SUPPORT_HIGH_SPEED_SFT 24
+#define SUPPORT_HIGH_SPEED_HI 24
+#define SUPPORT_HIGH_SPEED_SZ 1
+#define BSS_MSK 0x0e000000
+#define BSS_I_MSK 0xf1ffffff
+#define BSS_SFT 25
+#define BSS_HI 27
+#define BSS_SZ 3
+#define FBR_100H_REG_MSK 0x0000000f
+#define FBR_100H_REG_I_MSK 0xfffffff0
+#define FBR_100H_REG_SFT 0
+#define FBR_100H_REG_HI 3
+#define FBR_100H_REG_SZ 4
+#define CSASUPPORT_MSK 0x00000040
+#define CSASUPPORT_I_MSK 0xffffffbf
+#define CSASUPPORT_SFT 6
+#define CSASUPPORT_HI 6
+#define CSASUPPORT_SZ 1
+#define ENABLECSA_MSK 0x00000080
+#define ENABLECSA_I_MSK 0xffffff7f
+#define ENABLECSA_SFT 7
+#define ENABLECSA_HI 7
+#define ENABLECSA_SZ 1
+#define FBR_101H_REG_MSK 0x0000ff00
+#define FBR_101H_REG_I_MSK 0xffff00ff
+#define FBR_101H_REG_SFT 8
+#define FBR_101H_REG_HI 15
+#define FBR_101H_REG_SZ 8
+#define FBR_109H_REG_MSK 0x01ffff00
+#define FBR_109H_REG_I_MSK 0xfe0000ff
+#define FBR_109H_REG_SFT 8
+#define FBR_109H_REG_HI 24
+#define FBR_109H_REG_SZ 17
+#define F0_CIS_CONTENT_REG_31_0_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_31_0_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_31_0_SFT 0
+#define F0_CIS_CONTENT_REG_31_0_HI 31
+#define F0_CIS_CONTENT_REG_31_0_SZ 32
+#define F0_CIS_CONTENT_REG_63_32_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_63_32_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_63_32_SFT 0
+#define F0_CIS_CONTENT_REG_63_32_HI 31
+#define F0_CIS_CONTENT_REG_63_32_SZ 32
+#define F0_CIS_CONTENT_REG_95_64_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_95_64_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_95_64_SFT 0
+#define F0_CIS_CONTENT_REG_95_64_HI 31
+#define F0_CIS_CONTENT_REG_95_64_SZ 32
+#define F0_CIS_CONTENT_REG_127_96_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_127_96_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_127_96_SFT 0
+#define F0_CIS_CONTENT_REG_127_96_HI 31
+#define F0_CIS_CONTENT_REG_127_96_SZ 32
+#define F0_CIS_CONTENT_REG_159_128_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_159_128_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_159_128_SFT 0
+#define F0_CIS_CONTENT_REG_159_128_HI 31
+#define F0_CIS_CONTENT_REG_159_128_SZ 32
+#define F0_CIS_CONTENT_REG_191_160_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_191_160_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_191_160_SFT 0
+#define F0_CIS_CONTENT_REG_191_160_HI 31
+#define F0_CIS_CONTENT_REG_191_160_SZ 32
+#define F0_CIS_CONTENT_REG_223_192_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_223_192_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_223_192_SFT 0
+#define F0_CIS_CONTENT_REG_223_192_HI 31
+#define F0_CIS_CONTENT_REG_223_192_SZ 32
+#define F0_CIS_CONTENT_REG_255_224_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_255_224_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_255_224_SFT 0
+#define F0_CIS_CONTENT_REG_255_224_HI 31
+#define F0_CIS_CONTENT_REG_255_224_SZ 32
+#define F0_CIS_CONTENT_REG_287_256_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_287_256_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_287_256_SFT 0
+#define F0_CIS_CONTENT_REG_287_256_HI 31
+#define F0_CIS_CONTENT_REG_287_256_SZ 32
+#define F0_CIS_CONTENT_REG_319_288_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_319_288_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_319_288_SFT 0
+#define F0_CIS_CONTENT_REG_319_288_HI 31
+#define F0_CIS_CONTENT_REG_319_288_SZ 32
+#define F0_CIS_CONTENT_REG_351_320_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_351_320_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_351_320_SFT 0
+#define F0_CIS_CONTENT_REG_351_320_HI 31
+#define F0_CIS_CONTENT_REG_351_320_SZ 32
+#define F0_CIS_CONTENT_REG_383_352_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_383_352_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_383_352_SFT 0
+#define F0_CIS_CONTENT_REG_383_352_HI 31
+#define F0_CIS_CONTENT_REG_383_352_SZ 32
+#define F0_CIS_CONTENT_REG_415_384_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_415_384_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_415_384_SFT 0
+#define F0_CIS_CONTENT_REG_415_384_HI 31
+#define F0_CIS_CONTENT_REG_415_384_SZ 32
+#define F0_CIS_CONTENT_REG_447_416_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_447_416_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_447_416_SFT 0
+#define F0_CIS_CONTENT_REG_447_416_HI 31
+#define F0_CIS_CONTENT_REG_447_416_SZ 32
+#define F0_CIS_CONTENT_REG_479_448_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_479_448_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_479_448_SFT 0
+#define F0_CIS_CONTENT_REG_479_448_HI 31
+#define F0_CIS_CONTENT_REG_479_448_SZ 32
+#define F0_CIS_CONTENT_REG_511_480_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_511_480_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_511_480_SFT 0
+#define F0_CIS_CONTENT_REG_511_480_HI 31
+#define F0_CIS_CONTENT_REG_511_480_SZ 32
+#define F1_CIS_CONTENT_REG_31_0_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_31_0_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_31_0_SFT 0
+#define F1_CIS_CONTENT_REG_31_0_HI 31
+#define F1_CIS_CONTENT_REG_31_0_SZ 32
+#define F1_CIS_CONTENT_REG_63_32_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_63_32_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_63_32_SFT 0
+#define F1_CIS_CONTENT_REG_63_32_HI 31
+#define F1_CIS_CONTENT_REG_63_32_SZ 32
+#define F1_CIS_CONTENT_REG_95_64_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_95_64_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_95_64_SFT 0
+#define F1_CIS_CONTENT_REG_95_64_HI 31
+#define F1_CIS_CONTENT_REG_95_64_SZ 32
+#define F1_CIS_CONTENT_REG_127_96_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_127_96_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_127_96_SFT 0
+#define F1_CIS_CONTENT_REG_127_96_HI 31
+#define F1_CIS_CONTENT_REG_127_96_SZ 32
+#define F1_CIS_CONTENT_REG_159_128_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_159_128_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_159_128_SFT 0
+#define F1_CIS_CONTENT_REG_159_128_HI 31
+#define F1_CIS_CONTENT_REG_159_128_SZ 32
+#define F1_CIS_CONTENT_REG_191_160_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_191_160_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_191_160_SFT 0
+#define F1_CIS_CONTENT_REG_191_160_HI 31
+#define F1_CIS_CONTENT_REG_191_160_SZ 32
+#define F1_CIS_CONTENT_REG_223_192_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_223_192_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_223_192_SFT 0
+#define F1_CIS_CONTENT_REG_223_192_HI 31
+#define F1_CIS_CONTENT_REG_223_192_SZ 32
+#define F1_CIS_CONTENT_REG_255_224_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_255_224_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_255_224_SFT 0
+#define F1_CIS_CONTENT_REG_255_224_HI 31
+#define F1_CIS_CONTENT_REG_255_224_SZ 32
+#define F1_CIS_CONTENT_REG_287_256_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_287_256_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_287_256_SFT 0
+#define F1_CIS_CONTENT_REG_287_256_HI 31
+#define F1_CIS_CONTENT_REG_287_256_SZ 32
+#define F1_CIS_CONTENT_REG_319_288_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_319_288_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_319_288_SFT 0
+#define F1_CIS_CONTENT_REG_319_288_HI 31
+#define F1_CIS_CONTENT_REG_319_288_SZ 32
+#define F1_CIS_CONTENT_REG_351_320_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_351_320_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_351_320_SFT 0
+#define F1_CIS_CONTENT_REG_351_320_HI 31
+#define F1_CIS_CONTENT_REG_351_320_SZ 32
+#define F1_CIS_CONTENT_REG_383_352_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_383_352_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_383_352_SFT 0
+#define F1_CIS_CONTENT_REG_383_352_HI 31
+#define F1_CIS_CONTENT_REG_383_352_SZ 32
+#define F1_CIS_CONTENT_REG_415_384_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_415_384_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_415_384_SFT 0
+#define F1_CIS_CONTENT_REG_415_384_HI 31
+#define F1_CIS_CONTENT_REG_415_384_SZ 32
+#define F1_CIS_CONTENT_REG_447_416_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_447_416_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_447_416_SFT 0
+#define F1_CIS_CONTENT_REG_447_416_HI 31
+#define F1_CIS_CONTENT_REG_447_416_SZ 32
+#define F1_CIS_CONTENT_REG_479_448_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_479_448_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_479_448_SFT 0
+#define F1_CIS_CONTENT_REG_479_448_HI 31
+#define F1_CIS_CONTENT_REG_479_448_SZ 32
+#define F1_CIS_CONTENT_REG_511_480_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_511_480_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_511_480_SFT 0
+#define F1_CIS_CONTENT_REG_511_480_HI 31
+#define F1_CIS_CONTENT_REG_511_480_SZ 32
+#define SPI_MODE_MSK 0xffffffff
+#define SPI_MODE_I_MSK 0x00000000
+#define SPI_MODE_SFT 0
+#define SPI_MODE_HI 31
+#define SPI_MODE_SZ 32
+#define RX_QUOTA_MSK 0x0000ffff
+#define RX_QUOTA_I_MSK 0xffff0000
+#define RX_QUOTA_SFT 0
+#define RX_QUOTA_HI 15
+#define RX_QUOTA_SZ 16
+#define CONDI_NUM_MSK 0x000000ff
+#define CONDI_NUM_I_MSK 0xffffff00
+#define CONDI_NUM_SFT 0
+#define CONDI_NUM_HI 7
+#define CONDI_NUM_SZ 8
+#define HOST_PATH_MSK 0x00000001
+#define HOST_PATH_I_MSK 0xfffffffe
+#define HOST_PATH_SFT 0
+#define HOST_PATH_HI 0
+#define HOST_PATH_SZ 1
+#define TX_SEG_MSK 0xffffffff
+#define TX_SEG_I_MSK 0x00000000
+#define TX_SEG_SFT 0
+#define TX_SEG_HI 31
+#define TX_SEG_SZ 32
+#define BRST_MODE_MSK 0x00000001
+#define BRST_MODE_I_MSK 0xfffffffe
+#define BRST_MODE_SFT 0
+#define BRST_MODE_HI 0
+#define BRST_MODE_SZ 1
+#define CLK_WIDTH_MSK 0x0000ffff
+#define CLK_WIDTH_I_MSK 0xffff0000
+#define CLK_WIDTH_SFT 0
+#define CLK_WIDTH_HI 15
+#define CLK_WIDTH_SZ 16
+#define CSN_INTER_MSK 0xffff0000
+#define CSN_INTER_I_MSK 0x0000ffff
+#define CSN_INTER_SFT 16
+#define CSN_INTER_HI 31
+#define CSN_INTER_SZ 16
+#define BACK_DLY_MSK 0x0000ffff
+#define BACK_DLY_I_MSK 0xffff0000
+#define BACK_DLY_SFT 0
+#define BACK_DLY_HI 15
+#define BACK_DLY_SZ 16
+#define FRONT_DLY_MSK 0xffff0000
+#define FRONT_DLY_I_MSK 0x0000ffff
+#define FRONT_DLY_SFT 16
+#define FRONT_DLY_HI 31
+#define FRONT_DLY_SZ 16
+#define RX_FIFO_FAIL_MSK 0x00000002
+#define RX_FIFO_FAIL_I_MSK 0xfffffffd
+#define RX_FIFO_FAIL_SFT 1
+#define RX_FIFO_FAIL_HI 1
+#define RX_FIFO_FAIL_SZ 1
+#define RX_HOST_FAIL_MSK 0x00000004
+#define RX_HOST_FAIL_I_MSK 0xfffffffb
+#define RX_HOST_FAIL_SFT 2
+#define RX_HOST_FAIL_HI 2
+#define RX_HOST_FAIL_SZ 1
+#define TX_FIFO_FAIL_MSK 0x00000008
+#define TX_FIFO_FAIL_I_MSK 0xfffffff7
+#define TX_FIFO_FAIL_SFT 3
+#define TX_FIFO_FAIL_HI 3
+#define TX_FIFO_FAIL_SZ 1
+#define TX_HOST_FAIL_MSK 0x00000010
+#define TX_HOST_FAIL_I_MSK 0xffffffef
+#define TX_HOST_FAIL_SFT 4
+#define TX_HOST_FAIL_HI 4
+#define TX_HOST_FAIL_SZ 1
+#define SPI_DOUBLE_ALLOC_MSK 0x00000020
+#define SPI_DOUBLE_ALLOC_I_MSK 0xffffffdf
+#define SPI_DOUBLE_ALLOC_SFT 5
+#define SPI_DOUBLE_ALLOC_HI 5
+#define SPI_DOUBLE_ALLOC_SZ 1
+#define SPI_TX_NO_ALLOC_MSK 0x00000040
+#define SPI_TX_NO_ALLOC_I_MSK 0xffffffbf
+#define SPI_TX_NO_ALLOC_SFT 6
+#define SPI_TX_NO_ALLOC_HI 6
+#define SPI_TX_NO_ALLOC_SZ 1
+#define RDATA_RDY_MSK 0x00000080
+#define RDATA_RDY_I_MSK 0xffffff7f
+#define RDATA_RDY_SFT 7
+#define RDATA_RDY_HI 7
+#define RDATA_RDY_SZ 1
+#define SPI_ALLOC_STATUS_MSK 0x00000100
+#define SPI_ALLOC_STATUS_I_MSK 0xfffffeff
+#define SPI_ALLOC_STATUS_SFT 8
+#define SPI_ALLOC_STATUS_HI 8
+#define SPI_ALLOC_STATUS_SZ 1
+#define SPI_DBG_WR_FIFO_FULL_MSK 0x00000200
+#define SPI_DBG_WR_FIFO_FULL_I_MSK 0xfffffdff
+#define SPI_DBG_WR_FIFO_FULL_SFT 9
+#define SPI_DBG_WR_FIFO_FULL_HI 9
+#define SPI_DBG_WR_FIFO_FULL_SZ 1
+#define RX_LEN_MSK 0xffff0000
+#define RX_LEN_I_MSK 0x0000ffff
+#define RX_LEN_SFT 16
+#define RX_LEN_HI 31
+#define RX_LEN_SZ 16
+#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_MSK 0x00000007
+#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_I_MSK 0xfffffff8
+#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_SFT 0
+#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_HI 2
+#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_SZ 3
+#define SPI_HOST_TX_ALLOC_PKBUF_MSK 0x00000100
+#define SPI_HOST_TX_ALLOC_PKBUF_I_MSK 0xfffffeff
+#define SPI_HOST_TX_ALLOC_PKBUF_SFT 8
+#define SPI_HOST_TX_ALLOC_PKBUF_HI 8
+#define SPI_HOST_TX_ALLOC_PKBUF_SZ 1
+#define SPI_TX_ALLOC_SIZE_MSK 0x000000ff
+#define SPI_TX_ALLOC_SIZE_I_MSK 0xffffff00
+#define SPI_TX_ALLOC_SIZE_SFT 0
+#define SPI_TX_ALLOC_SIZE_HI 7
+#define SPI_TX_ALLOC_SIZE_SZ 8
+#define RD_DAT_CNT_MSK 0x0000ffff
+#define RD_DAT_CNT_I_MSK 0xffff0000
+#define RD_DAT_CNT_SFT 0
+#define RD_DAT_CNT_HI 15
+#define RD_DAT_CNT_SZ 16
+#define RD_STS_CNT_MSK 0xffff0000
+#define RD_STS_CNT_I_MSK 0x0000ffff
+#define RD_STS_CNT_SFT 16
+#define RD_STS_CNT_HI 31
+#define RD_STS_CNT_SZ 16
+#define JUDGE_CNT_MSK 0x0000ffff
+#define JUDGE_CNT_I_MSK 0xffff0000
+#define JUDGE_CNT_SFT 0
+#define JUDGE_CNT_HI 15
+#define JUDGE_CNT_SZ 16
+#define RD_STS_CNT_CLR_MSK 0x00010000
+#define RD_STS_CNT_CLR_I_MSK 0xfffeffff
+#define RD_STS_CNT_CLR_SFT 16
+#define RD_STS_CNT_CLR_HI 16
+#define RD_STS_CNT_CLR_SZ 1
+#define RD_DAT_CNT_CLR_MSK 0x00020000
+#define RD_DAT_CNT_CLR_I_MSK 0xfffdffff
+#define RD_DAT_CNT_CLR_SFT 17
+#define RD_DAT_CNT_CLR_HI 17
+#define RD_DAT_CNT_CLR_SZ 1
+#define JUDGE_CNT_CLR_MSK 0x00040000
+#define JUDGE_CNT_CLR_I_MSK 0xfffbffff
+#define JUDGE_CNT_CLR_SFT 18
+#define JUDGE_CNT_CLR_HI 18
+#define JUDGE_CNT_CLR_SZ 1
+#define TX_DONE_CNT_MSK 0x0000ffff
+#define TX_DONE_CNT_I_MSK 0xffff0000
+#define TX_DONE_CNT_SFT 0
+#define TX_DONE_CNT_HI 15
+#define TX_DONE_CNT_SZ 16
+#define TX_DISCARD_CNT_MSK 0xffff0000
+#define TX_DISCARD_CNT_I_MSK 0x0000ffff
+#define TX_DISCARD_CNT_SFT 16
+#define TX_DISCARD_CNT_HI 31
+#define TX_DISCARD_CNT_SZ 16
+#define TX_SET_CNT_MSK 0x0000ffff
+#define TX_SET_CNT_I_MSK 0xffff0000
+#define TX_SET_CNT_SFT 0
+#define TX_SET_CNT_HI 15
+#define TX_SET_CNT_SZ 16
+#define TX_DISCARD_CNT_CLR_MSK 0x00010000
+#define TX_DISCARD_CNT_CLR_I_MSK 0xfffeffff
+#define TX_DISCARD_CNT_CLR_SFT 16
+#define TX_DISCARD_CNT_CLR_HI 16
+#define TX_DISCARD_CNT_CLR_SZ 1
+#define TX_DONE_CNT_CLR_MSK 0x00020000
+#define TX_DONE_CNT_CLR_I_MSK 0xfffdffff
+#define TX_DONE_CNT_CLR_SFT 17
+#define TX_DONE_CNT_CLR_HI 17
+#define TX_DONE_CNT_CLR_SZ 1
+#define TX_SET_CNT_CLR_MSK 0x00040000
+#define TX_SET_CNT_CLR_I_MSK 0xfffbffff
+#define TX_SET_CNT_CLR_SFT 18
+#define TX_SET_CNT_CLR_HI 18
+#define TX_SET_CNT_CLR_SZ 1
+#define DAT_MODE_OFF_MSK 0x00080000
+#define DAT_MODE_OFF_I_MSK 0xfff7ffff
+#define DAT_MODE_OFF_SFT 19
+#define DAT_MODE_OFF_HI 19
+#define DAT_MODE_OFF_SZ 1
+#define TX_FIFO_RESIDUE_MSK 0x00700000
+#define TX_FIFO_RESIDUE_I_MSK 0xff8fffff
+#define TX_FIFO_RESIDUE_SFT 20
+#define TX_FIFO_RESIDUE_HI 22
+#define TX_FIFO_RESIDUE_SZ 3
+#define RX_FIFO_RESIDUE_MSK 0x07000000
+#define RX_FIFO_RESIDUE_I_MSK 0xf8ffffff
+#define RX_FIFO_RESIDUE_SFT 24
+#define RX_FIFO_RESIDUE_HI 26
+#define RX_FIFO_RESIDUE_SZ 3
+#define RX_RDY_MSK 0x00000001
+#define RX_RDY_I_MSK 0xfffffffe
+#define RX_RDY_SFT 0
+#define RX_RDY_HI 0
+#define RX_RDY_SZ 1
+#define SDIO_SYS_INT_MSK 0x00000004
+#define SDIO_SYS_INT_I_MSK 0xfffffffb
+#define SDIO_SYS_INT_SFT 2
+#define SDIO_SYS_INT_HI 2
+#define SDIO_SYS_INT_SZ 1
+#define EDCA0_LOWTHOLD_INT_MSK 0x00000008
+#define EDCA0_LOWTHOLD_INT_I_MSK 0xfffffff7
+#define EDCA0_LOWTHOLD_INT_SFT 3
+#define EDCA0_LOWTHOLD_INT_HI 3
+#define EDCA0_LOWTHOLD_INT_SZ 1
+#define EDCA1_LOWTHOLD_INT_MSK 0x00000010
+#define EDCA1_LOWTHOLD_INT_I_MSK 0xffffffef
+#define EDCA1_LOWTHOLD_INT_SFT 4
+#define EDCA1_LOWTHOLD_INT_HI 4
+#define EDCA1_LOWTHOLD_INT_SZ 1
+#define EDCA2_LOWTHOLD_INT_MSK 0x00000020
+#define EDCA2_LOWTHOLD_INT_I_MSK 0xffffffdf
+#define EDCA2_LOWTHOLD_INT_SFT 5
+#define EDCA2_LOWTHOLD_INT_HI 5
+#define EDCA2_LOWTHOLD_INT_SZ 1
+#define EDCA3_LOWTHOLD_INT_MSK 0x00000040
+#define EDCA3_LOWTHOLD_INT_I_MSK 0xffffffbf
+#define EDCA3_LOWTHOLD_INT_SFT 6
+#define EDCA3_LOWTHOLD_INT_HI 6
+#define EDCA3_LOWTHOLD_INT_SZ 1
+#define TX_LIMIT_INT_IN_MSK 0x00000080
+#define TX_LIMIT_INT_IN_I_MSK 0xffffff7f
+#define TX_LIMIT_INT_IN_SFT 7
+#define TX_LIMIT_INT_IN_HI 7
+#define TX_LIMIT_INT_IN_SZ 1
+#define SPI_FN1_MSK 0x00007f00
+#define SPI_FN1_I_MSK 0xffff80ff
+#define SPI_FN1_SFT 8
+#define SPI_FN1_HI 14
+#define SPI_FN1_SZ 7
+#define SPI_CLK_EN_INT_MSK 0x00008000
+#define SPI_CLK_EN_INT_I_MSK 0xffff7fff
+#define SPI_CLK_EN_INT_SFT 15
+#define SPI_CLK_EN_INT_HI 15
+#define SPI_CLK_EN_INT_SZ 1
+#define SPI_HOST_MASK_MSK 0x00ff0000
+#define SPI_HOST_MASK_I_MSK 0xff00ffff
+#define SPI_HOST_MASK_SFT 16
+#define SPI_HOST_MASK_HI 23
+#define SPI_HOST_MASK_SZ 8
+#define I2CM_INT_WDONE_MSK 0x00000001
+#define I2CM_INT_WDONE_I_MSK 0xfffffffe
+#define I2CM_INT_WDONE_SFT 0
+#define I2CM_INT_WDONE_HI 0
+#define I2CM_INT_WDONE_SZ 1
+#define I2CM_INT_RDONE_MSK 0x00000002
+#define I2CM_INT_RDONE_I_MSK 0xfffffffd
+#define I2CM_INT_RDONE_SFT 1
+#define I2CM_INT_RDONE_HI 1
+#define I2CM_INT_RDONE_SZ 1
+#define I2CM_IDLE_MSK 0x00000004
+#define I2CM_IDLE_I_MSK 0xfffffffb
+#define I2CM_IDLE_SFT 2
+#define I2CM_IDLE_HI 2
+#define I2CM_IDLE_SZ 1
+#define I2CM_INT_MISMATCH_MSK 0x00000008
+#define I2CM_INT_MISMATCH_I_MSK 0xfffffff7
+#define I2CM_INT_MISMATCH_SFT 3
+#define I2CM_INT_MISMATCH_HI 3
+#define I2CM_INT_MISMATCH_SZ 1
+#define I2CM_PSCL_MSK 0x00003ff0
+#define I2CM_PSCL_I_MSK 0xffffc00f
+#define I2CM_PSCL_SFT 4
+#define I2CM_PSCL_HI 13
+#define I2CM_PSCL_SZ 10
+#define I2CM_MANUAL_MODE_MSK 0x00010000
+#define I2CM_MANUAL_MODE_I_MSK 0xfffeffff
+#define I2CM_MANUAL_MODE_SFT 16
+#define I2CM_MANUAL_MODE_HI 16
+#define I2CM_MANUAL_MODE_SZ 1
+#define I2CM_INT_WDATA_NEED_MSK 0x00020000
+#define I2CM_INT_WDATA_NEED_I_MSK 0xfffdffff
+#define I2CM_INT_WDATA_NEED_SFT 17
+#define I2CM_INT_WDATA_NEED_HI 17
+#define I2CM_INT_WDATA_NEED_SZ 1
+#define I2CM_INT_RDATA_NEED_MSK 0x00040000
+#define I2CM_INT_RDATA_NEED_I_MSK 0xfffbffff
+#define I2CM_INT_RDATA_NEED_SFT 18
+#define I2CM_INT_RDATA_NEED_HI 18
+#define I2CM_INT_RDATA_NEED_SZ 1
+#define I2CM_DEV_A_MSK 0x000003ff
+#define I2CM_DEV_A_I_MSK 0xfffffc00
+#define I2CM_DEV_A_SFT 0
+#define I2CM_DEV_A_HI 9
+#define I2CM_DEV_A_SZ 10
+#define I2CM_DEV_A10B_MSK 0x00004000
+#define I2CM_DEV_A10B_I_MSK 0xffffbfff
+#define I2CM_DEV_A10B_SFT 14
+#define I2CM_DEV_A10B_HI 14
+#define I2CM_DEV_A10B_SZ 1
+#define I2CM_RX_MSK 0x00008000
+#define I2CM_RX_I_MSK 0xffff7fff
+#define I2CM_RX_SFT 15
+#define I2CM_RX_HI 15
+#define I2CM_RX_SZ 1
+#define I2CM_LEN_MSK 0x0000ffff
+#define I2CM_LEN_I_MSK 0xffff0000
+#define I2CM_LEN_SFT 0
+#define I2CM_LEN_HI 15
+#define I2CM_LEN_SZ 16
+#define I2CM_T_LEFT_MSK 0x00070000
+#define I2CM_T_LEFT_I_MSK 0xfff8ffff
+#define I2CM_T_LEFT_SFT 16
+#define I2CM_T_LEFT_HI 18
+#define I2CM_T_LEFT_SZ 3
+#define I2CM_R_GET_MSK 0x07000000
+#define I2CM_R_GET_I_MSK 0xf8ffffff
+#define I2CM_R_GET_SFT 24
+#define I2CM_R_GET_HI 26
+#define I2CM_R_GET_SZ 3
+#define I2CM_WDAT_MSK 0xffffffff
+#define I2CM_WDAT_I_MSK 0x00000000
+#define I2CM_WDAT_SFT 0
+#define I2CM_WDAT_HI 31
+#define I2CM_WDAT_SZ 32
+#define I2CM_RDAT_MSK 0xffffffff
+#define I2CM_RDAT_I_MSK 0x00000000
+#define I2CM_RDAT_SFT 0
+#define I2CM_RDAT_HI 31
+#define I2CM_RDAT_SZ 32
+#define I2CM_SR_LEN_MSK 0x0000ffff
+#define I2CM_SR_LEN_I_MSK 0xffff0000
+#define I2CM_SR_LEN_SFT 0
+#define I2CM_SR_LEN_HI 15
+#define I2CM_SR_LEN_SZ 16
+#define I2CM_SR_RX_MSK 0x00010000
+#define I2CM_SR_RX_I_MSK 0xfffeffff
+#define I2CM_SR_RX_SFT 16
+#define I2CM_SR_RX_HI 16
+#define I2CM_SR_RX_SZ 1
+#define I2CM_REPEAT_START_MSK 0x00020000
+#define I2CM_REPEAT_START_I_MSK 0xfffdffff
+#define I2CM_REPEAT_START_SFT 17
+#define I2CM_REPEAT_START_HI 17
+#define I2CM_REPEAT_START_SZ 1
+#define UART_DATA_MSK 0x000000ff
+#define UART_DATA_I_MSK 0xffffff00
+#define UART_DATA_SFT 0
+#define UART_DATA_HI 7
+#define UART_DATA_SZ 8
+#define DATA_RDY_IE_MSK 0x00000001
+#define DATA_RDY_IE_I_MSK 0xfffffffe
+#define DATA_RDY_IE_SFT 0
+#define DATA_RDY_IE_HI 0
+#define DATA_RDY_IE_SZ 1
+#define THR_EMPTY_IE_MSK 0x00000002
+#define THR_EMPTY_IE_I_MSK 0xfffffffd
+#define THR_EMPTY_IE_SFT 1
+#define THR_EMPTY_IE_HI 1
+#define THR_EMPTY_IE_SZ 1
+#define RX_LINESTS_IE_MSK 0x00000004
+#define RX_LINESTS_IE_I_MSK 0xfffffffb
+#define RX_LINESTS_IE_SFT 2
+#define RX_LINESTS_IE_HI 2
+#define RX_LINESTS_IE_SZ 1
+#define MDM_STS_IE_MSK 0x00000008
+#define MDM_STS_IE_I_MSK 0xfffffff7
+#define MDM_STS_IE_SFT 3
+#define MDM_STS_IE_HI 3
+#define MDM_STS_IE_SZ 1
+#define DMA_RXEND_IE_MSK 0x00000040
+#define DMA_RXEND_IE_I_MSK 0xffffffbf
+#define DMA_RXEND_IE_SFT 6
+#define DMA_RXEND_IE_HI 6
+#define DMA_RXEND_IE_SZ 1
+#define DMA_TXEND_IE_MSK 0x00000080
+#define DMA_TXEND_IE_I_MSK 0xffffff7f
+#define DMA_TXEND_IE_SFT 7
+#define DMA_TXEND_IE_HI 7
+#define DMA_TXEND_IE_SZ 1
+#define FIFO_EN_MSK 0x00000001
+#define FIFO_EN_I_MSK 0xfffffffe
+#define FIFO_EN_SFT 0
+#define FIFO_EN_HI 0
+#define FIFO_EN_SZ 1
+#define RXFIFO_RST_MSK 0x00000002
+#define RXFIFO_RST_I_MSK 0xfffffffd
+#define RXFIFO_RST_SFT 1
+#define RXFIFO_RST_HI 1
+#define RXFIFO_RST_SZ 1
+#define TXFIFO_RST_MSK 0x00000004
+#define TXFIFO_RST_I_MSK 0xfffffffb
+#define TXFIFO_RST_SFT 2
+#define TXFIFO_RST_HI 2
+#define TXFIFO_RST_SZ 1
+#define DMA_MODE_MSK 0x00000008
+#define DMA_MODE_I_MSK 0xfffffff7
+#define DMA_MODE_SFT 3
+#define DMA_MODE_HI 3
+#define DMA_MODE_SZ 1
+#define EN_AUTO_RTS_MSK 0x00000010
+#define EN_AUTO_RTS_I_MSK 0xffffffef
+#define EN_AUTO_RTS_SFT 4
+#define EN_AUTO_RTS_HI 4
+#define EN_AUTO_RTS_SZ 1
+#define EN_AUTO_CTS_MSK 0x00000020
+#define EN_AUTO_CTS_I_MSK 0xffffffdf
+#define EN_AUTO_CTS_SFT 5
+#define EN_AUTO_CTS_HI 5
+#define EN_AUTO_CTS_SZ 1
+#define RXFIFO_TRGLVL_MSK 0x000000c0
+#define RXFIFO_TRGLVL_I_MSK 0xffffff3f
+#define RXFIFO_TRGLVL_SFT 6
+#define RXFIFO_TRGLVL_HI 7
+#define RXFIFO_TRGLVL_SZ 2
+#define WORD_LEN_MSK 0x00000003
+#define WORD_LEN_I_MSK 0xfffffffc
+#define WORD_LEN_SFT 0
+#define WORD_LEN_HI 1
+#define WORD_LEN_SZ 2
+#define STOP_BIT_MSK 0x00000004
+#define STOP_BIT_I_MSK 0xfffffffb
+#define STOP_BIT_SFT 2
+#define STOP_BIT_HI 2
+#define STOP_BIT_SZ 1
+#define PARITY_EN_MSK 0x00000008
+#define PARITY_EN_I_MSK 0xfffffff7
+#define PARITY_EN_SFT 3
+#define PARITY_EN_HI 3
+#define PARITY_EN_SZ 1
+#define EVEN_PARITY_MSK 0x00000010
+#define EVEN_PARITY_I_MSK 0xffffffef
+#define EVEN_PARITY_SFT 4
+#define EVEN_PARITY_HI 4
+#define EVEN_PARITY_SZ 1
+#define FORCE_PARITY_MSK 0x00000020
+#define FORCE_PARITY_I_MSK 0xffffffdf
+#define FORCE_PARITY_SFT 5
+#define FORCE_PARITY_HI 5
+#define FORCE_PARITY_SZ 1
+#define SET_BREAK_MSK 0x00000040
+#define SET_BREAK_I_MSK 0xffffffbf
+#define SET_BREAK_SFT 6
+#define SET_BREAK_HI 6
+#define SET_BREAK_SZ 1
+#define DLAB_MSK 0x00000080
+#define DLAB_I_MSK 0xffffff7f
+#define DLAB_SFT 7
+#define DLAB_HI 7
+#define DLAB_SZ 1
+#define DTR_MSK 0x00000001
+#define DTR_I_MSK 0xfffffffe
+#define DTR_SFT 0
+#define DTR_HI 0
+#define DTR_SZ 1
+#define RTS_MSK 0x00000002
+#define RTS_I_MSK 0xfffffffd
+#define RTS_SFT 1
+#define RTS_HI 1
+#define RTS_SZ 1
+#define OUT_1_MSK 0x00000004
+#define OUT_1_I_MSK 0xfffffffb
+#define OUT_1_SFT 2
+#define OUT_1_HI 2
+#define OUT_1_SZ 1
+#define OUT_2_MSK 0x00000008
+#define OUT_2_I_MSK 0xfffffff7
+#define OUT_2_SFT 3
+#define OUT_2_HI 3
+#define OUT_2_SZ 1
+#define LOOP_BACK_MSK 0x00000010
+#define LOOP_BACK_I_MSK 0xffffffef
+#define LOOP_BACK_SFT 4
+#define LOOP_BACK_HI 4
+#define LOOP_BACK_SZ 1
+#define DATA_RDY_MSK 0x00000001
+#define DATA_RDY_I_MSK 0xfffffffe
+#define DATA_RDY_SFT 0
+#define DATA_RDY_HI 0
+#define DATA_RDY_SZ 1
+#define OVERRUN_ERR_MSK 0x00000002
+#define OVERRUN_ERR_I_MSK 0xfffffffd
+#define OVERRUN_ERR_SFT 1
+#define OVERRUN_ERR_HI 1
+#define OVERRUN_ERR_SZ 1
+#define PARITY_ERR_MSK 0x00000004
+#define PARITY_ERR_I_MSK 0xfffffffb
+#define PARITY_ERR_SFT 2
+#define PARITY_ERR_HI 2
+#define PARITY_ERR_SZ 1
+#define FRAMING_ERR_MSK 0x00000008
+#define FRAMING_ERR_I_MSK 0xfffffff7
+#define FRAMING_ERR_SFT 3
+#define FRAMING_ERR_HI 3
+#define FRAMING_ERR_SZ 1
+#define BREAK_INT_MSK 0x00000010
+#define BREAK_INT_I_MSK 0xffffffef
+#define BREAK_INT_SFT 4
+#define BREAK_INT_HI 4
+#define BREAK_INT_SZ 1
+#define THR_EMPTY_MSK 0x00000020
+#define THR_EMPTY_I_MSK 0xffffffdf
+#define THR_EMPTY_SFT 5
+#define THR_EMPTY_HI 5
+#define THR_EMPTY_SZ 1
+#define TX_EMPTY_MSK 0x00000040
+#define TX_EMPTY_I_MSK 0xffffffbf
+#define TX_EMPTY_SFT 6
+#define TX_EMPTY_HI 6
+#define TX_EMPTY_SZ 1
+#define FIFODATA_ERR_MSK 0x00000080
+#define FIFODATA_ERR_I_MSK 0xffffff7f
+#define FIFODATA_ERR_SFT 7
+#define FIFODATA_ERR_HI 7
+#define FIFODATA_ERR_SZ 1
+#define DELTA_CTS_MSK 0x00000001
+#define DELTA_CTS_I_MSK 0xfffffffe
+#define DELTA_CTS_SFT 0
+#define DELTA_CTS_HI 0
+#define DELTA_CTS_SZ 1
+#define DELTA_DSR_MSK 0x00000002
+#define DELTA_DSR_I_MSK 0xfffffffd
+#define DELTA_DSR_SFT 1
+#define DELTA_DSR_HI 1
+#define DELTA_DSR_SZ 1
+#define TRAILEDGE_RI_MSK 0x00000004
+#define TRAILEDGE_RI_I_MSK 0xfffffffb
+#define TRAILEDGE_RI_SFT 2
+#define TRAILEDGE_RI_HI 2
+#define TRAILEDGE_RI_SZ 1
+#define DELTA_CD_MSK 0x00000008
+#define DELTA_CD_I_MSK 0xfffffff7
+#define DELTA_CD_SFT 3
+#define DELTA_CD_HI 3
+#define DELTA_CD_SZ 1
+#define CTS_MSK 0x00000010
+#define CTS_I_MSK 0xffffffef
+#define CTS_SFT 4
+#define CTS_HI 4
+#define CTS_SZ 1
+#define DSR_MSK 0x00000020
+#define DSR_I_MSK 0xffffffdf
+#define DSR_SFT 5
+#define DSR_HI 5
+#define DSR_SZ 1
+#define RI_MSK 0x00000040
+#define RI_I_MSK 0xffffffbf
+#define RI_SFT 6
+#define RI_HI 6
+#define RI_SZ 1
+#define CD_MSK 0x00000080
+#define CD_I_MSK 0xffffff7f
+#define CD_SFT 7
+#define CD_HI 7
+#define CD_SZ 1
+#define BRDC_DIV_MSK 0x0000ffff
+#define BRDC_DIV_I_MSK 0xffff0000
+#define BRDC_DIV_SFT 0
+#define BRDC_DIV_HI 15
+#define BRDC_DIV_SZ 16
+#define RTHR_L_MSK 0x0000000f
+#define RTHR_L_I_MSK 0xfffffff0
+#define RTHR_L_SFT 0
+#define RTHR_L_HI 3
+#define RTHR_L_SZ 4
+#define RTHR_H_MSK 0x000000f0
+#define RTHR_H_I_MSK 0xffffff0f
+#define RTHR_H_SFT 4
+#define RTHR_H_HI 7
+#define RTHR_H_SZ 4
+#define INT_IDCODE_MSK 0x0000000f
+#define INT_IDCODE_I_MSK 0xfffffff0
+#define INT_IDCODE_SFT 0
+#define INT_IDCODE_HI 3
+#define INT_IDCODE_SZ 4
+#define FIFOS_ENABLED_MSK 0x000000c0
+#define FIFOS_ENABLED_I_MSK 0xffffff3f
+#define FIFOS_ENABLED_SFT 6
+#define FIFOS_ENABLED_HI 7
+#define FIFOS_ENABLED_SZ 2
+#define DAT_UART_DATA_MSK 0x000000ff
+#define DAT_UART_DATA_I_MSK 0xffffff00
+#define DAT_UART_DATA_SFT 0
+#define DAT_UART_DATA_HI 7
+#define DAT_UART_DATA_SZ 8
+#define DAT_DATA_RDY_IE_MSK 0x00000001
+#define DAT_DATA_RDY_IE_I_MSK 0xfffffffe
+#define DAT_DATA_RDY_IE_SFT 0
+#define DAT_DATA_RDY_IE_HI 0
+#define DAT_DATA_RDY_IE_SZ 1
+#define DAT_THR_EMPTY_IE_MSK 0x00000002
+#define DAT_THR_EMPTY_IE_I_MSK 0xfffffffd
+#define DAT_THR_EMPTY_IE_SFT 1
+#define DAT_THR_EMPTY_IE_HI 1
+#define DAT_THR_EMPTY_IE_SZ 1
+#define DAT_RX_LINESTS_IE_MSK 0x00000004
+#define DAT_RX_LINESTS_IE_I_MSK 0xfffffffb
+#define DAT_RX_LINESTS_IE_SFT 2
+#define DAT_RX_LINESTS_IE_HI 2
+#define DAT_RX_LINESTS_IE_SZ 1
+#define DAT_MDM_STS_IE_MSK 0x00000008
+#define DAT_MDM_STS_IE_I_MSK 0xfffffff7
+#define DAT_MDM_STS_IE_SFT 3
+#define DAT_MDM_STS_IE_HI 3
+#define DAT_MDM_STS_IE_SZ 1
+#define DAT_DMA_RXEND_IE_MSK 0x00000040
+#define DAT_DMA_RXEND_IE_I_MSK 0xffffffbf
+#define DAT_DMA_RXEND_IE_SFT 6
+#define DAT_DMA_RXEND_IE_HI 6
+#define DAT_DMA_RXEND_IE_SZ 1
+#define DAT_DMA_TXEND_IE_MSK 0x00000080
+#define DAT_DMA_TXEND_IE_I_MSK 0xffffff7f
+#define DAT_DMA_TXEND_IE_SFT 7
+#define DAT_DMA_TXEND_IE_HI 7
+#define DAT_DMA_TXEND_IE_SZ 1
+#define DAT_FIFO_EN_MSK 0x00000001
+#define DAT_FIFO_EN_I_MSK 0xfffffffe
+#define DAT_FIFO_EN_SFT 0
+#define DAT_FIFO_EN_HI 0
+#define DAT_FIFO_EN_SZ 1
+#define DAT_RXFIFO_RST_MSK 0x00000002
+#define DAT_RXFIFO_RST_I_MSK 0xfffffffd
+#define DAT_RXFIFO_RST_SFT 1
+#define DAT_RXFIFO_RST_HI 1
+#define DAT_RXFIFO_RST_SZ 1
+#define DAT_TXFIFO_RST_MSK 0x00000004
+#define DAT_TXFIFO_RST_I_MSK 0xfffffffb
+#define DAT_TXFIFO_RST_SFT 2
+#define DAT_TXFIFO_RST_HI 2
+#define DAT_TXFIFO_RST_SZ 1
+#define DAT_DMA_MODE_MSK 0x00000008
+#define DAT_DMA_MODE_I_MSK 0xfffffff7
+#define DAT_DMA_MODE_SFT 3
+#define DAT_DMA_MODE_HI 3
+#define DAT_DMA_MODE_SZ 1
+#define DAT_EN_AUTO_RTS_MSK 0x00000010
+#define DAT_EN_AUTO_RTS_I_MSK 0xffffffef
+#define DAT_EN_AUTO_RTS_SFT 4
+#define DAT_EN_AUTO_RTS_HI 4
+#define DAT_EN_AUTO_RTS_SZ 1
+#define DAT_EN_AUTO_CTS_MSK 0x00000020
+#define DAT_EN_AUTO_CTS_I_MSK 0xffffffdf
+#define DAT_EN_AUTO_CTS_SFT 5
+#define DAT_EN_AUTO_CTS_HI 5
+#define DAT_EN_AUTO_CTS_SZ 1
+#define DAT_RXFIFO_TRGLVL_MSK 0x000000c0
+#define DAT_RXFIFO_TRGLVL_I_MSK 0xffffff3f
+#define DAT_RXFIFO_TRGLVL_SFT 6
+#define DAT_RXFIFO_TRGLVL_HI 7
+#define DAT_RXFIFO_TRGLVL_SZ 2
+#define DAT_WORD_LEN_MSK 0x00000003
+#define DAT_WORD_LEN_I_MSK 0xfffffffc
+#define DAT_WORD_LEN_SFT 0
+#define DAT_WORD_LEN_HI 1
+#define DAT_WORD_LEN_SZ 2
+#define DAT_STOP_BIT_MSK 0x00000004
+#define DAT_STOP_BIT_I_MSK 0xfffffffb
+#define DAT_STOP_BIT_SFT 2
+#define DAT_STOP_BIT_HI 2
+#define DAT_STOP_BIT_SZ 1
+#define DAT_PARITY_EN_MSK 0x00000008
+#define DAT_PARITY_EN_I_MSK 0xfffffff7
+#define DAT_PARITY_EN_SFT 3
+#define DAT_PARITY_EN_HI 3
+#define DAT_PARITY_EN_SZ 1
+#define DAT_EVEN_PARITY_MSK 0x00000010
+#define DAT_EVEN_PARITY_I_MSK 0xffffffef
+#define DAT_EVEN_PARITY_SFT 4
+#define DAT_EVEN_PARITY_HI 4
+#define DAT_EVEN_PARITY_SZ 1
+#define DAT_FORCE_PARITY_MSK 0x00000020
+#define DAT_FORCE_PARITY_I_MSK 0xffffffdf
+#define DAT_FORCE_PARITY_SFT 5
+#define DAT_FORCE_PARITY_HI 5
+#define DAT_FORCE_PARITY_SZ 1
+#define DAT_SET_BREAK_MSK 0x00000040
+#define DAT_SET_BREAK_I_MSK 0xffffffbf
+#define DAT_SET_BREAK_SFT 6
+#define DAT_SET_BREAK_HI 6
+#define DAT_SET_BREAK_SZ 1
+#define DAT_DLAB_MSK 0x00000080
+#define DAT_DLAB_I_MSK 0xffffff7f
+#define DAT_DLAB_SFT 7
+#define DAT_DLAB_HI 7
+#define DAT_DLAB_SZ 1
+#define DAT_DTR_MSK 0x00000001
+#define DAT_DTR_I_MSK 0xfffffffe
+#define DAT_DTR_SFT 0
+#define DAT_DTR_HI 0
+#define DAT_DTR_SZ 1
+#define DAT_RTS_MSK 0x00000002
+#define DAT_RTS_I_MSK 0xfffffffd
+#define DAT_RTS_SFT 1
+#define DAT_RTS_HI 1
+#define DAT_RTS_SZ 1
+#define DAT_OUT_1_MSK 0x00000004
+#define DAT_OUT_1_I_MSK 0xfffffffb
+#define DAT_OUT_1_SFT 2
+#define DAT_OUT_1_HI 2
+#define DAT_OUT_1_SZ 1
+#define DAT_OUT_2_MSK 0x00000008
+#define DAT_OUT_2_I_MSK 0xfffffff7
+#define DAT_OUT_2_SFT 3
+#define DAT_OUT_2_HI 3
+#define DAT_OUT_2_SZ 1
+#define DAT_LOOP_BACK_MSK 0x00000010
+#define DAT_LOOP_BACK_I_MSK 0xffffffef
+#define DAT_LOOP_BACK_SFT 4
+#define DAT_LOOP_BACK_HI 4
+#define DAT_LOOP_BACK_SZ 1
+#define DAT_DATA_RDY_MSK 0x00000001
+#define DAT_DATA_RDY_I_MSK 0xfffffffe
+#define DAT_DATA_RDY_SFT 0
+#define DAT_DATA_RDY_HI 0
+#define DAT_DATA_RDY_SZ 1
+#define DAT_OVERRUN_ERR_MSK 0x00000002
+#define DAT_OVERRUN_ERR_I_MSK 0xfffffffd
+#define DAT_OVERRUN_ERR_SFT 1
+#define DAT_OVERRUN_ERR_HI 1
+#define DAT_OVERRUN_ERR_SZ 1
+#define DAT_PARITY_ERR_MSK 0x00000004
+#define DAT_PARITY_ERR_I_MSK 0xfffffffb
+#define DAT_PARITY_ERR_SFT 2
+#define DAT_PARITY_ERR_HI 2
+#define DAT_PARITY_ERR_SZ 1
+#define DAT_FRAMING_ERR_MSK 0x00000008
+#define DAT_FRAMING_ERR_I_MSK 0xfffffff7
+#define DAT_FRAMING_ERR_SFT 3
+#define DAT_FRAMING_ERR_HI 3
+#define DAT_FRAMING_ERR_SZ 1
+#define DAT_BREAK_INT_MSK 0x00000010
+#define DAT_BREAK_INT_I_MSK 0xffffffef
+#define DAT_BREAK_INT_SFT 4
+#define DAT_BREAK_INT_HI 4
+#define DAT_BREAK_INT_SZ 1
+#define DAT_THR_EMPTY_MSK 0x00000020
+#define DAT_THR_EMPTY_I_MSK 0xffffffdf
+#define DAT_THR_EMPTY_SFT 5
+#define DAT_THR_EMPTY_HI 5
+#define DAT_THR_EMPTY_SZ 1
+#define DAT_TX_EMPTY_MSK 0x00000040
+#define DAT_TX_EMPTY_I_MSK 0xffffffbf
+#define DAT_TX_EMPTY_SFT 6
+#define DAT_TX_EMPTY_HI 6
+#define DAT_TX_EMPTY_SZ 1
+#define DAT_FIFODATA_ERR_MSK 0x00000080
+#define DAT_FIFODATA_ERR_I_MSK 0xffffff7f
+#define DAT_FIFODATA_ERR_SFT 7
+#define DAT_FIFODATA_ERR_HI 7
+#define DAT_FIFODATA_ERR_SZ 1
+#define DAT_DELTA_CTS_MSK 0x00000001
+#define DAT_DELTA_CTS_I_MSK 0xfffffffe
+#define DAT_DELTA_CTS_SFT 0
+#define DAT_DELTA_CTS_HI 0
+#define DAT_DELTA_CTS_SZ 1
+#define DAT_DELTA_DSR_MSK 0x00000002
+#define DAT_DELTA_DSR_I_MSK 0xfffffffd
+#define DAT_DELTA_DSR_SFT 1
+#define DAT_DELTA_DSR_HI 1
+#define DAT_DELTA_DSR_SZ 1
+#define DAT_TRAILEDGE_RI_MSK 0x00000004
+#define DAT_TRAILEDGE_RI_I_MSK 0xfffffffb
+#define DAT_TRAILEDGE_RI_SFT 2
+#define DAT_TRAILEDGE_RI_HI 2
+#define DAT_TRAILEDGE_RI_SZ 1
+#define DAT_DELTA_CD_MSK 0x00000008
+#define DAT_DELTA_CD_I_MSK 0xfffffff7
+#define DAT_DELTA_CD_SFT 3
+#define DAT_DELTA_CD_HI 3
+#define DAT_DELTA_CD_SZ 1
+#define DAT_CTS_MSK 0x00000010
+#define DAT_CTS_I_MSK 0xffffffef
+#define DAT_CTS_SFT 4
+#define DAT_CTS_HI 4
+#define DAT_CTS_SZ 1
+#define DAT_DSR_MSK 0x00000020
+#define DAT_DSR_I_MSK 0xffffffdf
+#define DAT_DSR_SFT 5
+#define DAT_DSR_HI 5
+#define DAT_DSR_SZ 1
+#define DAT_RI_MSK 0x00000040
+#define DAT_RI_I_MSK 0xffffffbf
+#define DAT_RI_SFT 6
+#define DAT_RI_HI 6
+#define DAT_RI_SZ 1
+#define DAT_CD_MSK 0x00000080
+#define DAT_CD_I_MSK 0xffffff7f
+#define DAT_CD_SFT 7
+#define DAT_CD_HI 7
+#define DAT_CD_SZ 1
+#define DAT_BRDC_DIV_MSK 0x0000ffff
+#define DAT_BRDC_DIV_I_MSK 0xffff0000
+#define DAT_BRDC_DIV_SFT 0
+#define DAT_BRDC_DIV_HI 15
+#define DAT_BRDC_DIV_SZ 16
+#define DAT_RTHR_L_MSK 0x0000000f
+#define DAT_RTHR_L_I_MSK 0xfffffff0
+#define DAT_RTHR_L_SFT 0
+#define DAT_RTHR_L_HI 3
+#define DAT_RTHR_L_SZ 4
+#define DAT_RTHR_H_MSK 0x000000f0
+#define DAT_RTHR_H_I_MSK 0xffffff0f
+#define DAT_RTHR_H_SFT 4
+#define DAT_RTHR_H_HI 7
+#define DAT_RTHR_H_SZ 4
+#define DAT_INT_IDCODE_MSK 0x0000000f
+#define DAT_INT_IDCODE_I_MSK 0xfffffff0
+#define DAT_INT_IDCODE_SFT 0
+#define DAT_INT_IDCODE_HI 3
+#define DAT_INT_IDCODE_SZ 4
+#define DAT_FIFOS_ENABLED_MSK 0x000000c0
+#define DAT_FIFOS_ENABLED_I_MSK 0xffffff3f
+#define DAT_FIFOS_ENABLED_SFT 6
+#define DAT_FIFOS_ENABLED_HI 7
+#define DAT_FIFOS_ENABLED_SZ 2
+#define MASK_TOP_MSK 0xffffffff
+#define MASK_TOP_I_MSK 0x00000000
+#define MASK_TOP_SFT 0
+#define MASK_TOP_HI 31
+#define MASK_TOP_SZ 32
+#define INT_MODE_MSK 0xffffffff
+#define INT_MODE_I_MSK 0x00000000
+#define INT_MODE_SFT 0
+#define INT_MODE_HI 31
+#define INT_MODE_SZ 32
+#define IRQ_PHY_0_MSK 0x00000001
+#define IRQ_PHY_0_I_MSK 0xfffffffe
+#define IRQ_PHY_0_SFT 0
+#define IRQ_PHY_0_HI 0
+#define IRQ_PHY_0_SZ 1
+#define IRQ_PHY_1_MSK 0x00000002
+#define IRQ_PHY_1_I_MSK 0xfffffffd
+#define IRQ_PHY_1_SFT 1
+#define IRQ_PHY_1_HI 1
+#define IRQ_PHY_1_SZ 1
+#define IRQ_SDIO_MSK 0x00000004
+#define IRQ_SDIO_I_MSK 0xfffffffb
+#define IRQ_SDIO_SFT 2
+#define IRQ_SDIO_HI 2
+#define IRQ_SDIO_SZ 1
+#define IRQ_BEACON_DONE_MSK 0x00000008
+#define IRQ_BEACON_DONE_I_MSK 0xfffffff7
+#define IRQ_BEACON_DONE_SFT 3
+#define IRQ_BEACON_DONE_HI 3
+#define IRQ_BEACON_DONE_SZ 1
+#define IRQ_BEACON_MSK 0x00000010
+#define IRQ_BEACON_I_MSK 0xffffffef
+#define IRQ_BEACON_SFT 4
+#define IRQ_BEACON_HI 4
+#define IRQ_BEACON_SZ 1
+#define IRQ_PRE_BEACON_MSK 0x00000020
+#define IRQ_PRE_BEACON_I_MSK 0xffffffdf
+#define IRQ_PRE_BEACON_SFT 5
+#define IRQ_PRE_BEACON_HI 5
+#define IRQ_PRE_BEACON_SZ 1
+#define IRQ_EDCA0_TX_DONE_MSK 0x00000040
+#define IRQ_EDCA0_TX_DONE_I_MSK 0xffffffbf
+#define IRQ_EDCA0_TX_DONE_SFT 6
+#define IRQ_EDCA0_TX_DONE_HI 6
+#define IRQ_EDCA0_TX_DONE_SZ 1
+#define IRQ_EDCA1_TX_DONE_MSK 0x00000080
+#define IRQ_EDCA1_TX_DONE_I_MSK 0xffffff7f
+#define IRQ_EDCA1_TX_DONE_SFT 7
+#define IRQ_EDCA1_TX_DONE_HI 7
+#define IRQ_EDCA1_TX_DONE_SZ 1
+#define IRQ_EDCA2_TX_DONE_MSK 0x00000100
+#define IRQ_EDCA2_TX_DONE_I_MSK 0xfffffeff
+#define IRQ_EDCA2_TX_DONE_SFT 8
+#define IRQ_EDCA2_TX_DONE_HI 8
+#define IRQ_EDCA2_TX_DONE_SZ 1
+#define IRQ_EDCA3_TX_DONE_MSK 0x00000200
+#define IRQ_EDCA3_TX_DONE_I_MSK 0xfffffdff
+#define IRQ_EDCA3_TX_DONE_SFT 9
+#define IRQ_EDCA3_TX_DONE_HI 9
+#define IRQ_EDCA3_TX_DONE_SZ 1
+#define IRQ_EDCA4_TX_DONE_MSK 0x00000400
+#define IRQ_EDCA4_TX_DONE_I_MSK 0xfffffbff
+#define IRQ_EDCA4_TX_DONE_SFT 10
+#define IRQ_EDCA4_TX_DONE_HI 10
+#define IRQ_EDCA4_TX_DONE_SZ 1
+#define IRQ_BEACON_DTIM_MSK 0x00001000
+#define IRQ_BEACON_DTIM_I_MSK 0xffffefff
+#define IRQ_BEACON_DTIM_SFT 12
+#define IRQ_BEACON_DTIM_HI 12
+#define IRQ_BEACON_DTIM_SZ 1
+#define IRQ_EDCA0_LOWTHOLD_INT_MSK 0x00002000
+#define IRQ_EDCA0_LOWTHOLD_INT_I_MSK 0xffffdfff
+#define IRQ_EDCA0_LOWTHOLD_INT_SFT 13
+#define IRQ_EDCA0_LOWTHOLD_INT_HI 13
+#define IRQ_EDCA0_LOWTHOLD_INT_SZ 1
+#define IRQ_EDCA1_LOWTHOLD_INT_MSK 0x00004000
+#define IRQ_EDCA1_LOWTHOLD_INT_I_MSK 0xffffbfff
+#define IRQ_EDCA1_LOWTHOLD_INT_SFT 14
+#define IRQ_EDCA1_LOWTHOLD_INT_HI 14
+#define IRQ_EDCA1_LOWTHOLD_INT_SZ 1
+#define IRQ_EDCA2_LOWTHOLD_INT_MSK 0x00008000
+#define IRQ_EDCA2_LOWTHOLD_INT_I_MSK 0xffff7fff
+#define IRQ_EDCA2_LOWTHOLD_INT_SFT 15
+#define IRQ_EDCA2_LOWTHOLD_INT_HI 15
+#define IRQ_EDCA2_LOWTHOLD_INT_SZ 1
+#define IRQ_EDCA3_LOWTHOLD_INT_MSK 0x00010000
+#define IRQ_EDCA3_LOWTHOLD_INT_I_MSK 0xfffeffff
+#define IRQ_EDCA3_LOWTHOLD_INT_SFT 16
+#define IRQ_EDCA3_LOWTHOLD_INT_HI 16
+#define IRQ_EDCA3_LOWTHOLD_INT_SZ 1
+#define IRQ_FENCE_HIT_INT_MSK 0x00020000
+#define IRQ_FENCE_HIT_INT_I_MSK 0xfffdffff
+#define IRQ_FENCE_HIT_INT_SFT 17
+#define IRQ_FENCE_HIT_INT_HI 17
+#define IRQ_FENCE_HIT_INT_SZ 1
+#define IRQ_ILL_ADDR_INT_MSK 0x00040000
+#define IRQ_ILL_ADDR_INT_I_MSK 0xfffbffff
+#define IRQ_ILL_ADDR_INT_SFT 18
+#define IRQ_ILL_ADDR_INT_HI 18
+#define IRQ_ILL_ADDR_INT_SZ 1
+#define IRQ_MBOX_MSK 0x00080000
+#define IRQ_MBOX_I_MSK 0xfff7ffff
+#define IRQ_MBOX_SFT 19
+#define IRQ_MBOX_HI 19
+#define IRQ_MBOX_SZ 1
+#define IRQ_US_TIMER0_MSK 0x00100000
+#define IRQ_US_TIMER0_I_MSK 0xffefffff
+#define IRQ_US_TIMER0_SFT 20
+#define IRQ_US_TIMER0_HI 20
+#define IRQ_US_TIMER0_SZ 1
+#define IRQ_US_TIMER1_MSK 0x00200000
+#define IRQ_US_TIMER1_I_MSK 0xffdfffff
+#define IRQ_US_TIMER1_SFT 21
+#define IRQ_US_TIMER1_HI 21
+#define IRQ_US_TIMER1_SZ 1
+#define IRQ_US_TIMER2_MSK 0x00400000
+#define IRQ_US_TIMER2_I_MSK 0xffbfffff
+#define IRQ_US_TIMER2_SFT 22
+#define IRQ_US_TIMER2_HI 22
+#define IRQ_US_TIMER2_SZ 1
+#define IRQ_US_TIMER3_MSK 0x00800000
+#define IRQ_US_TIMER3_I_MSK 0xff7fffff
+#define IRQ_US_TIMER3_SFT 23
+#define IRQ_US_TIMER3_HI 23
+#define IRQ_US_TIMER3_SZ 1
+#define IRQ_MS_TIMER0_MSK 0x01000000
+#define IRQ_MS_TIMER0_I_MSK 0xfeffffff
+#define IRQ_MS_TIMER0_SFT 24
+#define IRQ_MS_TIMER0_HI 24
+#define IRQ_MS_TIMER0_SZ 1
+#define IRQ_MS_TIMER1_MSK 0x02000000
+#define IRQ_MS_TIMER1_I_MSK 0xfdffffff
+#define IRQ_MS_TIMER1_SFT 25
+#define IRQ_MS_TIMER1_HI 25
+#define IRQ_MS_TIMER1_SZ 1
+#define IRQ_MS_TIMER2_MSK 0x04000000
+#define IRQ_MS_TIMER2_I_MSK 0xfbffffff
+#define IRQ_MS_TIMER2_SFT 26
+#define IRQ_MS_TIMER2_HI 26
+#define IRQ_MS_TIMER2_SZ 1
+#define IRQ_MS_TIMER3_MSK 0x08000000
+#define IRQ_MS_TIMER3_I_MSK 0xf7ffffff
+#define IRQ_MS_TIMER3_SFT 27
+#define IRQ_MS_TIMER3_HI 27
+#define IRQ_MS_TIMER3_SZ 1
+#define IRQ_TX_LIMIT_INT_MSK 0x10000000
+#define IRQ_TX_LIMIT_INT_I_MSK 0xefffffff
+#define IRQ_TX_LIMIT_INT_SFT 28
+#define IRQ_TX_LIMIT_INT_HI 28
+#define IRQ_TX_LIMIT_INT_SZ 1
+#define IRQ_DMA0_MSK 0x20000000
+#define IRQ_DMA0_I_MSK 0xdfffffff
+#define IRQ_DMA0_SFT 29
+#define IRQ_DMA0_HI 29
+#define IRQ_DMA0_SZ 1
+#define IRQ_CO_DMA_MSK 0x40000000
+#define IRQ_CO_DMA_I_MSK 0xbfffffff
+#define IRQ_CO_DMA_SFT 30
+#define IRQ_CO_DMA_HI 30
+#define IRQ_CO_DMA_SZ 1
+#define IRQ_PERI_GROUP_MSK 0x80000000
+#define IRQ_PERI_GROUP_I_MSK 0x7fffffff
+#define IRQ_PERI_GROUP_SFT 31
+#define IRQ_PERI_GROUP_HI 31
+#define IRQ_PERI_GROUP_SZ 1
+#define FIQ_STATUS_MSK 0xffffffff
+#define FIQ_STATUS_I_MSK 0x00000000
+#define FIQ_STATUS_SFT 0
+#define FIQ_STATUS_HI 31
+#define FIQ_STATUS_SZ 32
+#define IRQ_RAW_MSK 0xffffffff
+#define IRQ_RAW_I_MSK 0x00000000
+#define IRQ_RAW_SFT 0
+#define IRQ_RAW_HI 31
+#define IRQ_RAW_SZ 32
+#define FIQ_RAW_MSK 0xffffffff
+#define FIQ_RAW_I_MSK 0x00000000
+#define FIQ_RAW_SFT 0
+#define FIQ_RAW_HI 31
+#define FIQ_RAW_SZ 32
+#define INT_PERI_MASK_MSK 0xffffffff
+#define INT_PERI_MASK_I_MSK 0x00000000
+#define INT_PERI_MASK_SFT 0
+#define INT_PERI_MASK_HI 31
+#define INT_PERI_MASK_SZ 32
+#define PERI_RTC_MSK 0x00000001
+#define PERI_RTC_I_MSK 0xfffffffe
+#define PERI_RTC_SFT 0
+#define PERI_RTC_HI 0
+#define PERI_RTC_SZ 1
+#define IRQ_UART0_TX_MSK 0x00000002
+#define IRQ_UART0_TX_I_MSK 0xfffffffd
+#define IRQ_UART0_TX_SFT 1
+#define IRQ_UART0_TX_HI 1
+#define IRQ_UART0_TX_SZ 1
+#define IRQ_UART0_RX_MSK 0x00000004
+#define IRQ_UART0_RX_I_MSK 0xfffffffb
+#define IRQ_UART0_RX_SFT 2
+#define IRQ_UART0_RX_HI 2
+#define IRQ_UART0_RX_SZ 1
+#define PERI_GPI_2_MSK 0x00000008
+#define PERI_GPI_2_I_MSK 0xfffffff7
+#define PERI_GPI_2_SFT 3
+#define PERI_GPI_2_HI 3
+#define PERI_GPI_2_SZ 1
+#define IRQ_SPI_IPC_MSK 0x00000010
+#define IRQ_SPI_IPC_I_MSK 0xffffffef
+#define IRQ_SPI_IPC_SFT 4
+#define IRQ_SPI_IPC_HI 4
+#define IRQ_SPI_IPC_SZ 1
+#define PERI_GPI_1_0_MSK 0x00000060
+#define PERI_GPI_1_0_I_MSK 0xffffff9f
+#define PERI_GPI_1_0_SFT 5
+#define PERI_GPI_1_0_HI 6
+#define PERI_GPI_1_0_SZ 2
+#define SCRT_INT_1_MSK 0x00000080
+#define SCRT_INT_1_I_MSK 0xffffff7f
+#define SCRT_INT_1_SFT 7
+#define SCRT_INT_1_HI 7
+#define SCRT_INT_1_SZ 1
+#define MMU_ALC_ERR_MSK 0x00000100
+#define MMU_ALC_ERR_I_MSK 0xfffffeff
+#define MMU_ALC_ERR_SFT 8
+#define MMU_ALC_ERR_HI 8
+#define MMU_ALC_ERR_SZ 1
+#define MMU_RLS_ERR_MSK 0x00000200
+#define MMU_RLS_ERR_I_MSK 0xfffffdff
+#define MMU_RLS_ERR_SFT 9
+#define MMU_RLS_ERR_HI 9
+#define MMU_RLS_ERR_SZ 1
+#define ID_MNG_INT_1_MSK 0x00000400
+#define ID_MNG_INT_1_I_MSK 0xfffffbff
+#define ID_MNG_INT_1_SFT 10
+#define ID_MNG_INT_1_HI 10
+#define ID_MNG_INT_1_SZ 1
+#define MBOX_INT_1_MSK 0x00000800
+#define MBOX_INT_1_I_MSK 0xfffff7ff
+#define MBOX_INT_1_SFT 11
+#define MBOX_INT_1_HI 11
+#define MBOX_INT_1_SZ 1
+#define MBOX_INT_2_MSK 0x00001000
+#define MBOX_INT_2_I_MSK 0xffffefff
+#define MBOX_INT_2_SFT 12
+#define MBOX_INT_2_HI 12
+#define MBOX_INT_2_SZ 1
+#define MBOX_INT_3_MSK 0x00002000
+#define MBOX_INT_3_I_MSK 0xffffdfff
+#define MBOX_INT_3_SFT 13
+#define MBOX_INT_3_HI 13
+#define MBOX_INT_3_SZ 1
+#define HCI_INT_1_MSK 0x00004000
+#define HCI_INT_1_I_MSK 0xffffbfff
+#define HCI_INT_1_SFT 14
+#define HCI_INT_1_HI 14
+#define HCI_INT_1_SZ 1
+#define UART_RX_TIMEOUT_MSK 0x00008000
+#define UART_RX_TIMEOUT_I_MSK 0xffff7fff
+#define UART_RX_TIMEOUT_SFT 15
+#define UART_RX_TIMEOUT_HI 15
+#define UART_RX_TIMEOUT_SZ 1
+#define UART_MULTI_IRQ_MSK 0x00010000
+#define UART_MULTI_IRQ_I_MSK 0xfffeffff
+#define UART_MULTI_IRQ_SFT 16
+#define UART_MULTI_IRQ_HI 16
+#define UART_MULTI_IRQ_SZ 1
+#define ID_MNG_INT_2_MSK 0x00020000
+#define ID_MNG_INT_2_I_MSK 0xfffdffff
+#define ID_MNG_INT_2_SFT 17
+#define ID_MNG_INT_2_HI 17
+#define ID_MNG_INT_2_SZ 1
+#define DMN_NOHIT_INT_MSK 0x00040000
+#define DMN_NOHIT_INT_I_MSK 0xfffbffff
+#define DMN_NOHIT_INT_SFT 18
+#define DMN_NOHIT_INT_HI 18
+#define DMN_NOHIT_INT_SZ 1
+#define ID_THOLD_RX_MSK 0x00080000
+#define ID_THOLD_RX_I_MSK 0xfff7ffff
+#define ID_THOLD_RX_SFT 19
+#define ID_THOLD_RX_HI 19
+#define ID_THOLD_RX_SZ 1
+#define ID_THOLD_TX_MSK 0x00100000
+#define ID_THOLD_TX_I_MSK 0xffefffff
+#define ID_THOLD_TX_SFT 20
+#define ID_THOLD_TX_HI 20
+#define ID_THOLD_TX_SZ 1
+#define ID_DOUBLE_RLS_MSK 0x00200000
+#define ID_DOUBLE_RLS_I_MSK 0xffdfffff
+#define ID_DOUBLE_RLS_SFT 21
+#define ID_DOUBLE_RLS_HI 21
+#define ID_DOUBLE_RLS_SZ 1
+#define RX_ID_LEN_THOLD_MSK 0x00400000
+#define RX_ID_LEN_THOLD_I_MSK 0xffbfffff
+#define RX_ID_LEN_THOLD_SFT 22
+#define RX_ID_LEN_THOLD_HI 22
+#define RX_ID_LEN_THOLD_SZ 1
+#define TX_ID_LEN_THOLD_MSK 0x00800000
+#define TX_ID_LEN_THOLD_I_MSK 0xff7fffff
+#define TX_ID_LEN_THOLD_SFT 23
+#define TX_ID_LEN_THOLD_HI 23
+#define TX_ID_LEN_THOLD_SZ 1
+#define ALL_ID_LEN_THOLD_MSK 0x01000000
+#define ALL_ID_LEN_THOLD_I_MSK 0xfeffffff
+#define ALL_ID_LEN_THOLD_SFT 24
+#define ALL_ID_LEN_THOLD_HI 24
+#define ALL_ID_LEN_THOLD_SZ 1
+#define DMN_MCU_INT_MSK 0x02000000
+#define DMN_MCU_INT_I_MSK 0xfdffffff
+#define DMN_MCU_INT_SFT 25
+#define DMN_MCU_INT_HI 25
+#define DMN_MCU_INT_SZ 1
+#define IRQ_DAT_UART_TX_MSK 0x04000000
+#define IRQ_DAT_UART_TX_I_MSK 0xfbffffff
+#define IRQ_DAT_UART_TX_SFT 26
+#define IRQ_DAT_UART_TX_HI 26
+#define IRQ_DAT_UART_TX_SZ 1
+#define IRQ_DAT_UART_RX_MSK 0x08000000
+#define IRQ_DAT_UART_RX_I_MSK 0xf7ffffff
+#define IRQ_DAT_UART_RX_SFT 27
+#define IRQ_DAT_UART_RX_HI 27
+#define IRQ_DAT_UART_RX_SZ 1
+#define DAT_UART_RX_TIMEOUT_MSK 0x10000000
+#define DAT_UART_RX_TIMEOUT_I_MSK 0xefffffff
+#define DAT_UART_RX_TIMEOUT_SFT 28
+#define DAT_UART_RX_TIMEOUT_HI 28
+#define DAT_UART_RX_TIMEOUT_SZ 1
+#define DAT_UART_MULTI_IRQ_MSK 0x20000000
+#define DAT_UART_MULTI_IRQ_I_MSK 0xdfffffff
+#define DAT_UART_MULTI_IRQ_SFT 29
+#define DAT_UART_MULTI_IRQ_HI 29
+#define DAT_UART_MULTI_IRQ_SZ 1
+#define ALR_ABT_NOCHG_INT_IRQ_MSK 0x40000000
+#define ALR_ABT_NOCHG_INT_IRQ_I_MSK 0xbfffffff
+#define ALR_ABT_NOCHG_INT_IRQ_SFT 30
+#define ALR_ABT_NOCHG_INT_IRQ_HI 30
+#define ALR_ABT_NOCHG_INT_IRQ_SZ 1
+#define TBLNEQ_MNGPKT_INT_IRQ_MSK 0x80000000
+#define TBLNEQ_MNGPKT_INT_IRQ_I_MSK 0x7fffffff
+#define TBLNEQ_MNGPKT_INT_IRQ_SFT 31
+#define TBLNEQ_MNGPKT_INT_IRQ_HI 31
+#define TBLNEQ_MNGPKT_INT_IRQ_SZ 1
+#define INTR_PERI_RAW_MSK 0xffffffff
+#define INTR_PERI_RAW_I_MSK 0x00000000
+#define INTR_PERI_RAW_SFT 0
+#define INTR_PERI_RAW_HI 31
+#define INTR_PERI_RAW_SZ 32
+#define INTR_GPI00_CFG_MSK 0x00000003
+#define INTR_GPI00_CFG_I_MSK 0xfffffffc
+#define INTR_GPI00_CFG_SFT 0
+#define INTR_GPI00_CFG_HI 1
+#define INTR_GPI00_CFG_SZ 2
+#define INTR_GPI01_CFG_MSK 0x0000000c
+#define INTR_GPI01_CFG_I_MSK 0xfffffff3
+#define INTR_GPI01_CFG_SFT 2
+#define INTR_GPI01_CFG_HI 3
+#define INTR_GPI01_CFG_SZ 2
+#define SYS_RST_INT_MSK 0x00000001
+#define SYS_RST_INT_I_MSK 0xfffffffe
+#define SYS_RST_INT_SFT 0
+#define SYS_RST_INT_HI 0
+#define SYS_RST_INT_SZ 1
+#define SPI_IPC_ADDR_MSK 0xffffffff
+#define SPI_IPC_ADDR_I_MSK 0x00000000
+#define SPI_IPC_ADDR_SFT 0
+#define SPI_IPC_ADDR_HI 31
+#define SPI_IPC_ADDR_SZ 32
+#define SD_MASK_TOP_MSK 0xffffffff
+#define SD_MASK_TOP_I_MSK 0x00000000
+#define SD_MASK_TOP_SFT 0
+#define SD_MASK_TOP_HI 31
+#define SD_MASK_TOP_SZ 32
+#define IRQ_PHY_0_SD_MSK 0x00000001
+#define IRQ_PHY_0_SD_I_MSK 0xfffffffe
+#define IRQ_PHY_0_SD_SFT 0
+#define IRQ_PHY_0_SD_HI 0
+#define IRQ_PHY_0_SD_SZ 1
+#define IRQ_PHY_1_SD_MSK 0x00000002
+#define IRQ_PHY_1_SD_I_MSK 0xfffffffd
+#define IRQ_PHY_1_SD_SFT 1
+#define IRQ_PHY_1_SD_HI 1
+#define IRQ_PHY_1_SD_SZ 1
+#define IRQ_SDIO_SD_MSK 0x00000004
+#define IRQ_SDIO_SD_I_MSK 0xfffffffb
+#define IRQ_SDIO_SD_SFT 2
+#define IRQ_SDIO_SD_HI 2
+#define IRQ_SDIO_SD_SZ 1
+#define IRQ_BEACON_DONE_SD_MSK 0x00000008
+#define IRQ_BEACON_DONE_SD_I_MSK 0xfffffff7
+#define IRQ_BEACON_DONE_SD_SFT 3
+#define IRQ_BEACON_DONE_SD_HI 3
+#define IRQ_BEACON_DONE_SD_SZ 1
+#define IRQ_BEACON_SD_MSK 0x00000010
+#define IRQ_BEACON_SD_I_MSK 0xffffffef
+#define IRQ_BEACON_SD_SFT 4
+#define IRQ_BEACON_SD_HI 4
+#define IRQ_BEACON_SD_SZ 1
+#define IRQ_PRE_BEACON_SD_MSK 0x00000020
+#define IRQ_PRE_BEACON_SD_I_MSK 0xffffffdf
+#define IRQ_PRE_BEACON_SD_SFT 5
+#define IRQ_PRE_BEACON_SD_HI 5
+#define IRQ_PRE_BEACON_SD_SZ 1
+#define IRQ_EDCA0_TX_DONE_SD_MSK 0x00000040
+#define IRQ_EDCA0_TX_DONE_SD_I_MSK 0xffffffbf
+#define IRQ_EDCA0_TX_DONE_SD_SFT 6
+#define IRQ_EDCA0_TX_DONE_SD_HI 6
+#define IRQ_EDCA0_TX_DONE_SD_SZ 1
+#define IRQ_EDCA1_TX_DONE_SD_MSK 0x00000080
+#define IRQ_EDCA1_TX_DONE_SD_I_MSK 0xffffff7f
+#define IRQ_EDCA1_TX_DONE_SD_SFT 7
+#define IRQ_EDCA1_TX_DONE_SD_HI 7
+#define IRQ_EDCA1_TX_DONE_SD_SZ 1
+#define IRQ_EDCA2_TX_DONE_SD_MSK 0x00000100
+#define IRQ_EDCA2_TX_DONE_SD_I_MSK 0xfffffeff
+#define IRQ_EDCA2_TX_DONE_SD_SFT 8
+#define IRQ_EDCA2_TX_DONE_SD_HI 8
+#define IRQ_EDCA2_TX_DONE_SD_SZ 1
+#define IRQ_EDCA3_TX_DONE_SD_MSK 0x00000200
+#define IRQ_EDCA3_TX_DONE_SD_I_MSK 0xfffffdff
+#define IRQ_EDCA3_TX_DONE_SD_SFT 9
+#define IRQ_EDCA3_TX_DONE_SD_HI 9
+#define IRQ_EDCA3_TX_DONE_SD_SZ 1
+#define IRQ_EDCA4_TX_DONE_SD_MSK 0x00000400
+#define IRQ_EDCA4_TX_DONE_SD_I_MSK 0xfffffbff
+#define IRQ_EDCA4_TX_DONE_SD_SFT 10
+#define IRQ_EDCA4_TX_DONE_SD_HI 10
+#define IRQ_EDCA4_TX_DONE_SD_SZ 1
+#define IRQ_BEACON_DTIM_SD_MSK 0x00001000
+#define IRQ_BEACON_DTIM_SD_I_MSK 0xffffefff
+#define IRQ_BEACON_DTIM_SD_SFT 12
+#define IRQ_BEACON_DTIM_SD_HI 12
+#define IRQ_BEACON_DTIM_SD_SZ 1
+#define IRQ_EDCA0_LOWTHOLD_INT_SD_MSK 0x00002000
+#define IRQ_EDCA0_LOWTHOLD_INT_SD_I_MSK 0xffffdfff
+#define IRQ_EDCA0_LOWTHOLD_INT_SD_SFT 13
+#define IRQ_EDCA0_LOWTHOLD_INT_SD_HI 13
+#define IRQ_EDCA0_LOWTHOLD_INT_SD_SZ 1
+#define IRQ_EDCA1_LOWTHOLD_INT_SD_MSK 0x00004000
+#define IRQ_EDCA1_LOWTHOLD_INT_SD_I_MSK 0xffffbfff
+#define IRQ_EDCA1_LOWTHOLD_INT_SD_SFT 14
+#define IRQ_EDCA1_LOWTHOLD_INT_SD_HI 14
+#define IRQ_EDCA1_LOWTHOLD_INT_SD_SZ 1
+#define IRQ_EDCA2_LOWTHOLD_INT_SD_MSK 0x00008000
+#define IRQ_EDCA2_LOWTHOLD_INT_SD_I_MSK 0xffff7fff
+#define IRQ_EDCA2_LOWTHOLD_INT_SD_SFT 15
+#define IRQ_EDCA2_LOWTHOLD_INT_SD_HI 15
+#define IRQ_EDCA2_LOWTHOLD_INT_SD_SZ 1
+#define IRQ_EDCA3_LOWTHOLD_INT_SD_MSK 0x00010000
+#define IRQ_EDCA3_LOWTHOLD_INT_SD_I_MSK 0xfffeffff
+#define IRQ_EDCA3_LOWTHOLD_INT_SD_SFT 16
+#define IRQ_EDCA3_LOWTHOLD_INT_SD_HI 16
+#define IRQ_EDCA3_LOWTHOLD_INT_SD_SZ 1
+#define IRQ_FENCE_HIT_INT_SD_MSK 0x00020000
+#define IRQ_FENCE_HIT_INT_SD_I_MSK 0xfffdffff
+#define IRQ_FENCE_HIT_INT_SD_SFT 17
+#define IRQ_FENCE_HIT_INT_SD_HI 17
+#define IRQ_FENCE_HIT_INT_SD_SZ 1
+#define IRQ_ILL_ADDR_INT_SD_MSK 0x00040000
+#define IRQ_ILL_ADDR_INT_SD_I_MSK 0xfffbffff
+#define IRQ_ILL_ADDR_INT_SD_SFT 18
+#define IRQ_ILL_ADDR_INT_SD_HI 18
+#define IRQ_ILL_ADDR_INT_SD_SZ 1
+#define IRQ_MBOX_SD_MSK 0x00080000
+#define IRQ_MBOX_SD_I_MSK 0xfff7ffff
+#define IRQ_MBOX_SD_SFT 19
+#define IRQ_MBOX_SD_HI 19
+#define IRQ_MBOX_SD_SZ 1
+#define IRQ_US_TIMER0_SD_MSK 0x00100000
+#define IRQ_US_TIMER0_SD_I_MSK 0xffefffff
+#define IRQ_US_TIMER0_SD_SFT 20
+#define IRQ_US_TIMER0_SD_HI 20
+#define IRQ_US_TIMER0_SD_SZ 1
+#define IRQ_US_TIMER1_SD_MSK 0x00200000
+#define IRQ_US_TIMER1_SD_I_MSK 0xffdfffff
+#define IRQ_US_TIMER1_SD_SFT 21
+#define IRQ_US_TIMER1_SD_HI 21
+#define IRQ_US_TIMER1_SD_SZ 1
+#define IRQ_US_TIMER2_SD_MSK 0x00400000
+#define IRQ_US_TIMER2_SD_I_MSK 0xffbfffff
+#define IRQ_US_TIMER2_SD_SFT 22
+#define IRQ_US_TIMER2_SD_HI 22
+#define IRQ_US_TIMER2_SD_SZ 1
+#define IRQ_US_TIMER3_SD_MSK 0x00800000
+#define IRQ_US_TIMER3_SD_I_MSK 0xff7fffff
+#define IRQ_US_TIMER3_SD_SFT 23
+#define IRQ_US_TIMER3_SD_HI 23
+#define IRQ_US_TIMER3_SD_SZ 1
+#define IRQ_MS_TIMER0_SD_MSK 0x01000000
+#define IRQ_MS_TIMER0_SD_I_MSK 0xfeffffff
+#define IRQ_MS_TIMER0_SD_SFT 24
+#define IRQ_MS_TIMER0_SD_HI 24
+#define IRQ_MS_TIMER0_SD_SZ 1
+#define IRQ_MS_TIMER1_SD_MSK 0x02000000
+#define IRQ_MS_TIMER1_SD_I_MSK 0xfdffffff
+#define IRQ_MS_TIMER1_SD_SFT 25
+#define IRQ_MS_TIMER1_SD_HI 25
+#define IRQ_MS_TIMER1_SD_SZ 1
+#define IRQ_MS_TIMER2_SD_MSK 0x04000000
+#define IRQ_MS_TIMER2_SD_I_MSK 0xfbffffff
+#define IRQ_MS_TIMER2_SD_SFT 26
+#define IRQ_MS_TIMER2_SD_HI 26
+#define IRQ_MS_TIMER2_SD_SZ 1
+#define IRQ_MS_TIMER3_SD_MSK 0x08000000
+#define IRQ_MS_TIMER3_SD_I_MSK 0xf7ffffff
+#define IRQ_MS_TIMER3_SD_SFT 27
+#define IRQ_MS_TIMER3_SD_HI 27
+#define IRQ_MS_TIMER3_SD_SZ 1
+#define IRQ_TX_LIMIT_INT_SD_MSK 0x10000000
+#define IRQ_TX_LIMIT_INT_SD_I_MSK 0xefffffff
+#define IRQ_TX_LIMIT_INT_SD_SFT 28
+#define IRQ_TX_LIMIT_INT_SD_HI 28
+#define IRQ_TX_LIMIT_INT_SD_SZ 1
+#define IRQ_DMA0_SD_MSK 0x20000000
+#define IRQ_DMA0_SD_I_MSK 0xdfffffff
+#define IRQ_DMA0_SD_SFT 29
+#define IRQ_DMA0_SD_HI 29
+#define IRQ_DMA0_SD_SZ 1
+#define IRQ_CO_DMA_SD_MSK 0x40000000
+#define IRQ_CO_DMA_SD_I_MSK 0xbfffffff
+#define IRQ_CO_DMA_SD_SFT 30
+#define IRQ_CO_DMA_SD_HI 30
+#define IRQ_CO_DMA_SD_SZ 1
+#define IRQ_PERI_GROUP_SD_MSK 0x80000000
+#define IRQ_PERI_GROUP_SD_I_MSK 0x7fffffff
+#define IRQ_PERI_GROUP_SD_SFT 31
+#define IRQ_PERI_GROUP_SD_HI 31
+#define IRQ_PERI_GROUP_SD_SZ 1
+#define INT_PERI_MASK_SD_MSK 0xffffffff
+#define INT_PERI_MASK_SD_I_MSK 0x00000000
+#define INT_PERI_MASK_SD_SFT 0
+#define INT_PERI_MASK_SD_HI 31
+#define INT_PERI_MASK_SD_SZ 32
+#define PERI_RTC_SD_MSK 0x00000001
+#define PERI_RTC_SD_I_MSK 0xfffffffe
+#define PERI_RTC_SD_SFT 0
+#define PERI_RTC_SD_HI 0
+#define PERI_RTC_SD_SZ 1
+#define IRQ_UART0_TX_SD_MSK 0x00000002
+#define IRQ_UART0_TX_SD_I_MSK 0xfffffffd
+#define IRQ_UART0_TX_SD_SFT 1
+#define IRQ_UART0_TX_SD_HI 1
+#define IRQ_UART0_TX_SD_SZ 1
+#define IRQ_UART0_RX_SD_MSK 0x00000004
+#define IRQ_UART0_RX_SD_I_MSK 0xfffffffb
+#define IRQ_UART0_RX_SD_SFT 2
+#define IRQ_UART0_RX_SD_HI 2
+#define IRQ_UART0_RX_SD_SZ 1
+#define PERI_GPI_SD_2_MSK 0x00000008
+#define PERI_GPI_SD_2_I_MSK 0xfffffff7
+#define PERI_GPI_SD_2_SFT 3
+#define PERI_GPI_SD_2_HI 3
+#define PERI_GPI_SD_2_SZ 1
+#define IRQ_SPI_IPC_SD_MSK 0x00000010
+#define IRQ_SPI_IPC_SD_I_MSK 0xffffffef
+#define IRQ_SPI_IPC_SD_SFT 4
+#define IRQ_SPI_IPC_SD_HI 4
+#define IRQ_SPI_IPC_SD_SZ 1
+#define PERI_GPI_SD_1_0_MSK 0x00000060
+#define PERI_GPI_SD_1_0_I_MSK 0xffffff9f
+#define PERI_GPI_SD_1_0_SFT 5
+#define PERI_GPI_SD_1_0_HI 6
+#define PERI_GPI_SD_1_0_SZ 2
+#define SCRT_INT_1_SD_MSK 0x00000080
+#define SCRT_INT_1_SD_I_MSK 0xffffff7f
+#define SCRT_INT_1_SD_SFT 7
+#define SCRT_INT_1_SD_HI 7
+#define SCRT_INT_1_SD_SZ 1
+#define MMU_ALC_ERR_SD_MSK 0x00000100
+#define MMU_ALC_ERR_SD_I_MSK 0xfffffeff
+#define MMU_ALC_ERR_SD_SFT 8
+#define MMU_ALC_ERR_SD_HI 8
+#define MMU_ALC_ERR_SD_SZ 1
+#define MMU_RLS_ERR_SD_MSK 0x00000200
+#define MMU_RLS_ERR_SD_I_MSK 0xfffffdff
+#define MMU_RLS_ERR_SD_SFT 9
+#define MMU_RLS_ERR_SD_HI 9
+#define MMU_RLS_ERR_SD_SZ 1
+#define ID_MNG_INT_1_SD_MSK 0x00000400
+#define ID_MNG_INT_1_SD_I_MSK 0xfffffbff
+#define ID_MNG_INT_1_SD_SFT 10
+#define ID_MNG_INT_1_SD_HI 10
+#define ID_MNG_INT_1_SD_SZ 1
+#define MBOX_INT_1_SD_MSK 0x00000800
+#define MBOX_INT_1_SD_I_MSK 0xfffff7ff
+#define MBOX_INT_1_SD_SFT 11
+#define MBOX_INT_1_SD_HI 11
+#define MBOX_INT_1_SD_SZ 1
+#define MBOX_INT_2_SD_MSK 0x00001000
+#define MBOX_INT_2_SD_I_MSK 0xffffefff
+#define MBOX_INT_2_SD_SFT 12
+#define MBOX_INT_2_SD_HI 12
+#define MBOX_INT_2_SD_SZ 1
+#define MBOX_INT_3_SD_MSK 0x00002000
+#define MBOX_INT_3_SD_I_MSK 0xffffdfff
+#define MBOX_INT_3_SD_SFT 13
+#define MBOX_INT_3_SD_HI 13
+#define MBOX_INT_3_SD_SZ 1
+#define HCI_INT_1_SD_MSK 0x00004000
+#define HCI_INT_1_SD_I_MSK 0xffffbfff
+#define HCI_INT_1_SD_SFT 14
+#define HCI_INT_1_SD_HI 14
+#define HCI_INT_1_SD_SZ 1
+#define UART_RX_TIMEOUT_SD_MSK 0x00008000
+#define UART_RX_TIMEOUT_SD_I_MSK 0xffff7fff
+#define UART_RX_TIMEOUT_SD_SFT 15
+#define UART_RX_TIMEOUT_SD_HI 15
+#define UART_RX_TIMEOUT_SD_SZ 1
+#define UART_MULTI_IRQ_SD_MSK 0x00010000
+#define UART_MULTI_IRQ_SD_I_MSK 0xfffeffff
+#define UART_MULTI_IRQ_SD_SFT 16
+#define UART_MULTI_IRQ_SD_HI 16
+#define UART_MULTI_IRQ_SD_SZ 1
+#define ID_MNG_INT_2_SD_MSK 0x00020000
+#define ID_MNG_INT_2_SD_I_MSK 0xfffdffff
+#define ID_MNG_INT_2_SD_SFT 17
+#define ID_MNG_INT_2_SD_HI 17
+#define ID_MNG_INT_2_SD_SZ 1
+#define DMN_NOHIT_INT_SD_MSK 0x00040000
+#define DMN_NOHIT_INT_SD_I_MSK 0xfffbffff
+#define DMN_NOHIT_INT_SD_SFT 18
+#define DMN_NOHIT_INT_SD_HI 18
+#define DMN_NOHIT_INT_SD_SZ 1
+#define ID_THOLD_RX_SD_MSK 0x00080000
+#define ID_THOLD_RX_SD_I_MSK 0xfff7ffff
+#define ID_THOLD_RX_SD_SFT 19
+#define ID_THOLD_RX_SD_HI 19
+#define ID_THOLD_RX_SD_SZ 1
+#define ID_THOLD_TX_SD_MSK 0x00100000
+#define ID_THOLD_TX_SD_I_MSK 0xffefffff
+#define ID_THOLD_TX_SD_SFT 20
+#define ID_THOLD_TX_SD_HI 20
+#define ID_THOLD_TX_SD_SZ 1
+#define ID_DOUBLE_RLS_SD_MSK 0x00200000
+#define ID_DOUBLE_RLS_SD_I_MSK 0xffdfffff
+#define ID_DOUBLE_RLS_SD_SFT 21
+#define ID_DOUBLE_RLS_SD_HI 21
+#define ID_DOUBLE_RLS_SD_SZ 1
+#define RX_ID_LEN_THOLD_SD_MSK 0x00400000
+#define RX_ID_LEN_THOLD_SD_I_MSK 0xffbfffff
+#define RX_ID_LEN_THOLD_SD_SFT 22
+#define RX_ID_LEN_THOLD_SD_HI 22
+#define RX_ID_LEN_THOLD_SD_SZ 1
+#define TX_ID_LEN_THOLD_SD_MSK 0x00800000
+#define TX_ID_LEN_THOLD_SD_I_MSK 0xff7fffff
+#define TX_ID_LEN_THOLD_SD_SFT 23
+#define TX_ID_LEN_THOLD_SD_HI 23
+#define TX_ID_LEN_THOLD_SD_SZ 1
+#define ALL_ID_LEN_THOLD_SD_MSK 0x01000000
+#define ALL_ID_LEN_THOLD_SD_I_MSK 0xfeffffff
+#define ALL_ID_LEN_THOLD_SD_SFT 24
+#define ALL_ID_LEN_THOLD_SD_HI 24
+#define ALL_ID_LEN_THOLD_SD_SZ 1
+#define DMN_MCU_INT_SD_MSK 0x02000000
+#define DMN_MCU_INT_SD_I_MSK 0xfdffffff
+#define DMN_MCU_INT_SD_SFT 25
+#define DMN_MCU_INT_SD_HI 25
+#define DMN_MCU_INT_SD_SZ 1
+#define IRQ_DAT_UART_TX_SD_MSK 0x04000000
+#define IRQ_DAT_UART_TX_SD_I_MSK 0xfbffffff
+#define IRQ_DAT_UART_TX_SD_SFT 26
+#define IRQ_DAT_UART_TX_SD_HI 26
+#define IRQ_DAT_UART_TX_SD_SZ 1
+#define IRQ_DAT_UART_RX_SD_MSK 0x08000000
+#define IRQ_DAT_UART_RX_SD_I_MSK 0xf7ffffff
+#define IRQ_DAT_UART_RX_SD_SFT 27
+#define IRQ_DAT_UART_RX_SD_HI 27
+#define IRQ_DAT_UART_RX_SD_SZ 1
+#define DAT_UART_RX_TIMEOUT_SD_MSK 0x10000000
+#define DAT_UART_RX_TIMEOUT_SD_I_MSK 0xefffffff
+#define DAT_UART_RX_TIMEOUT_SD_SFT 28
+#define DAT_UART_RX_TIMEOUT_SD_HI 28
+#define DAT_UART_RX_TIMEOUT_SD_SZ 1
+#define DAT_UART_MULTI_IRQ_SD_MSK 0x20000000
+#define DAT_UART_MULTI_IRQ_SD_I_MSK 0xdfffffff
+#define DAT_UART_MULTI_IRQ_SD_SFT 29
+#define DAT_UART_MULTI_IRQ_SD_HI 29
+#define DAT_UART_MULTI_IRQ_SD_SZ 1
+#define ALR_ABT_NOCHG_INT_IRQ_SD_MSK 0x40000000
+#define ALR_ABT_NOCHG_INT_IRQ_SD_I_MSK 0xbfffffff
+#define ALR_ABT_NOCHG_INT_IRQ_SD_SFT 30
+#define ALR_ABT_NOCHG_INT_IRQ_SD_HI 30
+#define ALR_ABT_NOCHG_INT_IRQ_SD_SZ 1
+#define TBLNEQ_MNGPKT_INT_IRQ_SD_MSK 0x80000000
+#define TBLNEQ_MNGPKT_INT_IRQ_SD_I_MSK 0x7fffffff
+#define TBLNEQ_MNGPKT_INT_IRQ_SD_SFT 31
+#define TBLNEQ_MNGPKT_INT_IRQ_SD_HI 31
+#define TBLNEQ_MNGPKT_INT_IRQ_SD_SZ 1
+#define DBG_SPI_MODE_MSK 0xffffffff
+#define DBG_SPI_MODE_I_MSK 0x00000000
+#define DBG_SPI_MODE_SFT 0
+#define DBG_SPI_MODE_HI 31
+#define DBG_SPI_MODE_SZ 32
+#define DBG_RX_QUOTA_MSK 0x0000ffff
+#define DBG_RX_QUOTA_I_MSK 0xffff0000
+#define DBG_RX_QUOTA_SFT 0
+#define DBG_RX_QUOTA_HI 15
+#define DBG_RX_QUOTA_SZ 16
+#define DBG_CONDI_NUM_MSK 0x000000ff
+#define DBG_CONDI_NUM_I_MSK 0xffffff00
+#define DBG_CONDI_NUM_SFT 0
+#define DBG_CONDI_NUM_HI 7
+#define DBG_CONDI_NUM_SZ 8
+#define DBG_HOST_PATH_MSK 0x00000001
+#define DBG_HOST_PATH_I_MSK 0xfffffffe
+#define DBG_HOST_PATH_SFT 0
+#define DBG_HOST_PATH_HI 0
+#define DBG_HOST_PATH_SZ 1
+#define DBG_TX_SEG_MSK 0xffffffff
+#define DBG_TX_SEG_I_MSK 0x00000000
+#define DBG_TX_SEG_SFT 0
+#define DBG_TX_SEG_HI 31
+#define DBG_TX_SEG_SZ 32
+#define DBG_BRST_MODE_MSK 0x00000001
+#define DBG_BRST_MODE_I_MSK 0xfffffffe
+#define DBG_BRST_MODE_SFT 0
+#define DBG_BRST_MODE_HI 0
+#define DBG_BRST_MODE_SZ 1
+#define DBG_CLK_WIDTH_MSK 0x0000ffff
+#define DBG_CLK_WIDTH_I_MSK 0xffff0000
+#define DBG_CLK_WIDTH_SFT 0
+#define DBG_CLK_WIDTH_HI 15
+#define DBG_CLK_WIDTH_SZ 16
+#define DBG_CSN_INTER_MSK 0xffff0000
+#define DBG_CSN_INTER_I_MSK 0x0000ffff
+#define DBG_CSN_INTER_SFT 16
+#define DBG_CSN_INTER_HI 31
+#define DBG_CSN_INTER_SZ 16
+#define DBG_BACK_DLY_MSK 0x0000ffff
+#define DBG_BACK_DLY_I_MSK 0xffff0000
+#define DBG_BACK_DLY_SFT 0
+#define DBG_BACK_DLY_HI 15
+#define DBG_BACK_DLY_SZ 16
+#define DBG_FRONT_DLY_MSK 0xffff0000
+#define DBG_FRONT_DLY_I_MSK 0x0000ffff
+#define DBG_FRONT_DLY_SFT 16
+#define DBG_FRONT_DLY_HI 31
+#define DBG_FRONT_DLY_SZ 16
+#define DBG_RX_FIFO_FAIL_MSK 0x00000002
+#define DBG_RX_FIFO_FAIL_I_MSK 0xfffffffd
+#define DBG_RX_FIFO_FAIL_SFT 1
+#define DBG_RX_FIFO_FAIL_HI 1
+#define DBG_RX_FIFO_FAIL_SZ 1
+#define DBG_RX_HOST_FAIL_MSK 0x00000004
+#define DBG_RX_HOST_FAIL_I_MSK 0xfffffffb
+#define DBG_RX_HOST_FAIL_SFT 2
+#define DBG_RX_HOST_FAIL_HI 2
+#define DBG_RX_HOST_FAIL_SZ 1
+#define DBG_TX_FIFO_FAIL_MSK 0x00000008
+#define DBG_TX_FIFO_FAIL_I_MSK 0xfffffff7
+#define DBG_TX_FIFO_FAIL_SFT 3
+#define DBG_TX_FIFO_FAIL_HI 3
+#define DBG_TX_FIFO_FAIL_SZ 1
+#define DBG_TX_HOST_FAIL_MSK 0x00000010
+#define DBG_TX_HOST_FAIL_I_MSK 0xffffffef
+#define DBG_TX_HOST_FAIL_SFT 4
+#define DBG_TX_HOST_FAIL_HI 4
+#define DBG_TX_HOST_FAIL_SZ 1
+#define DBG_SPI_DOUBLE_ALLOC_MSK 0x00000020
+#define DBG_SPI_DOUBLE_ALLOC_I_MSK 0xffffffdf
+#define DBG_SPI_DOUBLE_ALLOC_SFT 5
+#define DBG_SPI_DOUBLE_ALLOC_HI 5
+#define DBG_SPI_DOUBLE_ALLOC_SZ 1
+#define DBG_SPI_TX_NO_ALLOC_MSK 0x00000040
+#define DBG_SPI_TX_NO_ALLOC_I_MSK 0xffffffbf
+#define DBG_SPI_TX_NO_ALLOC_SFT 6
+#define DBG_SPI_TX_NO_ALLOC_HI 6
+#define DBG_SPI_TX_NO_ALLOC_SZ 1
+#define DBG_RDATA_RDY_MSK 0x00000080
+#define DBG_RDATA_RDY_I_MSK 0xffffff7f
+#define DBG_RDATA_RDY_SFT 7
+#define DBG_RDATA_RDY_HI 7
+#define DBG_RDATA_RDY_SZ 1
+#define DBG_SPI_ALLOC_STATUS_MSK 0x00000100
+#define DBG_SPI_ALLOC_STATUS_I_MSK 0xfffffeff
+#define DBG_SPI_ALLOC_STATUS_SFT 8
+#define DBG_SPI_ALLOC_STATUS_HI 8
+#define DBG_SPI_ALLOC_STATUS_SZ 1
+#define DBG_SPI_DBG_WR_FIFO_FULL_MSK 0x00000200
+#define DBG_SPI_DBG_WR_FIFO_FULL_I_MSK 0xfffffdff
+#define DBG_SPI_DBG_WR_FIFO_FULL_SFT 9
+#define DBG_SPI_DBG_WR_FIFO_FULL_HI 9
+#define DBG_SPI_DBG_WR_FIFO_FULL_SZ 1
+#define DBG_RX_LEN_MSK 0xffff0000
+#define DBG_RX_LEN_I_MSK 0x0000ffff
+#define DBG_RX_LEN_SFT 16
+#define DBG_RX_LEN_HI 31
+#define DBG_RX_LEN_SZ 16
+#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_MSK 0x00000007
+#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_I_MSK 0xfffffff8
+#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_SFT 0
+#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_HI 2
+#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_SZ 3
+#define DBG_SPI_HOST_TX_ALLOC_PKBUF_MSK 0x00000100
+#define DBG_SPI_HOST_TX_ALLOC_PKBUF_I_MSK 0xfffffeff
+#define DBG_SPI_HOST_TX_ALLOC_PKBUF_SFT 8
+#define DBG_SPI_HOST_TX_ALLOC_PKBUF_HI 8
+#define DBG_SPI_HOST_TX_ALLOC_PKBUF_SZ 1
+#define DBG_SPI_TX_ALLOC_SIZE_MSK 0x000000ff
+#define DBG_SPI_TX_ALLOC_SIZE_I_MSK 0xffffff00
+#define DBG_SPI_TX_ALLOC_SIZE_SFT 0
+#define DBG_SPI_TX_ALLOC_SIZE_HI 7
+#define DBG_SPI_TX_ALLOC_SIZE_SZ 8
+#define DBG_RD_DAT_CNT_MSK 0x0000ffff
+#define DBG_RD_DAT_CNT_I_MSK 0xffff0000
+#define DBG_RD_DAT_CNT_SFT 0
+#define DBG_RD_DAT_CNT_HI 15
+#define DBG_RD_DAT_CNT_SZ 16
+#define DBG_RD_STS_CNT_MSK 0xffff0000
+#define DBG_RD_STS_CNT_I_MSK 0x0000ffff
+#define DBG_RD_STS_CNT_SFT 16
+#define DBG_RD_STS_CNT_HI 31
+#define DBG_RD_STS_CNT_SZ 16
+#define DBG_JUDGE_CNT_MSK 0x0000ffff
+#define DBG_JUDGE_CNT_I_MSK 0xffff0000
+#define DBG_JUDGE_CNT_SFT 0
+#define DBG_JUDGE_CNT_HI 15
+#define DBG_JUDGE_CNT_SZ 16
+#define DBG_RD_STS_CNT_CLR_MSK 0x00010000
+#define DBG_RD_STS_CNT_CLR_I_MSK 0xfffeffff
+#define DBG_RD_STS_CNT_CLR_SFT 16
+#define DBG_RD_STS_CNT_CLR_HI 16
+#define DBG_RD_STS_CNT_CLR_SZ 1
+#define DBG_RD_DAT_CNT_CLR_MSK 0x00020000
+#define DBG_RD_DAT_CNT_CLR_I_MSK 0xfffdffff
+#define DBG_RD_DAT_CNT_CLR_SFT 17
+#define DBG_RD_DAT_CNT_CLR_HI 17
+#define DBG_RD_DAT_CNT_CLR_SZ 1
+#define DBG_JUDGE_CNT_CLR_MSK 0x00040000
+#define DBG_JUDGE_CNT_CLR_I_MSK 0xfffbffff
+#define DBG_JUDGE_CNT_CLR_SFT 18
+#define DBG_JUDGE_CNT_CLR_HI 18
+#define DBG_JUDGE_CNT_CLR_SZ 1
+#define DBG_TX_DONE_CNT_MSK 0x0000ffff
+#define DBG_TX_DONE_CNT_I_MSK 0xffff0000
+#define DBG_TX_DONE_CNT_SFT 0
+#define DBG_TX_DONE_CNT_HI 15
+#define DBG_TX_DONE_CNT_SZ 16
+#define DBG_TX_DISCARD_CNT_MSK 0xffff0000
+#define DBG_TX_DISCARD_CNT_I_MSK 0x0000ffff
+#define DBG_TX_DISCARD_CNT_SFT 16
+#define DBG_TX_DISCARD_CNT_HI 31
+#define DBG_TX_DISCARD_CNT_SZ 16
+#define DBG_TX_SET_CNT_MSK 0x0000ffff
+#define DBG_TX_SET_CNT_I_MSK 0xffff0000
+#define DBG_TX_SET_CNT_SFT 0
+#define DBG_TX_SET_CNT_HI 15
+#define DBG_TX_SET_CNT_SZ 16
+#define DBG_TX_DISCARD_CNT_CLR_MSK 0x00010000
+#define DBG_TX_DISCARD_CNT_CLR_I_MSK 0xfffeffff
+#define DBG_TX_DISCARD_CNT_CLR_SFT 16
+#define DBG_TX_DISCARD_CNT_CLR_HI 16
+#define DBG_TX_DISCARD_CNT_CLR_SZ 1
+#define DBG_TX_DONE_CNT_CLR_MSK 0x00020000
+#define DBG_TX_DONE_CNT_CLR_I_MSK 0xfffdffff
+#define DBG_TX_DONE_CNT_CLR_SFT 17
+#define DBG_TX_DONE_CNT_CLR_HI 17
+#define DBG_TX_DONE_CNT_CLR_SZ 1
+#define DBG_TX_SET_CNT_CLR_MSK 0x00040000
+#define DBG_TX_SET_CNT_CLR_I_MSK 0xfffbffff
+#define DBG_TX_SET_CNT_CLR_SFT 18
+#define DBG_TX_SET_CNT_CLR_HI 18
+#define DBG_TX_SET_CNT_CLR_SZ 1
+#define DBG_DAT_MODE_OFF_MSK 0x00080000
+#define DBG_DAT_MODE_OFF_I_MSK 0xfff7ffff
+#define DBG_DAT_MODE_OFF_SFT 19
+#define DBG_DAT_MODE_OFF_HI 19
+#define DBG_DAT_MODE_OFF_SZ 1
+#define DBG_TX_FIFO_RESIDUE_MSK 0x00700000
+#define DBG_TX_FIFO_RESIDUE_I_MSK 0xff8fffff
+#define DBG_TX_FIFO_RESIDUE_SFT 20
+#define DBG_TX_FIFO_RESIDUE_HI 22
+#define DBG_TX_FIFO_RESIDUE_SZ 3
+#define DBG_RX_FIFO_RESIDUE_MSK 0x07000000
+#define DBG_RX_FIFO_RESIDUE_I_MSK 0xf8ffffff
+#define DBG_RX_FIFO_RESIDUE_SFT 24
+#define DBG_RX_FIFO_RESIDUE_HI 26
+#define DBG_RX_FIFO_RESIDUE_SZ 3
+#define DBG_RX_RDY_MSK 0x00000001
+#define DBG_RX_RDY_I_MSK 0xfffffffe
+#define DBG_RX_RDY_SFT 0
+#define DBG_RX_RDY_HI 0
+#define DBG_RX_RDY_SZ 1
+#define DBG_SDIO_SYS_INT_MSK 0x00000004
+#define DBG_SDIO_SYS_INT_I_MSK 0xfffffffb
+#define DBG_SDIO_SYS_INT_SFT 2
+#define DBG_SDIO_SYS_INT_HI 2
+#define DBG_SDIO_SYS_INT_SZ 1
+#define DBG_EDCA0_LOWTHOLD_INT_MSK 0x00000008
+#define DBG_EDCA0_LOWTHOLD_INT_I_MSK 0xfffffff7
+#define DBG_EDCA0_LOWTHOLD_INT_SFT 3
+#define DBG_EDCA0_LOWTHOLD_INT_HI 3
+#define DBG_EDCA0_LOWTHOLD_INT_SZ 1
+#define DBG_EDCA1_LOWTHOLD_INT_MSK 0x00000010
+#define DBG_EDCA1_LOWTHOLD_INT_I_MSK 0xffffffef
+#define DBG_EDCA1_LOWTHOLD_INT_SFT 4
+#define DBG_EDCA1_LOWTHOLD_INT_HI 4
+#define DBG_EDCA1_LOWTHOLD_INT_SZ 1
+#define DBG_EDCA2_LOWTHOLD_INT_MSK 0x00000020
+#define DBG_EDCA2_LOWTHOLD_INT_I_MSK 0xffffffdf
+#define DBG_EDCA2_LOWTHOLD_INT_SFT 5
+#define DBG_EDCA2_LOWTHOLD_INT_HI 5
+#define DBG_EDCA2_LOWTHOLD_INT_SZ 1
+#define DBG_EDCA3_LOWTHOLD_INT_MSK 0x00000040
+#define DBG_EDCA3_LOWTHOLD_INT_I_MSK 0xffffffbf
+#define DBG_EDCA3_LOWTHOLD_INT_SFT 6
+#define DBG_EDCA3_LOWTHOLD_INT_HI 6
+#define DBG_EDCA3_LOWTHOLD_INT_SZ 1
+#define DBG_TX_LIMIT_INT_IN_MSK 0x00000080
+#define DBG_TX_LIMIT_INT_IN_I_MSK 0xffffff7f
+#define DBG_TX_LIMIT_INT_IN_SFT 7
+#define DBG_TX_LIMIT_INT_IN_HI 7
+#define DBG_TX_LIMIT_INT_IN_SZ 1
+#define DBG_SPI_FN1_MSK 0x00007f00
+#define DBG_SPI_FN1_I_MSK 0xffff80ff
+#define DBG_SPI_FN1_SFT 8
+#define DBG_SPI_FN1_HI 14
+#define DBG_SPI_FN1_SZ 7
+#define DBG_SPI_CLK_EN_INT_MSK 0x00008000
+#define DBG_SPI_CLK_EN_INT_I_MSK 0xffff7fff
+#define DBG_SPI_CLK_EN_INT_SFT 15
+#define DBG_SPI_CLK_EN_INT_HI 15
+#define DBG_SPI_CLK_EN_INT_SZ 1
+#define DBG_SPI_HOST_MASK_MSK 0x00ff0000
+#define DBG_SPI_HOST_MASK_I_MSK 0xff00ffff
+#define DBG_SPI_HOST_MASK_SFT 16
+#define DBG_SPI_HOST_MASK_HI 23
+#define DBG_SPI_HOST_MASK_SZ 8
+#define BOOT_ADDR_MSK 0x00ffffff
+#define BOOT_ADDR_I_MSK 0xff000000
+#define BOOT_ADDR_SFT 0
+#define BOOT_ADDR_HI 23
+#define BOOT_ADDR_SZ 24
+#define CHECK_SUM_FAIL_MSK 0x80000000
+#define CHECK_SUM_FAIL_I_MSK 0x7fffffff
+#define CHECK_SUM_FAIL_SFT 31
+#define CHECK_SUM_FAIL_HI 31
+#define CHECK_SUM_FAIL_SZ 1
+#define VERIFY_DATA_MSK 0xffffffff
+#define VERIFY_DATA_I_MSK 0x00000000
+#define VERIFY_DATA_SFT 0
+#define VERIFY_DATA_HI 31
+#define VERIFY_DATA_SZ 32
+#define FLASH_ADDR_MSK 0x00ffffff
+#define FLASH_ADDR_I_MSK 0xff000000
+#define FLASH_ADDR_SFT 0
+#define FLASH_ADDR_HI 23
+#define FLASH_ADDR_SZ 24
+#define FLASH_CMD_CLR_MSK 0x10000000
+#define FLASH_CMD_CLR_I_MSK 0xefffffff
+#define FLASH_CMD_CLR_SFT 28
+#define FLASH_CMD_CLR_HI 28
+#define FLASH_CMD_CLR_SZ 1
+#define FLASH_DMA_CLR_MSK 0x20000000
+#define FLASH_DMA_CLR_I_MSK 0xdfffffff
+#define FLASH_DMA_CLR_SFT 29
+#define FLASH_DMA_CLR_HI 29
+#define FLASH_DMA_CLR_SZ 1
+#define DMA_EN_MSK 0x40000000
+#define DMA_EN_I_MSK 0xbfffffff
+#define DMA_EN_SFT 30
+#define DMA_EN_HI 30
+#define DMA_EN_SZ 1
+#define DMA_BUSY_MSK 0x80000000
+#define DMA_BUSY_I_MSK 0x7fffffff
+#define DMA_BUSY_SFT 31
+#define DMA_BUSY_HI 31
+#define DMA_BUSY_SZ 1
+#define SRAM_ADDR_MSK 0xffffffff
+#define SRAM_ADDR_I_MSK 0x00000000
+#define SRAM_ADDR_SFT 0
+#define SRAM_ADDR_HI 31
+#define SRAM_ADDR_SZ 32
+#define FLASH_DMA_LEN_MSK 0xffffffff
+#define FLASH_DMA_LEN_I_MSK 0x00000000
+#define FLASH_DMA_LEN_SFT 0
+#define FLASH_DMA_LEN_HI 31
+#define FLASH_DMA_LEN_SZ 32
+#define FLASH_FRONT_DLY_MSK 0x0000ffff
+#define FLASH_FRONT_DLY_I_MSK 0xffff0000
+#define FLASH_FRONT_DLY_SFT 0
+#define FLASH_FRONT_DLY_HI 15
+#define FLASH_FRONT_DLY_SZ 16
+#define FLASH_BACK_DLY_MSK 0xffff0000
+#define FLASH_BACK_DLY_I_MSK 0x0000ffff
+#define FLASH_BACK_DLY_SFT 16
+#define FLASH_BACK_DLY_HI 31
+#define FLASH_BACK_DLY_SZ 16
+#define FLASH_CLK_WIDTH_MSK 0x0000ffff
+#define FLASH_CLK_WIDTH_I_MSK 0xffff0000
+#define FLASH_CLK_WIDTH_SFT 0
+#define FLASH_CLK_WIDTH_HI 15
+#define FLASH_CLK_WIDTH_SZ 16
+#define SPI_BUSY_MSK 0x00010000
+#define SPI_BUSY_I_MSK 0xfffeffff
+#define SPI_BUSY_SFT 16
+#define SPI_BUSY_HI 16
+#define SPI_BUSY_SZ 1
+#define FLS_REMAP_MSK 0x00020000
+#define FLS_REMAP_I_MSK 0xfffdffff
+#define FLS_REMAP_SFT 17
+#define FLS_REMAP_HI 17
+#define FLS_REMAP_SZ 1
+#define PBUS_SWP_MSK 0x00040000
+#define PBUS_SWP_I_MSK 0xfffbffff
+#define PBUS_SWP_SFT 18
+#define PBUS_SWP_HI 18
+#define PBUS_SWP_SZ 1
+#define BIT_MODE1_MSK 0x00080000
+#define BIT_MODE1_I_MSK 0xfff7ffff
+#define BIT_MODE1_SFT 19
+#define BIT_MODE1_HI 19
+#define BIT_MODE1_SZ 1
+#define BIT_MODE2_MSK 0x00100000
+#define BIT_MODE2_I_MSK 0xffefffff
+#define BIT_MODE2_SFT 20
+#define BIT_MODE2_HI 20
+#define BIT_MODE2_SZ 1
+#define BIT_MODE4_MSK 0x00200000
+#define BIT_MODE4_I_MSK 0xffdfffff
+#define BIT_MODE4_SFT 21
+#define BIT_MODE4_HI 21
+#define BIT_MODE4_SZ 1
+#define BOOT_CHECK_SUM_MSK 0xffffffff
+#define BOOT_CHECK_SUM_I_MSK 0x00000000
+#define BOOT_CHECK_SUM_SFT 0
+#define BOOT_CHECK_SUM_HI 31
+#define BOOT_CHECK_SUM_SZ 32
+#define CHECK_SUM_TAG_MSK 0xffffffff
+#define CHECK_SUM_TAG_I_MSK 0x00000000
+#define CHECK_SUM_TAG_SFT 0
+#define CHECK_SUM_TAG_HI 31
+#define CHECK_SUM_TAG_SZ 32
+#define CMD_LEN_MSK 0x0000ffff
+#define CMD_LEN_I_MSK 0xffff0000
+#define CMD_LEN_SFT 0
+#define CMD_LEN_HI 15
+#define CMD_LEN_SZ 16
+#define CMD_ADDR_MSK 0xffffffff
+#define CMD_ADDR_I_MSK 0x00000000
+#define CMD_ADDR_SFT 0
+#define CMD_ADDR_HI 31
+#define CMD_ADDR_SZ 32
+#define DMA_ADR_SRC_MSK 0xffffffff
+#define DMA_ADR_SRC_I_MSK 0x00000000
+#define DMA_ADR_SRC_SFT 0
+#define DMA_ADR_SRC_HI 31
+#define DMA_ADR_SRC_SZ 32
+#define DMA_ADR_DST_MSK 0xffffffff
+#define DMA_ADR_DST_I_MSK 0x00000000
+#define DMA_ADR_DST_SFT 0
+#define DMA_ADR_DST_HI 31
+#define DMA_ADR_DST_SZ 32
+#define DMA_SRC_SIZE_MSK 0x00000007
+#define DMA_SRC_SIZE_I_MSK 0xfffffff8
+#define DMA_SRC_SIZE_SFT 0
+#define DMA_SRC_SIZE_HI 2
+#define DMA_SRC_SIZE_SZ 3
+#define DMA_SRC_INC_MSK 0x00000008
+#define DMA_SRC_INC_I_MSK 0xfffffff7
+#define DMA_SRC_INC_SFT 3
+#define DMA_SRC_INC_HI 3
+#define DMA_SRC_INC_SZ 1
+#define DMA_DST_SIZE_MSK 0x00000070
+#define DMA_DST_SIZE_I_MSK 0xffffff8f
+#define DMA_DST_SIZE_SFT 4
+#define DMA_DST_SIZE_HI 6
+#define DMA_DST_SIZE_SZ 3
+#define DMA_DST_INC_MSK 0x00000080
+#define DMA_DST_INC_I_MSK 0xffffff7f
+#define DMA_DST_INC_SFT 7
+#define DMA_DST_INC_HI 7
+#define DMA_DST_INC_SZ 1
+#define DMA_FAST_FILL_MSK 0x00000100
+#define DMA_FAST_FILL_I_MSK 0xfffffeff
+#define DMA_FAST_FILL_SFT 8
+#define DMA_FAST_FILL_HI 8
+#define DMA_FAST_FILL_SZ 1
+#define DMA_SDIO_KICK_MSK 0x00001000
+#define DMA_SDIO_KICK_I_MSK 0xffffefff
+#define DMA_SDIO_KICK_SFT 12
+#define DMA_SDIO_KICK_HI 12
+#define DMA_SDIO_KICK_SZ 1
+#define DMA_BADR_EN_MSK 0x00002000
+#define DMA_BADR_EN_I_MSK 0xffffdfff
+#define DMA_BADR_EN_SFT 13
+#define DMA_BADR_EN_HI 13
+#define DMA_BADR_EN_SZ 1
+#define DMA_LEN_MSK 0xffff0000
+#define DMA_LEN_I_MSK 0x0000ffff
+#define DMA_LEN_SFT 16
+#define DMA_LEN_HI 31
+#define DMA_LEN_SZ 16
+#define DMA_INT_MASK_MSK 0x00000001
+#define DMA_INT_MASK_I_MSK 0xfffffffe
+#define DMA_INT_MASK_SFT 0
+#define DMA_INT_MASK_HI 0
+#define DMA_INT_MASK_SZ 1
+#define DMA_STS_MSK 0x00000100
+#define DMA_STS_I_MSK 0xfffffeff
+#define DMA_STS_SFT 8
+#define DMA_STS_HI 8
+#define DMA_STS_SZ 1
+#define DMA_FINISH_MSK 0x80000000
+#define DMA_FINISH_I_MSK 0x7fffffff
+#define DMA_FINISH_SFT 31
+#define DMA_FINISH_HI 31
+#define DMA_FINISH_SZ 1
+#define DMA_CONST_MSK 0xffffffff
+#define DMA_CONST_I_MSK 0x00000000
+#define DMA_CONST_SFT 0
+#define DMA_CONST_HI 31
+#define DMA_CONST_SZ 32
+#define SLEEP_WAKE_CNT_MSK 0x00ffffff
+#define SLEEP_WAKE_CNT_I_MSK 0xff000000
+#define SLEEP_WAKE_CNT_SFT 0
+#define SLEEP_WAKE_CNT_HI 23
+#define SLEEP_WAKE_CNT_SZ 24
+#define RG_DLDO_LEVEL_MSK 0x07000000
+#define RG_DLDO_LEVEL_I_MSK 0xf8ffffff
+#define RG_DLDO_LEVEL_SFT 24
+#define RG_DLDO_LEVEL_HI 26
+#define RG_DLDO_LEVEL_SZ 3
+#define RG_DLDO_BOOST_IQ_MSK 0x08000000
+#define RG_DLDO_BOOST_IQ_I_MSK 0xf7ffffff
+#define RG_DLDO_BOOST_IQ_SFT 27
+#define RG_DLDO_BOOST_IQ_HI 27
+#define RG_DLDO_BOOST_IQ_SZ 1
+#define RG_BUCK_LEVEL_MSK 0x70000000
+#define RG_BUCK_LEVEL_I_MSK 0x8fffffff
+#define RG_BUCK_LEVEL_SFT 28
+#define RG_BUCK_LEVEL_HI 30
+#define RG_BUCK_LEVEL_SZ 3
+#define RG_BUCK_VREF_SEL_MSK 0x80000000
+#define RG_BUCK_VREF_SEL_I_MSK 0x7fffffff
+#define RG_BUCK_VREF_SEL_SFT 31
+#define RG_BUCK_VREF_SEL_HI 31
+#define RG_BUCK_VREF_SEL_SZ 1
+#define RG_RTC_OSC_RES_SW_MANUAL_MSK 0x000003ff
+#define RG_RTC_OSC_RES_SW_MANUAL_I_MSK 0xfffffc00
+#define RG_RTC_OSC_RES_SW_MANUAL_SFT 0
+#define RG_RTC_OSC_RES_SW_MANUAL_HI 9
+#define RG_RTC_OSC_RES_SW_MANUAL_SZ 10
+#define RG_RTC_OSC_RES_SW_MSK 0x03ff0000
+#define RG_RTC_OSC_RES_SW_I_MSK 0xfc00ffff
+#define RG_RTC_OSC_RES_SW_SFT 16
+#define RG_RTC_OSC_RES_SW_HI 25
+#define RG_RTC_OSC_RES_SW_SZ 10
+#define RTC_OSC_CAL_RES_RDY_MSK 0x80000000
+#define RTC_OSC_CAL_RES_RDY_I_MSK 0x7fffffff
+#define RTC_OSC_CAL_RES_RDY_SFT 31
+#define RTC_OSC_CAL_RES_RDY_HI 31
+#define RTC_OSC_CAL_RES_RDY_SZ 1
+#define RG_DCDC_MODE_MSK 0x00000001
+#define RG_DCDC_MODE_I_MSK 0xfffffffe
+#define RG_DCDC_MODE_SFT 0
+#define RG_DCDC_MODE_HI 0
+#define RG_DCDC_MODE_SZ 1
+#define RG_BUCK_EN_PSM_MSK 0x00000010
+#define RG_BUCK_EN_PSM_I_MSK 0xffffffef
+#define RG_BUCK_EN_PSM_SFT 4
+#define RG_BUCK_EN_PSM_HI 4
+#define RG_BUCK_EN_PSM_SZ 1
+#define RG_BUCK_PSM_VTH_MSK 0x00000100
+#define RG_BUCK_PSM_VTH_I_MSK 0xfffffeff
+#define RG_BUCK_PSM_VTH_SFT 8
+#define RG_BUCK_PSM_VTH_HI 8
+#define RG_BUCK_PSM_VTH_SZ 1
+#define RG_RTC_OSC_RES_SW_MANUAL_EN_MSK 0x00001000
+#define RG_RTC_OSC_RES_SW_MANUAL_EN_I_MSK 0xffffefff
+#define RG_RTC_OSC_RES_SW_MANUAL_EN_SFT 12
+#define RG_RTC_OSC_RES_SW_MANUAL_EN_HI 12
+#define RG_RTC_OSC_RES_SW_MANUAL_EN_SZ 1
+#define RG_RTC_RDY_DEGLITCH_TIMER_MSK 0x00006000
+#define RG_RTC_RDY_DEGLITCH_TIMER_I_MSK 0xffff9fff
+#define RG_RTC_RDY_DEGLITCH_TIMER_SFT 13
+#define RG_RTC_RDY_DEGLITCH_TIMER_HI 14
+#define RG_RTC_RDY_DEGLITCH_TIMER_SZ 2
+#define RTC_CAL_ENA_MSK 0x00010000
+#define RTC_CAL_ENA_I_MSK 0xfffeffff
+#define RTC_CAL_ENA_SFT 16
+#define RTC_CAL_ENA_HI 16
+#define RTC_CAL_ENA_SZ 1
+#define PMU_WAKE_TRIG_EVENT_MSK 0x00000003
+#define PMU_WAKE_TRIG_EVENT_I_MSK 0xfffffffc
+#define PMU_WAKE_TRIG_EVENT_SFT 0
+#define PMU_WAKE_TRIG_EVENT_HI 1
+#define PMU_WAKE_TRIG_EVENT_SZ 2
+#define DIGI_TOP_POR_MASK_MSK 0x00000010
+#define DIGI_TOP_POR_MASK_I_MSK 0xffffffef
+#define DIGI_TOP_POR_MASK_SFT 4
+#define DIGI_TOP_POR_MASK_HI 4
+#define DIGI_TOP_POR_MASK_SZ 1
+#define PMU_ENTER_SLEEP_MODE_MSK 0x00000100
+#define PMU_ENTER_SLEEP_MODE_I_MSK 0xfffffeff
+#define PMU_ENTER_SLEEP_MODE_SFT 8
+#define PMU_ENTER_SLEEP_MODE_HI 8
+#define PMU_ENTER_SLEEP_MODE_SZ 1
+#define RG_RTC_DUMMIES_MSK 0xffff0000
+#define RG_RTC_DUMMIES_I_MSK 0x0000ffff
+#define RG_RTC_DUMMIES_SFT 16
+#define RG_RTC_DUMMIES_HI 31
+#define RG_RTC_DUMMIES_SZ 16
+#define RTC_EN_MSK 0x00000001
+#define RTC_EN_I_MSK 0xfffffffe
+#define RTC_EN_SFT 0
+#define RTC_EN_HI 0
+#define RTC_EN_SZ 1
+#define RTC_SRC_MSK 0x00000002
+#define RTC_SRC_I_MSK 0xfffffffd
+#define RTC_SRC_SFT 1
+#define RTC_SRC_HI 1
+#define RTC_SRC_SZ 1
+#define RTC_TICK_CNT_MSK 0x7fff0000
+#define RTC_TICK_CNT_I_MSK 0x8000ffff
+#define RTC_TICK_CNT_SFT 16
+#define RTC_TICK_CNT_HI 30
+#define RTC_TICK_CNT_SZ 15
+#define RTC_INT_SEC_MASK_MSK 0x00000001
+#define RTC_INT_SEC_MASK_I_MSK 0xfffffffe
+#define RTC_INT_SEC_MASK_SFT 0
+#define RTC_INT_SEC_MASK_HI 0
+#define RTC_INT_SEC_MASK_SZ 1
+#define RTC_INT_ALARM_MASK_MSK 0x00000002
+#define RTC_INT_ALARM_MASK_I_MSK 0xfffffffd
+#define RTC_INT_ALARM_MASK_SFT 1
+#define RTC_INT_ALARM_MASK_HI 1
+#define RTC_INT_ALARM_MASK_SZ 1
+#define RTC_INT_SEC_MSK 0x00010000
+#define RTC_INT_SEC_I_MSK 0xfffeffff
+#define RTC_INT_SEC_SFT 16
+#define RTC_INT_SEC_HI 16
+#define RTC_INT_SEC_SZ 1
+#define RTC_INT_ALARM_MSK 0x00020000
+#define RTC_INT_ALARM_I_MSK 0xfffdffff
+#define RTC_INT_ALARM_SFT 17
+#define RTC_INT_ALARM_HI 17
+#define RTC_INT_ALARM_SZ 1
+#define RTC_SEC_START_CNT_MSK 0xffffffff
+#define RTC_SEC_START_CNT_I_MSK 0x00000000
+#define RTC_SEC_START_CNT_SFT 0
+#define RTC_SEC_START_CNT_HI 31
+#define RTC_SEC_START_CNT_SZ 32
+#define RTC_SEC_CNT_MSK 0xffffffff
+#define RTC_SEC_CNT_I_MSK 0x00000000
+#define RTC_SEC_CNT_SFT 0
+#define RTC_SEC_CNT_HI 31
+#define RTC_SEC_CNT_SZ 32
+#define RTC_SEC_ALARM_VALUE_MSK 0xffffffff
+#define RTC_SEC_ALARM_VALUE_I_MSK 0x00000000
+#define RTC_SEC_ALARM_VALUE_SFT 0
+#define RTC_SEC_ALARM_VALUE_HI 31
+#define RTC_SEC_ALARM_VALUE_SZ 32
+#define D2_DMA_ADR_SRC_MSK 0xffffffff
+#define D2_DMA_ADR_SRC_I_MSK 0x00000000
+#define D2_DMA_ADR_SRC_SFT 0
+#define D2_DMA_ADR_SRC_HI 31
+#define D2_DMA_ADR_SRC_SZ 32
+#define D2_DMA_ADR_DST_MSK 0xffffffff
+#define D2_DMA_ADR_DST_I_MSK 0x00000000
+#define D2_DMA_ADR_DST_SFT 0
+#define D2_DMA_ADR_DST_HI 31
+#define D2_DMA_ADR_DST_SZ 32
+#define D2_DMA_SRC_SIZE_MSK 0x00000007
+#define D2_DMA_SRC_SIZE_I_MSK 0xfffffff8
+#define D2_DMA_SRC_SIZE_SFT 0
+#define D2_DMA_SRC_SIZE_HI 2
+#define D2_DMA_SRC_SIZE_SZ 3
+#define D2_DMA_SRC_INC_MSK 0x00000008
+#define D2_DMA_SRC_INC_I_MSK 0xfffffff7
+#define D2_DMA_SRC_INC_SFT 3
+#define D2_DMA_SRC_INC_HI 3
+#define D2_DMA_SRC_INC_SZ 1
+#define D2_DMA_DST_SIZE_MSK 0x00000070
+#define D2_DMA_DST_SIZE_I_MSK 0xffffff8f
+#define D2_DMA_DST_SIZE_SFT 4
+#define D2_DMA_DST_SIZE_HI 6
+#define D2_DMA_DST_SIZE_SZ 3
+#define D2_DMA_DST_INC_MSK 0x00000080
+#define D2_DMA_DST_INC_I_MSK 0xffffff7f
+#define D2_DMA_DST_INC_SFT 7
+#define D2_DMA_DST_INC_HI 7
+#define D2_DMA_DST_INC_SZ 1
+#define D2_DMA_FAST_FILL_MSK 0x00000100
+#define D2_DMA_FAST_FILL_I_MSK 0xfffffeff
+#define D2_DMA_FAST_FILL_SFT 8
+#define D2_DMA_FAST_FILL_HI 8
+#define D2_DMA_FAST_FILL_SZ 1
+#define D2_DMA_SDIO_KICK_MSK 0x00001000
+#define D2_DMA_SDIO_KICK_I_MSK 0xffffefff
+#define D2_DMA_SDIO_KICK_SFT 12
+#define D2_DMA_SDIO_KICK_HI 12
+#define D2_DMA_SDIO_KICK_SZ 1
+#define D2_DMA_BADR_EN_MSK 0x00002000
+#define D2_DMA_BADR_EN_I_MSK 0xffffdfff
+#define D2_DMA_BADR_EN_SFT 13
+#define D2_DMA_BADR_EN_HI 13
+#define D2_DMA_BADR_EN_SZ 1
+#define D2_DMA_LEN_MSK 0xffff0000
+#define D2_DMA_LEN_I_MSK 0x0000ffff
+#define D2_DMA_LEN_SFT 16
+#define D2_DMA_LEN_HI 31
+#define D2_DMA_LEN_SZ 16
+#define D2_DMA_INT_MASK_MSK 0x00000001
+#define D2_DMA_INT_MASK_I_MSK 0xfffffffe
+#define D2_DMA_INT_MASK_SFT 0
+#define D2_DMA_INT_MASK_HI 0
+#define D2_DMA_INT_MASK_SZ 1
+#define D2_DMA_STS_MSK 0x00000100
+#define D2_DMA_STS_I_MSK 0xfffffeff
+#define D2_DMA_STS_SFT 8
+#define D2_DMA_STS_HI 8
+#define D2_DMA_STS_SZ 1
+#define D2_DMA_FINISH_MSK 0x80000000
+#define D2_DMA_FINISH_I_MSK 0x7fffffff
+#define D2_DMA_FINISH_SFT 31
+#define D2_DMA_FINISH_HI 31
+#define D2_DMA_FINISH_SZ 1
+#define D2_DMA_CONST_MSK 0xffffffff
+#define D2_DMA_CONST_I_MSK 0x00000000
+#define D2_DMA_CONST_SFT 0
+#define D2_DMA_CONST_HI 31
+#define D2_DMA_CONST_SZ 32
+#define TRAP_UNKNOWN_TYPE_MSK 0x00000001
+#define TRAP_UNKNOWN_TYPE_I_MSK 0xfffffffe
+#define TRAP_UNKNOWN_TYPE_SFT 0
+#define TRAP_UNKNOWN_TYPE_HI 0
+#define TRAP_UNKNOWN_TYPE_SZ 1
+#define TX_ON_DEMAND_ENA_MSK 0x00000002
+#define TX_ON_DEMAND_ENA_I_MSK 0xfffffffd
+#define TX_ON_DEMAND_ENA_SFT 1
+#define TX_ON_DEMAND_ENA_HI 1
+#define TX_ON_DEMAND_ENA_SZ 1
+#define RX_2_HOST_MSK 0x00000004
+#define RX_2_HOST_I_MSK 0xfffffffb
+#define RX_2_HOST_SFT 2
+#define RX_2_HOST_HI 2
+#define RX_2_HOST_SZ 1
+#define AUTO_SEQNO_MSK 0x00000008
+#define AUTO_SEQNO_I_MSK 0xfffffff7
+#define AUTO_SEQNO_SFT 3
+#define AUTO_SEQNO_HI 3
+#define AUTO_SEQNO_SZ 1
+#define BYPASSS_TX_PARSER_ENCAP_MSK 0x00000010
+#define BYPASSS_TX_PARSER_ENCAP_I_MSK 0xffffffef
+#define BYPASSS_TX_PARSER_ENCAP_SFT 4
+#define BYPASSS_TX_PARSER_ENCAP_HI 4
+#define BYPASSS_TX_PARSER_ENCAP_SZ 1
+#define HDR_STRIP_MSK 0x00000020
+#define HDR_STRIP_I_MSK 0xffffffdf
+#define HDR_STRIP_SFT 5
+#define HDR_STRIP_HI 5
+#define HDR_STRIP_SZ 1
+#define ERP_PROTECT_MSK 0x000000c0
+#define ERP_PROTECT_I_MSK 0xffffff3f
+#define ERP_PROTECT_SFT 6
+#define ERP_PROTECT_HI 7
+#define ERP_PROTECT_SZ 2
+#define PRO_VER_MSK 0x00000300
+#define PRO_VER_I_MSK 0xfffffcff
+#define PRO_VER_SFT 8
+#define PRO_VER_HI 9
+#define PRO_VER_SZ 2
+#define TXQ_ID0_MSK 0x00007000
+#define TXQ_ID0_I_MSK 0xffff8fff
+#define TXQ_ID0_SFT 12
+#define TXQ_ID0_HI 14
+#define TXQ_ID0_SZ 3
+#define TXQ_ID1_MSK 0x00070000
+#define TXQ_ID1_I_MSK 0xfff8ffff
+#define TXQ_ID1_SFT 16
+#define TXQ_ID1_HI 18
+#define TXQ_ID1_SZ 3
+#define TX_ETHER_TRAP_EN_MSK 0x00100000
+#define TX_ETHER_TRAP_EN_I_MSK 0xffefffff
+#define TX_ETHER_TRAP_EN_SFT 20
+#define TX_ETHER_TRAP_EN_HI 20
+#define TX_ETHER_TRAP_EN_SZ 1
+#define RX_ETHER_TRAP_EN_MSK 0x00200000
+#define RX_ETHER_TRAP_EN_I_MSK 0xffdfffff
+#define RX_ETHER_TRAP_EN_SFT 21
+#define RX_ETHER_TRAP_EN_HI 21
+#define RX_ETHER_TRAP_EN_SZ 1
+#define RX_NULL_TRAP_EN_MSK 0x00400000
+#define RX_NULL_TRAP_EN_I_MSK 0xffbfffff
+#define RX_NULL_TRAP_EN_SFT 22
+#define RX_NULL_TRAP_EN_HI 22
+#define RX_NULL_TRAP_EN_SZ 1
+#define RX_GET_TX_QUEUE_EN_MSK 0x02000000
+#define RX_GET_TX_QUEUE_EN_I_MSK 0xfdffffff
+#define RX_GET_TX_QUEUE_EN_SFT 25
+#define RX_GET_TX_QUEUE_EN_HI 25
+#define RX_GET_TX_QUEUE_EN_SZ 1
+#define HCI_INQ_SEL_MSK 0x04000000
+#define HCI_INQ_SEL_I_MSK 0xfbffffff
+#define HCI_INQ_SEL_SFT 26
+#define HCI_INQ_SEL_HI 26
+#define HCI_INQ_SEL_SZ 1
+#define TRX_DEBUG_CNT_ENA_MSK 0x10000000
+#define TRX_DEBUG_CNT_ENA_I_MSK 0xefffffff
+#define TRX_DEBUG_CNT_ENA_SFT 28
+#define TRX_DEBUG_CNT_ENA_HI 28
+#define TRX_DEBUG_CNT_ENA_SZ 1
+#define WAKE_SOON_WITH_SCK_MSK 0x00000001
+#define WAKE_SOON_WITH_SCK_I_MSK 0xfffffffe
+#define WAKE_SOON_WITH_SCK_SFT 0
+#define WAKE_SOON_WITH_SCK_HI 0
+#define WAKE_SOON_WITH_SCK_SZ 1
+#define TX_FLOW_CTRL_MSK 0x0000ffff
+#define TX_FLOW_CTRL_I_MSK 0xffff0000
+#define TX_FLOW_CTRL_SFT 0
+#define TX_FLOW_CTRL_HI 15
+#define TX_FLOW_CTRL_SZ 16
+#define TX_FLOW_MGMT_MSK 0xffff0000
+#define TX_FLOW_MGMT_I_MSK 0x0000ffff
+#define TX_FLOW_MGMT_SFT 16
+#define TX_FLOW_MGMT_HI 31
+#define TX_FLOW_MGMT_SZ 16
+#define TX_FLOW_DATA_MSK 0xffffffff
+#define TX_FLOW_DATA_I_MSK 0x00000000
+#define TX_FLOW_DATA_SFT 0
+#define TX_FLOW_DATA_HI 31
+#define TX_FLOW_DATA_SZ 32
+#define DOT11RTSTHRESHOLD_MSK 0xffff0000
+#define DOT11RTSTHRESHOLD_I_MSK 0x0000ffff
+#define DOT11RTSTHRESHOLD_SFT 16
+#define DOT11RTSTHRESHOLD_HI 31
+#define DOT11RTSTHRESHOLD_SZ 16
+#define TXF_ID_MSK 0x0000003f
+#define TXF_ID_I_MSK 0xffffffc0
+#define TXF_ID_SFT 0
+#define TXF_ID_HI 5
+#define TXF_ID_SZ 6
+#define SEQ_CTRL_MSK 0x0000ffff
+#define SEQ_CTRL_I_MSK 0xffff0000
+#define SEQ_CTRL_SFT 0
+#define SEQ_CTRL_HI 15
+#define SEQ_CTRL_SZ 16
+#define TX_PBOFFSET_MSK 0x000000ff
+#define TX_PBOFFSET_I_MSK 0xffffff00
+#define TX_PBOFFSET_SFT 0
+#define TX_PBOFFSET_HI 7
+#define TX_PBOFFSET_SZ 8
+#define TX_INFO_SIZE_MSK 0x0000ff00
+#define TX_INFO_SIZE_I_MSK 0xffff00ff
+#define TX_INFO_SIZE_SFT 8
+#define TX_INFO_SIZE_HI 15
+#define TX_INFO_SIZE_SZ 8
+#define RX_INFO_SIZE_MSK 0x00ff0000
+#define RX_INFO_SIZE_I_MSK 0xff00ffff
+#define RX_INFO_SIZE_SFT 16
+#define RX_INFO_SIZE_HI 23
+#define RX_INFO_SIZE_SZ 8
+#define RX_LAST_PHY_SIZE_MSK 0xff000000
+#define RX_LAST_PHY_SIZE_I_MSK 0x00ffffff
+#define RX_LAST_PHY_SIZE_SFT 24
+#define RX_LAST_PHY_SIZE_HI 31
+#define RX_LAST_PHY_SIZE_SZ 8
+#define TX_INFO_CLEAR_SIZE_MSK 0x0000003f
+#define TX_INFO_CLEAR_SIZE_I_MSK 0xffffffc0
+#define TX_INFO_CLEAR_SIZE_SFT 0
+#define TX_INFO_CLEAR_SIZE_HI 5
+#define TX_INFO_CLEAR_SIZE_SZ 6
+#define TX_INFO_CLEAR_ENABLE_MSK 0x00000100
+#define TX_INFO_CLEAR_ENABLE_I_MSK 0xfffffeff
+#define TX_INFO_CLEAR_ENABLE_SFT 8
+#define TX_INFO_CLEAR_ENABLE_HI 8
+#define TX_INFO_CLEAR_ENABLE_SZ 1
+#define TXTRAP_ETHTYPE1_MSK 0x0000ffff
+#define TXTRAP_ETHTYPE1_I_MSK 0xffff0000
+#define TXTRAP_ETHTYPE1_SFT 0
+#define TXTRAP_ETHTYPE1_HI 15
+#define TXTRAP_ETHTYPE1_SZ 16
+#define TXTRAP_ETHTYPE0_MSK 0xffff0000
+#define TXTRAP_ETHTYPE0_I_MSK 0x0000ffff
+#define TXTRAP_ETHTYPE0_SFT 16
+#define TXTRAP_ETHTYPE0_HI 31
+#define TXTRAP_ETHTYPE0_SZ 16
+#define RXTRAP_ETHTYPE1_MSK 0x0000ffff
+#define RXTRAP_ETHTYPE1_I_MSK 0xffff0000
+#define RXTRAP_ETHTYPE1_SFT 0
+#define RXTRAP_ETHTYPE1_HI 15
+#define RXTRAP_ETHTYPE1_SZ 16
+#define RXTRAP_ETHTYPE0_MSK 0xffff0000
+#define RXTRAP_ETHTYPE0_I_MSK 0x0000ffff
+#define RXTRAP_ETHTYPE0_SFT 16
+#define RXTRAP_ETHTYPE0_HI 31
+#define RXTRAP_ETHTYPE0_SZ 16
+#define TX_PKT_COUNTER_MSK 0xffffffff
+#define TX_PKT_COUNTER_I_MSK 0x00000000
+#define TX_PKT_COUNTER_SFT 0
+#define TX_PKT_COUNTER_HI 31
+#define TX_PKT_COUNTER_SZ 32
+#define RX_PKT_COUNTER_MSK 0xffffffff
+#define RX_PKT_COUNTER_I_MSK 0x00000000
+#define RX_PKT_COUNTER_SFT 0
+#define RX_PKT_COUNTER_HI 31
+#define RX_PKT_COUNTER_SZ 32
+#define HOST_CMD_COUNTER_MSK 0x000000ff
+#define HOST_CMD_COUNTER_I_MSK 0xffffff00
+#define HOST_CMD_COUNTER_SFT 0
+#define HOST_CMD_COUNTER_HI 7
+#define HOST_CMD_COUNTER_SZ 8
+#define HOST_EVENT_COUNTER_MSK 0x000000ff
+#define HOST_EVENT_COUNTER_I_MSK 0xffffff00
+#define HOST_EVENT_COUNTER_SFT 0
+#define HOST_EVENT_COUNTER_HI 7
+#define HOST_EVENT_COUNTER_SZ 8
+#define TX_PKT_DROP_COUNTER_MSK 0x000000ff
+#define TX_PKT_DROP_COUNTER_I_MSK 0xffffff00
+#define TX_PKT_DROP_COUNTER_SFT 0
+#define TX_PKT_DROP_COUNTER_HI 7
+#define TX_PKT_DROP_COUNTER_SZ 8
+#define RX_PKT_DROP_COUNTER_MSK 0x000000ff
+#define RX_PKT_DROP_COUNTER_I_MSK 0xffffff00
+#define RX_PKT_DROP_COUNTER_SFT 0
+#define RX_PKT_DROP_COUNTER_HI 7
+#define RX_PKT_DROP_COUNTER_SZ 8
+#define TX_PKT_TRAP_COUNTER_MSK 0x000000ff
+#define TX_PKT_TRAP_COUNTER_I_MSK 0xffffff00
+#define TX_PKT_TRAP_COUNTER_SFT 0
+#define TX_PKT_TRAP_COUNTER_HI 7
+#define TX_PKT_TRAP_COUNTER_SZ 8
+#define RX_PKT_TRAP_COUNTER_MSK 0x000000ff
+#define RX_PKT_TRAP_COUNTER_I_MSK 0xffffff00
+#define RX_PKT_TRAP_COUNTER_SFT 0
+#define RX_PKT_TRAP_COUNTER_HI 7
+#define RX_PKT_TRAP_COUNTER_SZ 8
+#define HOST_TX_FAIL_COUNTER_MSK 0x000000ff
+#define HOST_TX_FAIL_COUNTER_I_MSK 0xffffff00
+#define HOST_TX_FAIL_COUNTER_SFT 0
+#define HOST_TX_FAIL_COUNTER_HI 7
+#define HOST_TX_FAIL_COUNTER_SZ 8
+#define HOST_RX_FAIL_COUNTER_MSK 0x000000ff
+#define HOST_RX_FAIL_COUNTER_I_MSK 0xffffff00
+#define HOST_RX_FAIL_COUNTER_SFT 0
+#define HOST_RX_FAIL_COUNTER_HI 7
+#define HOST_RX_FAIL_COUNTER_SZ 8
+#define HCI_STATE_MONITOR_MSK 0xffffffff
+#define HCI_STATE_MONITOR_I_MSK 0x00000000
+#define HCI_STATE_MONITOR_SFT 0
+#define HCI_STATE_MONITOR_HI 31
+#define HCI_STATE_MONITOR_SZ 32
+#define HCI_ST_TIMEOUT_MONITOR_MSK 0xffffffff
+#define HCI_ST_TIMEOUT_MONITOR_I_MSK 0x00000000
+#define HCI_ST_TIMEOUT_MONITOR_SFT 0
+#define HCI_ST_TIMEOUT_MONITOR_HI 31
+#define HCI_ST_TIMEOUT_MONITOR_SZ 32
+#define TX_ON_DEMAND_LENGTH_MSK 0xffffffff
+#define TX_ON_DEMAND_LENGTH_I_MSK 0x00000000
+#define TX_ON_DEMAND_LENGTH_SFT 0
+#define TX_ON_DEMAND_LENGTH_HI 31
+#define TX_ON_DEMAND_LENGTH_SZ 32
+#define HCI_MONITOR_REG1_MSK 0xffffffff
+#define HCI_MONITOR_REG1_I_MSK 0x00000000
+#define HCI_MONITOR_REG1_SFT 0
+#define HCI_MONITOR_REG1_HI 31
+#define HCI_MONITOR_REG1_SZ 32
+#define HCI_MONITOR_REG2_MSK 0xffffffff
+#define HCI_MONITOR_REG2_I_MSK 0x00000000
+#define HCI_MONITOR_REG2_SFT 0
+#define HCI_MONITOR_REG2_HI 31
+#define HCI_MONITOR_REG2_SZ 32
+#define HCI_TX_ALLOC_TIME_31_0_MSK 0xffffffff
+#define HCI_TX_ALLOC_TIME_31_0_I_MSK 0x00000000
+#define HCI_TX_ALLOC_TIME_31_0_SFT 0
+#define HCI_TX_ALLOC_TIME_31_0_HI 31
+#define HCI_TX_ALLOC_TIME_31_0_SZ 32
+#define HCI_TX_ALLOC_TIME_47_32_MSK 0x0000ffff
+#define HCI_TX_ALLOC_TIME_47_32_I_MSK 0xffff0000
+#define HCI_TX_ALLOC_TIME_47_32_SFT 0
+#define HCI_TX_ALLOC_TIME_47_32_HI 15
+#define HCI_TX_ALLOC_TIME_47_32_SZ 16
+#define HCI_MB_MAX_CNT_MSK 0x00ff0000
+#define HCI_MB_MAX_CNT_I_MSK 0xff00ffff
+#define HCI_MB_MAX_CNT_SFT 16
+#define HCI_MB_MAX_CNT_HI 23
+#define HCI_MB_MAX_CNT_SZ 8
+#define HCI_TX_ALLOC_CNT_31_0_MSK 0xffffffff
+#define HCI_TX_ALLOC_CNT_31_0_I_MSK 0x00000000
+#define HCI_TX_ALLOC_CNT_31_0_SFT 0
+#define HCI_TX_ALLOC_CNT_31_0_HI 31
+#define HCI_TX_ALLOC_CNT_31_0_SZ 32
+#define HCI_TX_ALLOC_CNT_47_32_MSK 0x0000ffff
+#define HCI_TX_ALLOC_CNT_47_32_I_MSK 0xffff0000
+#define HCI_TX_ALLOC_CNT_47_32_SFT 0
+#define HCI_TX_ALLOC_CNT_47_32_HI 15
+#define HCI_TX_ALLOC_CNT_47_32_SZ 16
+#define HCI_PROC_CNT_MSK 0x00ff0000
+#define HCI_PROC_CNT_I_MSK 0xff00ffff
+#define HCI_PROC_CNT_SFT 16
+#define HCI_PROC_CNT_HI 23
+#define HCI_PROC_CNT_SZ 8
+#define SDIO_TRANS_CNT_MSK 0xff000000
+#define SDIO_TRANS_CNT_I_MSK 0x00ffffff
+#define SDIO_TRANS_CNT_SFT 24
+#define SDIO_TRANS_CNT_HI 31
+#define SDIO_TRANS_CNT_SZ 8
+#define SDIO_TX_INVALID_CNT_31_0_MSK 0xffffffff
+#define SDIO_TX_INVALID_CNT_31_0_I_MSK 0x00000000
+#define SDIO_TX_INVALID_CNT_31_0_SFT 0
+#define SDIO_TX_INVALID_CNT_31_0_HI 31
+#define SDIO_TX_INVALID_CNT_31_0_SZ 32
+#define SDIO_TX_INVALID_CNT_47_32_MSK 0x0000ffff
+#define SDIO_TX_INVALID_CNT_47_32_I_MSK 0xffff0000
+#define SDIO_TX_INVALID_CNT_47_32_SFT 0
+#define SDIO_TX_INVALID_CNT_47_32_HI 15
+#define SDIO_TX_INVALID_CNT_47_32_SZ 16
+#define CS_START_ADDR_MSK 0x0000ffff
+#define CS_START_ADDR_I_MSK 0xffff0000
+#define CS_START_ADDR_SFT 0
+#define CS_START_ADDR_HI 15
+#define CS_START_ADDR_SZ 16
+#define CS_PKT_ID_MSK 0x007f0000
+#define CS_PKT_ID_I_MSK 0xff80ffff
+#define CS_PKT_ID_SFT 16
+#define CS_PKT_ID_HI 22
+#define CS_PKT_ID_SZ 7
+#define ADD_LEN_MSK 0x0000ffff
+#define ADD_LEN_I_MSK 0xffff0000
+#define ADD_LEN_SFT 0
+#define ADD_LEN_HI 15
+#define ADD_LEN_SZ 16
+#define CS_ADDER_EN_MSK 0x00000001
+#define CS_ADDER_EN_I_MSK 0xfffffffe
+#define CS_ADDER_EN_SFT 0
+#define CS_ADDER_EN_HI 0
+#define CS_ADDER_EN_SZ 1
+#define PSEUDO_MSK 0x00000002
+#define PSEUDO_I_MSK 0xfffffffd
+#define PSEUDO_SFT 1
+#define PSEUDO_HI 1
+#define PSEUDO_SZ 1
+#define CALCULATE_MSK 0xffffffff
+#define CALCULATE_I_MSK 0x00000000
+#define CALCULATE_SFT 0
+#define CALCULATE_HI 31
+#define CALCULATE_SZ 32
+#define L4_LEN_MSK 0x0000ffff
+#define L4_LEN_I_MSK 0xffff0000
+#define L4_LEN_SFT 0
+#define L4_LEN_HI 15
+#define L4_LEN_SZ 16
+#define L4_PROTOL_MSK 0x00ff0000
+#define L4_PROTOL_I_MSK 0xff00ffff
+#define L4_PROTOL_SFT 16
+#define L4_PROTOL_HI 23
+#define L4_PROTOL_SZ 8
+#define CHECK_SUM_MSK 0x0000ffff
+#define CHECK_SUM_I_MSK 0xffff0000
+#define CHECK_SUM_SFT 0
+#define CHECK_SUM_HI 15
+#define CHECK_SUM_SZ 16
+#define RAND_EN_MSK 0x00000001
+#define RAND_EN_I_MSK 0xfffffffe
+#define RAND_EN_SFT 0
+#define RAND_EN_HI 0
+#define RAND_EN_SZ 1
+#define RAND_NUM_MSK 0xffffffff
+#define RAND_NUM_I_MSK 0x00000000
+#define RAND_NUM_SFT 0
+#define RAND_NUM_HI 31
+#define RAND_NUM_SZ 32
+#define MUL_OP1_MSK 0xffffffff
+#define MUL_OP1_I_MSK 0x00000000
+#define MUL_OP1_SFT 0
+#define MUL_OP1_HI 31
+#define MUL_OP1_SZ 32
+#define MUL_OP2_MSK 0xffffffff
+#define MUL_OP2_I_MSK 0x00000000
+#define MUL_OP2_SFT 0
+#define MUL_OP2_HI 31
+#define MUL_OP2_SZ 32
+#define MUL_ANS0_MSK 0xffffffff
+#define MUL_ANS0_I_MSK 0x00000000
+#define MUL_ANS0_SFT 0
+#define MUL_ANS0_HI 31
+#define MUL_ANS0_SZ 32
+#define MUL_ANS1_MSK 0xffffffff
+#define MUL_ANS1_I_MSK 0x00000000
+#define MUL_ANS1_SFT 0
+#define MUL_ANS1_HI 31
+#define MUL_ANS1_SZ 32
+#define RD_ADDR_MSK 0x0000ffff
+#define RD_ADDR_I_MSK 0xffff0000
+#define RD_ADDR_SFT 0
+#define RD_ADDR_HI 15
+#define RD_ADDR_SZ 16
+#define RD_ID_MSK 0x007f0000
+#define RD_ID_I_MSK 0xff80ffff
+#define RD_ID_SFT 16
+#define RD_ID_HI 22
+#define RD_ID_SZ 7
+#define WR_ADDR_MSK 0x0000ffff
+#define WR_ADDR_I_MSK 0xffff0000
+#define WR_ADDR_SFT 0
+#define WR_ADDR_HI 15
+#define WR_ADDR_SZ 16
+#define WR_ID_MSK 0x007f0000
+#define WR_ID_I_MSK 0xff80ffff
+#define WR_ID_SFT 16
+#define WR_ID_HI 22
+#define WR_ID_SZ 7
+#define LEN_MSK 0x0000ffff
+#define LEN_I_MSK 0xffff0000
+#define LEN_SFT 0
+#define LEN_HI 15
+#define LEN_SZ 16
+#define CLR_MSK 0x00000001
+#define CLR_I_MSK 0xfffffffe
+#define CLR_SFT 0
+#define CLR_HI 0
+#define CLR_SZ 1
+#define PHY_MODE_MSK 0x00000003
+#define PHY_MODE_I_MSK 0xfffffffc
+#define PHY_MODE_SFT 0
+#define PHY_MODE_HI 1
+#define PHY_MODE_SZ 2
+#define SHRT_PREAM_MSK 0x00000004
+#define SHRT_PREAM_I_MSK 0xfffffffb
+#define SHRT_PREAM_SFT 2
+#define SHRT_PREAM_HI 2
+#define SHRT_PREAM_SZ 1
+#define SHRT_GI_MSK 0x00000008
+#define SHRT_GI_I_MSK 0xfffffff7
+#define SHRT_GI_SFT 3
+#define SHRT_GI_HI 3
+#define SHRT_GI_SZ 1
+#define DATA_RATE_MSK 0x000007f0
+#define DATA_RATE_I_MSK 0xfffff80f
+#define DATA_RATE_SFT 4
+#define DATA_RATE_HI 10
+#define DATA_RATE_SZ 7
+#define MCS_MSK 0x00007000
+#define MCS_I_MSK 0xffff8fff
+#define MCS_SFT 12
+#define MCS_HI 14
+#define MCS_SZ 3
+#define FRAME_LEN_MSK 0xffff0000
+#define FRAME_LEN_I_MSK 0x0000ffff
+#define FRAME_LEN_SFT 16
+#define FRAME_LEN_HI 31
+#define FRAME_LEN_SZ 16
+#define DURATION_MSK 0x0000ffff
+#define DURATION_I_MSK 0xffff0000
+#define DURATION_SFT 0
+#define DURATION_HI 15
+#define DURATION_SZ 16
+#define SHA_DST_ADDR_MSK 0xffffffff
+#define SHA_DST_ADDR_I_MSK 0x00000000
+#define SHA_DST_ADDR_SFT 0
+#define SHA_DST_ADDR_HI 31
+#define SHA_DST_ADDR_SZ 32
+#define SHA_SRC_ADDR_MSK 0xffffffff
+#define SHA_SRC_ADDR_I_MSK 0x00000000
+#define SHA_SRC_ADDR_SFT 0
+#define SHA_SRC_ADDR_HI 31
+#define SHA_SRC_ADDR_SZ 32
+#define SHA_BUSY_MSK 0x00000001
+#define SHA_BUSY_I_MSK 0xfffffffe
+#define SHA_BUSY_SFT 0
+#define SHA_BUSY_HI 0
+#define SHA_BUSY_SZ 1
+#define SHA_ENDIAN_MSK 0x00000002
+#define SHA_ENDIAN_I_MSK 0xfffffffd
+#define SHA_ENDIAN_SFT 1
+#define SHA_ENDIAN_HI 1
+#define SHA_ENDIAN_SZ 1
+#define EFS_CLKFREQ_MSK 0x00000fff
+#define EFS_CLKFREQ_I_MSK 0xfffff000
+#define EFS_CLKFREQ_SFT 0
+#define EFS_CLKFREQ_HI 11
+#define EFS_CLKFREQ_SZ 12
+#define LOW_ACTIVE_MSK 0x00010000
+#define LOW_ACTIVE_I_MSK 0xfffeffff
+#define LOW_ACTIVE_SFT 16
+#define LOW_ACTIVE_HI 16
+#define LOW_ACTIVE_SZ 1
+#define EFS_CLKFREQ_RD_MSK 0x0ff00000
+#define EFS_CLKFREQ_RD_I_MSK 0xf00fffff
+#define EFS_CLKFREQ_RD_SFT 20
+#define EFS_CLKFREQ_RD_HI 27
+#define EFS_CLKFREQ_RD_SZ 8
+#define EFS_PRE_RD_MSK 0xf0000000
+#define EFS_PRE_RD_I_MSK 0x0fffffff
+#define EFS_PRE_RD_SFT 28
+#define EFS_PRE_RD_HI 31
+#define EFS_PRE_RD_SZ 4
+#define EFS_LDO_ON_MSK 0x0000ffff
+#define EFS_LDO_ON_I_MSK 0xffff0000
+#define EFS_LDO_ON_SFT 0
+#define EFS_LDO_ON_HI 15
+#define EFS_LDO_ON_SZ 16
+#define EFS_LDO_OFF_MSK 0xffff0000
+#define EFS_LDO_OFF_I_MSK 0x0000ffff
+#define EFS_LDO_OFF_SFT 16
+#define EFS_LDO_OFF_HI 31
+#define EFS_LDO_OFF_SZ 16
+#define EFS_RDATA_0_MSK 0xffffffff
+#define EFS_RDATA_0_I_MSK 0x00000000
+#define EFS_RDATA_0_SFT 0
+#define EFS_RDATA_0_HI 31
+#define EFS_RDATA_0_SZ 32
+#define EFS_WDATA_0_MSK 0xffffffff
+#define EFS_WDATA_0_I_MSK 0x00000000
+#define EFS_WDATA_0_SFT 0
+#define EFS_WDATA_0_HI 31
+#define EFS_WDATA_0_SZ 32
+#define EFS_RDATA_1_MSK 0xffffffff
+#define EFS_RDATA_1_I_MSK 0x00000000
+#define EFS_RDATA_1_SFT 0
+#define EFS_RDATA_1_HI 31
+#define EFS_RDATA_1_SZ 32
+#define EFS_WDATA_1_MSK 0xffffffff
+#define EFS_WDATA_1_I_MSK 0x00000000
+#define EFS_WDATA_1_SFT 0
+#define EFS_WDATA_1_HI 31
+#define EFS_WDATA_1_SZ 32
+#define EFS_RDATA_2_MSK 0xffffffff
+#define EFS_RDATA_2_I_MSK 0x00000000
+#define EFS_RDATA_2_SFT 0
+#define EFS_RDATA_2_HI 31
+#define EFS_RDATA_2_SZ 32
+#define EFS_WDATA_2_MSK 0xffffffff
+#define EFS_WDATA_2_I_MSK 0x00000000
+#define EFS_WDATA_2_SFT 0
+#define EFS_WDATA_2_HI 31
+#define EFS_WDATA_2_SZ 32
+#define EFS_RDATA_3_MSK 0xffffffff
+#define EFS_RDATA_3_I_MSK 0x00000000
+#define EFS_RDATA_3_SFT 0
+#define EFS_RDATA_3_HI 31
+#define EFS_RDATA_3_SZ 32
+#define EFS_WDATA_3_MSK 0xffffffff
+#define EFS_WDATA_3_I_MSK 0x00000000
+#define EFS_WDATA_3_SFT 0
+#define EFS_WDATA_3_HI 31
+#define EFS_WDATA_3_SZ 32
+#define EFS_RDATA_4_MSK 0xffffffff
+#define EFS_RDATA_4_I_MSK 0x00000000
+#define EFS_RDATA_4_SFT 0
+#define EFS_RDATA_4_HI 31
+#define EFS_RDATA_4_SZ 32
+#define EFS_WDATA_4_MSK 0xffffffff
+#define EFS_WDATA_4_I_MSK 0x00000000
+#define EFS_WDATA_4_SFT 0
+#define EFS_WDATA_4_HI 31
+#define EFS_WDATA_4_SZ 32
+#define EFS_RDATA_5_MSK 0xffffffff
+#define EFS_RDATA_5_I_MSK 0x00000000
+#define EFS_RDATA_5_SFT 0
+#define EFS_RDATA_5_HI 31
+#define EFS_RDATA_5_SZ 32
+#define EFS_WDATA_5_MSK 0xffffffff
+#define EFS_WDATA_5_I_MSK 0x00000000
+#define EFS_WDATA_5_SFT 0
+#define EFS_WDATA_5_HI 31
+#define EFS_WDATA_5_SZ 32
+#define EFS_RDATA_6_MSK 0xffffffff
+#define EFS_RDATA_6_I_MSK 0x00000000
+#define EFS_RDATA_6_SFT 0
+#define EFS_RDATA_6_HI 31
+#define EFS_RDATA_6_SZ 32
+#define EFS_WDATA_6_MSK 0xffffffff
+#define EFS_WDATA_6_I_MSK 0x00000000
+#define EFS_WDATA_6_SFT 0
+#define EFS_WDATA_6_HI 31
+#define EFS_WDATA_6_SZ 32
+#define EFS_RDATA_7_MSK 0xffffffff
+#define EFS_RDATA_7_I_MSK 0x00000000
+#define EFS_RDATA_7_SFT 0
+#define EFS_RDATA_7_HI 31
+#define EFS_RDATA_7_SZ 32
+#define EFS_WDATA_7_MSK 0xffffffff
+#define EFS_WDATA_7_I_MSK 0x00000000
+#define EFS_WDATA_7_SFT 0
+#define EFS_WDATA_7_HI 31
+#define EFS_WDATA_7_SZ 32
+#define EFS_SPI_RD0_EN_MSK 0x00000001
+#define EFS_SPI_RD0_EN_I_MSK 0xfffffffe
+#define EFS_SPI_RD0_EN_SFT 0
+#define EFS_SPI_RD0_EN_HI 0
+#define EFS_SPI_RD0_EN_SZ 1
+#define EFS_SPI_RD1_EN_MSK 0x00000001
+#define EFS_SPI_RD1_EN_I_MSK 0xfffffffe
+#define EFS_SPI_RD1_EN_SFT 0
+#define EFS_SPI_RD1_EN_HI 0
+#define EFS_SPI_RD1_EN_SZ 1
+#define EFS_SPI_RD2_EN_MSK 0x00000001
+#define EFS_SPI_RD2_EN_I_MSK 0xfffffffe
+#define EFS_SPI_RD2_EN_SFT 0
+#define EFS_SPI_RD2_EN_HI 0
+#define EFS_SPI_RD2_EN_SZ 1
+#define EFS_SPI_RD3_EN_MSK 0x00000001
+#define EFS_SPI_RD3_EN_I_MSK 0xfffffffe
+#define EFS_SPI_RD3_EN_SFT 0
+#define EFS_SPI_RD3_EN_HI 0
+#define EFS_SPI_RD3_EN_SZ 1
+#define EFS_SPI_RD4_EN_MSK 0x00000001
+#define EFS_SPI_RD4_EN_I_MSK 0xfffffffe
+#define EFS_SPI_RD4_EN_SFT 0
+#define EFS_SPI_RD4_EN_HI 0
+#define EFS_SPI_RD4_EN_SZ 1
+#define EFS_SPI_RD5_EN_MSK 0x00000001
+#define EFS_SPI_RD5_EN_I_MSK 0xfffffffe
+#define EFS_SPI_RD5_EN_SFT 0
+#define EFS_SPI_RD5_EN_HI 0
+#define EFS_SPI_RD5_EN_SZ 1
+#define EFS_SPI_RD6_EN_MSK 0x00000001
+#define EFS_SPI_RD6_EN_I_MSK 0xfffffffe
+#define EFS_SPI_RD6_EN_SFT 0
+#define EFS_SPI_RD6_EN_HI 0
+#define EFS_SPI_RD6_EN_SZ 1
+#define EFS_SPI_RD7_EN_MSK 0x00000001
+#define EFS_SPI_RD7_EN_I_MSK 0xfffffffe
+#define EFS_SPI_RD7_EN_SFT 0
+#define EFS_SPI_RD7_EN_HI 0
+#define EFS_SPI_RD7_EN_SZ 1
+#define EFS_SPI_RBUSY_MSK 0x00000001
+#define EFS_SPI_RBUSY_I_MSK 0xfffffffe
+#define EFS_SPI_RBUSY_SFT 0
+#define EFS_SPI_RBUSY_HI 0
+#define EFS_SPI_RBUSY_SZ 1
+#define EFS_SPI_RDATA_0_MSK 0xffffffff
+#define EFS_SPI_RDATA_0_I_MSK 0x00000000
+#define EFS_SPI_RDATA_0_SFT 0
+#define EFS_SPI_RDATA_0_HI 31
+#define EFS_SPI_RDATA_0_SZ 32
+#define EFS_SPI_RDATA_1_MSK 0xffffffff
+#define EFS_SPI_RDATA_1_I_MSK 0x00000000
+#define EFS_SPI_RDATA_1_SFT 0
+#define EFS_SPI_RDATA_1_HI 31
+#define EFS_SPI_RDATA_1_SZ 32
+#define EFS_SPI_RDATA_2_MSK 0xffffffff
+#define EFS_SPI_RDATA_2_I_MSK 0x00000000
+#define EFS_SPI_RDATA_2_SFT 0
+#define EFS_SPI_RDATA_2_HI 31
+#define EFS_SPI_RDATA_2_SZ 32
+#define EFS_SPI_RDATA_3_MSK 0xffffffff
+#define EFS_SPI_RDATA_3_I_MSK 0x00000000
+#define EFS_SPI_RDATA_3_SFT 0
+#define EFS_SPI_RDATA_3_HI 31
+#define EFS_SPI_RDATA_3_SZ 32
+#define EFS_SPI_RDATA_4_MSK 0xffffffff
+#define EFS_SPI_RDATA_4_I_MSK 0x00000000
+#define EFS_SPI_RDATA_4_SFT 0
+#define EFS_SPI_RDATA_4_HI 31
+#define EFS_SPI_RDATA_4_SZ 32
+#define EFS_SPI_RDATA_5_MSK 0xffffffff
+#define EFS_SPI_RDATA_5_I_MSK 0x00000000
+#define EFS_SPI_RDATA_5_SFT 0
+#define EFS_SPI_RDATA_5_HI 31
+#define EFS_SPI_RDATA_5_SZ 32
+#define EFS_SPI_RDATA_6_MSK 0xffffffff
+#define EFS_SPI_RDATA_6_I_MSK 0x00000000
+#define EFS_SPI_RDATA_6_SFT 0
+#define EFS_SPI_RDATA_6_HI 31
+#define EFS_SPI_RDATA_6_SZ 32
+#define EFS_SPI_RDATA_7_MSK 0xffffffff
+#define EFS_SPI_RDATA_7_I_MSK 0x00000000
+#define EFS_SPI_RDATA_7_SFT 0
+#define EFS_SPI_RDATA_7_HI 31
+#define EFS_SPI_RDATA_7_SZ 32
+#define GET_RK_MSK 0x00000001
+#define GET_RK_I_MSK 0xfffffffe
+#define GET_RK_SFT 0
+#define GET_RK_HI 0
+#define GET_RK_SZ 1
+#define FORCE_GET_RK_MSK 0x00000002
+#define FORCE_GET_RK_I_MSK 0xfffffffd
+#define FORCE_GET_RK_SFT 1
+#define FORCE_GET_RK_HI 1
+#define FORCE_GET_RK_SZ 1
+#define SMS4_DESCRY_EN_MSK 0x00000010
+#define SMS4_DESCRY_EN_I_MSK 0xffffffef
+#define SMS4_DESCRY_EN_SFT 4
+#define SMS4_DESCRY_EN_HI 4
+#define SMS4_DESCRY_EN_SZ 1
+#define DEC_DOUT_MSB_MSK 0x00000001
+#define DEC_DOUT_MSB_I_MSK 0xfffffffe
+#define DEC_DOUT_MSB_SFT 0
+#define DEC_DOUT_MSB_HI 0
+#define DEC_DOUT_MSB_SZ 1
+#define DEC_DIN_MSB_MSK 0x00000002
+#define DEC_DIN_MSB_I_MSK 0xfffffffd
+#define DEC_DIN_MSB_SFT 1
+#define DEC_DIN_MSB_HI 1
+#define DEC_DIN_MSB_SZ 1
+#define ENC_DOUT_MSB_MSK 0x00000004
+#define ENC_DOUT_MSB_I_MSK 0xfffffffb
+#define ENC_DOUT_MSB_SFT 2
+#define ENC_DOUT_MSB_HI 2
+#define ENC_DOUT_MSB_SZ 1
+#define ENC_DIN_MSB_MSK 0x00000008
+#define ENC_DIN_MSB_I_MSK 0xfffffff7
+#define ENC_DIN_MSB_SFT 3
+#define ENC_DIN_MSB_HI 3
+#define ENC_DIN_MSB_SZ 1
+#define KEY_DIN_MSB_MSK 0x00000010
+#define KEY_DIN_MSB_I_MSK 0xffffffef
+#define KEY_DIN_MSB_SFT 4
+#define KEY_DIN_MSB_HI 4
+#define KEY_DIN_MSB_SZ 1
+#define SMS4_CBC_EN_MSK 0x00000001
+#define SMS4_CBC_EN_I_MSK 0xfffffffe
+#define SMS4_CBC_EN_SFT 0
+#define SMS4_CBC_EN_HI 0
+#define SMS4_CBC_EN_SZ 1
+#define SMS4_CFB_EN_MSK 0x00000002
+#define SMS4_CFB_EN_I_MSK 0xfffffffd
+#define SMS4_CFB_EN_SFT 1
+#define SMS4_CFB_EN_HI 1
+#define SMS4_CFB_EN_SZ 1
+#define SMS4_OFB_EN_MSK 0x00000004
+#define SMS4_OFB_EN_I_MSK 0xfffffffb
+#define SMS4_OFB_EN_SFT 2
+#define SMS4_OFB_EN_HI 2
+#define SMS4_OFB_EN_SZ 1
+#define SMS4_START_TRIG_MSK 0x00000001
+#define SMS4_START_TRIG_I_MSK 0xfffffffe
+#define SMS4_START_TRIG_SFT 0
+#define SMS4_START_TRIG_HI 0
+#define SMS4_START_TRIG_SZ 1
+#define SMS4_BUSY_MSK 0x00000001
+#define SMS4_BUSY_I_MSK 0xfffffffe
+#define SMS4_BUSY_SFT 0
+#define SMS4_BUSY_HI 0
+#define SMS4_BUSY_SZ 1
+#define SMS4_DONE_MSK 0x00000001
+#define SMS4_DONE_I_MSK 0xfffffffe
+#define SMS4_DONE_SFT 0
+#define SMS4_DONE_HI 0
+#define SMS4_DONE_SZ 1
+#define SMS4_DATAIN_0_MSK 0xffffffff
+#define SMS4_DATAIN_0_I_MSK 0x00000000
+#define SMS4_DATAIN_0_SFT 0
+#define SMS4_DATAIN_0_HI 31
+#define SMS4_DATAIN_0_SZ 32
+#define SMS4_DATAIN_1_MSK 0xffffffff
+#define SMS4_DATAIN_1_I_MSK 0x00000000
+#define SMS4_DATAIN_1_SFT 0
+#define SMS4_DATAIN_1_HI 31
+#define SMS4_DATAIN_1_SZ 32
+#define SMS4_DATAIN_2_MSK 0xffffffff
+#define SMS4_DATAIN_2_I_MSK 0x00000000
+#define SMS4_DATAIN_2_SFT 0
+#define SMS4_DATAIN_2_HI 31
+#define SMS4_DATAIN_2_SZ 32
+#define SMS4_DATAIN_3_MSK 0xffffffff
+#define SMS4_DATAIN_3_I_MSK 0x00000000
+#define SMS4_DATAIN_3_SFT 0
+#define SMS4_DATAIN_3_HI 31
+#define SMS4_DATAIN_3_SZ 32
+#define SMS4_DATAOUT_0_MSK 0xffffffff
+#define SMS4_DATAOUT_0_I_MSK 0x00000000
+#define SMS4_DATAOUT_0_SFT 0
+#define SMS4_DATAOUT_0_HI 31
+#define SMS4_DATAOUT_0_SZ 32
+#define SMS4_DATAOUT_1_MSK 0xffffffff
+#define SMS4_DATAOUT_1_I_MSK 0x00000000
+#define SMS4_DATAOUT_1_SFT 0
+#define SMS4_DATAOUT_1_HI 31
+#define SMS4_DATAOUT_1_SZ 32
+#define SMS4_DATAOUT_2_MSK 0xffffffff
+#define SMS4_DATAOUT_2_I_MSK 0x00000000
+#define SMS4_DATAOUT_2_SFT 0
+#define SMS4_DATAOUT_2_HI 31
+#define SMS4_DATAOUT_2_SZ 32
+#define SMS4_DATAOUT_3_MSK 0xffffffff
+#define SMS4_DATAOUT_3_I_MSK 0x00000000
+#define SMS4_DATAOUT_3_SFT 0
+#define SMS4_DATAOUT_3_HI 31
+#define SMS4_DATAOUT_3_SZ 32
+#define SMS4_KEY_0_MSK 0xffffffff
+#define SMS4_KEY_0_I_MSK 0x00000000
+#define SMS4_KEY_0_SFT 0
+#define SMS4_KEY_0_HI 31
+#define SMS4_KEY_0_SZ 32
+#define SMS4_KEY_1_MSK 0xffffffff
+#define SMS4_KEY_1_I_MSK 0x00000000
+#define SMS4_KEY_1_SFT 0
+#define SMS4_KEY_1_HI 31
+#define SMS4_KEY_1_SZ 32
+#define SMS4_KEY_2_MSK 0xffffffff
+#define SMS4_KEY_2_I_MSK 0x00000000
+#define SMS4_KEY_2_SFT 0
+#define SMS4_KEY_2_HI 31
+#define SMS4_KEY_2_SZ 32
+#define SMS4_KEY_3_MSK 0xffffffff
+#define SMS4_KEY_3_I_MSK 0x00000000
+#define SMS4_KEY_3_SFT 0
+#define SMS4_KEY_3_HI 31
+#define SMS4_KEY_3_SZ 32
+#define SMS4_MODE_IV0_MSK 0xffffffff
+#define SMS4_MODE_IV0_I_MSK 0x00000000
+#define SMS4_MODE_IV0_SFT 0
+#define SMS4_MODE_IV0_HI 31
+#define SMS4_MODE_IV0_SZ 32
+#define SMS4_MODE_IV1_MSK 0xffffffff
+#define SMS4_MODE_IV1_I_MSK 0x00000000
+#define SMS4_MODE_IV1_SFT 0
+#define SMS4_MODE_IV1_HI 31
+#define SMS4_MODE_IV1_SZ 32
+#define SMS4_MODE_IV2_MSK 0xffffffff
+#define SMS4_MODE_IV2_I_MSK 0x00000000
+#define SMS4_MODE_IV2_SFT 0
+#define SMS4_MODE_IV2_HI 31
+#define SMS4_MODE_IV2_SZ 32
+#define SMS4_MODE_IV3_MSK 0xffffffff
+#define SMS4_MODE_IV3_I_MSK 0x00000000
+#define SMS4_MODE_IV3_SFT 0
+#define SMS4_MODE_IV3_HI 31
+#define SMS4_MODE_IV3_SZ 32
+#define SMS4_OFB_ENC0_MSK 0xffffffff
+#define SMS4_OFB_ENC0_I_MSK 0x00000000
+#define SMS4_OFB_ENC0_SFT 0
+#define SMS4_OFB_ENC0_HI 31
+#define SMS4_OFB_ENC0_SZ 32
+#define SMS4_OFB_ENC1_MSK 0xffffffff
+#define SMS4_OFB_ENC1_I_MSK 0x00000000
+#define SMS4_OFB_ENC1_SFT 0
+#define SMS4_OFB_ENC1_HI 31
+#define SMS4_OFB_ENC1_SZ 32
+#define SMS4_OFB_ENC2_MSK 0xffffffff
+#define SMS4_OFB_ENC2_I_MSK 0x00000000
+#define SMS4_OFB_ENC2_SFT 0
+#define SMS4_OFB_ENC2_HI 31
+#define SMS4_OFB_ENC2_SZ 32
+#define SMS4_OFB_ENC3_MSK 0xffffffff
+#define SMS4_OFB_ENC3_I_MSK 0x00000000
+#define SMS4_OFB_ENC3_SFT 0
+#define SMS4_OFB_ENC3_HI 31
+#define SMS4_OFB_ENC3_SZ 32
+#define MRX_MCAST_TB0_31_0_MSK 0xffffffff
+#define MRX_MCAST_TB0_31_0_I_MSK 0x00000000
+#define MRX_MCAST_TB0_31_0_SFT 0
+#define MRX_MCAST_TB0_31_0_HI 31
+#define MRX_MCAST_TB0_31_0_SZ 32
+#define MRX_MCAST_TB0_47_32_MSK 0x0000ffff
+#define MRX_MCAST_TB0_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_TB0_47_32_SFT 0
+#define MRX_MCAST_TB0_47_32_HI 15
+#define MRX_MCAST_TB0_47_32_SZ 16
+#define MRX_MCAST_MASK0_31_0_MSK 0xffffffff
+#define MRX_MCAST_MASK0_31_0_I_MSK 0x00000000
+#define MRX_MCAST_MASK0_31_0_SFT 0
+#define MRX_MCAST_MASK0_31_0_HI 31
+#define MRX_MCAST_MASK0_31_0_SZ 32
+#define MRX_MCAST_MASK0_47_32_MSK 0x0000ffff
+#define MRX_MCAST_MASK0_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_MASK0_47_32_SFT 0
+#define MRX_MCAST_MASK0_47_32_HI 15
+#define MRX_MCAST_MASK0_47_32_SZ 16
+#define MRX_MCAST_CTRL_0_MSK 0x00000003
+#define MRX_MCAST_CTRL_0_I_MSK 0xfffffffc
+#define MRX_MCAST_CTRL_0_SFT 0
+#define MRX_MCAST_CTRL_0_HI 1
+#define MRX_MCAST_CTRL_0_SZ 2
+#define MRX_MCAST_TB1_31_0_MSK 0xffffffff
+#define MRX_MCAST_TB1_31_0_I_MSK 0x00000000
+#define MRX_MCAST_TB1_31_0_SFT 0
+#define MRX_MCAST_TB1_31_0_HI 31
+#define MRX_MCAST_TB1_31_0_SZ 32
+#define MRX_MCAST_TB1_47_32_MSK 0x0000ffff
+#define MRX_MCAST_TB1_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_TB1_47_32_SFT 0
+#define MRX_MCAST_TB1_47_32_HI 15
+#define MRX_MCAST_TB1_47_32_SZ 16
+#define MRX_MCAST_MASK1_31_0_MSK 0xffffffff
+#define MRX_MCAST_MASK1_31_0_I_MSK 0x00000000
+#define MRX_MCAST_MASK1_31_0_SFT 0
+#define MRX_MCAST_MASK1_31_0_HI 31
+#define MRX_MCAST_MASK1_31_0_SZ 32
+#define MRX_MCAST_MASK1_47_32_MSK 0x0000ffff
+#define MRX_MCAST_MASK1_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_MASK1_47_32_SFT 0
+#define MRX_MCAST_MASK1_47_32_HI 15
+#define MRX_MCAST_MASK1_47_32_SZ 16
+#define MRX_MCAST_CTRL_1_MSK 0x00000003
+#define MRX_MCAST_CTRL_1_I_MSK 0xfffffffc
+#define MRX_MCAST_CTRL_1_SFT 0
+#define MRX_MCAST_CTRL_1_HI 1
+#define MRX_MCAST_CTRL_1_SZ 2
+#define MRX_MCAST_TB2_31_0_MSK 0xffffffff
+#define MRX_MCAST_TB2_31_0_I_MSK 0x00000000
+#define MRX_MCAST_TB2_31_0_SFT 0
+#define MRX_MCAST_TB2_31_0_HI 31
+#define MRX_MCAST_TB2_31_0_SZ 32
+#define MRX_MCAST_TB2_47_32_MSK 0x0000ffff
+#define MRX_MCAST_TB2_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_TB2_47_32_SFT 0
+#define MRX_MCAST_TB2_47_32_HI 15
+#define MRX_MCAST_TB2_47_32_SZ 16
+#define MRX_MCAST_MASK2_31_0_MSK 0xffffffff
+#define MRX_MCAST_MASK2_31_0_I_MSK 0x00000000
+#define MRX_MCAST_MASK2_31_0_SFT 0
+#define MRX_MCAST_MASK2_31_0_HI 31
+#define MRX_MCAST_MASK2_31_0_SZ 32
+#define MRX_MCAST_MASK2_47_32_MSK 0x0000ffff
+#define MRX_MCAST_MASK2_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_MASK2_47_32_SFT 0
+#define MRX_MCAST_MASK2_47_32_HI 15
+#define MRX_MCAST_MASK2_47_32_SZ 16
+#define MRX_MCAST_CTRL_2_MSK 0x00000003
+#define MRX_MCAST_CTRL_2_I_MSK 0xfffffffc
+#define MRX_MCAST_CTRL_2_SFT 0
+#define MRX_MCAST_CTRL_2_HI 1
+#define MRX_MCAST_CTRL_2_SZ 2
+#define MRX_MCAST_TB3_31_0_MSK 0xffffffff
+#define MRX_MCAST_TB3_31_0_I_MSK 0x00000000
+#define MRX_MCAST_TB3_31_0_SFT 0
+#define MRX_MCAST_TB3_31_0_HI 31
+#define MRX_MCAST_TB3_31_0_SZ 32
+#define MRX_MCAST_TB3_47_32_MSK 0x0000ffff
+#define MRX_MCAST_TB3_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_TB3_47_32_SFT 0
+#define MRX_MCAST_TB3_47_32_HI 15
+#define MRX_MCAST_TB3_47_32_SZ 16
+#define MRX_MCAST_MASK3_31_0_MSK 0xffffffff
+#define MRX_MCAST_MASK3_31_0_I_MSK 0x00000000
+#define MRX_MCAST_MASK3_31_0_SFT 0
+#define MRX_MCAST_MASK3_31_0_HI 31
+#define MRX_MCAST_MASK3_31_0_SZ 32
+#define MRX_MCAST_MASK3_47_32_MSK 0x0000ffff
+#define MRX_MCAST_MASK3_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_MASK3_47_32_SFT 0
+#define MRX_MCAST_MASK3_47_32_HI 15
+#define MRX_MCAST_MASK3_47_32_SZ 16
+#define MRX_MCAST_CTRL_3_MSK 0x00000003
+#define MRX_MCAST_CTRL_3_I_MSK 0xfffffffc
+#define MRX_MCAST_CTRL_3_SFT 0
+#define MRX_MCAST_CTRL_3_HI 1
+#define MRX_MCAST_CTRL_3_SZ 2
+#define MRX_PHY_INFO_MSK 0xffffffff
+#define MRX_PHY_INFO_I_MSK 0x00000000
+#define MRX_PHY_INFO_SFT 0
+#define MRX_PHY_INFO_HI 31
+#define MRX_PHY_INFO_SZ 32
+#define DBG_BA_TYPE_MSK 0x0000003f
+#define DBG_BA_TYPE_I_MSK 0xffffffc0
+#define DBG_BA_TYPE_SFT 0
+#define DBG_BA_TYPE_HI 5
+#define DBG_BA_TYPE_SZ 6
+#define DBG_BA_SEQ_MSK 0x000fff00
+#define DBG_BA_SEQ_I_MSK 0xfff000ff
+#define DBG_BA_SEQ_SFT 8
+#define DBG_BA_SEQ_HI 19
+#define DBG_BA_SEQ_SZ 12
+#define MRX_FLT_TB0_MSK 0x00007fff
+#define MRX_FLT_TB0_I_MSK 0xffff8000
+#define MRX_FLT_TB0_SFT 0
+#define MRX_FLT_TB0_HI 14
+#define MRX_FLT_TB0_SZ 15
+#define MRX_FLT_TB1_MSK 0x00007fff
+#define MRX_FLT_TB1_I_MSK 0xffff8000
+#define MRX_FLT_TB1_SFT 0
+#define MRX_FLT_TB1_HI 14
+#define MRX_FLT_TB1_SZ 15
+#define MRX_FLT_TB2_MSK 0x00007fff
+#define MRX_FLT_TB2_I_MSK 0xffff8000
+#define MRX_FLT_TB2_SFT 0
+#define MRX_FLT_TB2_HI 14
+#define MRX_FLT_TB2_SZ 15
+#define MRX_FLT_TB3_MSK 0x00007fff
+#define MRX_FLT_TB3_I_MSK 0xffff8000
+#define MRX_FLT_TB3_SFT 0
+#define MRX_FLT_TB3_HI 14
+#define MRX_FLT_TB3_SZ 15
+#define MRX_FLT_TB4_MSK 0x00007fff
+#define MRX_FLT_TB4_I_MSK 0xffff8000
+#define MRX_FLT_TB4_SFT 0
+#define MRX_FLT_TB4_HI 14
+#define MRX_FLT_TB4_SZ 15
+#define MRX_FLT_TB5_MSK 0x00007fff
+#define MRX_FLT_TB5_I_MSK 0xffff8000
+#define MRX_FLT_TB5_SFT 0
+#define MRX_FLT_TB5_HI 14
+#define MRX_FLT_TB5_SZ 15
+#define MRX_FLT_TB6_MSK 0x00007fff
+#define MRX_FLT_TB6_I_MSK 0xffff8000
+#define MRX_FLT_TB6_SFT 0
+#define MRX_FLT_TB6_HI 14
+#define MRX_FLT_TB6_SZ 15
+#define MRX_FLT_TB7_MSK 0x00007fff
+#define MRX_FLT_TB7_I_MSK 0xffff8000
+#define MRX_FLT_TB7_SFT 0
+#define MRX_FLT_TB7_HI 14
+#define MRX_FLT_TB7_SZ 15
+#define MRX_FLT_TB8_MSK 0x00007fff
+#define MRX_FLT_TB8_I_MSK 0xffff8000
+#define MRX_FLT_TB8_SFT 0
+#define MRX_FLT_TB8_HI 14
+#define MRX_FLT_TB8_SZ 15
+#define MRX_FLT_TB9_MSK 0x00007fff
+#define MRX_FLT_TB9_I_MSK 0xffff8000
+#define MRX_FLT_TB9_SFT 0
+#define MRX_FLT_TB9_HI 14
+#define MRX_FLT_TB9_SZ 15
+#define MRX_FLT_TB10_MSK 0x00007fff
+#define MRX_FLT_TB10_I_MSK 0xffff8000
+#define MRX_FLT_TB10_SFT 0
+#define MRX_FLT_TB10_HI 14
+#define MRX_FLT_TB10_SZ 15
+#define MRX_FLT_TB11_MSK 0x00007fff
+#define MRX_FLT_TB11_I_MSK 0xffff8000
+#define MRX_FLT_TB11_SFT 0
+#define MRX_FLT_TB11_HI 14
+#define MRX_FLT_TB11_SZ 15
+#define MRX_FLT_TB12_MSK 0x00007fff
+#define MRX_FLT_TB12_I_MSK 0xffff8000
+#define MRX_FLT_TB12_SFT 0
+#define MRX_FLT_TB12_HI 14
+#define MRX_FLT_TB12_SZ 15
+#define MRX_FLT_TB13_MSK 0x00007fff
+#define MRX_FLT_TB13_I_MSK 0xffff8000
+#define MRX_FLT_TB13_SFT 0
+#define MRX_FLT_TB13_HI 14
+#define MRX_FLT_TB13_SZ 15
+#define MRX_FLT_TB14_MSK 0x00007fff
+#define MRX_FLT_TB14_I_MSK 0xffff8000
+#define MRX_FLT_TB14_SFT 0
+#define MRX_FLT_TB14_HI 14
+#define MRX_FLT_TB14_SZ 15
+#define MRX_FLT_TB15_MSK 0x00007fff
+#define MRX_FLT_TB15_I_MSK 0xffff8000
+#define MRX_FLT_TB15_SFT 0
+#define MRX_FLT_TB15_HI 14
+#define MRX_FLT_TB15_SZ 15
+#define MRX_FLT_EN0_MSK 0x0000ffff
+#define MRX_FLT_EN0_I_MSK 0xffff0000
+#define MRX_FLT_EN0_SFT 0
+#define MRX_FLT_EN0_HI 15
+#define MRX_FLT_EN0_SZ 16
+#define MRX_FLT_EN1_MSK 0x0000ffff
+#define MRX_FLT_EN1_I_MSK 0xffff0000
+#define MRX_FLT_EN1_SFT 0
+#define MRX_FLT_EN1_HI 15
+#define MRX_FLT_EN1_SZ 16
+#define MRX_FLT_EN2_MSK 0x0000ffff
+#define MRX_FLT_EN2_I_MSK 0xffff0000
+#define MRX_FLT_EN2_SFT 0
+#define MRX_FLT_EN2_HI 15
+#define MRX_FLT_EN2_SZ 16
+#define MRX_FLT_EN3_MSK 0x0000ffff
+#define MRX_FLT_EN3_I_MSK 0xffff0000
+#define MRX_FLT_EN3_SFT 0
+#define MRX_FLT_EN3_HI 15
+#define MRX_FLT_EN3_SZ 16
+#define MRX_FLT_EN4_MSK 0x0000ffff
+#define MRX_FLT_EN4_I_MSK 0xffff0000
+#define MRX_FLT_EN4_SFT 0
+#define MRX_FLT_EN4_HI 15
+#define MRX_FLT_EN4_SZ 16
+#define MRX_FLT_EN5_MSK 0x0000ffff
+#define MRX_FLT_EN5_I_MSK 0xffff0000
+#define MRX_FLT_EN5_SFT 0
+#define MRX_FLT_EN5_HI 15
+#define MRX_FLT_EN5_SZ 16
+#define MRX_FLT_EN6_MSK 0x0000ffff
+#define MRX_FLT_EN6_I_MSK 0xffff0000
+#define MRX_FLT_EN6_SFT 0
+#define MRX_FLT_EN6_HI 15
+#define MRX_FLT_EN6_SZ 16
+#define MRX_FLT_EN7_MSK 0x0000ffff
+#define MRX_FLT_EN7_I_MSK 0xffff0000
+#define MRX_FLT_EN7_SFT 0
+#define MRX_FLT_EN7_HI 15
+#define MRX_FLT_EN7_SZ 16
+#define MRX_FLT_EN8_MSK 0x0000ffff
+#define MRX_FLT_EN8_I_MSK 0xffff0000
+#define MRX_FLT_EN8_SFT 0
+#define MRX_FLT_EN8_HI 15
+#define MRX_FLT_EN8_SZ 16
+#define MRX_LEN_FLT_MSK 0x0000ffff
+#define MRX_LEN_FLT_I_MSK 0xffff0000
+#define MRX_LEN_FLT_SFT 0
+#define MRX_LEN_FLT_HI 15
+#define MRX_LEN_FLT_SZ 16
+#define RX_FLOW_DATA_MSK 0xffffffff
+#define RX_FLOW_DATA_I_MSK 0x00000000
+#define RX_FLOW_DATA_SFT 0
+#define RX_FLOW_DATA_HI 31
+#define RX_FLOW_DATA_SZ 32
+#define RX_FLOW_MNG_MSK 0x0000ffff
+#define RX_FLOW_MNG_I_MSK 0xffff0000
+#define RX_FLOW_MNG_SFT 0
+#define RX_FLOW_MNG_HI 15
+#define RX_FLOW_MNG_SZ 16
+#define RX_FLOW_CTRL_MSK 0x0000ffff
+#define RX_FLOW_CTRL_I_MSK 0xffff0000
+#define RX_FLOW_CTRL_SFT 0
+#define RX_FLOW_CTRL_HI 15
+#define RX_FLOW_CTRL_SZ 16
+#define MRX_STP_EN_MSK 0x00000001
+#define MRX_STP_EN_I_MSK 0xfffffffe
+#define MRX_STP_EN_SFT 0
+#define MRX_STP_EN_HI 0
+#define MRX_STP_EN_SZ 1
+#define MRX_STP_OFST_MSK 0x0000ff00
+#define MRX_STP_OFST_I_MSK 0xffff00ff
+#define MRX_STP_OFST_SFT 8
+#define MRX_STP_OFST_HI 15
+#define MRX_STP_OFST_SZ 8
+#define DBG_FF_FULL_MSK 0x0000ffff
+#define DBG_FF_FULL_I_MSK 0xffff0000
+#define DBG_FF_FULL_SFT 0
+#define DBG_FF_FULL_HI 15
+#define DBG_FF_FULL_SZ 16
+#define DBG_FF_FULL_CLR_MSK 0x80000000
+#define DBG_FF_FULL_CLR_I_MSK 0x7fffffff
+#define DBG_FF_FULL_CLR_SFT 31
+#define DBG_FF_FULL_CLR_HI 31
+#define DBG_FF_FULL_CLR_SZ 1
+#define DBG_WFF_FULL_MSK 0x0000ffff
+#define DBG_WFF_FULL_I_MSK 0xffff0000
+#define DBG_WFF_FULL_SFT 0
+#define DBG_WFF_FULL_HI 15
+#define DBG_WFF_FULL_SZ 16
+#define DBG_WFF_FULL_CLR_MSK 0x80000000
+#define DBG_WFF_FULL_CLR_I_MSK 0x7fffffff
+#define DBG_WFF_FULL_CLR_SFT 31
+#define DBG_WFF_FULL_CLR_HI 31
+#define DBG_WFF_FULL_CLR_SZ 1
+#define DBG_MB_FULL_MSK 0x0000ffff
+#define DBG_MB_FULL_I_MSK 0xffff0000
+#define DBG_MB_FULL_SFT 0
+#define DBG_MB_FULL_HI 15
+#define DBG_MB_FULL_SZ 16
+#define DBG_MB_FULL_CLR_MSK 0x80000000
+#define DBG_MB_FULL_CLR_I_MSK 0x7fffffff
+#define DBG_MB_FULL_CLR_SFT 31
+#define DBG_MB_FULL_CLR_HI 31
+#define DBG_MB_FULL_CLR_SZ 1
+#define BA_CTRL_MSK 0x00000003
+#define BA_CTRL_I_MSK 0xfffffffc
+#define BA_CTRL_SFT 0
+#define BA_CTRL_HI 1
+#define BA_CTRL_SZ 2
+#define BA_DBG_EN_MSK 0x00000004
+#define BA_DBG_EN_I_MSK 0xfffffffb
+#define BA_DBG_EN_SFT 2
+#define BA_DBG_EN_HI 2
+#define BA_DBG_EN_SZ 1
+#define BA_AGRE_EN_MSK 0x00000008
+#define BA_AGRE_EN_I_MSK 0xfffffff7
+#define BA_AGRE_EN_SFT 3
+#define BA_AGRE_EN_HI 3
+#define BA_AGRE_EN_SZ 1
+#define BA_TA_31_0_MSK 0xffffffff
+#define BA_TA_31_0_I_MSK 0x00000000
+#define BA_TA_31_0_SFT 0
+#define BA_TA_31_0_HI 31
+#define BA_TA_31_0_SZ 32
+#define BA_TA_47_32_MSK 0x0000ffff
+#define BA_TA_47_32_I_MSK 0xffff0000
+#define BA_TA_47_32_SFT 0
+#define BA_TA_47_32_HI 15
+#define BA_TA_47_32_SZ 16
+#define BA_TID_MSK 0x0000000f
+#define BA_TID_I_MSK 0xfffffff0
+#define BA_TID_SFT 0
+#define BA_TID_HI 3
+#define BA_TID_SZ 4
+#define BA_ST_SEQ_MSK 0x00000fff
+#define BA_ST_SEQ_I_MSK 0xfffff000
+#define BA_ST_SEQ_SFT 0
+#define BA_ST_SEQ_HI 11
+#define BA_ST_SEQ_SZ 12
+#define BA_SB0_MSK 0xffffffff
+#define BA_SB0_I_MSK 0x00000000
+#define BA_SB0_SFT 0
+#define BA_SB0_HI 31
+#define BA_SB0_SZ 32
+#define BA_SB1_MSK 0xffffffff
+#define BA_SB1_I_MSK 0x00000000
+#define BA_SB1_SFT 0
+#define BA_SB1_HI 31
+#define BA_SB1_SZ 32
+#define MRX_WD_MSK 0x0001ffff
+#define MRX_WD_I_MSK 0xfffe0000
+#define MRX_WD_SFT 0
+#define MRX_WD_HI 16
+#define MRX_WD_SZ 17
+#define ACK_GEN_EN_MSK 0x00000001
+#define ACK_GEN_EN_I_MSK 0xfffffffe
+#define ACK_GEN_EN_SFT 0
+#define ACK_GEN_EN_HI 0
+#define ACK_GEN_EN_SZ 1
+#define BA_GEN_EN_MSK 0x00000002
+#define BA_GEN_EN_I_MSK 0xfffffffd
+#define BA_GEN_EN_SFT 1
+#define BA_GEN_EN_HI 1
+#define BA_GEN_EN_SZ 1
+#define ACK_GEN_DUR_MSK 0x0000ffff
+#define ACK_GEN_DUR_I_MSK 0xffff0000
+#define ACK_GEN_DUR_SFT 0
+#define ACK_GEN_DUR_HI 15
+#define ACK_GEN_DUR_SZ 16
+#define ACK_GEN_INFO_MSK 0x003f0000
+#define ACK_GEN_INFO_I_MSK 0xffc0ffff
+#define ACK_GEN_INFO_SFT 16
+#define ACK_GEN_INFO_HI 21
+#define ACK_GEN_INFO_SZ 6
+#define ACK_GEN_RA_31_0_MSK 0xffffffff
+#define ACK_GEN_RA_31_0_I_MSK 0x00000000
+#define ACK_GEN_RA_31_0_SFT 0
+#define ACK_GEN_RA_31_0_HI 31
+#define ACK_GEN_RA_31_0_SZ 32
+#define ACK_GEN_RA_47_32_MSK 0x0000ffff
+#define ACK_GEN_RA_47_32_I_MSK 0xffff0000
+#define ACK_GEN_RA_47_32_SFT 0
+#define ACK_GEN_RA_47_32_HI 15
+#define ACK_GEN_RA_47_32_SZ 16
+#define MIB_LEN_FAIL_MSK 0x0000ffff
+#define MIB_LEN_FAIL_I_MSK 0xffff0000
+#define MIB_LEN_FAIL_SFT 0
+#define MIB_LEN_FAIL_HI 15
+#define MIB_LEN_FAIL_SZ 16
+#define TRAP_HW_ID_MSK 0x0000000f
+#define TRAP_HW_ID_I_MSK 0xfffffff0
+#define TRAP_HW_ID_SFT 0
+#define TRAP_HW_ID_HI 3
+#define TRAP_HW_ID_SZ 4
+#define ID_IN_USE_MSK 0x000000ff
+#define ID_IN_USE_I_MSK 0xffffff00
+#define ID_IN_USE_SFT 0
+#define ID_IN_USE_HI 7
+#define ID_IN_USE_SZ 8
+#define MRX_ERR_MSK 0xffffffff
+#define MRX_ERR_I_MSK 0x00000000
+#define MRX_ERR_SFT 0
+#define MRX_ERR_HI 31
+#define MRX_ERR_SZ 32
+#define W0_T0_SEQ_MSK 0x0000ffff
+#define W0_T0_SEQ_I_MSK 0xffff0000
+#define W0_T0_SEQ_SFT 0
+#define W0_T0_SEQ_HI 15
+#define W0_T0_SEQ_SZ 16
+#define W0_T1_SEQ_MSK 0x0000ffff
+#define W0_T1_SEQ_I_MSK 0xffff0000
+#define W0_T1_SEQ_SFT 0
+#define W0_T1_SEQ_HI 15
+#define W0_T1_SEQ_SZ 16
+#define W0_T2_SEQ_MSK 0x0000ffff
+#define W0_T2_SEQ_I_MSK 0xffff0000
+#define W0_T2_SEQ_SFT 0
+#define W0_T2_SEQ_HI 15
+#define W0_T2_SEQ_SZ 16
+#define W0_T3_SEQ_MSK 0x0000ffff
+#define W0_T3_SEQ_I_MSK 0xffff0000
+#define W0_T3_SEQ_SFT 0
+#define W0_T3_SEQ_HI 15
+#define W0_T3_SEQ_SZ 16
+#define W0_T4_SEQ_MSK 0x0000ffff
+#define W0_T4_SEQ_I_MSK 0xffff0000
+#define W0_T4_SEQ_SFT 0
+#define W0_T4_SEQ_HI 15
+#define W0_T4_SEQ_SZ 16
+#define W0_T5_SEQ_MSK 0x0000ffff
+#define W0_T5_SEQ_I_MSK 0xffff0000
+#define W0_T5_SEQ_SFT 0
+#define W0_T5_SEQ_HI 15
+#define W0_T5_SEQ_SZ 16
+#define W0_T6_SEQ_MSK 0x0000ffff
+#define W0_T6_SEQ_I_MSK 0xffff0000
+#define W0_T6_SEQ_SFT 0
+#define W0_T6_SEQ_HI 15
+#define W0_T6_SEQ_SZ 16
+#define W0_T7_SEQ_MSK 0x0000ffff
+#define W0_T7_SEQ_I_MSK 0xffff0000
+#define W0_T7_SEQ_SFT 0
+#define W0_T7_SEQ_HI 15
+#define W0_T7_SEQ_SZ 16
+#define W1_T0_SEQ_MSK 0x0000ffff
+#define W1_T0_SEQ_I_MSK 0xffff0000
+#define W1_T0_SEQ_SFT 0
+#define W1_T0_SEQ_HI 15
+#define W1_T0_SEQ_SZ 16
+#define W1_T1_SEQ_MSK 0x0000ffff
+#define W1_T1_SEQ_I_MSK 0xffff0000
+#define W1_T1_SEQ_SFT 0
+#define W1_T1_SEQ_HI 15
+#define W1_T1_SEQ_SZ 16
+#define W1_T2_SEQ_MSK 0x0000ffff
+#define W1_T2_SEQ_I_MSK 0xffff0000
+#define W1_T2_SEQ_SFT 0
+#define W1_T2_SEQ_HI 15
+#define W1_T2_SEQ_SZ 16
+#define W1_T3_SEQ_MSK 0x0000ffff
+#define W1_T3_SEQ_I_MSK 0xffff0000
+#define W1_T3_SEQ_SFT 0
+#define W1_T3_SEQ_HI 15
+#define W1_T3_SEQ_SZ 16
+#define W1_T4_SEQ_MSK 0x0000ffff
+#define W1_T4_SEQ_I_MSK 0xffff0000
+#define W1_T4_SEQ_SFT 0
+#define W1_T4_SEQ_HI 15
+#define W1_T4_SEQ_SZ 16
+#define W1_T5_SEQ_MSK 0x0000ffff
+#define W1_T5_SEQ_I_MSK 0xffff0000
+#define W1_T5_SEQ_SFT 0
+#define W1_T5_SEQ_HI 15
+#define W1_T5_SEQ_SZ 16
+#define W1_T6_SEQ_MSK 0x0000ffff
+#define W1_T6_SEQ_I_MSK 0xffff0000
+#define W1_T6_SEQ_SFT 0
+#define W1_T6_SEQ_HI 15
+#define W1_T6_SEQ_SZ 16
+#define W1_T7_SEQ_MSK 0x0000ffff
+#define W1_T7_SEQ_I_MSK 0xffff0000
+#define W1_T7_SEQ_SFT 0
+#define W1_T7_SEQ_HI 15
+#define W1_T7_SEQ_SZ 16
+#define ADDR1A_SEL_MSK 0x00000003
+#define ADDR1A_SEL_I_MSK 0xfffffffc
+#define ADDR1A_SEL_SFT 0
+#define ADDR1A_SEL_HI 1
+#define ADDR1A_SEL_SZ 2
+#define ADDR2A_SEL_MSK 0x0000000c
+#define ADDR2A_SEL_I_MSK 0xfffffff3
+#define ADDR2A_SEL_SFT 2
+#define ADDR2A_SEL_HI 3
+#define ADDR2A_SEL_SZ 2
+#define ADDR3A_SEL_MSK 0x00000030
+#define ADDR3A_SEL_I_MSK 0xffffffcf
+#define ADDR3A_SEL_SFT 4
+#define ADDR3A_SEL_HI 5
+#define ADDR3A_SEL_SZ 2
+#define ADDR1B_SEL_MSK 0x000000c0
+#define ADDR1B_SEL_I_MSK 0xffffff3f
+#define ADDR1B_SEL_SFT 6
+#define ADDR1B_SEL_HI 7
+#define ADDR1B_SEL_SZ 2
+#define ADDR2B_SEL_MSK 0x00000300
+#define ADDR2B_SEL_I_MSK 0xfffffcff
+#define ADDR2B_SEL_SFT 8
+#define ADDR2B_SEL_HI 9
+#define ADDR2B_SEL_SZ 2
+#define ADDR3B_SEL_MSK 0x00000c00
+#define ADDR3B_SEL_I_MSK 0xfffff3ff
+#define ADDR3B_SEL_SFT 10
+#define ADDR3B_SEL_HI 11
+#define ADDR3B_SEL_SZ 2
+#define ADDR3C_SEL_MSK 0x00003000
+#define ADDR3C_SEL_I_MSK 0xffffcfff
+#define ADDR3C_SEL_SFT 12
+#define ADDR3C_SEL_HI 13
+#define ADDR3C_SEL_SZ 2
+#define FRM_CTRL_MSK 0x0000003f
+#define FRM_CTRL_I_MSK 0xffffffc0
+#define FRM_CTRL_SFT 0
+#define FRM_CTRL_HI 5
+#define FRM_CTRL_SZ 6
+#define CSR_PHY_INFO_MSK 0x00007fff
+#define CSR_PHY_INFO_I_MSK 0xffff8000
+#define CSR_PHY_INFO_SFT 0
+#define CSR_PHY_INFO_HI 14
+#define CSR_PHY_INFO_SZ 15
+#define AMPDU_SIG_MSK 0x000000ff
+#define AMPDU_SIG_I_MSK 0xffffff00
+#define AMPDU_SIG_SFT 0
+#define AMPDU_SIG_HI 7
+#define AMPDU_SIG_SZ 8
+#define MIB_AMPDU_MSK 0xffffffff
+#define MIB_AMPDU_I_MSK 0x00000000
+#define MIB_AMPDU_SFT 0
+#define MIB_AMPDU_HI 31
+#define MIB_AMPDU_SZ 32
+#define LEN_FLT_MSK 0x0000ffff
+#define LEN_FLT_I_MSK 0xffff0000
+#define LEN_FLT_SFT 0
+#define LEN_FLT_HI 15
+#define LEN_FLT_SZ 16
+#define MIB_DELIMITER_MSK 0x0000ffff
+#define MIB_DELIMITER_I_MSK 0xffff0000
+#define MIB_DELIMITER_SFT 0
+#define MIB_DELIMITER_HI 15
+#define MIB_DELIMITER_SZ 16
+#define MTX_INT_Q0_Q_EMPTY_MSK 0x00010000
+#define MTX_INT_Q0_Q_EMPTY_I_MSK 0xfffeffff
+#define MTX_INT_Q0_Q_EMPTY_SFT 16
+#define MTX_INT_Q0_Q_EMPTY_HI 16
+#define MTX_INT_Q0_Q_EMPTY_SZ 1
+#define MTX_INT_Q0_TXOP_RUNOUT_MSK 0x00020000
+#define MTX_INT_Q0_TXOP_RUNOUT_I_MSK 0xfffdffff
+#define MTX_INT_Q0_TXOP_RUNOUT_SFT 17
+#define MTX_INT_Q0_TXOP_RUNOUT_HI 17
+#define MTX_INT_Q0_TXOP_RUNOUT_SZ 1
+#define MTX_INT_Q1_Q_EMPTY_MSK 0x00040000
+#define MTX_INT_Q1_Q_EMPTY_I_MSK 0xfffbffff
+#define MTX_INT_Q1_Q_EMPTY_SFT 18
+#define MTX_INT_Q1_Q_EMPTY_HI 18
+#define MTX_INT_Q1_Q_EMPTY_SZ 1
+#define MTX_INT_Q1_TXOP_RUNOUT_MSK 0x00080000
+#define MTX_INT_Q1_TXOP_RUNOUT_I_MSK 0xfff7ffff
+#define MTX_INT_Q1_TXOP_RUNOUT_SFT 19
+#define MTX_INT_Q1_TXOP_RUNOUT_HI 19
+#define MTX_INT_Q1_TXOP_RUNOUT_SZ 1
+#define MTX_INT_Q2_Q_EMPTY_MSK 0x00100000
+#define MTX_INT_Q2_Q_EMPTY_I_MSK 0xffefffff
+#define MTX_INT_Q2_Q_EMPTY_SFT 20
+#define MTX_INT_Q2_Q_EMPTY_HI 20
+#define MTX_INT_Q2_Q_EMPTY_SZ 1
+#define MTX_INT_Q2_TXOP_RUNOUT_MSK 0x00200000
+#define MTX_INT_Q2_TXOP_RUNOUT_I_MSK 0xffdfffff
+#define MTX_INT_Q2_TXOP_RUNOUT_SFT 21
+#define MTX_INT_Q2_TXOP_RUNOUT_HI 21
+#define MTX_INT_Q2_TXOP_RUNOUT_SZ 1
+#define MTX_INT_Q3_Q_EMPTY_MSK 0x00400000
+#define MTX_INT_Q3_Q_EMPTY_I_MSK 0xffbfffff
+#define MTX_INT_Q3_Q_EMPTY_SFT 22
+#define MTX_INT_Q3_Q_EMPTY_HI 22
+#define MTX_INT_Q3_Q_EMPTY_SZ 1
+#define MTX_INT_Q3_TXOP_RUNOUT_MSK 0x00800000
+#define MTX_INT_Q3_TXOP_RUNOUT_I_MSK 0xff7fffff
+#define MTX_INT_Q3_TXOP_RUNOUT_SFT 23
+#define MTX_INT_Q3_TXOP_RUNOUT_HI 23
+#define MTX_INT_Q3_TXOP_RUNOUT_SZ 1
+#define MTX_INT_Q4_Q_EMPTY_MSK 0x01000000
+#define MTX_INT_Q4_Q_EMPTY_I_MSK 0xfeffffff
+#define MTX_INT_Q4_Q_EMPTY_SFT 24
+#define MTX_INT_Q4_Q_EMPTY_HI 24
+#define MTX_INT_Q4_Q_EMPTY_SZ 1
+#define MTX_INT_Q4_TXOP_RUNOUT_MSK 0x02000000
+#define MTX_INT_Q4_TXOP_RUNOUT_I_MSK 0xfdffffff
+#define MTX_INT_Q4_TXOP_RUNOUT_SFT 25
+#define MTX_INT_Q4_TXOP_RUNOUT_HI 25
+#define MTX_INT_Q4_TXOP_RUNOUT_SZ 1
+#define MTX_EN_INT_Q0_Q_EMPTY_MSK 0x00010000
+#define MTX_EN_INT_Q0_Q_EMPTY_I_MSK 0xfffeffff
+#define MTX_EN_INT_Q0_Q_EMPTY_SFT 16
+#define MTX_EN_INT_Q0_Q_EMPTY_HI 16
+#define MTX_EN_INT_Q0_Q_EMPTY_SZ 1
+#define MTX_EN_INT_Q0_TXOP_RUNOUT_MSK 0x00020000
+#define MTX_EN_INT_Q0_TXOP_RUNOUT_I_MSK 0xfffdffff
+#define MTX_EN_INT_Q0_TXOP_RUNOUT_SFT 17
+#define MTX_EN_INT_Q0_TXOP_RUNOUT_HI 17
+#define MTX_EN_INT_Q0_TXOP_RUNOUT_SZ 1
+#define MTX_EN_INT_Q1_Q_EMPTY_MSK 0x00040000
+#define MTX_EN_INT_Q1_Q_EMPTY_I_MSK 0xfffbffff
+#define MTX_EN_INT_Q1_Q_EMPTY_SFT 18
+#define MTX_EN_INT_Q1_Q_EMPTY_HI 18
+#define MTX_EN_INT_Q1_Q_EMPTY_SZ 1
+#define MTX_EN_INT_Q1_TXOP_RUNOUT_MSK 0x00080000
+#define MTX_EN_INT_Q1_TXOP_RUNOUT_I_MSK 0xfff7ffff
+#define MTX_EN_INT_Q1_TXOP_RUNOUT_SFT 19
+#define MTX_EN_INT_Q1_TXOP_RUNOUT_HI 19
+#define MTX_EN_INT_Q1_TXOP_RUNOUT_SZ 1
+#define MTX_EN_INT_Q2_Q_EMPTY_MSK 0x00100000
+#define MTX_EN_INT_Q2_Q_EMPTY_I_MSK 0xffefffff
+#define MTX_EN_INT_Q2_Q_EMPTY_SFT 20
+#define MTX_EN_INT_Q2_Q_EMPTY_HI 20
+#define MTX_EN_INT_Q2_Q_EMPTY_SZ 1
+#define MTX_EN_INT_Q2_TXOP_RUNOUT_MSK 0x00200000
+#define MTX_EN_INT_Q2_TXOP_RUNOUT_I_MSK 0xffdfffff
+#define MTX_EN_INT_Q2_TXOP_RUNOUT_SFT 21
+#define MTX_EN_INT_Q2_TXOP_RUNOUT_HI 21
+#define MTX_EN_INT_Q2_TXOP_RUNOUT_SZ 1
+#define MTX_EN_INT_Q3_Q_EMPTY_MSK 0x00400000
+#define MTX_EN_INT_Q3_Q_EMPTY_I_MSK 0xffbfffff
+#define MTX_EN_INT_Q3_Q_EMPTY_SFT 22
+#define MTX_EN_INT_Q3_Q_EMPTY_HI 22
+#define MTX_EN_INT_Q3_Q_EMPTY_SZ 1
+#define MTX_EN_INT_Q3_TXOP_RUNOUT_MSK 0x00800000
+#define MTX_EN_INT_Q3_TXOP_RUNOUT_I_MSK 0xff7fffff
+#define MTX_EN_INT_Q3_TXOP_RUNOUT_SFT 23
+#define MTX_EN_INT_Q3_TXOP_RUNOUT_HI 23
+#define MTX_EN_INT_Q3_TXOP_RUNOUT_SZ 1
+#define MTX_EN_INT_Q4_Q_EMPTY_MSK 0x01000000
+#define MTX_EN_INT_Q4_Q_EMPTY_I_MSK 0xfeffffff
+#define MTX_EN_INT_Q4_Q_EMPTY_SFT 24
+#define MTX_EN_INT_Q4_Q_EMPTY_HI 24
+#define MTX_EN_INT_Q4_Q_EMPTY_SZ 1
+#define MTX_EN_INT_Q4_TXOP_RUNOUT_MSK 0x02000000
+#define MTX_EN_INT_Q4_TXOP_RUNOUT_I_MSK 0xfdffffff
+#define MTX_EN_INT_Q4_TXOP_RUNOUT_SFT 25
+#define MTX_EN_INT_Q4_TXOP_RUNOUT_HI 25
+#define MTX_EN_INT_Q4_TXOP_RUNOUT_SZ 1
+#define MTX_MTX2PHY_SLOW_MSK 0x00000001
+#define MTX_MTX2PHY_SLOW_I_MSK 0xfffffffe
+#define MTX_MTX2PHY_SLOW_SFT 0
+#define MTX_MTX2PHY_SLOW_HI 0
+#define MTX_MTX2PHY_SLOW_SZ 1
+#define MTX_M2M_SLOW_PRD_MSK 0x0000000e
+#define MTX_M2M_SLOW_PRD_I_MSK 0xfffffff1
+#define MTX_M2M_SLOW_PRD_SFT 1
+#define MTX_M2M_SLOW_PRD_HI 3
+#define MTX_M2M_SLOW_PRD_SZ 3
+#define MTX_AMPDU_CRC_AUTO_MSK 0x00000020
+#define MTX_AMPDU_CRC_AUTO_I_MSK 0xffffffdf
+#define MTX_AMPDU_CRC_AUTO_SFT 5
+#define MTX_AMPDU_CRC_AUTO_HI 5
+#define MTX_AMPDU_CRC_AUTO_SZ 1
+#define MTX_FAST_RSP_MODE_MSK 0x00000040
+#define MTX_FAST_RSP_MODE_I_MSK 0xffffffbf
+#define MTX_FAST_RSP_MODE_SFT 6
+#define MTX_FAST_RSP_MODE_HI 6
+#define MTX_FAST_RSP_MODE_SZ 1
+#define MTX_RAW_DATA_MODE_MSK 0x00000080
+#define MTX_RAW_DATA_MODE_I_MSK 0xffffff7f
+#define MTX_RAW_DATA_MODE_SFT 7
+#define MTX_RAW_DATA_MODE_HI 7
+#define MTX_RAW_DATA_MODE_SZ 1
+#define MTX_ACK_DUR0_MSK 0x00000100
+#define MTX_ACK_DUR0_I_MSK 0xfffffeff
+#define MTX_ACK_DUR0_SFT 8
+#define MTX_ACK_DUR0_HI 8
+#define MTX_ACK_DUR0_SZ 1
+#define MTX_TSF_AUTO_BCN_MSK 0x00000400
+#define MTX_TSF_AUTO_BCN_I_MSK 0xfffffbff
+#define MTX_TSF_AUTO_BCN_SFT 10
+#define MTX_TSF_AUTO_BCN_HI 10
+#define MTX_TSF_AUTO_BCN_SZ 1
+#define MTX_TSF_AUTO_MISC_MSK 0x00000800
+#define MTX_TSF_AUTO_MISC_I_MSK 0xfffff7ff
+#define MTX_TSF_AUTO_MISC_SFT 11
+#define MTX_TSF_AUTO_MISC_HI 11
+#define MTX_TSF_AUTO_MISC_SZ 1
+#define MTX_FORCE_CS_IDLE_MSK 0x00001000
+#define MTX_FORCE_CS_IDLE_I_MSK 0xffffefff
+#define MTX_FORCE_CS_IDLE_SFT 12
+#define MTX_FORCE_CS_IDLE_HI 12
+#define MTX_FORCE_CS_IDLE_SZ 1
+#define MTX_FORCE_BKF_RXEN0_MSK 0x00002000
+#define MTX_FORCE_BKF_RXEN0_I_MSK 0xffffdfff
+#define MTX_FORCE_BKF_RXEN0_SFT 13
+#define MTX_FORCE_BKF_RXEN0_HI 13
+#define MTX_FORCE_BKF_RXEN0_SZ 1
+#define MTX_FORCE_DMA_RXEN0_MSK 0x00004000
+#define MTX_FORCE_DMA_RXEN0_I_MSK 0xffffbfff
+#define MTX_FORCE_DMA_RXEN0_SFT 14
+#define MTX_FORCE_DMA_RXEN0_HI 14
+#define MTX_FORCE_DMA_RXEN0_SZ 1
+#define MTX_FORCE_RXEN0_MSK 0x00008000
+#define MTX_FORCE_RXEN0_I_MSK 0xffff7fff
+#define MTX_FORCE_RXEN0_SFT 15
+#define MTX_FORCE_RXEN0_HI 15
+#define MTX_FORCE_RXEN0_SZ 1
+#define MTX_HALT_Q_MB_MSK 0x003f0000
+#define MTX_HALT_Q_MB_I_MSK 0xffc0ffff
+#define MTX_HALT_Q_MB_SFT 16
+#define MTX_HALT_Q_MB_HI 21
+#define MTX_HALT_Q_MB_SZ 6
+#define MTX_CTS_SET_DIF_MSK 0x00400000
+#define MTX_CTS_SET_DIF_I_MSK 0xffbfffff
+#define MTX_CTS_SET_DIF_SFT 22
+#define MTX_CTS_SET_DIF_HI 22
+#define MTX_CTS_SET_DIF_SZ 1
+#define MTX_AMPDU_SET_DIF_MSK 0x00800000
+#define MTX_AMPDU_SET_DIF_I_MSK 0xff7fffff
+#define MTX_AMPDU_SET_DIF_SFT 23
+#define MTX_AMPDU_SET_DIF_HI 23
+#define MTX_AMPDU_SET_DIF_SZ 1
+#define MTX_EDCCA_TOUT_MSK 0x000003ff
+#define MTX_EDCCA_TOUT_I_MSK 0xfffffc00
+#define MTX_EDCCA_TOUT_SFT 0
+#define MTX_EDCCA_TOUT_HI 9
+#define MTX_EDCCA_TOUT_SZ 10
+#define MTX_INT_BCN_MSK 0x00000002
+#define MTX_INT_BCN_I_MSK 0xfffffffd
+#define MTX_INT_BCN_SFT 1
+#define MTX_INT_BCN_HI 1
+#define MTX_INT_BCN_SZ 1
+#define MTX_INT_DTIM_MSK 0x00000008
+#define MTX_INT_DTIM_I_MSK 0xfffffff7
+#define MTX_INT_DTIM_SFT 3
+#define MTX_INT_DTIM_HI 3
+#define MTX_INT_DTIM_SZ 1
+#define MTX_EN_INT_BCN_MSK 0x00000002
+#define MTX_EN_INT_BCN_I_MSK 0xfffffffd
+#define MTX_EN_INT_BCN_SFT 1
+#define MTX_EN_INT_BCN_HI 1
+#define MTX_EN_INT_BCN_SZ 1
+#define MTX_EN_INT_DTIM_MSK 0x00000008
+#define MTX_EN_INT_DTIM_I_MSK 0xfffffff7
+#define MTX_EN_INT_DTIM_SFT 3
+#define MTX_EN_INT_DTIM_HI 3
+#define MTX_EN_INT_DTIM_SZ 1
+#define MTX_BCN_TIMER_EN_MSK 0x00000001
+#define MTX_BCN_TIMER_EN_I_MSK 0xfffffffe
+#define MTX_BCN_TIMER_EN_SFT 0
+#define MTX_BCN_TIMER_EN_HI 0
+#define MTX_BCN_TIMER_EN_SZ 1
+#define MTX_TIME_STAMP_AUTO_FILL_MSK 0x00000002
+#define MTX_TIME_STAMP_AUTO_FILL_I_MSK 0xfffffffd
+#define MTX_TIME_STAMP_AUTO_FILL_SFT 1
+#define MTX_TIME_STAMP_AUTO_FILL_HI 1
+#define MTX_TIME_STAMP_AUTO_FILL_SZ 1
+#define MTX_TSF_TIMER_EN_MSK 0x00000020
+#define MTX_TSF_TIMER_EN_I_MSK 0xffffffdf
+#define MTX_TSF_TIMER_EN_SFT 5
+#define MTX_TSF_TIMER_EN_HI 5
+#define MTX_TSF_TIMER_EN_SZ 1
+#define MTX_HALT_MNG_UNTIL_DTIM_MSK 0x00000040
+#define MTX_HALT_MNG_UNTIL_DTIM_I_MSK 0xffffffbf
+#define MTX_HALT_MNG_UNTIL_DTIM_SFT 6
+#define MTX_HALT_MNG_UNTIL_DTIM_HI 6
+#define MTX_HALT_MNG_UNTIL_DTIM_SZ 1
+#define MTX_INT_DTIM_NUM_MSK 0x0000ff00
+#define MTX_INT_DTIM_NUM_I_MSK 0xffff00ff
+#define MTX_INT_DTIM_NUM_SFT 8
+#define MTX_INT_DTIM_NUM_HI 15
+#define MTX_INT_DTIM_NUM_SZ 8
+#define MTX_AUTO_FLUSH_Q4_MSK 0x00010000
+#define MTX_AUTO_FLUSH_Q4_I_MSK 0xfffeffff
+#define MTX_AUTO_FLUSH_Q4_SFT 16
+#define MTX_AUTO_FLUSH_Q4_HI 16
+#define MTX_AUTO_FLUSH_Q4_SZ 1
+#define MTX_BCN_PKTID_CH_LOCK_MSK 0x00000001
+#define MTX_BCN_PKTID_CH_LOCK_I_MSK 0xfffffffe
+#define MTX_BCN_PKTID_CH_LOCK_SFT 0
+#define MTX_BCN_PKTID_CH_LOCK_HI 0
+#define MTX_BCN_PKTID_CH_LOCK_SZ 1
+#define MTX_BCN_CFG_VLD_MSK 0x00000006
+#define MTX_BCN_CFG_VLD_I_MSK 0xfffffff9
+#define MTX_BCN_CFG_VLD_SFT 1
+#define MTX_BCN_CFG_VLD_HI 2
+#define MTX_BCN_CFG_VLD_SZ 2
+#define MTX_AUTO_BCN_ONGOING_MSK 0x00000008
+#define MTX_AUTO_BCN_ONGOING_I_MSK 0xfffffff7
+#define MTX_AUTO_BCN_ONGOING_SFT 3
+#define MTX_AUTO_BCN_ONGOING_HI 3
+#define MTX_AUTO_BCN_ONGOING_SZ 1
+#define MTX_BCN_TIMER_MSK 0xffff0000
+#define MTX_BCN_TIMER_I_MSK 0x0000ffff
+#define MTX_BCN_TIMER_SFT 16
+#define MTX_BCN_TIMER_HI 31
+#define MTX_BCN_TIMER_SZ 16
+#define MTX_BCN_PERIOD_MSK 0x0000ffff
+#define MTX_BCN_PERIOD_I_MSK 0xffff0000
+#define MTX_BCN_PERIOD_SFT 0
+#define MTX_BCN_PERIOD_HI 15
+#define MTX_BCN_PERIOD_SZ 16
+#define MTX_DTIM_NUM_MSK 0xff000000
+#define MTX_DTIM_NUM_I_MSK 0x00ffffff
+#define MTX_DTIM_NUM_SFT 24
+#define MTX_DTIM_NUM_HI 31
+#define MTX_DTIM_NUM_SZ 8
+#define MTX_BCN_TSF_L_MSK 0xffffffff
+#define MTX_BCN_TSF_L_I_MSK 0x00000000
+#define MTX_BCN_TSF_L_SFT 0
+#define MTX_BCN_TSF_L_HI 31
+#define MTX_BCN_TSF_L_SZ 32
+#define MTX_BCN_TSF_U_MSK 0xffffffff
+#define MTX_BCN_TSF_U_I_MSK 0x00000000
+#define MTX_BCN_TSF_U_SFT 0
+#define MTX_BCN_TSF_U_HI 31
+#define MTX_BCN_TSF_U_SZ 32
+#define MTX_BCN_PKT_ID0_MSK 0x0000007f
+#define MTX_BCN_PKT_ID0_I_MSK 0xffffff80
+#define MTX_BCN_PKT_ID0_SFT 0
+#define MTX_BCN_PKT_ID0_HI 6
+#define MTX_BCN_PKT_ID0_SZ 7
+#define MTX_DTIM_OFST0_MSK 0x03ff0000
+#define MTX_DTIM_OFST0_I_MSK 0xfc00ffff
+#define MTX_DTIM_OFST0_SFT 16
+#define MTX_DTIM_OFST0_HI 25
+#define MTX_DTIM_OFST0_SZ 10
+#define MTX_BCN_PKT_ID1_MSK 0x0000007f
+#define MTX_BCN_PKT_ID1_I_MSK 0xffffff80
+#define MTX_BCN_PKT_ID1_SFT 0
+#define MTX_BCN_PKT_ID1_HI 6
+#define MTX_BCN_PKT_ID1_SZ 7
+#define MTX_DTIM_OFST1_MSK 0x03ff0000
+#define MTX_DTIM_OFST1_I_MSK 0xfc00ffff
+#define MTX_DTIM_OFST1_SFT 16
+#define MTX_DTIM_OFST1_HI 25
+#define MTX_DTIM_OFST1_SZ 10
+#define MTX_CCA_MSK 0x00000001
+#define MTX_CCA_I_MSK 0xfffffffe
+#define MTX_CCA_SFT 0
+#define MTX_CCA_HI 0
+#define MTX_CCA_SZ 1
+#define MRX_CCA_MSK 0x00000002
+#define MRX_CCA_I_MSK 0xfffffffd
+#define MRX_CCA_SFT 1
+#define MRX_CCA_HI 1
+#define MRX_CCA_SZ 1
+#define MTX_DMA_FSM_MSK 0x0000001c
+#define MTX_DMA_FSM_I_MSK 0xffffffe3
+#define MTX_DMA_FSM_SFT 2
+#define MTX_DMA_FSM_HI 4
+#define MTX_DMA_FSM_SZ 3
+#define CH_ST_FSM_MSK 0x000000e0
+#define CH_ST_FSM_I_MSK 0xffffff1f
+#define CH_ST_FSM_SFT 5
+#define CH_ST_FSM_HI 7
+#define CH_ST_FSM_SZ 3
+#define MTX_GNT_LOCK_MSK 0x00000100
+#define MTX_GNT_LOCK_I_MSK 0xfffffeff
+#define MTX_GNT_LOCK_SFT 8
+#define MTX_GNT_LOCK_HI 8
+#define MTX_GNT_LOCK_SZ 1
+#define MTX_DMA_REQ_MSK 0x00000200
+#define MTX_DMA_REQ_I_MSK 0xfffffdff
+#define MTX_DMA_REQ_SFT 9
+#define MTX_DMA_REQ_HI 9
+#define MTX_DMA_REQ_SZ 1
+#define MTX_Q_REQ_MSK 0x00000400
+#define MTX_Q_REQ_I_MSK 0xfffffbff
+#define MTX_Q_REQ_SFT 10
+#define MTX_Q_REQ_HI 10
+#define MTX_Q_REQ_SZ 1
+#define MTX_TX_EN_MSK 0x00000800
+#define MTX_TX_EN_I_MSK 0xfffff7ff
+#define MTX_TX_EN_SFT 11
+#define MTX_TX_EN_HI 11
+#define MTX_TX_EN_SZ 1
+#define MRX_RX_EN_MSK 0x00001000
+#define MRX_RX_EN_I_MSK 0xffffefff
+#define MRX_RX_EN_SFT 12
+#define MRX_RX_EN_HI 12
+#define MRX_RX_EN_SZ 1
+#define DBG_PRTC_PRD_MSK 0x00002000
+#define DBG_PRTC_PRD_I_MSK 0xffffdfff
+#define DBG_PRTC_PRD_SFT 13
+#define DBG_PRTC_PRD_HI 13
+#define DBG_PRTC_PRD_SZ 1
+#define DBG_DMA_RDY_MSK 0x00004000
+#define DBG_DMA_RDY_I_MSK 0xffffbfff
+#define DBG_DMA_RDY_SFT 14
+#define DBG_DMA_RDY_HI 14
+#define DBG_DMA_RDY_SZ 1
+#define DBG_WAIT_RSP_MSK 0x00008000
+#define DBG_WAIT_RSP_I_MSK 0xffff7fff
+#define DBG_WAIT_RSP_SFT 15
+#define DBG_WAIT_RSP_HI 15
+#define DBG_WAIT_RSP_SZ 1
+#define DBG_CFRM_BUSY_MSK 0x00010000
+#define DBG_CFRM_BUSY_I_MSK 0xfffeffff
+#define DBG_CFRM_BUSY_SFT 16
+#define DBG_CFRM_BUSY_HI 16
+#define DBG_CFRM_BUSY_SZ 1
+#define DBG_RST_MSK 0x00000001
+#define DBG_RST_I_MSK 0xfffffffe
+#define DBG_RST_SFT 0
+#define DBG_RST_HI 0
+#define DBG_RST_SZ 1
+#define DBG_MODE_MSK 0x00000002
+#define DBG_MODE_I_MSK 0xfffffffd
+#define DBG_MODE_SFT 1
+#define DBG_MODE_HI 1
+#define DBG_MODE_SZ 1
+#define MB_REQ_DUR_MSK 0x0000ffff
+#define MB_REQ_DUR_I_MSK 0xffff0000
+#define MB_REQ_DUR_SFT 0
+#define MB_REQ_DUR_HI 15
+#define MB_REQ_DUR_SZ 16
+#define RX_EN_DUR_MSK 0xffff0000
+#define RX_EN_DUR_I_MSK 0x0000ffff
+#define RX_EN_DUR_SFT 16
+#define RX_EN_DUR_HI 31
+#define RX_EN_DUR_SZ 16
+#define RX_CS_DUR_MSK 0x0000ffff
+#define RX_CS_DUR_I_MSK 0xffff0000
+#define RX_CS_DUR_SFT 0
+#define RX_CS_DUR_HI 15
+#define RX_CS_DUR_SZ 16
+#define TX_CCA_DUR_MSK 0xffff0000
+#define TX_CCA_DUR_I_MSK 0x0000ffff
+#define TX_CCA_DUR_SFT 16
+#define TX_CCA_DUR_HI 31
+#define TX_CCA_DUR_SZ 16
+#define Q_REQ_DUR_MSK 0x0000ffff
+#define Q_REQ_DUR_I_MSK 0xffff0000
+#define Q_REQ_DUR_SFT 0
+#define Q_REQ_DUR_HI 15
+#define Q_REQ_DUR_SZ 16
+#define CH_STA0_DUR_MSK 0xffff0000
+#define CH_STA0_DUR_I_MSK 0x0000ffff
+#define CH_STA0_DUR_SFT 16
+#define CH_STA0_DUR_HI 31
+#define CH_STA0_DUR_SZ 16
+#define MTX_DUR_RSP_TOUT_B_MSK 0x000000ff
+#define MTX_DUR_RSP_TOUT_B_I_MSK 0xffffff00
+#define MTX_DUR_RSP_TOUT_B_SFT 0
+#define MTX_DUR_RSP_TOUT_B_HI 7
+#define MTX_DUR_RSP_TOUT_B_SZ 8
+#define MTX_DUR_RSP_TOUT_G_MSK 0x0000ff00
+#define MTX_DUR_RSP_TOUT_G_I_MSK 0xffff00ff
+#define MTX_DUR_RSP_TOUT_G_SFT 8
+#define MTX_DUR_RSP_TOUT_G_HI 15
+#define MTX_DUR_RSP_TOUT_G_SZ 8
+#define MTX_DUR_RSP_SIFS_MSK 0x000000ff
+#define MTX_DUR_RSP_SIFS_I_MSK 0xffffff00
+#define MTX_DUR_RSP_SIFS_SFT 0
+#define MTX_DUR_RSP_SIFS_HI 7
+#define MTX_DUR_RSP_SIFS_SZ 8
+#define MTX_DUR_BURST_SIFS_MSK 0x0000ff00
+#define MTX_DUR_BURST_SIFS_I_MSK 0xffff00ff
+#define MTX_DUR_BURST_SIFS_SFT 8
+#define MTX_DUR_BURST_SIFS_HI 15
+#define MTX_DUR_BURST_SIFS_SZ 8
+#define MTX_DUR_SLOT_MSK 0x003f0000
+#define MTX_DUR_SLOT_I_MSK 0xffc0ffff
+#define MTX_DUR_SLOT_SFT 16
+#define MTX_DUR_SLOT_HI 21
+#define MTX_DUR_SLOT_SZ 6
+#define MTX_DUR_RSP_EIFS_MSK 0xffc00000
+#define MTX_DUR_RSP_EIFS_I_MSK 0x003fffff
+#define MTX_DUR_RSP_EIFS_SFT 22
+#define MTX_DUR_RSP_EIFS_HI 31
+#define MTX_DUR_RSP_EIFS_SZ 10
+#define MTX_DUR_RSP_SIFS_G_MSK 0x000000ff
+#define MTX_DUR_RSP_SIFS_G_I_MSK 0xffffff00
+#define MTX_DUR_RSP_SIFS_G_SFT 0
+#define MTX_DUR_RSP_SIFS_G_HI 7
+#define MTX_DUR_RSP_SIFS_G_SZ 8
+#define MTX_DUR_BURST_SIFS_G_MSK 0x0000ff00
+#define MTX_DUR_BURST_SIFS_G_I_MSK 0xffff00ff
+#define MTX_DUR_BURST_SIFS_G_SFT 8
+#define MTX_DUR_BURST_SIFS_G_HI 15
+#define MTX_DUR_BURST_SIFS_G_SZ 8
+#define MTX_DUR_SLOT_G_MSK 0x003f0000
+#define MTX_DUR_SLOT_G_I_MSK 0xffc0ffff
+#define MTX_DUR_SLOT_G_SFT 16
+#define MTX_DUR_SLOT_G_HI 21
+#define MTX_DUR_SLOT_G_SZ 6
+#define MTX_DUR_RSP_EIFS_G_MSK 0xffc00000
+#define MTX_DUR_RSP_EIFS_G_I_MSK 0x003fffff
+#define MTX_DUR_RSP_EIFS_G_SFT 22
+#define MTX_DUR_RSP_EIFS_G_HI 31
+#define MTX_DUR_RSP_EIFS_G_SZ 10
+#define CH_STA1_DUR_MSK 0x0000ffff
+#define CH_STA1_DUR_I_MSK 0xffff0000
+#define CH_STA1_DUR_SFT 0
+#define CH_STA1_DUR_HI 15
+#define CH_STA1_DUR_SZ 16
+#define CH_STA2_DUR_MSK 0xffff0000
+#define CH_STA2_DUR_I_MSK 0x0000ffff
+#define CH_STA2_DUR_SFT 16
+#define CH_STA2_DUR_HI 31
+#define CH_STA2_DUR_SZ 16
+#define MTX_NAV_MSK 0x0000ffff
+#define MTX_NAV_I_MSK 0xffff0000
+#define MTX_NAV_SFT 0
+#define MTX_NAV_HI 15
+#define MTX_NAV_SZ 16
+#define MTX_MIB_CNT0_MSK 0x3fffffff
+#define MTX_MIB_CNT0_I_MSK 0xc0000000
+#define MTX_MIB_CNT0_SFT 0
+#define MTX_MIB_CNT0_HI 29
+#define MTX_MIB_CNT0_SZ 30
+#define MTX_MIB_EN0_MSK 0x40000000
+#define MTX_MIB_EN0_I_MSK 0xbfffffff
+#define MTX_MIB_EN0_SFT 30
+#define MTX_MIB_EN0_HI 30
+#define MTX_MIB_EN0_SZ 1
+#define MTX_MIB_CNT1_MSK 0x3fffffff
+#define MTX_MIB_CNT1_I_MSK 0xc0000000
+#define MTX_MIB_CNT1_SFT 0
+#define MTX_MIB_CNT1_HI 29
+#define MTX_MIB_CNT1_SZ 30
+#define MTX_MIB_EN1_MSK 0x40000000
+#define MTX_MIB_EN1_I_MSK 0xbfffffff
+#define MTX_MIB_EN1_SFT 30
+#define MTX_MIB_EN1_HI 30
+#define MTX_MIB_EN1_SZ 1
+#define CH_STA3_DUR_MSK 0x0000ffff
+#define CH_STA3_DUR_I_MSK 0xffff0000
+#define CH_STA3_DUR_SFT 0
+#define CH_STA3_DUR_HI 15
+#define CH_STA3_DUR_SZ 16
+#define CH_STA4_DUR_MSK 0xffff0000
+#define CH_STA4_DUR_I_MSK 0x0000ffff
+#define CH_STA4_DUR_SFT 16
+#define CH_STA4_DUR_HI 31
+#define CH_STA4_DUR_SZ 16
+#define TXQ0_MTX_Q_PRE_LD_MSK 0x00000002
+#define TXQ0_MTX_Q_PRE_LD_I_MSK 0xfffffffd
+#define TXQ0_MTX_Q_PRE_LD_SFT 1
+#define TXQ0_MTX_Q_PRE_LD_HI 1
+#define TXQ0_MTX_Q_PRE_LD_SZ 1
+#define TXQ0_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004
+#define TXQ0_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb
+#define TXQ0_MTX_Q_BKF_CNT_FIXED_SFT 2
+#define TXQ0_MTX_Q_BKF_CNT_FIXED_HI 2
+#define TXQ0_MTX_Q_BKF_CNT_FIXED_SZ 1
+#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008
+#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7
+#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3
+#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_HI 3
+#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1
+#define TXQ0_MTX_Q_MB_NO_RLS_MSK 0x00000010
+#define TXQ0_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
+#define TXQ0_MTX_Q_MB_NO_RLS_SFT 4
+#define TXQ0_MTX_Q_MB_NO_RLS_HI 4
+#define TXQ0_MTX_Q_MB_NO_RLS_SZ 1
+#define TXQ0_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020
+#define TXQ0_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf
+#define TXQ0_MTX_Q_TXOP_FRC_BUR_SFT 5
+#define TXQ0_MTX_Q_TXOP_FRC_BUR_HI 5
+#define TXQ0_MTX_Q_TXOP_FRC_BUR_SZ 1
+#define TXQ0_MTX_Q_RND_MODE_MSK 0x000000c0
+#define TXQ0_MTX_Q_RND_MODE_I_MSK 0xffffff3f
+#define TXQ0_MTX_Q_RND_MODE_SFT 6
+#define TXQ0_MTX_Q_RND_MODE_HI 7
+#define TXQ0_MTX_Q_RND_MODE_SZ 2
+#define TXQ0_MTX_Q_AIFSN_MSK 0x0000000f
+#define TXQ0_MTX_Q_AIFSN_I_MSK 0xfffffff0
+#define TXQ0_MTX_Q_AIFSN_SFT 0
+#define TXQ0_MTX_Q_AIFSN_HI 3
+#define TXQ0_MTX_Q_AIFSN_SZ 4
+#define TXQ0_MTX_Q_ECWMIN_MSK 0x00000f00
+#define TXQ0_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
+#define TXQ0_MTX_Q_ECWMIN_SFT 8
+#define TXQ0_MTX_Q_ECWMIN_HI 11
+#define TXQ0_MTX_Q_ECWMIN_SZ 4
+#define TXQ0_MTX_Q_ECWMAX_MSK 0x0000f000
+#define TXQ0_MTX_Q_ECWMAX_I_MSK 0xffff0fff
+#define TXQ0_MTX_Q_ECWMAX_SFT 12
+#define TXQ0_MTX_Q_ECWMAX_HI 15
+#define TXQ0_MTX_Q_ECWMAX_SZ 4
+#define TXQ0_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
+#define TXQ0_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
+#define TXQ0_MTX_Q_TXOP_LIMIT_SFT 16
+#define TXQ0_MTX_Q_TXOP_LIMIT_HI 31
+#define TXQ0_MTX_Q_TXOP_LIMIT_SZ 16
+#define TXQ0_MTX_Q_BKF_CNT_MSK 0x0000ffff
+#define TXQ0_MTX_Q_BKF_CNT_I_MSK 0xffff0000
+#define TXQ0_MTX_Q_BKF_CNT_SFT 0
+#define TXQ0_MTX_Q_BKF_CNT_HI 15
+#define TXQ0_MTX_Q_BKF_CNT_SZ 16
+#define TXQ0_MTX_Q_SRC_LIMIT_MSK 0x000000ff
+#define TXQ0_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00
+#define TXQ0_MTX_Q_SRC_LIMIT_SFT 0
+#define TXQ0_MTX_Q_SRC_LIMIT_HI 7
+#define TXQ0_MTX_Q_SRC_LIMIT_SZ 8
+#define TXQ0_MTX_Q_LRC_LIMIT_MSK 0x0000ff00
+#define TXQ0_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff
+#define TXQ0_MTX_Q_LRC_LIMIT_SFT 8
+#define TXQ0_MTX_Q_LRC_LIMIT_HI 15
+#define TXQ0_MTX_Q_LRC_LIMIT_SZ 8
+#define TXQ0_MTX_Q_ID_MAP_L_MSK 0xffffffff
+#define TXQ0_MTX_Q_ID_MAP_L_I_MSK 0x00000000
+#define TXQ0_MTX_Q_ID_MAP_L_SFT 0
+#define TXQ0_MTX_Q_ID_MAP_L_HI 31
+#define TXQ0_MTX_Q_ID_MAP_L_SZ 32
+#define TXQ0_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff
+#define TXQ0_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000
+#define TXQ0_MTX_Q_TXOP_CH_THD_SFT 0
+#define TXQ0_MTX_Q_TXOP_CH_THD_HI 15
+#define TXQ0_MTX_Q_TXOP_CH_THD_SZ 16
+#define TXQ0_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff
+#define TXQ0_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000
+#define TXQ0_MTX_Q_TXOP_OV_THD_SFT 0
+#define TXQ0_MTX_Q_TXOP_OV_THD_HI 15
+#define TXQ0_MTX_Q_TXOP_OV_THD_SZ 16
+#define TXQ1_MTX_Q_PRE_LD_MSK 0x00000002
+#define TXQ1_MTX_Q_PRE_LD_I_MSK 0xfffffffd
+#define TXQ1_MTX_Q_PRE_LD_SFT 1
+#define TXQ1_MTX_Q_PRE_LD_HI 1
+#define TXQ1_MTX_Q_PRE_LD_SZ 1
+#define TXQ1_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004
+#define TXQ1_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb
+#define TXQ1_MTX_Q_BKF_CNT_FIXED_SFT 2
+#define TXQ1_MTX_Q_BKF_CNT_FIXED_HI 2
+#define TXQ1_MTX_Q_BKF_CNT_FIXED_SZ 1
+#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008
+#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7
+#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3
+#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_HI 3
+#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1
+#define TXQ1_MTX_Q_MB_NO_RLS_MSK 0x00000010
+#define TXQ1_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
+#define TXQ1_MTX_Q_MB_NO_RLS_SFT 4
+#define TXQ1_MTX_Q_MB_NO_RLS_HI 4
+#define TXQ1_MTX_Q_MB_NO_RLS_SZ 1
+#define TXQ1_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020
+#define TXQ1_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf
+#define TXQ1_MTX_Q_TXOP_FRC_BUR_SFT 5
+#define TXQ1_MTX_Q_TXOP_FRC_BUR_HI 5
+#define TXQ1_MTX_Q_TXOP_FRC_BUR_SZ 1
+#define TXQ1_MTX_Q_RND_MODE_MSK 0x000000c0
+#define TXQ1_MTX_Q_RND_MODE_I_MSK 0xffffff3f
+#define TXQ1_MTX_Q_RND_MODE_SFT 6
+#define TXQ1_MTX_Q_RND_MODE_HI 7
+#define TXQ1_MTX_Q_RND_MODE_SZ 2
+#define TXQ1_MTX_Q_AIFSN_MSK 0x0000000f
+#define TXQ1_MTX_Q_AIFSN_I_MSK 0xfffffff0
+#define TXQ1_MTX_Q_AIFSN_SFT 0
+#define TXQ1_MTX_Q_AIFSN_HI 3
+#define TXQ1_MTX_Q_AIFSN_SZ 4
+#define TXQ1_MTX_Q_ECWMIN_MSK 0x00000f00
+#define TXQ1_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
+#define TXQ1_MTX_Q_ECWMIN_SFT 8
+#define TXQ1_MTX_Q_ECWMIN_HI 11
+#define TXQ1_MTX_Q_ECWMIN_SZ 4
+#define TXQ1_MTX_Q_ECWMAX_MSK 0x0000f000
+#define TXQ1_MTX_Q_ECWMAX_I_MSK 0xffff0fff
+#define TXQ1_MTX_Q_ECWMAX_SFT 12
+#define TXQ1_MTX_Q_ECWMAX_HI 15
+#define TXQ1_MTX_Q_ECWMAX_SZ 4
+#define TXQ1_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
+#define TXQ1_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
+#define TXQ1_MTX_Q_TXOP_LIMIT_SFT 16
+#define TXQ1_MTX_Q_TXOP_LIMIT_HI 31
+#define TXQ1_MTX_Q_TXOP_LIMIT_SZ 16
+#define TXQ1_MTX_Q_BKF_CNT_MSK 0x0000ffff
+#define TXQ1_MTX_Q_BKF_CNT_I_MSK 0xffff0000
+#define TXQ1_MTX_Q_BKF_CNT_SFT 0
+#define TXQ1_MTX_Q_BKF_CNT_HI 15
+#define TXQ1_MTX_Q_BKF_CNT_SZ 16
+#define TXQ1_MTX_Q_SRC_LIMIT_MSK 0x000000ff
+#define TXQ1_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00
+#define TXQ1_MTX_Q_SRC_LIMIT_SFT 0
+#define TXQ1_MTX_Q_SRC_LIMIT_HI 7
+#define TXQ1_MTX_Q_SRC_LIMIT_SZ 8
+#define TXQ1_MTX_Q_LRC_LIMIT_MSK 0x0000ff00
+#define TXQ1_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff
+#define TXQ1_MTX_Q_LRC_LIMIT_SFT 8
+#define TXQ1_MTX_Q_LRC_LIMIT_HI 15
+#define TXQ1_MTX_Q_LRC_LIMIT_SZ 8
+#define TXQ1_MTX_Q_ID_MAP_L_MSK 0xffffffff
+#define TXQ1_MTX_Q_ID_MAP_L_I_MSK 0x00000000
+#define TXQ1_MTX_Q_ID_MAP_L_SFT 0
+#define TXQ1_MTX_Q_ID_MAP_L_HI 31
+#define TXQ1_MTX_Q_ID_MAP_L_SZ 32
+#define TXQ1_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff
+#define TXQ1_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000
+#define TXQ1_MTX_Q_TXOP_CH_THD_SFT 0
+#define TXQ1_MTX_Q_TXOP_CH_THD_HI 15
+#define TXQ1_MTX_Q_TXOP_CH_THD_SZ 16
+#define TXQ1_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff
+#define TXQ1_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000
+#define TXQ1_MTX_Q_TXOP_OV_THD_SFT 0
+#define TXQ1_MTX_Q_TXOP_OV_THD_HI 15
+#define TXQ1_MTX_Q_TXOP_OV_THD_SZ 16
+#define TXQ2_MTX_Q_PRE_LD_MSK 0x00000002
+#define TXQ2_MTX_Q_PRE_LD_I_MSK 0xfffffffd
+#define TXQ2_MTX_Q_PRE_LD_SFT 1
+#define TXQ2_MTX_Q_PRE_LD_HI 1
+#define TXQ2_MTX_Q_PRE_LD_SZ 1
+#define TXQ2_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004
+#define TXQ2_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb
+#define TXQ2_MTX_Q_BKF_CNT_FIXED_SFT 2
+#define TXQ2_MTX_Q_BKF_CNT_FIXED_HI 2
+#define TXQ2_MTX_Q_BKF_CNT_FIXED_SZ 1
+#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008
+#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7
+#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3
+#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_HI 3
+#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1
+#define TXQ2_MTX_Q_MB_NO_RLS_MSK 0x00000010
+#define TXQ2_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
+#define TXQ2_MTX_Q_MB_NO_RLS_SFT 4
+#define TXQ2_MTX_Q_MB_NO_RLS_HI 4
+#define TXQ2_MTX_Q_MB_NO_RLS_SZ 1
+#define TXQ2_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020
+#define TXQ2_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf
+#define TXQ2_MTX_Q_TXOP_FRC_BUR_SFT 5
+#define TXQ2_MTX_Q_TXOP_FRC_BUR_HI 5
+#define TXQ2_MTX_Q_TXOP_FRC_BUR_SZ 1
+#define TXQ2_MTX_Q_RND_MODE_MSK 0x000000c0
+#define TXQ2_MTX_Q_RND_MODE_I_MSK 0xffffff3f
+#define TXQ2_MTX_Q_RND_MODE_SFT 6
+#define TXQ2_MTX_Q_RND_MODE_HI 7
+#define TXQ2_MTX_Q_RND_MODE_SZ 2
+#define TXQ2_MTX_Q_AIFSN_MSK 0x0000000f
+#define TXQ2_MTX_Q_AIFSN_I_MSK 0xfffffff0
+#define TXQ2_MTX_Q_AIFSN_SFT 0
+#define TXQ2_MTX_Q_AIFSN_HI 3
+#define TXQ2_MTX_Q_AIFSN_SZ 4
+#define TXQ2_MTX_Q_ECWMIN_MSK 0x00000f00
+#define TXQ2_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
+#define TXQ2_MTX_Q_ECWMIN_SFT 8
+#define TXQ2_MTX_Q_ECWMIN_HI 11
+#define TXQ2_MTX_Q_ECWMIN_SZ 4
+#define TXQ2_MTX_Q_ECWMAX_MSK 0x0000f000
+#define TXQ2_MTX_Q_ECWMAX_I_MSK 0xffff0fff
+#define TXQ2_MTX_Q_ECWMAX_SFT 12
+#define TXQ2_MTX_Q_ECWMAX_HI 15
+#define TXQ2_MTX_Q_ECWMAX_SZ 4
+#define TXQ2_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
+#define TXQ2_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
+#define TXQ2_MTX_Q_TXOP_LIMIT_SFT 16
+#define TXQ2_MTX_Q_TXOP_LIMIT_HI 31
+#define TXQ2_MTX_Q_TXOP_LIMIT_SZ 16
+#define TXQ2_MTX_Q_BKF_CNT_MSK 0x0000ffff
+#define TXQ2_MTX_Q_BKF_CNT_I_MSK 0xffff0000
+#define TXQ2_MTX_Q_BKF_CNT_SFT 0
+#define TXQ2_MTX_Q_BKF_CNT_HI 15
+#define TXQ2_MTX_Q_BKF_CNT_SZ 16
+#define TXQ2_MTX_Q_SRC_LIMIT_MSK 0x000000ff
+#define TXQ2_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00
+#define TXQ2_MTX_Q_SRC_LIMIT_SFT 0
+#define TXQ2_MTX_Q_SRC_LIMIT_HI 7
+#define TXQ2_MTX_Q_SRC_LIMIT_SZ 8
+#define TXQ2_MTX_Q_LRC_LIMIT_MSK 0x0000ff00
+#define TXQ2_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff
+#define TXQ2_MTX_Q_LRC_LIMIT_SFT 8
+#define TXQ2_MTX_Q_LRC_LIMIT_HI 15
+#define TXQ2_MTX_Q_LRC_LIMIT_SZ 8
+#define TXQ2_MTX_Q_ID_MAP_L_MSK 0xffffffff
+#define TXQ2_MTX_Q_ID_MAP_L_I_MSK 0x00000000
+#define TXQ2_MTX_Q_ID_MAP_L_SFT 0
+#define TXQ2_MTX_Q_ID_MAP_L_HI 31
+#define TXQ2_MTX_Q_ID_MAP_L_SZ 32
+#define TXQ2_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff
+#define TXQ2_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000
+#define TXQ2_MTX_Q_TXOP_CH_THD_SFT 0
+#define TXQ2_MTX_Q_TXOP_CH_THD_HI 15
+#define TXQ2_MTX_Q_TXOP_CH_THD_SZ 16
+#define TXQ2_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff
+#define TXQ2_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000
+#define TXQ2_MTX_Q_TXOP_OV_THD_SFT 0
+#define TXQ2_MTX_Q_TXOP_OV_THD_HI 15
+#define TXQ2_MTX_Q_TXOP_OV_THD_SZ 16
+#define TXQ3_MTX_Q_PRE_LD_MSK 0x00000002
+#define TXQ3_MTX_Q_PRE_LD_I_MSK 0xfffffffd
+#define TXQ3_MTX_Q_PRE_LD_SFT 1
+#define TXQ3_MTX_Q_PRE_LD_HI 1
+#define TXQ3_MTX_Q_PRE_LD_SZ 1
+#define TXQ3_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004
+#define TXQ3_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb
+#define TXQ3_MTX_Q_BKF_CNT_FIXED_SFT 2
+#define TXQ3_MTX_Q_BKF_CNT_FIXED_HI 2
+#define TXQ3_MTX_Q_BKF_CNT_FIXED_SZ 1
+#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008
+#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7
+#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3
+#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_HI 3
+#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1
+#define TXQ3_MTX_Q_MB_NO_RLS_MSK 0x00000010
+#define TXQ3_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
+#define TXQ3_MTX_Q_MB_NO_RLS_SFT 4
+#define TXQ3_MTX_Q_MB_NO_RLS_HI 4
+#define TXQ3_MTX_Q_MB_NO_RLS_SZ 1
+#define TXQ3_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020
+#define TXQ3_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf
+#define TXQ3_MTX_Q_TXOP_FRC_BUR_SFT 5
+#define TXQ3_MTX_Q_TXOP_FRC_BUR_HI 5
+#define TXQ3_MTX_Q_TXOP_FRC_BUR_SZ 1
+#define TXQ3_MTX_Q_RND_MODE_MSK 0x000000c0
+#define TXQ3_MTX_Q_RND_MODE_I_MSK 0xffffff3f
+#define TXQ3_MTX_Q_RND_MODE_SFT 6
+#define TXQ3_MTX_Q_RND_MODE_HI 7
+#define TXQ3_MTX_Q_RND_MODE_SZ 2
+#define TXQ3_MTX_Q_AIFSN_MSK 0x0000000f
+#define TXQ3_MTX_Q_AIFSN_I_MSK 0xfffffff0
+#define TXQ3_MTX_Q_AIFSN_SFT 0
+#define TXQ3_MTX_Q_AIFSN_HI 3
+#define TXQ3_MTX_Q_AIFSN_SZ 4
+#define TXQ3_MTX_Q_ECWMIN_MSK 0x00000f00
+#define TXQ3_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
+#define TXQ3_MTX_Q_ECWMIN_SFT 8
+#define TXQ3_MTX_Q_ECWMIN_HI 11
+#define TXQ3_MTX_Q_ECWMIN_SZ 4
+#define TXQ3_MTX_Q_ECWMAX_MSK 0x0000f000
+#define TXQ3_MTX_Q_ECWMAX_I_MSK 0xffff0fff
+#define TXQ3_MTX_Q_ECWMAX_SFT 12
+#define TXQ3_MTX_Q_ECWMAX_HI 15
+#define TXQ3_MTX_Q_ECWMAX_SZ 4
+#define TXQ3_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
+#define TXQ3_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
+#define TXQ3_MTX_Q_TXOP_LIMIT_SFT 16
+#define TXQ3_MTX_Q_TXOP_LIMIT_HI 31
+#define TXQ3_MTX_Q_TXOP_LIMIT_SZ 16
+#define TXQ3_MTX_Q_BKF_CNT_MSK 0x0000ffff
+#define TXQ3_MTX_Q_BKF_CNT_I_MSK 0xffff0000
+#define TXQ3_MTX_Q_BKF_CNT_SFT 0
+#define TXQ3_MTX_Q_BKF_CNT_HI 15
+#define TXQ3_MTX_Q_BKF_CNT_SZ 16
+#define TXQ3_MTX_Q_SRC_LIMIT_MSK 0x000000ff
+#define TXQ3_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00
+#define TXQ3_MTX_Q_SRC_LIMIT_SFT 0
+#define TXQ3_MTX_Q_SRC_LIMIT_HI 7
+#define TXQ3_MTX_Q_SRC_LIMIT_SZ 8
+#define TXQ3_MTX_Q_LRC_LIMIT_MSK 0x0000ff00
+#define TXQ3_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff
+#define TXQ3_MTX_Q_LRC_LIMIT_SFT 8
+#define TXQ3_MTX_Q_LRC_LIMIT_HI 15
+#define TXQ3_MTX_Q_LRC_LIMIT_SZ 8
+#define TXQ3_MTX_Q_ID_MAP_L_MSK 0xffffffff
+#define TXQ3_MTX_Q_ID_MAP_L_I_MSK 0x00000000
+#define TXQ3_MTX_Q_ID_MAP_L_SFT 0
+#define TXQ3_MTX_Q_ID_MAP_L_HI 31
+#define TXQ3_MTX_Q_ID_MAP_L_SZ 32
+#define TXQ3_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff
+#define TXQ3_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000
+#define TXQ3_MTX_Q_TXOP_CH_THD_SFT 0
+#define TXQ3_MTX_Q_TXOP_CH_THD_HI 15
+#define TXQ3_MTX_Q_TXOP_CH_THD_SZ 16
+#define TXQ3_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff
+#define TXQ3_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000
+#define TXQ3_MTX_Q_TXOP_OV_THD_SFT 0
+#define TXQ3_MTX_Q_TXOP_OV_THD_HI 15
+#define TXQ3_MTX_Q_TXOP_OV_THD_SZ 16
+#define TXQ4_MTX_Q_PRE_LD_MSK 0x00000002
+#define TXQ4_MTX_Q_PRE_LD_I_MSK 0xfffffffd
+#define TXQ4_MTX_Q_PRE_LD_SFT 1
+#define TXQ4_MTX_Q_PRE_LD_HI 1
+#define TXQ4_MTX_Q_PRE_LD_SZ 1
+#define TXQ4_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004
+#define TXQ4_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb
+#define TXQ4_MTX_Q_BKF_CNT_FIXED_SFT 2
+#define TXQ4_MTX_Q_BKF_CNT_FIXED_HI 2
+#define TXQ4_MTX_Q_BKF_CNT_FIXED_SZ 1
+#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008
+#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7
+#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3
+#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_HI 3
+#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1
+#define TXQ4_MTX_Q_MB_NO_RLS_MSK 0x00000010
+#define TXQ4_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
+#define TXQ4_MTX_Q_MB_NO_RLS_SFT 4
+#define TXQ4_MTX_Q_MB_NO_RLS_HI 4
+#define TXQ4_MTX_Q_MB_NO_RLS_SZ 1
+#define TXQ4_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020
+#define TXQ4_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf
+#define TXQ4_MTX_Q_TXOP_FRC_BUR_SFT 5
+#define TXQ4_MTX_Q_TXOP_FRC_BUR_HI 5
+#define TXQ4_MTX_Q_TXOP_FRC_BUR_SZ 1
+#define TXQ4_MTX_Q_RND_MODE_MSK 0x000000c0
+#define TXQ4_MTX_Q_RND_MODE_I_MSK 0xffffff3f
+#define TXQ4_MTX_Q_RND_MODE_SFT 6
+#define TXQ4_MTX_Q_RND_MODE_HI 7
+#define TXQ4_MTX_Q_RND_MODE_SZ 2
+#define TXQ4_MTX_Q_AIFSN_MSK 0x0000000f
+#define TXQ4_MTX_Q_AIFSN_I_MSK 0xfffffff0
+#define TXQ4_MTX_Q_AIFSN_SFT 0
+#define TXQ4_MTX_Q_AIFSN_HI 3
+#define TXQ4_MTX_Q_AIFSN_SZ 4
+#define TXQ4_MTX_Q_ECWMIN_MSK 0x00000f00
+#define TXQ4_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
+#define TXQ4_MTX_Q_ECWMIN_SFT 8
+#define TXQ4_MTX_Q_ECWMIN_HI 11
+#define TXQ4_MTX_Q_ECWMIN_SZ 4
+#define TXQ4_MTX_Q_ECWMAX_MSK 0x0000f000
+#define TXQ4_MTX_Q_ECWMAX_I_MSK 0xffff0fff
+#define TXQ4_MTX_Q_ECWMAX_SFT 12
+#define TXQ4_MTX_Q_ECWMAX_HI 15
+#define TXQ4_MTX_Q_ECWMAX_SZ 4
+#define TXQ4_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
+#define TXQ4_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
+#define TXQ4_MTX_Q_TXOP_LIMIT_SFT 16
+#define TXQ4_MTX_Q_TXOP_LIMIT_HI 31
+#define TXQ4_MTX_Q_TXOP_LIMIT_SZ 16
+#define TXQ4_MTX_Q_BKF_CNT_MSK 0x0000ffff
+#define TXQ4_MTX_Q_BKF_CNT_I_MSK 0xffff0000
+#define TXQ4_MTX_Q_BKF_CNT_SFT 0
+#define TXQ4_MTX_Q_BKF_CNT_HI 15
+#define TXQ4_MTX_Q_BKF_CNT_SZ 16
+#define TXQ4_MTX_Q_SRC_LIMIT_MSK 0x000000ff
+#define TXQ4_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00
+#define TXQ4_MTX_Q_SRC_LIMIT_SFT 0
+#define TXQ4_MTX_Q_SRC_LIMIT_HI 7
+#define TXQ4_MTX_Q_SRC_LIMIT_SZ 8
+#define TXQ4_MTX_Q_LRC_LIMIT_MSK 0x0000ff00
+#define TXQ4_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff
+#define TXQ4_MTX_Q_LRC_LIMIT_SFT 8
+#define TXQ4_MTX_Q_LRC_LIMIT_HI 15
+#define TXQ4_MTX_Q_LRC_LIMIT_SZ 8
+#define TXQ4_MTX_Q_ID_MAP_L_MSK 0xffffffff
+#define TXQ4_MTX_Q_ID_MAP_L_I_MSK 0x00000000
+#define TXQ4_MTX_Q_ID_MAP_L_SFT 0
+#define TXQ4_MTX_Q_ID_MAP_L_HI 31
+#define TXQ4_MTX_Q_ID_MAP_L_SZ 32
+#define TXQ4_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff
+#define TXQ4_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000
+#define TXQ4_MTX_Q_TXOP_CH_THD_SFT 0
+#define TXQ4_MTX_Q_TXOP_CH_THD_HI 15
+#define TXQ4_MTX_Q_TXOP_CH_THD_SZ 16
+#define TXQ4_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff
+#define TXQ4_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000
+#define TXQ4_MTX_Q_TXOP_OV_THD_SFT 0
+#define TXQ4_MTX_Q_TXOP_OV_THD_HI 15
+#define TXQ4_MTX_Q_TXOP_OV_THD_SZ 16
+#define VALID0_MSK 0x00000001
+#define VALID0_I_MSK 0xfffffffe
+#define VALID0_SFT 0
+#define VALID0_HI 0
+#define VALID0_SZ 1
+#define PEER_QOS_EN0_MSK 0x00000002
+#define PEER_QOS_EN0_I_MSK 0xfffffffd
+#define PEER_QOS_EN0_SFT 1
+#define PEER_QOS_EN0_HI 1
+#define PEER_QOS_EN0_SZ 1
+#define PEER_OP_MODE0_MSK 0x0000000c
+#define PEER_OP_MODE0_I_MSK 0xfffffff3
+#define PEER_OP_MODE0_SFT 2
+#define PEER_OP_MODE0_HI 3
+#define PEER_OP_MODE0_SZ 2
+#define PEER_HT_MODE0_MSK 0x00000030
+#define PEER_HT_MODE0_I_MSK 0xffffffcf
+#define PEER_HT_MODE0_SFT 4
+#define PEER_HT_MODE0_HI 5
+#define PEER_HT_MODE0_SZ 2
+#define PEER_MAC0_31_0_MSK 0xffffffff
+#define PEER_MAC0_31_0_I_MSK 0x00000000
+#define PEER_MAC0_31_0_SFT 0
+#define PEER_MAC0_31_0_HI 31
+#define PEER_MAC0_31_0_SZ 32
+#define PEER_MAC0_47_32_MSK 0x0000ffff
+#define PEER_MAC0_47_32_I_MSK 0xffff0000
+#define PEER_MAC0_47_32_SFT 0
+#define PEER_MAC0_47_32_HI 15
+#define PEER_MAC0_47_32_SZ 16
+#define TX_ACK_POLICY_0_0_MSK 0x00000003
+#define TX_ACK_POLICY_0_0_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_0_SFT 0
+#define TX_ACK_POLICY_0_0_HI 1
+#define TX_ACK_POLICY_0_0_SZ 2
+#define TX_SEQ_CTRL_0_0_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_0_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_0_SFT 0
+#define TX_SEQ_CTRL_0_0_HI 11
+#define TX_SEQ_CTRL_0_0_SZ 12
+#define TX_ACK_POLICY_0_1_MSK 0x00000003
+#define TX_ACK_POLICY_0_1_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_1_SFT 0
+#define TX_ACK_POLICY_0_1_HI 1
+#define TX_ACK_POLICY_0_1_SZ 2
+#define TX_SEQ_CTRL_0_1_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_1_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_1_SFT 0
+#define TX_SEQ_CTRL_0_1_HI 11
+#define TX_SEQ_CTRL_0_1_SZ 12
+#define TX_ACK_POLICY_0_2_MSK 0x00000003
+#define TX_ACK_POLICY_0_2_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_2_SFT 0
+#define TX_ACK_POLICY_0_2_HI 1
+#define TX_ACK_POLICY_0_2_SZ 2
+#define TX_SEQ_CTRL_0_2_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_2_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_2_SFT 0
+#define TX_SEQ_CTRL_0_2_HI 11
+#define TX_SEQ_CTRL_0_2_SZ 12
+#define TX_ACK_POLICY_0_3_MSK 0x00000003
+#define TX_ACK_POLICY_0_3_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_3_SFT 0
+#define TX_ACK_POLICY_0_3_HI 1
+#define TX_ACK_POLICY_0_3_SZ 2
+#define TX_SEQ_CTRL_0_3_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_3_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_3_SFT 0
+#define TX_SEQ_CTRL_0_3_HI 11
+#define TX_SEQ_CTRL_0_3_SZ 12
+#define TX_ACK_POLICY_0_4_MSK 0x00000003
+#define TX_ACK_POLICY_0_4_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_4_SFT 0
+#define TX_ACK_POLICY_0_4_HI 1
+#define TX_ACK_POLICY_0_4_SZ 2
+#define TX_SEQ_CTRL_0_4_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_4_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_4_SFT 0
+#define TX_SEQ_CTRL_0_4_HI 11
+#define TX_SEQ_CTRL_0_4_SZ 12
+#define TX_ACK_POLICY_0_5_MSK 0x00000003
+#define TX_ACK_POLICY_0_5_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_5_SFT 0
+#define TX_ACK_POLICY_0_5_HI 1
+#define TX_ACK_POLICY_0_5_SZ 2
+#define TX_SEQ_CTRL_0_5_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_5_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_5_SFT 0
+#define TX_SEQ_CTRL_0_5_HI 11
+#define TX_SEQ_CTRL_0_5_SZ 12
+#define TX_ACK_POLICY_0_6_MSK 0x00000003
+#define TX_ACK_POLICY_0_6_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_6_SFT 0
+#define TX_ACK_POLICY_0_6_HI 1
+#define TX_ACK_POLICY_0_6_SZ 2
+#define TX_SEQ_CTRL_0_6_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_6_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_6_SFT 0
+#define TX_SEQ_CTRL_0_6_HI 11
+#define TX_SEQ_CTRL_0_6_SZ 12
+#define TX_ACK_POLICY_0_7_MSK 0x00000003
+#define TX_ACK_POLICY_0_7_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_7_SFT 0
+#define TX_ACK_POLICY_0_7_HI 1
+#define TX_ACK_POLICY_0_7_SZ 2
+#define TX_SEQ_CTRL_0_7_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_7_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_7_SFT 0
+#define TX_SEQ_CTRL_0_7_HI 11
+#define TX_SEQ_CTRL_0_7_SZ 12
+#define VALID1_MSK 0x00000001
+#define VALID1_I_MSK 0xfffffffe
+#define VALID1_SFT 0
+#define VALID1_HI 0
+#define VALID1_SZ 1
+#define PEER_QOS_EN1_MSK 0x00000002
+#define PEER_QOS_EN1_I_MSK 0xfffffffd
+#define PEER_QOS_EN1_SFT 1
+#define PEER_QOS_EN1_HI 1
+#define PEER_QOS_EN1_SZ 1
+#define PEER_OP_MODE1_MSK 0x0000000c
+#define PEER_OP_MODE1_I_MSK 0xfffffff3
+#define PEER_OP_MODE1_SFT 2
+#define PEER_OP_MODE1_HI 3
+#define PEER_OP_MODE1_SZ 2
+#define PEER_HT_MODE1_MSK 0x00000030
+#define PEER_HT_MODE1_I_MSK 0xffffffcf
+#define PEER_HT_MODE1_SFT 4
+#define PEER_HT_MODE1_HI 5
+#define PEER_HT_MODE1_SZ 2
+#define PEER_MAC1_31_0_MSK 0xffffffff
+#define PEER_MAC1_31_0_I_MSK 0x00000000
+#define PEER_MAC1_31_0_SFT 0
+#define PEER_MAC1_31_0_HI 31
+#define PEER_MAC1_31_0_SZ 32
+#define PEER_MAC1_47_32_MSK 0x0000ffff
+#define PEER_MAC1_47_32_I_MSK 0xffff0000
+#define PEER_MAC1_47_32_SFT 0
+#define PEER_MAC1_47_32_HI 15
+#define PEER_MAC1_47_32_SZ 16
+#define TX_ACK_POLICY_1_0_MSK 0x00000003
+#define TX_ACK_POLICY_1_0_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_0_SFT 0
+#define TX_ACK_POLICY_1_0_HI 1
+#define TX_ACK_POLICY_1_0_SZ 2
+#define TX_SEQ_CTRL_1_0_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_0_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_0_SFT 0
+#define TX_SEQ_CTRL_1_0_HI 11
+#define TX_SEQ_CTRL_1_0_SZ 12
+#define TX_ACK_POLICY_1_1_MSK 0x00000003
+#define TX_ACK_POLICY_1_1_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_1_SFT 0
+#define TX_ACK_POLICY_1_1_HI 1
+#define TX_ACK_POLICY_1_1_SZ 2
+#define TX_SEQ_CTRL_1_1_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_1_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_1_SFT 0
+#define TX_SEQ_CTRL_1_1_HI 11
+#define TX_SEQ_CTRL_1_1_SZ 12
+#define TX_ACK_POLICY_1_2_MSK 0x00000003
+#define TX_ACK_POLICY_1_2_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_2_SFT 0
+#define TX_ACK_POLICY_1_2_HI 1
+#define TX_ACK_POLICY_1_2_SZ 2
+#define TX_SEQ_CTRL_1_2_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_2_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_2_SFT 0
+#define TX_SEQ_CTRL_1_2_HI 11
+#define TX_SEQ_CTRL_1_2_SZ 12
+#define TX_ACK_POLICY_1_3_MSK 0x00000003
+#define TX_ACK_POLICY_1_3_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_3_SFT 0
+#define TX_ACK_POLICY_1_3_HI 1
+#define TX_ACK_POLICY_1_3_SZ 2
+#define TX_SEQ_CTRL_1_3_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_3_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_3_SFT 0
+#define TX_SEQ_CTRL_1_3_HI 11
+#define TX_SEQ_CTRL_1_3_SZ 12
+#define TX_ACK_POLICY_1_4_MSK 0x00000003
+#define TX_ACK_POLICY_1_4_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_4_SFT 0
+#define TX_ACK_POLICY_1_4_HI 1
+#define TX_ACK_POLICY_1_4_SZ 2
+#define TX_SEQ_CTRL_1_4_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_4_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_4_SFT 0
+#define TX_SEQ_CTRL_1_4_HI 11
+#define TX_SEQ_CTRL_1_4_SZ 12
+#define TX_ACK_POLICY_1_5_MSK 0x00000003
+#define TX_ACK_POLICY_1_5_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_5_SFT 0
+#define TX_ACK_POLICY_1_5_HI 1
+#define TX_ACK_POLICY_1_5_SZ 2
+#define TX_SEQ_CTRL_1_5_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_5_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_5_SFT 0
+#define TX_SEQ_CTRL_1_5_HI 11
+#define TX_SEQ_CTRL_1_5_SZ 12
+#define TX_ACK_POLICY_1_6_MSK 0x00000003
+#define TX_ACK_POLICY_1_6_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_6_SFT 0
+#define TX_ACK_POLICY_1_6_HI 1
+#define TX_ACK_POLICY_1_6_SZ 2
+#define TX_SEQ_CTRL_1_6_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_6_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_6_SFT 0
+#define TX_SEQ_CTRL_1_6_HI 11
+#define TX_SEQ_CTRL_1_6_SZ 12
+#define TX_ACK_POLICY_1_7_MSK 0x00000003
+#define TX_ACK_POLICY_1_7_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_7_SFT 0
+#define TX_ACK_POLICY_1_7_HI 1
+#define TX_ACK_POLICY_1_7_SZ 2
+#define TX_SEQ_CTRL_1_7_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_7_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_7_SFT 0
+#define TX_SEQ_CTRL_1_7_HI 11
+#define TX_SEQ_CTRL_1_7_SZ 12
+#define INFO0_MSK 0xffffffff
+#define INFO0_I_MSK 0x00000000
+#define INFO0_SFT 0
+#define INFO0_HI 31
+#define INFO0_SZ 32
+#define INFO1_MSK 0xffffffff
+#define INFO1_I_MSK 0x00000000
+#define INFO1_SFT 0
+#define INFO1_HI 31
+#define INFO1_SZ 32
+#define INFO2_MSK 0xffffffff
+#define INFO2_I_MSK 0x00000000
+#define INFO2_SFT 0
+#define INFO2_HI 31
+#define INFO2_SZ 32
+#define INFO3_MSK 0xffffffff
+#define INFO3_I_MSK 0x00000000
+#define INFO3_SFT 0
+#define INFO3_HI 31
+#define INFO3_SZ 32
+#define INFO4_MSK 0xffffffff
+#define INFO4_I_MSK 0x00000000
+#define INFO4_SFT 0
+#define INFO4_HI 31
+#define INFO4_SZ 32
+#define INFO5_MSK 0xffffffff
+#define INFO5_I_MSK 0x00000000
+#define INFO5_SFT 0
+#define INFO5_HI 31
+#define INFO5_SZ 32
+#define INFO6_MSK 0xffffffff
+#define INFO6_I_MSK 0x00000000
+#define INFO6_SFT 0
+#define INFO6_HI 31
+#define INFO6_SZ 32
+#define INFO7_MSK 0xffffffff
+#define INFO7_I_MSK 0x00000000
+#define INFO7_SFT 0
+#define INFO7_HI 31
+#define INFO7_SZ 32
+#define INFO8_MSK 0xffffffff
+#define INFO8_I_MSK 0x00000000
+#define INFO8_SFT 0
+#define INFO8_HI 31
+#define INFO8_SZ 32
+#define INFO9_MSK 0xffffffff
+#define INFO9_I_MSK 0x00000000
+#define INFO9_SFT 0
+#define INFO9_HI 31
+#define INFO9_SZ 32
+#define INFO10_MSK 0xffffffff
+#define INFO10_I_MSK 0x00000000
+#define INFO10_SFT 0
+#define INFO10_HI 31
+#define INFO10_SZ 32
+#define INFO11_MSK 0xffffffff
+#define INFO11_I_MSK 0x00000000
+#define INFO11_SFT 0
+#define INFO11_HI 31
+#define INFO11_SZ 32
+#define INFO12_MSK 0xffffffff
+#define INFO12_I_MSK 0x00000000
+#define INFO12_SFT 0
+#define INFO12_HI 31
+#define INFO12_SZ 32
+#define INFO13_MSK 0xffffffff
+#define INFO13_I_MSK 0x00000000
+#define INFO13_SFT 0
+#define INFO13_HI 31
+#define INFO13_SZ 32
+#define INFO14_MSK 0xffffffff
+#define INFO14_I_MSK 0x00000000
+#define INFO14_SFT 0
+#define INFO14_HI 31
+#define INFO14_SZ 32
+#define INFO15_MSK 0xffffffff
+#define INFO15_I_MSK 0x00000000
+#define INFO15_SFT 0
+#define INFO15_HI 31
+#define INFO15_SZ 32
+#define INFO16_MSK 0xffffffff
+#define INFO16_I_MSK 0x00000000
+#define INFO16_SFT 0
+#define INFO16_HI 31
+#define INFO16_SZ 32
+#define INFO17_MSK 0xffffffff
+#define INFO17_I_MSK 0x00000000
+#define INFO17_SFT 0
+#define INFO17_HI 31
+#define INFO17_SZ 32
+#define INFO18_MSK 0xffffffff
+#define INFO18_I_MSK 0x00000000
+#define INFO18_SFT 0
+#define INFO18_HI 31
+#define INFO18_SZ 32
+#define INFO19_MSK 0xffffffff
+#define INFO19_I_MSK 0x00000000
+#define INFO19_SFT 0
+#define INFO19_HI 31
+#define INFO19_SZ 32
+#define INFO20_MSK 0xffffffff
+#define INFO20_I_MSK 0x00000000
+#define INFO20_SFT 0
+#define INFO20_HI 31
+#define INFO20_SZ 32
+#define INFO21_MSK 0xffffffff
+#define INFO21_I_MSK 0x00000000
+#define INFO21_SFT 0
+#define INFO21_HI 31
+#define INFO21_SZ 32
+#define INFO22_MSK 0xffffffff
+#define INFO22_I_MSK 0x00000000
+#define INFO22_SFT 0
+#define INFO22_HI 31
+#define INFO22_SZ 32
+#define INFO23_MSK 0xffffffff
+#define INFO23_I_MSK 0x00000000
+#define INFO23_SFT 0
+#define INFO23_HI 31
+#define INFO23_SZ 32
+#define INFO24_MSK 0xffffffff
+#define INFO24_I_MSK 0x00000000
+#define INFO24_SFT 0
+#define INFO24_HI 31
+#define INFO24_SZ 32
+#define INFO25_MSK 0xffffffff
+#define INFO25_I_MSK 0x00000000
+#define INFO25_SFT 0
+#define INFO25_HI 31
+#define INFO25_SZ 32
+#define INFO26_MSK 0xffffffff
+#define INFO26_I_MSK 0x00000000
+#define INFO26_SFT 0
+#define INFO26_HI 31
+#define INFO26_SZ 32
+#define INFO27_MSK 0xffffffff
+#define INFO27_I_MSK 0x00000000
+#define INFO27_SFT 0
+#define INFO27_HI 31
+#define INFO27_SZ 32
+#define INFO28_MSK 0xffffffff
+#define INFO28_I_MSK 0x00000000
+#define INFO28_SFT 0
+#define INFO28_HI 31
+#define INFO28_SZ 32
+#define INFO29_MSK 0xffffffff
+#define INFO29_I_MSK 0x00000000
+#define INFO29_SFT 0
+#define INFO29_HI 31
+#define INFO29_SZ 32
+#define INFO30_MSK 0xffffffff
+#define INFO30_I_MSK 0x00000000
+#define INFO30_SFT 0
+#define INFO30_HI 31
+#define INFO30_SZ 32
+#define INFO31_MSK 0xffffffff
+#define INFO31_I_MSK 0x00000000
+#define INFO31_SFT 0
+#define INFO31_HI 31
+#define INFO31_SZ 32
+#define INFO32_MSK 0xffffffff
+#define INFO32_I_MSK 0x00000000
+#define INFO32_SFT 0
+#define INFO32_HI 31
+#define INFO32_SZ 32
+#define INFO33_MSK 0xffffffff
+#define INFO33_I_MSK 0x00000000
+#define INFO33_SFT 0
+#define INFO33_HI 31
+#define INFO33_SZ 32
+#define INFO34_MSK 0xffffffff
+#define INFO34_I_MSK 0x00000000
+#define INFO34_SFT 0
+#define INFO34_HI 31
+#define INFO34_SZ 32
+#define INFO35_MSK 0xffffffff
+#define INFO35_I_MSK 0x00000000
+#define INFO35_SFT 0
+#define INFO35_HI 31
+#define INFO35_SZ 32
+#define INFO36_MSK 0xffffffff
+#define INFO36_I_MSK 0x00000000
+#define INFO36_SFT 0
+#define INFO36_HI 31
+#define INFO36_SZ 32
+#define INFO37_MSK 0xffffffff
+#define INFO37_I_MSK 0x00000000
+#define INFO37_SFT 0
+#define INFO37_HI 31
+#define INFO37_SZ 32
+#define INFO38_MSK 0xffffffff
+#define INFO38_I_MSK 0x00000000
+#define INFO38_SFT 0
+#define INFO38_HI 31
+#define INFO38_SZ 32
+#define INFO_MASK_MSK 0xffffffff
+#define INFO_MASK_I_MSK 0x00000000
+#define INFO_MASK_SFT 0
+#define INFO_MASK_HI 31
+#define INFO_MASK_SZ 32
+#define INFO_DEF_RATE_MSK 0x0000003f
+#define INFO_DEF_RATE_I_MSK 0xffffffc0
+#define INFO_DEF_RATE_SFT 0
+#define INFO_DEF_RATE_HI 5
+#define INFO_DEF_RATE_SZ 6
+#define INFO_MRX_OFFSET_MSK 0x000f0000
+#define INFO_MRX_OFFSET_I_MSK 0xfff0ffff
+#define INFO_MRX_OFFSET_SFT 16
+#define INFO_MRX_OFFSET_HI 19
+#define INFO_MRX_OFFSET_SZ 4
+#define BCAST_RATEUNKNOW_MSK 0x3f000000
+#define BCAST_RATEUNKNOW_I_MSK 0xc0ffffff
+#define BCAST_RATEUNKNOW_SFT 24
+#define BCAST_RATEUNKNOW_HI 29
+#define BCAST_RATEUNKNOW_SZ 6
+#define INFO_IDX_TBL_ADDR_MSK 0xffffffff
+#define INFO_IDX_TBL_ADDR_I_MSK 0x00000000
+#define INFO_IDX_TBL_ADDR_SFT 0
+#define INFO_IDX_TBL_ADDR_HI 31
+#define INFO_IDX_TBL_ADDR_SZ 32
+#define INFO_LEN_TBL_ADDR_MSK 0xffffffff
+#define INFO_LEN_TBL_ADDR_I_MSK 0x00000000
+#define INFO_LEN_TBL_ADDR_SFT 0
+#define INFO_LEN_TBL_ADDR_HI 31
+#define INFO_LEN_TBL_ADDR_SZ 32
+#define IC_TAG_31_0_MSK 0xffffffff
+#define IC_TAG_31_0_I_MSK 0x00000000
+#define IC_TAG_31_0_SFT 0
+#define IC_TAG_31_0_HI 31
+#define IC_TAG_31_0_SZ 32
+#define IC_TAG_63_32_MSK 0xffffffff
+#define IC_TAG_63_32_I_MSK 0x00000000
+#define IC_TAG_63_32_SFT 0
+#define IC_TAG_63_32_HI 31
+#define IC_TAG_63_32_SZ 32
+#define CH1_PRI_MSK 0x00000003
+#define CH1_PRI_I_MSK 0xfffffffc
+#define CH1_PRI_SFT 0
+#define CH1_PRI_HI 1
+#define CH1_PRI_SZ 2
+#define CH2_PRI_MSK 0x00000300
+#define CH2_PRI_I_MSK 0xfffffcff
+#define CH2_PRI_SFT 8
+#define CH2_PRI_HI 9
+#define CH2_PRI_SZ 2
+#define CH3_PRI_MSK 0x00030000
+#define CH3_PRI_I_MSK 0xfffcffff
+#define CH3_PRI_SFT 16
+#define CH3_PRI_HI 17
+#define CH3_PRI_SZ 2
+#define RG_MAC_LPBK_MSK 0x00000001
+#define RG_MAC_LPBK_I_MSK 0xfffffffe
+#define RG_MAC_LPBK_SFT 0
+#define RG_MAC_LPBK_HI 0
+#define RG_MAC_LPBK_SZ 1
+#define RG_MAC_M2M_MSK 0x00000002
+#define RG_MAC_M2M_I_MSK 0xfffffffd
+#define RG_MAC_M2M_SFT 1
+#define RG_MAC_M2M_HI 1
+#define RG_MAC_M2M_SZ 1
+#define RG_PHY_LPBK_MSK 0x00000004
+#define RG_PHY_LPBK_I_MSK 0xfffffffb
+#define RG_PHY_LPBK_SFT 2
+#define RG_PHY_LPBK_HI 2
+#define RG_PHY_LPBK_SZ 1
+#define RG_LPBK_RX_EN_MSK 0x00000008
+#define RG_LPBK_RX_EN_I_MSK 0xfffffff7
+#define RG_LPBK_RX_EN_SFT 3
+#define RG_LPBK_RX_EN_HI 3
+#define RG_LPBK_RX_EN_SZ 1
+#define EXT_MAC_MODE_MSK 0x00000010
+#define EXT_MAC_MODE_I_MSK 0xffffffef
+#define EXT_MAC_MODE_SFT 4
+#define EXT_MAC_MODE_HI 4
+#define EXT_MAC_MODE_SZ 1
+#define EXT_PHY_MODE_MSK 0x00000020
+#define EXT_PHY_MODE_I_MSK 0xffffffdf
+#define EXT_PHY_MODE_SFT 5
+#define EXT_PHY_MODE_HI 5
+#define EXT_PHY_MODE_SZ 1
+#define ASIC_TAG_MSK 0xff000000
+#define ASIC_TAG_I_MSK 0x00ffffff
+#define ASIC_TAG_SFT 24
+#define ASIC_TAG_HI 31
+#define ASIC_TAG_SZ 8
+#define HCI_SW_RST_MSK 0x00000001
+#define HCI_SW_RST_I_MSK 0xfffffffe
+#define HCI_SW_RST_SFT 0
+#define HCI_SW_RST_HI 0
+#define HCI_SW_RST_SZ 1
+#define CO_PROC_SW_RST_MSK 0x00000002
+#define CO_PROC_SW_RST_I_MSK 0xfffffffd
+#define CO_PROC_SW_RST_SFT 1
+#define CO_PROC_SW_RST_HI 1
+#define CO_PROC_SW_RST_SZ 1
+#define MTX_MISC_SW_RST_MSK 0x00000008
+#define MTX_MISC_SW_RST_I_MSK 0xfffffff7
+#define MTX_MISC_SW_RST_SFT 3
+#define MTX_MISC_SW_RST_HI 3
+#define MTX_MISC_SW_RST_SZ 1
+#define MTX_QUE_SW_RST_MSK 0x00000010
+#define MTX_QUE_SW_RST_I_MSK 0xffffffef
+#define MTX_QUE_SW_RST_SFT 4
+#define MTX_QUE_SW_RST_HI 4
+#define MTX_QUE_SW_RST_SZ 1
+#define MTX_CHST_SW_RST_MSK 0x00000020
+#define MTX_CHST_SW_RST_I_MSK 0xffffffdf
+#define MTX_CHST_SW_RST_SFT 5
+#define MTX_CHST_SW_RST_HI 5
+#define MTX_CHST_SW_RST_SZ 1
+#define MTX_BCN_SW_RST_MSK 0x00000040
+#define MTX_BCN_SW_RST_I_MSK 0xffffffbf
+#define MTX_BCN_SW_RST_SFT 6
+#define MTX_BCN_SW_RST_HI 6
+#define MTX_BCN_SW_RST_SZ 1
+#define MRX_SW_RST_MSK 0x00000080
+#define MRX_SW_RST_I_MSK 0xffffff7f
+#define MRX_SW_RST_SFT 7
+#define MRX_SW_RST_HI 7
+#define MRX_SW_RST_SZ 1
+#define AMPDU_SW_RST_MSK 0x00000100
+#define AMPDU_SW_RST_I_MSK 0xfffffeff
+#define AMPDU_SW_RST_SFT 8
+#define AMPDU_SW_RST_HI 8
+#define AMPDU_SW_RST_SZ 1
+#define MMU_SW_RST_MSK 0x00000200
+#define MMU_SW_RST_I_MSK 0xfffffdff
+#define MMU_SW_RST_SFT 9
+#define MMU_SW_RST_HI 9
+#define MMU_SW_RST_SZ 1
+#define ID_MNG_SW_RST_MSK 0x00000800
+#define ID_MNG_SW_RST_I_MSK 0xfffff7ff
+#define ID_MNG_SW_RST_SFT 11
+#define ID_MNG_SW_RST_HI 11
+#define ID_MNG_SW_RST_SZ 1
+#define MBOX_SW_RST_MSK 0x00001000
+#define MBOX_SW_RST_I_MSK 0xffffefff
+#define MBOX_SW_RST_SFT 12
+#define MBOX_SW_RST_HI 12
+#define MBOX_SW_RST_SZ 1
+#define SCRT_SW_RST_MSK 0x00002000
+#define SCRT_SW_RST_I_MSK 0xffffdfff
+#define SCRT_SW_RST_SFT 13
+#define SCRT_SW_RST_HI 13
+#define SCRT_SW_RST_SZ 1
+#define MIC_SW_RST_MSK 0x00004000
+#define MIC_SW_RST_I_MSK 0xffffbfff
+#define MIC_SW_RST_SFT 14
+#define MIC_SW_RST_HI 14
+#define MIC_SW_RST_SZ 1
+#define CO_PROC_ENG_RST_MSK 0x00000002
+#define CO_PROC_ENG_RST_I_MSK 0xfffffffd
+#define CO_PROC_ENG_RST_SFT 1
+#define CO_PROC_ENG_RST_HI 1
+#define CO_PROC_ENG_RST_SZ 1
+#define MTX_MISC_ENG_RST_MSK 0x00000008
+#define MTX_MISC_ENG_RST_I_MSK 0xfffffff7
+#define MTX_MISC_ENG_RST_SFT 3
+#define MTX_MISC_ENG_RST_HI 3
+#define MTX_MISC_ENG_RST_SZ 1
+#define MTX_QUE_ENG_RST_MSK 0x00000010
+#define MTX_QUE_ENG_RST_I_MSK 0xffffffef
+#define MTX_QUE_ENG_RST_SFT 4
+#define MTX_QUE_ENG_RST_HI 4
+#define MTX_QUE_ENG_RST_SZ 1
+#define MTX_CHST_ENG_RST_MSK 0x00000020
+#define MTX_CHST_ENG_RST_I_MSK 0xffffffdf
+#define MTX_CHST_ENG_RST_SFT 5
+#define MTX_CHST_ENG_RST_HI 5
+#define MTX_CHST_ENG_RST_SZ 1
+#define MTX_BCN_ENG_RST_MSK 0x00000040
+#define MTX_BCN_ENG_RST_I_MSK 0xffffffbf
+#define MTX_BCN_ENG_RST_SFT 6
+#define MTX_BCN_ENG_RST_HI 6
+#define MTX_BCN_ENG_RST_SZ 1
+#define MRX_ENG_RST_MSK 0x00000080
+#define MRX_ENG_RST_I_MSK 0xffffff7f
+#define MRX_ENG_RST_SFT 7
+#define MRX_ENG_RST_HI 7
+#define MRX_ENG_RST_SZ 1
+#define AMPDU_ENG_RST_MSK 0x00000100
+#define AMPDU_ENG_RST_I_MSK 0xfffffeff
+#define AMPDU_ENG_RST_SFT 8
+#define AMPDU_ENG_RST_HI 8
+#define AMPDU_ENG_RST_SZ 1
+#define ID_MNG_ENG_RST_MSK 0x00004000
+#define ID_MNG_ENG_RST_I_MSK 0xffffbfff
+#define ID_MNG_ENG_RST_SFT 14
+#define ID_MNG_ENG_RST_HI 14
+#define ID_MNG_ENG_RST_SZ 1
+#define MBOX_ENG_RST_MSK 0x00008000
+#define MBOX_ENG_RST_I_MSK 0xffff7fff
+#define MBOX_ENG_RST_SFT 15
+#define MBOX_ENG_RST_HI 15
+#define MBOX_ENG_RST_SZ 1
+#define SCRT_ENG_RST_MSK 0x00010000
+#define SCRT_ENG_RST_I_MSK 0xfffeffff
+#define SCRT_ENG_RST_SFT 16
+#define SCRT_ENG_RST_HI 16
+#define SCRT_ENG_RST_SZ 1
+#define MIC_ENG_RST_MSK 0x00020000
+#define MIC_ENG_RST_I_MSK 0xfffdffff
+#define MIC_ENG_RST_SFT 17
+#define MIC_ENG_RST_HI 17
+#define MIC_ENG_RST_SZ 1
+#define CO_PROC_CSR_RST_MSK 0x00000002
+#define CO_PROC_CSR_RST_I_MSK 0xfffffffd
+#define CO_PROC_CSR_RST_SFT 1
+#define CO_PROC_CSR_RST_HI 1
+#define CO_PROC_CSR_RST_SZ 1
+#define MTX_MISC_CSR_RST_MSK 0x00000008
+#define MTX_MISC_CSR_RST_I_MSK 0xfffffff7
+#define MTX_MISC_CSR_RST_SFT 3
+#define MTX_MISC_CSR_RST_HI 3
+#define MTX_MISC_CSR_RST_SZ 1
+#define MTX_QUE0_CSR_RST_MSK 0x00000010
+#define MTX_QUE0_CSR_RST_I_MSK 0xffffffef
+#define MTX_QUE0_CSR_RST_SFT 4
+#define MTX_QUE0_CSR_RST_HI 4
+#define MTX_QUE0_CSR_RST_SZ 1
+#define MTX_QUE1_CSR_RST_MSK 0x00000020
+#define MTX_QUE1_CSR_RST_I_MSK 0xffffffdf
+#define MTX_QUE1_CSR_RST_SFT 5
+#define MTX_QUE1_CSR_RST_HI 5
+#define MTX_QUE1_CSR_RST_SZ 1
+#define MTX_QUE2_CSR_RST_MSK 0x00000040
+#define MTX_QUE2_CSR_RST_I_MSK 0xffffffbf
+#define MTX_QUE2_CSR_RST_SFT 6
+#define MTX_QUE2_CSR_RST_HI 6
+#define MTX_QUE2_CSR_RST_SZ 1
+#define MTX_QUE3_CSR_RST_MSK 0x00000080
+#define MTX_QUE3_CSR_RST_I_MSK 0xffffff7f
+#define MTX_QUE3_CSR_RST_SFT 7
+#define MTX_QUE3_CSR_RST_HI 7
+#define MTX_QUE3_CSR_RST_SZ 1
+#define MTX_QUE4_CSR_RST_MSK 0x00000100
+#define MTX_QUE4_CSR_RST_I_MSK 0xfffffeff
+#define MTX_QUE4_CSR_RST_SFT 8
+#define MTX_QUE4_CSR_RST_HI 8
+#define MTX_QUE4_CSR_RST_SZ 1
+#define MTX_QUE5_CSR_RST_MSK 0x00000200
+#define MTX_QUE5_CSR_RST_I_MSK 0xfffffdff
+#define MTX_QUE5_CSR_RST_SFT 9
+#define MTX_QUE5_CSR_RST_HI 9
+#define MTX_QUE5_CSR_RST_SZ 1
+#define MRX_CSR_RST_MSK 0x00000400
+#define MRX_CSR_RST_I_MSK 0xfffffbff
+#define MRX_CSR_RST_SFT 10
+#define MRX_CSR_RST_HI 10
+#define MRX_CSR_RST_SZ 1
+#define AMPDU_CSR_RST_MSK 0x00000800
+#define AMPDU_CSR_RST_I_MSK 0xfffff7ff
+#define AMPDU_CSR_RST_SFT 11
+#define AMPDU_CSR_RST_HI 11
+#define AMPDU_CSR_RST_SZ 1
+#define SCRT_CSR_RST_MSK 0x00002000
+#define SCRT_CSR_RST_I_MSK 0xffffdfff
+#define SCRT_CSR_RST_SFT 13
+#define SCRT_CSR_RST_HI 13
+#define SCRT_CSR_RST_SZ 1
+#define ID_MNG_CSR_RST_MSK 0x00004000
+#define ID_MNG_CSR_RST_I_MSK 0xffffbfff
+#define ID_MNG_CSR_RST_SFT 14
+#define ID_MNG_CSR_RST_HI 14
+#define ID_MNG_CSR_RST_SZ 1
+#define MBOX_CSR_RST_MSK 0x00008000
+#define MBOX_CSR_RST_I_MSK 0xffff7fff
+#define MBOX_CSR_RST_SFT 15
+#define MBOX_CSR_RST_HI 15
+#define MBOX_CSR_RST_SZ 1
+#define HCI_CLK_EN_MSK 0x00000001
+#define HCI_CLK_EN_I_MSK 0xfffffffe
+#define HCI_CLK_EN_SFT 0
+#define HCI_CLK_EN_HI 0
+#define HCI_CLK_EN_SZ 1
+#define CO_PROC_CLK_EN_MSK 0x00000002
+#define CO_PROC_CLK_EN_I_MSK 0xfffffffd
+#define CO_PROC_CLK_EN_SFT 1
+#define CO_PROC_CLK_EN_HI 1
+#define CO_PROC_CLK_EN_SZ 1
+#define MTX_MISC_CLK_EN_MSK 0x00000008
+#define MTX_MISC_CLK_EN_I_MSK 0xfffffff7
+#define MTX_MISC_CLK_EN_SFT 3
+#define MTX_MISC_CLK_EN_HI 3
+#define MTX_MISC_CLK_EN_SZ 1
+#define MTX_QUE_CLK_EN_MSK 0x00000010
+#define MTX_QUE_CLK_EN_I_MSK 0xffffffef
+#define MTX_QUE_CLK_EN_SFT 4
+#define MTX_QUE_CLK_EN_HI 4
+#define MTX_QUE_CLK_EN_SZ 1
+#define MRX_CLK_EN_MSK 0x00000020
+#define MRX_CLK_EN_I_MSK 0xffffffdf
+#define MRX_CLK_EN_SFT 5
+#define MRX_CLK_EN_HI 5
+#define MRX_CLK_EN_SZ 1
+#define AMPDU_CLK_EN_MSK 0x00000040
+#define AMPDU_CLK_EN_I_MSK 0xffffffbf
+#define AMPDU_CLK_EN_SFT 6
+#define AMPDU_CLK_EN_HI 6
+#define AMPDU_CLK_EN_SZ 1
+#define MMU_CLK_EN_MSK 0x00000080
+#define MMU_CLK_EN_I_MSK 0xffffff7f
+#define MMU_CLK_EN_SFT 7
+#define MMU_CLK_EN_HI 7
+#define MMU_CLK_EN_SZ 1
+#define ID_MNG_CLK_EN_MSK 0x00000200
+#define ID_MNG_CLK_EN_I_MSK 0xfffffdff
+#define ID_MNG_CLK_EN_SFT 9
+#define ID_MNG_CLK_EN_HI 9
+#define ID_MNG_CLK_EN_SZ 1
+#define MBOX_CLK_EN_MSK 0x00000400
+#define MBOX_CLK_EN_I_MSK 0xfffffbff
+#define MBOX_CLK_EN_SFT 10
+#define MBOX_CLK_EN_HI 10
+#define MBOX_CLK_EN_SZ 1
+#define SCRT_CLK_EN_MSK 0x00000800
+#define SCRT_CLK_EN_I_MSK 0xfffff7ff
+#define SCRT_CLK_EN_SFT 11
+#define SCRT_CLK_EN_HI 11
+#define SCRT_CLK_EN_SZ 1
+#define MIC_CLK_EN_MSK 0x00001000
+#define MIC_CLK_EN_I_MSK 0xffffefff
+#define MIC_CLK_EN_SFT 12
+#define MIC_CLK_EN_HI 12
+#define MIC_CLK_EN_SZ 1
+#define MIB_CLK_EN_MSK 0x00002000
+#define MIB_CLK_EN_I_MSK 0xffffdfff
+#define MIB_CLK_EN_SFT 13
+#define MIB_CLK_EN_HI 13
+#define MIB_CLK_EN_SZ 1
+#define HCI_ENG_CLK_EN_MSK 0x00000001
+#define HCI_ENG_CLK_EN_I_MSK 0xfffffffe
+#define HCI_ENG_CLK_EN_SFT 0
+#define HCI_ENG_CLK_EN_HI 0
+#define HCI_ENG_CLK_EN_SZ 1
+#define CO_PROC_ENG_CLK_EN_MSK 0x00000002
+#define CO_PROC_ENG_CLK_EN_I_MSK 0xfffffffd
+#define CO_PROC_ENG_CLK_EN_SFT 1
+#define CO_PROC_ENG_CLK_EN_HI 1
+#define CO_PROC_ENG_CLK_EN_SZ 1
+#define MTX_MISC_ENG_CLK_EN_MSK 0x00000008
+#define MTX_MISC_ENG_CLK_EN_I_MSK 0xfffffff7
+#define MTX_MISC_ENG_CLK_EN_SFT 3
+#define MTX_MISC_ENG_CLK_EN_HI 3
+#define MTX_MISC_ENG_CLK_EN_SZ 1
+#define MTX_QUE_ENG_CLK_EN_MSK 0x00000010
+#define MTX_QUE_ENG_CLK_EN_I_MSK 0xffffffef
+#define MTX_QUE_ENG_CLK_EN_SFT 4
+#define MTX_QUE_ENG_CLK_EN_HI 4
+#define MTX_QUE_ENG_CLK_EN_SZ 1
+#define MRX_ENG_CLK_EN_MSK 0x00000020
+#define MRX_ENG_CLK_EN_I_MSK 0xffffffdf
+#define MRX_ENG_CLK_EN_SFT 5
+#define MRX_ENG_CLK_EN_HI 5
+#define MRX_ENG_CLK_EN_SZ 1
+#define AMPDU_ENG_CLK_EN_MSK 0x00000040
+#define AMPDU_ENG_CLK_EN_I_MSK 0xffffffbf
+#define AMPDU_ENG_CLK_EN_SFT 6
+#define AMPDU_ENG_CLK_EN_HI 6
+#define AMPDU_ENG_CLK_EN_SZ 1
+#define ID_MNG_ENG_CLK_EN_MSK 0x00001000
+#define ID_MNG_ENG_CLK_EN_I_MSK 0xffffefff
+#define ID_MNG_ENG_CLK_EN_SFT 12
+#define ID_MNG_ENG_CLK_EN_HI 12
+#define ID_MNG_ENG_CLK_EN_SZ 1
+#define MBOX_ENG_CLK_EN_MSK 0x00002000
+#define MBOX_ENG_CLK_EN_I_MSK 0xffffdfff
+#define MBOX_ENG_CLK_EN_SFT 13
+#define MBOX_ENG_CLK_EN_HI 13
+#define MBOX_ENG_CLK_EN_SZ 1
+#define SCRT_ENG_CLK_EN_MSK 0x00004000
+#define SCRT_ENG_CLK_EN_I_MSK 0xffffbfff
+#define SCRT_ENG_CLK_EN_SFT 14
+#define SCRT_ENG_CLK_EN_HI 14
+#define SCRT_ENG_CLK_EN_SZ 1
+#define MIC_ENG_CLK_EN_MSK 0x00008000
+#define MIC_ENG_CLK_EN_I_MSK 0xffff7fff
+#define MIC_ENG_CLK_EN_SFT 15
+#define MIC_ENG_CLK_EN_HI 15
+#define MIC_ENG_CLK_EN_SZ 1
+#define CO_PROC_CSR_CLK_EN_MSK 0x00000002
+#define CO_PROC_CSR_CLK_EN_I_MSK 0xfffffffd
+#define CO_PROC_CSR_CLK_EN_SFT 1
+#define CO_PROC_CSR_CLK_EN_HI 1
+#define CO_PROC_CSR_CLK_EN_SZ 1
+#define MRX_CSR_CLK_EN_MSK 0x00000400
+#define MRX_CSR_CLK_EN_I_MSK 0xfffffbff
+#define MRX_CSR_CLK_EN_SFT 10
+#define MRX_CSR_CLK_EN_HI 10
+#define MRX_CSR_CLK_EN_SZ 1
+#define AMPDU_CSR_CLK_EN_MSK 0x00000800
+#define AMPDU_CSR_CLK_EN_I_MSK 0xfffff7ff
+#define AMPDU_CSR_CLK_EN_SFT 11
+#define AMPDU_CSR_CLK_EN_HI 11
+#define AMPDU_CSR_CLK_EN_SZ 1
+#define SCRT_CSR_CLK_EN_MSK 0x00002000
+#define SCRT_CSR_CLK_EN_I_MSK 0xffffdfff
+#define SCRT_CSR_CLK_EN_SFT 13
+#define SCRT_CSR_CLK_EN_HI 13
+#define SCRT_CSR_CLK_EN_SZ 1
+#define ID_MNG_CSR_CLK_EN_MSK 0x00004000
+#define ID_MNG_CSR_CLK_EN_I_MSK 0xffffbfff
+#define ID_MNG_CSR_CLK_EN_SFT 14
+#define ID_MNG_CSR_CLK_EN_HI 14
+#define ID_MNG_CSR_CLK_EN_SZ 1
+#define MBOX_CSR_CLK_EN_MSK 0x00008000
+#define MBOX_CSR_CLK_EN_I_MSK 0xffff7fff
+#define MBOX_CSR_CLK_EN_SFT 15
+#define MBOX_CSR_CLK_EN_HI 15
+#define MBOX_CSR_CLK_EN_SZ 1
+#define OP_MODE_MSK 0x00000003
+#define OP_MODE_I_MSK 0xfffffffc
+#define OP_MODE_SFT 0
+#define OP_MODE_HI 1
+#define OP_MODE_SZ 2
+#define HT_MODE_MSK 0x0000000c
+#define HT_MODE_I_MSK 0xfffffff3
+#define HT_MODE_SFT 2
+#define HT_MODE_HI 3
+#define HT_MODE_SZ 2
+#define QOS_EN_MSK 0x00000010
+#define QOS_EN_I_MSK 0xffffffef
+#define QOS_EN_SFT 4
+#define QOS_EN_HI 4
+#define QOS_EN_SZ 1
+#define PB_OFFSET_MSK 0x0000ff00
+#define PB_OFFSET_I_MSK 0xffff00ff
+#define PB_OFFSET_SFT 8
+#define PB_OFFSET_HI 15
+#define PB_OFFSET_SZ 8
+#define SNIFFER_MODE_MSK 0x00010000
+#define SNIFFER_MODE_I_MSK 0xfffeffff
+#define SNIFFER_MODE_SFT 16
+#define SNIFFER_MODE_HI 16
+#define SNIFFER_MODE_SZ 1
+#define DUP_FLT_MSK 0x00020000
+#define DUP_FLT_I_MSK 0xfffdffff
+#define DUP_FLT_SFT 17
+#define DUP_FLT_HI 17
+#define DUP_FLT_SZ 1
+#define TX_PKT_RSVD_MSK 0x001c0000
+#define TX_PKT_RSVD_I_MSK 0xffe3ffff
+#define TX_PKT_RSVD_SFT 18
+#define TX_PKT_RSVD_HI 20
+#define TX_PKT_RSVD_SZ 3
+#define AMPDU_SNIFFER_MSK 0x00200000
+#define AMPDU_SNIFFER_I_MSK 0xffdfffff
+#define AMPDU_SNIFFER_SFT 21
+#define AMPDU_SNIFFER_HI 21
+#define AMPDU_SNIFFER_SZ 1
+#define REASON_TRAP0_MSK 0xffffffff
+#define REASON_TRAP0_I_MSK 0x00000000
+#define REASON_TRAP0_SFT 0
+#define REASON_TRAP0_HI 31
+#define REASON_TRAP0_SZ 32
+#define REASON_TRAP1_MSK 0xffffffff
+#define REASON_TRAP1_I_MSK 0x00000000
+#define REASON_TRAP1_SFT 0
+#define REASON_TRAP1_HI 31
+#define REASON_TRAP1_SZ 32
+#define BSSID_31_0_MSK 0xffffffff
+#define BSSID_31_0_I_MSK 0x00000000
+#define BSSID_31_0_SFT 0
+#define BSSID_31_0_HI 31
+#define BSSID_31_0_SZ 32
+#define BSSID_47_32_MSK 0x0000ffff
+#define BSSID_47_32_I_MSK 0xffff0000
+#define BSSID_47_32_SFT 0
+#define BSSID_47_32_HI 15
+#define BSSID_47_32_SZ 16
+#define SCRT_STATE_MSK 0x0000000f
+#define SCRT_STATE_I_MSK 0xfffffff0
+#define SCRT_STATE_SFT 0
+#define SCRT_STATE_HI 3
+#define SCRT_STATE_SZ 4
+#define STA_MAC_31_0_MSK 0xffffffff
+#define STA_MAC_31_0_I_MSK 0x00000000
+#define STA_MAC_31_0_SFT 0
+#define STA_MAC_31_0_HI 31
+#define STA_MAC_31_0_SZ 32
+#define STA_MAC_47_32_MSK 0x0000ffff
+#define STA_MAC_47_32_I_MSK 0xffff0000
+#define STA_MAC_47_32_SFT 0
+#define STA_MAC_47_32_HI 15
+#define STA_MAC_47_32_SZ 16
+#define PAIR_SCRT_MSK 0x00000007
+#define PAIR_SCRT_I_MSK 0xfffffff8
+#define PAIR_SCRT_SFT 0
+#define PAIR_SCRT_HI 2
+#define PAIR_SCRT_SZ 3
+#define GRP_SCRT_MSK 0x00000038
+#define GRP_SCRT_I_MSK 0xffffffc7
+#define GRP_SCRT_SFT 3
+#define GRP_SCRT_HI 5
+#define GRP_SCRT_SZ 3
+#define SCRT_PKT_ID_MSK 0x00001fc0
+#define SCRT_PKT_ID_I_MSK 0xffffe03f
+#define SCRT_PKT_ID_SFT 6
+#define SCRT_PKT_ID_HI 12
+#define SCRT_PKT_ID_SZ 7
+#define SCRT_RPLY_IGNORE_MSK 0x00010000
+#define SCRT_RPLY_IGNORE_I_MSK 0xfffeffff
+#define SCRT_RPLY_IGNORE_SFT 16
+#define SCRT_RPLY_IGNORE_HI 16
+#define SCRT_RPLY_IGNORE_SZ 1
+#define COEXIST_EN_MSK 0x00000001
+#define COEXIST_EN_I_MSK 0xfffffffe
+#define COEXIST_EN_SFT 0
+#define COEXIST_EN_HI 0
+#define COEXIST_EN_SZ 1
+#define WIRE_MODE_MSK 0x0000000e
+#define WIRE_MODE_I_MSK 0xfffffff1
+#define WIRE_MODE_SFT 1
+#define WIRE_MODE_HI 3
+#define WIRE_MODE_SZ 3
+#define WL_RX_PRI_MSK 0x00000010
+#define WL_RX_PRI_I_MSK 0xffffffef
+#define WL_RX_PRI_SFT 4
+#define WL_RX_PRI_HI 4
+#define WL_RX_PRI_SZ 1
+#define WL_TX_PRI_MSK 0x00000020
+#define WL_TX_PRI_I_MSK 0xffffffdf
+#define WL_TX_PRI_SFT 5
+#define WL_TX_PRI_HI 5
+#define WL_TX_PRI_SZ 1
+#define GURAN_USE_EN_MSK 0x00000100
+#define GURAN_USE_EN_I_MSK 0xfffffeff
+#define GURAN_USE_EN_SFT 8
+#define GURAN_USE_EN_HI 8
+#define GURAN_USE_EN_SZ 1
+#define GURAN_USE_CTRL_MSK 0x00000200
+#define GURAN_USE_CTRL_I_MSK 0xfffffdff
+#define GURAN_USE_CTRL_SFT 9
+#define GURAN_USE_CTRL_HI 9
+#define GURAN_USE_CTRL_SZ 1
+#define BEACON_TIMEOUT_EN_MSK 0x00000400
+#define BEACON_TIMEOUT_EN_I_MSK 0xfffffbff
+#define BEACON_TIMEOUT_EN_SFT 10
+#define BEACON_TIMEOUT_EN_HI 10
+#define BEACON_TIMEOUT_EN_SZ 1
+#define WLAN_ACT_POL_MSK 0x00000800
+#define WLAN_ACT_POL_I_MSK 0xfffff7ff
+#define WLAN_ACT_POL_SFT 11
+#define WLAN_ACT_POL_HI 11
+#define WLAN_ACT_POL_SZ 1
+#define DUAL_ANT_EN_MSK 0x00001000
+#define DUAL_ANT_EN_I_MSK 0xffffefff
+#define DUAL_ANT_EN_SFT 12
+#define DUAL_ANT_EN_HI 12
+#define DUAL_ANT_EN_SZ 1
+#define TRSW_PHY_POL_MSK 0x00010000
+#define TRSW_PHY_POL_I_MSK 0xfffeffff
+#define TRSW_PHY_POL_SFT 16
+#define TRSW_PHY_POL_HI 16
+#define TRSW_PHY_POL_SZ 1
+#define WIFI_TX_SW_POL_MSK 0x00020000
+#define WIFI_TX_SW_POL_I_MSK 0xfffdffff
+#define WIFI_TX_SW_POL_SFT 17
+#define WIFI_TX_SW_POL_HI 17
+#define WIFI_TX_SW_POL_SZ 1
+#define WIFI_RX_SW_POL_MSK 0x00040000
+#define WIFI_RX_SW_POL_I_MSK 0xfffbffff
+#define WIFI_RX_SW_POL_SFT 18
+#define WIFI_RX_SW_POL_HI 18
+#define WIFI_RX_SW_POL_SZ 1
+#define BT_SW_POL_MSK 0x00080000
+#define BT_SW_POL_I_MSK 0xfff7ffff
+#define BT_SW_POL_SFT 19
+#define BT_SW_POL_HI 19
+#define BT_SW_POL_SZ 1
+#define BT_PRI_SMP_TIME_MSK 0x000000ff
+#define BT_PRI_SMP_TIME_I_MSK 0xffffff00
+#define BT_PRI_SMP_TIME_SFT 0
+#define BT_PRI_SMP_TIME_HI 7
+#define BT_PRI_SMP_TIME_SZ 8
+#define BT_STA_SMP_TIME_MSK 0x0000ff00
+#define BT_STA_SMP_TIME_I_MSK 0xffff00ff
+#define BT_STA_SMP_TIME_SFT 8
+#define BT_STA_SMP_TIME_HI 15
+#define BT_STA_SMP_TIME_SZ 8
+#define BEACON_TIMEOUT_MSK 0x00ff0000
+#define BEACON_TIMEOUT_I_MSK 0xff00ffff
+#define BEACON_TIMEOUT_SFT 16
+#define BEACON_TIMEOUT_HI 23
+#define BEACON_TIMEOUT_SZ 8
+#define WLAN_REMAIN_TIME_MSK 0xff000000
+#define WLAN_REMAIN_TIME_I_MSK 0x00ffffff
+#define WLAN_REMAIN_TIME_SFT 24
+#define WLAN_REMAIN_TIME_HI 31
+#define WLAN_REMAIN_TIME_SZ 8
+#define SW_MANUAL_EN_MSK 0x00000001
+#define SW_MANUAL_EN_I_MSK 0xfffffffe
+#define SW_MANUAL_EN_SFT 0
+#define SW_MANUAL_EN_HI 0
+#define SW_MANUAL_EN_SZ 1
+#define SW_WL_TX_MSK 0x00000002
+#define SW_WL_TX_I_MSK 0xfffffffd
+#define SW_WL_TX_SFT 1
+#define SW_WL_TX_HI 1
+#define SW_WL_TX_SZ 1
+#define SW_WL_RX_MSK 0x00000004
+#define SW_WL_RX_I_MSK 0xfffffffb
+#define SW_WL_RX_SFT 2
+#define SW_WL_RX_HI 2
+#define SW_WL_RX_SZ 1
+#define SW_BT_TRX_MSK 0x00000008
+#define SW_BT_TRX_I_MSK 0xfffffff7
+#define SW_BT_TRX_SFT 3
+#define SW_BT_TRX_HI 3
+#define SW_BT_TRX_SZ 1
+#define BT_TXBAR_MANUAL_EN_MSK 0x00000010
+#define BT_TXBAR_MANUAL_EN_I_MSK 0xffffffef
+#define BT_TXBAR_MANUAL_EN_SFT 4
+#define BT_TXBAR_MANUAL_EN_HI 4
+#define BT_TXBAR_MANUAL_EN_SZ 1
+#define BT_TXBAR_SET_MSK 0x00000020
+#define BT_TXBAR_SET_I_MSK 0xffffffdf
+#define BT_TXBAR_SET_SFT 5
+#define BT_TXBAR_SET_HI 5
+#define BT_TXBAR_SET_SZ 1
+#define BT_BUSY_MANUAL_EN_MSK 0x00000100
+#define BT_BUSY_MANUAL_EN_I_MSK 0xfffffeff
+#define BT_BUSY_MANUAL_EN_SFT 8
+#define BT_BUSY_MANUAL_EN_HI 8
+#define BT_BUSY_MANUAL_EN_SZ 1
+#define BT_BUSY_SET_MSK 0x00000200
+#define BT_BUSY_SET_I_MSK 0xfffffdff
+#define BT_BUSY_SET_SFT 9
+#define BT_BUSY_SET_HI 9
+#define BT_BUSY_SET_SZ 1
+#define G0_PKT_CLS_MIB_EN_MSK 0x00000004
+#define G0_PKT_CLS_MIB_EN_I_MSK 0xfffffffb
+#define G0_PKT_CLS_MIB_EN_SFT 2
+#define G0_PKT_CLS_MIB_EN_HI 2
+#define G0_PKT_CLS_MIB_EN_SZ 1
+#define G0_PKT_CLS_ONGOING_MSK 0x00000008
+#define G0_PKT_CLS_ONGOING_I_MSK 0xfffffff7
+#define G0_PKT_CLS_ONGOING_SFT 3
+#define G0_PKT_CLS_ONGOING_HI 3
+#define G0_PKT_CLS_ONGOING_SZ 1
+#define G1_PKT_CLS_MIB_EN_MSK 0x00000010
+#define G1_PKT_CLS_MIB_EN_I_MSK 0xffffffef
+#define G1_PKT_CLS_MIB_EN_SFT 4
+#define G1_PKT_CLS_MIB_EN_HI 4
+#define G1_PKT_CLS_MIB_EN_SZ 1
+#define G1_PKT_CLS_ONGOING_MSK 0x00000020
+#define G1_PKT_CLS_ONGOING_I_MSK 0xffffffdf
+#define G1_PKT_CLS_ONGOING_SFT 5
+#define G1_PKT_CLS_ONGOING_HI 5
+#define G1_PKT_CLS_ONGOING_SZ 1
+#define Q0_PKT_CLS_MIB_EN_MSK 0x00000040
+#define Q0_PKT_CLS_MIB_EN_I_MSK 0xffffffbf
+#define Q0_PKT_CLS_MIB_EN_SFT 6
+#define Q0_PKT_CLS_MIB_EN_HI 6
+#define Q0_PKT_CLS_MIB_EN_SZ 1
+#define Q0_PKT_CLS_ONGOING_MSK 0x00000080
+#define Q0_PKT_CLS_ONGOING_I_MSK 0xffffff7f
+#define Q0_PKT_CLS_ONGOING_SFT 7
+#define Q0_PKT_CLS_ONGOING_HI 7
+#define Q0_PKT_CLS_ONGOING_SZ 1
+#define Q1_PKT_CLS_MIB_EN_MSK 0x00000100
+#define Q1_PKT_CLS_MIB_EN_I_MSK 0xfffffeff
+#define Q1_PKT_CLS_MIB_EN_SFT 8
+#define Q1_PKT_CLS_MIB_EN_HI 8
+#define Q1_PKT_CLS_MIB_EN_SZ 1
+#define Q1_PKT_CLS_ONGOING_MSK 0x00000200
+#define Q1_PKT_CLS_ONGOING_I_MSK 0xfffffdff
+#define Q1_PKT_CLS_ONGOING_SFT 9
+#define Q1_PKT_CLS_ONGOING_HI 9
+#define Q1_PKT_CLS_ONGOING_SZ 1
+#define Q2_PKT_CLS_MIB_EN_MSK 0x00000400
+#define Q2_PKT_CLS_MIB_EN_I_MSK 0xfffffbff
+#define Q2_PKT_CLS_MIB_EN_SFT 10
+#define Q2_PKT_CLS_MIB_EN_HI 10
+#define Q2_PKT_CLS_MIB_EN_SZ 1
+#define Q2_PKT_CLS_ONGOING_MSK 0x00000800
+#define Q2_PKT_CLS_ONGOING_I_MSK 0xfffff7ff
+#define Q2_PKT_CLS_ONGOING_SFT 11
+#define Q2_PKT_CLS_ONGOING_HI 11
+#define Q2_PKT_CLS_ONGOING_SZ 1
+#define Q3_PKT_CLS_MIB_EN_MSK 0x00001000
+#define Q3_PKT_CLS_MIB_EN_I_MSK 0xffffefff
+#define Q3_PKT_CLS_MIB_EN_SFT 12
+#define Q3_PKT_CLS_MIB_EN_HI 12
+#define Q3_PKT_CLS_MIB_EN_SZ 1
+#define Q3_PKT_CLS_ONGOING_MSK 0x00002000
+#define Q3_PKT_CLS_ONGOING_I_MSK 0xffffdfff
+#define Q3_PKT_CLS_ONGOING_SFT 13
+#define Q3_PKT_CLS_ONGOING_HI 13
+#define Q3_PKT_CLS_ONGOING_SZ 1
+#define SCRT_PKT_CLS_MIB_EN_MSK 0x00004000
+#define SCRT_PKT_CLS_MIB_EN_I_MSK 0xffffbfff
+#define SCRT_PKT_CLS_MIB_EN_SFT 14
+#define SCRT_PKT_CLS_MIB_EN_HI 14
+#define SCRT_PKT_CLS_MIB_EN_SZ 1
+#define SCRT_PKT_CLS_ONGOING_MSK 0x00008000
+#define SCRT_PKT_CLS_ONGOING_I_MSK 0xffff7fff
+#define SCRT_PKT_CLS_ONGOING_SFT 15
+#define SCRT_PKT_CLS_ONGOING_HI 15
+#define SCRT_PKT_CLS_ONGOING_SZ 1
+#define MISC_PKT_CLS_MIB_EN_MSK 0x00010000
+#define MISC_PKT_CLS_MIB_EN_I_MSK 0xfffeffff
+#define MISC_PKT_CLS_MIB_EN_SFT 16
+#define MISC_PKT_CLS_MIB_EN_HI 16
+#define MISC_PKT_CLS_MIB_EN_SZ 1
+#define MISC_PKT_CLS_ONGOING_MSK 0x00020000
+#define MISC_PKT_CLS_ONGOING_I_MSK 0xfffdffff
+#define MISC_PKT_CLS_ONGOING_SFT 17
+#define MISC_PKT_CLS_ONGOING_HI 17
+#define MISC_PKT_CLS_ONGOING_SZ 1
+#define MTX_WSID0_SUCC_MSK 0x0000ffff
+#define MTX_WSID0_SUCC_I_MSK 0xffff0000
+#define MTX_WSID0_SUCC_SFT 0
+#define MTX_WSID0_SUCC_HI 15
+#define MTX_WSID0_SUCC_SZ 16
+#define MTX_WSID0_FRM_MSK 0x0000ffff
+#define MTX_WSID0_FRM_I_MSK 0xffff0000
+#define MTX_WSID0_FRM_SFT 0
+#define MTX_WSID0_FRM_HI 15
+#define MTX_WSID0_FRM_SZ 16
+#define MTX_WSID0_RETRY_MSK 0x0000ffff
+#define MTX_WSID0_RETRY_I_MSK 0xffff0000
+#define MTX_WSID0_RETRY_SFT 0
+#define MTX_WSID0_RETRY_HI 15
+#define MTX_WSID0_RETRY_SZ 16
+#define MTX_WSID0_TOTAL_MSK 0x0000ffff
+#define MTX_WSID0_TOTAL_I_MSK 0xffff0000
+#define MTX_WSID0_TOTAL_SFT 0
+#define MTX_WSID0_TOTAL_HI 15
+#define MTX_WSID0_TOTAL_SZ 16
+#define MTX_GRP_MSK 0x000fffff
+#define MTX_GRP_I_MSK 0xfff00000
+#define MTX_GRP_SFT 0
+#define MTX_GRP_HI 19
+#define MTX_GRP_SZ 20
+#define MTX_FAIL_MSK 0x0000ffff
+#define MTX_FAIL_I_MSK 0xffff0000
+#define MTX_FAIL_SFT 0
+#define MTX_FAIL_HI 15
+#define MTX_FAIL_SZ 16
+#define MTX_RETRY_MSK 0x000fffff
+#define MTX_RETRY_I_MSK 0xfff00000
+#define MTX_RETRY_SFT 0
+#define MTX_RETRY_HI 19
+#define MTX_RETRY_SZ 20
+#define MTX_MULTI_RETRY_MSK 0x000fffff
+#define MTX_MULTI_RETRY_I_MSK 0xfff00000
+#define MTX_MULTI_RETRY_SFT 0
+#define MTX_MULTI_RETRY_HI 19
+#define MTX_MULTI_RETRY_SZ 20
+#define MTX_RTS_SUCC_MSK 0x0000ffff
+#define MTX_RTS_SUCC_I_MSK 0xffff0000
+#define MTX_RTS_SUCC_SFT 0
+#define MTX_RTS_SUCC_HI 15
+#define MTX_RTS_SUCC_SZ 16
+#define MTX_RTS_FAIL_MSK 0x0000ffff
+#define MTX_RTS_FAIL_I_MSK 0xffff0000
+#define MTX_RTS_FAIL_SFT 0
+#define MTX_RTS_FAIL_HI 15
+#define MTX_RTS_FAIL_SZ 16
+#define MTX_ACK_FAIL_MSK 0x0000ffff
+#define MTX_ACK_FAIL_I_MSK 0xffff0000
+#define MTX_ACK_FAIL_SFT 0
+#define MTX_ACK_FAIL_HI 15
+#define MTX_ACK_FAIL_SZ 16
+#define MTX_FRM_MSK 0x000fffff
+#define MTX_FRM_I_MSK 0xfff00000
+#define MTX_FRM_SFT 0
+#define MTX_FRM_HI 19
+#define MTX_FRM_SZ 20
+#define MTX_ACK_TX_MSK 0x0000ffff
+#define MTX_ACK_TX_I_MSK 0xffff0000
+#define MTX_ACK_TX_SFT 0
+#define MTX_ACK_TX_HI 15
+#define MTX_ACK_TX_SZ 16
+#define MTX_CTS_TX_MSK 0x0000ffff
+#define MTX_CTS_TX_I_MSK 0xffff0000
+#define MTX_CTS_TX_SFT 0
+#define MTX_CTS_TX_HI 15
+#define MTX_CTS_TX_SZ 16
+#define MRX_DUP_MSK 0x0000ffff
+#define MRX_DUP_I_MSK 0xffff0000
+#define MRX_DUP_SFT 0
+#define MRX_DUP_HI 15
+#define MRX_DUP_SZ 16
+#define MRX_FRG_MSK 0x000fffff
+#define MRX_FRG_I_MSK 0xfff00000
+#define MRX_FRG_SFT 0
+#define MRX_FRG_HI 19
+#define MRX_FRG_SZ 20
+#define MRX_GRP_MSK 0x000fffff
+#define MRX_GRP_I_MSK 0xfff00000
+#define MRX_GRP_SFT 0
+#define MRX_GRP_HI 19
+#define MRX_GRP_SZ 20
+#define MRX_FCS_ERR_MSK 0x0000ffff
+#define MRX_FCS_ERR_I_MSK 0xffff0000
+#define MRX_FCS_ERR_SFT 0
+#define MRX_FCS_ERR_HI 15
+#define MRX_FCS_ERR_SZ 16
+#define MRX_FCS_SUC_MSK 0x0000ffff
+#define MRX_FCS_SUC_I_MSK 0xffff0000
+#define MRX_FCS_SUC_SFT 0
+#define MRX_FCS_SUC_HI 15
+#define MRX_FCS_SUC_SZ 16
+#define MRX_MISS_MSK 0x0000ffff
+#define MRX_MISS_I_MSK 0xffff0000
+#define MRX_MISS_SFT 0
+#define MRX_MISS_HI 15
+#define MRX_MISS_SZ 16
+#define MRX_ALC_FAIL_MSK 0x0000ffff
+#define MRX_ALC_FAIL_I_MSK 0xffff0000
+#define MRX_ALC_FAIL_SFT 0
+#define MRX_ALC_FAIL_HI 15
+#define MRX_ALC_FAIL_SZ 16
+#define MRX_DAT_NTF_MSK 0x0000ffff
+#define MRX_DAT_NTF_I_MSK 0xffff0000
+#define MRX_DAT_NTF_SFT 0
+#define MRX_DAT_NTF_HI 15
+#define MRX_DAT_NTF_SZ 16
+#define MRX_RTS_NTF_MSK 0x0000ffff
+#define MRX_RTS_NTF_I_MSK 0xffff0000
+#define MRX_RTS_NTF_SFT 0
+#define MRX_RTS_NTF_HI 15
+#define MRX_RTS_NTF_SZ 16
+#define MRX_CTS_NTF_MSK 0x0000ffff
+#define MRX_CTS_NTF_I_MSK 0xffff0000
+#define MRX_CTS_NTF_SFT 0
+#define MRX_CTS_NTF_HI 15
+#define MRX_CTS_NTF_SZ 16
+#define MRX_ACK_NTF_MSK 0x0000ffff
+#define MRX_ACK_NTF_I_MSK 0xffff0000
+#define MRX_ACK_NTF_SFT 0
+#define MRX_ACK_NTF_HI 15
+#define MRX_ACK_NTF_SZ 16
+#define MRX_BA_NTF_MSK 0x0000ffff
+#define MRX_BA_NTF_I_MSK 0xffff0000
+#define MRX_BA_NTF_SFT 0
+#define MRX_BA_NTF_HI 15
+#define MRX_BA_NTF_SZ 16
+#define MRX_DATA_NTF_MSK 0x0000ffff
+#define MRX_DATA_NTF_I_MSK 0xffff0000
+#define MRX_DATA_NTF_SFT 0
+#define MRX_DATA_NTF_HI 15
+#define MRX_DATA_NTF_SZ 16
+#define MRX_MNG_NTF_MSK 0x0000ffff
+#define MRX_MNG_NTF_I_MSK 0xffff0000
+#define MRX_MNG_NTF_SFT 0
+#define MRX_MNG_NTF_HI 15
+#define MRX_MNG_NTF_SZ 16
+#define MRX_DAT_CRC_NTF_MSK 0x0000ffff
+#define MRX_DAT_CRC_NTF_I_MSK 0xffff0000
+#define MRX_DAT_CRC_NTF_SFT 0
+#define MRX_DAT_CRC_NTF_HI 15
+#define MRX_DAT_CRC_NTF_SZ 16
+#define MRX_BAR_NTF_MSK 0x0000ffff
+#define MRX_BAR_NTF_I_MSK 0xffff0000
+#define MRX_BAR_NTF_SFT 0
+#define MRX_BAR_NTF_HI 15
+#define MRX_BAR_NTF_SZ 16
+#define MRX_MB_MISS_MSK 0x0000ffff
+#define MRX_MB_MISS_I_MSK 0xffff0000
+#define MRX_MB_MISS_SFT 0
+#define MRX_MB_MISS_HI 15
+#define MRX_MB_MISS_SZ 16
+#define MRX_NIDLE_MISS_MSK 0x0000ffff
+#define MRX_NIDLE_MISS_I_MSK 0xffff0000
+#define MRX_NIDLE_MISS_SFT 0
+#define MRX_NIDLE_MISS_HI 15
+#define MRX_NIDLE_MISS_SZ 16
+#define MRX_CSR_NTF_MSK 0x0000ffff
+#define MRX_CSR_NTF_I_MSK 0xffff0000
+#define MRX_CSR_NTF_SFT 0
+#define MRX_CSR_NTF_HI 15
+#define MRX_CSR_NTF_SZ 16
+#define DBG_Q0_SUCC_MSK 0x0000ffff
+#define DBG_Q0_SUCC_I_MSK 0xffff0000
+#define DBG_Q0_SUCC_SFT 0
+#define DBG_Q0_SUCC_HI 15
+#define DBG_Q0_SUCC_SZ 16
+#define DBG_Q0_FAIL_MSK 0x0000ffff
+#define DBG_Q0_FAIL_I_MSK 0xffff0000
+#define DBG_Q0_FAIL_SFT 0
+#define DBG_Q0_FAIL_HI 15
+#define DBG_Q0_FAIL_SZ 16
+#define DBG_Q0_ACK_SUCC_MSK 0x0000ffff
+#define DBG_Q0_ACK_SUCC_I_MSK 0xffff0000
+#define DBG_Q0_ACK_SUCC_SFT 0
+#define DBG_Q0_ACK_SUCC_HI 15
+#define DBG_Q0_ACK_SUCC_SZ 16
+#define DBG_Q0_ACK_FAIL_MSK 0x0000ffff
+#define DBG_Q0_ACK_FAIL_I_MSK 0xffff0000
+#define DBG_Q0_ACK_FAIL_SFT 0
+#define DBG_Q0_ACK_FAIL_HI 15
+#define DBG_Q0_ACK_FAIL_SZ 16
+#define DBG_Q1_SUCC_MSK 0x0000ffff
+#define DBG_Q1_SUCC_I_MSK 0xffff0000
+#define DBG_Q1_SUCC_SFT 0
+#define DBG_Q1_SUCC_HI 15
+#define DBG_Q1_SUCC_SZ 16
+#define DBG_Q1_FAIL_MSK 0x0000ffff
+#define DBG_Q1_FAIL_I_MSK 0xffff0000
+#define DBG_Q1_FAIL_SFT 0
+#define DBG_Q1_FAIL_HI 15
+#define DBG_Q1_FAIL_SZ 16
+#define DBG_Q1_ACK_SUCC_MSK 0x0000ffff
+#define DBG_Q1_ACK_SUCC_I_MSK 0xffff0000
+#define DBG_Q1_ACK_SUCC_SFT 0
+#define DBG_Q1_ACK_SUCC_HI 15
+#define DBG_Q1_ACK_SUCC_SZ 16
+#define DBG_Q1_ACK_FAIL_MSK 0x0000ffff
+#define DBG_Q1_ACK_FAIL_I_MSK 0xffff0000
+#define DBG_Q1_ACK_FAIL_SFT 0
+#define DBG_Q1_ACK_FAIL_HI 15
+#define DBG_Q1_ACK_FAIL_SZ 16
+#define DBG_Q2_SUCC_MSK 0x0000ffff
+#define DBG_Q2_SUCC_I_MSK 0xffff0000
+#define DBG_Q2_SUCC_SFT 0
+#define DBG_Q2_SUCC_HI 15
+#define DBG_Q2_SUCC_SZ 16
+#define DBG_Q2_FAIL_MSK 0x0000ffff
+#define DBG_Q2_FAIL_I_MSK 0xffff0000
+#define DBG_Q2_FAIL_SFT 0
+#define DBG_Q2_FAIL_HI 15
+#define DBG_Q2_FAIL_SZ 16
+#define DBG_Q2_ACK_SUCC_MSK 0x0000ffff
+#define DBG_Q2_ACK_SUCC_I_MSK 0xffff0000
+#define DBG_Q2_ACK_SUCC_SFT 0
+#define DBG_Q2_ACK_SUCC_HI 15
+#define DBG_Q2_ACK_SUCC_SZ 16
+#define DBG_Q2_ACK_FAIL_MSK 0x0000ffff
+#define DBG_Q2_ACK_FAIL_I_MSK 0xffff0000
+#define DBG_Q2_ACK_FAIL_SFT 0
+#define DBG_Q2_ACK_FAIL_HI 15
+#define DBG_Q2_ACK_FAIL_SZ 16
+#define DBG_Q3_SUCC_MSK 0x0000ffff
+#define DBG_Q3_SUCC_I_MSK 0xffff0000
+#define DBG_Q3_SUCC_SFT 0
+#define DBG_Q3_SUCC_HI 15
+#define DBG_Q3_SUCC_SZ 16
+#define DBG_Q3_FAIL_MSK 0x0000ffff
+#define DBG_Q3_FAIL_I_MSK 0xffff0000
+#define DBG_Q3_FAIL_SFT 0
+#define DBG_Q3_FAIL_HI 15
+#define DBG_Q3_FAIL_SZ 16
+#define DBG_Q3_ACK_SUCC_MSK 0x0000ffff
+#define DBG_Q3_ACK_SUCC_I_MSK 0xffff0000
+#define DBG_Q3_ACK_SUCC_SFT 0
+#define DBG_Q3_ACK_SUCC_HI 15
+#define DBG_Q3_ACK_SUCC_SZ 16
+#define DBG_Q3_ACK_FAIL_MSK 0x0000ffff
+#define DBG_Q3_ACK_FAIL_I_MSK 0xffff0000
+#define DBG_Q3_ACK_FAIL_SFT 0
+#define DBG_Q3_ACK_FAIL_HI 15
+#define DBG_Q3_ACK_FAIL_SZ 16
+#define SCRT_TKIP_CERR_MSK 0x000fffff
+#define SCRT_TKIP_CERR_I_MSK 0xfff00000
+#define SCRT_TKIP_CERR_SFT 0
+#define SCRT_TKIP_CERR_HI 19
+#define SCRT_TKIP_CERR_SZ 20
+#define SCRT_TKIP_MIC_ERR_MSK 0x000fffff
+#define SCRT_TKIP_MIC_ERR_I_MSK 0xfff00000
+#define SCRT_TKIP_MIC_ERR_SFT 0
+#define SCRT_TKIP_MIC_ERR_HI 19
+#define SCRT_TKIP_MIC_ERR_SZ 20
+#define SCRT_TKIP_RPLY_MSK 0x000fffff
+#define SCRT_TKIP_RPLY_I_MSK 0xfff00000
+#define SCRT_TKIP_RPLY_SFT 0
+#define SCRT_TKIP_RPLY_HI 19
+#define SCRT_TKIP_RPLY_SZ 20
+#define SCRT_CCMP_RPLY_MSK 0x000fffff
+#define SCRT_CCMP_RPLY_I_MSK 0xfff00000
+#define SCRT_CCMP_RPLY_SFT 0
+#define SCRT_CCMP_RPLY_HI 19
+#define SCRT_CCMP_RPLY_SZ 20
+#define SCRT_CCMP_CERR_MSK 0x000fffff
+#define SCRT_CCMP_CERR_I_MSK 0xfff00000
+#define SCRT_CCMP_CERR_SFT 0
+#define SCRT_CCMP_CERR_HI 19
+#define SCRT_CCMP_CERR_SZ 20
+#define DBG_LEN_CRC_FAIL_MSK 0x0000ffff
+#define DBG_LEN_CRC_FAIL_I_MSK 0xffff0000
+#define DBG_LEN_CRC_FAIL_SFT 0
+#define DBG_LEN_CRC_FAIL_HI 15
+#define DBG_LEN_CRC_FAIL_SZ 16
+#define DBG_LEN_ALC_FAIL_MSK 0x0000ffff
+#define DBG_LEN_ALC_FAIL_I_MSK 0xffff0000
+#define DBG_LEN_ALC_FAIL_SFT 0
+#define DBG_LEN_ALC_FAIL_HI 15
+#define DBG_LEN_ALC_FAIL_SZ 16
+#define DBG_AMPDU_PASS_MSK 0x0000ffff
+#define DBG_AMPDU_PASS_I_MSK 0xffff0000
+#define DBG_AMPDU_PASS_SFT 0
+#define DBG_AMPDU_PASS_HI 15
+#define DBG_AMPDU_PASS_SZ 16
+#define DBG_AMPDU_FAIL_MSK 0x0000ffff
+#define DBG_AMPDU_FAIL_I_MSK 0xffff0000
+#define DBG_AMPDU_FAIL_SFT 0
+#define DBG_AMPDU_FAIL_HI 15
+#define DBG_AMPDU_FAIL_SZ 16
+#define RXID_ALC_CNT_FAIL_MSK 0x0000ffff
+#define RXID_ALC_CNT_FAIL_I_MSK 0xffff0000
+#define RXID_ALC_CNT_FAIL_SFT 0
+#define RXID_ALC_CNT_FAIL_HI 15
+#define RXID_ALC_CNT_FAIL_SZ 16
+#define RXID_ALC_LEN_FAIL_MSK 0x0000ffff
+#define RXID_ALC_LEN_FAIL_I_MSK 0xffff0000
+#define RXID_ALC_LEN_FAIL_SFT 0
+#define RXID_ALC_LEN_FAIL_HI 15
+#define RXID_ALC_LEN_FAIL_SZ 16
+#define CBR_RG_EN_MANUAL_MSK 0x00000001
+#define CBR_RG_EN_MANUAL_I_MSK 0xfffffffe
+#define CBR_RG_EN_MANUAL_SFT 0
+#define CBR_RG_EN_MANUAL_HI 0
+#define CBR_RG_EN_MANUAL_SZ 1
+#define CBR_RG_TX_EN_MSK 0x00000002
+#define CBR_RG_TX_EN_I_MSK 0xfffffffd
+#define CBR_RG_TX_EN_SFT 1
+#define CBR_RG_TX_EN_HI 1
+#define CBR_RG_TX_EN_SZ 1
+#define CBR_RG_TX_PA_EN_MSK 0x00000004
+#define CBR_RG_TX_PA_EN_I_MSK 0xfffffffb
+#define CBR_RG_TX_PA_EN_SFT 2
+#define CBR_RG_TX_PA_EN_HI 2
+#define CBR_RG_TX_PA_EN_SZ 1
+#define CBR_RG_TX_DAC_EN_MSK 0x00000008
+#define CBR_RG_TX_DAC_EN_I_MSK 0xfffffff7
+#define CBR_RG_TX_DAC_EN_SFT 3
+#define CBR_RG_TX_DAC_EN_HI 3
+#define CBR_RG_TX_DAC_EN_SZ 1
+#define CBR_RG_RX_AGC_MSK 0x00000010
+#define CBR_RG_RX_AGC_I_MSK 0xffffffef
+#define CBR_RG_RX_AGC_SFT 4
+#define CBR_RG_RX_AGC_HI 4
+#define CBR_RG_RX_AGC_SZ 1
+#define CBR_RG_RX_GAIN_MANUAL_MSK 0x00000020
+#define CBR_RG_RX_GAIN_MANUAL_I_MSK 0xffffffdf
+#define CBR_RG_RX_GAIN_MANUAL_SFT 5
+#define CBR_RG_RX_GAIN_MANUAL_HI 5
+#define CBR_RG_RX_GAIN_MANUAL_SZ 1
+#define CBR_RG_RFG_MSK 0x000000c0
+#define CBR_RG_RFG_I_MSK 0xffffff3f
+#define CBR_RG_RFG_SFT 6
+#define CBR_RG_RFG_HI 7
+#define CBR_RG_RFG_SZ 2
+#define CBR_RG_PGAG_MSK 0x00000f00
+#define CBR_RG_PGAG_I_MSK 0xfffff0ff
+#define CBR_RG_PGAG_SFT 8
+#define CBR_RG_PGAG_HI 11
+#define CBR_RG_PGAG_SZ 4
+#define CBR_RG_MODE_MSK 0x00003000
+#define CBR_RG_MODE_I_MSK 0xffffcfff
+#define CBR_RG_MODE_SFT 12
+#define CBR_RG_MODE_HI 13
+#define CBR_RG_MODE_SZ 2
+#define CBR_RG_EN_TX_TRSW_MSK 0x00004000
+#define CBR_RG_EN_TX_TRSW_I_MSK 0xffffbfff
+#define CBR_RG_EN_TX_TRSW_SFT 14
+#define CBR_RG_EN_TX_TRSW_HI 14
+#define CBR_RG_EN_TX_TRSW_SZ 1
+#define CBR_RG_EN_SX_MSK 0x00008000
+#define CBR_RG_EN_SX_I_MSK 0xffff7fff
+#define CBR_RG_EN_SX_SFT 15
+#define CBR_RG_EN_SX_HI 15
+#define CBR_RG_EN_SX_SZ 1
+#define CBR_RG_EN_RX_LNA_MSK 0x00010000
+#define CBR_RG_EN_RX_LNA_I_MSK 0xfffeffff
+#define CBR_RG_EN_RX_LNA_SFT 16
+#define CBR_RG_EN_RX_LNA_HI 16
+#define CBR_RG_EN_RX_LNA_SZ 1
+#define CBR_RG_EN_RX_MIXER_MSK 0x00020000
+#define CBR_RG_EN_RX_MIXER_I_MSK 0xfffdffff
+#define CBR_RG_EN_RX_MIXER_SFT 17
+#define CBR_RG_EN_RX_MIXER_HI 17
+#define CBR_RG_EN_RX_MIXER_SZ 1
+#define CBR_RG_EN_RX_DIV2_MSK 0x00040000
+#define CBR_RG_EN_RX_DIV2_I_MSK 0xfffbffff
+#define CBR_RG_EN_RX_DIV2_SFT 18
+#define CBR_RG_EN_RX_DIV2_HI 18
+#define CBR_RG_EN_RX_DIV2_SZ 1
+#define CBR_RG_EN_RX_LOBUF_MSK 0x00080000
+#define CBR_RG_EN_RX_LOBUF_I_MSK 0xfff7ffff
+#define CBR_RG_EN_RX_LOBUF_SFT 19
+#define CBR_RG_EN_RX_LOBUF_HI 19
+#define CBR_RG_EN_RX_LOBUF_SZ 1
+#define CBR_RG_EN_RX_TZ_MSK 0x00100000
+#define CBR_RG_EN_RX_TZ_I_MSK 0xffefffff
+#define CBR_RG_EN_RX_TZ_SFT 20
+#define CBR_RG_EN_RX_TZ_HI 20
+#define CBR_RG_EN_RX_TZ_SZ 1
+#define CBR_RG_EN_RX_FILTER_MSK 0x00200000
+#define CBR_RG_EN_RX_FILTER_I_MSK 0xffdfffff
+#define CBR_RG_EN_RX_FILTER_SFT 21
+#define CBR_RG_EN_RX_FILTER_HI 21
+#define CBR_RG_EN_RX_FILTER_SZ 1
+#define CBR_RG_EN_RX_HPF_MSK 0x00400000
+#define CBR_RG_EN_RX_HPF_I_MSK 0xffbfffff
+#define CBR_RG_EN_RX_HPF_SFT 22
+#define CBR_RG_EN_RX_HPF_HI 22
+#define CBR_RG_EN_RX_HPF_SZ 1
+#define CBR_RG_EN_RX_RSSI_MSK 0x00800000
+#define CBR_RG_EN_RX_RSSI_I_MSK 0xff7fffff
+#define CBR_RG_EN_RX_RSSI_SFT 23
+#define CBR_RG_EN_RX_RSSI_HI 23
+#define CBR_RG_EN_RX_RSSI_SZ 1
+#define CBR_RG_EN_ADC_MSK 0x01000000
+#define CBR_RG_EN_ADC_I_MSK 0xfeffffff
+#define CBR_RG_EN_ADC_SFT 24
+#define CBR_RG_EN_ADC_HI 24
+#define CBR_RG_EN_ADC_SZ 1
+#define CBR_RG_EN_TX_MOD_MSK 0x02000000
+#define CBR_RG_EN_TX_MOD_I_MSK 0xfdffffff
+#define CBR_RG_EN_TX_MOD_SFT 25
+#define CBR_RG_EN_TX_MOD_HI 25
+#define CBR_RG_EN_TX_MOD_SZ 1
+#define CBR_RG_EN_TX_DIV2_MSK 0x04000000
+#define CBR_RG_EN_TX_DIV2_I_MSK 0xfbffffff
+#define CBR_RG_EN_TX_DIV2_SFT 26
+#define CBR_RG_EN_TX_DIV2_HI 26
+#define CBR_RG_EN_TX_DIV2_SZ 1
+#define CBR_RG_EN_TX_DIV2_BUF_MSK 0x08000000
+#define CBR_RG_EN_TX_DIV2_BUF_I_MSK 0xf7ffffff
+#define CBR_RG_EN_TX_DIV2_BUF_SFT 27
+#define CBR_RG_EN_TX_DIV2_BUF_HI 27
+#define CBR_RG_EN_TX_DIV2_BUF_SZ 1
+#define CBR_RG_EN_TX_LOBF_MSK 0x10000000
+#define CBR_RG_EN_TX_LOBF_I_MSK 0xefffffff
+#define CBR_RG_EN_TX_LOBF_SFT 28
+#define CBR_RG_EN_TX_LOBF_HI 28
+#define CBR_RG_EN_TX_LOBF_SZ 1
+#define CBR_RG_EN_RX_LOBF_MSK 0x20000000
+#define CBR_RG_EN_RX_LOBF_I_MSK 0xdfffffff
+#define CBR_RG_EN_RX_LOBF_SFT 29
+#define CBR_RG_EN_RX_LOBF_HI 29
+#define CBR_RG_EN_RX_LOBF_SZ 1
+#define CBR_RG_SEL_DPLL_CLK_MSK 0x40000000
+#define CBR_RG_SEL_DPLL_CLK_I_MSK 0xbfffffff
+#define CBR_RG_SEL_DPLL_CLK_SFT 30
+#define CBR_RG_SEL_DPLL_CLK_HI 30
+#define CBR_RG_SEL_DPLL_CLK_SZ 1
+#define CBR_RG_EN_TX_DPD_MSK 0x00000001
+#define CBR_RG_EN_TX_DPD_I_MSK 0xfffffffe
+#define CBR_RG_EN_TX_DPD_SFT 0
+#define CBR_RG_EN_TX_DPD_HI 0
+#define CBR_RG_EN_TX_DPD_SZ 1
+#define CBR_RG_EN_TX_TSSI_MSK 0x00000002
+#define CBR_RG_EN_TX_TSSI_I_MSK 0xfffffffd
+#define CBR_RG_EN_TX_TSSI_SFT 1
+#define CBR_RG_EN_TX_TSSI_HI 1
+#define CBR_RG_EN_TX_TSSI_SZ 1
+#define CBR_RG_EN_RX_IQCAL_MSK 0x00000004
+#define CBR_RG_EN_RX_IQCAL_I_MSK 0xfffffffb
+#define CBR_RG_EN_RX_IQCAL_SFT 2
+#define CBR_RG_EN_RX_IQCAL_HI 2
+#define CBR_RG_EN_RX_IQCAL_SZ 1
+#define CBR_RG_EN_TX_DAC_CAL_MSK 0x00000008
+#define CBR_RG_EN_TX_DAC_CAL_I_MSK 0xfffffff7
+#define CBR_RG_EN_TX_DAC_CAL_SFT 3
+#define CBR_RG_EN_TX_DAC_CAL_HI 3
+#define CBR_RG_EN_TX_DAC_CAL_SZ 1
+#define CBR_RG_EN_TX_SELF_MIXER_MSK 0x00000010
+#define CBR_RG_EN_TX_SELF_MIXER_I_MSK 0xffffffef
+#define CBR_RG_EN_TX_SELF_MIXER_SFT 4
+#define CBR_RG_EN_TX_SELF_MIXER_HI 4
+#define CBR_RG_EN_TX_SELF_MIXER_SZ 1
+#define CBR_RG_EN_TX_DAC_OUT_MSK 0x00000020
+#define CBR_RG_EN_TX_DAC_OUT_I_MSK 0xffffffdf
+#define CBR_RG_EN_TX_DAC_OUT_SFT 5
+#define CBR_RG_EN_TX_DAC_OUT_HI 5
+#define CBR_RG_EN_TX_DAC_OUT_SZ 1
+#define CBR_RG_EN_LDO_RX_FE_MSK 0x00000040
+#define CBR_RG_EN_LDO_RX_FE_I_MSK 0xffffffbf
+#define CBR_RG_EN_LDO_RX_FE_SFT 6
+#define CBR_RG_EN_LDO_RX_FE_HI 6
+#define CBR_RG_EN_LDO_RX_FE_SZ 1
+#define CBR_RG_EN_LDO_ABB_MSK 0x00000080
+#define CBR_RG_EN_LDO_ABB_I_MSK 0xffffff7f
+#define CBR_RG_EN_LDO_ABB_SFT 7
+#define CBR_RG_EN_LDO_ABB_HI 7
+#define CBR_RG_EN_LDO_ABB_SZ 1
+#define CBR_RG_EN_LDO_AFE_MSK 0x00000100
+#define CBR_RG_EN_LDO_AFE_I_MSK 0xfffffeff
+#define CBR_RG_EN_LDO_AFE_SFT 8
+#define CBR_RG_EN_LDO_AFE_HI 8
+#define CBR_RG_EN_LDO_AFE_SZ 1
+#define CBR_RG_EN_SX_CHPLDO_MSK 0x00000200
+#define CBR_RG_EN_SX_CHPLDO_I_MSK 0xfffffdff
+#define CBR_RG_EN_SX_CHPLDO_SFT 9
+#define CBR_RG_EN_SX_CHPLDO_HI 9
+#define CBR_RG_EN_SX_CHPLDO_SZ 1
+#define CBR_RG_EN_SX_LOBFLDO_MSK 0x00000400
+#define CBR_RG_EN_SX_LOBFLDO_I_MSK 0xfffffbff
+#define CBR_RG_EN_SX_LOBFLDO_SFT 10
+#define CBR_RG_EN_SX_LOBFLDO_HI 10
+#define CBR_RG_EN_SX_LOBFLDO_SZ 1
+#define CBR_RG_EN_IREF_RX_MSK 0x00000800
+#define CBR_RG_EN_IREF_RX_I_MSK 0xfffff7ff
+#define CBR_RG_EN_IREF_RX_SFT 11
+#define CBR_RG_EN_IREF_RX_HI 11
+#define CBR_RG_EN_IREF_RX_SZ 1
+#define CBR_RG_DCDC_MODE_MSK 0x00001000
+#define CBR_RG_DCDC_MODE_I_MSK 0xffffefff
+#define CBR_RG_DCDC_MODE_SFT 12
+#define CBR_RG_DCDC_MODE_HI 12
+#define CBR_RG_DCDC_MODE_SZ 1
+#define CBR_RG_LDO_LEVEL_RX_FE_MSK 0x00000007
+#define CBR_RG_LDO_LEVEL_RX_FE_I_MSK 0xfffffff8
+#define CBR_RG_LDO_LEVEL_RX_FE_SFT 0
+#define CBR_RG_LDO_LEVEL_RX_FE_HI 2
+#define CBR_RG_LDO_LEVEL_RX_FE_SZ 3
+#define CBR_RG_LDO_LEVEL_ABB_MSK 0x00000038
+#define CBR_RG_LDO_LEVEL_ABB_I_MSK 0xffffffc7
+#define CBR_RG_LDO_LEVEL_ABB_SFT 3
+#define CBR_RG_LDO_LEVEL_ABB_HI 5
+#define CBR_RG_LDO_LEVEL_ABB_SZ 3
+#define CBR_RG_LDO_LEVEL_AFE_MSK 0x000001c0
+#define CBR_RG_LDO_LEVEL_AFE_I_MSK 0xfffffe3f
+#define CBR_RG_LDO_LEVEL_AFE_SFT 6
+#define CBR_RG_LDO_LEVEL_AFE_HI 8
+#define CBR_RG_LDO_LEVEL_AFE_SZ 3
+#define CBR_RG_SX_LDO_CHP_LEVEL_MSK 0x00000e00
+#define CBR_RG_SX_LDO_CHP_LEVEL_I_MSK 0xfffff1ff
+#define CBR_RG_SX_LDO_CHP_LEVEL_SFT 9
+#define CBR_RG_SX_LDO_CHP_LEVEL_HI 11
+#define CBR_RG_SX_LDO_CHP_LEVEL_SZ 3
+#define CBR_RG_SX_LDO_LOBF_LEVEL_MSK 0x00007000
+#define CBR_RG_SX_LDO_LOBF_LEVEL_I_MSK 0xffff8fff
+#define CBR_RG_SX_LDO_LOBF_LEVEL_SFT 12
+#define CBR_RG_SX_LDO_LOBF_LEVEL_HI 14
+#define CBR_RG_SX_LDO_LOBF_LEVEL_SZ 3
+#define CBR_RG_SX_LDO_XOSC_LEVEL_MSK 0x00038000
+#define CBR_RG_SX_LDO_XOSC_LEVEL_I_MSK 0xfffc7fff
+#define CBR_RG_SX_LDO_XOSC_LEVEL_SFT 15
+#define CBR_RG_SX_LDO_XOSC_LEVEL_HI 17
+#define CBR_RG_SX_LDO_XOSC_LEVEL_SZ 3
+#define CBR_RG_DP_LDO_LEVEL_MSK 0x001c0000
+#define CBR_RG_DP_LDO_LEVEL_I_MSK 0xffe3ffff
+#define CBR_RG_DP_LDO_LEVEL_SFT 18
+#define CBR_RG_DP_LDO_LEVEL_HI 20
+#define CBR_RG_DP_LDO_LEVEL_SZ 3
+#define CBR_RG_SX_LDO_VCO_LEVEL_MSK 0x00e00000
+#define CBR_RG_SX_LDO_VCO_LEVEL_I_MSK 0xff1fffff
+#define CBR_RG_SX_LDO_VCO_LEVEL_SFT 21
+#define CBR_RG_SX_LDO_VCO_LEVEL_HI 23
+#define CBR_RG_SX_LDO_VCO_LEVEL_SZ 3
+#define CBR_RG_TX_LDO_TX_LEVEL_MSK 0x07000000
+#define CBR_RG_TX_LDO_TX_LEVEL_I_MSK 0xf8ffffff
+#define CBR_RG_TX_LDO_TX_LEVEL_SFT 24
+#define CBR_RG_TX_LDO_TX_LEVEL_HI 26
+#define CBR_RG_TX_LDO_TX_LEVEL_SZ 3
+#define CBR_RG_BUCK_LEVEL_MSK 0x38000000
+#define CBR_RG_BUCK_LEVEL_I_MSK 0xc7ffffff
+#define CBR_RG_BUCK_LEVEL_SFT 27
+#define CBR_RG_BUCK_LEVEL_HI 29
+#define CBR_RG_BUCK_LEVEL_SZ 3
+#define CBR_RG_EN_RX_PADSW_MSK 0x00000001
+#define CBR_RG_EN_RX_PADSW_I_MSK 0xfffffffe
+#define CBR_RG_EN_RX_PADSW_SFT 0
+#define CBR_RG_EN_RX_PADSW_HI 0
+#define CBR_RG_EN_RX_PADSW_SZ 1
+#define CBR_RG_EN_RX_TESTNODE_MSK 0x00000002
+#define CBR_RG_EN_RX_TESTNODE_I_MSK 0xfffffffd
+#define CBR_RG_EN_RX_TESTNODE_SFT 1
+#define CBR_RG_EN_RX_TESTNODE_HI 1
+#define CBR_RG_EN_RX_TESTNODE_SZ 1
+#define CBR_RG_RX_ABBCFIX_MSK 0x00000004
+#define CBR_RG_RX_ABBCFIX_I_MSK 0xfffffffb
+#define CBR_RG_RX_ABBCFIX_SFT 2
+#define CBR_RG_RX_ABBCFIX_HI 2
+#define CBR_RG_RX_ABBCFIX_SZ 1
+#define CBR_RG_RX_ABBCTUNE_MSK 0x000001f8
+#define CBR_RG_RX_ABBCTUNE_I_MSK 0xfffffe07
+#define CBR_RG_RX_ABBCTUNE_SFT 3
+#define CBR_RG_RX_ABBCTUNE_HI 8
+#define CBR_RG_RX_ABBCTUNE_SZ 6
+#define CBR_RG_RX_ABBOUT_TRI_STATE_MSK 0x00000200
+#define CBR_RG_RX_ABBOUT_TRI_STATE_I_MSK 0xfffffdff
+#define CBR_RG_RX_ABBOUT_TRI_STATE_SFT 9
+#define CBR_RG_RX_ABBOUT_TRI_STATE_HI 9
+#define CBR_RG_RX_ABBOUT_TRI_STATE_SZ 1
+#define CBR_RG_RX_ABB_N_MODE_MSK 0x00000400
+#define CBR_RG_RX_ABB_N_MODE_I_MSK 0xfffffbff
+#define CBR_RG_RX_ABB_N_MODE_SFT 10
+#define CBR_RG_RX_ABB_N_MODE_HI 10
+#define CBR_RG_RX_ABB_N_MODE_SZ 1
+#define CBR_RG_RX_EN_LOOPA_MSK 0x00000800
+#define CBR_RG_RX_EN_LOOPA_I_MSK 0xfffff7ff
+#define CBR_RG_RX_EN_LOOPA_SFT 11
+#define CBR_RG_RX_EN_LOOPA_HI 11
+#define CBR_RG_RX_EN_LOOPA_SZ 1
+#define CBR_RG_RX_FILTERI1ST_MSK 0x00003000
+#define CBR_RG_RX_FILTERI1ST_I_MSK 0xffffcfff
+#define CBR_RG_RX_FILTERI1ST_SFT 12
+#define CBR_RG_RX_FILTERI1ST_HI 13
+#define CBR_RG_RX_FILTERI1ST_SZ 2
+#define CBR_RG_RX_FILTERI2ND_MSK 0x0000c000
+#define CBR_RG_RX_FILTERI2ND_I_MSK 0xffff3fff
+#define CBR_RG_RX_FILTERI2ND_SFT 14
+#define CBR_RG_RX_FILTERI2ND_HI 15
+#define CBR_RG_RX_FILTERI2ND_SZ 2
+#define CBR_RG_RX_FILTERI3RD_MSK 0x00030000
+#define CBR_RG_RX_FILTERI3RD_I_MSK 0xfffcffff
+#define CBR_RG_RX_FILTERI3RD_SFT 16
+#define CBR_RG_RX_FILTERI3RD_HI 17
+#define CBR_RG_RX_FILTERI3RD_SZ 2
+#define CBR_RG_RX_FILTERI_COURSE_MSK 0x000c0000
+#define CBR_RG_RX_FILTERI_COURSE_I_MSK 0xfff3ffff
+#define CBR_RG_RX_FILTERI_COURSE_SFT 18
+#define CBR_RG_RX_FILTERI_COURSE_HI 19
+#define CBR_RG_RX_FILTERI_COURSE_SZ 2
+#define CBR_RG_RX_FILTERVCM_MSK 0x00300000
+#define CBR_RG_RX_FILTERVCM_I_MSK 0xffcfffff
+#define CBR_RG_RX_FILTERVCM_SFT 20
+#define CBR_RG_RX_FILTERVCM_HI 21
+#define CBR_RG_RX_FILTERVCM_SZ 2
+#define CBR_RG_RX_HPF3M_MSK 0x00400000
+#define CBR_RG_RX_HPF3M_I_MSK 0xffbfffff
+#define CBR_RG_RX_HPF3M_SFT 22
+#define CBR_RG_RX_HPF3M_HI 22
+#define CBR_RG_RX_HPF3M_SZ 1
+#define CBR_RG_RX_HPF300K_MSK 0x00800000
+#define CBR_RG_RX_HPF300K_I_MSK 0xff7fffff
+#define CBR_RG_RX_HPF300K_SFT 23
+#define CBR_RG_RX_HPF300K_HI 23
+#define CBR_RG_RX_HPF300K_SZ 1
+#define CBR_RG_RX_HPFI_MSK 0x03000000
+#define CBR_RG_RX_HPFI_I_MSK 0xfcffffff
+#define CBR_RG_RX_HPFI_SFT 24
+#define CBR_RG_RX_HPFI_HI 25
+#define CBR_RG_RX_HPFI_SZ 2
+#define CBR_RG_RX_HPF_FINALCORNER_MSK 0x0c000000
+#define CBR_RG_RX_HPF_FINALCORNER_I_MSK 0xf3ffffff
+#define CBR_RG_RX_HPF_FINALCORNER_SFT 26
+#define CBR_RG_RX_HPF_FINALCORNER_HI 27
+#define CBR_RG_RX_HPF_FINALCORNER_SZ 2
+#define CBR_RG_RX_HPF_SETTLE1_C_MSK 0x30000000
+#define CBR_RG_RX_HPF_SETTLE1_C_I_MSK 0xcfffffff
+#define CBR_RG_RX_HPF_SETTLE1_C_SFT 28
+#define CBR_RG_RX_HPF_SETTLE1_C_HI 29
+#define CBR_RG_RX_HPF_SETTLE1_C_SZ 2
+#define CBR_RG_RX_HPF_SETTLE1_R_MSK 0x00000003
+#define CBR_RG_RX_HPF_SETTLE1_R_I_MSK 0xfffffffc
+#define CBR_RG_RX_HPF_SETTLE1_R_SFT 0
+#define CBR_RG_RX_HPF_SETTLE1_R_HI 1
+#define CBR_RG_RX_HPF_SETTLE1_R_SZ 2
+#define CBR_RG_RX_HPF_SETTLE2_C_MSK 0x0000000c
+#define CBR_RG_RX_HPF_SETTLE2_C_I_MSK 0xfffffff3
+#define CBR_RG_RX_HPF_SETTLE2_C_SFT 2
+#define CBR_RG_RX_HPF_SETTLE2_C_HI 3
+#define CBR_RG_RX_HPF_SETTLE2_C_SZ 2
+#define CBR_RG_RX_HPF_SETTLE2_R_MSK 0x00000030
+#define CBR_RG_RX_HPF_SETTLE2_R_I_MSK 0xffffffcf
+#define CBR_RG_RX_HPF_SETTLE2_R_SFT 4
+#define CBR_RG_RX_HPF_SETTLE2_R_HI 5
+#define CBR_RG_RX_HPF_SETTLE2_R_SZ 2
+#define CBR_RG_RX_HPF_VCMCON2_MSK 0x000000c0
+#define CBR_RG_RX_HPF_VCMCON2_I_MSK 0xffffff3f
+#define CBR_RG_RX_HPF_VCMCON2_SFT 6
+#define CBR_RG_RX_HPF_VCMCON2_HI 7
+#define CBR_RG_RX_HPF_VCMCON2_SZ 2
+#define CBR_RG_RX_HPF_VCMCON_MSK 0x00000300
+#define CBR_RG_RX_HPF_VCMCON_I_MSK 0xfffffcff
+#define CBR_RG_RX_HPF_VCMCON_SFT 8
+#define CBR_RG_RX_HPF_VCMCON_HI 9
+#define CBR_RG_RX_HPF_VCMCON_SZ 2
+#define CBR_RG_RX_OUTVCM_MSK 0x00000c00
+#define CBR_RG_RX_OUTVCM_I_MSK 0xfffff3ff
+#define CBR_RG_RX_OUTVCM_SFT 10
+#define CBR_RG_RX_OUTVCM_HI 11
+#define CBR_RG_RX_OUTVCM_SZ 2
+#define CBR_RG_RX_TZI_MSK 0x00003000
+#define CBR_RG_RX_TZI_I_MSK 0xffffcfff
+#define CBR_RG_RX_TZI_SFT 12
+#define CBR_RG_RX_TZI_HI 13
+#define CBR_RG_RX_TZI_SZ 2
+#define CBR_RG_RX_TZ_OUT_TRISTATE_MSK 0x00004000
+#define CBR_RG_RX_TZ_OUT_TRISTATE_I_MSK 0xffffbfff
+#define CBR_RG_RX_TZ_OUT_TRISTATE_SFT 14
+#define CBR_RG_RX_TZ_OUT_TRISTATE_HI 14
+#define CBR_RG_RX_TZ_OUT_TRISTATE_SZ 1
+#define CBR_RG_RX_TZ_VCM_MSK 0x00018000
+#define CBR_RG_RX_TZ_VCM_I_MSK 0xfffe7fff
+#define CBR_RG_RX_TZ_VCM_SFT 15
+#define CBR_RG_RX_TZ_VCM_HI 16
+#define CBR_RG_RX_TZ_VCM_SZ 2
+#define CBR_RG_EN_RX_RSSI_TESTNODE_MSK 0x000e0000
+#define CBR_RG_EN_RX_RSSI_TESTNODE_I_MSK 0xfff1ffff
+#define CBR_RG_EN_RX_RSSI_TESTNODE_SFT 17
+#define CBR_RG_EN_RX_RSSI_TESTNODE_HI 19
+#define CBR_RG_EN_RX_RSSI_TESTNODE_SZ 3
+#define CBR_RG_RX_ADCRSSI_CLKSEL_MSK 0x00100000
+#define CBR_RG_RX_ADCRSSI_CLKSEL_I_MSK 0xffefffff
+#define CBR_RG_RX_ADCRSSI_CLKSEL_SFT 20
+#define CBR_RG_RX_ADCRSSI_CLKSEL_HI 20
+#define CBR_RG_RX_ADCRSSI_CLKSEL_SZ 1
+#define CBR_RG_RX_ADCRSSI_VCM_MSK 0x00600000
+#define CBR_RG_RX_ADCRSSI_VCM_I_MSK 0xff9fffff
+#define CBR_RG_RX_ADCRSSI_VCM_SFT 21
+#define CBR_RG_RX_ADCRSSI_VCM_HI 22
+#define CBR_RG_RX_ADCRSSI_VCM_SZ 2
+#define CBR_RG_RX_REC_LPFCORNER_MSK 0x01800000
+#define CBR_RG_RX_REC_LPFCORNER_I_MSK 0xfe7fffff
+#define CBR_RG_RX_REC_LPFCORNER_SFT 23
+#define CBR_RG_RX_REC_LPFCORNER_HI 24
+#define CBR_RG_RX_REC_LPFCORNER_SZ 2
+#define CBR_RG_RSSI_CLOCK_GATING_MSK 0x02000000
+#define CBR_RG_RSSI_CLOCK_GATING_I_MSK 0xfdffffff
+#define CBR_RG_RSSI_CLOCK_GATING_SFT 25
+#define CBR_RG_RSSI_CLOCK_GATING_HI 25
+#define CBR_RG_RSSI_CLOCK_GATING_SZ 1
+#define CBR_RG_TXPGA_CAPSW_MSK 0x00000003
+#define CBR_RG_TXPGA_CAPSW_I_MSK 0xfffffffc
+#define CBR_RG_TXPGA_CAPSW_SFT 0
+#define CBR_RG_TXPGA_CAPSW_HI 1
+#define CBR_RG_TXPGA_CAPSW_SZ 2
+#define CBR_RG_TXPGA_MAIN_MSK 0x000000fc
+#define CBR_RG_TXPGA_MAIN_I_MSK 0xffffff03
+#define CBR_RG_TXPGA_MAIN_SFT 2
+#define CBR_RG_TXPGA_MAIN_HI 7
+#define CBR_RG_TXPGA_MAIN_SZ 6
+#define CBR_RG_TXPGA_STEER_MSK 0x00003f00
+#define CBR_RG_TXPGA_STEER_I_MSK 0xffffc0ff
+#define CBR_RG_TXPGA_STEER_SFT 8
+#define CBR_RG_TXPGA_STEER_HI 13
+#define CBR_RG_TXPGA_STEER_SZ 6
+#define CBR_RG_TXMOD_GMCELL_MSK 0x0000c000
+#define CBR_RG_TXMOD_GMCELL_I_MSK 0xffff3fff
+#define CBR_RG_TXMOD_GMCELL_SFT 14
+#define CBR_RG_TXMOD_GMCELL_HI 15
+#define CBR_RG_TXMOD_GMCELL_SZ 2
+#define CBR_RG_TXLPF_GMCELL_MSK 0x00030000
+#define CBR_RG_TXLPF_GMCELL_I_MSK 0xfffcffff
+#define CBR_RG_TXLPF_GMCELL_SFT 16
+#define CBR_RG_TXLPF_GMCELL_HI 17
+#define CBR_RG_TXLPF_GMCELL_SZ 2
+#define CBR_RG_PACELL_EN_MSK 0x001c0000
+#define CBR_RG_PACELL_EN_I_MSK 0xffe3ffff
+#define CBR_RG_PACELL_EN_SFT 18
+#define CBR_RG_PACELL_EN_HI 20
+#define CBR_RG_PACELL_EN_SZ 3
+#define CBR_RG_PABIAS_CTRL_MSK 0x01e00000
+#define CBR_RG_PABIAS_CTRL_I_MSK 0xfe1fffff
+#define CBR_RG_PABIAS_CTRL_SFT 21
+#define CBR_RG_PABIAS_CTRL_HI 24
+#define CBR_RG_PABIAS_CTRL_SZ 4
+#define CBR_RG_PABIAS_AB_MSK 0x02000000
+#define CBR_RG_PABIAS_AB_I_MSK 0xfdffffff
+#define CBR_RG_PABIAS_AB_SFT 25
+#define CBR_RG_PABIAS_AB_HI 25
+#define CBR_RG_PABIAS_AB_SZ 1
+#define CBR_RG_TX_DIV_VSET_MSK 0x0c000000
+#define CBR_RG_TX_DIV_VSET_I_MSK 0xf3ffffff
+#define CBR_RG_TX_DIV_VSET_SFT 26
+#define CBR_RG_TX_DIV_VSET_HI 27
+#define CBR_RG_TX_DIV_VSET_SZ 2
+#define CBR_RG_TX_LOBUF_VSET_MSK 0x30000000
+#define CBR_RG_TX_LOBUF_VSET_I_MSK 0xcfffffff
+#define CBR_RG_TX_LOBUF_VSET_SFT 28
+#define CBR_RG_TX_LOBUF_VSET_HI 29
+#define CBR_RG_TX_LOBUF_VSET_SZ 2
+#define CBR_RG_RX_SQDC_MSK 0x00000007
+#define CBR_RG_RX_SQDC_I_MSK 0xfffffff8
+#define CBR_RG_RX_SQDC_SFT 0
+#define CBR_RG_RX_SQDC_HI 2
+#define CBR_RG_RX_SQDC_SZ 3
+#define CBR_RG_RX_DIV2_CORE_MSK 0x00000018
+#define CBR_RG_RX_DIV2_CORE_I_MSK 0xffffffe7
+#define CBR_RG_RX_DIV2_CORE_SFT 3
+#define CBR_RG_RX_DIV2_CORE_HI 4
+#define CBR_RG_RX_DIV2_CORE_SZ 2
+#define CBR_RG_RX_LOBUF_MSK 0x00000060
+#define CBR_RG_RX_LOBUF_I_MSK 0xffffff9f
+#define CBR_RG_RX_LOBUF_SFT 5
+#define CBR_RG_RX_LOBUF_HI 6
+#define CBR_RG_RX_LOBUF_SZ 2
+#define CBR_RG_TX_DPDGM_BIAS_MSK 0x00000780
+#define CBR_RG_TX_DPDGM_BIAS_I_MSK 0xfffff87f
+#define CBR_RG_TX_DPDGM_BIAS_SFT 7
+#define CBR_RG_TX_DPDGM_BIAS_HI 10
+#define CBR_RG_TX_DPDGM_BIAS_SZ 4
+#define CBR_RG_TX_DPD_DIV_MSK 0x00007800
+#define CBR_RG_TX_DPD_DIV_I_MSK 0xffff87ff
+#define CBR_RG_TX_DPD_DIV_SFT 11
+#define CBR_RG_TX_DPD_DIV_HI 14
+#define CBR_RG_TX_DPD_DIV_SZ 4
+#define CBR_RG_TX_TSSI_BIAS_MSK 0x00038000
+#define CBR_RG_TX_TSSI_BIAS_I_MSK 0xfffc7fff
+#define CBR_RG_TX_TSSI_BIAS_SFT 15
+#define CBR_RG_TX_TSSI_BIAS_HI 17
+#define CBR_RG_TX_TSSI_BIAS_SZ 3
+#define CBR_RG_TX_TSSI_DIV_MSK 0x001c0000
+#define CBR_RG_TX_TSSI_DIV_I_MSK 0xffe3ffff
+#define CBR_RG_TX_TSSI_DIV_SFT 18
+#define CBR_RG_TX_TSSI_DIV_HI 20
+#define CBR_RG_TX_TSSI_DIV_SZ 3
+#define CBR_RG_TX_TSSI_TESTMODE_MSK 0x00200000
+#define CBR_RG_TX_TSSI_TESTMODE_I_MSK 0xffdfffff
+#define CBR_RG_TX_TSSI_TESTMODE_SFT 21
+#define CBR_RG_TX_TSSI_TESTMODE_HI 21
+#define CBR_RG_TX_TSSI_TESTMODE_SZ 1
+#define CBR_RG_TX_TSSI_TEST_MSK 0x00c00000
+#define CBR_RG_TX_TSSI_TEST_I_MSK 0xff3fffff
+#define CBR_RG_TX_TSSI_TEST_SFT 22
+#define CBR_RG_TX_TSSI_TEST_HI 23
+#define CBR_RG_TX_TSSI_TEST_SZ 2
+#define CBR_RG_RX_HG_LNA_GC_MSK 0x00000003
+#define CBR_RG_RX_HG_LNA_GC_I_MSK 0xfffffffc
+#define CBR_RG_RX_HG_LNA_GC_SFT 0
+#define CBR_RG_RX_HG_LNA_GC_HI 1
+#define CBR_RG_RX_HG_LNA_GC_SZ 2
+#define CBR_RG_RX_HG_LNAHGN_BIAS_MSK 0x0000003c
+#define CBR_RG_RX_HG_LNAHGN_BIAS_I_MSK 0xffffffc3
+#define CBR_RG_RX_HG_LNAHGN_BIAS_SFT 2
+#define CBR_RG_RX_HG_LNAHGN_BIAS_HI 5
+#define CBR_RG_RX_HG_LNAHGN_BIAS_SZ 4
+#define CBR_RG_RX_HG_LNAHGP_BIAS_MSK 0x000003c0
+#define CBR_RG_RX_HG_LNAHGP_BIAS_I_MSK 0xfffffc3f
+#define CBR_RG_RX_HG_LNAHGP_BIAS_SFT 6
+#define CBR_RG_RX_HG_LNAHGP_BIAS_HI 9
+#define CBR_RG_RX_HG_LNAHGP_BIAS_SZ 4
+#define CBR_RG_RX_HG_LNALG_BIAS_MSK 0x00003c00
+#define CBR_RG_RX_HG_LNALG_BIAS_I_MSK 0xffffc3ff
+#define CBR_RG_RX_HG_LNALG_BIAS_SFT 10
+#define CBR_RG_RX_HG_LNALG_BIAS_HI 13
+#define CBR_RG_RX_HG_LNALG_BIAS_SZ 4
+#define CBR_RG_RX_HG_TZ_GC_MSK 0x0000c000
+#define CBR_RG_RX_HG_TZ_GC_I_MSK 0xffff3fff
+#define CBR_RG_RX_HG_TZ_GC_SFT 14
+#define CBR_RG_RX_HG_TZ_GC_HI 15
+#define CBR_RG_RX_HG_TZ_GC_SZ 2
+#define CBR_RG_RX_HG_TZ_CAP_MSK 0x00070000
+#define CBR_RG_RX_HG_TZ_CAP_I_MSK 0xfff8ffff
+#define CBR_RG_RX_HG_TZ_CAP_SFT 16
+#define CBR_RG_RX_HG_TZ_CAP_HI 18
+#define CBR_RG_RX_HG_TZ_CAP_SZ 3
+#define CBR_RG_RX_MG_LNA_GC_MSK 0x00000003
+#define CBR_RG_RX_MG_LNA_GC_I_MSK 0xfffffffc
+#define CBR_RG_RX_MG_LNA_GC_SFT 0
+#define CBR_RG_RX_MG_LNA_GC_HI 1
+#define CBR_RG_RX_MG_LNA_GC_SZ 2
+#define CBR_RG_RX_MG_LNAHGN_BIAS_MSK 0x0000003c
+#define CBR_RG_RX_MG_LNAHGN_BIAS_I_MSK 0xffffffc3
+#define CBR_RG_RX_MG_LNAHGN_BIAS_SFT 2
+#define CBR_RG_RX_MG_LNAHGN_BIAS_HI 5
+#define CBR_RG_RX_MG_LNAHGN_BIAS_SZ 4
+#define CBR_RG_RX_MG_LNAHGP_BIAS_MSK 0x000003c0
+#define CBR_RG_RX_MG_LNAHGP_BIAS_I_MSK 0xfffffc3f
+#define CBR_RG_RX_MG_LNAHGP_BIAS_SFT 6
+#define CBR_RG_RX_MG_LNAHGP_BIAS_HI 9
+#define CBR_RG_RX_MG_LNAHGP_BIAS_SZ 4
+#define CBR_RG_RX_MG_LNALG_BIAS_MSK 0x00003c00
+#define CBR_RG_RX_MG_LNALG_BIAS_I_MSK 0xffffc3ff
+#define CBR_RG_RX_MG_LNALG_BIAS_SFT 10
+#define CBR_RG_RX_MG_LNALG_BIAS_HI 13
+#define CBR_RG_RX_MG_LNALG_BIAS_SZ 4
+#define CBR_RG_RX_MG_TZ_GC_MSK 0x0000c000
+#define CBR_RG_RX_MG_TZ_GC_I_MSK 0xffff3fff
+#define CBR_RG_RX_MG_TZ_GC_SFT 14
+#define CBR_RG_RX_MG_TZ_GC_HI 15
+#define CBR_RG_RX_MG_TZ_GC_SZ 2
+#define CBR_RG_RX_MG_TZ_CAP_MSK 0x00070000
+#define CBR_RG_RX_MG_TZ_CAP_I_MSK 0xfff8ffff
+#define CBR_RG_RX_MG_TZ_CAP_SFT 16
+#define CBR_RG_RX_MG_TZ_CAP_HI 18
+#define CBR_RG_RX_MG_TZ_CAP_SZ 3
+#define CBR_RG_RX_LG_LNA_GC_MSK 0x00000003
+#define CBR_RG_RX_LG_LNA_GC_I_MSK 0xfffffffc
+#define CBR_RG_RX_LG_LNA_GC_SFT 0
+#define CBR_RG_RX_LG_LNA_GC_HI 1
+#define CBR_RG_RX_LG_LNA_GC_SZ 2
+#define CBR_RG_RX_LG_LNAHGN_BIAS_MSK 0x0000003c
+#define CBR_RG_RX_LG_LNAHGN_BIAS_I_MSK 0xffffffc3
+#define CBR_RG_RX_LG_LNAHGN_BIAS_SFT 2
+#define CBR_RG_RX_LG_LNAHGN_BIAS_HI 5
+#define CBR_RG_RX_LG_LNAHGN_BIAS_SZ 4
+#define CBR_RG_RX_LG_LNAHGP_BIAS_MSK 0x000003c0
+#define CBR_RG_RX_LG_LNAHGP_BIAS_I_MSK 0xfffffc3f
+#define CBR_RG_RX_LG_LNAHGP_BIAS_SFT 6
+#define CBR_RG_RX_LG_LNAHGP_BIAS_HI 9
+#define CBR_RG_RX_LG_LNAHGP_BIAS_SZ 4
+#define CBR_RG_RX_LG_LNALG_BIAS_MSK 0x00003c00
+#define CBR_RG_RX_LG_LNALG_BIAS_I_MSK 0xffffc3ff
+#define CBR_RG_RX_LG_LNALG_BIAS_SFT 10
+#define CBR_RG_RX_LG_LNALG_BIAS_HI 13
+#define CBR_RG_RX_LG_LNALG_BIAS_SZ 4
+#define CBR_RG_RX_LG_TZ_GC_MSK 0x0000c000
+#define CBR_RG_RX_LG_TZ_GC_I_MSK 0xffff3fff
+#define CBR_RG_RX_LG_TZ_GC_SFT 14
+#define CBR_RG_RX_LG_TZ_GC_HI 15
+#define CBR_RG_RX_LG_TZ_GC_SZ 2
+#define CBR_RG_RX_LG_TZ_CAP_MSK 0x00070000
+#define CBR_RG_RX_LG_TZ_CAP_I_MSK 0xfff8ffff
+#define CBR_RG_RX_LG_TZ_CAP_SFT 16
+#define CBR_RG_RX_LG_TZ_CAP_HI 18
+#define CBR_RG_RX_LG_TZ_CAP_SZ 3
+#define CBR_RG_RX_ULG_LNA_GC_MSK 0x00000003
+#define CBR_RG_RX_ULG_LNA_GC_I_MSK 0xfffffffc
+#define CBR_RG_RX_ULG_LNA_GC_SFT 0
+#define CBR_RG_RX_ULG_LNA_GC_HI 1
+#define CBR_RG_RX_ULG_LNA_GC_SZ 2
+#define CBR_RG_RX_ULG_LNAHGN_BIAS_MSK 0x0000003c
+#define CBR_RG_RX_ULG_LNAHGN_BIAS_I_MSK 0xffffffc3
+#define CBR_RG_RX_ULG_LNAHGN_BIAS_SFT 2
+#define CBR_RG_RX_ULG_LNAHGN_BIAS_HI 5
+#define CBR_RG_RX_ULG_LNAHGN_BIAS_SZ 4
+#define CBR_RG_RX_ULG_LNAHGP_BIAS_MSK 0x000003c0
+#define CBR_RG_RX_ULG_LNAHGP_BIAS_I_MSK 0xfffffc3f
+#define CBR_RG_RX_ULG_LNAHGP_BIAS_SFT 6
+#define CBR_RG_RX_ULG_LNAHGP_BIAS_HI 9
+#define CBR_RG_RX_ULG_LNAHGP_BIAS_SZ 4
+#define CBR_RG_RX_ULG_LNALG_BIAS_MSK 0x00003c00
+#define CBR_RG_RX_ULG_LNALG_BIAS_I_MSK 0xffffc3ff
+#define CBR_RG_RX_ULG_LNALG_BIAS_SFT 10
+#define CBR_RG_RX_ULG_LNALG_BIAS_HI 13
+#define CBR_RG_RX_ULG_LNALG_BIAS_SZ 4
+#define CBR_RG_RX_ULG_TZ_GC_MSK 0x0000c000
+#define CBR_RG_RX_ULG_TZ_GC_I_MSK 0xffff3fff
+#define CBR_RG_RX_ULG_TZ_GC_SFT 14
+#define CBR_RG_RX_ULG_TZ_GC_HI 15
+#define CBR_RG_RX_ULG_TZ_GC_SZ 2
+#define CBR_RG_RX_ULG_TZ_CAP_MSK 0x00070000
+#define CBR_RG_RX_ULG_TZ_CAP_I_MSK 0xfff8ffff
+#define CBR_RG_RX_ULG_TZ_CAP_SFT 16
+#define CBR_RG_RX_ULG_TZ_CAP_HI 18
+#define CBR_RG_RX_ULG_TZ_CAP_SZ 3
+#define CBR_RG_HPF1_FAST_SET_X_MSK 0x00000001
+#define CBR_RG_HPF1_FAST_SET_X_I_MSK 0xfffffffe
+#define CBR_RG_HPF1_FAST_SET_X_SFT 0
+#define CBR_RG_HPF1_FAST_SET_X_HI 0
+#define CBR_RG_HPF1_FAST_SET_X_SZ 1
+#define CBR_RG_HPF1_FAST_SET_Y_MSK 0x00000002
+#define CBR_RG_HPF1_FAST_SET_Y_I_MSK 0xfffffffd
+#define CBR_RG_HPF1_FAST_SET_Y_SFT 1
+#define CBR_RG_HPF1_FAST_SET_Y_HI 1
+#define CBR_RG_HPF1_FAST_SET_Y_SZ 1
+#define CBR_RG_HPF1_FAST_SET_Z_MSK 0x00000004
+#define CBR_RG_HPF1_FAST_SET_Z_I_MSK 0xfffffffb
+#define CBR_RG_HPF1_FAST_SET_Z_SFT 2
+#define CBR_RG_HPF1_FAST_SET_Z_HI 2
+#define CBR_RG_HPF1_FAST_SET_Z_SZ 1
+#define CBR_RG_HPF_T1A_MSK 0x00000018
+#define CBR_RG_HPF_T1A_I_MSK 0xffffffe7
+#define CBR_RG_HPF_T1A_SFT 3
+#define CBR_RG_HPF_T1A_HI 4
+#define CBR_RG_HPF_T1A_SZ 2
+#define CBR_RG_HPF_T1B_MSK 0x00000060
+#define CBR_RG_HPF_T1B_I_MSK 0xffffff9f
+#define CBR_RG_HPF_T1B_SFT 5
+#define CBR_RG_HPF_T1B_HI 6
+#define CBR_RG_HPF_T1B_SZ 2
+#define CBR_RG_HPF_T1C_MSK 0x00000180
+#define CBR_RG_HPF_T1C_I_MSK 0xfffffe7f
+#define CBR_RG_HPF_T1C_SFT 7
+#define CBR_RG_HPF_T1C_HI 8
+#define CBR_RG_HPF_T1C_SZ 2
+#define CBR_RG_RX_LNA_TRI_SEL_MSK 0x00000600
+#define CBR_RG_RX_LNA_TRI_SEL_I_MSK 0xfffff9ff
+#define CBR_RG_RX_LNA_TRI_SEL_SFT 9
+#define CBR_RG_RX_LNA_TRI_SEL_HI 10
+#define CBR_RG_RX_LNA_TRI_SEL_SZ 2
+#define CBR_RG_RX_LNA_SETTLE_MSK 0x00001800
+#define CBR_RG_RX_LNA_SETTLE_I_MSK 0xffffe7ff
+#define CBR_RG_RX_LNA_SETTLE_SFT 11
+#define CBR_RG_RX_LNA_SETTLE_HI 12
+#define CBR_RG_RX_LNA_SETTLE_SZ 2
+#define CBR_RG_ADC_CLKSEL_MSK 0x00000001
+#define CBR_RG_ADC_CLKSEL_I_MSK 0xfffffffe
+#define CBR_RG_ADC_CLKSEL_SFT 0
+#define CBR_RG_ADC_CLKSEL_HI 0
+#define CBR_RG_ADC_CLKSEL_SZ 1
+#define CBR_RG_ADC_DIBIAS_MSK 0x00000006
+#define CBR_RG_ADC_DIBIAS_I_MSK 0xfffffff9
+#define CBR_RG_ADC_DIBIAS_SFT 1
+#define CBR_RG_ADC_DIBIAS_HI 2
+#define CBR_RG_ADC_DIBIAS_SZ 2
+#define CBR_RG_ADC_DIVR_MSK 0x00000008
+#define CBR_RG_ADC_DIVR_I_MSK 0xfffffff7
+#define CBR_RG_ADC_DIVR_SFT 3
+#define CBR_RG_ADC_DIVR_HI 3
+#define CBR_RG_ADC_DIVR_SZ 1
+#define CBR_RG_ADC_DVCMI_MSK 0x00000030
+#define CBR_RG_ADC_DVCMI_I_MSK 0xffffffcf
+#define CBR_RG_ADC_DVCMI_SFT 4
+#define CBR_RG_ADC_DVCMI_HI 5
+#define CBR_RG_ADC_DVCMI_SZ 2
+#define CBR_RG_ADC_SAMSEL_MSK 0x000003c0
+#define CBR_RG_ADC_SAMSEL_I_MSK 0xfffffc3f
+#define CBR_RG_ADC_SAMSEL_SFT 6
+#define CBR_RG_ADC_SAMSEL_HI 9
+#define CBR_RG_ADC_SAMSEL_SZ 4
+#define CBR_RG_ADC_STNBY_MSK 0x00000400
+#define CBR_RG_ADC_STNBY_I_MSK 0xfffffbff
+#define CBR_RG_ADC_STNBY_SFT 10
+#define CBR_RG_ADC_STNBY_HI 10
+#define CBR_RG_ADC_STNBY_SZ 1
+#define CBR_RG_ADC_TESTMODE_MSK 0x00000800
+#define CBR_RG_ADC_TESTMODE_I_MSK 0xfffff7ff
+#define CBR_RG_ADC_TESTMODE_SFT 11
+#define CBR_RG_ADC_TESTMODE_HI 11
+#define CBR_RG_ADC_TESTMODE_SZ 1
+#define CBR_RG_ADC_TSEL_MSK 0x0000f000
+#define CBR_RG_ADC_TSEL_I_MSK 0xffff0fff
+#define CBR_RG_ADC_TSEL_SFT 12
+#define CBR_RG_ADC_TSEL_HI 15
+#define CBR_RG_ADC_TSEL_SZ 4
+#define CBR_RG_ADC_VRSEL_MSK 0x00030000
+#define CBR_RG_ADC_VRSEL_I_MSK 0xfffcffff
+#define CBR_RG_ADC_VRSEL_SFT 16
+#define CBR_RG_ADC_VRSEL_HI 17
+#define CBR_RG_ADC_VRSEL_SZ 2
+#define CBR_RG_DICMP_MSK 0x000c0000
+#define CBR_RG_DICMP_I_MSK 0xfff3ffff
+#define CBR_RG_DICMP_SFT 18
+#define CBR_RG_DICMP_HI 19
+#define CBR_RG_DICMP_SZ 2
+#define CBR_RG_DIOP_MSK 0x00300000
+#define CBR_RG_DIOP_I_MSK 0xffcfffff
+#define CBR_RG_DIOP_SFT 20
+#define CBR_RG_DIOP_HI 21
+#define CBR_RG_DIOP_SZ 2
+#define CBR_RG_DACI1ST_MSK 0x00000003
+#define CBR_RG_DACI1ST_I_MSK 0xfffffffc
+#define CBR_RG_DACI1ST_SFT 0
+#define CBR_RG_DACI1ST_HI 1
+#define CBR_RG_DACI1ST_SZ 2
+#define CBR_RG_TX_DACLPF_ICOURSE_MSK 0x0000000c
+#define CBR_RG_TX_DACLPF_ICOURSE_I_MSK 0xfffffff3
+#define CBR_RG_TX_DACLPF_ICOURSE_SFT 2
+#define CBR_RG_TX_DACLPF_ICOURSE_HI 3
+#define CBR_RG_TX_DACLPF_ICOURSE_SZ 2
+#define CBR_RG_TX_DACLPF_IFINE_MSK 0x00000030
+#define CBR_RG_TX_DACLPF_IFINE_I_MSK 0xffffffcf
+#define CBR_RG_TX_DACLPF_IFINE_SFT 4
+#define CBR_RG_TX_DACLPF_IFINE_HI 5
+#define CBR_RG_TX_DACLPF_IFINE_SZ 2
+#define CBR_RG_TX_DACLPF_VCM_MSK 0x000000c0
+#define CBR_RG_TX_DACLPF_VCM_I_MSK 0xffffff3f
+#define CBR_RG_TX_DACLPF_VCM_SFT 6
+#define CBR_RG_TX_DACLPF_VCM_HI 7
+#define CBR_RG_TX_DACLPF_VCM_SZ 2
+#define CBR_RG_TX_DAC_CKEDGE_SEL_MSK 0x00000100
+#define CBR_RG_TX_DAC_CKEDGE_SEL_I_MSK 0xfffffeff
+#define CBR_RG_TX_DAC_CKEDGE_SEL_SFT 8
+#define CBR_RG_TX_DAC_CKEDGE_SEL_HI 8
+#define CBR_RG_TX_DAC_CKEDGE_SEL_SZ 1
+#define CBR_RG_TX_DAC_IBIAS_MSK 0x00000600
+#define CBR_RG_TX_DAC_IBIAS_I_MSK 0xfffff9ff
+#define CBR_RG_TX_DAC_IBIAS_SFT 9
+#define CBR_RG_TX_DAC_IBIAS_HI 10
+#define CBR_RG_TX_DAC_IBIAS_SZ 2
+#define CBR_RG_TX_DAC_OS_MSK 0x00003800
+#define CBR_RG_TX_DAC_OS_I_MSK 0xffffc7ff
+#define CBR_RG_TX_DAC_OS_SFT 11
+#define CBR_RG_TX_DAC_OS_HI 13
+#define CBR_RG_TX_DAC_OS_SZ 3
+#define CBR_RG_TX_DAC_RCAL_MSK 0x0000c000
+#define CBR_RG_TX_DAC_RCAL_I_MSK 0xffff3fff
+#define CBR_RG_TX_DAC_RCAL_SFT 14
+#define CBR_RG_TX_DAC_RCAL_HI 15
+#define CBR_RG_TX_DAC_RCAL_SZ 2
+#define CBR_RG_TX_DAC_TSEL_MSK 0x000f0000
+#define CBR_RG_TX_DAC_TSEL_I_MSK 0xfff0ffff
+#define CBR_RG_TX_DAC_TSEL_SFT 16
+#define CBR_RG_TX_DAC_TSEL_HI 19
+#define CBR_RG_TX_DAC_TSEL_SZ 4
+#define CBR_RG_TX_EN_VOLTAGE_IN_MSK 0x00100000
+#define CBR_RG_TX_EN_VOLTAGE_IN_I_MSK 0xffefffff
+#define CBR_RG_TX_EN_VOLTAGE_IN_SFT 20
+#define CBR_RG_TX_EN_VOLTAGE_IN_HI 20
+#define CBR_RG_TX_EN_VOLTAGE_IN_SZ 1
+#define CBR_RG_TXLPF_BYPASS_MSK 0x00200000
+#define CBR_RG_TXLPF_BYPASS_I_MSK 0xffdfffff
+#define CBR_RG_TXLPF_BYPASS_SFT 21
+#define CBR_RG_TXLPF_BYPASS_HI 21
+#define CBR_RG_TXLPF_BYPASS_SZ 1
+#define CBR_RG_TXLPF_BOOSTI_MSK 0x00400000
+#define CBR_RG_TXLPF_BOOSTI_I_MSK 0xffbfffff
+#define CBR_RG_TXLPF_BOOSTI_SFT 22
+#define CBR_RG_TXLPF_BOOSTI_HI 22
+#define CBR_RG_TXLPF_BOOSTI_SZ 1
+#define CBR_RG_EN_SX_R3_MSK 0x00000001
+#define CBR_RG_EN_SX_R3_I_MSK 0xfffffffe
+#define CBR_RG_EN_SX_R3_SFT 0
+#define CBR_RG_EN_SX_R3_HI 0
+#define CBR_RG_EN_SX_R3_SZ 1
+#define CBR_RG_EN_SX_CH_MSK 0x00000002
+#define CBR_RG_EN_SX_CH_I_MSK 0xfffffffd
+#define CBR_RG_EN_SX_CH_SFT 1
+#define CBR_RG_EN_SX_CH_HI 1
+#define CBR_RG_EN_SX_CH_SZ 1
+#define CBR_RG_EN_SX_CHP_MSK 0x00000004
+#define CBR_RG_EN_SX_CHP_I_MSK 0xfffffffb
+#define CBR_RG_EN_SX_CHP_SFT 2
+#define CBR_RG_EN_SX_CHP_HI 2
+#define CBR_RG_EN_SX_CHP_SZ 1
+#define CBR_RG_EN_SX_DIVCK_MSK 0x00000008
+#define CBR_RG_EN_SX_DIVCK_I_MSK 0xfffffff7
+#define CBR_RG_EN_SX_DIVCK_SFT 3
+#define CBR_RG_EN_SX_DIVCK_HI 3
+#define CBR_RG_EN_SX_DIVCK_SZ 1
+#define CBR_RG_EN_SX_VCOBF_MSK 0x00000010
+#define CBR_RG_EN_SX_VCOBF_I_MSK 0xffffffef
+#define CBR_RG_EN_SX_VCOBF_SFT 4
+#define CBR_RG_EN_SX_VCOBF_HI 4
+#define CBR_RG_EN_SX_VCOBF_SZ 1
+#define CBR_RG_EN_SX_VCO_MSK 0x00000020
+#define CBR_RG_EN_SX_VCO_I_MSK 0xffffffdf
+#define CBR_RG_EN_SX_VCO_SFT 5
+#define CBR_RG_EN_SX_VCO_HI 5
+#define CBR_RG_EN_SX_VCO_SZ 1
+#define CBR_RG_EN_SX_MOD_MSK 0x00000040
+#define CBR_RG_EN_SX_MOD_I_MSK 0xffffffbf
+#define CBR_RG_EN_SX_MOD_SFT 6
+#define CBR_RG_EN_SX_MOD_HI 6
+#define CBR_RG_EN_SX_MOD_SZ 1
+#define CBR_RG_EN_SX_LCK_MSK 0x00000080
+#define CBR_RG_EN_SX_LCK_I_MSK 0xffffff7f
+#define CBR_RG_EN_SX_LCK_SFT 7
+#define CBR_RG_EN_SX_LCK_HI 7
+#define CBR_RG_EN_SX_LCK_SZ 1
+#define CBR_RG_EN_SX_DITHER_MSK 0x00000100
+#define CBR_RG_EN_SX_DITHER_I_MSK 0xfffffeff
+#define CBR_RG_EN_SX_DITHER_SFT 8
+#define CBR_RG_EN_SX_DITHER_HI 8
+#define CBR_RG_EN_SX_DITHER_SZ 1
+#define CBR_RG_EN_SX_DELCAL_MSK 0x00000200
+#define CBR_RG_EN_SX_DELCAL_I_MSK 0xfffffdff
+#define CBR_RG_EN_SX_DELCAL_SFT 9
+#define CBR_RG_EN_SX_DELCAL_HI 9
+#define CBR_RG_EN_SX_DELCAL_SZ 1
+#define CBR_RG_EN_SX_PC_BYPASS_MSK 0x00000400
+#define CBR_RG_EN_SX_PC_BYPASS_I_MSK 0xfffffbff
+#define CBR_RG_EN_SX_PC_BYPASS_SFT 10
+#define CBR_RG_EN_SX_PC_BYPASS_HI 10
+#define CBR_RG_EN_SX_PC_BYPASS_SZ 1
+#define CBR_RG_EN_SX_VT_MON_MSK 0x00000800
+#define CBR_RG_EN_SX_VT_MON_I_MSK 0xfffff7ff
+#define CBR_RG_EN_SX_VT_MON_SFT 11
+#define CBR_RG_EN_SX_VT_MON_HI 11
+#define CBR_RG_EN_SX_VT_MON_SZ 1
+#define CBR_RG_EN_SX_VT_MON_DG_MSK 0x00001000
+#define CBR_RG_EN_SX_VT_MON_DG_I_MSK 0xffffefff
+#define CBR_RG_EN_SX_VT_MON_DG_SFT 12
+#define CBR_RG_EN_SX_VT_MON_DG_HI 12
+#define CBR_RG_EN_SX_VT_MON_DG_SZ 1
+#define CBR_RG_EN_SX_DIV_MSK 0x00002000
+#define CBR_RG_EN_SX_DIV_I_MSK 0xffffdfff
+#define CBR_RG_EN_SX_DIV_SFT 13
+#define CBR_RG_EN_SX_DIV_HI 13
+#define CBR_RG_EN_SX_DIV_SZ 1
+#define CBR_RG_EN_SX_LPF_MSK 0x00004000
+#define CBR_RG_EN_SX_LPF_I_MSK 0xffffbfff
+#define CBR_RG_EN_SX_LPF_SFT 14
+#define CBR_RG_EN_SX_LPF_HI 14
+#define CBR_RG_EN_SX_LPF_SZ 1
+#define CBR_RG_SX_RFCTRL_F_MSK 0x00ffffff
+#define CBR_RG_SX_RFCTRL_F_I_MSK 0xff000000
+#define CBR_RG_SX_RFCTRL_F_SFT 0
+#define CBR_RG_SX_RFCTRL_F_HI 23
+#define CBR_RG_SX_RFCTRL_F_SZ 24
+#define CBR_RG_SX_SEL_CP_MSK 0x0f000000
+#define CBR_RG_SX_SEL_CP_I_MSK 0xf0ffffff
+#define CBR_RG_SX_SEL_CP_SFT 24
+#define CBR_RG_SX_SEL_CP_HI 27
+#define CBR_RG_SX_SEL_CP_SZ 4
+#define CBR_RG_SX_SEL_CS_MSK 0xf0000000
+#define CBR_RG_SX_SEL_CS_I_MSK 0x0fffffff
+#define CBR_RG_SX_SEL_CS_SFT 28
+#define CBR_RG_SX_SEL_CS_HI 31
+#define CBR_RG_SX_SEL_CS_SZ 4
+#define CBR_RG_SX_RFCTRL_CH_MSK 0x000007ff
+#define CBR_RG_SX_RFCTRL_CH_I_MSK 0xfffff800
+#define CBR_RG_SX_RFCTRL_CH_SFT 0
+#define CBR_RG_SX_RFCTRL_CH_HI 10
+#define CBR_RG_SX_RFCTRL_CH_SZ 11
+#define CBR_RG_SX_SEL_C3_MSK 0x00007800
+#define CBR_RG_SX_SEL_C3_I_MSK 0xffff87ff
+#define CBR_RG_SX_SEL_C3_SFT 11
+#define CBR_RG_SX_SEL_C3_HI 14
+#define CBR_RG_SX_SEL_C3_SZ 4
+#define CBR_RG_SX_SEL_RS_MSK 0x000f8000
+#define CBR_RG_SX_SEL_RS_I_MSK 0xfff07fff
+#define CBR_RG_SX_SEL_RS_SFT 15
+#define CBR_RG_SX_SEL_RS_HI 19
+#define CBR_RG_SX_SEL_RS_SZ 5
+#define CBR_RG_SX_SEL_R3_MSK 0x01f00000
+#define CBR_RG_SX_SEL_R3_I_MSK 0xfe0fffff
+#define CBR_RG_SX_SEL_R3_SFT 20
+#define CBR_RG_SX_SEL_R3_HI 24
+#define CBR_RG_SX_SEL_R3_SZ 5
+#define CBR_RG_SX_SEL_ICHP_MSK 0x0000001f
+#define CBR_RG_SX_SEL_ICHP_I_MSK 0xffffffe0
+#define CBR_RG_SX_SEL_ICHP_SFT 0
+#define CBR_RG_SX_SEL_ICHP_HI 4
+#define CBR_RG_SX_SEL_ICHP_SZ 5
+#define CBR_RG_SX_SEL_PCHP_MSK 0x000003e0
+#define CBR_RG_SX_SEL_PCHP_I_MSK 0xfffffc1f
+#define CBR_RG_SX_SEL_PCHP_SFT 5
+#define CBR_RG_SX_SEL_PCHP_HI 9
+#define CBR_RG_SX_SEL_PCHP_SZ 5
+#define CBR_RG_SX_SEL_CHP_REGOP_MSK 0x00003c00
+#define CBR_RG_SX_SEL_CHP_REGOP_I_MSK 0xffffc3ff
+#define CBR_RG_SX_SEL_CHP_REGOP_SFT 10
+#define CBR_RG_SX_SEL_CHP_REGOP_HI 13
+#define CBR_RG_SX_SEL_CHP_REGOP_SZ 4
+#define CBR_RG_SX_SEL_CHP_UNIOP_MSK 0x0003c000
+#define CBR_RG_SX_SEL_CHP_UNIOP_I_MSK 0xfffc3fff
+#define CBR_RG_SX_SEL_CHP_UNIOP_SFT 14
+#define CBR_RG_SX_SEL_CHP_UNIOP_HI 17
+#define CBR_RG_SX_SEL_CHP_UNIOP_SZ 4
+#define CBR_RG_SX_CHP_IOST_POL_MSK 0x00040000
+#define CBR_RG_SX_CHP_IOST_POL_I_MSK 0xfffbffff
+#define CBR_RG_SX_CHP_IOST_POL_SFT 18
+#define CBR_RG_SX_CHP_IOST_POL_HI 18
+#define CBR_RG_SX_CHP_IOST_POL_SZ 1
+#define CBR_RG_SX_CHP_IOST_MSK 0x00380000
+#define CBR_RG_SX_CHP_IOST_I_MSK 0xffc7ffff
+#define CBR_RG_SX_CHP_IOST_SFT 19
+#define CBR_RG_SX_CHP_IOST_HI 21
+#define CBR_RG_SX_CHP_IOST_SZ 3
+#define CBR_RG_SX_PFDSEL_MSK 0x00400000
+#define CBR_RG_SX_PFDSEL_I_MSK 0xffbfffff
+#define CBR_RG_SX_PFDSEL_SFT 22
+#define CBR_RG_SX_PFDSEL_HI 22
+#define CBR_RG_SX_PFDSEL_SZ 1
+#define CBR_RG_SX_PFD_SET_MSK 0x00800000
+#define CBR_RG_SX_PFD_SET_I_MSK 0xff7fffff
+#define CBR_RG_SX_PFD_SET_SFT 23
+#define CBR_RG_SX_PFD_SET_HI 23
+#define CBR_RG_SX_PFD_SET_SZ 1
+#define CBR_RG_SX_PFD_SET1_MSK 0x01000000
+#define CBR_RG_SX_PFD_SET1_I_MSK 0xfeffffff
+#define CBR_RG_SX_PFD_SET1_SFT 24
+#define CBR_RG_SX_PFD_SET1_HI 24
+#define CBR_RG_SX_PFD_SET1_SZ 1
+#define CBR_RG_SX_PFD_SET2_MSK 0x02000000
+#define CBR_RG_SX_PFD_SET2_I_MSK 0xfdffffff
+#define CBR_RG_SX_PFD_SET2_SFT 25
+#define CBR_RG_SX_PFD_SET2_HI 25
+#define CBR_RG_SX_PFD_SET2_SZ 1
+#define CBR_RG_SX_VBNCAS_SEL_MSK 0x04000000
+#define CBR_RG_SX_VBNCAS_SEL_I_MSK 0xfbffffff
+#define CBR_RG_SX_VBNCAS_SEL_SFT 26
+#define CBR_RG_SX_VBNCAS_SEL_HI 26
+#define CBR_RG_SX_VBNCAS_SEL_SZ 1
+#define CBR_RG_SX_PFD_RST_H_MSK 0x08000000
+#define CBR_RG_SX_PFD_RST_H_I_MSK 0xf7ffffff
+#define CBR_RG_SX_PFD_RST_H_SFT 27
+#define CBR_RG_SX_PFD_RST_H_HI 27
+#define CBR_RG_SX_PFD_RST_H_SZ 1
+#define CBR_RG_SX_PFD_TRUP_MSK 0x10000000
+#define CBR_RG_SX_PFD_TRUP_I_MSK 0xefffffff
+#define CBR_RG_SX_PFD_TRUP_SFT 28
+#define CBR_RG_SX_PFD_TRUP_HI 28
+#define CBR_RG_SX_PFD_TRUP_SZ 1
+#define CBR_RG_SX_PFD_TRDN_MSK 0x20000000
+#define CBR_RG_SX_PFD_TRDN_I_MSK 0xdfffffff
+#define CBR_RG_SX_PFD_TRDN_SFT 29
+#define CBR_RG_SX_PFD_TRDN_HI 29
+#define CBR_RG_SX_PFD_TRDN_SZ 1
+#define CBR_RG_SX_PFD_TRSEL_MSK 0x40000000
+#define CBR_RG_SX_PFD_TRSEL_I_MSK 0xbfffffff
+#define CBR_RG_SX_PFD_TRSEL_SFT 30
+#define CBR_RG_SX_PFD_TRSEL_HI 30
+#define CBR_RG_SX_PFD_TRSEL_SZ 1
+#define CBR_RG_SX_VCOBA_R_MSK 0x00000007
+#define CBR_RG_SX_VCOBA_R_I_MSK 0xfffffff8
+#define CBR_RG_SX_VCOBA_R_SFT 0
+#define CBR_RG_SX_VCOBA_R_HI 2
+#define CBR_RG_SX_VCOBA_R_SZ 3
+#define CBR_RG_SX_VCORSEL_MSK 0x000000f8
+#define CBR_RG_SX_VCORSEL_I_MSK 0xffffff07
+#define CBR_RG_SX_VCORSEL_SFT 3
+#define CBR_RG_SX_VCORSEL_HI 7
+#define CBR_RG_SX_VCORSEL_SZ 5
+#define CBR_RG_SX_VCOCUSEL_MSK 0x00000f00
+#define CBR_RG_SX_VCOCUSEL_I_MSK 0xfffff0ff
+#define CBR_RG_SX_VCOCUSEL_SFT 8
+#define CBR_RG_SX_VCOCUSEL_HI 11
+#define CBR_RG_SX_VCOCUSEL_SZ 4
+#define CBR_RG_SX_RXBFSEL_MSK 0x0000f000
+#define CBR_RG_SX_RXBFSEL_I_MSK 0xffff0fff
+#define CBR_RG_SX_RXBFSEL_SFT 12
+#define CBR_RG_SX_RXBFSEL_HI 15
+#define CBR_RG_SX_RXBFSEL_SZ 4
+#define CBR_RG_SX_TXBFSEL_MSK 0x000f0000
+#define CBR_RG_SX_TXBFSEL_I_MSK 0xfff0ffff
+#define CBR_RG_SX_TXBFSEL_SFT 16
+#define CBR_RG_SX_TXBFSEL_HI 19
+#define CBR_RG_SX_TXBFSEL_SZ 4
+#define CBR_RG_SX_VCOBFSEL_MSK 0x00f00000
+#define CBR_RG_SX_VCOBFSEL_I_MSK 0xff0fffff
+#define CBR_RG_SX_VCOBFSEL_SFT 20
+#define CBR_RG_SX_VCOBFSEL_HI 23
+#define CBR_RG_SX_VCOBFSEL_SZ 4
+#define CBR_RG_SX_DIVBFSEL_MSK 0x0f000000
+#define CBR_RG_SX_DIVBFSEL_I_MSK 0xf0ffffff
+#define CBR_RG_SX_DIVBFSEL_SFT 24
+#define CBR_RG_SX_DIVBFSEL_HI 27
+#define CBR_RG_SX_DIVBFSEL_SZ 4
+#define CBR_RG_SX_GNDR_SEL_MSK 0xf0000000
+#define CBR_RG_SX_GNDR_SEL_I_MSK 0x0fffffff
+#define CBR_RG_SX_GNDR_SEL_SFT 28
+#define CBR_RG_SX_GNDR_SEL_HI 31
+#define CBR_RG_SX_GNDR_SEL_SZ 4
+#define CBR_RG_SX_DITHER_WEIGHT_MSK 0x00000003
+#define CBR_RG_SX_DITHER_WEIGHT_I_MSK 0xfffffffc
+#define CBR_RG_SX_DITHER_WEIGHT_SFT 0
+#define CBR_RG_SX_DITHER_WEIGHT_HI 1
+#define CBR_RG_SX_DITHER_WEIGHT_SZ 2
+#define CBR_RG_SX_MOD_ERRCMP_MSK 0x0000000c
+#define CBR_RG_SX_MOD_ERRCMP_I_MSK 0xfffffff3
+#define CBR_RG_SX_MOD_ERRCMP_SFT 2
+#define CBR_RG_SX_MOD_ERRCMP_HI 3
+#define CBR_RG_SX_MOD_ERRCMP_SZ 2
+#define CBR_RG_SX_MOD_ORDER_MSK 0x00000030
+#define CBR_RG_SX_MOD_ORDER_I_MSK 0xffffffcf
+#define CBR_RG_SX_MOD_ORDER_SFT 4
+#define CBR_RG_SX_MOD_ORDER_HI 5
+#define CBR_RG_SX_MOD_ORDER_SZ 2
+#define CBR_RG_SX_SDM_D1_MSK 0x00000040
+#define CBR_RG_SX_SDM_D1_I_MSK 0xffffffbf
+#define CBR_RG_SX_SDM_D1_SFT 6
+#define CBR_RG_SX_SDM_D1_HI 6
+#define CBR_RG_SX_SDM_D1_SZ 1
+#define CBR_RG_SX_SDM_D2_MSK 0x00000080
+#define CBR_RG_SX_SDM_D2_I_MSK 0xffffff7f
+#define CBR_RG_SX_SDM_D2_SFT 7
+#define CBR_RG_SX_SDM_D2_HI 7
+#define CBR_RG_SX_SDM_D2_SZ 1
+#define CBR_RG_SDM_PASS_MSK 0x00000100
+#define CBR_RG_SDM_PASS_I_MSK 0xfffffeff
+#define CBR_RG_SDM_PASS_SFT 8
+#define CBR_RG_SDM_PASS_HI 8
+#define CBR_RG_SDM_PASS_SZ 1
+#define CBR_RG_SX_RST_H_DIV_MSK 0x00000200
+#define CBR_RG_SX_RST_H_DIV_I_MSK 0xfffffdff
+#define CBR_RG_SX_RST_H_DIV_SFT 9
+#define CBR_RG_SX_RST_H_DIV_HI 9
+#define CBR_RG_SX_RST_H_DIV_SZ 1
+#define CBR_RG_SX_SDM_EDGE_MSK 0x00000400
+#define CBR_RG_SX_SDM_EDGE_I_MSK 0xfffffbff
+#define CBR_RG_SX_SDM_EDGE_SFT 10
+#define CBR_RG_SX_SDM_EDGE_HI 10
+#define CBR_RG_SX_SDM_EDGE_SZ 1
+#define CBR_RG_SX_XO_GM_MSK 0x00001800
+#define CBR_RG_SX_XO_GM_I_MSK 0xffffe7ff
+#define CBR_RG_SX_XO_GM_SFT 11
+#define CBR_RG_SX_XO_GM_HI 12
+#define CBR_RG_SX_XO_GM_SZ 2
+#define CBR_RG_SX_REFBYTWO_MSK 0x00002000
+#define CBR_RG_SX_REFBYTWO_I_MSK 0xffffdfff
+#define CBR_RG_SX_REFBYTWO_SFT 13
+#define CBR_RG_SX_REFBYTWO_HI 13
+#define CBR_RG_SX_REFBYTWO_SZ 1
+#define CBR_RG_SX_XO_SWCAP_MSK 0x0003c000
+#define CBR_RG_SX_XO_SWCAP_I_MSK 0xfffc3fff
+#define CBR_RG_SX_XO_SWCAP_SFT 14
+#define CBR_RG_SX_XO_SWCAP_HI 17
+#define CBR_RG_SX_XO_SWCAP_SZ 4
+#define CBR_RG_SX_SDMLUT_INV_MSK 0x00040000
+#define CBR_RG_SX_SDMLUT_INV_I_MSK 0xfffbffff
+#define CBR_RG_SX_SDMLUT_INV_SFT 18
+#define CBR_RG_SX_SDMLUT_INV_HI 18
+#define CBR_RG_SX_SDMLUT_INV_SZ 1
+#define CBR_RG_SX_LCKEN_MSK 0x00080000
+#define CBR_RG_SX_LCKEN_I_MSK 0xfff7ffff
+#define CBR_RG_SX_LCKEN_SFT 19
+#define CBR_RG_SX_LCKEN_HI 19
+#define CBR_RG_SX_LCKEN_SZ 1
+#define CBR_RG_SX_PREVDD_MSK 0x00f00000
+#define CBR_RG_SX_PREVDD_I_MSK 0xff0fffff
+#define CBR_RG_SX_PREVDD_SFT 20
+#define CBR_RG_SX_PREVDD_HI 23
+#define CBR_RG_SX_PREVDD_SZ 4
+#define CBR_RG_SX_PSCONTERVDD_MSK 0x0f000000
+#define CBR_RG_SX_PSCONTERVDD_I_MSK 0xf0ffffff
+#define CBR_RG_SX_PSCONTERVDD_SFT 24
+#define CBR_RG_SX_PSCONTERVDD_HI 27
+#define CBR_RG_SX_PSCONTERVDD_SZ 4
+#define CBR_RG_SX_MOD_ERR_DELAY_MSK 0x30000000
+#define CBR_RG_SX_MOD_ERR_DELAY_I_MSK 0xcfffffff
+#define CBR_RG_SX_MOD_ERR_DELAY_SFT 28
+#define CBR_RG_SX_MOD_ERR_DELAY_HI 29
+#define CBR_RG_SX_MOD_ERR_DELAY_SZ 2
+#define CBR_RG_SX_MODDB_MSK 0x40000000
+#define CBR_RG_SX_MODDB_I_MSK 0xbfffffff
+#define CBR_RG_SX_MODDB_SFT 30
+#define CBR_RG_SX_MODDB_HI 30
+#define CBR_RG_SX_MODDB_SZ 1
+#define CBR_RG_SX_CV_CURVE_SEL_MSK 0x00000003
+#define CBR_RG_SX_CV_CURVE_SEL_I_MSK 0xfffffffc
+#define CBR_RG_SX_CV_CURVE_SEL_SFT 0
+#define CBR_RG_SX_CV_CURVE_SEL_HI 1
+#define CBR_RG_SX_CV_CURVE_SEL_SZ 2
+#define CBR_RG_SX_SEL_DELAY_MSK 0x0000007c
+#define CBR_RG_SX_SEL_DELAY_I_MSK 0xffffff83
+#define CBR_RG_SX_SEL_DELAY_SFT 2
+#define CBR_RG_SX_SEL_DELAY_HI 6
+#define CBR_RG_SX_SEL_DELAY_SZ 5
+#define CBR_RG_SX_REF_CYCLE_MSK 0x00000780
+#define CBR_RG_SX_REF_CYCLE_I_MSK 0xfffff87f
+#define CBR_RG_SX_REF_CYCLE_SFT 7
+#define CBR_RG_SX_REF_CYCLE_HI 10
+#define CBR_RG_SX_REF_CYCLE_SZ 4
+#define CBR_RG_SX_VCOBY16_MSK 0x00000800
+#define CBR_RG_SX_VCOBY16_I_MSK 0xfffff7ff
+#define CBR_RG_SX_VCOBY16_SFT 11
+#define CBR_RG_SX_VCOBY16_HI 11
+#define CBR_RG_SX_VCOBY16_SZ 1
+#define CBR_RG_SX_VCOBY32_MSK 0x00001000
+#define CBR_RG_SX_VCOBY32_I_MSK 0xffffefff
+#define CBR_RG_SX_VCOBY32_SFT 12
+#define CBR_RG_SX_VCOBY32_HI 12
+#define CBR_RG_SX_VCOBY32_SZ 1
+#define CBR_RG_SX_PH_MSK 0x00002000
+#define CBR_RG_SX_PH_I_MSK 0xffffdfff
+#define CBR_RG_SX_PH_SFT 13
+#define CBR_RG_SX_PH_HI 13
+#define CBR_RG_SX_PH_SZ 1
+#define CBR_RG_SX_PL_MSK 0x00004000
+#define CBR_RG_SX_PL_I_MSK 0xffffbfff
+#define CBR_RG_SX_PL_SFT 14
+#define CBR_RG_SX_PL_HI 14
+#define CBR_RG_SX_PL_SZ 1
+#define CBR_RG_SX_VT_MON_MODE_MSK 0x00000001
+#define CBR_RG_SX_VT_MON_MODE_I_MSK 0xfffffffe
+#define CBR_RG_SX_VT_MON_MODE_SFT 0
+#define CBR_RG_SX_VT_MON_MODE_HI 0
+#define CBR_RG_SX_VT_MON_MODE_SZ 1
+#define CBR_RG_SX_VT_TH_HI_MSK 0x00000006
+#define CBR_RG_SX_VT_TH_HI_I_MSK 0xfffffff9
+#define CBR_RG_SX_VT_TH_HI_SFT 1
+#define CBR_RG_SX_VT_TH_HI_HI 2
+#define CBR_RG_SX_VT_TH_HI_SZ 2
+#define CBR_RG_SX_VT_TH_LO_MSK 0x00000018
+#define CBR_RG_SX_VT_TH_LO_I_MSK 0xffffffe7
+#define CBR_RG_SX_VT_TH_LO_SFT 3
+#define CBR_RG_SX_VT_TH_LO_HI 4
+#define CBR_RG_SX_VT_TH_LO_SZ 2
+#define CBR_RG_SX_VT_SET_MSK 0x00000020
+#define CBR_RG_SX_VT_SET_I_MSK 0xffffffdf
+#define CBR_RG_SX_VT_SET_SFT 5
+#define CBR_RG_SX_VT_SET_HI 5
+#define CBR_RG_SX_VT_SET_SZ 1
+#define CBR_RG_SX_VT_MON_TMR_MSK 0x00007fc0
+#define CBR_RG_SX_VT_MON_TMR_I_MSK 0xffff803f
+#define CBR_RG_SX_VT_MON_TMR_SFT 6
+#define CBR_RG_SX_VT_MON_TMR_HI 14
+#define CBR_RG_SX_VT_MON_TMR_SZ 9
+#define CBR_RG_IDEAL_CYCLE_MSK 0x0fff8000
+#define CBR_RG_IDEAL_CYCLE_I_MSK 0xf0007fff
+#define CBR_RG_IDEAL_CYCLE_SFT 15
+#define CBR_RG_IDEAL_CYCLE_HI 27
+#define CBR_RG_IDEAL_CYCLE_SZ 13
+#define CBR_RG_EN_DP_VT_MON_MSK 0x00000001
+#define CBR_RG_EN_DP_VT_MON_I_MSK 0xfffffffe
+#define CBR_RG_EN_DP_VT_MON_SFT 0
+#define CBR_RG_EN_DP_VT_MON_HI 0
+#define CBR_RG_EN_DP_VT_MON_SZ 1
+#define CBR_RG_DP_VT_TH_HI_MSK 0x00000006
+#define CBR_RG_DP_VT_TH_HI_I_MSK 0xfffffff9
+#define CBR_RG_DP_VT_TH_HI_SFT 1
+#define CBR_RG_DP_VT_TH_HI_HI 2
+#define CBR_RG_DP_VT_TH_HI_SZ 2
+#define CBR_RG_DP_VT_TH_LO_MSK 0x00000018
+#define CBR_RG_DP_VT_TH_LO_I_MSK 0xffffffe7
+#define CBR_RG_DP_VT_TH_LO_SFT 3
+#define CBR_RG_DP_VT_TH_LO_HI 4
+#define CBR_RG_DP_VT_TH_LO_SZ 2
+#define CBR_RG_DP_VT_MON_TMR_MSK 0x00003fe0
+#define CBR_RG_DP_VT_MON_TMR_I_MSK 0xffffc01f
+#define CBR_RG_DP_VT_MON_TMR_SFT 5
+#define CBR_RG_DP_VT_MON_TMR_HI 13
+#define CBR_RG_DP_VT_MON_TMR_SZ 9
+#define CBR_RG_DP_CK320BY2_MSK 0x00004000
+#define CBR_RG_DP_CK320BY2_I_MSK 0xffffbfff
+#define CBR_RG_DP_CK320BY2_SFT 14
+#define CBR_RG_DP_CK320BY2_HI 14
+#define CBR_RG_DP_CK320BY2_SZ 1
+#define CBR_RG_SX_DELCTRL_MSK 0x001f8000
+#define CBR_RG_SX_DELCTRL_I_MSK 0xffe07fff
+#define CBR_RG_SX_DELCTRL_SFT 15
+#define CBR_RG_SX_DELCTRL_HI 20
+#define CBR_RG_SX_DELCTRL_SZ 6
+#define CBR_RG_DP_OD_TEST_MSK 0x00200000
+#define CBR_RG_DP_OD_TEST_I_MSK 0xffdfffff
+#define CBR_RG_DP_OD_TEST_SFT 21
+#define CBR_RG_DP_OD_TEST_HI 21
+#define CBR_RG_DP_OD_TEST_SZ 1
+#define CBR_RG_DP_BBPLL_BP_MSK 0x00000001
+#define CBR_RG_DP_BBPLL_BP_I_MSK 0xfffffffe
+#define CBR_RG_DP_BBPLL_BP_SFT 0
+#define CBR_RG_DP_BBPLL_BP_HI 0
+#define CBR_RG_DP_BBPLL_BP_SZ 1
+#define CBR_RG_DP_BBPLL_ICP_MSK 0x00000006
+#define CBR_RG_DP_BBPLL_ICP_I_MSK 0xfffffff9
+#define CBR_RG_DP_BBPLL_ICP_SFT 1
+#define CBR_RG_DP_BBPLL_ICP_HI 2
+#define CBR_RG_DP_BBPLL_ICP_SZ 2
+#define CBR_RG_DP_BBPLL_IDUAL_MSK 0x00000018
+#define CBR_RG_DP_BBPLL_IDUAL_I_MSK 0xffffffe7
+#define CBR_RG_DP_BBPLL_IDUAL_SFT 3
+#define CBR_RG_DP_BBPLL_IDUAL_HI 4
+#define CBR_RG_DP_BBPLL_IDUAL_SZ 2
+#define CBR_RG_DP_BBPLL_OD_TEST_MSK 0x000001e0
+#define CBR_RG_DP_BBPLL_OD_TEST_I_MSK 0xfffffe1f
+#define CBR_RG_DP_BBPLL_OD_TEST_SFT 5
+#define CBR_RG_DP_BBPLL_OD_TEST_HI 8
+#define CBR_RG_DP_BBPLL_OD_TEST_SZ 4
+#define CBR_RG_DP_BBPLL_PD_MSK 0x00000200
+#define CBR_RG_DP_BBPLL_PD_I_MSK 0xfffffdff
+#define CBR_RG_DP_BBPLL_PD_SFT 9
+#define CBR_RG_DP_BBPLL_PD_HI 9
+#define CBR_RG_DP_BBPLL_PD_SZ 1
+#define CBR_RG_DP_BBPLL_TESTSEL_MSK 0x00001c00
+#define CBR_RG_DP_BBPLL_TESTSEL_I_MSK 0xffffe3ff
+#define CBR_RG_DP_BBPLL_TESTSEL_SFT 10
+#define CBR_RG_DP_BBPLL_TESTSEL_HI 12
+#define CBR_RG_DP_BBPLL_TESTSEL_SZ 3
+#define CBR_RG_DP_BBPLL_PFD_DLY_MSK 0x00006000
+#define CBR_RG_DP_BBPLL_PFD_DLY_I_MSK 0xffff9fff
+#define CBR_RG_DP_BBPLL_PFD_DLY_SFT 13
+#define CBR_RG_DP_BBPLL_PFD_DLY_HI 14
+#define CBR_RG_DP_BBPLL_PFD_DLY_SZ 2
+#define CBR_RG_DP_RP_MSK 0x00038000
+#define CBR_RG_DP_RP_I_MSK 0xfffc7fff
+#define CBR_RG_DP_RP_SFT 15
+#define CBR_RG_DP_RP_HI 17
+#define CBR_RG_DP_RP_SZ 3
+#define CBR_RG_DP_RHP_MSK 0x000c0000
+#define CBR_RG_DP_RHP_I_MSK 0xfff3ffff
+#define CBR_RG_DP_RHP_SFT 18
+#define CBR_RG_DP_RHP_HI 19
+#define CBR_RG_DP_RHP_SZ 2
+#define CBR_RG_DP_DR3_MSK 0x00700000
+#define CBR_RG_DP_DR3_I_MSK 0xff8fffff
+#define CBR_RG_DP_DR3_SFT 20
+#define CBR_RG_DP_DR3_HI 22
+#define CBR_RG_DP_DR3_SZ 3
+#define CBR_RG_DP_DCP_MSK 0x07800000
+#define CBR_RG_DP_DCP_I_MSK 0xf87fffff
+#define CBR_RG_DP_DCP_SFT 23
+#define CBR_RG_DP_DCP_HI 26
+#define CBR_RG_DP_DCP_SZ 4
+#define CBR_RG_DP_DCS_MSK 0x78000000
+#define CBR_RG_DP_DCS_I_MSK 0x87ffffff
+#define CBR_RG_DP_DCS_SFT 27
+#define CBR_RG_DP_DCS_HI 30
+#define CBR_RG_DP_DCS_SZ 4
+#define CBR_RG_DP_FBDIV_MSK 0x00000fff
+#define CBR_RG_DP_FBDIV_I_MSK 0xfffff000
+#define CBR_RG_DP_FBDIV_SFT 0
+#define CBR_RG_DP_FBDIV_HI 11
+#define CBR_RG_DP_FBDIV_SZ 12
+#define CBR_RG_DP_FODIV_MSK 0x003ff000
+#define CBR_RG_DP_FODIV_I_MSK 0xffc00fff
+#define CBR_RG_DP_FODIV_SFT 12
+#define CBR_RG_DP_FODIV_HI 21
+#define CBR_RG_DP_FODIV_SZ 10
+#define CBR_RG_DP_REFDIV_MSK 0xffc00000
+#define CBR_RG_DP_REFDIV_I_MSK 0x003fffff
+#define CBR_RG_DP_REFDIV_SFT 22
+#define CBR_RG_DP_REFDIV_HI 31
+#define CBR_RG_DP_REFDIV_SZ 10
+#define CBR_RG_IDACAI_PGAG15_MSK 0x0000003f
+#define CBR_RG_IDACAI_PGAG15_I_MSK 0xffffffc0
+#define CBR_RG_IDACAI_PGAG15_SFT 0
+#define CBR_RG_IDACAI_PGAG15_HI 5
+#define CBR_RG_IDACAI_PGAG15_SZ 6
+#define CBR_RG_IDACAQ_PGAG15_MSK 0x00000fc0
+#define CBR_RG_IDACAQ_PGAG15_I_MSK 0xfffff03f
+#define CBR_RG_IDACAQ_PGAG15_SFT 6
+#define CBR_RG_IDACAQ_PGAG15_HI 11
+#define CBR_RG_IDACAQ_PGAG15_SZ 6
+#define CBR_RG_IDACAI_PGAG14_MSK 0x0003f000
+#define CBR_RG_IDACAI_PGAG14_I_MSK 0xfffc0fff
+#define CBR_RG_IDACAI_PGAG14_SFT 12
+#define CBR_RG_IDACAI_PGAG14_HI 17
+#define CBR_RG_IDACAI_PGAG14_SZ 6
+#define CBR_RG_IDACAQ_PGAG14_MSK 0x00fc0000
+#define CBR_RG_IDACAQ_PGAG14_I_MSK 0xff03ffff
+#define CBR_RG_IDACAQ_PGAG14_SFT 18
+#define CBR_RG_IDACAQ_PGAG14_HI 23
+#define CBR_RG_IDACAQ_PGAG14_SZ 6
+#define CBR_RG_IDACAI_PGAG13_MSK 0x0000003f
+#define CBR_RG_IDACAI_PGAG13_I_MSK 0xffffffc0
+#define CBR_RG_IDACAI_PGAG13_SFT 0
+#define CBR_RG_IDACAI_PGAG13_HI 5
+#define CBR_RG_IDACAI_PGAG13_SZ 6
+#define CBR_RG_IDACAQ_PGAG13_MSK 0x00000fc0
+#define CBR_RG_IDACAQ_PGAG13_I_MSK 0xfffff03f
+#define CBR_RG_IDACAQ_PGAG13_SFT 6
+#define CBR_RG_IDACAQ_PGAG13_HI 11
+#define CBR_RG_IDACAQ_PGAG13_SZ 6
+#define CBR_RG_IDACAI_PGAG12_MSK 0x0003f000
+#define CBR_RG_IDACAI_PGAG12_I_MSK 0xfffc0fff
+#define CBR_RG_IDACAI_PGAG12_SFT 12
+#define CBR_RG_IDACAI_PGAG12_HI 17
+#define CBR_RG_IDACAI_PGAG12_SZ 6
+#define CBR_RG_IDACAQ_PGAG12_MSK 0x00fc0000
+#define CBR_RG_IDACAQ_PGAG12_I_MSK 0xff03ffff
+#define CBR_RG_IDACAQ_PGAG12_SFT 18
+#define CBR_RG_IDACAQ_PGAG12_HI 23
+#define CBR_RG_IDACAQ_PGAG12_SZ 6
+#define CBR_RG_IDACAI_PGAG11_MSK 0x0000003f
+#define CBR_RG_IDACAI_PGAG11_I_MSK 0xffffffc0
+#define CBR_RG_IDACAI_PGAG11_SFT 0
+#define CBR_RG_IDACAI_PGAG11_HI 5
+#define CBR_RG_IDACAI_PGAG11_SZ 6
+#define CBR_RG_IDACAQ_PGAG11_MSK 0x00000fc0
+#define CBR_RG_IDACAQ_PGAG11_I_MSK 0xfffff03f
+#define CBR_RG_IDACAQ_PGAG11_SFT 6
+#define CBR_RG_IDACAQ_PGAG11_HI 11
+#define CBR_RG_IDACAQ_PGAG11_SZ 6
+#define CBR_RG_IDACAI_PGAG10_MSK 0x0003f000
+#define CBR_RG_IDACAI_PGAG10_I_MSK 0xfffc0fff
+#define CBR_RG_IDACAI_PGAG10_SFT 12
+#define CBR_RG_IDACAI_PGAG10_HI 17
+#define CBR_RG_IDACAI_PGAG10_SZ 6
+#define CBR_RG_IDACAQ_PGAG10_MSK 0x00fc0000
+#define CBR_RG_IDACAQ_PGAG10_I_MSK 0xff03ffff
+#define CBR_RG_IDACAQ_PGAG10_SFT 18
+#define CBR_RG_IDACAQ_PGAG10_HI 23
+#define CBR_RG_IDACAQ_PGAG10_SZ 6
+#define CBR_RG_IDACAI_PGAG9_MSK 0x0000003f
+#define CBR_RG_IDACAI_PGAG9_I_MSK 0xffffffc0
+#define CBR_RG_IDACAI_PGAG9_SFT 0
+#define CBR_RG_IDACAI_PGAG9_HI 5
+#define CBR_RG_IDACAI_PGAG9_SZ 6
+#define CBR_RG_IDACAQ_PGAG9_MSK 0x00000fc0
+#define CBR_RG_IDACAQ_PGAG9_I_MSK 0xfffff03f
+#define CBR_RG_IDACAQ_PGAG9_SFT 6
+#define CBR_RG_IDACAQ_PGAG9_HI 11
+#define CBR_RG_IDACAQ_PGAG9_SZ 6
+#define CBR_RG_IDACAI_PGAG8_MSK 0x0003f000
+#define CBR_RG_IDACAI_PGAG8_I_MSK 0xfffc0fff
+#define CBR_RG_IDACAI_PGAG8_SFT 12
+#define CBR_RG_IDACAI_PGAG8_HI 17
+#define CBR_RG_IDACAI_PGAG8_SZ 6
+#define CBR_RG_IDACAQ_PGAG8_MSK 0x00fc0000
+#define CBR_RG_IDACAQ_PGAG8_I_MSK 0xff03ffff
+#define CBR_RG_IDACAQ_PGAG8_SFT 18
+#define CBR_RG_IDACAQ_PGAG8_HI 23
+#define CBR_RG_IDACAQ_PGAG8_SZ 6
+#define CBR_RG_IDACAI_PGAG7_MSK 0x0000003f
+#define CBR_RG_IDACAI_PGAG7_I_MSK 0xffffffc0
+#define CBR_RG_IDACAI_PGAG7_SFT 0
+#define CBR_RG_IDACAI_PGAG7_HI 5
+#define CBR_RG_IDACAI_PGAG7_SZ 6
+#define CBR_RG_IDACAQ_PGAG7_MSK 0x00000fc0
+#define CBR_RG_IDACAQ_PGAG7_I_MSK 0xfffff03f
+#define CBR_RG_IDACAQ_PGAG7_SFT 6
+#define CBR_RG_IDACAQ_PGAG7_HI 11
+#define CBR_RG_IDACAQ_PGAG7_SZ 6
+#define CBR_RG_IDACAI_PGAG6_MSK 0x0003f000
+#define CBR_RG_IDACAI_PGAG6_I_MSK 0xfffc0fff
+#define CBR_RG_IDACAI_PGAG6_SFT 12
+#define CBR_RG_IDACAI_PGAG6_HI 17
+#define CBR_RG_IDACAI_PGAG6_SZ 6
+#define CBR_RG_IDACAQ_PGAG6_MSK 0x00fc0000
+#define CBR_RG_IDACAQ_PGAG6_I_MSK 0xff03ffff
+#define CBR_RG_IDACAQ_PGAG6_SFT 18
+#define CBR_RG_IDACAQ_PGAG6_HI 23
+#define CBR_RG_IDACAQ_PGAG6_SZ 6
+#define CBR_RG_IDACAI_PGAG5_MSK 0x0000003f
+#define CBR_RG_IDACAI_PGAG5_I_MSK 0xffffffc0
+#define CBR_RG_IDACAI_PGAG5_SFT 0
+#define CBR_RG_IDACAI_PGAG5_HI 5
+#define CBR_RG_IDACAI_PGAG5_SZ 6
+#define CBR_RG_IDACAQ_PGAG5_MSK 0x00000fc0
+#define CBR_RG_IDACAQ_PGAG5_I_MSK 0xfffff03f
+#define CBR_RG_IDACAQ_PGAG5_SFT 6
+#define CBR_RG_IDACAQ_PGAG5_HI 11
+#define CBR_RG_IDACAQ_PGAG5_SZ 6
+#define CBR_RG_IDACAI_PGAG4_MSK 0x0003f000
+#define CBR_RG_IDACAI_PGAG4_I_MSK 0xfffc0fff
+#define CBR_RG_IDACAI_PGAG4_SFT 12
+#define CBR_RG_IDACAI_PGAG4_HI 17
+#define CBR_RG_IDACAI_PGAG4_SZ 6
+#define CBR_RG_IDACAQ_PGAG4_MSK 0x00fc0000
+#define CBR_RG_IDACAQ_PGAG4_I_MSK 0xff03ffff
+#define CBR_RG_IDACAQ_PGAG4_SFT 18
+#define CBR_RG_IDACAQ_PGAG4_HI 23
+#define CBR_RG_IDACAQ_PGAG4_SZ 6
+#define CBR_RG_IDACAI_PGAG3_MSK 0x0000003f
+#define CBR_RG_IDACAI_PGAG3_I_MSK 0xffffffc0
+#define CBR_RG_IDACAI_PGAG3_SFT 0
+#define CBR_RG_IDACAI_PGAG3_HI 5
+#define CBR_RG_IDACAI_PGAG3_SZ 6
+#define CBR_RG_IDACAQ_PGAG3_MSK 0x00000fc0
+#define CBR_RG_IDACAQ_PGAG3_I_MSK 0xfffff03f
+#define CBR_RG_IDACAQ_PGAG3_SFT 6
+#define CBR_RG_IDACAQ_PGAG3_HI 11
+#define CBR_RG_IDACAQ_PGAG3_SZ 6
+#define CBR_RG_IDACAI_PGAG2_MSK 0x0003f000
+#define CBR_RG_IDACAI_PGAG2_I_MSK 0xfffc0fff
+#define CBR_RG_IDACAI_PGAG2_SFT 12
+#define CBR_RG_IDACAI_PGAG2_HI 17
+#define CBR_RG_IDACAI_PGAG2_SZ 6
+#define CBR_RG_IDACAQ_PGAG2_MSK 0x00fc0000
+#define CBR_RG_IDACAQ_PGAG2_I_MSK 0xff03ffff
+#define CBR_RG_IDACAQ_PGAG2_SFT 18
+#define CBR_RG_IDACAQ_PGAG2_HI 23
+#define CBR_RG_IDACAQ_PGAG2_SZ 6
+#define CBR_RG_IDACAI_PGAG1_MSK 0x0000003f
+#define CBR_RG_IDACAI_PGAG1_I_MSK 0xffffffc0
+#define CBR_RG_IDACAI_PGAG1_SFT 0
+#define CBR_RG_IDACAI_PGAG1_HI 5
+#define CBR_RG_IDACAI_PGAG1_SZ 6
+#define CBR_RG_IDACAQ_PGAG1_MSK 0x00000fc0
+#define CBR_RG_IDACAQ_PGAG1_I_MSK 0xfffff03f
+#define CBR_RG_IDACAQ_PGAG1_SFT 6
+#define CBR_RG_IDACAQ_PGAG1_HI 11
+#define CBR_RG_IDACAQ_PGAG1_SZ 6
+#define CBR_RG_IDACAI_PGAG0_MSK 0x0003f000
+#define CBR_RG_IDACAI_PGAG0_I_MSK 0xfffc0fff
+#define CBR_RG_IDACAI_PGAG0_SFT 12
+#define CBR_RG_IDACAI_PGAG0_HI 17
+#define CBR_RG_IDACAI_PGAG0_SZ 6
+#define CBR_RG_IDACAQ_PGAG0_MSK 0x00fc0000
+#define CBR_RG_IDACAQ_PGAG0_I_MSK 0xff03ffff
+#define CBR_RG_IDACAQ_PGAG0_SFT 18
+#define CBR_RG_IDACAQ_PGAG0_HI 23
+#define CBR_RG_IDACAQ_PGAG0_SZ 6
+#define CBR_RG_EN_RCAL_MSK 0x00000001
+#define CBR_RG_EN_RCAL_I_MSK 0xfffffffe
+#define CBR_RG_EN_RCAL_SFT 0
+#define CBR_RG_EN_RCAL_HI 0
+#define CBR_RG_EN_RCAL_SZ 1
+#define CBR_RG_RCAL_SPD_MSK 0x00000002
+#define CBR_RG_RCAL_SPD_I_MSK 0xfffffffd
+#define CBR_RG_RCAL_SPD_SFT 1
+#define CBR_RG_RCAL_SPD_HI 1
+#define CBR_RG_RCAL_SPD_SZ 1
+#define CBR_RG_RCAL_TMR_MSK 0x000001fc
+#define CBR_RG_RCAL_TMR_I_MSK 0xfffffe03
+#define CBR_RG_RCAL_TMR_SFT 2
+#define CBR_RG_RCAL_TMR_HI 8
+#define CBR_RG_RCAL_TMR_SZ 7
+#define CBR_RG_RCAL_CODE_CWR_MSK 0x00000200
+#define CBR_RG_RCAL_CODE_CWR_I_MSK 0xfffffdff
+#define CBR_RG_RCAL_CODE_CWR_SFT 9
+#define CBR_RG_RCAL_CODE_CWR_HI 9
+#define CBR_RG_RCAL_CODE_CWR_SZ 1
+#define CBR_RG_RCAL_CODE_CWD_MSK 0x00007c00
+#define CBR_RG_RCAL_CODE_CWD_I_MSK 0xffff83ff
+#define CBR_RG_RCAL_CODE_CWD_SFT 10
+#define CBR_RG_RCAL_CODE_CWD_HI 14
+#define CBR_RG_RCAL_CODE_CWD_SZ 5
+#define CBR_RG_SX_SUB_SEL_CWR_MSK 0x00000001
+#define CBR_RG_SX_SUB_SEL_CWR_I_MSK 0xfffffffe
+#define CBR_RG_SX_SUB_SEL_CWR_SFT 0
+#define CBR_RG_SX_SUB_SEL_CWR_HI 0
+#define CBR_RG_SX_SUB_SEL_CWR_SZ 1
+#define CBR_RG_SX_SUB_SEL_CWD_MSK 0x000000fe
+#define CBR_RG_SX_SUB_SEL_CWD_I_MSK 0xffffff01
+#define CBR_RG_SX_SUB_SEL_CWD_SFT 1
+#define CBR_RG_SX_SUB_SEL_CWD_HI 7
+#define CBR_RG_SX_SUB_SEL_CWD_SZ 7
+#define CBR_RG_DP_BBPLL_BS_CWR_MSK 0x00000100
+#define CBR_RG_DP_BBPLL_BS_CWR_I_MSK 0xfffffeff
+#define CBR_RG_DP_BBPLL_BS_CWR_SFT 8
+#define CBR_RG_DP_BBPLL_BS_CWR_HI 8
+#define CBR_RG_DP_BBPLL_BS_CWR_SZ 1
+#define CBR_RG_DP_BBPLL_BS_CWD_MSK 0x00007e00
+#define CBR_RG_DP_BBPLL_BS_CWD_I_MSK 0xffff81ff
+#define CBR_RG_DP_BBPLL_BS_CWD_SFT 9
+#define CBR_RG_DP_BBPLL_BS_CWD_HI 14
+#define CBR_RG_DP_BBPLL_BS_CWD_SZ 6
+#define CBR_RCAL_RDY_MSK 0x00000001
+#define CBR_RCAL_RDY_I_MSK 0xfffffffe
+#define CBR_RCAL_RDY_SFT 0
+#define CBR_RCAL_RDY_HI 0
+#define CBR_RCAL_RDY_SZ 1
+#define CBR_DA_LCK_RDY_MSK 0x00000002
+#define CBR_DA_LCK_RDY_I_MSK 0xfffffffd
+#define CBR_DA_LCK_RDY_SFT 1
+#define CBR_DA_LCK_RDY_HI 1
+#define CBR_DA_LCK_RDY_SZ 1
+#define CBR_VT_MON_RDY_MSK 0x00000004
+#define CBR_VT_MON_RDY_I_MSK 0xfffffffb
+#define CBR_VT_MON_RDY_SFT 2
+#define CBR_VT_MON_RDY_HI 2
+#define CBR_VT_MON_RDY_SZ 1
+#define CBR_DP_VT_MON_RDY_MSK 0x00000008
+#define CBR_DP_VT_MON_RDY_I_MSK 0xfffffff7
+#define CBR_DP_VT_MON_RDY_SFT 3
+#define CBR_DP_VT_MON_RDY_HI 3
+#define CBR_DP_VT_MON_RDY_SZ 1
+#define CBR_CH_RDY_MSK 0x00000010
+#define CBR_CH_RDY_I_MSK 0xffffffef
+#define CBR_CH_RDY_SFT 4
+#define CBR_CH_RDY_HI 4
+#define CBR_CH_RDY_SZ 1
+#define CBR_DA_R_CODE_LUT_MSK 0x000007c0
+#define CBR_DA_R_CODE_LUT_I_MSK 0xfffff83f
+#define CBR_DA_R_CODE_LUT_SFT 6
+#define CBR_DA_R_CODE_LUT_HI 10
+#define CBR_DA_R_CODE_LUT_SZ 5
+#define CBR_AD_SX_VT_MON_Q_MSK 0x00001800
+#define CBR_AD_SX_VT_MON_Q_I_MSK 0xffffe7ff
+#define CBR_AD_SX_VT_MON_Q_SFT 11
+#define CBR_AD_SX_VT_MON_Q_HI 12
+#define CBR_AD_SX_VT_MON_Q_SZ 2
+#define CBR_AD_DP_VT_MON_Q_MSK 0x00006000
+#define CBR_AD_DP_VT_MON_Q_I_MSK 0xffff9fff
+#define CBR_AD_DP_VT_MON_Q_SFT 13
+#define CBR_AD_DP_VT_MON_Q_HI 14
+#define CBR_AD_DP_VT_MON_Q_SZ 2
+#define CBR_DA_R_CAL_CODE_MSK 0x0000001f
+#define CBR_DA_R_CAL_CODE_I_MSK 0xffffffe0
+#define CBR_DA_R_CAL_CODE_SFT 0
+#define CBR_DA_R_CAL_CODE_HI 4
+#define CBR_DA_R_CAL_CODE_SZ 5
+#define CBR_DA_SX_SUB_SEL_MSK 0x00000fe0
+#define CBR_DA_SX_SUB_SEL_I_MSK 0xfffff01f
+#define CBR_DA_SX_SUB_SEL_SFT 5
+#define CBR_DA_SX_SUB_SEL_HI 11
+#define CBR_DA_SX_SUB_SEL_SZ 7
+#define CBR_DA_DP_BBPLL_BS_MSK 0x0003f000
+#define CBR_DA_DP_BBPLL_BS_I_MSK 0xfffc0fff
+#define CBR_DA_DP_BBPLL_BS_SFT 12
+#define CBR_DA_DP_BBPLL_BS_HI 17
+#define CBR_DA_DP_BBPLL_BS_SZ 6
+#define CBR_TX_EN_MSK 0x00000001
+#define CBR_TX_EN_I_MSK 0xfffffffe
+#define CBR_TX_EN_SFT 0
+#define CBR_TX_EN_HI 0
+#define CBR_TX_EN_SZ 1
+#define CBR_TX_CNT_RST_MSK 0x00000002
+#define CBR_TX_CNT_RST_I_MSK 0xfffffffd
+#define CBR_TX_CNT_RST_SFT 1
+#define CBR_TX_CNT_RST_HI 1
+#define CBR_TX_CNT_RST_SZ 1
+#define CBR_IFS_TIME_MSK 0x000000fc
+#define CBR_IFS_TIME_I_MSK 0xffffff03
+#define CBR_IFS_TIME_SFT 2
+#define CBR_IFS_TIME_HI 7
+#define CBR_IFS_TIME_SZ 6
+#define CBR_LENGTH_TARGET_MSK 0x000fff00
+#define CBR_LENGTH_TARGET_I_MSK 0xfff000ff
+#define CBR_LENGTH_TARGET_SFT 8
+#define CBR_LENGTH_TARGET_HI 19
+#define CBR_LENGTH_TARGET_SZ 12
+#define CBR_TX_CNT_TARGET_MSK 0xff000000
+#define CBR_TX_CNT_TARGET_I_MSK 0x00ffffff
+#define CBR_TX_CNT_TARGET_SFT 24
+#define CBR_TX_CNT_TARGET_HI 31
+#define CBR_TX_CNT_TARGET_SZ 8
+#define CBR_TC_CNT_TARGET_MSK 0x00ffffff
+#define CBR_TC_CNT_TARGET_I_MSK 0xff000000
+#define CBR_TC_CNT_TARGET_SFT 0
+#define CBR_TC_CNT_TARGET_HI 23
+#define CBR_TC_CNT_TARGET_SZ 24
+#define CBR_PLCP_PSDU_DATA_MEM_MSK 0x000000ff
+#define CBR_PLCP_PSDU_DATA_MEM_I_MSK 0xffffff00
+#define CBR_PLCP_PSDU_DATA_MEM_SFT 0
+#define CBR_PLCP_PSDU_DATA_MEM_HI 7
+#define CBR_PLCP_PSDU_DATA_MEM_SZ 8
+#define CBR_PLCP_PSDU_PREAMBLE_SHORT_MSK 0x00000100
+#define CBR_PLCP_PSDU_PREAMBLE_SHORT_I_MSK 0xfffffeff
+#define CBR_PLCP_PSDU_PREAMBLE_SHORT_SFT 8
+#define CBR_PLCP_PSDU_PREAMBLE_SHORT_HI 8
+#define CBR_PLCP_PSDU_PREAMBLE_SHORT_SZ 1
+#define CBR_PLCP_BYTE_LENGTH_MSK 0x001ffe00
+#define CBR_PLCP_BYTE_LENGTH_I_MSK 0xffe001ff
+#define CBR_PLCP_BYTE_LENGTH_SFT 9
+#define CBR_PLCP_BYTE_LENGTH_HI 20
+#define CBR_PLCP_BYTE_LENGTH_SZ 12
+#define CBR_PLCP_PSDU_RATE_MSK 0x00600000
+#define CBR_PLCP_PSDU_RATE_I_MSK 0xff9fffff
+#define CBR_PLCP_PSDU_RATE_SFT 21
+#define CBR_PLCP_PSDU_RATE_HI 22
+#define CBR_PLCP_PSDU_RATE_SZ 2
+#define CBR_TAIL_TIME_MSK 0x1f800000
+#define CBR_TAIL_TIME_I_MSK 0xe07fffff
+#define CBR_TAIL_TIME_SFT 23
+#define CBR_TAIL_TIME_HI 28
+#define CBR_TAIL_TIME_SZ 6
+#define CBR_RG_O_PAD_PD_MSK 0x00000001
+#define CBR_RG_O_PAD_PD_I_MSK 0xfffffffe
+#define CBR_RG_O_PAD_PD_SFT 0
+#define CBR_RG_O_PAD_PD_HI 0
+#define CBR_RG_O_PAD_PD_SZ 1
+#define CBR_RG_I_PAD_PD_MSK 0x00000002
+#define CBR_RG_I_PAD_PD_I_MSK 0xfffffffd
+#define CBR_RG_I_PAD_PD_SFT 1
+#define CBR_RG_I_PAD_PD_HI 1
+#define CBR_RG_I_PAD_PD_SZ 1
+#define CBR_SEL_ADCKP_INV_MSK 0x00000004
+#define CBR_SEL_ADCKP_INV_I_MSK 0xfffffffb
+#define CBR_SEL_ADCKP_INV_SFT 2
+#define CBR_SEL_ADCKP_INV_HI 2
+#define CBR_SEL_ADCKP_INV_SZ 1
+#define CBR_RG_PAD_DS_MSK 0x00000008
+#define CBR_RG_PAD_DS_I_MSK 0xfffffff7
+#define CBR_RG_PAD_DS_SFT 3
+#define CBR_RG_PAD_DS_HI 3
+#define CBR_RG_PAD_DS_SZ 1
+#define CBR_SEL_ADCKP_MUX_MSK 0x00000010
+#define CBR_SEL_ADCKP_MUX_I_MSK 0xffffffef
+#define CBR_SEL_ADCKP_MUX_SFT 4
+#define CBR_SEL_ADCKP_MUX_HI 4
+#define CBR_SEL_ADCKP_MUX_SZ 1
+#define CBR_RG_PAD_DS_CLK_MSK 0x00000020
+#define CBR_RG_PAD_DS_CLK_I_MSK 0xffffffdf
+#define CBR_RG_PAD_DS_CLK_SFT 5
+#define CBR_RG_PAD_DS_CLK_HI 5
+#define CBR_RG_PAD_DS_CLK_SZ 1
+#define CBR_INTP_SEL_MSK 0x00000200
+#define CBR_INTP_SEL_I_MSK 0xfffffdff
+#define CBR_INTP_SEL_SFT 9
+#define CBR_INTP_SEL_HI 9
+#define CBR_INTP_SEL_SZ 1
+#define CBR_IQ_SWP_MSK 0x00000400
+#define CBR_IQ_SWP_I_MSK 0xfffffbff
+#define CBR_IQ_SWP_SFT 10
+#define CBR_IQ_SWP_HI 10
+#define CBR_IQ_SWP_SZ 1
+#define CBR_RG_EN_EXT_DA_MSK 0x00000800
+#define CBR_RG_EN_EXT_DA_I_MSK 0xfffff7ff
+#define CBR_RG_EN_EXT_DA_SFT 11
+#define CBR_RG_EN_EXT_DA_HI 11
+#define CBR_RG_EN_EXT_DA_SZ 1
+#define CBR_RG_DIS_DA_OFFSET_MSK 0x00001000
+#define CBR_RG_DIS_DA_OFFSET_I_MSK 0xffffefff
+#define CBR_RG_DIS_DA_OFFSET_SFT 12
+#define CBR_RG_DIS_DA_OFFSET_HI 12
+#define CBR_RG_DIS_DA_OFFSET_SZ 1
+#define CBR_DBG_SEL_MSK 0x000f0000
+#define CBR_DBG_SEL_I_MSK 0xfff0ffff
+#define CBR_DBG_SEL_SFT 16
+#define CBR_DBG_SEL_HI 19
+#define CBR_DBG_SEL_SZ 4
+#define CBR_DBG_EN_MSK 0x00100000
+#define CBR_DBG_EN_I_MSK 0xffefffff
+#define CBR_DBG_EN_SFT 20
+#define CBR_DBG_EN_HI 20
+#define CBR_DBG_EN_SZ 1
+#define CBR_RG_PKT_GEN_TX_CNT_MSK 0xffffffff
+#define CBR_RG_PKT_GEN_TX_CNT_I_MSK 0x00000000
+#define CBR_RG_PKT_GEN_TX_CNT_SFT 0
+#define CBR_RG_PKT_GEN_TX_CNT_HI 31
+#define CBR_RG_PKT_GEN_TX_CNT_SZ 32
+#define CBR_TP_SEL_MSK 0x0000001f
+#define CBR_TP_SEL_I_MSK 0xffffffe0
+#define CBR_TP_SEL_SFT 0
+#define CBR_TP_SEL_HI 4
+#define CBR_TP_SEL_SZ 5
+#define CBR_IDEAL_IQ_EN_MSK 0x00000020
+#define CBR_IDEAL_IQ_EN_I_MSK 0xffffffdf
+#define CBR_IDEAL_IQ_EN_SFT 5
+#define CBR_IDEAL_IQ_EN_HI 5
+#define CBR_IDEAL_IQ_EN_SZ 1
+#define CBR_DATA_OUT_SEL_MSK 0x000001c0
+#define CBR_DATA_OUT_SEL_I_MSK 0xfffffe3f
+#define CBR_DATA_OUT_SEL_SFT 6
+#define CBR_DATA_OUT_SEL_HI 8
+#define CBR_DATA_OUT_SEL_SZ 3
+#define CBR_TWO_TONE_EN_MSK 0x00000200
+#define CBR_TWO_TONE_EN_I_MSK 0xfffffdff
+#define CBR_TWO_TONE_EN_SFT 9
+#define CBR_TWO_TONE_EN_HI 9
+#define CBR_TWO_TONE_EN_SZ 1
+#define CBR_FREQ_SEL_MSK 0x00ff0000
+#define CBR_FREQ_SEL_I_MSK 0xff00ffff
+#define CBR_FREQ_SEL_SFT 16
+#define CBR_FREQ_SEL_HI 23
+#define CBR_FREQ_SEL_SZ 8
+#define CBR_IQ_SCALE_MSK 0xff000000
+#define CBR_IQ_SCALE_I_MSK 0x00ffffff
+#define CBR_IQ_SCALE_SFT 24
+#define CBR_IQ_SCALE_HI 31
+#define CBR_IQ_SCALE_SZ 8
+#define CPU_QUE_POP_MSK 0x00000001
+#define CPU_QUE_POP_I_MSK 0xfffffffe
+#define CPU_QUE_POP_SFT 0
+#define CPU_QUE_POP_HI 0
+#define CPU_QUE_POP_SZ 1
+#define CPU_INT_MSK 0x00000004
+#define CPU_INT_I_MSK 0xfffffffb
+#define CPU_INT_SFT 2
+#define CPU_INT_HI 2
+#define CPU_INT_SZ 1
+#define CPU_ID_TB0_MSK 0xffffffff
+#define CPU_ID_TB0_I_MSK 0x00000000
+#define CPU_ID_TB0_SFT 0
+#define CPU_ID_TB0_HI 31
+#define CPU_ID_TB0_SZ 32
+#define CPU_ID_TB1_MSK 0xffffffff
+#define CPU_ID_TB1_I_MSK 0x00000000
+#define CPU_ID_TB1_SFT 0
+#define CPU_ID_TB1_HI 31
+#define CPU_ID_TB1_SZ 32
+#define HW_PKTID_MSK 0x000007ff
+#define HW_PKTID_I_MSK 0xfffff800
+#define HW_PKTID_SFT 0
+#define HW_PKTID_HI 10
+#define HW_PKTID_SZ 11
+#define CH0_INT_ADDR_MSK 0xffffffff
+#define CH0_INT_ADDR_I_MSK 0x00000000
+#define CH0_INT_ADDR_SFT 0
+#define CH0_INT_ADDR_HI 31
+#define CH0_INT_ADDR_SZ 32
+#define PRI_HW_PKTID_MSK 0x000007ff
+#define PRI_HW_PKTID_I_MSK 0xfffff800
+#define PRI_HW_PKTID_SFT 0
+#define PRI_HW_PKTID_HI 10
+#define PRI_HW_PKTID_SZ 11
+#define CH0_FULL_MSK 0x00000001
+#define CH0_FULL_I_MSK 0xfffffffe
+#define CH0_FULL_SFT 0
+#define CH0_FULL_HI 0
+#define CH0_FULL_SZ 1
+#define FF0_EMPTY_MSK 0x00000002
+#define FF0_EMPTY_I_MSK 0xfffffffd
+#define FF0_EMPTY_SFT 1
+#define FF0_EMPTY_HI 1
+#define FF0_EMPTY_SZ 1
+#define RLS_BUSY_MSK 0x00000200
+#define RLS_BUSY_I_MSK 0xfffffdff
+#define RLS_BUSY_SFT 9
+#define RLS_BUSY_HI 9
+#define RLS_BUSY_SZ 1
+#define RLS_COUNT_CLR_MSK 0x00000400
+#define RLS_COUNT_CLR_I_MSK 0xfffffbff
+#define RLS_COUNT_CLR_SFT 10
+#define RLS_COUNT_CLR_HI 10
+#define RLS_COUNT_CLR_SZ 1
+#define RTN_COUNT_CLR_MSK 0x00000800
+#define RTN_COUNT_CLR_I_MSK 0xfffff7ff
+#define RTN_COUNT_CLR_SFT 11
+#define RTN_COUNT_CLR_HI 11
+#define RTN_COUNT_CLR_SZ 1
+#define RLS_COUNT_MSK 0x00ff0000
+#define RLS_COUNT_I_MSK 0xff00ffff
+#define RLS_COUNT_SFT 16
+#define RLS_COUNT_HI 23
+#define RLS_COUNT_SZ 8
+#define RTN_COUNT_MSK 0xff000000
+#define RTN_COUNT_I_MSK 0x00ffffff
+#define RTN_COUNT_SFT 24
+#define RTN_COUNT_HI 31
+#define RTN_COUNT_SZ 8
+#define FF0_CNT_MSK 0x0000001f
+#define FF0_CNT_I_MSK 0xffffffe0
+#define FF0_CNT_SFT 0
+#define FF0_CNT_HI 4
+#define FF0_CNT_SZ 5
+#define FF1_CNT_MSK 0x000001e0
+#define FF1_CNT_I_MSK 0xfffffe1f
+#define FF1_CNT_SFT 5
+#define FF1_CNT_HI 8
+#define FF1_CNT_SZ 4
+#define FF3_CNT_MSK 0x00003800
+#define FF3_CNT_I_MSK 0xffffc7ff
+#define FF3_CNT_SFT 11
+#define FF3_CNT_HI 13
+#define FF3_CNT_SZ 3
+#define FF5_CNT_MSK 0x000e0000
+#define FF5_CNT_I_MSK 0xfff1ffff
+#define FF5_CNT_SFT 17
+#define FF5_CNT_HI 19
+#define FF5_CNT_SZ 3
+#define FF6_CNT_MSK 0x00700000
+#define FF6_CNT_I_MSK 0xff8fffff
+#define FF6_CNT_SFT 20
+#define FF6_CNT_HI 22
+#define FF6_CNT_SZ 3
+#define FF7_CNT_MSK 0x03800000
+#define FF7_CNT_I_MSK 0xfc7fffff
+#define FF7_CNT_SFT 23
+#define FF7_CNT_HI 25
+#define FF7_CNT_SZ 3
+#define FF8_CNT_MSK 0x1c000000
+#define FF8_CNT_I_MSK 0xe3ffffff
+#define FF8_CNT_SFT 26
+#define FF8_CNT_HI 28
+#define FF8_CNT_SZ 3
+#define FF9_CNT_MSK 0xe0000000
+#define FF9_CNT_I_MSK 0x1fffffff
+#define FF9_CNT_SFT 29
+#define FF9_CNT_HI 31
+#define FF9_CNT_SZ 3
+#define FF10_CNT_MSK 0x00000007
+#define FF10_CNT_I_MSK 0xfffffff8
+#define FF10_CNT_SFT 0
+#define FF10_CNT_HI 2
+#define FF10_CNT_SZ 3
+#define FF11_CNT_MSK 0x00000038
+#define FF11_CNT_I_MSK 0xffffffc7
+#define FF11_CNT_SFT 3
+#define FF11_CNT_HI 5
+#define FF11_CNT_SZ 3
+#define FF12_CNT_MSK 0x000001c0
+#define FF12_CNT_I_MSK 0xfffffe3f
+#define FF12_CNT_SFT 6
+#define FF12_CNT_HI 8
+#define FF12_CNT_SZ 3
+#define FF13_CNT_MSK 0x00000600
+#define FF13_CNT_I_MSK 0xfffff9ff
+#define FF13_CNT_SFT 9
+#define FF13_CNT_HI 10
+#define FF13_CNT_SZ 2
+#define FF14_CNT_MSK 0x00001800
+#define FF14_CNT_I_MSK 0xffffe7ff
+#define FF14_CNT_SFT 11
+#define FF14_CNT_HI 12
+#define FF14_CNT_SZ 2
+#define FF15_CNT_MSK 0x00006000
+#define FF15_CNT_I_MSK 0xffff9fff
+#define FF15_CNT_SFT 13
+#define FF15_CNT_HI 14
+#define FF15_CNT_SZ 2
+#define FF4_CNT_MSK 0x000f8000
+#define FF4_CNT_I_MSK 0xfff07fff
+#define FF4_CNT_SFT 15
+#define FF4_CNT_HI 19
+#define FF4_CNT_SZ 5
+#define FF2_CNT_MSK 0x00700000
+#define FF2_CNT_I_MSK 0xff8fffff
+#define FF2_CNT_SFT 20
+#define FF2_CNT_HI 22
+#define FF2_CNT_SZ 3
+#define CH1_FULL_MSK 0x00000002
+#define CH1_FULL_I_MSK 0xfffffffd
+#define CH1_FULL_SFT 1
+#define CH1_FULL_HI 1
+#define CH1_FULL_SZ 1
+#define CH2_FULL_MSK 0x00000004
+#define CH2_FULL_I_MSK 0xfffffffb
+#define CH2_FULL_SFT 2
+#define CH2_FULL_HI 2
+#define CH2_FULL_SZ 1
+#define CH3_FULL_MSK 0x00000008
+#define CH3_FULL_I_MSK 0xfffffff7
+#define CH3_FULL_SFT 3
+#define CH3_FULL_HI 3
+#define CH3_FULL_SZ 1
+#define CH4_FULL_MSK 0x00000010
+#define CH4_FULL_I_MSK 0xffffffef
+#define CH4_FULL_SFT 4
+#define CH4_FULL_HI 4
+#define CH4_FULL_SZ 1
+#define CH5_FULL_MSK 0x00000020
+#define CH5_FULL_I_MSK 0xffffffdf
+#define CH5_FULL_SFT 5
+#define CH5_FULL_HI 5
+#define CH5_FULL_SZ 1
+#define CH6_FULL_MSK 0x00000040
+#define CH6_FULL_I_MSK 0xffffffbf
+#define CH6_FULL_SFT 6
+#define CH6_FULL_HI 6
+#define CH6_FULL_SZ 1
+#define CH7_FULL_MSK 0x00000080
+#define CH7_FULL_I_MSK 0xffffff7f
+#define CH7_FULL_SFT 7
+#define CH7_FULL_HI 7
+#define CH7_FULL_SZ 1
+#define CH8_FULL_MSK 0x00000100
+#define CH8_FULL_I_MSK 0xfffffeff
+#define CH8_FULL_SFT 8
+#define CH8_FULL_HI 8
+#define CH8_FULL_SZ 1
+#define CH9_FULL_MSK 0x00000200
+#define CH9_FULL_I_MSK 0xfffffdff
+#define CH9_FULL_SFT 9
+#define CH9_FULL_HI 9
+#define CH9_FULL_SZ 1
+#define CH10_FULL_MSK 0x00000400
+#define CH10_FULL_I_MSK 0xfffffbff
+#define CH10_FULL_SFT 10
+#define CH10_FULL_HI 10
+#define CH10_FULL_SZ 1
+#define CH11_FULL_MSK 0x00000800
+#define CH11_FULL_I_MSK 0xfffff7ff
+#define CH11_FULL_SFT 11
+#define CH11_FULL_HI 11
+#define CH11_FULL_SZ 1
+#define CH12_FULL_MSK 0x00001000
+#define CH12_FULL_I_MSK 0xffffefff
+#define CH12_FULL_SFT 12
+#define CH12_FULL_HI 12
+#define CH12_FULL_SZ 1
+#define CH13_FULL_MSK 0x00002000
+#define CH13_FULL_I_MSK 0xffffdfff
+#define CH13_FULL_SFT 13
+#define CH13_FULL_HI 13
+#define CH13_FULL_SZ 1
+#define CH14_FULL_MSK 0x00004000
+#define CH14_FULL_I_MSK 0xffffbfff
+#define CH14_FULL_SFT 14
+#define CH14_FULL_HI 14
+#define CH14_FULL_SZ 1
+#define CH15_FULL_MSK 0x00008000
+#define CH15_FULL_I_MSK 0xffff7fff
+#define CH15_FULL_SFT 15
+#define CH15_FULL_HI 15
+#define CH15_FULL_SZ 1
+#define HALT_CH0_MSK 0x00000001
+#define HALT_CH0_I_MSK 0xfffffffe
+#define HALT_CH0_SFT 0
+#define HALT_CH0_HI 0
+#define HALT_CH0_SZ 1
+#define HALT_CH1_MSK 0x00000002
+#define HALT_CH1_I_MSK 0xfffffffd
+#define HALT_CH1_SFT 1
+#define HALT_CH1_HI 1
+#define HALT_CH1_SZ 1
+#define HALT_CH2_MSK 0x00000004
+#define HALT_CH2_I_MSK 0xfffffffb
+#define HALT_CH2_SFT 2
+#define HALT_CH2_HI 2
+#define HALT_CH2_SZ 1
+#define HALT_CH3_MSK 0x00000008
+#define HALT_CH3_I_MSK 0xfffffff7
+#define HALT_CH3_SFT 3
+#define HALT_CH3_HI 3
+#define HALT_CH3_SZ 1
+#define HALT_CH4_MSK 0x00000010
+#define HALT_CH4_I_MSK 0xffffffef
+#define HALT_CH4_SFT 4
+#define HALT_CH4_HI 4
+#define HALT_CH4_SZ 1
+#define HALT_CH5_MSK 0x00000020
+#define HALT_CH5_I_MSK 0xffffffdf
+#define HALT_CH5_SFT 5
+#define HALT_CH5_HI 5
+#define HALT_CH5_SZ 1
+#define HALT_CH6_MSK 0x00000040
+#define HALT_CH6_I_MSK 0xffffffbf
+#define HALT_CH6_SFT 6
+#define HALT_CH6_HI 6
+#define HALT_CH6_SZ 1
+#define HALT_CH7_MSK 0x00000080
+#define HALT_CH7_I_MSK 0xffffff7f
+#define HALT_CH7_SFT 7
+#define HALT_CH7_HI 7
+#define HALT_CH7_SZ 1
+#define HALT_CH8_MSK 0x00000100
+#define HALT_CH8_I_MSK 0xfffffeff
+#define HALT_CH8_SFT 8
+#define HALT_CH8_HI 8
+#define HALT_CH8_SZ 1
+#define HALT_CH9_MSK 0x00000200
+#define HALT_CH9_I_MSK 0xfffffdff
+#define HALT_CH9_SFT 9
+#define HALT_CH9_HI 9
+#define HALT_CH9_SZ 1
+#define HALT_CH10_MSK 0x00000400
+#define HALT_CH10_I_MSK 0xfffffbff
+#define HALT_CH10_SFT 10
+#define HALT_CH10_HI 10
+#define HALT_CH10_SZ 1
+#define HALT_CH11_MSK 0x00000800
+#define HALT_CH11_I_MSK 0xfffff7ff
+#define HALT_CH11_SFT 11
+#define HALT_CH11_HI 11
+#define HALT_CH11_SZ 1
+#define HALT_CH12_MSK 0x00001000
+#define HALT_CH12_I_MSK 0xffffefff
+#define HALT_CH12_SFT 12
+#define HALT_CH12_HI 12
+#define HALT_CH12_SZ 1
+#define HALT_CH13_MSK 0x00002000
+#define HALT_CH13_I_MSK 0xffffdfff
+#define HALT_CH13_SFT 13
+#define HALT_CH13_HI 13
+#define HALT_CH13_SZ 1
+#define HALT_CH14_MSK 0x00004000
+#define HALT_CH14_I_MSK 0xffffbfff
+#define HALT_CH14_SFT 14
+#define HALT_CH14_HI 14
+#define HALT_CH14_SZ 1
+#define HALT_CH15_MSK 0x00008000
+#define HALT_CH15_I_MSK 0xffff7fff
+#define HALT_CH15_SFT 15
+#define HALT_CH15_HI 15
+#define HALT_CH15_SZ 1
+#define STOP_MBOX_MSK 0x00010000
+#define STOP_MBOX_I_MSK 0xfffeffff
+#define STOP_MBOX_SFT 16
+#define STOP_MBOX_HI 16
+#define STOP_MBOX_SZ 1
+#define MB_ERR_AUTO_HALT_EN_MSK 0x00100000
+#define MB_ERR_AUTO_HALT_EN_I_MSK 0xffefffff
+#define MB_ERR_AUTO_HALT_EN_SFT 20
+#define MB_ERR_AUTO_HALT_EN_HI 20
+#define MB_ERR_AUTO_HALT_EN_SZ 1
+#define MB_EXCEPT_CLR_MSK 0x00200000
+#define MB_EXCEPT_CLR_I_MSK 0xffdfffff
+#define MB_EXCEPT_CLR_SFT 21
+#define MB_EXCEPT_CLR_HI 21
+#define MB_EXCEPT_CLR_SZ 1
+#define MB_EXCEPT_CASE_MSK 0xff000000
+#define MB_EXCEPT_CASE_I_MSK 0x00ffffff
+#define MB_EXCEPT_CASE_SFT 24
+#define MB_EXCEPT_CASE_HI 31
+#define MB_EXCEPT_CASE_SZ 8
+#define MB_DBG_TIME_STEP_MSK 0x0000ffff
+#define MB_DBG_TIME_STEP_I_MSK 0xffff0000
+#define MB_DBG_TIME_STEP_SFT 0
+#define MB_DBG_TIME_STEP_HI 15
+#define MB_DBG_TIME_STEP_SZ 16
+#define DBG_TYPE_MSK 0x00030000
+#define DBG_TYPE_I_MSK 0xfffcffff
+#define DBG_TYPE_SFT 16
+#define DBG_TYPE_HI 17
+#define DBG_TYPE_SZ 2
+#define MB_DBG_CLR_MSK 0x00040000
+#define MB_DBG_CLR_I_MSK 0xfffbffff
+#define MB_DBG_CLR_SFT 18
+#define MB_DBG_CLR_HI 18
+#define MB_DBG_CLR_SZ 1
+#define DBG_ALC_LOG_EN_MSK 0x00080000
+#define DBG_ALC_LOG_EN_I_MSK 0xfff7ffff
+#define DBG_ALC_LOG_EN_SFT 19
+#define DBG_ALC_LOG_EN_HI 19
+#define DBG_ALC_LOG_EN_SZ 1
+#define MB_DBG_COUNTER_EN_MSK 0x01000000
+#define MB_DBG_COUNTER_EN_I_MSK 0xfeffffff
+#define MB_DBG_COUNTER_EN_SFT 24
+#define MB_DBG_COUNTER_EN_HI 24
+#define MB_DBG_COUNTER_EN_SZ 1
+#define MB_DBG_EN_MSK 0x80000000
+#define MB_DBG_EN_I_MSK 0x7fffffff
+#define MB_DBG_EN_SFT 31
+#define MB_DBG_EN_HI 31
+#define MB_DBG_EN_SZ 1
+#define MB_DBG_RECORD_CNT_MSK 0x0000ffff
+#define MB_DBG_RECORD_CNT_I_MSK 0xffff0000
+#define MB_DBG_RECORD_CNT_SFT 0
+#define MB_DBG_RECORD_CNT_HI 15
+#define MB_DBG_RECORD_CNT_SZ 16
+#define MB_DBG_LENGTH_MSK 0xffff0000
+#define MB_DBG_LENGTH_I_MSK 0x0000ffff
+#define MB_DBG_LENGTH_SFT 16
+#define MB_DBG_LENGTH_HI 31
+#define MB_DBG_LENGTH_SZ 16
+#define MB_DBG_CFG_ADDR_MSK 0xffffffff
+#define MB_DBG_CFG_ADDR_I_MSK 0x00000000
+#define MB_DBG_CFG_ADDR_SFT 0
+#define MB_DBG_CFG_ADDR_HI 31
+#define MB_DBG_CFG_ADDR_SZ 32
+#define DBG_HWID0_WR_EN_MSK 0x00000001
+#define DBG_HWID0_WR_EN_I_MSK 0xfffffffe
+#define DBG_HWID0_WR_EN_SFT 0
+#define DBG_HWID0_WR_EN_HI 0
+#define DBG_HWID0_WR_EN_SZ 1
+#define DBG_HWID1_WR_EN_MSK 0x00000002
+#define DBG_HWID1_WR_EN_I_MSK 0xfffffffd
+#define DBG_HWID1_WR_EN_SFT 1
+#define DBG_HWID1_WR_EN_HI 1
+#define DBG_HWID1_WR_EN_SZ 1
+#define DBG_HWID2_WR_EN_MSK 0x00000004
+#define DBG_HWID2_WR_EN_I_MSK 0xfffffffb
+#define DBG_HWID2_WR_EN_SFT 2
+#define DBG_HWID2_WR_EN_HI 2
+#define DBG_HWID2_WR_EN_SZ 1
+#define DBG_HWID3_WR_EN_MSK 0x00000008
+#define DBG_HWID3_WR_EN_I_MSK 0xfffffff7
+#define DBG_HWID3_WR_EN_SFT 3
+#define DBG_HWID3_WR_EN_HI 3
+#define DBG_HWID3_WR_EN_SZ 1
+#define DBG_HWID4_WR_EN_MSK 0x00000010
+#define DBG_HWID4_WR_EN_I_MSK 0xffffffef
+#define DBG_HWID4_WR_EN_SFT 4
+#define DBG_HWID4_WR_EN_HI 4
+#define DBG_HWID4_WR_EN_SZ 1
+#define DBG_HWID5_WR_EN_MSK 0x00000020
+#define DBG_HWID5_WR_EN_I_MSK 0xffffffdf
+#define DBG_HWID5_WR_EN_SFT 5
+#define DBG_HWID5_WR_EN_HI 5
+#define DBG_HWID5_WR_EN_SZ 1
+#define DBG_HWID6_WR_EN_MSK 0x00000040
+#define DBG_HWID6_WR_EN_I_MSK 0xffffffbf
+#define DBG_HWID6_WR_EN_SFT 6
+#define DBG_HWID6_WR_EN_HI 6
+#define DBG_HWID6_WR_EN_SZ 1
+#define DBG_HWID7_WR_EN_MSK 0x00000080
+#define DBG_HWID7_WR_EN_I_MSK 0xffffff7f
+#define DBG_HWID7_WR_EN_SFT 7
+#define DBG_HWID7_WR_EN_HI 7
+#define DBG_HWID7_WR_EN_SZ 1
+#define DBG_HWID8_WR_EN_MSK 0x00000100
+#define DBG_HWID8_WR_EN_I_MSK 0xfffffeff
+#define DBG_HWID8_WR_EN_SFT 8
+#define DBG_HWID8_WR_EN_HI 8
+#define DBG_HWID8_WR_EN_SZ 1
+#define DBG_HWID9_WR_EN_MSK 0x00000200
+#define DBG_HWID9_WR_EN_I_MSK 0xfffffdff
+#define DBG_HWID9_WR_EN_SFT 9
+#define DBG_HWID9_WR_EN_HI 9
+#define DBG_HWID9_WR_EN_SZ 1
+#define DBG_HWID10_WR_EN_MSK 0x00000400
+#define DBG_HWID10_WR_EN_I_MSK 0xfffffbff
+#define DBG_HWID10_WR_EN_SFT 10
+#define DBG_HWID10_WR_EN_HI 10
+#define DBG_HWID10_WR_EN_SZ 1
+#define DBG_HWID11_WR_EN_MSK 0x00000800
+#define DBG_HWID11_WR_EN_I_MSK 0xfffff7ff
+#define DBG_HWID11_WR_EN_SFT 11
+#define DBG_HWID11_WR_EN_HI 11
+#define DBG_HWID11_WR_EN_SZ 1
+#define DBG_HWID12_WR_EN_MSK 0x00001000
+#define DBG_HWID12_WR_EN_I_MSK 0xffffefff
+#define DBG_HWID12_WR_EN_SFT 12
+#define DBG_HWID12_WR_EN_HI 12
+#define DBG_HWID12_WR_EN_SZ 1
+#define DBG_HWID13_WR_EN_MSK 0x00002000
+#define DBG_HWID13_WR_EN_I_MSK 0xffffdfff
+#define DBG_HWID13_WR_EN_SFT 13
+#define DBG_HWID13_WR_EN_HI 13
+#define DBG_HWID13_WR_EN_SZ 1
+#define DBG_HWID14_WR_EN_MSK 0x00004000
+#define DBG_HWID14_WR_EN_I_MSK 0xffffbfff
+#define DBG_HWID14_WR_EN_SFT 14
+#define DBG_HWID14_WR_EN_HI 14
+#define DBG_HWID14_WR_EN_SZ 1
+#define DBG_HWID15_WR_EN_MSK 0x00008000
+#define DBG_HWID15_WR_EN_I_MSK 0xffff7fff
+#define DBG_HWID15_WR_EN_SFT 15
+#define DBG_HWID15_WR_EN_HI 15
+#define DBG_HWID15_WR_EN_SZ 1
+#define DBG_HWID0_RD_EN_MSK 0x00010000
+#define DBG_HWID0_RD_EN_I_MSK 0xfffeffff
+#define DBG_HWID0_RD_EN_SFT 16
+#define DBG_HWID0_RD_EN_HI 16
+#define DBG_HWID0_RD_EN_SZ 1
+#define DBG_HWID1_RD_EN_MSK 0x00020000
+#define DBG_HWID1_RD_EN_I_MSK 0xfffdffff
+#define DBG_HWID1_RD_EN_SFT 17
+#define DBG_HWID1_RD_EN_HI 17
+#define DBG_HWID1_RD_EN_SZ 1
+#define DBG_HWID2_RD_EN_MSK 0x00040000
+#define DBG_HWID2_RD_EN_I_MSK 0xfffbffff
+#define DBG_HWID2_RD_EN_SFT 18
+#define DBG_HWID2_RD_EN_HI 18
+#define DBG_HWID2_RD_EN_SZ 1
+#define DBG_HWID3_RD_EN_MSK 0x00080000
+#define DBG_HWID3_RD_EN_I_MSK 0xfff7ffff
+#define DBG_HWID3_RD_EN_SFT 19
+#define DBG_HWID3_RD_EN_HI 19
+#define DBG_HWID3_RD_EN_SZ 1
+#define DBG_HWID4_RD_EN_MSK 0x00100000
+#define DBG_HWID4_RD_EN_I_MSK 0xffefffff
+#define DBG_HWID4_RD_EN_SFT 20
+#define DBG_HWID4_RD_EN_HI 20
+#define DBG_HWID4_RD_EN_SZ 1
+#define DBG_HWID5_RD_EN_MSK 0x00200000
+#define DBG_HWID5_RD_EN_I_MSK 0xffdfffff
+#define DBG_HWID5_RD_EN_SFT 21
+#define DBG_HWID5_RD_EN_HI 21
+#define DBG_HWID5_RD_EN_SZ 1
+#define DBG_HWID6_RD_EN_MSK 0x00400000
+#define DBG_HWID6_RD_EN_I_MSK 0xffbfffff
+#define DBG_HWID6_RD_EN_SFT 22
+#define DBG_HWID6_RD_EN_HI 22
+#define DBG_HWID6_RD_EN_SZ 1
+#define DBG_HWID7_RD_EN_MSK 0x00800000
+#define DBG_HWID7_RD_EN_I_MSK 0xff7fffff
+#define DBG_HWID7_RD_EN_SFT 23
+#define DBG_HWID7_RD_EN_HI 23
+#define DBG_HWID7_RD_EN_SZ 1
+#define DBG_HWID8_RD_EN_MSK 0x01000000
+#define DBG_HWID8_RD_EN_I_MSK 0xfeffffff
+#define DBG_HWID8_RD_EN_SFT 24
+#define DBG_HWID8_RD_EN_HI 24
+#define DBG_HWID8_RD_EN_SZ 1
+#define DBG_HWID9_RD_EN_MSK 0x02000000
+#define DBG_HWID9_RD_EN_I_MSK 0xfdffffff
+#define DBG_HWID9_RD_EN_SFT 25
+#define DBG_HWID9_RD_EN_HI 25
+#define DBG_HWID9_RD_EN_SZ 1
+#define DBG_HWID10_RD_EN_MSK 0x04000000
+#define DBG_HWID10_RD_EN_I_MSK 0xfbffffff
+#define DBG_HWID10_RD_EN_SFT 26
+#define DBG_HWID10_RD_EN_HI 26
+#define DBG_HWID10_RD_EN_SZ 1
+#define DBG_HWID11_RD_EN_MSK 0x08000000
+#define DBG_HWID11_RD_EN_I_MSK 0xf7ffffff
+#define DBG_HWID11_RD_EN_SFT 27
+#define DBG_HWID11_RD_EN_HI 27
+#define DBG_HWID11_RD_EN_SZ 1
+#define DBG_HWID12_RD_EN_MSK 0x10000000
+#define DBG_HWID12_RD_EN_I_MSK 0xefffffff
+#define DBG_HWID12_RD_EN_SFT 28
+#define DBG_HWID12_RD_EN_HI 28
+#define DBG_HWID12_RD_EN_SZ 1
+#define DBG_HWID13_RD_EN_MSK 0x20000000
+#define DBG_HWID13_RD_EN_I_MSK 0xdfffffff
+#define DBG_HWID13_RD_EN_SFT 29
+#define DBG_HWID13_RD_EN_HI 29
+#define DBG_HWID13_RD_EN_SZ 1
+#define DBG_HWID14_RD_EN_MSK 0x40000000
+#define DBG_HWID14_RD_EN_I_MSK 0xbfffffff
+#define DBG_HWID14_RD_EN_SFT 30
+#define DBG_HWID14_RD_EN_HI 30
+#define DBG_HWID14_RD_EN_SZ 1
+#define DBG_HWID15_RD_EN_MSK 0x80000000
+#define DBG_HWID15_RD_EN_I_MSK 0x7fffffff
+#define DBG_HWID15_RD_EN_SFT 31
+#define DBG_HWID15_RD_EN_HI 31
+#define DBG_HWID15_RD_EN_SZ 1
+#define MB_OUT_QUEUE_EN_MSK 0x00000002
+#define MB_OUT_QUEUE_EN_I_MSK 0xfffffffd
+#define MB_OUT_QUEUE_EN_SFT 1
+#define MB_OUT_QUEUE_EN_HI 1
+#define MB_OUT_QUEUE_EN_SZ 1
+#define CH0_QUEUE_FLUSH_MSK 0x00000001
+#define CH0_QUEUE_FLUSH_I_MSK 0xfffffffe
+#define CH0_QUEUE_FLUSH_SFT 0
+#define CH0_QUEUE_FLUSH_HI 0
+#define CH0_QUEUE_FLUSH_SZ 1
+#define CH1_QUEUE_FLUSH_MSK 0x00000002
+#define CH1_QUEUE_FLUSH_I_MSK 0xfffffffd
+#define CH1_QUEUE_FLUSH_SFT 1
+#define CH1_QUEUE_FLUSH_HI 1
+#define CH1_QUEUE_FLUSH_SZ 1
+#define CH2_QUEUE_FLUSH_MSK 0x00000004
+#define CH2_QUEUE_FLUSH_I_MSK 0xfffffffb
+#define CH2_QUEUE_FLUSH_SFT 2
+#define CH2_QUEUE_FLUSH_HI 2
+#define CH2_QUEUE_FLUSH_SZ 1
+#define CH3_QUEUE_FLUSH_MSK 0x00000008
+#define CH3_QUEUE_FLUSH_I_MSK 0xfffffff7
+#define CH3_QUEUE_FLUSH_SFT 3
+#define CH3_QUEUE_FLUSH_HI 3
+#define CH3_QUEUE_FLUSH_SZ 1
+#define CH4_QUEUE_FLUSH_MSK 0x00000010
+#define CH4_QUEUE_FLUSH_I_MSK 0xffffffef
+#define CH4_QUEUE_FLUSH_SFT 4
+#define CH4_QUEUE_FLUSH_HI 4
+#define CH4_QUEUE_FLUSH_SZ 1
+#define CH5_QUEUE_FLUSH_MSK 0x00000020
+#define CH5_QUEUE_FLUSH_I_MSK 0xffffffdf
+#define CH5_QUEUE_FLUSH_SFT 5
+#define CH5_QUEUE_FLUSH_HI 5
+#define CH5_QUEUE_FLUSH_SZ 1
+#define CH6_QUEUE_FLUSH_MSK 0x00000040
+#define CH6_QUEUE_FLUSH_I_MSK 0xffffffbf
+#define CH6_QUEUE_FLUSH_SFT 6
+#define CH6_QUEUE_FLUSH_HI 6
+#define CH6_QUEUE_FLUSH_SZ 1
+#define CH7_QUEUE_FLUSH_MSK 0x00000080
+#define CH7_QUEUE_FLUSH_I_MSK 0xffffff7f
+#define CH7_QUEUE_FLUSH_SFT 7
+#define CH7_QUEUE_FLUSH_HI 7
+#define CH7_QUEUE_FLUSH_SZ 1
+#define CH8_QUEUE_FLUSH_MSK 0x00000100
+#define CH8_QUEUE_FLUSH_I_MSK 0xfffffeff
+#define CH8_QUEUE_FLUSH_SFT 8
+#define CH8_QUEUE_FLUSH_HI 8
+#define CH8_QUEUE_FLUSH_SZ 1
+#define CH9_QUEUE_FLUSH_MSK 0x00000200
+#define CH9_QUEUE_FLUSH_I_MSK 0xfffffdff
+#define CH9_QUEUE_FLUSH_SFT 9
+#define CH9_QUEUE_FLUSH_HI 9
+#define CH9_QUEUE_FLUSH_SZ 1
+#define CH10_QUEUE_FLUSH_MSK 0x00000400
+#define CH10_QUEUE_FLUSH_I_MSK 0xfffffbff
+#define CH10_QUEUE_FLUSH_SFT 10
+#define CH10_QUEUE_FLUSH_HI 10
+#define CH10_QUEUE_FLUSH_SZ 1
+#define CH11_QUEUE_FLUSH_MSK 0x00000800
+#define CH11_QUEUE_FLUSH_I_MSK 0xfffff7ff
+#define CH11_QUEUE_FLUSH_SFT 11
+#define CH11_QUEUE_FLUSH_HI 11
+#define CH11_QUEUE_FLUSH_SZ 1
+#define CH12_QUEUE_FLUSH_MSK 0x00001000
+#define CH12_QUEUE_FLUSH_I_MSK 0xffffefff
+#define CH12_QUEUE_FLUSH_SFT 12
+#define CH12_QUEUE_FLUSH_HI 12
+#define CH12_QUEUE_FLUSH_SZ 1
+#define CH13_QUEUE_FLUSH_MSK 0x00002000
+#define CH13_QUEUE_FLUSH_I_MSK 0xffffdfff
+#define CH13_QUEUE_FLUSH_SFT 13
+#define CH13_QUEUE_FLUSH_HI 13
+#define CH13_QUEUE_FLUSH_SZ 1
+#define CH14_QUEUE_FLUSH_MSK 0x00004000
+#define CH14_QUEUE_FLUSH_I_MSK 0xffffbfff
+#define CH14_QUEUE_FLUSH_SFT 14
+#define CH14_QUEUE_FLUSH_HI 14
+#define CH14_QUEUE_FLUSH_SZ 1
+#define CH15_QUEUE_FLUSH_MSK 0x00008000
+#define CH15_QUEUE_FLUSH_I_MSK 0xffff7fff
+#define CH15_QUEUE_FLUSH_SFT 15
+#define CH15_QUEUE_FLUSH_HI 15
+#define CH15_QUEUE_FLUSH_SZ 1
+#define FFO0_CNT_MSK 0x0000001f
+#define FFO0_CNT_I_MSK 0xffffffe0
+#define FFO0_CNT_SFT 0
+#define FFO0_CNT_HI 4
+#define FFO0_CNT_SZ 5
+#define FFO1_CNT_MSK 0x000003e0
+#define FFO1_CNT_I_MSK 0xfffffc1f
+#define FFO1_CNT_SFT 5
+#define FFO1_CNT_HI 9
+#define FFO1_CNT_SZ 5
+#define FFO2_CNT_MSK 0x00000c00
+#define FFO2_CNT_I_MSK 0xfffff3ff
+#define FFO2_CNT_SFT 10
+#define FFO2_CNT_HI 11
+#define FFO2_CNT_SZ 2
+#define FFO3_CNT_MSK 0x000f8000
+#define FFO3_CNT_I_MSK 0xfff07fff
+#define FFO3_CNT_SFT 15
+#define FFO3_CNT_HI 19
+#define FFO3_CNT_SZ 5
+#define FFO4_CNT_MSK 0x00300000
+#define FFO4_CNT_I_MSK 0xffcfffff
+#define FFO4_CNT_SFT 20
+#define FFO4_CNT_HI 21
+#define FFO4_CNT_SZ 2
+#define FFO5_CNT_MSK 0x0e000000
+#define FFO5_CNT_I_MSK 0xf1ffffff
+#define FFO5_CNT_SFT 25
+#define FFO5_CNT_HI 27
+#define FFO5_CNT_SZ 3
+#define FFO6_CNT_MSK 0x0000000f
+#define FFO6_CNT_I_MSK 0xfffffff0
+#define FFO6_CNT_SFT 0
+#define FFO6_CNT_HI 3
+#define FFO6_CNT_SZ 4
+#define FFO7_CNT_MSK 0x000003e0
+#define FFO7_CNT_I_MSK 0xfffffc1f
+#define FFO7_CNT_SFT 5
+#define FFO7_CNT_HI 9
+#define FFO7_CNT_SZ 5
+#define FFO8_CNT_MSK 0x00007c00
+#define FFO8_CNT_I_MSK 0xffff83ff
+#define FFO8_CNT_SFT 10
+#define FFO8_CNT_HI 14
+#define FFO8_CNT_SZ 5
+#define FFO9_CNT_MSK 0x000f8000
+#define FFO9_CNT_I_MSK 0xfff07fff
+#define FFO9_CNT_SFT 15
+#define FFO9_CNT_HI 19
+#define FFO9_CNT_SZ 5
+#define FFO10_CNT_MSK 0x00f00000
+#define FFO10_CNT_I_MSK 0xff0fffff
+#define FFO10_CNT_SFT 20
+#define FFO10_CNT_HI 23
+#define FFO10_CNT_SZ 4
+#define FFO11_CNT_MSK 0x3e000000
+#define FFO11_CNT_I_MSK 0xc1ffffff
+#define FFO11_CNT_SFT 25
+#define FFO11_CNT_HI 29
+#define FFO11_CNT_SZ 5
+#define FFO12_CNT_MSK 0x00000007
+#define FFO12_CNT_I_MSK 0xfffffff8
+#define FFO12_CNT_SFT 0
+#define FFO12_CNT_HI 2
+#define FFO12_CNT_SZ 3
+#define FFO13_CNT_MSK 0x00000060
+#define FFO13_CNT_I_MSK 0xffffff9f
+#define FFO13_CNT_SFT 5
+#define FFO13_CNT_HI 6
+#define FFO13_CNT_SZ 2
+#define FFO14_CNT_MSK 0x00000c00
+#define FFO14_CNT_I_MSK 0xfffff3ff
+#define FFO14_CNT_SFT 10
+#define FFO14_CNT_HI 11
+#define FFO14_CNT_SZ 2
+#define FFO15_CNT_MSK 0x001f8000
+#define FFO15_CNT_I_MSK 0xffe07fff
+#define FFO15_CNT_SFT 15
+#define FFO15_CNT_HI 20
+#define FFO15_CNT_SZ 6
+#define CH0_FFO_FULL_MSK 0x00000001
+#define CH0_FFO_FULL_I_MSK 0xfffffffe
+#define CH0_FFO_FULL_SFT 0
+#define CH0_FFO_FULL_HI 0
+#define CH0_FFO_FULL_SZ 1
+#define CH1_FFO_FULL_MSK 0x00000002
+#define CH1_FFO_FULL_I_MSK 0xfffffffd
+#define CH1_FFO_FULL_SFT 1
+#define CH1_FFO_FULL_HI 1
+#define CH1_FFO_FULL_SZ 1
+#define CH2_FFO_FULL_MSK 0x00000004
+#define CH2_FFO_FULL_I_MSK 0xfffffffb
+#define CH2_FFO_FULL_SFT 2
+#define CH2_FFO_FULL_HI 2
+#define CH2_FFO_FULL_SZ 1
+#define CH3_FFO_FULL_MSK 0x00000008
+#define CH3_FFO_FULL_I_MSK 0xfffffff7
+#define CH3_FFO_FULL_SFT 3
+#define CH3_FFO_FULL_HI 3
+#define CH3_FFO_FULL_SZ 1
+#define CH4_FFO_FULL_MSK 0x00000010
+#define CH4_FFO_FULL_I_MSK 0xffffffef
+#define CH4_FFO_FULL_SFT 4
+#define CH4_FFO_FULL_HI 4
+#define CH4_FFO_FULL_SZ 1
+#define CH5_FFO_FULL_MSK 0x00000020
+#define CH5_FFO_FULL_I_MSK 0xffffffdf
+#define CH5_FFO_FULL_SFT 5
+#define CH5_FFO_FULL_HI 5
+#define CH5_FFO_FULL_SZ 1
+#define CH6_FFO_FULL_MSK 0x00000040
+#define CH6_FFO_FULL_I_MSK 0xffffffbf
+#define CH6_FFO_FULL_SFT 6
+#define CH6_FFO_FULL_HI 6
+#define CH6_FFO_FULL_SZ 1
+#define CH7_FFO_FULL_MSK 0x00000080
+#define CH7_FFO_FULL_I_MSK 0xffffff7f
+#define CH7_FFO_FULL_SFT 7
+#define CH7_FFO_FULL_HI 7
+#define CH7_FFO_FULL_SZ 1
+#define CH8_FFO_FULL_MSK 0x00000100
+#define CH8_FFO_FULL_I_MSK 0xfffffeff
+#define CH8_FFO_FULL_SFT 8
+#define CH8_FFO_FULL_HI 8
+#define CH8_FFO_FULL_SZ 1
+#define CH9_FFO_FULL_MSK 0x00000200
+#define CH9_FFO_FULL_I_MSK 0xfffffdff
+#define CH9_FFO_FULL_SFT 9
+#define CH9_FFO_FULL_HI 9
+#define CH9_FFO_FULL_SZ 1
+#define CH10_FFO_FULL_MSK 0x00000400
+#define CH10_FFO_FULL_I_MSK 0xfffffbff
+#define CH10_FFO_FULL_SFT 10
+#define CH10_FFO_FULL_HI 10
+#define CH10_FFO_FULL_SZ 1
+#define CH11_FFO_FULL_MSK 0x00000800
+#define CH11_FFO_FULL_I_MSK 0xfffff7ff
+#define CH11_FFO_FULL_SFT 11
+#define CH11_FFO_FULL_HI 11
+#define CH11_FFO_FULL_SZ 1
+#define CH12_FFO_FULL_MSK 0x00001000
+#define CH12_FFO_FULL_I_MSK 0xffffefff
+#define CH12_FFO_FULL_SFT 12
+#define CH12_FFO_FULL_HI 12
+#define CH12_FFO_FULL_SZ 1
+#define CH13_FFO_FULL_MSK 0x00002000
+#define CH13_FFO_FULL_I_MSK 0xffffdfff
+#define CH13_FFO_FULL_SFT 13
+#define CH13_FFO_FULL_HI 13
+#define CH13_FFO_FULL_SZ 1
+#define CH14_FFO_FULL_MSK 0x00004000
+#define CH14_FFO_FULL_I_MSK 0xffffbfff
+#define CH14_FFO_FULL_SFT 14
+#define CH14_FFO_FULL_HI 14
+#define CH14_FFO_FULL_SZ 1
+#define CH15_FFO_FULL_MSK 0x00008000
+#define CH15_FFO_FULL_I_MSK 0xffff7fff
+#define CH15_FFO_FULL_SFT 15
+#define CH15_FFO_FULL_HI 15
+#define CH15_FFO_FULL_SZ 1
+#define CH0_LOWTHOLD_INT_MSK 0x00000001
+#define CH0_LOWTHOLD_INT_I_MSK 0xfffffffe
+#define CH0_LOWTHOLD_INT_SFT 0
+#define CH0_LOWTHOLD_INT_HI 0
+#define CH0_LOWTHOLD_INT_SZ 1
+#define CH1_LOWTHOLD_INT_MSK 0x00000002
+#define CH1_LOWTHOLD_INT_I_MSK 0xfffffffd
+#define CH1_LOWTHOLD_INT_SFT 1
+#define CH1_LOWTHOLD_INT_HI 1
+#define CH1_LOWTHOLD_INT_SZ 1
+#define CH2_LOWTHOLD_INT_MSK 0x00000004
+#define CH2_LOWTHOLD_INT_I_MSK 0xfffffffb
+#define CH2_LOWTHOLD_INT_SFT 2
+#define CH2_LOWTHOLD_INT_HI 2
+#define CH2_LOWTHOLD_INT_SZ 1
+#define CH3_LOWTHOLD_INT_MSK 0x00000008
+#define CH3_LOWTHOLD_INT_I_MSK 0xfffffff7
+#define CH3_LOWTHOLD_INT_SFT 3
+#define CH3_LOWTHOLD_INT_HI 3
+#define CH3_LOWTHOLD_INT_SZ 1
+#define CH4_LOWTHOLD_INT_MSK 0x00000010
+#define CH4_LOWTHOLD_INT_I_MSK 0xffffffef
+#define CH4_LOWTHOLD_INT_SFT 4
+#define CH4_LOWTHOLD_INT_HI 4
+#define CH4_LOWTHOLD_INT_SZ 1
+#define CH5_LOWTHOLD_INT_MSK 0x00000020
+#define CH5_LOWTHOLD_INT_I_MSK 0xffffffdf
+#define CH5_LOWTHOLD_INT_SFT 5
+#define CH5_LOWTHOLD_INT_HI 5
+#define CH5_LOWTHOLD_INT_SZ 1
+#define CH6_LOWTHOLD_INT_MSK 0x00000040
+#define CH6_LOWTHOLD_INT_I_MSK 0xffffffbf
+#define CH6_LOWTHOLD_INT_SFT 6
+#define CH6_LOWTHOLD_INT_HI 6
+#define CH6_LOWTHOLD_INT_SZ 1
+#define CH7_LOWTHOLD_INT_MSK 0x00000080
+#define CH7_LOWTHOLD_INT_I_MSK 0xffffff7f
+#define CH7_LOWTHOLD_INT_SFT 7
+#define CH7_LOWTHOLD_INT_HI 7
+#define CH7_LOWTHOLD_INT_SZ 1
+#define CH8_LOWTHOLD_INT_MSK 0x00000100
+#define CH8_LOWTHOLD_INT_I_MSK 0xfffffeff
+#define CH8_LOWTHOLD_INT_SFT 8
+#define CH8_LOWTHOLD_INT_HI 8
+#define CH8_LOWTHOLD_INT_SZ 1
+#define CH9_LOWTHOLD_INT_MSK 0x00000200
+#define CH9_LOWTHOLD_INT_I_MSK 0xfffffdff
+#define CH9_LOWTHOLD_INT_SFT 9
+#define CH9_LOWTHOLD_INT_HI 9
+#define CH9_LOWTHOLD_INT_SZ 1
+#define CH10_LOWTHOLD_INT_MSK 0x00000400
+#define CH10_LOWTHOLD_INT_I_MSK 0xfffffbff
+#define CH10_LOWTHOLD_INT_SFT 10
+#define CH10_LOWTHOLD_INT_HI 10
+#define CH10_LOWTHOLD_INT_SZ 1
+#define CH11_LOWTHOLD_INT_MSK 0x00000800
+#define CH11_LOWTHOLD_INT_I_MSK 0xfffff7ff
+#define CH11_LOWTHOLD_INT_SFT 11
+#define CH11_LOWTHOLD_INT_HI 11
+#define CH11_LOWTHOLD_INT_SZ 1
+#define CH12_LOWTHOLD_INT_MSK 0x00001000
+#define CH12_LOWTHOLD_INT_I_MSK 0xffffefff
+#define CH12_LOWTHOLD_INT_SFT 12
+#define CH12_LOWTHOLD_INT_HI 12
+#define CH12_LOWTHOLD_INT_SZ 1
+#define CH13_LOWTHOLD_INT_MSK 0x00002000
+#define CH13_LOWTHOLD_INT_I_MSK 0xffffdfff
+#define CH13_LOWTHOLD_INT_SFT 13
+#define CH13_LOWTHOLD_INT_HI 13
+#define CH13_LOWTHOLD_INT_SZ 1
+#define CH14_LOWTHOLD_INT_MSK 0x00004000
+#define CH14_LOWTHOLD_INT_I_MSK 0xffffbfff
+#define CH14_LOWTHOLD_INT_SFT 14
+#define CH14_LOWTHOLD_INT_HI 14
+#define CH14_LOWTHOLD_INT_SZ 1
+#define CH15_LOWTHOLD_INT_MSK 0x00008000
+#define CH15_LOWTHOLD_INT_I_MSK 0xffff7fff
+#define CH15_LOWTHOLD_INT_SFT 15
+#define CH15_LOWTHOLD_INT_HI 15
+#define CH15_LOWTHOLD_INT_SZ 1
+#define MB_LOW_THOLD_EN_MSK 0x80000000
+#define MB_LOW_THOLD_EN_I_MSK 0x7fffffff
+#define MB_LOW_THOLD_EN_SFT 31
+#define MB_LOW_THOLD_EN_HI 31
+#define MB_LOW_THOLD_EN_SZ 1
+#define CH0_LOWTHOLD_MSK 0x0000001f
+#define CH0_LOWTHOLD_I_MSK 0xffffffe0
+#define CH0_LOWTHOLD_SFT 0
+#define CH0_LOWTHOLD_HI 4
+#define CH0_LOWTHOLD_SZ 5
+#define CH1_LOWTHOLD_MSK 0x00001f00
+#define CH1_LOWTHOLD_I_MSK 0xffffe0ff
+#define CH1_LOWTHOLD_SFT 8
+#define CH1_LOWTHOLD_HI 12
+#define CH1_LOWTHOLD_SZ 5
+#define CH2_LOWTHOLD_MSK 0x001f0000
+#define CH2_LOWTHOLD_I_MSK 0xffe0ffff
+#define CH2_LOWTHOLD_SFT 16
+#define CH2_LOWTHOLD_HI 20
+#define CH2_LOWTHOLD_SZ 5
+#define CH3_LOWTHOLD_MSK 0x1f000000
+#define CH3_LOWTHOLD_I_MSK 0xe0ffffff
+#define CH3_LOWTHOLD_SFT 24
+#define CH3_LOWTHOLD_HI 28
+#define CH3_LOWTHOLD_SZ 5
+#define CH4_LOWTHOLD_MSK 0x0000001f
+#define CH4_LOWTHOLD_I_MSK 0xffffffe0
+#define CH4_LOWTHOLD_SFT 0
+#define CH4_LOWTHOLD_HI 4
+#define CH4_LOWTHOLD_SZ 5
+#define CH5_LOWTHOLD_MSK 0x00001f00
+#define CH5_LOWTHOLD_I_MSK 0xffffe0ff
+#define CH5_LOWTHOLD_SFT 8
+#define CH5_LOWTHOLD_HI 12
+#define CH5_LOWTHOLD_SZ 5
+#define CH6_LOWTHOLD_MSK 0x001f0000
+#define CH6_LOWTHOLD_I_MSK 0xffe0ffff
+#define CH6_LOWTHOLD_SFT 16
+#define CH6_LOWTHOLD_HI 20
+#define CH6_LOWTHOLD_SZ 5
+#define CH7_LOWTHOLD_MSK 0x1f000000
+#define CH7_LOWTHOLD_I_MSK 0xe0ffffff
+#define CH7_LOWTHOLD_SFT 24
+#define CH7_LOWTHOLD_HI 28
+#define CH7_LOWTHOLD_SZ 5
+#define CH8_LOWTHOLD_MSK 0x0000001f
+#define CH8_LOWTHOLD_I_MSK 0xffffffe0
+#define CH8_LOWTHOLD_SFT 0
+#define CH8_LOWTHOLD_HI 4
+#define CH8_LOWTHOLD_SZ 5
+#define CH9_LOWTHOLD_MSK 0x00001f00
+#define CH9_LOWTHOLD_I_MSK 0xffffe0ff
+#define CH9_LOWTHOLD_SFT 8
+#define CH9_LOWTHOLD_HI 12
+#define CH9_LOWTHOLD_SZ 5
+#define CH10_LOWTHOLD_MSK 0x001f0000
+#define CH10_LOWTHOLD_I_MSK 0xffe0ffff
+#define CH10_LOWTHOLD_SFT 16
+#define CH10_LOWTHOLD_HI 20
+#define CH10_LOWTHOLD_SZ 5
+#define CH11_LOWTHOLD_MSK 0x1f000000
+#define CH11_LOWTHOLD_I_MSK 0xe0ffffff
+#define CH11_LOWTHOLD_SFT 24
+#define CH11_LOWTHOLD_HI 28
+#define CH11_LOWTHOLD_SZ 5
+#define CH12_LOWTHOLD_MSK 0x0000001f
+#define CH12_LOWTHOLD_I_MSK 0xffffffe0
+#define CH12_LOWTHOLD_SFT 0
+#define CH12_LOWTHOLD_HI 4
+#define CH12_LOWTHOLD_SZ 5
+#define CH13_LOWTHOLD_MSK 0x00001f00
+#define CH13_LOWTHOLD_I_MSK 0xffffe0ff
+#define CH13_LOWTHOLD_SFT 8
+#define CH13_LOWTHOLD_HI 12
+#define CH13_LOWTHOLD_SZ 5
+#define CH14_LOWTHOLD_MSK 0x001f0000
+#define CH14_LOWTHOLD_I_MSK 0xffe0ffff
+#define CH14_LOWTHOLD_SFT 16
+#define CH14_LOWTHOLD_HI 20
+#define CH14_LOWTHOLD_SZ 5
+#define CH15_LOWTHOLD_MSK 0x1f000000
+#define CH15_LOWTHOLD_I_MSK 0xe0ffffff
+#define CH15_LOWTHOLD_SFT 24
+#define CH15_LOWTHOLD_HI 28
+#define CH15_LOWTHOLD_SZ 5
+#define TRASH_TIMEOUT_EN_MSK 0x00000001
+#define TRASH_TIMEOUT_EN_I_MSK 0xfffffffe
+#define TRASH_TIMEOUT_EN_SFT 0
+#define TRASH_TIMEOUT_EN_HI 0
+#define TRASH_TIMEOUT_EN_SZ 1
+#define TRASH_CAN_INT_MSK 0x00000002
+#define TRASH_CAN_INT_I_MSK 0xfffffffd
+#define TRASH_CAN_INT_SFT 1
+#define TRASH_CAN_INT_HI 1
+#define TRASH_CAN_INT_SZ 1
+#define TRASH_INT_ID_MSK 0x000007f0
+#define TRASH_INT_ID_I_MSK 0xfffff80f
+#define TRASH_INT_ID_SFT 4
+#define TRASH_INT_ID_HI 10
+#define TRASH_INT_ID_SZ 7
+#define TRASH_TIMEOUT_MSK 0x03ff0000
+#define TRASH_TIMEOUT_I_MSK 0xfc00ffff
+#define TRASH_TIMEOUT_SFT 16
+#define TRASH_TIMEOUT_HI 25
+#define TRASH_TIMEOUT_SZ 10
+#define CH0_WRFF_FLUSH_MSK 0x00000001
+#define CH0_WRFF_FLUSH_I_MSK 0xfffffffe
+#define CH0_WRFF_FLUSH_SFT 0
+#define CH0_WRFF_FLUSH_HI 0
+#define CH0_WRFF_FLUSH_SZ 1
+#define CH1_WRFF_FLUSH_MSK 0x00000002
+#define CH1_WRFF_FLUSH_I_MSK 0xfffffffd
+#define CH1_WRFF_FLUSH_SFT 1
+#define CH1_WRFF_FLUSH_HI 1
+#define CH1_WRFF_FLUSH_SZ 1
+#define CH2_WRFF_FLUSH_MSK 0x00000004
+#define CH2_WRFF_FLUSH_I_MSK 0xfffffffb
+#define CH2_WRFF_FLUSH_SFT 2
+#define CH2_WRFF_FLUSH_HI 2
+#define CH2_WRFF_FLUSH_SZ 1
+#define CH3_WRFF_FLUSH_MSK 0x00000008
+#define CH3_WRFF_FLUSH_I_MSK 0xfffffff7
+#define CH3_WRFF_FLUSH_SFT 3
+#define CH3_WRFF_FLUSH_HI 3
+#define CH3_WRFF_FLUSH_SZ 1
+#define CH4_WRFF_FLUSH_MSK 0x00000010
+#define CH4_WRFF_FLUSH_I_MSK 0xffffffef
+#define CH4_WRFF_FLUSH_SFT 4
+#define CH4_WRFF_FLUSH_HI 4
+#define CH4_WRFF_FLUSH_SZ 1
+#define CH5_WRFF_FLUSH_MSK 0x00000020
+#define CH5_WRFF_FLUSH_I_MSK 0xffffffdf
+#define CH5_WRFF_FLUSH_SFT 5
+#define CH5_WRFF_FLUSH_HI 5
+#define CH5_WRFF_FLUSH_SZ 1
+#define CH6_WRFF_FLUSH_MSK 0x00000040
+#define CH6_WRFF_FLUSH_I_MSK 0xffffffbf
+#define CH6_WRFF_FLUSH_SFT 6
+#define CH6_WRFF_FLUSH_HI 6
+#define CH6_WRFF_FLUSH_SZ 1
+#define CH7_WRFF_FLUSH_MSK 0x00000080
+#define CH7_WRFF_FLUSH_I_MSK 0xffffff7f
+#define CH7_WRFF_FLUSH_SFT 7
+#define CH7_WRFF_FLUSH_HI 7
+#define CH7_WRFF_FLUSH_SZ 1
+#define CH8_WRFF_FLUSH_MSK 0x00000100
+#define CH8_WRFF_FLUSH_I_MSK 0xfffffeff
+#define CH8_WRFF_FLUSH_SFT 8
+#define CH8_WRFF_FLUSH_HI 8
+#define CH8_WRFF_FLUSH_SZ 1
+#define CH9_WRFF_FLUSH_MSK 0x00000200
+#define CH9_WRFF_FLUSH_I_MSK 0xfffffdff
+#define CH9_WRFF_FLUSH_SFT 9
+#define CH9_WRFF_FLUSH_HI 9
+#define CH9_WRFF_FLUSH_SZ 1
+#define CH10_WRFF_FLUSH_MSK 0x00000400
+#define CH10_WRFF_FLUSH_I_MSK 0xfffffbff
+#define CH10_WRFF_FLUSH_SFT 10
+#define CH10_WRFF_FLUSH_HI 10
+#define CH10_WRFF_FLUSH_SZ 1
+#define CH11_WRFF_FLUSH_MSK 0x00000800
+#define CH11_WRFF_FLUSH_I_MSK 0xfffff7ff
+#define CH11_WRFF_FLUSH_SFT 11
+#define CH11_WRFF_FLUSH_HI 11
+#define CH11_WRFF_FLUSH_SZ 1
+#define CH12_WRFF_FLUSH_MSK 0x00001000
+#define CH12_WRFF_FLUSH_I_MSK 0xffffefff
+#define CH12_WRFF_FLUSH_SFT 12
+#define CH12_WRFF_FLUSH_HI 12
+#define CH12_WRFF_FLUSH_SZ 1
+#define CH13_WRFF_FLUSH_MSK 0x00002000
+#define CH13_WRFF_FLUSH_I_MSK 0xffffdfff
+#define CH13_WRFF_FLUSH_SFT 13
+#define CH13_WRFF_FLUSH_HI 13
+#define CH13_WRFF_FLUSH_SZ 1
+#define CH14_WRFF_FLUSH_MSK 0x00004000
+#define CH14_WRFF_FLUSH_I_MSK 0xffffbfff
+#define CH14_WRFF_FLUSH_SFT 14
+#define CH14_WRFF_FLUSH_HI 14
+#define CH14_WRFF_FLUSH_SZ 1
+#define CPU_ID_TB2_MSK 0xffffffff
+#define CPU_ID_TB2_I_MSK 0x00000000
+#define CPU_ID_TB2_SFT 0
+#define CPU_ID_TB2_HI 31
+#define CPU_ID_TB2_SZ 32
+#define CPU_ID_TB3_MSK 0xffffffff
+#define CPU_ID_TB3_I_MSK 0x00000000
+#define CPU_ID_TB3_SFT 0
+#define CPU_ID_TB3_HI 31
+#define CPU_ID_TB3_SZ 32
+#define IQ_LOG_EN_MSK 0x00000001
+#define IQ_LOG_EN_I_MSK 0xfffffffe
+#define IQ_LOG_EN_SFT 0
+#define IQ_LOG_EN_HI 0
+#define IQ_LOG_EN_SZ 1
+#define IQ_LOG_STOP_MODE_MSK 0x00000001
+#define IQ_LOG_STOP_MODE_I_MSK 0xfffffffe
+#define IQ_LOG_STOP_MODE_SFT 0
+#define IQ_LOG_STOP_MODE_HI 0
+#define IQ_LOG_STOP_MODE_SZ 1
+#define GPIO_STOP_EN_MSK 0x00000010
+#define GPIO_STOP_EN_I_MSK 0xffffffef
+#define GPIO_STOP_EN_SFT 4
+#define GPIO_STOP_EN_HI 4
+#define GPIO_STOP_EN_SZ 1
+#define GPIO_STOP_POL_MSK 0x00000020
+#define GPIO_STOP_POL_I_MSK 0xffffffdf
+#define GPIO_STOP_POL_SFT 5
+#define GPIO_STOP_POL_HI 5
+#define GPIO_STOP_POL_SZ 1
+#define IQ_LOG_TIMER_MSK 0xffff0000
+#define IQ_LOG_TIMER_I_MSK 0x0000ffff
+#define IQ_LOG_TIMER_SFT 16
+#define IQ_LOG_TIMER_HI 31
+#define IQ_LOG_TIMER_SZ 16
+#define IQ_LOG_LEN_MSK 0x0000ffff
+#define IQ_LOG_LEN_I_MSK 0xffff0000
+#define IQ_LOG_LEN_SFT 0
+#define IQ_LOG_LEN_HI 15
+#define IQ_LOG_LEN_SZ 16
+#define IQ_LOG_TAIL_ADR_MSK 0x0000ffff
+#define IQ_LOG_TAIL_ADR_I_MSK 0xffff0000
+#define IQ_LOG_TAIL_ADR_SFT 0
+#define IQ_LOG_TAIL_ADR_HI 15
+#define IQ_LOG_TAIL_ADR_SZ 16
+#define ALC_LENG_MSK 0x0003ffff
+#define ALC_LENG_I_MSK 0xfffc0000
+#define ALC_LENG_SFT 0
+#define ALC_LENG_HI 17
+#define ALC_LENG_SZ 18
+#define CH0_DYN_PRI_MSK 0x00300000
+#define CH0_DYN_PRI_I_MSK 0xffcfffff
+#define CH0_DYN_PRI_SFT 20
+#define CH0_DYN_PRI_HI 21
+#define CH0_DYN_PRI_SZ 2
+#define MCU_PKTID_MSK 0xffffffff
+#define MCU_PKTID_I_MSK 0x00000000
+#define MCU_PKTID_SFT 0
+#define MCU_PKTID_HI 31
+#define MCU_PKTID_SZ 32
+#define CH0_STA_PRI_MSK 0x00000003
+#define CH0_STA_PRI_I_MSK 0xfffffffc
+#define CH0_STA_PRI_SFT 0
+#define CH0_STA_PRI_HI 1
+#define CH0_STA_PRI_SZ 2
+#define CH1_STA_PRI_MSK 0x00000030
+#define CH1_STA_PRI_I_MSK 0xffffffcf
+#define CH1_STA_PRI_SFT 4
+#define CH1_STA_PRI_HI 5
+#define CH1_STA_PRI_SZ 2
+#define CH2_STA_PRI_MSK 0x00000300
+#define CH2_STA_PRI_I_MSK 0xfffffcff
+#define CH2_STA_PRI_SFT 8
+#define CH2_STA_PRI_HI 9
+#define CH2_STA_PRI_SZ 2
+#define CH3_STA_PRI_MSK 0x00003000
+#define CH3_STA_PRI_I_MSK 0xffffcfff
+#define CH3_STA_PRI_SFT 12
+#define CH3_STA_PRI_HI 13
+#define CH3_STA_PRI_SZ 2
+#define ID_TB0_MSK 0xffffffff
+#define ID_TB0_I_MSK 0x00000000
+#define ID_TB0_SFT 0
+#define ID_TB0_HI 31
+#define ID_TB0_SZ 32
+#define ID_TB1_MSK 0xffffffff
+#define ID_TB1_I_MSK 0x00000000
+#define ID_TB1_SFT 0
+#define ID_TB1_HI 31
+#define ID_TB1_SZ 32
+#define ID_MNG_HALT_MSK 0x00000010
+#define ID_MNG_HALT_I_MSK 0xffffffef
+#define ID_MNG_HALT_SFT 4
+#define ID_MNG_HALT_HI 4
+#define ID_MNG_HALT_SZ 1
+#define ID_MNG_ERR_HALT_EN_MSK 0x00000020
+#define ID_MNG_ERR_HALT_EN_I_MSK 0xffffffdf
+#define ID_MNG_ERR_HALT_EN_SFT 5
+#define ID_MNG_ERR_HALT_EN_HI 5
+#define ID_MNG_ERR_HALT_EN_SZ 1
+#define ID_EXCEPT_FLG_CLR_MSK 0x00000040
+#define ID_EXCEPT_FLG_CLR_I_MSK 0xffffffbf
+#define ID_EXCEPT_FLG_CLR_SFT 6
+#define ID_EXCEPT_FLG_CLR_HI 6
+#define ID_EXCEPT_FLG_CLR_SZ 1
+#define ID_EXCEPT_FLG_MSK 0x00000080
+#define ID_EXCEPT_FLG_I_MSK 0xffffff7f
+#define ID_EXCEPT_FLG_SFT 7
+#define ID_EXCEPT_FLG_HI 7
+#define ID_EXCEPT_FLG_SZ 1
+#define ID_FULL_MSK 0x00000001
+#define ID_FULL_I_MSK 0xfffffffe
+#define ID_FULL_SFT 0
+#define ID_FULL_HI 0
+#define ID_FULL_SZ 1
+#define ID_MNG_BUSY_MSK 0x00000002
+#define ID_MNG_BUSY_I_MSK 0xfffffffd
+#define ID_MNG_BUSY_SFT 1
+#define ID_MNG_BUSY_HI 1
+#define ID_MNG_BUSY_SZ 1
+#define REQ_LOCK_MSK 0x00000004
+#define REQ_LOCK_I_MSK 0xfffffffb
+#define REQ_LOCK_SFT 2
+#define REQ_LOCK_HI 2
+#define REQ_LOCK_SZ 1
+#define CH0_REQ_LOCK_MSK 0x00000010
+#define CH0_REQ_LOCK_I_MSK 0xffffffef
+#define CH0_REQ_LOCK_SFT 4
+#define CH0_REQ_LOCK_HI 4
+#define CH0_REQ_LOCK_SZ 1
+#define CH1_REQ_LOCK_MSK 0x00000020
+#define CH1_REQ_LOCK_I_MSK 0xffffffdf
+#define CH1_REQ_LOCK_SFT 5
+#define CH1_REQ_LOCK_HI 5
+#define CH1_REQ_LOCK_SZ 1
+#define CH2_REQ_LOCK_MSK 0x00000040
+#define CH2_REQ_LOCK_I_MSK 0xffffffbf
+#define CH2_REQ_LOCK_SFT 6
+#define CH2_REQ_LOCK_HI 6
+#define CH2_REQ_LOCK_SZ 1
+#define CH3_REQ_LOCK_MSK 0x00000080
+#define CH3_REQ_LOCK_I_MSK 0xffffff7f
+#define CH3_REQ_LOCK_SFT 7
+#define CH3_REQ_LOCK_HI 7
+#define CH3_REQ_LOCK_SZ 1
+#define REQ_LOCK_INT_EN_MSK 0x00000100
+#define REQ_LOCK_INT_EN_I_MSK 0xfffffeff
+#define REQ_LOCK_INT_EN_SFT 8
+#define REQ_LOCK_INT_EN_HI 8
+#define REQ_LOCK_INT_EN_SZ 1
+#define REQ_LOCK_INT_MSK 0x00000200
+#define REQ_LOCK_INT_I_MSK 0xfffffdff
+#define REQ_LOCK_INT_SFT 9
+#define REQ_LOCK_INT_HI 9
+#define REQ_LOCK_INT_SZ 1
+#define MCU_ALC_READY_MSK 0x00000001
+#define MCU_ALC_READY_I_MSK 0xfffffffe
+#define MCU_ALC_READY_SFT 0
+#define MCU_ALC_READY_HI 0
+#define MCU_ALC_READY_SZ 1
+#define ALC_FAIL_MSK 0x00000002
+#define ALC_FAIL_I_MSK 0xfffffffd
+#define ALC_FAIL_SFT 1
+#define ALC_FAIL_HI 1
+#define ALC_FAIL_SZ 1
+#define ALC_BUSY_MSK 0x00000004
+#define ALC_BUSY_I_MSK 0xfffffffb
+#define ALC_BUSY_SFT 2
+#define ALC_BUSY_HI 2
+#define ALC_BUSY_SZ 1
+#define CH0_NVLD_MSK 0x00000010
+#define CH0_NVLD_I_MSK 0xffffffef
+#define CH0_NVLD_SFT 4
+#define CH0_NVLD_HI 4
+#define CH0_NVLD_SZ 1
+#define CH1_NVLD_MSK 0x00000020
+#define CH1_NVLD_I_MSK 0xffffffdf
+#define CH1_NVLD_SFT 5
+#define CH1_NVLD_HI 5
+#define CH1_NVLD_SZ 1
+#define CH2_NVLD_MSK 0x00000040
+#define CH2_NVLD_I_MSK 0xffffffbf
+#define CH2_NVLD_SFT 6
+#define CH2_NVLD_HI 6
+#define CH2_NVLD_SZ 1
+#define CH3_NVLD_MSK 0x00000080
+#define CH3_NVLD_I_MSK 0xffffff7f
+#define CH3_NVLD_SFT 7
+#define CH3_NVLD_HI 7
+#define CH3_NVLD_SZ 1
+#define ALC_INT_ID_MSK 0x00007f00
+#define ALC_INT_ID_I_MSK 0xffff80ff
+#define ALC_INT_ID_SFT 8
+#define ALC_INT_ID_HI 14
+#define ALC_INT_ID_SZ 7
+#define ALC_TIMEOUT_MSK 0x03ff0000
+#define ALC_TIMEOUT_I_MSK 0xfc00ffff
+#define ALC_TIMEOUT_SFT 16
+#define ALC_TIMEOUT_HI 25
+#define ALC_TIMEOUT_SZ 10
+#define ALC_TIMEOUT_INT_EN_MSK 0x40000000
+#define ALC_TIMEOUT_INT_EN_I_MSK 0xbfffffff
+#define ALC_TIMEOUT_INT_EN_SFT 30
+#define ALC_TIMEOUT_INT_EN_HI 30
+#define ALC_TIMEOUT_INT_EN_SZ 1
+#define ALC_TIMEOUT_INT_MSK 0x80000000
+#define ALC_TIMEOUT_INT_I_MSK 0x7fffffff
+#define ALC_TIMEOUT_INT_SFT 31
+#define ALC_TIMEOUT_INT_HI 31
+#define ALC_TIMEOUT_INT_SZ 1
+#define TX_ID_COUNT_MSK 0x000000ff
+#define TX_ID_COUNT_I_MSK 0xffffff00
+#define TX_ID_COUNT_SFT 0
+#define TX_ID_COUNT_HI 7
+#define TX_ID_COUNT_SZ 8
+#define RX_ID_COUNT_MSK 0x0000ff00
+#define RX_ID_COUNT_I_MSK 0xffff00ff
+#define RX_ID_COUNT_SFT 8
+#define RX_ID_COUNT_HI 15
+#define RX_ID_COUNT_SZ 8
+#define TX_ID_THOLD_MSK 0x000000ff
+#define TX_ID_THOLD_I_MSK 0xffffff00
+#define TX_ID_THOLD_SFT 0
+#define TX_ID_THOLD_HI 7
+#define TX_ID_THOLD_SZ 8
+#define RX_ID_THOLD_MSK 0x0000ff00
+#define RX_ID_THOLD_I_MSK 0xffff00ff
+#define RX_ID_THOLD_SFT 8
+#define RX_ID_THOLD_HI 15
+#define RX_ID_THOLD_SZ 8
+#define ID_THOLD_RX_INT_MSK 0x00010000
+#define ID_THOLD_RX_INT_I_MSK 0xfffeffff
+#define ID_THOLD_RX_INT_SFT 16
+#define ID_THOLD_RX_INT_HI 16
+#define ID_THOLD_RX_INT_SZ 1
+#define RX_INT_CH_MSK 0x000e0000
+#define RX_INT_CH_I_MSK 0xfff1ffff
+#define RX_INT_CH_SFT 17
+#define RX_INT_CH_HI 19
+#define RX_INT_CH_SZ 3
+#define ID_THOLD_TX_INT_MSK 0x00100000
+#define ID_THOLD_TX_INT_I_MSK 0xffefffff
+#define ID_THOLD_TX_INT_SFT 20
+#define ID_THOLD_TX_INT_HI 20
+#define ID_THOLD_TX_INT_SZ 1
+#define TX_INT_CH_MSK 0x00e00000
+#define TX_INT_CH_I_MSK 0xff1fffff
+#define TX_INT_CH_SFT 21
+#define TX_INT_CH_HI 23
+#define TX_INT_CH_SZ 3
+#define ID_THOLD_INT_EN_MSK 0x01000000
+#define ID_THOLD_INT_EN_I_MSK 0xfeffffff
+#define ID_THOLD_INT_EN_SFT 24
+#define ID_THOLD_INT_EN_HI 24
+#define ID_THOLD_INT_EN_SZ 1
+#define TX_ID_TB0_MSK 0xffffffff
+#define TX_ID_TB0_I_MSK 0x00000000
+#define TX_ID_TB0_SFT 0
+#define TX_ID_TB0_HI 31
+#define TX_ID_TB0_SZ 32
+#define TX_ID_TB1_MSK 0xffffffff
+#define TX_ID_TB1_I_MSK 0x00000000
+#define TX_ID_TB1_SFT 0
+#define TX_ID_TB1_HI 31
+#define TX_ID_TB1_SZ 32
+#define RX_ID_TB0_MSK 0xffffffff
+#define RX_ID_TB0_I_MSK 0x00000000
+#define RX_ID_TB0_SFT 0
+#define RX_ID_TB0_HI 31
+#define RX_ID_TB0_SZ 32
+#define RX_ID_TB1_MSK 0xffffffff
+#define RX_ID_TB1_I_MSK 0x00000000
+#define RX_ID_TB1_SFT 0
+#define RX_ID_TB1_HI 31
+#define RX_ID_TB1_SZ 32
+#define DOUBLE_RLS_INT_EN_MSK 0x00000001
+#define DOUBLE_RLS_INT_EN_I_MSK 0xfffffffe
+#define DOUBLE_RLS_INT_EN_SFT 0
+#define DOUBLE_RLS_INT_EN_HI 0
+#define DOUBLE_RLS_INT_EN_SZ 1
+#define ID_DOUBLE_RLS_INT_MSK 0x00000002
+#define ID_DOUBLE_RLS_INT_I_MSK 0xfffffffd
+#define ID_DOUBLE_RLS_INT_SFT 1
+#define ID_DOUBLE_RLS_INT_HI 1
+#define ID_DOUBLE_RLS_INT_SZ 1
+#define DOUBLE_RLS_ID_MSK 0x00007f00
+#define DOUBLE_RLS_ID_I_MSK 0xffff80ff
+#define DOUBLE_RLS_ID_SFT 8
+#define DOUBLE_RLS_ID_HI 14
+#define DOUBLE_RLS_ID_SZ 7
+#define ID_LEN_THOLD_INT_EN_MSK 0x00000001
+#define ID_LEN_THOLD_INT_EN_I_MSK 0xfffffffe
+#define ID_LEN_THOLD_INT_EN_SFT 0
+#define ID_LEN_THOLD_INT_EN_HI 0
+#define ID_LEN_THOLD_INT_EN_SZ 1
+#define ALL_ID_LEN_THOLD_INT_MSK 0x00000002
+#define ALL_ID_LEN_THOLD_INT_I_MSK 0xfffffffd
+#define ALL_ID_LEN_THOLD_INT_SFT 1
+#define ALL_ID_LEN_THOLD_INT_HI 1
+#define ALL_ID_LEN_THOLD_INT_SZ 1
+#define TX_ID_LEN_THOLD_INT_MSK 0x00000004
+#define TX_ID_LEN_THOLD_INT_I_MSK 0xfffffffb
+#define TX_ID_LEN_THOLD_INT_SFT 2
+#define TX_ID_LEN_THOLD_INT_HI 2
+#define TX_ID_LEN_THOLD_INT_SZ 1
+#define RX_ID_LEN_THOLD_INT_MSK 0x00000008
+#define RX_ID_LEN_THOLD_INT_I_MSK 0xfffffff7
+#define RX_ID_LEN_THOLD_INT_SFT 3
+#define RX_ID_LEN_THOLD_INT_HI 3
+#define RX_ID_LEN_THOLD_INT_SZ 1
+#define ID_TX_LEN_THOLD_MSK 0x00001ff0
+#define ID_TX_LEN_THOLD_I_MSK 0xffffe00f
+#define ID_TX_LEN_THOLD_SFT 4
+#define ID_TX_LEN_THOLD_HI 12
+#define ID_TX_LEN_THOLD_SZ 9
+#define ID_RX_LEN_THOLD_MSK 0x003fe000
+#define ID_RX_LEN_THOLD_I_MSK 0xffc01fff
+#define ID_RX_LEN_THOLD_SFT 13
+#define ID_RX_LEN_THOLD_HI 21
+#define ID_RX_LEN_THOLD_SZ 9
+#define ID_LEN_THOLD_MSK 0x7fc00000
+#define ID_LEN_THOLD_I_MSK 0x803fffff
+#define ID_LEN_THOLD_SFT 22
+#define ID_LEN_THOLD_HI 30
+#define ID_LEN_THOLD_SZ 9
+#define ALL_ID_ALC_LEN_MSK 0x000001ff
+#define ALL_ID_ALC_LEN_I_MSK 0xfffffe00
+#define ALL_ID_ALC_LEN_SFT 0
+#define ALL_ID_ALC_LEN_HI 8
+#define ALL_ID_ALC_LEN_SZ 9
+#define TX_ID_ALC_LEN_MSK 0x0003fe00
+#define TX_ID_ALC_LEN_I_MSK 0xfffc01ff
+#define TX_ID_ALC_LEN_SFT 9
+#define TX_ID_ALC_LEN_HI 17
+#define TX_ID_ALC_LEN_SZ 9
+#define RX_ID_ALC_LEN_MSK 0x07fc0000
+#define RX_ID_ALC_LEN_I_MSK 0xf803ffff
+#define RX_ID_ALC_LEN_SFT 18
+#define RX_ID_ALC_LEN_HI 26
+#define RX_ID_ALC_LEN_SZ 9
+#define CH_ARB_EN_MSK 0x00000001
+#define CH_ARB_EN_I_MSK 0xfffffffe
+#define CH_ARB_EN_SFT 0
+#define CH_ARB_EN_HI 0
+#define CH_ARB_EN_SZ 1
+#define CH_PRI1_MSK 0x00000030
+#define CH_PRI1_I_MSK 0xffffffcf
+#define CH_PRI1_SFT 4
+#define CH_PRI1_HI 5
+#define CH_PRI1_SZ 2
+#define CH_PRI2_MSK 0x00000300
+#define CH_PRI2_I_MSK 0xfffffcff
+#define CH_PRI2_SFT 8
+#define CH_PRI2_HI 9
+#define CH_PRI2_SZ 2
+#define CH_PRI3_MSK 0x00003000
+#define CH_PRI3_I_MSK 0xffffcfff
+#define CH_PRI3_SFT 12
+#define CH_PRI3_HI 13
+#define CH_PRI3_SZ 2
+#define CH_PRI4_MSK 0x00030000
+#define CH_PRI4_I_MSK 0xfffcffff
+#define CH_PRI4_SFT 16
+#define CH_PRI4_HI 17
+#define CH_PRI4_SZ 2
+#define TX_ID_REMAIN_MSK 0x0000007f
+#define TX_ID_REMAIN_I_MSK 0xffffff80
+#define TX_ID_REMAIN_SFT 0
+#define TX_ID_REMAIN_HI 6
+#define TX_ID_REMAIN_SZ 7
+#define TX_PAGE_REMAIN_MSK 0x0001ff00
+#define TX_PAGE_REMAIN_I_MSK 0xfffe00ff
+#define TX_PAGE_REMAIN_SFT 8
+#define TX_PAGE_REMAIN_HI 16
+#define TX_PAGE_REMAIN_SZ 9
+#define ID_PAGE_MAX_SIZE_MSK 0x000001ff
+#define ID_PAGE_MAX_SIZE_I_MSK 0xfffffe00
+#define ID_PAGE_MAX_SIZE_SFT 0
+#define ID_PAGE_MAX_SIZE_HI 8
+#define ID_PAGE_MAX_SIZE_SZ 9
+#define TX_PAGE_LIMIT_MSK 0x000001ff
+#define TX_PAGE_LIMIT_I_MSK 0xfffffe00
+#define TX_PAGE_LIMIT_SFT 0
+#define TX_PAGE_LIMIT_HI 8
+#define TX_PAGE_LIMIT_SZ 9
+#define TX_COUNT_LIMIT_MSK 0x00ff0000
+#define TX_COUNT_LIMIT_I_MSK 0xff00ffff
+#define TX_COUNT_LIMIT_SFT 16
+#define TX_COUNT_LIMIT_HI 23
+#define TX_COUNT_LIMIT_SZ 8
+#define TX_LIMIT_INT_MSK 0x40000000
+#define TX_LIMIT_INT_I_MSK 0xbfffffff
+#define TX_LIMIT_INT_SFT 30
+#define TX_LIMIT_INT_HI 30
+#define TX_LIMIT_INT_SZ 1
+#define TX_LIMIT_INT_EN_MSK 0x80000000
+#define TX_LIMIT_INT_EN_I_MSK 0x7fffffff
+#define TX_LIMIT_INT_EN_SFT 31
+#define TX_LIMIT_INT_EN_HI 31
+#define TX_LIMIT_INT_EN_SZ 1
+#define TX_PAGE_USE_7_0_MSK 0x000000ff
+#define TX_PAGE_USE_7_0_I_MSK 0xffffff00
+#define TX_PAGE_USE_7_0_SFT 0
+#define TX_PAGE_USE_7_0_HI 7
+#define TX_PAGE_USE_7_0_SZ 8
+#define TX_ID_USE_5_0_MSK 0x00003f00
+#define TX_ID_USE_5_0_I_MSK 0xffffc0ff
+#define TX_ID_USE_5_0_SFT 8
+#define TX_ID_USE_5_0_HI 13
+#define TX_ID_USE_5_0_SZ 6
+#define EDCA0_FFO_CNT_MSK 0x0003c000
+#define EDCA0_FFO_CNT_I_MSK 0xfffc3fff
+#define EDCA0_FFO_CNT_SFT 14
+#define EDCA0_FFO_CNT_HI 17
+#define EDCA0_FFO_CNT_SZ 4
+#define EDCA1_FFO_CNT_3_0_MSK 0x003c0000
+#define EDCA1_FFO_CNT_3_0_I_MSK 0xffc3ffff
+#define EDCA1_FFO_CNT_3_0_SFT 18
+#define EDCA1_FFO_CNT_3_0_HI 21
+#define EDCA1_FFO_CNT_3_0_SZ 4
+#define EDCA2_FFO_CNT_MSK 0x07c00000
+#define EDCA2_FFO_CNT_I_MSK 0xf83fffff
+#define EDCA2_FFO_CNT_SFT 22
+#define EDCA2_FFO_CNT_HI 26
+#define EDCA2_FFO_CNT_SZ 5
+#define EDCA3_FFO_CNT_MSK 0xf8000000
+#define EDCA3_FFO_CNT_I_MSK 0x07ffffff
+#define EDCA3_FFO_CNT_SFT 27
+#define EDCA3_FFO_CNT_HI 31
+#define EDCA3_FFO_CNT_SZ 5
+#define ID_TB2_MSK 0xffffffff
+#define ID_TB2_I_MSK 0x00000000
+#define ID_TB2_SFT 0
+#define ID_TB2_HI 31
+#define ID_TB2_SZ 32
+#define ID_TB3_MSK 0xffffffff
+#define ID_TB3_I_MSK 0x00000000
+#define ID_TB3_SFT 0
+#define ID_TB3_HI 31
+#define ID_TB3_SZ 32
+#define TX_ID_TB2_MSK 0xffffffff
+#define TX_ID_TB2_I_MSK 0x00000000
+#define TX_ID_TB2_SFT 0
+#define TX_ID_TB2_HI 31
+#define TX_ID_TB2_SZ 32
+#define TX_ID_TB3_MSK 0xffffffff
+#define TX_ID_TB3_I_MSK 0x00000000
+#define TX_ID_TB3_SFT 0
+#define TX_ID_TB3_HI 31
+#define TX_ID_TB3_SZ 32
+#define RX_ID_TB2_MSK 0xffffffff
+#define RX_ID_TB2_I_MSK 0x00000000
+#define RX_ID_TB2_SFT 0
+#define RX_ID_TB2_HI 31
+#define RX_ID_TB2_SZ 32
+#define RX_ID_TB3_MSK 0xffffffff
+#define RX_ID_TB3_I_MSK 0x00000000
+#define RX_ID_TB3_SFT 0
+#define RX_ID_TB3_HI 31
+#define RX_ID_TB3_SZ 32
+#define TX_PAGE_USE2_MSK 0x000001ff
+#define TX_PAGE_USE2_I_MSK 0xfffffe00
+#define TX_PAGE_USE2_SFT 0
+#define TX_PAGE_USE2_HI 8
+#define TX_PAGE_USE2_SZ 9
+#define TX_ID_USE2_MSK 0x0001fe00
+#define TX_ID_USE2_I_MSK 0xfffe01ff
+#define TX_ID_USE2_SFT 9
+#define TX_ID_USE2_HI 16
+#define TX_ID_USE2_SZ 8
+#define EDCA4_FFO_CNT_MSK 0x001e0000
+#define EDCA4_FFO_CNT_I_MSK 0xffe1ffff
+#define EDCA4_FFO_CNT_SFT 17
+#define EDCA4_FFO_CNT_HI 20
+#define EDCA4_FFO_CNT_SZ 4
+#define TX_PAGE_USE3_MSK 0x000001ff
+#define TX_PAGE_USE3_I_MSK 0xfffffe00
+#define TX_PAGE_USE3_SFT 0
+#define TX_PAGE_USE3_HI 8
+#define TX_PAGE_USE3_SZ 9
+#define TX_ID_USE3_MSK 0x0001fe00
+#define TX_ID_USE3_I_MSK 0xfffe01ff
+#define TX_ID_USE3_SFT 9
+#define TX_ID_USE3_HI 16
+#define TX_ID_USE3_SZ 8
+#define EDCA1_FFO_CNT2_MSK 0x03e00000
+#define EDCA1_FFO_CNT2_I_MSK 0xfc1fffff
+#define EDCA1_FFO_CNT2_SFT 21
+#define EDCA1_FFO_CNT2_HI 25
+#define EDCA1_FFO_CNT2_SZ 5
+#define EDCA4_FFO_CNT2_MSK 0x3c000000
+#define EDCA4_FFO_CNT2_I_MSK 0xc3ffffff
+#define EDCA4_FFO_CNT2_SFT 26
+#define EDCA4_FFO_CNT2_HI 29
+#define EDCA4_FFO_CNT2_SZ 4
+#define TX_PAGE_USE4_MSK 0x000001ff
+#define TX_PAGE_USE4_I_MSK 0xfffffe00
+#define TX_PAGE_USE4_SFT 0
+#define TX_PAGE_USE4_HI 8
+#define TX_PAGE_USE4_SZ 9
+#define TX_ID_USE4_MSK 0x0001fe00
+#define TX_ID_USE4_I_MSK 0xfffe01ff
+#define TX_ID_USE4_SFT 9
+#define TX_ID_USE4_HI 16
+#define TX_ID_USE4_SZ 8
+#define EDCA2_FFO_CNT2_MSK 0x003e0000
+#define EDCA2_FFO_CNT2_I_MSK 0xffc1ffff
+#define EDCA2_FFO_CNT2_SFT 17
+#define EDCA2_FFO_CNT2_HI 21
+#define EDCA2_FFO_CNT2_SZ 5
+#define EDCA3_FFO_CNT2_MSK 0x07c00000
+#define EDCA3_FFO_CNT2_I_MSK 0xf83fffff
+#define EDCA3_FFO_CNT2_SFT 22
+#define EDCA3_FFO_CNT2_HI 26
+#define EDCA3_FFO_CNT2_SZ 5
+#define TX_ID_IFO_LEN_MSK 0x000001ff
+#define TX_ID_IFO_LEN_I_MSK 0xfffffe00
+#define TX_ID_IFO_LEN_SFT 0
+#define TX_ID_IFO_LEN_HI 8
+#define TX_ID_IFO_LEN_SZ 9
+#define RX_ID_IFO_LEN_MSK 0x01ff0000
+#define RX_ID_IFO_LEN_I_MSK 0xfe00ffff
+#define RX_ID_IFO_LEN_SFT 16
+#define RX_ID_IFO_LEN_HI 24
+#define RX_ID_IFO_LEN_SZ 9
+#define MAX_ALL_ALC_ID_CNT_MSK 0x000000ff
+#define MAX_ALL_ALC_ID_CNT_I_MSK 0xffffff00
+#define MAX_ALL_ALC_ID_CNT_SFT 0
+#define MAX_ALL_ALC_ID_CNT_HI 7
+#define MAX_ALL_ALC_ID_CNT_SZ 8
+#define MAX_TX_ALC_ID_CNT_MSK 0x0000ff00
+#define MAX_TX_ALC_ID_CNT_I_MSK 0xffff00ff
+#define MAX_TX_ALC_ID_CNT_SFT 8
+#define MAX_TX_ALC_ID_CNT_HI 15
+#define MAX_TX_ALC_ID_CNT_SZ 8
+#define MAX_RX_ALC_ID_CNT_MSK 0x00ff0000
+#define MAX_RX_ALC_ID_CNT_I_MSK 0xff00ffff
+#define MAX_RX_ALC_ID_CNT_SFT 16
+#define MAX_RX_ALC_ID_CNT_HI 23
+#define MAX_RX_ALC_ID_CNT_SZ 8
+#define MAX_ALL_ID_ALC_LEN_MSK 0x000001ff
+#define MAX_ALL_ID_ALC_LEN_I_MSK 0xfffffe00
+#define MAX_ALL_ID_ALC_LEN_SFT 0
+#define MAX_ALL_ID_ALC_LEN_HI 8
+#define MAX_ALL_ID_ALC_LEN_SZ 9
+#define MAX_TX_ID_ALC_LEN_MSK 0x0003fe00
+#define MAX_TX_ID_ALC_LEN_I_MSK 0xfffc01ff
+#define MAX_TX_ID_ALC_LEN_SFT 9
+#define MAX_TX_ID_ALC_LEN_HI 17
+#define MAX_TX_ID_ALC_LEN_SZ 9
+#define MAX_RX_ID_ALC_LEN_MSK 0x07fc0000
+#define MAX_RX_ID_ALC_LEN_I_MSK 0xf803ffff
+#define MAX_RX_ID_ALC_LEN_SFT 18
+#define MAX_RX_ID_ALC_LEN_HI 26
+#define MAX_RX_ID_ALC_LEN_SZ 9
+#define RG_PMDLBK_MSK 0x00000001
+#define RG_PMDLBK_I_MSK 0xfffffffe
+#define RG_PMDLBK_SFT 0
+#define RG_PMDLBK_HI 0
+#define RG_PMDLBK_SZ 1
+#define RG_RDYACK_SEL_MSK 0x00000006
+#define RG_RDYACK_SEL_I_MSK 0xfffffff9
+#define RG_RDYACK_SEL_SFT 1
+#define RG_RDYACK_SEL_HI 2
+#define RG_RDYACK_SEL_SZ 2
+#define RG_ADEDGE_SEL_MSK 0x00000008
+#define RG_ADEDGE_SEL_I_MSK 0xfffffff7
+#define RG_ADEDGE_SEL_SFT 3
+#define RG_ADEDGE_SEL_HI 3
+#define RG_ADEDGE_SEL_SZ 1
+#define RG_SIGN_SWAP_MSK 0x00000010
+#define RG_SIGN_SWAP_I_MSK 0xffffffef
+#define RG_SIGN_SWAP_SFT 4
+#define RG_SIGN_SWAP_HI 4
+#define RG_SIGN_SWAP_SZ 1
+#define RG_IQ_SWAP_MSK 0x00000020
+#define RG_IQ_SWAP_I_MSK 0xffffffdf
+#define RG_IQ_SWAP_SFT 5
+#define RG_IQ_SWAP_HI 5
+#define RG_IQ_SWAP_SZ 1
+#define RG_Q_INV_MSK 0x00000040
+#define RG_Q_INV_I_MSK 0xffffffbf
+#define RG_Q_INV_SFT 6
+#define RG_Q_INV_HI 6
+#define RG_Q_INV_SZ 1
+#define RG_I_INV_MSK 0x00000080
+#define RG_I_INV_I_MSK 0xffffff7f
+#define RG_I_INV_SFT 7
+#define RG_I_INV_HI 7
+#define RG_I_INV_SZ 1
+#define RG_BYPASS_ACI_MSK 0x00000100
+#define RG_BYPASS_ACI_I_MSK 0xfffffeff
+#define RG_BYPASS_ACI_SFT 8
+#define RG_BYPASS_ACI_HI 8
+#define RG_BYPASS_ACI_SZ 1
+#define RG_LBK_ANA_PATH_MSK 0x00000200
+#define RG_LBK_ANA_PATH_I_MSK 0xfffffdff
+#define RG_LBK_ANA_PATH_SFT 9
+#define RG_LBK_ANA_PATH_HI 9
+#define RG_LBK_ANA_PATH_SZ 1
+#define RG_SPECTRUM_LEAKY_FACTOR_MSK 0x00000c00
+#define RG_SPECTRUM_LEAKY_FACTOR_I_MSK 0xfffff3ff
+#define RG_SPECTRUM_LEAKY_FACTOR_SFT 10
+#define RG_SPECTRUM_LEAKY_FACTOR_HI 11
+#define RG_SPECTRUM_LEAKY_FACTOR_SZ 2
+#define RG_SPECTRUM_BW_MSK 0x00003000
+#define RG_SPECTRUM_BW_I_MSK 0xffffcfff
+#define RG_SPECTRUM_BW_SFT 12
+#define RG_SPECTRUM_BW_HI 13
+#define RG_SPECTRUM_BW_SZ 2
+#define RG_SPECTRUM_FREQ_MANUAL_MSK 0x00004000
+#define RG_SPECTRUM_FREQ_MANUAL_I_MSK 0xffffbfff
+#define RG_SPECTRUM_FREQ_MANUAL_SFT 14
+#define RG_SPECTRUM_FREQ_MANUAL_HI 14
+#define RG_SPECTRUM_FREQ_MANUAL_SZ 1
+#define RG_SPECTRUM_EN_MSK 0x00008000
+#define RG_SPECTRUM_EN_I_MSK 0xffff7fff
+#define RG_SPECTRUM_EN_SFT 15
+#define RG_SPECTRUM_EN_HI 15
+#define RG_SPECTRUM_EN_SZ 1
+#define RG_TXPWRLVL_SET_MSK 0x00ff0000
+#define RG_TXPWRLVL_SET_I_MSK 0xff00ffff
+#define RG_TXPWRLVL_SET_SFT 16
+#define RG_TXPWRLVL_SET_HI 23
+#define RG_TXPWRLVL_SET_SZ 8
+#define RG_TXPWRLVL_SEL_MSK 0x01000000
+#define RG_TXPWRLVL_SEL_I_MSK 0xfeffffff
+#define RG_TXPWRLVL_SEL_SFT 24
+#define RG_TXPWRLVL_SEL_HI 24
+#define RG_TXPWRLVL_SEL_SZ 1
+#define RG_RF_BB_CLK_SEL_MSK 0x80000000
+#define RG_RF_BB_CLK_SEL_I_MSK 0x7fffffff
+#define RG_RF_BB_CLK_SEL_SFT 31
+#define RG_RF_BB_CLK_SEL_HI 31
+#define RG_RF_BB_CLK_SEL_SZ 1
+#define RG_PHY_MD_EN_MSK 0x00000001
+#define RG_PHY_MD_EN_I_MSK 0xfffffffe
+#define RG_PHY_MD_EN_SFT 0
+#define RG_PHY_MD_EN_HI 0
+#define RG_PHY_MD_EN_SZ 1
+#define RG_PHYRX_MD_EN_MSK 0x00000002
+#define RG_PHYRX_MD_EN_I_MSK 0xfffffffd
+#define RG_PHYRX_MD_EN_SFT 1
+#define RG_PHYRX_MD_EN_HI 1
+#define RG_PHYRX_MD_EN_SZ 1
+#define RG_PHYTX_MD_EN_MSK 0x00000004
+#define RG_PHYTX_MD_EN_I_MSK 0xfffffffb
+#define RG_PHYTX_MD_EN_SFT 2
+#define RG_PHYTX_MD_EN_HI 2
+#define RG_PHYTX_MD_EN_SZ 1
+#define RG_PHY11GN_MD_EN_MSK 0x00000008
+#define RG_PHY11GN_MD_EN_I_MSK 0xfffffff7
+#define RG_PHY11GN_MD_EN_SFT 3
+#define RG_PHY11GN_MD_EN_HI 3
+#define RG_PHY11GN_MD_EN_SZ 1
+#define RG_PHY11B_MD_EN_MSK 0x00000010
+#define RG_PHY11B_MD_EN_I_MSK 0xffffffef
+#define RG_PHY11B_MD_EN_SFT 4
+#define RG_PHY11B_MD_EN_HI 4
+#define RG_PHY11B_MD_EN_SZ 1
+#define RG_PHYRXFIFO_MD_EN_MSK 0x00000020
+#define RG_PHYRXFIFO_MD_EN_I_MSK 0xffffffdf
+#define RG_PHYRXFIFO_MD_EN_SFT 5
+#define RG_PHYRXFIFO_MD_EN_HI 5
+#define RG_PHYRXFIFO_MD_EN_SZ 1
+#define RG_PHYTXFIFO_MD_EN_MSK 0x00000040
+#define RG_PHYTXFIFO_MD_EN_I_MSK 0xffffffbf
+#define RG_PHYTXFIFO_MD_EN_SFT 6
+#define RG_PHYTXFIFO_MD_EN_HI 6
+#define RG_PHYTXFIFO_MD_EN_SZ 1
+#define RG_PHY11BGN_MD_EN_MSK 0x00000100
+#define RG_PHY11BGN_MD_EN_I_MSK 0xfffffeff
+#define RG_PHY11BGN_MD_EN_SFT 8
+#define RG_PHY11BGN_MD_EN_HI 8
+#define RG_PHY11BGN_MD_EN_SZ 1
+#define RG_FORCE_11GN_EN_MSK 0x00001000
+#define RG_FORCE_11GN_EN_I_MSK 0xffffefff
+#define RG_FORCE_11GN_EN_SFT 12
+#define RG_FORCE_11GN_EN_HI 12
+#define RG_FORCE_11GN_EN_SZ 1
+#define RG_FORCE_11B_EN_MSK 0x00002000
+#define RG_FORCE_11B_EN_I_MSK 0xffffdfff
+#define RG_FORCE_11B_EN_SFT 13
+#define RG_FORCE_11B_EN_HI 13
+#define RG_FORCE_11B_EN_SZ 1
+#define RG_FFT_MEM_CLK_EN_RX_MSK 0x00004000
+#define RG_FFT_MEM_CLK_EN_RX_I_MSK 0xffffbfff
+#define RG_FFT_MEM_CLK_EN_RX_SFT 14
+#define RG_FFT_MEM_CLK_EN_RX_HI 14
+#define RG_FFT_MEM_CLK_EN_RX_SZ 1
+#define RG_FFT_MEM_CLK_EN_TX_MSK 0x00008000
+#define RG_FFT_MEM_CLK_EN_TX_I_MSK 0xffff7fff
+#define RG_FFT_MEM_CLK_EN_TX_SFT 15
+#define RG_FFT_MEM_CLK_EN_TX_HI 15
+#define RG_FFT_MEM_CLK_EN_TX_SZ 1
+#define RG_PHY_IQ_TRIG_SEL_MSK 0x000f0000
+#define RG_PHY_IQ_TRIG_SEL_I_MSK 0xfff0ffff
+#define RG_PHY_IQ_TRIG_SEL_SFT 16
+#define RG_PHY_IQ_TRIG_SEL_HI 19
+#define RG_PHY_IQ_TRIG_SEL_SZ 4
+#define RG_SPECTRUM_FREQ_MSK 0x3ff00000
+#define RG_SPECTRUM_FREQ_I_MSK 0xc00fffff
+#define RG_SPECTRUM_FREQ_SFT 20
+#define RG_SPECTRUM_FREQ_HI 29
+#define RG_SPECTRUM_FREQ_SZ 10
+#define SVN_VERSION_MSK 0xffffffff
+#define SVN_VERSION_I_MSK 0x00000000
+#define SVN_VERSION_SFT 0
+#define SVN_VERSION_HI 31
+#define SVN_VERSION_SZ 32
+#define RG_LENGTH_MSK 0x0000ffff
+#define RG_LENGTH_I_MSK 0xffff0000
+#define RG_LENGTH_SFT 0
+#define RG_LENGTH_HI 15
+#define RG_LENGTH_SZ 16
+#define RG_PKT_MODE_MSK 0x00070000
+#define RG_PKT_MODE_I_MSK 0xfff8ffff
+#define RG_PKT_MODE_SFT 16
+#define RG_PKT_MODE_HI 18
+#define RG_PKT_MODE_SZ 3
+#define RG_CH_BW_MSK 0x00380000
+#define RG_CH_BW_I_MSK 0xffc7ffff
+#define RG_CH_BW_SFT 19
+#define RG_CH_BW_HI 21
+#define RG_CH_BW_SZ 3
+#define RG_PRM_MSK 0x00400000
+#define RG_PRM_I_MSK 0xffbfffff
+#define RG_PRM_SFT 22
+#define RG_PRM_HI 22
+#define RG_PRM_SZ 1
+#define RG_SHORTGI_MSK 0x00800000
+#define RG_SHORTGI_I_MSK 0xff7fffff
+#define RG_SHORTGI_SFT 23
+#define RG_SHORTGI_HI 23
+#define RG_SHORTGI_SZ 1
+#define RG_RATE_MSK 0x7f000000
+#define RG_RATE_I_MSK 0x80ffffff
+#define RG_RATE_SFT 24
+#define RG_RATE_HI 30
+#define RG_RATE_SZ 7
+#define RG_L_LENGTH_MSK 0x00000fff
+#define RG_L_LENGTH_I_MSK 0xfffff000
+#define RG_L_LENGTH_SFT 0
+#define RG_L_LENGTH_HI 11
+#define RG_L_LENGTH_SZ 12
+#define RG_L_RATE_MSK 0x00007000
+#define RG_L_RATE_I_MSK 0xffff8fff
+#define RG_L_RATE_SFT 12
+#define RG_L_RATE_HI 14
+#define RG_L_RATE_SZ 3
+#define RG_SERVICE_MSK 0xffff0000
+#define RG_SERVICE_I_MSK 0x0000ffff
+#define RG_SERVICE_SFT 16
+#define RG_SERVICE_HI 31
+#define RG_SERVICE_SZ 16
+#define RG_SMOOTHING_MSK 0x00000001
+#define RG_SMOOTHING_I_MSK 0xfffffffe
+#define RG_SMOOTHING_SFT 0
+#define RG_SMOOTHING_HI 0
+#define RG_SMOOTHING_SZ 1
+#define RG_NO_SOUND_MSK 0x00000002
+#define RG_NO_SOUND_I_MSK 0xfffffffd
+#define RG_NO_SOUND_SFT 1
+#define RG_NO_SOUND_HI 1
+#define RG_NO_SOUND_SZ 1
+#define RG_AGGREGATE_MSK 0x00000004
+#define RG_AGGREGATE_I_MSK 0xfffffffb
+#define RG_AGGREGATE_SFT 2
+#define RG_AGGREGATE_HI 2
+#define RG_AGGREGATE_SZ 1
+#define RG_STBC_MSK 0x00000018
+#define RG_STBC_I_MSK 0xffffffe7
+#define RG_STBC_SFT 3
+#define RG_STBC_HI 4
+#define RG_STBC_SZ 2
+#define RG_FEC_MSK 0x00000020
+#define RG_FEC_I_MSK 0xffffffdf
+#define RG_FEC_SFT 5
+#define RG_FEC_HI 5
+#define RG_FEC_SZ 1
+#define RG_N_ESS_MSK 0x000000c0
+#define RG_N_ESS_I_MSK 0xffffff3f
+#define RG_N_ESS_SFT 6
+#define RG_N_ESS_HI 7
+#define RG_N_ESS_SZ 2
+#define RG_TXPWRLVL_MSK 0x0000ff00
+#define RG_TXPWRLVL_I_MSK 0xffff00ff
+#define RG_TXPWRLVL_SFT 8
+#define RG_TXPWRLVL_HI 15
+#define RG_TXPWRLVL_SZ 8
+#define RG_TX_START_MSK 0x00000001
+#define RG_TX_START_I_MSK 0xfffffffe
+#define RG_TX_START_SFT 0
+#define RG_TX_START_HI 0
+#define RG_TX_START_SZ 1
+#define RG_IFS_TIME_MSK 0x000000fc
+#define RG_IFS_TIME_I_MSK 0xffffff03
+#define RG_IFS_TIME_SFT 2
+#define RG_IFS_TIME_HI 7
+#define RG_IFS_TIME_SZ 6
+#define RG_CONTINUOUS_DATA_MSK 0x00000100
+#define RG_CONTINUOUS_DATA_I_MSK 0xfffffeff
+#define RG_CONTINUOUS_DATA_SFT 8
+#define RG_CONTINUOUS_DATA_HI 8
+#define RG_CONTINUOUS_DATA_SZ 1
+#define RG_DATA_SEL_MSK 0x00000600
+#define RG_DATA_SEL_I_MSK 0xfffff9ff
+#define RG_DATA_SEL_SFT 9
+#define RG_DATA_SEL_HI 10
+#define RG_DATA_SEL_SZ 2
+#define RG_TX_D_MSK 0x00ff0000
+#define RG_TX_D_I_MSK 0xff00ffff
+#define RG_TX_D_SFT 16
+#define RG_TX_D_HI 23
+#define RG_TX_D_SZ 8
+#define RG_TX_CNT_TARGET_MSK 0xffffffff
+#define RG_TX_CNT_TARGET_I_MSK 0x00000000
+#define RG_TX_CNT_TARGET_SFT 0
+#define RG_TX_CNT_TARGET_HI 31
+#define RG_TX_CNT_TARGET_SZ 32
+#define RG_FFT_IFFT_MODE_MSK 0x000000c0
+#define RG_FFT_IFFT_MODE_I_MSK 0xffffff3f
+#define RG_FFT_IFFT_MODE_SFT 6
+#define RG_FFT_IFFT_MODE_HI 7
+#define RG_FFT_IFFT_MODE_SZ 2
+#define RG_DAC_DBG_MODE_MSK 0x00000100
+#define RG_DAC_DBG_MODE_I_MSK 0xfffffeff
+#define RG_DAC_DBG_MODE_SFT 8
+#define RG_DAC_DBG_MODE_HI 8
+#define RG_DAC_DBG_MODE_SZ 1
+#define RG_DAC_SGN_SWAP_MSK 0x00000200
+#define RG_DAC_SGN_SWAP_I_MSK 0xfffffdff
+#define RG_DAC_SGN_SWAP_SFT 9
+#define RG_DAC_SGN_SWAP_HI 9
+#define RG_DAC_SGN_SWAP_SZ 1
+#define RG_TXD_SEL_MSK 0x00000c00
+#define RG_TXD_SEL_I_MSK 0xfffff3ff
+#define RG_TXD_SEL_SFT 10
+#define RG_TXD_SEL_HI 11
+#define RG_TXD_SEL_SZ 2
+#define RG_UP8X_MSK 0x00ff0000
+#define RG_UP8X_I_MSK 0xff00ffff
+#define RG_UP8X_SFT 16
+#define RG_UP8X_HI 23
+#define RG_UP8X_SZ 8
+#define RG_IQ_DC_BYP_MSK 0x01000000
+#define RG_IQ_DC_BYP_I_MSK 0xfeffffff
+#define RG_IQ_DC_BYP_SFT 24
+#define RG_IQ_DC_BYP_HI 24
+#define RG_IQ_DC_BYP_SZ 1
+#define RG_IQ_DC_LEAKY_FACTOR_MSK 0x30000000
+#define RG_IQ_DC_LEAKY_FACTOR_I_MSK 0xcfffffff
+#define RG_IQ_DC_LEAKY_FACTOR_SFT 28
+#define RG_IQ_DC_LEAKY_FACTOR_HI 29
+#define RG_IQ_DC_LEAKY_FACTOR_SZ 2
+#define RG_DAC_DCEN_MSK 0x00000001
+#define RG_DAC_DCEN_I_MSK 0xfffffffe
+#define RG_DAC_DCEN_SFT 0
+#define RG_DAC_DCEN_HI 0
+#define RG_DAC_DCEN_SZ 1
+#define RG_DAC_DCQ_MSK 0x00003ff0
+#define RG_DAC_DCQ_I_MSK 0xffffc00f
+#define RG_DAC_DCQ_SFT 4
+#define RG_DAC_DCQ_HI 13
+#define RG_DAC_DCQ_SZ 10
+#define RG_DAC_DCI_MSK 0x03ff0000
+#define RG_DAC_DCI_I_MSK 0xfc00ffff
+#define RG_DAC_DCI_SFT 16
+#define RG_DAC_DCI_HI 25
+#define RG_DAC_DCI_SZ 10
+#define RG_PGA_REFDB_SAT_MSK 0x0000007f
+#define RG_PGA_REFDB_SAT_I_MSK 0xffffff80
+#define RG_PGA_REFDB_SAT_SFT 0
+#define RG_PGA_REFDB_SAT_HI 6
+#define RG_PGA_REFDB_SAT_SZ 7
+#define RG_PGA_REFDB_TOP_MSK 0x00007f00
+#define RG_PGA_REFDB_TOP_I_MSK 0xffff80ff
+#define RG_PGA_REFDB_TOP_SFT 8
+#define RG_PGA_REFDB_TOP_HI 14
+#define RG_PGA_REFDB_TOP_SZ 7
+#define RG_PGA_REF_UND_MSK 0x03ff0000
+#define RG_PGA_REF_UND_I_MSK 0xfc00ffff
+#define RG_PGA_REF_UND_SFT 16
+#define RG_PGA_REF_UND_HI 25
+#define RG_PGA_REF_UND_SZ 10
+#define RG_RF_REF_SAT_MSK 0xf0000000
+#define RG_RF_REF_SAT_I_MSK 0x0fffffff
+#define RG_RF_REF_SAT_SFT 28
+#define RG_RF_REF_SAT_HI 31
+#define RG_RF_REF_SAT_SZ 4
+#define RG_PGAGC_SET_MSK 0x0000000f
+#define RG_PGAGC_SET_I_MSK 0xfffffff0
+#define RG_PGAGC_SET_SFT 0
+#define RG_PGAGC_SET_HI 3
+#define RG_PGAGC_SET_SZ 4
+#define RG_PGAGC_OW_MSK 0x00000010
+#define RG_PGAGC_OW_I_MSK 0xffffffef
+#define RG_PGAGC_OW_SFT 4
+#define RG_PGAGC_OW_HI 4
+#define RG_PGAGC_OW_SZ 1
+#define RG_RFGC_SET_MSK 0x00000060
+#define RG_RFGC_SET_I_MSK 0xffffff9f
+#define RG_RFGC_SET_SFT 5
+#define RG_RFGC_SET_HI 6
+#define RG_RFGC_SET_SZ 2
+#define RG_RFGC_OW_MSK 0x00000080
+#define RG_RFGC_OW_I_MSK 0xffffff7f
+#define RG_RFGC_OW_SFT 7
+#define RG_RFGC_OW_HI 7
+#define RG_RFGC_OW_SZ 1
+#define RG_WAIT_T_RXAGC_MSK 0x00003f00
+#define RG_WAIT_T_RXAGC_I_MSK 0xffffc0ff
+#define RG_WAIT_T_RXAGC_SFT 8
+#define RG_WAIT_T_RXAGC_HI 13
+#define RG_WAIT_T_RXAGC_SZ 6
+#define RG_RXAGC_SET_MSK 0x00004000
+#define RG_RXAGC_SET_I_MSK 0xffffbfff
+#define RG_RXAGC_SET_SFT 14
+#define RG_RXAGC_SET_HI 14
+#define RG_RXAGC_SET_SZ 1
+#define RG_RXAGC_OW_MSK 0x00008000
+#define RG_RXAGC_OW_I_MSK 0xffff7fff
+#define RG_RXAGC_OW_SFT 15
+#define RG_RXAGC_OW_HI 15
+#define RG_RXAGC_OW_SZ 1
+#define RG_WAIT_T_FINAL_MSK 0x003f0000
+#define RG_WAIT_T_FINAL_I_MSK 0xffc0ffff
+#define RG_WAIT_T_FINAL_SFT 16
+#define RG_WAIT_T_FINAL_HI 21
+#define RG_WAIT_T_FINAL_SZ 6
+#define RG_WAIT_T_MSK 0x3f000000
+#define RG_WAIT_T_I_MSK 0xc0ffffff
+#define RG_WAIT_T_SFT 24
+#define RG_WAIT_T_HI 29
+#define RG_WAIT_T_SZ 6
+#define RG_ULG_PGA_SAT_PGA_GAIN_MSK 0x0000000f
+#define RG_ULG_PGA_SAT_PGA_GAIN_I_MSK 0xfffffff0
+#define RG_ULG_PGA_SAT_PGA_GAIN_SFT 0
+#define RG_ULG_PGA_SAT_PGA_GAIN_HI 3
+#define RG_ULG_PGA_SAT_PGA_GAIN_SZ 4
+#define RG_LG_PGA_UND_PGA_GAIN_MSK 0x000000f0
+#define RG_LG_PGA_UND_PGA_GAIN_I_MSK 0xffffff0f
+#define RG_LG_PGA_UND_PGA_GAIN_SFT 4
+#define RG_LG_PGA_UND_PGA_GAIN_HI 7
+#define RG_LG_PGA_UND_PGA_GAIN_SZ 4
+#define RG_LG_PGA_SAT_PGA_GAIN_MSK 0x00000f00
+#define RG_LG_PGA_SAT_PGA_GAIN_I_MSK 0xfffff0ff
+#define RG_LG_PGA_SAT_PGA_GAIN_SFT 8
+#define RG_LG_PGA_SAT_PGA_GAIN_HI 11
+#define RG_LG_PGA_SAT_PGA_GAIN_SZ 4
+#define RG_LG_RF_SAT_PGA_GAIN_MSK 0x0000f000
+#define RG_LG_RF_SAT_PGA_GAIN_I_MSK 0xffff0fff
+#define RG_LG_RF_SAT_PGA_GAIN_SFT 12
+#define RG_LG_RF_SAT_PGA_GAIN_HI 15
+#define RG_LG_RF_SAT_PGA_GAIN_SZ 4
+#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_MSK 0x000f0000
+#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_I_MSK 0xfff0ffff
+#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_SFT 16
+#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_HI 19
+#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_SZ 4
+#define RG_HG_PGA_SAT2_PGA_GAIN_MSK 0x00f00000
+#define RG_HG_PGA_SAT2_PGA_GAIN_I_MSK 0xff0fffff
+#define RG_HG_PGA_SAT2_PGA_GAIN_SFT 20
+#define RG_HG_PGA_SAT2_PGA_GAIN_HI 23
+#define RG_HG_PGA_SAT2_PGA_GAIN_SZ 4
+#define RG_HG_PGA_SAT1_PGA_GAIN_MSK 0x0f000000
+#define RG_HG_PGA_SAT1_PGA_GAIN_I_MSK 0xf0ffffff
+#define RG_HG_PGA_SAT1_PGA_GAIN_SFT 24
+#define RG_HG_PGA_SAT1_PGA_GAIN_HI 27
+#define RG_HG_PGA_SAT1_PGA_GAIN_SZ 4
+#define RG_HG_RF_SAT_PGA_GAIN_MSK 0xf0000000
+#define RG_HG_RF_SAT_PGA_GAIN_I_MSK 0x0fffffff
+#define RG_HG_RF_SAT_PGA_GAIN_SFT 28
+#define RG_HG_RF_SAT_PGA_GAIN_HI 31
+#define RG_HG_RF_SAT_PGA_GAIN_SZ 4
+#define RG_MG_PGA_JB_TH_MSK 0x0000000f
+#define RG_MG_PGA_JB_TH_I_MSK 0xfffffff0
+#define RG_MG_PGA_JB_TH_SFT 0
+#define RG_MG_PGA_JB_TH_HI 3
+#define RG_MG_PGA_JB_TH_SZ 4
+#define RG_MA_PGA_LOW_TH_CNT_LMT_MSK 0x001f0000
+#define RG_MA_PGA_LOW_TH_CNT_LMT_I_MSK 0xffe0ffff
+#define RG_MA_PGA_LOW_TH_CNT_LMT_SFT 16
+#define RG_MA_PGA_LOW_TH_CNT_LMT_HI 20
+#define RG_MA_PGA_LOW_TH_CNT_LMT_SZ 5
+#define RG_WR_RFGC_INIT_SET_MSK 0x00600000
+#define RG_WR_RFGC_INIT_SET_I_MSK 0xff9fffff
+#define RG_WR_RFGC_INIT_SET_SFT 21
+#define RG_WR_RFGC_INIT_SET_HI 22
+#define RG_WR_RFGC_INIT_SET_SZ 2
+#define RG_WR_RFGC_INIT_EN_MSK 0x00800000
+#define RG_WR_RFGC_INIT_EN_I_MSK 0xff7fffff
+#define RG_WR_RFGC_INIT_EN_SFT 23
+#define RG_WR_RFGC_INIT_EN_HI 23
+#define RG_WR_RFGC_INIT_EN_SZ 1
+#define RG_MA_PGA_HIGH_TH_CNT_LMT_MSK 0x1f000000
+#define RG_MA_PGA_HIGH_TH_CNT_LMT_I_MSK 0xe0ffffff
+#define RG_MA_PGA_HIGH_TH_CNT_LMT_SFT 24
+#define RG_MA_PGA_HIGH_TH_CNT_LMT_HI 28
+#define RG_MA_PGA_HIGH_TH_CNT_LMT_SZ 5
+#define RG_AGC_THRESHOLD_MSK 0x00003fff
+#define RG_AGC_THRESHOLD_I_MSK 0xffffc000
+#define RG_AGC_THRESHOLD_SFT 0
+#define RG_AGC_THRESHOLD_HI 13
+#define RG_AGC_THRESHOLD_SZ 14
+#define RG_ACI_POINT_CNT_LMT_11B_MSK 0x007f0000
+#define RG_ACI_POINT_CNT_LMT_11B_I_MSK 0xff80ffff
+#define RG_ACI_POINT_CNT_LMT_11B_SFT 16
+#define RG_ACI_POINT_CNT_LMT_11B_HI 22
+#define RG_ACI_POINT_CNT_LMT_11B_SZ 7
+#define RG_ACI_DAGC_LEAKY_FACTOR_11B_MSK 0x03000000
+#define RG_ACI_DAGC_LEAKY_FACTOR_11B_I_MSK 0xfcffffff
+#define RG_ACI_DAGC_LEAKY_FACTOR_11B_SFT 24
+#define RG_ACI_DAGC_LEAKY_FACTOR_11B_HI 25
+#define RG_ACI_DAGC_LEAKY_FACTOR_11B_SZ 2
+#define RG_WR_ACI_GAIN_INI_SEL_11B_MSK 0x000000ff
+#define RG_WR_ACI_GAIN_INI_SEL_11B_I_MSK 0xffffff00
+#define RG_WR_ACI_GAIN_INI_SEL_11B_SFT 0
+#define RG_WR_ACI_GAIN_INI_SEL_11B_HI 7
+#define RG_WR_ACI_GAIN_INI_SEL_11B_SZ 8
+#define RG_WR_ACI_GAIN_SEL_11B_MSK 0x0000ff00
+#define RG_WR_ACI_GAIN_SEL_11B_I_MSK 0xffff00ff
+#define RG_WR_ACI_GAIN_SEL_11B_SFT 8
+#define RG_WR_ACI_GAIN_SEL_11B_HI 15
+#define RG_WR_ACI_GAIN_SEL_11B_SZ 8
+#define RG_ACI_DAGC_SET_VALUE_11B_MSK 0x007f0000
+#define RG_ACI_DAGC_SET_VALUE_11B_I_MSK 0xff80ffff
+#define RG_ACI_DAGC_SET_VALUE_11B_SFT 16
+#define RG_ACI_DAGC_SET_VALUE_11B_HI 22
+#define RG_ACI_DAGC_SET_VALUE_11B_SZ 7
+#define RG_WR_ACI_GAIN_OW_11B_MSK 0x80000000
+#define RG_WR_ACI_GAIN_OW_11B_I_MSK 0x7fffffff
+#define RG_WR_ACI_GAIN_OW_11B_SFT 31
+#define RG_WR_ACI_GAIN_OW_11B_HI 31
+#define RG_WR_ACI_GAIN_OW_11B_SZ 1
+#define RG_ACI_POINT_CNT_LMT_11GN_MSK 0x000000ff
+#define RG_ACI_POINT_CNT_LMT_11GN_I_MSK 0xffffff00
+#define RG_ACI_POINT_CNT_LMT_11GN_SFT 0
+#define RG_ACI_POINT_CNT_LMT_11GN_HI 7
+#define RG_ACI_POINT_CNT_LMT_11GN_SZ 8
+#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_MSK 0x00000300
+#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_I_MSK 0xfffffcff
+#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_SFT 8
+#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_HI 9
+#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_SZ 2
+#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_MSK 0xff000000
+#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_I_MSK 0x00ffffff
+#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_SFT 24
+#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_HI 31
+#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_SZ 8
+#define RG_ACI_DAGC_SET_VALUE_11GN_MSK 0x0000007f
+#define RG_ACI_DAGC_SET_VALUE_11GN_I_MSK 0xffffff80
+#define RG_ACI_DAGC_SET_VALUE_11GN_SFT 0
+#define RG_ACI_DAGC_SET_VALUE_11GN_HI 6
+#define RG_ACI_DAGC_SET_VALUE_11GN_SZ 7
+#define RG_ACI_GAIN_INI_VAL_11GN_MSK 0x0000ff00
+#define RG_ACI_GAIN_INI_VAL_11GN_I_MSK 0xffff00ff
+#define RG_ACI_GAIN_INI_VAL_11GN_SFT 8
+#define RG_ACI_GAIN_INI_VAL_11GN_HI 15
+#define RG_ACI_GAIN_INI_VAL_11GN_SZ 8
+#define RG_ACI_GAIN_OW_VAL_11GN_MSK 0x00ff0000
+#define RG_ACI_GAIN_OW_VAL_11GN_I_MSK 0xff00ffff
+#define RG_ACI_GAIN_OW_VAL_11GN_SFT 16
+#define RG_ACI_GAIN_OW_VAL_11GN_HI 23
+#define RG_ACI_GAIN_OW_VAL_11GN_SZ 8
+#define RG_ACI_GAIN_OW_11GN_MSK 0x80000000
+#define RG_ACI_GAIN_OW_11GN_I_MSK 0x7fffffff
+#define RG_ACI_GAIN_OW_11GN_SFT 31
+#define RG_ACI_GAIN_OW_11GN_HI 31
+#define RG_ACI_GAIN_OW_11GN_SZ 1
+#define RO_CCA_PWR_MA_11GN_MSK 0x0000007f
+#define RO_CCA_PWR_MA_11GN_I_MSK 0xffffff80
+#define RO_CCA_PWR_MA_11GN_SFT 0
+#define RO_CCA_PWR_MA_11GN_HI 6
+#define RO_CCA_PWR_MA_11GN_SZ 7
+#define RO_ED_STATE_MSK 0x00008000
+#define RO_ED_STATE_I_MSK 0xffff7fff
+#define RO_ED_STATE_SFT 15
+#define RO_ED_STATE_HI 15
+#define RO_ED_STATE_SZ 1
+#define RO_CCA_PWR_MA_11B_MSK 0x007f0000
+#define RO_CCA_PWR_MA_11B_I_MSK 0xff80ffff
+#define RO_CCA_PWR_MA_11B_SFT 16
+#define RO_CCA_PWR_MA_11B_HI 22
+#define RO_CCA_PWR_MA_11B_SZ 7
+#define RO_PGA_PWR_FF1_MSK 0x00003fff
+#define RO_PGA_PWR_FF1_I_MSK 0xffffc000
+#define RO_PGA_PWR_FF1_SFT 0
+#define RO_PGA_PWR_FF1_HI 13
+#define RO_PGA_PWR_FF1_SZ 14
+#define RO_RF_PWR_FF1_MSK 0x000f0000
+#define RO_RF_PWR_FF1_I_MSK 0xfff0ffff
+#define RO_RF_PWR_FF1_SFT 16
+#define RO_RF_PWR_FF1_HI 19
+#define RO_RF_PWR_FF1_SZ 4
+#define RO_PGAGC_FF1_MSK 0x0f000000
+#define RO_PGAGC_FF1_I_MSK 0xf0ffffff
+#define RO_PGAGC_FF1_SFT 24
+#define RO_PGAGC_FF1_HI 27
+#define RO_PGAGC_FF1_SZ 4
+#define RO_RFGC_FF1_MSK 0x30000000
+#define RO_RFGC_FF1_I_MSK 0xcfffffff
+#define RO_RFGC_FF1_SFT 28
+#define RO_RFGC_FF1_HI 29
+#define RO_RFGC_FF1_SZ 2
+#define RO_PGA_PWR_FF2_MSK 0x00003fff
+#define RO_PGA_PWR_FF2_I_MSK 0xffffc000
+#define RO_PGA_PWR_FF2_SFT 0
+#define RO_PGA_PWR_FF2_HI 13
+#define RO_PGA_PWR_FF2_SZ 14
+#define RO_RF_PWR_FF2_MSK 0x000f0000
+#define RO_RF_PWR_FF2_I_MSK 0xfff0ffff
+#define RO_RF_PWR_FF2_SFT 16
+#define RO_RF_PWR_FF2_HI 19
+#define RO_RF_PWR_FF2_SZ 4
+#define RO_PGAGC_FF2_MSK 0x0f000000
+#define RO_PGAGC_FF2_I_MSK 0xf0ffffff
+#define RO_PGAGC_FF2_SFT 24
+#define RO_PGAGC_FF2_HI 27
+#define RO_PGAGC_FF2_SZ 4
+#define RO_RFGC_FF2_MSK 0x30000000
+#define RO_RFGC_FF2_I_MSK 0xcfffffff
+#define RO_RFGC_FF2_SFT 28
+#define RO_RFGC_FF2_HI 29
+#define RO_RFGC_FF2_SZ 2
+#define RO_PGA_PWR_FF3_MSK 0x00003fff
+#define RO_PGA_PWR_FF3_I_MSK 0xffffc000
+#define RO_PGA_PWR_FF3_SFT 0
+#define RO_PGA_PWR_FF3_HI 13
+#define RO_PGA_PWR_FF3_SZ 14
+#define RO_RF_PWR_FF3_MSK 0x000f0000
+#define RO_RF_PWR_FF3_I_MSK 0xfff0ffff
+#define RO_RF_PWR_FF3_SFT 16
+#define RO_RF_PWR_FF3_HI 19
+#define RO_RF_PWR_FF3_SZ 4
+#define RO_PGAGC_FF3_MSK 0x0f000000
+#define RO_PGAGC_FF3_I_MSK 0xf0ffffff
+#define RO_PGAGC_FF3_SFT 24
+#define RO_PGAGC_FF3_HI 27
+#define RO_PGAGC_FF3_SZ 4
+#define RO_RFGC_FF3_MSK 0x30000000
+#define RO_RFGC_FF3_I_MSK 0xcfffffff
+#define RO_RFGC_FF3_SFT 28
+#define RO_RFGC_FF3_HI 29
+#define RO_RFGC_FF3_SZ 2
+#define RG_TX_DES_RATE_MSK 0x0000001f
+#define RG_TX_DES_RATE_I_MSK 0xffffffe0
+#define RG_TX_DES_RATE_SFT 0
+#define RG_TX_DES_RATE_HI 4
+#define RG_TX_DES_RATE_SZ 5
+#define RG_TX_DES_MODE_MSK 0x00001f00
+#define RG_TX_DES_MODE_I_MSK 0xffffe0ff
+#define RG_TX_DES_MODE_SFT 8
+#define RG_TX_DES_MODE_HI 12
+#define RG_TX_DES_MODE_SZ 5
+#define RG_TX_DES_LEN_LO_MSK 0x001f0000
+#define RG_TX_DES_LEN_LO_I_MSK 0xffe0ffff
+#define RG_TX_DES_LEN_LO_SFT 16
+#define RG_TX_DES_LEN_LO_HI 20
+#define RG_TX_DES_LEN_LO_SZ 5
+#define RG_TX_DES_LEN_UP_MSK 0x1f000000
+#define RG_TX_DES_LEN_UP_I_MSK 0xe0ffffff
+#define RG_TX_DES_LEN_UP_SFT 24
+#define RG_TX_DES_LEN_UP_HI 28
+#define RG_TX_DES_LEN_UP_SZ 5
+#define RG_TX_DES_SRVC_UP_MSK 0x0000001f
+#define RG_TX_DES_SRVC_UP_I_MSK 0xffffffe0
+#define RG_TX_DES_SRVC_UP_SFT 0
+#define RG_TX_DES_SRVC_UP_HI 4
+#define RG_TX_DES_SRVC_UP_SZ 5
+#define RG_TX_DES_L_LEN_LO_MSK 0x00001f00
+#define RG_TX_DES_L_LEN_LO_I_MSK 0xffffe0ff
+#define RG_TX_DES_L_LEN_LO_SFT 8
+#define RG_TX_DES_L_LEN_LO_HI 12
+#define RG_TX_DES_L_LEN_LO_SZ 5
+#define RG_TX_DES_L_LEN_UP_MSK 0x001f0000
+#define RG_TX_DES_L_LEN_UP_I_MSK 0xffe0ffff
+#define RG_TX_DES_L_LEN_UP_SFT 16
+#define RG_TX_DES_L_LEN_UP_HI 20
+#define RG_TX_DES_L_LEN_UP_SZ 5
+#define RG_TX_DES_TYPE_MSK 0x1f000000
+#define RG_TX_DES_TYPE_I_MSK 0xe0ffffff
+#define RG_TX_DES_TYPE_SFT 24
+#define RG_TX_DES_TYPE_HI 28
+#define RG_TX_DES_TYPE_SZ 5
+#define RG_TX_DES_L_LEN_UP_COMB_MSK 0x00000001
+#define RG_TX_DES_L_LEN_UP_COMB_I_MSK 0xfffffffe
+#define RG_TX_DES_L_LEN_UP_COMB_SFT 0
+#define RG_TX_DES_L_LEN_UP_COMB_HI 0
+#define RG_TX_DES_L_LEN_UP_COMB_SZ 1
+#define RG_TX_DES_TYPE_COMB_MSK 0x00000010
+#define RG_TX_DES_TYPE_COMB_I_MSK 0xffffffef
+#define RG_TX_DES_TYPE_COMB_SFT 4
+#define RG_TX_DES_TYPE_COMB_HI 4
+#define RG_TX_DES_TYPE_COMB_SZ 1
+#define RG_TX_DES_RATE_COMB_MSK 0x00000100
+#define RG_TX_DES_RATE_COMB_I_MSK 0xfffffeff
+#define RG_TX_DES_RATE_COMB_SFT 8
+#define RG_TX_DES_RATE_COMB_HI 8
+#define RG_TX_DES_RATE_COMB_SZ 1
+#define RG_TX_DES_MODE_COMB_MSK 0x00001000
+#define RG_TX_DES_MODE_COMB_I_MSK 0xffffefff
+#define RG_TX_DES_MODE_COMB_SFT 12
+#define RG_TX_DES_MODE_COMB_HI 12
+#define RG_TX_DES_MODE_COMB_SZ 1
+#define RG_TX_DES_PWRLVL_MSK 0x001f0000
+#define RG_TX_DES_PWRLVL_I_MSK 0xffe0ffff
+#define RG_TX_DES_PWRLVL_SFT 16
+#define RG_TX_DES_PWRLVL_HI 20
+#define RG_TX_DES_PWRLVL_SZ 5
+#define RG_TX_DES_SRVC_LO_MSK 0x1f000000
+#define RG_TX_DES_SRVC_LO_I_MSK 0xe0ffffff
+#define RG_TX_DES_SRVC_LO_SFT 24
+#define RG_TX_DES_SRVC_LO_HI 28
+#define RG_TX_DES_SRVC_LO_SZ 5
+#define RG_RX_DES_RATE_MSK 0x0000003f
+#define RG_RX_DES_RATE_I_MSK 0xffffffc0
+#define RG_RX_DES_RATE_SFT 0
+#define RG_RX_DES_RATE_HI 5
+#define RG_RX_DES_RATE_SZ 6
+#define RG_RX_DES_MODE_MSK 0x00003f00
+#define RG_RX_DES_MODE_I_MSK 0xffffc0ff
+#define RG_RX_DES_MODE_SFT 8
+#define RG_RX_DES_MODE_HI 13
+#define RG_RX_DES_MODE_SZ 6
+#define RG_RX_DES_LEN_LO_MSK 0x003f0000
+#define RG_RX_DES_LEN_LO_I_MSK 0xffc0ffff
+#define RG_RX_DES_LEN_LO_SFT 16
+#define RG_RX_DES_LEN_LO_HI 21
+#define RG_RX_DES_LEN_LO_SZ 6
+#define RG_RX_DES_LEN_UP_MSK 0x3f000000
+#define RG_RX_DES_LEN_UP_I_MSK 0xc0ffffff
+#define RG_RX_DES_LEN_UP_SFT 24
+#define RG_RX_DES_LEN_UP_HI 29
+#define RG_RX_DES_LEN_UP_SZ 6
+#define RG_RX_DES_SRVC_UP_MSK 0x0000003f
+#define RG_RX_DES_SRVC_UP_I_MSK 0xffffffc0
+#define RG_RX_DES_SRVC_UP_SFT 0
+#define RG_RX_DES_SRVC_UP_HI 5
+#define RG_RX_DES_SRVC_UP_SZ 6
+#define RG_RX_DES_L_LEN_LO_MSK 0x00003f00
+#define RG_RX_DES_L_LEN_LO_I_MSK 0xffffc0ff
+#define RG_RX_DES_L_LEN_LO_SFT 8
+#define RG_RX_DES_L_LEN_LO_HI 13
+#define RG_RX_DES_L_LEN_LO_SZ 6
+#define RG_RX_DES_L_LEN_UP_MSK 0x003f0000
+#define RG_RX_DES_L_LEN_UP_I_MSK 0xffc0ffff
+#define RG_RX_DES_L_LEN_UP_SFT 16
+#define RG_RX_DES_L_LEN_UP_HI 21
+#define RG_RX_DES_L_LEN_UP_SZ 6
+#define RG_RX_DES_TYPE_MSK 0x3f000000
+#define RG_RX_DES_TYPE_I_MSK 0xc0ffffff
+#define RG_RX_DES_TYPE_SFT 24
+#define RG_RX_DES_TYPE_HI 29
+#define RG_RX_DES_TYPE_SZ 6
+#define RG_RX_DES_L_LEN_UP_COMB_MSK 0x00000001
+#define RG_RX_DES_L_LEN_UP_COMB_I_MSK 0xfffffffe
+#define RG_RX_DES_L_LEN_UP_COMB_SFT 0
+#define RG_RX_DES_L_LEN_UP_COMB_HI 0
+#define RG_RX_DES_L_LEN_UP_COMB_SZ 1
+#define RG_RX_DES_TYPE_COMB_MSK 0x00000010
+#define RG_RX_DES_TYPE_COMB_I_MSK 0xffffffef
+#define RG_RX_DES_TYPE_COMB_SFT 4
+#define RG_RX_DES_TYPE_COMB_HI 4
+#define RG_RX_DES_TYPE_COMB_SZ 1
+#define RG_RX_DES_RATE_COMB_MSK 0x00000100
+#define RG_RX_DES_RATE_COMB_I_MSK 0xfffffeff
+#define RG_RX_DES_RATE_COMB_SFT 8
+#define RG_RX_DES_RATE_COMB_HI 8
+#define RG_RX_DES_RATE_COMB_SZ 1
+#define RG_RX_DES_MODE_COMB_MSK 0x00001000
+#define RG_RX_DES_MODE_COMB_I_MSK 0xffffefff
+#define RG_RX_DES_MODE_COMB_SFT 12
+#define RG_RX_DES_MODE_COMB_HI 12
+#define RG_RX_DES_MODE_COMB_SZ 1
+#define RG_RX_DES_SNR_MSK 0x000f0000
+#define RG_RX_DES_SNR_I_MSK 0xfff0ffff
+#define RG_RX_DES_SNR_SFT 16
+#define RG_RX_DES_SNR_HI 19
+#define RG_RX_DES_SNR_SZ 4
+#define RG_RX_DES_RCPI_MSK 0x00f00000
+#define RG_RX_DES_RCPI_I_MSK 0xff0fffff
+#define RG_RX_DES_RCPI_SFT 20
+#define RG_RX_DES_RCPI_HI 23
+#define RG_RX_DES_RCPI_SZ 4
+#define RG_RX_DES_SRVC_LO_MSK 0x3f000000
+#define RG_RX_DES_SRVC_LO_I_MSK 0xc0ffffff
+#define RG_RX_DES_SRVC_LO_SFT 24
+#define RG_RX_DES_SRVC_LO_HI 29
+#define RG_RX_DES_SRVC_LO_SZ 6
+#define RO_TX_DES_EXCP_RATE_CNT_MSK 0x000000ff
+#define RO_TX_DES_EXCP_RATE_CNT_I_MSK 0xffffff00
+#define RO_TX_DES_EXCP_RATE_CNT_SFT 0
+#define RO_TX_DES_EXCP_RATE_CNT_HI 7
+#define RO_TX_DES_EXCP_RATE_CNT_SZ 8
+#define RO_TX_DES_EXCP_CH_BW_CNT_MSK 0x0000ff00
+#define RO_TX_DES_EXCP_CH_BW_CNT_I_MSK 0xffff00ff
+#define RO_TX_DES_EXCP_CH_BW_CNT_SFT 8
+#define RO_TX_DES_EXCP_CH_BW_CNT_HI 15
+#define RO_TX_DES_EXCP_CH_BW_CNT_SZ 8
+#define RO_TX_DES_EXCP_MODE_CNT_MSK 0x00ff0000
+#define RO_TX_DES_EXCP_MODE_CNT_I_MSK 0xff00ffff
+#define RO_TX_DES_EXCP_MODE_CNT_SFT 16
+#define RO_TX_DES_EXCP_MODE_CNT_HI 23
+#define RO_TX_DES_EXCP_MODE_CNT_SZ 8
+#define RG_TX_DES_EXCP_RATE_DEFAULT_MSK 0x07000000
+#define RG_TX_DES_EXCP_RATE_DEFAULT_I_MSK 0xf8ffffff
+#define RG_TX_DES_EXCP_RATE_DEFAULT_SFT 24
+#define RG_TX_DES_EXCP_RATE_DEFAULT_HI 26
+#define RG_TX_DES_EXCP_RATE_DEFAULT_SZ 3
+#define RG_TX_DES_EXCP_MODE_DEFAULT_MSK 0x70000000
+#define RG_TX_DES_EXCP_MODE_DEFAULT_I_MSK 0x8fffffff
+#define RG_TX_DES_EXCP_MODE_DEFAULT_SFT 28
+#define RG_TX_DES_EXCP_MODE_DEFAULT_HI 30
+#define RG_TX_DES_EXCP_MODE_DEFAULT_SZ 3
+#define RG_TX_DES_EXCP_CLR_MSK 0x80000000
+#define RG_TX_DES_EXCP_CLR_I_MSK 0x7fffffff
+#define RG_TX_DES_EXCP_CLR_SFT 31
+#define RG_TX_DES_EXCP_CLR_HI 31
+#define RG_TX_DES_EXCP_CLR_SZ 1
+#define RG_TX_DES_ACK_WIDTH_MSK 0x00000001
+#define RG_TX_DES_ACK_WIDTH_I_MSK 0xfffffffe
+#define RG_TX_DES_ACK_WIDTH_SFT 0
+#define RG_TX_DES_ACK_WIDTH_HI 0
+#define RG_TX_DES_ACK_WIDTH_SZ 1
+#define RG_TX_DES_ACK_PRD_MSK 0x0000000e
+#define RG_TX_DES_ACK_PRD_I_MSK 0xfffffff1
+#define RG_TX_DES_ACK_PRD_SFT 1
+#define RG_TX_DES_ACK_PRD_HI 3
+#define RG_TX_DES_ACK_PRD_SZ 3
+#define RG_RX_DES_SNR_GN_MSK 0x003f0000
+#define RG_RX_DES_SNR_GN_I_MSK 0xffc0ffff
+#define RG_RX_DES_SNR_GN_SFT 16
+#define RG_RX_DES_SNR_GN_HI 21
+#define RG_RX_DES_SNR_GN_SZ 6
+#define RG_RX_DES_RCPI_GN_MSK 0x3f000000
+#define RG_RX_DES_RCPI_GN_I_MSK 0xc0ffffff
+#define RG_RX_DES_RCPI_GN_SFT 24
+#define RG_RX_DES_RCPI_GN_HI 29
+#define RG_RX_DES_RCPI_GN_SZ 6
+#define RG_TST_TBUS_SEL_MSK 0x0000000f
+#define RG_TST_TBUS_SEL_I_MSK 0xfffffff0
+#define RG_TST_TBUS_SEL_SFT 0
+#define RG_TST_TBUS_SEL_HI 3
+#define RG_TST_TBUS_SEL_SZ 4
+#define RG_RSSI_OFFSET_MSK 0x00ff0000
+#define RG_RSSI_OFFSET_I_MSK 0xff00ffff
+#define RG_RSSI_OFFSET_SFT 16
+#define RG_RSSI_OFFSET_HI 23
+#define RG_RSSI_OFFSET_SZ 8
+#define RG_RSSI_INV_MSK 0x01000000
+#define RG_RSSI_INV_I_MSK 0xfeffffff
+#define RG_RSSI_INV_SFT 24
+#define RG_RSSI_INV_HI 24
+#define RG_RSSI_INV_SZ 1
+#define RG_TST_ADC_ON_MSK 0x40000000
+#define RG_TST_ADC_ON_I_MSK 0xbfffffff
+#define RG_TST_ADC_ON_SFT 30
+#define RG_TST_ADC_ON_HI 30
+#define RG_TST_ADC_ON_SZ 1
+#define RG_TST_EXT_GAIN_MSK 0x80000000
+#define RG_TST_EXT_GAIN_I_MSK 0x7fffffff
+#define RG_TST_EXT_GAIN_SFT 31
+#define RG_TST_EXT_GAIN_HI 31
+#define RG_TST_EXT_GAIN_SZ 1
+#define RG_DAC_Q_SET_MSK 0x000003ff
+#define RG_DAC_Q_SET_I_MSK 0xfffffc00
+#define RG_DAC_Q_SET_SFT 0
+#define RG_DAC_Q_SET_HI 9
+#define RG_DAC_Q_SET_SZ 10
+#define RG_DAC_I_SET_MSK 0x003ff000
+#define RG_DAC_I_SET_I_MSK 0xffc00fff
+#define RG_DAC_I_SET_SFT 12
+#define RG_DAC_I_SET_HI 21
+#define RG_DAC_I_SET_SZ 10
+#define RG_DAC_EN_MAN_MSK 0x10000000
+#define RG_DAC_EN_MAN_I_MSK 0xefffffff
+#define RG_DAC_EN_MAN_SFT 28
+#define RG_DAC_EN_MAN_HI 28
+#define RG_DAC_EN_MAN_SZ 1
+#define RG_IQC_FFT_EN_MSK 0x20000000
+#define RG_IQC_FFT_EN_I_MSK 0xdfffffff
+#define RG_IQC_FFT_EN_SFT 29
+#define RG_IQC_FFT_EN_HI 29
+#define RG_IQC_FFT_EN_SZ 1
+#define RG_DAC_MAN_Q_EN_MSK 0x40000000
+#define RG_DAC_MAN_Q_EN_I_MSK 0xbfffffff
+#define RG_DAC_MAN_Q_EN_SFT 30
+#define RG_DAC_MAN_Q_EN_HI 30
+#define RG_DAC_MAN_Q_EN_SZ 1
+#define RG_DAC_MAN_I_EN_MSK 0x80000000
+#define RG_DAC_MAN_I_EN_I_MSK 0x7fffffff
+#define RG_DAC_MAN_I_EN_SFT 31
+#define RG_DAC_MAN_I_EN_HI 31
+#define RG_DAC_MAN_I_EN_SZ 1
+#define RO_MRX_EN_CNT_MSK 0x0000ffff
+#define RO_MRX_EN_CNT_I_MSK 0xffff0000
+#define RO_MRX_EN_CNT_SFT 0
+#define RO_MRX_EN_CNT_HI 15
+#define RO_MRX_EN_CNT_SZ 16
+#define RG_MRX_EN_CNT_RST_N_MSK 0x80000000
+#define RG_MRX_EN_CNT_RST_N_I_MSK 0x7fffffff
+#define RG_MRX_EN_CNT_RST_N_SFT 31
+#define RG_MRX_EN_CNT_RST_N_HI 31
+#define RG_MRX_EN_CNT_RST_N_SZ 1
+#define RG_PA_RISE_TIME_MSK 0x000000ff
+#define RG_PA_RISE_TIME_I_MSK 0xffffff00
+#define RG_PA_RISE_TIME_SFT 0
+#define RG_PA_RISE_TIME_HI 7
+#define RG_PA_RISE_TIME_SZ 8
+#define RG_RFTX_RISE_TIME_MSK 0x0000ff00
+#define RG_RFTX_RISE_TIME_I_MSK 0xffff00ff
+#define RG_RFTX_RISE_TIME_SFT 8
+#define RG_RFTX_RISE_TIME_HI 15
+#define RG_RFTX_RISE_TIME_SZ 8
+#define RG_DAC_RISE_TIME_MSK 0x00ff0000
+#define RG_DAC_RISE_TIME_I_MSK 0xff00ffff
+#define RG_DAC_RISE_TIME_SFT 16
+#define RG_DAC_RISE_TIME_HI 23
+#define RG_DAC_RISE_TIME_SZ 8
+#define RG_SW_RISE_TIME_MSK 0xff000000
+#define RG_SW_RISE_TIME_I_MSK 0x00ffffff
+#define RG_SW_RISE_TIME_SFT 24
+#define RG_SW_RISE_TIME_HI 31
+#define RG_SW_RISE_TIME_SZ 8
+#define RG_PA_FALL_TIME_MSK 0x000000ff
+#define RG_PA_FALL_TIME_I_MSK 0xffffff00
+#define RG_PA_FALL_TIME_SFT 0
+#define RG_PA_FALL_TIME_HI 7
+#define RG_PA_FALL_TIME_SZ 8
+#define RG_RFTX_FALL_TIME_MSK 0x0000ff00
+#define RG_RFTX_FALL_TIME_I_MSK 0xffff00ff
+#define RG_RFTX_FALL_TIME_SFT 8
+#define RG_RFTX_FALL_TIME_HI 15
+#define RG_RFTX_FALL_TIME_SZ 8
+#define RG_DAC_FALL_TIME_MSK 0x00ff0000
+#define RG_DAC_FALL_TIME_I_MSK 0xff00ffff
+#define RG_DAC_FALL_TIME_SFT 16
+#define RG_DAC_FALL_TIME_HI 23
+#define RG_DAC_FALL_TIME_SZ 8
+#define RG_SW_FALL_TIME_MSK 0xff000000
+#define RG_SW_FALL_TIME_I_MSK 0x00ffffff
+#define RG_SW_FALL_TIME_SFT 24
+#define RG_SW_FALL_TIME_HI 31
+#define RG_SW_FALL_TIME_SZ 8
+#define RG_ANT_SW_0_MSK 0x00000007
+#define RG_ANT_SW_0_I_MSK 0xfffffff8
+#define RG_ANT_SW_0_SFT 0
+#define RG_ANT_SW_0_HI 2
+#define RG_ANT_SW_0_SZ 3
+#define RG_ANT_SW_1_MSK 0x00000038
+#define RG_ANT_SW_1_I_MSK 0xffffffc7
+#define RG_ANT_SW_1_SFT 3
+#define RG_ANT_SW_1_HI 5
+#define RG_ANT_SW_1_SZ 3
+#define RG_MTX_LEN_LOWER_TH_0_MSK 0x00001fff
+#define RG_MTX_LEN_LOWER_TH_0_I_MSK 0xffffe000
+#define RG_MTX_LEN_LOWER_TH_0_SFT 0
+#define RG_MTX_LEN_LOWER_TH_0_HI 12
+#define RG_MTX_LEN_LOWER_TH_0_SZ 13
+#define RG_MTX_LEN_UPPER_TH_0_MSK 0x1fff0000
+#define RG_MTX_LEN_UPPER_TH_0_I_MSK 0xe000ffff
+#define RG_MTX_LEN_UPPER_TH_0_SFT 16
+#define RG_MTX_LEN_UPPER_TH_0_HI 28
+#define RG_MTX_LEN_UPPER_TH_0_SZ 13
+#define RG_MTX_LEN_CNT_EN_0_MSK 0x80000000
+#define RG_MTX_LEN_CNT_EN_0_I_MSK 0x7fffffff
+#define RG_MTX_LEN_CNT_EN_0_SFT 31
+#define RG_MTX_LEN_CNT_EN_0_HI 31
+#define RG_MTX_LEN_CNT_EN_0_SZ 1
+#define RG_MTX_LEN_LOWER_TH_1_MSK 0x00001fff
+#define RG_MTX_LEN_LOWER_TH_1_I_MSK 0xffffe000
+#define RG_MTX_LEN_LOWER_TH_1_SFT 0
+#define RG_MTX_LEN_LOWER_TH_1_HI 12
+#define RG_MTX_LEN_LOWER_TH_1_SZ 13
+#define RG_MTX_LEN_UPPER_TH_1_MSK 0x1fff0000
+#define RG_MTX_LEN_UPPER_TH_1_I_MSK 0xe000ffff
+#define RG_MTX_LEN_UPPER_TH_1_SFT 16
+#define RG_MTX_LEN_UPPER_TH_1_HI 28
+#define RG_MTX_LEN_UPPER_TH_1_SZ 13
+#define RG_MTX_LEN_CNT_EN_1_MSK 0x80000000
+#define RG_MTX_LEN_CNT_EN_1_I_MSK 0x7fffffff
+#define RG_MTX_LEN_CNT_EN_1_SFT 31
+#define RG_MTX_LEN_CNT_EN_1_HI 31
+#define RG_MTX_LEN_CNT_EN_1_SZ 1
+#define RG_MRX_LEN_LOWER_TH_0_MSK 0x00001fff
+#define RG_MRX_LEN_LOWER_TH_0_I_MSK 0xffffe000
+#define RG_MRX_LEN_LOWER_TH_0_SFT 0
+#define RG_MRX_LEN_LOWER_TH_0_HI 12
+#define RG_MRX_LEN_LOWER_TH_0_SZ 13
+#define RG_MRX_LEN_UPPER_TH_0_MSK 0x1fff0000
+#define RG_MRX_LEN_UPPER_TH_0_I_MSK 0xe000ffff
+#define RG_MRX_LEN_UPPER_TH_0_SFT 16
+#define RG_MRX_LEN_UPPER_TH_0_HI 28
+#define RG_MRX_LEN_UPPER_TH_0_SZ 13
+#define RG_MRX_LEN_CNT_EN_0_MSK 0x80000000
+#define RG_MRX_LEN_CNT_EN_0_I_MSK 0x7fffffff
+#define RG_MRX_LEN_CNT_EN_0_SFT 31
+#define RG_MRX_LEN_CNT_EN_0_HI 31
+#define RG_MRX_LEN_CNT_EN_0_SZ 1
+#define RG_MRX_LEN_LOWER_TH_1_MSK 0x00001fff
+#define RG_MRX_LEN_LOWER_TH_1_I_MSK 0xffffe000
+#define RG_MRX_LEN_LOWER_TH_1_SFT 0
+#define RG_MRX_LEN_LOWER_TH_1_HI 12
+#define RG_MRX_LEN_LOWER_TH_1_SZ 13
+#define RG_MRX_LEN_UPPER_TH_1_MSK 0x1fff0000
+#define RG_MRX_LEN_UPPER_TH_1_I_MSK 0xe000ffff
+#define RG_MRX_LEN_UPPER_TH_1_SFT 16
+#define RG_MRX_LEN_UPPER_TH_1_HI 28
+#define RG_MRX_LEN_UPPER_TH_1_SZ 13
+#define RG_MRX_LEN_CNT_EN_1_MSK 0x80000000
+#define RG_MRX_LEN_CNT_EN_1_I_MSK 0x7fffffff
+#define RG_MRX_LEN_CNT_EN_1_SFT 31
+#define RG_MRX_LEN_CNT_EN_1_HI 31
+#define RG_MRX_LEN_CNT_EN_1_SZ 1
+#define RO_MTX_LEN_CNT_1_MSK 0x0000ffff
+#define RO_MTX_LEN_CNT_1_I_MSK 0xffff0000
+#define RO_MTX_LEN_CNT_1_SFT 0
+#define RO_MTX_LEN_CNT_1_HI 15
+#define RO_MTX_LEN_CNT_1_SZ 16
+#define RO_MTX_LEN_CNT_0_MSK 0xffff0000
+#define RO_MTX_LEN_CNT_0_I_MSK 0x0000ffff
+#define RO_MTX_LEN_CNT_0_SFT 16
+#define RO_MTX_LEN_CNT_0_HI 31
+#define RO_MTX_LEN_CNT_0_SZ 16
+#define RO_MRX_LEN_CNT_1_MSK 0x0000ffff
+#define RO_MRX_LEN_CNT_1_I_MSK 0xffff0000
+#define RO_MRX_LEN_CNT_1_SFT 0
+#define RO_MRX_LEN_CNT_1_HI 15
+#define RO_MRX_LEN_CNT_1_SZ 16
+#define RO_MRX_LEN_CNT_0_MSK 0xffff0000
+#define RO_MRX_LEN_CNT_0_I_MSK 0x0000ffff
+#define RO_MRX_LEN_CNT_0_SFT 16
+#define RO_MRX_LEN_CNT_0_HI 31
+#define RO_MRX_LEN_CNT_0_SZ 16
+#define RG_MODE_REG_IN_16_MSK 0x0000ffff
+#define RG_MODE_REG_IN_16_I_MSK 0xffff0000
+#define RG_MODE_REG_IN_16_SFT 0
+#define RG_MODE_REG_IN_16_HI 15
+#define RG_MODE_REG_IN_16_SZ 16
+#define RG_PARALLEL_DR_16_MSK 0x00100000
+#define RG_PARALLEL_DR_16_I_MSK 0xffefffff
+#define RG_PARALLEL_DR_16_SFT 20
+#define RG_PARALLEL_DR_16_HI 20
+#define RG_PARALLEL_DR_16_SZ 1
+#define RG_MBRUN_16_MSK 0x01000000
+#define RG_MBRUN_16_I_MSK 0xfeffffff
+#define RG_MBRUN_16_SFT 24
+#define RG_MBRUN_16_HI 24
+#define RG_MBRUN_16_SZ 1
+#define RG_SHIFT_DR_16_MSK 0x10000000
+#define RG_SHIFT_DR_16_I_MSK 0xefffffff
+#define RG_SHIFT_DR_16_SFT 28
+#define RG_SHIFT_DR_16_HI 28
+#define RG_SHIFT_DR_16_SZ 1
+#define RG_MODE_REG_SI_16_MSK 0x20000000
+#define RG_MODE_REG_SI_16_I_MSK 0xdfffffff
+#define RG_MODE_REG_SI_16_SFT 29
+#define RG_MODE_REG_SI_16_HI 29
+#define RG_MODE_REG_SI_16_SZ 1
+#define RG_SIMULATION_MODE_16_MSK 0x40000000
+#define RG_SIMULATION_MODE_16_I_MSK 0xbfffffff
+#define RG_SIMULATION_MODE_16_SFT 30
+#define RG_SIMULATION_MODE_16_HI 30
+#define RG_SIMULATION_MODE_16_SZ 1
+#define RG_DBIST_MODE_16_MSK 0x80000000
+#define RG_DBIST_MODE_16_I_MSK 0x7fffffff
+#define RG_DBIST_MODE_16_SFT 31
+#define RG_DBIST_MODE_16_HI 31
+#define RG_DBIST_MODE_16_SZ 1
+#define RO_MODE_REG_OUT_16_MSK 0x0000ffff
+#define RO_MODE_REG_OUT_16_I_MSK 0xffff0000
+#define RO_MODE_REG_OUT_16_SFT 0
+#define RO_MODE_REG_OUT_16_HI 15
+#define RO_MODE_REG_OUT_16_SZ 16
+#define RO_MODE_REG_SO_16_MSK 0x01000000
+#define RO_MODE_REG_SO_16_I_MSK 0xfeffffff
+#define RO_MODE_REG_SO_16_SFT 24
+#define RO_MODE_REG_SO_16_HI 24
+#define RO_MODE_REG_SO_16_SZ 1
+#define RO_MONITOR_BUS_16_MSK 0x0007ffff
+#define RO_MONITOR_BUS_16_I_MSK 0xfff80000
+#define RO_MONITOR_BUS_16_SFT 0
+#define RO_MONITOR_BUS_16_HI 18
+#define RO_MONITOR_BUS_16_SZ 19
+#define RG_MRX_TYPE_1_MSK 0x000000ff
+#define RG_MRX_TYPE_1_I_MSK 0xffffff00
+#define RG_MRX_TYPE_1_SFT 0
+#define RG_MRX_TYPE_1_HI 7
+#define RG_MRX_TYPE_1_SZ 8
+#define RG_MRX_TYPE_0_MSK 0x0000ff00
+#define RG_MRX_TYPE_0_I_MSK 0xffff00ff
+#define RG_MRX_TYPE_0_SFT 8
+#define RG_MRX_TYPE_0_HI 15
+#define RG_MRX_TYPE_0_SZ 8
+#define RG_MTX_TYPE_1_MSK 0x00ff0000
+#define RG_MTX_TYPE_1_I_MSK 0xff00ffff
+#define RG_MTX_TYPE_1_SFT 16
+#define RG_MTX_TYPE_1_HI 23
+#define RG_MTX_TYPE_1_SZ 8
+#define RG_MTX_TYPE_0_MSK 0xff000000
+#define RG_MTX_TYPE_0_I_MSK 0x00ffffff
+#define RG_MTX_TYPE_0_SFT 24
+#define RG_MTX_TYPE_0_HI 31
+#define RG_MTX_TYPE_0_SZ 8
+#define RO_MTX_TYPE_CNT_1_MSK 0x0000ffff
+#define RO_MTX_TYPE_CNT_1_I_MSK 0xffff0000
+#define RO_MTX_TYPE_CNT_1_SFT 0
+#define RO_MTX_TYPE_CNT_1_HI 15
+#define RO_MTX_TYPE_CNT_1_SZ 16
+#define RO_MTX_TYPE_CNT_0_MSK 0xffff0000
+#define RO_MTX_TYPE_CNT_0_I_MSK 0x0000ffff
+#define RO_MTX_TYPE_CNT_0_SFT 16
+#define RO_MTX_TYPE_CNT_0_HI 31
+#define RO_MTX_TYPE_CNT_0_SZ 16
+#define RO_MRX_TYPE_CNT_1_MSK 0x0000ffff
+#define RO_MRX_TYPE_CNT_1_I_MSK 0xffff0000
+#define RO_MRX_TYPE_CNT_1_SFT 0
+#define RO_MRX_TYPE_CNT_1_HI 15
+#define RO_MRX_TYPE_CNT_1_SZ 16
+#define RO_MRX_TYPE_CNT_0_MSK 0xffff0000
+#define RO_MRX_TYPE_CNT_0_I_MSK 0x0000ffff
+#define RO_MRX_TYPE_CNT_0_SFT 16
+#define RO_MRX_TYPE_CNT_0_HI 31
+#define RO_MRX_TYPE_CNT_0_SZ 16
+#define RG_HB_COEF0_MSK 0x00000fff
+#define RG_HB_COEF0_I_MSK 0xfffff000
+#define RG_HB_COEF0_SFT 0
+#define RG_HB_COEF0_HI 11
+#define RG_HB_COEF0_SZ 12
+#define RG_HB_COEF1_MSK 0x0fff0000
+#define RG_HB_COEF1_I_MSK 0xf000ffff
+#define RG_HB_COEF1_SFT 16
+#define RG_HB_COEF1_HI 27
+#define RG_HB_COEF1_SZ 12
+#define RG_HB_COEF2_MSK 0x00000fff
+#define RG_HB_COEF2_I_MSK 0xfffff000
+#define RG_HB_COEF2_SFT 0
+#define RG_HB_COEF2_HI 11
+#define RG_HB_COEF2_SZ 12
+#define RG_HB_COEF3_MSK 0x0fff0000
+#define RG_HB_COEF3_I_MSK 0xf000ffff
+#define RG_HB_COEF3_SFT 16
+#define RG_HB_COEF3_HI 27
+#define RG_HB_COEF3_SZ 12
+#define RG_HB_COEF4_MSK 0x00000fff
+#define RG_HB_COEF4_I_MSK 0xfffff000
+#define RG_HB_COEF4_SFT 0
+#define RG_HB_COEF4_HI 11
+#define RG_HB_COEF4_SZ 12
+#define RO_TBUS_O_MSK 0x000fffff
+#define RO_TBUS_O_I_MSK 0xfff00000
+#define RO_TBUS_O_SFT 0
+#define RO_TBUS_O_HI 19
+#define RO_TBUS_O_SZ 20
+#define RG_LPF4_00_MSK 0x00001fff
+#define RG_LPF4_00_I_MSK 0xffffe000
+#define RG_LPF4_00_SFT 0
+#define RG_LPF4_00_HI 12
+#define RG_LPF4_00_SZ 13
+#define RG_LPF4_01_MSK 0x00001fff
+#define RG_LPF4_01_I_MSK 0xffffe000
+#define RG_LPF4_01_SFT 0
+#define RG_LPF4_01_HI 12
+#define RG_LPF4_01_SZ 13
+#define RG_LPF4_02_MSK 0x00001fff
+#define RG_LPF4_02_I_MSK 0xffffe000
+#define RG_LPF4_02_SFT 0
+#define RG_LPF4_02_HI 12
+#define RG_LPF4_02_SZ 13
+#define RG_LPF4_03_MSK 0x00001fff
+#define RG_LPF4_03_I_MSK 0xffffe000
+#define RG_LPF4_03_SFT 0
+#define RG_LPF4_03_HI 12
+#define RG_LPF4_03_SZ 13
+#define RG_LPF4_04_MSK 0x00001fff
+#define RG_LPF4_04_I_MSK 0xffffe000
+#define RG_LPF4_04_SFT 0
+#define RG_LPF4_04_HI 12
+#define RG_LPF4_04_SZ 13
+#define RG_LPF4_05_MSK 0x00001fff
+#define RG_LPF4_05_I_MSK 0xffffe000
+#define RG_LPF4_05_SFT 0
+#define RG_LPF4_05_HI 12
+#define RG_LPF4_05_SZ 13
+#define RG_LPF4_06_MSK 0x00001fff
+#define RG_LPF4_06_I_MSK 0xffffe000
+#define RG_LPF4_06_SFT 0
+#define RG_LPF4_06_HI 12
+#define RG_LPF4_06_SZ 13
+#define RG_LPF4_07_MSK 0x00001fff
+#define RG_LPF4_07_I_MSK 0xffffe000
+#define RG_LPF4_07_SFT 0
+#define RG_LPF4_07_HI 12
+#define RG_LPF4_07_SZ 13
+#define RG_LPF4_08_MSK 0x00001fff
+#define RG_LPF4_08_I_MSK 0xffffe000
+#define RG_LPF4_08_SFT 0
+#define RG_LPF4_08_HI 12
+#define RG_LPF4_08_SZ 13
+#define RG_LPF4_09_MSK 0x00001fff
+#define RG_LPF4_09_I_MSK 0xffffe000
+#define RG_LPF4_09_SFT 0
+#define RG_LPF4_09_HI 12
+#define RG_LPF4_09_SZ 13
+#define RG_LPF4_10_MSK 0x00001fff
+#define RG_LPF4_10_I_MSK 0xffffe000
+#define RG_LPF4_10_SFT 0
+#define RG_LPF4_10_HI 12
+#define RG_LPF4_10_SZ 13
+#define RG_LPF4_11_MSK 0x00001fff
+#define RG_LPF4_11_I_MSK 0xffffe000
+#define RG_LPF4_11_SFT 0
+#define RG_LPF4_11_HI 12
+#define RG_LPF4_11_SZ 13
+#define RG_LPF4_12_MSK 0x00001fff
+#define RG_LPF4_12_I_MSK 0xffffe000
+#define RG_LPF4_12_SFT 0
+#define RG_LPF4_12_HI 12
+#define RG_LPF4_12_SZ 13
+#define RG_LPF4_13_MSK 0x00001fff
+#define RG_LPF4_13_I_MSK 0xffffe000
+#define RG_LPF4_13_SFT 0
+#define RG_LPF4_13_HI 12
+#define RG_LPF4_13_SZ 13
+#define RG_LPF4_14_MSK 0x00001fff
+#define RG_LPF4_14_I_MSK 0xffffe000
+#define RG_LPF4_14_SFT 0
+#define RG_LPF4_14_HI 12
+#define RG_LPF4_14_SZ 13
+#define RG_LPF4_15_MSK 0x00001fff
+#define RG_LPF4_15_I_MSK 0xffffe000
+#define RG_LPF4_15_SFT 0
+#define RG_LPF4_15_HI 12
+#define RG_LPF4_15_SZ 13
+#define RG_LPF4_16_MSK 0x00001fff
+#define RG_LPF4_16_I_MSK 0xffffe000
+#define RG_LPF4_16_SFT 0
+#define RG_LPF4_16_HI 12
+#define RG_LPF4_16_SZ 13
+#define RG_LPF4_17_MSK 0x00001fff
+#define RG_LPF4_17_I_MSK 0xffffe000
+#define RG_LPF4_17_SFT 0
+#define RG_LPF4_17_HI 12
+#define RG_LPF4_17_SZ 13
+#define RG_LPF4_18_MSK 0x00001fff
+#define RG_LPF4_18_I_MSK 0xffffe000
+#define RG_LPF4_18_SFT 0
+#define RG_LPF4_18_HI 12
+#define RG_LPF4_18_SZ 13
+#define RG_LPF4_19_MSK 0x00001fff
+#define RG_LPF4_19_I_MSK 0xffffe000
+#define RG_LPF4_19_SFT 0
+#define RG_LPF4_19_HI 12
+#define RG_LPF4_19_SZ 13
+#define RG_LPF4_20_MSK 0x00001fff
+#define RG_LPF4_20_I_MSK 0xffffe000
+#define RG_LPF4_20_SFT 0
+#define RG_LPF4_20_HI 12
+#define RG_LPF4_20_SZ 13
+#define RG_LPF4_21_MSK 0x00001fff
+#define RG_LPF4_21_I_MSK 0xffffe000
+#define RG_LPF4_21_SFT 0
+#define RG_LPF4_21_HI 12
+#define RG_LPF4_21_SZ 13
+#define RG_LPF4_22_MSK 0x00001fff
+#define RG_LPF4_22_I_MSK 0xffffe000
+#define RG_LPF4_22_SFT 0
+#define RG_LPF4_22_HI 12
+#define RG_LPF4_22_SZ 13
+#define RG_LPF4_23_MSK 0x00001fff
+#define RG_LPF4_23_I_MSK 0xffffe000
+#define RG_LPF4_23_SFT 0
+#define RG_LPF4_23_HI 12
+#define RG_LPF4_23_SZ 13
+#define RG_LPF4_24_MSK 0x00001fff
+#define RG_LPF4_24_I_MSK 0xffffe000
+#define RG_LPF4_24_SFT 0
+#define RG_LPF4_24_HI 12
+#define RG_LPF4_24_SZ 13
+#define RG_LPF4_25_MSK 0x00001fff
+#define RG_LPF4_25_I_MSK 0xffffe000
+#define RG_LPF4_25_SFT 0
+#define RG_LPF4_25_HI 12
+#define RG_LPF4_25_SZ 13
+#define RG_LPF4_26_MSK 0x00001fff
+#define RG_LPF4_26_I_MSK 0xffffe000
+#define RG_LPF4_26_SFT 0
+#define RG_LPF4_26_HI 12
+#define RG_LPF4_26_SZ 13
+#define RG_LPF4_27_MSK 0x00001fff
+#define RG_LPF4_27_I_MSK 0xffffe000
+#define RG_LPF4_27_SFT 0
+#define RG_LPF4_27_HI 12
+#define RG_LPF4_27_SZ 13
+#define RG_LPF4_28_MSK 0x00001fff
+#define RG_LPF4_28_I_MSK 0xffffe000
+#define RG_LPF4_28_SFT 0
+#define RG_LPF4_28_HI 12
+#define RG_LPF4_28_SZ 13
+#define RG_LPF4_29_MSK 0x00001fff
+#define RG_LPF4_29_I_MSK 0xffffe000
+#define RG_LPF4_29_SFT 0
+#define RG_LPF4_29_HI 12
+#define RG_LPF4_29_SZ 13
+#define RG_LPF4_30_MSK 0x00001fff
+#define RG_LPF4_30_I_MSK 0xffffe000
+#define RG_LPF4_30_SFT 0
+#define RG_LPF4_30_HI 12
+#define RG_LPF4_30_SZ 13
+#define RG_LPF4_31_MSK 0x00001fff
+#define RG_LPF4_31_I_MSK 0xffffe000
+#define RG_LPF4_31_SFT 0
+#define RG_LPF4_31_HI 12
+#define RG_LPF4_31_SZ 13
+#define RG_LPF4_32_MSK 0x00001fff
+#define RG_LPF4_32_I_MSK 0xffffe000
+#define RG_LPF4_32_SFT 0
+#define RG_LPF4_32_HI 12
+#define RG_LPF4_32_SZ 13
+#define RG_LPF4_33_MSK 0x00001fff
+#define RG_LPF4_33_I_MSK 0xffffe000
+#define RG_LPF4_33_SFT 0
+#define RG_LPF4_33_HI 12
+#define RG_LPF4_33_SZ 13
+#define RG_LPF4_34_MSK 0x00001fff
+#define RG_LPF4_34_I_MSK 0xffffe000
+#define RG_LPF4_34_SFT 0
+#define RG_LPF4_34_HI 12
+#define RG_LPF4_34_SZ 13
+#define RG_LPF4_35_MSK 0x00001fff
+#define RG_LPF4_35_I_MSK 0xffffe000
+#define RG_LPF4_35_SFT 0
+#define RG_LPF4_35_HI 12
+#define RG_LPF4_35_SZ 13
+#define RG_LPF4_36_MSK 0x00001fff
+#define RG_LPF4_36_I_MSK 0xffffe000
+#define RG_LPF4_36_SFT 0
+#define RG_LPF4_36_HI 12
+#define RG_LPF4_36_SZ 13
+#define RG_LPF4_37_MSK 0x00001fff
+#define RG_LPF4_37_I_MSK 0xffffe000
+#define RG_LPF4_37_SFT 0
+#define RG_LPF4_37_HI 12
+#define RG_LPF4_37_SZ 13
+#define RG_LPF4_38_MSK 0x00001fff
+#define RG_LPF4_38_I_MSK 0xffffe000
+#define RG_LPF4_38_SFT 0
+#define RG_LPF4_38_HI 12
+#define RG_LPF4_38_SZ 13
+#define RG_LPF4_39_MSK 0x00001fff
+#define RG_LPF4_39_I_MSK 0xffffe000
+#define RG_LPF4_39_SFT 0
+#define RG_LPF4_39_HI 12
+#define RG_LPF4_39_SZ 13
+#define RG_LPF4_40_MSK 0x00001fff
+#define RG_LPF4_40_I_MSK 0xffffe000
+#define RG_LPF4_40_SFT 0
+#define RG_LPF4_40_HI 12
+#define RG_LPF4_40_SZ 13
+#define RG_BP_SMB_MSK 0x00002000
+#define RG_BP_SMB_I_MSK 0xffffdfff
+#define RG_BP_SMB_SFT 13
+#define RG_BP_SMB_HI 13
+#define RG_BP_SMB_SZ 1
+#define RG_EN_SRVC_MSK 0x00004000
+#define RG_EN_SRVC_I_MSK 0xffffbfff
+#define RG_EN_SRVC_SFT 14
+#define RG_EN_SRVC_HI 14
+#define RG_EN_SRVC_SZ 1
+#define RG_DES_SPD_MSK 0x00030000
+#define RG_DES_SPD_I_MSK 0xfffcffff
+#define RG_DES_SPD_SFT 16
+#define RG_DES_SPD_HI 17
+#define RG_DES_SPD_SZ 2
+#define RG_BB_11B_RISE_TIME_MSK 0x000000ff
+#define RG_BB_11B_RISE_TIME_I_MSK 0xffffff00
+#define RG_BB_11B_RISE_TIME_SFT 0
+#define RG_BB_11B_RISE_TIME_HI 7
+#define RG_BB_11B_RISE_TIME_SZ 8
+#define RG_BB_11B_FALL_TIME_MSK 0x0000ff00
+#define RG_BB_11B_FALL_TIME_I_MSK 0xffff00ff
+#define RG_BB_11B_FALL_TIME_SFT 8
+#define RG_BB_11B_FALL_TIME_HI 15
+#define RG_BB_11B_FALL_TIME_SZ 8
+#define RG_WR_TX_EN_CNT_RST_N_MSK 0x00000001
+#define RG_WR_TX_EN_CNT_RST_N_I_MSK 0xfffffffe
+#define RG_WR_TX_EN_CNT_RST_N_SFT 0
+#define RG_WR_TX_EN_CNT_RST_N_HI 0
+#define RG_WR_TX_EN_CNT_RST_N_SZ 1
+#define RO_TX_EN_CNT_MSK 0x0000ffff
+#define RO_TX_EN_CNT_I_MSK 0xffff0000
+#define RO_TX_EN_CNT_SFT 0
+#define RO_TX_EN_CNT_HI 15
+#define RO_TX_EN_CNT_SZ 16
+#define RO_TX_CNT_MSK 0xffffffff
+#define RO_TX_CNT_I_MSK 0x00000000
+#define RO_TX_CNT_SFT 0
+#define RO_TX_CNT_HI 31
+#define RO_TX_CNT_SZ 32
+#define RG_POS_DES_11B_L_EXT_MSK 0x0000000f
+#define RG_POS_DES_11B_L_EXT_I_MSK 0xfffffff0
+#define RG_POS_DES_11B_L_EXT_SFT 0
+#define RG_POS_DES_11B_L_EXT_HI 3
+#define RG_POS_DES_11B_L_EXT_SZ 4
+#define RG_PRE_DES_11B_DLY_MSK 0x000000f0
+#define RG_PRE_DES_11B_DLY_I_MSK 0xffffff0f
+#define RG_PRE_DES_11B_DLY_SFT 4
+#define RG_PRE_DES_11B_DLY_HI 7
+#define RG_PRE_DES_11B_DLY_SZ 4
+#define RG_CNT_CCA_LMT_MSK 0x000f0000
+#define RG_CNT_CCA_LMT_I_MSK 0xfff0ffff
+#define RG_CNT_CCA_LMT_SFT 16
+#define RG_CNT_CCA_LMT_HI 19
+#define RG_CNT_CCA_LMT_SZ 4
+#define RG_BYPASS_DESCRAMBLER_MSK 0x20000000
+#define RG_BYPASS_DESCRAMBLER_I_MSK 0xdfffffff
+#define RG_BYPASS_DESCRAMBLER_SFT 29
+#define RG_BYPASS_DESCRAMBLER_HI 29
+#define RG_BYPASS_DESCRAMBLER_SZ 1
+#define RG_BYPASS_AGC_MSK 0x80000000
+#define RG_BYPASS_AGC_I_MSK 0x7fffffff
+#define RG_BYPASS_AGC_SFT 31
+#define RG_BYPASS_AGC_HI 31
+#define RG_BYPASS_AGC_SZ 1
+#define RG_CCA_BIT_CNT_LMT_RX_MSK 0x000000f0
+#define RG_CCA_BIT_CNT_LMT_RX_I_MSK 0xffffff0f
+#define RG_CCA_BIT_CNT_LMT_RX_SFT 4
+#define RG_CCA_BIT_CNT_LMT_RX_HI 7
+#define RG_CCA_BIT_CNT_LMT_RX_SZ 4
+#define RG_CCA_SCALE_BF_MSK 0x007f0000
+#define RG_CCA_SCALE_BF_I_MSK 0xff80ffff
+#define RG_CCA_SCALE_BF_SFT 16
+#define RG_CCA_SCALE_BF_HI 22
+#define RG_CCA_SCALE_BF_SZ 7
+#define RG_PEAK_IDX_CNT_SEL_MSK 0x30000000
+#define RG_PEAK_IDX_CNT_SEL_I_MSK 0xcfffffff
+#define RG_PEAK_IDX_CNT_SEL_SFT 28
+#define RG_PEAK_IDX_CNT_SEL_HI 29
+#define RG_PEAK_IDX_CNT_SEL_SZ 2
+#define RG_TR_KI_T2_MSK 0x00000007
+#define RG_TR_KI_T2_I_MSK 0xfffffff8
+#define RG_TR_KI_T2_SFT 0
+#define RG_TR_KI_T2_HI 2
+#define RG_TR_KI_T2_SZ 3
+#define RG_TR_KP_T2_MSK 0x00000070
+#define RG_TR_KP_T2_I_MSK 0xffffff8f
+#define RG_TR_KP_T2_SFT 4
+#define RG_TR_KP_T2_HI 6
+#define RG_TR_KP_T2_SZ 3
+#define RG_TR_KI_T1_MSK 0x00000700
+#define RG_TR_KI_T1_I_MSK 0xfffff8ff
+#define RG_TR_KI_T1_SFT 8
+#define RG_TR_KI_T1_HI 10
+#define RG_TR_KI_T1_SZ 3
+#define RG_TR_KP_T1_MSK 0x00007000
+#define RG_TR_KP_T1_I_MSK 0xffff8fff
+#define RG_TR_KP_T1_SFT 12
+#define RG_TR_KP_T1_HI 14
+#define RG_TR_KP_T1_SZ 3
+#define RG_CR_KI_T1_MSK 0x00070000
+#define RG_CR_KI_T1_I_MSK 0xfff8ffff
+#define RG_CR_KI_T1_SFT 16
+#define RG_CR_KI_T1_HI 18
+#define RG_CR_KI_T1_SZ 3
+#define RG_CR_KP_T1_MSK 0x00700000
+#define RG_CR_KP_T1_I_MSK 0xff8fffff
+#define RG_CR_KP_T1_SFT 20
+#define RG_CR_KP_T1_HI 22
+#define RG_CR_KP_T1_SZ 3
+#define RG_CHIP_CNT_SLICER_MSK 0x0000001f
+#define RG_CHIP_CNT_SLICER_I_MSK 0xffffffe0
+#define RG_CHIP_CNT_SLICER_SFT 0
+#define RG_CHIP_CNT_SLICER_HI 4
+#define RG_CHIP_CNT_SLICER_SZ 5
+#define RG_CE_T4_CNT_LMT_MSK 0x0000ff00
+#define RG_CE_T4_CNT_LMT_I_MSK 0xffff00ff
+#define RG_CE_T4_CNT_LMT_SFT 8
+#define RG_CE_T4_CNT_LMT_HI 15
+#define RG_CE_T4_CNT_LMT_SZ 8
+#define RG_CE_T3_CNT_LMT_MSK 0x00ff0000
+#define RG_CE_T3_CNT_LMT_I_MSK 0xff00ffff
+#define RG_CE_T3_CNT_LMT_SFT 16
+#define RG_CE_T3_CNT_LMT_HI 23
+#define RG_CE_T3_CNT_LMT_SZ 8
+#define RG_CE_T2_CNT_LMT_MSK 0xff000000
+#define RG_CE_T2_CNT_LMT_I_MSK 0x00ffffff
+#define RG_CE_T2_CNT_LMT_SFT 24
+#define RG_CE_T2_CNT_LMT_HI 31
+#define RG_CE_T2_CNT_LMT_SZ 8
+#define RG_CE_MU_T1_MSK 0x00000007
+#define RG_CE_MU_T1_I_MSK 0xfffffff8
+#define RG_CE_MU_T1_SFT 0
+#define RG_CE_MU_T1_HI 2
+#define RG_CE_MU_T1_SZ 3
+#define RG_CE_DLY_SEL_MSK 0x003f0000
+#define RG_CE_DLY_SEL_I_MSK 0xffc0ffff
+#define RG_CE_DLY_SEL_SFT 16
+#define RG_CE_DLY_SEL_HI 21
+#define RG_CE_DLY_SEL_SZ 6
+#define RG_CE_MU_T8_MSK 0x00000007
+#define RG_CE_MU_T8_I_MSK 0xfffffff8
+#define RG_CE_MU_T8_SFT 0
+#define RG_CE_MU_T8_HI 2
+#define RG_CE_MU_T8_SZ 3
+#define RG_CE_MU_T7_MSK 0x00000070
+#define RG_CE_MU_T7_I_MSK 0xffffff8f
+#define RG_CE_MU_T7_SFT 4
+#define RG_CE_MU_T7_HI 6
+#define RG_CE_MU_T7_SZ 3
+#define RG_CE_MU_T6_MSK 0x00000700
+#define RG_CE_MU_T6_I_MSK 0xfffff8ff
+#define RG_CE_MU_T6_SFT 8
+#define RG_CE_MU_T6_HI 10
+#define RG_CE_MU_T6_SZ 3
+#define RG_CE_MU_T5_MSK 0x00007000
+#define RG_CE_MU_T5_I_MSK 0xffff8fff
+#define RG_CE_MU_T5_SFT 12
+#define RG_CE_MU_T5_HI 14
+#define RG_CE_MU_T5_SZ 3
+#define RG_CE_MU_T4_MSK 0x00070000
+#define RG_CE_MU_T4_I_MSK 0xfff8ffff
+#define RG_CE_MU_T4_SFT 16
+#define RG_CE_MU_T4_HI 18
+#define RG_CE_MU_T4_SZ 3
+#define RG_CE_MU_T3_MSK 0x00700000
+#define RG_CE_MU_T3_I_MSK 0xff8fffff
+#define RG_CE_MU_T3_SFT 20
+#define RG_CE_MU_T3_HI 22
+#define RG_CE_MU_T3_SZ 3
+#define RG_CE_MU_T2_MSK 0x07000000
+#define RG_CE_MU_T2_I_MSK 0xf8ffffff
+#define RG_CE_MU_T2_SFT 24
+#define RG_CE_MU_T2_HI 26
+#define RG_CE_MU_T2_SZ 3
+#define RG_EQ_MU_FB_T2_MSK 0x0000000f
+#define RG_EQ_MU_FB_T2_I_MSK 0xfffffff0
+#define RG_EQ_MU_FB_T2_SFT 0
+#define RG_EQ_MU_FB_T2_HI 3
+#define RG_EQ_MU_FB_T2_SZ 4
+#define RG_EQ_MU_FF_T2_MSK 0x000000f0
+#define RG_EQ_MU_FF_T2_I_MSK 0xffffff0f
+#define RG_EQ_MU_FF_T2_SFT 4
+#define RG_EQ_MU_FF_T2_HI 7
+#define RG_EQ_MU_FF_T2_SZ 4
+#define RG_EQ_MU_FB_T1_MSK 0x000f0000
+#define RG_EQ_MU_FB_T1_I_MSK 0xfff0ffff
+#define RG_EQ_MU_FB_T1_SFT 16
+#define RG_EQ_MU_FB_T1_HI 19
+#define RG_EQ_MU_FB_T1_SZ 4
+#define RG_EQ_MU_FF_T1_MSK 0x00f00000
+#define RG_EQ_MU_FF_T1_I_MSK 0xff0fffff
+#define RG_EQ_MU_FF_T1_SFT 20
+#define RG_EQ_MU_FF_T1_HI 23
+#define RG_EQ_MU_FF_T1_SZ 4
+#define RG_EQ_MU_FB_T4_MSK 0x0000000f
+#define RG_EQ_MU_FB_T4_I_MSK 0xfffffff0
+#define RG_EQ_MU_FB_T4_SFT 0
+#define RG_EQ_MU_FB_T4_HI 3
+#define RG_EQ_MU_FB_T4_SZ 4
+#define RG_EQ_MU_FF_T4_MSK 0x000000f0
+#define RG_EQ_MU_FF_T4_I_MSK 0xffffff0f
+#define RG_EQ_MU_FF_T4_SFT 4
+#define RG_EQ_MU_FF_T4_HI 7
+#define RG_EQ_MU_FF_T4_SZ 4
+#define RG_EQ_MU_FB_T3_MSK 0x000f0000
+#define RG_EQ_MU_FB_T3_I_MSK 0xfff0ffff
+#define RG_EQ_MU_FB_T3_SFT 16
+#define RG_EQ_MU_FB_T3_HI 19
+#define RG_EQ_MU_FB_T3_SZ 4
+#define RG_EQ_MU_FF_T3_MSK 0x00f00000
+#define RG_EQ_MU_FF_T3_I_MSK 0xff0fffff
+#define RG_EQ_MU_FF_T3_SFT 20
+#define RG_EQ_MU_FF_T3_HI 23
+#define RG_EQ_MU_FF_T3_SZ 4
+#define RG_EQ_KI_T2_MSK 0x00000700
+#define RG_EQ_KI_T2_I_MSK 0xfffff8ff
+#define RG_EQ_KI_T2_SFT 8
+#define RG_EQ_KI_T2_HI 10
+#define RG_EQ_KI_T2_SZ 3
+#define RG_EQ_KP_T2_MSK 0x00007000
+#define RG_EQ_KP_T2_I_MSK 0xffff8fff
+#define RG_EQ_KP_T2_SFT 12
+#define RG_EQ_KP_T2_HI 14
+#define RG_EQ_KP_T2_SZ 3
+#define RG_EQ_KI_T1_MSK 0x00070000
+#define RG_EQ_KI_T1_I_MSK 0xfff8ffff
+#define RG_EQ_KI_T1_SFT 16
+#define RG_EQ_KI_T1_HI 18
+#define RG_EQ_KI_T1_SZ 3
+#define RG_EQ_KP_T1_MSK 0x00700000
+#define RG_EQ_KP_T1_I_MSK 0xff8fffff
+#define RG_EQ_KP_T1_SFT 20
+#define RG_EQ_KP_T1_HI 22
+#define RG_EQ_KP_T1_SZ 3
+#define RG_TR_LPF_RATE_MSK 0x003fffff
+#define RG_TR_LPF_RATE_I_MSK 0xffc00000
+#define RG_TR_LPF_RATE_SFT 0
+#define RG_TR_LPF_RATE_HI 21
+#define RG_TR_LPF_RATE_SZ 22
+#define RG_CE_BIT_CNT_LMT_MSK 0x0000007f
+#define RG_CE_BIT_CNT_LMT_I_MSK 0xffffff80
+#define RG_CE_BIT_CNT_LMT_SFT 0
+#define RG_CE_BIT_CNT_LMT_HI 6
+#define RG_CE_BIT_CNT_LMT_SZ 7
+#define RG_CE_CH_MAIN_SET_MSK 0x00000080
+#define RG_CE_CH_MAIN_SET_I_MSK 0xffffff7f
+#define RG_CE_CH_MAIN_SET_SFT 7
+#define RG_CE_CH_MAIN_SET_HI 7
+#define RG_CE_CH_MAIN_SET_SZ 1
+#define RG_TC_BIT_CNT_LMT_MSK 0x00007f00
+#define RG_TC_BIT_CNT_LMT_I_MSK 0xffff80ff
+#define RG_TC_BIT_CNT_LMT_SFT 8
+#define RG_TC_BIT_CNT_LMT_HI 14
+#define RG_TC_BIT_CNT_LMT_SZ 7
+#define RG_CR_BIT_CNT_LMT_MSK 0x007f0000
+#define RG_CR_BIT_CNT_LMT_I_MSK 0xff80ffff
+#define RG_CR_BIT_CNT_LMT_SFT 16
+#define RG_CR_BIT_CNT_LMT_HI 22
+#define RG_CR_BIT_CNT_LMT_SZ 7
+#define RG_TR_BIT_CNT_LMT_MSK 0x7f000000
+#define RG_TR_BIT_CNT_LMT_I_MSK 0x80ffffff
+#define RG_TR_BIT_CNT_LMT_SFT 24
+#define RG_TR_BIT_CNT_LMT_HI 30
+#define RG_TR_BIT_CNT_LMT_SZ 7
+#define RG_EQ_MAIN_TAP_MAN_MSK 0x00000001
+#define RG_EQ_MAIN_TAP_MAN_I_MSK 0xfffffffe
+#define RG_EQ_MAIN_TAP_MAN_SFT 0
+#define RG_EQ_MAIN_TAP_MAN_HI 0
+#define RG_EQ_MAIN_TAP_MAN_SZ 1
+#define RG_EQ_MAIN_TAP_COEF_MSK 0x07ff0000
+#define RG_EQ_MAIN_TAP_COEF_I_MSK 0xf800ffff
+#define RG_EQ_MAIN_TAP_COEF_SFT 16
+#define RG_EQ_MAIN_TAP_COEF_HI 26
+#define RG_EQ_MAIN_TAP_COEF_SZ 11
+#define RG_PWRON_DLY_TH_11B_MSK 0x000000ff
+#define RG_PWRON_DLY_TH_11B_I_MSK 0xffffff00
+#define RG_PWRON_DLY_TH_11B_SFT 0
+#define RG_PWRON_DLY_TH_11B_HI 7
+#define RG_PWRON_DLY_TH_11B_SZ 8
+#define RG_SFD_BIT_CNT_LMT_MSK 0x00ff0000
+#define RG_SFD_BIT_CNT_LMT_I_MSK 0xff00ffff
+#define RG_SFD_BIT_CNT_LMT_SFT 16
+#define RG_SFD_BIT_CNT_LMT_HI 23
+#define RG_SFD_BIT_CNT_LMT_SZ 8
+#define RG_CCA_PWR_TH_RX_MSK 0x00007fff
+#define RG_CCA_PWR_TH_RX_I_MSK 0xffff8000
+#define RG_CCA_PWR_TH_RX_SFT 0
+#define RG_CCA_PWR_TH_RX_HI 14
+#define RG_CCA_PWR_TH_RX_SZ 15
+#define RG_CCA_PWR_CNT_TH_MSK 0x001f0000
+#define RG_CCA_PWR_CNT_TH_I_MSK 0xffe0ffff
+#define RG_CCA_PWR_CNT_TH_SFT 16
+#define RG_CCA_PWR_CNT_TH_HI 20
+#define RG_CCA_PWR_CNT_TH_SZ 5
+#define B_FREQ_OS_MSK 0x000007ff
+#define B_FREQ_OS_I_MSK 0xfffff800
+#define B_FREQ_OS_SFT 0
+#define B_FREQ_OS_HI 10
+#define B_FREQ_OS_SZ 11
+#define B_SNR_MSK 0x0000007f
+#define B_SNR_I_MSK 0xffffff80
+#define B_SNR_SFT 0
+#define B_SNR_HI 6
+#define B_SNR_SZ 7
+#define B_RCPI_MSK 0x007f0000
+#define B_RCPI_I_MSK 0xff80ffff
+#define B_RCPI_SFT 16
+#define B_RCPI_HI 22
+#define B_RCPI_SZ 7
+#define CRC_CNT_MSK 0x0000ffff
+#define CRC_CNT_I_MSK 0xffff0000
+#define CRC_CNT_SFT 0
+#define CRC_CNT_HI 15
+#define CRC_CNT_SZ 16
+#define SFD_CNT_MSK 0xffff0000
+#define SFD_CNT_I_MSK 0x0000ffff
+#define SFD_CNT_SFT 16
+#define SFD_CNT_HI 31
+#define SFD_CNT_SZ 16
+#define B_PACKET_ERR_CNT_MSK 0x0000ffff
+#define B_PACKET_ERR_CNT_I_MSK 0xffff0000
+#define B_PACKET_ERR_CNT_SFT 0
+#define B_PACKET_ERR_CNT_HI 15
+#define B_PACKET_ERR_CNT_SZ 16
+#define PACKET_ERR_MSK 0x00010000
+#define PACKET_ERR_I_MSK 0xfffeffff
+#define PACKET_ERR_SFT 16
+#define PACKET_ERR_HI 16
+#define PACKET_ERR_SZ 1
+#define B_PACKET_CNT_MSK 0x0000ffff
+#define B_PACKET_CNT_I_MSK 0xffff0000
+#define B_PACKET_CNT_SFT 0
+#define B_PACKET_CNT_HI 15
+#define B_PACKET_CNT_SZ 16
+#define B_CCA_CNT_MSK 0xffff0000
+#define B_CCA_CNT_I_MSK 0x0000ffff
+#define B_CCA_CNT_SFT 16
+#define B_CCA_CNT_HI 31
+#define B_CCA_CNT_SZ 16
+#define B_LENGTH_FIELD_MSK 0x0000ffff
+#define B_LENGTH_FIELD_I_MSK 0xffff0000
+#define B_LENGTH_FIELD_SFT 0
+#define B_LENGTH_FIELD_HI 15
+#define B_LENGTH_FIELD_SZ 16
+#define SFD_FIELD_MSK 0xffff0000
+#define SFD_FIELD_I_MSK 0x0000ffff
+#define SFD_FIELD_SFT 16
+#define SFD_FIELD_HI 31
+#define SFD_FIELD_SZ 16
+#define SIGNAL_FIELD_MSK 0x000000ff
+#define SIGNAL_FIELD_I_MSK 0xffffff00
+#define SIGNAL_FIELD_SFT 0
+#define SIGNAL_FIELD_HI 7
+#define SIGNAL_FIELD_SZ 8
+#define B_SERVICE_FIELD_MSK 0x0000ff00
+#define B_SERVICE_FIELD_I_MSK 0xffff00ff
+#define B_SERVICE_FIELD_SFT 8
+#define B_SERVICE_FIELD_HI 15
+#define B_SERVICE_FIELD_SZ 8
+#define CRC_CORRECT_MSK 0x00010000
+#define CRC_CORRECT_I_MSK 0xfffeffff
+#define CRC_CORRECT_SFT 16
+#define CRC_CORRECT_HI 16
+#define CRC_CORRECT_SZ 1
+#define DEBUG_SEL_MSK 0x0000000f
+#define DEBUG_SEL_I_MSK 0xfffffff0
+#define DEBUG_SEL_SFT 0
+#define DEBUG_SEL_HI 3
+#define DEBUG_SEL_SZ 4
+#define RG_PACKET_STAT_EN_11B_MSK 0x00100000
+#define RG_PACKET_STAT_EN_11B_I_MSK 0xffefffff
+#define RG_PACKET_STAT_EN_11B_SFT 20
+#define RG_PACKET_STAT_EN_11B_HI 20
+#define RG_PACKET_STAT_EN_11B_SZ 1
+#define RG_BIT_REVERSE_MSK 0x00200000
+#define RG_BIT_REVERSE_I_MSK 0xffdfffff
+#define RG_BIT_REVERSE_SFT 21
+#define RG_BIT_REVERSE_HI 21
+#define RG_BIT_REVERSE_SZ 1
+#define RX_PHY_11B_SOFT_RST_N_MSK 0x00000001
+#define RX_PHY_11B_SOFT_RST_N_I_MSK 0xfffffffe
+#define RX_PHY_11B_SOFT_RST_N_SFT 0
+#define RX_PHY_11B_SOFT_RST_N_HI 0
+#define RX_PHY_11B_SOFT_RST_N_SZ 1
+#define RG_CE_BYPASS_TAP_MSK 0x000000f0
+#define RG_CE_BYPASS_TAP_I_MSK 0xffffff0f
+#define RG_CE_BYPASS_TAP_SFT 4
+#define RG_CE_BYPASS_TAP_HI 7
+#define RG_CE_BYPASS_TAP_SZ 4
+#define RG_EQ_BYPASS_FBW_TAP_MSK 0x00000f00
+#define RG_EQ_BYPASS_FBW_TAP_I_MSK 0xfffff0ff
+#define RG_EQ_BYPASS_FBW_TAP_SFT 8
+#define RG_EQ_BYPASS_FBW_TAP_HI 11
+#define RG_EQ_BYPASS_FBW_TAP_SZ 4
+#define RG_BB_11GN_RISE_TIME_MSK 0x000000ff
+#define RG_BB_11GN_RISE_TIME_I_MSK 0xffffff00
+#define RG_BB_11GN_RISE_TIME_SFT 0
+#define RG_BB_11GN_RISE_TIME_HI 7
+#define RG_BB_11GN_RISE_TIME_SZ 8
+#define RG_BB_11GN_FALL_TIME_MSK 0x0000ff00
+#define RG_BB_11GN_FALL_TIME_I_MSK 0xffff00ff
+#define RG_BB_11GN_FALL_TIME_SFT 8
+#define RG_BB_11GN_FALL_TIME_HI 15
+#define RG_BB_11GN_FALL_TIME_SZ 8
+#define RG_HTCARR52_FFT_SCALE_MSK 0x000003ff
+#define RG_HTCARR52_FFT_SCALE_I_MSK 0xfffffc00
+#define RG_HTCARR52_FFT_SCALE_SFT 0
+#define RG_HTCARR52_FFT_SCALE_HI 9
+#define RG_HTCARR52_FFT_SCALE_SZ 10
+#define RG_HTCARR56_FFT_SCALE_MSK 0x003ff000
+#define RG_HTCARR56_FFT_SCALE_I_MSK 0xffc00fff
+#define RG_HTCARR56_FFT_SCALE_SFT 12
+#define RG_HTCARR56_FFT_SCALE_HI 21
+#define RG_HTCARR56_FFT_SCALE_SZ 10
+#define RG_PACKET_STAT_EN_MSK 0x00800000
+#define RG_PACKET_STAT_EN_I_MSK 0xff7fffff
+#define RG_PACKET_STAT_EN_SFT 23
+#define RG_PACKET_STAT_EN_HI 23
+#define RG_PACKET_STAT_EN_SZ 1
+#define RG_SMB_DEF_MSK 0x7f000000
+#define RG_SMB_DEF_I_MSK 0x80ffffff
+#define RG_SMB_DEF_SFT 24
+#define RG_SMB_DEF_HI 30
+#define RG_SMB_DEF_SZ 7
+#define RG_CONTINUOUS_DATA_11GN_MSK 0x80000000
+#define RG_CONTINUOUS_DATA_11GN_I_MSK 0x7fffffff
+#define RG_CONTINUOUS_DATA_11GN_SFT 31
+#define RG_CONTINUOUS_DATA_11GN_HI 31
+#define RG_CONTINUOUS_DATA_11GN_SZ 1
+#define RO_TX_CNT_R_MSK 0xffffffff
+#define RO_TX_CNT_R_I_MSK 0x00000000
+#define RO_TX_CNT_R_SFT 0
+#define RO_TX_CNT_R_HI 31
+#define RO_TX_CNT_R_SZ 32
+#define RO_PACKET_ERR_CNT_MSK 0x0000ffff
+#define RO_PACKET_ERR_CNT_I_MSK 0xffff0000
+#define RO_PACKET_ERR_CNT_SFT 0
+#define RO_PACKET_ERR_CNT_HI 15
+#define RO_PACKET_ERR_CNT_SZ 16
+#define RG_POS_DES_11GN_L_EXT_MSK 0x0000000f
+#define RG_POS_DES_11GN_L_EXT_I_MSK 0xfffffff0
+#define RG_POS_DES_11GN_L_EXT_SFT 0
+#define RG_POS_DES_11GN_L_EXT_HI 3
+#define RG_POS_DES_11GN_L_EXT_SZ 4
+#define RG_PRE_DES_11GN_DLY_MSK 0x000000f0
+#define RG_PRE_DES_11GN_DLY_I_MSK 0xffffff0f
+#define RG_PRE_DES_11GN_DLY_SFT 4
+#define RG_PRE_DES_11GN_DLY_HI 7
+#define RG_PRE_DES_11GN_DLY_SZ 4
+#define RG_TR_LPF_KI_G_T1_MSK 0x0000000f
+#define RG_TR_LPF_KI_G_T1_I_MSK 0xfffffff0
+#define RG_TR_LPF_KI_G_T1_SFT 0
+#define RG_TR_LPF_KI_G_T1_HI 3
+#define RG_TR_LPF_KI_G_T1_SZ 4
+#define RG_TR_LPF_KP_G_T1_MSK 0x000000f0
+#define RG_TR_LPF_KP_G_T1_I_MSK 0xffffff0f
+#define RG_TR_LPF_KP_G_T1_SFT 4
+#define RG_TR_LPF_KP_G_T1_HI 7
+#define RG_TR_LPF_KP_G_T1_SZ 4
+#define RG_TR_CNT_T1_MSK 0x0000ff00
+#define RG_TR_CNT_T1_I_MSK 0xffff00ff
+#define RG_TR_CNT_T1_SFT 8
+#define RG_TR_CNT_T1_HI 15
+#define RG_TR_CNT_T1_SZ 8
+#define RG_TR_LPF_KI_G_T0_MSK 0x000f0000
+#define RG_TR_LPF_KI_G_T0_I_MSK 0xfff0ffff
+#define RG_TR_LPF_KI_G_T0_SFT 16
+#define RG_TR_LPF_KI_G_T0_HI 19
+#define RG_TR_LPF_KI_G_T0_SZ 4
+#define RG_TR_LPF_KP_G_T0_MSK 0x00f00000
+#define RG_TR_LPF_KP_G_T0_I_MSK 0xff0fffff
+#define RG_TR_LPF_KP_G_T0_SFT 20
+#define RG_TR_LPF_KP_G_T0_HI 23
+#define RG_TR_LPF_KP_G_T0_SZ 4
+#define RG_TR_CNT_T0_MSK 0xff000000
+#define RG_TR_CNT_T0_I_MSK 0x00ffffff
+#define RG_TR_CNT_T0_SFT 24
+#define RG_TR_CNT_T0_HI 31
+#define RG_TR_CNT_T0_SZ 8
+#define RG_TR_LPF_KI_G_T2_MSK 0x0000000f
+#define RG_TR_LPF_KI_G_T2_I_MSK 0xfffffff0
+#define RG_TR_LPF_KI_G_T2_SFT 0
+#define RG_TR_LPF_KI_G_T2_HI 3
+#define RG_TR_LPF_KI_G_T2_SZ 4
+#define RG_TR_LPF_KP_G_T2_MSK 0x000000f0
+#define RG_TR_LPF_KP_G_T2_I_MSK 0xffffff0f
+#define RG_TR_LPF_KP_G_T2_SFT 4
+#define RG_TR_LPF_KP_G_T2_HI 7
+#define RG_TR_LPF_KP_G_T2_SZ 4
+#define RG_TR_CNT_T2_MSK 0x0000ff00
+#define RG_TR_CNT_T2_I_MSK 0xffff00ff
+#define RG_TR_CNT_T2_SFT 8
+#define RG_TR_CNT_T2_HI 15
+#define RG_TR_CNT_T2_SZ 8
+#define RG_TR_LPF_KI_G_MSK 0x0000000f
+#define RG_TR_LPF_KI_G_I_MSK 0xfffffff0
+#define RG_TR_LPF_KI_G_SFT 0
+#define RG_TR_LPF_KI_G_HI 3
+#define RG_TR_LPF_KI_G_SZ 4
+#define RG_TR_LPF_KP_G_MSK 0x000000f0
+#define RG_TR_LPF_KP_G_I_MSK 0xffffff0f
+#define RG_TR_LPF_KP_G_SFT 4
+#define RG_TR_LPF_KP_G_HI 7
+#define RG_TR_LPF_KP_G_SZ 4
+#define RG_TR_LPF_RATE_G_MSK 0x3fffff00
+#define RG_TR_LPF_RATE_G_I_MSK 0xc00000ff
+#define RG_TR_LPF_RATE_G_SFT 8
+#define RG_TR_LPF_RATE_G_HI 29
+#define RG_TR_LPF_RATE_G_SZ 22
+#define RG_CR_LPF_KI_G_MSK 0x00000007
+#define RG_CR_LPF_KI_G_I_MSK 0xfffffff8
+#define RG_CR_LPF_KI_G_SFT 0
+#define RG_CR_LPF_KI_G_HI 2
+#define RG_CR_LPF_KI_G_SZ 3
+#define RG_SYM_BOUND_CNT_MSK 0x00007f00
+#define RG_SYM_BOUND_CNT_I_MSK 0xffff80ff
+#define RG_SYM_BOUND_CNT_SFT 8
+#define RG_SYM_BOUND_CNT_HI 14
+#define RG_SYM_BOUND_CNT_SZ 7
+#define RG_XSCOR32_RATIO_MSK 0x007f0000
+#define RG_XSCOR32_RATIO_I_MSK 0xff80ffff
+#define RG_XSCOR32_RATIO_SFT 16
+#define RG_XSCOR32_RATIO_HI 22
+#define RG_XSCOR32_RATIO_SZ 7
+#define RG_ATCOR64_CNT_LMT_MSK 0x7f000000
+#define RG_ATCOR64_CNT_LMT_I_MSK 0x80ffffff
+#define RG_ATCOR64_CNT_LMT_SFT 24
+#define RG_ATCOR64_CNT_LMT_HI 30
+#define RG_ATCOR64_CNT_LMT_SZ 7
+#define RG_ATCOR16_CNT_LMT2_MSK 0x00007f00
+#define RG_ATCOR16_CNT_LMT2_I_MSK 0xffff80ff
+#define RG_ATCOR16_CNT_LMT2_SFT 8
+#define RG_ATCOR16_CNT_LMT2_HI 14
+#define RG_ATCOR16_CNT_LMT2_SZ 7
+#define RG_ATCOR16_CNT_LMT1_MSK 0x007f0000
+#define RG_ATCOR16_CNT_LMT1_I_MSK 0xff80ffff
+#define RG_ATCOR16_CNT_LMT1_SFT 16
+#define RG_ATCOR16_CNT_LMT1_HI 22
+#define RG_ATCOR16_CNT_LMT1_SZ 7
+#define RG_ATCOR16_RATIO_SB_MSK 0x7f000000
+#define RG_ATCOR16_RATIO_SB_I_MSK 0x80ffffff
+#define RG_ATCOR16_RATIO_SB_SFT 24
+#define RG_ATCOR16_RATIO_SB_HI 30
+#define RG_ATCOR16_RATIO_SB_SZ 7
+#define RG_XSCOR64_CNT_LMT2_MSK 0x007f0000
+#define RG_XSCOR64_CNT_LMT2_I_MSK 0xff80ffff
+#define RG_XSCOR64_CNT_LMT2_SFT 16
+#define RG_XSCOR64_CNT_LMT2_HI 22
+#define RG_XSCOR64_CNT_LMT2_SZ 7
+#define RG_XSCOR64_CNT_LMT1_MSK 0x7f000000
+#define RG_XSCOR64_CNT_LMT1_I_MSK 0x80ffffff
+#define RG_XSCOR64_CNT_LMT1_SFT 24
+#define RG_XSCOR64_CNT_LMT1_HI 30
+#define RG_XSCOR64_CNT_LMT1_SZ 7
+#define RG_RX_FFT_SCALE_MSK 0x000003ff
+#define RG_RX_FFT_SCALE_I_MSK 0xfffffc00
+#define RG_RX_FFT_SCALE_SFT 0
+#define RG_RX_FFT_SCALE_HI 9
+#define RG_RX_FFT_SCALE_SZ 10
+#define RG_VITERBI_AB_SWAP_MSK 0x00010000
+#define RG_VITERBI_AB_SWAP_I_MSK 0xfffeffff
+#define RG_VITERBI_AB_SWAP_SFT 16
+#define RG_VITERBI_AB_SWAP_HI 16
+#define RG_VITERBI_AB_SWAP_SZ 1
+#define RG_ATCOR16_CNT_TH_MSK 0x0f000000
+#define RG_ATCOR16_CNT_TH_I_MSK 0xf0ffffff
+#define RG_ATCOR16_CNT_TH_SFT 24
+#define RG_ATCOR16_CNT_TH_HI 27
+#define RG_ATCOR16_CNT_TH_SZ 4
+#define RG_NORMSQUARE_LOW_SNR_7_MSK 0x000000ff
+#define RG_NORMSQUARE_LOW_SNR_7_I_MSK 0xffffff00
+#define RG_NORMSQUARE_LOW_SNR_7_SFT 0
+#define RG_NORMSQUARE_LOW_SNR_7_HI 7
+#define RG_NORMSQUARE_LOW_SNR_7_SZ 8
+#define RG_NORMSQUARE_LOW_SNR_6_MSK 0x0000ff00
+#define RG_NORMSQUARE_LOW_SNR_6_I_MSK 0xffff00ff
+#define RG_NORMSQUARE_LOW_SNR_6_SFT 8
+#define RG_NORMSQUARE_LOW_SNR_6_HI 15
+#define RG_NORMSQUARE_LOW_SNR_6_SZ 8
+#define RG_NORMSQUARE_LOW_SNR_5_MSK 0x00ff0000
+#define RG_NORMSQUARE_LOW_SNR_5_I_MSK 0xff00ffff
+#define RG_NORMSQUARE_LOW_SNR_5_SFT 16
+#define RG_NORMSQUARE_LOW_SNR_5_HI 23
+#define RG_NORMSQUARE_LOW_SNR_5_SZ 8
+#define RG_NORMSQUARE_LOW_SNR_4_MSK 0xff000000
+#define RG_NORMSQUARE_LOW_SNR_4_I_MSK 0x00ffffff
+#define RG_NORMSQUARE_LOW_SNR_4_SFT 24
+#define RG_NORMSQUARE_LOW_SNR_4_HI 31
+#define RG_NORMSQUARE_LOW_SNR_4_SZ 8
+#define RG_NORMSQUARE_LOW_SNR_8_MSK 0xff000000
+#define RG_NORMSQUARE_LOW_SNR_8_I_MSK 0x00ffffff
+#define RG_NORMSQUARE_LOW_SNR_8_SFT 24
+#define RG_NORMSQUARE_LOW_SNR_8_HI 31
+#define RG_NORMSQUARE_LOW_SNR_8_SZ 8
+#define RG_NORMSQUARE_SNR_3_MSK 0x000000ff
+#define RG_NORMSQUARE_SNR_3_I_MSK 0xffffff00
+#define RG_NORMSQUARE_SNR_3_SFT 0
+#define RG_NORMSQUARE_SNR_3_HI 7
+#define RG_NORMSQUARE_SNR_3_SZ 8
+#define RG_NORMSQUARE_SNR_2_MSK 0x0000ff00
+#define RG_NORMSQUARE_SNR_2_I_MSK 0xffff00ff
+#define RG_NORMSQUARE_SNR_2_SFT 8
+#define RG_NORMSQUARE_SNR_2_HI 15
+#define RG_NORMSQUARE_SNR_2_SZ 8
+#define RG_NORMSQUARE_SNR_1_MSK 0x00ff0000
+#define RG_NORMSQUARE_SNR_1_I_MSK 0xff00ffff
+#define RG_NORMSQUARE_SNR_1_SFT 16
+#define RG_NORMSQUARE_SNR_1_HI 23
+#define RG_NORMSQUARE_SNR_1_SZ 8
+#define RG_NORMSQUARE_SNR_0_MSK 0xff000000
+#define RG_NORMSQUARE_SNR_0_I_MSK 0x00ffffff
+#define RG_NORMSQUARE_SNR_0_SFT 24
+#define RG_NORMSQUARE_SNR_0_HI 31
+#define RG_NORMSQUARE_SNR_0_SZ 8
+#define RG_NORMSQUARE_SNR_7_MSK 0x000000ff
+#define RG_NORMSQUARE_SNR_7_I_MSK 0xffffff00
+#define RG_NORMSQUARE_SNR_7_SFT 0
+#define RG_NORMSQUARE_SNR_7_HI 7
+#define RG_NORMSQUARE_SNR_7_SZ 8
+#define RG_NORMSQUARE_SNR_6_MSK 0x0000ff00
+#define RG_NORMSQUARE_SNR_6_I_MSK 0xffff00ff
+#define RG_NORMSQUARE_SNR_6_SFT 8
+#define RG_NORMSQUARE_SNR_6_HI 15
+#define RG_NORMSQUARE_SNR_6_SZ 8
+#define RG_NORMSQUARE_SNR_5_MSK 0x00ff0000
+#define RG_NORMSQUARE_SNR_5_I_MSK 0xff00ffff
+#define RG_NORMSQUARE_SNR_5_SFT 16
+#define RG_NORMSQUARE_SNR_5_HI 23
+#define RG_NORMSQUARE_SNR_5_SZ 8
+#define RG_NORMSQUARE_SNR_4_MSK 0xff000000
+#define RG_NORMSQUARE_SNR_4_I_MSK 0x00ffffff
+#define RG_NORMSQUARE_SNR_4_SFT 24
+#define RG_NORMSQUARE_SNR_4_HI 31
+#define RG_NORMSQUARE_SNR_4_SZ 8
+#define RG_NORMSQUARE_SNR_8_MSK 0xff000000
+#define RG_NORMSQUARE_SNR_8_I_MSK 0x00ffffff
+#define RG_NORMSQUARE_SNR_8_SFT 24
+#define RG_NORMSQUARE_SNR_8_HI 31
+#define RG_NORMSQUARE_SNR_8_SZ 8
+#define RG_SNR_TH_64QAM_MSK 0x0000007f
+#define RG_SNR_TH_64QAM_I_MSK 0xffffff80
+#define RG_SNR_TH_64QAM_SFT 0
+#define RG_SNR_TH_64QAM_HI 6
+#define RG_SNR_TH_64QAM_SZ 7
+#define RG_SNR_TH_16QAM_MSK 0x00007f00
+#define RG_SNR_TH_16QAM_I_MSK 0xffff80ff
+#define RG_SNR_TH_16QAM_SFT 8
+#define RG_SNR_TH_16QAM_HI 14
+#define RG_SNR_TH_16QAM_SZ 7
+#define RG_ATCOR16_CNT_PLUS_LMT2_MSK 0x0000007f
+#define RG_ATCOR16_CNT_PLUS_LMT2_I_MSK 0xffffff80
+#define RG_ATCOR16_CNT_PLUS_LMT2_SFT 0
+#define RG_ATCOR16_CNT_PLUS_LMT2_HI 6
+#define RG_ATCOR16_CNT_PLUS_LMT2_SZ 7
+#define RG_ATCOR16_CNT_PLUS_LMT1_MSK 0x00007f00
+#define RG_ATCOR16_CNT_PLUS_LMT1_I_MSK 0xffff80ff
+#define RG_ATCOR16_CNT_PLUS_LMT1_SFT 8
+#define RG_ATCOR16_CNT_PLUS_LMT1_HI 14
+#define RG_ATCOR16_CNT_PLUS_LMT1_SZ 7
+#define RG_SYM_BOUND_METHOD_MSK 0x00030000
+#define RG_SYM_BOUND_METHOD_I_MSK 0xfffcffff
+#define RG_SYM_BOUND_METHOD_SFT 16
+#define RG_SYM_BOUND_METHOD_HI 17
+#define RG_SYM_BOUND_METHOD_SZ 2
+#define RG_PWRON_DLY_TH_11GN_MSK 0x000000ff
+#define RG_PWRON_DLY_TH_11GN_I_MSK 0xffffff00
+#define RG_PWRON_DLY_TH_11GN_SFT 0
+#define RG_PWRON_DLY_TH_11GN_HI 7
+#define RG_PWRON_DLY_TH_11GN_SZ 8
+#define RG_SB_START_CNT_MSK 0x00007f00
+#define RG_SB_START_CNT_I_MSK 0xffff80ff
+#define RG_SB_START_CNT_SFT 8
+#define RG_SB_START_CNT_HI 14
+#define RG_SB_START_CNT_SZ 7
+#define RG_POW16_CNT_TH_MSK 0x000000f0
+#define RG_POW16_CNT_TH_I_MSK 0xffffff0f
+#define RG_POW16_CNT_TH_SFT 4
+#define RG_POW16_CNT_TH_HI 7
+#define RG_POW16_CNT_TH_SZ 4
+#define RG_POW16_SHORT_CNT_LMT_MSK 0x00000700
+#define RG_POW16_SHORT_CNT_LMT_I_MSK 0xfffff8ff
+#define RG_POW16_SHORT_CNT_LMT_SFT 8
+#define RG_POW16_SHORT_CNT_LMT_HI 10
+#define RG_POW16_SHORT_CNT_LMT_SZ 3
+#define RG_POW16_TH_L_MSK 0x7f000000
+#define RG_POW16_TH_L_I_MSK 0x80ffffff
+#define RG_POW16_TH_L_SFT 24
+#define RG_POW16_TH_L_HI 30
+#define RG_POW16_TH_L_SZ 7
+#define RG_XSCOR16_SHORT_CNT_LMT_MSK 0x00000007
+#define RG_XSCOR16_SHORT_CNT_LMT_I_MSK 0xfffffff8
+#define RG_XSCOR16_SHORT_CNT_LMT_SFT 0
+#define RG_XSCOR16_SHORT_CNT_LMT_HI 2
+#define RG_XSCOR16_SHORT_CNT_LMT_SZ 3
+#define RG_XSCOR16_RATIO_MSK 0x00007f00
+#define RG_XSCOR16_RATIO_I_MSK 0xffff80ff
+#define RG_XSCOR16_RATIO_SFT 8
+#define RG_XSCOR16_RATIO_HI 14
+#define RG_XSCOR16_RATIO_SZ 7
+#define RG_ATCOR16_SHORT_CNT_LMT_MSK 0x00070000
+#define RG_ATCOR16_SHORT_CNT_LMT_I_MSK 0xfff8ffff
+#define RG_ATCOR16_SHORT_CNT_LMT_SFT 16
+#define RG_ATCOR16_SHORT_CNT_LMT_HI 18
+#define RG_ATCOR16_SHORT_CNT_LMT_SZ 3
+#define RG_ATCOR16_RATIO_CCD_MSK 0x7f000000
+#define RG_ATCOR16_RATIO_CCD_I_MSK 0x80ffffff
+#define RG_ATCOR16_RATIO_CCD_SFT 24
+#define RG_ATCOR16_RATIO_CCD_HI 30
+#define RG_ATCOR16_RATIO_CCD_SZ 7
+#define RG_ATCOR64_ACC_LMT_MSK 0x0000007f
+#define RG_ATCOR64_ACC_LMT_I_MSK 0xffffff80
+#define RG_ATCOR64_ACC_LMT_SFT 0
+#define RG_ATCOR64_ACC_LMT_HI 6
+#define RG_ATCOR64_ACC_LMT_SZ 7
+#define RG_ATCOR16_SHORT_CNT_LMT2_MSK 0x00070000
+#define RG_ATCOR16_SHORT_CNT_LMT2_I_MSK 0xfff8ffff
+#define RG_ATCOR16_SHORT_CNT_LMT2_SFT 16
+#define RG_ATCOR16_SHORT_CNT_LMT2_HI 18
+#define RG_ATCOR16_SHORT_CNT_LMT2_SZ 3
+#define RG_VITERBI_TB_BITS_MSK 0xff000000
+#define RG_VITERBI_TB_BITS_I_MSK 0x00ffffff
+#define RG_VITERBI_TB_BITS_SFT 24
+#define RG_VITERBI_TB_BITS_HI 31
+#define RG_VITERBI_TB_BITS_SZ 8
+#define RG_CR_CNT_UPDATE_MSK 0x000000ff
+#define RG_CR_CNT_UPDATE_I_MSK 0xffffff00
+#define RG_CR_CNT_UPDATE_SFT 0
+#define RG_CR_CNT_UPDATE_HI 7
+#define RG_CR_CNT_UPDATE_SZ 8
+#define RG_TR_CNT_UPDATE_MSK 0x00ff0000
+#define RG_TR_CNT_UPDATE_I_MSK 0xff00ffff
+#define RG_TR_CNT_UPDATE_SFT 16
+#define RG_TR_CNT_UPDATE_HI 23
+#define RG_TR_CNT_UPDATE_SZ 8
+#define RG_BYPASS_CPE_MA_MSK 0x00000010
+#define RG_BYPASS_CPE_MA_I_MSK 0xffffffef
+#define RG_BYPASS_CPE_MA_SFT 4
+#define RG_BYPASS_CPE_MA_HI 4
+#define RG_BYPASS_CPE_MA_SZ 1
+#define RG_PILOT_BNDRY_SHIFT_MSK 0x00000700
+#define RG_PILOT_BNDRY_SHIFT_I_MSK 0xfffff8ff
+#define RG_PILOT_BNDRY_SHIFT_SFT 8
+#define RG_PILOT_BNDRY_SHIFT_HI 10
+#define RG_PILOT_BNDRY_SHIFT_SZ 3
+#define RG_EQ_SHORT_GI_SHIFT_MSK 0x00007000
+#define RG_EQ_SHORT_GI_SHIFT_I_MSK 0xffff8fff
+#define RG_EQ_SHORT_GI_SHIFT_SFT 12
+#define RG_EQ_SHORT_GI_SHIFT_HI 14
+#define RG_EQ_SHORT_GI_SHIFT_SZ 3
+#define RG_FFT_WDW_SHORT_SHIFT_MSK 0x00070000
+#define RG_FFT_WDW_SHORT_SHIFT_I_MSK 0xfff8ffff
+#define RG_FFT_WDW_SHORT_SHIFT_SFT 16
+#define RG_FFT_WDW_SHORT_SHIFT_HI 18
+#define RG_FFT_WDW_SHORT_SHIFT_SZ 3
+#define RG_CHSMTH_COEF_MSK 0x00030000
+#define RG_CHSMTH_COEF_I_MSK 0xfffcffff
+#define RG_CHSMTH_COEF_SFT 16
+#define RG_CHSMTH_COEF_HI 17
+#define RG_CHSMTH_COEF_SZ 2
+#define RG_CHSMTH_EN_MSK 0x00040000
+#define RG_CHSMTH_EN_I_MSK 0xfffbffff
+#define RG_CHSMTH_EN_SFT 18
+#define RG_CHSMTH_EN_HI 18
+#define RG_CHSMTH_EN_SZ 1
+#define RG_CHEST_DD_FACTOR_MSK 0x07000000
+#define RG_CHEST_DD_FACTOR_I_MSK 0xf8ffffff
+#define RG_CHEST_DD_FACTOR_SFT 24
+#define RG_CHEST_DD_FACTOR_HI 26
+#define RG_CHEST_DD_FACTOR_SZ 3
+#define RG_CH_UPDATE_MSK 0x80000000
+#define RG_CH_UPDATE_I_MSK 0x7fffffff
+#define RG_CH_UPDATE_SFT 31
+#define RG_CH_UPDATE_HI 31
+#define RG_CH_UPDATE_SZ 1
+#define RG_FMT_DET_MM_TH_MSK 0x000000ff
+#define RG_FMT_DET_MM_TH_I_MSK 0xffffff00
+#define RG_FMT_DET_MM_TH_SFT 0
+#define RG_FMT_DET_MM_TH_HI 7
+#define RG_FMT_DET_MM_TH_SZ 8
+#define RG_FMT_DET_GF_TH_MSK 0x0000ff00
+#define RG_FMT_DET_GF_TH_I_MSK 0xffff00ff
+#define RG_FMT_DET_GF_TH_SFT 8
+#define RG_FMT_DET_GF_TH_HI 15
+#define RG_FMT_DET_GF_TH_SZ 8
+#define RG_DO_NOT_CHECK_L_RATE_MSK 0x02000000
+#define RG_DO_NOT_CHECK_L_RATE_I_MSK 0xfdffffff
+#define RG_DO_NOT_CHECK_L_RATE_SFT 25
+#define RG_DO_NOT_CHECK_L_RATE_HI 25
+#define RG_DO_NOT_CHECK_L_RATE_SZ 1
+#define RG_FMT_DET_LENGTH_TH_MSK 0x0000ffff
+#define RG_FMT_DET_LENGTH_TH_I_MSK 0xffff0000
+#define RG_FMT_DET_LENGTH_TH_SFT 0
+#define RG_FMT_DET_LENGTH_TH_HI 15
+#define RG_FMT_DET_LENGTH_TH_SZ 16
+#define RG_L_LENGTH_MAX_MSK 0xffff0000
+#define RG_L_LENGTH_MAX_I_MSK 0x0000ffff
+#define RG_L_LENGTH_MAX_SFT 16
+#define RG_L_LENGTH_MAX_HI 31
+#define RG_L_LENGTH_MAX_SZ 16
+#define RG_TX_TIME_EXT_MSK 0x000000ff
+#define RG_TX_TIME_EXT_I_MSK 0xffffff00
+#define RG_TX_TIME_EXT_SFT 0
+#define RG_TX_TIME_EXT_HI 7
+#define RG_TX_TIME_EXT_SZ 8
+#define RG_MAC_DES_SPACE_MSK 0x00f00000
+#define RG_MAC_DES_SPACE_I_MSK 0xff0fffff
+#define RG_MAC_DES_SPACE_SFT 20
+#define RG_MAC_DES_SPACE_HI 23
+#define RG_MAC_DES_SPACE_SZ 4
+#define RG_TR_LPF_STBC_GF_KI_G_MSK 0x0000000f
+#define RG_TR_LPF_STBC_GF_KI_G_I_MSK 0xfffffff0
+#define RG_TR_LPF_STBC_GF_KI_G_SFT 0
+#define RG_TR_LPF_STBC_GF_KI_G_HI 3
+#define RG_TR_LPF_STBC_GF_KI_G_SZ 4
+#define RG_TR_LPF_STBC_GF_KP_G_MSK 0x000000f0
+#define RG_TR_LPF_STBC_GF_KP_G_I_MSK 0xffffff0f
+#define RG_TR_LPF_STBC_GF_KP_G_SFT 4
+#define RG_TR_LPF_STBC_GF_KP_G_HI 7
+#define RG_TR_LPF_STBC_GF_KP_G_SZ 4
+#define RG_TR_LPF_STBC_MF_KI_G_MSK 0x00000f00
+#define RG_TR_LPF_STBC_MF_KI_G_I_MSK 0xfffff0ff
+#define RG_TR_LPF_STBC_MF_KI_G_SFT 8
+#define RG_TR_LPF_STBC_MF_KI_G_HI 11
+#define RG_TR_LPF_STBC_MF_KI_G_SZ 4
+#define RG_TR_LPF_STBC_MF_KP_G_MSK 0x0000f000
+#define RG_TR_LPF_STBC_MF_KP_G_I_MSK 0xffff0fff
+#define RG_TR_LPF_STBC_MF_KP_G_SFT 12
+#define RG_TR_LPF_STBC_MF_KP_G_HI 15
+#define RG_TR_LPF_STBC_MF_KP_G_SZ 4
+#define RG_MODE_REG_IN_80_MSK 0x0001ffff
+#define RG_MODE_REG_IN_80_I_MSK 0xfffe0000
+#define RG_MODE_REG_IN_80_SFT 0
+#define RG_MODE_REG_IN_80_HI 16
+#define RG_MODE_REG_IN_80_SZ 17
+#define RG_PARALLEL_DR_80_MSK 0x00100000
+#define RG_PARALLEL_DR_80_I_MSK 0xffefffff
+#define RG_PARALLEL_DR_80_SFT 20
+#define RG_PARALLEL_DR_80_HI 20
+#define RG_PARALLEL_DR_80_SZ 1
+#define RG_MBRUN_80_MSK 0x01000000
+#define RG_MBRUN_80_I_MSK 0xfeffffff
+#define RG_MBRUN_80_SFT 24
+#define RG_MBRUN_80_HI 24
+#define RG_MBRUN_80_SZ 1
+#define RG_SHIFT_DR_80_MSK 0x10000000
+#define RG_SHIFT_DR_80_I_MSK 0xefffffff
+#define RG_SHIFT_DR_80_SFT 28
+#define RG_SHIFT_DR_80_HI 28
+#define RG_SHIFT_DR_80_SZ 1
+#define RG_MODE_REG_SI_80_MSK 0x20000000
+#define RG_MODE_REG_SI_80_I_MSK 0xdfffffff
+#define RG_MODE_REG_SI_80_SFT 29
+#define RG_MODE_REG_SI_80_HI 29
+#define RG_MODE_REG_SI_80_SZ 1
+#define RG_SIMULATION_MODE_80_MSK 0x40000000
+#define RG_SIMULATION_MODE_80_I_MSK 0xbfffffff
+#define RG_SIMULATION_MODE_80_SFT 30
+#define RG_SIMULATION_MODE_80_HI 30
+#define RG_SIMULATION_MODE_80_SZ 1
+#define RG_DBIST_MODE_80_MSK 0x80000000
+#define RG_DBIST_MODE_80_I_MSK 0x7fffffff
+#define RG_DBIST_MODE_80_SFT 31
+#define RG_DBIST_MODE_80_HI 31
+#define RG_DBIST_MODE_80_SZ 1
+#define RG_MODE_REG_IN_64_MSK 0x0000ffff
+#define RG_MODE_REG_IN_64_I_MSK 0xffff0000
+#define RG_MODE_REG_IN_64_SFT 0
+#define RG_MODE_REG_IN_64_HI 15
+#define RG_MODE_REG_IN_64_SZ 16
+#define RG_PARALLEL_DR_64_MSK 0x00100000
+#define RG_PARALLEL_DR_64_I_MSK 0xffefffff
+#define RG_PARALLEL_DR_64_SFT 20
+#define RG_PARALLEL_DR_64_HI 20
+#define RG_PARALLEL_DR_64_SZ 1
+#define RG_MBRUN_64_MSK 0x01000000
+#define RG_MBRUN_64_I_MSK 0xfeffffff
+#define RG_MBRUN_64_SFT 24
+#define RG_MBRUN_64_HI 24
+#define RG_MBRUN_64_SZ 1
+#define RG_SHIFT_DR_64_MSK 0x10000000
+#define RG_SHIFT_DR_64_I_MSK 0xefffffff
+#define RG_SHIFT_DR_64_SFT 28
+#define RG_SHIFT_DR_64_HI 28
+#define RG_SHIFT_DR_64_SZ 1
+#define RG_MODE_REG_SI_64_MSK 0x20000000
+#define RG_MODE_REG_SI_64_I_MSK 0xdfffffff
+#define RG_MODE_REG_SI_64_SFT 29
+#define RG_MODE_REG_SI_64_HI 29
+#define RG_MODE_REG_SI_64_SZ 1
+#define RG_SIMULATION_MODE_64_MSK 0x40000000
+#define RG_SIMULATION_MODE_64_I_MSK 0xbfffffff
+#define RG_SIMULATION_MODE_64_SFT 30
+#define RG_SIMULATION_MODE_64_HI 30
+#define RG_SIMULATION_MODE_64_SZ 1
+#define RG_DBIST_MODE_64_MSK 0x80000000
+#define RG_DBIST_MODE_64_I_MSK 0x7fffffff
+#define RG_DBIST_MODE_64_SFT 31
+#define RG_DBIST_MODE_64_HI 31
+#define RG_DBIST_MODE_64_SZ 1
+#define RO_MODE_REG_OUT_80_MSK 0x0001ffff
+#define RO_MODE_REG_OUT_80_I_MSK 0xfffe0000
+#define RO_MODE_REG_OUT_80_SFT 0
+#define RO_MODE_REG_OUT_80_HI 16
+#define RO_MODE_REG_OUT_80_SZ 17
+#define RO_MODE_REG_SO_80_MSK 0x01000000
+#define RO_MODE_REG_SO_80_I_MSK 0xfeffffff
+#define RO_MODE_REG_SO_80_SFT 24
+#define RO_MODE_REG_SO_80_HI 24
+#define RO_MODE_REG_SO_80_SZ 1
+#define RO_MONITOR_BUS_80_MSK 0x003fffff
+#define RO_MONITOR_BUS_80_I_MSK 0xffc00000
+#define RO_MONITOR_BUS_80_SFT 0
+#define RO_MONITOR_BUS_80_HI 21
+#define RO_MONITOR_BUS_80_SZ 22
+#define RO_MODE_REG_OUT_64_MSK 0x0000ffff
+#define RO_MODE_REG_OUT_64_I_MSK 0xffff0000
+#define RO_MODE_REG_OUT_64_SFT 0
+#define RO_MODE_REG_OUT_64_HI 15
+#define RO_MODE_REG_OUT_64_SZ 16
+#define RO_MODE_REG_SO_64_MSK 0x01000000
+#define RO_MODE_REG_SO_64_I_MSK 0xfeffffff
+#define RO_MODE_REG_SO_64_SFT 24
+#define RO_MODE_REG_SO_64_HI 24
+#define RO_MODE_REG_SO_64_SZ 1
+#define RO_MONITOR_BUS_64_MSK 0x0007ffff
+#define RO_MONITOR_BUS_64_I_MSK 0xfff80000
+#define RO_MONITOR_BUS_64_SFT 0
+#define RO_MONITOR_BUS_64_HI 18
+#define RO_MONITOR_BUS_64_SZ 19
+#define RO_SPECTRUM_DATA_MSK 0xffffffff
+#define RO_SPECTRUM_DATA_I_MSK 0x00000000
+#define RO_SPECTRUM_DATA_SFT 0
+#define RO_SPECTRUM_DATA_HI 31
+#define RO_SPECTRUM_DATA_SZ 32
+#define GN_SNR_MSK 0x0000007f
+#define GN_SNR_I_MSK 0xffffff80
+#define GN_SNR_SFT 0
+#define GN_SNR_HI 6
+#define GN_SNR_SZ 7
+#define GN_NOISE_PWR_MSK 0x00007f00
+#define GN_NOISE_PWR_I_MSK 0xffff80ff
+#define GN_NOISE_PWR_SFT 8
+#define GN_NOISE_PWR_HI 14
+#define GN_NOISE_PWR_SZ 7
+#define GN_RCPI_MSK 0x007f0000
+#define GN_RCPI_I_MSK 0xff80ffff
+#define GN_RCPI_SFT 16
+#define GN_RCPI_HI 22
+#define GN_RCPI_SZ 7
+#define GN_SIGNAL_PWR_MSK 0x7f000000
+#define GN_SIGNAL_PWR_I_MSK 0x80ffffff
+#define GN_SIGNAL_PWR_SFT 24
+#define GN_SIGNAL_PWR_HI 30
+#define GN_SIGNAL_PWR_SZ 7
+#define RO_FREQ_OS_LTS_MSK 0x00007fff
+#define RO_FREQ_OS_LTS_I_MSK 0xffff8000
+#define RO_FREQ_OS_LTS_SFT 0
+#define RO_FREQ_OS_LTS_HI 14
+#define RO_FREQ_OS_LTS_SZ 15
+#define CSTATE_MSK 0x000f0000
+#define CSTATE_I_MSK 0xfff0ffff
+#define CSTATE_SFT 16
+#define CSTATE_HI 19
+#define CSTATE_SZ 4
+#define SIGNAL_FIELD0_MSK 0x00ffffff
+#define SIGNAL_FIELD0_I_MSK 0xff000000
+#define SIGNAL_FIELD0_SFT 0
+#define SIGNAL_FIELD0_HI 23
+#define SIGNAL_FIELD0_SZ 24
+#define SIGNAL_FIELD1_MSK 0x00ffffff
+#define SIGNAL_FIELD1_I_MSK 0xff000000
+#define SIGNAL_FIELD1_SFT 0
+#define SIGNAL_FIELD1_HI 23
+#define SIGNAL_FIELD1_SZ 24
+#define GN_PACKET_ERR_CNT_MSK 0x0000ffff
+#define GN_PACKET_ERR_CNT_I_MSK 0xffff0000
+#define GN_PACKET_ERR_CNT_SFT 0
+#define GN_PACKET_ERR_CNT_HI 15
+#define GN_PACKET_ERR_CNT_SZ 16
+#define GN_PACKET_CNT_MSK 0x0000ffff
+#define GN_PACKET_CNT_I_MSK 0xffff0000
+#define GN_PACKET_CNT_SFT 0
+#define GN_PACKET_CNT_HI 15
+#define GN_PACKET_CNT_SZ 16
+#define GN_CCA_CNT_MSK 0xffff0000
+#define GN_CCA_CNT_I_MSK 0x0000ffff
+#define GN_CCA_CNT_SFT 16
+#define GN_CCA_CNT_HI 31
+#define GN_CCA_CNT_SZ 16
+#define GN_LENGTH_FIELD_MSK 0x0000ffff
+#define GN_LENGTH_FIELD_I_MSK 0xffff0000
+#define GN_LENGTH_FIELD_SFT 0
+#define GN_LENGTH_FIELD_HI 15
+#define GN_LENGTH_FIELD_SZ 16
+#define GN_SERVICE_FIELD_MSK 0xffff0000
+#define GN_SERVICE_FIELD_I_MSK 0x0000ffff
+#define GN_SERVICE_FIELD_SFT 16
+#define GN_SERVICE_FIELD_HI 31
+#define GN_SERVICE_FIELD_SZ 16
+#define RO_HT_MCS_40M_MSK 0x0000007f
+#define RO_HT_MCS_40M_I_MSK 0xffffff80
+#define RO_HT_MCS_40M_SFT 0
+#define RO_HT_MCS_40M_HI 6
+#define RO_HT_MCS_40M_SZ 7
+#define RO_L_RATE_40M_MSK 0x00003f00
+#define RO_L_RATE_40M_I_MSK 0xffffc0ff
+#define RO_L_RATE_40M_SFT 8
+#define RO_L_RATE_40M_HI 13
+#define RO_L_RATE_40M_SZ 6
+#define RG_DAGC_CNT_TH_MSK 0x00000003
+#define RG_DAGC_CNT_TH_I_MSK 0xfffffffc
+#define RG_DAGC_CNT_TH_SFT 0
+#define RG_DAGC_CNT_TH_HI 1
+#define RG_DAGC_CNT_TH_SZ 2
+#define RG_PACKET_STAT_EN_11GN_MSK 0x00100000
+#define RG_PACKET_STAT_EN_11GN_I_MSK 0xffefffff
+#define RG_PACKET_STAT_EN_11GN_SFT 20
+#define RG_PACKET_STAT_EN_11GN_HI 20
+#define RG_PACKET_STAT_EN_11GN_SZ 1
+#define RX_PHY_11GN_SOFT_RST_N_MSK 0x00000001
+#define RX_PHY_11GN_SOFT_RST_N_I_MSK 0xfffffffe
+#define RX_PHY_11GN_SOFT_RST_N_SFT 0
+#define RX_PHY_11GN_SOFT_RST_N_HI 0
+#define RX_PHY_11GN_SOFT_RST_N_SZ 1
+#define RG_RIFS_EN_MSK 0x00000002
+#define RG_RIFS_EN_I_MSK 0xfffffffd
+#define RG_RIFS_EN_SFT 1
+#define RG_RIFS_EN_HI 1
+#define RG_RIFS_EN_SZ 1
+#define RG_STBC_EN_MSK 0x00000004
+#define RG_STBC_EN_I_MSK 0xfffffffb
+#define RG_STBC_EN_SFT 2
+#define RG_STBC_EN_HI 2
+#define RG_STBC_EN_SZ 1
+#define RG_COR_SEL_MSK 0x00000008
+#define RG_COR_SEL_I_MSK 0xfffffff7
+#define RG_COR_SEL_SFT 3
+#define RG_COR_SEL_HI 3
+#define RG_COR_SEL_SZ 1
+#define RG_INI_PHASE_MSK 0x00000030
+#define RG_INI_PHASE_I_MSK 0xffffffcf
+#define RG_INI_PHASE_SFT 4
+#define RG_INI_PHASE_HI 5
+#define RG_INI_PHASE_SZ 2
+#define RG_HT_LTF_SEL_EQ_MSK 0x00000040
+#define RG_HT_LTF_SEL_EQ_I_MSK 0xffffffbf
+#define RG_HT_LTF_SEL_EQ_SFT 6
+#define RG_HT_LTF_SEL_EQ_HI 6
+#define RG_HT_LTF_SEL_EQ_SZ 1
+#define RG_HT_LTF_SEL_PILOT_MSK 0x00000080
+#define RG_HT_LTF_SEL_PILOT_I_MSK 0xffffff7f
+#define RG_HT_LTF_SEL_PILOT_SFT 7
+#define RG_HT_LTF_SEL_PILOT_HI 7
+#define RG_HT_LTF_SEL_PILOT_SZ 1
+#define RG_CCA_PWR_SEL_MSK 0x00000200
+#define RG_CCA_PWR_SEL_I_MSK 0xfffffdff
+#define RG_CCA_PWR_SEL_SFT 9
+#define RG_CCA_PWR_SEL_HI 9
+#define RG_CCA_PWR_SEL_SZ 1
+#define RG_CCA_XSCOR_PWR_SEL_MSK 0x00000400
+#define RG_CCA_XSCOR_PWR_SEL_I_MSK 0xfffffbff
+#define RG_CCA_XSCOR_PWR_SEL_SFT 10
+#define RG_CCA_XSCOR_PWR_SEL_HI 10
+#define RG_CCA_XSCOR_PWR_SEL_SZ 1
+#define RG_CCA_XSCOR_AVGPWR_SEL_MSK 0x00000800
+#define RG_CCA_XSCOR_AVGPWR_SEL_I_MSK 0xfffff7ff
+#define RG_CCA_XSCOR_AVGPWR_SEL_SFT 11
+#define RG_CCA_XSCOR_AVGPWR_SEL_HI 11
+#define RG_CCA_XSCOR_AVGPWR_SEL_SZ 1
+#define RG_DEBUG_SEL_MSK 0x0000f000
+#define RG_DEBUG_SEL_I_MSK 0xffff0fff
+#define RG_DEBUG_SEL_SFT 12
+#define RG_DEBUG_SEL_HI 15
+#define RG_DEBUG_SEL_SZ 4
+#define RG_POST_CLK_EN_MSK 0x00010000
+#define RG_POST_CLK_EN_I_MSK 0xfffeffff
+#define RG_POST_CLK_EN_SFT 16
+#define RG_POST_CLK_EN_HI 16
+#define RG_POST_CLK_EN_SZ 1
+#define IQCAL_RF_TX_EN_MSK 0x00000001
+#define IQCAL_RF_TX_EN_I_MSK 0xfffffffe
+#define IQCAL_RF_TX_EN_SFT 0
+#define IQCAL_RF_TX_EN_HI 0
+#define IQCAL_RF_TX_EN_SZ 1
+#define IQCAL_RF_TX_PA_EN_MSK 0x00000002
+#define IQCAL_RF_TX_PA_EN_I_MSK 0xfffffffd
+#define IQCAL_RF_TX_PA_EN_SFT 1
+#define IQCAL_RF_TX_PA_EN_HI 1
+#define IQCAL_RF_TX_PA_EN_SZ 1
+#define IQCAL_RF_TX_DAC_EN_MSK 0x00000004
+#define IQCAL_RF_TX_DAC_EN_I_MSK 0xfffffffb
+#define IQCAL_RF_TX_DAC_EN_SFT 2
+#define IQCAL_RF_TX_DAC_EN_HI 2
+#define IQCAL_RF_TX_DAC_EN_SZ 1
+#define IQCAL_RF_RX_AGC_MSK 0x00000008
+#define IQCAL_RF_RX_AGC_I_MSK 0xfffffff7
+#define IQCAL_RF_RX_AGC_SFT 3
+#define IQCAL_RF_RX_AGC_HI 3
+#define IQCAL_RF_RX_AGC_SZ 1
+#define IQCAL_RF_PGAG_MSK 0x00000f00
+#define IQCAL_RF_PGAG_I_MSK 0xfffff0ff
+#define IQCAL_RF_PGAG_SFT 8
+#define IQCAL_RF_PGAG_HI 11
+#define IQCAL_RF_PGAG_SZ 4
+#define IQCAL_RF_RFG_MSK 0x00003000
+#define IQCAL_RF_RFG_I_MSK 0xffffcfff
+#define IQCAL_RF_RFG_SFT 12
+#define IQCAL_RF_RFG_HI 13
+#define IQCAL_RF_RFG_SZ 2
+#define RG_TONEGEN_FREQ_MSK 0x007f0000
+#define RG_TONEGEN_FREQ_I_MSK 0xff80ffff
+#define RG_TONEGEN_FREQ_SFT 16
+#define RG_TONEGEN_FREQ_HI 22
+#define RG_TONEGEN_FREQ_SZ 7
+#define RG_TONEGEN_EN_MSK 0x00800000
+#define RG_TONEGEN_EN_I_MSK 0xff7fffff
+#define RG_TONEGEN_EN_SFT 23
+#define RG_TONEGEN_EN_HI 23
+#define RG_TONEGEN_EN_SZ 1
+#define RG_TONEGEN_INIT_PH_MSK 0x7f000000
+#define RG_TONEGEN_INIT_PH_I_MSK 0x80ffffff
+#define RG_TONEGEN_INIT_PH_SFT 24
+#define RG_TONEGEN_INIT_PH_HI 30
+#define RG_TONEGEN_INIT_PH_SZ 7
+#define RG_TONEGEN2_FREQ_MSK 0x0000007f
+#define RG_TONEGEN2_FREQ_I_MSK 0xffffff80
+#define RG_TONEGEN2_FREQ_SFT 0
+#define RG_TONEGEN2_FREQ_HI 6
+#define RG_TONEGEN2_FREQ_SZ 7
+#define RG_TONEGEN2_EN_MSK 0x00000080
+#define RG_TONEGEN2_EN_I_MSK 0xffffff7f
+#define RG_TONEGEN2_EN_SFT 7
+#define RG_TONEGEN2_EN_HI 7
+#define RG_TONEGEN2_EN_SZ 1
+#define RG_TONEGEN2_SCALE_MSK 0x0000ff00
+#define RG_TONEGEN2_SCALE_I_MSK 0xffff00ff
+#define RG_TONEGEN2_SCALE_SFT 8
+#define RG_TONEGEN2_SCALE_HI 15
+#define RG_TONEGEN2_SCALE_SZ 8
+#define RG_TXIQ_CLP_THD_I_MSK 0x000003ff
+#define RG_TXIQ_CLP_THD_I_I_MSK 0xfffffc00
+#define RG_TXIQ_CLP_THD_I_SFT 0
+#define RG_TXIQ_CLP_THD_I_HI 9
+#define RG_TXIQ_CLP_THD_I_SZ 10
+#define RG_TXIQ_CLP_THD_Q_MSK 0x03ff0000
+#define RG_TXIQ_CLP_THD_Q_I_MSK 0xfc00ffff
+#define RG_TXIQ_CLP_THD_Q_SFT 16
+#define RG_TXIQ_CLP_THD_Q_HI 25
+#define RG_TXIQ_CLP_THD_Q_SZ 10
+#define RG_TX_I_SCALE_MSK 0x000000ff
+#define RG_TX_I_SCALE_I_MSK 0xffffff00
+#define RG_TX_I_SCALE_SFT 0
+#define RG_TX_I_SCALE_HI 7
+#define RG_TX_I_SCALE_SZ 8
+#define RG_TX_Q_SCALE_MSK 0x0000ff00
+#define RG_TX_Q_SCALE_I_MSK 0xffff00ff
+#define RG_TX_Q_SCALE_SFT 8
+#define RG_TX_Q_SCALE_HI 15
+#define RG_TX_Q_SCALE_SZ 8
+#define RG_TX_IQ_SWP_MSK 0x00010000
+#define RG_TX_IQ_SWP_I_MSK 0xfffeffff
+#define RG_TX_IQ_SWP_SFT 16
+#define RG_TX_IQ_SWP_HI 16
+#define RG_TX_IQ_SWP_SZ 1
+#define RG_TX_SGN_OUT_MSK 0x00020000
+#define RG_TX_SGN_OUT_I_MSK 0xfffdffff
+#define RG_TX_SGN_OUT_SFT 17
+#define RG_TX_SGN_OUT_HI 17
+#define RG_TX_SGN_OUT_SZ 1
+#define RG_TXIQ_EMU_IDX_MSK 0x003c0000
+#define RG_TXIQ_EMU_IDX_I_MSK 0xffc3ffff
+#define RG_TXIQ_EMU_IDX_SFT 18
+#define RG_TXIQ_EMU_IDX_HI 21
+#define RG_TXIQ_EMU_IDX_SZ 4
+#define RG_TX_IQ_SRC_MSK 0x03000000
+#define RG_TX_IQ_SRC_I_MSK 0xfcffffff
+#define RG_TX_IQ_SRC_SFT 24
+#define RG_TX_IQ_SRC_HI 25
+#define RG_TX_IQ_SRC_SZ 2
+#define RG_TX_I_DC_MSK 0x000003ff
+#define RG_TX_I_DC_I_MSK 0xfffffc00
+#define RG_TX_I_DC_SFT 0
+#define RG_TX_I_DC_HI 9
+#define RG_TX_I_DC_SZ 10
+#define RG_TX_Q_DC_MSK 0x03ff0000
+#define RG_TX_Q_DC_I_MSK 0xfc00ffff
+#define RG_TX_Q_DC_SFT 16
+#define RG_TX_Q_DC_HI 25
+#define RG_TX_Q_DC_SZ 10
+#define RG_TX_IQ_THETA_MSK 0x0000001f
+#define RG_TX_IQ_THETA_I_MSK 0xffffffe0
+#define RG_TX_IQ_THETA_SFT 0
+#define RG_TX_IQ_THETA_HI 4
+#define RG_TX_IQ_THETA_SZ 5
+#define RG_TX_IQ_ALPHA_MSK 0x00001f00
+#define RG_TX_IQ_ALPHA_I_MSK 0xffffe0ff
+#define RG_TX_IQ_ALPHA_SFT 8
+#define RG_TX_IQ_ALPHA_HI 12
+#define RG_TX_IQ_ALPHA_SZ 5
+#define RG_TXIQ_NOSHRINK_MSK 0x00002000
+#define RG_TXIQ_NOSHRINK_I_MSK 0xffffdfff
+#define RG_TXIQ_NOSHRINK_SFT 13
+#define RG_TXIQ_NOSHRINK_HI 13
+#define RG_TXIQ_NOSHRINK_SZ 1
+#define RG_TX_I_OFFSET_MSK 0x00ff0000
+#define RG_TX_I_OFFSET_I_MSK 0xff00ffff
+#define RG_TX_I_OFFSET_SFT 16
+#define RG_TX_I_OFFSET_HI 23
+#define RG_TX_I_OFFSET_SZ 8
+#define RG_TX_Q_OFFSET_MSK 0xff000000
+#define RG_TX_Q_OFFSET_I_MSK 0x00ffffff
+#define RG_TX_Q_OFFSET_SFT 24
+#define RG_TX_Q_OFFSET_HI 31
+#define RG_TX_Q_OFFSET_SZ 8
+#define RG_RX_IQ_THETA_MSK 0x0000001f
+#define RG_RX_IQ_THETA_I_MSK 0xffffffe0
+#define RG_RX_IQ_THETA_SFT 0
+#define RG_RX_IQ_THETA_HI 4
+#define RG_RX_IQ_THETA_SZ 5
+#define RG_RX_IQ_ALPHA_MSK 0x00001f00
+#define RG_RX_IQ_ALPHA_I_MSK 0xffffe0ff
+#define RG_RX_IQ_ALPHA_SFT 8
+#define RG_RX_IQ_ALPHA_HI 12
+#define RG_RX_IQ_ALPHA_SZ 5
+#define RG_RXIQ_NOSHRINK_MSK 0x00002000
+#define RG_RXIQ_NOSHRINK_I_MSK 0xffffdfff
+#define RG_RXIQ_NOSHRINK_SFT 13
+#define RG_RXIQ_NOSHRINK_HI 13
+#define RG_RXIQ_NOSHRINK_SZ 1
+#define RG_MA_DPTH_MSK 0x0000000f
+#define RG_MA_DPTH_I_MSK 0xfffffff0
+#define RG_MA_DPTH_SFT 0
+#define RG_MA_DPTH_HI 3
+#define RG_MA_DPTH_SZ 4
+#define RG_INTG_PH_MSK 0x000003f0
+#define RG_INTG_PH_I_MSK 0xfffffc0f
+#define RG_INTG_PH_SFT 4
+#define RG_INTG_PH_HI 9
+#define RG_INTG_PH_SZ 6
+#define RG_INTG_PRD_MSK 0x00001c00
+#define RG_INTG_PRD_I_MSK 0xffffe3ff
+#define RG_INTG_PRD_SFT 10
+#define RG_INTG_PRD_HI 12
+#define RG_INTG_PRD_SZ 3
+#define RG_INTG_MU_MSK 0x00006000
+#define RG_INTG_MU_I_MSK 0xffff9fff
+#define RG_INTG_MU_SFT 13
+#define RG_INTG_MU_HI 14
+#define RG_INTG_MU_SZ 2
+#define RG_IQCAL_SPRM_SELQ_MSK 0x00010000
+#define RG_IQCAL_SPRM_SELQ_I_MSK 0xfffeffff
+#define RG_IQCAL_SPRM_SELQ_SFT 16
+#define RG_IQCAL_SPRM_SELQ_HI 16
+#define RG_IQCAL_SPRM_SELQ_SZ 1
+#define RG_IQCAL_SPRM_EN_MSK 0x00020000
+#define RG_IQCAL_SPRM_EN_I_MSK 0xfffdffff
+#define RG_IQCAL_SPRM_EN_SFT 17
+#define RG_IQCAL_SPRM_EN_HI 17
+#define RG_IQCAL_SPRM_EN_SZ 1
+#define RG_IQCAL_SPRM_FREQ_MSK 0x00fc0000
+#define RG_IQCAL_SPRM_FREQ_I_MSK 0xff03ffff
+#define RG_IQCAL_SPRM_FREQ_SFT 18
+#define RG_IQCAL_SPRM_FREQ_HI 23
+#define RG_IQCAL_SPRM_FREQ_SZ 6
+#define RG_IQCAL_IQCOL_EN_MSK 0x01000000
+#define RG_IQCAL_IQCOL_EN_I_MSK 0xfeffffff
+#define RG_IQCAL_IQCOL_EN_SFT 24
+#define RG_IQCAL_IQCOL_EN_HI 24
+#define RG_IQCAL_IQCOL_EN_SZ 1
+#define RG_IQCAL_ALPHA_ESTM_EN_MSK 0x02000000
+#define RG_IQCAL_ALPHA_ESTM_EN_I_MSK 0xfdffffff
+#define RG_IQCAL_ALPHA_ESTM_EN_SFT 25
+#define RG_IQCAL_ALPHA_ESTM_EN_HI 25
+#define RG_IQCAL_ALPHA_ESTM_EN_SZ 1
+#define RG_IQCAL_DC_EN_MSK 0x04000000
+#define RG_IQCAL_DC_EN_I_MSK 0xfbffffff
+#define RG_IQCAL_DC_EN_SFT 26
+#define RG_IQCAL_DC_EN_HI 26
+#define RG_IQCAL_DC_EN_SZ 1
+#define RG_PHEST_STBY_MSK 0x08000000
+#define RG_PHEST_STBY_I_MSK 0xf7ffffff
+#define RG_PHEST_STBY_SFT 27
+#define RG_PHEST_STBY_HI 27
+#define RG_PHEST_STBY_SZ 1
+#define RG_PHEST_EN_MSK 0x10000000
+#define RG_PHEST_EN_I_MSK 0xefffffff
+#define RG_PHEST_EN_SFT 28
+#define RG_PHEST_EN_HI 28
+#define RG_PHEST_EN_SZ 1
+#define RG_GP_DIV_EN_MSK 0x20000000
+#define RG_GP_DIV_EN_I_MSK 0xdfffffff
+#define RG_GP_DIV_EN_SFT 29
+#define RG_GP_DIV_EN_HI 29
+#define RG_GP_DIV_EN_SZ 1
+#define RG_DPD_GAIN_EST_EN_MSK 0x40000000
+#define RG_DPD_GAIN_EST_EN_I_MSK 0xbfffffff
+#define RG_DPD_GAIN_EST_EN_SFT 30
+#define RG_DPD_GAIN_EST_EN_HI 30
+#define RG_DPD_GAIN_EST_EN_SZ 1
+#define RG_IQCAL_MULT_OP0_MSK 0x000003ff
+#define RG_IQCAL_MULT_OP0_I_MSK 0xfffffc00
+#define RG_IQCAL_MULT_OP0_SFT 0
+#define RG_IQCAL_MULT_OP0_HI 9
+#define RG_IQCAL_MULT_OP0_SZ 10
+#define RG_IQCAL_MULT_OP1_MSK 0x03ff0000
+#define RG_IQCAL_MULT_OP1_I_MSK 0xfc00ffff
+#define RG_IQCAL_MULT_OP1_SFT 16
+#define RG_IQCAL_MULT_OP1_HI 25
+#define RG_IQCAL_MULT_OP1_SZ 10
+#define RO_IQCAL_O_MSK 0x000fffff
+#define RO_IQCAL_O_I_MSK 0xfff00000
+#define RO_IQCAL_O_SFT 0
+#define RO_IQCAL_O_HI 19
+#define RO_IQCAL_O_SZ 20
+#define RO_IQCAL_SPRM_RDY_MSK 0x00100000
+#define RO_IQCAL_SPRM_RDY_I_MSK 0xffefffff
+#define RO_IQCAL_SPRM_RDY_SFT 20
+#define RO_IQCAL_SPRM_RDY_HI 20
+#define RO_IQCAL_SPRM_RDY_SZ 1
+#define RO_IQCAL_IQCOL_RDY_MSK 0x00200000
+#define RO_IQCAL_IQCOL_RDY_I_MSK 0xffdfffff
+#define RO_IQCAL_IQCOL_RDY_SFT 21
+#define RO_IQCAL_IQCOL_RDY_HI 21
+#define RO_IQCAL_IQCOL_RDY_SZ 1
+#define RO_IQCAL_ALPHA_ESTM_RDY_MSK 0x00400000
+#define RO_IQCAL_ALPHA_ESTM_RDY_I_MSK 0xffbfffff
+#define RO_IQCAL_ALPHA_ESTM_RDY_SFT 22
+#define RO_IQCAL_ALPHA_ESTM_RDY_HI 22
+#define RO_IQCAL_ALPHA_ESTM_RDY_SZ 1
+#define RO_IQCAL_DC_RDY_MSK 0x00800000
+#define RO_IQCAL_DC_RDY_I_MSK 0xff7fffff
+#define RO_IQCAL_DC_RDY_SFT 23
+#define RO_IQCAL_DC_RDY_HI 23
+#define RO_IQCAL_DC_RDY_SZ 1
+#define RO_IQCAL_MULT_RDY_MSK 0x01000000
+#define RO_IQCAL_MULT_RDY_I_MSK 0xfeffffff
+#define RO_IQCAL_MULT_RDY_SFT 24
+#define RO_IQCAL_MULT_RDY_HI 24
+#define RO_IQCAL_MULT_RDY_SZ 1
+#define RO_FFT_ENRG_RDY_MSK 0x02000000
+#define RO_FFT_ENRG_RDY_I_MSK 0xfdffffff
+#define RO_FFT_ENRG_RDY_SFT 25
+#define RO_FFT_ENRG_RDY_HI 25
+#define RO_FFT_ENRG_RDY_SZ 1
+#define RO_PHEST_RDY_MSK 0x04000000
+#define RO_PHEST_RDY_I_MSK 0xfbffffff
+#define RO_PHEST_RDY_SFT 26
+#define RO_PHEST_RDY_HI 26
+#define RO_PHEST_RDY_SZ 1
+#define RO_GP_DIV_RDY_MSK 0x08000000
+#define RO_GP_DIV_RDY_I_MSK 0xf7ffffff
+#define RO_GP_DIV_RDY_SFT 27
+#define RO_GP_DIV_RDY_HI 27
+#define RO_GP_DIV_RDY_SZ 1
+#define RO_GAIN_EST_RDY_MSK 0x10000000
+#define RO_GAIN_EST_RDY_I_MSK 0xefffffff
+#define RO_GAIN_EST_RDY_SFT 28
+#define RO_GAIN_EST_RDY_HI 28
+#define RO_GAIN_EST_RDY_SZ 1
+#define RO_AMP_O_MSK 0x000001ff
+#define RO_AMP_O_I_MSK 0xfffffe00
+#define RO_AMP_O_SFT 0
+#define RO_AMP_O_HI 8
+#define RO_AMP_O_SZ 9
+#define RG_RX_I_SCALE_MSK 0x000000ff
+#define RG_RX_I_SCALE_I_MSK 0xffffff00
+#define RG_RX_I_SCALE_SFT 0
+#define RG_RX_I_SCALE_HI 7
+#define RG_RX_I_SCALE_SZ 8
+#define RG_RX_Q_SCALE_MSK 0x0000ff00
+#define RG_RX_Q_SCALE_I_MSK 0xffff00ff
+#define RG_RX_Q_SCALE_SFT 8
+#define RG_RX_Q_SCALE_HI 15
+#define RG_RX_Q_SCALE_SZ 8
+#define RG_RX_I_OFFSET_MSK 0x00ff0000
+#define RG_RX_I_OFFSET_I_MSK 0xff00ffff
+#define RG_RX_I_OFFSET_SFT 16
+#define RG_RX_I_OFFSET_HI 23
+#define RG_RX_I_OFFSET_SZ 8
+#define RG_RX_Q_OFFSET_MSK 0xff000000
+#define RG_RX_Q_OFFSET_I_MSK 0x00ffffff
+#define RG_RX_Q_OFFSET_SFT 24
+#define RG_RX_Q_OFFSET_HI 31
+#define RG_RX_Q_OFFSET_SZ 8
+#define RG_RX_IQ_SWP_MSK 0x00000001
+#define RG_RX_IQ_SWP_I_MSK 0xfffffffe
+#define RG_RX_IQ_SWP_SFT 0
+#define RG_RX_IQ_SWP_HI 0
+#define RG_RX_IQ_SWP_SZ 1
+#define RG_RX_SGN_IN_MSK 0x00000002
+#define RG_RX_SGN_IN_I_MSK 0xfffffffd
+#define RG_RX_SGN_IN_SFT 1
+#define RG_RX_SGN_IN_HI 1
+#define RG_RX_SGN_IN_SZ 1
+#define RG_RX_IQ_SRC_MSK 0x0000000c
+#define RG_RX_IQ_SRC_I_MSK 0xfffffff3
+#define RG_RX_IQ_SRC_SFT 2
+#define RG_RX_IQ_SRC_HI 3
+#define RG_RX_IQ_SRC_SZ 2
+#define RG_ACI_GAIN_MSK 0x00000ff0
+#define RG_ACI_GAIN_I_MSK 0xfffff00f
+#define RG_ACI_GAIN_SFT 4
+#define RG_ACI_GAIN_HI 11
+#define RG_ACI_GAIN_SZ 8
+#define RG_FFT_EN_MSK 0x00001000
+#define RG_FFT_EN_I_MSK 0xffffefff
+#define RG_FFT_EN_SFT 12
+#define RG_FFT_EN_HI 12
+#define RG_FFT_EN_SZ 1
+#define RG_FFT_MOD_MSK 0x00002000
+#define RG_FFT_MOD_I_MSK 0xffffdfff
+#define RG_FFT_MOD_SFT 13
+#define RG_FFT_MOD_HI 13
+#define RG_FFT_MOD_SZ 1
+#define RG_FFT_SCALE_MSK 0x00ffc000
+#define RG_FFT_SCALE_I_MSK 0xff003fff
+#define RG_FFT_SCALE_SFT 14
+#define RG_FFT_SCALE_HI 23
+#define RG_FFT_SCALE_SZ 10
+#define RG_FFT_ENRG_FREQ_MSK 0x3f000000
+#define RG_FFT_ENRG_FREQ_I_MSK 0xc0ffffff
+#define RG_FFT_ENRG_FREQ_SFT 24
+#define RG_FFT_ENRG_FREQ_HI 29
+#define RG_FFT_ENRG_FREQ_SZ 6
+#define RG_FPGA_80M_PH_UP_MSK 0x40000000
+#define RG_FPGA_80M_PH_UP_I_MSK 0xbfffffff
+#define RG_FPGA_80M_PH_UP_SFT 30
+#define RG_FPGA_80M_PH_UP_HI 30
+#define RG_FPGA_80M_PH_UP_SZ 1
+#define RG_FPGA_80M_PH_STP_MSK 0x80000000
+#define RG_FPGA_80M_PH_STP_I_MSK 0x7fffffff
+#define RG_FPGA_80M_PH_STP_SFT 31
+#define RG_FPGA_80M_PH_STP_HI 31
+#define RG_FPGA_80M_PH_STP_SZ 1
+#define RG_ADC2LA_SEL_MSK 0x00000001
+#define RG_ADC2LA_SEL_I_MSK 0xfffffffe
+#define RG_ADC2LA_SEL_SFT 0
+#define RG_ADC2LA_SEL_HI 0
+#define RG_ADC2LA_SEL_SZ 1
+#define RG_ADC2LA_CLKPH_MSK 0x00000002
+#define RG_ADC2LA_CLKPH_I_MSK 0xfffffffd
+#define RG_ADC2LA_CLKPH_SFT 1
+#define RG_ADC2LA_CLKPH_HI 1
+#define RG_ADC2LA_CLKPH_SZ 1
+#define RG_RXIQ_EMU_IDX_MSK 0x0000000f
+#define RG_RXIQ_EMU_IDX_I_MSK 0xfffffff0
+#define RG_RXIQ_EMU_IDX_SFT 0
+#define RG_RXIQ_EMU_IDX_HI 3
+#define RG_RXIQ_EMU_IDX_SZ 4
+#define RG_IQCAL_BP_ACI_MSK 0x00000010
+#define RG_IQCAL_BP_ACI_I_MSK 0xffffffef
+#define RG_IQCAL_BP_ACI_SFT 4
+#define RG_IQCAL_BP_ACI_HI 4
+#define RG_IQCAL_BP_ACI_SZ 1
+#define RG_DPD_AM_EN_MSK 0x00000001
+#define RG_DPD_AM_EN_I_MSK 0xfffffffe
+#define RG_DPD_AM_EN_SFT 0
+#define RG_DPD_AM_EN_HI 0
+#define RG_DPD_AM_EN_SZ 1
+#define RG_DPD_PM_EN_MSK 0x00000002
+#define RG_DPD_PM_EN_I_MSK 0xfffffffd
+#define RG_DPD_PM_EN_SFT 1
+#define RG_DPD_PM_EN_HI 1
+#define RG_DPD_PM_EN_SZ 1
+#define RG_DPD_PM_AMSEL_MSK 0x00000004
+#define RG_DPD_PM_AMSEL_I_MSK 0xfffffffb
+#define RG_DPD_PM_AMSEL_SFT 2
+#define RG_DPD_PM_AMSEL_HI 2
+#define RG_DPD_PM_AMSEL_SZ 1
+#define RG_DPD_020_GAIN_MSK 0x000003ff
+#define RG_DPD_020_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_020_GAIN_SFT 0
+#define RG_DPD_020_GAIN_HI 9
+#define RG_DPD_020_GAIN_SZ 10
+#define RG_DPD_040_GAIN_MSK 0x03ff0000
+#define RG_DPD_040_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_040_GAIN_SFT 16
+#define RG_DPD_040_GAIN_HI 25
+#define RG_DPD_040_GAIN_SZ 10
+#define RG_DPD_060_GAIN_MSK 0x000003ff
+#define RG_DPD_060_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_060_GAIN_SFT 0
+#define RG_DPD_060_GAIN_HI 9
+#define RG_DPD_060_GAIN_SZ 10
+#define RG_DPD_080_GAIN_MSK 0x03ff0000
+#define RG_DPD_080_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_080_GAIN_SFT 16
+#define RG_DPD_080_GAIN_HI 25
+#define RG_DPD_080_GAIN_SZ 10
+#define RG_DPD_0A0_GAIN_MSK 0x000003ff
+#define RG_DPD_0A0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_0A0_GAIN_SFT 0
+#define RG_DPD_0A0_GAIN_HI 9
+#define RG_DPD_0A0_GAIN_SZ 10
+#define RG_DPD_0C0_GAIN_MSK 0x03ff0000
+#define RG_DPD_0C0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_0C0_GAIN_SFT 16
+#define RG_DPD_0C0_GAIN_HI 25
+#define RG_DPD_0C0_GAIN_SZ 10
+#define RG_DPD_0D0_GAIN_MSK 0x000003ff
+#define RG_DPD_0D0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_0D0_GAIN_SFT 0
+#define RG_DPD_0D0_GAIN_HI 9
+#define RG_DPD_0D0_GAIN_SZ 10
+#define RG_DPD_0E0_GAIN_MSK 0x03ff0000
+#define RG_DPD_0E0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_0E0_GAIN_SFT 16
+#define RG_DPD_0E0_GAIN_HI 25
+#define RG_DPD_0E0_GAIN_SZ 10
+#define RG_DPD_0F0_GAIN_MSK 0x000003ff
+#define RG_DPD_0F0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_0F0_GAIN_SFT 0
+#define RG_DPD_0F0_GAIN_HI 9
+#define RG_DPD_0F0_GAIN_SZ 10
+#define RG_DPD_100_GAIN_MSK 0x03ff0000
+#define RG_DPD_100_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_100_GAIN_SFT 16
+#define RG_DPD_100_GAIN_HI 25
+#define RG_DPD_100_GAIN_SZ 10
+#define RG_DPD_110_GAIN_MSK 0x000003ff
+#define RG_DPD_110_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_110_GAIN_SFT 0
+#define RG_DPD_110_GAIN_HI 9
+#define RG_DPD_110_GAIN_SZ 10
+#define RG_DPD_120_GAIN_MSK 0x03ff0000
+#define RG_DPD_120_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_120_GAIN_SFT 16
+#define RG_DPD_120_GAIN_HI 25
+#define RG_DPD_120_GAIN_SZ 10
+#define RG_DPD_130_GAIN_MSK 0x000003ff
+#define RG_DPD_130_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_130_GAIN_SFT 0
+#define RG_DPD_130_GAIN_HI 9
+#define RG_DPD_130_GAIN_SZ 10
+#define RG_DPD_140_GAIN_MSK 0x03ff0000
+#define RG_DPD_140_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_140_GAIN_SFT 16
+#define RG_DPD_140_GAIN_HI 25
+#define RG_DPD_140_GAIN_SZ 10
+#define RG_DPD_150_GAIN_MSK 0x000003ff
+#define RG_DPD_150_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_150_GAIN_SFT 0
+#define RG_DPD_150_GAIN_HI 9
+#define RG_DPD_150_GAIN_SZ 10
+#define RG_DPD_160_GAIN_MSK 0x03ff0000
+#define RG_DPD_160_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_160_GAIN_SFT 16
+#define RG_DPD_160_GAIN_HI 25
+#define RG_DPD_160_GAIN_SZ 10
+#define RG_DPD_170_GAIN_MSK 0x000003ff
+#define RG_DPD_170_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_170_GAIN_SFT 0
+#define RG_DPD_170_GAIN_HI 9
+#define RG_DPD_170_GAIN_SZ 10
+#define RG_DPD_180_GAIN_MSK 0x03ff0000
+#define RG_DPD_180_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_180_GAIN_SFT 16
+#define RG_DPD_180_GAIN_HI 25
+#define RG_DPD_180_GAIN_SZ 10
+#define RG_DPD_190_GAIN_MSK 0x000003ff
+#define RG_DPD_190_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_190_GAIN_SFT 0
+#define RG_DPD_190_GAIN_HI 9
+#define RG_DPD_190_GAIN_SZ 10
+#define RG_DPD_1A0_GAIN_MSK 0x03ff0000
+#define RG_DPD_1A0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_1A0_GAIN_SFT 16
+#define RG_DPD_1A0_GAIN_HI 25
+#define RG_DPD_1A0_GAIN_SZ 10
+#define RG_DPD_1B0_GAIN_MSK 0x000003ff
+#define RG_DPD_1B0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_1B0_GAIN_SFT 0
+#define RG_DPD_1B0_GAIN_HI 9
+#define RG_DPD_1B0_GAIN_SZ 10
+#define RG_DPD_1C0_GAIN_MSK 0x03ff0000
+#define RG_DPD_1C0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_1C0_GAIN_SFT 16
+#define RG_DPD_1C0_GAIN_HI 25
+#define RG_DPD_1C0_GAIN_SZ 10
+#define RG_DPD_1D0_GAIN_MSK 0x000003ff
+#define RG_DPD_1D0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_1D0_GAIN_SFT 0
+#define RG_DPD_1D0_GAIN_HI 9
+#define RG_DPD_1D0_GAIN_SZ 10
+#define RG_DPD_1E0_GAIN_MSK 0x03ff0000
+#define RG_DPD_1E0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_1E0_GAIN_SFT 16
+#define RG_DPD_1E0_GAIN_HI 25
+#define RG_DPD_1E0_GAIN_SZ 10
+#define RG_DPD_1F0_GAIN_MSK 0x000003ff
+#define RG_DPD_1F0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_1F0_GAIN_SFT 0
+#define RG_DPD_1F0_GAIN_HI 9
+#define RG_DPD_1F0_GAIN_SZ 10
+#define RG_DPD_200_GAIN_MSK 0x03ff0000
+#define RG_DPD_200_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_200_GAIN_SFT 16
+#define RG_DPD_200_GAIN_HI 25
+#define RG_DPD_200_GAIN_SZ 10
+#define RG_DPD_020_PH_MSK 0x00001fff
+#define RG_DPD_020_PH_I_MSK 0xffffe000
+#define RG_DPD_020_PH_SFT 0
+#define RG_DPD_020_PH_HI 12
+#define RG_DPD_020_PH_SZ 13
+#define RG_DPD_040_PH_MSK 0x1fff0000
+#define RG_DPD_040_PH_I_MSK 0xe000ffff
+#define RG_DPD_040_PH_SFT 16
+#define RG_DPD_040_PH_HI 28
+#define RG_DPD_040_PH_SZ 13
+#define RG_DPD_060_PH_MSK 0x00001fff
+#define RG_DPD_060_PH_I_MSK 0xffffe000
+#define RG_DPD_060_PH_SFT 0
+#define RG_DPD_060_PH_HI 12
+#define RG_DPD_060_PH_SZ 13
+#define RG_DPD_080_PH_MSK 0x1fff0000
+#define RG_DPD_080_PH_I_MSK 0xe000ffff
+#define RG_DPD_080_PH_SFT 16
+#define RG_DPD_080_PH_HI 28
+#define RG_DPD_080_PH_SZ 13
+#define RG_DPD_0A0_PH_MSK 0x00001fff
+#define RG_DPD_0A0_PH_I_MSK 0xffffe000
+#define RG_DPD_0A0_PH_SFT 0
+#define RG_DPD_0A0_PH_HI 12
+#define RG_DPD_0A0_PH_SZ 13
+#define RG_DPD_0C0_PH_MSK 0x1fff0000
+#define RG_DPD_0C0_PH_I_MSK 0xe000ffff
+#define RG_DPD_0C0_PH_SFT 16
+#define RG_DPD_0C0_PH_HI 28
+#define RG_DPD_0C0_PH_SZ 13
+#define RG_DPD_0D0_PH_MSK 0x00001fff
+#define RG_DPD_0D0_PH_I_MSK 0xffffe000
+#define RG_DPD_0D0_PH_SFT 0
+#define RG_DPD_0D0_PH_HI 12
+#define RG_DPD_0D0_PH_SZ 13
+#define RG_DPD_0E0_PH_MSK 0x1fff0000
+#define RG_DPD_0E0_PH_I_MSK 0xe000ffff
+#define RG_DPD_0E0_PH_SFT 16
+#define RG_DPD_0E0_PH_HI 28
+#define RG_DPD_0E0_PH_SZ 13
+#define RG_DPD_0F0_PH_MSK 0x00001fff
+#define RG_DPD_0F0_PH_I_MSK 0xffffe000
+#define RG_DPD_0F0_PH_SFT 0
+#define RG_DPD_0F0_PH_HI 12
+#define RG_DPD_0F0_PH_SZ 13
+#define RG_DPD_100_PH_MSK 0x1fff0000
+#define RG_DPD_100_PH_I_MSK 0xe000ffff
+#define RG_DPD_100_PH_SFT 16
+#define RG_DPD_100_PH_HI 28
+#define RG_DPD_100_PH_SZ 13
+#define RG_DPD_110_PH_MSK 0x00001fff
+#define RG_DPD_110_PH_I_MSK 0xffffe000
+#define RG_DPD_110_PH_SFT 0
+#define RG_DPD_110_PH_HI 12
+#define RG_DPD_110_PH_SZ 13
+#define RG_DPD_120_PH_MSK 0x1fff0000
+#define RG_DPD_120_PH_I_MSK 0xe000ffff
+#define RG_DPD_120_PH_SFT 16
+#define RG_DPD_120_PH_HI 28
+#define RG_DPD_120_PH_SZ 13
+#define RG_DPD_130_PH_MSK 0x00001fff
+#define RG_DPD_130_PH_I_MSK 0xffffe000
+#define RG_DPD_130_PH_SFT 0
+#define RG_DPD_130_PH_HI 12
+#define RG_DPD_130_PH_SZ 13
+#define RG_DPD_140_PH_MSK 0x1fff0000
+#define RG_DPD_140_PH_I_MSK 0xe000ffff
+#define RG_DPD_140_PH_SFT 16
+#define RG_DPD_140_PH_HI 28
+#define RG_DPD_140_PH_SZ 13
+#define RG_DPD_150_PH_MSK 0x00001fff
+#define RG_DPD_150_PH_I_MSK 0xffffe000
+#define RG_DPD_150_PH_SFT 0
+#define RG_DPD_150_PH_HI 12
+#define RG_DPD_150_PH_SZ 13
+#define RG_DPD_160_PH_MSK 0x1fff0000
+#define RG_DPD_160_PH_I_MSK 0xe000ffff
+#define RG_DPD_160_PH_SFT 16
+#define RG_DPD_160_PH_HI 28
+#define RG_DPD_160_PH_SZ 13
+#define RG_DPD_170_PH_MSK 0x00001fff
+#define RG_DPD_170_PH_I_MSK 0xffffe000
+#define RG_DPD_170_PH_SFT 0
+#define RG_DPD_170_PH_HI 12
+#define RG_DPD_170_PH_SZ 13
+#define RG_DPD_180_PH_MSK 0x1fff0000
+#define RG_DPD_180_PH_I_MSK 0xe000ffff
+#define RG_DPD_180_PH_SFT 16
+#define RG_DPD_180_PH_HI 28
+#define RG_DPD_180_PH_SZ 13
+#define RG_DPD_190_PH_MSK 0x00001fff
+#define RG_DPD_190_PH_I_MSK 0xffffe000
+#define RG_DPD_190_PH_SFT 0
+#define RG_DPD_190_PH_HI 12
+#define RG_DPD_190_PH_SZ 13
+#define RG_DPD_1A0_PH_MSK 0x1fff0000
+#define RG_DPD_1A0_PH_I_MSK 0xe000ffff
+#define RG_DPD_1A0_PH_SFT 16
+#define RG_DPD_1A0_PH_HI 28
+#define RG_DPD_1A0_PH_SZ 13
+#define RG_DPD_1B0_PH_MSK 0x00001fff
+#define RG_DPD_1B0_PH_I_MSK 0xffffe000
+#define RG_DPD_1B0_PH_SFT 0
+#define RG_DPD_1B0_PH_HI 12
+#define RG_DPD_1B0_PH_SZ 13
+#define RG_DPD_1C0_PH_MSK 0x1fff0000
+#define RG_DPD_1C0_PH_I_MSK 0xe000ffff
+#define RG_DPD_1C0_PH_SFT 16
+#define RG_DPD_1C0_PH_HI 28
+#define RG_DPD_1C0_PH_SZ 13
+#define RG_DPD_1D0_PH_MSK 0x00001fff
+#define RG_DPD_1D0_PH_I_MSK 0xffffe000
+#define RG_DPD_1D0_PH_SFT 0
+#define RG_DPD_1D0_PH_HI 12
+#define RG_DPD_1D0_PH_SZ 13
+#define RG_DPD_1E0_PH_MSK 0x1fff0000
+#define RG_DPD_1E0_PH_I_MSK 0xe000ffff
+#define RG_DPD_1E0_PH_SFT 16
+#define RG_DPD_1E0_PH_HI 28
+#define RG_DPD_1E0_PH_SZ 13
+#define RG_DPD_1F0_PH_MSK 0x00001fff
+#define RG_DPD_1F0_PH_I_MSK 0xffffe000
+#define RG_DPD_1F0_PH_SFT 0
+#define RG_DPD_1F0_PH_HI 12
+#define RG_DPD_1F0_PH_SZ 13
+#define RG_DPD_200_PH_MSK 0x1fff0000
+#define RG_DPD_200_PH_I_MSK 0xe000ffff
+#define RG_DPD_200_PH_SFT 16
+#define RG_DPD_200_PH_HI 28
+#define RG_DPD_200_PH_SZ 13
+#define RG_DPD_GAIN_EST_Y0_MSK 0x000001ff
+#define RG_DPD_GAIN_EST_Y0_I_MSK 0xfffffe00
+#define RG_DPD_GAIN_EST_Y0_SFT 0
+#define RG_DPD_GAIN_EST_Y0_HI 8
+#define RG_DPD_GAIN_EST_Y0_SZ 9
+#define RG_DPD_GAIN_EST_Y1_MSK 0x01ff0000
+#define RG_DPD_GAIN_EST_Y1_I_MSK 0xfe00ffff
+#define RG_DPD_GAIN_EST_Y1_SFT 16
+#define RG_DPD_GAIN_EST_Y1_HI 24
+#define RG_DPD_GAIN_EST_Y1_SZ 9
+#define RG_DPD_LOOP_GAIN_MSK 0x000003ff
+#define RG_DPD_LOOP_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_LOOP_GAIN_SFT 0
+#define RG_DPD_LOOP_GAIN_HI 9
+#define RG_DPD_LOOP_GAIN_SZ 10
+#define RG_DPD_GAIN_EST_X0_MSK 0x000001ff
+#define RG_DPD_GAIN_EST_X0_I_MSK 0xfffffe00
+#define RG_DPD_GAIN_EST_X0_SFT 0
+#define RG_DPD_GAIN_EST_X0_HI 8
+#define RG_DPD_GAIN_EST_X0_SZ 9
+#define RO_DPD_GAIN_MSK 0x03ff0000
+#define RO_DPD_GAIN_I_MSK 0xfc00ffff
+#define RO_DPD_GAIN_SFT 16
+#define RO_DPD_GAIN_HI 25
+#define RO_DPD_GAIN_SZ 10
+#define TX_SCALE_11B_MSK 0x000000ff
+#define TX_SCALE_11B_I_MSK 0xffffff00
+#define TX_SCALE_11B_SFT 0
+#define TX_SCALE_11B_HI 7
+#define TX_SCALE_11B_SZ 8
+#define TX_SCALE_11B_P0D5_MSK 0x0000ff00
+#define TX_SCALE_11B_P0D5_I_MSK 0xffff00ff
+#define TX_SCALE_11B_P0D5_SFT 8
+#define TX_SCALE_11B_P0D5_HI 15
+#define TX_SCALE_11B_P0D5_SZ 8
+#define TX_SCALE_11G_MSK 0x00ff0000
+#define TX_SCALE_11G_I_MSK 0xff00ffff
+#define TX_SCALE_11G_SFT 16
+#define TX_SCALE_11G_HI 23
+#define TX_SCALE_11G_SZ 8
+#define TX_SCALE_11G_P0D5_MSK 0xff000000
+#define TX_SCALE_11G_P0D5_I_MSK 0x00ffffff
+#define TX_SCALE_11G_P0D5_SFT 24
+#define TX_SCALE_11G_P0D5_HI 31
+#define TX_SCALE_11G_P0D5_SZ 8
+#define RG_EN_MANUAL_MSK 0x00000001
+#define RG_EN_MANUAL_I_MSK 0xfffffffe
+#define RG_EN_MANUAL_SFT 0
+#define RG_EN_MANUAL_HI 0
+#define RG_EN_MANUAL_SZ 1
+#define RG_TX_EN_MSK 0x00000002
+#define RG_TX_EN_I_MSK 0xfffffffd
+#define RG_TX_EN_SFT 1
+#define RG_TX_EN_HI 1
+#define RG_TX_EN_SZ 1
+#define RG_TX_PA_EN_MSK 0x00000004
+#define RG_TX_PA_EN_I_MSK 0xfffffffb
+#define RG_TX_PA_EN_SFT 2
+#define RG_TX_PA_EN_HI 2
+#define RG_TX_PA_EN_SZ 1
+#define RG_TX_DAC_EN_MSK 0x00000008
+#define RG_TX_DAC_EN_I_MSK 0xfffffff7
+#define RG_TX_DAC_EN_SFT 3
+#define RG_TX_DAC_EN_HI 3
+#define RG_TX_DAC_EN_SZ 1
+#define RG_RX_AGC_MSK 0x00000010
+#define RG_RX_AGC_I_MSK 0xffffffef
+#define RG_RX_AGC_SFT 4
+#define RG_RX_AGC_HI 4
+#define RG_RX_AGC_SZ 1
+#define RG_RX_GAIN_MANUAL_MSK 0x00000020
+#define RG_RX_GAIN_MANUAL_I_MSK 0xffffffdf
+#define RG_RX_GAIN_MANUAL_SFT 5
+#define RG_RX_GAIN_MANUAL_HI 5
+#define RG_RX_GAIN_MANUAL_SZ 1
+#define RG_RFG_MSK 0x000000c0
+#define RG_RFG_I_MSK 0xffffff3f
+#define RG_RFG_SFT 6
+#define RG_RFG_HI 7
+#define RG_RFG_SZ 2
+#define RG_PGAG_MSK 0x00000f00
+#define RG_PGAG_I_MSK 0xfffff0ff
+#define RG_PGAG_SFT 8
+#define RG_PGAG_HI 11
+#define RG_PGAG_SZ 4
+#define RG_MODE_MSK 0x00003000
+#define RG_MODE_I_MSK 0xffffcfff
+#define RG_MODE_SFT 12
+#define RG_MODE_HI 13
+#define RG_MODE_SZ 2
+#define RG_EN_TX_TRSW_MSK 0x00004000
+#define RG_EN_TX_TRSW_I_MSK 0xffffbfff
+#define RG_EN_TX_TRSW_SFT 14
+#define RG_EN_TX_TRSW_HI 14
+#define RG_EN_TX_TRSW_SZ 1
+#define RG_EN_SX_MSK 0x00008000
+#define RG_EN_SX_I_MSK 0xffff7fff
+#define RG_EN_SX_SFT 15
+#define RG_EN_SX_HI 15
+#define RG_EN_SX_SZ 1
+#define RG_EN_RX_LNA_MSK 0x00010000
+#define RG_EN_RX_LNA_I_MSK 0xfffeffff
+#define RG_EN_RX_LNA_SFT 16
+#define RG_EN_RX_LNA_HI 16
+#define RG_EN_RX_LNA_SZ 1
+#define RG_EN_RX_MIXER_MSK 0x00020000
+#define RG_EN_RX_MIXER_I_MSK 0xfffdffff
+#define RG_EN_RX_MIXER_SFT 17
+#define RG_EN_RX_MIXER_HI 17
+#define RG_EN_RX_MIXER_SZ 1
+#define RG_EN_RX_DIV2_MSK 0x00040000
+#define RG_EN_RX_DIV2_I_MSK 0xfffbffff
+#define RG_EN_RX_DIV2_SFT 18
+#define RG_EN_RX_DIV2_HI 18
+#define RG_EN_RX_DIV2_SZ 1
+#define RG_EN_RX_LOBUF_MSK 0x00080000
+#define RG_EN_RX_LOBUF_I_MSK 0xfff7ffff
+#define RG_EN_RX_LOBUF_SFT 19
+#define RG_EN_RX_LOBUF_HI 19
+#define RG_EN_RX_LOBUF_SZ 1
+#define RG_EN_RX_TZ_MSK 0x00100000
+#define RG_EN_RX_TZ_I_MSK 0xffefffff
+#define RG_EN_RX_TZ_SFT 20
+#define RG_EN_RX_TZ_HI 20
+#define RG_EN_RX_TZ_SZ 1
+#define RG_EN_RX_FILTER_MSK 0x00200000
+#define RG_EN_RX_FILTER_I_MSK 0xffdfffff
+#define RG_EN_RX_FILTER_SFT 21
+#define RG_EN_RX_FILTER_HI 21
+#define RG_EN_RX_FILTER_SZ 1
+#define RG_EN_RX_HPF_MSK 0x00400000
+#define RG_EN_RX_HPF_I_MSK 0xffbfffff
+#define RG_EN_RX_HPF_SFT 22
+#define RG_EN_RX_HPF_HI 22
+#define RG_EN_RX_HPF_SZ 1
+#define RG_EN_RX_RSSI_MSK 0x00800000
+#define RG_EN_RX_RSSI_I_MSK 0xff7fffff
+#define RG_EN_RX_RSSI_SFT 23
+#define RG_EN_RX_RSSI_HI 23
+#define RG_EN_RX_RSSI_SZ 1
+#define RG_EN_ADC_MSK 0x01000000
+#define RG_EN_ADC_I_MSK 0xfeffffff
+#define RG_EN_ADC_SFT 24
+#define RG_EN_ADC_HI 24
+#define RG_EN_ADC_SZ 1
+#define RG_EN_TX_MOD_MSK 0x02000000
+#define RG_EN_TX_MOD_I_MSK 0xfdffffff
+#define RG_EN_TX_MOD_SFT 25
+#define RG_EN_TX_MOD_HI 25
+#define RG_EN_TX_MOD_SZ 1
+#define RG_EN_TX_DIV2_MSK 0x04000000
+#define RG_EN_TX_DIV2_I_MSK 0xfbffffff
+#define RG_EN_TX_DIV2_SFT 26
+#define RG_EN_TX_DIV2_HI 26
+#define RG_EN_TX_DIV2_SZ 1
+#define RG_EN_TX_DIV2_BUF_MSK 0x08000000
+#define RG_EN_TX_DIV2_BUF_I_MSK 0xf7ffffff
+#define RG_EN_TX_DIV2_BUF_SFT 27
+#define RG_EN_TX_DIV2_BUF_HI 27
+#define RG_EN_TX_DIV2_BUF_SZ 1
+#define RG_EN_TX_LOBF_MSK 0x10000000
+#define RG_EN_TX_LOBF_I_MSK 0xefffffff
+#define RG_EN_TX_LOBF_SFT 28
+#define RG_EN_TX_LOBF_HI 28
+#define RG_EN_TX_LOBF_SZ 1
+#define RG_EN_RX_LOBF_MSK 0x20000000
+#define RG_EN_RX_LOBF_I_MSK 0xdfffffff
+#define RG_EN_RX_LOBF_SFT 29
+#define RG_EN_RX_LOBF_HI 29
+#define RG_EN_RX_LOBF_SZ 1
+#define RG_SEL_DPLL_CLK_MSK 0x40000000
+#define RG_SEL_DPLL_CLK_I_MSK 0xbfffffff
+#define RG_SEL_DPLL_CLK_SFT 30
+#define RG_SEL_DPLL_CLK_HI 30
+#define RG_SEL_DPLL_CLK_SZ 1
+#define RG_EN_CLK_960MBY13_UART_MSK 0x80000000
+#define RG_EN_CLK_960MBY13_UART_I_MSK 0x7fffffff
+#define RG_EN_CLK_960MBY13_UART_SFT 31
+#define RG_EN_CLK_960MBY13_UART_HI 31
+#define RG_EN_CLK_960MBY13_UART_SZ 1
+#define RG_EN_TX_DPD_MSK 0x00000001
+#define RG_EN_TX_DPD_I_MSK 0xfffffffe
+#define RG_EN_TX_DPD_SFT 0
+#define RG_EN_TX_DPD_HI 0
+#define RG_EN_TX_DPD_SZ 1
+#define RG_EN_TX_TSSI_MSK 0x00000002
+#define RG_EN_TX_TSSI_I_MSK 0xfffffffd
+#define RG_EN_TX_TSSI_SFT 1
+#define RG_EN_TX_TSSI_HI 1
+#define RG_EN_TX_TSSI_SZ 1
+#define RG_EN_RX_IQCAL_MSK 0x00000004
+#define RG_EN_RX_IQCAL_I_MSK 0xfffffffb
+#define RG_EN_RX_IQCAL_SFT 2
+#define RG_EN_RX_IQCAL_HI 2
+#define RG_EN_RX_IQCAL_SZ 1
+#define RG_EN_TX_DAC_CAL_MSK 0x00000008
+#define RG_EN_TX_DAC_CAL_I_MSK 0xfffffff7
+#define RG_EN_TX_DAC_CAL_SFT 3
+#define RG_EN_TX_DAC_CAL_HI 3
+#define RG_EN_TX_DAC_CAL_SZ 1
+#define RG_EN_TX_SELF_MIXER_MSK 0x00000010
+#define RG_EN_TX_SELF_MIXER_I_MSK 0xffffffef
+#define RG_EN_TX_SELF_MIXER_SFT 4
+#define RG_EN_TX_SELF_MIXER_HI 4
+#define RG_EN_TX_SELF_MIXER_SZ 1
+#define RG_EN_TX_DAC_OUT_MSK 0x00000020
+#define RG_EN_TX_DAC_OUT_I_MSK 0xffffffdf
+#define RG_EN_TX_DAC_OUT_SFT 5
+#define RG_EN_TX_DAC_OUT_HI 5
+#define RG_EN_TX_DAC_OUT_SZ 1
+#define RG_EN_LDO_RX_FE_MSK 0x00000040
+#define RG_EN_LDO_RX_FE_I_MSK 0xffffffbf
+#define RG_EN_LDO_RX_FE_SFT 6
+#define RG_EN_LDO_RX_FE_HI 6
+#define RG_EN_LDO_RX_FE_SZ 1
+#define RG_EN_LDO_ABB_MSK 0x00000080
+#define RG_EN_LDO_ABB_I_MSK 0xffffff7f
+#define RG_EN_LDO_ABB_SFT 7
+#define RG_EN_LDO_ABB_HI 7
+#define RG_EN_LDO_ABB_SZ 1
+#define RG_EN_LDO_AFE_MSK 0x00000100
+#define RG_EN_LDO_AFE_I_MSK 0xfffffeff
+#define RG_EN_LDO_AFE_SFT 8
+#define RG_EN_LDO_AFE_HI 8
+#define RG_EN_LDO_AFE_SZ 1
+#define RG_EN_SX_CHPLDO_MSK 0x00000200
+#define RG_EN_SX_CHPLDO_I_MSK 0xfffffdff
+#define RG_EN_SX_CHPLDO_SFT 9
+#define RG_EN_SX_CHPLDO_HI 9
+#define RG_EN_SX_CHPLDO_SZ 1
+#define RG_EN_SX_LOBFLDO_MSK 0x00000400
+#define RG_EN_SX_LOBFLDO_I_MSK 0xfffffbff
+#define RG_EN_SX_LOBFLDO_SFT 10
+#define RG_EN_SX_LOBFLDO_HI 10
+#define RG_EN_SX_LOBFLDO_SZ 1
+#define RG_EN_IREF_RX_MSK 0x00000800
+#define RG_EN_IREF_RX_I_MSK 0xfffff7ff
+#define RG_EN_IREF_RX_SFT 11
+#define RG_EN_IREF_RX_HI 11
+#define RG_EN_IREF_RX_SZ 1
+#define RG_EN_TX_DAC_VOUT_MSK 0x00002000
+#define RG_EN_TX_DAC_VOUT_I_MSK 0xffffdfff
+#define RG_EN_TX_DAC_VOUT_SFT 13
+#define RG_EN_TX_DAC_VOUT_HI 13
+#define RG_EN_TX_DAC_VOUT_SZ 1
+#define RG_EN_SX_LCK_BIN_MSK 0x00004000
+#define RG_EN_SX_LCK_BIN_I_MSK 0xffffbfff
+#define RG_EN_SX_LCK_BIN_SFT 14
+#define RG_EN_SX_LCK_BIN_HI 14
+#define RG_EN_SX_LCK_BIN_SZ 1
+#define RG_RTC_CAL_MODE_MSK 0x00010000
+#define RG_RTC_CAL_MODE_I_MSK 0xfffeffff
+#define RG_RTC_CAL_MODE_SFT 16
+#define RG_RTC_CAL_MODE_HI 16
+#define RG_RTC_CAL_MODE_SZ 1
+#define RG_EN_IQPAD_IOSW_MSK 0x00020000
+#define RG_EN_IQPAD_IOSW_I_MSK 0xfffdffff
+#define RG_EN_IQPAD_IOSW_SFT 17
+#define RG_EN_IQPAD_IOSW_HI 17
+#define RG_EN_IQPAD_IOSW_SZ 1
+#define RG_EN_TESTPAD_IOSW_MSK 0x00040000
+#define RG_EN_TESTPAD_IOSW_I_MSK 0xfffbffff
+#define RG_EN_TESTPAD_IOSW_SFT 18
+#define RG_EN_TESTPAD_IOSW_HI 18
+#define RG_EN_TESTPAD_IOSW_SZ 1
+#define RG_EN_TRXBF_BYPASS_MSK 0x00080000
+#define RG_EN_TRXBF_BYPASS_I_MSK 0xfff7ffff
+#define RG_EN_TRXBF_BYPASS_SFT 19
+#define RG_EN_TRXBF_BYPASS_HI 19
+#define RG_EN_TRXBF_BYPASS_SZ 1
+#define RG_LDO_LEVEL_RX_FE_MSK 0x00000007
+#define RG_LDO_LEVEL_RX_FE_I_MSK 0xfffffff8
+#define RG_LDO_LEVEL_RX_FE_SFT 0
+#define RG_LDO_LEVEL_RX_FE_HI 2
+#define RG_LDO_LEVEL_RX_FE_SZ 3
+#define RG_LDO_LEVEL_ABB_MSK 0x00000038
+#define RG_LDO_LEVEL_ABB_I_MSK 0xffffffc7
+#define RG_LDO_LEVEL_ABB_SFT 3
+#define RG_LDO_LEVEL_ABB_HI 5
+#define RG_LDO_LEVEL_ABB_SZ 3
+#define RG_LDO_LEVEL_AFE_MSK 0x000001c0
+#define RG_LDO_LEVEL_AFE_I_MSK 0xfffffe3f
+#define RG_LDO_LEVEL_AFE_SFT 6
+#define RG_LDO_LEVEL_AFE_HI 8
+#define RG_LDO_LEVEL_AFE_SZ 3
+#define RG_SX_LDO_CHP_LEVEL_MSK 0x00000e00
+#define RG_SX_LDO_CHP_LEVEL_I_MSK 0xfffff1ff
+#define RG_SX_LDO_CHP_LEVEL_SFT 9
+#define RG_SX_LDO_CHP_LEVEL_HI 11
+#define RG_SX_LDO_CHP_LEVEL_SZ 3
+#define RG_SX_LDO_LOBF_LEVEL_MSK 0x00007000
+#define RG_SX_LDO_LOBF_LEVEL_I_MSK 0xffff8fff
+#define RG_SX_LDO_LOBF_LEVEL_SFT 12
+#define RG_SX_LDO_LOBF_LEVEL_HI 14
+#define RG_SX_LDO_LOBF_LEVEL_SZ 3
+#define RG_SX_LDO_XOSC_LEVEL_MSK 0x00038000
+#define RG_SX_LDO_XOSC_LEVEL_I_MSK 0xfffc7fff
+#define RG_SX_LDO_XOSC_LEVEL_SFT 15
+#define RG_SX_LDO_XOSC_LEVEL_HI 17
+#define RG_SX_LDO_XOSC_LEVEL_SZ 3
+#define RG_DP_LDO_LEVEL_MSK 0x001c0000
+#define RG_DP_LDO_LEVEL_I_MSK 0xffe3ffff
+#define RG_DP_LDO_LEVEL_SFT 18
+#define RG_DP_LDO_LEVEL_HI 20
+#define RG_DP_LDO_LEVEL_SZ 3
+#define RG_SX_LDO_VCO_LEVEL_MSK 0x00e00000
+#define RG_SX_LDO_VCO_LEVEL_I_MSK 0xff1fffff
+#define RG_SX_LDO_VCO_LEVEL_SFT 21
+#define RG_SX_LDO_VCO_LEVEL_HI 23
+#define RG_SX_LDO_VCO_LEVEL_SZ 3
+#define RG_TX_LDO_TX_LEVEL_MSK 0x07000000
+#define RG_TX_LDO_TX_LEVEL_I_MSK 0xf8ffffff
+#define RG_TX_LDO_TX_LEVEL_SFT 24
+#define RG_TX_LDO_TX_LEVEL_HI 26
+#define RG_TX_LDO_TX_LEVEL_SZ 3
+#define RG_EN_RX_PADSW_MSK 0x00000001
+#define RG_EN_RX_PADSW_I_MSK 0xfffffffe
+#define RG_EN_RX_PADSW_SFT 0
+#define RG_EN_RX_PADSW_HI 0
+#define RG_EN_RX_PADSW_SZ 1
+#define RG_EN_RX_TESTNODE_MSK 0x00000002
+#define RG_EN_RX_TESTNODE_I_MSK 0xfffffffd
+#define RG_EN_RX_TESTNODE_SFT 1
+#define RG_EN_RX_TESTNODE_HI 1
+#define RG_EN_RX_TESTNODE_SZ 1
+#define RG_RX_ABBCFIX_MSK 0x00000004
+#define RG_RX_ABBCFIX_I_MSK 0xfffffffb
+#define RG_RX_ABBCFIX_SFT 2
+#define RG_RX_ABBCFIX_HI 2
+#define RG_RX_ABBCFIX_SZ 1
+#define RG_RX_ABBCTUNE_MSK 0x000001f8
+#define RG_RX_ABBCTUNE_I_MSK 0xfffffe07
+#define RG_RX_ABBCTUNE_SFT 3
+#define RG_RX_ABBCTUNE_HI 8
+#define RG_RX_ABBCTUNE_SZ 6
+#define RG_RX_ABBOUT_TRI_STATE_MSK 0x00000200
+#define RG_RX_ABBOUT_TRI_STATE_I_MSK 0xfffffdff
+#define RG_RX_ABBOUT_TRI_STATE_SFT 9
+#define RG_RX_ABBOUT_TRI_STATE_HI 9
+#define RG_RX_ABBOUT_TRI_STATE_SZ 1
+#define RG_RX_ABB_N_MODE_MSK 0x00000400
+#define RG_RX_ABB_N_MODE_I_MSK 0xfffffbff
+#define RG_RX_ABB_N_MODE_SFT 10
+#define RG_RX_ABB_N_MODE_HI 10
+#define RG_RX_ABB_N_MODE_SZ 1
+#define RG_RX_EN_LOOPA_MSK 0x00000800
+#define RG_RX_EN_LOOPA_I_MSK 0xfffff7ff
+#define RG_RX_EN_LOOPA_SFT 11
+#define RG_RX_EN_LOOPA_HI 11
+#define RG_RX_EN_LOOPA_SZ 1
+#define RG_RX_FILTERI1ST_MSK 0x00003000
+#define RG_RX_FILTERI1ST_I_MSK 0xffffcfff
+#define RG_RX_FILTERI1ST_SFT 12
+#define RG_RX_FILTERI1ST_HI 13
+#define RG_RX_FILTERI1ST_SZ 2
+#define RG_RX_FILTERI2ND_MSK 0x0000c000
+#define RG_RX_FILTERI2ND_I_MSK 0xffff3fff
+#define RG_RX_FILTERI2ND_SFT 14
+#define RG_RX_FILTERI2ND_HI 15
+#define RG_RX_FILTERI2ND_SZ 2
+#define RG_RX_FILTERI3RD_MSK 0x00030000
+#define RG_RX_FILTERI3RD_I_MSK 0xfffcffff
+#define RG_RX_FILTERI3RD_SFT 16
+#define RG_RX_FILTERI3RD_HI 17
+#define RG_RX_FILTERI3RD_SZ 2
+#define RG_RX_FILTERI_COURSE_MSK 0x000c0000
+#define RG_RX_FILTERI_COURSE_I_MSK 0xfff3ffff
+#define RG_RX_FILTERI_COURSE_SFT 18
+#define RG_RX_FILTERI_COURSE_HI 19
+#define RG_RX_FILTERI_COURSE_SZ 2
+#define RG_RX_FILTERVCM_MSK 0x00300000
+#define RG_RX_FILTERVCM_I_MSK 0xffcfffff
+#define RG_RX_FILTERVCM_SFT 20
+#define RG_RX_FILTERVCM_HI 21
+#define RG_RX_FILTERVCM_SZ 2
+#define RG_RX_HPF3M_MSK 0x00400000
+#define RG_RX_HPF3M_I_MSK 0xffbfffff
+#define RG_RX_HPF3M_SFT 22
+#define RG_RX_HPF3M_HI 22
+#define RG_RX_HPF3M_SZ 1
+#define RG_RX_HPF300K_MSK 0x00800000
+#define RG_RX_HPF300K_I_MSK 0xff7fffff
+#define RG_RX_HPF300K_SFT 23
+#define RG_RX_HPF300K_HI 23
+#define RG_RX_HPF300K_SZ 1
+#define RG_RX_HPFI_MSK 0x03000000
+#define RG_RX_HPFI_I_MSK 0xfcffffff
+#define RG_RX_HPFI_SFT 24
+#define RG_RX_HPFI_HI 25
+#define RG_RX_HPFI_SZ 2
+#define RG_RX_HPF_FINALCORNER_MSK 0x0c000000
+#define RG_RX_HPF_FINALCORNER_I_MSK 0xf3ffffff
+#define RG_RX_HPF_FINALCORNER_SFT 26
+#define RG_RX_HPF_FINALCORNER_HI 27
+#define RG_RX_HPF_FINALCORNER_SZ 2
+#define RG_RX_HPF_SETTLE1_C_MSK 0x30000000
+#define RG_RX_HPF_SETTLE1_C_I_MSK 0xcfffffff
+#define RG_RX_HPF_SETTLE1_C_SFT 28
+#define RG_RX_HPF_SETTLE1_C_HI 29
+#define RG_RX_HPF_SETTLE1_C_SZ 2
+#define RG_RX_HPF_SETTLE1_R_MSK 0x00000003
+#define RG_RX_HPF_SETTLE1_R_I_MSK 0xfffffffc
+#define RG_RX_HPF_SETTLE1_R_SFT 0
+#define RG_RX_HPF_SETTLE1_R_HI 1
+#define RG_RX_HPF_SETTLE1_R_SZ 2
+#define RG_RX_HPF_SETTLE2_C_MSK 0x0000000c
+#define RG_RX_HPF_SETTLE2_C_I_MSK 0xfffffff3
+#define RG_RX_HPF_SETTLE2_C_SFT 2
+#define RG_RX_HPF_SETTLE2_C_HI 3
+#define RG_RX_HPF_SETTLE2_C_SZ 2
+#define RG_RX_HPF_SETTLE2_R_MSK 0x00000030
+#define RG_RX_HPF_SETTLE2_R_I_MSK 0xffffffcf
+#define RG_RX_HPF_SETTLE2_R_SFT 4
+#define RG_RX_HPF_SETTLE2_R_HI 5
+#define RG_RX_HPF_SETTLE2_R_SZ 2
+#define RG_RX_HPF_VCMCON2_MSK 0x000000c0
+#define RG_RX_HPF_VCMCON2_I_MSK 0xffffff3f
+#define RG_RX_HPF_VCMCON2_SFT 6
+#define RG_RX_HPF_VCMCON2_HI 7
+#define RG_RX_HPF_VCMCON2_SZ 2
+#define RG_RX_HPF_VCMCON_MSK 0x00000300
+#define RG_RX_HPF_VCMCON_I_MSK 0xfffffcff
+#define RG_RX_HPF_VCMCON_SFT 8
+#define RG_RX_HPF_VCMCON_HI 9
+#define RG_RX_HPF_VCMCON_SZ 2
+#define RG_RX_OUTVCM_MSK 0x00000c00
+#define RG_RX_OUTVCM_I_MSK 0xfffff3ff
+#define RG_RX_OUTVCM_SFT 10
+#define RG_RX_OUTVCM_HI 11
+#define RG_RX_OUTVCM_SZ 2
+#define RG_RX_TZI_MSK 0x00003000
+#define RG_RX_TZI_I_MSK 0xffffcfff
+#define RG_RX_TZI_SFT 12
+#define RG_RX_TZI_HI 13
+#define RG_RX_TZI_SZ 2
+#define RG_RX_TZ_OUT_TRISTATE_MSK 0x00004000
+#define RG_RX_TZ_OUT_TRISTATE_I_MSK 0xffffbfff
+#define RG_RX_TZ_OUT_TRISTATE_SFT 14
+#define RG_RX_TZ_OUT_TRISTATE_HI 14
+#define RG_RX_TZ_OUT_TRISTATE_SZ 1
+#define RG_RX_TZ_VCM_MSK 0x00018000
+#define RG_RX_TZ_VCM_I_MSK 0xfffe7fff
+#define RG_RX_TZ_VCM_SFT 15
+#define RG_RX_TZ_VCM_HI 16
+#define RG_RX_TZ_VCM_SZ 2
+#define RG_EN_RX_RSSI_TESTNODE_MSK 0x000e0000
+#define RG_EN_RX_RSSI_TESTNODE_I_MSK 0xfff1ffff
+#define RG_EN_RX_RSSI_TESTNODE_SFT 17
+#define RG_EN_RX_RSSI_TESTNODE_HI 19
+#define RG_EN_RX_RSSI_TESTNODE_SZ 3
+#define RG_RX_ADCRSSI_CLKSEL_MSK 0x00100000
+#define RG_RX_ADCRSSI_CLKSEL_I_MSK 0xffefffff
+#define RG_RX_ADCRSSI_CLKSEL_SFT 20
+#define RG_RX_ADCRSSI_CLKSEL_HI 20
+#define RG_RX_ADCRSSI_CLKSEL_SZ 1
+#define RG_RX_ADCRSSI_VCM_MSK 0x00600000
+#define RG_RX_ADCRSSI_VCM_I_MSK 0xff9fffff
+#define RG_RX_ADCRSSI_VCM_SFT 21
+#define RG_RX_ADCRSSI_VCM_HI 22
+#define RG_RX_ADCRSSI_VCM_SZ 2
+#define RG_RX_REC_LPFCORNER_MSK 0x01800000
+#define RG_RX_REC_LPFCORNER_I_MSK 0xfe7fffff
+#define RG_RX_REC_LPFCORNER_SFT 23
+#define RG_RX_REC_LPFCORNER_HI 24
+#define RG_RX_REC_LPFCORNER_SZ 2
+#define RG_RSSI_CLOCK_GATING_MSK 0x02000000
+#define RG_RSSI_CLOCK_GATING_I_MSK 0xfdffffff
+#define RG_RSSI_CLOCK_GATING_SFT 25
+#define RG_RSSI_CLOCK_GATING_HI 25
+#define RG_RSSI_CLOCK_GATING_SZ 1
+#define RG_TXPGA_CAPSW_MSK 0x00000003
+#define RG_TXPGA_CAPSW_I_MSK 0xfffffffc
+#define RG_TXPGA_CAPSW_SFT 0
+#define RG_TXPGA_CAPSW_HI 1
+#define RG_TXPGA_CAPSW_SZ 2
+#define RG_TXPGA_MAIN_MSK 0x000000fc
+#define RG_TXPGA_MAIN_I_MSK 0xffffff03
+#define RG_TXPGA_MAIN_SFT 2
+#define RG_TXPGA_MAIN_HI 7
+#define RG_TXPGA_MAIN_SZ 6
+#define RG_TXPGA_STEER_MSK 0x00003f00
+#define RG_TXPGA_STEER_I_MSK 0xffffc0ff
+#define RG_TXPGA_STEER_SFT 8
+#define RG_TXPGA_STEER_HI 13
+#define RG_TXPGA_STEER_SZ 6
+#define RG_TXMOD_GMCELL_MSK 0x0000c000
+#define RG_TXMOD_GMCELL_I_MSK 0xffff3fff
+#define RG_TXMOD_GMCELL_SFT 14
+#define RG_TXMOD_GMCELL_HI 15
+#define RG_TXMOD_GMCELL_SZ 2
+#define RG_TXLPF_GMCELL_MSK 0x00030000
+#define RG_TXLPF_GMCELL_I_MSK 0xfffcffff
+#define RG_TXLPF_GMCELL_SFT 16
+#define RG_TXLPF_GMCELL_HI 17
+#define RG_TXLPF_GMCELL_SZ 2
+#define RG_PACELL_EN_MSK 0x001c0000
+#define RG_PACELL_EN_I_MSK 0xffe3ffff
+#define RG_PACELL_EN_SFT 18
+#define RG_PACELL_EN_HI 20
+#define RG_PACELL_EN_SZ 3
+#define RG_PABIAS_CTRL_MSK 0x01e00000
+#define RG_PABIAS_CTRL_I_MSK 0xfe1fffff
+#define RG_PABIAS_CTRL_SFT 21
+#define RG_PABIAS_CTRL_HI 24
+#define RG_PABIAS_CTRL_SZ 4
+#define RG_TX_DIV_VSET_MSK 0x0c000000
+#define RG_TX_DIV_VSET_I_MSK 0xf3ffffff
+#define RG_TX_DIV_VSET_SFT 26
+#define RG_TX_DIV_VSET_HI 27
+#define RG_TX_DIV_VSET_SZ 2
+#define RG_TX_LOBUF_VSET_MSK 0x30000000
+#define RG_TX_LOBUF_VSET_I_MSK 0xcfffffff
+#define RG_TX_LOBUF_VSET_SFT 28
+#define RG_TX_LOBUF_VSET_HI 29
+#define RG_TX_LOBUF_VSET_SZ 2
+#define RG_RX_SQDC_MSK 0x00000007
+#define RG_RX_SQDC_I_MSK 0xfffffff8
+#define RG_RX_SQDC_SFT 0
+#define RG_RX_SQDC_HI 2
+#define RG_RX_SQDC_SZ 3
+#define RG_RX_DIV2_CORE_MSK 0x00000018
+#define RG_RX_DIV2_CORE_I_MSK 0xffffffe7
+#define RG_RX_DIV2_CORE_SFT 3
+#define RG_RX_DIV2_CORE_HI 4
+#define RG_RX_DIV2_CORE_SZ 2
+#define RG_RX_LOBUF_MSK 0x00000060
+#define RG_RX_LOBUF_I_MSK 0xffffff9f
+#define RG_RX_LOBUF_SFT 5
+#define RG_RX_LOBUF_HI 6
+#define RG_RX_LOBUF_SZ 2
+#define RG_TX_DPDGM_BIAS_MSK 0x00000780
+#define RG_TX_DPDGM_BIAS_I_MSK 0xfffff87f
+#define RG_TX_DPDGM_BIAS_SFT 7
+#define RG_TX_DPDGM_BIAS_HI 10
+#define RG_TX_DPDGM_BIAS_SZ 4
+#define RG_TX_DPD_DIV_MSK 0x00007800
+#define RG_TX_DPD_DIV_I_MSK 0xffff87ff
+#define RG_TX_DPD_DIV_SFT 11
+#define RG_TX_DPD_DIV_HI 14
+#define RG_TX_DPD_DIV_SZ 4
+#define RG_TX_TSSI_BIAS_MSK 0x00038000
+#define RG_TX_TSSI_BIAS_I_MSK 0xfffc7fff
+#define RG_TX_TSSI_BIAS_SFT 15
+#define RG_TX_TSSI_BIAS_HI 17
+#define RG_TX_TSSI_BIAS_SZ 3
+#define RG_TX_TSSI_DIV_MSK 0x001c0000
+#define RG_TX_TSSI_DIV_I_MSK 0xffe3ffff
+#define RG_TX_TSSI_DIV_SFT 18
+#define RG_TX_TSSI_DIV_HI 20
+#define RG_TX_TSSI_DIV_SZ 3
+#define RG_TX_TSSI_TESTMODE_MSK 0x00200000
+#define RG_TX_TSSI_TESTMODE_I_MSK 0xffdfffff
+#define RG_TX_TSSI_TESTMODE_SFT 21
+#define RG_TX_TSSI_TESTMODE_HI 21
+#define RG_TX_TSSI_TESTMODE_SZ 1
+#define RG_TX_TSSI_TEST_MSK 0x00c00000
+#define RG_TX_TSSI_TEST_I_MSK 0xff3fffff
+#define RG_TX_TSSI_TEST_SFT 22
+#define RG_TX_TSSI_TEST_HI 23
+#define RG_TX_TSSI_TEST_SZ 2
+#define RG_PACASCODE_CTRL_MSK 0x07000000
+#define RG_PACASCODE_CTRL_I_MSK 0xf8ffffff
+#define RG_PACASCODE_CTRL_SFT 24
+#define RG_PACASCODE_CTRL_HI 26
+#define RG_PACASCODE_CTRL_SZ 3
+#define RG_RX_HG_LNA_GC_MSK 0x00000003
+#define RG_RX_HG_LNA_GC_I_MSK 0xfffffffc
+#define RG_RX_HG_LNA_GC_SFT 0
+#define RG_RX_HG_LNA_GC_HI 1
+#define RG_RX_HG_LNA_GC_SZ 2
+#define RG_RX_HG_LNAHGN_BIAS_MSK 0x0000003c
+#define RG_RX_HG_LNAHGN_BIAS_I_MSK 0xffffffc3
+#define RG_RX_HG_LNAHGN_BIAS_SFT 2
+#define RG_RX_HG_LNAHGN_BIAS_HI 5
+#define RG_RX_HG_LNAHGN_BIAS_SZ 4
+#define RG_RX_HG_LNAHGP_BIAS_MSK 0x000003c0
+#define RG_RX_HG_LNAHGP_BIAS_I_MSK 0xfffffc3f
+#define RG_RX_HG_LNAHGP_BIAS_SFT 6
+#define RG_RX_HG_LNAHGP_BIAS_HI 9
+#define RG_RX_HG_LNAHGP_BIAS_SZ 4
+#define RG_RX_HG_LNALG_BIAS_MSK 0x00003c00
+#define RG_RX_HG_LNALG_BIAS_I_MSK 0xffffc3ff
+#define RG_RX_HG_LNALG_BIAS_SFT 10
+#define RG_RX_HG_LNALG_BIAS_HI 13
+#define RG_RX_HG_LNALG_BIAS_SZ 4
+#define RG_RX_HG_TZ_GC_MSK 0x0000c000
+#define RG_RX_HG_TZ_GC_I_MSK 0xffff3fff
+#define RG_RX_HG_TZ_GC_SFT 14
+#define RG_RX_HG_TZ_GC_HI 15
+#define RG_RX_HG_TZ_GC_SZ 2
+#define RG_RX_HG_TZ_CAP_MSK 0x00070000
+#define RG_RX_HG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_RX_HG_TZ_CAP_SFT 16
+#define RG_RX_HG_TZ_CAP_HI 18
+#define RG_RX_HG_TZ_CAP_SZ 3
+#define RG_RX_MG_LNA_GC_MSK 0x00000003
+#define RG_RX_MG_LNA_GC_I_MSK 0xfffffffc
+#define RG_RX_MG_LNA_GC_SFT 0
+#define RG_RX_MG_LNA_GC_HI 1
+#define RG_RX_MG_LNA_GC_SZ 2
+#define RG_RX_MG_LNAHGN_BIAS_MSK 0x0000003c
+#define RG_RX_MG_LNAHGN_BIAS_I_MSK 0xffffffc3
+#define RG_RX_MG_LNAHGN_BIAS_SFT 2
+#define RG_RX_MG_LNAHGN_BIAS_HI 5
+#define RG_RX_MG_LNAHGN_BIAS_SZ 4
+#define RG_RX_MG_LNAHGP_BIAS_MSK 0x000003c0
+#define RG_RX_MG_LNAHGP_BIAS_I_MSK 0xfffffc3f
+#define RG_RX_MG_LNAHGP_BIAS_SFT 6
+#define RG_RX_MG_LNAHGP_BIAS_HI 9
+#define RG_RX_MG_LNAHGP_BIAS_SZ 4
+#define RG_RX_MG_LNALG_BIAS_MSK 0x00003c00
+#define RG_RX_MG_LNALG_BIAS_I_MSK 0xffffc3ff
+#define RG_RX_MG_LNALG_BIAS_SFT 10
+#define RG_RX_MG_LNALG_BIAS_HI 13
+#define RG_RX_MG_LNALG_BIAS_SZ 4
+#define RG_RX_MG_TZ_GC_MSK 0x0000c000
+#define RG_RX_MG_TZ_GC_I_MSK 0xffff3fff
+#define RG_RX_MG_TZ_GC_SFT 14
+#define RG_RX_MG_TZ_GC_HI 15
+#define RG_RX_MG_TZ_GC_SZ 2
+#define RG_RX_MG_TZ_CAP_MSK 0x00070000
+#define RG_RX_MG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_RX_MG_TZ_CAP_SFT 16
+#define RG_RX_MG_TZ_CAP_HI 18
+#define RG_RX_MG_TZ_CAP_SZ 3
+#define RG_RX_LG_LNA_GC_MSK 0x00000003
+#define RG_RX_LG_LNA_GC_I_MSK 0xfffffffc
+#define RG_RX_LG_LNA_GC_SFT 0
+#define RG_RX_LG_LNA_GC_HI 1
+#define RG_RX_LG_LNA_GC_SZ 2
+#define RG_RX_LG_LNAHGN_BIAS_MSK 0x0000003c
+#define RG_RX_LG_LNAHGN_BIAS_I_MSK 0xffffffc3
+#define RG_RX_LG_LNAHGN_BIAS_SFT 2
+#define RG_RX_LG_LNAHGN_BIAS_HI 5
+#define RG_RX_LG_LNAHGN_BIAS_SZ 4
+#define RG_RX_LG_LNAHGP_BIAS_MSK 0x000003c0
+#define RG_RX_LG_LNAHGP_BIAS_I_MSK 0xfffffc3f
+#define RG_RX_LG_LNAHGP_BIAS_SFT 6
+#define RG_RX_LG_LNAHGP_BIAS_HI 9
+#define RG_RX_LG_LNAHGP_BIAS_SZ 4
+#define RG_RX_LG_LNALG_BIAS_MSK 0x00003c00
+#define RG_RX_LG_LNALG_BIAS_I_MSK 0xffffc3ff
+#define RG_RX_LG_LNALG_BIAS_SFT 10
+#define RG_RX_LG_LNALG_BIAS_HI 13
+#define RG_RX_LG_LNALG_BIAS_SZ 4
+#define RG_RX_LG_TZ_GC_MSK 0x0000c000
+#define RG_RX_LG_TZ_GC_I_MSK 0xffff3fff
+#define RG_RX_LG_TZ_GC_SFT 14
+#define RG_RX_LG_TZ_GC_HI 15
+#define RG_RX_LG_TZ_GC_SZ 2
+#define RG_RX_LG_TZ_CAP_MSK 0x00070000
+#define RG_RX_LG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_RX_LG_TZ_CAP_SFT 16
+#define RG_RX_LG_TZ_CAP_HI 18
+#define RG_RX_LG_TZ_CAP_SZ 3
+#define RG_RX_ULG_LNA_GC_MSK 0x00000003
+#define RG_RX_ULG_LNA_GC_I_MSK 0xfffffffc
+#define RG_RX_ULG_LNA_GC_SFT 0
+#define RG_RX_ULG_LNA_GC_HI 1
+#define RG_RX_ULG_LNA_GC_SZ 2
+#define RG_RX_ULG_LNAHGN_BIAS_MSK 0x0000003c
+#define RG_RX_ULG_LNAHGN_BIAS_I_MSK 0xffffffc3
+#define RG_RX_ULG_LNAHGN_BIAS_SFT 2
+#define RG_RX_ULG_LNAHGN_BIAS_HI 5
+#define RG_RX_ULG_LNAHGN_BIAS_SZ 4
+#define RG_RX_ULG_LNAHGP_BIAS_MSK 0x000003c0
+#define RG_RX_ULG_LNAHGP_BIAS_I_MSK 0xfffffc3f
+#define RG_RX_ULG_LNAHGP_BIAS_SFT 6
+#define RG_RX_ULG_LNAHGP_BIAS_HI 9
+#define RG_RX_ULG_LNAHGP_BIAS_SZ 4
+#define RG_RX_ULG_LNALG_BIAS_MSK 0x00003c00
+#define RG_RX_ULG_LNALG_BIAS_I_MSK 0xffffc3ff
+#define RG_RX_ULG_LNALG_BIAS_SFT 10
+#define RG_RX_ULG_LNALG_BIAS_HI 13
+#define RG_RX_ULG_LNALG_BIAS_SZ 4
+#define RG_RX_ULG_TZ_GC_MSK 0x0000c000
+#define RG_RX_ULG_TZ_GC_I_MSK 0xffff3fff
+#define RG_RX_ULG_TZ_GC_SFT 14
+#define RG_RX_ULG_TZ_GC_HI 15
+#define RG_RX_ULG_TZ_GC_SZ 2
+#define RG_RX_ULG_TZ_CAP_MSK 0x00070000
+#define RG_RX_ULG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_RX_ULG_TZ_CAP_SFT 16
+#define RG_RX_ULG_TZ_CAP_HI 18
+#define RG_RX_ULG_TZ_CAP_SZ 3
+#define RG_HPF1_FAST_SET_X_MSK 0x00000001
+#define RG_HPF1_FAST_SET_X_I_MSK 0xfffffffe
+#define RG_HPF1_FAST_SET_X_SFT 0
+#define RG_HPF1_FAST_SET_X_HI 0
+#define RG_HPF1_FAST_SET_X_SZ 1
+#define RG_HPF1_FAST_SET_Y_MSK 0x00000002
+#define RG_HPF1_FAST_SET_Y_I_MSK 0xfffffffd
+#define RG_HPF1_FAST_SET_Y_SFT 1
+#define RG_HPF1_FAST_SET_Y_HI 1
+#define RG_HPF1_FAST_SET_Y_SZ 1
+#define RG_HPF1_FAST_SET_Z_MSK 0x00000004
+#define RG_HPF1_FAST_SET_Z_I_MSK 0xfffffffb
+#define RG_HPF1_FAST_SET_Z_SFT 2
+#define RG_HPF1_FAST_SET_Z_HI 2
+#define RG_HPF1_FAST_SET_Z_SZ 1
+#define RG_HPF_T1A_MSK 0x00000018
+#define RG_HPF_T1A_I_MSK 0xffffffe7
+#define RG_HPF_T1A_SFT 3
+#define RG_HPF_T1A_HI 4
+#define RG_HPF_T1A_SZ 2
+#define RG_HPF_T1B_MSK 0x00000060
+#define RG_HPF_T1B_I_MSK 0xffffff9f
+#define RG_HPF_T1B_SFT 5
+#define RG_HPF_T1B_HI 6
+#define RG_HPF_T1B_SZ 2
+#define RG_HPF_T1C_MSK 0x00000180
+#define RG_HPF_T1C_I_MSK 0xfffffe7f
+#define RG_HPF_T1C_SFT 7
+#define RG_HPF_T1C_HI 8
+#define RG_HPF_T1C_SZ 2
+#define RG_RX_LNA_TRI_SEL_MSK 0x00000600
+#define RG_RX_LNA_TRI_SEL_I_MSK 0xfffff9ff
+#define RG_RX_LNA_TRI_SEL_SFT 9
+#define RG_RX_LNA_TRI_SEL_HI 10
+#define RG_RX_LNA_TRI_SEL_SZ 2
+#define RG_RX_LNA_SETTLE_MSK 0x00001800
+#define RG_RX_LNA_SETTLE_I_MSK 0xffffe7ff
+#define RG_RX_LNA_SETTLE_SFT 11
+#define RG_RX_LNA_SETTLE_HI 12
+#define RG_RX_LNA_SETTLE_SZ 2
+#define RG_TXGAIN_PHYCTRL_MSK 0x00002000
+#define RG_TXGAIN_PHYCTRL_I_MSK 0xffffdfff
+#define RG_TXGAIN_PHYCTRL_SFT 13
+#define RG_TXGAIN_PHYCTRL_HI 13
+#define RG_TXGAIN_PHYCTRL_SZ 1
+#define RG_TX_GAIN_MSK 0x003fc000
+#define RG_TX_GAIN_I_MSK 0xffc03fff
+#define RG_TX_GAIN_SFT 14
+#define RG_TX_GAIN_HI 21
+#define RG_TX_GAIN_SZ 8
+#define RG_TXGAIN_MANUAL_MSK 0x00400000
+#define RG_TXGAIN_MANUAL_I_MSK 0xffbfffff
+#define RG_TXGAIN_MANUAL_SFT 22
+#define RG_TXGAIN_MANUAL_HI 22
+#define RG_TXGAIN_MANUAL_SZ 1
+#define RG_TX_GAIN_OFFSET_MSK 0x07800000
+#define RG_TX_GAIN_OFFSET_I_MSK 0xf87fffff
+#define RG_TX_GAIN_OFFSET_SFT 23
+#define RG_TX_GAIN_OFFSET_HI 26
+#define RG_TX_GAIN_OFFSET_SZ 4
+#define RG_ADC_CLKSEL_MSK 0x00000001
+#define RG_ADC_CLKSEL_I_MSK 0xfffffffe
+#define RG_ADC_CLKSEL_SFT 0
+#define RG_ADC_CLKSEL_HI 0
+#define RG_ADC_CLKSEL_SZ 1
+#define RG_ADC_DIBIAS_MSK 0x00000006
+#define RG_ADC_DIBIAS_I_MSK 0xfffffff9
+#define RG_ADC_DIBIAS_SFT 1
+#define RG_ADC_DIBIAS_HI 2
+#define RG_ADC_DIBIAS_SZ 2
+#define RG_ADC_DIVR_MSK 0x00000008
+#define RG_ADC_DIVR_I_MSK 0xfffffff7
+#define RG_ADC_DIVR_SFT 3
+#define RG_ADC_DIVR_HI 3
+#define RG_ADC_DIVR_SZ 1
+#define RG_ADC_DVCMI_MSK 0x00000030
+#define RG_ADC_DVCMI_I_MSK 0xffffffcf
+#define RG_ADC_DVCMI_SFT 4
+#define RG_ADC_DVCMI_HI 5
+#define RG_ADC_DVCMI_SZ 2
+#define RG_ADC_SAMSEL_MSK 0x000003c0
+#define RG_ADC_SAMSEL_I_MSK 0xfffffc3f
+#define RG_ADC_SAMSEL_SFT 6
+#define RG_ADC_SAMSEL_HI 9
+#define RG_ADC_SAMSEL_SZ 4
+#define RG_ADC_STNBY_MSK 0x00000400
+#define RG_ADC_STNBY_I_MSK 0xfffffbff
+#define RG_ADC_STNBY_SFT 10
+#define RG_ADC_STNBY_HI 10
+#define RG_ADC_STNBY_SZ 1
+#define RG_ADC_TESTMODE_MSK 0x00000800
+#define RG_ADC_TESTMODE_I_MSK 0xfffff7ff
+#define RG_ADC_TESTMODE_SFT 11
+#define RG_ADC_TESTMODE_HI 11
+#define RG_ADC_TESTMODE_SZ 1
+#define RG_ADC_TSEL_MSK 0x0000f000
+#define RG_ADC_TSEL_I_MSK 0xffff0fff
+#define RG_ADC_TSEL_SFT 12
+#define RG_ADC_TSEL_HI 15
+#define RG_ADC_TSEL_SZ 4
+#define RG_ADC_VRSEL_MSK 0x00030000
+#define RG_ADC_VRSEL_I_MSK 0xfffcffff
+#define RG_ADC_VRSEL_SFT 16
+#define RG_ADC_VRSEL_HI 17
+#define RG_ADC_VRSEL_SZ 2
+#define RG_DICMP_MSK 0x000c0000
+#define RG_DICMP_I_MSK 0xfff3ffff
+#define RG_DICMP_SFT 18
+#define RG_DICMP_HI 19
+#define RG_DICMP_SZ 2
+#define RG_DIOP_MSK 0x00300000
+#define RG_DIOP_I_MSK 0xffcfffff
+#define RG_DIOP_SFT 20
+#define RG_DIOP_HI 21
+#define RG_DIOP_SZ 2
+#define RG_SARADC_VRSEL_MSK 0x00c00000
+#define RG_SARADC_VRSEL_I_MSK 0xff3fffff
+#define RG_SARADC_VRSEL_SFT 22
+#define RG_SARADC_VRSEL_HI 23
+#define RG_SARADC_VRSEL_SZ 2
+#define RG_EN_SAR_TEST_MSK 0x03000000
+#define RG_EN_SAR_TEST_I_MSK 0xfcffffff
+#define RG_EN_SAR_TEST_SFT 24
+#define RG_EN_SAR_TEST_HI 25
+#define RG_EN_SAR_TEST_SZ 2
+#define RG_SARADC_THERMAL_MSK 0x04000000
+#define RG_SARADC_THERMAL_I_MSK 0xfbffffff
+#define RG_SARADC_THERMAL_SFT 26
+#define RG_SARADC_THERMAL_HI 26
+#define RG_SARADC_THERMAL_SZ 1
+#define RG_SARADC_TSSI_MSK 0x08000000
+#define RG_SARADC_TSSI_I_MSK 0xf7ffffff
+#define RG_SARADC_TSSI_SFT 27
+#define RG_SARADC_TSSI_HI 27
+#define RG_SARADC_TSSI_SZ 1
+#define RG_CLK_SAR_SEL_MSK 0x30000000
+#define RG_CLK_SAR_SEL_I_MSK 0xcfffffff
+#define RG_CLK_SAR_SEL_SFT 28
+#define RG_CLK_SAR_SEL_HI 29
+#define RG_CLK_SAR_SEL_SZ 2
+#define RG_EN_SARADC_MSK 0x40000000
+#define RG_EN_SARADC_I_MSK 0xbfffffff
+#define RG_EN_SARADC_SFT 30
+#define RG_EN_SARADC_HI 30
+#define RG_EN_SARADC_SZ 1
+#define RG_DACI1ST_MSK 0x00000003
+#define RG_DACI1ST_I_MSK 0xfffffffc
+#define RG_DACI1ST_SFT 0
+#define RG_DACI1ST_HI 1
+#define RG_DACI1ST_SZ 2
+#define RG_TX_DACLPF_ICOURSE_MSK 0x0000000c
+#define RG_TX_DACLPF_ICOURSE_I_MSK 0xfffffff3
+#define RG_TX_DACLPF_ICOURSE_SFT 2
+#define RG_TX_DACLPF_ICOURSE_HI 3
+#define RG_TX_DACLPF_ICOURSE_SZ 2
+#define RG_TX_DACLPF_IFINE_MSK 0x00000030
+#define RG_TX_DACLPF_IFINE_I_MSK 0xffffffcf
+#define RG_TX_DACLPF_IFINE_SFT 4
+#define RG_TX_DACLPF_IFINE_HI 5
+#define RG_TX_DACLPF_IFINE_SZ 2
+#define RG_TX_DACLPF_VCM_MSK 0x000000c0
+#define RG_TX_DACLPF_VCM_I_MSK 0xffffff3f
+#define RG_TX_DACLPF_VCM_SFT 6
+#define RG_TX_DACLPF_VCM_HI 7
+#define RG_TX_DACLPF_VCM_SZ 2
+#define RG_TX_DAC_CKEDGE_SEL_MSK 0x00000100
+#define RG_TX_DAC_CKEDGE_SEL_I_MSK 0xfffffeff
+#define RG_TX_DAC_CKEDGE_SEL_SFT 8
+#define RG_TX_DAC_CKEDGE_SEL_HI 8
+#define RG_TX_DAC_CKEDGE_SEL_SZ 1
+#define RG_TX_DAC_IBIAS_MSK 0x00000600
+#define RG_TX_DAC_IBIAS_I_MSK 0xfffff9ff
+#define RG_TX_DAC_IBIAS_SFT 9
+#define RG_TX_DAC_IBIAS_HI 10
+#define RG_TX_DAC_IBIAS_SZ 2
+#define RG_TX_DAC_OS_MSK 0x00003800
+#define RG_TX_DAC_OS_I_MSK 0xffffc7ff
+#define RG_TX_DAC_OS_SFT 11
+#define RG_TX_DAC_OS_HI 13
+#define RG_TX_DAC_OS_SZ 3
+#define RG_TX_DAC_RCAL_MSK 0x0000c000
+#define RG_TX_DAC_RCAL_I_MSK 0xffff3fff
+#define RG_TX_DAC_RCAL_SFT 14
+#define RG_TX_DAC_RCAL_HI 15
+#define RG_TX_DAC_RCAL_SZ 2
+#define RG_TX_DAC_TSEL_MSK 0x000f0000
+#define RG_TX_DAC_TSEL_I_MSK 0xfff0ffff
+#define RG_TX_DAC_TSEL_SFT 16
+#define RG_TX_DAC_TSEL_HI 19
+#define RG_TX_DAC_TSEL_SZ 4
+#define RG_TX_EN_VOLTAGE_IN_MSK 0x00100000
+#define RG_TX_EN_VOLTAGE_IN_I_MSK 0xffefffff
+#define RG_TX_EN_VOLTAGE_IN_SFT 20
+#define RG_TX_EN_VOLTAGE_IN_HI 20
+#define RG_TX_EN_VOLTAGE_IN_SZ 1
+#define RG_TXLPF_BYPASS_MSK 0x00200000
+#define RG_TXLPF_BYPASS_I_MSK 0xffdfffff
+#define RG_TXLPF_BYPASS_SFT 21
+#define RG_TXLPF_BYPASS_HI 21
+#define RG_TXLPF_BYPASS_SZ 1
+#define RG_TXLPF_BOOSTI_MSK 0x00400000
+#define RG_TXLPF_BOOSTI_I_MSK 0xffbfffff
+#define RG_TXLPF_BOOSTI_SFT 22
+#define RG_TXLPF_BOOSTI_HI 22
+#define RG_TXLPF_BOOSTI_SZ 1
+#define RG_TX_DAC_IOFFSET_MSK 0x07800000
+#define RG_TX_DAC_IOFFSET_I_MSK 0xf87fffff
+#define RG_TX_DAC_IOFFSET_SFT 23
+#define RG_TX_DAC_IOFFSET_HI 26
+#define RG_TX_DAC_IOFFSET_SZ 4
+#define RG_TX_DAC_QOFFSET_MSK 0x78000000
+#define RG_TX_DAC_QOFFSET_I_MSK 0x87ffffff
+#define RG_TX_DAC_QOFFSET_SFT 27
+#define RG_TX_DAC_QOFFSET_HI 30
+#define RG_TX_DAC_QOFFSET_SZ 4
+#define RG_EN_SX_R3_MSK 0x00000001
+#define RG_EN_SX_R3_I_MSK 0xfffffffe
+#define RG_EN_SX_R3_SFT 0
+#define RG_EN_SX_R3_HI 0
+#define RG_EN_SX_R3_SZ 1
+#define RG_EN_SX_CH_MSK 0x00000002
+#define RG_EN_SX_CH_I_MSK 0xfffffffd
+#define RG_EN_SX_CH_SFT 1
+#define RG_EN_SX_CH_HI 1
+#define RG_EN_SX_CH_SZ 1
+#define RG_EN_SX_CHP_MSK 0x00000004
+#define RG_EN_SX_CHP_I_MSK 0xfffffffb
+#define RG_EN_SX_CHP_SFT 2
+#define RG_EN_SX_CHP_HI 2
+#define RG_EN_SX_CHP_SZ 1
+#define RG_EN_SX_DIVCK_MSK 0x00000008
+#define RG_EN_SX_DIVCK_I_MSK 0xfffffff7
+#define RG_EN_SX_DIVCK_SFT 3
+#define RG_EN_SX_DIVCK_HI 3
+#define RG_EN_SX_DIVCK_SZ 1
+#define RG_EN_SX_VCOBF_MSK 0x00000010
+#define RG_EN_SX_VCOBF_I_MSK 0xffffffef
+#define RG_EN_SX_VCOBF_SFT 4
+#define RG_EN_SX_VCOBF_HI 4
+#define RG_EN_SX_VCOBF_SZ 1
+#define RG_EN_SX_VCO_MSK 0x00000020
+#define RG_EN_SX_VCO_I_MSK 0xffffffdf
+#define RG_EN_SX_VCO_SFT 5
+#define RG_EN_SX_VCO_HI 5
+#define RG_EN_SX_VCO_SZ 1
+#define RG_EN_SX_MOD_MSK 0x00000040
+#define RG_EN_SX_MOD_I_MSK 0xffffffbf
+#define RG_EN_SX_MOD_SFT 6
+#define RG_EN_SX_MOD_HI 6
+#define RG_EN_SX_MOD_SZ 1
+#define RG_EN_SX_DITHER_MSK 0x00000100
+#define RG_EN_SX_DITHER_I_MSK 0xfffffeff
+#define RG_EN_SX_DITHER_SFT 8
+#define RG_EN_SX_DITHER_HI 8
+#define RG_EN_SX_DITHER_SZ 1
+#define RG_EN_SX_VT_MON_MSK 0x00000800
+#define RG_EN_SX_VT_MON_I_MSK 0xfffff7ff
+#define RG_EN_SX_VT_MON_SFT 11
+#define RG_EN_SX_VT_MON_HI 11
+#define RG_EN_SX_VT_MON_SZ 1
+#define RG_EN_SX_VT_MON_DG_MSK 0x00001000
+#define RG_EN_SX_VT_MON_DG_I_MSK 0xffffefff
+#define RG_EN_SX_VT_MON_DG_SFT 12
+#define RG_EN_SX_VT_MON_DG_HI 12
+#define RG_EN_SX_VT_MON_DG_SZ 1
+#define RG_EN_SX_DIV_MSK 0x00002000
+#define RG_EN_SX_DIV_I_MSK 0xffffdfff
+#define RG_EN_SX_DIV_SFT 13
+#define RG_EN_SX_DIV_HI 13
+#define RG_EN_SX_DIV_SZ 1
+#define RG_EN_SX_LPF_MSK 0x00004000
+#define RG_EN_SX_LPF_I_MSK 0xffffbfff
+#define RG_EN_SX_LPF_SFT 14
+#define RG_EN_SX_LPF_HI 14
+#define RG_EN_SX_LPF_SZ 1
+#define RG_EN_DPL_MOD_MSK 0x00008000
+#define RG_EN_DPL_MOD_I_MSK 0xffff7fff
+#define RG_EN_DPL_MOD_SFT 15
+#define RG_EN_DPL_MOD_HI 15
+#define RG_EN_DPL_MOD_SZ 1
+#define RG_DPL_MOD_ORDER_MSK 0x00030000
+#define RG_DPL_MOD_ORDER_I_MSK 0xfffcffff
+#define RG_DPL_MOD_ORDER_SFT 16
+#define RG_DPL_MOD_ORDER_HI 17
+#define RG_DPL_MOD_ORDER_SZ 2
+#define RG_SX_RFCTRL_F_MSK 0x00ffffff
+#define RG_SX_RFCTRL_F_I_MSK 0xff000000
+#define RG_SX_RFCTRL_F_SFT 0
+#define RG_SX_RFCTRL_F_HI 23
+#define RG_SX_RFCTRL_F_SZ 24
+#define RG_SX_SEL_CP_MSK 0x0f000000
+#define RG_SX_SEL_CP_I_MSK 0xf0ffffff
+#define RG_SX_SEL_CP_SFT 24
+#define RG_SX_SEL_CP_HI 27
+#define RG_SX_SEL_CP_SZ 4
+#define RG_SX_SEL_CS_MSK 0xf0000000
+#define RG_SX_SEL_CS_I_MSK 0x0fffffff
+#define RG_SX_SEL_CS_SFT 28
+#define RG_SX_SEL_CS_HI 31
+#define RG_SX_SEL_CS_SZ 4
+#define RG_SX_RFCTRL_CH_MSK 0x000007ff
+#define RG_SX_RFCTRL_CH_I_MSK 0xfffff800
+#define RG_SX_RFCTRL_CH_SFT 0
+#define RG_SX_RFCTRL_CH_HI 10
+#define RG_SX_RFCTRL_CH_SZ 11
+#define RG_SX_SEL_C3_MSK 0x00007800
+#define RG_SX_SEL_C3_I_MSK 0xffff87ff
+#define RG_SX_SEL_C3_SFT 11
+#define RG_SX_SEL_C3_HI 14
+#define RG_SX_SEL_C3_SZ 4
+#define RG_SX_SEL_RS_MSK 0x000f8000
+#define RG_SX_SEL_RS_I_MSK 0xfff07fff
+#define RG_SX_SEL_RS_SFT 15
+#define RG_SX_SEL_RS_HI 19
+#define RG_SX_SEL_RS_SZ 5
+#define RG_SX_SEL_R3_MSK 0x01f00000
+#define RG_SX_SEL_R3_I_MSK 0xfe0fffff
+#define RG_SX_SEL_R3_SFT 20
+#define RG_SX_SEL_R3_HI 24
+#define RG_SX_SEL_R3_SZ 5
+#define RG_SX_SEL_ICHP_MSK 0x0000001f
+#define RG_SX_SEL_ICHP_I_MSK 0xffffffe0
+#define RG_SX_SEL_ICHP_SFT 0
+#define RG_SX_SEL_ICHP_HI 4
+#define RG_SX_SEL_ICHP_SZ 5
+#define RG_SX_SEL_PCHP_MSK 0x000003e0
+#define RG_SX_SEL_PCHP_I_MSK 0xfffffc1f
+#define RG_SX_SEL_PCHP_SFT 5
+#define RG_SX_SEL_PCHP_HI 9
+#define RG_SX_SEL_PCHP_SZ 5
+#define RG_SX_SEL_CHP_REGOP_MSK 0x00003c00
+#define RG_SX_SEL_CHP_REGOP_I_MSK 0xffffc3ff
+#define RG_SX_SEL_CHP_REGOP_SFT 10
+#define RG_SX_SEL_CHP_REGOP_HI 13
+#define RG_SX_SEL_CHP_REGOP_SZ 4
+#define RG_SX_SEL_CHP_UNIOP_MSK 0x0003c000
+#define RG_SX_SEL_CHP_UNIOP_I_MSK 0xfffc3fff
+#define RG_SX_SEL_CHP_UNIOP_SFT 14
+#define RG_SX_SEL_CHP_UNIOP_HI 17
+#define RG_SX_SEL_CHP_UNIOP_SZ 4
+#define RG_SX_CHP_IOST_POL_MSK 0x00040000
+#define RG_SX_CHP_IOST_POL_I_MSK 0xfffbffff
+#define RG_SX_CHP_IOST_POL_SFT 18
+#define RG_SX_CHP_IOST_POL_HI 18
+#define RG_SX_CHP_IOST_POL_SZ 1
+#define RG_SX_CHP_IOST_MSK 0x00380000
+#define RG_SX_CHP_IOST_I_MSK 0xffc7ffff
+#define RG_SX_CHP_IOST_SFT 19
+#define RG_SX_CHP_IOST_HI 21
+#define RG_SX_CHP_IOST_SZ 3
+#define RG_SX_PFDSEL_MSK 0x00400000
+#define RG_SX_PFDSEL_I_MSK 0xffbfffff
+#define RG_SX_PFDSEL_SFT 22
+#define RG_SX_PFDSEL_HI 22
+#define RG_SX_PFDSEL_SZ 1
+#define RG_SX_PFD_SET_MSK 0x00800000
+#define RG_SX_PFD_SET_I_MSK 0xff7fffff
+#define RG_SX_PFD_SET_SFT 23
+#define RG_SX_PFD_SET_HI 23
+#define RG_SX_PFD_SET_SZ 1
+#define RG_SX_PFD_SET1_MSK 0x01000000
+#define RG_SX_PFD_SET1_I_MSK 0xfeffffff
+#define RG_SX_PFD_SET1_SFT 24
+#define RG_SX_PFD_SET1_HI 24
+#define RG_SX_PFD_SET1_SZ 1
+#define RG_SX_PFD_SET2_MSK 0x02000000
+#define RG_SX_PFD_SET2_I_MSK 0xfdffffff
+#define RG_SX_PFD_SET2_SFT 25
+#define RG_SX_PFD_SET2_HI 25
+#define RG_SX_PFD_SET2_SZ 1
+#define RG_SX_VBNCAS_SEL_MSK 0x04000000
+#define RG_SX_VBNCAS_SEL_I_MSK 0xfbffffff
+#define RG_SX_VBNCAS_SEL_SFT 26
+#define RG_SX_VBNCAS_SEL_HI 26
+#define RG_SX_VBNCAS_SEL_SZ 1
+#define RG_SX_PFD_RST_H_MSK 0x08000000
+#define RG_SX_PFD_RST_H_I_MSK 0xf7ffffff
+#define RG_SX_PFD_RST_H_SFT 27
+#define RG_SX_PFD_RST_H_HI 27
+#define RG_SX_PFD_RST_H_SZ 1
+#define RG_SX_PFD_TRUP_MSK 0x10000000
+#define RG_SX_PFD_TRUP_I_MSK 0xefffffff
+#define RG_SX_PFD_TRUP_SFT 28
+#define RG_SX_PFD_TRUP_HI 28
+#define RG_SX_PFD_TRUP_SZ 1
+#define RG_SX_PFD_TRDN_MSK 0x20000000
+#define RG_SX_PFD_TRDN_I_MSK 0xdfffffff
+#define RG_SX_PFD_TRDN_SFT 29
+#define RG_SX_PFD_TRDN_HI 29
+#define RG_SX_PFD_TRDN_SZ 1
+#define RG_SX_PFD_TRSEL_MSK 0x40000000
+#define RG_SX_PFD_TRSEL_I_MSK 0xbfffffff
+#define RG_SX_PFD_TRSEL_SFT 30
+#define RG_SX_PFD_TRSEL_HI 30
+#define RG_SX_PFD_TRSEL_SZ 1
+#define RG_SX_VCOBA_R_MSK 0x00000007
+#define RG_SX_VCOBA_R_I_MSK 0xfffffff8
+#define RG_SX_VCOBA_R_SFT 0
+#define RG_SX_VCOBA_R_HI 2
+#define RG_SX_VCOBA_R_SZ 3
+#define RG_SX_VCORSEL_MSK 0x000000f8
+#define RG_SX_VCORSEL_I_MSK 0xffffff07
+#define RG_SX_VCORSEL_SFT 3
+#define RG_SX_VCORSEL_HI 7
+#define RG_SX_VCORSEL_SZ 5
+#define RG_SX_VCOCUSEL_MSK 0x00000f00
+#define RG_SX_VCOCUSEL_I_MSK 0xfffff0ff
+#define RG_SX_VCOCUSEL_SFT 8
+#define RG_SX_VCOCUSEL_HI 11
+#define RG_SX_VCOCUSEL_SZ 4
+#define RG_SX_RXBFSEL_MSK 0x0000f000
+#define RG_SX_RXBFSEL_I_MSK 0xffff0fff
+#define RG_SX_RXBFSEL_SFT 12
+#define RG_SX_RXBFSEL_HI 15
+#define RG_SX_RXBFSEL_SZ 4
+#define RG_SX_TXBFSEL_MSK 0x000f0000
+#define RG_SX_TXBFSEL_I_MSK 0xfff0ffff
+#define RG_SX_TXBFSEL_SFT 16
+#define RG_SX_TXBFSEL_HI 19
+#define RG_SX_TXBFSEL_SZ 4
+#define RG_SX_VCOBFSEL_MSK 0x00f00000
+#define RG_SX_VCOBFSEL_I_MSK 0xff0fffff
+#define RG_SX_VCOBFSEL_SFT 20
+#define RG_SX_VCOBFSEL_HI 23
+#define RG_SX_VCOBFSEL_SZ 4
+#define RG_SX_DIVBFSEL_MSK 0x0f000000
+#define RG_SX_DIVBFSEL_I_MSK 0xf0ffffff
+#define RG_SX_DIVBFSEL_SFT 24
+#define RG_SX_DIVBFSEL_HI 27
+#define RG_SX_DIVBFSEL_SZ 4
+#define RG_SX_GNDR_SEL_MSK 0xf0000000
+#define RG_SX_GNDR_SEL_I_MSK 0x0fffffff
+#define RG_SX_GNDR_SEL_SFT 28
+#define RG_SX_GNDR_SEL_HI 31
+#define RG_SX_GNDR_SEL_SZ 4
+#define RG_SX_DITHER_WEIGHT_MSK 0x00000003
+#define RG_SX_DITHER_WEIGHT_I_MSK 0xfffffffc
+#define RG_SX_DITHER_WEIGHT_SFT 0
+#define RG_SX_DITHER_WEIGHT_HI 1
+#define RG_SX_DITHER_WEIGHT_SZ 2
+#define RG_SX_MOD_ORDER_MSK 0x00000030
+#define RG_SX_MOD_ORDER_I_MSK 0xffffffcf
+#define RG_SX_MOD_ORDER_SFT 4
+#define RG_SX_MOD_ORDER_HI 5
+#define RG_SX_MOD_ORDER_SZ 2
+#define RG_SX_RST_H_DIV_MSK 0x00000200
+#define RG_SX_RST_H_DIV_I_MSK 0xfffffdff
+#define RG_SX_RST_H_DIV_SFT 9
+#define RG_SX_RST_H_DIV_HI 9
+#define RG_SX_RST_H_DIV_SZ 1
+#define RG_SX_SDM_EDGE_MSK 0x00000400
+#define RG_SX_SDM_EDGE_I_MSK 0xfffffbff
+#define RG_SX_SDM_EDGE_SFT 10
+#define RG_SX_SDM_EDGE_HI 10
+#define RG_SX_SDM_EDGE_SZ 1
+#define RG_SX_XO_GM_MSK 0x00001800
+#define RG_SX_XO_GM_I_MSK 0xffffe7ff
+#define RG_SX_XO_GM_SFT 11
+#define RG_SX_XO_GM_HI 12
+#define RG_SX_XO_GM_SZ 2
+#define RG_SX_REFBYTWO_MSK 0x00002000
+#define RG_SX_REFBYTWO_I_MSK 0xffffdfff
+#define RG_SX_REFBYTWO_SFT 13
+#define RG_SX_REFBYTWO_HI 13
+#define RG_SX_REFBYTWO_SZ 1
+#define RG_SX_LCKEN_MSK 0x00080000
+#define RG_SX_LCKEN_I_MSK 0xfff7ffff
+#define RG_SX_LCKEN_SFT 19
+#define RG_SX_LCKEN_HI 19
+#define RG_SX_LCKEN_SZ 1
+#define RG_SX_PREVDD_MSK 0x00f00000
+#define RG_SX_PREVDD_I_MSK 0xff0fffff
+#define RG_SX_PREVDD_SFT 20
+#define RG_SX_PREVDD_HI 23
+#define RG_SX_PREVDD_SZ 4
+#define RG_SX_PSCONTERVDD_MSK 0x0f000000
+#define RG_SX_PSCONTERVDD_I_MSK 0xf0ffffff
+#define RG_SX_PSCONTERVDD_SFT 24
+#define RG_SX_PSCONTERVDD_HI 27
+#define RG_SX_PSCONTERVDD_SZ 4
+#define RG_SX_PH_MSK 0x00002000
+#define RG_SX_PH_I_MSK 0xffffdfff
+#define RG_SX_PH_SFT 13
+#define RG_SX_PH_HI 13
+#define RG_SX_PH_SZ 1
+#define RG_SX_PL_MSK 0x00004000
+#define RG_SX_PL_I_MSK 0xffffbfff
+#define RG_SX_PL_SFT 14
+#define RG_SX_PL_HI 14
+#define RG_SX_PL_SZ 1
+#define RG_XOSC_CBANK_XO_MSK 0x00078000
+#define RG_XOSC_CBANK_XO_I_MSK 0xfff87fff
+#define RG_XOSC_CBANK_XO_SFT 15
+#define RG_XOSC_CBANK_XO_HI 18
+#define RG_XOSC_CBANK_XO_SZ 4
+#define RG_XOSC_CBANK_XI_MSK 0x00780000
+#define RG_XOSC_CBANK_XI_I_MSK 0xff87ffff
+#define RG_XOSC_CBANK_XI_SFT 19
+#define RG_XOSC_CBANK_XI_HI 22
+#define RG_XOSC_CBANK_XI_SZ 4
+#define RG_SX_VT_MON_MODE_MSK 0x00000001
+#define RG_SX_VT_MON_MODE_I_MSK 0xfffffffe
+#define RG_SX_VT_MON_MODE_SFT 0
+#define RG_SX_VT_MON_MODE_HI 0
+#define RG_SX_VT_MON_MODE_SZ 1
+#define RG_SX_VT_TH_HI_MSK 0x00000006
+#define RG_SX_VT_TH_HI_I_MSK 0xfffffff9
+#define RG_SX_VT_TH_HI_SFT 1
+#define RG_SX_VT_TH_HI_HI 2
+#define RG_SX_VT_TH_HI_SZ 2
+#define RG_SX_VT_TH_LO_MSK 0x00000018
+#define RG_SX_VT_TH_LO_I_MSK 0xffffffe7
+#define RG_SX_VT_TH_LO_SFT 3
+#define RG_SX_VT_TH_LO_HI 4
+#define RG_SX_VT_TH_LO_SZ 2
+#define RG_SX_VT_SET_MSK 0x00000020
+#define RG_SX_VT_SET_I_MSK 0xffffffdf
+#define RG_SX_VT_SET_SFT 5
+#define RG_SX_VT_SET_HI 5
+#define RG_SX_VT_SET_SZ 1
+#define RG_SX_VT_MON_TMR_MSK 0x00007fc0
+#define RG_SX_VT_MON_TMR_I_MSK 0xffff803f
+#define RG_SX_VT_MON_TMR_SFT 6
+#define RG_SX_VT_MON_TMR_HI 14
+#define RG_SX_VT_MON_TMR_SZ 9
+#define RG_EN_DP_VT_MON_MSK 0x00000001
+#define RG_EN_DP_VT_MON_I_MSK 0xfffffffe
+#define RG_EN_DP_VT_MON_SFT 0
+#define RG_EN_DP_VT_MON_HI 0
+#define RG_EN_DP_VT_MON_SZ 1
+#define RG_DP_VT_TH_HI_MSK 0x00000006
+#define RG_DP_VT_TH_HI_I_MSK 0xfffffff9
+#define RG_DP_VT_TH_HI_SFT 1
+#define RG_DP_VT_TH_HI_HI 2
+#define RG_DP_VT_TH_HI_SZ 2
+#define RG_DP_VT_TH_LO_MSK 0x00000018
+#define RG_DP_VT_TH_LO_I_MSK 0xffffffe7
+#define RG_DP_VT_TH_LO_SFT 3
+#define RG_DP_VT_TH_LO_HI 4
+#define RG_DP_VT_TH_LO_SZ 2
+#define RG_DP_CK320BY2_MSK 0x00004000
+#define RG_DP_CK320BY2_I_MSK 0xffffbfff
+#define RG_DP_CK320BY2_SFT 14
+#define RG_DP_CK320BY2_HI 14
+#define RG_DP_CK320BY2_SZ 1
+#define RG_DP_OD_TEST_MSK 0x00200000
+#define RG_DP_OD_TEST_I_MSK 0xffdfffff
+#define RG_DP_OD_TEST_SFT 21
+#define RG_DP_OD_TEST_HI 21
+#define RG_DP_OD_TEST_SZ 1
+#define RG_DP_BBPLL_BP_MSK 0x00000001
+#define RG_DP_BBPLL_BP_I_MSK 0xfffffffe
+#define RG_DP_BBPLL_BP_SFT 0
+#define RG_DP_BBPLL_BP_HI 0
+#define RG_DP_BBPLL_BP_SZ 1
+#define RG_DP_BBPLL_ICP_MSK 0x00000006
+#define RG_DP_BBPLL_ICP_I_MSK 0xfffffff9
+#define RG_DP_BBPLL_ICP_SFT 1
+#define RG_DP_BBPLL_ICP_HI 2
+#define RG_DP_BBPLL_ICP_SZ 2
+#define RG_DP_BBPLL_IDUAL_MSK 0x00000018
+#define RG_DP_BBPLL_IDUAL_I_MSK 0xffffffe7
+#define RG_DP_BBPLL_IDUAL_SFT 3
+#define RG_DP_BBPLL_IDUAL_HI 4
+#define RG_DP_BBPLL_IDUAL_SZ 2
+#define RG_DP_BBPLL_OD_TEST_MSK 0x000001e0
+#define RG_DP_BBPLL_OD_TEST_I_MSK 0xfffffe1f
+#define RG_DP_BBPLL_OD_TEST_SFT 5
+#define RG_DP_BBPLL_OD_TEST_HI 8
+#define RG_DP_BBPLL_OD_TEST_SZ 4
+#define RG_DP_BBPLL_PD_MSK 0x00000200
+#define RG_DP_BBPLL_PD_I_MSK 0xfffffdff
+#define RG_DP_BBPLL_PD_SFT 9
+#define RG_DP_BBPLL_PD_HI 9
+#define RG_DP_BBPLL_PD_SZ 1
+#define RG_DP_BBPLL_TESTSEL_MSK 0x00001c00
+#define RG_DP_BBPLL_TESTSEL_I_MSK 0xffffe3ff
+#define RG_DP_BBPLL_TESTSEL_SFT 10
+#define RG_DP_BBPLL_TESTSEL_HI 12
+#define RG_DP_BBPLL_TESTSEL_SZ 3
+#define RG_DP_BBPLL_PFD_DLY_MSK 0x00006000
+#define RG_DP_BBPLL_PFD_DLY_I_MSK 0xffff9fff
+#define RG_DP_BBPLL_PFD_DLY_SFT 13
+#define RG_DP_BBPLL_PFD_DLY_HI 14
+#define RG_DP_BBPLL_PFD_DLY_SZ 2
+#define RG_DP_RP_MSK 0x00038000
+#define RG_DP_RP_I_MSK 0xfffc7fff
+#define RG_DP_RP_SFT 15
+#define RG_DP_RP_HI 17
+#define RG_DP_RP_SZ 3
+#define RG_DP_RHP_MSK 0x000c0000
+#define RG_DP_RHP_I_MSK 0xfff3ffff
+#define RG_DP_RHP_SFT 18
+#define RG_DP_RHP_HI 19
+#define RG_DP_RHP_SZ 2
+#define RG_DP_BBPLL_SDM_EDGE_MSK 0x80000000
+#define RG_DP_BBPLL_SDM_EDGE_I_MSK 0x7fffffff
+#define RG_DP_BBPLL_SDM_EDGE_SFT 31
+#define RG_DP_BBPLL_SDM_EDGE_HI 31
+#define RG_DP_BBPLL_SDM_EDGE_SZ 1
+#define RG_DP_FODIV_MSK 0x0007f000
+#define RG_DP_FODIV_I_MSK 0xfff80fff
+#define RG_DP_FODIV_SFT 12
+#define RG_DP_FODIV_HI 18
+#define RG_DP_FODIV_SZ 7
+#define RG_DP_REFDIV_MSK 0x1fc00000
+#define RG_DP_REFDIV_I_MSK 0xe03fffff
+#define RG_DP_REFDIV_SFT 22
+#define RG_DP_REFDIV_HI 28
+#define RG_DP_REFDIV_SZ 7
+#define RG_IDACAI_PGAG15_MSK 0x0000003f
+#define RG_IDACAI_PGAG15_I_MSK 0xffffffc0
+#define RG_IDACAI_PGAG15_SFT 0
+#define RG_IDACAI_PGAG15_HI 5
+#define RG_IDACAI_PGAG15_SZ 6
+#define RG_IDACAQ_PGAG15_MSK 0x00000fc0
+#define RG_IDACAQ_PGAG15_I_MSK 0xfffff03f
+#define RG_IDACAQ_PGAG15_SFT 6
+#define RG_IDACAQ_PGAG15_HI 11
+#define RG_IDACAQ_PGAG15_SZ 6
+#define RG_IDACAI_PGAG14_MSK 0x0003f000
+#define RG_IDACAI_PGAG14_I_MSK 0xfffc0fff
+#define RG_IDACAI_PGAG14_SFT 12
+#define RG_IDACAI_PGAG14_HI 17
+#define RG_IDACAI_PGAG14_SZ 6
+#define RG_IDACAQ_PGAG14_MSK 0x00fc0000
+#define RG_IDACAQ_PGAG14_I_MSK 0xff03ffff
+#define RG_IDACAQ_PGAG14_SFT 18
+#define RG_IDACAQ_PGAG14_HI 23
+#define RG_IDACAQ_PGAG14_SZ 6
+#define RG_DP_BBPLL_BS_MSK 0x3f000000
+#define RG_DP_BBPLL_BS_I_MSK 0xc0ffffff
+#define RG_DP_BBPLL_BS_SFT 24
+#define RG_DP_BBPLL_BS_HI 29
+#define RG_DP_BBPLL_BS_SZ 6
+#define RG_IDACAI_PGAG13_MSK 0x0000003f
+#define RG_IDACAI_PGAG13_I_MSK 0xffffffc0
+#define RG_IDACAI_PGAG13_SFT 0
+#define RG_IDACAI_PGAG13_HI 5
+#define RG_IDACAI_PGAG13_SZ 6
+#define RG_IDACAQ_PGAG13_MSK 0x00000fc0
+#define RG_IDACAQ_PGAG13_I_MSK 0xfffff03f
+#define RG_IDACAQ_PGAG13_SFT 6
+#define RG_IDACAQ_PGAG13_HI 11
+#define RG_IDACAQ_PGAG13_SZ 6
+#define RG_IDACAI_PGAG12_MSK 0x0003f000
+#define RG_IDACAI_PGAG12_I_MSK 0xfffc0fff
+#define RG_IDACAI_PGAG12_SFT 12
+#define RG_IDACAI_PGAG12_HI 17
+#define RG_IDACAI_PGAG12_SZ 6
+#define RG_IDACAQ_PGAG12_MSK 0x00fc0000
+#define RG_IDACAQ_PGAG12_I_MSK 0xff03ffff
+#define RG_IDACAQ_PGAG12_SFT 18
+#define RG_IDACAQ_PGAG12_HI 23
+#define RG_IDACAQ_PGAG12_SZ 6
+#define RG_IDACAI_PGAG11_MSK 0x0000003f
+#define RG_IDACAI_PGAG11_I_MSK 0xffffffc0
+#define RG_IDACAI_PGAG11_SFT 0
+#define RG_IDACAI_PGAG11_HI 5
+#define RG_IDACAI_PGAG11_SZ 6
+#define RG_IDACAQ_PGAG11_MSK 0x00000fc0
+#define RG_IDACAQ_PGAG11_I_MSK 0xfffff03f
+#define RG_IDACAQ_PGAG11_SFT 6
+#define RG_IDACAQ_PGAG11_HI 11
+#define RG_IDACAQ_PGAG11_SZ 6
+#define RG_IDACAI_PGAG10_MSK 0x0003f000
+#define RG_IDACAI_PGAG10_I_MSK 0xfffc0fff
+#define RG_IDACAI_PGAG10_SFT 12
+#define RG_IDACAI_PGAG10_HI 17
+#define RG_IDACAI_PGAG10_SZ 6
+#define RG_IDACAQ_PGAG10_MSK 0x00fc0000
+#define RG_IDACAQ_PGAG10_I_MSK 0xff03ffff
+#define RG_IDACAQ_PGAG10_SFT 18
+#define RG_IDACAQ_PGAG10_HI 23
+#define RG_IDACAQ_PGAG10_SZ 6
+#define RG_IDACAI_PGAG9_MSK 0x0000003f
+#define RG_IDACAI_PGAG9_I_MSK 0xffffffc0
+#define RG_IDACAI_PGAG9_SFT 0
+#define RG_IDACAI_PGAG9_HI 5
+#define RG_IDACAI_PGAG9_SZ 6
+#define RG_IDACAQ_PGAG9_MSK 0x00000fc0
+#define RG_IDACAQ_PGAG9_I_MSK 0xfffff03f
+#define RG_IDACAQ_PGAG9_SFT 6
+#define RG_IDACAQ_PGAG9_HI 11
+#define RG_IDACAQ_PGAG9_SZ 6
+#define RG_IDACAI_PGAG8_MSK 0x0003f000
+#define RG_IDACAI_PGAG8_I_MSK 0xfffc0fff
+#define RG_IDACAI_PGAG8_SFT 12
+#define RG_IDACAI_PGAG8_HI 17
+#define RG_IDACAI_PGAG8_SZ 6
+#define RG_IDACAQ_PGAG8_MSK 0x00fc0000
+#define RG_IDACAQ_PGAG8_I_MSK 0xff03ffff
+#define RG_IDACAQ_PGAG8_SFT 18
+#define RG_IDACAQ_PGAG8_HI 23
+#define RG_IDACAQ_PGAG8_SZ 6
+#define RG_IDACAI_PGAG7_MSK 0x0000003f
+#define RG_IDACAI_PGAG7_I_MSK 0xffffffc0
+#define RG_IDACAI_PGAG7_SFT 0
+#define RG_IDACAI_PGAG7_HI 5
+#define RG_IDACAI_PGAG7_SZ 6
+#define RG_IDACAQ_PGAG7_MSK 0x00000fc0
+#define RG_IDACAQ_PGAG7_I_MSK 0xfffff03f
+#define RG_IDACAQ_PGAG7_SFT 6
+#define RG_IDACAQ_PGAG7_HI 11
+#define RG_IDACAQ_PGAG7_SZ 6
+#define RG_IDACAI_PGAG6_MSK 0x0003f000
+#define RG_IDACAI_PGAG6_I_MSK 0xfffc0fff
+#define RG_IDACAI_PGAG6_SFT 12
+#define RG_IDACAI_PGAG6_HI 17
+#define RG_IDACAI_PGAG6_SZ 6
+#define RG_IDACAQ_PGAG6_MSK 0x00fc0000
+#define RG_IDACAQ_PGAG6_I_MSK 0xff03ffff
+#define RG_IDACAQ_PGAG6_SFT 18
+#define RG_IDACAQ_PGAG6_HI 23
+#define RG_IDACAQ_PGAG6_SZ 6
+#define RG_IDACAI_PGAG5_MSK 0x0000003f
+#define RG_IDACAI_PGAG5_I_MSK 0xffffffc0
+#define RG_IDACAI_PGAG5_SFT 0
+#define RG_IDACAI_PGAG5_HI 5
+#define RG_IDACAI_PGAG5_SZ 6
+#define RG_IDACAQ_PGAG5_MSK 0x00000fc0
+#define RG_IDACAQ_PGAG5_I_MSK 0xfffff03f
+#define RG_IDACAQ_PGAG5_SFT 6
+#define RG_IDACAQ_PGAG5_HI 11
+#define RG_IDACAQ_PGAG5_SZ 6
+#define RG_IDACAI_PGAG4_MSK 0x0003f000
+#define RG_IDACAI_PGAG4_I_MSK 0xfffc0fff
+#define RG_IDACAI_PGAG4_SFT 12
+#define RG_IDACAI_PGAG4_HI 17
+#define RG_IDACAI_PGAG4_SZ 6
+#define RG_IDACAQ_PGAG4_MSK 0x00fc0000
+#define RG_IDACAQ_PGAG4_I_MSK 0xff03ffff
+#define RG_IDACAQ_PGAG4_SFT 18
+#define RG_IDACAQ_PGAG4_HI 23
+#define RG_IDACAQ_PGAG4_SZ 6
+#define RG_IDACAI_PGAG3_MSK 0x0000003f
+#define RG_IDACAI_PGAG3_I_MSK 0xffffffc0
+#define RG_IDACAI_PGAG3_SFT 0
+#define RG_IDACAI_PGAG3_HI 5
+#define RG_IDACAI_PGAG3_SZ 6
+#define RG_IDACAQ_PGAG3_MSK 0x00000fc0
+#define RG_IDACAQ_PGAG3_I_MSK 0xfffff03f
+#define RG_IDACAQ_PGAG3_SFT 6
+#define RG_IDACAQ_PGAG3_HI 11
+#define RG_IDACAQ_PGAG3_SZ 6
+#define RG_IDACAI_PGAG2_MSK 0x0003f000
+#define RG_IDACAI_PGAG2_I_MSK 0xfffc0fff
+#define RG_IDACAI_PGAG2_SFT 12
+#define RG_IDACAI_PGAG2_HI 17
+#define RG_IDACAI_PGAG2_SZ 6
+#define RG_IDACAQ_PGAG2_MSK 0x00fc0000
+#define RG_IDACAQ_PGAG2_I_MSK 0xff03ffff
+#define RG_IDACAQ_PGAG2_SFT 18
+#define RG_IDACAQ_PGAG2_HI 23
+#define RG_IDACAQ_PGAG2_SZ 6
+#define RG_IDACAI_PGAG1_MSK 0x0000003f
+#define RG_IDACAI_PGAG1_I_MSK 0xffffffc0
+#define RG_IDACAI_PGAG1_SFT 0
+#define RG_IDACAI_PGAG1_HI 5
+#define RG_IDACAI_PGAG1_SZ 6
+#define RG_IDACAQ_PGAG1_MSK 0x00000fc0
+#define RG_IDACAQ_PGAG1_I_MSK 0xfffff03f
+#define RG_IDACAQ_PGAG1_SFT 6
+#define RG_IDACAQ_PGAG1_HI 11
+#define RG_IDACAQ_PGAG1_SZ 6
+#define RG_IDACAI_PGAG0_MSK 0x0003f000
+#define RG_IDACAI_PGAG0_I_MSK 0xfffc0fff
+#define RG_IDACAI_PGAG0_SFT 12
+#define RG_IDACAI_PGAG0_HI 17
+#define RG_IDACAI_PGAG0_SZ 6
+#define RG_IDACAQ_PGAG0_MSK 0x00fc0000
+#define RG_IDACAQ_PGAG0_I_MSK 0xff03ffff
+#define RG_IDACAQ_PGAG0_SFT 18
+#define RG_IDACAQ_PGAG0_HI 23
+#define RG_IDACAQ_PGAG0_SZ 6
+#define RG_EN_RCAL_MSK 0x00000001
+#define RG_EN_RCAL_I_MSK 0xfffffffe
+#define RG_EN_RCAL_SFT 0
+#define RG_EN_RCAL_HI 0
+#define RG_EN_RCAL_SZ 1
+#define RG_RCAL_SPD_MSK 0x00000002
+#define RG_RCAL_SPD_I_MSK 0xfffffffd
+#define RG_RCAL_SPD_SFT 1
+#define RG_RCAL_SPD_HI 1
+#define RG_RCAL_SPD_SZ 1
+#define RG_RCAL_TMR_MSK 0x000001fc
+#define RG_RCAL_TMR_I_MSK 0xfffffe03
+#define RG_RCAL_TMR_SFT 2
+#define RG_RCAL_TMR_HI 8
+#define RG_RCAL_TMR_SZ 7
+#define RG_RCAL_CODE_CWR_MSK 0x00000200
+#define RG_RCAL_CODE_CWR_I_MSK 0xfffffdff
+#define RG_RCAL_CODE_CWR_SFT 9
+#define RG_RCAL_CODE_CWR_HI 9
+#define RG_RCAL_CODE_CWR_SZ 1
+#define RG_RCAL_CODE_CWD_MSK 0x00007c00
+#define RG_RCAL_CODE_CWD_I_MSK 0xffff83ff
+#define RG_RCAL_CODE_CWD_SFT 10
+#define RG_RCAL_CODE_CWD_HI 14
+#define RG_RCAL_CODE_CWD_SZ 5
+#define RG_SX_SUB_SEL_CWR_MSK 0x00000001
+#define RG_SX_SUB_SEL_CWR_I_MSK 0xfffffffe
+#define RG_SX_SUB_SEL_CWR_SFT 0
+#define RG_SX_SUB_SEL_CWR_HI 0
+#define RG_SX_SUB_SEL_CWR_SZ 1
+#define RG_SX_SUB_SEL_CWD_MSK 0x000000fe
+#define RG_SX_SUB_SEL_CWD_I_MSK 0xffffff01
+#define RG_SX_SUB_SEL_CWD_SFT 1
+#define RG_SX_SUB_SEL_CWD_HI 7
+#define RG_SX_SUB_SEL_CWD_SZ 7
+#define RG_SX_LCK_BIN_OFFSET_MSK 0x00078000
+#define RG_SX_LCK_BIN_OFFSET_I_MSK 0xfff87fff
+#define RG_SX_LCK_BIN_OFFSET_SFT 15
+#define RG_SX_LCK_BIN_OFFSET_HI 18
+#define RG_SX_LCK_BIN_OFFSET_SZ 4
+#define RG_SX_LCK_BIN_PRECISION_MSK 0x00080000
+#define RG_SX_LCK_BIN_PRECISION_I_MSK 0xfff7ffff
+#define RG_SX_LCK_BIN_PRECISION_SFT 19
+#define RG_SX_LCK_BIN_PRECISION_HI 19
+#define RG_SX_LCK_BIN_PRECISION_SZ 1
+#define RG_SX_LOCK_EN_N_MSK 0x00100000
+#define RG_SX_LOCK_EN_N_I_MSK 0xffefffff
+#define RG_SX_LOCK_EN_N_SFT 20
+#define RG_SX_LOCK_EN_N_HI 20
+#define RG_SX_LOCK_EN_N_SZ 1
+#define RG_SX_LOCK_MANUAL_MSK 0x00200000
+#define RG_SX_LOCK_MANUAL_I_MSK 0xffdfffff
+#define RG_SX_LOCK_MANUAL_SFT 21
+#define RG_SX_LOCK_MANUAL_HI 21
+#define RG_SX_LOCK_MANUAL_SZ 1
+#define RG_SX_SUB_MANUAL_MSK 0x00400000
+#define RG_SX_SUB_MANUAL_I_MSK 0xffbfffff
+#define RG_SX_SUB_MANUAL_SFT 22
+#define RG_SX_SUB_MANUAL_HI 22
+#define RG_SX_SUB_MANUAL_SZ 1
+#define RG_SX_SUB_SEL_MSK 0x3f800000
+#define RG_SX_SUB_SEL_I_MSK 0xc07fffff
+#define RG_SX_SUB_SEL_SFT 23
+#define RG_SX_SUB_SEL_HI 29
+#define RG_SX_SUB_SEL_SZ 7
+#define RG_SX_MUX_SEL_VTH_BINL_MSK 0x40000000
+#define RG_SX_MUX_SEL_VTH_BINL_I_MSK 0xbfffffff
+#define RG_SX_MUX_SEL_VTH_BINL_SFT 30
+#define RG_SX_MUX_SEL_VTH_BINL_HI 30
+#define RG_SX_MUX_SEL_VTH_BINL_SZ 1
+#define RG_TRX_DUMMMY_MSK 0xffffffff
+#define RG_TRX_DUMMMY_I_MSK 0x00000000
+#define RG_TRX_DUMMMY_SFT 0
+#define RG_TRX_DUMMMY_HI 31
+#define RG_TRX_DUMMMY_SZ 32
+#define RG_SX_DUMMMY_MSK 0xffffffff
+#define RG_SX_DUMMMY_I_MSK 0x00000000
+#define RG_SX_DUMMMY_SFT 0
+#define RG_SX_DUMMMY_HI 31
+#define RG_SX_DUMMMY_SZ 32
+#define RCAL_RDY_MSK 0x00000001
+#define RCAL_RDY_I_MSK 0xfffffffe
+#define RCAL_RDY_SFT 0
+#define RCAL_RDY_HI 0
+#define RCAL_RDY_SZ 1
+#define LCK_BIN_RDY_MSK 0x00000002
+#define LCK_BIN_RDY_I_MSK 0xfffffffd
+#define LCK_BIN_RDY_SFT 1
+#define LCK_BIN_RDY_HI 1
+#define LCK_BIN_RDY_SZ 1
+#define VT_MON_RDY_MSK 0x00000004
+#define VT_MON_RDY_I_MSK 0xfffffffb
+#define VT_MON_RDY_SFT 2
+#define VT_MON_RDY_HI 2
+#define VT_MON_RDY_SZ 1
+#define DA_R_CODE_LUT_MSK 0x000007c0
+#define DA_R_CODE_LUT_I_MSK 0xfffff83f
+#define DA_R_CODE_LUT_SFT 6
+#define DA_R_CODE_LUT_HI 10
+#define DA_R_CODE_LUT_SZ 5
+#define AD_SX_VT_MON_Q_MSK 0x00001800
+#define AD_SX_VT_MON_Q_I_MSK 0xffffe7ff
+#define AD_SX_VT_MON_Q_SFT 11
+#define AD_SX_VT_MON_Q_HI 12
+#define AD_SX_VT_MON_Q_SZ 2
+#define AD_DP_VT_MON_Q_MSK 0x00006000
+#define AD_DP_VT_MON_Q_I_MSK 0xffff9fff
+#define AD_DP_VT_MON_Q_SFT 13
+#define AD_DP_VT_MON_Q_HI 14
+#define AD_DP_VT_MON_Q_SZ 2
+#define RTC_CAL_RDY_MSK 0x00008000
+#define RTC_CAL_RDY_I_MSK 0xffff7fff
+#define RTC_CAL_RDY_SFT 15
+#define RTC_CAL_RDY_HI 15
+#define RTC_CAL_RDY_SZ 1
+#define RG_SARADC_BIT_MSK 0x003f0000
+#define RG_SARADC_BIT_I_MSK 0xffc0ffff
+#define RG_SARADC_BIT_SFT 16
+#define RG_SARADC_BIT_HI 21
+#define RG_SARADC_BIT_SZ 6
+#define SAR_ADC_FSM_RDY_MSK 0x00400000
+#define SAR_ADC_FSM_RDY_I_MSK 0xffbfffff
+#define SAR_ADC_FSM_RDY_SFT 22
+#define SAR_ADC_FSM_RDY_HI 22
+#define SAR_ADC_FSM_RDY_SZ 1
+#define AD_CIRCUIT_VERSION_MSK 0x07800000
+#define AD_CIRCUIT_VERSION_I_MSK 0xf87fffff
+#define AD_CIRCUIT_VERSION_SFT 23
+#define AD_CIRCUIT_VERSION_HI 26
+#define AD_CIRCUIT_VERSION_SZ 4
+#define DA_R_CAL_CODE_MSK 0x0000001f
+#define DA_R_CAL_CODE_I_MSK 0xffffffe0
+#define DA_R_CAL_CODE_SFT 0
+#define DA_R_CAL_CODE_HI 4
+#define DA_R_CAL_CODE_SZ 5
+#define DA_SX_SUB_SEL_MSK 0x00000fe0
+#define DA_SX_SUB_SEL_I_MSK 0xfffff01f
+#define DA_SX_SUB_SEL_SFT 5
+#define DA_SX_SUB_SEL_HI 11
+#define DA_SX_SUB_SEL_SZ 7
+#define RG_DPL_RFCTRL_CH_MSK 0x000007ff
+#define RG_DPL_RFCTRL_CH_I_MSK 0xfffff800
+#define RG_DPL_RFCTRL_CH_SFT 0
+#define RG_DPL_RFCTRL_CH_HI 10
+#define RG_DPL_RFCTRL_CH_SZ 11
+#define RG_RSSIADC_RO_BIT_MSK 0x00007800
+#define RG_RSSIADC_RO_BIT_I_MSK 0xffff87ff
+#define RG_RSSIADC_RO_BIT_SFT 11
+#define RG_RSSIADC_RO_BIT_HI 14
+#define RG_RSSIADC_RO_BIT_SZ 4
+#define RG_RX_ADC_I_RO_BIT_MSK 0x007f8000
+#define RG_RX_ADC_I_RO_BIT_I_MSK 0xff807fff
+#define RG_RX_ADC_I_RO_BIT_SFT 15
+#define RG_RX_ADC_I_RO_BIT_HI 22
+#define RG_RX_ADC_I_RO_BIT_SZ 8
+#define RG_RX_ADC_Q_RO_BIT_MSK 0x7f800000
+#define RG_RX_ADC_Q_RO_BIT_I_MSK 0x807fffff
+#define RG_RX_ADC_Q_RO_BIT_SFT 23
+#define RG_RX_ADC_Q_RO_BIT_HI 30
+#define RG_RX_ADC_Q_RO_BIT_SZ 8
+#define RG_DPL_RFCTRL_F_MSK 0x00ffffff
+#define RG_DPL_RFCTRL_F_I_MSK 0xff000000
+#define RG_DPL_RFCTRL_F_SFT 0
+#define RG_DPL_RFCTRL_F_HI 23
+#define RG_DPL_RFCTRL_F_SZ 24
+#define RG_SX_TARGET_CNT_MSK 0x00001fff
+#define RG_SX_TARGET_CNT_I_MSK 0xffffe000
+#define RG_SX_TARGET_CNT_SFT 0
+#define RG_SX_TARGET_CNT_HI 12
+#define RG_SX_TARGET_CNT_SZ 13
+#define RG_RTC_OFFSET_MSK 0x000000ff
+#define RG_RTC_OFFSET_I_MSK 0xffffff00
+#define RG_RTC_OFFSET_SFT 0
+#define RG_RTC_OFFSET_HI 7
+#define RG_RTC_OFFSET_SZ 8
+#define RG_RTC_CAL_TARGET_COUNT_MSK 0x000fff00
+#define RG_RTC_CAL_TARGET_COUNT_I_MSK 0xfff000ff
+#define RG_RTC_CAL_TARGET_COUNT_SFT 8
+#define RG_RTC_CAL_TARGET_COUNT_HI 19
+#define RG_RTC_CAL_TARGET_COUNT_SZ 12
+#define RG_RF_D_REG_MSK 0x0000ffff
+#define RG_RF_D_REG_I_MSK 0xffff0000
+#define RG_RF_D_REG_SFT 0
+#define RG_RF_D_REG_HI 15
+#define RG_RF_D_REG_SZ 16
+#define DIRECT_MODE_MSK 0x00000001
+#define DIRECT_MODE_I_MSK 0xfffffffe
+#define DIRECT_MODE_SFT 0
+#define DIRECT_MODE_HI 0
+#define DIRECT_MODE_SZ 1
+#define TAG_INTERLEAVE_MD_MSK 0x00000002
+#define TAG_INTERLEAVE_MD_I_MSK 0xfffffffd
+#define TAG_INTERLEAVE_MD_SFT 1
+#define TAG_INTERLEAVE_MD_HI 1
+#define TAG_INTERLEAVE_MD_SZ 1
+#define DIS_DEMAND_MSK 0x00000004
+#define DIS_DEMAND_I_MSK 0xfffffffb
+#define DIS_DEMAND_SFT 2
+#define DIS_DEMAND_HI 2
+#define DIS_DEMAND_SZ 1
+#define SAME_ID_ALLOC_MD_MSK 0x00000008
+#define SAME_ID_ALLOC_MD_I_MSK 0xfffffff7
+#define SAME_ID_ALLOC_MD_SFT 3
+#define SAME_ID_ALLOC_MD_HI 3
+#define SAME_ID_ALLOC_MD_SZ 1
+#define HS_ACCESS_MD_MSK 0x00000010
+#define HS_ACCESS_MD_I_MSK 0xffffffef
+#define HS_ACCESS_MD_SFT 4
+#define HS_ACCESS_MD_HI 4
+#define HS_ACCESS_MD_SZ 1
+#define SRAM_ACCESS_MD_MSK 0x00000020
+#define SRAM_ACCESS_MD_I_MSK 0xffffffdf
+#define SRAM_ACCESS_MD_SFT 5
+#define SRAM_ACCESS_MD_HI 5
+#define SRAM_ACCESS_MD_SZ 1
+#define NOHIT_RPASS_MD_MSK 0x00000040
+#define NOHIT_RPASS_MD_I_MSK 0xffffffbf
+#define NOHIT_RPASS_MD_SFT 6
+#define NOHIT_RPASS_MD_HI 6
+#define NOHIT_RPASS_MD_SZ 1
+#define DMN_FLAG_CLR_MSK 0x00000080
+#define DMN_FLAG_CLR_I_MSK 0xffffff7f
+#define DMN_FLAG_CLR_SFT 7
+#define DMN_FLAG_CLR_HI 7
+#define DMN_FLAG_CLR_SZ 1
+#define ERR_SW_RST_N_MSK 0x00000100
+#define ERR_SW_RST_N_I_MSK 0xfffffeff
+#define ERR_SW_RST_N_SFT 8
+#define ERR_SW_RST_N_HI 8
+#define ERR_SW_RST_N_SZ 1
+#define ALR_SW_RST_N_MSK 0x00000200
+#define ALR_SW_RST_N_I_MSK 0xfffffdff
+#define ALR_SW_RST_N_SFT 9
+#define ALR_SW_RST_N_HI 9
+#define ALR_SW_RST_N_SZ 1
+#define MCH_SW_RST_N_MSK 0x00000400
+#define MCH_SW_RST_N_I_MSK 0xfffffbff
+#define MCH_SW_RST_N_SFT 10
+#define MCH_SW_RST_N_HI 10
+#define MCH_SW_RST_N_SZ 1
+#define TAG_SW_RST_N_MSK 0x00000800
+#define TAG_SW_RST_N_I_MSK 0xfffff7ff
+#define TAG_SW_RST_N_SFT 11
+#define TAG_SW_RST_N_HI 11
+#define TAG_SW_RST_N_SZ 1
+#define ABT_SW_RST_N_MSK 0x00001000
+#define ABT_SW_RST_N_I_MSK 0xffffefff
+#define ABT_SW_RST_N_SFT 12
+#define ABT_SW_RST_N_HI 12
+#define ABT_SW_RST_N_SZ 1
+#define MMU_VER_MSK 0x0000e000
+#define MMU_VER_I_MSK 0xffff1fff
+#define MMU_VER_SFT 13
+#define MMU_VER_HI 15
+#define MMU_VER_SZ 3
+#define MMU_SHARE_MCU_MSK 0x00ff0000
+#define MMU_SHARE_MCU_I_MSK 0xff00ffff
+#define MMU_SHARE_MCU_SFT 16
+#define MMU_SHARE_MCU_HI 23
+#define MMU_SHARE_MCU_SZ 8
+#define HS_WR_MSK 0x00000001
+#define HS_WR_I_MSK 0xfffffffe
+#define HS_WR_SFT 0
+#define HS_WR_HI 0
+#define HS_WR_SZ 1
+#define HS_FLAG_MSK 0x00000010
+#define HS_FLAG_I_MSK 0xffffffef
+#define HS_FLAG_SFT 4
+#define HS_FLAG_HI 4
+#define HS_FLAG_SZ 1
+#define HS_ID_MSK 0x00007f00
+#define HS_ID_I_MSK 0xffff80ff
+#define HS_ID_SFT 8
+#define HS_ID_HI 14
+#define HS_ID_SZ 7
+#define HS_CHANNEL_MSK 0x000f0000
+#define HS_CHANNEL_I_MSK 0xfff0ffff
+#define HS_CHANNEL_SFT 16
+#define HS_CHANNEL_HI 19
+#define HS_CHANNEL_SZ 4
+#define HS_PAGE_MSK 0x00f00000
+#define HS_PAGE_I_MSK 0xff0fffff
+#define HS_PAGE_SFT 20
+#define HS_PAGE_HI 23
+#define HS_PAGE_SZ 4
+#define HS_DATA_MSK 0xff000000
+#define HS_DATA_I_MSK 0x00ffffff
+#define HS_DATA_SFT 24
+#define HS_DATA_HI 31
+#define HS_DATA_SZ 8
+#define CPU_POR0_MSK 0x0000000f
+#define CPU_POR0_I_MSK 0xfffffff0
+#define CPU_POR0_SFT 0
+#define CPU_POR0_HI 3
+#define CPU_POR0_SZ 4
+#define CPU_POR1_MSK 0x000000f0
+#define CPU_POR1_I_MSK 0xffffff0f
+#define CPU_POR1_SFT 4
+#define CPU_POR1_HI 7
+#define CPU_POR1_SZ 4
+#define CPU_POR2_MSK 0x00000f00
+#define CPU_POR2_I_MSK 0xfffff0ff
+#define CPU_POR2_SFT 8
+#define CPU_POR2_HI 11
+#define CPU_POR2_SZ 4
+#define CPU_POR3_MSK 0x0000f000
+#define CPU_POR3_I_MSK 0xffff0fff
+#define CPU_POR3_SFT 12
+#define CPU_POR3_HI 15
+#define CPU_POR3_SZ 4
+#define CPU_POR4_MSK 0x000f0000
+#define CPU_POR4_I_MSK 0xfff0ffff
+#define CPU_POR4_SFT 16
+#define CPU_POR4_HI 19
+#define CPU_POR4_SZ 4
+#define CPU_POR5_MSK 0x00f00000
+#define CPU_POR5_I_MSK 0xff0fffff
+#define CPU_POR5_SFT 20
+#define CPU_POR5_HI 23
+#define CPU_POR5_SZ 4
+#define CPU_POR6_MSK 0x0f000000
+#define CPU_POR6_I_MSK 0xf0ffffff
+#define CPU_POR6_SFT 24
+#define CPU_POR6_HI 27
+#define CPU_POR6_SZ 4
+#define CPU_POR7_MSK 0xf0000000
+#define CPU_POR7_I_MSK 0x0fffffff
+#define CPU_POR7_SFT 28
+#define CPU_POR7_HI 31
+#define CPU_POR7_SZ 4
+#define CPU_POR8_MSK 0x0000000f
+#define CPU_POR8_I_MSK 0xfffffff0
+#define CPU_POR8_SFT 0
+#define CPU_POR8_HI 3
+#define CPU_POR8_SZ 4
+#define CPU_POR9_MSK 0x000000f0
+#define CPU_POR9_I_MSK 0xffffff0f
+#define CPU_POR9_SFT 4
+#define CPU_POR9_HI 7
+#define CPU_POR9_SZ 4
+#define CPU_PORA_MSK 0x00000f00
+#define CPU_PORA_I_MSK 0xfffff0ff
+#define CPU_PORA_SFT 8
+#define CPU_PORA_HI 11
+#define CPU_PORA_SZ 4
+#define CPU_PORB_MSK 0x0000f000
+#define CPU_PORB_I_MSK 0xffff0fff
+#define CPU_PORB_SFT 12
+#define CPU_PORB_HI 15
+#define CPU_PORB_SZ 4
+#define CPU_PORC_MSK 0x000f0000
+#define CPU_PORC_I_MSK 0xfff0ffff
+#define CPU_PORC_SFT 16
+#define CPU_PORC_HI 19
+#define CPU_PORC_SZ 4
+#define CPU_PORD_MSK 0x00f00000
+#define CPU_PORD_I_MSK 0xff0fffff
+#define CPU_PORD_SFT 20
+#define CPU_PORD_HI 23
+#define CPU_PORD_SZ 4
+#define CPU_PORE_MSK 0x0f000000
+#define CPU_PORE_I_MSK 0xf0ffffff
+#define CPU_PORE_SFT 24
+#define CPU_PORE_HI 27
+#define CPU_PORE_SZ 4
+#define CPU_PORF_MSK 0xf0000000
+#define CPU_PORF_I_MSK 0x0fffffff
+#define CPU_PORF_SFT 28
+#define CPU_PORF_HI 31
+#define CPU_PORF_SZ 4
+#define ACC_WR_LEN_MSK 0x0000003f
+#define ACC_WR_LEN_I_MSK 0xffffffc0
+#define ACC_WR_LEN_SFT 0
+#define ACC_WR_LEN_HI 5
+#define ACC_WR_LEN_SZ 6
+#define ACC_RD_LEN_MSK 0x00003f00
+#define ACC_RD_LEN_I_MSK 0xffffc0ff
+#define ACC_RD_LEN_SFT 8
+#define ACC_RD_LEN_HI 13
+#define ACC_RD_LEN_SZ 6
+#define REQ_NACK_CLR_MSK 0x00008000
+#define REQ_NACK_CLR_I_MSK 0xffff7fff
+#define REQ_NACK_CLR_SFT 15
+#define REQ_NACK_CLR_HI 15
+#define REQ_NACK_CLR_SZ 1
+#define NACK_FLAG_BUS_MSK 0xffff0000
+#define NACK_FLAG_BUS_I_MSK 0x0000ffff
+#define NACK_FLAG_BUS_SFT 16
+#define NACK_FLAG_BUS_HI 31
+#define NACK_FLAG_BUS_SZ 16
+#define DMN_R_PASS_MSK 0x0000ffff
+#define DMN_R_PASS_I_MSK 0xffff0000
+#define DMN_R_PASS_SFT 0
+#define DMN_R_PASS_HI 15
+#define DMN_R_PASS_SZ 16
+#define PARA_ALC_RLS_MSK 0x00010000
+#define PARA_ALC_RLS_I_MSK 0xfffeffff
+#define PARA_ALC_RLS_SFT 16
+#define PARA_ALC_RLS_HI 16
+#define PARA_ALC_RLS_SZ 1
+#define REQ_PORNS_CHGEN_MSK 0x01000000
+#define REQ_PORNS_CHGEN_I_MSK 0xfeffffff
+#define REQ_PORNS_CHGEN_SFT 24
+#define REQ_PORNS_CHGEN_HI 24
+#define REQ_PORNS_CHGEN_SZ 1
+#define ALC_ABT_ID_MSK 0x0000007f
+#define ALC_ABT_ID_I_MSK 0xffffff80
+#define ALC_ABT_ID_SFT 0
+#define ALC_ABT_ID_HI 6
+#define ALC_ABT_ID_SZ 7
+#define ALC_ABT_INT_MSK 0x00008000
+#define ALC_ABT_INT_I_MSK 0xffff7fff
+#define ALC_ABT_INT_SFT 15
+#define ALC_ABT_INT_HI 15
+#define ALC_ABT_INT_SZ 1
+#define RLS_ABT_ID_MSK 0x007f0000
+#define RLS_ABT_ID_I_MSK 0xff80ffff
+#define RLS_ABT_ID_SFT 16
+#define RLS_ABT_ID_HI 22
+#define RLS_ABT_ID_SZ 7
+#define RLS_ABT_INT_MSK 0x80000000
+#define RLS_ABT_INT_I_MSK 0x7fffffff
+#define RLS_ABT_INT_SFT 31
+#define RLS_ABT_INT_HI 31
+#define RLS_ABT_INT_SZ 1
+#define DEBUG_CTL_MSK 0x000000ff
+#define DEBUG_CTL_I_MSK 0xffffff00
+#define DEBUG_CTL_SFT 0
+#define DEBUG_CTL_HI 7
+#define DEBUG_CTL_SZ 8
+#define DEBUG_H16_MSK 0x00000100
+#define DEBUG_H16_I_MSK 0xfffffeff
+#define DEBUG_H16_SFT 8
+#define DEBUG_H16_HI 8
+#define DEBUG_H16_SZ 1
+#define DEBUG_OUT_MSK 0xffffffff
+#define DEBUG_OUT_I_MSK 0x00000000
+#define DEBUG_OUT_SFT 0
+#define DEBUG_OUT_HI 31
+#define DEBUG_OUT_SZ 32
+#define ALC_ERR_MSK 0x00000001
+#define ALC_ERR_I_MSK 0xfffffffe
+#define ALC_ERR_SFT 0
+#define ALC_ERR_HI 0
+#define ALC_ERR_SZ 1
+#define RLS_ERR_MSK 0x00000002
+#define RLS_ERR_I_MSK 0xfffffffd
+#define RLS_ERR_SFT 1
+#define RLS_ERR_HI 1
+#define RLS_ERR_SZ 1
+#define AL_STATE_MSK 0x00000700
+#define AL_STATE_I_MSK 0xfffff8ff
+#define AL_STATE_SFT 8
+#define AL_STATE_HI 10
+#define AL_STATE_SZ 3
+#define RL_STATE_MSK 0x00007000
+#define RL_STATE_I_MSK 0xffff8fff
+#define RL_STATE_SFT 12
+#define RL_STATE_HI 14
+#define RL_STATE_SZ 3
+#define ALC_ERR_ID_MSK 0x007f0000
+#define ALC_ERR_ID_I_MSK 0xff80ffff
+#define ALC_ERR_ID_SFT 16
+#define ALC_ERR_ID_HI 22
+#define ALC_ERR_ID_SZ 7
+#define RLS_ERR_ID_MSK 0x7f000000
+#define RLS_ERR_ID_I_MSK 0x80ffffff
+#define RLS_ERR_ID_SFT 24
+#define RLS_ERR_ID_HI 30
+#define RLS_ERR_ID_SZ 7
+#define DMN_NOHIT_FLAG_MSK 0x00000001
+#define DMN_NOHIT_FLAG_I_MSK 0xfffffffe
+#define DMN_NOHIT_FLAG_SFT 0
+#define DMN_NOHIT_FLAG_HI 0
+#define DMN_NOHIT_FLAG_SZ 1
+#define DMN_FLAG_MSK 0x00000002
+#define DMN_FLAG_I_MSK 0xfffffffd
+#define DMN_FLAG_SFT 1
+#define DMN_FLAG_HI 1
+#define DMN_FLAG_SZ 1
+#define DMN_WR_MSK 0x00000008
+#define DMN_WR_I_MSK 0xfffffff7
+#define DMN_WR_SFT 3
+#define DMN_WR_HI 3
+#define DMN_WR_SZ 1
+#define DMN_PORT_MSK 0x000000f0
+#define DMN_PORT_I_MSK 0xffffff0f
+#define DMN_PORT_SFT 4
+#define DMN_PORT_HI 7
+#define DMN_PORT_SZ 4
+#define DMN_NHIT_ID_MSK 0x00007f00
+#define DMN_NHIT_ID_I_MSK 0xffff80ff
+#define DMN_NHIT_ID_SFT 8
+#define DMN_NHIT_ID_HI 14
+#define DMN_NHIT_ID_SZ 7
+#define DMN_NHIT_ADDR_MSK 0xffff0000
+#define DMN_NHIT_ADDR_I_MSK 0x0000ffff
+#define DMN_NHIT_ADDR_SFT 16
+#define DMN_NHIT_ADDR_HI 31
+#define DMN_NHIT_ADDR_SZ 16
+#define TX_MOUNT_MSK 0x000000ff
+#define TX_MOUNT_I_MSK 0xffffff00
+#define TX_MOUNT_SFT 0
+#define TX_MOUNT_HI 7
+#define TX_MOUNT_SZ 8
+#define RX_MOUNT_MSK 0x0000ff00
+#define RX_MOUNT_I_MSK 0xffff00ff
+#define RX_MOUNT_SFT 8
+#define RX_MOUNT_HI 15
+#define RX_MOUNT_SZ 8
+#define AVA_TAG_MSK 0x01ff0000
+#define AVA_TAG_I_MSK 0xfe00ffff
+#define AVA_TAG_SFT 16
+#define AVA_TAG_HI 24
+#define AVA_TAG_SZ 9
+#define PKTBUF_FULL_MSK 0x80000000
+#define PKTBUF_FULL_I_MSK 0x7fffffff
+#define PKTBUF_FULL_SFT 31
+#define PKTBUF_FULL_HI 31
+#define PKTBUF_FULL_SZ 1
+#define DMN_NOHIT_MCU_MSK 0x00000001
+#define DMN_NOHIT_MCU_I_MSK 0xfffffffe
+#define DMN_NOHIT_MCU_SFT 0
+#define DMN_NOHIT_MCU_HI 0
+#define DMN_NOHIT_MCU_SZ 1
+#define DMN_MCU_FLAG_MSK 0x00000002
+#define DMN_MCU_FLAG_I_MSK 0xfffffffd
+#define DMN_MCU_FLAG_SFT 1
+#define DMN_MCU_FLAG_HI 1
+#define DMN_MCU_FLAG_SZ 1
+#define DMN_MCU_WR_MSK 0x00000008
+#define DMN_MCU_WR_I_MSK 0xfffffff7
+#define DMN_MCU_WR_SFT 3
+#define DMN_MCU_WR_HI 3
+#define DMN_MCU_WR_SZ 1
+#define DMN_MCU_PORT_MSK 0x000000f0
+#define DMN_MCU_PORT_I_MSK 0xffffff0f
+#define DMN_MCU_PORT_SFT 4
+#define DMN_MCU_PORT_HI 7
+#define DMN_MCU_PORT_SZ 4
+#define DMN_MCU_ID_MSK 0x00007f00
+#define DMN_MCU_ID_I_MSK 0xffff80ff
+#define DMN_MCU_ID_SFT 8
+#define DMN_MCU_ID_HI 14
+#define DMN_MCU_ID_SZ 7
+#define DMN_MCU_ADDR_MSK 0xffff0000
+#define DMN_MCU_ADDR_I_MSK 0x0000ffff
+#define DMN_MCU_ADDR_SFT 16
+#define DMN_MCU_ADDR_HI 31
+#define DMN_MCU_ADDR_SZ 16
+#define MB_IDTBL_31_0_MSK 0xffffffff
+#define MB_IDTBL_31_0_I_MSK 0x00000000
+#define MB_IDTBL_31_0_SFT 0
+#define MB_IDTBL_31_0_HI 31
+#define MB_IDTBL_31_0_SZ 32
+#define MB_IDTBL_63_32_MSK 0xffffffff
+#define MB_IDTBL_63_32_I_MSK 0x00000000
+#define MB_IDTBL_63_32_SFT 0
+#define MB_IDTBL_63_32_HI 31
+#define MB_IDTBL_63_32_SZ 32
+#define MB_IDTBL_95_64_MSK 0xffffffff
+#define MB_IDTBL_95_64_I_MSK 0x00000000
+#define MB_IDTBL_95_64_SFT 0
+#define MB_IDTBL_95_64_HI 31
+#define MB_IDTBL_95_64_SZ 32
+#define MB_IDTBL_127_96_MSK 0xffffffff
+#define MB_IDTBL_127_96_I_MSK 0x00000000
+#define MB_IDTBL_127_96_SFT 0
+#define MB_IDTBL_127_96_HI 31
+#define MB_IDTBL_127_96_SZ 32
+#define PKT_IDTBL_31_0_MSK 0xffffffff
+#define PKT_IDTBL_31_0_I_MSK 0x00000000
+#define PKT_IDTBL_31_0_SFT 0
+#define PKT_IDTBL_31_0_HI 31
+#define PKT_IDTBL_31_0_SZ 32
+#define PKT_IDTBL_63_32_MSK 0xffffffff
+#define PKT_IDTBL_63_32_I_MSK 0x00000000
+#define PKT_IDTBL_63_32_SFT 0
+#define PKT_IDTBL_63_32_HI 31
+#define PKT_IDTBL_63_32_SZ 32
+#define PKT_IDTBL_95_64_MSK 0xffffffff
+#define PKT_IDTBL_95_64_I_MSK 0x00000000
+#define PKT_IDTBL_95_64_SFT 0
+#define PKT_IDTBL_95_64_HI 31
+#define PKT_IDTBL_95_64_SZ 32
+#define PKT_IDTBL_127_96_MSK 0xffffffff
+#define PKT_IDTBL_127_96_I_MSK 0x00000000
+#define PKT_IDTBL_127_96_SFT 0
+#define PKT_IDTBL_127_96_HI 31
+#define PKT_IDTBL_127_96_SZ 32
+#define DMN_IDTBL_31_0_MSK 0xffffffff
+#define DMN_IDTBL_31_0_I_MSK 0x00000000
+#define DMN_IDTBL_31_0_SFT 0
+#define DMN_IDTBL_31_0_HI 31
+#define DMN_IDTBL_31_0_SZ 32
+#define DMN_IDTBL_63_32_MSK 0xffffffff
+#define DMN_IDTBL_63_32_I_MSK 0x00000000
+#define DMN_IDTBL_63_32_SFT 0
+#define DMN_IDTBL_63_32_HI 31
+#define DMN_IDTBL_63_32_SZ 32
+#define DMN_IDTBL_95_64_MSK 0xffffffff
+#define DMN_IDTBL_95_64_I_MSK 0x00000000
+#define DMN_IDTBL_95_64_SFT 0
+#define DMN_IDTBL_95_64_HI 31
+#define DMN_IDTBL_95_64_SZ 32
+#define DMN_IDTBL_127_96_MSK 0xffffffff
+#define DMN_IDTBL_127_96_I_MSK 0x00000000
+#define DMN_IDTBL_127_96_SFT 0
+#define DMN_IDTBL_127_96_HI 31
+#define DMN_IDTBL_127_96_SZ 32
+#define NEQ_MB_ID_31_0_MSK 0xffffffff
+#define NEQ_MB_ID_31_0_I_MSK 0x00000000
+#define NEQ_MB_ID_31_0_SFT 0
+#define NEQ_MB_ID_31_0_HI 31
+#define NEQ_MB_ID_31_0_SZ 32
+#define NEQ_MB_ID_63_32_MSK 0xffffffff
+#define NEQ_MB_ID_63_32_I_MSK 0x00000000
+#define NEQ_MB_ID_63_32_SFT 0
+#define NEQ_MB_ID_63_32_HI 31
+#define NEQ_MB_ID_63_32_SZ 32
+#define NEQ_MB_ID_95_64_MSK 0xffffffff
+#define NEQ_MB_ID_95_64_I_MSK 0x00000000
+#define NEQ_MB_ID_95_64_SFT 0
+#define NEQ_MB_ID_95_64_HI 31
+#define NEQ_MB_ID_95_64_SZ 32
+#define NEQ_MB_ID_127_96_MSK 0xffffffff
+#define NEQ_MB_ID_127_96_I_MSK 0x00000000
+#define NEQ_MB_ID_127_96_SFT 0
+#define NEQ_MB_ID_127_96_HI 31
+#define NEQ_MB_ID_127_96_SZ 32
+#define NEQ_PKT_ID_31_0_MSK 0xffffffff
+#define NEQ_PKT_ID_31_0_I_MSK 0x00000000
+#define NEQ_PKT_ID_31_0_SFT 0
+#define NEQ_PKT_ID_31_0_HI 31
+#define NEQ_PKT_ID_31_0_SZ 32
+#define NEQ_PKT_ID_63_32_MSK 0xffffffff
+#define NEQ_PKT_ID_63_32_I_MSK 0x00000000
+#define NEQ_PKT_ID_63_32_SFT 0
+#define NEQ_PKT_ID_63_32_HI 31
+#define NEQ_PKT_ID_63_32_SZ 32
+#define NEQ_PKT_ID_95_64_MSK 0xffffffff
+#define NEQ_PKT_ID_95_64_I_MSK 0x00000000
+#define NEQ_PKT_ID_95_64_SFT 0
+#define NEQ_PKT_ID_95_64_HI 31
+#define NEQ_PKT_ID_95_64_SZ 32
+#define NEQ_PKT_ID_127_96_MSK 0xffffffff
+#define NEQ_PKT_ID_127_96_I_MSK 0x00000000
+#define NEQ_PKT_ID_127_96_SFT 0
+#define NEQ_PKT_ID_127_96_HI 31
+#define NEQ_PKT_ID_127_96_SZ 32
+#define ALC_NOCHG_ID_MSK 0x0000007f
+#define ALC_NOCHG_ID_I_MSK 0xffffff80
+#define ALC_NOCHG_ID_SFT 0
+#define ALC_NOCHG_ID_HI 6
+#define ALC_NOCHG_ID_SZ 7
+#define ALC_NOCHG_INT_MSK 0x00008000
+#define ALC_NOCHG_INT_I_MSK 0xffff7fff
+#define ALC_NOCHG_INT_SFT 15
+#define ALC_NOCHG_INT_HI 15
+#define ALC_NOCHG_INT_SZ 1
+#define NEQ_PKT_FLAG_MSK 0x00010000
+#define NEQ_PKT_FLAG_I_MSK 0xfffeffff
+#define NEQ_PKT_FLAG_SFT 16
+#define NEQ_PKT_FLAG_HI 16
+#define NEQ_PKT_FLAG_SZ 1
+#define NEQ_MB_FLAG_MSK 0x01000000
+#define NEQ_MB_FLAG_I_MSK 0xfeffffff
+#define NEQ_MB_FLAG_SFT 24
+#define NEQ_MB_FLAG_HI 24
+#define NEQ_MB_FLAG_SZ 1
+#define SRAM_TAG_0_MSK 0x0000ffff
+#define SRAM_TAG_0_I_MSK 0xffff0000
+#define SRAM_TAG_0_SFT 0
+#define SRAM_TAG_0_HI 15
+#define SRAM_TAG_0_SZ 16
+#define SRAM_TAG_1_MSK 0xffff0000
+#define SRAM_TAG_1_I_MSK 0x0000ffff
+#define SRAM_TAG_1_SFT 16
+#define SRAM_TAG_1_HI 31
+#define SRAM_TAG_1_SZ 16
+#define SRAM_TAG_2_MSK 0x0000ffff
+#define SRAM_TAG_2_I_MSK 0xffff0000
+#define SRAM_TAG_2_SFT 0
+#define SRAM_TAG_2_HI 15
+#define SRAM_TAG_2_SZ 16
+#define SRAM_TAG_3_MSK 0xffff0000
+#define SRAM_TAG_3_I_MSK 0x0000ffff
+#define SRAM_TAG_3_SFT 16
+#define SRAM_TAG_3_HI 31
+#define SRAM_TAG_3_SZ 16
+#define SRAM_TAG_4_MSK 0x0000ffff
+#define SRAM_TAG_4_I_MSK 0xffff0000
+#define SRAM_TAG_4_SFT 0
+#define SRAM_TAG_4_HI 15
+#define SRAM_TAG_4_SZ 16
+#define SRAM_TAG_5_MSK 0xffff0000
+#define SRAM_TAG_5_I_MSK 0x0000ffff
+#define SRAM_TAG_5_SFT 16
+#define SRAM_TAG_5_HI 31
+#define SRAM_TAG_5_SZ 16
+#define SRAM_TAG_6_MSK 0x0000ffff
+#define SRAM_TAG_6_I_MSK 0xffff0000
+#define SRAM_TAG_6_SFT 0
+#define SRAM_TAG_6_HI 15
+#define SRAM_TAG_6_SZ 16
+#define SRAM_TAG_7_MSK 0xffff0000
+#define SRAM_TAG_7_I_MSK 0x0000ffff
+#define SRAM_TAG_7_SFT 16
+#define SRAM_TAG_7_HI 31
+#define SRAM_TAG_7_SZ 16
+#define SRAM_TAG_8_MSK 0x0000ffff
+#define SRAM_TAG_8_I_MSK 0xffff0000
+#define SRAM_TAG_8_SFT 0
+#define SRAM_TAG_8_HI 15
+#define SRAM_TAG_8_SZ 16
+#define SRAM_TAG_9_MSK 0xffff0000
+#define SRAM_TAG_9_I_MSK 0x0000ffff
+#define SRAM_TAG_9_SFT 16
+#define SRAM_TAG_9_HI 31
+#define SRAM_TAG_9_SZ 16
+#define SRAM_TAG_10_MSK 0x0000ffff
+#define SRAM_TAG_10_I_MSK 0xffff0000
+#define SRAM_TAG_10_SFT 0
+#define SRAM_TAG_10_HI 15
+#define SRAM_TAG_10_SZ 16
+#define SRAM_TAG_11_MSK 0xffff0000
+#define SRAM_TAG_11_I_MSK 0x0000ffff
+#define SRAM_TAG_11_SFT 16
+#define SRAM_TAG_11_HI 31
+#define SRAM_TAG_11_SZ 16
+#define SRAM_TAG_12_MSK 0x0000ffff
+#define SRAM_TAG_12_I_MSK 0xffff0000
+#define SRAM_TAG_12_SFT 0
+#define SRAM_TAG_12_HI 15
+#define SRAM_TAG_12_SZ 16
+#define SRAM_TAG_13_MSK 0xffff0000
+#define SRAM_TAG_13_I_MSK 0x0000ffff
+#define SRAM_TAG_13_SFT 16
+#define SRAM_TAG_13_HI 31
+#define SRAM_TAG_13_SZ 16
+#define SRAM_TAG_14_MSK 0x0000ffff
+#define SRAM_TAG_14_I_MSK 0xffff0000
+#define SRAM_TAG_14_SFT 0
+#define SRAM_TAG_14_HI 15
+#define SRAM_TAG_14_SZ 16
+#define SRAM_TAG_15_MSK 0xffff0000
+#define SRAM_TAG_15_I_MSK 0x0000ffff
+#define SRAM_TAG_15_SFT 16
+#define SRAM_TAG_15_HI 31
+#define SRAM_TAG_15_SZ 16
diff --git a/drivers/net/wireless/ssv6x5x/include/ssv6200_common.h b/drivers/net/wireless/ssv6x5x/include/ssv6200_common.h
new file mode 100644
index 000000000..4386a5065
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/include/ssv6200_common.h
@@ -0,0 +1,188 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV6200_COMMON_H_
+#define _SSV6200_COMMON_H_
+#include <ssv6xxx_common.h>
+#define FW_VERSION_REG ADR_TX_SEG
+#define M_ENG_CPU 0x00
+#define M_ENG_HWHCI 0x01
+#define M_ENG_EMPTY 0x02
+#define M_ENG_ENCRYPT 0x03
+#define M_ENG_MACRX 0x04
+#define M_ENG_MIC 0x05
+#define M_ENG_TX_EDCA0 0x06
+#define M_ENG_TX_EDCA1 0x07
+#define M_ENG_TX_EDCA2 0x08
+#define M_ENG_TX_EDCA3 0x09
+#define M_ENG_TX_MNG 0x0A
+#define M_ENG_ENCRYPT_SEC 0x0B
+#define M_ENG_MIC_SEC 0x0C
+#define M_ENG_RESERVED_1 0x0D
+#define M_ENG_RESERVED_2 0x0E
+#define M_ENG_TRASH_CAN 0x0F
+#define M_ENG_MAX (M_ENG_TRASH_CAN+1)
+#define M_CPU_HWENG 0x00
+#define M_CPU_TXL34CS 0x01
+#define M_CPU_RXL34CS 0x02
+#define M_CPU_DEFRAG 0x03
+#define M_CPU_EDCATX 0x04
+#define M_CPU_RXDATA 0x05
+#define M_CPU_RXMGMT 0x06
+#define M_CPU_RXCTRL 0x07
+#define M_CPU_FRAG 0x08
+#define M_CPU_TXTPUT 0x09
+#ifndef ID_TRAP_SW_TXTPUT
+#define ID_TRAP_SW_TXTPUT 50
+#endif
+#define TXPB_OFFSET 80
+#define RXPB_OFFSET 80
+#define SSV6200_TX_PKT_RSVD_SETTING 0x3
+#define SSV6200_TX_PKT_RSVD SSV6200_TX_PKT_RSVD_SETTING*16
+#define SSV6200_ALLOC_RSVD TXPB_OFFSET+SSV6200_TX_PKT_RSVD
+#ifndef SSV_SUPPORT_HAL
+struct ssv6200_tx_desc {
+    u32 len:16;
+    u32 c_type:3;
+    u32 f80211:1;
+    u32 qos:1;
+    u32 ht:1;
+    u32 use_4addr:1;
+    u32 RSVD_0:3;
+    u32 bc_que:1;
+    u32 security:1;
+    u32 more_data:1;
+    u32 stype_b5b4:2;
+    u32 extra_info:1;
+    u32 fCmd;
+    u32 hdr_offset:8;
+    u32 frag:1;
+    u32 unicast:1;
+    u32 hdr_len:6;
+    u32 tx_report:1;
+    u32 tx_burst:1;
+    u32 ack_policy:2;
+    u32 aggregation:1;
+    u32 RSVD_1:3;
+    u32 do_rts_cts:2;
+    u32 reason:6;
+    u32 payload_offset:8;
+    u32 RSVD_4:7;
+    u32 RSVD_2:1;
+    u32 fCmdIdx:3;
+    u32 wsid:4;
+    u32 txq_idx:3;
+    u32 TxF_ID:6;
+    u32 rts_cts_nav:16;
+    u32 frame_consume_time:10;
+    u32 crate_idx:6;
+    u32 drate_idx:6;
+    u32 dl_length:12;
+    u32 RSVD_3:14;
+    u32 RESERVED[8];
+    struct fw_rc_retry_params rc_params[SSV62XX_TX_MAX_RATES];
+};
+struct ssv6200_rx_desc {
+    u32 len:16;
+    u32 c_type:3;
+    u32 f80211:1;
+    u32 qos:1;
+    u32 ht:1;
+    u32 use_4addr:1;
+    u32 l3cs_err:1;
+    u32 l4cs_err:1;
+    u32 align2:1;
+    u32 RSVD_0:2;
+    u32 psm:1;
+    u32 stype_b5b4:2;
+    u32 extra_info:1;
+    u32 edca0_used:4;
+    u32 edca1_used:5;
+    u32 edca2_used:5;
+    u32 edca3_used:5;
+    u32 mng_used:4;
+    u32 tx_page_used:9;
+    u32 hdr_offset:8;
+    u32 frag:1;
+    u32 unicast:1;
+    u32 hdr_len:6;
+    u32 RxResult:8;
+    u32 wildcard_bssid:1;
+    u32 RSVD_1:1;
+    u32 reason:6;
+    u32 payload_offset:8;
+    u32 tx_id_used:8;
+    u32 fCmdIdx:3;
+    u32 wsid:4;
+    u32 RSVD_3:3;
+    u32 rate_idx:6;
+};
+struct ssv6200_rxphy_info {
+    u32 len:16;
+    u32 rsvd0:16;
+    u32 mode:3;
+    u32 ch_bw:3;
+    u32 preamble:1;
+    u32 ht_short_gi:1;
+    u32 rate:7;
+    u32 rsvd1:1;
+    u32 smoothing:1;
+    u32 no_sounding:1;
+    u32 aggregate:1;
+    u32 stbc:2;
+    u32 fec:1;
+    u32 n_ess:2;
+    u32 rsvd2:8;
+    u32 l_length:12;
+    u32 l_rate:3;
+    u32 rsvd3:17;
+    u32 rsvd4;
+    u32 rpci:8;
+    u32 snr:8;
+    u32 service:16;
+};
+struct ssv6200_rxphy_info_padding {
+    u32 rpci:8;
+    u32 snr:8;
+    u32 RSVD:16;
+};
+struct ssv6200_txphy_info {
+    u32 rsvd[7];
+};
+#endif
+#define SSV_NUM_HW_STA 2
+typedef enum {
+    SSV6XXX_RC_COUNTER_CLEAR = 1,
+    SSV6XXX_RC_REPORT,
+} ssv6xxx_host_rate_control_event;
+struct ssv62xx_tx_rate {
+    s8 data_rate;
+    u8 count;
+} __attribute__((packed));
+struct ampdu_ba_notify_data {
+    u8 wsid;
+    struct ssv62xx_tx_rate tried_rates[SSV62XX_TX_MAX_RATES];
+    u16 seq_no[MAX_AGGR_NUM];
+} __attribute__((packed));
+struct firmware_rate_control_report_data {
+    u8 wsid;
+    struct ssv62xx_tx_rate rates[SSV62XX_TX_MAX_RATES];
+    u16 ampdu_len;
+    u16 ampdu_ack_len;
+    int ack_signal;
+} __attribute__((packed));
+#define RC_RETRY_PARAM_OFFSET ((sizeof(struct fw_rc_retry_params))*SSV62XX_TX_MAX_RATES)
+#define SSV_RC_RATE_MAX 39
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/include/ssv6200_configuration.h b/drivers/net/wireless/ssv6x5x/include/ssv6200_configuration.h
new file mode 100644
index 000000000..18e549582
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/include/ssv6200_configuration.h
@@ -0,0 +1,374 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef SSV_SUPPORT_HAL
+ssv_cabrio_reg phy_setting[]= {
+    {0xce0071bc, 0x565B565B},
+    {0xce000008, 0x0000006a},
+    {0xce00000c, 0x00000064},
+    {0xce000010, 0x00007FFF},
+    {0xce000014, 0x00000003},
+    {0xce000018, 0x0055003C},
+    {0xce00001c, 0x00000064},
+    {0xce000020, 0x20000000},
+    {0xce00002c, 0x00000000},
+    {0xce000030, 0x80046072},
+    {0xce000034, 0x1f300f6f},
+    {0xce000038, 0x660F36D0},
+    {0xce00003c, 0x106C0004},
+    {0xce000040, 0x01601400},
+    {0xce000044, 0x00600008},
+    {0xce000048, 0xff000160},
+    {0xce00004c, 0x00000840},
+    {0xce000060, 0x01000405},
+    {0xce000064, 0x06090813},
+    {0xce000068, 0x12070000},
+    {0xce00006c, 0x01000405},
+    {0xce000070, 0x06090813},
+    {0xce000074, 0x12010000},
+    {0xce000078, 0x00000000},
+    {0xce00007c, 0x10110003},
+    {0xce000080, 0x0110000F},
+    {0xce000084, 0x00000000},
+    {0xce000088, 0x00000000},
+    {0xce000094, 0x01012425},
+    {0xce000098, 0x01010101},
+    {0xce00009c, 0x00000011},
+    {0xce0000a0, 0x1fff0000},
+    {0xce0000a4, 0x1fff0000},
+    {0xce0000a8, 0x1fff0000},
+    {0xce0000ac, 0x1fff0000},
+    {0xce0000b8, 0x0000fe3e},
+    {0xce0000fc, 0xffffffff},
+    {0xce000108, 0x0ead04f5},
+    {0xce00010c, 0x0fd60080},
+    {0xce000110, 0x00000009},
+    {0xce0010a4, 0x0000002c},
+    {0xce0010b4, 0x00003001},
+    {0xce0010d4, 0x00000001},
+    {0xce002000, 0x00000044},
+    {0xce002004, 0x00040000},
+    {0xce002008, 0x20300050},
+    {0xce00200c, 0x00003467},
+    {0xce002010, 0x00430000},
+    {0xce002014, 0x20304015},
+    {0xce002018, 0x00390005},
+    {0xce00201c, 0x05555555},
+    {0xce002020, 0x00570057},
+    {0xce002024, 0x00570057},
+    {0xce002028, 0x00236700},
+    {0xce00202c, 0x000d1746},
+    {0xce002030, 0x05061787},
+    {0xce002034, 0x07800000},
+    {0xce00209c, 0x00900008},
+    {0xce0020a0, 0x00000000},
+    {0xce0023f8, 0x00000000},
+    {0xce0023fc, 0x00000001},
+    {0xce0030a4, 0x00001901},
+    {0xce0030b8, 0x5d08908e},
+    {0xce004000, 0x00000044},
+    {0xce004004, 0x00750075},
+    {0xce004008, 0x00000075},
+    {0xce00400c, 0x10000075},
+    {0xce004010, 0x3F384905},
+    {0xce004014, 0x40182000},
+    {0xce004018, 0x20600000},
+    {0xce00401c, 0x0C010120},
+    {0xce004020, 0x50505050},
+    {0xce004024, 0x50000000},
+    {0xce004028, 0x50505050},
+    {0xce00402c, 0x506070A0},
+    {0xce004030, 0xF0000000},
+    {0xce004034, 0x00002424},
+    {0xce004038, 0x00001420},
+    {0xce00409c, 0x0000300A},
+    {0xce0040c0, 0x20000280},
+    {0xce0040c4, 0x30023002},
+    {0xce0040c8, 0x0000003a},
+    {0xce004130, 0x40000000},
+    {0xce004164, 0x009C007E},
+    {0xce004180, 0x00044400},
+    {0xce004188, 0x82000000},
+    {0xce004190, 0x00000000},
+    {0xce004194, 0xffffffff},
+    {0xce004380, 0x00700010},
+    {0xce004384, 0x00007575},
+    {0xce004388, 0x0001fe3e},
+    {0xce00438c, 0x0000fe3e},
+    {0xce0043f8, 0x00000001},
+    {0xce007000, 0x00000000},
+    {0xce007004, 0x00008000},
+    {0xce007008, 0x00000000},
+    {0xce00700c, 0x00000000},
+    {0xce007010, 0x00000000},
+    {0xce007014, 0x00000000},
+    {0xce007018, 0x00000000},
+    {0xce00701c, 0x00000000},
+    {0xce007020, 0x00000000},
+    {0xce007024, 0x00000000},
+    {0xce007028, 0x00000000},
+    {0xce00702c, 0x00000000},
+    {0xce007030, 0x00000000},
+    {0xce007034, 0x00000000},
+    {0xce007038, 0x00000000},
+    {0xce00703c, 0x00000000},
+    {0xce007040, 0x02000200},
+    {0xce007048, 0x00000000},
+    {0xce00704c, 0x00000000},
+    {0xce007050, 0x00000000},
+    {0xce007054, 0x00000000},
+    {0xce007058, 0x000028ff},
+    {0xce00705c, 0x00000000},
+    {0xce007060, 0x00000000},
+    {0xce007064, 0x00000000},
+    {0xce007068, 0x00000000},
+    {0xce00706c, 0x00000202},
+    {0xce007070, 0x80ffc200},
+    {0xce007074, 0x00000000},
+    {0xce007078, 0x00000000},
+    {0xce00707c, 0x00000000},
+    {0xce007080, 0x00000000},
+    {0xce007084, 0x00000000},
+    {0xce007088, 0x00000000},
+    {0xce00708c, 0x00000000},
+    {0xce007090, 0x00000000},
+    {0xce007094, 0x00000000},
+    {0xce007098, 0x00000000},
+    {0xce00709c, 0x00000000},
+    {0xce0070a0, 0x00000000},
+    {0xce0070a4, 0x00000000},
+    {0xce0070a8, 0x00000000},
+    {0xce0070ac, 0x00000000},
+    {0xce0070b0, 0x00000000},
+    {0xce0070b4, 0x00000000},
+    {0xce0070b8, 0x00000000},
+    {0xce0070bc, 0x00000000},
+    {0xce0070c0, 0x00000000},
+    {0xce0070c4, 0x00000000},
+    {0xce0070c8, 0x00000000},
+    {0xce0070cc, 0x00000000},
+    {0xce0070d0, 0x00000000},
+    {0xce0070d4, 0x00000000},
+    {0xce0070d8, 0x00000000},
+    {0xce0070dc, 0x00000000},
+    {0xce0070e0, 0x00000000},
+    {0xce0070e4, 0x00000000},
+    {0xce0070e8, 0x00000000},
+    {0xce0070ec, 0x00000000},
+    {0xce0070f0, 0x00000000},
+    {0xce0070f4, 0x00000000},
+    {0xce0070f8, 0x00000000},
+    {0xce0070fc, 0x00000000},
+    {0xce007100, 0x00000000},
+    {0xce007104, 0x00000000},
+    {0xce007108, 0x00000000},
+    {0xce00710c, 0x00000000},
+    {0xce007110, 0x00000000},
+    {0xce007114, 0x00000000},
+    {0xce007118, 0x00000000},
+    {0xce00711c, 0x00000000},
+    {0xce007120, 0x02000200},
+    {0xce007124, 0x02000200},
+    {0xce007128, 0x02000200},
+    {0xce00712c, 0x02000200},
+    {0xce007130, 0x02000200},
+    {0xce007134, 0x02000200},
+    {0xce007138, 0x02000200},
+    {0xce00713c, 0x02000200},
+    {0xce007140, 0x02000200},
+    {0xce007144, 0x02000200},
+    {0xce007148, 0x02000200},
+    {0xce00714c, 0x02000200},
+    {0xce007150, 0x02000200},
+    {0xce007154, 0x02000200},
+    {0xce007158, 0x00000000},
+    {0xce00715c, 0x00000000},
+    {0xce007160, 0x00000000},
+    {0xce007164, 0x00000000},
+    {0xce007168, 0x00000000},
+    {0xce00716c, 0x00000000},
+    {0xce007170, 0x00000000},
+    {0xce007174, 0x00000000},
+    {0xce007178, 0x00000000},
+    {0xce00717c, 0x00000000},
+    {0xce007180, 0x00000000},
+    {0xce007184, 0x00000000},
+    {0xce007188, 0x00000000},
+    {0xce00718c, 0x00000000},
+    {0xce007190, 0x00000000},
+    {0xce007194, 0x00000000},
+    {0xce007198, 0x00000000},
+    {0xce00719c, 0x00000000},
+    {0xce0071a0, 0x00000000},
+    {0xce0071a4, 0x00000000},
+    {0xce0071a8, 0x00000000},
+    {0xce0071ac, 0x00000000},
+    {0xce0071b0, 0x00000000},
+    {0xce0071b4, 0x00000100},
+    {0xce0071b8, 0x00000000},
+    {0xce0071c0, 0x00000000},
+    {0xce0071c4, 0x00000000},
+    {0xce0071c8, 0x00000000},
+    {0xce0071cc, 0x00000000},
+    {0xce0071d0, 0x00000000},
+    {0xce0071d4, 0x00000000},
+    {0xce0071d8, 0x00000000},
+    {0xce0071dc, 0x00000000},
+    {0xce0071e0, 0x00000000},
+    {0xce0071e4, 0x00000000},
+    {0xce0071e8, 0x00000000},
+    {0xce0071ec, 0x00000000},
+    {0xce0071f0, 0x00000000},
+    {0xce0071f4, 0x00000000},
+    {0xce0071f8, 0x00000000},
+    {0xce0071fc, 0x00000000},
+#ifdef CONFIG_SSV_CABRIO_E
+    {0xce0043fc, 0x000104e5},
+    {0xce007044, 0x00028080},
+    {0xce000000, 0x80000016},
+#endif
+#ifdef CONFIG_SSV_CABRIO_A
+    {0xce0043fc, 0x000004e1},
+    {0xce007044, 0x00038080},
+    {0xce000000, 0x0000001e},
+#endif
+};
+static const u32 wifi_tx_gain[]= {
+    0x79807980,
+    0x72797279,
+    0x6C726C72,
+    0x666C666C,
+    0x60666066,
+    0x5B605B60,
+    0x565B565B,
+    0x51565156,
+    0x4C514C51,
+    0x484C484C,
+    0x44484448,
+    0x40444044,
+    0x3C403C40,
+    0x3A3D3A3D,
+    0x36393639,
+};
+#ifndef CONFIG_SSV_CABRIO_A
+static ssv_cabrio_reg asic_rf_setting[]= {
+    {0xCE010038, 0x0003E07C},
+    {0xCE010060, 0x00406000},
+    {0xCE01009C, 0x00000024},
+    {0xCE0100A0, 0x00EC4CC5},
+    {0xCE010000, 0x40002000},
+    {0xCE010004, 0x00020FC0},
+    {0xCE010008, 0x000DF69B},
+    {0xCE010014, 0x3D3E84FE},
+    {0xCE010018, 0x01457D79},
+    {0xCE01001C, 0x000103A7},
+    {0xCE010020, 0x000103A6},
+    {0xCE01002C, 0x00032CA8},
+    {0xCE010048, 0xFCCCCF27},
+    {0xCE010050, 0x00444000},
+    {0xCE01000C, 0x151558C5},
+    {0xCE010010, 0x01011A88},
+    {0xCE010024, 0x00012001},
+    {0xCE010028, 0x00036000},
+    {0xCE010030, 0x20EA0224},
+    {0xCE010034, 0x44000755},
+    {0xCE01003C, 0x55D89D8A},
+    {0xCE010040, 0x005508BB},
+    {0xCE010044, 0x07C08BFF},
+    {0xCE01004C, 0x07700830},
+    {0xCE010054, 0x00007FF4},
+    {0xCE010058, 0x0000000E},
+    {0xCE01005C, 0x00088018},
+    {0xCE010064, 0x08820820},
+    {0xCE010068, 0x00820820},
+    {0xCE01006C, 0x00820820},
+    {0xCE010070, 0x00820820},
+    {0xCE010074, 0x00820820},
+    {0xCE010078, 0x00820820},
+    {0xCE01007C, 0x00820820},
+    {0xCE010080, 0x00820820},
+    {0xCE010084, 0x00004080},
+    {0xCE010088, 0x200800FE},
+    {0xCE01008C, 0xAAAAAAAA},
+    {0xCE010090, 0xAAAAAAAA},
+    {0xCE010094, 0x0000A487},
+    {0xCE010098, 0x0000070E},
+    {0xCE0100A4, 0x00000F43},
+    {0xCE0100A8, 0x00098900},
+    {0xCE0100AC, 0x00000000},
+    {0xC00003AC, 0x00000000},
+    {0xC00003B0, 0x00000000},
+    {0xC00003B4, 0x00000000},
+    {0xC00003BC, 0x00000000},
+    {0xC0001D00, 0x5E000040},
+    {0xC0001D04, 0x015D015D},
+    {0xC0001D08, 0x00000001},
+    {0xC0001D0C, 0x55550000},
+    {0xC0001D20, 0x7FFF0000},
+    {0xC0001D24, 0x00000003},
+    {0xC0001D28, 0x00000000},
+    {0xC0001D2C, 0x00000000},
+};
+#endif
+#ifdef CONFIG_SSV_CABRIO_A
+static ssv_cabrio_reg fpga_rf_setting[]= {
+    {0xcb110000,0x5F00EFCE},
+    {0xcb110004,0x00001FC0},
+    {0xcb110008,0x1C96CA3A},
+    {0xcb11000c,0x15155A74},
+    {0xcb110010,0x01011A88},
+    {0xcb110014,0x3CBF703C},
+    {0xcb110018,0x00057579},
+    {0xcb11001c,0x000103A7},
+    {0xcb110020,0x000103A6},
+    {0xcb110024,0x00012001},
+    {0xcb110028,0x00036000},
+    {0xcb11002c,0x00000CA8},
+    {0xcb110030,0x002A0224},
+    {0xcb110034,0x00001E55},
+    {0xcb110038,0x00006C7C},
+    {0xcb11003c,0x55666666},
+    {0xcb110040,0x005508F8},
+    {0xcb110044,0x07C08BFF},
+    {0xcb110048,0xF1111A27},
+    {0xcb11004c,0x2773F53C},
+    {0xcb110050,0x00000A7C},
+    {0xcb110054,0x00087FF8},
+    {0xcb110058,0x00103014},
+    {0xcb11005c,0x0000848A},
+    {0xcb110060,0x00406030},
+    {0xcb110064,0x00820820},
+    {0xcb110068,0x00820820},
+    {0xcb11006c,0x00820820},
+    {0xcb110070,0x00820820},
+    {0xcb110074,0x00820820},
+    {0xcb110078,0x00820820},
+    {0xcb11007c,0x00820820},
+    {0xcb110080,0x00820820},
+    {0xcb110084,0x00004080},
+    {0xcb110088,0x00003EAA},
+    {0xcb11008c,0x5E00FFEB},
+    {0xcb110090,0xAAAAAAAA},
+    {0xcb110094,0x0000243F},
+    {0xcb110098,0x00018B10},
+    {0xcb120080,0x00000000},
+    {0xcb120084,0x00000000},
+    {0xcb120088,0x00000000},
+    {0xcb120090,0x00000813},
+    {0xcb120094,0x00000000},
+    {0xcb1203f8,0xFF000000},
+};
+#endif
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/include/ssv6200_reg.h b/drivers/net/wireless/ssv6x5x/include/ssv6200_reg.h
new file mode 100644
index 000000000..42775fce1
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/include/ssv6200_reg.h
@@ -0,0 +1,9693 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define SYS_REG_BASE 0xc0000000
+#define WBOOT_REG_BASE 0xc0000100
+#define TU0_US_REG_BASE 0xc0000200
+#define TU1_US_REG_BASE 0xc0000210
+#define TU2_US_REG_BASE 0xc0000220
+#define TU3_US_REG_BASE 0xc0000230
+#define TM0_MS_REG_BASE 0xc0000240
+#define TM1_MS_REG_BASE 0xc0000250
+#define TM2_MS_REG_BASE 0xc0000260
+#define TM3_MS_REG_BASE 0xc0000270
+#define MCU_WDT_REG_BASE 0xc0000280
+#define SYS_WDT_REG_BASE 0xc0000284
+#define GPIO_REG_BASE 0xc0000300
+#define SD_REG_BASE 0xc0000800
+#define SPI_REG_BASE 0xc0000a00
+#define CSR_I2C_MST_BASE 0xc0000b00
+#define UART_REG_BASE 0xc0000c00
+#define DAT_UART_REG_BASE 0xc0000d00
+#define INT_REG_BASE 0xc0000e00
+#define DBG_SPI_REG_BASE 0xc0000f00
+#define FLASH_SPI_REG_BASE 0xc0001000
+#define DMA_REG_BASE 0xc0001c00
+#define CSR_PMU_BASE 0xc0001d00
+#define CSR_RTC_BASE 0xc0001d20
+#define RTC_RAM_BASE 0xc0001d80
+#define D2_DMA_REG_BASE 0xc0001e00
+#define HCI_REG_BASE 0xc1000000
+#define CO_REG_BASE 0xc2000000
+#define EFS_REG_BASE 0xc2000100
+#define SMS4_REG_BASE 0xc3000000
+#define MRX_REG_BASE 0xc6000000
+#define AMPDU_REG_BASE 0xc6001000
+#define MT_REG_CSR_BASE 0xc6002000
+#define TXQ0_MT_Q_REG_CSR_BASE 0xc6002100
+#define TXQ1_MT_Q_REG_CSR_BASE 0xc6002200
+#define TXQ2_MT_Q_REG_CSR_BASE 0xc6002300
+#define TXQ3_MT_Q_REG_CSR_BASE 0xc6002400
+#define TXQ4_MT_Q_REG_CSR_BASE 0xc6002500
+#define HIF_INFO_BASE 0xca000000
+#define PHY_RATE_INFO_BASE 0xca000200
+#define MAC_GLB_SET_BASE 0xca000300
+#define BTCX_REG_BASE 0xca000400
+#define MIB_REG_BASE 0xca000800
+#define CBR_A_REG_BASE 0xcb000000
+#define MB_REG_BASE 0xcd000000
+#define ID_MNG_REG_BASE 0xcd010000
+#define CSR_PHY_BASE 0xce000000
+#define CSR_RF_BASE 0xce010000
+#define MMU_REG_BASE 0xcf000000
+#define SYS_REG_BANK_SIZE 0x000000b4
+#define WBOOT_REG_BANK_SIZE 0x0000000c
+#define TU0_US_REG_BANK_SIZE 0x00000010
+#define TU1_US_REG_BANK_SIZE 0x00000010
+#define TU2_US_REG_BANK_SIZE 0x00000010
+#define TU3_US_REG_BANK_SIZE 0x00000010
+#define TM0_MS_REG_BANK_SIZE 0x00000010
+#define TM1_MS_REG_BANK_SIZE 0x00000010
+#define TM2_MS_REG_BANK_SIZE 0x00000010
+#define TM3_MS_REG_BANK_SIZE 0x00000010
+#define MCU_WDT_REG_BANK_SIZE 0x00000004
+#define SYS_WDT_REG_BANK_SIZE 0x00000004
+#define GPIO_REG_BANK_SIZE 0x000000d4
+#define SD_REG_BANK_SIZE 0x00000180
+#define SPI_REG_BANK_SIZE 0x00000040
+#define CSR_I2C_MST_BANK_SIZE 0x00000018
+#define UART_REG_BANK_SIZE 0x00000028
+#define DAT_UART_REG_BANK_SIZE 0x00000028
+#define INT_REG_BANK_SIZE 0x0000004c
+#define DBG_SPI_REG_BANK_SIZE 0x00000040
+#define FLASH_SPI_REG_BANK_SIZE 0x0000002c
+#define DMA_REG_BANK_SIZE 0x00000014
+#define CSR_PMU_BANK_SIZE 0x00000100
+#define CSR_RTC_BANK_SIZE 0x000000e0
+#define RTC_RAM_BANK_SIZE 0x00000080
+#define D2_DMA_REG_BANK_SIZE 0x00000014
+#define HCI_REG_BANK_SIZE 0x000000cc
+#define CO_REG_BANK_SIZE 0x000000ac
+#define EFS_REG_BANK_SIZE 0x0000006c
+#define SMS4_REG_BANK_SIZE 0x00000070
+#define MRX_REG_BANK_SIZE 0x00000198
+#define AMPDU_REG_BANK_SIZE 0x00000014
+#define MT_REG_CSR_BANK_SIZE 0x00000100
+#define TXQ0_MT_Q_REG_CSR_BANK_SIZE 0x0000001c
+#define TXQ1_MT_Q_REG_CSR_BANK_SIZE 0x0000001c
+#define TXQ2_MT_Q_REG_CSR_BANK_SIZE 0x0000001c
+#define TXQ3_MT_Q_REG_CSR_BANK_SIZE 0x0000001c
+#define TXQ4_MT_Q_REG_CSR_BANK_SIZE 0x0000001c
+#define HIF_INFO_BANK_SIZE 0x0000009c
+#define PHY_RATE_INFO_BANK_SIZE 0x000000b8
+#define MAC_GLB_SET_BANK_SIZE 0x0000003c
+#define BTCX_REG_BANK_SIZE 0x0000000c
+#define MIB_REG_BANK_SIZE 0x00000480
+#define CBR_A_REG_BANK_SIZE 0x001203fc
+#define MB_REG_BANK_SIZE 0x000000a0
+#define ID_MNG_REG_BANK_SIZE 0x00000084
+#define CSR_PHY_BANK_SIZE 0x000071c0
+#define CSR_RF_BANK_SIZE 0x000000b0
+#define MMU_REG_BANK_SIZE 0x000000c0
+#define ADR_BRG_SW_RST (SYS_REG_BASE+0x00000000)
+#define ADR_BOOT (SYS_REG_BASE+0x00000004)
+#define ADR_CHIP_ID_0 (SYS_REG_BASE+0x00000008)
+#define ADR_CHIP_ID_1 (SYS_REG_BASE+0x0000000c)
+#define ADR_CHIP_ID_2 (SYS_REG_BASE+0x00000010)
+#define ADR_CHIP_ID_3 (SYS_REG_BASE+0x00000014)
+#define ADR_CLOCK_SELECTION (SYS_REG_BASE+0x00000018)
+#define ADR_PLATFORM_CLOCK_ENABLE (SYS_REG_BASE+0x0000001c)
+#define ADR_SYS_CSR_CLOCK_ENABLE (SYS_REG_BASE+0x00000020)
+#define ADR_MCU_DBG_SEL (SYS_REG_BASE+0x00000024)
+#define ADR_MCU_DBG_DATA (SYS_REG_BASE+0x00000028)
+#define ADR_AHB_BRG_STATUS (SYS_REG_BASE+0x0000002c)
+#define ADR_BIST_BIST_CTRL (SYS_REG_BASE+0x00000030)
+#define ADR_BIST_MODE_REG_IN (SYS_REG_BASE+0x00000034)
+#define ADR_BIST_MODE_REG_OUT (SYS_REG_BASE+0x00000038)
+#define ADR_BIST_MONITOR_BUS_LSB (SYS_REG_BASE+0x0000003c)
+#define ADR_BIST_MONITOR_BUS_MSB (SYS_REG_BASE+0x00000040)
+#define ADR_TB_ADR_SEL (SYS_REG_BASE+0x00000044)
+#define ADR_TB_RDATA (SYS_REG_BASE+0x00000048)
+#define ADR_UART_W2B (SYS_REG_BASE+0x0000004c)
+#define ADR_AHB_ILL_ADDR (SYS_REG_BASE+0x00000050)
+#define ADR_AHB_FEN_ADDR (SYS_REG_BASE+0x00000054)
+#define ADR_AHB_ILLFEN_STATUS (SYS_REG_BASE+0x00000058)
+#define ADR_PWM_A (SYS_REG_BASE+0x00000080)
+#define ADR_PWM_B (SYS_REG_BASE+0x00000084)
+#define ADR_HBUSREQ_LOCK (SYS_REG_BASE+0x00000090)
+#define ADR_HBURST_LOCK (SYS_REG_BASE+0x00000094)
+#define ADR_PRESCALER_USTIMER (SYS_REG_BASE+0x000000a0)
+#define ADR_BIST_MODE_REG_IN_MMU (SYS_REG_BASE+0x000000a4)
+#define ADR_BIST_MODE_REG_OUT_MMU (SYS_REG_BASE+0x000000a8)
+#define ADR_BIST_MONITOR_BUS_MMU (SYS_REG_BASE+0x000000ac)
+#define ADR_TEST_MODE (SYS_REG_BASE+0x000000b0)
+#define ADR_BOOT_INFO (WBOOT_REG_BASE+0x00000000)
+#define ADR_SD_INIT_CFG (WBOOT_REG_BASE+0x00000004)
+#define ADR_SPARE_UART_INFO (WBOOT_REG_BASE+0x00000008)
+#define ADR_TU0_MICROSECOND_TIMER (TU0_US_REG_BASE+0x00000000)
+#define ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE (TU0_US_REG_BASE+0x00000004)
+#define ADR_TU0_DUMMY_BIT_0 (TU0_US_REG_BASE+0x00000008)
+#define ADR_TU0_DUMMY_BIT_1 (TU0_US_REG_BASE+0x0000000c)
+#define ADR_TU1_MICROSECOND_TIMER (TU1_US_REG_BASE+0x00000000)
+#define ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE (TU1_US_REG_BASE+0x00000004)
+#define ADR_TU1_DUMMY_BIT_0 (TU1_US_REG_BASE+0x00000008)
+#define ADR_TU1_DUMMY_BIT_1 (TU1_US_REG_BASE+0x0000000c)
+#define ADR_TU2_MICROSECOND_TIMER (TU2_US_REG_BASE+0x00000000)
+#define ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE (TU2_US_REG_BASE+0x00000004)
+#define ADR_TU2_DUMMY_BIT_0 (TU2_US_REG_BASE+0x00000008)
+#define ADR_TU2_DUMMY_BIT_1 (TU2_US_REG_BASE+0x0000000c)
+#define ADR_TU3_MICROSECOND_TIMER (TU3_US_REG_BASE+0x00000000)
+#define ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE (TU3_US_REG_BASE+0x00000004)
+#define ADR_TU3_DUMMY_BIT_0 (TU3_US_REG_BASE+0x00000008)
+#define ADR_TU3_DUMMY_BIT_1 (TU3_US_REG_BASE+0x0000000c)
+#define ADR_TM0_MILISECOND_TIMER (TM0_MS_REG_BASE+0x00000000)
+#define ADR_TM0_CURRENT_MILISECOND_TIME_VALUE (TM0_MS_REG_BASE+0x00000004)
+#define ADR_TM0_DUMMY_BIT_0 (TM0_MS_REG_BASE+0x00000008)
+#define ADR_TM0_DUMMY_BIT_1 (TM0_MS_REG_BASE+0x0000000c)
+#define ADR_TM1_MILISECOND_TIMER (TM1_MS_REG_BASE+0x00000000)
+#define ADR_TM1_CURRENT_MILISECOND_TIME_VALUE (TM1_MS_REG_BASE+0x00000004)
+#define ADR_TM1_DUMMY_BIT_0 (TM1_MS_REG_BASE+0x00000008)
+#define ADR_TM1_DUMMY_BIT_1 (TM1_MS_REG_BASE+0x0000000c)
+#define ADR_TM2_MILISECOND_TIMER (TM2_MS_REG_BASE+0x00000000)
+#define ADR_TM2_CURRENT_MILISECOND_TIME_VALUE (TM2_MS_REG_BASE+0x00000004)
+#define ADR_TM2_DUMMY_BIT_0 (TM2_MS_REG_BASE+0x00000008)
+#define ADR_TM2_DUMMY_BIT_1 (TM2_MS_REG_BASE+0x0000000c)
+#define ADR_TM3_MILISECOND_TIMER (TM3_MS_REG_BASE+0x00000000)
+#define ADR_TM3_CURRENT_MILISECOND_TIME_VALUE (TM3_MS_REG_BASE+0x00000004)
+#define ADR_TM3_DUMMY_BIT_0 (TM3_MS_REG_BASE+0x00000008)
+#define ADR_TM3_DUMMY_BIT_1 (TM3_MS_REG_BASE+0x0000000c)
+#define ADR_MCU_WDOG_REG (MCU_WDT_REG_BASE+0x00000000)
+#define ADR_SYS_WDOG_REG (SYS_WDT_REG_BASE+0x00000000)
+#define ADR_PAD6 (GPIO_REG_BASE+0x00000000)
+#define ADR_PAD7 (GPIO_REG_BASE+0x00000004)
+#define ADR_PAD8 (GPIO_REG_BASE+0x00000008)
+#define ADR_PAD9 (GPIO_REG_BASE+0x0000000c)
+#define ADR_PAD11 (GPIO_REG_BASE+0x00000010)
+#define ADR_PAD15 (GPIO_REG_BASE+0x00000014)
+#define ADR_PAD16 (GPIO_REG_BASE+0x00000018)
+#define ADR_PAD17 (GPIO_REG_BASE+0x0000001c)
+#define ADR_PAD18 (GPIO_REG_BASE+0x00000020)
+#define ADR_PAD19 (GPIO_REG_BASE+0x00000024)
+#define ADR_PAD20 (GPIO_REG_BASE+0x00000028)
+#define ADR_PAD21 (GPIO_REG_BASE+0x0000002c)
+#define ADR_PAD22 (GPIO_REG_BASE+0x00000030)
+#define ADR_PAD24 (GPIO_REG_BASE+0x00000034)
+#define ADR_PAD25 (GPIO_REG_BASE+0x00000038)
+#define ADR_PAD27 (GPIO_REG_BASE+0x0000003c)
+#define ADR_PAD28 (GPIO_REG_BASE+0x00000040)
+#define ADR_PAD29 (GPIO_REG_BASE+0x00000044)
+#define ADR_PAD30 (GPIO_REG_BASE+0x00000048)
+#define ADR_PAD31 (GPIO_REG_BASE+0x0000004c)
+#define ADR_PAD32 (GPIO_REG_BASE+0x00000050)
+#define ADR_PAD33 (GPIO_REG_BASE+0x00000054)
+#define ADR_PAD34 (GPIO_REG_BASE+0x00000058)
+#define ADR_PAD42 (GPIO_REG_BASE+0x0000005c)
+#define ADR_PAD43 (GPIO_REG_BASE+0x00000060)
+#define ADR_PAD44 (GPIO_REG_BASE+0x00000064)
+#define ADR_PAD45 (GPIO_REG_BASE+0x00000068)
+#define ADR_PAD46 (GPIO_REG_BASE+0x0000006c)
+#define ADR_PAD47 (GPIO_REG_BASE+0x00000070)
+#define ADR_PAD48 (GPIO_REG_BASE+0x00000074)
+#define ADR_PAD49 (GPIO_REG_BASE+0x00000078)
+#define ADR_PAD50 (GPIO_REG_BASE+0x0000007c)
+#define ADR_PAD51 (GPIO_REG_BASE+0x00000080)
+#define ADR_PAD52 (GPIO_REG_BASE+0x00000084)
+#define ADR_PAD53 (GPIO_REG_BASE+0x00000088)
+#define ADR_PAD54 (GPIO_REG_BASE+0x0000008c)
+#define ADR_PAD56 (GPIO_REG_BASE+0x00000090)
+#define ADR_PAD57 (GPIO_REG_BASE+0x00000094)
+#define ADR_PAD58 (GPIO_REG_BASE+0x00000098)
+#define ADR_PAD59 (GPIO_REG_BASE+0x0000009c)
+#define ADR_PAD60 (GPIO_REG_BASE+0x000000a0)
+#define ADR_PAD61 (GPIO_REG_BASE+0x000000a4)
+#define ADR_PAD62 (GPIO_REG_BASE+0x000000a8)
+#define ADR_PAD64 (GPIO_REG_BASE+0x000000ac)
+#define ADR_PAD65 (GPIO_REG_BASE+0x000000b0)
+#define ADR_PAD66 (GPIO_REG_BASE+0x000000b4)
+#define ADR_PAD68 (GPIO_REG_BASE+0x000000b8)
+#define ADR_PAD67 (GPIO_REG_BASE+0x000000bc)
+#define ADR_PAD69 (GPIO_REG_BASE+0x000000c0)
+#define ADR_PAD70 (GPIO_REG_BASE+0x000000c4)
+#define ADR_PAD231 (GPIO_REG_BASE+0x000000c8)
+#define ADR_PIN_SEL_0 (GPIO_REG_BASE+0x000000cc)
+#define ADR_PIN_SEL_1 (GPIO_REG_BASE+0x000000d0)
+#define ADR_IO_PORT_REG (SD_REG_BASE+0x00000000)
+#define ADR_INT_MASK_REG (SD_REG_BASE+0x00000004)
+#define ADR_INT_STATUS_REG (SD_REG_BASE+0x00000008)
+#define ADR_FN1_STATUS_REG (SD_REG_BASE+0x0000000c)
+#define ADR_CARD_PKT_STATUS_TEST (SD_REG_BASE+0x00000010)
+#define ADR_SYSTEM_INFORMATION_REG (SD_REG_BASE+0x0000001c)
+#define ADR_CARD_RCA_REG (SD_REG_BASE+0x00000020)
+#define ADR_SDIO_FIFO_WR_THLD_REG (SD_REG_BASE+0x00000024)
+#define ADR_SDIO_FIFO_WR_LIMIT_REG (SD_REG_BASE+0x00000028)
+#define ADR_SDIO_TX_DATA_BATCH_SIZE_REG (SD_REG_BASE+0x0000002c)
+#define ADR_SDIO_THLD_FOR_CMD53RD_REG (SD_REG_BASE+0x00000030)
+#define ADR_SDIO_RX_DATA_BATCH_SIZE_REG (SD_REG_BASE+0x00000034)
+#define ADR_SDIO_LOG_START_END_DATA_REG (SD_REG_BASE+0x00000038)
+#define ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG (SD_REG_BASE+0x00000040)
+#define ADR_SDIO_LAST_CMD_INDEX_CRC_REG (SD_REG_BASE+0x00000044)
+#define ADR_SDIO_LAST_CMD_ARG_REG (SD_REG_BASE+0x00000048)
+#define ADR_SDIO_BUS_STATE_DEBUG_MONITOR (SD_REG_BASE+0x0000004c)
+#define ADR_SDIO_CARD_STATUS_REG (SD_REG_BASE+0x00000050)
+#define ADR_R5_RESP_FLAG_OUT_TIMING (SD_REG_BASE+0x00000054)
+#define ADR_CMD52_DATA_FOR_LAST_TIME (SD_REG_BASE+0x0000005c)
+#define ADR_FN1_DMA_START_ADDR_REG (SD_REG_BASE+0x00000060)
+#define ADR_FN1_INT_CTRL_RESET (SD_REG_BASE+0x00000064)
+#define ADR_IO_REG_PORT_REG (SD_REG_BASE+0x00000070)
+#define ADR_SDIO_FIFO_ERROR_CNT (SD_REG_BASE+0x0000007c)
+#define ADR_SDIO_CRC7_CRC16_ERROR_REG (SD_REG_BASE+0x00000080)
+#define ADR_SDIO_BLOCK_CNT_INFO (SD_REG_BASE+0x00000084)
+#define ADR_RX_DATA_CMD52_ABORT_COUNT (SD_REG_BASE+0x0000008c)
+#define ADR_FIFO_PTR_READ_BLOCK_CNT (SD_REG_BASE+0x00000090)
+#define ADR_TX_TIME_OUT_READ_CTRL (SD_REG_BASE+0x00000094)
+#define ADR_SDIO_TX_ALLOC_REG (SD_REG_BASE+0x00000098)
+#define ADR_SDIO_TX_INFORM (SD_REG_BASE+0x0000009c)
+#define ADR_F1_BLOCK_SIZE_0_REG (SD_REG_BASE+0x000000a0)
+#define ADR_SDIO_COMMAND_LOG_DATA_31_0 (SD_REG_BASE+0x000000b0)
+#define ADR_SDIO_COMMAND_LOG_DATA_63_32 (SD_REG_BASE+0x000000b4)
+#define ADR_SYSTEM_INFORMATION_REGISTER (SD_REG_BASE+0x000000bc)
+#define ADR_CCCR_00H_REG (SD_REG_BASE+0x000000c0)
+#define ADR_CCCR_04H_REG (SD_REG_BASE+0x000000c4)
+#define ADR_CCCR_08H_REG (SD_REG_BASE+0x000000c8)
+#define ADR_CCCR_13H_REG (SD_REG_BASE+0x000000d0)
+#define ADR_FBR_100H_REG (SD_REG_BASE+0x000000e0)
+#define ADR_FBR_109H_REG (SD_REG_BASE+0x000000e8)
+#define ADR_F0_CIS_CONTENT_REG_0 (SD_REG_BASE+0x00000100)
+#define ADR_F0_CIS_CONTENT_REG_1 (SD_REG_BASE+0x00000104)
+#define ADR_F0_CIS_CONTENT_REG_2 (SD_REG_BASE+0x00000108)
+#define ADR_F0_CIS_CONTENT_REG_3 (SD_REG_BASE+0x0000010c)
+#define ADR_F0_CIS_CONTENT_REG_4 (SD_REG_BASE+0x00000110)
+#define ADR_F0_CIS_CONTENT_REG_5 (SD_REG_BASE+0x00000114)
+#define ADR_F0_CIS_CONTENT_REG_6 (SD_REG_BASE+0x00000118)
+#define ADR_F0_CIS_CONTENT_REG_7 (SD_REG_BASE+0x0000011c)
+#define ADR_F0_CIS_CONTENT_REG_8 (SD_REG_BASE+0x00000120)
+#define ADR_F0_CIS_CONTENT_REG_9 (SD_REG_BASE+0x00000124)
+#define ADR_F0_CIS_CONTENT_REG_10 (SD_REG_BASE+0x00000128)
+#define ADR_F0_CIS_CONTENT_REG_11 (SD_REG_BASE+0x0000012c)
+#define ADR_F0_CIS_CONTENT_REG_12 (SD_REG_BASE+0x00000130)
+#define ADR_F0_CIS_CONTENT_REG_13 (SD_REG_BASE+0x00000134)
+#define ADR_F0_CIS_CONTENT_REG_14 (SD_REG_BASE+0x00000138)
+#define ADR_F0_CIS_CONTENT_REG_15 (SD_REG_BASE+0x0000013c)
+#define ADR_F1_CIS_CONTENT_REG_0 (SD_REG_BASE+0x00000140)
+#define ADR_F1_CIS_CONTENT_REG_1 (SD_REG_BASE+0x00000144)
+#define ADR_F1_CIS_CONTENT_REG_2 (SD_REG_BASE+0x00000148)
+#define ADR_F1_CIS_CONTENT_REG_3 (SD_REG_BASE+0x0000014c)
+#define ADR_F1_CIS_CONTENT_REG_4 (SD_REG_BASE+0x00000150)
+#define ADR_F1_CIS_CONTENT_REG_5 (SD_REG_BASE+0x00000154)
+#define ADR_F1_CIS_CONTENT_REG_6 (SD_REG_BASE+0x00000158)
+#define ADR_F1_CIS_CONTENT_REG_7 (SD_REG_BASE+0x0000015c)
+#define ADR_F1_CIS_CONTENT_REG_8 (SD_REG_BASE+0x00000160)
+#define ADR_F1_CIS_CONTENT_REG_9 (SD_REG_BASE+0x00000164)
+#define ADR_F1_CIS_CONTENT_REG_10 (SD_REG_BASE+0x00000168)
+#define ADR_F1_CIS_CONTENT_REG_11 (SD_REG_BASE+0x0000016c)
+#define ADR_F1_CIS_CONTENT_REG_12 (SD_REG_BASE+0x00000170)
+#define ADR_F1_CIS_CONTENT_REG_13 (SD_REG_BASE+0x00000174)
+#define ADR_F1_CIS_CONTENT_REG_14 (SD_REG_BASE+0x00000178)
+#define ADR_F1_CIS_CONTENT_REG_15 (SD_REG_BASE+0x0000017c)
+#define ADR_SPI_MODE (SPI_REG_BASE+0x00000000)
+#define ADR_RX_QUOTA (SPI_REG_BASE+0x00000004)
+#define ADR_CONDITION_NUMBER (SPI_REG_BASE+0x00000008)
+#define ADR_HOST_PATH (SPI_REG_BASE+0x0000000c)
+#define ADR_TX_SEG (SPI_REG_BASE+0x00000010)
+#define ADR_DEBUG_BURST_MODE (SPI_REG_BASE+0x00000014)
+#define ADR_SPI_TO_PHY_PARAM1 (SPI_REG_BASE+0x00000018)
+#define ADR_SPI_TO_PHY_PARAM2 (SPI_REG_BASE+0x0000001c)
+#define ADR_SPI_STS (SPI_REG_BASE+0x00000020)
+#define ADR_TX_ALLOC_SET (SPI_REG_BASE+0x00000024)
+#define ADR_TX_ALLOC (SPI_REG_BASE+0x00000028)
+#define ADR_DBG_CNT (SPI_REG_BASE+0x0000002c)
+#define ADR_DBG_CNT2 (SPI_REG_BASE+0x00000030)
+#define ADR_DBG_CNT3 (SPI_REG_BASE+0x00000034)
+#define ADR_DBG_CNT4 (SPI_REG_BASE+0x00000038)
+#define ADR_INT_TAG (SPI_REG_BASE+0x0000003c)
+#define ADR_I2CM_EN (CSR_I2C_MST_BASE+0x00000000)
+#define ADR_I2CM_DEV_A (CSR_I2C_MST_BASE+0x00000004)
+#define ADR_I2CM_LEN (CSR_I2C_MST_BASE+0x00000008)
+#define ADR_I2CM_WDAT (CSR_I2C_MST_BASE+0x0000000c)
+#define ADR_I2CM_RDAT (CSR_I2C_MST_BASE+0x00000010)
+#define ADR_I2CM_EN_2 (CSR_I2C_MST_BASE+0x00000014)
+#define ADR_UART_DATA (UART_REG_BASE+0x00000000)
+#define ADR_UART_IER (UART_REG_BASE+0x00000004)
+#define ADR_UART_FCR (UART_REG_BASE+0x00000008)
+#define ADR_UART_LCR (UART_REG_BASE+0x0000000c)
+#define ADR_UART_MCR (UART_REG_BASE+0x00000010)
+#define ADR_UART_LSR (UART_REG_BASE+0x00000014)
+#define ADR_UART_MSR (UART_REG_BASE+0x00000018)
+#define ADR_UART_SPR (UART_REG_BASE+0x0000001c)
+#define ADR_UART_RTHR (UART_REG_BASE+0x00000020)
+#define ADR_UART_ISR (UART_REG_BASE+0x00000024)
+#define ADR_DAT_UART_DATA (DAT_UART_REG_BASE+0x00000000)
+#define ADR_DAT_UART_IER (DAT_UART_REG_BASE+0x00000004)
+#define ADR_DAT_UART_FCR (DAT_UART_REG_BASE+0x00000008)
+#define ADR_DAT_UART_LCR (DAT_UART_REG_BASE+0x0000000c)
+#define ADR_DAT_UART_MCR (DAT_UART_REG_BASE+0x00000010)
+#define ADR_DAT_UART_LSR (DAT_UART_REG_BASE+0x00000014)
+#define ADR_DAT_UART_MSR (DAT_UART_REG_BASE+0x00000018)
+#define ADR_DAT_UART_SPR (DAT_UART_REG_BASE+0x0000001c)
+#define ADR_DAT_UART_RTHR (DAT_UART_REG_BASE+0x00000020)
+#define ADR_DAT_UART_ISR (DAT_UART_REG_BASE+0x00000024)
+#define ADR_INT_MASK (INT_REG_BASE+0x00000000)
+#define ADR_INT_MODE (INT_REG_BASE+0x00000004)
+#define ADR_INT_IRQ_STS (INT_REG_BASE+0x00000008)
+#define ADR_INT_FIQ_STS (INT_REG_BASE+0x0000000c)
+#define ADR_INT_IRQ_RAW (INT_REG_BASE+0x00000010)
+#define ADR_INT_FIQ_RAW (INT_REG_BASE+0x00000014)
+#define ADR_INT_PERI_MASK (INT_REG_BASE+0x00000018)
+#define ADR_INT_PERI_STS (INT_REG_BASE+0x0000001c)
+#define ADR_INT_PERI_RAW (INT_REG_BASE+0x00000020)
+#define ADR_INT_GPI_CFG (INT_REG_BASE+0x00000024)
+#define ADR_SYS_INT_FOR_HOST (INT_REG_BASE+0x00000028)
+#define ADR_SPI_IPC (INT_REG_BASE+0x00000034)
+#define ADR_SDIO_IPC (INT_REG_BASE+0x00000038)
+#define ADR_SDIO_MASK (INT_REG_BASE+0x0000003c)
+#define ADR_SDIO_IRQ_STS (INT_REG_BASE+0x00000040)
+#define ADR_SD_PERI_MASK (INT_REG_BASE+0x00000044)
+#define ADR_SD_PERI_STS (INT_REG_BASE+0x00000048)
+#define ADR_DBG_SPI_MODE (DBG_SPI_REG_BASE+0x00000000)
+#define ADR_DBG_RX_QUOTA (DBG_SPI_REG_BASE+0x00000004)
+#define ADR_DBG_CONDITION_NUMBER (DBG_SPI_REG_BASE+0x00000008)
+#define ADR_DBG_HOST_PATH (DBG_SPI_REG_BASE+0x0000000c)
+#define ADR_DBG_TX_SEG (DBG_SPI_REG_BASE+0x00000010)
+#define ADR_DBG_DEBUG_BURST_MODE (DBG_SPI_REG_BASE+0x00000014)
+#define ADR_DBG_SPI_TO_PHY_PARAM1 (DBG_SPI_REG_BASE+0x00000018)
+#define ADR_DBG_SPI_TO_PHY_PARAM2 (DBG_SPI_REG_BASE+0x0000001c)
+#define ADR_DBG_SPI_STS (DBG_SPI_REG_BASE+0x00000020)
+#define ADR_DBG_TX_ALLOC_SET (DBG_SPI_REG_BASE+0x00000024)
+#define ADR_DBG_TX_ALLOC (DBG_SPI_REG_BASE+0x00000028)
+#define ADR_DBG_DBG_CNT (DBG_SPI_REG_BASE+0x0000002c)
+#define ADR_DBG_DBG_CNT2 (DBG_SPI_REG_BASE+0x00000030)
+#define ADR_DBG_DBG_CNT3 (DBG_SPI_REG_BASE+0x00000034)
+#define ADR_DBG_DBG_CNT4 (DBG_SPI_REG_BASE+0x00000038)
+#define ADR_DBG_INT_TAG (DBG_SPI_REG_BASE+0x0000003c)
+#define ADR_BOOT_ADDR (FLASH_SPI_REG_BASE+0x00000000)
+#define ADR_VERIFY_DATA (FLASH_SPI_REG_BASE+0x00000004)
+#define ADR_FLASH_ADDR (FLASH_SPI_REG_BASE+0x00000008)
+#define ADR_SRAM_ADDR (FLASH_SPI_REG_BASE+0x0000000c)
+#define ADR_LEN (FLASH_SPI_REG_BASE+0x00000010)
+#define ADR_SPI_PARAM (FLASH_SPI_REG_BASE+0x00000014)
+#define ADR_SPI_PARAM2 (FLASH_SPI_REG_BASE+0x00000018)
+#define ADR_CHECK_SUM_RESULT (FLASH_SPI_REG_BASE+0x0000001c)
+#define ADR_CHECK_SUM_IN_FILE (FLASH_SPI_REG_BASE+0x00000020)
+#define ADR_COMMAND_LEN (FLASH_SPI_REG_BASE+0x00000024)
+#define ADR_COMMAND_ADDR (FLASH_SPI_REG_BASE+0x00000028)
+#define ADR_DMA_ADR_SRC (DMA_REG_BASE+0x00000000)
+#define ADR_DMA_ADR_DST (DMA_REG_BASE+0x00000004)
+#define ADR_DMA_CTRL (DMA_REG_BASE+0x00000008)
+#define ADR_DMA_INT (DMA_REG_BASE+0x0000000c)
+#define ADR_DMA_FILL_CONST (DMA_REG_BASE+0x00000010)
+#define ADR_PMU_0 (CSR_PMU_BASE+0x00000000)
+#define ADR_PMU_1 (CSR_PMU_BASE+0x00000004)
+#define ADR_PMU_2 (CSR_PMU_BASE+0x00000008)
+#define ADR_PMU_3 (CSR_PMU_BASE+0x0000000c)
+#define ADR_RTC_1 (CSR_RTC_BASE+0x00000000)
+#define ADR_RTC_2 (CSR_RTC_BASE+0x00000004)
+#define ADR_RTC_3W (CSR_RTC_BASE+0x00000008)
+#define ADR_RTC_3R (CSR_RTC_BASE+0x00000008)
+#define ADR_RTC_4 (CSR_RTC_BASE+0x0000000c)
+#define ADR_RTC_RAM (RTC_RAM_BASE+0x00000000)
+#define ADR_D2_DMA_ADR_SRC (D2_DMA_REG_BASE+0x00000000)
+#define ADR_D2_DMA_ADR_DST (D2_DMA_REG_BASE+0x00000004)
+#define ADR_D2_DMA_CTRL (D2_DMA_REG_BASE+0x00000008)
+#define ADR_D2_DMA_INT (D2_DMA_REG_BASE+0x0000000c)
+#define ADR_D2_DMA_FILL_CONST (D2_DMA_REG_BASE+0x00000010)
+#define ADR_CONTROL (HCI_REG_BASE+0x00000000)
+#define ADR_SDIO_WAKE_MODE (HCI_REG_BASE+0x00000004)
+#define ADR_TX_FLOW_0 (HCI_REG_BASE+0x00000008)
+#define ADR_TX_FLOW_1 (HCI_REG_BASE+0x0000000c)
+#define ADR_THREASHOLD (HCI_REG_BASE+0x00000018)
+#define ADR_TXFID_INCREASE (HCI_REG_BASE+0x00000020)
+#define ADR_GLOBAL_SEQUENCE (HCI_REG_BASE+0x00000028)
+#define ADR_HCI_TX_RX_INFO_SIZE (HCI_REG_BASE+0x00000030)
+#define ADR_HCI_TX_INFO_CLEAR (HCI_REG_BASE+0x00000034)
+#define ADR_TX_ETHER_TYPE_0 (HCI_REG_BASE+0x00000050)
+#define ADR_TX_ETHER_TYPE_1 (HCI_REG_BASE+0x00000054)
+#define ADR_RX_ETHER_TYPE_0 (HCI_REG_BASE+0x00000060)
+#define ADR_RX_ETHER_TYPE_1 (HCI_REG_BASE+0x00000064)
+#define ADR_PACKET_COUNTER_INFO_0 (HCI_REG_BASE+0x00000070)
+#define ADR_PACKET_COUNTER_INFO_1 (HCI_REG_BASE+0x00000074)
+#define ADR_PACKET_COUNTER_INFO_2 (HCI_REG_BASE+0x00000078)
+#define ADR_PACKET_COUNTER_INFO_3 (HCI_REG_BASE+0x0000007c)
+#define ADR_PACKET_COUNTER_INFO_4 (HCI_REG_BASE+0x00000080)
+#define ADR_PACKET_COUNTER_INFO_5 (HCI_REG_BASE+0x00000084)
+#define ADR_PACKET_COUNTER_INFO_6 (HCI_REG_BASE+0x00000088)
+#define ADR_PACKET_COUNTER_INFO_7 (HCI_REG_BASE+0x0000008c)
+#define ADR_SDIO_TX_RX_FAIL_COUNTER_0 (HCI_REG_BASE+0x00000090)
+#define ADR_SDIO_TX_RX_FAIL_COUNTER_1 (HCI_REG_BASE+0x00000094)
+#define ADR_HCI_STATE_DEBUG_MODE_0 (HCI_REG_BASE+0x000000a0)
+#define ADR_HCI_STATE_DEBUG_MODE_1 (HCI_REG_BASE+0x000000a4)
+#define ADR_HCI_STATE_DEBUG_MODE_2 (HCI_REG_BASE+0x000000a8)
+#define ADR_HCI_STATE_DEBUG_MODE_3 (HCI_REG_BASE+0x000000ac)
+#define ADR_HCI_STATE_DEBUG_MODE_4 (HCI_REG_BASE+0x000000b0)
+#define ADR_HCI_STATE_DEBUG_MODE_5 (HCI_REG_BASE+0x000000b4)
+#define ADR_HCI_STATE_DEBUG_MODE_6 (HCI_REG_BASE+0x000000b8)
+#define ADR_HCI_STATE_DEBUG_MODE_7 (HCI_REG_BASE+0x000000bc)
+#define ADR_HCI_STATE_DEBUG_MODE_8 (HCI_REG_BASE+0x000000c0)
+#define ADR_HCI_STATE_DEBUG_MODE_9 (HCI_REG_BASE+0x000000c4)
+#define ADR_HCI_STATE_DEBUG_MODE_10 (HCI_REG_BASE+0x000000c8)
+#define ADR_CS_START_ADDR (CO_REG_BASE+0x00000000)
+#define ADR_CS_ADD_LEN (CO_REG_BASE+0x00000004)
+#define ADR_CS_CMD (CO_REG_BASE+0x00000008)
+#define ADR_CS_INI_BUF (CO_REG_BASE+0x0000000c)
+#define ADR_CS_PSEUDO_BUF (CO_REG_BASE+0x00000010)
+#define ADR_CS_CHECK_SUM (CO_REG_BASE+0x00000014)
+#define ADR_RAND_EN (CO_REG_BASE+0x00000018)
+#define ADR_RAND_NUM (CO_REG_BASE+0x0000001c)
+#define ADR_MUL_OP1 (CO_REG_BASE+0x00000060)
+#define ADR_MUL_OP2 (CO_REG_BASE+0x00000064)
+#define ADR_MUL_ANS0 (CO_REG_BASE+0x00000068)
+#define ADR_MUL_ANS1 (CO_REG_BASE+0x0000006c)
+#define ADR_DMA_RDATA (CO_REG_BASE+0x00000070)
+#define ADR_DMA_WDATA (CO_REG_BASE+0x00000074)
+#define ADR_DMA_LEN (CO_REG_BASE+0x00000078)
+#define ADR_DMA_CLR (CO_REG_BASE+0x0000007c)
+#define ADR_NAV_DATA (CO_REG_BASE+0x00000080)
+#define ADR_CO_NAV (CO_REG_BASE+0x00000084)
+#define ADR_SHA_DST_ADDR (CO_REG_BASE+0x000000a0)
+#define ADR_SHA_SRC_ADDR (CO_REG_BASE+0x000000a4)
+#define ADR_SHA_SETTING (CO_REG_BASE+0x000000a8)
+#define ADR_EFUSE_CLK_FREQ (EFS_REG_BASE+0x00000000)
+#define ADR_EFUSE_LDO_TIME (EFS_REG_BASE+0x00000004)
+#define ADR_EFUSE_AHB_RDATA_0 (EFS_REG_BASE+0x00000008)
+#define ADR_EFUSE_WDATA_0 (EFS_REG_BASE+0x00000008)
+#define ADR_EFUSE_AHB_RDATA_1 (EFS_REG_BASE+0x0000000c)
+#define ADR_EFUSE_WDATA_1 (EFS_REG_BASE+0x0000000c)
+#define ADR_EFUSE_AHB_RDATA_2 (EFS_REG_BASE+0x00000010)
+#define ADR_EFUSE_WDATA_2 (EFS_REG_BASE+0x00000010)
+#define ADR_EFUSE_AHB_RDATA_3 (EFS_REG_BASE+0x00000014)
+#define ADR_EFUSE_WDATA_3 (EFS_REG_BASE+0x00000014)
+#define ADR_EFUSE_AHB_RDATA_4 (EFS_REG_BASE+0x00000018)
+#define ADR_EFUSE_WDATA_4 (EFS_REG_BASE+0x00000018)
+#define ADR_EFUSE_AHB_RDATA_5 (EFS_REG_BASE+0x0000001c)
+#define ADR_EFUSE_WDATA_5 (EFS_REG_BASE+0x0000001c)
+#define ADR_EFUSE_AHB_RDATA_6 (EFS_REG_BASE+0x00000020)
+#define ADR_EFUSE_WDATA_6 (EFS_REG_BASE+0x00000020)
+#define ADR_EFUSE_AHB_RDATA_7 (EFS_REG_BASE+0x00000024)
+#define ADR_EFUSE_WDATA_7 (EFS_REG_BASE+0x00000024)
+#define ADR_EFUSE_SPI_RD0_EN (EFS_REG_BASE+0x00000028)
+#define ADR_EFUSE_SPI_RD1_EN (EFS_REG_BASE+0x0000002c)
+#define ADR_EFUSE_SPI_RD2_EN (EFS_REG_BASE+0x00000030)
+#define ADR_EFUSE_SPI_RD3_EN (EFS_REG_BASE+0x00000034)
+#define ADR_EFUSE_SPI_RD4_EN (EFS_REG_BASE+0x00000038)
+#define ADR_EFUSE_SPI_RD5_EN (EFS_REG_BASE+0x0000003c)
+#define ADR_EFUSE_SPI_RD6_EN (EFS_REG_BASE+0x00000040)
+#define ADR_EFUSE_SPI_RD7_EN (EFS_REG_BASE+0x00000044)
+#define ADR_EFUSE_SPI_BUSY (EFS_REG_BASE+0x00000048)
+#define ADR_EFUSE_SPI_RDATA_0 (EFS_REG_BASE+0x0000004c)
+#define ADR_EFUSE_SPI_RDATA_1 (EFS_REG_BASE+0x00000050)
+#define ADR_EFUSE_SPI_RDATA_2 (EFS_REG_BASE+0x00000054)
+#define ADR_EFUSE_SPI_RDATA_3 (EFS_REG_BASE+0x00000058)
+#define ADR_EFUSE_SPI_RDATA_4 (EFS_REG_BASE+0x0000005c)
+#define ADR_EFUSE_SPI_RDATA_5 (EFS_REG_BASE+0x00000060)
+#define ADR_EFUSE_SPI_RDATA_6 (EFS_REG_BASE+0x00000064)
+#define ADR_EFUSE_SPI_RDATA_7 (EFS_REG_BASE+0x00000068)
+#define ADR_SMS4_CFG1 (SMS4_REG_BASE+0x00000000)
+#define ADR_SMS4_CFG2 (SMS4_REG_BASE+0x00000004)
+#define ADR_SMS4_MODE1 (SMS4_REG_BASE+0x00000008)
+#define ADR_SMS4_TRIG (SMS4_REG_BASE+0x00000010)
+#define ADR_SMS4_STATUS1 (SMS4_REG_BASE+0x00000014)
+#define ADR_SMS4_STATUS2 (SMS4_REG_BASE+0x00000018)
+#define ADR_SMS4_DATA_IN0 (SMS4_REG_BASE+0x00000020)
+#define ADR_SMS4_DATA_IN1 (SMS4_REG_BASE+0x00000024)
+#define ADR_SMS4_DATA_IN2 (SMS4_REG_BASE+0x00000028)
+#define ADR_SMS4_DATA_IN3 (SMS4_REG_BASE+0x0000002c)
+#define ADR_SMS4_DATA_OUT0 (SMS4_REG_BASE+0x00000030)
+#define ADR_SMS4_DATA_OUT1 (SMS4_REG_BASE+0x00000034)
+#define ADR_SMS4_DATA_OUT2 (SMS4_REG_BASE+0x00000038)
+#define ADR_SMS4_DATA_OUT3 (SMS4_REG_BASE+0x0000003c)
+#define ADR_SMS4_KEY_0 (SMS4_REG_BASE+0x00000040)
+#define ADR_SMS4_KEY_1 (SMS4_REG_BASE+0x00000044)
+#define ADR_SMS4_KEY_2 (SMS4_REG_BASE+0x00000048)
+#define ADR_SMS4_KEY_3 (SMS4_REG_BASE+0x0000004c)
+#define ADR_SMS4_MODE_IV0 (SMS4_REG_BASE+0x00000050)
+#define ADR_SMS4_MODE_IV1 (SMS4_REG_BASE+0x00000054)
+#define ADR_SMS4_MODE_IV2 (SMS4_REG_BASE+0x00000058)
+#define ADR_SMS4_MODE_IV3 (SMS4_REG_BASE+0x0000005c)
+#define ADR_SMS4_OFB_ENC0 (SMS4_REG_BASE+0x00000060)
+#define ADR_SMS4_OFB_ENC1 (SMS4_REG_BASE+0x00000064)
+#define ADR_SMS4_OFB_ENC2 (SMS4_REG_BASE+0x00000068)
+#define ADR_SMS4_OFB_ENC3 (SMS4_REG_BASE+0x0000006c)
+#define ADR_MRX_MCAST_TB0_0 (MRX_REG_BASE+0x00000000)
+#define ADR_MRX_MCAST_TB0_1 (MRX_REG_BASE+0x00000004)
+#define ADR_MRX_MCAST_MK0_0 (MRX_REG_BASE+0x00000008)
+#define ADR_MRX_MCAST_MK0_1 (MRX_REG_BASE+0x0000000c)
+#define ADR_MRX_MCAST_CTRL0 (MRX_REG_BASE+0x00000010)
+#define ADR_MRX_MCAST_TB1_0 (MRX_REG_BASE+0x00000014)
+#define ADR_MRX_MCAST_TB1_1 (MRX_REG_BASE+0x00000018)
+#define ADR_MRX_MCAST_MK1_0 (MRX_REG_BASE+0x0000001c)
+#define ADR_MRX_MCAST_MK1_1 (MRX_REG_BASE+0x00000020)
+#define ADR_MRX_MCAST_CTRL1 (MRX_REG_BASE+0x00000024)
+#define ADR_MRX_MCAST_TB2_0 (MRX_REG_BASE+0x00000028)
+#define ADR_MRX_MCAST_TB2_1 (MRX_REG_BASE+0x0000002c)
+#define ADR_MRX_MCAST_MK2_0 (MRX_REG_BASE+0x00000030)
+#define ADR_MRX_MCAST_MK2_1 (MRX_REG_BASE+0x00000034)
+#define ADR_MRX_MCAST_CTRL2 (MRX_REG_BASE+0x00000038)
+#define ADR_MRX_MCAST_TB3_0 (MRX_REG_BASE+0x0000003c)
+#define ADR_MRX_MCAST_TB3_1 (MRX_REG_BASE+0x00000040)
+#define ADR_MRX_MCAST_MK3_0 (MRX_REG_BASE+0x00000044)
+#define ADR_MRX_MCAST_MK3_1 (MRX_REG_BASE+0x00000048)
+#define ADR_MRX_MCAST_CTRL3 (MRX_REG_BASE+0x0000004c)
+#define ADR_MRX_PHY_INFO (MRX_REG_BASE+0x00000050)
+#define ADR_MRX_BA_DBG (MRX_REG_BASE+0x00000054)
+#define ADR_MRX_FLT_TB0 (MRX_REG_BASE+0x00000070)
+#define ADR_MRX_FLT_TB1 (MRX_REG_BASE+0x00000074)
+#define ADR_MRX_FLT_TB2 (MRX_REG_BASE+0x00000078)
+#define ADR_MRX_FLT_TB3 (MRX_REG_BASE+0x0000007c)
+#define ADR_MRX_FLT_TB4 (MRX_REG_BASE+0x00000080)
+#define ADR_MRX_FLT_TB5 (MRX_REG_BASE+0x00000084)
+#define ADR_MRX_FLT_TB6 (MRX_REG_BASE+0x00000088)
+#define ADR_MRX_FLT_TB7 (MRX_REG_BASE+0x0000008c)
+#define ADR_MRX_FLT_TB8 (MRX_REG_BASE+0x00000090)
+#define ADR_MRX_FLT_TB9 (MRX_REG_BASE+0x00000094)
+#define ADR_MRX_FLT_TB10 (MRX_REG_BASE+0x00000098)
+#define ADR_MRX_FLT_TB11 (MRX_REG_BASE+0x0000009c)
+#define ADR_MRX_FLT_TB12 (MRX_REG_BASE+0x000000a0)
+#define ADR_MRX_FLT_TB13 (MRX_REG_BASE+0x000000a4)
+#define ADR_MRX_FLT_TB14 (MRX_REG_BASE+0x000000a8)
+#define ADR_MRX_FLT_TB15 (MRX_REG_BASE+0x000000ac)
+#define ADR_MRX_FLT_EN0 (MRX_REG_BASE+0x000000b0)
+#define ADR_MRX_FLT_EN1 (MRX_REG_BASE+0x000000b4)
+#define ADR_MRX_FLT_EN2 (MRX_REG_BASE+0x000000b8)
+#define ADR_MRX_FLT_EN3 (MRX_REG_BASE+0x000000bc)
+#define ADR_MRX_FLT_EN4 (MRX_REG_BASE+0x000000c0)
+#define ADR_MRX_FLT_EN5 (MRX_REG_BASE+0x000000c4)
+#define ADR_MRX_FLT_EN6 (MRX_REG_BASE+0x000000c8)
+#define ADR_MRX_FLT_EN7 (MRX_REG_BASE+0x000000cc)
+#define ADR_MRX_FLT_EN8 (MRX_REG_BASE+0x000000d0)
+#define ADR_MRX_LEN_FLT (MRX_REG_BASE+0x000000d4)
+#define ADR_RX_FLOW_DATA (MRX_REG_BASE+0x000000e0)
+#define ADR_RX_FLOW_MNG (MRX_REG_BASE+0x000000e4)
+#define ADR_RX_FLOW_CTRL (MRX_REG_BASE+0x000000e8)
+#define ADR_RX_TIME_STAMP_CFG (MRX_REG_BASE+0x000000ec)
+#define ADR_DBG_FF_FULL (MRX_REG_BASE+0x000000f0)
+#define ADR_DBG_WFF_FULL (MRX_REG_BASE+0x000000f4)
+#define ADR_DBG_MB_FULL (MRX_REG_BASE+0x000000f8)
+#define ADR_BA_CTRL (MRX_REG_BASE+0x00000100)
+#define ADR_BA_TA_0 (MRX_REG_BASE+0x00000104)
+#define ADR_BA_TA_1 (MRX_REG_BASE+0x00000108)
+#define ADR_BA_TID (MRX_REG_BASE+0x0000010c)
+#define ADR_BA_ST_SEQ (MRX_REG_BASE+0x00000110)
+#define ADR_BA_SB0 (MRX_REG_BASE+0x00000114)
+#define ADR_BA_SB1 (MRX_REG_BASE+0x00000118)
+#define ADR_MRX_WATCH_DOG (MRX_REG_BASE+0x0000011c)
+#define ADR_ACK_GEN_EN (MRX_REG_BASE+0x00000120)
+#define ADR_ACK_GEN_PARA (MRX_REG_BASE+0x00000124)
+#define ADR_ACK_GEN_RA_0 (MRX_REG_BASE+0x00000128)
+#define ADR_ACK_GEN_RA_1 (MRX_REG_BASE+0x0000012c)
+#define ADR_MIB_LEN_FAIL (MRX_REG_BASE+0x00000130)
+#define ADR_TRAP_HW_ID (MRX_REG_BASE+0x00000134)
+#define ADR_ID_IN_USE (MRX_REG_BASE+0x00000138)
+#define ADR_MRX_ERR (MRX_REG_BASE+0x0000013c)
+#define ADR_WSID0_TID0_RX_SEQ (MRX_REG_BASE+0x00000140)
+#define ADR_WSID0_TID1_RX_SEQ (MRX_REG_BASE+0x00000144)
+#define ADR_WSID0_TID2_RX_SEQ (MRX_REG_BASE+0x00000148)
+#define ADR_WSID0_TID3_RX_SEQ (MRX_REG_BASE+0x0000014c)
+#define ADR_WSID0_TID4_RX_SEQ (MRX_REG_BASE+0x00000150)
+#define ADR_WSID0_TID5_RX_SEQ (MRX_REG_BASE+0x00000154)
+#define ADR_WSID0_TID6_RX_SEQ (MRX_REG_BASE+0x00000158)
+#define ADR_WSID0_TID7_RX_SEQ (MRX_REG_BASE+0x0000015c)
+#define ADR_WSID1_TID0_RX_SEQ (MRX_REG_BASE+0x00000170)
+#define ADR_WSID1_TID1_RX_SEQ (MRX_REG_BASE+0x00000174)
+#define ADR_WSID1_TID2_RX_SEQ (MRX_REG_BASE+0x00000178)
+#define ADR_WSID1_TID3_RX_SEQ (MRX_REG_BASE+0x0000017c)
+#define ADR_WSID1_TID4_RX_SEQ (MRX_REG_BASE+0x00000180)
+#define ADR_WSID1_TID5_RX_SEQ (MRX_REG_BASE+0x00000184)
+#define ADR_WSID1_TID6_RX_SEQ (MRX_REG_BASE+0x00000188)
+#define ADR_WSID1_TID7_RX_SEQ (MRX_REG_BASE+0x0000018c)
+#define ADR_HDR_ADDR_SEL (MRX_REG_BASE+0x00000190)
+#define ADR_FRAME_TYPE_CNTR_SET (MRX_REG_BASE+0x00000194)
+#define ADR_PHY_INFO (AMPDU_REG_BASE+0x00000000)
+#define ADR_AMPDU_SIG (AMPDU_REG_BASE+0x00000004)
+#define ADR_MIB_AMPDU (AMPDU_REG_BASE+0x00000008)
+#define ADR_LEN_FLT (AMPDU_REG_BASE+0x0000000c)
+#define ADR_MIB_DELIMITER (AMPDU_REG_BASE+0x00000010)
+#define ADR_MTX_INT_STS (MT_REG_CSR_BASE+0x00000000)
+#define ADR_MTX_INT_EN (MT_REG_CSR_BASE+0x00000004)
+#define ADR_MTX_MISC_EN (MT_REG_CSR_BASE+0x00000008)
+#define ADR_MTX_EDCCA_TOUT (MT_REG_CSR_BASE+0x00000010)
+#define ADR_MTX_BCN_INT_STS (MT_REG_CSR_BASE+0x000000a0)
+#define ADR_MTX_BCN_EN_INT (MT_REG_CSR_BASE+0x000000a4)
+#define ADR_MTX_BCN_EN_MISC (MT_REG_CSR_BASE+0x000000a8)
+#define ADR_MTX_BCN_MISC (MT_REG_CSR_BASE+0x000000ac)
+#define ADR_MTX_BCN_PRD (MT_REG_CSR_BASE+0x000000b0)
+#define ADR_MTX_BCN_TSF_L (MT_REG_CSR_BASE+0x000000b4)
+#define ADR_MTX_BCN_TSF_U (MT_REG_CSR_BASE+0x000000b8)
+#define ADR_MTX_BCN_CFG0 (MT_REG_CSR_BASE+0x000000bc)
+#define ADR_MTX_BCN_CFG1 (MT_REG_CSR_BASE+0x000000c0)
+#define ADR_MTX_STATUS (MT_REG_CSR_BASE+0x000000cc)
+#define ADR_MTX_DBG_CTRL (MT_REG_CSR_BASE+0x000000d0)
+#define ADR_MTX_DBG_DAT0 (MT_REG_CSR_BASE+0x000000d4)
+#define ADR_MTX_DBG_DAT1 (MT_REG_CSR_BASE+0x000000d8)
+#define ADR_MTX_DBG_DAT2 (MT_REG_CSR_BASE+0x000000dc)
+#define ADR_MTX_DUR_TOUT (MT_REG_CSR_BASE+0x000000e0)
+#define ADR_MTX_DUR_IFS (MT_REG_CSR_BASE+0x000000e4)
+#define ADR_MTX_DUR_SIFS_G (MT_REG_CSR_BASE+0x000000e8)
+#define ADR_MTX_DBG_DAT3 (MT_REG_CSR_BASE+0x000000ec)
+#define ADR_MTX_NAV (MT_REG_CSR_BASE+0x000000f0)
+#define ADR_MTX_MIB_WSID0 (MT_REG_CSR_BASE+0x000000f4)
+#define ADR_MTX_MIB_WSID1 (MT_REG_CSR_BASE+0x000000f8)
+#define ADR_MTX_DBG_DAT4 (MT_REG_CSR_BASE+0x000000fc)
+#define ADR_TXQ0_MTX_Q_MISC_EN (TXQ0_MT_Q_REG_CSR_BASE+0x00000000)
+#define ADR_TXQ0_MTX_Q_AIFSN (TXQ0_MT_Q_REG_CSR_BASE+0x00000004)
+#define ADR_TXQ0_MTX_Q_BKF_CNT (TXQ0_MT_Q_REG_CSR_BASE+0x00000008)
+#define ADR_TXQ0_MTX_Q_RC_LIMIT (TXQ0_MT_Q_REG_CSR_BASE+0x0000000c)
+#define ADR_TXQ0_MTX_Q_ID_MAP_L (TXQ0_MT_Q_REG_CSR_BASE+0x00000010)
+#define ADR_TXQ0_MTX_Q_TXOP_CH_THD (TXQ0_MT_Q_REG_CSR_BASE+0x00000014)
+#define ADR_TXQ0_MTX_Q_TXOP_OV_THD (TXQ0_MT_Q_REG_CSR_BASE+0x00000018)
+#define ADR_TXQ1_MTX_Q_MISC_EN (TXQ1_MT_Q_REG_CSR_BASE+0x00000000)
+#define ADR_TXQ1_MTX_Q_AIFSN (TXQ1_MT_Q_REG_CSR_BASE+0x00000004)
+#define ADR_TXQ1_MTX_Q_BKF_CNT (TXQ1_MT_Q_REG_CSR_BASE+0x00000008)
+#define ADR_TXQ1_MTX_Q_RC_LIMIT (TXQ1_MT_Q_REG_CSR_BASE+0x0000000c)
+#define ADR_TXQ1_MTX_Q_ID_MAP_L (TXQ1_MT_Q_REG_CSR_BASE+0x00000010)
+#define ADR_TXQ1_MTX_Q_TXOP_CH_THD (TXQ1_MT_Q_REG_CSR_BASE+0x00000014)
+#define ADR_TXQ1_MTX_Q_TXOP_OV_THD (TXQ1_MT_Q_REG_CSR_BASE+0x00000018)
+#define ADR_TXQ2_MTX_Q_MISC_EN (TXQ2_MT_Q_REG_CSR_BASE+0x00000000)
+#define ADR_TXQ2_MTX_Q_AIFSN (TXQ2_MT_Q_REG_CSR_BASE+0x00000004)
+#define ADR_TXQ2_MTX_Q_BKF_CNT (TXQ2_MT_Q_REG_CSR_BASE+0x00000008)
+#define ADR_TXQ2_MTX_Q_RC_LIMIT (TXQ2_MT_Q_REG_CSR_BASE+0x0000000c)
+#define ADR_TXQ2_MTX_Q_ID_MAP_L (TXQ2_MT_Q_REG_CSR_BASE+0x00000010)
+#define ADR_TXQ2_MTX_Q_TXOP_CH_THD (TXQ2_MT_Q_REG_CSR_BASE+0x00000014)
+#define ADR_TXQ2_MTX_Q_TXOP_OV_THD (TXQ2_MT_Q_REG_CSR_BASE+0x00000018)
+#define ADR_TXQ3_MTX_Q_MISC_EN (TXQ3_MT_Q_REG_CSR_BASE+0x00000000)
+#define ADR_TXQ3_MTX_Q_AIFSN (TXQ3_MT_Q_REG_CSR_BASE+0x00000004)
+#define ADR_TXQ3_MTX_Q_BKF_CNT (TXQ3_MT_Q_REG_CSR_BASE+0x00000008)
+#define ADR_TXQ3_MTX_Q_RC_LIMIT (TXQ3_MT_Q_REG_CSR_BASE+0x0000000c)
+#define ADR_TXQ3_MTX_Q_ID_MAP_L (TXQ3_MT_Q_REG_CSR_BASE+0x00000010)
+#define ADR_TXQ3_MTX_Q_TXOP_CH_THD (TXQ3_MT_Q_REG_CSR_BASE+0x00000014)
+#define ADR_TXQ3_MTX_Q_TXOP_OV_THD (TXQ3_MT_Q_REG_CSR_BASE+0x00000018)
+#define ADR_TXQ4_MTX_Q_MISC_EN (TXQ4_MT_Q_REG_CSR_BASE+0x00000000)
+#define ADR_TXQ4_MTX_Q_AIFSN (TXQ4_MT_Q_REG_CSR_BASE+0x00000004)
+#define ADR_TXQ4_MTX_Q_BKF_CNT (TXQ4_MT_Q_REG_CSR_BASE+0x00000008)
+#define ADR_TXQ4_MTX_Q_RC_LIMIT (TXQ4_MT_Q_REG_CSR_BASE+0x0000000c)
+#define ADR_TXQ4_MTX_Q_ID_MAP_L (TXQ4_MT_Q_REG_CSR_BASE+0x00000010)
+#define ADR_TXQ4_MTX_Q_TXOP_CH_THD (TXQ4_MT_Q_REG_CSR_BASE+0x00000014)
+#define ADR_TXQ4_MTX_Q_TXOP_OV_THD (TXQ4_MT_Q_REG_CSR_BASE+0x00000018)
+#define ADR_WSID0 (HIF_INFO_BASE+0x00000000)
+#define ADR_PEER_MAC0_0 (HIF_INFO_BASE+0x00000004)
+#define ADR_PEER_MAC0_1 (HIF_INFO_BASE+0x00000008)
+#define ADR_TX_ACK_POLICY_0_0 (HIF_INFO_BASE+0x0000000c)
+#define ADR_TX_SEQ_CTRL_0_0 (HIF_INFO_BASE+0x00000010)
+#define ADR_TX_ACK_POLICY_0_1 (HIF_INFO_BASE+0x00000014)
+#define ADR_TX_SEQ_CTRL_0_1 (HIF_INFO_BASE+0x00000018)
+#define ADR_TX_ACK_POLICY_0_2 (HIF_INFO_BASE+0x0000001c)
+#define ADR_TX_SEQ_CTRL_0_2 (HIF_INFO_BASE+0x00000020)
+#define ADR_TX_ACK_POLICY_0_3 (HIF_INFO_BASE+0x00000024)
+#define ADR_TX_SEQ_CTRL_0_3 (HIF_INFO_BASE+0x00000028)
+#define ADR_TX_ACK_POLICY_0_4 (HIF_INFO_BASE+0x0000002c)
+#define ADR_TX_SEQ_CTRL_0_4 (HIF_INFO_BASE+0x00000030)
+#define ADR_TX_ACK_POLICY_0_5 (HIF_INFO_BASE+0x00000034)
+#define ADR_TX_SEQ_CTRL_0_5 (HIF_INFO_BASE+0x00000038)
+#define ADR_TX_ACK_POLICY_0_6 (HIF_INFO_BASE+0x0000003c)
+#define ADR_TX_SEQ_CTRL_0_6 (HIF_INFO_BASE+0x00000040)
+#define ADR_TX_ACK_POLICY_0_7 (HIF_INFO_BASE+0x00000044)
+#define ADR_TX_SEQ_CTRL_0_7 (HIF_INFO_BASE+0x00000048)
+#define ADR_WSID1 (HIF_INFO_BASE+0x00000050)
+#define ADR_PEER_MAC1_0 (HIF_INFO_BASE+0x00000054)
+#define ADR_PEER_MAC1_1 (HIF_INFO_BASE+0x00000058)
+#define ADR_TX_ACK_POLICY_1_0 (HIF_INFO_BASE+0x0000005c)
+#define ADR_TX_SEQ_CTRL_1_0 (HIF_INFO_BASE+0x00000060)
+#define ADR_TX_ACK_POLICY_1_1 (HIF_INFO_BASE+0x00000064)
+#define ADR_TX_SEQ_CTRL_1_1 (HIF_INFO_BASE+0x00000068)
+#define ADR_TX_ACK_POLICY_1_2 (HIF_INFO_BASE+0x0000006c)
+#define ADR_TX_SEQ_CTRL_1_2 (HIF_INFO_BASE+0x00000070)
+#define ADR_TX_ACK_POLICY_1_3 (HIF_INFO_BASE+0x00000074)
+#define ADR_TX_SEQ_CTRL_1_3 (HIF_INFO_BASE+0x00000078)
+#define ADR_TX_ACK_POLICY_1_4 (HIF_INFO_BASE+0x0000007c)
+#define ADR_TX_SEQ_CTRL_1_4 (HIF_INFO_BASE+0x00000080)
+#define ADR_TX_ACK_POLICY_1_5 (HIF_INFO_BASE+0x00000084)
+#define ADR_TX_SEQ_CTRL_1_5 (HIF_INFO_BASE+0x00000088)
+#define ADR_TX_ACK_POLICY_1_6 (HIF_INFO_BASE+0x0000008c)
+#define ADR_TX_SEQ_CTRL_1_6 (HIF_INFO_BASE+0x00000090)
+#define ADR_TX_ACK_POLICY_1_7 (HIF_INFO_BASE+0x00000094)
+#define ADR_TX_SEQ_CTRL_1_7 (HIF_INFO_BASE+0x00000098)
+#define ADR_INFO0 (PHY_RATE_INFO_BASE+0x00000000)
+#define ADR_INFO1 (PHY_RATE_INFO_BASE+0x00000004)
+#define ADR_INFO2 (PHY_RATE_INFO_BASE+0x00000008)
+#define ADR_INFO3 (PHY_RATE_INFO_BASE+0x0000000c)
+#define ADR_INFO4 (PHY_RATE_INFO_BASE+0x00000010)
+#define ADR_INFO5 (PHY_RATE_INFO_BASE+0x00000014)
+#define ADR_INFO6 (PHY_RATE_INFO_BASE+0x00000018)
+#define ADR_INFO7 (PHY_RATE_INFO_BASE+0x0000001c)
+#define ADR_INFO8 (PHY_RATE_INFO_BASE+0x00000020)
+#define ADR_INFO9 (PHY_RATE_INFO_BASE+0x00000024)
+#define ADR_INFO10 (PHY_RATE_INFO_BASE+0x00000028)
+#define ADR_INFO11 (PHY_RATE_INFO_BASE+0x0000002c)
+#define ADR_INFO12 (PHY_RATE_INFO_BASE+0x00000030)
+#define ADR_INFO13 (PHY_RATE_INFO_BASE+0x00000034)
+#define ADR_INFO14 (PHY_RATE_INFO_BASE+0x00000038)
+#define ADR_INFO15 (PHY_RATE_INFO_BASE+0x0000003c)
+#define ADR_INFO16 (PHY_RATE_INFO_BASE+0x00000040)
+#define ADR_INFO17 (PHY_RATE_INFO_BASE+0x00000044)
+#define ADR_INFO18 (PHY_RATE_INFO_BASE+0x00000048)
+#define ADR_INFO19 (PHY_RATE_INFO_BASE+0x0000004c)
+#define ADR_INFO20 (PHY_RATE_INFO_BASE+0x00000050)
+#define ADR_INFO21 (PHY_RATE_INFO_BASE+0x00000054)
+#define ADR_INFO22 (PHY_RATE_INFO_BASE+0x00000058)
+#define ADR_INFO23 (PHY_RATE_INFO_BASE+0x0000005c)
+#define ADR_INFO24 (PHY_RATE_INFO_BASE+0x00000060)
+#define ADR_INFO25 (PHY_RATE_INFO_BASE+0x00000064)
+#define ADR_INFO26 (PHY_RATE_INFO_BASE+0x00000068)
+#define ADR_INFO27 (PHY_RATE_INFO_BASE+0x0000006c)
+#define ADR_INFO28 (PHY_RATE_INFO_BASE+0x00000070)
+#define ADR_INFO29 (PHY_RATE_INFO_BASE+0x00000074)
+#define ADR_INFO30 (PHY_RATE_INFO_BASE+0x00000078)
+#define ADR_INFO31 (PHY_RATE_INFO_BASE+0x0000007c)
+#define ADR_INFO32 (PHY_RATE_INFO_BASE+0x00000080)
+#define ADR_INFO33 (PHY_RATE_INFO_BASE+0x00000084)
+#define ADR_INFO34 (PHY_RATE_INFO_BASE+0x00000088)
+#define ADR_INFO35 (PHY_RATE_INFO_BASE+0x0000008c)
+#define ADR_INFO36 (PHY_RATE_INFO_BASE+0x00000090)
+#define ADR_INFO37 (PHY_RATE_INFO_BASE+0x00000094)
+#define ADR_INFO38 (PHY_RATE_INFO_BASE+0x00000098)
+#define ADR_INFO_MASK (PHY_RATE_INFO_BASE+0x0000009c)
+#define ADR_INFO_RATE_OFFSET (PHY_RATE_INFO_BASE+0x000000a0)
+#define ADR_INFO_IDX_ADDR (PHY_RATE_INFO_BASE+0x000000a4)
+#define ADR_INFO_LEN_ADDR (PHY_RATE_INFO_BASE+0x000000a8)
+#define ADR_IC_TIME_TAG_0 (PHY_RATE_INFO_BASE+0x000000ac)
+#define ADR_IC_TIME_TAG_1 (PHY_RATE_INFO_BASE+0x000000b0)
+#define ADR_PACKET_ID_ALLOCATION_PRIORITY (PHY_RATE_INFO_BASE+0x000000b4)
+#define ADR_MAC_MODE (MAC_GLB_SET_BASE+0x00000000)
+#define ADR_ALL_SOFTWARE_RESET (MAC_GLB_SET_BASE+0x00000004)
+#define ADR_ENG_SOFTWARE_RESET (MAC_GLB_SET_BASE+0x00000008)
+#define ADR_CSR_SOFTWARE_RESET (MAC_GLB_SET_BASE+0x0000000c)
+#define ADR_MAC_CLOCK_ENABLE (MAC_GLB_SET_BASE+0x00000010)
+#define ADR_MAC_ENGINE_CLOCK_ENABLE (MAC_GLB_SET_BASE+0x00000014)
+#define ADR_MAC_CSR_CLOCK_ENABLE (MAC_GLB_SET_BASE+0x00000018)
+#define ADR_GLBLE_SET (MAC_GLB_SET_BASE+0x0000001c)
+#define ADR_REASON_TRAP0 (MAC_GLB_SET_BASE+0x00000020)
+#define ADR_REASON_TRAP1 (MAC_GLB_SET_BASE+0x00000024)
+#define ADR_BSSID_0 (MAC_GLB_SET_BASE+0x00000028)
+#define ADR_BSSID_1 (MAC_GLB_SET_BASE+0x0000002c)
+#define ADR_SCRT_STATE (MAC_GLB_SET_BASE+0x0000002c)
+#define ADR_STA_MAC_0 (MAC_GLB_SET_BASE+0x00000030)
+#define ADR_STA_MAC_1 (MAC_GLB_SET_BASE+0x00000034)
+#define ADR_SCRT_SET (MAC_GLB_SET_BASE+0x00000038)
+#define ADR_BTCX0 (BTCX_REG_BASE+0x00000000)
+#define ADR_BTCX1 (BTCX_REG_BASE+0x00000004)
+#define ADR_SWITCH_CTL (BTCX_REG_BASE+0x00000008)
+#define ADR_MIB_EN (MIB_REG_BASE+0x00000000)
+#define ADR_MTX_WSID0_SUCC (MIB_REG_BASE+0x00000118)
+#define ADR_MTX_WSID0_FRM (MIB_REG_BASE+0x00000128)
+#define ADR_MTX_WSID0_RETRY (MIB_REG_BASE+0x00000138)
+#define ADR_MTX_WSID0_TOTAL (MIB_REG_BASE+0x00000148)
+#define ADR_MTX_GROUP (MIB_REG_BASE+0x0000016c)
+#define ADR_MTX_FAIL (MIB_REG_BASE+0x00000170)
+#define ADR_MTX_RETRY (MIB_REG_BASE+0x00000174)
+#define ADR_MTX_MULTI_RETRY (MIB_REG_BASE+0x00000178)
+#define ADR_MTX_RTS_SUCCESS (MIB_REG_BASE+0x0000017c)
+#define ADR_MTX_RTS_FAIL (MIB_REG_BASE+0x00000180)
+#define ADR_MTX_ACK_FAIL (MIB_REG_BASE+0x00000184)
+#define ADR_MTX_FRM (MIB_REG_BASE+0x00000188)
+#define ADR_MTX_ACK_TX (MIB_REG_BASE+0x0000018c)
+#define ADR_MTX_CTS_TX (MIB_REG_BASE+0x00000190)
+#define ADR_MRX_DUP_FRM (MIB_REG_BASE+0x00000194)
+#define ADR_MRX_FRG_FRM (MIB_REG_BASE+0x00000198)
+#define ADR_MRX_GROUP_FRM (MIB_REG_BASE+0x0000019c)
+#define ADR_MRX_FCS_ERR (MIB_REG_BASE+0x000001a0)
+#define ADR_MRX_FCS_SUCC (MIB_REG_BASE+0x000001a4)
+#define ADR_MRX_MISS (MIB_REG_BASE+0x000001a8)
+#define ADR_MRX_ALC_FAIL (MIB_REG_BASE+0x000001ac)
+#define ADR_MRX_DAT_NTF (MIB_REG_BASE+0x000001b0)
+#define ADR_MRX_RTS_NTF (MIB_REG_BASE+0x000001b4)
+#define ADR_MRX_CTS_NTF (MIB_REG_BASE+0x000001b8)
+#define ADR_MRX_ACK_NTF (MIB_REG_BASE+0x000001bc)
+#define ADR_MRX_BA_NTF (MIB_REG_BASE+0x000001c0)
+#define ADR_MRX_DATA_NTF (MIB_REG_BASE+0x000001c4)
+#define ADR_MRX_MNG_NTF (MIB_REG_BASE+0x000001c8)
+#define ADR_MRX_DAT_CRC_NTF (MIB_REG_BASE+0x000001cc)
+#define ADR_MRX_BAR_NTF (MIB_REG_BASE+0x000001d0)
+#define ADR_MRX_MB_MISS (MIB_REG_BASE+0x000001d4)
+#define ADR_MRX_NIDLE_MISS (MIB_REG_BASE+0x000001d8)
+#define ADR_MRX_CSR_NTF (MIB_REG_BASE+0x000001dc)
+#define ADR_DBG_Q0_FRM_SUCCESS (MIB_REG_BASE+0x00000218)
+#define ADR_DBG_Q0_FRM_FAIL (MIB_REG_BASE+0x0000021c)
+#define ADR_DBG_Q0_ACK_SUCCESS (MIB_REG_BASE+0x00000220)
+#define ADR_DBG_Q0_ACK_FAIL (MIB_REG_BASE+0x00000224)
+#define ADR_DBG_Q1_FRM_SUCCESS (MIB_REG_BASE+0x00000268)
+#define ADR_DBG_Q1_FRM_FAIL (MIB_REG_BASE+0x0000026c)
+#define ADR_DBG_Q1_ACK_SUCCESS (MIB_REG_BASE+0x00000270)
+#define ADR_DBG_Q1_ACK_FAIL (MIB_REG_BASE+0x00000274)
+#define ADR_DBG_Q2_FRM_SUCCESS (MIB_REG_BASE+0x00000318)
+#define ADR_DBG_Q2_FRM_FAIL (MIB_REG_BASE+0x0000031c)
+#define ADR_DBG_Q2_ACK_SUCCESS (MIB_REG_BASE+0x00000320)
+#define ADR_DBG_Q2_ACK_FAIL (MIB_REG_BASE+0x00000324)
+#define ADR_DBG_Q3_FRM_SUCCESS (MIB_REG_BASE+0x00000368)
+#define ADR_DBG_Q3_FRM_FAIL (MIB_REG_BASE+0x0000036c)
+#define ADR_DBG_Q3_ACK_SUCCESS (MIB_REG_BASE+0x00000370)
+#define ADR_DBG_Q3_ACK_FAIL (MIB_REG_BASE+0x00000374)
+#define ADR_MIB_SCRT_TKIP0 (MIB_REG_BASE+0x00000418)
+#define ADR_MIB_SCRT_TKIP1 (MIB_REG_BASE+0x0000041c)
+#define ADR_MIB_SCRT_TKIP2 (MIB_REG_BASE+0x00000420)
+#define ADR_MIB_SCRT_CCMP0 (MIB_REG_BASE+0x00000424)
+#define ADR_MIB_SCRT_CCMP1 (MIB_REG_BASE+0x00000428)
+#define ADR_DBG_LEN_CRC_FAIL (MIB_REG_BASE+0x00000468)
+#define ADR_DBG_LEN_ALC_FAIL (MIB_REG_BASE+0x0000046c)
+#define ADR_DBG_AMPDU_PASS (MIB_REG_BASE+0x00000470)
+#define ADR_DBG_AMPDU_FAIL (MIB_REG_BASE+0x00000474)
+#define ADR_ID_ALC_FAIL1 (MIB_REG_BASE+0x00000478)
+#define ADR_ID_ALC_FAIL2 (MIB_REG_BASE+0x0000047c)
+#define ADR_CBR_HARD_WIRE_PIN_REGISTER (CBR_A_REG_BASE+0x00110000)
+#define ADR_CBR_MANUAL_ENABLE_REGISTER (CBR_A_REG_BASE+0x00110004)
+#define ADR_CBR_LDO_REGISTER (CBR_A_REG_BASE+0x00110008)
+#define ADR_CBR_ABB_REGISTER_1 (CBR_A_REG_BASE+0x0011000c)
+#define ADR_CBR_ABB_REGISTER_2 (CBR_A_REG_BASE+0x00110010)
+#define ADR_CBR_TX_FE_REGISTER (CBR_A_REG_BASE+0x00110014)
+#define ADR_CBR_RX_FE_REGISTER_1 (CBR_A_REG_BASE+0x00110018)
+#define ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1 (CBR_A_REG_BASE+0x0011001c)
+#define ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2 (CBR_A_REG_BASE+0x00110020)
+#define ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3 (CBR_A_REG_BASE+0x00110024)
+#define ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4 (CBR_A_REG_BASE+0x00110028)
+#define ADR_CBR_RX_FSM_REGISTER (CBR_A_REG_BASE+0x0011002c)
+#define ADR_CBR_RX_ADC_REGISTER (CBR_A_REG_BASE+0x00110030)
+#define ADR_CBR_TX_DAC_REGISTER (CBR_A_REG_BASE+0x00110034)
+#define ADR_CBR_SX_ENABLE_RGISTER (CBR_A_REG_BASE+0x00110038)
+#define ADR_CBR_SYN_RGISTER_1 (CBR_A_REG_BASE+0x0011003c)
+#define ADR_CBR_SYN_RGISTER_2 (CBR_A_REG_BASE+0x00110040)
+#define ADR_CBR_SYN_PFD_CHP (CBR_A_REG_BASE+0x00110044)
+#define ADR_CBR_SYN_VCO_LOBF (CBR_A_REG_BASE+0x00110048)
+#define ADR_CBR_SYN_DIV_SDM_XOSC (CBR_A_REG_BASE+0x0011004c)
+#define ADR_CBR_SYN_LCK1 (CBR_A_REG_BASE+0x00110050)
+#define ADR_CBR_SYN_LCK2 (CBR_A_REG_BASE+0x00110054)
+#define ADR_CBR_DPLL_VCO_REGISTER (CBR_A_REG_BASE+0x00110058)
+#define ADR_CBR_DPLL_CP_PFD_REGISTER (CBR_A_REG_BASE+0x0011005c)
+#define ADR_CBR_DPLL_DIVIDER_REGISTER (CBR_A_REG_BASE+0x00110060)
+#define ADR_CBR_DCOC_IDAC_REGISTER1 (CBR_A_REG_BASE+0x00110064)
+#define ADR_CBR_DCOC_IDAC_REGISTER2 (CBR_A_REG_BASE+0x00110068)
+#define ADR_CBR_DCOC_IDAC_REGISTER3 (CBR_A_REG_BASE+0x0011006c)
+#define ADR_CBR_DCOC_IDAC_REGISTER4 (CBR_A_REG_BASE+0x00110070)
+#define ADR_CBR_DCOC_IDAC_REGISTER5 (CBR_A_REG_BASE+0x00110074)
+#define ADR_CBR_DCOC_IDAC_REGISTER6 (CBR_A_REG_BASE+0x00110078)
+#define ADR_CBR_DCOC_IDAC_REGISTER7 (CBR_A_REG_BASE+0x0011007c)
+#define ADR_CBR_DCOC_IDAC_REGISTER8 (CBR_A_REG_BASE+0x00110080)
+#define ADR_CBR_RCAL_REGISTER (CBR_A_REG_BASE+0x00110084)
+#define ADR_CBR_MANUAL_REGISTER (CBR_A_REG_BASE+0x00110088)
+#define ADR_CBR_TRX_DUMMY_REGISTER (CBR_A_REG_BASE+0x0011008c)
+#define ADR_CBR_SX_DUMMY_REGISTER (CBR_A_REG_BASE+0x00110090)
+#define ADR_CBR_READ_ONLY_FLAGS_1 (CBR_A_REG_BASE+0x00110094)
+#define ADR_CBR_READ_ONLY_FLAGS_2 (CBR_A_REG_BASE+0x00110098)
+#define ADR_CBR_RG_PKT_GEN_0 (CBR_A_REG_BASE+0x00120080)
+#define ADR_CBR_RG_PKT_GEN_1 (CBR_A_REG_BASE+0x00120084)
+#define ADR_CBR_RG_PKT_GEN_2 (CBR_A_REG_BASE+0x00120088)
+#define ADR_CBR_RG_INTEGRATION (CBR_A_REG_BASE+0x00120090)
+#define ADR_CBR_RG_PKT_GEN_TXCNT (CBR_A_REG_BASE+0x00120094)
+#define ADR_CBR_PATTERN_GEN (CBR_A_REG_BASE+0x001203f8)
+#define ADR_MB_CPU_INT (MB_REG_BASE+0x00000004)
+#define ADR_CPU_ID_TB0 (MB_REG_BASE+0x00000008)
+#define ADR_CPU_ID_TB1 (MB_REG_BASE+0x0000000c)
+#define ADR_CH0_TRIG_1 (MB_REG_BASE+0x00000010)
+#define ADR_CH0_TRIG_0 (MB_REG_BASE+0x00000010)
+#define ADR_CH0_PRI_TRIG (MB_REG_BASE+0x00000014)
+#define ADR_MCU_STATUS (MB_REG_BASE+0x00000018)
+#define ADR_RD_IN_FFCNT1 (MB_REG_BASE+0x0000001c)
+#define ADR_RD_IN_FFCNT2 (MB_REG_BASE+0x00000020)
+#define ADR_RD_FFIN_FULL (MB_REG_BASE+0x00000024)
+#define ADR_MBOX_HALT_CFG (MB_REG_BASE+0x0000002c)
+#define ADR_MB_DBG_CFG1 (MB_REG_BASE+0x00000030)
+#define ADR_MB_DBG_CFG2 (MB_REG_BASE+0x00000034)
+#define ADR_MB_DBG_CFG3 (MB_REG_BASE+0x00000038)
+#define ADR_MB_DBG_CFG4 (MB_REG_BASE+0x0000003c)
+#define ADR_MB_OUT_QUEUE_CFG (MB_REG_BASE+0x00000040)
+#define ADR_MB_OUT_QUEUE_FLUSH (MB_REG_BASE+0x00000044)
+#define ADR_RD_FFOUT_CNT1 (MB_REG_BASE+0x00000048)
+#define ADR_RD_FFOUT_CNT2 (MB_REG_BASE+0x0000004c)
+#define ADR_RD_FFOUT_CNT3 (MB_REG_BASE+0x00000050)
+#define ADR_RD_FFOUT_FULL (MB_REG_BASE+0x00000054)
+#define ADR_MB_THRESHOLD6 (MB_REG_BASE+0x0000006c)
+#define ADR_MB_THRESHOLD7 (MB_REG_BASE+0x00000070)
+#define ADR_MB_THRESHOLD8 (MB_REG_BASE+0x00000074)
+#define ADR_MB_THRESHOLD9 (MB_REG_BASE+0x00000078)
+#define ADR_MB_THRESHOLD10 (MB_REG_BASE+0x0000007c)
+#define ADR_MB_TRASH_CFG (MB_REG_BASE+0x00000080)
+#define ADR_MB_IN_FF_FLUSH (MB_REG_BASE+0x00000084)
+#define ADR_CPU_ID_TB2 (MB_REG_BASE+0x00000088)
+#define ADR_CPU_ID_TB3 (MB_REG_BASE+0x0000008c)
+#define ADR_PHY_IQ_LOG_CFG0 (MB_REG_BASE+0x00000090)
+#define ADR_PHY_IQ_LOG_CFG1 (MB_REG_BASE+0x00000094)
+#define ADR_PHY_IQ_LOG_LEN (MB_REG_BASE+0x00000098)
+#define ADR_PHY_IQ_LOG_PTR (MB_REG_BASE+0x0000009c)
+#define ADR_WR_ALC (ID_MNG_REG_BASE+0x00000000)
+#define ADR_GETID (ID_MNG_REG_BASE+0x00000000)
+#define ADR_CH_STA_PRI (ID_MNG_REG_BASE+0x00000004)
+#define ADR_RD_ID0 (ID_MNG_REG_BASE+0x00000008)
+#define ADR_RD_ID1 (ID_MNG_REG_BASE+0x0000000c)
+#define ADR_IMD_CFG (ID_MNG_REG_BASE+0x00000010)
+#define ADR_IMD_STA (ID_MNG_REG_BASE+0x00000014)
+#define ADR_ALC_STA (ID_MNG_REG_BASE+0x00000018)
+#define ADR_TRX_ID_COUNT (ID_MNG_REG_BASE+0x0000001c)
+#define ADR_TRX_ID_THRESHOLD (ID_MNG_REG_BASE+0x00000020)
+#define ADR_TX_ID0 (ID_MNG_REG_BASE+0x00000024)
+#define ADR_TX_ID1 (ID_MNG_REG_BASE+0x00000028)
+#define ADR_RX_ID0 (ID_MNG_REG_BASE+0x0000002c)
+#define ADR_RX_ID1 (ID_MNG_REG_BASE+0x00000030)
+#define ADR_RTN_STA (ID_MNG_REG_BASE+0x00000034)
+#define ADR_ID_LEN_THREADSHOLD1 (ID_MNG_REG_BASE+0x00000038)
+#define ADR_ID_LEN_THREADSHOLD2 (ID_MNG_REG_BASE+0x0000003c)
+#define ADR_CH_ARB_PRI (ID_MNG_REG_BASE+0x00000040)
+#define ADR_TX_ID_REMAIN_STATUS (ID_MNG_REG_BASE+0x00000044)
+#define ADR_ID_INFO_STA (ID_MNG_REG_BASE+0x00000048)
+#define ADR_TX_LIMIT_INTR (ID_MNG_REG_BASE+0x0000004c)
+#define ADR_TX_ID_ALL_INFO (ID_MNG_REG_BASE+0x00000050)
+#define ADR_RD_ID2 (ID_MNG_REG_BASE+0x00000054)
+#define ADR_RD_ID3 (ID_MNG_REG_BASE+0x00000058)
+#define ADR_TX_ID2 (ID_MNG_REG_BASE+0x0000005c)
+#define ADR_TX_ID3 (ID_MNG_REG_BASE+0x00000060)
+#define ADR_RX_ID2 (ID_MNG_REG_BASE+0x00000064)
+#define ADR_RX_ID3 (ID_MNG_REG_BASE+0x00000068)
+#define ADR_TX_ID_ALL_INFO2 (ID_MNG_REG_BASE+0x0000006c)
+#define ADR_TX_ID_ALL_INFO_A (ID_MNG_REG_BASE+0x00000070)
+#define ADR_TX_ID_ALL_INFO_B (ID_MNG_REG_BASE+0x00000074)
+#define ADR_TX_ID_REMAIN_STATUS2 (ID_MNG_REG_BASE+0x00000078)
+#define ADR_ALC_ID_INFO (ID_MNG_REG_BASE+0x0000007c)
+#define ADR_ALC_ID_INF1 (ID_MNG_REG_BASE+0x00000080)
+#define ADR_PHY_EN_0 (CSR_PHY_BASE+0x00000000)
+#define ADR_PHY_EN_1 (CSR_PHY_BASE+0x00000004)
+#define ADR_SVN_VERSION_REG (CSR_PHY_BASE+0x00000008)
+#define ADR_PHY_PKT_GEN_0 (CSR_PHY_BASE+0x0000000c)
+#define ADR_PHY_PKT_GEN_1 (CSR_PHY_BASE+0x00000010)
+#define ADR_PHY_PKT_GEN_2 (CSR_PHY_BASE+0x00000014)
+#define ADR_PHY_PKT_GEN_3 (CSR_PHY_BASE+0x00000018)
+#define ADR_PHY_PKT_GEN_4 (CSR_PHY_BASE+0x0000001c)
+#define ADR_PHY_REG_00 (CSR_PHY_BASE+0x00000020)
+#define ADR_PHY_REG_01 (CSR_PHY_BASE+0x0000002c)
+#define ADR_PHY_REG_02_AGC (CSR_PHY_BASE+0x00000030)
+#define ADR_PHY_REG_03_AGC (CSR_PHY_BASE+0x00000034)
+#define ADR_PHY_REG_04_AGC (CSR_PHY_BASE+0x00000038)
+#define ADR_PHY_REG_05_AGC (CSR_PHY_BASE+0x0000003c)
+#define ADR_PHY_REG_06_11B_DAGC (CSR_PHY_BASE+0x00000040)
+#define ADR_PHY_REG_07_11B_DAGC (CSR_PHY_BASE+0x00000044)
+#define ADR_PHY_REG_08_11GN_DAGC (CSR_PHY_BASE+0x00000048)
+#define ADR_PHY_REG_09_11GN_DAGC (CSR_PHY_BASE+0x0000004c)
+#define ADR_PHY_READ_REG_00_DIG_PWR (CSR_PHY_BASE+0x00000050)
+#define ADR_PHY_READ_REG_01_RF_GAIN_PWR (CSR_PHY_BASE+0x00000054)
+#define ADR_PHY_READ_REG_02_RF_GAIN_PWR (CSR_PHY_BASE+0x00000058)
+#define ADR_PHY_READ_REG_03_RF_GAIN_PWR (CSR_PHY_BASE+0x0000005c)
+#define ADR_PHY_REG_10_TX_DES (CSR_PHY_BASE+0x00000060)
+#define ADR_PHY_REG_11_TX_DES (CSR_PHY_BASE+0x00000064)
+#define ADR_PHY_REG_12_TX_DES (CSR_PHY_BASE+0x00000068)
+#define ADR_PHY_REG_13_RX_DES (CSR_PHY_BASE+0x0000006c)
+#define ADR_PHY_REG_14_RX_DES (CSR_PHY_BASE+0x00000070)
+#define ADR_PHY_REG_15_RX_DES (CSR_PHY_BASE+0x00000074)
+#define ADR_PHY_REG_16_TX_DES_EXCP (CSR_PHY_BASE+0x00000078)
+#define ADR_PHY_REG_17_TX_DES_EXCP (CSR_PHY_BASE+0x0000007c)
+#define ADR_PHY_REG_18_RSSI_SNR (CSR_PHY_BASE+0x00000080)
+#define ADR_PHY_REG_19_DAC_MANUAL (CSR_PHY_BASE+0x00000084)
+#define ADR_PHY_REG_20_MRX_CNT (CSR_PHY_BASE+0x00000088)
+#define ADR_PHY_REG_21_TRX_RAMP (CSR_PHY_BASE+0x00000094)
+#define ADR_PHY_REG_22_TRX_RAMP (CSR_PHY_BASE+0x00000098)
+#define ADR_PHY_REG_23_ANT (CSR_PHY_BASE+0x0000009c)
+#define ADR_PHY_REG_24_MTX_LEN_CNT (CSR_PHY_BASE+0x000000a0)
+#define ADR_PHY_REG_25_MTX_LEN_CNT (CSR_PHY_BASE+0x000000a4)
+#define ADR_PHY_REG_26_MRX_LEN_CNT (CSR_PHY_BASE+0x000000a8)
+#define ADR_PHY_REG_27_MRX_LEN_CNT (CSR_PHY_BASE+0x000000ac)
+#define ADR_PHY_READ_REG_04 (CSR_PHY_BASE+0x000000b0)
+#define ADR_PHY_READ_REG_05 (CSR_PHY_BASE+0x000000b4)
+#define ADR_PHY_REG_28_BIST (CSR_PHY_BASE+0x000000b8)
+#define ADR_PHY_READ_REG_06_BIST (CSR_PHY_BASE+0x000000d8)
+#define ADR_PHY_READ_REG_07_BIST (CSR_PHY_BASE+0x000000f0)
+#define ADR_PHY_REG_29_MTRX_MAC (CSR_PHY_BASE+0x000000fc)
+#define ADR_PHY_READ_REG_08_MTRX_MAC (CSR_PHY_BASE+0x00000100)
+#define ADR_PHY_READ_REG_09_MTRX_MAC (CSR_PHY_BASE+0x00000104)
+#define ADR_PHY_REG_30_TX_UP_FIL (CSR_PHY_BASE+0x00000108)
+#define ADR_PHY_REG_31_TX_UP_FIL (CSR_PHY_BASE+0x0000010c)
+#define ADR_PHY_REG_32_TX_UP_FIL (CSR_PHY_BASE+0x00000110)
+#define ADR_PHY_READ_TBUS (CSR_PHY_BASE+0x000003fc)
+#define ADR_TX_11B_FIL_COEF_00 (CSR_PHY_BASE+0x00001000)
+#define ADR_TX_11B_FIL_COEF_01 (CSR_PHY_BASE+0x00001004)
+#define ADR_TX_11B_FIL_COEF_02 (CSR_PHY_BASE+0x00001008)
+#define ADR_TX_11B_FIL_COEF_03 (CSR_PHY_BASE+0x0000100c)
+#define ADR_TX_11B_FIL_COEF_04 (CSR_PHY_BASE+0x00001010)
+#define ADR_TX_11B_FIL_COEF_05 (CSR_PHY_BASE+0x00001014)
+#define ADR_TX_11B_FIL_COEF_06 (CSR_PHY_BASE+0x00001018)
+#define ADR_TX_11B_FIL_COEF_07 (CSR_PHY_BASE+0x0000101c)
+#define ADR_TX_11B_FIL_COEF_08 (CSR_PHY_BASE+0x00001020)
+#define ADR_TX_11B_FIL_COEF_09 (CSR_PHY_BASE+0x00001024)
+#define ADR_TX_11B_FIL_COEF_10 (CSR_PHY_BASE+0x00001028)
+#define ADR_TX_11B_FIL_COEF_11 (CSR_PHY_BASE+0x0000102c)
+#define ADR_TX_11B_FIL_COEF_12 (CSR_PHY_BASE+0x00001030)
+#define ADR_TX_11B_FIL_COEF_13 (CSR_PHY_BASE+0x00001034)
+#define ADR_TX_11B_FIL_COEF_14 (CSR_PHY_BASE+0x00001038)
+#define ADR_TX_11B_FIL_COEF_15 (CSR_PHY_BASE+0x0000103c)
+#define ADR_TX_11B_FIL_COEF_16 (CSR_PHY_BASE+0x00001040)
+#define ADR_TX_11B_FIL_COEF_17 (CSR_PHY_BASE+0x00001044)
+#define ADR_TX_11B_FIL_COEF_18 (CSR_PHY_BASE+0x00001048)
+#define ADR_TX_11B_FIL_COEF_19 (CSR_PHY_BASE+0x0000104c)
+#define ADR_TX_11B_FIL_COEF_20 (CSR_PHY_BASE+0x00001050)
+#define ADR_TX_11B_FIL_COEF_21 (CSR_PHY_BASE+0x00001054)
+#define ADR_TX_11B_FIL_COEF_22 (CSR_PHY_BASE+0x00001058)
+#define ADR_TX_11B_FIL_COEF_23 (CSR_PHY_BASE+0x0000105c)
+#define ADR_TX_11B_FIL_COEF_24 (CSR_PHY_BASE+0x00001060)
+#define ADR_TX_11B_FIL_COEF_25 (CSR_PHY_BASE+0x00001064)
+#define ADR_TX_11B_FIL_COEF_26 (CSR_PHY_BASE+0x00001068)
+#define ADR_TX_11B_FIL_COEF_27 (CSR_PHY_BASE+0x0000106c)
+#define ADR_TX_11B_FIL_COEF_28 (CSR_PHY_BASE+0x00001070)
+#define ADR_TX_11B_FIL_COEF_29 (CSR_PHY_BASE+0x00001074)
+#define ADR_TX_11B_FIL_COEF_30 (CSR_PHY_BASE+0x00001078)
+#define ADR_TX_11B_FIL_COEF_31 (CSR_PHY_BASE+0x0000107c)
+#define ADR_TX_11B_FIL_COEF_32 (CSR_PHY_BASE+0x00001080)
+#define ADR_TX_11B_FIL_COEF_33 (CSR_PHY_BASE+0x00001084)
+#define ADR_TX_11B_FIL_COEF_34 (CSR_PHY_BASE+0x00001088)
+#define ADR_TX_11B_FIL_COEF_35 (CSR_PHY_BASE+0x0000108c)
+#define ADR_TX_11B_FIL_COEF_36 (CSR_PHY_BASE+0x00001090)
+#define ADR_TX_11B_FIL_COEF_37 (CSR_PHY_BASE+0x00001094)
+#define ADR_TX_11B_FIL_COEF_38 (CSR_PHY_BASE+0x00001098)
+#define ADR_TX_11B_FIL_COEF_39 (CSR_PHY_BASE+0x0000109c)
+#define ADR_TX_11B_FIL_COEF_40 (CSR_PHY_BASE+0x000010a0)
+#define ADR_TX_11B_PLCP (CSR_PHY_BASE+0x000010a4)
+#define ADR_TX_11B_RAMP (CSR_PHY_BASE+0x000010b4)
+#define ADR_TX_11B_EN_CNT_RST_N (CSR_PHY_BASE+0x000010d4)
+#define ADR_TX_11B_EN_CNT (CSR_PHY_BASE+0x000010d8)
+#define ADR_TX_11B_PKT_GEN_CNT (CSR_PHY_BASE+0x00001c00)
+#define ADR_RX_11B_DES_DLY (CSR_PHY_BASE+0x00002000)
+#define ADR_RX_11B_CCA_0 (CSR_PHY_BASE+0x00002004)
+#define ADR_RX_11B_CCA_1 (CSR_PHY_BASE+0x00002008)
+#define ADR_RX_11B_TR_KP_KI_0 (CSR_PHY_BASE+0x0000200c)
+#define ADR_RX_11B_TR_KP_KI_1 (CSR_PHY_BASE+0x00002010)
+#define ADR_RX_11B_CE_CNT_THRESHOLD (CSR_PHY_BASE+0x00002014)
+#define ADR_RX_11B_CE_MU_0 (CSR_PHY_BASE+0x00002018)
+#define ADR_RX_11B_CE_MU_1 (CSR_PHY_BASE+0x0000201c)
+#define ADR_RX_11B_EQ_MU_0 (CSR_PHY_BASE+0x00002020)
+#define ADR_RX_11B_EQ_MU_1 (CSR_PHY_BASE+0x00002024)
+#define ADR_RX_11B_EQ_CR_KP_KI (CSR_PHY_BASE+0x00002028)
+#define ADR_RX_11B_LPF_RATE (CSR_PHY_BASE+0x0000202c)
+#define ADR_RX_11B_CIT_CNT_THRESHOLD (CSR_PHY_BASE+0x00002030)
+#define ADR_RX_11B_EQ_CH_MAIN_TAP (CSR_PHY_BASE+0x00002034)
+#define ADR_RX_11B_SEARCH_CNT_TH (CSR_PHY_BASE+0x0000209c)
+#define ADR_RX_11B_CCA_CONTROL (CSR_PHY_BASE+0x000020a0)
+#define ADR_RX_11B_FREQUENCY_OFFSET (CSR_PHY_BASE+0x000023d4)
+#define ADR_RX_11B_SNR_RSSI (CSR_PHY_BASE+0x000023d8)
+#define ADR_RX_11B_SFD_CRC_CNT (CSR_PHY_BASE+0x000023e4)
+#define ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT (CSR_PHY_BASE+0x000023e8)
+#define ADR_RX_11B_PKT_CCA_AND_PKT_CNT (CSR_PHY_BASE+0x000023ec)
+#define ADR_RX_11B_SFD_FILED_0 (CSR_PHY_BASE+0x000023f0)
+#define ADR_RX_11B_SFD_FIELD_1 (CSR_PHY_BASE+0x000023f4)
+#define ADR_RX_11B_PKT_STAT_EN (CSR_PHY_BASE+0x000023f8)
+#define ADR_RX_11B_SOFT_RST (CSR_PHY_BASE+0x000023fc)
+#define ADR_TX_11GN_RAMP (CSR_PHY_BASE+0x000030a4)
+#define ADR_TX_11GN_PLCP (CSR_PHY_BASE+0x000030b8)
+#define ADR_TX_11GN_PKT_GEN_CNT (CSR_PHY_BASE+0x00003c00)
+#define ADR_TX_11GN_PLCP_CRC_ERR_CNT (CSR_PHY_BASE+0x00003c08)
+#define ADR_RX_11GN_DES_DLY (CSR_PHY_BASE+0x00004000)
+#define ADR_RX_11GN_TR_0 (CSR_PHY_BASE+0x00004004)
+#define ADR_RX_11GN_TR_1 (CSR_PHY_BASE+0x00004008)
+#define ADR_RX_11GN_TR_2 (CSR_PHY_BASE+0x0000400c)
+#define ADR_RX_11GN_CCA_0 (CSR_PHY_BASE+0x00004010)
+#define ADR_RX_11GN_CCA_1 (CSR_PHY_BASE+0x00004014)
+#define ADR_RX_11GN_CCA_2 (CSR_PHY_BASE+0x00004018)
+#define ADR_RX_11GN_CCA_FFT_SCALE (CSR_PHY_BASE+0x0000401c)
+#define ADR_RX_11GN_SOFT_DEMAP_0 (CSR_PHY_BASE+0x00004020)
+#define ADR_RX_11GN_SOFT_DEMAP_1 (CSR_PHY_BASE+0x00004024)
+#define ADR_RX_11GN_SOFT_DEMAP_2 (CSR_PHY_BASE+0x00004028)
+#define ADR_RX_11GN_SOFT_DEMAP_3 (CSR_PHY_BASE+0x0000402c)
+#define ADR_RX_11GN_SOFT_DEMAP_4 (CSR_PHY_BASE+0x00004030)
+#define ADR_RX_11GN_SOFT_DEMAP_5 (CSR_PHY_BASE+0x00004034)
+#define ADR_RX_11GN_SYM_BOUND_0 (CSR_PHY_BASE+0x00004038)
+#define ADR_RX_11GN_SYM_BOUND_1 (CSR_PHY_BASE+0x0000409c)
+#define ADR_RX_11GN_CCA_PWR (CSR_PHY_BASE+0x000040c0)
+#define ADR_RX_11GN_CCA_CNT (CSR_PHY_BASE+0x000040c4)
+#define ADR_RX_11GN_CCA_ATCOR_RE_CHECK (CSR_PHY_BASE+0x000040c8)
+#define ADR_RX_11GN_VTB_TB (CSR_PHY_BASE+0x00004130)
+#define ADR_RX_11GN_ERR_UPDATE (CSR_PHY_BASE+0x00004164)
+#define ADR_RX_11GN_SHORT_GI (CSR_PHY_BASE+0x00004180)
+#define ADR_RX_11GN_CHANNEL_UPDATE (CSR_PHY_BASE+0x00004188)
+#define ADR_RX_11GN_PKT_FORMAT_0 (CSR_PHY_BASE+0x00004190)
+#define ADR_RX_11GN_PKT_FORMAT_1 (CSR_PHY_BASE+0x00004194)
+#define ADR_RX_11GN_TX_TIME (CSR_PHY_BASE+0x00004380)
+#define ADR_RX_11GN_STBC_TR_KP_KI (CSR_PHY_BASE+0x00004384)
+#define ADR_RX_11GN_BIST_0 (CSR_PHY_BASE+0x00004388)
+#define ADR_RX_11GN_BIST_1 (CSR_PHY_BASE+0x0000438c)
+#define ADR_RX_11GN_BIST_2 (CSR_PHY_BASE+0x000043c0)
+#define ADR_RX_11GN_BIST_3 (CSR_PHY_BASE+0x000043c4)
+#define ADR_RX_11GN_BIST_4 (CSR_PHY_BASE+0x000043c8)
+#define ADR_RX_11GN_BIST_5 (CSR_PHY_BASE+0x000043cc)
+#define ADR_RX_11GN_SPECTRUM_ANALYZER (CSR_PHY_BASE+0x000043d4)
+#define ADR_RX_11GN_READ_0 (CSR_PHY_BASE+0x000043d8)
+#define ADR_RX_11GN_FREQ_OFFSET (CSR_PHY_BASE+0x000043dc)
+#define ADR_RX_11GN_SIGNAL_FIELD_0 (CSR_PHY_BASE+0x000043e0)
+#define ADR_RX_11GN_SIGNAL_FIELD_1 (CSR_PHY_BASE+0x000043e4)
+#define ADR_RX_11GN_PKT_ERR_CNT (CSR_PHY_BASE+0x000043e8)
+#define ADR_RX_11GN_PKT_CCA_AND_PKT_CNT (CSR_PHY_BASE+0x000043ec)
+#define ADR_RX_11GN_SERVICE_LENGTH_FIELD (CSR_PHY_BASE+0x000043f0)
+#define ADR_RX_11GN_RATE (CSR_PHY_BASE+0x000043f4)
+#define ADR_RX_11GN_STAT_EN (CSR_PHY_BASE+0x000043f8)
+#define ADR_RX_11GN_SOFT_RST (CSR_PHY_BASE+0x000043fc)
+#define ADR_RF_CONTROL_0 (CSR_PHY_BASE+0x00007000)
+#define ADR_RF_CONTROL_1 (CSR_PHY_BASE+0x00007004)
+#define ADR_TX_IQ_CONTROL_0 (CSR_PHY_BASE+0x00007040)
+#define ADR_TX_IQ_CONTROL_1 (CSR_PHY_BASE+0x00007044)
+#define ADR_TX_IQ_CONTROL_2 (CSR_PHY_BASE+0x00007048)
+#define ADR_TX_COMPENSATION_CONTROL (CSR_PHY_BASE+0x0000704c)
+#define ADR_RX_COMPENSATION_CONTROL (CSR_PHY_BASE+0x00007050)
+#define ADR_RX_OBSERVATION_CIRCUIT_0 (CSR_PHY_BASE+0x00007058)
+#define ADR_RX_OBSERVATION_CIRCUIT_1 (CSR_PHY_BASE+0x0000705c)
+#define ADR_RX_OBSERVATION_CIRCUIT_2 (CSR_PHY_BASE+0x00007060)
+#define ADR_RX_OBSERVATION_CIRCUIT_3 (CSR_PHY_BASE+0x00007064)
+#define ADR_RF_IQ_CONTROL_0 (CSR_PHY_BASE+0x0000706c)
+#define ADR_RF_IQ_CONTROL_1 (CSR_PHY_BASE+0x00007070)
+#define ADR_RF_IQ_CONTROL_2 (CSR_PHY_BASE+0x00007074)
+#define ADR_RF_IQ_CONTROL_3 (CSR_PHY_BASE+0x00007078)
+#define ADR_DPD_CONTROL (CSR_PHY_BASE+0x0000711c)
+#define ADR_DPD_GAIN_TABLE_0 (CSR_PHY_BASE+0x00007120)
+#define ADR_DPD_GAIN_TABLE_1 (CSR_PHY_BASE+0x00007124)
+#define ADR_DPD_GAIN_TABLE_2 (CSR_PHY_BASE+0x00007128)
+#define ADR_DPD_GAIN_TABLE_3 (CSR_PHY_BASE+0x00007130)
+#define ADR_DPD_GAIN_TABLE_4 (CSR_PHY_BASE+0x00007134)
+#define ADR_DPD_GAIN_TABLE_5 (CSR_PHY_BASE+0x00007138)
+#define ADR_DPD_GAIN_TABLE_6 (CSR_PHY_BASE+0x0000713c)
+#define ADR_DPD_GAIN_TABLE_7 (CSR_PHY_BASE+0x00007140)
+#define ADR_DPD_GAIN_TABLE_8 (CSR_PHY_BASE+0x00007144)
+#define ADR_DPD_GAIN_TABLE_9 (CSR_PHY_BASE+0x00007148)
+#define ADR_DPD_GAIN_TABLE_A (CSR_PHY_BASE+0x0000714c)
+#define ADR_DPD_GAIN_TABLE_B (CSR_PHY_BASE+0x00007150)
+#define ADR_DPD_GAIN_TABLE_C (CSR_PHY_BASE+0x00007154)
+#define ADR_DPD_PH_TABLE_0 (CSR_PHY_BASE+0x00007170)
+#define ADR_DPD_PH_TABLE_1 (CSR_PHY_BASE+0x00007174)
+#define ADR_DPD_PH_TABLE_2 (CSR_PHY_BASE+0x00007178)
+#define ADR_DPD_PH_TABLE_3 (CSR_PHY_BASE+0x00007180)
+#define ADR_DPD_PH_TABLE_4 (CSR_PHY_BASE+0x00007184)
+#define ADR_DPD_PH_TABLE_5 (CSR_PHY_BASE+0x00007188)
+#define ADR_DPD_PH_TABLE_6 (CSR_PHY_BASE+0x0000718c)
+#define ADR_DPD_PH_TABLE_7 (CSR_PHY_BASE+0x00007190)
+#define ADR_DPD_PH_TABLE_8 (CSR_PHY_BASE+0x00007194)
+#define ADR_DPD_PH_TABLE_9 (CSR_PHY_BASE+0x00007198)
+#define ADR_DPD_PH_TABLE_A (CSR_PHY_BASE+0x0000719c)
+#define ADR_DPD_PH_TABLE_B (CSR_PHY_BASE+0x000071a0)
+#define ADR_DPD_PH_TABLE_C (CSR_PHY_BASE+0x000071a4)
+#define ADR_DPD_GAIN_ESTIMATION_0 (CSR_PHY_BASE+0x000071b0)
+#define ADR_DPD_GAIN_ESTIMATION_1 (CSR_PHY_BASE+0x000071b4)
+#define ADR_DPD_GAIN_ESTIMATION_2 (CSR_PHY_BASE+0x000071b8)
+#define ADR_TX_GAIN_FACTOR (CSR_PHY_BASE+0x000071bc)
+#define ADR_HARD_WIRE_PIN_REGISTER (CSR_RF_BASE+0x00000000)
+#define ADR_MANUAL_ENABLE_REGISTER (CSR_RF_BASE+0x00000004)
+#define ADR_LDO_REGISTER (CSR_RF_BASE+0x00000008)
+#define ADR_ABB_REGISTER_1 (CSR_RF_BASE+0x0000000c)
+#define ADR_ABB_REGISTER_2 (CSR_RF_BASE+0x00000010)
+#define ADR_TX_FE_REGISTER (CSR_RF_BASE+0x00000014)
+#define ADR_RX_FE_REGISTER_1 (CSR_RF_BASE+0x00000018)
+#define ADR_RX_FE_GAIN_DECODER_REGISTER_1 (CSR_RF_BASE+0x0000001c)
+#define ADR_RX_FE_GAIN_DECODER_REGISTER_2 (CSR_RF_BASE+0x00000020)
+#define ADR_RX_FE_GAIN_DECODER_REGISTER_3 (CSR_RF_BASE+0x00000024)
+#define ADR_RX_FE_GAIN_DECODER_REGISTER_4 (CSR_RF_BASE+0x00000028)
+#define ADR_RX_TX_FSM_REGISTER (CSR_RF_BASE+0x0000002c)
+#define ADR_RX_ADC_REGISTER (CSR_RF_BASE+0x00000030)
+#define ADR_TX_DAC_REGISTER (CSR_RF_BASE+0x00000034)
+#define ADR_SX_ENABLE_REGISTER (CSR_RF_BASE+0x00000038)
+#define ADR_SYN_REGISTER_1 (CSR_RF_BASE+0x0000003c)
+#define ADR_SYN_REGISTER_2 (CSR_RF_BASE+0x00000040)
+#define ADR_SYN_PFD_CHP (CSR_RF_BASE+0x00000044)
+#define ADR_SYN_VCO_LOBF (CSR_RF_BASE+0x00000048)
+#define ADR_SYN_DIV_SDM_XOSC (CSR_RF_BASE+0x0000004c)
+#define ADR_SYN_KVCO_XO_FINE_TUNE_CBANK (CSR_RF_BASE+0x00000050)
+#define ADR_SYN_LCK_VT (CSR_RF_BASE+0x00000054)
+#define ADR_DPLL_VCO_REGISTER (CSR_RF_BASE+0x00000058)
+#define ADR_DPLL_CP_PFD_REGISTER (CSR_RF_BASE+0x0000005c)
+#define ADR_DPLL_DIVIDER_REGISTER (CSR_RF_BASE+0x00000060)
+#define ADR_DCOC_IDAC_REGISTER1 (CSR_RF_BASE+0x00000064)
+#define ADR_DCOC_IDAC_REGISTER2 (CSR_RF_BASE+0x00000068)
+#define ADR_DCOC_IDAC_REGISTER3 (CSR_RF_BASE+0x0000006c)
+#define ADR_DCOC_IDAC_REGISTER4 (CSR_RF_BASE+0x00000070)
+#define ADR_DCOC_IDAC_REGISTER5 (CSR_RF_BASE+0x00000074)
+#define ADR_DCOC_IDAC_REGISTER6 (CSR_RF_BASE+0x00000078)
+#define ADR_DCOC_IDAC_REGISTER7 (CSR_RF_BASE+0x0000007c)
+#define ADR_DCOC_IDAC_REGISTER8 (CSR_RF_BASE+0x00000080)
+#define ADR_RCAL_REGISTER (CSR_RF_BASE+0x00000084)
+#define ADR_SX_LCK_BIN_REGISTERS_I (CSR_RF_BASE+0x00000088)
+#define ADR_TRX_DUMMY_REGISTER (CSR_RF_BASE+0x0000008c)
+#define ADR_SX_DUMMY_REGISTER (CSR_RF_BASE+0x00000090)
+#define ADR_READ_ONLY_FLAGS_1 (CSR_RF_BASE+0x00000094)
+#define ADR_READ_ONLY_FLAGS_2 (CSR_RF_BASE+0x00000098)
+#define ADR_DPLL_FB_DIVIDER_REGISTERS_I (CSR_RF_BASE+0x0000009c)
+#define ADR_DPLL_FB_DIVIDER_REGISTERS_II (CSR_RF_BASE+0x000000a0)
+#define ADR_SX_LCK_BIN_REGISTERS_II (CSR_RF_BASE+0x000000a4)
+#define ADR_RC_OSC_32K_CAL_REGISTERS (CSR_RF_BASE+0x000000a8)
+#define ADR_RF_D_DIGITAL_DEBUG_PORT_REGISTER (CSR_RF_BASE+0x000000ac)
+#define ADR_MMU_CTRL (MMU_REG_BASE+0x00000000)
+#define ADR_HS_CTRL (MMU_REG_BASE+0x00000004)
+#define ADR_CPU_POR0_7 (MMU_REG_BASE+0x00000008)
+#define ADR_CPU_POR8_F (MMU_REG_BASE+0x0000000c)
+#define ADR_REG_LEN_CTRL (MMU_REG_BASE+0x00000010)
+#define ADR_DMN_READ_BYPASS (MMU_REG_BASE+0x00000014)
+#define ADR_ALC_RLS_ABORT (MMU_REG_BASE+0x00000018)
+#define ADR_DEBUG_CTL (MMU_REG_BASE+0x00000020)
+#define ADR_DEBUG_OUT (MMU_REG_BASE+0x00000024)
+#define ADR_MMU_STATUS (MMU_REG_BASE+0x00000028)
+#define ADR_DMN_STATUS (MMU_REG_BASE+0x0000002c)
+#define ADR_TAG_STATUS (MMU_REG_BASE+0x00000030)
+#define ADR_DMN_MCU_STATUS (MMU_REG_BASE+0x00000034)
+#define ADR_MB_IDTBL_0_STATUS (MMU_REG_BASE+0x00000040)
+#define ADR_MB_IDTBL_1_STATUS (MMU_REG_BASE+0x00000044)
+#define ADR_MB_IDTBL_2_STATUS (MMU_REG_BASE+0x00000048)
+#define ADR_MB_IDTBL_3_STATUS (MMU_REG_BASE+0x0000004c)
+#define ADR_PKT_IDTBL_0_STATUS (MMU_REG_BASE+0x00000050)
+#define ADR_PKT_IDTBL_1_STATUS (MMU_REG_BASE+0x00000054)
+#define ADR_PKT_IDTBL_2_STATUS (MMU_REG_BASE+0x00000058)
+#define ADR_PKT_IDTBL_3_STATUS (MMU_REG_BASE+0x0000005c)
+#define ADR_DMN_IDTBL_0_STATUS (MMU_REG_BASE+0x00000060)
+#define ADR_DMN_IDTBL_1_STATUS (MMU_REG_BASE+0x00000064)
+#define ADR_DMN_IDTBL_2_STATUS (MMU_REG_BASE+0x00000068)
+#define ADR_DMN_IDTBL_3_STATUS (MMU_REG_BASE+0x0000006c)
+#define ADR_MB_NEQID_0_STATUS (MMU_REG_BASE+0x00000070)
+#define ADR_MB_NEQID_1_STATUS (MMU_REG_BASE+0x00000074)
+#define ADR_MB_NEQID_2_STATUS (MMU_REG_BASE+0x00000078)
+#define ADR_MB_NEQID_3_STATUS (MMU_REG_BASE+0x0000007c)
+#define ADR_PKT_NEQID_0_STATUS (MMU_REG_BASE+0x00000080)
+#define ADR_PKT_NEQID_1_STATUS (MMU_REG_BASE+0x00000084)
+#define ADR_PKT_NEQID_2_STATUS (MMU_REG_BASE+0x00000088)
+#define ADR_PKT_NEQID_3_STATUS (MMU_REG_BASE+0x0000008c)
+#define ADR_ALC_NOCHG_ID_STATUS (MMU_REG_BASE+0x00000090)
+#define ADR_TAG_SRAM0_F_STATUS_0 (MMU_REG_BASE+0x000000a0)
+#define ADR_TAG_SRAM0_F_STATUS_1 (MMU_REG_BASE+0x000000a4)
+#define ADR_TAG_SRAM0_F_STATUS_2 (MMU_REG_BASE+0x000000a8)
+#define ADR_TAG_SRAM0_F_STATUS_3 (MMU_REG_BASE+0x000000ac)
+#define ADR_TAG_SRAM0_F_STATUS_4 (MMU_REG_BASE+0x000000b0)
+#define ADR_TAG_SRAM0_F_STATUS_5 (MMU_REG_BASE+0x000000b4)
+#define ADR_TAG_SRAM0_F_STATUS_6 (MMU_REG_BASE+0x000000b8)
+#define ADR_TAG_SRAM0_F_STATUS_7 (MMU_REG_BASE+0x000000bc)
+#define GET_MCU_ENABLE (((REG32(ADR_BRG_SW_RST)) & 0x00000001 ) >> 0)
+#define GET_MAC_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000002 ) >> 1)
+#define GET_MCU_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000004 ) >> 2)
+#define GET_SDIO_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000008 ) >> 3)
+#define GET_SPI_SLV_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000010 ) >> 4)
+#define GET_UART_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000020 ) >> 5)
+#define GET_DMA_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000040 ) >> 6)
+#define GET_WDT_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000080 ) >> 7)
+#define GET_I2C_SLV_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000100 ) >> 8)
+#define GET_INT_CTL_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000200 ) >> 9)
+#define GET_BTCX_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000400 ) >> 10)
+#define GET_GPIO_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000800 ) >> 11)
+#define GET_US0TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00001000 ) >> 12)
+#define GET_US1TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00002000 ) >> 13)
+#define GET_US2TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00004000 ) >> 14)
+#define GET_US3TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00008000 ) >> 15)
+#define GET_MS0TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00010000 ) >> 16)
+#define GET_MS1TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00020000 ) >> 17)
+#define GET_MS2TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00040000 ) >> 18)
+#define GET_MS3TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00080000 ) >> 19)
+#define GET_RF_BB_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00100000 ) >> 20)
+#define GET_SYS_ALL_RST (((REG32(ADR_BRG_SW_RST)) & 0x00200000 ) >> 21)
+#define GET_DAT_UART_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00400000 ) >> 22)
+#define GET_I2C_MST_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00800000 ) >> 23)
+#define GET_RG_REBOOT (((REG32(ADR_BOOT)) & 0x00000001 ) >> 0)
+#define GET_TRAP_IMG_FLS (((REG32(ADR_BOOT)) & 0x00010000 ) >> 16)
+#define GET_TRAP_REBOOT (((REG32(ADR_BOOT)) & 0x00020000 ) >> 17)
+#define GET_TRAP_BOOT_FLS (((REG32(ADR_BOOT)) & 0x00040000 ) >> 18)
+#define GET_CHIP_ID_31_0 (((REG32(ADR_CHIP_ID_0)) & 0xffffffff ) >> 0)
+#define GET_CHIP_ID_63_32 (((REG32(ADR_CHIP_ID_1)) & 0xffffffff ) >> 0)
+#define GET_CHIP_ID_95_64 (((REG32(ADR_CHIP_ID_2)) & 0xffffffff ) >> 0)
+#define GET_CHIP_ID_127_96 (((REG32(ADR_CHIP_ID_3)) & 0xffffffff ) >> 0)
+#define GET_CK_SEL_1_0 (((REG32(ADR_CLOCK_SELECTION)) & 0x00000003 ) >> 0)
+#define GET_CK_SEL_2 (((REG32(ADR_CLOCK_SELECTION)) & 0x00000004 ) >> 2)
+#define GET_SYS_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000001 ) >> 0)
+#define GET_MAC_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000002 ) >> 1)
+#define GET_MCU_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000004 ) >> 2)
+#define GET_SDIO_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000008 ) >> 3)
+#define GET_SPI_SLV_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000010 ) >> 4)
+#define GET_UART_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000020 ) >> 5)
+#define GET_DMA_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000040 ) >> 6)
+#define GET_WDT_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000080 ) >> 7)
+#define GET_I2C_SLV_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000100 ) >> 8)
+#define GET_INT_CTL_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000200 ) >> 9)
+#define GET_BTCX_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000400 ) >> 10)
+#define GET_GPIO_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000800 ) >> 11)
+#define GET_US0TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00001000 ) >> 12)
+#define GET_US1TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00002000 ) >> 13)
+#define GET_US2TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00004000 ) >> 14)
+#define GET_US3TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00008000 ) >> 15)
+#define GET_MS0TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00010000 ) >> 16)
+#define GET_MS1TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00020000 ) >> 17)
+#define GET_MS2TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00040000 ) >> 18)
+#define GET_MS3TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00080000 ) >> 19)
+#define GET_BIST_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00100000 ) >> 20)
+#define GET_I2C_MST_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00800000 ) >> 23)
+#define GET_BTCX_CSR_CLK_EN (((REG32(ADR_SYS_CSR_CLOCK_ENABLE)) & 0x00000400 ) >> 10)
+#define GET_MCU_DBG_SEL (((REG32(ADR_MCU_DBG_SEL)) & 0x0000003f ) >> 0)
+#define GET_MCU_STOP_NOGRANT (((REG32(ADR_MCU_DBG_SEL)) & 0x00000100 ) >> 8)
+#define GET_MCU_STOP_ANYTIME (((REG32(ADR_MCU_DBG_SEL)) & 0x00000200 ) >> 9)
+#define GET_MCU_DBG_DATA (((REG32(ADR_MCU_DBG_DATA)) & 0xffffffff ) >> 0)
+#define GET_AHB_SW_RST (((REG32(ADR_AHB_BRG_STATUS)) & 0x00000001 ) >> 0)
+#define GET_AHB_ERR_RST (((REG32(ADR_AHB_BRG_STATUS)) & 0x00000002 ) >> 1)
+#define GET_REG_AHB_DEBUG_MX (((REG32(ADR_AHB_BRG_STATUS)) & 0x00000030 ) >> 4)
+#define GET_REG_PKT_W_NBRT (((REG32(ADR_AHB_BRG_STATUS)) & 0x00000100 ) >> 8)
+#define GET_REG_PKT_R_NBRT (((REG32(ADR_AHB_BRG_STATUS)) & 0x00000200 ) >> 9)
+#define GET_IQ_SRAM_SEL_0 (((REG32(ADR_AHB_BRG_STATUS)) & 0x00001000 ) >> 12)
+#define GET_IQ_SRAM_SEL_1 (((REG32(ADR_AHB_BRG_STATUS)) & 0x00002000 ) >> 13)
+#define GET_IQ_SRAM_SEL_2 (((REG32(ADR_AHB_BRG_STATUS)) & 0x00004000 ) >> 14)
+#define GET_AHB_STATUS (((REG32(ADR_AHB_BRG_STATUS)) & 0xffff0000 ) >> 16)
+#define GET_PARALLEL_DR (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000001 ) >> 0)
+#define GET_MBRUN (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000010 ) >> 4)
+#define GET_SHIFT_DR (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000100 ) >> 8)
+#define GET_MODE_REG_SI (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000200 ) >> 9)
+#define GET_SIMULATION_MODE (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000400 ) >> 10)
+#define GET_DBIST_MODE (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000800 ) >> 11)
+#define GET_MODE_REG_IN (((REG32(ADR_BIST_MODE_REG_IN)) & 0x001fffff ) >> 0)
+#define GET_MODE_REG_OUT_MCU (((REG32(ADR_BIST_MODE_REG_OUT)) & 0x001fffff ) >> 0)
+#define GET_MODE_REG_SO_MCU (((REG32(ADR_BIST_MODE_REG_OUT)) & 0x80000000 ) >> 31)
+#define GET_MONITOR_BUS_MCU_31_0 (((REG32(ADR_BIST_MONITOR_BUS_LSB)) & 0xffffffff ) >> 0)
+#define GET_MONITOR_BUS_MCU_33_32 (((REG32(ADR_BIST_MONITOR_BUS_MSB)) & 0x00000003 ) >> 0)
+#define GET_TB_ADR_SEL (((REG32(ADR_TB_ADR_SEL)) & 0x0000ffff ) >> 0)
+#define GET_TB_CS (((REG32(ADR_TB_ADR_SEL)) & 0x80000000 ) >> 31)
+#define GET_TB_RDATA (((REG32(ADR_TB_RDATA)) & 0xffffffff ) >> 0)
+#define GET_UART_W2B_EN (((REG32(ADR_UART_W2B)) & 0x00000001 ) >> 0)
+#define GET_DATA_UART_W2B_EN (((REG32(ADR_UART_W2B)) & 0x00000010 ) >> 4)
+#define GET_AHB_ILL_ADDR (((REG32(ADR_AHB_ILL_ADDR)) & 0xffffffff ) >> 0)
+#define GET_AHB_FEN_ADDR (((REG32(ADR_AHB_FEN_ADDR)) & 0xffffffff ) >> 0)
+#define GET_ILL_ADDR_CLR (((REG32(ADR_AHB_ILLFEN_STATUS)) & 0x00000001 ) >> 0)
+#define GET_FENCE_HIT_CLR (((REG32(ADR_AHB_ILLFEN_STATUS)) & 0x00000002 ) >> 1)
+#define GET_ILL_ADDR_INT (((REG32(ADR_AHB_ILLFEN_STATUS)) & 0x00000010 ) >> 4)
+#define GET_FENCE_HIT_INT (((REG32(ADR_AHB_ILLFEN_STATUS)) & 0x00000020 ) >> 5)
+#define GET_PWM_INI_VALUE_P_A (((REG32(ADR_PWM_A)) & 0x000000ff ) >> 0)
+#define GET_PWM_INI_VALUE_N_A (((REG32(ADR_PWM_A)) & 0x0000ff00 ) >> 8)
+#define GET_PWM_POST_SCALER_A (((REG32(ADR_PWM_A)) & 0x000f0000 ) >> 16)
+#define GET_PWM_ALWAYSON_A (((REG32(ADR_PWM_A)) & 0x20000000 ) >> 29)
+#define GET_PWM_INVERT_A (((REG32(ADR_PWM_A)) & 0x40000000 ) >> 30)
+#define GET_PWM_ENABLE_A (((REG32(ADR_PWM_A)) & 0x80000000 ) >> 31)
+#define GET_PWM_INI_VALUE_P_B (((REG32(ADR_PWM_B)) & 0x000000ff ) >> 0)
+#define GET_PWM_INI_VALUE_N_B (((REG32(ADR_PWM_B)) & 0x0000ff00 ) >> 8)
+#define GET_PWM_POST_SCALER_B (((REG32(ADR_PWM_B)) & 0x000f0000 ) >> 16)
+#define GET_PWM_ALWAYSON_B (((REG32(ADR_PWM_B)) & 0x20000000 ) >> 29)
+#define GET_PWM_INVERT_B (((REG32(ADR_PWM_B)) & 0x40000000 ) >> 30)
+#define GET_PWM_ENABLE_B (((REG32(ADR_PWM_B)) & 0x80000000 ) >> 31)
+#define GET_HBUSREQ_LOCK (((REG32(ADR_HBUSREQ_LOCK)) & 0x00001fff ) >> 0)
+#define GET_HBURST_LOCK (((REG32(ADR_HBURST_LOCK)) & 0x00001fff ) >> 0)
+#define GET_PRESCALER_USTIMER (((REG32(ADR_PRESCALER_USTIMER)) & 0x000001ff ) >> 0)
+#define GET_MODE_REG_IN_MMU (((REG32(ADR_BIST_MODE_REG_IN_MMU)) & 0x0000ffff ) >> 0)
+#define GET_MODE_REG_OUT_MMU (((REG32(ADR_BIST_MODE_REG_OUT_MMU)) & 0x0000ffff ) >> 0)
+#define GET_MODE_REG_SO_MMU (((REG32(ADR_BIST_MODE_REG_OUT_MMU)) & 0x80000000 ) >> 31)
+#define GET_MONITOR_BUS_MMU (((REG32(ADR_BIST_MONITOR_BUS_MMU)) & 0x0007ffff ) >> 0)
+#define GET_TEST_MODE0 (((REG32(ADR_TEST_MODE)) & 0x00000001 ) >> 0)
+#define GET_TEST_MODE1 (((REG32(ADR_TEST_MODE)) & 0x00000002 ) >> 1)
+#define GET_TEST_MODE2 (((REG32(ADR_TEST_MODE)) & 0x00000004 ) >> 2)
+#define GET_TEST_MODE3 (((REG32(ADR_TEST_MODE)) & 0x00000008 ) >> 3)
+#define GET_TEST_MODE4 (((REG32(ADR_TEST_MODE)) & 0x00000010 ) >> 4)
+#define GET_TEST_MODE_ALL (((REG32(ADR_TEST_MODE)) & 0x00000020 ) >> 5)
+#define GET_WDT_INIT (((REG32(ADR_BOOT_INFO)) & 0x00000001 ) >> 0)
+#define GET_SD_HOST_INIT (((REG32(ADR_BOOT_INFO)) & 0x00000002 ) >> 1)
+#define GET_ALLOW_SD_RESET (((REG32(ADR_SD_INIT_CFG)) & 0x00000001 ) >> 0)
+#define GET_UART_NRTS (((REG32(ADR_SPARE_UART_INFO)) & 0x00000001 ) >> 0)
+#define GET_UART_NCTS (((REG32(ADR_SPARE_UART_INFO)) & 0x00000002 ) >> 1)
+#define GET_TU0_TM_INIT_VALUE (((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TU0_TM_MODE (((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TU0_TM_INT_STS_DONE (((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TU0_TM_INT_MASK (((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TU0_TM_CUR_VALUE (((REG32(ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_TU1_TM_INIT_VALUE (((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TU1_TM_MODE (((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TU1_TM_INT_STS_DONE (((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TU1_TM_INT_MASK (((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TU1_TM_CUR_VALUE (((REG32(ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_TU2_TM_INIT_VALUE (((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TU2_TM_MODE (((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TU2_TM_INT_STS_DONE (((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TU2_TM_INT_MASK (((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TU2_TM_CUR_VALUE (((REG32(ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_TU3_TM_INIT_VALUE (((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TU3_TM_MODE (((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TU3_TM_INT_STS_DONE (((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TU3_TM_INT_MASK (((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TU3_TM_CUR_VALUE (((REG32(ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_TM0_TM_INIT_VALUE (((REG32(ADR_TM0_MILISECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TM0_TM_MODE (((REG32(ADR_TM0_MILISECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TM0_TM_INT_STS_DONE (((REG32(ADR_TM0_MILISECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TM0_TM_INT_MASK (((REG32(ADR_TM0_MILISECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TM0_TM_CUR_VALUE (((REG32(ADR_TM0_CURRENT_MILISECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_TM1_TM_INIT_VALUE (((REG32(ADR_TM1_MILISECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TM1_TM_MODE (((REG32(ADR_TM1_MILISECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TM1_TM_INT_STS_DONE (((REG32(ADR_TM1_MILISECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TM1_TM_INT_MASK (((REG32(ADR_TM1_MILISECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TM1_TM_CUR_VALUE (((REG32(ADR_TM1_CURRENT_MILISECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_TM2_TM_INIT_VALUE (((REG32(ADR_TM2_MILISECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TM2_TM_MODE (((REG32(ADR_TM2_MILISECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TM2_TM_INT_STS_DONE (((REG32(ADR_TM2_MILISECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TM2_TM_INT_MASK (((REG32(ADR_TM2_MILISECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TM2_TM_CUR_VALUE (((REG32(ADR_TM2_CURRENT_MILISECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_TM3_TM_INIT_VALUE (((REG32(ADR_TM3_MILISECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TM3_TM_MODE (((REG32(ADR_TM3_MILISECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TM3_TM_INT_STS_DONE (((REG32(ADR_TM3_MILISECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TM3_TM_INT_MASK (((REG32(ADR_TM3_MILISECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TM3_TM_CUR_VALUE (((REG32(ADR_TM3_CURRENT_MILISECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_MCU_WDT_TIME_CNT (((REG32(ADR_MCU_WDOG_REG)) & 0x0000ffff ) >> 0)
+#define GET_MCU_WDT_STATUS (((REG32(ADR_MCU_WDOG_REG)) & 0x00020000 ) >> 17)
+#define GET_MCU_WDOG_ENA (((REG32(ADR_MCU_WDOG_REG)) & 0x80000000 ) >> 31)
+#define GET_SYS_WDT_TIME_CNT (((REG32(ADR_SYS_WDOG_REG)) & 0x0000ffff ) >> 0)
+#define GET_SYS_WDT_STATUS (((REG32(ADR_SYS_WDOG_REG)) & 0x00020000 ) >> 17)
+#define GET_SYS_WDOG_ENA (((REG32(ADR_SYS_WDOG_REG)) & 0x80000000 ) >> 31)
+#define GET_XLNA_EN_O_OE (((REG32(ADR_PAD6)) & 0x00000001 ) >> 0)
+#define GET_XLNA_EN_O_PE (((REG32(ADR_PAD6)) & 0x00000002 ) >> 1)
+#define GET_PAD6_IE (((REG32(ADR_PAD6)) & 0x00000008 ) >> 3)
+#define GET_PAD6_SEL_I (((REG32(ADR_PAD6)) & 0x00000030 ) >> 4)
+#define GET_PAD6_OD (((REG32(ADR_PAD6)) & 0x00000100 ) >> 8)
+#define GET_PAD6_SEL_O (((REG32(ADR_PAD6)) & 0x00001000 ) >> 12)
+#define GET_XLNA_EN_O_C (((REG32(ADR_PAD6)) & 0x10000000 ) >> 28)
+#define GET_WIFI_TX_SW_O_OE (((REG32(ADR_PAD7)) & 0x00000001 ) >> 0)
+#define GET_WIFI_TX_SW_O_PE (((REG32(ADR_PAD7)) & 0x00000002 ) >> 1)
+#define GET_PAD7_IE (((REG32(ADR_PAD7)) & 0x00000008 ) >> 3)
+#define GET_PAD7_SEL_I (((REG32(ADR_PAD7)) & 0x00000030 ) >> 4)
+#define GET_PAD7_OD (((REG32(ADR_PAD7)) & 0x00000100 ) >> 8)
+#define GET_PAD7_SEL_O (((REG32(ADR_PAD7)) & 0x00001000 ) >> 12)
+#define GET_WIFI_TX_SW_O_C (((REG32(ADR_PAD7)) & 0x10000000 ) >> 28)
+#define GET_WIFI_RX_SW_O_OE (((REG32(ADR_PAD8)) & 0x00000001 ) >> 0)
+#define GET_WIFI_RX_SW_O_PE (((REG32(ADR_PAD8)) & 0x00000002 ) >> 1)
+#define GET_PAD8_IE (((REG32(ADR_PAD8)) & 0x00000008 ) >> 3)
+#define GET_PAD8_SEL_I (((REG32(ADR_PAD8)) & 0x00000030 ) >> 4)
+#define GET_PAD8_OD (((REG32(ADR_PAD8)) & 0x00000100 ) >> 8)
+#define GET_WIFI_RX_SW_O_C (((REG32(ADR_PAD8)) & 0x10000000 ) >> 28)
+#define GET_BT_SW_O_OE (((REG32(ADR_PAD9)) & 0x00000001 ) >> 0)
+#define GET_BT_SW_O_PE (((REG32(ADR_PAD9)) & 0x00000002 ) >> 1)
+#define GET_PAD9_IE (((REG32(ADR_PAD9)) & 0x00000008 ) >> 3)
+#define GET_PAD9_SEL_I (((REG32(ADR_PAD9)) & 0x00000030 ) >> 4)
+#define GET_PAD9_OD (((REG32(ADR_PAD9)) & 0x00000100 ) >> 8)
+#define GET_PAD9_SEL_O (((REG32(ADR_PAD9)) & 0x00001000 ) >> 12)
+#define GET_BT_SW_O_C (((REG32(ADR_PAD9)) & 0x10000000 ) >> 28)
+#define GET_XPA_EN_O_OE (((REG32(ADR_PAD11)) & 0x00000001 ) >> 0)
+#define GET_XPA_EN_O_PE (((REG32(ADR_PAD11)) & 0x00000002 ) >> 1)
+#define GET_PAD11_IE (((REG32(ADR_PAD11)) & 0x00000008 ) >> 3)
+#define GET_PAD11_SEL_I (((REG32(ADR_PAD11)) & 0x00000030 ) >> 4)
+#define GET_PAD11_OD (((REG32(ADR_PAD11)) & 0x00000100 ) >> 8)
+#define GET_PAD11_SEL_O (((REG32(ADR_PAD11)) & 0x00001000 ) >> 12)
+#define GET_XPA_EN_O_C (((REG32(ADR_PAD11)) & 0x10000000 ) >> 28)
+#define GET_PAD15_OE (((REG32(ADR_PAD15)) & 0x00000001 ) >> 0)
+#define GET_PAD15_PE (((REG32(ADR_PAD15)) & 0x00000002 ) >> 1)
+#define GET_PAD15_DS (((REG32(ADR_PAD15)) & 0x00000004 ) >> 2)
+#define GET_PAD15_IE (((REG32(ADR_PAD15)) & 0x00000008 ) >> 3)
+#define GET_PAD15_SEL_I (((REG32(ADR_PAD15)) & 0x00000030 ) >> 4)
+#define GET_PAD15_OD (((REG32(ADR_PAD15)) & 0x00000100 ) >> 8)
+#define GET_PAD15_SEL_O (((REG32(ADR_PAD15)) & 0x00001000 ) >> 12)
+#define GET_TEST_1_ID (((REG32(ADR_PAD15)) & 0x10000000 ) >> 28)
+#define GET_PAD16_OE (((REG32(ADR_PAD16)) & 0x00000001 ) >> 0)
+#define GET_PAD16_PE (((REG32(ADR_PAD16)) & 0x00000002 ) >> 1)
+#define GET_PAD16_DS (((REG32(ADR_PAD16)) & 0x00000004 ) >> 2)
+#define GET_PAD16_IE (((REG32(ADR_PAD16)) & 0x00000008 ) >> 3)
+#define GET_PAD16_SEL_I (((REG32(ADR_PAD16)) & 0x00000030 ) >> 4)
+#define GET_PAD16_OD (((REG32(ADR_PAD16)) & 0x00000100 ) >> 8)
+#define GET_PAD16_SEL_O (((REG32(ADR_PAD16)) & 0x00001000 ) >> 12)
+#define GET_TEST_2_ID (((REG32(ADR_PAD16)) & 0x10000000 ) >> 28)
+#define GET_PAD17_OE (((REG32(ADR_PAD17)) & 0x00000001 ) >> 0)
+#define GET_PAD17_PE (((REG32(ADR_PAD17)) & 0x00000002 ) >> 1)
+#define GET_PAD17_DS (((REG32(ADR_PAD17)) & 0x00000004 ) >> 2)
+#define GET_PAD17_IE (((REG32(ADR_PAD17)) & 0x00000008 ) >> 3)
+#define GET_PAD17_SEL_I (((REG32(ADR_PAD17)) & 0x00000030 ) >> 4)
+#define GET_PAD17_OD (((REG32(ADR_PAD17)) & 0x00000100 ) >> 8)
+#define GET_PAD17_SEL_O (((REG32(ADR_PAD17)) & 0x00001000 ) >> 12)
+#define GET_TEST_3_ID (((REG32(ADR_PAD17)) & 0x10000000 ) >> 28)
+#define GET_PAD18_OE (((REG32(ADR_PAD18)) & 0x00000001 ) >> 0)
+#define GET_PAD18_PE (((REG32(ADR_PAD18)) & 0x00000002 ) >> 1)
+#define GET_PAD18_DS (((REG32(ADR_PAD18)) & 0x00000004 ) >> 2)
+#define GET_PAD18_IE (((REG32(ADR_PAD18)) & 0x00000008 ) >> 3)
+#define GET_PAD18_SEL_I (((REG32(ADR_PAD18)) & 0x00000030 ) >> 4)
+#define GET_PAD18_OD (((REG32(ADR_PAD18)) & 0x00000100 ) >> 8)
+#define GET_PAD18_SEL_O (((REG32(ADR_PAD18)) & 0x00003000 ) >> 12)
+#define GET_TEST_4_ID (((REG32(ADR_PAD18)) & 0x10000000 ) >> 28)
+#define GET_PAD19_OE (((REG32(ADR_PAD19)) & 0x00000001 ) >> 0)
+#define GET_PAD19_PE (((REG32(ADR_PAD19)) & 0x00000002 ) >> 1)
+#define GET_PAD19_DS (((REG32(ADR_PAD19)) & 0x00000004 ) >> 2)
+#define GET_PAD19_IE (((REG32(ADR_PAD19)) & 0x00000008 ) >> 3)
+#define GET_PAD19_SEL_I (((REG32(ADR_PAD19)) & 0x00000030 ) >> 4)
+#define GET_PAD19_OD (((REG32(ADR_PAD19)) & 0x00000100 ) >> 8)
+#define GET_PAD19_SEL_O (((REG32(ADR_PAD19)) & 0x00007000 ) >> 12)
+#define GET_SHORT_TO_20_ID (((REG32(ADR_PAD19)) & 0x10000000 ) >> 28)
+#define GET_PAD20_OE (((REG32(ADR_PAD20)) & 0x00000001 ) >> 0)
+#define GET_PAD20_PE (((REG32(ADR_PAD20)) & 0x00000002 ) >> 1)
+#define GET_PAD20_DS (((REG32(ADR_PAD20)) & 0x00000004 ) >> 2)
+#define GET_PAD20_IE (((REG32(ADR_PAD20)) & 0x00000008 ) >> 3)
+#define GET_PAD20_SEL_I (((REG32(ADR_PAD20)) & 0x000000f0 ) >> 4)
+#define GET_PAD20_OD (((REG32(ADR_PAD20)) & 0x00000100 ) >> 8)
+#define GET_PAD20_SEL_O (((REG32(ADR_PAD20)) & 0x00003000 ) >> 12)
+#define GET_STRAP0 (((REG32(ADR_PAD20)) & 0x08000000 ) >> 27)
+#define GET_GPIO_TEST_1_ID (((REG32(ADR_PAD20)) & 0x10000000 ) >> 28)
+#define GET_PAD21_OE (((REG32(ADR_PAD21)) & 0x00000001 ) >> 0)
+#define GET_PAD21_PE (((REG32(ADR_PAD21)) & 0x00000002 ) >> 1)
+#define GET_PAD21_DS (((REG32(ADR_PAD21)) & 0x00000004 ) >> 2)
+#define GET_PAD21_IE (((REG32(ADR_PAD21)) & 0x00000008 ) >> 3)
+#define GET_PAD21_SEL_I (((REG32(ADR_PAD21)) & 0x00000070 ) >> 4)
+#define GET_PAD21_OD (((REG32(ADR_PAD21)) & 0x00000100 ) >> 8)
+#define GET_PAD21_SEL_O (((REG32(ADR_PAD21)) & 0x00003000 ) >> 12)
+#define GET_STRAP3 (((REG32(ADR_PAD21)) & 0x08000000 ) >> 27)
+#define GET_GPIO_TEST_2_ID (((REG32(ADR_PAD21)) & 0x10000000 ) >> 28)
+#define GET_PAD22_OE (((REG32(ADR_PAD22)) & 0x00000001 ) >> 0)
+#define GET_PAD22_PE (((REG32(ADR_PAD22)) & 0x00000002 ) >> 1)
+#define GET_PAD22_DS (((REG32(ADR_PAD22)) & 0x00000004 ) >> 2)
+#define GET_PAD22_IE (((REG32(ADR_PAD22)) & 0x00000008 ) >> 3)
+#define GET_PAD22_SEL_I (((REG32(ADR_PAD22)) & 0x00000070 ) >> 4)
+#define GET_PAD22_OD (((REG32(ADR_PAD22)) & 0x00000100 ) >> 8)
+#define GET_PAD22_SEL_O (((REG32(ADR_PAD22)) & 0x00007000 ) >> 12)
+#define GET_PAD22_SEL_OE (((REG32(ADR_PAD22)) & 0x00100000 ) >> 20)
+#define GET_GPIO_TEST_3_ID (((REG32(ADR_PAD22)) & 0x10000000 ) >> 28)
+#define GET_PAD24_OE (((REG32(ADR_PAD24)) & 0x00000001 ) >> 0)
+#define GET_PAD24_PE (((REG32(ADR_PAD24)) & 0x00000002 ) >> 1)
+#define GET_PAD24_DS (((REG32(ADR_PAD24)) & 0x00000004 ) >> 2)
+#define GET_PAD24_IE (((REG32(ADR_PAD24)) & 0x00000008 ) >> 3)
+#define GET_PAD24_SEL_I (((REG32(ADR_PAD24)) & 0x00000030 ) >> 4)
+#define GET_PAD24_OD (((REG32(ADR_PAD24)) & 0x00000100 ) >> 8)
+#define GET_PAD24_SEL_O (((REG32(ADR_PAD24)) & 0x00007000 ) >> 12)
+#define GET_GPIO_TEST_4_ID (((REG32(ADR_PAD24)) & 0x10000000 ) >> 28)
+#define GET_PAD25_OE (((REG32(ADR_PAD25)) & 0x00000001 ) >> 0)
+#define GET_PAD25_PE (((REG32(ADR_PAD25)) & 0x00000002 ) >> 1)
+#define GET_PAD25_DS (((REG32(ADR_PAD25)) & 0x00000004 ) >> 2)
+#define GET_PAD25_IE (((REG32(ADR_PAD25)) & 0x00000008 ) >> 3)
+#define GET_PAD25_SEL_I (((REG32(ADR_PAD25)) & 0x00000070 ) >> 4)
+#define GET_PAD25_OD (((REG32(ADR_PAD25)) & 0x00000100 ) >> 8)
+#define GET_PAD25_SEL_O (((REG32(ADR_PAD25)) & 0x00007000 ) >> 12)
+#define GET_PAD25_SEL_OE (((REG32(ADR_PAD25)) & 0x00100000 ) >> 20)
+#define GET_STRAP1 (((REG32(ADR_PAD25)) & 0x08000000 ) >> 27)
+#define GET_GPIO_1_ID (((REG32(ADR_PAD25)) & 0x10000000 ) >> 28)
+#define GET_PAD27_OE (((REG32(ADR_PAD27)) & 0x00000001 ) >> 0)
+#define GET_PAD27_PE (((REG32(ADR_PAD27)) & 0x00000002 ) >> 1)
+#define GET_PAD27_DS (((REG32(ADR_PAD27)) & 0x00000004 ) >> 2)
+#define GET_PAD27_IE (((REG32(ADR_PAD27)) & 0x00000008 ) >> 3)
+#define GET_PAD27_SEL_I (((REG32(ADR_PAD27)) & 0x00000070 ) >> 4)
+#define GET_PAD27_OD (((REG32(ADR_PAD27)) & 0x00000100 ) >> 8)
+#define GET_PAD27_SEL_O (((REG32(ADR_PAD27)) & 0x00007000 ) >> 12)
+#define GET_GPIO_2_ID (((REG32(ADR_PAD27)) & 0x10000000 ) >> 28)
+#define GET_PAD28_OE (((REG32(ADR_PAD28)) & 0x00000001 ) >> 0)
+#define GET_PAD28_PE (((REG32(ADR_PAD28)) & 0x00000002 ) >> 1)
+#define GET_PAD28_DS (((REG32(ADR_PAD28)) & 0x00000004 ) >> 2)
+#define GET_PAD28_IE (((REG32(ADR_PAD28)) & 0x00000008 ) >> 3)
+#define GET_PAD28_SEL_I (((REG32(ADR_PAD28)) & 0x00000070 ) >> 4)
+#define GET_PAD28_OD (((REG32(ADR_PAD28)) & 0x00000100 ) >> 8)
+#define GET_PAD28_SEL_O (((REG32(ADR_PAD28)) & 0x0000f000 ) >> 12)
+#define GET_PAD28_SEL_OE (((REG32(ADR_PAD28)) & 0x00100000 ) >> 20)
+#define GET_GPIO_3_ID (((REG32(ADR_PAD28)) & 0x10000000 ) >> 28)
+#define GET_PAD29_OE (((REG32(ADR_PAD29)) & 0x00000001 ) >> 0)
+#define GET_PAD29_PE (((REG32(ADR_PAD29)) & 0x00000002 ) >> 1)
+#define GET_PAD29_DS (((REG32(ADR_PAD29)) & 0x00000004 ) >> 2)
+#define GET_PAD29_IE (((REG32(ADR_PAD29)) & 0x00000008 ) >> 3)
+#define GET_PAD29_SEL_I (((REG32(ADR_PAD29)) & 0x00000070 ) >> 4)
+#define GET_PAD29_OD (((REG32(ADR_PAD29)) & 0x00000100 ) >> 8)
+#define GET_PAD29_SEL_O (((REG32(ADR_PAD29)) & 0x00007000 ) >> 12)
+#define GET_GPIO_TEST_5_ID (((REG32(ADR_PAD29)) & 0x10000000 ) >> 28)
+#define GET_PAD30_OE (((REG32(ADR_PAD30)) & 0x00000001 ) >> 0)
+#define GET_PAD30_PE (((REG32(ADR_PAD30)) & 0x00000002 ) >> 1)
+#define GET_PAD30_DS (((REG32(ADR_PAD30)) & 0x00000004 ) >> 2)
+#define GET_PAD30_IE (((REG32(ADR_PAD30)) & 0x00000008 ) >> 3)
+#define GET_PAD30_SEL_I (((REG32(ADR_PAD30)) & 0x00000030 ) >> 4)
+#define GET_PAD30_OD (((REG32(ADR_PAD30)) & 0x00000100 ) >> 8)
+#define GET_PAD30_SEL_O (((REG32(ADR_PAD30)) & 0x00003000 ) >> 12)
+#define GET_TEST_6_ID (((REG32(ADR_PAD30)) & 0x10000000 ) >> 28)
+#define GET_PAD31_OE (((REG32(ADR_PAD31)) & 0x00000001 ) >> 0)
+#define GET_PAD31_PE (((REG32(ADR_PAD31)) & 0x00000002 ) >> 1)
+#define GET_PAD31_DS (((REG32(ADR_PAD31)) & 0x00000004 ) >> 2)
+#define GET_PAD31_IE (((REG32(ADR_PAD31)) & 0x00000008 ) >> 3)
+#define GET_PAD31_SEL_I (((REG32(ADR_PAD31)) & 0x00000030 ) >> 4)
+#define GET_PAD31_OD (((REG32(ADR_PAD31)) & 0x00000100 ) >> 8)
+#define GET_PAD31_SEL_O (((REG32(ADR_PAD31)) & 0x00003000 ) >> 12)
+#define GET_TEST_7_ID (((REG32(ADR_PAD31)) & 0x10000000 ) >> 28)
+#define GET_PAD32_OE (((REG32(ADR_PAD32)) & 0x00000001 ) >> 0)
+#define GET_PAD32_PE (((REG32(ADR_PAD32)) & 0x00000002 ) >> 1)
+#define GET_PAD32_DS (((REG32(ADR_PAD32)) & 0x00000004 ) >> 2)
+#define GET_PAD32_IE (((REG32(ADR_PAD32)) & 0x00000008 ) >> 3)
+#define GET_PAD32_SEL_I (((REG32(ADR_PAD32)) & 0x00000030 ) >> 4)
+#define GET_PAD32_OD (((REG32(ADR_PAD32)) & 0x00000100 ) >> 8)
+#define GET_PAD32_SEL_O (((REG32(ADR_PAD32)) & 0x00003000 ) >> 12)
+#define GET_TEST_8_ID (((REG32(ADR_PAD32)) & 0x10000000 ) >> 28)
+#define GET_PAD33_OE (((REG32(ADR_PAD33)) & 0x00000001 ) >> 0)
+#define GET_PAD33_PE (((REG32(ADR_PAD33)) & 0x00000002 ) >> 1)
+#define GET_PAD33_DS (((REG32(ADR_PAD33)) & 0x00000004 ) >> 2)
+#define GET_PAD33_IE (((REG32(ADR_PAD33)) & 0x00000008 ) >> 3)
+#define GET_PAD33_SEL_I (((REG32(ADR_PAD33)) & 0x00000030 ) >> 4)
+#define GET_PAD33_OD (((REG32(ADR_PAD33)) & 0x00000100 ) >> 8)
+#define GET_PAD33_SEL_O (((REG32(ADR_PAD33)) & 0x00003000 ) >> 12)
+#define GET_TEST_9_ID (((REG32(ADR_PAD33)) & 0x10000000 ) >> 28)
+#define GET_PAD34_OE (((REG32(ADR_PAD34)) & 0x00000001 ) >> 0)
+#define GET_PAD34_PE (((REG32(ADR_PAD34)) & 0x00000002 ) >> 1)
+#define GET_PAD34_DS (((REG32(ADR_PAD34)) & 0x00000004 ) >> 2)
+#define GET_PAD34_IE (((REG32(ADR_PAD34)) & 0x00000008 ) >> 3)
+#define GET_PAD34_SEL_I (((REG32(ADR_PAD34)) & 0x00000030 ) >> 4)
+#define GET_PAD34_OD (((REG32(ADR_PAD34)) & 0x00000100 ) >> 8)
+#define GET_PAD34_SEL_O (((REG32(ADR_PAD34)) & 0x00003000 ) >> 12)
+#define GET_TEST_10_ID (((REG32(ADR_PAD34)) & 0x10000000 ) >> 28)
+#define GET_PAD42_OE (((REG32(ADR_PAD42)) & 0x00000001 ) >> 0)
+#define GET_PAD42_PE (((REG32(ADR_PAD42)) & 0x00000002 ) >> 1)
+#define GET_PAD42_DS (((REG32(ADR_PAD42)) & 0x00000004 ) >> 2)
+#define GET_PAD42_IE (((REG32(ADR_PAD42)) & 0x00000008 ) >> 3)
+#define GET_PAD42_SEL_I (((REG32(ADR_PAD42)) & 0x00000030 ) >> 4)
+#define GET_PAD42_OD (((REG32(ADR_PAD42)) & 0x00000100 ) >> 8)
+#define GET_PAD42_SEL_O (((REG32(ADR_PAD42)) & 0x00001000 ) >> 12)
+#define GET_TEST_11_ID (((REG32(ADR_PAD42)) & 0x10000000 ) >> 28)
+#define GET_PAD43_OE (((REG32(ADR_PAD43)) & 0x00000001 ) >> 0)
+#define GET_PAD43_PE (((REG32(ADR_PAD43)) & 0x00000002 ) >> 1)
+#define GET_PAD43_DS (((REG32(ADR_PAD43)) & 0x00000004 ) >> 2)
+#define GET_PAD43_IE (((REG32(ADR_PAD43)) & 0x00000008 ) >> 3)
+#define GET_PAD43_SEL_I (((REG32(ADR_PAD43)) & 0x00000030 ) >> 4)
+#define GET_PAD43_OD (((REG32(ADR_PAD43)) & 0x00000100 ) >> 8)
+#define GET_PAD43_SEL_O (((REG32(ADR_PAD43)) & 0x00001000 ) >> 12)
+#define GET_TEST_12_ID (((REG32(ADR_PAD43)) & 0x10000000 ) >> 28)
+#define GET_PAD44_OE (((REG32(ADR_PAD44)) & 0x00000001 ) >> 0)
+#define GET_PAD44_PE (((REG32(ADR_PAD44)) & 0x00000002 ) >> 1)
+#define GET_PAD44_DS (((REG32(ADR_PAD44)) & 0x00000004 ) >> 2)
+#define GET_PAD44_IE (((REG32(ADR_PAD44)) & 0x00000008 ) >> 3)
+#define GET_PAD44_SEL_I (((REG32(ADR_PAD44)) & 0x00000030 ) >> 4)
+#define GET_PAD44_OD (((REG32(ADR_PAD44)) & 0x00000100 ) >> 8)
+#define GET_PAD44_SEL_O (((REG32(ADR_PAD44)) & 0x00003000 ) >> 12)
+#define GET_TEST_13_ID (((REG32(ADR_PAD44)) & 0x10000000 ) >> 28)
+#define GET_PAD45_OE (((REG32(ADR_PAD45)) & 0x00000001 ) >> 0)
+#define GET_PAD45_PE (((REG32(ADR_PAD45)) & 0x00000002 ) >> 1)
+#define GET_PAD45_DS (((REG32(ADR_PAD45)) & 0x00000004 ) >> 2)
+#define GET_PAD45_IE (((REG32(ADR_PAD45)) & 0x00000008 ) >> 3)
+#define GET_PAD45_SEL_I (((REG32(ADR_PAD45)) & 0x00000030 ) >> 4)
+#define GET_PAD45_OD (((REG32(ADR_PAD45)) & 0x00000100 ) >> 8)
+#define GET_PAD45_SEL_O (((REG32(ADR_PAD45)) & 0x00003000 ) >> 12)
+#define GET_TEST_14_ID (((REG32(ADR_PAD45)) & 0x10000000 ) >> 28)
+#define GET_PAD46_OE (((REG32(ADR_PAD46)) & 0x00000001 ) >> 0)
+#define GET_PAD46_PE (((REG32(ADR_PAD46)) & 0x00000002 ) >> 1)
+#define GET_PAD46_DS (((REG32(ADR_PAD46)) & 0x00000004 ) >> 2)
+#define GET_PAD46_IE (((REG32(ADR_PAD46)) & 0x00000008 ) >> 3)
+#define GET_PAD46_SEL_I (((REG32(ADR_PAD46)) & 0x00000030 ) >> 4)
+#define GET_PAD46_OD (((REG32(ADR_PAD46)) & 0x00000100 ) >> 8)
+#define GET_PAD46_SEL_O (((REG32(ADR_PAD46)) & 0x00003000 ) >> 12)
+#define GET_TEST_15_ID (((REG32(ADR_PAD46)) & 0x10000000 ) >> 28)
+#define GET_PAD47_OE (((REG32(ADR_PAD47)) & 0x00000001 ) >> 0)
+#define GET_PAD47_PE (((REG32(ADR_PAD47)) & 0x00000002 ) >> 1)
+#define GET_PAD47_DS (((REG32(ADR_PAD47)) & 0x00000004 ) >> 2)
+#define GET_PAD47_SEL_I (((REG32(ADR_PAD47)) & 0x00000030 ) >> 4)
+#define GET_PAD47_OD (((REG32(ADR_PAD47)) & 0x00000100 ) >> 8)
+#define GET_PAD47_SEL_O (((REG32(ADR_PAD47)) & 0x00003000 ) >> 12)
+#define GET_PAD47_SEL_OE (((REG32(ADR_PAD47)) & 0x00100000 ) >> 20)
+#define GET_GPIO_9_ID (((REG32(ADR_PAD47)) & 0x10000000 ) >> 28)
+#define GET_PAD48_OE (((REG32(ADR_PAD48)) & 0x00000001 ) >> 0)
+#define GET_PAD48_PE (((REG32(ADR_PAD48)) & 0x00000002 ) >> 1)
+#define GET_PAD48_DS (((REG32(ADR_PAD48)) & 0x00000004 ) >> 2)
+#define GET_PAD48_IE (((REG32(ADR_PAD48)) & 0x00000008 ) >> 3)
+#define GET_PAD48_SEL_I (((REG32(ADR_PAD48)) & 0x00000070 ) >> 4)
+#define GET_PAD48_OD (((REG32(ADR_PAD48)) & 0x00000100 ) >> 8)
+#define GET_PAD48_PE_SEL (((REG32(ADR_PAD48)) & 0x00000800 ) >> 11)
+#define GET_PAD48_SEL_O (((REG32(ADR_PAD48)) & 0x00003000 ) >> 12)
+#define GET_PAD48_SEL_OE (((REG32(ADR_PAD48)) & 0x00100000 ) >> 20)
+#define GET_GPIO_10_ID (((REG32(ADR_PAD48)) & 0x10000000 ) >> 28)
+#define GET_PAD49_OE (((REG32(ADR_PAD49)) & 0x00000001 ) >> 0)
+#define GET_PAD49_PE (((REG32(ADR_PAD49)) & 0x00000002 ) >> 1)
+#define GET_PAD49_DS (((REG32(ADR_PAD49)) & 0x00000004 ) >> 2)
+#define GET_PAD49_IE (((REG32(ADR_PAD49)) & 0x00000008 ) >> 3)
+#define GET_PAD49_SEL_I (((REG32(ADR_PAD49)) & 0x00000070 ) >> 4)
+#define GET_PAD49_OD (((REG32(ADR_PAD49)) & 0x00000100 ) >> 8)
+#define GET_PAD49_SEL_O (((REG32(ADR_PAD49)) & 0x00003000 ) >> 12)
+#define GET_PAD49_SEL_OE (((REG32(ADR_PAD49)) & 0x00100000 ) >> 20)
+#define GET_GPIO_11_ID (((REG32(ADR_PAD49)) & 0x10000000 ) >> 28)
+#define GET_PAD50_OE (((REG32(ADR_PAD50)) & 0x00000001 ) >> 0)
+#define GET_PAD50_PE (((REG32(ADR_PAD50)) & 0x00000002 ) >> 1)
+#define GET_PAD50_DS (((REG32(ADR_PAD50)) & 0x00000004 ) >> 2)
+#define GET_PAD50_IE (((REG32(ADR_PAD50)) & 0x00000008 ) >> 3)
+#define GET_PAD50_SEL_I (((REG32(ADR_PAD50)) & 0x00000070 ) >> 4)
+#define GET_PAD50_OD (((REG32(ADR_PAD50)) & 0x00000100 ) >> 8)
+#define GET_PAD50_SEL_O (((REG32(ADR_PAD50)) & 0x00003000 ) >> 12)
+#define GET_PAD50_SEL_OE (((REG32(ADR_PAD50)) & 0x00100000 ) >> 20)
+#define GET_GPIO_12_ID (((REG32(ADR_PAD50)) & 0x10000000 ) >> 28)
+#define GET_PAD51_OE (((REG32(ADR_PAD51)) & 0x00000001 ) >> 0)
+#define GET_PAD51_PE (((REG32(ADR_PAD51)) & 0x00000002 ) >> 1)
+#define GET_PAD51_DS (((REG32(ADR_PAD51)) & 0x00000004 ) >> 2)
+#define GET_PAD51_IE (((REG32(ADR_PAD51)) & 0x00000008 ) >> 3)
+#define GET_PAD51_SEL_I (((REG32(ADR_PAD51)) & 0x00000030 ) >> 4)
+#define GET_PAD51_OD (((REG32(ADR_PAD51)) & 0x00000100 ) >> 8)
+#define GET_PAD51_SEL_O (((REG32(ADR_PAD51)) & 0x00001000 ) >> 12)
+#define GET_PAD51_SEL_OE (((REG32(ADR_PAD51)) & 0x00100000 ) >> 20)
+#define GET_GPIO_13_ID (((REG32(ADR_PAD51)) & 0x10000000 ) >> 28)
+#define GET_PAD52_OE (((REG32(ADR_PAD52)) & 0x00000001 ) >> 0)
+#define GET_PAD52_PE (((REG32(ADR_PAD52)) & 0x00000002 ) >> 1)
+#define GET_PAD52_DS (((REG32(ADR_PAD52)) & 0x00000004 ) >> 2)
+#define GET_PAD52_SEL_I (((REG32(ADR_PAD52)) & 0x00000030 ) >> 4)
+#define GET_PAD52_OD (((REG32(ADR_PAD52)) & 0x00000100 ) >> 8)
+#define GET_PAD52_SEL_O (((REG32(ADR_PAD52)) & 0x00001000 ) >> 12)
+#define GET_PAD52_SEL_OE (((REG32(ADR_PAD52)) & 0x00100000 ) >> 20)
+#define GET_GPIO_14_ID (((REG32(ADR_PAD52)) & 0x10000000 ) >> 28)
+#define GET_PAD53_OE (((REG32(ADR_PAD53)) & 0x00000001 ) >> 0)
+#define GET_PAD53_PE (((REG32(ADR_PAD53)) & 0x00000002 ) >> 1)
+#define GET_PAD53_DS (((REG32(ADR_PAD53)) & 0x00000004 ) >> 2)
+#define GET_PAD53_IE (((REG32(ADR_PAD53)) & 0x00000008 ) >> 3)
+#define GET_PAD53_SEL_I (((REG32(ADR_PAD53)) & 0x00000030 ) >> 4)
+#define GET_PAD53_OD (((REG32(ADR_PAD53)) & 0x00000100 ) >> 8)
+#define GET_PAD53_SEL_O (((REG32(ADR_PAD53)) & 0x00001000 ) >> 12)
+#define GET_JTAG_TMS_ID (((REG32(ADR_PAD53)) & 0x10000000 ) >> 28)
+#define GET_PAD54_OE (((REG32(ADR_PAD54)) & 0x00000001 ) >> 0)
+#define GET_PAD54_PE (((REG32(ADR_PAD54)) & 0x00000002 ) >> 1)
+#define GET_PAD54_DS (((REG32(ADR_PAD54)) & 0x00000004 ) >> 2)
+#define GET_PAD54_OD (((REG32(ADR_PAD54)) & 0x00000100 ) >> 8)
+#define GET_PAD54_SEL_O (((REG32(ADR_PAD54)) & 0x00003000 ) >> 12)
+#define GET_JTAG_TCK_ID (((REG32(ADR_PAD54)) & 0x10000000 ) >> 28)
+#define GET_PAD56_PE (((REG32(ADR_PAD56)) & 0x00000002 ) >> 1)
+#define GET_PAD56_DS (((REG32(ADR_PAD56)) & 0x00000004 ) >> 2)
+#define GET_PAD56_SEL_I (((REG32(ADR_PAD56)) & 0x00000010 ) >> 4)
+#define GET_PAD56_OD (((REG32(ADR_PAD56)) & 0x00000100 ) >> 8)
+#define GET_JTAG_TDI_ID (((REG32(ADR_PAD56)) & 0x10000000 ) >> 28)
+#define GET_PAD57_OE (((REG32(ADR_PAD57)) & 0x00000001 ) >> 0)
+#define GET_PAD57_PE (((REG32(ADR_PAD57)) & 0x00000002 ) >> 1)
+#define GET_PAD57_DS (((REG32(ADR_PAD57)) & 0x00000004 ) >> 2)
+#define GET_PAD57_IE (((REG32(ADR_PAD57)) & 0x00000008 ) >> 3)
+#define GET_PAD57_SEL_I (((REG32(ADR_PAD57)) & 0x00000030 ) >> 4)
+#define GET_PAD57_OD (((REG32(ADR_PAD57)) & 0x00000100 ) >> 8)
+#define GET_PAD57_SEL_O (((REG32(ADR_PAD57)) & 0x00003000 ) >> 12)
+#define GET_PAD57_SEL_OE (((REG32(ADR_PAD57)) & 0x00100000 ) >> 20)
+#define GET_JTAG_TDO_ID (((REG32(ADR_PAD57)) & 0x10000000 ) >> 28)
+#define GET_PAD58_OE (((REG32(ADR_PAD58)) & 0x00000001 ) >> 0)
+#define GET_PAD58_PE (((REG32(ADR_PAD58)) & 0x00000002 ) >> 1)
+#define GET_PAD58_DS (((REG32(ADR_PAD58)) & 0x00000004 ) >> 2)
+#define GET_PAD58_IE (((REG32(ADR_PAD58)) & 0x00000008 ) >> 3)
+#define GET_PAD58_SEL_I (((REG32(ADR_PAD58)) & 0x00000030 ) >> 4)
+#define GET_PAD58_OD (((REG32(ADR_PAD58)) & 0x00000100 ) >> 8)
+#define GET_PAD58_SEL_O (((REG32(ADR_PAD58)) & 0x00001000 ) >> 12)
+#define GET_TEST_16_ID (((REG32(ADR_PAD58)) & 0x10000000 ) >> 28)
+#define GET_PAD59_OE (((REG32(ADR_PAD59)) & 0x00000001 ) >> 0)
+#define GET_PAD59_PE (((REG32(ADR_PAD59)) & 0x00000002 ) >> 1)
+#define GET_PAD59_DS (((REG32(ADR_PAD59)) & 0x00000004 ) >> 2)
+#define GET_PAD59_IE (((REG32(ADR_PAD59)) & 0x00000008 ) >> 3)
+#define GET_PAD59_SEL_I (((REG32(ADR_PAD59)) & 0x00000030 ) >> 4)
+#define GET_PAD59_OD (((REG32(ADR_PAD59)) & 0x00000100 ) >> 8)
+#define GET_PAD59_SEL_O (((REG32(ADR_PAD59)) & 0x00001000 ) >> 12)
+#define GET_TEST_17_ID (((REG32(ADR_PAD59)) & 0x10000000 ) >> 28)
+#define GET_PAD60_OE (((REG32(ADR_PAD60)) & 0x00000001 ) >> 0)
+#define GET_PAD60_PE (((REG32(ADR_PAD60)) & 0x00000002 ) >> 1)
+#define GET_PAD60_DS (((REG32(ADR_PAD60)) & 0x00000004 ) >> 2)
+#define GET_PAD60_IE (((REG32(ADR_PAD60)) & 0x00000008 ) >> 3)
+#define GET_PAD60_SEL_I (((REG32(ADR_PAD60)) & 0x00000030 ) >> 4)
+#define GET_PAD60_OD (((REG32(ADR_PAD60)) & 0x00000100 ) >> 8)
+#define GET_PAD60_SEL_O (((REG32(ADR_PAD60)) & 0x00001000 ) >> 12)
+#define GET_TEST_18_ID (((REG32(ADR_PAD60)) & 0x10000000 ) >> 28)
+#define GET_PAD61_OE (((REG32(ADR_PAD61)) & 0x00000001 ) >> 0)
+#define GET_PAD61_PE (((REG32(ADR_PAD61)) & 0x00000002 ) >> 1)
+#define GET_PAD61_DS (((REG32(ADR_PAD61)) & 0x00000004 ) >> 2)
+#define GET_PAD61_IE (((REG32(ADR_PAD61)) & 0x00000008 ) >> 3)
+#define GET_PAD61_SEL_I (((REG32(ADR_PAD61)) & 0x00000010 ) >> 4)
+#define GET_PAD61_OD (((REG32(ADR_PAD61)) & 0x00000100 ) >> 8)
+#define GET_PAD61_SEL_O (((REG32(ADR_PAD61)) & 0x00003000 ) >> 12)
+#define GET_TEST_19_ID (((REG32(ADR_PAD61)) & 0x10000000 ) >> 28)
+#define GET_PAD62_OE (((REG32(ADR_PAD62)) & 0x00000001 ) >> 0)
+#define GET_PAD62_PE (((REG32(ADR_PAD62)) & 0x00000002 ) >> 1)
+#define GET_PAD62_DS (((REG32(ADR_PAD62)) & 0x00000004 ) >> 2)
+#define GET_PAD62_IE (((REG32(ADR_PAD62)) & 0x00000008 ) >> 3)
+#define GET_PAD62_SEL_I (((REG32(ADR_PAD62)) & 0x00000010 ) >> 4)
+#define GET_PAD62_OD (((REG32(ADR_PAD62)) & 0x00000100 ) >> 8)
+#define GET_PAD62_SEL_O (((REG32(ADR_PAD62)) & 0x00001000 ) >> 12)
+#define GET_TEST_20_ID (((REG32(ADR_PAD62)) & 0x10000000 ) >> 28)
+#define GET_PAD64_OE (((REG32(ADR_PAD64)) & 0x00000001 ) >> 0)
+#define GET_PAD64_PE (((REG32(ADR_PAD64)) & 0x00000002 ) >> 1)
+#define GET_PAD64_DS (((REG32(ADR_PAD64)) & 0x00000004 ) >> 2)
+#define GET_PAD64_IE (((REG32(ADR_PAD64)) & 0x00000008 ) >> 3)
+#define GET_PAD64_SEL_I (((REG32(ADR_PAD64)) & 0x00000070 ) >> 4)
+#define GET_PAD64_OD (((REG32(ADR_PAD64)) & 0x00000100 ) >> 8)
+#define GET_PAD64_SEL_O (((REG32(ADR_PAD64)) & 0x00003000 ) >> 12)
+#define GET_PAD64_SEL_OE (((REG32(ADR_PAD64)) & 0x00100000 ) >> 20)
+#define GET_GPIO_15_IP_ID (((REG32(ADR_PAD64)) & 0x10000000 ) >> 28)
+#define GET_PAD65_OE (((REG32(ADR_PAD65)) & 0x00000001 ) >> 0)
+#define GET_PAD65_PE (((REG32(ADR_PAD65)) & 0x00000002 ) >> 1)
+#define GET_PAD65_DS (((REG32(ADR_PAD65)) & 0x00000004 ) >> 2)
+#define GET_PAD65_IE (((REG32(ADR_PAD65)) & 0x00000008 ) >> 3)
+#define GET_PAD65_SEL_I (((REG32(ADR_PAD65)) & 0x00000070 ) >> 4)
+#define GET_PAD65_OD (((REG32(ADR_PAD65)) & 0x00000100 ) >> 8)
+#define GET_PAD65_SEL_O (((REG32(ADR_PAD65)) & 0x00001000 ) >> 12)
+#define GET_GPIO_TEST_7_IN_ID (((REG32(ADR_PAD65)) & 0x10000000 ) >> 28)
+#define GET_PAD66_OE (((REG32(ADR_PAD66)) & 0x00000001 ) >> 0)
+#define GET_PAD66_PE (((REG32(ADR_PAD66)) & 0x00000002 ) >> 1)
+#define GET_PAD66_DS (((REG32(ADR_PAD66)) & 0x00000004 ) >> 2)
+#define GET_PAD66_IE (((REG32(ADR_PAD66)) & 0x00000008 ) >> 3)
+#define GET_PAD66_SEL_I (((REG32(ADR_PAD66)) & 0x00000030 ) >> 4)
+#define GET_PAD66_OD (((REG32(ADR_PAD66)) & 0x00000100 ) >> 8)
+#define GET_PAD66_SEL_O (((REG32(ADR_PAD66)) & 0x00003000 ) >> 12)
+#define GET_GPIO_17_QP_ID (((REG32(ADR_PAD66)) & 0x10000000 ) >> 28)
+#define GET_PAD68_OE (((REG32(ADR_PAD68)) & 0x00000001 ) >> 0)
+#define GET_PAD68_PE (((REG32(ADR_PAD68)) & 0x00000002 ) >> 1)
+#define GET_PAD68_DS (((REG32(ADR_PAD68)) & 0x00000004 ) >> 2)
+#define GET_PAD68_IE (((REG32(ADR_PAD68)) & 0x00000008 ) >> 3)
+#define GET_PAD68_OD (((REG32(ADR_PAD68)) & 0x00000100 ) >> 8)
+#define GET_PAD68_SEL_O (((REG32(ADR_PAD68)) & 0x00001000 ) >> 12)
+#define GET_GPIO_19_ID (((REG32(ADR_PAD68)) & 0x10000000 ) >> 28)
+#define GET_PAD67_OE (((REG32(ADR_PAD67)) & 0x00000001 ) >> 0)
+#define GET_PAD67_PE (((REG32(ADR_PAD67)) & 0x00000002 ) >> 1)
+#define GET_PAD67_DS (((REG32(ADR_PAD67)) & 0x00000004 ) >> 2)
+#define GET_PAD67_IE (((REG32(ADR_PAD67)) & 0x00000008 ) >> 3)
+#define GET_PAD67_SEL_I (((REG32(ADR_PAD67)) & 0x00000070 ) >> 4)
+#define GET_PAD67_OD (((REG32(ADR_PAD67)) & 0x00000100 ) >> 8)
+#define GET_PAD67_SEL_O (((REG32(ADR_PAD67)) & 0x00003000 ) >> 12)
+#define GET_GPIO_TEST_8_QN_ID (((REG32(ADR_PAD67)) & 0x10000000 ) >> 28)
+#define GET_PAD69_OE (((REG32(ADR_PAD69)) & 0x00000001 ) >> 0)
+#define GET_PAD69_PE (((REG32(ADR_PAD69)) & 0x00000002 ) >> 1)
+#define GET_PAD69_DS (((REG32(ADR_PAD69)) & 0x00000004 ) >> 2)
+#define GET_PAD69_IE (((REG32(ADR_PAD69)) & 0x00000008 ) >> 3)
+#define GET_PAD69_SEL_I (((REG32(ADR_PAD69)) & 0x00000030 ) >> 4)
+#define GET_PAD69_OD (((REG32(ADR_PAD69)) & 0x00000100 ) >> 8)
+#define GET_PAD69_SEL_O (((REG32(ADR_PAD69)) & 0x00001000 ) >> 12)
+#define GET_STRAP2 (((REG32(ADR_PAD69)) & 0x08000000 ) >> 27)
+#define GET_GPIO_20_ID (((REG32(ADR_PAD69)) & 0x10000000 ) >> 28)
+#define GET_PAD70_OE (((REG32(ADR_PAD70)) & 0x00000001 ) >> 0)
+#define GET_PAD70_PE (((REG32(ADR_PAD70)) & 0x00000002 ) >> 1)
+#define GET_PAD70_DS (((REG32(ADR_PAD70)) & 0x00000004 ) >> 2)
+#define GET_PAD70_IE (((REG32(ADR_PAD70)) & 0x00000008 ) >> 3)
+#define GET_PAD70_SEL_I (((REG32(ADR_PAD70)) & 0x00000030 ) >> 4)
+#define GET_PAD70_OD (((REG32(ADR_PAD70)) & 0x00000100 ) >> 8)
+#define GET_PAD70_SEL_O (((REG32(ADR_PAD70)) & 0x00007000 ) >> 12)
+#define GET_GPIO_21_ID (((REG32(ADR_PAD70)) & 0x10000000 ) >> 28)
+#define GET_PAD231_OE (((REG32(ADR_PAD231)) & 0x00000001 ) >> 0)
+#define GET_PAD231_PE (((REG32(ADR_PAD231)) & 0x00000002 ) >> 1)
+#define GET_PAD231_DS (((REG32(ADR_PAD231)) & 0x00000004 ) >> 2)
+#define GET_PAD231_IE (((REG32(ADR_PAD231)) & 0x00000008 ) >> 3)
+#define GET_PAD231_OD (((REG32(ADR_PAD231)) & 0x00000100 ) >> 8)
+#define GET_PIN_40_OR_56_ID (((REG32(ADR_PAD231)) & 0x10000000 ) >> 28)
+#define GET_MP_PHY2RX_DATA__0_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000001 ) >> 0)
+#define GET_MP_PHY2RX_DATA__1_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000002 ) >> 1)
+#define GET_MP_TX_FF_RPTR__1_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000004 ) >> 2)
+#define GET_MP_RX_FF_WPTR__2_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000008 ) >> 3)
+#define GET_MP_RX_FF_WPTR__1_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000010 ) >> 4)
+#define GET_MP_RX_FF_WPTR__0_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000020 ) >> 5)
+#define GET_MP_PHY2RX_DATA__2_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000040 ) >> 6)
+#define GET_MP_PHY2RX_DATA__4_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000080 ) >> 7)
+#define GET_I2CM_SDA_ID_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000300 ) >> 8)
+#define GET_CRYSTAL_OUT_REQ_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000400 ) >> 10)
+#define GET_MP_PHY2RX_DATA__5_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000800 ) >> 11)
+#define GET_MP_PHY2RX_DATA__3_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00001000 ) >> 12)
+#define GET_UART_RXD_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00006000 ) >> 13)
+#define GET_MP_PHY2RX_DATA__6_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00008000 ) >> 15)
+#define GET_DAT_UART_NCTS_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00010000 ) >> 16)
+#define GET_GPIO_LOG_STOP_SEL (((REG32(ADR_PIN_SEL_0)) & 0x000e0000 ) >> 17)
+#define GET_MP_TX_FF_RPTR__0_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00100000 ) >> 20)
+#define GET_MP_PHY_RX_WRST_N_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00200000 ) >> 21)
+#define GET_EXT_32K_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00c00000 ) >> 22)
+#define GET_MP_PHY2RX_DATA__7_SEL (((REG32(ADR_PIN_SEL_0)) & 0x01000000 ) >> 24)
+#define GET_MP_TX_FF_RPTR__2_SEL (((REG32(ADR_PIN_SEL_0)) & 0x02000000 ) >> 25)
+#define GET_PMUINT_WAKE_SEL (((REG32(ADR_PIN_SEL_0)) & 0x1c000000 ) >> 26)
+#define GET_I2CM_SCL_ID_SEL (((REG32(ADR_PIN_SEL_0)) & 0x20000000 ) >> 29)
+#define GET_MP_MRX_RX_EN_SEL (((REG32(ADR_PIN_SEL_0)) & 0x40000000 ) >> 30)
+#define GET_DAT_UART_RXD_SEL_0 (((REG32(ADR_PIN_SEL_0)) & 0x80000000 ) >> 31)
+#define GET_DAT_UART_RXD_SEL_1 (((REG32(ADR_PIN_SEL_1)) & 0x00000001 ) >> 0)
+#define GET_SPI_DI_SEL (((REG32(ADR_PIN_SEL_1)) & 0x00000002 ) >> 1)
+#define GET_IO_PORT_REG (((REG32(ADR_IO_PORT_REG)) & 0x0001ffff ) >> 0)
+#define GET_MASK_RX_INT (((REG32(ADR_INT_MASK_REG)) & 0x00000001 ) >> 0)
+#define GET_MASK_TX_INT (((REG32(ADR_INT_MASK_REG)) & 0x00000002 ) >> 1)
+#define GET_MASK_SOC_SYSTEM_INT (((REG32(ADR_INT_MASK_REG)) & 0x00000004 ) >> 2)
+#define GET_EDCA0_LOW_THR_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000008 ) >> 3)
+#define GET_EDCA1_LOW_THR_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000010 ) >> 4)
+#define GET_EDCA2_LOW_THR_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000020 ) >> 5)
+#define GET_EDCA3_LOW_THR_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000040 ) >> 6)
+#define GET_TX_LIMIT_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000080 ) >> 7)
+#define GET_RX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000001 ) >> 0)
+#define GET_TX_COMPLETE_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000002 ) >> 1)
+#define GET_SOC_SYSTEM_INT_STATUS (((REG32(ADR_INT_STATUS_REG)) & 0x00000004 ) >> 2)
+#define GET_EDCA0_LOW_THR_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000008 ) >> 3)
+#define GET_EDCA1_LOW_THR_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000010 ) >> 4)
+#define GET_EDCA2_LOW_THR_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000020 ) >> 5)
+#define GET_EDCA3_LOW_THR_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000040 ) >> 6)
+#define GET_TX_LIMIT_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000080 ) >> 7)
+#define GET_HOST_TRIGGERED_RX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000100 ) >> 8)
+#define GET_HOST_TRIGGERED_TX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000200 ) >> 9)
+#define GET_SOC_TRIGGER_RX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000400 ) >> 10)
+#define GET_SOC_TRIGGER_TX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000800 ) >> 11)
+#define GET_RDY_FOR_TX_RX (((REG32(ADR_FN1_STATUS_REG)) & 0x00000001 ) >> 0)
+#define GET_RDY_FOR_FW_DOWNLOAD (((REG32(ADR_FN1_STATUS_REG)) & 0x00000002 ) >> 1)
+#define GET_ILLEGAL_CMD_RESP_OPTION (((REG32(ADR_FN1_STATUS_REG)) & 0x00000004 ) >> 2)
+#define GET_SDIO_TRX_DATA_SEQUENCE (((REG32(ADR_FN1_STATUS_REG)) & 0x00000008 ) >> 3)
+#define GET_GPIO_INT_TRIGGER_OPTION (((REG32(ADR_FN1_STATUS_REG)) & 0x00000010 ) >> 4)
+#define GET_TRIGGER_FUNCTION_SETTING (((REG32(ADR_FN1_STATUS_REG)) & 0x00000060 ) >> 5)
+#define GET_CMD52_ABORT_RESPONSE (((REG32(ADR_FN1_STATUS_REG)) & 0x00000080 ) >> 7)
+#define GET_RX_PACKET_LENGTH (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x0000ffff ) >> 0)
+#define GET_CARD_FW_DL_STATUS (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x00ff0000 ) >> 16)
+#define GET_TX_RX_LOOP_BACK_TEST (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x01000000 ) >> 24)
+#define GET_SDIO_LOOP_BACK_TEST (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x02000000 ) >> 25)
+#define GET_CMD52_ABORT_ACTIVE (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x10000000 ) >> 28)
+#define GET_CMD52_RESET_ACTIVE (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x20000000 ) >> 29)
+#define GET_SDIO_PARTIAL_RESET_ACTIVE (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x40000000 ) >> 30)
+#define GET_SDIO_ALL_RESE_ACTIVE (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x80000000 ) >> 31)
+#define GET_RX_PACKET_LENGTH2 (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x0000ffff ) >> 0)
+#define GET_RX_INT1 (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x00010000 ) >> 16)
+#define GET_TX_DONE (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x00020000 ) >> 17)
+#define GET_HCI_TRX_FINISH (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x00040000 ) >> 18)
+#define GET_ALLOCATE_STATUS (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x00080000 ) >> 19)
+#define GET_HCI_INPUT_FF_CNT (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x00f00000 ) >> 20)
+#define GET_HCI_OUTPUT_FF_CNT (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x1f000000 ) >> 24)
+#define GET_AHB_HANG4 (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x20000000 ) >> 29)
+#define GET_HCI_IN_QUE_EMPTY (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x40000000 ) >> 30)
+#define GET_SYSTEM_INT (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x80000000 ) >> 31)
+#define GET_CARD_RCA_REG (((REG32(ADR_CARD_RCA_REG)) & 0x0000ffff ) >> 0)
+#define GET_SDIO_FIFO_WR_THLD_REG (((REG32(ADR_SDIO_FIFO_WR_THLD_REG)) & 0x000001ff ) >> 0)
+#define GET_SDIO_FIFO_WR_LIMIT_REG (((REG32(ADR_SDIO_FIFO_WR_LIMIT_REG)) & 0x000001ff ) >> 0)
+#define GET_SDIO_TX_DATA_BATCH_SIZE_REG (((REG32(ADR_SDIO_TX_DATA_BATCH_SIZE_REG)) & 0x000001ff ) >> 0)
+#define GET_SDIO_THLD_FOR_CMD53RD_REG (((REG32(ADR_SDIO_THLD_FOR_CMD53RD_REG)) & 0x000001ff ) >> 0)
+#define GET_SDIO_RX_DATA_BATCH_SIZE_REG (((REG32(ADR_SDIO_RX_DATA_BATCH_SIZE_REG)) & 0x000001ff ) >> 0)
+#define GET_START_BYTE_VALUE (((REG32(ADR_SDIO_LOG_START_END_DATA_REG)) & 0x000000ff ) >> 0)
+#define GET_END_BYTE_VALUE (((REG32(ADR_SDIO_LOG_START_END_DATA_REG)) & 0x0000ff00 ) >> 8)
+#define GET_SDIO_BYTE_MODE_BATCH_SIZE_REG (((REG32(ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG)) & 0x000000ff ) >> 0)
+#define GET_SDIO_LAST_CMD_INDEX_REG (((REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) & 0x0000003f ) >> 0)
+#define GET_SDIO_LAST_CMD_CRC_REG (((REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) & 0x00007f00 ) >> 8)
+#define GET_SDIO_LAST_CMD_ARG_REG (((REG32(ADR_SDIO_LAST_CMD_ARG_REG)) & 0xffffffff ) >> 0)
+#define GET_SDIO_BUS_STATE_REG (((REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) & 0x0000001f ) >> 0)
+#define GET_SDIO_BUSY_LONG_CNT (((REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) & 0xffff0000 ) >> 16)
+#define GET_SDIO_CARD_STATUS_REG (((REG32(ADR_SDIO_CARD_STATUS_REG)) & 0xffffffff ) >> 0)
+#define GET_R5_RESPONSE_FLAG (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x000000ff ) >> 0)
+#define GET_RESP_OUT_EDGE (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x00000100 ) >> 8)
+#define GET_DAT_OUT_EDGE (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x00000200 ) >> 9)
+#define GET_MCU_TO_SDIO_INFO_MASK (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x00010000 ) >> 16)
+#define GET_INT_THROUGH_PIN (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x00020000 ) >> 17)
+#define GET_WRITE_DATA (((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0x000000ff ) >> 0)
+#define GET_WRITE_ADDRESS (((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0x0000ff00 ) >> 8)
+#define GET_READ_DATA (((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0x00ff0000 ) >> 16)
+#define GET_READ_ADDRESS (((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0xff000000 ) >> 24)
+#define GET_FN1_DMA_START_ADDR_REG (((REG32(ADR_FN1_DMA_START_ADDR_REG)) & 0xffffffff ) >> 0)
+#define GET_SDIO_TO_MCU_INFO (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x000000ff ) >> 0)
+#define GET_SDIO_PARTIAL_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00000100 ) >> 8)
+#define GET_SDIO_ALL_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00000200 ) >> 9)
+#define GET_PERI_MAC_ALL_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00000400 ) >> 10)
+#define GET_MAC_ALL_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00000800 ) >> 11)
+#define GET_AHB_BRIDGE_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00001000 ) >> 12)
+#define GET_IO_REG_PORT_REG (((REG32(ADR_IO_REG_PORT_REG)) & 0x0001ffff ) >> 0)
+#define GET_SDIO_FIFO_EMPTY_CNT (((REG32(ADR_SDIO_FIFO_ERROR_CNT)) & 0x0000ffff ) >> 0)
+#define GET_SDIO_FIFO_FULL_CNT (((REG32(ADR_SDIO_FIFO_ERROR_CNT)) & 0xffff0000 ) >> 16)
+#define GET_SDIO_CRC7_ERROR_CNT (((REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) & 0x0000ffff ) >> 0)
+#define GET_SDIO_CRC16_ERROR_CNT (((REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) & 0xffff0000 ) >> 16)
+#define GET_SDIO_RD_BLOCK_CNT (((REG32(ADR_SDIO_BLOCK_CNT_INFO)) & 0x000001ff ) >> 0)
+#define GET_SDIO_WR_BLOCK_CNT (((REG32(ADR_SDIO_BLOCK_CNT_INFO)) & 0x01ff0000 ) >> 16)
+#define GET_CMD52_RD_ABORT_CNT (((REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) & 0x000f0000 ) >> 16)
+#define GET_CMD52_WR_ABORT_CNT (((REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) & 0x00f00000 ) >> 20)
+#define GET_SDIO_FIFO_WR_PTR_REG (((REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) & 0x000000ff ) >> 0)
+#define GET_SDIO_FIFO_RD_PTR_REG (((REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) & 0x0000ff00 ) >> 8)
+#define GET_SDIO_READ_DATA_CTRL (((REG32(ADR_TX_TIME_OUT_READ_CTRL)) & 0x00010000 ) >> 16)
+#define GET_TX_SIZE_BEFORE_SHIFT (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x000000ff ) >> 0)
+#define GET_TX_SIZE_SHIFT_BITS (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00000700 ) >> 8)
+#define GET_SDIO_TX_ALLOC_STATE (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00001000 ) >> 12)
+#define GET_ALLOCATE_STATUS2 (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00010000 ) >> 16)
+#define GET_NO_ALLOCATE_SEND_ERROR (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00020000 ) >> 17)
+#define GET_DOUBLE_ALLOCATE_ERROR (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00040000 ) >> 18)
+#define GET_TX_DONE_STATUS (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00080000 ) >> 19)
+#define GET_AHB_HANG2 (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00100000 ) >> 20)
+#define GET_HCI_TRX_FINISH2 (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00200000 ) >> 21)
+#define GET_INTR_RX (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00400000 ) >> 22)
+#define GET_HCI_INPUT_QUEUE_FULL (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00800000 ) >> 23)
+#define GET_ALLOCATESTATUS (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000001 ) >> 0)
+#define GET_HCI_TRX_FINISH3 (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000002 ) >> 1)
+#define GET_HCI_IN_QUE_EMPTY2 (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000004 ) >> 2)
+#define GET_MTX_MNG_UPTHOLD_INT (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000008 ) >> 3)
+#define GET_EDCA0_UPTHOLD_INT (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000010 ) >> 4)
+#define GET_EDCA1_UPTHOLD_INT (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000020 ) >> 5)
+#define GET_EDCA2_UPTHOLD_INT (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000040 ) >> 6)
+#define GET_EDCA3_UPTHOLD_INT (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000080 ) >> 7)
+#define GET_TX_PAGE_REMAIN2 (((REG32(ADR_SDIO_TX_INFORM)) & 0x0000ff00 ) >> 8)
+#define GET_TX_ID_REMAIN3 (((REG32(ADR_SDIO_TX_INFORM)) & 0x007f0000 ) >> 16)
+#define GET_HCI_OUTPUT_FF_CNT_0 (((REG32(ADR_SDIO_TX_INFORM)) & 0x00800000 ) >> 23)
+#define GET_HCI_OUTPUT_FF_CNT2 (((REG32(ADR_SDIO_TX_INFORM)) & 0x0f000000 ) >> 24)
+#define GET_HCI_INPUT_FF_CNT2 (((REG32(ADR_SDIO_TX_INFORM)) & 0xf0000000 ) >> 28)
+#define GET_F1_BLOCK_SIZE_0_REG (((REG32(ADR_F1_BLOCK_SIZE_0_REG)) & 0x00000fff ) >> 0)
+#define GET_START_BYTE_VALUE2 (((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0x000000ff ) >> 0)
+#define GET_COMMAND_COUNTER (((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0x0000ff00 ) >> 8)
+#define GET_CMD_LOG_PART1 (((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0xffff0000 ) >> 16)
+#define GET_CMD_LOG_PART2 (((REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) & 0x00ffffff ) >> 0)
+#define GET_END_BYTE_VALUE2 (((REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) & 0xff000000 ) >> 24)
+#define GET_RX_PACKET_LENGTH3 (((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0x0000ffff ) >> 0)
+#define GET_RX_INT3 (((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0x00010000 ) >> 16)
+#define GET_TX_ID_REMAIN2 (((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0x00fe0000 ) >> 17)
+#define GET_TX_PAGE_REMAIN3 (((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0xff000000 ) >> 24)
+#define GET_CCCR_00H_REG (((REG32(ADR_CCCR_00H_REG)) & 0x000000ff ) >> 0)
+#define GET_CCCR_02H_REG (((REG32(ADR_CCCR_00H_REG)) & 0x00ff0000 ) >> 16)
+#define GET_CCCR_03H_REG (((REG32(ADR_CCCR_00H_REG)) & 0xff000000 ) >> 24)
+#define GET_CCCR_04H_REG (((REG32(ADR_CCCR_04H_REG)) & 0x000000ff ) >> 0)
+#define GET_CCCR_05H_REG (((REG32(ADR_CCCR_04H_REG)) & 0x0000ff00 ) >> 8)
+#define GET_CCCR_06H_REG (((REG32(ADR_CCCR_04H_REG)) & 0x000f0000 ) >> 16)
+#define GET_CCCR_07H_REG (((REG32(ADR_CCCR_04H_REG)) & 0xff000000 ) >> 24)
+#define GET_SUPPORT_DIRECT_COMMAND_SDIO (((REG32(ADR_CCCR_08H_REG)) & 0x00000001 ) >> 0)
+#define GET_SUPPORT_MULTIPLE_BLOCK_TRANSFER (((REG32(ADR_CCCR_08H_REG)) & 0x00000002 ) >> 1)
+#define GET_SUPPORT_READ_WAIT (((REG32(ADR_CCCR_08H_REG)) & 0x00000004 ) >> 2)
+#define GET_SUPPORT_BUS_CONTROL (((REG32(ADR_CCCR_08H_REG)) & 0x00000008 ) >> 3)
+#define GET_SUPPORT_BLOCK_GAP_INTERRUPT (((REG32(ADR_CCCR_08H_REG)) & 0x00000010 ) >> 4)
+#define GET_ENABLE_BLOCK_GAP_INTERRUPT (((REG32(ADR_CCCR_08H_REG)) & 0x00000020 ) >> 5)
+#define GET_LOW_SPEED_CARD (((REG32(ADR_CCCR_08H_REG)) & 0x00000040 ) >> 6)
+#define GET_LOW_SPEED_CARD_4BIT (((REG32(ADR_CCCR_08H_REG)) & 0x00000080 ) >> 7)
+#define GET_COMMON_CIS_PONTER (((REG32(ADR_CCCR_08H_REG)) & 0x01ffff00 ) >> 8)
+#define GET_SUPPORT_HIGH_SPEED (((REG32(ADR_CCCR_13H_REG)) & 0x01000000 ) >> 24)
+#define GET_BSS (((REG32(ADR_CCCR_13H_REG)) & 0x0e000000 ) >> 25)
+#define GET_FBR_100H_REG (((REG32(ADR_FBR_100H_REG)) & 0x0000000f ) >> 0)
+#define GET_CSASUPPORT (((REG32(ADR_FBR_100H_REG)) & 0x00000040 ) >> 6)
+#define GET_ENABLECSA (((REG32(ADR_FBR_100H_REG)) & 0x00000080 ) >> 7)
+#define GET_FBR_101H_REG (((REG32(ADR_FBR_100H_REG)) & 0x0000ff00 ) >> 8)
+#define GET_FBR_109H_REG (((REG32(ADR_FBR_109H_REG)) & 0x01ffff00 ) >> 8)
+#define GET_F0_CIS_CONTENT_REG_31_0 (((REG32(ADR_F0_CIS_CONTENT_REG_0)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_63_32 (((REG32(ADR_F0_CIS_CONTENT_REG_1)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_95_64 (((REG32(ADR_F0_CIS_CONTENT_REG_2)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_127_96 (((REG32(ADR_F0_CIS_CONTENT_REG_3)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_159_128 (((REG32(ADR_F0_CIS_CONTENT_REG_4)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_191_160 (((REG32(ADR_F0_CIS_CONTENT_REG_5)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_223_192 (((REG32(ADR_F0_CIS_CONTENT_REG_6)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_255_224 (((REG32(ADR_F0_CIS_CONTENT_REG_7)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_287_256 (((REG32(ADR_F0_CIS_CONTENT_REG_8)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_319_288 (((REG32(ADR_F0_CIS_CONTENT_REG_9)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_351_320 (((REG32(ADR_F0_CIS_CONTENT_REG_10)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_383_352 (((REG32(ADR_F0_CIS_CONTENT_REG_11)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_415_384 (((REG32(ADR_F0_CIS_CONTENT_REG_12)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_447_416 (((REG32(ADR_F0_CIS_CONTENT_REG_13)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_479_448 (((REG32(ADR_F0_CIS_CONTENT_REG_14)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_511_480 (((REG32(ADR_F0_CIS_CONTENT_REG_15)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_31_0 (((REG32(ADR_F1_CIS_CONTENT_REG_0)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_63_32 (((REG32(ADR_F1_CIS_CONTENT_REG_1)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_95_64 (((REG32(ADR_F1_CIS_CONTENT_REG_2)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_127_96 (((REG32(ADR_F1_CIS_CONTENT_REG_3)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_159_128 (((REG32(ADR_F1_CIS_CONTENT_REG_4)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_191_160 (((REG32(ADR_F1_CIS_CONTENT_REG_5)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_223_192 (((REG32(ADR_F1_CIS_CONTENT_REG_6)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_255_224 (((REG32(ADR_F1_CIS_CONTENT_REG_7)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_287_256 (((REG32(ADR_F1_CIS_CONTENT_REG_8)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_319_288 (((REG32(ADR_F1_CIS_CONTENT_REG_9)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_351_320 (((REG32(ADR_F1_CIS_CONTENT_REG_10)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_383_352 (((REG32(ADR_F1_CIS_CONTENT_REG_11)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_415_384 (((REG32(ADR_F1_CIS_CONTENT_REG_12)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_447_416 (((REG32(ADR_F1_CIS_CONTENT_REG_13)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_479_448 (((REG32(ADR_F1_CIS_CONTENT_REG_14)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_511_480 (((REG32(ADR_F1_CIS_CONTENT_REG_15)) & 0xffffffff ) >> 0)
+#define GET_SPI_MODE (((REG32(ADR_SPI_MODE)) & 0xffffffff ) >> 0)
+#define GET_RX_QUOTA (((REG32(ADR_RX_QUOTA)) & 0x0000ffff ) >> 0)
+#define GET_CONDI_NUM (((REG32(ADR_CONDITION_NUMBER)) & 0x000000ff ) >> 0)
+#define GET_HOST_PATH (((REG32(ADR_HOST_PATH)) & 0x00000001 ) >> 0)
+#define GET_TX_SEG (((REG32(ADR_TX_SEG)) & 0xffffffff ) >> 0)
+#define GET_BRST_MODE (((REG32(ADR_DEBUG_BURST_MODE)) & 0x00000001 ) >> 0)
+#define GET_CLK_WIDTH (((REG32(ADR_SPI_TO_PHY_PARAM1)) & 0x0000ffff ) >> 0)
+#define GET_CSN_INTER (((REG32(ADR_SPI_TO_PHY_PARAM1)) & 0xffff0000 ) >> 16)
+#define GET_BACK_DLY (((REG32(ADR_SPI_TO_PHY_PARAM2)) & 0x0000ffff ) >> 0)
+#define GET_FRONT_DLY (((REG32(ADR_SPI_TO_PHY_PARAM2)) & 0xffff0000 ) >> 16)
+#define GET_RX_FIFO_FAIL (((REG32(ADR_SPI_STS)) & 0x00000002 ) >> 1)
+#define GET_RX_HOST_FAIL (((REG32(ADR_SPI_STS)) & 0x00000004 ) >> 2)
+#define GET_TX_FIFO_FAIL (((REG32(ADR_SPI_STS)) & 0x00000008 ) >> 3)
+#define GET_TX_HOST_FAIL (((REG32(ADR_SPI_STS)) & 0x00000010 ) >> 4)
+#define GET_SPI_DOUBLE_ALLOC (((REG32(ADR_SPI_STS)) & 0x00000020 ) >> 5)
+#define GET_SPI_TX_NO_ALLOC (((REG32(ADR_SPI_STS)) & 0x00000040 ) >> 6)
+#define GET_RDATA_RDY (((REG32(ADR_SPI_STS)) & 0x00000080 ) >> 7)
+#define GET_SPI_ALLOC_STATUS (((REG32(ADR_SPI_STS)) & 0x00000100 ) >> 8)
+#define GET_SPI_DBG_WR_FIFO_FULL (((REG32(ADR_SPI_STS)) & 0x00000200 ) >> 9)
+#define GET_RX_LEN (((REG32(ADR_SPI_STS)) & 0xffff0000 ) >> 16)
+#define GET_SPI_TX_ALLOC_SIZE_SHIFT_BITS (((REG32(ADR_TX_ALLOC_SET)) & 0x00000007 ) >> 0)
+#define GET_SPI_HOST_TX_ALLOC_PKBUF (((REG32(ADR_TX_ALLOC_SET)) & 0x00000100 ) >> 8)
+#define GET_SPI_TX_ALLOC_SIZE (((REG32(ADR_TX_ALLOC)) & 0x000000ff ) >> 0)
+#define GET_RD_DAT_CNT (((REG32(ADR_DBG_CNT)) & 0x0000ffff ) >> 0)
+#define GET_RD_STS_CNT (((REG32(ADR_DBG_CNT)) & 0xffff0000 ) >> 16)
+#define GET_JUDGE_CNT (((REG32(ADR_DBG_CNT2)) & 0x0000ffff ) >> 0)
+#define GET_RD_STS_CNT_CLR (((REG32(ADR_DBG_CNT2)) & 0x00010000 ) >> 16)
+#define GET_RD_DAT_CNT_CLR (((REG32(ADR_DBG_CNT2)) & 0x00020000 ) >> 17)
+#define GET_JUDGE_CNT_CLR (((REG32(ADR_DBG_CNT2)) & 0x00040000 ) >> 18)
+#define GET_TX_DONE_CNT (((REG32(ADR_DBG_CNT3)) & 0x0000ffff ) >> 0)
+#define GET_TX_DISCARD_CNT (((REG32(ADR_DBG_CNT3)) & 0xffff0000 ) >> 16)
+#define GET_TX_SET_CNT (((REG32(ADR_DBG_CNT4)) & 0x0000ffff ) >> 0)
+#define GET_TX_DISCARD_CNT_CLR (((REG32(ADR_DBG_CNT4)) & 0x00010000 ) >> 16)
+#define GET_TX_DONE_CNT_CLR (((REG32(ADR_DBG_CNT4)) & 0x00020000 ) >> 17)
+#define GET_TX_SET_CNT_CLR (((REG32(ADR_DBG_CNT4)) & 0x00040000 ) >> 18)
+#define GET_DAT_MODE_OFF (((REG32(ADR_DBG_CNT4)) & 0x00080000 ) >> 19)
+#define GET_TX_FIFO_RESIDUE (((REG32(ADR_DBG_CNT4)) & 0x00700000 ) >> 20)
+#define GET_RX_FIFO_RESIDUE (((REG32(ADR_DBG_CNT4)) & 0x07000000 ) >> 24)
+#define GET_RX_RDY (((REG32(ADR_INT_TAG)) & 0x00000001 ) >> 0)
+#define GET_SDIO_SYS_INT (((REG32(ADR_INT_TAG)) & 0x00000004 ) >> 2)
+#define GET_EDCA0_LOWTHOLD_INT (((REG32(ADR_INT_TAG)) & 0x00000008 ) >> 3)
+#define GET_EDCA1_LOWTHOLD_INT (((REG32(ADR_INT_TAG)) & 0x00000010 ) >> 4)
+#define GET_EDCA2_LOWTHOLD_INT (((REG32(ADR_INT_TAG)) & 0x00000020 ) >> 5)
+#define GET_EDCA3_LOWTHOLD_INT (((REG32(ADR_INT_TAG)) & 0x00000040 ) >> 6)
+#define GET_TX_LIMIT_INT_IN (((REG32(ADR_INT_TAG)) & 0x00000080 ) >> 7)
+#define GET_SPI_FN1 (((REG32(ADR_INT_TAG)) & 0x00007f00 ) >> 8)
+#define GET_SPI_CLK_EN_INT (((REG32(ADR_INT_TAG)) & 0x00008000 ) >> 15)
+#define GET_SPI_HOST_MASK (((REG32(ADR_INT_TAG)) & 0x00ff0000 ) >> 16)
+#define GET_I2CM_INT_WDONE (((REG32(ADR_I2CM_EN)) & 0x00000001 ) >> 0)
+#define GET_I2CM_INT_RDONE (((REG32(ADR_I2CM_EN)) & 0x00000002 ) >> 1)
+#define GET_I2CM_IDLE (((REG32(ADR_I2CM_EN)) & 0x00000004 ) >> 2)
+#define GET_I2CM_INT_MISMATCH (((REG32(ADR_I2CM_EN)) & 0x00000008 ) >> 3)
+#define GET_I2CM_PSCL (((REG32(ADR_I2CM_EN)) & 0x00003ff0 ) >> 4)
+#define GET_I2CM_MANUAL_MODE (((REG32(ADR_I2CM_EN)) & 0x00010000 ) >> 16)
+#define GET_I2CM_INT_WDATA_NEED (((REG32(ADR_I2CM_EN)) & 0x00020000 ) >> 17)
+#define GET_I2CM_INT_RDATA_NEED (((REG32(ADR_I2CM_EN)) & 0x00040000 ) >> 18)
+#define GET_I2CM_DEV_A (((REG32(ADR_I2CM_DEV_A)) & 0x000003ff ) >> 0)
+#define GET_I2CM_DEV_A10B (((REG32(ADR_I2CM_DEV_A)) & 0x00004000 ) >> 14)
+#define GET_I2CM_RX (((REG32(ADR_I2CM_DEV_A)) & 0x00008000 ) >> 15)
+#define GET_I2CM_LEN (((REG32(ADR_I2CM_LEN)) & 0x0000ffff ) >> 0)
+#define GET_I2CM_T_LEFT (((REG32(ADR_I2CM_LEN)) & 0x00070000 ) >> 16)
+#define GET_I2CM_R_GET (((REG32(ADR_I2CM_LEN)) & 0x07000000 ) >> 24)
+#define GET_I2CM_WDAT (((REG32(ADR_I2CM_WDAT)) & 0xffffffff ) >> 0)
+#define GET_I2CM_RDAT (((REG32(ADR_I2CM_RDAT)) & 0xffffffff ) >> 0)
+#define GET_I2CM_SR_LEN (((REG32(ADR_I2CM_EN_2)) & 0x0000ffff ) >> 0)
+#define GET_I2CM_SR_RX (((REG32(ADR_I2CM_EN_2)) & 0x00010000 ) >> 16)
+#define GET_I2CM_REPEAT_START (((REG32(ADR_I2CM_EN_2)) & 0x00020000 ) >> 17)
+#define GET_UART_DATA (((REG32(ADR_UART_DATA)) & 0x000000ff ) >> 0)
+#define GET_DATA_RDY_IE (((REG32(ADR_UART_IER)) & 0x00000001 ) >> 0)
+#define GET_THR_EMPTY_IE (((REG32(ADR_UART_IER)) & 0x00000002 ) >> 1)
+#define GET_RX_LINESTS_IE (((REG32(ADR_UART_IER)) & 0x00000004 ) >> 2)
+#define GET_MDM_STS_IE (((REG32(ADR_UART_IER)) & 0x00000008 ) >> 3)
+#define GET_DMA_RXEND_IE (((REG32(ADR_UART_IER)) & 0x00000040 ) >> 6)
+#define GET_DMA_TXEND_IE (((REG32(ADR_UART_IER)) & 0x00000080 ) >> 7)
+#define GET_FIFO_EN (((REG32(ADR_UART_FCR)) & 0x00000001 ) >> 0)
+#define GET_RXFIFO_RST (((REG32(ADR_UART_FCR)) & 0x00000002 ) >> 1)
+#define GET_TXFIFO_RST (((REG32(ADR_UART_FCR)) & 0x00000004 ) >> 2)
+#define GET_DMA_MODE (((REG32(ADR_UART_FCR)) & 0x00000008 ) >> 3)
+#define GET_EN_AUTO_RTS (((REG32(ADR_UART_FCR)) & 0x00000010 ) >> 4)
+#define GET_EN_AUTO_CTS (((REG32(ADR_UART_FCR)) & 0x00000020 ) >> 5)
+#define GET_RXFIFO_TRGLVL (((REG32(ADR_UART_FCR)) & 0x000000c0 ) >> 6)
+#define GET_WORD_LEN (((REG32(ADR_UART_LCR)) & 0x00000003 ) >> 0)
+#define GET_STOP_BIT (((REG32(ADR_UART_LCR)) & 0x00000004 ) >> 2)
+#define GET_PARITY_EN (((REG32(ADR_UART_LCR)) & 0x00000008 ) >> 3)
+#define GET_EVEN_PARITY (((REG32(ADR_UART_LCR)) & 0x00000010 ) >> 4)
+#define GET_FORCE_PARITY (((REG32(ADR_UART_LCR)) & 0x00000020 ) >> 5)
+#define GET_SET_BREAK (((REG32(ADR_UART_LCR)) & 0x00000040 ) >> 6)
+#define GET_DLAB (((REG32(ADR_UART_LCR)) & 0x00000080 ) >> 7)
+#define GET_DTR (((REG32(ADR_UART_MCR)) & 0x00000001 ) >> 0)
+#define GET_RTS (((REG32(ADR_UART_MCR)) & 0x00000002 ) >> 1)
+#define GET_OUT_1 (((REG32(ADR_UART_MCR)) & 0x00000004 ) >> 2)
+#define GET_OUT_2 (((REG32(ADR_UART_MCR)) & 0x00000008 ) >> 3)
+#define GET_LOOP_BACK (((REG32(ADR_UART_MCR)) & 0x00000010 ) >> 4)
+#define GET_DATA_RDY (((REG32(ADR_UART_LSR)) & 0x00000001 ) >> 0)
+#define GET_OVERRUN_ERR (((REG32(ADR_UART_LSR)) & 0x00000002 ) >> 1)
+#define GET_PARITY_ERR (((REG32(ADR_UART_LSR)) & 0x00000004 ) >> 2)
+#define GET_FRAMING_ERR (((REG32(ADR_UART_LSR)) & 0x00000008 ) >> 3)
+#define GET_BREAK_INT (((REG32(ADR_UART_LSR)) & 0x00000010 ) >> 4)
+#define GET_THR_EMPTY (((REG32(ADR_UART_LSR)) & 0x00000020 ) >> 5)
+#define GET_TX_EMPTY (((REG32(ADR_UART_LSR)) & 0x00000040 ) >> 6)
+#define GET_FIFODATA_ERR (((REG32(ADR_UART_LSR)) & 0x00000080 ) >> 7)
+#define GET_DELTA_CTS (((REG32(ADR_UART_MSR)) & 0x00000001 ) >> 0)
+#define GET_DELTA_DSR (((REG32(ADR_UART_MSR)) & 0x00000002 ) >> 1)
+#define GET_TRAILEDGE_RI (((REG32(ADR_UART_MSR)) & 0x00000004 ) >> 2)
+#define GET_DELTA_CD (((REG32(ADR_UART_MSR)) & 0x00000008 ) >> 3)
+#define GET_CTS (((REG32(ADR_UART_MSR)) & 0x00000010 ) >> 4)
+#define GET_DSR (((REG32(ADR_UART_MSR)) & 0x00000020 ) >> 5)
+#define GET_RI (((REG32(ADR_UART_MSR)) & 0x00000040 ) >> 6)
+#define GET_CD (((REG32(ADR_UART_MSR)) & 0x00000080 ) >> 7)
+#define GET_BRDC_DIV (((REG32(ADR_UART_SPR)) & 0x0000ffff ) >> 0)
+#define GET_RTHR_L (((REG32(ADR_UART_RTHR)) & 0x0000000f ) >> 0)
+#define GET_RTHR_H (((REG32(ADR_UART_RTHR)) & 0x000000f0 ) >> 4)
+#define GET_INT_IDCODE (((REG32(ADR_UART_ISR)) & 0x0000000f ) >> 0)
+#define GET_FIFOS_ENABLED (((REG32(ADR_UART_ISR)) & 0x000000c0 ) >> 6)
+#define GET_DAT_UART_DATA (((REG32(ADR_DAT_UART_DATA)) & 0x000000ff ) >> 0)
+#define GET_DAT_DATA_RDY_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000001 ) >> 0)
+#define GET_DAT_THR_EMPTY_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000002 ) >> 1)
+#define GET_DAT_RX_LINESTS_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000004 ) >> 2)
+#define GET_DAT_MDM_STS_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000008 ) >> 3)
+#define GET_DAT_DMA_RXEND_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000040 ) >> 6)
+#define GET_DAT_DMA_TXEND_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000080 ) >> 7)
+#define GET_DAT_FIFO_EN (((REG32(ADR_DAT_UART_FCR)) & 0x00000001 ) >> 0)
+#define GET_DAT_RXFIFO_RST (((REG32(ADR_DAT_UART_FCR)) & 0x00000002 ) >> 1)
+#define GET_DAT_TXFIFO_RST (((REG32(ADR_DAT_UART_FCR)) & 0x00000004 ) >> 2)
+#define GET_DAT_DMA_MODE (((REG32(ADR_DAT_UART_FCR)) & 0x00000008 ) >> 3)
+#define GET_DAT_EN_AUTO_RTS (((REG32(ADR_DAT_UART_FCR)) & 0x00000010 ) >> 4)
+#define GET_DAT_EN_AUTO_CTS (((REG32(ADR_DAT_UART_FCR)) & 0x00000020 ) >> 5)
+#define GET_DAT_RXFIFO_TRGLVL (((REG32(ADR_DAT_UART_FCR)) & 0x000000c0 ) >> 6)
+#define GET_DAT_WORD_LEN (((REG32(ADR_DAT_UART_LCR)) & 0x00000003 ) >> 0)
+#define GET_DAT_STOP_BIT (((REG32(ADR_DAT_UART_LCR)) & 0x00000004 ) >> 2)
+#define GET_DAT_PARITY_EN (((REG32(ADR_DAT_UART_LCR)) & 0x00000008 ) >> 3)
+#define GET_DAT_EVEN_PARITY (((REG32(ADR_DAT_UART_LCR)) & 0x00000010 ) >> 4)
+#define GET_DAT_FORCE_PARITY (((REG32(ADR_DAT_UART_LCR)) & 0x00000020 ) >> 5)
+#define GET_DAT_SET_BREAK (((REG32(ADR_DAT_UART_LCR)) & 0x00000040 ) >> 6)
+#define GET_DAT_DLAB (((REG32(ADR_DAT_UART_LCR)) & 0x00000080 ) >> 7)
+#define GET_DAT_DTR (((REG32(ADR_DAT_UART_MCR)) & 0x00000001 ) >> 0)
+#define GET_DAT_RTS (((REG32(ADR_DAT_UART_MCR)) & 0x00000002 ) >> 1)
+#define GET_DAT_OUT_1 (((REG32(ADR_DAT_UART_MCR)) & 0x00000004 ) >> 2)
+#define GET_DAT_OUT_2 (((REG32(ADR_DAT_UART_MCR)) & 0x00000008 ) >> 3)
+#define GET_DAT_LOOP_BACK (((REG32(ADR_DAT_UART_MCR)) & 0x00000010 ) >> 4)
+#define GET_DAT_DATA_RDY (((REG32(ADR_DAT_UART_LSR)) & 0x00000001 ) >> 0)
+#define GET_DAT_OVERRUN_ERR (((REG32(ADR_DAT_UART_LSR)) & 0x00000002 ) >> 1)
+#define GET_DAT_PARITY_ERR (((REG32(ADR_DAT_UART_LSR)) & 0x00000004 ) >> 2)
+#define GET_DAT_FRAMING_ERR (((REG32(ADR_DAT_UART_LSR)) & 0x00000008 ) >> 3)
+#define GET_DAT_BREAK_INT (((REG32(ADR_DAT_UART_LSR)) & 0x00000010 ) >> 4)
+#define GET_DAT_THR_EMPTY (((REG32(ADR_DAT_UART_LSR)) & 0x00000020 ) >> 5)
+#define GET_DAT_TX_EMPTY (((REG32(ADR_DAT_UART_LSR)) & 0x00000040 ) >> 6)
+#define GET_DAT_FIFODATA_ERR (((REG32(ADR_DAT_UART_LSR)) & 0x00000080 ) >> 7)
+#define GET_DAT_DELTA_CTS (((REG32(ADR_DAT_UART_MSR)) & 0x00000001 ) >> 0)
+#define GET_DAT_DELTA_DSR (((REG32(ADR_DAT_UART_MSR)) & 0x00000002 ) >> 1)
+#define GET_DAT_TRAILEDGE_RI (((REG32(ADR_DAT_UART_MSR)) & 0x00000004 ) >> 2)
+#define GET_DAT_DELTA_CD (((REG32(ADR_DAT_UART_MSR)) & 0x00000008 ) >> 3)
+#define GET_DAT_CTS (((REG32(ADR_DAT_UART_MSR)) & 0x00000010 ) >> 4)
+#define GET_DAT_DSR (((REG32(ADR_DAT_UART_MSR)) & 0x00000020 ) >> 5)
+#define GET_DAT_RI (((REG32(ADR_DAT_UART_MSR)) & 0x00000040 ) >> 6)
+#define GET_DAT_CD (((REG32(ADR_DAT_UART_MSR)) & 0x00000080 ) >> 7)
+#define GET_DAT_BRDC_DIV (((REG32(ADR_DAT_UART_SPR)) & 0x0000ffff ) >> 0)
+#define GET_DAT_RTHR_L (((REG32(ADR_DAT_UART_RTHR)) & 0x0000000f ) >> 0)
+#define GET_DAT_RTHR_H (((REG32(ADR_DAT_UART_RTHR)) & 0x000000f0 ) >> 4)
+#define GET_DAT_INT_IDCODE (((REG32(ADR_DAT_UART_ISR)) & 0x0000000f ) >> 0)
+#define GET_DAT_FIFOS_ENABLED (((REG32(ADR_DAT_UART_ISR)) & 0x000000c0 ) >> 6)
+#define GET_MASK_TOP (((REG32(ADR_INT_MASK)) & 0xffffffff ) >> 0)
+#define GET_INT_MODE (((REG32(ADR_INT_MODE)) & 0xffffffff ) >> 0)
+#define GET_IRQ_PHY_0 (((REG32(ADR_INT_IRQ_STS)) & 0x00000001 ) >> 0)
+#define GET_IRQ_PHY_1 (((REG32(ADR_INT_IRQ_STS)) & 0x00000002 ) >> 1)
+#define GET_IRQ_SDIO (((REG32(ADR_INT_IRQ_STS)) & 0x00000004 ) >> 2)
+#define GET_IRQ_BEACON_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000008 ) >> 3)
+#define GET_IRQ_BEACON (((REG32(ADR_INT_IRQ_STS)) & 0x00000010 ) >> 4)
+#define GET_IRQ_PRE_BEACON (((REG32(ADR_INT_IRQ_STS)) & 0x00000020 ) >> 5)
+#define GET_IRQ_EDCA0_TX_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000040 ) >> 6)
+#define GET_IRQ_EDCA1_TX_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000080 ) >> 7)
+#define GET_IRQ_EDCA2_TX_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000100 ) >> 8)
+#define GET_IRQ_EDCA3_TX_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000200 ) >> 9)
+#define GET_IRQ_EDCA4_TX_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000400 ) >> 10)
+#define GET_IRQ_BEACON_DTIM (((REG32(ADR_INT_IRQ_STS)) & 0x00001000 ) >> 12)
+#define GET_IRQ_EDCA0_LOWTHOLD_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00002000 ) >> 13)
+#define GET_IRQ_EDCA1_LOWTHOLD_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00004000 ) >> 14)
+#define GET_IRQ_EDCA2_LOWTHOLD_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00008000 ) >> 15)
+#define GET_IRQ_EDCA3_LOWTHOLD_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00010000 ) >> 16)
+#define GET_IRQ_FENCE_HIT_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00020000 ) >> 17)
+#define GET_IRQ_ILL_ADDR_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00040000 ) >> 18)
+#define GET_IRQ_MBOX (((REG32(ADR_INT_IRQ_STS)) & 0x00080000 ) >> 19)
+#define GET_IRQ_US_TIMER0 (((REG32(ADR_INT_IRQ_STS)) & 0x00100000 ) >> 20)
+#define GET_IRQ_US_TIMER1 (((REG32(ADR_INT_IRQ_STS)) & 0x00200000 ) >> 21)
+#define GET_IRQ_US_TIMER2 (((REG32(ADR_INT_IRQ_STS)) & 0x00400000 ) >> 22)
+#define GET_IRQ_US_TIMER3 (((REG32(ADR_INT_IRQ_STS)) & 0x00800000 ) >> 23)
+#define GET_IRQ_MS_TIMER0 (((REG32(ADR_INT_IRQ_STS)) & 0x01000000 ) >> 24)
+#define GET_IRQ_MS_TIMER1 (((REG32(ADR_INT_IRQ_STS)) & 0x02000000 ) >> 25)
+#define GET_IRQ_MS_TIMER2 (((REG32(ADR_INT_IRQ_STS)) & 0x04000000 ) >> 26)
+#define GET_IRQ_MS_TIMER3 (((REG32(ADR_INT_IRQ_STS)) & 0x08000000 ) >> 27)
+#define GET_IRQ_TX_LIMIT_INT (((REG32(ADR_INT_IRQ_STS)) & 0x10000000 ) >> 28)
+#define GET_IRQ_DMA0 (((REG32(ADR_INT_IRQ_STS)) & 0x20000000 ) >> 29)
+#define GET_IRQ_CO_DMA (((REG32(ADR_INT_IRQ_STS)) & 0x40000000 ) >> 30)
+#define GET_IRQ_PERI_GROUP (((REG32(ADR_INT_IRQ_STS)) & 0x80000000 ) >> 31)
+#define GET_FIQ_STATUS (((REG32(ADR_INT_FIQ_STS)) & 0xffffffff ) >> 0)
+#define GET_IRQ_RAW (((REG32(ADR_INT_IRQ_RAW)) & 0xffffffff ) >> 0)
+#define GET_FIQ_RAW (((REG32(ADR_INT_FIQ_RAW)) & 0xffffffff ) >> 0)
+#define GET_INT_PERI_MASK (((REG32(ADR_INT_PERI_MASK)) & 0xffffffff ) >> 0)
+#define GET_PERI_RTC (((REG32(ADR_INT_PERI_STS)) & 0x00000001 ) >> 0)
+#define GET_IRQ_UART0_TX (((REG32(ADR_INT_PERI_STS)) & 0x00000002 ) >> 1)
+#define GET_IRQ_UART0_RX (((REG32(ADR_INT_PERI_STS)) & 0x00000004 ) >> 2)
+#define GET_PERI_GPI_2 (((REG32(ADR_INT_PERI_STS)) & 0x00000008 ) >> 3)
+#define GET_IRQ_SPI_IPC (((REG32(ADR_INT_PERI_STS)) & 0x00000010 ) >> 4)
+#define GET_PERI_GPI_1_0 (((REG32(ADR_INT_PERI_STS)) & 0x00000060 ) >> 5)
+#define GET_SCRT_INT_1 (((REG32(ADR_INT_PERI_STS)) & 0x00000080 ) >> 7)
+#define GET_MMU_ALC_ERR (((REG32(ADR_INT_PERI_STS)) & 0x00000100 ) >> 8)
+#define GET_MMU_RLS_ERR (((REG32(ADR_INT_PERI_STS)) & 0x00000200 ) >> 9)
+#define GET_ID_MNG_INT_1 (((REG32(ADR_INT_PERI_STS)) & 0x00000400 ) >> 10)
+#define GET_MBOX_INT_1 (((REG32(ADR_INT_PERI_STS)) & 0x00000800 ) >> 11)
+#define GET_MBOX_INT_2 (((REG32(ADR_INT_PERI_STS)) & 0x00001000 ) >> 12)
+#define GET_MBOX_INT_3 (((REG32(ADR_INT_PERI_STS)) & 0x00002000 ) >> 13)
+#define GET_HCI_INT_1 (((REG32(ADR_INT_PERI_STS)) & 0x00004000 ) >> 14)
+#define GET_UART_RX_TIMEOUT (((REG32(ADR_INT_PERI_STS)) & 0x00008000 ) >> 15)
+#define GET_UART_MULTI_IRQ (((REG32(ADR_INT_PERI_STS)) & 0x00010000 ) >> 16)
+#define GET_ID_MNG_INT_2 (((REG32(ADR_INT_PERI_STS)) & 0x00020000 ) >> 17)
+#define GET_DMN_NOHIT_INT (((REG32(ADR_INT_PERI_STS)) & 0x00040000 ) >> 18)
+#define GET_ID_THOLD_RX (((REG32(ADR_INT_PERI_STS)) & 0x00080000 ) >> 19)
+#define GET_ID_THOLD_TX (((REG32(ADR_INT_PERI_STS)) & 0x00100000 ) >> 20)
+#define GET_ID_DOUBLE_RLS (((REG32(ADR_INT_PERI_STS)) & 0x00200000 ) >> 21)
+#define GET_RX_ID_LEN_THOLD (((REG32(ADR_INT_PERI_STS)) & 0x00400000 ) >> 22)
+#define GET_TX_ID_LEN_THOLD (((REG32(ADR_INT_PERI_STS)) & 0x00800000 ) >> 23)
+#define GET_ALL_ID_LEN_THOLD (((REG32(ADR_INT_PERI_STS)) & 0x01000000 ) >> 24)
+#define GET_DMN_MCU_INT (((REG32(ADR_INT_PERI_STS)) & 0x02000000 ) >> 25)
+#define GET_IRQ_DAT_UART_TX (((REG32(ADR_INT_PERI_STS)) & 0x04000000 ) >> 26)
+#define GET_IRQ_DAT_UART_RX (((REG32(ADR_INT_PERI_STS)) & 0x08000000 ) >> 27)
+#define GET_DAT_UART_RX_TIMEOUT (((REG32(ADR_INT_PERI_STS)) & 0x10000000 ) >> 28)
+#define GET_DAT_UART_MULTI_IRQ (((REG32(ADR_INT_PERI_STS)) & 0x20000000 ) >> 29)
+#define GET_ALR_ABT_NOCHG_INT_IRQ (((REG32(ADR_INT_PERI_STS)) & 0x40000000 ) >> 30)
+#define GET_TBLNEQ_MNGPKT_INT_IRQ (((REG32(ADR_INT_PERI_STS)) & 0x80000000 ) >> 31)
+#define GET_INTR_PERI_RAW (((REG32(ADR_INT_PERI_RAW)) & 0xffffffff ) >> 0)
+#define GET_INTR_GPI00_CFG (((REG32(ADR_INT_GPI_CFG)) & 0x00000003 ) >> 0)
+#define GET_INTR_GPI01_CFG (((REG32(ADR_INT_GPI_CFG)) & 0x0000000c ) >> 2)
+#define GET_SYS_RST_INT (((REG32(ADR_SYS_INT_FOR_HOST)) & 0x00000001 ) >> 0)
+#define GET_SPI_IPC_ADDR (((REG32(ADR_SPI_IPC)) & 0xffffffff ) >> 0)
+#define GET_SD_MASK_TOP (((REG32(ADR_SDIO_MASK)) & 0xffffffff ) >> 0)
+#define GET_IRQ_PHY_0_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000001 ) >> 0)
+#define GET_IRQ_PHY_1_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000002 ) >> 1)
+#define GET_IRQ_SDIO_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000004 ) >> 2)
+#define GET_IRQ_BEACON_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000008 ) >> 3)
+#define GET_IRQ_BEACON_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000010 ) >> 4)
+#define GET_IRQ_PRE_BEACON_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000020 ) >> 5)
+#define GET_IRQ_EDCA0_TX_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000040 ) >> 6)
+#define GET_IRQ_EDCA1_TX_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000080 ) >> 7)
+#define GET_IRQ_EDCA2_TX_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000100 ) >> 8)
+#define GET_IRQ_EDCA3_TX_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000200 ) >> 9)
+#define GET_IRQ_EDCA4_TX_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000400 ) >> 10)
+#define GET_IRQ_BEACON_DTIM_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00001000 ) >> 12)
+#define GET_IRQ_EDCA0_LOWTHOLD_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00002000 ) >> 13)
+#define GET_IRQ_EDCA1_LOWTHOLD_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00004000 ) >> 14)
+#define GET_IRQ_EDCA2_LOWTHOLD_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00008000 ) >> 15)
+#define GET_IRQ_EDCA3_LOWTHOLD_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00010000 ) >> 16)
+#define GET_IRQ_FENCE_HIT_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00020000 ) >> 17)
+#define GET_IRQ_ILL_ADDR_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00040000 ) >> 18)
+#define GET_IRQ_MBOX_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00080000 ) >> 19)
+#define GET_IRQ_US_TIMER0_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00100000 ) >> 20)
+#define GET_IRQ_US_TIMER1_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00200000 ) >> 21)
+#define GET_IRQ_US_TIMER2_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00400000 ) >> 22)
+#define GET_IRQ_US_TIMER3_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00800000 ) >> 23)
+#define GET_IRQ_MS_TIMER0_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x01000000 ) >> 24)
+#define GET_IRQ_MS_TIMER1_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x02000000 ) >> 25)
+#define GET_IRQ_MS_TIMER2_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x04000000 ) >> 26)
+#define GET_IRQ_MS_TIMER3_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x08000000 ) >> 27)
+#define GET_IRQ_TX_LIMIT_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x10000000 ) >> 28)
+#define GET_IRQ_DMA0_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x20000000 ) >> 29)
+#define GET_IRQ_CO_DMA_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x40000000 ) >> 30)
+#define GET_IRQ_PERI_GROUP_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x80000000 ) >> 31)
+#define GET_INT_PERI_MASK_SD (((REG32(ADR_SD_PERI_MASK)) & 0xffffffff ) >> 0)
+#define GET_PERI_RTC_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000001 ) >> 0)
+#define GET_IRQ_UART0_TX_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000002 ) >> 1)
+#define GET_IRQ_UART0_RX_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000004 ) >> 2)
+#define GET_PERI_GPI_SD_2 (((REG32(ADR_SD_PERI_STS)) & 0x00000008 ) >> 3)
+#define GET_IRQ_SPI_IPC_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000010 ) >> 4)
+#define GET_PERI_GPI_SD_1_0 (((REG32(ADR_SD_PERI_STS)) & 0x00000060 ) >> 5)
+#define GET_SCRT_INT_1_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000080 ) >> 7)
+#define GET_MMU_ALC_ERR_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000100 ) >> 8)
+#define GET_MMU_RLS_ERR_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000200 ) >> 9)
+#define GET_ID_MNG_INT_1_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000400 ) >> 10)
+#define GET_MBOX_INT_1_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000800 ) >> 11)
+#define GET_MBOX_INT_2_SD (((REG32(ADR_SD_PERI_STS)) & 0x00001000 ) >> 12)
+#define GET_MBOX_INT_3_SD (((REG32(ADR_SD_PERI_STS)) & 0x00002000 ) >> 13)
+#define GET_HCI_INT_1_SD (((REG32(ADR_SD_PERI_STS)) & 0x00004000 ) >> 14)
+#define GET_UART_RX_TIMEOUT_SD (((REG32(ADR_SD_PERI_STS)) & 0x00008000 ) >> 15)
+#define GET_UART_MULTI_IRQ_SD (((REG32(ADR_SD_PERI_STS)) & 0x00010000 ) >> 16)
+#define GET_ID_MNG_INT_2_SD (((REG32(ADR_SD_PERI_STS)) & 0x00020000 ) >> 17)
+#define GET_DMN_NOHIT_INT_SD (((REG32(ADR_SD_PERI_STS)) & 0x00040000 ) >> 18)
+#define GET_ID_THOLD_RX_SD (((REG32(ADR_SD_PERI_STS)) & 0x00080000 ) >> 19)
+#define GET_ID_THOLD_TX_SD (((REG32(ADR_SD_PERI_STS)) & 0x00100000 ) >> 20)
+#define GET_ID_DOUBLE_RLS_SD (((REG32(ADR_SD_PERI_STS)) & 0x00200000 ) >> 21)
+#define GET_RX_ID_LEN_THOLD_SD (((REG32(ADR_SD_PERI_STS)) & 0x00400000 ) >> 22)
+#define GET_TX_ID_LEN_THOLD_SD (((REG32(ADR_SD_PERI_STS)) & 0x00800000 ) >> 23)
+#define GET_ALL_ID_LEN_THOLD_SD (((REG32(ADR_SD_PERI_STS)) & 0x01000000 ) >> 24)
+#define GET_DMN_MCU_INT_SD (((REG32(ADR_SD_PERI_STS)) & 0x02000000 ) >> 25)
+#define GET_IRQ_DAT_UART_TX_SD (((REG32(ADR_SD_PERI_STS)) & 0x04000000 ) >> 26)
+#define GET_IRQ_DAT_UART_RX_SD (((REG32(ADR_SD_PERI_STS)) & 0x08000000 ) >> 27)
+#define GET_DAT_UART_RX_TIMEOUT_SD (((REG32(ADR_SD_PERI_STS)) & 0x10000000 ) >> 28)
+#define GET_DAT_UART_MULTI_IRQ_SD (((REG32(ADR_SD_PERI_STS)) & 0x20000000 ) >> 29)
+#define GET_ALR_ABT_NOCHG_INT_IRQ_SD (((REG32(ADR_SD_PERI_STS)) & 0x40000000 ) >> 30)
+#define GET_TBLNEQ_MNGPKT_INT_IRQ_SD (((REG32(ADR_SD_PERI_STS)) & 0x80000000 ) >> 31)
+#define GET_DBG_SPI_MODE (((REG32(ADR_DBG_SPI_MODE)) & 0xffffffff ) >> 0)
+#define GET_DBG_RX_QUOTA (((REG32(ADR_DBG_RX_QUOTA)) & 0x0000ffff ) >> 0)
+#define GET_DBG_CONDI_NUM (((REG32(ADR_DBG_CONDITION_NUMBER)) & 0x000000ff ) >> 0)
+#define GET_DBG_HOST_PATH (((REG32(ADR_DBG_HOST_PATH)) & 0x00000001 ) >> 0)
+#define GET_DBG_TX_SEG (((REG32(ADR_DBG_TX_SEG)) & 0xffffffff ) >> 0)
+#define GET_DBG_BRST_MODE (((REG32(ADR_DBG_DEBUG_BURST_MODE)) & 0x00000001 ) >> 0)
+#define GET_DBG_CLK_WIDTH (((REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) & 0x0000ffff ) >> 0)
+#define GET_DBG_CSN_INTER (((REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) & 0xffff0000 ) >> 16)
+#define GET_DBG_BACK_DLY (((REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) & 0x0000ffff ) >> 0)
+#define GET_DBG_FRONT_DLY (((REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) & 0xffff0000 ) >> 16)
+#define GET_DBG_RX_FIFO_FAIL (((REG32(ADR_DBG_SPI_STS)) & 0x00000002 ) >> 1)
+#define GET_DBG_RX_HOST_FAIL (((REG32(ADR_DBG_SPI_STS)) & 0x00000004 ) >> 2)
+#define GET_DBG_TX_FIFO_FAIL (((REG32(ADR_DBG_SPI_STS)) & 0x00000008 ) >> 3)
+#define GET_DBG_TX_HOST_FAIL (((REG32(ADR_DBG_SPI_STS)) & 0x00000010 ) >> 4)
+#define GET_DBG_SPI_DOUBLE_ALLOC (((REG32(ADR_DBG_SPI_STS)) & 0x00000020 ) >> 5)
+#define GET_DBG_SPI_TX_NO_ALLOC (((REG32(ADR_DBG_SPI_STS)) & 0x00000040 ) >> 6)
+#define GET_DBG_RDATA_RDY (((REG32(ADR_DBG_SPI_STS)) & 0x00000080 ) >> 7)
+#define GET_DBG_SPI_ALLOC_STATUS (((REG32(ADR_DBG_SPI_STS)) & 0x00000100 ) >> 8)
+#define GET_DBG_SPI_DBG_WR_FIFO_FULL (((REG32(ADR_DBG_SPI_STS)) & 0x00000200 ) >> 9)
+#define GET_DBG_RX_LEN (((REG32(ADR_DBG_SPI_STS)) & 0xffff0000 ) >> 16)
+#define GET_DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS (((REG32(ADR_DBG_TX_ALLOC_SET)) & 0x00000007 ) >> 0)
+#define GET_DBG_SPI_HOST_TX_ALLOC_PKBUF (((REG32(ADR_DBG_TX_ALLOC_SET)) & 0x00000100 ) >> 8)
+#define GET_DBG_SPI_TX_ALLOC_SIZE (((REG32(ADR_DBG_TX_ALLOC)) & 0x000000ff ) >> 0)
+#define GET_DBG_RD_DAT_CNT (((REG32(ADR_DBG_DBG_CNT)) & 0x0000ffff ) >> 0)
+#define GET_DBG_RD_STS_CNT (((REG32(ADR_DBG_DBG_CNT)) & 0xffff0000 ) >> 16)
+#define GET_DBG_JUDGE_CNT (((REG32(ADR_DBG_DBG_CNT2)) & 0x0000ffff ) >> 0)
+#define GET_DBG_RD_STS_CNT_CLR (((REG32(ADR_DBG_DBG_CNT2)) & 0x00010000 ) >> 16)
+#define GET_DBG_RD_DAT_CNT_CLR (((REG32(ADR_DBG_DBG_CNT2)) & 0x00020000 ) >> 17)
+#define GET_DBG_JUDGE_CNT_CLR (((REG32(ADR_DBG_DBG_CNT2)) & 0x00040000 ) >> 18)
+#define GET_DBG_TX_DONE_CNT (((REG32(ADR_DBG_DBG_CNT3)) & 0x0000ffff ) >> 0)
+#define GET_DBG_TX_DISCARD_CNT (((REG32(ADR_DBG_DBG_CNT3)) & 0xffff0000 ) >> 16)
+#define GET_DBG_TX_SET_CNT (((REG32(ADR_DBG_DBG_CNT4)) & 0x0000ffff ) >> 0)
+#define GET_DBG_TX_DISCARD_CNT_CLR (((REG32(ADR_DBG_DBG_CNT4)) & 0x00010000 ) >> 16)
+#define GET_DBG_TX_DONE_CNT_CLR (((REG32(ADR_DBG_DBG_CNT4)) & 0x00020000 ) >> 17)
+#define GET_DBG_TX_SET_CNT_CLR (((REG32(ADR_DBG_DBG_CNT4)) & 0x00040000 ) >> 18)
+#define GET_DBG_DAT_MODE_OFF (((REG32(ADR_DBG_DBG_CNT4)) & 0x00080000 ) >> 19)
+#define GET_DBG_TX_FIFO_RESIDUE (((REG32(ADR_DBG_DBG_CNT4)) & 0x00700000 ) >> 20)
+#define GET_DBG_RX_FIFO_RESIDUE (((REG32(ADR_DBG_DBG_CNT4)) & 0x07000000 ) >> 24)
+#define GET_DBG_RX_RDY (((REG32(ADR_DBG_INT_TAG)) & 0x00000001 ) >> 0)
+#define GET_DBG_SDIO_SYS_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00000004 ) >> 2)
+#define GET_DBG_EDCA0_LOWTHOLD_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00000008 ) >> 3)
+#define GET_DBG_EDCA1_LOWTHOLD_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00000010 ) >> 4)
+#define GET_DBG_EDCA2_LOWTHOLD_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00000020 ) >> 5)
+#define GET_DBG_EDCA3_LOWTHOLD_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00000040 ) >> 6)
+#define GET_DBG_TX_LIMIT_INT_IN (((REG32(ADR_DBG_INT_TAG)) & 0x00000080 ) >> 7)
+#define GET_DBG_SPI_FN1 (((REG32(ADR_DBG_INT_TAG)) & 0x00007f00 ) >> 8)
+#define GET_DBG_SPI_CLK_EN_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00008000 ) >> 15)
+#define GET_DBG_SPI_HOST_MASK (((REG32(ADR_DBG_INT_TAG)) & 0x00ff0000 ) >> 16)
+#define GET_BOOT_ADDR (((REG32(ADR_BOOT_ADDR)) & 0x00ffffff ) >> 0)
+#define GET_CHECK_SUM_FAIL (((REG32(ADR_BOOT_ADDR)) & 0x80000000 ) >> 31)
+#define GET_VERIFY_DATA (((REG32(ADR_VERIFY_DATA)) & 0xffffffff ) >> 0)
+#define GET_FLASH_ADDR (((REG32(ADR_FLASH_ADDR)) & 0x00ffffff ) >> 0)
+#define GET_FLASH_CMD_CLR (((REG32(ADR_FLASH_ADDR)) & 0x10000000 ) >> 28)
+#define GET_FLASH_DMA_CLR (((REG32(ADR_FLASH_ADDR)) & 0x20000000 ) >> 29)
+#define GET_DMA_EN (((REG32(ADR_FLASH_ADDR)) & 0x40000000 ) >> 30)
+#define GET_DMA_BUSY (((REG32(ADR_FLASH_ADDR)) & 0x80000000 ) >> 31)
+#define GET_SRAM_ADDR (((REG32(ADR_SRAM_ADDR)) & 0xffffffff ) >> 0)
+#define GET_FLASH_DMA_LEN (((REG32(ADR_LEN)) & 0xffffffff ) >> 0)
+#define GET_FLASH_FRONT_DLY (((REG32(ADR_SPI_PARAM)) & 0x0000ffff ) >> 0)
+#define GET_FLASH_BACK_DLY (((REG32(ADR_SPI_PARAM)) & 0xffff0000 ) >> 16)
+#define GET_FLASH_CLK_WIDTH (((REG32(ADR_SPI_PARAM2)) & 0x0000ffff ) >> 0)
+#define GET_SPI_BUSY (((REG32(ADR_SPI_PARAM2)) & 0x00010000 ) >> 16)
+#define GET_FLS_REMAP (((REG32(ADR_SPI_PARAM2)) & 0x00020000 ) >> 17)
+#define GET_PBUS_SWP (((REG32(ADR_SPI_PARAM2)) & 0x00040000 ) >> 18)
+#define GET_BIT_MODE1 (((REG32(ADR_SPI_PARAM2)) & 0x00080000 ) >> 19)
+#define GET_BIT_MODE2 (((REG32(ADR_SPI_PARAM2)) & 0x00100000 ) >> 20)
+#define GET_BIT_MODE4 (((REG32(ADR_SPI_PARAM2)) & 0x00200000 ) >> 21)
+#define GET_BOOT_CHECK_SUM (((REG32(ADR_CHECK_SUM_RESULT)) & 0xffffffff ) >> 0)
+#define GET_CHECK_SUM_TAG (((REG32(ADR_CHECK_SUM_IN_FILE)) & 0xffffffff ) >> 0)
+#define GET_CMD_LEN (((REG32(ADR_COMMAND_LEN)) & 0x0000ffff ) >> 0)
+#define GET_CMD_ADDR (((REG32(ADR_COMMAND_ADDR)) & 0xffffffff ) >> 0)
+#define GET_DMA_ADR_SRC (((REG32(ADR_DMA_ADR_SRC)) & 0xffffffff ) >> 0)
+#define GET_DMA_ADR_DST (((REG32(ADR_DMA_ADR_DST)) & 0xffffffff ) >> 0)
+#define GET_DMA_SRC_SIZE (((REG32(ADR_DMA_CTRL)) & 0x00000007 ) >> 0)
+#define GET_DMA_SRC_INC (((REG32(ADR_DMA_CTRL)) & 0x00000008 ) >> 3)
+#define GET_DMA_DST_SIZE (((REG32(ADR_DMA_CTRL)) & 0x00000070 ) >> 4)
+#define GET_DMA_DST_INC (((REG32(ADR_DMA_CTRL)) & 0x00000080 ) >> 7)
+#define GET_DMA_FAST_FILL (((REG32(ADR_DMA_CTRL)) & 0x00000100 ) >> 8)
+#define GET_DMA_SDIO_KICK (((REG32(ADR_DMA_CTRL)) & 0x00001000 ) >> 12)
+#define GET_DMA_BADR_EN (((REG32(ADR_DMA_CTRL)) & 0x00002000 ) >> 13)
+#define GET_DMA_LEN (((REG32(ADR_DMA_CTRL)) & 0xffff0000 ) >> 16)
+#define GET_DMA_INT_MASK (((REG32(ADR_DMA_INT)) & 0x00000001 ) >> 0)
+#define GET_DMA_STS (((REG32(ADR_DMA_INT)) & 0x00000100 ) >> 8)
+#define GET_DMA_FINISH (((REG32(ADR_DMA_INT)) & 0x80000000 ) >> 31)
+#define GET_DMA_CONST (((REG32(ADR_DMA_FILL_CONST)) & 0xffffffff ) >> 0)
+#define GET_SLEEP_WAKE_CNT (((REG32(ADR_PMU_0)) & 0x00ffffff ) >> 0)
+#define GET_RG_DLDO_LEVEL (((REG32(ADR_PMU_0)) & 0x07000000 ) >> 24)
+#define GET_RG_DLDO_BOOST_IQ (((REG32(ADR_PMU_0)) & 0x08000000 ) >> 27)
+#define GET_RG_BUCK_LEVEL (((REG32(ADR_PMU_0)) & 0x70000000 ) >> 28)
+#define GET_RG_BUCK_VREF_SEL (((REG32(ADR_PMU_0)) & 0x80000000 ) >> 31)
+#define GET_RG_RTC_OSC_RES_SW_MANUAL (((REG32(ADR_PMU_1)) & 0x000003ff ) >> 0)
+#define GET_RG_RTC_OSC_RES_SW (((REG32(ADR_PMU_1)) & 0x03ff0000 ) >> 16)
+#define GET_RTC_OSC_CAL_RES_RDY (((REG32(ADR_PMU_1)) & 0x80000000 ) >> 31)
+#define GET_RG_DCDC_MODE (((REG32(ADR_PMU_2)) & 0x00000001 ) >> 0)
+#define GET_RG_BUCK_EN_PSM (((REG32(ADR_PMU_2)) & 0x00000010 ) >> 4)
+#define GET_RG_BUCK_PSM_VTH (((REG32(ADR_PMU_2)) & 0x00000100 ) >> 8)
+#define GET_RG_RTC_OSC_RES_SW_MANUAL_EN (((REG32(ADR_PMU_2)) & 0x00001000 ) >> 12)
+#define GET_RG_RTC_RDY_DEGLITCH_TIMER (((REG32(ADR_PMU_2)) & 0x00006000 ) >> 13)
+#define GET_RTC_CAL_ENA (((REG32(ADR_PMU_2)) & 0x00010000 ) >> 16)
+#define GET_PMU_WAKE_TRIG_EVENT (((REG32(ADR_PMU_3)) & 0x00000003 ) >> 0)
+#define GET_DIGI_TOP_POR_MASK (((REG32(ADR_PMU_3)) & 0x00000010 ) >> 4)
+#define GET_PMU_ENTER_SLEEP_MODE (((REG32(ADR_PMU_3)) & 0x00000100 ) >> 8)
+#define GET_RG_RTC_DUMMIES (((REG32(ADR_PMU_3)) & 0xffff0000 ) >> 16)
+#define GET_RTC_EN (((REG32(ADR_RTC_1)) & 0x00000001 ) >> 0)
+#define GET_RTC_SRC (((REG32(ADR_RTC_1)) & 0x00000002 ) >> 1)
+#define GET_RTC_TICK_CNT (((REG32(ADR_RTC_1)) & 0x7fff0000 ) >> 16)
+#define GET_RTC_INT_SEC_MASK (((REG32(ADR_RTC_2)) & 0x00000001 ) >> 0)
+#define GET_RTC_INT_ALARM_MASK (((REG32(ADR_RTC_2)) & 0x00000002 ) >> 1)
+#define GET_RTC_INT_SEC (((REG32(ADR_RTC_2)) & 0x00010000 ) >> 16)
+#define GET_RTC_INT_ALARM (((REG32(ADR_RTC_2)) & 0x00020000 ) >> 17)
+#define GET_RTC_SEC_START_CNT (((REG32(ADR_RTC_3W)) & 0xffffffff ) >> 0)
+#define GET_RTC_SEC_CNT (((REG32(ADR_RTC_3R)) & 0xffffffff ) >> 0)
+#define GET_RTC_SEC_ALARM_VALUE (((REG32(ADR_RTC_4)) & 0xffffffff ) >> 0)
+#define GET_D2_DMA_ADR_SRC (((REG32(ADR_D2_DMA_ADR_SRC)) & 0xffffffff ) >> 0)
+#define GET_D2_DMA_ADR_DST (((REG32(ADR_D2_DMA_ADR_DST)) & 0xffffffff ) >> 0)
+#define GET_D2_DMA_SRC_SIZE (((REG32(ADR_D2_DMA_CTRL)) & 0x00000007 ) >> 0)
+#define GET_D2_DMA_SRC_INC (((REG32(ADR_D2_DMA_CTRL)) & 0x00000008 ) >> 3)
+#define GET_D2_DMA_DST_SIZE (((REG32(ADR_D2_DMA_CTRL)) & 0x00000070 ) >> 4)
+#define GET_D2_DMA_DST_INC (((REG32(ADR_D2_DMA_CTRL)) & 0x00000080 ) >> 7)
+#define GET_D2_DMA_FAST_FILL (((REG32(ADR_D2_DMA_CTRL)) & 0x00000100 ) >> 8)
+#define GET_D2_DMA_SDIO_KICK (((REG32(ADR_D2_DMA_CTRL)) & 0x00001000 ) >> 12)
+#define GET_D2_DMA_BADR_EN (((REG32(ADR_D2_DMA_CTRL)) & 0x00002000 ) >> 13)
+#define GET_D2_DMA_LEN (((REG32(ADR_D2_DMA_CTRL)) & 0xffff0000 ) >> 16)
+#define GET_D2_DMA_INT_MASK (((REG32(ADR_D2_DMA_INT)) & 0x00000001 ) >> 0)
+#define GET_D2_DMA_STS (((REG32(ADR_D2_DMA_INT)) & 0x00000100 ) >> 8)
+#define GET_D2_DMA_FINISH (((REG32(ADR_D2_DMA_INT)) & 0x80000000 ) >> 31)
+#define GET_D2_DMA_CONST (((REG32(ADR_D2_DMA_FILL_CONST)) & 0xffffffff ) >> 0)
+#define GET_TRAP_UNKNOWN_TYPE (((REG32(ADR_CONTROL)) & 0x00000001 ) >> 0)
+#define GET_TX_ON_DEMAND_ENA (((REG32(ADR_CONTROL)) & 0x00000002 ) >> 1)
+#define GET_RX_2_HOST (((REG32(ADR_CONTROL)) & 0x00000004 ) >> 2)
+#define GET_AUTO_SEQNO (((REG32(ADR_CONTROL)) & 0x00000008 ) >> 3)
+#define GET_BYPASSS_TX_PARSER_ENCAP (((REG32(ADR_CONTROL)) & 0x00000010 ) >> 4)
+#define GET_HDR_STRIP (((REG32(ADR_CONTROL)) & 0x00000020 ) >> 5)
+#define GET_ERP_PROTECT (((REG32(ADR_CONTROL)) & 0x000000c0 ) >> 6)
+#define GET_PRO_VER (((REG32(ADR_CONTROL)) & 0x00000300 ) >> 8)
+#define GET_TXQ_ID0 (((REG32(ADR_CONTROL)) & 0x00007000 ) >> 12)
+#define GET_TXQ_ID1 (((REG32(ADR_CONTROL)) & 0x00070000 ) >> 16)
+#define GET_TX_ETHER_TRAP_EN (((REG32(ADR_CONTROL)) & 0x00100000 ) >> 20)
+#define GET_RX_ETHER_TRAP_EN (((REG32(ADR_CONTROL)) & 0x00200000 ) >> 21)
+#define GET_RX_NULL_TRAP_EN (((REG32(ADR_CONTROL)) & 0x00400000 ) >> 22)
+#define GET_RX_GET_TX_QUEUE_EN (((REG32(ADR_CONTROL)) & 0x02000000 ) >> 25)
+#define GET_HCI_INQ_SEL (((REG32(ADR_CONTROL)) & 0x04000000 ) >> 26)
+#define GET_TRX_DEBUG_CNT_ENA (((REG32(ADR_CONTROL)) & 0x10000000 ) >> 28)
+#define GET_WAKE_SOON_WITH_SCK (((REG32(ADR_SDIO_WAKE_MODE)) & 0x00000001 ) >> 0)
+#define GET_TX_FLOW_CTRL (((REG32(ADR_TX_FLOW_0)) & 0x0000ffff ) >> 0)
+#define GET_TX_FLOW_MGMT (((REG32(ADR_TX_FLOW_0)) & 0xffff0000 ) >> 16)
+#define GET_TX_FLOW_DATA (((REG32(ADR_TX_FLOW_1)) & 0xffffffff ) >> 0)
+#define GET_DOT11RTSTHRESHOLD (((REG32(ADR_THREASHOLD)) & 0xffff0000 ) >> 16)
+#define GET_TXF_ID (((REG32(ADR_TXFID_INCREASE)) & 0x0000003f ) >> 0)
+#define GET_SEQ_CTRL (((REG32(ADR_GLOBAL_SEQUENCE)) & 0x0000ffff ) >> 0)
+#define GET_TX_PBOFFSET (((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0x000000ff ) >> 0)
+#define GET_TX_INFO_SIZE (((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0x0000ff00 ) >> 8)
+#define GET_RX_INFO_SIZE (((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0x00ff0000 ) >> 16)
+#define GET_RX_LAST_PHY_SIZE (((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0xff000000 ) >> 24)
+#define GET_TX_INFO_CLEAR_SIZE (((REG32(ADR_HCI_TX_INFO_CLEAR)) & 0x0000003f ) >> 0)
+#define GET_TX_INFO_CLEAR_ENABLE (((REG32(ADR_HCI_TX_INFO_CLEAR)) & 0x00000100 ) >> 8)
+#define GET_TXTRAP_ETHTYPE1 (((REG32(ADR_TX_ETHER_TYPE_1)) & 0x0000ffff ) >> 0)
+#define GET_TXTRAP_ETHTYPE0 (((REG32(ADR_TX_ETHER_TYPE_1)) & 0xffff0000 ) >> 16)
+#define GET_RXTRAP_ETHTYPE1 (((REG32(ADR_RX_ETHER_TYPE_1)) & 0x0000ffff ) >> 0)
+#define GET_RXTRAP_ETHTYPE0 (((REG32(ADR_RX_ETHER_TYPE_1)) & 0xffff0000 ) >> 16)
+#define GET_TX_PKT_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_0)) & 0xffffffff ) >> 0)
+#define GET_RX_PKT_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_1)) & 0xffffffff ) >> 0)
+#define GET_HOST_CMD_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_2)) & 0x000000ff ) >> 0)
+#define GET_HOST_EVENT_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_3)) & 0x000000ff ) >> 0)
+#define GET_TX_PKT_DROP_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_4)) & 0x000000ff ) >> 0)
+#define GET_RX_PKT_DROP_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_5)) & 0x000000ff ) >> 0)
+#define GET_TX_PKT_TRAP_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_6)) & 0x000000ff ) >> 0)
+#define GET_RX_PKT_TRAP_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_7)) & 0x000000ff ) >> 0)
+#define GET_HOST_TX_FAIL_COUNTER (((REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_0)) & 0x000000ff ) >> 0)
+#define GET_HOST_RX_FAIL_COUNTER (((REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_1)) & 0x000000ff ) >> 0)
+#define GET_HCI_STATE_MONITOR (((REG32(ADR_HCI_STATE_DEBUG_MODE_0)) & 0xffffffff ) >> 0)
+#define GET_HCI_ST_TIMEOUT_MONITOR (((REG32(ADR_HCI_STATE_DEBUG_MODE_1)) & 0xffffffff ) >> 0)
+#define GET_TX_ON_DEMAND_LENGTH (((REG32(ADR_HCI_STATE_DEBUG_MODE_2)) & 0xffffffff ) >> 0)
+#define GET_HCI_MONITOR_REG1 (((REG32(ADR_HCI_STATE_DEBUG_MODE_3)) & 0xffffffff ) >> 0)
+#define GET_HCI_MONITOR_REG2 (((REG32(ADR_HCI_STATE_DEBUG_MODE_4)) & 0xffffffff ) >> 0)
+#define GET_HCI_TX_ALLOC_TIME_31_0 (((REG32(ADR_HCI_STATE_DEBUG_MODE_5)) & 0xffffffff ) >> 0)
+#define GET_HCI_TX_ALLOC_TIME_47_32 (((REG32(ADR_HCI_STATE_DEBUG_MODE_6)) & 0x0000ffff ) >> 0)
+#define GET_HCI_MB_MAX_CNT (((REG32(ADR_HCI_STATE_DEBUG_MODE_6)) & 0x00ff0000 ) >> 16)
+#define GET_HCI_TX_ALLOC_CNT_31_0 (((REG32(ADR_HCI_STATE_DEBUG_MODE_7)) & 0xffffffff ) >> 0)
+#define GET_HCI_TX_ALLOC_CNT_47_32 (((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0x0000ffff ) >> 0)
+#define GET_HCI_PROC_CNT (((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0x00ff0000 ) >> 16)
+#define GET_SDIO_TRANS_CNT (((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0xff000000 ) >> 24)
+#define GET_SDIO_TX_INVALID_CNT_31_0 (((REG32(ADR_HCI_STATE_DEBUG_MODE_9)) & 0xffffffff ) >> 0)
+#define GET_SDIO_TX_INVALID_CNT_47_32 (((REG32(ADR_HCI_STATE_DEBUG_MODE_10)) & 0x0000ffff ) >> 0)
+#define GET_CS_START_ADDR (((REG32(ADR_CS_START_ADDR)) & 0x0000ffff ) >> 0)
+#define GET_CS_PKT_ID (((REG32(ADR_CS_START_ADDR)) & 0x007f0000 ) >> 16)
+#define GET_ADD_LEN (((REG32(ADR_CS_ADD_LEN)) & 0x0000ffff ) >> 0)
+#define GET_CS_ADDER_EN (((REG32(ADR_CS_CMD)) & 0x00000001 ) >> 0)
+#define GET_PSEUDO (((REG32(ADR_CS_CMD)) & 0x00000002 ) >> 1)
+#define GET_CALCULATE (((REG32(ADR_CS_INI_BUF)) & 0xffffffff ) >> 0)
+#define GET_L4_LEN (((REG32(ADR_CS_PSEUDO_BUF)) & 0x0000ffff ) >> 0)
+#define GET_L4_PROTOL (((REG32(ADR_CS_PSEUDO_BUF)) & 0x00ff0000 ) >> 16)
+#define GET_CHECK_SUM (((REG32(ADR_CS_CHECK_SUM)) & 0x0000ffff ) >> 0)
+#define GET_RAND_EN (((REG32(ADR_RAND_EN)) & 0x00000001 ) >> 0)
+#define GET_RAND_NUM (((REG32(ADR_RAND_NUM)) & 0xffffffff ) >> 0)
+#define GET_MUL_OP1 (((REG32(ADR_MUL_OP1)) & 0xffffffff ) >> 0)
+#define GET_MUL_OP2 (((REG32(ADR_MUL_OP2)) & 0xffffffff ) >> 0)
+#define GET_MUL_ANS0 (((REG32(ADR_MUL_ANS0)) & 0xffffffff ) >> 0)
+#define GET_MUL_ANS1 (((REG32(ADR_MUL_ANS1)) & 0xffffffff ) >> 0)
+#define GET_RD_ADDR (((REG32(ADR_DMA_RDATA)) & 0x0000ffff ) >> 0)
+#define GET_RD_ID (((REG32(ADR_DMA_RDATA)) & 0x007f0000 ) >> 16)
+#define GET_WR_ADDR (((REG32(ADR_DMA_WDATA)) & 0x0000ffff ) >> 0)
+#define GET_WR_ID (((REG32(ADR_DMA_WDATA)) & 0x007f0000 ) >> 16)
+#define GET_LEN (((REG32(ADR_DMA_LEN)) & 0x0000ffff ) >> 0)
+#define GET_CLR (((REG32(ADR_DMA_CLR)) & 0x00000001 ) >> 0)
+#define GET_PHY_MODE (((REG32(ADR_NAV_DATA)) & 0x00000003 ) >> 0)
+#define GET_SHRT_PREAM (((REG32(ADR_NAV_DATA)) & 0x00000004 ) >> 2)
+#define GET_SHRT_GI (((REG32(ADR_NAV_DATA)) & 0x00000008 ) >> 3)
+#define GET_DATA_RATE (((REG32(ADR_NAV_DATA)) & 0x000007f0 ) >> 4)
+#define GET_MCS (((REG32(ADR_NAV_DATA)) & 0x00007000 ) >> 12)
+#define GET_FRAME_LEN (((REG32(ADR_NAV_DATA)) & 0xffff0000 ) >> 16)
+#define GET_DURATION (((REG32(ADR_CO_NAV)) & 0x0000ffff ) >> 0)
+#define GET_SHA_DST_ADDR (((REG32(ADR_SHA_DST_ADDR)) & 0xffffffff ) >> 0)
+#define GET_SHA_SRC_ADDR (((REG32(ADR_SHA_SRC_ADDR)) & 0xffffffff ) >> 0)
+#define GET_SHA_BUSY (((REG32(ADR_SHA_SETTING)) & 0x00000001 ) >> 0)
+#define GET_SHA_ENDIAN (((REG32(ADR_SHA_SETTING)) & 0x00000002 ) >> 1)
+#define GET_EFS_CLKFREQ (((REG32(ADR_EFUSE_CLK_FREQ)) & 0x00000fff ) >> 0)
+#define GET_LOW_ACTIVE (((REG32(ADR_EFUSE_CLK_FREQ)) & 0x00010000 ) >> 16)
+#define GET_EFS_CLKFREQ_RD (((REG32(ADR_EFUSE_CLK_FREQ)) & 0x0ff00000 ) >> 20)
+#define GET_EFS_PRE_RD (((REG32(ADR_EFUSE_CLK_FREQ)) & 0xf0000000 ) >> 28)
+#define GET_EFS_LDO_ON (((REG32(ADR_EFUSE_LDO_TIME)) & 0x0000ffff ) >> 0)
+#define GET_EFS_LDO_OFF (((REG32(ADR_EFUSE_LDO_TIME)) & 0xffff0000 ) >> 16)
+#define GET_EFS_RDATA_0 (((REG32(ADR_EFUSE_AHB_RDATA_0)) & 0xffffffff ) >> 0)
+#define GET_EFS_WDATA_0 (((REG32(ADR_EFUSE_WDATA_0)) & 0xffffffff ) >> 0)
+#define GET_EFS_RDATA_1 (((REG32(ADR_EFUSE_AHB_RDATA_1)) & 0xffffffff ) >> 0)
+#define GET_EFS_WDATA_1 (((REG32(ADR_EFUSE_WDATA_1)) & 0xffffffff ) >> 0)
+#define GET_EFS_RDATA_2 (((REG32(ADR_EFUSE_AHB_RDATA_2)) & 0xffffffff ) >> 0)
+#define GET_EFS_WDATA_2 (((REG32(ADR_EFUSE_WDATA_2)) & 0xffffffff ) >> 0)
+#define GET_EFS_RDATA_3 (((REG32(ADR_EFUSE_AHB_RDATA_3)) & 0xffffffff ) >> 0)
+#define GET_EFS_WDATA_3 (((REG32(ADR_EFUSE_WDATA_3)) & 0xffffffff ) >> 0)
+#define GET_EFS_RDATA_4 (((REG32(ADR_EFUSE_AHB_RDATA_4)) & 0xffffffff ) >> 0)
+#define GET_EFS_WDATA_4 (((REG32(ADR_EFUSE_WDATA_4)) & 0xffffffff ) >> 0)
+#define GET_EFS_RDATA_5 (((REG32(ADR_EFUSE_AHB_RDATA_5)) & 0xffffffff ) >> 0)
+#define GET_EFS_WDATA_5 (((REG32(ADR_EFUSE_WDATA_5)) & 0xffffffff ) >> 0)
+#define GET_EFS_RDATA_6 (((REG32(ADR_EFUSE_AHB_RDATA_6)) & 0xffffffff ) >> 0)
+#define GET_EFS_WDATA_6 (((REG32(ADR_EFUSE_WDATA_6)) & 0xffffffff ) >> 0)
+#define GET_EFS_RDATA_7 (((REG32(ADR_EFUSE_AHB_RDATA_7)) & 0xffffffff ) >> 0)
+#define GET_EFS_WDATA_7 (((REG32(ADR_EFUSE_WDATA_7)) & 0xffffffff ) >> 0)
+#define GET_EFS_SPI_RD0_EN (((REG32(ADR_EFUSE_SPI_RD0_EN)) & 0x00000001 ) >> 0)
+#define GET_EFS_SPI_RD1_EN (((REG32(ADR_EFUSE_SPI_RD1_EN)) & 0x00000001 ) >> 0)
+#define GET_EFS_SPI_RD2_EN (((REG32(ADR_EFUSE_SPI_RD2_EN)) & 0x00000001 ) >> 0)
+#define GET_EFS_SPI_RD3_EN (((REG32(ADR_EFUSE_SPI_RD3_EN)) & 0x00000001 ) >> 0)
+#define GET_EFS_SPI_RD4_EN (((REG32(ADR_EFUSE_SPI_RD4_EN)) & 0x00000001 ) >> 0)
+#define GET_EFS_SPI_RD5_EN (((REG32(ADR_EFUSE_SPI_RD5_EN)) & 0x00000001 ) >> 0)
+#define GET_EFS_SPI_RD6_EN (((REG32(ADR_EFUSE_SPI_RD6_EN)) & 0x00000001 ) >> 0)
+#define GET_EFS_SPI_RD7_EN (((REG32(ADR_EFUSE_SPI_RD7_EN)) & 0x00000001 ) >> 0)
+#define GET_EFS_SPI_RBUSY (((REG32(ADR_EFUSE_SPI_BUSY)) & 0x00000001 ) >> 0)
+#define GET_EFS_SPI_RDATA_0 (((REG32(ADR_EFUSE_SPI_RDATA_0)) & 0xffffffff ) >> 0)
+#define GET_EFS_SPI_RDATA_1 (((REG32(ADR_EFUSE_SPI_RDATA_1)) & 0xffffffff ) >> 0)
+#define GET_EFS_SPI_RDATA_2 (((REG32(ADR_EFUSE_SPI_RDATA_2)) & 0xffffffff ) >> 0)
+#define GET_EFS_SPI_RDATA_3 (((REG32(ADR_EFUSE_SPI_RDATA_3)) & 0xffffffff ) >> 0)
+#define GET_EFS_SPI_RDATA_4 (((REG32(ADR_EFUSE_SPI_RDATA_4)) & 0xffffffff ) >> 0)
+#define GET_EFS_SPI_RDATA_5 (((REG32(ADR_EFUSE_SPI_RDATA_5)) & 0xffffffff ) >> 0)
+#define GET_EFS_SPI_RDATA_6 (((REG32(ADR_EFUSE_SPI_RDATA_6)) & 0xffffffff ) >> 0)
+#define GET_EFS_SPI_RDATA_7 (((REG32(ADR_EFUSE_SPI_RDATA_7)) & 0xffffffff ) >> 0)
+#define GET_GET_RK (((REG32(ADR_SMS4_CFG1)) & 0x00000001 ) >> 0)
+#define GET_FORCE_GET_RK (((REG32(ADR_SMS4_CFG1)) & 0x00000002 ) >> 1)
+#define GET_SMS4_DESCRY_EN (((REG32(ADR_SMS4_CFG1)) & 0x00000010 ) >> 4)
+#define GET_DEC_DOUT_MSB (((REG32(ADR_SMS4_CFG2)) & 0x00000001 ) >> 0)
+#define GET_DEC_DIN_MSB (((REG32(ADR_SMS4_CFG2)) & 0x00000002 ) >> 1)
+#define GET_ENC_DOUT_MSB (((REG32(ADR_SMS4_CFG2)) & 0x00000004 ) >> 2)
+#define GET_ENC_DIN_MSB (((REG32(ADR_SMS4_CFG2)) & 0x00000008 ) >> 3)
+#define GET_KEY_DIN_MSB (((REG32(ADR_SMS4_CFG2)) & 0x00000010 ) >> 4)
+#define GET_SMS4_CBC_EN (((REG32(ADR_SMS4_MODE1)) & 0x00000001 ) >> 0)
+#define GET_SMS4_CFB_EN (((REG32(ADR_SMS4_MODE1)) & 0x00000002 ) >> 1)
+#define GET_SMS4_OFB_EN (((REG32(ADR_SMS4_MODE1)) & 0x00000004 ) >> 2)
+#define GET_SMS4_START_TRIG (((REG32(ADR_SMS4_TRIG)) & 0x00000001 ) >> 0)
+#define GET_SMS4_BUSY (((REG32(ADR_SMS4_STATUS1)) & 0x00000001 ) >> 0)
+#define GET_SMS4_DONE (((REG32(ADR_SMS4_STATUS2)) & 0x00000001 ) >> 0)
+#define GET_SMS4_DATAIN_0 (((REG32(ADR_SMS4_DATA_IN0)) & 0xffffffff ) >> 0)
+#define GET_SMS4_DATAIN_1 (((REG32(ADR_SMS4_DATA_IN1)) & 0xffffffff ) >> 0)
+#define GET_SMS4_DATAIN_2 (((REG32(ADR_SMS4_DATA_IN2)) & 0xffffffff ) >> 0)
+#define GET_SMS4_DATAIN_3 (((REG32(ADR_SMS4_DATA_IN3)) & 0xffffffff ) >> 0)
+#define GET_SMS4_DATAOUT_0 (((REG32(ADR_SMS4_DATA_OUT0)) & 0xffffffff ) >> 0)
+#define GET_SMS4_DATAOUT_1 (((REG32(ADR_SMS4_DATA_OUT1)) & 0xffffffff ) >> 0)
+#define GET_SMS4_DATAOUT_2 (((REG32(ADR_SMS4_DATA_OUT2)) & 0xffffffff ) >> 0)
+#define GET_SMS4_DATAOUT_3 (((REG32(ADR_SMS4_DATA_OUT3)) & 0xffffffff ) >> 0)
+#define GET_SMS4_KEY_0 (((REG32(ADR_SMS4_KEY_0)) & 0xffffffff ) >> 0)
+#define GET_SMS4_KEY_1 (((REG32(ADR_SMS4_KEY_1)) & 0xffffffff ) >> 0)
+#define GET_SMS4_KEY_2 (((REG32(ADR_SMS4_KEY_2)) & 0xffffffff ) >> 0)
+#define GET_SMS4_KEY_3 (((REG32(ADR_SMS4_KEY_3)) & 0xffffffff ) >> 0)
+#define GET_SMS4_MODE_IV0 (((REG32(ADR_SMS4_MODE_IV0)) & 0xffffffff ) >> 0)
+#define GET_SMS4_MODE_IV1 (((REG32(ADR_SMS4_MODE_IV1)) & 0xffffffff ) >> 0)
+#define GET_SMS4_MODE_IV2 (((REG32(ADR_SMS4_MODE_IV2)) & 0xffffffff ) >> 0)
+#define GET_SMS4_MODE_IV3 (((REG32(ADR_SMS4_MODE_IV3)) & 0xffffffff ) >> 0)
+#define GET_SMS4_OFB_ENC0 (((REG32(ADR_SMS4_OFB_ENC0)) & 0xffffffff ) >> 0)
+#define GET_SMS4_OFB_ENC1 (((REG32(ADR_SMS4_OFB_ENC1)) & 0xffffffff ) >> 0)
+#define GET_SMS4_OFB_ENC2 (((REG32(ADR_SMS4_OFB_ENC2)) & 0xffffffff ) >> 0)
+#define GET_SMS4_OFB_ENC3 (((REG32(ADR_SMS4_OFB_ENC3)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_TB0_31_0 (((REG32(ADR_MRX_MCAST_TB0_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_TB0_47_32 (((REG32(ADR_MRX_MCAST_TB0_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_MASK0_31_0 (((REG32(ADR_MRX_MCAST_MK0_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_MASK0_47_32 (((REG32(ADR_MRX_MCAST_MK0_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_CTRL_0 (((REG32(ADR_MRX_MCAST_CTRL0)) & 0x00000003 ) >> 0)
+#define GET_MRX_MCAST_TB1_31_0 (((REG32(ADR_MRX_MCAST_TB1_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_TB1_47_32 (((REG32(ADR_MRX_MCAST_TB1_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_MASK1_31_0 (((REG32(ADR_MRX_MCAST_MK1_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_MASK1_47_32 (((REG32(ADR_MRX_MCAST_MK1_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_CTRL_1 (((REG32(ADR_MRX_MCAST_CTRL1)) & 0x00000003 ) >> 0)
+#define GET_MRX_MCAST_TB2_31_0 (((REG32(ADR_MRX_MCAST_TB2_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_TB2_47_32 (((REG32(ADR_MRX_MCAST_TB2_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_MASK2_31_0 (((REG32(ADR_MRX_MCAST_MK2_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_MASK2_47_32 (((REG32(ADR_MRX_MCAST_MK2_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_CTRL_2 (((REG32(ADR_MRX_MCAST_CTRL2)) & 0x00000003 ) >> 0)
+#define GET_MRX_MCAST_TB3_31_0 (((REG32(ADR_MRX_MCAST_TB3_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_TB3_47_32 (((REG32(ADR_MRX_MCAST_TB3_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_MASK3_31_0 (((REG32(ADR_MRX_MCAST_MK3_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_MASK3_47_32 (((REG32(ADR_MRX_MCAST_MK3_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_CTRL_3 (((REG32(ADR_MRX_MCAST_CTRL3)) & 0x00000003 ) >> 0)
+#define GET_MRX_PHY_INFO (((REG32(ADR_MRX_PHY_INFO)) & 0xffffffff ) >> 0)
+#define GET_DBG_BA_TYPE (((REG32(ADR_MRX_BA_DBG)) & 0x0000003f ) >> 0)
+#define GET_DBG_BA_SEQ (((REG32(ADR_MRX_BA_DBG)) & 0x000fff00 ) >> 8)
+#define GET_MRX_FLT_TB0 (((REG32(ADR_MRX_FLT_TB0)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB1 (((REG32(ADR_MRX_FLT_TB1)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB2 (((REG32(ADR_MRX_FLT_TB2)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB3 (((REG32(ADR_MRX_FLT_TB3)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB4 (((REG32(ADR_MRX_FLT_TB4)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB5 (((REG32(ADR_MRX_FLT_TB5)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB6 (((REG32(ADR_MRX_FLT_TB6)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB7 (((REG32(ADR_MRX_FLT_TB7)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB8 (((REG32(ADR_MRX_FLT_TB8)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB9 (((REG32(ADR_MRX_FLT_TB9)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB10 (((REG32(ADR_MRX_FLT_TB10)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB11 (((REG32(ADR_MRX_FLT_TB11)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB12 (((REG32(ADR_MRX_FLT_TB12)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB13 (((REG32(ADR_MRX_FLT_TB13)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB14 (((REG32(ADR_MRX_FLT_TB14)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB15 (((REG32(ADR_MRX_FLT_TB15)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_EN0 (((REG32(ADR_MRX_FLT_EN0)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN1 (((REG32(ADR_MRX_FLT_EN1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN2 (((REG32(ADR_MRX_FLT_EN2)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN3 (((REG32(ADR_MRX_FLT_EN3)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN4 (((REG32(ADR_MRX_FLT_EN4)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN5 (((REG32(ADR_MRX_FLT_EN5)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN6 (((REG32(ADR_MRX_FLT_EN6)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN7 (((REG32(ADR_MRX_FLT_EN7)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN8 (((REG32(ADR_MRX_FLT_EN8)) & 0x0000ffff ) >> 0)
+#define GET_MRX_LEN_FLT (((REG32(ADR_MRX_LEN_FLT)) & 0x0000ffff ) >> 0)
+#define GET_RX_FLOW_DATA (((REG32(ADR_RX_FLOW_DATA)) & 0xffffffff ) >> 0)
+#define GET_RX_FLOW_MNG (((REG32(ADR_RX_FLOW_MNG)) & 0x0000ffff ) >> 0)
+#define GET_RX_FLOW_CTRL (((REG32(ADR_RX_FLOW_CTRL)) & 0x0000ffff ) >> 0)
+#define GET_MRX_STP_EN (((REG32(ADR_RX_TIME_STAMP_CFG)) & 0x00000001 ) >> 0)
+#define GET_MRX_STP_OFST (((REG32(ADR_RX_TIME_STAMP_CFG)) & 0x0000ff00 ) >> 8)
+#define GET_DBG_FF_FULL (((REG32(ADR_DBG_FF_FULL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_FF_FULL_CLR (((REG32(ADR_DBG_FF_FULL)) & 0x80000000 ) >> 31)
+#define GET_DBG_WFF_FULL (((REG32(ADR_DBG_WFF_FULL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_WFF_FULL_CLR (((REG32(ADR_DBG_WFF_FULL)) & 0x80000000 ) >> 31)
+#define GET_DBG_MB_FULL (((REG32(ADR_DBG_MB_FULL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_MB_FULL_CLR (((REG32(ADR_DBG_MB_FULL)) & 0x80000000 ) >> 31)
+#define GET_BA_CTRL (((REG32(ADR_BA_CTRL)) & 0x00000003 ) >> 0)
+#define GET_BA_DBG_EN (((REG32(ADR_BA_CTRL)) & 0x00000004 ) >> 2)
+#define GET_BA_AGRE_EN (((REG32(ADR_BA_CTRL)) & 0x00000008 ) >> 3)
+#define GET_BA_TA_31_0 (((REG32(ADR_BA_TA_0)) & 0xffffffff ) >> 0)
+#define GET_BA_TA_47_32 (((REG32(ADR_BA_TA_1)) & 0x0000ffff ) >> 0)
+#define GET_BA_TID (((REG32(ADR_BA_TID)) & 0x0000000f ) >> 0)
+#define GET_BA_ST_SEQ (((REG32(ADR_BA_ST_SEQ)) & 0x00000fff ) >> 0)
+#define GET_BA_SB0 (((REG32(ADR_BA_SB0)) & 0xffffffff ) >> 0)
+#define GET_BA_SB1 (((REG32(ADR_BA_SB1)) & 0xffffffff ) >> 0)
+#define GET_MRX_WD (((REG32(ADR_MRX_WATCH_DOG)) & 0x0001ffff ) >> 0)
+#define GET_ACK_GEN_EN (((REG32(ADR_ACK_GEN_EN)) & 0x00000001 ) >> 0)
+#define GET_BA_GEN_EN (((REG32(ADR_ACK_GEN_EN)) & 0x00000002 ) >> 1)
+#define GET_ACK_GEN_DUR (((REG32(ADR_ACK_GEN_PARA)) & 0x0000ffff ) >> 0)
+#define GET_ACK_GEN_INFO (((REG32(ADR_ACK_GEN_PARA)) & 0x003f0000 ) >> 16)
+#define GET_ACK_GEN_RA_31_0 (((REG32(ADR_ACK_GEN_RA_0)) & 0xffffffff ) >> 0)
+#define GET_ACK_GEN_RA_47_32 (((REG32(ADR_ACK_GEN_RA_1)) & 0x0000ffff ) >> 0)
+#define GET_MIB_LEN_FAIL (((REG32(ADR_MIB_LEN_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_TRAP_HW_ID (((REG32(ADR_TRAP_HW_ID)) & 0x0000000f ) >> 0)
+#define GET_ID_IN_USE (((REG32(ADR_ID_IN_USE)) & 0x000000ff ) >> 0)
+#define GET_MRX_ERR (((REG32(ADR_MRX_ERR)) & 0xffffffff ) >> 0)
+#define GET_W0_T0_SEQ (((REG32(ADR_WSID0_TID0_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W0_T1_SEQ (((REG32(ADR_WSID0_TID1_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W0_T2_SEQ (((REG32(ADR_WSID0_TID2_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W0_T3_SEQ (((REG32(ADR_WSID0_TID3_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W0_T4_SEQ (((REG32(ADR_WSID0_TID4_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W0_T5_SEQ (((REG32(ADR_WSID0_TID5_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W0_T6_SEQ (((REG32(ADR_WSID0_TID6_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W0_T7_SEQ (((REG32(ADR_WSID0_TID7_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W1_T0_SEQ (((REG32(ADR_WSID1_TID0_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W1_T1_SEQ (((REG32(ADR_WSID1_TID1_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W1_T2_SEQ (((REG32(ADR_WSID1_TID2_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W1_T3_SEQ (((REG32(ADR_WSID1_TID3_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W1_T4_SEQ (((REG32(ADR_WSID1_TID4_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W1_T5_SEQ (((REG32(ADR_WSID1_TID5_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W1_T6_SEQ (((REG32(ADR_WSID1_TID6_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W1_T7_SEQ (((REG32(ADR_WSID1_TID7_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_ADDR1A_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00000003 ) >> 0)
+#define GET_ADDR2A_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x0000000c ) >> 2)
+#define GET_ADDR3A_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00000030 ) >> 4)
+#define GET_ADDR1B_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x000000c0 ) >> 6)
+#define GET_ADDR2B_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00000300 ) >> 8)
+#define GET_ADDR3B_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00000c00 ) >> 10)
+#define GET_ADDR3C_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00003000 ) >> 12)
+#define GET_FRM_CTRL (((REG32(ADR_FRAME_TYPE_CNTR_SET)) & 0x0000003f ) >> 0)
+#define GET_CSR_PHY_INFO (((REG32(ADR_PHY_INFO)) & 0x00007fff ) >> 0)
+#define GET_AMPDU_SIG (((REG32(ADR_AMPDU_SIG)) & 0x000000ff ) >> 0)
+#define GET_MIB_AMPDU (((REG32(ADR_MIB_AMPDU)) & 0xffffffff ) >> 0)
+#define GET_LEN_FLT (((REG32(ADR_LEN_FLT)) & 0x0000ffff ) >> 0)
+#define GET_MIB_DELIMITER (((REG32(ADR_MIB_DELIMITER)) & 0x0000ffff ) >> 0)
+#define GET_MTX_INT_Q0_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x00010000 ) >> 16)
+#define GET_MTX_INT_Q0_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x00020000 ) >> 17)
+#define GET_MTX_INT_Q1_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x00040000 ) >> 18)
+#define GET_MTX_INT_Q1_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x00080000 ) >> 19)
+#define GET_MTX_INT_Q2_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x00100000 ) >> 20)
+#define GET_MTX_INT_Q2_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x00200000 ) >> 21)
+#define GET_MTX_INT_Q3_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x00400000 ) >> 22)
+#define GET_MTX_INT_Q3_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x00800000 ) >> 23)
+#define GET_MTX_INT_Q4_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x01000000 ) >> 24)
+#define GET_MTX_INT_Q4_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x02000000 ) >> 25)
+#define GET_MTX_EN_INT_Q0_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x00010000 ) >> 16)
+#define GET_MTX_EN_INT_Q0_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x00020000 ) >> 17)
+#define GET_MTX_EN_INT_Q1_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x00040000 ) >> 18)
+#define GET_MTX_EN_INT_Q1_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x00080000 ) >> 19)
+#define GET_MTX_EN_INT_Q2_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x00100000 ) >> 20)
+#define GET_MTX_EN_INT_Q2_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x00200000 ) >> 21)
+#define GET_MTX_EN_INT_Q3_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x00400000 ) >> 22)
+#define GET_MTX_EN_INT_Q3_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x00800000 ) >> 23)
+#define GET_MTX_EN_INT_Q4_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x01000000 ) >> 24)
+#define GET_MTX_EN_INT_Q4_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x02000000 ) >> 25)
+#define GET_MTX_MTX2PHY_SLOW (((REG32(ADR_MTX_MISC_EN)) & 0x00000001 ) >> 0)
+#define GET_MTX_M2M_SLOW_PRD (((REG32(ADR_MTX_MISC_EN)) & 0x0000000e ) >> 1)
+#define GET_MTX_AMPDU_CRC_AUTO (((REG32(ADR_MTX_MISC_EN)) & 0x00000020 ) >> 5)
+#define GET_MTX_FAST_RSP_MODE (((REG32(ADR_MTX_MISC_EN)) & 0x00000040 ) >> 6)
+#define GET_MTX_RAW_DATA_MODE (((REG32(ADR_MTX_MISC_EN)) & 0x00000080 ) >> 7)
+#define GET_MTX_ACK_DUR0 (((REG32(ADR_MTX_MISC_EN)) & 0x00000100 ) >> 8)
+#define GET_MTX_TSF_AUTO_BCN (((REG32(ADR_MTX_MISC_EN)) & 0x00000400 ) >> 10)
+#define GET_MTX_TSF_AUTO_MISC (((REG32(ADR_MTX_MISC_EN)) & 0x00000800 ) >> 11)
+#define GET_MTX_FORCE_CS_IDLE (((REG32(ADR_MTX_MISC_EN)) & 0x00001000 ) >> 12)
+#define GET_MTX_FORCE_BKF_RXEN0 (((REG32(ADR_MTX_MISC_EN)) & 0x00002000 ) >> 13)
+#define GET_MTX_FORCE_DMA_RXEN0 (((REG32(ADR_MTX_MISC_EN)) & 0x00004000 ) >> 14)
+#define GET_MTX_FORCE_RXEN0 (((REG32(ADR_MTX_MISC_EN)) & 0x00008000 ) >> 15)
+#define GET_MTX_HALT_Q_MB (((REG32(ADR_MTX_MISC_EN)) & 0x003f0000 ) >> 16)
+#define GET_MTX_CTS_SET_DIF (((REG32(ADR_MTX_MISC_EN)) & 0x00400000 ) >> 22)
+#define GET_MTX_AMPDU_SET_DIF (((REG32(ADR_MTX_MISC_EN)) & 0x00800000 ) >> 23)
+#define GET_MTX_EDCCA_TOUT (((REG32(ADR_MTX_EDCCA_TOUT)) & 0x000003ff ) >> 0)
+#define GET_MTX_INT_BCN (((REG32(ADR_MTX_BCN_INT_STS)) & 0x00000002 ) >> 1)
+#define GET_MTX_INT_DTIM (((REG32(ADR_MTX_BCN_INT_STS)) & 0x00000008 ) >> 3)
+#define GET_MTX_EN_INT_BCN (((REG32(ADR_MTX_BCN_EN_INT)) & 0x00000002 ) >> 1)
+#define GET_MTX_EN_INT_DTIM (((REG32(ADR_MTX_BCN_EN_INT)) & 0x00000008 ) >> 3)
+#define GET_MTX_BCN_TIMER_EN (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00000001 ) >> 0)
+#define GET_MTX_TIME_STAMP_AUTO_FILL (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00000002 ) >> 1)
+#define GET_MTX_TSF_TIMER_EN (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00000020 ) >> 5)
+#define GET_MTX_HALT_MNG_UNTIL_DTIM (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00000040 ) >> 6)
+#define GET_MTX_INT_DTIM_NUM (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x0000ff00 ) >> 8)
+#define GET_MTX_AUTO_FLUSH_Q4 (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00010000 ) >> 16)
+#define GET_MTX_BCN_PKTID_CH_LOCK (((REG32(ADR_MTX_BCN_MISC)) & 0x00000001 ) >> 0)
+#define GET_MTX_BCN_CFG_VLD (((REG32(ADR_MTX_BCN_MISC)) & 0x00000006 ) >> 1)
+#define GET_MTX_AUTO_BCN_ONGOING (((REG32(ADR_MTX_BCN_MISC)) & 0x00000008 ) >> 3)
+#define GET_MTX_BCN_TIMER (((REG32(ADR_MTX_BCN_MISC)) & 0xffff0000 ) >> 16)
+#define GET_MTX_BCN_PERIOD (((REG32(ADR_MTX_BCN_PRD)) & 0x0000ffff ) >> 0)
+#define GET_MTX_DTIM_NUM (((REG32(ADR_MTX_BCN_PRD)) & 0xff000000 ) >> 24)
+#define GET_MTX_BCN_TSF_L (((REG32(ADR_MTX_BCN_TSF_L)) & 0xffffffff ) >> 0)
+#define GET_MTX_BCN_TSF_U (((REG32(ADR_MTX_BCN_TSF_U)) & 0xffffffff ) >> 0)
+#define GET_MTX_BCN_PKT_ID0 (((REG32(ADR_MTX_BCN_CFG0)) & 0x0000007f ) >> 0)
+#define GET_MTX_DTIM_OFST0 (((REG32(ADR_MTX_BCN_CFG0)) & 0x03ff0000 ) >> 16)
+#define GET_MTX_BCN_PKT_ID1 (((REG32(ADR_MTX_BCN_CFG1)) & 0x0000007f ) >> 0)
+#define GET_MTX_DTIM_OFST1 (((REG32(ADR_MTX_BCN_CFG1)) & 0x03ff0000 ) >> 16)
+#define GET_MTX_CCA (((REG32(ADR_MTX_STATUS)) & 0x00000001 ) >> 0)
+#define GET_MRX_CCA (((REG32(ADR_MTX_STATUS)) & 0x00000002 ) >> 1)
+#define GET_MTX_DMA_FSM (((REG32(ADR_MTX_STATUS)) & 0x0000001c ) >> 2)
+#define GET_CH_ST_FSM (((REG32(ADR_MTX_STATUS)) & 0x000000e0 ) >> 5)
+#define GET_MTX_GNT_LOCK (((REG32(ADR_MTX_STATUS)) & 0x00000100 ) >> 8)
+#define GET_MTX_DMA_REQ (((REG32(ADR_MTX_STATUS)) & 0x00000200 ) >> 9)
+#define GET_MTX_Q_REQ (((REG32(ADR_MTX_STATUS)) & 0x00000400 ) >> 10)
+#define GET_MTX_TX_EN (((REG32(ADR_MTX_STATUS)) & 0x00000800 ) >> 11)
+#define GET_MRX_RX_EN (((REG32(ADR_MTX_STATUS)) & 0x00001000 ) >> 12)
+#define GET_DBG_PRTC_PRD (((REG32(ADR_MTX_STATUS)) & 0x00002000 ) >> 13)
+#define GET_DBG_DMA_RDY (((REG32(ADR_MTX_STATUS)) & 0x00004000 ) >> 14)
+#define GET_DBG_WAIT_RSP (((REG32(ADR_MTX_STATUS)) & 0x00008000 ) >> 15)
+#define GET_DBG_CFRM_BUSY (((REG32(ADR_MTX_STATUS)) & 0x00010000 ) >> 16)
+#define GET_DBG_RST (((REG32(ADR_MTX_DBG_CTRL)) & 0x00000001 ) >> 0)
+#define GET_DBG_MODE (((REG32(ADR_MTX_DBG_CTRL)) & 0x00000002 ) >> 1)
+#define GET_MB_REQ_DUR (((REG32(ADR_MTX_DBG_DAT0)) & 0x0000ffff ) >> 0)
+#define GET_RX_EN_DUR (((REG32(ADR_MTX_DBG_DAT0)) & 0xffff0000 ) >> 16)
+#define GET_RX_CS_DUR (((REG32(ADR_MTX_DBG_DAT1)) & 0x0000ffff ) >> 0)
+#define GET_TX_CCA_DUR (((REG32(ADR_MTX_DBG_DAT1)) & 0xffff0000 ) >> 16)
+#define GET_Q_REQ_DUR (((REG32(ADR_MTX_DBG_DAT2)) & 0x0000ffff ) >> 0)
+#define GET_CH_STA0_DUR (((REG32(ADR_MTX_DBG_DAT2)) & 0xffff0000 ) >> 16)
+#define GET_MTX_DUR_RSP_TOUT_B (((REG32(ADR_MTX_DUR_TOUT)) & 0x000000ff ) >> 0)
+#define GET_MTX_DUR_RSP_TOUT_G (((REG32(ADR_MTX_DUR_TOUT)) & 0x0000ff00 ) >> 8)
+#define GET_MTX_DUR_RSP_SIFS (((REG32(ADR_MTX_DUR_IFS)) & 0x000000ff ) >> 0)
+#define GET_MTX_DUR_BURST_SIFS (((REG32(ADR_MTX_DUR_IFS)) & 0x0000ff00 ) >> 8)
+#define GET_MTX_DUR_SLOT (((REG32(ADR_MTX_DUR_IFS)) & 0x003f0000 ) >> 16)
+#define GET_MTX_DUR_RSP_EIFS (((REG32(ADR_MTX_DUR_IFS)) & 0xffc00000 ) >> 22)
+#define GET_MTX_DUR_RSP_SIFS_G (((REG32(ADR_MTX_DUR_SIFS_G)) & 0x000000ff ) >> 0)
+#define GET_MTX_DUR_BURST_SIFS_G (((REG32(ADR_MTX_DUR_SIFS_G)) & 0x0000ff00 ) >> 8)
+#define GET_MTX_DUR_SLOT_G (((REG32(ADR_MTX_DUR_SIFS_G)) & 0x003f0000 ) >> 16)
+#define GET_MTX_DUR_RSP_EIFS_G (((REG32(ADR_MTX_DUR_SIFS_G)) & 0xffc00000 ) >> 22)
+#define GET_CH_STA1_DUR (((REG32(ADR_MTX_DBG_DAT3)) & 0x0000ffff ) >> 0)
+#define GET_CH_STA2_DUR (((REG32(ADR_MTX_DBG_DAT3)) & 0xffff0000 ) >> 16)
+#define GET_MTX_NAV (((REG32(ADR_MTX_NAV)) & 0x0000ffff ) >> 0)
+#define GET_MTX_MIB_CNT0 (((REG32(ADR_MTX_MIB_WSID0)) & 0x3fffffff ) >> 0)
+#define GET_MTX_MIB_EN0 (((REG32(ADR_MTX_MIB_WSID0)) & 0x40000000 ) >> 30)
+#define GET_MTX_MIB_CNT1 (((REG32(ADR_MTX_MIB_WSID1)) & 0x3fffffff ) >> 0)
+#define GET_MTX_MIB_EN1 (((REG32(ADR_MTX_MIB_WSID1)) & 0x40000000 ) >> 30)
+#define GET_CH_STA3_DUR (((REG32(ADR_MTX_DBG_DAT4)) & 0x0000ffff ) >> 0)
+#define GET_CH_STA4_DUR (((REG32(ADR_MTX_DBG_DAT4)) & 0xffff0000 ) >> 16)
+#define GET_TXQ0_MTX_Q_PRE_LD (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000002 ) >> 1)
+#define GET_TXQ0_MTX_Q_BKF_CNT_FIXED (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000004 ) >> 2)
+#define GET_TXQ0_MTX_Q_TXOP_SUB_FRM_TIME (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000008 ) >> 3)
+#define GET_TXQ0_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4)
+#define GET_TXQ0_MTX_Q_TXOP_FRC_BUR (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000020 ) >> 5)
+#define GET_TXQ0_MTX_Q_RND_MODE (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x000000c0 ) >> 6)
+#define GET_TXQ0_MTX_Q_AIFSN (((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0x0000000f ) >> 0)
+#define GET_TXQ0_MTX_Q_ECWMIN (((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8)
+#define GET_TXQ0_MTX_Q_ECWMAX (((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12)
+#define GET_TXQ0_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16)
+#define GET_TXQ0_MTX_Q_BKF_CNT (((REG32(ADR_TXQ0_MTX_Q_BKF_CNT)) & 0x0000ffff ) >> 0)
+#define GET_TXQ0_MTX_Q_SRC_LIMIT (((REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) & 0x000000ff ) >> 0)
+#define GET_TXQ0_MTX_Q_LRC_LIMIT (((REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) & 0x0000ff00 ) >> 8)
+#define GET_TXQ0_MTX_Q_ID_MAP_L (((REG32(ADR_TXQ0_MTX_Q_ID_MAP_L)) & 0xffffffff ) >> 0)
+#define GET_TXQ0_MTX_Q_TXOP_CH_THD (((REG32(ADR_TXQ0_MTX_Q_TXOP_CH_THD)) & 0x0000ffff ) >> 0)
+#define GET_TXQ0_MTX_Q_TXOP_OV_THD (((REG32(ADR_TXQ0_MTX_Q_TXOP_OV_THD)) & 0x0000ffff ) >> 0)
+#define GET_TXQ1_MTX_Q_PRE_LD (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000002 ) >> 1)
+#define GET_TXQ1_MTX_Q_BKF_CNT_FIXED (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000004 ) >> 2)
+#define GET_TXQ1_MTX_Q_TXOP_SUB_FRM_TIME (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000008 ) >> 3)
+#define GET_TXQ1_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4)
+#define GET_TXQ1_MTX_Q_TXOP_FRC_BUR (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000020 ) >> 5)
+#define GET_TXQ1_MTX_Q_RND_MODE (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x000000c0 ) >> 6)
+#define GET_TXQ1_MTX_Q_AIFSN (((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0x0000000f ) >> 0)
+#define GET_TXQ1_MTX_Q_ECWMIN (((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8)
+#define GET_TXQ1_MTX_Q_ECWMAX (((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12)
+#define GET_TXQ1_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16)
+#define GET_TXQ1_MTX_Q_BKF_CNT (((REG32(ADR_TXQ1_MTX_Q_BKF_CNT)) & 0x0000ffff ) >> 0)
+#define GET_TXQ1_MTX_Q_SRC_LIMIT (((REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) & 0x000000ff ) >> 0)
+#define GET_TXQ1_MTX_Q_LRC_LIMIT (((REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) & 0x0000ff00 ) >> 8)
+#define GET_TXQ1_MTX_Q_ID_MAP_L (((REG32(ADR_TXQ1_MTX_Q_ID_MAP_L)) & 0xffffffff ) >> 0)
+#define GET_TXQ1_MTX_Q_TXOP_CH_THD (((REG32(ADR_TXQ1_MTX_Q_TXOP_CH_THD)) & 0x0000ffff ) >> 0)
+#define GET_TXQ1_MTX_Q_TXOP_OV_THD (((REG32(ADR_TXQ1_MTX_Q_TXOP_OV_THD)) & 0x0000ffff ) >> 0)
+#define GET_TXQ2_MTX_Q_PRE_LD (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000002 ) >> 1)
+#define GET_TXQ2_MTX_Q_BKF_CNT_FIXED (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000004 ) >> 2)
+#define GET_TXQ2_MTX_Q_TXOP_SUB_FRM_TIME (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000008 ) >> 3)
+#define GET_TXQ2_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4)
+#define GET_TXQ2_MTX_Q_TXOP_FRC_BUR (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000020 ) >> 5)
+#define GET_TXQ2_MTX_Q_RND_MODE (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x000000c0 ) >> 6)
+#define GET_TXQ2_MTX_Q_AIFSN (((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0x0000000f ) >> 0)
+#define GET_TXQ2_MTX_Q_ECWMIN (((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8)
+#define GET_TXQ2_MTX_Q_ECWMAX (((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12)
+#define GET_TXQ2_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16)
+#define GET_TXQ2_MTX_Q_BKF_CNT (((REG32(ADR_TXQ2_MTX_Q_BKF_CNT)) & 0x0000ffff ) >> 0)
+#define GET_TXQ2_MTX_Q_SRC_LIMIT (((REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) & 0x000000ff ) >> 0)
+#define GET_TXQ2_MTX_Q_LRC_LIMIT (((REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) & 0x0000ff00 ) >> 8)
+#define GET_TXQ2_MTX_Q_ID_MAP_L (((REG32(ADR_TXQ2_MTX_Q_ID_MAP_L)) & 0xffffffff ) >> 0)
+#define GET_TXQ2_MTX_Q_TXOP_CH_THD (((REG32(ADR_TXQ2_MTX_Q_TXOP_CH_THD)) & 0x0000ffff ) >> 0)
+#define GET_TXQ2_MTX_Q_TXOP_OV_THD (((REG32(ADR_TXQ2_MTX_Q_TXOP_OV_THD)) & 0x0000ffff ) >> 0)
+#define GET_TXQ3_MTX_Q_PRE_LD (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000002 ) >> 1)
+#define GET_TXQ3_MTX_Q_BKF_CNT_FIXED (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000004 ) >> 2)
+#define GET_TXQ3_MTX_Q_TXOP_SUB_FRM_TIME (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000008 ) >> 3)
+#define GET_TXQ3_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4)
+#define GET_TXQ3_MTX_Q_TXOP_FRC_BUR (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000020 ) >> 5)
+#define GET_TXQ3_MTX_Q_RND_MODE (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x000000c0 ) >> 6)
+#define GET_TXQ3_MTX_Q_AIFSN (((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0x0000000f ) >> 0)
+#define GET_TXQ3_MTX_Q_ECWMIN (((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8)
+#define GET_TXQ3_MTX_Q_ECWMAX (((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12)
+#define GET_TXQ3_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16)
+#define GET_TXQ3_MTX_Q_BKF_CNT (((REG32(ADR_TXQ3_MTX_Q_BKF_CNT)) & 0x0000ffff ) >> 0)
+#define GET_TXQ3_MTX_Q_SRC_LIMIT (((REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) & 0x000000ff ) >> 0)
+#define GET_TXQ3_MTX_Q_LRC_LIMIT (((REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) & 0x0000ff00 ) >> 8)
+#define GET_TXQ3_MTX_Q_ID_MAP_L (((REG32(ADR_TXQ3_MTX_Q_ID_MAP_L)) & 0xffffffff ) >> 0)
+#define GET_TXQ3_MTX_Q_TXOP_CH_THD (((REG32(ADR_TXQ3_MTX_Q_TXOP_CH_THD)) & 0x0000ffff ) >> 0)
+#define GET_TXQ3_MTX_Q_TXOP_OV_THD (((REG32(ADR_TXQ3_MTX_Q_TXOP_OV_THD)) & 0x0000ffff ) >> 0)
+#define GET_TXQ4_MTX_Q_PRE_LD (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000002 ) >> 1)
+#define GET_TXQ4_MTX_Q_BKF_CNT_FIXED (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000004 ) >> 2)
+#define GET_TXQ4_MTX_Q_TXOP_SUB_FRM_TIME (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000008 ) >> 3)
+#define GET_TXQ4_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4)
+#define GET_TXQ4_MTX_Q_TXOP_FRC_BUR (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000020 ) >> 5)
+#define GET_TXQ4_MTX_Q_RND_MODE (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x000000c0 ) >> 6)
+#define GET_TXQ4_MTX_Q_AIFSN (((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0x0000000f ) >> 0)
+#define GET_TXQ4_MTX_Q_ECWMIN (((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8)
+#define GET_TXQ4_MTX_Q_ECWMAX (((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12)
+#define GET_TXQ4_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16)
+#define GET_TXQ4_MTX_Q_BKF_CNT (((REG32(ADR_TXQ4_MTX_Q_BKF_CNT)) & 0x0000ffff ) >> 0)
+#define GET_TXQ4_MTX_Q_SRC_LIMIT (((REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) & 0x000000ff ) >> 0)
+#define GET_TXQ4_MTX_Q_LRC_LIMIT (((REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) & 0x0000ff00 ) >> 8)
+#define GET_TXQ4_MTX_Q_ID_MAP_L (((REG32(ADR_TXQ4_MTX_Q_ID_MAP_L)) & 0xffffffff ) >> 0)
+#define GET_TXQ4_MTX_Q_TXOP_CH_THD (((REG32(ADR_TXQ4_MTX_Q_TXOP_CH_THD)) & 0x0000ffff ) >> 0)
+#define GET_TXQ4_MTX_Q_TXOP_OV_THD (((REG32(ADR_TXQ4_MTX_Q_TXOP_OV_THD)) & 0x0000ffff ) >> 0)
+#define GET_VALID0 (((REG32(ADR_WSID0)) & 0x00000001 ) >> 0)
+#define GET_PEER_QOS_EN0 (((REG32(ADR_WSID0)) & 0x00000002 ) >> 1)
+#define GET_PEER_OP_MODE0 (((REG32(ADR_WSID0)) & 0x0000000c ) >> 2)
+#define GET_PEER_HT_MODE0 (((REG32(ADR_WSID0)) & 0x00000030 ) >> 4)
+#define GET_PEER_MAC0_31_0 (((REG32(ADR_PEER_MAC0_0)) & 0xffffffff ) >> 0)
+#define GET_PEER_MAC0_47_32 (((REG32(ADR_PEER_MAC0_1)) & 0x0000ffff ) >> 0)
+#define GET_TX_ACK_POLICY_0_0 (((REG32(ADR_TX_ACK_POLICY_0_0)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_0 (((REG32(ADR_TX_SEQ_CTRL_0_0)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_0_1 (((REG32(ADR_TX_ACK_POLICY_0_1)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_1 (((REG32(ADR_TX_SEQ_CTRL_0_1)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_0_2 (((REG32(ADR_TX_ACK_POLICY_0_2)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_2 (((REG32(ADR_TX_SEQ_CTRL_0_2)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_0_3 (((REG32(ADR_TX_ACK_POLICY_0_3)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_3 (((REG32(ADR_TX_SEQ_CTRL_0_3)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_0_4 (((REG32(ADR_TX_ACK_POLICY_0_4)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_4 (((REG32(ADR_TX_SEQ_CTRL_0_4)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_0_5 (((REG32(ADR_TX_ACK_POLICY_0_5)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_5 (((REG32(ADR_TX_SEQ_CTRL_0_5)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_0_6 (((REG32(ADR_TX_ACK_POLICY_0_6)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_6 (((REG32(ADR_TX_SEQ_CTRL_0_6)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_0_7 (((REG32(ADR_TX_ACK_POLICY_0_7)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_7 (((REG32(ADR_TX_SEQ_CTRL_0_7)) & 0x00000fff ) >> 0)
+#define GET_VALID1 (((REG32(ADR_WSID1)) & 0x00000001 ) >> 0)
+#define GET_PEER_QOS_EN1 (((REG32(ADR_WSID1)) & 0x00000002 ) >> 1)
+#define GET_PEER_OP_MODE1 (((REG32(ADR_WSID1)) & 0x0000000c ) >> 2)
+#define GET_PEER_HT_MODE1 (((REG32(ADR_WSID1)) & 0x00000030 ) >> 4)
+#define GET_PEER_MAC1_31_0 (((REG32(ADR_PEER_MAC1_0)) & 0xffffffff ) >> 0)
+#define GET_PEER_MAC1_47_32 (((REG32(ADR_PEER_MAC1_1)) & 0x0000ffff ) >> 0)
+#define GET_TX_ACK_POLICY_1_0 (((REG32(ADR_TX_ACK_POLICY_1_0)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_0 (((REG32(ADR_TX_SEQ_CTRL_1_0)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_1_1 (((REG32(ADR_TX_ACK_POLICY_1_1)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_1 (((REG32(ADR_TX_SEQ_CTRL_1_1)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_1_2 (((REG32(ADR_TX_ACK_POLICY_1_2)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_2 (((REG32(ADR_TX_SEQ_CTRL_1_2)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_1_3 (((REG32(ADR_TX_ACK_POLICY_1_3)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_3 (((REG32(ADR_TX_SEQ_CTRL_1_3)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_1_4 (((REG32(ADR_TX_ACK_POLICY_1_4)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_4 (((REG32(ADR_TX_SEQ_CTRL_1_4)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_1_5 (((REG32(ADR_TX_ACK_POLICY_1_5)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_5 (((REG32(ADR_TX_SEQ_CTRL_1_5)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_1_6 (((REG32(ADR_TX_ACK_POLICY_1_6)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_6 (((REG32(ADR_TX_SEQ_CTRL_1_6)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_1_7 (((REG32(ADR_TX_ACK_POLICY_1_7)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_7 (((REG32(ADR_TX_SEQ_CTRL_1_7)) & 0x00000fff ) >> 0)
+#define GET_INFO0 (((REG32(ADR_INFO0)) & 0xffffffff ) >> 0)
+#define GET_INFO1 (((REG32(ADR_INFO1)) & 0xffffffff ) >> 0)
+#define GET_INFO2 (((REG32(ADR_INFO2)) & 0xffffffff ) >> 0)
+#define GET_INFO3 (((REG32(ADR_INFO3)) & 0xffffffff ) >> 0)
+#define GET_INFO4 (((REG32(ADR_INFO4)) & 0xffffffff ) >> 0)
+#define GET_INFO5 (((REG32(ADR_INFO5)) & 0xffffffff ) >> 0)
+#define GET_INFO6 (((REG32(ADR_INFO6)) & 0xffffffff ) >> 0)
+#define GET_INFO7 (((REG32(ADR_INFO7)) & 0xffffffff ) >> 0)
+#define GET_INFO8 (((REG32(ADR_INFO8)) & 0xffffffff ) >> 0)
+#define GET_INFO9 (((REG32(ADR_INFO9)) & 0xffffffff ) >> 0)
+#define GET_INFO10 (((REG32(ADR_INFO10)) & 0xffffffff ) >> 0)
+#define GET_INFO11 (((REG32(ADR_INFO11)) & 0xffffffff ) >> 0)
+#define GET_INFO12 (((REG32(ADR_INFO12)) & 0xffffffff ) >> 0)
+#define GET_INFO13 (((REG32(ADR_INFO13)) & 0xffffffff ) >> 0)
+#define GET_INFO14 (((REG32(ADR_INFO14)) & 0xffffffff ) >> 0)
+#define GET_INFO15 (((REG32(ADR_INFO15)) & 0xffffffff ) >> 0)
+#define GET_INFO16 (((REG32(ADR_INFO16)) & 0xffffffff ) >> 0)
+#define GET_INFO17 (((REG32(ADR_INFO17)) & 0xffffffff ) >> 0)
+#define GET_INFO18 (((REG32(ADR_INFO18)) & 0xffffffff ) >> 0)
+#define GET_INFO19 (((REG32(ADR_INFO19)) & 0xffffffff ) >> 0)
+#define GET_INFO20 (((REG32(ADR_INFO20)) & 0xffffffff ) >> 0)
+#define GET_INFO21 (((REG32(ADR_INFO21)) & 0xffffffff ) >> 0)
+#define GET_INFO22 (((REG32(ADR_INFO22)) & 0xffffffff ) >> 0)
+#define GET_INFO23 (((REG32(ADR_INFO23)) & 0xffffffff ) >> 0)
+#define GET_INFO24 (((REG32(ADR_INFO24)) & 0xffffffff ) >> 0)
+#define GET_INFO25 (((REG32(ADR_INFO25)) & 0xffffffff ) >> 0)
+#define GET_INFO26 (((REG32(ADR_INFO26)) & 0xffffffff ) >> 0)
+#define GET_INFO27 (((REG32(ADR_INFO27)) & 0xffffffff ) >> 0)
+#define GET_INFO28 (((REG32(ADR_INFO28)) & 0xffffffff ) >> 0)
+#define GET_INFO29 (((REG32(ADR_INFO29)) & 0xffffffff ) >> 0)
+#define GET_INFO30 (((REG32(ADR_INFO30)) & 0xffffffff ) >> 0)
+#define GET_INFO31 (((REG32(ADR_INFO31)) & 0xffffffff ) >> 0)
+#define GET_INFO32 (((REG32(ADR_INFO32)) & 0xffffffff ) >> 0)
+#define GET_INFO33 (((REG32(ADR_INFO33)) & 0xffffffff ) >> 0)
+#define GET_INFO34 (((REG32(ADR_INFO34)) & 0xffffffff ) >> 0)
+#define GET_INFO35 (((REG32(ADR_INFO35)) & 0xffffffff ) >> 0)
+#define GET_INFO36 (((REG32(ADR_INFO36)) & 0xffffffff ) >> 0)
+#define GET_INFO37 (((REG32(ADR_INFO37)) & 0xffffffff ) >> 0)
+#define GET_INFO38 (((REG32(ADR_INFO38)) & 0xffffffff ) >> 0)
+#define GET_INFO_MASK (((REG32(ADR_INFO_MASK)) & 0xffffffff ) >> 0)
+#define GET_INFO_DEF_RATE (((REG32(ADR_INFO_RATE_OFFSET)) & 0x0000003f ) >> 0)
+#define GET_INFO_MRX_OFFSET (((REG32(ADR_INFO_RATE_OFFSET)) & 0x000f0000 ) >> 16)
+#define GET_BCAST_RATEUNKNOW (((REG32(ADR_INFO_RATE_OFFSET)) & 0x3f000000 ) >> 24)
+#define GET_INFO_IDX_TBL_ADDR (((REG32(ADR_INFO_IDX_ADDR)) & 0xffffffff ) >> 0)
+#define GET_INFO_LEN_TBL_ADDR (((REG32(ADR_INFO_LEN_ADDR)) & 0xffffffff ) >> 0)
+#define GET_IC_TAG_31_0 (((REG32(ADR_IC_TIME_TAG_0)) & 0xffffffff ) >> 0)
+#define GET_IC_TAG_63_32 (((REG32(ADR_IC_TIME_TAG_1)) & 0xffffffff ) >> 0)
+#define GET_CH1_PRI (((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0x00000003 ) >> 0)
+#define GET_CH2_PRI (((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0x00000300 ) >> 8)
+#define GET_CH3_PRI (((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0x00030000 ) >> 16)
+#define GET_RG_MAC_LPBK (((REG32(ADR_MAC_MODE)) & 0x00000001 ) >> 0)
+#define GET_RG_MAC_M2M (((REG32(ADR_MAC_MODE)) & 0x00000002 ) >> 1)
+#define GET_RG_PHY_LPBK (((REG32(ADR_MAC_MODE)) & 0x00000004 ) >> 2)
+#define GET_RG_LPBK_RX_EN (((REG32(ADR_MAC_MODE)) & 0x00000008 ) >> 3)
+#define GET_EXT_MAC_MODE (((REG32(ADR_MAC_MODE)) & 0x00000010 ) >> 4)
+#define GET_EXT_PHY_MODE (((REG32(ADR_MAC_MODE)) & 0x00000020 ) >> 5)
+#define GET_ASIC_TAG (((REG32(ADR_MAC_MODE)) & 0xff000000 ) >> 24)
+#define GET_HCI_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000001 ) >> 0)
+#define GET_CO_PROC_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000002 ) >> 1)
+#define GET_MTX_MISC_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000008 ) >> 3)
+#define GET_MTX_QUE_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000010 ) >> 4)
+#define GET_MTX_CHST_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000020 ) >> 5)
+#define GET_MTX_BCN_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000040 ) >> 6)
+#define GET_MRX_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000080 ) >> 7)
+#define GET_AMPDU_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000100 ) >> 8)
+#define GET_MMU_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000200 ) >> 9)
+#define GET_ID_MNG_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000800 ) >> 11)
+#define GET_MBOX_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00001000 ) >> 12)
+#define GET_SCRT_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00002000 ) >> 13)
+#define GET_MIC_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00004000 ) >> 14)
+#define GET_CO_PROC_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000002 ) >> 1)
+#define GET_MTX_MISC_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000008 ) >> 3)
+#define GET_MTX_QUE_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000010 ) >> 4)
+#define GET_MTX_CHST_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000020 ) >> 5)
+#define GET_MTX_BCN_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000040 ) >> 6)
+#define GET_MRX_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000080 ) >> 7)
+#define GET_AMPDU_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000100 ) >> 8)
+#define GET_ID_MNG_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00004000 ) >> 14)
+#define GET_MBOX_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00008000 ) >> 15)
+#define GET_SCRT_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00010000 ) >> 16)
+#define GET_MIC_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00020000 ) >> 17)
+#define GET_CO_PROC_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000002 ) >> 1)
+#define GET_MTX_MISC_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000008 ) >> 3)
+#define GET_MTX_QUE0_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000010 ) >> 4)
+#define GET_MTX_QUE1_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000020 ) >> 5)
+#define GET_MTX_QUE2_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000040 ) >> 6)
+#define GET_MTX_QUE3_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000080 ) >> 7)
+#define GET_MTX_QUE4_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000100 ) >> 8)
+#define GET_MTX_QUE5_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000200 ) >> 9)
+#define GET_MRX_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000400 ) >> 10)
+#define GET_AMPDU_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000800 ) >> 11)
+#define GET_SCRT_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00002000 ) >> 13)
+#define GET_ID_MNG_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00004000 ) >> 14)
+#define GET_MBOX_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00008000 ) >> 15)
+#define GET_HCI_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000001 ) >> 0)
+#define GET_CO_PROC_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000002 ) >> 1)
+#define GET_MTX_MISC_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000008 ) >> 3)
+#define GET_MTX_QUE_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000010 ) >> 4)
+#define GET_MRX_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000020 ) >> 5)
+#define GET_AMPDU_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000040 ) >> 6)
+#define GET_MMU_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000080 ) >> 7)
+#define GET_ID_MNG_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000200 ) >> 9)
+#define GET_MBOX_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000400 ) >> 10)
+#define GET_SCRT_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000800 ) >> 11)
+#define GET_MIC_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00001000 ) >> 12)
+#define GET_MIB_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00002000 ) >> 13)
+#define GET_HCI_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000001 ) >> 0)
+#define GET_CO_PROC_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000002 ) >> 1)
+#define GET_MTX_MISC_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000008 ) >> 3)
+#define GET_MTX_QUE_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000010 ) >> 4)
+#define GET_MRX_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000020 ) >> 5)
+#define GET_AMPDU_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000040 ) >> 6)
+#define GET_ID_MNG_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00001000 ) >> 12)
+#define GET_MBOX_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00002000 ) >> 13)
+#define GET_SCRT_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00004000 ) >> 14)
+#define GET_MIC_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00008000 ) >> 15)
+#define GET_CO_PROC_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00000002 ) >> 1)
+#define GET_MRX_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00000400 ) >> 10)
+#define GET_AMPDU_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00000800 ) >> 11)
+#define GET_SCRT_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00002000 ) >> 13)
+#define GET_ID_MNG_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00004000 ) >> 14)
+#define GET_MBOX_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00008000 ) >> 15)
+#define GET_OP_MODE (((REG32(ADR_GLBLE_SET)) & 0x00000003 ) >> 0)
+#define GET_HT_MODE (((REG32(ADR_GLBLE_SET)) & 0x0000000c ) >> 2)
+#define GET_QOS_EN (((REG32(ADR_GLBLE_SET)) & 0x00000010 ) >> 4)
+#define GET_PB_OFFSET (((REG32(ADR_GLBLE_SET)) & 0x0000ff00 ) >> 8)
+#define GET_SNIFFER_MODE (((REG32(ADR_GLBLE_SET)) & 0x00010000 ) >> 16)
+#define GET_DUP_FLT (((REG32(ADR_GLBLE_SET)) & 0x00020000 ) >> 17)
+#define GET_TX_PKT_RSVD (((REG32(ADR_GLBLE_SET)) & 0x001c0000 ) >> 18)
+#define GET_AMPDU_SNIFFER (((REG32(ADR_GLBLE_SET)) & 0x00200000 ) >> 21)
+#define GET_REASON_TRAP0 (((REG32(ADR_REASON_TRAP0)) & 0xffffffff ) >> 0)
+#define GET_REASON_TRAP1 (((REG32(ADR_REASON_TRAP1)) & 0xffffffff ) >> 0)
+#define GET_BSSID_31_0 (((REG32(ADR_BSSID_0)) & 0xffffffff ) >> 0)
+#define GET_BSSID_47_32 (((REG32(ADR_BSSID_1)) & 0x0000ffff ) >> 0)
+#define GET_SCRT_STATE (((REG32(ADR_SCRT_STATE)) & 0x0000000f ) >> 0)
+#define GET_STA_MAC_31_0 (((REG32(ADR_STA_MAC_0)) & 0xffffffff ) >> 0)
+#define GET_STA_MAC_47_32 (((REG32(ADR_STA_MAC_1)) & 0x0000ffff ) >> 0)
+#define GET_PAIR_SCRT (((REG32(ADR_SCRT_SET)) & 0x00000007 ) >> 0)
+#define GET_GRP_SCRT (((REG32(ADR_SCRT_SET)) & 0x00000038 ) >> 3)
+#define GET_SCRT_PKT_ID (((REG32(ADR_SCRT_SET)) & 0x00001fc0 ) >> 6)
+#define GET_SCRT_RPLY_IGNORE (((REG32(ADR_SCRT_SET)) & 0x00010000 ) >> 16)
+#define GET_COEXIST_EN (((REG32(ADR_BTCX0)) & 0x00000001 ) >> 0)
+#define GET_WIRE_MODE (((REG32(ADR_BTCX0)) & 0x0000000e ) >> 1)
+#define GET_WL_RX_PRI (((REG32(ADR_BTCX0)) & 0x00000010 ) >> 4)
+#define GET_WL_TX_PRI (((REG32(ADR_BTCX0)) & 0x00000020 ) >> 5)
+#define GET_GURAN_USE_EN (((REG32(ADR_BTCX0)) & 0x00000100 ) >> 8)
+#define GET_GURAN_USE_CTRL (((REG32(ADR_BTCX0)) & 0x00000200 ) >> 9)
+#define GET_BEACON_TIMEOUT_EN (((REG32(ADR_BTCX0)) & 0x00000400 ) >> 10)
+#define GET_WLAN_ACT_POL (((REG32(ADR_BTCX0)) & 0x00000800 ) >> 11)
+#define GET_DUAL_ANT_EN (((REG32(ADR_BTCX0)) & 0x00001000 ) >> 12)
+#define GET_TRSW_PHY_POL (((REG32(ADR_BTCX0)) & 0x00010000 ) >> 16)
+#define GET_WIFI_TX_SW_POL (((REG32(ADR_BTCX0)) & 0x00020000 ) >> 17)
+#define GET_WIFI_RX_SW_POL (((REG32(ADR_BTCX0)) & 0x00040000 ) >> 18)
+#define GET_BT_SW_POL (((REG32(ADR_BTCX0)) & 0x00080000 ) >> 19)
+#define GET_BT_PRI_SMP_TIME (((REG32(ADR_BTCX1)) & 0x000000ff ) >> 0)
+#define GET_BT_STA_SMP_TIME (((REG32(ADR_BTCX1)) & 0x0000ff00 ) >> 8)
+#define GET_BEACON_TIMEOUT (((REG32(ADR_BTCX1)) & 0x00ff0000 ) >> 16)
+#define GET_WLAN_REMAIN_TIME (((REG32(ADR_BTCX1)) & 0xff000000 ) >> 24)
+#define GET_SW_MANUAL_EN (((REG32(ADR_SWITCH_CTL)) & 0x00000001 ) >> 0)
+#define GET_SW_WL_TX (((REG32(ADR_SWITCH_CTL)) & 0x00000002 ) >> 1)
+#define GET_SW_WL_RX (((REG32(ADR_SWITCH_CTL)) & 0x00000004 ) >> 2)
+#define GET_SW_BT_TRX (((REG32(ADR_SWITCH_CTL)) & 0x00000008 ) >> 3)
+#define GET_BT_TXBAR_MANUAL_EN (((REG32(ADR_SWITCH_CTL)) & 0x00000010 ) >> 4)
+#define GET_BT_TXBAR_SET (((REG32(ADR_SWITCH_CTL)) & 0x00000020 ) >> 5)
+#define GET_BT_BUSY_MANUAL_EN (((REG32(ADR_SWITCH_CTL)) & 0x00000100 ) >> 8)
+#define GET_BT_BUSY_SET (((REG32(ADR_SWITCH_CTL)) & 0x00000200 ) >> 9)
+#define GET_G0_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000004 ) >> 2)
+#define GET_G0_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000008 ) >> 3)
+#define GET_G1_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000010 ) >> 4)
+#define GET_G1_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000020 ) >> 5)
+#define GET_Q0_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000040 ) >> 6)
+#define GET_Q0_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000080 ) >> 7)
+#define GET_Q1_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000100 ) >> 8)
+#define GET_Q1_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000200 ) >> 9)
+#define GET_Q2_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000400 ) >> 10)
+#define GET_Q2_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000800 ) >> 11)
+#define GET_Q3_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00001000 ) >> 12)
+#define GET_Q3_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00002000 ) >> 13)
+#define GET_SCRT_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00004000 ) >> 14)
+#define GET_SCRT_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00008000 ) >> 15)
+#define GET_MISC_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00010000 ) >> 16)
+#define GET_MISC_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00020000 ) >> 17)
+#define GET_MTX_WSID0_SUCC (((REG32(ADR_MTX_WSID0_SUCC)) & 0x0000ffff ) >> 0)
+#define GET_MTX_WSID0_FRM (((REG32(ADR_MTX_WSID0_FRM)) & 0x0000ffff ) >> 0)
+#define GET_MTX_WSID0_RETRY (((REG32(ADR_MTX_WSID0_RETRY)) & 0x0000ffff ) >> 0)
+#define GET_MTX_WSID0_TOTAL (((REG32(ADR_MTX_WSID0_TOTAL)) & 0x0000ffff ) >> 0)
+#define GET_MTX_GRP (((REG32(ADR_MTX_GROUP)) & 0x000fffff ) >> 0)
+#define GET_MTX_FAIL (((REG32(ADR_MTX_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RETRY (((REG32(ADR_MTX_RETRY)) & 0x000fffff ) >> 0)
+#define GET_MTX_MULTI_RETRY (((REG32(ADR_MTX_MULTI_RETRY)) & 0x000fffff ) >> 0)
+#define GET_MTX_RTS_SUCC (((REG32(ADR_MTX_RTS_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RTS_FAIL (((REG32(ADR_MTX_RTS_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_MTX_ACK_FAIL (((REG32(ADR_MTX_ACK_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_MTX_FRM (((REG32(ADR_MTX_FRM)) & 0x000fffff ) >> 0)
+#define GET_MTX_ACK_TX (((REG32(ADR_MTX_ACK_TX)) & 0x0000ffff ) >> 0)
+#define GET_MTX_CTS_TX (((REG32(ADR_MTX_CTS_TX)) & 0x0000ffff ) >> 0)
+#define GET_MRX_DUP (((REG32(ADR_MRX_DUP_FRM)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FRG (((REG32(ADR_MRX_FRG_FRM)) & 0x000fffff ) >> 0)
+#define GET_MRX_GRP (((REG32(ADR_MRX_GROUP_FRM)) & 0x000fffff ) >> 0)
+#define GET_MRX_FCS_ERR (((REG32(ADR_MRX_FCS_ERR)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FCS_SUC (((REG32(ADR_MRX_FCS_SUCC)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MISS (((REG32(ADR_MRX_MISS)) & 0x0000ffff ) >> 0)
+#define GET_MRX_ALC_FAIL (((REG32(ADR_MRX_ALC_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_MRX_DAT_NTF (((REG32(ADR_MRX_DAT_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_RTS_NTF (((REG32(ADR_MRX_RTS_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_CTS_NTF (((REG32(ADR_MRX_CTS_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_ACK_NTF (((REG32(ADR_MRX_ACK_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_BA_NTF (((REG32(ADR_MRX_BA_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_DATA_NTF (((REG32(ADR_MRX_DATA_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MNG_NTF (((REG32(ADR_MRX_MNG_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_DAT_CRC_NTF (((REG32(ADR_MRX_DAT_CRC_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_BAR_NTF (((REG32(ADR_MRX_BAR_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MB_MISS (((REG32(ADR_MRX_MB_MISS)) & 0x0000ffff ) >> 0)
+#define GET_MRX_NIDLE_MISS (((REG32(ADR_MRX_NIDLE_MISS)) & 0x0000ffff ) >> 0)
+#define GET_MRX_CSR_NTF (((REG32(ADR_MRX_CSR_NTF)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q0_SUCC (((REG32(ADR_DBG_Q0_FRM_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q0_FAIL (((REG32(ADR_DBG_Q0_FRM_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q0_ACK_SUCC (((REG32(ADR_DBG_Q0_ACK_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q0_ACK_FAIL (((REG32(ADR_DBG_Q0_ACK_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q1_SUCC (((REG32(ADR_DBG_Q1_FRM_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q1_FAIL (((REG32(ADR_DBG_Q1_FRM_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q1_ACK_SUCC (((REG32(ADR_DBG_Q1_ACK_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q1_ACK_FAIL (((REG32(ADR_DBG_Q1_ACK_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q2_SUCC (((REG32(ADR_DBG_Q2_FRM_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q2_FAIL (((REG32(ADR_DBG_Q2_FRM_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q2_ACK_SUCC (((REG32(ADR_DBG_Q2_ACK_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q2_ACK_FAIL (((REG32(ADR_DBG_Q2_ACK_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q3_SUCC (((REG32(ADR_DBG_Q3_FRM_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q3_FAIL (((REG32(ADR_DBG_Q3_FRM_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q3_ACK_SUCC (((REG32(ADR_DBG_Q3_ACK_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q3_ACK_FAIL (((REG32(ADR_DBG_Q3_ACK_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_SCRT_TKIP_CERR (((REG32(ADR_MIB_SCRT_TKIP0)) & 0x000fffff ) >> 0)
+#define GET_SCRT_TKIP_MIC_ERR (((REG32(ADR_MIB_SCRT_TKIP1)) & 0x000fffff ) >> 0)
+#define GET_SCRT_TKIP_RPLY (((REG32(ADR_MIB_SCRT_TKIP2)) & 0x000fffff ) >> 0)
+#define GET_SCRT_CCMP_RPLY (((REG32(ADR_MIB_SCRT_CCMP0)) & 0x000fffff ) >> 0)
+#define GET_SCRT_CCMP_CERR (((REG32(ADR_MIB_SCRT_CCMP1)) & 0x000fffff ) >> 0)
+#define GET_DBG_LEN_CRC_FAIL (((REG32(ADR_DBG_LEN_CRC_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_LEN_ALC_FAIL (((REG32(ADR_DBG_LEN_ALC_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_AMPDU_PASS (((REG32(ADR_DBG_AMPDU_PASS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_AMPDU_FAIL (((REG32(ADR_DBG_AMPDU_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_RXID_ALC_CNT_FAIL (((REG32(ADR_ID_ALC_FAIL1)) & 0x0000ffff ) >> 0)
+#define GET_RXID_ALC_LEN_FAIL (((REG32(ADR_ID_ALC_FAIL2)) & 0x0000ffff ) >> 0)
+#define GET_CBR_RG_EN_MANUAL (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_TX_EN (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_CBR_RG_TX_PA_EN (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_CBR_RG_TX_DAC_EN (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_CBR_RG_RX_AGC (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_CBR_RG_RX_GAIN_MANUAL (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000020 ) >> 5)
+#define GET_CBR_RG_RFG (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x000000c0 ) >> 6)
+#define GET_CBR_RG_PGAG (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000f00 ) >> 8)
+#define GET_CBR_RG_MODE (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00003000 ) >> 12)
+#define GET_CBR_RG_EN_TX_TRSW (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_CBR_RG_EN_SX (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00008000 ) >> 15)
+#define GET_CBR_RG_EN_RX_LNA (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00010000 ) >> 16)
+#define GET_CBR_RG_EN_RX_MIXER (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00020000 ) >> 17)
+#define GET_CBR_RG_EN_RX_DIV2 (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00040000 ) >> 18)
+#define GET_CBR_RG_EN_RX_LOBUF (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00080000 ) >> 19)
+#define GET_CBR_RG_EN_RX_TZ (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00100000 ) >> 20)
+#define GET_CBR_RG_EN_RX_FILTER (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00200000 ) >> 21)
+#define GET_CBR_RG_EN_RX_HPF (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00400000 ) >> 22)
+#define GET_CBR_RG_EN_RX_RSSI (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00800000 ) >> 23)
+#define GET_CBR_RG_EN_ADC (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x01000000 ) >> 24)
+#define GET_CBR_RG_EN_TX_MOD (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x02000000 ) >> 25)
+#define GET_CBR_RG_EN_TX_DIV2 (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x04000000 ) >> 26)
+#define GET_CBR_RG_EN_TX_DIV2_BUF (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x08000000 ) >> 27)
+#define GET_CBR_RG_EN_TX_LOBF (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x10000000 ) >> 28)
+#define GET_CBR_RG_EN_RX_LOBF (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x20000000 ) >> 29)
+#define GET_CBR_RG_SEL_DPLL_CLK (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x40000000 ) >> 30)
+#define GET_CBR_RG_EN_TX_DPD (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_EN_TX_TSSI (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_CBR_RG_EN_RX_IQCAL (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_CBR_RG_EN_TX_DAC_CAL (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_CBR_RG_EN_TX_SELF_MIXER (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_CBR_RG_EN_TX_DAC_OUT (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000020 ) >> 5)
+#define GET_CBR_RG_EN_LDO_RX_FE (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000040 ) >> 6)
+#define GET_CBR_RG_EN_LDO_ABB (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000080 ) >> 7)
+#define GET_CBR_RG_EN_LDO_AFE (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000100 ) >> 8)
+#define GET_CBR_RG_EN_SX_CHPLDO (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000200 ) >> 9)
+#define GET_CBR_RG_EN_SX_LOBFLDO (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000400 ) >> 10)
+#define GET_CBR_RG_EN_IREF_RX (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_CBR_RG_DCDC_MODE (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00001000 ) >> 12)
+#define GET_CBR_RG_LDO_LEVEL_RX_FE (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00000007 ) >> 0)
+#define GET_CBR_RG_LDO_LEVEL_ABB (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00000038 ) >> 3)
+#define GET_CBR_RG_LDO_LEVEL_AFE (((REG32(ADR_CBR_LDO_REGISTER)) & 0x000001c0 ) >> 6)
+#define GET_CBR_RG_SX_LDO_CHP_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00000e00 ) >> 9)
+#define GET_CBR_RG_SX_LDO_LOBF_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00007000 ) >> 12)
+#define GET_CBR_RG_SX_LDO_XOSC_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00038000 ) >> 15)
+#define GET_CBR_RG_DP_LDO_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x001c0000 ) >> 18)
+#define GET_CBR_RG_SX_LDO_VCO_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00e00000 ) >> 21)
+#define GET_CBR_RG_TX_LDO_TX_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x07000000 ) >> 24)
+#define GET_CBR_RG_BUCK_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x38000000 ) >> 27)
+#define GET_CBR_RG_EN_RX_PADSW (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_EN_RX_TESTNODE (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000002 ) >> 1)
+#define GET_CBR_RG_RX_ABBCFIX (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000004 ) >> 2)
+#define GET_CBR_RG_RX_ABBCTUNE (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x000001f8 ) >> 3)
+#define GET_CBR_RG_RX_ABBOUT_TRI_STATE (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000200 ) >> 9)
+#define GET_CBR_RG_RX_ABB_N_MODE (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000400 ) >> 10)
+#define GET_CBR_RG_RX_EN_LOOPA (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000800 ) >> 11)
+#define GET_CBR_RG_RX_FILTERI1ST (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00003000 ) >> 12)
+#define GET_CBR_RG_RX_FILTERI2ND (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x0000c000 ) >> 14)
+#define GET_CBR_RG_RX_FILTERI3RD (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00030000 ) >> 16)
+#define GET_CBR_RG_RX_FILTERI_COURSE (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x000c0000 ) >> 18)
+#define GET_CBR_RG_RX_FILTERVCM (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00300000 ) >> 20)
+#define GET_CBR_RG_RX_HPF3M (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00400000 ) >> 22)
+#define GET_CBR_RG_RX_HPF300K (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00800000 ) >> 23)
+#define GET_CBR_RG_RX_HPFI (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x03000000 ) >> 24)
+#define GET_CBR_RG_RX_HPF_FINALCORNER (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x0c000000 ) >> 26)
+#define GET_CBR_RG_RX_HPF_SETTLE1_C (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x30000000 ) >> 28)
+#define GET_CBR_RG_RX_HPF_SETTLE1_R (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00000003 ) >> 0)
+#define GET_CBR_RG_RX_HPF_SETTLE2_C (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x0000000c ) >> 2)
+#define GET_CBR_RG_RX_HPF_SETTLE2_R (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00000030 ) >> 4)
+#define GET_CBR_RG_RX_HPF_VCMCON2 (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x000000c0 ) >> 6)
+#define GET_CBR_RG_RX_HPF_VCMCON (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00000300 ) >> 8)
+#define GET_CBR_RG_RX_OUTVCM (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00000c00 ) >> 10)
+#define GET_CBR_RG_RX_TZI (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00003000 ) >> 12)
+#define GET_CBR_RG_RX_TZ_OUT_TRISTATE (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00004000 ) >> 14)
+#define GET_CBR_RG_RX_TZ_VCM (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00018000 ) >> 15)
+#define GET_CBR_RG_EN_RX_RSSI_TESTNODE (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x000e0000 ) >> 17)
+#define GET_CBR_RG_RX_ADCRSSI_CLKSEL (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00100000 ) >> 20)
+#define GET_CBR_RG_RX_ADCRSSI_VCM (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00600000 ) >> 21)
+#define GET_CBR_RG_RX_REC_LPFCORNER (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x01800000 ) >> 23)
+#define GET_CBR_RG_RSSI_CLOCK_GATING (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x02000000 ) >> 25)
+#define GET_CBR_RG_TXPGA_CAPSW (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_CBR_RG_TXPGA_MAIN (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x000000fc ) >> 2)
+#define GET_CBR_RG_TXPGA_STEER (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x00003f00 ) >> 8)
+#define GET_CBR_RG_TXMOD_GMCELL (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x0000c000 ) >> 14)
+#define GET_CBR_RG_TXLPF_GMCELL (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x00030000 ) >> 16)
+#define GET_CBR_RG_PACELL_EN (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x001c0000 ) >> 18)
+#define GET_CBR_RG_PABIAS_CTRL (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x01e00000 ) >> 21)
+#define GET_CBR_RG_PABIAS_AB (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x02000000 ) >> 25)
+#define GET_CBR_RG_TX_DIV_VSET (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x0c000000 ) >> 26)
+#define GET_CBR_RG_TX_LOBUF_VSET (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x30000000 ) >> 28)
+#define GET_CBR_RG_RX_SQDC (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00000007 ) >> 0)
+#define GET_CBR_RG_RX_DIV2_CORE (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00000018 ) >> 3)
+#define GET_CBR_RG_RX_LOBUF (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00000060 ) >> 5)
+#define GET_CBR_RG_TX_DPDGM_BIAS (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00000780 ) >> 7)
+#define GET_CBR_RG_TX_DPD_DIV (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00007800 ) >> 11)
+#define GET_CBR_RG_TX_TSSI_BIAS (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00038000 ) >> 15)
+#define GET_CBR_RG_TX_TSSI_DIV (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x001c0000 ) >> 18)
+#define GET_CBR_RG_TX_TSSI_TESTMODE (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00200000 ) >> 21)
+#define GET_CBR_RG_TX_TSSI_TEST (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00c00000 ) >> 22)
+#define GET_CBR_RG_RX_HG_LNA_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00000003 ) >> 0)
+#define GET_CBR_RG_RX_HG_LNAHGN_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x0000003c ) >> 2)
+#define GET_CBR_RG_RX_HG_LNAHGP_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x000003c0 ) >> 6)
+#define GET_CBR_RG_RX_HG_LNALG_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00003c00 ) >> 10)
+#define GET_CBR_RG_RX_HG_TZ_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x0000c000 ) >> 14)
+#define GET_CBR_RG_RX_HG_TZ_CAP (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00070000 ) >> 16)
+#define GET_CBR_RG_RX_MG_LNA_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00000003 ) >> 0)
+#define GET_CBR_RG_RX_MG_LNAHGN_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x0000003c ) >> 2)
+#define GET_CBR_RG_RX_MG_LNAHGP_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x000003c0 ) >> 6)
+#define GET_CBR_RG_RX_MG_LNALG_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00003c00 ) >> 10)
+#define GET_CBR_RG_RX_MG_TZ_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x0000c000 ) >> 14)
+#define GET_CBR_RG_RX_MG_TZ_CAP (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00070000 ) >> 16)
+#define GET_CBR_RG_RX_LG_LNA_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00000003 ) >> 0)
+#define GET_CBR_RG_RX_LG_LNAHGN_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x0000003c ) >> 2)
+#define GET_CBR_RG_RX_LG_LNAHGP_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x000003c0 ) >> 6)
+#define GET_CBR_RG_RX_LG_LNALG_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00003c00 ) >> 10)
+#define GET_CBR_RG_RX_LG_TZ_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x0000c000 ) >> 14)
+#define GET_CBR_RG_RX_LG_TZ_CAP (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00070000 ) >> 16)
+#define GET_CBR_RG_RX_ULG_LNA_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00000003 ) >> 0)
+#define GET_CBR_RG_RX_ULG_LNAHGN_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x0000003c ) >> 2)
+#define GET_CBR_RG_RX_ULG_LNAHGP_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x000003c0 ) >> 6)
+#define GET_CBR_RG_RX_ULG_LNALG_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00003c00 ) >> 10)
+#define GET_CBR_RG_RX_ULG_TZ_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x0000c000 ) >> 14)
+#define GET_CBR_RG_RX_ULG_TZ_CAP (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00070000 ) >> 16)
+#define GET_CBR_RG_HPF1_FAST_SET_X (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_HPF1_FAST_SET_Y (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_CBR_RG_HPF1_FAST_SET_Z (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_CBR_RG_HPF_T1A (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000018 ) >> 3)
+#define GET_CBR_RG_HPF_T1B (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000060 ) >> 5)
+#define GET_CBR_RG_HPF_T1C (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000180 ) >> 7)
+#define GET_CBR_RG_RX_LNA_TRI_SEL (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000600 ) >> 9)
+#define GET_CBR_RG_RX_LNA_SETTLE (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00001800 ) >> 11)
+#define GET_CBR_RG_ADC_CLKSEL (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_ADC_DIBIAS (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000006 ) >> 1)
+#define GET_CBR_RG_ADC_DIVR (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_CBR_RG_ADC_DVCMI (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000030 ) >> 4)
+#define GET_CBR_RG_ADC_SAMSEL (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x000003c0 ) >> 6)
+#define GET_CBR_RG_ADC_STNBY (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000400 ) >> 10)
+#define GET_CBR_RG_ADC_TESTMODE (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_CBR_RG_ADC_TSEL (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x0000f000 ) >> 12)
+#define GET_CBR_RG_ADC_VRSEL (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00030000 ) >> 16)
+#define GET_CBR_RG_DICMP (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x000c0000 ) >> 18)
+#define GET_CBR_RG_DIOP (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00300000 ) >> 20)
+#define GET_CBR_RG_DACI1ST (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_CBR_RG_TX_DACLPF_ICOURSE (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_CBR_RG_TX_DACLPF_IFINE (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00000030 ) >> 4)
+#define GET_CBR_RG_TX_DACLPF_VCM (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x000000c0 ) >> 6)
+#define GET_CBR_RG_TX_DAC_CKEDGE_SEL (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00000100 ) >> 8)
+#define GET_CBR_RG_TX_DAC_IBIAS (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00000600 ) >> 9)
+#define GET_CBR_RG_TX_DAC_OS (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00003800 ) >> 11)
+#define GET_CBR_RG_TX_DAC_RCAL (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x0000c000 ) >> 14)
+#define GET_CBR_RG_TX_DAC_TSEL (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x000f0000 ) >> 16)
+#define GET_CBR_RG_TX_EN_VOLTAGE_IN (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00100000 ) >> 20)
+#define GET_CBR_RG_TXLPF_BYPASS (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00200000 ) >> 21)
+#define GET_CBR_RG_TXLPF_BOOSTI (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00400000 ) >> 22)
+#define GET_CBR_RG_EN_SX_R3 (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_EN_SX_CH (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000002 ) >> 1)
+#define GET_CBR_RG_EN_SX_CHP (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000004 ) >> 2)
+#define GET_CBR_RG_EN_SX_DIVCK (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000008 ) >> 3)
+#define GET_CBR_RG_EN_SX_VCOBF (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000010 ) >> 4)
+#define GET_CBR_RG_EN_SX_VCO (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000020 ) >> 5)
+#define GET_CBR_RG_EN_SX_MOD (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000040 ) >> 6)
+#define GET_CBR_RG_EN_SX_LCK (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000080 ) >> 7)
+#define GET_CBR_RG_EN_SX_DITHER (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000100 ) >> 8)
+#define GET_CBR_RG_EN_SX_DELCAL (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000200 ) >> 9)
+#define GET_CBR_RG_EN_SX_PC_BYPASS (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000400 ) >> 10)
+#define GET_CBR_RG_EN_SX_VT_MON (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000800 ) >> 11)
+#define GET_CBR_RG_EN_SX_VT_MON_DG (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00001000 ) >> 12)
+#define GET_CBR_RG_EN_SX_DIV (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00002000 ) >> 13)
+#define GET_CBR_RG_EN_SX_LPF (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00004000 ) >> 14)
+#define GET_CBR_RG_SX_RFCTRL_F (((REG32(ADR_CBR_SYN_RGISTER_1)) & 0x00ffffff ) >> 0)
+#define GET_CBR_RG_SX_SEL_CP (((REG32(ADR_CBR_SYN_RGISTER_1)) & 0x0f000000 ) >> 24)
+#define GET_CBR_RG_SX_SEL_CS (((REG32(ADR_CBR_SYN_RGISTER_1)) & 0xf0000000 ) >> 28)
+#define GET_CBR_RG_SX_RFCTRL_CH (((REG32(ADR_CBR_SYN_RGISTER_2)) & 0x000007ff ) >> 0)
+#define GET_CBR_RG_SX_SEL_C3 (((REG32(ADR_CBR_SYN_RGISTER_2)) & 0x00007800 ) >> 11)
+#define GET_CBR_RG_SX_SEL_RS (((REG32(ADR_CBR_SYN_RGISTER_2)) & 0x000f8000 ) >> 15)
+#define GET_CBR_RG_SX_SEL_R3 (((REG32(ADR_CBR_SYN_RGISTER_2)) & 0x01f00000 ) >> 20)
+#define GET_CBR_RG_SX_SEL_ICHP (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x0000001f ) >> 0)
+#define GET_CBR_RG_SX_SEL_PCHP (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x000003e0 ) >> 5)
+#define GET_CBR_RG_SX_SEL_CHP_REGOP (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x00003c00 ) >> 10)
+#define GET_CBR_RG_SX_SEL_CHP_UNIOP (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x0003c000 ) >> 14)
+#define GET_CBR_RG_SX_CHP_IOST_POL (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x00040000 ) >> 18)
+#define GET_CBR_RG_SX_CHP_IOST (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x00380000 ) >> 19)
+#define GET_CBR_RG_SX_PFDSEL (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x00400000 ) >> 22)
+#define GET_CBR_RG_SX_PFD_SET (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x00800000 ) >> 23)
+#define GET_CBR_RG_SX_PFD_SET1 (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x01000000 ) >> 24)
+#define GET_CBR_RG_SX_PFD_SET2 (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x02000000 ) >> 25)
+#define GET_CBR_RG_SX_VBNCAS_SEL (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x04000000 ) >> 26)
+#define GET_CBR_RG_SX_PFD_RST_H (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x08000000 ) >> 27)
+#define GET_CBR_RG_SX_PFD_TRUP (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x10000000 ) >> 28)
+#define GET_CBR_RG_SX_PFD_TRDN (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x20000000 ) >> 29)
+#define GET_CBR_RG_SX_PFD_TRSEL (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x40000000 ) >> 30)
+#define GET_CBR_RG_SX_VCOBA_R (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x00000007 ) >> 0)
+#define GET_CBR_RG_SX_VCORSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x000000f8 ) >> 3)
+#define GET_CBR_RG_SX_VCOCUSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x00000f00 ) >> 8)
+#define GET_CBR_RG_SX_RXBFSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x0000f000 ) >> 12)
+#define GET_CBR_RG_SX_TXBFSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x000f0000 ) >> 16)
+#define GET_CBR_RG_SX_VCOBFSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x00f00000 ) >> 20)
+#define GET_CBR_RG_SX_DIVBFSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x0f000000 ) >> 24)
+#define GET_CBR_RG_SX_GNDR_SEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xf0000000 ) >> 28)
+#define GET_CBR_RG_SX_DITHER_WEIGHT (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000003 ) >> 0)
+#define GET_CBR_RG_SX_MOD_ERRCMP (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x0000000c ) >> 2)
+#define GET_CBR_RG_SX_MOD_ORDER (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000030 ) >> 4)
+#define GET_CBR_RG_SX_SDM_D1 (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000040 ) >> 6)
+#define GET_CBR_RG_SX_SDM_D2 (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000080 ) >> 7)
+#define GET_CBR_RG_SDM_PASS (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000100 ) >> 8)
+#define GET_CBR_RG_SX_RST_H_DIV (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000200 ) >> 9)
+#define GET_CBR_RG_SX_SDM_EDGE (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000400 ) >> 10)
+#define GET_CBR_RG_SX_XO_GM (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00001800 ) >> 11)
+#define GET_CBR_RG_SX_REFBYTWO (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00002000 ) >> 13)
+#define GET_CBR_RG_SX_XO_SWCAP (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x0003c000 ) >> 14)
+#define GET_CBR_RG_SX_SDMLUT_INV (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00040000 ) >> 18)
+#define GET_CBR_RG_SX_LCKEN (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00080000 ) >> 19)
+#define GET_CBR_RG_SX_PREVDD (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00f00000 ) >> 20)
+#define GET_CBR_RG_SX_PSCONTERVDD (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x0f000000 ) >> 24)
+#define GET_CBR_RG_SX_MOD_ERR_DELAY (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x30000000 ) >> 28)
+#define GET_CBR_RG_SX_MODDB (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x40000000 ) >> 30)
+#define GET_CBR_RG_SX_CV_CURVE_SEL (((REG32(ADR_CBR_SYN_LCK1)) & 0x00000003 ) >> 0)
+#define GET_CBR_RG_SX_SEL_DELAY (((REG32(ADR_CBR_SYN_LCK1)) & 0x0000007c ) >> 2)
+#define GET_CBR_RG_SX_REF_CYCLE (((REG32(ADR_CBR_SYN_LCK1)) & 0x00000780 ) >> 7)
+#define GET_CBR_RG_SX_VCOBY16 (((REG32(ADR_CBR_SYN_LCK1)) & 0x00000800 ) >> 11)
+#define GET_CBR_RG_SX_VCOBY32 (((REG32(ADR_CBR_SYN_LCK1)) & 0x00001000 ) >> 12)
+#define GET_CBR_RG_SX_PH (((REG32(ADR_CBR_SYN_LCK1)) & 0x00002000 ) >> 13)
+#define GET_CBR_RG_SX_PL (((REG32(ADR_CBR_SYN_LCK1)) & 0x00004000 ) >> 14)
+#define GET_CBR_RG_SX_VT_MON_MODE (((REG32(ADR_CBR_SYN_LCK2)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_SX_VT_TH_HI (((REG32(ADR_CBR_SYN_LCK2)) & 0x00000006 ) >> 1)
+#define GET_CBR_RG_SX_VT_TH_LO (((REG32(ADR_CBR_SYN_LCK2)) & 0x00000018 ) >> 3)
+#define GET_CBR_RG_SX_VT_SET (((REG32(ADR_CBR_SYN_LCK2)) & 0x00000020 ) >> 5)
+#define GET_CBR_RG_SX_VT_MON_TMR (((REG32(ADR_CBR_SYN_LCK2)) & 0x00007fc0 ) >> 6)
+#define GET_CBR_RG_IDEAL_CYCLE (((REG32(ADR_CBR_SYN_LCK2)) & 0x0fff8000 ) >> 15)
+#define GET_CBR_RG_EN_DP_VT_MON (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_DP_VT_TH_HI (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00000006 ) >> 1)
+#define GET_CBR_RG_DP_VT_TH_LO (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00000018 ) >> 3)
+#define GET_CBR_RG_DP_VT_MON_TMR (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00003fe0 ) >> 5)
+#define GET_CBR_RG_DP_CK320BY2 (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_CBR_RG_SX_DELCTRL (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x001f8000 ) >> 15)
+#define GET_CBR_RG_DP_OD_TEST (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00200000 ) >> 21)
+#define GET_CBR_RG_DP_BBPLL_BP (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_DP_BBPLL_ICP (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00000006 ) >> 1)
+#define GET_CBR_RG_DP_BBPLL_IDUAL (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00000018 ) >> 3)
+#define GET_CBR_RG_DP_BBPLL_OD_TEST (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x000001e0 ) >> 5)
+#define GET_CBR_RG_DP_BBPLL_PD (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00000200 ) >> 9)
+#define GET_CBR_RG_DP_BBPLL_TESTSEL (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00001c00 ) >> 10)
+#define GET_CBR_RG_DP_BBPLL_PFD_DLY (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00006000 ) >> 13)
+#define GET_CBR_RG_DP_RP (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00038000 ) >> 15)
+#define GET_CBR_RG_DP_RHP (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x000c0000 ) >> 18)
+#define GET_CBR_RG_DP_DR3 (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00700000 ) >> 20)
+#define GET_CBR_RG_DP_DCP (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x07800000 ) >> 23)
+#define GET_CBR_RG_DP_DCS (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x78000000 ) >> 27)
+#define GET_CBR_RG_DP_FBDIV (((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0x00000fff ) >> 0)
+#define GET_CBR_RG_DP_FODIV (((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0x003ff000 ) >> 12)
+#define GET_CBR_RG_DP_REFDIV (((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0xffc00000 ) >> 22)
+#define GET_CBR_RG_IDACAI_PGAG15 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0x0000003f ) >> 0)
+#define GET_CBR_RG_IDACAQ_PGAG15 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0x00000fc0 ) >> 6)
+#define GET_CBR_RG_IDACAI_PGAG14 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0x0003f000 ) >> 12)
+#define GET_CBR_RG_IDACAQ_PGAG14 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0x00fc0000 ) >> 18)
+#define GET_CBR_RG_IDACAI_PGAG13 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0x0000003f ) >> 0)
+#define GET_CBR_RG_IDACAQ_PGAG13 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0x00000fc0 ) >> 6)
+#define GET_CBR_RG_IDACAI_PGAG12 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0x0003f000 ) >> 12)
+#define GET_CBR_RG_IDACAQ_PGAG12 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0x00fc0000 ) >> 18)
+#define GET_CBR_RG_IDACAI_PGAG11 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0x0000003f ) >> 0)
+#define GET_CBR_RG_IDACAQ_PGAG11 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0x00000fc0 ) >> 6)
+#define GET_CBR_RG_IDACAI_PGAG10 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0x0003f000 ) >> 12)
+#define GET_CBR_RG_IDACAQ_PGAG10 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0x00fc0000 ) >> 18)
+#define GET_CBR_RG_IDACAI_PGAG9 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0x0000003f ) >> 0)
+#define GET_CBR_RG_IDACAQ_PGAG9 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0x00000fc0 ) >> 6)
+#define GET_CBR_RG_IDACAI_PGAG8 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0x0003f000 ) >> 12)
+#define GET_CBR_RG_IDACAQ_PGAG8 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0x00fc0000 ) >> 18)
+#define GET_CBR_RG_IDACAI_PGAG7 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0x0000003f ) >> 0)
+#define GET_CBR_RG_IDACAQ_PGAG7 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0x00000fc0 ) >> 6)
+#define GET_CBR_RG_IDACAI_PGAG6 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0x0003f000 ) >> 12)
+#define GET_CBR_RG_IDACAQ_PGAG6 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0x00fc0000 ) >> 18)
+#define GET_CBR_RG_IDACAI_PGAG5 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0x0000003f ) >> 0)
+#define GET_CBR_RG_IDACAQ_PGAG5 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0x00000fc0 ) >> 6)
+#define GET_CBR_RG_IDACAI_PGAG4 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0x0003f000 ) >> 12)
+#define GET_CBR_RG_IDACAQ_PGAG4 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0x00fc0000 ) >> 18)
+#define GET_CBR_RG_IDACAI_PGAG3 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0x0000003f ) >> 0)
+#define GET_CBR_RG_IDACAQ_PGAG3 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0x00000fc0 ) >> 6)
+#define GET_CBR_RG_IDACAI_PGAG2 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0x0003f000 ) >> 12)
+#define GET_CBR_RG_IDACAQ_PGAG2 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0x00fc0000 ) >> 18)
+#define GET_CBR_RG_IDACAI_PGAG1 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0x0000003f ) >> 0)
+#define GET_CBR_RG_IDACAQ_PGAG1 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0x00000fc0 ) >> 6)
+#define GET_CBR_RG_IDACAI_PGAG0 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0x0003f000 ) >> 12)
+#define GET_CBR_RG_IDACAQ_PGAG0 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0x00fc0000 ) >> 18)
+#define GET_CBR_RG_EN_RCAL (((REG32(ADR_CBR_RCAL_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_RCAL_SPD (((REG32(ADR_CBR_RCAL_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_CBR_RG_RCAL_TMR (((REG32(ADR_CBR_RCAL_REGISTER)) & 0x000001fc ) >> 2)
+#define GET_CBR_RG_RCAL_CODE_CWR (((REG32(ADR_CBR_RCAL_REGISTER)) & 0x00000200 ) >> 9)
+#define GET_CBR_RG_RCAL_CODE_CWD (((REG32(ADR_CBR_RCAL_REGISTER)) & 0x00007c00 ) >> 10)
+#define GET_CBR_RG_SX_SUB_SEL_CWR (((REG32(ADR_CBR_MANUAL_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_SX_SUB_SEL_CWD (((REG32(ADR_CBR_MANUAL_REGISTER)) & 0x000000fe ) >> 1)
+#define GET_CBR_RG_DP_BBPLL_BS_CWR (((REG32(ADR_CBR_MANUAL_REGISTER)) & 0x00000100 ) >> 8)
+#define GET_CBR_RG_DP_BBPLL_BS_CWD (((REG32(ADR_CBR_MANUAL_REGISTER)) & 0x00007e00 ) >> 9)
+#define GET_CBR_RCAL_RDY (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00000001 ) >> 0)
+#define GET_CBR_DA_LCK_RDY (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00000002 ) >> 1)
+#define GET_CBR_VT_MON_RDY (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00000004 ) >> 2)
+#define GET_CBR_DP_VT_MON_RDY (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00000008 ) >> 3)
+#define GET_CBR_CH_RDY (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00000010 ) >> 4)
+#define GET_CBR_DA_R_CODE_LUT (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x000007c0 ) >> 6)
+#define GET_CBR_AD_SX_VT_MON_Q (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00001800 ) >> 11)
+#define GET_CBR_AD_DP_VT_MON_Q (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00006000 ) >> 13)
+#define GET_CBR_DA_R_CAL_CODE (((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0x0000001f ) >> 0)
+#define GET_CBR_DA_SX_SUB_SEL (((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0x00000fe0 ) >> 5)
+#define GET_CBR_DA_DP_BBPLL_BS (((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0x0003f000 ) >> 12)
+#define GET_CBR_TX_EN (((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0x00000001 ) >> 0)
+#define GET_CBR_TX_CNT_RST (((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0x00000002 ) >> 1)
+#define GET_CBR_IFS_TIME (((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0x000000fc ) >> 2)
+#define GET_CBR_LENGTH_TARGET (((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0x000fff00 ) >> 8)
+#define GET_CBR_TX_CNT_TARGET (((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0xff000000 ) >> 24)
+#define GET_CBR_TC_CNT_TARGET (((REG32(ADR_CBR_RG_PKT_GEN_1)) & 0x00ffffff ) >> 0)
+#define GET_CBR_PLCP_PSDU_DATA_MEM (((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0x000000ff ) >> 0)
+#define GET_CBR_PLCP_PSDU_PREAMBLE_SHORT (((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0x00000100 ) >> 8)
+#define GET_CBR_PLCP_BYTE_LENGTH (((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0x001ffe00 ) >> 9)
+#define GET_CBR_PLCP_PSDU_RATE (((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0x00600000 ) >> 21)
+#define GET_CBR_TAIL_TIME (((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0x1f800000 ) >> 23)
+#define GET_CBR_RG_O_PAD_PD (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_I_PAD_PD (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000002 ) >> 1)
+#define GET_CBR_SEL_ADCKP_INV (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000004 ) >> 2)
+#define GET_CBR_RG_PAD_DS (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000008 ) >> 3)
+#define GET_CBR_SEL_ADCKP_MUX (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000010 ) >> 4)
+#define GET_CBR_RG_PAD_DS_CLK (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000020 ) >> 5)
+#define GET_CBR_INTP_SEL (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000200 ) >> 9)
+#define GET_CBR_IQ_SWP (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000400 ) >> 10)
+#define GET_CBR_RG_EN_EXT_DA (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000800 ) >> 11)
+#define GET_CBR_RG_DIS_DA_OFFSET (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00001000 ) >> 12)
+#define GET_CBR_DBG_SEL (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x000f0000 ) >> 16)
+#define GET_CBR_DBG_EN (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00100000 ) >> 20)
+#define GET_CBR_RG_PKT_GEN_TX_CNT (((REG32(ADR_CBR_RG_PKT_GEN_TXCNT)) & 0xffffffff ) >> 0)
+#define GET_CBR_TP_SEL (((REG32(ADR_CBR_PATTERN_GEN)) & 0x0000001f ) >> 0)
+#define GET_CBR_IDEAL_IQ_EN (((REG32(ADR_CBR_PATTERN_GEN)) & 0x00000020 ) >> 5)
+#define GET_CBR_DATA_OUT_SEL (((REG32(ADR_CBR_PATTERN_GEN)) & 0x000001c0 ) >> 6)
+#define GET_CBR_TWO_TONE_EN (((REG32(ADR_CBR_PATTERN_GEN)) & 0x00000200 ) >> 9)
+#define GET_CBR_FREQ_SEL (((REG32(ADR_CBR_PATTERN_GEN)) & 0x00ff0000 ) >> 16)
+#define GET_CBR_IQ_SCALE (((REG32(ADR_CBR_PATTERN_GEN)) & 0xff000000 ) >> 24)
+#define GET_CPU_QUE_POP (((REG32(ADR_MB_CPU_INT)) & 0x00000001 ) >> 0)
+#define GET_CPU_INT (((REG32(ADR_MB_CPU_INT)) & 0x00000004 ) >> 2)
+#define GET_CPU_ID_TB0 (((REG32(ADR_CPU_ID_TB0)) & 0xffffffff ) >> 0)
+#define GET_CPU_ID_TB1 (((REG32(ADR_CPU_ID_TB1)) & 0xffffffff ) >> 0)
+#define GET_HW_PKTID (((REG32(ADR_CH0_TRIG_1)) & 0x000007ff ) >> 0)
+#define GET_CH0_INT_ADDR (((REG32(ADR_CH0_TRIG_0)) & 0xffffffff ) >> 0)
+#define GET_PRI_HW_PKTID (((REG32(ADR_CH0_PRI_TRIG)) & 0x000007ff ) >> 0)
+#define GET_CH0_FULL (((REG32(ADR_MCU_STATUS)) & 0x00000001 ) >> 0)
+#define GET_FF0_EMPTY (((REG32(ADR_MCU_STATUS)) & 0x00000002 ) >> 1)
+#define GET_RLS_BUSY (((REG32(ADR_MCU_STATUS)) & 0x00000200 ) >> 9)
+#define GET_RLS_COUNT_CLR (((REG32(ADR_MCU_STATUS)) & 0x00000400 ) >> 10)
+#define GET_RTN_COUNT_CLR (((REG32(ADR_MCU_STATUS)) & 0x00000800 ) >> 11)
+#define GET_RLS_COUNT (((REG32(ADR_MCU_STATUS)) & 0x00ff0000 ) >> 16)
+#define GET_RTN_COUNT (((REG32(ADR_MCU_STATUS)) & 0xff000000 ) >> 24)
+#define GET_FF0_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x0000001f ) >> 0)
+#define GET_FF1_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x000001e0 ) >> 5)
+#define GET_FF3_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x00003800 ) >> 11)
+#define GET_FF5_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x000e0000 ) >> 17)
+#define GET_FF6_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x00700000 ) >> 20)
+#define GET_FF7_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x03800000 ) >> 23)
+#define GET_FF8_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x1c000000 ) >> 26)
+#define GET_FF9_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0xe0000000 ) >> 29)
+#define GET_FF10_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00000007 ) >> 0)
+#define GET_FF11_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00000038 ) >> 3)
+#define GET_FF12_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x000001c0 ) >> 6)
+#define GET_FF13_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00000600 ) >> 9)
+#define GET_FF14_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00001800 ) >> 11)
+#define GET_FF15_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00006000 ) >> 13)
+#define GET_FF4_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x000f8000 ) >> 15)
+#define GET_FF2_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00700000 ) >> 20)
+#define GET_CH1_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000002 ) >> 1)
+#define GET_CH2_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000004 ) >> 2)
+#define GET_CH3_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000008 ) >> 3)
+#define GET_CH4_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000010 ) >> 4)
+#define GET_CH5_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000020 ) >> 5)
+#define GET_CH6_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000040 ) >> 6)
+#define GET_CH7_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000080 ) >> 7)
+#define GET_CH8_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000100 ) >> 8)
+#define GET_CH9_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000200 ) >> 9)
+#define GET_CH10_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000400 ) >> 10)
+#define GET_CH11_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000800 ) >> 11)
+#define GET_CH12_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00001000 ) >> 12)
+#define GET_CH13_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00002000 ) >> 13)
+#define GET_CH14_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00004000 ) >> 14)
+#define GET_CH15_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00008000 ) >> 15)
+#define GET_HALT_CH0 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000001 ) >> 0)
+#define GET_HALT_CH1 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000002 ) >> 1)
+#define GET_HALT_CH2 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000004 ) >> 2)
+#define GET_HALT_CH3 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000008 ) >> 3)
+#define GET_HALT_CH4 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000010 ) >> 4)
+#define GET_HALT_CH5 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000020 ) >> 5)
+#define GET_HALT_CH6 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000040 ) >> 6)
+#define GET_HALT_CH7 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000080 ) >> 7)
+#define GET_HALT_CH8 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000100 ) >> 8)
+#define GET_HALT_CH9 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000200 ) >> 9)
+#define GET_HALT_CH10 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000400 ) >> 10)
+#define GET_HALT_CH11 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000800 ) >> 11)
+#define GET_HALT_CH12 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00001000 ) >> 12)
+#define GET_HALT_CH13 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00002000 ) >> 13)
+#define GET_HALT_CH14 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00004000 ) >> 14)
+#define GET_HALT_CH15 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00008000 ) >> 15)
+#define GET_STOP_MBOX (((REG32(ADR_MBOX_HALT_CFG)) & 0x00010000 ) >> 16)
+#define GET_MB_ERR_AUTO_HALT_EN (((REG32(ADR_MBOX_HALT_CFG)) & 0x00100000 ) >> 20)
+#define GET_MB_EXCEPT_CLR (((REG32(ADR_MBOX_HALT_CFG)) & 0x00200000 ) >> 21)
+#define GET_MB_EXCEPT_CASE (((REG32(ADR_MBOX_HALT_CFG)) & 0xff000000 ) >> 24)
+#define GET_MB_DBG_TIME_STEP (((REG32(ADR_MB_DBG_CFG1)) & 0x0000ffff ) >> 0)
+#define GET_DBG_TYPE (((REG32(ADR_MB_DBG_CFG1)) & 0x00030000 ) >> 16)
+#define GET_MB_DBG_CLR (((REG32(ADR_MB_DBG_CFG1)) & 0x00040000 ) >> 18)
+#define GET_DBG_ALC_LOG_EN (((REG32(ADR_MB_DBG_CFG1)) & 0x00080000 ) >> 19)
+#define GET_MB_DBG_COUNTER_EN (((REG32(ADR_MB_DBG_CFG1)) & 0x01000000 ) >> 24)
+#define GET_MB_DBG_EN (((REG32(ADR_MB_DBG_CFG1)) & 0x80000000 ) >> 31)
+#define GET_MB_DBG_RECORD_CNT (((REG32(ADR_MB_DBG_CFG2)) & 0x0000ffff ) >> 0)
+#define GET_MB_DBG_LENGTH (((REG32(ADR_MB_DBG_CFG2)) & 0xffff0000 ) >> 16)
+#define GET_MB_DBG_CFG_ADDR (((REG32(ADR_MB_DBG_CFG3)) & 0xffffffff ) >> 0)
+#define GET_DBG_HWID0_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000001 ) >> 0)
+#define GET_DBG_HWID1_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000002 ) >> 1)
+#define GET_DBG_HWID2_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000004 ) >> 2)
+#define GET_DBG_HWID3_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000008 ) >> 3)
+#define GET_DBG_HWID4_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000010 ) >> 4)
+#define GET_DBG_HWID5_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000020 ) >> 5)
+#define GET_DBG_HWID6_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000040 ) >> 6)
+#define GET_DBG_HWID7_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000080 ) >> 7)
+#define GET_DBG_HWID8_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000100 ) >> 8)
+#define GET_DBG_HWID9_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000200 ) >> 9)
+#define GET_DBG_HWID10_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000400 ) >> 10)
+#define GET_DBG_HWID11_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000800 ) >> 11)
+#define GET_DBG_HWID12_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00001000 ) >> 12)
+#define GET_DBG_HWID13_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00002000 ) >> 13)
+#define GET_DBG_HWID14_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00004000 ) >> 14)
+#define GET_DBG_HWID15_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00008000 ) >> 15)
+#define GET_DBG_HWID0_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00010000 ) >> 16)
+#define GET_DBG_HWID1_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00020000 ) >> 17)
+#define GET_DBG_HWID2_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00040000 ) >> 18)
+#define GET_DBG_HWID3_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00080000 ) >> 19)
+#define GET_DBG_HWID4_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00100000 ) >> 20)
+#define GET_DBG_HWID5_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00200000 ) >> 21)
+#define GET_DBG_HWID6_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00400000 ) >> 22)
+#define GET_DBG_HWID7_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00800000 ) >> 23)
+#define GET_DBG_HWID8_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x01000000 ) >> 24)
+#define GET_DBG_HWID9_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x02000000 ) >> 25)
+#define GET_DBG_HWID10_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x04000000 ) >> 26)
+#define GET_DBG_HWID11_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x08000000 ) >> 27)
+#define GET_DBG_HWID12_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x10000000 ) >> 28)
+#define GET_DBG_HWID13_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x20000000 ) >> 29)
+#define GET_DBG_HWID14_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x40000000 ) >> 30)
+#define GET_DBG_HWID15_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x80000000 ) >> 31)
+#define GET_MB_OUT_QUEUE_EN (((REG32(ADR_MB_OUT_QUEUE_CFG)) & 0x00000002 ) >> 1)
+#define GET_CH0_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000001 ) >> 0)
+#define GET_CH1_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000002 ) >> 1)
+#define GET_CH2_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000004 ) >> 2)
+#define GET_CH3_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000008 ) >> 3)
+#define GET_CH4_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000010 ) >> 4)
+#define GET_CH5_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000020 ) >> 5)
+#define GET_CH6_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000040 ) >> 6)
+#define GET_CH7_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000080 ) >> 7)
+#define GET_CH8_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000100 ) >> 8)
+#define GET_CH9_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000200 ) >> 9)
+#define GET_CH10_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000400 ) >> 10)
+#define GET_CH11_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000800 ) >> 11)
+#define GET_CH12_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00001000 ) >> 12)
+#define GET_CH13_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00002000 ) >> 13)
+#define GET_CH14_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00004000 ) >> 14)
+#define GET_CH15_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00008000 ) >> 15)
+#define GET_FFO0_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x0000001f ) >> 0)
+#define GET_FFO1_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x000003e0 ) >> 5)
+#define GET_FFO2_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x00000c00 ) >> 10)
+#define GET_FFO3_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x000f8000 ) >> 15)
+#define GET_FFO4_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x00300000 ) >> 20)
+#define GET_FFO5_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x0e000000 ) >> 25)
+#define GET_FFO6_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x0000000f ) >> 0)
+#define GET_FFO7_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x000003e0 ) >> 5)
+#define GET_FFO8_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x00007c00 ) >> 10)
+#define GET_FFO9_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x000f8000 ) >> 15)
+#define GET_FFO10_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x00f00000 ) >> 20)
+#define GET_FFO11_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x3e000000 ) >> 25)
+#define GET_FFO12_CNT (((REG32(ADR_RD_FFOUT_CNT3)) & 0x00000007 ) >> 0)
+#define GET_FFO13_CNT (((REG32(ADR_RD_FFOUT_CNT3)) & 0x00000060 ) >> 5)
+#define GET_FFO14_CNT (((REG32(ADR_RD_FFOUT_CNT3)) & 0x00000c00 ) >> 10)
+#define GET_FFO15_CNT (((REG32(ADR_RD_FFOUT_CNT3)) & 0x001f8000 ) >> 15)
+#define GET_CH0_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000001 ) >> 0)
+#define GET_CH1_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000002 ) >> 1)
+#define GET_CH2_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000004 ) >> 2)
+#define GET_CH3_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000008 ) >> 3)
+#define GET_CH4_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000010 ) >> 4)
+#define GET_CH5_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000020 ) >> 5)
+#define GET_CH6_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000040 ) >> 6)
+#define GET_CH7_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000080 ) >> 7)
+#define GET_CH8_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000100 ) >> 8)
+#define GET_CH9_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000200 ) >> 9)
+#define GET_CH10_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000400 ) >> 10)
+#define GET_CH11_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000800 ) >> 11)
+#define GET_CH12_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00001000 ) >> 12)
+#define GET_CH13_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00002000 ) >> 13)
+#define GET_CH14_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00004000 ) >> 14)
+#define GET_CH15_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00008000 ) >> 15)
+#define GET_CH0_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000001 ) >> 0)
+#define GET_CH1_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000002 ) >> 1)
+#define GET_CH2_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000004 ) >> 2)
+#define GET_CH3_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000008 ) >> 3)
+#define GET_CH4_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000010 ) >> 4)
+#define GET_CH5_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000020 ) >> 5)
+#define GET_CH6_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000040 ) >> 6)
+#define GET_CH7_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000080 ) >> 7)
+#define GET_CH8_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000100 ) >> 8)
+#define GET_CH9_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000200 ) >> 9)
+#define GET_CH10_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000400 ) >> 10)
+#define GET_CH11_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000800 ) >> 11)
+#define GET_CH12_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00001000 ) >> 12)
+#define GET_CH13_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00002000 ) >> 13)
+#define GET_CH14_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00004000 ) >> 14)
+#define GET_CH15_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00008000 ) >> 15)
+#define GET_MB_LOW_THOLD_EN (((REG32(ADR_MB_THRESHOLD6)) & 0x80000000 ) >> 31)
+#define GET_CH0_LOWTHOLD (((REG32(ADR_MB_THRESHOLD7)) & 0x0000001f ) >> 0)
+#define GET_CH1_LOWTHOLD (((REG32(ADR_MB_THRESHOLD7)) & 0x00001f00 ) >> 8)
+#define GET_CH2_LOWTHOLD (((REG32(ADR_MB_THRESHOLD7)) & 0x001f0000 ) >> 16)
+#define GET_CH3_LOWTHOLD (((REG32(ADR_MB_THRESHOLD7)) & 0x1f000000 ) >> 24)
+#define GET_CH4_LOWTHOLD (((REG32(ADR_MB_THRESHOLD8)) & 0x0000001f ) >> 0)
+#define GET_CH5_LOWTHOLD (((REG32(ADR_MB_THRESHOLD8)) & 0x00001f00 ) >> 8)
+#define GET_CH6_LOWTHOLD (((REG32(ADR_MB_THRESHOLD8)) & 0x001f0000 ) >> 16)
+#define GET_CH7_LOWTHOLD (((REG32(ADR_MB_THRESHOLD8)) & 0x1f000000 ) >> 24)
+#define GET_CH8_LOWTHOLD (((REG32(ADR_MB_THRESHOLD9)) & 0x0000001f ) >> 0)
+#define GET_CH9_LOWTHOLD (((REG32(ADR_MB_THRESHOLD9)) & 0x00001f00 ) >> 8)
+#define GET_CH10_LOWTHOLD (((REG32(ADR_MB_THRESHOLD9)) & 0x001f0000 ) >> 16)
+#define GET_CH11_LOWTHOLD (((REG32(ADR_MB_THRESHOLD9)) & 0x1f000000 ) >> 24)
+#define GET_CH12_LOWTHOLD (((REG32(ADR_MB_THRESHOLD10)) & 0x0000001f ) >> 0)
+#define GET_CH13_LOWTHOLD (((REG32(ADR_MB_THRESHOLD10)) & 0x00001f00 ) >> 8)
+#define GET_CH14_LOWTHOLD (((REG32(ADR_MB_THRESHOLD10)) & 0x001f0000 ) >> 16)
+#define GET_CH15_LOWTHOLD (((REG32(ADR_MB_THRESHOLD10)) & 0x1f000000 ) >> 24)
+#define GET_TRASH_TIMEOUT_EN (((REG32(ADR_MB_TRASH_CFG)) & 0x00000001 ) >> 0)
+#define GET_TRASH_CAN_INT (((REG32(ADR_MB_TRASH_CFG)) & 0x00000002 ) >> 1)
+#define GET_TRASH_INT_ID (((REG32(ADR_MB_TRASH_CFG)) & 0x000007f0 ) >> 4)
+#define GET_TRASH_TIMEOUT (((REG32(ADR_MB_TRASH_CFG)) & 0x03ff0000 ) >> 16)
+#define GET_CH0_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000001 ) >> 0)
+#define GET_CH1_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000002 ) >> 1)
+#define GET_CH2_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000004 ) >> 2)
+#define GET_CH3_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000008 ) >> 3)
+#define GET_CH4_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000010 ) >> 4)
+#define GET_CH5_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000020 ) >> 5)
+#define GET_CH6_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000040 ) >> 6)
+#define GET_CH7_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000080 ) >> 7)
+#define GET_CH8_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000100 ) >> 8)
+#define GET_CH9_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000200 ) >> 9)
+#define GET_CH10_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000400 ) >> 10)
+#define GET_CH11_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000800 ) >> 11)
+#define GET_CH12_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00001000 ) >> 12)
+#define GET_CH13_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00002000 ) >> 13)
+#define GET_CH14_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00004000 ) >> 14)
+#define GET_CPU_ID_TB2 (((REG32(ADR_CPU_ID_TB2)) & 0xffffffff ) >> 0)
+#define GET_CPU_ID_TB3 (((REG32(ADR_CPU_ID_TB3)) & 0xffffffff ) >> 0)
+#define GET_IQ_LOG_EN (((REG32(ADR_PHY_IQ_LOG_CFG0)) & 0x00000001 ) >> 0)
+#define GET_IQ_LOG_STOP_MODE (((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0x00000001 ) >> 0)
+#define GET_GPIO_STOP_EN (((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0x00000010 ) >> 4)
+#define GET_GPIO_STOP_POL (((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0x00000020 ) >> 5)
+#define GET_IQ_LOG_TIMER (((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0xffff0000 ) >> 16)
+#define GET_IQ_LOG_LEN (((REG32(ADR_PHY_IQ_LOG_LEN)) & 0x0000ffff ) >> 0)
+#define GET_IQ_LOG_TAIL_ADR (((REG32(ADR_PHY_IQ_LOG_PTR)) & 0x0000ffff ) >> 0)
+#define GET_ALC_LENG (((REG32(ADR_WR_ALC)) & 0x0003ffff ) >> 0)
+#define GET_CH0_DYN_PRI (((REG32(ADR_WR_ALC)) & 0x00300000 ) >> 20)
+#define GET_MCU_PKTID (((REG32(ADR_GETID)) & 0xffffffff ) >> 0)
+#define GET_CH0_STA_PRI (((REG32(ADR_CH_STA_PRI)) & 0x00000003 ) >> 0)
+#define GET_CH1_STA_PRI (((REG32(ADR_CH_STA_PRI)) & 0x00000030 ) >> 4)
+#define GET_CH2_STA_PRI (((REG32(ADR_CH_STA_PRI)) & 0x00000300 ) >> 8)
+#define GET_CH3_STA_PRI (((REG32(ADR_CH_STA_PRI)) & 0x00003000 ) >> 12)
+#define GET_ID_TB0 (((REG32(ADR_RD_ID0)) & 0xffffffff ) >> 0)
+#define GET_ID_TB1 (((REG32(ADR_RD_ID1)) & 0xffffffff ) >> 0)
+#define GET_ID_MNG_HALT (((REG32(ADR_IMD_CFG)) & 0x00000010 ) >> 4)
+#define GET_ID_MNG_ERR_HALT_EN (((REG32(ADR_IMD_CFG)) & 0x00000020 ) >> 5)
+#define GET_ID_EXCEPT_FLG_CLR (((REG32(ADR_IMD_CFG)) & 0x00000040 ) >> 6)
+#define GET_ID_EXCEPT_FLG (((REG32(ADR_IMD_CFG)) & 0x00000080 ) >> 7)
+#define GET_ID_FULL (((REG32(ADR_IMD_STA)) & 0x00000001 ) >> 0)
+#define GET_ID_MNG_BUSY (((REG32(ADR_IMD_STA)) & 0x00000002 ) >> 1)
+#define GET_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000004 ) >> 2)
+#define GET_CH0_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000010 ) >> 4)
+#define GET_CH1_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000020 ) >> 5)
+#define GET_CH2_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000040 ) >> 6)
+#define GET_CH3_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000080 ) >> 7)
+#define GET_REQ_LOCK_INT_EN (((REG32(ADR_IMD_STA)) & 0x00000100 ) >> 8)
+#define GET_REQ_LOCK_INT (((REG32(ADR_IMD_STA)) & 0x00000200 ) >> 9)
+#define GET_MCU_ALC_READY (((REG32(ADR_ALC_STA)) & 0x00000001 ) >> 0)
+#define GET_ALC_FAIL (((REG32(ADR_ALC_STA)) & 0x00000002 ) >> 1)
+#define GET_ALC_BUSY (((REG32(ADR_ALC_STA)) & 0x00000004 ) >> 2)
+#define GET_CH0_NVLD (((REG32(ADR_ALC_STA)) & 0x00000010 ) >> 4)
+#define GET_CH1_NVLD (((REG32(ADR_ALC_STA)) & 0x00000020 ) >> 5)
+#define GET_CH2_NVLD (((REG32(ADR_ALC_STA)) & 0x00000040 ) >> 6)
+#define GET_CH3_NVLD (((REG32(ADR_ALC_STA)) & 0x00000080 ) >> 7)
+#define GET_ALC_INT_ID (((REG32(ADR_ALC_STA)) & 0x00007f00 ) >> 8)
+#define GET_ALC_TIMEOUT (((REG32(ADR_ALC_STA)) & 0x03ff0000 ) >> 16)
+#define GET_ALC_TIMEOUT_INT_EN (((REG32(ADR_ALC_STA)) & 0x40000000 ) >> 30)
+#define GET_ALC_TIMEOUT_INT (((REG32(ADR_ALC_STA)) & 0x80000000 ) >> 31)
+#define GET_TX_ID_COUNT (((REG32(ADR_TRX_ID_COUNT)) & 0x000000ff ) >> 0)
+#define GET_RX_ID_COUNT (((REG32(ADR_TRX_ID_COUNT)) & 0x0000ff00 ) >> 8)
+#define GET_TX_ID_THOLD (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x000000ff ) >> 0)
+#define GET_RX_ID_THOLD (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x0000ff00 ) >> 8)
+#define GET_ID_THOLD_RX_INT (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x00010000 ) >> 16)
+#define GET_RX_INT_CH (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x000e0000 ) >> 17)
+#define GET_ID_THOLD_TX_INT (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x00100000 ) >> 20)
+#define GET_TX_INT_CH (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x00e00000 ) >> 21)
+#define GET_ID_THOLD_INT_EN (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x01000000 ) >> 24)
+#define GET_TX_ID_TB0 (((REG32(ADR_TX_ID0)) & 0xffffffff ) >> 0)
+#define GET_TX_ID_TB1 (((REG32(ADR_TX_ID1)) & 0xffffffff ) >> 0)
+#define GET_RX_ID_TB0 (((REG32(ADR_RX_ID0)) & 0xffffffff ) >> 0)
+#define GET_RX_ID_TB1 (((REG32(ADR_RX_ID1)) & 0xffffffff ) >> 0)
+#define GET_DOUBLE_RLS_INT_EN (((REG32(ADR_RTN_STA)) & 0x00000001 ) >> 0)
+#define GET_ID_DOUBLE_RLS_INT (((REG32(ADR_RTN_STA)) & 0x00000002 ) >> 1)
+#define GET_DOUBLE_RLS_ID (((REG32(ADR_RTN_STA)) & 0x00007f00 ) >> 8)
+#define GET_ID_LEN_THOLD_INT_EN (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00000001 ) >> 0)
+#define GET_ALL_ID_LEN_THOLD_INT (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00000002 ) >> 1)
+#define GET_TX_ID_LEN_THOLD_INT (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00000004 ) >> 2)
+#define GET_RX_ID_LEN_THOLD_INT (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00000008 ) >> 3)
+#define GET_ID_TX_LEN_THOLD (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00001ff0 ) >> 4)
+#define GET_ID_RX_LEN_THOLD (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x003fe000 ) >> 13)
+#define GET_ID_LEN_THOLD (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x7fc00000 ) >> 22)
+#define GET_ALL_ID_ALC_LEN (((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0x000001ff ) >> 0)
+#define GET_TX_ID_ALC_LEN (((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0x0003fe00 ) >> 9)
+#define GET_RX_ID_ALC_LEN (((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0x07fc0000 ) >> 18)
+#define GET_CH_ARB_EN (((REG32(ADR_CH_ARB_PRI)) & 0x00000001 ) >> 0)
+#define GET_CH_PRI1 (((REG32(ADR_CH_ARB_PRI)) & 0x00000030 ) >> 4)
+#define GET_CH_PRI2 (((REG32(ADR_CH_ARB_PRI)) & 0x00000300 ) >> 8)
+#define GET_CH_PRI3 (((REG32(ADR_CH_ARB_PRI)) & 0x00003000 ) >> 12)
+#define GET_CH_PRI4 (((REG32(ADR_CH_ARB_PRI)) & 0x00030000 ) >> 16)
+#define GET_TX_ID_REMAIN (((REG32(ADR_TX_ID_REMAIN_STATUS)) & 0x0000007f ) >> 0)
+#define GET_TX_PAGE_REMAIN (((REG32(ADR_TX_ID_REMAIN_STATUS)) & 0x0001ff00 ) >> 8)
+#define GET_ID_PAGE_MAX_SIZE (((REG32(ADR_ID_INFO_STA)) & 0x000001ff ) >> 0)
+#define GET_TX_PAGE_LIMIT (((REG32(ADR_TX_LIMIT_INTR)) & 0x000001ff ) >> 0)
+#define GET_TX_COUNT_LIMIT (((REG32(ADR_TX_LIMIT_INTR)) & 0x00ff0000 ) >> 16)
+#define GET_TX_LIMIT_INT (((REG32(ADR_TX_LIMIT_INTR)) & 0x40000000 ) >> 30)
+#define GET_TX_LIMIT_INT_EN (((REG32(ADR_TX_LIMIT_INTR)) & 0x80000000 ) >> 31)
+#define GET_TX_PAGE_USE_7_0 (((REG32(ADR_TX_ID_ALL_INFO)) & 0x000000ff ) >> 0)
+#define GET_TX_ID_USE_5_0 (((REG32(ADR_TX_ID_ALL_INFO)) & 0x00003f00 ) >> 8)
+#define GET_EDCA0_FFO_CNT (((REG32(ADR_TX_ID_ALL_INFO)) & 0x0003c000 ) >> 14)
+#define GET_EDCA1_FFO_CNT_3_0 (((REG32(ADR_TX_ID_ALL_INFO)) & 0x003c0000 ) >> 18)
+#define GET_EDCA2_FFO_CNT (((REG32(ADR_TX_ID_ALL_INFO)) & 0x07c00000 ) >> 22)
+#define GET_EDCA3_FFO_CNT (((REG32(ADR_TX_ID_ALL_INFO)) & 0xf8000000 ) >> 27)
+#define GET_ID_TB2 (((REG32(ADR_RD_ID2)) & 0xffffffff ) >> 0)
+#define GET_ID_TB3 (((REG32(ADR_RD_ID3)) & 0xffffffff ) >> 0)
+#define GET_TX_ID_TB2 (((REG32(ADR_TX_ID2)) & 0xffffffff ) >> 0)
+#define GET_TX_ID_TB3 (((REG32(ADR_TX_ID3)) & 0xffffffff ) >> 0)
+#define GET_RX_ID_TB2 (((REG32(ADR_RX_ID2)) & 0xffffffff ) >> 0)
+#define GET_RX_ID_TB3 (((REG32(ADR_RX_ID3)) & 0xffffffff ) >> 0)
+#define GET_TX_PAGE_USE2 (((REG32(ADR_TX_ID_ALL_INFO2)) & 0x000001ff ) >> 0)
+#define GET_TX_ID_USE2 (((REG32(ADR_TX_ID_ALL_INFO2)) & 0x0001fe00 ) >> 9)
+#define GET_EDCA4_FFO_CNT (((REG32(ADR_TX_ID_ALL_INFO2)) & 0x001e0000 ) >> 17)
+#define GET_TX_PAGE_USE3 (((REG32(ADR_TX_ID_ALL_INFO_A)) & 0x000001ff ) >> 0)
+#define GET_TX_ID_USE3 (((REG32(ADR_TX_ID_ALL_INFO_A)) & 0x0001fe00 ) >> 9)
+#define GET_EDCA1_FFO_CNT2 (((REG32(ADR_TX_ID_ALL_INFO_A)) & 0x03e00000 ) >> 21)
+#define GET_EDCA4_FFO_CNT2 (((REG32(ADR_TX_ID_ALL_INFO_A)) & 0x3c000000 ) >> 26)
+#define GET_TX_PAGE_USE4 (((REG32(ADR_TX_ID_ALL_INFO_B)) & 0x000001ff ) >> 0)
+#define GET_TX_ID_USE4 (((REG32(ADR_TX_ID_ALL_INFO_B)) & 0x0001fe00 ) >> 9)
+#define GET_EDCA2_FFO_CNT2 (((REG32(ADR_TX_ID_ALL_INFO_B)) & 0x003e0000 ) >> 17)
+#define GET_EDCA3_FFO_CNT2 (((REG32(ADR_TX_ID_ALL_INFO_B)) & 0x07c00000 ) >> 22)
+#define GET_TX_ID_IFO_LEN (((REG32(ADR_TX_ID_REMAIN_STATUS2)) & 0x000001ff ) >> 0)
+#define GET_RX_ID_IFO_LEN (((REG32(ADR_TX_ID_REMAIN_STATUS2)) & 0x01ff0000 ) >> 16)
+#define GET_MAX_ALL_ALC_ID_CNT (((REG32(ADR_ALC_ID_INFO)) & 0x000000ff ) >> 0)
+#define GET_MAX_TX_ALC_ID_CNT (((REG32(ADR_ALC_ID_INFO)) & 0x0000ff00 ) >> 8)
+#define GET_MAX_RX_ALC_ID_CNT (((REG32(ADR_ALC_ID_INFO)) & 0x00ff0000 ) >> 16)
+#define GET_MAX_ALL_ID_ALC_LEN (((REG32(ADR_ALC_ID_INF1)) & 0x000001ff ) >> 0)
+#define GET_MAX_TX_ID_ALC_LEN (((REG32(ADR_ALC_ID_INF1)) & 0x0003fe00 ) >> 9)
+#define GET_MAX_RX_ID_ALC_LEN (((REG32(ADR_ALC_ID_INF1)) & 0x07fc0000 ) >> 18)
+#define GET_RG_PMDLBK (((REG32(ADR_PHY_EN_0)) & 0x00000001 ) >> 0)
+#define GET_RG_RDYACK_SEL (((REG32(ADR_PHY_EN_0)) & 0x00000006 ) >> 1)
+#define GET_RG_ADEDGE_SEL (((REG32(ADR_PHY_EN_0)) & 0x00000008 ) >> 3)
+#define GET_RG_SIGN_SWAP (((REG32(ADR_PHY_EN_0)) & 0x00000010 ) >> 4)
+#define GET_RG_IQ_SWAP (((REG32(ADR_PHY_EN_0)) & 0x00000020 ) >> 5)
+#define GET_RG_Q_INV (((REG32(ADR_PHY_EN_0)) & 0x00000040 ) >> 6)
+#define GET_RG_I_INV (((REG32(ADR_PHY_EN_0)) & 0x00000080 ) >> 7)
+#define GET_RG_BYPASS_ACI (((REG32(ADR_PHY_EN_0)) & 0x00000100 ) >> 8)
+#define GET_RG_LBK_ANA_PATH (((REG32(ADR_PHY_EN_0)) & 0x00000200 ) >> 9)
+#define GET_RG_SPECTRUM_LEAKY_FACTOR (((REG32(ADR_PHY_EN_0)) & 0x00000c00 ) >> 10)
+#define GET_RG_SPECTRUM_BW (((REG32(ADR_PHY_EN_0)) & 0x00003000 ) >> 12)
+#define GET_RG_SPECTRUM_FREQ_MANUAL (((REG32(ADR_PHY_EN_0)) & 0x00004000 ) >> 14)
+#define GET_RG_SPECTRUM_EN (((REG32(ADR_PHY_EN_0)) & 0x00008000 ) >> 15)
+#define GET_RG_TXPWRLVL_SET (((REG32(ADR_PHY_EN_0)) & 0x00ff0000 ) >> 16)
+#define GET_RG_TXPWRLVL_SEL (((REG32(ADR_PHY_EN_0)) & 0x01000000 ) >> 24)
+#define GET_RG_RF_BB_CLK_SEL (((REG32(ADR_PHY_EN_0)) & 0x80000000 ) >> 31)
+#define GET_RG_PHY_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000001 ) >> 0)
+#define GET_RG_PHYRX_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000002 ) >> 1)
+#define GET_RG_PHYTX_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000004 ) >> 2)
+#define GET_RG_PHY11GN_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000008 ) >> 3)
+#define GET_RG_PHY11B_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000010 ) >> 4)
+#define GET_RG_PHYRXFIFO_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000020 ) >> 5)
+#define GET_RG_PHYTXFIFO_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000040 ) >> 6)
+#define GET_RG_PHY11BGN_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000100 ) >> 8)
+#define GET_RG_FORCE_11GN_EN (((REG32(ADR_PHY_EN_1)) & 0x00001000 ) >> 12)
+#define GET_RG_FORCE_11B_EN (((REG32(ADR_PHY_EN_1)) & 0x00002000 ) >> 13)
+#define GET_RG_FFT_MEM_CLK_EN_RX (((REG32(ADR_PHY_EN_1)) & 0x00004000 ) >> 14)
+#define GET_RG_FFT_MEM_CLK_EN_TX (((REG32(ADR_PHY_EN_1)) & 0x00008000 ) >> 15)
+#define GET_RG_PHY_IQ_TRIG_SEL (((REG32(ADR_PHY_EN_1)) & 0x000f0000 ) >> 16)
+#define GET_RG_SPECTRUM_FREQ (((REG32(ADR_PHY_EN_1)) & 0x3ff00000 ) >> 20)
+#define GET_SVN_VERSION (((REG32(ADR_SVN_VERSION_REG)) & 0xffffffff ) >> 0)
+#define GET_RG_LENGTH (((REG32(ADR_PHY_PKT_GEN_0)) & 0x0000ffff ) >> 0)
+#define GET_RG_PKT_MODE (((REG32(ADR_PHY_PKT_GEN_0)) & 0x00070000 ) >> 16)
+#define GET_RG_CH_BW (((REG32(ADR_PHY_PKT_GEN_0)) & 0x00380000 ) >> 19)
+#define GET_RG_PRM (((REG32(ADR_PHY_PKT_GEN_0)) & 0x00400000 ) >> 22)
+#define GET_RG_SHORTGI (((REG32(ADR_PHY_PKT_GEN_0)) & 0x00800000 ) >> 23)
+#define GET_RG_RATE (((REG32(ADR_PHY_PKT_GEN_0)) & 0x7f000000 ) >> 24)
+#define GET_RG_L_LENGTH (((REG32(ADR_PHY_PKT_GEN_1)) & 0x00000fff ) >> 0)
+#define GET_RG_L_RATE (((REG32(ADR_PHY_PKT_GEN_1)) & 0x00007000 ) >> 12)
+#define GET_RG_SERVICE (((REG32(ADR_PHY_PKT_GEN_1)) & 0xffff0000 ) >> 16)
+#define GET_RG_SMOOTHING (((REG32(ADR_PHY_PKT_GEN_2)) & 0x00000001 ) >> 0)
+#define GET_RG_NO_SOUND (((REG32(ADR_PHY_PKT_GEN_2)) & 0x00000002 ) >> 1)
+#define GET_RG_AGGREGATE (((REG32(ADR_PHY_PKT_GEN_2)) & 0x00000004 ) >> 2)
+#define GET_RG_STBC (((REG32(ADR_PHY_PKT_GEN_2)) & 0x00000018 ) >> 3)
+#define GET_RG_FEC (((REG32(ADR_PHY_PKT_GEN_2)) & 0x00000020 ) >> 5)
+#define GET_RG_N_ESS (((REG32(ADR_PHY_PKT_GEN_2)) & 0x000000c0 ) >> 6)
+#define GET_RG_TXPWRLVL (((REG32(ADR_PHY_PKT_GEN_2)) & 0x0000ff00 ) >> 8)
+#define GET_RG_TX_START (((REG32(ADR_PHY_PKT_GEN_3)) & 0x00000001 ) >> 0)
+#define GET_RG_IFS_TIME (((REG32(ADR_PHY_PKT_GEN_3)) & 0x000000fc ) >> 2)
+#define GET_RG_CONTINUOUS_DATA (((REG32(ADR_PHY_PKT_GEN_3)) & 0x00000100 ) >> 8)
+#define GET_RG_DATA_SEL (((REG32(ADR_PHY_PKT_GEN_3)) & 0x00000600 ) >> 9)
+#define GET_RG_TX_D (((REG32(ADR_PHY_PKT_GEN_3)) & 0x00ff0000 ) >> 16)
+#define GET_RG_TX_CNT_TARGET (((REG32(ADR_PHY_PKT_GEN_4)) & 0xffffffff ) >> 0)
+#define GET_RG_FFT_IFFT_MODE (((REG32(ADR_PHY_REG_00)) & 0x000000c0 ) >> 6)
+#define GET_RG_DAC_DBG_MODE (((REG32(ADR_PHY_REG_00)) & 0x00000100 ) >> 8)
+#define GET_RG_DAC_SGN_SWAP (((REG32(ADR_PHY_REG_00)) & 0x00000200 ) >> 9)
+#define GET_RG_TXD_SEL (((REG32(ADR_PHY_REG_00)) & 0x00000c00 ) >> 10)
+#define GET_RG_UP8X (((REG32(ADR_PHY_REG_00)) & 0x00ff0000 ) >> 16)
+#define GET_RG_IQ_DC_BYP (((REG32(ADR_PHY_REG_00)) & 0x01000000 ) >> 24)
+#define GET_RG_IQ_DC_LEAKY_FACTOR (((REG32(ADR_PHY_REG_00)) & 0x30000000 ) >> 28)
+#define GET_RG_DAC_DCEN (((REG32(ADR_PHY_REG_01)) & 0x00000001 ) >> 0)
+#define GET_RG_DAC_DCQ (((REG32(ADR_PHY_REG_01)) & 0x00003ff0 ) >> 4)
+#define GET_RG_DAC_DCI (((REG32(ADR_PHY_REG_01)) & 0x03ff0000 ) >> 16)
+#define GET_RG_PGA_REFDB_SAT (((REG32(ADR_PHY_REG_02_AGC)) & 0x0000007f ) >> 0)
+#define GET_RG_PGA_REFDB_TOP (((REG32(ADR_PHY_REG_02_AGC)) & 0x00007f00 ) >> 8)
+#define GET_RG_PGA_REF_UND (((REG32(ADR_PHY_REG_02_AGC)) & 0x03ff0000 ) >> 16)
+#define GET_RG_RF_REF_SAT (((REG32(ADR_PHY_REG_02_AGC)) & 0xf0000000 ) >> 28)
+#define GET_RG_PGAGC_SET (((REG32(ADR_PHY_REG_03_AGC)) & 0x0000000f ) >> 0)
+#define GET_RG_PGAGC_OW (((REG32(ADR_PHY_REG_03_AGC)) & 0x00000010 ) >> 4)
+#define GET_RG_RFGC_SET (((REG32(ADR_PHY_REG_03_AGC)) & 0x00000060 ) >> 5)
+#define GET_RG_RFGC_OW (((REG32(ADR_PHY_REG_03_AGC)) & 0x00000080 ) >> 7)
+#define GET_RG_WAIT_T_RXAGC (((REG32(ADR_PHY_REG_03_AGC)) & 0x00003f00 ) >> 8)
+#define GET_RG_RXAGC_SET (((REG32(ADR_PHY_REG_03_AGC)) & 0x00004000 ) >> 14)
+#define GET_RG_RXAGC_OW (((REG32(ADR_PHY_REG_03_AGC)) & 0x00008000 ) >> 15)
+#define GET_RG_WAIT_T_FINAL (((REG32(ADR_PHY_REG_03_AGC)) & 0x003f0000 ) >> 16)
+#define GET_RG_WAIT_T (((REG32(ADR_PHY_REG_03_AGC)) & 0x3f000000 ) >> 24)
+#define GET_RG_ULG_PGA_SAT_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x0000000f ) >> 0)
+#define GET_RG_LG_PGA_UND_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x000000f0 ) >> 4)
+#define GET_RG_LG_PGA_SAT_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x00000f00 ) >> 8)
+#define GET_RG_LG_RF_SAT_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x0000f000 ) >> 12)
+#define GET_RG_MG_RF_SAT_PGANOREF_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x000f0000 ) >> 16)
+#define GET_RG_HG_PGA_SAT2_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x00f00000 ) >> 20)
+#define GET_RG_HG_PGA_SAT1_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x0f000000 ) >> 24)
+#define GET_RG_HG_RF_SAT_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0xf0000000 ) >> 28)
+#define GET_RG_MG_PGA_JB_TH (((REG32(ADR_PHY_REG_05_AGC)) & 0x0000000f ) >> 0)
+#define GET_RG_MA_PGA_LOW_TH_CNT_LMT (((REG32(ADR_PHY_REG_05_AGC)) & 0x001f0000 ) >> 16)
+#define GET_RG_WR_RFGC_INIT_SET (((REG32(ADR_PHY_REG_05_AGC)) & 0x00600000 ) >> 21)
+#define GET_RG_WR_RFGC_INIT_EN (((REG32(ADR_PHY_REG_05_AGC)) & 0x00800000 ) >> 23)
+#define GET_RG_MA_PGA_HIGH_TH_CNT_LMT (((REG32(ADR_PHY_REG_05_AGC)) & 0x1f000000 ) >> 24)
+#define GET_RG_AGC_THRESHOLD (((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0x00003fff ) >> 0)
+#define GET_RG_ACI_POINT_CNT_LMT_11B (((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0x007f0000 ) >> 16)
+#define GET_RG_ACI_DAGC_LEAKY_FACTOR_11B (((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0x03000000 ) >> 24)
+#define GET_RG_WR_ACI_GAIN_INI_SEL_11B (((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0x000000ff ) >> 0)
+#define GET_RG_WR_ACI_GAIN_SEL_11B (((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0x0000ff00 ) >> 8)
+#define GET_RG_ACI_DAGC_SET_VALUE_11B (((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0x007f0000 ) >> 16)
+#define GET_RG_WR_ACI_GAIN_OW_11B (((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0x80000000 ) >> 31)
+#define GET_RG_ACI_POINT_CNT_LMT_11GN (((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0x000000ff ) >> 0)
+#define GET_RG_ACI_DAGC_LEAKY_FACTOR_11GN (((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0x00000300 ) >> 8)
+#define GET_RG_ACI_DAGC_DONE_CNT_LMT_11GN (((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0xff000000 ) >> 24)
+#define GET_RG_ACI_DAGC_SET_VALUE_11GN (((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0x0000007f ) >> 0)
+#define GET_RG_ACI_GAIN_INI_VAL_11GN (((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0x0000ff00 ) >> 8)
+#define GET_RG_ACI_GAIN_OW_VAL_11GN (((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0x00ff0000 ) >> 16)
+#define GET_RG_ACI_GAIN_OW_11GN (((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0x80000000 ) >> 31)
+#define GET_RO_CCA_PWR_MA_11GN (((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0x0000007f ) >> 0)
+#define GET_RO_ED_STATE (((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0x00008000 ) >> 15)
+#define GET_RO_CCA_PWR_MA_11B (((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0x007f0000 ) >> 16)
+#define GET_RO_PGA_PWR_FF1 (((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0x00003fff ) >> 0)
+#define GET_RO_RF_PWR_FF1 (((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0x000f0000 ) >> 16)
+#define GET_RO_PGAGC_FF1 (((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0x0f000000 ) >> 24)
+#define GET_RO_RFGC_FF1 (((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0x30000000 ) >> 28)
+#define GET_RO_PGA_PWR_FF2 (((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0x00003fff ) >> 0)
+#define GET_RO_RF_PWR_FF2 (((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0x000f0000 ) >> 16)
+#define GET_RO_PGAGC_FF2 (((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0x0f000000 ) >> 24)
+#define GET_RO_RFGC_FF2 (((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0x30000000 ) >> 28)
+#define GET_RO_PGA_PWR_FF3 (((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0x00003fff ) >> 0)
+#define GET_RO_RF_PWR_FF3 (((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0x000f0000 ) >> 16)
+#define GET_RO_PGAGC_FF3 (((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0x0f000000 ) >> 24)
+#define GET_RO_RFGC_FF3 (((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0x30000000 ) >> 28)
+#define GET_RG_TX_DES_RATE (((REG32(ADR_PHY_REG_10_TX_DES)) & 0x0000001f ) >> 0)
+#define GET_RG_TX_DES_MODE (((REG32(ADR_PHY_REG_10_TX_DES)) & 0x00001f00 ) >> 8)
+#define GET_RG_TX_DES_LEN_LO (((REG32(ADR_PHY_REG_10_TX_DES)) & 0x001f0000 ) >> 16)
+#define GET_RG_TX_DES_LEN_UP (((REG32(ADR_PHY_REG_10_TX_DES)) & 0x1f000000 ) >> 24)
+#define GET_RG_TX_DES_SRVC_UP (((REG32(ADR_PHY_REG_11_TX_DES)) & 0x0000001f ) >> 0)
+#define GET_RG_TX_DES_L_LEN_LO (((REG32(ADR_PHY_REG_11_TX_DES)) & 0x00001f00 ) >> 8)
+#define GET_RG_TX_DES_L_LEN_UP (((REG32(ADR_PHY_REG_11_TX_DES)) & 0x001f0000 ) >> 16)
+#define GET_RG_TX_DES_TYPE (((REG32(ADR_PHY_REG_11_TX_DES)) & 0x1f000000 ) >> 24)
+#define GET_RG_TX_DES_L_LEN_UP_COMB (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x00000001 ) >> 0)
+#define GET_RG_TX_DES_TYPE_COMB (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x00000010 ) >> 4)
+#define GET_RG_TX_DES_RATE_COMB (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x00000100 ) >> 8)
+#define GET_RG_TX_DES_MODE_COMB (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x00001000 ) >> 12)
+#define GET_RG_TX_DES_PWRLVL (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x001f0000 ) >> 16)
+#define GET_RG_TX_DES_SRVC_LO (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x1f000000 ) >> 24)
+#define GET_RG_RX_DES_RATE (((REG32(ADR_PHY_REG_13_RX_DES)) & 0x0000003f ) >> 0)
+#define GET_RG_RX_DES_MODE (((REG32(ADR_PHY_REG_13_RX_DES)) & 0x00003f00 ) >> 8)
+#define GET_RG_RX_DES_LEN_LO (((REG32(ADR_PHY_REG_13_RX_DES)) & 0x003f0000 ) >> 16)
+#define GET_RG_RX_DES_LEN_UP (((REG32(ADR_PHY_REG_13_RX_DES)) & 0x3f000000 ) >> 24)
+#define GET_RG_RX_DES_SRVC_UP (((REG32(ADR_PHY_REG_14_RX_DES)) & 0x0000003f ) >> 0)
+#define GET_RG_RX_DES_L_LEN_LO (((REG32(ADR_PHY_REG_14_RX_DES)) & 0x00003f00 ) >> 8)
+#define GET_RG_RX_DES_L_LEN_UP (((REG32(ADR_PHY_REG_14_RX_DES)) & 0x003f0000 ) >> 16)
+#define GET_RG_RX_DES_TYPE (((REG32(ADR_PHY_REG_14_RX_DES)) & 0x3f000000 ) >> 24)
+#define GET_RG_RX_DES_L_LEN_UP_COMB (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x00000001 ) >> 0)
+#define GET_RG_RX_DES_TYPE_COMB (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x00000010 ) >> 4)
+#define GET_RG_RX_DES_RATE_COMB (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x00000100 ) >> 8)
+#define GET_RG_RX_DES_MODE_COMB (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x00001000 ) >> 12)
+#define GET_RG_RX_DES_SNR (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x000f0000 ) >> 16)
+#define GET_RG_RX_DES_RCPI (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x00f00000 ) >> 20)
+#define GET_RG_RX_DES_SRVC_LO (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x3f000000 ) >> 24)
+#define GET_RO_TX_DES_EXCP_RATE_CNT (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x000000ff ) >> 0)
+#define GET_RO_TX_DES_EXCP_CH_BW_CNT (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x0000ff00 ) >> 8)
+#define GET_RO_TX_DES_EXCP_MODE_CNT (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x00ff0000 ) >> 16)
+#define GET_RG_TX_DES_EXCP_RATE_DEFAULT (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x07000000 ) >> 24)
+#define GET_RG_TX_DES_EXCP_MODE_DEFAULT (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x70000000 ) >> 28)
+#define GET_RG_TX_DES_EXCP_CLR (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x80000000 ) >> 31)
+#define GET_RG_TX_DES_ACK_WIDTH (((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0x00000001 ) >> 0)
+#define GET_RG_TX_DES_ACK_PRD (((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0x0000000e ) >> 1)
+#define GET_RG_RX_DES_SNR_GN (((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0x003f0000 ) >> 16)
+#define GET_RG_RX_DES_RCPI_GN (((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0x3f000000 ) >> 24)
+#define GET_RG_TST_TBUS_SEL (((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x0000000f ) >> 0)
+#define GET_RG_RSSI_OFFSET (((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x00ff0000 ) >> 16)
+#define GET_RG_RSSI_INV (((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x01000000 ) >> 24)
+#define GET_RG_TST_ADC_ON (((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x40000000 ) >> 30)
+#define GET_RG_TST_EXT_GAIN (((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x80000000 ) >> 31)
+#define GET_RG_DAC_Q_SET (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x000003ff ) >> 0)
+#define GET_RG_DAC_I_SET (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x003ff000 ) >> 12)
+#define GET_RG_DAC_EN_MAN (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x10000000 ) >> 28)
+#define GET_RG_IQC_FFT_EN (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x20000000 ) >> 29)
+#define GET_RG_DAC_MAN_Q_EN (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x40000000 ) >> 30)
+#define GET_RG_DAC_MAN_I_EN (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x80000000 ) >> 31)
+#define GET_RO_MRX_EN_CNT (((REG32(ADR_PHY_REG_20_MRX_CNT)) & 0x0000ffff ) >> 0)
+#define GET_RG_MRX_EN_CNT_RST_N (((REG32(ADR_PHY_REG_20_MRX_CNT)) & 0x80000000 ) >> 31)
+#define GET_RG_PA_RISE_TIME (((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0x000000ff ) >> 0)
+#define GET_RG_RFTX_RISE_TIME (((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0x0000ff00 ) >> 8)
+#define GET_RG_DAC_RISE_TIME (((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0x00ff0000 ) >> 16)
+#define GET_RG_SW_RISE_TIME (((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0xff000000 ) >> 24)
+#define GET_RG_PA_FALL_TIME (((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0x000000ff ) >> 0)
+#define GET_RG_RFTX_FALL_TIME (((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0x0000ff00 ) >> 8)
+#define GET_RG_DAC_FALL_TIME (((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0x00ff0000 ) >> 16)
+#define GET_RG_SW_FALL_TIME (((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0xff000000 ) >> 24)
+#define GET_RG_ANT_SW_0 (((REG32(ADR_PHY_REG_23_ANT)) & 0x00000007 ) >> 0)
+#define GET_RG_ANT_SW_1 (((REG32(ADR_PHY_REG_23_ANT)) & 0x00000038 ) >> 3)
+#define GET_RG_MTX_LEN_LOWER_TH_0 (((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0x00001fff ) >> 0)
+#define GET_RG_MTX_LEN_UPPER_TH_0 (((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0x1fff0000 ) >> 16)
+#define GET_RG_MTX_LEN_CNT_EN_0 (((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0x80000000 ) >> 31)
+#define GET_RG_MTX_LEN_LOWER_TH_1 (((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0x00001fff ) >> 0)
+#define GET_RG_MTX_LEN_UPPER_TH_1 (((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0x1fff0000 ) >> 16)
+#define GET_RG_MTX_LEN_CNT_EN_1 (((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0x80000000 ) >> 31)
+#define GET_RG_MRX_LEN_LOWER_TH_0 (((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0x00001fff ) >> 0)
+#define GET_RG_MRX_LEN_UPPER_TH_0 (((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0x1fff0000 ) >> 16)
+#define GET_RG_MRX_LEN_CNT_EN_0 (((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0x80000000 ) >> 31)
+#define GET_RG_MRX_LEN_LOWER_TH_1 (((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0x00001fff ) >> 0)
+#define GET_RG_MRX_LEN_UPPER_TH_1 (((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0x1fff0000 ) >> 16)
+#define GET_RG_MRX_LEN_CNT_EN_1 (((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0x80000000 ) >> 31)
+#define GET_RO_MTX_LEN_CNT_1 (((REG32(ADR_PHY_READ_REG_04)) & 0x0000ffff ) >> 0)
+#define GET_RO_MTX_LEN_CNT_0 (((REG32(ADR_PHY_READ_REG_04)) & 0xffff0000 ) >> 16)
+#define GET_RO_MRX_LEN_CNT_1 (((REG32(ADR_PHY_READ_REG_05)) & 0x0000ffff ) >> 0)
+#define GET_RO_MRX_LEN_CNT_0 (((REG32(ADR_PHY_READ_REG_05)) & 0xffff0000 ) >> 16)
+#define GET_RG_MODE_REG_IN_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x0000ffff ) >> 0)
+#define GET_RG_PARALLEL_DR_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x00100000 ) >> 20)
+#define GET_RG_MBRUN_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x01000000 ) >> 24)
+#define GET_RG_SHIFT_DR_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x10000000 ) >> 28)
+#define GET_RG_MODE_REG_SI_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x20000000 ) >> 29)
+#define GET_RG_SIMULATION_MODE_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x40000000 ) >> 30)
+#define GET_RG_DBIST_MODE_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x80000000 ) >> 31)
+#define GET_RO_MODE_REG_OUT_16 (((REG32(ADR_PHY_READ_REG_06_BIST)) & 0x0000ffff ) >> 0)
+#define GET_RO_MODE_REG_SO_16 (((REG32(ADR_PHY_READ_REG_06_BIST)) & 0x01000000 ) >> 24)
+#define GET_RO_MONITOR_BUS_16 (((REG32(ADR_PHY_READ_REG_07_BIST)) & 0x0007ffff ) >> 0)
+#define GET_RG_MRX_TYPE_1 (((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0x000000ff ) >> 0)
+#define GET_RG_MRX_TYPE_0 (((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0x0000ff00 ) >> 8)
+#define GET_RG_MTX_TYPE_1 (((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0x00ff0000 ) >> 16)
+#define GET_RG_MTX_TYPE_0 (((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0xff000000 ) >> 24)
+#define GET_RO_MTX_TYPE_CNT_1 (((REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) & 0x0000ffff ) >> 0)
+#define GET_RO_MTX_TYPE_CNT_0 (((REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) & 0xffff0000 ) >> 16)
+#define GET_RO_MRX_TYPE_CNT_1 (((REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) & 0x0000ffff ) >> 0)
+#define GET_RO_MRX_TYPE_CNT_0 (((REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) & 0xffff0000 ) >> 16)
+#define GET_RG_HB_COEF0 (((REG32(ADR_PHY_REG_30_TX_UP_FIL)) & 0x00000fff ) >> 0)
+#define GET_RG_HB_COEF1 (((REG32(ADR_PHY_REG_30_TX_UP_FIL)) & 0x0fff0000 ) >> 16)
+#define GET_RG_HB_COEF2 (((REG32(ADR_PHY_REG_31_TX_UP_FIL)) & 0x00000fff ) >> 0)
+#define GET_RG_HB_COEF3 (((REG32(ADR_PHY_REG_31_TX_UP_FIL)) & 0x0fff0000 ) >> 16)
+#define GET_RG_HB_COEF4 (((REG32(ADR_PHY_REG_32_TX_UP_FIL)) & 0x00000fff ) >> 0)
+#define GET_RO_TBUS_O (((REG32(ADR_PHY_READ_TBUS)) & 0x000fffff ) >> 0)
+#define GET_RG_LPF4_00 (((REG32(ADR_TX_11B_FIL_COEF_00)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_01 (((REG32(ADR_TX_11B_FIL_COEF_01)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_02 (((REG32(ADR_TX_11B_FIL_COEF_02)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_03 (((REG32(ADR_TX_11B_FIL_COEF_03)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_04 (((REG32(ADR_TX_11B_FIL_COEF_04)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_05 (((REG32(ADR_TX_11B_FIL_COEF_05)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_06 (((REG32(ADR_TX_11B_FIL_COEF_06)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_07 (((REG32(ADR_TX_11B_FIL_COEF_07)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_08 (((REG32(ADR_TX_11B_FIL_COEF_08)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_09 (((REG32(ADR_TX_11B_FIL_COEF_09)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_10 (((REG32(ADR_TX_11B_FIL_COEF_10)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_11 (((REG32(ADR_TX_11B_FIL_COEF_11)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_12 (((REG32(ADR_TX_11B_FIL_COEF_12)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_13 (((REG32(ADR_TX_11B_FIL_COEF_13)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_14 (((REG32(ADR_TX_11B_FIL_COEF_14)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_15 (((REG32(ADR_TX_11B_FIL_COEF_15)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_16 (((REG32(ADR_TX_11B_FIL_COEF_16)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_17 (((REG32(ADR_TX_11B_FIL_COEF_17)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_18 (((REG32(ADR_TX_11B_FIL_COEF_18)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_19 (((REG32(ADR_TX_11B_FIL_COEF_19)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_20 (((REG32(ADR_TX_11B_FIL_COEF_20)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_21 (((REG32(ADR_TX_11B_FIL_COEF_21)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_22 (((REG32(ADR_TX_11B_FIL_COEF_22)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_23 (((REG32(ADR_TX_11B_FIL_COEF_23)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_24 (((REG32(ADR_TX_11B_FIL_COEF_24)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_25 (((REG32(ADR_TX_11B_FIL_COEF_25)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_26 (((REG32(ADR_TX_11B_FIL_COEF_26)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_27 (((REG32(ADR_TX_11B_FIL_COEF_27)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_28 (((REG32(ADR_TX_11B_FIL_COEF_28)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_29 (((REG32(ADR_TX_11B_FIL_COEF_29)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_30 (((REG32(ADR_TX_11B_FIL_COEF_30)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_31 (((REG32(ADR_TX_11B_FIL_COEF_31)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_32 (((REG32(ADR_TX_11B_FIL_COEF_32)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_33 (((REG32(ADR_TX_11B_FIL_COEF_33)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_34 (((REG32(ADR_TX_11B_FIL_COEF_34)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_35 (((REG32(ADR_TX_11B_FIL_COEF_35)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_36 (((REG32(ADR_TX_11B_FIL_COEF_36)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_37 (((REG32(ADR_TX_11B_FIL_COEF_37)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_38 (((REG32(ADR_TX_11B_FIL_COEF_38)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_39 (((REG32(ADR_TX_11B_FIL_COEF_39)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_40 (((REG32(ADR_TX_11B_FIL_COEF_40)) & 0x00001fff ) >> 0)
+#define GET_RG_BP_SMB (((REG32(ADR_TX_11B_PLCP)) & 0x00002000 ) >> 13)
+#define GET_RG_EN_SRVC (((REG32(ADR_TX_11B_PLCP)) & 0x00004000 ) >> 14)
+#define GET_RG_DES_SPD (((REG32(ADR_TX_11B_PLCP)) & 0x00030000 ) >> 16)
+#define GET_RG_BB_11B_RISE_TIME (((REG32(ADR_TX_11B_RAMP)) & 0x000000ff ) >> 0)
+#define GET_RG_BB_11B_FALL_TIME (((REG32(ADR_TX_11B_RAMP)) & 0x0000ff00 ) >> 8)
+#define GET_RG_WR_TX_EN_CNT_RST_N (((REG32(ADR_TX_11B_EN_CNT_RST_N)) & 0x00000001 ) >> 0)
+#define GET_RO_TX_EN_CNT (((REG32(ADR_TX_11B_EN_CNT)) & 0x0000ffff ) >> 0)
+#define GET_RO_TX_CNT (((REG32(ADR_TX_11B_PKT_GEN_CNT)) & 0xffffffff ) >> 0)
+#define GET_RG_POS_DES_11B_L_EXT (((REG32(ADR_RX_11B_DES_DLY)) & 0x0000000f ) >> 0)
+#define GET_RG_PRE_DES_11B_DLY (((REG32(ADR_RX_11B_DES_DLY)) & 0x000000f0 ) >> 4)
+#define GET_RG_CNT_CCA_LMT (((REG32(ADR_RX_11B_CCA_0)) & 0x000f0000 ) >> 16)
+#define GET_RG_BYPASS_DESCRAMBLER (((REG32(ADR_RX_11B_CCA_0)) & 0x20000000 ) >> 29)
+#define GET_RG_BYPASS_AGC (((REG32(ADR_RX_11B_CCA_0)) & 0x80000000 ) >> 31)
+#define GET_RG_CCA_BIT_CNT_LMT_RX (((REG32(ADR_RX_11B_CCA_1)) & 0x000000f0 ) >> 4)
+#define GET_RG_CCA_SCALE_BF (((REG32(ADR_RX_11B_CCA_1)) & 0x007f0000 ) >> 16)
+#define GET_RG_PEAK_IDX_CNT_SEL (((REG32(ADR_RX_11B_CCA_1)) & 0x30000000 ) >> 28)
+#define GET_RG_TR_KI_T2 (((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0x00000007 ) >> 0)
+#define GET_RG_TR_KP_T2 (((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0x00000070 ) >> 4)
+#define GET_RG_TR_KI_T1 (((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0x00000700 ) >> 8)
+#define GET_RG_TR_KP_T1 (((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0x00007000 ) >> 12)
+#define GET_RG_CR_KI_T1 (((REG32(ADR_RX_11B_TR_KP_KI_1)) & 0x00070000 ) >> 16)
+#define GET_RG_CR_KP_T1 (((REG32(ADR_RX_11B_TR_KP_KI_1)) & 0x00700000 ) >> 20)
+#define GET_RG_CHIP_CNT_SLICER (((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0x0000001f ) >> 0)
+#define GET_RG_CE_T4_CNT_LMT (((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0x0000ff00 ) >> 8)
+#define GET_RG_CE_T3_CNT_LMT (((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0x00ff0000 ) >> 16)
+#define GET_RG_CE_T2_CNT_LMT (((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0xff000000 ) >> 24)
+#define GET_RG_CE_MU_T1 (((REG32(ADR_RX_11B_CE_MU_0)) & 0x00000007 ) >> 0)
+#define GET_RG_CE_DLY_SEL (((REG32(ADR_RX_11B_CE_MU_0)) & 0x003f0000 ) >> 16)
+#define GET_RG_CE_MU_T8 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00000007 ) >> 0)
+#define GET_RG_CE_MU_T7 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00000070 ) >> 4)
+#define GET_RG_CE_MU_T6 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00000700 ) >> 8)
+#define GET_RG_CE_MU_T5 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00007000 ) >> 12)
+#define GET_RG_CE_MU_T4 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00070000 ) >> 16)
+#define GET_RG_CE_MU_T3 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00700000 ) >> 20)
+#define GET_RG_CE_MU_T2 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x07000000 ) >> 24)
+#define GET_RG_EQ_MU_FB_T2 (((REG32(ADR_RX_11B_EQ_MU_0)) & 0x0000000f ) >> 0)
+#define GET_RG_EQ_MU_FF_T2 (((REG32(ADR_RX_11B_EQ_MU_0)) & 0x000000f0 ) >> 4)
+#define GET_RG_EQ_MU_FB_T1 (((REG32(ADR_RX_11B_EQ_MU_0)) & 0x000f0000 ) >> 16)
+#define GET_RG_EQ_MU_FF_T1 (((REG32(ADR_RX_11B_EQ_MU_0)) & 0x00f00000 ) >> 20)
+#define GET_RG_EQ_MU_FB_T4 (((REG32(ADR_RX_11B_EQ_MU_1)) & 0x0000000f ) >> 0)
+#define GET_RG_EQ_MU_FF_T4 (((REG32(ADR_RX_11B_EQ_MU_1)) & 0x000000f0 ) >> 4)
+#define GET_RG_EQ_MU_FB_T3 (((REG32(ADR_RX_11B_EQ_MU_1)) & 0x000f0000 ) >> 16)
+#define GET_RG_EQ_MU_FF_T3 (((REG32(ADR_RX_11B_EQ_MU_1)) & 0x00f00000 ) >> 20)
+#define GET_RG_EQ_KI_T2 (((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0x00000700 ) >> 8)
+#define GET_RG_EQ_KP_T2 (((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0x00007000 ) >> 12)
+#define GET_RG_EQ_KI_T1 (((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0x00070000 ) >> 16)
+#define GET_RG_EQ_KP_T1 (((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0x00700000 ) >> 20)
+#define GET_RG_TR_LPF_RATE (((REG32(ADR_RX_11B_LPF_RATE)) & 0x003fffff ) >> 0)
+#define GET_RG_CE_BIT_CNT_LMT (((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x0000007f ) >> 0)
+#define GET_RG_CE_CH_MAIN_SET (((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x00000080 ) >> 7)
+#define GET_RG_TC_BIT_CNT_LMT (((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x00007f00 ) >> 8)
+#define GET_RG_CR_BIT_CNT_LMT (((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x007f0000 ) >> 16)
+#define GET_RG_TR_BIT_CNT_LMT (((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x7f000000 ) >> 24)
+#define GET_RG_EQ_MAIN_TAP_MAN (((REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) & 0x00000001 ) >> 0)
+#define GET_RG_EQ_MAIN_TAP_COEF (((REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) & 0x07ff0000 ) >> 16)
+#define GET_RG_PWRON_DLY_TH_11B (((REG32(ADR_RX_11B_SEARCH_CNT_TH)) & 0x000000ff ) >> 0)
+#define GET_RG_SFD_BIT_CNT_LMT (((REG32(ADR_RX_11B_SEARCH_CNT_TH)) & 0x00ff0000 ) >> 16)
+#define GET_RG_CCA_PWR_TH_RX (((REG32(ADR_RX_11B_CCA_CONTROL)) & 0x00007fff ) >> 0)
+#define GET_RG_CCA_PWR_CNT_TH (((REG32(ADR_RX_11B_CCA_CONTROL)) & 0x001f0000 ) >> 16)
+#define GET_B_FREQ_OS (((REG32(ADR_RX_11B_FREQUENCY_OFFSET)) & 0x000007ff ) >> 0)
+#define GET_B_SNR (((REG32(ADR_RX_11B_SNR_RSSI)) & 0x0000007f ) >> 0)
+#define GET_B_RCPI (((REG32(ADR_RX_11B_SNR_RSSI)) & 0x007f0000 ) >> 16)
+#define GET_CRC_CNT (((REG32(ADR_RX_11B_SFD_CRC_CNT)) & 0x0000ffff ) >> 0)
+#define GET_SFD_CNT (((REG32(ADR_RX_11B_SFD_CRC_CNT)) & 0xffff0000 ) >> 16)
+#define GET_B_PACKET_ERR_CNT (((REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) & 0x0000ffff ) >> 0)
+#define GET_PACKET_ERR (((REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) & 0x00010000 ) >> 16)
+#define GET_B_PACKET_CNT (((REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) & 0x0000ffff ) >> 0)
+#define GET_B_CCA_CNT (((REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) & 0xffff0000 ) >> 16)
+#define GET_B_LENGTH_FIELD (((REG32(ADR_RX_11B_SFD_FILED_0)) & 0x0000ffff ) >> 0)
+#define GET_SFD_FIELD (((REG32(ADR_RX_11B_SFD_FILED_0)) & 0xffff0000 ) >> 16)
+#define GET_SIGNAL_FIELD (((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0x000000ff ) >> 0)
+#define GET_B_SERVICE_FIELD (((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0x0000ff00 ) >> 8)
+#define GET_CRC_CORRECT (((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0x00010000 ) >> 16)
+#define GET_DEBUG_SEL (((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0x0000000f ) >> 0)
+#define GET_RG_PACKET_STAT_EN_11B (((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0x00100000 ) >> 20)
+#define GET_RG_BIT_REVERSE (((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0x00200000 ) >> 21)
+#define GET_RX_PHY_11B_SOFT_RST_N (((REG32(ADR_RX_11B_SOFT_RST)) & 0x00000001 ) >> 0)
+#define GET_RG_CE_BYPASS_TAP (((REG32(ADR_RX_11B_SOFT_RST)) & 0x000000f0 ) >> 4)
+#define GET_RG_EQ_BYPASS_FBW_TAP (((REG32(ADR_RX_11B_SOFT_RST)) & 0x00000f00 ) >> 8)
+#define GET_RG_BB_11GN_RISE_TIME (((REG32(ADR_TX_11GN_RAMP)) & 0x000000ff ) >> 0)
+#define GET_RG_BB_11GN_FALL_TIME (((REG32(ADR_TX_11GN_RAMP)) & 0x0000ff00 ) >> 8)
+#define GET_RG_HTCARR52_FFT_SCALE (((REG32(ADR_TX_11GN_PLCP)) & 0x000003ff ) >> 0)
+#define GET_RG_HTCARR56_FFT_SCALE (((REG32(ADR_TX_11GN_PLCP)) & 0x003ff000 ) >> 12)
+#define GET_RG_PACKET_STAT_EN (((REG32(ADR_TX_11GN_PLCP)) & 0x00800000 ) >> 23)
+#define GET_RG_SMB_DEF (((REG32(ADR_TX_11GN_PLCP)) & 0x7f000000 ) >> 24)
+#define GET_RG_CONTINUOUS_DATA_11GN (((REG32(ADR_TX_11GN_PLCP)) & 0x80000000 ) >> 31)
+#define GET_RO_TX_CNT_R (((REG32(ADR_TX_11GN_PKT_GEN_CNT)) & 0xffffffff ) >> 0)
+#define GET_RO_PACKET_ERR_CNT (((REG32(ADR_TX_11GN_PLCP_CRC_ERR_CNT)) & 0x0000ffff ) >> 0)
+#define GET_RG_POS_DES_11GN_L_EXT (((REG32(ADR_RX_11GN_DES_DLY)) & 0x0000000f ) >> 0)
+#define GET_RG_PRE_DES_11GN_DLY (((REG32(ADR_RX_11GN_DES_DLY)) & 0x000000f0 ) >> 4)
+#define GET_RG_TR_LPF_KI_G_T1 (((REG32(ADR_RX_11GN_TR_0)) & 0x0000000f ) >> 0)
+#define GET_RG_TR_LPF_KP_G_T1 (((REG32(ADR_RX_11GN_TR_0)) & 0x000000f0 ) >> 4)
+#define GET_RG_TR_CNT_T1 (((REG32(ADR_RX_11GN_TR_0)) & 0x0000ff00 ) >> 8)
+#define GET_RG_TR_LPF_KI_G_T0 (((REG32(ADR_RX_11GN_TR_0)) & 0x000f0000 ) >> 16)
+#define GET_RG_TR_LPF_KP_G_T0 (((REG32(ADR_RX_11GN_TR_0)) & 0x00f00000 ) >> 20)
+#define GET_RG_TR_CNT_T0 (((REG32(ADR_RX_11GN_TR_0)) & 0xff000000 ) >> 24)
+#define GET_RG_TR_LPF_KI_G_T2 (((REG32(ADR_RX_11GN_TR_1)) & 0x0000000f ) >> 0)
+#define GET_RG_TR_LPF_KP_G_T2 (((REG32(ADR_RX_11GN_TR_1)) & 0x000000f0 ) >> 4)
+#define GET_RG_TR_CNT_T2 (((REG32(ADR_RX_11GN_TR_1)) & 0x0000ff00 ) >> 8)
+#define GET_RG_TR_LPF_KI_G (((REG32(ADR_RX_11GN_TR_2)) & 0x0000000f ) >> 0)
+#define GET_RG_TR_LPF_KP_G (((REG32(ADR_RX_11GN_TR_2)) & 0x000000f0 ) >> 4)
+#define GET_RG_TR_LPF_RATE_G (((REG32(ADR_RX_11GN_TR_2)) & 0x3fffff00 ) >> 8)
+#define GET_RG_CR_LPF_KI_G (((REG32(ADR_RX_11GN_CCA_0)) & 0x00000007 ) >> 0)
+#define GET_RG_SYM_BOUND_CNT (((REG32(ADR_RX_11GN_CCA_0)) & 0x00007f00 ) >> 8)
+#define GET_RG_XSCOR32_RATIO (((REG32(ADR_RX_11GN_CCA_0)) & 0x007f0000 ) >> 16)
+#define GET_RG_ATCOR64_CNT_LMT (((REG32(ADR_RX_11GN_CCA_0)) & 0x7f000000 ) >> 24)
+#define GET_RG_ATCOR16_CNT_LMT2 (((REG32(ADR_RX_11GN_CCA_1)) & 0x00007f00 ) >> 8)
+#define GET_RG_ATCOR16_CNT_LMT1 (((REG32(ADR_RX_11GN_CCA_1)) & 0x007f0000 ) >> 16)
+#define GET_RG_ATCOR16_RATIO_SB (((REG32(ADR_RX_11GN_CCA_1)) & 0x7f000000 ) >> 24)
+#define GET_RG_XSCOR64_CNT_LMT2 (((REG32(ADR_RX_11GN_CCA_2)) & 0x007f0000 ) >> 16)
+#define GET_RG_XSCOR64_CNT_LMT1 (((REG32(ADR_RX_11GN_CCA_2)) & 0x7f000000 ) >> 24)
+#define GET_RG_RX_FFT_SCALE (((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0x000003ff ) >> 0)
+#define GET_RG_VITERBI_AB_SWAP (((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0x00010000 ) >> 16)
+#define GET_RG_ATCOR16_CNT_TH (((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0x0f000000 ) >> 24)
+#define GET_RG_NORMSQUARE_LOW_SNR_7 (((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0x000000ff ) >> 0)
+#define GET_RG_NORMSQUARE_LOW_SNR_6 (((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0x0000ff00 ) >> 8)
+#define GET_RG_NORMSQUARE_LOW_SNR_5 (((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0x00ff0000 ) >> 16)
+#define GET_RG_NORMSQUARE_LOW_SNR_4 (((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0xff000000 ) >> 24)
+#define GET_RG_NORMSQUARE_LOW_SNR_8 (((REG32(ADR_RX_11GN_SOFT_DEMAP_1)) & 0xff000000 ) >> 24)
+#define GET_RG_NORMSQUARE_SNR_3 (((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0x000000ff ) >> 0)
+#define GET_RG_NORMSQUARE_SNR_2 (((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0x0000ff00 ) >> 8)
+#define GET_RG_NORMSQUARE_SNR_1 (((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0x00ff0000 ) >> 16)
+#define GET_RG_NORMSQUARE_SNR_0 (((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0xff000000 ) >> 24)
+#define GET_RG_NORMSQUARE_SNR_7 (((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0x000000ff ) >> 0)
+#define GET_RG_NORMSQUARE_SNR_6 (((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0x0000ff00 ) >> 8)
+#define GET_RG_NORMSQUARE_SNR_5 (((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0x00ff0000 ) >> 16)
+#define GET_RG_NORMSQUARE_SNR_4 (((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0xff000000 ) >> 24)
+#define GET_RG_NORMSQUARE_SNR_8 (((REG32(ADR_RX_11GN_SOFT_DEMAP_4)) & 0xff000000 ) >> 24)
+#define GET_RG_SNR_TH_64QAM (((REG32(ADR_RX_11GN_SOFT_DEMAP_5)) & 0x0000007f ) >> 0)
+#define GET_RG_SNR_TH_16QAM (((REG32(ADR_RX_11GN_SOFT_DEMAP_5)) & 0x00007f00 ) >> 8)
+#define GET_RG_ATCOR16_CNT_PLUS_LMT2 (((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0x0000007f ) >> 0)
+#define GET_RG_ATCOR16_CNT_PLUS_LMT1 (((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0x00007f00 ) >> 8)
+#define GET_RG_SYM_BOUND_METHOD (((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0x00030000 ) >> 16)
+#define GET_RG_PWRON_DLY_TH_11GN (((REG32(ADR_RX_11GN_SYM_BOUND_1)) & 0x000000ff ) >> 0)
+#define GET_RG_SB_START_CNT (((REG32(ADR_RX_11GN_SYM_BOUND_1)) & 0x00007f00 ) >> 8)
+#define GET_RG_POW16_CNT_TH (((REG32(ADR_RX_11GN_CCA_PWR)) & 0x000000f0 ) >> 4)
+#define GET_RG_POW16_SHORT_CNT_LMT (((REG32(ADR_RX_11GN_CCA_PWR)) & 0x00000700 ) >> 8)
+#define GET_RG_POW16_TH_L (((REG32(ADR_RX_11GN_CCA_PWR)) & 0x7f000000 ) >> 24)
+#define GET_RG_XSCOR16_SHORT_CNT_LMT (((REG32(ADR_RX_11GN_CCA_CNT)) & 0x00000007 ) >> 0)
+#define GET_RG_XSCOR16_RATIO (((REG32(ADR_RX_11GN_CCA_CNT)) & 0x00007f00 ) >> 8)
+#define GET_RG_ATCOR16_SHORT_CNT_LMT (((REG32(ADR_RX_11GN_CCA_CNT)) & 0x00070000 ) >> 16)
+#define GET_RG_ATCOR16_RATIO_CCD (((REG32(ADR_RX_11GN_CCA_CNT)) & 0x7f000000 ) >> 24)
+#define GET_RG_ATCOR64_ACC_LMT (((REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) & 0x0000007f ) >> 0)
+#define GET_RG_ATCOR16_SHORT_CNT_LMT2 (((REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) & 0x00070000 ) >> 16)
+#define GET_RG_VITERBI_TB_BITS (((REG32(ADR_RX_11GN_VTB_TB)) & 0xff000000 ) >> 24)
+#define GET_RG_CR_CNT_UPDATE (((REG32(ADR_RX_11GN_ERR_UPDATE)) & 0x000000ff ) >> 0)
+#define GET_RG_TR_CNT_UPDATE (((REG32(ADR_RX_11GN_ERR_UPDATE)) & 0x00ff0000 ) >> 16)
+#define GET_RG_BYPASS_CPE_MA (((REG32(ADR_RX_11GN_SHORT_GI)) & 0x00000010 ) >> 4)
+#define GET_RG_PILOT_BNDRY_SHIFT (((REG32(ADR_RX_11GN_SHORT_GI)) & 0x00000700 ) >> 8)
+#define GET_RG_EQ_SHORT_GI_SHIFT (((REG32(ADR_RX_11GN_SHORT_GI)) & 0x00007000 ) >> 12)
+#define GET_RG_FFT_WDW_SHORT_SHIFT (((REG32(ADR_RX_11GN_SHORT_GI)) & 0x00070000 ) >> 16)
+#define GET_RG_CHSMTH_COEF (((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0x00030000 ) >> 16)
+#define GET_RG_CHSMTH_EN (((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0x00040000 ) >> 18)
+#define GET_RG_CHEST_DD_FACTOR (((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0x07000000 ) >> 24)
+#define GET_RG_CH_UPDATE (((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0x80000000 ) >> 31)
+#define GET_RG_FMT_DET_MM_TH (((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0x000000ff ) >> 0)
+#define GET_RG_FMT_DET_GF_TH (((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0x0000ff00 ) >> 8)
+#define GET_RG_DO_NOT_CHECK_L_RATE (((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0x02000000 ) >> 25)
+#define GET_RG_FMT_DET_LENGTH_TH (((REG32(ADR_RX_11GN_PKT_FORMAT_1)) & 0x0000ffff ) >> 0)
+#define GET_RG_L_LENGTH_MAX (((REG32(ADR_RX_11GN_PKT_FORMAT_1)) & 0xffff0000 ) >> 16)
+#define GET_RG_TX_TIME_EXT (((REG32(ADR_RX_11GN_TX_TIME)) & 0x000000ff ) >> 0)
+#define GET_RG_MAC_DES_SPACE (((REG32(ADR_RX_11GN_TX_TIME)) & 0x00f00000 ) >> 20)
+#define GET_RG_TR_LPF_STBC_GF_KI_G (((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0x0000000f ) >> 0)
+#define GET_RG_TR_LPF_STBC_GF_KP_G (((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0x000000f0 ) >> 4)
+#define GET_RG_TR_LPF_STBC_MF_KI_G (((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0x00000f00 ) >> 8)
+#define GET_RG_TR_LPF_STBC_MF_KP_G (((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0x0000f000 ) >> 12)
+#define GET_RG_MODE_REG_IN_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x0001ffff ) >> 0)
+#define GET_RG_PARALLEL_DR_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x00100000 ) >> 20)
+#define GET_RG_MBRUN_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x01000000 ) >> 24)
+#define GET_RG_SHIFT_DR_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x10000000 ) >> 28)
+#define GET_RG_MODE_REG_SI_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x20000000 ) >> 29)
+#define GET_RG_SIMULATION_MODE_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x40000000 ) >> 30)
+#define GET_RG_DBIST_MODE_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x80000000 ) >> 31)
+#define GET_RG_MODE_REG_IN_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x0000ffff ) >> 0)
+#define GET_RG_PARALLEL_DR_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x00100000 ) >> 20)
+#define GET_RG_MBRUN_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x01000000 ) >> 24)
+#define GET_RG_SHIFT_DR_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x10000000 ) >> 28)
+#define GET_RG_MODE_REG_SI_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x20000000 ) >> 29)
+#define GET_RG_SIMULATION_MODE_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x40000000 ) >> 30)
+#define GET_RG_DBIST_MODE_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x80000000 ) >> 31)
+#define GET_RO_MODE_REG_OUT_80 (((REG32(ADR_RX_11GN_BIST_2)) & 0x0001ffff ) >> 0)
+#define GET_RO_MODE_REG_SO_80 (((REG32(ADR_RX_11GN_BIST_2)) & 0x01000000 ) >> 24)
+#define GET_RO_MONITOR_BUS_80 (((REG32(ADR_RX_11GN_BIST_3)) & 0x003fffff ) >> 0)
+#define GET_RO_MODE_REG_OUT_64 (((REG32(ADR_RX_11GN_BIST_4)) & 0x0000ffff ) >> 0)
+#define GET_RO_MODE_REG_SO_64 (((REG32(ADR_RX_11GN_BIST_4)) & 0x01000000 ) >> 24)
+#define GET_RO_MONITOR_BUS_64 (((REG32(ADR_RX_11GN_BIST_5)) & 0x0007ffff ) >> 0)
+#define GET_RO_SPECTRUM_DATA (((REG32(ADR_RX_11GN_SPECTRUM_ANALYZER)) & 0xffffffff ) >> 0)
+#define GET_GN_SNR (((REG32(ADR_RX_11GN_READ_0)) & 0x0000007f ) >> 0)
+#define GET_GN_NOISE_PWR (((REG32(ADR_RX_11GN_READ_0)) & 0x00007f00 ) >> 8)
+#define GET_GN_RCPI (((REG32(ADR_RX_11GN_READ_0)) & 0x007f0000 ) >> 16)
+#define GET_GN_SIGNAL_PWR (((REG32(ADR_RX_11GN_READ_0)) & 0x7f000000 ) >> 24)
+#define GET_RO_FREQ_OS_LTS (((REG32(ADR_RX_11GN_FREQ_OFFSET)) & 0x00007fff ) >> 0)
+#define GET_CSTATE (((REG32(ADR_RX_11GN_FREQ_OFFSET)) & 0x000f0000 ) >> 16)
+#define GET_SIGNAL_FIELD0 (((REG32(ADR_RX_11GN_SIGNAL_FIELD_0)) & 0x00ffffff ) >> 0)
+#define GET_SIGNAL_FIELD1 (((REG32(ADR_RX_11GN_SIGNAL_FIELD_1)) & 0x00ffffff ) >> 0)
+#define GET_GN_PACKET_ERR_CNT (((REG32(ADR_RX_11GN_PKT_ERR_CNT)) & 0x0000ffff ) >> 0)
+#define GET_GN_PACKET_CNT (((REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) & 0x0000ffff ) >> 0)
+#define GET_GN_CCA_CNT (((REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) & 0xffff0000 ) >> 16)
+#define GET_GN_LENGTH_FIELD (((REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) & 0x0000ffff ) >> 0)
+#define GET_GN_SERVICE_FIELD (((REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) & 0xffff0000 ) >> 16)
+#define GET_RO_HT_MCS_40M (((REG32(ADR_RX_11GN_RATE)) & 0x0000007f ) >> 0)
+#define GET_RO_L_RATE_40M (((REG32(ADR_RX_11GN_RATE)) & 0x00003f00 ) >> 8)
+#define GET_RG_DAGC_CNT_TH (((REG32(ADR_RX_11GN_STAT_EN)) & 0x00000003 ) >> 0)
+#define GET_RG_PACKET_STAT_EN_11GN (((REG32(ADR_RX_11GN_STAT_EN)) & 0x00100000 ) >> 20)
+#define GET_RX_PHY_11GN_SOFT_RST_N (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000001 ) >> 0)
+#define GET_RG_RIFS_EN (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000002 ) >> 1)
+#define GET_RG_STBC_EN (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000004 ) >> 2)
+#define GET_RG_COR_SEL (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000008 ) >> 3)
+#define GET_RG_INI_PHASE (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000030 ) >> 4)
+#define GET_RG_HT_LTF_SEL_EQ (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000040 ) >> 6)
+#define GET_RG_HT_LTF_SEL_PILOT (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000080 ) >> 7)
+#define GET_RG_CCA_PWR_SEL (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000200 ) >> 9)
+#define GET_RG_CCA_XSCOR_PWR_SEL (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000400 ) >> 10)
+#define GET_RG_CCA_XSCOR_AVGPWR_SEL (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000800 ) >> 11)
+#define GET_RG_DEBUG_SEL (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x0000f000 ) >> 12)
+#define GET_RG_POST_CLK_EN (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00010000 ) >> 16)
+#define GET_IQCAL_RF_TX_EN (((REG32(ADR_RF_CONTROL_0)) & 0x00000001 ) >> 0)
+#define GET_IQCAL_RF_TX_PA_EN (((REG32(ADR_RF_CONTROL_0)) & 0x00000002 ) >> 1)
+#define GET_IQCAL_RF_TX_DAC_EN (((REG32(ADR_RF_CONTROL_0)) & 0x00000004 ) >> 2)
+#define GET_IQCAL_RF_RX_AGC (((REG32(ADR_RF_CONTROL_0)) & 0x00000008 ) >> 3)
+#define GET_IQCAL_RF_PGAG (((REG32(ADR_RF_CONTROL_0)) & 0x00000f00 ) >> 8)
+#define GET_IQCAL_RF_RFG (((REG32(ADR_RF_CONTROL_0)) & 0x00003000 ) >> 12)
+#define GET_RG_TONEGEN_FREQ (((REG32(ADR_RF_CONTROL_0)) & 0x007f0000 ) >> 16)
+#define GET_RG_TONEGEN_EN (((REG32(ADR_RF_CONTROL_0)) & 0x00800000 ) >> 23)
+#define GET_RG_TONEGEN_INIT_PH (((REG32(ADR_RF_CONTROL_0)) & 0x7f000000 ) >> 24)
+#define GET_RG_TONEGEN2_FREQ (((REG32(ADR_RF_CONTROL_1)) & 0x0000007f ) >> 0)
+#define GET_RG_TONEGEN2_EN (((REG32(ADR_RF_CONTROL_1)) & 0x00000080 ) >> 7)
+#define GET_RG_TONEGEN2_SCALE (((REG32(ADR_RF_CONTROL_1)) & 0x0000ff00 ) >> 8)
+#define GET_RG_TXIQ_CLP_THD_I (((REG32(ADR_TX_IQ_CONTROL_0)) & 0x000003ff ) >> 0)
+#define GET_RG_TXIQ_CLP_THD_Q (((REG32(ADR_TX_IQ_CONTROL_0)) & 0x03ff0000 ) >> 16)
+#define GET_RG_TX_I_SCALE (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x000000ff ) >> 0)
+#define GET_RG_TX_Q_SCALE (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x0000ff00 ) >> 8)
+#define GET_RG_TX_IQ_SWP (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x00010000 ) >> 16)
+#define GET_RG_TX_SGN_OUT (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x00020000 ) >> 17)
+#define GET_RG_TXIQ_EMU_IDX (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x003c0000 ) >> 18)
+#define GET_RG_TX_IQ_SRC (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x03000000 ) >> 24)
+#define GET_RG_TX_I_DC (((REG32(ADR_TX_IQ_CONTROL_2)) & 0x000003ff ) >> 0)
+#define GET_RG_TX_Q_DC (((REG32(ADR_TX_IQ_CONTROL_2)) & 0x03ff0000 ) >> 16)
+#define GET_RG_TX_IQ_THETA (((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0x0000001f ) >> 0)
+#define GET_RG_TX_IQ_ALPHA (((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0x00001f00 ) >> 8)
+#define GET_RG_TXIQ_NOSHRINK (((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0x00002000 ) >> 13)
+#define GET_RG_TX_I_OFFSET (((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0x00ff0000 ) >> 16)
+#define GET_RG_TX_Q_OFFSET (((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0xff000000 ) >> 24)
+#define GET_RG_RX_IQ_THETA (((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0x0000001f ) >> 0)
+#define GET_RG_RX_IQ_ALPHA (((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0x00001f00 ) >> 8)
+#define GET_RG_RXIQ_NOSHRINK (((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0x00002000 ) >> 13)
+#define GET_RG_MA_DPTH (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x0000000f ) >> 0)
+#define GET_RG_INTG_PH (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x000003f0 ) >> 4)
+#define GET_RG_INTG_PRD (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x00001c00 ) >> 10)
+#define GET_RG_INTG_MU (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x00006000 ) >> 13)
+#define GET_RG_IQCAL_SPRM_SELQ (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x00010000 ) >> 16)
+#define GET_RG_IQCAL_SPRM_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x00020000 ) >> 17)
+#define GET_RG_IQCAL_SPRM_FREQ (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x00fc0000 ) >> 18)
+#define GET_RG_IQCAL_IQCOL_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x01000000 ) >> 24)
+#define GET_RG_IQCAL_ALPHA_ESTM_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x02000000 ) >> 25)
+#define GET_RG_IQCAL_DC_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x04000000 ) >> 26)
+#define GET_RG_PHEST_STBY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x08000000 ) >> 27)
+#define GET_RG_PHEST_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x10000000 ) >> 28)
+#define GET_RG_GP_DIV_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x20000000 ) >> 29)
+#define GET_RG_DPD_GAIN_EST_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x40000000 ) >> 30)
+#define GET_RG_IQCAL_MULT_OP0 (((REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) & 0x000003ff ) >> 0)
+#define GET_RG_IQCAL_MULT_OP1 (((REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) & 0x03ff0000 ) >> 16)
+#define GET_RO_IQCAL_O (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x000fffff ) >> 0)
+#define GET_RO_IQCAL_SPRM_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x00100000 ) >> 20)
+#define GET_RO_IQCAL_IQCOL_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x00200000 ) >> 21)
+#define GET_RO_IQCAL_ALPHA_ESTM_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x00400000 ) >> 22)
+#define GET_RO_IQCAL_DC_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x00800000 ) >> 23)
+#define GET_RO_IQCAL_MULT_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x01000000 ) >> 24)
+#define GET_RO_FFT_ENRG_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x02000000 ) >> 25)
+#define GET_RO_PHEST_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x04000000 ) >> 26)
+#define GET_RO_GP_DIV_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x08000000 ) >> 27)
+#define GET_RO_GAIN_EST_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x10000000 ) >> 28)
+#define GET_RO_AMP_O (((REG32(ADR_RX_OBSERVATION_CIRCUIT_3)) & 0x000001ff ) >> 0)
+#define GET_RG_RX_I_SCALE (((REG32(ADR_RF_IQ_CONTROL_0)) & 0x000000ff ) >> 0)
+#define GET_RG_RX_Q_SCALE (((REG32(ADR_RF_IQ_CONTROL_0)) & 0x0000ff00 ) >> 8)
+#define GET_RG_RX_I_OFFSET (((REG32(ADR_RF_IQ_CONTROL_0)) & 0x00ff0000 ) >> 16)
+#define GET_RG_RX_Q_OFFSET (((REG32(ADR_RF_IQ_CONTROL_0)) & 0xff000000 ) >> 24)
+#define GET_RG_RX_IQ_SWP (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00000001 ) >> 0)
+#define GET_RG_RX_SGN_IN (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00000002 ) >> 1)
+#define GET_RG_RX_IQ_SRC (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x0000000c ) >> 2)
+#define GET_RG_ACI_GAIN (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00000ff0 ) >> 4)
+#define GET_RG_FFT_EN (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00001000 ) >> 12)
+#define GET_RG_FFT_MOD (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00002000 ) >> 13)
+#define GET_RG_FFT_SCALE (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00ffc000 ) >> 14)
+#define GET_RG_FFT_ENRG_FREQ (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x3f000000 ) >> 24)
+#define GET_RG_FPGA_80M_PH_UP (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x40000000 ) >> 30)
+#define GET_RG_FPGA_80M_PH_STP (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x80000000 ) >> 31)
+#define GET_RG_ADC2LA_SEL (((REG32(ADR_RF_IQ_CONTROL_2)) & 0x00000001 ) >> 0)
+#define GET_RG_ADC2LA_CLKPH (((REG32(ADR_RF_IQ_CONTROL_2)) & 0x00000002 ) >> 1)
+#define GET_RG_RXIQ_EMU_IDX (((REG32(ADR_RF_IQ_CONTROL_3)) & 0x0000000f ) >> 0)
+#define GET_RG_IQCAL_BP_ACI (((REG32(ADR_RF_IQ_CONTROL_3)) & 0x00000010 ) >> 4)
+#define GET_RG_DPD_AM_EN (((REG32(ADR_DPD_CONTROL)) & 0x00000001 ) >> 0)
+#define GET_RG_DPD_PM_EN (((REG32(ADR_DPD_CONTROL)) & 0x00000002 ) >> 1)
+#define GET_RG_DPD_PM_AMSEL (((REG32(ADR_DPD_CONTROL)) & 0x00000004 ) >> 2)
+#define GET_RG_DPD_020_GAIN (((REG32(ADR_DPD_GAIN_TABLE_0)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_040_GAIN (((REG32(ADR_DPD_GAIN_TABLE_0)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_060_GAIN (((REG32(ADR_DPD_GAIN_TABLE_1)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_080_GAIN (((REG32(ADR_DPD_GAIN_TABLE_1)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_0A0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_2)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_0C0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_2)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_0D0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_3)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_0E0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_3)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_0F0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_4)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_100_GAIN (((REG32(ADR_DPD_GAIN_TABLE_4)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_110_GAIN (((REG32(ADR_DPD_GAIN_TABLE_5)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_120_GAIN (((REG32(ADR_DPD_GAIN_TABLE_5)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_130_GAIN (((REG32(ADR_DPD_GAIN_TABLE_6)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_140_GAIN (((REG32(ADR_DPD_GAIN_TABLE_6)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_150_GAIN (((REG32(ADR_DPD_GAIN_TABLE_7)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_160_GAIN (((REG32(ADR_DPD_GAIN_TABLE_7)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_170_GAIN (((REG32(ADR_DPD_GAIN_TABLE_8)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_180_GAIN (((REG32(ADR_DPD_GAIN_TABLE_8)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_190_GAIN (((REG32(ADR_DPD_GAIN_TABLE_9)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_1A0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_9)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_1B0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_A)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_1C0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_A)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_1D0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_B)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_1E0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_B)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_1F0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_C)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_200_GAIN (((REG32(ADR_DPD_GAIN_TABLE_C)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_020_PH (((REG32(ADR_DPD_PH_TABLE_0)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_040_PH (((REG32(ADR_DPD_PH_TABLE_0)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_060_PH (((REG32(ADR_DPD_PH_TABLE_1)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_080_PH (((REG32(ADR_DPD_PH_TABLE_1)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_0A0_PH (((REG32(ADR_DPD_PH_TABLE_2)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_0C0_PH (((REG32(ADR_DPD_PH_TABLE_2)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_0D0_PH (((REG32(ADR_DPD_PH_TABLE_3)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_0E0_PH (((REG32(ADR_DPD_PH_TABLE_3)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_0F0_PH (((REG32(ADR_DPD_PH_TABLE_4)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_100_PH (((REG32(ADR_DPD_PH_TABLE_4)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_110_PH (((REG32(ADR_DPD_PH_TABLE_5)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_120_PH (((REG32(ADR_DPD_PH_TABLE_5)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_130_PH (((REG32(ADR_DPD_PH_TABLE_6)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_140_PH (((REG32(ADR_DPD_PH_TABLE_6)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_150_PH (((REG32(ADR_DPD_PH_TABLE_7)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_160_PH (((REG32(ADR_DPD_PH_TABLE_7)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_170_PH (((REG32(ADR_DPD_PH_TABLE_8)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_180_PH (((REG32(ADR_DPD_PH_TABLE_8)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_190_PH (((REG32(ADR_DPD_PH_TABLE_9)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_1A0_PH (((REG32(ADR_DPD_PH_TABLE_9)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_1B0_PH (((REG32(ADR_DPD_PH_TABLE_A)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_1C0_PH (((REG32(ADR_DPD_PH_TABLE_A)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_1D0_PH (((REG32(ADR_DPD_PH_TABLE_B)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_1E0_PH (((REG32(ADR_DPD_PH_TABLE_B)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_1F0_PH (((REG32(ADR_DPD_PH_TABLE_C)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_200_PH (((REG32(ADR_DPD_PH_TABLE_C)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_GAIN_EST_Y0 (((REG32(ADR_DPD_GAIN_ESTIMATION_0)) & 0x000001ff ) >> 0)
+#define GET_RG_DPD_GAIN_EST_Y1 (((REG32(ADR_DPD_GAIN_ESTIMATION_0)) & 0x01ff0000 ) >> 16)
+#define GET_RG_DPD_LOOP_GAIN (((REG32(ADR_DPD_GAIN_ESTIMATION_1)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_GAIN_EST_X0 (((REG32(ADR_DPD_GAIN_ESTIMATION_2)) & 0x000001ff ) >> 0)
+#define GET_RO_DPD_GAIN (((REG32(ADR_DPD_GAIN_ESTIMATION_2)) & 0x03ff0000 ) >> 16)
+#define GET_TX_SCALE_11B (((REG32(ADR_TX_GAIN_FACTOR)) & 0x000000ff ) >> 0)
+#define GET_TX_SCALE_11B_P0D5 (((REG32(ADR_TX_GAIN_FACTOR)) & 0x0000ff00 ) >> 8)
+#define GET_TX_SCALE_11G (((REG32(ADR_TX_GAIN_FACTOR)) & 0x00ff0000 ) >> 16)
+#define GET_TX_SCALE_11G_P0D5 (((REG32(ADR_TX_GAIN_FACTOR)) & 0xff000000 ) >> 24)
+#define GET_RG_EN_MANUAL (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_TX_EN (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_RG_TX_PA_EN (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_RG_TX_DAC_EN (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_RG_RX_AGC (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_RG_RX_GAIN_MANUAL (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000020 ) >> 5)
+#define GET_RG_RFG (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x000000c0 ) >> 6)
+#define GET_RG_PGAG (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000f00 ) >> 8)
+#define GET_RG_MODE (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00003000 ) >> 12)
+#define GET_RG_EN_TX_TRSW (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_RG_EN_SX (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00008000 ) >> 15)
+#define GET_RG_EN_RX_LNA (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00010000 ) >> 16)
+#define GET_RG_EN_RX_MIXER (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00020000 ) >> 17)
+#define GET_RG_EN_RX_DIV2 (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00040000 ) >> 18)
+#define GET_RG_EN_RX_LOBUF (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00080000 ) >> 19)
+#define GET_RG_EN_RX_TZ (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00100000 ) >> 20)
+#define GET_RG_EN_RX_FILTER (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00200000 ) >> 21)
+#define GET_RG_EN_RX_HPF (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00400000 ) >> 22)
+#define GET_RG_EN_RX_RSSI (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00800000 ) >> 23)
+#define GET_RG_EN_ADC (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x01000000 ) >> 24)
+#define GET_RG_EN_TX_MOD (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x02000000 ) >> 25)
+#define GET_RG_EN_TX_DIV2 (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x04000000 ) >> 26)
+#define GET_RG_EN_TX_DIV2_BUF (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x08000000 ) >> 27)
+#define GET_RG_EN_TX_LOBF (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x10000000 ) >> 28)
+#define GET_RG_EN_RX_LOBF (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x20000000 ) >> 29)
+#define GET_RG_SEL_DPLL_CLK (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x40000000 ) >> 30)
+#define GET_RG_EN_CLK_960MBY13_UART (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x80000000 ) >> 31)
+#define GET_RG_EN_TX_DPD (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_EN_TX_TSSI (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_RG_EN_RX_IQCAL (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_RG_EN_TX_DAC_CAL (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_RG_EN_TX_SELF_MIXER (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_RG_EN_TX_DAC_OUT (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000020 ) >> 5)
+#define GET_RG_EN_LDO_RX_FE (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000040 ) >> 6)
+#define GET_RG_EN_LDO_ABB (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000080 ) >> 7)
+#define GET_RG_EN_LDO_AFE (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000100 ) >> 8)
+#define GET_RG_EN_SX_CHPLDO (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000200 ) >> 9)
+#define GET_RG_EN_SX_LOBFLDO (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000400 ) >> 10)
+#define GET_RG_EN_IREF_RX (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_RG_EN_TX_DAC_VOUT (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00002000 ) >> 13)
+#define GET_RG_EN_SX_LCK_BIN (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_RG_RTC_CAL_MODE (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00010000 ) >> 16)
+#define GET_RG_EN_IQPAD_IOSW (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00020000 ) >> 17)
+#define GET_RG_EN_TESTPAD_IOSW (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00040000 ) >> 18)
+#define GET_RG_EN_TRXBF_BYPASS (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00080000 ) >> 19)
+#define GET_RG_LDO_LEVEL_RX_FE (((REG32(ADR_LDO_REGISTER)) & 0x00000007 ) >> 0)
+#define GET_RG_LDO_LEVEL_ABB (((REG32(ADR_LDO_REGISTER)) & 0x00000038 ) >> 3)
+#define GET_RG_LDO_LEVEL_AFE (((REG32(ADR_LDO_REGISTER)) & 0x000001c0 ) >> 6)
+#define GET_RG_SX_LDO_CHP_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x00000e00 ) >> 9)
+#define GET_RG_SX_LDO_LOBF_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x00007000 ) >> 12)
+#define GET_RG_SX_LDO_XOSC_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x00038000 ) >> 15)
+#define GET_RG_DP_LDO_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x001c0000 ) >> 18)
+#define GET_RG_SX_LDO_VCO_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x00e00000 ) >> 21)
+#define GET_RG_TX_LDO_TX_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x07000000 ) >> 24)
+#define GET_RG_EN_RX_PADSW (((REG32(ADR_ABB_REGISTER_1)) & 0x00000001 ) >> 0)
+#define GET_RG_EN_RX_TESTNODE (((REG32(ADR_ABB_REGISTER_1)) & 0x00000002 ) >> 1)
+#define GET_RG_RX_ABBCFIX (((REG32(ADR_ABB_REGISTER_1)) & 0x00000004 ) >> 2)
+#define GET_RG_RX_ABBCTUNE (((REG32(ADR_ABB_REGISTER_1)) & 0x000001f8 ) >> 3)
+#define GET_RG_RX_ABBOUT_TRI_STATE (((REG32(ADR_ABB_REGISTER_1)) & 0x00000200 ) >> 9)
+#define GET_RG_RX_ABB_N_MODE (((REG32(ADR_ABB_REGISTER_1)) & 0x00000400 ) >> 10)
+#define GET_RG_RX_EN_LOOPA (((REG32(ADR_ABB_REGISTER_1)) & 0x00000800 ) >> 11)
+#define GET_RG_RX_FILTERI1ST (((REG32(ADR_ABB_REGISTER_1)) & 0x00003000 ) >> 12)
+#define GET_RG_RX_FILTERI2ND (((REG32(ADR_ABB_REGISTER_1)) & 0x0000c000 ) >> 14)
+#define GET_RG_RX_FILTERI3RD (((REG32(ADR_ABB_REGISTER_1)) & 0x00030000 ) >> 16)
+#define GET_RG_RX_FILTERI_COURSE (((REG32(ADR_ABB_REGISTER_1)) & 0x000c0000 ) >> 18)
+#define GET_RG_RX_FILTERVCM (((REG32(ADR_ABB_REGISTER_1)) & 0x00300000 ) >> 20)
+#define GET_RG_RX_HPF3M (((REG32(ADR_ABB_REGISTER_1)) & 0x00400000 ) >> 22)
+#define GET_RG_RX_HPF300K (((REG32(ADR_ABB_REGISTER_1)) & 0x00800000 ) >> 23)
+#define GET_RG_RX_HPFI (((REG32(ADR_ABB_REGISTER_1)) & 0x03000000 ) >> 24)
+#define GET_RG_RX_HPF_FINALCORNER (((REG32(ADR_ABB_REGISTER_1)) & 0x0c000000 ) >> 26)
+#define GET_RG_RX_HPF_SETTLE1_C (((REG32(ADR_ABB_REGISTER_1)) & 0x30000000 ) >> 28)
+#define GET_RG_RX_HPF_SETTLE1_R (((REG32(ADR_ABB_REGISTER_2)) & 0x00000003 ) >> 0)
+#define GET_RG_RX_HPF_SETTLE2_C (((REG32(ADR_ABB_REGISTER_2)) & 0x0000000c ) >> 2)
+#define GET_RG_RX_HPF_SETTLE2_R (((REG32(ADR_ABB_REGISTER_2)) & 0x00000030 ) >> 4)
+#define GET_RG_RX_HPF_VCMCON2 (((REG32(ADR_ABB_REGISTER_2)) & 0x000000c0 ) >> 6)
+#define GET_RG_RX_HPF_VCMCON (((REG32(ADR_ABB_REGISTER_2)) & 0x00000300 ) >> 8)
+#define GET_RG_RX_OUTVCM (((REG32(ADR_ABB_REGISTER_2)) & 0x00000c00 ) >> 10)
+#define GET_RG_RX_TZI (((REG32(ADR_ABB_REGISTER_2)) & 0x00003000 ) >> 12)
+#define GET_RG_RX_TZ_OUT_TRISTATE (((REG32(ADR_ABB_REGISTER_2)) & 0x00004000 ) >> 14)
+#define GET_RG_RX_TZ_VCM (((REG32(ADR_ABB_REGISTER_2)) & 0x00018000 ) >> 15)
+#define GET_RG_EN_RX_RSSI_TESTNODE (((REG32(ADR_ABB_REGISTER_2)) & 0x000e0000 ) >> 17)
+#define GET_RG_RX_ADCRSSI_CLKSEL (((REG32(ADR_ABB_REGISTER_2)) & 0x00100000 ) >> 20)
+#define GET_RG_RX_ADCRSSI_VCM (((REG32(ADR_ABB_REGISTER_2)) & 0x00600000 ) >> 21)
+#define GET_RG_RX_REC_LPFCORNER (((REG32(ADR_ABB_REGISTER_2)) & 0x01800000 ) >> 23)
+#define GET_RG_RSSI_CLOCK_GATING (((REG32(ADR_ABB_REGISTER_2)) & 0x02000000 ) >> 25)
+#define GET_RG_TXPGA_CAPSW (((REG32(ADR_TX_FE_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_TXPGA_MAIN (((REG32(ADR_TX_FE_REGISTER)) & 0x000000fc ) >> 2)
+#define GET_RG_TXPGA_STEER (((REG32(ADR_TX_FE_REGISTER)) & 0x00003f00 ) >> 8)
+#define GET_RG_TXMOD_GMCELL (((REG32(ADR_TX_FE_REGISTER)) & 0x0000c000 ) >> 14)
+#define GET_RG_TXLPF_GMCELL (((REG32(ADR_TX_FE_REGISTER)) & 0x00030000 ) >> 16)
+#define GET_RG_PACELL_EN (((REG32(ADR_TX_FE_REGISTER)) & 0x001c0000 ) >> 18)
+#define GET_RG_PABIAS_CTRL (((REG32(ADR_TX_FE_REGISTER)) & 0x01e00000 ) >> 21)
+#define GET_RG_TX_DIV_VSET (((REG32(ADR_TX_FE_REGISTER)) & 0x0c000000 ) >> 26)
+#define GET_RG_TX_LOBUF_VSET (((REG32(ADR_TX_FE_REGISTER)) & 0x30000000 ) >> 28)
+#define GET_RG_RX_SQDC (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00000007 ) >> 0)
+#define GET_RG_RX_DIV2_CORE (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00000018 ) >> 3)
+#define GET_RG_RX_LOBUF (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00000060 ) >> 5)
+#define GET_RG_TX_DPDGM_BIAS (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00000780 ) >> 7)
+#define GET_RG_TX_DPD_DIV (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00007800 ) >> 11)
+#define GET_RG_TX_TSSI_BIAS (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00038000 ) >> 15)
+#define GET_RG_TX_TSSI_DIV (((REG32(ADR_RX_FE_REGISTER_1)) & 0x001c0000 ) >> 18)
+#define GET_RG_TX_TSSI_TESTMODE (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00200000 ) >> 21)
+#define GET_RG_TX_TSSI_TEST (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00c00000 ) >> 22)
+#define GET_RG_PACASCODE_CTRL (((REG32(ADR_RX_FE_REGISTER_1)) & 0x07000000 ) >> 24)
+#define GET_RG_RX_HG_LNA_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00000003 ) >> 0)
+#define GET_RG_RX_HG_LNAHGN_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x0000003c ) >> 2)
+#define GET_RG_RX_HG_LNAHGP_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x000003c0 ) >> 6)
+#define GET_RG_RX_HG_LNALG_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00003c00 ) >> 10)
+#define GET_RG_RX_HG_TZ_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x0000c000 ) >> 14)
+#define GET_RG_RX_HG_TZ_CAP (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00070000 ) >> 16)
+#define GET_RG_RX_MG_LNA_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00000003 ) >> 0)
+#define GET_RG_RX_MG_LNAHGN_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x0000003c ) >> 2)
+#define GET_RG_RX_MG_LNAHGP_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x000003c0 ) >> 6)
+#define GET_RG_RX_MG_LNALG_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00003c00 ) >> 10)
+#define GET_RG_RX_MG_TZ_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x0000c000 ) >> 14)
+#define GET_RG_RX_MG_TZ_CAP (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00070000 ) >> 16)
+#define GET_RG_RX_LG_LNA_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00000003 ) >> 0)
+#define GET_RG_RX_LG_LNAHGN_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x0000003c ) >> 2)
+#define GET_RG_RX_LG_LNAHGP_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x000003c0 ) >> 6)
+#define GET_RG_RX_LG_LNALG_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00003c00 ) >> 10)
+#define GET_RG_RX_LG_TZ_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x0000c000 ) >> 14)
+#define GET_RG_RX_LG_TZ_CAP (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00070000 ) >> 16)
+#define GET_RG_RX_ULG_LNA_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00000003 ) >> 0)
+#define GET_RG_RX_ULG_LNAHGN_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x0000003c ) >> 2)
+#define GET_RG_RX_ULG_LNAHGP_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x000003c0 ) >> 6)
+#define GET_RG_RX_ULG_LNALG_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00003c00 ) >> 10)
+#define GET_RG_RX_ULG_TZ_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x0000c000 ) >> 14)
+#define GET_RG_RX_ULG_TZ_CAP (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00070000 ) >> 16)
+#define GET_RG_HPF1_FAST_SET_X (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_HPF1_FAST_SET_Y (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_RG_HPF1_FAST_SET_Z (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_RG_HPF_T1A (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000018 ) >> 3)
+#define GET_RG_HPF_T1B (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000060 ) >> 5)
+#define GET_RG_HPF_T1C (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000180 ) >> 7)
+#define GET_RG_RX_LNA_TRI_SEL (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000600 ) >> 9)
+#define GET_RG_RX_LNA_SETTLE (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00001800 ) >> 11)
+#define GET_RG_TXGAIN_PHYCTRL (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00002000 ) >> 13)
+#define GET_RG_TX_GAIN (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x003fc000 ) >> 14)
+#define GET_RG_TXGAIN_MANUAL (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00400000 ) >> 22)
+#define GET_RG_TX_GAIN_OFFSET (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x07800000 ) >> 23)
+#define GET_RG_ADC_CLKSEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_ADC_DIBIAS (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000006 ) >> 1)
+#define GET_RG_ADC_DIVR (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_RG_ADC_DVCMI (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000030 ) >> 4)
+#define GET_RG_ADC_SAMSEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x000003c0 ) >> 6)
+#define GET_RG_ADC_STNBY (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000400 ) >> 10)
+#define GET_RG_ADC_TESTMODE (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_RG_ADC_TSEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x0000f000 ) >> 12)
+#define GET_RG_ADC_VRSEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x00030000 ) >> 16)
+#define GET_RG_DICMP (((REG32(ADR_RX_ADC_REGISTER)) & 0x000c0000 ) >> 18)
+#define GET_RG_DIOP (((REG32(ADR_RX_ADC_REGISTER)) & 0x00300000 ) >> 20)
+#define GET_RG_SARADC_VRSEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x00c00000 ) >> 22)
+#define GET_RG_EN_SAR_TEST (((REG32(ADR_RX_ADC_REGISTER)) & 0x03000000 ) >> 24)
+#define GET_RG_SARADC_THERMAL (((REG32(ADR_RX_ADC_REGISTER)) & 0x04000000 ) >> 26)
+#define GET_RG_SARADC_TSSI (((REG32(ADR_RX_ADC_REGISTER)) & 0x08000000 ) >> 27)
+#define GET_RG_CLK_SAR_SEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x30000000 ) >> 28)
+#define GET_RG_EN_SARADC (((REG32(ADR_RX_ADC_REGISTER)) & 0x40000000 ) >> 30)
+#define GET_RG_DACI1ST (((REG32(ADR_TX_DAC_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_TX_DACLPF_ICOURSE (((REG32(ADR_TX_DAC_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_TX_DACLPF_IFINE (((REG32(ADR_TX_DAC_REGISTER)) & 0x00000030 ) >> 4)
+#define GET_RG_TX_DACLPF_VCM (((REG32(ADR_TX_DAC_REGISTER)) & 0x000000c0 ) >> 6)
+#define GET_RG_TX_DAC_CKEDGE_SEL (((REG32(ADR_TX_DAC_REGISTER)) & 0x00000100 ) >> 8)
+#define GET_RG_TX_DAC_IBIAS (((REG32(ADR_TX_DAC_REGISTER)) & 0x00000600 ) >> 9)
+#define GET_RG_TX_DAC_OS (((REG32(ADR_TX_DAC_REGISTER)) & 0x00003800 ) >> 11)
+#define GET_RG_TX_DAC_RCAL (((REG32(ADR_TX_DAC_REGISTER)) & 0x0000c000 ) >> 14)
+#define GET_RG_TX_DAC_TSEL (((REG32(ADR_TX_DAC_REGISTER)) & 0x000f0000 ) >> 16)
+#define GET_RG_TX_EN_VOLTAGE_IN (((REG32(ADR_TX_DAC_REGISTER)) & 0x00100000 ) >> 20)
+#define GET_RG_TXLPF_BYPASS (((REG32(ADR_TX_DAC_REGISTER)) & 0x00200000 ) >> 21)
+#define GET_RG_TXLPF_BOOSTI (((REG32(ADR_TX_DAC_REGISTER)) & 0x00400000 ) >> 22)
+#define GET_RG_TX_DAC_IOFFSET (((REG32(ADR_TX_DAC_REGISTER)) & 0x07800000 ) >> 23)
+#define GET_RG_TX_DAC_QOFFSET (((REG32(ADR_TX_DAC_REGISTER)) & 0x78000000 ) >> 27)
+#define GET_RG_EN_SX_R3 (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_EN_SX_CH (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_RG_EN_SX_CHP (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_RG_EN_SX_DIVCK (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_RG_EN_SX_VCOBF (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_RG_EN_SX_VCO (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000020 ) >> 5)
+#define GET_RG_EN_SX_MOD (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000040 ) >> 6)
+#define GET_RG_EN_SX_DITHER (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000100 ) >> 8)
+#define GET_RG_EN_SX_VT_MON (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_RG_EN_SX_VT_MON_DG (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00001000 ) >> 12)
+#define GET_RG_EN_SX_DIV (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00002000 ) >> 13)
+#define GET_RG_EN_SX_LPF (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_RG_EN_DPL_MOD (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00008000 ) >> 15)
+#define GET_RG_DPL_MOD_ORDER (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00030000 ) >> 16)
+#define GET_RG_SX_RFCTRL_F (((REG32(ADR_SYN_REGISTER_1)) & 0x00ffffff ) >> 0)
+#define GET_RG_SX_SEL_CP (((REG32(ADR_SYN_REGISTER_1)) & 0x0f000000 ) >> 24)
+#define GET_RG_SX_SEL_CS (((REG32(ADR_SYN_REGISTER_1)) & 0xf0000000 ) >> 28)
+#define GET_RG_SX_RFCTRL_CH (((REG32(ADR_SYN_REGISTER_2)) & 0x000007ff ) >> 0)
+#define GET_RG_SX_SEL_C3 (((REG32(ADR_SYN_REGISTER_2)) & 0x00007800 ) >> 11)
+#define GET_RG_SX_SEL_RS (((REG32(ADR_SYN_REGISTER_2)) & 0x000f8000 ) >> 15)
+#define GET_RG_SX_SEL_R3 (((REG32(ADR_SYN_REGISTER_2)) & 0x01f00000 ) >> 20)
+#define GET_RG_SX_SEL_ICHP (((REG32(ADR_SYN_PFD_CHP)) & 0x0000001f ) >> 0)
+#define GET_RG_SX_SEL_PCHP (((REG32(ADR_SYN_PFD_CHP)) & 0x000003e0 ) >> 5)
+#define GET_RG_SX_SEL_CHP_REGOP (((REG32(ADR_SYN_PFD_CHP)) & 0x00003c00 ) >> 10)
+#define GET_RG_SX_SEL_CHP_UNIOP (((REG32(ADR_SYN_PFD_CHP)) & 0x0003c000 ) >> 14)
+#define GET_RG_SX_CHP_IOST_POL (((REG32(ADR_SYN_PFD_CHP)) & 0x00040000 ) >> 18)
+#define GET_RG_SX_CHP_IOST (((REG32(ADR_SYN_PFD_CHP)) & 0x00380000 ) >> 19)
+#define GET_RG_SX_PFDSEL (((REG32(ADR_SYN_PFD_CHP)) & 0x00400000 ) >> 22)
+#define GET_RG_SX_PFD_SET (((REG32(ADR_SYN_PFD_CHP)) & 0x00800000 ) >> 23)
+#define GET_RG_SX_PFD_SET1 (((REG32(ADR_SYN_PFD_CHP)) & 0x01000000 ) >> 24)
+#define GET_RG_SX_PFD_SET2 (((REG32(ADR_SYN_PFD_CHP)) & 0x02000000 ) >> 25)
+#define GET_RG_SX_VBNCAS_SEL (((REG32(ADR_SYN_PFD_CHP)) & 0x04000000 ) >> 26)
+#define GET_RG_SX_PFD_RST_H (((REG32(ADR_SYN_PFD_CHP)) & 0x08000000 ) >> 27)
+#define GET_RG_SX_PFD_TRUP (((REG32(ADR_SYN_PFD_CHP)) & 0x10000000 ) >> 28)
+#define GET_RG_SX_PFD_TRDN (((REG32(ADR_SYN_PFD_CHP)) & 0x20000000 ) >> 29)
+#define GET_RG_SX_PFD_TRSEL (((REG32(ADR_SYN_PFD_CHP)) & 0x40000000 ) >> 30)
+#define GET_RG_SX_VCOBA_R (((REG32(ADR_SYN_VCO_LOBF)) & 0x00000007 ) >> 0)
+#define GET_RG_SX_VCORSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x000000f8 ) >> 3)
+#define GET_RG_SX_VCOCUSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x00000f00 ) >> 8)
+#define GET_RG_SX_RXBFSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x0000f000 ) >> 12)
+#define GET_RG_SX_TXBFSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x000f0000 ) >> 16)
+#define GET_RG_SX_VCOBFSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x00f00000 ) >> 20)
+#define GET_RG_SX_DIVBFSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x0f000000 ) >> 24)
+#define GET_RG_SX_GNDR_SEL (((REG32(ADR_SYN_VCO_LOBF)) & 0xf0000000 ) >> 28)
+#define GET_RG_SX_DITHER_WEIGHT (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00000003 ) >> 0)
+#define GET_RG_SX_MOD_ORDER (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00000030 ) >> 4)
+#define GET_RG_SX_RST_H_DIV (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00000200 ) >> 9)
+#define GET_RG_SX_SDM_EDGE (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00000400 ) >> 10)
+#define GET_RG_SX_XO_GM (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00001800 ) >> 11)
+#define GET_RG_SX_REFBYTWO (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00002000 ) >> 13)
+#define GET_RG_SX_LCKEN (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00080000 ) >> 19)
+#define GET_RG_SX_PREVDD (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00f00000 ) >> 20)
+#define GET_RG_SX_PSCONTERVDD (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x0f000000 ) >> 24)
+#define GET_RG_SX_PH (((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0x00002000 ) >> 13)
+#define GET_RG_SX_PL (((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0x00004000 ) >> 14)
+#define GET_RG_XOSC_CBANK_XO (((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0x00078000 ) >> 15)
+#define GET_RG_XOSC_CBANK_XI (((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0x00780000 ) >> 19)
+#define GET_RG_SX_VT_MON_MODE (((REG32(ADR_SYN_LCK_VT)) & 0x00000001 ) >> 0)
+#define GET_RG_SX_VT_TH_HI (((REG32(ADR_SYN_LCK_VT)) & 0x00000006 ) >> 1)
+#define GET_RG_SX_VT_TH_LO (((REG32(ADR_SYN_LCK_VT)) & 0x00000018 ) >> 3)
+#define GET_RG_SX_VT_SET (((REG32(ADR_SYN_LCK_VT)) & 0x00000020 ) >> 5)
+#define GET_RG_SX_VT_MON_TMR (((REG32(ADR_SYN_LCK_VT)) & 0x00007fc0 ) >> 6)
+#define GET_RG_EN_DP_VT_MON (((REG32(ADR_DPLL_VCO_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_DP_VT_TH_HI (((REG32(ADR_DPLL_VCO_REGISTER)) & 0x00000006 ) >> 1)
+#define GET_RG_DP_VT_TH_LO (((REG32(ADR_DPLL_VCO_REGISTER)) & 0x00000018 ) >> 3)
+#define GET_RG_DP_CK320BY2 (((REG32(ADR_DPLL_VCO_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_RG_DP_OD_TEST (((REG32(ADR_DPLL_VCO_REGISTER)) & 0x00200000 ) >> 21)
+#define GET_RG_DP_BBPLL_BP (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_DP_BBPLL_ICP (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00000006 ) >> 1)
+#define GET_RG_DP_BBPLL_IDUAL (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00000018 ) >> 3)
+#define GET_RG_DP_BBPLL_OD_TEST (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x000001e0 ) >> 5)
+#define GET_RG_DP_BBPLL_PD (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00000200 ) >> 9)
+#define GET_RG_DP_BBPLL_TESTSEL (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00001c00 ) >> 10)
+#define GET_RG_DP_BBPLL_PFD_DLY (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00006000 ) >> 13)
+#define GET_RG_DP_RP (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00038000 ) >> 15)
+#define GET_RG_DP_RHP (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x000c0000 ) >> 18)
+#define GET_RG_DP_BBPLL_SDM_EDGE (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x80000000 ) >> 31)
+#define GET_RG_DP_FODIV (((REG32(ADR_DPLL_DIVIDER_REGISTER)) & 0x0007f000 ) >> 12)
+#define GET_RG_DP_REFDIV (((REG32(ADR_DPLL_DIVIDER_REGISTER)) & 0x1fc00000 ) >> 22)
+#define GET_RG_IDACAI_PGAG15 (((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0x0000003f ) >> 0)
+#define GET_RG_IDACAQ_PGAG15 (((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0x00000fc0 ) >> 6)
+#define GET_RG_IDACAI_PGAG14 (((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0x0003f000 ) >> 12)
+#define GET_RG_IDACAQ_PGAG14 (((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0x00fc0000 ) >> 18)
+#define GET_RG_DP_BBPLL_BS (((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0x3f000000 ) >> 24)
+#define GET_RG_IDACAI_PGAG13 (((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0x0000003f ) >> 0)
+#define GET_RG_IDACAQ_PGAG13 (((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0x00000fc0 ) >> 6)
+#define GET_RG_IDACAI_PGAG12 (((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0x0003f000 ) >> 12)
+#define GET_RG_IDACAQ_PGAG12 (((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0x00fc0000 ) >> 18)
+#define GET_RG_IDACAI_PGAG11 (((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0x0000003f ) >> 0)
+#define GET_RG_IDACAQ_PGAG11 (((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0x00000fc0 ) >> 6)
+#define GET_RG_IDACAI_PGAG10 (((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0x0003f000 ) >> 12)
+#define GET_RG_IDACAQ_PGAG10 (((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0x00fc0000 ) >> 18)
+#define GET_RG_IDACAI_PGAG9 (((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0x0000003f ) >> 0)
+#define GET_RG_IDACAQ_PGAG9 (((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0x00000fc0 ) >> 6)
+#define GET_RG_IDACAI_PGAG8 (((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0x0003f000 ) >> 12)
+#define GET_RG_IDACAQ_PGAG8 (((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0x00fc0000 ) >> 18)
+#define GET_RG_IDACAI_PGAG7 (((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0x0000003f ) >> 0)
+#define GET_RG_IDACAQ_PGAG7 (((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0x00000fc0 ) >> 6)
+#define GET_RG_IDACAI_PGAG6 (((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0x0003f000 ) >> 12)
+#define GET_RG_IDACAQ_PGAG6 (((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0x00fc0000 ) >> 18)
+#define GET_RG_IDACAI_PGAG5 (((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0x0000003f ) >> 0)
+#define GET_RG_IDACAQ_PGAG5 (((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0x00000fc0 ) >> 6)
+#define GET_RG_IDACAI_PGAG4 (((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0x0003f000 ) >> 12)
+#define GET_RG_IDACAQ_PGAG4 (((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0x00fc0000 ) >> 18)
+#define GET_RG_IDACAI_PGAG3 (((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0x0000003f ) >> 0)
+#define GET_RG_IDACAQ_PGAG3 (((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0x00000fc0 ) >> 6)
+#define GET_RG_IDACAI_PGAG2 (((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0x0003f000 ) >> 12)
+#define GET_RG_IDACAQ_PGAG2 (((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0x00fc0000 ) >> 18)
+#define GET_RG_IDACAI_PGAG1 (((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0x0000003f ) >> 0)
+#define GET_RG_IDACAQ_PGAG1 (((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0x00000fc0 ) >> 6)
+#define GET_RG_IDACAI_PGAG0 (((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0x0003f000 ) >> 12)
+#define GET_RG_IDACAQ_PGAG0 (((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0x00fc0000 ) >> 18)
+#define GET_RG_EN_RCAL (((REG32(ADR_RCAL_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_RCAL_SPD (((REG32(ADR_RCAL_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_RG_RCAL_TMR (((REG32(ADR_RCAL_REGISTER)) & 0x000001fc ) >> 2)
+#define GET_RG_RCAL_CODE_CWR (((REG32(ADR_RCAL_REGISTER)) & 0x00000200 ) >> 9)
+#define GET_RG_RCAL_CODE_CWD (((REG32(ADR_RCAL_REGISTER)) & 0x00007c00 ) >> 10)
+#define GET_RG_SX_SUB_SEL_CWR (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00000001 ) >> 0)
+#define GET_RG_SX_SUB_SEL_CWD (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x000000fe ) >> 1)
+#define GET_RG_SX_LCK_BIN_OFFSET (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00078000 ) >> 15)
+#define GET_RG_SX_LCK_BIN_PRECISION (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00080000 ) >> 19)
+#define GET_RG_SX_LOCK_EN_N (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00100000 ) >> 20)
+#define GET_RG_SX_LOCK_MANUAL (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00200000 ) >> 21)
+#define GET_RG_SX_SUB_MANUAL (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00400000 ) >> 22)
+#define GET_RG_SX_SUB_SEL (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x3f800000 ) >> 23)
+#define GET_RG_SX_MUX_SEL_VTH_BINL (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x40000000 ) >> 30)
+#define GET_RG_TRX_DUMMMY (((REG32(ADR_TRX_DUMMY_REGISTER)) & 0xffffffff ) >> 0)
+#define GET_RG_SX_DUMMMY (((REG32(ADR_SX_DUMMY_REGISTER)) & 0xffffffff ) >> 0)
+#define GET_RCAL_RDY (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00000001 ) >> 0)
+#define GET_LCK_BIN_RDY (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00000002 ) >> 1)
+#define GET_VT_MON_RDY (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00000004 ) >> 2)
+#define GET_DA_R_CODE_LUT (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x000007c0 ) >> 6)
+#define GET_AD_SX_VT_MON_Q (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00001800 ) >> 11)
+#define GET_AD_DP_VT_MON_Q (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00006000 ) >> 13)
+#define GET_RTC_CAL_RDY (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00008000 ) >> 15)
+#define GET_RG_SARADC_BIT (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x003f0000 ) >> 16)
+#define GET_SAR_ADC_FSM_RDY (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00400000 ) >> 22)
+#define GET_AD_CIRCUIT_VERSION (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x07800000 ) >> 23)
+#define GET_DA_R_CAL_CODE (((REG32(ADR_READ_ONLY_FLAGS_2)) & 0x0000001f ) >> 0)
+#define GET_DA_SX_SUB_SEL (((REG32(ADR_READ_ONLY_FLAGS_2)) & 0x00000fe0 ) >> 5)
+#define GET_RG_DPL_RFCTRL_CH (((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0x000007ff ) >> 0)
+#define GET_RG_RSSIADC_RO_BIT (((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0x00007800 ) >> 11)
+#define GET_RG_RX_ADC_I_RO_BIT (((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0x007f8000 ) >> 15)
+#define GET_RG_RX_ADC_Q_RO_BIT (((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0x7f800000 ) >> 23)
+#define GET_RG_DPL_RFCTRL_F (((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_II)) & 0x00ffffff ) >> 0)
+#define GET_RG_SX_TARGET_CNT (((REG32(ADR_SX_LCK_BIN_REGISTERS_II)) & 0x00001fff ) >> 0)
+#define GET_RG_RTC_OFFSET (((REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) & 0x000000ff ) >> 0)
+#define GET_RG_RTC_CAL_TARGET_COUNT (((REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) & 0x000fff00 ) >> 8)
+#define GET_RG_RF_D_REG (((REG32(ADR_RF_D_DIGITAL_DEBUG_PORT_REGISTER)) & 0x0000ffff ) >> 0)
+#define GET_DIRECT_MODE (((REG32(ADR_MMU_CTRL)) & 0x00000001 ) >> 0)
+#define GET_TAG_INTERLEAVE_MD (((REG32(ADR_MMU_CTRL)) & 0x00000002 ) >> 1)
+#define GET_DIS_DEMAND (((REG32(ADR_MMU_CTRL)) & 0x00000004 ) >> 2)
+#define GET_SAME_ID_ALLOC_MD (((REG32(ADR_MMU_CTRL)) & 0x00000008 ) >> 3)
+#define GET_HS_ACCESS_MD (((REG32(ADR_MMU_CTRL)) & 0x00000010 ) >> 4)
+#define GET_SRAM_ACCESS_MD (((REG32(ADR_MMU_CTRL)) & 0x00000020 ) >> 5)
+#define GET_NOHIT_RPASS_MD (((REG32(ADR_MMU_CTRL)) & 0x00000040 ) >> 6)
+#define GET_DMN_FLAG_CLR (((REG32(ADR_MMU_CTRL)) & 0x00000080 ) >> 7)
+#define GET_ERR_SW_RST_N (((REG32(ADR_MMU_CTRL)) & 0x00000100 ) >> 8)
+#define GET_ALR_SW_RST_N (((REG32(ADR_MMU_CTRL)) & 0x00000200 ) >> 9)
+#define GET_MCH_SW_RST_N (((REG32(ADR_MMU_CTRL)) & 0x00000400 ) >> 10)
+#define GET_TAG_SW_RST_N (((REG32(ADR_MMU_CTRL)) & 0x00000800 ) >> 11)
+#define GET_ABT_SW_RST_N (((REG32(ADR_MMU_CTRL)) & 0x00001000 ) >> 12)
+#define GET_MMU_VER (((REG32(ADR_MMU_CTRL)) & 0x0000e000 ) >> 13)
+#define GET_MMU_SHARE_MCU (((REG32(ADR_MMU_CTRL)) & 0x00ff0000 ) >> 16)
+#define GET_HS_WR (((REG32(ADR_HS_CTRL)) & 0x00000001 ) >> 0)
+#define GET_HS_FLAG (((REG32(ADR_HS_CTRL)) & 0x00000010 ) >> 4)
+#define GET_HS_ID (((REG32(ADR_HS_CTRL)) & 0x00007f00 ) >> 8)
+#define GET_HS_CHANNEL (((REG32(ADR_HS_CTRL)) & 0x000f0000 ) >> 16)
+#define GET_HS_PAGE (((REG32(ADR_HS_CTRL)) & 0x00f00000 ) >> 20)
+#define GET_HS_DATA (((REG32(ADR_HS_CTRL)) & 0xff000000 ) >> 24)
+#define GET_CPU_POR0 (((REG32(ADR_CPU_POR0_7)) & 0x0000000f ) >> 0)
+#define GET_CPU_POR1 (((REG32(ADR_CPU_POR0_7)) & 0x000000f0 ) >> 4)
+#define GET_CPU_POR2 (((REG32(ADR_CPU_POR0_7)) & 0x00000f00 ) >> 8)
+#define GET_CPU_POR3 (((REG32(ADR_CPU_POR0_7)) & 0x0000f000 ) >> 12)
+#define GET_CPU_POR4 (((REG32(ADR_CPU_POR0_7)) & 0x000f0000 ) >> 16)
+#define GET_CPU_POR5 (((REG32(ADR_CPU_POR0_7)) & 0x00f00000 ) >> 20)
+#define GET_CPU_POR6 (((REG32(ADR_CPU_POR0_7)) & 0x0f000000 ) >> 24)
+#define GET_CPU_POR7 (((REG32(ADR_CPU_POR0_7)) & 0xf0000000 ) >> 28)
+#define GET_CPU_POR8 (((REG32(ADR_CPU_POR8_F)) & 0x0000000f ) >> 0)
+#define GET_CPU_POR9 (((REG32(ADR_CPU_POR8_F)) & 0x000000f0 ) >> 4)
+#define GET_CPU_PORA (((REG32(ADR_CPU_POR8_F)) & 0x00000f00 ) >> 8)
+#define GET_CPU_PORB (((REG32(ADR_CPU_POR8_F)) & 0x0000f000 ) >> 12)
+#define GET_CPU_PORC (((REG32(ADR_CPU_POR8_F)) & 0x000f0000 ) >> 16)
+#define GET_CPU_PORD (((REG32(ADR_CPU_POR8_F)) & 0x00f00000 ) >> 20)
+#define GET_CPU_PORE (((REG32(ADR_CPU_POR8_F)) & 0x0f000000 ) >> 24)
+#define GET_CPU_PORF (((REG32(ADR_CPU_POR8_F)) & 0xf0000000 ) >> 28)
+#define GET_ACC_WR_LEN (((REG32(ADR_REG_LEN_CTRL)) & 0x0000003f ) >> 0)
+#define GET_ACC_RD_LEN (((REG32(ADR_REG_LEN_CTRL)) & 0x00003f00 ) >> 8)
+#define GET_REQ_NACK_CLR (((REG32(ADR_REG_LEN_CTRL)) & 0x00008000 ) >> 15)
+#define GET_NACK_FLAG_BUS (((REG32(ADR_REG_LEN_CTRL)) & 0xffff0000 ) >> 16)
+#define GET_DMN_R_PASS (((REG32(ADR_DMN_READ_BYPASS)) & 0x0000ffff ) >> 0)
+#define GET_PARA_ALC_RLS (((REG32(ADR_DMN_READ_BYPASS)) & 0x00010000 ) >> 16)
+#define GET_REQ_PORNS_CHGEN (((REG32(ADR_DMN_READ_BYPASS)) & 0x01000000 ) >> 24)
+#define GET_ALC_ABT_ID (((REG32(ADR_ALC_RLS_ABORT)) & 0x0000007f ) >> 0)
+#define GET_ALC_ABT_INT (((REG32(ADR_ALC_RLS_ABORT)) & 0x00008000 ) >> 15)
+#define GET_RLS_ABT_ID (((REG32(ADR_ALC_RLS_ABORT)) & 0x007f0000 ) >> 16)
+#define GET_RLS_ABT_INT (((REG32(ADR_ALC_RLS_ABORT)) & 0x80000000 ) >> 31)
+#define GET_DEBUG_CTL (((REG32(ADR_DEBUG_CTL)) & 0x000000ff ) >> 0)
+#define GET_DEBUG_H16 (((REG32(ADR_DEBUG_CTL)) & 0x00000100 ) >> 8)
+#define GET_DEBUG_OUT (((REG32(ADR_DEBUG_OUT)) & 0xffffffff ) >> 0)
+#define GET_ALC_ERR (((REG32(ADR_MMU_STATUS)) & 0x00000001 ) >> 0)
+#define GET_RLS_ERR (((REG32(ADR_MMU_STATUS)) & 0x00000002 ) >> 1)
+#define GET_AL_STATE (((REG32(ADR_MMU_STATUS)) & 0x00000700 ) >> 8)
+#define GET_RL_STATE (((REG32(ADR_MMU_STATUS)) & 0x00007000 ) >> 12)
+#define GET_ALC_ERR_ID (((REG32(ADR_MMU_STATUS)) & 0x007f0000 ) >> 16)
+#define GET_RLS_ERR_ID (((REG32(ADR_MMU_STATUS)) & 0x7f000000 ) >> 24)
+#define GET_DMN_NOHIT_FLAG (((REG32(ADR_DMN_STATUS)) & 0x00000001 ) >> 0)
+#define GET_DMN_FLAG (((REG32(ADR_DMN_STATUS)) & 0x00000002 ) >> 1)
+#define GET_DMN_WR (((REG32(ADR_DMN_STATUS)) & 0x00000008 ) >> 3)
+#define GET_DMN_PORT (((REG32(ADR_DMN_STATUS)) & 0x000000f0 ) >> 4)
+#define GET_DMN_NHIT_ID (((REG32(ADR_DMN_STATUS)) & 0x00007f00 ) >> 8)
+#define GET_DMN_NHIT_ADDR (((REG32(ADR_DMN_STATUS)) & 0xffff0000 ) >> 16)
+#define GET_TX_MOUNT (((REG32(ADR_TAG_STATUS)) & 0x000000ff ) >> 0)
+#define GET_RX_MOUNT (((REG32(ADR_TAG_STATUS)) & 0x0000ff00 ) >> 8)
+#define GET_AVA_TAG (((REG32(ADR_TAG_STATUS)) & 0x01ff0000 ) >> 16)
+#define GET_PKTBUF_FULL (((REG32(ADR_TAG_STATUS)) & 0x80000000 ) >> 31)
+#define GET_DMN_NOHIT_MCU (((REG32(ADR_DMN_MCU_STATUS)) & 0x00000001 ) >> 0)
+#define GET_DMN_MCU_FLAG (((REG32(ADR_DMN_MCU_STATUS)) & 0x00000002 ) >> 1)
+#define GET_DMN_MCU_WR (((REG32(ADR_DMN_MCU_STATUS)) & 0x00000008 ) >> 3)
+#define GET_DMN_MCU_PORT (((REG32(ADR_DMN_MCU_STATUS)) & 0x000000f0 ) >> 4)
+#define GET_DMN_MCU_ID (((REG32(ADR_DMN_MCU_STATUS)) & 0x00007f00 ) >> 8)
+#define GET_DMN_MCU_ADDR (((REG32(ADR_DMN_MCU_STATUS)) & 0xffff0000 ) >> 16)
+#define GET_MB_IDTBL_31_0 (((REG32(ADR_MB_IDTBL_0_STATUS)) & 0xffffffff ) >> 0)
+#define GET_MB_IDTBL_63_32 (((REG32(ADR_MB_IDTBL_1_STATUS)) & 0xffffffff ) >> 0)
+#define GET_MB_IDTBL_95_64 (((REG32(ADR_MB_IDTBL_2_STATUS)) & 0xffffffff ) >> 0)
+#define GET_MB_IDTBL_127_96 (((REG32(ADR_MB_IDTBL_3_STATUS)) & 0xffffffff ) >> 0)
+#define GET_PKT_IDTBL_31_0 (((REG32(ADR_PKT_IDTBL_0_STATUS)) & 0xffffffff ) >> 0)
+#define GET_PKT_IDTBL_63_32 (((REG32(ADR_PKT_IDTBL_1_STATUS)) & 0xffffffff ) >> 0)
+#define GET_PKT_IDTBL_95_64 (((REG32(ADR_PKT_IDTBL_2_STATUS)) & 0xffffffff ) >> 0)
+#define GET_PKT_IDTBL_127_96 (((REG32(ADR_PKT_IDTBL_3_STATUS)) & 0xffffffff ) >> 0)
+#define GET_DMN_IDTBL_31_0 (((REG32(ADR_DMN_IDTBL_0_STATUS)) & 0xffffffff ) >> 0)
+#define GET_DMN_IDTBL_63_32 (((REG32(ADR_DMN_IDTBL_1_STATUS)) & 0xffffffff ) >> 0)
+#define GET_DMN_IDTBL_95_64 (((REG32(ADR_DMN_IDTBL_2_STATUS)) & 0xffffffff ) >> 0)
+#define GET_DMN_IDTBL_127_96 (((REG32(ADR_DMN_IDTBL_3_STATUS)) & 0xffffffff ) >> 0)
+#define GET_NEQ_MB_ID_31_0 (((REG32(ADR_MB_NEQID_0_STATUS)) & 0xffffffff ) >> 0)
+#define GET_NEQ_MB_ID_63_32 (((REG32(ADR_MB_NEQID_1_STATUS)) & 0xffffffff ) >> 0)
+#define GET_NEQ_MB_ID_95_64 (((REG32(ADR_MB_NEQID_2_STATUS)) & 0xffffffff ) >> 0)
+#define GET_NEQ_MB_ID_127_96 (((REG32(ADR_MB_NEQID_3_STATUS)) & 0xffffffff ) >> 0)
+#define GET_NEQ_PKT_ID_31_0 (((REG32(ADR_PKT_NEQID_0_STATUS)) & 0xffffffff ) >> 0)
+#define GET_NEQ_PKT_ID_63_32 (((REG32(ADR_PKT_NEQID_1_STATUS)) & 0xffffffff ) >> 0)
+#define GET_NEQ_PKT_ID_95_64 (((REG32(ADR_PKT_NEQID_2_STATUS)) & 0xffffffff ) >> 0)
+#define GET_NEQ_PKT_ID_127_96 (((REG32(ADR_PKT_NEQID_3_STATUS)) & 0xffffffff ) >> 0)
+#define GET_ALC_NOCHG_ID (((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0x0000007f ) >> 0)
+#define GET_ALC_NOCHG_INT (((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0x00008000 ) >> 15)
+#define GET_NEQ_PKT_FLAG (((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0x00010000 ) >> 16)
+#define GET_NEQ_MB_FLAG (((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0x01000000 ) >> 24)
+#define GET_SRAM_TAG_0 (((REG32(ADR_TAG_SRAM0_F_STATUS_0)) & 0x0000ffff ) >> 0)
+#define GET_SRAM_TAG_1 (((REG32(ADR_TAG_SRAM0_F_STATUS_0)) & 0xffff0000 ) >> 16)
+#define GET_SRAM_TAG_2 (((REG32(ADR_TAG_SRAM0_F_STATUS_1)) & 0x0000ffff ) >> 0)
+#define GET_SRAM_TAG_3 (((REG32(ADR_TAG_SRAM0_F_STATUS_1)) & 0xffff0000 ) >> 16)
+#define GET_SRAM_TAG_4 (((REG32(ADR_TAG_SRAM0_F_STATUS_2)) & 0x0000ffff ) >> 0)
+#define GET_SRAM_TAG_5 (((REG32(ADR_TAG_SRAM0_F_STATUS_2)) & 0xffff0000 ) >> 16)
+#define GET_SRAM_TAG_6 (((REG32(ADR_TAG_SRAM0_F_STATUS_3)) & 0x0000ffff ) >> 0)
+#define GET_SRAM_TAG_7 (((REG32(ADR_TAG_SRAM0_F_STATUS_3)) & 0xffff0000 ) >> 16)
+#define GET_SRAM_TAG_8 (((REG32(ADR_TAG_SRAM0_F_STATUS_4)) & 0x0000ffff ) >> 0)
+#define GET_SRAM_TAG_9 (((REG32(ADR_TAG_SRAM0_F_STATUS_4)) & 0xffff0000 ) >> 16)
+#define GET_SRAM_TAG_10 (((REG32(ADR_TAG_SRAM0_F_STATUS_5)) & 0x0000ffff ) >> 0)
+#define GET_SRAM_TAG_11 (((REG32(ADR_TAG_SRAM0_F_STATUS_5)) & 0xffff0000 ) >> 16)
+#define GET_SRAM_TAG_12 (((REG32(ADR_TAG_SRAM0_F_STATUS_6)) & 0x0000ffff ) >> 0)
+#define GET_SRAM_TAG_13 (((REG32(ADR_TAG_SRAM0_F_STATUS_6)) & 0xffff0000 ) >> 16)
+#define GET_SRAM_TAG_14 (((REG32(ADR_TAG_SRAM0_F_STATUS_7)) & 0x0000ffff ) >> 0)
+#define GET_SRAM_TAG_15 (((REG32(ADR_TAG_SRAM0_F_STATUS_7)) & 0xffff0000 ) >> 16)
+#define SET_MCU_ENABLE(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 0) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffffe))
+#define SET_MAC_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 1) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffffd))
+#define SET_MCU_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 2) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffffb))
+#define SET_SDIO_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 3) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffff7))
+#define SET_SPI_SLV_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 4) | ((REG32(ADR_BRG_SW_RST)) & 0xffffffef))
+#define SET_UART_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 5) | ((REG32(ADR_BRG_SW_RST)) & 0xffffffdf))
+#define SET_DMA_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 6) | ((REG32(ADR_BRG_SW_RST)) & 0xffffffbf))
+#define SET_WDT_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 7) | ((REG32(ADR_BRG_SW_RST)) & 0xffffff7f))
+#define SET_I2C_SLV_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 8) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffeff))
+#define SET_INT_CTL_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 9) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffdff))
+#define SET_BTCX_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 10) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffbff))
+#define SET_GPIO_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 11) | ((REG32(ADR_BRG_SW_RST)) & 0xfffff7ff))
+#define SET_US0TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 12) | ((REG32(ADR_BRG_SW_RST)) & 0xffffefff))
+#define SET_US1TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 13) | ((REG32(ADR_BRG_SW_RST)) & 0xffffdfff))
+#define SET_US2TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 14) | ((REG32(ADR_BRG_SW_RST)) & 0xffffbfff))
+#define SET_US3TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 15) | ((REG32(ADR_BRG_SW_RST)) & 0xffff7fff))
+#define SET_MS0TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 16) | ((REG32(ADR_BRG_SW_RST)) & 0xfffeffff))
+#define SET_MS1TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 17) | ((REG32(ADR_BRG_SW_RST)) & 0xfffdffff))
+#define SET_MS2TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 18) | ((REG32(ADR_BRG_SW_RST)) & 0xfffbffff))
+#define SET_MS3TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 19) | ((REG32(ADR_BRG_SW_RST)) & 0xfff7ffff))
+#define SET_RF_BB_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 20) | ((REG32(ADR_BRG_SW_RST)) & 0xffefffff))
+#define SET_SYS_ALL_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 21) | ((REG32(ADR_BRG_SW_RST)) & 0xffdfffff))
+#define SET_DAT_UART_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 22) | ((REG32(ADR_BRG_SW_RST)) & 0xffbfffff))
+#define SET_I2C_MST_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 23) | ((REG32(ADR_BRG_SW_RST)) & 0xff7fffff))
+#define SET_RG_REBOOT(_VAL_) (REG32(ADR_BOOT)) = (((_VAL_) << 0) | ((REG32(ADR_BOOT)) & 0xfffffffe))
+#define SET_TRAP_IMG_FLS(_VAL_) (REG32(ADR_BOOT)) = (((_VAL_) << 16) | ((REG32(ADR_BOOT)) & 0xfffeffff))
+#define SET_TRAP_REBOOT(_VAL_) (REG32(ADR_BOOT)) = (((_VAL_) << 17) | ((REG32(ADR_BOOT)) & 0xfffdffff))
+#define SET_TRAP_BOOT_FLS(_VAL_) (REG32(ADR_BOOT)) = (((_VAL_) << 18) | ((REG32(ADR_BOOT)) & 0xfffbffff))
+#define SET_CHIP_ID_31_0(_VAL_) (REG32(ADR_CHIP_ID_0)) = (((_VAL_) << 0) | ((REG32(ADR_CHIP_ID_0)) & 0x00000000))
+#define SET_CHIP_ID_63_32(_VAL_) (REG32(ADR_CHIP_ID_1)) = (((_VAL_) << 0) | ((REG32(ADR_CHIP_ID_1)) & 0x00000000))
+#define SET_CHIP_ID_95_64(_VAL_) (REG32(ADR_CHIP_ID_2)) = (((_VAL_) << 0) | ((REG32(ADR_CHIP_ID_2)) & 0x00000000))
+#define SET_CHIP_ID_127_96(_VAL_) (REG32(ADR_CHIP_ID_3)) = (((_VAL_) << 0) | ((REG32(ADR_CHIP_ID_3)) & 0x00000000))
+#define SET_CK_SEL_1_0(_VAL_) (REG32(ADR_CLOCK_SELECTION)) = (((_VAL_) << 0) | ((REG32(ADR_CLOCK_SELECTION)) & 0xfffffffc))
+#define SET_CK_SEL_2(_VAL_) (REG32(ADR_CLOCK_SELECTION)) = (((_VAL_) << 2) | ((REG32(ADR_CLOCK_SELECTION)) & 0xfffffffb))
+#define SET_SYS_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 0) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffffe))
+#define SET_MAC_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 1) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffffd))
+#define SET_MCU_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 2) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffffb))
+#define SET_SDIO_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 3) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffff7))
+#define SET_SPI_SLV_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 4) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffffef))
+#define SET_UART_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 5) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffffdf))
+#define SET_DMA_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 6) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffffbf))
+#define SET_WDT_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 7) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffff7f))
+#define SET_I2C_SLV_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 8) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffeff))
+#define SET_INT_CTL_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 9) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffdff))
+#define SET_BTCX_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 10) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffbff))
+#define SET_GPIO_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 11) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffff7ff))
+#define SET_US0TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 12) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffefff))
+#define SET_US1TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 13) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffdfff))
+#define SET_US2TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 14) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffbfff))
+#define SET_US3TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 15) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffff7fff))
+#define SET_MS0TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 16) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffeffff))
+#define SET_MS1TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 17) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffdffff))
+#define SET_MS2TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 18) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffbffff))
+#define SET_MS3TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 19) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfff7ffff))
+#define SET_BIST_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 20) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffefffff))
+#define SET_I2C_MST_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 23) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xff7fffff))
+#define SET_BTCX_CSR_CLK_EN(_VAL_) (REG32(ADR_SYS_CSR_CLOCK_ENABLE)) = (((_VAL_) << 10) | ((REG32(ADR_SYS_CSR_CLOCK_ENABLE)) & 0xfffffbff))
+#define SET_MCU_DBG_SEL(_VAL_) (REG32(ADR_MCU_DBG_SEL)) = (((_VAL_) << 0) | ((REG32(ADR_MCU_DBG_SEL)) & 0xffffffc0))
+#define SET_MCU_STOP_NOGRANT(_VAL_) (REG32(ADR_MCU_DBG_SEL)) = (((_VAL_) << 8) | ((REG32(ADR_MCU_DBG_SEL)) & 0xfffffeff))
+#define SET_MCU_STOP_ANYTIME(_VAL_) (REG32(ADR_MCU_DBG_SEL)) = (((_VAL_) << 9) | ((REG32(ADR_MCU_DBG_SEL)) & 0xfffffdff))
+#define SET_MCU_DBG_DATA(_VAL_) (REG32(ADR_MCU_DBG_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_MCU_DBG_DATA)) & 0x00000000))
+#define SET_AHB_SW_RST(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xfffffffe))
+#define SET_AHB_ERR_RST(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xfffffffd))
+#define SET_REG_AHB_DEBUG_MX(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 4) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xffffffcf))
+#define SET_REG_PKT_W_NBRT(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xfffffeff))
+#define SET_REG_PKT_R_NBRT(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 9) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xfffffdff))
+#define SET_IQ_SRAM_SEL_0(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 12) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xffffefff))
+#define SET_IQ_SRAM_SEL_1(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 13) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xffffdfff))
+#define SET_IQ_SRAM_SEL_2(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 14) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xffffbfff))
+#define SET_AHB_STATUS(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_AHB_BRG_STATUS)) & 0x0000ffff))
+#define SET_PARALLEL_DR(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xfffffffe))
+#define SET_MBRUN(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 4) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xffffffef))
+#define SET_SHIFT_DR(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xfffffeff))
+#define SET_MODE_REG_SI(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 9) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xfffffdff))
+#define SET_SIMULATION_MODE(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 10) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xfffffbff))
+#define SET_DBIST_MODE(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 11) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xfffff7ff))
+#define SET_MODE_REG_IN(_VAL_) (REG32(ADR_BIST_MODE_REG_IN)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MODE_REG_IN)) & 0xffe00000))
+#define SET_MODE_REG_OUT_MCU(_VAL_) (REG32(ADR_BIST_MODE_REG_OUT)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MODE_REG_OUT)) & 0xffe00000))
+#define SET_MODE_REG_SO_MCU(_VAL_) (REG32(ADR_BIST_MODE_REG_OUT)) = (((_VAL_) << 31) | ((REG32(ADR_BIST_MODE_REG_OUT)) & 0x7fffffff))
+#define SET_MONITOR_BUS_MCU_31_0(_VAL_) (REG32(ADR_BIST_MONITOR_BUS_LSB)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MONITOR_BUS_LSB)) & 0x00000000))
+#define SET_MONITOR_BUS_MCU_33_32(_VAL_) (REG32(ADR_BIST_MONITOR_BUS_MSB)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MONITOR_BUS_MSB)) & 0xfffffffc))
+#define SET_TB_ADR_SEL(_VAL_) (REG32(ADR_TB_ADR_SEL)) = (((_VAL_) << 0) | ((REG32(ADR_TB_ADR_SEL)) & 0xffff0000))
+#define SET_TB_CS(_VAL_) (REG32(ADR_TB_ADR_SEL)) = (((_VAL_) << 31) | ((REG32(ADR_TB_ADR_SEL)) & 0x7fffffff))
+#define SET_TB_RDATA(_VAL_) (REG32(ADR_TB_RDATA)) = (((_VAL_) << 0) | ((REG32(ADR_TB_RDATA)) & 0x00000000))
+#define SET_UART_W2B_EN(_VAL_) (REG32(ADR_UART_W2B)) = (((_VAL_) << 0) | ((REG32(ADR_UART_W2B)) & 0xfffffffe))
+#define SET_DATA_UART_W2B_EN(_VAL_) (REG32(ADR_UART_W2B)) = (((_VAL_) << 4) | ((REG32(ADR_UART_W2B)) & 0xffffffef))
+#define SET_AHB_ILL_ADDR(_VAL_) (REG32(ADR_AHB_ILL_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_AHB_ILL_ADDR)) & 0x00000000))
+#define SET_AHB_FEN_ADDR(_VAL_) (REG32(ADR_AHB_FEN_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_AHB_FEN_ADDR)) & 0x00000000))
+#define SET_ILL_ADDR_CLR(_VAL_) (REG32(ADR_AHB_ILLFEN_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_AHB_ILLFEN_STATUS)) & 0xfffffffe))
+#define SET_FENCE_HIT_CLR(_VAL_) (REG32(ADR_AHB_ILLFEN_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_AHB_ILLFEN_STATUS)) & 0xfffffffd))
+#define SET_ILL_ADDR_INT(_VAL_) (REG32(ADR_AHB_ILLFEN_STATUS)) = (((_VAL_) << 4) | ((REG32(ADR_AHB_ILLFEN_STATUS)) & 0xffffffef))
+#define SET_FENCE_HIT_INT(_VAL_) (REG32(ADR_AHB_ILLFEN_STATUS)) = (((_VAL_) << 5) | ((REG32(ADR_AHB_ILLFEN_STATUS)) & 0xffffffdf))
+#define SET_PWM_INI_VALUE_P_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 0) | ((REG32(ADR_PWM_A)) & 0xffffff00))
+#define SET_PWM_INI_VALUE_N_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 8) | ((REG32(ADR_PWM_A)) & 0xffff00ff))
+#define SET_PWM_POST_SCALER_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 16) | ((REG32(ADR_PWM_A)) & 0xfff0ffff))
+#define SET_PWM_ALWAYSON_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 29) | ((REG32(ADR_PWM_A)) & 0xdfffffff))
+#define SET_PWM_INVERT_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 30) | ((REG32(ADR_PWM_A)) & 0xbfffffff))
+#define SET_PWM_ENABLE_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 31) | ((REG32(ADR_PWM_A)) & 0x7fffffff))
+#define SET_PWM_INI_VALUE_P_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 0) | ((REG32(ADR_PWM_B)) & 0xffffff00))
+#define SET_PWM_INI_VALUE_N_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 8) | ((REG32(ADR_PWM_B)) & 0xffff00ff))
+#define SET_PWM_POST_SCALER_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 16) | ((REG32(ADR_PWM_B)) & 0xfff0ffff))
+#define SET_PWM_ALWAYSON_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 29) | ((REG32(ADR_PWM_B)) & 0xdfffffff))
+#define SET_PWM_INVERT_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 30) | ((REG32(ADR_PWM_B)) & 0xbfffffff))
+#define SET_PWM_ENABLE_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 31) | ((REG32(ADR_PWM_B)) & 0x7fffffff))
+#define SET_HBUSREQ_LOCK(_VAL_) (REG32(ADR_HBUSREQ_LOCK)) = (((_VAL_) << 0) | ((REG32(ADR_HBUSREQ_LOCK)) & 0xffffe000))
+#define SET_HBURST_LOCK(_VAL_) (REG32(ADR_HBURST_LOCK)) = (((_VAL_) << 0) | ((REG32(ADR_HBURST_LOCK)) & 0xffffe000))
+#define SET_PRESCALER_USTIMER(_VAL_) (REG32(ADR_PRESCALER_USTIMER)) = (((_VAL_) << 0) | ((REG32(ADR_PRESCALER_USTIMER)) & 0xfffffe00))
+#define SET_MODE_REG_IN_MMU(_VAL_) (REG32(ADR_BIST_MODE_REG_IN_MMU)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MODE_REG_IN_MMU)) & 0xffff0000))
+#define SET_MODE_REG_OUT_MMU(_VAL_) (REG32(ADR_BIST_MODE_REG_OUT_MMU)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MODE_REG_OUT_MMU)) & 0xffff0000))
+#define SET_MODE_REG_SO_MMU(_VAL_) (REG32(ADR_BIST_MODE_REG_OUT_MMU)) = (((_VAL_) << 31) | ((REG32(ADR_BIST_MODE_REG_OUT_MMU)) & 0x7fffffff))
+#define SET_MONITOR_BUS_MMU(_VAL_) (REG32(ADR_BIST_MONITOR_BUS_MMU)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MONITOR_BUS_MMU)) & 0xfff80000))
+#define SET_TEST_MODE0(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_TEST_MODE)) & 0xfffffffe))
+#define SET_TEST_MODE1(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 1) | ((REG32(ADR_TEST_MODE)) & 0xfffffffd))
+#define SET_TEST_MODE2(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 2) | ((REG32(ADR_TEST_MODE)) & 0xfffffffb))
+#define SET_TEST_MODE3(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 3) | ((REG32(ADR_TEST_MODE)) & 0xfffffff7))
+#define SET_TEST_MODE4(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 4) | ((REG32(ADR_TEST_MODE)) & 0xffffffef))
+#define SET_TEST_MODE_ALL(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 5) | ((REG32(ADR_TEST_MODE)) & 0xffffffdf))
+#define SET_WDT_INIT(_VAL_) (REG32(ADR_BOOT_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_BOOT_INFO)) & 0xfffffffe))
+#define SET_SD_HOST_INIT(_VAL_) (REG32(ADR_BOOT_INFO)) = (((_VAL_) << 1) | ((REG32(ADR_BOOT_INFO)) & 0xfffffffd))
+#define SET_ALLOW_SD_RESET(_VAL_) (REG32(ADR_SD_INIT_CFG)) = (((_VAL_) << 0) | ((REG32(ADR_SD_INIT_CFG)) & 0xfffffffe))
+#define SET_UART_NRTS(_VAL_) (REG32(ADR_SPARE_UART_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_SPARE_UART_INFO)) & 0xfffffffe))
+#define SET_UART_NCTS(_VAL_) (REG32(ADR_SPARE_UART_INFO)) = (((_VAL_) << 1) | ((REG32(ADR_SPARE_UART_INFO)) & 0xfffffffd))
+#define SET_TU0_TM_INIT_VALUE(_VAL_) (REG32(ADR_TU0_MICROSECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0xffff0000))
+#define SET_TU0_TM_MODE(_VAL_) (REG32(ADR_TU0_MICROSECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0xfffeffff))
+#define SET_TU0_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TU0_MICROSECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0xfffdffff))
+#define SET_TU0_TM_INT_MASK(_VAL_) (REG32(ADR_TU0_MICROSECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0xfffbffff))
+#define SET_TU0_TM_CUR_VALUE(_VAL_) (REG32(ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE)) & 0xffff0000))
+#define SET_TU1_TM_INIT_VALUE(_VAL_) (REG32(ADR_TU1_MICROSECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0xffff0000))
+#define SET_TU1_TM_MODE(_VAL_) (REG32(ADR_TU1_MICROSECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0xfffeffff))
+#define SET_TU1_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TU1_MICROSECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0xfffdffff))
+#define SET_TU1_TM_INT_MASK(_VAL_) (REG32(ADR_TU1_MICROSECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0xfffbffff))
+#define SET_TU1_TM_CUR_VALUE(_VAL_) (REG32(ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE)) & 0xffff0000))
+#define SET_TU2_TM_INIT_VALUE(_VAL_) (REG32(ADR_TU2_MICROSECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0xffff0000))
+#define SET_TU2_TM_MODE(_VAL_) (REG32(ADR_TU2_MICROSECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0xfffeffff))
+#define SET_TU2_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TU2_MICROSECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0xfffdffff))
+#define SET_TU2_TM_INT_MASK(_VAL_) (REG32(ADR_TU2_MICROSECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0xfffbffff))
+#define SET_TU2_TM_CUR_VALUE(_VAL_) (REG32(ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE)) & 0xffff0000))
+#define SET_TU3_TM_INIT_VALUE(_VAL_) (REG32(ADR_TU3_MICROSECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0xffff0000))
+#define SET_TU3_TM_MODE(_VAL_) (REG32(ADR_TU3_MICROSECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0xfffeffff))
+#define SET_TU3_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TU3_MICROSECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0xfffdffff))
+#define SET_TU3_TM_INT_MASK(_VAL_) (REG32(ADR_TU3_MICROSECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0xfffbffff))
+#define SET_TU3_TM_CUR_VALUE(_VAL_) (REG32(ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE)) & 0xffff0000))
+#define SET_TM0_TM_INIT_VALUE(_VAL_) (REG32(ADR_TM0_MILISECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TM0_MILISECOND_TIMER)) & 0xffff0000))
+#define SET_TM0_TM_MODE(_VAL_) (REG32(ADR_TM0_MILISECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TM0_MILISECOND_TIMER)) & 0xfffeffff))
+#define SET_TM0_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TM0_MILISECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TM0_MILISECOND_TIMER)) & 0xfffdffff))
+#define SET_TM0_TM_INT_MASK(_VAL_) (REG32(ADR_TM0_MILISECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TM0_MILISECOND_TIMER)) & 0xfffbffff))
+#define SET_TM0_TM_CUR_VALUE(_VAL_) (REG32(ADR_TM0_CURRENT_MILISECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TM0_CURRENT_MILISECOND_TIME_VALUE)) & 0xffff0000))
+#define SET_TM1_TM_INIT_VALUE(_VAL_) (REG32(ADR_TM1_MILISECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TM1_MILISECOND_TIMER)) & 0xffff0000))
+#define SET_TM1_TM_MODE(_VAL_) (REG32(ADR_TM1_MILISECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TM1_MILISECOND_TIMER)) & 0xfffeffff))
+#define SET_TM1_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TM1_MILISECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TM1_MILISECOND_TIMER)) & 0xfffdffff))
+#define SET_TM1_TM_INT_MASK(_VAL_) (REG32(ADR_TM1_MILISECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TM1_MILISECOND_TIMER)) & 0xfffbffff))
+#define SET_TM1_TM_CUR_VALUE(_VAL_) (REG32(ADR_TM1_CURRENT_MILISECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TM1_CURRENT_MILISECOND_TIME_VALUE)) & 0xffff0000))
+#define SET_TM2_TM_INIT_VALUE(_VAL_) (REG32(ADR_TM2_MILISECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TM2_MILISECOND_TIMER)) & 0xffff0000))
+#define SET_TM2_TM_MODE(_VAL_) (REG32(ADR_TM2_MILISECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TM2_MILISECOND_TIMER)) & 0xfffeffff))
+#define SET_TM2_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TM2_MILISECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TM2_MILISECOND_TIMER)) & 0xfffdffff))
+#define SET_TM2_TM_INT_MASK(_VAL_) (REG32(ADR_TM2_MILISECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TM2_MILISECOND_TIMER)) & 0xfffbffff))
+#define SET_TM2_TM_CUR_VALUE(_VAL_) (REG32(ADR_TM2_CURRENT_MILISECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TM2_CURRENT_MILISECOND_TIME_VALUE)) & 0xffff0000))
+#define SET_TM3_TM_INIT_VALUE(_VAL_) (REG32(ADR_TM3_MILISECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TM3_MILISECOND_TIMER)) & 0xffff0000))
+#define SET_TM3_TM_MODE(_VAL_) (REG32(ADR_TM3_MILISECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TM3_MILISECOND_TIMER)) & 0xfffeffff))
+#define SET_TM3_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TM3_MILISECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TM3_MILISECOND_TIMER)) & 0xfffdffff))
+#define SET_TM3_TM_INT_MASK(_VAL_) (REG32(ADR_TM3_MILISECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TM3_MILISECOND_TIMER)) & 0xfffbffff))
+#define SET_TM3_TM_CUR_VALUE(_VAL_) (REG32(ADR_TM3_CURRENT_MILISECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TM3_CURRENT_MILISECOND_TIME_VALUE)) & 0xffff0000))
+#define SET_MCU_WDT_TIME_CNT(_VAL_) (REG32(ADR_MCU_WDOG_REG)) = (((_VAL_) << 0) | ((REG32(ADR_MCU_WDOG_REG)) & 0xffff0000))
+#define SET_MCU_WDT_STATUS(_VAL_) (REG32(ADR_MCU_WDOG_REG)) = (((_VAL_) << 17) | ((REG32(ADR_MCU_WDOG_REG)) & 0xfffdffff))
+#define SET_MCU_WDOG_ENA(_VAL_) (REG32(ADR_MCU_WDOG_REG)) = (((_VAL_) << 31) | ((REG32(ADR_MCU_WDOG_REG)) & 0x7fffffff))
+#define SET_SYS_WDT_TIME_CNT(_VAL_) (REG32(ADR_SYS_WDOG_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SYS_WDOG_REG)) & 0xffff0000))
+#define SET_SYS_WDT_STATUS(_VAL_) (REG32(ADR_SYS_WDOG_REG)) = (((_VAL_) << 17) | ((REG32(ADR_SYS_WDOG_REG)) & 0xfffdffff))
+#define SET_SYS_WDOG_ENA(_VAL_) (REG32(ADR_SYS_WDOG_REG)) = (((_VAL_) << 31) | ((REG32(ADR_SYS_WDOG_REG)) & 0x7fffffff))
+#define SET_XLNA_EN_O_OE(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 0) | ((REG32(ADR_PAD6)) & 0xfffffffe))
+#define SET_XLNA_EN_O_PE(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 1) | ((REG32(ADR_PAD6)) & 0xfffffffd))
+#define SET_PAD6_IE(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 3) | ((REG32(ADR_PAD6)) & 0xfffffff7))
+#define SET_PAD6_SEL_I(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 4) | ((REG32(ADR_PAD6)) & 0xffffffcf))
+#define SET_PAD6_OD(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 8) | ((REG32(ADR_PAD6)) & 0xfffffeff))
+#define SET_PAD6_SEL_O(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 12) | ((REG32(ADR_PAD6)) & 0xffffefff))
+#define SET_XLNA_EN_O_C(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 28) | ((REG32(ADR_PAD6)) & 0xefffffff))
+#define SET_WIFI_TX_SW_O_OE(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 0) | ((REG32(ADR_PAD7)) & 0xfffffffe))
+#define SET_WIFI_TX_SW_O_PE(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 1) | ((REG32(ADR_PAD7)) & 0xfffffffd))
+#define SET_PAD7_IE(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 3) | ((REG32(ADR_PAD7)) & 0xfffffff7))
+#define SET_PAD7_SEL_I(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 4) | ((REG32(ADR_PAD7)) & 0xffffffcf))
+#define SET_PAD7_OD(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 8) | ((REG32(ADR_PAD7)) & 0xfffffeff))
+#define SET_PAD7_SEL_O(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 12) | ((REG32(ADR_PAD7)) & 0xffffefff))
+#define SET_WIFI_TX_SW_O_C(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 28) | ((REG32(ADR_PAD7)) & 0xefffffff))
+#define SET_WIFI_RX_SW_O_OE(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 0) | ((REG32(ADR_PAD8)) & 0xfffffffe))
+#define SET_WIFI_RX_SW_O_PE(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 1) | ((REG32(ADR_PAD8)) & 0xfffffffd))
+#define SET_PAD8_IE(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 3) | ((REG32(ADR_PAD8)) & 0xfffffff7))
+#define SET_PAD8_SEL_I(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 4) | ((REG32(ADR_PAD8)) & 0xffffffcf))
+#define SET_PAD8_OD(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 8) | ((REG32(ADR_PAD8)) & 0xfffffeff))
+#define SET_WIFI_RX_SW_O_C(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 28) | ((REG32(ADR_PAD8)) & 0xefffffff))
+#define SET_BT_SW_O_OE(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 0) | ((REG32(ADR_PAD9)) & 0xfffffffe))
+#define SET_BT_SW_O_PE(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 1) | ((REG32(ADR_PAD9)) & 0xfffffffd))
+#define SET_PAD9_IE(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 3) | ((REG32(ADR_PAD9)) & 0xfffffff7))
+#define SET_PAD9_SEL_I(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 4) | ((REG32(ADR_PAD9)) & 0xffffffcf))
+#define SET_PAD9_OD(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 8) | ((REG32(ADR_PAD9)) & 0xfffffeff))
+#define SET_PAD9_SEL_O(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 12) | ((REG32(ADR_PAD9)) & 0xffffefff))
+#define SET_BT_SW_O_C(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 28) | ((REG32(ADR_PAD9)) & 0xefffffff))
+#define SET_XPA_EN_O_OE(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 0) | ((REG32(ADR_PAD11)) & 0xfffffffe))
+#define SET_XPA_EN_O_PE(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 1) | ((REG32(ADR_PAD11)) & 0xfffffffd))
+#define SET_PAD11_IE(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 3) | ((REG32(ADR_PAD11)) & 0xfffffff7))
+#define SET_PAD11_SEL_I(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 4) | ((REG32(ADR_PAD11)) & 0xffffffcf))
+#define SET_PAD11_OD(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 8) | ((REG32(ADR_PAD11)) & 0xfffffeff))
+#define SET_PAD11_SEL_O(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 12) | ((REG32(ADR_PAD11)) & 0xffffefff))
+#define SET_XPA_EN_O_C(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 28) | ((REG32(ADR_PAD11)) & 0xefffffff))
+#define SET_PAD15_OE(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 0) | ((REG32(ADR_PAD15)) & 0xfffffffe))
+#define SET_PAD15_PE(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 1) | ((REG32(ADR_PAD15)) & 0xfffffffd))
+#define SET_PAD15_DS(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 2) | ((REG32(ADR_PAD15)) & 0xfffffffb))
+#define SET_PAD15_IE(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 3) | ((REG32(ADR_PAD15)) & 0xfffffff7))
+#define SET_PAD15_SEL_I(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 4) | ((REG32(ADR_PAD15)) & 0xffffffcf))
+#define SET_PAD15_OD(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 8) | ((REG32(ADR_PAD15)) & 0xfffffeff))
+#define SET_PAD15_SEL_O(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 12) | ((REG32(ADR_PAD15)) & 0xffffefff))
+#define SET_TEST_1_ID(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 28) | ((REG32(ADR_PAD15)) & 0xefffffff))
+#define SET_PAD16_OE(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 0) | ((REG32(ADR_PAD16)) & 0xfffffffe))
+#define SET_PAD16_PE(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 1) | ((REG32(ADR_PAD16)) & 0xfffffffd))
+#define SET_PAD16_DS(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 2) | ((REG32(ADR_PAD16)) & 0xfffffffb))
+#define SET_PAD16_IE(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 3) | ((REG32(ADR_PAD16)) & 0xfffffff7))
+#define SET_PAD16_SEL_I(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 4) | ((REG32(ADR_PAD16)) & 0xffffffcf))
+#define SET_PAD16_OD(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 8) | ((REG32(ADR_PAD16)) & 0xfffffeff))
+#define SET_PAD16_SEL_O(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 12) | ((REG32(ADR_PAD16)) & 0xffffefff))
+#define SET_TEST_2_ID(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 28) | ((REG32(ADR_PAD16)) & 0xefffffff))
+#define SET_PAD17_OE(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 0) | ((REG32(ADR_PAD17)) & 0xfffffffe))
+#define SET_PAD17_PE(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 1) | ((REG32(ADR_PAD17)) & 0xfffffffd))
+#define SET_PAD17_DS(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 2) | ((REG32(ADR_PAD17)) & 0xfffffffb))
+#define SET_PAD17_IE(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 3) | ((REG32(ADR_PAD17)) & 0xfffffff7))
+#define SET_PAD17_SEL_I(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 4) | ((REG32(ADR_PAD17)) & 0xffffffcf))
+#define SET_PAD17_OD(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 8) | ((REG32(ADR_PAD17)) & 0xfffffeff))
+#define SET_PAD17_SEL_O(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 12) | ((REG32(ADR_PAD17)) & 0xffffefff))
+#define SET_TEST_3_ID(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 28) | ((REG32(ADR_PAD17)) & 0xefffffff))
+#define SET_PAD18_OE(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 0) | ((REG32(ADR_PAD18)) & 0xfffffffe))
+#define SET_PAD18_PE(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 1) | ((REG32(ADR_PAD18)) & 0xfffffffd))
+#define SET_PAD18_DS(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 2) | ((REG32(ADR_PAD18)) & 0xfffffffb))
+#define SET_PAD18_IE(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 3) | ((REG32(ADR_PAD18)) & 0xfffffff7))
+#define SET_PAD18_SEL_I(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 4) | ((REG32(ADR_PAD18)) & 0xffffffcf))
+#define SET_PAD18_OD(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 8) | ((REG32(ADR_PAD18)) & 0xfffffeff))
+#define SET_PAD18_SEL_O(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 12) | ((REG32(ADR_PAD18)) & 0xffffcfff))
+#define SET_TEST_4_ID(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 28) | ((REG32(ADR_PAD18)) & 0xefffffff))
+#define SET_PAD19_OE(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 0) | ((REG32(ADR_PAD19)) & 0xfffffffe))
+#define SET_PAD19_PE(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 1) | ((REG32(ADR_PAD19)) & 0xfffffffd))
+#define SET_PAD19_DS(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 2) | ((REG32(ADR_PAD19)) & 0xfffffffb))
+#define SET_PAD19_IE(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 3) | ((REG32(ADR_PAD19)) & 0xfffffff7))
+#define SET_PAD19_SEL_I(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 4) | ((REG32(ADR_PAD19)) & 0xffffffcf))
+#define SET_PAD19_OD(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 8) | ((REG32(ADR_PAD19)) & 0xfffffeff))
+#define SET_PAD19_SEL_O(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 12) | ((REG32(ADR_PAD19)) & 0xffff8fff))
+#define SET_SHORT_TO_20_ID(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 28) | ((REG32(ADR_PAD19)) & 0xefffffff))
+#define SET_PAD20_OE(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 0) | ((REG32(ADR_PAD20)) & 0xfffffffe))
+#define SET_PAD20_PE(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 1) | ((REG32(ADR_PAD20)) & 0xfffffffd))
+#define SET_PAD20_DS(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 2) | ((REG32(ADR_PAD20)) & 0xfffffffb))
+#define SET_PAD20_IE(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 3) | ((REG32(ADR_PAD20)) & 0xfffffff7))
+#define SET_PAD20_SEL_I(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 4) | ((REG32(ADR_PAD20)) & 0xffffff0f))
+#define SET_PAD20_OD(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 8) | ((REG32(ADR_PAD20)) & 0xfffffeff))
+#define SET_PAD20_SEL_O(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 12) | ((REG32(ADR_PAD20)) & 0xffffcfff))
+#define SET_STRAP0(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 27) | ((REG32(ADR_PAD20)) & 0xf7ffffff))
+#define SET_GPIO_TEST_1_ID(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 28) | ((REG32(ADR_PAD20)) & 0xefffffff))
+#define SET_PAD21_OE(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 0) | ((REG32(ADR_PAD21)) & 0xfffffffe))
+#define SET_PAD21_PE(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 1) | ((REG32(ADR_PAD21)) & 0xfffffffd))
+#define SET_PAD21_DS(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 2) | ((REG32(ADR_PAD21)) & 0xfffffffb))
+#define SET_PAD21_IE(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 3) | ((REG32(ADR_PAD21)) & 0xfffffff7))
+#define SET_PAD21_SEL_I(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 4) | ((REG32(ADR_PAD21)) & 0xffffff8f))
+#define SET_PAD21_OD(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 8) | ((REG32(ADR_PAD21)) & 0xfffffeff))
+#define SET_PAD21_SEL_O(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 12) | ((REG32(ADR_PAD21)) & 0xffffcfff))
+#define SET_STRAP3(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 27) | ((REG32(ADR_PAD21)) & 0xf7ffffff))
+#define SET_GPIO_TEST_2_ID(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 28) | ((REG32(ADR_PAD21)) & 0xefffffff))
+#define SET_PAD22_OE(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 0) | ((REG32(ADR_PAD22)) & 0xfffffffe))
+#define SET_PAD22_PE(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 1) | ((REG32(ADR_PAD22)) & 0xfffffffd))
+#define SET_PAD22_DS(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 2) | ((REG32(ADR_PAD22)) & 0xfffffffb))
+#define SET_PAD22_IE(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 3) | ((REG32(ADR_PAD22)) & 0xfffffff7))
+#define SET_PAD22_SEL_I(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 4) | ((REG32(ADR_PAD22)) & 0xffffff8f))
+#define SET_PAD22_OD(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 8) | ((REG32(ADR_PAD22)) & 0xfffffeff))
+#define SET_PAD22_SEL_O(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 12) | ((REG32(ADR_PAD22)) & 0xffff8fff))
+#define SET_PAD22_SEL_OE(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 20) | ((REG32(ADR_PAD22)) & 0xffefffff))
+#define SET_GPIO_TEST_3_ID(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 28) | ((REG32(ADR_PAD22)) & 0xefffffff))
+#define SET_PAD24_OE(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 0) | ((REG32(ADR_PAD24)) & 0xfffffffe))
+#define SET_PAD24_PE(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 1) | ((REG32(ADR_PAD24)) & 0xfffffffd))
+#define SET_PAD24_DS(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 2) | ((REG32(ADR_PAD24)) & 0xfffffffb))
+#define SET_PAD24_IE(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 3) | ((REG32(ADR_PAD24)) & 0xfffffff7))
+#define SET_PAD24_SEL_I(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 4) | ((REG32(ADR_PAD24)) & 0xffffffcf))
+#define SET_PAD24_OD(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 8) | ((REG32(ADR_PAD24)) & 0xfffffeff))
+#define SET_PAD24_SEL_O(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 12) | ((REG32(ADR_PAD24)) & 0xffff8fff))
+#define SET_GPIO_TEST_4_ID(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 28) | ((REG32(ADR_PAD24)) & 0xefffffff))
+#define SET_PAD25_OE(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 0) | ((REG32(ADR_PAD25)) & 0xfffffffe))
+#define SET_PAD25_PE(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 1) | ((REG32(ADR_PAD25)) & 0xfffffffd))
+#define SET_PAD25_DS(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 2) | ((REG32(ADR_PAD25)) & 0xfffffffb))
+#define SET_PAD25_IE(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 3) | ((REG32(ADR_PAD25)) & 0xfffffff7))
+#define SET_PAD25_SEL_I(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 4) | ((REG32(ADR_PAD25)) & 0xffffff8f))
+#define SET_PAD25_OD(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 8) | ((REG32(ADR_PAD25)) & 0xfffffeff))
+#define SET_PAD25_SEL_O(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 12) | ((REG32(ADR_PAD25)) & 0xffff8fff))
+#define SET_PAD25_SEL_OE(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 20) | ((REG32(ADR_PAD25)) & 0xffefffff))
+#define SET_STRAP1(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 27) | ((REG32(ADR_PAD25)) & 0xf7ffffff))
+#define SET_GPIO_1_ID(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 28) | ((REG32(ADR_PAD25)) & 0xefffffff))
+#define SET_PAD27_OE(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 0) | ((REG32(ADR_PAD27)) & 0xfffffffe))
+#define SET_PAD27_PE(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 1) | ((REG32(ADR_PAD27)) & 0xfffffffd))
+#define SET_PAD27_DS(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 2) | ((REG32(ADR_PAD27)) & 0xfffffffb))
+#define SET_PAD27_IE(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 3) | ((REG32(ADR_PAD27)) & 0xfffffff7))
+#define SET_PAD27_SEL_I(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 4) | ((REG32(ADR_PAD27)) & 0xffffff8f))
+#define SET_PAD27_OD(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 8) | ((REG32(ADR_PAD27)) & 0xfffffeff))
+#define SET_PAD27_SEL_O(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 12) | ((REG32(ADR_PAD27)) & 0xffff8fff))
+#define SET_GPIO_2_ID(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 28) | ((REG32(ADR_PAD27)) & 0xefffffff))
+#define SET_PAD28_OE(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 0) | ((REG32(ADR_PAD28)) & 0xfffffffe))
+#define SET_PAD28_PE(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 1) | ((REG32(ADR_PAD28)) & 0xfffffffd))
+#define SET_PAD28_DS(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 2) | ((REG32(ADR_PAD28)) & 0xfffffffb))
+#define SET_PAD28_IE(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 3) | ((REG32(ADR_PAD28)) & 0xfffffff7))
+#define SET_PAD28_SEL_I(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 4) | ((REG32(ADR_PAD28)) & 0xffffff8f))
+#define SET_PAD28_OD(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 8) | ((REG32(ADR_PAD28)) & 0xfffffeff))
+#define SET_PAD28_SEL_O(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 12) | ((REG32(ADR_PAD28)) & 0xffff0fff))
+#define SET_PAD28_SEL_OE(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 20) | ((REG32(ADR_PAD28)) & 0xffefffff))
+#define SET_GPIO_3_ID(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 28) | ((REG32(ADR_PAD28)) & 0xefffffff))
+#define SET_PAD29_OE(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 0) | ((REG32(ADR_PAD29)) & 0xfffffffe))
+#define SET_PAD29_PE(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 1) | ((REG32(ADR_PAD29)) & 0xfffffffd))
+#define SET_PAD29_DS(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 2) | ((REG32(ADR_PAD29)) & 0xfffffffb))
+#define SET_PAD29_IE(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 3) | ((REG32(ADR_PAD29)) & 0xfffffff7))
+#define SET_PAD29_SEL_I(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 4) | ((REG32(ADR_PAD29)) & 0xffffff8f))
+#define SET_PAD29_OD(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 8) | ((REG32(ADR_PAD29)) & 0xfffffeff))
+#define SET_PAD29_SEL_O(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 12) | ((REG32(ADR_PAD29)) & 0xffff8fff))
+#define SET_GPIO_TEST_5_ID(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 28) | ((REG32(ADR_PAD29)) & 0xefffffff))
+#define SET_PAD30_OE(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 0) | ((REG32(ADR_PAD30)) & 0xfffffffe))
+#define SET_PAD30_PE(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 1) | ((REG32(ADR_PAD30)) & 0xfffffffd))
+#define SET_PAD30_DS(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 2) | ((REG32(ADR_PAD30)) & 0xfffffffb))
+#define SET_PAD30_IE(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 3) | ((REG32(ADR_PAD30)) & 0xfffffff7))
+#define SET_PAD30_SEL_I(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 4) | ((REG32(ADR_PAD30)) & 0xffffffcf))
+#define SET_PAD30_OD(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 8) | ((REG32(ADR_PAD30)) & 0xfffffeff))
+#define SET_PAD30_SEL_O(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 12) | ((REG32(ADR_PAD30)) & 0xffffcfff))
+#define SET_TEST_6_ID(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 28) | ((REG32(ADR_PAD30)) & 0xefffffff))
+#define SET_PAD31_OE(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 0) | ((REG32(ADR_PAD31)) & 0xfffffffe))
+#define SET_PAD31_PE(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 1) | ((REG32(ADR_PAD31)) & 0xfffffffd))
+#define SET_PAD31_DS(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 2) | ((REG32(ADR_PAD31)) & 0xfffffffb))
+#define SET_PAD31_IE(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 3) | ((REG32(ADR_PAD31)) & 0xfffffff7))
+#define SET_PAD31_SEL_I(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 4) | ((REG32(ADR_PAD31)) & 0xffffffcf))
+#define SET_PAD31_OD(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 8) | ((REG32(ADR_PAD31)) & 0xfffffeff))
+#define SET_PAD31_SEL_O(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 12) | ((REG32(ADR_PAD31)) & 0xffffcfff))
+#define SET_TEST_7_ID(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 28) | ((REG32(ADR_PAD31)) & 0xefffffff))
+#define SET_PAD32_OE(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 0) | ((REG32(ADR_PAD32)) & 0xfffffffe))
+#define SET_PAD32_PE(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 1) | ((REG32(ADR_PAD32)) & 0xfffffffd))
+#define SET_PAD32_DS(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 2) | ((REG32(ADR_PAD32)) & 0xfffffffb))
+#define SET_PAD32_IE(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 3) | ((REG32(ADR_PAD32)) & 0xfffffff7))
+#define SET_PAD32_SEL_I(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 4) | ((REG32(ADR_PAD32)) & 0xffffffcf))
+#define SET_PAD32_OD(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 8) | ((REG32(ADR_PAD32)) & 0xfffffeff))
+#define SET_PAD32_SEL_O(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 12) | ((REG32(ADR_PAD32)) & 0xffffcfff))
+#define SET_TEST_8_ID(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 28) | ((REG32(ADR_PAD32)) & 0xefffffff))
+#define SET_PAD33_OE(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 0) | ((REG32(ADR_PAD33)) & 0xfffffffe))
+#define SET_PAD33_PE(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 1) | ((REG32(ADR_PAD33)) & 0xfffffffd))
+#define SET_PAD33_DS(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 2) | ((REG32(ADR_PAD33)) & 0xfffffffb))
+#define SET_PAD33_IE(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 3) | ((REG32(ADR_PAD33)) & 0xfffffff7))
+#define SET_PAD33_SEL_I(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 4) | ((REG32(ADR_PAD33)) & 0xffffffcf))
+#define SET_PAD33_OD(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 8) | ((REG32(ADR_PAD33)) & 0xfffffeff))
+#define SET_PAD33_SEL_O(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 12) | ((REG32(ADR_PAD33)) & 0xffffcfff))
+#define SET_TEST_9_ID(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 28) | ((REG32(ADR_PAD33)) & 0xefffffff))
+#define SET_PAD34_OE(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 0) | ((REG32(ADR_PAD34)) & 0xfffffffe))
+#define SET_PAD34_PE(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 1) | ((REG32(ADR_PAD34)) & 0xfffffffd))
+#define SET_PAD34_DS(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 2) | ((REG32(ADR_PAD34)) & 0xfffffffb))
+#define SET_PAD34_IE(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 3) | ((REG32(ADR_PAD34)) & 0xfffffff7))
+#define SET_PAD34_SEL_I(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 4) | ((REG32(ADR_PAD34)) & 0xffffffcf))
+#define SET_PAD34_OD(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 8) | ((REG32(ADR_PAD34)) & 0xfffffeff))
+#define SET_PAD34_SEL_O(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 12) | ((REG32(ADR_PAD34)) & 0xffffcfff))
+#define SET_TEST_10_ID(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 28) | ((REG32(ADR_PAD34)) & 0xefffffff))
+#define SET_PAD42_OE(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 0) | ((REG32(ADR_PAD42)) & 0xfffffffe))
+#define SET_PAD42_PE(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 1) | ((REG32(ADR_PAD42)) & 0xfffffffd))
+#define SET_PAD42_DS(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 2) | ((REG32(ADR_PAD42)) & 0xfffffffb))
+#define SET_PAD42_IE(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 3) | ((REG32(ADR_PAD42)) & 0xfffffff7))
+#define SET_PAD42_SEL_I(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 4) | ((REG32(ADR_PAD42)) & 0xffffffcf))
+#define SET_PAD42_OD(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 8) | ((REG32(ADR_PAD42)) & 0xfffffeff))
+#define SET_PAD42_SEL_O(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 12) | ((REG32(ADR_PAD42)) & 0xffffefff))
+#define SET_TEST_11_ID(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 28) | ((REG32(ADR_PAD42)) & 0xefffffff))
+#define SET_PAD43_OE(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 0) | ((REG32(ADR_PAD43)) & 0xfffffffe))
+#define SET_PAD43_PE(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 1) | ((REG32(ADR_PAD43)) & 0xfffffffd))
+#define SET_PAD43_DS(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 2) | ((REG32(ADR_PAD43)) & 0xfffffffb))
+#define SET_PAD43_IE(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 3) | ((REG32(ADR_PAD43)) & 0xfffffff7))
+#define SET_PAD43_SEL_I(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 4) | ((REG32(ADR_PAD43)) & 0xffffffcf))
+#define SET_PAD43_OD(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 8) | ((REG32(ADR_PAD43)) & 0xfffffeff))
+#define SET_PAD43_SEL_O(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 12) | ((REG32(ADR_PAD43)) & 0xffffefff))
+#define SET_TEST_12_ID(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 28) | ((REG32(ADR_PAD43)) & 0xefffffff))
+#define SET_PAD44_OE(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 0) | ((REG32(ADR_PAD44)) & 0xfffffffe))
+#define SET_PAD44_PE(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 1) | ((REG32(ADR_PAD44)) & 0xfffffffd))
+#define SET_PAD44_DS(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 2) | ((REG32(ADR_PAD44)) & 0xfffffffb))
+#define SET_PAD44_IE(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 3) | ((REG32(ADR_PAD44)) & 0xfffffff7))
+#define SET_PAD44_SEL_I(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 4) | ((REG32(ADR_PAD44)) & 0xffffffcf))
+#define SET_PAD44_OD(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 8) | ((REG32(ADR_PAD44)) & 0xfffffeff))
+#define SET_PAD44_SEL_O(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 12) | ((REG32(ADR_PAD44)) & 0xffffcfff))
+#define SET_TEST_13_ID(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 28) | ((REG32(ADR_PAD44)) & 0xefffffff))
+#define SET_PAD45_OE(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 0) | ((REG32(ADR_PAD45)) & 0xfffffffe))
+#define SET_PAD45_PE(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 1) | ((REG32(ADR_PAD45)) & 0xfffffffd))
+#define SET_PAD45_DS(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 2) | ((REG32(ADR_PAD45)) & 0xfffffffb))
+#define SET_PAD45_IE(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 3) | ((REG32(ADR_PAD45)) & 0xfffffff7))
+#define SET_PAD45_SEL_I(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 4) | ((REG32(ADR_PAD45)) & 0xffffffcf))
+#define SET_PAD45_OD(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 8) | ((REG32(ADR_PAD45)) & 0xfffffeff))
+#define SET_PAD45_SEL_O(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 12) | ((REG32(ADR_PAD45)) & 0xffffcfff))
+#define SET_TEST_14_ID(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 28) | ((REG32(ADR_PAD45)) & 0xefffffff))
+#define SET_PAD46_OE(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 0) | ((REG32(ADR_PAD46)) & 0xfffffffe))
+#define SET_PAD46_PE(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 1) | ((REG32(ADR_PAD46)) & 0xfffffffd))
+#define SET_PAD46_DS(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 2) | ((REG32(ADR_PAD46)) & 0xfffffffb))
+#define SET_PAD46_IE(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 3) | ((REG32(ADR_PAD46)) & 0xfffffff7))
+#define SET_PAD46_SEL_I(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 4) | ((REG32(ADR_PAD46)) & 0xffffffcf))
+#define SET_PAD46_OD(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 8) | ((REG32(ADR_PAD46)) & 0xfffffeff))
+#define SET_PAD46_SEL_O(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 12) | ((REG32(ADR_PAD46)) & 0xffffcfff))
+#define SET_TEST_15_ID(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 28) | ((REG32(ADR_PAD46)) & 0xefffffff))
+#define SET_PAD47_OE(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 0) | ((REG32(ADR_PAD47)) & 0xfffffffe))
+#define SET_PAD47_PE(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 1) | ((REG32(ADR_PAD47)) & 0xfffffffd))
+#define SET_PAD47_DS(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 2) | ((REG32(ADR_PAD47)) & 0xfffffffb))
+#define SET_PAD47_SEL_I(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 4) | ((REG32(ADR_PAD47)) & 0xffffffcf))
+#define SET_PAD47_OD(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 8) | ((REG32(ADR_PAD47)) & 0xfffffeff))
+#define SET_PAD47_SEL_O(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 12) | ((REG32(ADR_PAD47)) & 0xffffcfff))
+#define SET_PAD47_SEL_OE(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 20) | ((REG32(ADR_PAD47)) & 0xffefffff))
+#define SET_GPIO_9_ID(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 28) | ((REG32(ADR_PAD47)) & 0xefffffff))
+#define SET_PAD48_OE(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 0) | ((REG32(ADR_PAD48)) & 0xfffffffe))
+#define SET_PAD48_PE(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 1) | ((REG32(ADR_PAD48)) & 0xfffffffd))
+#define SET_PAD48_DS(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 2) | ((REG32(ADR_PAD48)) & 0xfffffffb))
+#define SET_PAD48_IE(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 3) | ((REG32(ADR_PAD48)) & 0xfffffff7))
+#define SET_PAD48_SEL_I(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 4) | ((REG32(ADR_PAD48)) & 0xffffff8f))
+#define SET_PAD48_OD(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 8) | ((REG32(ADR_PAD48)) & 0xfffffeff))
+#define SET_PAD48_PE_SEL(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 11) | ((REG32(ADR_PAD48)) & 0xfffff7ff))
+#define SET_PAD48_SEL_O(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 12) | ((REG32(ADR_PAD48)) & 0xffffcfff))
+#define SET_PAD48_SEL_OE(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 20) | ((REG32(ADR_PAD48)) & 0xffefffff))
+#define SET_GPIO_10_ID(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 28) | ((REG32(ADR_PAD48)) & 0xefffffff))
+#define SET_PAD49_OE(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 0) | ((REG32(ADR_PAD49)) & 0xfffffffe))
+#define SET_PAD49_PE(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 1) | ((REG32(ADR_PAD49)) & 0xfffffffd))
+#define SET_PAD49_DS(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 2) | ((REG32(ADR_PAD49)) & 0xfffffffb))
+#define SET_PAD49_IE(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 3) | ((REG32(ADR_PAD49)) & 0xfffffff7))
+#define SET_PAD49_SEL_I(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 4) | ((REG32(ADR_PAD49)) & 0xffffff8f))
+#define SET_PAD49_OD(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 8) | ((REG32(ADR_PAD49)) & 0xfffffeff))
+#define SET_PAD49_SEL_O(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 12) | ((REG32(ADR_PAD49)) & 0xffffcfff))
+#define SET_PAD49_SEL_OE(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 20) | ((REG32(ADR_PAD49)) & 0xffefffff))
+#define SET_GPIO_11_ID(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 28) | ((REG32(ADR_PAD49)) & 0xefffffff))
+#define SET_PAD50_OE(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 0) | ((REG32(ADR_PAD50)) & 0xfffffffe))
+#define SET_PAD50_PE(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 1) | ((REG32(ADR_PAD50)) & 0xfffffffd))
+#define SET_PAD50_DS(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 2) | ((REG32(ADR_PAD50)) & 0xfffffffb))
+#define SET_PAD50_IE(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 3) | ((REG32(ADR_PAD50)) & 0xfffffff7))
+#define SET_PAD50_SEL_I(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 4) | ((REG32(ADR_PAD50)) & 0xffffff8f))
+#define SET_PAD50_OD(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 8) | ((REG32(ADR_PAD50)) & 0xfffffeff))
+#define SET_PAD50_SEL_O(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 12) | ((REG32(ADR_PAD50)) & 0xffffcfff))
+#define SET_PAD50_SEL_OE(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 20) | ((REG32(ADR_PAD50)) & 0xffefffff))
+#define SET_GPIO_12_ID(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 28) | ((REG32(ADR_PAD50)) & 0xefffffff))
+#define SET_PAD51_OE(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 0) | ((REG32(ADR_PAD51)) & 0xfffffffe))
+#define SET_PAD51_PE(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 1) | ((REG32(ADR_PAD51)) & 0xfffffffd))
+#define SET_PAD51_DS(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 2) | ((REG32(ADR_PAD51)) & 0xfffffffb))
+#define SET_PAD51_IE(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 3) | ((REG32(ADR_PAD51)) & 0xfffffff7))
+#define SET_PAD51_SEL_I(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 4) | ((REG32(ADR_PAD51)) & 0xffffffcf))
+#define SET_PAD51_OD(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 8) | ((REG32(ADR_PAD51)) & 0xfffffeff))
+#define SET_PAD51_SEL_O(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 12) | ((REG32(ADR_PAD51)) & 0xffffefff))
+#define SET_PAD51_SEL_OE(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 20) | ((REG32(ADR_PAD51)) & 0xffefffff))
+#define SET_GPIO_13_ID(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 28) | ((REG32(ADR_PAD51)) & 0xefffffff))
+#define SET_PAD52_OE(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 0) | ((REG32(ADR_PAD52)) & 0xfffffffe))
+#define SET_PAD52_PE(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 1) | ((REG32(ADR_PAD52)) & 0xfffffffd))
+#define SET_PAD52_DS(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 2) | ((REG32(ADR_PAD52)) & 0xfffffffb))
+#define SET_PAD52_SEL_I(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 4) | ((REG32(ADR_PAD52)) & 0xffffffcf))
+#define SET_PAD52_OD(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 8) | ((REG32(ADR_PAD52)) & 0xfffffeff))
+#define SET_PAD52_SEL_O(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 12) | ((REG32(ADR_PAD52)) & 0xffffefff))
+#define SET_PAD52_SEL_OE(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 20) | ((REG32(ADR_PAD52)) & 0xffefffff))
+#define SET_GPIO_14_ID(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 28) | ((REG32(ADR_PAD52)) & 0xefffffff))
+#define SET_PAD53_OE(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 0) | ((REG32(ADR_PAD53)) & 0xfffffffe))
+#define SET_PAD53_PE(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 1) | ((REG32(ADR_PAD53)) & 0xfffffffd))
+#define SET_PAD53_DS(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 2) | ((REG32(ADR_PAD53)) & 0xfffffffb))
+#define SET_PAD53_IE(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 3) | ((REG32(ADR_PAD53)) & 0xfffffff7))
+#define SET_PAD53_SEL_I(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 4) | ((REG32(ADR_PAD53)) & 0xffffffcf))
+#define SET_PAD53_OD(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 8) | ((REG32(ADR_PAD53)) & 0xfffffeff))
+#define SET_PAD53_SEL_O(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 12) | ((REG32(ADR_PAD53)) & 0xffffefff))
+#define SET_JTAG_TMS_ID(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 28) | ((REG32(ADR_PAD53)) & 0xefffffff))
+#define SET_PAD54_OE(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 0) | ((REG32(ADR_PAD54)) & 0xfffffffe))
+#define SET_PAD54_PE(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 1) | ((REG32(ADR_PAD54)) & 0xfffffffd))
+#define SET_PAD54_DS(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 2) | ((REG32(ADR_PAD54)) & 0xfffffffb))
+#define SET_PAD54_OD(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 8) | ((REG32(ADR_PAD54)) & 0xfffffeff))
+#define SET_PAD54_SEL_O(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 12) | ((REG32(ADR_PAD54)) & 0xffffcfff))
+#define SET_JTAG_TCK_ID(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 28) | ((REG32(ADR_PAD54)) & 0xefffffff))
+#define SET_PAD56_PE(_VAL_) (REG32(ADR_PAD56)) = (((_VAL_) << 1) | ((REG32(ADR_PAD56)) & 0xfffffffd))
+#define SET_PAD56_DS(_VAL_) (REG32(ADR_PAD56)) = (((_VAL_) << 2) | ((REG32(ADR_PAD56)) & 0xfffffffb))
+#define SET_PAD56_SEL_I(_VAL_) (REG32(ADR_PAD56)) = (((_VAL_) << 4) | ((REG32(ADR_PAD56)) & 0xffffffef))
+#define SET_PAD56_OD(_VAL_) (REG32(ADR_PAD56)) = (((_VAL_) << 8) | ((REG32(ADR_PAD56)) & 0xfffffeff))
+#define SET_JTAG_TDI_ID(_VAL_) (REG32(ADR_PAD56)) = (((_VAL_) << 28) | ((REG32(ADR_PAD56)) & 0xefffffff))
+#define SET_PAD57_OE(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 0) | ((REG32(ADR_PAD57)) & 0xfffffffe))
+#define SET_PAD57_PE(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 1) | ((REG32(ADR_PAD57)) & 0xfffffffd))
+#define SET_PAD57_DS(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 2) | ((REG32(ADR_PAD57)) & 0xfffffffb))
+#define SET_PAD57_IE(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 3) | ((REG32(ADR_PAD57)) & 0xfffffff7))
+#define SET_PAD57_SEL_I(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 4) | ((REG32(ADR_PAD57)) & 0xffffffcf))
+#define SET_PAD57_OD(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 8) | ((REG32(ADR_PAD57)) & 0xfffffeff))
+#define SET_PAD57_SEL_O(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 12) | ((REG32(ADR_PAD57)) & 0xffffcfff))
+#define SET_PAD57_SEL_OE(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 20) | ((REG32(ADR_PAD57)) & 0xffefffff))
+#define SET_JTAG_TDO_ID(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 28) | ((REG32(ADR_PAD57)) & 0xefffffff))
+#define SET_PAD58_OE(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 0) | ((REG32(ADR_PAD58)) & 0xfffffffe))
+#define SET_PAD58_PE(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 1) | ((REG32(ADR_PAD58)) & 0xfffffffd))
+#define SET_PAD58_DS(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 2) | ((REG32(ADR_PAD58)) & 0xfffffffb))
+#define SET_PAD58_IE(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 3) | ((REG32(ADR_PAD58)) & 0xfffffff7))
+#define SET_PAD58_SEL_I(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 4) | ((REG32(ADR_PAD58)) & 0xffffffcf))
+#define SET_PAD58_OD(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 8) | ((REG32(ADR_PAD58)) & 0xfffffeff))
+#define SET_PAD58_SEL_O(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 12) | ((REG32(ADR_PAD58)) & 0xffffefff))
+#define SET_TEST_16_ID(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 28) | ((REG32(ADR_PAD58)) & 0xefffffff))
+#define SET_PAD59_OE(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 0) | ((REG32(ADR_PAD59)) & 0xfffffffe))
+#define SET_PAD59_PE(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 1) | ((REG32(ADR_PAD59)) & 0xfffffffd))
+#define SET_PAD59_DS(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 2) | ((REG32(ADR_PAD59)) & 0xfffffffb))
+#define SET_PAD59_IE(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 3) | ((REG32(ADR_PAD59)) & 0xfffffff7))
+#define SET_PAD59_SEL_I(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 4) | ((REG32(ADR_PAD59)) & 0xffffffcf))
+#define SET_PAD59_OD(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 8) | ((REG32(ADR_PAD59)) & 0xfffffeff))
+#define SET_PAD59_SEL_O(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 12) | ((REG32(ADR_PAD59)) & 0xffffefff))
+#define SET_TEST_17_ID(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 28) | ((REG32(ADR_PAD59)) & 0xefffffff))
+#define SET_PAD60_OE(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 0) | ((REG32(ADR_PAD60)) & 0xfffffffe))
+#define SET_PAD60_PE(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 1) | ((REG32(ADR_PAD60)) & 0xfffffffd))
+#define SET_PAD60_DS(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 2) | ((REG32(ADR_PAD60)) & 0xfffffffb))
+#define SET_PAD60_IE(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 3) | ((REG32(ADR_PAD60)) & 0xfffffff7))
+#define SET_PAD60_SEL_I(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 4) | ((REG32(ADR_PAD60)) & 0xffffffcf))
+#define SET_PAD60_OD(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 8) | ((REG32(ADR_PAD60)) & 0xfffffeff))
+#define SET_PAD60_SEL_O(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 12) | ((REG32(ADR_PAD60)) & 0xffffefff))
+#define SET_TEST_18_ID(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 28) | ((REG32(ADR_PAD60)) & 0xefffffff))
+#define SET_PAD61_OE(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 0) | ((REG32(ADR_PAD61)) & 0xfffffffe))
+#define SET_PAD61_PE(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 1) | ((REG32(ADR_PAD61)) & 0xfffffffd))
+#define SET_PAD61_DS(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 2) | ((REG32(ADR_PAD61)) & 0xfffffffb))
+#define SET_PAD61_IE(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 3) | ((REG32(ADR_PAD61)) & 0xfffffff7))
+#define SET_PAD61_SEL_I(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 4) | ((REG32(ADR_PAD61)) & 0xffffffef))
+#define SET_PAD61_OD(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 8) | ((REG32(ADR_PAD61)) & 0xfffffeff))
+#define SET_PAD61_SEL_O(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 12) | ((REG32(ADR_PAD61)) & 0xffffcfff))
+#define SET_TEST_19_ID(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 28) | ((REG32(ADR_PAD61)) & 0xefffffff))
+#define SET_PAD62_OE(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 0) | ((REG32(ADR_PAD62)) & 0xfffffffe))
+#define SET_PAD62_PE(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 1) | ((REG32(ADR_PAD62)) & 0xfffffffd))
+#define SET_PAD62_DS(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 2) | ((REG32(ADR_PAD62)) & 0xfffffffb))
+#define SET_PAD62_IE(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 3) | ((REG32(ADR_PAD62)) & 0xfffffff7))
+#define SET_PAD62_SEL_I(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 4) | ((REG32(ADR_PAD62)) & 0xffffffef))
+#define SET_PAD62_OD(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 8) | ((REG32(ADR_PAD62)) & 0xfffffeff))
+#define SET_PAD62_SEL_O(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 12) | ((REG32(ADR_PAD62)) & 0xffffefff))
+#define SET_TEST_20_ID(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 28) | ((REG32(ADR_PAD62)) & 0xefffffff))
+#define SET_PAD64_OE(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 0) | ((REG32(ADR_PAD64)) & 0xfffffffe))
+#define SET_PAD64_PE(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 1) | ((REG32(ADR_PAD64)) & 0xfffffffd))
+#define SET_PAD64_DS(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 2) | ((REG32(ADR_PAD64)) & 0xfffffffb))
+#define SET_PAD64_IE(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 3) | ((REG32(ADR_PAD64)) & 0xfffffff7))
+#define SET_PAD64_SEL_I(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 4) | ((REG32(ADR_PAD64)) & 0xffffff8f))
+#define SET_PAD64_OD(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 8) | ((REG32(ADR_PAD64)) & 0xfffffeff))
+#define SET_PAD64_SEL_O(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 12) | ((REG32(ADR_PAD64)) & 0xffffcfff))
+#define SET_PAD64_SEL_OE(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 20) | ((REG32(ADR_PAD64)) & 0xffefffff))
+#define SET_GPIO_15_IP_ID(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 28) | ((REG32(ADR_PAD64)) & 0xefffffff))
+#define SET_PAD65_OE(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 0) | ((REG32(ADR_PAD65)) & 0xfffffffe))
+#define SET_PAD65_PE(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 1) | ((REG32(ADR_PAD65)) & 0xfffffffd))
+#define SET_PAD65_DS(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 2) | ((REG32(ADR_PAD65)) & 0xfffffffb))
+#define SET_PAD65_IE(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 3) | ((REG32(ADR_PAD65)) & 0xfffffff7))
+#define SET_PAD65_SEL_I(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 4) | ((REG32(ADR_PAD65)) & 0xffffff8f))
+#define SET_PAD65_OD(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 8) | ((REG32(ADR_PAD65)) & 0xfffffeff))
+#define SET_PAD65_SEL_O(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 12) | ((REG32(ADR_PAD65)) & 0xffffefff))
+#define SET_GPIO_TEST_7_IN_ID(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 28) | ((REG32(ADR_PAD65)) & 0xefffffff))
+#define SET_PAD66_OE(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 0) | ((REG32(ADR_PAD66)) & 0xfffffffe))
+#define SET_PAD66_PE(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 1) | ((REG32(ADR_PAD66)) & 0xfffffffd))
+#define SET_PAD66_DS(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 2) | ((REG32(ADR_PAD66)) & 0xfffffffb))
+#define SET_PAD66_IE(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 3) | ((REG32(ADR_PAD66)) & 0xfffffff7))
+#define SET_PAD66_SEL_I(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 4) | ((REG32(ADR_PAD66)) & 0xffffffcf))
+#define SET_PAD66_OD(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 8) | ((REG32(ADR_PAD66)) & 0xfffffeff))
+#define SET_PAD66_SEL_O(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 12) | ((REG32(ADR_PAD66)) & 0xffffcfff))
+#define SET_GPIO_17_QP_ID(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 28) | ((REG32(ADR_PAD66)) & 0xefffffff))
+#define SET_PAD68_OE(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 0) | ((REG32(ADR_PAD68)) & 0xfffffffe))
+#define SET_PAD68_PE(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 1) | ((REG32(ADR_PAD68)) & 0xfffffffd))
+#define SET_PAD68_DS(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 2) | ((REG32(ADR_PAD68)) & 0xfffffffb))
+#define SET_PAD68_IE(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 3) | ((REG32(ADR_PAD68)) & 0xfffffff7))
+#define SET_PAD68_OD(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 8) | ((REG32(ADR_PAD68)) & 0xfffffeff))
+#define SET_PAD68_SEL_O(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 12) | ((REG32(ADR_PAD68)) & 0xffffefff))
+#define SET_GPIO_19_ID(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 28) | ((REG32(ADR_PAD68)) & 0xefffffff))
+#define SET_PAD67_OE(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 0) | ((REG32(ADR_PAD67)) & 0xfffffffe))
+#define SET_PAD67_PE(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 1) | ((REG32(ADR_PAD67)) & 0xfffffffd))
+#define SET_PAD67_DS(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 2) | ((REG32(ADR_PAD67)) & 0xfffffffb))
+#define SET_PAD67_IE(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 3) | ((REG32(ADR_PAD67)) & 0xfffffff7))
+#define SET_PAD67_SEL_I(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 4) | ((REG32(ADR_PAD67)) & 0xffffff8f))
+#define SET_PAD67_OD(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 8) | ((REG32(ADR_PAD67)) & 0xfffffeff))
+#define SET_PAD67_SEL_O(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 12) | ((REG32(ADR_PAD67)) & 0xffffcfff))
+#define SET_GPIO_TEST_8_QN_ID(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 28) | ((REG32(ADR_PAD67)) & 0xefffffff))
+#define SET_PAD69_OE(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 0) | ((REG32(ADR_PAD69)) & 0xfffffffe))
+#define SET_PAD69_PE(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 1) | ((REG32(ADR_PAD69)) & 0xfffffffd))
+#define SET_PAD69_DS(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 2) | ((REG32(ADR_PAD69)) & 0xfffffffb))
+#define SET_PAD69_IE(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 3) | ((REG32(ADR_PAD69)) & 0xfffffff7))
+#define SET_PAD69_SEL_I(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 4) | ((REG32(ADR_PAD69)) & 0xffffffcf))
+#define SET_PAD69_OD(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 8) | ((REG32(ADR_PAD69)) & 0xfffffeff))
+#define SET_PAD69_SEL_O(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 12) | ((REG32(ADR_PAD69)) & 0xffffefff))
+#define SET_STRAP2(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 27) | ((REG32(ADR_PAD69)) & 0xf7ffffff))
+#define SET_GPIO_20_ID(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 28) | ((REG32(ADR_PAD69)) & 0xefffffff))
+#define SET_PAD70_OE(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 0) | ((REG32(ADR_PAD70)) & 0xfffffffe))
+#define SET_PAD70_PE(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 1) | ((REG32(ADR_PAD70)) & 0xfffffffd))
+#define SET_PAD70_DS(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 2) | ((REG32(ADR_PAD70)) & 0xfffffffb))
+#define SET_PAD70_IE(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 3) | ((REG32(ADR_PAD70)) & 0xfffffff7))
+#define SET_PAD70_SEL_I(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 4) | ((REG32(ADR_PAD70)) & 0xffffffcf))
+#define SET_PAD70_OD(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 8) | ((REG32(ADR_PAD70)) & 0xfffffeff))
+#define SET_PAD70_SEL_O(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 12) | ((REG32(ADR_PAD70)) & 0xffff8fff))
+#define SET_GPIO_21_ID(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 28) | ((REG32(ADR_PAD70)) & 0xefffffff))
+#define SET_PAD231_OE(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 0) | ((REG32(ADR_PAD231)) & 0xfffffffe))
+#define SET_PAD231_PE(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 1) | ((REG32(ADR_PAD231)) & 0xfffffffd))
+#define SET_PAD231_DS(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 2) | ((REG32(ADR_PAD231)) & 0xfffffffb))
+#define SET_PAD231_IE(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 3) | ((REG32(ADR_PAD231)) & 0xfffffff7))
+#define SET_PAD231_OD(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 8) | ((REG32(ADR_PAD231)) & 0xfffffeff))
+#define SET_PIN_40_OR_56_ID(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 28) | ((REG32(ADR_PAD231)) & 0xefffffff))
+#define SET_MP_PHY2RX_DATA__0_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 0) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffffe))
+#define SET_MP_PHY2RX_DATA__1_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 1) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffffd))
+#define SET_MP_TX_FF_RPTR__1_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 2) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffffb))
+#define SET_MP_RX_FF_WPTR__2_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 3) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffff7))
+#define SET_MP_RX_FF_WPTR__1_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 4) | ((REG32(ADR_PIN_SEL_0)) & 0xffffffef))
+#define SET_MP_RX_FF_WPTR__0_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 5) | ((REG32(ADR_PIN_SEL_0)) & 0xffffffdf))
+#define SET_MP_PHY2RX_DATA__2_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 6) | ((REG32(ADR_PIN_SEL_0)) & 0xffffffbf))
+#define SET_MP_PHY2RX_DATA__4_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 7) | ((REG32(ADR_PIN_SEL_0)) & 0xffffff7f))
+#define SET_I2CM_SDA_ID_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 8) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffcff))
+#define SET_CRYSTAL_OUT_REQ_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 10) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffbff))
+#define SET_MP_PHY2RX_DATA__5_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 11) | ((REG32(ADR_PIN_SEL_0)) & 0xfffff7ff))
+#define SET_MP_PHY2RX_DATA__3_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 12) | ((REG32(ADR_PIN_SEL_0)) & 0xffffefff))
+#define SET_UART_RXD_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 13) | ((REG32(ADR_PIN_SEL_0)) & 0xffff9fff))
+#define SET_MP_PHY2RX_DATA__6_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 15) | ((REG32(ADR_PIN_SEL_0)) & 0xffff7fff))
+#define SET_DAT_UART_NCTS_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 16) | ((REG32(ADR_PIN_SEL_0)) & 0xfffeffff))
+#define SET_GPIO_LOG_STOP_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 17) | ((REG32(ADR_PIN_SEL_0)) & 0xfff1ffff))
+#define SET_MP_TX_FF_RPTR__0_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 20) | ((REG32(ADR_PIN_SEL_0)) & 0xffefffff))
+#define SET_MP_PHY_RX_WRST_N_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 21) | ((REG32(ADR_PIN_SEL_0)) & 0xffdfffff))
+#define SET_EXT_32K_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 22) | ((REG32(ADR_PIN_SEL_0)) & 0xff3fffff))
+#define SET_MP_PHY2RX_DATA__7_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 24) | ((REG32(ADR_PIN_SEL_0)) & 0xfeffffff))
+#define SET_MP_TX_FF_RPTR__2_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 25) | ((REG32(ADR_PIN_SEL_0)) & 0xfdffffff))
+#define SET_PMUINT_WAKE_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 26) | ((REG32(ADR_PIN_SEL_0)) & 0xe3ffffff))
+#define SET_I2CM_SCL_ID_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 29) | ((REG32(ADR_PIN_SEL_0)) & 0xdfffffff))
+#define SET_MP_MRX_RX_EN_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 30) | ((REG32(ADR_PIN_SEL_0)) & 0xbfffffff))
+#define SET_DAT_UART_RXD_SEL_0(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 31) | ((REG32(ADR_PIN_SEL_0)) & 0x7fffffff))
+#define SET_DAT_UART_RXD_SEL_1(_VAL_) (REG32(ADR_PIN_SEL_1)) = (((_VAL_) << 0) | ((REG32(ADR_PIN_SEL_1)) & 0xfffffffe))
+#define SET_SPI_DI_SEL(_VAL_) (REG32(ADR_PIN_SEL_1)) = (((_VAL_) << 1) | ((REG32(ADR_PIN_SEL_1)) & 0xfffffffd))
+#define SET_IO_PORT_REG(_VAL_) (REG32(ADR_IO_PORT_REG)) = (((_VAL_) << 0) | ((REG32(ADR_IO_PORT_REG)) & 0xfffe0000))
+#define SET_MASK_RX_INT(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 0) | ((REG32(ADR_INT_MASK_REG)) & 0xfffffffe))
+#define SET_MASK_TX_INT(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 1) | ((REG32(ADR_INT_MASK_REG)) & 0xfffffffd))
+#define SET_MASK_SOC_SYSTEM_INT(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 2) | ((REG32(ADR_INT_MASK_REG)) & 0xfffffffb))
+#define SET_EDCA0_LOW_THR_INT_MASK(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 3) | ((REG32(ADR_INT_MASK_REG)) & 0xfffffff7))
+#define SET_EDCA1_LOW_THR_INT_MASK(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 4) | ((REG32(ADR_INT_MASK_REG)) & 0xffffffef))
+#define SET_EDCA2_LOW_THR_INT_MASK(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 5) | ((REG32(ADR_INT_MASK_REG)) & 0xffffffdf))
+#define SET_EDCA3_LOW_THR_INT_MASK(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 6) | ((REG32(ADR_INT_MASK_REG)) & 0xffffffbf))
+#define SET_TX_LIMIT_INT_MASK(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 7) | ((REG32(ADR_INT_MASK_REG)) & 0xffffff7f))
+#define SET_RX_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 0) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffffe))
+#define SET_TX_COMPLETE_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 1) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffffd))
+#define SET_SOC_SYSTEM_INT_STATUS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 2) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffffb))
+#define SET_EDCA0_LOW_THR_INT_STS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 3) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffff7))
+#define SET_EDCA1_LOW_THR_INT_STS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 4) | ((REG32(ADR_INT_STATUS_REG)) & 0xffffffef))
+#define SET_EDCA2_LOW_THR_INT_STS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 5) | ((REG32(ADR_INT_STATUS_REG)) & 0xffffffdf))
+#define SET_EDCA3_LOW_THR_INT_STS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 6) | ((REG32(ADR_INT_STATUS_REG)) & 0xffffffbf))
+#define SET_TX_LIMIT_INT_STS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 7) | ((REG32(ADR_INT_STATUS_REG)) & 0xffffff7f))
+#define SET_HOST_TRIGGERED_RX_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 8) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffeff))
+#define SET_HOST_TRIGGERED_TX_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 9) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffdff))
+#define SET_SOC_TRIGGER_RX_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 10) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffbff))
+#define SET_SOC_TRIGGER_TX_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 11) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffff7ff))
+#define SET_RDY_FOR_TX_RX(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 0) | ((REG32(ADR_FN1_STATUS_REG)) & 0xfffffffe))
+#define SET_RDY_FOR_FW_DOWNLOAD(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 1) | ((REG32(ADR_FN1_STATUS_REG)) & 0xfffffffd))
+#define SET_ILLEGAL_CMD_RESP_OPTION(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 2) | ((REG32(ADR_FN1_STATUS_REG)) & 0xfffffffb))
+#define SET_SDIO_TRX_DATA_SEQUENCE(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 3) | ((REG32(ADR_FN1_STATUS_REG)) & 0xfffffff7))
+#define SET_GPIO_INT_TRIGGER_OPTION(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 4) | ((REG32(ADR_FN1_STATUS_REG)) & 0xffffffef))
+#define SET_TRIGGER_FUNCTION_SETTING(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 5) | ((REG32(ADR_FN1_STATUS_REG)) & 0xffffff9f))
+#define SET_CMD52_ABORT_RESPONSE(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 7) | ((REG32(ADR_FN1_STATUS_REG)) & 0xffffff7f))
+#define SET_RX_PACKET_LENGTH(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 0) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xffff0000))
+#define SET_CARD_FW_DL_STATUS(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 16) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xff00ffff))
+#define SET_TX_RX_LOOP_BACK_TEST(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 24) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xfeffffff))
+#define SET_SDIO_LOOP_BACK_TEST(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 25) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xfdffffff))
+#define SET_CMD52_ABORT_ACTIVE(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 28) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xefffffff))
+#define SET_CMD52_RESET_ACTIVE(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 29) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xdfffffff))
+#define SET_SDIO_PARTIAL_RESET_ACTIVE(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 30) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xbfffffff))
+#define SET_SDIO_ALL_RESE_ACTIVE(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 31) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x7fffffff))
+#define SET_RX_PACKET_LENGTH2(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xffff0000))
+#define SET_RX_INT1(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 16) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xfffeffff))
+#define SET_TX_DONE(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 17) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xfffdffff))
+#define SET_HCI_TRX_FINISH(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 18) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xfffbffff))
+#define SET_ALLOCATE_STATUS(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 19) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xfff7ffff))
+#define SET_HCI_INPUT_FF_CNT(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 20) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xff0fffff))
+#define SET_HCI_OUTPUT_FF_CNT(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 24) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xe0ffffff))
+#define SET_AHB_HANG4(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 29) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xdfffffff))
+#define SET_HCI_IN_QUE_EMPTY(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 30) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xbfffffff))
+#define SET_SYSTEM_INT(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 31) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x7fffffff))
+#define SET_CARD_RCA_REG(_VAL_) (REG32(ADR_CARD_RCA_REG)) = (((_VAL_) << 0) | ((REG32(ADR_CARD_RCA_REG)) & 0xffff0000))
+#define SET_SDIO_FIFO_WR_THLD_REG(_VAL_) (REG32(ADR_SDIO_FIFO_WR_THLD_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_FIFO_WR_THLD_REG)) & 0xfffffe00))
+#define SET_SDIO_FIFO_WR_LIMIT_REG(_VAL_) (REG32(ADR_SDIO_FIFO_WR_LIMIT_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_FIFO_WR_LIMIT_REG)) & 0xfffffe00))
+#define SET_SDIO_TX_DATA_BATCH_SIZE_REG(_VAL_) (REG32(ADR_SDIO_TX_DATA_BATCH_SIZE_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_TX_DATA_BATCH_SIZE_REG)) & 0xfffffe00))
+#define SET_SDIO_THLD_FOR_CMD53RD_REG(_VAL_) (REG32(ADR_SDIO_THLD_FOR_CMD53RD_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_THLD_FOR_CMD53RD_REG)) & 0xfffffe00))
+#define SET_SDIO_RX_DATA_BATCH_SIZE_REG(_VAL_) (REG32(ADR_SDIO_RX_DATA_BATCH_SIZE_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_RX_DATA_BATCH_SIZE_REG)) & 0xfffffe00))
+#define SET_START_BYTE_VALUE(_VAL_) (REG32(ADR_SDIO_LOG_START_END_DATA_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_LOG_START_END_DATA_REG)) & 0xffffff00))
+#define SET_END_BYTE_VALUE(_VAL_) (REG32(ADR_SDIO_LOG_START_END_DATA_REG)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_LOG_START_END_DATA_REG)) & 0xffff00ff))
+#define SET_SDIO_BYTE_MODE_BATCH_SIZE_REG(_VAL_) (REG32(ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG)) & 0xffffff00))
+#define SET_SDIO_LAST_CMD_INDEX_REG(_VAL_) (REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) & 0xffffffc0))
+#define SET_SDIO_LAST_CMD_CRC_REG(_VAL_) (REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) & 0xffff80ff))
+#define SET_SDIO_LAST_CMD_ARG_REG(_VAL_) (REG32(ADR_SDIO_LAST_CMD_ARG_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_LAST_CMD_ARG_REG)) & 0x00000000))
+#define SET_SDIO_BUS_STATE_REG(_VAL_) (REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) & 0xffffffe0))
+#define SET_SDIO_BUSY_LONG_CNT(_VAL_) (REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) & 0x0000ffff))
+#define SET_SDIO_CARD_STATUS_REG(_VAL_) (REG32(ADR_SDIO_CARD_STATUS_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_CARD_STATUS_REG)) & 0x00000000))
+#define SET_R5_RESPONSE_FLAG(_VAL_) (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (((_VAL_) << 0) | ((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0xffffff00))
+#define SET_RESP_OUT_EDGE(_VAL_) (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (((_VAL_) << 8) | ((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0xfffffeff))
+#define SET_DAT_OUT_EDGE(_VAL_) (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (((_VAL_) << 9) | ((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0xfffffdff))
+#define SET_MCU_TO_SDIO_INFO_MASK(_VAL_) (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (((_VAL_) << 16) | ((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0xfffeffff))
+#define SET_INT_THROUGH_PIN(_VAL_) (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (((_VAL_) << 17) | ((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0xfffdffff))
+#define SET_WRITE_DATA(_VAL_) (REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) = (((_VAL_) << 0) | ((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0xffffff00))
+#define SET_WRITE_ADDRESS(_VAL_) (REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) = (((_VAL_) << 8) | ((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0xffff00ff))
+#define SET_READ_DATA(_VAL_) (REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) = (((_VAL_) << 16) | ((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0xff00ffff))
+#define SET_READ_ADDRESS(_VAL_) (REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) = (((_VAL_) << 24) | ((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0x00ffffff))
+#define SET_FN1_DMA_START_ADDR_REG(_VAL_) (REG32(ADR_FN1_DMA_START_ADDR_REG)) = (((_VAL_) << 0) | ((REG32(ADR_FN1_DMA_START_ADDR_REG)) & 0x00000000))
+#define SET_SDIO_TO_MCU_INFO(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 0) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xffffff00))
+#define SET_SDIO_PARTIAL_RESET(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 8) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xfffffeff))
+#define SET_SDIO_ALL_RESET(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 9) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xfffffdff))
+#define SET_PERI_MAC_ALL_RESET(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 10) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xfffffbff))
+#define SET_MAC_ALL_RESET(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 11) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xfffff7ff))
+#define SET_AHB_BRIDGE_RESET(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 12) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xffffefff))
+#define SET_IO_REG_PORT_REG(_VAL_) (REG32(ADR_IO_REG_PORT_REG)) = (((_VAL_) << 0) | ((REG32(ADR_IO_REG_PORT_REG)) & 0xfffe0000))
+#define SET_SDIO_FIFO_EMPTY_CNT(_VAL_) (REG32(ADR_SDIO_FIFO_ERROR_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_FIFO_ERROR_CNT)) & 0xffff0000))
+#define SET_SDIO_FIFO_FULL_CNT(_VAL_) (REG32(ADR_SDIO_FIFO_ERROR_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_FIFO_ERROR_CNT)) & 0x0000ffff))
+#define SET_SDIO_CRC7_ERROR_CNT(_VAL_) (REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) & 0xffff0000))
+#define SET_SDIO_CRC16_ERROR_CNT(_VAL_) (REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) & 0x0000ffff))
+#define SET_SDIO_RD_BLOCK_CNT(_VAL_) (REG32(ADR_SDIO_BLOCK_CNT_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_BLOCK_CNT_INFO)) & 0xfffffe00))
+#define SET_SDIO_WR_BLOCK_CNT(_VAL_) (REG32(ADR_SDIO_BLOCK_CNT_INFO)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_BLOCK_CNT_INFO)) & 0xfe00ffff))
+#define SET_CMD52_RD_ABORT_CNT(_VAL_) (REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) & 0xfff0ffff))
+#define SET_CMD52_WR_ABORT_CNT(_VAL_) (REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) = (((_VAL_) << 20) | ((REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) & 0xff0fffff))
+#define SET_SDIO_FIFO_WR_PTR_REG(_VAL_) (REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) & 0xffffff00))
+#define SET_SDIO_FIFO_RD_PTR_REG(_VAL_) (REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) = (((_VAL_) << 8) | ((REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) & 0xffff00ff))
+#define SET_SDIO_READ_DATA_CTRL(_VAL_) (REG32(ADR_TX_TIME_OUT_READ_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_TX_TIME_OUT_READ_CTRL)) & 0xfffeffff))
+#define SET_TX_SIZE_BEFORE_SHIFT(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xffffff00))
+#define SET_TX_SIZE_SHIFT_BITS(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xfffff8ff))
+#define SET_SDIO_TX_ALLOC_STATE(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 12) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xffffefff))
+#define SET_ALLOCATE_STATUS2(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xfffeffff))
+#define SET_NO_ALLOCATE_SEND_ERROR(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 17) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xfffdffff))
+#define SET_DOUBLE_ALLOCATE_ERROR(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 18) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xfffbffff))
+#define SET_TX_DONE_STATUS(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 19) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xfff7ffff))
+#define SET_AHB_HANG2(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 20) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xffefffff))
+#define SET_HCI_TRX_FINISH2(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 21) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xffdfffff))
+#define SET_INTR_RX(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 22) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xffbfffff))
+#define SET_HCI_INPUT_QUEUE_FULL(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 23) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xff7fffff))
+#define SET_ALLOCATESTATUS(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xfffffffe))
+#define SET_HCI_TRX_FINISH3(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 1) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xfffffffd))
+#define SET_HCI_IN_QUE_EMPTY2(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 2) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xfffffffb))
+#define SET_MTX_MNG_UPTHOLD_INT(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 3) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xfffffff7))
+#define SET_EDCA0_UPTHOLD_INT(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 4) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xffffffef))
+#define SET_EDCA1_UPTHOLD_INT(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 5) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xffffffdf))
+#define SET_EDCA2_UPTHOLD_INT(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 6) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xffffffbf))
+#define SET_EDCA3_UPTHOLD_INT(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 7) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xffffff7f))
+#define SET_TX_PAGE_REMAIN2(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xffff00ff))
+#define SET_TX_ID_REMAIN3(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xff80ffff))
+#define SET_HCI_OUTPUT_FF_CNT_0(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 23) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xff7fffff))
+#define SET_HCI_OUTPUT_FF_CNT2(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 24) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xf0ffffff))
+#define SET_HCI_INPUT_FF_CNT2(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 28) | ((REG32(ADR_SDIO_TX_INFORM)) & 0x0fffffff))
+#define SET_F1_BLOCK_SIZE_0_REG(_VAL_) (REG32(ADR_F1_BLOCK_SIZE_0_REG)) = (((_VAL_) << 0) | ((REG32(ADR_F1_BLOCK_SIZE_0_REG)) & 0xfffff000))
+#define SET_START_BYTE_VALUE2(_VAL_) (REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0xffffff00))
+#define SET_COMMAND_COUNTER(_VAL_) (REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0xffff00ff))
+#define SET_CMD_LOG_PART1(_VAL_) (REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0x0000ffff))
+#define SET_CMD_LOG_PART2(_VAL_) (REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) & 0xff000000))
+#define SET_END_BYTE_VALUE2(_VAL_) (REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) = (((_VAL_) << 24) | ((REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) & 0x00ffffff))
+#define SET_RX_PACKET_LENGTH3(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0xffff0000))
+#define SET_RX_INT3(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0xfffeffff))
+#define SET_TX_ID_REMAIN2(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REGISTER)) = (((_VAL_) << 17) | ((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0xff01ffff))
+#define SET_TX_PAGE_REMAIN3(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0x00ffffff))
+#define SET_CCCR_00H_REG(_VAL_) (REG32(ADR_CCCR_00H_REG)) = (((_VAL_) << 0) | ((REG32(ADR_CCCR_00H_REG)) & 0xffffff00))
+#define SET_CCCR_02H_REG(_VAL_) (REG32(ADR_CCCR_00H_REG)) = (((_VAL_) << 16) | ((REG32(ADR_CCCR_00H_REG)) & 0xff00ffff))
+#define SET_CCCR_03H_REG(_VAL_) (REG32(ADR_CCCR_00H_REG)) = (((_VAL_) << 24) | ((REG32(ADR_CCCR_00H_REG)) & 0x00ffffff))
+#define SET_CCCR_04H_REG(_VAL_) (REG32(ADR_CCCR_04H_REG)) = (((_VAL_) << 0) | ((REG32(ADR_CCCR_04H_REG)) & 0xffffff00))
+#define SET_CCCR_05H_REG(_VAL_) (REG32(ADR_CCCR_04H_REG)) = (((_VAL_) << 8) | ((REG32(ADR_CCCR_04H_REG)) & 0xffff00ff))
+#define SET_CCCR_06H_REG(_VAL_) (REG32(ADR_CCCR_04H_REG)) = (((_VAL_) << 16) | ((REG32(ADR_CCCR_04H_REG)) & 0xfff0ffff))
+#define SET_CCCR_07H_REG(_VAL_) (REG32(ADR_CCCR_04H_REG)) = (((_VAL_) << 24) | ((REG32(ADR_CCCR_04H_REG)) & 0x00ffffff))
+#define SET_SUPPORT_DIRECT_COMMAND_SDIO(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 0) | ((REG32(ADR_CCCR_08H_REG)) & 0xfffffffe))
+#define SET_SUPPORT_MULTIPLE_BLOCK_TRANSFER(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 1) | ((REG32(ADR_CCCR_08H_REG)) & 0xfffffffd))
+#define SET_SUPPORT_READ_WAIT(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 2) | ((REG32(ADR_CCCR_08H_REG)) & 0xfffffffb))
+#define SET_SUPPORT_BUS_CONTROL(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 3) | ((REG32(ADR_CCCR_08H_REG)) & 0xfffffff7))
+#define SET_SUPPORT_BLOCK_GAP_INTERRUPT(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 4) | ((REG32(ADR_CCCR_08H_REG)) & 0xffffffef))
+#define SET_ENABLE_BLOCK_GAP_INTERRUPT(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 5) | ((REG32(ADR_CCCR_08H_REG)) & 0xffffffdf))
+#define SET_LOW_SPEED_CARD(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 6) | ((REG32(ADR_CCCR_08H_REG)) & 0xffffffbf))
+#define SET_LOW_SPEED_CARD_4BIT(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 7) | ((REG32(ADR_CCCR_08H_REG)) & 0xffffff7f))
+#define SET_COMMON_CIS_PONTER(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 8) | ((REG32(ADR_CCCR_08H_REG)) & 0xfe0000ff))
+#define SET_SUPPORT_HIGH_SPEED(_VAL_) (REG32(ADR_CCCR_13H_REG)) = (((_VAL_) << 24) | ((REG32(ADR_CCCR_13H_REG)) & 0xfeffffff))
+#define SET_BSS(_VAL_) (REG32(ADR_CCCR_13H_REG)) = (((_VAL_) << 25) | ((REG32(ADR_CCCR_13H_REG)) & 0xf1ffffff))
+#define SET_FBR_100H_REG(_VAL_) (REG32(ADR_FBR_100H_REG)) = (((_VAL_) << 0) | ((REG32(ADR_FBR_100H_REG)) & 0xfffffff0))
+#define SET_CSASUPPORT(_VAL_) (REG32(ADR_FBR_100H_REG)) = (((_VAL_) << 6) | ((REG32(ADR_FBR_100H_REG)) & 0xffffffbf))
+#define SET_ENABLECSA(_VAL_) (REG32(ADR_FBR_100H_REG)) = (((_VAL_) << 7) | ((REG32(ADR_FBR_100H_REG)) & 0xffffff7f))
+#define SET_FBR_101H_REG(_VAL_) (REG32(ADR_FBR_100H_REG)) = (((_VAL_) << 8) | ((REG32(ADR_FBR_100H_REG)) & 0xffff00ff))
+#define SET_FBR_109H_REG(_VAL_) (REG32(ADR_FBR_109H_REG)) = (((_VAL_) << 8) | ((REG32(ADR_FBR_109H_REG)) & 0xfe0000ff))
+#define SET_F0_CIS_CONTENT_REG_31_0(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_0)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_0)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_63_32(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_1)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_1)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_95_64(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_2)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_2)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_127_96(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_3)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_3)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_159_128(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_4)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_4)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_191_160(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_5)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_5)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_223_192(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_6)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_6)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_255_224(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_7)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_7)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_287_256(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_8)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_8)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_319_288(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_9)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_9)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_351_320(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_10)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_10)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_383_352(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_11)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_11)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_415_384(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_12)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_12)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_447_416(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_13)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_13)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_479_448(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_14)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_14)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_511_480(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_15)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_15)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_31_0(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_0)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_0)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_63_32(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_1)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_1)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_95_64(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_2)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_2)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_127_96(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_3)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_3)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_159_128(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_4)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_4)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_191_160(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_5)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_5)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_223_192(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_6)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_6)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_255_224(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_7)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_7)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_287_256(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_8)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_8)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_319_288(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_9)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_9)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_351_320(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_10)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_10)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_383_352(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_11)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_11)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_415_384(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_12)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_12)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_447_416(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_13)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_13)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_479_448(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_14)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_14)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_511_480(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_15)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_15)) & 0x00000000))
+#define SET_SPI_MODE(_VAL_) (REG32(ADR_SPI_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_MODE)) & 0x00000000))
+#define SET_RX_QUOTA(_VAL_) (REG32(ADR_RX_QUOTA)) = (((_VAL_) << 0) | ((REG32(ADR_RX_QUOTA)) & 0xffff0000))
+#define SET_CONDI_NUM(_VAL_) (REG32(ADR_CONDITION_NUMBER)) = (((_VAL_) << 0) | ((REG32(ADR_CONDITION_NUMBER)) & 0xffffff00))
+#define SET_HOST_PATH(_VAL_) (REG32(ADR_HOST_PATH)) = (((_VAL_) << 0) | ((REG32(ADR_HOST_PATH)) & 0xfffffffe))
+#define SET_TX_SEG(_VAL_) (REG32(ADR_TX_SEG)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEG)) & 0x00000000))
+#define SET_BRST_MODE(_VAL_) (REG32(ADR_DEBUG_BURST_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_DEBUG_BURST_MODE)) & 0xfffffffe))
+#define SET_CLK_WIDTH(_VAL_) (REG32(ADR_SPI_TO_PHY_PARAM1)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_TO_PHY_PARAM1)) & 0xffff0000))
+#define SET_CSN_INTER(_VAL_) (REG32(ADR_SPI_TO_PHY_PARAM1)) = (((_VAL_) << 16) | ((REG32(ADR_SPI_TO_PHY_PARAM1)) & 0x0000ffff))
+#define SET_BACK_DLY(_VAL_) (REG32(ADR_SPI_TO_PHY_PARAM2)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_TO_PHY_PARAM2)) & 0xffff0000))
+#define SET_FRONT_DLY(_VAL_) (REG32(ADR_SPI_TO_PHY_PARAM2)) = (((_VAL_) << 16) | ((REG32(ADR_SPI_TO_PHY_PARAM2)) & 0x0000ffff))
+#define SET_RX_FIFO_FAIL(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 1) | ((REG32(ADR_SPI_STS)) & 0xfffffffd))
+#define SET_RX_HOST_FAIL(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 2) | ((REG32(ADR_SPI_STS)) & 0xfffffffb))
+#define SET_TX_FIFO_FAIL(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 3) | ((REG32(ADR_SPI_STS)) & 0xfffffff7))
+#define SET_TX_HOST_FAIL(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 4) | ((REG32(ADR_SPI_STS)) & 0xffffffef))
+#define SET_SPI_DOUBLE_ALLOC(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 5) | ((REG32(ADR_SPI_STS)) & 0xffffffdf))
+#define SET_SPI_TX_NO_ALLOC(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 6) | ((REG32(ADR_SPI_STS)) & 0xffffffbf))
+#define SET_RDATA_RDY(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 7) | ((REG32(ADR_SPI_STS)) & 0xffffff7f))
+#define SET_SPI_ALLOC_STATUS(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 8) | ((REG32(ADR_SPI_STS)) & 0xfffffeff))
+#define SET_SPI_DBG_WR_FIFO_FULL(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 9) | ((REG32(ADR_SPI_STS)) & 0xfffffdff))
+#define SET_RX_LEN(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 16) | ((REG32(ADR_SPI_STS)) & 0x0000ffff))
+#define SET_SPI_TX_ALLOC_SIZE_SHIFT_BITS(_VAL_) (REG32(ADR_TX_ALLOC_SET)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ALLOC_SET)) & 0xfffffff8))
+#define SET_SPI_HOST_TX_ALLOC_PKBUF(_VAL_) (REG32(ADR_TX_ALLOC_SET)) = (((_VAL_) << 8) | ((REG32(ADR_TX_ALLOC_SET)) & 0xfffffeff))
+#define SET_SPI_TX_ALLOC_SIZE(_VAL_) (REG32(ADR_TX_ALLOC)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ALLOC)) & 0xffffff00))
+#define SET_RD_DAT_CNT(_VAL_) (REG32(ADR_DBG_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_CNT)) & 0xffff0000))
+#define SET_RD_STS_CNT(_VAL_) (REG32(ADR_DBG_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_CNT)) & 0x0000ffff))
+#define SET_JUDGE_CNT(_VAL_) (REG32(ADR_DBG_CNT2)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_CNT2)) & 0xffff0000))
+#define SET_RD_STS_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT2)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_CNT2)) & 0xfffeffff))
+#define SET_RD_DAT_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT2)) = (((_VAL_) << 17) | ((REG32(ADR_DBG_CNT2)) & 0xfffdffff))
+#define SET_JUDGE_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT2)) = (((_VAL_) << 18) | ((REG32(ADR_DBG_CNT2)) & 0xfffbffff))
+#define SET_TX_DONE_CNT(_VAL_) (REG32(ADR_DBG_CNT3)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_CNT3)) & 0xffff0000))
+#define SET_TX_DISCARD_CNT(_VAL_) (REG32(ADR_DBG_CNT3)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_CNT3)) & 0x0000ffff))
+#define SET_TX_SET_CNT(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_CNT4)) & 0xffff0000))
+#define SET_TX_DISCARD_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_CNT4)) & 0xfffeffff))
+#define SET_TX_DONE_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 17) | ((REG32(ADR_DBG_CNT4)) & 0xfffdffff))
+#define SET_TX_SET_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 18) | ((REG32(ADR_DBG_CNT4)) & 0xfffbffff))
+#define SET_DAT_MODE_OFF(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 19) | ((REG32(ADR_DBG_CNT4)) & 0xfff7ffff))
+#define SET_TX_FIFO_RESIDUE(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 20) | ((REG32(ADR_DBG_CNT4)) & 0xff8fffff))
+#define SET_RX_FIFO_RESIDUE(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 24) | ((REG32(ADR_DBG_CNT4)) & 0xf8ffffff))
+#define SET_RX_RDY(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 0) | ((REG32(ADR_INT_TAG)) & 0xfffffffe))
+#define SET_SDIO_SYS_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 2) | ((REG32(ADR_INT_TAG)) & 0xfffffffb))
+#define SET_EDCA0_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 3) | ((REG32(ADR_INT_TAG)) & 0xfffffff7))
+#define SET_EDCA1_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 4) | ((REG32(ADR_INT_TAG)) & 0xffffffef))
+#define SET_EDCA2_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 5) | ((REG32(ADR_INT_TAG)) & 0xffffffdf))
+#define SET_EDCA3_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 6) | ((REG32(ADR_INT_TAG)) & 0xffffffbf))
+#define SET_TX_LIMIT_INT_IN(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 7) | ((REG32(ADR_INT_TAG)) & 0xffffff7f))
+#define SET_SPI_FN1(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 8) | ((REG32(ADR_INT_TAG)) & 0xffff80ff))
+#define SET_SPI_CLK_EN_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 15) | ((REG32(ADR_INT_TAG)) & 0xffff7fff))
+#define SET_SPI_HOST_MASK(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 16) | ((REG32(ADR_INT_TAG)) & 0xff00ffff))
+#define SET_I2CM_INT_WDONE(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_EN)) & 0xfffffffe))
+#define SET_I2CM_INT_RDONE(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 1) | ((REG32(ADR_I2CM_EN)) & 0xfffffffd))
+#define SET_I2CM_IDLE(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 2) | ((REG32(ADR_I2CM_EN)) & 0xfffffffb))
+#define SET_I2CM_INT_MISMATCH(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 3) | ((REG32(ADR_I2CM_EN)) & 0xfffffff7))
+#define SET_I2CM_PSCL(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 4) | ((REG32(ADR_I2CM_EN)) & 0xffffc00f))
+#define SET_I2CM_MANUAL_MODE(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 16) | ((REG32(ADR_I2CM_EN)) & 0xfffeffff))
+#define SET_I2CM_INT_WDATA_NEED(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 17) | ((REG32(ADR_I2CM_EN)) & 0xfffdffff))
+#define SET_I2CM_INT_RDATA_NEED(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 18) | ((REG32(ADR_I2CM_EN)) & 0xfffbffff))
+#define SET_I2CM_DEV_A(_VAL_) (REG32(ADR_I2CM_DEV_A)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_DEV_A)) & 0xfffffc00))
+#define SET_I2CM_DEV_A10B(_VAL_) (REG32(ADR_I2CM_DEV_A)) = (((_VAL_) << 14) | ((REG32(ADR_I2CM_DEV_A)) & 0xffffbfff))
+#define SET_I2CM_RX(_VAL_) (REG32(ADR_I2CM_DEV_A)) = (((_VAL_) << 15) | ((REG32(ADR_I2CM_DEV_A)) & 0xffff7fff))
+#define SET_I2CM_LEN(_VAL_) (REG32(ADR_I2CM_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_LEN)) & 0xffff0000))
+#define SET_I2CM_T_LEFT(_VAL_) (REG32(ADR_I2CM_LEN)) = (((_VAL_) << 16) | ((REG32(ADR_I2CM_LEN)) & 0xfff8ffff))
+#define SET_I2CM_R_GET(_VAL_) (REG32(ADR_I2CM_LEN)) = (((_VAL_) << 24) | ((REG32(ADR_I2CM_LEN)) & 0xf8ffffff))
+#define SET_I2CM_WDAT(_VAL_) (REG32(ADR_I2CM_WDAT)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_WDAT)) & 0x00000000))
+#define SET_I2CM_RDAT(_VAL_) (REG32(ADR_I2CM_RDAT)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_RDAT)) & 0x00000000))
+#define SET_I2CM_SR_LEN(_VAL_) (REG32(ADR_I2CM_EN_2)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_EN_2)) & 0xffff0000))
+#define SET_I2CM_SR_RX(_VAL_) (REG32(ADR_I2CM_EN_2)) = (((_VAL_) << 16) | ((REG32(ADR_I2CM_EN_2)) & 0xfffeffff))
+#define SET_I2CM_REPEAT_START(_VAL_) (REG32(ADR_I2CM_EN_2)) = (((_VAL_) << 17) | ((REG32(ADR_I2CM_EN_2)) & 0xfffdffff))
+#define SET_UART_DATA(_VAL_) (REG32(ADR_UART_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_UART_DATA)) & 0xffffff00))
+#define SET_DATA_RDY_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 0) | ((REG32(ADR_UART_IER)) & 0xfffffffe))
+#define SET_THR_EMPTY_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 1) | ((REG32(ADR_UART_IER)) & 0xfffffffd))
+#define SET_RX_LINESTS_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 2) | ((REG32(ADR_UART_IER)) & 0xfffffffb))
+#define SET_MDM_STS_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 3) | ((REG32(ADR_UART_IER)) & 0xfffffff7))
+#define SET_DMA_RXEND_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 6) | ((REG32(ADR_UART_IER)) & 0xffffffbf))
+#define SET_DMA_TXEND_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 7) | ((REG32(ADR_UART_IER)) & 0xffffff7f))
+#define SET_FIFO_EN(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_FCR)) & 0xfffffffe))
+#define SET_RXFIFO_RST(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 1) | ((REG32(ADR_UART_FCR)) & 0xfffffffd))
+#define SET_TXFIFO_RST(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 2) | ((REG32(ADR_UART_FCR)) & 0xfffffffb))
+#define SET_DMA_MODE(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 3) | ((REG32(ADR_UART_FCR)) & 0xfffffff7))
+#define SET_EN_AUTO_RTS(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_FCR)) & 0xffffffef))
+#define SET_EN_AUTO_CTS(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 5) | ((REG32(ADR_UART_FCR)) & 0xffffffdf))
+#define SET_RXFIFO_TRGLVL(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 6) | ((REG32(ADR_UART_FCR)) & 0xffffff3f))
+#define SET_WORD_LEN(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_LCR)) & 0xfffffffc))
+#define SET_STOP_BIT(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 2) | ((REG32(ADR_UART_LCR)) & 0xfffffffb))
+#define SET_PARITY_EN(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 3) | ((REG32(ADR_UART_LCR)) & 0xfffffff7))
+#define SET_EVEN_PARITY(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_LCR)) & 0xffffffef))
+#define SET_FORCE_PARITY(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 5) | ((REG32(ADR_UART_LCR)) & 0xffffffdf))
+#define SET_SET_BREAK(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 6) | ((REG32(ADR_UART_LCR)) & 0xffffffbf))
+#define SET_DLAB(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 7) | ((REG32(ADR_UART_LCR)) & 0xffffff7f))
+#define SET_DTR(_VAL_) (REG32(ADR_UART_MCR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_MCR)) & 0xfffffffe))
+#define SET_RTS(_VAL_) (REG32(ADR_UART_MCR)) = (((_VAL_) << 1) | ((REG32(ADR_UART_MCR)) & 0xfffffffd))
+#define SET_OUT_1(_VAL_) (REG32(ADR_UART_MCR)) = (((_VAL_) << 2) | ((REG32(ADR_UART_MCR)) & 0xfffffffb))
+#define SET_OUT_2(_VAL_) (REG32(ADR_UART_MCR)) = (((_VAL_) << 3) | ((REG32(ADR_UART_MCR)) & 0xfffffff7))
+#define SET_LOOP_BACK(_VAL_) (REG32(ADR_UART_MCR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_MCR)) & 0xffffffef))
+#define SET_DATA_RDY(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_LSR)) & 0xfffffffe))
+#define SET_OVERRUN_ERR(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 1) | ((REG32(ADR_UART_LSR)) & 0xfffffffd))
+#define SET_PARITY_ERR(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 2) | ((REG32(ADR_UART_LSR)) & 0xfffffffb))
+#define SET_FRAMING_ERR(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 3) | ((REG32(ADR_UART_LSR)) & 0xfffffff7))
+#define SET_BREAK_INT(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_LSR)) & 0xffffffef))
+#define SET_THR_EMPTY(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 5) | ((REG32(ADR_UART_LSR)) & 0xffffffdf))
+#define SET_TX_EMPTY(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 6) | ((REG32(ADR_UART_LSR)) & 0xffffffbf))
+#define SET_FIFODATA_ERR(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 7) | ((REG32(ADR_UART_LSR)) & 0xffffff7f))
+#define SET_DELTA_CTS(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_MSR)) & 0xfffffffe))
+#define SET_DELTA_DSR(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 1) | ((REG32(ADR_UART_MSR)) & 0xfffffffd))
+#define SET_TRAILEDGE_RI(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 2) | ((REG32(ADR_UART_MSR)) & 0xfffffffb))
+#define SET_DELTA_CD(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 3) | ((REG32(ADR_UART_MSR)) & 0xfffffff7))
+#define SET_CTS(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_MSR)) & 0xffffffef))
+#define SET_DSR(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 5) | ((REG32(ADR_UART_MSR)) & 0xffffffdf))
+#define SET_RI(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 6) | ((REG32(ADR_UART_MSR)) & 0xffffffbf))
+#define SET_CD(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 7) | ((REG32(ADR_UART_MSR)) & 0xffffff7f))
+#define SET_BRDC_DIV(_VAL_) (REG32(ADR_UART_SPR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_SPR)) & 0xffff0000))
+#define SET_RTHR_L(_VAL_) (REG32(ADR_UART_RTHR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_RTHR)) & 0xfffffff0))
+#define SET_RTHR_H(_VAL_) (REG32(ADR_UART_RTHR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_RTHR)) & 0xffffff0f))
+#define SET_INT_IDCODE(_VAL_) (REG32(ADR_UART_ISR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_ISR)) & 0xfffffff0))
+#define SET_FIFOS_ENABLED(_VAL_) (REG32(ADR_UART_ISR)) = (((_VAL_) << 6) | ((REG32(ADR_UART_ISR)) & 0xffffff3f))
+#define SET_DAT_UART_DATA(_VAL_) (REG32(ADR_DAT_UART_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_DATA)) & 0xffffff00))
+#define SET_DAT_DATA_RDY_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_IER)) & 0xfffffffe))
+#define SET_DAT_THR_EMPTY_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 1) | ((REG32(ADR_DAT_UART_IER)) & 0xfffffffd))
+#define SET_DAT_RX_LINESTS_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_IER)) & 0xfffffffb))
+#define SET_DAT_MDM_STS_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_IER)) & 0xfffffff7))
+#define SET_DAT_DMA_RXEND_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_IER)) & 0xffffffbf))
+#define SET_DAT_DMA_TXEND_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 7) | ((REG32(ADR_DAT_UART_IER)) & 0xffffff7f))
+#define SET_DAT_FIFO_EN(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_FCR)) & 0xfffffffe))
+#define SET_DAT_RXFIFO_RST(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 1) | ((REG32(ADR_DAT_UART_FCR)) & 0xfffffffd))
+#define SET_DAT_TXFIFO_RST(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_FCR)) & 0xfffffffb))
+#define SET_DAT_DMA_MODE(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_FCR)) & 0xfffffff7))
+#define SET_DAT_EN_AUTO_RTS(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_FCR)) & 0xffffffef))
+#define SET_DAT_EN_AUTO_CTS(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 5) | ((REG32(ADR_DAT_UART_FCR)) & 0xffffffdf))
+#define SET_DAT_RXFIFO_TRGLVL(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_FCR)) & 0xffffff3f))
+#define SET_DAT_WORD_LEN(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_LCR)) & 0xfffffffc))
+#define SET_DAT_STOP_BIT(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_LCR)) & 0xfffffffb))
+#define SET_DAT_PARITY_EN(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_LCR)) & 0xfffffff7))
+#define SET_DAT_EVEN_PARITY(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_LCR)) & 0xffffffef))
+#define SET_DAT_FORCE_PARITY(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 5) | ((REG32(ADR_DAT_UART_LCR)) & 0xffffffdf))
+#define SET_DAT_SET_BREAK(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_LCR)) & 0xffffffbf))
+#define SET_DAT_DLAB(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 7) | ((REG32(ADR_DAT_UART_LCR)) & 0xffffff7f))
+#define SET_DAT_DTR(_VAL_) (REG32(ADR_DAT_UART_MCR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_MCR)) & 0xfffffffe))
+#define SET_DAT_RTS(_VAL_) (REG32(ADR_DAT_UART_MCR)) = (((_VAL_) << 1) | ((REG32(ADR_DAT_UART_MCR)) & 0xfffffffd))
+#define SET_DAT_OUT_1(_VAL_) (REG32(ADR_DAT_UART_MCR)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_MCR)) & 0xfffffffb))
+#define SET_DAT_OUT_2(_VAL_) (REG32(ADR_DAT_UART_MCR)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_MCR)) & 0xfffffff7))
+#define SET_DAT_LOOP_BACK(_VAL_) (REG32(ADR_DAT_UART_MCR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_MCR)) & 0xffffffef))
+#define SET_DAT_DATA_RDY(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_LSR)) & 0xfffffffe))
+#define SET_DAT_OVERRUN_ERR(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 1) | ((REG32(ADR_DAT_UART_LSR)) & 0xfffffffd))
+#define SET_DAT_PARITY_ERR(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_LSR)) & 0xfffffffb))
+#define SET_DAT_FRAMING_ERR(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_LSR)) & 0xfffffff7))
+#define SET_DAT_BREAK_INT(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_LSR)) & 0xffffffef))
+#define SET_DAT_THR_EMPTY(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 5) | ((REG32(ADR_DAT_UART_LSR)) & 0xffffffdf))
+#define SET_DAT_TX_EMPTY(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_LSR)) & 0xffffffbf))
+#define SET_DAT_FIFODATA_ERR(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 7) | ((REG32(ADR_DAT_UART_LSR)) & 0xffffff7f))
+#define SET_DAT_DELTA_CTS(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_MSR)) & 0xfffffffe))
+#define SET_DAT_DELTA_DSR(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 1) | ((REG32(ADR_DAT_UART_MSR)) & 0xfffffffd))
+#define SET_DAT_TRAILEDGE_RI(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_MSR)) & 0xfffffffb))
+#define SET_DAT_DELTA_CD(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_MSR)) & 0xfffffff7))
+#define SET_DAT_CTS(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_MSR)) & 0xffffffef))
+#define SET_DAT_DSR(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 5) | ((REG32(ADR_DAT_UART_MSR)) & 0xffffffdf))
+#define SET_DAT_RI(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_MSR)) & 0xffffffbf))
+#define SET_DAT_CD(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 7) | ((REG32(ADR_DAT_UART_MSR)) & 0xffffff7f))
+#define SET_DAT_BRDC_DIV(_VAL_) (REG32(ADR_DAT_UART_SPR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_SPR)) & 0xffff0000))
+#define SET_DAT_RTHR_L(_VAL_) (REG32(ADR_DAT_UART_RTHR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_RTHR)) & 0xfffffff0))
+#define SET_DAT_RTHR_H(_VAL_) (REG32(ADR_DAT_UART_RTHR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_RTHR)) & 0xffffff0f))
+#define SET_DAT_INT_IDCODE(_VAL_) (REG32(ADR_DAT_UART_ISR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_ISR)) & 0xfffffff0))
+#define SET_DAT_FIFOS_ENABLED(_VAL_) (REG32(ADR_DAT_UART_ISR)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_ISR)) & 0xffffff3f))
+#define SET_MASK_TOP(_VAL_) (REG32(ADR_INT_MASK)) = (((_VAL_) << 0) | ((REG32(ADR_INT_MASK)) & 0x00000000))
+#define SET_INT_MODE(_VAL_) (REG32(ADR_INT_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_INT_MODE)) & 0x00000000))
+#define SET_IRQ_PHY_0(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 0) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffffe))
+#define SET_IRQ_PHY_1(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 1) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffffd))
+#define SET_IRQ_SDIO(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 2) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffffb))
+#define SET_IRQ_BEACON_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 3) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffff7))
+#define SET_IRQ_BEACON(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 4) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffffef))
+#define SET_IRQ_PRE_BEACON(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 5) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffffdf))
+#define SET_IRQ_EDCA0_TX_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 6) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffffbf))
+#define SET_IRQ_EDCA1_TX_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 7) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffff7f))
+#define SET_IRQ_EDCA2_TX_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 8) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffeff))
+#define SET_IRQ_EDCA3_TX_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 9) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffdff))
+#define SET_IRQ_EDCA4_TX_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 10) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffbff))
+#define SET_IRQ_BEACON_DTIM(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 12) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffefff))
+#define SET_IRQ_EDCA0_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 13) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffdfff))
+#define SET_IRQ_EDCA1_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 14) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffbfff))
+#define SET_IRQ_EDCA2_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 15) | ((REG32(ADR_INT_IRQ_STS)) & 0xffff7fff))
+#define SET_IRQ_EDCA3_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 16) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffeffff))
+#define SET_IRQ_FENCE_HIT_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 17) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffdffff))
+#define SET_IRQ_ILL_ADDR_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 18) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffbffff))
+#define SET_IRQ_MBOX(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 19) | ((REG32(ADR_INT_IRQ_STS)) & 0xfff7ffff))
+#define SET_IRQ_US_TIMER0(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 20) | ((REG32(ADR_INT_IRQ_STS)) & 0xffefffff))
+#define SET_IRQ_US_TIMER1(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 21) | ((REG32(ADR_INT_IRQ_STS)) & 0xffdfffff))
+#define SET_IRQ_US_TIMER2(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 22) | ((REG32(ADR_INT_IRQ_STS)) & 0xffbfffff))
+#define SET_IRQ_US_TIMER3(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 23) | ((REG32(ADR_INT_IRQ_STS)) & 0xff7fffff))
+#define SET_IRQ_MS_TIMER0(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 24) | ((REG32(ADR_INT_IRQ_STS)) & 0xfeffffff))
+#define SET_IRQ_MS_TIMER1(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 25) | ((REG32(ADR_INT_IRQ_STS)) & 0xfdffffff))
+#define SET_IRQ_MS_TIMER2(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 26) | ((REG32(ADR_INT_IRQ_STS)) & 0xfbffffff))
+#define SET_IRQ_MS_TIMER3(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 27) | ((REG32(ADR_INT_IRQ_STS)) & 0xf7ffffff))
+#define SET_IRQ_TX_LIMIT_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 28) | ((REG32(ADR_INT_IRQ_STS)) & 0xefffffff))
+#define SET_IRQ_DMA0(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 29) | ((REG32(ADR_INT_IRQ_STS)) & 0xdfffffff))
+#define SET_IRQ_CO_DMA(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 30) | ((REG32(ADR_INT_IRQ_STS)) & 0xbfffffff))
+#define SET_IRQ_PERI_GROUP(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 31) | ((REG32(ADR_INT_IRQ_STS)) & 0x7fffffff))
+#define SET_FIQ_STATUS(_VAL_) (REG32(ADR_INT_FIQ_STS)) = (((_VAL_) << 0) | ((REG32(ADR_INT_FIQ_STS)) & 0x00000000))
+#define SET_IRQ_RAW(_VAL_) (REG32(ADR_INT_IRQ_RAW)) = (((_VAL_) << 0) | ((REG32(ADR_INT_IRQ_RAW)) & 0x00000000))
+#define SET_FIQ_RAW(_VAL_) (REG32(ADR_INT_FIQ_RAW)) = (((_VAL_) << 0) | ((REG32(ADR_INT_FIQ_RAW)) & 0x00000000))
+#define SET_INT_PERI_MASK(_VAL_) (REG32(ADR_INT_PERI_MASK)) = (((_VAL_) << 0) | ((REG32(ADR_INT_PERI_MASK)) & 0x00000000))
+#define SET_PERI_RTC(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 0) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffffe))
+#define SET_IRQ_UART0_TX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 1) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffffd))
+#define SET_IRQ_UART0_RX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 2) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffffb))
+#define SET_PERI_GPI_2(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 3) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffff7))
+#define SET_IRQ_SPI_IPC(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 4) | ((REG32(ADR_INT_PERI_STS)) & 0xffffffef))
+#define SET_PERI_GPI_1_0(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 5) | ((REG32(ADR_INT_PERI_STS)) & 0xffffff9f))
+#define SET_SCRT_INT_1(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 7) | ((REG32(ADR_INT_PERI_STS)) & 0xffffff7f))
+#define SET_MMU_ALC_ERR(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 8) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffeff))
+#define SET_MMU_RLS_ERR(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 9) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffdff))
+#define SET_ID_MNG_INT_1(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 10) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffbff))
+#define SET_MBOX_INT_1(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 11) | ((REG32(ADR_INT_PERI_STS)) & 0xfffff7ff))
+#define SET_MBOX_INT_2(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 12) | ((REG32(ADR_INT_PERI_STS)) & 0xffffefff))
+#define SET_MBOX_INT_3(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 13) | ((REG32(ADR_INT_PERI_STS)) & 0xffffdfff))
+#define SET_HCI_INT_1(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 14) | ((REG32(ADR_INT_PERI_STS)) & 0xffffbfff))
+#define SET_UART_RX_TIMEOUT(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 15) | ((REG32(ADR_INT_PERI_STS)) & 0xffff7fff))
+#define SET_UART_MULTI_IRQ(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 16) | ((REG32(ADR_INT_PERI_STS)) & 0xfffeffff))
+#define SET_ID_MNG_INT_2(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 17) | ((REG32(ADR_INT_PERI_STS)) & 0xfffdffff))
+#define SET_DMN_NOHIT_INT(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 18) | ((REG32(ADR_INT_PERI_STS)) & 0xfffbffff))
+#define SET_ID_THOLD_RX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 19) | ((REG32(ADR_INT_PERI_STS)) & 0xfff7ffff))
+#define SET_ID_THOLD_TX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 20) | ((REG32(ADR_INT_PERI_STS)) & 0xffefffff))
+#define SET_ID_DOUBLE_RLS(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 21) | ((REG32(ADR_INT_PERI_STS)) & 0xffdfffff))
+#define SET_RX_ID_LEN_THOLD(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 22) | ((REG32(ADR_INT_PERI_STS)) & 0xffbfffff))
+#define SET_TX_ID_LEN_THOLD(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 23) | ((REG32(ADR_INT_PERI_STS)) & 0xff7fffff))
+#define SET_ALL_ID_LEN_THOLD(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 24) | ((REG32(ADR_INT_PERI_STS)) & 0xfeffffff))
+#define SET_DMN_MCU_INT(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 25) | ((REG32(ADR_INT_PERI_STS)) & 0xfdffffff))
+#define SET_IRQ_DAT_UART_TX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 26) | ((REG32(ADR_INT_PERI_STS)) & 0xfbffffff))
+#define SET_IRQ_DAT_UART_RX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 27) | ((REG32(ADR_INT_PERI_STS)) & 0xf7ffffff))
+#define SET_DAT_UART_RX_TIMEOUT(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 28) | ((REG32(ADR_INT_PERI_STS)) & 0xefffffff))
+#define SET_DAT_UART_MULTI_IRQ(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 29) | ((REG32(ADR_INT_PERI_STS)) & 0xdfffffff))
+#define SET_ALR_ABT_NOCHG_INT_IRQ(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 30) | ((REG32(ADR_INT_PERI_STS)) & 0xbfffffff))
+#define SET_TBLNEQ_MNGPKT_INT_IRQ(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 31) | ((REG32(ADR_INT_PERI_STS)) & 0x7fffffff))
+#define SET_INTR_PERI_RAW(_VAL_) (REG32(ADR_INT_PERI_RAW)) = (((_VAL_) << 0) | ((REG32(ADR_INT_PERI_RAW)) & 0x00000000))
+#define SET_INTR_GPI00_CFG(_VAL_) (REG32(ADR_INT_GPI_CFG)) = (((_VAL_) << 0) | ((REG32(ADR_INT_GPI_CFG)) & 0xfffffffc))
+#define SET_INTR_GPI01_CFG(_VAL_) (REG32(ADR_INT_GPI_CFG)) = (((_VAL_) << 2) | ((REG32(ADR_INT_GPI_CFG)) & 0xfffffff3))
+#define SET_SYS_RST_INT(_VAL_) (REG32(ADR_SYS_INT_FOR_HOST)) = (((_VAL_) << 0) | ((REG32(ADR_SYS_INT_FOR_HOST)) & 0xfffffffe))
+#define SET_SPI_IPC_ADDR(_VAL_) (REG32(ADR_SPI_IPC)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_IPC)) & 0x00000000))
+#define SET_SD_MASK_TOP(_VAL_) (REG32(ADR_SDIO_MASK)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_MASK)) & 0x00000000))
+#define SET_IRQ_PHY_0_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffffe))
+#define SET_IRQ_PHY_1_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 1) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffffd))
+#define SET_IRQ_SDIO_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 2) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffffb))
+#define SET_IRQ_BEACON_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 3) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffff7))
+#define SET_IRQ_BEACON_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 4) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffffef))
+#define SET_IRQ_PRE_BEACON_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 5) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffffdf))
+#define SET_IRQ_EDCA0_TX_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 6) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffffbf))
+#define SET_IRQ_EDCA1_TX_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 7) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffff7f))
+#define SET_IRQ_EDCA2_TX_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffeff))
+#define SET_IRQ_EDCA3_TX_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 9) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffdff))
+#define SET_IRQ_EDCA4_TX_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 10) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffbff))
+#define SET_IRQ_BEACON_DTIM_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 12) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffefff))
+#define SET_IRQ_EDCA0_LOWTHOLD_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 13) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffdfff))
+#define SET_IRQ_EDCA1_LOWTHOLD_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 14) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffbfff))
+#define SET_IRQ_EDCA2_LOWTHOLD_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 15) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffff7fff))
+#define SET_IRQ_EDCA3_LOWTHOLD_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffeffff))
+#define SET_IRQ_FENCE_HIT_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 17) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffdffff))
+#define SET_IRQ_ILL_ADDR_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 18) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffbffff))
+#define SET_IRQ_MBOX_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 19) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfff7ffff))
+#define SET_IRQ_US_TIMER0_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 20) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffefffff))
+#define SET_IRQ_US_TIMER1_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 21) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffdfffff))
+#define SET_IRQ_US_TIMER2_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 22) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffbfffff))
+#define SET_IRQ_US_TIMER3_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 23) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xff7fffff))
+#define SET_IRQ_MS_TIMER0_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 24) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfeffffff))
+#define SET_IRQ_MS_TIMER1_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 25) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfdffffff))
+#define SET_IRQ_MS_TIMER2_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 26) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfbffffff))
+#define SET_IRQ_MS_TIMER3_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 27) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xf7ffffff))
+#define SET_IRQ_TX_LIMIT_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 28) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xefffffff))
+#define SET_IRQ_DMA0_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 29) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xdfffffff))
+#define SET_IRQ_CO_DMA_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 30) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xbfffffff))
+#define SET_IRQ_PERI_GROUP_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 31) | ((REG32(ADR_SDIO_IRQ_STS)) & 0x7fffffff))
+#define SET_INT_PERI_MASK_SD(_VAL_) (REG32(ADR_SD_PERI_MASK)) = (((_VAL_) << 0) | ((REG32(ADR_SD_PERI_MASK)) & 0x00000000))
+#define SET_PERI_RTC_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 0) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffffe))
+#define SET_IRQ_UART0_TX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 1) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffffd))
+#define SET_IRQ_UART0_RX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 2) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffffb))
+#define SET_PERI_GPI_SD_2(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 3) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffff7))
+#define SET_IRQ_SPI_IPC_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 4) | ((REG32(ADR_SD_PERI_STS)) & 0xffffffef))
+#define SET_PERI_GPI_SD_1_0(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 5) | ((REG32(ADR_SD_PERI_STS)) & 0xffffff9f))
+#define SET_SCRT_INT_1_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 7) | ((REG32(ADR_SD_PERI_STS)) & 0xffffff7f))
+#define SET_MMU_ALC_ERR_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 8) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffeff))
+#define SET_MMU_RLS_ERR_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 9) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffdff))
+#define SET_ID_MNG_INT_1_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 10) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffbff))
+#define SET_MBOX_INT_1_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 11) | ((REG32(ADR_SD_PERI_STS)) & 0xfffff7ff))
+#define SET_MBOX_INT_2_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 12) | ((REG32(ADR_SD_PERI_STS)) & 0xffffefff))
+#define SET_MBOX_INT_3_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 13) | ((REG32(ADR_SD_PERI_STS)) & 0xffffdfff))
+#define SET_HCI_INT_1_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 14) | ((REG32(ADR_SD_PERI_STS)) & 0xffffbfff))
+#define SET_UART_RX_TIMEOUT_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 15) | ((REG32(ADR_SD_PERI_STS)) & 0xffff7fff))
+#define SET_UART_MULTI_IRQ_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 16) | ((REG32(ADR_SD_PERI_STS)) & 0xfffeffff))
+#define SET_ID_MNG_INT_2_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 17) | ((REG32(ADR_SD_PERI_STS)) & 0xfffdffff))
+#define SET_DMN_NOHIT_INT_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 18) | ((REG32(ADR_SD_PERI_STS)) & 0xfffbffff))
+#define SET_ID_THOLD_RX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 19) | ((REG32(ADR_SD_PERI_STS)) & 0xfff7ffff))
+#define SET_ID_THOLD_TX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 20) | ((REG32(ADR_SD_PERI_STS)) & 0xffefffff))
+#define SET_ID_DOUBLE_RLS_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 21) | ((REG32(ADR_SD_PERI_STS)) & 0xffdfffff))
+#define SET_RX_ID_LEN_THOLD_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 22) | ((REG32(ADR_SD_PERI_STS)) & 0xffbfffff))
+#define SET_TX_ID_LEN_THOLD_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 23) | ((REG32(ADR_SD_PERI_STS)) & 0xff7fffff))
+#define SET_ALL_ID_LEN_THOLD_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 24) | ((REG32(ADR_SD_PERI_STS)) & 0xfeffffff))
+#define SET_DMN_MCU_INT_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 25) | ((REG32(ADR_SD_PERI_STS)) & 0xfdffffff))
+#define SET_IRQ_DAT_UART_TX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 26) | ((REG32(ADR_SD_PERI_STS)) & 0xfbffffff))
+#define SET_IRQ_DAT_UART_RX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 27) | ((REG32(ADR_SD_PERI_STS)) & 0xf7ffffff))
+#define SET_DAT_UART_RX_TIMEOUT_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 28) | ((REG32(ADR_SD_PERI_STS)) & 0xefffffff))
+#define SET_DAT_UART_MULTI_IRQ_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 29) | ((REG32(ADR_SD_PERI_STS)) & 0xdfffffff))
+#define SET_ALR_ABT_NOCHG_INT_IRQ_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 30) | ((REG32(ADR_SD_PERI_STS)) & 0xbfffffff))
+#define SET_TBLNEQ_MNGPKT_INT_IRQ_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 31) | ((REG32(ADR_SD_PERI_STS)) & 0x7fffffff))
+#define SET_DBG_SPI_MODE(_VAL_) (REG32(ADR_DBG_SPI_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_SPI_MODE)) & 0x00000000))
+#define SET_DBG_RX_QUOTA(_VAL_) (REG32(ADR_DBG_RX_QUOTA)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_RX_QUOTA)) & 0xffff0000))
+#define SET_DBG_CONDI_NUM(_VAL_) (REG32(ADR_DBG_CONDITION_NUMBER)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_CONDITION_NUMBER)) & 0xffffff00))
+#define SET_DBG_HOST_PATH(_VAL_) (REG32(ADR_DBG_HOST_PATH)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_HOST_PATH)) & 0xfffffffe))
+#define SET_DBG_TX_SEG(_VAL_) (REG32(ADR_DBG_TX_SEG)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_TX_SEG)) & 0x00000000))
+#define SET_DBG_BRST_MODE(_VAL_) (REG32(ADR_DBG_DEBUG_BURST_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_DEBUG_BURST_MODE)) & 0xfffffffe))
+#define SET_DBG_CLK_WIDTH(_VAL_) (REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) & 0xffff0000))
+#define SET_DBG_CSN_INTER(_VAL_) (REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) & 0x0000ffff))
+#define SET_DBG_BACK_DLY(_VAL_) (REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) & 0xffff0000))
+#define SET_DBG_FRONT_DLY(_VAL_) (REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) & 0x0000ffff))
+#define SET_DBG_RX_FIFO_FAIL(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 1) | ((REG32(ADR_DBG_SPI_STS)) & 0xfffffffd))
+#define SET_DBG_RX_HOST_FAIL(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 2) | ((REG32(ADR_DBG_SPI_STS)) & 0xfffffffb))
+#define SET_DBG_TX_FIFO_FAIL(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 3) | ((REG32(ADR_DBG_SPI_STS)) & 0xfffffff7))
+#define SET_DBG_TX_HOST_FAIL(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 4) | ((REG32(ADR_DBG_SPI_STS)) & 0xffffffef))
+#define SET_DBG_SPI_DOUBLE_ALLOC(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 5) | ((REG32(ADR_DBG_SPI_STS)) & 0xffffffdf))
+#define SET_DBG_SPI_TX_NO_ALLOC(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 6) | ((REG32(ADR_DBG_SPI_STS)) & 0xffffffbf))
+#define SET_DBG_RDATA_RDY(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 7) | ((REG32(ADR_DBG_SPI_STS)) & 0xffffff7f))
+#define SET_DBG_SPI_ALLOC_STATUS(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 8) | ((REG32(ADR_DBG_SPI_STS)) & 0xfffffeff))
+#define SET_DBG_SPI_DBG_WR_FIFO_FULL(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 9) | ((REG32(ADR_DBG_SPI_STS)) & 0xfffffdff))
+#define SET_DBG_RX_LEN(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_SPI_STS)) & 0x0000ffff))
+#define SET_DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS(_VAL_) (REG32(ADR_DBG_TX_ALLOC_SET)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_TX_ALLOC_SET)) & 0xfffffff8))
+#define SET_DBG_SPI_HOST_TX_ALLOC_PKBUF(_VAL_) (REG32(ADR_DBG_TX_ALLOC_SET)) = (((_VAL_) << 8) | ((REG32(ADR_DBG_TX_ALLOC_SET)) & 0xfffffeff))
+#define SET_DBG_SPI_TX_ALLOC_SIZE(_VAL_) (REG32(ADR_DBG_TX_ALLOC)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_TX_ALLOC)) & 0xffffff00))
+#define SET_DBG_RD_DAT_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_DBG_CNT)) & 0xffff0000))
+#define SET_DBG_RD_STS_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_DBG_CNT)) & 0x0000ffff))
+#define SET_DBG_JUDGE_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT2)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_DBG_CNT2)) & 0xffff0000))
+#define SET_DBG_RD_STS_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT2)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_DBG_CNT2)) & 0xfffeffff))
+#define SET_DBG_RD_DAT_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT2)) = (((_VAL_) << 17) | ((REG32(ADR_DBG_DBG_CNT2)) & 0xfffdffff))
+#define SET_DBG_JUDGE_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT2)) = (((_VAL_) << 18) | ((REG32(ADR_DBG_DBG_CNT2)) & 0xfffbffff))
+#define SET_DBG_TX_DONE_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT3)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_DBG_CNT3)) & 0xffff0000))
+#define SET_DBG_TX_DISCARD_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT3)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_DBG_CNT3)) & 0x0000ffff))
+#define SET_DBG_TX_SET_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xffff0000))
+#define SET_DBG_TX_DISCARD_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xfffeffff))
+#define SET_DBG_TX_DONE_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 17) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xfffdffff))
+#define SET_DBG_TX_SET_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 18) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xfffbffff))
+#define SET_DBG_DAT_MODE_OFF(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 19) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xfff7ffff))
+#define SET_DBG_TX_FIFO_RESIDUE(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 20) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xff8fffff))
+#define SET_DBG_RX_FIFO_RESIDUE(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 24) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xf8ffffff))
+#define SET_DBG_RX_RDY(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_INT_TAG)) & 0xfffffffe))
+#define SET_DBG_SDIO_SYS_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 2) | ((REG32(ADR_DBG_INT_TAG)) & 0xfffffffb))
+#define SET_DBG_EDCA0_LOWTHOLD_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 3) | ((REG32(ADR_DBG_INT_TAG)) & 0xfffffff7))
+#define SET_DBG_EDCA1_LOWTHOLD_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 4) | ((REG32(ADR_DBG_INT_TAG)) & 0xffffffef))
+#define SET_DBG_EDCA2_LOWTHOLD_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 5) | ((REG32(ADR_DBG_INT_TAG)) & 0xffffffdf))
+#define SET_DBG_EDCA3_LOWTHOLD_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 6) | ((REG32(ADR_DBG_INT_TAG)) & 0xffffffbf))
+#define SET_DBG_TX_LIMIT_INT_IN(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 7) | ((REG32(ADR_DBG_INT_TAG)) & 0xffffff7f))
+#define SET_DBG_SPI_FN1(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 8) | ((REG32(ADR_DBG_INT_TAG)) & 0xffff80ff))
+#define SET_DBG_SPI_CLK_EN_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 15) | ((REG32(ADR_DBG_INT_TAG)) & 0xffff7fff))
+#define SET_DBG_SPI_HOST_MASK(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_INT_TAG)) & 0xff00ffff))
+#define SET_BOOT_ADDR(_VAL_) (REG32(ADR_BOOT_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_BOOT_ADDR)) & 0xff000000))
+#define SET_CHECK_SUM_FAIL(_VAL_) (REG32(ADR_BOOT_ADDR)) = (((_VAL_) << 31) | ((REG32(ADR_BOOT_ADDR)) & 0x7fffffff))
+#define SET_VERIFY_DATA(_VAL_) (REG32(ADR_VERIFY_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_VERIFY_DATA)) & 0x00000000))
+#define SET_FLASH_ADDR(_VAL_) (REG32(ADR_FLASH_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_FLASH_ADDR)) & 0xff000000))
+#define SET_FLASH_CMD_CLR(_VAL_) (REG32(ADR_FLASH_ADDR)) = (((_VAL_) << 28) | ((REG32(ADR_FLASH_ADDR)) & 0xefffffff))
+#define SET_FLASH_DMA_CLR(_VAL_) (REG32(ADR_FLASH_ADDR)) = (((_VAL_) << 29) | ((REG32(ADR_FLASH_ADDR)) & 0xdfffffff))
+#define SET_DMA_EN(_VAL_) (REG32(ADR_FLASH_ADDR)) = (((_VAL_) << 30) | ((REG32(ADR_FLASH_ADDR)) & 0xbfffffff))
+#define SET_DMA_BUSY(_VAL_) (REG32(ADR_FLASH_ADDR)) = (((_VAL_) << 31) | ((REG32(ADR_FLASH_ADDR)) & 0x7fffffff))
+#define SET_SRAM_ADDR(_VAL_) (REG32(ADR_SRAM_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_SRAM_ADDR)) & 0x00000000))
+#define SET_FLASH_DMA_LEN(_VAL_) (REG32(ADR_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_LEN)) & 0x00000000))
+#define SET_FLASH_FRONT_DLY(_VAL_) (REG32(ADR_SPI_PARAM)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_PARAM)) & 0xffff0000))
+#define SET_FLASH_BACK_DLY(_VAL_) (REG32(ADR_SPI_PARAM)) = (((_VAL_) << 16) | ((REG32(ADR_SPI_PARAM)) & 0x0000ffff))
+#define SET_FLASH_CLK_WIDTH(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_PARAM2)) & 0xffff0000))
+#define SET_SPI_BUSY(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 16) | ((REG32(ADR_SPI_PARAM2)) & 0xfffeffff))
+#define SET_FLS_REMAP(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 17) | ((REG32(ADR_SPI_PARAM2)) & 0xfffdffff))
+#define SET_PBUS_SWP(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 18) | ((REG32(ADR_SPI_PARAM2)) & 0xfffbffff))
+#define SET_BIT_MODE1(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 19) | ((REG32(ADR_SPI_PARAM2)) & 0xfff7ffff))
+#define SET_BIT_MODE2(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 20) | ((REG32(ADR_SPI_PARAM2)) & 0xffefffff))
+#define SET_BIT_MODE4(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 21) | ((REG32(ADR_SPI_PARAM2)) & 0xffdfffff))
+#define SET_BOOT_CHECK_SUM(_VAL_) (REG32(ADR_CHECK_SUM_RESULT)) = (((_VAL_) << 0) | ((REG32(ADR_CHECK_SUM_RESULT)) & 0x00000000))
+#define SET_CHECK_SUM_TAG(_VAL_) (REG32(ADR_CHECK_SUM_IN_FILE)) = (((_VAL_) << 0) | ((REG32(ADR_CHECK_SUM_IN_FILE)) & 0x00000000))
+#define SET_CMD_LEN(_VAL_) (REG32(ADR_COMMAND_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_COMMAND_LEN)) & 0xffff0000))
+#define SET_CMD_ADDR(_VAL_) (REG32(ADR_COMMAND_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_COMMAND_ADDR)) & 0x00000000))
+#define SET_DMA_ADR_SRC(_VAL_) (REG32(ADR_DMA_ADR_SRC)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_ADR_SRC)) & 0x00000000))
+#define SET_DMA_ADR_DST(_VAL_) (REG32(ADR_DMA_ADR_DST)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_ADR_DST)) & 0x00000000))
+#define SET_DMA_SRC_SIZE(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_CTRL)) & 0xfffffff8))
+#define SET_DMA_SRC_INC(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 3) | ((REG32(ADR_DMA_CTRL)) & 0xfffffff7))
+#define SET_DMA_DST_SIZE(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 4) | ((REG32(ADR_DMA_CTRL)) & 0xffffff8f))
+#define SET_DMA_DST_INC(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 7) | ((REG32(ADR_DMA_CTRL)) & 0xffffff7f))
+#define SET_DMA_FAST_FILL(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_DMA_CTRL)) & 0xfffffeff))
+#define SET_DMA_SDIO_KICK(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 12) | ((REG32(ADR_DMA_CTRL)) & 0xffffefff))
+#define SET_DMA_BADR_EN(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 13) | ((REG32(ADR_DMA_CTRL)) & 0xffffdfff))
+#define SET_DMA_LEN(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_DMA_CTRL)) & 0x0000ffff))
+#define SET_DMA_INT_MASK(_VAL_) (REG32(ADR_DMA_INT)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_INT)) & 0xfffffffe))
+#define SET_DMA_STS(_VAL_) (REG32(ADR_DMA_INT)) = (((_VAL_) << 8) | ((REG32(ADR_DMA_INT)) & 0xfffffeff))
+#define SET_DMA_FINISH(_VAL_) (REG32(ADR_DMA_INT)) = (((_VAL_) << 31) | ((REG32(ADR_DMA_INT)) & 0x7fffffff))
+#define SET_DMA_CONST(_VAL_) (REG32(ADR_DMA_FILL_CONST)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_FILL_CONST)) & 0x00000000))
+#define SET_SLEEP_WAKE_CNT(_VAL_) (REG32(ADR_PMU_0)) = (((_VAL_) << 0) | ((REG32(ADR_PMU_0)) & 0xff000000))
+#define SET_RG_DLDO_LEVEL(_VAL_) (REG32(ADR_PMU_0)) = (((_VAL_) << 24) | ((REG32(ADR_PMU_0)) & 0xf8ffffff))
+#define SET_RG_DLDO_BOOST_IQ(_VAL_) (REG32(ADR_PMU_0)) = (((_VAL_) << 27) | ((REG32(ADR_PMU_0)) & 0xf7ffffff))
+#define SET_RG_BUCK_LEVEL(_VAL_) (REG32(ADR_PMU_0)) = (((_VAL_) << 28) | ((REG32(ADR_PMU_0)) & 0x8fffffff))
+#define SET_RG_BUCK_VREF_SEL(_VAL_) (REG32(ADR_PMU_0)) = (((_VAL_) << 31) | ((REG32(ADR_PMU_0)) & 0x7fffffff))
+#define SET_RG_RTC_OSC_RES_SW_MANUAL(_VAL_) (REG32(ADR_PMU_1)) = (((_VAL_) << 0) | ((REG32(ADR_PMU_1)) & 0xfffffc00))
+#define SET_RG_RTC_OSC_RES_SW(_VAL_) (REG32(ADR_PMU_1)) = (((_VAL_) << 16) | ((REG32(ADR_PMU_1)) & 0xfc00ffff))
+#define SET_RTC_OSC_CAL_RES_RDY(_VAL_) (REG32(ADR_PMU_1)) = (((_VAL_) << 31) | ((REG32(ADR_PMU_1)) & 0x7fffffff))
+#define SET_RG_DCDC_MODE(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 0) | ((REG32(ADR_PMU_2)) & 0xfffffffe))
+#define SET_RG_BUCK_EN_PSM(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 4) | ((REG32(ADR_PMU_2)) & 0xffffffef))
+#define SET_RG_BUCK_PSM_VTH(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 8) | ((REG32(ADR_PMU_2)) & 0xfffffeff))
+#define SET_RG_RTC_OSC_RES_SW_MANUAL_EN(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 12) | ((REG32(ADR_PMU_2)) & 0xffffefff))
+#define SET_RG_RTC_RDY_DEGLITCH_TIMER(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 13) | ((REG32(ADR_PMU_2)) & 0xffff9fff))
+#define SET_RTC_CAL_ENA(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 16) | ((REG32(ADR_PMU_2)) & 0xfffeffff))
+#define SET_PMU_WAKE_TRIG_EVENT(_VAL_) (REG32(ADR_PMU_3)) = (((_VAL_) << 0) | ((REG32(ADR_PMU_3)) & 0xfffffffc))
+#define SET_DIGI_TOP_POR_MASK(_VAL_) (REG32(ADR_PMU_3)) = (((_VAL_) << 4) | ((REG32(ADR_PMU_3)) & 0xffffffef))
+#define SET_PMU_ENTER_SLEEP_MODE(_VAL_) (REG32(ADR_PMU_3)) = (((_VAL_) << 8) | ((REG32(ADR_PMU_3)) & 0xfffffeff))
+#define SET_RG_RTC_DUMMIES(_VAL_) (REG32(ADR_PMU_3)) = (((_VAL_) << 16) | ((REG32(ADR_PMU_3)) & 0x0000ffff))
+#define SET_RTC_EN(_VAL_) (REG32(ADR_RTC_1)) = (((_VAL_) << 0) | ((REG32(ADR_RTC_1)) & 0xfffffffe))
+#define SET_RTC_SRC(_VAL_) (REG32(ADR_RTC_1)) = (((_VAL_) << 1) | ((REG32(ADR_RTC_1)) & 0xfffffffd))
+#define SET_RTC_TICK_CNT(_VAL_) (REG32(ADR_RTC_1)) = (((_VAL_) << 16) | ((REG32(ADR_RTC_1)) & 0x8000ffff))
+#define SET_RTC_INT_SEC_MASK(_VAL_) (REG32(ADR_RTC_2)) = (((_VAL_) << 0) | ((REG32(ADR_RTC_2)) & 0xfffffffe))
+#define SET_RTC_INT_ALARM_MASK(_VAL_) (REG32(ADR_RTC_2)) = (((_VAL_) << 1) | ((REG32(ADR_RTC_2)) & 0xfffffffd))
+#define SET_RTC_INT_SEC(_VAL_) (REG32(ADR_RTC_2)) = (((_VAL_) << 16) | ((REG32(ADR_RTC_2)) & 0xfffeffff))
+#define SET_RTC_INT_ALARM(_VAL_) (REG32(ADR_RTC_2)) = (((_VAL_) << 17) | ((REG32(ADR_RTC_2)) & 0xfffdffff))
+#define SET_RTC_SEC_START_CNT(_VAL_) (REG32(ADR_RTC_3W)) = (((_VAL_) << 0) | ((REG32(ADR_RTC_3W)) & 0x00000000))
+#define SET_RTC_SEC_CNT(_VAL_) (REG32(ADR_RTC_3R)) = (((_VAL_) << 0) | ((REG32(ADR_RTC_3R)) & 0x00000000))
+#define SET_RTC_SEC_ALARM_VALUE(_VAL_) (REG32(ADR_RTC_4)) = (((_VAL_) << 0) | ((REG32(ADR_RTC_4)) & 0x00000000))
+#define SET_D2_DMA_ADR_SRC(_VAL_) (REG32(ADR_D2_DMA_ADR_SRC)) = (((_VAL_) << 0) | ((REG32(ADR_D2_DMA_ADR_SRC)) & 0x00000000))
+#define SET_D2_DMA_ADR_DST(_VAL_) (REG32(ADR_D2_DMA_ADR_DST)) = (((_VAL_) << 0) | ((REG32(ADR_D2_DMA_ADR_DST)) & 0x00000000))
+#define SET_D2_DMA_SRC_SIZE(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_D2_DMA_CTRL)) & 0xfffffff8))
+#define SET_D2_DMA_SRC_INC(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 3) | ((REG32(ADR_D2_DMA_CTRL)) & 0xfffffff7))
+#define SET_D2_DMA_DST_SIZE(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 4) | ((REG32(ADR_D2_DMA_CTRL)) & 0xffffff8f))
+#define SET_D2_DMA_DST_INC(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 7) | ((REG32(ADR_D2_DMA_CTRL)) & 0xffffff7f))
+#define SET_D2_DMA_FAST_FILL(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_D2_DMA_CTRL)) & 0xfffffeff))
+#define SET_D2_DMA_SDIO_KICK(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 12) | ((REG32(ADR_D2_DMA_CTRL)) & 0xffffefff))
+#define SET_D2_DMA_BADR_EN(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 13) | ((REG32(ADR_D2_DMA_CTRL)) & 0xffffdfff))
+#define SET_D2_DMA_LEN(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_D2_DMA_CTRL)) & 0x0000ffff))
+#define SET_D2_DMA_INT_MASK(_VAL_) (REG32(ADR_D2_DMA_INT)) = (((_VAL_) << 0) | ((REG32(ADR_D2_DMA_INT)) & 0xfffffffe))
+#define SET_D2_DMA_STS(_VAL_) (REG32(ADR_D2_DMA_INT)) = (((_VAL_) << 8) | ((REG32(ADR_D2_DMA_INT)) & 0xfffffeff))
+#define SET_D2_DMA_FINISH(_VAL_) (REG32(ADR_D2_DMA_INT)) = (((_VAL_) << 31) | ((REG32(ADR_D2_DMA_INT)) & 0x7fffffff))
+#define SET_D2_DMA_CONST(_VAL_) (REG32(ADR_D2_DMA_FILL_CONST)) = (((_VAL_) << 0) | ((REG32(ADR_D2_DMA_FILL_CONST)) & 0x00000000))
+#define SET_TRAP_UNKNOWN_TYPE(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 0) | ((REG32(ADR_CONTROL)) & 0xfffffffe))
+#define SET_TX_ON_DEMAND_ENA(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 1) | ((REG32(ADR_CONTROL)) & 0xfffffffd))
+#define SET_RX_2_HOST(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 2) | ((REG32(ADR_CONTROL)) & 0xfffffffb))
+#define SET_AUTO_SEQNO(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 3) | ((REG32(ADR_CONTROL)) & 0xfffffff7))
+#define SET_BYPASSS_TX_PARSER_ENCAP(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 4) | ((REG32(ADR_CONTROL)) & 0xffffffef))
+#define SET_HDR_STRIP(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 5) | ((REG32(ADR_CONTROL)) & 0xffffffdf))
+#define SET_ERP_PROTECT(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 6) | ((REG32(ADR_CONTROL)) & 0xffffff3f))
+#define SET_PRO_VER(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 8) | ((REG32(ADR_CONTROL)) & 0xfffffcff))
+#define SET_TXQ_ID0(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 12) | ((REG32(ADR_CONTROL)) & 0xffff8fff))
+#define SET_TXQ_ID1(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 16) | ((REG32(ADR_CONTROL)) & 0xfff8ffff))
+#define SET_TX_ETHER_TRAP_EN(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 20) | ((REG32(ADR_CONTROL)) & 0xffefffff))
+#define SET_RX_ETHER_TRAP_EN(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 21) | ((REG32(ADR_CONTROL)) & 0xffdfffff))
+#define SET_RX_NULL_TRAP_EN(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 22) | ((REG32(ADR_CONTROL)) & 0xffbfffff))
+#define SET_RX_GET_TX_QUEUE_EN(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 25) | ((REG32(ADR_CONTROL)) & 0xfdffffff))
+#define SET_HCI_INQ_SEL(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 26) | ((REG32(ADR_CONTROL)) & 0xfbffffff))
+#define SET_TRX_DEBUG_CNT_ENA(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 28) | ((REG32(ADR_CONTROL)) & 0xefffffff))
+#define SET_WAKE_SOON_WITH_SCK(_VAL_) (REG32(ADR_SDIO_WAKE_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_WAKE_MODE)) & 0xfffffffe))
+#define SET_TX_FLOW_CTRL(_VAL_) (REG32(ADR_TX_FLOW_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_FLOW_0)) & 0xffff0000))
+#define SET_TX_FLOW_MGMT(_VAL_) (REG32(ADR_TX_FLOW_0)) = (((_VAL_) << 16) | ((REG32(ADR_TX_FLOW_0)) & 0x0000ffff))
+#define SET_TX_FLOW_DATA(_VAL_) (REG32(ADR_TX_FLOW_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_FLOW_1)) & 0x00000000))
+#define SET_DOT11RTSTHRESHOLD(_VAL_) (REG32(ADR_THREASHOLD)) = (((_VAL_) << 16) | ((REG32(ADR_THREASHOLD)) & 0x0000ffff))
+#define SET_TXF_ID(_VAL_) (REG32(ADR_TXFID_INCREASE)) = (((_VAL_) << 0) | ((REG32(ADR_TXFID_INCREASE)) & 0xffffffc0))
+#define SET_SEQ_CTRL(_VAL_) (REG32(ADR_GLOBAL_SEQUENCE)) = (((_VAL_) << 0) | ((REG32(ADR_GLOBAL_SEQUENCE)) & 0xffff0000))
+#define SET_TX_PBOFFSET(_VAL_) (REG32(ADR_HCI_TX_RX_INFO_SIZE)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0xffffff00))
+#define SET_TX_INFO_SIZE(_VAL_) (REG32(ADR_HCI_TX_RX_INFO_SIZE)) = (((_VAL_) << 8) | ((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0xffff00ff))
+#define SET_RX_INFO_SIZE(_VAL_) (REG32(ADR_HCI_TX_RX_INFO_SIZE)) = (((_VAL_) << 16) | ((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0xff00ffff))
+#define SET_RX_LAST_PHY_SIZE(_VAL_) (REG32(ADR_HCI_TX_RX_INFO_SIZE)) = (((_VAL_) << 24) | ((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0x00ffffff))
+#define SET_TX_INFO_CLEAR_SIZE(_VAL_) (REG32(ADR_HCI_TX_INFO_CLEAR)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_TX_INFO_CLEAR)) & 0xffffffc0))
+#define SET_TX_INFO_CLEAR_ENABLE(_VAL_) (REG32(ADR_HCI_TX_INFO_CLEAR)) = (((_VAL_) << 8) | ((REG32(ADR_HCI_TX_INFO_CLEAR)) & 0xfffffeff))
+#define SET_TXTRAP_ETHTYPE1(_VAL_) (REG32(ADR_TX_ETHER_TYPE_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ETHER_TYPE_1)) & 0xffff0000))
+#define SET_TXTRAP_ETHTYPE0(_VAL_) (REG32(ADR_TX_ETHER_TYPE_1)) = (((_VAL_) << 16) | ((REG32(ADR_TX_ETHER_TYPE_1)) & 0x0000ffff))
+#define SET_RXTRAP_ETHTYPE1(_VAL_) (REG32(ADR_RX_ETHER_TYPE_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ETHER_TYPE_1)) & 0xffff0000))
+#define SET_RXTRAP_ETHTYPE0(_VAL_) (REG32(ADR_RX_ETHER_TYPE_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_ETHER_TYPE_1)) & 0x0000ffff))
+#define SET_TX_PKT_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_0)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_0)) & 0x00000000))
+#define SET_RX_PKT_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_1)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_1)) & 0x00000000))
+#define SET_HOST_CMD_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_2)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_2)) & 0xffffff00))
+#define SET_HOST_EVENT_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_3)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_3)) & 0xffffff00))
+#define SET_TX_PKT_DROP_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_4)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_4)) & 0xffffff00))
+#define SET_RX_PKT_DROP_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_5)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_5)) & 0xffffff00))
+#define SET_TX_PKT_TRAP_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_6)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_6)) & 0xffffff00))
+#define SET_RX_PKT_TRAP_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_7)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_7)) & 0xffffff00))
+#define SET_HOST_TX_FAIL_COUNTER(_VAL_) (REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_0)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_0)) & 0xffffff00))
+#define SET_HOST_RX_FAIL_COUNTER(_VAL_) (REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_1)) & 0xffffff00))
+#define SET_HCI_STATE_MONITOR(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_0)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_0)) & 0x00000000))
+#define SET_HCI_ST_TIMEOUT_MONITOR(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_1)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_1)) & 0x00000000))
+#define SET_TX_ON_DEMAND_LENGTH(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_2)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_2)) & 0x00000000))
+#define SET_HCI_MONITOR_REG1(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_3)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_3)) & 0x00000000))
+#define SET_HCI_MONITOR_REG2(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_4)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_4)) & 0x00000000))
+#define SET_HCI_TX_ALLOC_TIME_31_0(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_5)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_5)) & 0x00000000))
+#define SET_HCI_TX_ALLOC_TIME_47_32(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_6)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_6)) & 0xffff0000))
+#define SET_HCI_MB_MAX_CNT(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_6)) = (((_VAL_) << 16) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_6)) & 0xff00ffff))
+#define SET_HCI_TX_ALLOC_CNT_31_0(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_7)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_7)) & 0x00000000))
+#define SET_HCI_TX_ALLOC_CNT_47_32(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_8)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0xffff0000))
+#define SET_HCI_PROC_CNT(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_8)) = (((_VAL_) << 16) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0xff00ffff))
+#define SET_SDIO_TRANS_CNT(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_8)) = (((_VAL_) << 24) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0x00ffffff))
+#define SET_SDIO_TX_INVALID_CNT_31_0(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_9)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_9)) & 0x00000000))
+#define SET_SDIO_TX_INVALID_CNT_47_32(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_10)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_10)) & 0xffff0000))
+#define SET_CS_START_ADDR(_VAL_) (REG32(ADR_CS_START_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_CS_START_ADDR)) & 0xffff0000))
+#define SET_CS_PKT_ID(_VAL_) (REG32(ADR_CS_START_ADDR)) = (((_VAL_) << 16) | ((REG32(ADR_CS_START_ADDR)) & 0xff80ffff))
+#define SET_ADD_LEN(_VAL_) (REG32(ADR_CS_ADD_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_CS_ADD_LEN)) & 0xffff0000))
+#define SET_CS_ADDER_EN(_VAL_) (REG32(ADR_CS_CMD)) = (((_VAL_) << 0) | ((REG32(ADR_CS_CMD)) & 0xfffffffe))
+#define SET_PSEUDO(_VAL_) (REG32(ADR_CS_CMD)) = (((_VAL_) << 1) | ((REG32(ADR_CS_CMD)) & 0xfffffffd))
+#define SET_CALCULATE(_VAL_) (REG32(ADR_CS_INI_BUF)) = (((_VAL_) << 0) | ((REG32(ADR_CS_INI_BUF)) & 0x00000000))
+#define SET_L4_LEN(_VAL_) (REG32(ADR_CS_PSEUDO_BUF)) = (((_VAL_) << 0) | ((REG32(ADR_CS_PSEUDO_BUF)) & 0xffff0000))
+#define SET_L4_PROTOL(_VAL_) (REG32(ADR_CS_PSEUDO_BUF)) = (((_VAL_) << 16) | ((REG32(ADR_CS_PSEUDO_BUF)) & 0xff00ffff))
+#define SET_CHECK_SUM(_VAL_) (REG32(ADR_CS_CHECK_SUM)) = (((_VAL_) << 0) | ((REG32(ADR_CS_CHECK_SUM)) & 0xffff0000))
+#define SET_RAND_EN(_VAL_) (REG32(ADR_RAND_EN)) = (((_VAL_) << 0) | ((REG32(ADR_RAND_EN)) & 0xfffffffe))
+#define SET_RAND_NUM(_VAL_) (REG32(ADR_RAND_NUM)) = (((_VAL_) << 0) | ((REG32(ADR_RAND_NUM)) & 0x00000000))
+#define SET_MUL_OP1(_VAL_) (REG32(ADR_MUL_OP1)) = (((_VAL_) << 0) | ((REG32(ADR_MUL_OP1)) & 0x00000000))
+#define SET_MUL_OP2(_VAL_) (REG32(ADR_MUL_OP2)) = (((_VAL_) << 0) | ((REG32(ADR_MUL_OP2)) & 0x00000000))
+#define SET_MUL_ANS0(_VAL_) (REG32(ADR_MUL_ANS0)) = (((_VAL_) << 0) | ((REG32(ADR_MUL_ANS0)) & 0x00000000))
+#define SET_MUL_ANS1(_VAL_) (REG32(ADR_MUL_ANS1)) = (((_VAL_) << 0) | ((REG32(ADR_MUL_ANS1)) & 0x00000000))
+#define SET_RD_ADDR(_VAL_) (REG32(ADR_DMA_RDATA)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_RDATA)) & 0xffff0000))
+#define SET_RD_ID(_VAL_) (REG32(ADR_DMA_RDATA)) = (((_VAL_) << 16) | ((REG32(ADR_DMA_RDATA)) & 0xff80ffff))
+#define SET_WR_ADDR(_VAL_) (REG32(ADR_DMA_WDATA)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_WDATA)) & 0xffff0000))
+#define SET_WR_ID(_VAL_) (REG32(ADR_DMA_WDATA)) = (((_VAL_) << 16) | ((REG32(ADR_DMA_WDATA)) & 0xff80ffff))
+#define SET_LEN(_VAL_) (REG32(ADR_DMA_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_LEN)) & 0xffff0000))
+#define SET_CLR(_VAL_) (REG32(ADR_DMA_CLR)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_CLR)) & 0xfffffffe))
+#define SET_PHY_MODE(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_NAV_DATA)) & 0xfffffffc))
+#define SET_SHRT_PREAM(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 2) | ((REG32(ADR_NAV_DATA)) & 0xfffffffb))
+#define SET_SHRT_GI(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 3) | ((REG32(ADR_NAV_DATA)) & 0xfffffff7))
+#define SET_DATA_RATE(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 4) | ((REG32(ADR_NAV_DATA)) & 0xfffff80f))
+#define SET_MCS(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 12) | ((REG32(ADR_NAV_DATA)) & 0xffff8fff))
+#define SET_FRAME_LEN(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 16) | ((REG32(ADR_NAV_DATA)) & 0x0000ffff))
+#define SET_DURATION(_VAL_) (REG32(ADR_CO_NAV)) = (((_VAL_) << 0) | ((REG32(ADR_CO_NAV)) & 0xffff0000))
+#define SET_SHA_DST_ADDR(_VAL_) (REG32(ADR_SHA_DST_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_SHA_DST_ADDR)) & 0x00000000))
+#define SET_SHA_SRC_ADDR(_VAL_) (REG32(ADR_SHA_SRC_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_SHA_SRC_ADDR)) & 0x00000000))
+#define SET_SHA_BUSY(_VAL_) (REG32(ADR_SHA_SETTING)) = (((_VAL_) << 0) | ((REG32(ADR_SHA_SETTING)) & 0xfffffffe))
+#define SET_SHA_ENDIAN(_VAL_) (REG32(ADR_SHA_SETTING)) = (((_VAL_) << 1) | ((REG32(ADR_SHA_SETTING)) & 0xfffffffd))
+#define SET_EFS_CLKFREQ(_VAL_) (REG32(ADR_EFUSE_CLK_FREQ)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_CLK_FREQ)) & 0xfffff000))
+#define SET_LOW_ACTIVE(_VAL_) (REG32(ADR_EFUSE_CLK_FREQ)) = (((_VAL_) << 16) | ((REG32(ADR_EFUSE_CLK_FREQ)) & 0xfffeffff))
+#define SET_EFS_CLKFREQ_RD(_VAL_) (REG32(ADR_EFUSE_CLK_FREQ)) = (((_VAL_) << 20) | ((REG32(ADR_EFUSE_CLK_FREQ)) & 0xf00fffff))
+#define SET_EFS_PRE_RD(_VAL_) (REG32(ADR_EFUSE_CLK_FREQ)) = (((_VAL_) << 28) | ((REG32(ADR_EFUSE_CLK_FREQ)) & 0x0fffffff))
+#define SET_EFS_LDO_ON(_VAL_) (REG32(ADR_EFUSE_LDO_TIME)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_LDO_TIME)) & 0xffff0000))
+#define SET_EFS_LDO_OFF(_VAL_) (REG32(ADR_EFUSE_LDO_TIME)) = (((_VAL_) << 16) | ((REG32(ADR_EFUSE_LDO_TIME)) & 0x0000ffff))
+#define SET_EFS_RDATA_0(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_0)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_0)) & 0x00000000))
+#define SET_EFS_WDATA_0(_VAL_) (REG32(ADR_EFUSE_WDATA_0)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_0)) & 0x00000000))
+#define SET_EFS_RDATA_1(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_1)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_1)) & 0x00000000))
+#define SET_EFS_WDATA_1(_VAL_) (REG32(ADR_EFUSE_WDATA_1)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_1)) & 0x00000000))
+#define SET_EFS_RDATA_2(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_2)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_2)) & 0x00000000))
+#define SET_EFS_WDATA_2(_VAL_) (REG32(ADR_EFUSE_WDATA_2)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_2)) & 0x00000000))
+#define SET_EFS_RDATA_3(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_3)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_3)) & 0x00000000))
+#define SET_EFS_WDATA_3(_VAL_) (REG32(ADR_EFUSE_WDATA_3)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_3)) & 0x00000000))
+#define SET_EFS_RDATA_4(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_4)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_4)) & 0x00000000))
+#define SET_EFS_WDATA_4(_VAL_) (REG32(ADR_EFUSE_WDATA_4)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_4)) & 0x00000000))
+#define SET_EFS_RDATA_5(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_5)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_5)) & 0x00000000))
+#define SET_EFS_WDATA_5(_VAL_) (REG32(ADR_EFUSE_WDATA_5)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_5)) & 0x00000000))
+#define SET_EFS_RDATA_6(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_6)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_6)) & 0x00000000))
+#define SET_EFS_WDATA_6(_VAL_) (REG32(ADR_EFUSE_WDATA_6)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_6)) & 0x00000000))
+#define SET_EFS_RDATA_7(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_7)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_7)) & 0x00000000))
+#define SET_EFS_WDATA_7(_VAL_) (REG32(ADR_EFUSE_WDATA_7)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_7)) & 0x00000000))
+#define SET_EFS_SPI_RD0_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD0_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD0_EN)) & 0xfffffffe))
+#define SET_EFS_SPI_RD1_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD1_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD1_EN)) & 0xfffffffe))
+#define SET_EFS_SPI_RD2_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD2_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD2_EN)) & 0xfffffffe))
+#define SET_EFS_SPI_RD3_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD3_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD3_EN)) & 0xfffffffe))
+#define SET_EFS_SPI_RD4_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD4_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD4_EN)) & 0xfffffffe))
+#define SET_EFS_SPI_RD5_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD5_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD5_EN)) & 0xfffffffe))
+#define SET_EFS_SPI_RD6_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD6_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD6_EN)) & 0xfffffffe))
+#define SET_EFS_SPI_RD7_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD7_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD7_EN)) & 0xfffffffe))
+#define SET_EFS_SPI_RBUSY(_VAL_) (REG32(ADR_EFUSE_SPI_BUSY)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_BUSY)) & 0xfffffffe))
+#define SET_EFS_SPI_RDATA_0(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_0)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_0)) & 0x00000000))
+#define SET_EFS_SPI_RDATA_1(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_1)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_1)) & 0x00000000))
+#define SET_EFS_SPI_RDATA_2(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_2)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_2)) & 0x00000000))
+#define SET_EFS_SPI_RDATA_3(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_3)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_3)) & 0x00000000))
+#define SET_EFS_SPI_RDATA_4(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_4)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_4)) & 0x00000000))
+#define SET_EFS_SPI_RDATA_5(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_5)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_5)) & 0x00000000))
+#define SET_EFS_SPI_RDATA_6(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_6)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_6)) & 0x00000000))
+#define SET_EFS_SPI_RDATA_7(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_7)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_7)) & 0x00000000))
+#define SET_GET_RK(_VAL_) (REG32(ADR_SMS4_CFG1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_CFG1)) & 0xfffffffe))
+#define SET_FORCE_GET_RK(_VAL_) (REG32(ADR_SMS4_CFG1)) = (((_VAL_) << 1) | ((REG32(ADR_SMS4_CFG1)) & 0xfffffffd))
+#define SET_SMS4_DESCRY_EN(_VAL_) (REG32(ADR_SMS4_CFG1)) = (((_VAL_) << 4) | ((REG32(ADR_SMS4_CFG1)) & 0xffffffef))
+#define SET_DEC_DOUT_MSB(_VAL_) (REG32(ADR_SMS4_CFG2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_CFG2)) & 0xfffffffe))
+#define SET_DEC_DIN_MSB(_VAL_) (REG32(ADR_SMS4_CFG2)) = (((_VAL_) << 1) | ((REG32(ADR_SMS4_CFG2)) & 0xfffffffd))
+#define SET_ENC_DOUT_MSB(_VAL_) (REG32(ADR_SMS4_CFG2)) = (((_VAL_) << 2) | ((REG32(ADR_SMS4_CFG2)) & 0xfffffffb))
+#define SET_ENC_DIN_MSB(_VAL_) (REG32(ADR_SMS4_CFG2)) = (((_VAL_) << 3) | ((REG32(ADR_SMS4_CFG2)) & 0xfffffff7))
+#define SET_KEY_DIN_MSB(_VAL_) (REG32(ADR_SMS4_CFG2)) = (((_VAL_) << 4) | ((REG32(ADR_SMS4_CFG2)) & 0xffffffef))
+#define SET_SMS4_CBC_EN(_VAL_) (REG32(ADR_SMS4_MODE1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_MODE1)) & 0xfffffffe))
+#define SET_SMS4_CFB_EN(_VAL_) (REG32(ADR_SMS4_MODE1)) = (((_VAL_) << 1) | ((REG32(ADR_SMS4_MODE1)) & 0xfffffffd))
+#define SET_SMS4_OFB_EN(_VAL_) (REG32(ADR_SMS4_MODE1)) = (((_VAL_) << 2) | ((REG32(ADR_SMS4_MODE1)) & 0xfffffffb))
+#define SET_SMS4_START_TRIG(_VAL_) (REG32(ADR_SMS4_TRIG)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_TRIG)) & 0xfffffffe))
+#define SET_SMS4_BUSY(_VAL_) (REG32(ADR_SMS4_STATUS1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_STATUS1)) & 0xfffffffe))
+#define SET_SMS4_DONE(_VAL_) (REG32(ADR_SMS4_STATUS2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_STATUS2)) & 0xfffffffe))
+#define SET_SMS4_DATAIN_0(_VAL_) (REG32(ADR_SMS4_DATA_IN0)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_IN0)) & 0x00000000))
+#define SET_SMS4_DATAIN_1(_VAL_) (REG32(ADR_SMS4_DATA_IN1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_IN1)) & 0x00000000))
+#define SET_SMS4_DATAIN_2(_VAL_) (REG32(ADR_SMS4_DATA_IN2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_IN2)) & 0x00000000))
+#define SET_SMS4_DATAIN_3(_VAL_) (REG32(ADR_SMS4_DATA_IN3)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_IN3)) & 0x00000000))
+#define SET_SMS4_DATAOUT_0(_VAL_) (REG32(ADR_SMS4_DATA_OUT0)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_OUT0)) & 0x00000000))
+#define SET_SMS4_DATAOUT_1(_VAL_) (REG32(ADR_SMS4_DATA_OUT1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_OUT1)) & 0x00000000))
+#define SET_SMS4_DATAOUT_2(_VAL_) (REG32(ADR_SMS4_DATA_OUT2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_OUT2)) & 0x00000000))
+#define SET_SMS4_DATAOUT_3(_VAL_) (REG32(ADR_SMS4_DATA_OUT3)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_OUT3)) & 0x00000000))
+#define SET_SMS4_KEY_0(_VAL_) (REG32(ADR_SMS4_KEY_0)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_KEY_0)) & 0x00000000))
+#define SET_SMS4_KEY_1(_VAL_) (REG32(ADR_SMS4_KEY_1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_KEY_1)) & 0x00000000))
+#define SET_SMS4_KEY_2(_VAL_) (REG32(ADR_SMS4_KEY_2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_KEY_2)) & 0x00000000))
+#define SET_SMS4_KEY_3(_VAL_) (REG32(ADR_SMS4_KEY_3)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_KEY_3)) & 0x00000000))
+#define SET_SMS4_MODE_IV0(_VAL_) (REG32(ADR_SMS4_MODE_IV0)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_MODE_IV0)) & 0x00000000))
+#define SET_SMS4_MODE_IV1(_VAL_) (REG32(ADR_SMS4_MODE_IV1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_MODE_IV1)) & 0x00000000))
+#define SET_SMS4_MODE_IV2(_VAL_) (REG32(ADR_SMS4_MODE_IV2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_MODE_IV2)) & 0x00000000))
+#define SET_SMS4_MODE_IV3(_VAL_) (REG32(ADR_SMS4_MODE_IV3)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_MODE_IV3)) & 0x00000000))
+#define SET_SMS4_OFB_ENC0(_VAL_) (REG32(ADR_SMS4_OFB_ENC0)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_OFB_ENC0)) & 0x00000000))
+#define SET_SMS4_OFB_ENC1(_VAL_) (REG32(ADR_SMS4_OFB_ENC1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_OFB_ENC1)) & 0x00000000))
+#define SET_SMS4_OFB_ENC2(_VAL_) (REG32(ADR_SMS4_OFB_ENC2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_OFB_ENC2)) & 0x00000000))
+#define SET_SMS4_OFB_ENC3(_VAL_) (REG32(ADR_SMS4_OFB_ENC3)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_OFB_ENC3)) & 0x00000000))
+#define SET_MRX_MCAST_TB0_31_0(_VAL_) (REG32(ADR_MRX_MCAST_TB0_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB0_0)) & 0x00000000))
+#define SET_MRX_MCAST_TB0_47_32(_VAL_) (REG32(ADR_MRX_MCAST_TB0_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB0_1)) & 0xffff0000))
+#define SET_MRX_MCAST_MASK0_31_0(_VAL_) (REG32(ADR_MRX_MCAST_MK0_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK0_0)) & 0x00000000))
+#define SET_MRX_MCAST_MASK0_47_32(_VAL_) (REG32(ADR_MRX_MCAST_MK0_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK0_1)) & 0xffff0000))
+#define SET_MRX_MCAST_CTRL_0(_VAL_) (REG32(ADR_MRX_MCAST_CTRL0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_CTRL0)) & 0xfffffffc))
+#define SET_MRX_MCAST_TB1_31_0(_VAL_) (REG32(ADR_MRX_MCAST_TB1_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB1_0)) & 0x00000000))
+#define SET_MRX_MCAST_TB1_47_32(_VAL_) (REG32(ADR_MRX_MCAST_TB1_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB1_1)) & 0xffff0000))
+#define SET_MRX_MCAST_MASK1_31_0(_VAL_) (REG32(ADR_MRX_MCAST_MK1_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK1_0)) & 0x00000000))
+#define SET_MRX_MCAST_MASK1_47_32(_VAL_) (REG32(ADR_MRX_MCAST_MK1_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK1_1)) & 0xffff0000))
+#define SET_MRX_MCAST_CTRL_1(_VAL_) (REG32(ADR_MRX_MCAST_CTRL1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_CTRL1)) & 0xfffffffc))
+#define SET_MRX_MCAST_TB2_31_0(_VAL_) (REG32(ADR_MRX_MCAST_TB2_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB2_0)) & 0x00000000))
+#define SET_MRX_MCAST_TB2_47_32(_VAL_) (REG32(ADR_MRX_MCAST_TB2_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB2_1)) & 0xffff0000))
+#define SET_MRX_MCAST_MASK2_31_0(_VAL_) (REG32(ADR_MRX_MCAST_MK2_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK2_0)) & 0x00000000))
+#define SET_MRX_MCAST_MASK2_47_32(_VAL_) (REG32(ADR_MRX_MCAST_MK2_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK2_1)) & 0xffff0000))
+#define SET_MRX_MCAST_CTRL_2(_VAL_) (REG32(ADR_MRX_MCAST_CTRL2)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_CTRL2)) & 0xfffffffc))
+#define SET_MRX_MCAST_TB3_31_0(_VAL_) (REG32(ADR_MRX_MCAST_TB3_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB3_0)) & 0x00000000))
+#define SET_MRX_MCAST_TB3_47_32(_VAL_) (REG32(ADR_MRX_MCAST_TB3_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB3_1)) & 0xffff0000))
+#define SET_MRX_MCAST_MASK3_31_0(_VAL_) (REG32(ADR_MRX_MCAST_MK3_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK3_0)) & 0x00000000))
+#define SET_MRX_MCAST_MASK3_47_32(_VAL_) (REG32(ADR_MRX_MCAST_MK3_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK3_1)) & 0xffff0000))
+#define SET_MRX_MCAST_CTRL_3(_VAL_) (REG32(ADR_MRX_MCAST_CTRL3)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_CTRL3)) & 0xfffffffc))
+#define SET_MRX_PHY_INFO(_VAL_) (REG32(ADR_MRX_PHY_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_PHY_INFO)) & 0x00000000))
+#define SET_DBG_BA_TYPE(_VAL_) (REG32(ADR_MRX_BA_DBG)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_BA_DBG)) & 0xffffffc0))
+#define SET_DBG_BA_SEQ(_VAL_) (REG32(ADR_MRX_BA_DBG)) = (((_VAL_) << 8) | ((REG32(ADR_MRX_BA_DBG)) & 0xfff000ff))
+#define SET_MRX_FLT_TB0(_VAL_) (REG32(ADR_MRX_FLT_TB0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB0)) & 0xffff8000))
+#define SET_MRX_FLT_TB1(_VAL_) (REG32(ADR_MRX_FLT_TB1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB1)) & 0xffff8000))
+#define SET_MRX_FLT_TB2(_VAL_) (REG32(ADR_MRX_FLT_TB2)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB2)) & 0xffff8000))
+#define SET_MRX_FLT_TB3(_VAL_) (REG32(ADR_MRX_FLT_TB3)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB3)) & 0xffff8000))
+#define SET_MRX_FLT_TB4(_VAL_) (REG32(ADR_MRX_FLT_TB4)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB4)) & 0xffff8000))
+#define SET_MRX_FLT_TB5(_VAL_) (REG32(ADR_MRX_FLT_TB5)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB5)) & 0xffff8000))
+#define SET_MRX_FLT_TB6(_VAL_) (REG32(ADR_MRX_FLT_TB6)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB6)) & 0xffff8000))
+#define SET_MRX_FLT_TB7(_VAL_) (REG32(ADR_MRX_FLT_TB7)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB7)) & 0xffff8000))
+#define SET_MRX_FLT_TB8(_VAL_) (REG32(ADR_MRX_FLT_TB8)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB8)) & 0xffff8000))
+#define SET_MRX_FLT_TB9(_VAL_) (REG32(ADR_MRX_FLT_TB9)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB9)) & 0xffff8000))
+#define SET_MRX_FLT_TB10(_VAL_) (REG32(ADR_MRX_FLT_TB10)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB10)) & 0xffff8000))
+#define SET_MRX_FLT_TB11(_VAL_) (REG32(ADR_MRX_FLT_TB11)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB11)) & 0xffff8000))
+#define SET_MRX_FLT_TB12(_VAL_) (REG32(ADR_MRX_FLT_TB12)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB12)) & 0xffff8000))
+#define SET_MRX_FLT_TB13(_VAL_) (REG32(ADR_MRX_FLT_TB13)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB13)) & 0xffff8000))
+#define SET_MRX_FLT_TB14(_VAL_) (REG32(ADR_MRX_FLT_TB14)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB14)) & 0xffff8000))
+#define SET_MRX_FLT_TB15(_VAL_) (REG32(ADR_MRX_FLT_TB15)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB15)) & 0xffff8000))
+#define SET_MRX_FLT_EN0(_VAL_) (REG32(ADR_MRX_FLT_EN0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN0)) & 0xffff0000))
+#define SET_MRX_FLT_EN1(_VAL_) (REG32(ADR_MRX_FLT_EN1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN1)) & 0xffff0000))
+#define SET_MRX_FLT_EN2(_VAL_) (REG32(ADR_MRX_FLT_EN2)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN2)) & 0xffff0000))
+#define SET_MRX_FLT_EN3(_VAL_) (REG32(ADR_MRX_FLT_EN3)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN3)) & 0xffff0000))
+#define SET_MRX_FLT_EN4(_VAL_) (REG32(ADR_MRX_FLT_EN4)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN4)) & 0xffff0000))
+#define SET_MRX_FLT_EN5(_VAL_) (REG32(ADR_MRX_FLT_EN5)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN5)) & 0xffff0000))
+#define SET_MRX_FLT_EN6(_VAL_) (REG32(ADR_MRX_FLT_EN6)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN6)) & 0xffff0000))
+#define SET_MRX_FLT_EN7(_VAL_) (REG32(ADR_MRX_FLT_EN7)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN7)) & 0xffff0000))
+#define SET_MRX_FLT_EN8(_VAL_) (REG32(ADR_MRX_FLT_EN8)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN8)) & 0xffff0000))
+#define SET_MRX_LEN_FLT(_VAL_) (REG32(ADR_MRX_LEN_FLT)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_LEN_FLT)) & 0xffff0000))
+#define SET_RX_FLOW_DATA(_VAL_) (REG32(ADR_RX_FLOW_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FLOW_DATA)) & 0x00000000))
+#define SET_RX_FLOW_MNG(_VAL_) (REG32(ADR_RX_FLOW_MNG)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FLOW_MNG)) & 0xffff0000))
+#define SET_RX_FLOW_CTRL(_VAL_) (REG32(ADR_RX_FLOW_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FLOW_CTRL)) & 0xffff0000))
+#define SET_MRX_STP_EN(_VAL_) (REG32(ADR_RX_TIME_STAMP_CFG)) = (((_VAL_) << 0) | ((REG32(ADR_RX_TIME_STAMP_CFG)) & 0xfffffffe))
+#define SET_MRX_STP_OFST(_VAL_) (REG32(ADR_RX_TIME_STAMP_CFG)) = (((_VAL_) << 8) | ((REG32(ADR_RX_TIME_STAMP_CFG)) & 0xffff00ff))
+#define SET_DBG_FF_FULL(_VAL_) (REG32(ADR_DBG_FF_FULL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_FF_FULL)) & 0xffff0000))
+#define SET_DBG_FF_FULL_CLR(_VAL_) (REG32(ADR_DBG_FF_FULL)) = (((_VAL_) << 31) | ((REG32(ADR_DBG_FF_FULL)) & 0x7fffffff))
+#define SET_DBG_WFF_FULL(_VAL_) (REG32(ADR_DBG_WFF_FULL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_WFF_FULL)) & 0xffff0000))
+#define SET_DBG_WFF_FULL_CLR(_VAL_) (REG32(ADR_DBG_WFF_FULL)) = (((_VAL_) << 31) | ((REG32(ADR_DBG_WFF_FULL)) & 0x7fffffff))
+#define SET_DBG_MB_FULL(_VAL_) (REG32(ADR_DBG_MB_FULL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_MB_FULL)) & 0xffff0000))
+#define SET_DBG_MB_FULL_CLR(_VAL_) (REG32(ADR_DBG_MB_FULL)) = (((_VAL_) << 31) | ((REG32(ADR_DBG_MB_FULL)) & 0x7fffffff))
+#define SET_BA_CTRL(_VAL_) (REG32(ADR_BA_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_BA_CTRL)) & 0xfffffffc))
+#define SET_BA_DBG_EN(_VAL_) (REG32(ADR_BA_CTRL)) = (((_VAL_) << 2) | ((REG32(ADR_BA_CTRL)) & 0xfffffffb))
+#define SET_BA_AGRE_EN(_VAL_) (REG32(ADR_BA_CTRL)) = (((_VAL_) << 3) | ((REG32(ADR_BA_CTRL)) & 0xfffffff7))
+#define SET_BA_TA_31_0(_VAL_) (REG32(ADR_BA_TA_0)) = (((_VAL_) << 0) | ((REG32(ADR_BA_TA_0)) & 0x00000000))
+#define SET_BA_TA_47_32(_VAL_) (REG32(ADR_BA_TA_1)) = (((_VAL_) << 0) | ((REG32(ADR_BA_TA_1)) & 0xffff0000))
+#define SET_BA_TID(_VAL_) (REG32(ADR_BA_TID)) = (((_VAL_) << 0) | ((REG32(ADR_BA_TID)) & 0xfffffff0))
+#define SET_BA_ST_SEQ(_VAL_) (REG32(ADR_BA_ST_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_BA_ST_SEQ)) & 0xfffff000))
+#define SET_BA_SB0(_VAL_) (REG32(ADR_BA_SB0)) = (((_VAL_) << 0) | ((REG32(ADR_BA_SB0)) & 0x00000000))
+#define SET_BA_SB1(_VAL_) (REG32(ADR_BA_SB1)) = (((_VAL_) << 0) | ((REG32(ADR_BA_SB1)) & 0x00000000))
+#define SET_MRX_WD(_VAL_) (REG32(ADR_MRX_WATCH_DOG)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_WATCH_DOG)) & 0xfffe0000))
+#define SET_ACK_GEN_EN(_VAL_) (REG32(ADR_ACK_GEN_EN)) = (((_VAL_) << 0) | ((REG32(ADR_ACK_GEN_EN)) & 0xfffffffe))
+#define SET_BA_GEN_EN(_VAL_) (REG32(ADR_ACK_GEN_EN)) = (((_VAL_) << 1) | ((REG32(ADR_ACK_GEN_EN)) & 0xfffffffd))
+#define SET_ACK_GEN_DUR(_VAL_) (REG32(ADR_ACK_GEN_PARA)) = (((_VAL_) << 0) | ((REG32(ADR_ACK_GEN_PARA)) & 0xffff0000))
+#define SET_ACK_GEN_INFO(_VAL_) (REG32(ADR_ACK_GEN_PARA)) = (((_VAL_) << 16) | ((REG32(ADR_ACK_GEN_PARA)) & 0xffc0ffff))
+#define SET_ACK_GEN_RA_31_0(_VAL_) (REG32(ADR_ACK_GEN_RA_0)) = (((_VAL_) << 0) | ((REG32(ADR_ACK_GEN_RA_0)) & 0x00000000))
+#define SET_ACK_GEN_RA_47_32(_VAL_) (REG32(ADR_ACK_GEN_RA_1)) = (((_VAL_) << 0) | ((REG32(ADR_ACK_GEN_RA_1)) & 0xffff0000))
+#define SET_MIB_LEN_FAIL(_VAL_) (REG32(ADR_MIB_LEN_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_LEN_FAIL)) & 0xffff0000))
+#define SET_TRAP_HW_ID(_VAL_) (REG32(ADR_TRAP_HW_ID)) = (((_VAL_) << 0) | ((REG32(ADR_TRAP_HW_ID)) & 0xfffffff0))
+#define SET_ID_IN_USE(_VAL_) (REG32(ADR_ID_IN_USE)) = (((_VAL_) << 0) | ((REG32(ADR_ID_IN_USE)) & 0xffffff00))
+#define SET_MRX_ERR(_VAL_) (REG32(ADR_MRX_ERR)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_ERR)) & 0x00000000))
+#define SET_W0_T0_SEQ(_VAL_) (REG32(ADR_WSID0_TID0_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID0_RX_SEQ)) & 0xffff0000))
+#define SET_W0_T1_SEQ(_VAL_) (REG32(ADR_WSID0_TID1_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID1_RX_SEQ)) & 0xffff0000))
+#define SET_W0_T2_SEQ(_VAL_) (REG32(ADR_WSID0_TID2_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID2_RX_SEQ)) & 0xffff0000))
+#define SET_W0_T3_SEQ(_VAL_) (REG32(ADR_WSID0_TID3_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID3_RX_SEQ)) & 0xffff0000))
+#define SET_W0_T4_SEQ(_VAL_) (REG32(ADR_WSID0_TID4_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID4_RX_SEQ)) & 0xffff0000))
+#define SET_W0_T5_SEQ(_VAL_) (REG32(ADR_WSID0_TID5_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID5_RX_SEQ)) & 0xffff0000))
+#define SET_W0_T6_SEQ(_VAL_) (REG32(ADR_WSID0_TID6_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID6_RX_SEQ)) & 0xffff0000))
+#define SET_W0_T7_SEQ(_VAL_) (REG32(ADR_WSID0_TID7_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID7_RX_SEQ)) & 0xffff0000))
+#define SET_W1_T0_SEQ(_VAL_) (REG32(ADR_WSID1_TID0_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID0_RX_SEQ)) & 0xffff0000))
+#define SET_W1_T1_SEQ(_VAL_) (REG32(ADR_WSID1_TID1_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID1_RX_SEQ)) & 0xffff0000))
+#define SET_W1_T2_SEQ(_VAL_) (REG32(ADR_WSID1_TID2_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID2_RX_SEQ)) & 0xffff0000))
+#define SET_W1_T3_SEQ(_VAL_) (REG32(ADR_WSID1_TID3_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID3_RX_SEQ)) & 0xffff0000))
+#define SET_W1_T4_SEQ(_VAL_) (REG32(ADR_WSID1_TID4_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID4_RX_SEQ)) & 0xffff0000))
+#define SET_W1_T5_SEQ(_VAL_) (REG32(ADR_WSID1_TID5_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID5_RX_SEQ)) & 0xffff0000))
+#define SET_W1_T6_SEQ(_VAL_) (REG32(ADR_WSID1_TID6_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID6_RX_SEQ)) & 0xffff0000))
+#define SET_W1_T7_SEQ(_VAL_) (REG32(ADR_WSID1_TID7_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID7_RX_SEQ)) & 0xffff0000))
+#define SET_ADDR1A_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 0) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xfffffffc))
+#define SET_ADDR2A_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 2) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xfffffff3))
+#define SET_ADDR3A_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 4) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xffffffcf))
+#define SET_ADDR1B_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 6) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xffffff3f))
+#define SET_ADDR2B_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 8) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xfffffcff))
+#define SET_ADDR3B_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 10) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xfffff3ff))
+#define SET_ADDR3C_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 12) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xffffcfff))
+#define SET_FRM_CTRL(_VAL_) (REG32(ADR_FRAME_TYPE_CNTR_SET)) = (((_VAL_) << 0) | ((REG32(ADR_FRAME_TYPE_CNTR_SET)) & 0xffffffc0))
+#define SET_CSR_PHY_INFO(_VAL_) (REG32(ADR_PHY_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_INFO)) & 0xffff8000))
+#define SET_AMPDU_SIG(_VAL_) (REG32(ADR_AMPDU_SIG)) = (((_VAL_) << 0) | ((REG32(ADR_AMPDU_SIG)) & 0xffffff00))
+#define SET_MIB_AMPDU(_VAL_) (REG32(ADR_MIB_AMPDU)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_AMPDU)) & 0x00000000))
+#define SET_LEN_FLT(_VAL_) (REG32(ADR_LEN_FLT)) = (((_VAL_) << 0) | ((REG32(ADR_LEN_FLT)) & 0xffff0000))
+#define SET_MIB_DELIMITER(_VAL_) (REG32(ADR_MIB_DELIMITER)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_DELIMITER)) & 0xffff0000))
+#define SET_MTX_INT_Q0_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_INT_STS)) & 0xfffeffff))
+#define SET_MTX_INT_Q0_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 17) | ((REG32(ADR_MTX_INT_STS)) & 0xfffdffff))
+#define SET_MTX_INT_Q1_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 18) | ((REG32(ADR_MTX_INT_STS)) & 0xfffbffff))
+#define SET_MTX_INT_Q1_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 19) | ((REG32(ADR_MTX_INT_STS)) & 0xfff7ffff))
+#define SET_MTX_INT_Q2_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 20) | ((REG32(ADR_MTX_INT_STS)) & 0xffefffff))
+#define SET_MTX_INT_Q2_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 21) | ((REG32(ADR_MTX_INT_STS)) & 0xffdfffff))
+#define SET_MTX_INT_Q3_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 22) | ((REG32(ADR_MTX_INT_STS)) & 0xffbfffff))
+#define SET_MTX_INT_Q3_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 23) | ((REG32(ADR_MTX_INT_STS)) & 0xff7fffff))
+#define SET_MTX_INT_Q4_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 24) | ((REG32(ADR_MTX_INT_STS)) & 0xfeffffff))
+#define SET_MTX_INT_Q4_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 25) | ((REG32(ADR_MTX_INT_STS)) & 0xfdffffff))
+#define SET_MTX_EN_INT_Q0_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_INT_EN)) & 0xfffeffff))
+#define SET_MTX_EN_INT_Q0_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 17) | ((REG32(ADR_MTX_INT_EN)) & 0xfffdffff))
+#define SET_MTX_EN_INT_Q1_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 18) | ((REG32(ADR_MTX_INT_EN)) & 0xfffbffff))
+#define SET_MTX_EN_INT_Q1_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 19) | ((REG32(ADR_MTX_INT_EN)) & 0xfff7ffff))
+#define SET_MTX_EN_INT_Q2_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 20) | ((REG32(ADR_MTX_INT_EN)) & 0xffefffff))
+#define SET_MTX_EN_INT_Q2_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 21) | ((REG32(ADR_MTX_INT_EN)) & 0xffdfffff))
+#define SET_MTX_EN_INT_Q3_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 22) | ((REG32(ADR_MTX_INT_EN)) & 0xffbfffff))
+#define SET_MTX_EN_INT_Q3_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 23) | ((REG32(ADR_MTX_INT_EN)) & 0xff7fffff))
+#define SET_MTX_EN_INT_Q4_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 24) | ((REG32(ADR_MTX_INT_EN)) & 0xfeffffff))
+#define SET_MTX_EN_INT_Q4_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 25) | ((REG32(ADR_MTX_INT_EN)) & 0xfdffffff))
+#define SET_MTX_MTX2PHY_SLOW(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_MISC_EN)) & 0xfffffffe))
+#define SET_MTX_M2M_SLOW_PRD(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_MISC_EN)) & 0xfffffff1))
+#define SET_MTX_AMPDU_CRC_AUTO(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffffdf))
+#define SET_MTX_FAST_RSP_MODE(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffffbf))
+#define SET_MTX_RAW_DATA_MODE(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 7) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffff7f))
+#define SET_MTX_ACK_DUR0(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_MISC_EN)) & 0xfffffeff))
+#define SET_MTX_TSF_AUTO_BCN(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 10) | ((REG32(ADR_MTX_MISC_EN)) & 0xfffffbff))
+#define SET_MTX_TSF_AUTO_MISC(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 11) | ((REG32(ADR_MTX_MISC_EN)) & 0xfffff7ff))
+#define SET_MTX_FORCE_CS_IDLE(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 12) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffefff))
+#define SET_MTX_FORCE_BKF_RXEN0(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 13) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffdfff))
+#define SET_MTX_FORCE_DMA_RXEN0(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 14) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffbfff))
+#define SET_MTX_FORCE_RXEN0(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 15) | ((REG32(ADR_MTX_MISC_EN)) & 0xffff7fff))
+#define SET_MTX_HALT_Q_MB(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_MISC_EN)) & 0xffc0ffff))
+#define SET_MTX_CTS_SET_DIF(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 22) | ((REG32(ADR_MTX_MISC_EN)) & 0xffbfffff))
+#define SET_MTX_AMPDU_SET_DIF(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 23) | ((REG32(ADR_MTX_MISC_EN)) & 0xff7fffff))
+#define SET_MTX_EDCCA_TOUT(_VAL_) (REG32(ADR_MTX_EDCCA_TOUT)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_EDCCA_TOUT)) & 0xfffffc00))
+#define SET_MTX_INT_BCN(_VAL_) (REG32(ADR_MTX_BCN_INT_STS)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_BCN_INT_STS)) & 0xfffffffd))
+#define SET_MTX_INT_DTIM(_VAL_) (REG32(ADR_MTX_BCN_INT_STS)) = (((_VAL_) << 3) | ((REG32(ADR_MTX_BCN_INT_STS)) & 0xfffffff7))
+#define SET_MTX_EN_INT_BCN(_VAL_) (REG32(ADR_MTX_BCN_EN_INT)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_BCN_EN_INT)) & 0xfffffffd))
+#define SET_MTX_EN_INT_DTIM(_VAL_) (REG32(ADR_MTX_BCN_EN_INT)) = (((_VAL_) << 3) | ((REG32(ADR_MTX_BCN_EN_INT)) & 0xfffffff7))
+#define SET_MTX_BCN_TIMER_EN(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xfffffffe))
+#define SET_MTX_TIME_STAMP_AUTO_FILL(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xfffffffd))
+#define SET_MTX_TSF_TIMER_EN(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 5) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xffffffdf))
+#define SET_MTX_HALT_MNG_UNTIL_DTIM(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 6) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xffffffbf))
+#define SET_MTX_INT_DTIM_NUM(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xffff00ff))
+#define SET_MTX_AUTO_FLUSH_Q4(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xfffeffff))
+#define SET_MTX_BCN_PKTID_CH_LOCK(_VAL_) (REG32(ADR_MTX_BCN_MISC)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_MISC)) & 0xfffffffe))
+#define SET_MTX_BCN_CFG_VLD(_VAL_) (REG32(ADR_MTX_BCN_MISC)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_BCN_MISC)) & 0xfffffff9))
+#define SET_MTX_AUTO_BCN_ONGOING(_VAL_) (REG32(ADR_MTX_BCN_MISC)) = (((_VAL_) << 3) | ((REG32(ADR_MTX_BCN_MISC)) & 0xfffffff7))
+#define SET_MTX_BCN_TIMER(_VAL_) (REG32(ADR_MTX_BCN_MISC)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_BCN_MISC)) & 0x0000ffff))
+#define SET_MTX_BCN_PERIOD(_VAL_) (REG32(ADR_MTX_BCN_PRD)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_PRD)) & 0xffff0000))
+#define SET_MTX_DTIM_NUM(_VAL_) (REG32(ADR_MTX_BCN_PRD)) = (((_VAL_) << 24) | ((REG32(ADR_MTX_BCN_PRD)) & 0x00ffffff))
+#define SET_MTX_BCN_TSF_L(_VAL_) (REG32(ADR_MTX_BCN_TSF_L)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_TSF_L)) & 0x00000000))
+#define SET_MTX_BCN_TSF_U(_VAL_) (REG32(ADR_MTX_BCN_TSF_U)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_TSF_U)) & 0x00000000))
+#define SET_MTX_BCN_PKT_ID0(_VAL_) (REG32(ADR_MTX_BCN_CFG0)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_CFG0)) & 0xffffff80))
+#define SET_MTX_DTIM_OFST0(_VAL_) (REG32(ADR_MTX_BCN_CFG0)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_BCN_CFG0)) & 0xfc00ffff))
+#define SET_MTX_BCN_PKT_ID1(_VAL_) (REG32(ADR_MTX_BCN_CFG1)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_CFG1)) & 0xffffff80))
+#define SET_MTX_DTIM_OFST1(_VAL_) (REG32(ADR_MTX_BCN_CFG1)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_BCN_CFG1)) & 0xfc00ffff))
+#define SET_MTX_CCA(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_STATUS)) & 0xfffffffe))
+#define SET_MRX_CCA(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_STATUS)) & 0xfffffffd))
+#define SET_MTX_DMA_FSM(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 2) | ((REG32(ADR_MTX_STATUS)) & 0xffffffe3))
+#define SET_CH_ST_FSM(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 5) | ((REG32(ADR_MTX_STATUS)) & 0xffffff1f))
+#define SET_MTX_GNT_LOCK(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_STATUS)) & 0xfffffeff))
+#define SET_MTX_DMA_REQ(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 9) | ((REG32(ADR_MTX_STATUS)) & 0xfffffdff))
+#define SET_MTX_Q_REQ(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 10) | ((REG32(ADR_MTX_STATUS)) & 0xfffffbff))
+#define SET_MTX_TX_EN(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 11) | ((REG32(ADR_MTX_STATUS)) & 0xfffff7ff))
+#define SET_MRX_RX_EN(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 12) | ((REG32(ADR_MTX_STATUS)) & 0xffffefff))
+#define SET_DBG_PRTC_PRD(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 13) | ((REG32(ADR_MTX_STATUS)) & 0xffffdfff))
+#define SET_DBG_DMA_RDY(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 14) | ((REG32(ADR_MTX_STATUS)) & 0xffffbfff))
+#define SET_DBG_WAIT_RSP(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 15) | ((REG32(ADR_MTX_STATUS)) & 0xffff7fff))
+#define SET_DBG_CFRM_BUSY(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_STATUS)) & 0xfffeffff))
+#define SET_DBG_RST(_VAL_) (REG32(ADR_MTX_DBG_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_CTRL)) & 0xfffffffe))
+#define SET_DBG_MODE(_VAL_) (REG32(ADR_MTX_DBG_CTRL)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_DBG_CTRL)) & 0xfffffffd))
+#define SET_MB_REQ_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT0)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_DAT0)) & 0xffff0000))
+#define SET_RX_EN_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT0)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DBG_DAT0)) & 0x0000ffff))
+#define SET_RX_CS_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT1)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_DAT1)) & 0xffff0000))
+#define SET_TX_CCA_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT1)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DBG_DAT1)) & 0x0000ffff))
+#define SET_Q_REQ_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT2)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_DAT2)) & 0xffff0000))
+#define SET_CH_STA0_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT2)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DBG_DAT2)) & 0x0000ffff))
+#define SET_MTX_DUR_RSP_TOUT_B(_VAL_) (REG32(ADR_MTX_DUR_TOUT)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DUR_TOUT)) & 0xffffff00))
+#define SET_MTX_DUR_RSP_TOUT_G(_VAL_) (REG32(ADR_MTX_DUR_TOUT)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_DUR_TOUT)) & 0xffff00ff))
+#define SET_MTX_DUR_RSP_SIFS(_VAL_) (REG32(ADR_MTX_DUR_IFS)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DUR_IFS)) & 0xffffff00))
+#define SET_MTX_DUR_BURST_SIFS(_VAL_) (REG32(ADR_MTX_DUR_IFS)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_DUR_IFS)) & 0xffff00ff))
+#define SET_MTX_DUR_SLOT(_VAL_) (REG32(ADR_MTX_DUR_IFS)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DUR_IFS)) & 0xffc0ffff))
+#define SET_MTX_DUR_RSP_EIFS(_VAL_) (REG32(ADR_MTX_DUR_IFS)) = (((_VAL_) << 22) | ((REG32(ADR_MTX_DUR_IFS)) & 0x003fffff))
+#define SET_MTX_DUR_RSP_SIFS_G(_VAL_) (REG32(ADR_MTX_DUR_SIFS_G)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DUR_SIFS_G)) & 0xffffff00))
+#define SET_MTX_DUR_BURST_SIFS_G(_VAL_) (REG32(ADR_MTX_DUR_SIFS_G)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_DUR_SIFS_G)) & 0xffff00ff))
+#define SET_MTX_DUR_SLOT_G(_VAL_) (REG32(ADR_MTX_DUR_SIFS_G)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DUR_SIFS_G)) & 0xffc0ffff))
+#define SET_MTX_DUR_RSP_EIFS_G(_VAL_) (REG32(ADR_MTX_DUR_SIFS_G)) = (((_VAL_) << 22) | ((REG32(ADR_MTX_DUR_SIFS_G)) & 0x003fffff))
+#define SET_CH_STA1_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT3)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_DAT3)) & 0xffff0000))
+#define SET_CH_STA2_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT3)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DBG_DAT3)) & 0x0000ffff))
+#define SET_MTX_NAV(_VAL_) (REG32(ADR_MTX_NAV)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_NAV)) & 0xffff0000))
+#define SET_MTX_MIB_CNT0(_VAL_) (REG32(ADR_MTX_MIB_WSID0)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_MIB_WSID0)) & 0xc0000000))
+#define SET_MTX_MIB_EN0(_VAL_) (REG32(ADR_MTX_MIB_WSID0)) = (((_VAL_) << 30) | ((REG32(ADR_MTX_MIB_WSID0)) & 0xbfffffff))
+#define SET_MTX_MIB_CNT1(_VAL_) (REG32(ADR_MTX_MIB_WSID1)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_MIB_WSID1)) & 0xc0000000))
+#define SET_MTX_MIB_EN1(_VAL_) (REG32(ADR_MTX_MIB_WSID1)) = (((_VAL_) << 30) | ((REG32(ADR_MTX_MIB_WSID1)) & 0xbfffffff))
+#define SET_CH_STA3_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT4)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_DAT4)) & 0xffff0000))
+#define SET_CH_STA4_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT4)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DBG_DAT4)) & 0x0000ffff))
+#define SET_TXQ0_MTX_Q_PRE_LD(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xfffffffd))
+#define SET_TXQ0_MTX_Q_BKF_CNT_FIXED(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 2) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xfffffffb))
+#define SET_TXQ0_MTX_Q_TXOP_SUB_FRM_TIME(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 3) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xfffffff7))
+#define SET_TXQ0_MTX_Q_MB_NO_RLS(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 4) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xffffffef))
+#define SET_TXQ0_MTX_Q_TXOP_FRC_BUR(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xffffffdf))
+#define SET_TXQ0_MTX_Q_RND_MODE(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xffffff3f))
+#define SET_TXQ0_MTX_Q_AIFSN(_VAL_) (REG32(ADR_TXQ0_MTX_Q_AIFSN)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0xfffffff0))
+#define SET_TXQ0_MTX_Q_ECWMIN(_VAL_) (REG32(ADR_TXQ0_MTX_Q_AIFSN)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0xfffff0ff))
+#define SET_TXQ0_MTX_Q_ECWMAX(_VAL_) (REG32(ADR_TXQ0_MTX_Q_AIFSN)) = (((_VAL_) << 12) | ((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0xffff0fff))
+#define SET_TXQ0_MTX_Q_TXOP_LIMIT(_VAL_) (REG32(ADR_TXQ0_MTX_Q_AIFSN)) = (((_VAL_) << 16) | ((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0x0000ffff))
+#define SET_TXQ0_MTX_Q_BKF_CNT(_VAL_) (REG32(ADR_TXQ0_MTX_Q_BKF_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_BKF_CNT)) & 0xffff0000))
+#define SET_TXQ0_MTX_Q_SRC_LIMIT(_VAL_) (REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) & 0xffffff00))
+#define SET_TXQ0_MTX_Q_LRC_LIMIT(_VAL_) (REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) & 0xffff00ff))
+#define SET_TXQ0_MTX_Q_ID_MAP_L(_VAL_) (REG32(ADR_TXQ0_MTX_Q_ID_MAP_L)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_ID_MAP_L)) & 0x00000000))
+#define SET_TXQ0_MTX_Q_TXOP_CH_THD(_VAL_) (REG32(ADR_TXQ0_MTX_Q_TXOP_CH_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_TXOP_CH_THD)) & 0xffff0000))
+#define SET_TXQ0_MTX_Q_TXOP_OV_THD(_VAL_) (REG32(ADR_TXQ0_MTX_Q_TXOP_OV_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_TXOP_OV_THD)) & 0xffff0000))
+#define SET_TXQ1_MTX_Q_PRE_LD(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xfffffffd))
+#define SET_TXQ1_MTX_Q_BKF_CNT_FIXED(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 2) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xfffffffb))
+#define SET_TXQ1_MTX_Q_TXOP_SUB_FRM_TIME(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 3) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xfffffff7))
+#define SET_TXQ1_MTX_Q_MB_NO_RLS(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 4) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xffffffef))
+#define SET_TXQ1_MTX_Q_TXOP_FRC_BUR(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xffffffdf))
+#define SET_TXQ1_MTX_Q_RND_MODE(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xffffff3f))
+#define SET_TXQ1_MTX_Q_AIFSN(_VAL_) (REG32(ADR_TXQ1_MTX_Q_AIFSN)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0xfffffff0))
+#define SET_TXQ1_MTX_Q_ECWMIN(_VAL_) (REG32(ADR_TXQ1_MTX_Q_AIFSN)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0xfffff0ff))
+#define SET_TXQ1_MTX_Q_ECWMAX(_VAL_) (REG32(ADR_TXQ1_MTX_Q_AIFSN)) = (((_VAL_) << 12) | ((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0xffff0fff))
+#define SET_TXQ1_MTX_Q_TXOP_LIMIT(_VAL_) (REG32(ADR_TXQ1_MTX_Q_AIFSN)) = (((_VAL_) << 16) | ((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0x0000ffff))
+#define SET_TXQ1_MTX_Q_BKF_CNT(_VAL_) (REG32(ADR_TXQ1_MTX_Q_BKF_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_BKF_CNT)) & 0xffff0000))
+#define SET_TXQ1_MTX_Q_SRC_LIMIT(_VAL_) (REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) & 0xffffff00))
+#define SET_TXQ1_MTX_Q_LRC_LIMIT(_VAL_) (REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) & 0xffff00ff))
+#define SET_TXQ1_MTX_Q_ID_MAP_L(_VAL_) (REG32(ADR_TXQ1_MTX_Q_ID_MAP_L)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_ID_MAP_L)) & 0x00000000))
+#define SET_TXQ1_MTX_Q_TXOP_CH_THD(_VAL_) (REG32(ADR_TXQ1_MTX_Q_TXOP_CH_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_TXOP_CH_THD)) & 0xffff0000))
+#define SET_TXQ1_MTX_Q_TXOP_OV_THD(_VAL_) (REG32(ADR_TXQ1_MTX_Q_TXOP_OV_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_TXOP_OV_THD)) & 0xffff0000))
+#define SET_TXQ2_MTX_Q_PRE_LD(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xfffffffd))
+#define SET_TXQ2_MTX_Q_BKF_CNT_FIXED(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 2) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xfffffffb))
+#define SET_TXQ2_MTX_Q_TXOP_SUB_FRM_TIME(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 3) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xfffffff7))
+#define SET_TXQ2_MTX_Q_MB_NO_RLS(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 4) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xffffffef))
+#define SET_TXQ2_MTX_Q_TXOP_FRC_BUR(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xffffffdf))
+#define SET_TXQ2_MTX_Q_RND_MODE(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xffffff3f))
+#define SET_TXQ2_MTX_Q_AIFSN(_VAL_) (REG32(ADR_TXQ2_MTX_Q_AIFSN)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0xfffffff0))
+#define SET_TXQ2_MTX_Q_ECWMIN(_VAL_) (REG32(ADR_TXQ2_MTX_Q_AIFSN)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0xfffff0ff))
+#define SET_TXQ2_MTX_Q_ECWMAX(_VAL_) (REG32(ADR_TXQ2_MTX_Q_AIFSN)) = (((_VAL_) << 12) | ((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0xffff0fff))
+#define SET_TXQ2_MTX_Q_TXOP_LIMIT(_VAL_) (REG32(ADR_TXQ2_MTX_Q_AIFSN)) = (((_VAL_) << 16) | ((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0x0000ffff))
+#define SET_TXQ2_MTX_Q_BKF_CNT(_VAL_) (REG32(ADR_TXQ2_MTX_Q_BKF_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_BKF_CNT)) & 0xffff0000))
+#define SET_TXQ2_MTX_Q_SRC_LIMIT(_VAL_) (REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) & 0xffffff00))
+#define SET_TXQ2_MTX_Q_LRC_LIMIT(_VAL_) (REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) & 0xffff00ff))
+#define SET_TXQ2_MTX_Q_ID_MAP_L(_VAL_) (REG32(ADR_TXQ2_MTX_Q_ID_MAP_L)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_ID_MAP_L)) & 0x00000000))
+#define SET_TXQ2_MTX_Q_TXOP_CH_THD(_VAL_) (REG32(ADR_TXQ2_MTX_Q_TXOP_CH_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_TXOP_CH_THD)) & 0xffff0000))
+#define SET_TXQ2_MTX_Q_TXOP_OV_THD(_VAL_) (REG32(ADR_TXQ2_MTX_Q_TXOP_OV_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_TXOP_OV_THD)) & 0xffff0000))
+#define SET_TXQ3_MTX_Q_PRE_LD(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xfffffffd))
+#define SET_TXQ3_MTX_Q_BKF_CNT_FIXED(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 2) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xfffffffb))
+#define SET_TXQ3_MTX_Q_TXOP_SUB_FRM_TIME(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 3) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xfffffff7))
+#define SET_TXQ3_MTX_Q_MB_NO_RLS(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 4) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xffffffef))
+#define SET_TXQ3_MTX_Q_TXOP_FRC_BUR(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xffffffdf))
+#define SET_TXQ3_MTX_Q_RND_MODE(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xffffff3f))
+#define SET_TXQ3_MTX_Q_AIFSN(_VAL_) (REG32(ADR_TXQ3_MTX_Q_AIFSN)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0xfffffff0))
+#define SET_TXQ3_MTX_Q_ECWMIN(_VAL_) (REG32(ADR_TXQ3_MTX_Q_AIFSN)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0xfffff0ff))
+#define SET_TXQ3_MTX_Q_ECWMAX(_VAL_) (REG32(ADR_TXQ3_MTX_Q_AIFSN)) = (((_VAL_) << 12) | ((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0xffff0fff))
+#define SET_TXQ3_MTX_Q_TXOP_LIMIT(_VAL_) (REG32(ADR_TXQ3_MTX_Q_AIFSN)) = (((_VAL_) << 16) | ((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0x0000ffff))
+#define SET_TXQ3_MTX_Q_BKF_CNT(_VAL_) (REG32(ADR_TXQ3_MTX_Q_BKF_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_BKF_CNT)) & 0xffff0000))
+#define SET_TXQ3_MTX_Q_SRC_LIMIT(_VAL_) (REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) & 0xffffff00))
+#define SET_TXQ3_MTX_Q_LRC_LIMIT(_VAL_) (REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) & 0xffff00ff))
+#define SET_TXQ3_MTX_Q_ID_MAP_L(_VAL_) (REG32(ADR_TXQ3_MTX_Q_ID_MAP_L)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_ID_MAP_L)) & 0x00000000))
+#define SET_TXQ3_MTX_Q_TXOP_CH_THD(_VAL_) (REG32(ADR_TXQ3_MTX_Q_TXOP_CH_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_TXOP_CH_THD)) & 0xffff0000))
+#define SET_TXQ3_MTX_Q_TXOP_OV_THD(_VAL_) (REG32(ADR_TXQ3_MTX_Q_TXOP_OV_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_TXOP_OV_THD)) & 0xffff0000))
+#define SET_TXQ4_MTX_Q_PRE_LD(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xfffffffd))
+#define SET_TXQ4_MTX_Q_BKF_CNT_FIXED(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 2) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xfffffffb))
+#define SET_TXQ4_MTX_Q_TXOP_SUB_FRM_TIME(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 3) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xfffffff7))
+#define SET_TXQ4_MTX_Q_MB_NO_RLS(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 4) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xffffffef))
+#define SET_TXQ4_MTX_Q_TXOP_FRC_BUR(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xffffffdf))
+#define SET_TXQ4_MTX_Q_RND_MODE(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xffffff3f))
+#define SET_TXQ4_MTX_Q_AIFSN(_VAL_) (REG32(ADR_TXQ4_MTX_Q_AIFSN)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0xfffffff0))
+#define SET_TXQ4_MTX_Q_ECWMIN(_VAL_) (REG32(ADR_TXQ4_MTX_Q_AIFSN)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0xfffff0ff))
+#define SET_TXQ4_MTX_Q_ECWMAX(_VAL_) (REG32(ADR_TXQ4_MTX_Q_AIFSN)) = (((_VAL_) << 12) | ((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0xffff0fff))
+#define SET_TXQ4_MTX_Q_TXOP_LIMIT(_VAL_) (REG32(ADR_TXQ4_MTX_Q_AIFSN)) = (((_VAL_) << 16) | ((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0x0000ffff))
+#define SET_TXQ4_MTX_Q_BKF_CNT(_VAL_) (REG32(ADR_TXQ4_MTX_Q_BKF_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_BKF_CNT)) & 0xffff0000))
+#define SET_TXQ4_MTX_Q_SRC_LIMIT(_VAL_) (REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) & 0xffffff00))
+#define SET_TXQ4_MTX_Q_LRC_LIMIT(_VAL_) (REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) & 0xffff00ff))
+#define SET_TXQ4_MTX_Q_ID_MAP_L(_VAL_) (REG32(ADR_TXQ4_MTX_Q_ID_MAP_L)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_ID_MAP_L)) & 0x00000000))
+#define SET_TXQ4_MTX_Q_TXOP_CH_THD(_VAL_) (REG32(ADR_TXQ4_MTX_Q_TXOP_CH_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_TXOP_CH_THD)) & 0xffff0000))
+#define SET_TXQ4_MTX_Q_TXOP_OV_THD(_VAL_) (REG32(ADR_TXQ4_MTX_Q_TXOP_OV_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_TXOP_OV_THD)) & 0xffff0000))
+#define SET_VALID0(_VAL_) (REG32(ADR_WSID0)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0)) & 0xfffffffe))
+#define SET_PEER_QOS_EN0(_VAL_) (REG32(ADR_WSID0)) = (((_VAL_) << 1) | ((REG32(ADR_WSID0)) & 0xfffffffd))
+#define SET_PEER_OP_MODE0(_VAL_) (REG32(ADR_WSID0)) = (((_VAL_) << 2) | ((REG32(ADR_WSID0)) & 0xfffffff3))
+#define SET_PEER_HT_MODE0(_VAL_) (REG32(ADR_WSID0)) = (((_VAL_) << 4) | ((REG32(ADR_WSID0)) & 0xffffffcf))
+#define SET_PEER_MAC0_31_0(_VAL_) (REG32(ADR_PEER_MAC0_0)) = (((_VAL_) << 0) | ((REG32(ADR_PEER_MAC0_0)) & 0x00000000))
+#define SET_PEER_MAC0_47_32(_VAL_) (REG32(ADR_PEER_MAC0_1)) = (((_VAL_) << 0) | ((REG32(ADR_PEER_MAC0_1)) & 0xffff0000))
+#define SET_TX_ACK_POLICY_0_0(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_0)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_0_0(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_0)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_0_1(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_1)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_0_1(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_1)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_0_2(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_2)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_0_2(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_2)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_0_3(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_3)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_3)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_0_3(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_3)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_3)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_0_4(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_4)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_4)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_0_4(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_4)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_4)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_0_5(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_5)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_5)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_0_5(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_5)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_5)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_0_6(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_6)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_6)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_0_6(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_6)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_6)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_0_7(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_7)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_7)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_0_7(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_7)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_7)) & 0xfffff000))
+#define SET_VALID1(_VAL_) (REG32(ADR_WSID1)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1)) & 0xfffffffe))
+#define SET_PEER_QOS_EN1(_VAL_) (REG32(ADR_WSID1)) = (((_VAL_) << 1) | ((REG32(ADR_WSID1)) & 0xfffffffd))
+#define SET_PEER_OP_MODE1(_VAL_) (REG32(ADR_WSID1)) = (((_VAL_) << 2) | ((REG32(ADR_WSID1)) & 0xfffffff3))
+#define SET_PEER_HT_MODE1(_VAL_) (REG32(ADR_WSID1)) = (((_VAL_) << 4) | ((REG32(ADR_WSID1)) & 0xffffffcf))
+#define SET_PEER_MAC1_31_0(_VAL_) (REG32(ADR_PEER_MAC1_0)) = (((_VAL_) << 0) | ((REG32(ADR_PEER_MAC1_0)) & 0x00000000))
+#define SET_PEER_MAC1_47_32(_VAL_) (REG32(ADR_PEER_MAC1_1)) = (((_VAL_) << 0) | ((REG32(ADR_PEER_MAC1_1)) & 0xffff0000))
+#define SET_TX_ACK_POLICY_1_0(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_0)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_1_0(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_0)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_1_1(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_1)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_1_1(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_1)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_1_2(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_2)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_1_2(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_2)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_1_3(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_3)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_3)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_1_3(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_3)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_3)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_1_4(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_4)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_4)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_1_4(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_4)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_4)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_1_5(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_5)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_5)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_1_5(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_5)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_5)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_1_6(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_6)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_6)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_1_6(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_6)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_6)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_1_7(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_7)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_7)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_1_7(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_7)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_7)) & 0xfffff000))
+#define SET_INFO0(_VAL_) (REG32(ADR_INFO0)) = (((_VAL_) << 0) | ((REG32(ADR_INFO0)) & 0x00000000))
+#define SET_INFO1(_VAL_) (REG32(ADR_INFO1)) = (((_VAL_) << 0) | ((REG32(ADR_INFO1)) & 0x00000000))
+#define SET_INFO2(_VAL_) (REG32(ADR_INFO2)) = (((_VAL_) << 0) | ((REG32(ADR_INFO2)) & 0x00000000))
+#define SET_INFO3(_VAL_) (REG32(ADR_INFO3)) = (((_VAL_) << 0) | ((REG32(ADR_INFO3)) & 0x00000000))
+#define SET_INFO4(_VAL_) (REG32(ADR_INFO4)) = (((_VAL_) << 0) | ((REG32(ADR_INFO4)) & 0x00000000))
+#define SET_INFO5(_VAL_) (REG32(ADR_INFO5)) = (((_VAL_) << 0) | ((REG32(ADR_INFO5)) & 0x00000000))
+#define SET_INFO6(_VAL_) (REG32(ADR_INFO6)) = (((_VAL_) << 0) | ((REG32(ADR_INFO6)) & 0x00000000))
+#define SET_INFO7(_VAL_) (REG32(ADR_INFO7)) = (((_VAL_) << 0) | ((REG32(ADR_INFO7)) & 0x00000000))
+#define SET_INFO8(_VAL_) (REG32(ADR_INFO8)) = (((_VAL_) << 0) | ((REG32(ADR_INFO8)) & 0x00000000))
+#define SET_INFO9(_VAL_) (REG32(ADR_INFO9)) = (((_VAL_) << 0) | ((REG32(ADR_INFO9)) & 0x00000000))
+#define SET_INFO10(_VAL_) (REG32(ADR_INFO10)) = (((_VAL_) << 0) | ((REG32(ADR_INFO10)) & 0x00000000))
+#define SET_INFO11(_VAL_) (REG32(ADR_INFO11)) = (((_VAL_) << 0) | ((REG32(ADR_INFO11)) & 0x00000000))
+#define SET_INFO12(_VAL_) (REG32(ADR_INFO12)) = (((_VAL_) << 0) | ((REG32(ADR_INFO12)) & 0x00000000))
+#define SET_INFO13(_VAL_) (REG32(ADR_INFO13)) = (((_VAL_) << 0) | ((REG32(ADR_INFO13)) & 0x00000000))
+#define SET_INFO14(_VAL_) (REG32(ADR_INFO14)) = (((_VAL_) << 0) | ((REG32(ADR_INFO14)) & 0x00000000))
+#define SET_INFO15(_VAL_) (REG32(ADR_INFO15)) = (((_VAL_) << 0) | ((REG32(ADR_INFO15)) & 0x00000000))
+#define SET_INFO16(_VAL_) (REG32(ADR_INFO16)) = (((_VAL_) << 0) | ((REG32(ADR_INFO16)) & 0x00000000))
+#define SET_INFO17(_VAL_) (REG32(ADR_INFO17)) = (((_VAL_) << 0) | ((REG32(ADR_INFO17)) & 0x00000000))
+#define SET_INFO18(_VAL_) (REG32(ADR_INFO18)) = (((_VAL_) << 0) | ((REG32(ADR_INFO18)) & 0x00000000))
+#define SET_INFO19(_VAL_) (REG32(ADR_INFO19)) = (((_VAL_) << 0) | ((REG32(ADR_INFO19)) & 0x00000000))
+#define SET_INFO20(_VAL_) (REG32(ADR_INFO20)) = (((_VAL_) << 0) | ((REG32(ADR_INFO20)) & 0x00000000))
+#define SET_INFO21(_VAL_) (REG32(ADR_INFO21)) = (((_VAL_) << 0) | ((REG32(ADR_INFO21)) & 0x00000000))
+#define SET_INFO22(_VAL_) (REG32(ADR_INFO22)) = (((_VAL_) << 0) | ((REG32(ADR_INFO22)) & 0x00000000))
+#define SET_INFO23(_VAL_) (REG32(ADR_INFO23)) = (((_VAL_) << 0) | ((REG32(ADR_INFO23)) & 0x00000000))
+#define SET_INFO24(_VAL_) (REG32(ADR_INFO24)) = (((_VAL_) << 0) | ((REG32(ADR_INFO24)) & 0x00000000))
+#define SET_INFO25(_VAL_) (REG32(ADR_INFO25)) = (((_VAL_) << 0) | ((REG32(ADR_INFO25)) & 0x00000000))
+#define SET_INFO26(_VAL_) (REG32(ADR_INFO26)) = (((_VAL_) << 0) | ((REG32(ADR_INFO26)) & 0x00000000))
+#define SET_INFO27(_VAL_) (REG32(ADR_INFO27)) = (((_VAL_) << 0) | ((REG32(ADR_INFO27)) & 0x00000000))
+#define SET_INFO28(_VAL_) (REG32(ADR_INFO28)) = (((_VAL_) << 0) | ((REG32(ADR_INFO28)) & 0x00000000))
+#define SET_INFO29(_VAL_) (REG32(ADR_INFO29)) = (((_VAL_) << 0) | ((REG32(ADR_INFO29)) & 0x00000000))
+#define SET_INFO30(_VAL_) (REG32(ADR_INFO30)) = (((_VAL_) << 0) | ((REG32(ADR_INFO30)) & 0x00000000))
+#define SET_INFO31(_VAL_) (REG32(ADR_INFO31)) = (((_VAL_) << 0) | ((REG32(ADR_INFO31)) & 0x00000000))
+#define SET_INFO32(_VAL_) (REG32(ADR_INFO32)) = (((_VAL_) << 0) | ((REG32(ADR_INFO32)) & 0x00000000))
+#define SET_INFO33(_VAL_) (REG32(ADR_INFO33)) = (((_VAL_) << 0) | ((REG32(ADR_INFO33)) & 0x00000000))
+#define SET_INFO34(_VAL_) (REG32(ADR_INFO34)) = (((_VAL_) << 0) | ((REG32(ADR_INFO34)) & 0x00000000))
+#define SET_INFO35(_VAL_) (REG32(ADR_INFO35)) = (((_VAL_) << 0) | ((REG32(ADR_INFO35)) & 0x00000000))
+#define SET_INFO36(_VAL_) (REG32(ADR_INFO36)) = (((_VAL_) << 0) | ((REG32(ADR_INFO36)) & 0x00000000))
+#define SET_INFO37(_VAL_) (REG32(ADR_INFO37)) = (((_VAL_) << 0) | ((REG32(ADR_INFO37)) & 0x00000000))
+#define SET_INFO38(_VAL_) (REG32(ADR_INFO38)) = (((_VAL_) << 0) | ((REG32(ADR_INFO38)) & 0x00000000))
+#define SET_INFO_MASK(_VAL_) (REG32(ADR_INFO_MASK)) = (((_VAL_) << 0) | ((REG32(ADR_INFO_MASK)) & 0x00000000))
+#define SET_INFO_DEF_RATE(_VAL_) (REG32(ADR_INFO_RATE_OFFSET)) = (((_VAL_) << 0) | ((REG32(ADR_INFO_RATE_OFFSET)) & 0xffffffc0))
+#define SET_INFO_MRX_OFFSET(_VAL_) (REG32(ADR_INFO_RATE_OFFSET)) = (((_VAL_) << 16) | ((REG32(ADR_INFO_RATE_OFFSET)) & 0xfff0ffff))
+#define SET_BCAST_RATEUNKNOW(_VAL_) (REG32(ADR_INFO_RATE_OFFSET)) = (((_VAL_) << 24) | ((REG32(ADR_INFO_RATE_OFFSET)) & 0xc0ffffff))
+#define SET_INFO_IDX_TBL_ADDR(_VAL_) (REG32(ADR_INFO_IDX_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_INFO_IDX_ADDR)) & 0x00000000))
+#define SET_INFO_LEN_TBL_ADDR(_VAL_) (REG32(ADR_INFO_LEN_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_INFO_LEN_ADDR)) & 0x00000000))
+#define SET_IC_TAG_31_0(_VAL_) (REG32(ADR_IC_TIME_TAG_0)) = (((_VAL_) << 0) | ((REG32(ADR_IC_TIME_TAG_0)) & 0x00000000))
+#define SET_IC_TAG_63_32(_VAL_) (REG32(ADR_IC_TIME_TAG_1)) = (((_VAL_) << 0) | ((REG32(ADR_IC_TIME_TAG_1)) & 0x00000000))
+#define SET_CH1_PRI(_VAL_) (REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0xfffffffc))
+#define SET_CH2_PRI(_VAL_) (REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) = (((_VAL_) << 8) | ((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0xfffffcff))
+#define SET_CH3_PRI(_VAL_) (REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) = (((_VAL_) << 16) | ((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0xfffcffff))
+#define SET_RG_MAC_LPBK(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_MAC_MODE)) & 0xfffffffe))
+#define SET_RG_MAC_M2M(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 1) | ((REG32(ADR_MAC_MODE)) & 0xfffffffd))
+#define SET_RG_PHY_LPBK(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 2) | ((REG32(ADR_MAC_MODE)) & 0xfffffffb))
+#define SET_RG_LPBK_RX_EN(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 3) | ((REG32(ADR_MAC_MODE)) & 0xfffffff7))
+#define SET_EXT_MAC_MODE(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 4) | ((REG32(ADR_MAC_MODE)) & 0xffffffef))
+#define SET_EXT_PHY_MODE(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 5) | ((REG32(ADR_MAC_MODE)) & 0xffffffdf))
+#define SET_ASIC_TAG(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 24) | ((REG32(ADR_MAC_MODE)) & 0x00ffffff))
+#define SET_HCI_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 0) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffffffe))
+#define SET_CO_PROC_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 1) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffffffd))
+#define SET_MTX_MISC_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 3) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffffff7))
+#define SET_MTX_QUE_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 4) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffffef))
+#define SET_MTX_CHST_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 5) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffffdf))
+#define SET_MTX_BCN_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 6) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffffbf))
+#define SET_MRX_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 7) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffff7f))
+#define SET_AMPDU_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 8) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffffeff))
+#define SET_MMU_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 9) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffffdff))
+#define SET_ID_MNG_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 11) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffff7ff))
+#define SET_MBOX_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 12) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffefff))
+#define SET_SCRT_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 13) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffdfff))
+#define SET_MIC_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 14) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffbfff))
+#define SET_CO_PROC_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 1) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xfffffffd))
+#define SET_MTX_MISC_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 3) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xfffffff7))
+#define SET_MTX_QUE_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 4) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffffffef))
+#define SET_MTX_CHST_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 5) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffffffdf))
+#define SET_MTX_BCN_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 6) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffffffbf))
+#define SET_MRX_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 7) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffffff7f))
+#define SET_AMPDU_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 8) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xfffffeff))
+#define SET_ID_MNG_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 14) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffffbfff))
+#define SET_MBOX_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 15) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffff7fff))
+#define SET_SCRT_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 16) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xfffeffff))
+#define SET_MIC_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 17) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xfffdffff))
+#define SET_CO_PROC_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 1) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffffffd))
+#define SET_MTX_MISC_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 3) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffffff7))
+#define SET_MTX_QUE0_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 4) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffffef))
+#define SET_MTX_QUE1_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 5) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffffdf))
+#define SET_MTX_QUE2_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 6) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffffbf))
+#define SET_MTX_QUE3_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 7) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffff7f))
+#define SET_MTX_QUE4_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 8) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffffeff))
+#define SET_MTX_QUE5_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 9) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffffdff))
+#define SET_MRX_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 10) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffffbff))
+#define SET_AMPDU_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 11) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffff7ff))
+#define SET_SCRT_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 13) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffdfff))
+#define SET_ID_MNG_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 14) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffbfff))
+#define SET_MBOX_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 15) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffff7fff))
+#define SET_HCI_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 0) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffffffe))
+#define SET_CO_PROC_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 1) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffffffd))
+#define SET_MTX_MISC_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 3) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffffff7))
+#define SET_MTX_QUE_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 4) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffffef))
+#define SET_MRX_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 5) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffffdf))
+#define SET_AMPDU_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 6) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffffbf))
+#define SET_MMU_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 7) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffff7f))
+#define SET_ID_MNG_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 9) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffffdff))
+#define SET_MBOX_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 10) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffffbff))
+#define SET_SCRT_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 11) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffff7ff))
+#define SET_MIC_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 12) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffefff))
+#define SET_MIB_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 13) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffdfff))
+#define SET_HCI_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 0) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xfffffffe))
+#define SET_CO_PROC_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 1) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xfffffffd))
+#define SET_MTX_MISC_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 3) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xfffffff7))
+#define SET_MTX_QUE_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 4) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffffef))
+#define SET_MRX_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 5) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffffdf))
+#define SET_AMPDU_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 6) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffffbf))
+#define SET_ID_MNG_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 12) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffefff))
+#define SET_MBOX_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 13) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffdfff))
+#define SET_SCRT_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 14) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffbfff))
+#define SET_MIC_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 15) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffff7fff))
+#define SET_CO_PROC_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 1) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xfffffffd))
+#define SET_MRX_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 10) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xfffffbff))
+#define SET_AMPDU_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 11) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xfffff7ff))
+#define SET_SCRT_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 13) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xffffdfff))
+#define SET_ID_MNG_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 14) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xffffbfff))
+#define SET_MBOX_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 15) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xffff7fff))
+#define SET_OP_MODE(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 0) | ((REG32(ADR_GLBLE_SET)) & 0xfffffffc))
+#define SET_HT_MODE(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 2) | ((REG32(ADR_GLBLE_SET)) & 0xfffffff3))
+#define SET_QOS_EN(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 4) | ((REG32(ADR_GLBLE_SET)) & 0xffffffef))
+#define SET_PB_OFFSET(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 8) | ((REG32(ADR_GLBLE_SET)) & 0xffff00ff))
+#define SET_SNIFFER_MODE(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 16) | ((REG32(ADR_GLBLE_SET)) & 0xfffeffff))
+#define SET_DUP_FLT(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 17) | ((REG32(ADR_GLBLE_SET)) & 0xfffdffff))
+#define SET_TX_PKT_RSVD(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 18) | ((REG32(ADR_GLBLE_SET)) & 0xffe3ffff))
+#define SET_AMPDU_SNIFFER(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 21) | ((REG32(ADR_GLBLE_SET)) & 0xffdfffff))
+#define SET_REASON_TRAP0(_VAL_) (REG32(ADR_REASON_TRAP0)) = (((_VAL_) << 0) | ((REG32(ADR_REASON_TRAP0)) & 0x00000000))
+#define SET_REASON_TRAP1(_VAL_) (REG32(ADR_REASON_TRAP1)) = (((_VAL_) << 0) | ((REG32(ADR_REASON_TRAP1)) & 0x00000000))
+#define SET_BSSID_31_0(_VAL_) (REG32(ADR_BSSID_0)) = (((_VAL_) << 0) | ((REG32(ADR_BSSID_0)) & 0x00000000))
+#define SET_BSSID_47_32(_VAL_) (REG32(ADR_BSSID_1)) = (((_VAL_) << 0) | ((REG32(ADR_BSSID_1)) & 0xffff0000))
+#define SET_SCRT_STATE(_VAL_) (REG32(ADR_SCRT_STATE)) = (((_VAL_) << 0) | ((REG32(ADR_SCRT_STATE)) & 0xfffffff0))
+#define SET_STA_MAC_31_0(_VAL_) (REG32(ADR_STA_MAC_0)) = (((_VAL_) << 0) | ((REG32(ADR_STA_MAC_0)) & 0x00000000))
+#define SET_STA_MAC_47_32(_VAL_) (REG32(ADR_STA_MAC_1)) = (((_VAL_) << 0) | ((REG32(ADR_STA_MAC_1)) & 0xffff0000))
+#define SET_PAIR_SCRT(_VAL_) (REG32(ADR_SCRT_SET)) = (((_VAL_) << 0) | ((REG32(ADR_SCRT_SET)) & 0xfffffff8))
+#define SET_GRP_SCRT(_VAL_) (REG32(ADR_SCRT_SET)) = (((_VAL_) << 3) | ((REG32(ADR_SCRT_SET)) & 0xffffffc7))
+#define SET_SCRT_PKT_ID(_VAL_) (REG32(ADR_SCRT_SET)) = (((_VAL_) << 6) | ((REG32(ADR_SCRT_SET)) & 0xffffe03f))
+#define SET_SCRT_RPLY_IGNORE(_VAL_) (REG32(ADR_SCRT_SET)) = (((_VAL_) << 16) | ((REG32(ADR_SCRT_SET)) & 0xfffeffff))
+#define SET_COEXIST_EN(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 0) | ((REG32(ADR_BTCX0)) & 0xfffffffe))
+#define SET_WIRE_MODE(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 1) | ((REG32(ADR_BTCX0)) & 0xfffffff1))
+#define SET_WL_RX_PRI(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 4) | ((REG32(ADR_BTCX0)) & 0xffffffef))
+#define SET_WL_TX_PRI(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 5) | ((REG32(ADR_BTCX0)) & 0xffffffdf))
+#define SET_GURAN_USE_EN(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 8) | ((REG32(ADR_BTCX0)) & 0xfffffeff))
+#define SET_GURAN_USE_CTRL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 9) | ((REG32(ADR_BTCX0)) & 0xfffffdff))
+#define SET_BEACON_TIMEOUT_EN(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 10) | ((REG32(ADR_BTCX0)) & 0xfffffbff))
+#define SET_WLAN_ACT_POL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 11) | ((REG32(ADR_BTCX0)) & 0xfffff7ff))
+#define SET_DUAL_ANT_EN(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 12) | ((REG32(ADR_BTCX0)) & 0xffffefff))
+#define SET_TRSW_PHY_POL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 16) | ((REG32(ADR_BTCX0)) & 0xfffeffff))
+#define SET_WIFI_TX_SW_POL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 17) | ((REG32(ADR_BTCX0)) & 0xfffdffff))
+#define SET_WIFI_RX_SW_POL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 18) | ((REG32(ADR_BTCX0)) & 0xfffbffff))
+#define SET_BT_SW_POL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 19) | ((REG32(ADR_BTCX0)) & 0xfff7ffff))
+#define SET_BT_PRI_SMP_TIME(_VAL_) (REG32(ADR_BTCX1)) = (((_VAL_) << 0) | ((REG32(ADR_BTCX1)) & 0xffffff00))
+#define SET_BT_STA_SMP_TIME(_VAL_) (REG32(ADR_BTCX1)) = (((_VAL_) << 8) | ((REG32(ADR_BTCX1)) & 0xffff00ff))
+#define SET_BEACON_TIMEOUT(_VAL_) (REG32(ADR_BTCX1)) = (((_VAL_) << 16) | ((REG32(ADR_BTCX1)) & 0xff00ffff))
+#define SET_WLAN_REMAIN_TIME(_VAL_) (REG32(ADR_BTCX1)) = (((_VAL_) << 24) | ((REG32(ADR_BTCX1)) & 0x00ffffff))
+#define SET_SW_MANUAL_EN(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 0) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffffe))
+#define SET_SW_WL_TX(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 1) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffffd))
+#define SET_SW_WL_RX(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 2) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffffb))
+#define SET_SW_BT_TRX(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 3) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffff7))
+#define SET_BT_TXBAR_MANUAL_EN(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 4) | ((REG32(ADR_SWITCH_CTL)) & 0xffffffef))
+#define SET_BT_TXBAR_SET(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 5) | ((REG32(ADR_SWITCH_CTL)) & 0xffffffdf))
+#define SET_BT_BUSY_MANUAL_EN(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 8) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffeff))
+#define SET_BT_BUSY_SET(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 9) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffdff))
+#define SET_G0_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 2) | ((REG32(ADR_MIB_EN)) & 0xfffffffb))
+#define SET_G0_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 3) | ((REG32(ADR_MIB_EN)) & 0xfffffff7))
+#define SET_G1_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 4) | ((REG32(ADR_MIB_EN)) & 0xffffffef))
+#define SET_G1_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 5) | ((REG32(ADR_MIB_EN)) & 0xffffffdf))
+#define SET_Q0_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 6) | ((REG32(ADR_MIB_EN)) & 0xffffffbf))
+#define SET_Q0_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 7) | ((REG32(ADR_MIB_EN)) & 0xffffff7f))
+#define SET_Q1_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 8) | ((REG32(ADR_MIB_EN)) & 0xfffffeff))
+#define SET_Q1_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 9) | ((REG32(ADR_MIB_EN)) & 0xfffffdff))
+#define SET_Q2_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 10) | ((REG32(ADR_MIB_EN)) & 0xfffffbff))
+#define SET_Q2_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 11) | ((REG32(ADR_MIB_EN)) & 0xfffff7ff))
+#define SET_Q3_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 12) | ((REG32(ADR_MIB_EN)) & 0xffffefff))
+#define SET_Q3_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 13) | ((REG32(ADR_MIB_EN)) & 0xffffdfff))
+#define SET_SCRT_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 14) | ((REG32(ADR_MIB_EN)) & 0xffffbfff))
+#define SET_SCRT_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 15) | ((REG32(ADR_MIB_EN)) & 0xffff7fff))
+#define SET_MISC_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 16) | ((REG32(ADR_MIB_EN)) & 0xfffeffff))
+#define SET_MISC_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 17) | ((REG32(ADR_MIB_EN)) & 0xfffdffff))
+#define SET_MTX_WSID0_SUCC(_VAL_) (REG32(ADR_MTX_WSID0_SUCC)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_WSID0_SUCC)) & 0xffff0000))
+#define SET_MTX_WSID0_FRM(_VAL_) (REG32(ADR_MTX_WSID0_FRM)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_WSID0_FRM)) & 0xffff0000))
+#define SET_MTX_WSID0_RETRY(_VAL_) (REG32(ADR_MTX_WSID0_RETRY)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_WSID0_RETRY)) & 0xffff0000))
+#define SET_MTX_WSID0_TOTAL(_VAL_) (REG32(ADR_MTX_WSID0_TOTAL)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_WSID0_TOTAL)) & 0xffff0000))
+#define SET_MTX_GRP(_VAL_) (REG32(ADR_MTX_GROUP)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_GROUP)) & 0xfff00000))
+#define SET_MTX_FAIL(_VAL_) (REG32(ADR_MTX_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_FAIL)) & 0xffff0000))
+#define SET_MTX_RETRY(_VAL_) (REG32(ADR_MTX_RETRY)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_RETRY)) & 0xfff00000))
+#define SET_MTX_MULTI_RETRY(_VAL_) (REG32(ADR_MTX_MULTI_RETRY)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_MULTI_RETRY)) & 0xfff00000))
+#define SET_MTX_RTS_SUCC(_VAL_) (REG32(ADR_MTX_RTS_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_RTS_SUCCESS)) & 0xffff0000))
+#define SET_MTX_RTS_FAIL(_VAL_) (REG32(ADR_MTX_RTS_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_RTS_FAIL)) & 0xffff0000))
+#define SET_MTX_ACK_FAIL(_VAL_) (REG32(ADR_MTX_ACK_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_ACK_FAIL)) & 0xffff0000))
+#define SET_MTX_FRM(_VAL_) (REG32(ADR_MTX_FRM)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_FRM)) & 0xfff00000))
+#define SET_MTX_ACK_TX(_VAL_) (REG32(ADR_MTX_ACK_TX)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_ACK_TX)) & 0xffff0000))
+#define SET_MTX_CTS_TX(_VAL_) (REG32(ADR_MTX_CTS_TX)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_CTS_TX)) & 0xffff0000))
+#define SET_MRX_DUP(_VAL_) (REG32(ADR_MRX_DUP_FRM)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_DUP_FRM)) & 0xffff0000))
+#define SET_MRX_FRG(_VAL_) (REG32(ADR_MRX_FRG_FRM)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FRG_FRM)) & 0xfff00000))
+#define SET_MRX_GRP(_VAL_) (REG32(ADR_MRX_GROUP_FRM)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_GROUP_FRM)) & 0xfff00000))
+#define SET_MRX_FCS_ERR(_VAL_) (REG32(ADR_MRX_FCS_ERR)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FCS_ERR)) & 0xffff0000))
+#define SET_MRX_FCS_SUC(_VAL_) (REG32(ADR_MRX_FCS_SUCC)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FCS_SUCC)) & 0xffff0000))
+#define SET_MRX_MISS(_VAL_) (REG32(ADR_MRX_MISS)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MISS)) & 0xffff0000))
+#define SET_MRX_ALC_FAIL(_VAL_) (REG32(ADR_MRX_ALC_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_ALC_FAIL)) & 0xffff0000))
+#define SET_MRX_DAT_NTF(_VAL_) (REG32(ADR_MRX_DAT_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_DAT_NTF)) & 0xffff0000))
+#define SET_MRX_RTS_NTF(_VAL_) (REG32(ADR_MRX_RTS_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_RTS_NTF)) & 0xffff0000))
+#define SET_MRX_CTS_NTF(_VAL_) (REG32(ADR_MRX_CTS_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_CTS_NTF)) & 0xffff0000))
+#define SET_MRX_ACK_NTF(_VAL_) (REG32(ADR_MRX_ACK_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_ACK_NTF)) & 0xffff0000))
+#define SET_MRX_BA_NTF(_VAL_) (REG32(ADR_MRX_BA_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_BA_NTF)) & 0xffff0000))
+#define SET_MRX_DATA_NTF(_VAL_) (REG32(ADR_MRX_DATA_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_DATA_NTF)) & 0xffff0000))
+#define SET_MRX_MNG_NTF(_VAL_) (REG32(ADR_MRX_MNG_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MNG_NTF)) & 0xffff0000))
+#define SET_MRX_DAT_CRC_NTF(_VAL_) (REG32(ADR_MRX_DAT_CRC_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_DAT_CRC_NTF)) & 0xffff0000))
+#define SET_MRX_BAR_NTF(_VAL_) (REG32(ADR_MRX_BAR_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_BAR_NTF)) & 0xffff0000))
+#define SET_MRX_MB_MISS(_VAL_) (REG32(ADR_MRX_MB_MISS)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MB_MISS)) & 0xffff0000))
+#define SET_MRX_NIDLE_MISS(_VAL_) (REG32(ADR_MRX_NIDLE_MISS)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_NIDLE_MISS)) & 0xffff0000))
+#define SET_MRX_CSR_NTF(_VAL_) (REG32(ADR_MRX_CSR_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_CSR_NTF)) & 0xffff0000))
+#define SET_DBG_Q0_SUCC(_VAL_) (REG32(ADR_DBG_Q0_FRM_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q0_FRM_SUCCESS)) & 0xffff0000))
+#define SET_DBG_Q0_FAIL(_VAL_) (REG32(ADR_DBG_Q0_FRM_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q0_FRM_FAIL)) & 0xffff0000))
+#define SET_DBG_Q0_ACK_SUCC(_VAL_) (REG32(ADR_DBG_Q0_ACK_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q0_ACK_SUCCESS)) & 0xffff0000))
+#define SET_DBG_Q0_ACK_FAIL(_VAL_) (REG32(ADR_DBG_Q0_ACK_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q0_ACK_FAIL)) & 0xffff0000))
+#define SET_DBG_Q1_SUCC(_VAL_) (REG32(ADR_DBG_Q1_FRM_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q1_FRM_SUCCESS)) & 0xffff0000))
+#define SET_DBG_Q1_FAIL(_VAL_) (REG32(ADR_DBG_Q1_FRM_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q1_FRM_FAIL)) & 0xffff0000))
+#define SET_DBG_Q1_ACK_SUCC(_VAL_) (REG32(ADR_DBG_Q1_ACK_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q1_ACK_SUCCESS)) & 0xffff0000))
+#define SET_DBG_Q1_ACK_FAIL(_VAL_) (REG32(ADR_DBG_Q1_ACK_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q1_ACK_FAIL)) & 0xffff0000))
+#define SET_DBG_Q2_SUCC(_VAL_) (REG32(ADR_DBG_Q2_FRM_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q2_FRM_SUCCESS)) & 0xffff0000))
+#define SET_DBG_Q2_FAIL(_VAL_) (REG32(ADR_DBG_Q2_FRM_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q2_FRM_FAIL)) & 0xffff0000))
+#define SET_DBG_Q2_ACK_SUCC(_VAL_) (REG32(ADR_DBG_Q2_ACK_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q2_ACK_SUCCESS)) & 0xffff0000))
+#define SET_DBG_Q2_ACK_FAIL(_VAL_) (REG32(ADR_DBG_Q2_ACK_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q2_ACK_FAIL)) & 0xffff0000))
+#define SET_DBG_Q3_SUCC(_VAL_) (REG32(ADR_DBG_Q3_FRM_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q3_FRM_SUCCESS)) & 0xffff0000))
+#define SET_DBG_Q3_FAIL(_VAL_) (REG32(ADR_DBG_Q3_FRM_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q3_FRM_FAIL)) & 0xffff0000))
+#define SET_DBG_Q3_ACK_SUCC(_VAL_) (REG32(ADR_DBG_Q3_ACK_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q3_ACK_SUCCESS)) & 0xffff0000))
+#define SET_DBG_Q3_ACK_FAIL(_VAL_) (REG32(ADR_DBG_Q3_ACK_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q3_ACK_FAIL)) & 0xffff0000))
+#define SET_SCRT_TKIP_CERR(_VAL_) (REG32(ADR_MIB_SCRT_TKIP0)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_SCRT_TKIP0)) & 0xfff00000))
+#define SET_SCRT_TKIP_MIC_ERR(_VAL_) (REG32(ADR_MIB_SCRT_TKIP1)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_SCRT_TKIP1)) & 0xfff00000))
+#define SET_SCRT_TKIP_RPLY(_VAL_) (REG32(ADR_MIB_SCRT_TKIP2)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_SCRT_TKIP2)) & 0xfff00000))
+#define SET_SCRT_CCMP_RPLY(_VAL_) (REG32(ADR_MIB_SCRT_CCMP0)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_SCRT_CCMP0)) & 0xfff00000))
+#define SET_SCRT_CCMP_CERR(_VAL_) (REG32(ADR_MIB_SCRT_CCMP1)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_SCRT_CCMP1)) & 0xfff00000))
+#define SET_DBG_LEN_CRC_FAIL(_VAL_) (REG32(ADR_DBG_LEN_CRC_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_LEN_CRC_FAIL)) & 0xffff0000))
+#define SET_DBG_LEN_ALC_FAIL(_VAL_) (REG32(ADR_DBG_LEN_ALC_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_LEN_ALC_FAIL)) & 0xffff0000))
+#define SET_DBG_AMPDU_PASS(_VAL_) (REG32(ADR_DBG_AMPDU_PASS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_AMPDU_PASS)) & 0xffff0000))
+#define SET_DBG_AMPDU_FAIL(_VAL_) (REG32(ADR_DBG_AMPDU_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_AMPDU_FAIL)) & 0xffff0000))
+#define SET_RXID_ALC_CNT_FAIL(_VAL_) (REG32(ADR_ID_ALC_FAIL1)) = (((_VAL_) << 0) | ((REG32(ADR_ID_ALC_FAIL1)) & 0xffff0000))
+#define SET_RXID_ALC_LEN_FAIL(_VAL_) (REG32(ADR_ID_ALC_FAIL2)) = (((_VAL_) << 0) | ((REG32(ADR_ID_ALC_FAIL2)) & 0xffff0000))
+#define SET_CBR_RG_EN_MANUAL(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffe))
+#define SET_CBR_RG_TX_EN(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffd))
+#define SET_CBR_RG_TX_PA_EN(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffb))
+#define SET_CBR_RG_TX_DAC_EN(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffffff7))
+#define SET_CBR_RG_RX_AGC(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffffffef))
+#define SET_CBR_RG_RX_GAIN_MANUAL(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffffffdf))
+#define SET_CBR_RG_RFG(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffffff3f))
+#define SET_CBR_RG_PGAG(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffff0ff))
+#define SET_CBR_RG_MODE(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffffcfff))
+#define SET_CBR_RG_EN_TX_TRSW(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffffbfff))
+#define SET_CBR_RG_EN_SX(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffff7fff))
+#define SET_CBR_RG_EN_RX_LNA(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffeffff))
+#define SET_CBR_RG_EN_RX_MIXER(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 17) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffdffff))
+#define SET_CBR_RG_EN_RX_DIV2(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffbffff))
+#define SET_CBR_RG_EN_RX_LOBUF(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 19) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfff7ffff))
+#define SET_CBR_RG_EN_RX_TZ(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffefffff))
+#define SET_CBR_RG_EN_RX_FILTER(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffdfffff))
+#define SET_CBR_RG_EN_RX_HPF(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffbfffff))
+#define SET_CBR_RG_EN_RX_RSSI(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xff7fffff))
+#define SET_CBR_RG_EN_ADC(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfeffffff))
+#define SET_CBR_RG_EN_TX_MOD(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 25) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfdffffff))
+#define SET_CBR_RG_EN_TX_DIV2(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 26) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfbffffff))
+#define SET_CBR_RG_EN_TX_DIV2_BUF(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xf7ffffff))
+#define SET_CBR_RG_EN_TX_LOBF(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xefffffff))
+#define SET_CBR_RG_EN_RX_LOBF(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 29) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xdfffffff))
+#define SET_CBR_RG_SEL_DPLL_CLK(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 30) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xbfffffff))
+#define SET_CBR_RG_EN_TX_DPD(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffffe))
+#define SET_CBR_RG_EN_TX_TSSI(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffffd))
+#define SET_CBR_RG_EN_RX_IQCAL(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffffb))
+#define SET_CBR_RG_EN_TX_DAC_CAL(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffff7))
+#define SET_CBR_RG_EN_TX_SELF_MIXER(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xffffffef))
+#define SET_CBR_RG_EN_TX_DAC_OUT(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xffffffdf))
+#define SET_CBR_RG_EN_LDO_RX_FE(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xffffffbf))
+#define SET_CBR_RG_EN_LDO_ABB(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xffffff7f))
+#define SET_CBR_RG_EN_LDO_AFE(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffeff))
+#define SET_CBR_RG_EN_SX_CHPLDO(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffdff))
+#define SET_CBR_RG_EN_SX_LOBFLDO(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffbff))
+#define SET_CBR_RG_EN_IREF_RX(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffff7ff))
+#define SET_CBR_RG_DCDC_MODE(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xffffefff))
+#define SET_CBR_RG_LDO_LEVEL_RX_FE(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xfffffff8))
+#define SET_CBR_RG_LDO_LEVEL_ABB(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xffffffc7))
+#define SET_CBR_RG_LDO_LEVEL_AFE(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xfffffe3f))
+#define SET_CBR_RG_SX_LDO_CHP_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xfffff1ff))
+#define SET_CBR_RG_SX_LDO_LOBF_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xffff8fff))
+#define SET_CBR_RG_SX_LDO_XOSC_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xfffc7fff))
+#define SET_CBR_RG_DP_LDO_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xffe3ffff))
+#define SET_CBR_RG_SX_LDO_VCO_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xff1fffff))
+#define SET_CBR_RG_TX_LDO_TX_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xf8ffffff))
+#define SET_CBR_RG_BUCK_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xc7ffffff))
+#define SET_CBR_RG_EN_RX_PADSW(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffffe))
+#define SET_CBR_RG_EN_RX_TESTNODE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffffd))
+#define SET_CBR_RG_RX_ABBCFIX(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffffb))
+#define SET_CBR_RG_RX_ABBCTUNE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffe07))
+#define SET_CBR_RG_RX_ABBOUT_TRI_STATE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffdff))
+#define SET_CBR_RG_RX_ABB_N_MODE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffbff))
+#define SET_CBR_RG_RX_EN_LOOPA(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffff7ff))
+#define SET_CBR_RG_RX_FILTERI1ST(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xffffcfff))
+#define SET_CBR_RG_RX_FILTERI2ND(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xffff3fff))
+#define SET_CBR_RG_RX_FILTERI3RD(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffcffff))
+#define SET_CBR_RG_RX_FILTERI_COURSE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfff3ffff))
+#define SET_CBR_RG_RX_FILTERVCM(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xffcfffff))
+#define SET_CBR_RG_RX_HPF3M(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xffbfffff))
+#define SET_CBR_RG_RX_HPF300K(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xff7fffff))
+#define SET_CBR_RG_RX_HPFI(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfcffffff))
+#define SET_CBR_RG_RX_HPF_FINALCORNER(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 26) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xf3ffffff))
+#define SET_CBR_RG_RX_HPF_SETTLE1_C(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xcfffffff))
+#define SET_CBR_RG_RX_HPF_SETTLE1_R(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfffffffc))
+#define SET_CBR_RG_RX_HPF_SETTLE2_C(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfffffff3))
+#define SET_CBR_RG_RX_HPF_SETTLE2_R(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xffffffcf))
+#define SET_CBR_RG_RX_HPF_VCMCON2(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xffffff3f))
+#define SET_CBR_RG_RX_HPF_VCMCON(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfffffcff))
+#define SET_CBR_RG_RX_OUTVCM(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfffff3ff))
+#define SET_CBR_RG_RX_TZI(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xffffcfff))
+#define SET_CBR_RG_RX_TZ_OUT_TRISTATE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xffffbfff))
+#define SET_CBR_RG_RX_TZ_VCM(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfffe7fff))
+#define SET_CBR_RG_EN_RX_RSSI_TESTNODE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 17) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfff1ffff))
+#define SET_CBR_RG_RX_ADCRSSI_CLKSEL(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xffefffff))
+#define SET_CBR_RG_RX_ADCRSSI_VCM(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xff9fffff))
+#define SET_CBR_RG_RX_REC_LPFCORNER(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfe7fffff))
+#define SET_CBR_RG_RSSI_CLOCK_GATING(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 25) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfdffffff))
+#define SET_CBR_RG_TXPGA_CAPSW(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xfffffffc))
+#define SET_CBR_RG_TXPGA_MAIN(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xffffff03))
+#define SET_CBR_RG_TXPGA_STEER(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xffffc0ff))
+#define SET_CBR_RG_TXMOD_GMCELL(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xffff3fff))
+#define SET_CBR_RG_TXLPF_GMCELL(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xfffcffff))
+#define SET_CBR_RG_PACELL_EN(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xffe3ffff))
+#define SET_CBR_RG_PABIAS_CTRL(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xfe1fffff))
+#define SET_CBR_RG_PABIAS_AB(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 25) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xfdffffff))
+#define SET_CBR_RG_TX_DIV_VSET(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 26) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xf3ffffff))
+#define SET_CBR_RG_TX_LOBUF_VSET(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xcfffffff))
+#define SET_CBR_RG_RX_SQDC(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xfffffff8))
+#define SET_CBR_RG_RX_DIV2_CORE(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xffffffe7))
+#define SET_CBR_RG_RX_LOBUF(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xffffff9f))
+#define SET_CBR_RG_TX_DPDGM_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xfffff87f))
+#define SET_CBR_RG_TX_DPD_DIV(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xffff87ff))
+#define SET_CBR_RG_TX_TSSI_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xfffc7fff))
+#define SET_CBR_RG_TX_TSSI_DIV(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xffe3ffff))
+#define SET_CBR_RG_TX_TSSI_TESTMODE(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xffdfffff))
+#define SET_CBR_RG_TX_TSSI_TEST(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xff3fffff))
+#define SET_CBR_RG_RX_HG_LNA_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfffffffc))
+#define SET_CBR_RG_RX_HG_LNAHGN_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffffffc3))
+#define SET_CBR_RG_RX_HG_LNAHGP_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfffffc3f))
+#define SET_CBR_RG_RX_HG_LNALG_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffffc3ff))
+#define SET_CBR_RG_RX_HG_TZ_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffff3fff))
+#define SET_CBR_RG_RX_HG_TZ_CAP(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfff8ffff))
+#define SET_CBR_RG_RX_MG_LNA_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfffffffc))
+#define SET_CBR_RG_RX_MG_LNAHGN_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffffffc3))
+#define SET_CBR_RG_RX_MG_LNAHGP_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfffffc3f))
+#define SET_CBR_RG_RX_MG_LNALG_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffffc3ff))
+#define SET_CBR_RG_RX_MG_TZ_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffff3fff))
+#define SET_CBR_RG_RX_MG_TZ_CAP(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfff8ffff))
+#define SET_CBR_RG_RX_LG_LNA_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfffffffc))
+#define SET_CBR_RG_RX_LG_LNAHGN_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffffffc3))
+#define SET_CBR_RG_RX_LG_LNAHGP_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfffffc3f))
+#define SET_CBR_RG_RX_LG_LNALG_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffffc3ff))
+#define SET_CBR_RG_RX_LG_TZ_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffff3fff))
+#define SET_CBR_RG_RX_LG_TZ_CAP(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfff8ffff))
+#define SET_CBR_RG_RX_ULG_LNA_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfffffffc))
+#define SET_CBR_RG_RX_ULG_LNAHGN_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffffffc3))
+#define SET_CBR_RG_RX_ULG_LNAHGP_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfffffc3f))
+#define SET_CBR_RG_RX_ULG_LNALG_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffffc3ff))
+#define SET_CBR_RG_RX_ULG_TZ_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffff3fff))
+#define SET_CBR_RG_RX_ULG_TZ_CAP(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfff8ffff))
+#define SET_CBR_RG_HPF1_FAST_SET_X(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xfffffffe))
+#define SET_CBR_RG_HPF1_FAST_SET_Y(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xfffffffd))
+#define SET_CBR_RG_HPF1_FAST_SET_Z(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xfffffffb))
+#define SET_CBR_RG_HPF_T1A(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xffffffe7))
+#define SET_CBR_RG_HPF_T1B(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xffffff9f))
+#define SET_CBR_RG_HPF_T1C(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xfffffe7f))
+#define SET_CBR_RG_RX_LNA_TRI_SEL(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xfffff9ff))
+#define SET_CBR_RG_RX_LNA_SETTLE(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xffffe7ff))
+#define SET_CBR_RG_ADC_CLKSEL(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffffffe))
+#define SET_CBR_RG_ADC_DIBIAS(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffffff9))
+#define SET_CBR_RG_ADC_DIVR(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffffff7))
+#define SET_CBR_RG_ADC_DVCMI(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xffffffcf))
+#define SET_CBR_RG_ADC_SAMSEL(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffffc3f))
+#define SET_CBR_RG_ADC_STNBY(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffffbff))
+#define SET_CBR_RG_ADC_TESTMODE(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffff7ff))
+#define SET_CBR_RG_ADC_TSEL(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xffff0fff))
+#define SET_CBR_RG_ADC_VRSEL(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffcffff))
+#define SET_CBR_RG_DICMP(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfff3ffff))
+#define SET_CBR_RG_DIOP(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xffcfffff))
+#define SET_CBR_RG_DACI1ST(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xfffffffc))
+#define SET_CBR_RG_TX_DACLPF_ICOURSE(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xfffffff3))
+#define SET_CBR_RG_TX_DACLPF_IFINE(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffffffcf))
+#define SET_CBR_RG_TX_DACLPF_VCM(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffffff3f))
+#define SET_CBR_RG_TX_DAC_CKEDGE_SEL(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xfffffeff))
+#define SET_CBR_RG_TX_DAC_IBIAS(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xfffff9ff))
+#define SET_CBR_RG_TX_DAC_OS(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffffc7ff))
+#define SET_CBR_RG_TX_DAC_RCAL(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffff3fff))
+#define SET_CBR_RG_TX_DAC_TSEL(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xfff0ffff))
+#define SET_CBR_RG_TX_EN_VOLTAGE_IN(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffefffff))
+#define SET_CBR_RG_TXLPF_BYPASS(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffdfffff))
+#define SET_CBR_RG_TXLPF_BOOSTI(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffbfffff))
+#define SET_CBR_RG_EN_SX_R3(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffffe))
+#define SET_CBR_RG_EN_SX_CH(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffffd))
+#define SET_CBR_RG_EN_SX_CHP(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffffb))
+#define SET_CBR_RG_EN_SX_DIVCK(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffff7))
+#define SET_CBR_RG_EN_SX_VCOBF(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffffef))
+#define SET_CBR_RG_EN_SX_VCO(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffffdf))
+#define SET_CBR_RG_EN_SX_MOD(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffffbf))
+#define SET_CBR_RG_EN_SX_LCK(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffff7f))
+#define SET_CBR_RG_EN_SX_DITHER(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffeff))
+#define SET_CBR_RG_EN_SX_DELCAL(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffdff))
+#define SET_CBR_RG_EN_SX_PC_BYPASS(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffbff))
+#define SET_CBR_RG_EN_SX_VT_MON(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffff7ff))
+#define SET_CBR_RG_EN_SX_VT_MON_DG(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffefff))
+#define SET_CBR_RG_EN_SX_DIV(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffdfff))
+#define SET_CBR_RG_EN_SX_LPF(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffbfff))
+#define SET_CBR_RG_SX_RFCTRL_F(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_RGISTER_1)) & 0xff000000))
+#define SET_CBR_RG_SX_SEL_CP(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_1)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_SYN_RGISTER_1)) & 0xf0ffffff))
+#define SET_CBR_RG_SX_SEL_CS(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_1)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_SYN_RGISTER_1)) & 0x0fffffff))
+#define SET_CBR_RG_SX_RFCTRL_CH(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_RGISTER_2)) & 0xfffff800))
+#define SET_CBR_RG_SX_SEL_C3(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_2)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_SYN_RGISTER_2)) & 0xffff87ff))
+#define SET_CBR_RG_SX_SEL_RS(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_2)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_SYN_RGISTER_2)) & 0xfff07fff))
+#define SET_CBR_RG_SX_SEL_R3(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_2)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_SYN_RGISTER_2)) & 0xfe0fffff))
+#define SET_CBR_RG_SX_SEL_ICHP(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xffffffe0))
+#define SET_CBR_RG_SX_SEL_PCHP(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfffffc1f))
+#define SET_CBR_RG_SX_SEL_CHP_REGOP(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xffffc3ff))
+#define SET_CBR_RG_SX_SEL_CHP_UNIOP(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfffc3fff))
+#define SET_CBR_RG_SX_CHP_IOST_POL(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfffbffff))
+#define SET_CBR_RG_SX_CHP_IOST(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 19) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xffc7ffff))
+#define SET_CBR_RG_SX_PFDSEL(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xffbfffff))
+#define SET_CBR_RG_SX_PFD_SET(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xff7fffff))
+#define SET_CBR_RG_SX_PFD_SET1(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfeffffff))
+#define SET_CBR_RG_SX_PFD_SET2(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 25) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfdffffff))
+#define SET_CBR_RG_SX_VBNCAS_SEL(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 26) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfbffffff))
+#define SET_CBR_RG_SX_PFD_RST_H(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 27) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xf7ffffff))
+#define SET_CBR_RG_SX_PFD_TRUP(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xefffffff))
+#define SET_CBR_RG_SX_PFD_TRDN(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 29) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xdfffffff))
+#define SET_CBR_RG_SX_PFD_TRSEL(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 30) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xbfffffff))
+#define SET_CBR_RG_SX_VCOBA_R(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xfffffff8))
+#define SET_CBR_RG_SX_VCORSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xffffff07))
+#define SET_CBR_RG_SX_VCOCUSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xfffff0ff))
+#define SET_CBR_RG_SX_RXBFSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xffff0fff))
+#define SET_CBR_RG_SX_TXBFSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xfff0ffff))
+#define SET_CBR_RG_SX_VCOBFSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xff0fffff))
+#define SET_CBR_RG_SX_DIVBFSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xf0ffffff))
+#define SET_CBR_RG_SX_GNDR_SEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x0fffffff))
+#define SET_CBR_RG_SX_DITHER_WEIGHT(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffffffc))
+#define SET_CBR_RG_SX_MOD_ERRCMP(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffffff3))
+#define SET_CBR_RG_SX_MOD_ORDER(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xffffffcf))
+#define SET_CBR_RG_SX_SDM_D1(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xffffffbf))
+#define SET_CBR_RG_SX_SDM_D2(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xffffff7f))
+#define SET_CBR_RG_SDM_PASS(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffffeff))
+#define SET_CBR_RG_SX_RST_H_DIV(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffffdff))
+#define SET_CBR_RG_SX_SDM_EDGE(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffffbff))
+#define SET_CBR_RG_SX_XO_GM(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xffffe7ff))
+#define SET_CBR_RG_SX_REFBYTWO(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 13) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xffffdfff))
+#define SET_CBR_RG_SX_XO_SWCAP(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffc3fff))
+#define SET_CBR_RG_SX_SDMLUT_INV(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffbffff))
+#define SET_CBR_RG_SX_LCKEN(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 19) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfff7ffff))
+#define SET_CBR_RG_SX_PREVDD(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xff0fffff))
+#define SET_CBR_RG_SX_PSCONTERVDD(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xf0ffffff))
+#define SET_CBR_RG_SX_MOD_ERR_DELAY(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xcfffffff))
+#define SET_CBR_RG_SX_MODDB(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 30) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xbfffffff))
+#define SET_CBR_RG_SX_CV_CURVE_SEL(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xfffffffc))
+#define SET_CBR_RG_SX_SEL_DELAY(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xffffff83))
+#define SET_CBR_RG_SX_REF_CYCLE(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xfffff87f))
+#define SET_CBR_RG_SX_VCOBY16(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xfffff7ff))
+#define SET_CBR_RG_SX_VCOBY32(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xffffefff))
+#define SET_CBR_RG_SX_PH(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 13) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xffffdfff))
+#define SET_CBR_RG_SX_PL(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xffffbfff))
+#define SET_CBR_RG_SX_VT_MON_MODE(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xfffffffe))
+#define SET_CBR_RG_SX_VT_TH_HI(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xfffffff9))
+#define SET_CBR_RG_SX_VT_TH_LO(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xffffffe7))
+#define SET_CBR_RG_SX_VT_SET(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xffffffdf))
+#define SET_CBR_RG_SX_VT_MON_TMR(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xffff803f))
+#define SET_CBR_RG_IDEAL_CYCLE(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xf0007fff))
+#define SET_CBR_RG_EN_DP_VT_MON(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xfffffffe))
+#define SET_CBR_RG_DP_VT_TH_HI(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xfffffff9))
+#define SET_CBR_RG_DP_VT_TH_LO(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xffffffe7))
+#define SET_CBR_RG_DP_VT_MON_TMR(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xffffc01f))
+#define SET_CBR_RG_DP_CK320BY2(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xffffbfff))
+#define SET_CBR_RG_SX_DELCTRL(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xffe07fff))
+#define SET_CBR_RG_DP_OD_TEST(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xffdfffff))
+#define SET_CBR_RG_DP_BBPLL_BP(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfffffffe))
+#define SET_CBR_RG_DP_BBPLL_ICP(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfffffff9))
+#define SET_CBR_RG_DP_BBPLL_IDUAL(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xffffffe7))
+#define SET_CBR_RG_DP_BBPLL_OD_TEST(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfffffe1f))
+#define SET_CBR_RG_DP_BBPLL_PD(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfffffdff))
+#define SET_CBR_RG_DP_BBPLL_TESTSEL(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xffffe3ff))
+#define SET_CBR_RG_DP_BBPLL_PFD_DLY(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xffff9fff))
+#define SET_CBR_RG_DP_RP(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfffc7fff))
+#define SET_CBR_RG_DP_RHP(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfff3ffff))
+#define SET_CBR_RG_DP_DR3(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xff8fffff))
+#define SET_CBR_RG_DP_DCP(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xf87fffff))
+#define SET_CBR_RG_DP_DCS(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x87ffffff))
+#define SET_CBR_RG_DP_FBDIV(_VAL_) (REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0xfffff000))
+#define SET_CBR_RG_DP_FODIV(_VAL_) (REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0xffc00fff))
+#define SET_CBR_RG_DP_REFDIV(_VAL_) (REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0x003fffff))
+#define SET_CBR_RG_IDACAI_PGAG15(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0xffffffc0))
+#define SET_CBR_RG_IDACAQ_PGAG15(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0xfffff03f))
+#define SET_CBR_RG_IDACAI_PGAG14(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0xfffc0fff))
+#define SET_CBR_RG_IDACAQ_PGAG14(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0xff03ffff))
+#define SET_CBR_RG_IDACAI_PGAG13(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0xffffffc0))
+#define SET_CBR_RG_IDACAQ_PGAG13(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0xfffff03f))
+#define SET_CBR_RG_IDACAI_PGAG12(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0xfffc0fff))
+#define SET_CBR_RG_IDACAQ_PGAG12(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0xff03ffff))
+#define SET_CBR_RG_IDACAI_PGAG11(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0xffffffc0))
+#define SET_CBR_RG_IDACAQ_PGAG11(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0xfffff03f))
+#define SET_CBR_RG_IDACAI_PGAG10(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0xfffc0fff))
+#define SET_CBR_RG_IDACAQ_PGAG10(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0xff03ffff))
+#define SET_CBR_RG_IDACAI_PGAG9(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0xffffffc0))
+#define SET_CBR_RG_IDACAQ_PGAG9(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0xfffff03f))
+#define SET_CBR_RG_IDACAI_PGAG8(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0xfffc0fff))
+#define SET_CBR_RG_IDACAQ_PGAG8(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0xff03ffff))
+#define SET_CBR_RG_IDACAI_PGAG7(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0xffffffc0))
+#define SET_CBR_RG_IDACAQ_PGAG7(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0xfffff03f))
+#define SET_CBR_RG_IDACAI_PGAG6(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0xfffc0fff))
+#define SET_CBR_RG_IDACAQ_PGAG6(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0xff03ffff))
+#define SET_CBR_RG_IDACAI_PGAG5(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0xffffffc0))
+#define SET_CBR_RG_IDACAQ_PGAG5(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0xfffff03f))
+#define SET_CBR_RG_IDACAI_PGAG4(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0xfffc0fff))
+#define SET_CBR_RG_IDACAQ_PGAG4(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0xff03ffff))
+#define SET_CBR_RG_IDACAI_PGAG3(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0xffffffc0))
+#define SET_CBR_RG_IDACAQ_PGAG3(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0xfffff03f))
+#define SET_CBR_RG_IDACAI_PGAG2(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0xfffc0fff))
+#define SET_CBR_RG_IDACAQ_PGAG2(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0xff03ffff))
+#define SET_CBR_RG_IDACAI_PGAG1(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0xffffffc0))
+#define SET_CBR_RG_IDACAQ_PGAG1(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0xfffff03f))
+#define SET_CBR_RG_IDACAI_PGAG0(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0xfffc0fff))
+#define SET_CBR_RG_IDACAQ_PGAG0(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0xff03ffff))
+#define SET_CBR_RG_EN_RCAL(_VAL_) (REG32(ADR_CBR_RCAL_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RCAL_REGISTER)) & 0xfffffffe))
+#define SET_CBR_RG_RCAL_SPD(_VAL_) (REG32(ADR_CBR_RCAL_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_RCAL_REGISTER)) & 0xfffffffd))
+#define SET_CBR_RG_RCAL_TMR(_VAL_) (REG32(ADR_CBR_RCAL_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RCAL_REGISTER)) & 0xfffffe03))
+#define SET_CBR_RG_RCAL_CODE_CWR(_VAL_) (REG32(ADR_CBR_RCAL_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_RCAL_REGISTER)) & 0xfffffdff))
+#define SET_CBR_RG_RCAL_CODE_CWD(_VAL_) (REG32(ADR_CBR_RCAL_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RCAL_REGISTER)) & 0xffff83ff))
+#define SET_CBR_RG_SX_SUB_SEL_CWR(_VAL_) (REG32(ADR_CBR_MANUAL_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_MANUAL_REGISTER)) & 0xfffffffe))
+#define SET_CBR_RG_SX_SUB_SEL_CWD(_VAL_) (REG32(ADR_CBR_MANUAL_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_MANUAL_REGISTER)) & 0xffffff01))
+#define SET_CBR_RG_DP_BBPLL_BS_CWR(_VAL_) (REG32(ADR_CBR_MANUAL_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_MANUAL_REGISTER)) & 0xfffffeff))
+#define SET_CBR_RG_DP_BBPLL_BS_CWD(_VAL_) (REG32(ADR_CBR_MANUAL_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_MANUAL_REGISTER)) & 0xffff81ff))
+#define SET_CBR_RCAL_RDY(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xfffffffe))
+#define SET_CBR_DA_LCK_RDY(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xfffffffd))
+#define SET_CBR_VT_MON_RDY(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xfffffffb))
+#define SET_CBR_DP_VT_MON_RDY(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xfffffff7))
+#define SET_CBR_CH_RDY(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xffffffef))
+#define SET_CBR_DA_R_CODE_LUT(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xfffff83f))
+#define SET_CBR_AD_SX_VT_MON_Q(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xffffe7ff))
+#define SET_CBR_AD_DP_VT_MON_Q(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 13) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xffff9fff))
+#define SET_CBR_DA_R_CAL_CODE(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0xffffffe0))
+#define SET_CBR_DA_SX_SUB_SEL(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_2)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0xfffff01f))
+#define SET_CBR_DA_DP_BBPLL_BS(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_2)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0xfffc0fff))
+#define SET_CBR_TX_EN(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_0)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0xfffffffe))
+#define SET_CBR_TX_CNT_RST(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_0)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0xfffffffd))
+#define SET_CBR_IFS_TIME(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_0)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0xffffff03))
+#define SET_CBR_LENGTH_TARGET(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_0)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0xfff000ff))
+#define SET_CBR_TX_CNT_TARGET(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_0)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0x00ffffff))
+#define SET_CBR_TC_CNT_TARGET(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RG_PKT_GEN_1)) & 0xff000000))
+#define SET_CBR_PLCP_PSDU_DATA_MEM(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0xffffff00))
+#define SET_CBR_PLCP_PSDU_PREAMBLE_SHORT(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_2)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0xfffffeff))
+#define SET_CBR_PLCP_BYTE_LENGTH(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_2)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0xffe001ff))
+#define SET_CBR_PLCP_PSDU_RATE(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_2)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0xff9fffff))
+#define SET_CBR_TAIL_TIME(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_2)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0xe07fffff))
+#define SET_CBR_RG_O_PAD_PD(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffffe))
+#define SET_CBR_RG_I_PAD_PD(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffffd))
+#define SET_CBR_SEL_ADCKP_INV(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffffb))
+#define SET_CBR_RG_PAD_DS(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffff7))
+#define SET_CBR_SEL_ADCKP_MUX(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xffffffef))
+#define SET_CBR_RG_PAD_DS_CLK(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xffffffdf))
+#define SET_CBR_INTP_SEL(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffdff))
+#define SET_CBR_IQ_SWP(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffbff))
+#define SET_CBR_RG_EN_EXT_DA(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffff7ff))
+#define SET_CBR_RG_DIS_DA_OFFSET(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xffffefff))
+#define SET_CBR_DBG_SEL(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfff0ffff))
+#define SET_CBR_DBG_EN(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xffefffff))
+#define SET_CBR_RG_PKT_GEN_TX_CNT(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_TXCNT)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RG_PKT_GEN_TXCNT)) & 0x00000000))
+#define SET_CBR_TP_SEL(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0xffffffe0))
+#define SET_CBR_IDEAL_IQ_EN(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0xffffffdf))
+#define SET_CBR_DATA_OUT_SEL(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0xfffffe3f))
+#define SET_CBR_TWO_TONE_EN(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0xfffffdff))
+#define SET_CBR_FREQ_SEL(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0xff00ffff))
+#define SET_CBR_IQ_SCALE(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0x00ffffff))
+#define SET_CPU_QUE_POP(_VAL_) (REG32(ADR_MB_CPU_INT)) = (((_VAL_) << 0) | ((REG32(ADR_MB_CPU_INT)) & 0xfffffffe))
+#define SET_CPU_INT(_VAL_) (REG32(ADR_MB_CPU_INT)) = (((_VAL_) << 2) | ((REG32(ADR_MB_CPU_INT)) & 0xfffffffb))
+#define SET_CPU_ID_TB0(_VAL_) (REG32(ADR_CPU_ID_TB0)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_ID_TB0)) & 0x00000000))
+#define SET_CPU_ID_TB1(_VAL_) (REG32(ADR_CPU_ID_TB1)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_ID_TB1)) & 0x00000000))
+#define SET_HW_PKTID(_VAL_) (REG32(ADR_CH0_TRIG_1)) = (((_VAL_) << 0) | ((REG32(ADR_CH0_TRIG_1)) & 0xfffff800))
+#define SET_CH0_INT_ADDR(_VAL_) (REG32(ADR_CH0_TRIG_0)) = (((_VAL_) << 0) | ((REG32(ADR_CH0_TRIG_0)) & 0x00000000))
+#define SET_PRI_HW_PKTID(_VAL_) (REG32(ADR_CH0_PRI_TRIG)) = (((_VAL_) << 0) | ((REG32(ADR_CH0_PRI_TRIG)) & 0xfffff800))
+#define SET_CH0_FULL(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MCU_STATUS)) & 0xfffffffe))
+#define SET_FF0_EMPTY(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_MCU_STATUS)) & 0xfffffffd))
+#define SET_RLS_BUSY(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 9) | ((REG32(ADR_MCU_STATUS)) & 0xfffffdff))
+#define SET_RLS_COUNT_CLR(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 10) | ((REG32(ADR_MCU_STATUS)) & 0xfffffbff))
+#define SET_RTN_COUNT_CLR(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 11) | ((REG32(ADR_MCU_STATUS)) & 0xfffff7ff))
+#define SET_RLS_COUNT(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_MCU_STATUS)) & 0xff00ffff))
+#define SET_RTN_COUNT(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 24) | ((REG32(ADR_MCU_STATUS)) & 0x00ffffff))
+#define SET_FF0_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 0) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xffffffe0))
+#define SET_FF1_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 5) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xfffffe1f))
+#define SET_FF3_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 11) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xffffc7ff))
+#define SET_FF5_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 17) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xfff1ffff))
+#define SET_FF6_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 20) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xff8fffff))
+#define SET_FF7_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 23) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xfc7fffff))
+#define SET_FF8_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 26) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xe3ffffff))
+#define SET_FF9_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 29) | ((REG32(ADR_RD_IN_FFCNT1)) & 0x1fffffff))
+#define SET_FF10_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 0) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xfffffff8))
+#define SET_FF11_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 3) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xffffffc7))
+#define SET_FF12_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 6) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xfffffe3f))
+#define SET_FF13_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 9) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xfffff9ff))
+#define SET_FF14_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 11) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xffffe7ff))
+#define SET_FF15_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 13) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xffff9fff))
+#define SET_FF4_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 15) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xfff07fff))
+#define SET_FF2_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 20) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xff8fffff))
+#define SET_CH1_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 1) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffffd))
+#define SET_CH2_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 2) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffffb))
+#define SET_CH3_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 3) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffff7))
+#define SET_CH4_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 4) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffffef))
+#define SET_CH5_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 5) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffffdf))
+#define SET_CH6_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 6) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffffbf))
+#define SET_CH7_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 7) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffff7f))
+#define SET_CH8_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 8) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffeff))
+#define SET_CH9_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 9) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffdff))
+#define SET_CH10_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 10) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffbff))
+#define SET_CH11_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 11) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffff7ff))
+#define SET_CH12_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 12) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffefff))
+#define SET_CH13_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 13) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffdfff))
+#define SET_CH14_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 14) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffbfff))
+#define SET_CH15_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 15) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffff7fff))
+#define SET_HALT_CH0(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 0) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffffe))
+#define SET_HALT_CH1(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 1) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffffd))
+#define SET_HALT_CH2(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 2) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffffb))
+#define SET_HALT_CH3(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 3) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffff7))
+#define SET_HALT_CH4(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 4) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffffef))
+#define SET_HALT_CH5(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 5) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffffdf))
+#define SET_HALT_CH6(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 6) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffffbf))
+#define SET_HALT_CH7(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 7) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffff7f))
+#define SET_HALT_CH8(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 8) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffeff))
+#define SET_HALT_CH9(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 9) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffdff))
+#define SET_HALT_CH10(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 10) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffbff))
+#define SET_HALT_CH11(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 11) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffff7ff))
+#define SET_HALT_CH12(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 12) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffefff))
+#define SET_HALT_CH13(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 13) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffdfff))
+#define SET_HALT_CH14(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 14) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffbfff))
+#define SET_HALT_CH15(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 15) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffff7fff))
+#define SET_STOP_MBOX(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 16) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffeffff))
+#define SET_MB_ERR_AUTO_HALT_EN(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 20) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffefffff))
+#define SET_MB_EXCEPT_CLR(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 21) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffdfffff))
+#define SET_MB_EXCEPT_CASE(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 24) | ((REG32(ADR_MBOX_HALT_CFG)) & 0x00ffffff))
+#define SET_MB_DBG_TIME_STEP(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 0) | ((REG32(ADR_MB_DBG_CFG1)) & 0xffff0000))
+#define SET_DBG_TYPE(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 16) | ((REG32(ADR_MB_DBG_CFG1)) & 0xfffcffff))
+#define SET_MB_DBG_CLR(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 18) | ((REG32(ADR_MB_DBG_CFG1)) & 0xfffbffff))
+#define SET_DBG_ALC_LOG_EN(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 19) | ((REG32(ADR_MB_DBG_CFG1)) & 0xfff7ffff))
+#define SET_MB_DBG_COUNTER_EN(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 24) | ((REG32(ADR_MB_DBG_CFG1)) & 0xfeffffff))
+#define SET_MB_DBG_EN(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 31) | ((REG32(ADR_MB_DBG_CFG1)) & 0x7fffffff))
+#define SET_MB_DBG_RECORD_CNT(_VAL_) (REG32(ADR_MB_DBG_CFG2)) = (((_VAL_) << 0) | ((REG32(ADR_MB_DBG_CFG2)) & 0xffff0000))
+#define SET_MB_DBG_LENGTH(_VAL_) (REG32(ADR_MB_DBG_CFG2)) = (((_VAL_) << 16) | ((REG32(ADR_MB_DBG_CFG2)) & 0x0000ffff))
+#define SET_MB_DBG_CFG_ADDR(_VAL_) (REG32(ADR_MB_DBG_CFG3)) = (((_VAL_) << 0) | ((REG32(ADR_MB_DBG_CFG3)) & 0x00000000))
+#define SET_DBG_HWID0_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 0) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffffe))
+#define SET_DBG_HWID1_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 1) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffffd))
+#define SET_DBG_HWID2_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 2) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffffb))
+#define SET_DBG_HWID3_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 3) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffff7))
+#define SET_DBG_HWID4_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 4) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffffef))
+#define SET_DBG_HWID5_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 5) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffffdf))
+#define SET_DBG_HWID6_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 6) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffffbf))
+#define SET_DBG_HWID7_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 7) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffff7f))
+#define SET_DBG_HWID8_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 8) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffeff))
+#define SET_DBG_HWID9_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 9) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffdff))
+#define SET_DBG_HWID10_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 10) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffbff))
+#define SET_DBG_HWID11_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 11) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffff7ff))
+#define SET_DBG_HWID12_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 12) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffefff))
+#define SET_DBG_HWID13_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 13) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffdfff))
+#define SET_DBG_HWID14_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 14) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffbfff))
+#define SET_DBG_HWID15_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 15) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffff7fff))
+#define SET_DBG_HWID0_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 16) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffeffff))
+#define SET_DBG_HWID1_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 17) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffdffff))
+#define SET_DBG_HWID2_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 18) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffbffff))
+#define SET_DBG_HWID3_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 19) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfff7ffff))
+#define SET_DBG_HWID4_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 20) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffefffff))
+#define SET_DBG_HWID5_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 21) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffdfffff))
+#define SET_DBG_HWID6_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 22) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffbfffff))
+#define SET_DBG_HWID7_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 23) | ((REG32(ADR_MB_DBG_CFG4)) & 0xff7fffff))
+#define SET_DBG_HWID8_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 24) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfeffffff))
+#define SET_DBG_HWID9_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 25) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfdffffff))
+#define SET_DBG_HWID10_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 26) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfbffffff))
+#define SET_DBG_HWID11_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 27) | ((REG32(ADR_MB_DBG_CFG4)) & 0xf7ffffff))
+#define SET_DBG_HWID12_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 28) | ((REG32(ADR_MB_DBG_CFG4)) & 0xefffffff))
+#define SET_DBG_HWID13_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 29) | ((REG32(ADR_MB_DBG_CFG4)) & 0xdfffffff))
+#define SET_DBG_HWID14_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 30) | ((REG32(ADR_MB_DBG_CFG4)) & 0xbfffffff))
+#define SET_DBG_HWID15_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 31) | ((REG32(ADR_MB_DBG_CFG4)) & 0x7fffffff))
+#define SET_MB_OUT_QUEUE_EN(_VAL_) (REG32(ADR_MB_OUT_QUEUE_CFG)) = (((_VAL_) << 1) | ((REG32(ADR_MB_OUT_QUEUE_CFG)) & 0xfffffffd))
+#define SET_CH0_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 0) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffffe))
+#define SET_CH1_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 1) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffffd))
+#define SET_CH2_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 2) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffffb))
+#define SET_CH3_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 3) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffff7))
+#define SET_CH4_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 4) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffffef))
+#define SET_CH5_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 5) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffffdf))
+#define SET_CH6_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 6) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffffbf))
+#define SET_CH7_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 7) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffff7f))
+#define SET_CH8_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 8) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffeff))
+#define SET_CH9_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 9) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffdff))
+#define SET_CH10_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 10) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffbff))
+#define SET_CH11_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 11) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffff7ff))
+#define SET_CH12_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 12) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffefff))
+#define SET_CH13_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 13) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffdfff))
+#define SET_CH14_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 14) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffbfff))
+#define SET_CH15_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 15) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffff7fff))
+#define SET_FFO0_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 0) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xffffffe0))
+#define SET_FFO1_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 5) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xfffffc1f))
+#define SET_FFO2_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 10) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xfffff3ff))
+#define SET_FFO3_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 15) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xfff07fff))
+#define SET_FFO4_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 20) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xffcfffff))
+#define SET_FFO5_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 25) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xf1ffffff))
+#define SET_FFO6_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 0) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xfffffff0))
+#define SET_FFO7_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 5) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xfffffc1f))
+#define SET_FFO8_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 10) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xffff83ff))
+#define SET_FFO9_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 15) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xfff07fff))
+#define SET_FFO10_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 20) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xff0fffff))
+#define SET_FFO11_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 25) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xc1ffffff))
+#define SET_FFO12_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT3)) = (((_VAL_) << 0) | ((REG32(ADR_RD_FFOUT_CNT3)) & 0xfffffff8))
+#define SET_FFO13_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT3)) = (((_VAL_) << 5) | ((REG32(ADR_RD_FFOUT_CNT3)) & 0xffffff9f))
+#define SET_FFO14_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT3)) = (((_VAL_) << 10) | ((REG32(ADR_RD_FFOUT_CNT3)) & 0xfffff3ff))
+#define SET_FFO15_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT3)) = (((_VAL_) << 15) | ((REG32(ADR_RD_FFOUT_CNT3)) & 0xffe07fff))
+#define SET_CH0_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 0) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffffe))
+#define SET_CH1_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 1) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffffd))
+#define SET_CH2_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 2) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffffb))
+#define SET_CH3_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 3) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffff7))
+#define SET_CH4_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 4) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffffef))
+#define SET_CH5_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 5) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffffdf))
+#define SET_CH6_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 6) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffffbf))
+#define SET_CH7_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 7) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffff7f))
+#define SET_CH8_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 8) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffeff))
+#define SET_CH9_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 9) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffdff))
+#define SET_CH10_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 10) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffbff))
+#define SET_CH11_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 11) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffff7ff))
+#define SET_CH12_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 12) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffefff))
+#define SET_CH13_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 13) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffdfff))
+#define SET_CH14_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 14) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffbfff))
+#define SET_CH15_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 15) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffff7fff))
+#define SET_CH0_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 0) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffffe))
+#define SET_CH1_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 1) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffffd))
+#define SET_CH2_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 2) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffffb))
+#define SET_CH3_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 3) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffff7))
+#define SET_CH4_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 4) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffffef))
+#define SET_CH5_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 5) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffffdf))
+#define SET_CH6_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 6) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffffbf))
+#define SET_CH7_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 7) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffff7f))
+#define SET_CH8_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 8) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffeff))
+#define SET_CH9_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 9) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffdff))
+#define SET_CH10_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 10) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffbff))
+#define SET_CH11_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 11) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffff7ff))
+#define SET_CH12_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 12) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffefff))
+#define SET_CH13_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 13) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffdfff))
+#define SET_CH14_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 14) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffbfff))
+#define SET_CH15_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 15) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffff7fff))
+#define SET_MB_LOW_THOLD_EN(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 31) | ((REG32(ADR_MB_THRESHOLD6)) & 0x7fffffff))
+#define SET_CH0_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD7)) = (((_VAL_) << 0) | ((REG32(ADR_MB_THRESHOLD7)) & 0xffffffe0))
+#define SET_CH1_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD7)) = (((_VAL_) << 8) | ((REG32(ADR_MB_THRESHOLD7)) & 0xffffe0ff))
+#define SET_CH2_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD7)) = (((_VAL_) << 16) | ((REG32(ADR_MB_THRESHOLD7)) & 0xffe0ffff))
+#define SET_CH3_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD7)) = (((_VAL_) << 24) | ((REG32(ADR_MB_THRESHOLD7)) & 0xe0ffffff))
+#define SET_CH4_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD8)) = (((_VAL_) << 0) | ((REG32(ADR_MB_THRESHOLD8)) & 0xffffffe0))
+#define SET_CH5_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD8)) = (((_VAL_) << 8) | ((REG32(ADR_MB_THRESHOLD8)) & 0xffffe0ff))
+#define SET_CH6_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD8)) = (((_VAL_) << 16) | ((REG32(ADR_MB_THRESHOLD8)) & 0xffe0ffff))
+#define SET_CH7_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD8)) = (((_VAL_) << 24) | ((REG32(ADR_MB_THRESHOLD8)) & 0xe0ffffff))
+#define SET_CH8_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD9)) = (((_VAL_) << 0) | ((REG32(ADR_MB_THRESHOLD9)) & 0xffffffe0))
+#define SET_CH9_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD9)) = (((_VAL_) << 8) | ((REG32(ADR_MB_THRESHOLD9)) & 0xffffe0ff))
+#define SET_CH10_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD9)) = (((_VAL_) << 16) | ((REG32(ADR_MB_THRESHOLD9)) & 0xffe0ffff))
+#define SET_CH11_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD9)) = (((_VAL_) << 24) | ((REG32(ADR_MB_THRESHOLD9)) & 0xe0ffffff))
+#define SET_CH12_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD10)) = (((_VAL_) << 0) | ((REG32(ADR_MB_THRESHOLD10)) & 0xffffffe0))
+#define SET_CH13_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD10)) = (((_VAL_) << 8) | ((REG32(ADR_MB_THRESHOLD10)) & 0xffffe0ff))
+#define SET_CH14_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD10)) = (((_VAL_) << 16) | ((REG32(ADR_MB_THRESHOLD10)) & 0xffe0ffff))
+#define SET_CH15_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD10)) = (((_VAL_) << 24) | ((REG32(ADR_MB_THRESHOLD10)) & 0xe0ffffff))
+#define SET_TRASH_TIMEOUT_EN(_VAL_) (REG32(ADR_MB_TRASH_CFG)) = (((_VAL_) << 0) | ((REG32(ADR_MB_TRASH_CFG)) & 0xfffffffe))
+#define SET_TRASH_CAN_INT(_VAL_) (REG32(ADR_MB_TRASH_CFG)) = (((_VAL_) << 1) | ((REG32(ADR_MB_TRASH_CFG)) & 0xfffffffd))
+#define SET_TRASH_INT_ID(_VAL_) (REG32(ADR_MB_TRASH_CFG)) = (((_VAL_) << 4) | ((REG32(ADR_MB_TRASH_CFG)) & 0xfffff80f))
+#define SET_TRASH_TIMEOUT(_VAL_) (REG32(ADR_MB_TRASH_CFG)) = (((_VAL_) << 16) | ((REG32(ADR_MB_TRASH_CFG)) & 0xfc00ffff))
+#define SET_CH0_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 0) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffffe))
+#define SET_CH1_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 1) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffffd))
+#define SET_CH2_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 2) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffffb))
+#define SET_CH3_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 3) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffff7))
+#define SET_CH4_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 4) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffffef))
+#define SET_CH5_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 5) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffffdf))
+#define SET_CH6_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 6) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffffbf))
+#define SET_CH7_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 7) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffff7f))
+#define SET_CH8_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 8) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffeff))
+#define SET_CH9_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 9) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffdff))
+#define SET_CH10_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 10) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffbff))
+#define SET_CH11_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 11) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffff7ff))
+#define SET_CH12_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 12) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffefff))
+#define SET_CH13_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 13) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffdfff))
+#define SET_CH14_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 14) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffbfff))
+#define SET_CPU_ID_TB2(_VAL_) (REG32(ADR_CPU_ID_TB2)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_ID_TB2)) & 0x00000000))
+#define SET_CPU_ID_TB3(_VAL_) (REG32(ADR_CPU_ID_TB3)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_ID_TB3)) & 0x00000000))
+#define SET_IQ_LOG_EN(_VAL_) (REG32(ADR_PHY_IQ_LOG_CFG0)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_IQ_LOG_CFG0)) & 0xfffffffe))
+#define SET_IQ_LOG_STOP_MODE(_VAL_) (REG32(ADR_PHY_IQ_LOG_CFG1)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0xfffffffe))
+#define SET_GPIO_STOP_EN(_VAL_) (REG32(ADR_PHY_IQ_LOG_CFG1)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0xffffffef))
+#define SET_GPIO_STOP_POL(_VAL_) (REG32(ADR_PHY_IQ_LOG_CFG1)) = (((_VAL_) << 5) | ((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0xffffffdf))
+#define SET_IQ_LOG_TIMER(_VAL_) (REG32(ADR_PHY_IQ_LOG_CFG1)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0x0000ffff))
+#define SET_IQ_LOG_LEN(_VAL_) (REG32(ADR_PHY_IQ_LOG_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_IQ_LOG_LEN)) & 0xffff0000))
+#define SET_IQ_LOG_TAIL_ADR(_VAL_) (REG32(ADR_PHY_IQ_LOG_PTR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_IQ_LOG_PTR)) & 0xffff0000))
+#define SET_ALC_LENG(_VAL_) (REG32(ADR_WR_ALC)) = (((_VAL_) << 0) | ((REG32(ADR_WR_ALC)) & 0xfffc0000))
+#define SET_CH0_DYN_PRI(_VAL_) (REG32(ADR_WR_ALC)) = (((_VAL_) << 20) | ((REG32(ADR_WR_ALC)) & 0xffcfffff))
+#define SET_MCU_PKTID(_VAL_) (REG32(ADR_GETID)) = (((_VAL_) << 0) | ((REG32(ADR_GETID)) & 0x00000000))
+#define SET_CH0_STA_PRI(_VAL_) (REG32(ADR_CH_STA_PRI)) = (((_VAL_) << 0) | ((REG32(ADR_CH_STA_PRI)) & 0xfffffffc))
+#define SET_CH1_STA_PRI(_VAL_) (REG32(ADR_CH_STA_PRI)) = (((_VAL_) << 4) | ((REG32(ADR_CH_STA_PRI)) & 0xffffffcf))
+#define SET_CH2_STA_PRI(_VAL_) (REG32(ADR_CH_STA_PRI)) = (((_VAL_) << 8) | ((REG32(ADR_CH_STA_PRI)) & 0xfffffcff))
+#define SET_CH3_STA_PRI(_VAL_) (REG32(ADR_CH_STA_PRI)) = (((_VAL_) << 12) | ((REG32(ADR_CH_STA_PRI)) & 0xffffcfff))
+#define SET_ID_TB0(_VAL_) (REG32(ADR_RD_ID0)) = (((_VAL_) << 0) | ((REG32(ADR_RD_ID0)) & 0x00000000))
+#define SET_ID_TB1(_VAL_) (REG32(ADR_RD_ID1)) = (((_VAL_) << 0) | ((REG32(ADR_RD_ID1)) & 0x00000000))
+#define SET_ID_MNG_HALT(_VAL_) (REG32(ADR_IMD_CFG)) = (((_VAL_) << 4) | ((REG32(ADR_IMD_CFG)) & 0xffffffef))
+#define SET_ID_MNG_ERR_HALT_EN(_VAL_) (REG32(ADR_IMD_CFG)) = (((_VAL_) << 5) | ((REG32(ADR_IMD_CFG)) & 0xffffffdf))
+#define SET_ID_EXCEPT_FLG_CLR(_VAL_) (REG32(ADR_IMD_CFG)) = (((_VAL_) << 6) | ((REG32(ADR_IMD_CFG)) & 0xffffffbf))
+#define SET_ID_EXCEPT_FLG(_VAL_) (REG32(ADR_IMD_CFG)) = (((_VAL_) << 7) | ((REG32(ADR_IMD_CFG)) & 0xffffff7f))
+#define SET_ID_FULL(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 0) | ((REG32(ADR_IMD_STA)) & 0xfffffffe))
+#define SET_ID_MNG_BUSY(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 1) | ((REG32(ADR_IMD_STA)) & 0xfffffffd))
+#define SET_REQ_LOCK(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 2) | ((REG32(ADR_IMD_STA)) & 0xfffffffb))
+#define SET_CH0_REQ_LOCK(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 4) | ((REG32(ADR_IMD_STA)) & 0xffffffef))
+#define SET_CH1_REQ_LOCK(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 5) | ((REG32(ADR_IMD_STA)) & 0xffffffdf))
+#define SET_CH2_REQ_LOCK(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 6) | ((REG32(ADR_IMD_STA)) & 0xffffffbf))
+#define SET_CH3_REQ_LOCK(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 7) | ((REG32(ADR_IMD_STA)) & 0xffffff7f))
+#define SET_REQ_LOCK_INT_EN(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 8) | ((REG32(ADR_IMD_STA)) & 0xfffffeff))
+#define SET_REQ_LOCK_INT(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 9) | ((REG32(ADR_IMD_STA)) & 0xfffffdff))
+#define SET_MCU_ALC_READY(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 0) | ((REG32(ADR_ALC_STA)) & 0xfffffffe))
+#define SET_ALC_FAIL(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 1) | ((REG32(ADR_ALC_STA)) & 0xfffffffd))
+#define SET_ALC_BUSY(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 2) | ((REG32(ADR_ALC_STA)) & 0xfffffffb))
+#define SET_CH0_NVLD(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 4) | ((REG32(ADR_ALC_STA)) & 0xffffffef))
+#define SET_CH1_NVLD(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 5) | ((REG32(ADR_ALC_STA)) & 0xffffffdf))
+#define SET_CH2_NVLD(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 6) | ((REG32(ADR_ALC_STA)) & 0xffffffbf))
+#define SET_CH3_NVLD(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 7) | ((REG32(ADR_ALC_STA)) & 0xffffff7f))
+#define SET_ALC_INT_ID(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 8) | ((REG32(ADR_ALC_STA)) & 0xffff80ff))
+#define SET_ALC_TIMEOUT(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 16) | ((REG32(ADR_ALC_STA)) & 0xfc00ffff))
+#define SET_ALC_TIMEOUT_INT_EN(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 30) | ((REG32(ADR_ALC_STA)) & 0xbfffffff))
+#define SET_ALC_TIMEOUT_INT(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 31) | ((REG32(ADR_ALC_STA)) & 0x7fffffff))
+#define SET_TX_ID_COUNT(_VAL_) (REG32(ADR_TRX_ID_COUNT)) = (((_VAL_) << 0) | ((REG32(ADR_TRX_ID_COUNT)) & 0xffffff00))
+#define SET_RX_ID_COUNT(_VAL_) (REG32(ADR_TRX_ID_COUNT)) = (((_VAL_) << 8) | ((REG32(ADR_TRX_ID_COUNT)) & 0xffff00ff))
+#define SET_TX_ID_THOLD(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 0) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xffffff00))
+#define SET_RX_ID_THOLD(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 8) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xffff00ff))
+#define SET_ID_THOLD_RX_INT(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 16) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xfffeffff))
+#define SET_RX_INT_CH(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 17) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xfff1ffff))
+#define SET_ID_THOLD_TX_INT(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 20) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xffefffff))
+#define SET_TX_INT_CH(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 21) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xff1fffff))
+#define SET_ID_THOLD_INT_EN(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 24) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xfeffffff))
+#define SET_TX_ID_TB0(_VAL_) (REG32(ADR_TX_ID0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID0)) & 0x00000000))
+#define SET_TX_ID_TB1(_VAL_) (REG32(ADR_TX_ID1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID1)) & 0x00000000))
+#define SET_RX_ID_TB0(_VAL_) (REG32(ADR_RX_ID0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ID0)) & 0x00000000))
+#define SET_RX_ID_TB1(_VAL_) (REG32(ADR_RX_ID1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ID1)) & 0x00000000))
+#define SET_DOUBLE_RLS_INT_EN(_VAL_) (REG32(ADR_RTN_STA)) = (((_VAL_) << 0) | ((REG32(ADR_RTN_STA)) & 0xfffffffe))
+#define SET_ID_DOUBLE_RLS_INT(_VAL_) (REG32(ADR_RTN_STA)) = (((_VAL_) << 1) | ((REG32(ADR_RTN_STA)) & 0xfffffffd))
+#define SET_DOUBLE_RLS_ID(_VAL_) (REG32(ADR_RTN_STA)) = (((_VAL_) << 8) | ((REG32(ADR_RTN_STA)) & 0xffff80ff))
+#define SET_ID_LEN_THOLD_INT_EN(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 0) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xfffffffe))
+#define SET_ALL_ID_LEN_THOLD_INT(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 1) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xfffffffd))
+#define SET_TX_ID_LEN_THOLD_INT(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 2) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xfffffffb))
+#define SET_RX_ID_LEN_THOLD_INT(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 3) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xfffffff7))
+#define SET_ID_TX_LEN_THOLD(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 4) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xffffe00f))
+#define SET_ID_RX_LEN_THOLD(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 13) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xffc01fff))
+#define SET_ID_LEN_THOLD(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 22) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x803fffff))
+#define SET_ALL_ID_ALC_LEN(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD2)) = (((_VAL_) << 0) | ((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0xfffffe00))
+#define SET_TX_ID_ALC_LEN(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD2)) = (((_VAL_) << 9) | ((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0xfffc01ff))
+#define SET_RX_ID_ALC_LEN(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD2)) = (((_VAL_) << 18) | ((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0xf803ffff))
+#define SET_CH_ARB_EN(_VAL_) (REG32(ADR_CH_ARB_PRI)) = (((_VAL_) << 0) | ((REG32(ADR_CH_ARB_PRI)) & 0xfffffffe))
+#define SET_CH_PRI1(_VAL_) (REG32(ADR_CH_ARB_PRI)) = (((_VAL_) << 4) | ((REG32(ADR_CH_ARB_PRI)) & 0xffffffcf))
+#define SET_CH_PRI2(_VAL_) (REG32(ADR_CH_ARB_PRI)) = (((_VAL_) << 8) | ((REG32(ADR_CH_ARB_PRI)) & 0xfffffcff))
+#define SET_CH_PRI3(_VAL_) (REG32(ADR_CH_ARB_PRI)) = (((_VAL_) << 12) | ((REG32(ADR_CH_ARB_PRI)) & 0xffffcfff))
+#define SET_CH_PRI4(_VAL_) (REG32(ADR_CH_ARB_PRI)) = (((_VAL_) << 16) | ((REG32(ADR_CH_ARB_PRI)) & 0xfffcffff))
+#define SET_TX_ID_REMAIN(_VAL_) (REG32(ADR_TX_ID_REMAIN_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_REMAIN_STATUS)) & 0xffffff80))
+#define SET_TX_PAGE_REMAIN(_VAL_) (REG32(ADR_TX_ID_REMAIN_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_TX_ID_REMAIN_STATUS)) & 0xfffe00ff))
+#define SET_ID_PAGE_MAX_SIZE(_VAL_) (REG32(ADR_ID_INFO_STA)) = (((_VAL_) << 0) | ((REG32(ADR_ID_INFO_STA)) & 0xfffffe00))
+#define SET_TX_PAGE_LIMIT(_VAL_) (REG32(ADR_TX_LIMIT_INTR)) = (((_VAL_) << 0) | ((REG32(ADR_TX_LIMIT_INTR)) & 0xfffffe00))
+#define SET_TX_COUNT_LIMIT(_VAL_) (REG32(ADR_TX_LIMIT_INTR)) = (((_VAL_) << 16) | ((REG32(ADR_TX_LIMIT_INTR)) & 0xff00ffff))
+#define SET_TX_LIMIT_INT(_VAL_) (REG32(ADR_TX_LIMIT_INTR)) = (((_VAL_) << 30) | ((REG32(ADR_TX_LIMIT_INTR)) & 0xbfffffff))
+#define SET_TX_LIMIT_INT_EN(_VAL_) (REG32(ADR_TX_LIMIT_INTR)) = (((_VAL_) << 31) | ((REG32(ADR_TX_LIMIT_INTR)) & 0x7fffffff))
+#define SET_TX_PAGE_USE_7_0(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0xffffff00))
+#define SET_TX_ID_USE_5_0(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 8) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0xffffc0ff))
+#define SET_EDCA0_FFO_CNT(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 14) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0xfffc3fff))
+#define SET_EDCA1_FFO_CNT_3_0(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 18) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0xffc3ffff))
+#define SET_EDCA2_FFO_CNT(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 22) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0xf83fffff))
+#define SET_EDCA3_FFO_CNT(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 27) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0x07ffffff))
+#define SET_ID_TB2(_VAL_) (REG32(ADR_RD_ID2)) = (((_VAL_) << 0) | ((REG32(ADR_RD_ID2)) & 0x00000000))
+#define SET_ID_TB3(_VAL_) (REG32(ADR_RD_ID3)) = (((_VAL_) << 0) | ((REG32(ADR_RD_ID3)) & 0x00000000))
+#define SET_TX_ID_TB2(_VAL_) (REG32(ADR_TX_ID2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID2)) & 0x00000000))
+#define SET_TX_ID_TB3(_VAL_) (REG32(ADR_TX_ID3)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID3)) & 0x00000000))
+#define SET_RX_ID_TB2(_VAL_) (REG32(ADR_RX_ID2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ID2)) & 0x00000000))
+#define SET_RX_ID_TB3(_VAL_) (REG32(ADR_RX_ID3)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ID3)) & 0x00000000))
+#define SET_TX_PAGE_USE2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_ALL_INFO2)) & 0xfffffe00))
+#define SET_TX_ID_USE2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO2)) = (((_VAL_) << 9) | ((REG32(ADR_TX_ID_ALL_INFO2)) & 0xfffe01ff))
+#define SET_EDCA4_FFO_CNT(_VAL_) (REG32(ADR_TX_ID_ALL_INFO2)) = (((_VAL_) << 17) | ((REG32(ADR_TX_ID_ALL_INFO2)) & 0xffe1ffff))
+#define SET_TX_PAGE_USE3(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_A)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_ALL_INFO_A)) & 0xfffffe00))
+#define SET_TX_ID_USE3(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_A)) = (((_VAL_) << 9) | ((REG32(ADR_TX_ID_ALL_INFO_A)) & 0xfffe01ff))
+#define SET_EDCA1_FFO_CNT2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_A)) = (((_VAL_) << 21) | ((REG32(ADR_TX_ID_ALL_INFO_A)) & 0xfc1fffff))
+#define SET_EDCA4_FFO_CNT2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_A)) = (((_VAL_) << 26) | ((REG32(ADR_TX_ID_ALL_INFO_A)) & 0xc3ffffff))
+#define SET_TX_PAGE_USE4(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_B)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_ALL_INFO_B)) & 0xfffffe00))
+#define SET_TX_ID_USE4(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_B)) = (((_VAL_) << 9) | ((REG32(ADR_TX_ID_ALL_INFO_B)) & 0xfffe01ff))
+#define SET_EDCA2_FFO_CNT2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_B)) = (((_VAL_) << 17) | ((REG32(ADR_TX_ID_ALL_INFO_B)) & 0xffc1ffff))
+#define SET_EDCA3_FFO_CNT2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_B)) = (((_VAL_) << 22) | ((REG32(ADR_TX_ID_ALL_INFO_B)) & 0xf83fffff))
+#define SET_TX_ID_IFO_LEN(_VAL_) (REG32(ADR_TX_ID_REMAIN_STATUS2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_REMAIN_STATUS2)) & 0xfffffe00))
+#define SET_RX_ID_IFO_LEN(_VAL_) (REG32(ADR_TX_ID_REMAIN_STATUS2)) = (((_VAL_) << 16) | ((REG32(ADR_TX_ID_REMAIN_STATUS2)) & 0xfe00ffff))
+#define SET_MAX_ALL_ALC_ID_CNT(_VAL_) (REG32(ADR_ALC_ID_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_ALC_ID_INFO)) & 0xffffff00))
+#define SET_MAX_TX_ALC_ID_CNT(_VAL_) (REG32(ADR_ALC_ID_INFO)) = (((_VAL_) << 8) | ((REG32(ADR_ALC_ID_INFO)) & 0xffff00ff))
+#define SET_MAX_RX_ALC_ID_CNT(_VAL_) (REG32(ADR_ALC_ID_INFO)) = (((_VAL_) << 16) | ((REG32(ADR_ALC_ID_INFO)) & 0xff00ffff))
+#define SET_MAX_ALL_ID_ALC_LEN(_VAL_) (REG32(ADR_ALC_ID_INF1)) = (((_VAL_) << 0) | ((REG32(ADR_ALC_ID_INF1)) & 0xfffffe00))
+#define SET_MAX_TX_ID_ALC_LEN(_VAL_) (REG32(ADR_ALC_ID_INF1)) = (((_VAL_) << 9) | ((REG32(ADR_ALC_ID_INF1)) & 0xfffc01ff))
+#define SET_MAX_RX_ID_ALC_LEN(_VAL_) (REG32(ADR_ALC_ID_INF1)) = (((_VAL_) << 18) | ((REG32(ADR_ALC_ID_INF1)) & 0xf803ffff))
+#define SET_RG_PMDLBK(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_EN_0)) & 0xfffffffe))
+#define SET_RG_RDYACK_SEL(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 1) | ((REG32(ADR_PHY_EN_0)) & 0xfffffff9))
+#define SET_RG_ADEDGE_SEL(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 3) | ((REG32(ADR_PHY_EN_0)) & 0xfffffff7))
+#define SET_RG_SIGN_SWAP(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_EN_0)) & 0xffffffef))
+#define SET_RG_IQ_SWAP(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 5) | ((REG32(ADR_PHY_EN_0)) & 0xffffffdf))
+#define SET_RG_Q_INV(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 6) | ((REG32(ADR_PHY_EN_0)) & 0xffffffbf))
+#define SET_RG_I_INV(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 7) | ((REG32(ADR_PHY_EN_0)) & 0xffffff7f))
+#define SET_RG_BYPASS_ACI(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_EN_0)) & 0xfffffeff))
+#define SET_RG_LBK_ANA_PATH(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 9) | ((REG32(ADR_PHY_EN_0)) & 0xfffffdff))
+#define SET_RG_SPECTRUM_LEAKY_FACTOR(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 10) | ((REG32(ADR_PHY_EN_0)) & 0xfffff3ff))
+#define SET_RG_SPECTRUM_BW(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_EN_0)) & 0xffffcfff))
+#define SET_RG_SPECTRUM_FREQ_MANUAL(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 14) | ((REG32(ADR_PHY_EN_0)) & 0xffffbfff))
+#define SET_RG_SPECTRUM_EN(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 15) | ((REG32(ADR_PHY_EN_0)) & 0xffff7fff))
+#define SET_RG_TXPWRLVL_SET(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_EN_0)) & 0xff00ffff))
+#define SET_RG_TXPWRLVL_SEL(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_EN_0)) & 0xfeffffff))
+#define SET_RG_RF_BB_CLK_SEL(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_EN_0)) & 0x7fffffff))
+#define SET_RG_PHY_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_EN_1)) & 0xfffffffe))
+#define SET_RG_PHYRX_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 1) | ((REG32(ADR_PHY_EN_1)) & 0xfffffffd))
+#define SET_RG_PHYTX_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 2) | ((REG32(ADR_PHY_EN_1)) & 0xfffffffb))
+#define SET_RG_PHY11GN_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 3) | ((REG32(ADR_PHY_EN_1)) & 0xfffffff7))
+#define SET_RG_PHY11B_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_EN_1)) & 0xffffffef))
+#define SET_RG_PHYRXFIFO_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 5) | ((REG32(ADR_PHY_EN_1)) & 0xffffffdf))
+#define SET_RG_PHYTXFIFO_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 6) | ((REG32(ADR_PHY_EN_1)) & 0xffffffbf))
+#define SET_RG_PHY11BGN_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_EN_1)) & 0xfffffeff))
+#define SET_RG_FORCE_11GN_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_EN_1)) & 0xffffefff))
+#define SET_RG_FORCE_11B_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 13) | ((REG32(ADR_PHY_EN_1)) & 0xffffdfff))
+#define SET_RG_FFT_MEM_CLK_EN_RX(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 14) | ((REG32(ADR_PHY_EN_1)) & 0xffffbfff))
+#define SET_RG_FFT_MEM_CLK_EN_TX(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 15) | ((REG32(ADR_PHY_EN_1)) & 0xffff7fff))
+#define SET_RG_PHY_IQ_TRIG_SEL(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_EN_1)) & 0xfff0ffff))
+#define SET_RG_SPECTRUM_FREQ(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 20) | ((REG32(ADR_PHY_EN_1)) & 0xc00fffff))
+#define SET_SVN_VERSION(_VAL_) (REG32(ADR_SVN_VERSION_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SVN_VERSION_REG)) & 0x00000000))
+#define SET_RG_LENGTH(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0xffff0000))
+#define SET_RG_PKT_MODE(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0xfff8ffff))
+#define SET_RG_CH_BW(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 19) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0xffc7ffff))
+#define SET_RG_PRM(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 22) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0xffbfffff))
+#define SET_RG_SHORTGI(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 23) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0xff7fffff))
+#define SET_RG_RATE(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0x80ffffff))
+#define SET_RG_L_LENGTH(_VAL_) (REG32(ADR_PHY_PKT_GEN_1)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_PKT_GEN_1)) & 0xfffff000))
+#define SET_RG_L_RATE(_VAL_) (REG32(ADR_PHY_PKT_GEN_1)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_PKT_GEN_1)) & 0xffff8fff))
+#define SET_RG_SERVICE(_VAL_) (REG32(ADR_PHY_PKT_GEN_1)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_PKT_GEN_1)) & 0x0000ffff))
+#define SET_RG_SMOOTHING(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xfffffffe))
+#define SET_RG_NO_SOUND(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 1) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xfffffffd))
+#define SET_RG_AGGREGATE(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 2) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xfffffffb))
+#define SET_RG_STBC(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 3) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xffffffe7))
+#define SET_RG_FEC(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 5) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xffffffdf))
+#define SET_RG_N_ESS(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 6) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xffffff3f))
+#define SET_RG_TXPWRLVL(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xffff00ff))
+#define SET_RG_TX_START(_VAL_) (REG32(ADR_PHY_PKT_GEN_3)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_PKT_GEN_3)) & 0xfffffffe))
+#define SET_RG_IFS_TIME(_VAL_) (REG32(ADR_PHY_PKT_GEN_3)) = (((_VAL_) << 2) | ((REG32(ADR_PHY_PKT_GEN_3)) & 0xffffff03))
+#define SET_RG_CONTINUOUS_DATA(_VAL_) (REG32(ADR_PHY_PKT_GEN_3)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_PKT_GEN_3)) & 0xfffffeff))
+#define SET_RG_DATA_SEL(_VAL_) (REG32(ADR_PHY_PKT_GEN_3)) = (((_VAL_) << 9) | ((REG32(ADR_PHY_PKT_GEN_3)) & 0xfffff9ff))
+#define SET_RG_TX_D(_VAL_) (REG32(ADR_PHY_PKT_GEN_3)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_PKT_GEN_3)) & 0xff00ffff))
+#define SET_RG_TX_CNT_TARGET(_VAL_) (REG32(ADR_PHY_PKT_GEN_4)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_PKT_GEN_4)) & 0x00000000))
+#define SET_RG_FFT_IFFT_MODE(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 6) | ((REG32(ADR_PHY_REG_00)) & 0xffffff3f))
+#define SET_RG_DAC_DBG_MODE(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_00)) & 0xfffffeff))
+#define SET_RG_DAC_SGN_SWAP(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 9) | ((REG32(ADR_PHY_REG_00)) & 0xfffffdff))
+#define SET_RG_TXD_SEL(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 10) | ((REG32(ADR_PHY_REG_00)) & 0xfffff3ff))
+#define SET_RG_UP8X(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_00)) & 0xff00ffff))
+#define SET_RG_IQ_DC_BYP(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_00)) & 0xfeffffff))
+#define SET_RG_IQ_DC_LEAKY_FACTOR(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_00)) & 0xcfffffff))
+#define SET_RG_DAC_DCEN(_VAL_) (REG32(ADR_PHY_REG_01)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_01)) & 0xfffffffe))
+#define SET_RG_DAC_DCQ(_VAL_) (REG32(ADR_PHY_REG_01)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_REG_01)) & 0xffffc00f))
+#define SET_RG_DAC_DCI(_VAL_) (REG32(ADR_PHY_REG_01)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_01)) & 0xfc00ffff))
+#define SET_RG_PGA_REFDB_SAT(_VAL_) (REG32(ADR_PHY_REG_02_AGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_02_AGC)) & 0xffffff80))
+#define SET_RG_PGA_REFDB_TOP(_VAL_) (REG32(ADR_PHY_REG_02_AGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_02_AGC)) & 0xffff80ff))
+#define SET_RG_PGA_REF_UND(_VAL_) (REG32(ADR_PHY_REG_02_AGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_02_AGC)) & 0xfc00ffff))
+#define SET_RG_RF_REF_SAT(_VAL_) (REG32(ADR_PHY_REG_02_AGC)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_02_AGC)) & 0x0fffffff))
+#define SET_RG_PGAGC_SET(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xfffffff0))
+#define SET_RG_PGAGC_OW(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffffffef))
+#define SET_RG_RFGC_SET(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 5) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffffff9f))
+#define SET_RG_RFGC_OW(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 7) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffffff7f))
+#define SET_RG_WAIT_T_RXAGC(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffffc0ff))
+#define SET_RG_RXAGC_SET(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 14) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffffbfff))
+#define SET_RG_RXAGC_OW(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 15) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffff7fff))
+#define SET_RG_WAIT_T_FINAL(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffc0ffff))
+#define SET_RG_WAIT_T(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xc0ffffff))
+#define SET_RG_ULG_PGA_SAT_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xfffffff0))
+#define SET_RG_LG_PGA_UND_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xffffff0f))
+#define SET_RG_LG_PGA_SAT_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xfffff0ff))
+#define SET_RG_LG_RF_SAT_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xffff0fff))
+#define SET_RG_MG_RF_SAT_PGANOREF_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xfff0ffff))
+#define SET_RG_HG_PGA_SAT2_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 20) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xff0fffff))
+#define SET_RG_HG_PGA_SAT1_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xf0ffffff))
+#define SET_RG_HG_RF_SAT_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_04_AGC)) & 0x0fffffff))
+#define SET_RG_MG_PGA_JB_TH(_VAL_) (REG32(ADR_PHY_REG_05_AGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_05_AGC)) & 0xfffffff0))
+#define SET_RG_MA_PGA_LOW_TH_CNT_LMT(_VAL_) (REG32(ADR_PHY_REG_05_AGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_05_AGC)) & 0xffe0ffff))
+#define SET_RG_WR_RFGC_INIT_SET(_VAL_) (REG32(ADR_PHY_REG_05_AGC)) = (((_VAL_) << 21) | ((REG32(ADR_PHY_REG_05_AGC)) & 0xff9fffff))
+#define SET_RG_WR_RFGC_INIT_EN(_VAL_) (REG32(ADR_PHY_REG_05_AGC)) = (((_VAL_) << 23) | ((REG32(ADR_PHY_REG_05_AGC)) & 0xff7fffff))
+#define SET_RG_MA_PGA_HIGH_TH_CNT_LMT(_VAL_) (REG32(ADR_PHY_REG_05_AGC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_05_AGC)) & 0xe0ffffff))
+#define SET_RG_AGC_THRESHOLD(_VAL_) (REG32(ADR_PHY_REG_06_11B_DAGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0xffffc000))
+#define SET_RG_ACI_POINT_CNT_LMT_11B(_VAL_) (REG32(ADR_PHY_REG_06_11B_DAGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0xff80ffff))
+#define SET_RG_ACI_DAGC_LEAKY_FACTOR_11B(_VAL_) (REG32(ADR_PHY_REG_06_11B_DAGC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0xfcffffff))
+#define SET_RG_WR_ACI_GAIN_INI_SEL_11B(_VAL_) (REG32(ADR_PHY_REG_07_11B_DAGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0xffffff00))
+#define SET_RG_WR_ACI_GAIN_SEL_11B(_VAL_) (REG32(ADR_PHY_REG_07_11B_DAGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0xffff00ff))
+#define SET_RG_ACI_DAGC_SET_VALUE_11B(_VAL_) (REG32(ADR_PHY_REG_07_11B_DAGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0xff80ffff))
+#define SET_RG_WR_ACI_GAIN_OW_11B(_VAL_) (REG32(ADR_PHY_REG_07_11B_DAGC)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0x7fffffff))
+#define SET_RG_ACI_POINT_CNT_LMT_11GN(_VAL_) (REG32(ADR_PHY_REG_08_11GN_DAGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0xffffff00))
+#define SET_RG_ACI_DAGC_LEAKY_FACTOR_11GN(_VAL_) (REG32(ADR_PHY_REG_08_11GN_DAGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0xfffffcff))
+#define SET_RG_ACI_DAGC_DONE_CNT_LMT_11GN(_VAL_) (REG32(ADR_PHY_REG_08_11GN_DAGC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0x00ffffff))
+#define SET_RG_ACI_DAGC_SET_VALUE_11GN(_VAL_) (REG32(ADR_PHY_REG_09_11GN_DAGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0xffffff80))
+#define SET_RG_ACI_GAIN_INI_VAL_11GN(_VAL_) (REG32(ADR_PHY_REG_09_11GN_DAGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0xffff00ff))
+#define SET_RG_ACI_GAIN_OW_VAL_11GN(_VAL_) (REG32(ADR_PHY_REG_09_11GN_DAGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0xff00ffff))
+#define SET_RG_ACI_GAIN_OW_11GN(_VAL_) (REG32(ADR_PHY_REG_09_11GN_DAGC)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0x7fffffff))
+#define SET_RO_CCA_PWR_MA_11GN(_VAL_) (REG32(ADR_PHY_READ_REG_00_DIG_PWR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0xffffff80))
+#define SET_RO_ED_STATE(_VAL_) (REG32(ADR_PHY_READ_REG_00_DIG_PWR)) = (((_VAL_) << 15) | ((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0xffff7fff))
+#define SET_RO_CCA_PWR_MA_11B(_VAL_) (REG32(ADR_PHY_READ_REG_00_DIG_PWR)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0xff80ffff))
+#define SET_RO_PGA_PWR_FF1(_VAL_) (REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0xffffc000))
+#define SET_RO_RF_PWR_FF1(_VAL_) (REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0xfff0ffff))
+#define SET_RO_PGAGC_FF1(_VAL_) (REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0xf0ffffff))
+#define SET_RO_RFGC_FF1(_VAL_) (REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0xcfffffff))
+#define SET_RO_PGA_PWR_FF2(_VAL_) (REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0xffffc000))
+#define SET_RO_RF_PWR_FF2(_VAL_) (REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0xfff0ffff))
+#define SET_RO_PGAGC_FF2(_VAL_) (REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0xf0ffffff))
+#define SET_RO_RFGC_FF2(_VAL_) (REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0xcfffffff))
+#define SET_RO_PGA_PWR_FF3(_VAL_) (REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0xffffc000))
+#define SET_RO_RF_PWR_FF3(_VAL_) (REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0xfff0ffff))
+#define SET_RO_PGAGC_FF3(_VAL_) (REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0xf0ffffff))
+#define SET_RO_RFGC_FF3(_VAL_) (REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0xcfffffff))
+#define SET_RG_TX_DES_RATE(_VAL_) (REG32(ADR_PHY_REG_10_TX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_10_TX_DES)) & 0xffffffe0))
+#define SET_RG_TX_DES_MODE(_VAL_) (REG32(ADR_PHY_REG_10_TX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_10_TX_DES)) & 0xffffe0ff))
+#define SET_RG_TX_DES_LEN_LO(_VAL_) (REG32(ADR_PHY_REG_10_TX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_10_TX_DES)) & 0xffe0ffff))
+#define SET_RG_TX_DES_LEN_UP(_VAL_) (REG32(ADR_PHY_REG_10_TX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_10_TX_DES)) & 0xe0ffffff))
+#define SET_RG_TX_DES_SRVC_UP(_VAL_) (REG32(ADR_PHY_REG_11_TX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_11_TX_DES)) & 0xffffffe0))
+#define SET_RG_TX_DES_L_LEN_LO(_VAL_) (REG32(ADR_PHY_REG_11_TX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_11_TX_DES)) & 0xffffe0ff))
+#define SET_RG_TX_DES_L_LEN_UP(_VAL_) (REG32(ADR_PHY_REG_11_TX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_11_TX_DES)) & 0xffe0ffff))
+#define SET_RG_TX_DES_TYPE(_VAL_) (REG32(ADR_PHY_REG_11_TX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_11_TX_DES)) & 0xe0ffffff))
+#define SET_RG_TX_DES_L_LEN_UP_COMB(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xfffffffe))
+#define SET_RG_TX_DES_TYPE_COMB(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xffffffef))
+#define SET_RG_TX_DES_RATE_COMB(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xfffffeff))
+#define SET_RG_TX_DES_MODE_COMB(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xffffefff))
+#define SET_RG_TX_DES_PWRLVL(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xffe0ffff))
+#define SET_RG_TX_DES_SRVC_LO(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xe0ffffff))
+#define SET_RG_RX_DES_RATE(_VAL_) (REG32(ADR_PHY_REG_13_RX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_13_RX_DES)) & 0xffffffc0))
+#define SET_RG_RX_DES_MODE(_VAL_) (REG32(ADR_PHY_REG_13_RX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_13_RX_DES)) & 0xffffc0ff))
+#define SET_RG_RX_DES_LEN_LO(_VAL_) (REG32(ADR_PHY_REG_13_RX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_13_RX_DES)) & 0xffc0ffff))
+#define SET_RG_RX_DES_LEN_UP(_VAL_) (REG32(ADR_PHY_REG_13_RX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_13_RX_DES)) & 0xc0ffffff))
+#define SET_RG_RX_DES_SRVC_UP(_VAL_) (REG32(ADR_PHY_REG_14_RX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_14_RX_DES)) & 0xffffffc0))
+#define SET_RG_RX_DES_L_LEN_LO(_VAL_) (REG32(ADR_PHY_REG_14_RX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_14_RX_DES)) & 0xffffc0ff))
+#define SET_RG_RX_DES_L_LEN_UP(_VAL_) (REG32(ADR_PHY_REG_14_RX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_14_RX_DES)) & 0xffc0ffff))
+#define SET_RG_RX_DES_TYPE(_VAL_) (REG32(ADR_PHY_REG_14_RX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_14_RX_DES)) & 0xc0ffffff))
+#define SET_RG_RX_DES_L_LEN_UP_COMB(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xfffffffe))
+#define SET_RG_RX_DES_TYPE_COMB(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xffffffef))
+#define SET_RG_RX_DES_RATE_COMB(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xfffffeff))
+#define SET_RG_RX_DES_MODE_COMB(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xffffefff))
+#define SET_RG_RX_DES_SNR(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xfff0ffff))
+#define SET_RG_RX_DES_RCPI(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 20) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xff0fffff))
+#define SET_RG_RX_DES_SRVC_LO(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xc0ffffff))
+#define SET_RO_TX_DES_EXCP_RATE_CNT(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0xffffff00))
+#define SET_RO_TX_DES_EXCP_CH_BW_CNT(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0xffff00ff))
+#define SET_RO_TX_DES_EXCP_MODE_CNT(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0xff00ffff))
+#define SET_RG_TX_DES_EXCP_RATE_DEFAULT(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0xf8ffffff))
+#define SET_RG_TX_DES_EXCP_MODE_DEFAULT(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x8fffffff))
+#define SET_RG_TX_DES_EXCP_CLR(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x7fffffff))
+#define SET_RG_TX_DES_ACK_WIDTH(_VAL_) (REG32(ADR_PHY_REG_17_TX_DES_EXCP)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0xfffffffe))
+#define SET_RG_TX_DES_ACK_PRD(_VAL_) (REG32(ADR_PHY_REG_17_TX_DES_EXCP)) = (((_VAL_) << 1) | ((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0xfffffff1))
+#define SET_RG_RX_DES_SNR_GN(_VAL_) (REG32(ADR_PHY_REG_17_TX_DES_EXCP)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0xffc0ffff))
+#define SET_RG_RX_DES_RCPI_GN(_VAL_) (REG32(ADR_PHY_REG_17_TX_DES_EXCP)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0xc0ffffff))
+#define SET_RG_TST_TBUS_SEL(_VAL_) (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0xfffffff0))
+#define SET_RG_RSSI_OFFSET(_VAL_) (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0xff00ffff))
+#define SET_RG_RSSI_INV(_VAL_) (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0xfeffffff))
+#define SET_RG_TST_ADC_ON(_VAL_) (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (((_VAL_) << 30) | ((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0xbfffffff))
+#define SET_RG_TST_EXT_GAIN(_VAL_) (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x7fffffff))
+#define SET_RG_DAC_Q_SET(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0xfffffc00))
+#define SET_RG_DAC_I_SET(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0xffc00fff))
+#define SET_RG_DAC_EN_MAN(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0xefffffff))
+#define SET_RG_IQC_FFT_EN(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 29) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0xdfffffff))
+#define SET_RG_DAC_MAN_Q_EN(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 30) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0xbfffffff))
+#define SET_RG_DAC_MAN_I_EN(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x7fffffff))
+#define SET_RO_MRX_EN_CNT(_VAL_) (REG32(ADR_PHY_REG_20_MRX_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_20_MRX_CNT)) & 0xffff0000))
+#define SET_RG_MRX_EN_CNT_RST_N(_VAL_) (REG32(ADR_PHY_REG_20_MRX_CNT)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_20_MRX_CNT)) & 0x7fffffff))
+#define SET_RG_PA_RISE_TIME(_VAL_) (REG32(ADR_PHY_REG_21_TRX_RAMP)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0xffffff00))
+#define SET_RG_RFTX_RISE_TIME(_VAL_) (REG32(ADR_PHY_REG_21_TRX_RAMP)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0xffff00ff))
+#define SET_RG_DAC_RISE_TIME(_VAL_) (REG32(ADR_PHY_REG_21_TRX_RAMP)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0xff00ffff))
+#define SET_RG_SW_RISE_TIME(_VAL_) (REG32(ADR_PHY_REG_21_TRX_RAMP)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0x00ffffff))
+#define SET_RG_PA_FALL_TIME(_VAL_) (REG32(ADR_PHY_REG_22_TRX_RAMP)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0xffffff00))
+#define SET_RG_RFTX_FALL_TIME(_VAL_) (REG32(ADR_PHY_REG_22_TRX_RAMP)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0xffff00ff))
+#define SET_RG_DAC_FALL_TIME(_VAL_) (REG32(ADR_PHY_REG_22_TRX_RAMP)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0xff00ffff))
+#define SET_RG_SW_FALL_TIME(_VAL_) (REG32(ADR_PHY_REG_22_TRX_RAMP)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0x00ffffff))
+#define SET_RG_ANT_SW_0(_VAL_) (REG32(ADR_PHY_REG_23_ANT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_23_ANT)) & 0xfffffff8))
+#define SET_RG_ANT_SW_1(_VAL_) (REG32(ADR_PHY_REG_23_ANT)) = (((_VAL_) << 3) | ((REG32(ADR_PHY_REG_23_ANT)) & 0xffffffc7))
+#define SET_RG_MTX_LEN_LOWER_TH_0(_VAL_) (REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0xffffe000))
+#define SET_RG_MTX_LEN_UPPER_TH_0(_VAL_) (REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0xe000ffff))
+#define SET_RG_MTX_LEN_CNT_EN_0(_VAL_) (REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0x7fffffff))
+#define SET_RG_MTX_LEN_LOWER_TH_1(_VAL_) (REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0xffffe000))
+#define SET_RG_MTX_LEN_UPPER_TH_1(_VAL_) (REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0xe000ffff))
+#define SET_RG_MTX_LEN_CNT_EN_1(_VAL_) (REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0x7fffffff))
+#define SET_RG_MRX_LEN_LOWER_TH_0(_VAL_) (REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0xffffe000))
+#define SET_RG_MRX_LEN_UPPER_TH_0(_VAL_) (REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0xe000ffff))
+#define SET_RG_MRX_LEN_CNT_EN_0(_VAL_) (REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0x7fffffff))
+#define SET_RG_MRX_LEN_LOWER_TH_1(_VAL_) (REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0xffffe000))
+#define SET_RG_MRX_LEN_UPPER_TH_1(_VAL_) (REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0xe000ffff))
+#define SET_RG_MRX_LEN_CNT_EN_1(_VAL_) (REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0x7fffffff))
+#define SET_RO_MTX_LEN_CNT_1(_VAL_) (REG32(ADR_PHY_READ_REG_04)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_04)) & 0xffff0000))
+#define SET_RO_MTX_LEN_CNT_0(_VAL_) (REG32(ADR_PHY_READ_REG_04)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_04)) & 0x0000ffff))
+#define SET_RO_MRX_LEN_CNT_1(_VAL_) (REG32(ADR_PHY_READ_REG_05)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_05)) & 0xffff0000))
+#define SET_RO_MRX_LEN_CNT_0(_VAL_) (REG32(ADR_PHY_READ_REG_05)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_05)) & 0x0000ffff))
+#define SET_RG_MODE_REG_IN_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xffff0000))
+#define SET_RG_PARALLEL_DR_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 20) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xffefffff))
+#define SET_RG_MBRUN_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xfeffffff))
+#define SET_RG_SHIFT_DR_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xefffffff))
+#define SET_RG_MODE_REG_SI_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 29) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xdfffffff))
+#define SET_RG_SIMULATION_MODE_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 30) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xbfffffff))
+#define SET_RG_DBIST_MODE_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_28_BIST)) & 0x7fffffff))
+#define SET_RO_MODE_REG_OUT_16(_VAL_) (REG32(ADR_PHY_READ_REG_06_BIST)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_06_BIST)) & 0xffff0000))
+#define SET_RO_MODE_REG_SO_16(_VAL_) (REG32(ADR_PHY_READ_REG_06_BIST)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_READ_REG_06_BIST)) & 0xfeffffff))
+#define SET_RO_MONITOR_BUS_16(_VAL_) (REG32(ADR_PHY_READ_REG_07_BIST)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_07_BIST)) & 0xfff80000))
+#define SET_RG_MRX_TYPE_1(_VAL_) (REG32(ADR_PHY_REG_29_MTRX_MAC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0xffffff00))
+#define SET_RG_MRX_TYPE_0(_VAL_) (REG32(ADR_PHY_REG_29_MTRX_MAC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0xffff00ff))
+#define SET_RG_MTX_TYPE_1(_VAL_) (REG32(ADR_PHY_REG_29_MTRX_MAC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0xff00ffff))
+#define SET_RG_MTX_TYPE_0(_VAL_) (REG32(ADR_PHY_REG_29_MTRX_MAC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0x00ffffff))
+#define SET_RO_MTX_TYPE_CNT_1(_VAL_) (REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) & 0xffff0000))
+#define SET_RO_MTX_TYPE_CNT_0(_VAL_) (REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) & 0x0000ffff))
+#define SET_RO_MRX_TYPE_CNT_1(_VAL_) (REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) & 0xffff0000))
+#define SET_RO_MRX_TYPE_CNT_0(_VAL_) (REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) & 0x0000ffff))
+#define SET_RG_HB_COEF0(_VAL_) (REG32(ADR_PHY_REG_30_TX_UP_FIL)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_30_TX_UP_FIL)) & 0xfffff000))
+#define SET_RG_HB_COEF1(_VAL_) (REG32(ADR_PHY_REG_30_TX_UP_FIL)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_30_TX_UP_FIL)) & 0xf000ffff))
+#define SET_RG_HB_COEF2(_VAL_) (REG32(ADR_PHY_REG_31_TX_UP_FIL)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_31_TX_UP_FIL)) & 0xfffff000))
+#define SET_RG_HB_COEF3(_VAL_) (REG32(ADR_PHY_REG_31_TX_UP_FIL)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_31_TX_UP_FIL)) & 0xf000ffff))
+#define SET_RG_HB_COEF4(_VAL_) (REG32(ADR_PHY_REG_32_TX_UP_FIL)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_32_TX_UP_FIL)) & 0xfffff000))
+#define SET_RO_TBUS_O(_VAL_) (REG32(ADR_PHY_READ_TBUS)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_TBUS)) & 0xfff00000))
+#define SET_RG_LPF4_00(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_00)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_00)) & 0xffffe000))
+#define SET_RG_LPF4_01(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_01)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_01)) & 0xffffe000))
+#define SET_RG_LPF4_02(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_02)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_02)) & 0xffffe000))
+#define SET_RG_LPF4_03(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_03)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_03)) & 0xffffe000))
+#define SET_RG_LPF4_04(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_04)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_04)) & 0xffffe000))
+#define SET_RG_LPF4_05(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_05)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_05)) & 0xffffe000))
+#define SET_RG_LPF4_06(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_06)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_06)) & 0xffffe000))
+#define SET_RG_LPF4_07(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_07)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_07)) & 0xffffe000))
+#define SET_RG_LPF4_08(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_08)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_08)) & 0xffffe000))
+#define SET_RG_LPF4_09(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_09)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_09)) & 0xffffe000))
+#define SET_RG_LPF4_10(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_10)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_10)) & 0xffffe000))
+#define SET_RG_LPF4_11(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_11)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_11)) & 0xffffe000))
+#define SET_RG_LPF4_12(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_12)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_12)) & 0xffffe000))
+#define SET_RG_LPF4_13(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_13)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_13)) & 0xffffe000))
+#define SET_RG_LPF4_14(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_14)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_14)) & 0xffffe000))
+#define SET_RG_LPF4_15(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_15)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_15)) & 0xffffe000))
+#define SET_RG_LPF4_16(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_16)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_16)) & 0xffffe000))
+#define SET_RG_LPF4_17(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_17)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_17)) & 0xffffe000))
+#define SET_RG_LPF4_18(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_18)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_18)) & 0xffffe000))
+#define SET_RG_LPF4_19(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_19)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_19)) & 0xffffe000))
+#define SET_RG_LPF4_20(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_20)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_20)) & 0xffffe000))
+#define SET_RG_LPF4_21(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_21)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_21)) & 0xffffe000))
+#define SET_RG_LPF4_22(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_22)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_22)) & 0xffffe000))
+#define SET_RG_LPF4_23(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_23)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_23)) & 0xffffe000))
+#define SET_RG_LPF4_24(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_24)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_24)) & 0xffffe000))
+#define SET_RG_LPF4_25(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_25)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_25)) & 0xffffe000))
+#define SET_RG_LPF4_26(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_26)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_26)) & 0xffffe000))
+#define SET_RG_LPF4_27(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_27)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_27)) & 0xffffe000))
+#define SET_RG_LPF4_28(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_28)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_28)) & 0xffffe000))
+#define SET_RG_LPF4_29(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_29)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_29)) & 0xffffe000))
+#define SET_RG_LPF4_30(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_30)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_30)) & 0xffffe000))
+#define SET_RG_LPF4_31(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_31)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_31)) & 0xffffe000))
+#define SET_RG_LPF4_32(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_32)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_32)) & 0xffffe000))
+#define SET_RG_LPF4_33(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_33)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_33)) & 0xffffe000))
+#define SET_RG_LPF4_34(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_34)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_34)) & 0xffffe000))
+#define SET_RG_LPF4_35(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_35)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_35)) & 0xffffe000))
+#define SET_RG_LPF4_36(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_36)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_36)) & 0xffffe000))
+#define SET_RG_LPF4_37(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_37)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_37)) & 0xffffe000))
+#define SET_RG_LPF4_38(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_38)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_38)) & 0xffffe000))
+#define SET_RG_LPF4_39(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_39)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_39)) & 0xffffe000))
+#define SET_RG_LPF4_40(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_40)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_40)) & 0xffffe000))
+#define SET_RG_BP_SMB(_VAL_) (REG32(ADR_TX_11B_PLCP)) = (((_VAL_) << 13) | ((REG32(ADR_TX_11B_PLCP)) & 0xffffdfff))
+#define SET_RG_EN_SRVC(_VAL_) (REG32(ADR_TX_11B_PLCP)) = (((_VAL_) << 14) | ((REG32(ADR_TX_11B_PLCP)) & 0xffffbfff))
+#define SET_RG_DES_SPD(_VAL_) (REG32(ADR_TX_11B_PLCP)) = (((_VAL_) << 16) | ((REG32(ADR_TX_11B_PLCP)) & 0xfffcffff))
+#define SET_RG_BB_11B_RISE_TIME(_VAL_) (REG32(ADR_TX_11B_RAMP)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_RAMP)) & 0xffffff00))
+#define SET_RG_BB_11B_FALL_TIME(_VAL_) (REG32(ADR_TX_11B_RAMP)) = (((_VAL_) << 8) | ((REG32(ADR_TX_11B_RAMP)) & 0xffff00ff))
+#define SET_RG_WR_TX_EN_CNT_RST_N(_VAL_) (REG32(ADR_TX_11B_EN_CNT_RST_N)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_EN_CNT_RST_N)) & 0xfffffffe))
+#define SET_RO_TX_EN_CNT(_VAL_) (REG32(ADR_TX_11B_EN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_EN_CNT)) & 0xffff0000))
+#define SET_RO_TX_CNT(_VAL_) (REG32(ADR_TX_11B_PKT_GEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_PKT_GEN_CNT)) & 0x00000000))
+#define SET_RG_POS_DES_11B_L_EXT(_VAL_) (REG32(ADR_RX_11B_DES_DLY)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_DES_DLY)) & 0xfffffff0))
+#define SET_RG_PRE_DES_11B_DLY(_VAL_) (REG32(ADR_RX_11B_DES_DLY)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_DES_DLY)) & 0xffffff0f))
+#define SET_RG_CNT_CCA_LMT(_VAL_) (REG32(ADR_RX_11B_CCA_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CCA_0)) & 0xfff0ffff))
+#define SET_RG_BYPASS_DESCRAMBLER(_VAL_) (REG32(ADR_RX_11B_CCA_0)) = (((_VAL_) << 29) | ((REG32(ADR_RX_11B_CCA_0)) & 0xdfffffff))
+#define SET_RG_BYPASS_AGC(_VAL_) (REG32(ADR_RX_11B_CCA_0)) = (((_VAL_) << 31) | ((REG32(ADR_RX_11B_CCA_0)) & 0x7fffffff))
+#define SET_RG_CCA_BIT_CNT_LMT_RX(_VAL_) (REG32(ADR_RX_11B_CCA_1)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_CCA_1)) & 0xffffff0f))
+#define SET_RG_CCA_SCALE_BF(_VAL_) (REG32(ADR_RX_11B_CCA_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CCA_1)) & 0xff80ffff))
+#define SET_RG_PEAK_IDX_CNT_SEL(_VAL_) (REG32(ADR_RX_11B_CCA_1)) = (((_VAL_) << 28) | ((REG32(ADR_RX_11B_CCA_1)) & 0xcfffffff))
+#define SET_RG_TR_KI_T2(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0xfffffff8))
+#define SET_RG_TR_KP_T2(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_0)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0xffffff8f))
+#define SET_RG_TR_KI_T1(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0xfffff8ff))
+#define SET_RG_TR_KP_T1(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_0)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0xffff8fff))
+#define SET_RG_CR_KI_T1(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_TR_KP_KI_1)) & 0xfff8ffff))
+#define SET_RG_CR_KP_T1(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_1)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_TR_KP_KI_1)) & 0xff8fffff))
+#define SET_RG_CHIP_CNT_SLICER(_VAL_) (REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0xffffffe0))
+#define SET_RG_CE_T4_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0xffff00ff))
+#define SET_RG_CE_T3_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0xff00ffff))
+#define SET_RG_CE_T2_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0x00ffffff))
+#define SET_RG_CE_MU_T1(_VAL_) (REG32(ADR_RX_11B_CE_MU_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_CE_MU_0)) & 0xfffffff8))
+#define SET_RG_CE_DLY_SEL(_VAL_) (REG32(ADR_RX_11B_CE_MU_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CE_MU_0)) & 0xffc0ffff))
+#define SET_RG_CE_MU_T8(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xfffffff8))
+#define SET_RG_CE_MU_T7(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xffffff8f))
+#define SET_RG_CE_MU_T6(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xfffff8ff))
+#define SET_RG_CE_MU_T5(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xffff8fff))
+#define SET_RG_CE_MU_T4(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xfff8ffff))
+#define SET_RG_CE_MU_T3(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xff8fffff))
+#define SET_RG_CE_MU_T2(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xf8ffffff))
+#define SET_RG_EQ_MU_FB_T2(_VAL_) (REG32(ADR_RX_11B_EQ_MU_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_EQ_MU_0)) & 0xfffffff0))
+#define SET_RG_EQ_MU_FF_T2(_VAL_) (REG32(ADR_RX_11B_EQ_MU_0)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_EQ_MU_0)) & 0xffffff0f))
+#define SET_RG_EQ_MU_FB_T1(_VAL_) (REG32(ADR_RX_11B_EQ_MU_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_EQ_MU_0)) & 0xfff0ffff))
+#define SET_RG_EQ_MU_FF_T1(_VAL_) (REG32(ADR_RX_11B_EQ_MU_0)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_EQ_MU_0)) & 0xff0fffff))
+#define SET_RG_EQ_MU_FB_T4(_VAL_) (REG32(ADR_RX_11B_EQ_MU_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_EQ_MU_1)) & 0xfffffff0))
+#define SET_RG_EQ_MU_FF_T4(_VAL_) (REG32(ADR_RX_11B_EQ_MU_1)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_EQ_MU_1)) & 0xffffff0f))
+#define SET_RG_EQ_MU_FB_T3(_VAL_) (REG32(ADR_RX_11B_EQ_MU_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_EQ_MU_1)) & 0xfff0ffff))
+#define SET_RG_EQ_MU_FF_T3(_VAL_) (REG32(ADR_RX_11B_EQ_MU_1)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_EQ_MU_1)) & 0xff0fffff))
+#define SET_RG_EQ_KI_T2(_VAL_) (REG32(ADR_RX_11B_EQ_CR_KP_KI)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0xfffff8ff))
+#define SET_RG_EQ_KP_T2(_VAL_) (REG32(ADR_RX_11B_EQ_CR_KP_KI)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0xffff8fff))
+#define SET_RG_EQ_KI_T1(_VAL_) (REG32(ADR_RX_11B_EQ_CR_KP_KI)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0xfff8ffff))
+#define SET_RG_EQ_KP_T1(_VAL_) (REG32(ADR_RX_11B_EQ_CR_KP_KI)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0xff8fffff))
+#define SET_RG_TR_LPF_RATE(_VAL_) (REG32(ADR_RX_11B_LPF_RATE)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_LPF_RATE)) & 0xffc00000))
+#define SET_RG_CE_BIT_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0xffffff80))
+#define SET_RG_CE_CH_MAIN_SET(_VAL_) (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (((_VAL_) << 7) | ((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0xffffff7f))
+#define SET_RG_TC_BIT_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0xffff80ff))
+#define SET_RG_CR_BIT_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0xff80ffff))
+#define SET_RG_TR_BIT_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x80ffffff))
+#define SET_RG_EQ_MAIN_TAP_MAN(_VAL_) (REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) & 0xfffffffe))
+#define SET_RG_EQ_MAIN_TAP_COEF(_VAL_) (REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) & 0xf800ffff))
+#define SET_RG_PWRON_DLY_TH_11B(_VAL_) (REG32(ADR_RX_11B_SEARCH_CNT_TH)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SEARCH_CNT_TH)) & 0xffffff00))
+#define SET_RG_SFD_BIT_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_SEARCH_CNT_TH)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_SEARCH_CNT_TH)) & 0xff00ffff))
+#define SET_RG_CCA_PWR_TH_RX(_VAL_) (REG32(ADR_RX_11B_CCA_CONTROL)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_CCA_CONTROL)) & 0xffff8000))
+#define SET_RG_CCA_PWR_CNT_TH(_VAL_) (REG32(ADR_RX_11B_CCA_CONTROL)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CCA_CONTROL)) & 0xffe0ffff))
+#define SET_B_FREQ_OS(_VAL_) (REG32(ADR_RX_11B_FREQUENCY_OFFSET)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_FREQUENCY_OFFSET)) & 0xfffff800))
+#define SET_B_SNR(_VAL_) (REG32(ADR_RX_11B_SNR_RSSI)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SNR_RSSI)) & 0xffffff80))
+#define SET_B_RCPI(_VAL_) (REG32(ADR_RX_11B_SNR_RSSI)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_SNR_RSSI)) & 0xff80ffff))
+#define SET_CRC_CNT(_VAL_) (REG32(ADR_RX_11B_SFD_CRC_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SFD_CRC_CNT)) & 0xffff0000))
+#define SET_SFD_CNT(_VAL_) (REG32(ADR_RX_11B_SFD_CRC_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_SFD_CRC_CNT)) & 0x0000ffff))
+#define SET_B_PACKET_ERR_CNT(_VAL_) (REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) & 0xffff0000))
+#define SET_PACKET_ERR(_VAL_) (REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) & 0xfffeffff))
+#define SET_B_PACKET_CNT(_VAL_) (REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) & 0xffff0000))
+#define SET_B_CCA_CNT(_VAL_) (REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) & 0x0000ffff))
+#define SET_B_LENGTH_FIELD(_VAL_) (REG32(ADR_RX_11B_SFD_FILED_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SFD_FILED_0)) & 0xffff0000))
+#define SET_SFD_FIELD(_VAL_) (REG32(ADR_RX_11B_SFD_FILED_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_SFD_FILED_0)) & 0x0000ffff))
+#define SET_SIGNAL_FIELD(_VAL_) (REG32(ADR_RX_11B_SFD_FIELD_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0xffffff00))
+#define SET_B_SERVICE_FIELD(_VAL_) (REG32(ADR_RX_11B_SFD_FIELD_1)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0xffff00ff))
+#define SET_CRC_CORRECT(_VAL_) (REG32(ADR_RX_11B_SFD_FIELD_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0xfffeffff))
+#define SET_DEBUG_SEL(_VAL_) (REG32(ADR_RX_11B_PKT_STAT_EN)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0xfffffff0))
+#define SET_RG_PACKET_STAT_EN_11B(_VAL_) (REG32(ADR_RX_11B_PKT_STAT_EN)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0xffefffff))
+#define SET_RG_BIT_REVERSE(_VAL_) (REG32(ADR_RX_11B_PKT_STAT_EN)) = (((_VAL_) << 21) | ((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0xffdfffff))
+#define SET_RX_PHY_11B_SOFT_RST_N(_VAL_) (REG32(ADR_RX_11B_SOFT_RST)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SOFT_RST)) & 0xfffffffe))
+#define SET_RG_CE_BYPASS_TAP(_VAL_) (REG32(ADR_RX_11B_SOFT_RST)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_SOFT_RST)) & 0xffffff0f))
+#define SET_RG_EQ_BYPASS_FBW_TAP(_VAL_) (REG32(ADR_RX_11B_SOFT_RST)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_SOFT_RST)) & 0xfffff0ff))
+#define SET_RG_BB_11GN_RISE_TIME(_VAL_) (REG32(ADR_TX_11GN_RAMP)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11GN_RAMP)) & 0xffffff00))
+#define SET_RG_BB_11GN_FALL_TIME(_VAL_) (REG32(ADR_TX_11GN_RAMP)) = (((_VAL_) << 8) | ((REG32(ADR_TX_11GN_RAMP)) & 0xffff00ff))
+#define SET_RG_HTCARR52_FFT_SCALE(_VAL_) (REG32(ADR_TX_11GN_PLCP)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11GN_PLCP)) & 0xfffffc00))
+#define SET_RG_HTCARR56_FFT_SCALE(_VAL_) (REG32(ADR_TX_11GN_PLCP)) = (((_VAL_) << 12) | ((REG32(ADR_TX_11GN_PLCP)) & 0xffc00fff))
+#define SET_RG_PACKET_STAT_EN(_VAL_) (REG32(ADR_TX_11GN_PLCP)) = (((_VAL_) << 23) | ((REG32(ADR_TX_11GN_PLCP)) & 0xff7fffff))
+#define SET_RG_SMB_DEF(_VAL_) (REG32(ADR_TX_11GN_PLCP)) = (((_VAL_) << 24) | ((REG32(ADR_TX_11GN_PLCP)) & 0x80ffffff))
+#define SET_RG_CONTINUOUS_DATA_11GN(_VAL_) (REG32(ADR_TX_11GN_PLCP)) = (((_VAL_) << 31) | ((REG32(ADR_TX_11GN_PLCP)) & 0x7fffffff))
+#define SET_RO_TX_CNT_R(_VAL_) (REG32(ADR_TX_11GN_PKT_GEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11GN_PKT_GEN_CNT)) & 0x00000000))
+#define SET_RO_PACKET_ERR_CNT(_VAL_) (REG32(ADR_TX_11GN_PLCP_CRC_ERR_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11GN_PLCP_CRC_ERR_CNT)) & 0xffff0000))
+#define SET_RG_POS_DES_11GN_L_EXT(_VAL_) (REG32(ADR_RX_11GN_DES_DLY)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_DES_DLY)) & 0xfffffff0))
+#define SET_RG_PRE_DES_11GN_DLY(_VAL_) (REG32(ADR_RX_11GN_DES_DLY)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_DES_DLY)) & 0xffffff0f))
+#define SET_RG_TR_LPF_KI_G_T1(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_TR_0)) & 0xfffffff0))
+#define SET_RG_TR_LPF_KP_G_T1(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_TR_0)) & 0xffffff0f))
+#define SET_RG_TR_CNT_T1(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_TR_0)) & 0xffff00ff))
+#define SET_RG_TR_LPF_KI_G_T0(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_TR_0)) & 0xfff0ffff))
+#define SET_RG_TR_LPF_KP_G_T0(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11GN_TR_0)) & 0xff0fffff))
+#define SET_RG_TR_CNT_T0(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_TR_0)) & 0x00ffffff))
+#define SET_RG_TR_LPF_KI_G_T2(_VAL_) (REG32(ADR_RX_11GN_TR_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_TR_1)) & 0xfffffff0))
+#define SET_RG_TR_LPF_KP_G_T2(_VAL_) (REG32(ADR_RX_11GN_TR_1)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_TR_1)) & 0xffffff0f))
+#define SET_RG_TR_CNT_T2(_VAL_) (REG32(ADR_RX_11GN_TR_1)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_TR_1)) & 0xffff00ff))
+#define SET_RG_TR_LPF_KI_G(_VAL_) (REG32(ADR_RX_11GN_TR_2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_TR_2)) & 0xfffffff0))
+#define SET_RG_TR_LPF_KP_G(_VAL_) (REG32(ADR_RX_11GN_TR_2)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_TR_2)) & 0xffffff0f))
+#define SET_RG_TR_LPF_RATE_G(_VAL_) (REG32(ADR_RX_11GN_TR_2)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_TR_2)) & 0xc00000ff))
+#define SET_RG_CR_LPF_KI_G(_VAL_) (REG32(ADR_RX_11GN_CCA_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_CCA_0)) & 0xfffffff8))
+#define SET_RG_SYM_BOUND_CNT(_VAL_) (REG32(ADR_RX_11GN_CCA_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_CCA_0)) & 0xffff80ff))
+#define SET_RG_XSCOR32_RATIO(_VAL_) (REG32(ADR_RX_11GN_CCA_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_0)) & 0xff80ffff))
+#define SET_RG_ATCOR64_CNT_LMT(_VAL_) (REG32(ADR_RX_11GN_CCA_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_0)) & 0x80ffffff))
+#define SET_RG_ATCOR16_CNT_LMT2(_VAL_) (REG32(ADR_RX_11GN_CCA_1)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_CCA_1)) & 0xffff80ff))
+#define SET_RG_ATCOR16_CNT_LMT1(_VAL_) (REG32(ADR_RX_11GN_CCA_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_1)) & 0xff80ffff))
+#define SET_RG_ATCOR16_RATIO_SB(_VAL_) (REG32(ADR_RX_11GN_CCA_1)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_1)) & 0x80ffffff))
+#define SET_RG_XSCOR64_CNT_LMT2(_VAL_) (REG32(ADR_RX_11GN_CCA_2)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_2)) & 0xff80ffff))
+#define SET_RG_XSCOR64_CNT_LMT1(_VAL_) (REG32(ADR_RX_11GN_CCA_2)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_2)) & 0x80ffffff))
+#define SET_RG_RX_FFT_SCALE(_VAL_) (REG32(ADR_RX_11GN_CCA_FFT_SCALE)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0xfffffc00))
+#define SET_RG_VITERBI_AB_SWAP(_VAL_) (REG32(ADR_RX_11GN_CCA_FFT_SCALE)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0xfffeffff))
+#define SET_RG_ATCOR16_CNT_TH(_VAL_) (REG32(ADR_RX_11GN_CCA_FFT_SCALE)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0xf0ffffff))
+#define SET_RG_NORMSQUARE_LOW_SNR_7(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0xffffff00))
+#define SET_RG_NORMSQUARE_LOW_SNR_6(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0xffff00ff))
+#define SET_RG_NORMSQUARE_LOW_SNR_5(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0xff00ffff))
+#define SET_RG_NORMSQUARE_LOW_SNR_4(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0x00ffffff))
+#define SET_RG_NORMSQUARE_LOW_SNR_8(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_1)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_1)) & 0x00ffffff))
+#define SET_RG_NORMSQUARE_SNR_3(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0xffffff00))
+#define SET_RG_NORMSQUARE_SNR_2(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_2)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0xffff00ff))
+#define SET_RG_NORMSQUARE_SNR_1(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_2)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0xff00ffff))
+#define SET_RG_NORMSQUARE_SNR_0(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_2)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0x00ffffff))
+#define SET_RG_NORMSQUARE_SNR_7(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_3)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0xffffff00))
+#define SET_RG_NORMSQUARE_SNR_6(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_3)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0xffff00ff))
+#define SET_RG_NORMSQUARE_SNR_5(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_3)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0xff00ffff))
+#define SET_RG_NORMSQUARE_SNR_4(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_3)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0x00ffffff))
+#define SET_RG_NORMSQUARE_SNR_8(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_4)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_4)) & 0x00ffffff))
+#define SET_RG_SNR_TH_64QAM(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_5)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_5)) & 0xffffff80))
+#define SET_RG_SNR_TH_16QAM(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_5)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_5)) & 0xffff80ff))
+#define SET_RG_ATCOR16_CNT_PLUS_LMT2(_VAL_) (REG32(ADR_RX_11GN_SYM_BOUND_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0xffffff80))
+#define SET_RG_ATCOR16_CNT_PLUS_LMT1(_VAL_) (REG32(ADR_RX_11GN_SYM_BOUND_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0xffff80ff))
+#define SET_RG_SYM_BOUND_METHOD(_VAL_) (REG32(ADR_RX_11GN_SYM_BOUND_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0xfffcffff))
+#define SET_RG_PWRON_DLY_TH_11GN(_VAL_) (REG32(ADR_RX_11GN_SYM_BOUND_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SYM_BOUND_1)) & 0xffffff00))
+#define SET_RG_SB_START_CNT(_VAL_) (REG32(ADR_RX_11GN_SYM_BOUND_1)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SYM_BOUND_1)) & 0xffff80ff))
+#define SET_RG_POW16_CNT_TH(_VAL_) (REG32(ADR_RX_11GN_CCA_PWR)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_CCA_PWR)) & 0xffffff0f))
+#define SET_RG_POW16_SHORT_CNT_LMT(_VAL_) (REG32(ADR_RX_11GN_CCA_PWR)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_CCA_PWR)) & 0xfffff8ff))
+#define SET_RG_POW16_TH_L(_VAL_) (REG32(ADR_RX_11GN_CCA_PWR)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_PWR)) & 0x80ffffff))
+#define SET_RG_XSCOR16_SHORT_CNT_LMT(_VAL_) (REG32(ADR_RX_11GN_CCA_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_CCA_CNT)) & 0xfffffff8))
+#define SET_RG_XSCOR16_RATIO(_VAL_) (REG32(ADR_RX_11GN_CCA_CNT)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_CCA_CNT)) & 0xffff80ff))
+#define SET_RG_ATCOR16_SHORT_CNT_LMT(_VAL_) (REG32(ADR_RX_11GN_CCA_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_CNT)) & 0xfff8ffff))
+#define SET_RG_ATCOR16_RATIO_CCD(_VAL_) (REG32(ADR_RX_11GN_CCA_CNT)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_CNT)) & 0x80ffffff))
+#define SET_RG_ATCOR64_ACC_LMT(_VAL_) (REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) & 0xffffff80))
+#define SET_RG_ATCOR16_SHORT_CNT_LMT2(_VAL_) (REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) & 0xfff8ffff))
+#define SET_RG_VITERBI_TB_BITS(_VAL_) (REG32(ADR_RX_11GN_VTB_TB)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_VTB_TB)) & 0x00ffffff))
+#define SET_RG_CR_CNT_UPDATE(_VAL_) (REG32(ADR_RX_11GN_ERR_UPDATE)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_ERR_UPDATE)) & 0xffffff00))
+#define SET_RG_TR_CNT_UPDATE(_VAL_) (REG32(ADR_RX_11GN_ERR_UPDATE)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_ERR_UPDATE)) & 0xff00ffff))
+#define SET_RG_BYPASS_CPE_MA(_VAL_) (REG32(ADR_RX_11GN_SHORT_GI)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_SHORT_GI)) & 0xffffffef))
+#define SET_RG_PILOT_BNDRY_SHIFT(_VAL_) (REG32(ADR_RX_11GN_SHORT_GI)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SHORT_GI)) & 0xfffff8ff))
+#define SET_RG_EQ_SHORT_GI_SHIFT(_VAL_) (REG32(ADR_RX_11GN_SHORT_GI)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11GN_SHORT_GI)) & 0xffff8fff))
+#define SET_RG_FFT_WDW_SHORT_SHIFT(_VAL_) (REG32(ADR_RX_11GN_SHORT_GI)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SHORT_GI)) & 0xfff8ffff))
+#define SET_RG_CHSMTH_COEF(_VAL_) (REG32(ADR_RX_11GN_CHANNEL_UPDATE)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0xfffcffff))
+#define SET_RG_CHSMTH_EN(_VAL_) (REG32(ADR_RX_11GN_CHANNEL_UPDATE)) = (((_VAL_) << 18) | ((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0xfffbffff))
+#define SET_RG_CHEST_DD_FACTOR(_VAL_) (REG32(ADR_RX_11GN_CHANNEL_UPDATE)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0xf8ffffff))
+#define SET_RG_CH_UPDATE(_VAL_) (REG32(ADR_RX_11GN_CHANNEL_UPDATE)) = (((_VAL_) << 31) | ((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0x7fffffff))
+#define SET_RG_FMT_DET_MM_TH(_VAL_) (REG32(ADR_RX_11GN_PKT_FORMAT_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0xffffff00))
+#define SET_RG_FMT_DET_GF_TH(_VAL_) (REG32(ADR_RX_11GN_PKT_FORMAT_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0xffff00ff))
+#define SET_RG_DO_NOT_CHECK_L_RATE(_VAL_) (REG32(ADR_RX_11GN_PKT_FORMAT_0)) = (((_VAL_) << 25) | ((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0xfdffffff))
+#define SET_RG_FMT_DET_LENGTH_TH(_VAL_) (REG32(ADR_RX_11GN_PKT_FORMAT_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_PKT_FORMAT_1)) & 0xffff0000))
+#define SET_RG_L_LENGTH_MAX(_VAL_) (REG32(ADR_RX_11GN_PKT_FORMAT_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_PKT_FORMAT_1)) & 0x0000ffff))
+#define SET_RG_TX_TIME_EXT(_VAL_) (REG32(ADR_RX_11GN_TX_TIME)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_TX_TIME)) & 0xffffff00))
+#define SET_RG_MAC_DES_SPACE(_VAL_) (REG32(ADR_RX_11GN_TX_TIME)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11GN_TX_TIME)) & 0xff0fffff))
+#define SET_RG_TR_LPF_STBC_GF_KI_G(_VAL_) (REG32(ADR_RX_11GN_STBC_TR_KP_KI)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0xfffffff0))
+#define SET_RG_TR_LPF_STBC_GF_KP_G(_VAL_) (REG32(ADR_RX_11GN_STBC_TR_KP_KI)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0xffffff0f))
+#define SET_RG_TR_LPF_STBC_MF_KI_G(_VAL_) (REG32(ADR_RX_11GN_STBC_TR_KP_KI)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0xfffff0ff))
+#define SET_RG_TR_LPF_STBC_MF_KP_G(_VAL_) (REG32(ADR_RX_11GN_STBC_TR_KP_KI)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0xffff0fff))
+#define SET_RG_MODE_REG_IN_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xfffe0000))
+#define SET_RG_PARALLEL_DR_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xffefffff))
+#define SET_RG_MBRUN_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xfeffffff))
+#define SET_RG_SHIFT_DR_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 28) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xefffffff))
+#define SET_RG_MODE_REG_SI_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 29) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xdfffffff))
+#define SET_RG_SIMULATION_MODE_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 30) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xbfffffff))
+#define SET_RG_DBIST_MODE_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 31) | ((REG32(ADR_RX_11GN_BIST_0)) & 0x7fffffff))
+#define SET_RG_MODE_REG_IN_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xffff0000))
+#define SET_RG_PARALLEL_DR_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xffefffff))
+#define SET_RG_MBRUN_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xfeffffff))
+#define SET_RG_SHIFT_DR_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 28) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xefffffff))
+#define SET_RG_MODE_REG_SI_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 29) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xdfffffff))
+#define SET_RG_SIMULATION_MODE_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 30) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xbfffffff))
+#define SET_RG_DBIST_MODE_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 31) | ((REG32(ADR_RX_11GN_BIST_1)) & 0x7fffffff))
+#define SET_RO_MODE_REG_OUT_80(_VAL_) (REG32(ADR_RX_11GN_BIST_2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_2)) & 0xfffe0000))
+#define SET_RO_MODE_REG_SO_80(_VAL_) (REG32(ADR_RX_11GN_BIST_2)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_BIST_2)) & 0xfeffffff))
+#define SET_RO_MONITOR_BUS_80(_VAL_) (REG32(ADR_RX_11GN_BIST_3)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_3)) & 0xffc00000))
+#define SET_RO_MODE_REG_OUT_64(_VAL_) (REG32(ADR_RX_11GN_BIST_4)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_4)) & 0xffff0000))
+#define SET_RO_MODE_REG_SO_64(_VAL_) (REG32(ADR_RX_11GN_BIST_4)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_BIST_4)) & 0xfeffffff))
+#define SET_RO_MONITOR_BUS_64(_VAL_) (REG32(ADR_RX_11GN_BIST_5)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_5)) & 0xfff80000))
+#define SET_RO_SPECTRUM_DATA(_VAL_) (REG32(ADR_RX_11GN_SPECTRUM_ANALYZER)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SPECTRUM_ANALYZER)) & 0x00000000))
+#define SET_GN_SNR(_VAL_) (REG32(ADR_RX_11GN_READ_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_READ_0)) & 0xffffff80))
+#define SET_GN_NOISE_PWR(_VAL_) (REG32(ADR_RX_11GN_READ_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_READ_0)) & 0xffff80ff))
+#define SET_GN_RCPI(_VAL_) (REG32(ADR_RX_11GN_READ_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_READ_0)) & 0xff80ffff))
+#define SET_GN_SIGNAL_PWR(_VAL_) (REG32(ADR_RX_11GN_READ_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_READ_0)) & 0x80ffffff))
+#define SET_RO_FREQ_OS_LTS(_VAL_) (REG32(ADR_RX_11GN_FREQ_OFFSET)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_FREQ_OFFSET)) & 0xffff8000))
+#define SET_CSTATE(_VAL_) (REG32(ADR_RX_11GN_FREQ_OFFSET)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_FREQ_OFFSET)) & 0xfff0ffff))
+#define SET_SIGNAL_FIELD0(_VAL_) (REG32(ADR_RX_11GN_SIGNAL_FIELD_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SIGNAL_FIELD_0)) & 0xff000000))
+#define SET_SIGNAL_FIELD1(_VAL_) (REG32(ADR_RX_11GN_SIGNAL_FIELD_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SIGNAL_FIELD_1)) & 0xff000000))
+#define SET_GN_PACKET_ERR_CNT(_VAL_) (REG32(ADR_RX_11GN_PKT_ERR_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_PKT_ERR_CNT)) & 0xffff0000))
+#define SET_GN_PACKET_CNT(_VAL_) (REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) & 0xffff0000))
+#define SET_GN_CCA_CNT(_VAL_) (REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) & 0x0000ffff))
+#define SET_GN_LENGTH_FIELD(_VAL_) (REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) & 0xffff0000))
+#define SET_GN_SERVICE_FIELD(_VAL_) (REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) & 0x0000ffff))
+#define SET_RO_HT_MCS_40M(_VAL_) (REG32(ADR_RX_11GN_RATE)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_RATE)) & 0xffffff80))
+#define SET_RO_L_RATE_40M(_VAL_) (REG32(ADR_RX_11GN_RATE)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_RATE)) & 0xffffc0ff))
+#define SET_RG_DAGC_CNT_TH(_VAL_) (REG32(ADR_RX_11GN_STAT_EN)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_STAT_EN)) & 0xfffffffc))
+#define SET_RG_PACKET_STAT_EN_11GN(_VAL_) (REG32(ADR_RX_11GN_STAT_EN)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11GN_STAT_EN)) & 0xffefffff))
+#define SET_RX_PHY_11GN_SOFT_RST_N(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffffe))
+#define SET_RG_RIFS_EN(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 1) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffffd))
+#define SET_RG_STBC_EN(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 2) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffffb))
+#define SET_RG_COR_SEL(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 3) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffff7))
+#define SET_RG_INI_PHASE(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xffffffcf))
+#define SET_RG_HT_LTF_SEL_EQ(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 6) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xffffffbf))
+#define SET_RG_HT_LTF_SEL_PILOT(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 7) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xffffff7f))
+#define SET_RG_CCA_PWR_SEL(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 9) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffdff))
+#define SET_RG_CCA_XSCOR_PWR_SEL(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 10) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffbff))
+#define SET_RG_CCA_XSCOR_AVGPWR_SEL(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 11) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffff7ff))
+#define SET_RG_DEBUG_SEL(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xffff0fff))
+#define SET_RG_POST_CLK_EN(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffeffff))
+#define SET_IQCAL_RF_TX_EN(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 0) | ((REG32(ADR_RF_CONTROL_0)) & 0xfffffffe))
+#define SET_IQCAL_RF_TX_PA_EN(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 1) | ((REG32(ADR_RF_CONTROL_0)) & 0xfffffffd))
+#define SET_IQCAL_RF_TX_DAC_EN(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 2) | ((REG32(ADR_RF_CONTROL_0)) & 0xfffffffb))
+#define SET_IQCAL_RF_RX_AGC(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 3) | ((REG32(ADR_RF_CONTROL_0)) & 0xfffffff7))
+#define SET_IQCAL_RF_PGAG(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 8) | ((REG32(ADR_RF_CONTROL_0)) & 0xfffff0ff))
+#define SET_IQCAL_RF_RFG(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 12) | ((REG32(ADR_RF_CONTROL_0)) & 0xffffcfff))
+#define SET_RG_TONEGEN_FREQ(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 16) | ((REG32(ADR_RF_CONTROL_0)) & 0xff80ffff))
+#define SET_RG_TONEGEN_EN(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 23) | ((REG32(ADR_RF_CONTROL_0)) & 0xff7fffff))
+#define SET_RG_TONEGEN_INIT_PH(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 24) | ((REG32(ADR_RF_CONTROL_0)) & 0x80ffffff))
+#define SET_RG_TONEGEN2_FREQ(_VAL_) (REG32(ADR_RF_CONTROL_1)) = (((_VAL_) << 0) | ((REG32(ADR_RF_CONTROL_1)) & 0xffffff80))
+#define SET_RG_TONEGEN2_EN(_VAL_) (REG32(ADR_RF_CONTROL_1)) = (((_VAL_) << 7) | ((REG32(ADR_RF_CONTROL_1)) & 0xffffff7f))
+#define SET_RG_TONEGEN2_SCALE(_VAL_) (REG32(ADR_RF_CONTROL_1)) = (((_VAL_) << 8) | ((REG32(ADR_RF_CONTROL_1)) & 0xffff00ff))
+#define SET_RG_TXIQ_CLP_THD_I(_VAL_) (REG32(ADR_TX_IQ_CONTROL_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_IQ_CONTROL_0)) & 0xfffffc00))
+#define SET_RG_TXIQ_CLP_THD_Q(_VAL_) (REG32(ADR_TX_IQ_CONTROL_0)) = (((_VAL_) << 16) | ((REG32(ADR_TX_IQ_CONTROL_0)) & 0xfc00ffff))
+#define SET_RG_TX_I_SCALE(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xffffff00))
+#define SET_RG_TX_Q_SCALE(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 8) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xffff00ff))
+#define SET_RG_TX_IQ_SWP(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 16) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xfffeffff))
+#define SET_RG_TX_SGN_OUT(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 17) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xfffdffff))
+#define SET_RG_TXIQ_EMU_IDX(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 18) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xffc3ffff))
+#define SET_RG_TX_IQ_SRC(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 24) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xfcffffff))
+#define SET_RG_TX_I_DC(_VAL_) (REG32(ADR_TX_IQ_CONTROL_2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_IQ_CONTROL_2)) & 0xfffffc00))
+#define SET_RG_TX_Q_DC(_VAL_) (REG32(ADR_TX_IQ_CONTROL_2)) = (((_VAL_) << 16) | ((REG32(ADR_TX_IQ_CONTROL_2)) & 0xfc00ffff))
+#define SET_RG_TX_IQ_THETA(_VAL_) (REG32(ADR_TX_COMPENSATION_CONTROL)) = (((_VAL_) << 0) | ((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0xffffffe0))
+#define SET_RG_TX_IQ_ALPHA(_VAL_) (REG32(ADR_TX_COMPENSATION_CONTROL)) = (((_VAL_) << 8) | ((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0xffffe0ff))
+#define SET_RG_TXIQ_NOSHRINK(_VAL_) (REG32(ADR_TX_COMPENSATION_CONTROL)) = (((_VAL_) << 13) | ((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0xffffdfff))
+#define SET_RG_TX_I_OFFSET(_VAL_) (REG32(ADR_TX_COMPENSATION_CONTROL)) = (((_VAL_) << 16) | ((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0xff00ffff))
+#define SET_RG_TX_Q_OFFSET(_VAL_) (REG32(ADR_TX_COMPENSATION_CONTROL)) = (((_VAL_) << 24) | ((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0x00ffffff))
+#define SET_RG_RX_IQ_THETA(_VAL_) (REG32(ADR_RX_COMPENSATION_CONTROL)) = (((_VAL_) << 0) | ((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0xffffffe0))
+#define SET_RG_RX_IQ_ALPHA(_VAL_) (REG32(ADR_RX_COMPENSATION_CONTROL)) = (((_VAL_) << 8) | ((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0xffffe0ff))
+#define SET_RG_RXIQ_NOSHRINK(_VAL_) (REG32(ADR_RX_COMPENSATION_CONTROL)) = (((_VAL_) << 13) | ((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0xffffdfff))
+#define SET_RG_MA_DPTH(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfffffff0))
+#define SET_RG_INTG_PH(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 4) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfffffc0f))
+#define SET_RG_INTG_PRD(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 10) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xffffe3ff))
+#define SET_RG_INTG_MU(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 13) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xffff9fff))
+#define SET_RG_IQCAL_SPRM_SELQ(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfffeffff))
+#define SET_RG_IQCAL_SPRM_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 17) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfffdffff))
+#define SET_RG_IQCAL_SPRM_FREQ(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 18) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xff03ffff))
+#define SET_RG_IQCAL_IQCOL_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfeffffff))
+#define SET_RG_IQCAL_ALPHA_ESTM_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 25) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfdffffff))
+#define SET_RG_IQCAL_DC_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 26) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfbffffff))
+#define SET_RG_PHEST_STBY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 27) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xf7ffffff))
+#define SET_RG_PHEST_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 28) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xefffffff))
+#define SET_RG_GP_DIV_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 29) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xdfffffff))
+#define SET_RG_DPD_GAIN_EST_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 30) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xbfffffff))
+#define SET_RG_IQCAL_MULT_OP0(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) & 0xfffffc00))
+#define SET_RG_IQCAL_MULT_OP1(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) & 0xfc00ffff))
+#define SET_RO_IQCAL_O(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xfff00000))
+#define SET_RO_IQCAL_SPRM_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 20) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xffefffff))
+#define SET_RO_IQCAL_IQCOL_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 21) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xffdfffff))
+#define SET_RO_IQCAL_ALPHA_ESTM_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 22) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xffbfffff))
+#define SET_RO_IQCAL_DC_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 23) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xff7fffff))
+#define SET_RO_IQCAL_MULT_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 24) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xfeffffff))
+#define SET_RO_FFT_ENRG_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 25) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xfdffffff))
+#define SET_RO_PHEST_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 26) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xfbffffff))
+#define SET_RO_GP_DIV_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 27) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xf7ffffff))
+#define SET_RO_GAIN_EST_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 28) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xefffffff))
+#define SET_RO_AMP_O(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_3)) = (((_VAL_) << 0) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_3)) & 0xfffffe00))
+#define SET_RG_RX_I_SCALE(_VAL_) (REG32(ADR_RF_IQ_CONTROL_0)) = (((_VAL_) << 0) | ((REG32(ADR_RF_IQ_CONTROL_0)) & 0xffffff00))
+#define SET_RG_RX_Q_SCALE(_VAL_) (REG32(ADR_RF_IQ_CONTROL_0)) = (((_VAL_) << 8) | ((REG32(ADR_RF_IQ_CONTROL_0)) & 0xffff00ff))
+#define SET_RG_RX_I_OFFSET(_VAL_) (REG32(ADR_RF_IQ_CONTROL_0)) = (((_VAL_) << 16) | ((REG32(ADR_RF_IQ_CONTROL_0)) & 0xff00ffff))
+#define SET_RG_RX_Q_OFFSET(_VAL_) (REG32(ADR_RF_IQ_CONTROL_0)) = (((_VAL_) << 24) | ((REG32(ADR_RF_IQ_CONTROL_0)) & 0x00ffffff))
+#define SET_RG_RX_IQ_SWP(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 0) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xfffffffe))
+#define SET_RG_RX_SGN_IN(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 1) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xfffffffd))
+#define SET_RG_RX_IQ_SRC(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 2) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xfffffff3))
+#define SET_RG_ACI_GAIN(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 4) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xfffff00f))
+#define SET_RG_FFT_EN(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 12) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xffffefff))
+#define SET_RG_FFT_MOD(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 13) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xffffdfff))
+#define SET_RG_FFT_SCALE(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 14) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xff003fff))
+#define SET_RG_FFT_ENRG_FREQ(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 24) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xc0ffffff))
+#define SET_RG_FPGA_80M_PH_UP(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 30) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xbfffffff))
+#define SET_RG_FPGA_80M_PH_STP(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 31) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0x7fffffff))
+#define SET_RG_ADC2LA_SEL(_VAL_) (REG32(ADR_RF_IQ_CONTROL_2)) = (((_VAL_) << 0) | ((REG32(ADR_RF_IQ_CONTROL_2)) & 0xfffffffe))
+#define SET_RG_ADC2LA_CLKPH(_VAL_) (REG32(ADR_RF_IQ_CONTROL_2)) = (((_VAL_) << 1) | ((REG32(ADR_RF_IQ_CONTROL_2)) & 0xfffffffd))
+#define SET_RG_RXIQ_EMU_IDX(_VAL_) (REG32(ADR_RF_IQ_CONTROL_3)) = (((_VAL_) << 0) | ((REG32(ADR_RF_IQ_CONTROL_3)) & 0xfffffff0))
+#define SET_RG_IQCAL_BP_ACI(_VAL_) (REG32(ADR_RF_IQ_CONTROL_3)) = (((_VAL_) << 4) | ((REG32(ADR_RF_IQ_CONTROL_3)) & 0xffffffef))
+#define SET_RG_DPD_AM_EN(_VAL_) (REG32(ADR_DPD_CONTROL)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_CONTROL)) & 0xfffffffe))
+#define SET_RG_DPD_PM_EN(_VAL_) (REG32(ADR_DPD_CONTROL)) = (((_VAL_) << 1) | ((REG32(ADR_DPD_CONTROL)) & 0xfffffffd))
+#define SET_RG_DPD_PM_AMSEL(_VAL_) (REG32(ADR_DPD_CONTROL)) = (((_VAL_) << 2) | ((REG32(ADR_DPD_CONTROL)) & 0xfffffffb))
+#define SET_RG_DPD_020_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_0)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_0)) & 0xfffffc00))
+#define SET_RG_DPD_040_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_0)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_0)) & 0xfc00ffff))
+#define SET_RG_DPD_060_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_1)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_1)) & 0xfffffc00))
+#define SET_RG_DPD_080_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_1)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_1)) & 0xfc00ffff))
+#define SET_RG_DPD_0A0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_2)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_2)) & 0xfffffc00))
+#define SET_RG_DPD_0C0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_2)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_2)) & 0xfc00ffff))
+#define SET_RG_DPD_0D0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_3)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_3)) & 0xfffffc00))
+#define SET_RG_DPD_0E0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_3)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_3)) & 0xfc00ffff))
+#define SET_RG_DPD_0F0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_4)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_4)) & 0xfffffc00))
+#define SET_RG_DPD_100_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_4)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_4)) & 0xfc00ffff))
+#define SET_RG_DPD_110_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_5)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_5)) & 0xfffffc00))
+#define SET_RG_DPD_120_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_5)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_5)) & 0xfc00ffff))
+#define SET_RG_DPD_130_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_6)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_6)) & 0xfffffc00))
+#define SET_RG_DPD_140_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_6)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_6)) & 0xfc00ffff))
+#define SET_RG_DPD_150_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_7)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_7)) & 0xfffffc00))
+#define SET_RG_DPD_160_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_7)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_7)) & 0xfc00ffff))
+#define SET_RG_DPD_170_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_8)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_8)) & 0xfffffc00))
+#define SET_RG_DPD_180_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_8)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_8)) & 0xfc00ffff))
+#define SET_RG_DPD_190_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_9)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_9)) & 0xfffffc00))
+#define SET_RG_DPD_1A0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_9)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_9)) & 0xfc00ffff))
+#define SET_RG_DPD_1B0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_A)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_A)) & 0xfffffc00))
+#define SET_RG_DPD_1C0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_A)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_A)) & 0xfc00ffff))
+#define SET_RG_DPD_1D0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_B)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_B)) & 0xfffffc00))
+#define SET_RG_DPD_1E0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_B)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_B)) & 0xfc00ffff))
+#define SET_RG_DPD_1F0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_C)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_C)) & 0xfffffc00))
+#define SET_RG_DPD_200_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_C)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_C)) & 0xfc00ffff))
+#define SET_RG_DPD_020_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_0)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_0)) & 0xffffe000))
+#define SET_RG_DPD_040_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_0)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_0)) & 0xe000ffff))
+#define SET_RG_DPD_060_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_1)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_1)) & 0xffffe000))
+#define SET_RG_DPD_080_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_1)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_1)) & 0xe000ffff))
+#define SET_RG_DPD_0A0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_2)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_2)) & 0xffffe000))
+#define SET_RG_DPD_0C0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_2)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_2)) & 0xe000ffff))
+#define SET_RG_DPD_0D0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_3)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_3)) & 0xffffe000))
+#define SET_RG_DPD_0E0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_3)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_3)) & 0xe000ffff))
+#define SET_RG_DPD_0F0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_4)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_4)) & 0xffffe000))
+#define SET_RG_DPD_100_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_4)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_4)) & 0xe000ffff))
+#define SET_RG_DPD_110_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_5)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_5)) & 0xffffe000))
+#define SET_RG_DPD_120_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_5)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_5)) & 0xe000ffff))
+#define SET_RG_DPD_130_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_6)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_6)) & 0xffffe000))
+#define SET_RG_DPD_140_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_6)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_6)) & 0xe000ffff))
+#define SET_RG_DPD_150_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_7)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_7)) & 0xffffe000))
+#define SET_RG_DPD_160_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_7)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_7)) & 0xe000ffff))
+#define SET_RG_DPD_170_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_8)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_8)) & 0xffffe000))
+#define SET_RG_DPD_180_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_8)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_8)) & 0xe000ffff))
+#define SET_RG_DPD_190_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_9)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_9)) & 0xffffe000))
+#define SET_RG_DPD_1A0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_9)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_9)) & 0xe000ffff))
+#define SET_RG_DPD_1B0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_A)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_A)) & 0xffffe000))
+#define SET_RG_DPD_1C0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_A)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_A)) & 0xe000ffff))
+#define SET_RG_DPD_1D0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_B)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_B)) & 0xffffe000))
+#define SET_RG_DPD_1E0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_B)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_B)) & 0xe000ffff))
+#define SET_RG_DPD_1F0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_C)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_C)) & 0xffffe000))
+#define SET_RG_DPD_200_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_C)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_C)) & 0xe000ffff))
+#define SET_RG_DPD_GAIN_EST_Y0(_VAL_) (REG32(ADR_DPD_GAIN_ESTIMATION_0)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_ESTIMATION_0)) & 0xfffffe00))
+#define SET_RG_DPD_GAIN_EST_Y1(_VAL_) (REG32(ADR_DPD_GAIN_ESTIMATION_0)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_ESTIMATION_0)) & 0xfe00ffff))
+#define SET_RG_DPD_LOOP_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_ESTIMATION_1)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_ESTIMATION_1)) & 0xfffffc00))
+#define SET_RG_DPD_GAIN_EST_X0(_VAL_) (REG32(ADR_DPD_GAIN_ESTIMATION_2)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_ESTIMATION_2)) & 0xfffffe00))
+#define SET_RO_DPD_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_ESTIMATION_2)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_ESTIMATION_2)) & 0xfc00ffff))
+#define SET_TX_SCALE_11B(_VAL_) (REG32(ADR_TX_GAIN_FACTOR)) = (((_VAL_) << 0) | ((REG32(ADR_TX_GAIN_FACTOR)) & 0xffffff00))
+#define SET_TX_SCALE_11B_P0D5(_VAL_) (REG32(ADR_TX_GAIN_FACTOR)) = (((_VAL_) << 8) | ((REG32(ADR_TX_GAIN_FACTOR)) & 0xffff00ff))
+#define SET_TX_SCALE_11G(_VAL_) (REG32(ADR_TX_GAIN_FACTOR)) = (((_VAL_) << 16) | ((REG32(ADR_TX_GAIN_FACTOR)) & 0xff00ffff))
+#define SET_TX_SCALE_11G_P0D5(_VAL_) (REG32(ADR_TX_GAIN_FACTOR)) = (((_VAL_) << 24) | ((REG32(ADR_TX_GAIN_FACTOR)) & 0x00ffffff))
+#define SET_RG_EN_MANUAL(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffe))
+#define SET_RG_TX_EN(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffd))
+#define SET_RG_TX_PA_EN(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffb))
+#define SET_RG_TX_DAC_EN(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffffff7))
+#define SET_RG_RX_AGC(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffffffef))
+#define SET_RG_RX_GAIN_MANUAL(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffffffdf))
+#define SET_RG_RFG(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffffff3f))
+#define SET_RG_PGAG(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffff0ff))
+#define SET_RG_MODE(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffffcfff))
+#define SET_RG_EN_TX_TRSW(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffffbfff))
+#define SET_RG_EN_SX(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffff7fff))
+#define SET_RG_EN_RX_LNA(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffeffff))
+#define SET_RG_EN_RX_MIXER(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 17) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffdffff))
+#define SET_RG_EN_RX_DIV2(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffbffff))
+#define SET_RG_EN_RX_LOBUF(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 19) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfff7ffff))
+#define SET_RG_EN_RX_TZ(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffefffff))
+#define SET_RG_EN_RX_FILTER(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffdfffff))
+#define SET_RG_EN_RX_HPF(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffbfffff))
+#define SET_RG_EN_RX_RSSI(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 23) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xff7fffff))
+#define SET_RG_EN_ADC(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfeffffff))
+#define SET_RG_EN_TX_MOD(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 25) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfdffffff))
+#define SET_RG_EN_TX_DIV2(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 26) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfbffffff))
+#define SET_RG_EN_TX_DIV2_BUF(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xf7ffffff))
+#define SET_RG_EN_TX_LOBF(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 28) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xefffffff))
+#define SET_RG_EN_RX_LOBF(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 29) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xdfffffff))
+#define SET_RG_SEL_DPLL_CLK(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 30) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xbfffffff))
+#define SET_RG_EN_CLK_960MBY13_UART(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 31) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x7fffffff))
+#define SET_RG_EN_TX_DPD(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffffe))
+#define SET_RG_EN_TX_TSSI(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffffd))
+#define SET_RG_EN_RX_IQCAL(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffffb))
+#define SET_RG_EN_TX_DAC_CAL(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffff7))
+#define SET_RG_EN_TX_SELF_MIXER(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffffef))
+#define SET_RG_EN_TX_DAC_OUT(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffffdf))
+#define SET_RG_EN_LDO_RX_FE(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffffbf))
+#define SET_RG_EN_LDO_ABB(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 7) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffff7f))
+#define SET_RG_EN_LDO_AFE(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffeff))
+#define SET_RG_EN_SX_CHPLDO(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffdff))
+#define SET_RG_EN_SX_LOBFLDO(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffbff))
+#define SET_RG_EN_IREF_RX(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffff7ff))
+#define SET_RG_EN_TX_DAC_VOUT(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffdfff))
+#define SET_RG_EN_SX_LCK_BIN(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffbfff))
+#define SET_RG_RTC_CAL_MODE(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffeffff))
+#define SET_RG_EN_IQPAD_IOSW(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 17) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffdffff))
+#define SET_RG_EN_TESTPAD_IOSW(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffbffff))
+#define SET_RG_EN_TRXBF_BYPASS(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 19) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfff7ffff))
+#define SET_RG_LDO_LEVEL_RX_FE(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_LDO_REGISTER)) & 0xfffffff8))
+#define SET_RG_LDO_LEVEL_ABB(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_LDO_REGISTER)) & 0xffffffc7))
+#define SET_RG_LDO_LEVEL_AFE(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_LDO_REGISTER)) & 0xfffffe3f))
+#define SET_RG_SX_LDO_CHP_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_LDO_REGISTER)) & 0xfffff1ff))
+#define SET_RG_SX_LDO_LOBF_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_LDO_REGISTER)) & 0xffff8fff))
+#define SET_RG_SX_LDO_XOSC_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_LDO_REGISTER)) & 0xfffc7fff))
+#define SET_RG_DP_LDO_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_LDO_REGISTER)) & 0xffe3ffff))
+#define SET_RG_SX_LDO_VCO_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_LDO_REGISTER)) & 0xff1fffff))
+#define SET_RG_TX_LDO_TX_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_LDO_REGISTER)) & 0xf8ffffff))
+#define SET_RG_EN_RX_PADSW(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffffe))
+#define SET_RG_EN_RX_TESTNODE(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 1) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffffd))
+#define SET_RG_RX_ABBCFIX(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 2) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffffb))
+#define SET_RG_RX_ABBCTUNE(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 3) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffe07))
+#define SET_RG_RX_ABBOUT_TRI_STATE(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 9) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffdff))
+#define SET_RG_RX_ABB_N_MODE(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 10) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffbff))
+#define SET_RG_RX_EN_LOOPA(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 11) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffff7ff))
+#define SET_RG_RX_FILTERI1ST(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 12) | ((REG32(ADR_ABB_REGISTER_1)) & 0xffffcfff))
+#define SET_RG_RX_FILTERI2ND(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 14) | ((REG32(ADR_ABB_REGISTER_1)) & 0xffff3fff))
+#define SET_RG_RX_FILTERI3RD(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 16) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffcffff))
+#define SET_RG_RX_FILTERI_COURSE(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 18) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfff3ffff))
+#define SET_RG_RX_FILTERVCM(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 20) | ((REG32(ADR_ABB_REGISTER_1)) & 0xffcfffff))
+#define SET_RG_RX_HPF3M(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 22) | ((REG32(ADR_ABB_REGISTER_1)) & 0xffbfffff))
+#define SET_RG_RX_HPF300K(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 23) | ((REG32(ADR_ABB_REGISTER_1)) & 0xff7fffff))
+#define SET_RG_RX_HPFI(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 24) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfcffffff))
+#define SET_RG_RX_HPF_FINALCORNER(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 26) | ((REG32(ADR_ABB_REGISTER_1)) & 0xf3ffffff))
+#define SET_RG_RX_HPF_SETTLE1_C(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 28) | ((REG32(ADR_ABB_REGISTER_1)) & 0xcfffffff))
+#define SET_RG_RX_HPF_SETTLE1_R(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfffffffc))
+#define SET_RG_RX_HPF_SETTLE2_C(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 2) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfffffff3))
+#define SET_RG_RX_HPF_SETTLE2_R(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 4) | ((REG32(ADR_ABB_REGISTER_2)) & 0xffffffcf))
+#define SET_RG_RX_HPF_VCMCON2(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 6) | ((REG32(ADR_ABB_REGISTER_2)) & 0xffffff3f))
+#define SET_RG_RX_HPF_VCMCON(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 8) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfffffcff))
+#define SET_RG_RX_OUTVCM(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 10) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfffff3ff))
+#define SET_RG_RX_TZI(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 12) | ((REG32(ADR_ABB_REGISTER_2)) & 0xffffcfff))
+#define SET_RG_RX_TZ_OUT_TRISTATE(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 14) | ((REG32(ADR_ABB_REGISTER_2)) & 0xffffbfff))
+#define SET_RG_RX_TZ_VCM(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 15) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfffe7fff))
+#define SET_RG_EN_RX_RSSI_TESTNODE(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 17) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfff1ffff))
+#define SET_RG_RX_ADCRSSI_CLKSEL(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 20) | ((REG32(ADR_ABB_REGISTER_2)) & 0xffefffff))
+#define SET_RG_RX_ADCRSSI_VCM(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 21) | ((REG32(ADR_ABB_REGISTER_2)) & 0xff9fffff))
+#define SET_RG_RX_REC_LPFCORNER(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 23) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfe7fffff))
+#define SET_RG_RSSI_CLOCK_GATING(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 25) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfdffffff))
+#define SET_RG_TXPGA_CAPSW(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_TX_FE_REGISTER)) & 0xfffffffc))
+#define SET_RG_TXPGA_MAIN(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_TX_FE_REGISTER)) & 0xffffff03))
+#define SET_RG_TXPGA_STEER(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_TX_FE_REGISTER)) & 0xffffc0ff))
+#define SET_RG_TXMOD_GMCELL(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_TX_FE_REGISTER)) & 0xffff3fff))
+#define SET_RG_TXLPF_GMCELL(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_TX_FE_REGISTER)) & 0xfffcffff))
+#define SET_RG_PACELL_EN(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_TX_FE_REGISTER)) & 0xffe3ffff))
+#define SET_RG_PABIAS_CTRL(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_TX_FE_REGISTER)) & 0xfe1fffff))
+#define SET_RG_TX_DIV_VSET(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 26) | ((REG32(ADR_TX_FE_REGISTER)) & 0xf3ffffff))
+#define SET_RG_TX_LOBUF_VSET(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 28) | ((REG32(ADR_TX_FE_REGISTER)) & 0xcfffffff))
+#define SET_RG_RX_SQDC(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xfffffff8))
+#define SET_RG_RX_DIV2_CORE(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 3) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xffffffe7))
+#define SET_RG_RX_LOBUF(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 5) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xffffff9f))
+#define SET_RG_TX_DPDGM_BIAS(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 7) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xfffff87f))
+#define SET_RG_TX_DPD_DIV(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 11) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xffff87ff))
+#define SET_RG_TX_TSSI_BIAS(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 15) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xfffc7fff))
+#define SET_RG_TX_TSSI_DIV(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 18) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xffe3ffff))
+#define SET_RG_TX_TSSI_TESTMODE(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 21) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xffdfffff))
+#define SET_RG_TX_TSSI_TEST(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 22) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xff3fffff))
+#define SET_RG_PACASCODE_CTRL(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 24) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xf8ffffff))
+#define SET_RG_RX_HG_LNA_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfffffffc))
+#define SET_RG_RX_HG_LNAHGN_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 2) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffffffc3))
+#define SET_RG_RX_HG_LNAHGP_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 6) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfffffc3f))
+#define SET_RG_RX_HG_LNALG_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 10) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffffc3ff))
+#define SET_RG_RX_HG_TZ_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 14) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffff3fff))
+#define SET_RG_RX_HG_TZ_CAP(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfff8ffff))
+#define SET_RG_RX_MG_LNA_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfffffffc))
+#define SET_RG_RX_MG_LNAHGN_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 2) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffffffc3))
+#define SET_RG_RX_MG_LNAHGP_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 6) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfffffc3f))
+#define SET_RG_RX_MG_LNALG_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 10) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffffc3ff))
+#define SET_RG_RX_MG_TZ_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 14) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffff3fff))
+#define SET_RG_RX_MG_TZ_CAP(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 16) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfff8ffff))
+#define SET_RG_RX_LG_LNA_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfffffffc))
+#define SET_RG_RX_LG_LNAHGN_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 2) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffffffc3))
+#define SET_RG_RX_LG_LNAHGP_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 6) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfffffc3f))
+#define SET_RG_RX_LG_LNALG_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 10) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffffc3ff))
+#define SET_RG_RX_LG_TZ_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 14) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffff3fff))
+#define SET_RG_RX_LG_TZ_CAP(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 16) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfff8ffff))
+#define SET_RG_RX_ULG_LNA_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfffffffc))
+#define SET_RG_RX_ULG_LNAHGN_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 2) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffffffc3))
+#define SET_RG_RX_ULG_LNAHGP_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 6) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfffffc3f))
+#define SET_RG_RX_ULG_LNALG_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 10) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffffc3ff))
+#define SET_RG_RX_ULG_TZ_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 14) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffff3fff))
+#define SET_RG_RX_ULG_TZ_CAP(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 16) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfff8ffff))
+#define SET_RG_HPF1_FAST_SET_X(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xfffffffe))
+#define SET_RG_HPF1_FAST_SET_Y(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xfffffffd))
+#define SET_RG_HPF1_FAST_SET_Z(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xfffffffb))
+#define SET_RG_HPF_T1A(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffffffe7))
+#define SET_RG_HPF_T1B(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffffff9f))
+#define SET_RG_HPF_T1C(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 7) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xfffffe7f))
+#define SET_RG_RX_LNA_TRI_SEL(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xfffff9ff))
+#define SET_RG_RX_LNA_SETTLE(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffffe7ff))
+#define SET_RG_TXGAIN_PHYCTRL(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffffdfff))
+#define SET_RG_TX_GAIN(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffc03fff))
+#define SET_RG_TXGAIN_MANUAL(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffbfffff))
+#define SET_RG_TX_GAIN_OFFSET(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 23) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xf87fffff))
+#define SET_RG_ADC_CLKSEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffffffe))
+#define SET_RG_ADC_DIBIAS(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffffff9))
+#define SET_RG_ADC_DIVR(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffffff7))
+#define SET_RG_ADC_DVCMI(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xffffffcf))
+#define SET_RG_ADC_SAMSEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffffc3f))
+#define SET_RG_ADC_STNBY(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffffbff))
+#define SET_RG_ADC_TESTMODE(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffff7ff))
+#define SET_RG_ADC_TSEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xffff0fff))
+#define SET_RG_ADC_VRSEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffcffff))
+#define SET_RG_DICMP(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfff3ffff))
+#define SET_RG_DIOP(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xffcfffff))
+#define SET_RG_SARADC_VRSEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xff3fffff))
+#define SET_RG_EN_SAR_TEST(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfcffffff))
+#define SET_RG_SARADC_THERMAL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 26) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfbffffff))
+#define SET_RG_SARADC_TSSI(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xf7ffffff))
+#define SET_RG_CLK_SAR_SEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 28) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xcfffffff))
+#define SET_RG_EN_SARADC(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 30) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xbfffffff))
+#define SET_RG_DACI1ST(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xfffffffc))
+#define SET_RG_TX_DACLPF_ICOURSE(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xfffffff3))
+#define SET_RG_TX_DACLPF_IFINE(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffffffcf))
+#define SET_RG_TX_DACLPF_VCM(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffffff3f))
+#define SET_RG_TX_DAC_CKEDGE_SEL(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xfffffeff))
+#define SET_RG_TX_DAC_IBIAS(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xfffff9ff))
+#define SET_RG_TX_DAC_OS(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffffc7ff))
+#define SET_RG_TX_DAC_RCAL(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffff3fff))
+#define SET_RG_TX_DAC_TSEL(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xfff0ffff))
+#define SET_RG_TX_EN_VOLTAGE_IN(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffefffff))
+#define SET_RG_TXLPF_BYPASS(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffdfffff))
+#define SET_RG_TXLPF_BOOSTI(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffbfffff))
+#define SET_RG_TX_DAC_IOFFSET(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 23) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xf87fffff))
+#define SET_RG_TX_DAC_QOFFSET(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_TX_DAC_REGISTER)) & 0x87ffffff))
+#define SET_RG_EN_SX_R3(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffffffe))
+#define SET_RG_EN_SX_CH(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffffffd))
+#define SET_RG_EN_SX_CHP(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffffffb))
+#define SET_RG_EN_SX_DIVCK(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffffff7))
+#define SET_RG_EN_SX_VCOBF(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffffef))
+#define SET_RG_EN_SX_VCO(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffffdf))
+#define SET_RG_EN_SX_MOD(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffffbf))
+#define SET_RG_EN_SX_DITHER(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffffeff))
+#define SET_RG_EN_SX_VT_MON(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffff7ff))
+#define SET_RG_EN_SX_VT_MON_DG(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffefff))
+#define SET_RG_EN_SX_DIV(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffdfff))
+#define SET_RG_EN_SX_LPF(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffbfff))
+#define SET_RG_EN_DPL_MOD(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffff7fff))
+#define SET_RG_DPL_MOD_ORDER(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffcffff))
+#define SET_RG_SX_RFCTRL_F(_VAL_) (REG32(ADR_SYN_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_REGISTER_1)) & 0xff000000))
+#define SET_RG_SX_SEL_CP(_VAL_) (REG32(ADR_SYN_REGISTER_1)) = (((_VAL_) << 24) | ((REG32(ADR_SYN_REGISTER_1)) & 0xf0ffffff))
+#define SET_RG_SX_SEL_CS(_VAL_) (REG32(ADR_SYN_REGISTER_1)) = (((_VAL_) << 28) | ((REG32(ADR_SYN_REGISTER_1)) & 0x0fffffff))
+#define SET_RG_SX_RFCTRL_CH(_VAL_) (REG32(ADR_SYN_REGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_REGISTER_2)) & 0xfffff800))
+#define SET_RG_SX_SEL_C3(_VAL_) (REG32(ADR_SYN_REGISTER_2)) = (((_VAL_) << 11) | ((REG32(ADR_SYN_REGISTER_2)) & 0xffff87ff))
+#define SET_RG_SX_SEL_RS(_VAL_) (REG32(ADR_SYN_REGISTER_2)) = (((_VAL_) << 15) | ((REG32(ADR_SYN_REGISTER_2)) & 0xfff07fff))
+#define SET_RG_SX_SEL_R3(_VAL_) (REG32(ADR_SYN_REGISTER_2)) = (((_VAL_) << 20) | ((REG32(ADR_SYN_REGISTER_2)) & 0xfe0fffff))
+#define SET_RG_SX_SEL_ICHP(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_PFD_CHP)) & 0xffffffe0))
+#define SET_RG_SX_SEL_PCHP(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 5) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfffffc1f))
+#define SET_RG_SX_SEL_CHP_REGOP(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 10) | ((REG32(ADR_SYN_PFD_CHP)) & 0xffffc3ff))
+#define SET_RG_SX_SEL_CHP_UNIOP(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 14) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfffc3fff))
+#define SET_RG_SX_CHP_IOST_POL(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 18) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfffbffff))
+#define SET_RG_SX_CHP_IOST(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 19) | ((REG32(ADR_SYN_PFD_CHP)) & 0xffc7ffff))
+#define SET_RG_SX_PFDSEL(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 22) | ((REG32(ADR_SYN_PFD_CHP)) & 0xffbfffff))
+#define SET_RG_SX_PFD_SET(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 23) | ((REG32(ADR_SYN_PFD_CHP)) & 0xff7fffff))
+#define SET_RG_SX_PFD_SET1(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 24) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfeffffff))
+#define SET_RG_SX_PFD_SET2(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 25) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfdffffff))
+#define SET_RG_SX_VBNCAS_SEL(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 26) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfbffffff))
+#define SET_RG_SX_PFD_RST_H(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 27) | ((REG32(ADR_SYN_PFD_CHP)) & 0xf7ffffff))
+#define SET_RG_SX_PFD_TRUP(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 28) | ((REG32(ADR_SYN_PFD_CHP)) & 0xefffffff))
+#define SET_RG_SX_PFD_TRDN(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 29) | ((REG32(ADR_SYN_PFD_CHP)) & 0xdfffffff))
+#define SET_RG_SX_PFD_TRSEL(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 30) | ((REG32(ADR_SYN_PFD_CHP)) & 0xbfffffff))
+#define SET_RG_SX_VCOBA_R(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xfffffff8))
+#define SET_RG_SX_VCORSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 3) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xffffff07))
+#define SET_RG_SX_VCOCUSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 8) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xfffff0ff))
+#define SET_RG_SX_RXBFSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 12) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xffff0fff))
+#define SET_RG_SX_TXBFSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 16) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xfff0ffff))
+#define SET_RG_SX_VCOBFSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 20) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xff0fffff))
+#define SET_RG_SX_DIVBFSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 24) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xf0ffffff))
+#define SET_RG_SX_GNDR_SEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 28) | ((REG32(ADR_SYN_VCO_LOBF)) & 0x0fffffff))
+#define SET_RG_SX_DITHER_WEIGHT(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xfffffffc))
+#define SET_RG_SX_MOD_ORDER(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 4) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xffffffcf))
+#define SET_RG_SX_RST_H_DIV(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 9) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xfffffdff))
+#define SET_RG_SX_SDM_EDGE(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 10) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xfffffbff))
+#define SET_RG_SX_XO_GM(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 11) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xffffe7ff))
+#define SET_RG_SX_REFBYTWO(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 13) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xffffdfff))
+#define SET_RG_SX_LCKEN(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 19) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xfff7ffff))
+#define SET_RG_SX_PREVDD(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 20) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xff0fffff))
+#define SET_RG_SX_PSCONTERVDD(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 24) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xf0ffffff))
+#define SET_RG_SX_PH(_VAL_) (REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) = (((_VAL_) << 13) | ((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0xffffdfff))
+#define SET_RG_SX_PL(_VAL_) (REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) = (((_VAL_) << 14) | ((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0xffffbfff))
+#define SET_RG_XOSC_CBANK_XO(_VAL_) (REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) = (((_VAL_) << 15) | ((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0xfff87fff))
+#define SET_RG_XOSC_CBANK_XI(_VAL_) (REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) = (((_VAL_) << 19) | ((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0xff87ffff))
+#define SET_RG_SX_VT_MON_MODE(_VAL_) (REG32(ADR_SYN_LCK_VT)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_LCK_VT)) & 0xfffffffe))
+#define SET_RG_SX_VT_TH_HI(_VAL_) (REG32(ADR_SYN_LCK_VT)) = (((_VAL_) << 1) | ((REG32(ADR_SYN_LCK_VT)) & 0xfffffff9))
+#define SET_RG_SX_VT_TH_LO(_VAL_) (REG32(ADR_SYN_LCK_VT)) = (((_VAL_) << 3) | ((REG32(ADR_SYN_LCK_VT)) & 0xffffffe7))
+#define SET_RG_SX_VT_SET(_VAL_) (REG32(ADR_SYN_LCK_VT)) = (((_VAL_) << 5) | ((REG32(ADR_SYN_LCK_VT)) & 0xffffffdf))
+#define SET_RG_SX_VT_MON_TMR(_VAL_) (REG32(ADR_SYN_LCK_VT)) = (((_VAL_) << 6) | ((REG32(ADR_SYN_LCK_VT)) & 0xffff803f))
+#define SET_RG_EN_DP_VT_MON(_VAL_) (REG32(ADR_DPLL_VCO_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_DPLL_VCO_REGISTER)) & 0xfffffffe))
+#define SET_RG_DP_VT_TH_HI(_VAL_) (REG32(ADR_DPLL_VCO_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_DPLL_VCO_REGISTER)) & 0xfffffff9))
+#define SET_RG_DP_VT_TH_LO(_VAL_) (REG32(ADR_DPLL_VCO_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_DPLL_VCO_REGISTER)) & 0xffffffe7))
+#define SET_RG_DP_CK320BY2(_VAL_) (REG32(ADR_DPLL_VCO_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_DPLL_VCO_REGISTER)) & 0xffffbfff))
+#define SET_RG_DP_OD_TEST(_VAL_) (REG32(ADR_DPLL_VCO_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_DPLL_VCO_REGISTER)) & 0xffdfffff))
+#define SET_RG_DP_BBPLL_BP(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfffffffe))
+#define SET_RG_DP_BBPLL_ICP(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfffffff9))
+#define SET_RG_DP_BBPLL_IDUAL(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xffffffe7))
+#define SET_RG_DP_BBPLL_OD_TEST(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfffffe1f))
+#define SET_RG_DP_BBPLL_PD(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfffffdff))
+#define SET_RG_DP_BBPLL_TESTSEL(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xffffe3ff))
+#define SET_RG_DP_BBPLL_PFD_DLY(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xffff9fff))
+#define SET_RG_DP_RP(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfffc7fff))
+#define SET_RG_DP_RHP(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfff3ffff))
+#define SET_RG_DP_BBPLL_SDM_EDGE(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 31) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x7fffffff))
+#define SET_RG_DP_FODIV(_VAL_) (REG32(ADR_DPLL_DIVIDER_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_DPLL_DIVIDER_REGISTER)) & 0xfff80fff))
+#define SET_RG_DP_REFDIV(_VAL_) (REG32(ADR_DPLL_DIVIDER_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_DPLL_DIVIDER_REGISTER)) & 0xe03fffff))
+#define SET_RG_IDACAI_PGAG15(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0xffffffc0))
+#define SET_RG_IDACAQ_PGAG15(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0xfffff03f))
+#define SET_RG_IDACAI_PGAG14(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0xfffc0fff))
+#define SET_RG_IDACAQ_PGAG14(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0xff03ffff))
+#define SET_RG_DP_BBPLL_BS(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 24) | ((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0xc0ffffff))
+#define SET_RG_IDACAI_PGAG13(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0xffffffc0))
+#define SET_RG_IDACAQ_PGAG13(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0xfffff03f))
+#define SET_RG_IDACAI_PGAG12(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0xfffc0fff))
+#define SET_RG_IDACAQ_PGAG12(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0xff03ffff))
+#define SET_RG_IDACAI_PGAG11(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0xffffffc0))
+#define SET_RG_IDACAQ_PGAG11(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0xfffff03f))
+#define SET_RG_IDACAI_PGAG10(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0xfffc0fff))
+#define SET_RG_IDACAQ_PGAG10(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0xff03ffff))
+#define SET_RG_IDACAI_PGAG9(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0xffffffc0))
+#define SET_RG_IDACAQ_PGAG9(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0xfffff03f))
+#define SET_RG_IDACAI_PGAG8(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0xfffc0fff))
+#define SET_RG_IDACAQ_PGAG8(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0xff03ffff))
+#define SET_RG_IDACAI_PGAG7(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0xffffffc0))
+#define SET_RG_IDACAQ_PGAG7(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0xfffff03f))
+#define SET_RG_IDACAI_PGAG6(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0xfffc0fff))
+#define SET_RG_IDACAQ_PGAG6(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0xff03ffff))
+#define SET_RG_IDACAI_PGAG5(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0xffffffc0))
+#define SET_RG_IDACAQ_PGAG5(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0xfffff03f))
+#define SET_RG_IDACAI_PGAG4(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0xfffc0fff))
+#define SET_RG_IDACAQ_PGAG4(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0xff03ffff))
+#define SET_RG_IDACAI_PGAG3(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0xffffffc0))
+#define SET_RG_IDACAQ_PGAG3(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0xfffff03f))
+#define SET_RG_IDACAI_PGAG2(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0xfffc0fff))
+#define SET_RG_IDACAQ_PGAG2(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0xff03ffff))
+#define SET_RG_IDACAI_PGAG1(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0xffffffc0))
+#define SET_RG_IDACAQ_PGAG1(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0xfffff03f))
+#define SET_RG_IDACAI_PGAG0(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0xfffc0fff))
+#define SET_RG_IDACAQ_PGAG0(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0xff03ffff))
+#define SET_RG_EN_RCAL(_VAL_) (REG32(ADR_RCAL_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_RCAL_REGISTER)) & 0xfffffffe))
+#define SET_RG_RCAL_SPD(_VAL_) (REG32(ADR_RCAL_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_RCAL_REGISTER)) & 0xfffffffd))
+#define SET_RG_RCAL_TMR(_VAL_) (REG32(ADR_RCAL_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_RCAL_REGISTER)) & 0xfffffe03))
+#define SET_RG_RCAL_CODE_CWR(_VAL_) (REG32(ADR_RCAL_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_RCAL_REGISTER)) & 0xfffffdff))
+#define SET_RG_RCAL_CODE_CWD(_VAL_) (REG32(ADR_RCAL_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_RCAL_REGISTER)) & 0xffff83ff))
+#define SET_RG_SX_SUB_SEL_CWR(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 0) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xfffffffe))
+#define SET_RG_SX_SUB_SEL_CWD(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 1) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xffffff01))
+#define SET_RG_SX_LCK_BIN_OFFSET(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 15) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xfff87fff))
+#define SET_RG_SX_LCK_BIN_PRECISION(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 19) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xfff7ffff))
+#define SET_RG_SX_LOCK_EN_N(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 20) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xffefffff))
+#define SET_RG_SX_LOCK_MANUAL(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 21) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xffdfffff))
+#define SET_RG_SX_SUB_MANUAL(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 22) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xffbfffff))
+#define SET_RG_SX_SUB_SEL(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 23) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xc07fffff))
+#define SET_RG_SX_MUX_SEL_VTH_BINL(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 30) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xbfffffff))
+#define SET_RG_TRX_DUMMMY(_VAL_) (REG32(ADR_TRX_DUMMY_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_TRX_DUMMY_REGISTER)) & 0x00000000))
+#define SET_RG_SX_DUMMMY(_VAL_) (REG32(ADR_SX_DUMMY_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_SX_DUMMY_REGISTER)) & 0x00000000))
+#define SET_RCAL_RDY(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 0) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xfffffffe))
+#define SET_LCK_BIN_RDY(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 1) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xfffffffd))
+#define SET_VT_MON_RDY(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 2) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xfffffffb))
+#define SET_DA_R_CODE_LUT(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 6) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xfffff83f))
+#define SET_AD_SX_VT_MON_Q(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 11) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xffffe7ff))
+#define SET_AD_DP_VT_MON_Q(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 13) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xffff9fff))
+#define SET_RTC_CAL_RDY(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 15) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xffff7fff))
+#define SET_RG_SARADC_BIT(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 16) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xffc0ffff))
+#define SET_SAR_ADC_FSM_RDY(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 22) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xffbfffff))
+#define SET_AD_CIRCUIT_VERSION(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 23) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xf87fffff))
+#define SET_DA_R_CAL_CODE(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_2)) = (((_VAL_) << 0) | ((REG32(ADR_READ_ONLY_FLAGS_2)) & 0xffffffe0))
+#define SET_DA_SX_SUB_SEL(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_2)) = (((_VAL_) << 5) | ((REG32(ADR_READ_ONLY_FLAGS_2)) & 0xfffff01f))
+#define SET_RG_DPL_RFCTRL_CH(_VAL_) (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) = (((_VAL_) << 0) | ((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0xfffff800))
+#define SET_RG_RSSIADC_RO_BIT(_VAL_) (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) = (((_VAL_) << 11) | ((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0xffff87ff))
+#define SET_RG_RX_ADC_I_RO_BIT(_VAL_) (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) = (((_VAL_) << 15) | ((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0xff807fff))
+#define SET_RG_RX_ADC_Q_RO_BIT(_VAL_) (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) = (((_VAL_) << 23) | ((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0x807fffff))
+#define SET_RG_DPL_RFCTRL_F(_VAL_) (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_II)) = (((_VAL_) << 0) | ((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_II)) & 0xff000000))
+#define SET_RG_SX_TARGET_CNT(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_II)) = (((_VAL_) << 0) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_II)) & 0xffffe000))
+#define SET_RG_RTC_OFFSET(_VAL_) (REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) = (((_VAL_) << 0) | ((REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) & 0xffffff00))
+#define SET_RG_RTC_CAL_TARGET_COUNT(_VAL_) (REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) = (((_VAL_) << 8) | ((REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) & 0xfff000ff))
+#define SET_RG_RF_D_REG(_VAL_) (REG32(ADR_RF_D_DIGITAL_DEBUG_PORT_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_RF_D_DIGITAL_DEBUG_PORT_REGISTER)) & 0xffff0000))
+#define SET_DIRECT_MODE(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_MMU_CTRL)) & 0xfffffffe))
+#define SET_TAG_INTERLEAVE_MD(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 1) | ((REG32(ADR_MMU_CTRL)) & 0xfffffffd))
+#define SET_DIS_DEMAND(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 2) | ((REG32(ADR_MMU_CTRL)) & 0xfffffffb))
+#define SET_SAME_ID_ALLOC_MD(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 3) | ((REG32(ADR_MMU_CTRL)) & 0xfffffff7))
+#define SET_HS_ACCESS_MD(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 4) | ((REG32(ADR_MMU_CTRL)) & 0xffffffef))
+#define SET_SRAM_ACCESS_MD(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 5) | ((REG32(ADR_MMU_CTRL)) & 0xffffffdf))
+#define SET_NOHIT_RPASS_MD(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 6) | ((REG32(ADR_MMU_CTRL)) & 0xffffffbf))
+#define SET_DMN_FLAG_CLR(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 7) | ((REG32(ADR_MMU_CTRL)) & 0xffffff7f))
+#define SET_ERR_SW_RST_N(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_MMU_CTRL)) & 0xfffffeff))
+#define SET_ALR_SW_RST_N(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 9) | ((REG32(ADR_MMU_CTRL)) & 0xfffffdff))
+#define SET_MCH_SW_RST_N(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 10) | ((REG32(ADR_MMU_CTRL)) & 0xfffffbff))
+#define SET_TAG_SW_RST_N(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 11) | ((REG32(ADR_MMU_CTRL)) & 0xfffff7ff))
+#define SET_ABT_SW_RST_N(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 12) | ((REG32(ADR_MMU_CTRL)) & 0xffffefff))
+#define SET_MMU_VER(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 13) | ((REG32(ADR_MMU_CTRL)) & 0xffff1fff))
+#define SET_MMU_SHARE_MCU(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_MMU_CTRL)) & 0xff00ffff))
+#define SET_HS_WR(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_HS_CTRL)) & 0xfffffffe))
+#define SET_HS_FLAG(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 4) | ((REG32(ADR_HS_CTRL)) & 0xffffffef))
+#define SET_HS_ID(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_HS_CTRL)) & 0xffff80ff))
+#define SET_HS_CHANNEL(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_HS_CTRL)) & 0xfff0ffff))
+#define SET_HS_PAGE(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 20) | ((REG32(ADR_HS_CTRL)) & 0xff0fffff))
+#define SET_HS_DATA(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 24) | ((REG32(ADR_HS_CTRL)) & 0x00ffffff))
+#define SET_CPU_POR0(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_POR0_7)) & 0xfffffff0))
+#define SET_CPU_POR1(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 4) | ((REG32(ADR_CPU_POR0_7)) & 0xffffff0f))
+#define SET_CPU_POR2(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 8) | ((REG32(ADR_CPU_POR0_7)) & 0xfffff0ff))
+#define SET_CPU_POR3(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 12) | ((REG32(ADR_CPU_POR0_7)) & 0xffff0fff))
+#define SET_CPU_POR4(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 16) | ((REG32(ADR_CPU_POR0_7)) & 0xfff0ffff))
+#define SET_CPU_POR5(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 20) | ((REG32(ADR_CPU_POR0_7)) & 0xff0fffff))
+#define SET_CPU_POR6(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 24) | ((REG32(ADR_CPU_POR0_7)) & 0xf0ffffff))
+#define SET_CPU_POR7(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 28) | ((REG32(ADR_CPU_POR0_7)) & 0x0fffffff))
+#define SET_CPU_POR8(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_POR8_F)) & 0xfffffff0))
+#define SET_CPU_POR9(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 4) | ((REG32(ADR_CPU_POR8_F)) & 0xffffff0f))
+#define SET_CPU_PORA(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 8) | ((REG32(ADR_CPU_POR8_F)) & 0xfffff0ff))
+#define SET_CPU_PORB(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 12) | ((REG32(ADR_CPU_POR8_F)) & 0xffff0fff))
+#define SET_CPU_PORC(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 16) | ((REG32(ADR_CPU_POR8_F)) & 0xfff0ffff))
+#define SET_CPU_PORD(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 20) | ((REG32(ADR_CPU_POR8_F)) & 0xff0fffff))
+#define SET_CPU_PORE(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 24) | ((REG32(ADR_CPU_POR8_F)) & 0xf0ffffff))
+#define SET_CPU_PORF(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 28) | ((REG32(ADR_CPU_POR8_F)) & 0x0fffffff))
+#define SET_ACC_WR_LEN(_VAL_) (REG32(ADR_REG_LEN_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_REG_LEN_CTRL)) & 0xffffffc0))
+#define SET_ACC_RD_LEN(_VAL_) (REG32(ADR_REG_LEN_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_REG_LEN_CTRL)) & 0xffffc0ff))
+#define SET_REQ_NACK_CLR(_VAL_) (REG32(ADR_REG_LEN_CTRL)) = (((_VAL_) << 15) | ((REG32(ADR_REG_LEN_CTRL)) & 0xffff7fff))
+#define SET_NACK_FLAG_BUS(_VAL_) (REG32(ADR_REG_LEN_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_REG_LEN_CTRL)) & 0x0000ffff))
+#define SET_DMN_R_PASS(_VAL_) (REG32(ADR_DMN_READ_BYPASS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_READ_BYPASS)) & 0xffff0000))
+#define SET_PARA_ALC_RLS(_VAL_) (REG32(ADR_DMN_READ_BYPASS)) = (((_VAL_) << 16) | ((REG32(ADR_DMN_READ_BYPASS)) & 0xfffeffff))
+#define SET_REQ_PORNS_CHGEN(_VAL_) (REG32(ADR_DMN_READ_BYPASS)) = (((_VAL_) << 24) | ((REG32(ADR_DMN_READ_BYPASS)) & 0xfeffffff))
+#define SET_ALC_ABT_ID(_VAL_) (REG32(ADR_ALC_RLS_ABORT)) = (((_VAL_) << 0) | ((REG32(ADR_ALC_RLS_ABORT)) & 0xffffff80))
+#define SET_ALC_ABT_INT(_VAL_) (REG32(ADR_ALC_RLS_ABORT)) = (((_VAL_) << 15) | ((REG32(ADR_ALC_RLS_ABORT)) & 0xffff7fff))
+#define SET_RLS_ABT_ID(_VAL_) (REG32(ADR_ALC_RLS_ABORT)) = (((_VAL_) << 16) | ((REG32(ADR_ALC_RLS_ABORT)) & 0xff80ffff))
+#define SET_RLS_ABT_INT(_VAL_) (REG32(ADR_ALC_RLS_ABORT)) = (((_VAL_) << 31) | ((REG32(ADR_ALC_RLS_ABORT)) & 0x7fffffff))
+#define SET_DEBUG_CTL(_VAL_) (REG32(ADR_DEBUG_CTL)) = (((_VAL_) << 0) | ((REG32(ADR_DEBUG_CTL)) & 0xffffff00))
+#define SET_DEBUG_H16(_VAL_) (REG32(ADR_DEBUG_CTL)) = (((_VAL_) << 8) | ((REG32(ADR_DEBUG_CTL)) & 0xfffffeff))
+#define SET_DEBUG_OUT(_VAL_) (REG32(ADR_DEBUG_OUT)) = (((_VAL_) << 0) | ((REG32(ADR_DEBUG_OUT)) & 0x00000000))
+#define SET_ALC_ERR(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MMU_STATUS)) & 0xfffffffe))
+#define SET_RLS_ERR(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_MMU_STATUS)) & 0xfffffffd))
+#define SET_AL_STATE(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_MMU_STATUS)) & 0xfffff8ff))
+#define SET_RL_STATE(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 12) | ((REG32(ADR_MMU_STATUS)) & 0xffff8fff))
+#define SET_ALC_ERR_ID(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_MMU_STATUS)) & 0xff80ffff))
+#define SET_RLS_ERR_ID(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 24) | ((REG32(ADR_MMU_STATUS)) & 0x80ffffff))
+#define SET_DMN_NOHIT_FLAG(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_STATUS)) & 0xfffffffe))
+#define SET_DMN_FLAG(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_DMN_STATUS)) & 0xfffffffd))
+#define SET_DMN_WR(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 3) | ((REG32(ADR_DMN_STATUS)) & 0xfffffff7))
+#define SET_DMN_PORT(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 4) | ((REG32(ADR_DMN_STATUS)) & 0xffffff0f))
+#define SET_DMN_NHIT_ID(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_DMN_STATUS)) & 0xffff80ff))
+#define SET_DMN_NHIT_ADDR(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_DMN_STATUS)) & 0x0000ffff))
+#define SET_TX_MOUNT(_VAL_) (REG32(ADR_TAG_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_STATUS)) & 0xffffff00))
+#define SET_RX_MOUNT(_VAL_) (REG32(ADR_TAG_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_TAG_STATUS)) & 0xffff00ff))
+#define SET_AVA_TAG(_VAL_) (REG32(ADR_TAG_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_STATUS)) & 0xfe00ffff))
+#define SET_PKTBUF_FULL(_VAL_) (REG32(ADR_TAG_STATUS)) = (((_VAL_) << 31) | ((REG32(ADR_TAG_STATUS)) & 0x7fffffff))
+#define SET_DMN_NOHIT_MCU(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_MCU_STATUS)) & 0xfffffffe))
+#define SET_DMN_MCU_FLAG(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_DMN_MCU_STATUS)) & 0xfffffffd))
+#define SET_DMN_MCU_WR(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 3) | ((REG32(ADR_DMN_MCU_STATUS)) & 0xfffffff7))
+#define SET_DMN_MCU_PORT(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 4) | ((REG32(ADR_DMN_MCU_STATUS)) & 0xffffff0f))
+#define SET_DMN_MCU_ID(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_DMN_MCU_STATUS)) & 0xffff80ff))
+#define SET_DMN_MCU_ADDR(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_DMN_MCU_STATUS)) & 0x0000ffff))
+#define SET_MB_IDTBL_31_0(_VAL_) (REG32(ADR_MB_IDTBL_0_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_IDTBL_0_STATUS)) & 0x00000000))
+#define SET_MB_IDTBL_63_32(_VAL_) (REG32(ADR_MB_IDTBL_1_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_IDTBL_1_STATUS)) & 0x00000000))
+#define SET_MB_IDTBL_95_64(_VAL_) (REG32(ADR_MB_IDTBL_2_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_IDTBL_2_STATUS)) & 0x00000000))
+#define SET_MB_IDTBL_127_96(_VAL_) (REG32(ADR_MB_IDTBL_3_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_IDTBL_3_STATUS)) & 0x00000000))
+#define SET_PKT_IDTBL_31_0(_VAL_) (REG32(ADR_PKT_IDTBL_0_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_IDTBL_0_STATUS)) & 0x00000000))
+#define SET_PKT_IDTBL_63_32(_VAL_) (REG32(ADR_PKT_IDTBL_1_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_IDTBL_1_STATUS)) & 0x00000000))
+#define SET_PKT_IDTBL_95_64(_VAL_) (REG32(ADR_PKT_IDTBL_2_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_IDTBL_2_STATUS)) & 0x00000000))
+#define SET_PKT_IDTBL_127_96(_VAL_) (REG32(ADR_PKT_IDTBL_3_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_IDTBL_3_STATUS)) & 0x00000000))
+#define SET_DMN_IDTBL_31_0(_VAL_) (REG32(ADR_DMN_IDTBL_0_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_IDTBL_0_STATUS)) & 0x00000000))
+#define SET_DMN_IDTBL_63_32(_VAL_) (REG32(ADR_DMN_IDTBL_1_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_IDTBL_1_STATUS)) & 0x00000000))
+#define SET_DMN_IDTBL_95_64(_VAL_) (REG32(ADR_DMN_IDTBL_2_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_IDTBL_2_STATUS)) & 0x00000000))
+#define SET_DMN_IDTBL_127_96(_VAL_) (REG32(ADR_DMN_IDTBL_3_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_IDTBL_3_STATUS)) & 0x00000000))
+#define SET_NEQ_MB_ID_31_0(_VAL_) (REG32(ADR_MB_NEQID_0_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_NEQID_0_STATUS)) & 0x00000000))
+#define SET_NEQ_MB_ID_63_32(_VAL_) (REG32(ADR_MB_NEQID_1_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_NEQID_1_STATUS)) & 0x00000000))
+#define SET_NEQ_MB_ID_95_64(_VAL_) (REG32(ADR_MB_NEQID_2_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_NEQID_2_STATUS)) & 0x00000000))
+#define SET_NEQ_MB_ID_127_96(_VAL_) (REG32(ADR_MB_NEQID_3_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_NEQID_3_STATUS)) & 0x00000000))
+#define SET_NEQ_PKT_ID_31_0(_VAL_) (REG32(ADR_PKT_NEQID_0_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_NEQID_0_STATUS)) & 0x00000000))
+#define SET_NEQ_PKT_ID_63_32(_VAL_) (REG32(ADR_PKT_NEQID_1_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_NEQID_1_STATUS)) & 0x00000000))
+#define SET_NEQ_PKT_ID_95_64(_VAL_) (REG32(ADR_PKT_NEQID_2_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_NEQID_2_STATUS)) & 0x00000000))
+#define SET_NEQ_PKT_ID_127_96(_VAL_) (REG32(ADR_PKT_NEQID_3_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_NEQID_3_STATUS)) & 0x00000000))
+#define SET_ALC_NOCHG_ID(_VAL_) (REG32(ADR_ALC_NOCHG_ID_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0xffffff80))
+#define SET_ALC_NOCHG_INT(_VAL_) (REG32(ADR_ALC_NOCHG_ID_STATUS)) = (((_VAL_) << 15) | ((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0xffff7fff))
+#define SET_NEQ_PKT_FLAG(_VAL_) (REG32(ADR_ALC_NOCHG_ID_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0xfffeffff))
+#define SET_NEQ_MB_FLAG(_VAL_) (REG32(ADR_ALC_NOCHG_ID_STATUS)) = (((_VAL_) << 24) | ((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0xfeffffff))
+#define SET_SRAM_TAG_0(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_0)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_0)) & 0xffff0000))
+#define SET_SRAM_TAG_1(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_0)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_0)) & 0x0000ffff))
+#define SET_SRAM_TAG_2(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_1)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_1)) & 0xffff0000))
+#define SET_SRAM_TAG_3(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_1)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_1)) & 0x0000ffff))
+#define SET_SRAM_TAG_4(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_2)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_2)) & 0xffff0000))
+#define SET_SRAM_TAG_5(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_2)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_2)) & 0x0000ffff))
+#define SET_SRAM_TAG_6(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_3)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_3)) & 0xffff0000))
+#define SET_SRAM_TAG_7(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_3)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_3)) & 0x0000ffff))
+#define SET_SRAM_TAG_8(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_4)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_4)) & 0xffff0000))
+#define SET_SRAM_TAG_9(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_4)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_4)) & 0x0000ffff))
+#define SET_SRAM_TAG_10(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_5)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_5)) & 0xffff0000))
+#define SET_SRAM_TAG_11(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_5)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_5)) & 0x0000ffff))
+#define SET_SRAM_TAG_12(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_6)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_6)) & 0xffff0000))
+#define SET_SRAM_TAG_13(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_6)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_6)) & 0x0000ffff))
+#define SET_SRAM_TAG_14(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_7)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_7)) & 0xffff0000))
+#define SET_SRAM_TAG_15(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_7)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_7)) & 0x0000ffff))
+#define DEF_BRG_SW_RST() (REG32(ADR_BRG_SW_RST)) = (0x00000000)
+#define DEF_BOOT() (REG32(ADR_BOOT)) = (0x00040000)
+#define DEF_CHIP_ID_0() (REG32(ADR_CHIP_ID_0)) = (0x31333131)
+#define DEF_CHIP_ID_1() (REG32(ADR_CHIP_ID_1)) = (0x322d3230)
+#define DEF_CHIP_ID_2() (REG32(ADR_CHIP_ID_2)) = (0x32303041)
+#define DEF_CHIP_ID_3() (REG32(ADR_CHIP_ID_3)) = (0x53535636)
+#define DEF_CLOCK_SELECTION() (REG32(ADR_CLOCK_SELECTION)) = (0x00000000)
+#define DEF_PLATFORM_CLOCK_ENABLE() (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (0x008fffff)
+#define DEF_SYS_CSR_CLOCK_ENABLE() (REG32(ADR_SYS_CSR_CLOCK_ENABLE)) = (0x00000400)
+#define DEF_MCU_DBG_SEL() (REG32(ADR_MCU_DBG_SEL)) = (0x00000000)
+#define DEF_MCU_DBG_DATA() (REG32(ADR_MCU_DBG_DATA)) = (0x00000000)
+#define DEF_AHB_BRG_STATUS() (REG32(ADR_AHB_BRG_STATUS)) = (0x00000000)
+#define DEF_BIST_BIST_CTRL() (REG32(ADR_BIST_BIST_CTRL)) = (0x00000000)
+#define DEF_BIST_MODE_REG_IN() (REG32(ADR_BIST_MODE_REG_IN)) = (0x001ffe3e)
+#define DEF_BIST_MODE_REG_OUT() (REG32(ADR_BIST_MODE_REG_OUT)) = (0x00000000)
+#define DEF_BIST_MONITOR_BUS_LSB() (REG32(ADR_BIST_MONITOR_BUS_LSB)) = (0x00000000)
+#define DEF_BIST_MONITOR_BUS_MSB() (REG32(ADR_BIST_MONITOR_BUS_MSB)) = (0x00000000)
+#define DEF_TB_ADR_SEL() (REG32(ADR_TB_ADR_SEL)) = (0x00000000)
+#define DEF_TB_RDATA() (REG32(ADR_TB_RDATA)) = (0x00000000)
+#define DEF_UART_W2B() (REG32(ADR_UART_W2B)) = (0x00000000)
+#define DEF_AHB_ILL_ADDR() (REG32(ADR_AHB_ILL_ADDR)) = (0x00000000)
+#define DEF_AHB_FEN_ADDR() (REG32(ADR_AHB_FEN_ADDR)) = (0x00000000)
+#define DEF_AHB_ILLFEN_STATUS() (REG32(ADR_AHB_ILLFEN_STATUS)) = (0x00000000)
+#define DEF_PWM_A() (REG32(ADR_PWM_A)) = (0x400a1010)
+#define DEF_PWM_B() (REG32(ADR_PWM_B)) = (0x400a1010)
+#define DEF_HBUSREQ_LOCK() (REG32(ADR_HBUSREQ_LOCK)) = (0x00001ffd)
+#define DEF_HBURST_LOCK() (REG32(ADR_HBURST_LOCK)) = (0x00000000)
+#define DEF_PRESCALER_USTIMER() (REG32(ADR_PRESCALER_USTIMER)) = (0x00000028)
+#define DEF_BIST_MODE_REG_IN_MMU() (REG32(ADR_BIST_MODE_REG_IN_MMU)) = (0x0000fe3e)
+#define DEF_BIST_MODE_REG_OUT_MMU() (REG32(ADR_BIST_MODE_REG_OUT_MMU)) = (0x00000000)
+#define DEF_BIST_MONITOR_BUS_MMU() (REG32(ADR_BIST_MONITOR_BUS_MMU)) = (0x00000000)
+#define DEF_TEST_MODE() (REG32(ADR_TEST_MODE)) = (0x00000000)
+#define DEF_BOOT_INFO() (REG32(ADR_BOOT_INFO)) = (0x00000000)
+#define DEF_SD_INIT_CFG() (REG32(ADR_SD_INIT_CFG)) = (0x00000000)
+#define DEF_SPARE_UART_INFO() (REG32(ADR_SPARE_UART_INFO)) = (0x00000000)
+#define DEF_TU0_MICROSECOND_TIMER() (REG32(ADR_TU0_MICROSECOND_TIMER)) = (0x00000000)
+#define DEF_TU0_CURRENT_MICROSECOND_TIME_VALUE() (REG32(ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TU0_DUMMY_BIT_0() (REG32(ADR_TU0_DUMMY_BIT_0)) = (0x00000000)
+#define DEF_TU0_DUMMY_BIT_1() (REG32(ADR_TU0_DUMMY_BIT_1)) = (0x00000000)
+#define DEF_TU1_MICROSECOND_TIMER() (REG32(ADR_TU1_MICROSECOND_TIMER)) = (0x00000000)
+#define DEF_TU1_CURRENT_MICROSECOND_TIME_VALUE() (REG32(ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TU1_DUMMY_BIT_0() (REG32(ADR_TU1_DUMMY_BIT_0)) = (0x00000000)
+#define DEF_TU1_DUMMY_BIT_1() (REG32(ADR_TU1_DUMMY_BIT_1)) = (0x00000000)
+#define DEF_TU2_MICROSECOND_TIMER() (REG32(ADR_TU2_MICROSECOND_TIMER)) = (0x00000000)
+#define DEF_TU2_CURRENT_MICROSECOND_TIME_VALUE() (REG32(ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TU2_DUMMY_BIT_0() (REG32(ADR_TU2_DUMMY_BIT_0)) = (0x00000000)
+#define DEF_TU2_DUMMY_BIT_1() (REG32(ADR_TU2_DUMMY_BIT_1)) = (0x00000000)
+#define DEF_TU3_MICROSECOND_TIMER() (REG32(ADR_TU3_MICROSECOND_TIMER)) = (0x00000000)
+#define DEF_TU3_CURRENT_MICROSECOND_TIME_VALUE() (REG32(ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TU3_DUMMY_BIT_0() (REG32(ADR_TU3_DUMMY_BIT_0)) = (0x00000000)
+#define DEF_TU3_DUMMY_BIT_1() (REG32(ADR_TU3_DUMMY_BIT_1)) = (0x00000000)
+#define DEF_TM0_MILISECOND_TIMER() (REG32(ADR_TM0_MILISECOND_TIMER)) = (0x00000000)
+#define DEF_TM0_CURRENT_MILISECOND_TIME_VALUE() (REG32(ADR_TM0_CURRENT_MILISECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TM0_DUMMY_BIT_0() (REG32(ADR_TM0_DUMMY_BIT_0)) = (0x00000000)
+#define DEF_TM0_DUMMY_BIT_1() (REG32(ADR_TM0_DUMMY_BIT_1)) = (0x00000000)
+#define DEF_TM1_MILISECOND_TIMER() (REG32(ADR_TM1_MILISECOND_TIMER)) = (0x00000000)
+#define DEF_TM1_CURRENT_MILISECOND_TIME_VALUE() (REG32(ADR_TM1_CURRENT_MILISECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TM1_DUMMY_BIT_0() (REG32(ADR_TM1_DUMMY_BIT_0)) = (0x00000000)
+#define DEF_TM1_DUMMY_BIT_1() (REG32(ADR_TM1_DUMMY_BIT_1)) = (0x00000000)
+#define DEF_TM2_MILISECOND_TIMER() (REG32(ADR_TM2_MILISECOND_TIMER)) = (0x00000000)
+#define DEF_TM2_CURRENT_MILISECOND_TIME_VALUE() (REG32(ADR_TM2_CURRENT_MILISECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TM2_DUMMY_BIT_0() (REG32(ADR_TM2_DUMMY_BIT_0)) = (0x00000000)
+#define DEF_TM2_DUMMY_BIT_1() (REG32(ADR_TM2_DUMMY_BIT_1)) = (0x00000000)
+#define DEF_TM3_MILISECOND_TIMER() (REG32(ADR_TM3_MILISECOND_TIMER)) = (0x00000000)
+#define DEF_TM3_CURRENT_MILISECOND_TIME_VALUE() (REG32(ADR_TM3_CURRENT_MILISECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TM3_DUMMY_BIT_0() (REG32(ADR_TM3_DUMMY_BIT_0)) = (0x00000000)
+#define DEF_TM3_DUMMY_BIT_1() (REG32(ADR_TM3_DUMMY_BIT_1)) = (0x00000000)
+#define DEF_MCU_WDOG_REG() (REG32(ADR_MCU_WDOG_REG)) = (0x00000000)
+#define DEF_SYS_WDOG_REG() (REG32(ADR_SYS_WDOG_REG)) = (0x00000000)
+#define DEF_PAD6() (REG32(ADR_PAD6)) = (0x00000008)
+#define DEF_PAD7() (REG32(ADR_PAD7)) = (0x00000008)
+#define DEF_PAD8() (REG32(ADR_PAD8)) = (0x00000008)
+#define DEF_PAD9() (REG32(ADR_PAD9)) = (0x00000008)
+#define DEF_PAD11() (REG32(ADR_PAD11)) = (0x00000008)
+#define DEF_PAD15() (REG32(ADR_PAD15)) = (0x0000000a)
+#define DEF_PAD16() (REG32(ADR_PAD16)) = (0x0000000a)
+#define DEF_PAD17() (REG32(ADR_PAD17)) = (0x0000000a)
+#define DEF_PAD18() (REG32(ADR_PAD18)) = (0x0000000a)
+#define DEF_PAD19() (REG32(ADR_PAD19)) = (0x00007000)
+#define DEF_PAD20() (REG32(ADR_PAD20)) = (0x0000000a)
+#define DEF_PAD21() (REG32(ADR_PAD21)) = (0x0000000a)
+#define DEF_PAD22() (REG32(ADR_PAD22)) = (0x00000009)
+#define DEF_PAD24() (REG32(ADR_PAD24)) = (0x00000008)
+#define DEF_PAD25() (REG32(ADR_PAD25)) = (0x0000000b)
+#define DEF_PAD27() (REG32(ADR_PAD27)) = (0x00000008)
+#define DEF_PAD28() (REG32(ADR_PAD28)) = (0x00000008)
+#define DEF_PAD29() (REG32(ADR_PAD29)) = (0x00000009)
+#define DEF_PAD30() (REG32(ADR_PAD30)) = (0x0000000a)
+#define DEF_PAD31() (REG32(ADR_PAD31)) = (0x0000000a)
+#define DEF_PAD32() (REG32(ADR_PAD32)) = (0x0000000a)
+#define DEF_PAD33() (REG32(ADR_PAD33)) = (0x0000000a)
+#define DEF_PAD34() (REG32(ADR_PAD34)) = (0x0000000a)
+#define DEF_PAD42() (REG32(ADR_PAD42)) = (0x0000000a)
+#define DEF_PAD43() (REG32(ADR_PAD43)) = (0x0000000a)
+#define DEF_PAD44() (REG32(ADR_PAD44)) = (0x0000000a)
+#define DEF_PAD45() (REG32(ADR_PAD45)) = (0x0000000a)
+#define DEF_PAD46() (REG32(ADR_PAD46)) = (0x0000000a)
+#define DEF_PAD47() (REG32(ADR_PAD47)) = (0x00100000)
+#define DEF_PAD48() (REG32(ADR_PAD48)) = (0x00100808)
+#define DEF_PAD49() (REG32(ADR_PAD49)) = (0x00100008)
+#define DEF_PAD50() (REG32(ADR_PAD50)) = (0x00100008)
+#define DEF_PAD51() (REG32(ADR_PAD51)) = (0x00100008)
+#define DEF_PAD52() (REG32(ADR_PAD52)) = (0x00100000)
+#define DEF_PAD53() (REG32(ADR_PAD53)) = (0x0000000a)
+#define DEF_PAD54() (REG32(ADR_PAD54)) = (0x00000000)
+#define DEF_PAD56() (REG32(ADR_PAD56)) = (0x00000000)
+#define DEF_PAD57() (REG32(ADR_PAD57)) = (0x00000008)
+#define DEF_PAD58() (REG32(ADR_PAD58)) = (0x0000000a)
+#define DEF_PAD59() (REG32(ADR_PAD59)) = (0x0000000a)
+#define DEF_PAD60() (REG32(ADR_PAD60)) = (0x0000000a)
+#define DEF_PAD61() (REG32(ADR_PAD61)) = (0x0000000a)
+#define DEF_PAD62() (REG32(ADR_PAD62)) = (0x0000000a)
+#define DEF_PAD64() (REG32(ADR_PAD64)) = (0x00000009)
+#define DEF_PAD65() (REG32(ADR_PAD65)) = (0x00000009)
+#define DEF_PAD66() (REG32(ADR_PAD66)) = (0x00000008)
+#define DEF_PAD68() (REG32(ADR_PAD68)) = (0x00000008)
+#define DEF_PAD67() (REG32(ADR_PAD67)) = (0x00000159)
+#define DEF_PAD69() (REG32(ADR_PAD69)) = (0x0000000b)
+#define DEF_PAD70() (REG32(ADR_PAD70)) = (0x00000008)
+#define DEF_PAD231() (REG32(ADR_PAD231)) = (0x00000008)
+#define DEF_PIN_SEL_0() (REG32(ADR_PIN_SEL_0)) = (0x00000000)
+#define DEF_PIN_SEL_1() (REG32(ADR_PIN_SEL_1)) = (0x00000000)
+#define DEF_IO_PORT_REG() (REG32(ADR_IO_PORT_REG)) = (0x00010000)
+#define DEF_INT_MASK_REG() (REG32(ADR_INT_MASK_REG)) = (0x000000ff)
+#define DEF_INT_STATUS_REG() (REG32(ADR_INT_STATUS_REG)) = (0x00000000)
+#define DEF_FN1_STATUS_REG() (REG32(ADR_FN1_STATUS_REG)) = (0x00000000)
+#define DEF_CARD_PKT_STATUS_TEST() (REG32(ADR_CARD_PKT_STATUS_TEST)) = (0x00000000)
+#define DEF_SYSTEM_INFORMATION_REG() (REG32(ADR_SYSTEM_INFORMATION_REG)) = (0x00000000)
+#define DEF_CARD_RCA_REG() (REG32(ADR_CARD_RCA_REG)) = (0x00000000)
+#define DEF_SDIO_FIFO_WR_THLD_REG() (REG32(ADR_SDIO_FIFO_WR_THLD_REG)) = (0x00000000)
+#define DEF_SDIO_FIFO_WR_LIMIT_REG() (REG32(ADR_SDIO_FIFO_WR_LIMIT_REG)) = (0x00000000)
+#define DEF_SDIO_TX_DATA_BATCH_SIZE_REG() (REG32(ADR_SDIO_TX_DATA_BATCH_SIZE_REG)) = (0x00000000)
+#define DEF_SDIO_THLD_FOR_CMD53RD_REG() (REG32(ADR_SDIO_THLD_FOR_CMD53RD_REG)) = (0x00000000)
+#define DEF_SDIO_RX_DATA_BATCH_SIZE_REG() (REG32(ADR_SDIO_RX_DATA_BATCH_SIZE_REG)) = (0x00000000)
+#define DEF_SDIO_LOG_START_END_DATA_REG() (REG32(ADR_SDIO_LOG_START_END_DATA_REG)) = (0x00000000)
+#define DEF_SDIO_BYTE_MODE_BATCH_SIZE_REG() (REG32(ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG)) = (0x00000000)
+#define DEF_SDIO_LAST_CMD_INDEX_CRC_REG() (REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) = (0x00000000)
+#define DEF_SDIO_LAST_CMD_ARG_REG() (REG32(ADR_SDIO_LAST_CMD_ARG_REG)) = (0x00000000)
+#define DEF_SDIO_BUS_STATE_DEBUG_MONITOR() (REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) = (0x00000000)
+#define DEF_SDIO_CARD_STATUS_REG() (REG32(ADR_SDIO_CARD_STATUS_REG)) = (0x00000000)
+#define DEF_R5_RESP_FLAG_OUT_TIMING() (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (0x00000000)
+#define DEF_CMD52_DATA_FOR_LAST_TIME() (REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) = (0x00000000)
+#define DEF_FN1_DMA_START_ADDR_REG() (REG32(ADR_FN1_DMA_START_ADDR_REG)) = (0x00000000)
+#define DEF_FN1_INT_CTRL_RESET() (REG32(ADR_FN1_INT_CTRL_RESET)) = (0x00000000)
+#define DEF_IO_REG_PORT_REG() (REG32(ADR_IO_REG_PORT_REG)) = (0x00010020)
+#define DEF_SDIO_FIFO_ERROR_CNT() (REG32(ADR_SDIO_FIFO_ERROR_CNT)) = (0x00000000)
+#define DEF_SDIO_CRC7_CRC16_ERROR_REG() (REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) = (0x00000000)
+#define DEF_SDIO_BLOCK_CNT_INFO() (REG32(ADR_SDIO_BLOCK_CNT_INFO)) = (0x00000000)
+#define DEF_RX_DATA_CMD52_ABORT_COUNT() (REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) = (0x00000000)
+#define DEF_FIFO_PTR_READ_BLOCK_CNT() (REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) = (0x00000000)
+#define DEF_TX_TIME_OUT_READ_CTRL() (REG32(ADR_TX_TIME_OUT_READ_CTRL)) = (0x00000000)
+#define DEF_SDIO_TX_ALLOC_REG() (REG32(ADR_SDIO_TX_ALLOC_REG)) = (0x00000000)
+#define DEF_SDIO_TX_INFORM() (REG32(ADR_SDIO_TX_INFORM)) = (0x00000000)
+#define DEF_F1_BLOCK_SIZE_0_REG() (REG32(ADR_F1_BLOCK_SIZE_0_REG)) = (0x00000000)
+#define DEF_SDIO_COMMAND_LOG_DATA_31_0() (REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) = (0x000000ec)
+#define DEF_SDIO_COMMAND_LOG_DATA_63_32() (REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) = (0xce000000)
+#define DEF_SYSTEM_INFORMATION_REGISTER() (REG32(ADR_SYSTEM_INFORMATION_REGISTER)) = (0x00000000)
+#define DEF_CCCR_00H_REG() (REG32(ADR_CCCR_00H_REG)) = (0x00000000)
+#define DEF_CCCR_04H_REG() (REG32(ADR_CCCR_04H_REG)) = (0x00000000)
+#define DEF_CCCR_08H_REG() (REG32(ADR_CCCR_08H_REG)) = (0x00000000)
+#define DEF_CCCR_13H_REG() (REG32(ADR_CCCR_13H_REG)) = (0x00000000)
+#define DEF_FBR_100H_REG() (REG32(ADR_FBR_100H_REG)) = (0x00000000)
+#define DEF_FBR_109H_REG() (REG32(ADR_FBR_109H_REG)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_0() (REG32(ADR_F0_CIS_CONTENT_REG_0)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_1() (REG32(ADR_F0_CIS_CONTENT_REG_1)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_2() (REG32(ADR_F0_CIS_CONTENT_REG_2)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_3() (REG32(ADR_F0_CIS_CONTENT_REG_3)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_4() (REG32(ADR_F0_CIS_CONTENT_REG_4)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_5() (REG32(ADR_F0_CIS_CONTENT_REG_5)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_6() (REG32(ADR_F0_CIS_CONTENT_REG_6)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_7() (REG32(ADR_F0_CIS_CONTENT_REG_7)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_8() (REG32(ADR_F0_CIS_CONTENT_REG_8)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_9() (REG32(ADR_F0_CIS_CONTENT_REG_9)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_10() (REG32(ADR_F0_CIS_CONTENT_REG_10)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_11() (REG32(ADR_F0_CIS_CONTENT_REG_11)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_12() (REG32(ADR_F0_CIS_CONTENT_REG_12)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_13() (REG32(ADR_F0_CIS_CONTENT_REG_13)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_14() (REG32(ADR_F0_CIS_CONTENT_REG_14)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_15() (REG32(ADR_F0_CIS_CONTENT_REG_15)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_0() (REG32(ADR_F1_CIS_CONTENT_REG_0)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_1() (REG32(ADR_F1_CIS_CONTENT_REG_1)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_2() (REG32(ADR_F1_CIS_CONTENT_REG_2)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_3() (REG32(ADR_F1_CIS_CONTENT_REG_3)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_4() (REG32(ADR_F1_CIS_CONTENT_REG_4)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_5() (REG32(ADR_F1_CIS_CONTENT_REG_5)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_6() (REG32(ADR_F1_CIS_CONTENT_REG_6)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_7() (REG32(ADR_F1_CIS_CONTENT_REG_7)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_8() (REG32(ADR_F1_CIS_CONTENT_REG_8)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_9() (REG32(ADR_F1_CIS_CONTENT_REG_9)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_10() (REG32(ADR_F1_CIS_CONTENT_REG_10)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_11() (REG32(ADR_F1_CIS_CONTENT_REG_11)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_12() (REG32(ADR_F1_CIS_CONTENT_REG_12)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_13() (REG32(ADR_F1_CIS_CONTENT_REG_13)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_14() (REG32(ADR_F1_CIS_CONTENT_REG_14)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_15() (REG32(ADR_F1_CIS_CONTENT_REG_15)) = (0x00000000)
+#define DEF_SPI_MODE() (REG32(ADR_SPI_MODE)) = (0x00000000)
+#define DEF_RX_QUOTA() (REG32(ADR_RX_QUOTA)) = (0x00000000)
+#define DEF_CONDITION_NUMBER() (REG32(ADR_CONDITION_NUMBER)) = (0x00000004)
+#define DEF_HOST_PATH() (REG32(ADR_HOST_PATH)) = (0x00000001)
+#define DEF_TX_SEG() (REG32(ADR_TX_SEG)) = (0x00000000)
+#define DEF_DEBUG_BURST_MODE() (REG32(ADR_DEBUG_BURST_MODE)) = (0x00000000)
+#define DEF_SPI_TO_PHY_PARAM1() (REG32(ADR_SPI_TO_PHY_PARAM1)) = (0x000e0006)
+#define DEF_SPI_TO_PHY_PARAM2() (REG32(ADR_SPI_TO_PHY_PARAM2)) = (0x000e000e)
+#define DEF_SPI_STS() (REG32(ADR_SPI_STS)) = (0x00000000)
+#define DEF_TX_ALLOC_SET() (REG32(ADR_TX_ALLOC_SET)) = (0x00000000)
+#define DEF_TX_ALLOC() (REG32(ADR_TX_ALLOC)) = (0x00000000)
+#define DEF_DBG_CNT() (REG32(ADR_DBG_CNT)) = (0x00000000)
+#define DEF_DBG_CNT2() (REG32(ADR_DBG_CNT2)) = (0x00000000)
+#define DEF_DBG_CNT3() (REG32(ADR_DBG_CNT3)) = (0x00000000)
+#define DEF_DBG_CNT4() (REG32(ADR_DBG_CNT4)) = (0x00000000)
+#define DEF_INT_TAG() (REG32(ADR_INT_TAG)) = (0x00000000)
+#define DEF_I2CM_EN() (REG32(ADR_I2CM_EN)) = (0x00000074)
+#define DEF_I2CM_DEV_A() (REG32(ADR_I2CM_DEV_A)) = (0x00008000)
+#define DEF_I2CM_LEN() (REG32(ADR_I2CM_LEN)) = (0x00000000)
+#define DEF_I2CM_WDAT() (REG32(ADR_I2CM_WDAT)) = (0x00000000)
+#define DEF_I2CM_RDAT() (REG32(ADR_I2CM_RDAT)) = (0x00000000)
+#define DEF_I2CM_EN_2() (REG32(ADR_I2CM_EN_2)) = (0x00010000)
+#define DEF_UART_DATA() (REG32(ADR_UART_DATA)) = (0x00000000)
+#define DEF_UART_IER() (REG32(ADR_UART_IER)) = (0x00000000)
+#define DEF_UART_FCR() (REG32(ADR_UART_FCR)) = (0x00000001)
+#define DEF_UART_LCR() (REG32(ADR_UART_LCR)) = (0x00000003)
+#define DEF_UART_MCR() (REG32(ADR_UART_MCR)) = (0x00000000)
+#define DEF_UART_LSR() (REG32(ADR_UART_LSR)) = (0x00000000)
+#define DEF_UART_MSR() (REG32(ADR_UART_MSR)) = (0x00000000)
+#define DEF_UART_SPR() (REG32(ADR_UART_SPR)) = (0x00000000)
+#define DEF_UART_RTHR() (REG32(ADR_UART_RTHR)) = (0x000000c8)
+#define DEF_UART_ISR() (REG32(ADR_UART_ISR)) = (0x000000c1)
+#define DEF_DAT_UART_DATA() (REG32(ADR_DAT_UART_DATA)) = (0x00000000)
+#define DEF_DAT_UART_IER() (REG32(ADR_DAT_UART_IER)) = (0x00000000)
+#define DEF_DAT_UART_FCR() (REG32(ADR_DAT_UART_FCR)) = (0x00000001)
+#define DEF_DAT_UART_LCR() (REG32(ADR_DAT_UART_LCR)) = (0x00000003)
+#define DEF_DAT_UART_MCR() (REG32(ADR_DAT_UART_MCR)) = (0x00000000)
+#define DEF_DAT_UART_LSR() (REG32(ADR_DAT_UART_LSR)) = (0x00000000)
+#define DEF_DAT_UART_MSR() (REG32(ADR_DAT_UART_MSR)) = (0x00000000)
+#define DEF_DAT_UART_SPR() (REG32(ADR_DAT_UART_SPR)) = (0x00000000)
+#define DEF_DAT_UART_RTHR() (REG32(ADR_DAT_UART_RTHR)) = (0x000000c8)
+#define DEF_DAT_UART_ISR() (REG32(ADR_DAT_UART_ISR)) = (0x000000c1)
+#define DEF_INT_MASK() (REG32(ADR_INT_MASK)) = (0xffffffff)
+#define DEF_INT_MODE() (REG32(ADR_INT_MODE)) = (0x00000000)
+#define DEF_INT_IRQ_STS() (REG32(ADR_INT_IRQ_STS)) = (0x00000000)
+#define DEF_INT_FIQ_STS() (REG32(ADR_INT_FIQ_STS)) = (0x00000000)
+#define DEF_INT_IRQ_RAW() (REG32(ADR_INT_IRQ_RAW)) = (0x00000000)
+#define DEF_INT_FIQ_RAW() (REG32(ADR_INT_FIQ_RAW)) = (0x00000000)
+#define DEF_INT_PERI_MASK() (REG32(ADR_INT_PERI_MASK)) = (0xffffffff)
+#define DEF_INT_PERI_STS() (REG32(ADR_INT_PERI_STS)) = (0x00000000)
+#define DEF_INT_PERI_RAW() (REG32(ADR_INT_PERI_RAW)) = (0x00000000)
+#define DEF_INT_GPI_CFG() (REG32(ADR_INT_GPI_CFG)) = (0x00000000)
+#define DEF_SYS_INT_FOR_HOST() (REG32(ADR_SYS_INT_FOR_HOST)) = (0x00000001)
+#define DEF_SPI_IPC() (REG32(ADR_SPI_IPC)) = (0x00000000)
+#define DEF_SDIO_IPC() (REG32(ADR_SDIO_IPC)) = (0x00000000)
+#define DEF_SDIO_MASK() (REG32(ADR_SDIO_MASK)) = (0xffffffff)
+#define DEF_SDIO_IRQ_STS() (REG32(ADR_SDIO_IRQ_STS)) = (0x00000000)
+#define DEF_SD_PERI_MASK() (REG32(ADR_SD_PERI_MASK)) = (0xffffffff)
+#define DEF_SD_PERI_STS() (REG32(ADR_SD_PERI_STS)) = (0x00000000)
+#define DEF_DBG_SPI_MODE() (REG32(ADR_DBG_SPI_MODE)) = (0x00000000)
+#define DEF_DBG_RX_QUOTA() (REG32(ADR_DBG_RX_QUOTA)) = (0x00000000)
+#define DEF_DBG_CONDITION_NUMBER() (REG32(ADR_DBG_CONDITION_NUMBER)) = (0x00000004)
+#define DEF_DBG_HOST_PATH() (REG32(ADR_DBG_HOST_PATH)) = (0x00000001)
+#define DEF_DBG_TX_SEG() (REG32(ADR_DBG_TX_SEG)) = (0x00000000)
+#define DEF_DBG_DEBUG_BURST_MODE() (REG32(ADR_DBG_DEBUG_BURST_MODE)) = (0x00000000)
+#define DEF_DBG_SPI_TO_PHY_PARAM1() (REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) = (0x000e0006)
+#define DEF_DBG_SPI_TO_PHY_PARAM2() (REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) = (0x000e000e)
+#define DEF_DBG_SPI_STS() (REG32(ADR_DBG_SPI_STS)) = (0x00000000)
+#define DEF_DBG_TX_ALLOC_SET() (REG32(ADR_DBG_TX_ALLOC_SET)) = (0x00000000)
+#define DEF_DBG_TX_ALLOC() (REG32(ADR_DBG_TX_ALLOC)) = (0x00000000)
+#define DEF_DBG_DBG_CNT() (REG32(ADR_DBG_DBG_CNT)) = (0x00000000)
+#define DEF_DBG_DBG_CNT2() (REG32(ADR_DBG_DBG_CNT2)) = (0x00000000)
+#define DEF_DBG_DBG_CNT3() (REG32(ADR_DBG_DBG_CNT3)) = (0x00000000)
+#define DEF_DBG_DBG_CNT4() (REG32(ADR_DBG_DBG_CNT4)) = (0x00000000)
+#define DEF_DBG_INT_TAG() (REG32(ADR_DBG_INT_TAG)) = (0x00000000)
+#define DEF_BOOT_ADDR() (REG32(ADR_BOOT_ADDR)) = (0x00000000)
+#define DEF_VERIFY_DATA() (REG32(ADR_VERIFY_DATA)) = (0x5e11aa11)
+#define DEF_FLASH_ADDR() (REG32(ADR_FLASH_ADDR)) = (0x00000000)
+#define DEF_SRAM_ADDR() (REG32(ADR_SRAM_ADDR)) = (0x00000000)
+#define DEF_LEN() (REG32(ADR_LEN)) = (0x00000000)
+#define DEF_SPI_PARAM() (REG32(ADR_SPI_PARAM)) = (0x000f000f)
+#define DEF_SPI_PARAM2() (REG32(ADR_SPI_PARAM2)) = (0x00040001)
+#define DEF_CHECK_SUM_RESULT() (REG32(ADR_CHECK_SUM_RESULT)) = (0x00000000)
+#define DEF_CHECK_SUM_IN_FILE() (REG32(ADR_CHECK_SUM_IN_FILE)) = (0x00000000)
+#define DEF_COMMAND_LEN() (REG32(ADR_COMMAND_LEN)) = (0x00000000)
+#define DEF_COMMAND_ADDR() (REG32(ADR_COMMAND_ADDR)) = (0x00000000)
+#define DEF_DMA_ADR_SRC() (REG32(ADR_DMA_ADR_SRC)) = (0x00000000)
+#define DEF_DMA_ADR_DST() (REG32(ADR_DMA_ADR_DST)) = (0x00000000)
+#define DEF_DMA_CTRL() (REG32(ADR_DMA_CTRL)) = (0x000000aa)
+#define DEF_DMA_INT() (REG32(ADR_DMA_INT)) = (0x00000001)
+#define DEF_DMA_FILL_CONST() (REG32(ADR_DMA_FILL_CONST)) = (0x00000000)
+#define DEF_PMU_0() (REG32(ADR_PMU_0)) = (0x0f000040)
+#define DEF_PMU_1() (REG32(ADR_PMU_1)) = (0x015d015d)
+#define DEF_PMU_2() (REG32(ADR_PMU_2)) = (0x00000000)
+#define DEF_PMU_3() (REG32(ADR_PMU_3)) = (0x55550000)
+#define DEF_RTC_1() (REG32(ADR_RTC_1)) = (0x7fff0000)
+#define DEF_RTC_2() (REG32(ADR_RTC_2)) = (0x00000003)
+#define DEF_RTC_3W() (REG32(ADR_RTC_3W)) = (0x00000000)
+#define DEF_RTC_3R() (REG32(ADR_RTC_3R)) = (0x00000000)
+#define DEF_RTC_4() (REG32(ADR_RTC_4)) = (0x00000000)
+#define DEF_D2_DMA_ADR_SRC() (REG32(ADR_D2_DMA_ADR_SRC)) = (0x00000000)
+#define DEF_D2_DMA_ADR_DST() (REG32(ADR_D2_DMA_ADR_DST)) = (0x00000000)
+#define DEF_D2_DMA_CTRL() (REG32(ADR_D2_DMA_CTRL)) = (0x000000aa)
+#define DEF_D2_DMA_INT() (REG32(ADR_D2_DMA_INT)) = (0x00000001)
+#define DEF_D2_DMA_FILL_CONST() (REG32(ADR_D2_DMA_FILL_CONST)) = (0x00000000)
+#define DEF_CONTROL() (REG32(ADR_CONTROL)) = (0x02700008)
+#define DEF_SDIO_WAKE_MODE() (REG32(ADR_SDIO_WAKE_MODE)) = (0x00000000)
+#define DEF_TX_FLOW_0() (REG32(ADR_TX_FLOW_0)) = (0x00000000)
+#define DEF_TX_FLOW_1() (REG32(ADR_TX_FLOW_1)) = (0x00000000)
+#define DEF_THREASHOLD() (REG32(ADR_THREASHOLD)) = (0x09000000)
+#define DEF_TXFID_INCREASE() (REG32(ADR_TXFID_INCREASE)) = (0x00000000)
+#define DEF_GLOBAL_SEQUENCE() (REG32(ADR_GLOBAL_SEQUENCE)) = (0x00000000)
+#define DEF_HCI_TX_RX_INFO_SIZE() (REG32(ADR_HCI_TX_RX_INFO_SIZE)) = (0x00040450)
+#define DEF_HCI_TX_INFO_CLEAR() (REG32(ADR_HCI_TX_INFO_CLEAR)) = (0x00000008)
+#define DEF_TX_ETHER_TYPE_0() (REG32(ADR_TX_ETHER_TYPE_0)) = (0x00000000)
+#define DEF_TX_ETHER_TYPE_1() (REG32(ADR_TX_ETHER_TYPE_1)) = (0x00000000)
+#define DEF_RX_ETHER_TYPE_0() (REG32(ADR_RX_ETHER_TYPE_0)) = (0x00000000)
+#define DEF_RX_ETHER_TYPE_1() (REG32(ADR_RX_ETHER_TYPE_1)) = (0x00000000)
+#define DEF_PACKET_COUNTER_INFO_0() (REG32(ADR_PACKET_COUNTER_INFO_0)) = (0x00000000)
+#define DEF_PACKET_COUNTER_INFO_1() (REG32(ADR_PACKET_COUNTER_INFO_1)) = (0x00000000)
+#define DEF_PACKET_COUNTER_INFO_2() (REG32(ADR_PACKET_COUNTER_INFO_2)) = (0x00000000)
+#define DEF_PACKET_COUNTER_INFO_3() (REG32(ADR_PACKET_COUNTER_INFO_3)) = (0x00000000)
+#define DEF_PACKET_COUNTER_INFO_4() (REG32(ADR_PACKET_COUNTER_INFO_4)) = (0x00000000)
+#define DEF_PACKET_COUNTER_INFO_5() (REG32(ADR_PACKET_COUNTER_INFO_5)) = (0x00000000)
+#define DEF_PACKET_COUNTER_INFO_6() (REG32(ADR_PACKET_COUNTER_INFO_6)) = (0x00000000)
+#define DEF_PACKET_COUNTER_INFO_7() (REG32(ADR_PACKET_COUNTER_INFO_7)) = (0x00000000)
+#define DEF_SDIO_TX_RX_FAIL_COUNTER_0() (REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_0)) = (0x00000000)
+#define DEF_SDIO_TX_RX_FAIL_COUNTER_1() (REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_1)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_0() (REG32(ADR_HCI_STATE_DEBUG_MODE_0)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_1() (REG32(ADR_HCI_STATE_DEBUG_MODE_1)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_2() (REG32(ADR_HCI_STATE_DEBUG_MODE_2)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_3() (REG32(ADR_HCI_STATE_DEBUG_MODE_3)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_4() (REG32(ADR_HCI_STATE_DEBUG_MODE_4)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_5() (REG32(ADR_HCI_STATE_DEBUG_MODE_5)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_6() (REG32(ADR_HCI_STATE_DEBUG_MODE_6)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_7() (REG32(ADR_HCI_STATE_DEBUG_MODE_7)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_8() (REG32(ADR_HCI_STATE_DEBUG_MODE_8)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_9() (REG32(ADR_HCI_STATE_DEBUG_MODE_9)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_10() (REG32(ADR_HCI_STATE_DEBUG_MODE_10)) = (0x00000000)
+#define DEF_CS_START_ADDR() (REG32(ADR_CS_START_ADDR)) = (0x00000000)
+#define DEF_CS_ADD_LEN() (REG32(ADR_CS_ADD_LEN)) = (0x00000000)
+#define DEF_CS_CMD() (REG32(ADR_CS_CMD)) = (0x00000000)
+#define DEF_CS_INI_BUF() (REG32(ADR_CS_INI_BUF)) = (0x00000000)
+#define DEF_CS_PSEUDO_BUF() (REG32(ADR_CS_PSEUDO_BUF)) = (0x00000000)
+#define DEF_CS_CHECK_SUM() (REG32(ADR_CS_CHECK_SUM)) = (0x00000000)
+#define DEF_RAND_EN() (REG32(ADR_RAND_EN)) = (0x00000000)
+#define DEF_RAND_NUM() (REG32(ADR_RAND_NUM)) = (0x00000000)
+#define DEF_MUL_OP1() (REG32(ADR_MUL_OP1)) = (0x00000000)
+#define DEF_MUL_OP2() (REG32(ADR_MUL_OP2)) = (0x00000000)
+#define DEF_MUL_ANS0() (REG32(ADR_MUL_ANS0)) = (0x00000000)
+#define DEF_MUL_ANS1() (REG32(ADR_MUL_ANS1)) = (0x00000000)
+#define DEF_DMA_RDATA() (REG32(ADR_DMA_RDATA)) = (0x00000000)
+#define DEF_DMA_WDATA() (REG32(ADR_DMA_WDATA)) = (0x00000000)
+#define DEF_DMA_LEN() (REG32(ADR_DMA_LEN)) = (0x00000000)
+#define DEF_DMA_CLR() (REG32(ADR_DMA_CLR)) = (0x00000000)
+#define DEF_NAV_DATA() (REG32(ADR_NAV_DATA)) = (0x00000000)
+#define DEF_CO_NAV() (REG32(ADR_CO_NAV)) = (0x00000000)
+#define DEF_SHA_DST_ADDR() (REG32(ADR_SHA_DST_ADDR)) = (0x00000000)
+#define DEF_SHA_SRC_ADDR() (REG32(ADR_SHA_SRC_ADDR)) = (0x00000000)
+#define DEF_SHA_SETTING() (REG32(ADR_SHA_SETTING)) = (0x00000002)
+#define DEF_EFUSE_CLK_FREQ() (REG32(ADR_EFUSE_CLK_FREQ)) = (0x610100d0)
+#define DEF_EFUSE_LDO_TIME() (REG32(ADR_EFUSE_LDO_TIME)) = (0x00020002)
+#define DEF_EFUSE_AHB_RDATA_0() (REG32(ADR_EFUSE_AHB_RDATA_0)) = (0x00000000)
+#define DEF_EFUSE_WDATA_0() (REG32(ADR_EFUSE_WDATA_0)) = (0x00000000)
+#define DEF_EFUSE_AHB_RDATA_1() (REG32(ADR_EFUSE_AHB_RDATA_1)) = (0x00000000)
+#define DEF_EFUSE_WDATA_1() (REG32(ADR_EFUSE_WDATA_1)) = (0x00000000)
+#define DEF_EFUSE_AHB_RDATA_2() (REG32(ADR_EFUSE_AHB_RDATA_2)) = (0x00000000)
+#define DEF_EFUSE_WDATA_2() (REG32(ADR_EFUSE_WDATA_2)) = (0x00000000)
+#define DEF_EFUSE_AHB_RDATA_3() (REG32(ADR_EFUSE_AHB_RDATA_3)) = (0x00000000)
+#define DEF_EFUSE_WDATA_3() (REG32(ADR_EFUSE_WDATA_3)) = (0x00000000)
+#define DEF_EFUSE_AHB_RDATA_4() (REG32(ADR_EFUSE_AHB_RDATA_4)) = (0x00000000)
+#define DEF_EFUSE_WDATA_4() (REG32(ADR_EFUSE_WDATA_4)) = (0x00000000)
+#define DEF_EFUSE_AHB_RDATA_5() (REG32(ADR_EFUSE_AHB_RDATA_5)) = (0x00000000)
+#define DEF_EFUSE_WDATA_5() (REG32(ADR_EFUSE_WDATA_5)) = (0x00000000)
+#define DEF_EFUSE_AHB_RDATA_6() (REG32(ADR_EFUSE_AHB_RDATA_6)) = (0x00000000)
+#define DEF_EFUSE_WDATA_6() (REG32(ADR_EFUSE_WDATA_6)) = (0x00000000)
+#define DEF_EFUSE_AHB_RDATA_7() (REG32(ADR_EFUSE_AHB_RDATA_7)) = (0x00000000)
+#define DEF_EFUSE_WDATA_7() (REG32(ADR_EFUSE_WDATA_7)) = (0x00000000)
+#define DEF_EFUSE_SPI_RD0_EN() (REG32(ADR_EFUSE_SPI_RD0_EN)) = (0x00000000)
+#define DEF_EFUSE_SPI_RD1_EN() (REG32(ADR_EFUSE_SPI_RD1_EN)) = (0x00000000)
+#define DEF_EFUSE_SPI_RD2_EN() (REG32(ADR_EFUSE_SPI_RD2_EN)) = (0x00000000)
+#define DEF_EFUSE_SPI_RD3_EN() (REG32(ADR_EFUSE_SPI_RD3_EN)) = (0x00000000)
+#define DEF_EFUSE_SPI_RD4_EN() (REG32(ADR_EFUSE_SPI_RD4_EN)) = (0x00000000)
+#define DEF_EFUSE_SPI_RD5_EN() (REG32(ADR_EFUSE_SPI_RD5_EN)) = (0x00000000)
+#define DEF_EFUSE_SPI_RD6_EN() (REG32(ADR_EFUSE_SPI_RD6_EN)) = (0x00000000)
+#define DEF_EFUSE_SPI_RD7_EN() (REG32(ADR_EFUSE_SPI_RD7_EN)) = (0x00000000)
+#define DEF_EFUSE_SPI_BUSY() (REG32(ADR_EFUSE_SPI_BUSY)) = (0x00000000)
+#define DEF_EFUSE_SPI_RDATA_0() (REG32(ADR_EFUSE_SPI_RDATA_0)) = (0x00000000)
+#define DEF_EFUSE_SPI_RDATA_1() (REG32(ADR_EFUSE_SPI_RDATA_1)) = (0x00000000)
+#define DEF_EFUSE_SPI_RDATA_2() (REG32(ADR_EFUSE_SPI_RDATA_2)) = (0x00000000)
+#define DEF_EFUSE_SPI_RDATA_3() (REG32(ADR_EFUSE_SPI_RDATA_3)) = (0x00000000)
+#define DEF_EFUSE_SPI_RDATA_4() (REG32(ADR_EFUSE_SPI_RDATA_4)) = (0x00000000)
+#define DEF_EFUSE_SPI_RDATA_5() (REG32(ADR_EFUSE_SPI_RDATA_5)) = (0x00000000)
+#define DEF_EFUSE_SPI_RDATA_6() (REG32(ADR_EFUSE_SPI_RDATA_6)) = (0x00000000)
+#define DEF_EFUSE_SPI_RDATA_7() (REG32(ADR_EFUSE_SPI_RDATA_7)) = (0x00000000)
+#define DEF_SMS4_CFG1() (REG32(ADR_SMS4_CFG1)) = (0x00000002)
+#define DEF_SMS4_CFG2() (REG32(ADR_SMS4_CFG2)) = (0x00000000)
+#define DEF_SMS4_MODE1() (REG32(ADR_SMS4_MODE1)) = (0x00000000)
+#define DEF_SMS4_TRIG() (REG32(ADR_SMS4_TRIG)) = (0x00000000)
+#define DEF_SMS4_STATUS1() (REG32(ADR_SMS4_STATUS1)) = (0x00000000)
+#define DEF_SMS4_STATUS2() (REG32(ADR_SMS4_STATUS2)) = (0x00000000)
+#define DEF_SMS4_DATA_IN0() (REG32(ADR_SMS4_DATA_IN0)) = (0x00000000)
+#define DEF_SMS4_DATA_IN1() (REG32(ADR_SMS4_DATA_IN1)) = (0x00000000)
+#define DEF_SMS4_DATA_IN2() (REG32(ADR_SMS4_DATA_IN2)) = (0x00000000)
+#define DEF_SMS4_DATA_IN3() (REG32(ADR_SMS4_DATA_IN3)) = (0x00000000)
+#define DEF_SMS4_DATA_OUT0() (REG32(ADR_SMS4_DATA_OUT0)) = (0x00000000)
+#define DEF_SMS4_DATA_OUT1() (REG32(ADR_SMS4_DATA_OUT1)) = (0x00000000)
+#define DEF_SMS4_DATA_OUT2() (REG32(ADR_SMS4_DATA_OUT2)) = (0x00000000)
+#define DEF_SMS4_DATA_OUT3() (REG32(ADR_SMS4_DATA_OUT3)) = (0x00000000)
+#define DEF_SMS4_KEY_0() (REG32(ADR_SMS4_KEY_0)) = (0x00000000)
+#define DEF_SMS4_KEY_1() (REG32(ADR_SMS4_KEY_1)) = (0x00000000)
+#define DEF_SMS4_KEY_2() (REG32(ADR_SMS4_KEY_2)) = (0x00000000)
+#define DEF_SMS4_KEY_3() (REG32(ADR_SMS4_KEY_3)) = (0x00000000)
+#define DEF_SMS4_MODE_IV0() (REG32(ADR_SMS4_MODE_IV0)) = (0x00000000)
+#define DEF_SMS4_MODE_IV1() (REG32(ADR_SMS4_MODE_IV1)) = (0x00000000)
+#define DEF_SMS4_MODE_IV2() (REG32(ADR_SMS4_MODE_IV2)) = (0x00000000)
+#define DEF_SMS4_MODE_IV3() (REG32(ADR_SMS4_MODE_IV3)) = (0x00000000)
+#define DEF_SMS4_OFB_ENC0() (REG32(ADR_SMS4_OFB_ENC0)) = (0x00000000)
+#define DEF_SMS4_OFB_ENC1() (REG32(ADR_SMS4_OFB_ENC1)) = (0x00000000)
+#define DEF_SMS4_OFB_ENC2() (REG32(ADR_SMS4_OFB_ENC2)) = (0x00000000)
+#define DEF_SMS4_OFB_ENC3() (REG32(ADR_SMS4_OFB_ENC3)) = (0x00000000)
+#define DEF_MRX_MCAST_TB0_0() (REG32(ADR_MRX_MCAST_TB0_0)) = (0x00000000)
+#define DEF_MRX_MCAST_TB0_1() (REG32(ADR_MRX_MCAST_TB0_1)) = (0x00000000)
+#define DEF_MRX_MCAST_MK0_0() (REG32(ADR_MRX_MCAST_MK0_0)) = (0x00000000)
+#define DEF_MRX_MCAST_MK0_1() (REG32(ADR_MRX_MCAST_MK0_1)) = (0x00000000)
+#define DEF_MRX_MCAST_CTRL0() (REG32(ADR_MRX_MCAST_CTRL0)) = (0x00000000)
+#define DEF_MRX_MCAST_TB1_0() (REG32(ADR_MRX_MCAST_TB1_0)) = (0x00000000)
+#define DEF_MRX_MCAST_TB1_1() (REG32(ADR_MRX_MCAST_TB1_1)) = (0x00000000)
+#define DEF_MRX_MCAST_MK1_0() (REG32(ADR_MRX_MCAST_MK1_0)) = (0x00000000)
+#define DEF_MRX_MCAST_MK1_1() (REG32(ADR_MRX_MCAST_MK1_1)) = (0x00000000)
+#define DEF_MRX_MCAST_CTRL1() (REG32(ADR_MRX_MCAST_CTRL1)) = (0x00000000)
+#define DEF_MRX_MCAST_TB2_0() (REG32(ADR_MRX_MCAST_TB2_0)) = (0x00000000)
+#define DEF_MRX_MCAST_TB2_1() (REG32(ADR_MRX_MCAST_TB2_1)) = (0x00000000)
+#define DEF_MRX_MCAST_MK2_0() (REG32(ADR_MRX_MCAST_MK2_0)) = (0x00000000)
+#define DEF_MRX_MCAST_MK2_1() (REG32(ADR_MRX_MCAST_MK2_1)) = (0x00000000)
+#define DEF_MRX_MCAST_CTRL2() (REG32(ADR_MRX_MCAST_CTRL2)) = (0x00000000)
+#define DEF_MRX_MCAST_TB3_0() (REG32(ADR_MRX_MCAST_TB3_0)) = (0x00000000)
+#define DEF_MRX_MCAST_TB3_1() (REG32(ADR_MRX_MCAST_TB3_1)) = (0x00000000)
+#define DEF_MRX_MCAST_MK3_0() (REG32(ADR_MRX_MCAST_MK3_0)) = (0x00000000)
+#define DEF_MRX_MCAST_MK3_1() (REG32(ADR_MRX_MCAST_MK3_1)) = (0x00000000)
+#define DEF_MRX_MCAST_CTRL3() (REG32(ADR_MRX_MCAST_CTRL3)) = (0x00000000)
+#define DEF_MRX_PHY_INFO() (REG32(ADR_MRX_PHY_INFO)) = (0x00000000)
+#define DEF_MRX_BA_DBG() (REG32(ADR_MRX_BA_DBG)) = (0x00000000)
+#define DEF_MRX_FLT_TB0() (REG32(ADR_MRX_FLT_TB0)) = (0x00003df5)
+#define DEF_MRX_FLT_TB1() (REG32(ADR_MRX_FLT_TB1)) = (0x000031f6)
+#define DEF_MRX_FLT_TB2() (REG32(ADR_MRX_FLT_TB2)) = (0x000035f9)
+#define DEF_MRX_FLT_TB3() (REG32(ADR_MRX_FLT_TB3)) = (0x000021c1)
+#define DEF_MRX_FLT_TB4() (REG32(ADR_MRX_FLT_TB4)) = (0x00004bf9)
+#define DEF_MRX_FLT_TB5() (REG32(ADR_MRX_FLT_TB5)) = (0x00004db1)
+#define DEF_MRX_FLT_TB6() (REG32(ADR_MRX_FLT_TB6)) = (0x000011fe)
+#define DEF_MRX_FLT_TB7() (REG32(ADR_MRX_FLT_TB7)) = (0x00000bfe)
+#define DEF_MRX_FLT_TB8() (REG32(ADR_MRX_FLT_TB8)) = (0x00000000)
+#define DEF_MRX_FLT_TB9() (REG32(ADR_MRX_FLT_TB9)) = (0x00000000)
+#define DEF_MRX_FLT_TB10() (REG32(ADR_MRX_FLT_TB10)) = (0x00000000)
+#define DEF_MRX_FLT_TB11() (REG32(ADR_MRX_FLT_TB11)) = (0x00000006)
+#define DEF_MRX_FLT_TB12() (REG32(ADR_MRX_FLT_TB12)) = (0x00000001)
+#define DEF_MRX_FLT_TB13() (REG32(ADR_MRX_FLT_TB13)) = (0x00000003)
+#define DEF_MRX_FLT_TB14() (REG32(ADR_MRX_FLT_TB14)) = (0x00000005)
+#define DEF_MRX_FLT_TB15() (REG32(ADR_MRX_FLT_TB15)) = (0x00000007)
+#define DEF_MRX_FLT_EN0() (REG32(ADR_MRX_FLT_EN0)) = (0x00002008)
+#define DEF_MRX_FLT_EN1() (REG32(ADR_MRX_FLT_EN1)) = (0x00001001)
+#define DEF_MRX_FLT_EN2() (REG32(ADR_MRX_FLT_EN2)) = (0x00000808)
+#define DEF_MRX_FLT_EN3() (REG32(ADR_MRX_FLT_EN3)) = (0x00001000)
+#define DEF_MRX_FLT_EN4() (REG32(ADR_MRX_FLT_EN4)) = (0x00002008)
+#define DEF_MRX_FLT_EN5() (REG32(ADR_MRX_FLT_EN5)) = (0x0000800e)
+#define DEF_MRX_FLT_EN6() (REG32(ADR_MRX_FLT_EN6)) = (0x00000838)
+#define DEF_MRX_FLT_EN7() (REG32(ADR_MRX_FLT_EN7)) = (0x00002008)
+#define DEF_MRX_FLT_EN8() (REG32(ADR_MRX_FLT_EN8)) = (0x00002008)
+#define DEF_MRX_LEN_FLT() (REG32(ADR_MRX_LEN_FLT)) = (0x00000000)
+#define DEF_RX_FLOW_DATA() (REG32(ADR_RX_FLOW_DATA)) = (0x00105034)
+#define DEF_RX_FLOW_MNG() (REG32(ADR_RX_FLOW_MNG)) = (0x00000004)
+#define DEF_RX_FLOW_CTRL() (REG32(ADR_RX_FLOW_CTRL)) = (0x00000004)
+#define DEF_RX_TIME_STAMP_CFG() (REG32(ADR_RX_TIME_STAMP_CFG)) = (0x00001c00)
+#define DEF_DBG_FF_FULL() (REG32(ADR_DBG_FF_FULL)) = (0x00000000)
+#define DEF_DBG_WFF_FULL() (REG32(ADR_DBG_WFF_FULL)) = (0x00000000)
+#define DEF_DBG_MB_FULL() (REG32(ADR_DBG_MB_FULL)) = (0x00000000)
+#define DEF_BA_CTRL() (REG32(ADR_BA_CTRL)) = (0x00000008)
+#define DEF_BA_TA_0() (REG32(ADR_BA_TA_0)) = (0x00000000)
+#define DEF_BA_TA_1() (REG32(ADR_BA_TA_1)) = (0x00000000)
+#define DEF_BA_TID() (REG32(ADR_BA_TID)) = (0x00000000)
+#define DEF_BA_ST_SEQ() (REG32(ADR_BA_ST_SEQ)) = (0x00000000)
+#define DEF_BA_SB0() (REG32(ADR_BA_SB0)) = (0x00000000)
+#define DEF_BA_SB1() (REG32(ADR_BA_SB1)) = (0x00000000)
+#define DEF_MRX_WATCH_DOG() (REG32(ADR_MRX_WATCH_DOG)) = (0x0000ffff)
+#define DEF_ACK_GEN_EN() (REG32(ADR_ACK_GEN_EN)) = (0x00000000)
+#define DEF_ACK_GEN_PARA() (REG32(ADR_ACK_GEN_PARA)) = (0x00000000)
+#define DEF_ACK_GEN_RA_0() (REG32(ADR_ACK_GEN_RA_0)) = (0x00000000)
+#define DEF_ACK_GEN_RA_1() (REG32(ADR_ACK_GEN_RA_1)) = (0x00000000)
+#define DEF_MIB_LEN_FAIL() (REG32(ADR_MIB_LEN_FAIL)) = (0x00000000)
+#define DEF_TRAP_HW_ID() (REG32(ADR_TRAP_HW_ID)) = (0x00000000)
+#define DEF_ID_IN_USE() (REG32(ADR_ID_IN_USE)) = (0x00000000)
+#define DEF_MRX_ERR() (REG32(ADR_MRX_ERR)) = (0x00000000)
+#define DEF_WSID0_TID0_RX_SEQ() (REG32(ADR_WSID0_TID0_RX_SEQ)) = (0x00000000)
+#define DEF_WSID0_TID1_RX_SEQ() (REG32(ADR_WSID0_TID1_RX_SEQ)) = (0x00000000)
+#define DEF_WSID0_TID2_RX_SEQ() (REG32(ADR_WSID0_TID2_RX_SEQ)) = (0x00000000)
+#define DEF_WSID0_TID3_RX_SEQ() (REG32(ADR_WSID0_TID3_RX_SEQ)) = (0x00000000)
+#define DEF_WSID0_TID4_RX_SEQ() (REG32(ADR_WSID0_TID4_RX_SEQ)) = (0x00000000)
+#define DEF_WSID0_TID5_RX_SEQ() (REG32(ADR_WSID0_TID5_RX_SEQ)) = (0x00000000)
+#define DEF_WSID0_TID6_RX_SEQ() (REG32(ADR_WSID0_TID6_RX_SEQ)) = (0x00000000)
+#define DEF_WSID0_TID7_RX_SEQ() (REG32(ADR_WSID0_TID7_RX_SEQ)) = (0x00000000)
+#define DEF_WSID1_TID0_RX_SEQ() (REG32(ADR_WSID1_TID0_RX_SEQ)) = (0x00000000)
+#define DEF_WSID1_TID1_RX_SEQ() (REG32(ADR_WSID1_TID1_RX_SEQ)) = (0x00000000)
+#define DEF_WSID1_TID2_RX_SEQ() (REG32(ADR_WSID1_TID2_RX_SEQ)) = (0x00000000)
+#define DEF_WSID1_TID3_RX_SEQ() (REG32(ADR_WSID1_TID3_RX_SEQ)) = (0x00000000)
+#define DEF_WSID1_TID4_RX_SEQ() (REG32(ADR_WSID1_TID4_RX_SEQ)) = (0x00000000)
+#define DEF_WSID1_TID5_RX_SEQ() (REG32(ADR_WSID1_TID5_RX_SEQ)) = (0x00000000)
+#define DEF_WSID1_TID6_RX_SEQ() (REG32(ADR_WSID1_TID6_RX_SEQ)) = (0x00000000)
+#define DEF_WSID1_TID7_RX_SEQ() (REG32(ADR_WSID1_TID7_RX_SEQ)) = (0x00000000)
+#define DEF_HDR_ADDR_SEL() (REG32(ADR_HDR_ADDR_SEL)) = (0x00003e79)
+#define DEF_FRAME_TYPE_CNTR_SET() (REG32(ADR_FRAME_TYPE_CNTR_SET)) = (0x00000000)
+#define DEF_PHY_INFO() (REG32(ADR_PHY_INFO)) = (0x00000000)
+#define DEF_AMPDU_SIG() (REG32(ADR_AMPDU_SIG)) = (0x0000004e)
+#define DEF_MIB_AMPDU() (REG32(ADR_MIB_AMPDU)) = (0x00000000)
+#define DEF_LEN_FLT() (REG32(ADR_LEN_FLT)) = (0x00000000)
+#define DEF_MIB_DELIMITER() (REG32(ADR_MIB_DELIMITER)) = (0x00000000)
+#define DEF_MTX_INT_STS() (REG32(ADR_MTX_INT_STS)) = (0x00000000)
+#define DEF_MTX_INT_EN() (REG32(ADR_MTX_INT_EN)) = (0x00000000)
+#define DEF_MTX_MISC_EN() (REG32(ADR_MTX_MISC_EN)) = (0x00c00c00)
+#define DEF_MTX_EDCCA_TOUT() (REG32(ADR_MTX_EDCCA_TOUT)) = (0x00000200)
+#define DEF_MTX_BCN_INT_STS() (REG32(ADR_MTX_BCN_INT_STS)) = (0x00000000)
+#define DEF_MTX_BCN_EN_INT() (REG32(ADR_MTX_BCN_EN_INT)) = (0x00000000)
+#define DEF_MTX_BCN_EN_MISC() (REG32(ADR_MTX_BCN_EN_MISC)) = (0x00000042)
+#define DEF_MTX_BCN_MISC() (REG32(ADR_MTX_BCN_MISC)) = (0x00000000)
+#define DEF_MTX_BCN_PRD() (REG32(ADR_MTX_BCN_PRD)) = (0x00000064)
+#define DEF_MTX_BCN_TSF_L() (REG32(ADR_MTX_BCN_TSF_L)) = (0x00000000)
+#define DEF_MTX_BCN_TSF_U() (REG32(ADR_MTX_BCN_TSF_U)) = (0x00000000)
+#define DEF_MTX_BCN_CFG0() (REG32(ADR_MTX_BCN_CFG0)) = (0x00000000)
+#define DEF_MTX_BCN_CFG1() (REG32(ADR_MTX_BCN_CFG1)) = (0x00000000)
+#define DEF_MTX_STATUS() (REG32(ADR_MTX_STATUS)) = (0x00000000)
+#define DEF_MTX_DBG_CTRL() (REG32(ADR_MTX_DBG_CTRL)) = (0x00000000)
+#define DEF_MTX_DBG_DAT0() (REG32(ADR_MTX_DBG_DAT0)) = (0x00000000)
+#define DEF_MTX_DBG_DAT1() (REG32(ADR_MTX_DBG_DAT1)) = (0x00000000)
+#define DEF_MTX_DBG_DAT2() (REG32(ADR_MTX_DBG_DAT2)) = (0x00000000)
+#define DEF_MTX_DUR_TOUT() (REG32(ADR_MTX_DUR_TOUT)) = (0x00002c2c)
+#define DEF_MTX_DUR_IFS() (REG32(ADR_MTX_DUR_IFS)) = (0x12d40a05)
+#define DEF_MTX_DUR_SIFS_G() (REG32(ADR_MTX_DUR_SIFS_G)) = (0x12c90100)
+#define DEF_MTX_DBG_DAT3() (REG32(ADR_MTX_DBG_DAT3)) = (0x00000000)
+#define DEF_MTX_NAV() (REG32(ADR_MTX_NAV)) = (0x00000000)
+#define DEF_MTX_MIB_WSID0() (REG32(ADR_MTX_MIB_WSID0)) = (0x00000000)
+#define DEF_MTX_MIB_WSID1() (REG32(ADR_MTX_MIB_WSID1)) = (0x00000000)
+#define DEF_MTX_DBG_DAT4() (REG32(ADR_MTX_DBG_DAT4)) = (0x00000000)
+#define DEF_TXQ0_MTX_Q_MISC_EN() (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (0x00000000)
+#define DEF_TXQ0_MTX_Q_AIFSN() (REG32(ADR_TXQ0_MTX_Q_AIFSN)) = (0x0000a502)
+#define DEF_TXQ0_MTX_Q_BKF_CNT() (REG32(ADR_TXQ0_MTX_Q_BKF_CNT)) = (0x00000000)
+#define DEF_TXQ0_MTX_Q_RC_LIMIT() (REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) = (0x00000407)
+#define DEF_TXQ0_MTX_Q_ID_MAP_L() (REG32(ADR_TXQ0_MTX_Q_ID_MAP_L)) = (0x00000000)
+#define DEF_TXQ0_MTX_Q_TXOP_CH_THD() (REG32(ADR_TXQ0_MTX_Q_TXOP_CH_THD)) = (0x00000000)
+#define DEF_TXQ0_MTX_Q_TXOP_OV_THD() (REG32(ADR_TXQ0_MTX_Q_TXOP_OV_THD)) = (0x00000000)
+#define DEF_TXQ1_MTX_Q_MISC_EN() (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (0x00000000)
+#define DEF_TXQ1_MTX_Q_AIFSN() (REG32(ADR_TXQ1_MTX_Q_AIFSN)) = (0x0000a502)
+#define DEF_TXQ1_MTX_Q_BKF_CNT() (REG32(ADR_TXQ1_MTX_Q_BKF_CNT)) = (0x00000000)
+#define DEF_TXQ1_MTX_Q_RC_LIMIT() (REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) = (0x00000407)
+#define DEF_TXQ1_MTX_Q_ID_MAP_L() (REG32(ADR_TXQ1_MTX_Q_ID_MAP_L)) = (0x00000000)
+#define DEF_TXQ1_MTX_Q_TXOP_CH_THD() (REG32(ADR_TXQ1_MTX_Q_TXOP_CH_THD)) = (0x00000000)
+#define DEF_TXQ1_MTX_Q_TXOP_OV_THD() (REG32(ADR_TXQ1_MTX_Q_TXOP_OV_THD)) = (0x00000000)
+#define DEF_TXQ2_MTX_Q_MISC_EN() (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (0x00000000)
+#define DEF_TXQ2_MTX_Q_AIFSN() (REG32(ADR_TXQ2_MTX_Q_AIFSN)) = (0x0000a502)
+#define DEF_TXQ2_MTX_Q_BKF_CNT() (REG32(ADR_TXQ2_MTX_Q_BKF_CNT)) = (0x00000000)
+#define DEF_TXQ2_MTX_Q_RC_LIMIT() (REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) = (0x00000407)
+#define DEF_TXQ2_MTX_Q_ID_MAP_L() (REG32(ADR_TXQ2_MTX_Q_ID_MAP_L)) = (0x00000000)
+#define DEF_TXQ2_MTX_Q_TXOP_CH_THD() (REG32(ADR_TXQ2_MTX_Q_TXOP_CH_THD)) = (0x00000000)
+#define DEF_TXQ2_MTX_Q_TXOP_OV_THD() (REG32(ADR_TXQ2_MTX_Q_TXOP_OV_THD)) = (0x00000000)
+#define DEF_TXQ3_MTX_Q_MISC_EN() (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (0x00000000)
+#define DEF_TXQ3_MTX_Q_AIFSN() (REG32(ADR_TXQ3_MTX_Q_AIFSN)) = (0x0000a502)
+#define DEF_TXQ3_MTX_Q_BKF_CNT() (REG32(ADR_TXQ3_MTX_Q_BKF_CNT)) = (0x00000000)
+#define DEF_TXQ3_MTX_Q_RC_LIMIT() (REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) = (0x00000407)
+#define DEF_TXQ3_MTX_Q_ID_MAP_L() (REG32(ADR_TXQ3_MTX_Q_ID_MAP_L)) = (0x00000000)
+#define DEF_TXQ3_MTX_Q_TXOP_CH_THD() (REG32(ADR_TXQ3_MTX_Q_TXOP_CH_THD)) = (0x00000000)
+#define DEF_TXQ3_MTX_Q_TXOP_OV_THD() (REG32(ADR_TXQ3_MTX_Q_TXOP_OV_THD)) = (0x00000000)
+#define DEF_TXQ4_MTX_Q_MISC_EN() (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (0x00000000)
+#define DEF_TXQ4_MTX_Q_AIFSN() (REG32(ADR_TXQ4_MTX_Q_AIFSN)) = (0x0000a502)
+#define DEF_TXQ4_MTX_Q_BKF_CNT() (REG32(ADR_TXQ4_MTX_Q_BKF_CNT)) = (0x00000000)
+#define DEF_TXQ4_MTX_Q_RC_LIMIT() (REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) = (0x00000407)
+#define DEF_TXQ4_MTX_Q_ID_MAP_L() (REG32(ADR_TXQ4_MTX_Q_ID_MAP_L)) = (0x00000000)
+#define DEF_TXQ4_MTX_Q_TXOP_CH_THD() (REG32(ADR_TXQ4_MTX_Q_TXOP_CH_THD)) = (0x00000000)
+#define DEF_TXQ4_MTX_Q_TXOP_OV_THD() (REG32(ADR_TXQ4_MTX_Q_TXOP_OV_THD)) = (0x00000000)
+#define DEF_WSID0() (REG32(ADR_WSID0)) = (0x00000000)
+#define DEF_PEER_MAC0_0() (REG32(ADR_PEER_MAC0_0)) = (0x00000000)
+#define DEF_PEER_MAC0_1() (REG32(ADR_PEER_MAC0_1)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_0() (REG32(ADR_TX_ACK_POLICY_0_0)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_0() (REG32(ADR_TX_SEQ_CTRL_0_0)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_1() (REG32(ADR_TX_ACK_POLICY_0_1)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_1() (REG32(ADR_TX_SEQ_CTRL_0_1)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_2() (REG32(ADR_TX_ACK_POLICY_0_2)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_2() (REG32(ADR_TX_SEQ_CTRL_0_2)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_3() (REG32(ADR_TX_ACK_POLICY_0_3)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_3() (REG32(ADR_TX_SEQ_CTRL_0_3)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_4() (REG32(ADR_TX_ACK_POLICY_0_4)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_4() (REG32(ADR_TX_SEQ_CTRL_0_4)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_5() (REG32(ADR_TX_ACK_POLICY_0_5)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_5() (REG32(ADR_TX_SEQ_CTRL_0_5)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_6() (REG32(ADR_TX_ACK_POLICY_0_6)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_6() (REG32(ADR_TX_SEQ_CTRL_0_6)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_7() (REG32(ADR_TX_ACK_POLICY_0_7)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_7() (REG32(ADR_TX_SEQ_CTRL_0_7)) = (0x00000000)
+#define DEF_WSID1() (REG32(ADR_WSID1)) = (0x00000000)
+#define DEF_PEER_MAC1_0() (REG32(ADR_PEER_MAC1_0)) = (0x00000000)
+#define DEF_PEER_MAC1_1() (REG32(ADR_PEER_MAC1_1)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_0() (REG32(ADR_TX_ACK_POLICY_1_0)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_0() (REG32(ADR_TX_SEQ_CTRL_1_0)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_1() (REG32(ADR_TX_ACK_POLICY_1_1)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_1() (REG32(ADR_TX_SEQ_CTRL_1_1)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_2() (REG32(ADR_TX_ACK_POLICY_1_2)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_2() (REG32(ADR_TX_SEQ_CTRL_1_2)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_3() (REG32(ADR_TX_ACK_POLICY_1_3)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_3() (REG32(ADR_TX_SEQ_CTRL_1_3)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_4() (REG32(ADR_TX_ACK_POLICY_1_4)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_4() (REG32(ADR_TX_SEQ_CTRL_1_4)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_5() (REG32(ADR_TX_ACK_POLICY_1_5)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_5() (REG32(ADR_TX_SEQ_CTRL_1_5)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_6() (REG32(ADR_TX_ACK_POLICY_1_6)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_6() (REG32(ADR_TX_SEQ_CTRL_1_6)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_7() (REG32(ADR_TX_ACK_POLICY_1_7)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_7() (REG32(ADR_TX_SEQ_CTRL_1_7)) = (0x00000000)
+#define DEF_INFO0() (REG32(ADR_INFO0)) = (0x00000000)
+#define DEF_INFO1() (REG32(ADR_INFO1)) = (0x00000100)
+#define DEF_INFO2() (REG32(ADR_INFO2)) = (0x00000200)
+#define DEF_INFO3() (REG32(ADR_INFO3)) = (0x00000300)
+#define DEF_INFO4() (REG32(ADR_INFO4)) = (0x00000140)
+#define DEF_INFO5() (REG32(ADR_INFO5)) = (0x00000240)
+#define DEF_INFO6() (REG32(ADR_INFO6)) = (0x00000340)
+#define DEF_INFO7() (REG32(ADR_INFO7)) = (0x00000001)
+#define DEF_INFO8() (REG32(ADR_INFO8)) = (0x00000101)
+#define DEF_INFO9() (REG32(ADR_INFO9)) = (0x00000201)
+#define DEF_INFO10() (REG32(ADR_INFO10)) = (0x00000301)
+#define DEF_INFO11() (REG32(ADR_INFO11)) = (0x00000401)
+#define DEF_INFO12() (REG32(ADR_INFO12)) = (0x00000501)
+#define DEF_INFO13() (REG32(ADR_INFO13)) = (0x00000601)
+#define DEF_INFO14() (REG32(ADR_INFO14)) = (0x00000701)
+#define DEF_INFO15() (REG32(ADR_INFO15)) = (0x00030002)
+#define DEF_INFO16() (REG32(ADR_INFO16)) = (0x00030102)
+#define DEF_INFO17() (REG32(ADR_INFO17)) = (0x00030202)
+#define DEF_INFO18() (REG32(ADR_INFO18)) = (0x00030302)
+#define DEF_INFO19() (REG32(ADR_INFO19)) = (0x00030402)
+#define DEF_INFO20() (REG32(ADR_INFO20)) = (0x00030502)
+#define DEF_INFO21() (REG32(ADR_INFO21)) = (0x00030602)
+#define DEF_INFO22() (REG32(ADR_INFO22)) = (0x00030702)
+#define DEF_INFO23() (REG32(ADR_INFO23)) = (0x00030082)
+#define DEF_INFO24() (REG32(ADR_INFO24)) = (0x00030182)
+#define DEF_INFO25() (REG32(ADR_INFO25)) = (0x00030282)
+#define DEF_INFO26() (REG32(ADR_INFO26)) = (0x00030382)
+#define DEF_INFO27() (REG32(ADR_INFO27)) = (0x00030482)
+#define DEF_INFO28() (REG32(ADR_INFO28)) = (0x00030582)
+#define DEF_INFO29() (REG32(ADR_INFO29)) = (0x00030682)
+#define DEF_INFO30() (REG32(ADR_INFO30)) = (0x00030782)
+#define DEF_INFO31() (REG32(ADR_INFO31)) = (0x00030042)
+#define DEF_INFO32() (REG32(ADR_INFO32)) = (0x00030142)
+#define DEF_INFO33() (REG32(ADR_INFO33)) = (0x00030242)
+#define DEF_INFO34() (REG32(ADR_INFO34)) = (0x00030342)
+#define DEF_INFO35() (REG32(ADR_INFO35)) = (0x00030442)
+#define DEF_INFO36() (REG32(ADR_INFO36)) = (0x00030542)
+#define DEF_INFO37() (REG32(ADR_INFO37)) = (0x00030642)
+#define DEF_INFO38() (REG32(ADR_INFO38)) = (0x00030742)
+#define DEF_INFO_MASK() (REG32(ADR_INFO_MASK)) = (0x00007fc7)
+#define DEF_INFO_RATE_OFFSET() (REG32(ADR_INFO_RATE_OFFSET)) = (0x00040000)
+#define DEF_INFO_IDX_ADDR() (REG32(ADR_INFO_IDX_ADDR)) = (0x00000000)
+#define DEF_INFO_LEN_ADDR() (REG32(ADR_INFO_LEN_ADDR)) = (0x00000000)
+#define DEF_IC_TIME_TAG_0() (REG32(ADR_IC_TIME_TAG_0)) = (0x00000000)
+#define DEF_IC_TIME_TAG_1() (REG32(ADR_IC_TIME_TAG_1)) = (0x00000000)
+#define DEF_PACKET_ID_ALLOCATION_PRIORITY() (REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) = (0x00000000)
+#define DEF_MAC_MODE() (REG32(ADR_MAC_MODE)) = (0x00000000)
+#define DEF_ALL_SOFTWARE_RESET() (REG32(ADR_ALL_SOFTWARE_RESET)) = (0x00000000)
+#define DEF_ENG_SOFTWARE_RESET() (REG32(ADR_ENG_SOFTWARE_RESET)) = (0x00000000)
+#define DEF_CSR_SOFTWARE_RESET() (REG32(ADR_CSR_SOFTWARE_RESET)) = (0x00000000)
+#define DEF_MAC_CLOCK_ENABLE() (REG32(ADR_MAC_CLOCK_ENABLE)) = (0x00003efb)
+#define DEF_MAC_ENGINE_CLOCK_ENABLE() (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (0x0000f07b)
+#define DEF_MAC_CSR_CLOCK_ENABLE() (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (0x0000ec02)
+#define DEF_GLBLE_SET() (REG32(ADR_GLBLE_SET)) = (0x000e5000)
+#define DEF_REASON_TRAP0() (REG32(ADR_REASON_TRAP0)) = (0x00000000)
+#define DEF_REASON_TRAP1() (REG32(ADR_REASON_TRAP1)) = (0x00000000)
+#define DEF_BSSID_0() (REG32(ADR_BSSID_0)) = (0x00000000)
+#define DEF_BSSID_1() (REG32(ADR_BSSID_1)) = (0x00000000)
+#define DEF_SCRT_STATE() (REG32(ADR_SCRT_STATE)) = (0x00000000)
+#define DEF_STA_MAC_0() (REG32(ADR_STA_MAC_0)) = (0x00000000)
+#define DEF_STA_MAC_1() (REG32(ADR_STA_MAC_1)) = (0x00000000)
+#define DEF_SCRT_SET() (REG32(ADR_SCRT_SET)) = (0x00000000)
+#define DEF_BTCX0() (REG32(ADR_BTCX0)) = (0x00000006)
+#define DEF_BTCX1() (REG32(ADR_BTCX1)) = (0x00000000)
+#define DEF_SWITCH_CTL() (REG32(ADR_SWITCH_CTL)) = (0x00000000)
+#define DEF_MIB_EN() (REG32(ADR_MIB_EN)) = (0x00000000)
+#define DEF_MTX_WSID0_SUCC() (REG32(ADR_MTX_WSID0_SUCC)) = (0x00000000)
+#define DEF_MTX_WSID0_FRM() (REG32(ADR_MTX_WSID0_FRM)) = (0x00000000)
+#define DEF_MTX_WSID0_RETRY() (REG32(ADR_MTX_WSID0_RETRY)) = (0x00000000)
+#define DEF_MTX_WSID0_TOTAL() (REG32(ADR_MTX_WSID0_TOTAL)) = (0x00000000)
+#define DEF_MTX_GROUP() (REG32(ADR_MTX_GROUP)) = (0x00000000)
+#define DEF_MTX_FAIL() (REG32(ADR_MTX_FAIL)) = (0x00000000)
+#define DEF_MTX_RETRY() (REG32(ADR_MTX_RETRY)) = (0x00000000)
+#define DEF_MTX_MULTI_RETRY() (REG32(ADR_MTX_MULTI_RETRY)) = (0x00000000)
+#define DEF_MTX_RTS_SUCCESS() (REG32(ADR_MTX_RTS_SUCCESS)) = (0x00000000)
+#define DEF_MTX_RTS_FAIL() (REG32(ADR_MTX_RTS_FAIL)) = (0x00000000)
+#define DEF_MTX_ACK_FAIL() (REG32(ADR_MTX_ACK_FAIL)) = (0x00000000)
+#define DEF_MTX_FRM() (REG32(ADR_MTX_FRM)) = (0x00000000)
+#define DEF_MTX_ACK_TX() (REG32(ADR_MTX_ACK_TX)) = (0x00000000)
+#define DEF_MTX_CTS_TX() (REG32(ADR_MTX_CTS_TX)) = (0x00000000)
+#define DEF_MRX_DUP_FRM() (REG32(ADR_MRX_DUP_FRM)) = (0x00000000)
+#define DEF_MRX_FRG_FRM() (REG32(ADR_MRX_FRG_FRM)) = (0x00000000)
+#define DEF_MRX_GROUP_FRM() (REG32(ADR_MRX_GROUP_FRM)) = (0x00000000)
+#define DEF_MRX_FCS_ERR() (REG32(ADR_MRX_FCS_ERR)) = (0x00000000)
+#define DEF_MRX_FCS_SUCC() (REG32(ADR_MRX_FCS_SUCC)) = (0x00000000)
+#define DEF_MRX_MISS() (REG32(ADR_MRX_MISS)) = (0x00000000)
+#define DEF_MRX_ALC_FAIL() (REG32(ADR_MRX_ALC_FAIL)) = (0x00000000)
+#define DEF_MRX_DAT_NTF() (REG32(ADR_MRX_DAT_NTF)) = (0x00000000)
+#define DEF_MRX_RTS_NTF() (REG32(ADR_MRX_RTS_NTF)) = (0x00000000)
+#define DEF_MRX_CTS_NTF() (REG32(ADR_MRX_CTS_NTF)) = (0x00000000)
+#define DEF_MRX_ACK_NTF() (REG32(ADR_MRX_ACK_NTF)) = (0x00000000)
+#define DEF_MRX_BA_NTF() (REG32(ADR_MRX_BA_NTF)) = (0x00000000)
+#define DEF_MRX_DATA_NTF() (REG32(ADR_MRX_DATA_NTF)) = (0x00000000)
+#define DEF_MRX_MNG_NTF() (REG32(ADR_MRX_MNG_NTF)) = (0x00000000)
+#define DEF_MRX_DAT_CRC_NTF() (REG32(ADR_MRX_DAT_CRC_NTF)) = (0x00000000)
+#define DEF_MRX_BAR_NTF() (REG32(ADR_MRX_BAR_NTF)) = (0x00000000)
+#define DEF_MRX_MB_MISS() (REG32(ADR_MRX_MB_MISS)) = (0x00000000)
+#define DEF_MRX_NIDLE_MISS() (REG32(ADR_MRX_NIDLE_MISS)) = (0x00000000)
+#define DEF_MRX_CSR_NTF() (REG32(ADR_MRX_CSR_NTF)) = (0x00000000)
+#define DEF_DBG_Q0_FRM_SUCCESS() (REG32(ADR_DBG_Q0_FRM_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q0_FRM_FAIL() (REG32(ADR_DBG_Q0_FRM_FAIL)) = (0x00000000)
+#define DEF_DBG_Q0_ACK_SUCCESS() (REG32(ADR_DBG_Q0_ACK_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q0_ACK_FAIL() (REG32(ADR_DBG_Q0_ACK_FAIL)) = (0x00000000)
+#define DEF_DBG_Q1_FRM_SUCCESS() (REG32(ADR_DBG_Q1_FRM_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q1_FRM_FAIL() (REG32(ADR_DBG_Q1_FRM_FAIL)) = (0x00000000)
+#define DEF_DBG_Q1_ACK_SUCCESS() (REG32(ADR_DBG_Q1_ACK_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q1_ACK_FAIL() (REG32(ADR_DBG_Q1_ACK_FAIL)) = (0x00000000)
+#define DEF_DBG_Q2_FRM_SUCCESS() (REG32(ADR_DBG_Q2_FRM_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q2_FRM_FAIL() (REG32(ADR_DBG_Q2_FRM_FAIL)) = (0x00000000)
+#define DEF_DBG_Q2_ACK_SUCCESS() (REG32(ADR_DBG_Q2_ACK_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q2_ACK_FAIL() (REG32(ADR_DBG_Q2_ACK_FAIL)) = (0x00000000)
+#define DEF_DBG_Q3_FRM_SUCCESS() (REG32(ADR_DBG_Q3_FRM_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q3_FRM_FAIL() (REG32(ADR_DBG_Q3_FRM_FAIL)) = (0x00000000)
+#define DEF_DBG_Q3_ACK_SUCCESS() (REG32(ADR_DBG_Q3_ACK_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q3_ACK_FAIL() (REG32(ADR_DBG_Q3_ACK_FAIL)) = (0x00000000)
+#define DEF_MIB_SCRT_TKIP0() (REG32(ADR_MIB_SCRT_TKIP0)) = (0x00000000)
+#define DEF_MIB_SCRT_TKIP1() (REG32(ADR_MIB_SCRT_TKIP1)) = (0x00000000)
+#define DEF_MIB_SCRT_TKIP2() (REG32(ADR_MIB_SCRT_TKIP2)) = (0x00000000)
+#define DEF_MIB_SCRT_CCMP0() (REG32(ADR_MIB_SCRT_CCMP0)) = (0x00000000)
+#define DEF_MIB_SCRT_CCMP1() (REG32(ADR_MIB_SCRT_CCMP1)) = (0x00000000)
+#define DEF_DBG_LEN_CRC_FAIL() (REG32(ADR_DBG_LEN_CRC_FAIL)) = (0x00000000)
+#define DEF_DBG_LEN_ALC_FAIL() (REG32(ADR_DBG_LEN_ALC_FAIL)) = (0x00000000)
+#define DEF_DBG_AMPDU_PASS() (REG32(ADR_DBG_AMPDU_PASS)) = (0x00000000)
+#define DEF_DBG_AMPDU_FAIL() (REG32(ADR_DBG_AMPDU_FAIL)) = (0x00000000)
+#define DEF_ID_ALC_FAIL1() (REG32(ADR_ID_ALC_FAIL1)) = (0x00000000)
+#define DEF_ID_ALC_FAIL2() (REG32(ADR_ID_ALC_FAIL2)) = (0x00000000)
+#define DEF_CBR_HARD_WIRE_PIN_REGISTER() (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (0x00004000)
+#define DEF_CBR_MANUAL_ENABLE_REGISTER() (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (0x00001fc0)
+#define DEF_CBR_LDO_REGISTER() (REG32(ADR_CBR_LDO_REGISTER)) = (0x2496db1b)
+#define DEF_CBR_ABB_REGISTER_1() (REG32(ADR_CBR_ABB_REGISTER_1)) = (0x151558dd)
+#define DEF_CBR_ABB_REGISTER_2() (REG32(ADR_CBR_ABB_REGISTER_2)) = (0x01011a88)
+#define DEF_CBR_TX_FE_REGISTER() (REG32(ADR_CBR_TX_FE_REGISTER)) = (0x3cbe84fe)
+#define DEF_CBR_RX_FE_REGISTER_1() (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (0x00657579)
+#define DEF_CBR_RX_FE_GAIN_DECODER_REGISTER_1() (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (0x000103a7)
+#define DEF_CBR_RX_FE_GAIN_DECODER_REGISTER_2() (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (0x000103a6)
+#define DEF_CBR_RX_FE_GAIN_DECODER_REGISTER_3() (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (0x00012001)
+#define DEF_CBR_RX_FE_GAIN_DECODER_REGISTER_4() (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (0x00036000)
+#define DEF_CBR_RX_FSM_REGISTER() (REG32(ADR_CBR_RX_FSM_REGISTER)) = (0x00000ca8)
+#define DEF_CBR_RX_ADC_REGISTER() (REG32(ADR_CBR_RX_ADC_REGISTER)) = (0x002a0224)
+#define DEF_CBR_TX_DAC_REGISTER() (REG32(ADR_CBR_TX_DAC_REGISTER)) = (0x00002655)
+#define DEF_CBR_SX_ENABLE_RGISTER() (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (0x0000647c)
+#define DEF_CBR_SYN_RGISTER_1() (REG32(ADR_CBR_SYN_RGISTER_1)) = (0xaa800000)
+#define DEF_CBR_SYN_RGISTER_2() (REG32(ADR_CBR_SYN_RGISTER_2)) = (0x00550800)
+#define DEF_CBR_SYN_PFD_CHP() (REG32(ADR_CBR_SYN_PFD_CHP)) = (0x07c0894a)
+#define DEF_CBR_SYN_VCO_LOBF() (REG32(ADR_CBR_SYN_VCO_LOBF)) = (0xfcccca27)
+#define DEF_CBR_SYN_DIV_SDM_XOSC() (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (0x2773c93c)
+#define DEF_CBR_SYN_LCK1() (REG32(ADR_CBR_SYN_LCK1)) = (0x00000a7c)
+#define DEF_CBR_SYN_LCK2() (REG32(ADR_CBR_SYN_LCK2)) = (0x01c67ff4)
+#define DEF_CBR_DPLL_VCO_REGISTER() (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (0x00103014)
+#define DEF_CBR_DPLL_CP_PFD_REGISTER() (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (0x0001848c)
+#define DEF_CBR_DPLL_DIVIDER_REGISTER() (REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) = (0x034061e0)
+#define DEF_CBR_DCOC_IDAC_REGISTER1() (REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) = (0x00820820)
+#define DEF_CBR_DCOC_IDAC_REGISTER2() (REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) = (0x00820820)
+#define DEF_CBR_DCOC_IDAC_REGISTER3() (REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) = (0x00820820)
+#define DEF_CBR_DCOC_IDAC_REGISTER4() (REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) = (0x00820820)
+#define DEF_CBR_DCOC_IDAC_REGISTER5() (REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) = (0x00820820)
+#define DEF_CBR_DCOC_IDAC_REGISTER6() (REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) = (0x00820820)
+#define DEF_CBR_DCOC_IDAC_REGISTER7() (REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) = (0x00820820)
+#define DEF_CBR_DCOC_IDAC_REGISTER8() (REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) = (0x00820820)
+#define DEF_CBR_RCAL_REGISTER() (REG32(ADR_CBR_RCAL_REGISTER)) = (0x00004080)
+#define DEF_CBR_MANUAL_REGISTER() (REG32(ADR_CBR_MANUAL_REGISTER)) = (0x00003e7e)
+#define DEF_CBR_TRX_DUMMY_REGISTER() (REG32(ADR_CBR_TRX_DUMMY_REGISTER)) = (0xaaaaaaaa)
+#define DEF_CBR_SX_DUMMY_REGISTER() (REG32(ADR_CBR_SX_DUMMY_REGISTER)) = (0xaaaaaaaa)
+#define DEF_CBR_RG_PKT_GEN_0() (REG32(ADR_CBR_RG_PKT_GEN_0)) = (0x00000000)
+#define DEF_CBR_RG_PKT_GEN_1() (REG32(ADR_CBR_RG_PKT_GEN_1)) = (0x00000000)
+#define DEF_CBR_RG_PKT_GEN_2() (REG32(ADR_CBR_RG_PKT_GEN_2)) = (0x00000000)
+#define DEF_CBR_RG_INTEGRATION() (REG32(ADR_CBR_RG_INTEGRATION)) = (0x00000000)
+#define DEF_CBR_RG_PKT_GEN_TXCNT() (REG32(ADR_CBR_RG_PKT_GEN_TXCNT)) = (0x00000000)
+#define DEF_CBR_PATTERN_GEN() (REG32(ADR_CBR_PATTERN_GEN)) = (0xff000000)
+#define DEF_MB_CPU_INT() (REG32(ADR_MB_CPU_INT)) = (0x00000000)
+#define DEF_CPU_ID_TB0() (REG32(ADR_CPU_ID_TB0)) = (0x00000000)
+#define DEF_CPU_ID_TB1() (REG32(ADR_CPU_ID_TB1)) = (0x00000000)
+#define DEF_CH0_TRIG_1() (REG32(ADR_CH0_TRIG_1)) = (0x00000000)
+#define DEF_CH0_TRIG_0() (REG32(ADR_CH0_TRIG_0)) = (0x00000000)
+#define DEF_CH0_PRI_TRIG() (REG32(ADR_CH0_PRI_TRIG)) = (0x00000000)
+#define DEF_MCU_STATUS() (REG32(ADR_MCU_STATUS)) = (0x00000000)
+#define DEF_RD_IN_FFCNT1() (REG32(ADR_RD_IN_FFCNT1)) = (0x00000000)
+#define DEF_RD_IN_FFCNT2() (REG32(ADR_RD_IN_FFCNT2)) = (0x00000000)
+#define DEF_RD_FFIN_FULL() (REG32(ADR_RD_FFIN_FULL)) = (0x00000000)
+#define DEF_MBOX_HALT_CFG() (REG32(ADR_MBOX_HALT_CFG)) = (0x00000000)
+#define DEF_MB_DBG_CFG1() (REG32(ADR_MB_DBG_CFG1)) = (0x00080000)
+#define DEF_MB_DBG_CFG2() (REG32(ADR_MB_DBG_CFG2)) = (0x00000000)
+#define DEF_MB_DBG_CFG3() (REG32(ADR_MB_DBG_CFG3)) = (0x00000000)
+#define DEF_MB_DBG_CFG4() (REG32(ADR_MB_DBG_CFG4)) = (0xffffffff)
+#define DEF_MB_OUT_QUEUE_CFG() (REG32(ADR_MB_OUT_QUEUE_CFG)) = (0x00000002)
+#define DEF_MB_OUT_QUEUE_FLUSH() (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (0x00000000)
+#define DEF_RD_FFOUT_CNT1() (REG32(ADR_RD_FFOUT_CNT1)) = (0x00000000)
+#define DEF_RD_FFOUT_CNT2() (REG32(ADR_RD_FFOUT_CNT2)) = (0x00000000)
+#define DEF_RD_FFOUT_CNT3() (REG32(ADR_RD_FFOUT_CNT3)) = (0x00000000)
+#define DEF_RD_FFOUT_FULL() (REG32(ADR_RD_FFOUT_FULL)) = (0x00000000)
+#define DEF_MB_THRESHOLD6() (REG32(ADR_MB_THRESHOLD6)) = (0x00000000)
+#define DEF_MB_THRESHOLD7() (REG32(ADR_MB_THRESHOLD7)) = (0x00000000)
+#define DEF_MB_THRESHOLD8() (REG32(ADR_MB_THRESHOLD8)) = (0x00000000)
+#define DEF_MB_THRESHOLD9() (REG32(ADR_MB_THRESHOLD9)) = (0x00000000)
+#define DEF_MB_THRESHOLD10() (REG32(ADR_MB_THRESHOLD10)) = (0x00000000)
+#define DEF_MB_TRASH_CFG() (REG32(ADR_MB_TRASH_CFG)) = (0x01000001)
+#define DEF_MB_IN_FF_FLUSH() (REG32(ADR_MB_IN_FF_FLUSH)) = (0x00000000)
+#define DEF_CPU_ID_TB2() (REG32(ADR_CPU_ID_TB2)) = (0x00000000)
+#define DEF_CPU_ID_TB3() (REG32(ADR_CPU_ID_TB3)) = (0x00000000)
+#define DEF_PHY_IQ_LOG_CFG0() (REG32(ADR_PHY_IQ_LOG_CFG0)) = (0x00000000)
+#define DEF_PHY_IQ_LOG_CFG1() (REG32(ADR_PHY_IQ_LOG_CFG1)) = (0x00000000)
+#define DEF_PHY_IQ_LOG_LEN() (REG32(ADR_PHY_IQ_LOG_LEN)) = (0x00001000)
+#define DEF_PHY_IQ_LOG_PTR() (REG32(ADR_PHY_IQ_LOG_PTR)) = (0x00000000)
+#define DEF_WR_ALC() (REG32(ADR_WR_ALC)) = (0x00000000)
+#define DEF_GETID() (REG32(ADR_GETID)) = (0x00000000)
+#define DEF_CH_STA_PRI() (REG32(ADR_CH_STA_PRI)) = (0x00000213)
+#define DEF_RD_ID0() (REG32(ADR_RD_ID0)) = (0x00000000)
+#define DEF_RD_ID1() (REG32(ADR_RD_ID1)) = (0x00000000)
+#define DEF_IMD_CFG() (REG32(ADR_IMD_CFG)) = (0x00000000)
+#define DEF_IMD_STA() (REG32(ADR_IMD_STA)) = (0x00000000)
+#define DEF_ALC_STA() (REG32(ADR_ALC_STA)) = (0x01000000)
+#define DEF_TRX_ID_COUNT() (REG32(ADR_TRX_ID_COUNT)) = (0x00000000)
+#define DEF_TRX_ID_THRESHOLD() (REG32(ADR_TRX_ID_THRESHOLD)) = (0x01ee3c3c)
+#define DEF_TX_ID0() (REG32(ADR_TX_ID0)) = (0x00000000)
+#define DEF_TX_ID1() (REG32(ADR_TX_ID1)) = (0x00000000)
+#define DEF_RX_ID0() (REG32(ADR_RX_ID0)) = (0x00000000)
+#define DEF_RX_ID1() (REG32(ADR_RX_ID1)) = (0x00000000)
+#define DEF_RTN_STA() (REG32(ADR_RTN_STA)) = (0x00000001)
+#define DEF_ID_LEN_THREADSHOLD1() (REG32(ADR_ID_LEN_THREADSHOLD1)) = (0x000f0641)
+#define DEF_ID_LEN_THREADSHOLD2() (REG32(ADR_ID_LEN_THREADSHOLD2)) = (0x00000000)
+#define DEF_CH_ARB_PRI() (REG32(ADR_CH_ARB_PRI)) = (0x00031201)
+#define DEF_TX_ID_REMAIN_STATUS() (REG32(ADR_TX_ID_REMAIN_STATUS)) = (0x00000000)
+#define DEF_ID_INFO_STA() (REG32(ADR_ID_INFO_STA)) = (0x00000100)
+#define DEF_TX_LIMIT_INTR() (REG32(ADR_TX_LIMIT_INTR)) = (0x00000000)
+#define DEF_TX_ID_ALL_INFO() (REG32(ADR_TX_ID_ALL_INFO)) = (0x00000000)
+#define DEF_RD_ID2() (REG32(ADR_RD_ID2)) = (0x00000000)
+#define DEF_RD_ID3() (REG32(ADR_RD_ID3)) = (0x00000000)
+#define DEF_TX_ID2() (REG32(ADR_TX_ID2)) = (0x00000000)
+#define DEF_TX_ID3() (REG32(ADR_TX_ID3)) = (0x00000000)
+#define DEF_RX_ID2() (REG32(ADR_RX_ID2)) = (0x00000000)
+#define DEF_RX_ID3() (REG32(ADR_RX_ID3)) = (0x00000000)
+#define DEF_TX_ID_ALL_INFO2() (REG32(ADR_TX_ID_ALL_INFO2)) = (0x00000000)
+#define DEF_TX_ID_ALL_INFO_A() (REG32(ADR_TX_ID_ALL_INFO_A)) = (0x00000000)
+#define DEF_TX_ID_ALL_INFO_B() (REG32(ADR_TX_ID_ALL_INFO_B)) = (0x00000000)
+#define DEF_TX_ID_REMAIN_STATUS2() (REG32(ADR_TX_ID_REMAIN_STATUS2)) = (0x01000100)
+#define DEF_ALC_ID_INFO() (REG32(ADR_ALC_ID_INFO)) = (0x00000000)
+#define DEF_ALC_ID_INF1() (REG32(ADR_ALC_ID_INF1)) = (0x00000000)
+#define DEF_PHY_EN_0() (REG32(ADR_PHY_EN_0)) = (0x00000014)
+#define DEF_PHY_EN_1() (REG32(ADR_PHY_EN_1)) = (0x00000000)
+#define DEF_SVN_VERSION_REG() (REG32(ADR_SVN_VERSION_REG)) = (0x00000000)
+#define DEF_PHY_PKT_GEN_0() (REG32(ADR_PHY_PKT_GEN_0)) = (0x00000064)
+#define DEF_PHY_PKT_GEN_1() (REG32(ADR_PHY_PKT_GEN_1)) = (0x00000fff)
+#define DEF_PHY_PKT_GEN_2() (REG32(ADR_PHY_PKT_GEN_2)) = (0x00000003)
+#define DEF_PHY_PKT_GEN_3() (REG32(ADR_PHY_PKT_GEN_3)) = (0x005a0220)
+#define DEF_PHY_PKT_GEN_4() (REG32(ADR_PHY_PKT_GEN_4)) = (0x00000001)
+#define DEF_PHY_REG_00() (REG32(ADR_PHY_REG_00)) = (0x10000000)
+#define DEF_PHY_REG_01() (REG32(ADR_PHY_REG_01)) = (0x00000000)
+#define DEF_PHY_REG_02_AGC() (REG32(ADR_PHY_REG_02_AGC)) = (0x80046771)
+#define DEF_PHY_REG_03_AGC() (REG32(ADR_PHY_REG_03_AGC)) = (0x1f300f6f)
+#define DEF_PHY_REG_04_AGC() (REG32(ADR_PHY_REG_04_AGC)) = (0x663f36d0)
+#define DEF_PHY_REG_05_AGC() (REG32(ADR_PHY_REG_05_AGC)) = (0x106c0000)
+#define DEF_PHY_REG_06_11B_DAGC() (REG32(ADR_PHY_REG_06_11B_DAGC)) = (0x01603fff)
+#define DEF_PHY_REG_07_11B_DAGC() (REG32(ADR_PHY_REG_07_11B_DAGC)) = (0x00600808)
+#define DEF_PHY_REG_08_11GN_DAGC() (REG32(ADR_PHY_REG_08_11GN_DAGC)) = (0xff000160)
+#define DEF_PHY_REG_09_11GN_DAGC() (REG32(ADR_PHY_REG_09_11GN_DAGC)) = (0x00080840)
+#define DEF_PHY_READ_REG_00_DIG_PWR() (REG32(ADR_PHY_READ_REG_00_DIG_PWR)) = (0x00000000)
+#define DEF_PHY_READ_REG_01_RF_GAIN_PWR() (REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) = (0x00000000)
+#define DEF_PHY_READ_REG_02_RF_GAIN_PWR() (REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) = (0x00000000)
+#define DEF_PHY_READ_REG_03_RF_GAIN_PWR() (REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) = (0x00000000)
+#define DEF_PHY_REG_10_TX_DES() (REG32(ADR_PHY_REG_10_TX_DES)) = (0x00010405)
+#define DEF_PHY_REG_11_TX_DES() (REG32(ADR_PHY_REG_11_TX_DES)) = (0x06090813)
+#define DEF_PHY_REG_12_TX_DES() (REG32(ADR_PHY_REG_12_TX_DES)) = (0x12070000)
+#define DEF_PHY_REG_13_RX_DES() (REG32(ADR_PHY_REG_13_RX_DES)) = (0x01000405)
+#define DEF_PHY_REG_14_RX_DES() (REG32(ADR_PHY_REG_14_RX_DES)) = (0x06090813)
+#define DEF_PHY_REG_15_RX_DES() (REG32(ADR_PHY_REG_15_RX_DES)) = (0x12010000)
+#define DEF_PHY_REG_16_TX_DES_EXCP() (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (0x00000000)
+#define DEF_PHY_REG_17_TX_DES_EXCP() (REG32(ADR_PHY_REG_17_TX_DES_EXCP)) = (0x10110000)
+#define DEF_PHY_REG_18_RSSI_SNR() (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (0x00fc000f)
+#define DEF_PHY_REG_19_DAC_MANUAL() (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (0x00000000)
+#define DEF_PHY_REG_20_MRX_CNT() (REG32(ADR_PHY_REG_20_MRX_CNT)) = (0x00000000)
+#define DEF_PHY_REG_21_TRX_RAMP() (REG32(ADR_PHY_REG_21_TRX_RAMP)) = (0x3c012801)
+#define DEF_PHY_REG_22_TRX_RAMP() (REG32(ADR_PHY_REG_22_TRX_RAMP)) = (0x24243724)
+#define DEF_PHY_REG_23_ANT() (REG32(ADR_PHY_REG_23_ANT)) = (0x00000011)
+#define DEF_PHY_REG_24_MTX_LEN_CNT() (REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) = (0x1fff0000)
+#define DEF_PHY_REG_25_MTX_LEN_CNT() (REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) = (0x1fff0000)
+#define DEF_PHY_REG_26_MRX_LEN_CNT() (REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) = (0x1fff0000)
+#define DEF_PHY_REG_27_MRX_LEN_CNT() (REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) = (0x1fff0000)
+#define DEF_PHY_READ_REG_04() (REG32(ADR_PHY_READ_REG_04)) = (0x00000000)
+#define DEF_PHY_READ_REG_05() (REG32(ADR_PHY_READ_REG_05)) = (0x00000000)
+#define DEF_PHY_REG_28_BIST() (REG32(ADR_PHY_REG_28_BIST)) = (0x0000fe3e)
+#define DEF_PHY_READ_REG_06_BIST() (REG32(ADR_PHY_READ_REG_06_BIST)) = (0x00000000)
+#define DEF_PHY_READ_REG_07_BIST() (REG32(ADR_PHY_READ_REG_07_BIST)) = (0x00000000)
+#define DEF_PHY_REG_29_MTRX_MAC() (REG32(ADR_PHY_REG_29_MTRX_MAC)) = (0xffffffff)
+#define DEF_PHY_READ_REG_08_MTRX_MAC() (REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) = (0x00000000)
+#define DEF_PHY_READ_REG_09_MTRX_MAC() (REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) = (0x00000000)
+#define DEF_PHY_REG_30_TX_UP_FIL() (REG32(ADR_PHY_REG_30_TX_UP_FIL)) = (0x0ead04f5)
+#define DEF_PHY_REG_31_TX_UP_FIL() (REG32(ADR_PHY_REG_31_TX_UP_FIL)) = (0x0fd60080)
+#define DEF_PHY_REG_32_TX_UP_FIL() (REG32(ADR_PHY_REG_32_TX_UP_FIL)) = (0x00000009)
+#define DEF_PHY_READ_TBUS() (REG32(ADR_PHY_READ_TBUS)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_00() (REG32(ADR_TX_11B_FIL_COEF_00)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_01() (REG32(ADR_TX_11B_FIL_COEF_01)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_02() (REG32(ADR_TX_11B_FIL_COEF_02)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_03() (REG32(ADR_TX_11B_FIL_COEF_03)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_04() (REG32(ADR_TX_11B_FIL_COEF_04)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_05() (REG32(ADR_TX_11B_FIL_COEF_05)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_06() (REG32(ADR_TX_11B_FIL_COEF_06)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_07() (REG32(ADR_TX_11B_FIL_COEF_07)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_08() (REG32(ADR_TX_11B_FIL_COEF_08)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_09() (REG32(ADR_TX_11B_FIL_COEF_09)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_10() (REG32(ADR_TX_11B_FIL_COEF_10)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_11() (REG32(ADR_TX_11B_FIL_COEF_11)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_12() (REG32(ADR_TX_11B_FIL_COEF_12)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_13() (REG32(ADR_TX_11B_FIL_COEF_13)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_14() (REG32(ADR_TX_11B_FIL_COEF_14)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_15() (REG32(ADR_TX_11B_FIL_COEF_15)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_16() (REG32(ADR_TX_11B_FIL_COEF_16)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_17() (REG32(ADR_TX_11B_FIL_COEF_17)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_18() (REG32(ADR_TX_11B_FIL_COEF_18)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_19() (REG32(ADR_TX_11B_FIL_COEF_19)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_20() (REG32(ADR_TX_11B_FIL_COEF_20)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_21() (REG32(ADR_TX_11B_FIL_COEF_21)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_22() (REG32(ADR_TX_11B_FIL_COEF_22)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_23() (REG32(ADR_TX_11B_FIL_COEF_23)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_24() (REG32(ADR_TX_11B_FIL_COEF_24)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_25() (REG32(ADR_TX_11B_FIL_COEF_25)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_26() (REG32(ADR_TX_11B_FIL_COEF_26)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_27() (REG32(ADR_TX_11B_FIL_COEF_27)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_28() (REG32(ADR_TX_11B_FIL_COEF_28)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_29() (REG32(ADR_TX_11B_FIL_COEF_29)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_30() (REG32(ADR_TX_11B_FIL_COEF_30)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_31() (REG32(ADR_TX_11B_FIL_COEF_31)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_32() (REG32(ADR_TX_11B_FIL_COEF_32)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_33() (REG32(ADR_TX_11B_FIL_COEF_33)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_34() (REG32(ADR_TX_11B_FIL_COEF_34)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_35() (REG32(ADR_TX_11B_FIL_COEF_35)) = (0x00000005)
+#define DEF_TX_11B_FIL_COEF_36() (REG32(ADR_TX_11B_FIL_COEF_36)) = (0x0000003d)
+#define DEF_TX_11B_FIL_COEF_37() (REG32(ADR_TX_11B_FIL_COEF_37)) = (0x00000162)
+#define DEF_TX_11B_FIL_COEF_38() (REG32(ADR_TX_11B_FIL_COEF_38)) = (0x00000400)
+#define DEF_TX_11B_FIL_COEF_39() (REG32(ADR_TX_11B_FIL_COEF_39)) = (0x00000699)
+#define DEF_TX_11B_FIL_COEF_40() (REG32(ADR_TX_11B_FIL_COEF_40)) = (0x00000787)
+#define DEF_TX_11B_PLCP() (REG32(ADR_TX_11B_PLCP)) = (0x00000000)
+#define DEF_TX_11B_RAMP() (REG32(ADR_TX_11B_RAMP)) = (0x0000403c)
+#define DEF_TX_11B_EN_CNT_RST_N() (REG32(ADR_TX_11B_EN_CNT_RST_N)) = (0x00000001)
+#define DEF_TX_11B_EN_CNT() (REG32(ADR_TX_11B_EN_CNT)) = (0x00000000)
+#define DEF_TX_11B_PKT_GEN_CNT() (REG32(ADR_TX_11B_PKT_GEN_CNT)) = (0x00000000)
+#define DEF_RX_11B_DES_DLY() (REG32(ADR_RX_11B_DES_DLY)) = (0x00000044)
+#define DEF_RX_11B_CCA_0() (REG32(ADR_RX_11B_CCA_0)) = (0x00040000)
+#define DEF_RX_11B_CCA_1() (REG32(ADR_RX_11B_CCA_1)) = (0x00400040)
+#define DEF_RX_11B_TR_KP_KI_0() (REG32(ADR_RX_11B_TR_KP_KI_0)) = (0x00003467)
+#define DEF_RX_11B_TR_KP_KI_1() (REG32(ADR_RX_11B_TR_KP_KI_1)) = (0x00540000)
+#define DEF_RX_11B_CE_CNT_THRESHOLD() (REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) = (0x12243615)
+#define DEF_RX_11B_CE_MU_0() (REG32(ADR_RX_11B_CE_MU_0)) = (0x00390002)
+#define DEF_RX_11B_CE_MU_1() (REG32(ADR_RX_11B_CE_MU_1)) = (0x03456777)
+#define DEF_RX_11B_EQ_MU_0() (REG32(ADR_RX_11B_EQ_MU_0)) = (0x00350046)
+#define DEF_RX_11B_EQ_MU_1() (REG32(ADR_RX_11B_EQ_MU_1)) = (0x00570057)
+#define DEF_RX_11B_EQ_CR_KP_KI() (REG32(ADR_RX_11B_EQ_CR_KP_KI)) = (0x00236700)
+#define DEF_RX_11B_LPF_RATE() (REG32(ADR_RX_11B_LPF_RATE)) = (0x000d1746)
+#define DEF_RX_11B_CIT_CNT_THRESHOLD() (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (0x04061787)
+#define DEF_RX_11B_EQ_CH_MAIN_TAP() (REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) = (0x07800000)
+#define DEF_RX_11B_SEARCH_CNT_TH() (REG32(ADR_RX_11B_SEARCH_CNT_TH)) = (0x00c0000a)
+#define DEF_RX_11B_CCA_CONTROL() (REG32(ADR_RX_11B_CCA_CONTROL)) = (0x00000000)
+#define DEF_RX_11B_FREQUENCY_OFFSET() (REG32(ADR_RX_11B_FREQUENCY_OFFSET)) = (0x00000000)
+#define DEF_RX_11B_SNR_RSSI() (REG32(ADR_RX_11B_SNR_RSSI)) = (0x00000000)
+#define DEF_RX_11B_SFD_CRC_CNT() (REG32(ADR_RX_11B_SFD_CRC_CNT)) = (0x00000000)
+#define DEF_RX_11B_PKT_ERR_AND_PKT_ERR_CNT() (REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) = (0x00000000)
+#define DEF_RX_11B_PKT_CCA_AND_PKT_CNT() (REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) = (0x00000000)
+#define DEF_RX_11B_SFD_FILED_0() (REG32(ADR_RX_11B_SFD_FILED_0)) = (0x00000000)
+#define DEF_RX_11B_SFD_FIELD_1() (REG32(ADR_RX_11B_SFD_FIELD_1)) = (0x00000000)
+#define DEF_RX_11B_PKT_STAT_EN() (REG32(ADR_RX_11B_PKT_STAT_EN)) = (0x00100000)
+#define DEF_RX_11B_SOFT_RST() (REG32(ADR_RX_11B_SOFT_RST)) = (0x00000001)
+#define DEF_TX_11GN_RAMP() (REG32(ADR_TX_11GN_RAMP)) = (0x0000233c)
+#define DEF_TX_11GN_PLCP() (REG32(ADR_TX_11GN_PLCP)) = (0x5d08908e)
+#define DEF_TX_11GN_PKT_GEN_CNT() (REG32(ADR_TX_11GN_PKT_GEN_CNT)) = (0x00000000)
+#define DEF_TX_11GN_PLCP_CRC_ERR_CNT() (REG32(ADR_TX_11GN_PLCP_CRC_ERR_CNT)) = (0x00000000)
+#define DEF_RX_11GN_DES_DLY() (REG32(ADR_RX_11GN_DES_DLY)) = (0x00000044)
+#define DEF_RX_11GN_TR_0() (REG32(ADR_RX_11GN_TR_0)) = (0x00750075)
+#define DEF_RX_11GN_TR_1() (REG32(ADR_RX_11GN_TR_1)) = (0x00000075)
+#define DEF_RX_11GN_TR_2() (REG32(ADR_RX_11GN_TR_2)) = (0x10000075)
+#define DEF_RX_11GN_CCA_0() (REG32(ADR_RX_11GN_CCA_0)) = (0x38324705)
+#define DEF_RX_11GN_CCA_1() (REG32(ADR_RX_11GN_CCA_1)) = (0x30182000)
+#define DEF_RX_11GN_CCA_2() (REG32(ADR_RX_11GN_CCA_2)) = (0x20600000)
+#define DEF_RX_11GN_CCA_FFT_SCALE() (REG32(ADR_RX_11GN_CCA_FFT_SCALE)) = (0x0a010100)
+#define DEF_RX_11GN_SOFT_DEMAP_0() (REG32(ADR_RX_11GN_SOFT_DEMAP_0)) = (0x50505050)
+#define DEF_RX_11GN_SOFT_DEMAP_1() (REG32(ADR_RX_11GN_SOFT_DEMAP_1)) = (0x50000000)
+#define DEF_RX_11GN_SOFT_DEMAP_2() (REG32(ADR_RX_11GN_SOFT_DEMAP_2)) = (0x50505050)
+#define DEF_RX_11GN_SOFT_DEMAP_3() (REG32(ADR_RX_11GN_SOFT_DEMAP_3)) = (0x50505050)
+#define DEF_RX_11GN_SOFT_DEMAP_4() (REG32(ADR_RX_11GN_SOFT_DEMAP_4)) = (0x50000000)
+#define DEF_RX_11GN_SOFT_DEMAP_5() (REG32(ADR_RX_11GN_SOFT_DEMAP_5)) = (0x00000000)
+#define DEF_RX_11GN_SYM_BOUND_0() (REG32(ADR_RX_11GN_SYM_BOUND_0)) = (0x00001420)
+#define DEF_RX_11GN_SYM_BOUND_1() (REG32(ADR_RX_11GN_SYM_BOUND_1)) = (0x0000200a)
+#define DEF_RX_11GN_CCA_PWR() (REG32(ADR_RX_11GN_CCA_PWR)) = (0x30000280)
+#define DEF_RX_11GN_CCA_CNT() (REG32(ADR_RX_11GN_CCA_CNT)) = (0x30023002)
+#define DEF_RX_11GN_CCA_ATCOR_RE_CHECK() (REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) = (0x0000003a)
+#define DEF_RX_11GN_VTB_TB() (REG32(ADR_RX_11GN_VTB_TB)) = (0x40000000)
+#define DEF_RX_11GN_ERR_UPDATE() (REG32(ADR_RX_11GN_ERR_UPDATE)) = (0x009e007e)
+#define DEF_RX_11GN_SHORT_GI() (REG32(ADR_RX_11GN_SHORT_GI)) = (0x00044400)
+#define DEF_RX_11GN_CHANNEL_UPDATE() (REG32(ADR_RX_11GN_CHANNEL_UPDATE)) = (0x82000000)
+#define DEF_RX_11GN_PKT_FORMAT_0() (REG32(ADR_RX_11GN_PKT_FORMAT_0)) = (0x02003030)
+#define DEF_RX_11GN_PKT_FORMAT_1() (REG32(ADR_RX_11GN_PKT_FORMAT_1)) = (0x092a092a)
+#define DEF_RX_11GN_TX_TIME() (REG32(ADR_RX_11GN_TX_TIME)) = (0x00700010)
+#define DEF_RX_11GN_STBC_TR_KP_KI() (REG32(ADR_RX_11GN_STBC_TR_KP_KI)) = (0x00007575)
+#define DEF_RX_11GN_BIST_0() (REG32(ADR_RX_11GN_BIST_0)) = (0x0001fe3e)
+#define DEF_RX_11GN_BIST_1() (REG32(ADR_RX_11GN_BIST_1)) = (0x0000fe3e)
+#define DEF_RX_11GN_BIST_2() (REG32(ADR_RX_11GN_BIST_2)) = (0x00000000)
+#define DEF_RX_11GN_BIST_3() (REG32(ADR_RX_11GN_BIST_3)) = (0x00000000)
+#define DEF_RX_11GN_BIST_4() (REG32(ADR_RX_11GN_BIST_4)) = (0x00000000)
+#define DEF_RX_11GN_BIST_5() (REG32(ADR_RX_11GN_BIST_5)) = (0x00000000)
+#define DEF_RX_11GN_SPECTRUM_ANALYZER() (REG32(ADR_RX_11GN_SPECTRUM_ANALYZER)) = (0x00000000)
+#define DEF_RX_11GN_READ_0() (REG32(ADR_RX_11GN_READ_0)) = (0x00000000)
+#define DEF_RX_11GN_FREQ_OFFSET() (REG32(ADR_RX_11GN_FREQ_OFFSET)) = (0x00000000)
+#define DEF_RX_11GN_SIGNAL_FIELD_0() (REG32(ADR_RX_11GN_SIGNAL_FIELD_0)) = (0x00000000)
+#define DEF_RX_11GN_SIGNAL_FIELD_1() (REG32(ADR_RX_11GN_SIGNAL_FIELD_1)) = (0x00000000)
+#define DEF_RX_11GN_PKT_ERR_CNT() (REG32(ADR_RX_11GN_PKT_ERR_CNT)) = (0x00000000)
+#define DEF_RX_11GN_PKT_CCA_AND_PKT_CNT() (REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) = (0x00000000)
+#define DEF_RX_11GN_SERVICE_LENGTH_FIELD() (REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) = (0x00000000)
+#define DEF_RX_11GN_RATE() (REG32(ADR_RX_11GN_RATE)) = (0x00000000)
+#define DEF_RX_11GN_STAT_EN() (REG32(ADR_RX_11GN_STAT_EN)) = (0x00100001)
+#define DEF_RX_11GN_SOFT_RST() (REG32(ADR_RX_11GN_SOFT_RST)) = (0x00000001)
+#define DEF_RF_CONTROL_0() (REG32(ADR_RF_CONTROL_0)) = (0x00000000)
+#define DEF_RF_CONTROL_1() (REG32(ADR_RF_CONTROL_1)) = (0x00008000)
+#define DEF_TX_IQ_CONTROL_0() (REG32(ADR_TX_IQ_CONTROL_0)) = (0x00200020)
+#define DEF_TX_IQ_CONTROL_1() (REG32(ADR_TX_IQ_CONTROL_1)) = (0x00028080)
+#define DEF_TX_IQ_CONTROL_2() (REG32(ADR_TX_IQ_CONTROL_2)) = (0x00000000)
+#define DEF_TX_COMPENSATION_CONTROL() (REG32(ADR_TX_COMPENSATION_CONTROL)) = (0x00000000)
+#define DEF_RX_COMPENSATION_CONTROL() (REG32(ADR_RX_COMPENSATION_CONTROL)) = (0x00000000)
+#define DEF_RX_OBSERVATION_CIRCUIT_0() (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (0x000028ff)
+#define DEF_RX_OBSERVATION_CIRCUIT_1() (REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) = (0x00000000)
+#define DEF_RX_OBSERVATION_CIRCUIT_2() (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (0x00000000)
+#define DEF_RX_OBSERVATION_CIRCUIT_3() (REG32(ADR_RX_OBSERVATION_CIRCUIT_3)) = (0x00000000)
+#define DEF_RF_IQ_CONTROL_0() (REG32(ADR_RF_IQ_CONTROL_0)) = (0x00000202)
+#define DEF_RF_IQ_CONTROL_1() (REG32(ADR_RF_IQ_CONTROL_1)) = (0x00ffc200)
+#define DEF_RF_IQ_CONTROL_2() (REG32(ADR_RF_IQ_CONTROL_2)) = (0x00000000)
+#define DEF_RF_IQ_CONTROL_3() (REG32(ADR_RF_IQ_CONTROL_3)) = (0x00000000)
+#define DEF_DPD_CONTROL() (REG32(ADR_DPD_CONTROL)) = (0x00000000)
+#define DEF_DPD_GAIN_TABLE_0() (REG32(ADR_DPD_GAIN_TABLE_0)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_1() (REG32(ADR_DPD_GAIN_TABLE_1)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_2() (REG32(ADR_DPD_GAIN_TABLE_2)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_3() (REG32(ADR_DPD_GAIN_TABLE_3)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_4() (REG32(ADR_DPD_GAIN_TABLE_4)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_5() (REG32(ADR_DPD_GAIN_TABLE_5)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_6() (REG32(ADR_DPD_GAIN_TABLE_6)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_7() (REG32(ADR_DPD_GAIN_TABLE_7)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_8() (REG32(ADR_DPD_GAIN_TABLE_8)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_9() (REG32(ADR_DPD_GAIN_TABLE_9)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_A() (REG32(ADR_DPD_GAIN_TABLE_A)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_B() (REG32(ADR_DPD_GAIN_TABLE_B)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_C() (REG32(ADR_DPD_GAIN_TABLE_C)) = (0x02000200)
+#define DEF_DPD_PH_TABLE_0() (REG32(ADR_DPD_PH_TABLE_0)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_1() (REG32(ADR_DPD_PH_TABLE_1)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_2() (REG32(ADR_DPD_PH_TABLE_2)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_3() (REG32(ADR_DPD_PH_TABLE_3)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_4() (REG32(ADR_DPD_PH_TABLE_4)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_5() (REG32(ADR_DPD_PH_TABLE_5)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_6() (REG32(ADR_DPD_PH_TABLE_6)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_7() (REG32(ADR_DPD_PH_TABLE_7)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_8() (REG32(ADR_DPD_PH_TABLE_8)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_9() (REG32(ADR_DPD_PH_TABLE_9)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_A() (REG32(ADR_DPD_PH_TABLE_A)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_B() (REG32(ADR_DPD_PH_TABLE_B)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_C() (REG32(ADR_DPD_PH_TABLE_C)) = (0x00000000)
+#define DEF_DPD_GAIN_ESTIMATION_0() (REG32(ADR_DPD_GAIN_ESTIMATION_0)) = (0x00000000)
+#define DEF_DPD_GAIN_ESTIMATION_1() (REG32(ADR_DPD_GAIN_ESTIMATION_1)) = (0x00000100)
+#define DEF_DPD_GAIN_ESTIMATION_2() (REG32(ADR_DPD_GAIN_ESTIMATION_2)) = (0x00000000)
+#define DEF_TX_GAIN_FACTOR() (REG32(ADR_TX_GAIN_FACTOR)) = (0x80808080)
+#define DEF_HARD_WIRE_PIN_REGISTER() (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (0x00004000)
+#define DEF_MANUAL_ENABLE_REGISTER() (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (0x00000fc0)
+#define DEF_LDO_REGISTER() (REG32(ADR_LDO_REGISTER)) = (0x000db71b)
+#define DEF_ABB_REGISTER_1() (REG32(ADR_ABB_REGISTER_1)) = (0x151558dd)
+#define DEF_ABB_REGISTER_2() (REG32(ADR_ABB_REGISTER_2)) = (0x01011a88)
+#define DEF_TX_FE_REGISTER() (REG32(ADR_TX_FE_REGISTER)) = (0x3d3e84fe)
+#define DEF_RX_FE_REGISTER_1() (REG32(ADR_RX_FE_REGISTER_1)) = (0x03457579)
+#define DEF_RX_FE_GAIN_DECODER_REGISTER_1() (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (0x000103a7)
+#define DEF_RX_FE_GAIN_DECODER_REGISTER_2() (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (0x000103a6)
+#define DEF_RX_FE_GAIN_DECODER_REGISTER_3() (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (0x00012001)
+#define DEF_RX_FE_GAIN_DECODER_REGISTER_4() (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (0x00036000)
+#define DEF_RX_TX_FSM_REGISTER() (REG32(ADR_RX_TX_FSM_REGISTER)) = (0x00030ca8)
+#define DEF_RX_ADC_REGISTER() (REG32(ADR_RX_ADC_REGISTER)) = (0x20ea0224)
+#define DEF_TX_DAC_REGISTER() (REG32(ADR_TX_DAC_REGISTER)) = (0x44000655)
+#define DEF_SX_ENABLE_REGISTER() (REG32(ADR_SX_ENABLE_REGISTER)) = (0x0003e07c)
+#define DEF_SYN_REGISTER_1() (REG32(ADR_SYN_REGISTER_1)) = (0xaa800000)
+#define DEF_SYN_REGISTER_2() (REG32(ADR_SYN_REGISTER_2)) = (0x00550800)
+#define DEF_SYN_PFD_CHP() (REG32(ADR_SYN_PFD_CHP)) = (0x07c0894a)
+#define DEF_SYN_VCO_LOBF() (REG32(ADR_SYN_VCO_LOBF)) = (0xfcccca27)
+#define DEF_SYN_DIV_SDM_XOSC() (REG32(ADR_SYN_DIV_SDM_XOSC)) = (0x07700830)
+#define DEF_SYN_KVCO_XO_FINE_TUNE_CBANK() (REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) = (0x00440000)
+#define DEF_SYN_LCK_VT() (REG32(ADR_SYN_LCK_VT)) = (0x00007ff4)
+#define DEF_DPLL_VCO_REGISTER() (REG32(ADR_DPLL_VCO_REGISTER)) = (0x0000000e)
+#define DEF_DPLL_CP_PFD_REGISTER() (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (0x00088008)
+#define DEF_DPLL_DIVIDER_REGISTER() (REG32(ADR_DPLL_DIVIDER_REGISTER)) = (0x00406000)
+#define DEF_DCOC_IDAC_REGISTER1() (REG32(ADR_DCOC_IDAC_REGISTER1)) = (0x08820820)
+#define DEF_DCOC_IDAC_REGISTER2() (REG32(ADR_DCOC_IDAC_REGISTER2)) = (0x00820820)
+#define DEF_DCOC_IDAC_REGISTER3() (REG32(ADR_DCOC_IDAC_REGISTER3)) = (0x00820820)
+#define DEF_DCOC_IDAC_REGISTER4() (REG32(ADR_DCOC_IDAC_REGISTER4)) = (0x00820820)
+#define DEF_DCOC_IDAC_REGISTER5() (REG32(ADR_DCOC_IDAC_REGISTER5)) = (0x00820820)
+#define DEF_DCOC_IDAC_REGISTER6() (REG32(ADR_DCOC_IDAC_REGISTER6)) = (0x00820820)
+#define DEF_DCOC_IDAC_REGISTER7() (REG32(ADR_DCOC_IDAC_REGISTER7)) = (0x00820820)
+#define DEF_DCOC_IDAC_REGISTER8() (REG32(ADR_DCOC_IDAC_REGISTER8)) = (0x00820820)
+#define DEF_RCAL_REGISTER() (REG32(ADR_RCAL_REGISTER)) = (0x00004080)
+#define DEF_SX_LCK_BIN_REGISTERS_I() (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (0x20080080)
+#define DEF_TRX_DUMMY_REGISTER() (REG32(ADR_TRX_DUMMY_REGISTER)) = (0xaaaaaaaa)
+#define DEF_SX_DUMMY_REGISTER() (REG32(ADR_SX_DUMMY_REGISTER)) = (0xaaaaaaaa)
+#define DEF_DPLL_FB_DIVIDER_REGISTERS_II() (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_II)) = (0x00ec2ec5)
+#define DEF_SX_LCK_BIN_REGISTERS_II() (REG32(ADR_SX_LCK_BIN_REGISTERS_II)) = (0x00000f13)
+#define DEF_RC_OSC_32K_CAL_REGISTERS() (REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) = (0x00098900)
+#define DEF_RF_D_DIGITAL_DEBUG_PORT_REGISTER() (REG32(ADR_RF_D_DIGITAL_DEBUG_PORT_REGISTER)) = (0x00000000)
+#define DEF_MMU_CTRL() (REG32(ADR_MMU_CTRL)) = (0x00002042)
+#define DEF_HS_CTRL() (REG32(ADR_HS_CTRL)) = (0x00000000)
+#define DEF_CPU_POR0_7() (REG32(ADR_CPU_POR0_7)) = (0x00000000)
+#define DEF_CPU_POR8_F() (REG32(ADR_CPU_POR8_F)) = (0x00000000)
+#define DEF_REG_LEN_CTRL() (REG32(ADR_REG_LEN_CTRL)) = (0x00000f0f)
+#define DEF_DMN_READ_BYPASS() (REG32(ADR_DMN_READ_BYPASS)) = (0x0000ffff)
+#define DEF_ALC_RLS_ABORT() (REG32(ADR_ALC_RLS_ABORT)) = (0x00000000)
+#define DEF_DEBUG_CTL() (REG32(ADR_DEBUG_CTL)) = (0x00000000)
+#define DEF_DEBUG_OUT() (REG32(ADR_DEBUG_OUT)) = (0x00000000)
+#define DEF_MMU_STATUS() (REG32(ADR_MMU_STATUS)) = (0x00000000)
+#define DEF_DMN_STATUS() (REG32(ADR_DMN_STATUS)) = (0x00000000)
+#define DEF_TAG_STATUS() (REG32(ADR_TAG_STATUS)) = (0x00000000)
+#define DEF_DMN_MCU_STATUS() (REG32(ADR_DMN_MCU_STATUS)) = (0x00000000)
+#define DEF_MB_IDTBL_0_STATUS() (REG32(ADR_MB_IDTBL_0_STATUS)) = (0x00000000)
+#define DEF_MB_IDTBL_1_STATUS() (REG32(ADR_MB_IDTBL_1_STATUS)) = (0x00000000)
+#define DEF_MB_IDTBL_2_STATUS() (REG32(ADR_MB_IDTBL_2_STATUS)) = (0x00000000)
+#define DEF_MB_IDTBL_3_STATUS() (REG32(ADR_MB_IDTBL_3_STATUS)) = (0x00000000)
+#define DEF_PKT_IDTBL_0_STATUS() (REG32(ADR_PKT_IDTBL_0_STATUS)) = (0x00000000)
+#define DEF_PKT_IDTBL_1_STATUS() (REG32(ADR_PKT_IDTBL_1_STATUS)) = (0x00000000)
+#define DEF_PKT_IDTBL_2_STATUS() (REG32(ADR_PKT_IDTBL_2_STATUS)) = (0x00000000)
+#define DEF_PKT_IDTBL_3_STATUS() (REG32(ADR_PKT_IDTBL_3_STATUS)) = (0x00000000)
+#define DEF_DMN_IDTBL_0_STATUS() (REG32(ADR_DMN_IDTBL_0_STATUS)) = (0x00000000)
+#define DEF_DMN_IDTBL_1_STATUS() (REG32(ADR_DMN_IDTBL_1_STATUS)) = (0x00000000)
+#define DEF_DMN_IDTBL_2_STATUS() (REG32(ADR_DMN_IDTBL_2_STATUS)) = (0x00000000)
+#define DEF_DMN_IDTBL_3_STATUS() (REG32(ADR_DMN_IDTBL_3_STATUS)) = (0x00000000)
+#define DEF_MB_NEQID_0_STATUS() (REG32(ADR_MB_NEQID_0_STATUS)) = (0x00000000)
+#define DEF_MB_NEQID_1_STATUS() (REG32(ADR_MB_NEQID_1_STATUS)) = (0x00000000)
+#define DEF_MB_NEQID_2_STATUS() (REG32(ADR_MB_NEQID_2_STATUS)) = (0x00000000)
+#define DEF_MB_NEQID_3_STATUS() (REG32(ADR_MB_NEQID_3_STATUS)) = (0x00000000)
+#define DEF_PKT_NEQID_0_STATUS() (REG32(ADR_PKT_NEQID_0_STATUS)) = (0x00000000)
+#define DEF_PKT_NEQID_1_STATUS() (REG32(ADR_PKT_NEQID_1_STATUS)) = (0x00000000)
+#define DEF_PKT_NEQID_2_STATUS() (REG32(ADR_PKT_NEQID_2_STATUS)) = (0x00000000)
+#define DEF_PKT_NEQID_3_STATUS() (REG32(ADR_PKT_NEQID_3_STATUS)) = (0x00000000)
+#define DEF_ALC_NOCHG_ID_STATUS() (REG32(ADR_ALC_NOCHG_ID_STATUS)) = (0x00000000)
+#define DEF_TAG_SRAM0_F_STATUS_0() (REG32(ADR_TAG_SRAM0_F_STATUS_0)) = (0x00000000)
+#define DEF_TAG_SRAM0_F_STATUS_1() (REG32(ADR_TAG_SRAM0_F_STATUS_1)) = (0x00000000)
+#define DEF_TAG_SRAM0_F_STATUS_2() (REG32(ADR_TAG_SRAM0_F_STATUS_2)) = (0x00000000)
+#define DEF_TAG_SRAM0_F_STATUS_3() (REG32(ADR_TAG_SRAM0_F_STATUS_3)) = (0x00000000)
+#define DEF_TAG_SRAM0_F_STATUS_4() (REG32(ADR_TAG_SRAM0_F_STATUS_4)) = (0x00000000)
+#define DEF_TAG_SRAM0_F_STATUS_5() (REG32(ADR_TAG_SRAM0_F_STATUS_5)) = (0x00000000)
+#define DEF_TAG_SRAM0_F_STATUS_6() (REG32(ADR_TAG_SRAM0_F_STATUS_6)) = (0x00000000)
+#define DEF_TAG_SRAM0_F_STATUS_7() (REG32(ADR_TAG_SRAM0_F_STATUS_7)) = (0x00000000)
diff --git a/drivers/net/wireless/ssv6x5x/include/ssv6200_reg_sim.h b/drivers/net/wireless/ssv6x5x/include/ssv6200_reg_sim.h
new file mode 100644
index 000000000..4143f9c21
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/include/ssv6200_reg_sim.h
@@ -0,0 +1,173 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "ssv6200_reg.h"
+#define BANK_COUNT 49
+static const u32 BASE_BANK_SSV6200[] = {
+    SYS_REG_BASE,
+    WBOOT_REG_BASE,
+    TU0_US_REG_BASE,
+    TU1_US_REG_BASE,
+    TU2_US_REG_BASE,
+    TU3_US_REG_BASE,
+    TM0_MS_REG_BASE,
+    TM1_MS_REG_BASE,
+    TM2_MS_REG_BASE,
+    TM3_MS_REG_BASE,
+    MCU_WDT_REG_BASE,
+    SYS_WDT_REG_BASE,
+    GPIO_REG_BASE,
+    SD_REG_BASE,
+    SPI_REG_BASE,
+    CSR_I2C_MST_BASE,
+    UART_REG_BASE,
+    DAT_UART_REG_BASE,
+    INT_REG_BASE,
+    DBG_SPI_REG_BASE,
+    FLASH_SPI_REG_BASE,
+    DMA_REG_BASE,
+    CSR_PMU_BASE,
+    CSR_RTC_BASE,
+    RTC_RAM_BASE,
+    D2_DMA_REG_BASE,
+    HCI_REG_BASE,
+    CO_REG_BASE,
+    EFS_REG_BASE,
+    SMS4_REG_BASE,
+    MRX_REG_BASE,
+    AMPDU_REG_BASE,
+    MT_REG_CSR_BASE,
+    TXQ0_MT_Q_REG_CSR_BASE,
+    TXQ1_MT_Q_REG_CSR_BASE,
+    TXQ2_MT_Q_REG_CSR_BASE,
+    TXQ3_MT_Q_REG_CSR_BASE,
+    TXQ4_MT_Q_REG_CSR_BASE,
+    HIF_INFO_BASE,
+    PHY_RATE_INFO_BASE,
+    MAC_GLB_SET_BASE,
+    BTCX_REG_BASE,
+    MIB_REG_BASE,
+    CBR_A_REG_BASE,
+    MB_REG_BASE,
+    ID_MNG_REG_BASE,
+    CSR_PHY_BASE,
+    CSR_RF_BASE,
+    MMU_REG_BASE,
+    0x00000000
+};
+static const char* STR_BANK_SSV6200[] = {
+    "SYS_REG",
+    "WBOOT_REG",
+    "TU0_US_REG",
+    "TU1_US_REG",
+    "TU2_US_REG",
+    "TU3_US_REG",
+    "TM0_MS_REG",
+    "TM1_MS_REG",
+    "TM2_MS_REG",
+    "TM3_MS_REG",
+    "MCU_WDT_REG",
+    "SYS_WDT_REG",
+    "GPIO_REG",
+    "SD_REG",
+    "SPI_REG",
+    "CSR_I2C_MST",
+    "UART_REG",
+    "DAT_UART_REG",
+    "INT_REG",
+    "DBG_SPI_REG",
+    "FLASH_SPI_REG",
+    "DMA_REG",
+    "CSR_PMU",
+    "CSR_RTC",
+    "RTC_RAM",
+    "D2_DMA_REG",
+    "HCI_REG",
+    "CO_REG",
+    "EFS_REG",
+    "SMS4_REG",
+    "MRX_REG",
+    "AMPDU_REG",
+    "MT_REG_CSR",
+    "TXQ0_MT_Q_REG_CSR",
+    "TXQ1_MT_Q_REG_CSR",
+    "TXQ2_MT_Q_REG_CSR",
+    "TXQ3_MT_Q_REG_CSR",
+    "TXQ4_MT_Q_REG_CSR",
+    "HIF_INFO",
+    "PHY_RATE_INFO",
+    "MAC_GLB_SET",
+    "BTCX_REG",
+    "MIB_REG",
+    "CBR_A_REG",
+    "MB_REG",
+    "ID_MNG_REG",
+    "CSR_PHY",
+    "CSR_RF",
+    "MMU_REG",
+    ""
+};
+static const u32 SIZE_BANK_SSV6200[] = {
+    SYS_REG_BANK_SIZE,
+    WBOOT_REG_BANK_SIZE,
+    TU0_US_REG_BANK_SIZE,
+    TU1_US_REG_BANK_SIZE,
+    TU2_US_REG_BANK_SIZE,
+    TU3_US_REG_BANK_SIZE,
+    TM0_MS_REG_BANK_SIZE,
+    TM1_MS_REG_BANK_SIZE,
+    TM2_MS_REG_BANK_SIZE,
+    TM3_MS_REG_BANK_SIZE,
+    MCU_WDT_REG_BANK_SIZE,
+    SYS_WDT_REG_BANK_SIZE,
+    GPIO_REG_BANK_SIZE,
+    SD_REG_BANK_SIZE,
+    SPI_REG_BANK_SIZE,
+    CSR_I2C_MST_BANK_SIZE,
+    UART_REG_BANK_SIZE,
+    DAT_UART_REG_BANK_SIZE,
+    INT_REG_BANK_SIZE,
+    DBG_SPI_REG_BANK_SIZE,
+    FLASH_SPI_REG_BANK_SIZE,
+    DMA_REG_BANK_SIZE,
+    CSR_PMU_BANK_SIZE,
+    CSR_RTC_BANK_SIZE,
+    RTC_RAM_BANK_SIZE,
+    D2_DMA_REG_BANK_SIZE,
+    HCI_REG_BANK_SIZE,
+    CO_REG_BANK_SIZE,
+    EFS_REG_BANK_SIZE,
+    SMS4_REG_BANK_SIZE,
+    MRX_REG_BANK_SIZE,
+    AMPDU_REG_BANK_SIZE,
+    MT_REG_CSR_BANK_SIZE,
+    TXQ0_MT_Q_REG_CSR_BANK_SIZE,
+    TXQ1_MT_Q_REG_CSR_BANK_SIZE,
+    TXQ2_MT_Q_REG_CSR_BANK_SIZE,
+    TXQ3_MT_Q_REG_CSR_BANK_SIZE,
+    TXQ4_MT_Q_REG_CSR_BANK_SIZE,
+    HIF_INFO_BANK_SIZE,
+    PHY_RATE_INFO_BANK_SIZE,
+    MAC_GLB_SET_BANK_SIZE,
+    BTCX_REG_BANK_SIZE,
+    MIB_REG_BANK_SIZE,
+    CBR_A_REG_BANK_SIZE,
+    MB_REG_BANK_SIZE,
+    ID_MNG_REG_BANK_SIZE,
+    CSR_PHY_BANK_SIZE,
+    CSR_RF_BANK_SIZE,
+    MMU_REG_BANK_SIZE,
+    0x00000000
+};
diff --git a/drivers/net/wireless/ssv6x5x/include/ssv6xxx_cfg.h b/drivers/net/wireless/ssv6x5x/include/ssv6xxx_cfg.h
new file mode 100644
index 000000000..1b54798cd
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/include/ssv6xxx_cfg.h
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV6XXX_H_
+#define _SSV6XXX_H_
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#ifdef SSV_MAC80211
+#include "ssv_mac80211.h"
+#else
+#include <net/mac80211.h>
+#endif
+#ifdef ECLIPSE
+#include <ssv_mod_conf.h>
+#endif
+#include "ssv6xxx_common.h"
+#ifndef SSV_SUPPORT_HAL
+#include <ssv6200_reg.h>
+#include <ssv6200_aux.h>
+#endif
+#include <hwif/hwif.h>
+#include <hci/ssv_hci.h>
+#ifdef SSV6200_ECO
+#define SSV6200_TOTAL_ID 128
+#ifndef HUW_DRV
+#define SSV6200_ID_TX_THRESHOLD 19
+#define SSV6200_ID_RX_THRESHOLD 60
+#define SSV6200_PAGE_TX_THRESHOLD 115
+#define SSV6200_PAGE_RX_THRESHOLD 115
+#define SSV6XXX_AMPDU_DIVIDER (2)
+#define SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER (SSV6200_PAGE_TX_THRESHOLD - (SSV6200_PAGE_TX_THRESHOLD/SSV6XXX_AMPDU_DIVIDER))
+#define SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER 2
+#else
+#undef SSV6200_ID_TX_THRESHOLD
+#undef SSV6200_ID_RX_THRESHOLD
+#undef SSV6200_PAGE_TX_THRESHOLD
+#undef SSV6200_PAGE_RX_THRESHOLD
+#undef SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER
+#undef SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER
+#define SSV6200_ID_TX_THRESHOLD 31
+#define SSV6200_ID_RX_THRESHOLD 31
+#define SSV6200_PAGE_TX_THRESHOLD 61
+#define SSV6200_PAGE_RX_THRESHOLD 61
+#define SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER 45
+#define SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER 2
+#endif
+#else
+#undef SSV6200_ID_TX_THRESHOLD
+#undef SSV6200_ID_RX_THRESHOLD
+#undef SSV6200_PAGE_TX_THRESHOLD
+#undef SSV6200_PAGE_RX_THRESHOLD
+#undef SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER
+#undef SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER
+#define SSV6200_ID_TX_THRESHOLD 63
+#define SSV6200_ID_RX_THRESHOLD 63
+#ifdef PREFER_RX
+#define SSV6200_PAGE_TX_THRESHOLD (126-24)
+#define SSV6200_PAGE_RX_THRESHOLD (126+24)
+#else
+#undef SSV6200_PAGE_TX_THRESHOLD
+#undef SSV6200_PAGE_RX_THRESHOLD
+#define SSV6200_PAGE_TX_THRESHOLD 126
+#define SSV6200_PAGE_RX_THRESHOLD 126
+#endif
+#define SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER (SSV6200_PAGE_TX_THRESHOLD/2)
+#define SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER 2
+#endif
+#define SSV6200_ID_NUMBER (128)
+#define PACKET_ADDR_2_ID(addr) ((addr >> 16) & 0x7F)
+#define SSV6200_ID_AC_RESERVED 1
+#define SSV6200_ID_AC_BK_OUT_QUEUE 8
+#define SSV6200_ID_AC_BE_OUT_QUEUE 15
+#define SSV6200_ID_AC_VI_OUT_QUEUE 16
+#define SSV6200_ID_AC_VO_OUT_QUEUE 16
+#define SSV6200_ID_MANAGER_QUEUE 8
+#define HW_MMU_PAGE_SHIFT 0x8
+#define HW_MMU_PAGE_MASK 0xff
+#define SSV6200_BT_PRI_SMP_TIME 0
+#define SSV6200_BT_STA_SMP_TIME (SSV6200_BT_PRI_SMP_TIME+0)
+#define SSV6200_WLAN_REMAIN_TIME 0
+#define BT_2WIRE_EN_MSK 0x00000400
+struct txResourceControl {
+    u32 txUsePage:8;
+    u32 txUseID:6;
+    u32 edca0:4;
+    u32 edca1:4;
+    u32 edca2:5;
+    u32 edca3:5;
+};
+#include "ssv_cfg.h"
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/include/ssv6xxx_common.h b/drivers/net/wireless/ssv6x5x/include/ssv6xxx_common.h
new file mode 100644
index 000000000..f3a3789d5
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/include/ssv6xxx_common.h
@@ -0,0 +1,370 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __SSV6XXX_COMMON_H__
+#define __SSV6XXX_COMMON_H__
+#include <ssv_chip_id.h>
+#define SSV_RC_MAX_HARDWARE_SUPPORT 1
+#define RC_FIRMWARE_REPORT_FLAG 0x80
+#define FIRWARE_NOT_MATCH_CODE 0xF1F1F1F1
+#define MAX_RX_PKT_RSVD 512
+#define MAX_FRAME_SIZE 2432
+#define MAX_FRAME_SIZE_DMG 4096
+#define HCI_RX_AGGR_SIZE 0x1b00
+#define MAX_HCI_RX_AGGR_SIZE (HCI_RX_AGGR_SIZE+MAX_FRAME_SIZE)
+#define RX_NORMAL_MODE 0x0001
+#define RX_HW_AGG_MODE 0x0002
+#define RX_HW_AGG_MODE_METH3 0x0004
+#define RX_BURSTREAD_MODE 0x0008
+#define RX_BURSTREAD_SZ_FROM_CMD 0x0001
+#define RX_BURSTREAD_SZ_MAX_FRAME 0x0002
+#define RX_BURSTREAD_SZ_MAX_FRAME_DMG 0x0003
+#define MAX_RX_BURSTREAD_CNT 3
+#define MAX_RX_BURSTREAD_LENGTH 1024
+#define LOG_TX_DESC 0x0001
+#define LOG_AMPDU_SSN 0x0002
+#define LOG_AMPDU_DBG 0x0004
+#define LOG_AMPDU_ERR 0x0008
+#define LOG_BEACON 0x0010
+#define LOG_RATE_CONTROL 0x0020
+#define LOG_RATE_REPORT 0x0040
+#define LOG_TX_FRAME 0x0080
+#define LOG_RX_DESC 0x0100
+#define LOG_HCI 0x0200
+#define LOG_HWIF 0x0400
+#define LOG_HAL 0x0800
+#define LOG_REGW 0x1000
+#define LOG_FLASH_BIN 0x2000
+#define MAX_AGGR_NUM (24)
+#define SSV62XX_TX_MAX_RATES 3
+struct fw_rc_retry_params {
+    u32 count:4;
+    u32 drate:6;
+    u32 crate:6;
+    u32 rts_cts_nav:16;
+    u32 frame_consume_time:10;
+    u32 dl_length:12;
+    u32 RSVD:10;
+} __attribute__((packed));
+#define TXPB_OFFSET 80
+#define RXPB_OFFSET 80
+#define SSV6XXX_CHIP_ID_LENGTH (24)
+#define SSV6XXX_CHIP_ID_SHORT_LENGTH (8)
+#define M0_TXREQ 0
+#define M1_TXREQ 1
+#define M2_TXREQ 2
+#define M0_RXEVENT 3
+#define M2_RXEVENT 4
+#define HOST_CMD 5
+#define HOST_EVENT 6
+#define RATE_RPT 7
+#ifndef SSV_SUPPORT_HAL
+#define SSV6XXX_RX_DESC_LEN \
+        (sizeof(struct ssv6200_rx_desc) + \
+         sizeof(struct ssv6200_rxphy_info))
+#define SSV6XXX_TX_DESC_LEN \
+        (sizeof(struct ssv6200_tx_desc) + 0)
+#endif
+#define SSV6XXX_PKT_RUN_TYPE_NOTUSED 0x0
+#define SSV6XXX_PKT_RUN_TYPE_AMPDU_START 0x1
+#define SSV6XXX_PKT_RUN_TYPE_AMPDU_END 0x7f
+#define SSV6XXX_PKT_RUN_TYPE_NULLFUN 0x80
+typedef enum __PBuf_Type_E {
+    NOTYPE_BUF = 0,
+    TX_BUF = 1,
+    RX_BUF = 2
+} PBuf_Type_E;
+typedef struct cfg_host_cmd {
+    u32 len:16;
+    u32 c_type:3;
+    u32 RSVD0:5;
+    u32 h_cmd:8;
+    u32 cmd_seq_no;
+    union {
+        u32 dummy;
+        u8 dat8[0];
+        u16 dat16[0];
+        u32 dat32[0];
+    };
+} HDR_HostCmd;
+#define HOST_CMD_HDR_LEN ((size_t)(((HDR_HostCmd *)100)->dat8)-100U)
+#define HOST_CMD_DUMMY_LEN 4
+struct sdio_rxtput_cfg {
+    u32 size_per_frame;
+    u32 total_frames;
+};
+typedef enum {
+    SSV6XXX_HOST_CMD_START = 0,
+    SSV6XXX_HOST_CMD_LOG = 1,
+    SSV6XXX_HOST_CMD_PS = 2,
+    SSV6XXX_HOST_CMD_INIT_CALI = 3,
+    SSV6XXX_HOST_CMD_RX_TPUT = 4,
+    SSV6XXX_HOST_CMD_TX_TPUT = 5,
+    SSV6XXX_HOST_CMD_SMART_ICOMM = 6,
+    SSV6XXX_HOST_CMD_WSID_OP = 7,
+    SSV6XXX_HOST_CMD_SET_NOA = 8,
+    SSV6XXX_HOST_CMD_TX_POLL = 9,
+    SSV6XXX_HOST_CMD_SOFT_BEACON = 10,
+    SSV6XXX_HOST_CMD_MRX_MODE = 11,
+    SSV6XXX_HOST_SOC_CMD_MAXID = 12,
+} ssv6xxx_host_cmd_id;
+typedef struct cfg_host_event {
+    u32 len :16;
+    u32 c_type :3;
+    u32 RSVD0 :5;
+    u32 h_event :8;
+    u32 evt_seq_no;
+    u8 dat[0];
+} HDR_HostEvent;
+typedef enum {
+    SOC_EVT_CMD_RESP = 0,
+    SOC_EVT_SCAN_RESULT = 1,
+    SOC_EVT_DEAUTH = 2,
+    SOC_EVT_GET_REG_RESP = 3,
+    SOC_EVT_NO_BA = 4,
+    SOC_EVT_RC_MPDU_REPORT = 5,
+    SOC_EVT_RC_AMPDU_REPORT = 6,
+    SOC_EVT_LOG = 7,
+    SOC_EVT_NOA = 8,
+    SOC_EVT_USER_END = 9,
+    SOC_EVT_SDIO_TEST_COMMAND = 10,
+    SOC_EVT_RESET_HOST = 11,
+    SOC_EVT_SDIO_TXTPUT_RESULT = 12,
+    SOC_EVT_TXLOOPBK_RESULT = 13,
+    SOC_EVT_SMART_ICOMM = 14,
+    SOC_EVT_BEACON_LOSS = 15,
+    SOC_EVT_TX_STUCK_RESP = 16,
+    SOC_EVT_SW_BEACON_RESP = 17,
+    SOC_EVT_MAXID = 18,
+} ssv6xxx_soc_event;
+#ifdef CONFIG_P2P_NOA
+typedef enum {
+    SSV6XXX_NOA_START = 0,
+    SSV6XXX_NOA_STOP,
+} ssv6xxx_host_noa_event;
+struct ssv62xx_noa_evt {
+    u8 evt_id;
+    u8 vif;
+} __attribute__((packed));
+#endif
+enum SSV6XXX_WSID_SEC {
+    SSV6XXX_WSID_SEC_NONE = 0,
+    SSV6XXX_WSID_SEC_PAIRWISE = 1<<0,
+    SSV6XXX_WSID_SEC_GROUP = 1<<1,
+};
+enum SSV6XXX_RETURN_STATE {
+    SSV6XXX_STATE_OK,
+    SSV6XXX_STATE_NG,
+    SSV6XXX_STATE_MAX
+};
+#ifdef FW_WSID_WATCH_LIST
+enum SSV6XXX_WSID_OPS {
+    SSV6XXX_WSID_OPS_ADD,
+    SSV6XXX_WSID_OPS_DEL,
+    SSV6XXX_WSID_OPS_RESETALL,
+    SSV6XXX_WSID_OPS_ENABLE_CAPS,
+    SSV6XXX_WSID_OPS_DISABLE_CAPS,
+    SSV6XXX_WSID_OPS_HWWSID_PAIRWISE_SET_TYPE,
+    SSV6XXX_WSID_OPS_HWWSID_GROUP_SET_TYPE,
+    SSV6XXX_WSID_OPS_MAX
+};
+enum SSV6XXX_WSID_SEC_TYPE {
+    SSV6XXX_WSID_SEC_SW,
+    SSV6XXX_WSID_SEC_HW,
+    SSV6XXX_WSID_SEC_TYPE_MAX
+};
+struct ssv6xxx_wsid_params {
+    u8 cmd;
+    u8 wsid_idx;
+    u8 target_wsid[6];
+    u8 hw_security;
+};
+#endif
+enum SSV6XXX_TX_POLL_TYPE {
+    SSV6XXX_TX_POLL_START = 0,
+    SSV6XXX_TX_POLL_RESET = 1,
+    SSV6XXX_TX_POLL_STOP = 2
+};
+enum SSV6XXX_SOFT_BEACON_TYPE {
+    SSV6XXX_SOFT_BEACON_START = 0,
+    SSV6XXX_SOFT_BEACON_STOP = 1
+};
+enum SSV6XXX_MRX_MODE_TYPE {
+    SSV6XXX_MRX_NORMAL = 0,
+    SSV6XXX_MRX_PROMISCUOUS = 1
+};
+struct ssv6xxx_iqk_cfg {
+    u32 cfg_xtal :8;
+    u32 cfg_pa :8;
+    u32 cfg_pabias_ctrl :8;
+    u32 cfg_pacascode_ctrl :8;
+    u32 cfg_tssi_trgt :8;
+    u32 cfg_tssi_div :8;
+    u32 cfg_def_tx_scale_11b :8;
+    u32 cfg_def_tx_scale_11b_p0d5 :8;
+    u32 cfg_def_tx_scale_11g :8;
+    u32 cfg_def_tx_scale_11g_p0d5 :8;
+    u32 cmd_sel;
+    union {
+        u32 fx_sel;
+        u32 argv;
+    };
+    u32 phy_tbl_size;
+    u32 rf_tbl_size;
+};
+#define PHY_SETTING_SIZE sizeof(phy_setting)
+struct ssv6xxx_ch_cfg {
+    u32 reg_addr;
+    u32 ch1_12_value;
+    u32 ch13_14_value;
+};
+#define IQK_CFG_LEN (sizeof(struct ssv6xxx_iqk_cfg))
+#define RF_SETTING_SIZE (sizeof(asic_rf_setting))
+#define MAX_PHY_SETTING_TABLE_SIZE 1920
+#define MAX_RF_SETTING_TABLE_SIZE 512
+typedef enum {
+    SSV6XXX_VOLT_DCDC_CONVERT = 0,
+    SSV6XXX_VOLT_LDO_CONVERT = 1,
+} ssv6xxx_cfg_volt;
+typedef enum {
+    SSV6XXX_VOLT_33V = 0,
+    SSV6XXX_VOLT_42V,
+} ssv6xxx_cfg_volt_value;
+typedef enum {
+    SSV6XXX_IQK_CFG_XTAL_26M = 0,
+    SSV6XXX_IQK_CFG_XTAL_40M,
+    SSV6XXX_IQK_CFG_XTAL_24M,
+    SSV6XXX_IQK_CFG_XTAL_25M,
+    SSV6XXX_IQK_CFG_XTAL_12M,
+    SSV6XXX_IQK_CFG_XTAL_16M,
+    SSV6XXX_IQK_CFG_XTAL_20M,
+    SSV6XXX_IQK_CFG_XTAL_32M,
+    SSV6XXX_IQK_CFG_XTAL_MAX,
+} ssv6xxx_iqk_cfg_xtal;
+typedef enum {
+    SSV6XXX_IQK_CFG_PA_DEF = 0,
+    SSV6XXX_IQK_CFG_PA_LI_MPB,
+    SSV6XXX_IQK_CFG_PA_LI_EVB,
+    SSV6XXX_IQK_CFG_PA_HP,
+} ssv6xxx_iqk_cfg_pa;
+typedef enum {
+    SSV6XXX_IQK_CMD_INIT_CALI = 0,
+    SSV6XXX_IQK_CMD_RTBL_LOAD,
+    SSV6XXX_IQK_CMD_RTBL_LOAD_DEF,
+    SSV6XXX_IQK_CMD_RTBL_RESET,
+    SSV6XXX_IQK_CMD_RTBL_SET,
+    SSV6XXX_IQK_CMD_RTBL_EXPORT,
+    SSV6XXX_IQK_CMD_TK_EVM,
+    SSV6XXX_IQK_CMD_TK_TONE,
+    SSV6XXX_IQK_CMD_TK_CHCH,
+} ssv6xxx_iqk_cmd_sel;
+#define SSV6XXX_IQK_TEMPERATURE 0x00000004
+#define SSV6XXX_IQK_RXDC 0x00000008
+#define SSV6XXX_IQK_RXRC 0x00000010
+#define SSV6XXX_IQK_TXDC 0x00000020
+#define SSV6XXX_IQK_TXIQ 0x00000040
+#define SSV6XXX_IQK_RXIQ 0x00000080
+#define SSV6XXX_IQK_TSSI 0x00000100
+#define SSV6XXX_IQK_PAPD 0x00000200
+typedef struct ssv_cabrio_reg_st {
+    u32 address;
+    u32 data;
+} ssv_cabrio_reg;
+#ifdef MULTI_THREAD_ENCRYPT
+enum ssv_pkt_crypt_status {
+    PKT_CRYPT_ST_DEC_PRE,
+    PKT_CRYPT_ST_ENC_PRE,
+    PKT_CRYPT_ST_DEC_DONE,
+    PKT_CRYPT_ST_ENC_DONE,
+    PKT_CRYPT_ST_FAIL,
+    PKT_CRYPT_ST_NOT_SUPPORT
+};
+#endif
+#ifdef CONFIG_DEBUG_SKB_TIMESTAMP
+#define SKB_DURATION_TIMEOUT_MS 100
+enum ssv_debug_skb_timestamp {
+    SKB_DURATION_STAGE_TX_ENQ,
+    SKB_DURATION_STAGE_TO_SDIO,
+    SKB_DURATION_STAGE_IN_HWQ,
+    SKB_DURATION_STAGE_END
+};
+#endif
+
+#define SSV_FIRMWARE_PATH_MAX 256
+#define SSV_FIRMWARE_MAX 32
+#ifdef CONFIG_SSV_SMARTLINK
+enum ssv_smart_icomm_cmd {
+    STOP_SMART_ICOMM,
+    START_SMART_ICOMM,
+    RESET_SMART_ICOMM,
+    MAX_SMART_ICOMM
+};
+struct ssv6xxx_si_cfg {
+    u8 ssid[32];
+    u8 password[64];
+    s32 ssid_len;
+    s32 password_len;
+} __attribute__((packed));
+#endif
+#ifdef CONFIG_SSV_CABRIO_E
+struct ssv6xxx_tx_loopback {
+    u32 reg;
+    u32 val;
+    u32 restore_val;
+    u8 restore;
+    u8 delay_ms;
+};
+#endif
+struct hci_rx_aggr_info {
+    u32 jmp_mpdu_len:16;
+    u32 accu_rx_len:16;
+    u32 RSVD0:15;
+    u32 tx_page_remain:9;
+    u32 tx_id_remain:8;
+    u32 edca0:4;
+    u32 edca1:5;
+    u32 edca2:5;
+    u32 edca3:5;
+    u32 edca4:4;
+    u32 edca5:5;
+    u32 RSVD1:4;
+} __attribute__((packed));
+struct ssv6xxx_tx_hw_info {
+    u32 tx_id_threshold;
+    u32 tx_page_threshold;
+    u32 tx_lowthreshold_page_trigger;
+    u32 tx_lowthreshold_id_trigger;
+    u32 bk_txq_size;
+    u32 be_txq_size;
+    u32 vi_txq_size;
+    u32 vo_txq_size;
+    u32 manage_txq_size;
+};
+struct ssv6xxx_rx_hw_info {
+    u32 rx_id_threshold;
+    u32 rx_page_threshold;
+    u32 rx_ba_ma_sessions;
+};
+#define ENABLE_FW_SELF_CHECK 1
+#define FW_START_SRAM_ADDR 0x00000000
+#define FW_BLOCK_SIZE 0x8000
+#define CHECKSUM_BLOCK_SIZE 1024
+#define FW_CHECKSUM_INIT (0x12345678)
+#define FW_STATUS_MASK (0x00FF0000)
+enum SSV_SRAM_MODE {
+    SRAM_MODE_ILM_64K_DLM_128K = 0,
+    SRAM_MODE_ILM_160K_DLM_32K,
+};
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/include/ssv_cfg.h b/drivers/net/wireless/ssv6x5x/include/ssv_cfg.h
new file mode 100644
index 000000000..b085cff10
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/include/ssv_cfg.h
@@ -0,0 +1,160 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV_CFG_H_
+#define _SSV_CFG_H_
+#define SSV6200_HW_CAP_HT 0x00000001
+#define SSV6200_HW_CAP_GF 0x00000002
+#define SSV6200_HW_CAP_2GHZ 0x00000004
+#define SSV6200_HW_CAP_5GHZ 0x00000008
+#define SSV6200_HW_CAP_SECURITY 0x00000010
+#define SSV6200_HW_CAP_SGI 0x00000020
+#define SSV6200_HW_CAP_HT40 0x00000040
+#define SSV6200_HW_CAP_AP 0x00000080
+#define SSV6200_HW_CAP_P2P 0x00000100
+#define SSV6200_HW_CAP_AMPDU_RX 0x00000200
+#define SSV6200_HW_CAP_AMPDU_TX 0x00000400
+#define SSV6200_HW_CAP_TDLS 0x00000800
+#define SSV6200_HW_CAP_STBC 0x00001000
+#define SSV6200_HW_CAP_HCI_RX_AGGR 0x00002000
+#define SSV6200_HW_CAP_BEACON 0x00004000
+#define EXTERNEL_CONFIG_SUPPORT 64
+#define USB_HW_RESOURCE_CHK_NONE 0x00000000
+#define USB_HW_RESOURCE_CHK_TXID 0x00000001
+#define USB_HW_RESOURCE_CHK_TXPAGE 0x00000002
+#define USB_HW_RESOURCE_CHK_SCAN 0x00000004
+#define USB_HW_RESOURCE_CHK_FORCE_OFF 0x00000008
+#define ONLINE_RESET_ENABLE 0x00000100
+#define ONLINE_RESET_EDCA_THRESHOLD_MASK 0x000000ff
+#define ONLINE_RESET_EDCA_THRESHOLD_SFT 0
+
+
+enum ssv_reg_domain {
+    DOMAIN_FCC = 0,
+    DOMAIN_china,
+    DOMAIN_ETSI,
+    DOMAIN_Japan,
+    DOMAIN_Japan2,
+    DOMAIN_Israel,
+    DOMAIN_Korea,
+    DOMAIN_North_America,
+    DOMAIN_Singapore,
+    DOMAIN_Taiwan,
+    DOMAIN_other = 0xff,
+};
+
+
+
+
+struct rc_setting {
+    u16 aging_period;
+    u16 target_success_67;
+    u16 target_success_5;
+    u16 target_success_4;
+    u16 target_success;
+    u16 up_pr;
+    u16 up_pr3;
+    u16 up_pr4;
+    u16 up_pr5;
+    u16 up_pr6;
+    u16 forbid;
+    u16 forbid3;
+    u16 forbid4;
+    u16 forbid5;
+    u16 forbid6;
+    u16 sample_pr_4;
+    u16 sample_pr_5;
+    u16 force_sample_pr;
+};
+struct ssv6xxx_cfg {
+    u32 hw_caps;
+    u32 def_chan;
+    u32 crystal_type;
+    u32 volt_regulator;
+    u32 force_chip_identity;
+    u32 ignore_firmware_version;
+    u8 maddr[2][6];
+    u32 n_maddr;
+    u32 use_sw_cipher;
+    u32 use_wpa2_only;
+    u32 online_reset;
+    bool tx_stuck_detect;
+    u32 r_calbration_result;
+    u32 sar_result;
+    u32 crystal_frequency_offset;
+    u32 tx_power_index_1;
+    u32 tx_power_index_2;
+    u32 chip_identity;
+    u32 rate_table_1;
+    u32 rate_table_2;
+    u32 wifi_tx_gain_level_gn;
+    u32 wifi_tx_gain_level_b;
+    u32 configuration[EXTERNEL_CONFIG_SUPPORT+1][2];
+    u8 firmware_path[128];
+    u8 flash_bin_path[128];
+    u8 external_firmware_name[128];
+    u8 mac_address_path[128];
+    u8 mac_output_path[128];
+    u32 ignore_efuse_mac;
+    u32 efuse_rate_gain_mask;
+    u32 mac_address_mode;
+    u32 beacon_rssi_minimal;
+    u32 rc_ht_support_cck;
+    u32 auto_rate_enable;
+    u32 rc_rate_idx_set;
+    u32 rc_retry_set;
+    u32 rc_mf;
+    u32 rc_long_short;
+    u32 rc_ht40;
+    u32 rc_phy_mode;
+    u32 rc_log;
+    u32 tx_id_threshold;
+    u32 tx_page_threshold;
+    u32 max_rx_aggr_size;
+    bool rx_burstread;
+    u32 hw_rx_agg_cnt;
+    bool hw_rx_agg_method_3;
+    u32 hw_rx_agg_timer_reload;
+    u32 usb_hw_resource;
+    u32 lpbk_pkt_cnt;
+    u32 lpbk_type;
+    u32 lpbk_sec;
+    u32 lpbk_mode;
+    bool clk_src_80m;
+    u32 rts_thres_len;
+    u32 cci;
+    u32 bk_txq_size;
+    u32 be_txq_size;
+    u32 vi_txq_size;
+    u32 vo_txq_size;
+    u32 manage_txq_size;
+    u32 aggr_size_sel_pr;
+    u32 greentx;
+    u32 gt_stepsize;
+    u32 gt_max_attenuation;
+    struct rc_setting rc_setting;
+    u32 directly_ack_low_threshold;
+    u32 directly_ack_high_threshold;
+    u32 txrxboost_prio;
+    u32 txrxboost_low_threshold;
+    u32 txrxboost_high_threshold;
+    u32 rx_threshold;
+    bool force_xtal_fo;
+    u32 auto_sgi;
+    u32 disable_dpd;
+    u32 mic_err_notify;
+    u32 domain;
+};
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/include/ssv_chip_id.h b/drivers/net/wireless/ssv6x5x/include/ssv_chip_id.h
new file mode 100644
index 000000000..965bcfd3f
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/include/ssv_chip_id.h
@@ -0,0 +1,30 @@
+#ifndef __SSV_CHIP_ID_H__
+#define __SSV_CHIP_ID_H__
+#define SSV6051_CHIP "SSV6200A0"
+#define SSV6051_CHIP_ECO3 "RSV6200A0"
+#define SSV6200A "SSV6200A"
+#define RSV6200A "RSV6200A"
+#define SSV6006A "SSV6006A"
+#define SSV6006C "SSV6006C"
+#define SSV6006D "SSV6006D"
+#define SSV6006 "SSV6006A0"
+#define SSV6006MP "SSV6006C0"
+#define SSV6166 "SSV6006D0"
+#define SSV6006D1 "SSV6006D1"
+#define SSV6006D2 "SSV6006D2"
+#define SSV6006D3 "SSV6006D3"
+#define SSV6051Q_P1 0x00000000
+#define SSV6051Q_P2 0x70000000
+#define SSV6051Z 0x71000000
+#define SSV6051Q 0x73000000
+#define SSV6051P 0x75000000
+#define SV6155P 0x70000000
+#define SV6156P 0x71000000
+#define SV6166P 0x72000000
+#define SV6151P_SV6152P 0x73000000
+#define SV6167Q 0x74000000
+#define SV6166F 0x75000000
+#define SV6255P 0x78000000
+#define SV6256P 0x79000000
+#define SV6267Q 0x7C000000
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/include/ssv_conf_parser.h b/drivers/net/wireless/ssv6x5x/include/ssv_conf_parser.h
new file mode 100644
index 000000000..6c095e638
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/include/ssv_conf_parser.h
@@ -0,0 +1,35 @@
+#ifndef __SSV_CONF_PARSER_H__
+#define __SSV_CONF_PARSER_H__
+char const *conf_parser[] = {
+"CONFIG_SSV_SUPPORT_ANDROID",
+"CONFIG_FW_ALIGNMENT_CHECK",
+"CONFIG_PLATFORM_SDIO_OUTPUT_TIMING_3",
+"CONFIG_PLATFORM_SDIO_BLOCK_SIZE_128",
+"MULTI_THREAD_ENCRYPT",
+"KTHREAD_BIND",
+"CONFIG_SSV_RSSI",
+"CONFIG_SSV_VENDOR_EXT_SUPPORT",
+"__CHECK_ENDIAN__",
+"SSV_SUPPORT_HAL",
+"SSV_SUPPORT_SSV6006",
+"CONFIG_SSV_CABRIO_E",
+"CONFIG_SSV6200_CLI_ENABLE",
+"CONFIG_SSV_TX_LOWTHRESHOLD",
+"RATE_CONTROL_REALTIME_UPDATE",
+"CONFIG_SSV6200_HAS_RX_WORKQUEUE",
+"USE_THREAD_RX",
+"USE_THREAD_TX",
+"ENABLE_AGGREGATE_IN_TIME",
+"ENABLE_INCREMENTAL_AGGREGATION",
+"USE_GENERIC_DECI_TBL",
+"USE_LOCAL_CRYPTO",
+"USE_LOCAL_WEP_CRYPTO",
+"USE_LOCAL_TKIP_CRYPTO",
+"USE_LOCAL_CCMP_CRYPTO",
+"USE_LOCAL_SMS4_CRYPTO",
+"CONFIG_SSV_WAPI",
+"HAS_CRYPTO_LOCK",
+"SSV6200_ECO",
+"CONFIG_SSV_CCI_IMPROVEMENT",
+""};
+#endif // __SSV_CONF_PARSER_H__
diff --git a/drivers/net/wireless/ssv6x5x/include/ssv_data_struct.h b/drivers/net/wireless/ssv6x5x/include/ssv_data_struct.h
new file mode 100644
index 000000000..893ab5eeb
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/include/ssv_data_struct.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV_DATA_STRUCT_H_
+#define _SSV_DATA_STRUCT_H_
+#include <linux/spinlock_types.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+struct ssv6xxx_queue {
+    struct list_head queue;
+    spinlock_t lock;
+};
+struct ssv6xxx_list_node {
+    struct list_head list;
+};
+static inline void tu_ssv6xxx_init_queue(struct ssv6xxx_queue *ssv_queue)
+{
+    INIT_LIST_HEAD(&ssv_queue->queue);
+    spin_lock_init(&ssv_queue->lock);
+}
+static inline void tu_ssv6xxx_init_list_node(struct ssv6xxx_list_node *node)
+{
+    INIT_LIST_HEAD(&node->list);
+}
+static inline void ssv6xxx_enqueue_list_node(struct ssv6xxx_list_node *node, struct ssv6xxx_queue *ssv_queue)
+{
+    unsigned long flags;
+    spin_lock_irqsave(&ssv_queue->lock, flags);
+    list_del_init(&node->list);
+    list_add_tail(&node->list, &ssv_queue->queue);
+    spin_unlock_irqrestore(&ssv_queue->lock, flags);
+}
+static inline struct ssv6xxx_list_node *ssv6xxx_dequeue_list_node(struct ssv6xxx_queue *ssv_queue)
+{
+    unsigned long flags;
+    struct ssv6xxx_list_node *ssv_list_node;
+    spin_lock_irqsave(&ssv_queue->lock, flags);
+    if (list_empty(&ssv_queue->queue)) {
+        ssv_list_node = NULL;
+    } else {
+        ssv_list_node = container_of((&ssv_queue->queue)->next, struct ssv6xxx_list_node, list);
+        list_del_init(&ssv_list_node->list);
+    }
+    spin_unlock_irqrestore(&ssv_queue->lock, flags);
+    return ssv_list_node;
+}
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/include/ssv_firmware_version.h b/drivers/net/wireless/ssv6x5x/include/ssv_firmware_version.h
new file mode 100644
index 000000000..7185a6b33
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/include/ssv_firmware_version.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV_FRIMWARE_VERSION_H_
+#define _SSV_FRIMWARE_VERSION_H_
+static u32 ssv_firmware_version = 17215;
+#define SSV_FIRMWARE_URl "http://192.168.15.30/svn/software/wifi/tag/smac-release-tag/SMAC.0000.1807/ssv6x5x/smac/hal/ssv6006/firmware"
+#define FRIMWARE_COMPILERHOST "willlu-Latitude-E5440"
+#define FRIMWARE_COMPILERDATE "08-09-2018-14:24:22"
+#define FRIMWARE_COMPILEROS "linux"
+#define FRIMWARE_COMPILEROSARCH "x86_64-linux-gnu-thread-multi"
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/include/ssv_mod_conf.h b/drivers/net/wireless/ssv6x5x/include/ssv_mod_conf.h
new file mode 100755
index 000000000..0744939e8
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/include/ssv_mod_conf.h
@@ -0,0 +1,86 @@
+#ifndef __SSV_MOD_CONF_H__
+#define __SSV_MOD_CONF_H__
+#ifndef __CHECK_ENDIAN__
+#define __CHECK_ENDIAN__
+#endif
+#ifndef DEBUG
+#define DEBUG
+#endif
+#ifndef SSV_SUPPORT_HAL
+#define SSV_SUPPORT_HAL
+#endif
+#ifndef SSV_SUPPORT_SSV6006
+#define SSV_SUPPORT_SSV6006
+#endif
+#ifndef CONFIG_SSV_CABRIO_E
+#define CONFIG_SSV_CABRIO_E
+#endif
+#ifndef CONFIG_SSV6200_CLI_ENABLE
+#define CONFIG_SSV6200_CLI_ENABLE
+#endif
+#ifndef CONFIG_SSV_TX_LOWTHRESHOLD
+#define CONFIG_SSV_TX_LOWTHRESHOLD
+#endif
+#ifndef RATE_CONTROL_REALTIME_UPDATE
+#define RATE_CONTROL_REALTIME_UPDATE
+#endif
+#ifndef CONFIG_SSV6200_HAS_RX_WORKQUEUE
+#define CONFIG_SSV6200_HAS_RX_WORKQUEUE
+#endif
+#ifndef USE_THREAD_RX
+#define USE_THREAD_RX
+#endif
+#ifndef USE_THREAD_TX
+#define USE_THREAD_TX
+#endif
+#ifndef ENABLE_AGGREGATE_IN_TIME
+#define ENABLE_AGGREGATE_IN_TIME
+#endif
+#ifndef ENABLE_INCREMENTAL_AGGREGATION
+#define ENABLE_INCREMENTAL_AGGREGATION
+#endif
+#ifndef USE_GENERIC_DECI_TBL
+#define USE_GENERIC_DECI_TBL
+#endif
+#ifndef USE_LOCAL_CRYPTO
+#define USE_LOCAL_CRYPTO
+#endif
+#ifndef USE_LOCAL_WEP_CRYPTO
+#define USE_LOCAL_WEP_CRYPTO
+#endif
+#ifndef USE_LOCAL_TKIP_CRYPTO
+#define USE_LOCAL_TKIP_CRYPTO
+#endif
+#ifndef USE_LOCAL_CCMP_CRYPTO
+#define USE_LOCAL_CCMP_CRYPTO
+#endif
+#ifndef USE_LOCAL_SMS4_CRYPTO
+#define USE_LOCAL_SMS4_CRYPTO
+#endif
+#ifndef CONFIG_SSV_WAPI
+#define CONFIG_SSV_WAPI
+#endif
+#ifndef HAS_CRYPTO_LOCK
+#define HAS_CRYPTO_LOCK
+#endif
+#ifndef SSV6200_ECO
+#define SSV6200_ECO
+#endif
+#ifndef CONFIG_SSV_CCI_IMPROVEMENT
+#define CONFIG_SSV_CCI_IMPROVEMENT
+#endif
+#ifndef REPORT_TX_STATUS_DIRECTLY
+#define REPORT_TX_STATUS_DIRECTLY
+#endif
+#ifndef CONFIG_IRQ_DEBUG_COUNT
+#define CONFIG_IRQ_DEBUG_COUNT
+#endif
+#ifndef CONFIG_SSV6XXX_DEBUGFS
+#define CONFIG_SSV6XXX_DEBUGFS
+#endif
+#define __must_check
+#define __devinit
+#define __devexit
+#define __init
+#define __exit
+#endif // __SSV_MOD_CONF_H__
diff --git a/drivers/net/wireless/ssv6x5x/include/ssv_version.h b/drivers/net/wireless/ssv6x5x/include/ssv_version.h
new file mode 100755
index 000000000..504f4256f
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/include/ssv_version.h
@@ -0,0 +1,13 @@
+#ifndef _SSV_VERSION_H_
+#define _SSV_VERSION_H_
+
+static u32 ssv_root_version = 17680;
+
+#define SSV_ROOT_URl "http://192.168.15.30/svn/software/QA_tags/Ubuntu-PC/SMAC.0000.1807.12.SPUR.90/ssv6x5x"
+#define COMPILERHOST "willlu-Latitude-E5440"
+#define COMPILERDATE "07-04-2019-17:27:36"
+#define COMPILEROS "linux"
+#define COMPILEROSARCH "x86_64-linux-gnu-thread-multi"
+
+#endif
+
diff --git a/drivers/net/wireless/ssv6x5x/kmsg.sh b/drivers/net/wireless/ssv6x5x/kmsg.sh
new file mode 100755
index 000000000..b8e2fc7f8
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/kmsg.sh
@@ -0,0 +1,2 @@
+#/bin/bash
+tail -f /var/log/kern.log
diff --git a/drivers/net/wireless/ssv6x5x/launch_ap_sta.sh b/drivers/net/wireless/ssv6x5x/launch_ap_sta.sh
new file mode 100755
index 000000000..0b648890e
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/launch_ap_sta.sh
@@ -0,0 +1,129 @@
+#!/bin/bash
+
+HOSTPAD_DIR=../../../../3rd-party/hostapd/hostapd2.0/
+WPA_SUPPLICANT_DIR=../../../../3rd-party/wpa_supplicant-2.4/wpa_supplicant
+
+## unload ap
+service isc-dhcp-server stop
+killall dhcpd
+killall hostapd
+killall wpa_supplicant
+
+# load driver
+./load.sh
+
+# find wlan1
+ssv_wlan_1=`script/find_ssv_wlan`
+
+sleep 1
+
+ssv_phy=`script/find_ssv_phy`
+if [ -z "$ssv_phy" ]; then
+    echo SSV PHY device not found.;
+    exit 1;
+fi
+
+ssv_wlan_1=`script/find_ssv_wlan`
+if [ -z "$ssv_wlan_1" ]; then
+    echo SSV primary WLAN device not found.;
+    exit 1;
+fi
+
+echo "Primary SSV WLAN interface is $ssv_wlan_1"
+
+# add wlan2
+ssv_wlan_2=`echo $ssv_wlan_1 | sed -e s/wlan//g`
+ssv_wlan_2=`expr $ssv_wlan_2 + 1`
+ssv_wlan_2="wlan$ssv_wlan_2"
+echo Second WLAN interface is $ssv_wlan_2
+
+echo "Add second interface $ssv_wlan_2 to SSV PHY device $ssv_phy"
+iw $ssv_phy interface add $ssv_wlan_2 type station
+
+sleep 1
+
+ssv_wlans="`script/find_ssv_wlan`"
+for ssv_wlan in $ssv_wlans; do
+    if [ $ssv_wlan != $ssv_wlan_1 ]; then
+        echo Second SSV WLAN device is actually $ssv_wlan
+        break;
+    fi
+done
+
+
+echo -e "${YELLOW}Config wireless AP...${NC}"
+#rm -rf load_dhcp.sh
+#rm -rf hostapd.conf
+#relpace wlan@@ to real device name
+cp script/template/load_dhcp.sh load_dhcp.sh
+
+awk 'NF' script/template/hostapd.conf | grep -v '#' > hostapd.conf
+awk 'NF' ap.cfg | grep -v '#' >> hostapd.conf
+
+sed -i "s/wlan@@/$ssv_wlan_1/" load_dhcp.sh
+sed -i "s/wlan@@/$ssv_wlan_1/" hostapd.conf
+
+chmod 777 load_dhcp.sh
+
+#move to right position
+#mv load_dhcp.sh $HOSTPAD_DIR
+#mv hostapd.conf $HOSTPAD_DIR/hostapd/
+
+dhcp_config_file="/etc/default/isc-dhcp-server"
+dhcp_config=$(grep "$ssv_wlan_1" $dhcp_config_file)
+if [ "$dhcp_config" == "" ]; then
+	echo -en "${YELLOW}Config $dhcp_config_file.....${NC}"
+	
+	rm -rf tmp
+	sed '/INTERFACE/d' /etc/default/isc-dhcp-server >>tmp
+	echo "INTERFACES=\"$ssv_wlan_1\"" >>tmp	
+	rm -rf $dhcp_config_file	
+	mv tmp /etc/default/isc-dhcp-server
+	
+	echo -e "${YELLOW}OK${NC}"
+fi
+	
+	
+dir=$(pwd)
+echo -e "${YELLOW}Wireless Done. ${NC}"
+trap handle_stop INT
+
+function version_great() { test "$(printf '%s\n' "$@" | sort -V | head -n 1)" != "$1"; }
+nmcli_version=$(nmcli -v | cut -d ' ' -f 4)
+chk_nmcli_version=0.9.8.999
+
+function handle_stop() {
+#    popd
+    if version_great $nmcli_version $chk_nmcli_version; then
+        nmcli radio wifi on
+    else
+        nmcli nm wifi on
+    fi
+    
+    echo -e "${YELLOW}Shutting down AP.${NC}"
+    ./ap_shutdown.sh
+}
+        
+
+if version_great $nmcli_version $chk_nmcli_version; then
+    nmcli radio wifi off
+else
+    nmcli nm wifi off
+fi
+
+sudo rfkill unblock wlan
+
+./load_dhcp.sh &
+
+PID=$!
+wait $PID
+
+echo -e "${YELLOW}Load AP...${NC}"
+echo -e "${GREEN}Launch hostapd.${NC}"
+#run hostapd2.0
+$HOSTPAD_DIR/hostapd/hostapd -t hostapd.conf &
+#hostapd -t hostapd.conf
+
+ifconfig $ssv_wlan_2 192.168.1.33 up
+sleep 2
+#$WPA_SUPPLICANT_DIR/wpa_supplicant -Dnl80211 -i $ssv_wlan_2 -c ./wpa_supplicant.conf -dd -B -f /var/log/wpa_supplicant.log
\ No newline at end of file
diff --git a/drivers/net/wireless/ssv6x5x/launch_sta_ap.sh b/drivers/net/wireless/ssv6x5x/launch_sta_ap.sh
new file mode 100755
index 000000000..98dd4066c
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/launch_sta_ap.sh
@@ -0,0 +1,121 @@
+#!/bin/bash
+
+HOSTPAD_DIR=/home/liamhu/svn/3rd-party/hostapd/hostapd2.0
+WPA_SUPPLICANT_DIR=/home/liamhu/wpa_supplicant-2.4/wpa_supplicant
+
+## unload ap
+service isc-dhcp-server stop
+killall dhcpd
+killall hostapd
+killall wpa_supplicant
+
+# load driver
+./load.sh
+
+# find wlan1
+ssv_wlan_1=`script/find_ssv_wlan`
+
+sleep 1
+
+ssv_phy=`script/find_ssv_phy`
+if [ -z "$ssv_phy" ]; then
+    echo SSV PHY device not found.;
+    exit 1;
+fi
+
+ssv_wlan_1=`script/find_ssv_wlan`
+if [ -z "$ssv_wlan_1" ]; then
+    echo SSV primary WLAN device not found.;
+    exit 1;
+fi
+
+echo "Primary SSV WLAN interface is $ssv_wlan_1"
+
+# add wlan2
+ssv_wlan_2=`echo $ssv_wlan_1 | sed -e s/wlan//g`
+ssv_wlan_2=`expr $ssv_wlan_2 + 1`
+ssv_wlan_2="wlan$ssv_wlan_2"
+echo Second WLAN interface is $ssv_wlan_2
+
+echo "Add second interface $ssv_wlan_2 to SSV PHY device $ssv_phy"
+iw $ssv_phy interface add $ssv_wlan_2 type station
+
+sleep 1
+
+ssv_wlans="`script/find_ssv_wlan`"
+for ssv_wlan in $ssv_wlans; do
+    if [ $ssv_wlan != $ssv_wlan_1 ]; then
+        echo Second SSV WLAN device is actually $ssv_wlan
+        break;
+    fi
+done
+
+ifconfig $ssv_wlan_1 192.168.1.33 up
+sleep 2
+$WPA_SUPPLICANT_DIR/wpa_supplicant -Dnl80211 -i $ssv_wlan_1 -c ./wpa_supplicant.conf -dd -B -f /var/log/wpa_supplicant.log
+
+echo -e "${YELLOW}Config wireless AP...${NC}"
+
+cp script/template/load_dhcp.sh load_dhcp.sh
+awk 'NF' script/template/hostapd.conf | grep -v '#' > hostapd.conf
+awk 'NF' ap.cfg | grep -v '#' >> hostapd.conf
+
+sed -i "s/wlan@@/$ssv_wlan/" load_dhcp.sh
+sed -i "s/wlan@@/$ssv_wlan/" hostapd.conf
+
+chmod 777 load_dhcp.sh
+
+dhcp_config_file="/etc/default/isc-dhcp-server"
+dhcp_config=$(grep "$ssv_wlan" $dhcp_config_file)
+if [ "$dhcp_config" == "" ]; then
+	echo -en "${YELLOW}Config $dhcp_config_file.....${NC}"
+	
+	rm -rf tmp
+	sed '/INTERFACE/d' /etc/default/isc-dhcp-server >>tmp
+	echo "INTERFACES=\"$ssv_wlan\"" >>tmp	
+	rm -rf $dhcp_config_file	
+	mv tmp /etc/default/isc-dhcp-server
+	
+	echo -e "${YELLOW}OK${NC}"
+fi
+	
+	
+dir=$(pwd)
+echo -e "${YELLOW}Wireless Done. ${NC}"
+trap handle_stop INT
+
+function version_great() { test "$(printf '%s\n' "$@" | sort -V | head -n 1)" != "$1"; }
+nmcli_version=$(nmcli -v | cut -d ' ' -f 4)
+chk_nmcli_version=0.9.8.999
+
+function handle_stop() {
+#    popd
+    if version_great $nmcli_version $chk_nmcli_version; then
+        nmcli radio wifi on
+    else
+        nmcli nm wifi on
+    fi
+        
+    echo -e "${YELLOW}Shutting down AP.${NC}"
+    ./ap_shutdown.sh
+}
+        
+
+if version_great $nmcli_version $chk_nmcli_version; then
+    nmcli radio wifi off
+else
+    nmcli nm wifi off
+fi
+
+sudo rfkill unblock wlan
+
+./load_dhcp.sh &
+
+PID=$!
+wait $PID
+
+echo -e "${YELLOW}Load AP...${NC}"
+echo -e "${GREEN}Launch hostapd.${NC}"
+#run hostapd2.0
+$HOSTPAD_DIR/hostapd/hostapd -t hostapd.conf
+
diff --git a/drivers/net/wireless/ssv6x5x/linux-build.sh b/drivers/net/wireless/ssv6x5x/linux-build.sh
new file mode 100755
index 000000000..75f909e49
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/linux-build.sh
@@ -0,0 +1,38 @@
+#!/bin/bash
+prompt="Pick the target platform:"
+chip_options=("a33" \
+              "a64" \
+              "h8" \
+              "h3")
+PLATFORM=""
+
+select opt in "${chip_options[@]}" "Quit"; do 
+    case "$REPLY" in
+
+    1 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+    2 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+    3 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+    4 ) echo "${chip_options[$REPLY-1]} is option";PLATFORM=${chip_options[$REPLY-1]};break;;
+
+    $(( ${#chip_options[@]}+1 )) ) echo "Goodbye!"; break;;
+    *) echo "Invalid option. Try another one.";continue;;
+    esac
+done
+
+echo ${chip_options[$REPLY-1]}
+echo $PLATFORM
+exit 0
+
+if [ "$PLATFORM" != "" ]; then
+./ver_info.pl include/ssv_version.h
+cp Makefile.cross_linux Makefile
+cp platforms/${chip_options[$REPLY-1]}.cfg ssv6051.cfg
+cp platforms/platform-config.mak platform-config.mak
+cp platforms/${chip_options[$REPLY-1]}-generic-wlan.c ssv6051-generic-wlan.c
+cp platforms/${chip_options[$REPLY-1]}-wifi.cfg ssv6051-wifi.cfg
+rm -rf platforms
+echo "Done Makefile!"
+else
+echo "Fail!"
+fi
+
diff --git a/drivers/net/wireless/ssv6x5x/load.sh b/drivers/net/wireless/ssv6x5x/load.sh
new file mode 100755
index 000000000..d3682659c
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/load.sh
@@ -0,0 +1,33 @@
+#/bin/bash
+
+echo "=================================================="
+echo "1.Copy firmware"
+echo "=================================================="
+cp image/* /lib/firmware/
+
+echo "=================================================="
+echo "1.Unload Module"
+echo "=================================================="
+./unload.sh
+
+echo "=================================================="
+echo "2.Set Hardware Capability"
+echo "=================================================="
+./ssvcfg.sh
+
+echo "=================================================="
+echo "3.Load MMC Module"
+echo "=================================================="
+
+modprobe sdhci-pci
+modprobe sdhci
+
+modprobe mmc_core sdiomaxclock=25000000
+modprobe mmc_block
+
+modprobe ssv6200_usb
+echo "=================================================="
+echo "4.Load SSV6200 Driver"
+echo "=================================================="
+#modprobe ssv6200_sdio
+
diff --git a/drivers/net/wireless/ssv6x5x/parser-conf.sh b/drivers/net/wireless/ssv6x5x/parser-conf.sh
new file mode 100755
index 000000000..796845d14
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/parser-conf.sh
@@ -0,0 +1,34 @@
+#!/bin/bash
+# Script to convert defines in compiler option in to C's defines
+# Should be executed in make file and it take ccflags-y as the
+# compiler options. The content will be redirected to the first arguement.
+
+temp=$1_temp
+
+echo "#ifndef __SSV_CONF_PARSER_H__" > $temp
+echo "#define __SSV_CONF_PARSER_H__" >> $temp
+
+echo "char const *conf_parser[] = {" >> $temp
+
+for flag in ${ccflags-y}; do
+	if [[ "$flag" =~ ^-D.* ]]; then
+		def=${flag:2}
+        if [[ "$def" =~ .= ]]; then
+            def_1=${def/\=/_}
+            echo "\"$def_1\"," >> $temp
+        else
+		    echo "\"$def\"," >> $temp
+        fi
+	fi
+done
+
+echo "\"\"};" >> $temp
+
+echo "#endif // __SSV_CONF_PARSER_H__" >> $temp
+
+DIFF=$(diff $1 $temp)
+if [ "$DIFF" == "" ]; then
+    rm $temp
+else
+    mv $temp $1
+fi
diff --git a/drivers/net/wireless/ssv6x5x/platform-config.mak b/drivers/net/wireless/ssv6x5x/platform-config.mak
new file mode 100755
index 000000000..fccd042e2
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platform-config.mak
@@ -0,0 +1,7 @@
+
+include $(KBUILD_TOP)/config_common.mak
+
+# SDIO delay chain
+#ccflags-y += -D CONFIG_SSV_SDIO_INPUT_DELAY=0x00000000
+#ccflags-y += -D CONFIG_SSV_SDIO_OUTPUT_DELAY=0x00000000
+
diff --git a/drivers/net/wireless/ssv6x5x/platforms/a33-generic-wlan.c b/drivers/net/wireless/ssv6x5x/platforms/a33-generic-wlan.c
new file mode 100644
index 000000000..3798964fa
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/a33-generic-wlan.c
@@ -0,0 +1,309 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/irq.h>
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/vmalloc.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/pm_runtime.h>
+#include <linux/mmc/host.h>
+#include <linux/delay.h>
+#include <linux/semaphore.h>
+#include <linux/regulator/consumer.h>
+#include <mach/hardware.h>
+#include <asm/io.h>
+#include <mach/sys_config.h>
+#include <linux/power/scenelock.h>
+#ifdef CONFIG_HAS_WAKELOCK
+#include <linux/wakelock.h>
+#endif
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
+#include <linux/printk.h>
+#include <linux/err.h>
+#else
+#include <config/printk.h>
+#endif
+#if LINUX_VERSION_CODE > KERNEL_VERSION(3,2,0)
+#include <linux/wlan_plat.h>
+#else
+struct wifi_platform_data {
+    int (*set_power)(int val);
+    int (*set_reset)(int val);
+    int (*set_carddetect)(int val);
+    void *(*mem_prealloc)(int section, unsigned long size);
+    int (*get_mac_addr)(unsigned char *buf);
+    void *(*get_country_code)(char *ccode);
+};
+#endif
+#ifdef CONFIG_HAS_WAKELOCK
+struct wake_lock icomm_wake_lock;
+#endif
+static int g_wifidev_registered = 0;
+static struct semaphore wifi_control_sem;
+static struct wifi_platform_data *wifi_control_data = NULL;
+#ifdef SSV_WAKEUP_HOST
+static unsigned int g_wifi_irq_rc = 0;
+#endif
+static int sdc_id = -1;
+#define SDIO_ID 1
+#define IRQ_RES_NAME "ssv_wlan_irq"
+#define WIFI_HOST_WAKE 0xFFFF
+extern void sunxi_mci_rescan_card(unsigned id, unsigned insert);
+extern int wifi_pm_gpio_ctrl(char *name, int level);
+extern int enable_wakeup_src(cpu_wakeup_src_e src, int para);
+extern int disable_wakeup_src(cpu_wakeup_src_e src, int para);
+extern void wifi_pm_power(int on);
+static int ssv_wifi_power(int on)
+{
+    printk("ssv pwr on=%d\n", on);
+    if (on) {
+        wifi_pm_power(0);
+        mdelay(50);
+        wifi_pm_power(1);
+    } else {
+        wifi_pm_power(0);
+    }
+    return 0;
+}
+static int ssv_wifi_reset(int on)
+{
+    return 0;
+}
+int ssv_wifi_set_carddetect(int val)
+{
+    sunxi_mci_rescan_card(sdc_id, val);
+    return 0;
+}
+static struct wifi_platform_data ssv_wifi_control = {
+    .set_power = ssv_wifi_power,
+    .set_reset = ssv_wifi_reset,
+    .set_carddetect = ssv_wifi_set_carddetect,
+};
+static struct resource resources[] = {
+    {
+        .start = WIFI_HOST_WAKE,
+        .flags = IORESOURCE_IRQ,
+        .name = IRQ_RES_NAME,
+    },
+};
+void ssv_wifi_device_release(struct device *dev)
+{
+    printk(KERN_INFO "ssv_wifi_device_release\n");
+}
+static struct platform_device ssv_wifi_device = {
+    .name = "ssv_wlan",
+    .id = 1,
+    .num_resources = ARRAY_SIZE(resources),
+    .resource = resources,
+    .dev = {
+        .platform_data = &ssv_wifi_control,
+        .release = ssv_wifi_device_release,
+    },
+};
+int wifi_set_power(int on, unsigned long msec)
+{
+    if (wifi_control_data && wifi_control_data->set_power) {
+        wifi_control_data->set_power(on);
+    }
+    if (msec)
+        msleep(msec);
+    return 0;
+}
+int wifi_set_reset(int on, unsigned long msec)
+{
+    if (wifi_control_data && wifi_control_data->set_reset) {
+        wifi_control_data->set_reset(on);
+    }
+    if (msec)
+        msleep(msec);
+    return 0;
+}
+static int wifi_set_carddetect(int on)
+{
+    if (wifi_control_data && wifi_control_data->set_carddetect) {
+        wifi_control_data->set_carddetect(on);
+    }
+    return 0;
+}
+#ifdef SSV_WAKEUP_HOST
+static irqreturn_t wifi_wakeup_irq_handler(int irq, void *dev)
+{
+    wake_lock_timeout(&icomm_wake_lock, HZ);
+    printk("***** %s ******\n", __func__);
+    return IRQ_HANDLED;
+}
+void setup_wifi_wakeup_BB(struct platform_device *pdev, bool bEnable)
+{
+    int ret = 0;
+    unsigned int oob_irq;
+    unsigned gpio_eint_wlan = 0;
+    bool enable = bEnable;
+    script_item_u val;
+    script_item_value_type_e type;
+    int wakeup_src_cnt = 0;
+    script_item_u *list = NULL;
+    wakeup_src_cnt = script_get_pio_list("wakeup_src_para", &list);
+    pr_err("wakeup src cnt is : %d. \n", wakeup_src_cnt);
+    type = script_get_item("wifi_para", "ssv6051_wl_host_wake", &val);
+    if (SCIRPT_ITEM_VALUE_TYPE_PIO != type || !enable) {
+        printk("No definition of wake up host PIN\n");
+        enable = false;
+    } else {
+        printk("WiFi wake up host PIN:%d=0x%x\n", val.gpio.gpio, val.gpio.gpio);
+        gpio_eint_wlan = val.gpio.gpio;
+        oob_irq = gpio_to_irq(gpio_eint_wlan);
+    }
+    if (enable) {
+        printk("%s: enable irq\n", __FUNCTION__);
+        g_wifi_irq_rc = oob_irq;
+        ret = request_threaded_irq(
+                  oob_irq, NULL, (void *)wifi_wakeup_irq_handler,
+                  IRQ_TYPE_EDGE_FALLING,
+                  "wlan_wakeup_irq", NULL);
+        enable_irq_wake(g_wifi_irq_rc);
+    } else {
+        if (g_wifi_irq_rc) {
+            free_irq(g_wifi_irq_rc, NULL);
+            g_wifi_irq_rc = 0;
+        }
+    }
+}
+#endif
+static int wifi_probe(struct platform_device *pdev)
+{
+    script_item_u val;
+    script_item_value_type_e type;
+    int ret = 0;
+    struct wifi_platform_data *wifi_ctrl =
+        (struct wifi_platform_data *)(pdev->dev.platform_data);
+    printk(KERN_ALERT "wifi_probe\n");
+    wifi_control_data = wifi_ctrl;
+    type = script_get_item("wifi_para", "wifi_sdc_id", &val);
+    if (SCIRPT_ITEM_VALUE_TYPE_INT!=type) {
+        printk("get wifi_sdc_id failed\n");
+        ret = -1;
+    } else {
+        sdc_id = val.val;
+    }
+    wifi_set_power(0, 40);
+    wifi_set_power(1, 50);
+    wifi_set_carddetect(1);
+#ifdef SSV_WAKEUP_HOST
+    setup_wifi_wakeup_BB(pdev, true);
+#endif
+    up(&wifi_control_sem);
+    return ret;
+}
+static int wifi_remove(struct platform_device *pdev)
+{
+    struct wifi_platform_data *wifi_ctrl =
+        (struct wifi_platform_data *)(pdev->dev.platform_data);
+    wifi_control_data = wifi_ctrl;
+#ifdef SSV_WAKEUP_HOST
+    setup_wifi_wakeup_BB(pdev, false);
+#endif
+    wifi_set_power(0, 0);
+    wifi_set_power(0, 0);
+    wifi_set_power(0, 0);
+    wifi_set_power(0, 0);
+    wifi_set_carddetect(0);
+    return 0;
+}
+static int wifi_suspend(struct platform_device *pdev, pm_message_t state)
+{
+    printk("%s\n", __FUNCTION__);
+    return 0;
+}
+static int wifi_resume(struct platform_device *pdev)
+{
+    printk("%s\n", __FUNCTION__);
+    sunxi_mci_rescan_card(sdc_id, 1);
+    wake_lock_timeout(&icomm_wake_lock, 5 * HZ);
+    return 0;
+}
+static struct platform_driver wifi_driver = {
+    .probe = wifi_probe,
+    .remove = wifi_remove,
+    .suspend = wifi_suspend,
+    .resume = wifi_resume,
+    .driver = {
+        .name = "ssv_wlan",
+    }
+};
+extern int tu_ssvdevice_init(void);
+extern void tu_ssvdevice_exit(void);
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+extern int aes_init(void);
+extern void aes_fini(void);
+extern int sha1_mod_init(void);
+extern void sha1_mod_fini(void);
+#endif
+int initWlan(void)
+{
+    int ret = 0;
+#ifdef CONFIG_HAS_WAKELOCK
+    wake_lock_init(&icomm_wake_lock, WAKE_LOCK_SUSPEND, "ssv6051");
+    wake_lock(&icomm_wake_lock);
+#endif
+    sema_init(&wifi_control_sem, 0);
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+    sha1_mod_init();
+    aes_init();
+#endif
+    platform_device_register(&ssv_wifi_device);
+    platform_driver_register(&wifi_driver);
+    g_wifidev_registered = 1;
+    if (down_timeout(&wifi_control_sem, msecs_to_jiffies(1000)) != 0) {
+        ret = -EINVAL;
+        printk(KERN_ALERT "%s: platform_driver_register timeout\n", __FUNCTION__);
+    }
+    ret = tu_ssvdevice_init();
+#ifdef CONFIG_HAS_WAKELOCK
+    wake_unlock(&icomm_wake_lock);
+#endif
+    return ret;
+}
+void exitWlan(void)
+{
+    if (g_wifidev_registered) {
+        tu_ssvdevice_exit();
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+        aes_fini();
+        sha1_mod_fini();
+#endif
+        platform_driver_unregister(&wifi_driver);
+        platform_device_unregister(&ssv_wifi_device);
+        g_wifidev_registered = 0;
+    }
+#ifdef CONFIG_HAS_WAKELOCK
+    wake_lock_destroy(&icomm_wake_lock);
+#endif
+    return;
+}
+static int tu_generic_wifi_init_module(void)
+{
+    return initWlan();
+}
+static void tu_generic_wifi_exit_module(void)
+{
+    exitWlan();
+}
+EXPORT_SYMBOL(tu_generic_wifi_init_module);
+EXPORT_SYMBOL(tu_generic_wifi_exit_module);
+module_init(tu_generic_wifi_init_module);
+module_exit(tu_generic_wifi_exit_module);
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/drivers/net/wireless/ssv6x5x/platforms/a33-wifi.cfg b/drivers/net/wireless/ssv6x5x/platforms/a33-wifi.cfg
new file mode 100755
index 000000000..6f28d7776
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/a33-wifi.cfg
@@ -0,0 +1,89 @@
+############################################################
+# A33
+# WIFI-CONFIGURATION
+##################################################
+
+##################################################
+# Firmware setting
+# Priority.1 insmod parameter "cfgfirmwarepath"
+# Priority.2 firmware_path
+# Priority.3 default firmware
+##################################################
+firmware_path = /etc/firmware/
+
+############################################################
+# MAC address
+#
+# Priority 1. From wifi.cfg [ hw_mac & hw_mac_2 ]
+#
+# Priority 2. From e-fuse[ON/OFF switch by wifi.cfg]
+#
+# Priority 3. From insert module parameter
+#
+# Priority 4. From external file path
+#   path only support some special charater "_" ":" "/" "." "-"
+#
+# Priority 5. Default[Software mode]
+#
+#   0. => 00:33:33:33:33:33
+#   1. => Always random
+#   2. => First random and write to file[Default path mac_output_path]
+#
+############################################################
+ignore_efuse_mac = 1
+mac_address_path = /mnt/private/ULI/factory/mac.txt
+mac_address_mode = 2
+mac_output_path = /data/wifimac
+
+##################################################
+# Hardware setting
+#
+#volt regulator(DCDC-0 LDO-1)
+#
+##################################################
+volt_regulator = 1
+
+##################################################
+# Default channel after wifi on
+# value range: [1 ~ 14]
+##################################################
+#def_chan = 6
+##################################################
+# Hardware Capability Settings:
+##################################################
+hw_cap_ampdu_rx = on
+hw_cap_ampdu_tx = on
+hw_cap_tdls = off
+
+use_wpa2_only = 1
+##################################################
+# TX power level setting [0-14]
+# The larger the number the smaller the TX power
+# 0 - The maximum power
+# 1 level = -0.5db
+#
+# 6051Z .. 4 or 4
+# 6051Q .. 2 or 5
+# 6051P .. 0 or 0
+#
+##################################################
+# High PA
+#wifi_tx_gain_level_b = 4
+#wifi_tx_gain_level_gn = 2
+#register = CE010018:02457D79
+
+# Normal PA
+#wifi_tx_gain_level_b = 4
+#wifi_tx_gain_level_gn = 4
+
+##################################################
+# Import extenal configuration(UP to 64 groups)
+# example:
+#    register = CE010010:91919191
+#    register = 00CC0010:00091919
+##################################################
+
+##################################################
+# The AP RSSI signal is less than -88dbm complement signal to -88dbm
+##################################################
+#beacon_rssi_minimal = 88
diff --git a/drivers/net/wireless/ssv6x5x/platforms/a33.cfg b/drivers/net/wireless/ssv6x5x/platforms/a33.cfg
new file mode 100755
index 000000000..608633b6d
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/a33.cfg
@@ -0,0 +1,17 @@
+############################################################
+# A33
+############################################################
+ccflags-y += -DCONFIG_SSV_SUPPORT_ANDROID
+#ccflags-y += -DCONFIG_SSV_SUPPORT_AES_ASM
+ccflags-y += -DCONFIG_FW_ALIGNMENT_CHECK
+ccflags-y += -DCONFIG_PLATFORM_SDIO_OUTPUT_TIMING=3
+#ccflags-y += -DMULTI_THREAD_ENCRYPT
+#ccflags-y += -DKTHREAD_BIND
+
+############################################################
+# Compiler path
+############################################################
+SSV_CROSS = $(ANDROID_BUILD_TOP)/../lichee/out/sun8iw5p1/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi-
+SSV_KERNEL_PATH = $(ANDROID_BUILD_TOP)/../lichee/linux-3.4
+SSV_ARCH = arm
+KMODDESTDIR = $(MODDESTDIR)
diff --git a/drivers/net/wireless/ssv6x5x/platforms/ak3916-generic-wlan.c b/drivers/net/wireless/ssv6x5x/platforms/ak3916-generic-wlan.c
new file mode 100644
index 000000000..76f3694ca
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/ak3916-generic-wlan.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/vmalloc.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/regulator/consumer.h>
+#include <asm/io.h>
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
+#include <linux/printk.h>
+#include <linux/err.h>
+#else
+#include <config/printk.h>
+#endif
+extern int tu_ssvdevice_init(void);
+extern void tu_ssvdevice_exit(void);
+int initWlan(void)
+{
+    int ret=0;
+    printk(KERN_INFO "wlan.c initWlan\n");
+    ret = tu_ssvdevice_init();
+    return ret;
+}
+void exitWlan(void)
+{
+    tu_ssvdevice_exit();
+    return;
+}
+static int tu_generic_wifi_init_module(void)
+{
+    return initWlan();
+}
+static void tu_generic_wifi_exit_module(void)
+{
+    exitWlan();
+}
+EXPORT_SYMBOL(tu_generic_wifi_init_module);
+EXPORT_SYMBOL(tu_generic_wifi_exit_module);
+#ifdef CONFIG_SSV6X5X
+late_initcall(tu_generic_wifi_init_module);
+#else
+module_init(tu_generic_wifi_init_module);
+#endif
+module_exit(tu_generic_wifi_exit_module);
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/drivers/net/wireless/ssv6x5x/platforms/ak3916-wifi.cfg b/drivers/net/wireless/ssv6x5x/platforms/ak3916-wifi.cfg
new file mode 100755
index 000000000..dd3cf373b
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/ak3916-wifi.cfg
@@ -0,0 +1,94 @@
+############################################################
+# Anyka 3916
+# WIFI-CONFIGURATION
+##################################################
+
+hw_mac = 00:a5:b5:39:16:00
+hw_mac_2 = 00:a5:b5:39:16:01
+
+##################################################
+# Firmware setting
+# Priority.1 insmod parameter "cfgfirmwarepath"
+# Priority.2 firmware_path
+# Priority.3 default firmware
+##################################################
+firmware_path = /usr/modules/
+
+############################################################
+# MAC address
+#
+# Priority 1. From wifi.cfg [ hw_mac & hw_mac_2 ]
+#
+# Priority 2. From e-fuse[ON/OFF switch by wifi.cfg]
+#
+# Priority 3. From insert module parameter
+#
+# Priority 4. From external file path
+#   path only support some special charater "_" ":" "/" "." "-"
+#
+# Priority 5. Default[Software mode]
+#
+#   0. => 00:33:33:33:33:33
+#   1. => Always random
+#   2. => First random and write to file[Default path mac_output_path]
+#
+############################################################
+#ignore_efuse_mac = 1
+#mac_address_path = /xxxx/xxxx
+#mac_address_mode = 2
+#mac_output_path = /data/wifimac
+
+##################################################
+# Hardware setting
+#
+#volt regulator(DCDC-0 LDO-1)
+#
+##################################################
+xtal_clock = 40
+volt_regulator = 1
+
+##################################################
+# Default channel after wifi on
+# value range: [1 ~ 14]
+##################################################
+#def_chan = 6
+##################################################
+# Hardware Capability Settings:
+##################################################
+hw_cap_ampdu_rx = on
+hw_cap_ampdu_tx = on
+hw_cap_tdls = off
+hw_cap_5ghz = off
+
+use_wpa2_only = 1
+##################################################
+# TX power level setting [0-14]
+# The larger the number the smaller the TX power
+# 0 - The maximum power
+# 1 level = -0.5db
+#
+# 6051Z .. 4 or 4
+# 6051Q .. 2 or 5
+# 6051P .. 0 or 0
+#
+##################################################
+#wifi_tx_gain_level_b = 2
+#wifi_tx_gain_level_gn = 5
+
+##################################################
+# Import extenal configuration(UP to 64 groups)
+# example:
+#    register = CE010010:91919191
+#    register = 00CC0010:00091919
+##################################################
+
+##################################################
+# The AP RSSI signal is less than -88dbm complement signal to -88dbm
+##################################################
+#beacon_rssi_minimal = 88
+
+##################################################
+# Direct Ack Threshold Settings:
+##################################################
+directly_ack_low_threshold = 64
+directly_ack_high_threshold = 512
diff --git a/drivers/net/wireless/ssv6x5x/platforms/ak3916.cfg b/drivers/net/wireless/ssv6x5x/platforms/ak3916.cfg
new file mode 100755
index 000000000..fdac6011a
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/ak3916.cfg
@@ -0,0 +1,23 @@
+############################################################
+# Anyka 3916
+############################################################
+
+#ccflags-y += -DCONFIG_SSV_SUPPORT_ANDROID
+ccflags-y += -DCONFIG_SSV_BUILD_AS_ONE_KO
+#ccflags-y += -DCONFIG_SSV_SUPPORT_AES_ASM
+ccflags-y += -DCONFIG_FW_ALIGNMENT_CHECK
+ccflags-y += -DCONFIG_PLATFORM_SDIO_OUTPUT_TIMING=0
+
+#ccflags-y += -DCONFIG_SMARTLINK
+############################################################
+# SSV Airkiss
+############################################################
+#cflags-y += -DCONFIG_SSV_SMARTLINK
+
+############################################################
+# Compiler path
+############################################################
+#SSV_CROSS = $(R_CROSS_COMPILE)
+#SSV_KERNEL_PATH = $(KERNEL_BUILD_PATH)
+#SSV_ARCH = $(R_ARCH)
+#KMODDESTDIR = $(MODDESTDIR)
diff --git a/drivers/net/wireless/ssv6x5x/platforms/aml-s805-generic-wlan.c b/drivers/net/wireless/ssv6x5x/platforms/aml-s805-generic-wlan.c
new file mode 100644
index 000000000..87a90cf7d
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/aml-s805-generic-wlan.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/irq.h>
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/vmalloc.h>
+#include <linux/gpio.h>
+#include <linux/mmc/host.h>
+#include <linux/delay.h>
+#include <linux/regulator/consumer.h>
+#include <linux/semaphore.h>
+#include <asm/io.h>
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
+#include <linux/printk.h>
+#include <linux/err.h>
+#else
+#include <config/printk.h>
+#endif
+extern void sdio_reinit(void);
+extern void extern_wifi_set_enable(int is_on);
+extern int wifi_setup_dt(void);
+#define GPIO_REG_WRITEL(val,reg) do{__raw_writel(val, CTL_PIN_BASE + (reg));}while(0)
+struct semaphore icomm_chipup_sem;
+static int g_wifidev_registered = 0;
+char ssvcabrio_fw_name[50] = "ssv6051-sw.bin";
+extern int tu_ssvdevice_init(void);
+extern void tu_ssvdevice_exit(void);
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+extern int aes_init(void);
+extern void aes_fini(void);
+extern int sha1_mod_init(void);
+extern void sha1_mod_fini(void);
+#endif
+int initWlan(void)
+{
+    int ret=0;
+    if (wifi_setup_dt()) {
+        printk("wifi_dt : fail to setup dt\n");
+        goto fail;
+    }
+    extern_wifi_set_enable(0);
+    mdelay(200);
+    extern_wifi_set_enable(1);
+    mdelay(200);
+    sdio_reinit();
+    mdelay(100);
+    g_wifidev_registered = 1;
+fail:
+    up(&icomm_chipup_sem);
+    return ret;
+}
+void exitWlan(void)
+{
+    if (g_wifidev_registered) {
+        tu_ssvdevice_exit();
+        extern_wifi_set_enable(0);
+        g_wifidev_registered = 0;
+    }
+    return;
+}
+static __init int tu_generic_wifi_init_module(void)
+{
+    int ret;
+    printk("%s\n", __func__);
+    sema_init(&icomm_chipup_sem, 0);
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+    sha1_mod_init();
+    aes_init();
+#endif
+    ret = initWlan();
+    if (down_timeout(&icomm_chipup_sem,
+                     msecs_to_jiffies(1000)) != 0) {
+        ret = -EINVAL;
+        printk(KERN_ALERT "%s: platform_driver_register timeout\n", __FUNCTION__);
+        goto out;
+    }
+    ret = tu_ssvdevice_init();
+out:
+    return ret;
+}
+static __exit void tu_generic_wifi_exit_module(void)
+{
+    printk("%s\n", __func__);
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+    aes_fini();
+    sha1_mod_fini();
+#endif
+    exitWlan();
+}
+EXPORT_SYMBOL(tu_generic_wifi_init_module);
+EXPORT_SYMBOL(tu_generic_wifi_exit_module);
+module_init(tu_generic_wifi_init_module);
+module_exit(tu_generic_wifi_exit_module);
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/drivers/net/wireless/ssv6x5x/platforms/aml-s805-wifi.cfg b/drivers/net/wireless/ssv6x5x/platforms/aml-s805-wifi.cfg
new file mode 100755
index 000000000..c77fd9ef1
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/aml-s805-wifi.cfg
@@ -0,0 +1,83 @@
+############################################################
+# S805
+# WIFI-CONFIGURATION
+##################################################
+
+##################################################
+# Firmware setting
+# Priority.1 insmod parameter "cfgfirmwarepath"
+# Priority.2 firmware_path
+# Priority.3 default firmware
+##################################################
+#firmware_path = /etc/firmware/
+
+############################################################
+# MAC address
+#
+# Priority 1. From wifi.cfg [ hw_mac & hw_mac_2 ]
+#
+# Priority 2. From e-fuse[ON/OFF switch by wifi.cfg]
+#
+# Priority 3. From insert module parameter
+#
+# Priority 4. From external file path
+#   path only support some special charater "_" ":" "/" "." "-"
+#
+# Priority 5. Default[Software mode]
+#
+#   0. => 00:33:33:33:33:33
+#   1. => Always random
+#   2. => First random and write to file[Default path mac_output_path]
+#
+############################################################
+ignore_efuse_mac = 0
+#mac_address_path = /xxxx/xxxx
+mac_address_mode = 2
+mac_output_path = /data/wifimac
+
+##################################################
+# Hardware setting
+#
+#volt regulator(DCDC-0 LDO-1)
+#
+##################################################
+volt_regulator = 1
+
+##################################################
+# Default channel after wifi on
+# value range: [1 ~ 14]
+##################################################
+#def_chan = 6
+##################################################
+# Hardware Capability Settings:
+##################################################
+hw_cap_ampdu_rx = on
+hw_cap_ampdu_tx = on
+hw_cap_tdls = off
+
+use_wpa2_only = 1
+##################################################
+# TX power level setting [0-14]
+# The larger the number the smaller the TX power
+# 0 - The maximum power
+# 1 level = -0.5db
+#
+# 6051Z .. 4 or 4
+# 6051Q .. 2 or 5
+# 6051P .. 0 or 0
+#
+##################################################
+#wifi_tx_gain_level_b = 2
+#wifi_tx_gain_level_gn = 5
+
+##################################################
+# Import extenal configuration(UP to 64 groups)
+# example:
+#    register = CE010010:91919191
+#    register = 00CC0010:00091919
+##################################################
+
+##################################################
+# The AP RSSI signal is less than -88dbm complement signal to -88dbm
+##################################################
+#beacon_rssi_minimal = 88
diff --git a/drivers/net/wireless/ssv6x5x/platforms/aml-s805.cfg b/drivers/net/wireless/ssv6x5x/platforms/aml-s805.cfg
new file mode 100755
index 000000000..1358a7b31
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/aml-s805.cfg
@@ -0,0 +1,21 @@
+############################################################
+# amlogic m201 s805
+############################################################
+ccflags-y += -DCONFIG_SSV_SUPPORT_ANDROID
+#ccflags-y += -DCONFIG_SSV_SUPPORT_AES_ASM
+ccflags-y += -DCONFIG_FW_ALIGNMENT_CHECK
+ccflags-y += -DCONFIG_PLATFORM_SDIO_OUTPUT_TIMING=3
+ccflags-y += -DCONFIG_PLATFORM_SDIO_BLOCK_SIZE=128
+#ccflags-y += -DMULTI_THREAD_ENCRYPT
+
+############################################################
+# Compiler path
+############################################################
+SSV_CROSS = arm-linux-gnueabihf-
+#SSV_CROSS = $(ANDROID_BUILD_TOP)/prebuilts/gcc/linux-x86/arm/arm-eabi-4.7/bin/arm-eabi-
+SSV_KERNEL_PATH = $(ANDROID_BUILD_TOP)/out/target/product/m201/obj/KERNEL_OBJ/
+#SSV_CROSS = $(ANDROID_BUILD_TOP)/prebuilts/gcc/linux-x86/arm/arm-eabi-4.7/bin/arm-eabi-
+#SSV_KERNEL_PATH = $(ANDROID_BUILD_TOP)/hardware/wifi/icomm/drivers/ssv6xxx/
+SSV_ARCH = arm
+KMODDESTDIR = $(MODDESTDIR)
+
diff --git a/drivers/net/wireless/ssv6x5x/platforms/aml-s905-generic-wlan.c b/drivers/net/wireless/ssv6x5x/platforms/aml-s905-generic-wlan.c
new file mode 100644
index 000000000..3078c437c
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/aml-s905-generic-wlan.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/irq.h>
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/vmalloc.h>
+#include <linux/gpio.h>
+#include <linux/mmc/host.h>
+#include <linux/delay.h>
+#include <linux/regulator/consumer.h>
+#include <linux/semaphore.h>
+#include <asm/io.h>
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
+#include <linux/printk.h>
+#include <linux/err.h>
+#else
+#include <config/printk.h>
+#endif
+extern void sdio_reinit(void);
+extern void extern_wifi_set_enable(int is_on);
+extern int wifi_setup_dt(void);
+#define GPIO_REG_WRITEL(val,reg) \
+ do { \
+  __raw_writel(val, CTL_PIN_BASE + (reg)); \
+ } while (0)
+struct semaphore icomm_chipup_sem;
+static int g_wifidev_registered = 0;
+char ssvcabrio_fw_name[50] = "ssv6051-sw.bin";
+extern int tu_ssvdevice_init(void);
+extern void tu_ssvdevice_exit(void);
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+extern int aes_init(void);
+extern void aes_fini(void);
+extern int sha1_mod_init(void);
+extern void sha1_mod_fini(void);
+#endif
+int initWlan(void)
+{
+    int ret = 0;
+    extern_wifi_set_enable(0);
+    mdelay(100);
+    extern_wifi_set_enable(1);
+    mdelay(100);
+    sdio_reinit();
+    mdelay(100);
+    g_wifidev_registered = 1;
+    up(&icomm_chipup_sem);
+    return ret;
+}
+void exitWlan(void)
+{
+    if (g_wifidev_registered) {
+        tu_ssvdevice_exit();
+        extern_wifi_set_enable(0);
+        g_wifidev_registered = 0;
+    }
+    return;
+}
+static __init int tu_generic_wifi_init_module(void)
+{
+    int ret;
+    printk("%s\n", __func__);
+    sema_init(&icomm_chipup_sem, 0);
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+    sha1_mod_init();
+    aes_init();
+#endif
+    ret = initWlan();
+    if (down_timeout(&icomm_chipup_sem, msecs_to_jiffies(1000)) != 0) {
+        ret = -EINVAL;
+        printk(KERN_ALERT "%s: platform_driver_register timeout\n",
+               __FUNCTION__);
+        goto out;
+    }
+    ret = tu_ssvdevice_init();
+out:
+    return ret;
+}
+static __exit void tu_generic_wifi_exit_module(void)
+{
+    printk("%s\n", __func__);
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+    aes_fini();
+    sha1_mod_fini();
+#endif
+    exitWlan();
+}
+EXPORT_SYMBOL(tu_generic_wifi_init_module);
+EXPORT_SYMBOL(tu_generic_wifi_exit_module);
+module_init(tu_generic_wifi_init_module);
+module_exit(tu_generic_wifi_exit_module);
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/drivers/net/wireless/ssv6x5x/platforms/aml-s905-wifi.cfg b/drivers/net/wireless/ssv6x5x/platforms/aml-s905-wifi.cfg
new file mode 100755
index 000000000..a624b6c79
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/aml-s905-wifi.cfg
@@ -0,0 +1,89 @@
+############################################################
+# S905
+# WIFI-CONFIGURATION
+##################################################
+
+##################################################
+# Firmware setting
+# Priority.1 insmod parameter "cfgfirmwarepath"
+# Priority.2 firmware_path
+# Priority.3 default firmware
+##################################################
+firmware_path = /etc/wifi/ssv/
+
+############################################################
+# MAC address
+#
+# Priority 1. From wifi.cfg [ hw_mac & hw_mac_2 ]
+#
+# Priority 2. From e-fuse[ON/OFF switch by wifi.cfg]
+#
+# Priority 3. From insert module parameter
+#
+# Priority 4. From external file path
+#   path only support some special charater "_" ":" "/" "." "-"
+#
+# Priority 5. Default[Software mode]
+#
+#   0. => 00:33:33:33:33:33
+#   1. => Always random
+#   2. => First random and write to file[Default path mac_output_path]
+#
+############################################################
+ignore_efuse_mac = 0
+#mac_address_path = /xxxx/xxxx
+mac_address_mode = 2
+mac_output_path = /data/wifimac
+
+##################################################
+# Hardware setting
+#
+#volt regulator(DCDC-0 LDO-1)
+#
+##################################################
+volt_regulator = 1
+
+##################################################
+# Default channel after wifi on
+# value range: [1 ~ 14]
+##################################################
+#def_chan = 6
+##################################################
+# Hardware Capability Settings:
+##################################################
+hw_cap_ampdu_rx = on
+hw_cap_ampdu_tx = on
+hw_cap_tdls = off
+
+use_wpa2_only = 1
+##################################################
+# TX power level setting [0-14]
+# The larger the number the smaller the TX power
+# 0 - The maximum power
+# 1 level = -0.5db
+#
+# 6051Z .. 4 or 4
+# 6051Q .. 2 or 5
+# 6051P .. 0 or 0
+#
+##################################################
+#wifi_tx_gain_level_b = 2
+#wifi_tx_gain_level_gn = 5
+
+##################################################
+# Import extenal configuration(UP to 64 groups)
+# example:
+#    register = CE010010:91919191
+#    register = 00CC0010:00091919
+##################################################
+
+##################################################
+# The AP RSSI signal is less than -88dbm complement signal to -88dbm
+##################################################
+#beacon_rssi_minimal = 88
+
+##################################################
+# Direct Ack Threshold Settings:
+##################################################
+directly_ack_low_threshold = 64
+directly_ack_high_threshold = 512
diff --git a/drivers/net/wireless/ssv6x5x/platforms/aml-s905.cfg b/drivers/net/wireless/ssv6x5x/platforms/aml-s905.cfg
new file mode 100755
index 000000000..25c738a83
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/aml-s905.cfg
@@ -0,0 +1,23 @@
+############################################################
+# amlogic s905
+############################################################
+ccflags-y += -DCONFIG_SSV_SUPPORT_ANDROID
+#ccflags-y += -DCONFIG_SSV_SUPPORT_AES_ASM
+ccflags-y += -DCONFIG_FW_ALIGNMENT_CHECK
+ccflags-y += -DCONFIG_PLATFORM_SDIO_OUTPUT_TIMING=3
+ccflags-y += -DCONFIG_PLATFORM_SDIO_BLOCK_SIZE=128
+#ccflags-y += -DMULTI_THREAD_ENCRYPT
+ccflags-y += -DCONFIG_SSV_OPENFILE_LOADFW
+ccflags-y += -DPLATFORM_FORCE_DISABLE_AMPDU_FLOW_CONTROL
+
+############################################################
+# Compiler path
+############################################################
+#SSV_CROSS = arm-linux-gnueabihf-
+#SSV_CROSS = $(ANDROID_BUILD_TOP)/prebuilts/gcc/linux-x86/arm/arm-eabi-4.7/bin/arm-eabi-
+#SSV_KERNEL_PATH = $(ANDROID_BUILD_TOP)/out/target/product/m201/obj/KERNEL_OBJ/
+#SSV_CROSS = $(ANDROID_BUILD_TOP)/prebuilts/gcc/linux-x86/arm/arm-eabi-4.7/bin/arm-eabi-
+#SSV_KERNEL_PATH = $(ANDROID_BUILD_TOP)/hardware/wifi/icomm/drivers/ssv6xxx/
+SSV_ARCH = arm64
+#KMODDESTDIR = $(MODDESTDIR)
+
diff --git a/drivers/net/wireless/ssv6x5x/platforms/aml-t920-wifi.cfg b/drivers/net/wireless/ssv6x5x/platforms/aml-t920-wifi.cfg
new file mode 100755
index 000000000..e2660d847
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/aml-t920-wifi.cfg
@@ -0,0 +1,96 @@
+############################################################
+# T920
+# WIFI-CONFIGURATION
+##################################################
+
+##################################################
+# Firmware setting
+# Priority.1 insmod parameter "cfgfirmwarepath"
+# Priority.2 firmware_path
+# Priority.3 default firmware
+##################################################
+firmware_path = /etc/wifi/ssv6x5x/
+
+############################################################
+# MAC address
+#
+# Priority 1. From wifi.cfg [ hw_mac & hw_mac_2 ]
+#
+# Priority 2. From e-fuse[ON/OFF switch by wifi.cfg]
+#
+# Priority 3. From insert module parameter
+#
+# Priority 4. From external file path
+#   path only support some special charater "_" ":" "/" "." "-"
+#
+# Priority 5. Default[Software mode]
+#
+#   0. => 00:33:33:33:33:33
+#   1. => Always random
+#   2. => First random and write to file[Default path mac_output_path]
+#
+############################################################
+ignore_efuse_mac = 1
+#mac_address_path = /xxxx/xxxx
+mac_address_mode = 2
+mac_output_path = /data/wifimac
+
+##################################################
+# Hardware setting
+#
+#volt regulator(DCDC-0 LDO-1)
+#
+##################################################
+#xtal_clock = 25
+volt_regulator = 1
+
+##################################################
+# Default channel after wifi on
+# value range: [1 ~ 14]
+##################################################
+#def_chan = 6
+##################################################
+# Hardware Capability Settings:
+##################################################
+hw_cap_ampdu_rx = on
+hw_cap_ampdu_tx = on
+hw_cap_5ghz = off
+hw_cap_tdls = off
+
+use_wpa2_only = 1
+##################################################
+# TX power level setting [0-14]
+# The larger the number the smaller the TX power
+# 0 - The maximum power
+# 1 level = -0.5db
+#
+# 6051Z .. 4 or 4
+# 6051Q .. 2 or 5
+# 6051P .. 0 or 0
+#
+##################################################
+#wifi_tx_gain_level_b = 2
+#wifi_tx_gain_level_gn = 5
+
+##################################################
+# Import extenal configuration(UP to 64 groups)
+# example:
+#    register = CE010010:91919191
+#    register = 00CC0010:00091919
+##################################################
+
+##################################################
+# The AP RSSI signal is less than -88dbm complement signal to -88dbm
+##################################################
+#beacon_rssi_minimal = 88
+
+##################################################
+# Direct Ack Threshold Settings:
+##################################################
+directly_ack_low_threshold = 64
+directly_ack_high_threshold = 512
+
+##################################################
+# TXRX SKBQ Threshold Settings:
+##################################################
+rx_threshold = 128
diff --git a/drivers/net/wireless/ssv6x5x/platforms/aml-t920.cfg b/drivers/net/wireless/ssv6x5x/platforms/aml-t920.cfg
new file mode 100755
index 000000000..8af3f674b
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/aml-t920.cfg
@@ -0,0 +1,23 @@
+############################################################
+# amlogic t920
+############################################################
+ccflags-y += -DCONFIG_SSV_SUPPORT_ANDROID
+#ccflags-y += -DCONFIG_SSV_SUPPORT_AES_ASM
+ccflags-y += -DCONFIG_FW_ALIGNMENT_CHECK
+ccflags-y += -DCONFIG_PLATFORM_SDIO_OUTPUT_TIMING=3
+ccflags-y += -DCONFIG_PLATFORM_SDIO_BLOCK_SIZE=128
+#ccflags-y += -DMULTI_THREAD_ENCRYPT
+ccflags-y += -DCONFIG_SSV_OPENFILE_LOADFW
+ccflags-y += -DPLATFORM_FORCE_DISABLE_AMPDU_FLOW_CONTROL
+
+############################################################
+# Compiler path
+############################################################
+#SSV_CROSS = arm-linux-gnueabihf-
+#SSV_CROSS = $(ANDROID_BUILD_TOP)/prebuilts/gcc/linux-x86/arm/arm-eabi-4.7/bin/arm-eabi-
+#SSV_KERNEL_PATH = $(ANDROID_BUILD_TOP)/out/target/product/m201/obj/KERNEL_OBJ/
+#SSV_CROSS = $(ANDROID_BUILD_TOP)/prebuilts/gcc/linux-x86/arm/arm-eabi-4.7/bin/arm-eabi-
+#SSV_KERNEL_PATH = $(ANDROID_BUILD_TOP)/hardware/wifi/icomm/drivers/ssv6xxx/
+SSV_ARCH = arm64
+#KMODDESTDIR = $(MODDESTDIR)
+
diff --git a/drivers/net/wireless/ssv6x5x/platforms/atm7039-action-generic-wlan.c b/drivers/net/wireless/ssv6x5x/platforms/atm7039-action-generic-wlan.c
new file mode 100644
index 000000000..be7a386c4
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/atm7039-action-generic-wlan.c
@@ -0,0 +1,266 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/irq.h>
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/vmalloc.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/pm_runtime.h>
+#include <linux/mmc/host.h>
+#include <linux/delay.h>
+#include <linux/semaphore.h>
+#include <linux/regulator/consumer.h>
+#include <mach/hardware.h>
+#include <asm/io.h>
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
+#include <linux/printk.h>
+#include <linux/err.h>
+#else
+#include <config/printk.h>
+#endif
+#if LINUX_VERSION_CODE > KERNEL_VERSION(3, 2, 0)
+#include <linux/wlan_plat.h>
+#else
+struct wifi_platform_data {
+    int (*set_power)(int val);
+    int (*set_reset)(int val);
+    int (*set_carddetect)(int val);
+    void *(*mem_prealloc)(int section, unsigned long size);
+    int (*get_mac_addr)(unsigned char *buf);
+    void *(*get_country_code)(char *ccode);
+};
+#endif
+#include <mach/wlan_plat_data.h>
+extern int acts_wifi_init(int type);
+extern void acts_wifi_cleanup(void);
+int platform_wifi_power_on(void)
+{
+    int ret = 0;
+    int wifi_type = 0;
+    wifi_type = WLAN_SSV6051;
+    ret = acts_wifi_init(wifi_type);
+    if (unlikely(ret < 0)) {
+        pr_err("SSV6051: Failed to register the power control driver.\n");
+        goto exit;
+    }
+exit:
+    return ret;
+}
+void platform_wifi_power_off(void)
+{
+    acts_wifi_cleanup();
+}
+static int g_wifidev_registered = 0;
+static struct semaphore wifi_control_sem;
+static struct wifi_platform_data *wifi_control_data = NULL;
+static struct resource *wifi_irqres = NULL;
+static int g_wifi_irq_rc = 0;
+#define IRQ_RES_NAME "ssv_wlan_irq"
+#define WIFI_HOST_WAKE 0xFFFF
+static int ssv_wifi_power(int on)
+{
+    printk("ssv pwr on=%d\n", on);
+    if (on) {
+    } else {
+    }
+    return 0;
+}
+static int ssv_wifi_reset(int on)
+{
+    return 0;
+}
+int ssv_wifi_set_carddetect(int val)
+{
+    val = val;
+    return 0;
+}
+static struct wifi_platform_data ssv_wifi_control = {
+    .set_power = ssv_wifi_power,
+    .set_reset = ssv_wifi_reset,
+    .set_carddetect = ssv_wifi_set_carddetect,
+};
+static struct resource resources[] = { {
+        .start = WIFI_HOST_WAKE,
+        .flags = IORESOURCE_IRQ,
+        .name = IRQ_RES_NAME,
+    },
+};
+void ssv_wifi_device_release(struct device *dev)
+{
+    printk(KERN_INFO "ssv_wifi_device_release\n");
+}
+static struct platform_device ssv_wifi_device = {
+    .name = "ssv_wlan",
+    .id = 1,
+    .num_resources = ARRAY_SIZE(resources),
+    .resource = resources,
+    .dev = {
+        .platform_data = &ssv_wifi_control,
+        .release = ssv_wifi_device_release,
+    },
+};
+int wifi_set_power(int on, unsigned long msec)
+{
+    if (wifi_control_data && wifi_control_data->set_power) {
+        wifi_control_data->set_power(on);
+    }
+    if (msec)
+        msleep(msec);
+    return 0;
+}
+int wifi_set_reset(int on, unsigned long msec)
+{
+    if (wifi_control_data && wifi_control_data->set_reset) {
+        wifi_control_data->set_reset(on);
+    }
+    if (msec)
+        msleep(msec);
+    return 0;
+}
+static int wifi_set_carddetect(int on)
+{
+    if (wifi_control_data && wifi_control_data->set_carddetect) {
+        wifi_control_data->set_carddetect(on);
+    }
+    return 0;
+}
+static irqreturn_t wifi_wakeup_irq_handler(int irq, void *dev)
+{
+    printk("sdhci_wakeup_irq_handler\n");
+    disable_irq_nosync(irq);
+    return IRQ_HANDLED;
+}
+void setup_wifi_wakeup_BB(struct platform_device *pdev, bool bEnable)
+{
+    int rc = 0, ret = 0;
+    if (bEnable) {
+        wifi_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
+                      IRQ_RES_NAME);
+        rc = (int)wifi_irqres->start;
+        g_wifi_irq_rc = rc;
+        ret = request_threaded_irq(
+                  rc, NULL, (void *)wifi_wakeup_irq_handler,
+#if LINUX_VERSION_CODE > KERNEL_VERSION(3, 0, 0)
+                  IRQ_TYPE_LEVEL_HIGH | IRQF_ONESHOT | IRQF_FORCE_RESUME,
+#else
+                  IRQ_TYPE_LEVEL_HIGH | IRQF_ONESHOT,
+#endif
+                  "wlan_wakeup_irq", NULL);
+        enable_irq_wake(g_wifi_irq_rc);
+    } else {
+        if (g_wifi_irq_rc) {
+            free_irq(g_wifi_irq_rc, NULL);
+            g_wifi_irq_rc = 0;
+        }
+    }
+}
+static int wifi_probe(struct platform_device *pdev)
+{
+    struct wifi_platform_data *wifi_ctrl =
+        (struct wifi_platform_data *)(pdev->dev.platform_data);
+    printk(KERN_ALERT "wifi_probe\n");
+    wifi_control_data = wifi_ctrl;
+    wifi_set_power(0, 40);
+    wifi_set_power(1, 10);
+    wifi_set_carddetect(1);
+    up(&wifi_control_sem);
+    return 0;
+}
+static int wifi_remove(struct platform_device *pdev)
+{
+    struct wifi_platform_data *wifi_ctrl =
+        (struct wifi_platform_data *)(pdev->dev.platform_data);
+    wifi_control_data = wifi_ctrl;
+    wifi_set_power(0, 0);
+    wifi_set_carddetect(0);
+    setup_wifi_wakeup_BB(pdev, false);
+    return 0;
+}
+static int wifi_suspend(struct platform_device *pdev, pm_message_t state)
+{
+    setup_wifi_wakeup_BB(pdev, true);
+    return 0;
+}
+static int wifi_resume(struct platform_device *pdev)
+{
+    setup_wifi_wakeup_BB(pdev, false);
+    return 0;
+}
+static struct platform_driver wifi_driver = { .probe = wifi_probe,
+           .remove = wifi_remove,
+           .suspend = wifi_suspend,
+           .resume = wifi_resume,
+           .driver = { .name =
+                           "ssv_wlan",
+                     }
+};
+extern int tu_ssvdevice_init(void);
+extern void tu_ssvdevice_exit(void);
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+extern int aes_init(void);
+extern void aes_fini(void);
+extern int sha1_mod_init(void);
+extern void sha1_mod_fini(void);
+#endif
+int initWlan(void)
+{
+    int ret = 0;
+    sema_init(&wifi_control_sem, 0);
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+    sha1_mod_init();
+    aes_init();
+#endif
+    platform_device_register(&ssv_wifi_device);
+    platform_driver_register(&wifi_driver);
+    (void)platform_wifi_power_on();
+    g_wifidev_registered = 1;
+    if (down_timeout(&wifi_control_sem, msecs_to_jiffies(1000)) != 0) {
+        ret = -EINVAL;
+        printk(KERN_ALERT "%s: platform_driver_register timeout\n",
+               __FUNCTION__);
+    }
+    ret = tu_ssvdevice_init();
+    return ret;
+}
+void exitWlan(void)
+{
+    if (g_wifidev_registered) {
+        tu_ssvdevice_exit();
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+        aes_fini();
+        sha1_mod_fini();
+#endif
+        (void)platform_wifi_power_off();
+        platform_driver_unregister(&wifi_driver);
+        platform_device_unregister(&ssv_wifi_device);
+        g_wifidev_registered = 0;
+    }
+    return;
+}
+static int tu_generic_wifi_init_module(void)
+{
+    return initWlan();
+}
+static void tu_generic_wifi_exit_module(void)
+{
+    exitWlan();
+}
+EXPORT_SYMBOL(tu_generic_wifi_init_module);
+EXPORT_SYMBOL(tu_generic_wifi_exit_module);
+module_init(tu_generic_wifi_init_module);
+module_exit(tu_generic_wifi_exit_module);
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/drivers/net/wireless/ssv6x5x/platforms/atm7039-action-wifi.cfg b/drivers/net/wireless/ssv6x5x/platforms/atm7039-action-wifi.cfg
new file mode 100755
index 000000000..478f18aa0
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/atm7039-action-wifi.cfg
@@ -0,0 +1,83 @@
+############################################################
+# ATM7039
+# WIFI-CONFIGURATION
+##################################################
+
+##################################################
+# Firmware setting
+# Priority.1 insmod parameter "cfgfirmwarepath"
+# Priority.2 firmware_path
+# Priority.3 default firmware
+##################################################
+firmware_path = /etc/firmware/
+
+############################################################
+# MAC address
+#
+# Priority 1. From wifi.cfg [ hw_mac & hw_mac_2 ]
+#
+# Priority 2. From e-fuse[ON/OFF switch by wifi.cfg]
+#
+# Priority 3. From insert module parameter
+#
+# Priority 4. From external file path
+#   path only support some special charater "_" ":" "/" "." "-"
+#
+# Priority 5. Default[Software mode]
+#
+#   0. => 00:33:33:33:33:33
+#   1. => Always random
+#   2. => First random and write to file[Default path mac_output_path]
+#
+############################################################
+ignore_efuse_mac = 0
+#mac_address_path = /xxxx/xxxx
+mac_address_mode = 2
+mac_output_path = /data/wifimac
+
+##################################################
+# Hardware setting
+#
+#volt regulator(DCDC-0 LDO-1)
+#
+##################################################
+volt_regulator = 1
+
+##################################################
+# Default channel after wifi on
+# value range: [1 ~ 14]
+##################################################
+#def_chan = 6
+##################################################
+# Hardware Capability Settings:
+##################################################
+hw_cap_ampdu_rx = on
+hw_cap_ampdu_tx = on
+hw_cap_tdls = off
+
+use_wpa2_only = 1
+##################################################
+# TX power level setting [0-14]
+# The larger the number the smaller the TX power
+# 0 - The maximum power
+# 1 level = -0.5db
+#
+# 6051Z .. 4 or 4
+# 6051Q .. 2 or 5
+# 6051P .. 0 or 0
+#
+##################################################
+#wifi_tx_gain_level_b = 2
+#wifi_tx_gain_level_gn = 5
+
+##################################################
+# Import extenal configuration(UP to 64 groups)
+# example:
+#    register = CE010010:91919191
+#    register = 00CC0010:00091919
+##################################################
+
+##################################################
+# The AP RSSI signal is less than -88dbm complement signal to -88dbm
+##################################################
+#beacon_rssi_minimal = 88
diff --git a/drivers/net/wireless/ssv6x5x/platforms/atm7039-action.cfg b/drivers/net/wireless/ssv6x5x/platforms/atm7039-action.cfg
new file mode 100755
index 000000000..fc68872dd
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/atm7039-action.cfg
@@ -0,0 +1,17 @@
+############################################################
+# ATM7039
+############################################################
+ccflags-y += -DCONFIG_SSV_SUPPORT_ANDROID
+#ccflags-y += -DCONFIG_SSV_SUPPORT_AES_ASM
+ccflags-y += -DCONFIG_FW_ALIGNMENT_CHECK
+ccflags-y += -DCONFIG_PLATFORM_SDIO_OUTPUT_TIMING=3
+#ccflags-y += -DMULTI_THREAD_ENCRYPT
+
+
+############################################################
+# Compiler path
+############################################################
+#SSV_CROSS = $(R_CROSS_COMPILE)
+#SSV_KERNEL_PATH = $(KERNEL_BUILD_PATH)
+#SSV_ARCH = $(R_ARCH)
+#KMODDESTDIR = $(MODDESTDIR)
diff --git a/drivers/net/wireless/ssv6x5x/platforms/cli b/drivers/net/wireless/ssv6x5x/platforms/cli
new file mode 100755
index 000000000..bc9b65bb7
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/cli
@@ -0,0 +1,6 @@
+
+SSV_DFS_FILE=/sys/kernel/debug/ssv/ssv_cmd
+if [ -f $SSV_DFS_FILE ]; then
+    echo "$*" > $SSV_DFS_FILE
+    cat $SSV_DFS_FILE
+fi
diff --git a/drivers/net/wireless/ssv6x5x/platforms/h3-generic-wlan.c b/drivers/net/wireless/ssv6x5x/platforms/h3-generic-wlan.c
new file mode 100644
index 000000000..f5b15bfa3
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/h3-generic-wlan.c
@@ -0,0 +1,253 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/irq.h>
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/vmalloc.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/pm_runtime.h>
+#include <linux/mmc/host.h>
+#include <linux/delay.h>
+#include <linux/semaphore.h>
+#include <linux/regulator/consumer.h>
+#include <mach/hardware.h>
+#include <asm/io.h>
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
+#include <linux/printk.h>
+#include <linux/err.h>
+#else
+#include <config/printk.h>
+#endif
+#if LINUX_VERSION_CODE > KERNEL_VERSION(3,2,0)
+#include <linux/wlan_plat.h>
+#else
+struct wifi_platform_data {
+    int (*set_power)(int val);
+    int (*set_reset)(int val);
+    int (*set_carddetect)(int val);
+    void *(*mem_prealloc)(int section, unsigned long size);
+    int (*get_mac_addr)(unsigned char *buf);
+    void *(*get_country_code)(char *ccode);
+};
+#endif
+#define GPIO_REG_WRITEL(val,reg) do{__raw_writel(val, CTL_PIN_BASE + (reg));}while(0)
+static int g_wifidev_registered = 0;
+static struct semaphore wifi_control_sem;
+static struct wifi_platform_data *wifi_control_data = NULL;
+static struct resource *wifi_irqres = NULL;
+static int g_wifi_irq_rc=0;
+#define SDIO_ID 1
+#define IRQ_RES_NAME "ssv_wlan_irq"
+#define WIFI_HOST_WAKE 0xFFFF
+extern void sunxi_mci_rescan_card(unsigned id, unsigned insert);
+extern int wifi_pm_gpio_ctrl(char* name, int level);
+static int ssv_wifi_power(int on)
+{
+    printk("ssv pwr on=%d\n",on);
+    if(on) {
+        wifi_pm_gpio_ctrl("wl_reg_on", 0);
+        mdelay(50);
+        wifi_pm_gpio_ctrl("wl_reg_on", 1);
+    } else {
+        wifi_pm_gpio_ctrl("wl_reg_on", 0);
+    }
+    return 0;
+}
+static int ssv_wifi_reset(int on)
+{
+    return 0;
+}
+int ssv_wifi_set_carddetect(int val)
+{
+    sunxi_mci_rescan_card(SDIO_ID, val);
+    return 0;
+}
+static struct wifi_platform_data ssv_wifi_control = {
+    .set_power = ssv_wifi_power,
+    .set_reset = ssv_wifi_reset,
+    .set_carddetect = ssv_wifi_set_carddetect,
+};
+static struct resource resources[] = {
+    {
+        .start = WIFI_HOST_WAKE,
+        .flags = IORESOURCE_IRQ,
+        .name = IRQ_RES_NAME,
+    },
+};
+void ssv_wifi_device_release(struct device *dev)
+{
+    printk(KERN_INFO "ssv_wifi_device_release\n");
+}
+static struct platform_device ssv_wifi_device = {
+    .name = "ssv_wlan",
+    .id = 1,
+    .num_resources = ARRAY_SIZE(resources),
+    .resource = resources,
+    .dev = {
+        .platform_data = &ssv_wifi_control,
+        .release = ssv_wifi_device_release,
+    },
+};
+int wifi_set_power(int on, unsigned long msec)
+{
+    if (wifi_control_data && wifi_control_data->set_power) {
+        wifi_control_data->set_power(on);
+    }
+    if (msec)
+        msleep(msec);
+    return 0;
+}
+int wifi_set_reset(int on, unsigned long msec)
+{
+    if (wifi_control_data && wifi_control_data->set_reset) {
+        wifi_control_data->set_reset(on);
+    }
+    if (msec)
+        msleep(msec);
+    return 0;
+}
+static int wifi_set_carddetect(int on)
+{
+    if (wifi_control_data && wifi_control_data->set_carddetect) {
+        wifi_control_data->set_carddetect(on);
+    }
+    return 0;
+}
+static irqreturn_t wifi_wakeup_irq_handler(int irq, void *dev)
+{
+    printk("sdhci_wakeup_irq_handler\n");
+    disable_irq_nosync(irq);
+    return IRQ_HANDLED;
+}
+void setup_wifi_wakeup_BB(struct platform_device *pdev, bool bEnable)
+{
+    int rc=0,ret=0;
+    if (bEnable) {
+        wifi_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ, IRQ_RES_NAME);
+        rc = (int)wifi_irqres->start;
+        g_wifi_irq_rc = rc;
+        ret = request_threaded_irq(rc,
+                                   NULL,
+                                   (void *)wifi_wakeup_irq_handler,
+#if LINUX_VERSION_CODE > KERNEL_VERSION(3,0,0)
+                                   IRQ_TYPE_LEVEL_HIGH | IRQF_ONESHOT |IRQF_FORCE_RESUME,
+#else
+                                   IRQ_TYPE_LEVEL_HIGH | IRQF_ONESHOT,
+#endif
+                                   "wlan_wakeup_irq", NULL);
+        enable_irq_wake(g_wifi_irq_rc);
+    } else {
+        if(g_wifi_irq_rc) {
+            free_irq(g_wifi_irq_rc,NULL);
+            g_wifi_irq_rc = 0;
+        }
+    }
+}
+static int wifi_probe(struct platform_device *pdev)
+{
+    struct wifi_platform_data *wifi_ctrl =
+        (struct wifi_platform_data *)(pdev->dev.platform_data);
+    printk(KERN_ALERT "wifi_probe\n");
+    wifi_control_data = wifi_ctrl;
+    wifi_set_power(0,40);
+    wifi_set_power(1,50);
+    wifi_set_carddetect(1);
+    up(&wifi_control_sem);
+    return 0;
+}
+static int wifi_remove(struct platform_device *pdev)
+{
+    struct wifi_platform_data *wifi_ctrl =
+        (struct wifi_platform_data *)(pdev->dev.platform_data);
+    wifi_control_data = wifi_ctrl;
+    wifi_set_power(0, 0);
+    wifi_set_power(0, 0);
+    wifi_set_power(0, 0);
+    wifi_set_power(0, 0);
+    wifi_set_carddetect(0);
+    return 0;
+}
+static int wifi_suspend(struct platform_device *pdev, pm_message_t state)
+{
+    return 0;
+}
+static int wifi_resume(struct platform_device *pdev)
+{
+    return 0;
+}
+static struct platform_driver wifi_driver = {
+    .probe = wifi_probe,
+    .remove = wifi_remove,
+    .suspend = wifi_suspend,
+    .resume = wifi_resume,
+    .driver = {
+        .name = "ssv_wlan",
+    }
+};
+extern int tu_ssvdevice_init(void);
+extern void tu_ssvdevice_exit(void);
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+extern int aes_init(void);
+extern void aes_fini(void);
+extern int sha1_mod_init(void);
+extern void sha1_mod_fini(void);
+#endif
+int initWlan(void)
+{
+    int ret=0;
+    sema_init(&wifi_control_sem, 0);
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+    sha1_mod_init();
+    aes_init();
+#endif
+    platform_device_register(&ssv_wifi_device);
+    platform_driver_register(&wifi_driver);
+    g_wifidev_registered = 1;
+    if (down_timeout(&wifi_control_sem, msecs_to_jiffies(1000)) != 0) {
+        ret = -EINVAL;
+        printk(KERN_ALERT "%s: platform_driver_register timeout\n", __FUNCTION__);
+    }
+    ret = tu_ssvdevice_init();
+    return ret;
+}
+void exitWlan(void)
+{
+    if (g_wifidev_registered) {
+        tu_ssvdevice_exit();
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+        aes_fini();
+        sha1_mod_fini();
+#endif
+        platform_driver_unregister(&wifi_driver);
+        platform_device_unregister(&ssv_wifi_device);
+        g_wifidev_registered = 0;
+    }
+    return;
+}
+static int tu_generic_wifi_init_module(void)
+{
+    return initWlan();
+}
+static void tu_generic_wifi_exit_module(void)
+{
+    exitWlan();
+}
+EXPORT_SYMBOL(tu_generic_wifi_init_module);
+EXPORT_SYMBOL(tu_generic_wifi_exit_module);
+module_init(tu_generic_wifi_init_module);
+module_exit(tu_generic_wifi_exit_module);
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/drivers/net/wireless/ssv6x5x/platforms/h3-wifi.cfg b/drivers/net/wireless/ssv6x5x/platforms/h3-wifi.cfg
new file mode 100755
index 000000000..6758bd142
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/h3-wifi.cfg
@@ -0,0 +1,83 @@
+##################################################
+# H3
+# WIFI-CONFIGURATION
+##################################################
+
+##################################################
+# Firmware setting
+# Priority.1 insmod parameter "cfgfirmwarepath"
+# Priority.2 firmware_path
+# Priority.3 default firmware
+##################################################
+firmware_path = /etc/firmware/
+
+############################################################
+# MAC address
+#
+# Priority 1. From wifi.cfg [ hw_mac & hw_mac_2 ]
+#
+# Priority 2. From e-fuse[ON/OFF switch by wifi.cfg]
+#
+# Priority 3. From insert module parameter
+#
+# Priority 4. From external file path
+#   path only support some special charater "_" ":" "/" "." "-"
+#
+# Priority 5. Default[Software mode]
+#
+#   0. => 00:33:33:33:33:33
+#   1. => Always random
+#   2. => First random and write to file[Default path mac_output_path]
+#
+############################################################
+ignore_efuse_mac = 0
+#mac_address_path = /xxxx/xxxx
+mac_address_mode = 2
+mac_output_path = /data/wifimac
+
+##################################################
+# Hardware setting
+#
+#volt regulator(DCDC-0 LDO-1)
+#
+##################################################
+volt_regulator = 1
+
+##################################################
+# Default channel after wifi on
+# value range: [1 ~ 14]
+##################################################
+#def_chan = 6
+##################################################
+# Hardware Capability Settings:
+##################################################
+hw_cap_ampdu_rx = on
+hw_cap_ampdu_tx = on
+hw_cap_tdls = off
+
+use_wpa2_only = 1
+##################################################
+# TX power level setting [0-14]
+# The larger the number the smaller the TX power
+# 0 - The maximum power
+# 1 level = -0.5db
+#
+# 6051Z .. 4 or 4
+# 6051Q .. 2 or 5
+# 6051P .. 0 or 0
+#
+##################################################
+#wifi_tx_gain_level_b = 4
+#wifi_tx_gain_level_gn = 4
+
+##################################################
+# Import extenal configuration(UP to 64 groups)
+# example:
+#    register = CE010010:91919191
+#    register = 00CC0010:00091919
+##################################################
+
+##################################################
+# The AP RSSI signal is less than -88dbm complement signal to -88dbm
+##################################################
+#beacon_rssi_minimal = 88
diff --git a/drivers/net/wireless/ssv6x5x/platforms/h3.cfg b/drivers/net/wireless/ssv6x5x/platforms/h3.cfg
new file mode 100755
index 000000000..7947b303c
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/h3.cfg
@@ -0,0 +1,17 @@
+############################################################
+# H3
+############################################################
+ccflags-y += -DCONFIG_SSV_SUPPORT_ANDROID
+#ccflags-y += -DCONFIG_SSV_SUPPORT_AES_ASM
+ccflags-y += -DCONFIG_FW_ALIGNMENT_CHECK
+ccflags-y += -DCONFIG_PLATFORM_SDIO_OUTPUT_TIMING=3
+#ccflags-y += -DMULTI_THREAD_ENCRYPT
+#ccflags-y += -DKTHREAD_BIND
+
+############################################################
+# Compiler path
+############################################################
+SSV_CROSS = $(ANDROID_BUILD_TOP)/../lichee/out/sun8iw7p1/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi-
+SSV_KERNEL_PATH = $(ANDROID_BUILD_TOP)/../lichee/linux-3.4
+SSV_ARCH = arm
+KMODDESTDIR = $(MODDESTDIR)
diff --git a/drivers/net/wireless/ssv6x5x/platforms/h8-generic-wlan.c b/drivers/net/wireless/ssv6x5x/platforms/h8-generic-wlan.c
new file mode 100644
index 000000000..f5b15bfa3
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/h8-generic-wlan.c
@@ -0,0 +1,253 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/irq.h>
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/vmalloc.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/pm_runtime.h>
+#include <linux/mmc/host.h>
+#include <linux/delay.h>
+#include <linux/semaphore.h>
+#include <linux/regulator/consumer.h>
+#include <mach/hardware.h>
+#include <asm/io.h>
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
+#include <linux/printk.h>
+#include <linux/err.h>
+#else
+#include <config/printk.h>
+#endif
+#if LINUX_VERSION_CODE > KERNEL_VERSION(3,2,0)
+#include <linux/wlan_plat.h>
+#else
+struct wifi_platform_data {
+    int (*set_power)(int val);
+    int (*set_reset)(int val);
+    int (*set_carddetect)(int val);
+    void *(*mem_prealloc)(int section, unsigned long size);
+    int (*get_mac_addr)(unsigned char *buf);
+    void *(*get_country_code)(char *ccode);
+};
+#endif
+#define GPIO_REG_WRITEL(val,reg) do{__raw_writel(val, CTL_PIN_BASE + (reg));}while(0)
+static int g_wifidev_registered = 0;
+static struct semaphore wifi_control_sem;
+static struct wifi_platform_data *wifi_control_data = NULL;
+static struct resource *wifi_irqres = NULL;
+static int g_wifi_irq_rc=0;
+#define SDIO_ID 1
+#define IRQ_RES_NAME "ssv_wlan_irq"
+#define WIFI_HOST_WAKE 0xFFFF
+extern void sunxi_mci_rescan_card(unsigned id, unsigned insert);
+extern int wifi_pm_gpio_ctrl(char* name, int level);
+static int ssv_wifi_power(int on)
+{
+    printk("ssv pwr on=%d\n",on);
+    if(on) {
+        wifi_pm_gpio_ctrl("wl_reg_on", 0);
+        mdelay(50);
+        wifi_pm_gpio_ctrl("wl_reg_on", 1);
+    } else {
+        wifi_pm_gpio_ctrl("wl_reg_on", 0);
+    }
+    return 0;
+}
+static int ssv_wifi_reset(int on)
+{
+    return 0;
+}
+int ssv_wifi_set_carddetect(int val)
+{
+    sunxi_mci_rescan_card(SDIO_ID, val);
+    return 0;
+}
+static struct wifi_platform_data ssv_wifi_control = {
+    .set_power = ssv_wifi_power,
+    .set_reset = ssv_wifi_reset,
+    .set_carddetect = ssv_wifi_set_carddetect,
+};
+static struct resource resources[] = {
+    {
+        .start = WIFI_HOST_WAKE,
+        .flags = IORESOURCE_IRQ,
+        .name = IRQ_RES_NAME,
+    },
+};
+void ssv_wifi_device_release(struct device *dev)
+{
+    printk(KERN_INFO "ssv_wifi_device_release\n");
+}
+static struct platform_device ssv_wifi_device = {
+    .name = "ssv_wlan",
+    .id = 1,
+    .num_resources = ARRAY_SIZE(resources),
+    .resource = resources,
+    .dev = {
+        .platform_data = &ssv_wifi_control,
+        .release = ssv_wifi_device_release,
+    },
+};
+int wifi_set_power(int on, unsigned long msec)
+{
+    if (wifi_control_data && wifi_control_data->set_power) {
+        wifi_control_data->set_power(on);
+    }
+    if (msec)
+        msleep(msec);
+    return 0;
+}
+int wifi_set_reset(int on, unsigned long msec)
+{
+    if (wifi_control_data && wifi_control_data->set_reset) {
+        wifi_control_data->set_reset(on);
+    }
+    if (msec)
+        msleep(msec);
+    return 0;
+}
+static int wifi_set_carddetect(int on)
+{
+    if (wifi_control_data && wifi_control_data->set_carddetect) {
+        wifi_control_data->set_carddetect(on);
+    }
+    return 0;
+}
+static irqreturn_t wifi_wakeup_irq_handler(int irq, void *dev)
+{
+    printk("sdhci_wakeup_irq_handler\n");
+    disable_irq_nosync(irq);
+    return IRQ_HANDLED;
+}
+void setup_wifi_wakeup_BB(struct platform_device *pdev, bool bEnable)
+{
+    int rc=0,ret=0;
+    if (bEnable) {
+        wifi_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ, IRQ_RES_NAME);
+        rc = (int)wifi_irqres->start;
+        g_wifi_irq_rc = rc;
+        ret = request_threaded_irq(rc,
+                                   NULL,
+                                   (void *)wifi_wakeup_irq_handler,
+#if LINUX_VERSION_CODE > KERNEL_VERSION(3,0,0)
+                                   IRQ_TYPE_LEVEL_HIGH | IRQF_ONESHOT |IRQF_FORCE_RESUME,
+#else
+                                   IRQ_TYPE_LEVEL_HIGH | IRQF_ONESHOT,
+#endif
+                                   "wlan_wakeup_irq", NULL);
+        enable_irq_wake(g_wifi_irq_rc);
+    } else {
+        if(g_wifi_irq_rc) {
+            free_irq(g_wifi_irq_rc,NULL);
+            g_wifi_irq_rc = 0;
+        }
+    }
+}
+static int wifi_probe(struct platform_device *pdev)
+{
+    struct wifi_platform_data *wifi_ctrl =
+        (struct wifi_platform_data *)(pdev->dev.platform_data);
+    printk(KERN_ALERT "wifi_probe\n");
+    wifi_control_data = wifi_ctrl;
+    wifi_set_power(0,40);
+    wifi_set_power(1,50);
+    wifi_set_carddetect(1);
+    up(&wifi_control_sem);
+    return 0;
+}
+static int wifi_remove(struct platform_device *pdev)
+{
+    struct wifi_platform_data *wifi_ctrl =
+        (struct wifi_platform_data *)(pdev->dev.platform_data);
+    wifi_control_data = wifi_ctrl;
+    wifi_set_power(0, 0);
+    wifi_set_power(0, 0);
+    wifi_set_power(0, 0);
+    wifi_set_power(0, 0);
+    wifi_set_carddetect(0);
+    return 0;
+}
+static int wifi_suspend(struct platform_device *pdev, pm_message_t state)
+{
+    return 0;
+}
+static int wifi_resume(struct platform_device *pdev)
+{
+    return 0;
+}
+static struct platform_driver wifi_driver = {
+    .probe = wifi_probe,
+    .remove = wifi_remove,
+    .suspend = wifi_suspend,
+    .resume = wifi_resume,
+    .driver = {
+        .name = "ssv_wlan",
+    }
+};
+extern int tu_ssvdevice_init(void);
+extern void tu_ssvdevice_exit(void);
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+extern int aes_init(void);
+extern void aes_fini(void);
+extern int sha1_mod_init(void);
+extern void sha1_mod_fini(void);
+#endif
+int initWlan(void)
+{
+    int ret=0;
+    sema_init(&wifi_control_sem, 0);
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+    sha1_mod_init();
+    aes_init();
+#endif
+    platform_device_register(&ssv_wifi_device);
+    platform_driver_register(&wifi_driver);
+    g_wifidev_registered = 1;
+    if (down_timeout(&wifi_control_sem, msecs_to_jiffies(1000)) != 0) {
+        ret = -EINVAL;
+        printk(KERN_ALERT "%s: platform_driver_register timeout\n", __FUNCTION__);
+    }
+    ret = tu_ssvdevice_init();
+    return ret;
+}
+void exitWlan(void)
+{
+    if (g_wifidev_registered) {
+        tu_ssvdevice_exit();
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+        aes_fini();
+        sha1_mod_fini();
+#endif
+        platform_driver_unregister(&wifi_driver);
+        platform_device_unregister(&ssv_wifi_device);
+        g_wifidev_registered = 0;
+    }
+    return;
+}
+static int tu_generic_wifi_init_module(void)
+{
+    return initWlan();
+}
+static void tu_generic_wifi_exit_module(void)
+{
+    exitWlan();
+}
+EXPORT_SYMBOL(tu_generic_wifi_init_module);
+EXPORT_SYMBOL(tu_generic_wifi_exit_module);
+module_init(tu_generic_wifi_init_module);
+module_exit(tu_generic_wifi_exit_module);
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/drivers/net/wireless/ssv6x5x/platforms/h8-wifi.cfg b/drivers/net/wireless/ssv6x5x/platforms/h8-wifi.cfg
new file mode 100755
index 000000000..9491016af
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/h8-wifi.cfg
@@ -0,0 +1,83 @@
+############################################################
+# H8
+# WIFI-CONFIGURATION
+##################################################
+
+##################################################
+# Firmware setting
+# Priority.1 insmod parameter "cfgfirmwarepath"
+# Priority.2 firmware_path
+# Priority.3 default firmware
+##################################################
+firmware_path = /etc/firmware/
+
+############################################################
+# MAC address
+#
+# Priority 1. From wifi.cfg [ hw_mac & hw_mac_2 ]
+#
+# Priority 2. From e-fuse[ON/OFF switch by wifi.cfg]
+#
+# Priority 3. From insert module parameter
+#
+# Priority 4. From external file path
+#   path only support some special charater "_" ":" "/" "." "-"
+#
+# Priority 5. Default[Software mode]
+#
+#   0. => 00:33:33:33:33:33
+#   1. => Always random
+#   2. => First random and write to file[Default path mac_output_path]
+#
+############################################################
+ignore_efuse_mac = 0
+#mac_address_path = /xxxx/xxxx
+mac_address_mode = 2
+mac_output_path = /data/wifimac
+
+##################################################
+# Hardware setting
+#
+#volt regulator(DCDC-0 LDO-1)
+#
+##################################################
+volt_regulator = 1
+
+##################################################
+# Default channel after wifi on
+# value range: [1 ~ 14]
+##################################################
+#def_chan = 6
+##################################################
+# Hardware Capability Settings:
+##################################################
+hw_cap_ampdu_rx = on
+hw_cap_ampdu_tx = on
+hw_cap_tdls = off
+
+use_wpa2_only = 1
+##################################################
+# TX power level setting [0-14]
+# The larger the number the smaller the TX power
+# 0 - The maximum power
+# 1 level = -0.5db
+#
+# 6051Z .. 4 or 4
+# 6051Q .. 2 or 5
+# 6051P .. 0 or 0
+#
+##################################################
+#wifi_tx_gain_level_b = 4
+#wifi_tx_gain_level_gn = 4
+
+##################################################
+# Import extenal configuration(UP to 64 groups)
+# example:
+#    register = CE010010:91919191
+#    register = 00CC0010:00091919
+##################################################
+
+##################################################
+# The AP RSSI signal is less than -88dbm complement signal to -88dbm
+##################################################
+#beacon_rssi_minimal = 88
diff --git a/drivers/net/wireless/ssv6x5x/platforms/h8.cfg b/drivers/net/wireless/ssv6x5x/platforms/h8.cfg
new file mode 100755
index 000000000..a2331cd61
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/h8.cfg
@@ -0,0 +1,17 @@
+############################################################
+# H8
+############################################################
+ccflags-y += -DCONFIG_SSV_SUPPORT_ANDROID
+#ccflags-y += -DCONFIG_SSV_SUPPORT_AES_ASM
+ccflags-y += -DCONFIG_FW_ALIGNMENT_CHECK
+ccflags-y += -DCONFIG_PLATFORM_SDIO_OUTPUT_TIMING=3
+#ccflags-y += -DMULTI_THREAD_ENCRYPT
+#ccflags-y += -DKTHREAD_BIND
+
+############################################################
+# Compiler path
+############################################################
+SSV_CROSS = $(ANDROID_BUILD_TOP)/../lichee/out/sun8iw7p1/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi-
+SSV_KERNEL_PATH = $(ANDROID_BUILD_TOP)/../lichee/linux-3.4
+SSV_ARCH = arm
+KMODDESTDIR = $(MODDESTDIR)
diff --git a/drivers/net/wireless/ssv6x5x/platforms/platform-config.mak b/drivers/net/wireless/ssv6x5x/platforms/platform-config.mak
new file mode 100755
index 000000000..fccd042e2
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/platform-config.mak
@@ -0,0 +1,7 @@
+
+include $(KBUILD_TOP)/config_common.mak
+
+# SDIO delay chain
+#ccflags-y += -D CONFIG_SSV_SDIO_INPUT_DELAY=0x00000000
+#ccflags-y += -D CONFIG_SSV_SDIO_OUTPUT_DELAY=0x00000000
+
diff --git a/drivers/net/wireless/ssv6x5x/platforms/rk3036-generic-wlan.c b/drivers/net/wireless/ssv6x5x/platforms/rk3036-generic-wlan.c
new file mode 100644
index 000000000..e0b23e425
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/rk3036-generic-wlan.c
@@ -0,0 +1,127 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/irq.h>
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/vmalloc.h>
+#include <linux/gpio.h>
+#include <linux/mmc/host.h>
+#include <linux/delay.h>
+#include <linux/regulator/consumer.h>
+#include <asm/io.h>
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
+#include <linux/printk.h>
+#include <linux/err.h>
+#else
+#include <config/printk.h>
+#endif
+extern int rockchip_wifi_power(int on);
+extern int rockchip_wifi_set_carddetect(int val);
+#ifdef ROCKCHIP_WIFI_AUTO_SUPPORT
+extern char wifi_chip_type_string[];
+#endif
+#define GPIO_REG_WRITEL(val,reg) \
+ do { \
+  __raw_writel(val, CTL_PIN_BASE + (reg)); \
+ } while (0)
+static int g_wifidev_registered = 0;
+extern int tu_ssvdevice_init(void);
+extern void tu_ssvdevice_exit(void);
+#if 0
+extern int ssv6xxx_get_dev_status(void);
+#endif
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+extern int aes_init(void);
+extern void aes_fini(void);
+extern int sha1_mod_init(void);
+extern void sha1_mod_fini(void);
+#endif
+void ssv_wifi_power(void)
+{
+    printk("[P] %s:\n", __FUNCTION__);
+    rockchip_wifi_set_carddetect(0);
+    msleep(150);
+    rockchip_wifi_power(0);
+    msleep(150);
+    rockchip_wifi_power(1);
+    msleep(150);
+    rockchip_wifi_set_carddetect(1);
+    msleep(150);
+}
+int initWlan(void)
+{
+    int ret = 0;
+    int time = 5;
+    ssv_wifi_power();
+    msleep(120);
+    g_wifidev_registered = 1;
+    ret = tu_ssvdevice_init();
+    while(time-- > 0) {
+        msleep(500);
+#if 0
+        if(ssv6xxx_get_dev_status() == 1)
+            break;
+#else
+        break;
+#endif
+        printk("%s : Retry to carddetect\n",__func__);
+        ssv_wifi_power();
+    }
+#ifdef ROCKCHIP_WIFI_AUTO_SUPPORT
+    if (!ret) {
+        strcpy(wifi_chip_type_string, "ssv6xxx");
+        printk(KERN_INFO "wifi_chip_type_string : %s\n",wifi_chip_type_string);
+    }
+#endif
+    return ret;
+}
+void exitWlan(void)
+{
+    if (g_wifidev_registered) {
+        tu_ssvdevice_exit();
+        msleep(50);
+#ifndef ROCKCHIP_WIFI_AUTO_SUPPORT
+        rockchip_wifi_set_carddetect(0);
+#endif
+        rockchip_wifi_power(0);
+        g_wifidev_registered = 0;
+    }
+    return;
+}
+static __init int tu_generic_wifi_init_module(void)
+{
+    printk("%s\n", __func__);
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+    sha1_mod_init();
+    aes_init();
+#endif
+    return initWlan();
+}
+static __exit void tu_generic_wifi_exit_module(void)
+{
+    printk("%s\n", __func__);
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+    aes_fini();
+    sha1_mod_fini();
+#endif
+    msleep(100);
+    exitWlan();
+}
+EXPORT_SYMBOL(tu_generic_wifi_init_module);
+EXPORT_SYMBOL(tu_generic_wifi_exit_module);
+module_init(tu_generic_wifi_init_module);
+module_exit(tu_generic_wifi_exit_module);
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/drivers/net/wireless/ssv6x5x/platforms/rk3036-wifi.cfg b/drivers/net/wireless/ssv6x5x/platforms/rk3036-wifi.cfg
new file mode 100755
index 000000000..c7f446805
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/rk3036-wifi.cfg
@@ -0,0 +1,94 @@
+############################################################
+# ROCKCHIP RK3X28 & RK322X
+# WIFI-CONFIGURATION
+##################################################
+
+hw_mac = 00:a5:b5:30:36:20
+hw_mac_2 = 00:a5:b5:30:36:21
+
+##################################################
+# Firmware setting
+# Priority.1 insmod parameter "cfgfirmwarepath"
+# Priority.2 firmware_path
+# Priority.3 default firmware
+##################################################
+firmware_path = /etc/firmware/
+
+############################################################
+# MAC address
+#
+# Priority 1. From wifi.cfg [ hw_mac & hw_mac_2 ]
+#
+# Priority 2. From e-fuse[ON/OFF switch by wifi.cfg]
+#
+# Priority 3. From insert module parameter
+#
+# Priority 4. From external file path
+#   path only support some special charater "_" ":" "/" "." "-"
+#
+# Priority 5. Default[Software mode]
+#
+#   0. => 00:33:33:33:33:33
+#   1. => Always random
+#   2. => First random and write to file[Default path mac_output_path]
+#
+############################################################
+#ignore_efuse_mac = 1
+#mac_address_path = /xxxx/xxxx
+#mac_address_mode = 2
+#mac_output_path = /data/wifimac
+
+##################################################
+# Hardware setting
+#
+#volt regulator(DCDC-0 LDO-1)
+#
+##################################################
+xtal_clock = 25
+volt_regulator = 1
+
+##################################################
+# Default channel after wifi on
+# value range: [1 ~ 14]
+##################################################
+#def_chan = 6
+##################################################
+# Hardware Capability Settings:
+##################################################
+hw_cap_ampdu_rx = on
+hw_cap_ampdu_tx = on
+hw_cap_tdls = off
+hw_cap_5ghz = off
+
+use_wpa2_only = 1
+##################################################
+# TX power level setting [0-14]
+# The larger the number the smaller the TX power
+# 0 - The maximum power
+# 1 level = -0.5db
+#
+# 6051Z .. 4 or 4
+# 6051Q .. 2 or 5
+# 6051P .. 0 or 0
+#
+##################################################
+#wifi_tx_gain_level_b = 2
+#wifi_tx_gain_level_gn = 5
+
+##################################################
+# Import extenal configuration(UP to 64 groups)
+# example:
+#    register = CE010010:91919191
+#    register = 00CC0010:00091919
+##################################################
+
+##################################################
+# The AP RSSI signal is less than -88dbm complement signal to -88dbm
+##################################################
+#beacon_rssi_minimal = 88
+
+##################################################
+# Direct Ack Threshold Settings:
+##################################################
+directly_ack_low_threshold = 64
+directly_ack_high_threshold = 512
diff --git a/drivers/net/wireless/ssv6x5x/platforms/rk3036.cfg b/drivers/net/wireless/ssv6x5x/platforms/rk3036.cfg
new file mode 100755
index 000000000..141466ce4
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/rk3036.cfg
@@ -0,0 +1,22 @@
+############################################################
+# RK3036
+############################################################
+ccflags-y += -DCONFIG_SSV_SUPPORT_ANDROID
+ccflags-y += -DCONFIG_SSV_SUPPORT_AES_ASM
+ccflags-y += -DCONFIG_FW_ALIGNMENT_CHECK
+ccflags-y += -DCONFIG_PLATFORM_SDIO_OUTPUT_TIMING=3
+ccflags-y += -DCONFIG_PLATFORM_SDIO_BLOCK_SIZE=128
+#ccflags-y += -DMULTI_THREAD_ENCRYPT
+ccflags-y += -DCONFIG_SSV_OPENFILE_LOADFW
+ccflags-y += -DPLATFORM_FORCE_DISABLE_AMPDU_FLOW_CONTROL
+#ccflags-y += -DKTHREAD_BIND
+#ccflags-y += -DCONFIG_SSV_RSSI
+
+############################################################
+# Compiler path
+############################################################
+SSV_CROSS = $(ANDROID_BUILD_TOP)/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi-
+SSV_KERNEL_PATH = $(ANDROID_BUILD_TOP)/kernel
+SSV_ARCH = arm
+KMODDESTDIR = $(MODDESTDIR)
+
diff --git a/drivers/net/wireless/ssv6x5x/platforms/rk3126-generic-wlan.c b/drivers/net/wireless/ssv6x5x/platforms/rk3126-generic-wlan.c
new file mode 100644
index 000000000..174c79aac
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/rk3126-generic-wlan.c
@@ -0,0 +1,266 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/irq.h>
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/vmalloc.h>
+#include <linux/gpio.h>
+#include <linux/mmc/host.h>
+#include <linux/delay.h>
+#include <linux/regulator/consumer.h>
+#include <linux/semaphore.h>
+#include <linux/platform_device.h>
+#ifdef CONFIG_HAS_WAKELOCK
+#include <linux/wakelock.h>
+#endif
+#include <asm/io.h>
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
+#include <linux/printk.h>
+#include <linux/err.h>
+#else
+#include <config/printk.h>
+#endif
+#if LINUX_VERSION_CODE > KERNEL_VERSION(3,2,0)
+#include <linux/wlan_plat.h>
+#else
+struct wifi_platform_data {
+    int (*set_power)(int val);
+    int (*set_reset)(int val);
+    int (*set_carddetect)(int val);
+    void *(*mem_prealloc)(int section, unsigned long size);
+    int (*get_mac_addr)(unsigned char *buf);
+    void *(*get_country_code)(char *ccode);
+};
+#endif
+extern int rockchip_wifi_power(int on);
+extern int rockchip_wifi_set_carddetect(int val);
+extern int ssv6xxx_get_dev_status(void);
+static struct wifi_platform_data *wifi_control_data = NULL;
+#define GPIO_REG_WRITEL(val,reg) do{__raw_writel(val, CTL_PIN_BASE + (reg));}while(0)
+unsigned int oob_irq = 0;
+static int g_wifidev_registered = 0;
+static struct semaphore wifi_control_sem;
+extern int rockchip_wifi_get_oob_irq(void);
+extern int tu_ssvdevice_init(void);
+extern void tu_ssvdevice_exit(void);
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+extern int aes_init(void);
+extern void aes_fini(void);
+extern int sha1_mod_init(void);
+extern void sha1_mod_fini(void);
+#endif
+#ifdef CONFIG_HAS_WAKELOCK
+struct wake_lock icomm_wake_lock;
+#endif
+static int icomm_wifi_power(int on)
+{
+    printk("%s: %d\n", __func__, on);
+    rockchip_wifi_power(on);
+    return 0;
+}
+int icomm_wifi_set_carddetect(int val)
+{
+    rockchip_wifi_set_carddetect(val);
+    return 0;
+}
+static struct wifi_platform_data icomm_wifi_control = {
+    .set_power = icomm_wifi_power,
+    .set_carddetect = icomm_wifi_set_carddetect,
+};
+void icomm_wifi_device_release(struct device *dev)
+{
+    printk("%s\n", __func__);
+}
+static struct platform_device icomm_wifi_device = {
+    .name = "icomm_wlan",
+    .id = 1,
+    .dev = {
+        .platform_data = &icomm_wifi_control,
+        .release = icomm_wifi_device_release,
+    },
+};
+int wifi_set_power(int on, unsigned long msec)
+{
+    if (wifi_control_data && wifi_control_data->set_power) {
+        wifi_control_data->set_power(on);
+    }
+    if (msec)
+        msleep(msec);
+    return 0;
+}
+static int wifi_set_carddetect(int on)
+{
+    if (wifi_control_data && wifi_control_data->set_carddetect) {
+        wifi_control_data->set_carddetect(on);
+    }
+    return 0;
+}
+static irqreturn_t wifi_wakeup_irq_handler(int irq, void *dev)
+{
+    printk("%s\n", __func__);
+    wake_lock_timeout(&icomm_wake_lock, HZ);
+    return IRQ_HANDLED;
+}
+void setup_wifi_wakeup_BB(void)
+{
+    int err;
+    oob_irq = rockchip_wifi_get_oob_irq();
+    if (oob_irq <= 0) {
+        printk("%s: oob_irq NULL\n", __func__);
+        return;
+    }
+    err = request_threaded_irq(oob_irq,
+                               wifi_wakeup_irq_handler,
+                               NULL,
+                               IRQF_TRIGGER_FALLING,
+                               "wlan_wakeup_irq",
+                               NULL);
+    printk("%s: set oob_irq:%d %s\n", __func__, oob_irq, (err < 0) ? "NG": "OK");
+}
+void free_wifi_wakeup_BB(void)
+{
+    if (oob_irq > 0) {
+        free_irq(oob_irq, NULL);
+        oob_irq = 0;
+    }
+}
+static int wifi_probe(struct platform_device *pdev)
+{
+    struct wifi_platform_data *wifi_ctrl =
+        (struct wifi_platform_data *)(pdev->dev.platform_data);
+    printk("%s\n", __func__);
+    wifi_control_data = wifi_ctrl;
+    wifi_set_power(0, 50);
+    wifi_set_power(1, 50);
+    wifi_set_carddetect(1);
+    msleep(120);
+    up(&wifi_control_sem);
+    return 0;
+}
+static int wifi_remove(struct platform_device *pdev)
+{
+    struct wifi_platform_data *wifi_ctrl =
+        (struct wifi_platform_data *)(pdev->dev.platform_data);
+    printk("%s\n", __func__);
+    wifi_control_data = wifi_ctrl;
+    wifi_set_carddetect(0);
+    msleep(120);
+    wifi_set_power(0, 50);
+#ifdef CONFIG_HAS_WAKELOCK
+    wake_lock_destroy(&icomm_wake_lock);
+#endif
+    return 0;
+}
+#ifdef CONFIG_PM
+static int wifi_suspend(struct platform_device *pdev, pm_message_t state)
+{
+    printk("%s\n", __func__);
+    return 0;
+}
+static int wifi_resume(struct platform_device *pdev)
+{
+    printk("%s\n", __func__);
+#if 0
+    if (wifi_control_data && wifi_control_data->set_carddetect) {
+        wifi_control_data->set_carddetect(0);
+    }
+    msleep(50);
+    if (wifi_control_data && wifi_control_data->set_carddetect) {
+        wifi_control_data->set_carddetect(1);
+    }
+#endif
+    return 0;
+}
+#endif
+static struct platform_driver wifi_driver = {
+    .probe = wifi_probe,
+    .remove = wifi_remove,
+#ifdef CONFIG_PM
+    .suspend = wifi_suspend,
+    .resume = wifi_resume,
+#endif
+    .driver = {
+        .name = "icomm_wlan",
+    }
+};
+int initWlan(void)
+{
+    int ret=0;
+#ifdef CONFIG_HAS_WAKELOCK
+    wake_lock_init(&icomm_wake_lock, WAKE_LOCK_SUSPEND, "ssv6051");
+    wake_lock(&icomm_wake_lock);
+#endif
+    sema_init(&wifi_control_sem, 0);
+    platform_device_register(&icomm_wifi_device);
+    platform_driver_register(&wifi_driver);
+    g_wifidev_registered = 1;
+    if (down_timeout(&wifi_control_sem, msecs_to_jiffies(1000)) != 0) {
+        ret = -EINVAL;
+        printk(KERN_ALERT "%s: platform_driver_register timeout\n", __FUNCTION__);
+    }
+    ret = tu_ssvdevice_init();
+#ifdef CONFIG_HAS_WAKELOCK
+    wake_unlock(&icomm_wake_lock);
+#endif
+    return ret;
+}
+void exitWlan(void)
+{
+    if (g_wifidev_registered) {
+        tu_ssvdevice_exit();
+        platform_driver_unregister(&wifi_driver);
+        platform_device_unregister(&icomm_wifi_device);
+        g_wifidev_registered = 0;
+    }
+    return;
+}
+static __init int tu_generic_wifi_init_module(void)
+{
+    int ret;
+    int time = 5;
+    printk("%s\n", __func__);
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+    sha1_mod_init();
+    aes_init();
+#endif
+    ret = initWlan();
+    while(time-- > 0) {
+        msleep(500);
+        if(ssv6xxx_get_dev_status() == 1)
+            break;
+        printk("%s : Retry to carddetect\n",__func__);
+        wifi_set_carddetect(0);
+        wifi_set_power(0, 50);
+        msleep(150);
+        wifi_set_power(1, 50);
+        wifi_set_carddetect(1);
+    }
+    return ret;
+}
+static __exit void tu_generic_wifi_exit_module(void)
+{
+    printk("%s\n", __func__);
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+    aes_fini();
+    sha1_mod_fini();
+#endif
+    exitWlan();
+}
+EXPORT_SYMBOL(tu_generic_wifi_init_module);
+EXPORT_SYMBOL(tu_generic_wifi_exit_module);
+module_init(tu_generic_wifi_init_module);
+module_exit(tu_generic_wifi_exit_module);
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/drivers/net/wireless/ssv6x5x/platforms/rk3126-wifi.cfg b/drivers/net/wireless/ssv6x5x/platforms/rk3126-wifi.cfg
new file mode 100755
index 000000000..ecbeab923
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/rk3126-wifi.cfg
@@ -0,0 +1,83 @@
+############################################################
+# RK3126
+# WIFI-CONFIGURATION
+##################################################
+
+##################################################
+# Firmware setting
+# Priority.1 insmod parameter "cfgfirmwarepath"
+# Priority.2 firmware_path
+# Priority.3 default firmware
+##################################################
+#firmware_path = /etc/firmware/
+
+############################################################
+# MAC address
+#
+# Priority 1. From wifi.cfg [ hw_mac & hw_mac_2 ]
+#
+# Priority 2. From e-fuse[ON/OFF switch by wifi.cfg]
+#
+# Priority 3. From insert module parameter
+#
+# Priority 4. From external file path
+#   path only support some special charater "_" ":" "/" "." "-"
+#
+# Priority 5. Default[Software mode]
+#
+#   0. => 00:33:33:33:33:33
+#   1. => Always random
+#   2. => First random and write to file[Default path mac_output_path]
+#
+############################################################
+ignore_efuse_mac = 0
+#mac_address_path = /xxxx/xxxx
+mac_address_mode = 2
+mac_output_path = /data/wifimac
+
+##################################################
+# Hardware setting
+#
+#volt regulator(DCDC-0 LDO-1)
+#
+##################################################
+volt_regulator = 1
+
+##################################################
+# Default channel after wifi on
+# value range: [1 ~ 14]
+##################################################
+#def_chan = 6
+##################################################
+# Hardware Capability Settings:
+##################################################
+hw_cap_ampdu_rx = on
+hw_cap_ampdu_tx = on
+hw_cap_tdls = off
+
+use_wpa2_only = 1
+##################################################
+# TX power level setting [0-14]
+# The larger the number the smaller the TX power
+# 0 - The maximum power
+# 1 level = -0.5db
+#
+# 6051Z .. 4 or 4
+# 6051Q .. 2 or 5
+# 6051P .. 0 or 0
+#
+##################################################
+#wifi_tx_gain_level_b = 4
+#wifi_tx_gain_level_gn = 4
+
+##################################################
+# Import extenal configuration(UP to 64 groups)
+# example:
+#    register = CE010010:91919191
+#    register = 00CC0010:00091919
+##################################################
+
+##################################################
+# The AP RSSI signal is less than -88dbm complement signal to -88dbm
+##################################################
+#beacon_rssi_minimal = 88
diff --git a/drivers/net/wireless/ssv6x5x/platforms/rk3126.cfg b/drivers/net/wireless/ssv6x5x/platforms/rk3126.cfg
new file mode 100755
index 000000000..cbe8cb2e1
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/rk3126.cfg
@@ -0,0 +1,19 @@
+############################################################
+# RK3128
+############################################################
+ccflags-y += -DCONFIG_SSV_SUPPORT_ANDROID
+#ccflags-y += -DCONFIG_SSV_SUPPORT_AES_ASM
+ccflags-y += -DCONFIG_FW_ALIGNMENT_CHECK
+ccflags-y += -DCONFIG_PLATFORM_SDIO_OUTPUT_TIMING=3
+ccflags-y += -DCONFIG_PLATFORM_SDIO_BLOCK_SIZE=128
+#ccflags-y += -DMULTI_THREAD_ENCRYPT
+#ccflags-y += -DKTHREAD_BIND
+
+############################################################
+# Compiler path
+############################################################
+SSV_CROSS = $(ANDROID_BUILD_TOP)/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi-
+SSV_KERNEL_PATH = $(ANDROID_BUILD_TOP)/kernel
+SSV_ARCH = arm
+KMODDESTDIR = $(MODDESTDIR)
+
diff --git a/drivers/net/wireless/ssv6x5x/platforms/rk3128-generic-wlan.c b/drivers/net/wireless/ssv6x5x/platforms/rk3128-generic-wlan.c
new file mode 100644
index 000000000..8de613d20
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/rk3128-generic-wlan.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/irq.h>
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/vmalloc.h>
+#include <linux/gpio.h>
+#include <linux/mmc/host.h>
+#include <linux/delay.h>
+#include <linux/regulator/consumer.h>
+#include <asm/io.h>
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
+#include <linux/printk.h>
+#include <linux/err.h>
+#else
+#include <config/printk.h>
+#endif
+extern int rockchip_wifi_power(int on);
+extern int rockchip_wifi_set_carddetect(int val);
+#define GPIO_REG_WRITEL(val,reg) do{__raw_writel(val, CTL_PIN_BASE + (reg));}while(0)
+static int g_wifidev_registered = 0;
+extern int tu_ssvdevice_init(void);
+extern void tu_ssvdevice_exit(void);
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+extern int aes_init(void);
+extern void aes_fini(void);
+extern int sha1_mod_init(void);
+extern void sha1_mod_fini(void);
+#endif
+int initWlan(void)
+{
+    int ret=0;
+    rockchip_wifi_set_carddetect(0);
+    msleep(50);
+    rockchip_wifi_power(0);
+    msleep(50);
+    rockchip_wifi_power(1);
+    msleep(50);
+    rockchip_wifi_set_carddetect(1);
+    msleep(120);
+    g_wifidev_registered = 1;
+    ret = tu_ssvdevice_init();
+    return ret;
+}
+void exitWlan(void)
+{
+    if (g_wifidev_registered) {
+        tu_ssvdevice_exit();
+        rockchip_wifi_set_carddetect(0);
+        rockchip_wifi_power(0);
+        g_wifidev_registered = 0;
+    }
+    return;
+}
+static __init int tu_generic_wifi_init_module(void)
+{
+    printk("%s\n", __func__);
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+    sha1_mod_init();
+    aes_init();
+#endif
+    return initWlan();
+}
+static __exit void tu_generic_wifi_exit_module(void)
+{
+    printk("%s\n", __func__);
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+    aes_fini();
+    sha1_mod_fini();
+#endif
+    exitWlan();
+}
+EXPORT_SYMBOL(tu_generic_wifi_init_module);
+EXPORT_SYMBOL(tu_generic_wifi_exit_module);
+module_init(tu_generic_wifi_init_module);
+module_exit(tu_generic_wifi_exit_module);
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/drivers/net/wireless/ssv6x5x/platforms/rk3128-wifi.cfg b/drivers/net/wireless/ssv6x5x/platforms/rk3128-wifi.cfg
new file mode 100755
index 000000000..d4cf39e5d
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/rk3128-wifi.cfg
@@ -0,0 +1,85 @@
+############################################################
+# RK3128
+# WIFI-CONFIGURATION
+##################################################
+
+##################################################
+# Firmware setting
+# Priority.1 insmod parameter "cfgfirmwarepath"
+# Priority.2 firmware_path
+# Priority.3 default firmware
+##################################################
+#firmware_path = /etc/firmware/
+
+############################################################
+# MAC address
+#
+# Priority 1. From wifi.cfg [ hw_mac & hw_mac_2 ]
+#
+# Priority 2. From e-fuse[ON/OFF switch by wifi.cfg]
+#
+# Priority 3. From insert module parameter
+#
+# Priority 4. From external file path
+#   path only support some special charater "_" ":" "/" "." "-"
+#
+# Priority 5. Default[Software mode]
+#
+#   0. => 00:33:33:33:33:33
+#   1. => Always random
+#   2. => First random and write to file[Default path mac_output_path]
+#
+############################################################
+ignore_efuse_mac = 0
+#mac_address_path = /xxxx/xxxx
+mac_address_mode = 2
+mac_output_path = /data/wifimac
+
+##################################################
+# Hardware setting
+#
+#volt regulator(DCDC-0 LDO-1)
+#
+##################################################
+volt_regulator = 1
+
+##################################################
+# Default channel after wifi on
+# value range: [1 ~ 14]
+##################################################
+#def_chan = 6
+##################################################
+# Hardware Capability Settings:
+##################################################
+hw_cap_ampdu_rx = on
+hw_cap_ampdu_tx = on
+hw_cap_tdls = off
+
+use_wpa2_only = 1
+##################################################
+# TX power level setting [0-14]
+# The larger the number the smaller the TX power
+# 0 - The maximum power
+# 1 level = -0.5db
+#
+# 6051Z .. 4 or 4
+# 6051Q .. 2 or 5
+# 6051P .. 0 or 0
+#
+##################################################
+#wifi_tx_gain_level_b = 2
+#wifi_tx_gain_level_gn = 5
+
+##################################################
+# Import extenal configuration(UP to 64 groups)
+# example:
+#    register = CE010010:91919191
+#    register = 00CC0010:00091919
+##################################################
+
+##################################################
+#
+# The AP RSSI signal is less than -88dbm complement signal to -88dbm
+#
+##################################################
+#beacon_rssi_minimal = 88
diff --git a/drivers/net/wireless/ssv6x5x/platforms/rk3128.cfg b/drivers/net/wireless/ssv6x5x/platforms/rk3128.cfg
new file mode 100755
index 000000000..cbe8cb2e1
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/rk3128.cfg
@@ -0,0 +1,19 @@
+############################################################
+# RK3128
+############################################################
+ccflags-y += -DCONFIG_SSV_SUPPORT_ANDROID
+#ccflags-y += -DCONFIG_SSV_SUPPORT_AES_ASM
+ccflags-y += -DCONFIG_FW_ALIGNMENT_CHECK
+ccflags-y += -DCONFIG_PLATFORM_SDIO_OUTPUT_TIMING=3
+ccflags-y += -DCONFIG_PLATFORM_SDIO_BLOCK_SIZE=128
+#ccflags-y += -DMULTI_THREAD_ENCRYPT
+#ccflags-y += -DKTHREAD_BIND
+
+############################################################
+# Compiler path
+############################################################
+SSV_CROSS = $(ANDROID_BUILD_TOP)/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi-
+SSV_KERNEL_PATH = $(ANDROID_BUILD_TOP)/kernel
+SSV_ARCH = arm
+KMODDESTDIR = $(MODDESTDIR)
+
diff --git a/drivers/net/wireless/ssv6x5x/platforms/rk322x-generic-wlan.c b/drivers/net/wireless/ssv6x5x/platforms/rk322x-generic-wlan.c
new file mode 100644
index 000000000..ade780d26
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/rk322x-generic-wlan.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/irq.h>
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/vmalloc.h>
+#include <linux/gpio.h>
+#include <linux/mmc/host.h>
+#include <linux/delay.h>
+#include <linux/regulator/consumer.h>
+#include <asm/io.h>
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
+#include <linux/printk.h>
+#include <linux/err.h>
+#else
+#include <config/printk.h>
+#endif
+extern int rockchip_wifi_power(int on);
+extern int rockchip_wifi_set_carddetect(int val);
+#ifdef ROCKCHIP_WIFI_AUTO_SUPPORT
+extern char wifi_chip_type_string[];
+#endif
+#define GPIO_REG_WRITEL(val,reg) \
+ do { \
+  __raw_writel(val, CTL_PIN_BASE + (reg)); \
+ } while (0)
+static int g_wifidev_registered = 0;
+extern int tu_ssvdevice_init(void);
+extern void tu_ssvdevice_exit(void);
+extern int ssv6xxx_get_dev_status(void);
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+extern int aes_init(void);
+extern void aes_fini(void);
+extern int sha1_mod_init(void);
+extern void sha1_mod_fini(void);
+#endif
+void ssv_wifi_power(void)
+{
+    rockchip_wifi_set_carddetect(0);
+    msleep(50);
+    rockchip_wifi_power(0);
+    msleep(50);
+    rockchip_wifi_power(1);
+    msleep(50);
+    rockchip_wifi_set_carddetect(1);
+}
+int initWlan(void)
+{
+    int ret = 0;
+    int time = 5;
+    ssv_wifi_power();
+    msleep(120);
+    g_wifidev_registered = 1;
+    ret = tu_ssvdevice_init();
+    while(time-- > 0) {
+        msleep(500);
+        if(ssv6xxx_get_dev_status() == 1)
+            break;
+        printk("%s : Retry to carddetect\n",__func__);
+        ssv_wifi_power();
+    }
+#ifdef ROCKCHIP_WIFI_AUTO_SUPPORT
+    if (!ret) {
+        strcpy(wifi_chip_type_string, "ssv6051");
+        printk(KERN_INFO "wifi_chip_type_string : %s\n",wifi_chip_type_string);
+    }
+#endif
+    return ret;
+}
+void exitWlan(void)
+{
+    if (g_wifidev_registered) {
+        tu_ssvdevice_exit();
+        msleep(50);
+#ifndef ROCKCHIP_WIFI_AUTO_SUPPORT
+        rockchip_wifi_set_carddetect(0);
+#endif
+        rockchip_wifi_power(0);
+        g_wifidev_registered = 0;
+    }
+    return;
+}
+static __init int tu_generic_wifi_init_module(void)
+{
+    printk("%s\n", __func__);
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+    sha1_mod_init();
+    aes_init();
+#endif
+    return initWlan();
+}
+static __exit void tu_generic_wifi_exit_module(void)
+{
+    printk("%s\n", __func__);
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+    aes_fini();
+    sha1_mod_fini();
+#endif
+    msleep(100);
+    exitWlan();
+}
+EXPORT_SYMBOL(tu_generic_wifi_init_module);
+EXPORT_SYMBOL(tu_generic_wifi_exit_module);
+module_init(tu_generic_wifi_init_module);
+module_exit(tu_generic_wifi_exit_module);
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/drivers/net/wireless/ssv6x5x/platforms/rk322x-wifi.cfg b/drivers/net/wireless/ssv6x5x/platforms/rk322x-wifi.cfg
new file mode 100755
index 000000000..d2f7c8544
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/rk322x-wifi.cfg
@@ -0,0 +1,78 @@
+############################################################
+# ROCKCHIP RK3X28 & RK322X
+# WIFI-CONFIGURATION
+##################################################
+
+##################################################
+# Firmware setting
+# Priority.1 insmod parameter "cfgfirmwarepath"
+# Priority.2 firmware_path
+# Priority.3 default firmware
+##################################################
+#firmware_path = /etc/firmware/
+
+############################################################
+# MAC address
+#
+# Priority 1. From wifi.cfg [ hw_mac & hw_mac_2 ]
+#
+# Priority 2. From e-fuse[ON/OFF switch by wifi.cfg]
+#
+# Priority 3. From insert module parameter
+#
+# Priority 4. From external file path
+#   path only support some special charater "_" ":" "/" "." "-"
+#
+# Priority 5. Default[Software mode]
+#
+#   0. => 00:33:33:33:33:33
+#   1. => Always random
+#   2. => First random and write to file[Default path mac_output_path]
+#
+############################################################
+ignore_efuse_mac = 0
+#mac_address_path = /xxxx/xxxx
+mac_address_mode = 2
+mac_output_path = /data/wifimac
+
+##################################################
+# Hardware setting
+#
+#volt regulator(DCDC-0 LDO-1)
+#
+##################################################
+volt_regulator = 1
+
+##################################################
+# Default channel after wifi on
+# value range: [1 ~ 14]
+##################################################
+#def_chan = 6
+##################################################
+# Hardware Capability Settings:
+##################################################
+hw_cap_ampdu_rx = on
+hw_cap_ampdu_tx = on
+hw_cap_tdls = off
+
+use_wpa2_only = 1
+##################################################
+# TX power level setting [0-14]
+# The larger the number the smaller the TX power
+# 0 - The maximum power
+# 1 level = -0.5db
+#
+# 6051Z .. 4 or 4
+# 6051Q .. 2 or 5
+# 6051P .. 0 or 0
+#
+##################################################
+#wifi_tx_gain_level_b = 2
+#wifi_tx_gain_level_gn = 5
+
+##################################################
+# Import extenal configuration(UP to 64 groups)
+# example:
+#    register = CE010010:91919191
+#    register = 00CC0010:00091919
+##################################################
diff --git a/drivers/net/wireless/ssv6x5x/platforms/rk322x.cfg b/drivers/net/wireless/ssv6x5x/platforms/rk322x.cfg
new file mode 100755
index 000000000..f05312d00
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/rk322x.cfg
@@ -0,0 +1,21 @@
+############################################################
+# RK322x
+############################################################
+ccflags-y += -DCONFIG_SSV_SUPPORT_ANDROID
+#ccflags-y += -DCONFIG_SSV_SUPPORT_AES_ASM
+ccflags-y += -DCONFIG_FW_ALIGNMENT_CHECK
+ccflags-y += -DCONFIG_PLATFORM_SDIO_OUTPUT_TIMING=3
+ccflags-y += -DCONFIG_PLATFORM_SDIO_BLOCK_SIZE=128
+#ccflags-y += -DMULTI_THREAD_ENCRYPT
+#ccflags-y += -DKTHREAD_BIND
+#ccflags-y += -DROCKCHIP_WIFI_AUTO_SUPPORT
+ccflags-y += -DCONFIG_SSV_RSSI
+
+############################################################
+# Compiler path
+############################################################
+SSV_CROSS = $(ANDROID_BUILD_TOP)/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi-
+SSV_KERNEL_PATH = $(ANDROID_BUILD_TOP)/kernel
+SSV_ARCH = arm
+KMODDESTDIR = $(MODDESTDIR)
+
diff --git a/drivers/net/wireless/ssv6x5x/platforms/t10-generic-wlan.c b/drivers/net/wireless/ssv6x5x/platforms/t10-generic-wlan.c
new file mode 100644
index 000000000..39a3361fc
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/t10-generic-wlan.c
@@ -0,0 +1,276 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/irq.h>
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/vmalloc.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/pm_runtime.h>
+#include <linux/mmc/host.h>
+#include <linux/delay.h>
+#include <linux/semaphore.h>
+#include <linux/regulator/consumer.h>
+#include <asm/io.h>
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
+#include <linux/printk.h>
+#include <linux/err.h>
+#else
+#include <config/printk.h>
+#endif
+#if LINUX_VERSION_CODE > KERNEL_VERSION(3,2,0)
+#include <linux/wlan_plat.h>
+#else
+struct wifi_platform_data {
+    int (*set_power)(int val);
+    int (*set_reset)(int val);
+    int (*set_carddetect)(int val);
+    void *(*mem_prealloc)(int section, unsigned long size);
+    int (*get_mac_addr)(unsigned char *buf);
+    void *(*get_country_code)(char *ccode);
+};
+#endif
+#define GPIO_REG_WRITEL(val,reg) do{__raw_writel(val, CTL_PIN_BASE + (reg));}while(0)
+static int g_wifidev_registered = 0;
+static struct semaphore wifi_control_sem;
+static struct wifi_platform_data *wifi_control_data = NULL;
+static struct resource *wifi_irqres = NULL;
+static int g_wifi_irq_rc=0;
+#define SDIO_ID 2
+#define IRQ_RES_NAME "ssv_wlan_irq"
+#define WIFI_HOST_WAKE 0xFFFF
+extern int ssv_6xxx_wlan_init(void);
+extern int ssv_wlan_power_on(int flag);
+extern int ssv_wlan_power_off(int flag);
+static int wifi_pm_gpio_ctrl(char* name, int level)
+{
+    (void)name;
+    (void)level;
+    if (level) {
+        ssv_wlan_power_on(1);
+    } else {
+        ssv_wlan_power_off(1);
+    }
+    return 0;
+}
+static int ssv_wifi_power(int on)
+{
+    printk("ssv pwr on=%d\n",on);
+    if(on) {
+        wifi_pm_gpio_ctrl("wifi_ssv6200_power", 0);
+        mdelay(50);
+        wifi_pm_gpio_ctrl("wifi_ssv6200_power", 1);
+    } else {
+        wifi_pm_gpio_ctrl("wifi_ssv6200_power", 0);
+    }
+    return 0;
+}
+static int ssv_wifi_reset(int on)
+{
+    return 0;
+}
+int ssv_wifi_set_carddetect(int val)
+{
+    if (val) {
+        ssv_wlan_power_on(1);
+    } else {
+        ssv_wlan_power_off(1);
+    }
+    return 0;
+}
+static struct wifi_platform_data ssv_wifi_control = {
+    .set_power = ssv_wifi_power,
+    .set_reset = ssv_wifi_reset,
+    .set_carddetect = ssv_wifi_set_carddetect,
+};
+static struct resource resources[] = {
+    {
+        .start = WIFI_HOST_WAKE,
+        .flags = IORESOURCE_IRQ,
+        .name = IRQ_RES_NAME,
+    },
+};
+void ssv_wifi_device_release(struct device *dev)
+{
+    printk(KERN_INFO "ssv_wifi_device_release\n");
+}
+static struct platform_device ssv_wifi_device = {
+    .name = "ssv_wlan",
+    .id = 1,
+    .num_resources = ARRAY_SIZE(resources),
+    .resource = resources,
+    .dev = {
+        .platform_data = &ssv_wifi_control,
+        .release = ssv_wifi_device_release,
+    },
+};
+int wifi_set_power(int on, unsigned long msec)
+{
+    if (wifi_control_data && wifi_control_data->set_power) {
+        wifi_control_data->set_power(on);
+    }
+    if (msec)
+        msleep(msec);
+    return 0;
+}
+int wifi_set_reset(int on, unsigned long msec)
+{
+    if (wifi_control_data && wifi_control_data->set_reset) {
+        wifi_control_data->set_reset(on);
+    }
+    if (msec)
+        msleep(msec);
+    return 0;
+}
+static int wifi_set_carddetect(int on)
+{
+    if (wifi_control_data && wifi_control_data->set_carddetect) {
+        printk("[Debug-%s-%d]------\n",__func__,__LINE__);
+        wifi_control_data->set_carddetect(on);
+    }
+    return 0;
+}
+static irqreturn_t wifi_wakeup_irq_handler(int irq, void *dev)
+{
+    printk("sdhci_wakeup_irq_handler\n");
+    disable_irq_nosync(irq);
+    return IRQ_HANDLED;
+}
+void setup_wifi_wakeup_BB(struct platform_device *pdev, bool bEnable)
+{
+    int rc=0,ret=0;
+    if (bEnable) {
+        wifi_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ, IRQ_RES_NAME);
+        rc = (int)wifi_irqres->start;
+        g_wifi_irq_rc = rc;
+        ret = request_threaded_irq(rc,
+                                   NULL,
+                                   (void *)wifi_wakeup_irq_handler,
+#if LINUX_VERSION_CODE > KERNEL_VERSION(3,0,0)
+                                   IRQ_TYPE_LEVEL_HIGH | IRQF_ONESHOT |IRQF_FORCE_RESUME,
+#else
+                                   IRQ_TYPE_LEVEL_HIGH | IRQF_ONESHOT,
+#endif
+                                   "wlan_wakeup_irq", NULL);
+        enable_irq_wake(g_wifi_irq_rc);
+    } else {
+        if(g_wifi_irq_rc) {
+            free_irq(g_wifi_irq_rc,NULL);
+            g_wifi_irq_rc = 0;
+        }
+    }
+}
+static int wifi_probe(struct platform_device *pdev)
+{
+    struct wifi_platform_data *wifi_ctrl =
+        (struct wifi_platform_data *)(pdev->dev.platform_data);
+    printk(KERN_ALERT "wifi_probe\n");
+    wifi_control_data = wifi_ctrl;
+#ifndef CONFIG_SSV6XXX
+    printk("[Debug-%s-%d]------\n",__func__,__LINE__);
+    ssv_6xxx_wlan_init();
+#endif
+    printk("[Debug-%s-%d]------\n",__func__,__LINE__);
+    wifi_set_carddetect(1);
+    up(&wifi_control_sem);
+    return 0;
+}
+static int wifi_remove(struct platform_device *pdev)
+{
+    struct wifi_platform_data *wifi_ctrl =
+        (struct wifi_platform_data *)(pdev->dev.platform_data);
+    wifi_control_data = wifi_ctrl;
+    wifi_set_power(0, 0);
+    wifi_set_carddetect(0);
+    setup_wifi_wakeup_BB(pdev,false);
+    return 0;
+}
+static int wifi_suspend(struct platform_device *pdev, pm_message_t state)
+{
+    setup_wifi_wakeup_BB(pdev,true);
+    return 0;
+}
+static int wifi_resume(struct platform_device *pdev)
+{
+    setup_wifi_wakeup_BB(pdev,false);
+    return 0;
+}
+static struct platform_driver wifi_driver = {
+    .probe = wifi_probe,
+    .remove = wifi_remove,
+    .suspend = wifi_suspend,
+    .resume = wifi_resume,
+    .driver = {
+        .name = "ssv_wlan",
+    }
+};
+extern int tu_ssvdevice_init(void);
+extern void tu_ssvdevice_exit(void);
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+extern int aes_init(void);
+extern void aes_fini(void);
+extern int sha1_mod_init(void);
+extern void sha1_mod_fini(void);
+#endif
+int initWlan(void)
+{
+    int ret=0;
+    sema_init(&wifi_control_sem, 0);
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+    sha1_mod_init();
+    aes_init();
+#endif
+    platform_device_register(&ssv_wifi_device);
+    platform_driver_register(&wifi_driver);
+    g_wifidev_registered = 1;
+    if (down_timeout(&wifi_control_sem, msecs_to_jiffies(1000)) != 0) {
+        ret = -EINVAL;
+        printk(KERN_ALERT "%s: platform_driver_register timeout\n", __FUNCTION__);
+    }
+    ret = tu_ssvdevice_init();
+    return ret;
+}
+void exitWlan(void)
+{
+    if (g_wifidev_registered) {
+        tu_ssvdevice_exit();
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+        aes_fini();
+        sha1_mod_fini();
+#endif
+        platform_driver_unregister(&wifi_driver);
+        platform_device_unregister(&ssv_wifi_device);
+        g_wifidev_registered = 0;
+    }
+    return;
+}
+static int tu_generic_wifi_init_module(void)
+{
+    return initWlan();
+}
+static void tu_generic_wifi_exit_module(void)
+{
+    exitWlan();
+}
+EXPORT_SYMBOL(tu_generic_wifi_init_module);
+EXPORT_SYMBOL(tu_generic_wifi_exit_module);
+#ifdef CONFIG_SSV6XXX
+late_initcall(tu_generic_wifi_init_module);
+#else
+module_init(tu_generic_wifi_init_module);
+#endif
+module_exit(tu_generic_wifi_exit_module);
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/drivers/net/wireless/ssv6x5x/platforms/t10-wifi.cfg b/drivers/net/wireless/ssv6x5x/platforms/t10-wifi.cfg
new file mode 100755
index 000000000..1731953d5
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/t10-wifi.cfg
@@ -0,0 +1,82 @@
+############################################################
+# Ingenic T10
+# WIFI-CONFIGURATION
+##################################################
+
+##################################################
+# Firmware setting
+# Priority.1 insmod parameter "cfgfirmwarepath"
+# Priority.2 firmware_path
+# Priority.3 default firmware
+##################################################
+#firmware_path =
+
+############################################################
+# MAC address
+#
+# Priority 1. From wifi.cfg [ hw_mac & hw_mac_2 ]
+#
+# Priority 2. From e-fuse[ON/OFF switch by wifi.cfg]
+#
+# Priority 3. From insert module parameter
+#
+# Priority 4. From external file path
+#   path only support some special charater "_" ":" "/" "." "-"
+#
+# Priority 5. Default[Software mode]
+#
+#   0. => 00:33:33:33:33:33
+#   1. => Always random
+#   2. => First random and write to file[Default path mac_output_path]
+#
+############################################################
+ignore_efuse_mac = 0
+mac_address_mode = 2
+mac_output_path = /data/wifimac
+
+##################################################
+# Hardware setting
+#
+#volt regulator(DCDC-0 LDO-1)
+#
+##################################################
+volt_regulator = 1
+
+##################################################
+# Default channel after wifi on
+# value range: [1 ~ 14]
+##################################################
+#def_chan = 6
+
+##################################################
+# Hardware Capability Settings:
+##################################################
+hw_cap_ampdu_rx = on
+hw_cap_ampdu_tx = off
+hw_cap_tdls = off
+
+use_wpa2_only = 1
+
+##################################################
+# TX power level setting [0-14]
+# The larger the number the smaller the TX power
+# 0 - The maximum power
+# 1 level = -0.5db
+#
+# 6051Z .. 4 or 4
+# 6051Q .. 2 or 5
+# 6051P .. 0 or 0
+#
+##################################################
+#wifi_tx_gain_level_b = 4
+#wifi_tx_gain_level_gn = 4
+
+##################################################
+# Import extenal configuration(UP to 64 groups)
+# example:
+#    register = CE010010:91919191
+#    register = 00CC0010:00091919
+##################################################
+#register = CE010008:008B7C1C
+#register = CE010014:3D7E84FE
+#register = CE010048:FCCCCC27
diff --git a/drivers/net/wireless/ssv6x5x/platforms/t10.cfg b/drivers/net/wireless/ssv6x5x/platforms/t10.cfg
new file mode 100755
index 000000000..b574a7edd
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/t10.cfg
@@ -0,0 +1,23 @@
+############################################################
+# Ingenic T10
+############################################################
+
+#ccflags-y += -DCONFIG_SSV_SUPPORT_ANDROID
+ccflags-y += -DCONFIG_SSV_BUILD_AS_ONE_KO
+#ccflags-y += -DCONFIG_SSV_SUPPORT_AES_ASM
+ccflags-y += -DCONFIG_FW_ALIGNMENT_CHECK
+ccflags-y += -DCONFIG_PLATFORM_SDIO_OUTPUT_TIMING=0
+
+ccflags-y += -DCONFIG_SMARTLINK
+############################################################
+# SSV Airkiss
+############################################################
+cflags-y += -DCONFIG_SSV_SMARTLINK
+
+############################################################
+# Compiler path
+############################################################
+#SSV_CROSS = $(R_CROSS_COMPILE)
+#SSV_KERNEL_PATH = $(KERNEL_BUILD_PATH)
+#SSV_ARCH = $(R_ARCH)
+#KMODDESTDIR = $(MODDESTDIR)
diff --git a/drivers/net/wireless/ssv6x5x/platforms/t20-generic-wlan.c b/drivers/net/wireless/ssv6x5x/platforms/t20-generic-wlan.c
new file mode 100644
index 000000000..76f3694ca
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/t20-generic-wlan.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/vmalloc.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/regulator/consumer.h>
+#include <asm/io.h>
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
+#include <linux/printk.h>
+#include <linux/err.h>
+#else
+#include <config/printk.h>
+#endif
+extern int tu_ssvdevice_init(void);
+extern void tu_ssvdevice_exit(void);
+int initWlan(void)
+{
+    int ret=0;
+    printk(KERN_INFO "wlan.c initWlan\n");
+    ret = tu_ssvdevice_init();
+    return ret;
+}
+void exitWlan(void)
+{
+    tu_ssvdevice_exit();
+    return;
+}
+static int tu_generic_wifi_init_module(void)
+{
+    return initWlan();
+}
+static void tu_generic_wifi_exit_module(void)
+{
+    exitWlan();
+}
+EXPORT_SYMBOL(tu_generic_wifi_init_module);
+EXPORT_SYMBOL(tu_generic_wifi_exit_module);
+#ifdef CONFIG_SSV6X5X
+late_initcall(tu_generic_wifi_init_module);
+#else
+module_init(tu_generic_wifi_init_module);
+#endif
+module_exit(tu_generic_wifi_exit_module);
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/drivers/net/wireless/ssv6x5x/platforms/t20-wifi.cfg b/drivers/net/wireless/ssv6x5x/platforms/t20-wifi.cfg
new file mode 100755
index 000000000..1731953d5
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/t20-wifi.cfg
@@ -0,0 +1,82 @@
+############################################################
+# Ingenic T10
+# WIFI-CONFIGURATION
+##################################################
+
+##################################################
+# Firmware setting
+# Priority.1 insmod parameter "cfgfirmwarepath"
+# Priority.2 firmware_path
+# Priority.3 default firmware
+##################################################
+#firmware_path =
+
+############################################################
+# MAC address
+#
+# Priority 1. From wifi.cfg [ hw_mac & hw_mac_2 ]
+#
+# Priority 2. From e-fuse[ON/OFF switch by wifi.cfg]
+#
+# Priority 3. From insert module parameter
+#
+# Priority 4. From external file path
+#   path only support some special charater "_" ":" "/" "." "-"
+#
+# Priority 5. Default[Software mode]
+#
+#   0. => 00:33:33:33:33:33
+#   1. => Always random
+#   2. => First random and write to file[Default path mac_output_path]
+#
+############################################################
+ignore_efuse_mac = 0
+mac_address_mode = 2
+mac_output_path = /data/wifimac
+
+##################################################
+# Hardware setting
+#
+#volt regulator(DCDC-0 LDO-1)
+#
+##################################################
+volt_regulator = 1
+
+##################################################
+# Default channel after wifi on
+# value range: [1 ~ 14]
+##################################################
+#def_chan = 6
+
+##################################################
+# Hardware Capability Settings:
+##################################################
+hw_cap_ampdu_rx = on
+hw_cap_ampdu_tx = off
+hw_cap_tdls = off
+
+use_wpa2_only = 1
+
+##################################################
+# TX power level setting [0-14]
+# The larger the number the smaller the TX power
+# 0 - The maximum power
+# 1 level = -0.5db
+#
+# 6051Z .. 4 or 4
+# 6051Q .. 2 or 5
+# 6051P .. 0 or 0
+#
+##################################################
+#wifi_tx_gain_level_b = 4
+#wifi_tx_gain_level_gn = 4
+
+##################################################
+# Import extenal configuration(UP to 64 groups)
+# example:
+#    register = CE010010:91919191
+#    register = 00CC0010:00091919
+##################################################
+#register = CE010008:008B7C1C
+#register = CE010014:3D7E84FE
+#register = CE010048:FCCCCC27
diff --git a/drivers/net/wireless/ssv6x5x/platforms/t20.cfg b/drivers/net/wireless/ssv6x5x/platforms/t20.cfg
new file mode 100755
index 000000000..513dccd40
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/t20.cfg
@@ -0,0 +1,23 @@
+############################################################
+# Ingenic T10
+############################################################
+
+#ccflags-y += -DCONFIG_SSV_SUPPORT_ANDROID
+ccflags-y += -DCONFIG_SSV_BUILD_AS_ONE_KO
+#ccflags-y += -DCONFIG_SSV_SUPPORT_AES_ASM
+ccflags-y += -DCONFIG_FW_ALIGNMENT_CHECK
+ccflags-y += -DCONFIG_PLATFORM_SDIO_OUTPUT_TIMING=0
+
+#ccflags-y += -DCONFIG_SMARTLINK
+############################################################
+# SSV Airkiss
+############################################################
+#cflags-y += -DCONFIG_SSV_SMARTLINK
+
+############################################################
+# Compiler path
+############################################################
+#SSV_CROSS = $(R_CROSS_COMPILE)
+#SSV_KERNEL_PATH = $(KERNEL_BUILD_PATH)
+#SSV_ARCH = $(R_ARCH)
+#KMODDESTDIR = $(MODDESTDIR)
diff --git a/drivers/net/wireless/ssv6x5x/platforms/x1000-generic-wlan.c b/drivers/net/wireless/ssv6x5x/platforms/x1000-generic-wlan.c
new file mode 100644
index 000000000..b800e1681
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/x1000-generic-wlan.c
@@ -0,0 +1,273 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/irq.h>
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/vmalloc.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/pm_runtime.h>
+#include <linux/mmc/host.h>
+#include <linux/delay.h>
+#include <linux/semaphore.h>
+#include <linux/regulator/consumer.h>
+#include <asm/io.h>
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
+#include <linux/printk.h>
+#include <linux/err.h>
+#else
+#include <config/printk.h>
+#endif
+#if LINUX_VERSION_CODE > KERNEL_VERSION(3,2,0)
+#include <linux/wlan_plat.h>
+#else
+struct wifi_platform_data {
+    int (*set_power)(int val);
+    int (*set_reset)(int val);
+    int (*set_carddetect)(int val);
+    void *(*mem_prealloc)(int section, unsigned long size);
+    int (*get_mac_addr)(unsigned char *buf);
+    void *(*get_country_code)(char *ccode);
+};
+#endif
+#define GPIO_REG_WRITEL(val,reg) do{__raw_writel(val, CTL_PIN_BASE + (reg));}while(0)
+static int g_wifidev_registered = 0;
+static struct semaphore wifi_control_sem;
+static struct wifi_platform_data *wifi_control_data = NULL;
+static struct resource *wifi_irqres = NULL;
+static int g_wifi_irq_rc=0;
+#define SDIO_ID 2
+#define IRQ_RES_NAME "ssv_wlan_irq"
+#define WIFI_HOST_WAKE 0xFFFF
+extern int ssv_6xxx_wlan_init(void);
+extern int ssv_wlan_power_on(int flag);
+extern int ssv_wlan_power_off(int flag);
+static int wifi_pm_gpio_ctrl(char* name, int level)
+{
+    (void)name;
+    (void)level;
+    if (level) {
+        ssv_wlan_power_on(1);
+    } else {
+        ssv_wlan_power_off(1);
+    }
+    return 0;
+}
+static int ssv_wifi_power(int on)
+{
+    printk("ssv pwr on=%d\n",on);
+    if(on) {
+        wifi_pm_gpio_ctrl("wifi_ssv6200_power", 0);
+        mdelay(50);
+        wifi_pm_gpio_ctrl("wifi_ssv6200_power", 1);
+    } else {
+        wifi_pm_gpio_ctrl("wifi_ssv6200_power", 0);
+    }
+    return 0;
+}
+static int ssv_wifi_reset(int on)
+{
+    return 0;
+}
+int ssv_wifi_set_carddetect(int val)
+{
+    if (val) {
+        ssv_wlan_power_on(1);
+    } else {
+        ssv_wlan_power_off(1);
+    }
+    return 0;
+}
+static struct wifi_platform_data ssv_wifi_control = {
+    .set_power = ssv_wifi_power,
+    .set_reset = ssv_wifi_reset,
+    .set_carddetect = ssv_wifi_set_carddetect,
+};
+static struct resource resources[] = {
+    {
+        .start = WIFI_HOST_WAKE,
+        .flags = IORESOURCE_IRQ,
+        .name = IRQ_RES_NAME,
+    },
+};
+void ssv_wifi_device_release(struct device *dev)
+{
+    printk(KERN_INFO "ssv_wifi_device_release\n");
+}
+static struct platform_device ssv_wifi_device = {
+    .name = "ssv_wlan",
+    .id = 1,
+    .num_resources = ARRAY_SIZE(resources),
+    .resource = resources,
+    .dev = {
+        .platform_data = &ssv_wifi_control,
+        .release = ssv_wifi_device_release,
+    },
+};
+int wifi_set_power(int on, unsigned long msec)
+{
+    if (wifi_control_data && wifi_control_data->set_power) {
+        wifi_control_data->set_power(on);
+    }
+    if (msec)
+        msleep(msec);
+    return 0;
+}
+int wifi_set_reset(int on, unsigned long msec)
+{
+    if (wifi_control_data && wifi_control_data->set_reset) {
+        wifi_control_data->set_reset(on);
+    }
+    if (msec)
+        msleep(msec);
+    return 0;
+}
+static int wifi_set_carddetect(int on)
+{
+    if (wifi_control_data && wifi_control_data->set_carddetect) {
+        wifi_control_data->set_carddetect(on);
+    }
+    return 0;
+}
+static irqreturn_t wifi_wakeup_irq_handler(int irq, void *dev)
+{
+    printk("sdhci_wakeup_irq_handler\n");
+    disable_irq_nosync(irq);
+    return IRQ_HANDLED;
+}
+void setup_wifi_wakeup_BB(struct platform_device *pdev, bool bEnable)
+{
+    int rc=0,ret=0;
+    if (bEnable) {
+        wifi_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ, IRQ_RES_NAME);
+        rc = (int)wifi_irqres->start;
+        g_wifi_irq_rc = rc;
+        ret = request_threaded_irq(rc,
+                                   NULL,
+                                   (void *)wifi_wakeup_irq_handler,
+#if LINUX_VERSION_CODE > KERNEL_VERSION(3,0,0)
+                                   IRQ_TYPE_LEVEL_HIGH | IRQF_ONESHOT |IRQF_FORCE_RESUME,
+#else
+                                   IRQ_TYPE_LEVEL_HIGH | IRQF_ONESHOT,
+#endif
+                                   "wlan_wakeup_irq", NULL);
+        enable_irq_wake(g_wifi_irq_rc);
+    } else {
+        if(g_wifi_irq_rc) {
+            free_irq(g_wifi_irq_rc,NULL);
+            g_wifi_irq_rc = 0;
+        }
+    }
+}
+static int wifi_probe(struct platform_device *pdev)
+{
+    struct wifi_platform_data *wifi_ctrl =
+        (struct wifi_platform_data *)(pdev->dev.platform_data);
+    printk(KERN_ALERT "wifi_probe\n");
+    wifi_control_data = wifi_ctrl;
+#ifndef CONFIG_SSV6XXX
+    ssv_6xxx_wlan_init();
+#endif
+    wifi_set_carddetect(1);
+    up(&wifi_control_sem);
+    return 0;
+}
+static int wifi_remove(struct platform_device *pdev)
+{
+    struct wifi_platform_data *wifi_ctrl =
+        (struct wifi_platform_data *)(pdev->dev.platform_data);
+    wifi_control_data = wifi_ctrl;
+    wifi_set_power(0, 0);
+    wifi_set_carddetect(0);
+    setup_wifi_wakeup_BB(pdev,false);
+    return 0;
+}
+static int wifi_suspend(struct platform_device *pdev, pm_message_t state)
+{
+    setup_wifi_wakeup_BB(pdev,true);
+    return 0;
+}
+static int wifi_resume(struct platform_device *pdev)
+{
+    setup_wifi_wakeup_BB(pdev,false);
+    return 0;
+}
+static struct platform_driver wifi_driver = {
+    .probe = wifi_probe,
+    .remove = wifi_remove,
+    .suspend = wifi_suspend,
+    .resume = wifi_resume,
+    .driver = {
+        .name = "ssv_wlan",
+    }
+};
+extern int tu_ssvdevice_init(void);
+extern void tu_ssvdevice_exit(void);
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+extern int aes_init(void);
+extern void aes_fini(void);
+extern int sha1_mod_init(void);
+extern void sha1_mod_fini(void);
+#endif
+int initWlan(void)
+{
+    int ret=0;
+    sema_init(&wifi_control_sem, 0);
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+    sha1_mod_init();
+    aes_init();
+#endif
+    platform_device_register(&ssv_wifi_device);
+    platform_driver_register(&wifi_driver);
+    g_wifidev_registered = 1;
+    if (down_timeout(&wifi_control_sem, msecs_to_jiffies(1000)) != 0) {
+        ret = -EINVAL;
+        printk(KERN_ALERT "%s: platform_driver_register timeout\n", __FUNCTION__);
+    }
+    ret = tu_ssvdevice_init();
+    return ret;
+}
+void exitWlan(void)
+{
+    if (g_wifidev_registered) {
+        tu_ssvdevice_exit();
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+        aes_fini();
+        sha1_mod_fini();
+#endif
+        platform_driver_unregister(&wifi_driver);
+        platform_device_unregister(&ssv_wifi_device);
+        g_wifidev_registered = 0;
+    }
+    return;
+}
+static int tu_generic_wifi_init_module(void)
+{
+    return initWlan();
+}
+static void tu_generic_wifi_exit_module(void)
+{
+    exitWlan();
+}
+EXPORT_SYMBOL(tu_generic_wifi_init_module);
+EXPORT_SYMBOL(tu_generic_wifi_exit_module);
+#ifdef CONFIG_SSV6XXX
+late_initcall(tu_generic_wifi_init_module);
+#else
+module_init(tu_generic_wifi_init_module);
+#endif
+module_exit(tu_generic_wifi_exit_module);
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/drivers/net/wireless/ssv6x5x/platforms/x1000-wifi.cfg b/drivers/net/wireless/ssv6x5x/platforms/x1000-wifi.cfg
new file mode 100755
index 000000000..5395d16ae
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/x1000-wifi.cfg
@@ -0,0 +1,81 @@
+############################################################
+# Ingenic X1000
+# WIFI-CONFIGURATION
+##################################################
+
+##################################################
+# Firmware setting
+# Priority.1 insmod parameter "cfgfirmwarepath"
+# Priority.2 firmware_path
+# Priority.3 default firmware
+##################################################
+#firmware_path =
+
+############################################################
+# MAC address
+#
+# Priority 1. From wifi.cfg [ hw_mac & hw_mac_2 ]
+#
+# Priority 2. From e-fuse[ON/OFF switch by wifi.cfg]
+#
+# Priority 3. From insert module parameter
+#
+# Priority 4. From external file path
+#   path only support some special charater "_" ":" "/" "." "-"
+#
+# Priority 5. Default[Software mode]
+#
+#   0. => 00:33:33:33:33:33
+#   1. => Always random
+#   2. => First random and write to file[Default path mac_output_path]
+#
+############################################################
+ignore_efuse_mac = 0
+mac_address_mode = 2
+mac_output_path = /opt/conf/wifimac
+
+##################################################
+# Hardware setting
+#
+#volt regulator(DCDC-0 LDO-1)
+#
+##################################################
+volt_regulator = 1
+
+##################################################
+# Default channel after wifi on
+# value range: [1 ~ 14]
+##################################################
+def_chan = 6
+##################################################
+# Hardware Capability Settings:
+##################################################
+hw_cap_ampdu_rx = on
+hw_cap_ampdu_tx = off
+hw_cap_tdls = off
+
+use_wpa2_only = 1
+
+##################################################
+# TX power level setting [0-14]
+# The larger the number the smaller the TX power
+# 0 - The maximum power
+# 1 level = -0.5db
+#
+# 6051Z .. 4 or 4
+# 6051Q .. 2 or 5
+# 6051P .. 0 or 0
+#
+##################################################
+#wifi_tx_gain_level_b = 4
+#wifi_tx_gain_level_gn = 4
+
+##################################################
+# Import extenal configuration(UP to 64 groups)
+# example:
+#    register = CE010010:91919191
+#    register = 00CC0010:00091919
+##################################################
+#register = CE010008:008B7C1C
+#register = CE010014:3D7E84FE
+#register = CE010048:FCCCCC27
diff --git a/drivers/net/wireless/ssv6x5x/platforms/x1000.cfg b/drivers/net/wireless/ssv6x5x/platforms/x1000.cfg
new file mode 100755
index 000000000..a418a5fe9
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/x1000.cfg
@@ -0,0 +1,22 @@
+############################################################
+# Ingenic X1000
+############################################################
+
+#ccflags-y += -DCONFIG_SSV_SUPPORT_ANDROID
+ccflags-y += -DCONFIG_SSV_BUILD_AS_ONE_KO
+#ccflags-y += -DCONFIG_SSV_SUPPORT_AES_ASM
+ccflags-y += -DCONFIG_FW_ALIGNMENT_CHECK
+ccflags-y += -DCONFIG_PLATFORM_SDIO_OUTPUT_TIMING=0
+ccflags-y += -DCONFIG_SMARTLINK
+############################################################
+# SSV Airkiss
+############################################################
+ccflags-y += -DCONFIG_SSV_SMARTLINK
+
+############################################################
+# Compiler path
+############################################################
+#SSV_CROSS = $(R_CROSS_COMPILE)
+#SSV_KERNEL_PATH = $(KERNEL_BUILD_PATH)
+#SSV_ARCH = $(R_ARCH)
+#KMODDESTDIR = $(MODDESTDIR)
diff --git a/drivers/net/wireless/ssv6x5x/platforms/xm-hi3518-generic-wlan.c b/drivers/net/wireless/ssv6x5x/platforms/xm-hi3518-generic-wlan.c
new file mode 100644
index 000000000..817f0a4e7
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/xm-hi3518-generic-wlan.c
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/irq.h>
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/vmalloc.h>
+#include <linux/gpio.h>
+#include <linux/mmc/host.h>
+#include <linux/delay.h>
+#include <linux/regulator/consumer.h>
+#include <asm/io.h>
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
+#include <linux/printk.h>
+#include <linux/err.h>
+#else
+#include <config/printk.h>
+#endif
+#define GPIO_REG_WRITEL(val,reg) do{__raw_writel(val, CTL_PIN_BASE + (reg));}while(0)
+extern void mmc_rescan_sdio(void);
+extern void wifi_power(int on);
+static int g_wifidev_registered = 0;
+extern int tu_ssvdevice_init(void);
+extern void tu_ssvdevice_exit(void);
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+extern int aes_init(void);
+extern void aes_fini(void);
+extern int sha1_mod_init(void);
+extern void sha1_mod_fini(void);
+#endif
+int initWlan(void)
+{
+    int ret=0;
+    wifi_power(0);
+    mdelay(10);
+    wifi_power(1);
+    mdelay(120);
+    mmc_rescan_sdio();
+    mdelay(120);
+    g_wifidev_registered = 1;
+    ret = tu_ssvdevice_init();
+    return ret;
+}
+void exitWlan(void)
+{
+    if (g_wifidev_registered) {
+        tu_ssvdevice_exit();
+        wifi_power(0);
+        g_wifidev_registered = 0;
+    }
+    return;
+}
+static __init int tu_generic_wifi_init_module(void)
+{
+    printk("%s\n", __func__);
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+    sha1_mod_init();
+    aes_init();
+#endif
+    return initWlan();
+}
+static __exit void tu_generic_wifi_exit_module(void)
+{
+    printk("%s\n", __func__);
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+    aes_fini();
+    sha1_mod_fini();
+#endif
+    exitWlan();
+}
+EXPORT_SYMBOL(tu_generic_wifi_init_module);
+EXPORT_SYMBOL(tu_generic_wifi_exit_module);
+module_init(tu_generic_wifi_init_module);
+module_exit(tu_generic_wifi_exit_module);
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/drivers/net/wireless/ssv6x5x/platforms/xm-hi3518-wifi.cfg b/drivers/net/wireless/ssv6x5x/platforms/xm-hi3518-wifi.cfg
new file mode 100755
index 000000000..302df70de
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/xm-hi3518-wifi.cfg
@@ -0,0 +1,83 @@
+############################################################
+# hi3518
+# WIFI-CONFIGURATION
+##################################################
+
+##################################################
+# Firmware setting
+# Priority.1 insmod parameter "cfgfirmwarepath"
+# Priority.2 firmware_path
+# Priority.3 default firmware
+##################################################
+firmware_path = /dev/
+
+############################################################
+# MAC address
+#
+# Priority 1. From wifi.cfg [ hw_mac & hw_mac_2 ]
+#
+# Priority 2. From e-fuse[ON/OFF switch by wifi.cfg]
+#
+# Priority 3. From insert module parameter
+#
+# Priority 4. From external file path
+#   path only support some special charater "_" ":" "/" "." "-"
+#
+# Priority 5. Default[Software mode]
+#
+#   0. => 00:33:33:33:33:33
+#   1. => Always random
+#   2. => First random and write to file[Default path mac_output_path]
+#
+############################################################
+ignore_efuse_mac = 0
+#mac_address_path = /xxxx/xxxx
+mac_address_mode = 2
+mac_output_path = /data/wifimac
+
+##################################################
+# Hardware setting
+#
+#volt regulator(DCDC-0 LDO-1)
+#
+##################################################
+volt_regulator = 1
+
+##################################################
+# Default channel after wifi on
+# value range: [1 ~ 14]
+##################################################
+def_chan = 6
+##################################################
+# Hardware Capability Settings:
+##################################################
+hw_cap_ampdu_rx = on
+hw_cap_ampdu_tx = on
+hw_cap_tdls = off
+
+use_wpa2_only = 1
+##################################################
+# TX power level setting [0-14]
+# The larger the number the smaller the TX power
+# 0 - The maximum power
+# 1 level = -0.5db
+#
+# 6051Z .. 4 or 4
+# 6051Q .. 2 or 5
+# 6051P .. 0 or 0
+#
+##################################################
+#wifi_tx_gain_level_b = 4
+#wifi_tx_gain_level_gn = 4
+
+##################################################
+# Import extenal configuration(UP to 64 groups)
+# example:
+#    register = CE010010:91919191
+#    register = 00CC0010:00091919
+##################################################
+
+##################################################
+# The AP RSSI signal is less than -88dbm complement signal to -88dbm
+##################################################
+#beacon_rssi_minimal = 88
\ No newline at end of file
diff --git a/drivers/net/wireless/ssv6x5x/platforms/xm-hi3518.cfg b/drivers/net/wireless/ssv6x5x/platforms/xm-hi3518.cfg
new file mode 100755
index 000000000..981cee8cd
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/platforms/xm-hi3518.cfg
@@ -0,0 +1,24 @@
+############################################################
+# XiongMai Hi3518
+############################################################
+ccflags-y += -DCONFIG_SSV_BUILD_AS_ONE_KO
+#ccflags-y += -DCONFIG_SSV_SUPPORT_AES_ASM
+ccflags-y += -DCONFIG_FW_ALIGNMENT_CHECK
+ccflags-y += -DCONFIG_PLATFORM_SDIO_OUTPUT_TIMING=3
+ccflags-y += -DCONFIG_PLATFORM_SDIO_BLOCK_SIZE=128
+ccflags-y += -DCONFIG_SSV_SMARTLINK
+#ccflags-y += -DMULTI_THREAD_ENCRYPT
+#ccflags-y += -DKTHREAD_BIND
+#ccflags-y += -DCONFIG_SSV_RSSI
+
+############################################################
+# Compiler path
+############################################################
+#SSV_CROSS = arm-hisiv100nptl-linux-
+SSV_CROSS = arm-hisiv300-linux-
+#SSV_KERNEL_PATH = /data/project/XiongMai/Hi3518_SDK_V1.0.9.0/osdrv/kernel/linux-3.0.y/
+SSV_KERNEL_PATH = /data/project/XiongMai/18EV200/Hi3518E_SDK_V1.0.2.0/osdrv/opensource/kernel/linux-3.4.y/
+SSV_ARCH = arm
+#SSV_STRIP = arm-hisiv100nptl-linux-strip
+SSV_STRIP = arm-hisiv300-linux-strip
+KMODDESTDIR = $(MODDESTDIR)
diff --git a/drivers/net/wireless/ssv6x5x/remove_old_driver.sh b/drivers/net/wireless/ssv6x5x/remove_old_driver.sh
new file mode 100755
index 000000000..373ce3da1
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/remove_old_driver.sh
@@ -0,0 +1,5 @@
+#/bin/bash
+
+KVERSION=$(uname -r)
+rm -fr /lib/modules/$KVERSION/kernel/drivers/net/wireless/ssv/
+rm -fr /lib/modules/$KVERSION/kernel/drivers/net/wireless/ssv6200/
diff --git a/drivers/net/wireless/ssv6x5x/rules.mak b/drivers/net/wireless/ssv6x5x/rules.mak
new file mode 100755
index 000000000..716cda648
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/rules.mak
@@ -0,0 +1,19 @@
+
+
+$(KMODULE_NAME)-y += $(KERN_SRCS:.c=.o)
+obj-$(CONFIG_SSV6X5X) += $(KMODULE_NAME).o
+
+
+.PHONY: all clean install
+
+all:
+	@$(MAKE) -C /lib/modules/$(KVERSION)/build \
+		SUBDIRS=$(KBUILD_DIR) CONFIG_DEBUG_SECTION_MISMATCH=y \
+		modules
+
+clean:
+	@$(MAKE) -C /lib/modules/$(KVERSION)/build SUBDIRS=$(KBUILD_DIR) clean
+
+install:
+	@$(MAKE) INSTALL_MOD_DIR=$(DRVPATH) -C /lib/modules/$(KVERSION)/build \
+	        M=$(KBUILD_DIR) modules_install
diff --git a/drivers/net/wireless/ssv6x5x/script/ap-aes.sh b/drivers/net/wireless/ssv6x5x/script/ap-aes.sh
new file mode 100755
index 000000000..9c0c05c4b
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/ap-aes.sh
@@ -0,0 +1,52 @@
+#!/bin/bash
+# ------------------------------
+
+# Clean up first.
+./unload_ap.sh
+./unload.sh
+./clean_log.sh
+
+# Load driver for AP mode.
+./ap.sh
+
+sleep 2
+
+# Check interface
+if [[ _$1 = _wlan* ]]; then
+    SSV_WLAN=$1
+else
+    SSV_WLAN=`./find_ssv_wlan`
+
+    if     [[ _$SSV_WLAN != _wlan* ]]; then
+        echo "No SSV WLAN device found."
+        exit 1;
+    fi
+fi
+echo SSV device for AP mode is $SSV_WLAN
+
+# Stop network manager from handling WiFi
+nmcli nm wifi off
+sudo rfkill unblock wlan
+
+# Configure
+ifconfig $SSV_WLAN 192.168.33.1 netmask 255.255.255.0
+cp dhcpd.conf /tmp/dhcpd_$SSV_WLAN.conf
+dhcpd -cf /tmp/dhcpd_$SSV_WLAN.conf -pf /var/run/dhcp-server/dhcpd.pid $SSV_WLAN
+bash -c "echo 1 >/proc/sys/net/ipv4/ip_forward" 
+iptables -t nat -A POSTROUTING -o eth0 -j MASQUERADE
+ap_name=`./get_mac $SSV_WLAN | cut -d ':' -f 3,4,5 | sed -e s/://g`
+ap_name=AP_$ap_name
+cat hostapd.conf.AES.template | sed -s s/HOSTAPD_IF/$SSV_WLAN/g | sed -s s/TestAP/$ap_name/g > hostapd.conf
+
+trap handle_stop INT
+
+function handle_stop() {
+    nmcli nm wifi on
+
+    ./unload_ap.sh
+    ./unload.sh
+    
+    echo AP mode stopped
+}
+        
+/usr/sbin/hostapd hostapd.conf
diff --git a/drivers/net/wireless/ssv6x5x/script/ap-no_sec.sh b/drivers/net/wireless/ssv6x5x/script/ap-no_sec.sh
new file mode 100755
index 000000000..062306a7d
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/ap-no_sec.sh
@@ -0,0 +1,25 @@
+#!/bin/bash
+# ------------------------------
+SSV_WLAN=`./find_ssv_wlan`
+
+if [[ _$SSV_WLAN != _wlan* ]]; then
+    echo "No SSV WLAN device found."
+    exit 1;
+fi
+
+echo SSV device is $SSV_WLAN
+
+nmcli nm wifi off
+sudo rfkill unblock wlan
+
+./unload_ap.sh
+ 
+ifconfig $SSV_WLAN 192.168.33.1 netmask 255.255.255.0
+dhcpd -c dhcpd.cfg -pf /var/run/dhcp-server/dhcpd.pid $SSV_WLAN
+bash -c "echo 1 >/proc/sys/net/ipv4/ip_forward" 
+iptables -t nat -A POSTROUTING -o eth0 -j MASQUERADE
+cat hostapd.conf.NO_SEC.template | sed -s s/HOSTAPD_IF/$SSV_WLAN/g  > hostapd.conf
+hostapd hostapd.conf
+
+nmcli nm wifi on
+# ------------------------------------
diff --git a/drivers/net/wireless/ssv6x5x/script/ap-tkip.sh b/drivers/net/wireless/ssv6x5x/script/ap-tkip.sh
new file mode 100755
index 000000000..de33e7a37
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/ap-tkip.sh
@@ -0,0 +1,50 @@
+#!/bin/bash
+# ------------------------------
+
+# Clean up first.
+./unload_ap.sh
+./unload.sh
+./clean_log.sh
+
+# Load driver for AP mode.
+./ap.sh
+
+sleep 2
+
+# Check interface
+if [[ _$1 = _wlan* ]]; then
+    SSV_WLAN=$1
+else
+    SSV_WLAN=`./find_ssv_wlan`
+
+    if     [[ _$SSV_WLAN != _wlan* ]]; then
+        echo "No SSV WLAN device found."
+        exit 1;
+    fi
+fi
+echo SSV device for AP mode is $SSV_WLAN
+
+# Stop network manager from handling WiFi
+nmcli nm wifi off
+sudo rfkill unblock wlan
+
+# Configure
+ifconfig $SSV_WLAN 192.168.33.1 netmask 255.255.255.0
+cp dhcpd.conf /tmp/dhcpd_$SSV_WLAN.conf
+dhcpd -cf /tmp/dhcpd_$SSV_WLAN.conf -pf /var/run/dhcp-server/dhcpd.pid $SSV_WLAN
+bash -c "echo 1 >/proc/sys/net/ipv4/ip_forward" 
+iptables -t nat -A POSTROUTING -o eth0 -j MASQUERADE
+cat hostapd.conf.TKIP.template | sed -s s/HOSTAPD_IF/$SSV_WLAN/g  > hostapd.conf
+
+trap handle_stop INT
+
+function handle_stop() {
+    nmcli nm wifi on
+
+    ./unload_ap.sh
+    ./unload.sh
+    
+    echo AP mode stopped
+}
+        
+hostapd hostapd.conf
diff --git a/drivers/net/wireless/ssv6x5x/script/ap.sh b/drivers/net/wireless/ssv6x5x/script/ap.sh
new file mode 100755
index 000000000..fef243e6d
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/ap.sh
@@ -0,0 +1,41 @@
+#!/bin/bash
+
+echo "=================================================="
+echo "1.Copy firmware"
+echo "=================================================="
+cp ../image/* /lib/firmware/
+
+echo "=================================================="
+echo "1.Unload Module"
+echo "=================================================="
+./unload.sh
+
+echo "=================================================="
+echo "2.Set Hardware Capability"
+echo "=================================================="
+
+eth0_local_mac=`ifconfig eth0  | grep HWaddr | sed -e 's/.*HWaddr //g' | sed -e 's/ //g' | cut -d ':' -f 4,5,6`
+[ "$eth0_local_mac" == "" ] && eth0_local_mac="45:67:89"
+local_mac=00:aa:bb:$eth0_local_mac
+local_mac_2=00:00:00:00:00:00
+echo WLAN MAC is $local_mac
+
+cat sta.cfg.template | sed -e "s/MAC_ADDR/$local_mac/g" | sed -e "s/MAC2ADDR/$local_mac_2/g" > sta_local_mac.cfg
+./ssvcfg.sh sta_local_mac.cfg
+
+echo "=================================================="
+echo "3.Load MMC Module"
+echo "=================================================="
+modprobe mmc_core sdiomaxclock=25000000
+modprobe sdhci
+modprobe sdhci-pci
+modprobe mmc_block
+
+echo "=================================================="
+echo "4.Load SSV6200 Driver"
+echo "=================================================="
+echo 6 > /proc/sys/kernel/printk
+
+modprobe ssv6200_sdio
+modprobe ssv6200_usb
+
diff --git a/drivers/net/wireless/ssv6x5x/script/ap2-aes.sh b/drivers/net/wireless/ssv6x5x/script/ap2-aes.sh
new file mode 100755
index 000000000..9aed19fe8
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/ap2-aes.sh
@@ -0,0 +1,32 @@
+#!/bin/bash
+# ------------------------------
+
+if [[ _$1 = _wlan* ]]; then
+    SSV_WLAN=$1
+else
+    SSV_WLAN=`./find_ssv_wlan`
+
+    if     [[ _$SSV_WLAN != _wlan* ]]; then
+        echo "No SSV WLAN device found."
+        exit 1;
+    fi
+fi
+echo SSV device for AP mode is $SSV_WLAN
+
+#nmcli nm wifi off
+#sudo rfkill unblock wlan
+
+./unload_ap.sh
+ 
+ifconfig $SSV_WLAN 192.168.33.1 netmask 255.255.255.0
+cp dhcpd.conf /tmp/dhcpd_$SSV_WLAN.conf
+dhcpd -cf /tmp/dhcpd_$SSV_WLAN.conf -pf /var/run/dhcp-server/dhcpd.pid $SSV_WLAN
+bash -c "echo 1 >/proc/sys/net/ipv4/ip_forward" 
+iptables -t nat -A POSTROUTING -o eth0 -j MASQUERADE
+cat hostapd.conf.AES.template | sed -s s/HOSTAPD_IF/$SSV_WLAN/g  > hostapd.conf
+hostapd hostapd.conf
+
+#nmcli nm wifi on
+
+echo AP mode stopped
+# ------------------------------------
diff --git a/drivers/net/wireless/ssv6x5x/script/ap_sta.sh b/drivers/net/wireless/ssv6x5x/script/ap_sta.sh
new file mode 100755
index 000000000..10b0691cf
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/ap_sta.sh
@@ -0,0 +1,22 @@
+#!/bin/bash
+#nmcli nm wifi off
+#sudo rfkill unblock wlan
+
+./unload_ap.sh
+
+ifconfig $1 192.168.33.1 netmask 255.255.255.0
+cp dhcpd.conf /tmp/dhcpd_$1.conf
+dhcpd -cf /tmp/dhcpd_$1.conf -pf /var/run/dhcp-server/dhcpd.pid $1
+bash -c "echo 1 >/proc/sys/net/ipv4/ip_forward" 
+iptables -t nat -A POSTROUTING -o $2 -j MASQUERADE
+if [ $# > 3 ]; then
+    echo 3:$3
+    cat hostapd.conf.AES.template | sed -s s/HOSTAPD_IF/$1/g  | sed -s s/TestAP/$3/g > hostapd.conf;
+else
+    cat hostapd.conf.AES.template | sed -s s/HOSTAPD_IF/$1/g  > hostapd.conf;
+fi
+#hostapd -e hostapd.entropy hostapd.conf
+hostapd hostapd.conf
+
+#nmcli nm wifi on
+# ------------------------------------
diff --git a/drivers/net/wireless/ssv6x5x/script/check_con_ap.sh b/drivers/net/wireless/ssv6x5x/script/check_con_ap.sh
new file mode 100755
index 000000000..257893189
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/check_con_ap.sh
@@ -0,0 +1,55 @@
+#/bin/bash
+#load/unload driver
+
+count=0
+
+S=1
+while [ "$S" == "1" ]
+do
+	  count=$[ count + 1 ]
+    sleep 3
+    dmesg -c
+    ./unload.sh
+    ./load.sh
+    sleep 3
+    ./cli mib reset
+    ./cli mib ampdurx
+    ./cli hci rxq show
+    sleep 60    
+    gotIp=$(ifconfig | grep "inet addr:192.168.2.22")
+    if [ "$gotIp" == "" ]; then
+  		echo -n "[$count]timeout..."
+  		addr=$(dmesg | grep "30 49 3b 01 3f c0")
+    	if [ "$addr" == "" ]; then	
+  			echo "no rx beacon..."
+		    ./cli mib ampdurx
+		    ./cli hci rxq show
+				./unload.sh
+  			break
+  		else
+  			echo "got rx beacon..."
+  			./cli mib ampdurx
+  			./cli hci rxq show
+  			sleep 2
+  		fi
+		else
+		
+			addr=$(dmesg | grep "30 49 3b 01 3f c0")
+    	if [ "$addr" == "" ]; then	
+  			echo "[$count] connet to ap... no rx beacon..."
+  		       ./cli mib ampdurx
+  		       ./cli hci rxq show
+             ./unload.sh
+                        
+  			break
+  		else
+  			echo "[$count]connet to ap... got rx beacon..." 
+  			./cli mib ampdurx
+  			./cli hci rxq show
+  			sleep 2 		
+  		fi
+			 
+    fi
+    
+done
+
diff --git a/drivers/net/wireless/ssv6x5x/script/clean_log.sh b/drivers/net/wireless/ssv6x5x/script/clean_log.sh
new file mode 100755
index 000000000..2a9320ba3
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/clean_log.sh
@@ -0,0 +1,4 @@
+#/bin/bash
+dmesg -C
+rm -fr /var/log/*
+service rsyslog restart
diff --git a/drivers/net/wireless/ssv6x5x/script/cli b/drivers/net/wireless/ssv6x5x/script/cli
new file mode 100755
index 000000000..6ce93640a
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/cli
@@ -0,0 +1,40 @@
+#!/bin/bash
+key_word="SSV|RSV"
+
+ssv_phy=""
+if [[ ${1} =~ "wlan" ]]; then
+	wlan_dirs=/sys/class/net/${1}/device/ieee80211/
+	if [ ! -e ${wlan_dirs} ]; then
+		echo "Could not find the ${1}."
+		exit 1;
+	fi
+	# shift wlanX
+	shift 1
+	ssv_phy=`ls ${wlan_dirs}`
+else
+	phy_dirs="/sys/class/ieee80211/*"
+
+	for phy_dir in $phy_dirs; do
+		if [ ! -d ${phy_dir}/device/driver ]; then
+			exit 1;
+		fi
+		drv_name=`ls ${phy_dir}/device/driver | grep -E $key_word`
+    	if [ ${drv_name} ]; then
+    		ssv_phy=`basename $phy_dir`;
+    		break;
+    	fi
+	done
+fi
+
+
+# excute CLI
+if [ ${ssv_phy} ]; then
+	SSV_CMD_FILE=/proc/ssv/${ssv_phy}/ssv_cmd
+	if [ -f $SSV_CMD_FILE ]; then
+		echo "$*" > $SSV_CMD_FILE
+		cat $SSV_CMD_FILE
+	fi
+else 
+	echo "./cli [wlanX] [CMD]"
+fi
+
diff --git a/drivers/net/wireless/ssv6x5x/script/cpu b/drivers/net/wireless/ssv6x5x/script/cpu
new file mode 100755
index 000000000..1a17e942d
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/cpu
@@ -0,0 +1,13 @@
+#!/bin/sh
+pid_list="`pgrep -d , ssv `,`pgrep -d , sdio`"
+cpu_list=/sys/devices/system/cpu/cpu?
+while [ true ] 
+    do 
+        #clear
+        echo "============================================================================"
+        top -b -n 1 -p $pid_list
+        for cpu in $cpu_list; do 
+	    echo "`basename $cpu` `cat $cpu/cpufreq/cpuinfo_cur_freq`"; 
+        done
+        #sleep 0.1
+    done
diff --git a/drivers/net/wireless/ssv6x5x/script/dhcpd.conf b/drivers/net/wireless/ssv6x5x/script/dhcpd.conf
new file mode 100755
index 000000000..46a186058
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/dhcpd.conf
@@ -0,0 +1,116 @@
+#
+# Sample configuration file for ISC dhcpd for Debian
+#
+# Attention: If /etc/ltsp/dhcpd.conf exists, that will be used as
+# configuration file instead of this file.
+#
+#
+
+# The ddns-updates-style parameter controls whether or not the server will
+# attempt to do a DNS update when a lease is confirmed. We default to the
+# behavior of the version 2 packages ('none', since DHCP v2 didn't
+# have support for DDNS.)
+ddns-update-style none;
+
+# option definitions common to all supported networks...
+option domain-name "example.org";
+option domain-name-servers ns1.example.org, ns2.example.org;
+
+default-lease-time 600;
+max-lease-time 7200;
+
+# If this DHCP server is the official DHCP server for the local
+# network, the authoritative directive should be uncommented.
+#authoritative;
+
+# Use this to send dhcp log messages to a different log file (you also
+# have to hack syslog.conf to complete the redirection).
+log-facility local7;
+
+# No service will be given on this subnet, but declaring it helps the 
+# DHCP server to understand the network topology.
+
+#subnet 10.152.187.0 netmask 255.255.255.0 {
+#}
+
+# This is a very basic subnet declaration.
+
+#subnet 10.254.239.0 netmask 255.255.255.224 {
+#  range 10.254.239.10 10.254.239.20;
+#  option routers rtr-239-0-1.example.org, rtr-239-0-2.example.org;
+#}
+
+# This declaration allows BOOTP clients to get dynamic addresses,
+# which we don't really recommend.
+
+#subnet 10.254.239.32 netmask 255.255.255.224 {
+#  range dynamic-bootp 10.254.239.40 10.254.239.60;
+#  option broadcast-address 10.254.239.31;
+#  option routers rtr-239-32-1.example.org;
+#}
+
+# A slightly different configuration for an internal subnet.
+#subnet 10.5.5.0 netmask 255.255.255.224 {
+#  range 10.5.5.26 10.5.5.30;
+#  option domain-name-servers ns1.internal.example.org;
+#  option domain-name "internal.example.org";
+#  option routers 10.5.5.1;
+#  option broadcast-address 10.5.5.31;
+#  default-lease-time 600;
+#  max-lease-time 7200;
+#}
+
+# Hosts which require special configuration options can be listed in
+# host statements.   If no address is specified, the address will be
+# allocated dynamically (if possible), but the host-specific information
+# will still come from the host declaration.
+
+#host passacaglia {
+#  hardware ethernet 0:0:c0:5d:bd:95;
+#  filename "vmunix.passacaglia";
+#  server-name "toccata.fugue.com";
+#}
+
+# Fixed IP addresses can also be specified for hosts.   These addresses
+# should not also be listed as being available for dynamic assignment.
+# Hosts for which fixed IP addresses have been specified can boot using
+# BOOTP or DHCP.   Hosts for which no fixed address is specified can only
+# be booted with DHCP, unless there is an address range on the subnet
+# to which a BOOTP client is connected which has the dynamic-bootp flag
+# set.
+#host fantasia {
+#  hardware ethernet 08:00:07:26:c0:a5;
+#  fixed-address fantasia.fugue.com;
+#}
+
+# You can declare a class of clients and then do address allocation
+# based on that.   The example below shows a case where all clients
+# in a certain class get addresses on the 10.17.224/24 subnet, and all
+# other clients get addresses on the 10.0.29/24 subnet.
+
+#class "foo" {
+#  match if substring (option vendor-class-identifier, 0, 4) = "SUNW";
+#}
+
+#shared-network 224-29 {
+#  subnet 10.17.224.0 netmask 255.255.255.0 {
+#    option routers rtr-224.example.org;
+#  }
+#  subnet 10.0.29.0 netmask 255.255.255.0 {
+#    option routers rtr-29.example.org;
+#  }
+#  pool {
+#    allow members of "foo";
+#    range 10.17.224.10 10.17.224.250;
+#  }
+#  pool {
+#    deny members of "foo";
+#    range 10.0.29.10 10.0.29.230;
+#  }
+#}
+
+subnet 192.168.33.0 netmask 255.255.255.0 {
+    range 192.168.33.100 192.168.33.110;
+    option routers 192.168.33.1;
+    option domain-name-servers 168.95.1.1;
+}
diff --git a/drivers/net/wireless/ssv6x5x/script/find_ssv_phy b/drivers/net/wireless/ssv6x5x/script/find_ssv_phy
new file mode 100755
index 000000000..33329edbf
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/find_ssv_phy
@@ -0,0 +1,11 @@
+#!/bin/sh
+phy_dirs="/sys/class/ieee80211/*"
+key_word="SSV|RSV"
+
+for phy_dir in $phy_dirs; do
+	drv_name=`ls ${phy_dir}/device/driver | grep -E $key_word`
+    if [ ${drv_name} ]; then
+    	echo `basename $phy_dir`;
+    	break;
+    fi
+done
diff --git a/drivers/net/wireless/ssv6x5x/script/find_ssv_wlan b/drivers/net/wireless/ssv6x5x/script/find_ssv_wlan
new file mode 100755
index 000000000..2fd551db1
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/find_ssv_wlan
@@ -0,0 +1,22 @@
+#!/bin/sh
+net_dirs="/sys/class/net/*"
+key_word="SSV|RSV"
+found=0
+for net_dir in $net_dirs; do
+	drv_dir="${net_dir}/phy80211/device/driver"
+	if [ ! -e ${drv_dir} ] ; then
+		continue;
+	fi
+	drv_name=`ls ${drv_dir} | grep -E $key_word`
+    if [ ${drv_name} ]; then
+    	echo `basename ${net_dir}`;
+    	found=`expr $found + 1`
+    	#break;
+    fi
+done
+
+if [ $found -gt 0 ]; then 
+    exit 0
+else
+    exit 1
+fi
diff --git a/drivers/net/wireless/ssv6x5x/script/genconf.sh b/drivers/net/wireless/ssv6x5x/script/genconf.sh
new file mode 100755
index 000000000..47d65e5ce
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/genconf.sh
@@ -0,0 +1,18 @@
+#!/bin/bash
+# Script to convert defines in compiler option in to C's defines
+# Should be executed in make file and it take ccflags-y as the
+# compiler options. The content will be redirected to the first arguement.
+
+echo "#ifndef __SSV_MOD_CONF_H__" > $1
+echo "#define __SSV_MOD_CONF_H__" >> $1
+
+for flag in ${ccflags-y}; do
+	if [[ "$flag" =~ ^-D.* ]]; then
+		#def=${flag//-D/}
+		def=${flag:2}
+		echo "#ifndef $def" >> $1
+		echo "#define $def" >> $1
+		echo "#endif" >> $1
+	fi
+done
+echo "#endif // __SSV_MOD_CONF_H__" >> $1
diff --git a/drivers/net/wireless/ssv6x5x/script/get_mac b/drivers/net/wireless/ssv6x5x/script/get_mac
new file mode 100755
index 000000000..fb14e4e01
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/get_mac
@@ -0,0 +1,10 @@
+#!/bin/sh
+if [ $# != 1 ]; then
+    interface=eth0
+else
+    interface=$1
+fi
+
+mac=`ifconfig $interface | grep HWaddr | sed -e 's/.*HWaddr //g' | sed -e 's/ //g'`
+
+echo $mac
diff --git a/drivers/net/wireless/ssv6x5x/script/gpio_reset.sh b/drivers/net/wireless/ssv6x5x/script/gpio_reset.sh
new file mode 100755
index 000000000..7371204f3
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/gpio_reset.sh
@@ -0,0 +1,58 @@
+#!/bin/bash
+USB_PORT=
+[[ $# -lt 1 || ( $1 != "on" && $1 != "off" ) ]] && echo "Usage: gpio_reset_on.sh on|off [FTDI_TTY_PORT]" && exit 1
+
+reset_enable=$1
+
+# If $2 is given, use it as the GPIO control port or use the one of the largest port ID.
+if [ $# == 1 ]; then
+    port_id=0
+    if [ -d "/sys/module/ftdi_sio/drivers/usb-serial:ftdi_sio" ]; then
+        for tty_port in /sys/module/ftdi_sio/drivers/usb-serial\:ftdi_sio/ttyUSB* ; do
+            id=`echo $tty_port | sed -e s/.*ttyUSB//`
+            [ $id -gt $port_id ] && port_id=$id
+        done
+    fi
+    USB_PORT=ttyUSB${port_id}
+    echo Using ${USB_PORT} as the control GPIO port
+else
+    USB_PORT=$2
+fi
+
+# Check if GPIO function is enabled in kernel FTDI serial driver.
+if [ ! -d "/sys/module/ftdi_sio/drivers/usb-serial:ftdi_sio/${USB_PORT}" -o ! -d "/sys/class/tty/${USB_PORT}" ]; then
+    echo "No GPIO support for ${USB_PORT}."
+    exit 1 
+fi
+
+# Find out the last GPIO # of this port
+gpio_id=0
+for gpio_chip in /sys/class/tty/${USB_PORT}/device/gpio/gpiochip*; do
+    gpio_id=`echo ${gpio_chip} | sed -e s/^.*gpiochip//`
+    gpio_id=`expr $gpio_id + 7`
+done
+
+# Make this GPIO port available
+gpio=/sys/class/gpio/gpio${gpio_id}
+if [ ! -d ${gpio} ]; then
+    echo Creating GPIO $gpio_id...
+    echo $gpio_id > /sys/class/gpio/export
+fi
+
+if [ -d ${gpio} ]; then
+    echo Using GPIO ${gpio} to control WiFi Reset.
+    dir=`cat ${gpio}/direction`
+    if [ $dir == in ]; then
+        echo "out" > ${gpio}/direction
+    fi
+    if [ $reset_enable == "on" ]; then
+        echo 0 > ${gpio}/value
+    else
+        echo 1 > ${gpio}/value
+    fi
+else
+    echo "Failed to enable GPIO to control WiFi."
+    exit 1
+fi
+
+exit 0
diff --git a/drivers/net/wireless/ssv6x5x/script/hci_mib b/drivers/net/wireless/ssv6x5x/script/hci_mib
new file mode 100755
index 000000000..ab84ffc1a
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/hci_mib
@@ -0,0 +1,37 @@
+#!/bin/sh
+key_word="SSV|RSV"
+
+if [ $# -lt 1 ]; then
+	echo "Usage: hci_mib PHY_IF $#";
+	exit;
+fi
+
+phy_dir="/sys/class/ieee80211/$1/device/driver"
+drv_name=`ls ${phy_dir} | grep -E $key_word`
+if [ -z ${drv_name} ]; then
+	echo "Cannot find SSV driver"
+    exit;
+fi
+
+phy_if=/sys/kernel/debug/ieee80211/$1/${drv_name}/hci
+if [ ! -d $phy_if ]; then 
+    echo "$phy_if does not exist.";
+    exit;
+fi
+
+cd $phy_if
+
+echo 0 > hci_isr_mib_enable
+echo 1 > hci_isr_mib_reset
+echo 1 > hci_isr_mib_enable
+
+sleep 10
+
+echo 0 > hci_isr_mib_enable
+
+echo "ISR total time: `cat isr_total_time`"
+echo "RX IO time: `cat rx_io_time`"
+echo "RX IO count: `cat rx_io_count`"
+echo "RX process time: `cat rx_proc_time`"
+echo "TX IO time: `cat tx_io_time`"
+echo "TX IO count: `cat tx_io_count`"
diff --git a/drivers/net/wireless/ssv6x5x/script/hostapd.conf.AES.template b/drivers/net/wireless/ssv6x5x/script/hostapd.conf.AES.template
new file mode 100755
index 000000000..e063c4ed3
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/hostapd.conf.AES.template
@@ -0,0 +1,1664 @@
+##### hostapd configuration file ##############################################
+# Empty lines and lines starting with # are ignored
+
+# AP netdevice name (without 'ap' postfix, i.e., wlan0 uses wlan0ap for
+# management frames); ath0 for madwifi
+interface=HOSTAPD_IF
+
+# In case of madwifi, atheros, and nl80211 driver interfaces, an additional
+# configuration parameter, bridge, may be used to notify hostapd if the
+# interface is included in a bridge. This parameter is not used with Host AP
+# driver. If the bridge parameter is not set, the drivers will automatically
+# figure out the bridge interface (assuming sysfs is enabled and mounted to
+# /sys) and this parameter may not be needed.
+#
+# For nl80211, this parameter can be used to request the AP interface to be
+# added to the bridge automatically (brctl may refuse to do this before hostapd
+# has been started to change the interface mode). If needed, the bridge
+# interface is also created.
+#bridge=br0
+
+# Driver interface type (hostap/wired/madwifi/test/none/nl80211/bsd);
+# default: hostap). nl80211 is used with all Linux mac80211 drivers.
+# Use driver=none if building hostapd as a standalone RADIUS server that does
+# not control any wireless/wired driver.
+# driver=hostap
+
+# hostapd event logger configuration
+#
+# Two output method: syslog and stdout (only usable if not forking to
+# background).
+#
+# Module bitfield (ORed bitfield of modules that will be logged; -1 = all
+# modules):
+# bit 0 (1) = IEEE 802.11
+# bit 1 (2) = IEEE 802.1X
+# bit 2 (4) = RADIUS
+# bit 3 (8) = WPA
+# bit 4 (16) = driver interface
+# bit 5 (32) = IAPP
+# bit 6 (64) = MLME
+#
+# Levels (minimum value for logged events):
+#  0 = verbose debugging
+#  1 = debugging
+#  2 = informational messages
+#  3 = notification
+#  4 = warning
+#
+logger_syslog=1
+logger_syslog_level=0
+logger_stdout=1
+logger_stdout_level=0
+
+# Interface for separate control program. If this is specified, hostapd
+# will create this directory and a UNIX domain socket for listening to requests
+# from external programs (CLI/GUI, etc.) for status information and
+# configuration. The socket file will be named based on the interface name, so
+# multiple hostapd processes/interfaces can be run at the same time if more
+# than one interface is used.
+# /var/run/hostapd is the recommended directory for sockets and by default,
+# hostapd_cli will use it when trying to connect with hostapd.
+ctrl_interface=/var/run/hostapd
+
+# Access control for the control interface can be configured by setting the
+# directory to allow only members of a group to use sockets. This way, it is
+# possible to run hostapd as root (since it needs to change network
+# configuration and open raw sockets) and still allow GUI/CLI components to be
+# run as non-root users. However, since the control interface can be used to
+# change the network configuration, this access needs to be protected in many
+# cases. By default, hostapd is configured to use gid 0 (root). If you
+# want to allow non-root users to use the contron interface, add a new group
+# and change this value to match with that group. Add users that should have
+# control interface access to this group.
+#
+# This variable can be a group name or gid.
+#ctrl_interface_group=wheel
+ctrl_interface_group=0
+
+
+##### IEEE 802.11 related configuration #######################################
+
+# SSID to be used in IEEE 802.11 management frames
+ssid=TestAP_CCMP
+# Alternative formats for configuring SSID
+# (double quoted string, hexdump, printf-escaped string)
+#ssid2="test"
+#ssid2=74657374
+#ssid2=P"hello\nthere"
+
+# UTF-8 SSID: Whether the SSID is to be interpreted using UTF-8 encoding
+#utf8_ssid=1
+
+# Country code (ISO/IEC 3166-1). Used to set regulatory domain.
+# Set as needed to indicate country in which device is operating.
+# This can limit available channels and transmit power.
+#country_code=US
+
+# Enable IEEE 802.11d. This advertises the country_code and the set of allowed
+# channels and transmit power levels based on the regulatory limits. The
+# country_code setting must be configured with the correct country for
+# IEEE 802.11d functions.
+# (default: 0 = disabled)
+#ieee80211d=1
+
+# Enable IEEE 802.11h. This enables radar detection and DFS support if
+# available. DFS support is required on outdoor 5 GHz channels in most countries
+# of the world. This can be used only with ieee80211d=1.
+# (default: 0 = disabled)
+#ieee80211h=1
+
+# Operation mode (a = IEEE 802.11a, b = IEEE 802.11b, g = IEEE 802.11g,
+# ad = IEEE 802.11ad (60 GHz); a/g options are used with IEEE 802.11n, too, to
+# specify band)
+# Default: IEEE 802.11b
+hw_mode=g
+
+# Channel number (IEEE 802.11)
+# (default: 0, i.e., not set)
+# Please note that some drivers do not use this value from hostapd and the
+# channel will need to be configured separately with iwconfig.
+#
+# If CONFIG_ACS build option is enabled, the channel can be selected
+# automatically at run time by setting channel=acs_survey or channel=0, both of
+# which will enable the ACS survey based algorithm.
+channel=11
+
+# ACS tuning - Automatic Channel Selection
+# See: http://wireless.kernel.org/en/users/Documentation/acs
+#
+# You can customize the ACS survey algorithm with following variables:
+#
+# acs_num_scans requirement is 1..100 - number of scans to be performed that
+# are used to trigger survey data gathering of an underlying device driver.
+# Scans are passive and typically take a little over 100ms (depending on the
+# driver) on each available channel for given hw_mode. Increasing this value
+# means sacrificing startup time and gathering more data wrt channel
+# interference that may help choosing a better channel. This can also help fine
+# tune the ACS scan time in case a driver has different scan dwell times.
+#
+# Defaults:
+#acs_num_scans=5
+
+# Beacon interval in kus (1.024 ms) (default: 100; range 15..65535)
+beacon_int=100
+
+# DTIM (delivery traffic information message) period (range 1..255):
+# number of beacons between DTIMs (1 = every beacon includes DTIM element)
+# (default: 2)
+dtim_period=1
+
+# Maximum number of stations allowed in station table. New stations will be
+# rejected after the station table is full. IEEE 802.11 has a limit of 2007
+# different association IDs, so this number should not be larger than that.
+# (default: 2007)
+max_num_sta=255
+
+# RTS/CTS threshold; 2347 = disabled (default); range 0..2347
+# If this field is not included in hostapd.conf, hostapd will not control
+# RTS threshold and 'iwconfig wlan# rts <val>' can be used to set it.
+rts_threshold=2347
+
+# Fragmentation threshold; 2346 = disabled (default); range 256..2346
+# If this field is not included in hostapd.conf, hostapd will not control
+# fragmentation threshold and 'iwconfig wlan# frag <val>' can be used to set
+# it.
+fragm_threshold=2346
+
+# Rate configuration
+# Default is to enable all rates supported by the hardware. This configuration
+# item allows this list be filtered so that only the listed rates will be left
+# in the list. If the list is empty, all rates are used. This list can have
+# entries that are not in the list of rates the hardware supports (such entries
+# are ignored). The entries in this list are in 100 kbps, i.e., 11 Mbps = 110.
+# If this item is present, at least one rate have to be matching with the rates
+# hardware supports.
+# default: use the most common supported rate setting for the selected
+# hw_mode (i.e., this line can be removed from configuration file in most
+# cases)
+#supported_rates=10 20 55 110 60 90 120 180 240 360 480 540
+
+# Basic rate set configuration
+# List of rates (in 100 kbps) that are included in the basic rate set.
+# If this item is not included, usually reasonable default set is used.
+#basic_rates=10 20
+#basic_rates=10 20 55 110
+#basic_rates=60 120 240
+
+# Short Preamble
+# This parameter can be used to enable optional use of short preamble for
+# frames sent at 2 Mbps, 5.5 Mbps, and 11 Mbps to improve network performance.
+# This applies only to IEEE 802.11b-compatible networks and this should only be
+# enabled if the local hardware supports use of short preamble. If any of the
+# associated STAs do not support short preamble, use of short preamble will be
+# disabled (and enabled when such STAs disassociate) dynamically.
+# 0 = do not allow use of short preamble (default)
+# 1 = allow use of short preamble
+#preamble=1
+
+# Station MAC address -based authentication
+# Please note that this kind of access control requires a driver that uses
+# hostapd to take care of management frame processing and as such, this can be
+# used with driver=hostap or driver=nl80211, but not with driver=madwifi.
+# 0 = accept unless in deny list
+# 1 = deny unless in accept list
+# 2 = use external RADIUS server (accept/deny lists are searched first)
+macaddr_acl=0
+
+# Accept/deny lists are read from separate files (containing list of
+# MAC addresses, one per line). Use absolute path name to make sure that the
+# files can be read on SIGHUP configuration reloads.
+#accept_mac_file=/etc/hostapd.accept
+#deny_mac_file=/etc/hostapd.deny
+
+# IEEE 802.11 specifies two authentication algorithms. hostapd can be
+# configured to allow both of these or only one. Open system authentication
+# should be used with IEEE 802.1X.
+# Bit fields of allowed authentication algorithms:
+# bit 0 = Open System Authentication
+# bit 1 = Shared Key Authentication (requires WEP)
+auth_algs=3
+
+# Send empty SSID in beacons and ignore probe request frames that do not
+# specify full SSID, i.e., require stations to know SSID.
+# default: disabled (0)
+# 1 = send empty (length=0) SSID in beacon and ignore probe request for
+#     broadcast SSID
+# 2 = clear SSID (ASCII 0), but keep the original length (this may be required
+#     with some clients that do not support empty SSID) and ignore probe
+#     requests for broadcast SSID
+ignore_broadcast_ssid=0
+
+# Additional vendor specfic elements for Beacon and Probe Response frames
+# This parameter can be used to add additional vendor specific element(s) into
+# the end of the Beacon and Probe Response frames. The format for these
+# element(s) is a hexdump of the raw information elements (id+len+payload for
+# one or more elements)
+#vendor_elements=dd0411223301
+
+# TX queue parameters (EDCF / bursting)
+# tx_queue_<queue name>_<param>
+# queues: data0, data1, data2, data3, after_beacon, beacon
+#		(data0 is the highest priority queue)
+# parameters:
+#   aifs: AIFS (default 2)
+#   cwmin: cwMin (1, 3, 7, 15, 31, 63, 127, 255, 511, 1023)
+#   cwmax: cwMax (1, 3, 7, 15, 31, 63, 127, 255, 511, 1023); cwMax >= cwMin
+#   burst: maximum length (in milliseconds with precision of up to 0.1 ms) for
+#          bursting
+#
+# Default WMM parameters (IEEE 802.11 draft; 11-03-0504-03-000e):
+# These parameters are used by the access point when transmitting frames
+# to the clients.
+#
+# Low priority / AC_BK = background
+#tx_queue_data3_aifs=7
+#tx_queue_data3_cwmin=15
+#tx_queue_data3_cwmax=1023
+#tx_queue_data3_burst=0
+# Note: for IEEE 802.11b mode: cWmin=31 cWmax=1023 burst=0
+#
+# Normal priority / AC_BE = best effort
+#tx_queue_data2_aifs=3
+#tx_queue_data2_cwmin=15
+#tx_queue_data2_cwmax=63
+#tx_queue_data2_burst=0
+# Note: for IEEE 802.11b mode: cWmin=31 cWmax=127 burst=0
+#
+# High priority / AC_VI = video
+#tx_queue_data1_aifs=1
+#tx_queue_data1_cwmin=7
+#tx_queue_data1_cwmax=15
+#tx_queue_data1_burst=3.0
+# Note: for IEEE 802.11b mode: cWmin=15 cWmax=31 burst=6.0
+#
+# Highest priority / AC_VO = voice
+#tx_queue_data0_aifs=1
+#tx_queue_data0_cwmin=3
+#tx_queue_data0_cwmax=7
+#tx_queue_data0_burst=1.5
+# Note: for IEEE 802.11b mode: cWmin=7 cWmax=15 burst=3.3
+
+# 802.1D Tag (= UP) to AC mappings
+# WMM specifies following mapping of data frames to different ACs. This mapping
+# can be configured using Linux QoS/tc and sch_pktpri.o module.
+# 802.1D Tag	802.1D Designation	Access Category	WMM Designation
+# 1		BK			AC_BK		Background
+# 2		-			AC_BK		Background
+# 0		BE			AC_BE		Best Effort
+# 3		EE			AC_BE		Best Effort
+# 4		CL			AC_VI		Video
+# 5		VI			AC_VI		Video
+# 6		VO			AC_VO		Voice
+# 7		NC			AC_VO		Voice
+# Data frames with no priority information: AC_BE
+# Management frames: AC_VO
+# PS-Poll frames: AC_BE
+
+# Default WMM parameters (IEEE 802.11 draft; 11-03-0504-03-000e):
+# for 802.11a or 802.11g networks
+# These parameters are sent to WMM clients when they associate.
+# The parameters will be used by WMM clients for frames transmitted to the
+# access point.
+#
+# note - txop_limit is in units of 32microseconds
+# note - acm is admission control mandatory flag. 0 = admission control not
+# required, 1 = mandatory
+# note - here cwMin and cmMax are in exponent form. the actual cw value used
+# will be (2^n)-1 where n is the value given here
+#
+wmm_enabled=1
+#
+# WMM-PS Unscheduled Automatic Power Save Delivery [U-APSD]
+# Enable this flag if U-APSD supported outside hostapd (eg., Firmware/driver)
+#uapsd_advertisement_enabled=1
+#
+# Low priority / AC_BK = background
+wmm_ac_bk_cwmin=4
+wmm_ac_bk_cwmax=10
+wmm_ac_bk_aifs=7
+wmm_ac_bk_txop_limit=0
+wmm_ac_bk_acm=0
+# Note: for IEEE 802.11b mode: cWmin=5 cWmax=10
+#
+# Normal priority / AC_BE = best effort
+wmm_ac_be_aifs=3
+wmm_ac_be_cwmin=4
+wmm_ac_be_cwmax=10
+wmm_ac_be_txop_limit=0
+wmm_ac_be_acm=0
+# Note: for IEEE 802.11b mode: cWmin=5 cWmax=7
+#
+# High priority / AC_VI = video
+wmm_ac_vi_aifs=2
+wmm_ac_vi_cwmin=3
+wmm_ac_vi_cwmax=4
+wmm_ac_vi_txop_limit=94
+wmm_ac_vi_acm=0
+# Note: for IEEE 802.11b mode: cWmin=4 cWmax=5 txop_limit=188
+#
+# Highest priority / AC_VO = voice
+wmm_ac_vo_aifs=2
+wmm_ac_vo_cwmin=2
+wmm_ac_vo_cwmax=3
+wmm_ac_vo_txop_limit=47
+wmm_ac_vo_acm=0
+# Note: for IEEE 802.11b mode: cWmin=3 cWmax=4 burst=102
+
+# Static WEP key configuration
+#
+# The key number to use when transmitting.
+# It must be between 0 and 3, and the corresponding key must be set.
+# default: not set
+#wep_default_key=0
+# The WEP keys to use.
+# A key may be a quoted string or unquoted hexadecimal digits.
+# The key length should be 5, 13, or 16 characters, or 10, 26, or 32
+# digits, depending on whether 40-bit (64-bit), 104-bit (128-bit), or
+# 128-bit (152-bit) WEP is used.
+# Only the default key must be supplied; the others are optional.
+# default: not set
+#wep_key0=123456789a
+#wep_key1="vwxyz"
+#wep_key2=0102030405060708090a0b0c0d
+#wep_key3=".2.4.6.8.0.23"
+
+# Station inactivity limit
+#
+# If a station does not send anything in ap_max_inactivity seconds, an
+# empty data frame is sent to it in order to verify whether it is
+# still in range. If this frame is not ACKed, the station will be
+# disassociated and then deauthenticated. This feature is used to
+# clear station table of old entries when the STAs move out of the
+# range.
+#
+# The station can associate again with the AP if it is still in range;
+# this inactivity poll is just used as a nicer way of verifying
+# inactivity; i.e., client will not report broken connection because
+# disassociation frame is not sent immediately without first polling
+# the STA with a data frame.
+# default: 300 (i.e., 5 minutes)
+#ap_max_inactivity=300
+#
+# The inactivity polling can be disabled to disconnect stations based on
+# inactivity timeout so that idle stations are more likely to be disconnected
+# even if they are still in range of the AP. This can be done by setting
+# skip_inactivity_poll to 1 (default 0).
+#skip_inactivity_poll=0
+
+# Disassociate stations based on excessive transmission failures or other
+# indications of connection loss. This depends on the driver capabilities and
+# may not be available with all drivers.
+#disassoc_low_ack=1
+
+# Maximum allowed Listen Interval (how many Beacon periods STAs are allowed to
+# remain asleep). Default: 65535 (no limit apart from field size)
+#max_listen_interval=100
+
+# WDS (4-address frame) mode with per-station virtual interfaces
+# (only supported with driver=nl80211)
+# This mode allows associated stations to use 4-address frames to allow layer 2
+# bridging to be used.
+#wds_sta=1
+
+# If bridge parameter is set, the WDS STA interface will be added to the same
+# bridge by default. This can be overridden with the wds_bridge parameter to
+# use a separate bridge.
+#wds_bridge=wds-br0
+
+# Start the AP with beaconing disabled by default.
+#start_disabled=0
+
+# Client isolation can be used to prevent low-level bridging of frames between
+# associated stations in the BSS. By default, this bridging is allowed.
+#ap_isolate=1
+
+# Fixed BSS Load value for testing purposes
+# This field can be used to configure hostapd to add a fixed BSS Load element
+# into Beacon and Probe Response frames for testing purposes. The format is
+# <station count>:<channel utilization>:<available admission capacity>
+#bss_load_test=12:80:20000
+
+##### IEEE 802.11n related configuration ######################################
+
+# ieee80211n: Whether IEEE 802.11n (HT) is enabled
+# 0 = disabled (default)
+# 1 = enabled
+# Note: You will also need to enable WMM for full HT functionality.
+ieee80211n=1
+
+# ht_capab: HT capabilities (list of flags)
+# LDPC coding capability: [LDPC] = supported
+# Supported channel width set: [HT40-] = both 20 MHz and 40 MHz with secondary
+#	channel below the primary channel; [HT40+] = both 20 MHz and 40 MHz
+#	with secondary channel below the primary channel
+#	(20 MHz only if neither is set)
+#	Note: There are limits on which channels can be used with HT40- and
+#	HT40+. Following table shows the channels that may be available for
+#	HT40- and HT40+ use per IEEE 802.11n Annex J:
+#	freq		HT40-		HT40+
+#	2.4 GHz		5-13		1-7 (1-9 in Europe/Japan)
+#	5 GHz		40,48,56,64	36,44,52,60
+#	(depending on the location, not all of these channels may be available
+#	for use)
+#	Please note that 40 MHz channels may switch their primary and secondary
+#	channels if needed or creation of 40 MHz channel maybe rejected based
+#	on overlapping BSSes. These changes are done automatically when hostapd
+#	is setting up the 40 MHz channel.
+# Spatial Multiplexing (SM) Power Save: [SMPS-STATIC] or [SMPS-DYNAMIC]
+#	(SMPS disabled if neither is set)
+# HT-greenfield: [GF] (disabled if not set)
+# Short GI for 20 MHz: [SHORT-GI-20] (disabled if not set)
+# Short GI for 40 MHz: [SHORT-GI-40] (disabled if not set)
+# Tx STBC: [TX-STBC] (disabled if not set)
+# Rx STBC: [RX-STBC1] (one spatial stream), [RX-STBC12] (one or two spatial
+#	streams), or [RX-STBC123] (one, two, or three spatial streams); Rx STBC
+#	disabled if none of these set
+# HT-delayed Block Ack: [DELAYED-BA] (disabled if not set)
+# Maximum A-MSDU length: [MAX-AMSDU-7935] for 7935 octets (3839 octets if not
+#	set)
+# DSSS/CCK Mode in 40 MHz: [DSSS_CCK-40] = allowed (not allowed if not set)
+# PSMP support: [PSMP] (disabled if not set)
+# L-SIG TXOP protection support: [LSIG-TXOP-PROT] (disabled if not set)
+#ht_capab=[HT40-][SHORT-GI-20][SHORT-GI-40]
+ht_capab=[SHORT-GI-20]
+
+# Require stations to support HT PHY (reject association if they do not)
+#require_ht=1
+
+# If set non-zero, require stations to perform scans of overlapping
+# channels to test for stations which would be affected by 40 MHz traffic.
+# This parameter sets the interval in seconds between these scans. This
+# is useful only for testing that stations properly set the OBSS interval,
+# since the other parameters in the OBSS scan parameters IE are set to 0.
+#obss_interval=0
+
+##### IEEE 802.11ac related configuration #####################################
+
+# ieee80211ac: Whether IEEE 802.11ac (VHT) is enabled
+# 0 = disabled (default)
+# 1 = enabled
+# Note: You will also need to enable WMM for full VHT functionality.
+#ieee80211ac=1
+
+# vht_capab: VHT capabilities (list of flags)
+#
+# vht_max_mpdu_len: [MAX-MPDU-7991] [MAX-MPDU-11454]
+# Indicates maximum MPDU length
+# 0 = 3895 octets (default)
+# 1 = 7991 octets
+# 2 = 11454 octets
+# 3 = reserved
+#
+# supported_chan_width: [VHT160] [VHT160-80PLUS80]
+# Indicates supported Channel widths
+# 0 = 160 MHz & 80+80 channel widths are not supported (default)
+# 1 = 160 MHz channel width is supported
+# 2 = 160 MHz & 80+80 channel widths are supported
+# 3 = reserved
+#
+# Rx LDPC coding capability: [RXLDPC]
+# Indicates support for receiving LDPC coded pkts
+# 0 = Not supported (default)
+# 1 = Supported
+#
+# Short GI for 80 MHz: [SHORT-GI-80]
+# Indicates short GI support for reception of packets transmitted with TXVECTOR
+# params format equal to VHT and CBW = 80Mhz
+# 0 = Not supported (default)
+# 1 = Supported
+#
+# Short GI for 160 MHz: [SHORT-GI-160]
+# Indicates short GI support for reception of packets transmitted with TXVECTOR
+# params format equal to VHT and CBW = 160Mhz
+# 0 = Not supported (default)
+# 1 = Supported
+#
+# Tx STBC: [TX-STBC-2BY1]
+# Indicates support for the transmission of at least 2x1 STBC
+# 0 = Not supported (default)
+# 1 = Supported
+#
+# Rx STBC: [RX-STBC-1] [RX-STBC-12] [RX-STBC-123] [RX-STBC-1234]
+# Indicates support for the reception of PPDUs using STBC
+# 0 = Not supported (default)
+# 1 = support of one spatial stream
+# 2 = support of one and two spatial streams
+# 3 = support of one, two and three spatial streams
+# 4 = support of one, two, three and four spatial streams
+# 5,6,7 = reserved
+#
+# SU Beamformer Capable: [SU-BEAMFORMER]
+# Indicates support for operation as a single user beamformer
+# 0 = Not supported (default)
+# 1 = Supported
+#
+# SU Beamformee Capable: [SU-BEAMFORMEE]
+# Indicates support for operation as a single user beamformee
+# 0 = Not supported (default)
+# 1 = Supported
+#
+# Compressed Steering Number of Beamformer Antennas Supported: [BF-ANTENNA-2]
+#   Beamformee's capability indicating the maximum number of beamformer
+#   antennas the beamformee can support when sending compressed beamforming
+#   feedback
+# If SU beamformer capable, set to maximum value minus 1
+# else reserved (default)
+#
+# Number of Sounding Dimensions: [SOUNDING-DIMENSION-2]
+# Beamformer's capability indicating the maximum value of the NUM_STS parameter
+# in the TXVECTOR of a VHT NDP
+# If SU beamformer capable, set to maximum value minus 1
+# else reserved (default)
+#
+# MU Beamformer Capable: [MU-BEAMFORMER]
+# Indicates support for operation as an MU beamformer
+# 0 = Not supported or sent by Non-AP STA (default)
+# 1 = Supported
+#
+# MU Beamformee Capable: [MU-BEAMFORMEE]
+# Indicates support for operation as an MU beamformee
+# 0 = Not supported or sent by AP (default)
+# 1 = Supported
+#
+# VHT TXOP PS: [VHT-TXOP-PS]
+# Indicates whether or not the AP supports VHT TXOP Power Save Mode
+#  or whether or not the STA is in VHT TXOP Power Save mode
+# 0 = VHT AP doesnt support VHT TXOP PS mode (OR) VHT Sta not in VHT TXOP PS
+#  mode
+# 1 = VHT AP supports VHT TXOP PS mode (OR) VHT Sta is in VHT TXOP power save
+#  mode
+#
+# +HTC-VHT Capable: [HTC-VHT]
+# Indicates whether or not the STA supports receiving a VHT variant HT Control
+# field.
+# 0 = Not supported (default)
+# 1 = supported
+#
+# Maximum A-MPDU Length Exponent: [MAX-A-MPDU-LEN-EXP0]..[MAX-A-MPDU-LEN-EXP7]
+# Indicates the maximum length of A-MPDU pre-EOF padding that the STA can recv
+# This field is an integer in the range of 0 to 7.
+# The length defined by this field is equal to
+# 2 pow(13 + Maximum A-MPDU Length Exponent) -1 octets
+#
+# VHT Link Adaptation Capable: [VHT-LINK-ADAPT2] [VHT-LINK-ADAPT3]
+# Indicates whether or not the STA supports link adaptation using VHT variant
+# HT Control field
+# If +HTC-VHTcapable is 1
+#  0 = (no feedback) if the STA does not provide VHT MFB (default)
+#  1 = reserved
+#  2 = (Unsolicited) if the STA provides only unsolicited VHT MFB
+#  3 = (Both) if the STA can provide VHT MFB in response to VHT MRQ and if the
+#      STA provides unsolicited VHT MFB
+# Reserved if +HTC-VHTcapable is 0
+#
+# Rx Antenna Pattern Consistency: [RX-ANTENNA-PATTERN]
+# Indicates the possibility of Rx antenna pattern change
+# 0 = Rx antenna pattern might change during the lifetime of an association
+# 1 = Rx antenna pattern does not change during the lifetime of an association
+#
+# Tx Antenna Pattern Consistency: [TX-ANTENNA-PATTERN]
+# Indicates the possibility of Tx antenna pattern change
+# 0 = Tx antenna pattern might change during the lifetime of an association
+# 1 = Tx antenna pattern does not change during the lifetime of an association
+#vht_capab=[SHORT-GI-80][HTC-VHT]
+#
+# Require stations to support VHT PHY (reject association if they do not)
+#require_vht=1
+
+# 0 = 20 or 40 MHz operating Channel width
+# 1 = 80 MHz channel width
+# 2 = 160 MHz channel width
+# 3 = 80+80 MHz channel width
+#vht_oper_chwidth=1
+#
+# center freq = 5 GHz + (5 * index)
+# So index 42 gives center freq 5.210 GHz
+# which is channel 42 in 5G band
+#
+#vht_oper_centr_freq_seg0_idx=42
+#
+# center freq = 5 GHz + (5 * index)
+# So index 159 gives center freq 5.795 GHz
+# which is channel 159 in 5G band
+#
+#vht_oper_centr_freq_seg1_idx=159
+
+##### IEEE 802.1X-2004 related configuration ##################################
+
+# Require IEEE 802.1X authorization
+#ieee8021x=1
+
+# IEEE 802.1X/EAPOL version
+# hostapd is implemented based on IEEE Std 802.1X-2004 which defines EAPOL
+# version 2. However, there are many client implementations that do not handle
+# the new version number correctly (they seem to drop the frames completely).
+# In order to make hostapd interoperate with these clients, the version number
+# can be set to the older version (1) with this configuration value.
+#eapol_version=2
+
+# Optional displayable message sent with EAP Request-Identity. The first \0
+# in this string will be converted to ASCII-0 (nul). This can be used to
+# separate network info (comma separated list of attribute=value pairs); see,
+# e.g., RFC 4284.
+#eap_message=hello
+#eap_message=hello\0networkid=netw,nasid=foo,portid=0,NAIRealms=example.com
+
+# WEP rekeying (disabled if key lengths are not set or are set to 0)
+# Key lengths for default/broadcast and individual/unicast keys:
+# 5 = 40-bit WEP (also known as 64-bit WEP with 40 secret bits)
+# 13 = 104-bit WEP (also known as 128-bit WEP with 104 secret bits)
+#wep_key_len_broadcast=5
+#wep_key_len_unicast=5
+# Rekeying period in seconds. 0 = do not rekey (i.e., set keys only once)
+#wep_rekey_period=300
+
+# EAPOL-Key index workaround (set bit7) for WinXP Supplicant (needed only if
+# only broadcast keys are used)
+eapol_key_index_workaround=0
+
+# EAP reauthentication period in seconds (default: 3600 seconds; 0 = disable
+# reauthentication).
+#eap_reauth_period=3600
+
+# Use PAE group address (01:80:c2:00:00:03) instead of individual target
+# address when sending EAPOL frames with driver=wired. This is the most common
+# mechanism used in wired authentication, but it also requires that the port
+# is only used by one station.
+#use_pae_group_addr=1
+
+##### Integrated EAP server ###################################################
+
+# Optionally, hostapd can be configured to use an integrated EAP server
+# to process EAP authentication locally without need for an external RADIUS
+# server. This functionality can be used both as a local authentication server
+# for IEEE 802.1X/EAPOL and as a RADIUS server for other devices.
+
+# Use integrated EAP server instead of external RADIUS authentication
+# server. This is also needed if hostapd is configured to act as a RADIUS
+# authentication server.
+eap_server=0
+
+# Path for EAP server user database
+# If SQLite support is included, this can be set to "sqlite:/path/to/sqlite.db"
+# to use SQLite database instead of a text file.
+#eap_user_file=/etc/hostapd.eap_user
+
+# CA certificate (PEM or DER file) for EAP-TLS/PEAP/TTLS
+#ca_cert=/etc/hostapd.ca.pem
+
+# Server certificate (PEM or DER file) for EAP-TLS/PEAP/TTLS
+#server_cert=/etc/hostapd.server.pem
+
+# Private key matching with the server certificate for EAP-TLS/PEAP/TTLS
+# This may point to the same file as server_cert if both certificate and key
+# are included in a single file. PKCS#12 (PFX) file (.p12/.pfx) can also be
+# used by commenting out server_cert and specifying the PFX file as the
+# private_key.
+#private_key=/etc/hostapd.server.prv
+
+# Passphrase for private key
+#private_key_passwd=secret passphrase
+
+# Server identity
+# EAP methods that provide mechanism for authenticated server identity delivery
+# use this value. If not set, "hostapd" is used as a default.
+#server_id=server.example.com
+
+# Enable CRL verification.
+# Note: hostapd does not yet support CRL downloading based on CDP. Thus, a
+# valid CRL signed by the CA is required to be included in the ca_cert file.
+# This can be done by using PEM format for CA certificate and CRL and
+# concatenating these into one file. Whenever CRL changes, hostapd needs to be
+# restarted to take the new CRL into use.
+# 0 = do not verify CRLs (default)
+# 1 = check the CRL of the user certificate
+# 2 = check all CRLs in the certificate path
+#check_crl=1
+
+# Cached OCSP stapling response (DER encoded)
+# If set, this file is sent as a certificate status response by the EAP server
+# if the EAP peer requests certificate status in the ClientHello message.
+# This cache file can be updated, e.g., by running following command
+# periodically to get an update from the OCSP responder:
+# openssl ocsp \
+#	-no_nonce \
+#	-CAfile /etc/hostapd.ca.pem \
+#	-issuer /etc/hostapd.ca.pem \
+#	-cert /etc/hostapd.server.pem \
+#	-url http://ocsp.example.com:8888/ \
+#	-respout /tmp/ocsp-cache.der
+#ocsp_stapling_response=/tmp/ocsp-cache.der
+
+# dh_file: File path to DH/DSA parameters file (in PEM format)
+# This is an optional configuration file for setting parameters for an
+# ephemeral DH key exchange. In most cases, the default RSA authentication does
+# not use this configuration. However, it is possible setup RSA to use
+# ephemeral DH key exchange. In addition, ciphers with DSA keys always use
+# ephemeral DH keys. This can be used to achieve forward secrecy. If the file
+# is in DSA parameters format, it will be automatically converted into DH
+# params. This parameter is required if anonymous EAP-FAST is used.
+# You can generate DH parameters file with OpenSSL, e.g.,
+# "openssl dhparam -out /etc/hostapd.dh.pem 1024"
+#dh_file=/etc/hostapd.dh.pem
+
+# Fragment size for EAP methods
+#fragment_size=1400
+
+# Finite cyclic group for EAP-pwd. Number maps to group of domain parameters
+# using the IANA repository for IKE (RFC 2409).
+#pwd_group=19
+
+# Configuration data for EAP-SIM database/authentication gateway interface.
+# This is a text string in implementation specific format. The example
+# implementation in eap_sim_db.c uses this as the UNIX domain socket name for
+# the HLR/AuC gateway (e.g., hlr_auc_gw). In this case, the path uses "unix:"
+# prefix. If hostapd is built with SQLite support (CONFIG_SQLITE=y in .config),
+# database file can be described with an optional db=<path> parameter.
+#eap_sim_db=unix:/tmp/hlr_auc_gw.sock
+#eap_sim_db=unix:/tmp/hlr_auc_gw.sock db=/tmp/hostapd.db
+
+# Encryption key for EAP-FAST PAC-Opaque values. This key must be a secret,
+# random value. It is configured as a 16-octet value in hex format. It can be
+# generated, e.g., with the following command:
+# od -tx1 -v -N16 /dev/random | colrm 1 8 | tr -d ' '
+#pac_opaque_encr_key=000102030405060708090a0b0c0d0e0f
+
+# EAP-FAST authority identity (A-ID)
+# A-ID indicates the identity of the authority that issues PACs. The A-ID
+# should be unique across all issuing servers. In theory, this is a variable
+# length field, but due to some existing implementations requiring A-ID to be
+# 16 octets in length, it is strongly recommended to use that length for the
+# field to provid interoperability with deployed peer implementations. This
+# field is configured in hex format.
+#eap_fast_a_id=101112131415161718191a1b1c1d1e1f
+
+# EAP-FAST authority identifier information (A-ID-Info)
+# This is a user-friendly name for the A-ID. For example, the enterprise name
+# and server name in a human-readable format. This field is encoded as UTF-8.
+#eap_fast_a_id_info=test server
+
+# Enable/disable different EAP-FAST provisioning modes:
+#0 = provisioning disabled
+#1 = only anonymous provisioning allowed
+#2 = only authenticated provisioning allowed
+#3 = both provisioning modes allowed (default)
+#eap_fast_prov=3
+
+# EAP-FAST PAC-Key lifetime in seconds (hard limit)
+#pac_key_lifetime=604800
+
+# EAP-FAST PAC-Key refresh time in seconds (soft limit on remaining hard
+# limit). The server will generate a new PAC-Key when this number of seconds
+# (or fewer) of the lifetime remains.
+#pac_key_refresh_time=86400
+
+# EAP-SIM and EAP-AKA protected success/failure indication using AT_RESULT_IND
+# (default: 0 = disabled).
+#eap_sim_aka_result_ind=1
+
+# Trusted Network Connect (TNC)
+# If enabled, TNC validation will be required before the peer is allowed to
+# connect. Note: This is only used with EAP-TTLS and EAP-FAST. If any other
+# EAP method is enabled, the peer will be allowed to connect without TNC.
+#tnc=1
+
+
+##### IEEE 802.11f - Inter-Access Point Protocol (IAPP) #######################
+
+# Interface to be used for IAPP broadcast packets
+#iapp_interface=eth0
+
+
+##### RADIUS client configuration #############################################
+# for IEEE 802.1X with external Authentication Server, IEEE 802.11
+# authentication with external ACL for MAC addresses, and accounting
+
+# The own IP address of the access point (used as NAS-IP-Address)
+own_ip_addr=127.0.0.1
+
+# Optional NAS-Identifier string for RADIUS messages. When used, this should be
+# a unique to the NAS within the scope of the RADIUS server. For example, a
+# fully qualified domain name can be used here.
+# When using IEEE 802.11r, nas_identifier must be set and must be between 1 and
+# 48 octets long.
+#nas_identifier=ap.example.com
+
+# RADIUS authentication server
+#auth_server_addr=127.0.0.1
+#auth_server_port=1812
+#auth_server_shared_secret=secret
+
+# RADIUS accounting server
+#acct_server_addr=127.0.0.1
+#acct_server_port=1813
+#acct_server_shared_secret=secret
+
+# Secondary RADIUS servers; to be used if primary one does not reply to
+# RADIUS packets. These are optional and there can be more than one secondary
+# server listed.
+#auth_server_addr=127.0.0.2
+#auth_server_port=1812
+#auth_server_shared_secret=secret2
+#
+#acct_server_addr=127.0.0.2
+#acct_server_port=1813
+#acct_server_shared_secret=secret2
+
+# Retry interval for trying to return to the primary RADIUS server (in
+# seconds). RADIUS client code will automatically try to use the next server
+# when the current server is not replying to requests. If this interval is set,
+# primary server will be retried after configured amount of time even if the
+# currently used secondary server is still working.
+#radius_retry_primary_interval=600
+
+
+# Interim accounting update interval
+# If this is set (larger than 0) and acct_server is configured, hostapd will
+# send interim accounting updates every N seconds. Note: if set, this overrides
+# possible Acct-Interim-Interval attribute in Access-Accept message. Thus, this
+# value should not be configured in hostapd.conf, if RADIUS server is used to
+# control the interim interval.
+# This value should not be less 600 (10 minutes) and must not be less than
+# 60 (1 minute).
+#radius_acct_interim_interval=600
+
+# Request Chargeable-User-Identity (RFC 4372)
+# This parameter can be used to configure hostapd to request CUI from the
+# RADIUS server by including Chargeable-User-Identity attribute into
+# Access-Request packets.
+#radius_request_cui=1
+
+# Dynamic VLAN mode; allow RADIUS authentication server to decide which VLAN
+# is used for the stations. This information is parsed from following RADIUS
+# attributes based on RFC 3580 and RFC 2868: Tunnel-Type (value 13 = VLAN),
+# Tunnel-Medium-Type (value 6 = IEEE 802), Tunnel-Private-Group-ID (value
+# VLANID as a string). Optionally, the local MAC ACL list (accept_mac_file) can
+# be used to set static client MAC address to VLAN ID mapping.
+# 0 = disabled (default)
+# 1 = option; use default interface if RADIUS server does not include VLAN ID
+# 2 = required; reject authentication if RADIUS server does not include VLAN ID
+#dynamic_vlan=0
+
+# VLAN interface list for dynamic VLAN mode is read from a separate text file.
+# This list is used to map VLAN ID from the RADIUS server to a network
+# interface. Each station is bound to one interface in the same way as with
+# multiple BSSIDs or SSIDs. Each line in this text file is defining a new
+# interface and the line must include VLAN ID and interface name separated by
+# white space (space or tab).
+# If no entries are provided by this file, the station is statically mapped
+# to <bss-iface>.<vlan-id> interfaces.
+#vlan_file=/etc/hostapd.vlan
+
+# Interface where 802.1q tagged packets should appear when a RADIUS server is
+# used to determine which VLAN a station is on.  hostapd creates a bridge for
+# each VLAN.  Then hostapd adds a VLAN interface (associated with the interface
+# indicated by 'vlan_tagged_interface') and the appropriate wireless interface
+# to the bridge.
+#vlan_tagged_interface=eth0
+
+# Bridge (prefix) to add the wifi and the tagged interface to. This gets the
+# VLAN ID appended. It defaults to brvlan%d if no tagged interface is given
+# and br%s.%d if a tagged interface is given, provided %s = tagged interface
+# and %d = VLAN ID.
+#vlan_bridge=brvlan
+
+# When hostapd creates a VLAN interface on vlan_tagged_interfaces, it needs
+# to know how to name it.
+# 0 = vlan<XXX>, e.g., vlan1
+# 1 = <vlan_tagged_interface>.<XXX>, e.g. eth0.1
+#vlan_naming=0
+
+# Arbitrary RADIUS attributes can be added into Access-Request and
+# Accounting-Request packets by specifying the contents of the attributes with
+# the following configuration parameters. There can be multiple of these to
+# add multiple attributes. These parameters can also be used to override some
+# of the attributes added automatically by hostapd.
+# Format: <attr_id>[:<syntax:value>]
+# attr_id: RADIUS attribute type (e.g., 26 = Vendor-Specific)
+# syntax: s = string (UTF-8), d = integer, x = octet string
+# value: attribute value in format indicated by the syntax
+# If syntax and value parts are omitted, a null value (single 0x00 octet) is
+# used.
+#
+# Additional Access-Request attributes
+# radius_auth_req_attr=<attr_id>[:<syntax:value>]
+# Examples:
+# Operator-Name = "Operator"
+#radius_auth_req_attr=126:s:Operator
+# Service-Type = Framed (2)
+#radius_auth_req_attr=6:d:2
+# Connect-Info = "testing" (this overrides the automatically generated value)
+#radius_auth_req_attr=77:s:testing
+# Same Connect-Info value set as a hexdump
+#radius_auth_req_attr=77:x:74657374696e67
+
+#
+# Additional Accounting-Request attributes
+# radius_acct_req_attr=<attr_id>[:<syntax:value>]
+# Examples:
+# Operator-Name = "Operator"
+#radius_acct_req_attr=126:s:Operator
+
+# Dynamic Authorization Extensions (RFC 5176)
+# This mechanism can be used to allow dynamic changes to user session based on
+# commands from a RADIUS server (or some other disconnect client that has the
+# needed session information). For example, Disconnect message can be used to
+# request an associated station to be disconnected.
+#
+# This is disabled by default. Set radius_das_port to non-zero UDP port
+# number to enable.
+#radius_das_port=3799
+#
+# DAS client (the host that can send Disconnect/CoA requests) and shared secret
+#radius_das_client=192.168.1.123 shared secret here
+#
+# DAS Event-Timestamp time window in seconds
+#radius_das_time_window=300
+#
+# DAS require Event-Timestamp
+#radius_das_require_event_timestamp=1
+
+##### RADIUS authentication server configuration ##############################
+
+# hostapd can be used as a RADIUS authentication server for other hosts. This
+# requires that the integrated EAP server is also enabled and both
+# authentication services are sharing the same configuration.
+
+# File name of the RADIUS clients configuration for the RADIUS server. If this
+# commented out, RADIUS server is disabled.
+#radius_server_clients=/etc/hostapd.radius_clients
+
+# The UDP port number for the RADIUS authentication server
+#radius_server_auth_port=1812
+
+# Use IPv6 with RADIUS server (IPv4 will also be supported using IPv6 API)
+#radius_server_ipv6=1
+
+
+##### WPA/IEEE 802.11i configuration ##########################################
+
+# Enable WPA. Setting this variable configures the AP to require WPA (either
+# WPA-PSK or WPA-RADIUS/EAP based on other configuration). For WPA-PSK, either
+# wpa_psk or wpa_passphrase must be set and wpa_key_mgmt must include WPA-PSK.
+# Instead of wpa_psk / wpa_passphrase, wpa_psk_radius might suffice.
+# For WPA-RADIUS/EAP, ieee8021x must be set (but without dynamic WEP keys),
+# RADIUS authentication server must be configured, and WPA-EAP must be included
+# in wpa_key_mgmt.
+# This field is a bit field that can be used to enable WPA (IEEE 802.11i/D3.0)
+# and/or WPA2 (full IEEE 802.11i/RSN):
+# bit0 = WPA
+# bit1 = IEEE 802.11i/RSN (WPA2) (dot11RSNAEnabled)
+wpa=2
+
+# WPA pre-shared keys for WPA-PSK. This can be either entered as a 256-bit
+# secret in hex format (64 hex digits), wpa_psk, or as an ASCII passphrase
+# (8..63 characters) that will be converted to PSK. This conversion uses SSID
+# so the PSK changes when ASCII passphrase is used and the SSID is changed.
+# wpa_psk (dot11RSNAConfigPSKValue)
+# wpa_passphrase (dot11RSNAConfigPSKPassPhrase)
+#wpa_psk=0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef
+wpa_passphrase=aaaaaaaa
+
+# Optionally, WPA PSKs can be read from a separate text file (containing list
+# of (PSK,MAC address) pairs. This allows more than one PSK to be configured.
+# Use absolute path name to make sure that the files can be read on SIGHUP
+# configuration reloads.
+#wpa_psk_file=/etc/hostapd.wpa_psk
+
+# Optionally, WPA passphrase can be received from RADIUS authentication server
+# This requires macaddr_acl to be set to 2 (RADIUS)
+# 0 = disabled (default)
+# 1 = optional; use default passphrase/psk if RADIUS server does not include
+#	Tunnel-Password
+# 2 = required; reject authentication if RADIUS server does not include
+#	Tunnel-Password
+#wpa_psk_radius=0
+
+# Set of accepted key management algorithms (WPA-PSK, WPA-EAP, or both). The
+# entries are separated with a space. WPA-PSK-SHA256 and WPA-EAP-SHA256 can be
+# added to enable SHA256-based stronger algorithms.
+# (dot11RSNAConfigAuthenticationSuitesTable)
+#wpa_key_mgmt=WPA-PSK WPA-EAP
+
+# Set of accepted cipher suites (encryption algorithms) for pairwise keys
+# (unicast packets). This is a space separated list of algorithms:
+# CCMP = AES in Counter mode with CBC-MAC [RFC 3610, IEEE 802.11i/D7.0]
+# TKIP = Temporal Key Integrity Protocol [IEEE 802.11i/D7.0]
+# Group cipher suite (encryption algorithm for broadcast and multicast frames)
+# is automatically selected based on this configuration. If only CCMP is
+# allowed as the pairwise cipher, group cipher will also be CCMP. Otherwise,
+# TKIP will be used as the group cipher.
+# (dot11RSNAConfigPairwiseCiphersTable)
+# Pairwise cipher for WPA (v1) (default: TKIP)
+#wpa_pairwise=TKIP CCMP
+# Pairwise cipher for RSN/WPA2 (default: use wpa_pairwise value)
+rsn_pairwise=CCMP
+
+# Time interval for rekeying GTK (broadcast/multicast encryption keys) in
+# seconds. (dot11RSNAConfigGroupRekeyTime)
+wpa_group_rekey=120
+
+# Rekey GTK when any STA that possesses the current GTK is leaving the BSS.
+# (dot11RSNAConfigGroupRekeyStrict)
+#wpa_strict_rekey=1
+
+# Time interval for rekeying GMK (master key used internally to generate GTKs
+# (in seconds).
+#wpa_gmk_rekey=86400
+
+# Maximum lifetime for PTK in seconds. This can be used to enforce rekeying of
+# PTK to mitigate some attacks against TKIP deficiencies.
+#wpa_ptk_rekey=600
+
+# Enable IEEE 802.11i/RSN/WPA2 pre-authentication. This is used to speed up
+# roaming be pre-authenticating IEEE 802.1X/EAP part of the full RSN
+# authentication and key handshake before actually associating with a new AP.
+# (dot11RSNAPreauthenticationEnabled)
+#rsn_preauth=1
+#
+# Space separated list of interfaces from which pre-authentication frames are
+# accepted (e.g., 'eth0' or 'eth0 wlan0wds0'. This list should include all
+# interface that are used for connections to other APs. This could include
+# wired interfaces and WDS links. The normal wireless data interface towards
+# associated stations (e.g., wlan0) should not be added, since
+# pre-authentication is only used with APs other than the currently associated
+# one.
+#rsn_preauth_interfaces=eth0
+
+# peerkey: Whether PeerKey negotiation for direct links (IEEE 802.11e) is
+# allowed. This is only used with RSN/WPA2.
+# 0 = disabled (default)
+# 1 = enabled
+#peerkey=1
+
+# ieee80211w: Whether management frame protection (MFP) is enabled
+# 0 = disabled (default)
+# 1 = optional
+# 2 = required
+#ieee80211w=0
+
+# Association SA Query maximum timeout (in TU = 1.024 ms; for MFP)
+# (maximum time to wait for a SA Query response)
+# dot11AssociationSAQueryMaximumTimeout, 1...4294967295
+#assoc_sa_query_max_timeout=1000
+
+# Association SA Query retry timeout (in TU = 1.024 ms; for MFP)
+# (time between two subsequent SA Query requests)
+# dot11AssociationSAQueryRetryTimeout, 1...4294967295
+#assoc_sa_query_retry_timeout=201
+
+# disable_pmksa_caching: Disable PMKSA caching
+# This parameter can be used to disable caching of PMKSA created through EAP
+# authentication. RSN preauthentication may still end up using PMKSA caching if
+# it is enabled (rsn_preauth=1).
+# 0 = PMKSA caching enabled (default)
+# 1 = PMKSA caching disabled
+#disable_pmksa_caching=0
+
+# okc: Opportunistic Key Caching (aka Proactive Key Caching)
+# Allow PMK cache to be shared opportunistically among configured interfaces
+# and BSSes (i.e., all configurations within a single hostapd process).
+# 0 = disabled (default)
+# 1 = enabled
+#okc=1
+
+# SAE threshold for anti-clogging mechanism (dot11RSNASAEAntiCloggingThreshold)
+# This parameter defines how many open SAE instances can be in progress at the
+# same time before the anti-clogging mechanism is taken into use.
+#sae_anti_clogging_threshold=5
+
+# Enabled SAE finite cyclic groups
+# SAE implementation are required to support group 19 (ECC group defined over a
+# 256-bit prime order field). All groups that are supported by the
+# implementation are enabled by default. This configuration parameter can be
+# used to specify a limited set of allowed groups. The group values are listed
+# in the IANA registry:
+# http://www.iana.org/assignments/ipsec-registry/ipsec-registry.xml#ipsec-registry-9
+#sae_groups=19 20 21 25 26
+
+##### IEEE 802.11r configuration ##############################################
+
+# Mobility Domain identifier (dot11FTMobilityDomainID, MDID)
+# MDID is used to indicate a group of APs (within an ESS, i.e., sharing the
+# same SSID) between which a STA can use Fast BSS Transition.
+# 2-octet identifier as a hex string.
+#mobility_domain=a1b2
+
+# PMK-R0 Key Holder identifier (dot11FTR0KeyHolderID)
+# 1 to 48 octet identifier.
+# This is configured with nas_identifier (see RADIUS client section above).
+
+# Default lifetime of the PMK-RO in minutes; range 1..65535
+# (dot11FTR0KeyLifetime)
+#r0_key_lifetime=10000
+
+# PMK-R1 Key Holder identifier (dot11FTR1KeyHolderID)
+# 6-octet identifier as a hex string.
+#r1_key_holder=000102030405
+
+# Reassociation deadline in time units (TUs / 1.024 ms; range 1000..65535)
+# (dot11FTReassociationDeadline)
+#reassociation_deadline=1000
+
+# List of R0KHs in the same Mobility Domain
+# format: <MAC address> <NAS Identifier> <128-bit key as hex string>
+# This list is used to map R0KH-ID (NAS Identifier) to a destination MAC
+# address when requesting PMK-R1 key from the R0KH that the STA used during the
+# Initial Mobility Domain Association.
+#r0kh=02:01:02:03:04:05 r0kh-1.example.com 000102030405060708090a0b0c0d0e0f
+#r0kh=02:01:02:03:04:06 r0kh-2.example.com 00112233445566778899aabbccddeeff
+# And so on.. One line per R0KH.
+
+# List of R1KHs in the same Mobility Domain
+# format: <MAC address> <R1KH-ID> <128-bit key as hex string>
+# This list is used to map R1KH-ID to a destination MAC address when sending
+# PMK-R1 key from the R0KH. This is also the list of authorized R1KHs in the MD
+# that can request PMK-R1 keys.
+#r1kh=02:01:02:03:04:05 02:11:22:33:44:55 000102030405060708090a0b0c0d0e0f
+#r1kh=02:01:02:03:04:06 02:11:22:33:44:66 00112233445566778899aabbccddeeff
+# And so on.. One line per R1KH.
+
+# Whether PMK-R1 push is enabled at R0KH
+# 0 = do not push PMK-R1 to all configured R1KHs (default)
+# 1 = push PMK-R1 to all configured R1KHs whenever a new PMK-R0 is derived
+#pmk_r1_push=1
+
+##### Neighbor table ##########################################################
+# Maximum number of entries kept in AP table (either for neigbor table or for
+# detecting Overlapping Legacy BSS Condition). The oldest entry will be
+# removed when adding a new entry that would make the list grow over this
+# limit. Note! WFA certification for IEEE 802.11g requires that OLBC is
+# enabled, so this field should not be set to 0 when using IEEE 802.11g.
+# default: 255
+#ap_table_max_size=255
+
+# Number of seconds of no frames received after which entries may be deleted
+# from the AP table. Since passive scanning is not usually performed frequently
+# this should not be set to very small value. In addition, there is no
+# guarantee that every scan cycle will receive beacon frames from the
+# neighboring APs.
+# default: 60
+#ap_table_expiration_time=3600
+
+
+##### Wi-Fi Protected Setup (WPS) #############################################
+
+# WPS state
+# 0 = WPS disabled (default)
+# 1 = WPS enabled, not configured
+# 2 = WPS enabled, configured
+#wps_state=2
+
+# Whether to manage this interface independently from other WPS interfaces
+# By default, a single hostapd process applies WPS operations to all configured
+# interfaces. This parameter can be used to disable that behavior for a subset
+# of interfaces. If this is set to non-zero for an interface, WPS commands
+# issued on that interface do not apply to other interfaces and WPS operations
+# performed on other interfaces do not affect this interface.
+#wps_independent=0
+
+# AP can be configured into a locked state where new WPS Registrar are not
+# accepted, but previously authorized Registrars (including the internal one)
+# can continue to add new Enrollees.
+#ap_setup_locked=1
+
+# Universally Unique IDentifier (UUID; see RFC 4122) of the device
+# This value is used as the UUID for the internal WPS Registrar. If the AP
+# is also using UPnP, this value should be set to the device's UPnP UUID.
+# If not configured, UUID will be generated based on the local MAC address.
+#uuid=12345678-9abc-def0-1234-56789abcdef0
+
+# Note: If wpa_psk_file is set, WPS is used to generate random, per-device PSKs
+# that will be appended to the wpa_psk_file. If wpa_psk_file is not set, the
+# default PSK (wpa_psk/wpa_passphrase) will be delivered to Enrollees. Use of
+# per-device PSKs is recommended as the more secure option (i.e., make sure to
+# set wpa_psk_file when using WPS with WPA-PSK).
+
+# When an Enrollee requests access to the network with PIN method, the Enrollee
+# PIN will need to be entered for the Registrar. PIN request notifications are
+# sent to hostapd ctrl_iface monitor. In addition, they can be written to a
+# text file that could be used, e.g., to populate the AP administration UI with
+# pending PIN requests. If the following variable is set, the PIN requests will
+# be written to the configured file.
+#wps_pin_requests=/var/run/hostapd_wps_pin_requests
+
+# Device Name
+# User-friendly description of device; up to 32 octets encoded in UTF-8
+#device_name=Wireless AP
+
+# Manufacturer
+# The manufacturer of the device (up to 64 ASCII characters)
+#manufacturer=Company
+
+# Model Name
+# Model of the device (up to 32 ASCII characters)
+#model_name=WAP
+
+# Model Number
+# Additional device description (up to 32 ASCII characters)
+#model_number=123
+
+# Serial Number
+# Serial number of the device (up to 32 characters)
+#serial_number=12345
+
+# Primary Device Type
+# Used format: <categ>-<OUI>-<subcateg>
+# categ = Category as an integer value
+# OUI = OUI and type octet as a 4-octet hex-encoded value; 0050F204 for
+#       default WPS OUI
+# subcateg = OUI-specific Sub Category as an integer value
+# Examples:
+#   1-0050F204-1 (Computer / PC)
+#   1-0050F204-2 (Computer / Server)
+#   5-0050F204-1 (Storage / NAS)
+#   6-0050F204-1 (Network Infrastructure / AP)
+#device_type=6-0050F204-1
+
+# OS Version
+# 4-octet operating system version number (hex string)
+#os_version=01020300
+
+# Config Methods
+# List of the supported configuration methods
+# Available methods: usba ethernet label display ext_nfc_token int_nfc_token
+#	nfc_interface push_button keypad virtual_display physical_display
+#	virtual_push_button physical_push_button
+#config_methods=label virtual_display virtual_push_button keypad
+
+# WPS capability discovery workaround for PBC with Windows 7
+# Windows 7 uses incorrect way of figuring out AP's WPS capabilities by acting
+# as a Registrar and using M1 from the AP. The config methods attribute in that
+# message is supposed to indicate only the configuration method supported by
+# the AP in Enrollee role, i.e., to add an external Registrar. For that case,
+# PBC shall not be used and as such, the PushButton config method is removed
+# from M1 by default. If pbc_in_m1=1 is included in the configuration file,
+# the PushButton config method is left in M1 (if included in config_methods
+# parameter) to allow Windows 7 to use PBC instead of PIN (e.g., from a label
+# in the AP).
+#pbc_in_m1=1
+
+# Static access point PIN for initial configuration and adding Registrars
+# If not set, hostapd will not allow external WPS Registrars to control the
+# access point. The AP PIN can also be set at runtime with hostapd_cli
+# wps_ap_pin command. Use of temporary (enabled by user action) and random
+# AP PIN is much more secure than configuring a static AP PIN here. As such,
+# use of the ap_pin parameter is not recommended if the AP device has means for
+# displaying a random PIN.
+#ap_pin=12345670
+
+# Skip building of automatic WPS credential
+# This can be used to allow the automatically generated Credential attribute to
+# be replaced with pre-configured Credential(s).
+#skip_cred_build=1
+
+# Additional Credential attribute(s)
+# This option can be used to add pre-configured Credential attributes into M8
+# message when acting as a Registrar. If skip_cred_build=1, this data will also
+# be able to override the Credential attribute that would have otherwise been
+# automatically generated based on network configuration. This configuration
+# option points to an external file that much contain the WPS Credential
+# attribute(s) as binary data.
+#extra_cred=hostapd.cred
+
+# Credential processing
+#   0 = process received credentials internally (default)
+#   1 = do not process received credentials; just pass them over ctrl_iface to
+#	external program(s)
+#   2 = process received credentials internally and pass them over ctrl_iface
+#	to external program(s)
+# Note: With wps_cred_processing=1, skip_cred_build should be set to 1 and
+# extra_cred be used to provide the Credential data for Enrollees.
+#
+# wps_cred_processing=1 will disabled automatic updates of hostapd.conf file
+# both for Credential processing and for marking AP Setup Locked based on
+# validation failures of AP PIN. An external program is responsible on updating
+# the configuration appropriately in this case.
+#wps_cred_processing=0
+
+# AP Settings Attributes for M7
+# By default, hostapd generates the AP Settings Attributes for M7 based on the
+# current configuration. It is possible to override this by providing a file
+# with pre-configured attributes. This is similar to extra_cred file format,
+# but the AP Settings attributes are not encapsulated in a Credential
+# attribute.
+#ap_settings=hostapd.ap_settings
+
+# WPS UPnP interface
+# If set, support for external Registrars is enabled.
+#upnp_iface=br0
+
+# Friendly Name (required for UPnP)
+# Short description for end use. Should be less than 64 characters.
+#friendly_name=WPS Access Point
+
+# Manufacturer URL (optional for UPnP)
+#manufacturer_url=http://www.example.com/
+
+# Model Description (recommended for UPnP)
+# Long description for end user. Should be less than 128 characters.
+#model_description=Wireless Access Point
+
+# Model URL (optional for UPnP)
+#model_url=http://www.example.com/model/
+
+# Universal Product Code (optional for UPnP)
+# 12-digit, all-numeric code that identifies the consumer package.
+#upc=123456789012
+
+# WPS RF Bands (a = 5G, b = 2.4G, g = 2.4G, ag = dual band)
+# This value should be set according to RF band(s) supported by the AP if
+# hw_mode is not set. For dual band dual concurrent devices, this needs to be
+# set to ag to allow both RF bands to be advertized.
+#wps_rf_bands=ag
+
+# NFC password token for WPS
+# These parameters can be used to configure a fixed NFC password token for the
+# AP. This can be generated, e.g., with nfc_pw_token from wpa_supplicant. When
+# these parameters are used, the AP is assumed to be deployed with a NFC tag
+# that includes the matching NFC password token (e.g., written based on the
+# NDEF record from nfc_pw_token).
+#
+#wps_nfc_dev_pw_id: Device Password ID (16..65535)
+#wps_nfc_dh_pubkey: Hexdump of DH Public Key
+#wps_nfc_dh_privkey: Hexdump of DH Private Key
+#wps_nfc_dev_pw: Hexdump of Device Password
+
+##### Wi-Fi Direct (P2P) ######################################################
+
+# Enable P2P Device management
+#manage_p2p=1
+
+# Allow cross connection
+#allow_cross_connection=1
+
+#### TDLS (IEEE 802.11z-2010) #################################################
+
+# Prohibit use of TDLS in this BSS
+#tdls_prohibit=1
+
+# Prohibit use of TDLS Channel Switching in this BSS
+#tdls_prohibit_chan_switch=1
+
+##### IEEE 802.11v-2011 #######################################################
+
+# Time advertisement
+# 0 = disabled (default)
+# 2 = UTC time at which the TSF timer is 0
+#time_advertisement=2
+
+# Local time zone as specified in 8.3 of IEEE Std 1003.1-2004:
+# stdoffset[dst[offset][,start[/time],end[/time]]]
+#time_zone=EST5
+
+# WNM-Sleep Mode (extended sleep mode for stations)
+# 0 = disabled (default)
+# 1 = enabled (allow stations to use WNM-Sleep Mode)
+#wnm_sleep_mode=1
+
+# BSS Transition Management
+# 0 = disabled (default)
+# 1 = enabled
+#bss_transition=1
+
+##### IEEE 802.11u-2011 #######################################################
+
+# Enable Interworking service
+#interworking=1
+
+# Access Network Type
+# 0 = Private network
+# 1 = Private network with guest access
+# 2 = Chargeable public network
+# 3 = Free public network
+# 4 = Personal device network
+# 5 = Emergency services only network
+# 14 = Test or experimental
+# 15 = Wildcard
+#access_network_type=0
+
+# Whether the network provides connectivity to the Internet
+# 0 = Unspecified
+# 1 = Network provides connectivity to the Internet
+#internet=1
+
+# Additional Step Required for Access
+# Note: This is only used with open network, i.e., ASRA shall ne set to 0 if
+# RSN is used.
+#asra=0
+
+# Emergency services reachable
+#esr=0
+
+# Unauthenticated emergency service accessible
+#uesa=0
+
+# Venue Info (optional)
+# The available values are defined in IEEE Std 802.11u-2011, 7.3.1.34.
+# Example values (group,type):
+# 0,0 = Unspecified
+# 1,7 = Convention Center
+# 1,13 = Coffee Shop
+# 2,0 = Unspecified Business
+# 7,1  Private Residence
+#venue_group=7
+#venue_type=1
+
+# Homogeneous ESS identifier (optional; dot11HESSID)
+# If set, this shall be identifical to one of the BSSIDs in the homogeneous
+# ESS and this shall be set to the same value across all BSSs in homogeneous
+# ESS.
+#hessid=02:03:04:05:06:07
+
+# Roaming Consortium List
+# Arbitrary number of Roaming Consortium OIs can be configured with each line
+# adding a new OI to the list. The first three entries are available through
+# Beacon and Probe Response frames. Any additional entry will be available only
+# through ANQP queries. Each OI is between 3 and 15 octets and is configured as
+# a hexstring.
+#roaming_consortium=021122
+#roaming_consortium=2233445566
+
+# Venue Name information
+# This parameter can be used to configure one or more Venue Name Duples for
+# Venue Name ANQP information. Each entry has a two or three character language
+# code (ISO-639) separated by colon from the venue name string.
+# Note that venue_group and venue_type have to be set for Venue Name
+# information to be complete.
+#venue_name=eng:Example venue
+#venue_name=fin:Esimerkkipaikka
+# Alternative format for language:value strings:
+# (double quoted string, printf-escaped string)
+#venue_name=P"eng:Example\nvenue"
+
+# Network Authentication Type
+# This parameter indicates what type of network authentication is used in the
+# network.
+# format: <network auth type indicator (1-octet hex str)> [redirect URL]
+# Network Authentication Type Indicator values:
+# 00 = Acceptance of terms and conditions
+# 01 = On-line enrollment supported
+# 02 = http/https redirection
+# 03 = DNS redirection
+#network_auth_type=00
+#network_auth_type=02http://www.example.com/redirect/me/here/
+
+# IP Address Type Availability
+# format: <1-octet encoded value as hex str>
+# (ipv4_type & 0x3f) << 2 | (ipv6_type & 0x3)
+# ipv4_type:
+# 0 = Address type not available
+# 1 = Public IPv4 address available
+# 2 = Port-restricted IPv4 address available
+# 3 = Single NATed private IPv4 address available
+# 4 = Double NATed private IPv4 address available
+# 5 = Port-restricted IPv4 address and single NATed IPv4 address available
+# 6 = Port-restricted IPv4 address and double NATed IPv4 address available
+# 7 = Availability of the address type is not known
+# ipv6_type:
+# 0 = Address type not available
+# 1 = Address type available
+# 2 = Availability of the address type not known
+#ipaddr_type_availability=14
+
+# Domain Name
+# format: <variable-octet str>[,<variable-octet str>]
+#domain_name=example.com,another.example.com,yet-another.example.com
+
+# 3GPP Cellular Network information
+# format: <MCC1,MNC1>[;<MCC2,MNC2>][;...]
+#anqp_3gpp_cell_net=244,91;310,026;234,56
+
+# NAI Realm information
+# One or more realm can be advertised. Each nai_realm line adds a new realm to
+# the set. These parameters provide information for stations using Interworking
+# network selection to allow automatic connection to a network based on
+# credentials.
+# format: <encoding>,<NAI Realm(s)>[,<EAP Method 1>][,<EAP Method 2>][,...]
+# encoding:
+#	0 = Realm formatted in accordance with IETF RFC 4282
+#	1 = UTF-8 formatted character string that is not formatted in
+#	    accordance with IETF RFC 4282
+# NAI Realm(s): Semi-colon delimited NAI Realm(s)
+# EAP Method: <EAP Method>[:<[AuthParam1:Val1]>][<[AuthParam2:Val2]>][...]
+# AuthParam (Table 8-188 in IEEE Std 802.11-2012):
+# ID 2 = Non-EAP Inner Authentication Type
+#	1 = PAP, 2 = CHAP, 3 = MSCHAP, 4 = MSCHAPV2
+# ID 3 = Inner authentication EAP Method Type
+# ID 5 = Credential Type
+#	1 = SIM, 2 = USIM, 3 = NFC Secure Element, 4 = Hardware Token,
+#	5 = Softoken, 6 = Certificate, 7 = username/password, 9 = Anonymous,
+#	10 = Vendor Specific
+#nai_realm=0,example.com;example.net
+# EAP methods EAP-TLS with certificate and EAP-TTLS/MSCHAPv2 with
+# username/password
+#nai_realm=0,example.org,13[5:6],21[2:4][5:7]
+
+# QoS Map Set configuration
+#
+# Comma delimited QoS Map Set in decimal values
+# (see IEEE Std 802.11-2012, 8.4.2.97)
+#
+# format:
+# [<DSCP Exceptions[DSCP,UP]>,]<UP 0 range[low,high]>,...<UP 7 range[low,high]>
+#
+# There can be up to 21 optional DSCP Exceptions which are pairs of DSCP Value
+# (0..63 or 255) and User Priority (0..7). This is followed by eight DSCP Range
+# descriptions with DSCP Low Value and DSCP High Value pairs (0..63 or 255) for
+# each UP starting from 0. If both low and high value are set to 255, the
+# corresponding UP is not used.
+#
+# default: not set
+#qos_map_set=53,2,22,6,8,15,0,7,255,255,16,31,32,39,255,255,40,47,255,255
+
+##### Hotspot 2.0 #############################################################
+
+# Enable Hotspot 2.0 support
+#hs20=1
+
+# Disable Downstream Group-Addressed Forwarding (DGAF)
+# This can be used to configure a network where no group-addressed frames are
+# allowed. The AP will not forward any group-address frames to the stations and
+# random GTKs are issued for each station to prevent associated stations from
+# forging such frames to other stations in the BSS.
+#disable_dgaf=1
+
+# Operator Friendly Name
+# This parameter can be used to configure one or more Operator Friendly Name
+# Duples. Each entry has a two or three character language code (ISO-639)
+# separated by colon from the operator friendly name string.
+#hs20_oper_friendly_name=eng:Example operator
+#hs20_oper_friendly_name=fin:Esimerkkioperaattori
+
+# Connection Capability
+# This can be used to advertise what type of IP traffic can be sent through the
+# hotspot (e.g., due to firewall allowing/blocking protocols/ports).
+# format: <IP Protocol>:<Port Number>:<Status>
+# IP Protocol: 1 = ICMP, 6 = TCP, 17 = UDP
+# Port Number: 0..65535
+# Status: 0 = Closed, 1 = Open, 2 = Unknown
+# Each hs20_conn_capab line is added to the list of advertised tuples.
+#hs20_conn_capab=1:0:2
+#hs20_conn_capab=6:22:1
+#hs20_conn_capab=17:5060:0
+
+# WAN Metrics
+# format: <WAN Info>:<DL Speed>:<UL Speed>:<DL Load>:<UL Load>:<LMD>
+# WAN Info: B0-B1: Link Status, B2: Symmetric Link, B3: At Capabity
+#    (encoded as two hex digits)
+#    Link Status: 1 = Link up, 2 = Link down, 3 = Link in test state
+# Downlink Speed: Estimate of WAN backhaul link current downlink speed in kbps;
+#	1..4294967295; 0 = unknown
+# Uplink Speed: Estimate of WAN backhaul link current uplink speed in kbps
+#	1..4294967295; 0 = unknown
+# Downlink Load: Current load of downlink WAN connection (scaled to 255 = 100%)
+# Uplink Load: Current load of uplink WAN connection (scaled to 255 = 100%)
+# Load Measurement Duration: Duration for measuring downlink/uplink load in
+# tenths of a second (1..65535); 0 if load cannot be determined
+#hs20_wan_metrics=01:8000:1000:80:240:3000
+
+# Operating Class Indication
+# List of operating classes the BSSes in this ESS use. The Global operating
+# classes in Table E-4 of IEEE Std 802.11-2012 Annex E define the values that
+# can be used in this.
+# format: hexdump of operating class octets
+# for example, operating classes 81 (2.4 GHz channels 1-13) and 115 (5 GHz
+# channels 36-48):
+#hs20_operating_class=5173
+
+##### TESTING OPTIONS #########################################################
+#
+# The options in this section are only available when the build configuration
+# option CONFIG_TESTING_OPTIONS is set while compiling hostapd. They allow
+# testing some scenarios that are otherwise difficult to reproduce.
+#
+# Ignore probe requests sent to hostapd with the given probability, must be a
+# floating point number in the range [0, 1).
+#ignore_probe_probability=0.0
+#
+# Ignore authentication frames with the given probability
+#ignore_auth_probability=0.0
+#
+# Ignore association requests with the given probability
+#ignore_assoc_probability=0.0
+#
+# Ignore reassociation requests with the given probability
+#ignore_reassoc_probability=0.0
+#
+# Corrupt Key MIC in GTK rekey EAPOL-Key frames with the given probability
+#corrupt_gtk_rekey_mic_probability=0.0
+
+##### Multiple BSSID support ##################################################
+#
+# Above configuration is using the default interface (wlan#, or multi-SSID VLAN
+# interfaces). Other BSSIDs can be added by using separator 'bss' with
+# default interface name to be allocated for the data packets of the new BSS.
+#
+# hostapd will generate BSSID mask based on the BSSIDs that are
+# configured. hostapd will verify that dev_addr & MASK == dev_addr. If this is
+# not the case, the MAC address of the radio must be changed before starting
+# hostapd (ifconfig wlan0 hw ether <MAC addr>). If a BSSID is configured for
+# every secondary BSS, this limitation is not applied at hostapd and other
+# masks may be used if the driver supports them (e.g., swap the locally
+# administered bit)
+#
+# BSSIDs are assigned in order to each BSS, unless an explicit BSSID is
+# specified using the 'bssid' parameter.
+# If an explicit BSSID is specified, it must be chosen such that it:
+# - results in a valid MASK that covers it and the dev_addr
+# - is not the same as the MAC address of the radio
+# - is not the same as any other explicitly specified BSSID
+#
+# Please note that hostapd uses some of the values configured for the first BSS
+# as the defaults for the following BSSes. However, it is recommended that all
+# BSSes include explicit configuration of all relevant configuration items.
+#
+#bss=wlan0_0
+#ssid=test2
+# most of the above items can be used here (apart from radio interface specific
+# items, like channel)
+
+#bss=wlan0_1
+#bssid=00:13:10:95:fe:0b
+# ...
diff --git a/drivers/net/wireless/ssv6x5x/script/hostapd.conf.NO_SEC.template b/drivers/net/wireless/ssv6x5x/script/hostapd.conf.NO_SEC.template
new file mode 100755
index 000000000..eff8920da
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/hostapd.conf.NO_SEC.template
@@ -0,0 +1,1664 @@
+##### hostapd configuration file ##############################################
+# Empty lines and lines starting with # are ignored
+
+# AP netdevice name (without 'ap' postfix, i.e., wlan0 uses wlan0ap for
+# management frames); ath0 for madwifi
+interface=HOSTAPD_IF
+
+# In case of madwifi, atheros, and nl80211 driver interfaces, an additional
+# configuration parameter, bridge, may be used to notify hostapd if the
+# interface is included in a bridge. This parameter is not used with Host AP
+# driver. If the bridge parameter is not set, the drivers will automatically
+# figure out the bridge interface (assuming sysfs is enabled and mounted to
+# /sys) and this parameter may not be needed.
+#
+# For nl80211, this parameter can be used to request the AP interface to be
+# added to the bridge automatically (brctl may refuse to do this before hostapd
+# has been started to change the interface mode). If needed, the bridge
+# interface is also created.
+#bridge=br0
+
+# Driver interface type (hostap/wired/madwifi/test/none/nl80211/bsd);
+# default: hostap). nl80211 is used with all Linux mac80211 drivers.
+# Use driver=none if building hostapd as a standalone RADIUS server that does
+# not control any wireless/wired driver.
+# driver=hostap
+
+# hostapd event logger configuration
+#
+# Two output method: syslog and stdout (only usable if not forking to
+# background).
+#
+# Module bitfield (ORed bitfield of modules that will be logged; -1 = all
+# modules):
+# bit 0 (1) = IEEE 802.11
+# bit 1 (2) = IEEE 802.1X
+# bit 2 (4) = RADIUS
+# bit 3 (8) = WPA
+# bit 4 (16) = driver interface
+# bit 5 (32) = IAPP
+# bit 6 (64) = MLME
+#
+# Levels (minimum value for logged events):
+#  0 = verbose debugging
+#  1 = debugging
+#  2 = informational messages
+#  3 = notification
+#  4 = warning
+#
+logger_syslog=1
+logger_syslog_level=0
+logger_stdout=1
+logger_stdout_level=0
+
+# Interface for separate control program. If this is specified, hostapd
+# will create this directory and a UNIX domain socket for listening to requests
+# from external programs (CLI/GUI, etc.) for status information and
+# configuration. The socket file will be named based on the interface name, so
+# multiple hostapd processes/interfaces can be run at the same time if more
+# than one interface is used.
+# /var/run/hostapd is the recommended directory for sockets and by default,
+# hostapd_cli will use it when trying to connect with hostapd.
+ctrl_interface=/var/run/hostapd
+
+# Access control for the control interface can be configured by setting the
+# directory to allow only members of a group to use sockets. This way, it is
+# possible to run hostapd as root (since it needs to change network
+# configuration and open raw sockets) and still allow GUI/CLI components to be
+# run as non-root users. However, since the control interface can be used to
+# change the network configuration, this access needs to be protected in many
+# cases. By default, hostapd is configured to use gid 0 (root). If you
+# want to allow non-root users to use the contron interface, add a new group
+# and change this value to match with that group. Add users that should have
+# control interface access to this group.
+#
+# This variable can be a group name or gid.
+#ctrl_interface_group=wheel
+ctrl_interface_group=0
+
+
+##### IEEE 802.11 related configuration #######################################
+
+# SSID to be used in IEEE 802.11 management frames
+ssid=TestAP
+# Alternative formats for configuring SSID
+# (double quoted string, hexdump, printf-escaped string)
+#ssid2="test"
+#ssid2=74657374
+#ssid2=P"hello\nthere"
+
+# UTF-8 SSID: Whether the SSID is to be interpreted using UTF-8 encoding
+#utf8_ssid=1
+
+# Country code (ISO/IEC 3166-1). Used to set regulatory domain.
+# Set as needed to indicate country in which device is operating.
+# This can limit available channels and transmit power.
+#country_code=US
+
+# Enable IEEE 802.11d. This advertises the country_code and the set of allowed
+# channels and transmit power levels based on the regulatory limits. The
+# country_code setting must be configured with the correct country for
+# IEEE 802.11d functions.
+# (default: 0 = disabled)
+#ieee80211d=1
+
+# Enable IEEE 802.11h. This enables radar detection and DFS support if
+# available. DFS support is required on outdoor 5 GHz channels in most countries
+# of the world. This can be used only with ieee80211d=1.
+# (default: 0 = disabled)
+#ieee80211h=1
+
+# Operation mode (a = IEEE 802.11a, b = IEEE 802.11b, g = IEEE 802.11g,
+# ad = IEEE 802.11ad (60 GHz); a/g options are used with IEEE 802.11n, too, to
+# specify band)
+# Default: IEEE 802.11b
+hw_mode=g
+
+# Channel number (IEEE 802.11)
+# (default: 0, i.e., not set)
+# Please note that some drivers do not use this value from hostapd and the
+# channel will need to be configured separately with iwconfig.
+#
+# If CONFIG_ACS build option is enabled, the channel can be selected
+# automatically at run time by setting channel=acs_survey or channel=0, both of
+# which will enable the ACS survey based algorithm.
+channel=6
+
+# ACS tuning - Automatic Channel Selection
+# See: http://wireless.kernel.org/en/users/Documentation/acs
+#
+# You can customize the ACS survey algorithm with following variables:
+#
+# acs_num_scans requirement is 1..100 - number of scans to be performed that
+# are used to trigger survey data gathering of an underlying device driver.
+# Scans are passive and typically take a little over 100ms (depending on the
+# driver) on each available channel for given hw_mode. Increasing this value
+# means sacrificing startup time and gathering more data wrt channel
+# interference that may help choosing a better channel. This can also help fine
+# tune the ACS scan time in case a driver has different scan dwell times.
+#
+# Defaults:
+#acs_num_scans=5
+
+# Beacon interval in kus (1.024 ms) (default: 100; range 15..65535)
+beacon_int=100
+
+# DTIM (delivery traffic information message) period (range 1..255):
+# number of beacons between DTIMs (1 = every beacon includes DTIM element)
+# (default: 2)
+dtim_period=2
+
+# Maximum number of stations allowed in station table. New stations will be
+# rejected after the station table is full. IEEE 802.11 has a limit of 2007
+# different association IDs, so this number should not be larger than that.
+# (default: 2007)
+max_num_sta=255
+
+# RTS/CTS threshold; 2347 = disabled (default); range 0..2347
+# If this field is not included in hostapd.conf, hostapd will not control
+# RTS threshold and 'iwconfig wlan# rts <val>' can be used to set it.
+rts_threshold=2347
+
+# Fragmentation threshold; 2346 = disabled (default); range 256..2346
+# If this field is not included in hostapd.conf, hostapd will not control
+# fragmentation threshold and 'iwconfig wlan# frag <val>' can be used to set
+# it.
+fragm_threshold=2346
+
+# Rate configuration
+# Default is to enable all rates supported by the hardware. This configuration
+# item allows this list be filtered so that only the listed rates will be left
+# in the list. If the list is empty, all rates are used. This list can have
+# entries that are not in the list of rates the hardware supports (such entries
+# are ignored). The entries in this list are in 100 kbps, i.e., 11 Mbps = 110.
+# If this item is present, at least one rate have to be matching with the rates
+# hardware supports.
+# default: use the most common supported rate setting for the selected
+# hw_mode (i.e., this line can be removed from configuration file in most
+# cases)
+#supported_rates=10 20 55 110 60 90 120 180 240 360 480 540
+
+# Basic rate set configuration
+# List of rates (in 100 kbps) that are included in the basic rate set.
+# If this item is not included, usually reasonable default set is used.
+#basic_rates=10 20
+#basic_rates=10 20 55 110
+#basic_rates=60 120 240
+
+# Short Preamble
+# This parameter can be used to enable optional use of short preamble for
+# frames sent at 2 Mbps, 5.5 Mbps, and 11 Mbps to improve network performance.
+# This applies only to IEEE 802.11b-compatible networks and this should only be
+# enabled if the local hardware supports use of short preamble. If any of the
+# associated STAs do not support short preamble, use of short preamble will be
+# disabled (and enabled when such STAs disassociate) dynamically.
+# 0 = do not allow use of short preamble (default)
+# 1 = allow use of short preamble
+#preamble=1
+
+# Station MAC address -based authentication
+# Please note that this kind of access control requires a driver that uses
+# hostapd to take care of management frame processing and as such, this can be
+# used with driver=hostap or driver=nl80211, but not with driver=madwifi.
+# 0 = accept unless in deny list
+# 1 = deny unless in accept list
+# 2 = use external RADIUS server (accept/deny lists are searched first)
+macaddr_acl=0
+
+# Accept/deny lists are read from separate files (containing list of
+# MAC addresses, one per line). Use absolute path name to make sure that the
+# files can be read on SIGHUP configuration reloads.
+#accept_mac_file=/etc/hostapd.accept
+#deny_mac_file=/etc/hostapd.deny
+
+# IEEE 802.11 specifies two authentication algorithms. hostapd can be
+# configured to allow both of these or only one. Open system authentication
+# should be used with IEEE 802.1X.
+# Bit fields of allowed authentication algorithms:
+# bit 0 = Open System Authentication
+# bit 1 = Shared Key Authentication (requires WEP)
+auth_algs=3
+
+# Send empty SSID in beacons and ignore probe request frames that do not
+# specify full SSID, i.e., require stations to know SSID.
+# default: disabled (0)
+# 1 = send empty (length=0) SSID in beacon and ignore probe request for
+#     broadcast SSID
+# 2 = clear SSID (ASCII 0), but keep the original length (this may be required
+#     with some clients that do not support empty SSID) and ignore probe
+#     requests for broadcast SSID
+ignore_broadcast_ssid=0
+
+# Additional vendor specfic elements for Beacon and Probe Response frames
+# This parameter can be used to add additional vendor specific element(s) into
+# the end of the Beacon and Probe Response frames. The format for these
+# element(s) is a hexdump of the raw information elements (id+len+payload for
+# one or more elements)
+#vendor_elements=dd0411223301
+
+# TX queue parameters (EDCF / bursting)
+# tx_queue_<queue name>_<param>
+# queues: data0, data1, data2, data3, after_beacon, beacon
+#		(data0 is the highest priority queue)
+# parameters:
+#   aifs: AIFS (default 2)
+#   cwmin: cwMin (1, 3, 7, 15, 31, 63, 127, 255, 511, 1023)
+#   cwmax: cwMax (1, 3, 7, 15, 31, 63, 127, 255, 511, 1023); cwMax >= cwMin
+#   burst: maximum length (in milliseconds with precision of up to 0.1 ms) for
+#          bursting
+#
+# Default WMM parameters (IEEE 802.11 draft; 11-03-0504-03-000e):
+# These parameters are used by the access point when transmitting frames
+# to the clients.
+#
+# Low priority / AC_BK = background
+#tx_queue_data3_aifs=7
+#tx_queue_data3_cwmin=15
+#tx_queue_data3_cwmax=1023
+#tx_queue_data3_burst=0
+# Note: for IEEE 802.11b mode: cWmin=31 cWmax=1023 burst=0
+#
+# Normal priority / AC_BE = best effort
+#tx_queue_data2_aifs=3
+#tx_queue_data2_cwmin=15
+#tx_queue_data2_cwmax=63
+#tx_queue_data2_burst=0
+# Note: for IEEE 802.11b mode: cWmin=31 cWmax=127 burst=0
+#
+# High priority / AC_VI = video
+#tx_queue_data1_aifs=1
+#tx_queue_data1_cwmin=7
+#tx_queue_data1_cwmax=15
+#tx_queue_data1_burst=3.0
+# Note: for IEEE 802.11b mode: cWmin=15 cWmax=31 burst=6.0
+#
+# Highest priority / AC_VO = voice
+#tx_queue_data0_aifs=1
+#tx_queue_data0_cwmin=3
+#tx_queue_data0_cwmax=7
+#tx_queue_data0_burst=1.5
+# Note: for IEEE 802.11b mode: cWmin=7 cWmax=15 burst=3.3
+
+# 802.1D Tag (= UP) to AC mappings
+# WMM specifies following mapping of data frames to different ACs. This mapping
+# can be configured using Linux QoS/tc and sch_pktpri.o module.
+# 802.1D Tag	802.1D Designation	Access Category	WMM Designation
+# 1		BK			AC_BK		Background
+# 2		-			AC_BK		Background
+# 0		BE			AC_BE		Best Effort
+# 3		EE			AC_BE		Best Effort
+# 4		CL			AC_VI		Video
+# 5		VI			AC_VI		Video
+# 6		VO			AC_VO		Voice
+# 7		NC			AC_VO		Voice
+# Data frames with no priority information: AC_BE
+# Management frames: AC_VO
+# PS-Poll frames: AC_BE
+
+# Default WMM parameters (IEEE 802.11 draft; 11-03-0504-03-000e):
+# for 802.11a or 802.11g networks
+# These parameters are sent to WMM clients when they associate.
+# The parameters will be used by WMM clients for frames transmitted to the
+# access point.
+#
+# note - txop_limit is in units of 32microseconds
+# note - acm is admission control mandatory flag. 0 = admission control not
+# required, 1 = mandatory
+# note - here cwMin and cmMax are in exponent form. the actual cw value used
+# will be (2^n)-1 where n is the value given here
+#
+wmm_enabled=1
+#
+# WMM-PS Unscheduled Automatic Power Save Delivery [U-APSD]
+# Enable this flag if U-APSD supported outside hostapd (eg., Firmware/driver)
+#uapsd_advertisement_enabled=1
+#
+# Low priority / AC_BK = background
+wmm_ac_bk_cwmin=4
+wmm_ac_bk_cwmax=10
+wmm_ac_bk_aifs=7
+wmm_ac_bk_txop_limit=0
+wmm_ac_bk_acm=0
+# Note: for IEEE 802.11b mode: cWmin=5 cWmax=10
+#
+# Normal priority / AC_BE = best effort
+wmm_ac_be_aifs=3
+wmm_ac_be_cwmin=4
+wmm_ac_be_cwmax=10
+wmm_ac_be_txop_limit=0
+wmm_ac_be_acm=0
+# Note: for IEEE 802.11b mode: cWmin=5 cWmax=7
+#
+# High priority / AC_VI = video
+wmm_ac_vi_aifs=2
+wmm_ac_vi_cwmin=3
+wmm_ac_vi_cwmax=4
+wmm_ac_vi_txop_limit=94
+wmm_ac_vi_acm=0
+# Note: for IEEE 802.11b mode: cWmin=4 cWmax=5 txop_limit=188
+#
+# Highest priority / AC_VO = voice
+wmm_ac_vo_aifs=2
+wmm_ac_vo_cwmin=2
+wmm_ac_vo_cwmax=3
+wmm_ac_vo_txop_limit=47
+wmm_ac_vo_acm=0
+# Note: for IEEE 802.11b mode: cWmin=3 cWmax=4 burst=102
+
+# Static WEP key configuration
+#
+# The key number to use when transmitting.
+# It must be between 0 and 3, and the corresponding key must be set.
+# default: not set
+#wep_default_key=0
+# The WEP keys to use.
+# A key may be a quoted string or unquoted hexadecimal digits.
+# The key length should be 5, 13, or 16 characters, or 10, 26, or 32
+# digits, depending on whether 40-bit (64-bit), 104-bit (128-bit), or
+# 128-bit (152-bit) WEP is used.
+# Only the default key must be supplied; the others are optional.
+# default: not set
+#wep_key0=123456789a
+#wep_key1="vwxyz"
+#wep_key2=0102030405060708090a0b0c0d
+#wep_key3=".2.4.6.8.0.23"
+
+# Station inactivity limit
+#
+# If a station does not send anything in ap_max_inactivity seconds, an
+# empty data frame is sent to it in order to verify whether it is
+# still in range. If this frame is not ACKed, the station will be
+# disassociated and then deauthenticated. This feature is used to
+# clear station table of old entries when the STAs move out of the
+# range.
+#
+# The station can associate again with the AP if it is still in range;
+# this inactivity poll is just used as a nicer way of verifying
+# inactivity; i.e., client will not report broken connection because
+# disassociation frame is not sent immediately without first polling
+# the STA with a data frame.
+# default: 300 (i.e., 5 minutes)
+#ap_max_inactivity=300
+#
+# The inactivity polling can be disabled to disconnect stations based on
+# inactivity timeout so that idle stations are more likely to be disconnected
+# even if they are still in range of the AP. This can be done by setting
+# skip_inactivity_poll to 1 (default 0).
+#skip_inactivity_poll=0
+
+# Disassociate stations based on excessive transmission failures or other
+# indications of connection loss. This depends on the driver capabilities and
+# may not be available with all drivers.
+#disassoc_low_ack=1
+
+# Maximum allowed Listen Interval (how many Beacon periods STAs are allowed to
+# remain asleep). Default: 65535 (no limit apart from field size)
+#max_listen_interval=100
+
+# WDS (4-address frame) mode with per-station virtual interfaces
+# (only supported with driver=nl80211)
+# This mode allows associated stations to use 4-address frames to allow layer 2
+# bridging to be used.
+#wds_sta=1
+
+# If bridge parameter is set, the WDS STA interface will be added to the same
+# bridge by default. This can be overridden with the wds_bridge parameter to
+# use a separate bridge.
+#wds_bridge=wds-br0
+
+# Start the AP with beaconing disabled by default.
+#start_disabled=0
+
+# Client isolation can be used to prevent low-level bridging of frames between
+# associated stations in the BSS. By default, this bridging is allowed.
+#ap_isolate=1
+
+# Fixed BSS Load value for testing purposes
+# This field can be used to configure hostapd to add a fixed BSS Load element
+# into Beacon and Probe Response frames for testing purposes. The format is
+# <station count>:<channel utilization>:<available admission capacity>
+#bss_load_test=12:80:20000
+
+##### IEEE 802.11n related configuration ######################################
+
+# ieee80211n: Whether IEEE 802.11n (HT) is enabled
+# 0 = disabled (default)
+# 1 = enabled
+# Note: You will also need to enable WMM for full HT functionality.
+ieee80211n=1
+
+# ht_capab: HT capabilities (list of flags)
+# LDPC coding capability: [LDPC] = supported
+# Supported channel width set: [HT40-] = both 20 MHz and 40 MHz with secondary
+#	channel below the primary channel; [HT40+] = both 20 MHz and 40 MHz
+#	with secondary channel below the primary channel
+#	(20 MHz only if neither is set)
+#	Note: There are limits on which channels can be used with HT40- and
+#	HT40+. Following table shows the channels that may be available for
+#	HT40- and HT40+ use per IEEE 802.11n Annex J:
+#	freq		HT40-		HT40+
+#	2.4 GHz		5-13		1-7 (1-9 in Europe/Japan)
+#	5 GHz		40,48,56,64	36,44,52,60
+#	(depending on the location, not all of these channels may be available
+#	for use)
+#	Please note that 40 MHz channels may switch their primary and secondary
+#	channels if needed or creation of 40 MHz channel maybe rejected based
+#	on overlapping BSSes. These changes are done automatically when hostapd
+#	is setting up the 40 MHz channel.
+# Spatial Multiplexing (SM) Power Save: [SMPS-STATIC] or [SMPS-DYNAMIC]
+#	(SMPS disabled if neither is set)
+# HT-greenfield: [GF] (disabled if not set)
+# Short GI for 20 MHz: [SHORT-GI-20] (disabled if not set)
+# Short GI for 40 MHz: [SHORT-GI-40] (disabled if not set)
+# Tx STBC: [TX-STBC] (disabled if not set)
+# Rx STBC: [RX-STBC1] (one spatial stream), [RX-STBC12] (one or two spatial
+#	streams), or [RX-STBC123] (one, two, or three spatial streams); Rx STBC
+#	disabled if none of these set
+# HT-delayed Block Ack: [DELAYED-BA] (disabled if not set)
+# Maximum A-MSDU length: [MAX-AMSDU-7935] for 7935 octets (3839 octets if not
+#	set)
+# DSSS/CCK Mode in 40 MHz: [DSSS_CCK-40] = allowed (not allowed if not set)
+# PSMP support: [PSMP] (disabled if not set)
+# L-SIG TXOP protection support: [LSIG-TXOP-PROT] (disabled if not set)
+#ht_capab=[HT40-][SHORT-GI-20][SHORT-GI-40]
+ht_capab=[SHORT-GI-20]
+
+# Require stations to support HT PHY (reject association if they do not)
+#require_ht=1
+
+# If set non-zero, require stations to perform scans of overlapping
+# channels to test for stations which would be affected by 40 MHz traffic.
+# This parameter sets the interval in seconds between these scans. This
+# is useful only for testing that stations properly set the OBSS interval,
+# since the other parameters in the OBSS scan parameters IE are set to 0.
+#obss_interval=0
+
+##### IEEE 802.11ac related configuration #####################################
+
+# ieee80211ac: Whether IEEE 802.11ac (VHT) is enabled
+# 0 = disabled (default)
+# 1 = enabled
+# Note: You will also need to enable WMM for full VHT functionality.
+#ieee80211ac=1
+
+# vht_capab: VHT capabilities (list of flags)
+#
+# vht_max_mpdu_len: [MAX-MPDU-7991] [MAX-MPDU-11454]
+# Indicates maximum MPDU length
+# 0 = 3895 octets (default)
+# 1 = 7991 octets
+# 2 = 11454 octets
+# 3 = reserved
+#
+# supported_chan_width: [VHT160] [VHT160-80PLUS80]
+# Indicates supported Channel widths
+# 0 = 160 MHz & 80+80 channel widths are not supported (default)
+# 1 = 160 MHz channel width is supported
+# 2 = 160 MHz & 80+80 channel widths are supported
+# 3 = reserved
+#
+# Rx LDPC coding capability: [RXLDPC]
+# Indicates support for receiving LDPC coded pkts
+# 0 = Not supported (default)
+# 1 = Supported
+#
+# Short GI for 80 MHz: [SHORT-GI-80]
+# Indicates short GI support for reception of packets transmitted with TXVECTOR
+# params format equal to VHT and CBW = 80Mhz
+# 0 = Not supported (default)
+# 1 = Supported
+#
+# Short GI for 160 MHz: [SHORT-GI-160]
+# Indicates short GI support for reception of packets transmitted with TXVECTOR
+# params format equal to VHT and CBW = 160Mhz
+# 0 = Not supported (default)
+# 1 = Supported
+#
+# Tx STBC: [TX-STBC-2BY1]
+# Indicates support for the transmission of at least 2x1 STBC
+# 0 = Not supported (default)
+# 1 = Supported
+#
+# Rx STBC: [RX-STBC-1] [RX-STBC-12] [RX-STBC-123] [RX-STBC-1234]
+# Indicates support for the reception of PPDUs using STBC
+# 0 = Not supported (default)
+# 1 = support of one spatial stream
+# 2 = support of one and two spatial streams
+# 3 = support of one, two and three spatial streams
+# 4 = support of one, two, three and four spatial streams
+# 5,6,7 = reserved
+#
+# SU Beamformer Capable: [SU-BEAMFORMER]
+# Indicates support for operation as a single user beamformer
+# 0 = Not supported (default)
+# 1 = Supported
+#
+# SU Beamformee Capable: [SU-BEAMFORMEE]
+# Indicates support for operation as a single user beamformee
+# 0 = Not supported (default)
+# 1 = Supported
+#
+# Compressed Steering Number of Beamformer Antennas Supported: [BF-ANTENNA-2]
+#   Beamformee's capability indicating the maximum number of beamformer
+#   antennas the beamformee can support when sending compressed beamforming
+#   feedback
+# If SU beamformer capable, set to maximum value minus 1
+# else reserved (default)
+#
+# Number of Sounding Dimensions: [SOUNDING-DIMENSION-2]
+# Beamformer's capability indicating the maximum value of the NUM_STS parameter
+# in the TXVECTOR of a VHT NDP
+# If SU beamformer capable, set to maximum value minus 1
+# else reserved (default)
+#
+# MU Beamformer Capable: [MU-BEAMFORMER]
+# Indicates support for operation as an MU beamformer
+# 0 = Not supported or sent by Non-AP STA (default)
+# 1 = Supported
+#
+# MU Beamformee Capable: [MU-BEAMFORMEE]
+# Indicates support for operation as an MU beamformee
+# 0 = Not supported or sent by AP (default)
+# 1 = Supported
+#
+# VHT TXOP PS: [VHT-TXOP-PS]
+# Indicates whether or not the AP supports VHT TXOP Power Save Mode
+#  or whether or not the STA is in VHT TXOP Power Save mode
+# 0 = VHT AP doesnt support VHT TXOP PS mode (OR) VHT Sta not in VHT TXOP PS
+#  mode
+# 1 = VHT AP supports VHT TXOP PS mode (OR) VHT Sta is in VHT TXOP power save
+#  mode
+#
+# +HTC-VHT Capable: [HTC-VHT]
+# Indicates whether or not the STA supports receiving a VHT variant HT Control
+# field.
+# 0 = Not supported (default)
+# 1 = supported
+#
+# Maximum A-MPDU Length Exponent: [MAX-A-MPDU-LEN-EXP0]..[MAX-A-MPDU-LEN-EXP7]
+# Indicates the maximum length of A-MPDU pre-EOF padding that the STA can recv
+# This field is an integer in the range of 0 to 7.
+# The length defined by this field is equal to
+# 2 pow(13 + Maximum A-MPDU Length Exponent) -1 octets
+#
+# VHT Link Adaptation Capable: [VHT-LINK-ADAPT2] [VHT-LINK-ADAPT3]
+# Indicates whether or not the STA supports link adaptation using VHT variant
+# HT Control field
+# If +HTC-VHTcapable is 1
+#  0 = (no feedback) if the STA does not provide VHT MFB (default)
+#  1 = reserved
+#  2 = (Unsolicited) if the STA provides only unsolicited VHT MFB
+#  3 = (Both) if the STA can provide VHT MFB in response to VHT MRQ and if the
+#      STA provides unsolicited VHT MFB
+# Reserved if +HTC-VHTcapable is 0
+#
+# Rx Antenna Pattern Consistency: [RX-ANTENNA-PATTERN]
+# Indicates the possibility of Rx antenna pattern change
+# 0 = Rx antenna pattern might change during the lifetime of an association
+# 1 = Rx antenna pattern does not change during the lifetime of an association
+#
+# Tx Antenna Pattern Consistency: [TX-ANTENNA-PATTERN]
+# Indicates the possibility of Tx antenna pattern change
+# 0 = Tx antenna pattern might change during the lifetime of an association
+# 1 = Tx antenna pattern does not change during the lifetime of an association
+#vht_capab=[SHORT-GI-80][HTC-VHT]
+#
+# Require stations to support VHT PHY (reject association if they do not)
+#require_vht=1
+
+# 0 = 20 or 40 MHz operating Channel width
+# 1 = 80 MHz channel width
+# 2 = 160 MHz channel width
+# 3 = 80+80 MHz channel width
+#vht_oper_chwidth=1
+#
+# center freq = 5 GHz + (5 * index)
+# So index 42 gives center freq 5.210 GHz
+# which is channel 42 in 5G band
+#
+#vht_oper_centr_freq_seg0_idx=42
+#
+# center freq = 5 GHz + (5 * index)
+# So index 159 gives center freq 5.795 GHz
+# which is channel 159 in 5G band
+#
+#vht_oper_centr_freq_seg1_idx=159
+
+##### IEEE 802.1X-2004 related configuration ##################################
+
+# Require IEEE 802.1X authorization
+#ieee8021x=1
+
+# IEEE 802.1X/EAPOL version
+# hostapd is implemented based on IEEE Std 802.1X-2004 which defines EAPOL
+# version 2. However, there are many client implementations that do not handle
+# the new version number correctly (they seem to drop the frames completely).
+# In order to make hostapd interoperate with these clients, the version number
+# can be set to the older version (1) with this configuration value.
+#eapol_version=2
+
+# Optional displayable message sent with EAP Request-Identity. The first \0
+# in this string will be converted to ASCII-0 (nul). This can be used to
+# separate network info (comma separated list of attribute=value pairs); see,
+# e.g., RFC 4284.
+#eap_message=hello
+#eap_message=hello\0networkid=netw,nasid=foo,portid=0,NAIRealms=example.com
+
+# WEP rekeying (disabled if key lengths are not set or are set to 0)
+# Key lengths for default/broadcast and individual/unicast keys:
+# 5 = 40-bit WEP (also known as 64-bit WEP with 40 secret bits)
+# 13 = 104-bit WEP (also known as 128-bit WEP with 104 secret bits)
+#wep_key_len_broadcast=5
+#wep_key_len_unicast=5
+# Rekeying period in seconds. 0 = do not rekey (i.e., set keys only once)
+#wep_rekey_period=300
+
+# EAPOL-Key index workaround (set bit7) for WinXP Supplicant (needed only if
+# only broadcast keys are used)
+eapol_key_index_workaround=0
+
+# EAP reauthentication period in seconds (default: 3600 seconds; 0 = disable
+# reauthentication).
+#eap_reauth_period=3600
+
+# Use PAE group address (01:80:c2:00:00:03) instead of individual target
+# address when sending EAPOL frames with driver=wired. This is the most common
+# mechanism used in wired authentication, but it also requires that the port
+# is only used by one station.
+#use_pae_group_addr=1
+
+##### Integrated EAP server ###################################################
+
+# Optionally, hostapd can be configured to use an integrated EAP server
+# to process EAP authentication locally without need for an external RADIUS
+# server. This functionality can be used both as a local authentication server
+# for IEEE 802.1X/EAPOL and as a RADIUS server for other devices.
+
+# Use integrated EAP server instead of external RADIUS authentication
+# server. This is also needed if hostapd is configured to act as a RADIUS
+# authentication server.
+eap_server=0
+
+# Path for EAP server user database
+# If SQLite support is included, this can be set to "sqlite:/path/to/sqlite.db"
+# to use SQLite database instead of a text file.
+#eap_user_file=/etc/hostapd.eap_user
+
+# CA certificate (PEM or DER file) for EAP-TLS/PEAP/TTLS
+#ca_cert=/etc/hostapd.ca.pem
+
+# Server certificate (PEM or DER file) for EAP-TLS/PEAP/TTLS
+#server_cert=/etc/hostapd.server.pem
+
+# Private key matching with the server certificate for EAP-TLS/PEAP/TTLS
+# This may point to the same file as server_cert if both certificate and key
+# are included in a single file. PKCS#12 (PFX) file (.p12/.pfx) can also be
+# used by commenting out server_cert and specifying the PFX file as the
+# private_key.
+#private_key=/etc/hostapd.server.prv
+
+# Passphrase for private key
+#private_key_passwd=secret passphrase
+
+# Server identity
+# EAP methods that provide mechanism for authenticated server identity delivery
+# use this value. If not set, "hostapd" is used as a default.
+#server_id=server.example.com
+
+# Enable CRL verification.
+# Note: hostapd does not yet support CRL downloading based on CDP. Thus, a
+# valid CRL signed by the CA is required to be included in the ca_cert file.
+# This can be done by using PEM format for CA certificate and CRL and
+# concatenating these into one file. Whenever CRL changes, hostapd needs to be
+# restarted to take the new CRL into use.
+# 0 = do not verify CRLs (default)
+# 1 = check the CRL of the user certificate
+# 2 = check all CRLs in the certificate path
+#check_crl=1
+
+# Cached OCSP stapling response (DER encoded)
+# If set, this file is sent as a certificate status response by the EAP server
+# if the EAP peer requests certificate status in the ClientHello message.
+# This cache file can be updated, e.g., by running following command
+# periodically to get an update from the OCSP responder:
+# openssl ocsp \
+#	-no_nonce \
+#	-CAfile /etc/hostapd.ca.pem \
+#	-issuer /etc/hostapd.ca.pem \
+#	-cert /etc/hostapd.server.pem \
+#	-url http://ocsp.example.com:8888/ \
+#	-respout /tmp/ocsp-cache.der
+#ocsp_stapling_response=/tmp/ocsp-cache.der
+
+# dh_file: File path to DH/DSA parameters file (in PEM format)
+# This is an optional configuration file for setting parameters for an
+# ephemeral DH key exchange. In most cases, the default RSA authentication does
+# not use this configuration. However, it is possible setup RSA to use
+# ephemeral DH key exchange. In addition, ciphers with DSA keys always use
+# ephemeral DH keys. This can be used to achieve forward secrecy. If the file
+# is in DSA parameters format, it will be automatically converted into DH
+# params. This parameter is required if anonymous EAP-FAST is used.
+# You can generate DH parameters file with OpenSSL, e.g.,
+# "openssl dhparam -out /etc/hostapd.dh.pem 1024"
+#dh_file=/etc/hostapd.dh.pem
+
+# Fragment size for EAP methods
+#fragment_size=1400
+
+# Finite cyclic group for EAP-pwd. Number maps to group of domain parameters
+# using the IANA repository for IKE (RFC 2409).
+#pwd_group=19
+
+# Configuration data for EAP-SIM database/authentication gateway interface.
+# This is a text string in implementation specific format. The example
+# implementation in eap_sim_db.c uses this as the UNIX domain socket name for
+# the HLR/AuC gateway (e.g., hlr_auc_gw). In this case, the path uses "unix:"
+# prefix. If hostapd is built with SQLite support (CONFIG_SQLITE=y in .config),
+# database file can be described with an optional db=<path> parameter.
+#eap_sim_db=unix:/tmp/hlr_auc_gw.sock
+#eap_sim_db=unix:/tmp/hlr_auc_gw.sock db=/tmp/hostapd.db
+
+# Encryption key for EAP-FAST PAC-Opaque values. This key must be a secret,
+# random value. It is configured as a 16-octet value in hex format. It can be
+# generated, e.g., with the following command:
+# od -tx1 -v -N16 /dev/random | colrm 1 8 | tr -d ' '
+#pac_opaque_encr_key=000102030405060708090a0b0c0d0e0f
+
+# EAP-FAST authority identity (A-ID)
+# A-ID indicates the identity of the authority that issues PACs. The A-ID
+# should be unique across all issuing servers. In theory, this is a variable
+# length field, but due to some existing implementations requiring A-ID to be
+# 16 octets in length, it is strongly recommended to use that length for the
+# field to provid interoperability with deployed peer implementations. This
+# field is configured in hex format.
+#eap_fast_a_id=101112131415161718191a1b1c1d1e1f
+
+# EAP-FAST authority identifier information (A-ID-Info)
+# This is a user-friendly name for the A-ID. For example, the enterprise name
+# and server name in a human-readable format. This field is encoded as UTF-8.
+#eap_fast_a_id_info=test server
+
+# Enable/disable different EAP-FAST provisioning modes:
+#0 = provisioning disabled
+#1 = only anonymous provisioning allowed
+#2 = only authenticated provisioning allowed
+#3 = both provisioning modes allowed (default)
+#eap_fast_prov=3
+
+# EAP-FAST PAC-Key lifetime in seconds (hard limit)
+#pac_key_lifetime=604800
+
+# EAP-FAST PAC-Key refresh time in seconds (soft limit on remaining hard
+# limit). The server will generate a new PAC-Key when this number of seconds
+# (or fewer) of the lifetime remains.
+#pac_key_refresh_time=86400
+
+# EAP-SIM and EAP-AKA protected success/failure indication using AT_RESULT_IND
+# (default: 0 = disabled).
+#eap_sim_aka_result_ind=1
+
+# Trusted Network Connect (TNC)
+# If enabled, TNC validation will be required before the peer is allowed to
+# connect. Note: This is only used with EAP-TTLS and EAP-FAST. If any other
+# EAP method is enabled, the peer will be allowed to connect without TNC.
+#tnc=1
+
+
+##### IEEE 802.11f - Inter-Access Point Protocol (IAPP) #######################
+
+# Interface to be used for IAPP broadcast packets
+#iapp_interface=eth0
+
+
+##### RADIUS client configuration #############################################
+# for IEEE 802.1X with external Authentication Server, IEEE 802.11
+# authentication with external ACL for MAC addresses, and accounting
+
+# The own IP address of the access point (used as NAS-IP-Address)
+own_ip_addr=127.0.0.1
+
+# Optional NAS-Identifier string for RADIUS messages. When used, this should be
+# a unique to the NAS within the scope of the RADIUS server. For example, a
+# fully qualified domain name can be used here.
+# When using IEEE 802.11r, nas_identifier must be set and must be between 1 and
+# 48 octets long.
+#nas_identifier=ap.example.com
+
+# RADIUS authentication server
+#auth_server_addr=127.0.0.1
+#auth_server_port=1812
+#auth_server_shared_secret=secret
+
+# RADIUS accounting server
+#acct_server_addr=127.0.0.1
+#acct_server_port=1813
+#acct_server_shared_secret=secret
+
+# Secondary RADIUS servers; to be used if primary one does not reply to
+# RADIUS packets. These are optional and there can be more than one secondary
+# server listed.
+#auth_server_addr=127.0.0.2
+#auth_server_port=1812
+#auth_server_shared_secret=secret2
+#
+#acct_server_addr=127.0.0.2
+#acct_server_port=1813
+#acct_server_shared_secret=secret2
+
+# Retry interval for trying to return to the primary RADIUS server (in
+# seconds). RADIUS client code will automatically try to use the next server
+# when the current server is not replying to requests. If this interval is set,
+# primary server will be retried after configured amount of time even if the
+# currently used secondary server is still working.
+#radius_retry_primary_interval=600
+
+
+# Interim accounting update interval
+# If this is set (larger than 0) and acct_server is configured, hostapd will
+# send interim accounting updates every N seconds. Note: if set, this overrides
+# possible Acct-Interim-Interval attribute in Access-Accept message. Thus, this
+# value should not be configured in hostapd.conf, if RADIUS server is used to
+# control the interim interval.
+# This value should not be less 600 (10 minutes) and must not be less than
+# 60 (1 minute).
+#radius_acct_interim_interval=600
+
+# Request Chargeable-User-Identity (RFC 4372)
+# This parameter can be used to configure hostapd to request CUI from the
+# RADIUS server by including Chargeable-User-Identity attribute into
+# Access-Request packets.
+#radius_request_cui=1
+
+# Dynamic VLAN mode; allow RADIUS authentication server to decide which VLAN
+# is used for the stations. This information is parsed from following RADIUS
+# attributes based on RFC 3580 and RFC 2868: Tunnel-Type (value 13 = VLAN),
+# Tunnel-Medium-Type (value 6 = IEEE 802), Tunnel-Private-Group-ID (value
+# VLANID as a string). Optionally, the local MAC ACL list (accept_mac_file) can
+# be used to set static client MAC address to VLAN ID mapping.
+# 0 = disabled (default)
+# 1 = option; use default interface if RADIUS server does not include VLAN ID
+# 2 = required; reject authentication if RADIUS server does not include VLAN ID
+#dynamic_vlan=0
+
+# VLAN interface list for dynamic VLAN mode is read from a separate text file.
+# This list is used to map VLAN ID from the RADIUS server to a network
+# interface. Each station is bound to one interface in the same way as with
+# multiple BSSIDs or SSIDs. Each line in this text file is defining a new
+# interface and the line must include VLAN ID and interface name separated by
+# white space (space or tab).
+# If no entries are provided by this file, the station is statically mapped
+# to <bss-iface>.<vlan-id> interfaces.
+#vlan_file=/etc/hostapd.vlan
+
+# Interface where 802.1q tagged packets should appear when a RADIUS server is
+# used to determine which VLAN a station is on.  hostapd creates a bridge for
+# each VLAN.  Then hostapd adds a VLAN interface (associated with the interface
+# indicated by 'vlan_tagged_interface') and the appropriate wireless interface
+# to the bridge.
+#vlan_tagged_interface=eth0
+
+# Bridge (prefix) to add the wifi and the tagged interface to. This gets the
+# VLAN ID appended. It defaults to brvlan%d if no tagged interface is given
+# and br%s.%d if a tagged interface is given, provided %s = tagged interface
+# and %d = VLAN ID.
+#vlan_bridge=brvlan
+
+# When hostapd creates a VLAN interface on vlan_tagged_interfaces, it needs
+# to know how to name it.
+# 0 = vlan<XXX>, e.g., vlan1
+# 1 = <vlan_tagged_interface>.<XXX>, e.g. eth0.1
+#vlan_naming=0
+
+# Arbitrary RADIUS attributes can be added into Access-Request and
+# Accounting-Request packets by specifying the contents of the attributes with
+# the following configuration parameters. There can be multiple of these to
+# add multiple attributes. These parameters can also be used to override some
+# of the attributes added automatically by hostapd.
+# Format: <attr_id>[:<syntax:value>]
+# attr_id: RADIUS attribute type (e.g., 26 = Vendor-Specific)
+# syntax: s = string (UTF-8), d = integer, x = octet string
+# value: attribute value in format indicated by the syntax
+# If syntax and value parts are omitted, a null value (single 0x00 octet) is
+# used.
+#
+# Additional Access-Request attributes
+# radius_auth_req_attr=<attr_id>[:<syntax:value>]
+# Examples:
+# Operator-Name = "Operator"
+#radius_auth_req_attr=126:s:Operator
+# Service-Type = Framed (2)
+#radius_auth_req_attr=6:d:2
+# Connect-Info = "testing" (this overrides the automatically generated value)
+#radius_auth_req_attr=77:s:testing
+# Same Connect-Info value set as a hexdump
+#radius_auth_req_attr=77:x:74657374696e67
+
+#
+# Additional Accounting-Request attributes
+# radius_acct_req_attr=<attr_id>[:<syntax:value>]
+# Examples:
+# Operator-Name = "Operator"
+#radius_acct_req_attr=126:s:Operator
+
+# Dynamic Authorization Extensions (RFC 5176)
+# This mechanism can be used to allow dynamic changes to user session based on
+# commands from a RADIUS server (or some other disconnect client that has the
+# needed session information). For example, Disconnect message can be used to
+# request an associated station to be disconnected.
+#
+# This is disabled by default. Set radius_das_port to non-zero UDP port
+# number to enable.
+#radius_das_port=3799
+#
+# DAS client (the host that can send Disconnect/CoA requests) and shared secret
+#radius_das_client=192.168.1.123 shared secret here
+#
+# DAS Event-Timestamp time window in seconds
+#radius_das_time_window=300
+#
+# DAS require Event-Timestamp
+#radius_das_require_event_timestamp=1
+
+##### RADIUS authentication server configuration ##############################
+
+# hostapd can be used as a RADIUS authentication server for other hosts. This
+# requires that the integrated EAP server is also enabled and both
+# authentication services are sharing the same configuration.
+
+# File name of the RADIUS clients configuration for the RADIUS server. If this
+# commented out, RADIUS server is disabled.
+#radius_server_clients=/etc/hostapd.radius_clients
+
+# The UDP port number for the RADIUS authentication server
+#radius_server_auth_port=1812
+
+# Use IPv6 with RADIUS server (IPv4 will also be supported using IPv6 API)
+#radius_server_ipv6=1
+
+
+##### WPA/IEEE 802.11i configuration ##########################################
+
+# Enable WPA. Setting this variable configures the AP to require WPA (either
+# WPA-PSK or WPA-RADIUS/EAP based on other configuration). For WPA-PSK, either
+# wpa_psk or wpa_passphrase must be set and wpa_key_mgmt must include WPA-PSK.
+# Instead of wpa_psk / wpa_passphrase, wpa_psk_radius might suffice.
+# For WPA-RADIUS/EAP, ieee8021x must be set (but without dynamic WEP keys),
+# RADIUS authentication server must be configured, and WPA-EAP must be included
+# in wpa_key_mgmt.
+# This field is a bit field that can be used to enable WPA (IEEE 802.11i/D3.0)
+# and/or WPA2 (full IEEE 802.11i/RSN):
+# bit0 = WPA
+# bit1 = IEEE 802.11i/RSN (WPA2) (dot11RSNAEnabled)
+#wpa=1
+
+# WPA pre-shared keys for WPA-PSK. This can be either entered as a 256-bit
+# secret in hex format (64 hex digits), wpa_psk, or as an ASCII passphrase
+# (8..63 characters) that will be converted to PSK. This conversion uses SSID
+# so the PSK changes when ASCII passphrase is used and the SSID is changed.
+# wpa_psk (dot11RSNAConfigPSKValue)
+# wpa_passphrase (dot11RSNAConfigPSKPassPhrase)
+#wpa_psk=0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef
+#wpa_passphrase=secret passphrase
+
+# Optionally, WPA PSKs can be read from a separate text file (containing list
+# of (PSK,MAC address) pairs. This allows more than one PSK to be configured.
+# Use absolute path name to make sure that the files can be read on SIGHUP
+# configuration reloads.
+#wpa_psk_file=/etc/hostapd.wpa_psk
+
+# Optionally, WPA passphrase can be received from RADIUS authentication server
+# This requires macaddr_acl to be set to 2 (RADIUS)
+# 0 = disabled (default)
+# 1 = optional; use default passphrase/psk if RADIUS server does not include
+#	Tunnel-Password
+# 2 = required; reject authentication if RADIUS server does not include
+#	Tunnel-Password
+#wpa_psk_radius=0
+
+# Set of accepted key management algorithms (WPA-PSK, WPA-EAP, or both). The
+# entries are separated with a space. WPA-PSK-SHA256 and WPA-EAP-SHA256 can be
+# added to enable SHA256-based stronger algorithms.
+# (dot11RSNAConfigAuthenticationSuitesTable)
+#wpa_key_mgmt=WPA-PSK WPA-EAP
+
+# Set of accepted cipher suites (encryption algorithms) for pairwise keys
+# (unicast packets). This is a space separated list of algorithms:
+# CCMP = AES in Counter mode with CBC-MAC [RFC 3610, IEEE 802.11i/D7.0]
+# TKIP = Temporal Key Integrity Protocol [IEEE 802.11i/D7.0]
+# Group cipher suite (encryption algorithm for broadcast and multicast frames)
+# is automatically selected based on this configuration. If only CCMP is
+# allowed as the pairwise cipher, group cipher will also be CCMP. Otherwise,
+# TKIP will be used as the group cipher.
+# (dot11RSNAConfigPairwiseCiphersTable)
+# Pairwise cipher for WPA (v1) (default: TKIP)
+#wpa_pairwise=TKIP CCMP
+# Pairwise cipher for RSN/WPA2 (default: use wpa_pairwise value)
+#rsn_pairwise=CCMP
+
+# Time interval for rekeying GTK (broadcast/multicast encryption keys) in
+# seconds. (dot11RSNAConfigGroupRekeyTime)
+#wpa_group_rekey=600
+
+# Rekey GTK when any STA that possesses the current GTK is leaving the BSS.
+# (dot11RSNAConfigGroupRekeyStrict)
+#wpa_strict_rekey=1
+
+# Time interval for rekeying GMK (master key used internally to generate GTKs
+# (in seconds).
+#wpa_gmk_rekey=86400
+
+# Maximum lifetime for PTK in seconds. This can be used to enforce rekeying of
+# PTK to mitigate some attacks against TKIP deficiencies.
+#wpa_ptk_rekey=600
+
+# Enable IEEE 802.11i/RSN/WPA2 pre-authentication. This is used to speed up
+# roaming be pre-authenticating IEEE 802.1X/EAP part of the full RSN
+# authentication and key handshake before actually associating with a new AP.
+# (dot11RSNAPreauthenticationEnabled)
+#rsn_preauth=1
+#
+# Space separated list of interfaces from which pre-authentication frames are
+# accepted (e.g., 'eth0' or 'eth0 wlan0wds0'. This list should include all
+# interface that are used for connections to other APs. This could include
+# wired interfaces and WDS links. The normal wireless data interface towards
+# associated stations (e.g., wlan0) should not be added, since
+# pre-authentication is only used with APs other than the currently associated
+# one.
+#rsn_preauth_interfaces=eth0
+
+# peerkey: Whether PeerKey negotiation for direct links (IEEE 802.11e) is
+# allowed. This is only used with RSN/WPA2.
+# 0 = disabled (default)
+# 1 = enabled
+#peerkey=1
+
+# ieee80211w: Whether management frame protection (MFP) is enabled
+# 0 = disabled (default)
+# 1 = optional
+# 2 = required
+#ieee80211w=0
+
+# Association SA Query maximum timeout (in TU = 1.024 ms; for MFP)
+# (maximum time to wait for a SA Query response)
+# dot11AssociationSAQueryMaximumTimeout, 1...4294967295
+#assoc_sa_query_max_timeout=1000
+
+# Association SA Query retry timeout (in TU = 1.024 ms; for MFP)
+# (time between two subsequent SA Query requests)
+# dot11AssociationSAQueryRetryTimeout, 1...4294967295
+#assoc_sa_query_retry_timeout=201
+
+# disable_pmksa_caching: Disable PMKSA caching
+# This parameter can be used to disable caching of PMKSA created through EAP
+# authentication. RSN preauthentication may still end up using PMKSA caching if
+# it is enabled (rsn_preauth=1).
+# 0 = PMKSA caching enabled (default)
+# 1 = PMKSA caching disabled
+#disable_pmksa_caching=0
+
+# okc: Opportunistic Key Caching (aka Proactive Key Caching)
+# Allow PMK cache to be shared opportunistically among configured interfaces
+# and BSSes (i.e., all configurations within a single hostapd process).
+# 0 = disabled (default)
+# 1 = enabled
+#okc=1
+
+# SAE threshold for anti-clogging mechanism (dot11RSNASAEAntiCloggingThreshold)
+# This parameter defines how many open SAE instances can be in progress at the
+# same time before the anti-clogging mechanism is taken into use.
+#sae_anti_clogging_threshold=5
+
+# Enabled SAE finite cyclic groups
+# SAE implementation are required to support group 19 (ECC group defined over a
+# 256-bit prime order field). All groups that are supported by the
+# implementation are enabled by default. This configuration parameter can be
+# used to specify a limited set of allowed groups. The group values are listed
+# in the IANA registry:
+# http://www.iana.org/assignments/ipsec-registry/ipsec-registry.xml#ipsec-registry-9
+#sae_groups=19 20 21 25 26
+
+##### IEEE 802.11r configuration ##############################################
+
+# Mobility Domain identifier (dot11FTMobilityDomainID, MDID)
+# MDID is used to indicate a group of APs (within an ESS, i.e., sharing the
+# same SSID) between which a STA can use Fast BSS Transition.
+# 2-octet identifier as a hex string.
+#mobility_domain=a1b2
+
+# PMK-R0 Key Holder identifier (dot11FTR0KeyHolderID)
+# 1 to 48 octet identifier.
+# This is configured with nas_identifier (see RADIUS client section above).
+
+# Default lifetime of the PMK-RO in minutes; range 1..65535
+# (dot11FTR0KeyLifetime)
+#r0_key_lifetime=10000
+
+# PMK-R1 Key Holder identifier (dot11FTR1KeyHolderID)
+# 6-octet identifier as a hex string.
+#r1_key_holder=000102030405
+
+# Reassociation deadline in time units (TUs / 1.024 ms; range 1000..65535)
+# (dot11FTReassociationDeadline)
+#reassociation_deadline=1000
+
+# List of R0KHs in the same Mobility Domain
+# format: <MAC address> <NAS Identifier> <128-bit key as hex string>
+# This list is used to map R0KH-ID (NAS Identifier) to a destination MAC
+# address when requesting PMK-R1 key from the R0KH that the STA used during the
+# Initial Mobility Domain Association.
+#r0kh=02:01:02:03:04:05 r0kh-1.example.com 000102030405060708090a0b0c0d0e0f
+#r0kh=02:01:02:03:04:06 r0kh-2.example.com 00112233445566778899aabbccddeeff
+# And so on.. One line per R0KH.
+
+# List of R1KHs in the same Mobility Domain
+# format: <MAC address> <R1KH-ID> <128-bit key as hex string>
+# This list is used to map R1KH-ID to a destination MAC address when sending
+# PMK-R1 key from the R0KH. This is also the list of authorized R1KHs in the MD
+# that can request PMK-R1 keys.
+#r1kh=02:01:02:03:04:05 02:11:22:33:44:55 000102030405060708090a0b0c0d0e0f
+#r1kh=02:01:02:03:04:06 02:11:22:33:44:66 00112233445566778899aabbccddeeff
+# And so on.. One line per R1KH.
+
+# Whether PMK-R1 push is enabled at R0KH
+# 0 = do not push PMK-R1 to all configured R1KHs (default)
+# 1 = push PMK-R1 to all configured R1KHs whenever a new PMK-R0 is derived
+#pmk_r1_push=1
+
+##### Neighbor table ##########################################################
+# Maximum number of entries kept in AP table (either for neigbor table or for
+# detecting Overlapping Legacy BSS Condition). The oldest entry will be
+# removed when adding a new entry that would make the list grow over this
+# limit. Note! WFA certification for IEEE 802.11g requires that OLBC is
+# enabled, so this field should not be set to 0 when using IEEE 802.11g.
+# default: 255
+#ap_table_max_size=255
+
+# Number of seconds of no frames received after which entries may be deleted
+# from the AP table. Since passive scanning is not usually performed frequently
+# this should not be set to very small value. In addition, there is no
+# guarantee that every scan cycle will receive beacon frames from the
+# neighboring APs.
+# default: 60
+#ap_table_expiration_time=3600
+
+
+##### Wi-Fi Protected Setup (WPS) #############################################
+
+# WPS state
+# 0 = WPS disabled (default)
+# 1 = WPS enabled, not configured
+# 2 = WPS enabled, configured
+#wps_state=2
+
+# Whether to manage this interface independently from other WPS interfaces
+# By default, a single hostapd process applies WPS operations to all configured
+# interfaces. This parameter can be used to disable that behavior for a subset
+# of interfaces. If this is set to non-zero for an interface, WPS commands
+# issued on that interface do not apply to other interfaces and WPS operations
+# performed on other interfaces do not affect this interface.
+#wps_independent=0
+
+# AP can be configured into a locked state where new WPS Registrar are not
+# accepted, but previously authorized Registrars (including the internal one)
+# can continue to add new Enrollees.
+#ap_setup_locked=1
+
+# Universally Unique IDentifier (UUID; see RFC 4122) of the device
+# This value is used as the UUID for the internal WPS Registrar. If the AP
+# is also using UPnP, this value should be set to the device's UPnP UUID.
+# If not configured, UUID will be generated based on the local MAC address.
+#uuid=12345678-9abc-def0-1234-56789abcdef0
+
+# Note: If wpa_psk_file is set, WPS is used to generate random, per-device PSKs
+# that will be appended to the wpa_psk_file. If wpa_psk_file is not set, the
+# default PSK (wpa_psk/wpa_passphrase) will be delivered to Enrollees. Use of
+# per-device PSKs is recommended as the more secure option (i.e., make sure to
+# set wpa_psk_file when using WPS with WPA-PSK).
+
+# When an Enrollee requests access to the network with PIN method, the Enrollee
+# PIN will need to be entered for the Registrar. PIN request notifications are
+# sent to hostapd ctrl_iface monitor. In addition, they can be written to a
+# text file that could be used, e.g., to populate the AP administration UI with
+# pending PIN requests. If the following variable is set, the PIN requests will
+# be written to the configured file.
+#wps_pin_requests=/var/run/hostapd_wps_pin_requests
+
+# Device Name
+# User-friendly description of device; up to 32 octets encoded in UTF-8
+#device_name=Wireless AP
+
+# Manufacturer
+# The manufacturer of the device (up to 64 ASCII characters)
+#manufacturer=Company
+
+# Model Name
+# Model of the device (up to 32 ASCII characters)
+#model_name=WAP
+
+# Model Number
+# Additional device description (up to 32 ASCII characters)
+#model_number=123
+
+# Serial Number
+# Serial number of the device (up to 32 characters)
+#serial_number=12345
+
+# Primary Device Type
+# Used format: <categ>-<OUI>-<subcateg>
+# categ = Category as an integer value
+# OUI = OUI and type octet as a 4-octet hex-encoded value; 0050F204 for
+#       default WPS OUI
+# subcateg = OUI-specific Sub Category as an integer value
+# Examples:
+#   1-0050F204-1 (Computer / PC)
+#   1-0050F204-2 (Computer / Server)
+#   5-0050F204-1 (Storage / NAS)
+#   6-0050F204-1 (Network Infrastructure / AP)
+#device_type=6-0050F204-1
+
+# OS Version
+# 4-octet operating system version number (hex string)
+#os_version=01020300
+
+# Config Methods
+# List of the supported configuration methods
+# Available methods: usba ethernet label display ext_nfc_token int_nfc_token
+#	nfc_interface push_button keypad virtual_display physical_display
+#	virtual_push_button physical_push_button
+#config_methods=label virtual_display virtual_push_button keypad
+
+# WPS capability discovery workaround for PBC with Windows 7
+# Windows 7 uses incorrect way of figuring out AP's WPS capabilities by acting
+# as a Registrar and using M1 from the AP. The config methods attribute in that
+# message is supposed to indicate only the configuration method supported by
+# the AP in Enrollee role, i.e., to add an external Registrar. For that case,
+# PBC shall not be used and as such, the PushButton config method is removed
+# from M1 by default. If pbc_in_m1=1 is included in the configuration file,
+# the PushButton config method is left in M1 (if included in config_methods
+# parameter) to allow Windows 7 to use PBC instead of PIN (e.g., from a label
+# in the AP).
+#pbc_in_m1=1
+
+# Static access point PIN for initial configuration and adding Registrars
+# If not set, hostapd will not allow external WPS Registrars to control the
+# access point. The AP PIN can also be set at runtime with hostapd_cli
+# wps_ap_pin command. Use of temporary (enabled by user action) and random
+# AP PIN is much more secure than configuring a static AP PIN here. As such,
+# use of the ap_pin parameter is not recommended if the AP device has means for
+# displaying a random PIN.
+#ap_pin=12345670
+
+# Skip building of automatic WPS credential
+# This can be used to allow the automatically generated Credential attribute to
+# be replaced with pre-configured Credential(s).
+#skip_cred_build=1
+
+# Additional Credential attribute(s)
+# This option can be used to add pre-configured Credential attributes into M8
+# message when acting as a Registrar. If skip_cred_build=1, this data will also
+# be able to override the Credential attribute that would have otherwise been
+# automatically generated based on network configuration. This configuration
+# option points to an external file that much contain the WPS Credential
+# attribute(s) as binary data.
+#extra_cred=hostapd.cred
+
+# Credential processing
+#   0 = process received credentials internally (default)
+#   1 = do not process received credentials; just pass them over ctrl_iface to
+#	external program(s)
+#   2 = process received credentials internally and pass them over ctrl_iface
+#	to external program(s)
+# Note: With wps_cred_processing=1, skip_cred_build should be set to 1 and
+# extra_cred be used to provide the Credential data for Enrollees.
+#
+# wps_cred_processing=1 will disabled automatic updates of hostapd.conf file
+# both for Credential processing and for marking AP Setup Locked based on
+# validation failures of AP PIN. An external program is responsible on updating
+# the configuration appropriately in this case.
+#wps_cred_processing=0
+
+# AP Settings Attributes for M7
+# By default, hostapd generates the AP Settings Attributes for M7 based on the
+# current configuration. It is possible to override this by providing a file
+# with pre-configured attributes. This is similar to extra_cred file format,
+# but the AP Settings attributes are not encapsulated in a Credential
+# attribute.
+#ap_settings=hostapd.ap_settings
+
+# WPS UPnP interface
+# If set, support for external Registrars is enabled.
+#upnp_iface=br0
+
+# Friendly Name (required for UPnP)
+# Short description for end use. Should be less than 64 characters.
+#friendly_name=WPS Access Point
+
+# Manufacturer URL (optional for UPnP)
+#manufacturer_url=http://www.example.com/
+
+# Model Description (recommended for UPnP)
+# Long description for end user. Should be less than 128 characters.
+#model_description=Wireless Access Point
+
+# Model URL (optional for UPnP)
+#model_url=http://www.example.com/model/
+
+# Universal Product Code (optional for UPnP)
+# 12-digit, all-numeric code that identifies the consumer package.
+#upc=123456789012
+
+# WPS RF Bands (a = 5G, b = 2.4G, g = 2.4G, ag = dual band)
+# This value should be set according to RF band(s) supported by the AP if
+# hw_mode is not set. For dual band dual concurrent devices, this needs to be
+# set to ag to allow both RF bands to be advertized.
+#wps_rf_bands=ag
+
+# NFC password token for WPS
+# These parameters can be used to configure a fixed NFC password token for the
+# AP. This can be generated, e.g., with nfc_pw_token from wpa_supplicant. When
+# these parameters are used, the AP is assumed to be deployed with a NFC tag
+# that includes the matching NFC password token (e.g., written based on the
+# NDEF record from nfc_pw_token).
+#
+#wps_nfc_dev_pw_id: Device Password ID (16..65535)
+#wps_nfc_dh_pubkey: Hexdump of DH Public Key
+#wps_nfc_dh_privkey: Hexdump of DH Private Key
+#wps_nfc_dev_pw: Hexdump of Device Password
+
+##### Wi-Fi Direct (P2P) ######################################################
+
+# Enable P2P Device management
+#manage_p2p=1
+
+# Allow cross connection
+#allow_cross_connection=1
+
+#### TDLS (IEEE 802.11z-2010) #################################################
+
+# Prohibit use of TDLS in this BSS
+#tdls_prohibit=1
+
+# Prohibit use of TDLS Channel Switching in this BSS
+#tdls_prohibit_chan_switch=1
+
+##### IEEE 802.11v-2011 #######################################################
+
+# Time advertisement
+# 0 = disabled (default)
+# 2 = UTC time at which the TSF timer is 0
+#time_advertisement=2
+
+# Local time zone as specified in 8.3 of IEEE Std 1003.1-2004:
+# stdoffset[dst[offset][,start[/time],end[/time]]]
+#time_zone=EST5
+
+# WNM-Sleep Mode (extended sleep mode for stations)
+# 0 = disabled (default)
+# 1 = enabled (allow stations to use WNM-Sleep Mode)
+#wnm_sleep_mode=1
+
+# BSS Transition Management
+# 0 = disabled (default)
+# 1 = enabled
+#bss_transition=1
+
+##### IEEE 802.11u-2011 #######################################################
+
+# Enable Interworking service
+#interworking=1
+
+# Access Network Type
+# 0 = Private network
+# 1 = Private network with guest access
+# 2 = Chargeable public network
+# 3 = Free public network
+# 4 = Personal device network
+# 5 = Emergency services only network
+# 14 = Test or experimental
+# 15 = Wildcard
+#access_network_type=0
+
+# Whether the network provides connectivity to the Internet
+# 0 = Unspecified
+# 1 = Network provides connectivity to the Internet
+#internet=1
+
+# Additional Step Required for Access
+# Note: This is only used with open network, i.e., ASRA shall ne set to 0 if
+# RSN is used.
+#asra=0
+
+# Emergency services reachable
+#esr=0
+
+# Unauthenticated emergency service accessible
+#uesa=0
+
+# Venue Info (optional)
+# The available values are defined in IEEE Std 802.11u-2011, 7.3.1.34.
+# Example values (group,type):
+# 0,0 = Unspecified
+# 1,7 = Convention Center
+# 1,13 = Coffee Shop
+# 2,0 = Unspecified Business
+# 7,1  Private Residence
+#venue_group=7
+#venue_type=1
+
+# Homogeneous ESS identifier (optional; dot11HESSID)
+# If set, this shall be identifical to one of the BSSIDs in the homogeneous
+# ESS and this shall be set to the same value across all BSSs in homogeneous
+# ESS.
+#hessid=02:03:04:05:06:07
+
+# Roaming Consortium List
+# Arbitrary number of Roaming Consortium OIs can be configured with each line
+# adding a new OI to the list. The first three entries are available through
+# Beacon and Probe Response frames. Any additional entry will be available only
+# through ANQP queries. Each OI is between 3 and 15 octets and is configured as
+# a hexstring.
+#roaming_consortium=021122
+#roaming_consortium=2233445566
+
+# Venue Name information
+# This parameter can be used to configure one or more Venue Name Duples for
+# Venue Name ANQP information. Each entry has a two or three character language
+# code (ISO-639) separated by colon from the venue name string.
+# Note that venue_group and venue_type have to be set for Venue Name
+# information to be complete.
+#venue_name=eng:Example venue
+#venue_name=fin:Esimerkkipaikka
+# Alternative format for language:value strings:
+# (double quoted string, printf-escaped string)
+#venue_name=P"eng:Example\nvenue"
+
+# Network Authentication Type
+# This parameter indicates what type of network authentication is used in the
+# network.
+# format: <network auth type indicator (1-octet hex str)> [redirect URL]
+# Network Authentication Type Indicator values:
+# 00 = Acceptance of terms and conditions
+# 01 = On-line enrollment supported
+# 02 = http/https redirection
+# 03 = DNS redirection
+#network_auth_type=00
+#network_auth_type=02http://www.example.com/redirect/me/here/
+
+# IP Address Type Availability
+# format: <1-octet encoded value as hex str>
+# (ipv4_type & 0x3f) << 2 | (ipv6_type & 0x3)
+# ipv4_type:
+# 0 = Address type not available
+# 1 = Public IPv4 address available
+# 2 = Port-restricted IPv4 address available
+# 3 = Single NATed private IPv4 address available
+# 4 = Double NATed private IPv4 address available
+# 5 = Port-restricted IPv4 address and single NATed IPv4 address available
+# 6 = Port-restricted IPv4 address and double NATed IPv4 address available
+# 7 = Availability of the address type is not known
+# ipv6_type:
+# 0 = Address type not available
+# 1 = Address type available
+# 2 = Availability of the address type not known
+#ipaddr_type_availability=14
+
+# Domain Name
+# format: <variable-octet str>[,<variable-octet str>]
+#domain_name=example.com,another.example.com,yet-another.example.com
+
+# 3GPP Cellular Network information
+# format: <MCC1,MNC1>[;<MCC2,MNC2>][;...]
+#anqp_3gpp_cell_net=244,91;310,026;234,56
+
+# NAI Realm information
+# One or more realm can be advertised. Each nai_realm line adds a new realm to
+# the set. These parameters provide information for stations using Interworking
+# network selection to allow automatic connection to a network based on
+# credentials.
+# format: <encoding>,<NAI Realm(s)>[,<EAP Method 1>][,<EAP Method 2>][,...]
+# encoding:
+#	0 = Realm formatted in accordance with IETF RFC 4282
+#	1 = UTF-8 formatted character string that is not formatted in
+#	    accordance with IETF RFC 4282
+# NAI Realm(s): Semi-colon delimited NAI Realm(s)
+# EAP Method: <EAP Method>[:<[AuthParam1:Val1]>][<[AuthParam2:Val2]>][...]
+# AuthParam (Table 8-188 in IEEE Std 802.11-2012):
+# ID 2 = Non-EAP Inner Authentication Type
+#	1 = PAP, 2 = CHAP, 3 = MSCHAP, 4 = MSCHAPV2
+# ID 3 = Inner authentication EAP Method Type
+# ID 5 = Credential Type
+#	1 = SIM, 2 = USIM, 3 = NFC Secure Element, 4 = Hardware Token,
+#	5 = Softoken, 6 = Certificate, 7 = username/password, 9 = Anonymous,
+#	10 = Vendor Specific
+#nai_realm=0,example.com;example.net
+# EAP methods EAP-TLS with certificate and EAP-TTLS/MSCHAPv2 with
+# username/password
+#nai_realm=0,example.org,13[5:6],21[2:4][5:7]
+
+# QoS Map Set configuration
+#
+# Comma delimited QoS Map Set in decimal values
+# (see IEEE Std 802.11-2012, 8.4.2.97)
+#
+# format:
+# [<DSCP Exceptions[DSCP,UP]>,]<UP 0 range[low,high]>,...<UP 7 range[low,high]>
+#
+# There can be up to 21 optional DSCP Exceptions which are pairs of DSCP Value
+# (0..63 or 255) and User Priority (0..7). This is followed by eight DSCP Range
+# descriptions with DSCP Low Value and DSCP High Value pairs (0..63 or 255) for
+# each UP starting from 0. If both low and high value are set to 255, the
+# corresponding UP is not used.
+#
+# default: not set
+#qos_map_set=53,2,22,6,8,15,0,7,255,255,16,31,32,39,255,255,40,47,255,255
+
+##### Hotspot 2.0 #############################################################
+
+# Enable Hotspot 2.0 support
+#hs20=1
+
+# Disable Downstream Group-Addressed Forwarding (DGAF)
+# This can be used to configure a network where no group-addressed frames are
+# allowed. The AP will not forward any group-address frames to the stations and
+# random GTKs are issued for each station to prevent associated stations from
+# forging such frames to other stations in the BSS.
+#disable_dgaf=1
+
+# Operator Friendly Name
+# This parameter can be used to configure one or more Operator Friendly Name
+# Duples. Each entry has a two or three character language code (ISO-639)
+# separated by colon from the operator friendly name string.
+#hs20_oper_friendly_name=eng:Example operator
+#hs20_oper_friendly_name=fin:Esimerkkioperaattori
+
+# Connection Capability
+# This can be used to advertise what type of IP traffic can be sent through the
+# hotspot (e.g., due to firewall allowing/blocking protocols/ports).
+# format: <IP Protocol>:<Port Number>:<Status>
+# IP Protocol: 1 = ICMP, 6 = TCP, 17 = UDP
+# Port Number: 0..65535
+# Status: 0 = Closed, 1 = Open, 2 = Unknown
+# Each hs20_conn_capab line is added to the list of advertised tuples.
+#hs20_conn_capab=1:0:2
+#hs20_conn_capab=6:22:1
+#hs20_conn_capab=17:5060:0
+
+# WAN Metrics
+# format: <WAN Info>:<DL Speed>:<UL Speed>:<DL Load>:<UL Load>:<LMD>
+# WAN Info: B0-B1: Link Status, B2: Symmetric Link, B3: At Capabity
+#    (encoded as two hex digits)
+#    Link Status: 1 = Link up, 2 = Link down, 3 = Link in test state
+# Downlink Speed: Estimate of WAN backhaul link current downlink speed in kbps;
+#	1..4294967295; 0 = unknown
+# Uplink Speed: Estimate of WAN backhaul link current uplink speed in kbps
+#	1..4294967295; 0 = unknown
+# Downlink Load: Current load of downlink WAN connection (scaled to 255 = 100%)
+# Uplink Load: Current load of uplink WAN connection (scaled to 255 = 100%)
+# Load Measurement Duration: Duration for measuring downlink/uplink load in
+# tenths of a second (1..65535); 0 if load cannot be determined
+#hs20_wan_metrics=01:8000:1000:80:240:3000
+
+# Operating Class Indication
+# List of operating classes the BSSes in this ESS use. The Global operating
+# classes in Table E-4 of IEEE Std 802.11-2012 Annex E define the values that
+# can be used in this.
+# format: hexdump of operating class octets
+# for example, operating classes 81 (2.4 GHz channels 1-13) and 115 (5 GHz
+# channels 36-48):
+#hs20_operating_class=5173
+
+##### TESTING OPTIONS #########################################################
+#
+# The options in this section are only available when the build configuration
+# option CONFIG_TESTING_OPTIONS is set while compiling hostapd. They allow
+# testing some scenarios that are otherwise difficult to reproduce.
+#
+# Ignore probe requests sent to hostapd with the given probability, must be a
+# floating point number in the range [0, 1).
+#ignore_probe_probability=0.0
+#
+# Ignore authentication frames with the given probability
+#ignore_auth_probability=0.0
+#
+# Ignore association requests with the given probability
+#ignore_assoc_probability=0.0
+#
+# Ignore reassociation requests with the given probability
+#ignore_reassoc_probability=0.0
+#
+# Corrupt Key MIC in GTK rekey EAPOL-Key frames with the given probability
+#corrupt_gtk_rekey_mic_probability=0.0
+
+##### Multiple BSSID support ##################################################
+#
+# Above configuration is using the default interface (wlan#, or multi-SSID VLAN
+# interfaces). Other BSSIDs can be added by using separator 'bss' with
+# default interface name to be allocated for the data packets of the new BSS.
+#
+# hostapd will generate BSSID mask based on the BSSIDs that are
+# configured. hostapd will verify that dev_addr & MASK == dev_addr. If this is
+# not the case, the MAC address of the radio must be changed before starting
+# hostapd (ifconfig wlan0 hw ether <MAC addr>). If a BSSID is configured for
+# every secondary BSS, this limitation is not applied at hostapd and other
+# masks may be used if the driver supports them (e.g., swap the locally
+# administered bit)
+#
+# BSSIDs are assigned in order to each BSS, unless an explicit BSSID is
+# specified using the 'bssid' parameter.
+# If an explicit BSSID is specified, it must be chosen such that it:
+# - results in a valid MASK that covers it and the dev_addr
+# - is not the same as the MAC address of the radio
+# - is not the same as any other explicitly specified BSSID
+#
+# Please note that hostapd uses some of the values configured for the first BSS
+# as the defaults for the following BSSes. However, it is recommended that all
+# BSSes include explicit configuration of all relevant configuration items.
+#
+#bss=wlan0_0
+#ssid=test2
+# most of the above items can be used here (apart from radio interface specific
+# items, like channel)
+
+#bss=wlan0_1
+#bssid=00:13:10:95:fe:0b
+# ...
diff --git a/drivers/net/wireless/ssv6x5x/script/hostapd.conf.TKIP.template b/drivers/net/wireless/ssv6x5x/script/hostapd.conf.TKIP.template
new file mode 100755
index 000000000..4cf2334e9
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/hostapd.conf.TKIP.template
@@ -0,0 +1,1665 @@
+##### hostapd configuration file ##############################################
+# Empty lines and lines starting with # are ignored
+
+# AP netdevice name (without 'ap' postfix, i.e., wlan0 uses wlan0ap for
+# management frames); ath0 for madwifi
+interface=HOSTAPD_IF
+
+# In case of madwifi, atheros, and nl80211 driver interfaces, an additional
+# configuration parameter, bridge, may be used to notify hostapd if the
+# interface is included in a bridge. This parameter is not used with Host AP
+# driver. If the bridge parameter is not set, the drivers will automatically
+# figure out the bridge interface (assuming sysfs is enabled and mounted to
+# /sys) and this parameter may not be needed.
+#
+# For nl80211, this parameter can be used to request the AP interface to be
+# added to the bridge automatically (brctl may refuse to do this before hostapd
+# has been started to change the interface mode). If needed, the bridge
+# interface is also created.
+#bridge=br0
+
+# Driver interface type (hostap/wired/madwifi/test/none/nl80211/bsd);
+# default: hostap). nl80211 is used with all Linux mac80211 drivers.
+# Use driver=none if building hostapd as a standalone RADIUS server that does
+# not control any wireless/wired driver.
+# driver=hostap
+
+# hostapd event logger configuration
+#
+# Two output method: syslog and stdout (only usable if not forking to
+# background).
+#
+# Module bitfield (ORed bitfield of modules that will be logged; -1 = all
+# modules):
+# bit 0 (1) = IEEE 802.11
+# bit 1 (2) = IEEE 802.1X
+# bit 2 (4) = RADIUS
+# bit 3 (8) = WPA
+# bit 4 (16) = driver interface
+# bit 5 (32) = IAPP
+# bit 6 (64) = MLME
+#
+# Levels (minimum value for logged events):
+#  0 = verbose debugging
+#  1 = debugging
+#  2 = informational messages
+#  3 = notification
+#  4 = warning
+#
+logger_syslog=1
+logger_syslog_level=0
+logger_stdout=1
+logger_stdout_level=0
+
+# Interface for separate control program. If this is specified, hostapd
+# will create this directory and a UNIX domain socket for listening to requests
+# from external programs (CLI/GUI, etc.) for status information and
+# configuration. The socket file will be named based on the interface name, so
+# multiple hostapd processes/interfaces can be run at the same time if more
+# than one interface is used.
+# /var/run/hostapd is the recommended directory for sockets and by default,
+# hostapd_cli will use it when trying to connect with hostapd.
+ctrl_interface=/var/run/hostapd
+
+# Access control for the control interface can be configured by setting the
+# directory to allow only members of a group to use sockets. This way, it is
+# possible to run hostapd as root (since it needs to change network
+# configuration and open raw sockets) and still allow GUI/CLI components to be
+# run as non-root users. However, since the control interface can be used to
+# change the network configuration, this access needs to be protected in many
+# cases. By default, hostapd is configured to use gid 0 (root). If you
+# want to allow non-root users to use the contron interface, add a new group
+# and change this value to match with that group. Add users that should have
+# control interface access to this group.
+#
+# This variable can be a group name or gid.
+#ctrl_interface_group=wheel
+ctrl_interface_group=0
+
+
+##### IEEE 802.11 related configuration #######################################
+
+# SSID to be used in IEEE 802.11 management frames
+ssid=TestAP_TKIP
+# Alternative formats for configuring SSID
+# (double quoted string, hexdump, printf-escaped string)
+#ssid2="test"
+#ssid2=74657374
+#ssid2=P"hello\nthere"
+
+# UTF-8 SSID: Whether the SSID is to be interpreted using UTF-8 encoding
+#utf8_ssid=1
+
+# Country code (ISO/IEC 3166-1). Used to set regulatory domain.
+# Set as needed to indicate country in which device is operating.
+# This can limit available channels and transmit power.
+#country_code=US
+
+# Enable IEEE 802.11d. This advertises the country_code and the set of allowed
+# channels and transmit power levels based on the regulatory limits. The
+# country_code setting must be configured with the correct country for
+# IEEE 802.11d functions.
+# (default: 0 = disabled)
+#ieee80211d=1
+
+# Enable IEEE 802.11h. This enables radar detection and DFS support if
+# available. DFS support is required on outdoor 5 GHz channels in most countries
+# of the world. This can be used only with ieee80211d=1.
+# (default: 0 = disabled)
+#ieee80211h=1
+
+# Operation mode (a = IEEE 802.11a, b = IEEE 802.11b, g = IEEE 802.11g,
+# ad = IEEE 802.11ad (60 GHz); a/g options are used with IEEE 802.11n, too, to
+# specify band)
+# Default: IEEE 802.11b
+hw_mode=g
+
+# Channel number (IEEE 802.11)
+# (default: 0, i.e., not set)
+# Please note that some drivers do not use this value from hostapd and the
+# channel will need to be configured separately with iwconfig.
+#
+# If CONFIG_ACS build option is enabled, the channel can be selected
+# automatically at run time by setting channel=acs_survey or channel=0, both of
+# which will enable the ACS survey based algorithm.
+channel=6
+
+# ACS tuning - Automatic Channel Selection
+# See: http://wireless.kernel.org/en/users/Documentation/acs
+#
+# You can customize the ACS survey algorithm with following variables:
+#
+# acs_num_scans requirement is 1..100 - number of scans to be performed that
+# are used to trigger survey data gathering of an underlying device driver.
+# Scans are passive and typically take a little over 100ms (depending on the
+# driver) on each available channel for given hw_mode. Increasing this value
+# means sacrificing startup time and gathering more data wrt channel
+# interference that may help choosing a better channel. This can also help fine
+# tune the ACS scan time in case a driver has different scan dwell times.
+#
+# Defaults:
+#acs_num_scans=5
+
+# Beacon interval in kus (1.024 ms) (default: 100; range 15..65535)
+beacon_int=100
+
+# DTIM (delivery traffic information message) period (range 1..255):
+# number of beacons between DTIMs (1 = every beacon includes DTIM element)
+# (default: 2)
+dtim_period=2
+
+# Maximum number of stations allowed in station table. New stations will be
+# rejected after the station table is full. IEEE 802.11 has a limit of 2007
+# different association IDs, so this number should not be larger than that.
+# (default: 2007)
+max_num_sta=255
+
+# RTS/CTS threshold; 2347 = disabled (default); range 0..2347
+# If this field is not included in hostapd.conf, hostapd will not control
+# RTS threshold and 'iwconfig wlan# rts <val>' can be used to set it.
+rts_threshold=2347
+
+# Fragmentation threshold; 2346 = disabled (default); range 256..2346
+# If this field is not included in hostapd.conf, hostapd will not control
+# fragmentation threshold and 'iwconfig wlan# frag <val>' can be used to set
+# it.
+fragm_threshold=2346
+
+# Rate configuration
+# Default is to enable all rates supported by the hardware. This configuration
+# item allows this list be filtered so that only the listed rates will be left
+# in the list. If the list is empty, all rates are used. This list can have
+# entries that are not in the list of rates the hardware supports (such entries
+# are ignored). The entries in this list are in 100 kbps, i.e., 11 Mbps = 110.
+# If this item is present, at least one rate have to be matching with the rates
+# hardware supports.
+# default: use the most common supported rate setting for the selected
+# hw_mode (i.e., this line can be removed from configuration file in most
+# cases)
+#supported_rates=10 20 55 110 60 90 120 180 240 360 480 540
+
+# Basic rate set configuration
+# List of rates (in 100 kbps) that are included in the basic rate set.
+# If this item is not included, usually reasonable default set is used.
+#basic_rates=10 20
+#basic_rates=10 20 55 110
+#basic_rates=60 120 240
+
+# Short Preamble
+# This parameter can be used to enable optional use of short preamble for
+# frames sent at 2 Mbps, 5.5 Mbps, and 11 Mbps to improve network performance.
+# This applies only to IEEE 802.11b-compatible networks and this should only be
+# enabled if the local hardware supports use of short preamble. If any of the
+# associated STAs do not support short preamble, use of short preamble will be
+# disabled (and enabled when such STAs disassociate) dynamically.
+# 0 = do not allow use of short preamble (default)
+# 1 = allow use of short preamble
+#preamble=1
+
+# Station MAC address -based authentication
+# Please note that this kind of access control requires a driver that uses
+# hostapd to take care of management frame processing and as such, this can be
+# used with driver=hostap or driver=nl80211, but not with driver=madwifi.
+# 0 = accept unless in deny list
+# 1 = deny unless in accept list
+# 2 = use external RADIUS server (accept/deny lists are searched first)
+macaddr_acl=0
+
+# Accept/deny lists are read from separate files (containing list of
+# MAC addresses, one per line). Use absolute path name to make sure that the
+# files can be read on SIGHUP configuration reloads.
+#accept_mac_file=/etc/hostapd.accept
+#deny_mac_file=/etc/hostapd.deny
+
+# IEEE 802.11 specifies two authentication algorithms. hostapd can be
+# configured to allow both of these or only one. Open system authentication
+# should be used with IEEE 802.1X.
+# Bit fields of allowed authentication algorithms:
+# bit 0 = Open System Authentication
+# bit 1 = Shared Key Authentication (requires WEP)
+auth_algs=3
+
+# Send empty SSID in beacons and ignore probe request frames that do not
+# specify full SSID, i.e., require stations to know SSID.
+# default: disabled (0)
+# 1 = send empty (length=0) SSID in beacon and ignore probe request for
+#     broadcast SSID
+# 2 = clear SSID (ASCII 0), but keep the original length (this may be required
+#     with some clients that do not support empty SSID) and ignore probe
+#     requests for broadcast SSID
+ignore_broadcast_ssid=0
+
+# Additional vendor specfic elements for Beacon and Probe Response frames
+# This parameter can be used to add additional vendor specific element(s) into
+# the end of the Beacon and Probe Response frames. The format for these
+# element(s) is a hexdump of the raw information elements (id+len+payload for
+# one or more elements)
+#vendor_elements=dd0411223301
+
+# TX queue parameters (EDCF / bursting)
+# tx_queue_<queue name>_<param>
+# queues: data0, data1, data2, data3, after_beacon, beacon
+#		(data0 is the highest priority queue)
+# parameters:
+#   aifs: AIFS (default 2)
+#   cwmin: cwMin (1, 3, 7, 15, 31, 63, 127, 255, 511, 1023)
+#   cwmax: cwMax (1, 3, 7, 15, 31, 63, 127, 255, 511, 1023); cwMax >= cwMin
+#   burst: maximum length (in milliseconds with precision of up to 0.1 ms) for
+#          bursting
+#
+# Default WMM parameters (IEEE 802.11 draft; 11-03-0504-03-000e):
+# These parameters are used by the access point when transmitting frames
+# to the clients.
+#
+# Low priority / AC_BK = background
+#tx_queue_data3_aifs=7
+#tx_queue_data3_cwmin=15
+#tx_queue_data3_cwmax=1023
+#tx_queue_data3_burst=0
+# Note: for IEEE 802.11b mode: cWmin=31 cWmax=1023 burst=0
+#
+# Normal priority / AC_BE = best effort
+#tx_queue_data2_aifs=3
+#tx_queue_data2_cwmin=15
+#tx_queue_data2_cwmax=63
+#tx_queue_data2_burst=0
+# Note: for IEEE 802.11b mode: cWmin=31 cWmax=127 burst=0
+#
+# High priority / AC_VI = video
+#tx_queue_data1_aifs=1
+#tx_queue_data1_cwmin=7
+#tx_queue_data1_cwmax=15
+#tx_queue_data1_burst=3.0
+# Note: for IEEE 802.11b mode: cWmin=15 cWmax=31 burst=6.0
+#
+# Highest priority / AC_VO = voice
+#tx_queue_data0_aifs=1
+#tx_queue_data0_cwmin=3
+#tx_queue_data0_cwmax=7
+#tx_queue_data0_burst=1.5
+# Note: for IEEE 802.11b mode: cWmin=7 cWmax=15 burst=3.3
+
+# 802.1D Tag (= UP) to AC mappings
+# WMM specifies following mapping of data frames to different ACs. This mapping
+# can be configured using Linux QoS/tc and sch_pktpri.o module.
+# 802.1D Tag	802.1D Designation	Access Category	WMM Designation
+# 1		BK			AC_BK		Background
+# 2		-			AC_BK		Background
+# 0		BE			AC_BE		Best Effort
+# 3		EE			AC_BE		Best Effort
+# 4		CL			AC_VI		Video
+# 5		VI			AC_VI		Video
+# 6		VO			AC_VO		Voice
+# 7		NC			AC_VO		Voice
+# Data frames with no priority information: AC_BE
+# Management frames: AC_VO
+# PS-Poll frames: AC_BE
+
+# Default WMM parameters (IEEE 802.11 draft; 11-03-0504-03-000e):
+# for 802.11a or 802.11g networks
+# These parameters are sent to WMM clients when they associate.
+# The parameters will be used by WMM clients for frames transmitted to the
+# access point.
+#
+# note - txop_limit is in units of 32microseconds
+# note - acm is admission control mandatory flag. 0 = admission control not
+# required, 1 = mandatory
+# note - here cwMin and cmMax are in exponent form. the actual cw value used
+# will be (2^n)-1 where n is the value given here
+#
+wmm_enabled=1
+#
+# WMM-PS Unscheduled Automatic Power Save Delivery [U-APSD]
+# Enable this flag if U-APSD supported outside hostapd (eg., Firmware/driver)
+#uapsd_advertisement_enabled=1
+#
+# Low priority / AC_BK = background
+wmm_ac_bk_cwmin=4
+wmm_ac_bk_cwmax=10
+wmm_ac_bk_aifs=7
+wmm_ac_bk_txop_limit=0
+wmm_ac_bk_acm=0
+# Note: for IEEE 802.11b mode: cWmin=5 cWmax=10
+#
+# Normal priority / AC_BE = best effort
+wmm_ac_be_aifs=3
+wmm_ac_be_cwmin=4
+wmm_ac_be_cwmax=10
+wmm_ac_be_txop_limit=0
+wmm_ac_be_acm=0
+# Note: for IEEE 802.11b mode: cWmin=5 cWmax=7
+#
+# High priority / AC_VI = video
+wmm_ac_vi_aifs=2
+wmm_ac_vi_cwmin=3
+wmm_ac_vi_cwmax=4
+wmm_ac_vi_txop_limit=94
+wmm_ac_vi_acm=0
+# Note: for IEEE 802.11b mode: cWmin=4 cWmax=5 txop_limit=188
+#
+# Highest priority / AC_VO = voice
+wmm_ac_vo_aifs=2
+wmm_ac_vo_cwmin=2
+wmm_ac_vo_cwmax=3
+wmm_ac_vo_txop_limit=47
+wmm_ac_vo_acm=0
+# Note: for IEEE 802.11b mode: cWmin=3 cWmax=4 burst=102
+
+# Static WEP key configuration
+#
+# The key number to use when transmitting.
+# It must be between 0 and 3, and the corresponding key must be set.
+# default: not set
+#wep_default_key=0
+# The WEP keys to use.
+# A key may be a quoted string or unquoted hexadecimal digits.
+# The key length should be 5, 13, or 16 characters, or 10, 26, or 32
+# digits, depending on whether 40-bit (64-bit), 104-bit (128-bit), or
+# 128-bit (152-bit) WEP is used.
+# Only the default key must be supplied; the others are optional.
+# default: not set
+#wep_key0=123456789a
+#wep_key1="vwxyz"
+#wep_key2=0102030405060708090a0b0c0d
+#wep_key3=".2.4.6.8.0.23"
+
+# Station inactivity limit
+#
+# If a station does not send anything in ap_max_inactivity seconds, an
+# empty data frame is sent to it in order to verify whether it is
+# still in range. If this frame is not ACKed, the station will be
+# disassociated and then deauthenticated. This feature is used to
+# clear station table of old entries when the STAs move out of the
+# range.
+#
+# The station can associate again with the AP if it is still in range;
+# this inactivity poll is just used as a nicer way of verifying
+# inactivity; i.e., client will not report broken connection because
+# disassociation frame is not sent immediately without first polling
+# the STA with a data frame.
+# default: 300 (i.e., 5 minutes)
+#ap_max_inactivity=300
+#
+# The inactivity polling can be disabled to disconnect stations based on
+# inactivity timeout so that idle stations are more likely to be disconnected
+# even if they are still in range of the AP. This can be done by setting
+# skip_inactivity_poll to 1 (default 0).
+#skip_inactivity_poll=0
+
+# Disassociate stations based on excessive transmission failures or other
+# indications of connection loss. This depends on the driver capabilities and
+# may not be available with all drivers.
+#disassoc_low_ack=1
+
+# Maximum allowed Listen Interval (how many Beacon periods STAs are allowed to
+# remain asleep). Default: 65535 (no limit apart from field size)
+#max_listen_interval=100
+
+# WDS (4-address frame) mode with per-station virtual interfaces
+# (only supported with driver=nl80211)
+# This mode allows associated stations to use 4-address frames to allow layer 2
+# bridging to be used.
+#wds_sta=1
+
+# If bridge parameter is set, the WDS STA interface will be added to the same
+# bridge by default. This can be overridden with the wds_bridge parameter to
+# use a separate bridge.
+#wds_bridge=wds-br0
+
+# Start the AP with beaconing disabled by default.
+#start_disabled=0
+
+# Client isolation can be used to prevent low-level bridging of frames between
+# associated stations in the BSS. By default, this bridging is allowed.
+#ap_isolate=1
+
+# Fixed BSS Load value for testing purposes
+# This field can be used to configure hostapd to add a fixed BSS Load element
+# into Beacon and Probe Response frames for testing purposes. The format is
+# <station count>:<channel utilization>:<available admission capacity>
+#bss_load_test=12:80:20000
+
+##### IEEE 802.11n related configuration ######################################
+
+# ieee80211n: Whether IEEE 802.11n (HT) is enabled
+# 0 = disabled (default)
+# 1 = enabled
+# Note: You will also need to enable WMM for full HT functionality.
+ieee80211n=1
+
+# ht_capab: HT capabilities (list of flags)
+# LDPC coding capability: [LDPC] = supported
+# Supported channel width set: [HT40-] = both 20 MHz and 40 MHz with secondary
+#	channel below the primary channel; [HT40+] = both 20 MHz and 40 MHz
+#	with secondary channel below the primary channel
+#	(20 MHz only if neither is set)
+#	Note: There are limits on which channels can be used with HT40- and
+#	HT40+. Following table shows the channels that may be available for
+#	HT40- and HT40+ use per IEEE 802.11n Annex J:
+#	freq		HT40-		HT40+
+#	2.4 GHz		5-13		1-7 (1-9 in Europe/Japan)
+#	5 GHz		40,48,56,64	36,44,52,60
+#	(depending on the location, not all of these channels may be available
+#	for use)
+#	Please note that 40 MHz channels may switch their primary and secondary
+#	channels if needed or creation of 40 MHz channel maybe rejected based
+#	on overlapping BSSes. These changes are done automatically when hostapd
+#	is setting up the 40 MHz channel.
+# Spatial Multiplexing (SM) Power Save: [SMPS-STATIC] or [SMPS-DYNAMIC]
+#	(SMPS disabled if neither is set)
+# HT-greenfield: [GF] (disabled if not set)
+# Short GI for 20 MHz: [SHORT-GI-20] (disabled if not set)
+# Short GI for 40 MHz: [SHORT-GI-40] (disabled if not set)
+# Tx STBC: [TX-STBC] (disabled if not set)
+# Rx STBC: [RX-STBC1] (one spatial stream), [RX-STBC12] (one or two spatial
+#	streams), or [RX-STBC123] (one, two, or three spatial streams); Rx STBC
+#	disabled if none of these set
+# HT-delayed Block Ack: [DELAYED-BA] (disabled if not set)
+# Maximum A-MSDU length: [MAX-AMSDU-7935] for 7935 octets (3839 octets if not
+#	set)
+# DSSS/CCK Mode in 40 MHz: [DSSS_CCK-40] = allowed (not allowed if not set)
+# PSMP support: [PSMP] (disabled if not set)
+# L-SIG TXOP protection support: [LSIG-TXOP-PROT] (disabled if not set)
+#ht_capab=[HT40-][SHORT-GI-20][SHORT-GI-40]
+ht_capab=[SHORT-GI-20]
+
+# Require stations to support HT PHY (reject association if they do not)
+#require_ht=1
+
+# If set non-zero, require stations to perform scans of overlapping
+# channels to test for stations which would be affected by 40 MHz traffic.
+# This parameter sets the interval in seconds between these scans. This
+# is useful only for testing that stations properly set the OBSS interval,
+# since the other parameters in the OBSS scan parameters IE are set to 0.
+#obss_interval=0
+
+##### IEEE 802.11ac related configuration #####################################
+
+# ieee80211ac: Whether IEEE 802.11ac (VHT) is enabled
+# 0 = disabled (default)
+# 1 = enabled
+# Note: You will also need to enable WMM for full VHT functionality.
+#ieee80211ac=1
+
+# vht_capab: VHT capabilities (list of flags)
+#
+# vht_max_mpdu_len: [MAX-MPDU-7991] [MAX-MPDU-11454]
+# Indicates maximum MPDU length
+# 0 = 3895 octets (default)
+# 1 = 7991 octets
+# 2 = 11454 octets
+# 3 = reserved
+#
+# supported_chan_width: [VHT160] [VHT160-80PLUS80]
+# Indicates supported Channel widths
+# 0 = 160 MHz & 80+80 channel widths are not supported (default)
+# 1 = 160 MHz channel width is supported
+# 2 = 160 MHz & 80+80 channel widths are supported
+# 3 = reserved
+#
+# Rx LDPC coding capability: [RXLDPC]
+# Indicates support for receiving LDPC coded pkts
+# 0 = Not supported (default)
+# 1 = Supported
+#
+# Short GI for 80 MHz: [SHORT-GI-80]
+# Indicates short GI support for reception of packets transmitted with TXVECTOR
+# params format equal to VHT and CBW = 80Mhz
+# 0 = Not supported (default)
+# 1 = Supported
+#
+# Short GI for 160 MHz: [SHORT-GI-160]
+# Indicates short GI support for reception of packets transmitted with TXVECTOR
+# params format equal to VHT and CBW = 160Mhz
+# 0 = Not supported (default)
+# 1 = Supported
+#
+# Tx STBC: [TX-STBC-2BY1]
+# Indicates support for the transmission of at least 2x1 STBC
+# 0 = Not supported (default)
+# 1 = Supported
+#
+# Rx STBC: [RX-STBC-1] [RX-STBC-12] [RX-STBC-123] [RX-STBC-1234]
+# Indicates support for the reception of PPDUs using STBC
+# 0 = Not supported (default)
+# 1 = support of one spatial stream
+# 2 = support of one and two spatial streams
+# 3 = support of one, two and three spatial streams
+# 4 = support of one, two, three and four spatial streams
+# 5,6,7 = reserved
+#
+# SU Beamformer Capable: [SU-BEAMFORMER]
+# Indicates support for operation as a single user beamformer
+# 0 = Not supported (default)
+# 1 = Supported
+#
+# SU Beamformee Capable: [SU-BEAMFORMEE]
+# Indicates support for operation as a single user beamformee
+# 0 = Not supported (default)
+# 1 = Supported
+#
+# Compressed Steering Number of Beamformer Antennas Supported: [BF-ANTENNA-2]
+#   Beamformee's capability indicating the maximum number of beamformer
+#   antennas the beamformee can support when sending compressed beamforming
+#   feedback
+# If SU beamformer capable, set to maximum value minus 1
+# else reserved (default)
+#
+# Number of Sounding Dimensions: [SOUNDING-DIMENSION-2]
+# Beamformer's capability indicating the maximum value of the NUM_STS parameter
+# in the TXVECTOR of a VHT NDP
+# If SU beamformer capable, set to maximum value minus 1
+# else reserved (default)
+#
+# MU Beamformer Capable: [MU-BEAMFORMER]
+# Indicates support for operation as an MU beamformer
+# 0 = Not supported or sent by Non-AP STA (default)
+# 1 = Supported
+#
+# MU Beamformee Capable: [MU-BEAMFORMEE]
+# Indicates support for operation as an MU beamformee
+# 0 = Not supported or sent by AP (default)
+# 1 = Supported
+#
+# VHT TXOP PS: [VHT-TXOP-PS]
+# Indicates whether or not the AP supports VHT TXOP Power Save Mode
+#  or whether or not the STA is in VHT TXOP Power Save mode
+# 0 = VHT AP doesnt support VHT TXOP PS mode (OR) VHT Sta not in VHT TXOP PS
+#  mode
+# 1 = VHT AP supports VHT TXOP PS mode (OR) VHT Sta is in VHT TXOP power save
+#  mode
+#
+# +HTC-VHT Capable: [HTC-VHT]
+# Indicates whether or not the STA supports receiving a VHT variant HT Control
+# field.
+# 0 = Not supported (default)
+# 1 = supported
+#
+# Maximum A-MPDU Length Exponent: [MAX-A-MPDU-LEN-EXP0]..[MAX-A-MPDU-LEN-EXP7]
+# Indicates the maximum length of A-MPDU pre-EOF padding that the STA can recv
+# This field is an integer in the range of 0 to 7.
+# The length defined by this field is equal to
+# 2 pow(13 + Maximum A-MPDU Length Exponent) -1 octets
+#
+# VHT Link Adaptation Capable: [VHT-LINK-ADAPT2] [VHT-LINK-ADAPT3]
+# Indicates whether or not the STA supports link adaptation using VHT variant
+# HT Control field
+# If +HTC-VHTcapable is 1
+#  0 = (no feedback) if the STA does not provide VHT MFB (default)
+#  1 = reserved
+#  2 = (Unsolicited) if the STA provides only unsolicited VHT MFB
+#  3 = (Both) if the STA can provide VHT MFB in response to VHT MRQ and if the
+#      STA provides unsolicited VHT MFB
+# Reserved if +HTC-VHTcapable is 0
+#
+# Rx Antenna Pattern Consistency: [RX-ANTENNA-PATTERN]
+# Indicates the possibility of Rx antenna pattern change
+# 0 = Rx antenna pattern might change during the lifetime of an association
+# 1 = Rx antenna pattern does not change during the lifetime of an association
+#
+# Tx Antenna Pattern Consistency: [TX-ANTENNA-PATTERN]
+# Indicates the possibility of Tx antenna pattern change
+# 0 = Tx antenna pattern might change during the lifetime of an association
+# 1 = Tx antenna pattern does not change during the lifetime of an association
+#vht_capab=[SHORT-GI-80][HTC-VHT]
+#
+# Require stations to support VHT PHY (reject association if they do not)
+#require_vht=1
+
+# 0 = 20 or 40 MHz operating Channel width
+# 1 = 80 MHz channel width
+# 2 = 160 MHz channel width
+# 3 = 80+80 MHz channel width
+#vht_oper_chwidth=1
+#
+# center freq = 5 GHz + (5 * index)
+# So index 42 gives center freq 5.210 GHz
+# which is channel 42 in 5G band
+#
+#vht_oper_centr_freq_seg0_idx=42
+#
+# center freq = 5 GHz + (5 * index)
+# So index 159 gives center freq 5.795 GHz
+# which is channel 159 in 5G band
+#
+#vht_oper_centr_freq_seg1_idx=159
+
+##### IEEE 802.1X-2004 related configuration ##################################
+
+# Require IEEE 802.1X authorization
+#ieee8021x=1
+
+# IEEE 802.1X/EAPOL version
+# hostapd is implemented based on IEEE Std 802.1X-2004 which defines EAPOL
+# version 2. However, there are many client implementations that do not handle
+# the new version number correctly (they seem to drop the frames completely).
+# In order to make hostapd interoperate with these clients, the version number
+# can be set to the older version (1) with this configuration value.
+#eapol_version=2
+
+# Optional displayable message sent with EAP Request-Identity. The first \0
+# in this string will be converted to ASCII-0 (nul). This can be used to
+# separate network info (comma separated list of attribute=value pairs); see,
+# e.g., RFC 4284.
+#eap_message=hello
+#eap_message=hello\0networkid=netw,nasid=foo,portid=0,NAIRealms=example.com
+
+# WEP rekeying (disabled if key lengths are not set or are set to 0)
+# Key lengths for default/broadcast and individual/unicast keys:
+# 5 = 40-bit WEP (also known as 64-bit WEP with 40 secret bits)
+# 13 = 104-bit WEP (also known as 128-bit WEP with 104 secret bits)
+#wep_key_len_broadcast=5
+#wep_key_len_unicast=5
+# Rekeying period in seconds. 0 = do not rekey (i.e., set keys only once)
+#wep_rekey_period=300
+
+# EAPOL-Key index workaround (set bit7) for WinXP Supplicant (needed only if
+# only broadcast keys are used)
+eapol_key_index_workaround=0
+
+# EAP reauthentication period in seconds (default: 3600 seconds; 0 = disable
+# reauthentication).
+#eap_reauth_period=3600
+
+# Use PAE group address (01:80:c2:00:00:03) instead of individual target
+# address when sending EAPOL frames with driver=wired. This is the most common
+# mechanism used in wired authentication, but it also requires that the port
+# is only used by one station.
+#use_pae_group_addr=1
+
+##### Integrated EAP server ###################################################
+
+# Optionally, hostapd can be configured to use an integrated EAP server
+# to process EAP authentication locally without need for an external RADIUS
+# server. This functionality can be used both as a local authentication server
+# for IEEE 802.1X/EAPOL and as a RADIUS server for other devices.
+
+# Use integrated EAP server instead of external RADIUS authentication
+# server. This is also needed if hostapd is configured to act as a RADIUS
+# authentication server.
+eap_server=0
+
+# Path for EAP server user database
+# If SQLite support is included, this can be set to "sqlite:/path/to/sqlite.db"
+# to use SQLite database instead of a text file.
+#eap_user_file=/etc/hostapd.eap_user
+
+# CA certificate (PEM or DER file) for EAP-TLS/PEAP/TTLS
+#ca_cert=/etc/hostapd.ca.pem
+
+# Server certificate (PEM or DER file) for EAP-TLS/PEAP/TTLS
+#server_cert=/etc/hostapd.server.pem
+
+# Private key matching with the server certificate for EAP-TLS/PEAP/TTLS
+# This may point to the same file as server_cert if both certificate and key
+# are included in a single file. PKCS#12 (PFX) file (.p12/.pfx) can also be
+# used by commenting out server_cert and specifying the PFX file as the
+# private_key.
+#private_key=/etc/hostapd.server.prv
+
+# Passphrase for private key
+#private_key_passwd=secret passphrase
+
+# Server identity
+# EAP methods that provide mechanism for authenticated server identity delivery
+# use this value. If not set, "hostapd" is used as a default.
+#server_id=server.example.com
+
+# Enable CRL verification.
+# Note: hostapd does not yet support CRL downloading based on CDP. Thus, a
+# valid CRL signed by the CA is required to be included in the ca_cert file.
+# This can be done by using PEM format for CA certificate and CRL and
+# concatenating these into one file. Whenever CRL changes, hostapd needs to be
+# restarted to take the new CRL into use.
+# 0 = do not verify CRLs (default)
+# 1 = check the CRL of the user certificate
+# 2 = check all CRLs in the certificate path
+#check_crl=1
+
+# Cached OCSP stapling response (DER encoded)
+# If set, this file is sent as a certificate status response by the EAP server
+# if the EAP peer requests certificate status in the ClientHello message.
+# This cache file can be updated, e.g., by running following command
+# periodically to get an update from the OCSP responder:
+# openssl ocsp \
+#	-no_nonce \
+#	-CAfile /etc/hostapd.ca.pem \
+#	-issuer /etc/hostapd.ca.pem \
+#	-cert /etc/hostapd.server.pem \
+#	-url http://ocsp.example.com:8888/ \
+#	-respout /tmp/ocsp-cache.der
+#ocsp_stapling_response=/tmp/ocsp-cache.der
+
+# dh_file: File path to DH/DSA parameters file (in PEM format)
+# This is an optional configuration file for setting parameters for an
+# ephemeral DH key exchange. In most cases, the default RSA authentication does
+# not use this configuration. However, it is possible setup RSA to use
+# ephemeral DH key exchange. In addition, ciphers with DSA keys always use
+# ephemeral DH keys. This can be used to achieve forward secrecy. If the file
+# is in DSA parameters format, it will be automatically converted into DH
+# params. This parameter is required if anonymous EAP-FAST is used.
+# You can generate DH parameters file with OpenSSL, e.g.,
+# "openssl dhparam -out /etc/hostapd.dh.pem 1024"
+#dh_file=/etc/hostapd.dh.pem
+
+# Fragment size for EAP methods
+#fragment_size=1400
+
+# Finite cyclic group for EAP-pwd. Number maps to group of domain parameters
+# using the IANA repository for IKE (RFC 2409).
+#pwd_group=19
+
+# Configuration data for EAP-SIM database/authentication gateway interface.
+# This is a text string in implementation specific format. The example
+# implementation in eap_sim_db.c uses this as the UNIX domain socket name for
+# the HLR/AuC gateway (e.g., hlr_auc_gw). In this case, the path uses "unix:"
+# prefix. If hostapd is built with SQLite support (CONFIG_SQLITE=y in .config),
+# database file can be described with an optional db=<path> parameter.
+#eap_sim_db=unix:/tmp/hlr_auc_gw.sock
+#eap_sim_db=unix:/tmp/hlr_auc_gw.sock db=/tmp/hostapd.db
+
+# Encryption key for EAP-FAST PAC-Opaque values. This key must be a secret,
+# random value. It is configured as a 16-octet value in hex format. It can be
+# generated, e.g., with the following command:
+# od -tx1 -v -N16 /dev/random | colrm 1 8 | tr -d ' '
+#pac_opaque_encr_key=000102030405060708090a0b0c0d0e0f
+
+# EAP-FAST authority identity (A-ID)
+# A-ID indicates the identity of the authority that issues PACs. The A-ID
+# should be unique across all issuing servers. In theory, this is a variable
+# length field, but due to some existing implementations requiring A-ID to be
+# 16 octets in length, it is strongly recommended to use that length for the
+# field to provid interoperability with deployed peer implementations. This
+# field is configured in hex format.
+#eap_fast_a_id=101112131415161718191a1b1c1d1e1f
+
+# EAP-FAST authority identifier information (A-ID-Info)
+# This is a user-friendly name for the A-ID. For example, the enterprise name
+# and server name in a human-readable format. This field is encoded as UTF-8.
+#eap_fast_a_id_info=test server
+
+# Enable/disable different EAP-FAST provisioning modes:
+#0 = provisioning disabled
+#1 = only anonymous provisioning allowed
+#2 = only authenticated provisioning allowed
+#3 = both provisioning modes allowed (default)
+#eap_fast_prov=3
+
+# EAP-FAST PAC-Key lifetime in seconds (hard limit)
+#pac_key_lifetime=604800
+
+# EAP-FAST PAC-Key refresh time in seconds (soft limit on remaining hard
+# limit). The server will generate a new PAC-Key when this number of seconds
+# (or fewer) of the lifetime remains.
+#pac_key_refresh_time=86400
+
+# EAP-SIM and EAP-AKA protected success/failure indication using AT_RESULT_IND
+# (default: 0 = disabled).
+#eap_sim_aka_result_ind=1
+
+# Trusted Network Connect (TNC)
+# If enabled, TNC validation will be required before the peer is allowed to
+# connect. Note: This is only used with EAP-TTLS and EAP-FAST. If any other
+# EAP method is enabled, the peer will be allowed to connect without TNC.
+#tnc=1
+
+
+##### IEEE 802.11f - Inter-Access Point Protocol (IAPP) #######################
+
+# Interface to be used for IAPP broadcast packets
+#iapp_interface=eth0
+
+
+##### RADIUS client configuration #############################################
+# for IEEE 802.1X with external Authentication Server, IEEE 802.11
+# authentication with external ACL for MAC addresses, and accounting
+
+# The own IP address of the access point (used as NAS-IP-Address)
+own_ip_addr=127.0.0.1
+
+# Optional NAS-Identifier string for RADIUS messages. When used, this should be
+# a unique to the NAS within the scope of the RADIUS server. For example, a
+# fully qualified domain name can be used here.
+# When using IEEE 802.11r, nas_identifier must be set and must be between 1 and
+# 48 octets long.
+#nas_identifier=ap.example.com
+
+# RADIUS authentication server
+#auth_server_addr=127.0.0.1
+#auth_server_port=1812
+#auth_server_shared_secret=secret
+
+# RADIUS accounting server
+#acct_server_addr=127.0.0.1
+#acct_server_port=1813
+#acct_server_shared_secret=secret
+
+# Secondary RADIUS servers; to be used if primary one does not reply to
+# RADIUS packets. These are optional and there can be more than one secondary
+# server listed.
+#auth_server_addr=127.0.0.2
+#auth_server_port=1812
+#auth_server_shared_secret=secret2
+#
+#acct_server_addr=127.0.0.2
+#acct_server_port=1813
+#acct_server_shared_secret=secret2
+
+# Retry interval for trying to return to the primary RADIUS server (in
+# seconds). RADIUS client code will automatically try to use the next server
+# when the current server is not replying to requests. If this interval is set,
+# primary server will be retried after configured amount of time even if the
+# currently used secondary server is still working.
+#radius_retry_primary_interval=600
+
+
+# Interim accounting update interval
+# If this is set (larger than 0) and acct_server is configured, hostapd will
+# send interim accounting updates every N seconds. Note: if set, this overrides
+# possible Acct-Interim-Interval attribute in Access-Accept message. Thus, this
+# value should not be configured in hostapd.conf, if RADIUS server is used to
+# control the interim interval.
+# This value should not be less 600 (10 minutes) and must not be less than
+# 60 (1 minute).
+#radius_acct_interim_interval=600
+
+# Request Chargeable-User-Identity (RFC 4372)
+# This parameter can be used to configure hostapd to request CUI from the
+# RADIUS server by including Chargeable-User-Identity attribute into
+# Access-Request packets.
+#radius_request_cui=1
+
+# Dynamic VLAN mode; allow RADIUS authentication server to decide which VLAN
+# is used for the stations. This information is parsed from following RADIUS
+# attributes based on RFC 3580 and RFC 2868: Tunnel-Type (value 13 = VLAN),
+# Tunnel-Medium-Type (value 6 = IEEE 802), Tunnel-Private-Group-ID (value
+# VLANID as a string). Optionally, the local MAC ACL list (accept_mac_file) can
+# be used to set static client MAC address to VLAN ID mapping.
+# 0 = disabled (default)
+# 1 = option; use default interface if RADIUS server does not include VLAN ID
+# 2 = required; reject authentication if RADIUS server does not include VLAN ID
+#dynamic_vlan=0
+
+# VLAN interface list for dynamic VLAN mode is read from a separate text file.
+# This list is used to map VLAN ID from the RADIUS server to a network
+# interface. Each station is bound to one interface in the same way as with
+# multiple BSSIDs or SSIDs. Each line in this text file is defining a new
+# interface and the line must include VLAN ID and interface name separated by
+# white space (space or tab).
+# If no entries are provided by this file, the station is statically mapped
+# to <bss-iface>.<vlan-id> interfaces.
+#vlan_file=/etc/hostapd.vlan
+
+# Interface where 802.1q tagged packets should appear when a RADIUS server is
+# used to determine which VLAN a station is on.  hostapd creates a bridge for
+# each VLAN.  Then hostapd adds a VLAN interface (associated with the interface
+# indicated by 'vlan_tagged_interface') and the appropriate wireless interface
+# to the bridge.
+#vlan_tagged_interface=eth0
+
+# Bridge (prefix) to add the wifi and the tagged interface to. This gets the
+# VLAN ID appended. It defaults to brvlan%d if no tagged interface is given
+# and br%s.%d if a tagged interface is given, provided %s = tagged interface
+# and %d = VLAN ID.
+#vlan_bridge=brvlan
+
+# When hostapd creates a VLAN interface on vlan_tagged_interfaces, it needs
+# to know how to name it.
+# 0 = vlan<XXX>, e.g., vlan1
+# 1 = <vlan_tagged_interface>.<XXX>, e.g. eth0.1
+#vlan_naming=0
+
+# Arbitrary RADIUS attributes can be added into Access-Request and
+# Accounting-Request packets by specifying the contents of the attributes with
+# the following configuration parameters. There can be multiple of these to
+# add multiple attributes. These parameters can also be used to override some
+# of the attributes added automatically by hostapd.
+# Format: <attr_id>[:<syntax:value>]
+# attr_id: RADIUS attribute type (e.g., 26 = Vendor-Specific)
+# syntax: s = string (UTF-8), d = integer, x = octet string
+# value: attribute value in format indicated by the syntax
+# If syntax and value parts are omitted, a null value (single 0x00 octet) is
+# used.
+#
+# Additional Access-Request attributes
+# radius_auth_req_attr=<attr_id>[:<syntax:value>]
+# Examples:
+# Operator-Name = "Operator"
+#radius_auth_req_attr=126:s:Operator
+# Service-Type = Framed (2)
+#radius_auth_req_attr=6:d:2
+# Connect-Info = "testing" (this overrides the automatically generated value)
+#radius_auth_req_attr=77:s:testing
+# Same Connect-Info value set as a hexdump
+#radius_auth_req_attr=77:x:74657374696e67
+
+#
+# Additional Accounting-Request attributes
+# radius_acct_req_attr=<attr_id>[:<syntax:value>]
+# Examples:
+# Operator-Name = "Operator"
+#radius_acct_req_attr=126:s:Operator
+
+# Dynamic Authorization Extensions (RFC 5176)
+# This mechanism can be used to allow dynamic changes to user session based on
+# commands from a RADIUS server (or some other disconnect client that has the
+# needed session information). For example, Disconnect message can be used to
+# request an associated station to be disconnected.
+#
+# This is disabled by default. Set radius_das_port to non-zero UDP port
+# number to enable.
+#radius_das_port=3799
+#
+# DAS client (the host that can send Disconnect/CoA requests) and shared secret
+#radius_das_client=192.168.1.123 shared secret here
+#
+# DAS Event-Timestamp time window in seconds
+#radius_das_time_window=300
+#
+# DAS require Event-Timestamp
+#radius_das_require_event_timestamp=1
+
+##### RADIUS authentication server configuration ##############################
+
+# hostapd can be used as a RADIUS authentication server for other hosts. This
+# requires that the integrated EAP server is also enabled and both
+# authentication services are sharing the same configuration.
+
+# File name of the RADIUS clients configuration for the RADIUS server. If this
+# commented out, RADIUS server is disabled.
+#radius_server_clients=/etc/hostapd.radius_clients
+
+# The UDP port number for the RADIUS authentication server
+#radius_server_auth_port=1812
+
+# Use IPv6 with RADIUS server (IPv4 will also be supported using IPv6 API)
+#radius_server_ipv6=1
+
+
+##### WPA/IEEE 802.11i configuration ##########################################
+
+# Enable WPA. Setting this variable configures the AP to require WPA (either
+# WPA-PSK or WPA-RADIUS/EAP based on other configuration). For WPA-PSK, either
+# wpa_psk or wpa_passphrase must be set and wpa_key_mgmt must include WPA-PSK.
+# Instead of wpa_psk / wpa_passphrase, wpa_psk_radius might suffice.
+# For WPA-RADIUS/EAP, ieee8021x must be set (but without dynamic WEP keys),
+# RADIUS authentication server must be configured, and WPA-EAP must be included
+# in wpa_key_mgmt.
+# This field is a bit field that can be used to enable WPA (IEEE 802.11i/D3.0)
+# and/or WPA2 (full IEEE 802.11i/RSN):
+# bit0 = WPA
+# bit1 = IEEE 802.11i/RSN (WPA2) (dot11RSNAEnabled)
+wpa=1
+
+# WPA pre-shared keys for WPA-PSK. This can be either entered as a 256-bit
+# secret in hex format (64 hex digits), wpa_psk, or as an ASCII passphrase
+# (8..63 characters) that will be converted to PSK. This conversion uses SSID
+# so the PSK changes when ASCII passphrase is used and the SSID is changed.
+# wpa_psk (dot11RSNAConfigPSKValue)
+# wpa_passphrase (dot11RSNAConfigPSKPassPhrase)
+#wpa_psk=0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef
+wpa_passphrase=aaaaaaaa
+
+# Optionally, WPA PSKs can be read from a separate text file (containing list
+# of (PSK,MAC address) pairs. This allows more than one PSK to be configured.
+# Use absolute path name to make sure that the files can be read on SIGHUP
+# configuration reloads.
+#wpa_psk_file=/etc/hostapd.wpa_psk
+
+# Optionally, WPA passphrase can be received from RADIUS authentication server
+# This requires macaddr_acl to be set to 2 (RADIUS)
+# 0 = disabled (default)
+# 1 = optional; use default passphrase/psk if RADIUS server does not include
+#	Tunnel-Password
+# 2 = required; reject authentication if RADIUS server does not include
+#	Tunnel-Password
+#wpa_psk_radius=0
+
+# Set of accepted key management algorithms (WPA-PSK, WPA-EAP, or both). The
+# entries are separated with a space. WPA-PSK-SHA256 and WPA-EAP-SHA256 can be
+# added to enable SHA256-based stronger algorithms.
+# (dot11RSNAConfigAuthenticationSuitesTable)
+#wpa_key_mgmt=WPA-PSK WPA-EAP
+
+# Set of accepted cipher suites (encryption algorithms) for pairwise keys
+# (unicast packets). This is a space separated list of algorithms:
+# CCMP = AES in Counter mode with CBC-MAC [RFC 3610, IEEE 802.11i/D7.0]
+# TKIP = Temporal Key Integrity Protocol [IEEE 802.11i/D7.0]
+# Group cipher suite (encryption algorithm for broadcast and multicast frames)
+# is automatically selected based on this configuration. If only CCMP is
+# allowed as the pairwise cipher, group cipher will also be CCMP. Otherwise,
+# TKIP will be used as the group cipher.
+# (dot11RSNAConfigPairwiseCiphersTable)
+# Pairwise cipher for WPA (v1) (default: TKIP)
+#wpa_pairwise=TKIP CCMP
+wpa_pairwise=TKIP
+# Pairwise cipher for RSN/WPA2 (default: use wpa_pairwise value)
+#rsn_pairwise=CCMP
+
+# Time interval for rekeying GTK (broadcast/multicast encryption keys) in
+# seconds. (dot11RSNAConfigGroupRekeyTime)
+wpa_group_rekey=600
+
+# Rekey GTK when any STA that possesses the current GTK is leaving the BSS.
+# (dot11RSNAConfigGroupRekeyStrict)
+#wpa_strict_rekey=1
+
+# Time interval for rekeying GMK (master key used internally to generate GTKs
+# (in seconds).
+#wpa_gmk_rekey=86400
+
+# Maximum lifetime for PTK in seconds. This can be used to enforce rekeying of
+# PTK to mitigate some attacks against TKIP deficiencies.
+#wpa_ptk_rekey=600
+
+# Enable IEEE 802.11i/RSN/WPA2 pre-authentication. This is used to speed up
+# roaming be pre-authenticating IEEE 802.1X/EAP part of the full RSN
+# authentication and key handshake before actually associating with a new AP.
+# (dot11RSNAPreauthenticationEnabled)
+#rsn_preauth=1
+#
+# Space separated list of interfaces from which pre-authentication frames are
+# accepted (e.g., 'eth0' or 'eth0 wlan0wds0'. This list should include all
+# interface that are used for connections to other APs. This could include
+# wired interfaces and WDS links. The normal wireless data interface towards
+# associated stations (e.g., wlan0) should not be added, since
+# pre-authentication is only used with APs other than the currently associated
+# one.
+#rsn_preauth_interfaces=eth0
+
+# peerkey: Whether PeerKey negotiation for direct links (IEEE 802.11e) is
+# allowed. This is only used with RSN/WPA2.
+# 0 = disabled (default)
+# 1 = enabled
+#peerkey=1
+
+# ieee80211w: Whether management frame protection (MFP) is enabled
+# 0 = disabled (default)
+# 1 = optional
+# 2 = required
+#ieee80211w=0
+
+# Association SA Query maximum timeout (in TU = 1.024 ms; for MFP)
+# (maximum time to wait for a SA Query response)
+# dot11AssociationSAQueryMaximumTimeout, 1...4294967295
+#assoc_sa_query_max_timeout=1000
+
+# Association SA Query retry timeout (in TU = 1.024 ms; for MFP)
+# (time between two subsequent SA Query requests)
+# dot11AssociationSAQueryRetryTimeout, 1...4294967295
+#assoc_sa_query_retry_timeout=201
+
+# disable_pmksa_caching: Disable PMKSA caching
+# This parameter can be used to disable caching of PMKSA created through EAP
+# authentication. RSN preauthentication may still end up using PMKSA caching if
+# it is enabled (rsn_preauth=1).
+# 0 = PMKSA caching enabled (default)
+# 1 = PMKSA caching disabled
+#disable_pmksa_caching=0
+
+# okc: Opportunistic Key Caching (aka Proactive Key Caching)
+# Allow PMK cache to be shared opportunistically among configured interfaces
+# and BSSes (i.e., all configurations within a single hostapd process).
+# 0 = disabled (default)
+# 1 = enabled
+#okc=1
+
+# SAE threshold for anti-clogging mechanism (dot11RSNASAEAntiCloggingThreshold)
+# This parameter defines how many open SAE instances can be in progress at the
+# same time before the anti-clogging mechanism is taken into use.
+#sae_anti_clogging_threshold=5
+
+# Enabled SAE finite cyclic groups
+# SAE implementation are required to support group 19 (ECC group defined over a
+# 256-bit prime order field). All groups that are supported by the
+# implementation are enabled by default. This configuration parameter can be
+# used to specify a limited set of allowed groups. The group values are listed
+# in the IANA registry:
+# http://www.iana.org/assignments/ipsec-registry/ipsec-registry.xml#ipsec-registry-9
+#sae_groups=19 20 21 25 26
+
+##### IEEE 802.11r configuration ##############################################
+
+# Mobility Domain identifier (dot11FTMobilityDomainID, MDID)
+# MDID is used to indicate a group of APs (within an ESS, i.e., sharing the
+# same SSID) between which a STA can use Fast BSS Transition.
+# 2-octet identifier as a hex string.
+#mobility_domain=a1b2
+
+# PMK-R0 Key Holder identifier (dot11FTR0KeyHolderID)
+# 1 to 48 octet identifier.
+# This is configured with nas_identifier (see RADIUS client section above).
+
+# Default lifetime of the PMK-RO in minutes; range 1..65535
+# (dot11FTR0KeyLifetime)
+#r0_key_lifetime=10000
+
+# PMK-R1 Key Holder identifier (dot11FTR1KeyHolderID)
+# 6-octet identifier as a hex string.
+#r1_key_holder=000102030405
+
+# Reassociation deadline in time units (TUs / 1.024 ms; range 1000..65535)
+# (dot11FTReassociationDeadline)
+#reassociation_deadline=1000
+
+# List of R0KHs in the same Mobility Domain
+# format: <MAC address> <NAS Identifier> <128-bit key as hex string>
+# This list is used to map R0KH-ID (NAS Identifier) to a destination MAC
+# address when requesting PMK-R1 key from the R0KH that the STA used during the
+# Initial Mobility Domain Association.
+#r0kh=02:01:02:03:04:05 r0kh-1.example.com 000102030405060708090a0b0c0d0e0f
+#r0kh=02:01:02:03:04:06 r0kh-2.example.com 00112233445566778899aabbccddeeff
+# And so on.. One line per R0KH.
+
+# List of R1KHs in the same Mobility Domain
+# format: <MAC address> <R1KH-ID> <128-bit key as hex string>
+# This list is used to map R1KH-ID to a destination MAC address when sending
+# PMK-R1 key from the R0KH. This is also the list of authorized R1KHs in the MD
+# that can request PMK-R1 keys.
+#r1kh=02:01:02:03:04:05 02:11:22:33:44:55 000102030405060708090a0b0c0d0e0f
+#r1kh=02:01:02:03:04:06 02:11:22:33:44:66 00112233445566778899aabbccddeeff
+# And so on.. One line per R1KH.
+
+# Whether PMK-R1 push is enabled at R0KH
+# 0 = do not push PMK-R1 to all configured R1KHs (default)
+# 1 = push PMK-R1 to all configured R1KHs whenever a new PMK-R0 is derived
+#pmk_r1_push=1
+
+##### Neighbor table ##########################################################
+# Maximum number of entries kept in AP table (either for neigbor table or for
+# detecting Overlapping Legacy BSS Condition). The oldest entry will be
+# removed when adding a new entry that would make the list grow over this
+# limit. Note! WFA certification for IEEE 802.11g requires that OLBC is
+# enabled, so this field should not be set to 0 when using IEEE 802.11g.
+# default: 255
+#ap_table_max_size=255
+
+# Number of seconds of no frames received after which entries may be deleted
+# from the AP table. Since passive scanning is not usually performed frequently
+# this should not be set to very small value. In addition, there is no
+# guarantee that every scan cycle will receive beacon frames from the
+# neighboring APs.
+# default: 60
+#ap_table_expiration_time=3600
+
+
+##### Wi-Fi Protected Setup (WPS) #############################################
+
+# WPS state
+# 0 = WPS disabled (default)
+# 1 = WPS enabled, not configured
+# 2 = WPS enabled, configured
+#wps_state=2
+
+# Whether to manage this interface independently from other WPS interfaces
+# By default, a single hostapd process applies WPS operations to all configured
+# interfaces. This parameter can be used to disable that behavior for a subset
+# of interfaces. If this is set to non-zero for an interface, WPS commands
+# issued on that interface do not apply to other interfaces and WPS operations
+# performed on other interfaces do not affect this interface.
+#wps_independent=0
+
+# AP can be configured into a locked state where new WPS Registrar are not
+# accepted, but previously authorized Registrars (including the internal one)
+# can continue to add new Enrollees.
+#ap_setup_locked=1
+
+# Universally Unique IDentifier (UUID; see RFC 4122) of the device
+# This value is used as the UUID for the internal WPS Registrar. If the AP
+# is also using UPnP, this value should be set to the device's UPnP UUID.
+# If not configured, UUID will be generated based on the local MAC address.
+#uuid=12345678-9abc-def0-1234-56789abcdef0
+
+# Note: If wpa_psk_file is set, WPS is used to generate random, per-device PSKs
+# that will be appended to the wpa_psk_file. If wpa_psk_file is not set, the
+# default PSK (wpa_psk/wpa_passphrase) will be delivered to Enrollees. Use of
+# per-device PSKs is recommended as the more secure option (i.e., make sure to
+# set wpa_psk_file when using WPS with WPA-PSK).
+
+# When an Enrollee requests access to the network with PIN method, the Enrollee
+# PIN will need to be entered for the Registrar. PIN request notifications are
+# sent to hostapd ctrl_iface monitor. In addition, they can be written to a
+# text file that could be used, e.g., to populate the AP administration UI with
+# pending PIN requests. If the following variable is set, the PIN requests will
+# be written to the configured file.
+#wps_pin_requests=/var/run/hostapd_wps_pin_requests
+
+# Device Name
+# User-friendly description of device; up to 32 octets encoded in UTF-8
+#device_name=Wireless AP
+
+# Manufacturer
+# The manufacturer of the device (up to 64 ASCII characters)
+#manufacturer=Company
+
+# Model Name
+# Model of the device (up to 32 ASCII characters)
+#model_name=WAP
+
+# Model Number
+# Additional device description (up to 32 ASCII characters)
+#model_number=123
+
+# Serial Number
+# Serial number of the device (up to 32 characters)
+#serial_number=12345
+
+# Primary Device Type
+# Used format: <categ>-<OUI>-<subcateg>
+# categ = Category as an integer value
+# OUI = OUI and type octet as a 4-octet hex-encoded value; 0050F204 for
+#       default WPS OUI
+# subcateg = OUI-specific Sub Category as an integer value
+# Examples:
+#   1-0050F204-1 (Computer / PC)
+#   1-0050F204-2 (Computer / Server)
+#   5-0050F204-1 (Storage / NAS)
+#   6-0050F204-1 (Network Infrastructure / AP)
+#device_type=6-0050F204-1
+
+# OS Version
+# 4-octet operating system version number (hex string)
+#os_version=01020300
+
+# Config Methods
+# List of the supported configuration methods
+# Available methods: usba ethernet label display ext_nfc_token int_nfc_token
+#	nfc_interface push_button keypad virtual_display physical_display
+#	virtual_push_button physical_push_button
+#config_methods=label virtual_display virtual_push_button keypad
+
+# WPS capability discovery workaround for PBC with Windows 7
+# Windows 7 uses incorrect way of figuring out AP's WPS capabilities by acting
+# as a Registrar and using M1 from the AP. The config methods attribute in that
+# message is supposed to indicate only the configuration method supported by
+# the AP in Enrollee role, i.e., to add an external Registrar. For that case,
+# PBC shall not be used and as such, the PushButton config method is removed
+# from M1 by default. If pbc_in_m1=1 is included in the configuration file,
+# the PushButton config method is left in M1 (if included in config_methods
+# parameter) to allow Windows 7 to use PBC instead of PIN (e.g., from a label
+# in the AP).
+#pbc_in_m1=1
+
+# Static access point PIN for initial configuration and adding Registrars
+# If not set, hostapd will not allow external WPS Registrars to control the
+# access point. The AP PIN can also be set at runtime with hostapd_cli
+# wps_ap_pin command. Use of temporary (enabled by user action) and random
+# AP PIN is much more secure than configuring a static AP PIN here. As such,
+# use of the ap_pin parameter is not recommended if the AP device has means for
+# displaying a random PIN.
+#ap_pin=12345670
+
+# Skip building of automatic WPS credential
+# This can be used to allow the automatically generated Credential attribute to
+# be replaced with pre-configured Credential(s).
+#skip_cred_build=1
+
+# Additional Credential attribute(s)
+# This option can be used to add pre-configured Credential attributes into M8
+# message when acting as a Registrar. If skip_cred_build=1, this data will also
+# be able to override the Credential attribute that would have otherwise been
+# automatically generated based on network configuration. This configuration
+# option points to an external file that much contain the WPS Credential
+# attribute(s) as binary data.
+#extra_cred=hostapd.cred
+
+# Credential processing
+#   0 = process received credentials internally (default)
+#   1 = do not process received credentials; just pass them over ctrl_iface to
+#	external program(s)
+#   2 = process received credentials internally and pass them over ctrl_iface
+#	to external program(s)
+# Note: With wps_cred_processing=1, skip_cred_build should be set to 1 and
+# extra_cred be used to provide the Credential data for Enrollees.
+#
+# wps_cred_processing=1 will disabled automatic updates of hostapd.conf file
+# both for Credential processing and for marking AP Setup Locked based on
+# validation failures of AP PIN. An external program is responsible on updating
+# the configuration appropriately in this case.
+#wps_cred_processing=0
+
+# AP Settings Attributes for M7
+# By default, hostapd generates the AP Settings Attributes for M7 based on the
+# current configuration. It is possible to override this by providing a file
+# with pre-configured attributes. This is similar to extra_cred file format,
+# but the AP Settings attributes are not encapsulated in a Credential
+# attribute.
+#ap_settings=hostapd.ap_settings
+
+# WPS UPnP interface
+# If set, support for external Registrars is enabled.
+#upnp_iface=br0
+
+# Friendly Name (required for UPnP)
+# Short description for end use. Should be less than 64 characters.
+#friendly_name=WPS Access Point
+
+# Manufacturer URL (optional for UPnP)
+#manufacturer_url=http://www.example.com/
+
+# Model Description (recommended for UPnP)
+# Long description for end user. Should be less than 128 characters.
+#model_description=Wireless Access Point
+
+# Model URL (optional for UPnP)
+#model_url=http://www.example.com/model/
+
+# Universal Product Code (optional for UPnP)
+# 12-digit, all-numeric code that identifies the consumer package.
+#upc=123456789012
+
+# WPS RF Bands (a = 5G, b = 2.4G, g = 2.4G, ag = dual band)
+# This value should be set according to RF band(s) supported by the AP if
+# hw_mode is not set. For dual band dual concurrent devices, this needs to be
+# set to ag to allow both RF bands to be advertized.
+#wps_rf_bands=ag
+
+# NFC password token for WPS
+# These parameters can be used to configure a fixed NFC password token for the
+# AP. This can be generated, e.g., with nfc_pw_token from wpa_supplicant. When
+# these parameters are used, the AP is assumed to be deployed with a NFC tag
+# that includes the matching NFC password token (e.g., written based on the
+# NDEF record from nfc_pw_token).
+#
+#wps_nfc_dev_pw_id: Device Password ID (16..65535)
+#wps_nfc_dh_pubkey: Hexdump of DH Public Key
+#wps_nfc_dh_privkey: Hexdump of DH Private Key
+#wps_nfc_dev_pw: Hexdump of Device Password
+
+##### Wi-Fi Direct (P2P) ######################################################
+
+# Enable P2P Device management
+#manage_p2p=1
+
+# Allow cross connection
+#allow_cross_connection=1
+
+#### TDLS (IEEE 802.11z-2010) #################################################
+
+# Prohibit use of TDLS in this BSS
+#tdls_prohibit=1
+
+# Prohibit use of TDLS Channel Switching in this BSS
+#tdls_prohibit_chan_switch=1
+
+##### IEEE 802.11v-2011 #######################################################
+
+# Time advertisement
+# 0 = disabled (default)
+# 2 = UTC time at which the TSF timer is 0
+#time_advertisement=2
+
+# Local time zone as specified in 8.3 of IEEE Std 1003.1-2004:
+# stdoffset[dst[offset][,start[/time],end[/time]]]
+#time_zone=EST5
+
+# WNM-Sleep Mode (extended sleep mode for stations)
+# 0 = disabled (default)
+# 1 = enabled (allow stations to use WNM-Sleep Mode)
+#wnm_sleep_mode=1
+
+# BSS Transition Management
+# 0 = disabled (default)
+# 1 = enabled
+#bss_transition=1
+
+##### IEEE 802.11u-2011 #######################################################
+
+# Enable Interworking service
+#interworking=1
+
+# Access Network Type
+# 0 = Private network
+# 1 = Private network with guest access
+# 2 = Chargeable public network
+# 3 = Free public network
+# 4 = Personal device network
+# 5 = Emergency services only network
+# 14 = Test or experimental
+# 15 = Wildcard
+#access_network_type=0
+
+# Whether the network provides connectivity to the Internet
+# 0 = Unspecified
+# 1 = Network provides connectivity to the Internet
+#internet=1
+
+# Additional Step Required for Access
+# Note: This is only used with open network, i.e., ASRA shall ne set to 0 if
+# RSN is used.
+#asra=0
+
+# Emergency services reachable
+#esr=0
+
+# Unauthenticated emergency service accessible
+#uesa=0
+
+# Venue Info (optional)
+# The available values are defined in IEEE Std 802.11u-2011, 7.3.1.34.
+# Example values (group,type):
+# 0,0 = Unspecified
+# 1,7 = Convention Center
+# 1,13 = Coffee Shop
+# 2,0 = Unspecified Business
+# 7,1  Private Residence
+#venue_group=7
+#venue_type=1
+
+# Homogeneous ESS identifier (optional; dot11HESSID)
+# If set, this shall be identifical to one of the BSSIDs in the homogeneous
+# ESS and this shall be set to the same value across all BSSs in homogeneous
+# ESS.
+#hessid=02:03:04:05:06:07
+
+# Roaming Consortium List
+# Arbitrary number of Roaming Consortium OIs can be configured with each line
+# adding a new OI to the list. The first three entries are available through
+# Beacon and Probe Response frames. Any additional entry will be available only
+# through ANQP queries. Each OI is between 3 and 15 octets and is configured as
+# a hexstring.
+#roaming_consortium=021122
+#roaming_consortium=2233445566
+
+# Venue Name information
+# This parameter can be used to configure one or more Venue Name Duples for
+# Venue Name ANQP information. Each entry has a two or three character language
+# code (ISO-639) separated by colon from the venue name string.
+# Note that venue_group and venue_type have to be set for Venue Name
+# information to be complete.
+#venue_name=eng:Example venue
+#venue_name=fin:Esimerkkipaikka
+# Alternative format for language:value strings:
+# (double quoted string, printf-escaped string)
+#venue_name=P"eng:Example\nvenue"
+
+# Network Authentication Type
+# This parameter indicates what type of network authentication is used in the
+# network.
+# format: <network auth type indicator (1-octet hex str)> [redirect URL]
+# Network Authentication Type Indicator values:
+# 00 = Acceptance of terms and conditions
+# 01 = On-line enrollment supported
+# 02 = http/https redirection
+# 03 = DNS redirection
+#network_auth_type=00
+#network_auth_type=02http://www.example.com/redirect/me/here/
+
+# IP Address Type Availability
+# format: <1-octet encoded value as hex str>
+# (ipv4_type & 0x3f) << 2 | (ipv6_type & 0x3)
+# ipv4_type:
+# 0 = Address type not available
+# 1 = Public IPv4 address available
+# 2 = Port-restricted IPv4 address available
+# 3 = Single NATed private IPv4 address available
+# 4 = Double NATed private IPv4 address available
+# 5 = Port-restricted IPv4 address and single NATed IPv4 address available
+# 6 = Port-restricted IPv4 address and double NATed IPv4 address available
+# 7 = Availability of the address type is not known
+# ipv6_type:
+# 0 = Address type not available
+# 1 = Address type available
+# 2 = Availability of the address type not known
+#ipaddr_type_availability=14
+
+# Domain Name
+# format: <variable-octet str>[,<variable-octet str>]
+#domain_name=example.com,another.example.com,yet-another.example.com
+
+# 3GPP Cellular Network information
+# format: <MCC1,MNC1>[;<MCC2,MNC2>][;...]
+#anqp_3gpp_cell_net=244,91;310,026;234,56
+
+# NAI Realm information
+# One or more realm can be advertised. Each nai_realm line adds a new realm to
+# the set. These parameters provide information for stations using Interworking
+# network selection to allow automatic connection to a network based on
+# credentials.
+# format: <encoding>,<NAI Realm(s)>[,<EAP Method 1>][,<EAP Method 2>][,...]
+# encoding:
+#	0 = Realm formatted in accordance with IETF RFC 4282
+#	1 = UTF-8 formatted character string that is not formatted in
+#	    accordance with IETF RFC 4282
+# NAI Realm(s): Semi-colon delimited NAI Realm(s)
+# EAP Method: <EAP Method>[:<[AuthParam1:Val1]>][<[AuthParam2:Val2]>][...]
+# AuthParam (Table 8-188 in IEEE Std 802.11-2012):
+# ID 2 = Non-EAP Inner Authentication Type
+#	1 = PAP, 2 = CHAP, 3 = MSCHAP, 4 = MSCHAPV2
+# ID 3 = Inner authentication EAP Method Type
+# ID 5 = Credential Type
+#	1 = SIM, 2 = USIM, 3 = NFC Secure Element, 4 = Hardware Token,
+#	5 = Softoken, 6 = Certificate, 7 = username/password, 9 = Anonymous,
+#	10 = Vendor Specific
+#nai_realm=0,example.com;example.net
+# EAP methods EAP-TLS with certificate and EAP-TTLS/MSCHAPv2 with
+# username/password
+#nai_realm=0,example.org,13[5:6],21[2:4][5:7]
+
+# QoS Map Set configuration
+#
+# Comma delimited QoS Map Set in decimal values
+# (see IEEE Std 802.11-2012, 8.4.2.97)
+#
+# format:
+# [<DSCP Exceptions[DSCP,UP]>,]<UP 0 range[low,high]>,...<UP 7 range[low,high]>
+#
+# There can be up to 21 optional DSCP Exceptions which are pairs of DSCP Value
+# (0..63 or 255) and User Priority (0..7). This is followed by eight DSCP Range
+# descriptions with DSCP Low Value and DSCP High Value pairs (0..63 or 255) for
+# each UP starting from 0. If both low and high value are set to 255, the
+# corresponding UP is not used.
+#
+# default: not set
+#qos_map_set=53,2,22,6,8,15,0,7,255,255,16,31,32,39,255,255,40,47,255,255
+
+##### Hotspot 2.0 #############################################################
+
+# Enable Hotspot 2.0 support
+#hs20=1
+
+# Disable Downstream Group-Addressed Forwarding (DGAF)
+# This can be used to configure a network where no group-addressed frames are
+# allowed. The AP will not forward any group-address frames to the stations and
+# random GTKs are issued for each station to prevent associated stations from
+# forging such frames to other stations in the BSS.
+#disable_dgaf=1
+
+# Operator Friendly Name
+# This parameter can be used to configure one or more Operator Friendly Name
+# Duples. Each entry has a two or three character language code (ISO-639)
+# separated by colon from the operator friendly name string.
+#hs20_oper_friendly_name=eng:Example operator
+#hs20_oper_friendly_name=fin:Esimerkkioperaattori
+
+# Connection Capability
+# This can be used to advertise what type of IP traffic can be sent through the
+# hotspot (e.g., due to firewall allowing/blocking protocols/ports).
+# format: <IP Protocol>:<Port Number>:<Status>
+# IP Protocol: 1 = ICMP, 6 = TCP, 17 = UDP
+# Port Number: 0..65535
+# Status: 0 = Closed, 1 = Open, 2 = Unknown
+# Each hs20_conn_capab line is added to the list of advertised tuples.
+#hs20_conn_capab=1:0:2
+#hs20_conn_capab=6:22:1
+#hs20_conn_capab=17:5060:0
+
+# WAN Metrics
+# format: <WAN Info>:<DL Speed>:<UL Speed>:<DL Load>:<UL Load>:<LMD>
+# WAN Info: B0-B1: Link Status, B2: Symmetric Link, B3: At Capabity
+#    (encoded as two hex digits)
+#    Link Status: 1 = Link up, 2 = Link down, 3 = Link in test state
+# Downlink Speed: Estimate of WAN backhaul link current downlink speed in kbps;
+#	1..4294967295; 0 = unknown
+# Uplink Speed: Estimate of WAN backhaul link current uplink speed in kbps
+#	1..4294967295; 0 = unknown
+# Downlink Load: Current load of downlink WAN connection (scaled to 255 = 100%)
+# Uplink Load: Current load of uplink WAN connection (scaled to 255 = 100%)
+# Load Measurement Duration: Duration for measuring downlink/uplink load in
+# tenths of a second (1..65535); 0 if load cannot be determined
+#hs20_wan_metrics=01:8000:1000:80:240:3000
+
+# Operating Class Indication
+# List of operating classes the BSSes in this ESS use. The Global operating
+# classes in Table E-4 of IEEE Std 802.11-2012 Annex E define the values that
+# can be used in this.
+# format: hexdump of operating class octets
+# for example, operating classes 81 (2.4 GHz channels 1-13) and 115 (5 GHz
+# channels 36-48):
+#hs20_operating_class=5173
+
+##### TESTING OPTIONS #########################################################
+#
+# The options in this section are only available when the build configuration
+# option CONFIG_TESTING_OPTIONS is set while compiling hostapd. They allow
+# testing some scenarios that are otherwise difficult to reproduce.
+#
+# Ignore probe requests sent to hostapd with the given probability, must be a
+# floating point number in the range [0, 1).
+#ignore_probe_probability=0.0
+#
+# Ignore authentication frames with the given probability
+#ignore_auth_probability=0.0
+#
+# Ignore association requests with the given probability
+#ignore_assoc_probability=0.0
+#
+# Ignore reassociation requests with the given probability
+#ignore_reassoc_probability=0.0
+#
+# Corrupt Key MIC in GTK rekey EAPOL-Key frames with the given probability
+#corrupt_gtk_rekey_mic_probability=0.0
+
+##### Multiple BSSID support ##################################################
+#
+# Above configuration is using the default interface (wlan#, or multi-SSID VLAN
+# interfaces). Other BSSIDs can be added by using separator 'bss' with
+# default interface name to be allocated for the data packets of the new BSS.
+#
+# hostapd will generate BSSID mask based on the BSSIDs that are
+# configured. hostapd will verify that dev_addr & MASK == dev_addr. If this is
+# not the case, the MAC address of the radio must be changed before starting
+# hostapd (ifconfig wlan0 hw ether <MAC addr>). If a BSSID is configured for
+# every secondary BSS, this limitation is not applied at hostapd and other
+# masks may be used if the driver supports them (e.g., swap the locally
+# administered bit)
+#
+# BSSIDs are assigned in order to each BSS, unless an explicit BSSID is
+# specified using the 'bssid' parameter.
+# If an explicit BSSID is specified, it must be chosen such that it:
+# - results in a valid MASK that covers it and the dev_addr
+# - is not the same as the MAC address of the radio
+# - is not the same as any other explicitly specified BSSID
+#
+# Please note that hostapd uses some of the values configured for the first BSS
+# as the defaults for the following BSSes. However, it is recommended that all
+# BSSes include explicit configuration of all relevant configuration items.
+#
+#bss=wlan0_0
+#ssid=test2
+# most of the above items can be used here (apart from radio interface specific
+# items, like channel)
+
+#bss=wlan0_1
+#bssid=00:13:10:95:fe:0b
+# ...
diff --git a/drivers/net/wireless/ssv6x5x/script/hostapd.conf.template b/drivers/net/wireless/ssv6x5x/script/hostapd.conf.template
new file mode 100755
index 000000000..e8fa0ba5d
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/hostapd.conf.template
@@ -0,0 +1,1663 @@
+##### hostapd configuration file ##############################################
+# Empty lines and lines starting with # are ignored
+
+# AP netdevice name (without 'ap' postfix, i.e., wlan0 uses wlan0ap for
+# management frames); ath0 for madwifi
+interface=HOSTAPD_IF
+
+# In case of madwifi, atheros, and nl80211 driver interfaces, an additional
+# configuration parameter, bridge, may be used to notify hostapd if the
+# interface is included in a bridge. This parameter is not used with Host AP
+# driver. If the bridge parameter is not set, the drivers will automatically
+# figure out the bridge interface (assuming sysfs is enabled and mounted to
+# /sys) and this parameter may not be needed.
+#
+# For nl80211, this parameter can be used to request the AP interface to be
+# added to the bridge automatically (brctl may refuse to do this before hostapd
+# has been started to change the interface mode). If needed, the bridge
+# interface is also created.
+#bridge=br0
+
+# Driver interface type (hostap/wired/madwifi/test/none/nl80211/bsd);
+# default: hostap). nl80211 is used with all Linux mac80211 drivers.
+# Use driver=none if building hostapd as a standalone RADIUS server that does
+# not control any wireless/wired driver.
+# driver=hostap
+
+# hostapd event logger configuration
+#
+# Two output method: syslog and stdout (only usable if not forking to
+# background).
+#
+# Module bitfield (ORed bitfield of modules that will be logged; -1 = all
+# modules):
+# bit 0 (1) = IEEE 802.11
+# bit 1 (2) = IEEE 802.1X
+# bit 2 (4) = RADIUS
+# bit 3 (8) = WPA
+# bit 4 (16) = driver interface
+# bit 5 (32) = IAPP
+# bit 6 (64) = MLME
+#
+# Levels (minimum value for logged events):
+#  0 = verbose debugging
+#  1 = debugging
+#  2 = informational messages
+#  3 = notification
+#  4 = warning
+#
+logger_syslog=1
+logger_syslog_level=0
+logger_stdout=1
+logger_stdout_level=0
+
+# Interface for separate control program. If this is specified, hostapd
+# will create this directory and a UNIX domain socket for listening to requests
+# from external programs (CLI/GUI, etc.) for status information and
+# configuration. The socket file will be named based on the interface name, so
+# multiple hostapd processes/interfaces can be run at the same time if more
+# than one interface is used.
+# /var/run/hostapd is the recommended directory for sockets and by default,
+# hostapd_cli will use it when trying to connect with hostapd.
+ctrl_interface=/var/run/hostapd
+
+# Access control for the control interface can be configured by setting the
+# directory to allow only members of a group to use sockets. This way, it is
+# possible to run hostapd as root (since it needs to change network
+# configuration and open raw sockets) and still allow GUI/CLI components to be
+# run as non-root users. However, since the control interface can be used to
+# change the network configuration, this access needs to be protected in many
+# cases. By default, hostapd is configured to use gid 0 (root). If you
+# want to allow non-root users to use the contron interface, add a new group
+# and change this value to match with that group. Add users that should have
+# control interface access to this group.
+#
+# This variable can be a group name or gid.
+#ctrl_interface_group=wheel
+ctrl_interface_group=0
+
+
+##### IEEE 802.11 related configuration #######################################
+
+# SSID to be used in IEEE 802.11 management frames
+ssid=test
+# Alternative formats for configuring SSID
+# (double quoted string, hexdump, printf-escaped string)
+#ssid2="test"
+#ssid2=74657374
+#ssid2=P"hello\nthere"
+
+# UTF-8 SSID: Whether the SSID is to be interpreted using UTF-8 encoding
+#utf8_ssid=1
+
+# Country code (ISO/IEC 3166-1). Used to set regulatory domain.
+# Set as needed to indicate country in which device is operating.
+# This can limit available channels and transmit power.
+#country_code=US
+
+# Enable IEEE 802.11d. This advertises the country_code and the set of allowed
+# channels and transmit power levels based on the regulatory limits. The
+# country_code setting must be configured with the correct country for
+# IEEE 802.11d functions.
+# (default: 0 = disabled)
+#ieee80211d=1
+
+# Enable IEEE 802.11h. This enables radar detection and DFS support if
+# available. DFS support is required on outdoor 5 GHz channels in most countries
+# of the world. This can be used only with ieee80211d=1.
+# (default: 0 = disabled)
+#ieee80211h=1
+
+# Operation mode (a = IEEE 802.11a, b = IEEE 802.11b, g = IEEE 802.11g,
+# ad = IEEE 802.11ad (60 GHz); a/g options are used with IEEE 802.11n, too, to
+# specify band)
+# Default: IEEE 802.11b
+hw_mode=g
+
+# Channel number (IEEE 802.11)
+# (default: 0, i.e., not set)
+# Please note that some drivers do not use this value from hostapd and the
+# channel will need to be configured separately with iwconfig.
+#
+# If CONFIG_ACS build option is enabled, the channel can be selected
+# automatically at run time by setting channel=acs_survey or channel=0, both of
+# which will enable the ACS survey based algorithm.
+channel=1
+
+# ACS tuning - Automatic Channel Selection
+# See: http://wireless.kernel.org/en/users/Documentation/acs
+#
+# You can customize the ACS survey algorithm with following variables:
+#
+# acs_num_scans requirement is 1..100 - number of scans to be performed that
+# are used to trigger survey data gathering of an underlying device driver.
+# Scans are passive and typically take a little over 100ms (depending on the
+# driver) on each available channel for given hw_mode. Increasing this value
+# means sacrificing startup time and gathering more data wrt channel
+# interference that may help choosing a better channel. This can also help fine
+# tune the ACS scan time in case a driver has different scan dwell times.
+#
+# Defaults:
+#acs_num_scans=5
+
+# Beacon interval in kus (1.024 ms) (default: 100; range 15..65535)
+beacon_int=100
+
+# DTIM (delivery traffic information message) period (range 1..255):
+# number of beacons between DTIMs (1 = every beacon includes DTIM element)
+# (default: 2)
+dtim_period=2
+
+# Maximum number of stations allowed in station table. New stations will be
+# rejected after the station table is full. IEEE 802.11 has a limit of 2007
+# different association IDs, so this number should not be larger than that.
+# (default: 2007)
+max_num_sta=255
+
+# RTS/CTS threshold; 2347 = disabled (default); range 0..2347
+# If this field is not included in hostapd.conf, hostapd will not control
+# RTS threshold and 'iwconfig wlan# rts <val>' can be used to set it.
+rts_threshold=2347
+
+# Fragmentation threshold; 2346 = disabled (default); range 256..2346
+# If this field is not included in hostapd.conf, hostapd will not control
+# fragmentation threshold and 'iwconfig wlan# frag <val>' can be used to set
+# it.
+fragm_threshold=2346
+
+# Rate configuration
+# Default is to enable all rates supported by the hardware. This configuration
+# item allows this list be filtered so that only the listed rates will be left
+# in the list. If the list is empty, all rates are used. This list can have
+# entries that are not in the list of rates the hardware supports (such entries
+# are ignored). The entries in this list are in 100 kbps, i.e., 11 Mbps = 110.
+# If this item is present, at least one rate have to be matching with the rates
+# hardware supports.
+# default: use the most common supported rate setting for the selected
+# hw_mode (i.e., this line can be removed from configuration file in most
+# cases)
+#supported_rates=10 20 55 110 60 90 120 180 240 360 480 540
+
+# Basic rate set configuration
+# List of rates (in 100 kbps) that are included in the basic rate set.
+# If this item is not included, usually reasonable default set is used.
+#basic_rates=10 20
+#basic_rates=10 20 55 110
+#basic_rates=60 120 240
+
+# Short Preamble
+# This parameter can be used to enable optional use of short preamble for
+# frames sent at 2 Mbps, 5.5 Mbps, and 11 Mbps to improve network performance.
+# This applies only to IEEE 802.11b-compatible networks and this should only be
+# enabled if the local hardware supports use of short preamble. If any of the
+# associated STAs do not support short preamble, use of short preamble will be
+# disabled (and enabled when such STAs disassociate) dynamically.
+# 0 = do not allow use of short preamble (default)
+# 1 = allow use of short preamble
+#preamble=1
+
+# Station MAC address -based authentication
+# Please note that this kind of access control requires a driver that uses
+# hostapd to take care of management frame processing and as such, this can be
+# used with driver=hostap or driver=nl80211, but not with driver=madwifi.
+# 0 = accept unless in deny list
+# 1 = deny unless in accept list
+# 2 = use external RADIUS server (accept/deny lists are searched first)
+macaddr_acl=0
+
+# Accept/deny lists are read from separate files (containing list of
+# MAC addresses, one per line). Use absolute path name to make sure that the
+# files can be read on SIGHUP configuration reloads.
+#accept_mac_file=/etc/hostapd.accept
+#deny_mac_file=/etc/hostapd.deny
+
+# IEEE 802.11 specifies two authentication algorithms. hostapd can be
+# configured to allow both of these or only one. Open system authentication
+# should be used with IEEE 802.1X.
+# Bit fields of allowed authentication algorithms:
+# bit 0 = Open System Authentication
+# bit 1 = Shared Key Authentication (requires WEP)
+auth_algs=3
+
+# Send empty SSID in beacons and ignore probe request frames that do not
+# specify full SSID, i.e., require stations to know SSID.
+# default: disabled (0)
+# 1 = send empty (length=0) SSID in beacon and ignore probe request for
+#     broadcast SSID
+# 2 = clear SSID (ASCII 0), but keep the original length (this may be required
+#     with some clients that do not support empty SSID) and ignore probe
+#     requests for broadcast SSID
+ignore_broadcast_ssid=0
+
+# Additional vendor specfic elements for Beacon and Probe Response frames
+# This parameter can be used to add additional vendor specific element(s) into
+# the end of the Beacon and Probe Response frames. The format for these
+# element(s) is a hexdump of the raw information elements (id+len+payload for
+# one or more elements)
+#vendor_elements=dd0411223301
+
+# TX queue parameters (EDCF / bursting)
+# tx_queue_<queue name>_<param>
+# queues: data0, data1, data2, data3, after_beacon, beacon
+#		(data0 is the highest priority queue)
+# parameters:
+#   aifs: AIFS (default 2)
+#   cwmin: cwMin (1, 3, 7, 15, 31, 63, 127, 255, 511, 1023)
+#   cwmax: cwMax (1, 3, 7, 15, 31, 63, 127, 255, 511, 1023); cwMax >= cwMin
+#   burst: maximum length (in milliseconds with precision of up to 0.1 ms) for
+#          bursting
+#
+# Default WMM parameters (IEEE 802.11 draft; 11-03-0504-03-000e):
+# These parameters are used by the access point when transmitting frames
+# to the clients.
+#
+# Low priority / AC_BK = background
+#tx_queue_data3_aifs=7
+#tx_queue_data3_cwmin=15
+#tx_queue_data3_cwmax=1023
+#tx_queue_data3_burst=0
+# Note: for IEEE 802.11b mode: cWmin=31 cWmax=1023 burst=0
+#
+# Normal priority / AC_BE = best effort
+#tx_queue_data2_aifs=3
+#tx_queue_data2_cwmin=15
+#tx_queue_data2_cwmax=63
+#tx_queue_data2_burst=0
+# Note: for IEEE 802.11b mode: cWmin=31 cWmax=127 burst=0
+#
+# High priority / AC_VI = video
+#tx_queue_data1_aifs=1
+#tx_queue_data1_cwmin=7
+#tx_queue_data1_cwmax=15
+#tx_queue_data1_burst=3.0
+# Note: for IEEE 802.11b mode: cWmin=15 cWmax=31 burst=6.0
+#
+# Highest priority / AC_VO = voice
+#tx_queue_data0_aifs=1
+#tx_queue_data0_cwmin=3
+#tx_queue_data0_cwmax=7
+#tx_queue_data0_burst=1.5
+# Note: for IEEE 802.11b mode: cWmin=7 cWmax=15 burst=3.3
+
+# 802.1D Tag (= UP) to AC mappings
+# WMM specifies following mapping of data frames to different ACs. This mapping
+# can be configured using Linux QoS/tc and sch_pktpri.o module.
+# 802.1D Tag	802.1D Designation	Access Category	WMM Designation
+# 1		BK			AC_BK		Background
+# 2		-			AC_BK		Background
+# 0		BE			AC_BE		Best Effort
+# 3		EE			AC_BE		Best Effort
+# 4		CL			AC_VI		Video
+# 5		VI			AC_VI		Video
+# 6		VO			AC_VO		Voice
+# 7		NC			AC_VO		Voice
+# Data frames with no priority information: AC_BE
+# Management frames: AC_VO
+# PS-Poll frames: AC_BE
+
+# Default WMM parameters (IEEE 802.11 draft; 11-03-0504-03-000e):
+# for 802.11a or 802.11g networks
+# These parameters are sent to WMM clients when they associate.
+# The parameters will be used by WMM clients for frames transmitted to the
+# access point.
+#
+# note - txop_limit is in units of 32microseconds
+# note - acm is admission control mandatory flag. 0 = admission control not
+# required, 1 = mandatory
+# note - here cwMin and cmMax are in exponent form. the actual cw value used
+# will be (2^n)-1 where n is the value given here
+#
+wmm_enabled=1
+#
+# WMM-PS Unscheduled Automatic Power Save Delivery [U-APSD]
+# Enable this flag if U-APSD supported outside hostapd (eg., Firmware/driver)
+#uapsd_advertisement_enabled=1
+#
+# Low priority / AC_BK = background
+wmm_ac_bk_cwmin=4
+wmm_ac_bk_cwmax=10
+wmm_ac_bk_aifs=7
+wmm_ac_bk_txop_limit=0
+wmm_ac_bk_acm=0
+# Note: for IEEE 802.11b mode: cWmin=5 cWmax=10
+#
+# Normal priority / AC_BE = best effort
+wmm_ac_be_aifs=3
+wmm_ac_be_cwmin=4
+wmm_ac_be_cwmax=10
+wmm_ac_be_txop_limit=0
+wmm_ac_be_acm=0
+# Note: for IEEE 802.11b mode: cWmin=5 cWmax=7
+#
+# High priority / AC_VI = video
+wmm_ac_vi_aifs=2
+wmm_ac_vi_cwmin=3
+wmm_ac_vi_cwmax=4
+wmm_ac_vi_txop_limit=94
+wmm_ac_vi_acm=0
+# Note: for IEEE 802.11b mode: cWmin=4 cWmax=5 txop_limit=188
+#
+# Highest priority / AC_VO = voice
+wmm_ac_vo_aifs=2
+wmm_ac_vo_cwmin=2
+wmm_ac_vo_cwmax=3
+wmm_ac_vo_txop_limit=47
+wmm_ac_vo_acm=0
+# Note: for IEEE 802.11b mode: cWmin=3 cWmax=4 burst=102
+
+# Static WEP key configuration
+#
+# The key number to use when transmitting.
+# It must be between 0 and 3, and the corresponding key must be set.
+# default: not set
+#wep_default_key=0
+# The WEP keys to use.
+# A key may be a quoted string or unquoted hexadecimal digits.
+# The key length should be 5, 13, or 16 characters, or 10, 26, or 32
+# digits, depending on whether 40-bit (64-bit), 104-bit (128-bit), or
+# 128-bit (152-bit) WEP is used.
+# Only the default key must be supplied; the others are optional.
+# default: not set
+#wep_key0=123456789a
+#wep_key1="vwxyz"
+#wep_key2=0102030405060708090a0b0c0d
+#wep_key3=".2.4.6.8.0.23"
+
+# Station inactivity limit
+#
+# If a station does not send anything in ap_max_inactivity seconds, an
+# empty data frame is sent to it in order to verify whether it is
+# still in range. If this frame is not ACKed, the station will be
+# disassociated and then deauthenticated. This feature is used to
+# clear station table of old entries when the STAs move out of the
+# range.
+#
+# The station can associate again with the AP if it is still in range;
+# this inactivity poll is just used as a nicer way of verifying
+# inactivity; i.e., client will not report broken connection because
+# disassociation frame is not sent immediately without first polling
+# the STA with a data frame.
+# default: 300 (i.e., 5 minutes)
+#ap_max_inactivity=300
+#
+# The inactivity polling can be disabled to disconnect stations based on
+# inactivity timeout so that idle stations are more likely to be disconnected
+# even if they are still in range of the AP. This can be done by setting
+# skip_inactivity_poll to 1 (default 0).
+#skip_inactivity_poll=0
+
+# Disassociate stations based on excessive transmission failures or other
+# indications of connection loss. This depends on the driver capabilities and
+# may not be available with all drivers.
+#disassoc_low_ack=1
+
+# Maximum allowed Listen Interval (how many Beacon periods STAs are allowed to
+# remain asleep). Default: 65535 (no limit apart from field size)
+#max_listen_interval=100
+
+# WDS (4-address frame) mode with per-station virtual interfaces
+# (only supported with driver=nl80211)
+# This mode allows associated stations to use 4-address frames to allow layer 2
+# bridging to be used.
+#wds_sta=1
+
+# If bridge parameter is set, the WDS STA interface will be added to the same
+# bridge by default. This can be overridden with the wds_bridge parameter to
+# use a separate bridge.
+#wds_bridge=wds-br0
+
+# Start the AP with beaconing disabled by default.
+#start_disabled=0
+
+# Client isolation can be used to prevent low-level bridging of frames between
+# associated stations in the BSS. By default, this bridging is allowed.
+#ap_isolate=1
+
+# Fixed BSS Load value for testing purposes
+# This field can be used to configure hostapd to add a fixed BSS Load element
+# into Beacon and Probe Response frames for testing purposes. The format is
+# <station count>:<channel utilization>:<available admission capacity>
+#bss_load_test=12:80:20000
+
+##### IEEE 802.11n related configuration ######################################
+
+# ieee80211n: Whether IEEE 802.11n (HT) is enabled
+# 0 = disabled (default)
+# 1 = enabled
+# Note: You will also need to enable WMM for full HT functionality.
+ieee80211n=1
+
+# ht_capab: HT capabilities (list of flags)
+# LDPC coding capability: [LDPC] = supported
+# Supported channel width set: [HT40-] = both 20 MHz and 40 MHz with secondary
+#	channel below the primary channel; [HT40+] = both 20 MHz and 40 MHz
+#	with secondary channel below the primary channel
+#	(20 MHz only if neither is set)
+#	Note: There are limits on which channels can be used with HT40- and
+#	HT40+. Following table shows the channels that may be available for
+#	HT40- and HT40+ use per IEEE 802.11n Annex J:
+#	freq		HT40-		HT40+
+#	2.4 GHz		5-13		1-7 (1-9 in Europe/Japan)
+#	5 GHz		40,48,56,64	36,44,52,60
+#	(depending on the location, not all of these channels may be available
+#	for use)
+#	Please note that 40 MHz channels may switch their primary and secondary
+#	channels if needed or creation of 40 MHz channel maybe rejected based
+#	on overlapping BSSes. These changes are done automatically when hostapd
+#	is setting up the 40 MHz channel.
+# Spatial Multiplexing (SM) Power Save: [SMPS-STATIC] or [SMPS-DYNAMIC]
+#	(SMPS disabled if neither is set)
+# HT-greenfield: [GF] (disabled if not set)
+# Short GI for 20 MHz: [SHORT-GI-20] (disabled if not set)
+# Short GI for 40 MHz: [SHORT-GI-40] (disabled if not set)
+# Tx STBC: [TX-STBC] (disabled if not set)
+# Rx STBC: [RX-STBC1] (one spatial stream), [RX-STBC12] (one or two spatial
+#	streams), or [RX-STBC123] (one, two, or three spatial streams); Rx STBC
+#	disabled if none of these set
+# HT-delayed Block Ack: [DELAYED-BA] (disabled if not set)
+# Maximum A-MSDU length: [MAX-AMSDU-7935] for 7935 octets (3839 octets if not
+#	set)
+# DSSS/CCK Mode in 40 MHz: [DSSS_CCK-40] = allowed (not allowed if not set)
+# PSMP support: [PSMP] (disabled if not set)
+# L-SIG TXOP protection support: [LSIG-TXOP-PROT] (disabled if not set)
+#ht_capab=[HT40-][SHORT-GI-20][SHORT-GI-40]
+
+# Require stations to support HT PHY (reject association if they do not)
+#require_ht=1
+
+# If set non-zero, require stations to perform scans of overlapping
+# channels to test for stations which would be affected by 40 MHz traffic.
+# This parameter sets the interval in seconds between these scans. This
+# is useful only for testing that stations properly set the OBSS interval,
+# since the other parameters in the OBSS scan parameters IE are set to 0.
+#obss_interval=0
+
+##### IEEE 802.11ac related configuration #####################################
+
+# ieee80211ac: Whether IEEE 802.11ac (VHT) is enabled
+# 0 = disabled (default)
+# 1 = enabled
+# Note: You will also need to enable WMM for full VHT functionality.
+#ieee80211ac=1
+
+# vht_capab: VHT capabilities (list of flags)
+#
+# vht_max_mpdu_len: [MAX-MPDU-7991] [MAX-MPDU-11454]
+# Indicates maximum MPDU length
+# 0 = 3895 octets (default)
+# 1 = 7991 octets
+# 2 = 11454 octets
+# 3 = reserved
+#
+# supported_chan_width: [VHT160] [VHT160-80PLUS80]
+# Indicates supported Channel widths
+# 0 = 160 MHz & 80+80 channel widths are not supported (default)
+# 1 = 160 MHz channel width is supported
+# 2 = 160 MHz & 80+80 channel widths are supported
+# 3 = reserved
+#
+# Rx LDPC coding capability: [RXLDPC]
+# Indicates support for receiving LDPC coded pkts
+# 0 = Not supported (default)
+# 1 = Supported
+#
+# Short GI for 80 MHz: [SHORT-GI-80]
+# Indicates short GI support for reception of packets transmitted with TXVECTOR
+# params format equal to VHT and CBW = 80Mhz
+# 0 = Not supported (default)
+# 1 = Supported
+#
+# Short GI for 160 MHz: [SHORT-GI-160]
+# Indicates short GI support for reception of packets transmitted with TXVECTOR
+# params format equal to VHT and CBW = 160Mhz
+# 0 = Not supported (default)
+# 1 = Supported
+#
+# Tx STBC: [TX-STBC-2BY1]
+# Indicates support for the transmission of at least 2x1 STBC
+# 0 = Not supported (default)
+# 1 = Supported
+#
+# Rx STBC: [RX-STBC-1] [RX-STBC-12] [RX-STBC-123] [RX-STBC-1234]
+# Indicates support for the reception of PPDUs using STBC
+# 0 = Not supported (default)
+# 1 = support of one spatial stream
+# 2 = support of one and two spatial streams
+# 3 = support of one, two and three spatial streams
+# 4 = support of one, two, three and four spatial streams
+# 5,6,7 = reserved
+#
+# SU Beamformer Capable: [SU-BEAMFORMER]
+# Indicates support for operation as a single user beamformer
+# 0 = Not supported (default)
+# 1 = Supported
+#
+# SU Beamformee Capable: [SU-BEAMFORMEE]
+# Indicates support for operation as a single user beamformee
+# 0 = Not supported (default)
+# 1 = Supported
+#
+# Compressed Steering Number of Beamformer Antennas Supported: [BF-ANTENNA-2]
+#   Beamformee's capability indicating the maximum number of beamformer
+#   antennas the beamformee can support when sending compressed beamforming
+#   feedback
+# If SU beamformer capable, set to maximum value minus 1
+# else reserved (default)
+#
+# Number of Sounding Dimensions: [SOUNDING-DIMENSION-2]
+# Beamformer's capability indicating the maximum value of the NUM_STS parameter
+# in the TXVECTOR of a VHT NDP
+# If SU beamformer capable, set to maximum value minus 1
+# else reserved (default)
+#
+# MU Beamformer Capable: [MU-BEAMFORMER]
+# Indicates support for operation as an MU beamformer
+# 0 = Not supported or sent by Non-AP STA (default)
+# 1 = Supported
+#
+# MU Beamformee Capable: [MU-BEAMFORMEE]
+# Indicates support for operation as an MU beamformee
+# 0 = Not supported or sent by AP (default)
+# 1 = Supported
+#
+# VHT TXOP PS: [VHT-TXOP-PS]
+# Indicates whether or not the AP supports VHT TXOP Power Save Mode
+#  or whether or not the STA is in VHT TXOP Power Save mode
+# 0 = VHT AP doesnt support VHT TXOP PS mode (OR) VHT Sta not in VHT TXOP PS
+#  mode
+# 1 = VHT AP supports VHT TXOP PS mode (OR) VHT Sta is in VHT TXOP power save
+#  mode
+#
+# +HTC-VHT Capable: [HTC-VHT]
+# Indicates whether or not the STA supports receiving a VHT variant HT Control
+# field.
+# 0 = Not supported (default)
+# 1 = supported
+#
+# Maximum A-MPDU Length Exponent: [MAX-A-MPDU-LEN-EXP0]..[MAX-A-MPDU-LEN-EXP7]
+# Indicates the maximum length of A-MPDU pre-EOF padding that the STA can recv
+# This field is an integer in the range of 0 to 7.
+# The length defined by this field is equal to
+# 2 pow(13 + Maximum A-MPDU Length Exponent) -1 octets
+#
+# VHT Link Adaptation Capable: [VHT-LINK-ADAPT2] [VHT-LINK-ADAPT3]
+# Indicates whether or not the STA supports link adaptation using VHT variant
+# HT Control field
+# If +HTC-VHTcapable is 1
+#  0 = (no feedback) if the STA does not provide VHT MFB (default)
+#  1 = reserved
+#  2 = (Unsolicited) if the STA provides only unsolicited VHT MFB
+#  3 = (Both) if the STA can provide VHT MFB in response to VHT MRQ and if the
+#      STA provides unsolicited VHT MFB
+# Reserved if +HTC-VHTcapable is 0
+#
+# Rx Antenna Pattern Consistency: [RX-ANTENNA-PATTERN]
+# Indicates the possibility of Rx antenna pattern change
+# 0 = Rx antenna pattern might change during the lifetime of an association
+# 1 = Rx antenna pattern does not change during the lifetime of an association
+#
+# Tx Antenna Pattern Consistency: [TX-ANTENNA-PATTERN]
+# Indicates the possibility of Tx antenna pattern change
+# 0 = Tx antenna pattern might change during the lifetime of an association
+# 1 = Tx antenna pattern does not change during the lifetime of an association
+#vht_capab=[SHORT-GI-80][HTC-VHT]
+#
+# Require stations to support VHT PHY (reject association if they do not)
+#require_vht=1
+
+# 0 = 20 or 40 MHz operating Channel width
+# 1 = 80 MHz channel width
+# 2 = 160 MHz channel width
+# 3 = 80+80 MHz channel width
+#vht_oper_chwidth=1
+#
+# center freq = 5 GHz + (5 * index)
+# So index 42 gives center freq 5.210 GHz
+# which is channel 42 in 5G band
+#
+#vht_oper_centr_freq_seg0_idx=42
+#
+# center freq = 5 GHz + (5 * index)
+# So index 159 gives center freq 5.795 GHz
+# which is channel 159 in 5G band
+#
+#vht_oper_centr_freq_seg1_idx=159
+
+##### IEEE 802.1X-2004 related configuration ##################################
+
+# Require IEEE 802.1X authorization
+#ieee8021x=1
+
+# IEEE 802.1X/EAPOL version
+# hostapd is implemented based on IEEE Std 802.1X-2004 which defines EAPOL
+# version 2. However, there are many client implementations that do not handle
+# the new version number correctly (they seem to drop the frames completely).
+# In order to make hostapd interoperate with these clients, the version number
+# can be set to the older version (1) with this configuration value.
+#eapol_version=2
+
+# Optional displayable message sent with EAP Request-Identity. The first \0
+# in this string will be converted to ASCII-0 (nul). This can be used to
+# separate network info (comma separated list of attribute=value pairs); see,
+# e.g., RFC 4284.
+#eap_message=hello
+#eap_message=hello\0networkid=netw,nasid=foo,portid=0,NAIRealms=example.com
+
+# WEP rekeying (disabled if key lengths are not set or are set to 0)
+# Key lengths for default/broadcast and individual/unicast keys:
+# 5 = 40-bit WEP (also known as 64-bit WEP with 40 secret bits)
+# 13 = 104-bit WEP (also known as 128-bit WEP with 104 secret bits)
+#wep_key_len_broadcast=5
+#wep_key_len_unicast=5
+# Rekeying period in seconds. 0 = do not rekey (i.e., set keys only once)
+#wep_rekey_period=300
+
+# EAPOL-Key index workaround (set bit7) for WinXP Supplicant (needed only if
+# only broadcast keys are used)
+eapol_key_index_workaround=0
+
+# EAP reauthentication period in seconds (default: 3600 seconds; 0 = disable
+# reauthentication).
+#eap_reauth_period=3600
+
+# Use PAE group address (01:80:c2:00:00:03) instead of individual target
+# address when sending EAPOL frames with driver=wired. This is the most common
+# mechanism used in wired authentication, but it also requires that the port
+# is only used by one station.
+#use_pae_group_addr=1
+
+##### Integrated EAP server ###################################################
+
+# Optionally, hostapd can be configured to use an integrated EAP server
+# to process EAP authentication locally without need for an external RADIUS
+# server. This functionality can be used both as a local authentication server
+# for IEEE 802.1X/EAPOL and as a RADIUS server for other devices.
+
+# Use integrated EAP server instead of external RADIUS authentication
+# server. This is also needed if hostapd is configured to act as a RADIUS
+# authentication server.
+eap_server=0
+
+# Path for EAP server user database
+# If SQLite support is included, this can be set to "sqlite:/path/to/sqlite.db"
+# to use SQLite database instead of a text file.
+#eap_user_file=/etc/hostapd.eap_user
+
+# CA certificate (PEM or DER file) for EAP-TLS/PEAP/TTLS
+#ca_cert=/etc/hostapd.ca.pem
+
+# Server certificate (PEM or DER file) for EAP-TLS/PEAP/TTLS
+#server_cert=/etc/hostapd.server.pem
+
+# Private key matching with the server certificate for EAP-TLS/PEAP/TTLS
+# This may point to the same file as server_cert if both certificate and key
+# are included in a single file. PKCS#12 (PFX) file (.p12/.pfx) can also be
+# used by commenting out server_cert and specifying the PFX file as the
+# private_key.
+#private_key=/etc/hostapd.server.prv
+
+# Passphrase for private key
+#private_key_passwd=secret passphrase
+
+# Server identity
+# EAP methods that provide mechanism for authenticated server identity delivery
+# use this value. If not set, "hostapd" is used as a default.
+#server_id=server.example.com
+
+# Enable CRL verification.
+# Note: hostapd does not yet support CRL downloading based on CDP. Thus, a
+# valid CRL signed by the CA is required to be included in the ca_cert file.
+# This can be done by using PEM format for CA certificate and CRL and
+# concatenating these into one file. Whenever CRL changes, hostapd needs to be
+# restarted to take the new CRL into use.
+# 0 = do not verify CRLs (default)
+# 1 = check the CRL of the user certificate
+# 2 = check all CRLs in the certificate path
+#check_crl=1
+
+# Cached OCSP stapling response (DER encoded)
+# If set, this file is sent as a certificate status response by the EAP server
+# if the EAP peer requests certificate status in the ClientHello message.
+# This cache file can be updated, e.g., by running following command
+# periodically to get an update from the OCSP responder:
+# openssl ocsp \
+#	-no_nonce \
+#	-CAfile /etc/hostapd.ca.pem \
+#	-issuer /etc/hostapd.ca.pem \
+#	-cert /etc/hostapd.server.pem \
+#	-url http://ocsp.example.com:8888/ \
+#	-respout /tmp/ocsp-cache.der
+#ocsp_stapling_response=/tmp/ocsp-cache.der
+
+# dh_file: File path to DH/DSA parameters file (in PEM format)
+# This is an optional configuration file for setting parameters for an
+# ephemeral DH key exchange. In most cases, the default RSA authentication does
+# not use this configuration. However, it is possible setup RSA to use
+# ephemeral DH key exchange. In addition, ciphers with DSA keys always use
+# ephemeral DH keys. This can be used to achieve forward secrecy. If the file
+# is in DSA parameters format, it will be automatically converted into DH
+# params. This parameter is required if anonymous EAP-FAST is used.
+# You can generate DH parameters file with OpenSSL, e.g.,
+# "openssl dhparam -out /etc/hostapd.dh.pem 1024"
+#dh_file=/etc/hostapd.dh.pem
+
+# Fragment size for EAP methods
+#fragment_size=1400
+
+# Finite cyclic group for EAP-pwd. Number maps to group of domain parameters
+# using the IANA repository for IKE (RFC 2409).
+#pwd_group=19
+
+# Configuration data for EAP-SIM database/authentication gateway interface.
+# This is a text string in implementation specific format. The example
+# implementation in eap_sim_db.c uses this as the UNIX domain socket name for
+# the HLR/AuC gateway (e.g., hlr_auc_gw). In this case, the path uses "unix:"
+# prefix. If hostapd is built with SQLite support (CONFIG_SQLITE=y in .config),
+# database file can be described with an optional db=<path> parameter.
+#eap_sim_db=unix:/tmp/hlr_auc_gw.sock
+#eap_sim_db=unix:/tmp/hlr_auc_gw.sock db=/tmp/hostapd.db
+
+# Encryption key for EAP-FAST PAC-Opaque values. This key must be a secret,
+# random value. It is configured as a 16-octet value in hex format. It can be
+# generated, e.g., with the following command:
+# od -tx1 -v -N16 /dev/random | colrm 1 8 | tr -d ' '
+#pac_opaque_encr_key=000102030405060708090a0b0c0d0e0f
+
+# EAP-FAST authority identity (A-ID)
+# A-ID indicates the identity of the authority that issues PACs. The A-ID
+# should be unique across all issuing servers. In theory, this is a variable
+# length field, but due to some existing implementations requiring A-ID to be
+# 16 octets in length, it is strongly recommended to use that length for the
+# field to provid interoperability with deployed peer implementations. This
+# field is configured in hex format.
+#eap_fast_a_id=101112131415161718191a1b1c1d1e1f
+
+# EAP-FAST authority identifier information (A-ID-Info)
+# This is a user-friendly name for the A-ID. For example, the enterprise name
+# and server name in a human-readable format. This field is encoded as UTF-8.
+#eap_fast_a_id_info=test server
+
+# Enable/disable different EAP-FAST provisioning modes:
+#0 = provisioning disabled
+#1 = only anonymous provisioning allowed
+#2 = only authenticated provisioning allowed
+#3 = both provisioning modes allowed (default)
+#eap_fast_prov=3
+
+# EAP-FAST PAC-Key lifetime in seconds (hard limit)
+#pac_key_lifetime=604800
+
+# EAP-FAST PAC-Key refresh time in seconds (soft limit on remaining hard
+# limit). The server will generate a new PAC-Key when this number of seconds
+# (or fewer) of the lifetime remains.
+#pac_key_refresh_time=86400
+
+# EAP-SIM and EAP-AKA protected success/failure indication using AT_RESULT_IND
+# (default: 0 = disabled).
+#eap_sim_aka_result_ind=1
+
+# Trusted Network Connect (TNC)
+# If enabled, TNC validation will be required before the peer is allowed to
+# connect. Note: This is only used with EAP-TTLS and EAP-FAST. If any other
+# EAP method is enabled, the peer will be allowed to connect without TNC.
+#tnc=1
+
+
+##### IEEE 802.11f - Inter-Access Point Protocol (IAPP) #######################
+
+# Interface to be used for IAPP broadcast packets
+#iapp_interface=eth0
+
+
+##### RADIUS client configuration #############################################
+# for IEEE 802.1X with external Authentication Server, IEEE 802.11
+# authentication with external ACL for MAC addresses, and accounting
+
+# The own IP address of the access point (used as NAS-IP-Address)
+own_ip_addr=127.0.0.1
+
+# Optional NAS-Identifier string for RADIUS messages. When used, this should be
+# a unique to the NAS within the scope of the RADIUS server. For example, a
+# fully qualified domain name can be used here.
+# When using IEEE 802.11r, nas_identifier must be set and must be between 1 and
+# 48 octets long.
+#nas_identifier=ap.example.com
+
+# RADIUS authentication server
+#auth_server_addr=127.0.0.1
+#auth_server_port=1812
+#auth_server_shared_secret=secret
+
+# RADIUS accounting server
+#acct_server_addr=127.0.0.1
+#acct_server_port=1813
+#acct_server_shared_secret=secret
+
+# Secondary RADIUS servers; to be used if primary one does not reply to
+# RADIUS packets. These are optional and there can be more than one secondary
+# server listed.
+#auth_server_addr=127.0.0.2
+#auth_server_port=1812
+#auth_server_shared_secret=secret2
+#
+#acct_server_addr=127.0.0.2
+#acct_server_port=1813
+#acct_server_shared_secret=secret2
+
+# Retry interval for trying to return to the primary RADIUS server (in
+# seconds). RADIUS client code will automatically try to use the next server
+# when the current server is not replying to requests. If this interval is set,
+# primary server will be retried after configured amount of time even if the
+# currently used secondary server is still working.
+#radius_retry_primary_interval=600
+
+
+# Interim accounting update interval
+# If this is set (larger than 0) and acct_server is configured, hostapd will
+# send interim accounting updates every N seconds. Note: if set, this overrides
+# possible Acct-Interim-Interval attribute in Access-Accept message. Thus, this
+# value should not be configured in hostapd.conf, if RADIUS server is used to
+# control the interim interval.
+# This value should not be less 600 (10 minutes) and must not be less than
+# 60 (1 minute).
+#radius_acct_interim_interval=600
+
+# Request Chargeable-User-Identity (RFC 4372)
+# This parameter can be used to configure hostapd to request CUI from the
+# RADIUS server by including Chargeable-User-Identity attribute into
+# Access-Request packets.
+#radius_request_cui=1
+
+# Dynamic VLAN mode; allow RADIUS authentication server to decide which VLAN
+# is used for the stations. This information is parsed from following RADIUS
+# attributes based on RFC 3580 and RFC 2868: Tunnel-Type (value 13 = VLAN),
+# Tunnel-Medium-Type (value 6 = IEEE 802), Tunnel-Private-Group-ID (value
+# VLANID as a string). Optionally, the local MAC ACL list (accept_mac_file) can
+# be used to set static client MAC address to VLAN ID mapping.
+# 0 = disabled (default)
+# 1 = option; use default interface if RADIUS server does not include VLAN ID
+# 2 = required; reject authentication if RADIUS server does not include VLAN ID
+#dynamic_vlan=0
+
+# VLAN interface list for dynamic VLAN mode is read from a separate text file.
+# This list is used to map VLAN ID from the RADIUS server to a network
+# interface. Each station is bound to one interface in the same way as with
+# multiple BSSIDs or SSIDs. Each line in this text file is defining a new
+# interface and the line must include VLAN ID and interface name separated by
+# white space (space or tab).
+# If no entries are provided by this file, the station is statically mapped
+# to <bss-iface>.<vlan-id> interfaces.
+#vlan_file=/etc/hostapd.vlan
+
+# Interface where 802.1q tagged packets should appear when a RADIUS server is
+# used to determine which VLAN a station is on.  hostapd creates a bridge for
+# each VLAN.  Then hostapd adds a VLAN interface (associated with the interface
+# indicated by 'vlan_tagged_interface') and the appropriate wireless interface
+# to the bridge.
+#vlan_tagged_interface=eth0
+
+# Bridge (prefix) to add the wifi and the tagged interface to. This gets the
+# VLAN ID appended. It defaults to brvlan%d if no tagged interface is given
+# and br%s.%d if a tagged interface is given, provided %s = tagged interface
+# and %d = VLAN ID.
+#vlan_bridge=brvlan
+
+# When hostapd creates a VLAN interface on vlan_tagged_interfaces, it needs
+# to know how to name it.
+# 0 = vlan<XXX>, e.g., vlan1
+# 1 = <vlan_tagged_interface>.<XXX>, e.g. eth0.1
+#vlan_naming=0
+
+# Arbitrary RADIUS attributes can be added into Access-Request and
+# Accounting-Request packets by specifying the contents of the attributes with
+# the following configuration parameters. There can be multiple of these to
+# add multiple attributes. These parameters can also be used to override some
+# of the attributes added automatically by hostapd.
+# Format: <attr_id>[:<syntax:value>]
+# attr_id: RADIUS attribute type (e.g., 26 = Vendor-Specific)
+# syntax: s = string (UTF-8), d = integer, x = octet string
+# value: attribute value in format indicated by the syntax
+# If syntax and value parts are omitted, a null value (single 0x00 octet) is
+# used.
+#
+# Additional Access-Request attributes
+# radius_auth_req_attr=<attr_id>[:<syntax:value>]
+# Examples:
+# Operator-Name = "Operator"
+#radius_auth_req_attr=126:s:Operator
+# Service-Type = Framed (2)
+#radius_auth_req_attr=6:d:2
+# Connect-Info = "testing" (this overrides the automatically generated value)
+#radius_auth_req_attr=77:s:testing
+# Same Connect-Info value set as a hexdump
+#radius_auth_req_attr=77:x:74657374696e67
+
+#
+# Additional Accounting-Request attributes
+# radius_acct_req_attr=<attr_id>[:<syntax:value>]
+# Examples:
+# Operator-Name = "Operator"
+#radius_acct_req_attr=126:s:Operator
+
+# Dynamic Authorization Extensions (RFC 5176)
+# This mechanism can be used to allow dynamic changes to user session based on
+# commands from a RADIUS server (or some other disconnect client that has the
+# needed session information). For example, Disconnect message can be used to
+# request an associated station to be disconnected.
+#
+# This is disabled by default. Set radius_das_port to non-zero UDP port
+# number to enable.
+#radius_das_port=3799
+#
+# DAS client (the host that can send Disconnect/CoA requests) and shared secret
+#radius_das_client=192.168.1.123 shared secret here
+#
+# DAS Event-Timestamp time window in seconds
+#radius_das_time_window=300
+#
+# DAS require Event-Timestamp
+#radius_das_require_event_timestamp=1
+
+##### RADIUS authentication server configuration ##############################
+
+# hostapd can be used as a RADIUS authentication server for other hosts. This
+# requires that the integrated EAP server is also enabled and both
+# authentication services are sharing the same configuration.
+
+# File name of the RADIUS clients configuration for the RADIUS server. If this
+# commented out, RADIUS server is disabled.
+#radius_server_clients=/etc/hostapd.radius_clients
+
+# The UDP port number for the RADIUS authentication server
+#radius_server_auth_port=1812
+
+# Use IPv6 with RADIUS server (IPv4 will also be supported using IPv6 API)
+#radius_server_ipv6=1
+
+
+##### WPA/IEEE 802.11i configuration ##########################################
+
+# Enable WPA. Setting this variable configures the AP to require WPA (either
+# WPA-PSK or WPA-RADIUS/EAP based on other configuration). For WPA-PSK, either
+# wpa_psk or wpa_passphrase must be set and wpa_key_mgmt must include WPA-PSK.
+# Instead of wpa_psk / wpa_passphrase, wpa_psk_radius might suffice.
+# For WPA-RADIUS/EAP, ieee8021x must be set (but without dynamic WEP keys),
+# RADIUS authentication server must be configured, and WPA-EAP must be included
+# in wpa_key_mgmt.
+# This field is a bit field that can be used to enable WPA (IEEE 802.11i/D3.0)
+# and/or WPA2 (full IEEE 802.11i/RSN):
+# bit0 = WPA
+# bit1 = IEEE 802.11i/RSN (WPA2) (dot11RSNAEnabled)
+#wpa=1
+
+# WPA pre-shared keys for WPA-PSK. This can be either entered as a 256-bit
+# secret in hex format (64 hex digits), wpa_psk, or as an ASCII passphrase
+# (8..63 characters) that will be converted to PSK. This conversion uses SSID
+# so the PSK changes when ASCII passphrase is used and the SSID is changed.
+# wpa_psk (dot11RSNAConfigPSKValue)
+# wpa_passphrase (dot11RSNAConfigPSKPassPhrase)
+#wpa_psk=0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef
+#wpa_passphrase=secret passphrase
+
+# Optionally, WPA PSKs can be read from a separate text file (containing list
+# of (PSK,MAC address) pairs. This allows more than one PSK to be configured.
+# Use absolute path name to make sure that the files can be read on SIGHUP
+# configuration reloads.
+#wpa_psk_file=/etc/hostapd.wpa_psk
+
+# Optionally, WPA passphrase can be received from RADIUS authentication server
+# This requires macaddr_acl to be set to 2 (RADIUS)
+# 0 = disabled (default)
+# 1 = optional; use default passphrase/psk if RADIUS server does not include
+#	Tunnel-Password
+# 2 = required; reject authentication if RADIUS server does not include
+#	Tunnel-Password
+#wpa_psk_radius=0
+
+# Set of accepted key management algorithms (WPA-PSK, WPA-EAP, or both). The
+# entries are separated with a space. WPA-PSK-SHA256 and WPA-EAP-SHA256 can be
+# added to enable SHA256-based stronger algorithms.
+# (dot11RSNAConfigAuthenticationSuitesTable)
+#wpa_key_mgmt=WPA-PSK WPA-EAP
+
+# Set of accepted cipher suites (encryption algorithms) for pairwise keys
+# (unicast packets). This is a space separated list of algorithms:
+# CCMP = AES in Counter mode with CBC-MAC [RFC 3610, IEEE 802.11i/D7.0]
+# TKIP = Temporal Key Integrity Protocol [IEEE 802.11i/D7.0]
+# Group cipher suite (encryption algorithm for broadcast and multicast frames)
+# is automatically selected based on this configuration. If only CCMP is
+# allowed as the pairwise cipher, group cipher will also be CCMP. Otherwise,
+# TKIP will be used as the group cipher.
+# (dot11RSNAConfigPairwiseCiphersTable)
+# Pairwise cipher for WPA (v1) (default: TKIP)
+#wpa_pairwise=TKIP CCMP
+# Pairwise cipher for RSN/WPA2 (default: use wpa_pairwise value)
+#rsn_pairwise=CCMP
+
+# Time interval for rekeying GTK (broadcast/multicast encryption keys) in
+# seconds. (dot11RSNAConfigGroupRekeyTime)
+#wpa_group_rekey=600
+
+# Rekey GTK when any STA that possesses the current GTK is leaving the BSS.
+# (dot11RSNAConfigGroupRekeyStrict)
+#wpa_strict_rekey=1
+
+# Time interval for rekeying GMK (master key used internally to generate GTKs
+# (in seconds).
+#wpa_gmk_rekey=86400
+
+# Maximum lifetime for PTK in seconds. This can be used to enforce rekeying of
+# PTK to mitigate some attacks against TKIP deficiencies.
+#wpa_ptk_rekey=600
+
+# Enable IEEE 802.11i/RSN/WPA2 pre-authentication. This is used to speed up
+# roaming be pre-authenticating IEEE 802.1X/EAP part of the full RSN
+# authentication and key handshake before actually associating with a new AP.
+# (dot11RSNAPreauthenticationEnabled)
+#rsn_preauth=1
+#
+# Space separated list of interfaces from which pre-authentication frames are
+# accepted (e.g., 'eth0' or 'eth0 wlan0wds0'. This list should include all
+# interface that are used for connections to other APs. This could include
+# wired interfaces and WDS links. The normal wireless data interface towards
+# associated stations (e.g., wlan0) should not be added, since
+# pre-authentication is only used with APs other than the currently associated
+# one.
+#rsn_preauth_interfaces=eth0
+
+# peerkey: Whether PeerKey negotiation for direct links (IEEE 802.11e) is
+# allowed. This is only used with RSN/WPA2.
+# 0 = disabled (default)
+# 1 = enabled
+#peerkey=1
+
+# ieee80211w: Whether management frame protection (MFP) is enabled
+# 0 = disabled (default)
+# 1 = optional
+# 2 = required
+#ieee80211w=0
+
+# Association SA Query maximum timeout (in TU = 1.024 ms; for MFP)
+# (maximum time to wait for a SA Query response)
+# dot11AssociationSAQueryMaximumTimeout, 1...4294967295
+#assoc_sa_query_max_timeout=1000
+
+# Association SA Query retry timeout (in TU = 1.024 ms; for MFP)
+# (time between two subsequent SA Query requests)
+# dot11AssociationSAQueryRetryTimeout, 1...4294967295
+#assoc_sa_query_retry_timeout=201
+
+# disable_pmksa_caching: Disable PMKSA caching
+# This parameter can be used to disable caching of PMKSA created through EAP
+# authentication. RSN preauthentication may still end up using PMKSA caching if
+# it is enabled (rsn_preauth=1).
+# 0 = PMKSA caching enabled (default)
+# 1 = PMKSA caching disabled
+#disable_pmksa_caching=0
+
+# okc: Opportunistic Key Caching (aka Proactive Key Caching)
+# Allow PMK cache to be shared opportunistically among configured interfaces
+# and BSSes (i.e., all configurations within a single hostapd process).
+# 0 = disabled (default)
+# 1 = enabled
+#okc=1
+
+# SAE threshold for anti-clogging mechanism (dot11RSNASAEAntiCloggingThreshold)
+# This parameter defines how many open SAE instances can be in progress at the
+# same time before the anti-clogging mechanism is taken into use.
+#sae_anti_clogging_threshold=5
+
+# Enabled SAE finite cyclic groups
+# SAE implementation are required to support group 19 (ECC group defined over a
+# 256-bit prime order field). All groups that are supported by the
+# implementation are enabled by default. This configuration parameter can be
+# used to specify a limited set of allowed groups. The group values are listed
+# in the IANA registry:
+# http://www.iana.org/assignments/ipsec-registry/ipsec-registry.xml#ipsec-registry-9
+#sae_groups=19 20 21 25 26
+
+##### IEEE 802.11r configuration ##############################################
+
+# Mobility Domain identifier (dot11FTMobilityDomainID, MDID)
+# MDID is used to indicate a group of APs (within an ESS, i.e., sharing the
+# same SSID) between which a STA can use Fast BSS Transition.
+# 2-octet identifier as a hex string.
+#mobility_domain=a1b2
+
+# PMK-R0 Key Holder identifier (dot11FTR0KeyHolderID)
+# 1 to 48 octet identifier.
+# This is configured with nas_identifier (see RADIUS client section above).
+
+# Default lifetime of the PMK-RO in minutes; range 1..65535
+# (dot11FTR0KeyLifetime)
+#r0_key_lifetime=10000
+
+# PMK-R1 Key Holder identifier (dot11FTR1KeyHolderID)
+# 6-octet identifier as a hex string.
+#r1_key_holder=000102030405
+
+# Reassociation deadline in time units (TUs / 1.024 ms; range 1000..65535)
+# (dot11FTReassociationDeadline)
+#reassociation_deadline=1000
+
+# List of R0KHs in the same Mobility Domain
+# format: <MAC address> <NAS Identifier> <128-bit key as hex string>
+# This list is used to map R0KH-ID (NAS Identifier) to a destination MAC
+# address when requesting PMK-R1 key from the R0KH that the STA used during the
+# Initial Mobility Domain Association.
+#r0kh=02:01:02:03:04:05 r0kh-1.example.com 000102030405060708090a0b0c0d0e0f
+#r0kh=02:01:02:03:04:06 r0kh-2.example.com 00112233445566778899aabbccddeeff
+# And so on.. One line per R0KH.
+
+# List of R1KHs in the same Mobility Domain
+# format: <MAC address> <R1KH-ID> <128-bit key as hex string>
+# This list is used to map R1KH-ID to a destination MAC address when sending
+# PMK-R1 key from the R0KH. This is also the list of authorized R1KHs in the MD
+# that can request PMK-R1 keys.
+#r1kh=02:01:02:03:04:05 02:11:22:33:44:55 000102030405060708090a0b0c0d0e0f
+#r1kh=02:01:02:03:04:06 02:11:22:33:44:66 00112233445566778899aabbccddeeff
+# And so on.. One line per R1KH.
+
+# Whether PMK-R1 push is enabled at R0KH
+# 0 = do not push PMK-R1 to all configured R1KHs (default)
+# 1 = push PMK-R1 to all configured R1KHs whenever a new PMK-R0 is derived
+#pmk_r1_push=1
+
+##### Neighbor table ##########################################################
+# Maximum number of entries kept in AP table (either for neigbor table or for
+# detecting Overlapping Legacy BSS Condition). The oldest entry will be
+# removed when adding a new entry that would make the list grow over this
+# limit. Note! WFA certification for IEEE 802.11g requires that OLBC is
+# enabled, so this field should not be set to 0 when using IEEE 802.11g.
+# default: 255
+#ap_table_max_size=255
+
+# Number of seconds of no frames received after which entries may be deleted
+# from the AP table. Since passive scanning is not usually performed frequently
+# this should not be set to very small value. In addition, there is no
+# guarantee that every scan cycle will receive beacon frames from the
+# neighboring APs.
+# default: 60
+#ap_table_expiration_time=3600
+
+
+##### Wi-Fi Protected Setup (WPS) #############################################
+
+# WPS state
+# 0 = WPS disabled (default)
+# 1 = WPS enabled, not configured
+# 2 = WPS enabled, configured
+#wps_state=2
+
+# Whether to manage this interface independently from other WPS interfaces
+# By default, a single hostapd process applies WPS operations to all configured
+# interfaces. This parameter can be used to disable that behavior for a subset
+# of interfaces. If this is set to non-zero for an interface, WPS commands
+# issued on that interface do not apply to other interfaces and WPS operations
+# performed on other interfaces do not affect this interface.
+#wps_independent=0
+
+# AP can be configured into a locked state where new WPS Registrar are not
+# accepted, but previously authorized Registrars (including the internal one)
+# can continue to add new Enrollees.
+#ap_setup_locked=1
+
+# Universally Unique IDentifier (UUID; see RFC 4122) of the device
+# This value is used as the UUID for the internal WPS Registrar. If the AP
+# is also using UPnP, this value should be set to the device's UPnP UUID.
+# If not configured, UUID will be generated based on the local MAC address.
+#uuid=12345678-9abc-def0-1234-56789abcdef0
+
+# Note: If wpa_psk_file is set, WPS is used to generate random, per-device PSKs
+# that will be appended to the wpa_psk_file. If wpa_psk_file is not set, the
+# default PSK (wpa_psk/wpa_passphrase) will be delivered to Enrollees. Use of
+# per-device PSKs is recommended as the more secure option (i.e., make sure to
+# set wpa_psk_file when using WPS with WPA-PSK).
+
+# When an Enrollee requests access to the network with PIN method, the Enrollee
+# PIN will need to be entered for the Registrar. PIN request notifications are
+# sent to hostapd ctrl_iface monitor. In addition, they can be written to a
+# text file that could be used, e.g., to populate the AP administration UI with
+# pending PIN requests. If the following variable is set, the PIN requests will
+# be written to the configured file.
+#wps_pin_requests=/var/run/hostapd_wps_pin_requests
+
+# Device Name
+# User-friendly description of device; up to 32 octets encoded in UTF-8
+#device_name=Wireless AP
+
+# Manufacturer
+# The manufacturer of the device (up to 64 ASCII characters)
+#manufacturer=Company
+
+# Model Name
+# Model of the device (up to 32 ASCII characters)
+#model_name=WAP
+
+# Model Number
+# Additional device description (up to 32 ASCII characters)
+#model_number=123
+
+# Serial Number
+# Serial number of the device (up to 32 characters)
+#serial_number=12345
+
+# Primary Device Type
+# Used format: <categ>-<OUI>-<subcateg>
+# categ = Category as an integer value
+# OUI = OUI and type octet as a 4-octet hex-encoded value; 0050F204 for
+#       default WPS OUI
+# subcateg = OUI-specific Sub Category as an integer value
+# Examples:
+#   1-0050F204-1 (Computer / PC)
+#   1-0050F204-2 (Computer / Server)
+#   5-0050F204-1 (Storage / NAS)
+#   6-0050F204-1 (Network Infrastructure / AP)
+#device_type=6-0050F204-1
+
+# OS Version
+# 4-octet operating system version number (hex string)
+#os_version=01020300
+
+# Config Methods
+# List of the supported configuration methods
+# Available methods: usba ethernet label display ext_nfc_token int_nfc_token
+#	nfc_interface push_button keypad virtual_display physical_display
+#	virtual_push_button physical_push_button
+#config_methods=label virtual_display virtual_push_button keypad
+
+# WPS capability discovery workaround for PBC with Windows 7
+# Windows 7 uses incorrect way of figuring out AP's WPS capabilities by acting
+# as a Registrar and using M1 from the AP. The config methods attribute in that
+# message is supposed to indicate only the configuration method supported by
+# the AP in Enrollee role, i.e., to add an external Registrar. For that case,
+# PBC shall not be used and as such, the PushButton config method is removed
+# from M1 by default. If pbc_in_m1=1 is included in the configuration file,
+# the PushButton config method is left in M1 (if included in config_methods
+# parameter) to allow Windows 7 to use PBC instead of PIN (e.g., from a label
+# in the AP).
+#pbc_in_m1=1
+
+# Static access point PIN for initial configuration and adding Registrars
+# If not set, hostapd will not allow external WPS Registrars to control the
+# access point. The AP PIN can also be set at runtime with hostapd_cli
+# wps_ap_pin command. Use of temporary (enabled by user action) and random
+# AP PIN is much more secure than configuring a static AP PIN here. As such,
+# use of the ap_pin parameter is not recommended if the AP device has means for
+# displaying a random PIN.
+#ap_pin=12345670
+
+# Skip building of automatic WPS credential
+# This can be used to allow the automatically generated Credential attribute to
+# be replaced with pre-configured Credential(s).
+#skip_cred_build=1
+
+# Additional Credential attribute(s)
+# This option can be used to add pre-configured Credential attributes into M8
+# message when acting as a Registrar. If skip_cred_build=1, this data will also
+# be able to override the Credential attribute that would have otherwise been
+# automatically generated based on network configuration. This configuration
+# option points to an external file that much contain the WPS Credential
+# attribute(s) as binary data.
+#extra_cred=hostapd.cred
+
+# Credential processing
+#   0 = process received credentials internally (default)
+#   1 = do not process received credentials; just pass them over ctrl_iface to
+#	external program(s)
+#   2 = process received credentials internally and pass them over ctrl_iface
+#	to external program(s)
+# Note: With wps_cred_processing=1, skip_cred_build should be set to 1 and
+# extra_cred be used to provide the Credential data for Enrollees.
+#
+# wps_cred_processing=1 will disabled automatic updates of hostapd.conf file
+# both for Credential processing and for marking AP Setup Locked based on
+# validation failures of AP PIN. An external program is responsible on updating
+# the configuration appropriately in this case.
+#wps_cred_processing=0
+
+# AP Settings Attributes for M7
+# By default, hostapd generates the AP Settings Attributes for M7 based on the
+# current configuration. It is possible to override this by providing a file
+# with pre-configured attributes. This is similar to extra_cred file format,
+# but the AP Settings attributes are not encapsulated in a Credential
+# attribute.
+#ap_settings=hostapd.ap_settings
+
+# WPS UPnP interface
+# If set, support for external Registrars is enabled.
+#upnp_iface=br0
+
+# Friendly Name (required for UPnP)
+# Short description for end use. Should be less than 64 characters.
+#friendly_name=WPS Access Point
+
+# Manufacturer URL (optional for UPnP)
+#manufacturer_url=http://www.example.com/
+
+# Model Description (recommended for UPnP)
+# Long description for end user. Should be less than 128 characters.
+#model_description=Wireless Access Point
+
+# Model URL (optional for UPnP)
+#model_url=http://www.example.com/model/
+
+# Universal Product Code (optional for UPnP)
+# 12-digit, all-numeric code that identifies the consumer package.
+#upc=123456789012
+
+# WPS RF Bands (a = 5G, b = 2.4G, g = 2.4G, ag = dual band)
+# This value should be set according to RF band(s) supported by the AP if
+# hw_mode is not set. For dual band dual concurrent devices, this needs to be
+# set to ag to allow both RF bands to be advertized.
+#wps_rf_bands=ag
+
+# NFC password token for WPS
+# These parameters can be used to configure a fixed NFC password token for the
+# AP. This can be generated, e.g., with nfc_pw_token from wpa_supplicant. When
+# these parameters are used, the AP is assumed to be deployed with a NFC tag
+# that includes the matching NFC password token (e.g., written based on the
+# NDEF record from nfc_pw_token).
+#
+#wps_nfc_dev_pw_id: Device Password ID (16..65535)
+#wps_nfc_dh_pubkey: Hexdump of DH Public Key
+#wps_nfc_dh_privkey: Hexdump of DH Private Key
+#wps_nfc_dev_pw: Hexdump of Device Password
+
+##### Wi-Fi Direct (P2P) ######################################################
+
+# Enable P2P Device management
+#manage_p2p=1
+
+# Allow cross connection
+#allow_cross_connection=1
+
+#### TDLS (IEEE 802.11z-2010) #################################################
+
+# Prohibit use of TDLS in this BSS
+#tdls_prohibit=1
+
+# Prohibit use of TDLS Channel Switching in this BSS
+#tdls_prohibit_chan_switch=1
+
+##### IEEE 802.11v-2011 #######################################################
+
+# Time advertisement
+# 0 = disabled (default)
+# 2 = UTC time at which the TSF timer is 0
+#time_advertisement=2
+
+# Local time zone as specified in 8.3 of IEEE Std 1003.1-2004:
+# stdoffset[dst[offset][,start[/time],end[/time]]]
+#time_zone=EST5
+
+# WNM-Sleep Mode (extended sleep mode for stations)
+# 0 = disabled (default)
+# 1 = enabled (allow stations to use WNM-Sleep Mode)
+#wnm_sleep_mode=1
+
+# BSS Transition Management
+# 0 = disabled (default)
+# 1 = enabled
+#bss_transition=1
+
+##### IEEE 802.11u-2011 #######################################################
+
+# Enable Interworking service
+#interworking=1
+
+# Access Network Type
+# 0 = Private network
+# 1 = Private network with guest access
+# 2 = Chargeable public network
+# 3 = Free public network
+# 4 = Personal device network
+# 5 = Emergency services only network
+# 14 = Test or experimental
+# 15 = Wildcard
+#access_network_type=0
+
+# Whether the network provides connectivity to the Internet
+# 0 = Unspecified
+# 1 = Network provides connectivity to the Internet
+#internet=1
+
+# Additional Step Required for Access
+# Note: This is only used with open network, i.e., ASRA shall ne set to 0 if
+# RSN is used.
+#asra=0
+
+# Emergency services reachable
+#esr=0
+
+# Unauthenticated emergency service accessible
+#uesa=0
+
+# Venue Info (optional)
+# The available values are defined in IEEE Std 802.11u-2011, 7.3.1.34.
+# Example values (group,type):
+# 0,0 = Unspecified
+# 1,7 = Convention Center
+# 1,13 = Coffee Shop
+# 2,0 = Unspecified Business
+# 7,1  Private Residence
+#venue_group=7
+#venue_type=1
+
+# Homogeneous ESS identifier (optional; dot11HESSID)
+# If set, this shall be identifical to one of the BSSIDs in the homogeneous
+# ESS and this shall be set to the same value across all BSSs in homogeneous
+# ESS.
+#hessid=02:03:04:05:06:07
+
+# Roaming Consortium List
+# Arbitrary number of Roaming Consortium OIs can be configured with each line
+# adding a new OI to the list. The first three entries are available through
+# Beacon and Probe Response frames. Any additional entry will be available only
+# through ANQP queries. Each OI is between 3 and 15 octets and is configured as
+# a hexstring.
+#roaming_consortium=021122
+#roaming_consortium=2233445566
+
+# Venue Name information
+# This parameter can be used to configure one or more Venue Name Duples for
+# Venue Name ANQP information. Each entry has a two or three character language
+# code (ISO-639) separated by colon from the venue name string.
+# Note that venue_group and venue_type have to be set for Venue Name
+# information to be complete.
+#venue_name=eng:Example venue
+#venue_name=fin:Esimerkkipaikka
+# Alternative format for language:value strings:
+# (double quoted string, printf-escaped string)
+#venue_name=P"eng:Example\nvenue"
+
+# Network Authentication Type
+# This parameter indicates what type of network authentication is used in the
+# network.
+# format: <network auth type indicator (1-octet hex str)> [redirect URL]
+# Network Authentication Type Indicator values:
+# 00 = Acceptance of terms and conditions
+# 01 = On-line enrollment supported
+# 02 = http/https redirection
+# 03 = DNS redirection
+#network_auth_type=00
+#network_auth_type=02http://www.example.com/redirect/me/here/
+
+# IP Address Type Availability
+# format: <1-octet encoded value as hex str>
+# (ipv4_type & 0x3f) << 2 | (ipv6_type & 0x3)
+# ipv4_type:
+# 0 = Address type not available
+# 1 = Public IPv4 address available
+# 2 = Port-restricted IPv4 address available
+# 3 = Single NATed private IPv4 address available
+# 4 = Double NATed private IPv4 address available
+# 5 = Port-restricted IPv4 address and single NATed IPv4 address available
+# 6 = Port-restricted IPv4 address and double NATed IPv4 address available
+# 7 = Availability of the address type is not known
+# ipv6_type:
+# 0 = Address type not available
+# 1 = Address type available
+# 2 = Availability of the address type not known
+#ipaddr_type_availability=14
+
+# Domain Name
+# format: <variable-octet str>[,<variable-octet str>]
+#domain_name=example.com,another.example.com,yet-another.example.com
+
+# 3GPP Cellular Network information
+# format: <MCC1,MNC1>[;<MCC2,MNC2>][;...]
+#anqp_3gpp_cell_net=244,91;310,026;234,56
+
+# NAI Realm information
+# One or more realm can be advertised. Each nai_realm line adds a new realm to
+# the set. These parameters provide information for stations using Interworking
+# network selection to allow automatic connection to a network based on
+# credentials.
+# format: <encoding>,<NAI Realm(s)>[,<EAP Method 1>][,<EAP Method 2>][,...]
+# encoding:
+#	0 = Realm formatted in accordance with IETF RFC 4282
+#	1 = UTF-8 formatted character string that is not formatted in
+#	    accordance with IETF RFC 4282
+# NAI Realm(s): Semi-colon delimited NAI Realm(s)
+# EAP Method: <EAP Method>[:<[AuthParam1:Val1]>][<[AuthParam2:Val2]>][...]
+# AuthParam (Table 8-188 in IEEE Std 802.11-2012):
+# ID 2 = Non-EAP Inner Authentication Type
+#	1 = PAP, 2 = CHAP, 3 = MSCHAP, 4 = MSCHAPV2
+# ID 3 = Inner authentication EAP Method Type
+# ID 5 = Credential Type
+#	1 = SIM, 2 = USIM, 3 = NFC Secure Element, 4 = Hardware Token,
+#	5 = Softoken, 6 = Certificate, 7 = username/password, 9 = Anonymous,
+#	10 = Vendor Specific
+#nai_realm=0,example.com;example.net
+# EAP methods EAP-TLS with certificate and EAP-TTLS/MSCHAPv2 with
+# username/password
+#nai_realm=0,example.org,13[5:6],21[2:4][5:7]
+
+# QoS Map Set configuration
+#
+# Comma delimited QoS Map Set in decimal values
+# (see IEEE Std 802.11-2012, 8.4.2.97)
+#
+# format:
+# [<DSCP Exceptions[DSCP,UP]>,]<UP 0 range[low,high]>,...<UP 7 range[low,high]>
+#
+# There can be up to 21 optional DSCP Exceptions which are pairs of DSCP Value
+# (0..63 or 255) and User Priority (0..7). This is followed by eight DSCP Range
+# descriptions with DSCP Low Value and DSCP High Value pairs (0..63 or 255) for
+# each UP starting from 0. If both low and high value are set to 255, the
+# corresponding UP is not used.
+#
+# default: not set
+#qos_map_set=53,2,22,6,8,15,0,7,255,255,16,31,32,39,255,255,40,47,255,255
+
+##### Hotspot 2.0 #############################################################
+
+# Enable Hotspot 2.0 support
+#hs20=1
+
+# Disable Downstream Group-Addressed Forwarding (DGAF)
+# This can be used to configure a network where no group-addressed frames are
+# allowed. The AP will not forward any group-address frames to the stations and
+# random GTKs are issued for each station to prevent associated stations from
+# forging such frames to other stations in the BSS.
+#disable_dgaf=1
+
+# Operator Friendly Name
+# This parameter can be used to configure one or more Operator Friendly Name
+# Duples. Each entry has a two or three character language code (ISO-639)
+# separated by colon from the operator friendly name string.
+#hs20_oper_friendly_name=eng:Example operator
+#hs20_oper_friendly_name=fin:Esimerkkioperaattori
+
+# Connection Capability
+# This can be used to advertise what type of IP traffic can be sent through the
+# hotspot (e.g., due to firewall allowing/blocking protocols/ports).
+# format: <IP Protocol>:<Port Number>:<Status>
+# IP Protocol: 1 = ICMP, 6 = TCP, 17 = UDP
+# Port Number: 0..65535
+# Status: 0 = Closed, 1 = Open, 2 = Unknown
+# Each hs20_conn_capab line is added to the list of advertised tuples.
+#hs20_conn_capab=1:0:2
+#hs20_conn_capab=6:22:1
+#hs20_conn_capab=17:5060:0
+
+# WAN Metrics
+# format: <WAN Info>:<DL Speed>:<UL Speed>:<DL Load>:<UL Load>:<LMD>
+# WAN Info: B0-B1: Link Status, B2: Symmetric Link, B3: At Capabity
+#    (encoded as two hex digits)
+#    Link Status: 1 = Link up, 2 = Link down, 3 = Link in test state
+# Downlink Speed: Estimate of WAN backhaul link current downlink speed in kbps;
+#	1..4294967295; 0 = unknown
+# Uplink Speed: Estimate of WAN backhaul link current uplink speed in kbps
+#	1..4294967295; 0 = unknown
+# Downlink Load: Current load of downlink WAN connection (scaled to 255 = 100%)
+# Uplink Load: Current load of uplink WAN connection (scaled to 255 = 100%)
+# Load Measurement Duration: Duration for measuring downlink/uplink load in
+# tenths of a second (1..65535); 0 if load cannot be determined
+#hs20_wan_metrics=01:8000:1000:80:240:3000
+
+# Operating Class Indication
+# List of operating classes the BSSes in this ESS use. The Global operating
+# classes in Table E-4 of IEEE Std 802.11-2012 Annex E define the values that
+# can be used in this.
+# format: hexdump of operating class octets
+# for example, operating classes 81 (2.4 GHz channels 1-13) and 115 (5 GHz
+# channels 36-48):
+#hs20_operating_class=5173
+
+##### TESTING OPTIONS #########################################################
+#
+# The options in this section are only available when the build configuration
+# option CONFIG_TESTING_OPTIONS is set while compiling hostapd. They allow
+# testing some scenarios that are otherwise difficult to reproduce.
+#
+# Ignore probe requests sent to hostapd with the given probability, must be a
+# floating point number in the range [0, 1).
+#ignore_probe_probability=0.0
+#
+# Ignore authentication frames with the given probability
+#ignore_auth_probability=0.0
+#
+# Ignore association requests with the given probability
+#ignore_assoc_probability=0.0
+#
+# Ignore reassociation requests with the given probability
+#ignore_reassoc_probability=0.0
+#
+# Corrupt Key MIC in GTK rekey EAPOL-Key frames with the given probability
+#corrupt_gtk_rekey_mic_probability=0.0
+
+##### Multiple BSSID support ##################################################
+#
+# Above configuration is using the default interface (wlan#, or multi-SSID VLAN
+# interfaces). Other BSSIDs can be added by using separator 'bss' with
+# default interface name to be allocated for the data packets of the new BSS.
+#
+# hostapd will generate BSSID mask based on the BSSIDs that are
+# configured. hostapd will verify that dev_addr & MASK == dev_addr. If this is
+# not the case, the MAC address of the radio must be changed before starting
+# hostapd (ifconfig wlan0 hw ether <MAC addr>). If a BSSID is configured for
+# every secondary BSS, this limitation is not applied at hostapd and other
+# masks may be used if the driver supports them (e.g., swap the locally
+# administered bit)
+#
+# BSSIDs are assigned in order to each BSS, unless an explicit BSSID is
+# specified using the 'bssid' parameter.
+# If an explicit BSSID is specified, it must be chosen such that it:
+# - results in a valid MASK that covers it and the dev_addr
+# - is not the same as the MAC address of the radio
+# - is not the same as any other explicitly specified BSSID
+#
+# Please note that hostapd uses some of the values configured for the first BSS
+# as the defaults for the following BSSes. However, it is recommended that all
+# BSSes include explicit configuration of all relevant configuration items.
+#
+#bss=wlan0_0
+#ssid=test2
+# most of the above items can be used here (apart from radio interface specific
+# items, like channel)
+
+#bss=wlan0_1
+#bssid=00:13:10:95:fe:0b
+# ...
diff --git a/drivers/net/wireless/ssv6x5x/script/kmsg.sh b/drivers/net/wireless/ssv6x5x/script/kmsg.sh
new file mode 100755
index 000000000..b8e2fc7f8
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/kmsg.sh
@@ -0,0 +1,2 @@
+#/bin/bash
+tail -f /var/log/kern.log
diff --git a/drivers/net/wireless/ssv6x5x/script/license.txt b/drivers/net/wireless/ssv6x5x/script/license.txt
new file mode 100755
index 000000000..286c64aba
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/license.txt
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
diff --git a/drivers/net/wireless/ssv6x5x/script/load_ap_sta.sh b/drivers/net/wireless/ssv6x5x/script/load_ap_sta.sh
new file mode 100755
index 000000000..82b1cdb2c
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/load_ap_sta.sh
@@ -0,0 +1,106 @@
+#!/bin/bash
+
+echo "=================================================="
+echo "1.Copy firmware"
+echo "=================================================="
+cp ../image/ssv6200-sw.bin /lib/firmware/
+
+echo "=================================================="
+echo "1.Unload Module"
+echo "=================================================="
+./unload_ap.sh
+./unload.sh
+./clean_log.sh
+
+echo "=================================================="
+echo "2.Set Hardware Capability"
+echo "=================================================="
+ifconfig eth0 down
+ifconfig eth0 > /dev/null
+if [ $? ]; then
+    eth0_local_mac=`ifconfig eth0  | grep HWaddr | sed -e 's/.*HWaddr //g' | sed -e 's/ //g' | cut -d ':' -f 4,5,6`
+    echo Use eth0 MAC address. 
+else
+    eth0_local_mac="45:67:89"
+    echo No eth0 found use defaul MAC address.
+fi
+
+ap_prefix=`echo $eth0_local_mac | cut -d ':' -f 1,2`
+ap_prefix=`echo $ap_prefix | sed -e 's/://g'`
+
+local_mac=00:a8:b8:$eth0_local_mac
+local_mac_2=`echo $local_mac | cut -d ':' -f 6`
+local_mac_2=`printf '%x' $[ ( 16#$local_mac_2 + 1 ) % 4 + ( 16#$local_mac_2 & 16#FC ) ] `
+ap_prefix="AP_$ap_prefix$local_mac_2"
+local_mac_2="`echo $local_mac | cut -d ':' -f 1,2,3,4,5`:$local_mac_2"
+
+echo Primary WLAN MAC is $local_mac
+echo Secondary WLAN MAC is $local_mac_2
+    
+cat sta.cfg.template | sed -e "s/MAC_ADDR/$local_mac/g" | sed -e "s/MAC2ADDR/$local_mac_2/g" > sta_local_mac.cfg
+./ssvcfg.sh sta_local_mac.cfg
+
+echo "=================================================="
+echo "3.Load MMC Module"
+echo "=================================================="
+modprobe mmc_core
+modprobe sdhci
+modprobe sdhci-pci
+modprobe mmc_block
+
+echo "=================================================="
+echo "4.Load SSV6200 Driver"
+echo "=================================================="
+echo 6 > /proc/sys/kernel/printk
+
+modprobe ssv6200_sdio
+modprobe ssv6200_usb
+
+sleep 1
+
+ssv_phy=`./find_ssv_phy`
+if [ -z "$ssv_phy" ]; then
+    echo SSV PHY device not found.;
+    exit 1;
+fi
+
+ssv_wlan_1=`./find_ssv_wlan`
+if [ -z "$ssv_wlan_1" ]; then
+    echo SSV primary WLAN device not found.;
+    exit 1;
+fi
+
+echo "Primary SSV WLAN interface is $ssv_wlan_1"
+
+ssv_wlan_2=`echo $ssv_wlan_1 | sed -e s/wlan//g`
+ssv_wlan_2=`expr $ssv_wlan_2 + 1`
+ssv_wlan_2="wlan$ssv_wlan_2"
+echo Second WLAN interface is $ssv_wlan_2
+
+echo "Add second interface $ssv_wlan_2 to SSV PHY device $ssv_phy"
+iw $ssv_phy interface add $ssv_wlan_2 type station
+
+sleep 1
+
+trap handle_stop INT
+
+function handle_stop() {
+    nmcli nm wifi on
+
+    ./unload_ap.sh
+    ./unload.sh
+    
+    ifconfig eth0 up
+    
+    echo AP mode stopped
+}
+        
+ssv_wlans="`./find_ssv_wlan`"
+for ssv_wlan in $ssv_wlans; do
+    if [ $ssv_wlan != $ssv_wlan_1 ]; then
+        echo Second SSV WLAN device is actually $ssv_wlan
+        ./ap_sta.sh $ssv_wlan $ssv_wlan_1 $ap_prefix
+        break;
+    fi
+done
+
diff --git a/drivers/net/wireless/ssv6x5x/script/load_unload.sh b/drivers/net/wireless/ssv6x5x/script/load_unload.sh
new file mode 100755
index 000000000..4f97e3d43
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/load_unload.sh
@@ -0,0 +1,12 @@
+#/bin/bash
+#load/unload driver
+
+count=0
+S=1
+while [ "$S" == "1" ]
+do
+    ./unload.sh
+    ./load.sh
+    sleep 10
+done
+
diff --git a/drivers/net/wireless/ssv6x5x/script/p2p-action.sh b/drivers/net/wireless/ssv6x5x/script/p2p-action.sh
new file mode 100755
index 000000000..b4e6b1161
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/p2p-action.sh
@@ -0,0 +1,115 @@
+#!/bin/sh
+
+IFNAME=$1
+CMD=$2
+
+kill_daemon() {
+    NAME=$1
+    PF=$2
+
+    if [ ! -r $PF ]; then
+	return
+    fi
+
+    PID=`cat $PF`
+    if [ $PID -gt 0 ]; then
+	if ps $PID | grep -q $NAME; then
+	    kill $PID
+	fi
+    fi
+    rm $PF
+}
+
+
+echo "$1 $2 $3 $4"
+if [ "$CMD" = "P2P-GROUP-STARTED" ]; then
+    GIFNAME=$3
+    echo "P2P-GROUP-STARTED $3 $4"
+    if [ "$4" = "GO" ]; then
+	kill_daemon dhclient /var/run/dhclient-$GIFNAME.pid
+	rm /var/run/dhclient.leases-$GIFNAME
+	kill_daemon dnsmasq /var/run/dnsmasq.pid-$GIFNAME
+	ifconfig $GIFNAME 192.168.42.1 up
+	if ! dnsmasq -x /var/run/dnsmasq.pid-$GIFNAME \
+	    -i $GIFNAME \
+	    -F192.168.42.11,192.168.42.99; then
+	    # another dnsmasq instance may be running and blocking us; try to
+	    # start with -z to avoid that
+	    dnsmasq -x /var/run/dnsmasq.pid-$GIFNAME \
+		-i $GIFNAME \
+		-F192.168.42.11,192.168.42.99 --listen-address 192.168.42.1 -z -p 0
+	fi
+    fi
+    if [ "$4" = "client" ]; then
+	kill_daemon dhclient /var/run/dhclient-$GIFNAME.pid
+	rm /var/run/dhclient.leases-$GIFNAME
+	kill_daemon dnsmasq /var/run/dnsmasq.pid-$GIFNAME
+	ipaddr=`echo "$*" | sed 's/.* ip_addr=\([^ ]*\).*/\1/'`
+	ipmask=`echo "$*" | sed 's/.* ip_mask=\([^ ]*\).*/\1/'`
+	goipaddr=`echo "$*" | sed 's/.* go_ip_addr=\([^ ]*\).*/\1/'`
+	if echo "$ipaddr$ipmask$goipaddr" | grep -q ' '; then
+	    ipaddr=""
+	    ipmask=""
+	    goipaddr=""
+	fi
+	if [ -n "$ipaddr" ]; then
+	    sudo ifconfig $GIFNAME "$ipaddr" netmask "$ipmask"
+	    sudo ip ro re default via "$goipaddr"
+	    exit 0
+	fi
+	dhclient -pf /var/run/dhclient-$GIFNAME.pid \
+	    -lf /var/run/dhclient.leases-$GIFNAME \
+	    -nw \
+	    $GIFNAME
+    fi
+fi
+#if [ "$CMD" = "CONNECTED" ]; then
+
+#   echo connect $IFNAME, dhclient for it > /dev/console
+
+#   dhclient $IFNAME
+
+#fi
+
+#if [ "$CMD" = "DISCONNECTED" ]; then
+
+#   echo disconnect $IFNAME, kill dhclient for it > /dev/console
+
+#   killall dhclient
+
+#fi
+
+if [ "$CMD" = "P2P-GROUP-REMOVED" ]; then
+    GIFNAME=$3
+    if [ "$4" = "GO" ]; then
+	kill_daemon dnsmasq /var/run/dnsmasq.pid-$GIFNAME
+	ifconfig $GIFNAME 0.0.0.0
+    fi
+    if [ "$4" = "client" ]; then
+	kill_daemon dhclient /var/run/dhclient-$GIFNAME.pid
+	rm /var/run/dhclient.leases-$GIFNAME
+	ifconfig $GIFNAME 0.0.0.0
+    fi
+fi
+
+if [ "$CMD" = "P2P-CROSS-CONNECT-ENABLE" ]; then
+    GIFNAME=$3
+    UPLINK=$4
+    echo "p2p-corss-connect-enable ifname=$GIFNAME upLink=$UPLINK"
+    # enable NAT/masquarade $GIFNAME -> $UPLINK
+    iptables -P FORWARD DROP
+    iptables -t nat -A POSTROUTING -o $UPLINK -j MASQUERADE
+    iptables -A FORWARD -i $UPLINK -o $GIFNAME -m state --state RELATED,ESTABLISHED -j ACCEPT
+    iptables -A FORWARD -i $GIFNAME -o $UPLINK -j ACCEPT
+    sysctl net.ipv4.ip_forward=1
+fi
+
+if [ "$CMD" = "P2P-CROSS-CONNECT-DISABLE" ]; then
+    GIFNAME=$3
+    UPLINK=$4
+    # disable NAT/masquarade $GIFNAME -> $UPLINK
+    sysctl net.ipv4.ip_forward=0
+    iptables -t nat -D POSTROUTING -o $UPLINK -j MASQUERADE
+    iptables -D FORWARD -i $UPLINK -o $GIFNAME -m state --state RELATED,ESTABLISHED -j ACCEPT
+    iptables -D FORWARD -i $GIFNAME -o $UPLINK -j ACCEPT
+fi
diff --git a/drivers/net/wireless/ssv6x5x/script/p2p.conf.template b/drivers/net/wireless/ssv6x5x/script/p2p.conf.template
new file mode 100755
index 000000000..e81e1c085
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/p2p.conf.template
@@ -0,0 +1,21 @@
+ctrl_interface=/var/run/wpa_supplicant
+update_config=0
+uuid=12345678-9abc-def0-1234-56789abcde22
+max_num_sta=1
+device_name=X86-Platform-P2P
+manufacturer=iComm Corporation
+model_name=Wi-Fi reference chip
+model_number=123
+serial_number=MAC_ADDR
+device_type=1-0050F204-1
+os_version=01020300
+config_methods=display push_button virtual_display virtual_push_button
+p2p_listen_reg_class=81
+p2p_listen_channel=11
+p2p_oper_reg_class=81
+p2p_oper_channel=11
+p2p_go_intent=7
+p2p_no_group_iface=1
+p2p_intra_bss=1
+persistent_reconnect=1
+
diff --git a/drivers/net/wireless/ssv6x5x/script/p2p_dual.sh b/drivers/net/wireless/ssv6x5x/script/p2p_dual.sh
new file mode 100755
index 000000000..956bb7df9
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/p2p_dual.sh
@@ -0,0 +1,103 @@
+#!/bin/bash
+
+echo "=================================================="
+echo "1.Copy firmware"
+echo "=================================================="
+cp ../image/* /lib/firmware/
+
+echo "=================================================="
+echo "1.Unload Module"
+echo "=================================================="
+./unload_ap.sh
+./unload.sh
+./clean_log.sh
+
+nmcli nm wifi off
+sudo rfkill unblock wlan
+
+echo "=================================================="
+echo "2.Set Hardware Capability"
+echo "=================================================="
+#ifconfig eth0 down
+#ifconfig eth0 > /dev/null
+if [ $? ]; then
+    eth0_local_mac=`ifconfig eth0  | grep HWaddr | sed -e 's/.*HWaddr //g' | sed -e 's/ //g' | cut -d ':' -f 4,5,6`
+    echo Use eth0 MAC address. 
+else
+    eth0_local_mac="45:67:89"
+    echo No eth0 found use defaul MAC address.
+fi
+
+local_mac=00:a8:b8:$eth0_local_mac
+local_mac_2=`echo $local_mac | cut -d ':' -f 6`
+local_mac_2=`printf '%x' $[ ( 16#$local_mac_2 + 1 ) % 4 + ( 16#$local_mac_2 & 16#FC ) ] `
+local_mac_2="`echo $local_mac | cut -d ':' -f 1,2,3,4,5`:$local_mac_2"
+
+echo Primary WLAN MAC is $local_mac
+echo Secondary WLAN MAC is $local_mac_2
+    
+cat sta.cfg.template | sed -e "s/MAC_ADDR/$local_mac/g" | sed -e "s/MAC2ADDR/$local_mac_2/g" > sta.cfg
+./ssvcfg.sh sta.cfg
+echo ----Secondary WLAN MAC is $local_mac_2
+
+echo "=================================================="
+echo "3.Load MMC Module"
+echo "=================================================="
+modprobe mmc_core
+modprobe sdhci
+modprobe sdhci-pci
+modprobe mmc_block
+
+echo "=================================================="
+echo "4.Load SSV6200 Driver"
+echo "=================================================="
+echo 6 > /proc/sys/kernel/printk
+
+modprobe ssv6200_sdio
+modprobe ssv6200_usb
+
+sleep 1
+
+ssv_phy=`./find_ssv_phy`
+if [ -z "$ssv_phy" ]; then
+    echo SSV PHY device not found.;
+    exit 1;
+fi
+
+ssv_wlan_1=`./find_ssv_wlan`
+if [ -z "$ssv_wlan_1" ]; then
+    echo SSV primary WLAN device not found.;
+    exit 1;
+fi
+
+echo "Primary SSV WLAN interface is $ssv_wlan_1"
+
+ssv_wlan_2=`echo $ssv_wlan_1 | sed -e s/wlan//g`
+ssv_wlan_2=`expr $ssv_wlan_2 + 1`
+ssv_wlan_2="wlan$ssv_wlan_2"
+echo Second WLAN interface is $ssv_wlan_2
+
+echo "Add second interface $ssv_wlan_2 to SSV PHY device $ssv_phy"
+iw $ssv_phy interface add $ssv_wlan_2 type  __p2pcl
+sleep 1
+ssv_wlans="`./find_ssv_wlan`"
+for ssv_wlan in $ssv_wlans; do
+    if [ $ssv_wlan != $ssv_wlan_1 ]; then
+            echo Second SSV WLAN device is actually $ssv_wlan
+#            ifconfig $ssv_wlan up
+            ssv_wlan_2=$ssv_wlan
+                            break;
+    fi
+done 
+#ifconfig $ssv_wlan_1 up
+
+cat wpa.conf.template | sed -e "s/MAC_ADDR/$local_mac/g"  > wpa.cfg
+cat p2p.conf.template | sed -e "s/MAC_ADDR/$local_mac_2/g" > p2p.cfg
+
+killall wpa_supplicant
+rm -rf log
+sleep 3
+
+wpa_supplicant -i $ssv_wlan_2 -c p2p.cfg -D nl80211 -N -i $ssv_wlan_1 -c wpa.cfg -D nl80211
+
+
diff --git a/drivers/net/wireless/ssv6x5x/script/p2p_single.sh b/drivers/net/wireless/ssv6x5x/script/p2p_single.sh
new file mode 100755
index 000000000..ee7cd3190
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/p2p_single.sh
@@ -0,0 +1,88 @@
+#!/bin/bash
+
+echo "=================================================="
+echo "1.Copy firmware"
+echo "=================================================="
+cp ../image/* /lib/firmware/
+
+echo "=================================================="
+echo "1.Unload Module"
+echo "=================================================="
+./unload_ap.sh
+./unload.sh
+./clean_log.sh
+
+nmcli nm wifi off
+sudo rfkill unblock wlan
+
+echo "=================================================="
+echo "2.Set Hardware Capability"
+echo "=================================================="
+#ifconfig eth0 down
+#ifconfig eth0 > /dev/null
+if [ $? ]; then
+    eth0_local_mac=`ifconfig eth0  | grep HWaddr | sed -e 's/.*HWaddr //g' | sed -e 's/ //g' | cut -d ':' -f 4,5,6`
+    echo Use eth0 MAC address. 
+else
+    eth0_local_mac="45:67:89"
+    echo No eth0 found use defaul MAC address.
+fi
+
+#local_mac=00:a8:b8:01:79:55
+local_mac=00:a8:b8:$eth0_local_mac
+local_mac_2=`echo $local_mac | cut -d ':' -f 6`
+local_mac_2=`printf '%x' $[ ( 16#$local_mac_2 + 1 ) % 4 + ( 16#$local_mac_2 & 16#FC ) ] `
+local_mac_2="`echo $local_mac | cut -d ':' -f 1,2,3,4,5`:$local_mac_2"
+
+echo Primary WLAN MAC is $local_mac
+    
+cat sta.cfg.template | sed -e "s/MAC_ADDR/$local_mac/g" | sed -e "s/MAC2ADDR/$local_mac_2/g" > sta.cfg
+./ssvcfg.sh sta.cfg
+
+echo "=================================================="
+echo "3.Load MMC Module"
+echo "=================================================="
+modprobe mmc_core
+modprobe sdhci
+modprobe sdhci-pci
+modprobe mmc_block
+
+echo "=================================================="
+echo "4.Load SSV6200 Driver"
+echo "=================================================="
+echo 6 > /proc/sys/kernel/printk
+
+modprobe ssv6200_sdio
+modprobe ssv6200_usb
+
+sleep 1
+
+ssv_phy=`./find_ssv_phy`
+if [ -z "$ssv_phy" ]; then
+    echo SSV PHY device not found.;
+    exit 1;
+fi
+
+ssv_wlan_1=`./find_ssv_wlan`
+if [ -z "$ssv_wlan_1" ]; then
+    echo SSV primary WLAN device not found.;
+    exit 1;
+fi
+
+echo "Primary SSV WLAN interface is $ssv_wlan_1"
+
+cat p2p.conf.template | sed -e "s/MAC_ADDR/$local_mac/g" > p2p.cfg
+
+killall wpa_supplicant
+
+pi=$(pidof dnsmasq)
+if [ $pi ]; then
+	echo "kill dnsmasq pid=$pi"
+	kill -9 $pi  
+fi
+
+rm -rf log
+sleep 3
+wpa_supplicant -i $ssv_wlan_1 -c p2p.cfg -D nl80211
+ 
+
diff --git a/drivers/net/wireless/ssv6x5x/script/pack b/drivers/net/wireless/ssv6x5x/script/pack
new file mode 100755
index 000000000..58ef0ea10
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/pack
@@ -0,0 +1,45 @@
+#!/bin/bash
+
+TARGET_DIR=pack
+
+rm -rf $TARGET_DIR
+
+src_c=`find . -name "*.c"`
+src_h=`find . -name "*.h"`
+src_mk=`find . \( -name Makefile -o -name "*.mak" \)`
+
+mkdir -p /tmp/pack > /dev/null
+
+# Process each source code in .c and .h.
+for src in $src_c $src_h; do
+        mkdir -p "/tmp/pack/`dirname $src`" > /dev/null
+	echo "Processing $src..."        
+	dir="$TARGET_DIR/`dirname $src`"
+	src_name="`basename $src`"
+	if [ ! -d $dir ]; then
+		mkdir -p $dir
+	fi
+	# Remove comment using preprocessor.
+	# And use indent to make the result comfort to Linux coding style
+	cat script/license.txt > "$dir/$src_name"
+	gcc -fpreprocessed -dD -E -P -std=gnu99 $src > /tmp/pack/$src
+	#cat /tmp/pack/$src | \
+	#indent -bad -bap -bbb -nbc -bbo -hnl -br -brs -c33 -cd33 -ncdb -ce -ci4 \
+	#-cli0 -d0 -di1 -nfc1 -i8 -ip0 -l80 -lp -npcs -nprs -npsl -sai \
+	#-saf -saw -ncs -nsc -sob -nfca -cp33 -ss -ts8 -il1 /tmp/pack/$src -o "$dir/$src_name"
+	clang-format-3.4 -style='{BasedOnStyle: LLVM, UseTab: Always, IndentWidth: 8, BreakBeforeBraces: Linux, AllowShortIfStatementsOnASingleLine: false, IndentCaseLabels: false}' \
+	    /tmp/pack/$src > "$dir/$src_name"
+	#$src | script/stripcmt > "$dir/$src_name"
+done
+
+# Copy every Makefile
+for src in $src_mk; do
+	cp $src "$TARGET_DIR/$src"
+done
+
+# No firmware code
+rm -rf "$TARGET_DIR/smac/firmware"
+rm -rf "$TARGET_DIR/ssv6200fmac"
+
+# Copy scripts and FW image
+cp -r image script *.sh $TARGET_DIR
diff --git a/drivers/net/wireless/ssv6x5x/script/pre-regular-test.sh b/drivers/net/wireless/ssv6x5x/script/pre-regular-test.sh
new file mode 100755
index 000000000..2a2c22f3d
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/pre-regular-test.sh
@@ -0,0 +1,17 @@
+#!/bin/bash
+
+echo "=================================================="
+echo "For regular test, create files for Disable AMPDU"
+echo "Output files on driver root directory:"
+echo " load1.sh"
+echo " ssvcfg1.sh"
+echo " sta1.sh"
+echo "=================================================="
+cp ../load.sh ../load1.sh
+cp ../ssvcfg.sh ../ssvcfg1.sh
+cp ../sta.cfg ../sta1.cfg
+
+find ../load1.sh | xargs -i sed -i 's/ssvcfg.sh/ssvcfg1.sh/g' {}
+find ../ssvcfg1.sh | xargs -i sed -i 's/sta.cfg/sta1.cfg/g' {}
+find ../sta1.cfg | xargs -i sed -i 's/hw_cap_ampdu_rx = on/hw_cap_ampdu_rx = off/g' {}
+find ../sta1.cfg | xargs -i sed -i 's/hw_cap_ampdu_tx = on/hw_cap_ampdu_tx = off/g' {}
\ No newline at end of file
diff --git a/drivers/net/wireless/ssv6x5x/script/rc_stat.sh b/drivers/net/wireless/ssv6x5x/script/rc_stat.sh
new file mode 100755
index 000000000..9e6a6e0e0
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/rc_stat.sh
@@ -0,0 +1,45 @@
+#!/bin/sh
+
+phy_dirs="/sys/class/ieee80211/*"
+net_dirs="/sys/class/net/*"
+SSV_IF="SSV|RSV"
+
+ssv_phy=""
+ssv_wlan=""
+
+## find ssv phy 
+for phy_dir in $phy_dirs; do
+	drv_name=`ls ${phy_dir}/device/driver | grep -E ${SSV_IF}`
+    if [ ${drv_name} ]; then
+    	ssv_phy=`basename $phy_dir`;
+    	break;
+    fi
+done
+
+if [ -z "$ssv_phy" ]; then
+    echo SSV PHY device not found.;
+    exit 1;
+fi
+
+## find ssv wlan 
+for net_dir in $net_dirs; do
+	drv_dir="${net_dir}/phy80211/device/driver"
+	if [ ! -e ${drv_dir} ] ; then
+		continue;
+	fi
+	drv_name=`ls ${drv_dir} | grep -E ${SSV_IF}`
+    if [ ${drv_name} ]; then
+    	ssv_wlan=`basename ${net_dir}`;
+    	break;
+    fi
+done
+
+if [ -z "$ssv_wlan" ]; then
+    echo SSV wlan device not found.;
+    exit 1;
+fi
+
+rc_stat=/sys/kernel/debug/ieee80211/${ssv_phy}/netdev:${ssv_wlan}/stations/*/rc_stats
+if [ -f ${rc_stat} ] ; then
+    cat ${rc_stat}
+fi
diff --git a/drivers/net/wireless/ssv6x5x/script/redoall b/drivers/net/wireless/ssv6x5x/script/redoall
new file mode 100755
index 000000000..a7ae1a6a2
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/redoall
@@ -0,0 +1,4 @@
+#!/bin/bash
+
+./redofw
+./redodrv
diff --git a/drivers/net/wireless/ssv6x5x/script/redodrv b/drivers/net/wireless/ssv6x5x/script/redodrv
new file mode 100755
index 000000000..30176680b
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/redodrv
@@ -0,0 +1,12 @@
+#!/bin/bash
+
+if [ "`whoami`" != "root" ]; then
+    echo Need to be root to execute.;
+    exit 1;
+fi
+
+
+./unload.sh
+./scratch
+./clean_log.sh
+# ./sta.sh
diff --git a/drivers/net/wireless/ssv6x5x/script/redofw b/drivers/net/wireless/ssv6x5x/script/redofw
new file mode 100755
index 000000000..fc83b08a4
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/redofw
@@ -0,0 +1,4 @@
+#!/bin/sh
+
+cd ../smac/firmware
+./firmware-build.sh
diff --git a/drivers/net/wireless/ssv6x5x/script/release b/drivers/net/wireless/ssv6x5x/script/release
new file mode 100755
index 000000000..552d00b36
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/release
@@ -0,0 +1,58 @@
+#!/bin/bash
+
+#TARGET_DIR=pack
+#rm -rf $TARGET_DIR
+TARGET_DIR=.
+
+src_c=`find . -name "*.c"`
+src_h=`find . -name "*.h"`
+src_mk=`find . \( -name Makefile -o -name "*.mak" \)`
+
+mkdir -p $TARGET_DIR/tmp/pack > /dev/null
+
+# Process each source code in .c and .h.
+for src in $src_c $src_h; do
+        mkdir -p "$TARGET_DIR/tmp/pack/`dirname $src`" > /dev/null
+	echo "Processing $src..."        
+	dir="$TARGET_DIR/`dirname $src`"
+	src_name="`basename $src`"
+	if [ ! -d $dir ]; then
+		mkdir -p $dir
+	fi
+	# Remove comment using preprocessor.
+	# And use indent to make the result comfort to Linux coding style
+	cat script/license.txt > $TARGET_DIR/tmp/pack/$src
+	gcc -fpreprocessed -dD -E -P -std=gnu99 $src >> $TARGET_DIR/tmp/pack/$src
+	#cat $TARGET_DIR/tmp/pack/$src | \
+	#indent -bad -bap -bbb -nbc -bbo -hnl -br -brs -c33 -cd33 -ncdb -ce -ci4 \
+	#-cli0 -d0 -di1 -nfc1 -i8 -ip0 -l80 -lp -npcs -nprs -npsl -sai \
+	#-saf -saw -ncs -nsc -sob -nfca -cp33 -ss -ts8 -il1 $TARGET_DIR/tmp/pack/$src -o "$dir/$src_name"
+	#clang-format-3.4 -style='{BasedOnStyle: LLVM, UseTab: Always, IndentWidth: 8, BreakBeforeBraces: Linux, AllowShortIfStatementsOnASingleLine: false, IndentCaseLabels: false}' $TARGET_DIR/tmp/pack/$src > "$dir/$src_name"
+	cp $TARGET_DIR/tmp/pack/$src "$dir/$src_name"
+	#$src | script/stripcmt > "$dir/$src_name"
+done
+
+# Copy every Makefile
+#for src in $src_mk; do
+#	cp $src "$TARGET_DIR/$src"
+#done
+
+# No firmware code
+rm -rf "$TARGET_DIR/smac/firmware"
+rm -rf "$TARGET_DIR/mac80211"
+rm -rf "$TARGET_DIR/smac/hal/ssv6051"
+rm -rf "$TARGET_DIR/smac/hal/ssv6006"
+rm -rf "$TARGET_DIR/utils"
+rm -rf "$TARGET_DIR/tmp"
+
+rm -rf "$TARGET_DIR/smac/image/cabrio-sw.bin"
+rm -rf "$TARGET_DIR/smac/image/ssv6051-sw.bin"
+
+# Remove unnecessary definition
+sed -i '/support 6006 fpga and 6051/d' $TARGET_DIR/config.mak
+sed -i '/SSV_SUPPORT_SSV6006AB/d' $TARGET_DIR/config.mak
+sed -i '/SSV_SUPPORT_SSV6051/d' $TARGET_DIR/config.mak
+sed -i '/SSV_SUPPORT_TURISMOA/d' $TARGET_DIR/config.mak
+
+# Copy scripts and FW image
+cp -r image script *.sh $TARGET_DIR
diff --git a/drivers/net/wireless/ssv6x5x/script/run_reload.sh b/drivers/net/wireless/ssv6x5x/script/run_reload.sh
new file mode 100755
index 000000000..b146b7f96
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/run_reload.sh
@@ -0,0 +1,49 @@
+#!/bin/bash
+# AP defines the AP the station is going to connect to.
+AP=N66
+# The FW_LOG is the firmware console log file. Used to keep track of firmware status of each run
+FW_LOG=~ssv/Desktop/fw.log
+# WIF is the wireless interface of the loaded driver 
+WIF=wlan5
+# RUN is the number of load/unload tests
+RUN=20000
+
+redo=0
+total=0
+failed=0
+for i in {1..$RUN}; do
+    echo "Unloading" | tee -a /var/log/kern.log
+    ./unload.sh 2&>1 > /dev/null
+    truncate -s 0 ~ssv/Desktop/fw.log
+    echo "#$i run" | tee -a /var/log/kern.log
+    ./sta_usb.sh 2&>1 > /dev/null
+    sleep 1
+    this_total=`cat $FW_LOG | sed -e 's/\r//g' | grep -iac loopback`
+    this_redo=`cat $FW_LOG | sed -e 's/\r//g' | grep -iac redo`
+    redo=$(( $redo + $this_redo ))
+    total=$(( $total + $this_total ))
+    [[ $this_redo -gt 0 ]] && failed=$(( $failed + 1 ))
+    echo "  > $this_redo / $this_total"
+    echo -n "  > Connecting to ${AP}"
+    connected=0
+    waits=0
+    while [[ $connected -eq 0 && waits -lt 60 ]]; do
+        nmcli con status id ${AP} 2&>1 > /dev/null && connected=1
+        [ $connected -eq 0 ] && echo -n "." && sleep 1
+        waits=$(( $waits + 1 ))
+        [[ $(( $waits % 8 )) == 0 ]] && wpa_cli -i $WIF scan
+    done
+    if [[ $connected -eq 1 && $waits -lt 60 ]]; then
+        echo "done ($failed/$redo/$total)" | tee -a /var/log/kern.log
+        sleep 1
+        echo ">> Disconnecting" | tee -a /var/log/kern.log
+        wpa_cli -i $WIF disconnect
+        nmcli con down id ${AP}
+        sleep 1
+        echo ">> IF down" | tee -a /var/log/kern.log
+        ifconfig $WIF down
+    else
+        echo "failed"
+    fi
+    cp ~ssv/Desktop/fw.log fw.log/fw_$i.log
+done
diff --git a/drivers/net/wireless/ssv6x5x/script/scan.cfg b/drivers/net/wireless/ssv6x5x/script/scan.cfg
new file mode 100755
index 000000000..6002b36e1
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/scan.cfg
@@ -0,0 +1,9 @@
+total_times_of_unload/reload = 2200
+target_IP_for_pinging = 192.168.1.1
+timeout_period = 20
+# OPEN, WPA/WPA2
+security = WPA2
+device_name = wlan16
+SSID = QA.ASUS
+PSK_phrase = qqqqqqqq
+scan_times = 10
diff --git a/drivers/net/wireless/ssv6x5x/script/scan_conn.sh b/drivers/net/wireless/ssv6x5x/script/scan_conn.sh
new file mode 100755
index 000000000..cd558e781
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/scan_conn.sh
@@ -0,0 +1,148 @@
+#!/bin/bash
+
+wpa_ret ( )
+{
+	if [ $1 != "OK" ]
+		then
+		if [ $3 == 1 ]
+			then
+			wpa_cli remove_network $2>/dev/null
+			echo "wpa_cli command failed on $2"
+		fi
+		exit 1
+	fi
+}
+
+connect_ap ( )
+{
+	#if [ $1 -eq 1 ]
+		#then
+		ssid=\""$2"\"
+		pw=\""$3"\"
+		declare -i scantimes=1
+		nw_no=$(wpa_cli add_network | sed '1d')
+		ret=$(wpa_cli set_network $nw_no ssid $ssid | sed '1d')
+		echo "Set ssid for nw $nw_no: $ret"
+		wpa_ret $ret $nw_no 1
+		if [ $5 == "WPA" -o $5 == "WPA2" ]
+			then
+			ret=$(wpa_cli set_network $nw_no psk $pw | sed '1d')
+                       	echo "Set PSK: $ret"
+                        wpa_ret $ret $nw_no 1
+		elif [ $5 == "WEP40" -o $5 == "WEP128" -o $5 == "OPEN" ]
+			then
+			ret=$(wpa_cli set_network $nw_no key_mgmt NONE | sed '1d')
+                       	echo "Set Key-mgmt: $ret"
+                        wpa_ret $ret $nw_no 1
+			ret=$(wpa_cli set_network $nw_no auth_alg OPEN | sed '1d')
+                        echo "Set Aith-alg: $ret"
+                        wpa_ret $ret $nw_no 1
+			if [ $5 != "OPEN" ]
+				then
+				ret=$(wpa_cli set_network $nw_no wep_key0 $pw | sed '1d')
+                        	echo "Set wep key: $ret"
+                        	wpa_ret $ret $nw_no 1
+			fi
+		fi 
+		#echo "Set proto"
+		#ret=$(wpa_cli set_network $nw_no proto WPA | sed '1d')
+		#wpa_cli status #echo $ret
+		#wpa_ret $ret $nw_no 1	
+		#echo "Set key_mgmt"
+		#ret=$(wpa_cli set_network $nw_no key_mgmt WPA-PSK | sed '1d')
+		#wpa_cli status #echo $ret
+		#wpa_ret $ret $nw_no 1	
+		#echo "Set pairwise"
+		#ret=$(wpa_cli set_network $nw_no pairwise CCMP | sed '1d')
+		#wpa_cli status #echo $ret
+		#wpa_ret $ret $nw_no 1	
+		#echo "Set group"
+		#ret=$(wpa_cli set_network $nw_no group CCMP | sed '1d')
+		#wpa_cli status #echo $ret
+		#wpa_ret $ret $nw_no 1	
+		ret=$(wpa_cli enable_network $nw_no | sed '1d')
+		echo "Enable nw $nw_no: $ret"
+		wpa_ret $ret $nw_no 1	
+		#echo "Connect"
+		#ret=$(wpa_cli reconnect | sed '1d')
+		#wpa_cli status #echo $ret
+		#wpa_ret $ret $nw_no 1	
+		state=$(wpa_cli status -i $1 | grep wpa_state | sed 's/wpa_state=//g')
+		form_st="INACTIVE"
+		while [ $state != "COMPLETED" ]
+		do
+			if [ $form_st != $state ]
+				then
+				echo "Status: $state"
+			fi
+			if [ $state == "SCANNING" ]
+				then
+				sleep 1
+			elif [ $state == "DISCONNECTED" ]
+				then
+				if [ $scantimes <= $4]
+					then
+					echo "Connect"
+                			ret=$(wpa_cli reconnect | sed '1d')
+					wpa_ret $ret $nw_no 1
+					$scantimes=$scantimes + 1
+				else
+					echo "exceed scan times=$scantimes"
+				fi
+			fi
+			form_st=$state
+			state=$(wpa_cli status -i $1 | grep wpa_state | sed 's/wpa_state=//g')
+		done
+		if [ $state == "COMPLETED" ]
+			then
+			echo "Connected and request for IP address"
+			dhclient -4 $1 >/dev/null
+		fi
+	#fi
+}
+
+if [ $# -eq 5 ]
+	then
+	echo "Scanning"
+	declare -i total_scantime=$4
+        for((i=1; i<=$4; i=i+1))
+	do
+		echo "scan loop:$i" 
+		scan_st=$(wpa_cli scan -i $1)
+		total_scantime=total_scantime-1
+		sleep 2
+		result=$(wpa_cli scan_results -i $1 | grep -c $2)
+		if [ $result -eq 1 ]
+			then
+			echo "Target AP $2 is found."
+			break;
+		fi
+	done
+        if [ $result -eq 1 ]
+		then
+		connect_ap $1 $2 $3 $total_scantime $5
+	else
+		echo "Target ap is not found"
+	fi
+
+
+elif [ $3 == "off" ]
+	then
+	echo "Disconnect AP"
+	dhclient -r $1 >/dev/null
+	dhclient -x >/dev/null 
+	nw_no=$(wpa_cli list_network | grep CURRENT | awk '{print $1}')
+	echo "Disable network"
+	ret=$(wpa_cli disable_network $nw_no | sed '1d')
+	wpa_ret $ret $nw_no 1	
+	echo "Remove network"
+	ret=$(wpa_cli remove_network $nw_no | sed '1d')
+	wpa_ret $ret $nw_no 0	
+else
+	echo "====================================================================================="
+	echo "manual scan & connect script"
+	echo "./scan_conn.sh <interface> <BSSID> <PW> <scan_times>"
+	echo "./scan_conn.sh <interface> <BSSID> off"
+	echo "====================================================================================="
+fi
+
diff --git a/drivers/net/wireless/ssv6x5x/script/scan_test.sh b/drivers/net/wireless/ssv6x5x/script/scan_test.sh
new file mode 100755
index 000000000..7e6706283
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/scan_test.sh
@@ -0,0 +1,125 @@
+#!/bin/bash
+
+read_cfg( )
+{
+	cat $1|grep $2|awk '{print $3}'
+	return 
+	
+}
+
+if [ "$1" == "icqc" ] 
+	then
+	:;
+# for user manual
+elif [ "$1" == "h" ] 
+	then
+
+echo "====================================================================================="
+echo "Unload/Reload & scan Flows"
+#echo "Format = ./scan_test.sh <total.times.of.unload/reload> <target.IP.for.pinging> <timeout period> <dev name> <SSID> <PW> <scan times> <Saved file name>"
+echo "Format = ./scan_test.sh <config file> <Saved file name>"
+echo "System Log of each unload/reload will be saved in folder [UnloadReloadScan]"
+echo "====================================================================================="
+
+
+else
+	# f=failed times;  p=passed times
+	declare -i f=0
+	declare -i p=0
+	declare -i pingok=0
+	
+	#expired parameter, ready to be removed.	
+	declare -i taketime=0
+	
+	setting=(total_times_of_unload target_IP_for_pinging timeout_period security device_name SSID PSK_phrase scan_times)
+
+	test ! -f $1 && echo "The cfg file is not existed!!!"
+	for((index=0 ; index < ${#setting[@]} ; index = index + 1))
+   		do
+ 		VARS[$index]=$(cat $1|grep ${setting[$index]}|awk '{print $3}')
+		#echo $index : ${VARS[$index]}
+	done
+	#exit 0
+	echo "################################################################################" >> $2
+	echo "Unload/Reload test start at   : `date`" >> $2 	
+	echo "Prepare $1 times unload/reload test"
+	mkdir UnloadReloadScan
+	#start test loop, loop count in [i]	
+	for ((i = 1 ; i <= ${VARS[0]} ; i = i + 1))
+	do
+	
+	echo "Loading driver..."
+	sleep 2
+	echo "!!!Current round of testing will begin in 3 seconds, please prepare to sniffer packets!!!"
+	sleep 3
+	./load.sh
+	./scan_conn.sh ${VARS[4]} ${VARS[5]} ${VARS[6]} ${VARS[7]} ${VARS[3]} & #$4 $5 $6 $7 $3 &
+	# take $3 parameter as the period of [waiting for association ready and DHCP protocol completed].
+	echo "****** Ping start!!  ******"
+	for((w=1;w<=${VARS[2]};w=w+1))
+	do
+		if ping -W 1 -c 1 ${VARS[1]} >/dev/null; then
+			pingok=1
+			echo "LOOP[$i] : Connection established in $w seconds. (Passed / Failed / Total = $p / $f / ${VARS[0]})" >> $2		
+			break
+		else
+			pingok=0
+		fi
+
+		echo $w
+		sleep 1
+	done
+
+	if [ "$pingok" = 1 ]; then
+		pingok=0
+    		p=$p+1
+		echo "****** Ping Passed!! (Passed / Failed / Total = $p / $f / ${VARS[0]})******"
+		dmesg -c > "./UnloadReloadScan/Log.of.Passed.Loop[$i].txt"
+		echo "================================================================================" >> "./UnloadReloadScan/Log.of.Passed.Loop[$i].txt"
+		echo "`date` :Interface Information:" >> "./UnloadReloadScan/Log.of.Passed.Loop[$i].txt"
+		ifconfig >> "./UnloadReloadScan/Log.of.Passed.Loop[$i].txt"
+		echo "================================================================================" >> "./UnloadReloadScan/Log.of.Passed.Loop[$i].txt"
+
+		sleep 2
+	else    
+		pingok=0		
+		f=$f+1
+		echo "LOOP[$i] : Connection establishing timeout ! (Passed / Failed / Total = $p / $f / ${VARS[0]})" >> $2
+		echo "****** Ping Failed!! (Passed / Failed / Total = $p / $f / ${VARS[0]})******"
+		dmesg -c > "./UnloadReloadScan/Log.of.Failed.Loop[$i].txt"
+		echo "================================================================================" >> "./UnloadReloadScan/Log.of.Failed.Loop[$i].txt"
+		echo "`date` :Interface Information:" >> "./UnloadReloadScan/Log.of.Failed.Loop[$i].txt"
+		ifconfig >> "./UnloadReloadScan/Log.of.Failed.Loop[$i].txt"
+		echo "================================================================================" >> "./UnloadReloadScan/Log.of.Failed.Loop[$i].txt"
+	fi
+	
+	./scan_conn.sh ${VARS[4]} ${VARS[5]} off
+	sleep 1
+	echo "unloading driver"
+	./unload.sh
+	echo "========================================================="
+	echo "Current loop = $i"		
+	echo "Current Result : Passed / Failed / Total = $p / $f / ${VARS[0]}"		
+	echo "========================================================="
+	if [ "$i" = "${VARS[0]}" ]; then
+		echo "All test loops were finished..."
+		echo "Unload/Reload test finished at: `date`" >> $2
+		echo "Result : Passed / Failed / Total = $p / $f / ${VARS[0]}" >> $2
+		echo "################################################################################" >> $2
+		echo " " >> $2		
+	else		
+		#take a break for next loop.
+		echo "!!!Current round of testing is ended, please stop sniffer packets!!!"
+		sleep 3
+	fi
+	done
+fi
+
+
+
+
+
+
+
+
+
diff --git a/drivers/net/wireless/ssv6x5x/script/scratch b/drivers/net/wireless/ssv6x5x/script/scratch
new file mode 100755
index 000000000..9d0ee696c
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/scratch
@@ -0,0 +1,11 @@
+#!/bin/sh
+
+if [ "`whoami`" != "root" ]; then
+    echo Need to be root to execute.;
+    exit 1;
+fi
+
+cd ..
+make clean
+make -j 4
+make install
diff --git a/drivers/net/wireless/ssv6x5x/script/show_dbg_log.sh b/drivers/net/wireless/ssv6x5x/script/show_dbg_log.sh
new file mode 100755
index 000000000..f6bfeb81e
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/show_dbg_log.sh
@@ -0,0 +1,39 @@
+#!/bin/bash
+key_word="SSV|RSV"
+
+ssv_phy=""
+if [[ ${1} =~ "wlan" ]]; then
+	wlan_dirs=/sys/class/net/${1}/device/ieee80211/
+	if [ ! -e ${wlan_dirs} ]; then
+		echo "Could not find the ${1}."
+		exit 1;
+	fi
+	# shift wlanX
+	shift 1
+	ssv_phy=`ls ${wlan_dirs}`
+else
+	phy_dirs="/sys/class/ieee80211/*"
+
+	for phy_dir in $phy_dirs; do
+		if [ ! -d ${phy_dir}/device/driver ]; then
+			exit 1;
+		fi
+		drv_name=`ls ${phy_dir}/device/driver | grep -E $key_word`
+    	if [ -n ${drv_name} ]; then
+    		ssv_phy=`basename $phy_dir`;
+    		break;
+    	fi
+	done
+fi
+
+
+# excute CLI
+if [ -n ${ssv_phy} ]; then
+	SSV_CMD_FILE=/proc/ssv/${ssv_phy}/ssv_dbg_fs
+	if [ -f $SSV_CMD_FILE ]; then
+		cat $SSV_CMD_FILE
+	fi
+else 
+	echo "./show_dbg_log.sh [wlanX]"
+fi
+
diff --git a/drivers/net/wireless/ssv6x5x/script/showq b/drivers/net/wireless/ssv6x5x/script/showq
new file mode 100755
index 000000000..0c3703043
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/showq
@@ -0,0 +1,53 @@
+#!/bin/bash
+ssv_phy=""
+drv_name=""
+key_word="SSV|RSV"
+
+if [[ ${1} =~ "wlan" ]]; then
+	wlan_dirs=/sys/class/net/${1}/device/ieee80211/
+	if [ ! -e ${wlan_dirs} ]; then
+		echo "Could not find the ${1}."
+		exit 1;
+	fi
+	ssv_phy=`ls ${wlan_dirs}`
+	drv_name=`ls /sys/class/ieee80211/${ssv_phy}/device/driver | grep -E $key_word`
+else
+	phy_dirs="/sys/class/ieee80211/*"
+
+	for phy_dir in $phy_dirs; do
+		if [ ! -d ${phy_dir}/device/driver ]; then
+			exit 1;
+		fi
+		drv_name=`ls ${phy_dir}/device/driver | grep -E $key_word`
+    	if [ ${drv_name} ]; then
+    		ssv_phy=`basename $phy_dir`;
+    		break;
+    	fi
+	done
+fi
+
+
+# excute CLI
+if [ -z ${ssv_phy} ]; then
+    echo SSV PHY device not found.;
+    exit 1;
+fi
+
+ssv_debugfs_dir=/sys/kernel/debug/ieee80211/${ssv_phy}/${drv_name}
+if [ ! -d $ssv_debugfs_dir ]; then
+    echo SSV debugfs not found.;
+    exit 1;
+fi
+
+cd $ssv_debugfs_dir
+
+cat queue_status
+cat hci/hw_txq_len
+
+find . -name ampdu_tx_summary -exec cat {} \;
+
+SSV_CMD_FILE=/proc/ssv/${ssv_phy}/ssv_cmd
+if [ -f $SSV_CMD_FILE ]; then
+    echo "hwq" > $SSV_CMD_FILE
+    cat $SSV_CMD_FILE
+fi
diff --git a/drivers/net/wireless/ssv6x5x/script/ssvcfg.sh b/drivers/net/wireless/ssv6x5x/script/ssvcfg.sh
new file mode 100755
index 000000000..c1d4740ab
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/ssvcfg.sh
@@ -0,0 +1,35 @@
+#/bin/bash
+
+KVERSION="`uname -r`"
+kern_mod=/lib/modules/$KVERSION/kernel/drivers/net/wireless/ssv6200/ssvdevicetype.ko
+type_str=`lsmod | grep "ssvdevicetype"`
+cfg_file=sta.cfg
+if [ $# -ge 1 ]; then 
+    cfg_file=$1; 
+    echo Using configuration file $1
+else
+    echo Using default configuration file $cfg_file \($?\)
+fi
+cfg_cmds=(`cat $cfg_file  | grep '^[a-zA-Z0-9]' | sed 's/ //g'`)
+#echo ${#cfg_cmds[*]}
+#echo ${!cfg_cmds[*]}
+#echo ${cfg_cmds[1]}
+
+if [ "$type_str" != "" ]; then
+    #rmmod ssv6200_sdio
+    #rmmod ssv6200s_core
+    #rmmod ssv6200_hci
+    rmmod ssvdevicetype
+fi
+
+
+if [ -f $kern_mod ]; then
+    insmod $kern_mod stacfgpath="$cfg_file"
+    #insmod $kern_mod
+    #./cli cfg reset
+    #for cmd in ${cfg_cmds[*]}
+    #do
+	#./cli cfg `echo $cmd | sed 's/=/ = /g'`
+    #done
+fi
+
diff --git a/drivers/net/wireless/ssv6x5x/script/sta.cfg.template b/drivers/net/wireless/ssv6x5x/script/sta.cfg.template
new file mode 100755
index 000000000..9e9794814
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/sta.cfg.template
@@ -0,0 +1,79 @@
+
+hw_mac = MAC_ADDR
+hw_mac_2 = MAC2ADDR
+
+############################################################
+# MAC address
+#
+# Priority 1. From wifi.cfg [ hw_mac & hw_mac_2 ]
+#
+# Priority 2. From e-fuse[ON/OFF switch by wifi.cfg]
+#
+# Priority 3. From insert module parameter
+#
+# Priority 4. From external file path
+#   path only support some special charater "_" ":" "/" "." "-"
+#
+# Priority 5. Default[Software mode]
+#
+#   0. => 00:33:33:33:33:33
+#   1. => Always random
+#   2. => First random and write to file[Default path mac_output_path]
+#
+############################################################
+#ignore_efuse_mac = 1
+#mac_address_path = /xxxx/xxxx
+#mac_address_mode = 0
+#mac_output_path = /data/wifimac
+
+##################################################
+# Firmware setting
+# Priority.1 insmod parameter "cfgfirmwarepath"
+# Priority.2 firmware_path
+# Priority.3 default firmware
+##################################################
+#firmware_path = /lib/firmware/
+
+##################################################
+# Hardware setting
+#
+#volt regulator(DCDC-0 LDO-1)
+#
+##################################################
+xtal_clock = 26
+volt_regulator = 1
+
+##################################################
+# Default channel after wifi on
+# value range: [1 ~ 14]
+##################################################
+def_chan = 6
+
+# Hardware Capability Settings:
+##################################################
+hw_cap_ht = on
+hw_cap_gf = off
+hw_cap_2ghz = on
+hw_cap_5ghz = off
+hw_cap_security = on
+hw_cap_sgi_20 = on
+hw_cap_sgi_40 = off
+hw_cap_ap = on
+hw_cap_p2p = on
+hw_cap_ampdu_rx = on
+hw_cap_ampdu_tx = on
+hw_cap_tdls = off
+hw_cap_stbc = on
+
+use_wpa2_only = 1
+
+##################################################
+# TX power level setting [0-14]
+# The larger the number the smaller the TX power
+# 0 - The maximum power
+# 1 level = -0.5db
+##################################################
+wifi_tx_gain_level_b = 6
+wifi_tx_gain_level_gn = 4
+
+
diff --git a/drivers/net/wireless/ssv6x5x/script/sta.sh b/drivers/net/wireless/ssv6x5x/script/sta.sh
new file mode 100755
index 000000000..9ea3553da
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/sta.sh
@@ -0,0 +1,43 @@
+#!/bin/bash
+
+echo "=================================================="
+echo "1.Copy firmware"
+echo "=================================================="
+cp ../image/* /lib/firmware/
+
+echo "=================================================="
+echo "1.Unload Module"
+echo "=================================================="
+./unload.sh
+
+echo "=================================================="
+echo "2.Set Hardware Capability"
+echo "=================================================="
+
+eth0_local_mac=`ifconfig eth0  | grep HWaddr | sed -e 's/.*HWaddr //g' | sed -e 's/ //g' | cut -d ':' -f 4,5,6`
+[ "$eth0_local_mac" == "" ] && eth0_local_mac="45:67:89"
+local_mac=00:a5:b5:$eth0_local_mac
+local_mac_2=`echo $local_mac | cut -d ':' -f 6`
+local_mac_2=`printf '%x' $[ ( 16#$local_mac_2 + 1 ) % 4 + ( 16#$local_mac_2 & 16#FC ) ] `
+local_mac_2="`echo $local_mac | cut -d ':' -f 1,2,3,4,5`:$local_mac_2"
+
+echo WLAN MAC is $local_mac
+
+cat sta.cfg.template | sed -e "s/MAC_ADDR/$local_mac/g" | sed -e "s/MAC2ADDR/$local_mac_2/g" > sta_local_mac.cfg
+./ssvcfg.sh sta_local_mac.cfg
+
+echo "=================================================="
+echo "3.Load MMC Module"
+echo "=================================================="
+modprobe mmc_core sdiomaxclock=25000000
+modprobe sdhci
+modprobe sdhci-pci
+modprobe mmc_block
+
+echo "=================================================="
+echo "4.Load SSV6200 Driver"
+echo "=================================================="
+echo 6 > /proc/sys/kernel/printk
+
+#modprobe ssv6200_sdio
+
diff --git a/drivers/net/wireless/ssv6x5x/script/sta_usb.sh b/drivers/net/wireless/ssv6x5x/script/sta_usb.sh
new file mode 100755
index 000000000..acc531983
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/sta_usb.sh
@@ -0,0 +1,49 @@
+#!/bin/bash
+
+echo "=================================================="
+echo "1.Copy firmware"
+echo "=================================================="
+cp ../image/* /lib/firmware/
+
+echo "=================================================="
+echo "1.Unload Module"
+echo "=================================================="
+./unload.sh
+
+./gpio_reset.sh on
+
+echo "=================================================="
+echo "2.Set Hardware Capability"
+echo "=================================================="
+
+eth0_local_mac=`ifconfig eth0  | grep HWaddr | sed -e 's/.*HWaddr //g' | sed -e 's/ //g' | cut -d ':' -f 4,5,6`
+[ "$eth0_local_mac" == "" ] && eth0_local_mac="45:67:89"
+local_mac=00:a5:b5:$eth0_local_mac
+local_mac_2=`echo $local_mac | cut -d ':' -f 6`
+local_mac_2=`printf '%x' $[ ( 16#$local_mac_2 + 1 ) % 4 + ( 16#$local_mac_2 & 16#FC ) ] `
+local_mac_2="`echo $local_mac | cut -d ':' -f 1,2,3,4,5`:$local_mac_2"
+
+echo WLAN MAC is $local_mac
+
+sleep 1
+./gpio_reset.sh off
+sleep 1
+
+cat sta.cfg.template | sed -e "s/MAC_ADDR/$local_mac/g" | sed -e "s/MAC2ADDR/$local_mac_2/g" > sta_local_mac.cfg
+./ssvcfg.sh sta_local_mac.cfg
+
+echo "=================================================="
+echo "3.Load MMC Module"
+echo "=================================================="
+modprobe mmc_core
+modprobe sdhci
+modprobe sdhci-pci
+modprobe mmc_block
+
+echo "=================================================="
+echo "4.Load SSV6200 Driver"
+echo "=================================================="
+echo 6 > /proc/sys/kernel/printk
+
+#modprobe ssv6200_sdio
+
diff --git a/drivers/net/wireless/ssv6x5x/script/template/hostapd.conf b/drivers/net/wireless/ssv6x5x/script/template/hostapd.conf
new file mode 100755
index 000000000..c9a5f2d65
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/template/hostapd.conf
@@ -0,0 +1,1536 @@
+##### hostapd configuration file ##############################################
+# Empty lines and lines starting with # are ignored
+
+# AP netdevice name (without 'ap' postfix, i.e., wlan0 uses wlan0ap for
+# management frames); ath0 for madwifi
+interface=wlan@@
+
+# In case of madwifi, atheros, and nl80211 driver interfaces, an additional
+# configuration parameter, bridge, may be used to notify hostapd if the
+# interface is included in a bridge. This parameter is not used with Host AP
+# driver. If the bridge parameter is not set, the drivers will automatically
+# figure out the bridge interface (assuming sysfs is enabled and mounted to
+# /sys) and this parameter may not be needed.
+#
+# For nl80211, this parameter can be used to request the AP interface to be
+# added to the bridge automatically (brctl may refuse to do this before hostapd
+# has been started to change the interface mode). If needed, the bridge
+# interface is also created.
+#bridge=br0
+
+# Driver interface type (hostap/wired/madwifi/test/none/nl80211/bsd);
+# default: hostap). nl80211 is used with all Linux mac80211 drivers.
+# Use driver=none if building hostapd as a standalone RADIUS server that does
+# not control any wireless/wired driver.
+driver=nl80211
+
+# hostapd event logger configuration
+#
+# Two output method: syslog and stdout (only usable if not forking to
+# background).
+#
+# Module bitfield (ORed bitfield of modules that will be logged; -1 = all
+# modules):
+# bit 0 (1) = IEEE 802.11
+# bit 1 (2) = IEEE 802.1X
+# bit 2 (4) = RADIUS
+# bit 3 (8) = WPA
+# bit 4 (16) = driver interface
+# bit 5 (32) = IAPP
+# bit 6 (64) = MLME
+#
+# Levels (minimum value for logged events):
+#  0 = verbose debugging
+#  1 = debugging
+#  2 = informational messages
+#  3 = notification
+#  4 = warning
+#
+logger_syslog=-1
+logger_syslog_level=2
+logger_stdout=-1
+logger_stdout_level=2
+
+# Dump file for state information (on SIGUSR1)
+dump_file=/tmp/hostapd.dump
+
+# Interface for separate control program. If this is specified, hostapd
+# will create this directory and a UNIX domain socket for listening to requests
+# from external programs (CLI/GUI, etc.) for status information and
+# configuration. The socket file will be named based on the interface name, so
+# multiple hostapd processes/interfaces can be run at the same time if more
+# than one interface is used.
+# /var/run/hostapd is the recommended directory for sockets and by default,
+# hostapd_cli will use it when trying to connect with hostapd.
+ctrl_interface=/var/run/hostapd
+
+# Access control for the control interface can be configured by setting the
+# directory to allow only members of a group to use sockets. This way, it is
+# possible to run hostapd as root (since it needs to change network
+# configuration and open raw sockets) and still allow GUI/CLI components to be
+# run as non-root users. However, since the control interface can be used to
+# change the network configuration, this access needs to be protected in many
+# cases. By default, hostapd is configured to use gid 0 (root). If you
+# want to allow non-root users to use the contron interface, add a new group
+# and change this value to match with that group. Add users that should have
+# control interface access to this group.
+#
+# This variable can be a group name or gid.
+#ctrl_interface_group=wheel
+ctrl_interface_group=0
+
+
+##### IEEE 802.11 related configuration #######################################
+
+# SSID to be used in IEEE 802.11 management frames
+#ssid=SSVQATestAP
+# Alternative formats for configuring SSID
+# (double quoted string, hexdump, printf-escaped string)
+#ssid2="test"
+#ssid2=74657374
+#ssid2=P"hello\nthere"
+
+# UTF-8 SSID: Whether the SSID is to be interpreted using UTF-8 encoding
+#utf8_ssid=1
+
+# Country code (ISO/IEC 3166-1). Used to set regulatory domain.
+# Set as needed to indicate country in which device is operating.
+# This can limit available channels and transmit power.
+#country_code=US
+
+# Enable IEEE 802.11d. This advertises the country_code and the set of allowed
+# channels and transmit power levels based on the regulatory limits. The
+# country_code setting must be configured with the correct country for
+# IEEE 802.11d functions.
+# (default: 0 = disabled)
+#ieee80211d=1
+
+# Operation mode (a = IEEE 802.11a, b = IEEE 802.11b, g = IEEE 802.11g,
+# ad = IEEE 802.11ad (60 GHz); a/g options are used with IEEE 802.11n, too, to
+# specify band)
+# Default: IEEE 802.11b
+hw_mode=g
+
+# Channel number (IEEE 802.11)
+# (default: 0, i.e., not set)
+# Please note that some drivers do not use this value from hostapd and the
+# channel will need to be configured separately with iwconfig.
+#channel=6
+
+# Beacon interval in kus (1.024 ms) (default: 100; range 15..65535)
+beacon_int=100
+
+# DTIM (delivery traffic information message) period (range 1..255):
+# number of beacons between DTIMs (1 = every beacon includes DTIM element)
+# (default: 2)
+dtim_period=2
+
+# Maximum number of stations allowed in station table. New stations will be
+# rejected after the station table is full. IEEE 802.11 has a limit of 2007
+# different association IDs, so this number should not be larger than that.
+# (default: 2007)
+max_num_sta=8
+
+# RTS/CTS threshold; 2347 = disabled (default); range 0..2347
+# If this field is not included in hostapd.conf, hostapd will not control
+# RTS threshold and 'iwconfig wlan# rts <val>' can be used to set it.
+rts_threshold=2347
+
+# Fragmentation threshold; 2346 = disabled (default); range 256..2346
+# If this field is not included in hostapd.conf, hostapd will not control
+# fragmentation threshold and 'iwconfig wlan# frag <val>' can be used to set
+# it.
+fragm_threshold=2346
+
+# Rate configuration
+# Default is to enable all rates supported by the hardware. This configuration
+# item allows this list be filtered so that only the listed rates will be left
+# in the list. If the list is empty, all rates are used. This list can have
+# entries that are not in the list of rates the hardware supports (such entries
+# are ignored). The entries in this list are in 100 kbps, i.e., 11 Mbps = 110.
+# If this item is present, at least one rate have to be matching with the rates
+# hardware supports.
+# default: use the most common supported rate setting for the selected
+# hw_mode (i.e., this line can be removed from configuration file in most
+# cases)
+#supported_rates=10 20 55 110 60 90 120 180 240 360 480 540
+
+# Basic rate set configuration
+# List of rates (in 100 kbps) that are included in the basic rate set.
+# If this item is not included, usually reasonable default set is used.
+#basic_rates=10 20
+#basic_rates=10 20 55 110
+#basic_rates=60 120 240
+
+# Short Preamble
+# This parameter can be used to enable optional use of short preamble for
+# frames sent at 2 Mbps, 5.5 Mbps, and 11 Mbps to improve network performance.
+# This applies only to IEEE 802.11b-compatible networks and this should only be
+# enabled if the local hardware supports use of short preamble. If any of the
+# associated STAs do not support short preamble, use of short preamble will be
+# disabled (and enabled when such STAs disassociate) dynamically.
+# 0 = do not allow use of short preamble (default)
+# 1 = allow use of short preamble
+#preamble=1
+
+# Station MAC address -based authentication
+# Please note that this kind of access control requires a driver that uses
+# hostapd to take care of management frame processing and as such, this can be
+# used with driver=hostap or driver=nl80211, but not with driver=madwifi.
+# 0 = accept unless in deny list
+# 1 = deny unless in accept list
+# 2 = use external RADIUS server (accept/deny lists are searched first)
+macaddr_acl=0
+
+# Accept/deny lists are read from separate files (containing list of
+# MAC addresses, one per line). Use absolute path name to make sure that the
+# files can be read on SIGHUP configuration reloads.
+#accept_mac_file=/etc/hostapd.accept
+#deny_mac_file=/etc/hostapd.deny
+
+# IEEE 802.11 specifies two authentication algorithms. hostapd can be
+# configured to allow both of these or only one. Open system authentication
+# should be used with IEEE 802.1X.
+# Bit fields of allowed authentication algorithms:
+# bit 0 = Open System Authentication
+# bit 1 = Shared Key Authentication (requires WEP)
+auth_algs=3
+
+# Send empty SSID in beacons and ignore probe request frames that do not
+# specify full SSID, i.e., require stations to know SSID.
+# default: disabled (0)
+# 1 = send empty (length=0) SSID in beacon and ignore probe request for
+#     broadcast SSID
+# 2 = clear SSID (ASCII 0), but keep the original length (this may be required
+#     with some clients that do not support empty SSID) and ignore probe
+#     requests for broadcast SSID
+ignore_broadcast_ssid=0
+
+# Additional vendor specfic elements for Beacon and Probe Response frames
+# This parameter can be used to add additional vendor specific element(s) into
+# the end of the Beacon and Probe Response frames. The format for these
+# element(s) is a hexdump of the raw information elements (id+len+payload for
+# one or more elements)
+#vendor_elements=dd0411223301
+
+# TX queue parameters (EDCF / bursting)
+# tx_queue_<queue name>_<param>
+# queues: data0, data1, data2, data3, after_beacon, beacon
+#		(data0 is the highest priority queue)
+# parameters:
+#   aifs: AIFS (default 2)
+#   cwmin: cwMin (1, 3, 7, 15, 31, 63, 127, 255, 511, 1023)
+#   cwmax: cwMax (1, 3, 7, 15, 31, 63, 127, 255, 511, 1023); cwMax >= cwMin
+#   burst: maximum length (in milliseconds with precision of up to 0.1 ms) for
+#          bursting
+#
+# Default WMM parameters (IEEE 802.11 draft; 11-03-0504-03-000e):
+# These parameters are used by the access point when transmitting frames
+# to the clients.
+#
+# Low priority / AC_BK = background
+#tx_queue_data3_aifs=7
+#tx_queue_data3_cwmin=15
+#tx_queue_data3_cwmax=1023
+#tx_queue_data3_burst=0
+# Note: for IEEE 802.11b mode: cWmin=31 cWmax=1023 burst=0
+#
+# Normal priority / AC_BE = best effort
+#tx_queue_data2_aifs=3
+#tx_queue_data2_cwmin=15
+#tx_queue_data2_cwmax=63
+#tx_queue_data2_burst=0
+# Note: for IEEE 802.11b mode: cWmin=31 cWmax=127 burst=0
+#
+# High priority / AC_VI = video
+#tx_queue_data1_aifs=1
+#tx_queue_data1_cwmin=7
+#tx_queue_data1_cwmax=15
+#tx_queue_data1_burst=3.0
+# Note: for IEEE 802.11b mode: cWmin=15 cWmax=31 burst=6.0
+#
+# Highest priority / AC_VO = voice
+#tx_queue_data0_aifs=1
+#tx_queue_data0_cwmin=3
+#tx_queue_data0_cwmax=7
+#tx_queue_data0_burst=1.5
+# Note: for IEEE 802.11b mode: cWmin=7 cWmax=15 burst=3.3
+
+# 802.1D Tag (= UP) to AC mappings
+# WMM specifies following mapping of data frames to different ACs. This mapping
+# can be configured using Linux QoS/tc and sch_pktpri.o module.
+# 802.1D Tag	802.1D Designation	Access Category	WMM Designation
+# 1		BK			AC_BK		Background
+# 2		-			AC_BK		Background
+# 0		BE			AC_BE		Best Effort
+# 3		EE			AC_BE		Best Effort
+# 4		CL			AC_VI		Video
+# 5		VI			AC_VI		Video
+# 6		VO			AC_VO		Voice
+# 7		NC			AC_VO		Voice
+# Data frames with no priority information: AC_BE
+# Management frames: AC_VO
+# PS-Poll frames: AC_BE
+
+# Default WMM parameters (IEEE 802.11 draft; 11-03-0504-03-000e):
+# for 802.11a or 802.11g networks
+# These parameters are sent to WMM clients when they associate.
+# The parameters will be used by WMM clients for frames transmitted to the
+# access point.
+#
+# note - txop_limit is in units of 32microseconds
+# note - acm is admission control mandatory flag. 0 = admission control not
+# required, 1 = mandatory
+# note - here cwMin and cmMax are in exponent form. the actual cw value used
+# will be (2^n)-1 where n is the value given here
+#
+wmm_enabled=1
+#
+# WMM-PS Unscheduled Automatic Power Save Delivery [U-APSD]
+# Enable this flag if U-APSD supported outside hostapd (eg., Firmware/driver)
+#uapsd_advertisement_enabled=1
+#
+# Low priority / AC_BK = background
+wmm_ac_bk_cwmin=4
+wmm_ac_bk_cwmax=10
+wmm_ac_bk_aifs=7
+wmm_ac_bk_txop_limit=0
+wmm_ac_bk_acm=0
+# Note: for IEEE 802.11b mode: cWmin=5 cWmax=10
+#
+# Normal priority / AC_BE = best effort
+wmm_ac_be_aifs=3
+wmm_ac_be_cwmin=4
+wmm_ac_be_cwmax=10
+wmm_ac_be_txop_limit=0
+wmm_ac_be_acm=0
+# Note: for IEEE 802.11b mode: cWmin=5 cWmax=7
+#
+# High priority / AC_VI = video
+wmm_ac_vi_aifs=2
+wmm_ac_vi_cwmin=3
+wmm_ac_vi_cwmax=4
+wmm_ac_vi_txop_limit=94
+wmm_ac_vi_acm=0
+# Note: for IEEE 802.11b mode: cWmin=4 cWmax=5 txop_limit=188
+#
+# Highest priority / AC_VO = voice
+wmm_ac_vo_aifs=2
+wmm_ac_vo_cwmin=2
+wmm_ac_vo_cwmax=3
+wmm_ac_vo_txop_limit=47
+wmm_ac_vo_acm=0
+# Note: for IEEE 802.11b mode: cWmin=3 cWmax=4 burst=102
+
+# Static WEP key configuration
+#
+# The key number to use when transmitting.
+# It must be between 0 and 3, and the corresponding key must be set.
+# default: not set
+#wep_default_key=0
+# The WEP keys to use.
+# A key may be a quoted string or unquoted hexadecimal digits.
+# The key length should be 5, 13, or 16 characters, or 10, 26, or 32
+# digits, depending on whether 40-bit (64-bit), 104-bit (128-bit), or
+# 128-bit (152-bit) WEP is used.
+# Only the default key must be supplied; the others are optional.
+# default: not set
+#wep_key0=123456789a
+#wep_key1="vwxyz"
+#wep_key2=0102030405060708090a0b0c0d
+#wep_key3=".2.4.6.8.0.23"
+
+# Station inactivity limit
+#
+# If a station does not send anything in ap_max_inactivity seconds, an
+# empty data frame is sent to it in order to verify whether it is
+# still in range. If this frame is not ACKed, the station will be
+# disassociated and then deauthenticated. This feature is used to
+# clear station table of old entries when the STAs move out of the
+# range.
+#
+# The station can associate again with the AP if it is still in range;
+# this inactivity poll is just used as a nicer way of verifying
+# inactivity; i.e., client will not report broken connection because
+# disassociation frame is not sent immediately without first polling
+# the STA with a data frame.
+# default: 300 (i.e., 5 minutes)
+#ap_max_inactivity=300
+#
+# The inactivity polling can be disabled to disconnect stations based on
+# inactivity timeout so that idle stations are more likely to be disconnected
+# even if they are still in range of the AP. This can be done by setting
+# skip_inactivity_poll to 1 (default 0).
+#skip_inactivity_poll=0
+
+# Disassociate stations based on excessive transmission failures or other
+# indications of connection loss. This depends on the driver capabilities and
+# may not be available with all drivers.
+#disassoc_low_ack=1
+
+# Maximum allowed Listen Interval (how many Beacon periods STAs are allowed to
+# remain asleep). Default: 65535 (no limit apart from field size)
+#max_listen_interval=100
+
+# WDS (4-address frame) mode with per-station virtual interfaces
+# (only supported with driver=nl80211)
+# This mode allows associated stations to use 4-address frames to allow layer 2
+# bridging to be used.
+#wds_sta=1
+
+# If bridge parameter is set, the WDS STA interface will be added to the same
+# bridge by default. This can be overridden with the wds_bridge parameter to
+# use a separate bridge.
+#wds_bridge=wds-br0
+
+# Client isolation can be used to prevent low-level bridging of frames between
+# associated stations in the BSS. By default, this bridging is allowed.
+#ap_isolate=1
+
+##### IEEE 802.11n related configuration ######################################
+
+# ieee80211n: Whether IEEE 802.11n (HT) is enabled
+# 0 = disabled (default)
+# 1 = enabled
+# Note: You will also need to enable WMM for full HT functionality.
+#ieee80211n=1
+
+# ht_capab: HT capabilities (list of flags)
+# LDPC coding capability: [LDPC] = supported
+# Supported channel width set: [HT40-] = both 20 MHz and 40 MHz with secondary
+#	channel below the primary channel; [HT40+] = both 20 MHz and 40 MHz
+#	with secondary channel below the primary channel
+#	(20 MHz only if neither is set)
+#	Note: There are limits on which channels can be used with HT40- and
+#	HT40+. Following table shows the channels that may be available for
+#	HT40- and HT40+ use per IEEE 802.11n Annex J:
+#	freq		HT40-		HT40+
+#	2.4 GHz		5-13		1-7 (1-9 in Europe/Japan)
+#	5 GHz		40,48,56,64	36,44,52,60
+#	(depending on the location, not all of these channels may be available
+#	for use)
+#	Please note that 40 MHz channels may switch their primary and secondary
+#	channels if needed or creation of 40 MHz channel maybe rejected based
+#	on overlapping BSSes. These changes are done automatically when hostapd
+#	is setting up the 40 MHz channel.
+# Spatial Multiplexing (SM) Power Save: [SMPS-STATIC] or [SMPS-DYNAMIC]
+#	(SMPS disabled if neither is set)
+# HT-greenfield: [GF] (disabled if not set)
+# Short GI for 20 MHz: [SHORT-GI-20] (disabled if not set)
+# Short GI for 40 MHz: [SHORT-GI-40] (disabled if not set)
+# Tx STBC: [TX-STBC] (disabled if not set)
+# Rx STBC: [RX-STBC1] (one spatial stream), [RX-STBC12] (one or two spatial
+#	streams), or [RX-STBC123] (one, two, or three spatial streams); Rx STBC
+#	disabled if none of these set
+# HT-delayed Block Ack: [DELAYED-BA] (disabled if not set)
+# Maximum A-MSDU length: [MAX-AMSDU-7935] for 7935 octets (3839 octets if not
+#	set)
+# DSSS/CCK Mode in 40 MHz: [DSSS_CCK-40] = allowed (not allowed if not set)
+# PSMP support: [PSMP] (disabled if not set)
+# L-SIG TXOP protection support: [LSIG-TXOP-PROT] (disabled if not set)
+#ht_capab=[SHORT-GI-20]
+
+# Require stations to support HT PHY (reject association if they do not)
+#require_ht=1
+
+##### IEEE 802.11ac related configuration #####################################
+
+# ieee80211ac: Whether IEEE 802.11ac (VHT) is enabled
+# 0 = disabled (default)
+# 1 = enabled
+# Note: You will also need to enable WMM for full VHT functionality.
+#ieee80211ac=1
+
+# vht_capab: VHT capabilities (list of flags)
+#
+# vht_max_mpdu_len: [MAX-MPDU-7991] [MAX-MPDU-11454]
+# Indicates maximum MPDU length
+# 0 = 3895 octets (default)
+# 1 = 7991 octets
+# 2 = 11454 octets
+# 3 = reserved
+#
+# supported_chan_width: [VHT160] [VHT160-80PLUS80]
+# Indicates supported Channel widths
+# 0 = 160 MHz & 80+80 channel widths are not supported (default)
+# 1 = 160 MHz channel width is supported
+# 2 = 160 MHz & 80+80 channel widths are supported
+# 3 = reserved
+#
+# Rx LDPC coding capability: [RXLDPC]
+# Indicates support for receiving LDPC coded pkts
+# 0 = Not supported (default)
+# 1 = Supported
+#
+# Short GI for 80 MHz: [SHORT-GI-80]
+# Indicates short GI support for reception of packets transmitted with TXVECTOR
+# params format equal to VHT and CBW = 80Mhz
+# 0 = Not supported (default)
+# 1 = Supported
+#
+# Short GI for 160 MHz: [SHORT-GI-160]
+# Indicates short GI support for reception of packets transmitted with TXVECTOR
+# params format equal to VHT and CBW = 160Mhz
+# 0 = Not supported (default)
+# 1 = Supported
+#
+# Tx STBC: [TX-STBC-2BY1]
+# Indicates support for the transmission of at least 2x1 STBC
+# 0 = Not supported (default)
+# 1 = Supported
+#
+# Rx STBC: [RX-STBC-1] [RX-STBC-12] [RX-STBC-123] [RX-STBC-1234]
+# Indicates support for the reception of PPDUs using STBC
+# 0 = Not supported (default)
+# 1 = support of one spatial stream
+# 2 = support of one and two spatial streams
+# 3 = support of one, two and three spatial streams
+# 4 = support of one, two, three and four spatial streams
+# 5,6,7 = reserved
+#
+# SU Beamformer Capable: [SU-BEAMFORMER]
+# Indicates support for operation as a single user beamformer
+# 0 = Not supported (default)
+# 1 = Supported
+#
+# SU Beamformee Capable: [SU-BEAMFORMEE]
+# Indicates support for operation as a single user beamformee
+# 0 = Not supported (default)
+# 1 = Supported
+#
+# Compressed Steering Number of Beamformer Antennas Supported: [BF-ANTENNA-2]
+#   Beamformee's capability indicating the maximum number of beamformer
+#   antennas the beamformee can support when sending compressed beamforming
+#   feedback
+# If SU beamformer capable, set to maximum value minus 1
+# else reserved (default)
+#
+# Number of Sounding Dimensions: [SOUNDING-DIMENSION-2]
+# Beamformer's capability indicating the maximum value of the NUM_STS parameter
+# in the TXVECTOR of a VHT NDP
+# If SU beamformer capable, set to maximum value minus 1
+# else reserved (default)
+#
+# MU Beamformer Capable: [MU-BEAMFORMER]
+# Indicates support for operation as an MU beamformer
+# 0 = Not supported or sent by Non-AP STA (default)
+# 1 = Supported
+#
+# MU Beamformee Capable: [MU-BEAMFORMEE]
+# Indicates support for operation as an MU beamformee
+# 0 = Not supported or sent by AP (default)
+# 1 = Supported
+#
+# VHT TXOP PS: [VHT-TXOP-PS]
+# Indicates whether or not the AP supports VHT TXOP Power Save Mode
+#  or whether or not the STA is in VHT TXOP Power Save mode
+# 0 = VHT AP doesnt support VHT TXOP PS mode (OR) VHT Sta not in VHT TXOP PS
+#  mode
+# 1 = VHT AP supports VHT TXOP PS mode (OR) VHT Sta is in VHT TXOP power save
+#  mode
+#
+# +HTC-VHT Capable: [HTC-VHT]
+# Indicates whether or not the STA supports receiving a VHT variant HT Control
+# field.
+# 0 = Not supported (default)
+# 1 = supported
+#
+# Maximum A-MPDU Length Exponent: [MAX-A-MPDU-LEN-EXP0]..[MAX-A-MPDU-LEN-EXP7]
+# Indicates the maximum length of A-MPDU pre-EOF padding that the STA can recv
+# This field is an integer in the range of 0 to 7.
+# The length defined by this field is equal to
+# 2 pow(13 + Maximum A-MPDU Length Exponent) -1 octets
+#
+# VHT Link Adaptation Capable: [VHT-LINK-ADAPT2] [VHT-LINK-ADAPT3]
+# Indicates whether or not the STA supports link adaptation using VHT variant
+# HT Control field
+# If +HTC-VHTcapable is 1
+#  0 = (no feedback) if the STA does not provide VHT MFB (default)
+#  1 = reserved
+#  2 = (Unsolicited) if the STA provides only unsolicited VHT MFB
+#  3 = (Both) if the STA can provide VHT MFB in response to VHT MRQ and if the
+#      STA provides unsolicited VHT MFB
+# Reserved if +HTC-VHTcapable is 0
+#
+# Rx Antenna Pattern Consistency: [RX-ANTENNA-PATTERN]
+# Indicates the possibility of Rx antenna pattern change
+# 0 = Rx antenna pattern might change during the lifetime of an association
+# 1 = Rx antenna pattern does not change during the lifetime of an association
+#
+# Tx Antenna Pattern Consistency: [TX-ANTENNA-PATTERN]
+# Indicates the possibility of Tx antenna pattern change
+# 0 = Tx antenna pattern might change during the lifetime of an association
+# 1 = Tx antenna pattern does not change during the lifetime of an association
+#vht_capab=[SHORT-GI-80][HTC-VHT]
+#
+# Require stations to support VHT PHY (reject association if they do not)
+#require_vht=1
+
+# 0 = 20 or 40 MHz operating Channel width
+# 1 = 80 MHz channel width
+# 2 = 160 MHz channel width
+# 3 = 80+80 MHz channel width
+#vht_oper_chwidth=1
+#
+# center freq = 5 GHz + (5 * index)
+# So index 42 gives center freq 5.210 GHz
+# which is channel 42 in 5G band
+#
+#vht_oper_centr_freq_seg0_idx=42
+#
+# center freq = 5 GHz + (5 * index)
+# So index 159 gives center freq 5.795 GHz
+# which is channel 159 in 5G band
+#
+#vht_oper_centr_freq_seg1_idx=159
+
+##### IEEE 802.1X-2004 related configuration ##################################
+
+# Require IEEE 802.1X authorization
+#ieee8021x=1
+
+# IEEE 802.1X/EAPOL version
+# hostapd is implemented based on IEEE Std 802.1X-2004 which defines EAPOL
+# version 2. However, there are many client implementations that do not handle
+# the new version number correctly (they seem to drop the frames completely).
+# In order to make hostapd interoperate with these clients, the version number
+# can be set to the older version (1) with this configuration value.
+#eapol_version=2
+
+# Optional displayable message sent with EAP Request-Identity. The first \0
+# in this string will be converted to ASCII-0 (nul). This can be used to
+# separate network info (comma separated list of attribute=value pairs); see,
+# e.g., RFC 4284.
+#eap_message=hello
+#eap_message=hello\0networkid=netw,nasid=foo,portid=0,NAIRealms=example.com
+
+# WEP rekeying (disabled if key lengths are not set or are set to 0)
+# Key lengths for default/broadcast and individual/unicast keys:
+# 5 = 40-bit WEP (also known as 64-bit WEP with 40 secret bits)
+# 13 = 104-bit WEP (also known as 128-bit WEP with 104 secret bits)
+#wep_key_len_broadcast=5
+#wep_key_len_unicast=5
+# Rekeying period in seconds. 0 = do not rekey (i.e., set keys only once)
+#wep_rekey_period=300
+
+# EAPOL-Key index workaround (set bit7) for WinXP Supplicant (needed only if
+# only broadcast keys are used)
+eapol_key_index_workaround=0
+
+# EAP reauthentication period in seconds (default: 3600 seconds; 0 = disable
+# reauthentication).
+#eap_reauth_period=3600
+
+# Use PAE group address (01:80:c2:00:00:03) instead of individual target
+# address when sending EAPOL frames with driver=wired. This is the most common
+# mechanism used in wired authentication, but it also requires that the port
+# is only used by one station.
+#use_pae_group_addr=1
+
+##### Integrated EAP server ###################################################
+
+# Optionally, hostapd can be configured to use an integrated EAP server
+# to process EAP authentication locally without need for an external RADIUS
+# server. This functionality can be used both as a local authentication server
+# for IEEE 802.1X/EAPOL and as a RADIUS server for other devices.
+
+# Use integrated EAP server instead of external RADIUS authentication
+# server. This is also needed if hostapd is configured to act as a RADIUS
+# authentication server.
+#eap_server=0
+
+# Path for EAP server user database
+# If SQLite support is included, this can be set to "sqlite:/path/to/sqlite.db"
+# to use SQLite database instead of a text file.
+#eap_user_file=/etc/hostapd.eap_user
+
+# CA certificate (PEM or DER file) for EAP-TLS/PEAP/TTLS
+#ca_cert=/etc/hostapd.ca.pem
+
+# Server certificate (PEM or DER file) for EAP-TLS/PEAP/TTLS
+#server_cert=/etc/hostapd.server.pem
+
+# Private key matching with the server certificate for EAP-TLS/PEAP/TTLS
+# This may point to the same file as server_cert if both certificate and key
+# are included in a single file. PKCS#12 (PFX) file (.p12/.pfx) can also be
+# used by commenting out server_cert and specifying the PFX file as the
+# private_key.
+#private_key=/etc/hostapd.server.prv
+
+# Passphrase for private key
+#private_key_passwd=secret passphrase
+
+# Enable CRL verification.
+# Note: hostapd does not yet support CRL downloading based on CDP. Thus, a
+# valid CRL signed by the CA is required to be included in the ca_cert file.
+# This can be done by using PEM format for CA certificate and CRL and
+# concatenating these into one file. Whenever CRL changes, hostapd needs to be
+# restarted to take the new CRL into use.
+# 0 = do not verify CRLs (default)
+# 1 = check the CRL of the user certificate
+# 2 = check all CRLs in the certificate path
+#check_crl=1
+
+# dh_file: File path to DH/DSA parameters file (in PEM format)
+# This is an optional configuration file for setting parameters for an
+# ephemeral DH key exchange. In most cases, the default RSA authentication does
+# not use this configuration. However, it is possible setup RSA to use
+# ephemeral DH key exchange. In addition, ciphers with DSA keys always use
+# ephemeral DH keys. This can be used to achieve forward secrecy. If the file
+# is in DSA parameters format, it will be automatically converted into DH
+# params. This parameter is required if anonymous EAP-FAST is used.
+# You can generate DH parameters file with OpenSSL, e.g.,
+# "openssl dhparam -out /etc/hostapd.dh.pem 1024"
+#dh_file=/etc/hostapd.dh.pem
+
+# Fragment size for EAP methods
+#fragment_size=1400
+
+# Finite cyclic group for EAP-pwd. Number maps to group of domain parameters
+# using the IANA repository for IKE (RFC 2409).
+#pwd_group=19
+
+# Configuration data for EAP-SIM database/authentication gateway interface.
+# This is a text string in implementation specific format. The example
+# implementation in eap_sim_db.c uses this as the UNIX domain socket name for
+# the HLR/AuC gateway (e.g., hlr_auc_gw). In this case, the path uses "unix:"
+# prefix. If hostapd is built with SQLite support (CONFIG_SQLITE=y in .config),
+# database file can be described with an optional db=<path> parameter.
+#eap_sim_db=unix:/tmp/hlr_auc_gw.sock
+#eap_sim_db=unix:/tmp/hlr_auc_gw.sock db=/tmp/hostapd.db
+
+# Encryption key for EAP-FAST PAC-Opaque values. This key must be a secret,
+# random value. It is configured as a 16-octet value in hex format. It can be
+# generated, e.g., with the following command:
+# od -tx1 -v -N16 /dev/random | colrm 1 8 | tr -d ' '
+#pac_opaque_encr_key=000102030405060708090a0b0c0d0e0f
+
+# EAP-FAST authority identity (A-ID)
+# A-ID indicates the identity of the authority that issues PACs. The A-ID
+# should be unique across all issuing servers. In theory, this is a variable
+# length field, but due to some existing implementations requiring A-ID to be
+# 16 octets in length, it is strongly recommended to use that length for the
+# field to provid interoperability with deployed peer implementations. This
+# field is configured in hex format.
+#eap_fast_a_id=101112131415161718191a1b1c1d1e1f
+
+# EAP-FAST authority identifier information (A-ID-Info)
+# This is a user-friendly name for the A-ID. For example, the enterprise name
+# and server name in a human-readable format. This field is encoded as UTF-8.
+#eap_fast_a_id_info=test server
+
+# Enable/disable different EAP-FAST provisioning modes:
+#0 = provisioning disabled
+#1 = only anonymous provisioning allowed
+#2 = only authenticated provisioning allowed
+#3 = both provisioning modes allowed (default)
+#eap_fast_prov=3
+
+# EAP-FAST PAC-Key lifetime in seconds (hard limit)
+#pac_key_lifetime=604800
+
+# EAP-FAST PAC-Key refresh time in seconds (soft limit on remaining hard
+# limit). The server will generate a new PAC-Key when this number of seconds
+# (or fewer) of the lifetime remains.
+#pac_key_refresh_time=86400
+
+# EAP-SIM and EAP-AKA protected success/failure indication using AT_RESULT_IND
+# (default: 0 = disabled).
+#eap_sim_aka_result_ind=1
+
+# Trusted Network Connect (TNC)
+# If enabled, TNC validation will be required before the peer is allowed to
+# connect. Note: This is only used with EAP-TTLS and EAP-FAST. If any other
+# EAP method is enabled, the peer will be allowed to connect without TNC.
+#tnc=1
+
+
+##### IEEE 802.11f - Inter-Access Point Protocol (IAPP) #######################
+
+# Interface to be used for IAPP broadcast packets
+#iapp_interface=eth0
+
+
+##### RADIUS client configuration #############################################
+# for IEEE 802.1X with external Authentication Server, IEEE 802.11
+# authentication with external ACL for MAC addresses, and accounting
+
+# The own IP address of the access point (used as NAS-IP-Address)
+own_ip_addr=127.0.0.1
+
+# Optional NAS-Identifier string for RADIUS messages. When used, this should be
+# a unique to the NAS within the scope of the RADIUS server. For example, a
+# fully qualified domain name can be used here.
+# When using IEEE 802.11r, nas_identifier must be set and must be between 1 and
+# 48 octets long.
+#nas_identifier=ap.example.com
+
+# RADIUS authentication server
+#auth_server_addr=127.0.0.1
+#auth_server_port=1812
+#auth_server_shared_secret=secret
+
+# RADIUS accounting server
+#acct_server_addr=127.0.0.1
+#acct_server_port=1813
+#acct_server_shared_secret=secret
+
+# Secondary RADIUS servers; to be used if primary one does not reply to
+# RADIUS packets. These are optional and there can be more than one secondary
+# server listed.
+#auth_server_addr=127.0.0.2
+#auth_server_port=1812
+#auth_server_shared_secret=secret2
+#
+#acct_server_addr=127.0.0.2
+#acct_server_port=1813
+#acct_server_shared_secret=secret2
+
+# Retry interval for trying to return to the primary RADIUS server (in
+# seconds). RADIUS client code will automatically try to use the next server
+# when the current server is not replying to requests. If this interval is set,
+# primary server will be retried after configured amount of time even if the
+# currently used secondary server is still working.
+#radius_retry_primary_interval=600
+
+
+# Interim accounting update interval
+# If this is set (larger than 0) and acct_server is configured, hostapd will
+# send interim accounting updates every N seconds. Note: if set, this overrides
+# possible Acct-Interim-Interval attribute in Access-Accept message. Thus, this
+# value should not be configured in hostapd.conf, if RADIUS server is used to
+# control the interim interval.
+# This value should not be less 600 (10 minutes) and must not be less than
+# 60 (1 minute).
+#radius_acct_interim_interval=600
+
+# Request Chargeable-User-Identity (RFC 4372)
+# This parameter can be used to configure hostapd to request CUI from the
+# RADIUS server by including Chargeable-User-Identity attribute into
+# Access-Request packets.
+#radius_request_cui=1
+
+# Dynamic VLAN mode; allow RADIUS authentication server to decide which VLAN
+# is used for the stations. This information is parsed from following RADIUS
+# attributes based on RFC 3580 and RFC 2868: Tunnel-Type (value 13 = VLAN),
+# Tunnel-Medium-Type (value 6 = IEEE 802), Tunnel-Private-Group-ID (value
+# VLANID as a string). vlan_file option below must be configured if dynamic
+# VLANs are used. Optionally, the local MAC ACL list (accept_mac_file) can be
+# used to set static client MAC address to VLAN ID mapping.
+# 0 = disabled (default)
+# 1 = option; use default interface if RADIUS server does not include VLAN ID
+# 2 = required; reject authentication if RADIUS server does not include VLAN ID
+#dynamic_vlan=0
+
+# VLAN interface list for dynamic VLAN mode is read from a separate text file.
+# This list is used to map VLAN ID from the RADIUS server to a network
+# interface. Each station is bound to one interface in the same way as with
+# multiple BSSIDs or SSIDs. Each line in this text file is defining a new
+# interface and the line must include VLAN ID and interface name separated by
+# white space (space or tab).
+#vlan_file=/etc/hostapd.vlan
+
+# Interface where 802.1q tagged packets should appear when a RADIUS server is
+# used to determine which VLAN a station is on.  hostapd creates a bridge for
+# each VLAN.  Then hostapd adds a VLAN interface (associated with the interface
+# indicated by 'vlan_tagged_interface') and the appropriate wireless interface
+# to the bridge.
+#vlan_tagged_interface=eth0
+
+# When hostapd creates a VLAN interface on vlan_tagged_interfaces, it needs
+# to know how to name it.
+# 0 = vlan<XXX>, e.g., vlan1
+# 1 = <vlan_tagged_interface>.<XXX>, e.g. eth0.1
+#vlan_naming=0
+
+# Arbitrary RADIUS attributes can be added into Access-Request and
+# Accounting-Request packets by specifying the contents of the attributes with
+# the following configuration parameters. There can be multiple of these to
+# add multiple attributes. These parameters can also be used to override some
+# of the attributes added automatically by hostapd.
+# Format: <attr_id>[:<syntax:value>]
+# attr_id: RADIUS attribute type (e.g., 26 = Vendor-Specific)
+# syntax: s = string (UTF-8), d = integer, x = octet string
+# value: attribute value in format indicated by the syntax
+# If syntax and value parts are omitted, a null value (single 0x00 octet) is
+# used.
+#
+# Additional Access-Request attributes
+# radius_auth_req_attr=<attr_id>[:<syntax:value>]
+# Examples:
+# Operator-Name = "Operator"
+#radius_auth_req_attr=126:s:Operator
+# Service-Type = Framed (2)
+#radius_auth_req_attr=6:d:2
+# Connect-Info = "testing" (this overrides the automatically generated value)
+#radius_auth_req_attr=77:s:testing
+# Same Connect-Info value set as a hexdump
+#radius_auth_req_attr=77:x:74657374696e67
+
+#
+# Additional Accounting-Request attributes
+# radius_acct_req_attr=<attr_id>[:<syntax:value>]
+# Examples:
+# Operator-Name = "Operator"
+#radius_acct_req_attr=126:s:Operator
+
+# Dynamic Authorization Extensions (RFC 5176)
+# This mechanism can be used to allow dynamic changes to user session based on
+# commands from a RADIUS server (or some other disconnect client that has the
+# needed session information). For example, Disconnect message can be used to
+# request an associated station to be disconnected.
+#
+# This is disabled by default. Set radius_das_port to non-zero UDP port
+# number to enable.
+#radius_das_port=3799
+#
+# DAS client (the host that can send Disconnect/CoA requests) and shared secret
+#radius_das_client=192.168.1.123 shared secret here
+#
+# DAS Event-Timestamp time window in seconds
+#radius_das_time_window=300
+#
+# DAS require Event-Timestamp
+#radius_das_require_event_timestamp=1
+
+##### RADIUS authentication server configuration ##############################
+
+# hostapd can be used as a RADIUS authentication server for other hosts. This
+# requires that the integrated EAP server is also enabled and both
+# authentication services are sharing the same configuration.
+
+# File name of the RADIUS clients configuration for the RADIUS server. If this
+# commented out, RADIUS server is disabled.
+#radius_server_clients=/etc/hostapd.radius_clients
+
+# The UDP port number for the RADIUS authentication server
+#radius_server_auth_port=1812
+
+# Use IPv6 with RADIUS server (IPv4 will also be supported using IPv6 API)
+#radius_server_ipv6=1
+
+
+##### WPA/IEEE 802.11i configuration ##########################################
+
+# Enable WPA. Setting this variable configures the AP to require WPA (either
+# WPA-PSK or WPA-RADIUS/EAP based on other configuration). For WPA-PSK, either
+# wpa_psk or wpa_passphrase must be set and wpa_key_mgmt must include WPA-PSK.
+# Instead of wpa_psk / wpa_passphrase, wpa_psk_radius might suffice.
+# For WPA-RADIUS/EAP, ieee8021x must be set (but without dynamic WEP keys),
+# RADIUS authentication server must be configured, and WPA-EAP must be included
+# in wpa_key_mgmt.
+# This field is a bit field that can be used to enable WPA (IEEE 802.11i/D3.0)
+# and/or WPA2 (full IEEE 802.11i/RSN):
+# bit0 = WPA
+# bit1 = IEEE 802.11i/RSN (WPA2) (dot11RSNAEnabled)
+#wpa=1
+
+# WPA pre-shared keys for WPA-PSK. This can be either entered as a 256-bit
+# secret in hex format (64 hex digits), wpa_psk, or as an ASCII passphrase
+# (8..63 characters) that will be converted to PSK. This conversion uses SSID
+# so the PSK changes when ASCII passphrase is used and the SSID is changed.
+# wpa_psk (dot11RSNAConfigPSKValue)
+# wpa_passphrase (dot11RSNAConfigPSKPassPhrase)
+#wpa_psk=0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef
+#wpa_passphrase=secret passphrase
+
+# Optionally, WPA PSKs can be read from a separate text file (containing list
+# of (PSK,MAC address) pairs. This allows more than one PSK to be configured.
+# Use absolute path name to make sure that the files can be read on SIGHUP
+# configuration reloads.
+#wpa_psk_file=/etc/hostapd.wpa_psk
+
+# Optionally, WPA passphrase can be received from RADIUS authentication server
+# This requires macaddr_acl to be set to 2 (RADIUS)
+# 0 = disabled (default)
+# 1 = optional; use default passphrase/psk if RADIUS server does not include
+#	Tunnel-Password
+# 2 = required; reject authentication if RADIUS server does not include
+#	Tunnel-Password
+#wpa_psk_radius=0
+
+# Set of accepted key management algorithms (WPA-PSK, WPA-EAP, or both). The
+# entries are separated with a space. WPA-PSK-SHA256 and WPA-EAP-SHA256 can be
+# added to enable SHA256-based stronger algorithms.
+# (dot11RSNAConfigAuthenticationSuitesTable)
+#wpa_key_mgmt=WPA-PSK WPA-EAP
+
+# Set of accepted cipher suites (encryption algorithms) for pairwise keys
+# (unicast packets). This is a space separated list of algorithms:
+# CCMP = AES in Counter mode with CBC-MAC [RFC 3610, IEEE 802.11i/D7.0]
+# TKIP = Temporal Key Integrity Protocol [IEEE 802.11i/D7.0]
+# Group cipher suite (encryption algorithm for broadcast and multicast frames)
+# is automatically selected based on this configuration. If only CCMP is
+# allowed as the pairwise cipher, group cipher will also be CCMP. Otherwise,
+# TKIP will be used as the group cipher.
+# (dot11RSNAConfigPairwiseCiphersTable)
+# Pairwise cipher for WPA (v1) (default: TKIP)
+#wpa_pairwise=TKIP CCMP
+# Pairwise cipher for RSN/WPA2 (default: use wpa_pairwise value)
+#rsn_pairwise=CCMP
+
+# Time interval for rekeying GTK (broadcast/multicast encryption keys) in
+# seconds. (dot11RSNAConfigGroupRekeyTime)
+#wpa_group_rekey=600
+
+# Rekey GTK when any STA that possesses the current GTK is leaving the BSS.
+# (dot11RSNAConfigGroupRekeyStrict)
+#wpa_strict_rekey=1
+
+# Time interval for rekeying GMK (master key used internally to generate GTKs
+# (in seconds).
+#wpa_gmk_rekey=86400
+
+# Maximum lifetime for PTK in seconds. This can be used to enforce rekeying of
+# PTK to mitigate some attacks against TKIP deficiencies.
+#wpa_ptk_rekey=600
+
+# Enable IEEE 802.11i/RSN/WPA2 pre-authentication. This is used to speed up
+# roaming be pre-authenticating IEEE 802.1X/EAP part of the full RSN
+# authentication and key handshake before actually associating with a new AP.
+# (dot11RSNAPreauthenticationEnabled)
+#rsn_preauth=1
+#
+# Space separated list of interfaces from which pre-authentication frames are
+# accepted (e.g., 'eth0' or 'eth0 wlan0wds0'. This list should include all
+# interface that are used for connections to other APs. This could include
+# wired interfaces and WDS links. The normal wireless data interface towards
+# associated stations (e.g., wlan0) should not be added, since
+# pre-authentication is only used with APs other than the currently associated
+# one.
+#rsn_preauth_interfaces=eth0
+
+# peerkey: Whether PeerKey negotiation for direct links (IEEE 802.11e) is
+# allowed. This is only used with RSN/WPA2.
+# 0 = disabled (default)
+# 1 = enabled
+#peerkey=1
+
+# ieee80211w: Whether management frame protection (MFP) is enabled
+# 0 = disabled (default)
+# 1 = optional
+# 2 = required
+#ieee80211w=0
+
+# Association SA Query maximum timeout (in TU = 1.024 ms; for MFP)
+# (maximum time to wait for a SA Query response)
+# dot11AssociationSAQueryMaximumTimeout, 1...4294967295
+#assoc_sa_query_max_timeout=1000
+
+# Association SA Query retry timeout (in TU = 1.024 ms; for MFP)
+# (time between two subsequent SA Query requests)
+# dot11AssociationSAQueryRetryTimeout, 1...4294967295
+#assoc_sa_query_retry_timeout=201
+
+# disable_pmksa_caching: Disable PMKSA caching
+# This parameter can be used to disable caching of PMKSA created through EAP
+# authentication. RSN preauthentication may still end up using PMKSA caching if
+# it is enabled (rsn_preauth=1).
+# 0 = PMKSA caching enabled (default)
+# 1 = PMKSA caching disabled
+#disable_pmksa_caching=0
+
+# okc: Opportunistic Key Caching (aka Proactive Key Caching)
+# Allow PMK cache to be shared opportunistically among configured interfaces
+# and BSSes (i.e., all configurations within a single hostapd process).
+# 0 = disabled (default)
+# 1 = enabled
+#okc=1
+
+
+##### IEEE 802.11r configuration ##############################################
+
+# Mobility Domain identifier (dot11FTMobilityDomainID, MDID)
+# MDID is used to indicate a group of APs (within an ESS, i.e., sharing the
+# same SSID) between which a STA can use Fast BSS Transition.
+# 2-octet identifier as a hex string.
+#mobility_domain=a1b2
+
+# PMK-R0 Key Holder identifier (dot11FTR0KeyHolderID)
+# 1 to 48 octet identifier.
+# This is configured with nas_identifier (see RADIUS client section above).
+
+# Default lifetime of the PMK-RO in minutes; range 1..65535
+# (dot11FTR0KeyLifetime)
+#r0_key_lifetime=10000
+
+# PMK-R1 Key Holder identifier (dot11FTR1KeyHolderID)
+# 6-octet identifier as a hex string.
+#r1_key_holder=000102030405
+
+# Reassociation deadline in time units (TUs / 1.024 ms; range 1000..65535)
+# (dot11FTReassociationDeadline)
+#reassociation_deadline=1000
+
+# List of R0KHs in the same Mobility Domain
+# format: <MAC address> <NAS Identifier> <128-bit key as hex string>
+# This list is used to map R0KH-ID (NAS Identifier) to a destination MAC
+# address when requesting PMK-R1 key from the R0KH that the STA used during the
+# Initial Mobility Domain Association.
+#r0kh=02:01:02:03:04:05 r0kh-1.example.com 000102030405060708090a0b0c0d0e0f
+#r0kh=02:01:02:03:04:06 r0kh-2.example.com 00112233445566778899aabbccddeeff
+# And so on.. One line per R0KH.
+
+# List of R1KHs in the same Mobility Domain
+# format: <MAC address> <R1KH-ID> <128-bit key as hex string>
+# This list is used to map R1KH-ID to a destination MAC address when sending
+# PMK-R1 key from the R0KH. This is also the list of authorized R1KHs in the MD
+# that can request PMK-R1 keys.
+#r1kh=02:01:02:03:04:05 02:11:22:33:44:55 000102030405060708090a0b0c0d0e0f
+#r1kh=02:01:02:03:04:06 02:11:22:33:44:66 00112233445566778899aabbccddeeff
+# And so on.. One line per R1KH.
+
+# Whether PMK-R1 push is enabled at R0KH
+# 0 = do not push PMK-R1 to all configured R1KHs (default)
+# 1 = push PMK-R1 to all configured R1KHs whenever a new PMK-R0 is derived
+#pmk_r1_push=1
+
+##### Neighbor table ##########################################################
+# Maximum number of entries kept in AP table (either for neigbor table or for
+# detecting Overlapping Legacy BSS Condition). The oldest entry will be
+# removed when adding a new entry that would make the list grow over this
+# limit. Note! WFA certification for IEEE 802.11g requires that OLBC is
+# enabled, so this field should not be set to 0 when using IEEE 802.11g.
+# default: 255
+#ap_table_max_size=255
+
+# Number of seconds of no frames received after which entries may be deleted
+# from the AP table. Since passive scanning is not usually performed frequently
+# this should not be set to very small value. In addition, there is no
+# guarantee that every scan cycle will receive beacon frames from the
+# neighboring APs.
+# default: 60
+#ap_table_expiration_time=3600
+
+
+##### Wi-Fi Protected Setup (WPS) #############################################
+
+# WPS state
+# 0 = WPS disabled (default)
+# 1 = WPS enabled, not configured
+# 2 = WPS enabled, configured
+#wps_state=2
+
+# AP can be configured into a locked state where new WPS Registrar are not
+# accepted, but previously authorized Registrars (including the internal one)
+# can continue to add new Enrollees.
+#ap_setup_locked=1
+
+# Universally Unique IDentifier (UUID; see RFC 4122) of the device
+# This value is used as the UUID for the internal WPS Registrar. If the AP
+# is also using UPnP, this value should be set to the device's UPnP UUID.
+# If not configured, UUID will be generated based on the local MAC address.
+#uuid=12345678-9abc-def0-1234-56789abcdef0
+
+# Note: If wpa_psk_file is set, WPS is used to generate random, per-device PSKs
+# that will be appended to the wpa_psk_file. If wpa_psk_file is not set, the
+# default PSK (wpa_psk/wpa_passphrase) will be delivered to Enrollees. Use of
+# per-device PSKs is recommended as the more secure option (i.e., make sure to
+# set wpa_psk_file when using WPS with WPA-PSK).
+
+# When an Enrollee requests access to the network with PIN method, the Enrollee
+# PIN will need to be entered for the Registrar. PIN request notifications are
+# sent to hostapd ctrl_iface monitor. In addition, they can be written to a
+# text file that could be used, e.g., to populate the AP administration UI with
+# pending PIN requests. If the following variable is set, the PIN requests will
+# be written to the configured file.
+#wps_pin_requests=/var/run/hostapd_wps_pin_requests
+
+# Device Name
+# User-friendly description of device; up to 32 octets encoded in UTF-8
+#device_name=Wireless AP
+
+# Manufacturer
+# The manufacturer of the device (up to 64 ASCII characters)
+#manufacturer=Company
+
+# Model Name
+# Model of the device (up to 32 ASCII characters)
+#model_name=WAP
+
+# Model Number
+# Additional device description (up to 32 ASCII characters)
+#model_number=123
+
+# Serial Number
+# Serial number of the device (up to 32 characters)
+#serial_number=12345
+
+# Primary Device Type
+# Used format: <categ>-<OUI>-<subcateg>
+# categ = Category as an integer value
+# OUI = OUI and type octet as a 4-octet hex-encoded value; 0050F204 for
+#       default WPS OUI
+# subcateg = OUI-specific Sub Category as an integer value
+# Examples:
+#   1-0050F204-1 (Computer / PC)
+#   1-0050F204-2 (Computer / Server)
+#   5-0050F204-1 (Storage / NAS)
+#   6-0050F204-1 (Network Infrastructure / AP)
+#device_type=6-0050F204-1
+
+# OS Version
+# 4-octet operating system version number (hex string)
+#os_version=01020300
+
+# Config Methods
+# List of the supported configuration methods
+# Available methods: usba ethernet label display ext_nfc_token int_nfc_token
+#	nfc_interface push_button keypad virtual_display physical_display
+#	virtual_push_button physical_push_button
+#config_methods=label virtual_display virtual_push_button keypad
+
+# WPS capability discovery workaround for PBC with Windows 7
+# Windows 7 uses incorrect way of figuring out AP's WPS capabilities by acting
+# as a Registrar and using M1 from the AP. The config methods attribute in that
+# message is supposed to indicate only the configuration method supported by
+# the AP in Enrollee role, i.e., to add an external Registrar. For that case,
+# PBC shall not be used and as such, the PushButton config method is removed
+# from M1 by default. If pbc_in_m1=1 is included in the configuration file,
+# the PushButton config method is left in M1 (if included in config_methods
+# parameter) to allow Windows 7 to use PBC instead of PIN (e.g., from a label
+# in the AP).
+#pbc_in_m1=1
+
+# Static access point PIN for initial configuration and adding Registrars
+# If not set, hostapd will not allow external WPS Registrars to control the
+# access point. The AP PIN can also be set at runtime with hostapd_cli
+# wps_ap_pin command. Use of temporary (enabled by user action) and random
+# AP PIN is much more secure than configuring a static AP PIN here. As such,
+# use of the ap_pin parameter is not recommended if the AP device has means for
+# displaying a random PIN.
+#ap_pin=12345670
+
+# Skip building of automatic WPS credential
+# This can be used to allow the automatically generated Credential attribute to
+# be replaced with pre-configured Credential(s).
+#skip_cred_build=1
+
+# Additional Credential attribute(s)
+# This option can be used to add pre-configured Credential attributes into M8
+# message when acting as a Registrar. If skip_cred_build=1, this data will also
+# be able to override the Credential attribute that would have otherwise been
+# automatically generated based on network configuration. This configuration
+# option points to an external file that much contain the WPS Credential
+# attribute(s) as binary data.
+#extra_cred=hostapd.cred
+
+# Credential processing
+#   0 = process received credentials internally (default)
+#   1 = do not process received credentials; just pass them over ctrl_iface to
+#	external program(s)
+#   2 = process received credentials internally and pass them over ctrl_iface
+#	to external program(s)
+# Note: With wps_cred_processing=1, skip_cred_build should be set to 1 and
+# extra_cred be used to provide the Credential data for Enrollees.
+#
+# wps_cred_processing=1 will disabled automatic updates of hostapd.conf file
+# both for Credential processing and for marking AP Setup Locked based on
+# validation failures of AP PIN. An external program is responsible on updating
+# the configuration appropriately in this case.
+#wps_cred_processing=0
+
+# AP Settings Attributes for M7
+# By default, hostapd generates the AP Settings Attributes for M7 based on the
+# current configuration. It is possible to override this by providing a file
+# with pre-configured attributes. This is similar to extra_cred file format,
+# but the AP Settings attributes are not encapsulated in a Credential
+# attribute.
+#ap_settings=hostapd.ap_settings
+
+# WPS UPnP interface
+# If set, support for external Registrars is enabled.
+#upnp_iface=br0
+
+# Friendly Name (required for UPnP)
+# Short description for end use. Should be less than 64 characters.
+#friendly_name=WPS Access Point
+
+# Manufacturer URL (optional for UPnP)
+#manufacturer_url=http://www.example.com/
+
+# Model Description (recommended for UPnP)
+# Long description for end user. Should be less than 128 characters.
+#model_description=Wireless Access Point
+
+# Model URL (optional for UPnP)
+#model_url=http://www.example.com/model/
+
+# Universal Product Code (optional for UPnP)
+# 12-digit, all-numeric code that identifies the consumer package.
+#upc=123456789012
+
+# WPS RF Bands (a = 5G, b = 2.4G, g = 2.4G, ag = dual band)
+# This value should be set according to RF band(s) supported by the AP if
+# hw_mode is not set. For dual band dual concurrent devices, this needs to be
+# set to ag to allow both RF bands to be advertized.
+#wps_rf_bands=ag
+
+# NFC password token for WPS
+# These parameters can be used to configure a fixed NFC password token for the
+# AP. This can be generated, e.g., with nfc_pw_token from wpa_supplicant. When
+# these parameters are used, the AP is assumed to be deployed with a NFC tag
+# that includes the matching NFC password token (e.g., written based on the
+# NDEF record from nfc_pw_token).
+#
+#wps_nfc_dev_pw_id: Device Password ID (16..65535)
+#wps_nfc_dh_pubkey: Hexdump of DH Public Key
+#wps_nfc_dh_privkey: Hexdump of DH Private Key
+#wps_nfc_dev_pw: Hexdump of Device Password
+
+##### Wi-Fi Direct (P2P) ######################################################
+
+# Enable P2P Device management
+#manage_p2p=1
+
+# Allow cross connection
+#allow_cross_connection=1
+
+#### TDLS (IEEE 802.11z-2010) #################################################
+
+# Prohibit use of TDLS in this BSS
+#tdls_prohibit=1
+
+# Prohibit use of TDLS Channel Switching in this BSS
+#tdls_prohibit_chan_switch=1
+
+##### IEEE 802.11v-2011 #######################################################
+
+# Time advertisement
+# 0 = disabled (default)
+# 2 = UTC time at which the TSF timer is 0
+#time_advertisement=2
+
+# Local time zone as specified in 8.3 of IEEE Std 1003.1-2004:
+# stdoffset[dst[offset][,start[/time],end[/time]]]
+#time_zone=EST5
+
+# WNM-Sleep Mode (extended sleep mode for stations)
+# 0 = disabled (default)
+# 1 = enabled (allow stations to use WNM-Sleep Mode)
+#wnm_sleep_mode=1
+
+# BSS Transition Management
+# 0 = disabled (default)
+# 1 = enabled
+#bss_transition=1
+
+##### IEEE 802.11u-2011 #######################################################
+
+# Enable Interworking service
+#interworking=1
+
+# Access Network Type
+# 0 = Private network
+# 1 = Private network with guest access
+# 2 = Chargeable public network
+# 3 = Free public network
+# 4 = Personal device network
+# 5 = Emergency services only network
+# 14 = Test or experimental
+# 15 = Wildcard
+#access_network_type=0
+
+# Whether the network provides connectivity to the Internet
+# 0 = Unspecified
+# 1 = Network provides connectivity to the Internet
+#internet=1
+
+# Additional Step Required for Access
+# Note: This is only used with open network, i.e., ASRA shall ne set to 0 if
+# RSN is used.
+#asra=0
+
+# Emergency services reachable
+#esr=0
+
+# Unauthenticated emergency service accessible
+#uesa=0
+
+# Venue Info (optional)
+# The available values are defined in IEEE Std 802.11u-2011, 7.3.1.34.
+# Example values (group,type):
+# 0,0 = Unspecified
+# 1,7 = Convention Center
+# 1,13 = Coffee Shop
+# 2,0 = Unspecified Business
+# 7,1  Private Residence
+#venue_group=7
+#venue_type=1
+
+# Homogeneous ESS identifier (optional; dot11HESSID)
+# If set, this shall be identifical to one of the BSSIDs in the homogeneous
+# ESS and this shall be set to the same value across all BSSs in homogeneous
+# ESS.
+#hessid=02:03:04:05:06:07
+
+# Roaming Consortium List
+# Arbitrary number of Roaming Consortium OIs can be configured with each line
+# adding a new OI to the list. The first three entries are available through
+# Beacon and Probe Response frames. Any additional entry will be available only
+# through ANQP queries. Each OI is between 3 and 15 octets and is configured as
+# a hexstring.
+#roaming_consortium=021122
+#roaming_consortium=2233445566
+
+# Venue Name information
+# This parameter can be used to configure one or more Venue Name Duples for
+# Venue Name ANQP information. Each entry has a two or three character language
+# code (ISO-639) separated by colon from the venue name string.
+# Note that venue_group and venue_type have to be set for Venue Name
+# information to be complete.
+#venue_name=eng:Example venue
+#venue_name=fin:Esimerkkipaikka
+
+# Network Authentication Type
+# This parameter indicates what type of network authentication is used in the
+# network.
+# format: <network auth type indicator (1-octet hex str)> [redirect URL]
+# Network Authentication Type Indicator values:
+# 00 = Acceptance of terms and conditions
+# 01 = On-line enrollment supported
+# 02 = http/https redirection
+# 03 = DNS redirection
+#network_auth_type=00
+#network_auth_type=02http://www.example.com/redirect/me/here/
+
+# IP Address Type Availability
+# format: <1-octet encoded value as hex str>
+# (ipv4_type & 0x3f) << 2 | (ipv6_type & 0x3)
+# ipv4_type:
+# 0 = Address type not available
+# 1 = Public IPv4 address available
+# 2 = Port-restricted IPv4 address available
+# 3 = Single NATed private IPv4 address available
+# 4 = Double NATed private IPv4 address available
+# 5 = Port-restricted IPv4 address and single NATed IPv4 address available
+# 6 = Port-restricted IPv4 address and double NATed IPv4 address available
+# 7 = Availability of the address type is not known
+# ipv6_type:
+# 0 = Address type not available
+# 1 = Address type available
+# 2 = Availability of the address type not known
+#ipaddr_type_availability=14
+
+# Domain Name
+# format: <variable-octet str>[,<variable-octet str>]
+#domain_name=example.com,another.example.com,yet-another.example.com
+
+# 3GPP Cellular Network information
+# format: <MCC1,MNC1>[;<MCC2,MNC2>][;...]
+#anqp_3gpp_cell_net=244,91;310,026;234,56
+
+# NAI Realm information
+# One or more realm can be advertised. Each nai_realm line adds a new realm to
+# the set. These parameters provide information for stations using Interworking
+# network selection to allow automatic connection to a network based on
+# credentials.
+# format: <encoding>,<NAI Realm(s)>[,<EAP Method 1>][,<EAP Method 2>][,...]
+# encoding:
+#	0 = Realm formatted in accordance with IETF RFC 4282
+#	1 = UTF-8 formatted character string that is not formatted in
+#	    accordance with IETF RFC 4282
+# NAI Realm(s): Semi-colon delimited NAI Realm(s)
+# EAP Method: <EAP Method>[:<[AuthParam1:Val1]>][<[AuthParam2:Val2]>][...]
+# AuthParam (Table 8-188 in IEEE Std 802.11-2012):
+# ID 2 = Non-EAP Inner Authentication Type
+#	1 = PAP, 2 = CHAP, 3 = MSCHAP, 4 = MSCHAPV2
+# ID 3 = Inner authentication EAP Method Type
+# ID 5 = Credential Type
+#	1 = SIM, 2 = USIM, 3 = NFC Secure Element, 4 = Hardware Token,
+#	5 = Softoken, 6 = Certificate, 7 = username/password, 9 = Anonymous,
+#	10 = Vendor Specific
+#nai_realm=0,example.com;example.net
+# EAP methods EAP-TLS with certificate and EAP-TTLS/MSCHAPv2 with
+# username/password
+#nai_realm=0,example.org,13[5:6],21[2:4][5:7]
+
+##### Hotspot 2.0 #############################################################
+
+# Enable Hotspot 2.0 support
+#hs20=1
+
+# Disable Downstream Group-Addressed Forwarding (DGAF)
+# This can be used to configure a network where no group-addressed frames are
+# allowed. The AP will not forward any group-address frames to the stations and
+# random GTKs are issued for each station to prevent associated stations from
+# forging such frames to other stations in the BSS.
+#disable_dgaf=1
+
+# Operator Friendly Name
+# This parameter can be used to configure one or more Operator Friendly Name
+# Duples. Each entry has a two or three character language code (ISO-639)
+# separated by colon from the operator friendly name string.
+#hs20_oper_friendly_name=eng:Example operator
+#hs20_oper_friendly_name=fin:Esimerkkioperaattori
+
+# Connection Capability
+# This can be used to advertise what type of IP traffic can be sent through the
+# hotspot (e.g., due to firewall allowing/blocking protocols/ports).
+# format: <IP Protocol>:<Port Number>:<Status>
+# IP Protocol: 1 = ICMP, 6 = TCP, 17 = UDP
+# Port Number: 0..65535
+# Status: 0 = Closed, 1 = Open, 2 = Unknown
+# Each hs20_conn_capab line is added to the list of advertised tuples.
+#hs20_conn_capab=1:0:2
+#hs20_conn_capab=6:22:1
+#hs20_conn_capab=17:5060:0
+
+# WAN Metrics
+# format: <WAN Info>:<DL Speed>:<UL Speed>:<DL Load>:<UL Load>:<LMD>
+# WAN Info: B0-B1: Link Status, B2: Symmetric Link, B3: At Capabity
+#    (encoded as two hex digits)
+#    Link Status: 1 = Link up, 2 = Link down, 3 = Link in test state
+# Downlink Speed: Estimate of WAN backhaul link current downlink speed in kbps;
+#	1..4294967295; 0 = unknown
+# Uplink Speed: Estimate of WAN backhaul link current uplink speed in kbps
+#	1..4294967295; 0 = unknown
+# Downlink Load: Current load of downlink WAN connection (scaled to 255 = 100%)
+# Uplink Load: Current load of uplink WAN connection (scaled to 255 = 100%)
+# Load Measurement Duration: Duration for measuring downlink/uplink load in
+# tenths of a second (1..65535); 0 if load cannot be determined
+#hs20_wan_metrics=01:8000:1000:80:240:3000
+
+# Operating Class Indication
+# List of operating classes the BSSes in this ESS use. The Global operating
+# classes in Table E-4 of IEEE Std 802.11-2012 Annex E define the values that
+# can be used in this.
+# format: hexdump of operating class octets
+# for example, operating classes 81 (2.4 GHz channels 1-13) and 115 (5 GHz
+# channels 36-48):
+#hs20_operating_class=5173
+
+##### Multiple BSSID support ##################################################
+#
+# Above configuration is using the default interface (wlan#, or multi-SSID VLAN
+# interfaces). Other BSSIDs can be added by using separator 'bss' with
+# default interface name to be allocated for the data packets of the new BSS.
+#
+# hostapd will generate BSSID mask based on the BSSIDs that are
+# configured. hostapd will verify that dev_addr & MASK == dev_addr. If this is
+# not the case, the MAC address of the radio must be changed before starting
+# hostapd (ifconfig wlan0 hw ether <MAC addr>). If a BSSID is configured for
+# every secondary BSS, this limitation is not applied at hostapd and other
+# masks may be used if the driver supports them (e.g., swap the locally
+# administered bit)
+#
+# BSSIDs are assigned in order to each BSS, unless an explicit BSSID is
+# specified using the 'bssid' parameter.
+# If an explicit BSSID is specified, it must be chosen such that it:
+# - results in a valid MASK that covers it and the dev_addr
+# - is not the same as the MAC address of the radio
+# - is not the same as any other explicitly specified BSSID
+#
+# Please note that hostapd uses some of the values configured for the first BSS
+# as the defaults for the following BSSes. However, it is recommended that all
+# BSSes include explicit configuration of all relevant configuration items.
+#
+#bss=wlan0_0
+#ssid=test2
+# most of the above items can be used here (apart from radio interface specific
+# items, like channel)
+
+#bss=wlan0_1
+#bssid=00:13:10:95:fe:0b
+# ...
+
diff --git a/drivers/net/wireless/ssv6x5x/script/template/load_dhcp.sh b/drivers/net/wireless/ssv6x5x/script/template/load_dhcp.sh
new file mode 100755
index 000000000..6eebc5f75
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/template/load_dhcp.sh
@@ -0,0 +1,40 @@
+#/bin/bash
+BLUE='\e[1;34m'
+GREEN='\e[1;32m'
+CYAN='\e[1;36m'
+RED='\e[1;31m'
+PURPLE='\e[1;35m'
+YELLOW='\e[1;33m'
+# No Color
+NC='\e[0m'
+
+echo -e "${YELLOW}Load DHCP...${NC}"
+echo -e "${YELLOW}Check DHCP Config...${NC}"
+dhcp_config_file="/etc/dhcp/dhcpd.conf"
+dhcp_domain="subnet 192.168.0.0 netmask 255.255.255.0"
+dhcp_config=$(grep "subnet 192.168.0.0 netmask 255.255.255.0" $dhcp_config_file)
+if [ "$dhcp_config" != "$dhcp_domain" ]; then
+	echo -en "${YELLOW}Config $dhcp_config_file.....${NC}"
+	echo "subnet 192.168.0.0 netmask 255.255.255.0" >> $dhcp_config_file
+	echo "{" >> $dhcp_config_file
+	echo "  range 192.168.0.2 192.168.0.10;" >> $dhcp_config_file
+	echo "  option routers 192.168.0.1;" >> $dhcp_config_file
+	echo "  option domain-name-servers 168.95.1.1;" >> $dhcp_config_file
+	echo "}" >> $dhcp_config_file
+
+	echo -e "${YELLOW}OK${NC}"
+else
+	echo -e "${YELLOW}192.168.0.x domain is existed${NC}"
+fi
+
+echo -e "${GREEN}Config IP.${NC}"
+ifconfig wlan@@ up
+ifconfig wlan@@ 192.168.0.1 netmask 255.255.255.0
+
+echo -e "${GREEN}Config DHCP Server.${NC}"
+service isc-dhcp-server start
+sleep 3
+
+echo -e "${GREEN}Config routing table.${NC}"
+bash -c "echo 1 >/proc/sys/net/ipv4/ip_forward"
+iptables -t nat -A POSTROUTING -o eth0 -j MASQUERADE
diff --git a/drivers/net/wireless/ssv6x5x/script/unload.sh b/drivers/net/wireless/ssv6x5x/script/unload.sh
new file mode 100755
index 000000000..f10e6b986
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/unload.sh
@@ -0,0 +1,4 @@
+#/bin/bash
+#if you want to modify unload process ,please modify  ../unload.sh, Do not change the file.
+../unload.sh
+
diff --git a/drivers/net/wireless/ssv6x5x/script/unload_ap.sh b/drivers/net/wireless/ssv6x5x/script/unload_ap.sh
new file mode 100755
index 000000000..1b975d0e9
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/unload_ap.sh
@@ -0,0 +1,8 @@
+#/bin/bash
+
+hostapd_pid=`pgrep hostapd`
+[ $? -eq 0 ] && (echo "\nKilling hostapd..."; kill -KILL $hostapd_pid)
+
+dhcpd_pid=`pgrep dhcpd`
+[ $? -eq 0 ] && (echo "\nKilling dhcpd..."; kill -KILL $dhcpd_pid)
+
diff --git a/drivers/net/wireless/ssv6x5x/script/unload_dhcp.sh b/drivers/net/wireless/ssv6x5x/script/unload_dhcp.sh
new file mode 100755
index 000000000..5616fb50b
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/unload_dhcp.sh
@@ -0,0 +1,4 @@
+#/bin/bash
+
+killall dhcpd
+#ps aux|grep dhcpd
diff --git a/drivers/net/wireless/ssv6x5x/script/wpa-cli-action.sh b/drivers/net/wireless/ssv6x5x/script/wpa-cli-action.sh
new file mode 100755
index 000000000..dddf0b9fa
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/wpa-cli-action.sh
@@ -0,0 +1 @@
+wpa_cli -i wlan2 -a p2p-action.sh
diff --git a/drivers/net/wireless/ssv6x5x/script/wpa.conf.template b/drivers/net/wireless/ssv6x5x/script/wpa.conf.template
new file mode 100755
index 000000000..58b1422e6
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/script/wpa.conf.template
@@ -0,0 +1,13 @@
+ctrl_interface=/var/run/wpa_supplicant
+ap_scan=1
+fast_reauth=1
+uuid=12345678-9abc-def0-1234-56789abcde11
+device_name=X86-Platform
+manufacturer=iComm Corporation
+model_name=Wi-Fi reference chip
+model_number=123
+serial_number=MAC_ADDR
+device_type=1-0050F204-1
+os_version=01020300
+config_methods=display push_button virtual_display virtual_push_button
+
diff --git a/drivers/net/wireless/ssv6x5x/smac-release.sh b/drivers/net/wireless/ssv6x5x/smac-release.sh
new file mode 100755
index 000000000..e6209c7ca
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac-release.sh
@@ -0,0 +1,131 @@
+#!/bin/bash
+release_options=("From wifi [trunk] -> [regular-tag]" \
+              "From wifi [trunk] -> [smac-release-tag]" \
+              "From wifi [regular-tag] -> [smac-release-tag] -> [QA_tags]" \
+              "From wifi [smac-release-tag] -> [QA_tags]" \
+              "From wifi [QA_tags] -> [software-mac]")
+
+
+echo ""
+echo "smac-release [Target Version tag] [JIRA ID] [Regular Version]"
+echo ""
+
+rm -rf $1
+rm -rf $3 
+
+select opt in "${release_options[@]}" "Quit"; do 
+    case "$REPLY" in
+
+    1 ) echo "${release_options[$REPLY-1]} is option";
+        if [ "$1" != "" ]; then
+        if [ "$3" != "" ]; then
+        rm -rf $1
+        rm -rf $3
+        svn copy http://192.168.15.30/svn/software/wifi/trunk/CABRIO-E/host_drivers/Linux \
+            http://192.168.15.30/svn/software/wifi/tag/regular-tag/$3 -m "release $3"
+        svn co http://192.168.15.30/svn/software/wifi/tag/regular-tag/$3
+        cd $3/ssv6x5x
+        ./gen-version.sh
+        svn commit * -m "$2 release $3"
+        else
+        echo "No WSD-XX or NO WSP-XX parameter"
+        fi
+        echo "Done!"
+        else
+        echo "No verion parameter!"
+        fi
+        break;;
+    2 ) echo "${release_options[$REPLY-1]} is option";
+        if [ "$1" != "" ]; then
+        if [ "$2" != "" ]; then
+        rm -rf $1
+        svn copy http://192.168.15.30/svn/software/wifi/trunk/CABRIO-E/host_drivers/Linux \
+            http://192.168.15.30/svn/software/wifi/tag/smac-release-tag/$1 -m "release $1"
+        svn co http://192.168.15.30/svn/software/wifi/tag/smac-release-tag/$1
+        cd $1/ssv6x5x
+        ./gen-version.sh
+        svn commit * -m "$2 release $1"
+        else
+        echo "No WSD-XX or NO WSP-XX parameter"
+        fi
+        echo "Done!"
+        else
+        echo "No verion parameter!"
+        fi
+        break;;
+    3 ) echo "${release_options[$REPLY-1]} is option";
+        if [ "$1" != "" ]; then
+        if [ "$3" != "" ]; then
+        rm -rf $1
+        rm -rf $3
+        svn copy http://192.168.15.30/svn/software/wifi/tag/regular-tag/$3 \
+            http://192.168.15.30/svn/software/wifi/tag/smac-release-tag/$1 -m "release $1"
+        svn co http://192.168.15.30/svn/software/wifi/tag/smac-release-tag/$1
+        cd $1/ssv6x5x
+        ./gen-version.sh
+        script/release
+        cd ../..
+        svn import $1 http://192.168.15.30/svn/software/QA_tags/Ubuntu-PC/$1 -m "$2 release $1"
+        rm -rf $1
+        svn co http://192.168.15.30/svn/software/QA_tags/Ubuntu-PC/$1
+        cd $1/ssv6x5x
+        ./gen-version.sh
+        svn commit * -m "$2 release $1"
+        else
+        echo "No WSD-XX or NO WSP-XX parameter"
+        fi
+        echo "Done!"
+        else
+        echo "No verion parameter!"
+        fi
+        break;;
+    4 ) echo "${release_options[$REPLY-1]} is option";
+        if [ "$1" != "" ]; then
+        if [ "$2" != "" ]; then
+        rm -rf $1
+        svn co http://192.168.15.30/svn/software/wifi/tag/smac-release-tag/$1
+        cd $1/ssv6x5x
+        script/release
+        cd ../..
+        svn import $1 http://192.168.15.30/svn/software/QA_tags/Ubuntu-PC/$1 -m "$2 release $1"
+        rm -rf $1
+        svn co http://192.168.15.30/svn/software/QA_tags/Ubuntu-PC/$1
+        cd $1/ssv6x5x
+        ./gen-version.sh
+        svn commit * -m "$2 release $1"        
+        else
+        echo "No WSD-XX or NO WSP-XX parameter"
+        fi
+        echo "Done!"
+        else
+        echo "No verion parameter!"
+        fi
+        break;;
+    5 ) echo "${release_options[$REPLY-1]} is option";
+        if [ "$1" != "" ]; then
+        if [ "$2" != "" ]; then
+        rm -rf $1
+        svn co http://192.168.15.30/svn/software/QA_tags/Ubuntu-PC/$1
+        cd $1
+        rm -rf hostapd
+        cd ..
+        svn import $1 http://192.168.15.30/svn/software/project/release/software-mac/$1 -m "$2 release $1"
+        rm -rf $1
+        svn co http://192.168.15.30/svn/software/project/release/software-mac/$1
+        cd $1/ssv6x5x
+        ./gen-version.sh
+        svn commit * -m "$2 release $1"
+        else
+        echo "No WSD-XX or NO WSP-XX parameter"
+        fi
+        echo "Done!"
+        else
+        echo "No verion parameter!"
+        fi
+        break;;
+
+    $(( ${#release_options[@]}+1 )) ) echo "Goodbye!"; break;;
+    *) echo "Invalid option. Try another one.";continue;;
+    esac
+done
+
diff --git a/drivers/net/wireless/ssv6x5x/smac/Makefile b/drivers/net/wireless/ssv6x5x/smac/Makefile
new file mode 100755
index 000000000..23e2e520a
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/Makefile
@@ -0,0 +1,76 @@
+ifeq ($(KBUILD_TOP),)
+    ifneq ($(KBUILD_EXTMOD),)
+    KBUILD_DIR := $(KBUILD_EXTMOD)
+    else
+    KBUILD_DIR := $(PWD)
+    endif
+KBUILD_TOP := $(KBUILD_DIR)/../
+endif
+
+include $(KBUILD_TOP)/config.mak
+
+
+KBUILD_EXTRA_SYMBOLS += $(KBUILD_TOP)/ssvdevice/Module.symvers
+KBUILD_EXTRA_SYMBOLS += $(KBUILD_TOP)/hci/Module.symvers
+
+KMODULE_NAME=ssv6200s_core
+KERN_SRCS := init.c
+KERN_SRCS += dev.c
+
+KERN_SRCS += ssv_rc_minstrel.c
+KERN_SRCS += ssv_rc_minstrel_ht.c
+KERN_SRCS += lib.c
+KERN_SRCS += ap.c
+KERN_SRCS += ampdu.c
+
+ifeq ($(findstring -DCONFIG_SSV6XXX_DEBUGFS, $(ccflags-y)), -DCONFIG_SSV6XXX_DEBUGFS)
+KERN_SRCS += ssv6xxx_debugfs.c
+endif
+
+ifeq ($(findstring -DUSE_LOCAL_CRYPTO, $(ccflags-y)), -DUSE_LOCAL_CRYPTO)
+KERN_SRCS += sec_ccmp.c
+KERN_SRCS += sec_tkip.c
+KERN_SRCS += sec_wep.c
+KERN_SRCS += wapi_sms4.c
+KERN_SRCS += sec_wpi.c
+endif
+
+KERN_SRCS += efuse.c
+KERN_SRCS += p2p.c
+KERN_SRCS += ssv_skb.c
+ifeq ($(findstring -DCONFIG_SMARTLINK, $(ccflags-y)), -DCONFIG_SMARTLINK)
+KERN_SRCS += ksmartlink.c
+ifeq ($(findstring -DCONFIG_SSV_SMARTLINK, $(ccflags-y)), -DCONFIG_SSV_SMARTLINK)
+KERN_SRCS += kssvsmart.c
+endif
+endif
+
+ifeq ($(findstring -DSSV_SUPPORT_HAL, $(ccflags-y)), -DSSV_SUPPORT_HAL)
+KERN_SRCS += hal/hal.c
+ifeq ($(findstring -DSSV_SUPPORT_SSV6051, $(ccflags-y)), -DSSV_SUPPORT_SSV6051)
+KERN_SRCS += ssv_rc.c
+KERN_SRCS += ssv_ht_rc.c
+KERN_SRCS += hal/ssv6051/ssv6051_mac.c
+KERN_SRCS += hal/ssv6051/ssv6051_phy.c
+KERN_SRCS += hal/ssv6051/ssv6051_cabrioA.c
+KERN_SRCS += hal/ssv6051/ssv6051_cabrioE.c
+endif
+ifeq ($(findstring -DSSV_SUPPORT_SSV6006, $(ccflags-y)), -DSSV_SUPPORT_SSV6006)
+KERN_SRCS += hal/ssv6006c/ssv6006_common.c
+KERN_SRCS += hal/ssv6006c/ssv6006C_mac.c
+KERN_SRCS += hal/ssv6006c/ssv6006_phy.c
+KERN_SRCS += hal/ssv6006c/ssv6006_turismoC.c
+ifeq ($(findstring -DSSV_SUPPORT_SSV6006AB, $(ccflags-y)), -DSSV_SUPPORT_SSV6006AB)
+KERN_SRCS += hal/ssv6006/ssv6006_mac.c
+KERN_SRCS += hal/ssv6006/ssv6006_cabrioA.c
+KERN_SRCS += hal/ssv6006/ssv6006_geminiA.c
+KERN_SRCS += hal/ssv6006/ssv6006_turismoA.c
+KERN_SRCS += hal/ssv6006/ssv6006_turismoB.c
+endif
+endif
+else
+KERN_SRCS += ssv_rc.c
+KERN_SRCS += ssv_ht_rc.c
+endif
+
+include $(KBUILD_TOP)/rules.mak
diff --git a/drivers/net/wireless/ssv6x5x/smac/ampdu.c b/drivers/net/wireless/ssv6x5x/smac/ampdu.c
new file mode 100644
index 000000000..a3bfedae6
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/ampdu.c
@@ -0,0 +1,2518 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/version.h>
+#include <ssv6200.h>
+#include "dev.h"
+#include "ap.h"
+#include "sec.h"
+#include "ssv_rc_common.h"
+#include "ssv_ht_rc.h"
+#include "ssv_skb.h"
+#include <hal.h>
+extern struct ieee80211_ops ssv6200_ops;
+#define BA_WAIT_TIMEOUT (100)
+#define AMPDU_TID_TO_SC(ampdu_tid) \
+    ({ \
+    struct AMPDU_TID_st *_ampdu_tid = (ampdu_tid); \
+    struct ieee80211_sta *sta = _ampdu_tid->sta; \
+    struct ssv_sta_priv_data *ssv_sta_priv = (struct ssv_sta_priv_data *) sta->drv_priv; \
+    const struct ssv_sta_info (*sta_info)[] = (const struct ssv_sta_info (*)[])(ssv_sta_priv->sta_info - ssv_sta_priv->sta_idx); \
+    struct ssv_softc *sc = container_of(sta_info, struct ssv_softc, sta_info); \
+    sc; \
+    })
+#define get_tid_aggr_len(agg_len,tid_data) \
+    ({ \
+        u32 agg_max_num = (tid_data)->agg_num_max; \
+        u32 to_agg_len = (agg_len); \
+        (agg_len >= agg_max_num) ? agg_max_num : to_agg_len; \
+    })
+#define NEXT_PKT_SN(sn) \
+    ({ (sn + 1) % SSV_AMPDU_MAX_SSN; })
+#define INC_PKT_SN(sn) \
+    ({ \
+        sn = NEXT_PKT_SN(sn); \
+        sn; \
+    })
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+static ssize_t ampdu_tx_mib_dump (struct ssv_sta_priv_data *ssv_sta_priv,
+                                  char *mib_str, ssize_t length);
+static int _dump_ba_skb (struct ssv_softc *sc, char *buf, int buf_size, struct sk_buff *ba_skb);
+#endif
+static struct sk_buff* _aggr_retry_mpdu (struct ssv_softc *sc,
+        struct AMPDU_TID_st *cur_AMPDU_TID,
+        struct sk_buff_head *retry_queue,
+        u32 max_aggr_len);
+int ssv6200_dump_BA_notification (char *buf,
+                                  struct ampdu_ba_notify_data *ba_notification);
+static struct sk_buff *_alloc_ampdu_skb (struct ssv_softc *sc,
+        struct AMPDU_TID_st *ampdu_tid,
+        u32 len);
+static bool _sync_ampdu_pkt_arr (struct ssv_softc *sc, struct AMPDU_TID_st *ampdu_tid,
+                                 struct sk_buff *ampdu_skb, bool retry);
+static int _acquire_new_ampdu_ssn_slot(struct ssv_softc *sc, struct sk_buff *ampdu);
+static void _put_mpdu_to_ampdu (struct ssv_softc *sc, struct sk_buff *ampdu,
+                                struct sk_buff *mpdu);
+static u32 _flush_early_ampdu_q (struct ssv_softc *sc,
+                                 struct AMPDU_TID_st *ampdu_tid);
+static bool _is_skb_q_empty (struct ssv_softc *sc, struct sk_buff *skb);
+static void _aggr_ampdu_tx_q (struct ieee80211_hw *hw,
+                              struct AMPDU_TID_st *ampdu_tid);
+static void _queue_early_ampdu (struct ssv_softc *sc,
+                                struct AMPDU_TID_st *ampdu_tid,
+                                struct sk_buff *ampdu_skb);
+void ssv6xxx_mark_skb_retry (struct ssv_softc *sc, struct SKB_info_st *skb_info,
+                             struct sk_buff *skb);
+static void _print_BA(struct AMPDU_TID_st *ampdu_tid);
+#ifdef CONFIG_DEBUG_SKB_TIMESTAMP
+unsigned int cal_duration_of_ampdu(struct sk_buff *ampdu_skb, int stage)
+{
+    unsigned int timeout;
+    SKB_info *mpdu_skb_info;
+    u16 ssn = 0;
+    struct sk_buff *mpdu = NULL;
+    struct ampdu_hdr_st *ampdu_hdr = NULL;
+    ktime_t current_ktime;
+    ampdu_hdr = (struct ampdu_hdr_st *) ampdu_skb->head;
+    ssn = ampdu_hdr->ssn[0];
+    mpdu = INDEX_PKT_BY_SSN(ampdu_hdr->ampdu_tid, ssn);
+    if (mpdu == NULL)
+        return 0;
+    mpdu_skb_info = (SKB_info *) (mpdu->head);
+    current_ktime = ktime_get();
+    timeout = (unsigned int)ktime_to_ms(ktime_sub(current_ktime, mpdu_skb_info->timestamp));
+    if (timeout > SKB_DURATION_TIMEOUT_MS) {
+        if (stage == SKB_DURATION_STAGE_TO_SDIO)
+            printk("*a_to_sdio: %ums\n", timeout);
+        else if (stage == SKB_DURATION_STAGE_TX_ENQ)
+            printk("*a_to_txenqueue: %ums\n", timeout);
+        else
+            printk("*a_in_hwq: %ums\n", timeout);
+    }
+    return timeout;
+}
+#endif
+static u8 _cal_ampdu_delm_half_crc (u8 value)
+{
+    u32 c32 = value, v32 = value;
+    c32 ^= (v32 >> 1) | (v32 << 7);
+    c32 ^= (v32 >> 2);
+    if (v32 & 2)
+        c32 ^= (0xC0);
+    c32 ^= ((v32 << 4) & 0x30);
+    return (u8) c32;
+}
+static u8 _cal_ampdu_delm_crc (u8 *pointer)
+{
+    u8 crc = 0xCF;
+    crc ^= _cal_ampdu_delm_half_crc(*pointer++);
+    crc = _cal_ampdu_delm_half_crc(crc) ^ _cal_ampdu_delm_half_crc(*pointer);
+    return ~crc;
+}
+static bool ssv6200_ampdu_add_delimiter_and_crc32 (struct sk_buff *mpdu)
+{
+    p_AMPDU_DELIMITER delimiter_p;
+    struct ieee80211_hdr *mpdu_hdr;
+    int ret;
+    u32 orig_mpdu_len = mpdu->len;
+    u32 pad = (4 - (orig_mpdu_len % 4)) % 4;
+    struct ieee80211_tx_info *info = IEEE80211_SKB_CB(mpdu);
+    struct ssv_vif_priv_data *vif_priv = (struct ssv_vif_priv_data *)info->control.vif->drv_priv;
+    mpdu_hdr = (struct ieee80211_hdr*) (mpdu->data);
+    mpdu_hdr->duration_id = AMPDU_TX_NAV_MCS_567;
+    ret = skb_padto(mpdu, mpdu->len + (AMPDU_FCS_LEN + pad));
+    if (ret) {
+        printk(KERN_ERR "Failed to extand skb for aggregation.");
+        return false;
+    }
+    skb_put(mpdu, AMPDU_FCS_LEN + pad);
+    skb_push(mpdu, AMPDU_DELIMITER_LEN);
+    delimiter_p = (p_AMPDU_DELIMITER) mpdu->data;
+    delimiter_p->reserved = 0;
+    delimiter_p->length = orig_mpdu_len + AMPDU_FCS_LEN;
+    if (vif_priv->pair_cipher == SSV_CIPHER_CCMP) {
+        delimiter_p->length += CCMP_MIC_LEN;
+    }
+    delimiter_p->signature = AMPDU_SIGNATURE;
+    delimiter_p->crc = _cal_ampdu_delm_crc((u8*) (delimiter_p));
+    return true;
+}
+const u16 ampdu_max_transmit_length[RATE_TABLE_SIZE] = {
+    0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0,
+    4429, 8860, 13291, 17723, 26586, 35448, 39880, 44311,
+    4921, 9844, 14768, 19692, 29539, 39387, 44311, 49234,
+    4429, 8860, 13291, 17723, 26586, 35448, 39880, 44311
+};
+int ssv6200_get_ampdu_max_transmit_length(int rate_idx)
+{
+    return ampdu_max_transmit_length[rate_idx];
+}
+static void ssv6200_ampdu_hw_init (struct ieee80211_hw *hw)
+{
+    struct ssv_softc *sc = hw->priv;
+    SSV_AMPDU_AUTO_CRC_EN(sc->sh);
+}
+bool _sync_ampdu_pkt_arr (struct ssv_softc *sc, struct AMPDU_TID_st *ampdu_tid
+                          , struct sk_buff *ampdu, bool retry)
+{
+    struct sk_buff **pp_aggr_pkt;
+    struct sk_buff *p_aggr_pkt;
+    unsigned long flags;
+    struct ampdu_hdr_st *ampdu_hdr = (struct ampdu_hdr_st *) ampdu->head;
+    struct sk_buff *mpdu;
+    u32 first_ssn = SSV_ILLEGAL_SN;
+    u32 old_aggr_pkt_num;
+    u32 old_baw_head;
+    u32 sync_num = skb_queue_len(&ampdu_hdr->mpdu_q);
+    bool ret = true;
+    spin_lock_irqsave(&ampdu_tid->pkt_array_lock, flags);
+    old_baw_head = ampdu_tid->ssv_baw_head;
+    old_aggr_pkt_num = ampdu_tid->aggr_pkt_num;
+    ampdu_tid->mib.ampdu_mib_ampdu_counter += 1;
+    ampdu_tid->mib.ampdu_mib_dist[sync_num] += 1;
+    do {
+        if (!retry) {
+            skb_queue_walk(&ampdu_hdr->mpdu_q, mpdu) {
+                if (mpdu == NULL) {
+                    ret = false;
+                    goto NoBAWin;
+                } else {
+                    u32 ssn = ampdu_skb_ssn(mpdu);
+                    if ((ampdu_tid->ssv_baw_head + SSV_AMPDU_BA_WINDOW_SIZE) < ssn)
+                        goto NoBAWin;
+                    p_aggr_pkt = INDEX_PKT_BY_SSN(ampdu_tid, ssn);
+                    if (p_aggr_pkt != NULL) {
+                        char msg[256];
+                        u32 sn = ampdu_skb_ssn(mpdu);
+                        struct ssv_softc *sc = AMPDU_TID_TO_SC(ampdu_tid);
+                        skb_queue_walk(&ampdu_hdr->mpdu_q, mpdu) {
+                            sn = ampdu_skb_ssn(mpdu);
+                            sprintf(msg, " %d", sn);
+                        }
+                        prn_aggr_err(sc, "ES %d -> %d (%s)\n",
+                                     ssn, ampdu_skb_ssn(p_aggr_pkt), msg);
+                        ret = false;
+                        goto NoBAWin;
+                    }
+                }
+            }
+            ampdu_tid->mib.ampdu_mib_mpdu_counter += sync_num;
+        } else
+            ampdu_tid->mib.ampdu_mib_aggr_retry_counter += 1;
+        skb_queue_walk(&ampdu_hdr->mpdu_q, mpdu) {
+            u32 ssn = ampdu_skb_ssn(mpdu);
+            SKB_info *mpdu_skb_info = (SKB_info *) (mpdu->head);
+            if (first_ssn == SSV_ILLEGAL_SN)
+                first_ssn = ssn;
+            pp_aggr_pkt = &INDEX_PKT_BY_SSN(ampdu_tid, ssn);
+            p_aggr_pkt = *pp_aggr_pkt;
+            *pp_aggr_pkt = mpdu;
+            if (!retry)
+                ampdu_tid->aggr_pkt_num++;
+            mpdu_skb_info->ampdu_tx_status = AMPDU_ST_AGGREGATED;
+            if (ampdu_tid->ssv_baw_head == SSV_ILLEGAL_SN) {
+                ampdu_tid->ssv_baw_head = ssn;
+            }
+            if ((p_aggr_pkt != NULL) && (mpdu != p_aggr_pkt)) {
+                prn_aggr_err(AMPDU_TID_TO_SC(ampdu_tid),
+                             "%d -> %d (H%d, N%d, Q%d)\n",
+                             ssn, ampdu_skb_ssn(p_aggr_pkt), old_baw_head, old_aggr_pkt_num, sync_num);
+            }
+        }
+    } while (0);
+NoBAWin:
+    spin_unlock_irqrestore(&ampdu_tid->pkt_array_lock, flags);
+#if 1
+    {
+        u32 page_count = (ampdu->len + SSV6200_ALLOC_RSVD);
+        if (page_count & HW_MMU_PAGE_MASK)
+            page_count = (page_count >> HW_MMU_PAGE_SHIFT) + 1;
+        else page_count = page_count >> HW_MMU_PAGE_SHIFT;
+        if (page_count > (sc->sh->tx_info.tx_page_threshold / 2))
+            printk(KERN_ERR "AMPDU requires pages %d(%d-%d-%d) exceeds resource limit %d.\n",
+                   page_count, ampdu->len, ampdu_hdr->max_size, ampdu_hdr->size,
+                   (sc->sh->tx_info.tx_page_threshold / 2));
+    }
+#endif
+    return ret;
+}
+struct sk_buff* _aggr_retry_mpdu (struct ssv_softc *sc,
+                                  struct AMPDU_TID_st *ampdu_tid,
+                                  struct sk_buff_head *retry_queue,
+                                  u32 max_aggr_len)
+{
+    struct sk_buff *retry_mpdu;
+    struct sk_buff *new_ampdu_skb;
+    u32 num_retry_mpdu;
+    u32 temp_i;
+    u32 total_skb_size;
+    unsigned long flags;
+    struct ampdu_hdr_st *ampdu_hdr;
+    u16 head_ssn = ampdu_tid->ssv_baw_head;
+    struct ieee80211_tx_info *info;
+    struct ssv_vif_priv_data *vif_priv;
+#if 0
+    if (cur_AMPDU_TID->ssv_baw_head == SSV_ILLEGAL_SN) {
+        struct sk_buff *skb = skb_peek(ampdu_skb_retry_queue);
+        prn_aggr_err(sc, "Rr %d\n", (skb == NULL) ? (-1) : ampdu_skb_ssn(skb));
+        return NULL;
+    }
+#else
+    BUG_ON(head_ssn == SSV_ILLEGAL_SN);
+#endif
+    num_retry_mpdu = skb_queue_len(retry_queue);
+    if (num_retry_mpdu == 0)
+        return NULL;
+    new_ampdu_skb = _alloc_ampdu_skb(sc, ampdu_tid, max_aggr_len);
+    if (new_ampdu_skb == 0)
+        return NULL;
+    ampdu_hdr = (struct ampdu_hdr_st *)new_ampdu_skb->head;
+    total_skb_size = 0;
+    spin_lock_irqsave(&retry_queue->lock, flags);
+    for (temp_i = 0; temp_i < ampdu_tid->agg_num_max; temp_i++) {
+        u32 new_total_skb_size;
+        retry_mpdu = skb_peek(retry_queue);
+        if (retry_mpdu == NULL) {
+            break;
+        }
+        info = IEEE80211_SKB_CB(retry_mpdu);
+        vif_priv = (struct ssv_vif_priv_data *)info->control.vif->drv_priv;
+        new_total_skb_size = total_skb_size + retry_mpdu->len;
+        if (vif_priv->pair_cipher == SSV_CIPHER_CCMP) {
+            new_total_skb_size += CCMP_MIC_LEN;
+        }
+        if (new_total_skb_size > ampdu_hdr->max_size)
+            break;
+        total_skb_size = new_total_skb_size;
+#if 0
+        if (ampdu_skb_retry_queue != NULL)
+            prn_aggr_err(sc, "R %d\n", SerialNumber);
+#endif
+        retry_mpdu = __skb_dequeue(retry_queue);
+        _put_mpdu_to_ampdu(sc, new_ampdu_skb, retry_mpdu);
+        ampdu_tid->mib.ampdu_mib_retry_counter++;
+    }
+    ampdu_tid->mib.ampdu_mib_aggr_retry_counter += 1;
+    ampdu_tid->mib.ampdu_mib_dist[temp_i] += 1;
+    spin_unlock_irqrestore(&retry_queue->lock, flags);
+#if 0
+    {
+        struct ampdu_hdr_st *ampdu_hdr = (struct ampdu_hdr_st *)new_ampdu_skb->head;
+        retry_mpdu = skb_peek(&ampdu_hdr->mpdu_q);
+        dev_alert(sc->dev, "rA %d - %d\n", ampdu_skb_ssn(retry_mpdu),
+                  skb_queue_len(&ampdu_hdr->mpdu_q));
+    }
+#endif
+    if (ampdu_hdr->mpdu_num == 0) {
+        dev_kfree_skb_any(new_ampdu_skb);
+        return NULL;
+    }
+    return new_ampdu_skb;
+}
+#ifndef SSV_SUPPORT_HAL
+static void _add_ampdu_txinfo (struct ssv_softc *sc, struct sk_buff *ampdu_skb)
+{
+    struct ssv6200_tx_desc *tx_desc;
+    ssv6xxx_add_txinfo(sc, ampdu_skb);
+    tx_desc = (struct ssv6200_tx_desc *) ampdu_skb->data;
+    tx_desc->tx_report = 1;
+#if 0
+    tx_desc->len = ampdu_skb->len;
+    tx_desc->c_type = M2_TXREQ;
+    tx_desc->f80211 = 1;
+    tx_desc->ht = 1;
+    tx_desc->qos = 1;
+    tx_desc->use_4addr = 0;
+    tx_desc->security = 0;
+    tx_desc->more_data = 0;
+    tx_desc->stype_b5b4 = 0;
+    tx_desc->extra_info = 0;
+    tx_desc->hdr_offset = sc->sh->cfg.txpb_offset;;
+    tx_desc->frag = 0;
+    tx_desc->unicast = 1;
+    tx_desc->hdr_len = 0;
+    tx_desc->RSVD_4 = 0;
+    tx_desc->tx_burst = 0;
+    tx_desc->ack_policy = 1;
+    tx_desc->aggregation = 1;
+    tx_desc->RSVD_1 = 0;
+    tx_desc->do_rts_cts = 0;
+    tx_desc->reason = 0;
+    tx_desc->payload_offset = tx_desc->hdr_offset + tx_desc->hdr_len;
+    tx_desc->RSVD_4 = 0;
+    tx_desc->RSVD_2 = 0;
+    tx_desc->fCmdIdx = 0;
+    tx_desc->wsid = 0;
+    tx_desc->txq_idx = 0;
+    tx_desc->TxF_ID = 0;
+    tx_desc->rts_cts_nav = 0;
+    tx_desc->frame_consume_time = 0;
+    tx_desc->crate_idx=0;
+    tx_desc->drate_idx = 22;
+    tx_desc->dl_length = 56;
+    tx_desc->RSVD_3 = 0;
+#endif
+#if 0
+    if(ampdu_skb != 0) {
+        u32 temp_i;
+        u8* temp8_p = (u8*)ampdu_skb->data;
+        ampdu_db_log("print txinfo.\n");
+        for(temp_i=0; temp_i < 24; temp_i++) {
+            ampdu_db_log_simple("%02x",*(u8*)(temp8_p + temp_i));
+            if(((temp_i+1) % 4) == 0) {
+                ampdu_db_log_simple("\n");
+            }
+        }
+        ampdu_db_log_simple("\n");
+    }
+#endif
+#if 0
+    if(ampdu_skb != 0) {
+        u32 temp_i;
+        u8* temp8_p = (u8*)ampdu_skb->data;
+        ampdu_db_log("print all skb.\n");
+        for(temp_i=0; temp_i < ampdu_skb->len; temp_i++) {
+            ampdu_db_log_simple("%02x",*(u8*)(temp8_p + temp_i));
+            if(((temp_i+1) % 4) == 0) {
+                ampdu_db_log_simple("\n");
+            }
+        }
+        ampdu_db_log_simple("\n");
+    }
+#endif
+}
+#endif
+void _send_hci_skb (struct ssv_softc *sc, struct sk_buff *skb, u32 tx_flag)
+{
+    u32 txq_idx;
+    int ret;
+    unsigned long flags;
+    txq_idx = SSV_GET_TX_DESC_TXQ_IDX(sc->sh, skb);
+    spin_lock_irqsave(&sc->tx_pkt_run_no_lock, flags);
+    _acquire_new_ampdu_ssn_slot(sc, skb);
+    spin_unlock_irqrestore(&sc->tx_pkt_run_no_lock, flags);
+    ret = AMPDU_HCI_SEND(sc->sh, skb, txq_idx, tx_flag);
+#if 1
+    if ((txq_idx > 3) && (ret <= 0)) {
+        prn_aggr_err(sc, "BUG!! %d %d\n", txq_idx, ret);
+    }
+#else
+    BUG_ON(txq_idx>3 && ret<=0);
+#endif
+}
+static void ssv6200_ampdu_add_txinfo_and_send_HCI (struct ssv_softc *sc,
+        struct sk_buff *ampdu_skb,
+        u32 tx_flag)
+{
+    SSV_ADD_AMPDU_TXINFO(sc, ampdu_skb);
+    _send_hci_skb(sc, ampdu_skb, tx_flag);
+}
+static void ssv6200_ampdu_change_retry_frame_rate(struct sk_buff_head *ampdu_skb_retry_queue_p)
+{
+    struct sk_buff *skb;
+    struct ieee80211_tx_info *info;
+    struct ieee80211_tx_rate *ar;
+    int i;
+    skb = skb_dequeue(ampdu_skb_retry_queue_p);
+    info = IEEE80211_SKB_CB(skb);
+    for (i = 0; i < 3; i++) {
+        ar = &info->control.rates[i];
+        ar->idx = 0;
+        ar->count = 4;
+        ar->flags = IEEE80211_TX_RC_MCS;
+    }
+    ar = &info->control.rates[3];
+    ar->idx = -1;
+    ar->count = 0;
+    skb_queue_head(ampdu_skb_retry_queue_p, skb);
+}
+static void ssv6200_ampdu_send_retry (
+    struct ieee80211_hw *hw, AMPDU_TID *cur_ampdu_tid,
+    struct sk_buff_head *ampdu_skb_retry_queue_p, bool send_aggr_tx)
+{
+    struct ssv_softc *sc = hw->priv;
+    struct sk_buff *ampdu_retry_skb, *retry_mpdu;
+    u32 ampdu_skb_retry_queue_len;
+    u32 max_agg_len;
+    u16 lowest_rate;
+    struct fw_rc_retry_params rates[SSV62XX_TX_MAX_RATES];
+    SKB_info *mpdu_skb_info;
+    unsigned long flags;
+    ampdu_skb_retry_queue_len = skb_queue_len(ampdu_skb_retry_queue_p);
+    if (ampdu_skb_retry_queue_len == 0)
+        return;
+    spin_lock_irqsave(&ampdu_skb_retry_queue_p->lock, flags);
+    ampdu_retry_skb = skb_peek(ampdu_skb_retry_queue_p);
+    lowest_rate = SSV_HT_RATE_UPDATE(sc, ampdu_retry_skb, rates);
+    max_agg_len = SSV_AMPDU_MAX_TRANSMIT_LENGTH(sc, ampdu_retry_skb, lowest_rate);
+    if (max_agg_len == 0) {
+        ssv6200_ampdu_change_retry_frame_rate(ampdu_skb_retry_queue_p);
+        ampdu_retry_skb = skb_peek(ampdu_skb_retry_queue_p);
+        max_agg_len = SSV_AMPDU_MAX_TRANSMIT_LENGTH(sc, ampdu_retry_skb, 15);
+    }
+    spin_unlock_irqrestore(&ampdu_skb_retry_queue_p->lock, flags);
+    if (max_agg_len > 0) {
+        struct ssv_sta_priv_data *ssv_sta_priv = (struct ssv_sta_priv_data *)cur_ampdu_tid->sta->drv_priv;
+        u32 cur_ampdu_max_size = ssv_sta_priv->max_ampdu_size;
+        if (max_agg_len >= cur_ampdu_max_size)
+            max_agg_len = cur_ampdu_max_size;
+        while (ampdu_skb_retry_queue_len > 0) {
+            spin_lock_irqsave(&ampdu_skb_retry_queue_p->lock, flags);
+            retry_mpdu = skb_peek(ampdu_skb_retry_queue_p);
+            mpdu_skb_info = (SKB_info *)(retry_mpdu->head);
+            mpdu_skb_info->lowest_rate = lowest_rate;
+            memcpy(mpdu_skb_info->rates, rates, sizeof(rates));
+            spin_unlock_irqrestore(&ampdu_skb_retry_queue_p->lock, flags);
+            ampdu_retry_skb = _aggr_retry_mpdu(sc, cur_ampdu_tid, ampdu_skb_retry_queue_p,
+                                               max_agg_len);
+            if (ampdu_retry_skb != NULL) {
+                _sync_ampdu_pkt_arr(sc, cur_ampdu_tid, ampdu_retry_skb, true);
+                ssv6200_ampdu_add_txinfo_and_send_HCI(sc, ampdu_retry_skb,
+                                                      AMPDU_HCI_SEND_HEAD_WITHOUT_FLOWCTRL);
+            } else {
+                prn_aggr_err(sc, "AMPDU retry failed.\n");
+                return;
+            }
+            ampdu_skb_retry_queue_len = skb_queue_len(ampdu_skb_retry_queue_p);
+        }
+    }
+}
+void ssv6200_ampdu_init (struct ieee80211_hw *hw)
+{
+    struct ssv_softc *sc = hw->priv;
+    ssv6200_ampdu_hw_init(hw);
+    sc->tx.ampdu_tx_group_id = 0;
+#ifdef USE_ENCRYPT_WORK
+    INIT_WORK(&sc->ampdu_tx_encry_work, encry_work);
+    INIT_WORK(&sc->sync_hwkey_work, sync_hw_key_work);
+#endif
+}
+void ssv6200_ampdu_deinit (struct ieee80211_hw *hw)
+{
+}
+void ssv6200_ampdu_release_skb (struct sk_buff *skb, struct ieee80211_hw *hw)
+{
+#if LINUX_VERSION_CODE >= 0x030400
+    ieee80211_free_txskb(hw, skb);
+#else
+    dev_kfree_skb_any(skb);
+#endif
+}
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+struct mib_dump_data {
+    char *prt_buff;
+    size_t buff_size;
+    size_t prt_len;
+};
+#define AMPDU_TX_MIB_SUMMARY_BUF_SIZE (4096)
+static ssize_t ampdu_tx_mib_summary_read (struct file *file,
+        char __user *user_buf, size_t count,
+        loff_t *ppos)
+{
+    struct ssv_sta_priv_data *ssv_sta_priv =
+        (struct ssv_sta_priv_data *) file->private_data;
+    char *summary_buf = kzalloc(AMPDU_TX_MIB_SUMMARY_BUF_SIZE, GFP_KERNEL);
+    ssize_t summary_size;
+    ssize_t ret;
+    if (!summary_buf)
+        return -ENOMEM;
+    summary_size = ampdu_tx_mib_dump(ssv_sta_priv, summary_buf,
+                                     AMPDU_TX_MIB_SUMMARY_BUF_SIZE);
+    ret = simple_read_from_buffer(user_buf, count, ppos, summary_buf,
+                                  summary_size);
+    kfree(summary_buf);
+    return ret;
+}
+static int ampdu_tx_mib_summary_open (struct inode *inode, struct file *file)
+{
+    file->private_data = inode->i_private;
+    return 0;
+}
+static const struct file_operations mib_summary_fops = { .read =
+        ampdu_tx_mib_summary_read, .open = ampdu_tx_mib_summary_open,
+};
+static ssize_t ampdu_tx_tid_window_read (struct file *file,
+        char __user *user_buf, size_t count,
+        loff_t *ppos)
+{
+    struct AMPDU_TID_st *ampdu_tid = (struct AMPDU_TID_st *)file->private_data;
+    char *summary_buf = kzalloc(AMPDU_TX_MIB_SUMMARY_BUF_SIZE, GFP_KERNEL);
+    ssize_t ret;
+    char *prn_ptr = summary_buf;
+    int prt_size;
+    int buf_size = AMPDU_TX_MIB_SUMMARY_BUF_SIZE;
+    int i;
+    struct sk_buff *ba_skb, *tmp_ba_skb;
+    struct ssv_softc *sc;
+    if (!summary_buf)
+        return -ENOMEM;
+    sc = AMPDU_TID_TO_SC(ampdu_tid);
+    prt_size = snprintf(prn_ptr, buf_size, "\nWMM_TID %d:\n"
+                        "\tWindow:",
+                        ampdu_tid->tidno);
+    prn_ptr += prt_size;
+    buf_size -= prt_size;
+    for (i = 0; i < SSV_AMPDU_BA_WINDOW_SIZE; i++) {
+        struct sk_buff *skb = ampdu_tid->aggr_pkts[i];
+        if ((i % 8) == 0) {
+            prt_size = snprintf(prn_ptr, buf_size, "\n\t\t");
+            prn_ptr += prt_size;
+            buf_size -= prt_size;
+        }
+        if (skb == NULL)
+            prt_size = snprintf(prn_ptr, buf_size, " %s", "NULL ");
+        else {
+            struct SKB_info_st *skb_info = (struct SKB_info_st *)(skb->head);
+            const char status_symbol[] = {'N',
+                                          'A',
+                                          'S',
+                                          'R',
+                                          'P',
+                                          'D'
+                                         };
+            prt_size = snprintf(prn_ptr, buf_size, " %4d%c", ampdu_skb_ssn(skb),
+                                ( (skb_info->ampdu_tx_status <= AMPDU_ST_DONE)
+                                  ? status_symbol[skb_info->ampdu_tx_status]
+                                  : 'X'));
+        }
+        prn_ptr += prt_size;
+        buf_size -= prt_size;
+    }
+    prt_size = snprintf(prn_ptr, buf_size, "\n\tEarly aggregated #: %d\n", ampdu_tid->early_aggr_skb_num);
+    prn_ptr += prt_size;
+    buf_size -= prt_size;
+    prt_size = snprintf(prn_ptr, buf_size, "\tBAW skb #: %d\n", ampdu_tid->aggr_pkt_num);
+    prn_ptr += prt_size;
+    buf_size -= prt_size;
+    prt_size = snprintf(prn_ptr, buf_size, "\tBAW head: %d\n", ampdu_tid->ssv_baw_head);
+    prn_ptr += prt_size;
+    buf_size -= prt_size;
+    prt_size = snprintf(prn_ptr, buf_size, "\tState: %d\n", ampdu_tid->state);
+    prn_ptr += prt_size;
+    buf_size -= prt_size;
+    prt_size = snprintf(prn_ptr, buf_size, "\tBA:\n");
+    prn_ptr += prt_size;
+    buf_size -= prt_size;
+    skb_queue_walk_safe(&ampdu_tid->ba_q, ba_skb, tmp_ba_skb) {
+        prt_size = _dump_ba_skb(sc, prn_ptr, buf_size, ba_skb);
+        prn_ptr += prt_size;
+        buf_size -= prt_size;
+    }
+    buf_size = AMPDU_TX_MIB_SUMMARY_BUF_SIZE - buf_size;
+    ret = simple_read_from_buffer(user_buf, count, ppos, summary_buf,
+                                  buf_size);
+    kfree(summary_buf);
+    return ret;
+}
+static int ampdu_tx_tid_window_open (struct inode *inode, struct file *file)
+{
+    file->private_data = inode->i_private;
+    return 0;
+}
+static const struct file_operations tid_window_fops = { .read =
+        ampdu_tx_tid_window_read, .open = ampdu_tx_tid_window_open,
+};
+static int ampdu_tx_mib_reset_open (struct inode *inode, struct file *file)
+{
+    file->private_data = inode->i_private;
+    return 0;
+}
+static ssize_t ampdu_tx_mib_reset_read (struct file *file,
+                                        char __user *user_buf, size_t count,
+                                        loff_t *ppos)
+{
+    char *reset_buf = kzalloc(64, GFP_KERNEL);
+    ssize_t ret;
+    u32 reset_size;
+    if (!reset_buf)
+        return -ENOMEM;
+    reset_size = snprintf(reset_buf, 63, "%d", 0);
+    ret = simple_read_from_buffer(user_buf, count, ppos, reset_buf,
+                                  reset_size);
+    kfree(reset_buf);
+    return ret;
+}
+static ssize_t ampdu_tx_mib_reset_write (struct file *file,
+        const char __user *buffer,
+        size_t count,
+        loff_t *pos)
+{
+    struct AMPDU_TID_st *ampdu_tid = (struct AMPDU_TID_st *)file->private_data;
+    memset(&ampdu_tid->mib, 0, sizeof(struct AMPDU_MIB_st));
+    return count;
+}
+static const struct file_operations mib_reset_fops
+    = { .read = ampdu_tx_mib_reset_read,
+    .open = ampdu_tx_mib_reset_open,
+    .write = ampdu_tx_mib_reset_write
+};
+static void ssv6200_ampdu_tx_init_debugfs (
+    struct ssv_softc *sc, struct ssv_sta_priv_data *ssv_sta_priv)
+{
+    struct ssv_sta_info *sta_info = ssv_sta_priv->sta_info;
+    int i;
+    struct dentry *sta_debugfs_dir = sta_info->debugfs_dir;
+    dev_info(sc->dev, "Creating AMPDU TX debugfs.\n");
+    if (sta_debugfs_dir == NULL) {
+        dev_err(sc->dev, "No STA debugfs.\n");
+        return;
+    }
+    debugfs_create_file("ampdu_tx_summary", 00444, sta_debugfs_dir,
+                        ssv_sta_priv, &mib_summary_fops);
+    debugfs_create_u32("total_BA", 00644, sta_debugfs_dir,
+                       &ssv_sta_priv->ampdu_mib_total_BA_counter);
+    for (i = 0; i < WMM_TID_NUM; i++) {
+        char debugfs_name[20];
+        struct dentry *ampdu_tx_debugfs_dir;
+        int j;
+        struct AMPDU_TID_st *ampdu_tid = &ssv_sta_priv->ampdu_tid[i];
+        struct AMPDU_MIB_st *ampdu_mib = &ampdu_tid->mib;
+        snprintf(debugfs_name, sizeof(debugfs_name), "ampdu_tx_%d", i);
+        ampdu_tx_debugfs_dir = debugfs_create_dir(debugfs_name,
+                               sta_debugfs_dir);
+        if (ampdu_tx_debugfs_dir == NULL) {
+            dev_err(sc->dev,
+                    "Failed to create debugfs for AMPDU TX TID %d: %s\n", i,
+                    debugfs_name);
+            continue;
+        }
+        ssv_sta_priv->ampdu_tid[i].debugfs_dir = ampdu_tx_debugfs_dir;
+        debugfs_create_file("baw_status", 00444, ampdu_tx_debugfs_dir,
+                            ampdu_tid, &tid_window_fops);
+        debugfs_create_file("reset", 00644, ampdu_tx_debugfs_dir,
+                            ampdu_tid, &mib_reset_fops);
+        debugfs_create_u32("total", 00444, ampdu_tx_debugfs_dir,
+                           &ampdu_mib->ampdu_mib_ampdu_counter);
+        debugfs_create_u32("retry", 00444, ampdu_tx_debugfs_dir,
+                           &ampdu_mib->ampdu_mib_retry_counter);
+        debugfs_create_u32("aggr_retry", 00444, ampdu_tx_debugfs_dir,
+                           &ampdu_mib->ampdu_mib_aggr_retry_counter);
+        debugfs_create_u32("BAR", 00444, ampdu_tx_debugfs_dir,
+                           &ampdu_mib->ampdu_mib_bar_counter);
+        debugfs_create_u32("Discarded", 00444, ampdu_tx_debugfs_dir,
+                           &ampdu_mib->ampdu_mib_discard_counter);
+        debugfs_create_u32("BA", 00444, ampdu_tx_debugfs_dir,
+                           &ampdu_mib->ampdu_mib_BA_counter);
+        debugfs_create_u32("Pass", 00444, ampdu_tx_debugfs_dir,
+                           &ampdu_mib->ampdu_mib_pass_counter);
+        for (j = 0; j <= SSV_AMPDU_aggr_num_max; j++) {
+            char dist_dbg_name[10];
+            snprintf(dist_dbg_name, sizeof(dist_dbg_name), "aggr_%d", j);
+            debugfs_create_u32(dist_dbg_name, 00444, ampdu_tx_debugfs_dir,
+                               &ampdu_mib->ampdu_mib_dist[j]);
+        }
+        skb_queue_head_init(&ssv_sta_priv->ampdu_tid[i].ba_q);
+    }
+}
+#endif
+void ssv6200_ampdu_tx_add_sta (struct ieee80211_hw *hw,
+                               struct ieee80211_sta *sta)
+{
+    struct ssv_sta_priv_data *ssv_sta_priv;
+    struct ssv_softc *sc;
+    u32 temp_i;
+    ssv_sta_priv = (struct ssv_sta_priv_data *) sta->drv_priv;
+    sc = (struct ssv_softc *) hw->priv;
+    for (temp_i = 0; temp_i < WMM_TID_NUM; temp_i++) {
+        ssv_sta_priv->ampdu_tid[temp_i].sta = sta;
+        ssv_sta_priv->ampdu_tid[temp_i].state = AMPDU_STATE_STOP;
+        spin_lock_init(
+            &ssv_sta_priv->ampdu_tid[temp_i].ampdu_skb_tx_queue_lock);
+        spin_lock_init(&ssv_sta_priv->ampdu_tid[temp_i].pkt_array_lock);
+    }
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+    ssv6200_ampdu_tx_init_debugfs(sc, ssv_sta_priv);
+#endif
+}
+int ssv6200_ampdu_rx_start(struct ieee80211_hw *hw, struct ieee80211_vif *vif, struct ieee80211_sta *sta,
+                           u16 tid, u16 *ssn, u8 buf_size)
+{
+    struct ssv_softc *sc = hw->priv;
+#ifdef WIFI_CERTIFIED
+    if (sc->rx_ba_session_count >= sc->sh->rx_info.rx_ba_ma_sessions) {
+#if LINUX_VERSION_CODE > KERNEL_VERSION(3,1,0)
+        ieee80211_stop_rx_ba_session(vif, (1<<(sc->ba_tid)), sc->ba_ra_addr);
+#endif
+        sc->rx_ba_session_count--;
+    }
+#else
+    if ((sc->rx_ba_session_count >= sc->sh->rx_info.rx_ba_ma_sessions) && (sc->rx_ba_sta != sta)) {
+        return -EBUSY;
+    } else if ((sc->rx_ba_session_count >= sc->sh->rx_info.rx_ba_ma_sessions) && (sc->rx_ba_sta == sta)) {
+#if LINUX_VERSION_CODE > KERNEL_VERSION(3,1,0)
+        ieee80211_stop_rx_ba_session(vif,(1<<(sc->ba_tid)),sc->ba_ra_addr);
+#endif
+        sc->rx_ba_session_count--;
+    }
+#endif
+    printk(KERN_ERR "IEEE80211_AMPDU_RX_START %02X:%02X:%02X:%02X:%02X:%02X %d.\n",
+           sta->addr[0], sta->addr[1], sta->addr[2], sta->addr[3],
+           sta->addr[4], sta->addr[5], tid);
+    sc->rx_ba_session_count++;
+    sc->rx_ba_sta = sta;
+    sc->ba_tid = tid;
+    sc->ba_ssn = *ssn;
+    memcpy(sc->ba_ra_addr, sta->addr, ETH_ALEN);
+    return 0;
+}
+void ssv6200_ampdu_tx_start (u16 tid, struct ieee80211_sta *sta,
+                             struct ieee80211_hw *hw, u16 *ssn)
+{
+    struct ssv_softc *sc = hw->priv;
+    struct ssv_sta_priv_data *ssv_sta_priv;
+    struct AMPDU_TID_st *ampdu_tid;
+    int i;
+    ssv_sta_priv = (struct ssv_sta_priv_data *) sta->drv_priv;
+    ampdu_tid = &ssv_sta_priv->ampdu_tid[tid];
+    if (ampdu_tid->state == AMPDU_STATE_START)
+        return;
+    ampdu_tid->ssv_baw_head = SSV_ILLEGAL_SN;
+#if 0
+    if (list_empty(&sc->tx.ampdu_tx_que)) {
+        sc->ampdu_rekey_pause = AMPDU_REKEY_PAUSE_STOP;
+    }
+#endif
+#ifdef DEBUG_AMPDU_FLUSH
+    printk(KERN_ERR "Adding %02X-%02X-%02X-%02X-%02X-%02X TID %d (%p).\n",
+           sta->addr[0], sta->addr[1], sta->addr[2],
+           sta->addr[3], sta->addr[4], sta->addr[5],
+           ampdu_tid->tidno, ampdu_tid);
+    {
+        int j;
+        for (j = 0; j <= MAX_TID; j++) {
+            if (sc->tid[j] == 0)
+                break;
+        }
+        if (j == MAX_TID) {
+            printk(KERN_ERR "No room for new TID.\n");
+        } else
+            sc->tid[j] = ampdu_tid;
+    }
+#endif
+    list_add_tail_rcu(&ampdu_tid->list, &sc->tx.ampdu_tx_que);
+    skb_queue_head_init(&ampdu_tid->ampdu_skb_tx_queue);
+#ifdef ENABLE_INCREMENTAL_AGGREGATION
+    skb_queue_head_init(&ampdu_tid->early_aggr_ampdu_q);
+    ampdu_tid->early_aggr_skb_num = 0;
+#endif
+    skb_queue_head_init(&ampdu_tid->ampdu_skb_wait_encry_queue);
+    skb_queue_head_init(&ampdu_tid->retry_queue);
+    skb_queue_head_init(&ampdu_tid->release_queue);
+    for (i = 0;
+         i < (sizeof(ampdu_tid->aggr_pkts) / sizeof(ampdu_tid->aggr_pkts[0]));
+         i++)
+        ampdu_tid->aggr_pkts[i] = 0;
+    ampdu_tid->aggr_pkt_num = 0;
+#ifdef ENABLE_AGGREGATE_IN_TIME
+    ampdu_tid->cur_ampdu_pkt = _alloc_ampdu_skb(sc, ampdu_tid, 0);
+#endif
+#ifdef AMPDU_CHECK_SKB_SEQNO
+    ssv_sta_priv->ampdu_tid[tid].last_seqno = (-1);
+#endif
+    ssv_sta_priv->ampdu_mib_total_BA_counter = 0;
+    memset(&ssv_sta_priv->ampdu_tid[tid].mib, 0, sizeof(struct AMPDU_MIB_st));
+    ssv_sta_priv->ampdu_tid[tid].state = AMPDU_STATE_START;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+    skb_queue_head_init(&ssv_sta_priv->ampdu_tid[tid].ba_q);
+#endif
+}
+void ssv6200_ampdu_tx_operation (u16 tid, struct ieee80211_sta *sta,
+                                 struct ieee80211_hw *hw, u8 buffer_size)
+{
+    struct ssv_sta_priv_data *ssv_sta_priv;
+    ssv_sta_priv = (struct ssv_sta_priv_data *) sta->drv_priv;
+    ssv_sta_priv->ampdu_tid[tid].tidno = tid;
+    ssv_sta_priv->ampdu_tid[tid].sta = sta;
+    ssv_sta_priv->ampdu_tid[tid].agg_num_max = MAX_AGGR_NUM;
+#if 1
+    if (buffer_size > IEEE80211_MAX_AMPDU_BUF) {
+        buffer_size = IEEE80211_MAX_AMPDU_BUF;
+    }
+    printk("ssv6200_ampdu_tx_operation:buffer_size=%d\n", buffer_size);
+    ssv_sta_priv->ampdu_tid[tid].ssv_baw_size = SSV_AMPDU_WINDOW_SIZE;
+#else
+    ssv_sta_priv->ampdu_tid[tid].ssv_baw_size = IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
+    if(buffer_size > IEEE80211_MAX_AMPDU_BUF) {
+        buffer_size = IEEE80211_MAX_AMPDU_BUF;
+    }
+    if(ssv_sta_priv->ampdu_tid[tid].ssv_baw_size > buffer_size) {
+        ssv_sta_priv->ampdu_tid[tid].ssv_baw_size = buffer_size;
+    }
+#endif
+    ssv_sta_priv->ampdu_tid[tid].state = AMPDU_STATE_OPERATION;
+}
+static void _clear_mpdu_q (struct ieee80211_hw *hw, struct sk_buff_head *q,
+                           bool aggregated_mpdu)
+{
+    struct ssv_softc *sc = hw->priv;
+    struct sk_buff *skb;
+    struct SKB_info_st *mpdu_skb_info_p = NULL;
+    while (1) {
+        skb = skb_dequeue(q);
+        if (!skb)
+            break;
+        mpdu_skb_info_p = (SKB_info *) (skb->head);
+        if (aggregated_mpdu)
+            skb_pull(skb, AMPDU_DELIMITER_LEN);
+        if (mpdu_skb_info_p->directly_ack)
+            dev_kfree_skb_any(skb);
+        else {
+            ieee80211_tx_status(hw, skb);
+        }
+        atomic_dec(&sc->ampdu_tx_frame);
+    }
+}
+void ssv6200_ampdu_tx_stop (u16 tid, struct ieee80211_sta *sta,
+                            struct ieee80211_hw *hw)
+{
+    struct ssv_softc *sc = hw->priv;
+    struct ssv_sta_priv_data *ssv_sta_priv;
+    struct sk_buff *ampdu_skb;
+    struct ampdu_hdr_st *ampdu_hdr;
+    struct SKB_info_st *skb_info;
+    int i = 0;
+    bool collect_ba_window_frame = false;
+    ssv_sta_priv = (struct ssv_sta_priv_data *) sta->drv_priv;
+    if (ssv_sta_priv->ampdu_tid[tid].state == AMPDU_STATE_STOP)
+        return;
+    ssv_sta_priv->ampdu_tid[tid].state = AMPDU_STATE_STOP;
+    printk("ssv6200_ampdu_tx_stop\n");
+    if (!list_empty(&sc->tx.ampdu_tx_que)) {
+#ifdef DEBUG_AMPDU_FLUSH
+        {
+            int j;
+            struct AMPDU_TID_st *ampdu_tid = &ssv_sta_priv->ampdu_tid[tid];
+            for (j = 0; j <= MAX_TID; j++)
+            {
+                if (sc->tid[j] == ampdu_tid)
+                    break;
+            }
+            if (j == MAX_TID)
+            {
+                printk(KERN_ERR "No TID found when deleting it.\n");
+            } else
+                sc->tid[j] = NULL;
+            printk(KERN_ERR "Deleting %02X-%02X-%02X-%02X-%02X-%02X TID %d (%p).\n",
+                   sta->addr[0], sta->addr[1], sta->addr[2],
+                   sta->addr[3], sta->addr[4], sta->addr[5],
+                   ampdu_tid->tidno, ampdu_tid);
+        }
+#endif
+        list_del_rcu(&ssv_sta_priv->ampdu_tid[tid].list);
+    }
+    for (i = 0; i < SSV_AMPDU_BA_WINDOW_SIZE; i++) {
+        struct sk_buff *skb = ssv_sta_priv->ampdu_tid[tid].aggr_pkts[i];
+        if (skb != NULL) {
+            skb_info = (struct SKB_info_st *) (skb->head);
+            skb_info->mpdu_retry_counter = SSV_AMPDU_retry_counter_max;
+            if(skb_info->ampdu_tx_status != AMPDU_ST_RETRY_Q) {
+                skb_info->ampdu_tx_status = AMPDU_ST_DROPPED;
+            }
+            collect_ba_window_frame = true;
+        }
+    }
+    if (collect_ba_window_frame) {
+        printk("collect ba sindow frame to release queue\n");
+        ssv6xxx_release_frames(&ssv_sta_priv->ampdu_tid[tid]);
+    }
+    printk("clear tx q len=%d\n",
+           skb_queue_len(&ssv_sta_priv->ampdu_tid[tid].ampdu_skb_tx_queue));
+    _clear_mpdu_q(sc->hw, &ssv_sta_priv->ampdu_tid[tid].ampdu_skb_tx_queue,
+                  true);
+    printk("clear retry q len=%d\n",
+           skb_queue_len(&ssv_sta_priv->ampdu_tid[tid].retry_queue));
+    _clear_mpdu_q(sc->hw, &ssv_sta_priv->ampdu_tid[tid].retry_queue, true);
+#ifdef USE_ENCRYPT_WORK
+    printk("clear encrypt q len=%d\n",skb_queue_len(&ssv_sta_priv->ampdu_tid[tid].ampdu_skb_wait_encry_queue));
+    _clear_mpdu_q(sc->hw, &ssv_sta_priv->ampdu_tid[tid].ampdu_skb_wait_encry_queue, false);
+#endif
+    printk("clear release q len=%d\n",
+           skb_queue_len(&ssv_sta_priv->ampdu_tid[tid].release_queue));
+    _clear_mpdu_q(sc->hw, &ssv_sta_priv->ampdu_tid[tid].release_queue, true);
+    printk("clear early aggr ampdu q len=%d\n",
+           skb_queue_len(&ssv_sta_priv->ampdu_tid[tid].early_aggr_ampdu_q));
+    while (skb_queue_len(&ssv_sta_priv->ampdu_tid[tid].early_aggr_ampdu_q)) {
+        ampdu_skb = skb_dequeue(&ssv_sta_priv->ampdu_tid[tid].early_aggr_ampdu_q);
+        ampdu_hdr = (struct ampdu_hdr_st *) ampdu_skb->head;
+        _clear_mpdu_q(sc->hw, &ampdu_hdr->mpdu_q, true);
+        ssv6200_ampdu_release_skb(ampdu_skb, sc->hw);
+    }
+#ifdef ENABLE_AGGREGATE_IN_TIME
+    if (ssv_sta_priv->ampdu_tid[tid].cur_ampdu_pkt != NULL) {
+        dev_kfree_skb_any(ssv_sta_priv->ampdu_tid[tid].cur_ampdu_pkt);
+        ssv_sta_priv->ampdu_tid[tid].cur_ampdu_pkt = NULL;
+    }
+#endif
+    ssv6200_tx_flow_control((void *) sc,
+                            sc->tx.hw_txqid[ssv_sta_priv->ampdu_tid[tid].ac],
+                            false, 1000);
+}
+void ssv6xxx_ampdu2mpdu(struct ieee80211_hw *hw, struct ieee80211_vif *vif, struct sk_buff *skb)
+{
+    struct ssv_softc *sc = hw->priv;
+    struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
+    struct SKB_info_st *skb_info = (struct SKB_info_st *)skb->head;
+    struct ieee80211_sta *sta = skb_info->sta;
+    struct ssv_sta_priv_data *ssv_sta_priv = (struct ssv_sta_priv_data *) sta->drv_priv;
+    struct AMPDU_TID_st *ampdu_tid;
+    u16 tidno = 0;
+    if (!sta)
+        return;
+    if (!SSV_RC_HT_STA_CURRENT_RATE_IS_CCK(sc, sta))
+        return;
+    ssv6xxx_ampdu_flush(sc->hw);
+    if (!ieee80211_is_data(hdr->frame_control))
+        return;
+    tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
+    ampdu_tid = &ssv_sta_priv->ampdu_tid[tidno];
+    if (ampdu_tid->state == AMPDU_STATE_STOP)
+        return;
+    if ((skb_queue_len(&ampdu_tid->early_aggr_ampdu_q) != 0) || (skb_queue_len(&ampdu_tid->retry_queue) != 0))
+        return;
+    if (ampdu_tid->aggr_pkt_num != 0)
+        return;
+    ieee80211_stop_tx_ba_session(sta, tidno);
+}
+static void ssv6200_ampdu_tx_state_stop_func (
+    struct ssv_softc *sc, struct ieee80211_sta *sta, struct sk_buff *skb,
+    struct AMPDU_TID_st *cur_AMPDU_TID)
+{
+    struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
+    u8 *skb_qos_ctl = ieee80211_get_qos_ctl(hdr);
+    u8 tid_no = skb_qos_ctl[0] & 0xf;
+    if ((sta->ht_cap.ht_supported == true)
+        && (!!(sc->sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_TX))) {
+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,32)
+        ieee80211_start_tx_ba_session(sc->hw, (u8*)(sta->addr), (u16)tid_no);
+#elif LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,37)
+        ieee80211_start_tx_ba_session(sta, tid_no);
+#else
+        ieee80211_start_tx_ba_session(sta, tid_no, 0);
+#endif
+        ampdu_db_log("start ampdu_tx(rc) : tid_no = %d\n", tid_no);
+    }
+}
+static void ssv6200_ampdu_tx_state_operation_func (
+    struct ssv_softc *sc, struct ieee80211_sta *sta, struct sk_buff *skb,
+    struct AMPDU_TID_st *cur_AMPDU_TID)
+{
+#if 0
+    else if (sc->ampdu_rekey_pause == AMPDU_REKEY_PAUSE_ONGOING) {
+        pause_ampdu = true;
+        printk("!!!ampdu_rekey_pause\n");
+    }
+#endif
+}
+void ssv6200_ampdu_tx_update_state (void *priv, struct ieee80211_sta *sta,
+                                    struct sk_buff *skb)
+{
+    struct ssv_softc *sc = (struct ssv_softc *) priv;
+    struct ssv_sta_priv_data *ssv_sta_priv =
+        (struct ssv_sta_priv_data *) sta->drv_priv;
+    struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
+    u8 *skb_qos_ctl;
+    u8 tid_no;
+    {
+        skb_qos_ctl = ieee80211_get_qos_ctl(hdr);
+        tid_no = skb_qos_ctl[0] & 0xf;
+        switch (ssv_sta_priv->ampdu_tid[tid_no].state) {
+        case AMPDU_STATE_STOP:
+            ssv6200_ampdu_tx_state_stop_func(
+                sc, sta, skb, &(ssv_sta_priv->ampdu_tid[tid_no]));
+            break;
+        case AMPDU_STATE_START:
+            break;
+        case AMPDU_STATE_OPERATION:
+            ssv6200_ampdu_tx_state_operation_func(
+                sc, sta, skb, &(ssv_sta_priv->ampdu_tid[tid_no]));
+            break;
+        default:
+            break;
+        }
+    }
+}
+static int _acquire_new_ampdu_ssn_slot(struct ssv_softc *sc, struct sk_buff *ampdu)
+{
+    struct ssv_sta_priv_data *ssv_sta_priv;
+    int i, find_ampdu_slot = -1;
+    struct ampdu_hdr_st *ampdu_hdr = (struct ampdu_hdr_st *) ampdu->head;
+    struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(ampdu->data + TXPB_OFFSET + AMPDU_DELIMITER_LEN);
+    struct ieee80211_sta *sta = NULL;
+    int j = 0, k;
+    struct AMPDU_TID_st *ampdu_tid;
+    sc->tx_pkt_run_no ++;
+    sc->tx_pkt_run_no &= SSV6XXX_PKT_RUN_TYPE_AMPDU_END;
+    if (sc->tx_pkt_run_no == SSV6XXX_PKT_RUN_TYPE_NOTUSED)
+        sc->tx_pkt_run_no ++;
+    SSV_UPDATE_AMPDU_TXINFO(sc, ampdu);
+    sta = ampdu_hdr->ampdu_tid->sta;
+    ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_AMPDU_SSN,
+             "%s: current tx_pkt_run_no %d\n", __func__, sc->tx_pkt_run_no);
+    for (i = 0; i < MAX_CONCUR_AMPDU; i++) {
+        if (ssv_sta_priv->ampdu_ssn[i].tx_pkt_run_no == sc->tx_pkt_run_no) {
+            dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_AMPDU_SSN,
+                     "Find the duplicated tx_pkt_run_no[%d]:ssn at slot %d", sc->tx_pkt_run_no, i);
+            ampdu_tid = &(ssv_sta_priv->ampdu_tid[ssv_sta_priv->ampdu_ssn[i].tid_no]);
+            for (k = 0; k < ssv_sta_priv->ampdu_ssn[i].mpdu_num; k++) {
+                u16 ssn = ssv_sta_priv->ampdu_ssn[i].ssn[k];
+                struct sk_buff *mpdu;
+                u32 skb_ssn;
+                struct SKB_info_st *skb_info;
+                dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_AMPDU_SSN," %d", ssn);
+                mpdu = INDEX_PKT_BY_SSN(ampdu_tid, ssn);
+                skb_ssn = (mpdu == NULL) ? (-1) : ampdu_skb_ssn(mpdu);
+                if (skb_ssn != ssn)
+                    continue;
+                skb_info = (struct SKB_info_st *) (mpdu->head);
+                skb_info->ampdu_tx_status = AMPDU_ST_RETRY;
+            }
+            dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_AMPDU_SSN,"\n current slot content");
+            for (j =0 ; j < MAX_CONCUR_AMPDU; j++) {
+                if (j %16 == 0)
+                    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_AMPDU_SSN,"\n");
+                dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_AMPDU_SSN,"%d: %d ", j, ssv_sta_priv->ampdu_ssn[j].tx_pkt_run_no);
+            }
+            dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_AMPDU_SSN,"\n");
+            memset((void*)&ssv_sta_priv->ampdu_ssn[i], 0, sizeof(struct aggr_ssn));
+        }
+        if ((find_ampdu_slot == -1) && (ssv_sta_priv->ampdu_ssn[i].tx_pkt_run_no == SSV6XXX_PKT_RUN_TYPE_NOTUSED)) {
+            find_ampdu_slot = i;
+        }
+    }
+    if (find_ampdu_slot != -1) {
+        dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_AMPDU_SSN,
+                 "%s: tx_pkt_run_no %d: slot %d ssn", __func__, sc->tx_pkt_run_no, find_ampdu_slot);
+        for (k = 0; k < ampdu_hdr->mpdu_num; k++) {
+            ssv_sta_priv->ampdu_ssn[find_ampdu_slot].ssn[k] = ampdu_hdr->ssn[k];
+            dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_AMPDU_SSN," %d,", ampdu_hdr->ssn[k]);
+        }
+        dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_AMPDU_SSN,"\n");
+        ssv_sta_priv->ampdu_ssn[find_ampdu_slot].tx_pkt_run_no = sc->tx_pkt_run_no;
+        ssv_sta_priv->ampdu_ssn[find_ampdu_slot].mpdu_num = ampdu_hdr->mpdu_num;
+        ssv_sta_priv->ampdu_ssn[find_ampdu_slot].tid_no = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
+    }
+    return find_ampdu_slot;
+}
+void _put_mpdu_to_ampdu (struct ssv_softc *sc, struct sk_buff *ampdu, struct sk_buff *mpdu)
+{
+    bool is_empty_ampdu = (ampdu->len == 0);
+    unsigned char *data_dest;
+    struct ampdu_hdr_st *ampdu_hdr = (struct ampdu_hdr_st *) ampdu->head;
+    struct ieee80211_tx_info *info = IEEE80211_SKB_CB(mpdu);
+    struct ssv_vif_priv_data *vif_priv = (struct ssv_vif_priv_data *)info->control.vif->drv_priv;
+    BUG_ON(skb_tailroom(ampdu) < mpdu->len);
+    data_dest = skb_tail_pointer(ampdu);
+    skb_put(ampdu, mpdu->len);
+    if (vif_priv->pair_cipher == SSV_CIPHER_CCMP) {
+        skb_put(ampdu, CCMP_MIC_LEN);
+    }
+    if (is_empty_ampdu) {
+        struct ieee80211_tx_info *ampdu_info = IEEE80211_SKB_CB(ampdu);
+        struct ieee80211_tx_info *mpdu_info = IEEE80211_SKB_CB(mpdu);
+        SKB_info *mpdu_skb_info = (SKB_info *)(mpdu->head);
+        u32 max_size_for_rate = SSV_AMPDU_MAX_TRANSMIT_LENGTH(sc, mpdu, mpdu_skb_info->lowest_rate);
+        BUG_ON(max_size_for_rate == 0);
+        memcpy(ampdu_info, mpdu_info, sizeof(struct ieee80211_tx_info));
+        skb_set_queue_mapping(ampdu, skb_get_queue_mapping(mpdu));
+        ampdu_hdr->first_sn = ampdu_skb_ssn(mpdu);
+        ampdu_hdr->sta = ((struct SKB_info_st *)mpdu->head)->sta;
+        if (ampdu_hdr->max_size > max_size_for_rate)
+            ampdu_hdr->max_size = max_size_for_rate;
+        memcpy(ampdu_hdr->rates, mpdu_skb_info->rates, sizeof(ampdu_hdr->rates));
+    }
+    memcpy(data_dest, mpdu->data, mpdu->len);
+    __skb_queue_tail(&ampdu_hdr->mpdu_q, mpdu);
+    ampdu_hdr->ssn[ampdu_hdr->mpdu_num++] = ampdu_skb_ssn(mpdu);
+    ampdu_hdr->size += mpdu->len;
+    if (vif_priv->pair_cipher == SSV_CIPHER_CCMP) {
+        ampdu_hdr->size += CCMP_MIC_LEN;
+    }
+    BUG_ON(ampdu_hdr->size > ampdu_hdr->max_size);
+}
+u32 _flush_early_ampdu_q (struct ssv_softc *sc, struct AMPDU_TID_st *ampdu_tid)
+{
+    u32 flushed_ampdu = 0;
+    unsigned long flags;
+    struct sk_buff_head *early_aggr_ampdu_q = &ampdu_tid->early_aggr_ampdu_q;
+    spin_lock_irqsave(&early_aggr_ampdu_q->lock, flags);
+    while (skb_queue_len(early_aggr_ampdu_q)) {
+        struct sk_buff *head_ampdu;
+        struct ampdu_hdr_st *head_ampdu_hdr;
+        u32 ampdu_aggr_num;
+        head_ampdu = skb_peek(early_aggr_ampdu_q);
+        head_ampdu_hdr = (struct ampdu_hdr_st *) head_ampdu->head;
+        ampdu_aggr_num = skb_queue_len(&head_ampdu_hdr->mpdu_q);
+        if (ampdu_aggr_num == 0) {
+            head_ampdu = __skb_dequeue(early_aggr_ampdu_q);
+            ssv6200_ampdu_release_skb(head_ampdu, sc->hw);
+            continue;
+        }
+        if ((SSV_AMPDU_BA_WINDOW_SIZE - ampdu_tid->aggr_pkt_num)
+            < ampdu_aggr_num)
+            break;
+        if (_sync_ampdu_pkt_arr(sc, ampdu_tid, head_ampdu, false)) {
+            head_ampdu = __skb_dequeue(early_aggr_ampdu_q);
+            ampdu_tid->early_aggr_skb_num -= ampdu_aggr_num;
+#ifdef SSV_AMPDU_FLOW_CONTROL
+            if (ampdu_tid->early_aggr_skb_num
+                <= SSV_AMPDU_FLOW_CONTROL_LOWER_BOUND) {
+                ssv6200_tx_flow_control((void *) sc,
+                                        sc->tx.hw_txqid[ampdu_tid->ac], false, 1000);
+            }
+#endif
+            if ((skb_queue_len(early_aggr_ampdu_q) == 0)
+                && (ampdu_tid->early_aggr_skb_num > 0)) {
+                printk(KERN_ERR "Empty early Q w. %d.\n", ampdu_tid->early_aggr_skb_num);
+            }
+            spin_unlock_irqrestore(&early_aggr_ampdu_q->lock, flags);
+            _send_hci_skb(sc, head_ampdu,
+                          AMPDU_HCI_SEND_TAIL_WITHOUT_FLOWCTRL);
+            spin_lock_irqsave(&early_aggr_ampdu_q->lock, flags);
+            flushed_ampdu++;
+        } else
+            break;
+    }
+    spin_unlock_irqrestore(&early_aggr_ampdu_q->lock, flags);
+    return flushed_ampdu;
+}
+void _aggr_ampdu_tx_q (struct ieee80211_hw *hw, struct AMPDU_TID_st *ampdu_tid)
+{
+    struct ssv_softc *sc = hw->priv;
+    struct sk_buff *ampdu_skb = ampdu_tid->cur_ampdu_pkt;
+    struct ieee80211_tx_info *info;
+    struct ssv_vif_priv_data *vif_priv;
+    while (skb_queue_len(&ampdu_tid->ampdu_skb_tx_queue)) {
+        u32 aggr_len;
+        struct sk_buff *mpdu_skb;
+        struct ampdu_hdr_st *ampdu_hdr;
+        bool is_aggr_full = false;
+        if (ampdu_skb == NULL) {
+            ampdu_skb = _alloc_ampdu_skb(sc, ampdu_tid, 0);
+            if (ampdu_skb == NULL)
+                break;
+            ampdu_tid->cur_ampdu_pkt = ampdu_skb;
+        }
+        ampdu_hdr = (struct ampdu_hdr_st *) ampdu_skb->head;
+        aggr_len = skb_queue_len(&ampdu_hdr->mpdu_q);
+        do {
+            struct sk_buff_head *tx_q = &ampdu_tid->ampdu_skb_tx_queue;
+            unsigned long flags;
+            u32 new_total_skb_size;
+            spin_lock_irqsave(&tx_q->lock, flags);
+            mpdu_skb = skb_peek(&ampdu_tid->ampdu_skb_tx_queue);
+            if (mpdu_skb == NULL) {
+                spin_unlock_irqrestore(&tx_q->lock, flags);
+                break;
+            }
+            info = IEEE80211_SKB_CB(mpdu_skb);
+            vif_priv = (struct ssv_vif_priv_data *)info->control.vif->drv_priv;
+            new_total_skb_size = mpdu_skb->len + ampdu_hdr->size;
+            if (vif_priv->pair_cipher == SSV_CIPHER_CCMP) {
+                new_total_skb_size += CCMP_MIC_LEN;
+            }
+            if ( new_total_skb_size > ampdu_hdr->max_size) {
+                is_aggr_full = true;
+                spin_unlock_irqrestore(&tx_q->lock, flags);
+                break;
+            }
+            mpdu_skb = __skb_dequeue(&ampdu_tid->ampdu_skb_tx_queue);
+            spin_unlock_irqrestore(&tx_q->lock, flags);
+            _put_mpdu_to_ampdu(sc, ampdu_skb, mpdu_skb);
+        } while (++aggr_len < MAX_AGGR_NUM );
+        if ( (is_aggr_full || (aggr_len >= MAX_AGGR_NUM))
+             || ( (aggr_len > 0)
+                  && (skb_queue_len(&ampdu_tid->early_aggr_ampdu_q) == 0)
+                  && (ampdu_tid->ssv_baw_head == SSV_ILLEGAL_SN)
+                  && _is_skb_q_empty(sc, ampdu_skb))) {
+            SSV_ADD_AMPDU_TXINFO(sc, ampdu_skb);
+            _queue_early_ampdu(sc, ampdu_tid, ampdu_skb);
+            ampdu_tid->cur_ampdu_pkt = ampdu_skb = NULL;
+        }
+        _flush_early_ampdu_q(sc, ampdu_tid);
+    }
+}
+void _queue_early_ampdu (struct ssv_softc *sc, struct AMPDU_TID_st *ampdu_tid,
+                         struct sk_buff *ampdu_skb)
+{
+    unsigned long flags;
+    struct ampdu_hdr_st *ampdu_hdr = (struct ampdu_hdr_st *) ampdu_skb->head;
+    spin_lock_irqsave(&ampdu_tid->early_aggr_ampdu_q.lock, flags);
+    __skb_queue_tail(&ampdu_tid->early_aggr_ampdu_q, ampdu_skb);
+    ampdu_tid->early_aggr_skb_num += skb_queue_len(&ampdu_hdr->mpdu_q);
+#ifdef SSV_AMPDU_FLOW_CONTROL
+    if (ampdu_tid->early_aggr_skb_num >= SSV_AMPDU_FLOW_CONTROL_UPPER_BOUND) {
+        ssv6200_tx_flow_control((void *) sc, sc->tx.hw_txqid[ampdu_tid->ac],
+                                true, 1000);
+    }
+#endif
+    spin_unlock_irqrestore(&ampdu_tid->early_aggr_ampdu_q.lock, flags);
+}
+void _flush_mpdu (struct ssv_softc *sc, struct ieee80211_sta *sta)
+{
+    unsigned long flags;
+    struct ssv_sta_priv_data *ssv_sta_priv = (struct ssv_sta_priv_data *) sta->drv_priv;
+    int i;
+    for (i = 0; i < (sizeof(ssv_sta_priv->ampdu_tid) / sizeof(ssv_sta_priv->ampdu_tid[0])); i++) {
+        struct AMPDU_TID_st *ampdu_tid = &ssv_sta_priv->ampdu_tid[i];
+        struct sk_buff_head *early_aggr_ampdu_q;
+        struct sk_buff *ampdu;
+        struct ampdu_hdr_st *ampdu_hdr;
+        struct sk_buff_head *mpdu_q;
+        struct sk_buff *mpdu;
+        if (ampdu_tid->state != AMPDU_STATE_OPERATION)
+            continue;
+        early_aggr_ampdu_q = &ampdu_tid->early_aggr_ampdu_q;
+        spin_lock_irqsave(&early_aggr_ampdu_q->lock, flags);
+        while ((ampdu = __skb_dequeue(early_aggr_ampdu_q)) != NULL) {
+            ampdu_hdr = (struct ampdu_hdr_st *)ampdu->head;
+            mpdu_q = &ampdu_hdr->mpdu_q;
+            spin_unlock_irqrestore(&early_aggr_ampdu_q->lock, flags);
+            while ((mpdu = __skb_dequeue(mpdu_q)) != NULL) {
+                _send_hci_skb(sc, mpdu, AMPDU_HCI_SEND_TAIL_WITHOUT_FLOWCTRL);
+            }
+            ssv6200_ampdu_release_skb(ampdu, sc->hw);
+            spin_lock_irqsave(&early_aggr_ampdu_q->lock, flags);
+        }
+        if (ampdu_tid->cur_ampdu_pkt != NULL) {
+            ampdu_hdr = (struct ampdu_hdr_st *)ampdu_tid->cur_ampdu_pkt->head;
+            mpdu_q = &ampdu_hdr->mpdu_q;
+            spin_unlock_irqrestore(&early_aggr_ampdu_q->lock, flags);
+            while ((mpdu = __skb_dequeue(mpdu_q)) != NULL) {
+                _send_hci_skb(sc, mpdu, AMPDU_HCI_SEND_TAIL_WITHOUT_FLOWCTRL);
+            }
+            ssv6200_ampdu_release_skb(ampdu_tid->cur_ampdu_pkt, sc->hw);
+            spin_lock_irqsave(&early_aggr_ampdu_q->lock, flags);
+            ampdu_tid->cur_ampdu_pkt = NULL;
+        }
+        spin_unlock_irqrestore(&early_aggr_ampdu_q->lock, flags);
+    }
+}
+bool ssv6200_ampdu_tx_handler (struct ieee80211_hw *hw, struct sk_buff *skb)
+{
+    struct ssv_softc *sc = hw->priv;
+    struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
+    struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
+    struct sk_buff *tx_skb = skb;
+    struct sk_buff *copy_skb = NULL;
+    struct SKB_info_st *mpdu_skb_info_p = (SKB_info *) (skb->head);
+    struct SKB_info_st *copy_skb_info_p = NULL;
+    struct ieee80211_sta *sta = mpdu_skb_info_p->sta;
+    struct ssv_sta_priv_data *ssv_sta_priv =
+        (struct ssv_sta_priv_data *) sta->drv_priv;
+    u8 tidno;
+    struct AMPDU_TID_st *ampdu_tid;
+    int ampdu_tx_frame = 0;
+    if (sta == NULL) {
+        WARN_ON(1);
+        return false;
+    }
+    tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
+    ampdu_db_log("tidno = %d\n", tidno);
+    ampdu_tid = &ssv_sta_priv->ampdu_tid[tidno];
+    if (ampdu_tid->state != AMPDU_STATE_OPERATION)
+        return false;
+#ifdef AMPDU_CHECK_SKB_SEQNO
+    {
+        u32 skb_seqno = ((struct ieee80211_hdr*) (skb->data))->seq_ctrl
+                        >> SSV_SEQ_NUM_SHIFT;
+        u32 tid_seqno = ampdu_tid->last_seqno;
+        if ((tid_seqno != (-1)) && (skb_seqno != NEXT_PKT_SN(tid_seqno))) {
+            prn_aggr_err(sc, "Non continueous seq no: %d - %d\n", tid_seqno, skb_seqno);
+            return false;
+        }
+        ampdu_tid->last_seqno = skb_seqno;
+    }
+#endif
+#if 1
+    mpdu_skb_info_p->lowest_rate = SSV_HT_RATE_UPDATE(sc, skb, mpdu_skb_info_p->rates);
+    if (SSV_AMPDU_MAX_TRANSMIT_LENGTH(sc, skb, mpdu_skb_info_p->lowest_rate) == 0) {
+        return false;
+    }
+#endif
+#if 0
+    if ((ampdu_tid->ssv_baw_head == SSV_ILLEGAL_SN)
+        && (skb_queue_len(&ampdu_tid->ampdu_skb_tx_queue) == 0)
+        && (skb_queue_len(&ampdu_tid->early_aggr_ampdu_q) == 0)
+        && ((ampdu_tid->cur_ampdu_pkt == NULL)
+            || (skb_queue_len(
+                    &((struct ampdu_hdr_st *) (ampdu_tid->cur_ampdu_pkt->head))->mpdu_q)
+                == 0))
+        && _is_skb_q_empty(sc, skb)) {
+        ampdu_tid->mib.ampdu_mib_pass_counter++;
+#if 0
+        prn_aggr_err(sc,
+                     "pass %d\n",
+                     ((struct ieee80211_hdr*)(skb->data))->seq_ctrl >> SSV_SEQ_NUM_SHIFT);
+#else
+        if ((ssv_sta_priv->ampdu_tid[tidno].mib.ampdu_mib_pass_counter % 1024) == 0)
+            prn_aggr_err(sc, "STA %d TID %d passed %d\n", ssv_sta_priv->sta_idx,
+                         ampdu_tid->tidno,
+                         ampdu_tid->mib.ampdu_mib_pass_counter);
+#endif
+        return false;
+    }
+#endif
+    mpdu_skb_info_p = (SKB_info *) (skb->head);
+    mpdu_skb_info_p->mpdu_retry_counter = 0;
+    mpdu_skb_info_p->ampdu_tx_status = AMPDU_ST_NON_AMPDU;
+    mpdu_skb_info_p->ampdu_tx_final_retry_count = 0;
+    mpdu_skb_info_p->directly_ack = false;
+    ssv_sta_priv->ampdu_tid[tidno].ac = skb_get_queue_mapping(skb);
+    ampdu_tx_frame = atomic_read(&sc->ampdu_tx_frame);
+    if ((sc->force_disable_directly_ack_tx != true) &&
+        (sc->sc_flags & SC_OP_DIRECTLY_ACK) &&
+        (ampdu_tx_frame < sc->directly_ack_high_threshold)) {
+        info = IEEE80211_SKB_CB(skb);
+        tx_skb = skb;
+        info->flags |= IEEE80211_TX_STAT_ACK;
+        copy_skb = skb_copy(tx_skb, GFP_ATOMIC);
+        if (!copy_skb) {
+            printk("create TX skb copy failed!\n");
+            return false;
+        }
+        ieee80211_tx_status(sc->hw, tx_skb);
+        skb = copy_skb;
+        copy_skb_info_p = (SKB_info *)(skb->head);
+        copy_skb_info_p->directly_ack = true;
+    } else {
+        sc->sc_flags &= ~SC_OP_DIRECTLY_ACK;
+    }
+    {
+        bool ret;
+        ret = ssv6200_ampdu_add_delimiter_and_crc32(skb);
+        if (ret == false) {
+            ssv6200_ampdu_release_skb(skb, hw);
+            return false;
+        }
+        skb_queue_tail(&ssv_sta_priv->ampdu_tid[tidno].ampdu_skb_tx_queue, skb);
+        atomic_inc(&sc->ampdu_tx_frame);
+        ssv_sta_priv->ampdu_tid[tidno].timestamp = jiffies;
+    }
+    _aggr_ampdu_tx_q(hw, &ssv_sta_priv->ampdu_tid[tidno]);
+    return true;
+}
+u32 ssv6xxx_ampdu_flush (struct ieee80211_hw *hw)
+{
+    struct ssv_softc *sc = hw->priv;
+    struct AMPDU_TID_st *cur_AMPDU_TID;
+    u32 flushed_ampdu = 0;
+    u32 tid_idx = 0;
+    if (!list_empty(&sc->tx.ampdu_tx_que)) {
+        list_for_each_entry_rcu(cur_AMPDU_TID, &sc->tx.ampdu_tx_que, list) {
+            tid_idx++;
+#ifdef DEBUG_AMPDU_FLUSH
+            {
+                int i = 0;
+                for (i = 0; i < MAX_TID; i++)
+                    if (sc->tid[i] == cur_AMPDU_TID)
+                        break;
+                if (i == MAX_TID) {
+                    printk(KERN_ERR "No matching TID (%d) found! %p\n", tid_idx, cur_AMPDU_TID);
+                    continue;
+                }
+            }
+#endif
+            if (cur_AMPDU_TID->state != AMPDU_STATE_OPERATION) {
+                struct ieee80211_sta *sta = cur_AMPDU_TID->sta;
+                struct ssv_sta_priv_data *sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+                dev_dbg(sc->dev, "STA %d TID %d is @%d\n",
+                        sta_priv->sta_idx, cur_AMPDU_TID->tidno,
+                        cur_AMPDU_TID->state);
+                continue;
+            }
+            if ((cur_AMPDU_TID->state == AMPDU_STATE_OPERATION)
+                && (skb_queue_len(&cur_AMPDU_TID->early_aggr_ampdu_q) == 0)
+                && (cur_AMPDU_TID->cur_ampdu_pkt != NULL)) {
+                struct ampdu_hdr_st *ampdu_hdr =
+                    (struct ampdu_hdr_st *) (cur_AMPDU_TID->cur_ampdu_pkt->head);
+                u32 aggr_len = skb_queue_len(&ampdu_hdr->mpdu_q);
+                if (aggr_len) {
+                    struct sk_buff *ampdu_skb = cur_AMPDU_TID->cur_ampdu_pkt;
+                    cur_AMPDU_TID->cur_ampdu_pkt = NULL;
+                    SSV_ADD_AMPDU_TXINFO(sc, ampdu_skb);
+                    _queue_early_ampdu(sc, cur_AMPDU_TID, ampdu_skb);
+#if 0
+                    prn_aggr_err(sc, "A%c %d %d\n", sc->tx_q_empty ? 'e' : 't',
+                                 ampdu_hdr->first_sn, aggr_len);
+#endif
+                }
+            }
+            if (skb_queue_len(&cur_AMPDU_TID->early_aggr_ampdu_q) > 0)
+                flushed_ampdu += _flush_early_ampdu_q(sc, cur_AMPDU_TID);
+        }
+    }
+    return flushed_ampdu;
+}
+int ssv6200_dump_BA_notification (char *buf,
+                                  struct ampdu_ba_notify_data *ba_notification)
+{
+    int i;
+    char *orig_buf = buf;
+    for (i = 0; i < MAX_AGGR_NUM; i++) {
+        if (ba_notification->seq_no[i] == (u16) (-1))
+            break;
+        buf += sprintf(buf, " %d", ba_notification->seq_no[i]);
+    }
+    return ((size_t)buf - (size_t)orig_buf);
+}
+int _dump_ba_skb (struct ssv_softc *sc, char *buf, int buf_size, struct sk_buff *ba_skb)
+{
+    struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) (ba_skb->data
+                                + sc->sh->rx_desc_len);
+    AMPDU_BLOCKACK *BA_frame = (AMPDU_BLOCKACK *) hdr;
+    u32 ssn = BA_frame->BA_ssn;
+    struct ampdu_ba_notify_data *ba_notification =
+        (struct ampdu_ba_notify_data *) (ba_skb->data + ba_skb->len
+                                         - sizeof(struct ampdu_ba_notify_data));
+    int prt_size;
+    prt_size = snprintf(buf, buf_size, "\n\t\t%04d %08X %08X -",
+                        ssn, BA_frame->BA_sn_bit_map[0], BA_frame->BA_sn_bit_map[1]);
+    buf_size -= prt_size;
+    buf += prt_size;
+    prt_size = prt_size + ssv6200_dump_BA_notification(buf, ba_notification);
+    return prt_size;
+}
+bool ssv6xxx_ssn_to_bit_idx (u32 start_ssn, u32 mpdu_ssn, u32 *word_idx,
+                             u32 *bit_idx)
+{
+    u32 ret_bit_idx, ret_word_idx = 0;
+    s32 diff = mpdu_ssn - start_ssn;
+    if (diff >= 0) {
+        if (diff >= SSV_AMPDU_BA_WINDOW_SIZE) {
+            return false;
+        }
+        ret_bit_idx = diff;
+    } else {
+        diff = -diff;
+        if (diff <= (SSV_AMPDU_MAX_SSN - SSV_AMPDU_BA_WINDOW_SIZE)) {
+            *word_idx = 0;
+            *bit_idx = 0;
+            return false;
+        }
+        ret_bit_idx = SSV_AMPDU_MAX_SSN - diff;
+    }
+    if (ret_bit_idx >= 32) {
+        ret_bit_idx -= 32;
+        ret_word_idx = 1;
+    }
+    *bit_idx = ret_bit_idx;
+    *word_idx = ret_word_idx;
+    return true;
+}
+bool ssv6xxx_inc_bit_idx (struct ssv_softc *sc, u32 ssn_1st, u32 ssn_next,
+                          u32 *word_idx, u32 *bit_idx)
+{
+    u32 ret_word_idx = *word_idx, ret_bit_idx = *bit_idx;
+    s32 diff = (s32) ssn_1st - (s32) ssn_next;
+    if (diff > 0) {
+        if (diff < (SSV_AMPDU_MAX_SSN - SSV_AMPDU_BA_WINDOW_SIZE)) {
+            prn_aggr_err(sc, "Irrational SN distance in AMPDU: %d %d.\n",
+                         ssn_1st, ssn_next);
+            return false;
+        }
+        diff = SSV_AMPDU_MAX_SSN - diff;
+    } else {
+        diff = -diff;
+    }
+    if (diff > SSV_AMPDU_MAX_SSN)
+        prn_aggr_err(sc, "DF %d - %d = %d\n", ssn_1st, ssn_next, diff);
+    ret_bit_idx += diff;
+    if (ret_bit_idx >= 32) {
+        ret_bit_idx -= 32;
+        ret_word_idx++;
+    }
+    *word_idx = ret_word_idx;
+    *bit_idx = ret_bit_idx;
+    return true;
+}
+void ssv6xxx_release_frames (struct AMPDU_TID_st *ampdu_tid)
+{
+    u32 head_ssn, head_ssn_before, last_ssn;
+    struct sk_buff **skb;
+    struct SKB_info_st *skb_info;
+    struct ssv_softc *sc = AMPDU_TID_TO_SC(ampdu_tid);
+    unsigned long flags;
+    spin_lock_irqsave(&ampdu_tid->pkt_array_lock, flags);
+    head_ssn_before = ampdu_tid->ssv_baw_head;
+#if 1
+    if (head_ssn_before >= SSV_AMPDU_MAX_SSN) {
+        spin_unlock_irqrestore(&ampdu_tid->pkt_array_lock, flags);
+        prn_aggr_err(sc, "l x.x %d\n", head_ssn_before);
+        return;
+    }
+#else
+    BUG_ON(head_ssn_before >= SSV_AMPDU_MAX_SSN);
+#endif
+    head_ssn = ampdu_tid->ssv_baw_head;
+    last_ssn = head_ssn;
+    do {
+        skb = &INDEX_PKT_BY_SSN(ampdu_tid, head_ssn);
+        if (*skb == NULL) {
+            head_ssn = SSV_ILLEGAL_SN;
+            {
+                int i;
+                char sn_str[66 * 5] = "";
+                char *str = sn_str;
+                for (i = 0; i < SSV_AMPDU_BA_WINDOW_SIZE; i++)
+                    if (ampdu_tid->aggr_pkts[i] != NULL) {
+                        str += sprintf(str, "%d ",
+                                       ampdu_skb_ssn(ampdu_tid->aggr_pkts[i]));
+                    }
+                *str = 0;
+                if (str == sn_str) {
+                } else
+                    prn_aggr_err(sc,
+                                 "ILL %d %d - %d (%s)\n",
+                                 head_ssn_before, last_ssn, ampdu_tid->aggr_pkt_num, sn_str);
+            }
+            break;
+        }
+        skb_info = (struct SKB_info_st *) ((*skb)->head);
+        if ((skb_info->ampdu_tx_status == AMPDU_ST_DONE)
+            || (skb_info->ampdu_tx_status == AMPDU_ST_DROPPED)) {
+            __skb_queue_tail(&ampdu_tid->release_queue, *skb);
+            *skb = NULL;
+            last_ssn = head_ssn;
+            INC_PKT_SN(head_ssn);
+            ampdu_tid->aggr_pkt_num--;
+            if (skb_info->ampdu_tx_status == AMPDU_ST_DROPPED)
+                ampdu_tid->mib.ampdu_mib_discard_counter++;
+        } else {
+            break;
+        }
+    } while (1);
+    ampdu_tid->ssv_baw_head = head_ssn;
+#if 0
+    if (head_ssn == SSV_ILLEGAL_SN) {
+        u32 i = head_ssn_before;
+        do {
+            skb = &INDEX_PKT_BY_SSN(ampdu_tid, i);
+            if (*skb != NULL)
+                prn_aggr_err(sc, "O.o %d: %d - %d\n", head_ssn_before, i, ampdu_skb_ssn(*skb));
+            INC_PKT_SN(i);
+        } while (i != head_ssn_before);
+    }
+#endif
+    spin_unlock_irqrestore(&ampdu_tid->pkt_array_lock, flags);
+#if 0
+    if (head_ssn_before != head_ssn) {
+        prn_aggr_err(sc, "H %d -> %d (%d - %d)\n", head_ssn_before, head_ssn,
+                     ampdu_tid->aggr_pkt_num, skb_queue_len(&ampdu_tid->ampdu_skb_tx_queue));
+    }
+#endif
+}
+static int _collect_retry_frames (struct AMPDU_TID_st *ampdu_tid)
+{
+    u16 ssn, head_ssn, end_ssn, diff;
+    int num_retry = 0;
+    int timeout_check = 1;
+    unsigned long check_jiffies = jiffies;
+    struct ssv_softc *sc = AMPDU_TID_TO_SC(ampdu_tid);
+    head_ssn = ampdu_tid->ssv_baw_head;
+    ssn = head_ssn;
+    if (ssn == SSV_ILLEGAL_SN)
+        return 0;
+    end_ssn = (head_ssn + SSV_AMPDU_BA_WINDOW_SIZE) % SSV_AMPDU_MAX_SSN;
+    do {
+        struct sk_buff *skb = INDEX_PKT_BY_SSN(ampdu_tid, ssn);
+        struct SKB_info_st *skb_info;
+        int timeout_retry = 0;
+        if (skb == NULL) {
+            INC_PKT_SN(ssn);
+            continue;
+        }
+        skb_info = (SKB_info *) (skb->head);
+        if ( timeout_check
+             && (skb_info->ampdu_tx_status == AMPDU_ST_SENT)) {
+            unsigned long cur_jiffies = jiffies;
+            unsigned long timeout_jiffies = skb_info->aggr_timestamp
+                                            + msecs_to_jiffies(BA_WAIT_TIMEOUT);
+            u32 delta_ms;
+            if (time_before(cur_jiffies, timeout_jiffies)) {
+                timeout_check = 0;
+                continue;
+            }
+            ssv6xxx_mark_skb_retry(sc, skb_info, skb);
+            delta_ms = jiffies_to_msecs((long)(cur_jiffies - skb_info->aggr_timestamp));
+            prn_aggr_err(sc, "t S%d-T%d-%d (%u)\n",
+                         ((struct ssv_sta_priv_data *)skb_info->sta->drv_priv)->sta_idx,
+                         ampdu_tid->tidno, ssn,
+                         delta_ms);
+            if (delta_ms > 1000) {
+                prn_aggr_err(sc, "Last checktime %lu - %lu = %u, cur jiffies %lu \n",
+                             check_jiffies, skb_info->aggr_timestamp,
+                             jiffies_to_msecs((long)(check_jiffies - skb_info->aggr_timestamp)), cur_jiffies);
+            }
+            timeout_retry = 1;
+        }
+        diff = SSV_AMPDU_SN_a_minus_b(head_ssn, ssn);
+        if (diff > ampdu_tid->ssv_baw_size) {
+            prn_aggr_dbg(sc, "Z. release skb (s %d, h %d, d %d)\n", ssn, head_ssn, diff);
+            skb_info->ampdu_tx_status = AMPDU_ST_DROPPED;
+        }
+        if (skb_info->ampdu_tx_status == AMPDU_ST_RETRY) {
+#if 0
+            if (!timeout_retry)
+                prn_aggr_dbg(sc, "r %d - %d\n", ssn, ampdu_skb_ssn(skb));
+#endif
+            skb_info->ampdu_tx_status = AMPDU_ST_RETRY_Q;
+            skb_queue_tail(&ampdu_tid->retry_queue, skb);
+            ampdu_tid->mib.ampdu_mib_retry_counter++;
+            num_retry++;
+        }
+        INC_PKT_SN(ssn);
+    } while (ssn != end_ssn);
+    ampdu_tid->timestamp = check_jiffies;
+    return num_retry;
+}
+void ssv6xxx_mark_skb_retry (struct ssv_softc *sc, struct SKB_info_st *skb_info, struct sk_buff *skb)
+{
+    struct SKB_info_st *mpdu_skb_info_p = (SKB_info *) (skb->head);
+    struct ieee80211_sta *sta = mpdu_skb_info_p->sta;
+    struct ssv_sta_priv_data *ssv_sta_priv = (struct ssv_sta_priv_data *) sta->drv_priv;
+    if (skb_info->ampdu_tx_status == AMPDU_ST_SENT) {
+        if (skb_info->mpdu_retry_counter == 0) {
+            struct ieee80211_hdr *skb_hdr = ampdu_skb_hdr(skb);
+            skb_hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
+        }
+        skb_info->ampdu_tx_status = AMPDU_ST_RETRY;
+        ssv_sta_priv->retry_samples[skb_info->mpdu_retry_counter]++;
+        skb_info->mpdu_retry_counter++;
+        if (skb_info->mpdu_retry_counter >= SSV_AMPDU_retry_counter_max) {
+            skb_info->ampdu_tx_status = AMPDU_ST_DROPPED;
+        }
+    }
+}
+void ssv6xxx_find_txpktrun_no_from_ssn(struct ssv_softc *sc, u32 ssn,
+                                       struct ssv_sta_priv_data *ssv_sta_priv)
+{
+    u32 i, j;
+    u8 slot;
+    for (i = 0; i < MAX_CONCUR_AMPDU; i ++) {
+        if (ssv_sta_priv->ampdu_ssn[i].mpdu_num != 0) {
+            for (j = 0 ; j < ssv_sta_priv->ampdu_ssn[i].mpdu_num; j++) {
+                if (ssv_sta_priv->ampdu_ssn[i].ssn[j] == ssn) {
+                    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_AMPDU_SSN,
+                             "==>%s: found new acked ssn %d, tx_pkt_run_no %d at slot %d \n", __func__
+                             , ssn,ssv_sta_priv->ampdu_ssn[i].tx_pkt_run_no, i);
+                    slot = i;
+                    goto out;
+                }
+            }
+        }
+    }
+out:
+    if ( i != MAX_CONCUR_AMPDU) {
+        memset((void*)&ssv_sta_priv->ampdu_ssn[slot], 0, sizeof(struct aggr_ssn));
+        dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_AMPDU_SSN,"%s: slot %d released!\n", __func__, slot);
+    } else {
+        dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_AMPDU_SSN,"%s: not found tx_pkt_run_no for this ssn %s\n", __func__, ssn);
+    }
+}
+u32 ssv6200_ba_map_walker (struct AMPDU_TID_st *ampdu_tid, u32 start_ssn,
+                           u32 sn_bit_map[2],
+                           struct ampdu_ba_notify_data *ba_notify_data,
+                           u32 *p_acked_num)
+{
+    int i = 0;
+    u32 ssn = ba_notify_data->seq_no[0];
+    u32 word_idx = (-1), bit_idx = (-1);
+    bool found = ssv6xxx_ssn_to_bit_idx(start_ssn, ssn, &word_idx, &bit_idx);
+    bool first_found = found;
+    u32 aggr_num = 0;
+    u32 acked_num = 0;
+    struct ssv_softc *sc = AMPDU_TID_TO_SC(ampdu_tid);
+    if (found && (word_idx >= 2 || bit_idx >= 32))
+        prn_aggr_err(sc, "idx error 1: %d %d %d %d\n",
+                     start_ssn, ssn, word_idx, bit_idx);
+    while ((i < MAX_AGGR_NUM) && (ssn < SSV_AMPDU_MAX_SSN)) {
+        u32 cur_ssn;
+        struct sk_buff *skb = INDEX_PKT_BY_SSN(ampdu_tid, ssn);
+        u32 skb_ssn = (skb == NULL) ? (-1) : ampdu_skb_ssn(skb);
+        struct SKB_info_st *skb_info;
+        aggr_num++;
+        if (skb_ssn != ssn) {
+            prn_aggr_err(sc, "Unmatched SSN packet: %d - %d - %d\n",
+                         ssn, skb_ssn, start_ssn);
+        } else {
+            skb_info = (struct SKB_info_st *) (skb->head);
+            if (found && (sn_bit_map[word_idx] & (1 << bit_idx))) {
+                if (skb_info->ampdu_tx_status == AMPDU_ST_SENT) {
+                    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_AMPDU_SSN,"%s: mark ssn %d done\n", __func__, ssn);
+                    skb_info->ampdu_tx_status = AMPDU_ST_DONE;
+                } else {
+                    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_AMPDU_SSN,"%s: Find a MPDU of status %d! ssn %d\n",
+                             __func__, skb_info->ampdu_tx_status, ssn);
+                }
+                acked_num++;
+            } else {
+                if (skb_info->ampdu_tx_status == AMPDU_ST_SENT) {
+                    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_AMPDU_SSN,"%s: mark ssn %d retry\n", __func__, ssn);
+                    ssv6xxx_mark_skb_retry(sc, skb_info, skb);
+                } else {
+                    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_AMPDU_SSN,"%s: Find a MPDU of status %d! ssn %d\n",
+                             __func__, skb_info->ampdu_tx_status, ssn);
+                }
+            }
+        }
+        cur_ssn = ssn;
+        if (++i >= MAX_AGGR_NUM)
+            break;
+        ssn = ba_notify_data->seq_no[i];
+        if (ssn >= SSV_AMPDU_MAX_SSN)
+            break;
+        if (first_found) {
+            u32 old_word_idx, old_bit_idx;
+            old_word_idx = word_idx;
+            old_bit_idx = bit_idx;
+            found = ssv6xxx_inc_bit_idx(sc, cur_ssn, ssn, &word_idx, &bit_idx);
+            if (found && (word_idx >= 2 || bit_idx >= 32)) {
+                prn_aggr_err(sc,
+                             "idx error 2: %d 0x%08X 0X%08X %d %d (%d %d) (%d %d)\n",
+                             start_ssn, sn_bit_map[1], sn_bit_map[0], cur_ssn, ssn, word_idx, bit_idx, old_word_idx, old_bit_idx);
+                found = false;
+            } else if (!found) {
+                char strbuf[256];
+                ssv6200_dump_BA_notification(strbuf, ba_notify_data);
+                prn_aggr_err(sc, "SN out-of-order: %d\n%s\n", start_ssn, strbuf);
+            }
+        } else {
+            found = ssv6xxx_ssn_to_bit_idx(start_ssn, ssn, &word_idx, &bit_idx);
+            first_found = found;
+            if (found && (word_idx >= 2 || bit_idx >= 32))
+                prn_aggr_err(sc, "idx error 3: %d %d %d %d\n",
+                             cur_ssn, ssn, word_idx, bit_idx);
+        }
+    }
+    ssv6xxx_release_frames(ampdu_tid);
+    if (p_acked_num != NULL)
+        *p_acked_num = acked_num;
+    return aggr_num;
+}
+static void _flush_release_queue (struct ieee80211_hw *hw,
+                                  struct sk_buff_head *release_queue)
+{
+    struct ssv_softc *sc = hw->priv;
+    int ampdu_tx_frame = 0;
+    do {
+        struct sk_buff *ampdu_skb = __skb_dequeue(release_queue);
+        struct ieee80211_tx_info *tx_info;
+        struct SKB_info_st *skb_info;
+        if (ampdu_skb == NULL)
+            break;
+        skb_info = (struct SKB_info_st *) (ampdu_skb->head);
+        skb_pull(ampdu_skb, AMPDU_DELIMITER_LEN);
+        tx_info = IEEE80211_SKB_CB(ampdu_skb);
+        ieee80211_tx_info_clear_status(tx_info);
+        tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
+        if (skb_info->ampdu_tx_status == AMPDU_ST_DONE)
+            tx_info->flags |= IEEE80211_TX_STAT_ACK;
+        tx_info->status.ampdu_len = 1;
+        tx_info->status.ampdu_ack_len = 1;
+        if (skb_info->directly_ack) {
+            dev_kfree_skb_any(ampdu_skb);
+        } else {
+#if defined(USE_THREAD_RX) && !defined(IRQ_PROC_TX_DATA)
+            ieee80211_tx_status(hw, ampdu_skb);
+#else
+            ieee80211_tx_status_irqsafe(hw, ampdu_skb);
+#endif
+        }
+        ampdu_tx_frame = atomic_sub_return(1, &sc->ampdu_tx_frame);
+        if (ampdu_tx_frame < sc->directly_ack_low_threshold)
+            sc->sc_flags |= SC_OP_DIRECTLY_ACK;
+    } while (1);
+}
+#if 0
+static u16 _get_BA_notification_hits(u16 ssn,u32 *bit_map,struct ampdu_ba_notify_data *ba_notification,u16 *max_continue_hits,u16 *aggr_num)
+{
+    int i;
+    u16 hits=0,continue_hits=0;
+    u64 bitMap=0;
+    if(bit_map)
+        bitMap = ((u64)bit_map[1]<<32) | (u64)(bit_map[0]);
+    for (i = 0; i < MAX_AGGR_NUM; i++) {
+        if (ba_notification->seq_no[i] == (u16)(-1))
+            break;
+        if(ssn <= ba_notification->seq_no[i]) {
+            if((bitMap>>(ba_notification->seq_no[i]-ssn))&0x1) {
+                hits++;
+                continue_hits++;
+                if(*max_continue_hits<=continue_hits)
+                    *max_continue_hits = continue_hits;
+            } else {
+                continue_hits=0;
+            }
+        }
+    }
+    *aggr_num = i;
+    return hits;
+}
+#endif
+void ssv6200_ampdu_no_BA_handler (struct ieee80211_hw *hw, struct sk_buff *skb)
+{
+    struct cfg_host_event *host_event = (struct cfg_host_event *) skb->data;
+    struct ampdu_ba_notify_data *ba_notification =
+        (struct ampdu_ba_notify_data *) &host_event->dat[0];
+    struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) (ba_notification + 1);
+    struct ssv_softc *sc = hw->priv;
+    struct ieee80211_sta *sta = ssv6xxx_find_sta_by_addr(sc, hdr->addr1);
+    u8 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
+    struct ssv_sta_priv_data *ssv_sta_priv;
+    char seq_str[256];
+    struct AMPDU_TID_st *ampdu_tid;
+    int i;
+    u16 aggr_num = 0;
+    struct firmware_rate_control_report_data *report_data;
+    if (sta == NULL) {
+        prn_aggr_err(sc,
+                     "NO BA for %d to unmatched STA %02X-%02X-%02X-%02X-%02X-%02X: %s\n",
+                     tidno, hdr->addr1[0], hdr->addr1[1], hdr->addr1[2], hdr->addr1[3], hdr->addr1[4], hdr->addr1[5], seq_str);
+        dev_kfree_skb_any(skb);
+        return;
+    }
+    ssv_sta_priv = (struct ssv_sta_priv_data *) sta->drv_priv;
+    down_read(&sc->sta_info_sem);
+    if ((ssv_sta_priv->sta_info->s_flags & STA_FLAG_VALID) == 0) {
+        up_read(&sc->sta_info_sem);
+        prn_aggr_err(sc, "%s(): sta_info is gone.\n", __func__);
+        dev_kfree_skb_any(skb);
+        return;
+    }
+    ssv6200_dump_BA_notification(seq_str, ba_notification);
+    ssv6xxx_find_txpktrun_no_from_ssn(sc, ba_notification->seq_no[0], ssv_sta_priv);
+    prn_aggr_err(sc,
+                 "NO BA for %d to %02X-%02X-%02X-%02X-%02X-%02X: %s\n",
+                 tidno, sta->addr[0], sta->addr[1], sta->addr[2], sta->addr[3], sta->addr[4], sta->addr[5], seq_str);
+    ampdu_tid = &ssv_sta_priv->ampdu_tid[tidno];
+    if (ampdu_tid->state != AMPDU_STATE_OPERATION) {
+        up_read(&sc->sta_info_sem);
+        dev_kfree_skb_any(skb);
+        return;
+    }
+    for (i = 0; i < MAX_AGGR_NUM; i++) {
+        u32 ssn = ba_notification->seq_no[i];
+        struct sk_buff *skb;
+        u32 skb_ssn;
+        struct SKB_info_st *skb_info;
+        if (ssn >= (4096))
+            break;
+        aggr_num++;
+        skb = INDEX_PKT_BY_SSN(ampdu_tid, ssn);
+        skb_ssn = (skb == NULL) ? (-1) : ampdu_skb_ssn(skb);
+        if (skb_ssn != ssn) {
+            prn_aggr_err(sc, "Unmatched SSN packet: %d - %d\n", ssn, skb_ssn);
+            continue;
+        }
+        skb_info = (struct SKB_info_st *) (skb->head);
+        if (skb_info->ampdu_tx_status == AMPDU_ST_SENT) {
+            if (skb_info->mpdu_retry_counter < SSV_AMPDU_retry_counter_max) {
+                if (skb_info->mpdu_retry_counter == 0) {
+                    struct ieee80211_hdr *skb_hdr = ampdu_skb_hdr(skb);
+                    skb_hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
+                }
+                skb_info->ampdu_tx_status = AMPDU_ST_RETRY;
+                ssv_sta_priv->retry_samples[skb_info->mpdu_retry_counter]++;
+                skb_info->mpdu_retry_counter++;
+            } else {
+                skb_info->ampdu_tx_status = AMPDU_ST_DROPPED;
+                prn_aggr_err(sc, "p %d\n", skb_ssn);
+            }
+        } else {
+            prn_aggr_err(sc, "S %d %d\n", skb_ssn, skb_info->ampdu_tx_status);
+        }
+    }
+    ssv6xxx_release_frames(ampdu_tid);
+    host_event->h_event = SOC_EVT_RC_AMPDU_REPORT;
+    report_data =
+        (struct firmware_rate_control_report_data *) &host_event->dat[0];
+    report_data->ampdu_len = aggr_num;
+    report_data->ampdu_ack_len = 0;
+    report_data->wsid = ssv_sta_priv->sta_info->hw_wsid;
+#if 0
+    printk("AMPDU report NO BA!!wsid[%d]didx[%d]F[%d]R[%d]S[%d]\n",report_data->wsid,report_data->data_rate,report_data->mpduFrames,report_data->mpduFrameRetry,report_data->mpduFrameSuccess);
+#endif
+    skb_queue_tail(&sc->rc_report_queue, skb);
+    if (sc->rc_report_sechedule == 0)
+        queue_work(sc->rc_report_workqueue, &sc->rc_report_work);
+    up_read(&sc->sta_info_sem);
+}
+#ifndef SSV_SUPPORT_HAL
+void ssv6200_ampdu_BA_handler (struct ieee80211_hw *hw, struct sk_buff *skb)
+{
+    struct ssv_softc *sc = hw->priv;
+    struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) (skb->data
+                                + sc->sh->rx_desc_len);
+    AMPDU_BLOCKACK *BA_frame = (AMPDU_BLOCKACK *) hdr;
+    struct ieee80211_sta *sta;
+    struct ssv_sta_priv_data *ssv_sta_priv;
+    struct ampdu_ba_notify_data *ba_notification;
+    u32 ssn, aggr_num = 0, acked_num = 0;
+    u8 tid_no;
+    u32 sn_bit_map[2];
+    struct firmware_rate_control_report_data *report_data;
+    HDR_HostEvent *host_evt;
+    sta = ssv6xxx_find_sta_by_rx_skb(sc, skb);
+    if (sta == NULL) {
+        if (skb->len > AMPDU_BA_FRAME_LEN) {
+            char strbuf[256];
+            struct ampdu_ba_notify_data *ba_notification =
+                (struct ampdu_ba_notify_data *) (skb->data + skb->len
+                                                 - sizeof(struct ampdu_ba_notify_data));
+            ssv6200_dump_BA_notification(strbuf, ba_notification);
+            prn_aggr_err(sc, "BA from not connected STA (%02X-%02X-%02X-%02X-%02X-%02X) (%s)\n",
+                         BA_frame->ta_addr[0], BA_frame->ta_addr[1], BA_frame->ta_addr[2],
+                         BA_frame->ta_addr[3], BA_frame->ta_addr[4], BA_frame->ta_addr[5], strbuf);
+        }
+        dev_kfree_skb_any(skb);
+        return;
+    }
+    ssv_sta_priv = (struct ssv_sta_priv_data *) sta->drv_priv;
+    ssn = BA_frame->BA_ssn;
+    sn_bit_map[0] = BA_frame->BA_sn_bit_map[0];
+    sn_bit_map[1] = BA_frame->BA_sn_bit_map[1];
+    tid_no = BA_frame->tid_info;
+    ssv_sta_priv->ampdu_mib_total_BA_counter++;
+    if (ssv_sta_priv->ampdu_tid[tid_no].state == AMPDU_STATE_STOP) {
+        prn_aggr_err(sc, "ssv6200_ampdu_BA_handler state == AMPDU_STATE_STOP.\n");
+        dev_kfree_skb_any(skb);
+        return;
+    }
+    ssv_sta_priv->ampdu_tid[tid_no].mib.ampdu_mib_BA_counter++;
+    if (skb->len <= AMPDU_BA_FRAME_LEN) {
+        prn_aggr_err(sc, "b %d\n", ssn);
+        dev_kfree_skb_any(skb);
+        return;
+    }
+    ba_notification =
+        (struct ampdu_ba_notify_data *) (skb->data + skb->len
+                                         - sizeof(struct ampdu_ba_notify_data));
+    ssv6xxx_find_txpktrun_no_from_ssn(sc, ba_notification->seq_no[0], ssv_sta_priv);
+#if 0
+    if (1) {
+        char strbuf[256];
+        ssv6200_dump_BA_notification(strbuf, ba_notification);
+        prn_aggr_err(sc, "B %d %08X %08X: %s\n", ssn, sn_bit_map[0], sn_bit_map[1], strbuf);
+    }
+#endif
+    aggr_num = ssv6200_ba_map_walker(&(ssv_sta_priv->ampdu_tid[tid_no]), ssn,
+                                     sn_bit_map, ba_notification, &acked_num);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+    if (ssv_sta_priv->ampdu_tid[tid_no].debugfs_dir) {
+        struct sk_buff *dup_skb;
+        if (skb_queue_len(&ssv_sta_priv->ampdu_tid[tid_no].ba_q) > 24) {
+            struct sk_buff *ba_skb = skb_dequeue(&ssv_sta_priv->ampdu_tid[tid_no].ba_q);
+            if (ba_skb)
+                dev_kfree_skb_any(ba_skb);
+        }
+        dup_skb = skb_clone(skb, GFP_ATOMIC);
+        if (dup_skb)
+            skb_queue_tail(&ssv_sta_priv->ampdu_tid[tid_no].ba_q, dup_skb);
+    }
+#endif
+    skb_trim(skb, skb->len - sizeof(struct ampdu_ba_notify_data));
+#if 0
+    total_debug_count++;
+    if (ba_notification_hits != ba_notification_aggr_num)
+        printk("rate[%d] firmware retry [%d] agg nums[%d] hits[%d] continue_hits[%d] \n",ba_notification.data_rate,ba_notification.retry_count,ba_notification_aggr_num,ba_notification_hits,ba_notification_continue_hits);
+    else {
+        if (ba_notification.retry_count==0)
+            total_perfect_debug_count++;
+        else
+            total_perfect_debug_count_but_firmware_retry++;
+    }
+    if ((total_debug_count % 2000) == 0) {
+        printk("Percentage %d/2000\n",total_perfect_debug_count);
+        printk("firmware retry [%d] no BA[%d]\n",total_perfect_debug_count_but_firmware_retry,no_ba_debug_count);
+        total_debug_count = 0;
+        total_perfect_debug_count_but_firmware_retry=0;
+        total_perfect_debug_count = 0;
+        no_ba_debug_count = 0;
+    }
+#endif
+    host_evt = (HDR_HostEvent *) skb->data;
+    host_evt->h_event = SOC_EVT_RC_AMPDU_REPORT;
+    report_data =
+        (struct firmware_rate_control_report_data *) &host_evt->dat[0];
+    memcpy(report_data, ba_notification,
+           sizeof(struct firmware_rate_control_report_data));
+    report_data->ampdu_len = aggr_num;
+    report_data->ampdu_ack_len = acked_num;
+#ifdef RATE_CONTROL_HT_PERCENTAGE_TRACE
+    if((acked_num) && (acked_num != aggr_num)) {
+        int i;
+        for (i = 0; i < SSV62XX_TX_MAX_RATES ; i++) {
+            if(report_data->rates[i].data_rate == -1)
+                break;
+            if(report_data->rates[i].count == 0) {
+                printk("*********************************\n");
+                printk("       Illegal HT report         \n");
+                printk("*********************************\n");
+            }
+            printk("        i=[%d] rate[%d] count[%d]\n",i,report_data->rates[i].data_rate,report_data->rates[i].count);
+        }
+        printk("AMPDU percentage = %d%% \n",acked_num*100/aggr_num);
+    } else if(acked_num == 0) {
+        printk("AMPDU percentage = 0%% aggr_num=%d acked_num=%d\n",aggr_num,acked_num);
+    }
+#endif
+    skb_queue_tail(&sc->rc_report_queue, skb);
+    if (sc->rc_report_sechedule == 0)
+        queue_work(sc->rc_report_workqueue, &sc->rc_report_work);
+}
+#endif
+static void _postprocess_BA (struct ssv_softc *sc, struct ssv_sta_info *sta_info, void *param)
+{
+    int j;
+    struct ssv_sta_priv_data *ssv_sta_priv;
+    if ( (sta_info->sta == NULL)
+         || ((sta_info->s_flags & STA_FLAG_VALID) == 0))
+        return;
+    ssv_sta_priv = (struct ssv_sta_priv_data *) sta_info->sta->drv_priv;
+    for (j = 0; j < WMM_TID_NUM; j++) {
+        AMPDU_TID *ampdu_tid = &ssv_sta_priv->ampdu_tid[j];
+        if (ampdu_tid->state != AMPDU_STATE_OPERATION)
+            continue;
+        _collect_retry_frames(ampdu_tid);
+        ssv6200_ampdu_send_retry(sc->hw, ampdu_tid, &ampdu_tid->retry_queue, true);
+        _flush_early_ampdu_q(sc, ampdu_tid);
+        _flush_release_queue(sc->hw, &ampdu_tid->release_queue);
+    }
+}
+void ssv6xxx_ampdu_postprocess_BA (struct ieee80211_hw *hw)
+{
+    struct ssv_softc *sc = hw->priv;
+    ssv6xxx_foreach_sta(sc, _postprocess_BA, NULL);
+}
+#ifndef SSV_SUPPORT_HAL
+static void ssv6200_hw_set_rx_ba_session (struct ssv_hw *sh, bool on, u8 *ta,
+        u16 tid, u16 ssn, u8 buf_size)
+{
+    if (on) {
+        u32 u32ta;
+        u32ta = 0;
+        u32ta |= (ta[0] & 0xff) << (8 * 0);
+        u32ta |= (ta[1] & 0xff) << (8 * 1);
+        u32ta |= (ta[2] & 0xff) << (8 * 2);
+        u32ta |= (ta[3] & 0xff) << (8 * 3);
+        SMAC_REG_WRITE(sh, ADR_BA_TA_0, u32ta);
+        u32ta = 0;
+        u32ta |= (ta[4] & 0xff) << (8 * 0);
+        u32ta |= (ta[5] & 0xff) << (8 * 1);
+        SMAC_REG_WRITE(sh, ADR_BA_TA_1, u32ta);
+        SMAC_REG_WRITE(sh, ADR_BA_TID, tid);
+        SMAC_REG_WRITE(sh, ADR_BA_ST_SEQ, ssn);
+        SMAC_REG_WRITE(sh, ADR_BA_SB0, 0);
+        SMAC_REG_WRITE(sh, ADR_BA_SB1, 0);
+        SMAC_REG_WRITE(sh, ADR_BA_CTRL,
+                       (1 << BA_AGRE_EN_SFT)| (3 << BA_CTRL_SFT));
+    } else {
+        SMAC_REG_WRITE(sh, ADR_BA_CTRL, 0x0);
+    }
+}
+#endif
+void ssv6xxx_set_ampdu_rx_add_work (struct work_struct *work)
+{
+    struct ssv_softc
+    *sc = container_of(work, struct ssv_softc, set_ampdu_rx_add_work);
+    SSV_SET_RX_BA(sc->sh, true, sc->ba_ra_addr, sc->ba_tid, sc->ba_ssn, 64);
+}
+void ssv6xxx_set_ampdu_rx_del_work (struct work_struct *work)
+{
+    struct ssv_softc*sc = container_of(work, struct ssv_softc,
+                                       set_ampdu_rx_del_work);
+    u8 addr[6] = { 0 };
+    SSV_SET_RX_BA(sc->sh, false, addr, 0, 0, 0);
+}
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+static void _reset_ampdu_mib (struct ssv_softc *sc, struct ssv_sta_info *sta_info, void *param)
+{
+    struct ieee80211_sta *sta = sta_info->sta;
+    struct ssv_sta_priv_data *ssv_sta_priv;
+    int i;
+    ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+    for (i = 0; i < WMM_TID_NUM; i++) {
+        ssv_sta_priv->ampdu_tid[i].ampdu_mib_reset = 1;
+    }
+}
+void ssv6xxx_ampdu_mib_reset (struct ieee80211_hw *hw)
+{
+    struct ssv_softc *sc = hw->priv;
+    if (sc == NULL)
+        return;
+    ssv6xxx_foreach_sta(sc, _reset_ampdu_mib, NULL);
+}
+ssize_t ampdu_tx_mib_dump (struct ssv_sta_priv_data *ssv_sta_priv,
+                           char *mib_str, ssize_t length)
+{
+    ssize_t buf_size = length;
+    ssize_t prt_size;
+    int j;
+    struct ssv_softc *sc;
+    struct ssv_sta_info *ssv_sta = ssv_sta_priv->sta_info, *first_ssv_sta;
+    first_ssv_sta = ssv_sta - ssv_sta_priv->sta_idx;
+    sc = container_of(first_ssv_sta, struct ssv_softc, sta_info[0]);
+    down_read(&sc->sta_info_sem);
+    if ((ssv_sta->s_flags & STA_FLAG_VALID) == 0) {
+        goto mib_dump_exit;
+    }
+    if (ssv_sta->sta == NULL) {
+        prt_size = snprintf(mib_str, buf_size, "\n    NULL STA.\n");
+        mib_str += prt_size;
+        buf_size -= prt_size;
+        goto mib_dump_exit;
+    }
+    for (j = 0; j < WMM_TID_NUM; j++) {
+        int k;
+        struct AMPDU_TID_st *ampdu_tid = &ssv_sta_priv->ampdu_tid[j];
+        struct AMPDU_MIB_st *ampdu_mib = &ampdu_tid->mib;
+        prt_size = snprintf(mib_str, buf_size, "\n    WMM_TID %d@%d\n", j,
+                            ampdu_tid->state);
+        mib_str += prt_size;
+        buf_size -= prt_size;
+        if (ampdu_tid->state != AMPDU_STATE_OPERATION)
+            continue;
+        prt_size = snprintf(mib_str, buf_size, "        BA window size: %d\n",
+                            ampdu_tid->ssv_baw_size);
+        mib_str += prt_size;
+        buf_size -= prt_size;
+        prt_size = snprintf(mib_str, buf_size, "        BA window head: %d\n",
+                            ampdu_tid->ssv_baw_head);
+        mib_str += prt_size;
+        buf_size -= prt_size;
+        prt_size = snprintf(mib_str, buf_size,
+                            "        Sending aggregated #: %d\n",
+                            ampdu_tid->aggr_pkt_num);
+        mib_str += prt_size;
+        buf_size -= prt_size;
+        prt_size = snprintf(
+                       mib_str, buf_size, "        Waiting #: %d\n",
+                       skb_queue_len(&ampdu_tid->ampdu_skb_tx_queue));
+        mib_str += prt_size;
+        buf_size -= prt_size;
+        prt_size = snprintf(mib_str, buf_size, "        Early aggregated %d\n",
+                            ampdu_tid->early_aggr_skb_num);
+        mib_str += prt_size;
+        buf_size -= prt_size;
+        prt_size = snprintf(mib_str, buf_size,
+                            "        MPDU: %d\n",
+                            ampdu_mib->ampdu_mib_mpdu_counter);
+        mib_str += prt_size;
+        buf_size -= prt_size;
+        prt_size = snprintf(mib_str, buf_size,
+                            "        Passed: %d\n", ampdu_mib->ampdu_mib_pass_counter);
+        mib_str += prt_size;
+        buf_size -= prt_size;
+        prt_size = snprintf(mib_str, buf_size,
+                            "        Retry: %d\n",
+                            ampdu_mib->ampdu_mib_retry_counter);
+        mib_str += prt_size;
+        buf_size -= prt_size;
+        prt_size = snprintf(mib_str, buf_size,
+                            "        AMPDU: %d\n",
+                            ampdu_mib->ampdu_mib_ampdu_counter);
+        mib_str += prt_size;
+        buf_size -= prt_size;
+        prt_size = snprintf(mib_str, buf_size,
+                            "        Retry AMPDU: %d\n",
+                            ampdu_mib->ampdu_mib_aggr_retry_counter);
+        mib_str += prt_size;
+        buf_size -= prt_size;
+        prt_size = snprintf(mib_str, buf_size,
+                            "        BAR count: %d\n",
+                            ampdu_mib->ampdu_mib_bar_counter);
+        mib_str += prt_size;
+        buf_size -= prt_size;
+        prt_size = snprintf(mib_str, buf_size,
+                            "        Discard count: %d\n",
+                            ampdu_mib->ampdu_mib_discard_counter);
+        mib_str += prt_size;
+        buf_size -= prt_size;
+        prt_size = snprintf(mib_str, buf_size,
+                            "        BA count: %d\n",
+                            ampdu_mib->ampdu_mib_BA_counter);
+        mib_str += prt_size;
+        buf_size -= prt_size;
+        prt_size = snprintf(mib_str, buf_size, "        Total BA count: %d\n",
+                            ssv_sta_priv->ampdu_mib_total_BA_counter);
+        mib_str += prt_size;
+        buf_size -= prt_size;
+        prt_size = snprintf(mib_str, buf_size, "        Aggr # count:\n");
+        mib_str += prt_size;
+        buf_size -= prt_size;
+        for (k = 0; k <= SSV_AMPDU_aggr_num_max; k++) {
+            prt_size = snprintf(mib_str, buf_size, "            %d: %d\n", k,
+                                ampdu_mib->ampdu_mib_dist[k]);
+            mib_str += prt_size;
+            buf_size -= prt_size;
+        }
+    }
+mib_dump_exit:
+    up_read(&sc->sta_info_sem);
+    return (length - buf_size);
+}
+#endif
+#if 0
+static void _dump_ampdu_mib (struct ssv_softc *sc, struct ssv_sta_info *sta_info, void *param)
+{
+    struct mib_dump_data *dump_data = (struct mib_dump_data *)param;
+    struct ieee80211_sta *sta;
+    struct ssv_sta_priv_data *ssv_sta_priv;
+    ssize_t buf_size;
+    ssize_t prt_size;
+    char *mib_str = dump_data->prt_buff;
+    if (param == NULL)
+        return;
+    buf_size = dump_data->buff_size - 1;
+    sta = sta_info->sta;
+    if ((sta == NULL) || ((sta_info->s_flags & STA_FLAG_VALID) == 0))
+        return;
+    prt_size = snprintf(mib_str, buf_size,
+                        "STA: %02X-%02X-%02X-%02X-%02X-%02X:\n",
+                        sta->addr[0], sta->addr[1], sta->addr[2],
+                        sta->addr[3], sta->addr[4], sta->addr[5]);
+    mib_str += prt_size;
+    buf_size -= prt_size;
+    ssv_sta_priv = (struct ssv_sta_priv_data *) sta->drv_priv;
+    prt_size = ampdu_tx_mib_dump(ssv_sta_priv, mib_str, buf_size);
+    mib_str += prt_size;
+    buf_size -= prt_size;
+    dump_data->prt_len = (dump_data->buff_size - 1 - buf_size);
+    dump_data->prt_buff = mib_str;
+    dump_data->buff_size = buf_size;
+}
+ssize_t ssv6xxx_ampdu_mib_dump (struct ieee80211_hw *hw, char *mib_str,
+                                ssize_t length)
+{
+    struct ssv_softc *sc = hw->priv;
+    ssize_t buf_size = length - 1;
+    struct mib_dump_data dump_data = {mib_str, buf_size, 0};
+    if (sc == NULL)
+        return 0;
+    ssv6xxx_foreach_sta(sc, _dump_ampdu_mib, &dump_data);
+    return dump_data.prt_len;
+}
+#endif
+struct sk_buff *_alloc_ampdu_skb (struct ssv_softc *sc, struct AMPDU_TID_st *ampdu_tid, u32 len)
+{
+    unsigned char *payload_addr;
+    u32 headroom = sc->hw->extra_tx_headroom;
+    u32 offset;
+    struct ssv_sta_priv_data *ssv_sta_priv = (struct ssv_sta_priv_data *)ampdu_tid->sta->drv_priv;
+    u32 cur_max_ampdu_size = ssv_sta_priv->max_ampdu_size;
+    u32 extra_room = sc->sh->tx_desc_len * 2 + 48;
+    u32 max_physical_len = (len && ((len + extra_room) < cur_max_ampdu_size))
+                           ? (len + extra_room)
+                           : cur_max_ampdu_size;
+    u32 skb_len = max_physical_len + headroom + 3;
+    struct sk_buff *ampdu_skb = __dev_alloc_skb(skb_len, GFP_KERNEL);
+    struct ampdu_hdr_st *ampdu_hdr;
+    if (ampdu_skb == NULL) {
+        dev_err(sc->dev, "AMPDU allocation of size %d(%d) failed\n", len, skb_len);
+        return NULL;
+    }
+    payload_addr = ampdu_skb->data + headroom - sc->sh->tx_desc_len;
+    offset = ((size_t) payload_addr) % 4U;
+    if (offset) {
+        printk(KERN_ERR "Align AMPDU data %d\n", offset);
+        skb_reserve(ampdu_skb, headroom + 4 - offset);
+    } else
+        skb_reserve(ampdu_skb, headroom);
+    ampdu_hdr = (struct ampdu_hdr_st *) ampdu_skb->head;
+    skb_queue_head_init(&ampdu_hdr->mpdu_q);
+    ampdu_hdr->max_size = max_physical_len - extra_room;
+    ampdu_hdr->size = 0;
+    ampdu_hdr->ampdu_tid = ampdu_tid;
+    memset(ampdu_hdr->ssn, 0xFF, sizeof(ampdu_hdr->ssn));
+    ampdu_hdr->mpdu_num = 0;
+    return ampdu_skb;
+}
+bool _is_skb_q_empty (struct ssv_softc *sc, struct sk_buff *skb)
+{
+    u32 ac = skb_get_queue_mapping(skb);
+    u32 hw_txqid = sc->tx.hw_txqid[ac];
+    return AMPDU_HCI_Q_EMPTY(sc->sh, hw_txqid);
+}
+static void _print_BA(struct AMPDU_TID_st *ampdu_tid)
+{
+    u16 i, head_ssn, ssn;
+    struct sk_buff *skb;
+    struct SKB_info_st *skb_info;
+    head_ssn = ampdu_tid->ssv_baw_head;
+    printk(" BA for tid %d:", ampdu_tid->tidno);
+    for (i = 0; i < SSV_AMPDU_BA_WINDOW_SIZE; i ++) {
+        ssn = (head_ssn + i)% SSV_AMPDU_MAX_SSN;
+        skb = INDEX_PKT_BY_SSN(ampdu_tid, ssn);
+        if ((i % 8) == 0) {
+            printk("\n");
+        }
+        if (skb == NULL) {
+            printk(" NULL   ");
+            continue;
+        }
+        skb_info = (SKB_info *) (skb->head);
+        switch (skb_info->ampdu_tx_status) {
+        case AMPDU_ST_NON_AMPDU:
+            printk(" %4d Non", ssn);
+            break;
+        case AMPDU_ST_AGGREGATED:
+            printk(" %4d Agg", ssn);
+            break;
+        case AMPDU_ST_SENT:
+            printk(" %4d S  ", ssn);
+            break;
+        case AMPDU_ST_RETRY:
+            printk(" %4d R  ", ssn);
+            break;
+        case AMPDU_ST_RETRY_Q:
+            printk(" %4d Rq ", ssn);
+            break;
+        case AMPDU_ST_DROPPED:
+            printk(" %4d Dr ", ssn);
+            break;
+        case AMPDU_ST_DONE:
+            printk(" %4d Do ", ssn);
+            break;
+        default:
+            break;
+        }
+    }
+    printk("\n");
+}
+static u32 _check_timeout (struct AMPDU_TID_st *ampdu_tid, u32 *has_drop)
+{
+    u16 ssn, head_ssn, end_ssn;
+    unsigned long check_jiffies = jiffies;
+    u32 has_retry = 0;
+    struct ssv_softc *sc = AMPDU_TID_TO_SC(ampdu_tid);
+    bool check_BA = false;
+    head_ssn = ampdu_tid->ssv_baw_head;
+    ssn = head_ssn;
+    if (ssn == SSV_ILLEGAL_SN)
+        return 0;
+    end_ssn = (head_ssn + SSV_AMPDU_BA_WINDOW_SIZE)
+              % SSV_AMPDU_MAX_SSN;
+    do {
+        struct sk_buff *skb = INDEX_PKT_BY_SSN(ampdu_tid, ssn);
+        struct SKB_info_st *skb_info;
+        unsigned long cur_jiffies;
+        unsigned long timeout_jiffies;
+        u32 delta_ms;
+        if (skb == NULL) {
+            INC_PKT_SN(ssn);
+            continue;
+        }
+        skb_info = (SKB_info *) (skb->head);
+        if (skb_info->ampdu_tx_status != AMPDU_ST_AGGREGATED) {
+            cur_jiffies = jiffies;
+            timeout_jiffies = skb_info->aggr_timestamp + msecs_to_jiffies(BA_WAIT_TIMEOUT);
+            if ( time_before(cur_jiffies, timeout_jiffies))
+                break;
+            delta_ms = jiffies_to_msecs((long)(cur_jiffies - skb_info->aggr_timestamp));
+            prn_aggr_err(sc, "rt S%d-T%d-%d (%u) current state %d\n",
+                         ((struct ssv_sta_priv_data *)skb_info->sta->drv_priv)->sta_idx,
+                         ampdu_tid->tidno, ssn,
+                         delta_ms, skb_info->ampdu_tx_status);
+            if (delta_ms > 1000) {
+                prn_aggr_err(sc, "Last checktime %lu - %lu = %u, cur_jiffies %lu\n",
+                             check_jiffies, skb_info->aggr_timestamp,
+                             jiffies_to_msecs((long)(check_jiffies - skb_info->aggr_timestamp)), cur_jiffies);
+                check_BA = true;
+            }
+            ssv6xxx_mark_skb_retry(sc, skb_info, skb);
+            if (skb_info->ampdu_tx_status == AMPDU_ST_RETRY)
+                has_retry++;;
+            if (skb_info->ampdu_tx_status == AMPDU_ST_DROPPED)
+                (*has_drop)++;
+        }
+        INC_PKT_SN(ssn);
+    } while (ssn != end_ssn);
+    if ((check_BA) && (sc->log_ctrl & LOG_AMPDU_ERR))
+        _print_BA(ampdu_tid);
+    ampdu_tid->timestamp = check_jiffies;
+    return has_retry;
+}
+void ssv6xxx_ampdu_check_timeout (struct ieee80211_hw *hw)
+{
+    struct ssv_softc *sc = hw->priv;
+    struct AMPDU_TID_st *cur_AMPDU_TID;
+    u32 has_retry = 0, has_drop = 0;
+    bool tx_q_empty = true;
+    int i;
+    if (!list_empty(&sc->tx.ampdu_tx_que)) {
+        list_for_each_entry_rcu(cur_AMPDU_TID, &sc->tx.ampdu_tx_que, list) {
+            has_retry = 0;
+            has_drop = 0;
+            if (cur_AMPDU_TID == NULL)
+                return;
+            if (cur_AMPDU_TID->state != AMPDU_STATE_OPERATION)
+                continue;
+            has_retry = _check_timeout(cur_AMPDU_TID, &has_drop);
+            if (has_retry) {
+                _collect_retry_frames(cur_AMPDU_TID);
+                ssv6200_ampdu_send_retry(sc->hw, cur_AMPDU_TID, &cur_AMPDU_TID->retry_queue,
+                                         true);
+            }
+            if (has_drop) {
+                ssv6xxx_release_frames(cur_AMPDU_TID);
+            }
+        }
+    }
+    for (i = 0; i < WMM_NUM_AC; i++) {
+        if (AMPDU_HCI_Q_EMPTY(sc->sh, i)) {
+            tx_q_empty = false;
+            break;
+        }
+    }
+    if (tx_q_empty == true)
+        ssv6xxx_ampdu_flush(sc->hw);
+}
+void ssv6xxx_ampdu_sent(struct ieee80211_hw *hw, struct sk_buff *ampdu)
+{
+    struct ssv_softc *sc = hw->priv;
+    struct ampdu_hdr_st *ampdu_hdr = (struct ampdu_hdr_st *) ampdu->head;
+    struct sk_buff *mpdu;
+    unsigned long cur_jiffies = jiffies;
+    int i;
+    SKB_info *mpdu_skb_info;
+    u16 ssn;
+    unsigned long flags;
+    if (ampdu_hdr->ampdu_tid->state != AMPDU_STATE_OPERATION)
+        return;
+    spin_lock_irqsave(&ampdu_hdr->ampdu_tid->pkt_array_lock, flags);
+    for (i = 0; i < ampdu_hdr->mpdu_num; i++) {
+        ssn = ampdu_hdr->ssn[i];
+        mpdu = INDEX_PKT_BY_SSN(ampdu_hdr->ampdu_tid, ssn);
+        if (mpdu == NULL) {
+            dev_err(sc->dev, "T%d-%d is a NULL MPDU.\n",
+                    ampdu_hdr->ampdu_tid->tidno, ssn);
+            continue;
+        }
+        if (ampdu_skb_ssn(mpdu) != ssn) {
+            dev_err(sc->dev, "T%d-%d does not match %d MPDU.\n",
+                    ampdu_hdr->ampdu_tid->tidno, ssn, ampdu_skb_ssn(mpdu));
+            continue;
+        }
+        mpdu_skb_info = (SKB_info *) (mpdu->head);
+        mpdu_skb_info->aggr_timestamp = cur_jiffies;
+        if ((mpdu_skb_info->ampdu_tx_status != AMPDU_ST_DROPPED) ||
+            (mpdu_skb_info->ampdu_tx_status != AMPDU_ST_DONE)) {
+            mpdu_skb_info->ampdu_tx_status = AMPDU_ST_SENT;
+        }
+    }
+    spin_unlock_irqrestore(&ampdu_hdr->ampdu_tid->pkt_array_lock, flags);
+}
diff --git a/drivers/net/wireless/ssv6x5x/smac/ampdu.h b/drivers/net/wireless/ssv6x5x/smac/ampdu.h
new file mode 100644
index 000000000..5a84e3d08
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/ampdu.h
@@ -0,0 +1,265 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _AMPDU_H_
+#define _AMPDU_H_
+#include <linux/version.h>
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,0,0)
+#include "linux_2_6_35.h"
+#endif
+#define Enable_ampdu_debug_log (0)
+#define Enable_AMPDU_Live_Time (0)
+#define Enable_HW_AUTO_CRC_32 (1)
+#define Enable_AMPDU_Rx (1)
+#define Enable_AMPDU_Tx (1)
+#define Enable_AMPDU_delay_work (1)
+#define USE_FLUSH_RETRY
+#define USE_AMPDU_TX_STATUS_ARRAY
+#define SSV_AMPDU_FLOW_CONTROL
+#define AMPDU_CHECK_SKB_SEQNO
+#ifdef PLATFORM_FORCE_DISABLE_AMPDU_FLOW_CONTROL
+#undef SSV_AMPDU_FLOW_CONTROL
+#endif
+#define SSV_AMPDU_aggr_num_max MAX_AGGR_NUM
+#define SSV_AMPDU_seq_num_max (4096)
+#define SSV_AMPDU_retry_counter_max (16)
+#define SSV_AMPDU_tx_group_id_max (64)
+#define SSV_AMPDU_MAX_SSN (4096)
+#define SSV_AMPDU_BA_WINDOW_SIZE (64)
+#define SSV_AMPDU_WINDOW_SIZE (64)
+#define SSV_AMPDU_SIZE_1_2(sh) (((sh)->tx_page_available /2) << HW_MMU_PAGE_SHIFT)
+#define SSV_AMPDU_SIZE_3_7(sh) (((sh)->tx_page_available *3 /7) << HW_MMU_PAGE_SHIFT)
+#define SSV_AMPDU_FLOW_CONTROL_UPPER_BOUND (256)
+#define SSV_AMPDU_FLOW_CONTROL_LOWER_BOUND (48)
+#define SSV_AMPDU_timer_period (50)
+#define SSV_AMPDU_TX_TIME_THRESHOLD (50)
+#define SSV_AMPDU_MPDU_LIVE_TIME (SSV_AMPDU_retry_counter_max*8)
+#define SSV_AMPDU_BA_TIME (50)
+#define SSV_ILLEGAL_SN (0xffff)
+#define AMPDU_BUFFER_SIZE (32*1024)
+#define AMPDU_SIGNATURE (0x4E)
+#define AMPDU_DELIMITER_LEN (4)
+#define AMPDU_FCS_LEN (4)
+#define AMPDU_RESERVED_LEN (3)
+#define AMPDU_TX_NAV_MCS_567 (48)
+#define SSV_SEQ_NUM_SHIFT (4)
+#define SSV_RETRY_BIT_SHIFT (11)
+#define IEEE80211_SEQ_SEQ_SHIFT (4)
+#define IEEE80211_AMPDU_BA_LEN (34)
+#define SSV6200_AMPDU_TRIGGER_INDEX 0
+#define SSV_SN_STATUS_Release (0xaa)
+#define SSV_SN_STATUS_Retry (0xbb)
+#define SSV_SN_STATUS_Wait_BA (0xcc)
+#define SSV_SN_STATUS_Discard (0xdd)
+#define AMPDU_HCI_SEND_TAIL_WITH_FLOWCTRL (0)
+#define AMPDU_HCI_SEND_HEAD_WITH_FLOWCTRL (1)
+#define AMPDU_HCI_SEND_TAIL_WITHOUT_FLOWCTRL (2)
+#define AMPDU_HCI_SEND_HEAD_WITHOUT_FLOWCTRL (3)
+#define SSV_BAR_CTRL_ACK_POLICY_NORMAL (0x0000)
+#define SSV_BAR_CTRL_CBMTID_COMPRESSED_BA (0x0004)
+#define SSV_BAR_CTRL_TID_INFO_SHIFT (12)
+#define AMPDU_STATE_START BIT(0)
+#define AMPDU_STATE_OPERATION BIT(1)
+#define AMPDU_STATE_STOP BIT(2)
+typedef enum {
+    AMPDU_REKEY_PAUSE_STOP=0,
+    AMPDU_REKEY_PAUSE_START,
+    AMPDU_REKEY_PAUSE_ONGOING,
+    AMPDU_REKEY_PAUSE_DEFER,
+    AMPDU_REKEY_PAUSE_HWKEY_SYNC,
+} AMPDU_REKEY_PAUSE_STATE;
+#define SSV_a_minus_b_in_c(a,b,c) \
+        ({ \
+            typeof(a) _a = (a); \
+            typeof(b) _b = (b); \
+            typeof(c) _c = (c); \
+            (((_a)>=(_b))?((_a)-(_b)):((_c)-(_b)+(_a))); \
+        })
+#define SSV_AMPDU_SN_a_minus_b(a,b) \
+        ({ \
+            typeof(a) _a = (a); \
+            typeof(b) _b = (b); \
+            (SSV_a_minus_b_in_c((_a), (_b), SSV_AMPDU_seq_num_max)); \
+        })
+#define AMPDU_HCI_SEND(_sh,_sk,_q,_flag) \
+        ({ \
+            typeof(_sh) __sh = (_sh); \
+            __sh->hci.hci_ops->hci_tx(__sh->hci.hci_ctrl, (_sk), (_q), (_flag)); \
+        })
+#define AMPDU_HCI_Q_EMPTY(_sh,_q) \
+        ({ \
+            typeof(_sh) __sh = (_sh); \
+            __sh->hci.hci_ops->hci_txq_empty(__sh->hci.hci_ctrl, (_q)); \
+        })
+enum AMPDU_TX_STATUS_E {
+    AMPDU_ST_NON_AMPDU,
+    AMPDU_ST_AGGREGATED,
+    AMPDU_ST_SENT,
+    AMPDU_ST_RETRY,
+    AMPDU_ST_RETRY_Q,
+    AMPDU_ST_DROPPED,
+    AMPDU_ST_DONE,
+};
+typedef struct AMPDU_MIB_st {
+    u32 ampdu_mib_mpdu_counter;
+    u32 ampdu_mib_retry_counter;
+    u32 ampdu_mib_ampdu_counter;
+    u32 ampdu_mib_aggr_retry_counter;
+    u32 ampdu_mib_bar_counter;
+    u32 ampdu_mib_discard_counter;
+    u32 ampdu_mib_total_BA_counter;
+    u32 ampdu_mib_BA_counter;
+    u32 ampdu_mib_pass_counter;
+    u32 ampdu_mib_dist[SSV_AMPDU_aggr_num_max + 1];
+} AMPDU_MIB;
+typedef struct AMPDU_TID_st {
+    struct list_head list;
+    volatile unsigned long timestamp;
+    u32 tidno;
+    u16 ac;
+    struct ieee80211_sta *sta;
+    u16 ssv_baw_size;
+    u8 agg_num_max;
+    u8 state;
+#ifdef AMPDU_CHECK_SKB_SEQNO
+    u32 last_seqno;
+#endif
+    struct sk_buff_head ampdu_skb_tx_queue;
+    spinlock_t ampdu_skb_tx_queue_lock;
+    struct sk_buff_head retry_queue;
+    struct sk_buff_head release_queue;
+    struct sk_buff *aggr_pkts[SSV_AMPDU_BA_WINDOW_SIZE];
+    volatile u32 aggr_pkt_num;
+    volatile u16 ssv_baw_head;
+    spinlock_t pkt_array_lock;
+#ifdef ENABLE_AGGREGATE_IN_TIME
+    struct sk_buff *cur_ampdu_pkt;
+    struct sk_buff_head early_aggr_ampdu_q;
+    u32 early_aggr_skb_num;
+#endif
+    struct sk_buff_head ampdu_skb_wait_encry_queue;
+    u32 ampdu_mib_reset;
+    struct AMPDU_MIB_st mib;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+    struct dentry *debugfs_dir;
+    struct sk_buff_head ba_q;
+#endif
+} AMPDU_TID, *p_AMPDU_TID;
+typedef struct AMPDU_DELIMITER_st {
+    u16 reserved:4;
+    u16 length:12;
+    u8 crc;
+    u8 signature;
+} AMPDU_DELIMITER, *p_AMPDU_DELIMITER;
+typedef struct AMPDU_BLOCKACK_st {
+    u16 frame_control;
+    u16 duration;
+    u8 ra_addr[ETH_ALEN];
+    u8 ta_addr[ETH_ALEN];
+    u16 BA_ack_ploicy:1;
+    u16 multi_tid:1;
+    u16 compress_bitmap:1;
+    u16 reserved:9;
+    u16 tid_info:4;
+    u16 BA_fragment_sn:4;
+    u16 BA_ssn:12;
+    u32 BA_sn_bit_map[2];
+} AMPDU_BLOCKACK, *p_AMPDU_BLOCKACK;
+struct ssv_bar {
+    unsigned short frame_control;
+    unsigned short duration;
+    unsigned char ra[6];
+    unsigned char ta[6];
+    unsigned short control;
+    unsigned short start_seq_num;
+} __attribute__ ((packed));
+#if Enable_ampdu_debug_log
+#define ampdu_db_log(format, args...) printk("~~~ampdu [%s:%d] "format, __FUNCTION__, __LINE__, ##args)
+#define ampdu_db_log_simple(format, args...) printk(format, ##args)
+#else
+#define ampdu_db_log(...) do {} while (0)
+#define ampdu_db_log_simple(...) do {} while (0)
+#endif
+#if Enable_AMPDU_delay_work
+void ssv6200_ampdu_delayed_work_callback_func(struct work_struct *work);
+#else
+void ssv6200_ampdu_timer_callback_func(unsigned long data);
+#endif
+void ssv6200_ampdu_init(struct ieee80211_hw *hw);
+void ssv6200_ampdu_deinit(struct ieee80211_hw *hw);
+void ssv6200_ampdu_release_skb(struct sk_buff *skb, struct ieee80211_hw *hw);
+int ssv6200_ampdu_rx_start(struct ieee80211_hw *hw, struct ieee80211_vif *vif, struct ieee80211_sta *sta,
+                           u16 tid, u16 *ssn, u8 buf_size);
+void ssv6200_ampdu_tx_start(u16 tid, struct ieee80211_sta *sta, struct ieee80211_hw *hw, u16 *ssn);
+void ssv6200_ampdu_tx_operation(u16 tid, struct ieee80211_sta *sta, struct ieee80211_hw *hw, u8 buffer_size);
+void ssv6200_ampdu_tx_stop(u16 tid, struct ieee80211_sta *sta, struct ieee80211_hw *hw);
+bool ssv6200_ampdu_tx_handler(struct ieee80211_hw *hw, struct sk_buff *skb);
+void ssv6xxx_ampdu2mpdu(struct ieee80211_hw *hw, struct ieee80211_vif *vif, struct sk_buff *skb);
+u32 ssv6xxx_ampdu_flush(struct ieee80211_hw *hw);
+void ssv6200_ampdu_timeout_tx (struct ieee80211_hw *hw);
+struct cfg_host_event;
+void ssv6200_ampdu_no_BA_handler(struct ieee80211_hw *hw, struct sk_buff *skb);
+void ssv6200_ampdu_BA_handler(struct ieee80211_hw *hw, struct sk_buff *skb);
+void ssv6200_ampdu_tx_update_state(void *priv, struct ieee80211_sta *sta, struct sk_buff *skb);
+void ssv6200_ampdu_tx_add_sta(struct ieee80211_hw *hw, struct ieee80211_sta *sta);
+void ssv6xxx_ampdu_postprocess_BA (struct ieee80211_hw *hw);
+void ssv6xxx_ampdu_check_timeout (struct ieee80211_hw *hw);
+void ssv6xxx_ampdu_sent (struct ieee80211_hw *hw, struct sk_buff *ampdu);
+extern void ssv6xxx_set_ampdu_rx_add_work(struct work_struct *work);
+extern void ssv6xxx_set_ampdu_rx_del_work(struct work_struct *work);
+void ssv6xxx_mib_reset (struct ieee80211_hw *hw);
+ssize_t ssv6xxx_mib_dump (struct ieee80211_hw *hw, char *mib_str, ssize_t length);
+#if 0
+void tx_work(struct work_struct *work);
+void retry_work(struct work_struct *work);
+#endif
+void encry_work(struct work_struct *work);
+void sync_hw_key_work(struct work_struct *work);
+#ifdef SSV_SUPPORT_HAL
+#define SSV_AMPDU_AUTO_CRC_EN(_sh) HAL_AMPDU_AUTO_CRC_EN(_sh)
+#define SSV_UPDATE_AMPDU_TXINFO(_sc,_ampdu_skb) \
+            HAL_UPDATE_AMPDU_TXINFO(_sc, _ampdu_skb)
+#define SSV_ADD_AMPDU_TXINFO(_sc,_ampdu_skb) HAL_ADD_AMPDU_TXINFO(_sc, _ampdu_skb)
+#define SSV_UPDATE_TXINFO(_sc,_ampdu_retry_skb) \
+            HAL_UPDATE_TXINFO(_sc, _ampdu_retry_skb)
+#define SSV_SET_RX_BA(_sh,_bool,_ba_ra_addr,_ba_tid,_ba_ssn,_val) \
+            HAL_SET_RX_BA(_sh, _bool, _ba_ra_addr, _ba_tid, _ba_ssn, _val)
+#define SSV_AMPDU_RX_START(_sc,_hw,_vif,_sta,_tid,_ssn,_buf_size) \
+            HAL_AMPDU_RX_START(_sc, _hw, _vif, _sta, _tid, _ssn, _buf_size)
+#define SSV_AMPDU_BA_HANDLER(_sc,_hw,_skb,_tx_pkt_run_no) \
+            HAL_AMPDU_BA_HANDLER( _sc, _hw, _skb, _tx_pkt_run_no)
+#define SSV_HT_RATE_UPDATE(_sc,_skb,_rates) \
+   HAL_HT_RATE_UPDATE(_sc, _skb, _rates)
+#define SSV_AMPDU_MAX_TRANSMIT_LENGTH(_sc,_skb,_rate_idx) \
+   HAL_AMPDU_MAX_TRANSMIT_LENGTH(_sc, _skb, _rate_idx)
+#else
+#define SSV_AMPDU_AUTO_CRC_EN(_sh) \
+            SMAC_REG_SET_BITS(_sh, ADR_MTX_MISC_EN, (0x1 << MTX_AMPDU_CRC_AUTO_SFT), MTX_AMPDU_CRC_AUTO_MSK)
+#define SSV_UPDATE_AMPDU_TXINFO(_sc,_ampdu_skb)
+#define SSV_ADD_AMPDU_TXINFO(_sc,_ampdu_skb) _add_ampdu_txinfo(_sc, _ampdu_skb)
+#define SSV_UPDATE_TXINFO(_sc,_ampdu_retry_skb) \
+            ssv6xxx_update_txinfo(_sc, _ampdu_retry_skb)
+#define SSV_SET_RX_BA(_sh,_bool,_ba_ra_addr,_ba_tid,_ba_ssn,_val) \
+            ssv6200_hw_set_rx_ba_session(_sh, _bool, _ba_ra_addr, _ba_tid, _ba_ssn, _val)
+#define SSV_AMPDU_RX_START(_sc,_hw,_vif,_sta,_tid,_ssn,_buf_size) \
+            ssv6200_ampdu_rx_start(_hw, _vif, _sta, _tid, _ssn, _buf_size)
+#define SSV_AMPDU_BA_HANDLER(_sc,_hw,_skb,_tx_pkt_run_no) \
+            ssv6200_ampdu_BA_handler( _hw, _skb)
+#define SSV_HT_RATE_UPDATE(_sc,_skb,_rates) \
+   ssv62xx_ht_rate_update(_skb, _sc, _rates)
+#define SSV_AMPDU_MAX_TRANSMIT_LENGTH(_sc,_skb,_rate_idx) \
+   ssv6200_get_ampdu_max_transmit_length(_rate_idx)
+#endif
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smac/ap.c b/drivers/net/wireless/ssv6x5x/smac/ap.c
new file mode 100644
index 000000000..aacb3e08b
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/ap.c
@@ -0,0 +1,524 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/version.h>
+#include <ssv6200.h>
+#include <linux/nl80211.h>
+#include <linux/etherdevice.h>
+#include <linux/delay.h>
+#include <linux/version.h>
+#include <linux/time.h>
+#include <linux/sched.h>
+#ifdef SSV_MAC80211
+#include "ssv_mac80211.h"
+#else
+#include <net/mac80211.h>
+#endif
+#include <ssv6200.h>
+#include "lib.h"
+#include "dev.h"
+#include "ap.h"
+#include "ssv_rc_common.h"
+#include "ssv_rc.h"
+#include <hal.h>
+int ssv6200_bcast_queue_len(struct ssv6xxx_bcast_txq *bcast_txq);
+#define IS_EQUAL(a,b) ( (a) == (b) )
+#define SET_BIT(v,b) ( (v) |= (0x01<<b) )
+#define CLEAR_BIT(v,b) ( (v) &= ~(0x01<<b) )
+#define IS_BIT_SET(v,b) ( (v) & (0x01<<(b) ) )
+#define PBUF_BASE_ADDR 0x80000000
+#define PBUF_ADDR_SHIFT 16
+#define PBUF_MapPkttoID(_PKT) (((u32)_PKT&0x0FFF0000)>>PBUF_ADDR_SHIFT)
+#define PBUF_MapIDtoPkt(_ID) (PBUF_BASE_ADDR|((_ID)<<PBUF_ADDR_SHIFT))
+#define SSV6xxx_BEACON_MAX_ALLOCATE_CNT 10
+#define MTX_BCN_PKTID_CH_LOCK_SHIFT MTX_BCN_PKTID_CH_LOCK_SFT
+#define MTX_BCN_CFG_VLD_SHIFT MTX_BCN_CFG_VLD_SFT
+#define MTX_BCN_CFG_VLD_MASK MTX_BCN_CFG_VLD_MSK
+#define AUTO_BCN_ONGOING_MASK MTX_AUTO_BCN_ONGOING_MSK
+#define AUTO_BCN_ONGOING_SHIFT MTX_AUTO_BCN_ONGOING_SFT
+#define MTX_BCN_TIMER_EN_SHIFT MTX_BCN_TIMER_EN_SFT
+#define MTX_TSF_TIMER_EN_SHIFT MTX_TSF_TIMER_EN_SFT
+#define MTX_HALT_MNG_UNTIL_DTIM_SHIFT MTX_HALT_MNG_UNTIL_DTIM_SFT
+#define MTX_BCN_ENABLE_MASK (MTX_BCN_TIMER_EN_I_MSK)
+#define MTX_BCN_PERIOD_SHIFT MTX_BCN_PERIOD_SFT
+#define MTX_DTIM_NUM_SHIFT MTX_DTIM_NUM_SFT
+#define MTX_DTIM_OFST0 MTX_DTIM_OFST0_SFT
+#ifndef SSV_SUPPORT_HAL
+enum ssv6xxx_beacon_type {
+    SSV6xxx_BEACON_0,
+    SSV6xxx_BEACON_1,
+};
+void ssv6xxx_beacon_reg_lock(struct ssv_hw *sh, bool block)
+{
+    dbgprint(&sh->sc->cmd_data, sh->sc->log_ctrl, LOG_BEACON,
+             "ssv6xxx_beacon_reg_lock   val[0x:%08x]\n ", block);
+    SMAC_REG_SET_BITS(sh, ADR_MTX_BCN_MISC, block<<MTX_BCN_PKTID_CH_LOCK_SFT,
+                      MTX_BCN_PKTID_CH_LOCK_MSK);
+}
+void ssv6xxx_beacon_set_info(struct ssv_hw *sh, u8 beacon_interval, u8 dtim_cnt)
+{
+    u32 val;
+    if(beacon_interval==0)
+        beacon_interval = 100;
+    dbgprint(&sh->sc->cmd_data, sh->sc->log_ctrl, LOG_BEACON,
+             "[A] BSS_CHANGED_BEACON_INT beacon_int[%d] dtim_cnt[%d]\n",beacon_interval, (dtim_cnt));
+    val = (beacon_interval<<MTX_BCN_PERIOD_SHIFT)| (dtim_cnt<<MTX_DTIM_NUM_SHIFT);
+    SMAC_REG_WRITE(sh, ADR_MTX_BCN_PRD, val);
+}
+bool ssv6xxx_beacon_enable(struct ssv_softc *sc, bool bEnable)
+{
+    u32 regval=0;
+    int ret = 0;
+    if(bEnable && !sc->beacon_usage) {
+        printk("[A] Reject to set beacon!!!.        ssv6xxx_beacon_enable bEnable[%d] sc->beacon_usage[%d]\n",bEnable,sc->beacon_usage);
+        sc->enable_beacon = BEACON_WAITING_ENABLED;
+        return 0;
+    }
+    if((bEnable && (BEACON_ENABLED & sc->enable_beacon))||
+       (!bEnable && !sc->enable_beacon)) {
+        printk("[A] ssv6xxx_beacon_enable bEnable[%d] and sc->enable_beacon[%d] are the same. no need to execute.\n",bEnable,sc->enable_beacon);
+        if(bEnable) {
+            printk("        Ignore enable beacon cmd!!!!\n");
+            return 0;
+        }
+    }
+    SMAC_REG_READ(sc->sh, ADR_MTX_BCN_EN_MISC, &regval);
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_BEACON,
+             "[A] ssv6xxx_beacon_enable read misc reg val [%08x]\n", regval);
+    regval &= MTX_BCN_ENABLE_MASK;
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_BEACON,
+             "[A] ssv6xxx_beacon_enable read misc reg val [%08x]\n", regval);
+    regval |= (bEnable<<MTX_BCN_TIMER_EN_SHIFT);
+    ret = SMAC_REG_WRITE(sc->sh, ADR_MTX_BCN_EN_MISC, regval);
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_BEACON,
+             "[A] ssv6xxx_beacon_enable read misc reg val [%08x]\n", regval);
+    sc->enable_beacon = (bEnable==true)?BEACON_ENABLED:0;
+    return ret;
+}
+int ssv6xxx_beacon_fill_content(struct ssv_softc *sc, u32 regaddr, u8 *beacon, int size)
+{
+    u32 i, j, val;
+    size = size/4;
+    for(i = 0; i < size; i++) {
+        val = 0;
+        for ( j = 0; j < 4; j ++) {
+            val += (*beacon++) << j*8;
+        }
+        dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_BEACON, "[%08x] ", val );
+        SMAC_REG_WRITE(sc->sh, regaddr+i*4, val);
+    }
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_BEACON,"\n");
+    return 0;
+}
+inline enum ssv6xxx_beacon_type ssv6xxx_beacon_get_valid_reg(struct ssv_hw *sh)
+{
+    u32 regval =0;
+    SMAC_REG_READ(sh, ADR_MTX_BCN_MISC, &regval);
+    regval &= MTX_BCN_CFG_VLD_MASK;
+    regval = regval >>MTX_BCN_CFG_VLD_SHIFT;
+    if(regval==0x2 || regval == 0x0)
+        return SSV6xxx_BEACON_0;
+    else if(regval==0x1)
+        return SSV6xxx_BEACON_1;
+    else
+        printk("=============>ERROR!!drv_bcn_reg_available\n");
+    return SSV6xxx_BEACON_0;
+}
+inline bool ssv6xxx_auto_bcn_ongoing(struct ssv_hw *sh)
+{
+    u32 regval;
+    SMAC_REG_READ(sh, ADR_MTX_BCN_MISC, &regval);
+    return ((AUTO_BCN_ONGOING_MASK & regval) >> AUTO_BCN_ONGOING_SHIFT);
+}
+void ssv6xxx_beacon_fill_tx_desc(struct ssv_softc *sc, struct sk_buff* beacon_skb)
+{
+    struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(beacon_skb);
+    struct ssv6200_tx_desc *tx_desc;
+    struct ssv_rate_info ssv_rate;
+    skb_push(beacon_skb, TXPB_OFFSET);
+    tx_desc = (struct ssv6200_tx_desc *)beacon_skb->data;
+    memset(tx_desc,0, TXPB_OFFSET);
+    ssv6xxx_rc_hw_rate_idx(sc, tx_info, &ssv_rate);
+    tx_desc->len = beacon_skb->len-TXPB_OFFSET;
+    tx_desc->c_type = M2_TXREQ;
+    tx_desc->f80211 = 1;
+    tx_desc->ack_policy = 1;
+    tx_desc->hdr_offset = TXPB_OFFSET;
+    tx_desc->hdr_len = 24;
+    tx_desc->payload_offset = tx_desc->hdr_offset + tx_desc->hdr_len;
+    tx_desc->crate_idx = ssv_rate.crate_hw_idx;
+    tx_desc->drate_idx = ssv_rate.drate_hw_idx;
+    skb_put(beacon_skb, 4);
+}
+#endif
+bool ssv6xxx_beacon_set(struct ssv_softc *sc, struct sk_buff *beacon_skb, int dtim_offset)
+{
+    enum ssv6xxx_beacon_type avl_bcn_type = SSV6xxx_BEACON_0;
+    bool ret = true;
+    SSV_SET_BEACON_REG_LOCK(sc->sh, true);
+    avl_bcn_type = SSV_BEACON_GET_VALID_CFG(sc->sh);
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_BEACON,
+             "[A] ssv6xxx_beacon_set avl_bcn_type[%d]\n", avl_bcn_type);
+    do {
+        if(IS_BIT_SET(sc->beacon_usage, avl_bcn_type)) {
+            dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_BEACON,
+                     "[A] beacon has already been set old len[%d] new len[%d]\n",
+                     sc->beacon_info[avl_bcn_type].len, beacon_skb->len);
+            if (sc->beacon_info[avl_bcn_type].len >= beacon_skb->len) {
+                break;
+            } else {
+                if (false == SSV_FREE_PBUF(sc, sc->beacon_info[avl_bcn_type].pubf_addr)) {
+                    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_BEACON,
+                             "=============>ERROR!!Intend to allcoate beacon from ASIC fail.\n");
+                    ret = false;
+                    goto out;
+                }
+                CLEAR_BIT(sc->beacon_usage, avl_bcn_type);
+            }
+        }
+        sc->beacon_info[avl_bcn_type].pubf_addr = SSV_ALLOC_PBUF(sc, beacon_skb->len, RX_BUF);
+        sc->beacon_info[avl_bcn_type].len = beacon_skb->len;
+        if(sc->beacon_info[avl_bcn_type].pubf_addr == 0) {
+            ret = false;
+            goto out;
+        }
+        SET_BIT(sc->beacon_usage, avl_bcn_type);
+        dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_BEACON,
+                 "[A] beacon type[%d] usage[%d] allocate new beacon addr[%08x] \n",
+                 avl_bcn_type, sc->beacon_usage, sc->beacon_info[avl_bcn_type].pubf_addr);
+    } while(0);
+#ifdef SSV_SUPPORT_HAL
+    HAL_FILL_BCN(sc, sc->beacon_info[avl_bcn_type].pubf_addr, beacon_skb);
+    HAL_SET_BCN_ID_DTIM(sc, avl_bcn_type, dtim_offset);
+#else
+    ssv6xxx_beacon_fill_content(sc, sc->beacon_info[avl_bcn_type].pubf_addr, beacon_skb->data, beacon_skb->len);
+    {
+        u32 reg_tx_beacon_adr = ADR_MTX_BCN_CFG0;
+        u32 val;
+        val = (PBUF_MapPkttoID(sc->beacon_info[avl_bcn_type].pubf_addr)
+               | (dtim_offset<<MTX_DTIM_OFST0));
+        if(avl_bcn_type == SSV6xxx_BEACON_1)
+            reg_tx_beacon_adr = ADR_MTX_BCN_CFG1;
+        SMAC_REG_WRITE(sc->sh, reg_tx_beacon_adr, val);
+    }
+#endif
+out:
+    SSV_SET_BEACON_REG_LOCK(sc->sh, false);
+    if(sc->beacon_usage && (sc->enable_beacon&BEACON_WAITING_ENABLED)) {
+        printk("[A] enable beacon for BEACON_WAITING_ENABLED flags\n");
+        SSV_BEACON_ENABLE(sc, true);
+    }
+    return ret;
+}
+void ssv6xxx_beacon_release(struct ssv_softc *sc)
+{
+    int cnt=10;
+    printk("[A] ssv6xxx_beacon_release Enter\n");
+    cancel_work_sync(&sc->set_tim_work);
+    do {
+        if (SSV_GET_BCN_ONGOING(sc->sh)) {
+            SSV_BEACON_ENABLE(sc, false);
+        } else {
+            break;
+        }
+        cnt--;
+        if(cnt<=0)
+            break;
+    } while(1);
+    if(IS_BIT_SET(sc->beacon_usage, SSV6xxx_BEACON_0)) {
+        SSV_FREE_PBUF(sc, sc->beacon_info[SSV6xxx_BEACON_0].pubf_addr);
+        CLEAR_BIT(sc->beacon_usage, SSV6xxx_BEACON_0);
+    }
+    if(IS_BIT_SET(sc->beacon_usage, SSV6xxx_BEACON_1)) {
+        SSV_FREE_PBUF(sc, sc->beacon_info[SSV6xxx_BEACON_1].pubf_addr);
+        CLEAR_BIT(sc->beacon_usage, SSV6xxx_BEACON_1);
+    }
+    sc->enable_beacon = 0;
+    if(sc->beacon_buf) {
+        dev_kfree_skb_any(sc->beacon_buf);
+        sc->beacon_buf = NULL;
+    }
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_BEACON, "[A] ssv6xxx_beacon_release leave\n");
+}
+void ssv6xxx_beacon_change(struct ssv_softc *sc, struct ieee80211_hw *hw, struct ieee80211_vif *vif, bool aid0_bit_set)
+{
+    struct sk_buff *skb;
+    struct sk_buff *old_skb = NULL;
+    u16 tim_offset, tim_length;
+    if(sc == NULL || hw == NULL || vif == NULL ) {
+        printk("[Error]........ssv6xxx_beacon_change input error\n");
+        return;
+    }
+    do {
+        skb = ieee80211_beacon_get_tim(hw, vif,
+                                       &tim_offset, &tim_length);
+        if(skb == NULL) {
+            printk("[Error]........skb is NULL\n");
+            break;
+        }
+        if (tim_offset && tim_length >= 6) {
+            skb->data[tim_offset + 2] = 0;
+            if (!(sc->sh->cfg.hw_caps & SSV6200_HW_CAP_BEACON))
+                skb->data[tim_offset + 3] = 1;
+            if (aid0_bit_set)
+                skb->data[tim_offset + 4] |= 1;
+            else
+                skb->data[tim_offset + 4] &= ~1;
+        }
+        dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_BEACON,
+                 "[A] beacon len [%d] tim_offset[%d]\n", skb->len, tim_offset);
+        SSV_FILL_BEACON_TX_DESC(sc, skb);
+        dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_BEACON,
+                 "[A] beacon len [%d] tim_offset[%d]\n", skb->len, tim_offset);
+        if(sc->beacon_buf) {
+            if(memcmp(sc->beacon_buf->data, skb->data, (skb->len-FCS_LEN)) == 0) {
+                old_skb = skb;
+                break;
+            } else {
+                old_skb = sc->beacon_buf;
+                sc->beacon_buf = skb;
+            }
+        } else {
+            sc->beacon_buf = skb;
+        }
+        tim_offset+=2;
+        if(ssv6xxx_beacon_set(sc, skb, tim_offset)) {
+            u8 dtim_cnt = vif->bss_conf.dtim_period-1;
+            if(sc->beacon_dtim_cnt != dtim_cnt) {
+                sc->beacon_dtim_cnt = dtim_cnt;
+                dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_BEACON,
+                         "[A] beacon_dtim_cnt [%d]\n", sc->beacon_dtim_cnt);
+                SSV_SET_BCN_IFNO(sc->sh, sc->beacon_interval,
+                                 sc->beacon_dtim_cnt);
+            }
+        }
+    } while(0);
+    if(old_skb)
+        dev_kfree_skb_any(old_skb);
+}
+void ssv6200_set_tim_work(struct work_struct *work)
+{
+    struct ssv_softc *sc =
+        container_of(work, struct ssv_softc, set_tim_work);
+#ifdef BROADCAST_DEBUG
+    printk("%s() enter\n", __FUNCTION__);
+#endif
+    ssv6xxx_beacon_change(sc, sc->hw, sc->ap_vif, sc->aid0_bit_set);
+#ifdef BROADCAST_DEBUG
+    printk("%s() leave\n", __FUNCTION__);
+#endif
+}
+int ssv6200_bcast_queue_len(struct ssv6xxx_bcast_txq *bcast_txq)
+{
+    u32 len;
+    unsigned long flags;
+    spin_lock_irqsave(&bcast_txq->txq_lock, flags);
+    len = bcast_txq->cur_qsize;
+    spin_unlock_irqrestore(&bcast_txq->txq_lock, flags);
+    return len;
+}
+struct sk_buff* ssv6200_bcast_dequeue(struct ssv6xxx_bcast_txq *bcast_txq, u8 *remain_len)
+{
+    struct sk_buff *skb = NULL;
+    unsigned long flags;
+    spin_lock_irqsave(&bcast_txq->txq_lock, flags);
+    if(bcast_txq->cur_qsize) {
+        bcast_txq->cur_qsize --;
+        if(remain_len)
+            *remain_len = bcast_txq->cur_qsize;
+        skb = __skb_dequeue(&bcast_txq->qhead);
+    }
+    spin_unlock_irqrestore(&bcast_txq->txq_lock, flags);
+    return skb;
+}
+int ssv6200_bcast_enqueue(struct ssv_softc *sc, struct ssv6xxx_bcast_txq *bcast_txq,
+                          struct sk_buff *skb)
+{
+    unsigned long flags;
+    spin_lock_irqsave(&bcast_txq->txq_lock, flags);
+    if (bcast_txq->cur_qsize >=
+        SSV6200_MAX_BCAST_QUEUE_LEN) {
+        struct sk_buff *old_skb;
+        old_skb = __skb_dequeue(&bcast_txq->qhead);
+        bcast_txq->cur_qsize --;
+        ssv6xxx_txbuf_free_skb(old_skb, (void*)sc);
+        printk("[B] ssv6200_bcast_enqueue - remove oldest queue\n");
+    }
+    __skb_queue_tail(&bcast_txq->qhead, skb);
+    bcast_txq->cur_qsize ++;
+    spin_unlock_irqrestore(&bcast_txq->txq_lock, flags);
+    return bcast_txq->cur_qsize;
+}
+void ssv6200_bcast_flush(struct ssv_softc *sc, struct ssv6xxx_bcast_txq *bcast_txq)
+{
+    struct sk_buff *skb;
+    unsigned long flags;
+#ifdef BCAST_DEBUG
+    printk("ssv6200_bcast_flush\n");
+#endif
+    spin_lock_irqsave(&bcast_txq->txq_lock, flags);
+    while(bcast_txq->cur_qsize > 0) {
+        skb = __skb_dequeue(&bcast_txq->qhead);
+        bcast_txq->cur_qsize --;
+        ssv6xxx_txbuf_free_skb(skb, (void*)sc);
+    }
+    spin_unlock_irqrestore(&bcast_txq->txq_lock, flags);
+}
+static int queue_block_cnt = 0;
+void ssv6200_bcast_tx_work(struct work_struct *work)
+{
+    struct ssv_softc *sc =
+        container_of(work, struct ssv_softc, bcast_tx_work.work);
+#if 1
+    struct sk_buff* skb;
+    int i;
+    u8 remain_size;
+#endif
+    unsigned long flags;
+    bool needtimer = true;
+    long tmo = sc->bcast_interval;
+    spin_lock_irqsave(&sc->ps_state_lock, flags);
+    do {
+#ifdef BCAST_DEBUG
+        printk("[B] bcast_timer: hw_mng_used[%d] HCI_TXQ_EMPTY[%d] bcast_queue_len[%d].....................\n",
+               sc->hw_mng_used, HCI_TXQ_EMPTY(sc->sh, 4), ssv6200_bcast_queue_len(&sc->bcast_txq));
+#endif
+        if(sc->hw_mng_used != 0 ||
+           false == HCI_TXQ_EMPTY(sc->sh, 4)) {
+#ifdef BCAST_DEBUG
+            printk("HW queue still have frames insdide. skip this one hw_mng_used[%d] bEmptyTXQ4[%d]\n",
+                   sc->hw_mng_used, HCI_TXQ_EMPTY(sc->sh, 4));
+#endif
+            queue_block_cnt++;
+            if(queue_block_cnt>5) {
+                queue_block_cnt = 0;
+                ssv6200_bcast_flush(sc, &sc->bcast_txq);
+                needtimer = false;
+            }
+            break;
+        }
+        queue_block_cnt = 0;
+        for(i=0; i<SSV6200_ID_MANAGER_QUEUE; i++) {
+            skb = ssv6200_bcast_dequeue(&sc->bcast_txq, &remain_size);
+            if(!skb) {
+                needtimer = false;
+                break;
+            }
+            if( (0 != remain_size) &&
+                (SSV6200_ID_MANAGER_QUEUE-1) != i ) {
+                struct ieee80211_hdr *hdr;
+                hdr = (struct ieee80211_hdr *) ((u8*)skb->data+TXPB_OFFSET);
+                hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_MOREDATA);
+            }
+#ifdef BCAST_DEBUG
+            printk("[B] bcast_timer:tx remain_size[%d] i[%d]\n", remain_size, i);
+#endif
+            spin_unlock_irqrestore(&sc->ps_state_lock, flags);
+            if(HCI_SEND(sc->sh, skb, 4)<0) {
+                printk("bcast_timer send fail!!!!!!! \n");
+                ssv6xxx_txbuf_free_skb(skb, (void*)sc);
+                BUG_ON(1);
+            }
+            spin_lock_irqsave(&sc->ps_state_lock, flags);
+        }
+    } while(0);
+    if(needtimer) {
+#ifdef BCAST_DEBUG
+        printk("[B] bcast_timer:need more timer to tx bcast frame time[%d]\n", sc->bcast_interval);
+#endif
+        queue_delayed_work(sc->config_wq,
+                           &sc->bcast_tx_work,
+                           tmo);
+    } else {
+#ifdef BCAST_DEBUG
+        printk("[B] bcast_timer: ssv6200_bcast_stop\n");
+#endif
+        ssv6200_bcast_stop(sc);
+    }
+    spin_unlock_irqrestore(&sc->ps_state_lock, flags);
+#ifdef BCAST_DEBUG
+    printk("[B] bcast_timer: leave.....................\n");
+#endif
+}
+void ssv6200_bcast_start_work(struct work_struct *work)
+{
+    struct ssv_softc *sc =
+        container_of(work, struct ssv_softc, bcast_start_work);
+#ifdef BCAST_DEBUG
+    printk("[B] ssv6200_bcast_start_work==\n");
+#endif
+    sc->bcast_interval = (sc->beacon_dtim_cnt+1) *
+                         (sc->beacon_interval + 20) * HZ / 1000;
+    if (!sc->aid0_bit_set) {
+        sc->aid0_bit_set = true;
+        ssv6xxx_beacon_change(sc, sc->hw,
+                              sc->ap_vif, sc->aid0_bit_set);
+        queue_delayed_work(sc->config_wq,
+                           &sc->bcast_tx_work,
+                           sc->bcast_interval);
+#ifdef BCAST_DEBUG
+        printk("[B] bcast_start_work: Modify timer to DTIM[%d]ms==\n",
+               (sc->beacon_dtim_cnt+1)*(sc->beacon_interval + 20));
+#endif
+    }
+}
+void ssv6200_bcast_stop_work(struct work_struct *work)
+{
+    struct ssv_softc *sc =
+        container_of(work, struct ssv_softc, bcast_stop_work.work);
+    long tmo = HZ / 100;
+#ifdef BCAST_DEBUG
+    printk("[B] ssv6200_bcast_stop_work\n");
+#endif
+    if (sc->aid0_bit_set) {
+        if(0== ssv6200_bcast_queue_len(&sc->bcast_txq)) {
+            cancel_delayed_work_sync(&sc->bcast_tx_work);
+            sc->aid0_bit_set = false;
+            ssv6xxx_beacon_change(sc, sc->hw,
+                                  sc->ap_vif, sc->aid0_bit_set);
+#ifdef BCAST_DEBUG
+            printk("remove group bit in DTIM\n");
+#endif
+        } else {
+#ifdef BCAST_DEBUG
+            printk("bcast_stop_work: bcast queue still have data. just modify timer to 10ms\n");
+#endif
+            queue_delayed_work(sc->config_wq,
+                               &sc->bcast_tx_work,
+                               tmo);
+        }
+    }
+}
+void ssv6200_bcast_stop(struct ssv_softc *sc)
+{
+    queue_delayed_work(sc->config_wq,
+                       &sc->bcast_stop_work, sc->beacon_interval*HZ/1024);
+}
+void ssv6200_bcast_start(struct ssv_softc *sc)
+{
+    queue_work(sc->config_wq, &sc->bcast_start_work);
+}
+void ssv6200_release_bcast_frame_res(struct ssv_softc *sc, struct ieee80211_vif *vif)
+{
+    unsigned long flags;
+    struct ssv_vif_priv_data *priv_vif = (struct ssv_vif_priv_data *)vif->drv_priv;
+    spin_lock_irqsave(&sc->ps_state_lock, flags);
+    priv_vif->sta_asleep_mask = 0;
+    spin_unlock_irqrestore(&sc->ps_state_lock, flags);
+    cancel_work_sync(&sc->bcast_start_work);
+    cancel_delayed_work_sync(&sc->bcast_stop_work);
+    ssv6200_bcast_flush(sc, &sc->bcast_txq);
+    cancel_delayed_work_sync(&sc->bcast_tx_work);
+}
diff --git a/drivers/net/wireless/ssv6x5x/smac/ap.h b/drivers/net/wireless/ssv6x5x/smac/ap.h
new file mode 100644
index 000000000..7fbe462c4
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/ap.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _AP_H_
+#define _AP_H_
+#ifndef SSV_SUPPORT_HAL
+#define BEACON_WAITING_ENABLED 1<<0
+#define BEACON_ENABLED 1<<1
+bool ssv6xxx_beacon_enable(struct ssv_softc *sc, bool bEnable);
+void ssv6xxx_beacon_set_info(struct ssv_hw *sh, u8 beacon_interval, u8 dtim_cnt);
+void ssv6xxx_beacon_fill_tx_desc(struct ssv_softc *sc, struct sk_buff* beacon_skb);
+#endif
+void ssv6xxx_beacon_change(struct ssv_softc *sc, struct ieee80211_hw *hw, struct ieee80211_vif *vif, bool aid0_bit_set);
+void ssv6xxx_beacon_release(struct ssv_softc *sc);
+void ssv6200_set_tim_work(struct work_struct *work);
+void ssv6200_bcast_start_work(struct work_struct *work);
+void ssv6200_bcast_stop_work(struct work_struct *work);
+void ssv6200_bcast_tx_work(struct work_struct *work);
+int ssv6200_bcast_queue_len(struct ssv6xxx_bcast_txq *bcast_txq);
+struct sk_buff* ssv6200_bcast_dequeue(struct ssv6xxx_bcast_txq *bcast_txq, u8 *remain_len);
+int ssv6200_bcast_enqueue(struct ssv_softc *sc, struct ssv6xxx_bcast_txq *bcast_txq, struct sk_buff *skb);
+void ssv6200_bcast_start(struct ssv_softc *sc);
+void ssv6200_bcast_stop(struct ssv_softc *sc);
+void ssv6200_release_bcast_frame_res(struct ssv_softc *sc, struct ieee80211_vif *vif);
+#ifdef SSV_SUPPORT_HAL
+#define SSV_SET_BEACON_REG_LOCK(_sh,_bool) HAL_SET_BEACON_REG_LOCK( _sh, _bool)
+#define SSV_BEACON_GET_VALID_CFG(_sh) HAL_BEACON_GET_VALID_CFG( _sh)
+#define SSV_ALLOC_PBUF(_sc,_len,_TX_BUF) HAL_ALLOC_PBUF( _sc, _len, _TX_BUF)
+#define SSV_BEACON_ENABLE(_sc,_bool) HAL_BEACON_ENABLE( _sc, _bool)
+#define SSV_GET_BCN_ONGOING(_sh) HAL_GET_BCN_ONGOING( _sh)
+#define SSV_SET_BCN_IFNO(_sh,_beacon_interval,_beacon_dtim_cnt) \
+            HAL_SET_BCN_IFNO( _sh, _beacon_interval, _beacon_dtim_cnt)
+#define SSV_FILL_BEACON_TX_DESC(_sc,_skb) HAL_FILL_BEACON_TX_DESC(_sc, _skb)
+#else
+#define SSV_SET_BEACON_REG_LOCK(_sh,_bool) ssv6xxx_beacon_reg_lock( _sh, _bool)
+#define SSV_BEACON_GET_VALID_CFG(_sh) ssv6xxx_beacon_get_valid_reg( _sh)
+#define SSV_ALLOC_PBUF(_sc,_len,_TX_BUF) ssv6xxx_pbuf_alloc( _sc, _len, _TX_BUF)
+#define SSV_BEACON_ENABLE(_sc,_bool) ssv6xxx_beacon_enable( _sc, _bool)
+#define SSV_GET_BCN_ONGOING(_sh) ssv6xxx_auto_bcn_ongoing( _sh)
+#define SSV_SET_BCN_IFNO(_sh,_beacon_interval,_beacon_dtim_cnt) \
+            ssv6xxx_beacon_set_info( _sh, _beacon_interval, _beacon_dtim_cnt)
+#define SSV_FILL_BEACON_TX_DESC(_sc,_skb) ssv6xxx_beacon_fill_tx_desc(_sc, _skb)
+#endif
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smac/dev.c b/drivers/net/wireless/ssv6x5x/smac/dev.c
new file mode 100644
index 000000000..3fe4c283d
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/dev.c
@@ -0,0 +1,6168 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/nl80211.h>
+#include <linux/etherdevice.h>
+#include <linux/delay.h>
+#include <linux/version.h>
+#include <linux/time.h>
+#include <linux/kthread.h>
+#ifdef SSV_MAC80211
+#include "ssv_mac80211.h"
+#else
+#include <net/mac80211.h>
+#endif
+#include <net/cfg80211.h>
+#include <ssv6200.h>
+#include <hci/hctrl.h>
+#include "lib.h"
+#include "ssv_rc.h"
+#include "ssv_ht_rc.h"
+#include "dev.h"
+#include "ap.h"
+#include "init.h"
+#include "p2p.h"
+#include "ssv_skb.h"
+#include <hal.h>
+#include <linux_80211.h>
+#ifdef CONFIG_SSV_SUPPORT_ANDROID
+#include "ssv_pm.h"
+#endif
+#ifdef MULTI_THREAD_ENCRYPT
+#include <linux/freezer.h>
+#endif
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,2,0) && LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0)
+#include "linux_3_0_0.h"
+#endif
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+#include "ssv6xxx_debugfs.h"
+#endif
+#define NO_USE_RXQ_LOCK
+#ifndef WLAN_CIPHER_SUITE_SMS4
+#define WLAN_CIPHER_SUITE_SMS4 0x00147201
+#endif
+#ifdef ENABLE_TX_Q_FLOW_CONTROL
+#ifdef MULTI_THREAD_ENCRYPT
+#define MAX_CRYPTO_Q_LEN (64)
+#define LOW_CRYPTO_Q_LEN (MAX_CRYPTO_Q_LEN/2)
+#endif
+#define MAX_TX_Q_LEN (64)
+#define LOW_TX_Q_LEN (MAX_TX_Q_LEN/2)
+#endif
+static u16 bits_per_symbol[][2] = {
+    { 26, 54 },
+    { 52, 108 },
+    { 78, 162 },
+    { 104, 216 },
+    { 156, 324 },
+    { 208, 432 },
+    { 234, 486 },
+    { 260, 540 },
+};
+void ssv6xxx_none_func(struct ssv_softc *sc)
+{
+    dev_info(sc->dev, "None function for this model!! \n");
+}
+static int ssv6xxx_push_log_to_circbuf(struct ssv_dbg_log *dbg_log, const char *src, unsigned int len)
+{
+    int i;
+    char *p = dbg_log->tail;
+    for (i = 0; i < len; i++) {
+        *p++ = src[i];
+        if (p == dbg_log->end) {
+            p = dbg_log->data;
+        }
+        if (dbg_log->size < dbg_log->totalsize) {
+            dbg_log->size++;
+        } else {
+            dbg_log->top++;
+            if (dbg_log->top == dbg_log->end) {
+                dbg_log->top = dbg_log->data;
+            }
+        }
+    }
+    dbg_log->tail = p;
+    return len;
+}
+void dbgprint(struct ssv_cmd_data *cmd_data, u32 log_ctrl, u32 log_id, const char *fmt,...)
+{
+    char tbuf[32], log[256], buf[300];
+    va_list args;
+    int buf_len = 0, log_len = 0;
+    unsigned long long t;
+    unsigned long nanosec_rem;
+    if (log_ctrl & log_id) {
+        if (!cmd_data->log_to_ram) {
+            va_start(args, fmt);
+            printk(fmt, args);
+            va_end(args);
+        } else {
+            va_start(args, fmt);
+            log_len = vsnprintf(log, sizeof(log)-1, fmt, args);
+            va_end(args);
+            if (log_len == (sizeof(log) - 1))
+                printk("%s(): log message is too long\n", __FUNCTION__);
+            log[log_len] = '\0';
+            t = cpu_clock(UINT_MAX);
+            nanosec_rem = do_div(t, 1000000000);
+            sprintf(tbuf, "[%5lu.%06lu]", (unsigned long)t, nanosec_rem / 1000);
+            buf_len = sprintf(buf, "%s %s", tbuf, log);
+            if ((cmd_data->dbg_log.data != NULL) && (cmd_data->dbg_log.totalsize != 0)) {
+                ssv6xxx_push_log_to_circbuf(&cmd_data->dbg_log, buf, buf_len);
+            }
+        }
+    }
+}
+void ssv6xxx_hci_dbgprint(void *argc, u32 log_id, const char *fmt,...)
+{
+    struct ssv_softc *sc = (struct ssv_softc *)argc;
+    struct ssv_cmd_data *cmd_data = &sc->cmd_data;
+    char log[256];
+    va_list args;
+    int log_len = 0;
+    if (sc->log_ctrl & log_id) {
+        va_start(args, fmt);
+        log_len = vsnprintf(log, sizeof(log)-1, fmt, args);
+        va_end(args);
+        if (log_len == (sizeof(log) - 1))
+            dev_dbg(sc->dev, "%s(): log message is too long\n", __FUNCTION__);
+        log[log_len] = '\0';
+        dbgprint(cmd_data, sc->log_ctrl, log_id, "%s", log);
+    }
+}
+#ifdef CONFIG_DEBUG_SKB_TIMESTAMP
+extern struct ssv6xxx_hci_ctrl *ssv_dbg_ctrl_hci;
+extern unsigned int cal_duration_of_ampdu(struct sk_buff *ampdu_skb, int stage);
+#endif
+static void _process_rx_q (struct ssv_softc *sc, struct sk_buff_head *rx_q, spinlock_t *rx_q_lock);
+static u32 _process_tx_done (struct ssv_softc *sc);
+#ifdef MULTI_THREAD_ENCRYPT
+static u32 _remove_sta_skb_from_q (struct ssv_softc *sc, struct sk_buff_head *q,
+                                   u32 addr0_3, u32 addr4_5);
+#ifdef CONFIG_DEBUG_SKB_TIMESTAMP
+unsigned int cal_duration_of_mpdu(struct sk_buff *mpdu_skb)
+{
+    unsigned int timeout;
+    SKB_info *mpdu_skb_info = (SKB_info *)mpdu_skb->head;
+    timeout = (unsigned int)ktime_to_ms(ktime_sub(ktime_get(), mpdu_skb_info->timestamp));
+    if (timeout > SKB_DURATION_TIMEOUT_MS)
+        dev_dbg(sc->dev, "*mpdu_duration: %ums\n", timeout);
+    return timeout;
+}
+#endif
+unsigned int skb_queue_len_safe(struct sk_buff_head *list)
+{
+    unsigned long flags;
+    unsigned int ret = 0;
+    spin_lock_irqsave(&list->lock, flags);
+    ret = skb_queue_len(list);
+    spin_unlock_irqrestore(&list->lock, flags);
+    return ret;
+}
+#endif
+#if 1
+void _ssv6xxx_hexdump(const char *title, const u8 *buf,
+                      size_t len)
+{
+    size_t i;
+    printk(KERN_DEBUG "%s - hexdump(len=%lu):\n", title, (unsigned long) len);
+    if (buf == NULL) {
+        printk(KERN_DEBUG " [NULL]");
+    } else {
+        for (i = 0; i < len; i++) {
+            printk(KERN_DEBUG " %02x", buf[i]);
+            if((i+1)%16 ==0)
+                printk(KERN_DEBUG "\n");
+        }
+    }
+    printk(KERN_DEBUG "\n-----------------------------\n");
+}
+#endif
+void ssv6xxx_txbuf_free_skb(struct sk_buff *skb, void *args)
+{
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,4,0)
+    struct ssv_softc *sc = (struct ssv_softc *)args;
+#endif
+    if (!skb)
+        return;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,4,0)
+    ieee80211_free_txskb(sc->hw, skb);
+#else
+    dev_kfree_skb_any(skb);
+#endif
+}
+#ifndef SSV_SUPPORT_HAL
+#define ADDRESS_OFFSET 16
+#define HW_ID_OFFSET 7
+#define MAX_FAIL_COUNT 100
+#define MAX_RETRY_COUNT 20
+static inline bool ssv6xxx_mcu_input_full(struct ssv_softc *sc)
+{
+    u32 regval=0;
+    SMAC_REG_READ(sc->sh, ADR_MCU_STATUS, &regval);
+    return CH0_FULL_MSK&regval;
+}
+u32 ssv6xxx_pbuf_alloc(struct ssv_softc *sc, int size, int type)
+{
+    u32 regval, pad;
+    int cnt = MAX_RETRY_COUNT;
+    int page_cnt = (size + ((1 << HW_MMU_PAGE_SHIFT) - 1)) >> HW_MMU_PAGE_SHIFT;
+    regval = 0;
+    mutex_lock(&sc->mem_mutex);
+    pad = size%4;
+    size += pad;
+    do {
+        SMAC_REG_WRITE(sc->sh, ADR_WR_ALC, (size | (type << 16)));
+        SMAC_REG_READ(sc->sh, ADR_WR_ALC, &regval);
+        if (regval == 0) {
+            cnt--;
+            msleep(1);
+        } else
+            break;
+    } while (cnt);
+    if (type == TX_BUF) {
+        sc->sh->tx_page_available -= page_cnt;
+        sc->sh->page_count[PACKET_ADDR_2_ID(regval)] = page_cnt;
+    }
+    mutex_unlock(&sc->mem_mutex);
+    if (regval == 0)
+        dev_err(sc->dev, "Failed to allocate packet buffer of %d bytes in %d type.",
+                size, type);
+    else {
+        dev_info(sc->dev, "Allocated %d type packet buffer of size %d (%d) at address %x.\n",
+                 type, size, page_cnt, regval);
+    }
+    return regval;
+}
+bool ssv6xxx_pbuf_free(struct ssv_softc *sc, u32 pbuf_addr)
+{
+    u32 regval=0;
+    u16 failCount=0;
+    u8 *p_tx_page_cnt = &sc->sh->page_count[PACKET_ADDR_2_ID(pbuf_addr)];
+    while (ssv6xxx_mcu_input_full(sc)) {
+        if (failCount++ < 1000) continue;
+        dev_dbg(sc->dev, "=============>ERROR!!MAILBOX Block[%d]\n", failCount);
+        return false;
+    }
+    mutex_lock(&sc->mem_mutex);
+    regval = ((M_ENG_TRASH_CAN << HW_ID_OFFSET) |(pbuf_addr >> ADDRESS_OFFSET));
+    dev_dbg(sc->dev, "[A] ssv6xxx_pbuf_free addr[%08x][%x]\n", pbuf_addr, regval);
+    SMAC_REG_WRITE(sc->sh, ADR_CH0_TRIG_1, regval);
+    if (*p_tx_page_cnt) {
+        sc->sh->tx_page_available += *p_tx_page_cnt;
+        *p_tx_page_cnt = 0;
+    }
+    mutex_unlock(&sc->mem_mutex);
+    return true;
+}
+#ifdef CONFIG_SSV_CABRIO_A
+static const struct ssv6xxx_calib_table vt_tbl[] = {
+    { 1, 0xf1, 0x333333, 3859},
+    { 2, 0xf1, 0xB33333, 3867},
+    { 3, 0xf2, 0x333333, 3875},
+    { 4, 0xf2, 0xB33333, 3883},
+    { 5, 0xf3, 0x333333, 3891},
+    { 6, 0xf3, 0xB33333, 3899},
+    { 7, 0xf4, 0x333333, 3907},
+    { 8, 0xf4, 0xB33333, 3915},
+    { 9, 0xf5, 0x333333, 3923},
+    { 10, 0xf5, 0xB33333, 3931},
+    { 11, 0xf6, 0x333333, 3939},
+    { 12, 0xf6, 0xB33333, 3947},
+    { 13, 0xf7, 0x333333, 3955},
+    { 14, 0xf8, 0x666666, 3974},
+};
+int ssv6xxx_set_channel(struct ssv_softc *sc, struct ieee80211_channel *channel, enum nl80211_channel_type)
+{
+    int retry_cnt, fail_cnt=0;
+    struct ssv_hw *sh=sc->sh;
+    u32 regval;
+    int ret = 0;
+    int chidx;
+    bool chidx_vld = 0;
+    int ch;
+    ch = chan->hw_value;
+    for(chidx = 0; chidx < (sizeof(vt_tbl)/sizeof(vt_tbl[0])); chidx++) {
+        if (vt_tbl[chidx].channel_id == ch) {
+            chidx_vld = 1;
+            break;
+        }
+    }
+    if (chidx_vld == 0) {
+        dev_dbg(sc->dev, "%s(): fail! channel_id not found in vt_tbl\n", __FUNCTION__);
+        return -1;
+    }
+    do {
+        if ((ret = SMAC_REG_READ(sh, ADR_SPI_TO_PHY_PARAM1, &regval)) != 0) break;
+        if ((ret = SMAC_REG_WRITE(sh,ADR_SPI_TO_PHY_PARAM1,(regval&~0xffff)|3)) != 0) break;
+        ssv6xxx_rf_disable(sc->sh);
+        if ((ret = SMAC_REG_SET_BITS(sc->sh, ADR_CBR_SYN_DIV_SDM_XOSC,
+                                     (0x01<<13), (0x01<<13))) != 0) break;
+        regval = vt_tbl[chidx].rf_ctrl_F;
+        if ((ret = SMAC_REG_SET_BITS(sc->sh, ADR_CBR_SYN_RGISTER_1,
+                                     (regval << 0), 0x00ffffff)) != 0) break;
+        regval = vt_tbl[chidx].rf_ctrl_N;
+        if ((ret = SMAC_REG_SET_BITS(sh, ADR_CBR_SYN_RGISTER_2,
+                                     (regval<<0), 0x000007ff)) != 0) break;
+        if ((ret = SMAC_REG_SET_BITS(sh, ADR_CBR_MANUAL_REGISTER,
+                                     (64<<1), (0x000007f<<1))) != 0) break;
+        if ((ret = SMAC_REG_SET_BITS(sh, ADR_CBR_MANUAL_REGISTER,
+                                     (1<<0), 0x00000001)) != 0) break;
+        if ((ret = SMAC_REG_SET_BITS(sh, ADR_CBR_MANUAL_REGISTER,
+                                     (0<<0), 0x00000001)) != 0) break;
+        if ((ret = SMAC_REG_SET_BITS(sh, ADR_CBR_SX_ENABLE_RGISTER,
+                                     (1<<11), 0x00000800)) != 0) break;
+        if ((ret = SMAC_REG_SET_BITS(sh, ADR_CBR_SX_ENABLE_RGISTER,
+                                     (0<<12), 0x00001000)) != 0) break;
+        if ((ret = SMAC_REG_SET_BITS(sh, ADR_CBR_SX_ENABLE_RGISTER,
+                                     (1<<12), 0x00001000)) != 0) break;
+        for(retry_cnt=20; retry_cnt>0; retry_cnt--) {
+            mdelay(20);
+            if ((ret = SMAC_REG_READ(sh, ADR_CBR_READ_ONLY_FLAGS_1, &regval)) != 0) break;
+            if (regval & 0x00000004) {
+                if ((ret = SMAC_REG_SET_BITS(sh, ADR_CBR_SX_ENABLE_RGISTER,
+                                             (0<<12), 0x00001000)) != 0) break;
+                if ((ret = SMAC_REG_READ(sh, ADR_CBR_READ_ONLY_FLAGS_1, &regval)) != 0) break;
+                if ((regval & 0x00001800) == 0) {
+                    ssv6xxx_rf_enable(sh);
+                    return 0;
+                } else {
+                    dev_dbg(sc->dev, "%s(): Lock channel %d fail!\n", __FUNCTION__, vt_tbl[chidx].channel_id);
+                    if ((ret = SMAC_REG_READ(sh, ADR_CBR_READ_ONLY_FLAGS_1, &regval)) != 0) break;
+                    dev_dbg(sc->dev, "%s(): dbg: vt-mon read out as %d when rdy\n", __FUNCTION__, ((regval & 0x00001800) >> 11));
+                    if ((ret = SMAC_REG_READ(sh, ADR_CBR_READ_ONLY_FLAGS_2, &regval)) != 0) break;
+                    dev_dbg(sc->dev, "%s(): dbg: sub-sel read out as %d when rdy\n", __FUNCTION__, ((regval & 0x00000fe0) >> 5));
+                    if ((ret = SMAC_REG_READ(sh, ADR_CBR_SYN_DIV_SDM_XOSC, &regval)) != 0) break;
+                    dev_dbg(sc->dev, "%s(): dbg: RG_SX_REFBYTWO read out as %d when rdy\n", __FUNCTION__, ((regval & 0x00002000) >> 13));
+                    if ((ret = SMAC_REG_READ(sh, ADR_CBR_SYN_RGISTER_1, &regval)) != 0) break;
+                    dev_dbg(sc->dev, "%s(): dbg: RG_SX_RFCTRL_F read out as 0x%08x when rdy\n", __FUNCTION__, ((regval & 0x00ffffff) >> 0));
+                    if ((ret = SMAC_REG_READ(sh, ADR_CBR_SYN_RGISTER_2, &regval)) != 0) break;
+                    dev_dbg(sc->dev, "%s(): dbg: RG_SX_RFCTRL_CH read out as 0x%08x when rdy\n", __FUNCTION__, ((regval & 0x000007ff) >> 0));
+                    if ((ret = SMAC_REG_READ(sh, ADR_CBR_SX_ENABLE_RGISTER, &regval)) != 0) break;
+                    dev_dbg(sc->dev, "%s(): dbg: RG_EN_SX_VT_MON_DG read out as %d when rdy\n", __FUNCTION__, ((regval & 0x00001000) >> 12));
+                }
+            }
+        }
+        fail_cnt++;
+        dev_dbg(sc->dev, "%s(): calibration fail [%d] rounds!!\n",
+               __FUNCTION__, fail_cnt);
+        if(fail_cnt == 100)
+            return -1;
+    } while(ret == 0);
+    return ret;
+}
+#endif
+#ifdef CONFIG_SSV_CABRIO_E
+static const struct ssv6xxx_calib_table vt_tbl[SSV6XXX_IQK_CFG_XTAL_MAX][14]= {
+    {
+        { 1, 0xB9, 0x89D89E, 3859},
+        { 2, 0xB9, 0xEC4EC5, 3867},
+        { 3, 0xBA, 0x4EC4EC, 3875},
+        { 4, 0xBA, 0xB13B14, 3883},
+        { 5, 0xBB, 0x13B13B, 3891},
+        { 6, 0xBB, 0x762762, 3899},
+        { 7, 0xBB, 0xD89D8A, 3907},
+        { 8, 0xBC, 0x3B13B1, 3915},
+        { 9, 0xBC, 0x9D89D9, 3923},
+        { 10, 0xBD, 0x000000, 3931},
+        { 11, 0xBD, 0x627627, 3939},
+        { 12, 0xBD, 0xC4EC4F, 3947},
+        { 13, 0xBE, 0x276276, 3955},
+        { 14, 0xBF, 0x13B13B, 3974},
+    },
+    {
+        { 1, 0xf1, 0x333333, 3859},
+        { 2, 0xf1, 0xB33333, 3867},
+        { 3, 0xf2, 0x333333, 3875},
+        { 4, 0xf2, 0xB33333, 3883},
+        { 5, 0xf3, 0x333333, 3891},
+        { 6, 0xf3, 0xB33333, 3899},
+        { 7, 0xf4, 0x333333, 3907},
+        { 8, 0xf4, 0xB33333, 3915},
+        { 9, 0xf5, 0x333333, 3923},
+        { 10, 0xf5, 0xB33333, 3931},
+        { 11, 0xf6, 0x333333, 3939},
+        { 12, 0xf6, 0xB33333, 3947},
+        { 13, 0xf7, 0x333333, 3955},
+        { 14, 0xf8, 0x666666, 3974},
+    },
+    {
+        { 1, 0xC9, 0x000000, 3859},
+        { 2, 0xC9, 0x6AAAAB, 3867},
+        { 3, 0xC9, 0xD55555, 3875},
+        { 4, 0xCA, 0x400000, 3883},
+        { 5, 0xCA, 0xAAAAAB, 3891},
+        { 6, 0xCB, 0x155555, 3899},
+        { 7, 0xCB, 0x800000, 3907},
+        { 8, 0xCB, 0xEAAAAB, 3915},
+        { 9, 0xCC, 0x555555, 3923},
+        { 10, 0xCC, 0xC00000, 3931},
+        { 11, 0xCD, 0x2AAAAB, 3939},
+        { 12, 0xCD, 0x955555, 3947},
+        { 13, 0xCE, 0x000000, 3955},
+        { 14, 0xCF, 0x000000, 3974},
+    }
+};
+#define FAIL_MAX 100
+#define RETRY_MAX 20
+int ssv6xxx_set_channel(struct ssv_softc *sc, struct ieee80211_channel *chan, enum nl80211_channel_type channel_type)
+{
+    struct ssv_hw *sh=sc->sh;
+    int retry_cnt, fail_cnt=0;
+    u32 regval;
+    int ret = -1;
+    int chidx;
+    bool chidx_vld = 0;
+    int ch;
+    ch = chan->hw_value;
+    dev_dbg(sc->dev, "Setting channel to %d\n", ch);
+    if((sh->cfg.chip_identity == SSV6051Z) || (sc->sh->cfg.chip_identity == SSV6051P)) {
+        if((ch == 13) || (ch == 14)) {
+            if(sh->ipd_channel_touch == 0) {
+                for (chidx = 0; chidx < sh->ch_cfg_size; chidx++) {
+                    SMAC_REG_WRITE(sh, sh->p_ch_cfg[chidx].reg_addr, sh->p_ch_cfg[chidx].ch13_14_value);
+                }
+                sh->ipd_channel_touch = 1;
+            }
+        } else {
+            if(sh->ipd_channel_touch) {
+                for (chidx = 0; chidx < sh->ch_cfg_size; chidx++) {
+                    SMAC_REG_WRITE(sh, sh->p_ch_cfg[chidx].reg_addr, sh->p_ch_cfg[chidx].ch1_12_value);
+                }
+                sh->ipd_channel_touch = 0;
+            }
+        }
+    }
+    for(chidx = 0; chidx < 14; chidx++) {
+        if (vt_tbl[sh->cfg.crystal_type][chidx].channel_id == ch) {
+            chidx_vld = 1;
+            break;
+        }
+    }
+    if (chidx_vld == 0) {
+        dev_dbg(sc->dev, "%s(): fail! channel_id not found in vt_tbl\n", __FUNCTION__);
+        goto exit;
+    }
+    if ((ret = ssv6xxx_rf_disable(sc->sh)) != 0)
+        goto exit;
+    do {
+        regval = vt_tbl[sh->cfg.crystal_type][chidx].rf_ctrl_F;
+        if ((ret = SMAC_RF_REG_SET_BITS(sc->sh, ADR_SYN_REGISTER_1,
+                                        (regval<<0), (0x00ffffff<<0))) != 0) break;
+        regval = vt_tbl[sh->cfg.crystal_type][chidx].rf_ctrl_N;
+        if ((ret = SMAC_RF_REG_SET_BITS(sc->sh, ADR_SYN_REGISTER_2,
+                                        (regval<<0), (0x07ff<<0))) != 0) break;
+        if ((ret = SMAC_RF_REG_READ(sc->sh, ADR_SX_LCK_BIN_REGISTERS_I, &regval)) != 0) break;
+        regval = vt_tbl[sh->cfg.crystal_type][chidx].rf_precision_default;
+        if ((ret = SMAC_RF_REG_SET_BITS(sc->sh, ADR_SX_LCK_BIN_REGISTERS_II,
+                                        (regval<<0), (0x1fff<<0))) != 0) break;
+        if ((ret = SMAC_RF_REG_SET_BITS(sc->sh, ADR_MANUAL_ENABLE_REGISTER,
+                                        (0x00<<14), (0x01<<14))) != 0) break;
+        if ((ret = SMAC_RF_REG_SET_BITS(sc->sh, ADR_MANUAL_ENABLE_REGISTER,
+                                        (0x01<<14), (0x01<<14))) != 0) break;
+        retry_cnt = 0;
+        do {
+            mdelay(1);
+            if ((ret = SMAC_RF_REG_READ(sc->sh, ADR_READ_ONLY_FLAGS_1, &regval)) != 0) break;
+            if (regval & 0x00000002) {
+                if ((ret = SMAC_RF_REG_READ(sc->sh, ADR_READ_ONLY_FLAGS_2, &regval)) != 0) break;
+                ret = ssv6xxx_rf_enable(sc->sh);
+#if 0
+                dev_dbg(sc->dev, "Lock to channel %d ([0xce010098]=%x)!!\n", vt_tbl[sh->cfg.crystal_type][chidx].channel_id, regval);
+                dev_dbg(sc->dev, "crystal_type [%d]\n",sh->cfg.crystal_type);
+                SMAC_REG_READ(sc->sh, 0xce010040, &regval);
+                dev_dbg(sc->dev, "0xce010040 [%x]\n",regval);
+                SMAC_REG_READ(sc->sh, 0xce0100a4, &regval);
+                dev_dbg(sc->dev, "0xce0100a4 [%x]\n",regval);
+                SMAC_REG_READ(sc->sh, ADR_DPLL_DIVIDER_REGISTER, &regval);
+                dev_dbg(sc->dev, "0xce010060 [%x]\n",regval);
+                SMAC_REG_READ(sc->sh, ADR_SX_ENABLE_REGISTER, &regval);
+                dev_dbg(sc->dev, "0xce010038 [%x]\n",regval);
+                SMAC_REG_READ(sc->sh, 0xce01003C, &regval);
+                dev_dbg(sc->dev, "0xce01003C [%x]\n",regval);
+                SMAC_REG_READ(sc->sh, ADR_DPLL_FB_DIVIDER_REGISTERS_I, &regval);
+                dev_dbg(sc->dev, "0xce01009c [%x]\n",regval);
+                SMAC_REG_READ(sc->sh, ADR_DPLL_FB_DIVIDER_REGISTERS_II, &regval);
+                dev_dbg(sc->dev, "0xce0100a0 [%x]\n",regval);
+                dev_dbg(sc->dev, "[%x][%x][%x]\n",vt_tbl[sh->cfg.crystal_type][chidx].rf_ctrl_N,vt_tbl[sh->cfg.crystal_type][chidx].rf_ctrl_F,vt_tbl[sh->cfg.crystal_type][chidx].rf_precision_default);
+#endif
+                dev_info(sc->dev, "Lock to channel %d ([0xce010098]=%x)!!\n", vt_tbl[sh->cfg.crystal_type][chidx].channel_id, regval);
+                sc->hw_chan = ch;
+                goto exit;
+            }
+            retry_cnt++;
+        } while(retry_cnt < RETRY_MAX);
+        fail_cnt++;
+        dev_dbg(sc->dev, "calibation fail:[%d]\n", fail_cnt);
+    } while((fail_cnt < FAIL_MAX) && (ret == 0));
+exit:
+    if(ch <= 7) {
+        if(sh->cfg.tx_power_index_1) {
+            SMAC_RF_REG_READ(sc->sh, ADR_RX_TX_FSM_REGISTER, &regval);
+            regval &= RG_TX_GAIN_OFFSET_I_MSK;
+            regval |= (sh->cfg.tx_power_index_1 << RG_TX_GAIN_OFFSET_SFT);
+            SMAC_REG_WRITE(sc->sh, ADR_RX_TX_FSM_REGISTER, regval);
+        } else if(sh->cfg.tx_power_index_2) {
+            SMAC_RF_REG_READ(sc->sh, ADR_RX_TX_FSM_REGISTER, &regval);
+            regval &= RG_TX_GAIN_OFFSET_I_MSK;
+            SMAC_REG_WRITE(sc->sh, ADR_RX_TX_FSM_REGISTER, regval);
+        }
+    } else {
+        if(sh->cfg.tx_power_index_2) {
+            SMAC_RF_REG_READ(sc->sh, ADR_RX_TX_FSM_REGISTER, &regval);
+            regval &= RG_TX_GAIN_OFFSET_I_MSK;
+            regval |= (sh->cfg.tx_power_index_2 << RG_TX_GAIN_OFFSET_SFT);
+            SMAC_REG_WRITE(sc->sh, ADR_RX_TX_FSM_REGISTER, regval);
+        } else if(sh->cfg.tx_power_index_1) {
+            SMAC_RF_REG_READ(sc->sh, ADR_RX_TX_FSM_REGISTER, &regval);
+            regval &= RG_TX_GAIN_OFFSET_I_MSK;
+            SMAC_REG_WRITE(sc->sh, ADR_RX_TX_FSM_REGISTER, regval);
+        }
+    }
+    return ret;
+}
+#endif
+int ssv6xxx_rf_enable(struct ssv_hw *sh)
+{
+    return SMAC_REG_SET_BITS(sh, ADR_CBR_HARD_WIRE_PIN_REGISTER,
+                             (RF_MODE_TRX_EN << CBR_RG_MODE_SFT), CBR_RG_MODE_MSK);
+}
+int ssv6xxx_rf_disable(struct ssv_hw *sh)
+{
+    return SMAC_REG_SET_BITS(sh,ADR_CBR_HARD_WIRE_PIN_REGISTER,
+                             (RF_MODE_STANDBY << CBR_RG_MODE_SFT), CBR_RG_MODE_MSK);
+}
+void ssv6xxx_set_on3_enable(struct ssv_hw *sh, bool val)
+{
+    return;
+}
+int ssv6xxx_update_decision_table(struct ssv_softc *sc)
+{
+    int i;
+    for(i=0; i<MAC_DECITBL1_SIZE; i++) {
+        SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_TB0+i*4,
+                       sc->mac_deci_tbl[i]);
+        SMAC_REG_CONFIRM(sc->sh, ADR_MRX_FLT_TB0+i*4,
+                         sc->mac_deci_tbl[i]);
+    }
+    for(i=0; i<MAC_DECITBL2_SIZE; i++) {
+        SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_EN0+i*4,
+                       sc->mac_deci_tbl[i+MAC_DECITBL1_SIZE]);
+        SMAC_REG_CONFIRM(sc->sh, ADR_MRX_FLT_EN0+i*4,
+                         sc->mac_deci_tbl[i+MAC_DECITBL1_SIZE]);
+    }
+    return 0;
+}
+static int ssv6xxx_set_macaddr(struct ssv_hw *sh, int vif_idx)
+{
+    int ret = 0;
+    if (vif_idx != 0) {
+        dev_dbg(sc->dev, "Does not support set MAC Address to HW for VIF %d\n", vif_idx);
+        return -1;
+    }
+    ret = SMAC_REG_WRITE(sh, ADR_STA_MAC_0, *((u32 *)&sh->cfg.maddr[0][0]));
+    if (!ret)
+        ret = SMAC_REG_WRITE(sh, ADR_STA_MAC_1, *((u32 *)&sh->cfg.maddr[0][4]));
+    return ret;
+}
+static int ssv6xxx_set_bssid(struct ssv_hw *sh, u8 *bssid)
+{
+    int ret = 0;
+    struct ssv_softc *sc = sh->sc;
+    memcpy(sc->bssid[0], bssid, 6);
+    ret = SMAC_REG_WRITE(sh, ADR_BSSID_0, *((u32 *)&sc->bssid[0][0]));
+    if (!ret)
+        ret = SMAC_REG_WRITE(sh, ADR_BSSID_1, *((u32 *)&sc->bssid[0][4]));
+    return ret;
+}
+static void ssv6xxx_set_op_mode(struct ssv_hw *sh, u32 op_mode)
+{
+    SMAC_REG_SET_BITS(sh, ADR_GLBLE_SET, op_mode, OP_MODE_MSK);
+}
+static void ssv6xxx_get_rx_desc_info(struct sk_buff *skb, u32 *packet_len, u32 *c_type,
+                                     u32 *tx_pkt_run_no)
+{
+    struct ssv6200_rx_desc *rxdesc = (struct ssv6200_rx_desc *)skb->data;
+    *packet_len = rxdesc->len;
+    *c_type = rxdesc->c_type;
+    *tx_pkt_run_no = SSV6XXX_PKT_RUN_TYPE_NOTUSED;
+}
+#endif
+int ssv6xxx_frame_hdrlen(struct ieee80211_hdr *hdr, bool is_ht)
+{
+#define CTRL_FRAME_INDEX(fc) ((hdr->frame_control-IEEE80211_STYPE_BACK_REQ)>>4)
+    u16 fc, CTRL_FLEN[]= { 16, 16, 16, 16, 10, 10, 16, 16 };
+    int hdr_len = 24;
+    fc = hdr->frame_control;
+    if (ieee80211_is_ctl(fc))
+        hdr_len = CTRL_FLEN[CTRL_FRAME_INDEX(fc)];
+    else if (ieee80211_is_mgmt(fc)) {
+        if (ieee80211_has_order(fc))
+            hdr_len += ((is_ht==1)? 4: 0);
+    } else {
+        if (ieee80211_has_a4(fc))
+            hdr_len += 6;
+        if (ieee80211_is_data_qos(fc)) {
+            hdr_len += 2;
+            if (ieee80211_has_order(hdr->frame_control) &&
+                is_ht==true)
+                hdr_len += 4;
+        }
+    }
+    return hdr_len;
+}
+#if 0
+static void ssv6xxx_dump_tx_desc(struct sk_buff *skb)
+{
+    struct ssv6200_tx_desc *tx_desc;
+    int s;
+    u8 *dat;
+    tx_desc = (struct ssv6200_tx_desc *)skb->data;
+    dev_dbg(sc->dev, ">> Tx Frame:\n");
+    for(s=0, dat=skb->data; s<tx_desc->hdr_len; s++) {
+        dev_dbg(sc->dev, "%02x ", dat[sizeof(*tx_desc)+s]);
+        if (((s+1)& 0x0F) == 0)
+            dev_dbg(sc->dev, "\n");
+    }
+    dev_dbg(sc->dev, "length: %d, c_type=%d, f80211=%d, qos=%d, ht=%d, use_4addr=%d, sec=%d\n",
+           tx_desc->len, tx_desc->c_type, tx_desc->f80211, tx_desc->qos, tx_desc->ht,
+           tx_desc->use_4addr, tx_desc->security);
+    dev_dbg(sc->dev, "more_data=%d, sub_type=%x, extra_info=%d\n", tx_desc->more_data,
+           tx_desc->stype_b5b4, tx_desc->extra_info);
+    dev_dbg(sc->dev, "fcmd=0x%08x, hdr_offset=%d, frag=%d, unicast=%d, hdr_len=%d\n",
+           tx_desc->fCmd, tx_desc->hdr_offset, tx_desc->frag, tx_desc->unicast,
+           tx_desc->hdr_len);
+    dev_dbg(sc->dev, "tx_burst=%d, ack_policy=%d, do_rts_cts=%d, reason=%d, payload_offset=%d\n",
+           tx_desc->tx_burst, tx_desc->ack_policy, tx_desc->do_rts_cts,
+           tx_desc->reason, tx_desc->payload_offset);
+    dev_dbg(sc->dev, "fcmdidx=%d, wsid=%d, txq_idx=%d\n",
+           tx_desc->fCmdIdx, tx_desc->wsid, tx_desc->txq_idx);
+    dev_dbg(sc->dev, "RTS/CTS Nav=%d, frame_time=%d, crate_idx=%d, drate_idx=%d, dl_len=%d\n",
+           tx_desc->rts_cts_nav, tx_desc->frame_consume_time, tx_desc->crate_idx, tx_desc->drate_idx,
+           tx_desc->dl_length);
+}
+static void ssv6xxx_dump_rx_desc(struct sk_buff *skb)
+{
+    struct ssv6200_rx_desc *rx_desc;
+    rx_desc = (struct ssv6200_rx_desc *)skb->data;
+    dev_dbg(sc->dev, ">> RX Descriptor:\n");
+    dev_dbg(sc->dev, "len=%d, c_type=%d, f80211=%d, qos=%d, ht=%d, use_4addr=%d, l3cs_err=%d, l4_cs_err=%d\n",
+           rx_desc->len, rx_desc->c_type, rx_desc->f80211, rx_desc->qos, rx_desc->ht, rx_desc->use_4addr,
+           rx_desc->l3cs_err, rx_desc->l4cs_err);
+    dev_dbg(sc->dev, "align2=%d, psm=%d, stype_b5b4=%d, extra_info=%d\n",
+           rx_desc->align2, rx_desc->psm, rx_desc->stype_b5b4, rx_desc->extra_info);
+    dev_dbg(sc->dev, "hdr_offset=%d, reason=%d, rx_result=%d\n", rx_desc->hdr_offset,
+           rx_desc->reason, rx_desc->RxResult);
+}
+#endif
+u32 ssv6xxx_ht_txtime(u8 rix, int pktlen, int width,
+                      int half_gi, bool is_gf)
+{
+    u32 nbits, nsymbits, duration, nsymbols;
+    int streams;
+    streams = 1;
+    nbits = (pktlen << 3) + OFDM_PLCP_BITS;
+    nsymbits = bits_per_symbol[rix % 8][width] * streams;
+    nsymbols = (nbits + nsymbits - 1) / nsymbits;
+    if (!half_gi)
+        duration = SYMBOL_TIME(nsymbols);
+    else {
+        if (!is_gf)
+            duration = DIV_ROUND_UP(SYMBOL_TIME_HALFGI(nsymbols), 4)<<2;
+        else
+            duration = SYMBOL_TIME_HALFGI(nsymbols);
+    }
+    duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams)+HT_SIGNAL_EXT;
+    if (is_gf)
+        duration -=12;
+    duration += HT_SIFS_TIME;
+    return duration;
+}
+u32 ssv6xxx_non_ht_txtime(u8 phy, int kbps,
+                          u32 frameLen, bool shortPreamble)
+{
+    u32 bits_per_symbol, num_bits, num_symbols;
+    u32 phy_time, tx_time;
+    if (kbps == 0)
+        return 0;
+    switch (phy) {
+    case WLAN_RC_PHY_CCK:
+        phy_time = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
+        if (shortPreamble)
+            phy_time >>= 1;
+        num_bits = frameLen << 3;
+        tx_time = CCK_SIFS_TIME + phy_time + ((num_bits * 1000) / kbps);
+        break;
+    case WLAN_RC_PHY_OFDM:
+        bits_per_symbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
+        num_bits = OFDM_PLCP_BITS + (frameLen << 3);
+        num_symbols = DIV_ROUND_UP(num_bits, bits_per_symbol);
+        tx_time = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
+                  + (num_symbols * OFDM_SYMBOL_TIME);
+        break;
+    default:
+        printk(KERN_ERR "Unknown phy %u\n", phy);
+        BUG_ON(1);
+        tx_time = 0;
+        break;
+    }
+    return tx_time;
+}
+#ifndef SSV_SUPPORT_HAL
+static u32 ssv6xxx_set_frame_duration(struct ieee80211_tx_info *info,
+                                      struct ssv_rate_info *ssv_rate, u16 len,
+                                      struct ssv6200_tx_desc *tx_desc, struct fw_rc_retry_params *rc_params,
+                                      struct ssv_softc *sc)
+{
+    struct ieee80211_tx_rate *tx_drate;
+    u32 frame_time=0, ack_time=0, rts_cts_nav=0, frame_consume_time=0;
+    u32 l_length=0, drate_kbps=0, crate_kbps=0;
+    bool ctrl_short_preamble=false, is_sgi, is_ht40;
+    bool is_ht, is_gf;
+    int d_phy,c_phy, nRCParams, mcsidx;
+    struct ssv_rate_ctrl *ssv_rc = NULL;
+    tx_drate = &info->control.rates[0];
+    is_sgi = !!(tx_drate->flags & IEEE80211_TX_RC_SHORT_GI);
+    is_ht40 = !!(tx_drate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
+    is_ht = !!(tx_drate->flags & IEEE80211_TX_RC_MCS);
+    is_gf = !!(tx_drate->flags & IEEE80211_TX_RC_GREEN_FIELD);
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
+    if ((info->control.short_preamble) ||
+        (tx_drate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE))
+        ctrl_short_preamble = true;
+#else
+    if ((info->control.vif &&
+         info->control.vif->bss_conf.use_short_preamble) ||
+        (tx_drate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE))
+        ctrl_short_preamble = true;
+#endif
+#ifdef FW_RC_RETRY_DEBUG
+    dev_dbg(sc->dev, "mcs = %d, data rate idx=%d\n",tx_drate->idx, tx_drate[3].count);
+#endif
+    for (nRCParams = 0; (nRCParams < SSV62XX_TX_MAX_RATES) ; nRCParams++) {
+        if ((rc_params == NULL) || (sc == NULL)) {
+            mcsidx = tx_drate->idx;
+            drate_kbps = ssv_rate->drate_kbps;
+            crate_kbps = ssv_rate->crate_kbps;
+        } else {
+            if(rc_params[nRCParams].count == 0) {
+                break;
+            }
+            ssv_rc = sc->rc;
+            mcsidx = (rc_params[nRCParams].drate - SSV62XX_RATE_MCS_INDEX) % MCS_GROUP_RATES;
+            drate_kbps = ssv_rc->rc_table[rc_params[nRCParams].drate].rate_kbps;
+            crate_kbps = ssv_rc->rc_table[rc_params[nRCParams].crate].rate_kbps;
+        }
+        if (tx_drate->flags & IEEE80211_TX_RC_MCS) {
+            frame_time = ssv6xxx_ht_txtime(mcsidx,
+                                           len, is_ht40, is_sgi, is_gf);
+            d_phy = 0;
+        } else {
+            if ((info->band == INDEX_80211_BAND_2GHZ) &&
+                !(ssv_rate->d_flags & IEEE80211_RATE_ERP_G))
+                d_phy = WLAN_RC_PHY_CCK;
+            else
+                d_phy = WLAN_RC_PHY_OFDM;
+            frame_time = ssv6xxx_non_ht_txtime(d_phy, drate_kbps,
+                                               len, ctrl_short_preamble);
+        }
+        if ((info->band == INDEX_80211_BAND_2GHZ) &&
+            !(ssv_rate->c_flags & IEEE80211_RATE_ERP_G))
+            c_phy = WLAN_RC_PHY_CCK;
+        else
+            c_phy = WLAN_RC_PHY_OFDM;
+        if (tx_desc->unicast) {
+            if (info->flags & IEEE80211_TX_CTL_AMPDU) {
+                ack_time = ssv6xxx_non_ht_txtime(c_phy,
+                                                 crate_kbps, BA_LEN, ctrl_short_preamble);
+            } else {
+                ack_time = ssv6xxx_non_ht_txtime(c_phy,
+                                                 crate_kbps, ACK_LEN, ctrl_short_preamble);
+            }
+        }
+        if (tx_desc->do_rts_cts & IEEE80211_TX_RC_USE_RTS_CTS) {
+            rts_cts_nav = frame_time;
+            rts_cts_nav += ack_time;
+            rts_cts_nav += ssv6xxx_non_ht_txtime(c_phy,
+                                                 crate_kbps, CTS_LEN, ctrl_short_preamble);
+            frame_consume_time = rts_cts_nav;
+            frame_consume_time += ssv6xxx_non_ht_txtime(c_phy,
+                                  crate_kbps, RTS_LEN, ctrl_short_preamble);
+        } else if (tx_desc->do_rts_cts & IEEE80211_TX_RC_USE_CTS_PROTECT) {
+            rts_cts_nav = frame_time;
+            rts_cts_nav += ack_time;
+            frame_consume_time = rts_cts_nav;
+            frame_consume_time += ssv6xxx_non_ht_txtime(c_phy,
+                                  crate_kbps, CTS_LEN, ctrl_short_preamble);
+        } else {;}
+        if (tx_drate->flags & IEEE80211_TX_RC_MCS) {
+            l_length = frame_time - HT_SIFS_TIME;
+            l_length = ((l_length-(HT_SIGNAL_EXT+20))+3)>>2;
+            l_length += ((l_length<<1) - 3);
+        }
+        if((rc_params == NULL) || (sc == NULL)) {
+            tx_desc->rts_cts_nav = rts_cts_nav;
+            tx_desc->frame_consume_time = (frame_consume_time>>5)+1;;
+            tx_desc->dl_length = l_length;
+            break;
+        } else {
+            rc_params[nRCParams].rts_cts_nav = rts_cts_nav;
+            rc_params[nRCParams].frame_consume_time = (frame_consume_time>>5)+1;
+            rc_params[nRCParams].dl_length = l_length;
+            if(nRCParams == 0) {
+                tx_desc->drate_idx = rc_params[nRCParams].drate;
+                tx_desc->crate_idx = rc_params[nRCParams].crate;
+                tx_desc->rts_cts_nav = rc_params[nRCParams].rts_cts_nav;
+                tx_desc->frame_consume_time = rc_params[nRCParams].frame_consume_time;
+                tx_desc->dl_length = rc_params[nRCParams].dl_length;
+            }
+        }
+    }
+    return ack_time;
+}
+#endif
+#ifdef FW_WSID_WATCH_LIST
+int hw_update_watch_wsid(struct ssv_softc *sc, struct ieee80211_sta *sta,
+                         struct ssv_sta_info *sta_info, int sta_idx, int rx_hw_sec, int ops)
+{
+    int ret = 0;
+    int retry_cnt=20;
+    struct sk_buff *skb = NULL;
+    struct cfg_host_cmd *host_cmd;
+    struct ssv6xxx_wsid_params *ptr;
+    dev_dbg(sc->dev, "cmd=%d for fw wsid list, wsid %d \n", ops, sta_idx);
+    skb = ssv_skb_alloc(sc, HOST_CMD_HDR_LEN + sizeof(struct ssv6xxx_wsid_params));
+    if(skb == NULL || sta_info == NULL || sc == NULL)
+        return -1;
+    skb->data_len = HOST_CMD_HDR_LEN + sizeof(struct ssv6xxx_wsid_params);
+    skb->len = skb->data_len;
+    host_cmd = (struct cfg_host_cmd *)skb->data;
+    host_cmd->c_type = HOST_CMD;
+    host_cmd->h_cmd = (u8)SSV6XXX_HOST_CMD_WSID_OP;
+    host_cmd->len = skb->data_len;
+    ptr = (struct ssv6xxx_wsid_params *)host_cmd->dat8;
+    ptr->cmd = ops;
+    ptr->hw_security = rx_hw_sec;
+    if ((ptr->cmd != SSV6XXX_WSID_OPS_HWWSID_PAIRWISE_SET_TYPE)
+        && (ptr->cmd != SSV6XXX_WSID_OPS_HWWSID_GROUP_SET_TYPE)) {
+        ptr->wsid_idx = (u8)(sta_idx - SSV_NUM_HW_STA);
+    } else {
+        ptr->wsid_idx = (u8)(sta_idx);
+    };
+    memcpy(&ptr->target_wsid, &sta->addr[0], 6);
+    while (((sc->sh->hci.hci_ops->hci_send_cmd(sc->sh->hci.hci_ctrl, skb)) != 0) && (retry_cnt)) {
+        dev_dbg(sc->dev, KERN_INFO "WSID cmd=%d retry=%d!!\n", ops, retry_cnt);
+        retry_cnt--;
+    }
+    dev_dbg(sc->dev, "%s: wsid_idx = %u\n", __FUNCTION__, ptr->wsid_idx);
+    ssv_skb_free(sc, skb);
+    if(ops == SSV6XXX_WSID_OPS_ADD)
+        sta_info->hw_wsid = sta_idx;
+    return ret;
+}
+#endif
+#ifndef SSV_SUPPORT_HAL
+static void ssv6200_hw_set_pair_type(struct ssv_hw *sh,u8 type)
+{
+    u32 temp;
+    SMAC_REG_READ(sh,ADR_SCRT_SET,&temp);
+    temp = (temp & PAIR_SCRT_I_MSK);
+    temp |= (type << PAIR_SCRT_SFT);
+    SMAC_REG_WRITE(sh,ADR_SCRT_SET, temp);
+    dev_dbg(sc->dev, "==>%s: write cipher type %d into hw\n",__func__,type);
+}
+static u32 ssv6200_hw_get_pair_type(struct ssv_hw *sh)
+{
+    u32 temp;
+    SMAC_REG_READ(sh,ADR_SCRT_SET,&temp);
+    temp &= PAIR_SCRT_MSK;
+    temp = (temp >> PAIR_SCRT_SFT);
+    SMAC_REG_WRITE(sh,ADR_SCRT_SET, temp);
+    dev_dbg(sc->dev, "==>%s: read cipher type %d from hw\n",__func__, temp);
+    return temp;
+}
+static void ssv6200_hw_set_group_type(struct ssv_hw *sh,u8 type)
+{
+    u32 temp;
+    SMAC_REG_READ(sh,ADR_SCRT_SET,&temp);
+    temp = temp & GRP_SCRT_I_MSK;
+    temp |= (type << GRP_SCRT_SFT);
+    SMAC_REG_WRITE(sh,ADR_SCRT_SET, temp);
+    dev_dbg(sc->dev, KERN_ERR "Set group key type %d\n", type);
+}
+void ssv6xxx_reset_sec_module(struct ssv_softc *sc)
+{
+    ssv6200_hw_set_group_type(sc->sh, ME_NONE);
+    ssv6200_hw_set_pair_type(sc->sh, ME_NONE);
+}
+static void ssv6xxx_disable_fw_wsid(struct ssv_softc *sc, int key_idx,
+                                    struct ssv_sta_priv_data *sta_priv, struct ssv_vif_priv_data *vif_priv)
+{
+#ifdef FW_WSID_WATCH_LIST
+    if (sta_priv) {
+        struct ssv_sta_info *sta_info = &sc->sta_info[sta_priv->sta_idx];
+        if ((key_idx == 0) && (sta_priv->has_hw_decrypt == true) && (sta_info->hw_wsid >= SSV_NUM_HW_STA)) {
+            hw_update_watch_wsid(sc, sta_info->sta, sta_info, sta_priv->sta_idx, SSV6XXX_WSID_SEC_PAIRWISE
+                                 , SSV6XXX_WSID_OPS_DISABLE_CAPS);
+        }
+    }
+    if(vif_priv) {
+        if((key_idx != 0) && !list_empty(&vif_priv->sta_list)) {
+            struct ssv_sta_priv_data *sta_priv_iter;
+            list_for_each_entry(sta_priv_iter, &vif_priv->sta_list, list) {
+                if (((sta_priv_iter->sta_info->s_flags & STA_FLAG_VALID) == 0)
+                    || (sta_priv_iter->sta_info->hw_wsid < SSV_NUM_HW_STA))
+                    continue;
+                hw_update_watch_wsid(sc, sta_priv_iter->sta_info->sta,
+                                     sta_priv_iter->sta_info, sta_priv_iter->sta_idx, SSV6XXX_WSID_SEC_GROUP
+                                     , SSV6XXX_WSID_OPS_DISABLE_CAPS);
+            }
+        }
+    }
+#endif
+}
+void ssv6xxx_write_pairwise_keyidx_to_hw(struct ssv_hw *sh, int key_idx, int wsid)
+{
+    int address = 0;
+#ifdef SSV6200_ECO
+    u32 sec_key_tbl_base = sh->hw_sec_key[0];
+#else
+    u32 sec_key_tbl_base = sh->hw_sec_key;
+#endif
+    u32 sec_key_tbl = sec_key_tbl_base;
+    address = sec_key_tbl
+              + (3*sizeof(struct ssv6xxx_hw_key))
+              + wsid*sizeof(struct ssv6xxx_hw_sta_key);
+#ifdef SSV6200_ECO
+    address += (0x10000*wsid);
+#endif
+    SMAC_REG_WRITE(sh, address, (u32)key_idx);
+}
+static void ssv6xxx_write_key_to_hw(struct ssv_softc *sc, struct ssv6xxx_hw_sec *sram_key,
+                                    int wsid, int key_idx, enum SSV6XXX_WSID_SEC key_type)
+{
+    int address = 0;
+    int *pointer = NULL;
+#ifdef SSV6200_ECO
+    u32 sec_key_tbl_base = sc->sh->hw_sec_key[0];
+#else
+    u32 sec_key_tbl_base = sc->sh->hw_sec_key;
+#endif
+    u32 sec_key_tbl = sec_key_tbl_base;
+    int i;
+    switch (key_type) {
+    case SSV6XXX_WSID_SEC_PAIRWISE:
+        address = sec_key_tbl
+                  + (3*sizeof(struct ssv6xxx_hw_key))
+                  + wsid*sizeof(struct ssv6xxx_hw_sta_key);
+#ifdef SSV6200_ECO
+        address += (0x10000*wsid);
+#endif
+        pointer = (int *)&sram_key->sta_key[wsid];
+        for (i = 0; i < (sizeof(struct ssv6xxx_hw_sta_key)/4); i++)
+            SMAC_REG_WRITE(sc->sh, address+(i*4), *(pointer++));
+        break;
+    case SSV6XXX_WSID_SEC_GROUP:
+#ifdef SSV6200_ECO
+        sec_key_tbl += (0x10000 * wsid);
+        address = sec_key_tbl
+                  + ((key_idx - 1) * sizeof(struct ssv6xxx_hw_key));
+        pointer = (int *)&sram_key->group_key[key_idx - 1];
+        for (i = 0; i < (sizeof(struct ssv6xxx_hw_key)/4); i++)
+            SMAC_REG_WRITE(sc->sh, address+(i*4), *(pointer++));
+#endif
+        address = sec_key_tbl
+                  + (3*sizeof(struct ssv6xxx_hw_key))
+                  + (wsid*sizeof(struct ssv6xxx_hw_sta_key));
+        pointer = (int *)&sram_key->sta_key[wsid];
+        SMAC_REG_WRITE(sc->sh, address, *(pointer));
+        break;
+    default:
+        dev_dbg(sc->dev, KERN_ERR "invalid key type %d.",key_type);
+        break;
+    }
+}
+static void ssv6xxx_enable_fw_wsid(struct ssv_softc *sc, struct ieee80211_sta *sta,
+                                   struct ssv_sta_info *sta_info, enum SSV6XXX_WSID_SEC key_type)
+{
+#ifdef FW_WSID_WATCH_LIST
+    int wsid = sta_info->hw_wsid;
+    if (wsid >= SSV_NUM_HW_STA) {
+        hw_update_watch_wsid(sc, sta, sta_info, sta_info->hw_wsid
+                             , key_type, SSV6XXX_WSID_OPS_ENABLE_CAPS);
+    }
+#endif
+}
+static bool ssv6xxx_wep_use_hw_cipher(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv)
+{
+    bool ret = false;
+    if (sc->sh->cfg.use_sw_cipher) {
+        return ret;
+    }
+    if (sc->sh->cfg.use_wpa2_only) {
+        dev_warn(sc->dev, "Use WPA2 HW security mode only.\n");
+    }
+    if ((sc->sh->cfg.use_wpa2_only == 0) && (vif_priv->vif_idx == 0)) {
+        ret = true;
+    }
+    return ret;
+}
+static bool ssv6xxx_pairwise_wpa_use_hw_cipher(struct ssv_softc *sc,
+        struct ssv_vif_priv_data *vif_priv, enum SSV_CIPHER_E cipher,
+        struct ssv_sta_priv_data *sta_priv)
+{
+    bool ret = false;
+    struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
+    bool tdls_link = false, tdls_use_sw_cipher = false, tkip_use_sw_cipher = false;
+    bool use_non_ccmp = false;
+    int another_vif_idx = ((vif_priv->vif_idx + 1) % 2);
+    struct ssv_vif_priv_data *another_vif_priv =
+        (struct ssv_vif_priv_data *)sc->vif_info[another_vif_idx].vif_priv;
+    if (sc->sh->cfg.use_sw_cipher) {
+        return ret;
+    }
+    if (sc->sh->cfg.use_wpa2_only) {
+        dev_warn(sc->dev, "Use WPA2 HW security mode only.\n");
+    }
+    if (vif_info->if_type == NL80211_IFTYPE_STATION) {
+        struct ssv_sta_priv_data *first_sta_priv =
+            list_first_entry(&vif_priv->sta_list, struct ssv_sta_priv_data, list);
+        if (first_sta_priv->sta_idx != sta_priv->sta_idx) {
+            tdls_link = true;
+        }
+        dev_dbg(sc->dev, "first sta idx %d, current sta idx %d\n",first_sta_priv->sta_idx,sta_priv->sta_idx);
+    }
+    if ((tdls_link) && (vif_priv->pair_cipher != SSV_CIPHER_CCMP)
+        && (sc->sh->cfg.use_wpa2_only == false)) {
+        tdls_use_sw_cipher = true;
+    }
+    if (another_vif_priv != NULL) {
+        if ((another_vif_priv->pair_cipher != SSV_CIPHER_CCMP)
+            && (another_vif_priv->pair_cipher != SSV_CIPHER_NONE)) {
+            use_non_ccmp = true;
+            dev_dbg(sc->dev, "another vif use none ccmp\n");
+        }
+    }
+    if ((((tdls_link) && (vif_priv->pair_cipher != SSV_CIPHER_CCMP)) || (use_non_ccmp))
+        && (sc->sh->cfg.use_wpa2_only == 1) && (cipher == SSV_CIPHER_CCMP)) {
+        u32 val;
+        SMAC_REG_READ(sc->sh, ADR_RX_FLOW_DATA, &val);
+        if (((val >>4) & 0xF) != M_ENG_CPU) {
+            SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_DATA, ((val & 0xf) | (M_ENG_CPU<<4)
+                           | (val & 0xfffffff0) <<4));
+            dev_info(sc->dev, "orginal Rx_Flow %x , modified flow %x \n", val,
+                     ((val & 0xf) | (M_ENG_CPU<<4) | (val & 0xfffffff0) <<4));
+        }
+    }
+    if ((cipher == SSV_CIPHER_TKIP) && (sc->sh->cfg.use_wpa2_only == 1)) {
+        tkip_use_sw_cipher = true;
+    }
+    dev_dbg(sc->dev, "%s==> tkip use sw cipher %d\n",__func__,tkip_use_sw_cipher);
+    if ( ( ((vif_priv->vif_idx == 0) && (tdls_use_sw_cipher == false)
+            && (tkip_use_sw_cipher == false)))
+         || ( (cipher == SSV_CIPHER_CCMP)
+              && (sc->sh->cfg.use_wpa2_only == 1))) {
+        ret = true;
+    }
+    return ret;
+}
+static bool ssv6xxx_use_hw_encrypt(int cipher, struct ssv_softc *sc,
+                                   struct ssv_sta_priv_data *sta_priv, struct ssv_vif_priv_data *vif_priv )
+{
+    if ((cipher == SSV_CIPHER_TKIP)
+        || ((!(sc->sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_TX) ||
+             (sta_priv->sta_info->sta->ht_cap.ht_supported == false))
+            && (vif_priv->force_sw_encrypt == false))) {
+        return true;
+    } else {
+        return false;
+    }
+}
+static bool ssv6xxx_group_wpa_use_hw_cipher(struct ssv_softc *sc,
+        struct ssv_vif_priv_data *vif_priv, enum SSV_CIPHER_E cipher)
+{
+    int ret =false;
+    bool tkip_use_sw_cipher = false;
+    if (sc->sh->cfg.use_sw_cipher) {
+        return ret;
+    }
+    if (sc->sh->cfg.use_wpa2_only) {
+        dev_warn(sc->dev, "Use WPA2 HW security mode only.\n");
+    }
+    if ((cipher == SSV_CIPHER_TKIP) && (sc->sh->cfg.use_wpa2_only == 1)) {
+        tkip_use_sw_cipher = true;
+    }
+    if (((vif_priv->vif_idx == 0) && (tkip_use_sw_cipher == false))
+        || ((cipher == SSV_CIPHER_CCMP) && (sc->sh->cfg.use_wpa2_only == 1))) {
+        ret = true;
+    }
+    return ret;
+}
+static bool ssv6xxx_chk_if_support_hw_bssid(struct ssv_softc *sc,
+        int vif_idx)
+{
+    if (!vif_idx)
+        return true;
+    dev_dbg(sc->dev, " %s: VIF %d doesn't support HW BSSID\n", __func__, vif_idx);
+    return false;
+}
+static void ssv6xxx_chk_dual_vif_chg_rx_flow(struct ssv_softc *sc,
+        struct ssv_vif_priv_data *vif_priv)
+{
+    int another_vif_idx = ((vif_priv->vif_idx + 1) % 2);
+    struct ssv_vif_priv_data *another_vif_priv =
+        (struct ssv_vif_priv_data *)sc->vif_info[another_vif_idx].vif_priv;
+    if ( another_vif_priv != NULL) {
+        if (((SSV6XXX_USE_SW_DECRYPT(vif_priv)
+              && SSV6XXX_USE_HW_DECRYPT (another_vif_priv)))
+            || ((SSV6XXX_USE_HW_DECRYPT (vif_priv)
+                 && (SSV6XXX_USE_SW_DECRYPT(another_vif_priv))))) {
+            u32 val;
+            SMAC_REG_READ(sc->sh, ADR_RX_FLOW_DATA, &val);
+            if (((val >>4) & 0xF) != M_ENG_CPU) {
+                SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_DATA, ((val & 0xf) | (M_ENG_CPU<<4)
+                               | (val & 0xfffffff0) <<4));
+                dev_info(sc->dev, "orginal Rx_Flow %x , modified flow %x \n", val,
+                         ((val & 0xf) | (M_ENG_CPU<<4) | (val & 0xfffffff0) <<4));
+            } else {
+                dev_dbg(sc->dev, " doesn't need to change rx flow\n");
+            }
+        }
+    }
+}
+static void ssv6xxx_set_fw_hwwsid_sec_type(struct ssv_softc *sc, struct ieee80211_sta *sta,
+        struct ssv_sta_info *sta_info, struct ssv_vif_priv_data *vif_priv)
+{
+    if (sta) {
+        struct ssv_sta_priv_data *sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+        int sta_idx = sta_priv->sta_idx;
+        if (SSV6200_USE_HW_WSID(sta_idx)) {
+            if (SSV6XXX_USE_SW_DECRYPT(sta_priv)) {
+                u32 cipher_setting;
+                cipher_setting = ssv6200_hw_get_pair_type(sc->sh);
+                if (cipher_setting != ME_NONE) {
+                    u32 val;
+                    SMAC_REG_READ(sc->sh, ADR_RX_FLOW_DATA, &val);
+                    if (((val >>4) & 0xF) != M_ENG_CPU) {
+                        SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_DATA,
+                                       ((val & 0xf) | (M_ENG_CPU<<4)
+                                        | (val & 0xfffffff0) <<4));
+                        dev_info(sc->dev, "orginal Rx_Flow %x , modified flow %x \n",
+                                 val, ((val & 0xf) | (M_ENG_CPU<<4) | (val & 0xfffffff0) <<4));
+                    } else {
+                        dev_dbg(sc->dev, " doesn't need to change rx flow\n");
+                    }
+                }
+            }
+            if (sta_priv->has_hw_decrypt) {
+                hw_update_watch_wsid(sc, sta, sta_info, sta_idx,
+                                     SSV6XXX_WSID_SEC_HW, SSV6XXX_WSID_OPS_HWWSID_PAIRWISE_SET_TYPE);
+                dev_dbg(sc->dev, "set hw wsid %d cipher mode to HW cipher for pairwise key\n", sta_idx);
+            }
+        }
+    } else {
+        struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
+        if (vif_info->if_type == NL80211_IFTYPE_STATION) {
+            struct ssv_sta_priv_data *first_sta_priv =
+                list_first_entry(&vif_priv->sta_list, struct ssv_sta_priv_data, list);
+            if (first_sta_priv !=NULL)
+                if (SSV6200_USE_HW_WSID(first_sta_priv->sta_idx)) {
+                    if (vif_priv->has_hw_decrypt) {
+                        hw_update_watch_wsid(sc, sta, sta_info, first_sta_priv->sta_idx,
+                                             SSV6XXX_WSID_SEC_HW, SSV6XXX_WSID_OPS_HWWSID_GROUP_SET_TYPE);
+                        dev_dbg(sc->dev, "set hw wsid %d cipher mode to HW cipher for group  key\n"
+                               , first_sta_priv->sta_idx);
+                    }
+                }
+        }
+    }
+}
+static int ssv6xxx_set_rx_flow(struct ssv_hw *sh, enum ssv_rx_flow type, u32 rxflow)
+{
+    switch (type) {
+    case RX_DATA_FLOW:
+        return SMAC_REG_WRITE(sh, ADR_RX_FLOW_DATA, rxflow);
+    case RX_MGMT_FLOW:
+        return SMAC_REG_WRITE(sh, ADR_RX_FLOW_MNG, rxflow);
+    case RX_CTRL_FLOW:
+        return SMAC_REG_WRITE(sh, ADR_RX_FLOW_CTRL, rxflow);
+    default:
+        return 1;
+    }
+}
+static void ssv6xxx_restore_rx_flow(struct ssv_softc *sc,
+                                    struct ssv_vif_priv_data *vif_priv, struct ieee80211_sta *sta)
+{
+    struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
+    int another_vif_idx = ((vif_priv->vif_idx + 1) % 2);
+    struct ssv_vif_priv_data *another_vif_priv =
+        (struct ssv_vif_priv_data *)sc->vif_info[another_vif_idx].vif_priv;
+    if (vif_info->if_type != NL80211_IFTYPE_AP) {
+        if ((SSV6XXX_USE_SW_DECRYPT(vif_priv)
+             && SSV6XXX_USE_HW_DECRYPT (another_vif_priv))
+            || (SSV6XXX_USE_SW_DECRYPT(another_vif_priv)
+                && SSV6XXX_USE_HW_DECRYPT (vif_priv))) {
+#ifdef CONFIG_SSV_HW_ENCRYPT_SW_DECRYPT
+            ssv6xxx_set_rx_flow(sc->sh, RX_DATA_FLOW, RX_HCI);
+#else
+            ssv6xxx_set_rx_flow(sc->sh, RX_DATA_FLOW, RX_CIPHER_HCI);
+#endif
+            dev_dbg(sc->dev, "redirect Rx flow for disconnect\n");
+        }
+    } else if (vif_info->if_type == NL80211_IFTYPE_AP) {
+        if (sta == NULL) {
+            if (SSV6XXX_USE_SW_DECRYPT(another_vif_priv)
+                && SSV6XXX_USE_HW_DECRYPT (vif_priv)) {
+#ifdef CONFIG_SSV_HW_ENCRYPT_SW_DECRYPT
+                ssv6xxx_set_rx_flow(sc->sh, RX_DATA_FLOW, RX_HCI);
+#else
+                ssv6xxx_set_rx_flow(sc->sh, RX_DATA_FLOW, RX_CIPHER_HCI);
+#endif
+                dev_dbg(sc->dev, "redirect Rx flow for disconnect, and clear group key type\n");
+            }
+        }
+    }
+}
+int ssv6xxx_get_tx_desc_ctype(struct sk_buff *skb)
+{
+    struct ssv6200_tx_desc *tx_desc = (struct ssv6200_tx_desc *) skb->data;
+    return tx_desc->c_type ;
+}
+int ssv6xxx_get_tx_desc_txq_idx(struct sk_buff *skb)
+{
+    struct ssv6200_tx_desc *tx_desc = (struct ssv6200_tx_desc *) skb->data;
+    return tx_desc->txq_idx ;
+}
+void ssv6xxx_phy_enable(struct ssv_hw *sh, bool val)
+{
+    SMAC_REG_SET_BITS(sh, ADR_PHY_EN_1, (val << RG_PHY_MD_EN_SFT), RG_PHY_MD_EN_MSK);
+}
+int ssv6xxx_update_null_func_txinfo(struct ssv_softc *sc, struct ieee80211_sta *sta, struct sk_buff *skb)
+{
+    return -1;
+}
+bool ssv6xxx_nullfun_frame_filter(struct ssv_hw *sh, struct sk_buff *skb)
+{
+    return false;
+}
+void ssv6xxx_reset_sysplf(struct ssv_hw *sh)
+{
+    SMAC_REG_SET_BITS(sh, ADR_BRG_SW_RST, (1 << MCU_SW_RST_SFT), MCU_SW_RST_MSK);
+}
+void tu_ssv6xxx_init_iqk(struct ssv_hw *sh)
+{
+#ifdef CONFIG_SSV_CABRIO_E
+    sh->iqk_cfg.cfg_xtal = SSV6XXX_IQK_CFG_XTAL_26M;
+#ifdef CONFIG_SSV_DPD
+    sh->iqk_cfg.cfg_pa = SSV6XXX_IQK_CFG_PA_LI_MPB;
+#else
+    sh->iqk_cfg.cfg_pa = SSV6XXX_IQK_CFG_PA_DEF;
+#endif
+    sh->iqk_cfg.cfg_pabias_ctrl = 0;
+    sh->iqk_cfg.cfg_pacascode_ctrl = 0;
+    sh->iqk_cfg.cfg_tssi_trgt = 26;
+    sh->iqk_cfg.cfg_tssi_div = 3;
+    sh->iqk_cfg.cfg_def_tx_scale_11b = 0x75;
+    sh->iqk_cfg.cfg_def_tx_scale_11b_p0d5 = 0x75;
+    sh->iqk_cfg.cfg_def_tx_scale_11g = 0x80;
+    sh->iqk_cfg.cfg_def_tx_scale_11g_p0d5 = 0x80;
+    sh->iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_INIT_CALI;
+    sh->iqk_cfg.fx_sel = SSV6XXX_IQK_TEMPERATURE
+                         + SSV6XXX_IQK_RXDC
+                         + SSV6XXX_IQK_RXRC
+                         + SSV6XXX_IQK_TXDC
+                         + SSV6XXX_IQK_TXIQ
+                         + SSV6XXX_IQK_RXIQ;
+#ifdef CONFIG_SSV_DPD
+    sh->iqk_cfg.fx_sel += SSV6XXX_IQK_PAPD;
+#endif
+#endif
+}
+void ssv6xxx_save_hw_status(struct ssv_softc *sc)
+{
+    struct ssv_hw *sh = sc->sh;
+    int i = 0;
+    int address = 0;
+    u32 word_data = 0;
+    u32 sec_key_tbl_base = sh->hw_sec_key[0];
+    u32 sec_key_tbl = sec_key_tbl_base;
+    for (i = 0; i < sizeof(struct ssv6xxx_hw_sec); i += 4) {
+        address = sec_key_tbl + i;
+        SMAC_REG_READ(sh, address, &word_data);
+        sh->write_hw_config_cb(sh->write_hw_config_args, address, word_data);
+    }
+}
+u64 ssv6xxx_get_ic_time_tag(struct ssv_hw *sh)
+{
+    u32 regval;
+    if(SMAC_REG_READ(sh, ADR_IC_TIME_TAG_1, &regval));
+    sh->chip_tag = ((u64) regval<<32);
+    if(SMAC_REG_READ(sh, ADR_IC_TIME_TAG_0, &regval));
+    sh->chip_tag |= (regval);
+    return sh->chip_tag;
+}
+void ssv6xxx_edca_enable(struct ssv_hw *sh, bool val)
+{
+    return;
+}
+void ssv6xxx_edca_stat(struct ssv_hw *sh)
+{
+}
+void ssv6xxx_send_tx_poll_cmd(struct ssv_hw *sh, u32 type)
+{
+    return;
+}
+int ssv6xxx_set_rx_ctrl_flow(struct ssv_hw *sh)
+{
+    return ssv6xxx_set_rx_flow(sh, RX_CTRL_FLOW, RX_CPU_HCI);
+}
+int ssv6xxx_get_rx_desc_hdr_offset(struct sk_buff *skb)
+{
+    struct ssv6200_rx_desc *rx_desc = (struct ssv6200_rx_desc *)skb->data;
+    return rx_desc->hdr_offset;
+}
+void ssv6xxx_fill_lpbk_tx_desc(struct sk_buff *skb, int security, unsigned char rate)
+{
+    return;
+}
+int ssv6xxx_chk_rx_rate_desc(struct ssv_hw *sh, struct sk_buff *skb);
+{
+    return 0;
+}
+int ssv6xxx_update_efuse_setting(struct ssv_hw *sh)
+{
+    return 0;
+}
+void ssv6xxx_do_temperature_compensation(struct ssv_hw *sh);
+{
+    return;
+}
+void ssv6xxx_pll_chk(struct ssv_hw *sh);
+{
+    return;
+}
+#ifdef CONFIG_SSV_CABRIO_E
+static void ssv6xxx_save_default_ipd_chcfg(struct ssv_hw *sh)
+{
+    int i;
+    if((sh->cfg.chip_identity == SSV6051Z) || (sh->cfg.chip_identity == SSV6051P)) {
+        for (i = 0; i < sh->ch_cfg_size; i++) {
+            SMAC_REG_READ(sh, sh->p_ch_cfg[i].reg_addr, &sh->p_ch_cfg[i].ch1_12_value);
+        }
+    }
+}
+#endif
+static void ssv6xxx_set_dur_burst_sifs_g(struct ssv_hw *sh, u32 val)
+{
+    u32 regval;
+    SMAC_REG_READ(sh, ADR_MTX_DUR_SIFS_G, &regval);
+    regval &= MTX_DUR_BURST_SIFS_G_I_MSK;
+    regval |= val << MTX_DUR_BURST_SIFS_G_SFT ;
+    SMAC_REG_WRITE(sh, ADR_MTX_DUR_SIFS_G, regval);
+}
+static void ssv6xxx_set_dur_slot(struct ssv_hw *sh, u32 val)
+{
+    u32 regval;
+    SMAC_REG_READ(sh, ADR_MTX_DUR_SIFS_G, &regval);
+    regval &= MTX_DUR_SLOT_G_I_MSK;
+    regval |= val << MTX_DUR_SLOT_G_SFT;
+    SMAC_REG_WRITE(sh, ADR_MTX_DUR_SIFS_G, regval);
+    SMAC_REG_READ(sh, ADR_MTX_DUR_IFS, &regval);
+    regval &= MTX_DUR_SLOT_I_MSK;
+    regval |= val << MTX_DUR_SLOT_SFT;
+    SMAC_REG_WRITE(sh, ADR_MTX_DUR_IFS, regval);
+}
+static void ssv6xxx_set_hw_wsid(struct ssv_softc *sc, struct ieee80211_vif *vif,
+                                struct ieee80211_sta *sta, int wsid)
+{
+    struct ssv_vif_priv_data *vif_priv = (struct ssv_vif_priv_data *)vif->drv_priv;
+    struct ssv_sta_priv_data *sta_priv_dat=(struct ssv_sta_priv_data *)sta->drv_priv;
+    struct ssv_sta_info *sta_info;
+    int i;
+    sta_info = &sc->sta_info[wsid];
+    if (sta_priv_dat->sta_idx < SSV_NUM_HW_STA) {
+        u32 reg_wsid[] = {ADR_WSID0, ADR_WSID1};
+        u32 reg_wsid_tid0[] = {ADR_WSID0_TID0_RX_SEQ, ADR_WSID1_TID0_RX_SEQ};
+        u32 reg_wsid_tid7[] = {ADR_WSID0_TID7_RX_SEQ, ADR_WSID1_TID7_RX_SEQ};
+#if 0
+        SMAC_REG_READ(sc->sh, reg_wsid[wsid], &reg_val);
+        if ((reg_val & 0x01) == 0) {
+#endif
+            SMAC_REG_WRITE(sc->sh, reg_wsid[wsid]+4, *((u32 *)&sta->addr[0]));
+            SMAC_REG_WRITE(sc->sh, reg_wsid[wsid]+8, *((u32 *)&sta->addr[4]));
+            SMAC_REG_WRITE(sc->sh, reg_wsid[wsid], 1);
+            for (i = reg_wsid_tid0[wsid]; i <= reg_wsid_tid7[wsid]; i += 4)
+                SMAC_REG_WRITE(sc->sh, i, 0);
+            ssv6xxx_rc_hw_reset(sc, sta_priv_dat->rc_idx, wsid);
+            sta_info->hw_wsid = sta_priv_dat->sta_idx;
+        }
+#ifdef FW_WSID_WATCH_LIST
+        else if ( (vif_priv->vif_idx == 0)
+                  || sc->sh->cfg.use_wpa2_only
+                ) {
+            sta_info->hw_wsid = sta_priv_dat->sta_idx;
+        }
+#endif
+    }
+    static void ssv6xxx_add_fw_wsid(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv,
+                                    struct ieee80211_sta *sta, struct ssv_sta_info *sta_info) {
+#ifdef FW_WSID_WATCH_LIST
+        struct ssv_sta_priv_data *sta_priv_dat=(struct ssv_sta_priv_data *)sta->drv_priv;
+        if (sta_info->hw_wsid >= SSV_NUM_HW_STA) {
+            int fw_sec_caps = SSV6XXX_WSID_SEC_NONE;
+            if (sta_priv_dat->has_hw_decrypt)
+                fw_sec_caps = SSV6XXX_WSID_SEC_PAIRWISE;
+            if (vif_priv->need_sw_decrypt)
+                fw_sec_caps |= SSV6XXX_WSID_SEC_GROUP;
+            hw_update_watch_wsid(sc, sta, sta_info, sta_priv_dat->sta_idx,
+                                 fw_sec_caps, SSV6XXX_WSID_OPS_ADD);
+        } else if (SSV6200_USE_HW_WSID(sta_priv_dat->sta_idx)) {
+            hw_update_watch_wsid(sc, sta, sta_info, sta_priv_dat->sta_idx,
+                                 SSV6XXX_WSID_SEC_SW, SSV6XXX_WSID_OPS_HWWSID_PAIRWISE_SET_TYPE);
+            hw_update_watch_wsid(sc, sta, sta_info, sta_priv_dat->sta_idx,
+                                 SSV6XXX_WSID_SEC_SW, SSV6XXX_WSID_OPS_HWWSID_GROUP_SET_TYPE);
+        }
+#endif
+    }
+    static void ssv6xxx_del_hw_wsid(struct ssv_softc *sc, int hw_wsid) {
+        if ((hw_wsid != -1) && (hw_wsid < SSV_NUM_HW_STA)) {
+            u32 reg_wsid[] = {ADR_WSID0, ADR_WSID1};
+            SMAC_REG_WRITE(sc->sh, reg_wsid[hw_wsid], 0x00);
+        }
+    }
+    static void ssv6xxx_set_wmm_param(struct ssv_softc *sc,
+                                      const struct ieee80211_tx_queue_params *params, u16 queue) {
+        u32 cw;
+        u8 hw_txqid = sc->tx.hw_txqid[queue];
+#if 1
+        cw = (params->aifs-1)&0xf;
+#else
+        cw = params->aifs&0xf;
+#endif
+        cw|= ((ilog2(params->cw_min+1))&0xf)<<TXQ1_MTX_Q_ECWMIN_SFT;
+        cw|= ((ilog2(params->cw_max+1))&0xf)<<TXQ1_MTX_Q_ECWMAX_SFT;
+        cw|= ((params->txop)&0xff)<<TXQ1_MTX_Q_TXOP_LIMIT_SFT;
+        SMAC_REG_WRITE(sc->sh, ADR_TXQ0_MTX_Q_AIFSN+0x100*hw_txqid, cw);
+    }
+#endif
+    static void hw_crypto_key_clear(struct ieee80211_hw *hw, int index, struct ieee80211_key_conf *key,
+                                    struct ssv_vif_priv_data *vif_priv, struct ssv_sta_priv_data *sta_priv) {
+#ifdef FW_WSID_WATCH_LIST
+        struct ssv_softc *sc = hw->priv;
+        if ((index == 0) && (sta_priv == NULL))
+            return;
+#endif
+        if ((index < 0) || (index >= 4))
+            return;
+#if 0
+        if(sta_info) {
+            sta_info->s_flags &= ~STA_FLAG_ENCRYPT;
+        }
+#endif
+        if (index > 0) {
+            if (vif_priv)
+                vif_priv->group_key_idx = 0;
+            if (sta_priv)
+                sta_priv->group_key_idx = 0;
+        }
+#ifdef FW_WSID_WATCH_LIST
+        SSV_DISABLE_FW_WSID(sc, index, sta_priv, vif_priv);
+#endif
+#if 0
+        if (index == 0) {
+            address = sec_key_tbl+(3*sizeof(struct ssv6xxx_hw_key))
+                      + wsid*sizeof(struct ssv6xxx_hw_sta_key);
+            for(i=0; i<(sizeof(struct ssv6xxx_hw_sta_key)/4); i++)
+                SMAC_REG_WRITE(sc->sh, address+i*4, 0x0);
+        } else {
+            address = sec_key_tbl+((index-1)*sizeof(struct ssv6xxx_hw_key));
+            for(i=0; i<(sizeof(struct ssv6xxx_hw_key)/4); i++)
+                SMAC_REG_WRITE(sc->sh,address+i*4, 0x0);
+        }
+#endif
+    }
+    void _set_wep_sw_crypto_key (struct ssv_softc *sc,
+                                 struct ssv_vif_info *vif_info,
+                                 struct ssv_sta_info *sta_info,
+                                 void *param) {
+        struct ssv_sta_priv_data *sta_priv = (struct ssv_sta_priv_data *)sta_info->sta->drv_priv;
+        struct ssv_vif_priv_data *vif_priv = (struct ssv_vif_priv_data *)vif_info->vif->drv_priv;
+        sta_priv->has_hw_encrypt = vif_priv->has_hw_encrypt;
+        sta_priv->has_hw_decrypt = vif_priv->has_hw_decrypt;
+        sta_priv->need_sw_encrypt = vif_priv->need_sw_encrypt;
+        sta_priv->need_sw_decrypt = vif_priv->need_sw_decrypt;
+#ifdef USE_LOCAL_WEP_CRYPTO
+        sta_priv->crypto_data.ops = vif_priv->crypto_data.ops;
+        sta_priv->crypto_data.priv = vif_priv->crypto_data.priv;
+#endif
+    }
+#ifndef SSV_SUPPORT_HAL
+    static void _set_wep_hw_crypto_pair_key (struct ssv_softc *sc,
+            struct ssv_vif_info *vif_info,
+            struct ssv_sta_info *sta_info,
+            void *param) {
+        int wsid = sta_info->hw_wsid;
+        struct ssv6xxx_hw_sec *sram_key = (struct ssv6xxx_hw_sec *)param;
+        u8 *key = sram_key->sta_key[0].pair.key;
+        u32 key_len = *(u16 *)&sram_key->sta_key[0].reserve[0];
+        struct ssv_sta_priv_data *sta_priv = (struct ssv_sta_priv_data *)sta_info->sta->drv_priv;
+        struct ssv_vif_priv_data *vif_priv = (struct ssv_vif_priv_data *)vif_info->vif->drv_priv;
+        if (wsid == (-1))
+            return;
+        sram_key->sta_key[wsid].pair_key_idx = 0;
+        sram_key->sta_key[wsid].group_key_idx = 0;
+        sta_priv->has_hw_encrypt = vif_priv->has_hw_encrypt;
+        sta_priv->has_hw_decrypt = vif_priv->has_hw_decrypt;
+        sta_priv->need_sw_encrypt = vif_priv->need_sw_encrypt;
+        sta_priv->need_sw_decrypt = vif_priv->need_sw_decrypt;
+        if (wsid != 0)
+            memcpy(sram_key->sta_key[wsid].pair.key, key, key_len);
+        SSV_WRITE_KEY_TO_HW(sc, vif_priv, sram_key, wsid, -1, SSV6XXX_WSID_SEC_PAIRWISE);
+    }
+    static void _set_wep_hw_crypto_group_key (struct ssv_softc *sc,
+            struct ssv_vif_info *vif_info,
+            struct ssv_sta_info *sta_info,
+            void *param) {
+        int wsid = sta_info->hw_wsid;
+        struct ssv6xxx_hw_sec *sram_key = (struct ssv6xxx_hw_sec *)param;
+        u32 key_idx = sram_key->sta_key[0].pair_key_idx;
+        struct ssv_sta_priv_data *sta_priv = (struct ssv_sta_priv_data *)sta_info->sta->drv_priv;
+        struct ssv_vif_priv_data *vif_priv = (struct ssv_vif_priv_data *)vif_info->vif->drv_priv;
+        if (wsid == (-1))
+            return;
+        if (wsid != 0) {
+            sram_key->sta_key[wsid].pair_key_idx = key_idx;
+            sram_key->sta_key[wsid].group_key_idx = key_idx;
+            sta_priv->has_hw_encrypt = vif_priv->has_hw_encrypt;
+            sta_priv->has_hw_decrypt = vif_priv->has_hw_decrypt;
+            sta_priv->need_sw_encrypt = vif_priv->need_sw_encrypt;
+            sta_priv->need_sw_decrypt = vif_priv->need_sw_decrypt;
+        }
+        SSV_WRITE_KEY_TO_HW(sc, vif_priv, sram_key, wsid, key_idx, SSV6XXX_WSID_SEC_GROUP);
+    }
+    static int hw_crypto_key_write_wep(struct ssv_softc *sc,
+                                       struct ieee80211_key_conf *keyconf,
+                                       u8 algorithm,
+                                       struct ssv_vif_info *vif_info) {
+        struct ssv6xxx_hw_sec *sramKey = &vif_info->sramKey;
+#ifndef SSV6200_ECO
+        int address = 0x00;
+        int *pointer=NULL;
+        u32 sec_key_tbl=sc->sh->hw_sec_key;
+        int i;
+#endif
+        if (keyconf->keyidx == 0) {
+            ssv6xxx_foreach_vif_sta(sc, vif_info, _set_wep_hw_crypto_pair_key, sramKey);
+        } else {
+#ifndef SSV6200_ECO
+            address = sec_key_tbl
+                      + ((keyconf->keyidx-1) * sizeof(struct ssv6xxx_hw_key));
+            pointer = (int *)&sramKey->group_key[keyconf->keyidx-1];
+            for (i=0; i<(sizeof(struct ssv6xxx_hw_key)/4); i++)
+                SMAC_REG_WRITE(sc->sh, address+(i*4), *(pointer++));
+#endif
+            ssv6xxx_foreach_vif_sta(sc, vif_info, _set_wep_hw_crypto_group_key, sramKey);
+        }
+        return 0;
+    }
+    static void _set_aes_tkip_hw_crypto_group_key (struct ssv_softc *sc,
+            struct ssv_vif_info *vif_info,
+            struct ssv_sta_info *sta_info,
+            void *param) {
+        int wsid = sta_info->hw_wsid;
+        struct ssv6xxx_hw_sec *sramKey = &(vif_info->sramKey);
+        int index = *(u8 *)param;
+        if (wsid == (-1))
+            return;
+        BUG_ON(index == 0);
+        dev_dbg(sc->dev, "Set CCMP/TKIP group key %d to WSID %d.\n", index, wsid);
+        sramKey->sta_key[wsid].group_key_idx = index;
+#ifdef SSV6200_ECO
+        if (vif_info->vif_priv != NULL)
+            dev_info(sc->dev, "Write group key %d to VIF %d \n",
+                     index, vif_info->vif_priv->vif_idx);
+        else
+            dev_err(sc->dev, "NULL VIF.\n");
+#endif
+        SSV_WRITE_KEY_TO_HW(sc, vif_info->vif_priv, sramKey, wsid, index, SSV6XXX_WSID_SEC_GROUP);
+        SSV_ENABLE_FW_WSID(sc, sta_info->sta, sta_info, SSV6XXX_WSID_SEC_GROUP);
+    }
+    static int _write_pairwise_key_to_hw (struct ssv_softc *sc,
+                                          int index, u8 algorithm,
+                                          const u8 *key, int key_len,
+                                          struct ieee80211_key_conf *keyconf,
+                                          struct ssv_vif_priv_data *vif_priv,
+                                          struct ssv_sta_priv_data *sta_priv) {
+        struct ssv6xxx_hw_sec *sramKey;
+        int wsid = (-1);
+        if (sta_priv == NULL) {
+            dev_err(sc->dev, "Set pair-wise key with NULL STA.\n");
+            return -EOPNOTSUPP;
+        }
+        wsid = sta_priv->sta_info->hw_wsid;
+        if ((wsid < 0) || (wsid >= SSV_NUM_STA)) {
+            dev_err(sc->dev, "Set pair-wise key to invalid WSID %d.\n", wsid);
+            return -EOPNOTSUPP;
+        }
+#if 0
+        sta_info->s_flags |= STA_FLAG_ENCRYPT;
+#endif
+        dev_dbg(sc->dev, "Set STA %d's pair-wise key of %d bytes.\n", wsid, key_len);
+        sramKey = &(sc->vif_info[vif_priv->vif_idx].sramKey);
+        sramKey->sta_key[wsid].pair_key_idx = 0;
+        sramKey->sta_key[wsid].group_key_idx = vif_priv->group_key_idx;
+        memcpy(sramKey->sta_key[wsid].pair.key, key, key_len);
+        SSV_WRITE_KEY_TO_HW(sc, vif_priv, sramKey, wsid, index, SSV6XXX_WSID_SEC_PAIRWISE);
+        SSV_ENABLE_FW_WSID(sc, sta_priv->sta_info->sta, sta_priv->sta_info,
+                           SSV6XXX_WSID_SEC_PAIRWISE);
+        return 0;
+    }
+    static int _write_group_key_to_hw (struct ssv_softc *sc,
+                                       int index, u8 algorithm,
+                                       const u8 *key, int key_len,
+                                       struct ieee80211_key_conf *keyconf,
+                                       struct ssv_vif_priv_data *vif_priv,
+                                       struct ssv_sta_priv_data *sta_priv) {
+        struct ssv6xxx_hw_sec *sramKey;
+#ifndef SSV6200_ECO
+        u32 sec_key_tbl_base = sc->sh->hw_sec_key;
+        int address = 0;
+        int *pointer = NULL;
+        int i;
+#endif
+        int wsid = sta_priv ? sta_priv->sta_info->hw_wsid : (-1);
+        int ret = 0;
+        if (vif_priv == NULL) {
+            dev_err(sc->dev, "Setting group key to NULL VIF\n");
+            return -EOPNOTSUPP;
+        }
+        dev_dbg(sc->dev, "Setting VIF %d group key %d of length %d to WSID %d.\n",
+                 vif_priv->vif_idx, index, key_len, wsid);
+        sramKey = &(sc->vif_info[vif_priv->vif_idx].sramKey);
+        vif_priv->group_key_idx = index;
+        if (sta_priv)
+            sta_priv->group_key_idx = index;
+        memcpy(sramKey->group_key[index-1].key, key, key_len);
+#ifndef SSV6200_ECO
+        address = sec_key_tbl_base + ((index-1)*sizeof(struct ssv6xxx_hw_key));
+        pointer = (int *)&sramKey->group_key[index-1];
+        for (i = 0; i < (sizeof(struct ssv6xxx_hw_key)/4); i++)
+            SMAC_REG_WRITE(sc->sh, address+(i*4), *(pointer++));
+#endif
+        WARN_ON(sc->vif_info[vif_priv->vif_idx].vif_priv == NULL);
+        ssv6xxx_foreach_vif_sta(sc, &sc->vif_info[vif_priv->vif_idx],
+                                _set_aes_tkip_hw_crypto_group_key, &index);
+        ret = 0;
+        return ret;
+    }
+    static void _store_wep_key(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv,
+                               struct ssv_sta_priv_data *sta_priv, enum SSV_CIPHER_E cipher, struct ieee80211_key_conf *key) {
+        struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
+        struct ssv6xxx_hw_sec *sram_key = &vif_info->sramKey;
+        sram_key->sta_key[0].pair_key_idx = key->keyidx;
+        sram_key->sta_key[0].group_key_idx = key->keyidx;
+        *(u16 *)&sram_key->sta_key[0].reserve[0] = key->keylen;
+        if (key->keyidx == 0) {
+            memcpy(sram_key->sta_key[0].pair.key, key->key, key->keylen);
+        } else {
+            memcpy(sram_key->group_key[key->keyidx - 1].key, key->key, key->keylen);
+        }
+        if ( ssv6xxx_wep_use_hw_cipher(sc, vif_priv)) {
+            ssv6200_hw_set_pair_type(sc->sh, cipher);
+            ssv6200_hw_set_group_type(sc->sh, cipher);
+            hw_crypto_key_write_wep(sc, key, cipher, &sc->vif_info[vif_priv->vif_idx]);
+        }
+    }
+#endif
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0)
+    static enum SSV_CIPHER_E _prepare_key (struct ieee80211_key_conf *key, struct ssv_softc *sc) {
+        enum SSV_CIPHER_E cipher;
+        switch (key->cipher) {
+        case WLAN_CIPHER_SUITE_WEP40:
+            cipher = SSV_CIPHER_WEP40;
+            break;
+        case WLAN_CIPHER_SUITE_WEP104:
+            cipher = SSV_CIPHER_WEP104;
+            break;
+        case WLAN_CIPHER_SUITE_TKIP:
+            cipher = SSV_CIPHER_TKIP;
+            break;
+        case WLAN_CIPHER_SUITE_CCMP:
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0)
+            if(sc->ccmp_h_sel)
+                key->flags |= (IEEE80211_KEY_FLAG_SW_MGMT | IEEE80211_KEY_FLAG_GENERATE_IV);
+            else
+                key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
+#else
+            if(sc->ccmp_h_sel)
+                key->flags |= (IEEE80211_KEY_FLAG_SW_MGMT_TX | IEEE80211_KEY_FLAG_RX_MGMT | IEEE80211_KEY_FLAG_GENERATE_IV);
+            else
+                key->flags |= (IEEE80211_KEY_FLAG_SW_MGMT_TX | IEEE80211_KEY_FLAG_RX_MGMT);
+#endif
+            cipher = SSV_CIPHER_CCMP;
+            break;
+#ifdef CONFIG_SSV_WAPI
+        case WLAN_CIPHER_SUITE_SMS4:
+            dev_dbg(sc->dev, "[I] %s, algorithm = WLAN_CIPHER_SUITE_SMS4\n", __func__);
+            cipher = SSV_CIPHER_SMS4;
+            break;
+#endif
+        default:
+            cipher = SSV_CIPHER_INVALID;
+            break;
+        }
+        return cipher;
+    }
+#else
+    static enum SSV_CIPHER_E _prepare_key (struct ieee80211_key_conf *key, struct ssv_softc *sc) {
+        enum SSV_CIPHER_E cipher;
+        switch (key->alg) {
+        case ALG_WEP:
+            if(key->keylen == 5)
+                cipher = SSV_CIPHER_WEP40;
+            else
+                cipher = SSV_CIPHER_WEP104;
+            break;
+        case ALG_TKIP:
+            cipher = SSV_CIPHER_TKIP;
+            key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
+            break;
+        case ALG_CCMP:
+            cipher = SSV_CIPHER_CCMP;
+            key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
+            break;
+        default:
+            cipher = SSV_CIPHER_INVALID;
+            break;
+        }
+        return cipher;
+    }
+#endif
+    int _set_key_wep (struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv,
+                      struct ssv_sta_priv_data *sta_priv, enum SSV_CIPHER_E cipher,
+                      struct ieee80211_key_conf *key) {
+        int ret = 0;
+        struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
+        dev_dbg(sc->dev, KERN_ERR "Set WEP %02X %02X %02X %02X %02X %02X %02X %02X... (%d %d)\n",
+               key->key[0], key->key[1], key->key[2], key->key[3],
+               key->key[4], key->key[5], key->key[6], key->key[7],
+               key->keyidx, key->keylen);
+        if ( SSV_WEP_USE_HW_CIPHER(sc, vif_priv)) {
+            vif_priv->has_hw_decrypt = true;
+            vif_priv->has_hw_encrypt = true;
+            vif_priv->need_sw_decrypt = false;
+            vif_priv->need_sw_encrypt = false;
+            vif_priv->use_mac80211_decrypt = false;
+        } else
+#ifdef USE_LOCAL_WEP_CRYPTO
+        {
+            INIT_WRITE_CRYPTO_DATA(crypto_data, &vif_priv->crypto_data);
+            vif_priv->has_hw_decrypt = false;
+            vif_priv->has_hw_encrypt = false;
+            if ((vif_priv->wep_idx >= 0) && (vif_priv->wep_idx < key->keyidx))
+                return -EOPNOTSUPP;
+            START_WRITE_CRYPTO_DATA(crypto_data);
+            if (crypto_data->ops && crypto_data->priv) {
+                crypto_data->ops->deinit(crypto_data->priv);
+                crypto_data->ops = NULL;
+                crypto_data->priv = NULL;
+            }
+            crypto_data->ops = get_crypto_wep_ops();
+            crypto_data->priv = NULL;
+            if (crypto_data->ops)
+                crypto_data->priv = crypto_data->ops->init(key->keyidx);
+            if (crypto_data->priv) {
+                crypto_data->ops->set_key(key->key, key->keylen, NULL, crypto_data->priv);
+                dev_err(sc->dev, "[Local Crypto]: VIF gets WEP crypto OK!\n");
+                dev_err(sc->dev, "[Local Crypto]: Use driver's encrypter.\n");
+                vif_priv->need_sw_decrypt = true;
+                vif_priv->need_sw_encrypt = true;
+                vif_priv->use_mac80211_decrypt = false;
+            } else {
+                dev_err(sc->dev, "[Local Crypto]: Failed to initialize driver's crypto!\n");
+                dev_info(sc->dev, "[Local Crypto]: Use MAC80211's encrypter.\n");
+                vif_priv->need_sw_decrypt = false;
+                vif_priv->need_sw_encrypt = false;
+                vif_priv->use_mac80211_decrypt = true;
+                ret = -EOPNOTSUPP;
+            }
+            ssv6xxx_foreach_vif_sta(sc, vif_info, _set_wep_sw_crypto_key, NULL);
+            END_WRITE_CRYPTO_DATA(crypto_data);
+        }
+#else
+        {
+            vif_priv->has_hw_decrypt = false;
+            vif_priv->has_hw_encrypt = false;
+            vif_priv->need_sw_decrypt = false;
+            vif_priv->need_sw_encrypt = false;
+            vif_priv->use_mac80211_decrypt = true;
+            ssv6xxx_foreach_vif_sta(sc, vif_info, _set_wep_sw_crypto_key, NULL);
+            ret = -EOPNOTSUPP;
+        }
+#endif
+        SSV_STORE_WEP_KEY(sc, vif_priv, sta_priv, cipher, key);
+        vif_priv->pair_cipher = vif_priv->group_cipher = cipher;
+        vif_priv->is_security_valid = true;
+        return ret;
+    }
+    static int _set_pairwise_key_tkip_ccmp (struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv,
+                                            struct ssv_sta_priv_data *sta_priv, enum SSV_CIPHER_E cipher,
+                                            struct ieee80211_key_conf *key) {
+        int ret = 0;
+        const char *cipher_name = (cipher == SSV_CIPHER_CCMP) ? "CCMP" : "TKIP";
+        if (sta_priv == NULL) {
+            dev_err(sc->dev, "Setting pairwise TKIP/CCMP key to NULL STA.\n");
+            return -EOPNOTSUPP;
+        }
+        if (SSV_PAIRWISE_WPA_USE_HW_CIPHER( sc, vif_priv, cipher, sta_priv)) {
+            sta_priv->has_hw_decrypt = true;
+            sta_priv->need_sw_decrypt = false;
+            sta_priv->use_mac80211_decrypt = false;
+            if (SSV_USE_HW_ENCRYPT(cipher, sc, sta_priv, vif_priv)) {
+                dev_dbg(sc->dev, "STA %d uses HW encrypter for pairwise.\n", sta_priv->sta_idx);
+                sta_priv->has_hw_encrypt = true;
+                sta_priv->need_sw_encrypt = false;
+                sta_priv->use_mac80211_decrypt = false;
+                ret = 0;
+            } else {
+                sta_priv->has_hw_encrypt = false;
+#ifdef USE_LOCAL_CCMP_CRYPTO
+                sta_priv->need_sw_encrypt = true;
+                sta_priv->use_mac80211_decrypt = false;
+                ret = 0;
+#else
+                sta_priv->need_sw_encrypt = false;
+                sta_priv->use_mac80211_decrypt = true;
+                ret = -EOPNOTSUPP;
+#endif
+            }
+        } else {
+            sta_priv->has_hw_encrypt = false;
+            sta_priv->has_hw_decrypt = false;
+#ifdef USE_LOCAL_CCMP_CRYPTO
+            sta_priv->need_sw_encrypt = true;
+            sta_priv->need_sw_decrypt = true;
+            sta_priv->use_mac80211_decrypt = false;
+            ret = 0;
+#else
+            dev_err(sc->dev, "STA %d MAC80211's %s cipher.\n", sta_priv->sta_idx, cipher_name);
+            sta_priv->need_sw_encrypt = false;
+            sta_priv->need_sw_decrypt = false;
+            sta_priv->use_mac80211_decrypt = true;
+            ret = -EOPNOTSUPP;
+#endif
+        }
+#ifdef USE_LOCAL_CRYPTO
+        if (sta_priv->need_sw_encrypt || sta_priv->need_sw_decrypt) {
+            struct ssv_crypto_ops *temp_crypt;
+            void *temp_crypt_priv = NULL;
+            INIT_WRITE_CRYPTO_DATA(crypto_data, &sta_priv->crypto_data);
+            START_WRITE_CRYPTO_DATA(crypto_data);
+            if (crypto_data->ops && crypto_data->priv) {
+                crypto_data->ops->deinit(crypto_data->priv);
+            }
+            temp_crypt = (cipher == SSV_CIPHER_CCMP)
+#ifdef USE_LOCAL_CCMP_CRYPTO
+                         ? get_crypto_ccmp_ops()
+#else
+                         ? NULL
+#endif
+#ifdef USE_LOCAL_TKIP_CRYPTO
+                         : get_crypto_tkip_ops();
+#else
+                         :
+                         NULL;
+#endif
+            if (temp_crypt)
+                temp_crypt_priv = temp_crypt->init(key->keyidx);
+            if (temp_crypt_priv) {
+                dev_err(sc->dev, "Use driver's %s cipher OK!\n", cipher_name);
+                temp_crypt->set_key(key->key, key->keylen, NULL, temp_crypt_priv);
+                crypto_data->priv = temp_crypt_priv;
+                crypto_data->ops = temp_crypt;
+            } else {
+                dev_err(sc->dev, "Failed to initialize driver's %s crypto! "
+                        "Use MAC80211's instead.\n", cipher_name);
+                sta_priv->need_sw_encrypt = false;
+                sta_priv->need_sw_decrypt = false;
+                sta_priv->use_mac80211_decrypt = true;
+                vif_priv->need_sw_encrypt = false;
+                vif_priv->need_sw_decrypt = false;
+                vif_priv->use_mac80211_decrypt = true;
+                ret = -EOPNOTSUPP;
+            }
+            END_WRITE_CRYPTO_DATA(crypto_data);
+        }
+#endif
+        if (sta_priv->has_hw_encrypt || sta_priv->has_hw_decrypt) {
+            SSV_SET_PAIRWISE_CIPHER_TYPE(sc->sh, cipher, sc->sta_info[sta_priv->sta_idx].hw_wsid);
+#if 0
+            ssv6200_hw_set_pair_type(sc->sh, SSV_CIPHER_NONE);
+            sta_priv->has_hw_encrypt = false;
+            sta_priv->has_hw_decrypt = false;
+            sta_priv->need_sw_encrypt = true;
+            sta_priv->need_sw_encrypt = true;
+#endif
+            SSV_WRITE_PAIRWISE_KEY_TO_HW(sc, key->keyidx, cipher,
+                                         key->key, key->keylen, key,
+                                         vif_priv, sta_priv);
+        }
+        if ( (vif_priv->has_hw_encrypt || vif_priv->has_hw_decrypt)
+             && (vif_priv->group_key_idx > 0)) {
+            SSV_SET_AES_TKIP_HW_CRYPTO_GROUP_KEY(sc, &sc->vif_info[vif_priv->vif_idx],
+                                                 &sc->sta_info[sta_priv->sta_idx], &vif_priv->group_key_idx);
+        }
+        return ret;
+    }
+    static int _set_group_key_tkip_ccmp (struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv,
+                                         struct ssv_sta_priv_data *sta_priv, enum SSV_CIPHER_E cipher,
+                                         struct ieee80211_key_conf *key) {
+        int ret = 0;
+        const char *cipher_name = (cipher == SSV_CIPHER_CCMP) ? "CCMP" : "TKIP";
+        vif_priv->group_cipher = cipher;
+        if (SSV_GROUP_WPA_USE_HW_CIPHER( sc, vif_priv, cipher)) {
+            dev_dbg(sc->dev, "VIF %d uses HW %s cipher for group.\n", vif_priv->vif_idx, cipher_name);
+#ifdef USE_MAC80211_DECRYPT_BROADCAST
+            vif_priv->has_hw_decrypt = false;
+            ret = -EOPNOTSUPP;
+#else
+            vif_priv->has_hw_decrypt = true;
+#endif
+            vif_priv->has_hw_encrypt = true;
+            vif_priv->need_sw_decrypt = false;
+            vif_priv->need_sw_encrypt = false;
+            vif_priv->use_mac80211_decrypt = false;
+        } else {
+            vif_priv->has_hw_decrypt = false;
+            vif_priv->has_hw_encrypt = false;
+#ifdef USE_LOCAL_CRYPTO
+            vif_priv->need_sw_encrypt = true;
+            vif_priv->need_sw_decrypt = true;
+            vif_priv->use_mac80211_decrypt = false;
+            ret = 0;
+#else
+            dev_err(sc->dev, "VIF %d uses MAC80211's %s cipher.\n", vif_priv->vif_idx, cipher_name);
+            vif_priv->need_sw_encrypt = false;
+            vif_priv->need_sw_decrypt = false;
+            vif_priv->use_mac80211_decrypt = true;
+            ret = -EOPNOTSUPP;
+#endif
+        }
+#ifdef USE_LOCAL_CRYPTO
+        if (vif_priv->need_sw_encrypt || vif_priv->need_sw_decrypt) {
+            struct ssv_crypto_ops *temp_crypt = NULL;
+            void *temp_crypt_priv = NULL;
+            INIT_WRITE_CRYPTO_DATA(crypto_data, &vif_priv->crypto_data);
+            START_WRITE_CRYPTO_DATA(crypto_data);
+            if (crypto_data->ops && crypto_data->priv)
+                crypto_data->ops->deinit(crypto_data->priv);
+            crypto_data->priv = NULL;
+            temp_crypt = (cipher == SSV_CIPHER_CCMP)
+#ifdef USE_LOCAL_CCMP_CRYPTO
+                         ? get_crypto_ccmp_ops()
+#else
+                         ? NULL
+#endif
+#ifdef USE_LOCAL_TKIP_CRYPTO
+                         : get_crypto_tkip_ops();
+#else
+                         :
+                         NULL;
+#endif
+            if (temp_crypt)
+                temp_crypt_priv = temp_crypt->init(key->keyidx);
+            if (temp_crypt_priv) {
+                dev_err(sc->dev, "VIF %d gets %s crypto OK! Use driver's crypto.\n",
+                        vif_priv->vif_idx, cipher_name);
+                temp_crypt->set_key(key->key, key->keylen, NULL, temp_crypt_priv);
+                crypto_data->priv = temp_crypt_priv;
+                crypto_data->ops = temp_crypt;
+            } else {
+                vif_priv->need_sw_encrypt = false;
+                vif_priv->need_sw_decrypt = false;
+                vif_priv->use_mac80211_decrypt = true;
+                dev_err(sc->dev, "VIF %d failed to initialize %s crypto!"
+                        " Use MAC80211's instead.\n", vif_priv->vif_idx, cipher_name);
+                ret = -EOPNOTSUPP;
+            }
+            END_WRITE_CRYPTO_DATA(crypto_data);
+        }
+#endif
+        if (vif_priv->has_hw_encrypt || vif_priv->has_hw_decrypt) {
+            int cipher_type;
+#ifdef USE_MAC80211_DECRYPT_BROADCAST
+            cipher_type = ME_NONE;
+#else
+            cipher_type = cipher;
+#endif
+            SSV_SET_GROUP_CIPHER_TYPE(sc->sh, vif_priv, cipher_type);
+            key->hw_key_idx = key->keyidx;
+            SSV_WRITE_GROUP_KEY_TO_HW(sc, key->keyidx, cipher,
+                                      key->key, key->keylen, key,
+                                      vif_priv, sta_priv);
+        }
+        vif_priv->is_security_valid = true;
+        SSV_CHK_DUAL_VIF_CHG_RX_FLOW( sc, vif_priv);
+        return ret;
+    }
+    static int _set_key_tkip_ccmp (struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv,
+                                   struct ssv_sta_priv_data *sta_priv, enum SSV_CIPHER_E cipher,
+                                   struct ieee80211_key_conf *key) {
+        if (key->keyidx == 0)
+            return _set_pairwise_key_tkip_ccmp(sc, vif_priv, sta_priv, cipher, key);
+        else
+            return _set_group_key_tkip_ccmp(sc, vif_priv, sta_priv, cipher, key);
+    }
+#ifdef USE_LOCAL_SMS4_CRYPTO
+    static int _set_pairwise_key_sms4 (struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv,
+                                       struct ssv_sta_priv_data *sta_priv, enum SSV_CIPHER_E cipher,
+                                       struct ieee80211_key_conf *key) {
+        int ret = 0;
+        INIT_WRITE_CRYPTO_DATA(crypto_data, NULL);
+        if (sta_priv == NULL) {
+            dev_err(sc->dev, "Setting pairwise SMS4 key to NULL STA.\n");
+            return -EOPNOTSUPP;
+        }
+        crypto_data = &sta_priv->crypto_data;
+        START_WRITE_CRYPTO_DATA(crypto_data);
+        sta_priv->has_hw_encrypt = false;
+        sta_priv->has_hw_decrypt = false;
+        sta_priv->need_sw_encrypt = true;
+        sta_priv->need_sw_decrypt = true;
+        sta_priv->use_mac80211_decrypt = false;
+        crypto_data->ops = get_crypto_wpi_ops();
+        if (crypto_data->ops)
+            crypto_data->priv = crypto_data->ops->init(key->keyidx);
+        if (crypto_data->priv) {
+            dev_err(sc->dev, "Use driver's SMS4 cipher OK!\n");
+            crypto_data->ops->set_key(key->key, key->keylen, NULL, crypto_data->priv);
+        } else {
+            dev_err(sc->dev, "Failed to initialize driver's SMS4 crypto!\n");
+            crypto_data->ops = NULL;
+            sta_priv->need_sw_encrypt = false;
+            sta_priv->need_sw_decrypt = false;
+            ret = -EOPNOTSUPP;
+        }
+        END_WRITE_CRYPTO_DATA(crypto_data);
+        return ret;
+    }
+    static int _set_group_key_sms4 (struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv,
+                                    struct ssv_sta_priv_data *sta_priv, enum SSV_CIPHER_E cipher,
+                                    struct ieee80211_key_conf *key) {
+        int ret = 0;
+        INIT_WRITE_CRYPTO_DATA(crypto_data, &vif_priv->crypto_data);
+        vif_priv->has_hw_encrypt = false;
+        vif_priv->has_hw_decrypt = false;
+        vif_priv->need_sw_encrypt = true;
+        vif_priv->need_sw_decrypt = true;
+        vif_priv->use_mac80211_decrypt = false;
+        START_WRITE_CRYPTO_DATA(crypto_data);
+        crypto_data->ops = get_crypto_wpi_ops();
+        if (crypto_data->ops)
+            crypto_data->priv = crypto_data->ops->init(key->keyidx);
+        if (crypto_data->priv) {
+            dev_err(sc->dev, "Use driver's SMS4 cipher OK!\n");
+            crypto_data->ops->set_key(key->key, key->keylen, NULL, crypto_data->priv);
+            vif_priv->is_security_valid = true;
+        } else {
+            dev_err(sc->dev, "Failed to initialize driver's SMS4 crypto!\n");
+            crypto_data->ops = NULL;
+            vif_priv->need_sw_encrypt = false;
+            vif_priv->need_sw_decrypt = false;
+            ret = -EOPNOTSUPP;
+            vif_priv->is_security_valid = false;
+        }
+        END_WRITE_CRYPTO_DATA(crypto_data);
+        return ret;
+    }
+    static int _set_key_sms4 (struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv,
+                              struct ssv_sta_priv_data *sta_priv, enum SSV_CIPHER_E cipher,
+                              struct ieee80211_key_conf *key) {
+        if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE)
+            return _set_pairwise_key_sms4(sc, vif_priv, sta_priv, cipher, key);
+        else
+            return _set_group_key_sms4(sc, vif_priv, sta_priv, cipher, key);
+    }
+#endif
+    static int ssv6200_set_key(struct ieee80211_hw *hw,
+                               enum set_key_cmd cmd,
+                               struct ieee80211_vif *vif,
+                               struct ieee80211_sta *sta,
+                               struct ieee80211_key_conf *key) {
+        struct ssv_softc *sc = hw->priv;
+        int ret = 0;
+        enum SSV_CIPHER_E cipher = SSV_CIPHER_NONE;
+        int sta_idx = (-1);
+        struct ssv_sta_info *sta_info = NULL;
+        struct ssv_sta_priv_data *sta_priv = NULL;
+        struct ssv_vif_priv_data *vif_priv = (struct ssv_vif_priv_data *)vif->drv_priv;
+        HCI_WRITE_HW_CONFIG_ON(sc->sh);
+#if 0
+        int another_vif_idx = ((vif_priv->vif_idx + 1) % 2);
+        struct ssv_vif_priv_data *another_vif_priv = NULL;
+        u32 another_vif_pair_cipher = 0;
+        u32 another_vif_group_cipher = 0;
+        if (sc->vif_info[another_vif_idx].vif) {
+            another_vif_priv = sc->vif_info[another_vif_idx].vif_priv;
+            another_vif_pair_cipher = another_vif_priv->pair_cipher;
+            another_vif_group_cipher = another_vif_priv->group_cipher;
+        }
+#endif
+        mutex_lock(&sc->mutex);
+        if (sta) {
+            sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+            sta_idx = sta_priv->sta_idx;
+            sta_info = &sc->sta_info[sta_idx];
+            if ((sta_info->s_flags & STA_FLAG_VALID) == 0) {
+                dev_warn(sc->dev, "%s(): sta_info is gone.\n", __func__);
+                ret = -ENODATA;
+                goto out;
+            }
+        }
+        BUG_ON((cmd!=SET_KEY) && (cmd!=DISABLE_KEY));
+        if (!(sc->sh->cfg.hw_caps & SSV6200_HW_CAP_SECURITY)) {
+            dev_warn(sc->dev, "HW does not support security.\n");
+            ret = -EOPNOTSUPP;
+            goto out;
+        }
+#ifndef USE_LOCAL_CRYPTO
+        if (sta_info && (sta_info->hw_wsid == (-1))) {
+            dev_warn(sc->dev, "Add STA without HW resource. Use MAC80211's solution.\n");
+            ret = -EOPNOTSUPP;
+            goto out;
+        }
+#endif
+        cipher = _prepare_key(key, sc);
+        dev_dbg(sc->dev,"Set key VIF %d VIF type %d STA %d algorithm = %d, key->keyidx = %d, cmd = %d\n",
+                vif_priv->vif_idx, vif->type, sta_idx, cipher, key->keyidx, cmd);
+        if (cipher == SSV_CIPHER_INVALID) {
+            dev_warn(sc->dev, "Unsupported cipher type.\n");
+            ret = -EOPNOTSUPP;
+            goto out;
+        }
+        switch (cmd) {
+        case SET_KEY: {
+#if 0
+            int i;
+            dev_dbg(sc->dev, "================================SET KEY=======================================\n");
+            if (sta_info == NULL) {
+                dev_dbg(sc->dev, "NULL STA cmd[%d] alg[%d] keyidx[%d] ", cmd, algorithm, key->keyidx);
+            } else {
+                dev_dbg(sc->dev, "STA WSID[%d] cmd[%d] alg[%d] keyidx[%d] ", sta_info->hw_wsid, cmd, algorithm, key->keyidx);
+            }
+            dev_dbg(sc->dev, "SET_KEY index[%d] flags[0x%x] algorithm[%d] key->keylen[%d]\n",
+                   key->keyidx, key->flags, algorithm, key->keylen);
+            for(i = 0; i < key->keylen; i++) {
+                dev_dbg(sc->dev, "[%02x]", key->key[i]);
+            }
+            dev_dbg(sc->dev, "\n");
+            dev_dbg(sc->dev, "===============================================================================\n");
+#endif
+            switch (cipher) {
+            case SSV_CIPHER_WEP40:
+            case SSV_CIPHER_WEP104:
+                ret = _set_key_wep(sc, vif_priv, sta_priv, cipher, key);
+                key->hw_key_idx = key->keyidx;
+                break;
+            case SSV_CIPHER_TKIP:
+            case SSV_CIPHER_CCMP:
+                ret = _set_key_tkip_ccmp(sc, vif_priv, sta_priv, cipher, key);
+                break;
+#ifdef CONFIG_SSV_WAPI
+            case SSV_CIPHER_SMS4:
+                ret = _set_key_sms4(sc, vif_priv, sta_priv, cipher, key);
+                break;
+#endif
+            default:
+                break;
+            }
+            if (sta) {
+                struct ssv_sta_priv_data *first_sta_priv =
+                    list_first_entry(&vif_priv->sta_list, struct ssv_sta_priv_data, list);
+                if (first_sta_priv->sta_idx == sta_priv->sta_idx) {
+                    vif_priv->pair_cipher = cipher;
+                }
+            }
+#ifdef FW_WSID_WATCH_LIST
+            SSV_SET_FW_HWWSID_SEC_TYPE(sc, sta, sta_info, vif_priv);
+#endif
+        }
+        break;
+        case DISABLE_KEY: {
+            int another_vif_idx = ((vif_priv->vif_idx + 1) % 2);
+            struct ssv_vif_priv_data *another_vif_priv =
+                (struct ssv_vif_priv_data *)sc->vif_info[another_vif_idx].vif_priv;
+#if 0
+            dev_dbg(sc->dev, "================================DEL KEY=======================================\n");
+            if(sta_info == NULL) {
+                dev_dbg(sc->dev, "NULL STA cmd[%d] alg[%d] keyidx[%d] ", cmd, cipher, key->keyidx);
+            } else {
+                dev_dbg(sc->dev, "STA WSID[%d] cmd[%d] alg[%d] keyidx[%d] ", sta_info->hw_wsid, cmd, cipher, key->keyidx);
+            }
+            dev_dbg(sc->dev, "DISABLE_KEY index[%d]\n",key->keyidx);
+            dev_dbg(sc->dev, "==============================================================================\n");
+#endif
+#if 0
+            if(key->keyidx == 0) {
+                sta_info->ampdu_ccmp_encrypt = false;
+            }
+#endif
+            if (another_vif_priv != NULL) {
+                SSV_RESTORE_RX_FLOW(sc, vif_priv, sta);
+            }
+            if ( sta == NULL) {
+                vif_priv->group_cipher = ME_NONE;
+                if ((another_vif_priv == NULL)
+                    || ((another_vif_priv != NULL) && (!SSV6XXX_USE_HW_DECRYPT(another_vif_priv)))) {
+                    SSV_SET_GROUP_CIPHER_TYPE(sc->sh, vif_priv, ME_NONE);
+                }
+            } else {
+                struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
+                if ((vif_info->if_type != NL80211_IFTYPE_AP) && (another_vif_priv == NULL)) {
+                    struct ssv_sta_priv_data *first_sta_priv =
+                        list_first_entry(&vif_priv->sta_list, struct ssv_sta_priv_data, list);
+                    if (sta_priv == first_sta_priv) {
+                        SSV_SET_PAIRWISE_CIPHER_TYPE(sc->sh, ME_NONE, sta_info->hw_wsid);
+                    }
+                }
+            }
+            if ((cipher == ME_WEP40) || (cipher == ME_WEP104)) {
+                vif_priv->wep_idx = -1;
+                vif_priv->wep_cipher = -1;
+            }
+            if ((cipher == ME_TKIP) || (cipher == ME_CCMP)) {
+                dev_dbg(sc->dev, KERN_ERR "Clear key %d VIF %d, STA %d\n",
+                       key->keyidx, (vif != NULL), (sta != NULL));
+                hw_crypto_key_clear(hw, key->keyidx, key, vif_priv, sta_priv);
+            }
+            {
+                if ((key->keyidx == 0) && (sta_priv != NULL)) {
+                    sta_priv->has_hw_decrypt = false;
+                    sta_priv->has_hw_encrypt = false;
+                    sta_priv->need_sw_encrypt = false;
+                    sta_priv->use_mac80211_decrypt = false;
+#ifdef USE_LOCAL_CRYPTO
+                    if (SSV_NEED_SW_CIPHER(sc->sh)) {
+                        INIT_WRITE_CRYPTO_DATA(crypto_data, &sta_priv->crypto_data);
+                        if (crypto_data->ops && crypto_data->priv) {
+#ifdef MULTI_THREAD_ENCRYPT
+                            unsigned long flags;
+                            u32 sta_addr0_3 = *(u32 *)&sta->addr[0];
+                            u32 sta_addr4_5 = (u32)*(u16 *)&sta->addr[4];
+                            u32 removed_skb_num;
+#endif
+                            START_WRITE_CRYPTO_DATA(crypto_data);
+                            crypto_data->ops->deinit(crypto_data->priv);
+                            crypto_data->priv = NULL;
+                            crypto_data->ops = NULL;
+                            END_WRITE_CRYPTO_DATA(crypto_data);
+#ifdef MULTI_THREAD_ENCRYPT
+                            spin_lock_irqsave(&sc->crypt_st_lock, flags);
+                            removed_skb_num = _remove_sta_skb_from_q(sc, &sc->preprocess_q,
+                                              sta_addr0_3, sta_addr4_5);
+                            spin_unlock_irqrestore(&sc->crypt_st_lock, flags);
+                            dev_err(sc->dev, "Clean up %d skb for STA %pM.\n", removed_skb_num, sta->addr);
+#endif
+                        }
+                    }
+#endif
+                }
+#ifdef USE_LOCAL_CRYPTO
+                else if (SSV_NEED_SW_CIPHER(sc->sh)) {
+                    INIT_WRITE_CRYPTO_DATA(crypto_data, &vif_priv->crypto_data);
+                    START_WRITE_CRYPTO_DATA(crypto_data);
+                    if (crypto_data->ops && crypto_data->priv)
+                        crypto_data->ops->deinit(crypto_data->priv);
+                    crypto_data->priv = NULL;
+                    crypto_data->ops = NULL;
+                    END_WRITE_CRYPTO_DATA(crypto_data);
+                }
+#endif
+                if ((vif_priv->is_security_valid) && (key->keyidx != 0)) {
+#if 0
+                    vif_priv->has_hw_decrypt = false;
+                    vif_priv->has_hw_encrypt = false;
+                    vif_priv->need_sw_encrypt = false;
+#endif
+                    vif_priv->is_security_valid = false;
+                }
+            }
+            ret = 0;
+        }
+        break;
+        default:
+            ret = -EINVAL;
+        }
+        if(sta_priv != NULL) {
+            dev_dbg(sc->dev, "sta: hw_en:%d, sw_en:%d, hw_de:%d, sw_de:%d,\n",
+                   (sta_priv->has_hw_encrypt==true),(sta_priv->need_sw_encrypt==true),
+                   (sta_priv->has_hw_decrypt==true),(sta_priv->need_sw_decrypt==true));
+        }
+        if(vif_priv) {
+            dev_dbg(sc->dev, "vif: hw_en:%d, sw_en:%d, hw_de:%d, sw_de:%d, valid:%d\n",
+                   (vif_priv->has_hw_encrypt==true),(vif_priv->need_sw_encrypt==true),
+                   (vif_priv->has_hw_decrypt==true),(vif_priv->need_sw_decrypt==true), (vif_priv->is_security_valid==true));
+        }
+#ifdef CONFIG_SSV_SW_ENCRYPT_HW_DECRYPT
+        ret = -EOPNOTSUPP;
+#endif
+out:
+        mutex_unlock(&sc->mutex);
+        dev_dbg(sc->dev, KERN_ERR "SET KEY %d\n", ret);
+        HCI_WRITE_HW_CONFIG_OFF(sc->sh);
+        return ret;
+    }
+    u32 _process_tx_done (struct ssv_softc *sc) {
+        struct ieee80211_tx_info *tx_info;
+        struct sk_buff *skb;
+        while ((skb = skb_dequeue(&sc->tx_done_q))) {
+            if (SSV_GET_TX_DESC_CTYPE(sc->sh, skb) > M2_TXREQ) {
+                ssv_skb_free(sc, skb);
+                dev_dbg(sc->dev, KERN_INFO "free cmd skb!\n");
+                continue;
+            }
+            tx_info = IEEE80211_SKB_CB(skb);
+            if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
+                ssv6200_ampdu_release_skb(skb, sc->hw);
+                continue;
+            }
+            skb_pull(skb, SSV_GET_TX_DESC_SIZE(sc->sh));
+            ieee80211_tx_info_clear_status(tx_info);
+            tx_info->flags |= IEEE80211_TX_STAT_ACK;
+            tx_info->status.ack_signal = 100;
+#ifdef REPORT_TX_DONE_IN_IRQ
+            ieee80211_tx_status_irqsafe(sc->hw, skb);
+#else
+            ieee80211_tx_status(sc->hw, skb);
+            if (skb_queue_len(&sc->rx_skb_q))
+                break;
+#endif
+        }
+        return skb_queue_len(&sc->tx_done_q);
+    }
+#ifdef REPORT_TX_DONE_IN_IRQ
+    void ssv6xxx_post_tx_cb(struct sk_buff_head *skb_head, void *args) {
+        struct ssv_softc *sc=(struct ssv_softc *)args;
+        _process_tx_done*(sc);
+    }
+#else
+    void ssv6xxx_post_tx_cb(struct sk_buff_head *skb_head, void *args) {
+        struct ssv_softc *sc=(struct ssv_softc *)args;
+        struct sk_buff *skb;
+        while ((skb=skb_dequeue(skb_head))) {
+            if (SSV_GET_TX_DESC_CTYPE(sc->sh, skb) > M2_TXREQ) {
+                ssv_skb_free(sc, skb);
+                dev_dbg(sc->dev, KERN_INFO "free cmd skb!\n");
+                continue;
+            }
+            if (SSV_NULLFUN_FRAME_FILTER(sc->sh, skb)) {
+                ssv_skb_free(sc, skb);
+                continue;
+            }
+            skb_queue_tail(&sc->tx_done_q, skb);
+        }
+        wake_up_interruptible(&sc->rx_wait_q);
+    }
+#endif
+    void ssv6xxx_pre_tx_cb(struct sk_buff *skb, void *args) {
+        struct ssv_softc *sc=(struct ssv_softc *)args;
+        struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
+        if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
+            ssv6xxx_ampdu_sent(sc->hw, skb);
+    }
+    void ssv6xxx_tx_rate_update(struct sk_buff *skb, void *args) {
+        struct ssv_softc *sc = args;
+#ifdef SSV_SUPPORT_HAL
+        HAL_TX_RATE_UPDATE(sc, skb);
+#else
+#ifdef RATE_CONTROL_REALTIME_UPDATE
+        struct ieee80211_hdr *hdr;
+        struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
+        struct ssv6200_tx_desc *tx_desc;
+        struct ssv_rate_info ssv_rate;
+        u32 nav=0;
+        int ret = 0;
+        tx_desc = (struct ssv6200_tx_desc *)skb->data;
+        if(tx_desc->c_type > M2_TXREQ)
+            return;
+        if (!(info->flags & IEEE80211_TX_CTL_AMPDU)) {
+            hdr = (struct ieee80211_hdr *)(skb->data + SSV6XXX_TX_DESC_LEN);
+            if ( ( ieee80211_is_data_qos(hdr->frame_control)
+                   || ieee80211_is_data(hdr->frame_control))
+                 && (tx_desc->wsid < SSV_RC_MAX_HARDWARE_SUPPORT)) {
+                ret = ssv6xxx_rc_hw_rate_update_check(skb, sc, tx_desc->do_rts_cts);
+                if (ret & RC_FIRMWARE_REPORT_FLAG) {
+                    {
+                        tx_desc->RSVD_0 = SSV6XXX_RC_REPORT;
+                        tx_desc->tx_report = 1;
+                    }
+                    ret &= 0xf;
+                }
+                if(ret) {
+                    ssv6xxx_rc_hw_rate_idx(sc, info, &ssv_rate);
+                    tx_desc->crate_idx = ssv_rate.crate_hw_idx;
+                    tx_desc->drate_idx = ssv_rate.drate_hw_idx;
+                    nav = ssv6xxx_set_frame_duration(info, &ssv_rate, skb->len+FCS_LEN, tx_desc, NULL, NULL);
+                    if (tx_desc->tx_burst == 0) {
+                        if (tx_desc->ack_policy != 0x01)
+                            hdr->duration_id = nav;
+                    }
+                }
+            }
+        }
+#endif
+#endif
+    }
+#ifndef SSV_SUPPORT_HAL
+    void ssv6xxx_update_txinfo (struct ssv_softc *sc, struct sk_buff *skb) {
+        struct ieee80211_hdr *hdr;
+        struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
+        struct ieee80211_sta *sta;
+        struct ssv_sta_info *sta_info = NULL;
+        struct ssv_sta_priv_data *ssv_sta_priv = NULL;
+        struct ssv_vif_priv_data *vif_priv = (struct ssv_vif_priv_data *)info->control.vif->drv_priv;
+        struct ssv6200_tx_desc *tx_desc = (struct ssv6200_tx_desc *)skb->data;
+        struct ieee80211_tx_rate *tx_drate;
+        struct ssv_rate_info ssv_rate;
+        int ac, hw_txqid;
+        u32 nav=0;
+        if (info->flags & IEEE80211_TX_CTL_AMPDU) {
+            struct ampdu_hdr_st *ampdu_hdr = (struct ampdu_hdr_st *)skb->head;
+            sta = ampdu_hdr->ampdu_tid->sta;
+            hdr = (struct ieee80211_hdr *)(skb->data + TXPB_OFFSET + AMPDU_DELIMITER_LEN);
+        } else {
+            struct SKB_info_st *skb_info = (struct SKB_info_st *)skb->head;
+            sta = skb_info->sta;
+            hdr = (struct ieee80211_hdr *)(skb->data + TXPB_OFFSET);
+        }
+        if (sta) {
+            ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+            down_read(&sc->sta_info_sem);
+            sta_info = ssv_sta_priv->sta_info;
+        }
+        if ((!sc->bq4_dtim) &&
+            (ieee80211_is_mgmt(hdr->frame_control) ||
+             ieee80211_is_nullfunc(hdr->frame_control) ||
+             ieee80211_is_qos_nullfunc(hdr->frame_control))) {
+            ac = 4;
+            hw_txqid = 4;
+        } else if((sc->bq4_dtim) &&
+                  info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
+            hw_txqid = 4;
+            ac = 4;
+        } else {
+            ac = skb_get_queue_mapping(skb);
+            hw_txqid = sc->tx.hw_txqid[ac];
+        }
+        tx_drate = &info->control.rates[0];
+        ssv6xxx_rc_hw_rate_idx(sc, info, &ssv_rate);
+        tx_desc->len = skb->len;
+        tx_desc->c_type = M2_TXREQ;
+        tx_desc->f80211 = 1;
+        tx_desc->qos = (ieee80211_is_data_qos(hdr->frame_control))? 1: 0;
+        if (tx_drate->flags & IEEE80211_TX_RC_MCS) {
+            if (ieee80211_is_mgmt(hdr->frame_control) &&
+                ieee80211_has_order(hdr->frame_control))
+                tx_desc->ht = 1;
+        }
+        tx_desc->use_4addr = (ieee80211_has_a4(hdr->frame_control))? 1: 0;
+        tx_desc->more_data = (ieee80211_has_morefrags(hdr->frame_control))? 1: 0;
+        tx_desc->stype_b5b4 = (cpu_to_le16(hdr->frame_control)>>4)&0x3;
+        tx_desc->frag = (tx_desc->more_data||(hdr->seq_ctrl&0xf))? 1: 0;
+        tx_desc->unicast = (is_multicast_ether_addr(hdr->addr1)) ? 0: 1;
+        tx_desc->tx_burst = (tx_desc->frag)? 1: 0;
+        tx_desc->wsid = (!sta_info || (sta_info->hw_wsid < 0)) ? 0x0F : sta_info->hw_wsid;
+        tx_desc->txq_idx = hw_txqid;
+        tx_desc->hdr_offset = TXPB_OFFSET;
+        tx_desc->hdr_len = ssv6xxx_frame_hdrlen(hdr, tx_desc->ht);
+        tx_desc->payload_offset = tx_desc->hdr_offset + tx_desc->hdr_len;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
+        if(info->control.use_rts)
+            tx_desc->do_rts_cts = IEEE80211_TX_RC_USE_RTS_CTS;
+        else if(info->control.use_cts_prot)
+            tx_desc->do_rts_cts = IEEE80211_TX_RC_USE_CTS_PROTECT;
+#else
+        tx_desc->do_rts_cts = RTS_CTS_PROTECT(tx_drate->flags);
+#endif
+#if 1
+        if(tx_desc->do_rts_cts == IEEE80211_TX_RC_USE_CTS_PROTECT)
+            tx_desc->do_rts_cts = IEEE80211_TX_RC_USE_RTS_CTS;
+#endif
+        if(tx_desc->do_rts_cts == IEEE80211_TX_RC_USE_CTS_PROTECT) {
+            tx_desc->crate_idx = 0;
+        } else
+            tx_desc->crate_idx = ssv_rate.crate_hw_idx;
+        tx_desc->drate_idx = ssv_rate.drate_hw_idx;
+        if (tx_desc->unicast == 0)
+            tx_desc->ack_policy = 1;
+        else if (tx_desc->qos == 1)
+            tx_desc->ack_policy = (*ieee80211_get_qos_ctl(hdr)&0x60)>>5;
+        else if(ieee80211_is_ctl(hdr->frame_control))
+            tx_desc->ack_policy = 1;
+        tx_desc->security = 0;
+        tx_desc->fCmdIdx = 0;
+        tx_desc->fCmd = (hw_txqid+M_ENG_TX_EDCA0);
+        if (info->flags & IEEE80211_TX_CTL_AMPDU) {
+#ifdef AMPDU_HAS_LEADING_FRAME
+            tx_desc->fCmd = (tx_desc->fCmd << 4) | M_ENG_CPU;
+#else
+            tx_desc->RSVD_1 = 1;
+#endif
+            tx_desc->aggregation = 1;
+            tx_desc->ack_policy = 0x01;
+            if ( (tx_desc->do_rts_cts == 0)
+                 && ( (sc->hw->wiphy->rts_threshold == (-1))
+                      || ((skb->len - sc->sh->tx_desc_len) > sc->hw->wiphy->rts_threshold))) {
+                tx_drate->flags |= IEEE80211_TX_RC_USE_RTS_CTS;
+                tx_desc->do_rts_cts = 1;
+            }
+        }
+        if ( ieee80211_has_protected(hdr->frame_control)
+             && ( ieee80211_is_data_qos(hdr->frame_control)
+                  || ieee80211_is_data(hdr->frame_control))) {
+            if ( (tx_desc->unicast && ssv_sta_priv && ssv_sta_priv->has_hw_encrypt)
+                 || (!tx_desc->unicast && vif_priv && vif_priv->has_hw_encrypt)) {
+                if (!tx_desc->unicast && !list_empty(&vif_priv->sta_list)) {
+                    struct ssv_sta_priv_data *one_sta_priv;
+                    int hw_wsid;
+                    one_sta_priv = list_first_entry(&vif_priv->sta_list, struct ssv_sta_priv_data, list);
+                    hw_wsid = one_sta_priv->sta_info->hw_wsid;
+                    if (hw_wsid != (-1)) {
+                        tx_desc->wsid = hw_wsid;
+                    }
+#if 0
+                    dev_dbg(sc->dev, KERN_ERR "HW ENC %d %02X:%02X:%02X:%02X:%02X:%02X\n",
+                           tx_desc->wsid,
+                           hdr->addr1[0], hdr->addr1[1], hdr->addr1[2],
+                           hdr->addr1[3], hdr->addr1[4], hdr->addr1[5]);
+                    _ssv6xxx_hexdump("M ", (const u8 *)skb->data, (skb->len > 128) ? 128 : skb->len);
+                    tx_desc->fCmd = (tx_desc->fCmd << 4) | M_ENG_CPU;
+#endif
+                }
+                tx_desc->fCmd = (tx_desc->fCmd << 4) | M_ENG_ENCRYPT;
+#if 0
+                if (dump_count++ < 10) {
+                    dev_dbg(sc->dev, KERN_ERR "HW ENC %d %02X:%02X:%02X:%02X:%02X:%02X\n",
+                           tx_desc->wsid,
+                           hdr->addr1[0], hdr->addr1[1], hdr->addr1[2],
+                           hdr->addr1[3], hdr->addr1[4], hdr->addr1[5]);
+                    tx_desc->tx_report = 1;
+                    _ssv6xxx_hexdump("M ", (const u8 *)skb->data, (skb->len > 128) ? 128 : skb->len);
+                }
+#endif
+            } else if (ssv_sta_priv->need_sw_encrypt) {
+            } else {
+            }
+        } else {
+        }
+        tx_desc->fCmd = (tx_desc->fCmd << 4) | M_ENG_HWHCI;
+#if 0
+        if ( ieee80211_is_data_qos(hdr->frame_control)
+             || ieee80211_is_data(hdr->frame_control))
+#endif
+#if 0
+            if (ieee80211_is_probe_resp(hdr->frame_control)) {
+                {
+                    dev_dbg(sc->dev, KERN_ERR "Probe Resp %d %02X:%02X:%02X:%02X:%02X:%02X\n",
+                           tx_desc->wsid,
+                           hdr->addr1[0], hdr->addr1[1], hdr->addr1[2],
+                           hdr->addr1[3], hdr->addr1[4], hdr->addr1[5]);
+                    _ssv6xxx_hexdump("M ", (const u8 *)skb->data, (skb->len > 128) ? 128 : skb->len);
+                }
+            }
+#endif
+#if 0
+        if ( (sc->sh->cfg.hw_caps & SSV6200_HW_CAP_SECURITY)
+             && (sc->algorithm != ME_NONE)) {
+            if ( (tx_desc->unicast == 0)
+                 || (sc->algorithm == ME_WEP104 || sc->algorithm == ME_WEP40)) {
+                tx_desc->wsid = 0;
+            }
+        }
+#endif
+#if 0
+        if (tx_desc->aggregation) {
+            tx_desc->do_rts_cts = 0;
+            tx_desc->fCmd = M_ENG_HWHCI|((hw_txqid+M_ENG_TX_EDCA0)<<4);
+            tx_desc->ack_policy = 0x01;
+        }
+#endif
+        if (tx_desc->aggregation == 1) {
+            struct ampdu_hdr_st *ampdu_hdr = (struct ampdu_hdr_st *)skb->head;
+            memcpy(&tx_desc->rc_params[0], ampdu_hdr->rates, sizeof(tx_desc->rc_params));
+            nav = ssv6xxx_set_frame_duration(info, &ssv_rate, (skb->len+FCS_LEN), tx_desc, &tx_desc->rc_params[0], sc);
+#ifdef FW_RC_RETRY_DEBUG
+            {
+                dev_dbg(sc->dev, "[FW_RC]:param[0]: drate =%d, count =%d, crate=%d, dl_length =%d, frame_consume_time =%d, rts_cts_nav=%d\n",
+                       tx_desc->rc_params[0].drate,tx_desc->rc_params[0].count,tx_desc->rc_params[0].crate,
+                       tx_desc->rc_params[0].dl_length, tx_desc->rc_params[0].frame_consume_time, tx_desc->rc_params[0].rts_cts_nav);
+                dev_dbg(sc->dev, "[FW_RC]:param[1]: drate =%d, count =%d, crate=%d, dl_length =%d, frame_consume_time =%d, rts_cts_nav=%d\n",
+                       tx_desc->rc_params[1].drate,tx_desc->rc_params[1].count,tx_desc->rc_params[1].crate,
+                       tx_desc->rc_params[1].dl_length, tx_desc->rc_params[1].frame_consume_time, tx_desc->rc_params[1].rts_cts_nav);
+                dev_dbg(sc->dev, "[FW_RC]:param[2]: drate =%d, count =%d, crate=%d, dl_length =%d, frame_consume_time =%d, rts_cts_nav=%d\n",
+                       tx_desc->rc_params[2].drate,tx_desc->rc_params[2].count,tx_desc->rc_params[2].crate,
+                       tx_desc->rc_params[2].dl_length, tx_desc->rc_params[2].frame_consume_time, tx_desc->rc_params[2].rts_cts_nav);
+            }
+#endif
+        } else {
+            nav = ssv6xxx_set_frame_duration(info, &ssv_rate, (skb->len+FCS_LEN), tx_desc, NULL, NULL);
+        }
+        if ( (tx_desc->aggregation==0)) {
+            if (tx_desc->tx_burst == 0) {
+                if (tx_desc->ack_policy != 0x01)
+                    hdr->duration_id = nav;
+            } else {
+            }
+        }
+        if (sta) {
+            up_read(&sc->sta_info_sem);
+        }
+    }
+    void ssv6xxx_add_txinfo (struct ssv_softc *sc, struct sk_buff *skb) {
+        struct ssv6200_tx_desc *tx_desc;
+        skb_push(skb, sc->sh->tx_desc_len);
+        tx_desc = (struct ssv6200_tx_desc *)skb->data;
+        memset((void *)tx_desc, 0, sc->sh->tx_desc_len);
+        ssv6xxx_update_txinfo(sc, skb);
+    }
+#endif
+#if (!defined(SSV_SUPPORT_HAL) || defined(SSV_SUPPORT_SSV6051))
+    int ssv6xxx_get_real_index(struct ssv_softc *sc, struct sk_buff *skb) {
+        struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
+        struct ieee80211_tx_rate *tx_drate;
+        struct ssv_rate_info ssv_rate;
+        tx_drate = &info->control.rates[0];
+        ssv6xxx_rc_hw_rate_idx(sc, info, &ssv_rate);
+        return ssv_rate.drate_hw_idx;
+    }
+#endif
+    static void ssv6xxx_update_wep_hw_security_setting(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv, struct ieee80211_key_conf *hw_key) {
+        u32 cipher;
+        u8 keyidx;
+        int wsid = -1;
+        struct ssv_sta_priv_data *sta_priv_iter;
+        if (hw_key) {
+            cipher = hw_key->cipher;
+            keyidx = hw_key->hw_key_idx;
+            if ((cipher == WLAN_CIPHER_SUITE_WEP40) || (cipher == WLAN_CIPHER_SUITE_WEP104)) {
+                if (vif_priv->wep_cipher != cipher) {
+                    dev_dbg(sc->dev, "Write WEP wlan cipher: 0x%x to HW\n", cipher);
+                    down_read(&sc->sta_info_sem);
+                    list_for_each_entry(sta_priv_iter, &vif_priv->sta_list, list) {
+                        if ((sc->sta_info[sta_priv_iter->sta_idx].s_flags & STA_FLAG_VALID) == 1) {
+                            wsid = sc->sta_info[sta_priv_iter->sta_idx].hw_wsid;
+                            if (wsid >= 0) {
+                                switch (cipher) {
+                                case WLAN_CIPHER_SUITE_WEP40:
+                                    HCI_WRITE_HW_CONFIG_ON(sc->sh);
+                                    vif_priv->wep_cipher = WLAN_CIPHER_SUITE_WEP40;
+                                    SSV_SET_PAIRWISE_CIPHER_TYPE(sc->sh, SSV_CIPHER_WEP40, wsid);
+                                    SSV_SET_GROUP_CIPHER_TYPE(sc->sh, vif_priv, SSV_CIPHER_WEP40);
+                                    HCI_WRITE_HW_CONFIG_OFF(sc->sh);
+                                    break;
+                                case WLAN_CIPHER_SUITE_WEP104:
+                                    HCI_WRITE_HW_CONFIG_ON(sc->sh);
+                                    vif_priv->wep_cipher = WLAN_CIPHER_SUITE_WEP104;
+                                    SSV_SET_PAIRWISE_CIPHER_TYPE(sc->sh, SSV_CIPHER_WEP104, wsid);
+                                    SSV_SET_GROUP_CIPHER_TYPE(sc->sh, vif_priv, SSV_CIPHER_WEP104);
+                                    HCI_WRITE_HW_CONFIG_OFF(sc->sh);
+                                    break;
+                                }
+                            }
+                        }
+                    }
+                    up_read(&sc->sta_info_sem);
+                }
+                if (vif_priv->wep_idx != keyidx) {
+                    dev_dbg(sc->dev, "Update WEP default key index for HW encryption\n");
+                    dev_dbg(sc->dev, "Write WEP key index: %d to HW\n", keyidx);
+                    vif_priv->wep_idx = keyidx;
+                    down_read(&sc->sta_info_sem);
+                    list_for_each_entry(sta_priv_iter, &vif_priv->sta_list, list) {
+                        if ((sc->sta_info[sta_priv_iter->sta_idx].s_flags & STA_FLAG_VALID) == 1) {
+                            HCI_WRITE_HW_CONFIG_ON(sc->sh);
+                            wsid = sc->sta_info[sta_priv_iter->sta_idx].hw_wsid;
+                            if (wsid >= 0)
+                                SSV_WRITE_PAIRWISE_KEYIDX_TO_HW(sc->sh, vif_priv->wep_idx, wsid);
+                            SSV_WRITE_GROUP_KEYIDX_TO_HW(sc->sh, vif_priv, vif_priv->wep_idx);
+                            HCI_WRITE_HW_CONFIG_OFF(sc->sh);
+                        }
+                    }
+                    up_read(&sc->sta_info_sem);
+                }
+            }
+        }
+    }
+    static void _ssv6xxx_tx (struct ieee80211_hw *hw, struct sk_buff *skb) {
+        struct ssv_softc *sc = hw->priv;
+        struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
+        struct ieee80211_vif *vif = info->control.vif;
+        struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
+        struct ssv_vif_priv_data *vif_priv = (struct ssv_vif_priv_data *)info->control.vif->drv_priv;
+#ifdef USE_LOCAL_CRYPTO
+        struct SKB_info_st *skb_info = (struct SKB_info_st *)skb->head;
+        struct ieee80211_sta *sta = skb_info->sta;
+        struct ssv_sta_priv_data *ssv_sta_priv = sta
+                ? (struct ssv_sta_priv_data *)sta->drv_priv
+                : NULL;
+#endif
+        u32 txq_idx;
+        int ret;
+        unsigned long flags;
+        bool send_hci=false;
+        if (vif_priv->has_hw_encrypt == true)
+            ssv6xxx_update_wep_hw_security_setting(sc, vif_priv, info->control.hw_key);
+#ifdef CONFIG_SSV_SUPPORT_ANDROID
+        if(sc->ps_status == PWRSV_PREPARE) {
+            if(ieee80211_is_data(hdr->frame_control))
+                ssv_wake_timeout(sc, 1);
+        }
+#endif
+        do {
+            if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
+                if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
+                    sc->tx.seq_no += 0x10;
+                hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
+                hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
+            }
+            if (sc->dbg_tx_frame) {
+                dev_dbg(sc->dev, "================================================\n");
+                _ssv6xxx_hexdump("TX frame", (const u8 *)skb->data, skb->len);
+            }
+#if 0
+            if ( (skb->protocol == cpu_to_be16(ETH_P_PAE))
+                 && ieee80211_is_data_qos(hdr->frame_control)) {
+                dev_dbg(sc->dev, KERN_ERR "EAPOL frame is %d\n", skb_get_queue_mapping(skb));
+            }
+#endif
+#ifdef USE_LOCAL_CRYPTO
+            if (
+#ifdef MULTI_THREAD_ENCRYPT
+                (skb_info->crypt_st == PKT_CRYPT_ST_NOT_SUPPORT) &&
+#endif
+                ieee80211_has_protected(hdr->frame_control)
+                && ( ieee80211_is_data_qos(hdr->frame_control)
+                     || ieee80211_is_data(hdr->frame_control))) {
+                bool unicast = !is_broadcast_ether_addr(hdr->addr1);
+                if ( ( unicast
+                       && (ssv_sta_priv != NULL)
+                       && ssv_sta_priv->need_sw_encrypt)
+                     || ( !unicast
+                          && vif_priv->is_security_valid
+                          && vif_priv->need_sw_encrypt)) {
+                    if(ssv6xxx_skb_encrypt(skb, sc) == (-1)) {
+                        ssv_skb_free(sc, skb);
+                        break;
+                    }
+                }
+            } else {
+            }
+#endif
+            if (info->flags & IEEE80211_TX_CTL_AMPDU) {
+                if (SSV_IS_LEGACY_RATE(sc, skb)) {
+                    info->flags &= (~IEEE80211_TX_CTL_AMPDU);
+                    goto tx_mpdu;
+                }
+#if 0
+                u8 tidno;
+                struct ieee80211_sta *sta = info->control.sta;
+                struct ssv_sta_priv_data *ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+                tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
+                if((ssv_sta_priv->ampdu_tid[tidno].state == AMPDU_STATE_OPERATION) &&
+                   (sc->ampdu_rekey_pause < AMPDU_REKEY_PAUSE_ONGOING))
+#endif
+                    if (ssv6200_ampdu_tx_handler(hw, skb)) {
+                        break;
+                    } else {
+                        info->flags &= (~IEEE80211_TX_CTL_AMPDU);
+                    }
+            }
+tx_mpdu:
+            if(sc->ccmp_h_sel)
+                SSV_PUT_MIC_SPACE_FOR_HW_CCMP_ENCRYPT(sc, skb);
+            ssv6xxx_ampdu2mpdu(hw, vif, skb);
+            SSV_ADD_TXINFO(sc, skb);
+            if( vif &&
+                vif->type == NL80211_IFTYPE_AP &&
+                (sc->bq4_dtim) &&
+                info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM ) {
+                struct ssv_vif_priv_data *priv_vif = (struct ssv_vif_priv_data *)vif->drv_priv;
+                u8 buffered = 0;
+                spin_lock_irqsave(&sc->ps_state_lock, flags);
+                if (priv_vif->sta_asleep_mask) {
+                    buffered = ssv6200_bcast_enqueue(sc, &sc->bcast_txq, skb);
+                    if (1 == buffered) {
+#ifdef BCAST_DEBUG
+                        dev_dbg(sc->dev, "ssv6200_tx:ssv6200_bcast_start\n");
+#endif
+                        ssv6200_bcast_start(sc);
+                    }
+                }
+                spin_unlock_irqrestore(&sc->ps_state_lock, flags);
+                if (buffered)
+                    break;
+            }
+            if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
+                struct ssv_vif_priv_data *vif_priv = (struct ssv_vif_priv_data *)vif->drv_priv;
+                dev_dbg(sc->dev, "vif[%d] sc->bq4_dtim[%d]\n", vif_priv->vif_idx, sc->bq4_dtim);
+            }
+            if ((sc->bScanning &&
+                 vif->p2p &&
+                 ieee80211_is_nullfunc(hdr->frame_control) &&
+                 ieee80211_has_pm(hdr->frame_control))
+                || (IS_MGMT_AND_BLOCK_CNTL(sc, hdr))) {
+                skb_pull(skb, SSV_GET_TX_DESC_SIZE(sc->sh));
+                info = IEEE80211_SKB_CB(skb);
+                ieee80211_tx_info_clear_status(info);
+                info->flags |= IEEE80211_TX_STAT_ACK;
+                info->status.ack_signal = 100;
+                ieee80211_tx_status(sc->hw, skb);
+            } else {
+                txq_idx = SSV_GET_TX_DESC_TXQ_IDX(sc->sh, skb);
+                ret = HCI_SEND(sc->sh, skb, txq_idx);
+            }
+            send_hci = true;
+        } while (0);
+#ifdef ENABLE_TX_Q_FLOW_CONTROL
+        if ( (skb_queue_len(&sc->tx_skb_q) < LOW_TX_Q_LEN)
+#ifdef MULTI_THREAD_ENCRYPT
+             && (skb_queue_len(&sc->preprocess_q) < LOW_CRYPTO_Q_LEN)
+             && (skb_queue_len(&sc->crypted_q) < LOW_CRYPTO_Q_LEN)
+#endif
+           ) {
+            if (sc->tx.flow_ctrl_status != 0) {
+                int ac;
+                for (ac = 0; ac < sc->hw->queues; ac++) {
+                    if ((sc->tx.flow_ctrl_status & BIT(ac)) == 0)
+                        ieee80211_wake_queue(sc->hw, ac);
+                }
+            } else {
+                ieee80211_wake_queues(sc->hw);
+            }
+        }
+#endif
+        if(sc->dbg_tx_frame) {
+            if(send_hci)
+                dev_dbg(sc->dev, "Tx frame send to HCI\n");
+            else
+                dev_dbg(sc->dev, "Tx frame queued\n");
+            dev_dbg(sc->dev, "================================================\n");
+        }
+    }
+#ifdef MULTI_THREAD_ENCRYPT
+    bool _is_encrypt_needed(struct sk_buff *skb) {
+        struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
+        struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
+        struct SKB_info_st *skb_info = (struct SKB_info_st *)skb->head;
+        struct ieee80211_sta *sta = skb_info->sta;
+        struct ssv_vif_priv_data *vif_priv = (struct ssv_vif_priv_data *)info->control.vif->drv_priv;
+        struct ssv_sta_priv_data *ssv_sta_priv = sta ? (struct ssv_sta_priv_data *)sta->drv_priv : NULL;
+        if ( ( !ieee80211_is_data_qos(hdr->frame_control)
+               && !ieee80211_is_data(hdr->frame_control))
+             || !ieee80211_has_protected(hdr->frame_control))
+            return false;
+        if (!is_unicast_ether_addr(hdr->addr1)) {
+            if ( vif_priv->is_security_valid
+                 && vif_priv->need_sw_encrypt
+#ifdef USE_LOCAL_CRYPTO
+                 && (vif_priv->crypto_data.ops != NULL)
+#endif
+               ) {
+                return true;
+            }
+        } else if (ssv_sta_priv != NULL) {
+            if ( ssv_sta_priv->need_sw_encrypt
+#ifdef USE_LOCAL_CRYPTO
+                 && (ssv_sta_priv->crypto_data.ops != NULL)
+#endif
+               )
+                return true;
+        }
+        return false;
+    }
+#endif
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,0,0)
+    static int ssv6200_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
+#elif LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0)
+    static void ssv6200_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
+#else
+    static void ssv6200_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control, struct sk_buff *skb)
+#endif
+    {
+        struct ssv_softc *sc = (struct ssv_softc *)hw->priv;
+        struct SKB_info_st *skb_info = (struct SKB_info_st *)skb->head;
+#ifdef MULTI_THREAD_ENCRYPT
+        struct ssv_encrypt_task_list *ta = NULL;
+        unsigned long flags;
+        int ret = -EOPNOTSUPP;
+#endif
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0)
+        struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
+        skb_info->sta = info->control.sta;
+#else
+        skb_info->sta = control ? control->sta : NULL;
+#endif
+#ifdef CONFIG_DEBUG_SKB_TIMESTAMP
+        skb_info->timestamp = ktime_get();
+#endif
+#if 0
+        _ssv6xxx_tx(hw, skb);
+#else
+#ifndef MULTI_THREAD_ENCRYPT
+        skb_queue_tail(&sc->tx_skb_q, skb);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+        if (sc->max_tx_skb_q_len < skb_queue_len(&sc->tx_skb_q))
+            sc->max_tx_skb_q_len = skb_queue_len(&sc->tx_skb_q);
+#endif
+        wake_up_interruptible(&sc->tx_wait_q);
+#else
+        skb_info->crypt_st = PKT_CRYPT_ST_ENC_DONE;
+        if(_is_encrypt_needed(skb)) {
+            skb_info->crypt_st = PKT_CRYPT_ST_ENC_PRE;
+            ret = ssv6xxx_skb_pre_encrypt(skb, sc);
+        }
+        if (ret == 0) {
+            bool done = false;
+            spin_lock_irqsave(&sc->crypt_st_lock, flags);
+            __skb_queue_tail(&sc->preprocess_q, skb);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+            if (sc->max_preprocess_q_len < skb_queue_len(&sc->preprocess_q))
+                sc->max_preprocess_q_len = skb_queue_len(&sc->preprocess_q);
+#endif
+            spin_unlock_irqrestore(&sc->crypt_st_lock, flags);
+            list_for_each_entry(ta, &sc->encrypt_task_head, list) {
+                if((cpu_online(ta->cpu_no)) && (ta->running == 0)) {
+                    wake_up(&ta->encrypt_wait_q);
+                    done = true;
+                    break;
+                }
+            }
+            if (done == false) {
+                wake_up(&ta->encrypt_wait_q);
+            }
+        } else if(ret == -EOPNOTSUPP) {
+            skb_info->crypt_st = PKT_CRYPT_ST_NOT_SUPPORT;
+            skb_queue_tail(&sc->tx_skb_q, skb);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+            if (sc->max_tx_skb_q_len < skb_queue_len(&sc->tx_skb_q))
+                sc->max_tx_skb_q_len = skb_queue_len(&sc->tx_skb_q);
+#endif
+            wake_up_interruptible(&sc->tx_wait_q);
+        } else {
+            dev_err(sc->dev, "strange fail to pre-encrypt packet/n");
+        }
+#endif
+#endif
+#ifdef ENABLE_TX_Q_FLOW_CONTROL
+        do {
+#ifdef MULTI_THREAD_ENCRYPT
+            if ( (skb_queue_len(&sc->preprocess_q) >= MAX_CRYPTO_Q_LEN)
+                 || (skb_queue_len(&sc->crypted_q) >= MAX_CRYPTO_Q_LEN)) {
+                ieee80211_stop_queues(sc->hw);
+                break;
+            }
+#endif
+            if (skb_queue_len(&sc->tx_skb_q) >= MAX_TX_Q_LEN)
+                ieee80211_stop_queues(sc->hw);
+        } while (0);
+#endif
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,0,0)
+        return NETDEV_TX_OK;
+#endif
+    }
+#ifdef MULTI_THREAD_ENCRYPT
+    int ssv6xxx_encrypt_task (void *data) {
+        struct ssv_softc *sc = (struct ssv_softc *)data;
+        unsigned long flags;
+        struct ssv_encrypt_task_list *ta = NULL;
+        struct task_struct *this_task = current;
+        int ori_prio;
+        int min_prio;
+        int cur_prio;
+        u32 cont_crypto_failure = 0;
+        const u32 max_cont_crypto_failure = 10;
+        ori_prio = this_task->prio;
+        min_prio = 0;
+        cur_prio = ori_prio;
+        dev_err(sc->dev, "Crypto task %d running with priority %d.\n", this_task->pid, ori_prio);
+        list_for_each_entry(ta, &sc->encrypt_task_head, list) {
+            if(ta->encrypt_task == current)
+                break;
+        }
+        while (!kthread_should_stop()) {
+            struct sk_buff *skb = NULL;
+            struct ieee80211_hdr *hdr = NULL;
+            unsigned long CPUMask = 0;
+            int enc_ret = 0;
+            volatile bool wakeup_tx;
+            if(skb_queue_len_safe(&sc->preprocess_q) == 0 || (ta->cpu_offline != 0) ) {
+                ta->running = 0;
+                set_current_state(TASK_UNINTERRUPTIBLE);
+                wait_event_timeout(ta->encrypt_wait_q,
+                                   ( (ta->cpu_offline == 0)
+                                     && (ta->paused == 0)
+                                     && skb_queue_len_safe(&sc->preprocess_q))
+                                   || kthread_should_stop(),
+                                   msecs_to_jiffies(60000));
+                set_current_state(TASK_RUNNING);
+                ta->running = 1;
+                CPUMask = *(cpumask_bits(&current->cpus_allowed));
+            }
+            if (kthread_should_stop()) {
+                dev_dbg(sc->dev, "[MT-ENCRYPT]: Quit Encryption task loop ...\n");
+                ta->running = 0;
+                break;
+            }
+            spin_lock_irqsave(&sc->crypt_st_lock, flags);
+            if ((skb = __skb_dequeue(&sc->preprocess_q)) != NULL) {
+                SKB_info * skb_info = (SKB_info *)skb->head;
+                __skb_queue_tail(&sc->crypted_q, skb);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+                if (sc->max_crypted_q_len < skb_queue_len(&sc->crypted_q))
+                    sc->max_crypted_q_len = skb_queue_len(&sc->crypted_q);
+#endif
+                spin_unlock_irqrestore(&sc->crypt_st_lock, flags);
+                if(skb_info->crypt_st == PKT_CRYPT_ST_ENC_PRE) {
+                    enc_ret = ssv6xxx_skb_encrypt(skb, sc);
+                    if (enc_ret == 0) {
+                        skb_info->crypt_st = PKT_CRYPT_ST_ENC_DONE;
+                        cont_crypto_failure = 0;
+                        if (cur_prio != ori_prio) {
+                            struct sched_param sp = { .sched_priority = ori_prio };
+                            spin_lock_irqsave(&sc->crypt_st_lock, flags);
+                            dev_err(sc->dev, "Set crypto task %d priority to %d.\n",
+                                    this_task->pid, sp.sched_priority);
+                            sched_setscheduler(this_task, this_task->policy, &sp);
+                            cur_prio = ori_prio;
+                            spin_unlock_irqrestore(&sc->crypt_st_lock, flags);
+                        }
+                    } else {
+                        skb_info->crypt_st = PKT_CRYPT_ST_FAIL;
+                    }
+                } else if(skb_info->crypt_st == PKT_CRYPT_ST_DEC_PRE) {
+                    struct ieee80211_sta *sta = skb_info->sta;
+                    struct ieee80211_rx_status *rxs = IEEE80211_SKB_RXCB(skb);
+                    enc_ret = ssv6xxx_skb_decrypt(skb, sta, sc);
+                    if (enc_ret >= 0) {
+                        skb_info->crypt_st = PKT_CRYPT_ST_DEC_DONE;
+                        hdr = (struct ieee80211_hdr *)(skb->data);
+                        hdr->frame_control = hdr->frame_control & ~(cpu_to_le16(IEEE80211_FCTL_PROTECTED));
+                        rxs->flag |= (RX_FLAG_DECRYPTED|RX_FLAG_IV_STRIPPED);
+                    } else {
+                        dev_err(sc->dev, "Decrypt fail, skb = %p\n", skb);
+                        skb_info->crypt_st = PKT_CRYPT_ST_FAIL;
+                    }
+                }
+                if (skb_info->crypt_st == PKT_CRYPT_ST_FAIL) {
+                    spin_lock_irqsave(&sc->crypt_st_lock, flags);
+                    __skb_unlink(skb, &sc->crypted_q);
+                    dev_err(sc->dev, "%d-%d(%d) crypto fail, skb = %p %d %d\n",
+                            this_task->on_cpu, this_task->pid, cur_prio, skb,
+                            cont_crypto_failure, ta->paused);
+                    spin_unlock_irqrestore(&sc->crypt_st_lock, flags);
+                    ssv_skb_free(sc, skb);
+                    skb = NULL;
+                    if (cont_crypto_failure == max_cont_crypto_failure) {
+                        spin_lock_irqsave(&sc->crypt_st_lock, flags);
+                        if (cur_prio != min_prio) {
+                            struct sched_param sp = { .sched_priority = min_prio };
+                            sched_setscheduler(this_task, this_task->policy, &sp);
+                            cur_prio = min_prio;
+                            dev_err(sc->dev, "Set crypto task %d priority to %d.\n",
+                                    this_task->pid, sp.sched_priority);
+                        }
+                        spin_unlock_irqrestore(&sc->crypt_st_lock, flags);
+                    } else {
+                        ++cont_crypto_failure;
+                    }
+                    schedule();
+                }
+            } else {
+                spin_unlock_irqrestore(&sc->crypt_st_lock, flags);
+            }
+            spin_lock_irqsave(&sc->crypt_st_lock, flags);
+            skb = NULL;
+            wakeup_tx = false;
+            while((skb = skb_peek(&sc->crypted_q)) != NULL) {
+                SKB_info* skb_info = (SKB_info*)skb->head;
+                if(skb_info->crypt_st == PKT_CRYPT_ST_ENC_DONE) {
+                    __skb_unlink(skb, &sc->crypted_q);
+                    skb_queue_tail(&sc->tx_skb_q, skb);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+                    if (sc->max_tx_skb_q_len < skb_queue_len(&sc->tx_skb_q))
+                        sc->max_tx_skb_q_len = skb_queue_len(&sc->tx_skb_q);
+#endif
+                    wakeup_tx = true;
+                    skb = NULL;
+                } else if(skb_info->crypt_st == PKT_CRYPT_ST_DEC_DONE) {
+                    __skb_unlink(skb, &sc->crypted_q);
+                    ieee80211_rx_irqsafe(sc->hw, skb);
+                } else
+                    break;
+            }
+            spin_unlock_irqrestore(&sc->crypt_st_lock, flags);
+            skb = NULL;
+            if(wakeup_tx) {
+                wake_up_interruptible(&sc->tx_wait_q);
+            }
+        }
+        return 0;
+    }
+    void _stop_crypto_task (struct ssv_softc *sc) {
+        struct ssv_encrypt_task_list *ta = NULL;
+        int num_running = 0;
+        list_for_each_entry(ta, &sc->encrypt_task_head, list) {
+            ta->paused = 1;
+        }
+        do {
+            num_running = 0;
+            list_for_each_entry(ta, &sc->encrypt_task_head, list) {
+                if (ta->running != 0) {
+                    int cpu_id = smp_processor_id();
+                    if (ta->cpu_no == cpu_id) {
+                        unsigned long flags;
+                        spin_lock_irqsave(&sc->crypt_st_lock, flags);
+                        dev_warn(sc->dev, "Crypto running on the same core. (%d, %d)\n", cpu_id, num_running);
+                        spin_unlock_irqrestore(&sc->crypt_st_lock, flags);
+                        continue;
+                    }
+                    ++num_running;
+                    break;
+                }
+            }
+        } while (num_running != 0);
+    }
+    void _resume_crypto_task (struct ssv_softc *sc) {
+        struct ssv_encrypt_task_list *ta = NULL;
+        list_for_each_entry(ta, &sc->encrypt_task_head, list) {
+            ta->paused = 0;
+            wake_up(&ta->encrypt_wait_q);
+        }
+    }
+    u32 _remove_sta_skb_from_q (struct ssv_softc *sc, struct sk_buff_head *q,
+                                u32 addr0_3, u32 addr4_5) {
+        struct sk_buff *skb, *skb_tmp;
+        u32 removed_skb_num = 0;
+        skb_queue_walk_safe(q, skb, skb_tmp) {
+            struct ieee80211_sta *skb_sta;
+            u32 skb_addr0_3;
+            u32 skb_addr4_5;
+            struct SKB_info_st *skb_info = (struct SKB_info_st *)skb->head;
+            skb_sta = skb_info->sta;
+            if (skb_sta == NULL)
+                continue;
+            skb_addr0_3 = *(u32 *)&skb_sta->addr[0];
+            skb_addr4_5 = (u32)*(u16 *)&skb_sta->addr[4];
+            if ((addr0_3 != skb_addr0_3) || (addr4_5 != skb_addr4_5))
+                continue;
+            __skb_unlink(skb, q);
+            ssv6xxx_txbuf_free_skb(skb, sc);
+            ++removed_skb_num;
+        }
+        return removed_skb_num;
+    }
+    void _clean_up_crypto_skb (struct ssv_softc *sc, struct ieee80211_sta *sta) {
+        unsigned long flags;
+        u32 sta_addr0_3 = *(u32 *)&sta->addr[0];
+        u32 sta_addr4_5 = (u32)*(u16 *)&sta->addr[4];
+        u32 removed_skb_num;
+        dev_info(sc->dev, "Clean up skb for STA %pM.\n", sta->addr);
+        _stop_crypto_task(sc);
+        spin_lock_irqsave(&sc->crypt_st_lock, flags);
+        removed_skb_num = _remove_sta_skb_from_q(sc, &sc->preprocess_q,
+                          sta_addr0_3, sta_addr4_5);
+        dev_info(sc->dev, "Removed %u MPDU from precess queue.\n", removed_skb_num);
+        removed_skb_num = _remove_sta_skb_from_q(sc, &sc->crypted_q,
+                          sta_addr0_3, sta_addr4_5);
+        dev_info(sc->dev, "Removed %u MPDU from encrypted queue.\n", removed_skb_num);
+        spin_unlock_irqrestore(&sc->crypt_st_lock, flags);
+        _resume_crypto_task(sc);
+    }
+#endif
+    int ssv6xxx_tx_task (void *data) {
+        struct ssv_softc *sc = (struct ssv_softc *)data;
+        u32 wait_period = SSV_AMPDU_timer_period / 2;
+        txrxboost_init();
+        dev_dbg(sc->dev, "SSV6XXX TX Task started.\n");
+        while (!kthread_should_stop()) {
+            u32 before_timeout = (-1);
+            before_timeout = wait_event_interruptible_timeout(sc->tx_wait_q,
+                             ( skb_queue_len(&sc->tx_skb_q)
+                               || kthread_should_stop()
+                               || sc->tx_q_empty),
+                             msecs_to_jiffies(wait_period));
+            if (kthread_should_stop()) {
+                dev_dbg(sc->dev, "Quit TX task loop...\n");
+                break;
+            }
+            txrxboost_change((u32)atomic_read(&sc->ampdu_tx_frame),
+                             sc->sh->cfg.txrxboost_low_threshold,
+                             sc->sh->cfg.txrxboost_high_threshold,
+                             sc->sh->cfg.txrxboost_prio);
+            do {
+                struct sk_buff *tx_skb = skb_dequeue(&sc->tx_skb_q);
+                if (tx_skb == NULL)
+                    break;
+                _ssv6xxx_tx(sc->hw, tx_skb);
+            } while (1);
+#ifdef CONFIG_DEBUG_SKB_TIMESTAMP
+            {
+                struct ssv_hw_txq *hw_txq = NULL;
+                struct ieee80211_tx_info *tx_info = NULL;
+                struct sk_buff *skb = NULL;
+                int txqid;
+                unsigned int timeout;
+                u32 status;
+                for (txqid=0; txqid<SSV_HW_TXQ_NUM; txqid++) {
+                    hw_txq = &ssv_dbg_ctrl_hci->hw_txq[txqid];
+                    skb = skb_peek(&hw_txq->qhead);
+                    if (skb != NULL) {
+                        tx_info = IEEE80211_SKB_CB(skb);
+                        if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
+                            timeout = cal_duration_of_ampdu(skb, SKB_DURATION_STAGE_IN_HWQ);
+                        else
+                            timeout = cal_duration_of_mpdu(skb);
+                        if (timeout > SKB_DURATION_TIMEOUT_MS) {
+                            HCI_IRQ_STATUS(ssv_dbg_ctrl_hci, &status);
+                            dev_dbg(sc->dev, "hci int_mask: %08x\n", ssv_dbg_ctrl_hci->int_mask);
+                            dev_dbg(sc->dev, "sdio status: %08x\n", status);
+                            dev_dbg(sc->dev, "hwq%d len: %d\n", txqid, skb_queue_len(&hw_txq->qhead));
+                        }
+                    }
+                }
+            }
+#endif
+            if (sc->tx_q_empty || (before_timeout == 0)) {
+                u32 flused_ampdu = ssv6xxx_ampdu_flush(sc->hw);
+                sc->tx_q_empty = false;
+                if (flused_ampdu == 0 && before_timeout == 0) {
+                    wait_period *= 2;
+                    if (wait_period > 1000)
+                        wait_period = 1000;
+                }
+            } else
+                wait_period = SSV_AMPDU_timer_period / 2;
+        }
+        return 0;
+    }
+    int ssv6xxx_rx_task (void *data) {
+        struct ssv_softc *sc = (struct ssv_softc *)data;
+        unsigned long wait_period = msecs_to_jiffies(200);
+        unsigned long last_timeout_check_jiffies = jiffies;
+        unsigned long cur_jiffies;
+        txrxboost_init();
+        dev_dbg(sc->dev, "SSV6XXX RX Task started.\n");
+        while (!kthread_should_stop()) {
+            u32 before_timeout = (-1);
+            before_timeout = wait_event_interruptible_timeout(sc->rx_wait_q,
+                             ( skb_queue_len(&sc->rx_skb_q)
+                               || skb_queue_len(&sc->tx_done_q)
+                               || kthread_should_stop()),
+                             wait_period);
+            if (kthread_should_stop()) {
+                dev_dbg(sc->dev, "Quit RX task loop...\n");
+                break;
+            }
+            txrxboost_change((u32)atomic_read(&sc->ampdu_tx_frame),
+                             sc->sh->cfg.txrxboost_low_threshold,
+                             sc->sh->cfg.txrxboost_high_threshold,
+                             sc->sh->cfg.txrxboost_prio);
+            cur_jiffies = jiffies;
+            if ( (before_timeout == 0)
+                 || time_before((last_timeout_check_jiffies + wait_period), cur_jiffies)) {
+                if (before_timeout == 0)
+                    sc->rx_stuck_idle_time++;
+                ssv6xxx_ampdu_check_timeout(sc->hw);
+                last_timeout_check_jiffies = cur_jiffies;
+            }
+            if (skb_queue_len(&sc->rx_skb_q)) {
+                sc->rx_stuck_idle_time = 0;
+                _process_rx_q(sc, &sc->rx_skb_q, NULL);
+            }
+            if (skb_queue_len(&sc->tx_done_q))
+                _process_tx_done(sc);
+        }
+        return 0;
+    }
+    void ssv6xxx_house_keeping(unsigned long argv) {
+        struct ssv_softc *sc = (struct ssv_softc *)argv;
+        if (!sc->mac80211_dev_started ||
+            (sc->sc_flags & SC_OP_HW_RESET) ||
+            (sc->sc_flags & SC_OP_BLOCK_CNTL))
+            return;
+        if (sc->sh->cfg.online_reset & ONLINE_RESET_ENABLE)
+            queue_work(sc->house_keeping_wq, &sc->rx_stuck_work);
+        queue_work(sc->house_keeping_wq, &sc->mib_edca_work);
+        if (sc->sh->cfg.tx_stuck_detect)
+            queue_work(sc->house_keeping_wq, &sc->tx_poll_work);
+#ifdef CONFIG_SSV_CCI_IMPROVEMENT
+        if ((sc->sh->cfg.cci & CCI_CTL) && (sc->bScanning == false)) {
+            if (sc->cci_modified) {
+                queue_work(sc->house_keeping_wq, &sc->cci_set_work);
+            }
+            if ((sc->cci_start) && (sc->sh->cfg.cci & CCI_SMART)) {
+                sc->cci_rx_unavailable_counter ++;
+                if (sc->sh->cfg.cci & CCI_DBG)
+                    dev_dbg(sc->dev, "cci rx not available count %d\n", sc->cci_rx_unavailable_counter);
+                if (sc->cci_rx_unavailable_counter >= 2) {
+                    queue_work(sc->house_keeping_wq, &sc->cci_clean_work);
+                    sc->cci_rx_unavailable_counter = 0;
+                }
+            }
+        }
+#endif
+        if ((sc->gt_enabled) && (sc->bScanning == false)) {
+            queue_work(sc->house_keeping_wq, &sc->set_txpwr_work);
+        }
+        if (sc->thermal_monitor) {
+            sc->thermal_monitor_counter ++;
+            if (sc->thermal_monitor_counter == HOUSE_KEEPING_10_SEC) {
+                queue_work(sc->house_keeping_wq, &sc->thermal_monitor_work);
+                sc->thermal_monitor_counter = 0;
+            }
+        }
+        mod_timer(&sc->house_keeping, jiffies + msecs_to_jiffies(HOUSE_KEEPING_TIMEOUT));
+    }
+#ifdef CONFIG_SMARTLINK
+    int ssv6xxx_get_channel(struct ssv_softc *sc, int *pch) {
+        *pch = sc->hw_chan;
+        return 0;
+    }
+    int ssv6xxx_set_promisc(struct ssv_softc *sc, int accept) {
+        u32 val=0;
+        if (accept)
+            val = MRX_MODE_PROMISCUOUS;
+        else
+            val = MRX_MODE_NORMAL;
+#ifdef SSV_SUPPORT_HAL
+        HAL_SET_MRX_MODE(sc->sh, val);
+#else
+        SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_TB13, val);
+#endif
+        return 0;
+    }
+    int ssv6xxx_get_promisc(struct ssv_softc *sc, int *paccept) {
+        u32 val=0;
+#ifdef SSV_SUPPORT_HAL
+        HAL_GET_MRX_MODE(sc->sh, &val);
+#else
+        SMAC_REG_READ(sc->sh, ADR_MRX_FLT_TB13, &val);
+#endif
+        if (val == MRX_MODE_PROMISCUOUS)
+            *paccept = 1;
+        else
+            *paccept = 0;
+        return 0;
+    }
+#endif
+    static int ssv6200_start(struct ieee80211_hw *hw) {
+        struct ssv_softc *sc = hw->priv;
+        struct ssv_hw *sh = sc->sh;
+        struct ieee80211_channel *chan;
+        enum nl80211_channel_type channel_type;
+        mutex_lock(&sc->mutex);
+        if (tu_ssv6xxx_init_mac(sc->sh) != 0) {
+            dev_dbg(sc->dev, "Initialize ssv6200 mac fail!!\n");
+            mutex_unlock(&sc->mutex);
+            return -1;
+        }
+#ifdef CONFIG_P2P_NOA
+        ssv6xxx_noa_reset(sc);
+#endif
+        HCI_START(sh);
+#ifndef SSV_SUPPORT_USB_LPM
+        SSV_SET_USB_LPM(sc, 0);
+#endif
+        {
+            int ret = SSV_DO_IQ_CALIB(sh, &sh->iqk_cfg);
+            if (ret != 0) {
+                dev_dbg(sc->dev, "IQ Calibration failed (%d)!!\n", ret);
+                mutex_unlock(&sc->mutex);
+                return ret;
+            }
+        }
+        SSV_EDCA_ENABLE(sc->sh, true);
+        SSV_SAVE_DEFAULT_IPD_CHCFG(sh);
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0)
+        chan = hw->conf.channel;
+        channel_type = hw->conf.channel_type;
+#else
+        chan = hw->conf.chandef.chan;
+        channel_type = cfg80211_get_chandef_type(&hw->conf.chandef);
+#endif
+        sc->cur_channel = chan;
+        dev_dbg(sc->dev, "%s(): current channel: %d,sc->ps_status=%d\n", __FUNCTION__, sc->cur_channel->hw_value,sc->ps_status);
+        HAL_SET_CHANNEL(sc, chan, channel_type);
+        sc->hw_chan = chan->hw_value;
+        sc->hw_chan_type = channel_type;
+        ieee80211_wake_queues(hw);
+        ssv6200_ampdu_init(hw);
+        SSV_SET_RF_ENABLE(sh);
+        sc->mac80211_dev_started = true;
+        SSV_SEND_TX_POLL_CMD(sc->sh, SSV6XXX_TX_POLL_START);
+        sc->house_keeping.expires = jiffies + msecs_to_jiffies(HOUSE_KEEPING_TIMEOUT);
+        if (!timer_pending(&sc->house_keeping))
+            add_timer(&sc->house_keeping);
+        mutex_unlock(&sc->mutex);
+        return 0;
+    }
+    static void ssv6200_stop(struct ieee80211_hw *hw) {
+        struct ssv_softc *sc=hw->priv;
+        u32 count=0;
+        dev_dbg(sc->dev, KERN_INFO "%s(): sc->ps_status=%d\n", __FUNCTION__,sc->ps_status);
+        mutex_lock(&sc->mutex);
+        sc->mac80211_dev_started = false;
+        SSV_SEND_TX_POLL_CMD(sc->sh, SSV6XXX_TX_POLL_STOP);
+        ssv6200_ampdu_deinit(hw);
+        SSV_SET_RF_DISABLE(sc->sh);
+        HCI_STOP(sc->sh);
+#ifndef NO_USE_RXQ_LOCK
+        while(0) {
+#else
+        while (skb_queue_len(&sc->rx.rxq_head)) {
+#endif
+            dev_dbg(sc->dev, "sc->rx.rxq_count=%d\n", sc->rx.rxq_count);
+            count ++;
+            if (count > 90000000) {
+                dev_dbg(sc->dev, "ERROR....ERROR......ERROR..........\n");
+                break;
+            }
+        }
+        HCI_TXQ_FLUSH(sc->sh, (TXQ_EDCA_0|TXQ_EDCA_1|TXQ_EDCA_2|
+                               TXQ_EDCA_3|TXQ_MGMT));
+#if 0
+        cancel_work_sync(&sc->rx_work);
+#endif
+        if((sc->ps_status == PWRSV_PREPARE)||(sc->ps_status == PWRSV_ENABLE)) {
+            ssv6xxx_enable_ps(sc);
+            SSV_SET_RF_ENABLE(sc->sh);
+        }
+        mutex_unlock(&sc->mutex);
+        dev_dbg(sc->dev, "%s(): leave\n", __FUNCTION__);
+    }
+    struct ssv_vif_priv_data * ssv6xxx_config_vif_res(struct ssv_softc *sc,
+            struct ieee80211_vif *vif) {
+        int i, vif_idx = -1;
+        struct ssv_vif_priv_data *priv_vif;
+        struct ssv_vif_info *vif_info;
+        bool find_empty_vif_idx = false;
+        lockdep_assert_held(&sc->mutex);
+        for (i=0 ; i<SSV6200_MAX_VIF ; i++) {
+            if ((sc->vif_info[i].vif != NULL) && (!memcmp(vif->addr, sc->vif_info[i].vif->addr, ETH_ALEN))) {
+                vif_idx = i;
+                break;
+            }
+            if ((sc->vif_info[i].vif == NULL) && !find_empty_vif_idx) {
+                find_empty_vif_idx = true;
+                vif_idx = i;
+            }
+        }
+        BUG_ON(vif_idx < 0);
+        dev_dbg(sc->dev, "ssv6xxx_config_vif_res id[%d].\n", vif_idx);
+        priv_vif = (struct ssv_vif_priv_data *)vif->drv_priv;
+        memset(priv_vif, 0, sizeof(struct ssv_vif_priv_data));
+        priv_vif->vif_idx = vif_idx;
+        memset(&sc->vif_info[vif_idx], 0, sizeof(sc->vif_info[0]));
+        sc->vif_info[vif_idx].vif = vif;
+        sc->vif_info[vif_idx].vif_priv = priv_vif;
+        INIT_LIST_HEAD(&priv_vif->sta_list);
+        priv_vif->pair_cipher = SSV_CIPHER_NONE;
+        priv_vif->group_cipher = SSV_CIPHER_NONE;
+        priv_vif->has_hw_decrypt = false;
+        priv_vif->has_hw_encrypt = false;
+        priv_vif->need_sw_encrypt = false;
+        priv_vif->need_sw_decrypt = false;
+        priv_vif->use_mac80211_decrypt = false;
+        priv_vif->is_security_valid = false;
+        priv_vif->force_sw_encrypt = (vif->type == NL80211_IFTYPE_AP);
+        priv_vif->wep_idx = -1;
+#ifdef USE_LOCAL_CRYPTO
+        if (SSV_NEED_SW_CIPHER(sc->sh)) {
+            priv_vif->crypto_data.ops = NULL;
+            priv_vif->crypto_data.priv = NULL;
+#ifdef HAS_CRYPTO_LOCK
+            rwlock_init(&priv_vif->crypto_data.lock);
+#endif
+        }
+#endif
+        vif_info = &sc->vif_info[priv_vif->vif_idx];
+        vif_info->if_type = vif->type;
+        vif_info->vif = vif;
+        return priv_vif;
+    }
+    static void _if_set_apmode(struct ieee80211_hw *hw,
+                               struct ieee80211_vif *vif) {
+        struct ssv_softc *sc=hw->priv;
+        struct ieee80211_channel *chan;
+        struct ssv_vif_priv_data *vif_priv = (struct ssv_vif_priv_data *)vif->drv_priv;
+        SSV_SET_BSSID(sc->sh, sc->sh->cfg.maddr[vif_priv->vif_idx], vif_priv->vif_idx);
+        SSV_SET_OP_MODE(sc->sh, SSV6XXX_OPMODE_AP, vif_priv->vif_idx);
+        BUG_ON(sc->ap_vif != NULL);
+        sc->ap_vif = vif;
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0)
+        chan = hw->conf.channel;
+#else
+        chan = hw->conf.chandef.chan;
+#endif
+        dev_dbg(sc->dev, "AP created at ch %d \n", chan->hw_value);
+        if ( !vif->p2p
+             && (vif_priv->vif_idx == 0)) {
+            dev_dbg(sc->dev, "Normal AP mode. Config Q4 to DTIM Q.\n");
+            SSV_HALT_MNGQ_UNTIL_DTIM(sc->sh);
+            sc->bq4_dtim = true;
+        }
+#ifdef CONFIG_SSV_SUPPORT_ANDROID
+        if(vif->p2p == 0) {
+            dev_dbg(sc->dev, KERN_INFO "AP mode init wifi_alive_lock\n");
+            ssv_wake_lock(sc);
+        }
+#endif
+    }
+    static int ssv6200_add_interface(struct ieee80211_hw *hw,
+                                     struct ieee80211_vif *vif) {
+        struct ssv_softc *sc=hw->priv;
+        int ret=0;
+        struct ssv_vif_priv_data *vif_priv = NULL;
+        dev_dbg(sc->dev, "[I] %s(): \n", __FUNCTION__);
+        if ( (sc->nvif >= SSV6200_MAX_VIF)
+             || ( ( (vif->type == NL80211_IFTYPE_AP)
+                    || (vif->p2p))
+                  && (sc->ap_vif != NULL))) {
+            dev_err(sc->dev, "Add interface of type %d (p2p: %d) failed.\n", vif->type, vif->p2p);
+            return -EOPNOTSUPP;
+        }
+        HCI_WRITE_HW_CONFIG_ON(sc->sh);
+        mutex_lock(&sc->mutex);
+        vif_priv = ssv6xxx_config_vif_res(sc, vif);
+        SSV_SET_MACADDR(sc->sh, vif_priv->vif_idx);
+        if ((vif->type == NL80211_IFTYPE_AP) || (vif->type == NL80211_IFTYPE_P2P_GO))
+            _if_set_apmode(hw, vif);
+        sc->nvif++;
+        dev_dbg(sc->dev, "VIF %02x:%02x:%02x:%02x:%02x:%02x of type %d is added.\n",
+                vif->addr[0], vif->addr[1], vif->addr[2],
+                vif->addr[3], vif->addr[4], vif->addr[5], vif->type);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+        ssv6xxx_debugfs_add_interface(sc, vif);
+#endif
+        mutex_unlock(&sc->mutex);
+        HCI_WRITE_HW_CONFIG_OFF(sc->sh);
+        return ret;
+    }
+    static int ssv6200_change_interface(struct ieee80211_hw *hw,
+                                        struct ieee80211_vif *vif,
+                                        enum nl80211_iftype new_type,
+                                        bool p2p) {
+        struct ssv_softc *sc = hw->priv;
+        struct ssv_vif_priv_data *vif_priv = (struct ssv_vif_priv_data *)vif->drv_priv;
+        int vif_idx = vif_priv->vif_idx;
+        mutex_lock(&sc->mutex);
+        dev_dbg(sc->dev, "@@@@@@ change id[%d] type %d to %d, p2p=%d\n", vif_idx, sc->vif_info[vif_idx].if_type, new_type, p2p);
+        sc->vif_info[vif_idx].if_type = new_type;
+        sc->force_disable_directly_ack_tx = p2p;
+        vif->type = new_type;
+        if ((vif->type == NL80211_IFTYPE_AP) || (vif->type == NL80211_IFTYPE_P2P_GO))
+            _if_set_apmode(hw, vif);
+        else {
+            u8 null_addr[6]= {0, 0, 0, 0, 0, 0};
+            sc->ap_vif = NULL;
+            SSV_SET_BSSID(sc->sh, null_addr, vif_priv->vif_idx);
+            SSV_SET_OP_MODE(sc->sh, SSV6XXX_OPMODE_STA, vif_priv->vif_idx);
+        }
+        vif->p2p = p2p;
+        mutex_unlock(&sc->mutex);
+        return 0;
+    }
+    static void ssv6200_remove_interface(struct ieee80211_hw *hw,
+                                         struct ieee80211_vif *vif) {
+        struct ssv_softc *sc = hw->priv;
+        struct ssv_vif_priv_data *vif_priv = (struct ssv_vif_priv_data *)vif->drv_priv;
+        dev_err(sc->dev,
+                "Removing interface %02x:%02x:%02x:%02x:%02x:%02x. PS=%d\n",
+                vif->addr[0], vif->addr[1], vif->addr[2],
+                vif->addr[3], vif->addr[4], vif->addr[5], sc->ps_status);
+        HCI_WRITE_HW_CONFIG_ON(sc->sh);
+        mutex_lock(&sc->mutex);
+#ifdef USE_LOCAL_CRYPTO
+        if (SSV_NEED_SW_CIPHER(sc->sh)) {
+            INIT_WRITE_CRYPTO_DATA(crypto_data, &vif_priv->crypto_data);
+            START_WRITE_CRYPTO_DATA(crypto_data);
+            if (crypto_data->ops && crypto_data->priv) {
+                crypto_data->ops->deinit(crypto_data->priv);
+            }
+            crypto_data->ops = NULL;
+            crypto_data->priv = NULL;
+            END_WRITE_CRYPTO_DATA(crypto_data);
+        }
+#endif
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+        ssv6xxx_debugfs_remove_interface(sc, vif);
+#endif
+        if (vif->type == NL80211_IFTYPE_AP) {
+            if (sc->bq4_dtim) {
+                sc->bq4_dtim = false;
+                ssv6200_release_bcast_frame_res(sc, vif);
+                SSV_UNHALT_MNGQ_UNTIL_DTIM(sc->sh);
+                dev_dbg(sc->dev, "Config Q4 to normal Q \n");
+            }
+            ssv6xxx_beacon_release(sc);
+            sc->ap_vif = NULL;
+#ifdef CONFIG_SSV_SUPPORT_ANDROID
+            if(vif->p2p == 0) {
+                ssv_wake_unlock(sc);
+                dev_dbg(sc->dev, KERN_INFO "AP mode destroy wifi_alive_lock\n");
+            }
+#endif
+        }
+        if (vif->type == NL80211_IFTYPE_STATION)
+            SSV_BEACON_LOSS_DISABLE(sc->sh);
+        memset(&sc->vif_info[vif_priv->vif_idx], 0, sizeof(struct ssv_vif_info));
+        sc->nvif--;
+        mutex_unlock(&sc->mutex);
+        HCI_WRITE_HW_CONFIG_OFF(sc->sh);
+    }
+    void ssv6xxx_enable_ps(struct ssv_softc *sc) {
+        sc->ps_status = PWRSV_ENABLE;
+    }
+    void ssv6xxx_disable_ps(struct ssv_softc *sc) {
+        sc->ps_status = PWRSV_DISABLE;
+        dev_dbg(sc->dev, KERN_INFO "PowerSave disabled\n");
+    }
+    static bool ssv6200_not_dual_intf_on_line(struct ssv_softc *sc) {
+        struct ieee80211_vif *vif;
+        int i = 0, assoc = 0, p2p = 0;
+        for (i = 0; i < SSV6200_MAX_VIF; i++) {
+            if (sc->vif_info[i].vif != NULL) {
+                vif = sc->vif_info[i].vif;
+                if ((vif->type == NL80211_IFTYPE_STATION) || (vif->type == NL80211_IFTYPE_P2P_CLIENT)) {
+                    if (vif->bss_conf.assoc)
+                        assoc++;
+                    if (vif->p2p)
+                        p2p++;
+                }
+            }
+        }
+        if ((p2p > 0) || (assoc == 2))
+            return false;
+        return true;
+    }
+    int ssvxxx_get_sta_assco_cnt(struct ssv_softc *sc) {
+        struct ieee80211_vif *vif;
+        int i = 0, assoc = 0;
+        for (i = 0; i < SSV6200_MAX_VIF; i++) {
+            if (sc->vif_info[i].vif != NULL) {
+                vif = sc->vif_info[i].vif;
+                if ((vif->type == NL80211_IFTYPE_STATION) || (vif->type == NL80211_IFTYPE_P2P_CLIENT)) {
+                    if (vif->bss_conf.assoc)
+                        assoc++;
+                }
+            }
+        }
+        return assoc;
+    }
+    static int ssv6200_config(struct ieee80211_hw *hw, u32 changed) {
+        struct ssv_softc *sc=hw->priv;
+        int ret=0;
+        HCI_WRITE_HW_CONFIG_ON(sc->sh);
+        mutex_lock(&sc->mutex);
+        if (changed & IEEE80211_CONF_CHANGE_POWER) {
+            struct ieee80211_conf *conf = &hw->conf;
+            dev_dbg(sc->dev, "IEEE80211_CONF_CHANGE_POWER change power level to %d\n", conf->power_level);
+        }
+        if (changed & IEEE80211_CONF_CHANGE_PS) {
+            struct ieee80211_conf *conf = &hw->conf;
+            if (conf->flags & IEEE80211_CONF_PS) {
+                dev_dbg(sc->dev, "Enable IEEE80211_CONF_PS ps_aid=%d\n",sc->ps_aid);
+            } else {
+                dev_dbg(sc->dev, "Disable IEEE80211_CONF_PS ps_aid=%d\n",sc->ps_aid);
+            }
+        }
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,0,0)
+        if (changed & IEEE80211_CONF_CHANGE_QOS) {
+            struct ieee80211_conf *conf = &hw->conf;
+            bool qos_active = !!(conf->flags & IEEE80211_CONF_QOS);
+            SMAC_REG_SET_BITS(sc->sh, ADR_GLBLE_SET,
+                              (qos_active<<QOS_EN_SFT), QOS_EN_MSK);
+        }
+#endif
+        if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
+            struct ieee80211_channel *chan;
+            enum nl80211_channel_type channel_type;
+            if ((sc->sc_flags & SC_OP_HW_RESET) ||
+                (sc->sc_flags & SC_OP_CHAN_FIXED))
+                goto out;
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0)
+            chan = hw->conf.channel;
+            channel_type = hw->conf.channel_type;
+#else
+            chan = hw->conf.chandef.chan;
+            channel_type = cfg80211_get_chandef_type(&hw->conf.chandef);
+#endif
+#if defined (CONFIG_SSV_SMARTLINK) || defined (CONFIG_SMARTLINK)
+            if (sc->ssv_smartlink_status) {
+                dev_dbg(sc->dev, "@@ %d\n",sc->ssv_smartlink_status);
+                goto out;
+            }
+#endif
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,0,0)
+            {
+                struct ieee80211_channel *curchan = hw->conf.channel;
+                if(sc->bScanning == true &&
+                   sc->channel_center_freq != curchan->center_freq && sc->isAssoc) {
+                    hw->conf.flags |= IEEE80211_CONF_OFFCHANNEL;
+                } else {
+                    hw->conf.flags &= ~IEEE80211_CONF_OFFCHANNEL;
+                }
+            }
+#endif
+#ifdef CONFIG_P2P_NOA
+            if(sc->p2p_noa.active_noa_vif) {
+                dev_dbg(sc->dev, "NOA operating-active vif[%02x] skip scan\n", sc->p2p_noa.active_noa_vif);
+                goto out;
+            }
+#endif
+            if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) {
+                if ( (IS_ALLOW_SCAN || IS_NON_AP_MODE || IS_NONE_STA_CONNECTED_IN_AP_MODE)
+                     && ssv6200_not_dual_intf_on_line(sc)
+                     && ((sc->hw_chan != chan->hw_value) || (sc->hw_chan_type != channel_type)) ) {
+                    int i = 1;
+                    sc->sc_flags |= SC_OP_OFFCHAN;
+                    HCI_PAUSE(sc->sh, (TXQ_EDCA_0|TXQ_EDCA_1|TXQ_EDCA_2|TXQ_EDCA_3| TXQ_MGMT));
+                    sc->rx_data_exist = false;
+                    mdelay(1);
+                    while ((sc->rx_data_exist == true) && (i < 200)) {
+                        i++;
+                        sc->rx_data_exist = false;
+                        mdelay(1);
+                    }
+                    HAL_SET_CHANNEL(sc, chan, channel_type);
+                    sc->hw_chan = chan->hw_value;
+                    sc->hw_chan_type = channel_type;
+                    HCI_RESUME(sc->sh, TXQ_MGMT);
+                } else {
+                    dev_dbg(sc->dev, "Off-channel to %d is ignored\n", chan->hw_value);
+                }
+            } else {
+                if ( ((sc->cur_channel == NULL)
+                      || (sc->sc_flags & SC_OP_OFFCHAN)
+                      || (sc->hw_chan != chan->hw_value)
+                      || (sc->hw_chan_type != channel_type)) ) {
+                    HCI_PAUSE(sc->sh, (TXQ_EDCA_0|TXQ_EDCA_1|TXQ_EDCA_2|TXQ_EDCA_3| TXQ_MGMT));
+                    HAL_SET_CHANNEL(sc, chan, channel_type);
+                    sc->cur_channel = chan;
+                    sc->hw_chan = chan->hw_value;
+                    sc->hw_chan_type = channel_type;
+                    HCI_RESUME(sc->sh, (TXQ_EDCA_0|TXQ_EDCA_1|TXQ_EDCA_2|TXQ_EDCA_3| TXQ_MGMT));
+                    sc->sc_flags &= ~SC_OP_OFFCHAN;
+                } else {
+                    dev_dbg(sc->dev, "Change to the same channel %d\n", chan->hw_value);
+                }
+            }
+        }
+out:
+        mutex_unlock(&sc->mutex);
+        HCI_WRITE_HW_CONFIG_OFF(sc->sh);
+        return ret;
+    }
+#if 0
+    static int sv6200_conf_tx(struct ieee80211_hw *hw,
+                              struct ieee80211_vif *vif, u16 queue,
+                              const struct ieee80211_tx_queue_params *params) {
+        struct ssv_softc *sc = hw->priv;
+        u32 cw;
+        u8 hw_txqid = sc->tx.hw_txqid[queue];
+        dev_dbg(sc->dev, "[I] sv6200_conf_tx qos[%d] queue[%d] aifsn[%d] cwmin[%d] cwmax[%d] txop[%d] \n",
+               vif->bss_conf.qos, queue, params->aifs, params->cw_min, params->cw_max, params->txop);
+        if (queue > NL80211_TXQ_Q_BK)
+            return 1;
+        mutex_lock(&sc->mutex);
+#define QOS_EN_MSK 0x00000010
+#define QOS_EN_I_MSK 0xffffffef
+#define QOS_EN_SFT 4
+#define QOS_EN_HI 4
+#define QOS_EN_SZ 1
+        SMAC_REG_SET_BITS(sc->sh, ADR_GLBLE_SET, (vif->bss_conf.qos<<QOS_EN_SFT), QOS_EN_MSK);
+        cw = params->aifs&0xf;
+        cw|= ((ilog2(params->cw_min+1))&0xf)<<8;
+        cw|= ((ilog2(params->cw_max+1))&0xf)<<12;
+        cw|= ((params->txop)&0xff)<<16;
+        SMAC_REG_WRITE(sc->sh, ADR_TXQ0_MTX_Q_AIFSN+0x100*hw_txqid, cw);
+        mutex_unlock(&sc->mutex);
+        return 0;
+    }
+#endif
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,2,0)
+#define SUPPORTED_FILTERS \
+    (FIF_PROMISC_IN_BSS | \
+    FIF_ALLMULTI | \
+    FIF_CONTROL | \
+    FIF_PSPOLL | \
+    FIF_OTHER_BSS | \
+    FIF_BCN_PRBRESP_PROMISC | \
+    FIF_PROBE_REQ | \
+    FIF_FCSFAIL)
+#else
+#define SUPPORTED_FILTERS \
+    (FIF_ALLMULTI | \
+    FIF_CONTROL | \
+    FIF_PSPOLL | \
+    FIF_OTHER_BSS | \
+    FIF_BCN_PRBRESP_PROMISC | \
+    FIF_PROBE_REQ | \
+    FIF_FCSFAIL)
+#endif
+    static void ssv6200_config_filter(struct ieee80211_hw *hw,
+                                      unsigned int changed_flags,
+                                      unsigned int *total_flags,
+                                      u64 multicast) {
+        changed_flags &= SUPPORTED_FILTERS;
+        *total_flags &= SUPPORTED_FILTERS;
+    }
+    static void ssv6200_bss_info_changed(struct ieee80211_hw *hw,
+                                         struct ieee80211_vif *vif, struct ieee80211_bss_conf *info,
+                                         u32 changed) {
+        struct ssv_vif_priv_data *priv_vif = (struct ssv_vif_priv_data *)vif->drv_priv;
+        struct ssv_softc *sc = hw->priv;
+#ifdef CONFIG_P2P_NOA
+        u8 null_address[6]= {0};
+#endif
+        HCI_WRITE_HW_CONFIG_ON(sc->sh);
+        mutex_lock(&sc->mutex);
+        if (changed & BSS_CHANGED_ERP_PREAMBLE) {
+            dev_dbg(sc->dev, "BSS Changed use_short_preamble[%d]\n", info->use_short_preamble);
+            if (info->use_short_preamble)
+                sc->sc_flags |= SC_OP_SHORT_PREAMBLE;
+            else
+                sc->sc_flags &= ~SC_OP_SHORT_PREAMBLE;
+        }
+        if (changed & BSS_CHANGED_ERP_CTS_PROT) {
+            dev_dbg(sc->dev, "BSS Changed use_cts_prot[%d]\n", info->use_cts_prot);
+            if (info->use_cts_prot)
+                sc->sc_flags |= SC_OP_CTS_PROT;
+            else
+                sc->sc_flags &= ~SC_OP_CTS_PROT;
+        }
+        if (SSV_CHK_IF_SUPPORT_HW_BSSID(sc, priv_vif->vif_idx)) {
+            if (changed & BSS_CHANGED_BSSID) {
+#ifdef CONFIG_P2P_NOA
+                struct ssv_vif_priv_data *vif_priv;
+                vif_priv = (struct ssv_vif_priv_data *)vif->drv_priv;
+#endif
+                SSV_SET_BSSID(sc->sh, (u8*)info->bssid, priv_vif->vif_idx);
+                dev_dbg(sc->dev, "BSS_CHANGED_BSSID: %02x:%02x:%02x:%02x:%02x:%02x\n",
+                       info->bssid[0], info->bssid[1], info->bssid[2],
+                       info->bssid[3], info->bssid[4], info->bssid[5]);
+#ifdef CONFIG_P2P_NOA
+                if(memcmp(info->bssid, null_address, 6))
+                    ssv6xxx_noa_hdl_bss_change(sc, MONITOR_NOA_CONF_ADD, vif_priv->vif_idx);
+                else
+                    ssv6xxx_noa_hdl_bss_change(sc, MONITOR_NOA_CONF_REMOVE, vif_priv->vif_idx);
+#endif
+            }
+            if (changed & BSS_CHANGED_ERP_SLOT) {
+                dev_dbg(sc->dev, "BSS_CHANGED_ERP_SLOT: use_short_slot[%d]\n", info->use_short_slot);
+                SSV_SET_DUR_BURST_SIFS_G(sc->sh, 0xa);
+                if (info->use_short_slot) {
+                    SSV_SET_DUR_SLOT(sc->sh, 0x9);
+                } else {
+                    SSV_SET_DUR_SLOT(sc->sh, 20);
+                }
+            }
+        }
+        if (changed & BSS_CHANGED_HT) {
+            dev_dbg(sc->dev, "BSS_CHANGED_HT: Untreated!!\n");
+        }
+        if (changed & BSS_CHANGED_BASIC_RATES) {
+            dev_dbg(sc->dev, "ssv6xxx_rc_update_basic_rate!!\n");
+            SSV_RC_UPDATE_BASIC_RATE(sc, info->basic_rates);
+        }
+        if (vif->type == NL80211_IFTYPE_STATION) {
+            struct ieee80211_channel *curchan;
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0)
+            curchan = hw->conf.channel;
+#else
+            curchan = hw->conf.chandef.chan;
+#endif
+            dev_dbg(sc->dev, "NL80211_IFTYPE_STATION!!\n");
+            if (changed & BSS_CHANGED_ASSOC) {
+                sc->isAssoc = info->assoc;
+                if(!sc->isAssoc) {
+                    sc->channel_center_freq = 0;
+                    sc->ps_aid = 0;
+#ifdef SSV_SUPPORT_USB_LPM
+                    SSV_SET_USB_LPM(sc, 1);
+#endif
+                } else {
+                    sc->channel_center_freq = curchan->center_freq;
+                    dev_dbg(sc->dev, KERN_INFO "!!info->aid = %d\n",info->aid);
+                    sc->ps_aid = info->aid;
+#ifdef SSV_SUPPORT_USB_LPM
+                    SSV_SET_USB_LPM(sc, 0);
+#endif
+                }
+            }
+            if ((changed & BSS_CHANGED_BEACON_INT) && (info->beacon_int != 0)
+               )
+                SSV_BEACON_LOSS_CONFIG(sc->sh, info->beacon_int, info->bssid);
+        }
+        if (vif->type == NL80211_IFTYPE_AP) {
+            if (changed & ( BSS_CHANGED_BEACON
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,0)
+                            | BSS_CHANGED_SSID
+#endif
+                            | BSS_CHANGED_BSSID
+                            | BSS_CHANGED_BASIC_RATES)) {
+#ifdef BROADCAST_DEBUG
+                dev_dbg(sc->dev, "[A] ssv6200_bss_info_changed:beacon changed\n");
+#endif
+                queue_work(sc->config_wq, &sc->set_tim_work);
+            }
+            if (changed & BSS_CHANGED_BEACON_INT) {
+                dev_dbg(sc->dev, "[A] BSS_CHANGED_BEACON_INT beacon_interval(%d)\n", info->beacon_int);
+                if (sc->beacon_interval != info->beacon_int) {
+                    sc->beacon_interval = info->beacon_int;
+                    SSV_SET_BCN_IFNO(sc->sh, sc->beacon_interval, sc->beacon_dtim_cnt);
+                }
+            }
+            if (changed & BSS_CHANGED_BEACON_ENABLED) {
+                dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_BEACON,
+                         "[A] BSS_CHANGED_BEACON_ENABLED (0x%x)\n", info->enable_beacon);
+                if (0 != SSV_BEACON_ENABLE(sc, info->enable_beacon)) {
+                    dev_err(sc->dev, "Beacon enable %d error.\n", info->enable_beacon);
+                }
+            }
+        }
+        mutex_unlock(&sc->mutex);
+        HCI_WRITE_HW_CONFIG_OFF(sc->sh);
+        dev_dbg(sc->dev, "[I] %s(): leave\n", __FUNCTION__);
+    }
+    static int ssv6200_sta_add(struct ieee80211_hw *hw,
+                               struct ieee80211_vif *vif,
+                               struct ieee80211_sta *sta) {
+        struct ssv_sta_priv_data *sta_priv_dat=NULL;
+        struct ssv_softc *sc=hw->priv;
+        struct ssv_sta_info *sta_info;
+        int s;
+        unsigned long flags;
+        int ret = 0;
+        struct ssv_vif_priv_data *vif_priv = (struct ssv_vif_priv_data *)vif->drv_priv;
+#ifndef SSV_SUPPORT_HAL
+        bool tdls_use_sw_cipher = false, tdls_link= false;
+#endif
+        dev_dbg(sc->dev, "[I] %s(): vif[%d] ", __FUNCTION__, vif_priv->vif_idx);
+        HCI_WRITE_HW_CONFIG_ON(sc->sh);
+        mutex_lock(&sc->mutex);
+        if (sc->force_triger_reset == true) {
+            vif_priv->sta_asleep_mask = 0;
+            do {
+                spin_lock_irqsave(&sc->ps_state_lock, flags);
+                for (s=0; s<SSV_NUM_STA; s++, sta_info++) {
+                    sta_info = &sc->sta_info[s];
+                    if ((sta_info->s_flags & STA_FLAG_VALID)) {
+                        if (sta_info->sta == sta) {
+                            dev_dbg(sc->dev, "search stat %02x:%02x:%02x:%02x:%02x:%02x to  wsid=%d\n",
+                                   sta->addr[0], sta->addr[1], sta->addr[2],
+                                   sta->addr[3], sta->addr[4], sta->addr[5], sta_info->hw_wsid);
+                            spin_unlock_irqrestore(&sc->ps_state_lock, flags);
+                            goto out;
+                        }
+                    }
+                }
+                spin_unlock_irqrestore(&sc->ps_state_lock, flags);
+                if (s >= SSV_NUM_STA) {
+                    break;
+                }
+            } while(0);
+        }
+        do {
+            spin_lock_irqsave(&sc->ps_state_lock, flags);
+#ifdef SSV_SUPPORT_HAL
+            s = HAL_GET_WSID(sc, vif, sta);
+            sta_info = &sc->sta_info[s];
+            sta_priv_dat = (struct ssv_sta_priv_data *)sta->drv_priv;
+#else
+            if ( !list_empty(&vif_priv->sta_list) && vif->type == NL80211_IFTYPE_STATION) {
+                tdls_link = true;
+            }
+            if ((tdls_link) && (vif_priv->pair_cipher != SSV_CIPHER_NONE)
+                && (vif_priv->pair_cipher != SSV_CIPHER_CCMP)
+                && (sc->sh->cfg.use_wpa2_only == false)) {
+                tdls_use_sw_cipher = true;
+            }
+#if 1
+            if (((vif_priv->vif_idx == 0) && (tdls_use_sw_cipher == false))
+                || sc->sh->cfg.use_wpa2_only)
+                s = 0;
+            else
+                s = 2;
+#else
+#endif
+            for (; s < SSV_NUM_STA; s++) {
+                sta_info = &sc->sta_info[s];
+                if ((sta_info->s_flags & STA_FLAG_VALID) == 0) {
+                    sta_info->aid = sta->aid;
+                    sta_info->sta = sta;
+                    sta_info->vif = vif;
+                    sta_info->s_flags = STA_FLAG_VALID;
+                    sta_priv_dat =
+                        (struct ssv_sta_priv_data *)sta->drv_priv;
+                    sta_priv_dat->sta_idx = s;
+                    sta_priv_dat->sta_info = sta_info;
+                    sta_priv_dat->has_hw_encrypt = false;
+                    sta_priv_dat->has_hw_decrypt = false;
+                    sta_priv_dat->need_sw_decrypt = false;
+                    sta_priv_dat->need_sw_encrypt = false;
+                    sta_priv_dat->use_mac80211_decrypt = false;
+#ifdef USE_LOCAL_CRYPTO
+                    if (SSV_NEED_SW_CIPHER(sc->sh)) {
+                        sta_priv_dat->crypto_data.ops = NULL;
+                        sta_priv_dat->crypto_data.priv = NULL;
+#ifdef HAS_CRYPTO_LOCK
+                        rwlock_init(&sta_priv_dat->crypto_data.lock);
+#endif
+                    }
+#endif
+                    if ( (vif_priv->pair_cipher == SSV_CIPHER_WEP40)
+                         || (vif_priv->pair_cipher == SSV_CIPHER_WEP104)) {
+#ifdef USE_LOCAL_CRYPTO
+                        if (vif_priv->crypto_data.ops != NULL) {
+                            sta_priv_dat->crypto_data.ops = vif_priv->crypto_data.ops;
+                            sta_priv_dat->crypto_data.priv = vif_priv->crypto_data.priv;
+                        }
+#endif
+                        sta_priv_dat->has_hw_encrypt = vif_priv->has_hw_encrypt;
+                        sta_priv_dat->has_hw_decrypt = vif_priv->has_hw_decrypt;
+                        sta_priv_dat->need_sw_encrypt = vif_priv->need_sw_encrypt;
+                        sta_priv_dat->need_sw_decrypt = vif_priv->need_sw_decrypt;
+                    }
+                    list_add_tail(&sta_priv_dat->list, &vif_priv->sta_list);
+                    break;
+                }
+            }
+#endif
+            spin_unlock_irqrestore(&sc->ps_state_lock, flags);
+            if (s >= SSV_NUM_STA) {
+                dev_err(sc->dev, "Number of STA exceeds driver limitation %d\n.", SSV_NUM_STA);
+                ret = -1;
+                break;
+            }
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+            ssv6xxx_debugfs_add_sta(sc, sta_info);
+#endif
+            if ( (vif_priv->pair_cipher == SSV_CIPHER_WEP40)
+                 || (vif_priv->pair_cipher == SSV_CIPHER_WEP104)) {
+                vif_priv->wep_idx = -1;
+                vif_priv->wep_cipher = -1;
+            }
+            sta_info->hw_wsid = -1;
+            SSV_SET_HW_WSID(sc, vif, sta, s);
+#ifdef SSV6200_ECO
+            if ((sta_priv_dat->has_hw_encrypt || sta_priv_dat->has_hw_decrypt) &&
+                ((vif_priv->pair_cipher == SSV_CIPHER_WEP40) || (vif_priv->pair_cipher == SSV_CIPHER_WEP104))) {
+#ifdef SSV_SUPPORT_HAL
+                HAL_SET_WEP_HW_CRYPTO_KEY(sc, sta_info, vif_priv);
+#else
+                struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
+                struct ssv6xxx_hw_sec *sramKey = &vif_info->sramKey;
+                _set_wep_hw_crypto_pair_key(sc, vif_info, sta_info, (void*)sramKey);
+                if (sramKey->sta_key[0].pair_key_idx != 0) {
+                    _set_wep_hw_crypto_group_key(sc, vif_info, sta_info, (void*)sramKey);
+                }
+#endif
+            }
+#endif
+            ssv6200_ampdu_tx_add_sta(hw, sta);
+#ifdef FW_WSID_WATCH_LIST
+            SSV_ADD_FW_WSID(sc, vif_priv, sta, sta_info);
+#endif
+            dev_dbg(sc->dev, "Add %02x:%02x:%02x:%02x:%02x:%02x to VIF %d sw_idx=%d, wsid=%d\n",
+                   sta->addr[0], sta->addr[1], sta->addr[2],
+                   sta->addr[3], sta->addr[4], sta->addr[5],
+                   vif_priv->vif_idx,
+                   sta_priv_dat->sta_idx, sta_info->hw_wsid);
+        } while (0);
+out:
+        mutex_unlock(&sc->mutex);
+        HCI_WRITE_HW_CONFIG_OFF(sc->sh);
+        if ((sc->ap_vif == NULL) && (ssvxxx_get_sta_assco_cnt(sc) == 0)
+            && (sc->sh->cfg.greentx & GT_ENABLE)) {
+            sc->gt_channel = sc->hw_chan;
+            sc->gt_enabled = true;
+        } else {
+            sc->dpd.pwr_mode = NORMAL_PWR;
+            sc->green_pwr = 0xff;
+            HAL_UPDATE_RF_PWR(sc);
+            sc->gt_enabled = false;
+        }
+        return ret;
+    }
+    void ssv6200_rx_flow_check(struct ssv_sta_priv_data *sta_priv_dat,
+                               struct ssv_softc *sc) {
+        if (SSV6200_USE_HW_WSID(sta_priv_dat->sta_idx) && (sta_priv_dat->need_sw_decrypt)) {
+            int other_hw_wsid = (sta_priv_dat->sta_idx+ 1) & 1;
+            struct ssv_sta_info *sta_info = &sc->sta_info[other_hw_wsid];
+            struct ieee80211_sta *sta = sta_info->sta;
+            struct ssv_sta_priv_data *sta_priv = (struct ssv_sta_priv_data *) sta->drv_priv;
+            if ((sta_info-> s_flags == 0)
+                || ((sta_info-> s_flags & STA_FLAG_VALID) && (sta_priv->has_hw_decrypt))) {
+#ifdef SSV_SUPPORT_HAL
+#ifdef CONFIG_SSV_HW_ENCRYPT_SW_DECRYPT
+                HAL_SET_RX_FLOW(sc->sh, RX_DATA_FLOW, RX_HCI);
+#else
+                HAL_SET_RX_FLOW(sc->sh, RX_DATA_FLOW, RX_CIPHER_HCI);
+#endif
+#else
+#ifdef CONFIG_SSV_HW_ENCRYPT_SW_DECRYPT
+                SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_DATA, M_ENG_MACRX|(M_ENG_HWHCI<<4));
+#else
+                SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_DATA, M_ENG_MACRX|(M_ENG_ENCRYPT_SEC<<4)|(M_ENG_HWHCI<<8));
+#endif
+#endif
+                dev_dbg(sc->dev, "redirect Rx flow for sta %d  disconnect\n",sta_priv_dat->sta_idx);
+            }
+        }
+    }
+    static int ssv6200_sta_remove(struct ieee80211_hw *hw,
+                                  struct ieee80211_vif *vif,
+                                  struct ieee80211_sta *sta) {
+        struct ssv_sta_priv_data *sta_priv_dat = (struct ssv_sta_priv_data *)sta->drv_priv;
+        struct ssv_softc *sc = hw->priv;
+        struct ssv_sta_info *sta_info = &sc->sta_info[sta_priv_dat->sta_idx];
+        unsigned long flags;
+        u32 bit;
+        struct ssv_vif_priv_data *priv_vif = (struct ssv_vif_priv_data *)vif->drv_priv;
+        u8 hw_wsid = -1;
+        BUG_ON(sta_priv_dat->sta_idx >= SSV_NUM_STA);
+#ifdef CONFIG_SSV_CCI_IMPROVEMENT
+#define RX_11B_CCA_IN_SCAN 0x20300080
+#ifndef SSV_SUPPORT_HAL
+        SMAC_REG_READ(sc->sh, 0xCE01000C, &sc->pre_11b_rx_abbctune);
+        SMAC_REG_READ(sc->sh, ADR_RX_11B_CCA_CONTROL, &sc->pre_11b_cca_control);
+        SMAC_REG_READ(sc->sh, ADR_RX_11B_CCA_1, &sc->pre_11b_cca_1);
+        SMAC_REG_WRITE(sc->sh, 0xCE01000C, (sc->pre_11b_rx_abbctune | (0x3F << 3)));
+        SMAC_REG_WRITE(sc->sh, ADR_RX_11B_CCA_CONTROL, 0x0);
+        SMAC_REG_WRITE(sc->sh, ADR_RX_11B_CCA_1, RX_11B_CCA_IN_SCAN);
+#else
+        sc->cci_current_level = 0;
+        sc->cci_start = false;
+        HAL_UPDATE_SCAN_CCI_SETTING(sc);
+#endif
+#endif
+        HCI_WRITE_HW_CONFIG_ON(sc->sh);
+        dev_notice(sc->dev,
+                   "Removing STA %d (%02X:%02X:%02X:%02X:%02X:%02X) from VIF %d\n.",
+                   sta_priv_dat->sta_idx, sta->addr[0], sta->addr[1], sta->addr[2],
+                   sta->addr[3], sta->addr[4], sta->addr[5], priv_vif->vif_idx);
+#if defined(IRQ_PROC_RX_DATA)
+        local_bh_disable();
+#endif
+        mutex_lock(&sc->mutex);
+        down_write(&sc->sta_info_sem);
+        ssv6200_rx_flow_check(sta_priv_dat, sc);
+        spin_lock_irqsave(&sc->ps_state_lock, flags);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+#endif
+#ifdef USE_LOCAL_CRYPTO
+        if (SSV_NEED_SW_CIPHER(sc->sh)) {
+            INIT_WRITE_CRYPTO_DATA(crypto_data, &sta_priv_dat->crypto_data);
+            START_WRITE_CRYPTO_DATA(crypto_data);
+            if (crypto_data->ops) {
+                if ( (priv_vif->crypto_data.ops != crypto_data->ops)
+                     && crypto_data->priv) {
+                    crypto_data->ops->deinit(crypto_data->priv);
+                    dev_info(sc->dev, "STA releases crypto OK!\n");
+                }
+                crypto_data->priv = NULL;
+                crypto_data->ops = NULL;
+            }
+            END_WRITE_CRYPTO_DATA(crypto_data);
+#ifdef MULTI_THREAD_ENCRYPT
+            _clean_up_crypto_skb(sc, sta);
+#endif
+        }
+#endif
+#if 0
+        if ((sc->ps_status == PWRSV_PREPARE)||(sc->ps_status == PWRSV_ENABLE)) {
+            memset(sta_info, 0, sizeof(*sta_info));
+            sta_priv_dat->sta_idx = -1;
+            list_del(&sta_priv_dat->list);
+            spin_unlock_irqrestore(&sc->ps_state_lock, flags);
+            return 0;
+        }
+#endif
+        bit = BIT(sta_priv_dat->sta_idx);
+        priv_vif->sta_asleep_mask &= ~bit;
+#ifdef SSV_SUPPORT_HAL
+        spin_unlock_irqrestore(&sc->ps_state_lock, flags);
+        HAL_DEL_FW_WSID(sc, sta, sta_info);
+        spin_lock_irqsave(&sc->ps_state_lock, flags);
+        hw_wsid = sta_info->hw_wsid;
+#else
+        if (sta_info->hw_wsid != -1) {
+#ifndef FW_WSID_WATCH_LIST
+            BUG_ON(sta_info->hw_wsid >= SSV_NUM_HW_STA);
+#endif
+            hw_wsid = sta_info->hw_wsid;
+        }
+#ifdef FW_WSID_WATCH_LIST
+        if (sta_info->hw_wsid >= SSV_NUM_HW_STA) {
+            spin_unlock_irqrestore(&sc->ps_state_lock, flags);
+            hw_update_watch_wsid(sc, sta, sta_info, sta_info->hw_wsid, 0, SSV6XXX_WSID_OPS_DEL);
+            spin_lock_irqsave(&sc->ps_state_lock, flags);
+        }
+#endif
+#endif
+#if 0
+        dev_dbg(sc->dev, "%s(): sw_idx=%d, hw_idx=%d sta_asleep_mask[%08x]\n", __FUNCTION__,
+               sta_priv_dat->sta_idx, sta_info->hw_wsid, sc->sta_asleep_mask);
+        dev_dbg(sc->dev, "Remove %02x:%02x:%02x:%02x:%02x:%02x to sw_idx=%d, wsid=%d\n",
+               sta->addr[0], sta->addr[1], sta->addr[2],
+               sta->addr[3], sta->addr[4], sta->addr[5], sta_priv_dat->sta_idx, sta_info->hw_wsid);
+#endif
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+        {
+            spin_unlock_irqrestore(&sc->ps_state_lock, flags);
+            ssv6xxx_debugfs_remove_sta(sc, sta_info);
+            spin_lock_irqsave(&sc->ps_state_lock, flags);
+        }
+#endif
+        memset(sta_info, 0, sizeof(*sta_info));
+        sta_priv_dat->sta_idx = -1;
+        list_del(&sta_priv_dat->list);
+        if (list_empty(&priv_vif->sta_list) && vif->type == NL80211_IFTYPE_STATION) {
+            priv_vif->pair_cipher = 0;
+            priv_vif->group_cipher = 0;
+            sc->ps_aid = 0;
+        }
+        spin_unlock_irqrestore(&sc->ps_state_lock, flags);
+#if 0
+        sta_info = sc->sta_info;
+        for(s=0; s<SSV_NUM_STA; s++, sta_info++) {
+            if (sta_info->s_flags & STA_FLAG_VALID)
+                continue;
+            if (sta_info->sta == sta &&
+                sta_info->vif == vif)
+                sta_info->s_flags = 0;
+        }
+#endif
+        SSV_DEL_HW_WSID(sc, hw_wsid);
+        dev_dbg(sc->dev, "hw wsid %u is removed.\n", hw_wsid);
+        up_write(&sc->sta_info_sem);
+        mutex_unlock(&sc->mutex);
+#if defined(IRQ_PROC_RX_DATA)
+        local_bh_enable();
+#endif
+        HCI_WRITE_HW_CONFIG_OFF(sc->sh);
+        if (sc->gt_enabled) {
+            sc->dpd.pwr_mode = NORMAL_PWR;
+            sc->green_pwr = 0xff;
+            HAL_UPDATE_RF_PWR(sc);
+            sc->gt_enabled = false;
+        }
+        return 0;
+    }
+    static void ssv6200_sta_notify(struct ieee80211_hw *hw,
+                                   struct ieee80211_vif *vif,
+                                   enum sta_notify_cmd cmd,
+                                   struct ieee80211_sta *sta) {
+        struct ssv_softc *sc = hw->priv;
+        struct ssv_vif_priv_data *priv_vif = (struct ssv_vif_priv_data *)vif->drv_priv;
+        struct ssv_sta_priv_data *sta_priv_dat = (struct ssv_sta_priv_data *)sta->drv_priv;
+        u32 bit, prev;
+        unsigned long flags;
+#ifdef BROADCAST_DEBUG
+#endif
+        spin_lock_irqsave(&sc->ps_state_lock, flags);
+        bit = BIT(sta_priv_dat->sta_idx);
+        prev = priv_vif->sta_asleep_mask & bit;
+        switch (cmd) {
+        case STA_NOTIFY_SLEEP:
+            if(!prev) {
+                if ( (vif->type == NL80211_IFTYPE_AP)
+                     && sc->bq4_dtim
+                     && !priv_vif->sta_asleep_mask
+                     && ssv6200_bcast_queue_len(&sc->bcast_txq)) {
+                    dev_dbg(sc->dev, "%s(): ssv6200_bcast_start\n", __FUNCTION__);
+                    ssv6200_bcast_start(sc);
+                }
+                priv_vif->sta_asleep_mask |= bit;
+            }
+            break;
+        case STA_NOTIFY_AWAKE:
+            if(prev) {
+                priv_vif->sta_asleep_mask &= ~bit;
+            }
+            break;
+        default:
+            break;
+        }
+        spin_unlock_irqrestore(&sc->ps_state_lock, flags);
+        return;
+    }
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,2,0)
+    static u64 ssv6200_get_tsf(struct ieee80211_hw *hw)
+#else
+    static u64 ssv6200_get_tsf(struct ieee80211_hw *hw,
+                               struct ieee80211_vif *vif)
+#endif
+    {
+        return 0;
+    }
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,19,0)
+    static void ssv6200_sw_scan_start(struct ieee80211_hw *hw,
+                                      struct ieee80211_vif *vif, const u8 *mac_addr)
+#else
+    static void ssv6200_sw_scan_start(struct ieee80211_hw *hw)
+#endif
+    {
+        struct ssv_softc *sc = hw->priv;
+        u32 dev_type = HCI_DEVICE_TYPE(sc->sh->hci.hci_ctrl);
+#ifdef CONFIG_SSV_CCI_IMPROVEMENT
+#define RX_11B_CCA_IN_SCAN 0x20300080
+#ifndef SSV_SUPPORT_HAL
+        SMAC_REG_READ(sc->sh, 0xCE01000C, &sc->pre_11b_rx_abbctune);
+        SMAC_REG_READ(sc->sh, ADR_RX_11B_CCA_CONTROL, &sc->pre_11b_cca_control);
+        SMAC_REG_READ(sc->sh, ADR_RX_11B_CCA_1, &sc->pre_11b_cca_1);
+        SMAC_REG_WRITE(sc->sh, 0xCE01000C, (sc->pre_11b_rx_abbctune | (0x3F << 3)));
+        SMAC_REG_WRITE(sc->sh, ADR_RX_11B_CCA_CONTROL, 0x0);
+        SMAC_REG_WRITE(sc->sh, ADR_RX_11B_CCA_1, RX_11B_CCA_IN_SCAN);
+#else
+        HAL_UPDATE_SCAN_CCI_SETTING(sc);
+#endif
+#endif
+        SSV_BEACON_LOSS_DISABLE(sc->sh);
+        if (dev_type == SSV_HWIF_INTERFACE_USB)
+            sc->sh->cfg.usb_hw_resource |= USB_HW_RESOURCE_CHK_SCAN;
+        sc->bScanning = true;
+        dev_dbg(sc->dev, "--------------%s(): \n", __FUNCTION__);
+    }
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,19,0)
+    static void ssv6200_sw_scan_complete(struct ieee80211_hw *hw,
+                                         struct ieee80211_vif *vif)
+#else
+    static void ssv6200_sw_scan_complete(struct ieee80211_hw *hw)
+#endif
+    {
+        struct ssv_softc *sc = hw->priv;
+        struct ieee80211_channel *curchan;
+        u32 dev_type = HCI_DEVICE_TYPE(sc->sh->hci.hci_ctrl);
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0)
+        curchan = hw->conf.channel;
+#else
+        curchan = hw->conf.chandef.chan;
+#endif
+#ifdef CONFIG_SSV_CCI_IMPROVEMENT
+#ifndef SSV_SUPPORT_HAL
+        SMAC_REG_WRITE(sc->sh, 0xCE01000C, sc->pre_11b_rx_abbctune);
+        SMAC_REG_WRITE(sc->sh, ADR_RX_11B_CCA_CONTROL, sc->pre_11b_cca_control);
+        SMAC_REG_WRITE(sc->sh, ADR_RX_11B_CCA_1, sc->pre_11b_cca_1);
+#else
+        HAL_RECOVERY_SCAN_CCI_SETTING(sc);
+#endif
+#endif
+        if (sc->isAssoc )
+            SSV_BEACON_LOSS_ENABLE(sc->sh);
+        if (dev_type == SSV_HWIF_INTERFACE_USB)
+            sc->sh->cfg.usb_hw_resource &= (~USB_HW_RESOURCE_CHK_SCAN);
+        sc->bScanning = false;
+        dev_dbg(sc->dev, "==============%s(): \n", __FUNCTION__);
+    }
+    static int ssv6200_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta,
+                               bool set) {
+        struct ssv_softc *sc = hw->priv;
+        struct ssv_sta_info *sta_info = NULL;
+        if (sta) {
+            sta_info = &sc->sta_info[((struct ssv_sta_priv_data *)sta->drv_priv)->sta_idx];
+            if ((sta_info->s_flags & STA_FLAG_VALID) == 0) {
+                dev_dbg(sc->dev, "%s(): sta_info is gone.\n", __func__);
+                goto out;
+            }
+        }
+        if (sta_info && (sta_info->tim_set^set)) {
+#ifdef BROADCAST_DEBUG
+            dev_dbg(sc->dev, "[I] [A] ssv6200_set_tim");
+#endif
+            sta_info->tim_set = set;
+            queue_work(sc->config_wq, &sc->set_tim_work);
+        }
+out:
+        return 0;
+    }
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,2,0)
+    static int ssv6200_conf_tx(struct ieee80211_hw *hw, u16 queue,
+                               const struct ieee80211_tx_queue_params *params)
+#else
+    static int ssv6200_conf_tx(struct ieee80211_hw *hw,
+                               struct ieee80211_vif *vif, u16 queue,
+                               const struct ieee80211_tx_queue_params *params)
+#endif
+    {
+        struct ssv_softc *sc = hw->priv;
+        int ret = 0;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,0)
+        struct ssv_vif_priv_data *priv_vif = (struct ssv_vif_priv_data *)vif->drv_priv;
+        dev_dbg(sc->dev, "[I] sv6200_conf_tx vif[%d] qos[%d] queue[%d] aifsn[%d] cwmin[%d] cwmax[%d] txop[%d] \n",
+               priv_vif->vif_idx,vif->bss_conf.qos, queue, params->aifs, params->cw_min, params->cw_max, params->txop);
+#else
+        dev_dbg(sc->dev, "[I] sv6200_conf_tx queue[%d] aifsn[%d] cwmin[%d] cwmax[%d] txop[%d] \n",
+               queue, params->aifs, params->cw_min, params->cw_max, params->txop);
+#endif
+        HCI_WRITE_HW_CONFIG_ON(sc->sh);
+        if (queue > NL80211_TXQ_Q_BK) {
+            ret = 1;
+            goto out;
+        }
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,0)
+        if ((priv_vif->vif_idx != 0) && (vif->p2p == 0) ) {
+            dev_warn(sc->dev, "WMM setting applicable to primary interface only.\n");
+            ret = 1;
+            goto out;
+        }
+#endif
+        mutex_lock(&sc->mutex);
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,0)
+        SSV_SET_QOS_ENABLE(sc->sh, vif->bss_conf.qos);
+#endif
+#if 0
+        {
+            cw = 0x4;
+            SMAC_REG_WRITE(sc->sh, ADR_TXQ0_MTX_Q_MISC_EN+0x100*hw_txqid, cw);
+            cw = 0x0;
+            SMAC_REG_WRITE(sc->sh, ADR_TXQ0_MTX_Q_BKF_CNT+0x100*hw_txqid, cw);
+        }
+#endif
+        SSV_SET_WMM_PARAM(sc, params, queue);
+        mutex_unlock(&sc->mutex);
+out:
+        HCI_WRITE_HW_CONFIG_OFF(sc->sh);
+        return ret;
+    }
+    static bool ssv6xxx_is_ampdu_rx_sta(struct ssv_softc *sc, struct ieee80211_sta *sta) {
+        struct ssv_sta_info *sta_info;
+        int i = 0;
+        bool find_peer = false;
+        for (i = 0; i < SSV_NUM_STA; i++) {
+            sta_info = &sc->sta_info[i];
+            if ((sta_info->s_flags & STA_FLAG_VALID) && (sta == sta_info->sta)) {
+                if (sta_info->s_flags & STA_FLAG_AMPDU_RX) {
+                    find_peer = true;
+                }
+                break;
+            }
+        }
+        return find_peer;
+    }
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,0,0)
+    static int ssv6200_ampdu_action(struct ieee80211_hw *hw,
+                                    struct ieee80211_vif *vif,
+                                    enum ieee80211_ampdu_mlme_action action,
+                                    struct ieee80211_sta *sta,
+                                    u16 tid, u16 *ssn)
+#elif LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0) && LINUX_VERSION_CODE < KERNEL_VERSION(4,4,0)
+    static int ssv6200_ampdu_action(struct ieee80211_hw *hw,
+                                    struct ieee80211_vif *vif,
+                                    enum ieee80211_ampdu_mlme_action action,
+                                    struct ieee80211_sta *sta,
+                                    u16 tid, u16 *ssn, u8 buf_size)
+#elif LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0) && LINUX_VERSION_CODE < KERNEL_VERSION(4,4,69)
+    static int ssv6200_ampdu_action(struct ieee80211_hw *hw,
+                                    struct ieee80211_vif *vif,
+                                    enum ieee80211_ampdu_mlme_action action,
+                                    struct ieee80211_sta *sta,
+                                    u16 tid, u16 *ssn, u8 buf_size, bool amsdu)
+#else
+    static int ssv6200_ampdu_action(struct ieee80211_hw *hw,
+                                    struct ieee80211_vif *vif,
+                                    struct ieee80211_ampdu_params *params)
+#endif
+    {
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,0,0)
+        u8 buf_size = 32;
+#endif
+        struct ssv_softc *sc = hw->priv;
+        struct ssv_sta_priv_data *sta_priv;
+        struct ssv_sta_info *sta_info;
+        bool find_peer = false;
+        int ret = 0;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,69)
+        struct ieee80211_sta *sta = params->sta;
+        enum ieee80211_ampdu_mlme_action action = params->action;
+        u16 tid = params->tid;
+        u16 *ssn = &(params->ssn);
+        u8 buf_size = params->buf_size;
+#endif
+        if(sta == NULL)
+            return ret;
+#if (!Enable_AMPDU_Rx)
+        if(action == IEEE80211_AMPDU_RX_START || action == IEEE80211_AMPDU_RX_STOP ) {
+            ampdu_db_log("Disable AMPDU_RX for test(1).\n");
+            return -EOPNOTSUPP;
+        }
+#endif
+#if (!Enable_AMPDU_Tx)
+        if(action == IEEE80211_AMPDU_TX_START || action == IEEE80211_AMPDU_TX_STOP || action == IEEE80211_AMPDU_TX_OPERATIONAL ) {
+            ampdu_db_log("Disable AMPDU_TX for test(1).\n");
+            return -EOPNOTSUPP;
+        }
+#endif
+        if((action == IEEE80211_AMPDU_RX_START || action == IEEE80211_AMPDU_RX_STOP ) &&
+           (!(sc->sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_RX))) {
+            ampdu_db_log("Disable AMPDU_RX(2).\n");
+            return -EOPNOTSUPP;
+        }
+        if( ( action == IEEE80211_AMPDU_TX_START
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0)
+              || action == IEEE80211_AMPDU_TX_STOP
+#else
+              || action == IEEE80211_AMPDU_TX_STOP_CONT
+              || action == IEEE80211_AMPDU_TX_STOP_FLUSH
+              || action == IEEE80211_AMPDU_TX_STOP_FLUSH_CONT
+#endif
+              || action == IEEE80211_AMPDU_TX_OPERATIONAL )
+            && (!(sc->sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_TX))) {
+            ampdu_db_log("Disable AMPDU_TX(2).\n");
+            return -EOPNOTSUPP;
+        }
+        mutex_lock(&sc->mutex);
+        if ((sc->sta_info[((struct ssv_sta_priv_data *)sta->drv_priv)->sta_idx].s_flags & STA_FLAG_VALID) == 0) {
+            dev_dbg(sc->dev, KERN_WARNING "%s(): sta_info is gone.\n", __func__);
+            return -ENODATA;
+        }
+        switch (action) {
+        case IEEE80211_AMPDU_RX_START:
+            ret = SSV_AMPDU_RX_START(sc, hw, vif, sta, tid, ssn, buf_size);
+            if (!ret)
+                queue_work(sc->config_wq, &sc->set_ampdu_rx_add_work);
+            break;
+        case IEEE80211_AMPDU_RX_STOP:
+            find_peer = ssv6xxx_is_ampdu_rx_sta(sc, sta);
+            if (!find_peer)
+                break;
+            sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+            sta_info = &sc->sta_info[sta_priv->sta_idx];
+            sta_info->s_flags &= ~(STA_FLAG_AMPDU_RX);
+            sc->rx_ba_session_count--;
+            if (sc->rx_ba_session_count <= 0) {
+                sc->rx_ba_sta = NULL;
+                sc->rx_ba_session_count = 0;
+            }
+            queue_work(sc->config_wq, &sc->set_ampdu_rx_del_work);
+            break;
+        case IEEE80211_AMPDU_TX_START:
+            dev_dbg(sc->dev, KERN_ERR "AMPDU_TX_START %02X:%02X:%02X:%02X:%02X:%02X %d.\n",
+                   sta->addr[0], sta->addr[1], sta->addr[2], sta->addr[3],
+                   sta->addr[4], sta->addr[5], tid);
+            sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+            sta_priv->max_ampdu_size = SSV_AMPDU_SIZE_1_2(sc->sh);
+            ssv6200_ampdu_tx_start(tid, sta, hw, ssn);
+            ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
+            break;
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0)
+        case IEEE80211_AMPDU_TX_STOP:
+#else
+        case IEEE80211_AMPDU_TX_STOP_CONT:
+        case IEEE80211_AMPDU_TX_STOP_FLUSH:
+        case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
+#endif
+            dev_dbg(sc->dev, KERN_ERR "AMPDU_TX_STOP %02X:%02X:%02X:%02X:%02X:%02X %d.\n",
+                   sta->addr[0], sta->addr[1], sta->addr[2], sta->addr[3],
+                   sta->addr[4], sta->addr[5], tid);
+            ssv6200_ampdu_tx_stop(tid, sta, hw);
+            ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
+            break;
+        case IEEE80211_AMPDU_TX_OPERATIONAL:
+            dev_dbg(sc->dev, KERN_ERR "AMPDU_TX_OPERATIONAL %02X:%02X:%02X:%02X:%02X:%02X %d.\n",
+                   sta->addr[0], sta->addr[1], sta->addr[2], sta->addr[3],
+                   sta->addr[4], sta->addr[5], tid);
+            ssv6200_ampdu_tx_operation(tid, sta, hw, buf_size);
+            break;
+        default:
+            ret = -EOPNOTSUPP;
+            break;
+        }
+        mutex_unlock(&sc->mutex);
+        return ret;
+    }
+#ifdef CONFIG_PM
+    int ssv6xxx_suspend (struct ieee80211_hw *hw, struct cfg80211_wowlan *wowlan) {
+        struct ssv_softc *sc = hw->priv;
+        dev_dbg(sc->dev, "ssv6xxx_suspend \n");
+        if (wowlan) {
+            mutex_lock(&sc->mutex);
+            device_init_wakeup(sc->dev, 1);
+            device_set_wakeup_enable(sc->dev, true);
+            mutex_unlock(&sc->mutex);
+        }
+        return 0;
+    }
+    int ssv6xxx_resume (struct ieee80211_hw *hw) {
+        printk(KERN_INFO "ssv6xxx_resume \n");
+        return 0;
+    }
+#endif
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,9,0)
+    void ssv6200_set_default_unicast_key(struct ieee80211_hw *hw,
+                                         struct ieee80211_vif *vif, int idx) {
+        struct ssv_vif_priv_data *vif_priv = (struct ssv_vif_priv_data *)vif->drv_priv;
+        if ((vif_priv->has_hw_encrypt == false) && ((vif_priv->pair_cipher == SSV_CIPHER_WEP40) || (vif_priv->pair_cipher == SSV_CIPHER_WEP104))) {
+            printk(KERN_DEBUG "Update WEP default key index %d for SW encryption\n", idx);
+            vif_priv->wep_idx = idx;
+        }
+    }
+#endif
+    struct ieee80211_ops ssv6200_ops = {
+        .tx = ssv6200_tx,
+        .start = ssv6200_start,
+        .stop = ssv6200_stop,
+        .add_interface = ssv6200_add_interface,
+        .change_interface = ssv6200_change_interface,
+        .remove_interface = ssv6200_remove_interface,
+        .config = ssv6200_config,
+        .configure_filter = ssv6200_config_filter,
+        .bss_info_changed = ssv6200_bss_info_changed,
+        .sta_add = ssv6200_sta_add,
+        .sta_remove = ssv6200_sta_remove,
+        .sta_notify = ssv6200_sta_notify,
+        .set_key = ssv6200_set_key,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,9,0)
+        .set_default_unicast_key = ssv6200_set_default_unicast_key,
+#endif
+        .sw_scan_start = ssv6200_sw_scan_start,
+        .sw_scan_complete = ssv6200_sw_scan_complete,
+        .get_tsf = ssv6200_get_tsf,
+        .set_tim = ssv6200_set_tim,
+        .conf_tx = ssv6200_conf_tx,
+        .ampdu_action = ssv6200_ampdu_action,
+#ifdef CONFIG_PM
+        .suspend = ssv6xxx_suspend,
+        .resume = ssv6xxx_resume,
+#endif
+    };
+#ifdef CONFIG_PM
+#ifndef SSV_SUPPORT_HAL
+    void ssv6xxx_save_clear_trap_reason(struct ssv_softc *sc) {
+        u32 trap0, trap1;
+        SMAC_REG_READ(sc->sh, ADR_REASON_TRAP0, &trap0);
+        SMAC_REG_READ(sc->sh, ADR_REASON_TRAP1, &trap1);
+        SMAC_REG_WRITE(sc->sh, ADR_REASON_TRAP0, 0x00000000);
+        SMAC_REG_WRITE(sc->sh, ADR_REASON_TRAP1, 0x00000000);
+        dev_dbg(sc->dev, "trap0 %08x, trap1 %08x\n", trap0, trap1);
+        sc->trap_data.reason_trap0 = trap0;
+        sc->trap_data.reason_trap1 = trap1;
+    }
+    void ssv6xxx_restore_trap_reason(struct ssv_softc *sc) {
+        SMAC_REG_WRITE(sc->sh, ADR_REASON_TRAP0, sc->trap_data.reason_trap0);
+        SMAC_REG_WRITE(sc->sh, ADR_REASON_TRAP1, sc->trap_data.reason_trap1);
+    }
+    void ssv6xxx_pmu_awake(struct ssv_softc *sc) {
+        SMAC_REG_SET_BITS(sc->sh, ADR_FN1_INT_CTRL_RESET, (1<<24), 0x01000000);
+        mdelay(5);
+        SMAC_REG_SET_BITS(sc->sh, ADR_FN1_INT_CTRL_RESET, (0<<24), 0x01000000);
+    }
+#endif
+    int ssv6xxx_trigger_pmu(struct ssv_softc *sc) {
+        struct sk_buff *skb;
+        struct cfg_host_cmd *host_cmd;
+        int retval = 0;
+        SSV_SAVE_CLEAR_TRAP_REASON(sc);
+        skb = ssv_skb_alloc(sc, HOST_CMD_HDR_LEN+HOST_CMD_DUMMY_LEN);
+        if (!skb) {
+            dev_dbg(sc->dev, "%s(): Fail to alloc cmd buffer.\n", __FUNCTION__);
+            return -1;
+        }
+        skb_put(skb, HOST_CMD_HDR_LEN+HOST_CMD_DUMMY_LEN);
+        host_cmd = (struct cfg_host_cmd *)skb->data;
+        host_cmd->c_type = HOST_CMD;
+        host_cmd->RSVD0 = 0;
+        host_cmd->h_cmd = (u8)SSV6XXX_HOST_CMD_PS;
+        host_cmd->len = HOST_CMD_HDR_LEN+HOST_CMD_DUMMY_LEN;
+        host_cmd->dummy = sc->ps_aid;
+        retval = HCI_SEND_CMD(sc->sh, skb);
+        ssv_skb_free(sc, skb);
+        return retval;
+    }
+    void ssv6xxx_power_sleep(void *param) {
+        struct ssv_softc *sc = (struct ssv_softc *)param;
+        int retval = 0;
+        retval = ssv6xxx_trigger_pmu(sc);
+        if (retval)
+            dev_dbg(sc->dev, "ssv6xxx_trigger_pmu fail!!\n");
+        mutex_lock(&sc->mutex);
+        ieee80211_stop_queues(sc->hw);
+        HCI_STOP(sc->sh);
+        HCI_TXQ_FLUSH(sc->sh, (TXQ_EDCA_0|TXQ_EDCA_1|TXQ_EDCA_2|TXQ_EDCA_3|TXQ_MGMT));
+        mutex_unlock(&sc->mutex);
+        return;
+    }
+    void ssv6xxx_power_awake(void *param) {
+        struct ssv_softc *sc = (struct ssv_softc *)param;
+        SSV_PMU_AWAKE(sc);
+        mutex_lock(&sc->mutex);
+        ieee80211_wake_queues(sc->hw);
+        if (sc->mac80211_dev_started == true)
+            HCI_START(sc->sh);
+        mdelay(1);
+        SSV_RESTORE_TRAP_REASON(sc);
+        mutex_unlock(&sc->mutex);
+        return;
+    }
+#endif
+    void ssv6xxx_enable_usb_acc(void *param, u8 epnum) {
+        struct ssv_softc *sc = (struct ssv_softc *)param;
+        SSV_ENABLE_USB_ACC(sc, epnum);
+        return;
+    }
+    void ssv6xxx_disable_usb_acc(void *param, u8 epnum) {
+        struct ssv_softc *sc = (struct ssv_softc *)param;
+        SSV_DISABLE_USB_ACC(sc, epnum);
+        return;
+    }
+    void ssv6xxx_jump_to_rom(void *param) {
+        struct ssv_softc *sc = (struct ssv_softc *)param;
+        SSV_JUMP_TO_ROM(sc);
+        return;
+    }
+    int ssv6xxx_rx_burstread_size(void *param) {
+        struct ssv_softc *sc = (struct ssv_softc *)param;
+        struct ssv_hw *sh = sc->sh;
+        return sh->rx_burstread_size_type;
+    }
+    int ssv6xxx_peek_next_pkt_len(struct sk_buff *skb, void *param) {
+        struct ssv_softc *sc = (struct ssv_softc *)param;
+        struct ssv_hw *sh = sc->sh;
+        struct hci_rx_aggr_info *rx_aggr_info = NULL;
+        int offset;
+        unsigned char *pdata = NULL;
+        if ((sh->rx_mode == RX_NORMAL_MODE) || (sh->rx_mode == RX_BURSTREAD_MODE))
+            return 0;
+        offset = 0;
+        pdata = skb->data;
+        while (offset < skb->len) {
+            rx_aggr_info = (struct hci_rx_aggr_info *)pdata;
+            if ((rx_aggr_info->jmp_mpdu_len == 0) ||
+                ((offset + rx_aggr_info->jmp_mpdu_len) > skb->len))
+                break;
+            pdata += rx_aggr_info->jmp_mpdu_len;
+            offset += rx_aggr_info->jmp_mpdu_len;
+        }
+        if (offset == skb->len)
+            return 0;
+        else {
+            if (sh->cfg.hw_rx_agg_method_3) {
+                if (rx_aggr_info->jmp_mpdu_len <= (MAX_FRAME_SIZE_DMG + MAX_RX_PKT_RSVD)) {
+                    return rx_aggr_info->jmp_mpdu_len;
+                } else {
+                    dev_dbg(sc->dev, "%s: jmp_mpdu_len %u is too big!\n", __func__, rx_aggr_info->jmp_mpdu_len);
+                    return 0;
+                }
+            } else {
+                if (rx_aggr_info->accu_rx_len <= (MAX_HCI_RX_AGGR_SIZE + MAX_RX_PKT_RSVD)) {
+                    return rx_aggr_info->accu_rx_len;
+                } else {
+                    dev_dbg(sc->dev, "%s: accu_rx_len %u is too big!\n", __func__, rx_aggr_info->accu_rx_len);
+                    return 0;
+                }
+            }
+        }
+    }
+#ifdef USE_LOCAL_CRYPTO
+#ifdef MULTI_THREAD_ENCRYPT
+    struct ssv_crypto_data * ssv6xxx_skb_get_tx_cryptops(struct sk_buff *mpdu) {
+        struct ieee80211_tx_info *info = IEEE80211_SKB_CB(mpdu);
+        struct SKB_info_st *skb_info = (struct SKB_info_st *)mpdu->head;
+        struct ieee80211_sta *sta = skb_info->sta;
+        struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)mpdu->data;
+        u32 unicast = (is_multicast_ether_addr(hdr->addr1))? 0: 1;
+        struct ssv_sta_priv_data *sta_priv_dat = NULL;
+        BUG_ON((size_t)info < (size_t)0x01000);
+        if (unicast) {
+            if (sta) {
+                sta_priv_dat = (struct ssv_sta_priv_data *)sta->drv_priv;
+                return &sta_priv_dat->crypto_data;
+            } else {
+                return NULL;
+            }
+        } else {
+            struct ssv_vif_priv_data *vif_priv = (struct ssv_vif_priv_data *)info->control.vif->drv_priv;
+            return &vif_priv->crypto_data;
+        }
+    }
+    int ssv6xxx_skb_pre_encrypt(struct sk_buff *mpdu, struct ssv_softc *sc) {
+        struct ssv_crypto_data *crypto_data = NULL;
+        struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)mpdu->data;
+        int ret = -1;
+        crypto_data = ssv6xxx_skb_get_tx_cryptops(mpdu);
+        if (crypto_data == NULL)
+            return -EOPNOTSUPP;
+        START_READ_CRYPTO_DATA(crypto_data);
+        if ((crypto_data->ops != NULL) && (crypto_data->ops->encrypt_prepare != NULL)) {
+            u32 hdrlen = ieee80211_hdrlen(hdr->frame_control);
+            ret = crypto_data->ops->encrypt_prepare(mpdu, hdrlen, crypto_data->priv);
+        } else {
+            ret = -EOPNOTSUPP;
+        }
+        END_READ_CRYPTO_DATA(crypto_data);
+        return ret;
+    }
+    int ssv6xxx_skb_pre_decrypt(struct sk_buff *mpdu, struct ieee80211_sta *sta, struct ssv_softc *sc) {
+        struct ssv_crypto_data *crypto_data = NULL;
+        struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)mpdu->data;
+        int ret = -1;
+        crypto_data = ssv6xxx_skb_get_rx_cryptops(sc, sta, mpdu);
+        if (crypto_data == NULL)
+            return -EOPNOTSUPP;
+        START_READ_CRYPTO_DATA(crypto_data);
+        if ((crypto_data->ops != NULL) && (crypto_data->ops->decrypt_prepare != NULL)) {
+            u32 hdrlen = ieee80211_hdrlen(hdr->frame_control);
+            ret = crypto_data->ops->decrypt_prepare(mpdu, hdrlen, crypto_data->priv);
+        } else {
+            ret = -EOPNOTSUPP;
+        }
+        END_READ_CRYPTO_DATA(crypto_data);
+        return ret;
+    }
+#endif
+    int ssv6xxx_skb_encrypt(struct sk_buff *mpdu, struct ssv_softc *sc) {
+        struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)mpdu->data;
+        int ret = 0;
+#ifndef MULTI_THREAD_ENCRYPT
+        struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(mpdu);
+        struct SKB_info_st *skb_info = (struct SKB_info_st *)mpdu->head;
+        struct ieee80211_sta *sta = skb_info->sta;
+        struct ssv_sta_priv_data *sta_priv_dat = NULL;
+        u32 unicast = (is_multicast_ether_addr(hdr->addr1))? 0: 1;
+#endif
+        struct ssv_crypto_data *crypto_data = NULL;
+#ifndef MULTI_THREAD_ENCRYPT
+        if (sta || unicast) {
+            sta_priv_dat = (struct ssv_sta_priv_data *)sta->drv_priv;
+            crypto_data = &sta_priv_dat->crypto_data;
+        } else {
+            struct ssv_vif_priv_data *vif_priv = (struct ssv_vif_priv_data *)tx_info->control.vif->drv_priv;
+            crypto_data = &vif_priv->crypto_data;
+        }
+#else
+        crypto_data = ssv6xxx_skb_get_tx_cryptops(mpdu);
+#endif
+        START_READ_CRYPTO_DATA(crypto_data);
+        if ((crypto_data == NULL) || (crypto_data->ops == NULL) || (crypto_data->priv == NULL)) {
+#if 0
+            u32 unicast = (is_multicast_ether_addr(hdr->addr1))? 0: 1;
+            dev_err(sc->dev, "[Local Crypto]: Encrypt %c %d %02X:%02X:%02X:%02X:%02X:%02X with NULL crypto.\n",
+                    unicast ? 'U' : 'B', mpdu->protocol,
+                    hdr->addr1[0], hdr->addr1[1], hdr->addr1[2],
+                    hdr->addr1[3], hdr->addr1[4], hdr->addr1[5]);
+#endif
+            ret = -1;
+        } else {
+            u32 hdrlen = ieee80211_hdrlen(hdr->frame_control);
+            ret = crypto_data->ops->encrypt_mpdu(mpdu, hdrlen, crypto_data->priv);
+        }
+        END_READ_CRYPTO_DATA(crypto_data);
+        return ret;
+    }
+    struct ssv_crypto_data *ssv6xxx_skb_get_rx_cryptops(struct ssv_softc *sc, struct ieee80211_sta *sta, struct sk_buff *mpdu) {
+        struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)mpdu->data;
+        struct ssv_sta_priv_data *sta_priv;
+        struct ssv_vif_priv_data *vif_priv;
+        struct ssv_vif_info *vif_info;
+        u32 unicast = 0;
+        if(sta == NULL) {
+            dev_dbg(sc->dev, "No sta, fail to get rx cryptops\n");
+            return NULL;
+        }
+        sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+#ifndef IRQ_PROC_RX_DATA
+        down_read(&sc->sta_info_sem);
+#else
+        while(!down_read_trylock(&sc->sta_info_sem));
+#endif
+        if ((sc->sta_info[sta_priv->sta_idx].s_flags & STA_FLAG_VALID) == 0) {
+            up_read(&sc->sta_info_sem);
+            dev_dbg(sc->dev, "%s(): sta_info is gone.\n", __func__);
+            return NULL;
+        }
+        vif_priv = (struct ssv_vif_priv_data *)sc->sta_info[sta_priv->sta_idx].vif->drv_priv;
+        vif_info = &sc->vif_info[vif_priv->vif_idx];
+        if (vif_info->if_type == NL80211_IFTYPE_STATION)
+            unicast = (is_multicast_ether_addr(hdr->addr1))?0:1;
+        if((sta->drv_priv != NULL) && (vif_info->if_type == NL80211_IFTYPE_AP)) {
+            up_read(&sc->sta_info_sem);
+            return &sta_priv->crypto_data;
+        } else if((sta->drv_priv != NULL) && (unicast == 1)) {
+            up_read(&sc->sta_info_sem);
+            return &sta_priv->crypto_data;
+        } else if((unicast != 1) && (vif_priv != NULL)) {
+            up_read(&sc->sta_info_sem);
+            return &vif_priv->crypto_data;
+        } else {
+            up_read(&sc->sta_info_sem);
+            dev_dbg(sc->dev, "[Local Crypto]: No useful drv_priv, sta = %p, unicast = %d, vif_priv = %p", sta, unicast, vif_priv);
+            if(sta != NULL)
+                dev_dbg(sc->dev, ", sta_priv = %p", sta->drv_priv);
+            dev_dbg(sc->dev, "\n");
+        }
+        return NULL;
+    }
+    int ssv6xxx_skb_decrypt(struct sk_buff *mpdu, struct ieee80211_sta *sta, struct ssv_softc *sc) {
+        struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)mpdu->data;
+        struct ssv_crypto_data *crypto_data = NULL;
+        u32 hdrlen = ieee80211_hdrlen(hdr->frame_control);
+        crypto_data = ssv6xxx_skb_get_rx_cryptops(sc, sta, mpdu);
+        if (crypto_data != NULL) {
+            int ret = -1;
+            START_READ_CRYPTO_DATA(crypto_data);
+            if ((crypto_data->ops != NULL) && (crypto_data->priv != NULL))
+                ret = crypto_data->ops->decrypt_mpdu(mpdu, hdrlen, crypto_data->priv);
+            END_READ_CRYPTO_DATA(crypto_data);
+            return ret;
+        }
+        dev_dbg(sc->dev, "[Local Crypto]: crytp is null\n");
+        return -1;
+    }
+#endif
+    int ssv6200_tx_flow_control(void *dev, int hw_txqid, bool fc_en,int debug) {
+        struct ssv_softc *sc=dev;
+        int ac;
+        BUG_ON(hw_txqid > 4);
+        if (hw_txqid == 4)
+            return 0;
+        ac = sc->tx.ac_txqid[hw_txqid];
+        if (fc_en == false) {
+            if (sc->tx.flow_ctrl_status & (1<<ac)) {
+                ieee80211_wake_queue(sc->hw, ac);
+                sc->tx.flow_ctrl_status &= ~(1<<ac);
+            } else {
+            }
+        } else {
+            if ((sc->tx.flow_ctrl_status & (1<<ac))==0) {
+                ieee80211_stop_queue(sc->hw, ac);
+                sc->tx.flow_ctrl_status |= (1<<ac);
+            } else {
+            }
+        }
+        return 0;
+    }
+    void ssv6xxx_tx_q_empty_cb (u32 txq_no, void *cb_data) {
+        struct ssv_softc *sc = cb_data;
+        BUG_ON(sc == NULL);
+        sc->tx_q_empty = true;
+        smp_mb();
+        wake_up_interruptible(&sc->tx_wait_q);
+    }
+#ifndef SSV_SUPPORT_HAL
+#ifdef CONFIG_SSV_CCI_IMPROVEMENT
+    struct ssv6xxx_b_cca_control adjust_cci[] = {
+        {0, 43, 0x00162000, 0x20400080},
+        {40, 48, 0x00161000, 0x20400080},
+        {45, 53, 0x00160800, 0x20400080},
+        {50, 63, 0x00160400, 0x20400080},
+        {60, 68, 0x00160200, 0x20400080},
+        {65, 73, 0x00160100, 0x20400080},
+        {70, 128, 0x00000000, 0x20300080},
+    };
+#define MAX_CCI_LEVEL 128
+    void mitigate_cci(struct ssv_softc *sc, struct ssv_sta_priv_data *sta_priv, u32 input_level) {
+        s32 i;
+        struct ssv_vif_priv_data *vif_priv = NULL;
+        struct ieee80211_vif *vif = NULL;
+        if (time_after(jiffies, sc->cci_last_jiffies + msecs_to_jiffies(3000))) {
+            if (input_level > MAX_CCI_LEVEL) {
+                dev_dbg(sc->dev, "mitigate_cci input error[%d]!!\n",input_level);
+                return;
+            }
+#ifndef IRQ_PROC_RX_DATA
+            down_read(&sc->sta_info_sem);
+#else
+            while(!down_read_trylock(&sc->sta_info_sem));
+#endif
+            if ((sta_priv->sta_info->s_flags & STA_FLAG_VALID) == 0) {
+                up_read(&sc->sta_info_sem);
+                dev_dbg(sc->dev, "%s(): sta_info is gone.\n", __func__);
+                return;
+            }
+            sc->cci_last_jiffies = jiffies;
+            vif = sta_priv->sta_info->vif;
+            vif_priv = (struct ssv_vif_priv_data *)vif->drv_priv;
+            if (vif_priv->vif_idx) {
+                up_read(&sc->sta_info_sem);
+                dev_dbg(sc->dev, "Interface skip CCI[%d]!!\n",vif_priv->vif_idx);
+                return;
+            }
+            if (vif->p2p == true) {
+                up_read(&sc->sta_info_sem);
+                dev_dbg(sc->dev, "Interface skip CCI by P2P!!\n");
+                return;
+            }
+            up_read(&sc->sta_info_sem);
+            if (sc->cci_current_level == 0) {
+                sc->cci_current_level = MAX_CCI_LEVEL;
+                sc->cci_current_gate = (sizeof(adjust_cci)/sizeof(adjust_cci[0])) - 1;
+            }
+#ifdef DEBUG_MITIGATE_CCI
+            dev_dbg(sc->dev, "jiffies=%lu, input_level=%d\n", jiffies, input_level);
+#endif
+            if(( input_level >= adjust_cci[sc->cci_current_gate].down_level) && (input_level <= adjust_cci[sc->cci_current_gate].upper_level)) {
+                sc->cci_current_level = input_level;
+#ifdef DEBUG_MITIGATE_CCI
+                dev_dbg(sc->dev, "Keep the 0xce0020a0[%x] 0xce002008[%x]!!\n"
+                       ,adjust_cci[sc->cci_current_gate].adjust_cca_control,adjust_cci[sc->cci_current_gate].adjust_cca_1);
+#endif
+            } else {
+                if(sc->cci_current_level < input_level) {
+                    for (i = 0; i < sizeof(adjust_cci)/sizeof(adjust_cci[0]); i++) {
+                        if (input_level <= adjust_cci[i].upper_level) {
+#ifdef DEBUG_MITIGATE_CCI
+                            dev_dbg(sc->dev, "gate=%d, input_level=%d, adjust_cci[%d].upper_level=%d, value=%08x\n",
+                                   sc->cci_current_gate, input_level, i, adjust_cci[i].upper_level, adjust_cci[i].adjust_cca_control);
+#endif
+                            sc->cci_current_level = input_level;
+                            sc->cci_current_gate = i;
+                            SMAC_REG_WRITE(sc->sh, ADR_RX_11B_CCA_CONTROL, adjust_cci[i].adjust_cca_control);
+                            SMAC_REG_WRITE(sc->sh, ADR_RX_11B_CCA_1, adjust_cci[i].adjust_cca_1);
+#ifdef DEBUG_MITIGATE_CCI
+                            dev_dbg(sc->dev, "##Set to the 0xce0020a0[%x] 0xce002008[%x]##!!\n"
+                                   ,adjust_cci[sc->cci_current_gate].adjust_cca_control,adjust_cci[sc->cci_current_gate].adjust_cca_1);
+#endif
+                            return;
+                        }
+                    }
+                } else {
+                    for (i = (sizeof(adjust_cci)/sizeof(adjust_cci[0]) -1); i >= 0; i--) {
+                        if (input_level >= adjust_cci[i].down_level) {
+#ifdef DEBUG_MITIGATE_CCI
+                            dev_dbg(sc->dev, "gate=%d, input_level=%d, adjust_cci[%d].down_level=%d, value=%08x\n",
+                                   sc->cci_current_gate, input_level, i, adjust_cci[i].down_level, adjust_cci[i].adjust_cca_control);
+#endif
+                            sc->cci_current_level = input_level;
+                            sc->cci_current_gate = i;
+                            SMAC_REG_WRITE(sc->sh, ADR_RX_11B_CCA_CONTROL, adjust_cci[i].adjust_cca_control);
+                            SMAC_REG_WRITE(sc->sh, ADR_RX_11B_CCA_1, adjust_cci[i].adjust_cca_1);
+#ifdef DEBUG_MITIGATE_CCI
+                            dev_dbg(sc->dev, "##Set to the 0xce0020a0[%x] 0xce002008[%x]##!!\n"
+                                   ,adjust_cci[sc->cci_current_gate].adjust_cca_control,adjust_cci[sc->cci_current_gate].adjust_cca_1);
+#endif
+                            return;
+                        }
+                    }
+                }
+            }
+        }
+    }
+#endif
+#endif
+
+    static u64 ssv6200_get_systime_us(void) {
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39))
+        struct timespec ts;
+        get_monotonic_boottime(&ts);
+        return ((u64)ts.tv_sec * 1000000) + ts.tv_nsec / 1000;
+#else
+        struct timeval tv;
+        do_gettimeofday(&tv);
+        return ((u64)tv.tv_sec * 1000000) + tv.tv_usec;
+#endif
+    }
+
+    static void _proc_data_rx_skb (struct ssv_softc *sc, struct sk_buff *rx_skb) {
+        struct ieee80211_rx_status *rxs;
+        struct ieee80211_hdr *hdr;
+        __le16 fc;
+#ifndef SSV_SUPPORT_HAL
+        struct ssv6200_rx_desc *rxdesc;
+        struct ssv6200_rxphy_info_padding *rxphypad;
+        struct ssv6200_rxphy_info *rxphy;
+        u8 rpci;
+#endif
+        struct ieee80211_channel *chan;
+        struct ieee80211_vif *vif = NULL;
+        struct ieee80211_sta *sta = NULL;
+        bool rx_hw_dec = false;
+        bool do_sw_dec = false;
+        struct ssv_sta_priv_data *sta_priv = NULL;
+        struct ssv_vif_priv_data *vif_priv = NULL;
+        SKB_info *skb_info = NULL;
+        u32 wsid, rate_idx, mng_used;
+        bool aggr;
+        int sec_err = 0;
+        bool mic_err = false, decode_err = false;
+#ifdef CONFIG_SSV_SMARTLINK
+        {
+            void smartlink_nl_send_msg(struct sk_buff *skb);
+            if (sc->ssv_smartlink_status) {
+#ifdef SSV_SUPPORT_HAL
+                skb_pull(rx_skb, HAL_GET_RX_DESC_SIZE(sc->sh));
+#else
+                skb_pull(rx_skb, sc->sh->rx_desc_len);
+#endif
+                skb_trim(rx_skb, rx_skb->len-sc->sh->rx_pinfo_pad);
+                smartlink_nl_send_msg(rx_skb);
+                goto drop_rx;
+            }
+        }
+#endif
+#ifdef SSV_SUPPORT_HAL
+        hdr = (struct ieee80211_hdr *)(rx_skb->data + HAL_GET_RX_DESC_SIZE(sc->sh));
+        wsid = HAL_GET_RX_DESC_WSID(sc->sh, rx_skb);
+        rate_idx= HAL_GET_RX_DESC_RATE_IDX(sc->sh, rx_skb);
+        aggr = HAL_IS_RX_AGGR(sc->sh, rx_skb);
+        mng_used = HAL_GET_RX_DESC_MNG_USED(sc->sh, rx_skb);
+#else
+        rxdesc = (struct ssv6200_rx_desc *)rx_skb->data;
+        rxphy = (struct ssv6200_rxphy_info *)(rx_skb->data + sizeof(*rxdesc));
+        rxphypad = (struct ssv6200_rxphy_info_padding *)(rx_skb->data + rx_skb->len - sizeof(struct ssv6200_rxphy_info_padding));
+        hdr = (struct ieee80211_hdr *)(rx_skb->data + sc->sh->rx_desc_len);
+        wsid = rxdesc->wsid;
+        rate_idx = rxdesc->rate_idx;
+        mng_used = rxdesc->mng_used;
+        aggr = rxphy->aggregate;
+#endif
+        fc = hdr->frame_control;
+        skb_info = (SKB_info *)rx_skb->head;
+
+        if(ieee80211_is_beacon(hdr->frame_control)) {
+            struct ieee80211_mgmt *mgmt_tmp = NULL;
+#ifdef 	SSV_SUPPORT_HAL
+            mgmt_tmp = (struct ieee80211_mgmt *)(rx_skb->data +  HAL_GET_RX_DESC_SIZE(sc->sh));
+#else
+            mgmt_tmp = (struct ieee80211_mgmt *)(rx_skb->data + SSV6XXX_RX_DESC_LEN );
+#endif
+            mgmt_tmp->u.beacon.timestamp = cpu_to_le64(ssv6200_get_systime_us()+ 10*1000*1000);
+            //dev_dbg(sc->dev, "beacon timestamp = %lld\n", mgmt_tmp->u.beacon.timestamp);
+        }
+
+        if(ieee80211_is_probe_resp(hdr->frame_control)) {
+            struct ieee80211_mgmt *mgmt_tmp = NULL;
+
+#ifdef 	SSV_SUPPORT_HAL
+            mgmt_tmp = (struct ieee80211_mgmt *)(rx_skb->data +  HAL_GET_RX_DESC_SIZE(sc->sh));
+#else
+            mgmt_tmp = (struct ieee80211_mgmt *)(rx_skb->data + SSV6XXX_RX_DESC_LEN );
+#endif
+            mgmt_tmp->u.probe_resp.timestamp = cpu_to_le64(ssv6200_get_systime_us()+ 10*1000*1000) ;
+            //dev_dbg(sc->dev, "probe_resp timestamp = %lld\n", mgmt_tmp->u.probe_resp.timestamp);
+        }
+
+
+#ifdef SSV_SUPPORT_HAL
+        HAL_RC_RX_DATA_HANDLER(sc, rx_skb, rate_idx);
+#else
+        if (wsid >= SSV_RC_MAX_HARDWARE_SUPPORT) {
+            if ( (ieee80211_is_data(hdr->frame_control))
+                 && (!(ieee80211_is_nullfunc(hdr->frame_control)))) {
+                ssv6xxx_rc_rx_data_handler(sc->hw, rx_skb, rate_idx);
+            }
+        }
+#endif
+        rxs = IEEE80211_SKB_RXCB(rx_skb);
+        memset(rxs, 0, sizeof(struct ieee80211_rx_status));
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0)
+        rxs->mactime = *((u32 *)&rx_skb->data[28]);
+#endif
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0)
+        chan = sc->hw->conf.channel;
+#else
+        chan = sc->hw->conf.chandef.chan;
+#endif
+        rxs->band = chan->band;
+        rxs->freq = chan->center_freq;
+        rxs->antenna = 1;
+        SSV_RC_MAC80211_RATE_IDX(sc, rate_idx, rxs);
+        sta = ssv6xxx_find_sta_by_rx_skb(sc, rx_skb);
+        if (sta) {
+            struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(rx_skb->data + sc->sh->rx_desc_len);
+            if (ieee80211_is_data(hdr->frame_control)) {
+                sc->rx_data_exist = true;
+            }
+        }
+#ifdef SSV_SUPPORT_HAL
+        HAL_UPDATE_RXSTATUS(sc, rx_skb, rxs);
+#else
+        if ((rate_idx < SSV62XX_G_RATE_INDEX && rxphypad->RSVD == 0) ||
+            (rate_idx >= SSV62XX_G_RATE_INDEX && rxphy->service == 0)) {
+            if (rxdesc->rate_idx < SSV62XX_G_RATE_INDEX)
+                rpci = rxphypad->rpci;
+            else
+                rpci = rxphy->rpci;
+            if((ieee80211_is_beacon(hdr->frame_control))||(ieee80211_is_probe_resp(hdr->frame_control))) {
+                sta = ssv6xxx_find_sta_by_rx_skb(sc, rx_skb);
+                if(sta) {
+                    sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+#ifdef SSV_RSSI_DEBUG
+                    dev_dbg(sc->dev, KERN_DEBUG "b_beacon %02X:%02X:%02X:%02X:%02X:%02X rssi=%d, snr=%d\n",
+                           hdr->addr2[0], hdr->addr2[1],hdr->addr2[2], hdr->addr2[3],
+                           hdr->addr2[4], hdr->addr2[5],rpci, rxphypad->snr);
+#endif
+                    if(sta_priv->beacon_rssi) {
+                        sta_priv->beacon_rssi = ((rpci<< RSSI_DECIMAL_POINT_SHIFT)
+                                                 + ((sta_priv->beacon_rssi<<RSSI_SMOOTHING_SHIFT) - sta_priv->beacon_rssi)) >> RSSI_SMOOTHING_SHIFT;
+                        rpci = (sta_priv->beacon_rssi >> RSSI_DECIMAL_POINT_SHIFT);
+                    } else
+                        sta_priv->beacon_rssi = (rpci<< RSSI_DECIMAL_POINT_SHIFT);
+#ifdef SSV_RSSI_DEBUG
+                    dev_dbg(sc->dev, "Beacon smoothing RSSI %d\n",rpci);
+#endif
+#ifdef CONFIG_SSV_CCI_IMPROVEMENT
+                    mitigate_cci(sc, sta_priv, rxphypad->rpci);
+#endif
+                }
+                if ( sc->sh->cfg.beacon_rssi_minimal ) {
+                    if ( rpci > sc->sh->cfg.beacon_rssi_minimal )
+                        rpci = sc->sh->cfg.beacon_rssi_minimal;
+                }
+#if 0
+                dev_dbg(sc->dev, "beacon %02X:%02X:%02X:%02X:%02X:%02X rxphypad-rpci=%d RxResult=%x wsid=%x\n",
+                       hdr->addr2[0], hdr->addr2[1], hdr->addr2[2],
+                       hdr->addr2[3], hdr->addr2[4], hdr->addr2[5], rpci, rxdesc->RxResult, rxdesc->wsid);
+#endif
+            }
+            rxs->signal = (-rpci);
+        } else {
+#ifdef SSV_RSSI_DEBUG
+            dev_dbg(sc->dev, "########unicast: %d, b_rssi/snr: %d/%d, gn_rssi/snr: %d/%d, rate:%d###############\n",
+                   rxdesc->unicast, (-rxphy->rpci), rxphy->snr, (-rxphypad->rpci), rxphypad->snr, rxdesc->rate_idx);
+            dev_dbg(sc->dev, "RSSI, %d, rate_idx, %d\n", rxs->signal, rxdesc->rate_idx);
+            dev_dbg(sc->dev, "rxdesc->RxResult = %x,rxdesc->wsid = %d\n",rxdesc->RxResult,rxdesc->wsid);
+#endif
+            sta = ssv6xxx_find_sta_by_rx_skb(sc, rx_skb);
+            if(sta) {
+                sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+                rxs->signal = -(sta_priv->beacon_rssi >> RSSI_DECIMAL_POINT_SHIFT);
+            }
+#ifdef SSV_RSSI_DEBUG
+            dev_dbg(sc->dev, "Others signal %d\n",rxs->signal);
+#endif
+        }
+#endif
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0)
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0)
+        rxs->flag |= RX_FLAG_MACTIME_MPDU;
+#else
+        //rxs->flag |= RX_FLAG_MACTIME_START;
+#endif
+        rxs->rx_flags = 0;
+#endif
+#if LINUX_VERSION_CODE >= 0x030400
+        if (aggr)
+            rxs->flag |= RX_FLAG_NO_SIGNAL_VAL;
+#endif
+        sc->hw_mng_used = mng_used;
+        if ( (ieee80211_is_data(fc) || ieee80211_is_data_qos(fc))
+             && ieee80211_has_protected(fc)) {
+            sta = ssv6xxx_find_sta_by_rx_skb(sc, rx_skb);
+            if (sta == NULL)
+                goto drop_rx;
+            sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+#ifndef IRQ_PROC_RX_DATA
+            down_read(&sc->sta_info_sem);
+#else
+            while(!down_read_trylock(&sc->sta_info_sem));
+#endif
+            if ((sc->sta_info[sta_priv->sta_idx].s_flags & STA_FLAG_VALID) == 0) {
+                up_read(&sc->sta_info_sem);
+                goto drop_rx;
+            }
+            vif = sc->sta_info[sta_priv->sta_idx].vif;
+            if (vif == NULL) {
+                up_read(&sc->sta_info_sem);
+                goto drop_rx;
+            }
+            if (is_broadcast_ether_addr(hdr->addr1)) {
+                vif_priv = (struct ssv_vif_priv_data *)vif->drv_priv;
+                rx_hw_dec = vif_priv->has_hw_decrypt;
+                do_sw_dec = vif_priv->need_sw_decrypt;
+            } else {
+                rx_hw_dec = sta_priv->has_hw_decrypt;
+                do_sw_dec = sta_priv->need_sw_decrypt;
+            }
+            up_read(&sc->sta_info_sem);
+#if 0
+            if (rx_count++ < 20) {
+                dev_dbg(sc->dev, KERN_ERR "HW DEC (%d - %d) %d %02X:%02X:%02X:%02X:%02X:%02X\n",
+                       rx_hw_dec, do_sw_dec, rxdesc->wsid,
+                       hdr->addr1[0], hdr->addr1[1], hdr->addr1[2],
+                       hdr->addr1[3], hdr->addr1[4], hdr->addr1[5]);
+                _ssv6xxx_hexdump("M ", (const u8 *)rx_skb->data, (rx_skb->len > 128) ? 128 : rx_skb->len);
+            }
+#endif
+#if 0
+            dev_err(sc->dev, "R %02X:%02X:%02X:%02X:%02X:%02X %d %d\n",
+                    hdr->addr2[0], hdr->addr2[1], hdr->addr2[2],
+                    hdr->addr2[3], hdr->addr2[4], hdr->addr2[5],
+                    rx_hw_dec, do_sw_dec);
+            _ssv6xxx_hexdump("R ", (const u8 *)rx_skb->data,
+                             (rx_skb->len > 128) ? 128 : rx_skb->len);
+#endif
+        }
+        if (sc->dbg_rx_frame) {
+            _ssv6xxx_hexdump("================================================================\n"
+                             "RX frame", (const u8 *)rx_skb->data, rx_skb->len);
+        }
+        sec_err = SSV_GET_SEC_DECODE_ERR(sc->sh, rx_skb, &mic_err, &decode_err);
+        skb_pull(rx_skb, sc->sh->rx_desc_len);
+        skb_trim(rx_skb, rx_skb->len - sc->sh->rx_pinfo_pad);
+#ifdef CONFIG_P2P_NOA
+        if(ieee80211_is_beacon(hdr->frame_control))
+            ssv6xxx_noa_detect(sc, hdr, rx_skb->len);
+#endif
+#ifdef USE_LOCAL_CRYPTO
+        if ((rx_hw_dec == false) && (do_sw_dec == true)) {
+            int ret = 0;
+#ifdef MULTI_THREAD_ENCRYPT
+            struct ssv_encrypt_task_list *ta = NULL;
+            unsigned long flags;
+#endif
+#ifndef MULTI_THREAD_ENCRYPT
+            ret = ssv6xxx_skb_decrypt(rx_skb, sta, sc);
+            if (ret < 0) {
+                dev_err(sc->dev, "[Local Crypto]: Fail to decrypt local: %02X:%02X:%02X:%02X:%02X:%02X, ret = %d.\n",
+                        hdr->addr2[0], hdr->addr2[1], hdr->addr2[2],
+                        hdr->addr2[3], hdr->addr2[4], hdr->addr2[5], ret);
+                goto drop_rx;
+            }
+#else
+            skb_info->sta = sta;
+            ret = ssv6xxx_skb_pre_decrypt(rx_skb, sta, sc);
+            if (ret == 0) {
+                skb_info->crypt_st = PKT_CRYPT_ST_DEC_PRE;
+                spin_lock_irqsave(&sc->crypt_st_lock, flags);
+                __skb_queue_tail(&sc->preprocess_q, rx_skb);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+                if (sc->max_preprocess_q_len < skb_queue_len(&sc->preprocess_q))
+                    sc->max_preprocess_q_len = skb_queue_len(&sc->preprocess_q);
+#endif
+                spin_unlock_irqrestore(&sc->crypt_st_lock, flags);
+                list_for_each_entry_reverse(ta, &sc->encrypt_task_head, list) {
+                    if ((cpu_online(ta->cpu_no)) && (ta->running == 0)) {
+                        wake_up(&ta->encrypt_wait_q);
+                        return;
+                    }
+                }
+                return;
+            } else if (ret ==(-EOPNOTSUPP)) {
+                ret = ssv6xxx_skb_decrypt(rx_skb, sta, sc);
+                if (ret < 0) {
+                    dev_err(sc->dev, "[Local Crypto]: Fail to decrypt local: %02X:%02X:%02X:%02X:%02X:%02X, ret = %d.\n",
+                            hdr->addr2[0], hdr->addr2[1], hdr->addr2[2],
+                            hdr->addr2[3], hdr->addr2[4], hdr->addr2[5], ret);
+                    goto drop_rx;
+                }
+            } else {
+                dev_dbg(sc->dev, "[MT-CRYPTO]: Failed to do pre-decrypt (%d)\n", ret);
+                dev_kfree_skb_any(rx_skb);
+                return;
+            }
+#endif
+        }
+#endif
+        if (rx_hw_dec || do_sw_dec) {
+            hdr = (struct ieee80211_hdr *)rx_skb->data;
+            rxs = IEEE80211_SKB_RXCB(rx_skb);
+            hdr->frame_control = hdr->frame_control & ~(cpu_to_le16(IEEE80211_FCTL_PROTECTED));
+            rxs->flag |= (RX_FLAG_DECRYPTED|RX_FLAG_IV_STRIPPED);
+            if (sec_err) {
+                vif_priv = (struct ssv_vif_priv_data *)vif->drv_priv;
+                if ((vif_priv->pair_cipher == SSV_CIPHER_TKIP) || (vif_priv->group_cipher == SSV_CIPHER_TKIP)) {
+                    if (mic_err) {
+                        rxs->flag |= RX_FLAG_MMIC_ERROR;
+                        dev_dbg(sc->dev, "TKIP MMIC error, set RX_FLAG_MMIC_ERROR flag\n");
+                    }
+                    if (decode_err) {
+                        if (sc->sh->cfg.mic_err_notify) {
+                            rxs->flag |= RX_FLAG_MMIC_ERROR;
+                            dev_dbg(sc->dev, "decode error frame add mic err flag to notify nl80211\n");
+                        } else {
+                            dev_dbg(sc->dev, "Drop decode error frame\n");
+                            goto drop_rx;
+                        }
+                    }
+                } else {
+                    goto drop_rx;
+                }
+            }
+        }
+#if 0
+        if ( is_broadcast_ether_addr(hdr->addr1)
+             && (ieee80211_is_data_qos(fc) || ieee80211_is_data(fc)))
+#endif
+#if 0
+            if (ieee80211_is_probe_req(fc)) {
+#if 0
+                dev_dbg(sc->dev, KERN_ERR "RX M: 1 %02X:%02X:%02X:%02X:%02X:%02X  (%d - %d - %d)\n",
+                       hdr->addr1[0], hdr->addr1[1], hdr->addr1[2],
+                       hdr->addr1[3], hdr->addr1[4], hdr->addr1[5],
+                       (le16_to_cpu(hdr->seq_ctrl) >> 4),
+                       rxdesc->wsid, ieee80211_has_protected(fc));
+#endif
+                dev_dbg(sc->dev, KERN_ERR "Probe Req: 2 %02X:%02X:%02X:%02X:%02X:%02X\n",
+                       hdr->addr2[0], hdr->addr2[1], hdr->addr2[2],
+                       hdr->addr2[3], hdr->addr2[4], hdr->addr2[5]);
+#if 0
+                dev_dbg(sc->dev, KERN_ERR "RX M: 3 %02X:%02X:%02X:%02X:%02X:%02X\n",
+                       hdr->addr3[0], hdr->addr3[1], hdr->addr3[2],
+                       hdr->addr3[3], hdr->addr3[4], hdr->addr3[5]);
+#endif
+                _ssv6xxx_hexdump("RX frame", (const u8 *)rx_skb->data,
+                                 (rx_skb->len > 128) ? 128 : rx_skb->len);
+            }
+#endif
+        if (sc->sc_flags & SC_OP_DEV_READY) {
+#if defined(USE_THREAD_RX) && !defined(IRQ_PROC_RX_DATA)
+            local_bh_disable();
+            ieee80211_rx(sc->hw, rx_skb);
+            local_bh_enable();
+#else
+            ieee80211_rx_irqsafe(sc->hw, rx_skb);
+#endif
+        } else
+            goto drop_rx;
+        return;
+drop_rx:
+#if 0
+        dev_err(sc->dev, "D %02X:%02X:%02X:%02X:%02X:%02X\n",
+                hdr->addr2[0], hdr->addr2[1], hdr->addr2[2],
+                hdr->addr2[3], hdr->addr2[4], hdr->addr2[5]);
+#endif
+        dev_kfree_skb_any(rx_skb);
+    }
+#ifdef IRQ_PROC_RX_DATA
+    static struct sk_buff *_proc_rx_skb (struct ssv_softc *sc, struct sk_buff *rx_skb) {
+        struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(rx_skb->data + sc->sh->rx_desc_len);
+        u32 packet_len, c_type, tx_pkt_run_no;
+        SSV_GET_RX_DESC_INFO(sc->sh, rx_skb, &packet_len, &c_type, &tx_pkt_run_no);
+        if ( ieee80211_is_back(hdr->frame_control)
+             || (rxdesc->c_type == HOST_EVENT)
+             || (rxdesc->c_type == RATE_RPT))
+            return rx_skb;
+        if(rx_skb->len != packet_len) {
+            if (rx_skb->len < packet_len) {
+                dev_warn(sc->dev, "%s(): incorrect frame length %d[%d][%d]\n", __FUNCTION__, rx_skb->len, packet_len, c_type);
+                dev_kfree_skb_any(rx_skb);
+                return NULL;
+            }
+            skb_trim(rx_skb, packet_len);
+        }
+        _proc_data_rx_skb(sc, rx_skb);
+        return NULL;
+    }
+#endif
+    int _process_rx_umac(struct ssv6xxx_umac_ops *umac, struct sk_buff *skb) {
+        if (umac && umac->umac_rx_raw) {
+            umac->umac_rx_raw(skb);
+            dev_kfree_skb_any(skb);
+            return 1;
+        }
+        return 0;
+    }
+#define BEACON_MISS_RSSI_THRESHOLD (-80)
+    void ssv6xxx_beacon_miss_work(struct work_struct *work) {
+        struct ssv_softc *sc = container_of(work, struct ssv_softc, beacon_miss_work);
+        struct ssv_vif_priv_data *vif_priv = NULL;
+        struct sk_buff *skb = NULL;
+        struct ieee80211_hdr_3addr *nullfunc = NULL;
+        int tx_desc_size = 0, vif_idx = 0, signal = 0;
+        int ret = 0;
+        int i = 0;
+        struct ieee80211_sta *sta = NULL;
+        struct ssv_sta_priv_data *sta_priv_iter;
+        u8 macaddr[ETH_ALEN];
+        memcpy(macaddr, sc->sh->cfg.maddr[0], ETH_ALEN);
+        skb = ssv_skb_alloc(sc, sizeof(struct ieee80211_hdr_3addr));
+        if (!skb)
+            return;
+        down_read(&sc->sta_info_sem);
+        for (i = 0; i < SSV6200_MAX_VIF; i++) {
+            if (sc->vif_info[i].vif == NULL)
+                continue;
+            if (sc->vif_info[i].vif->type == NL80211_IFTYPE_STATION)
+                break;
+        }
+        if (i == SSV6200_MAX_VIF)
+            goto out;
+        vif_priv = (struct ssv_vif_priv_data *)sc->vif_info[i].vif->drv_priv;
+        if (list_empty(&vif_priv->sta_list)) {
+            dev_dbg(sc->dev, "%s(): sta_list is empty.\n", __func__);
+            goto out;
+        }
+        list_for_each_entry(sta_priv_iter, &vif_priv->sta_list, list) {
+            if (sc->sta_info[sta_priv_iter->sta_idx].s_flags & STA_FLAG_VALID)
+                break;
+        }
+        signal = -(sta_priv_iter->beacon_rssi >> RSSI_DECIMAL_POINT_SHIFT);
+        if (signal < BEACON_MISS_RSSI_THRESHOLD)
+            goto out;
+        sta = sc->sta_info[sta_priv_iter->sta_idx].sta;
+        if (!sta)
+            goto out;
+        vif_idx = sc->vif_info[i].vif_priv->vif_idx;
+        tx_desc_size = SSV_GET_TX_DESC_SIZE(sc->sh);
+        skb_put(skb, tx_desc_size+sizeof(struct ieee80211_hdr_3addr));
+        nullfunc = (struct ieee80211_hdr_3addr *)(skb->data + tx_desc_size);
+        memset(nullfunc, 0, sizeof(struct ieee80211_hdr_3addr));
+        sc->tx.seq_no += 0x10;
+        nullfunc->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
+        nullfunc->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
+        nullfunc->frame_control = cpu_to_le16(IEEE80211_FTYPE_DATA |
+                                              IEEE80211_STYPE_NULLFUNC |
+                                              IEEE80211_FCTL_TODS);
+        memcpy(nullfunc->addr1, sc->bssid[vif_idx], ETH_ALEN);
+        memcpy(nullfunc->addr2, macaddr, ETH_ALEN);
+        memcpy(nullfunc->addr3, sc->bssid[vif_idx], ETH_ALEN);
+        ret = SSV_UPDATE_NULL_FUNC_TXINFO(sc, sta, skb);
+        if (ret < 0)
+            goto out;
+        ret = HCI_SEND(sc->sh, skb, 4);
+        if (ret < 0)
+            goto out;
+        up_read(&sc->sta_info_sem);
+        return;
+out:
+        up_read(&sc->sta_info_sem);
+        dev_kfree_skb_any(skb);
+    }
+#ifdef SSV_SUPPORT_HAL
+    static void ssv6xxx_process_rx_lpbk_ptk(struct ssv_softc *sc, struct sk_buff *skb) {
+        struct ieee80211_hdr_3addr *hdr = NULL;
+        int i, hdr_offset = 0, hdrlen = 0;
+        u8 *payload;
+        hdr_offset = SSV_GET_RX_DESC_HDR_OFFSET(sc->sh, skb);
+        hdr = (struct ieee80211_hdr_3addr *)(skb->data + hdr_offset);
+        hdrlen = ieee80211_hdrlen(hdr->frame_control);
+        if (0 < SSV_CHK_LPBK_RX_RATE_DESC(sc->sh, skb)) {
+            sc->lpbk_err_cnt++;
+            goto out;
+        }
+        payload = (u8 *)hdr + hdrlen;
+        for (i = (hdr_offset + hdrlen); i < (skb->len - 4); i++) {
+            if (hdr->seq_ctrl != *payload) {
+                _ssv6xxx_hexdump("lpbk pkt ", (const u8 *)skb->data, skb->len);
+                sc->lpbk_err_cnt++;
+                break;
+            }
+            payload++;
+        }
+out:
+        sc->lpbk_rx_pkt_cnt++;
+        dev_kfree_skb_any(skb);
+    }
+#endif
+    static bool _process_host_event(struct ssv_softc *sc, struct sk_buff *skb, bool *has_ba_processed) {
+        u32 c_type;
+        struct cfg_host_event *h_evt;
+#ifdef SSV_SUPPORT_HAL
+        c_type = HAL_GET_RX_DESC_CTYPE(sc->sh, skb);
+#else
+        struct ssv6200_rx_desc *rxdesc;
+        rxdesc = (struct ssv6200_rx_desc *)skb->data;
+        c_type = rxdesc->c_type;
+#endif
+        if (c_type != HOST_EVENT)
+            return false;
+        h_evt = (struct cfg_host_event *)skb->data;
+        switch (h_evt->h_event) {
+        case SOC_EVT_NO_BA:
+            ssv6200_ampdu_no_BA_handler(sc->hw, skb);
+#ifdef USE_FLUSH_RETRY
+            *has_ba_processed = true;
+#endif
+            break;
+        case SOC_EVT_RC_MPDU_REPORT:
+            skb_queue_tail(&sc->rc_report_queue, skb);
+            if (sc->rc_report_sechedule == 0)
+                queue_work(sc->rc_report_workqueue, &sc->rc_report_work);
+            break;
+        case SOC_EVT_SDIO_TEST_COMMAND:
+            if (h_evt->evt_seq_no == 0) {
+                dev_dbg(sc->dev, "SOC_EVT_SDIO_TEST_COMMAND\n");
+                sc->sdio_rx_evt_size = h_evt->len;
+                sc->sdio_throughput_timestamp = jiffies;
+            } else {
+                sc->sdio_rx_evt_size += h_evt->len;
+                if (time_after(jiffies,
+                               ( sc->sdio_throughput_timestamp
+                                 + msecs_to_jiffies(1000)))) {
+                    dev_dbg(sc->dev, "data[%ld] SDIO RX throughput %ld Kbps\n",
+                           sc->sdio_rx_evt_size,
+                           ( (sc->sdio_rx_evt_size << 3)
+                             / jiffies_to_msecs( jiffies
+                                                 - sc->sdio_throughput_timestamp)));
+                    sc->sdio_throughput_timestamp = jiffies;
+                    sc->sdio_rx_evt_size = 0;
+                }
+            }
+            dev_kfree_skb_any(skb);
+            break;
+        case SOC_EVT_RESET_HOST:
+            dev_kfree_skb_any(skb);
+            if ((sc->ap_vif == NULL) && (sc->sh->cfg.online_reset & ONLINE_RESET_ENABLE)) {
+                queue_work(sc->config_wq, &sc->hw_restart_work);
+            } else {
+                dev_warn(sc->dev, "Reset event ignored.\n");
+            }
+            break;
+#ifdef CONFIG_P2P_NOA
+        case SOC_EVT_NOA:
+            ssv6xxx_process_noa_event(sc, skb);
+            dev_kfree_skb_any(skb);
+            break;
+#endif
+        case SOC_EVT_SDIO_TXTPUT_RESULT:
+            dev_dbg(sc->dev, "data SDIO TX throughput %d Kbps\n", h_evt->evt_seq_no);
+            dev_kfree_skb_any(skb);
+            break;
+        case SOC_EVT_TXLOOPBK_RESULT:
+            if (h_evt->evt_seq_no == SSV6XXX_STATE_OK) {
+                dev_dbg(sc->dev, "FW TX LOOPBACK OK\n");
+                sc->iq_cali_done = IQ_CALI_OK;
+            } else {
+                dev_dbg(sc->dev, KERN_ERR "FW TX LOOPBACK FAILED\n");
+                sc->iq_cali_done = IQ_CALI_FAILED;
+            }
+            dev_kfree_skb_any(skb);
+            wake_up_interruptible(&sc->fw_wait_q);
+            break;
+#ifdef CONFIG_SSV_SMARTLINK
+        case SOC_EVT_SMART_ICOMM: {
+            extern void ssv6xxx_process_si_event(struct ssv_softc *sc, struct sk_buff *skb);
+            ssv6xxx_process_si_event(sc, skb);
+            dev_kfree_skb_any(skb);
+            break;
+        }
+#endif
+        case SOC_EVT_BEACON_LOSS:
+            dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_BEACON, "beacon dectection trigger\n");
+            dev_kfree_skb_any(skb);
+            queue_work(sc->config_wq, &sc->beacon_miss_work);
+            if (sc->isAssoc)
+                SSV_BEACON_LOSS_ENABLE(sc->sh);
+            break;
+        case SOC_EVT_TX_STUCK_RESP:
+            dev_dbg(sc->dev, "receive event tx_stuck!!\n");
+            dev_kfree_skb_any(skb);
+            break;
+        case SOC_EVT_SW_BEACON_RESP:
+            dev_dbg(sc->dev, "soft-beacon start!!\n");
+            dev_kfree_skb_any(skb);
+            break;
+        default:
+            dev_warn(sc->dev, "Unkown event %d received\n", h_evt->h_event);
+            dev_kfree_skb_any(skb);
+            break;
+        }
+        return true;
+    }
+    static void ssv6xxx_adjust_rx_burstread_sztype(struct ssv_softc *sc, struct sk_buff *skb) {
+        struct ssv_hw *sh = sc->sh;
+        if (sh->rx_mode != RX_BURSTREAD_MODE)
+            return;
+        if (skb->len > MAX_RX_BURSTREAD_LENGTH) {
+            sh->rx_burstread_cnt++;
+            if (sh->rx_burstread_cnt > MAX_RX_BURSTREAD_CNT)
+                sh->rx_burstread_size_type =
+                    (skb->len > MAX_FRAME_SIZE) ? RX_BURSTREAD_SZ_MAX_FRAME_DMG : RX_BURSTREAD_SZ_MAX_FRAME;
+        } else {
+            sh->rx_burstread_cnt = 0;
+            sh->rx_burstread_size_type = RX_BURSTREAD_SZ_FROM_CMD;
+        }
+    }
+    static bool ssv6xxx_aggr_frame_is_last(unsigned char *data, int offset, int length) {
+        struct hci_rx_aggr_info *rx_aggr_info = (struct hci_rx_aggr_info *)data;
+        struct hci_rx_aggr_info *next_rx_aggr_info;
+        if ((rx_aggr_info->jmp_mpdu_len + offset) == (length - 1))
+            return true;
+        next_rx_aggr_info = (struct hci_rx_aggr_info *)(data + rx_aggr_info->jmp_mpdu_len);
+        if ((next_rx_aggr_info->jmp_mpdu_len == 0) ||
+            (next_rx_aggr_info->jmp_mpdu_len > (length - (offset + rx_aggr_info->jmp_mpdu_len))))
+            return true;
+        return false;
+    }
+    void _process_rx_q (struct ssv_softc *sc, struct sk_buff_head *rx_q, spinlock_t *rx_q_lock) {
+        struct sk_buff *skb, *sskb;
+        struct ieee80211_hdr *hdr;
+        unsigned long flags=0;
+        u32 packet_len, c_type, tx_pkt_run_no;
+        int rx_mode = sc->sh->rx_mode;
+        int data_offset, data_length;
+        unsigned char *pdata, *psdata;
+        struct hci_rx_aggr_info *rx_aggr_info;
+        bool last_packet = false, no_ba_result = false;
+#ifdef USE_FLUSH_RETRY
+        bool has_ba_processed = false;
+#endif
+        while (1) {
+            if (rx_q_lock != NULL) {
+                spin_lock_irqsave(rx_q_lock, flags);
+                skb = __skb_dequeue(rx_q);
+            } else
+                skb = skb_dequeue(rx_q);
+            if (!skb) {
+                if (rx_q_lock != NULL)
+                    spin_unlock_irqrestore(rx_q_lock, flags);
+                break;
+            }
+            sc->rx.rxq_count --;
+            if (rx_q_lock != NULL)
+                spin_unlock_irqrestore(rx_q_lock, flags);
+            data_length = skb->len;
+            pdata = skb->data;
+            for (data_offset = 0; data_offset < data_length; ) {
+                if ((rx_mode == RX_NORMAL_MODE) || (rx_mode == RX_BURSTREAD_MODE)) {
+                    sskb = skb;
+                    data_offset = skb->len;
+                } else {
+                    last_packet = ssv6xxx_aggr_frame_is_last(pdata, data_offset, data_length);
+                    if (last_packet) {
+                        rx_aggr_info = (struct hci_rx_aggr_info *)pdata;
+                        if (((data_offset + sizeof(struct hci_rx_aggr_info)) > data_length) ||
+                            ((data_offset + rx_aggr_info->jmp_mpdu_len) > data_length)) {
+                            dev_kfree_skb_any(skb);
+                            break;
+                        }
+                        skb_pull(skb, sizeof(struct hci_rx_aggr_info));
+                        sskb = skb;
+                        data_offset = data_length;
+                    } else {
+                        rx_aggr_info = (struct hci_rx_aggr_info *)pdata;
+                        sskb = ssv_skb_alloc(sc, rx_aggr_info->jmp_mpdu_len);
+                        if (!sskb) {
+                            dev_warn(sc->dev, "%s(): cannot alloc skb buffer\n", __FUNCTION__);
+                            pdata += rx_aggr_info->jmp_mpdu_len;
+                            data_offset += rx_aggr_info->jmp_mpdu_len;
+                            continue;
+                        }
+                        if ((rx_aggr_info->jmp_mpdu_len == 0) ||
+                            (rx_aggr_info->jmp_mpdu_len > MAX_FRAME_SIZE) ||
+                            ((data_offset + sizeof(struct hci_rx_aggr_info)) > data_length) ||
+                            ((data_offset + rx_aggr_info->jmp_mpdu_len) > data_length)) {
+                            dev_kfree_skb_any(skb);
+                            dev_kfree_skb_any(sskb);
+                            break;
+                        }
+                        psdata = skb_put(sskb, (rx_aggr_info->jmp_mpdu_len - sizeof(struct hci_rx_aggr_info)));
+                        memcpy(psdata, pdata+sizeof(struct hci_rx_aggr_info),
+                               (rx_aggr_info->jmp_mpdu_len - sizeof(struct hci_rx_aggr_info)));
+                        pdata = skb_pull(skb, rx_aggr_info->jmp_mpdu_len);
+                        data_offset += rx_aggr_info->jmp_mpdu_len;
+                    }
+                }
+                SSV_GET_RX_DESC_INFO(sc->sh, sskb, &packet_len, &c_type, &tx_pkt_run_no);
+                if(sskb->len != packet_len) {
+                    if (sskb->len < packet_len) {
+                        dev_warn(sc->dev, "Incorrect frame length %d[%d][%d]\n", sskb->len, packet_len, c_type);
+                        dev_kfree_skb_any(sskb);
+                        continue;
+                    }
+                    skb_trim(sskb, packet_len);
+                }
+                if (_process_rx_umac(sc->umac, sskb))
+                    continue;
+                if (c_type == RATE_RPT) {
+                    SSV_RATE_REPORT_HANDLER(sc, sskb, &no_ba_result);
+#ifdef USE_FLUSH_RETRY
+                    has_ba_processed = no_ba_result;
+#endif
+                    continue;
+                }
+                if (_process_host_event(sc, sskb, &has_ba_processed))
+                    continue;
+#ifdef SSV_SUPPORT_HAL
+                if (sc->lpbk_enable) {
+                    ssv6xxx_process_rx_lpbk_ptk(sc, sskb);
+                    continue;
+                }
+#endif
+                hdr = (struct ieee80211_hdr *)(sskb->data + sc->sh->rx_desc_len);
+                if (ieee80211_is_back(hdr->frame_control)) {
+                    SSV_AMPDU_BA_HANDLER(sc, sc->hw, sskb, tx_pkt_run_no);
+#ifdef USE_FLUSH_RETRY
+                    has_ba_processed = true;
+#endif
+                    continue;
+                }
+                if (ieee80211_is_beacon(hdr->frame_control)) {
+                    if ((sc->isAssoc) && (sc->beacon_container_update_time == 0)) {
+                        sc->beacon_container = ssv_skb_alloc(sc, packet_len);
+                        skb_put(sc->beacon_container, packet_len);
+                        memcpy(sc->beacon_container->data, sskb->data, packet_len);
+                        sc->beacon_container_update_time = jiffies;
+                    }
+                }
+                ssv6xxx_adjust_rx_burstread_sztype(sc, sskb);
+                _proc_data_rx_skb(sc, sskb);
+            }
+        }
+#ifdef USE_FLUSH_RETRY
+        if (has_ba_processed) {
+            ssv6xxx_ampdu_postprocess_BA(sc->hw);
+        }
+#endif
+    }
+    int ssv6200_is_rx_q_full(void *args) {
+        struct ssv_softc *sc=args;
+        if (skb_queue_len(&sc->rx_skb_q) > sc->sh->cfg.rx_threshold) {
+            return 1;
+        } else {
+            return 0;
+        }
+    }
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+    int ssv6200_rx(struct sk_buff_head *rx_skb_q, void *args)
+#else
+    int ssv6200_rx(struct sk_buff *rx_skb, void *args)
+#endif
+    {
+        struct ssv_softc *sc=args;
+#ifdef IRQ_PROC_RX_DATA
+        struct sk_buff *skb;
+        skb = _proc_rx_skb(sc, rx_skb);
+        if (skb == NULL)
+            return 0;
+#endif
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+        while (skb_queue_len(rx_skb_q))
+            skb_queue_tail(&sc->rx_skb_q, skb_dequeue(rx_skb_q));
+#else
+        skb_queue_tail(&sc->rx_skb_q, rx_skb);
+#endif
+        wake_up_interruptible(&sc->rx_wait_q);
+        return 0;
+    }
+    void ssv6xxx_rx_stuck_process(struct work_struct *work) {
+        struct ssv_softc *sc = container_of(work, struct ssv_softc, rx_stuck_work);
+        struct ieee80211_vif *vif;
+        unsigned long wait_period = msecs_to_jiffies(60000);
+        unsigned long cur_jiffies;
+        int i = 0, edca_threshold = 0;
+        int assoc = 0, p2p = 0;
+        if ((sc->ap_vif == NULL) && (sc->isAssoc == true)) {
+            for (i = 0; i < SSV6200_MAX_VIF; i++) {
+                if (sc->vif_info[i].vif != NULL) {
+                    vif = sc->vif_info[i].vif;
+                    if ((vif->type == NL80211_IFTYPE_STATION) || (vif->type == NL80211_IFTYPE_P2P_CLIENT)) {
+                        if (vif->bss_conf.assoc)
+                            assoc++;
+                        if (vif->p2p)
+                            p2p++;
+                    }
+                }
+            }
+            if ((assoc == 1) && (p2p == 0)) {
+                cur_jiffies = jiffies;
+                edca_threshold =
+                    ((sc->sh->cfg.online_reset & ONLINE_RESET_EDCA_THRESHOLD_MASK) >> ONLINE_RESET_EDCA_THRESHOLD_SFT);
+                if ((sc->rx_stuck_idle_time >= MAX_RX_IDLE_INTERVAL) &&
+                    time_before((sc->rx_stuck_reset_time + wait_period), cur_jiffies)) {
+                    if (sc->primary_edca_mib > edca_threshold) {
+                        sc->rx_stuck_idle_time = 0;
+                        sc->rx_stuck_reset_time = cur_jiffies;
+                        if (sc->bScanning == false)
+                            queue_work(sc->config_wq, &sc->hw_restart_work);
+                    }
+                }
+            }
+        }
+    }
+    void ssv6xxx_mib_edca_process(struct work_struct *work) {
+        struct ssv_softc *sc = container_of(work, struct ssv_softc, mib_edca_work);
+        if (!sc->sh)
+            return;
+        SSV_EDCA_STAT(sc->sh);
+    }
+    void ssv6xxx_tx_poll_process(struct work_struct *work) {
+        struct ssv_softc *sc = container_of(work, struct ssv_softc, tx_poll_work);
+        if (!sc->sh)
+            return;
+        SSV_SEND_TX_POLL_CMD(sc->sh, SSV6XXX_TX_POLL_RESET);
+    }
+#ifdef CONFIG_SSV_CCI_IMPROVEMENT
+    void ssv6xxx_cci_clean_process(struct work_struct *work) {
+        struct ssv_softc *sc = container_of(work, struct ssv_softc, cci_clean_work);
+        if (!sc->sh)
+            return;
+#ifndef SSV_SUPPORT_HAL
+        SMAC_REG_READ(sc->sh, 0xCE01000C, &sc->pre_11b_rx_abbctune);
+        SMAC_REG_READ(sc->sh, ADR_RX_11B_CCA_CONTROL, &sc->pre_11b_cca_control);
+        SMAC_REG_READ(sc->sh, ADR_RX_11B_CCA_1, &sc->pre_11b_cca_1);
+        SMAC_REG_WRITE(sc->sh, 0xCE01000C, (sc->pre_11b_rx_abbctune | (0x3F << 3)));
+        SMAC_REG_WRITE(sc->sh, ADR_RX_11B_CCA_CONTROL, 0x0);
+        SMAC_REG_WRITE(sc->sh, ADR_RX_11B_CCA_1, RX_11B_CCA_IN_SCAN);
+#else
+        HAL_UPDATE_SCAN_CCI_SETTING(sc);
+#endif
+        sc->cci_current_level = MAX_CCI_LEVEL;
+        sc->cci_set = true;
+    }
+    void ssv6xxx_cci_set_process(struct work_struct *work) {
+        struct ssv_softc *sc = container_of(work, struct ssv_softc, cci_set_work);
+        if (!sc->sh)
+            return;
+#ifndef SSV_SUPPORT_HAL
+        SMAC_REG_WRITE(sc->sh, 0xCE01000C, sc->pre_11b_rx_abbctune);
+        SMAC_REG_WRITE(sc->sh, ADR_RX_11B_CCA_CONTROL, sc->pre_11b_cca_control);
+        SMAC_REG_WRITE(sc->sh, ADR_RX_11B_CCA_1, sc->pre_11b_cca_1);
+#else
+        HAL_RECOVERY_SCAN_CCI_SETTING(sc);
+#endif
+    }
+#endif
+    void ssv6xxx_set_txpwr_process(struct work_struct *work) {
+        struct ssv_softc *sc = container_of(work, struct ssv_softc, set_txpwr_work);
+        if (!sc->sh)
+            return;
+#ifdef SSV_SUPPORT_HAL
+        HAL_UPDATE_RF_PWR(sc);
+#endif
+    }
+    void ssv6xxx_thermal_monitor_process(struct work_struct *work) {
+        struct ssv_softc *sc = container_of(work, struct ssv_softc, thermal_monitor_work);
+        if (!sc->sh)
+            return;
+        SSV_DO_TEMPERATURE_COMPENSATION(sc->sh);
+    }
+#ifdef SSV_SUPPORT_HAL
+    void ssv6xxx_rc_report_work(struct work_struct *work) {
+        struct ssv_softc *sc = container_of(work, struct ssv_softc, rc_report_work);
+        struct sk_buff *skb;
+        sc->rc_report_sechedule = 1;
+        while(1) {
+            skb = skb_dequeue(&sc->rc_report_queue);
+            if(skb == NULL)
+                break;
+#ifdef DISABLE_RATE_CONTROL_SAMPLE
+            {
+                dev_kfree_skb_any(skb);
+                continue;
+            }
+#endif
+            HAL_RC_PROCESS_RATE_REPORT(sc, skb);
+            dev_kfree_skb_any(skb);
+        }
+        sc->rc_report_sechedule = 0;
+    }
+#else
+    void ssv6xxx_rc_report_work(struct work_struct *work) {
+        struct ssv_softc *sc = container_of(work, struct ssv_softc, rc_report_work);
+        struct ssv_rate_ctrl *ssv_rc=sc->rc;
+        struct sk_buff *skb;
+        struct cfg_host_event *host_event;
+        struct ssv_sta_rc_info *rc_sta=NULL;
+        struct firmware_rate_control_report_data *report_data;
+        struct ssv_sta_info *ssv_sta;
+        u8 hw_wsid = 0;
+        sc->rc_report_sechedule = 1;
+        while(1) {
+            skb = skb_dequeue(&sc->rc_report_queue);
+            if(skb == NULL)
+                break;
+#ifdef DISABLE_RATE_CONTROL_SAMPLE
+            {
+                dev_kfree_skb_any(skb);
+                continue;
+            }
+#endif
+            host_event = (struct cfg_host_event *)skb->data;
+            if((host_event->h_event == SOC_EVT_RC_AMPDU_REPORT) || (host_event->h_event == SOC_EVT_RC_MPDU_REPORT)) {
+                report_data = (struct firmware_rate_control_report_data *)&host_event->dat[0];
+                hw_wsid = report_data->wsid;
+            } else {
+                dev_dbg(sc->dev, "RC work get garbage!!\n");
+                dev_kfree_skb_any(skb);
+                continue;
+            }
+            if((hw_wsid >= SSV_RC_MAX_HARDWARE_SUPPORT) && (host_event->h_event == SOC_EVT_RC_MPDU_REPORT)) {
+#ifdef RATE_CONTROL_DEBUG
+                dev_dbg(sc->dev, "[RC]rc_sta is NULL pointer Check-0!!\n");
+#endif
+                dev_kfree_skb_any(skb);
+                continue;
+            }
+            if (hw_wsid >= SSV_NUM_STA) {
+                dev_warn(sc->dev, "[RC]hw_wsid[%d] is invaild!!\n", hw_wsid);
+                dev_kfree_skb_any(skb);
+                continue;
+            }
+            down_read(&sc->sta_info_sem);
+            ssv_sta = &sc->sta_info[hw_wsid];
+            if ((ssv_sta->s_flags & STA_FLAG_VALID) == 0) {
+                up_read(&sc->sta_info_sem);
+                dev_warn(sc->dev, "%s(): ssv_info is gone. (%d)\n", __FUNCTION__, hw_wsid);
+                return;
+            }
+            if (ssv_sta->sta == NULL) {
+                dev_err(sc->dev, "Null STA %d for RC report.\n", hw_wsid);
+                rc_sta = NULL;
+            } else {
+                struct ssv_sta_priv_data *ssv_sta_priv = (struct ssv_sta_priv_data *)ssv_sta->sta->drv_priv;
+                rc_sta = &ssv_rc->sta_rc_info[ssv_sta_priv->rc_idx];
+#if 0
+                if (rc_sta->rc_wsid != hw_wsid) {
+                    rc_sta = NULL;
+                }
+#endif
+            }
+            if(rc_sta == NULL) {
+                dev_err(sc->dev, "[RC]rc_sta %d is NULL pointer Check-1!!\n",hw_wsid);
+                dev_kfree_skb_any(skb);
+                continue;
+            }
+#if 0
+            if(rc_sta->rc_wsid != hw_wsid) {
+                dev_dbg(sc->dev, "[RC] wsid mapping [ERROR] feedback wsid[%d] rc_wsid[%d]...><\n",hw_wsid,rc_sta->rc_wsid);
+#if 1
+                for(i=0; i<SSV_RC_MAX_STA; i++) {
+                    rc_sta = &ssv_rc->sta_rc_info[i];
+                    if(rc_sta == NULL)
+                        break;
+                    if(hw_wsid == rc_sta->rc_wsid) {
+                        dev_dbg(sc->dev, "[RC] Get new mapping-%d-%d...@o@\n",hw_wsid, i);
+                        break;
+                    }
+                }
+                if(i == SSV_RC_MAX_STA)
+#endif
+                    rc_sta = NULL;
+            }
+#endif
+            if(rc_sta == NULL) {
+#ifdef RATE_CONTROL_DEBUG
+                dev_dbg(sc->dev, "[RC]rc_sta is NULL pointer Check-2!!\n");
+#endif
+                dev_kfree_skb_any(skb);
+                continue;
+            }
+            if (rc_sta->is_ht) {
+                if (hw_wsid < SSV_RC_MAX_HARDWARE_SUPPORT)
+                    ssv6xxx_legacy_report_handler(sc,skb,rc_sta);
+                ssv6xxx_ht_report_handler(sc,skb,rc_sta);
+            } else {
+                if (hw_wsid < SSV_RC_MAX_HARDWARE_SUPPORT)
+                    ssv6xxx_legacy_report_handler(sc,skb,rc_sta);
+            }
+            dev_kfree_skb_any(skb);
+        }
+        up_read(&sc->sta_info_sem);
+        sc->rc_report_sechedule = 0;
+    }
+#endif
+    struct ieee80211_sta *ssv6xxx_find_sta_by_rx_skb (struct ssv_softc *sc, struct sk_buff *skb) {
+        struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data + sc->sh->rx_desc_len);
+        u32 wsid;
+#ifdef SSV_SUPPORT_HAL
+        wsid = HAL_GET_RX_DESC_WSID(sc->sh, skb);
+#else
+        struct ssv6200_rx_desc *rxdesc = (struct ssv6200_rx_desc *)skb->data;;
+        wsid = rxdesc->wsid;
+#endif
+        if ((wsid >= 0) && (wsid < SSV_NUM_STA))
+            return sc->sta_info[wsid].sta;
+        else
+            return ssv6xxx_find_sta_by_addr(sc, hdr->addr2);
+    }
+    struct ieee80211_sta *ssv6xxx_find_sta_by_addr (struct ssv_softc *sc, u8 addr[6]) {
+        struct ieee80211_sta *sta;
+        int i;
+        for (i = 0; i < SSV6200_MAX_VIF; i++) {
+            if (sc->vif_info[i].vif == NULL)
+                continue;
+            sta = ieee80211_find_sta(sc->vif_info[i].vif, addr);
+            if (sta != NULL)
+                return sta;
+        }
+        return NULL;
+    }
+    void ssv6xxx_foreach_sta (struct ssv_softc *sc, void (*sta_func)(struct ssv_softc *, struct ssv_sta_info *, void *), void *param) {
+        int i;
+        BUG_ON(sta_func == NULL);
+#if 0
+        for (i = 0; i < SSV6200_MAX_VIF; i++) {
+            struct ssv_vif_priv_data *vif_priv;
+            int j;
+            if (sc->vif_info[i].vif == NULL)
+                continue;
+            vif_priv = (struct ssv_vif_priv_data *)sc->vif[i]->drv_priv;
+            for (j = 0; j < SSV_NUM_STA; j++) {
+                if ((vif_priv->sta_info[j].s_flags & STA_FLAG_VALID) == 0)
+                    continue;
+                (*sta_func)(sc, &vif_priv->sta_info[j], param);
+            }
+        }
+#else
+        down_read(&sc->sta_info_sem);
+        for (i = 0; i < SSV_NUM_STA; i++) {
+            if ((sc->sta_info[i].s_flags & STA_FLAG_VALID) == 0)
+                continue;
+            (*sta_func)(sc, &sc->sta_info[i], param);
+        }
+        up_read(&sc->sta_info_sem);
+#endif
+    }
+    void ssv6xxx_foreach_vif_sta (struct ssv_softc *sc,
+                                  struct ssv_vif_info *vif_info,
+                                  void (*sta_func)(struct ssv_softc *,
+                                          struct ssv_vif_info *,
+                                          struct ssv_sta_info *,
+                                          void *),
+                                  void *param) {
+        struct ssv_vif_priv_data *vif_priv;
+        struct ssv_sta_priv_data *sta_priv_iter;
+        BUG_ON(vif_info == NULL);
+        BUG_ON((size_t)vif_info < 0x30000);
+        vif_priv = (struct ssv_vif_priv_data *)vif_info->vif->drv_priv;
+        BUG_ON((size_t)vif_info->vif < 0x30000);
+        BUG_ON((size_t)vif_priv < 0x30000);
+        list_for_each_entry(sta_priv_iter, &vif_priv->sta_list, list) {
+            BUG_ON(sta_priv_iter == NULL);
+            BUG_ON((size_t)sta_priv_iter < 0x30000);
+            if ((sc->sta_info[sta_priv_iter->sta_idx].s_flags & STA_FLAG_VALID) == 0)
+                continue;
+            (*sta_func)(sc, vif_info, &sc->sta_info[sta_priv_iter->sta_idx], param);
+        }
+    }
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+    ssize_t ssv6xxx_tx_queue_status_dump (struct ssv_softc *sc, char *status_buf,
+                                          ssize_t length) {
+        ssize_t buf_size = length;
+        ssize_t prt_size;
+        prt_size = snprintf(status_buf, buf_size, "\nSMAC driver queue status:.\n");
+        status_buf += prt_size;
+        buf_size -= prt_size;
+#ifdef MULTI_THREAD_ENCRYPT
+        prt_size = snprintf(status_buf, buf_size, "\tCrypto pre-process queue: %d.\n",
+                            skb_queue_len(&sc->preprocess_q));
+        status_buf += prt_size;
+        buf_size -= prt_size;
+        prt_size = snprintf(status_buf, buf_size, "\tMax pre-process queue: %d.\n",
+                            sc->max_preprocess_q_len);
+        status_buf += prt_size;
+        buf_size -= prt_size;
+        prt_size = snprintf(status_buf, buf_size, "\tCrypto process queue: %d.\n",
+                            skb_queue_len(&sc->crypted_q));
+        status_buf += prt_size;
+        buf_size -= prt_size;
+        prt_size = snprintf(status_buf, buf_size, "\tMax process queue: %d.\n",
+                            sc->max_crypted_q_len);
+        status_buf += prt_size;
+        buf_size -= prt_size;
+#endif
+        prt_size = snprintf(status_buf, buf_size, "\tTX queue: %d\n",
+                            skb_queue_len(&sc->tx_skb_q));
+        status_buf += prt_size;
+        buf_size -= prt_size;
+        prt_size = snprintf(status_buf, buf_size, "\tMax TX queue: %d\n",
+                            sc->max_tx_skb_q_len);
+        status_buf += prt_size;
+        buf_size -= prt_size;
+        return (length - buf_size);
+    }
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smac/dev.h b/drivers/net/wireless/ssv6x5x/smac/dev.h
new file mode 100644
index 000000000..236010c78
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/dev.h
@@ -0,0 +1,1419 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _DEV_H_
+#define _DEV_H_
+#include <linux/version.h>
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#ifdef CONFIG_SSV_SUPPORT_ANDROID
+#include <linux/wakelock.h>
+#ifdef CONFIG_HAS_EARLYSUSPEND
+#include <linux/earlysuspend.h>
+#endif
+#endif
+#ifdef SSV_MAC80211
+#include "ssv_mac80211.h"
+#else
+#include <net/mac80211.h>
+#endif
+#include "ampdu.h"
+#include "ssv_rc_common.h"
+#include "drv_comm.h"
+#include "sec.h"
+#include "p2p.h"
+#include <linux/kthread.h>
+#define SSV_DRVER_NAME "ssv6x5x"
+#define RF_MODE_SHUTDOWN 0
+#define RF_MODE_STANDBY 1
+#define RF_MODE_TRX_EN 2
+#define MRX_MODE_PROMISCUOUS 0x2
+#define MRX_MODE_NORMAL 0x3
+#define CCI_CTL 0x1
+#define CCI_DBG 0x2
+#define CCI_P1 0x4
+#define CCI_P2 0x8
+#define CCI_SMART 0x10
+#define MAX_CCI_LEVEL 128
+#define GT_PWR_START_MASK 0xFF
+#define GT_ENABLE 0x100
+#define GT_DBG 0x200
+#define AUTOSGI_CTL 0x1
+#define AUTOSGI_DBG 0x2
+#define CCMP_MIC_LEN 8
+enum ssv_rx_flow {
+    RX_DATA_FLOW,
+    RX_MGMT_FLOW,
+    RX_CTRL_FLOW,
+};
+#ifdef CONFIG_PM
+struct ssv_trap_data {
+    u32 reason_trap0;
+    u32 reason_trap1;
+};
+#endif
+struct ssv_dbg_log {
+    int size;
+    int totalsize;
+    char *data;
+    char *top;
+    char *tail;
+    char *end;
+};
+struct ssv_cmd_data {
+    char *ssv6xxx_result_buf;
+    u32 rsbuf_len;
+    u32 rsbuf_size;
+    bool cmd_in_proc;
+    bool log_to_ram;
+    struct ssv_dbg_log dbg_log;
+    struct proc_dir_entry *proc_dev_entry;
+    atomic_t cli_count;
+};
+void dbgprint(struct ssv_cmd_data *cmd_data, u32 log_ctrl, u32 log_id, const char *fmt,...);
+void ssv6xxx_hci_dbgprint(void *argc, u32 log_id, const char *fmt,...);
+#define AMPDU_BA_FRAME_LEN (68)
+#define INDEX_PKT_BY_SSN(tid,ssn) \
+    ((tid)->aggr_pkts[(ssn) % SSV_AMPDU_BA_WINDOW_SIZE])
+#define MAX_CONCUR_AMPDU 64
+#define ampdu_skb_hdr(skb) ((struct ieee80211_hdr*)((u8*)((skb)->data)+AMPDU_DELIMITER_LEN))
+#define ampdu_skb_ssn(skb) ((ampdu_skb_hdr(skb)->seq_ctrl)>>SSV_SEQ_NUM_SHIFT)
+#define ampdu_hdr_ssn(hdr) ((hdr)->seq_ctrl>>SSV_SEQ_NUM_SHIFT)
+#if 1
+#define prn_aggr_dbg(_sc,fmt,...) \
+    do { \
+        dbgprint(&(_sc)->cmd_data, (_sc)->log_ctrl, LOG_AMPDU_DBG, KERN_DEBUG fmt, ##__VA_ARGS__); \
+    } while (0)
+#else
+#undef prn_aggr_dbg
+#define prn_aggr_dbg(sc,fmt,...)
+#endif
+#if 1
+#define prn_aggr_err(_sc,fmt,...) \
+    do { \
+        dbgprint(&(_sc)->cmd_data, (_sc)->log_ctrl, LOG_AMPDU_ERR, KERN_ERR fmt, ##__VA_ARGS__);\
+    } while (0)
+#else
+#define prn_aggr_err(fmt,...)
+#endif
+#define SSV_TEMPERATURE_NORMAL 0
+#define SSV_TEMPERATURE_HIGH 1
+#define SSV_TEMPERATURE_LOW 2
+#define RX_HCI M_ENG_MACRX|(M_ENG_HWHCI<<4)
+#define RX_CIPHER_HCI M_ENG_MACRX|(M_ENG_ENCRYPT_SEC<<4)|(M_ENG_HWHCI<<8)
+#define RX_CPU_HCI M_ENG_MACRX|(M_ENG_CPU<<4)|(M_ENG_HWHCI<<8)
+#define RX_TRASH M_ENG_MACRX|(M_ENG_TRASH_CAN<<4)
+#define RX_CIPHER_MIC_HCI M_ENG_MACRX|(M_ENG_ENCRYPT_SEC<<4)|(M_ENG_MIC_SEC<<8)|(M_ENG_HWHCI<<12)
+#define SSV6200_MAX_HW_MAC_ADDR 2
+#define SSV6200_MAX_VIF 2
+#define SSV6200_RX_BA_MAX_SESSIONS 1
+enum SSV6XXX_OPMODE {
+    SSV6XXX_OPMODE_STA = 0,
+    SSV6XXX_OPMODE_AP = 1,
+    SSV6XXX_OPMODE_IBSS = 2,
+    SSV6XXX_OPMODE_WDS = 3
+};
+#define SSV6200_USE_HW_WSID(_sta_idx) ((_sta_idx == 0) || (_sta_idx == 1))
+#define HW_MAX_RATE_TRIES 7
+#define MAC_DECITBL1_SIZE 16
+#define MAC_DECITBL2_SIZE 9
+#ifdef CONFIG_SSV_CCI_IMPROVEMENT
+struct ssv6xxx_b_cca_control {
+    u32 down_level;
+    u32 upper_level;
+    u32 adjust_cca_control;
+    u32 adjust_cca_1;
+};
+struct ssv6xxx_cca_control {
+    u32 down_level;
+    u32 upper_level;
+    u32 adjust_cck_cca_control;
+    u32 adjust_ofdm_cca_control;
+};
+#endif
+#ifndef USE_GENERIC_DECI_TBL
+extern u16 ap_deci_tbl[];
+extern u16 sta_deci_tbl[];
+#else
+extern u16 generic_deci_tbl[];
+#define ap_deci_tbl generic_deci_tbl
+#define sta_deci_tbl generic_deci_tbl
+#endif
+#define HT_SIGNAL_EXT 6
+#define HT_SIFS_TIME 10
+#define BITS_PER_BYTE 8
+#define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
+#define ACK_LEN (14)
+#define BA_LEN (32)
+#define RTS_LEN (20)
+#define CTS_LEN (14)
+#define L_STF 8
+#define L_LTF 8
+#define L_SIG 4
+#define HT_SIG 8
+#define HT_STF 4
+#define HT_LTF(_ns) (4 * (_ns))
+#define SYMBOL_TIME(_ns) ((_ns) << 2)
+#define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5)
+#define CCK_SIFS_TIME 10
+#define CCK_PREAMBLE_BITS 144
+#define CCK_PLCP_BITS 48
+#define OFDM_SIFS_TIME 16
+#define OFDM_PREAMBLE_TIME 20
+#define OFDM_PLCP_BITS 22
+#define OFDM_SYMBOL_TIME 4
+#define HOUSE_KEEPING_TIMEOUT 100
+#define MAX_RX_IDLE_INTERVAL 3
+#define HOUSE_KEEPING_1_SEC 10
+#define HOUSE_KEEPING_10_SEC 100
+#define WMM_AC_VO 0
+#define WMM_AC_VI 1
+#define WMM_AC_BE 2
+#define WMM_AC_BK 3
+#define WMM_NUM_AC 4
+#define WMM_TID_NUM 8
+#define TXQ_EDCA_0 0x01
+#define TXQ_EDCA_1 0x02
+#define TXQ_EDCA_2 0x04
+#define TXQ_EDCA_3 0x08
+#define TXQ_MGMT 0x10
+#define IS_SSV_HT(dsc) ((dsc)->rate_idx >= 15)
+#define IS_SSV_SHORT_GI(dsc) ((dsc)->rate_idx>=23 && (dsc)->rate_idx<=30)
+#define IS_SSV_HT_GF(dsc) ((dsc)->rate_idx >= 31)
+#define IS_SSV_SHORT_PRE(dsc) ((dsc)->rate_idx>=4 && (dsc)->rate_idx<=14)
+#define RSSI_SMOOTHING_SHIFT 5
+#define RSSI_DECIMAL_POINT_SHIFT 6
+#define SSV_EDCA_SCALE 10
+#define SSV_EDCA_FRAC(_val,_div) (((_val) << SSV_EDCA_SCALE) / _div)
+#define SSV_EDCA_TRUNC(_val) ((_val) >> SSV_EDCA_SCALE)
+#define GET_PRIMARY_EDCA(_sc) SSV_EDCA_TRUNC(_sc->primary_edca_mib * 100)
+#define GET_SECONDARY_EDCA(_sc) SSV_EDCA_TRUNC(_sc->secondary_edca_mib * 100)
+#ifndef SSV_SUPPORT_HAL
+#include "ssv_reg_acc.h"
+#endif
+#define HCI_START(_sh) \
+        ({ \
+            typeof(_sh) __sh = _sh; \
+            __sh->hci.hci_ops->hci_start(__sh->hci.hci_ctrl); \
+        })
+#define HCI_STOP(_sh) \
+        ({ \
+            typeof(_sh) __sh = _sh; \
+            __sh->hci.hci_ops->hci_stop(__sh->hci.hci_ctrl); \
+        })
+#define HCI_WRITE_HW_CONFIG_ON(_sh) \
+        ({ \
+            typeof(_sh) __sh = _sh; \
+            __sh->hci.hci_ops->hci_write_hw_config(__sh->hci.hci_ctrl, 1); \
+        })
+#define HCI_WRITE_HW_CONFIG_OFF(_sh) \
+        ({ \
+            typeof(_sh) __sh = _sh; \
+            __sh->hci.hci_ops->hci_write_hw_config(__sh->hci.hci_ctrl, 0); \
+        })
+#define HCI_SEND(_sh,_sk,_q) \
+        ({ \
+            typeof(_sh) __sh = _sh; \
+            __sh->hci.hci_ops->hci_tx(__sh->hci.hci_ctrl, _sk, _q, 0); \
+        })
+#define HCI_PAUSE(_sh,_mk) \
+        ({ \
+            typeof(_sh) __sh = _sh; \
+            __sh->hci.hci_ops->hci_tx_pause(__sh->hci.hci_ctrl, _mk); \
+        })
+#define HCI_RESUME(_sh,_mk) \
+        ({ \
+            typeof(_sh) __sh = _sh; \
+            __sh->hci.hci_ops->hci_tx_resume(__sh->hci.hci_ctrl, _mk); \
+        })
+#define HCI_TXQ_FLUSH(_sh,_mk) \
+        ({ \
+            typeof(_sh) __sh = _sh; \
+            __sh->hci.hci_ops->hci_txq_flush(__sh->hci.hci_ctrl, _mk); \
+        })
+#define HCI_TXQ_FLUSH_BY_STA(_sh,_aid) \
+        ({ \
+            typeof(_sh) __sh = _sh; \
+            __sh->hci.hci_ops->hci_txq_flush_by_sta(__sh->hci.hci_ctrl, _aid); \
+        })
+#define HCI_TXQ_EMPTY(_sh,_txqid) \
+        ({ \
+            typeof(_sh) __sh = _sh; \
+            __sh->hci.hci_ops->hci_txq_empty(__sh->hci.hci_ctrl, _txqid); \
+        })
+#define HCI_WAKEUP_PMU(_sh) \
+        ({ \
+            typeof(_sh) __sh = _sh; \
+            __sh->hci.hci_ops->hci_pmu_wakeup(__sh->hci.hci_ctrl); \
+        })
+#define HCI_SEND_CMD(_sh,_sk) \
+        ({ \
+            typeof(_sh) __sh = _sh; \
+            __sh->hci.hci_ops->hci_send_cmd(__sh->hci.hci_ctrl, _sk); \
+        })
+#define SSV6XXX_SET_HW_TABLE(sh_,tbl_) \
+({ \
+    int ret = 0; \
+    u32 i=0; \
+    for(; i<sizeof(tbl_)/sizeof(ssv_cabrio_reg); i++) { \
+        ret = SMAC_REG_WRITE(sh_, tbl_[i].address, tbl_[i].data); \
+        if (ret) break; \
+    } \
+    ret; \
+})
+#define SSV6XXX_USE_HW_DECRYPT(_priv) (_priv->has_hw_decrypt)
+#define SSV6XXX_USE_SW_DECRYPT(_priv) (SSV6XXX_USE_LOCAL_SW_DECRYPT(_priv) || SSV6XXX_USE_MAC80211_DECRYPT(_priv))
+#define SSV6XXX_USE_LOCAL_SW_DECRYPT(_priv) (_priv->need_sw_decrypt)
+#define SSV6XXX_USE_MAC80211_DECRYPT(_priv) (_priv->use_mac80211_decrypt)
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0)
+#define RTS_CTS_PROTECT(_flg) \
+    ((_flg)&IEEE80211_TX_RC_USE_RTS_CTS)? 1: \
+    ((_flg)&IEEE80211_TX_RC_USE_CTS_PROTECT)? 2: 0
+#endif
+struct ssv_softc;
+#ifdef CONFIG_P2P_NOA
+struct ssv_p2p_noa;
+#endif
+#define SSV6200_HT_TX_STREAMS 1
+#define SSV6200_HT_RX_STREAMS 1
+#define SSV6200_RX_HIGHEST_RATE 72
+enum PWRSV_STATUS {
+    PWRSV_DISABLE,
+    PWRSV_ENABLE,
+    PWRSV_PREPARE,
+};
+struct aggr_ssn {
+    u16 ssn[MAX_AGGR_NUM];
+    u16 tx_pkt_run_no;
+    u16 mpdu_num;
+    u8 tid_no;
+};
+struct ssv6xxx_calib_table {
+    u16 channel_id;
+    u32 rf_ctrl_N;
+    u32 rf_ctrl_F;
+    u16 rf_precision_default;
+};
+#ifdef SSV_SUPPORT_HAL
+struct ssv_hw;
+struct ssv_sta_priv_data;
+struct ssv_vif_priv_data;
+struct ssv_sta_info;
+struct ssv_vif_info;
+int hw_update_watch_wsid(struct ssv_softc *sc, struct ieee80211_sta *sta,
+                         struct ssv_sta_info *sta_info, int sta_idx, int rx_hw_sec, int ops);
+void _set_wep_sw_crypto_key(struct ssv_softc *sc, struct ssv_vif_info *vif_info,
+                            struct ssv_sta_info *sta_info, void *param);
+typedef enum {
+    CLK_SRC_OSC,
+    CLK_SRC_RTC,
+    CLK_SRC_SYNTH_80M,
+    CLK_SRC_SYNTH_40M,
+    CLK_SRC_MAX,
+} SSV_CLK_SRC;
+struct ssv_hal_ops {
+    void (*adj_config)(struct ssv_hw *sh);
+    bool (*need_sw_cipher)(struct ssv_hw *sh);
+    int (*init_mac)(struct ssv_hw *sh);
+    void (*reset_sysplf)(struct ssv_hw *sh);
+    struct ssv_hw * (*alloc_hw)(void);
+    int (*init_hw_sec_phy_table)(struct ssv_softc *sc);
+    int (*write_mac_ini)(struct ssv_hw *sh);
+    bool (*use_hw_encrypt)(int cipher, struct ssv_softc *sc,
+                           struct ssv_sta_priv_data *sta_priv, struct ssv_vif_priv_data *vif_priv);
+    int (*set_rx_flow)(struct ssv_hw *sh, enum ssv_rx_flow type, u32 rxflow);
+    int (*set_rx_ctrl_flow)(struct ssv_hw *sh);
+    int (*set_macaddr)(struct ssv_hw *sh, int vif_idx);
+    int (*set_bssid)(struct ssv_hw *sh, u8 *bssid, int vif_idx);
+    u64 (*get_ic_time_tag)(struct ssv_hw *sh);
+    void (*get_chip_id)(struct ssv_hw *sh);
+    bool (*if_chk_mac2)(struct ssv_hw *sh);
+    void (*save_hw_status)(struct ssv_softc *sc);
+    void (*pll_chk)(struct ssv_hw *sh);
+    void (*init_gpio_cfg)(struct ssv_hw *sh);
+    int (*get_wsid)(struct ssv_softc *sc, struct ieee80211_vif *vif,
+                    struct ieee80211_sta *sta);
+    void (*set_hw_wsid)(struct ssv_softc *sc, struct ieee80211_vif *vif,
+                        struct ieee80211_sta *sta, int wsid);
+    void (*del_hw_wsid)(struct ssv_softc *sc, int hw_wsid);
+    void (*add_fw_wsid)(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv,
+                        struct ieee80211_sta *sta, struct ssv_sta_info *sta_info);
+    void (*del_fw_wsid)(struct ssv_softc *sc, struct ieee80211_sta *sta,
+                        struct ssv_sta_info *sta_info);
+    void (*enable_fw_wsid)(struct ssv_softc *sc, struct ieee80211_sta *sta,
+                           struct ssv_sta_info *sta_info, enum SSV6XXX_WSID_SEC key_type);
+    void (*disable_fw_wsid)(struct ssv_softc *sc, int key_idx,
+                            struct ssv_sta_priv_data *sta_priv, struct ssv_vif_priv_data *vif_priv);
+    void (*set_fw_hwwsid_sec_type)(struct ssv_softc *sc, struct ieee80211_sta *sta,
+                                   struct ssv_sta_info *sta_info, struct ssv_vif_priv_data *vif_priv);
+    bool (*wep_use_hw_cipher)(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv);
+    bool (*pairwise_wpa_use_hw_cipher)(struct ssv_softc *sc,
+                                       struct ssv_vif_priv_data *vif_priv, enum SSV_CIPHER_E cipher,
+                                       struct ssv_sta_priv_data *sta_priv);
+    bool (*group_wpa_use_hw_cipher)(struct ssv_softc *sc,
+                                    struct ssv_vif_priv_data *vif_priv, enum SSV_CIPHER_E cipher);
+    void (*set_aes_tkip_hw_crypto_group_key) (struct ssv_softc *sc, struct ssv_vif_info *vif_info,
+            struct ssv_sta_info *sta_info, void *param);
+    int (*write_pairwise_key_to_hw) (struct ssv_softc *sc, int index, u8 algorithm, const u8 *key, int key_len,
+                                     struct ieee80211_key_conf *keyconf, struct ssv_vif_priv_data *vif_priv, struct ssv_sta_priv_data *sta_priv);
+    int (*write_group_key_to_hw) (struct ssv_softc *sc, int index, u8 algorithm, const u8 *key, int key_len,
+                                  struct ieee80211_key_conf *keyconf, struct ssv_vif_priv_data *vif_priv, struct ssv_sta_priv_data *sta_priv);
+    void (*write_pairwise_keyidx_to_hw)(struct ssv_hw *sh, int key_idx, int wsid);
+    void (*write_group_keyidx_to_hw)(struct ssv_hw *sh, struct ssv_vif_priv_data *vif_priv, int key_idx);
+    void (*write_key_to_hw)(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv,
+                            void *data_ptr, int wsid, int key_idx, enum SSV6XXX_WSID_SEC key_type);
+    void (*set_group_cipher_type)(struct ssv_hw *sh, struct ssv_vif_priv_data *vif_priv, u8 cipher);
+    void (*set_pairwise_cipher_type)(struct ssv_hw *sh, u8 cipher, u8 wsid);
+    bool (*chk_if_support_hw_bssid)(struct ssv_softc *sc, int vif_idx);
+    void (*chk_dual_vif_chg_rx_flow)(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv);
+    void (*restore_rx_flow)(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv, struct ieee80211_sta *sta);
+    void (*set_wep_hw_crypto_key)(struct ssv_softc *sc, struct ssv_sta_info *sta_info, struct ssv_vif_priv_data *vif_priv);
+    int (*hw_crypto_key_write_wep) (struct ssv_softc *sc, struct ieee80211_key_conf *keyconf, u8 algorithm, struct ssv_vif_info *vif_info);
+    void (*store_wep_key) (struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv, struct ssv_sta_priv_data *sta_priv,
+                           enum SSV_CIPHER_E cipher, struct ieee80211_key_conf *key);
+    bool (*put_mic_space_for_hw_ccmp_encrypt) (struct ssv_softc *sc, struct sk_buff *skb);
+#ifdef CONFIG_PM
+    void (*save_clear_trap_reason)(struct ssv_softc *sc);
+    void (*restore_trap_reason)(struct ssv_softc *sc);
+    void (*pmu_awake)(struct ssv_softc *sc);
+#endif
+    void (*set_replay_ignore)(struct ssv_hw *sh, u8 ignore);
+    void (*update_decision_table_6)(struct ssv_hw *sh, u32 val);
+    int (*update_decision_table)(struct ssv_softc *sc);
+    void (*get_fw_version)(struct ssv_hw *sh, u32 *regval);
+    void (*set_mrx_mode)(struct ssv_hw *sh, u32 regval);
+    void (*get_mrx_mode)(struct ssv_hw *sh, u32 *regval);
+    void (*set_op_mode)(struct ssv_hw *sh, u32 opmode, int vif_idx);
+    void (*set_halt_mngq_util_dtim)(struct ssv_hw *sh, bool val);
+    void (*set_dur_burst_sifs_g)(struct ssv_hw *sh, u32 val);
+    void (*set_dur_slot)(struct ssv_hw *sh, u32 val);
+    void (*set_sifs)(struct ssv_hw *sh, int band);
+    void (*set_qos_enable)(struct ssv_hw *sh, bool val);
+    void (*set_wmm_param)(struct ssv_softc *sc,
+                          const struct ieee80211_tx_queue_params *params, u16 queue);
+    void (*update_page_id)(struct ssv_hw *sh);
+    void (*init_tx_cfg)(struct ssv_hw *sh);
+    void (*init_rx_cfg)(struct ssv_hw *sh);
+    u32 (*alloc_pbuf)(struct ssv_softc *sc, int size, int type);
+    bool (*free_pbuf)(struct ssv_softc *sc, u32 pbuf_addr);
+    void (*ampdu_auto_crc_en)(struct ssv_hw *sh);
+    void (*set_rx_ba)(struct ssv_hw *sh, bool on, u8 *ta,
+                      u16 tid, u16 ssn, u8 buf_size);
+    u8 (*read_efuse)(struct ssv_hw *sh, u8 *pbuf);
+    void (*write_efuse)(struct ssv_hw *sh, u8 *data, u8 data_length);
+    int (*chg_clk_src)(struct ssv_hw *sh);
+    int (*update_efuse_setting)(struct ssv_hw *sh);
+    void (*do_temperature_compensation)(struct ssv_hw *sh);
+    void (*update_product_hw_setting)(struct ssv_hw *sh);
+    enum ssv6xxx_beacon_type (*beacon_get_valid_cfg)(struct ssv_hw *sh);
+    void (*set_beacon_reg_lock)(struct ssv_hw *sh, bool val);
+    void (*set_beacon_id_dtim)(struct ssv_softc *sc,
+                               enum ssv6xxx_beacon_type avl_bcn_type, int dtim_offset);
+    void (*fill_beacon)(struct ssv_softc *sc, u32 regaddr, struct sk_buff *skb);
+    bool (*beacon_enable)(struct ssv_softc *sc, bool bEnable);
+    void (*set_beacon_info)(struct ssv_hw *sh, u8 beacon_interval, u8 dtim_cnt);
+    bool (*get_bcn_ongoing)(struct ssv_hw *sh);
+    void (*beacon_loss_enable)(struct ssv_hw *sh);
+    void (*beacon_loss_disable)(struct ssv_hw *sh);
+    void (*beacon_loss_config)(struct ssv_hw *sh, u16 beacon_interval, const u8 *bssid);
+    void (*update_txq_mask)(struct ssv_hw *sh, u32 txq_mask);
+    void (*readrg_hci_inq_info)(struct ssv_hw *sh, int *hci_used_id, int *tx_use_page);
+    bool (*readrg_txq_info)(struct ssv_hw *sh, u32 *txq_info, int *hci_used_id);
+    bool (*readrg_txq_info2)(struct ssv_hw *sh, u32 *txq_info2, int *hci_used_id);
+    bool (*dump_wsid)(struct ssv_hw *sh);
+    bool (*dump_decision)(struct ssv_hw *sh);
+    u32 (*get_ffout_cnt)(u32 value, int tag);
+    u32 (*get_in_ffcnt)(u32 value, int tag);
+    void (*read_ffout_cnt)(struct ssv_hw *sh, u32 *value, u32 *value1, u32 *value2);
+    void (*read_in_ffcnt)(struct ssv_hw *sh, u32 *value, u32 *value1);
+    void (*read_id_len_threshold)(struct ssv_hw *sh, u32 *tx_len, u32 *rx_len);
+    void (*read_tag_status)(struct ssv_hw *sh, u32 *ava_status);
+    void (*cmd_mib)(struct ssv_softc *sc, int argc, char *argv[]);
+    void (*cmd_power_saving)(struct ssv_softc *sc, int argc, char *argv[]);
+    void (*cmd_hwinfo)(struct ssv_hw *sh, int argc, char *argv[]);
+    void (*cmd_cci)(struct ssv_hw *sh, int argc, char *argv[]);
+    void (*cmd_txgen)(struct ssv_hw *sh);
+    void (*cmd_rf)(struct ssv_hw *sh, int argc, char *argv[]);
+    void (*update_rf_pwr)(struct ssv_softc *sc);
+    void (*cmd_efuse)(struct ssv_hw *sh, int argc, char *argv[]);
+    void (*cmd_spectrum)(struct ssv_hw *sh);
+    void (*cmd_hwq_limit)(struct ssv_hw *sh, int argc, char *argv[]);
+    void (*get_rd_id_adr)(u32 *id_base_address);
+    int (*burst_read_reg)(struct ssv_hw *sh, u32 *addr, u32 *buf, u8 reg_amount);
+    int (*burst_write_reg)(struct ssv_hw *sh, u32 *addr, u32 *buf, u8 reg_amount);
+    int (*auto_gen_nullpkt)(struct ssv_hw *sh, int hwq);
+    void (*cmd_cali)(struct ssv_hw *sh, int argc, char *argv[]);
+    void (*load_fw_enable_mcu)(struct ssv_hw *sh);
+    int (*load_fw_disable_mcu)(struct ssv_hw *sh);
+    int (*load_fw_set_status)(struct ssv_hw *sh, u32 status);
+    int (*load_fw_get_status)(struct ssv_hw *sh, u32 *status);
+    void (*load_fw_pre_config_device)(struct ssv_hw *sh);
+    void (*load_fw_post_config_device)(struct ssv_hw *sh);
+    int (*reset_cpu)(struct ssv_hw *sh);
+    void (*set_sram_mode)(struct ssv_hw *sh, enum SSV_SRAM_MODE mode);
+    void (*enable_usb_acc)(struct ssv_softc *sc, u8 epnum);
+    void (*disable_usb_acc)(struct ssv_softc *sc, u8 epnum);
+    void (*set_usb_lpm)(struct ssv_softc *sc, u8 enable);
+    int (*jump_to_rom)(struct ssv_softc *sc);
+    void (*get_fw_name)(u8 *fw_name);
+    void (*send_tx_poll_cmd)(struct ssv_hw *sh, u32 type);
+    void (*flash_read_all_map)(struct ssv_hw *sh);
+    void (*wait_usb_rom_ready)(struct ssv_hw *sh);
+    void (*detach_usb_hci)(struct ssv_hw *sh);
+    void (*add_txinfo) (struct ssv_softc *sc, struct sk_buff *skb);
+    void (*update_txinfo)(struct ssv_softc *sc, struct sk_buff *skb);
+    void (*update_ampdu_txinfo)(struct ssv_softc *sc, struct sk_buff *ampdu_skb);
+    void (*add_ampdu_txinfo)(struct ssv_softc *sc, struct sk_buff *ampdu_skb);
+    int (*update_null_func_txinfo)(struct ssv_softc *sc, struct ieee80211_sta *sta, struct sk_buff *skb);
+    int (*get_tx_desc_size)(struct ssv_hw *sh);
+    int (*get_tx_desc_ctype)(struct sk_buff *skb );
+    int (*get_tx_desc_reason)(struct sk_buff *skb );
+    int (*get_tx_desc_txq_idx)(struct sk_buff *skb );
+    void (*tx_rate_update)(struct ssv_softc *sc, struct sk_buff *skb);
+    void (*txtput_set_desc)(struct ssv_hw *sh, struct sk_buff *skb );
+    void (*fill_beacon_tx_desc)(struct ssv_softc *sc, struct sk_buff* beacon_skb);
+    void (*fill_lpbk_tx_desc)(struct sk_buff *skb, int security, unsigned char rate);
+    int (*get_sec_decode_err)(struct sk_buff *skb, bool *mic_err, bool *decode_err);
+    int (*get_rx_desc_size)(struct ssv_hw *sh);
+    int (*get_rx_desc_length)(struct ssv_hw *sh);
+    u32 (*get_rx_desc_wsid)(struct sk_buff *skb);
+    u32 (*get_rx_desc_rate_idx)(struct sk_buff *skb);
+    u32 (*get_rx_desc_mng_used)(struct sk_buff *skb);
+    bool (*is_rx_aggr)(struct sk_buff *skb);
+    u32 (*get_rx_desc_ctype)(struct sk_buff *skb);
+    int (*get_rx_desc_hdr_offset)(struct sk_buff *skb);
+    int (*chk_lpbk_rx_rate_desc)(struct ssv_hw *sh, struct sk_buff *skb);
+    void (*get_rx_desc_info)(struct sk_buff *skb, u32 *packet_len, u32 *ctype,
+                             u32 *_tx_pkt_run_no);
+    bool (*nullfun_frame_filter)(struct sk_buff *skb);
+    void (*set_phy_mode)(struct ssv_hw *sh, bool val);
+    void (*phy_enable)(struct ssv_hw *sh, bool val);
+    void (*edca_enable)(struct ssv_hw *sh, bool val);
+    void (*edca_stat)(struct ssv_hw *sh);
+    void (*reset_mib_phy)(struct ssv_hw *sh);
+    void (*dump_mib_rx_phy)(struct ssv_hw *sh);
+    void (*rc_algorithm)(struct ssv_softc *sc);
+    void (*set_80211_hw_rate_config)(struct ssv_softc *sc);
+    void (*rc_legacy_bitrate_to_rate_desc)(int bitrate, u8 *drate);
+    void (*rc_rx_data_handler)(struct ssv_softc *sc, struct sk_buff *skb, u32 rate_index);
+    void (*rate_report_handler)(struct ssv_softc *sc, struct sk_buff *skb, bool *no_ba_result);
+    void (*rc_process_rate_report)(struct ssv_softc *sc, struct sk_buff *skb);
+    void (*rc_update_basic_rate)(struct ssv_softc *sc, u32 basic_rates);
+    s32 (*rc_ht_update_rate)(struct sk_buff *skb, struct ssv_softc *sc, struct fw_rc_retry_params *ar);
+    bool (*rc_ht_sta_current_rate_is_cck)(struct ieee80211_sta *sta);
+    void (*rc_mac80211_rate_idx)(struct ssv_softc *sc,
+                                 int hw_rate_idx, struct ieee80211_rx_status *rxs);
+    void (*update_rxstatus)(struct ssv_softc *sc,
+                            struct sk_buff *rx_skb, struct ieee80211_rx_status *rxs);
+#ifdef CONFIG_SSV_CCI_IMPROVEMENT
+    void (*update_scan_cci_setting)(struct ssv_softc *sc);
+    void (*recover_scan_cci_setting)(struct ssv_softc *sc);
+#endif
+    void (*cmd_rc)(struct ssv_hw *sh, int argc, char *argv[]);
+    void (*cmd_loopback)(struct ssv_hw *sh, int argc, char *argv[]);
+    void (*cmd_loopback_start)(struct ssv_hw *sh);
+    void (*cmd_loopback_setup_env)(struct ssv_hw *sh);
+    int (*ampdu_rx_start)(struct ieee80211_hw *hw, struct ieee80211_vif *vif, struct ieee80211_sta *sta,
+                          u16 tid, u16 *ssn, u8 buf_size);
+    void (*ampdu_ba_handler)(struct ieee80211_hw *hw, struct sk_buff *skb, u32 tx_pkt_run_no);
+    bool (*is_legacy_rate)(struct ssv_softc *sc, struct sk_buff *skb);
+    int (*ampdu_max_transmit_length)(struct ssv_softc *sc, struct sk_buff *skb, int rate_idx);
+    void (*load_phy_table)(ssv_cabrio_reg **phy_table);
+    u32 (*get_phy_table_size)(struct ssv_hw *sh);
+    void (*load_rf_table)(ssv_cabrio_reg **rf_table);
+    u32 (*get_rf_table_size)(struct ssv_hw *sh);
+    void (*init_pll)(struct ssv_hw *sh);
+    void (*update_cfg_hw_patch)(struct ssv_hw *sh, ssv_cabrio_reg *rf_table,
+                                ssv_cabrio_reg *phy_table);
+    void (*update_hw_config)(struct ssv_hw *sh, ssv_cabrio_reg *rf_table,
+                             ssv_cabrio_reg *phy_table);
+    int (*chg_pad_setting)(struct ssv_hw *sh);
+    int (*set_channel)(struct ssv_softc *sc, struct ieee80211_channel *channel, enum nl80211_channel_type);
+    int (*do_iq_cal)(struct ssv_hw *sh, struct ssv6xxx_iqk_cfg *p_cfg);
+    int (*set_pll_phy_rf)(struct ssv_hw *sh, ssv_cabrio_reg *rf_tbl, ssv_cabrio_reg *phy_tbl);
+    void (*dpd_enable)(struct ssv_hw *sh, bool val);
+    void (*init_ch_cfg)(struct ssv_hw *sh);
+    void (*init_iqk)(struct ssv_hw *sh);
+    void (*save_default_ipd_chcfg)(struct ssv_hw *sh);
+    void (*chg_ipd_phyinfo)(struct ssv_hw *sh);
+    bool (*set_rf_enable)(struct ssv_hw *sh, bool val);
+    bool (*dump_phy_reg)(struct ssv_hw *sh);
+    bool (*dump_rf_reg)(struct ssv_hw *sh);
+    bool (*support_iqk_cmd)(struct ssv_hw *sh);
+    void (*set_on3_enable)(struct ssv_hw *sh, bool val);
+};
+#endif
+struct ssv6xxx_umac_ops {
+    int (*umac_rx_raw)(struct sk_buff *);
+};
+struct ssv_hw_cfg {
+    u32 addr;
+    u32 value;
+    struct list_head list;
+};
+#define PADPDBAND 5
+#define MAX_PADPD_TONE 26
+struct ssv6006dpd {
+    u32 am[MAX_PADPD_TONE/2];
+    u32 pm[MAX_PADPD_TONE/2];
+};
+#define NORMAL_PWR 0
+#define ENHANCE_PWR 1
+#define GREEN_PWR 1
+struct ssv6006_padpd {
+    bool dpd_done[PADPDBAND];
+    bool dpd_disable[PADPDBAND];
+    bool pwr_mode;
+    bool spur_patched;
+    u8 current_band;
+    struct ssv6006dpd val[PADPDBAND];
+    u8 bbscale[PADPDBAND];
+};
+struct ssv6006_cal_result {
+    bool cal_done;
+    bool cal_iq_done[PADPDBAND];
+    u32 rxdc_2g[21];
+    u8 rxrc_bw20;
+    u8 rxrc_bw40;
+    u8 txdc_i_2g;
+    u8 txdc_q_2g;
+    u32 rxdc_5g[21];
+    u8 rxiq_alpha[PADPDBAND];
+    u8 rxiq_theta[PADPDBAND];
+    u8 txdc_i_5g;
+    u8 txdc_q_5g;
+    u8 txiq_alpha[PADPDBAND];
+    u8 txiq_theta[PADPDBAND];
+};
+struct ssv_tempe_table {
+    u8 g_band_gain[7];
+    u8 a_band_gain[4];
+    u16 xtal_offset;
+};
+struct ssv_flash_config {
+    bool exist;
+    struct ssv_tempe_table rt_config;
+    struct ssv_tempe_table ht_config;
+    struct ssv_tempe_table lt_config;
+    u8 xtal_offset_tempe_state;
+    u8 xtal_offset_low_boundary;
+    u8 xtal_offset_high_boundary;
+    u8 band_gain_tempe_state;
+    u8 band_gain_low_boundary;
+    u8 band_gain_high_boundary;
+    int chan;
+    u16 dcdc;
+    u16 padpd;
+    u32 g_band_pa_bias0;
+    u32 g_band_pa_bias1;
+    u32 a_band_pa_bias0;
+    u32 a_band_pa_bias1;
+    u8 rate_delta[13];
+};
+struct ssv_hw {
+    struct ssv_softc *sc;
+    struct ssv6xxx_platform_data *priv;
+    struct ssv6xxx_hci_info hci;
+    char chip_id[SSV6XXX_CHIP_ID_LENGTH];
+    u64 chip_tag;
+#ifdef SSV_SUPPORT_HAL
+    struct ssv_hal_ops hal_ops;
+#endif
+    u32 efuse_bitmap;
+    u32 tx_desc_len;
+    u32 rx_desc_len;
+    u32 rx_pinfo_pad;
+    u32 tx_page_available;
+    u32 ampdu_divider;
+    struct ssv6xxx_tx_hw_info tx_info;
+    struct ssv6xxx_rx_hw_info rx_info;
+#ifdef SSV6200_ECO
+    u32 hw_buf_ptr[SSV_RC_MAX_STA];
+    u32 hw_sec_key[SSV_RC_MAX_STA];
+#else
+    u32 hw_buf_ptr;
+    u32 hw_sec_key;
+#endif
+    u32 hw_pinfo;
+    struct ssv6xxx_cfg cfg;
+    struct ssv_flash_config flash_config;
+    u32 n_addresses;
+    struct mac_address maddr[SSV6200_MAX_HW_MAC_ADDR];
+    u8 ipd_channel_touch;
+    struct ssv6xxx_ch_cfg *p_ch_cfg;
+    u32 ch_cfg_size;
+    int rx_mode;
+    int rx_burstread_size_type;
+    int rx_burstread_cnt;
+    u8 *page_count;
+    struct list_head hw_cfg;
+    struct mutex hw_cfg_mutex;
+    void (*write_hw_config_cb)(void *param, u32 addr, u32 value);
+    void *write_hw_config_args;
+    struct ssv6xxx_iqk_cfg iqk_cfg;
+    u8 default_txgain[PADPDBAND];
+    struct ssv6006_cal_result cal;
+};
+struct ssv_tx {
+    u16 seq_no;
+    int hw_txqid[WMM_NUM_AC];
+    int ac_txqid[WMM_NUM_AC];
+    u32 flow_ctrl_status;
+    u32 tx_pkt[SSV_HW_TXQ_NUM];
+    u32 tx_frag[SSV_HW_TXQ_NUM];
+    struct list_head ampdu_tx_que;
+    spinlock_t ampdu_tx_que_lock;
+    u16 ampdu_tx_group_id;
+};
+struct ssv_rx {
+    struct sk_buff *rx_buf;
+    spinlock_t rxq_lock;
+    struct sk_buff_head rxq_head;
+    u32 rxq_count;
+};
+#ifdef MULTI_THREAD_ENCRYPT
+struct ssv_encrypt_task_list {
+    struct task_struct* encrypt_task;
+    wait_queue_head_t encrypt_wait_q;
+    volatile int started;
+    volatile int running;
+    volatile int paused;
+    volatile int cpu_offline;
+    u32 cpu_no;
+    struct list_head list;
+};
+#endif
+#define SSV6XXX_GET_STA_INFO(_sc,_s) \
+    &(_sc)->sta_info[((struct ssv_sta_priv_data *)((_s)->drv_priv))->sta_idx]
+#define STA_FLAG_VALID 0x00001
+#define STA_FLAG_QOS 0x00002
+#define STA_FLAG_AMPDU 0x00004
+#define STA_FLAG_ENCRYPT 0x00008
+#define STA_FLAG_AMPDU_RX 0x00010
+struct ssv_sta_info {
+    u16 aid;
+    u16 s_flags;
+    int hw_wsid;
+    struct ieee80211_sta *sta;
+    struct ieee80211_vif *vif;
+    bool tim_set;
+#if 0
+    struct ssv_crypto_ops *crypt;
+    void *crypt_priv;
+    u32 KeySelect;
+    bool ampdu_ccmp_encrypt;
+#endif
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+    struct dentry *debugfs_dir;
+#endif
+};
+struct ssv_vif_info {
+    struct ieee80211_vif *vif;
+    struct ssv_vif_priv_data *vif_priv;
+    enum nl80211_iftype if_type;
+    struct ssv6xxx_hw_sec sramKey;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+    struct dentry *debugfs_dir;
+#endif
+};
+struct rx_stats {
+    u64 n_pkts[8];
+    u64 g_pkts[8];
+    u64 cck_pkts[4];
+    u8 phy_mode;
+    u8 ht40;
+};
+struct ssv_sta_priv_data {
+    int sta_idx;
+    int rc_idx;
+    int rx_data_rate;
+    struct ssv_sta_info *sta_info;
+    struct list_head list;
+    u32 ampdu_mib_total_BA_counter;
+    AMPDU_TID ampdu_tid[WMM_TID_NUM];
+    bool has_hw_encrypt;
+    bool need_sw_encrypt;
+    bool has_hw_decrypt;
+    bool need_sw_decrypt;
+    bool use_mac80211_decrypt;
+    u8 group_key_idx;
+#ifdef USE_LOCAL_CRYPTO
+    struct ssv_crypto_data crypto_data;
+#endif
+    u32 beacon_rssi;
+    struct aggr_ssn ampdu_ssn[MAX_CONCUR_AMPDU];
+    void *rc_info;
+    struct rx_stats rxstats;
+    u32 retry_samples[16];
+    u16 max_ampdu_size;
+};
+struct wep_hw_key {
+    u8 keylen;
+    u8 key[SECURITY_KEY_LEN];
+};
+struct ssv_vif_priv_data {
+    int vif_idx;
+    struct list_head sta_list;
+    u32 sta_asleep_mask;
+    u32 pair_cipher;
+    u32 group_cipher;
+    bool is_security_valid;
+    bool has_hw_encrypt;
+    bool need_sw_encrypt;
+    bool has_hw_decrypt;
+    bool need_sw_decrypt;
+    bool use_mac80211_decrypt;
+    bool force_sw_encrypt;
+    u8 group_key_idx;
+    s8 wep_idx;
+    int wep_cipher;
+#ifdef USE_LOCAL_CRYPTO
+    struct ssv_crypto_data crypto_data;
+#endif
+};
+#define SC_OP_DEV_READY BIT(0)
+#define SC_OP_HW_RESET BIT(1)
+#define SC_OP_OFFCHAN BIT(2)
+#define SC_OP_FIXED_RATE BIT(3)
+#define SC_OP_SHORT_PREAMBLE BIT(4)
+#define SC_OP_CTS_PROT BIT(5)
+#define SC_OP_DIRECTLY_ACK BIT(6)
+#define SC_OP_BLOCK_CNTL BIT(7)
+#define SC_OP_CHAN_FIXED BIT(8)
+#define IS_ALLOW_SCAN (sc->p2p_status)
+#define IS_NON_AP_MODE (sc->ap_vif == NULL)
+#define IS_NONE_STA_CONNECTED_IN_AP_MODE (list_empty(&((struct ssv_vif_priv_data *)sc->ap_vif->drv_priv)->sta_list))
+#define IS_MGMT_AND_BLOCK_CNTL(_sc,_hdr) ((sc->sc_flags & SC_OP_BLOCK_CNTL) && (ieee80211_is_mgmt(_hdr->frame_control)))
+struct ssv6xxx_beacon_info {
+    u32 pubf_addr;
+    u16 len;
+    u8 tim_offset;
+    u8 tim_cnt;
+};
+#define SSV6200_MAX_BCAST_QUEUE_LEN 16
+struct ssv6xxx_bcast_txq {
+    spinlock_t txq_lock;
+    struct sk_buff_head qhead;
+    int cur_qsize;
+};
+#ifdef DEBUG_AMPDU_FLUSH
+typedef struct AMPDU_TID_st AMPDU_TID;
+#define MAX_TID (24)
+#endif
+struct _ssv6xxx_txtput {
+    struct task_struct *txtput_tsk;
+    struct sk_buff *skb;
+    u32 size_per_frame;
+    u32 loop_times;
+    u32 occupied_tx_pages;
+};
+struct ssv_softc {
+    struct ieee80211_hw *hw;
+    struct device *dev;
+    struct platform_device *platform_dev;
+    bool force_disable_directly_ack_tx;
+    u32 restart_counter;
+    bool force_triger_reset;
+    struct work_struct hw_restart_work;
+    unsigned long sdio_throughput_timestamp;
+    unsigned long sdio_rx_evt_size;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,7,0)
+    struct ieee80211_supported_band sbands[NUM_NL80211_BANDS];
+#else
+    struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
+#endif
+    struct ieee80211_channel *cur_channel;
+    u16 hw_chan;
+    u16 hw_chan_type;
+    struct mutex mutex;
+    struct ssv_hw *sh;
+    struct ssv_tx tx;
+    struct ssv_rx rx;
+    struct ssv_vif_info vif_info[SSV_NUM_VIF];
+    struct ssv_sta_info sta_info[SSV_NUM_STA];
+    struct ieee80211_vif *ap_vif;
+    u8 nvif;
+    u32 sc_flags;
+    bool mac80211_dev_started;
+    void *rc;
+    int max_rate_idx;
+    struct workqueue_struct *rc_report_workqueue;
+    struct sk_buff_head rc_report_queue;
+    struct work_struct rc_report_work;
+#ifdef DEBUG_AMPDU_FLUSH
+    struct AMPDU_TID_st *tid[MAX_TID];
+#endif
+    u16 rc_report_sechedule;
+    u16 *mac_deci_tbl;
+    struct workqueue_struct *config_wq;
+    bool bq4_dtim;
+    struct work_struct set_tim_work;
+    u8 enable_beacon;
+    u8 beacon_interval;
+    u8 beacon_dtim_cnt;
+    u8 beacon_usage;
+    struct ssv6xxx_beacon_info beacon_info[2];
+    struct sk_buff *beacon_buf;
+    struct work_struct beacon_miss_work;
+    struct sk_buff *beacon_container;
+    unsigned long beacon_container_update_time;
+    struct work_struct bcast_start_work;
+    struct delayed_work bcast_stop_work;
+    struct delayed_work bcast_tx_work;
+    bool aid0_bit_set;
+    u8 hw_mng_used;
+    struct ssv6xxx_bcast_txq bcast_txq;
+    int bcast_interval;
+    u8 bssid[2][6];
+    struct mutex mem_mutex;
+    spinlock_t ps_state_lock;
+    u8 hw_wsid_bit;
+    bool ccmp_h_sel;
+#if 0
+    struct work_struct ampdu_tx_encry_work;
+    bool ampdu_encry_work_scheduled;
+    bool ampdu_ccmp_encrypt;
+    struct work_struct sync_hwkey_work;
+    bool sync_hwkey_write;
+    struct ssv_sta_info *key_sync_sta_info;
+    AMPDU_REKEY_PAUSE_STATE ampdu_rekey_pause;
+#endif
+    int rx_ba_session_count;
+    struct ieee80211_sta *rx_ba_sta;
+    u8 rx_ba_bitmap;
+    u8 ba_ra_addr[ETH_ALEN];
+    u16 ba_tid;
+    u16 ba_ssn;
+    struct work_struct set_ampdu_rx_add_work;
+    struct work_struct set_ampdu_rx_del_work;
+    bool isAssoc;
+    u16 channel_center_freq;
+    u8 p2p_status;
+    bool bScanning;
+    int ps_status;
+    u16 ps_aid;
+#ifdef CONFIG_SSV_SUPPORT_ANDROID
+#ifdef CONFIG_HAS_EARLYSUSPEND
+    struct early_suspend early_suspend;
+#endif
+#ifdef CONFIG_HAS_WAKELOCK
+    struct wake_lock ssv_wake_lock_;
+#endif
+#endif
+    u16 tx_wait_q_woken;
+    wait_queue_head_t tx_wait_q;
+    struct sk_buff_head tx_skb_q;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+    u32 max_tx_skb_q_len;
+#endif
+    struct task_struct *tx_task;
+    bool tx_q_empty;
+    struct sk_buff_head tx_done_q;
+    u16 rx_wait_q_woken;
+    wait_queue_head_t rx_wait_q;
+    struct sk_buff_head rx_skb_q;
+    struct task_struct *rx_task;
+#ifdef MULTI_THREAD_ENCRYPT
+    struct list_head encrypt_task_head;
+    struct notifier_block cpu_nfb;
+    struct sk_buff_head preprocess_q;
+    struct sk_buff_head crypted_q;
+    spinlock_t crypt_st_lock;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+    u32 max_preprocess_q_len;
+    u32 max_crypted_q_len;
+#endif
+#endif
+    bool dbg_rx_frame;
+    bool dbg_tx_frame;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+    struct dentry *debugfs_dir;
+#endif
+#ifdef CONFIG_P2P_NOA
+    struct ssv_p2p_noa p2p_noa;
+#endif
+    u32 log_ctrl;
+    struct ssv_cmd_data cmd_data;
+#ifdef CONFIG_PM
+    struct ssv_trap_data trap_data;
+#endif
+    struct ssv6xxx_umac_ops *umac;
+    struct ssv6006_padpd dpd;
+    u8 green_pwr;
+    u8 current_pwr;
+    u8 gt_channel;
+    u8 default_pwr;
+    bool gt_enabled;
+    u8 tx_pkt_run_no;
+    spinlock_t tx_pkt_run_no_lock;
+    wait_queue_head_t fw_wait_q;
+    u32 iq_cali_done;
+    struct rw_semaphore sta_info_sem;
+#ifdef CONFIG_SMARTLINK
+    u32 ssv_smartlink_status;
+    u32 ssv_usr_pid;
+#endif
+#ifdef CONFIG_SSV_CCI_IMPROVEMENT
+    u32 pre_11b_cca_control;
+    u32 pre_11b_cca_1;
+    u32 pre_11b_rx_abbctune;
+    unsigned long cci_last_jiffies;
+    u32 cci_current_level;
+    u32 cci_current_gate;
+    bool cci_set;
+    bool cci_start;
+    bool cci_modified;
+    u8 cci_rx_unavailable_counter;
+#endif
+    u8 ack_counter;
+    struct timer_list house_keeping;
+    struct workqueue_struct *house_keeping_wq;
+    struct work_struct rx_stuck_work;
+    int rx_stuck_idle_time;
+    unsigned long rx_stuck_reset_time;
+    struct work_struct mib_edca_work;
+    int primary_edca_mib;
+    int secondary_edca_mib;
+    bool lpbk_enable;
+    int lpbk_tx_pkt_cnt;
+    int lpbk_rx_pkt_cnt;
+    int lpbk_err_cnt;
+    struct work_struct tx_poll_work;
+#ifdef CONFIG_SSV_CCI_IMPROVEMENT
+    struct work_struct cci_clean_work;
+    struct work_struct cci_set_work;
+#endif
+    struct work_struct set_txpwr_work;
+    bool thermal_monitor;
+    int thermal_monitor_counter;
+    struct work_struct thermal_monitor_work;
+    u8 rf_rc;
+    struct _ssv6xxx_txtput ssv_txtput;
+    atomic_t ampdu_tx_frame;
+    int directly_ack_low_threshold;
+    int directly_ack_high_threshold;
+    bool rx_data_exist;
+};
+enum {
+    IQ_CALI_RUNNING,
+    IQ_CALI_OK,
+    IQ_CALI_FAILED
+};
+void ssv6xxx_txbuf_free_skb(struct sk_buff *skb, void *args);
+void ssv6200_rx_process(struct work_struct *work);
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+int ssv6200_rx(struct sk_buff_head *rx_skb_q, void *args);
+#else
+int ssv6200_rx(struct sk_buff *rx_skb, void *args);
+#endif
+int ssv6200_is_rx_q_full(void *args);
+void ssv6xxx_post_tx_cb(struct sk_buff_head *skb_head, void *args);
+void ssv6xxx_pre_tx_cb(struct sk_buff *skb, void *args);
+void ssv6xxx_tx_rate_update(struct sk_buff *skb, void *args);
+int ssv6200_tx_flow_control(void *dev, int hw_txqid, bool fc_en, int debug);
+void ssv6xxx_tx_q_empty_cb (u32 txq_no, void *);
+#ifndef SSV_SUPPORT_HAL
+int ssv6xxx_rf_disable(struct ssv_hw *sh);
+int ssv6xxx_rf_enable(struct ssv_hw *sh);
+int ssv6xxx_set_channel(struct ssv_softc *sc, struct ieee80211_channel *channel, enum nl80211_channel_type);
+int ssv6xxx_set_on3_enable(struct ssv_hw *sh, bool val);
+#define HAL_SET_CHANNEL(_sc,_ch,_type) ssv6xxx_set_channel(_sc, _ch, _type)
+#endif
+#ifdef CONFIG_SMARTLINK
+int ssv6xxx_get_channel(struct ssv_softc *sc, int *pch);
+int ssv6xxx_set_promisc(struct ssv_softc *sc, int accept);
+int ssv6xxx_get_promisc(struct ssv_softc *sc, int *paccept);
+#endif
+int ssv6xxx_tx_task (void *data);
+int ssv6xxx_rx_task (void *data);
+void ssv6xxx_house_keeping(unsigned long argv);
+void ssv6xxx_rx_stuck_process(struct work_struct *work);
+void ssv6xxx_mib_edca_process(struct work_struct *work);
+void ssv6xxx_tx_poll_process(struct work_struct *work);
+void ssv6xxx_cci_clean_process(struct work_struct *work);
+void ssv6xxx_cci_set_process(struct work_struct *work);
+void ssv6xxx_set_txpwr_process(struct work_struct *work);
+void ssv6xxx_thermal_monitor_process(struct work_struct *work);
+#ifndef SSV_SUPPORT_HAL
+u32 ssv6xxx_pbuf_alloc(struct ssv_softc *sc, int size, int type);
+bool ssv6xxx_pbuf_free(struct ssv_softc *sc, u32 pbuf_addr);
+void ssv6xxx_add_txinfo(struct ssv_softc *sc, struct sk_buff *skb);
+void ssv6xxx_update_txinfo (struct ssv_softc *sc, struct sk_buff *skb);
+int ssv6xxx_update_decision_table(struct ssv_softc *sc);
+#endif
+void ssv6xxx_rc_report_work(struct work_struct *work);
+void ssv6xxx_ps_callback_func(unsigned long data);
+void ssv6xxx_enable_ps(struct ssv_softc *sc);
+void ssv6xxx_disable_ps(struct ssv_softc *sc);
+int ssv6xxx_skb_encrypt(struct sk_buff *mpdu,struct ssv_softc *sc);
+int ssv6xxx_skb_decrypt(struct sk_buff *mpdu, struct ieee80211_sta *sta,struct ssv_softc *sc);
+void ssv6200_sync_hw_key_sequence(struct ssv_softc *sc, struct ssv_sta_info* sta_info, bool bWrite);
+struct ieee80211_sta *ssv6xxx_find_sta_by_rx_skb (struct ssv_softc *sc, struct sk_buff *skb);
+struct ieee80211_sta *ssv6xxx_find_sta_by_addr (struct ssv_softc *sc, u8 addr[6]);
+void ssv6xxx_foreach_sta (struct ssv_softc *sc,
+                          void (*sta_func)(struct ssv_softc *,
+                                  struct ssv_sta_info *,
+                                  void *),
+                          void *param);
+void ssv6xxx_foreach_vif_sta (struct ssv_softc *sc,
+                              struct ssv_vif_info *vif_info,
+                              void (*sta_func)(struct ssv_softc *,
+                                      struct ssv_vif_info *,
+                                      struct ssv_sta_info *,
+                                      void *),
+                              void *param);
+#ifdef CONFIG_SSV_SUPPORT_ANDROID
+#ifdef CONFIG_HAS_EARLYSUSPEND
+void ssv6xxx_early_suspend(struct early_suspend *h);
+void ssv6xxx_late_resume(struct early_suspend *h);
+#endif
+#endif
+#ifdef USE_LOCAL_CRYPTO
+#ifdef MULTI_THREAD_ENCRYPT
+struct ssv_crypto_data *ssv6xxx_skb_get_tx_cryptops(struct sk_buff *mpdu);
+struct ssv_crypto_data *ssv6xxx_skb_get_rx_cryptops(struct ssv_softc *sc,
+        struct ieee80211_sta *sta,
+        struct sk_buff *mpdu);
+int ssv6xxx_skb_pre_encrypt(struct sk_buff *mpdu, struct ssv_softc *sc);
+int ssv6xxx_skb_pre_decrypt(struct sk_buff *mpdu, struct ieee80211_sta *sta, struct ssv_softc *sc);
+int ssv6xxx_encrypt_task (void *data);
+#endif
+#ifdef HAS_CRYPTO_LOCK
+#define INIT_WRITE_CRYPTO_DATA(data, init) \
+        struct ssv_crypto_data *data = (init); \
+        unsigned long data##_flags;
+#define START_WRITE_CRYPTO_DATA(data) \
+        do { \
+            write_lock_irqsave(&(data)->lock, data##_flags); \
+        } while (0)
+#define END_WRITE_CRYPTO_DATA(data) \
+        do { \
+            write_unlock_irqrestore(&(data)->lock, data##_flags); \
+        } while (0)
+#define START_READ_CRYPTO_DATA(data) \
+        do { \
+            read_lock(&(data)->lock); \
+        } while (0)
+#define END_READ_CRYPTO_DATA(data) \
+        do { \
+            read_unlock(&(data)->lock); \
+        } while (0)
+#else
+#define INIT_WRITE_CRYPTO_DATA(data, init) \
+        struct ssv_crypto_data *data = (init);
+#define START_WRITE_CRYPTO_DATA(data) do { } while (0)
+#define END_WRITE_CRYPTO_DATA(data) do { } while (0)
+#define START_READ_CRYPTO_DATA(data) do { } while (0)
+#define END_READ_CRYPTO_DATA(data) do { } while (0)
+#endif
+#endif
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ssize_t ssv6xxx_tx_queue_status_dump (struct ssv_softc *sc, char *status_buf,
+                                      ssize_t buf_size);
+#endif
+#ifdef SSV_SUPPORT_HAL
+#define SSV_UPDATE_PAGE_ID(_sh) HAL_UPDATE_PAGE_ID(_sh)
+#define SSV_RESET_SYSPLF(_sh) HAL_RESET_SYSPLF(_sh)
+#define SSV_INIT_IQK(_sh) HAL_INIT_IQK(_sh)
+#define SSV_SAVE_HW_STATUS(_sc) HAL_SAVE_HW_STATUS(_sc)
+#define SSV_IF_CHK_MAC2(_sh) HAL_IF_CHK_MAC2(_sh)
+#define SSV_GET_IC_TIME_TAG(_sh) HAL_GET_IC_TIME_TAG(_sh)
+#define SSV_RC_ALGORITHM(_sc) HAL_RC_ALGORITHM(_sc)
+#define SSV_SET_80211HW_RATE_CONFIG(_sc) HAL_SET_80211HW_RATE_CONFIG(_sc)
+#define SSV_RC_LEGACY_BITRATE_TO_RATE_DESC(_sc,_bitrate,_drate) \
+   HAL_RC_LEGACY_BITRATE_TO_RATE_DESC(_sc, _bitrate, _drate)
+#define SSV_DISABLE_FW_WSID(_sc,_index,_sta_priv,_vif_priv) \
+            HAL_DISABLE_FW_WSID(_sc, _index, _sta_priv, _vif_priv)
+#define SSV_ENABLE_FW_WSID(_sc,_sta,_sta_info,_type) \
+            HAL_ENABLE_FW_WSID(_sc, _sta, _sta_info, _type)
+#define SSV_WEP_USE_HW_CIPHER(_sc,_vif_priv) HAL_WEP_USE_HW_CIPHER(_sc, _vif_priv)
+#define SSV_PAIRWISE_WPA_USE_HW_CIPHER(_sc,_vif_priv,_cipher,_sta_priv) \
+            HAL_PAIRWISE_WPA_USE_HW_CIPHER( _sc, _vif_priv, _cipher, _sta_priv)
+#define SSV_USE_HW_ENCRYPT(_cipher,_sc,_sta_priv,_vif_priv) \
+            HAL_USE_HW_ENCRYPT(_cipher, _sc, _sta_priv, _vif_priv)
+#define SSV_GROUP_WPA_USE_HW_CIPHER(_sc,_vif_priv,_cipher) \
+            HAL_GROUP_WPA_USE_HW_CIPHER( _sc, _vif_priv, _cipher)
+#define SSV_SET_AES_TKIP_HW_CRYPTO_GROUP_KEY(_sc,_vif_info,_sta_info,_param) \
+            HAL_SET_AES_TKIP_HW_CRYPTO_GROUP_KEY(_sc, _vif_info, _sta_info, _param)
+#define SSV_WRITE_PAIRWISE_KEYIDX_TO_HW(_sh,_key_idx,_wsid) \
+            HAL_WRITE_PAIRWISE_KEYIDX_TO_HW(_sh, _key_idx, _wsid)
+#define SSV_WRITE_GROUP_KEYIDX_TO_HW(_sh,_key_idx,_wsid) \
+            HAL_WRITE_GROUP_KEYIDX_TO_HW(_sh, _key_idx, _wsid)
+#define SSV_WRITE_PAIRWISE_KEY_TO_HW(_sc,_key_idx,_alg,_key,_key_len,_keyconf,_vif_priv,_sta_priv) \
+            HAL_WRITE_PAIRWISE_KEY_TO_HW(_sc, _key_idx, _alg, _key, _key_len, _keyconf, _vif_priv, _sta_priv)
+#define SSV_WRITE_GROUP_KEY_TO_HW(_sc,_key_idx,_alg,_key,_key_len,_keyconf,_vif_priv,_sta_priv) \
+            HAL_WRITE_GROUP_KEY_TO_HW(_sc, _key_idx, _alg, _key, _key_len, _keyconf, _vif_priv, _sta_priv)
+#define SSV_WRITE_KEY_TO_HW(_sc,_vif_priv,_sram_ptr,_wsid,_key_idx,_key_type) \
+            HAL_WRITE_KEY_TO_HW(_sc, _vif_priv, _sram_ptr, _wsid, _key_idx, _key_type)
+#define SSV_SET_PAIRWISE_CIPHER_TYPE(_sh,_cipher,_wsid) \
+            HAL_SET_PAIRWISE_CIPHER_TYPE( _sh, _cipher, _wsid)
+#define SSV_SET_GROUP_CIPHER_TYPE(_sh,_vif_priv,_cipher) \
+            HAL_SET_GROUP_CIPHER_TYPE( _sh, _vif_priv, _cipher)
+#define SSV_CHK_IF_SUPPORT_HW_BSSID(_sc,_vif_idx) \
+            HAL_CHK_IF_SUPPORT_HW_BSSID( _sc, _vif_idx)
+#define SSV_CHK_DUAL_VIF_CHG_RX_FLOW(_sc,_vif_priv) \
+            HAL_CHK_DUAL_VIF_CHG_RX_FLOW( _sc, _vif_priv)
+#define SSV_SET_FW_HWWSID_SEC_TYPE(_sc,_sta,_sta_info,_vif_priv) \
+            HAL_SET_FW_HWWSID_SEC_TYPE( _sc, _sta, _sta_info, _vif_priv)
+#define SSV_SET_RX_CTRL_FLOW(_sh) HAL_SET_RX_CTRL_FLOW(_sh)
+#define SSV_RESTORE_RX_FLOW(_sc,_vif_priv,_sta) \
+            HAL_RESTORE_RX_FLOW( _sc, _vif_priv, _sta)
+#ifdef CONFIG_PM
+#define SSV_SAVE_CLEAR_TRAP_REASON(_sc) HAL_SAVE_CLEAR_TRAP_REASON(_sc)
+#define SSV_RESTORE_TRAP_REASON(_sc) HAL_RESTORE_TRAP_REASON(_sc);
+#define SSV_PMU_AWAKE(_sc) HAL_PMU_AWAKE(_sc)
+#endif
+#define SSV_ENABLE_USB_ACC(_sc,_epnum) HAL_ENABLE_USB_ACC(_sc, _epnum)
+#define SSV_DISABLE_USB_ACC(_sc,_epnum) HAL_DISABLE_USB_ACC(_sc, _epnum)
+#define SSV_SET_USB_LPM(_sc,_enable) HAL_SET_USB_LPM( _sc, _enable)
+#define SSV_JUMP_TO_ROM(_sc) HAL_JUMP_TO_ROM(_sc)
+#define SSV_STORE_WEP_KEY(_sc,_vif_priv,_sta_priv,_cipher,_key) \
+            HAL_STORE_WEP_KEY( _sc, _vif_priv, _sta_priv,_cipher, _key)
+#define SSV_PUT_MIC_SPACE_FOR_HW_CCMP_ENCRYPT(_sc,_skb) \
+            HAL_PUT_MIC_SPACE_FOR_HW_CCMP_ENCRYPT( _sc, _skb)
+#define SSV_GET_TX_DESC_CTYPE(_sh,_skb) HAL_GET_TX_DESC_CTYPE(_sh, _skb)
+#define SSV_GET_TX_DESC_SIZE(_sh) HAL_GET_TX_DESC_SIZE( _sh)
+#define SSV_UPDATE_NULL_FUNC_TXINFO(_sc,_sta,_skb) \
+                                                HAL_UPDATE_NULL_FUNC_TXINFO(_sc, _sta, _skb)
+#define SSV_ADD_TXINFO(_sc,_skb) HAL_ADD_TXINFO( _sc, _skb)
+#define SSV_GET_TX_DESC_TXQ_IDX(_sh,_skb) HAL_GET_TX_DESC_TXQ_IDX( _sh, _skb)
+#define SSV_SAVE_DEFAULT_IPD_CHCFG(_sh) HAL_SAVE_DEFAULT_IPD_CHCFG( _sh)
+#define SSV_SET_MACADDR(_sh,_vif_idx) HAL_SET_MACADDR( _sh, _vif_idx)
+#define SSV_SET_BSSID(_sh,_bssid,_vif_idx) HAL_SET_BSSID( _sh, _bssid, _vif_idx)
+#define SSV_SET_OP_MODE(_sh,_opmode,_vif_idx) HAL_SET_OP_MODE( _sh, _opmode, _vif_idx)
+#define SSV_HALT_MNGQ_UNTIL_DTIM(_sh) HAL_HALT_MNGQ_UNTIL_DTIM( _sh, true)
+#define SSV_UNHALT_MNGQ_UNTIL_DTIM(_sh) HAL_HALT_MNGQ_UNTIL_DTIM( _sh, false)
+#define SSV_SET_DUR_BURST_SIFS_G(_sh,_val) HAL_SET_DUR_BURST_SIFS_G( _sh, _val)
+#define SSV_SET_DUR_SLOT(_sh,_val) HAL_SET_DUR_SLOT( _sh, _val)
+#define SSV_SET_BCN_IFNO(_sh,_beacon_interval,_beacon_dtim_cnt) \
+            HAL_SET_BCN_IFNO( _sh, _beacon_interval, _beacon_dtim_cnt)
+#define SSV_BEACON_ENABLE(_sc,_bool) HAL_BEACON_ENABLE( _sc, _bool)
+#define SSV_SET_HW_WSID(_sc,_vif,_sta,_s) HAL_SET_HW_WSID( _sc, _vif, _sta, _s)
+#define SSV_ADD_FW_WSID(_sc,_vif_priv,_sta,_sta_info) \
+            HAL_ADD_FW_WSID( _sc, _vif_priv, _sta, _sta_info)
+#define SSV_DEL_HW_WSID(_sc,_hw_wsid) HAL_DEL_HW_WSID( _sc, _hw_wsid)
+#define SSV_SET_QOS_ENABLE(_sh,_qos) HAL_SET_QOS_ENABLE( _sh, _qos)
+#define SSV_SET_WMM_PARAM(_sc,_params,_queue) HAL_SET_WMM_PARAM( _sc, _params, _queue)
+#define SSV_RC_MAC80211_RATE_IDX(_sc,_rate_idx,_rxs) \
+            HAL_RC_MAC80211_RATE_IDX( _sc, _rate_idx, _rxs)
+#define SSV_INIT_TX_CFG(_sh) HAL_INIT_TX_CFG(_sh)
+#define SSV_INIT_RX_CFG(_sh) HAL_INIT_RX_CFG(_sh)
+#define SSV_FREE_PBUF(_sc,_hw_buf_ptr) HAL_FREE_PBUF(_sc, _hw_buf_ptr)
+#define SSV_GET_SEC_DECODE_ERR(_sh,_rx_skb,_mic_err,_decode_err) \
+            HAL_GET_SEC_DECODE_ERR(_sh, _rx_skb, _mic_err, _decode_err)
+#define SSV_GET_RX_DESC_INFO(_sh,_skb,_packet_len,_c_type,_tx_pkt_run_no) \
+            HAL_GET_RX_DESC_INFO( _sh, _skb, _packet_len, _c_type, _tx_pkt_run_no)
+#define SSV_GET_RX_DESC_HDR_OFFSET(_sh,_skb) \
+            HAL_GET_RX_DESC_HDR_OFFSET(_sh, _skb)
+#define SSV_IS_LEGACY_RATE(_sc,_skb) HAL_IS_LEGACY_RATE(_sc, _skb)
+#define SSV_RC_HT_STA_CURRENT_RATE_IS_CCK(_sc,_sta) \
+            HAL_RC_HT_STA_CURRENT_RATE_IS_CCK(_sc, _sta)
+#define SSV_RC_UPDATE_BASIC_RATE(_sc,_basic_rates) \
+   HAL_RC_UPDATE_BASIC_RATE(_sc, _basic_rates)
+#define SSV_NULLFUN_FRAME_FILTER(_sh,_skb) HAL_NULLFUN_FRAME_FILTER(_sh, _skb)
+#define SSV_RATE_REPORT_HANDLER(_sc,_skb,_no_ba_result) \
+            HAL_RATE_REPORT_HANDLER(_sc, _skb, _no_ba_result)
+#define SSV_ADJ_CONFIG(_sh) HAL_ADJ_CONFIG(_sh)
+#define SSV_BEACON_LOSS_ENABLE(_sh) HAL_BEACON_LOSS_ENABLE(_sh)
+#define SSV_BEACON_LOSS_DISABLE(_sh) HAL_BEACON_LOSS_DISABLE(_sh)
+#define SSV_BEACON_LOSS_CONFIG(_sh,_beacon_int,_bssid) \
+   HAL_BEACON_LOSS_CONFIG(_sh, _beacon_int, _bssid)
+#define SSV_PHY_ENABLE(_sh,_val) HAL_PHY_ENABLE(_sh, _val)
+#define SSV_EDCA_ENABLE(_sh,_val) HAL_EDCA_ENABLE(_sh, _val)
+#define SSV_EDCA_STAT(_sh) HAL_EDCA_STAT(_sh)
+#define SSV_FILL_LPBK_TX_DESC(_sc,_skb,_sec,_rate) \
+            HAL_FILL_LPBK_TX_DESC(_sc, _skb, _sec, _rate)
+#define SSV_CHK_LPBK_RX_RATE_DESC(_sh,_skb) HAL_CHK_LPBK_RX_RATE_DESC(_sh, _skb)
+#define SSV_SEND_TX_POLL_CMD(_sh,_type) HAL_SEND_TX_POLL_CMD(_sh, _type)
+#define SSV_UPDATE_EFUSE_SETTING(_sh) HAL_UPDATE_EFUSE_SETTING(_sh)
+#define SSV_DO_TEMPERATURE_COMPENSATION(_sh) HAL_DO_TEMPERATURE_COMPENSATION(_sh)
+#define SSV_PLL_CHK(_sh) HAL_PLL_CHK(_sh)
+#else
+int ssv6xxx_get_tx_desc_ctype(struct sk_buff *skb);
+int ssv6xxx_get_tx_desc_txq_idx(struct sk_buff *skb);
+int ssv6xxx_update_null_func_txinfo(struct ssv_softc *sc, struct ieee80211_sta *sta, struct sk_buff *skb);
+void ssv6xxx_rc_algorithm(struct ssv_softc *sc);
+void ssv6xxx_set_80211_hw_rate_config(struct ssv_softc *sc);
+void ssv6xxx_phy_enable(struct ssv_hw *sh, bool enable);
+bool ssv6xxx_nullfun_frame_filter(struct ssv_hw *sh, struct sk_buff *skb);
+void ssv6xxx_reset_sysplf(struct ssv_hw *sh);
+void tu_ssv6xxx_init_iqk(struct ssv_hw *sh);
+void ssv6xxx_save_hw_status(struct ssv_softc *sc);
+u64 ssv6xxx_get_ic_time_tag(struct ssv_hw *sh);
+void ssv6xxx_edca_enable(struct ssv_hw *sh, bool val);
+void ssv6xxx_edca_stat(struct ssv_hw *sh);
+void ssv6xxx_send_tx_poll_cmd(struct ssv_hw *sh, u32 type);
+int ssv6xxx_set_rx_ctrl_flow(struct ssv_hw *sh);
+int ssv6xxx_get_rx_desc_hdr_offset(struct sk_buff *skb);
+void ssv6xxx_fill_lpbk_tx_desc(struct sk_buff *skb, int security, unsigned char rate);
+int ssv6xxx_chk_rx_rate_desc(struct ssv_hw *sh, struct sk_buff *skb);
+int ssv6xxx_update_efuse_setting(struct ssv_hw *sh);
+void ssv6xxx_do_temperature_compensation(struct ssv_hw *sh);
+void ssv6xxx_pll_chk(struct ssv_hw *sh);
+#ifdef CONFIG_PM
+void ssv6xxx_save_clear_trap_reason(struct ssv_softc *sc);
+void ssv6xxx_restore_trap_reason(struct ssv_softc *sc);
+void ssv6xxx_pmu_awake(struct ssv_softc *sc);
+#endif
+#define SSV_UPDATE_PAGE_ID(_sh)
+#define SSV_RESET_SYSPLF(_sh) ssv6xxx_reset_sysplf(_sh)
+#define SSV_INIT_IQK(_sh) tu_ssv6xxx_init_iqk(_sh)
+#define SSV_SAVE_HW_STATUS(_sc) ssv6xxx_save_hw_status(_sc)
+#define SSV_IF_CHK_MAC2(_sh) (true)
+#define SSV_RC_ALGORITHM(_sc) ssv6xxx_rc_algorithm(_sc)
+#define SSV_SET_80211HW_RATE_CONFIG(_sc) ssv6xxx_set_80211_hw_rate_config(_sc)
+#define SSV_GET_IC_TIME_TAG(_sh) ssv6xxx_get_ic_time_tag(_sh)
+#define SSV_DISABLE_FW_WSID(_sc,_index,_sta_priv,_vif_priv) \
+            ssv6xxx_disable_fw_wsid(_sc, _index, _sta_priv, _vif_priv)
+#define SSV_ENABLE_FW_WSID(_sc,_sta,_sta_info,_type) \
+            ssv6xxx_enable_fw_wsid(_sc, _sta, _sta_info, _type)
+#define SSV_WEP_USE_HW_CIPHER(_sc,_vif_priv) ssv6xxx_wep_use_hw_cipher(sc, vif_priv)
+#define SSV_PAIRWISE_WPA_USE_HW_CIPHER(_sc,_vif_priv,_cipher,_sta_priv) \
+            ssv6xxx_pairwise_wpa_use_hw_cipher( _sc, _vif_priv, _cipher, _sta_priv)
+#define SSV_USE_HW_ENCRYPT(_cipher,_sc,_sta_priv,_vif_priv) \
+            ssv6xxx_use_hw_encrypt(_cipher, _sc, _sta_priv, _vif_priv)
+#define SSV_GROUP_WPA_USE_HW_CIPHER(_sc,_vif_priv,_cipher) \
+            ssv6xxx_group_wpa_use_hw_cipher( _sc, _vif_priv, _cipher)
+#define SSV_SET_AES_TKIP_HW_CRYPTO_GROUP_KEY(_sc,_vif_info,_sta_info,_param) \
+            _set_aes_tkip_hw_crypto_group_key(_sc, _vif_info, _sta_info, _param)
+#define SSV_WRITE_PAIRWISE_KEYIDX_TO_HW(_sh,_key_idx,_wsid) \
+            ssv6xxx_write_pairwise_keyidx_to_hw(_sh, _key_idx, _wsid)
+#define SSV_WRITE_GROUP_KEYIDX_TO_HW(_sh,_key_idx,_wsid)
+#define SSV_WRITE_PAIRWISE_KEY_TO_HW(_sc,_key_idx,_alg,_key,_key_len,_keyconf,_vif_priv,_sta_priv) \
+            _write_pairwise_key_to_hw(_sc, _key_idx, _alg, _key, _key_len, _keyconf, _vif_priv, _sta_priv)
+#define SSV_WRITE_GROUP_KEY_TO_HW(_sc,_key_idx,_alg,_key,_key_len,_keyconf,_vif_priv,_sta_priv) \
+            _write_group_key_to_hw(_sc, _key_idx, _alg, _key, _key_len, _keyconf, _vif_priv, _sta_priv)
+#define SSV_WRITE_KEY_TO_HW(_sc,_vif_priv,_sram_ptr,_wsid,_key_idx,_key_type) \
+            ssv6xxx_write_key_to_hw(_sc, _sram_ptr, _wsid, _key_idx, _key_type)
+#define SSV_SET_PAIRWISE_CIPHER_TYPE(_sh,_cipher,_wsid) \
+            ssv6200_hw_set_pair_type( _sh, _cipher)
+#define SSV_SET_GROUP_CIPHER_TYPE(_sh,_vif_priv,_cipher) \
+            ssv6200_hw_set_group_type( _sh, _cipher)
+#define SSV_CHK_IF_SUPPORT_HW_BSSID(_sc,_vif_idx) \
+            ssv6xxx_chk_if_support_hw_bssid( _sc, _vif_idx)
+#define SSV_CHK_DUAL_VIF_CHG_RX_FLOW(_sc,_vif_priv) \
+            ssv6xxx_chk_dual_vif_chg_rx_flow( _sc, _vif_priv)
+#define SSV_SET_FW_HWWSID_SEC_TYPE(_sc,_sta,_sta_info,_vif_priv) \
+            ssv6xxx_set_fw_hwwsid_sec_type( _sc, _sta, _sta_info, _vif_priv)
+#define SSV_SET_RX_CTRL_FLOW(_sh) ssv6xxx_set_rx_ctrl_flow(_sh)
+#define SSV_RESTORE_RX_FLOW(_sc,_vif_priv,_sta) \
+            ssv6xxx_restore_rx_flow( _sc, _vif_priv, _sta)
+#ifdef CONFIG_PM
+#define SSV_SAVE_CLEAR_TRAP_REASON(_sc) ssv6xxx_save_clear_trap_reason(_sc)
+#define SSV_RESTORE_TRAP_REASON(_sc) ssv6xxx_restore_trap_reason(_sc)
+#define SSV_PMU_AWAKE(_sc) ssv6xxx_pmu_awake(_sc)
+#endif
+#define SSV_ENABLE_USB_ACC(_sc,_epnum) ssv6xxx_none_func(_sc)
+#define SSV_DISABLE_USB_ACC(_sc,_epnum) ssv6xxx_none_func(_sc)
+#define SSV_SET_USB_LPM(_sc,_enable) ssv6xxx_none_func(_sc)
+#define SSV_JUMP_TO_ROM(_sc) ssv6xxx_none_func(_sc)
+#define SSV_HW_CRYPTO_KEY_WRITE_WEP(_sc,_keyconf,_alg,_vif_info) \
+            hw_crypto_key_write_wep( _sc, _keyconf, _alg, _vif_info)
+#define SSV_STORE_WEP_KEY(_sc,_vif_priv,_sta_priv,_cipher,_key) \
+            _store_wep_key( _sc, _vif_priv, _sta_priv, _cipher, _key)
+#define SSV_PUT_MIC_SPACE_FOR_HW_CCMP_ENCRYPT(_sc,_skb)
+#define SSV_GET_TX_DESC_CTYPE(_sh,_skb) ssv6xxx_get_tx_desc_ctype( _skb)
+#define SSV_GET_TX_DESC_SIZE(_sh) SSV6XXX_TX_DESC_LEN
+#define SSV_ADD_TXINFO(_sc,_skb) ssv6xxx_add_txinfo( _sc, _skb)
+#define SSV_UPDATE_NULL_FUNC_TXINFO(_sc,_sta,_skb) \
+                                                ssv6xxx_update_null_func_txinfo(_sc, _sta, _skb)
+#define SSV_GET_TX_DESC_TXQ_IDX(_sh,_skb) ssv6xxx_get_tx_desc_txq_idx( _skb)
+#define SSV_SET_MACADDR(_sh,_vif_idx) ssv6xxx_set_macaddr( _sh, _vif_idx)
+#define SSV_SET_BSSID(_sh,_bssid,_vif_idx) ssv6xxx_set_bssid( _sh, _bssid)
+#define SSV_SET_OP_MODE(_sh,_opmode,_vif_idx) ssv6xxx_set_op_mode( _sh, _opmode)
+#define SSV_HALT_MNGQ_UNTIL_DTIM(_sh) \
+            SMAC_REG_SET_BITS( _sh, ADR_MTX_BCN_EN_MISC, \
+                MTX_HALT_MNG_UNTIL_DTIM_MSK, MTX_HALT_MNG_UNTIL_DTIM_MSK)
+#define SSV_UNHALT_MNGQ_UNTIL_DTIM(_sh) \
+            SMAC_REG_SET_BITS( _sh, ADR_MTX_BCN_EN_MISC, 0, MTX_HALT_MNG_UNTIL_DTIM_MSK)
+#define SSV_SET_DUR_BURST_SIFS_G(_sh,_val) ssv6xxx_set_dur_burst_sifs_g( _sh, _val)
+#define SSV_SET_DUR_SLOT(_sh,_val) ssv6xxx_set_dur_slot( _sh, _val)
+#define SSV_SET_BCN_IFNO(_sh,_beacon_interval,_beacon_dtim_cnt) \
+            ssv6xxx_beacon_set_info( _sh, _beacon_interval, _beacon_dtim_cnt)
+#define SSV_BEACON_ENABLE(_sc,_bool) ssv6xxx_beacon_enable( _sc, _bool)
+#define SSV_SET_HW_WSID(_sc,_vif,_sta,_s) ssv6xxx_set_hw_wsid( _sc, _vif, _sta, _s)
+#define SSV_ADD_FW_WSID(_sc,_vif_priv,_sta,_sta_info) \
+            ssv6xxx_add_fw_wsid( _sc, _vif_priv, _sta, _sta_info)
+#define SSV_DEL_HW_WSID(_sc,_hw_wsid) ssv6xxx_del_hw_wsid( _sc, _hw_wsid)
+#define SSV_SET_QOS_ENABLE(_sh,_qos) \
+            SMAC_REG_SET_BITS( _sh, ADR_GLBLE_SET, ( (_qos)<<QOS_EN_SFT), QOS_EN_MSK)
+#define SSV_SET_WMM_PARAM(_sc,_params,_queue) ssv6xxx_set_wmm_param( _sc, _params, _queue)
+#define SSV_RC_MAC80211_RATE_IDX(_sc,_rate_idx,_rxs) \
+            ssv6xxx_rc_mac80211_rate_idx( _sc, _rate_idx, _rxs)
+#define SSV_FREE_PBUF(_sc,_hw_buf_ptr) ssv6xxx_pbuf_free(_sc, _hw_buf_ptr)
+#define SSV_GET_RX_DESC_INFO(_sh,_skb,_packet_len,_c_type,_tx_pkt_run_no) \
+            ssv6xxx_get_rx_desc_info( _skb, _packet_len, _c_type, _tx_pkt_run_no)
+#define SSV_GET_RX_DESC_HDR_OFFSET(_sh,_skb) \
+            ssv6xxx_get_rx_desc_hdr_offset(_sh, _skb)
+#define SSV_IS_LEGACY_RATE(_sc,_skb) (ssv6xxx_get_real_index(sc, skb) < SSV62XX_RATE_MCS_INDEX)
+#define SSV_RC_HT_STA_CURRENT_RATE_IS_CCK(_sc,_sta) (false)
+#define SSV_RC_UPDATE_BASIC_RATE(_sc,_basic_rates) \
+   ssv6xxx_rc_update_basic_rate(_sc, _basic_rates)
+#define SSV_PHY_ENABLE(_sh,_val) ssv6xxx_phy_enable(_sh, _val)
+#define SSV_NULLFUN_FRAME_FILTER(_sh,_skb) ssv6xxx_nullfun_frame_filter(_sh, _skb)
+#define SSV_EDCA_ENABLE(_sh,_val) ssv6xxx_edca_enable(_sh, _val)
+#define SSV_EDCA_STAT(_sh) ssv6xxx_edca_stat(_sh)
+#define SSV_FILL_LPBK_TX_DESC(_sc,_skb,_sec,_rate) \
+            ssv6xxx_fill_lpbk_tx_desc(_skb, _sec, _rate)
+#define SSV_CHK_LPBK_RX_RATE_DESC(_sh,_skb) ssv6xxx_chk_rx_rate_desc(_sh, _skb)
+#define SSV_SEND_TX_POLL_CMD(_sh,_type) ssv6xxx_send_tx_poll_cmd(_sh, _type)
+#define SSV_UPDATE_EFUSE_SETTING(_sh) ssv6xxx_update_efuse_setting(_sh)
+#define SSV_DO_TEMPERATURE_COMPENSATION(_sh) ssv6xxx_do_temperature_compensation(_sh)
+#define SSV_PLL_CHK(_sh) ssv6xxx_pll_chk(_sh)
+#define SSV_RATE_REPORT_HANDLER(_sc,_skb,_no_ba_result)
+#define SSV_RC_LEGACY_BITRATE_TO_RATE_DESC(_sc,_bitrate,_drate)
+#define SSV_BEACON_LOSS_ENABLE(_sh)
+#define SSV_BEACON_LOSS_DISABLE(_sh)
+#define SSV_BEACON_LOSS_CONFIG(_sh,_beacon_int,_bssid)
+#define SSV_GET_SEC_DECODE_ERR(_sh,_rx_skb,_mic_err,_decode_err) 0
+#ifdef CONFIG_SSV_CABRIO_E
+#define SSV_SAVE_DEFAULT_IPD_CHCFG(_sh) ssv6xxx_save_default_ipd_chcfg( _sh)
+#else
+#define SSV_SAVE_DEFAULT_IPD_CHCFG(_sh)
+#endif
+#define SSV_ADJ_CONFIG(_sh)
+#endif
+struct SKB_info_st;
+struct ampdu_ba_notify_data;
+int ssv6xxx_frame_hdrlen(struct ieee80211_hdr *hdr, bool is_ht);
+u32 ssv6xxx_ht_txtime(u8 rix, int pktlen, int width, int half_gi, bool is_gf);
+u32 ssv6xxx_non_ht_txtime(u8 phy, int kbps, u32 frameLen, bool shortPreamble);
+u32 ssv6200_ba_map_walker (struct AMPDU_TID_st *ampdu_tid, u32 start_ssn,
+                           u32 sn_bit_map[2], struct ampdu_ba_notify_data *ba_notify_data, u32 *p_acked_num);
+int ssv6200_dump_BA_notification (char *buf, struct ampdu_ba_notify_data *ba_notification);
+int ssv6xxx_get_real_index(struct ssv_softc *sc, struct sk_buff *skb);
+bool ssv6xxx_ssn_to_bit_idx (u32 start_ssn, u32 mpdu_ssn, u32 *word_idx,
+                             u32 *bit_idx);
+void ssv6xxx_mark_skb_retry (struct ssv_softc *sc, struct SKB_info_st *skb_info, struct sk_buff *skb);
+bool ssv6xxx_inc_bit_idx (struct ssv_softc *sc, u32 ssn_1st, u32 ssn_next, u32 *word_idx,
+                          u32 *bit_idx);
+void ssv6xxx_release_frames (struct AMPDU_TID_st *ampdu_tid);
+void ssv6xxx_find_txpktrun_no_from_BA(struct ssv_softc *sc, u32 start_ssn, u32 sn_bit_map[2]
+                                      , struct ssv_sta_priv_data *ssv_sta_priv);
+void ssv6xxx_find_txpktrun_no_from_ssn(struct ssv_softc *sc, u32 ssn,
+                                       struct ssv_sta_priv_data *ssv_sta_priv);
+void _ssv6xxx_hexdump(const char *title, const u8 *buf, size_t len);
+#ifdef CONFIG_PM
+void ssv6xxx_power_sleep(void *param);
+void ssv6xxx_power_awake(void *param);
+#endif
+int ssv6xxx_trigger_pmu(struct ssv_softc *sc);
+void ssv6xxx_enable_usb_acc(void *param, u8 epnum);
+void ssv6xxx_disable_usb_acc(void *param, u8 epnum);
+void ssv6xxx_jump_to_rom(void *param);
+int ssv6xxx_rx_burstread_size(void *param);
+int ssv6xxx_peek_next_pkt_len(struct sk_buff *skb, void *param);
+void ssv6xxx_beacon_miss_work(struct work_struct *work);
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smac/dev_tbl.h b/drivers/net/wireless/ssv6x5x/smac/dev_tbl.h
new file mode 100644
index 000000000..c5069b902
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/dev_tbl.h
@@ -0,0 +1,238 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _DEV_TBL_H_
+#define _DEV_TBL_H_
+#include "ssv6200_configuration.h"
+#include "drv_comm.h"
+#include <ssv6200_common.h>
+#ifndef SSV_SUPPORT_HAL
+#define ssv6200_phy_tbl phy_setting
+#ifdef CONFIG_SSV_CABRIO_E
+#define ssv6200_rf_tbl asic_rf_setting
+#else
+#undef ssv6200_rf_tbl
+#define ssv6200_rf_tbl fpga_rf_setting
+#endif
+#endif
+#define ACTION_DO_NOTHING 0
+#define ACTION_UPDATE_NAV 1
+#define ACTION_RESET_NAV 2
+#define ACTION_SIGNAL_ACK 3
+#define FRAME_ACCEPT 0
+#define FRAME_DROP 1
+#define SET_DEC_TBL(_type,_mask,_action,_drop) \
+    (_type<<9| \
+    _mask <<3| \
+    _action<<1| \
+    _drop)
+#ifndef USE_GENERIC_DECI_TBL
+u16 sta_deci_tbl[] = {
+    SET_DEC_TBL(0x1e, 0x3e, ACTION_RESET_NAV, FRAME_DROP),
+    SET_DEC_TBL(0x18, 0x3e, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
+    SET_DEC_TBL(0x1a, 0x3f, ACTION_SIGNAL_ACK, FRAME_DROP),
+    SET_DEC_TBL(0x10, 0x38, ACTION_DO_NOTHING, FRAME_DROP),
+    SET_DEC_TBL(0x25, 0x3f, ACTION_DO_NOTHING, FRAME_DROP),
+    SET_DEC_TBL(0x26, 0x36, ACTION_DO_NOTHING, FRAME_DROP),
+    SET_DEC_TBL(0x08, 0x3f, ACTION_DO_NOTHING, FRAME_ACCEPT),
+    SET_DEC_TBL(0x05, 0x3f, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
+    SET_DEC_TBL(0x0b, 0x3f, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
+    SET_DEC_TBL(0x01, 0x3d, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
+    SET_DEC_TBL(0x20, 0x30, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
+    SET_DEC_TBL(0x00, 0x00, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
+    SET_DEC_TBL(0x00, 0x00, ACTION_DO_NOTHING, FRAME_DROP),
+    SET_DEC_TBL(0x00, 0x00, ACTION_UPDATE_NAV, FRAME_DROP),
+    SET_DEC_TBL(0x00, 0x00, ACTION_RESET_NAV, FRAME_DROP),
+    SET_DEC_TBL(0x00, 0x00, ACTION_SIGNAL_ACK, FRAME_DROP),
+    0x2008,
+    0x1001,
+#if 0
+    0x8408,
+    0x1000,
+#else
+    0x0808,
+    0x1040,
+#endif
+    0x2008,
+    0x800E,
+    0x0BB8,
+    0x2B88,
+    0x0800,
+};
+u16 ap_deci_tbl[] = {
+    SET_DEC_TBL(0x1e, 0x3e, ACTION_RESET_NAV, FRAME_DROP),
+    SET_DEC_TBL(0x18, 0x3e, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
+    SET_DEC_TBL(0x1a, 0x3f, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
+    SET_DEC_TBL(0x10, 0x38, ACTION_DO_NOTHING, FRAME_DROP),
+    SET_DEC_TBL(0x25, 0x3f, ACTION_DO_NOTHING, FRAME_DROP),
+    SET_DEC_TBL(0x26, 0x36, ACTION_DO_NOTHING, FRAME_DROP),
+    SET_DEC_TBL(0x08, 0x3f, ACTION_DO_NOTHING, FRAME_DROP),
+    SET_DEC_TBL(0x20, 0x30, ACTION_DO_NOTHING, FRAME_DROP),
+    SET_DEC_TBL(0x00, 0x00, ACTION_DO_NOTHING, FRAME_ACCEPT),
+    SET_DEC_TBL(0x00, 0x00, ACTION_DO_NOTHING, FRAME_ACCEPT),
+    SET_DEC_TBL(0x20, 0x30, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
+    SET_DEC_TBL(0x00, 0x00, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
+    SET_DEC_TBL(0x00, 0x00, ACTION_DO_NOTHING, FRAME_DROP),
+    SET_DEC_TBL(0x00, 0x00, ACTION_UPDATE_NAV, FRAME_DROP),
+    SET_DEC_TBL(0x00, 0x00, ACTION_RESET_NAV, FRAME_DROP),
+    SET_DEC_TBL(0x00, 0x00, ACTION_SIGNAL_ACK, FRAME_DROP),
+    0x2008,
+    0x1001,
+    0x0888,
+    0x1040,
+    0x2008,
+    0x800E,
+    0x0800,
+    0x2008,
+    0x0800,
+};
+#else
+u16 generic_deci_tbl[] = {
+    SET_DEC_TBL(0x1e, 0x3e, ACTION_RESET_NAV, FRAME_DROP),
+    SET_DEC_TBL(0x18, 0x3e, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
+    SET_DEC_TBL(0x1a, 0x3f, ACTION_DO_NOTHING, FRAME_ACCEPT),
+    SET_DEC_TBL(0x10, 0x38, ACTION_DO_NOTHING, FRAME_DROP),
+    0,
+    0,
+    0,
+    SET_DEC_TBL(0x05, 0x3f, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
+    SET_DEC_TBL(0x0b, 0x3f, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
+    SET_DEC_TBL(0x01, 0x3d, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
+    SET_DEC_TBL(0x00, 0x00, ACTION_DO_NOTHING, FRAME_ACCEPT),
+    SET_DEC_TBL(0x00, 0x00, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
+    SET_DEC_TBL(0x00, 0x00, ACTION_DO_NOTHING, FRAME_DROP),
+    SET_DEC_TBL(0x00, 0x00, ACTION_UPDATE_NAV, FRAME_DROP),
+    SET_DEC_TBL(0x00, 0x00, ACTION_RESET_NAV, FRAME_DROP),
+    SET_DEC_TBL(0x00, 0x00, ACTION_SIGNAL_ACK, FRAME_DROP),
+    0x2008,
+    0x1001,
+    0x0400,
+    0x0400,
+    0x2000,
+    0x800E,
+    0x0800,
+    0x0B88,
+    0x0800,
+};
+#endif
+#ifdef USE_CONCURRENT_DECI_TBL
+u16 concurrent_deci_tbl[] = {
+    SET_DEC_TBL(0x1e, 0x3e, ACTION_RESET_NAV, FRAME_DROP),
+    SET_DEC_TBL(0x18, 0x3e, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
+    SET_DEC_TBL(0x1a, 0x3f, ACTION_DO_NOTHING, FRAME_ACCEPT),
+    SET_DEC_TBL(0x10, 0x38, ACTION_DO_NOTHING, FRAME_DROP),
+    SET_DEC_TBL(0x08, 0x3f, ACTION_DO_NOTHING, FRAME_ACCEPT),
+    0,
+    0,
+    SET_DEC_TBL(0x05, 0x3f, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
+    SET_DEC_TBL(0x0b, 0x3f, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
+    SET_DEC_TBL(0x01, 0x3d, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
+    SET_DEC_TBL(0x00, 0x00, ACTION_DO_NOTHING, FRAME_ACCEPT),
+    SET_DEC_TBL(0x00, 0x00, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
+    SET_DEC_TBL(0x00, 0x00, ACTION_DO_NOTHING, FRAME_DROP),
+    SET_DEC_TBL(0x00, 0x00, ACTION_UPDATE_NAV, FRAME_DROP),
+    SET_DEC_TBL(0x00, 0x00, ACTION_RESET_NAV, FRAME_DROP),
+    SET_DEC_TBL(0x00, 0x00, ACTION_SIGNAL_ACK, FRAME_DROP),
+    0x2008,
+    0x1001,
+    0x0400,
+    0x1010,
+    0x2000,
+    0x800E,
+    0x0800,
+    0x1000,
+    0x0800,
+    0x0400,
+    0x0800,
+};
+#endif
+#define SET_PHY_INFO(_ctsdur,_ba_rate_idx,_ack_rate_idx,_llength_idx,_llength_enable) \
+         (_ctsdur<<16| \
+         _ba_rate_idx <<10| \
+         _ack_rate_idx<<4| \
+         _llength_idx<<1| \
+         _llength_enable)
+#define SET_PHY_L_LENGTH(_l_ba,_l_rts,_l_cts_ack) (_l_ba<<12|_l_rts<<6 |_l_cts_ack)
+#if ((defined CONFIG_SSV_CABRIO_E) && !(defined SSV_SUPPORT_HAL))
+static u32 phy_info_6051z[] = {
+    0x18000000, 0x18000100, 0x18000200, 0x18000300, 0x18000140,
+    0x18000240, 0x18000340, 0x0C000001, 0x0C000101, 0x0C000201,
+    0x0C000301, 0x18000401, 0x18000501, 0x18000601, 0x18000701,
+    0x0C030002, 0x0C030102, 0x0C030202, 0x18030302, 0x18030402,
+    0x18030502, 0x18030602, 0x1C030702, 0x0C030082, 0x0C030182,
+    0x0C030282, 0x18030382, 0x18030482, 0x18030582, 0x18030682,
+    0x1C030782, 0x0C030042, 0x0C030142, 0x0C030242, 0x18030342,
+    0x18030442, 0x18030542, 0x18030642, 0x1C030742
+};
+#endif
+u32 phy_info_tbl[] = {
+    0x0C000000, 0x0C000100, 0x0C000200, 0x0C000300, 0x0C000140,
+    0x0C000240, 0x0C000340, 0x00000001, 0x00000101, 0x00000201,
+    0x00000301, 0x0C000401, 0x0C000501, 0x0C000601, 0x0C000701,
+    0x00030002, 0x00030102, 0x00030202, 0x0C030302, 0x0C030402,
+    0x0C030502, 0x0C030602, 0x10030702, 0x00030082, 0x00030182,
+    0x00030282, 0x0C030382, 0x0C030482, 0x0C030582, 0x0C030682,
+    0x10030782, 0x00030042, 0x00030142, 0x00030242, 0x0C030342,
+    0x0C030442, 0x0C030542, 0x0C030642, 0x10030742,
+    SET_PHY_INFO(314, 0, 0, 0, 0),
+    SET_PHY_INFO(258, 0, 1, 0, 0),
+    SET_PHY_INFO(223, 0, 1, 0, 0),
+    SET_PHY_INFO(213, 0, 1, 0, 0),
+    SET_PHY_INFO(162, 0, 4, 0, 0),
+    SET_PHY_INFO(127, 0, 4, 0, 0),
+    SET_PHY_INFO(117, 0, 4, 0, 0),
+    SET_PHY_INFO(60, 7, 7, 0, 0),
+    SET_PHY_INFO(52, 7, 7, 0, 0),
+    SET_PHY_INFO(48, 9, 9, 0, 0),
+    SET_PHY_INFO(44, 9, 9, 0, 0),
+    SET_PHY_INFO(44, 11, 11, 0, 0),
+    SET_PHY_INFO(40, 11, 11, 0, 0),
+    SET_PHY_INFO(40, 11, 11, 0, 0),
+    SET_PHY_INFO(40, 11, 11, 0, 0),
+    SET_PHY_INFO(76, 7, 7, 0, 1),
+    SET_PHY_INFO(64, 9, 9, 1, 1),
+    SET_PHY_INFO(60, 9, 9, 2, 1),
+    SET_PHY_INFO(60, 11, 11, 3, 1),
+    SET_PHY_INFO(56, 11, 11, 4, 1),
+    SET_PHY_INFO(56, 11, 11, 5, 1),
+    SET_PHY_INFO(56, 11, 11, 5, 1),
+    SET_PHY_INFO(56, 11, 11, 5, 1),
+    SET_PHY_INFO(76, 7, 7, 6, 1),
+    SET_PHY_INFO(64, 9, 9, 1, 1),
+    SET_PHY_INFO(60, 9, 9, 2, 1),
+    SET_PHY_INFO(60, 11, 11, 3, 1),
+    SET_PHY_INFO(56, 11, 11, 4, 1),
+    SET_PHY_INFO(56, 11, 11, 5, 1),
+    SET_PHY_INFO(56, 11, 11, 5, 1),
+    SET_PHY_INFO(56, 11, 11, 5, 1),
+    SET_PHY_INFO(64, 7, 7, 0, 0),
+    SET_PHY_INFO(52, 9, 9, 0, 0),
+    SET_PHY_INFO(48, 9, 9, 0, 0),
+    SET_PHY_INFO(48, 11, 11, 0, 0),
+    SET_PHY_INFO(44, 11, 11, 0, 0),
+    SET_PHY_INFO(44, 11, 11, 0, 0),
+    SET_PHY_INFO(44, 11, 11, 0, 0),
+    SET_PHY_INFO(44, 11, 11, 0, 0),
+    SET_PHY_L_LENGTH(50, 38, 35),
+    SET_PHY_L_LENGTH(35, 29, 26),
+    SET_PHY_L_LENGTH(29, 26, 23),
+    SET_PHY_L_LENGTH(26, 23, 23),
+    SET_PHY_L_LENGTH(23, 23, 20),
+    SET_PHY_L_LENGTH(23, 20, 20),
+    SET_PHY_L_LENGTH(47, 38, 35),
+    SET_PHY_L_LENGTH( 0, 0, 0),
+};
+size_t phy_info_tbl_size = sizeof(phy_info_tbl);
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smac/drv_comm.h b/drivers/net/wireless/ssv6x5x/smac/drv_comm.h
new file mode 100644
index 000000000..f5b2ea36d
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/drv_comm.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _DRV_COMM_H_
+#define _DRV_COMM_H_
+#define PHY_INFO_TBL1_SIZE 39
+#define PHY_INFO_TBL2_SIZE 39
+#define PHY_INFO_TBL3_SIZE 8
+#define ampdu_fw_rate_info_status_no_use BIT(0)
+#define ampdu_fw_rate_info_status_in_use BIT(1)
+#define ampdu_fw_rate_info_status_reset BIT(2)
+#define SSV_NUM_STA 8
+#define SSV_NUM_VIF 2
+#define SECURITY_KEY_LEN (32)
+enum SSV_CIPHER_E {
+    SSV_CIPHER_NONE,
+    SSV_CIPHER_WEP40,
+    SSV_CIPHER_WEP104,
+    SSV_CIPHER_TKIP,
+    SSV_CIPHER_CCMP,
+    SSV_CIPHER_SMS4,
+    SSV_CIPHER_INVALID = (-1)
+};
+#define ME_NONE 0
+#define ME_WEP40 1
+#define ME_WEP104 2
+#define ME_TKIP 3
+#define ME_CCMP 4
+#define ME_SMS4 5
+struct ssv6xxx_hw_key {
+    u8 key[SECURITY_KEY_LEN];
+    u32 tx_pn_l;
+    u32 tx_pn_h;
+    u32 rx_pn_l;
+    u32 rx_pn_h;
+} __attribute__((packed));
+struct ssv6xxx_hw_sta_key {
+    u8 pair_key_idx:4;
+    u8 group_key_idx:4;
+    u8 valid;
+    u8 reserve[2];
+    struct ssv6xxx_hw_key pair;
+} __attribute__((packed));
+struct ssv6xxx_hw_sec {
+    struct ssv6xxx_hw_key group_key[3];
+    struct ssv6xxx_hw_sta_key sta_key[8];
+} __attribute__((packed));
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smac/efuse.c b/drivers/net/wireless/ssv6x5x/smac/efuse.c
new file mode 100644
index 000000000..ec3b45f9c
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/efuse.c
@@ -0,0 +1,363 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/version.h>
+#include <linux/etherdevice.h>
+#include <ssv6200.h>
+#include "efuse.h"
+#include <hal.h>
+mm_segment_t oldfs;
+struct file *openFile(char *path,int flag,int mode)
+{
+    struct file *fp=NULL;
+    fp=filp_open(path, flag, 0);
+    if(IS_ERR(fp))
+        return NULL;
+    else
+        return fp;
+}
+int readFile(struct file *fp,char *buf,int readlen)
+{
+    if (fp->f_op && fp->f_op->read)
+        return fp->f_op->read(fp,buf,readlen, &fp->f_pos);
+    else
+        return -1;
+}
+int closeFile(struct file *fp)
+{
+    filp_close(fp,NULL);
+    return 0;
+}
+void initKernelEnv(void)
+{
+    oldfs = get_fs();
+    set_fs(KERNEL_DS);
+}
+void parseMac(char* mac, u_int8_t addr[])
+{
+    long b;
+    int i;
+    for (i = 0; i < 6; i++) {
+        b = simple_strtol(mac+(3*i), (char **) NULL, 16);
+        addr[i] = (char)b;
+    }
+}
+static int readfile_mac(u8 *path,u8 *mac_addr)
+{
+    char buf[128];
+    struct file *fp=NULL;
+    int ret=0;
+    fp=openFile(path,O_RDONLY,0);
+    if (fp!=NULL) {
+        initKernelEnv();
+        memset(buf,0,128);
+        if ((ret=readFile(fp,buf,128))>0) {
+            parseMac(buf,(uint8_t *)mac_addr);
+        } else
+            printk("read file error %d=[%s]\n",ret,path);
+        set_fs(oldfs);
+        closeFile(fp);
+    } else
+        printk("Read open File fail[%s]!!!! \n",path);
+    return ret;
+}
+static int write_mac_to_file(u8 *mac_path,u8 *mac_addr)
+{
+    char buf[128];
+    struct file *fp=NULL;
+    int ret=0,len;
+    mm_segment_t old_fs;
+    fp=openFile(mac_path,O_WRONLY|O_CREAT,0640);
+    if (fp!=NULL) {
+        initKernelEnv();
+        memset(buf,0,128);
+        sprintf(buf,"%x:%x:%x:%x:%x:%x",mac_addr[0],mac_addr[1],mac_addr[2],mac_addr[3],mac_addr[4],mac_addr[5]);
+        len = strlen(buf)+1;
+        old_fs = get_fs();
+        set_fs(KERNEL_DS);
+        fp->f_op->write(fp, (char *)buf, len, &fp->f_pos);
+        set_fs(old_fs);
+        closeFile(fp);
+    } else
+        printk("Write open File fail!!!![%s] \n",mac_path);
+    return ret;
+}
+#ifndef SSV_SUPPORT_HAL
+u8 read_efuse(struct ssv_hw *sh, u8 *pbuf)
+{
+    u32 val, i, j ;
+    SMAC_REG_WRITE(sh, ADR_PAD20, 0x11);
+    SMAC_REG_WRITE(sh, ADR_EFUSE_SPI_RD0_EN, 0x1);
+    SMAC_REG_READ(sh, ADR_EFUSE_SPI_RDATA_0, &val);
+    sh->cfg.chip_identity = val;
+    SMAC_REG_WRITE(sh, ADR_EFUSE_SPI_RD1_EN, 0x1);
+    SMAC_REG_READ(sh, ADR_EFUSE_SPI_RDATA_1, &val);
+    for (i = 0; i < (EFUSE_MAX_SECTION_MAP); i++) {
+        SMAC_REG_WRITE(sh, ADR_EFUSE_SPI_RD1_EN+i*4, 0x1);
+        SMAC_REG_READ(sh, ADR_EFUSE_SPI_RDATA_1+i*4, &val);
+        for ( j = 0; j < 4; j++)
+            *pbuf++ = ((val >> j*8) & 0xff);
+    }
+    SMAC_REG_WRITE(sh, ADR_PAD20,0x1800000a);
+    return 1;
+}
+void write_efuse(struct ssv_hw *sh, u8 *data, u8 data_length)
+{
+    return;
+}
+#endif
+u16 parser_efuse(struct ssv_hw *sh, u8 *pbuf, u8 *mac_addr, u8 *new_mac_addr, struct efuse_map *efuse_tbl)
+{
+    u8 *rtemp8,idx=0;
+    u16 shift=0,i;
+    u16 efuse_real_content_len = 0;
+    rtemp8 = pbuf;
+    if (*rtemp8 == 0x00) {
+        return efuse_real_content_len;
+    }
+    do {
+        idx = (*(rtemp8) >> shift)&0xf;
+        switch(idx) {
+        case EFUSE_R_CALIBRATION_RESULT:
+        case EFUSE_CRYSTAL_FREQUENCY_OFFSET:
+        case EFUSE_TX_POWER_INDEX_1:
+        case EFUSE_TX_POWER_INDEX_2:
+        case EFUSE_SAR_RESULT:
+        case EFUSE_CHIP_ID:
+        case NO_USE:
+        case EFUSE_VID:
+        case EFUSE_PID:
+        case EFUSE_RATE_TABLE_1:
+        case EFUSE_RATE_TABLE_2:
+            if(shift) {
+                rtemp8 ++;
+                efuse_tbl[idx].value = (u16)((u8)(*((u16*)rtemp8)) & ((1<< efuse_tbl[idx].byte_cnts) - 1));
+            } else {
+                efuse_tbl[idx].value = (u16)((u8)(*((u16*)rtemp8) >> 4) & ((1<< efuse_tbl[idx].byte_cnts) - 1));
+            }
+            efuse_real_content_len += (efuse_tbl[idx].offset + efuse_tbl[idx].byte_cnts);
+            sh->efuse_bitmap |= BIT(idx);
+            break;
+        case EFUSE_MAC:
+            if(shift) {
+                rtemp8 ++;
+                memcpy(mac_addr,rtemp8,6);
+            } else {
+                for(i=0; i<6; i++) {
+                    mac_addr[i] = (u16)(*((u16*)rtemp8) >> 4) & 0xff;
+                    rtemp8++;
+                }
+            }
+            efuse_real_content_len += (efuse_tbl[idx].offset + efuse_tbl[idx].byte_cnts);
+            sh->efuse_bitmap |= BIT(idx);
+            break;
+        case EFUSE_MAC_NEW:
+            if(shift) {
+                rtemp8 ++;
+                memcpy(new_mac_addr, rtemp8, 6);
+            } else {
+                for(i = 0; i < 6; i ++) {
+                    new_mac_addr[i] = (u16)(*((u16*)rtemp8) >> 4) & 0xff;
+                    rtemp8++;
+                }
+            }
+            efuse_real_content_len += (efuse_tbl[idx].offset + efuse_tbl[idx].byte_cnts);
+            sh->efuse_bitmap |= BIT(idx);
+            break;
+        default:
+            idx = 0;
+            break;
+        }
+        shift = efuse_real_content_len % 8;
+        rtemp8 = &pbuf[efuse_real_content_len / 8];
+    } while(idx != 0);
+    return efuse_real_content_len;
+}
+void addr_increase_copy(u8 *dst, u8 *src)
+{
+#if 0
+    u16 *a = (u16 *)dst;
+    const u16 *b = (const u16 *)src;
+    a[0] = b[0];
+    a[1] = b[1];
+    if (b[2] == 0xffff)
+        a[2] = b[2] - 1;
+    else
+        a[2] = b[2] + 1;
+#endif
+    u8 *a = (u8 *)dst;
+    const u8 *b = (const u8 *)src;
+    a[0] = b[0];
+    a[1] = b[1];
+    a[2] = b[2];
+    a[3] = b[3];
+    a[4] = b[4];
+    a[5] = b[5];
+    if (b[5] & 0x1)
+        a[5]--;
+    else
+        a[5]++;
+}
+static u8 key_char2num(u8 ch)
+{
+    if((ch>='0')&&(ch<='9'))
+        return ch - '0';
+    else if ((ch>='a')&&(ch<='f'))
+        return ch - 'a' + 10;
+    else if ((ch>='A')&&(ch<='F'))
+        return ch - 'A' + 10;
+    else
+        return 0xff;
+}
+u8 key_2char2num(u8 hch, u8 lch)
+{
+    return ((key_char2num(hch) << 4) | key_char2num(lch));
+}
+extern char* tu_ssv_initmac;
+#ifdef ROCKCHIP_3126_SUPPORT
+extern int rockchip_wifi_mac_addr(unsigned char *buf);
+#endif
+void efuse_read_all_map(struct ssv_hw *sh)
+{
+    u8 mac[ETH_ALEN] = {0};
+    int jj,kk;
+    u8 efuse_mapping_table[EFUSE_HWSET_MAX_SIZE/8];
+#ifndef CONFIG_SSV_RANDOM_MAC
+    u8 pseudo_mac0[ETH_ALEN] = { 0x00, 0x33, 0x33, 0x33, 0x33, 0x33 };
+#endif
+    u8 efuse_mac[ETH_ALEN];
+    u8 efuse_mac_new[ETH_ALEN];
+#ifdef EFUSE_DEBUG
+    int i;
+#endif
+    struct efuse_map ssv_efuse_item_table[] = {
+        {4, 0, 0},
+        {4, 8, 0},
+        {4, 8, 0},
+        {4, 48, 0},
+        {4, 8, 0},
+        {4, 8, 0},
+        {4, 8, 0},
+        {4, 4, 0},
+        {4, 0, 0},
+        {4, 16, 0},
+        {4, 16, 0},
+        {4, 48, 0},
+        {4, 8, 0},
+        {4, 8, 0},
+    };
+    memset(efuse_mac, 0x00, ETH_ALEN);
+    memset(efuse_mac_new, 0x00, ETH_ALEN);
+    memset(efuse_mapping_table,0x00,EFUSE_HWSET_MAX_SIZE/8);
+    SSV_READ_EFUSE(sh, efuse_mapping_table);
+#ifdef EFUSE_DEBUG
+    for(i=0; i<(EFUSE_HWSET_MAX_SIZE/8); i++) {
+        if(i%4 == 0)
+            printk("\n");
+        printk("%02x-",efuse_mapping_table[i]);
+    }
+    printk("\n");
+#endif
+    parser_efuse(sh, efuse_mapping_table, efuse_mac, efuse_mac_new, ssv_efuse_item_table);
+    if (sh->efuse_bitmap & BIT(EFUSE_R_CALIBRATION_RESULT))
+        sh->cfg.r_calbration_result = (u8)ssv_efuse_item_table[EFUSE_R_CALIBRATION_RESULT].value;
+    if (sh->efuse_bitmap & BIT(EFUSE_SAR_RESULT))
+        sh->cfg.sar_result = (u8)ssv_efuse_item_table[EFUSE_SAR_RESULT].value;
+    if (sh->efuse_bitmap & BIT(EFUSE_CRYSTAL_FREQUENCY_OFFSET))
+        sh->cfg.crystal_frequency_offset = (u8)ssv_efuse_item_table[EFUSE_CRYSTAL_FREQUENCY_OFFSET].value;
+    if (sh->efuse_bitmap & BIT(EFUSE_TX_POWER_INDEX_1))
+        sh->cfg.tx_power_index_1 = (u8)ssv_efuse_item_table[EFUSE_TX_POWER_INDEX_1].value;
+    if (sh->efuse_bitmap & BIT(EFUSE_TX_POWER_INDEX_2))
+        sh->cfg.tx_power_index_2 = (u8)ssv_efuse_item_table[EFUSE_TX_POWER_INDEX_2].value;
+    if (sh->efuse_bitmap & BIT(EFUSE_RATE_TABLE_1))
+        sh->cfg.rate_table_1 = (u8)ssv_efuse_item_table[EFUSE_RATE_TABLE_1].value;
+    if (sh->efuse_bitmap & BIT(EFUSE_RATE_TABLE_2))
+        sh->cfg.rate_table_2 = (u8)ssv_efuse_item_table[EFUSE_RATE_TABLE_2].value;
+    if (!is_valid_ether_addr(&sh->cfg.maddr[0][0])) {
+#ifdef ROCKCHIP_3126_SUPPORT
+        if (!rockchip_wifi_mac_addr(mac)) {
+            printk("=========> get mac address from flash [%02x:%02x:%02x:%02x:%02x:%02x]\n", mac[0], mac[1],
+                   mac[2], mac[3], mac[4], mac[5]);
+            if(is_valid_ether_addr(mac)) {
+                memcpy(&sh->cfg.maddr[0][0],mac,ETH_ALEN);
+                addr_increase_copy(&sh->cfg.maddr[1][0],mac);
+                goto Done;
+            }
+        }
+#endif
+        if(!sh->cfg.ignore_efuse_mac) {
+            if (is_valid_ether_addr(efuse_mac_new)) {
+                printk("MAC address from e-fuse\n");
+                memcpy(&sh->cfg.maddr[0][0], efuse_mac_new, ETH_ALEN);
+                addr_increase_copy(&sh->cfg.maddr[1][0], efuse_mac_new);
+                goto Done;
+            }
+        }
+        if (tu_ssv_initmac != NULL) {
+            for( jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3 ) {
+                mac[jj] = key_2char2num(tu_ssv_initmac[kk], tu_ssv_initmac[kk+ 1]);
+            }
+            if(is_valid_ether_addr(mac)) {
+                printk("MAC address from insert module\n");
+                memcpy(&sh->cfg.maddr[0][0],mac,ETH_ALEN);
+                addr_increase_copy(&sh->cfg.maddr[1][0],mac);
+                goto Done;
+            }
+        }
+        if (sh->cfg.mac_address_path[0] != 0x00) {
+            if((readfile_mac(sh->cfg.mac_address_path,&sh->cfg.maddr[0][0])) && (is_valid_ether_addr(&sh->cfg.maddr[0][0]))) {
+                printk("MAC address from sh->cfg.mac_address_path[wifi.cfg]\n");
+                addr_increase_copy(&sh->cfg.maddr[1][0], &sh->cfg.maddr[0][0]);
+                goto Done;
+            }
+        }
+        switch (sh->cfg.mac_address_mode) {
+        case 1:
+            get_random_bytes(&sh->cfg.maddr[0][0],ETH_ALEN);
+            sh->cfg.maddr[0][0] = sh->cfg.maddr[0][0] & 0xF0;
+            addr_increase_copy(&sh->cfg.maddr[1][0], &sh->cfg.maddr[0][0]);
+            break;
+        case 2:
+            if((readfile_mac(sh->cfg.mac_output_path,&sh->cfg.maddr[0][0])) && (is_valid_ether_addr(&sh->cfg.maddr[0][0]))) {
+                addr_increase_copy(&sh->cfg.maddr[1][0], &sh->cfg.maddr[0][0]);
+            } else {
+                {
+                    get_random_bytes(&sh->cfg.maddr[0][0],ETH_ALEN);
+                    sh->cfg.maddr[0][0] = sh->cfg.maddr[0][0] & 0xF0;
+                    addr_increase_copy(&sh->cfg.maddr[1][0], &sh->cfg.maddr[0][0]);
+                    if (sh->cfg.mac_output_path[0] != 0x00)
+                        write_mac_to_file(sh->cfg.mac_output_path,&sh->cfg.maddr[0][0]);
+                }
+            }
+            break;
+        default:
+            memcpy(&sh->cfg.maddr[0][0], pseudo_mac0, ETH_ALEN);
+            addr_increase_copy(&sh->cfg.maddr[1][0], pseudo_mac0);
+            break;
+        }
+        printk("MAC address from Software MAC mode[%d]\n",sh->cfg.mac_address_mode);
+    }
+Done:
+    printk("EFUSE configuration\n");
+    printk("Read efuse chip identity[%08x]\n", sh->cfg.chip_identity);
+    printk("r_calbration_result- %x\n", sh->cfg.r_calbration_result);
+    printk("sar_result- %x\n", sh->cfg.sar_result);
+    printk("crystal_frequency_offset- %x\n", sh->cfg.crystal_frequency_offset);
+    printk("tx_power_index_1- %x\n", sh->cfg.tx_power_index_1);
+    printk("tx_power_index_2- %x\n", sh->cfg.tx_power_index_2);
+    printk("MAC address - %pM\n", efuse_mac_new);
+    printk("rate_table_1- %x\n", sh->cfg.rate_table_1);
+    printk("rate_table_2- %x\n", sh->cfg.rate_table_2);
+}
diff --git a/drivers/net/wireless/ssv6x5x/smac/efuse.h b/drivers/net/wireless/ssv6x5x/smac/efuse.h
new file mode 100644
index 000000000..39a81f62c
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/efuse.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV_EFUSE_H_
+#define _SSV_EFUSE_H_
+#include "dev.h"
+struct efuse_map {
+    u8 offset;
+    u8 byte_cnts;
+    u16 value;
+};
+enum efuse_data_item {
+    EFUSE_R_CALIBRATION_RESULT = 1,
+    EFUSE_SAR_RESULT,
+    EFUSE_MAC,
+    EFUSE_CRYSTAL_FREQUENCY_OFFSET,
+    EFUSE_TX_POWER_INDEX_1,
+    EFUSE_TX_POWER_INDEX_2,
+    EFUSE_CHIP_ID,
+    NO_USE,
+    EFUSE_VID,
+    EFUSE_PID,
+    EFUSE_MAC_NEW,
+    EFUSE_RATE_TABLE_1,
+    EFUSE_RATE_TABLE_2
+};
+#ifdef SSV_SUPPORT_HAL
+#define SSV_READ_EFUSE(_sh,_table) HAL_READ_EFUSE(_sh, _table)
+#define SSV_WRITE_EFUSE(_sh,_pbuf,_len) HAL_WRITE_EFUSE(_sh, _pbuf, _len)
+#else
+#define EFUSE_HWSET_MAX_SIZE (256-32)
+#define EFUSE_MAX_SECTION_MAP (EFUSE_HWSET_MAX_SIZE>>5)
+#define SSV_EFUSE_ID_READ_SWITCH 0xC2000128
+#define SSV_EFUSE_ID_RAW_DATA_BASE 0xC200014C
+#define SSV_EFUSE_READ_SWITCH 0xC200012C
+#define SSV_EFUSE_RAW_DATA_BASE 0xC2000150
+u8 read_efuse(struct ssv_hw *sh, u8 *pbuf);
+void write_efuse(struct ssv_hw *sh, u8 *data, u8 data_length);
+#define SSV_READ_EFUSE(_sh,_table) read_efuse(_sh, _table)
+#define SSV_WRITE_EFUSE(_sh,_data,_len) write_efuse(_sh, _data, _len)
+#endif
+u16 parser_efuse(struct ssv_hw *sh, u8 *pbuf, u8 *mac_addr, u8 *new_mac_addr, struct efuse_map *efuse_tbl);
+void efuse_read_all_map(struct ssv_hw *sh);
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smac/hal/hal.c b/drivers/net/wireless/ssv6x5x/smac/hal/hal.c
new file mode 100644
index 000000000..bd00633b5
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/hal/hal.c
@@ -0,0 +1,352 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifdef ECLIPSE
+#include <ssv_mod_conf.h>
+#endif
+#include <linux/version.h>
+#include <linux/platform_device.h>
+#ifdef SSV_SUPPORT_HAL
+#include <linux/string.h>
+#include <ssv6200.h>
+#include <smac/dev.h>
+#include <hal.h>
+#include <smac/ssv_skb.h>
+static int ssv6xxx_do_iq_cal(struct ssv_hw *sh, struct ssv6xxx_iqk_cfg *p_cfg)
+{
+    struct ssv_softc *sc = sh->sc;
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_HAL,
+             "Do not need IQ CAL for this model!! \n");
+    return 0;
+}
+static void ssv6xxx_dpd_enable(struct ssv_hw *sh, bool val)
+{
+    struct ssv_softc *sc = sh->sc;
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_HAL,
+             "Not support DPD for this model!! \n");
+}
+static void tu_ssv6xxx_init_ch_cfg(struct ssv_hw *sh)
+{
+    struct ssv_softc *sc = sh->sc;
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_HAL,
+             "Not support set channel dependant cfg for this model!! \n");
+}
+static void tu_ssv6xxx_init_iqk(struct ssv_hw *sh)
+{
+    struct ssv_softc *sc = sh->sc;
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_HAL,
+             "Not support so save default iqk cfg for this model!! \n");
+}
+static void ssv6xxx_save_default_ipd_chcfg(struct ssv_hw *sh)
+{
+    struct ssv_softc *sc = sh->sc;
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_HAL,
+             "Not support to change phy info according to ipd for this model!! \n");
+}
+static void ssv6xxx_chg_ipd_phyinfo(struct ssv_hw *sh)
+{
+    struct ssv_softc *sc = sh->sc;
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_HAL,
+             "Not support to save default channel cfg for ipd for this model!! \n");
+}
+static void ssv6xxx_update_cfg_hw_patch(struct ssv_hw *sh,
+                                        ssv_cabrio_reg *rf_table, ssv_cabrio_reg *phy_table)
+{
+    struct ssv_softc *sc = sh->sc;
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_HAL,
+             "%s is not supported for this model!!\n",__func__);
+}
+static void ssv6xxx_update_hw_config(struct ssv_hw *sh,
+                                     ssv_cabrio_reg *rf_table, ssv_cabrio_reg *phy_table)
+{
+    struct ssv_softc *sc = sh->sc;
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_HAL,
+             "%s is not supported for this model!!\n",__func__);
+}
+static int ssv6xxx_chg_pad_setting(struct ssv_hw *sh)
+{
+    struct ssv_softc *sc = sh->sc;
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_HAL,
+             "%s is not supported for this model!!\n",__func__);
+    return 0;
+}
+static void ssv6xxx_cmd_cali(struct ssv_hw *sh, int argc, char *argv[])
+{
+    struct ssv_softc *sc = sh->sc;
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_HAL,
+             "%s is not supported for this model!!\n",__func__);
+}
+static void ssv6xxx_cmd_rc(struct ssv_hw *sh, int argc, char *argv[])
+{
+    struct ssv_softc *sc = sh->sc;
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_HAL,
+             "%s is not supported for this model!!\n",__func__);
+}
+static void ssv6xxx_cmd_efuse(struct ssv_hw *sh, int argc, char *argv[])
+{
+    struct ssv_softc *sc = sh->sc;
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_HAL,
+             "%s is not supported for this model!!\n",__func__);
+}
+static void ssv6xxx_set_sifs(struct ssv_hw *sh, int band)
+{
+    struct ssv_softc *sc = sh->sc;
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_HAL,
+             "%s is not supported for this model!!\n",__func__);
+}
+static void ssv6xxx_cmd_loopback(struct ssv_hw *sh, int argc, char *argv[])
+{
+    struct ssv_softc *sc = sh->sc;
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_HAL,
+             "%s is not supported for this model!!\n",__func__);
+}
+static void ssv6xxx_cmd_loopback_start(struct ssv_hw *sh)
+{
+    struct ssv_softc *sc = sh->sc;
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_HAL,
+             "%s is not supported for this model!!\n",__func__);
+}
+static void ssv6xxx_cmd_loopback_setup_env(struct ssv_hw *sh)
+{
+    struct ssv_softc *sc = sh->sc;
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_HAL,
+             "%s is not supported for this model!!\n",__func__);
+}
+static int ssv6xxx_chk_lpbk_rx_rate_desc(struct ssv_hw *sh, struct sk_buff *skb)
+{
+    struct ssv_softc *sc = sh->sc;
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_HAL,
+             "%s is not supported for this model!!\n",__func__);
+    return 0;
+}
+static void ssv6xxx_cmd_hwinfo(struct ssv_hw *sh, int argc, char *argv[])
+{
+    struct ssv_softc *sc = sh->sc;
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_HAL,
+             "%s is not supported for this model!!\n",__func__);
+}
+static int ssv6xxx_get_sec_decode_err(struct sk_buff *skb, bool *mic_err, bool *decode_err)
+{
+    return 0;
+}
+static void ssv6xxx_cmd_cci(struct ssv_hw *sh, int argc, char *argv[])
+{
+    struct ssv_softc *sc = sh->sc;
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_HAL,
+             "%s is not supported for this model!!\n",__func__);
+}
+static void ssv6xxx_cmd_txgen(struct ssv_hw *sh)
+{
+    struct ssv_softc *sc = sh->sc;
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_HAL,
+             "%s is not supported for this model!!\n",__func__);
+}
+static void ssv6xxx_cmd_rf(struct ssv_hw *sh, int argc, char *argv[])
+{
+    struct ssv_softc *sc = sh->sc;
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_HAL,
+             "%s is not supported for this model!!\n",__func__);
+}
+static void ssv6xxx_cmd_hwq_limit(struct ssv_hw *sh, int argc, char *argv[])
+{
+    struct ssv_softc *sc = sh->sc;
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_HAL,
+             "%s is not supported for this model!!\n",__func__);
+}
+static void ssv6xxx_update_rf_pwr(struct ssv_softc *sc)
+{
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_HAL,
+             "%s is not supported for this model!!\n",__func__);
+}
+static void tu_ssv6xxx_init_gpio_cfg(struct ssv_hw *sh)
+{
+    struct ssv_softc *sc = sh->sc;
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_HAL,
+             "%s is not supported for this model!!\n",__func__);
+}
+static void ssv6xxx_flash_read_all_map(struct ssv_hw *sh)
+{
+    struct ssv_softc *sc = sh->sc;
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_HAL,
+             "%s is not supported for this model!!\n",__func__);
+}
+static void ssv6xxx_write_efuse(struct ssv_hw *sh, u8 *data, u8 data_length)
+{
+    struct ssv_softc *sc = sh->sc;
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_HAL,
+             "%s is not supported for this model!!\n",__func__);
+}
+static int ssv6xxx_update_efuse_setting(struct ssv_hw *sh)
+{
+    struct ssv_softc *sc = sh->sc;
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_HAL,
+             "%s is not supported for this model!!\n",__func__);
+    return 0;
+}
+static void ssv6xxx_update_product_hw_setting(struct ssv_hw *sh)
+{
+    struct ssv_softc *sc = sh->sc;
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_HAL,
+             "%s is not supported for this model!!\n",__func__);
+}
+static void ssv6xxx_do_temperature_compensation(struct ssv_hw *sh)
+{
+    struct ssv_softc *sc = sh->sc;
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_HAL,
+             "%s is not supported for this model!!\n",__func__);
+}
+void ssv6xxx_set_on3_enable(struct ssv_hw *sh, bool val)
+{
+    struct ssv_softc *sc = sh->sc;
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_HAL,
+             "%s is not supported for this model!!\n",__func__);
+}
+static void ssv6xxx_cmd_spectrum(struct ssv_hw *sh)
+{
+    struct ssv_softc *sc = sh->sc;
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_HAL,
+             "%s is not supported for this model!!\n",__func__);
+}
+static void ssv6xxx_wait_usb_rom_ready(struct ssv_hw *sh)
+{
+    struct ssv_softc *sc = sh->sc;
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_HAL,
+             "%s is not supported for this model!!\n",__func__);
+}
+static void ssv6xxx_detach_usb_hci(struct ssv_hw *sh)
+{
+    struct ssv_softc *sc = sh->sc;
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_HAL,
+             "%s is not supported for this model!!\n",__func__);
+}
+static void ssv6xxx_pll_chk(struct ssv_hw *sh)
+{
+    struct ssv_softc *sc = sh->sc;
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_HAL,
+             "%s is not supported for this model!!\n",__func__);
+}
+static void ssv6xxx_attach_common_hal (struct ssv_hal_ops *hal_ops)
+{
+    hal_ops->do_iq_cal = ssv6xxx_do_iq_cal;
+    hal_ops->dpd_enable = ssv6xxx_dpd_enable;
+    hal_ops->init_ch_cfg = tu_ssv6xxx_init_ch_cfg;
+    hal_ops->init_iqk = tu_ssv6xxx_init_iqk;
+    hal_ops->save_default_ipd_chcfg = ssv6xxx_save_default_ipd_chcfg;
+    hal_ops->chg_ipd_phyinfo = ssv6xxx_chg_ipd_phyinfo;
+    hal_ops->update_cfg_hw_patch = ssv6xxx_update_cfg_hw_patch;
+    hal_ops->update_hw_config = ssv6xxx_update_hw_config;
+    hal_ops->chg_pad_setting = ssv6xxx_chg_pad_setting;
+    hal_ops->cmd_cali = ssv6xxx_cmd_cali;
+    hal_ops->cmd_rc = ssv6xxx_cmd_rc;
+    hal_ops->cmd_efuse = ssv6xxx_cmd_efuse;
+    hal_ops->set_sifs = ssv6xxx_set_sifs;
+    hal_ops->cmd_loopback = ssv6xxx_cmd_loopback;
+    hal_ops->cmd_loopback_start = ssv6xxx_cmd_loopback_start;
+    hal_ops->cmd_loopback_setup_env = ssv6xxx_cmd_loopback_setup_env;
+    hal_ops->chk_lpbk_rx_rate_desc = ssv6xxx_chk_lpbk_rx_rate_desc;
+    hal_ops->cmd_hwinfo = ssv6xxx_cmd_hwinfo;
+    hal_ops->get_sec_decode_err = ssv6xxx_get_sec_decode_err;
+    hal_ops->cmd_cci = ssv6xxx_cmd_cci;
+    hal_ops->cmd_txgen = ssv6xxx_cmd_txgen;
+    hal_ops->cmd_rf = ssv6xxx_cmd_rf;
+    hal_ops->cmd_hwq_limit = ssv6xxx_cmd_hwq_limit;
+    hal_ops->update_rf_pwr = ssv6xxx_update_rf_pwr;
+    hal_ops->init_gpio_cfg = tu_ssv6xxx_init_gpio_cfg;
+    hal_ops->flash_read_all_map = ssv6xxx_flash_read_all_map;
+    hal_ops->write_efuse = ssv6xxx_write_efuse;
+    hal_ops->update_efuse_setting = ssv6xxx_update_efuse_setting;
+    hal_ops->do_temperature_compensation = ssv6xxx_do_temperature_compensation;
+    hal_ops->update_product_hw_setting = ssv6xxx_update_product_hw_setting;
+    hal_ops->set_on3_enable = ssv6xxx_set_on3_enable;
+    hal_ops->cmd_spectrum = ssv6xxx_cmd_spectrum;
+    hal_ops->wait_usb_rom_ready = ssv6xxx_wait_usb_rom_ready;
+    hal_ops->detach_usb_hci = ssv6xxx_detach_usb_hci;
+    hal_ops->pll_chk = ssv6xxx_pll_chk;
+}
+int tu_ssv6xxx_init_hal(struct ssv_softc *sc)
+{
+    struct ssv_hw *sh;
+    int ret = 0;
+    struct ssv_hal_ops *hal_ops = NULL;
+    extern void ssv_attach_ssv6051(struct ssv_softc *sc, struct ssv_hal_ops *hal_ops);
+    extern void ssv_attach_ssv6006(struct ssv_softc *sc, struct ssv_hal_ops *hal_ops);
+    bool chip_supportted = false;
+    struct ssv6xxx_platform_data *priv = sc->dev->platform_data;
+    hal_ops = kzalloc(sizeof(struct ssv_hal_ops), GFP_KERNEL);
+    if (hal_ops == NULL) {
+        printk("%s(): Fail to alloc hal_ops\n", __FUNCTION__);
+        return -ENOMEM;
+    }
+    ssv6xxx_attach_common_hal(hal_ops);
+#ifdef SSV_SUPPORT_SSV6051
+    if ( strstr(priv->chip_id, SSV6051_CHIP)
+         || strstr(priv->chip_id, SSV6051_CHIP_ECO3)) {
+        printk(KERN_INFO"Attach SSV6051 family HAL function \n");
+        ssv_attach_ssv6051(sc, hal_ops);
+        chip_supportted = true;
+    }
+#endif
+#ifdef SSV_SUPPORT_SSV6006
+    if ( strstr(priv->chip_id, SSV6006)
+         || strstr(priv->chip_id, SSV6006C)
+         || strstr(priv->chip_id, SSV6006D)) {
+        printk(KERN_INFO"Attach SSV6006 family HAL function  \n");
+        ssv_attach_ssv6006(sc, hal_ops);
+        chip_supportted = true;
+    }
+#endif
+    if (!chip_supportted) {
+        printk(KERN_ERR "Chip \"%s\" is not supported by this driver\n", priv->chip_id);
+        ret = -EINVAL;
+        goto out;
+    }
+    sh = hal_ops->alloc_hw();
+    if (sh == NULL) {
+        ret = -ENOMEM;
+        goto out;
+    }
+    memcpy(&sh->hal_ops, hal_ops, sizeof(struct ssv_hal_ops));
+    sc->sh = sh;
+    sh->sc = sc;
+    INIT_LIST_HEAD(&sh->hw_cfg);
+    mutex_init(&sh->hw_cfg_mutex);
+    sh->priv = sc->dev->platform_data;
+    sh->hci.dev = sc->dev;
+    sh->hci.if_ops = sh->priv->ops;
+    sh->hci.skb_alloc = ssv_skb_alloc;
+    sh->hci.skb_free = ssv_skb_free;
+    sh->hci.hci_rx_cb = ssv6200_rx;
+    sh->hci.hci_is_rx_q_full = ssv6200_is_rx_q_full;
+    sh->priv->skb_alloc = ssv_skb_alloc_ex;
+    sh->priv->skb_free = ssv_skb_free;
+    sh->priv->skb_param = sc;
+#ifdef CONFIG_PM
+    sh->priv->suspend = ssv6xxx_power_sleep;
+    sh->priv->resume = ssv6xxx_power_awake;
+    sh->priv->pm_param = sc;
+#endif
+    sh->priv->enable_usb_acc = ssv6xxx_enable_usb_acc;
+    sh->priv->disable_usb_acc = ssv6xxx_disable_usb_acc;
+    sh->priv->jump_to_rom = ssv6xxx_jump_to_rom;
+    sh->priv->usb_param = sc;
+    sh->priv->rx_burstread_size = ssv6xxx_rx_burstread_size;
+    sh->priv->rx_burstread_param = sc;
+    sh->hci.sc = sc;
+    sh->hci.sh = sh;
+out:
+    kfree(hal_ops);
+    return ret;
+}
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/ssv6006C_aux.h b/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/ssv6006C_aux.h
new file mode 100644
index 000000000..1a0076ce0
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/ssv6006C_aux.h
@@ -0,0 +1,34665 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define FBUS_DMAC_SAR0_MSK 0xffffffff
+#define FBUS_DMAC_SAR0_I_MSK 0x00000000
+#define FBUS_DMAC_SAR0_SFT 0
+#define FBUS_DMAC_SAR0_HI 31
+#define FBUS_DMAC_SAR0_SZ 32
+#define FBUS_DMAC_DAR0_MSK 0xffffffff
+#define FBUS_DMAC_DAR0_I_MSK 0x00000000
+#define FBUS_DMAC_DAR0_SFT 0
+#define FBUS_DMAC_DAR0_HI 31
+#define FBUS_DMAC_DAR0_SZ 32
+#define FBUS_DMAC_INTR_EN0_MSK 0x00000001
+#define FBUS_DMAC_INTR_EN0_I_MSK 0xfffffffe
+#define FBUS_DMAC_INTR_EN0_SFT 0
+#define FBUS_DMAC_INTR_EN0_HI 0
+#define FBUS_DMAC_INTR_EN0_SZ 1
+#define FBUS_DMAC_DST_TR_WIDTH0_MSK 0x0000000e
+#define FBUS_DMAC_DST_TR_WIDTH0_I_MSK 0xfffffff1
+#define FBUS_DMAC_DST_TR_WIDTH0_SFT 1
+#define FBUS_DMAC_DST_TR_WIDTH0_HI 3
+#define FBUS_DMAC_DST_TR_WIDTH0_SZ 3
+#define FBUS_DMAC_SRC_TR_WIDTH0_MSK 0x00000070
+#define FBUS_DMAC_SRC_TR_WIDTH0_I_MSK 0xffffff8f
+#define FBUS_DMAC_SRC_TR_WIDTH0_SFT 4
+#define FBUS_DMAC_SRC_TR_WIDTH0_HI 6
+#define FBUS_DMAC_SRC_TR_WIDTH0_SZ 3
+#define FBUS_DMAC_DINC0_MSK 0x00000180
+#define FBUS_DMAC_DINC0_I_MSK 0xfffffe7f
+#define FBUS_DMAC_DINC0_SFT 7
+#define FBUS_DMAC_DINC0_HI 8
+#define FBUS_DMAC_DINC0_SZ 2
+#define FBUS_DMAC_SINC0_MSK 0x00000600
+#define FBUS_DMAC_SINC0_I_MSK 0xfffff9ff
+#define FBUS_DMAC_SINC0_SFT 9
+#define FBUS_DMAC_SINC0_HI 10
+#define FBUS_DMAC_SINC0_SZ 2
+#define FBUS_DMAC_DST_MSIZE0_MSK 0x00003800
+#define FBUS_DMAC_DST_MSIZE0_I_MSK 0xffffc7ff
+#define FBUS_DMAC_DST_MSIZE0_SFT 11
+#define FBUS_DMAC_DST_MSIZE0_HI 13
+#define FBUS_DMAC_DST_MSIZE0_SZ 3
+#define FBUS_DMAC_SRC_MSIZE0_MSK 0x0001c000
+#define FBUS_DMAC_SRC_MSIZE0_I_MSK 0xfffe3fff
+#define FBUS_DMAC_SRC_MSIZE0_SFT 14
+#define FBUS_DMAC_SRC_MSIZE0_HI 16
+#define FBUS_DMAC_SRC_MSIZE0_SZ 3
+#define FBUS_DMAC_FC_MODE0_MSK 0x00700000
+#define FBUS_DMAC_FC_MODE0_I_MSK 0xff8fffff
+#define FBUS_DMAC_FC_MODE0_SFT 20
+#define FBUS_DMAC_FC_MODE0_HI 22
+#define FBUS_DMAC_FC_MODE0_SZ 3
+#define FBUS_DMAC_BLOCK0_MSK 0x00000fff
+#define FBUS_DMAC_BLOCK0_I_MSK 0xfffff000
+#define FBUS_DMAC_BLOCK0_SFT 0
+#define FBUS_DMAC_BLOCK0_HI 11
+#define FBUS_DMAC_BLOCK0_SZ 12
+#define FBUS_DMAC_CH0_PRIOR_MSK 0x00000020
+#define FBUS_DMAC_CH0_PRIOR_I_MSK 0xffffffdf
+#define FBUS_DMAC_CH0_PRIOR_SFT 5
+#define FBUS_DMAC_CH0_PRIOR_HI 5
+#define FBUS_DMAC_CH0_PRIOR_SZ 1
+#define FBUS_DMAC_HS_SEL_DST0_MSK 0x00000400
+#define FBUS_DMAC_HS_SEL_DST0_I_MSK 0xfffffbff
+#define FBUS_DMAC_HS_SEL_DST0_SFT 10
+#define FBUS_DMAC_HS_SEL_DST0_HI 10
+#define FBUS_DMAC_HS_SEL_DST0_SZ 1
+#define FBUS_DMAC_HS_SEL_SRC0_MSK 0x00000800
+#define FBUS_DMAC_HS_SEL_SRC0_I_MSK 0xfffff7ff
+#define FBUS_DMAC_HS_SEL_SRC0_SFT 11
+#define FBUS_DMAC_HS_SEL_SRC0_HI 11
+#define FBUS_DMAC_HS_SEL_SRC0_SZ 1
+#define FBUS_DMAC_MAX_BURST_LEN0_MSK 0x3ff00000
+#define FBUS_DMAC_MAX_BURST_LEN0_I_MSK 0xc00fffff
+#define FBUS_DMAC_MAX_BURST_LEN0_SFT 20
+#define FBUS_DMAC_MAX_BURST_LEN0_HI 29
+#define FBUS_DMAC_MAX_BURST_LEN0_SZ 10
+#define FBUS_DMAC_SRC_HS_BUS_SEL0_MSK 0x00000380
+#define FBUS_DMAC_SRC_HS_BUS_SEL0_I_MSK 0xfffffc7f
+#define FBUS_DMAC_SRC_HS_BUS_SEL0_SFT 7
+#define FBUS_DMAC_SRC_HS_BUS_SEL0_HI 9
+#define FBUS_DMAC_SRC_HS_BUS_SEL0_SZ 3
+#define FBUS_DMAC_DST_HS_BUS_SEL0_MSK 0x00003800
+#define FBUS_DMAC_DST_HS_BUS_SEL0_I_MSK 0xffffc7ff
+#define FBUS_DMAC_DST_HS_BUS_SEL0_SFT 11
+#define FBUS_DMAC_DST_HS_BUS_SEL0_HI 13
+#define FBUS_DMAC_DST_HS_BUS_SEL0_SZ 3
+#define FBUS_DMAC_SAR1_MSK 0xffffffff
+#define FBUS_DMAC_SAR1_I_MSK 0x00000000
+#define FBUS_DMAC_SAR1_SFT 0
+#define FBUS_DMAC_SAR1_HI 31
+#define FBUS_DMAC_SAR1_SZ 32
+#define FBUS_DMAC_DAR1_MSK 0xffffffff
+#define FBUS_DMAC_DAR1_I_MSK 0x00000000
+#define FBUS_DMAC_DAR1_SFT 0
+#define FBUS_DMAC_DAR1_HI 31
+#define FBUS_DMAC_DAR1_SZ 32
+#define FBUS_DMAC_INTR_EN1_MSK 0x00000001
+#define FBUS_DMAC_INTR_EN1_I_MSK 0xfffffffe
+#define FBUS_DMAC_INTR_EN1_SFT 0
+#define FBUS_DMAC_INTR_EN1_HI 0
+#define FBUS_DMAC_INTR_EN1_SZ 1
+#define FBUS_DMAC_DST_TR_WIDTH1_MSK 0x0000000e
+#define FBUS_DMAC_DST_TR_WIDTH1_I_MSK 0xfffffff1
+#define FBUS_DMAC_DST_TR_WIDTH1_SFT 1
+#define FBUS_DMAC_DST_TR_WIDTH1_HI 3
+#define FBUS_DMAC_DST_TR_WIDTH1_SZ 3
+#define FBUS_DMAC_SRC_TR_WIDTH1_MSK 0x00000070
+#define FBUS_DMAC_SRC_TR_WIDTH1_I_MSK 0xffffff8f
+#define FBUS_DMAC_SRC_TR_WIDTH1_SFT 4
+#define FBUS_DMAC_SRC_TR_WIDTH1_HI 6
+#define FBUS_DMAC_SRC_TR_WIDTH1_SZ 3
+#define FBUS_DMAC_DINC1_MSK 0x00000180
+#define FBUS_DMAC_DINC1_I_MSK 0xfffffe7f
+#define FBUS_DMAC_DINC1_SFT 7
+#define FBUS_DMAC_DINC1_HI 8
+#define FBUS_DMAC_DINC1_SZ 2
+#define FBUS_DMAC_SINC1_MSK 0x00000600
+#define FBUS_DMAC_SINC1_I_MSK 0xfffff9ff
+#define FBUS_DMAC_SINC1_SFT 9
+#define FBUS_DMAC_SINC1_HI 10
+#define FBUS_DMAC_SINC1_SZ 2
+#define FBUS_DMAC_DST_MSIZE1_MSK 0x00003800
+#define FBUS_DMAC_DST_MSIZE1_I_MSK 0xffffc7ff
+#define FBUS_DMAC_DST_MSIZE1_SFT 11
+#define FBUS_DMAC_DST_MSIZE1_HI 13
+#define FBUS_DMAC_DST_MSIZE1_SZ 3
+#define FBUS_DMAC_SRC_MSIZE1_MSK 0x0001c000
+#define FBUS_DMAC_SRC_MSIZE1_I_MSK 0xfffe3fff
+#define FBUS_DMAC_SRC_MSIZE1_SFT 14
+#define FBUS_DMAC_SRC_MSIZE1_HI 16
+#define FBUS_DMAC_SRC_MSIZE1_SZ 3
+#define FBUS_DMAC_FC_MODE1_MSK 0x00700000
+#define FBUS_DMAC_FC_MODE1_I_MSK 0xff8fffff
+#define FBUS_DMAC_FC_MODE1_SFT 20
+#define FBUS_DMAC_FC_MODE1_HI 22
+#define FBUS_DMAC_FC_MODE1_SZ 3
+#define FBUS_DMAC_BLOCK1_MSK 0x00000fff
+#define FBUS_DMAC_BLOCK1_I_MSK 0xfffff000
+#define FBUS_DMAC_BLOCK1_SFT 0
+#define FBUS_DMAC_BLOCK1_HI 11
+#define FBUS_DMAC_BLOCK1_SZ 12
+#define FBUS_DMAC_CH1_PRIOR_MSK 0x00000020
+#define FBUS_DMAC_CH1_PRIOR_I_MSK 0xffffffdf
+#define FBUS_DMAC_CH1_PRIOR_SFT 5
+#define FBUS_DMAC_CH1_PRIOR_HI 5
+#define FBUS_DMAC_CH1_PRIOR_SZ 1
+#define FBUS_DMAC_HS_SEL_DST1_MSK 0x00000400
+#define FBUS_DMAC_HS_SEL_DST1_I_MSK 0xfffffbff
+#define FBUS_DMAC_HS_SEL_DST1_SFT 10
+#define FBUS_DMAC_HS_SEL_DST1_HI 10
+#define FBUS_DMAC_HS_SEL_DST1_SZ 1
+#define FBUS_DMAC_HS_SEL_SRC1_MSK 0x00000800
+#define FBUS_DMAC_HS_SEL_SRC1_I_MSK 0xfffff7ff
+#define FBUS_DMAC_HS_SEL_SRC1_SFT 11
+#define FBUS_DMAC_HS_SEL_SRC1_HI 11
+#define FBUS_DMAC_HS_SEL_SRC1_SZ 1
+#define FBUS_DMAC_MAX_BURST_LEN1_MSK 0x3ff00000
+#define FBUS_DMAC_MAX_BURST_LEN1_I_MSK 0xc00fffff
+#define FBUS_DMAC_MAX_BURST_LEN1_SFT 20
+#define FBUS_DMAC_MAX_BURST_LEN1_HI 29
+#define FBUS_DMAC_MAX_BURST_LEN1_SZ 10
+#define FBUS_DMAC_SRC_HS_BUS_SEL1_MSK 0x00000380
+#define FBUS_DMAC_SRC_HS_BUS_SEL1_I_MSK 0xfffffc7f
+#define FBUS_DMAC_SRC_HS_BUS_SEL1_SFT 7
+#define FBUS_DMAC_SRC_HS_BUS_SEL1_HI 9
+#define FBUS_DMAC_SRC_HS_BUS_SEL1_SZ 3
+#define FBUS_DMAC_DST_HS_BUS_SEL1_MSK 0x00003800
+#define FBUS_DMAC_DST_HS_BUS_SEL1_I_MSK 0xffffc7ff
+#define FBUS_DMAC_DST_HS_BUS_SEL1_SFT 11
+#define FBUS_DMAC_DST_HS_BUS_SEL1_HI 13
+#define FBUS_DMAC_DST_HS_BUS_SEL1_SZ 3
+#define FBUS_DMAC_CH_RAW_TR_MSK 0xffffffff
+#define FBUS_DMAC_CH_RAW_TR_I_MSK 0x00000000
+#define FBUS_DMAC_CH_RAW_TR_SFT 0
+#define FBUS_DMAC_CH_RAW_TR_HI 31
+#define FBUS_DMAC_CH_RAW_TR_SZ 32
+#define FBUS_DMAC_CH_ERR_TR_MSK 0xffffffff
+#define FBUS_DMAC_CH_ERR_TR_I_MSK 0x00000000
+#define FBUS_DMAC_CH_ERR_TR_SFT 0
+#define FBUS_DMAC_CH_ERR_TR_HI 31
+#define FBUS_DMAC_CH_ERR_TR_SZ 32
+#define FBUS_DMAC_CH_STATUSTR_TR_MSK 0xffffffff
+#define FBUS_DMAC_CH_STATUSTR_TR_I_MSK 0x00000000
+#define FBUS_DMAC_CH_STATUSTR_TR_SFT 0
+#define FBUS_DMAC_CH_STATUSTR_TR_HI 31
+#define FBUS_DMAC_CH_STATUSTR_TR_SZ 32
+#define FBUS_DMAC_CH_STATUSERR_TR_MSK 0xffffffff
+#define FBUS_DMAC_CH_STATUSERR_TR_I_MSK 0x00000000
+#define FBUS_DMAC_CH_STATUSERR_TR_SFT 0
+#define FBUS_DMAC_CH_STATUSERR_TR_HI 31
+#define FBUS_DMAC_CH_STATUSERR_TR_SZ 32
+#define FBUS_DMAC_CH_DEMASK_TR_MSK 0xffffffff
+#define FBUS_DMAC_CH_DEMASK_TR_I_MSK 0x00000000
+#define FBUS_DMAC_CH_DEMASK_TR_SFT 0
+#define FBUS_DMAC_CH_DEMASK_TR_HI 31
+#define FBUS_DMAC_CH_DEMASK_TR_SZ 32
+#define FBUS_DMAC_CH_DEMASK_ERR_MSK 0xffffffff
+#define FBUS_DMAC_CH_DEMASK_ERR_I_MSK 0x00000000
+#define FBUS_DMAC_CH_DEMASK_ERR_SFT 0
+#define FBUS_DMAC_CH_DEMASK_ERR_HI 31
+#define FBUS_DMAC_CH_DEMASK_ERR_SZ 32
+#define FBUS_DMAC_CH0_CLR_TR_MSK 0x00000001
+#define FBUS_DMAC_CH0_CLR_TR_I_MSK 0xfffffffe
+#define FBUS_DMAC_CH0_CLR_TR_SFT 0
+#define FBUS_DMAC_CH0_CLR_TR_HI 0
+#define FBUS_DMAC_CH0_CLR_TR_SZ 1
+#define FBUS_DMAC_CH1_CLR_TR_MSK 0x00000002
+#define FBUS_DMAC_CH1_CLR_TR_I_MSK 0xfffffffd
+#define FBUS_DMAC_CH1_CLR_TR_SFT 1
+#define FBUS_DMAC_CH1_CLR_TR_HI 1
+#define FBUS_DMAC_CH1_CLR_TR_SZ 1
+#define FBUS_DMAC_CH0_CLR_ERR_MSK 0x00000001
+#define FBUS_DMAC_CH0_CLR_ERR_I_MSK 0xfffffffe
+#define FBUS_DMAC_CH0_CLR_ERR_SFT 0
+#define FBUS_DMAC_CH0_CLR_ERR_HI 0
+#define FBUS_DMAC_CH0_CLR_ERR_SZ 1
+#define FBUS_DMAC_CH1_CLR_ERR_MSK 0x00000002
+#define FBUS_DMAC_CH1_CLR_ERR_I_MSK 0xfffffffd
+#define FBUS_DMAC_CH1_CLR_ERR_SFT 1
+#define FBUS_DMAC_CH1_CLR_ERR_HI 1
+#define FBUS_DMAC_CH1_CLR_ERR_SZ 1
+#define FBUS_DMAC_DISEN_SHS_SRC_REQ_MSK 0x0000ffff
+#define FBUS_DMAC_DISEN_SHS_SRC_REQ_I_MSK 0xffff0000
+#define FBUS_DMAC_DISEN_SHS_SRC_REQ_SFT 0
+#define FBUS_DMAC_DISEN_SHS_SRC_REQ_HI 15
+#define FBUS_DMAC_DISEN_SHS_SRC_REQ_SZ 16
+#define FBUS_DMAC_DISEN_SHS_DST_REQ_MSK 0x0000ffff
+#define FBUS_DMAC_DISEN_SHS_DST_REQ_I_MSK 0xffff0000
+#define FBUS_DMAC_DISEN_SHS_DST_REQ_SFT 0
+#define FBUS_DMAC_DISEN_SHS_DST_REQ_HI 15
+#define FBUS_DMAC_DISEN_SHS_DST_REQ_SZ 16
+#define FBUS_DMAC_DISEN_SHS_SRC_SREQ_MSK 0x0000ffff
+#define FBUS_DMAC_DISEN_SHS_SRC_SREQ_I_MSK 0xffff0000
+#define FBUS_DMAC_DISEN_SHS_SRC_SREQ_SFT 0
+#define FBUS_DMAC_DISEN_SHS_SRC_SREQ_HI 15
+#define FBUS_DMAC_DISEN_SHS_SRC_SREQ_SZ 16
+#define FBUS_DMAC_DISEN_SHS_DST_SREQ_MSK 0x0000ffff
+#define FBUS_DMAC_DISEN_SHS_DST_SREQ_I_MSK 0xffff0000
+#define FBUS_DMAC_DISEN_SHS_DST_SREQ_SFT 0
+#define FBUS_DMAC_DISEN_SHS_DST_SREQ_HI 15
+#define FBUS_DMAC_DISEN_SHS_DST_SREQ_SZ 16
+#define FBUS_DMAC_EN_MSK 0x00000001
+#define FBUS_DMAC_EN_I_MSK 0xfffffffe
+#define FBUS_DMAC_EN_SFT 0
+#define FBUS_DMAC_EN_HI 0
+#define FBUS_DMAC_EN_SZ 1
+#define FBUS_DMAC_CH_EN_MSK 0x0000ffff
+#define FBUS_DMAC_CH_EN_I_MSK 0xffff0000
+#define FBUS_DMAC_CH_EN_SFT 0
+#define FBUS_DMAC_CH_EN_HI 15
+#define FBUS_DMAC_CH_EN_SZ 16
+#define SBUS_DMAC_SAR0_MSK 0xffffffff
+#define SBUS_DMAC_SAR0_I_MSK 0x00000000
+#define SBUS_DMAC_SAR0_SFT 0
+#define SBUS_DMAC_SAR0_HI 31
+#define SBUS_DMAC_SAR0_SZ 32
+#define SBUS_DMAC_DAR0_MSK 0xffffffff
+#define SBUS_DMAC_DAR0_I_MSK 0x00000000
+#define SBUS_DMAC_DAR0_SFT 0
+#define SBUS_DMAC_DAR0_HI 31
+#define SBUS_DMAC_DAR0_SZ 32
+#define SBUS_DMAC_INTR_EN0_MSK 0x00000001
+#define SBUS_DMAC_INTR_EN0_I_MSK 0xfffffffe
+#define SBUS_DMAC_INTR_EN0_SFT 0
+#define SBUS_DMAC_INTR_EN0_HI 0
+#define SBUS_DMAC_INTR_EN0_SZ 1
+#define SBUS_DMAC_DST_TR_WIDTH0_MSK 0x0000000e
+#define SBUS_DMAC_DST_TR_WIDTH0_I_MSK 0xfffffff1
+#define SBUS_DMAC_DST_TR_WIDTH0_SFT 1
+#define SBUS_DMAC_DST_TR_WIDTH0_HI 3
+#define SBUS_DMAC_DST_TR_WIDTH0_SZ 3
+#define SBUS_DMAC_SRC_TR_WIDTH0_MSK 0x00000070
+#define SBUS_DMAC_SRC_TR_WIDTH0_I_MSK 0xffffff8f
+#define SBUS_DMAC_SRC_TR_WIDTH0_SFT 4
+#define SBUS_DMAC_SRC_TR_WIDTH0_HI 6
+#define SBUS_DMAC_SRC_TR_WIDTH0_SZ 3
+#define SBUS_DMAC_DINC0_MSK 0x00000180
+#define SBUS_DMAC_DINC0_I_MSK 0xfffffe7f
+#define SBUS_DMAC_DINC0_SFT 7
+#define SBUS_DMAC_DINC0_HI 8
+#define SBUS_DMAC_DINC0_SZ 2
+#define SBUS_DMAC_SINC0_MSK 0x00000600
+#define SBUS_DMAC_SINC0_I_MSK 0xfffff9ff
+#define SBUS_DMAC_SINC0_SFT 9
+#define SBUS_DMAC_SINC0_HI 10
+#define SBUS_DMAC_SINC0_SZ 2
+#define SBUS_DMAC_DST_MSIZE0_MSK 0x00003800
+#define SBUS_DMAC_DST_MSIZE0_I_MSK 0xffffc7ff
+#define SBUS_DMAC_DST_MSIZE0_SFT 11
+#define SBUS_DMAC_DST_MSIZE0_HI 13
+#define SBUS_DMAC_DST_MSIZE0_SZ 3
+#define SBUS_DMAC_SRC_MSIZE0_MSK 0x0001c000
+#define SBUS_DMAC_SRC_MSIZE0_I_MSK 0xfffe3fff
+#define SBUS_DMAC_SRC_MSIZE0_SFT 14
+#define SBUS_DMAC_SRC_MSIZE0_HI 16
+#define SBUS_DMAC_SRC_MSIZE0_SZ 3
+#define SBUS_DMAC_FC_MODE0_MSK 0x00700000
+#define SBUS_DMAC_FC_MODE0_I_MSK 0xff8fffff
+#define SBUS_DMAC_FC_MODE0_SFT 20
+#define SBUS_DMAC_FC_MODE0_HI 22
+#define SBUS_DMAC_FC_MODE0_SZ 3
+#define SBUS_DMAC_BLOCK0_MSK 0x00000fff
+#define SBUS_DMAC_BLOCK0_I_MSK 0xfffff000
+#define SBUS_DMAC_BLOCK0_SFT 0
+#define SBUS_DMAC_BLOCK0_HI 11
+#define SBUS_DMAC_BLOCK0_SZ 12
+#define SBUS_DMAC_CH0_PRIOR_MSK 0x00000020
+#define SBUS_DMAC_CH0_PRIOR_I_MSK 0xffffffdf
+#define SBUS_DMAC_CH0_PRIOR_SFT 5
+#define SBUS_DMAC_CH0_PRIOR_HI 5
+#define SBUS_DMAC_CH0_PRIOR_SZ 1
+#define SBUS_DMAC_HS_SEL_DST0_MSK 0x00000400
+#define SBUS_DMAC_HS_SEL_DST0_I_MSK 0xfffffbff
+#define SBUS_DMAC_HS_SEL_DST0_SFT 10
+#define SBUS_DMAC_HS_SEL_DST0_HI 10
+#define SBUS_DMAC_HS_SEL_DST0_SZ 1
+#define SBUS_DMAC_HS_SEL_SRC0_MSK 0x00000800
+#define SBUS_DMAC_HS_SEL_SRC0_I_MSK 0xfffff7ff
+#define SBUS_DMAC_HS_SEL_SRC0_SFT 11
+#define SBUS_DMAC_HS_SEL_SRC0_HI 11
+#define SBUS_DMAC_HS_SEL_SRC0_SZ 1
+#define SBUS_DMAC_MAX_BURST_LEN0_MSK 0x3ff00000
+#define SBUS_DMAC_MAX_BURST_LEN0_I_MSK 0xc00fffff
+#define SBUS_DMAC_MAX_BURST_LEN0_SFT 20
+#define SBUS_DMAC_MAX_BURST_LEN0_HI 29
+#define SBUS_DMAC_MAX_BURST_LEN0_SZ 10
+#define SBUS_DMAC_SRC_HS_BUS_SEL0_MSK 0x00000380
+#define SBUS_DMAC_SRC_HS_BUS_SEL0_I_MSK 0xfffffc7f
+#define SBUS_DMAC_SRC_HS_BUS_SEL0_SFT 7
+#define SBUS_DMAC_SRC_HS_BUS_SEL0_HI 9
+#define SBUS_DMAC_SRC_HS_BUS_SEL0_SZ 3
+#define SBUS_DMAC_DST_HS_BUS_SEL0_MSK 0x00003800
+#define SBUS_DMAC_DST_HS_BUS_SEL0_I_MSK 0xffffc7ff
+#define SBUS_DMAC_DST_HS_BUS_SEL0_SFT 11
+#define SBUS_DMAC_DST_HS_BUS_SEL0_HI 13
+#define SBUS_DMAC_DST_HS_BUS_SEL0_SZ 3
+#define SBUS_DMAC_SAR1_MSK 0xffffffff
+#define SBUS_DMAC_SAR1_I_MSK 0x00000000
+#define SBUS_DMAC_SAR1_SFT 0
+#define SBUS_DMAC_SAR1_HI 31
+#define SBUS_DMAC_SAR1_SZ 32
+#define SBUS_DMAC_DAR1_MSK 0xffffffff
+#define SBUS_DMAC_DAR1_I_MSK 0x00000000
+#define SBUS_DMAC_DAR1_SFT 0
+#define SBUS_DMAC_DAR1_HI 31
+#define SBUS_DMAC_DAR1_SZ 32
+#define SBUS_DMAC_INTR_EN1_MSK 0x00000001
+#define SBUS_DMAC_INTR_EN1_I_MSK 0xfffffffe
+#define SBUS_DMAC_INTR_EN1_SFT 0
+#define SBUS_DMAC_INTR_EN1_HI 0
+#define SBUS_DMAC_INTR_EN1_SZ 1
+#define SBUS_DMAC_DST_TR_WIDTH1_MSK 0x0000000e
+#define SBUS_DMAC_DST_TR_WIDTH1_I_MSK 0xfffffff1
+#define SBUS_DMAC_DST_TR_WIDTH1_SFT 1
+#define SBUS_DMAC_DST_TR_WIDTH1_HI 3
+#define SBUS_DMAC_DST_TR_WIDTH1_SZ 3
+#define SBUS_DMAC_SRC_TR_WIDTH1_MSK 0x00000070
+#define SBUS_DMAC_SRC_TR_WIDTH1_I_MSK 0xffffff8f
+#define SBUS_DMAC_SRC_TR_WIDTH1_SFT 4
+#define SBUS_DMAC_SRC_TR_WIDTH1_HI 6
+#define SBUS_DMAC_SRC_TR_WIDTH1_SZ 3
+#define SBUS_DMAC_DINC1_MSK 0x00000180
+#define SBUS_DMAC_DINC1_I_MSK 0xfffffe7f
+#define SBUS_DMAC_DINC1_SFT 7
+#define SBUS_DMAC_DINC1_HI 8
+#define SBUS_DMAC_DINC1_SZ 2
+#define SBUS_DMAC_SINC1_MSK 0x00000600
+#define SBUS_DMAC_SINC1_I_MSK 0xfffff9ff
+#define SBUS_DMAC_SINC1_SFT 9
+#define SBUS_DMAC_SINC1_HI 10
+#define SBUS_DMAC_SINC1_SZ 2
+#define SBUS_DMAC_DST_MSIZE1_MSK 0x00003800
+#define SBUS_DMAC_DST_MSIZE1_I_MSK 0xffffc7ff
+#define SBUS_DMAC_DST_MSIZE1_SFT 11
+#define SBUS_DMAC_DST_MSIZE1_HI 13
+#define SBUS_DMAC_DST_MSIZE1_SZ 3
+#define SBUS_DMAC_SRC_MSIZE1_MSK 0x0001c000
+#define SBUS_DMAC_SRC_MSIZE1_I_MSK 0xfffe3fff
+#define SBUS_DMAC_SRC_MSIZE1_SFT 14
+#define SBUS_DMAC_SRC_MSIZE1_HI 16
+#define SBUS_DMAC_SRC_MSIZE1_SZ 3
+#define SBUS_DMAC_FC_MODE1_MSK 0x00700000
+#define SBUS_DMAC_FC_MODE1_I_MSK 0xff8fffff
+#define SBUS_DMAC_FC_MODE1_SFT 20
+#define SBUS_DMAC_FC_MODE1_HI 22
+#define SBUS_DMAC_FC_MODE1_SZ 3
+#define SBUS_DMAC_BLOCK1_MSK 0x00000fff
+#define SBUS_DMAC_BLOCK1_I_MSK 0xfffff000
+#define SBUS_DMAC_BLOCK1_SFT 0
+#define SBUS_DMAC_BLOCK1_HI 11
+#define SBUS_DMAC_BLOCK1_SZ 12
+#define SBUS_DMAC_CH1_PRIOR_MSK 0x00000020
+#define SBUS_DMAC_CH1_PRIOR_I_MSK 0xffffffdf
+#define SBUS_DMAC_CH1_PRIOR_SFT 5
+#define SBUS_DMAC_CH1_PRIOR_HI 5
+#define SBUS_DMAC_CH1_PRIOR_SZ 1
+#define SBUS_DMAC_HS_SEL_DST1_MSK 0x00000400
+#define SBUS_DMAC_HS_SEL_DST1_I_MSK 0xfffffbff
+#define SBUS_DMAC_HS_SEL_DST1_SFT 10
+#define SBUS_DMAC_HS_SEL_DST1_HI 10
+#define SBUS_DMAC_HS_SEL_DST1_SZ 1
+#define SBUS_DMAC_HS_SEL_SRC1_MSK 0x00000800
+#define SBUS_DMAC_HS_SEL_SRC1_I_MSK 0xfffff7ff
+#define SBUS_DMAC_HS_SEL_SRC1_SFT 11
+#define SBUS_DMAC_HS_SEL_SRC1_HI 11
+#define SBUS_DMAC_HS_SEL_SRC1_SZ 1
+#define SBUS_DMAC_MAX_BURST_LEN1_MSK 0x3ff00000
+#define SBUS_DMAC_MAX_BURST_LEN1_I_MSK 0xc00fffff
+#define SBUS_DMAC_MAX_BURST_LEN1_SFT 20
+#define SBUS_DMAC_MAX_BURST_LEN1_HI 29
+#define SBUS_DMAC_MAX_BURST_LEN1_SZ 10
+#define SBUS_DMAC_SRC_HS_BUS_SEL1_MSK 0x00000380
+#define SBUS_DMAC_SRC_HS_BUS_SEL1_I_MSK 0xfffffc7f
+#define SBUS_DMAC_SRC_HS_BUS_SEL1_SFT 7
+#define SBUS_DMAC_SRC_HS_BUS_SEL1_HI 9
+#define SBUS_DMAC_SRC_HS_BUS_SEL1_SZ 3
+#define SBUS_DMAC_DST_HS_BUS_SEL1_MSK 0x00003800
+#define SBUS_DMAC_DST_HS_BUS_SEL1_I_MSK 0xffffc7ff
+#define SBUS_DMAC_DST_HS_BUS_SEL1_SFT 11
+#define SBUS_DMAC_DST_HS_BUS_SEL1_HI 13
+#define SBUS_DMAC_DST_HS_BUS_SEL1_SZ 3
+#define SBUS_DMAC_CH_RAW_TR_MSK 0xffffffff
+#define SBUS_DMAC_CH_RAW_TR_I_MSK 0x00000000
+#define SBUS_DMAC_CH_RAW_TR_SFT 0
+#define SBUS_DMAC_CH_RAW_TR_HI 31
+#define SBUS_DMAC_CH_RAW_TR_SZ 32
+#define SBUS_DMAC_CH_ERR_TR_MSK 0xffffffff
+#define SBUS_DMAC_CH_ERR_TR_I_MSK 0x00000000
+#define SBUS_DMAC_CH_ERR_TR_SFT 0
+#define SBUS_DMAC_CH_ERR_TR_HI 31
+#define SBUS_DMAC_CH_ERR_TR_SZ 32
+#define SBUS_DMAC_CH_STATUSTR_TR_MSK 0xffffffff
+#define SBUS_DMAC_CH_STATUSTR_TR_I_MSK 0x00000000
+#define SBUS_DMAC_CH_STATUSTR_TR_SFT 0
+#define SBUS_DMAC_CH_STATUSTR_TR_HI 31
+#define SBUS_DMAC_CH_STATUSTR_TR_SZ 32
+#define SBUS_DMAC_CH_STATUSERR_TR_MSK 0xffffffff
+#define SBUS_DMAC_CH_STATUSERR_TR_I_MSK 0x00000000
+#define SBUS_DMAC_CH_STATUSERR_TR_SFT 0
+#define SBUS_DMAC_CH_STATUSERR_TR_HI 31
+#define SBUS_DMAC_CH_STATUSERR_TR_SZ 32
+#define SBUS_DMAC_CH_DEMASK_TR_MSK 0xffffffff
+#define SBUS_DMAC_CH_DEMASK_TR_I_MSK 0x00000000
+#define SBUS_DMAC_CH_DEMASK_TR_SFT 0
+#define SBUS_DMAC_CH_DEMASK_TR_HI 31
+#define SBUS_DMAC_CH_DEMASK_TR_SZ 32
+#define SBUS_DMAC_CH_DEMASK_ERR_MSK 0xffffffff
+#define SBUS_DMAC_CH_DEMASK_ERR_I_MSK 0x00000000
+#define SBUS_DMAC_CH_DEMASK_ERR_SFT 0
+#define SBUS_DMAC_CH_DEMASK_ERR_HI 31
+#define SBUS_DMAC_CH_DEMASK_ERR_SZ 32
+#define SBUS_DMAC_CH0_CLR_TR_MSK 0x00000001
+#define SBUS_DMAC_CH0_CLR_TR_I_MSK 0xfffffffe
+#define SBUS_DMAC_CH0_CLR_TR_SFT 0
+#define SBUS_DMAC_CH0_CLR_TR_HI 0
+#define SBUS_DMAC_CH0_CLR_TR_SZ 1
+#define SBUS_DMAC_CH1_CLR_TR_MSK 0x00000002
+#define SBUS_DMAC_CH1_CLR_TR_I_MSK 0xfffffffd
+#define SBUS_DMAC_CH1_CLR_TR_SFT 1
+#define SBUS_DMAC_CH1_CLR_TR_HI 1
+#define SBUS_DMAC_CH1_CLR_TR_SZ 1
+#define SBUS_DMAC_CH0_CLR_ERR_MSK 0x00000001
+#define SBUS_DMAC_CH0_CLR_ERR_I_MSK 0xfffffffe
+#define SBUS_DMAC_CH0_CLR_ERR_SFT 0
+#define SBUS_DMAC_CH0_CLR_ERR_HI 0
+#define SBUS_DMAC_CH0_CLR_ERR_SZ 1
+#define SBUS_DMAC_CH1_CLR_ERR_MSK 0x00000002
+#define SBUS_DMAC_CH1_CLR_ERR_I_MSK 0xfffffffd
+#define SBUS_DMAC_CH1_CLR_ERR_SFT 1
+#define SBUS_DMAC_CH1_CLR_ERR_HI 1
+#define SBUS_DMAC_CH1_CLR_ERR_SZ 1
+#define SBUS_DMAC_DISEN_SHS_SRC_REQ_MSK 0x0000ffff
+#define SBUS_DMAC_DISEN_SHS_SRC_REQ_I_MSK 0xffff0000
+#define SBUS_DMAC_DISEN_SHS_SRC_REQ_SFT 0
+#define SBUS_DMAC_DISEN_SHS_SRC_REQ_HI 15
+#define SBUS_DMAC_DISEN_SHS_SRC_REQ_SZ 16
+#define SBUS_DMAC_DISEN_SHS_DST_REQ_MSK 0x0000ffff
+#define SBUS_DMAC_DISEN_SHS_DST_REQ_I_MSK 0xffff0000
+#define SBUS_DMAC_DISEN_SHS_DST_REQ_SFT 0
+#define SBUS_DMAC_DISEN_SHS_DST_REQ_HI 15
+#define SBUS_DMAC_DISEN_SHS_DST_REQ_SZ 16
+#define SBUS_DMAC_DISEN_SHS_SRC_SREQ_MSK 0x0000ffff
+#define SBUS_DMAC_DISEN_SHS_SRC_SREQ_I_MSK 0xffff0000
+#define SBUS_DMAC_DISEN_SHS_SRC_SREQ_SFT 0
+#define SBUS_DMAC_DISEN_SHS_SRC_SREQ_HI 15
+#define SBUS_DMAC_DISEN_SHS_SRC_SREQ_SZ 16
+#define SBUS_DMAC_DISEN_SHS_DST_SREQ_MSK 0x0000ffff
+#define SBUS_DMAC_DISEN_SHS_DST_SREQ_I_MSK 0xffff0000
+#define SBUS_DMAC_DISEN_SHS_DST_SREQ_SFT 0
+#define SBUS_DMAC_DISEN_SHS_DST_SREQ_HI 15
+#define SBUS_DMAC_DISEN_SHS_DST_SREQ_SZ 16
+#define SBUS_DMAC_EN_MSK 0x00000001
+#define SBUS_DMAC_EN_I_MSK 0xfffffffe
+#define SBUS_DMAC_EN_SFT 0
+#define SBUS_DMAC_EN_HI 0
+#define SBUS_DMAC_EN_SZ 1
+#define SBUS_DMAC_CH_EN_MSK 0x0000ffff
+#define SBUS_DMAC_CH_EN_I_MSK 0xffff0000
+#define SBUS_DMAC_CH_EN_SFT 0
+#define SBUS_DMAC_CH_EN_HI 15
+#define SBUS_DMAC_CH_EN_SZ 16
+#define I2S_ENABLE_MSK 0x00000001
+#define I2S_ENABLE_I_MSK 0xfffffffe
+#define I2S_ENABLE_SFT 0
+#define I2S_ENABLE_HI 0
+#define I2S_ENABLE_SZ 1
+#define I2S_RX_ENABLE_MSK 0x00000001
+#define I2S_RX_ENABLE_I_MSK 0xfffffffe
+#define I2S_RX_ENABLE_SFT 0
+#define I2S_RX_ENABLE_HI 0
+#define I2S_RX_ENABLE_SZ 1
+#define I2S_TX_ENABLE_MSK 0x00000001
+#define I2S_TX_ENABLE_I_MSK 0xfffffffe
+#define I2S_TX_ENABLE_SFT 0
+#define I2S_TX_ENABLE_HI 0
+#define I2S_TX_ENABLE_SZ 1
+#define I2S_SCLK_SOURCE_ENABLE_MSK 0x00000001
+#define I2S_SCLK_SOURCE_ENABLE_I_MSK 0xfffffffe
+#define I2S_SCLK_SOURCE_ENABLE_SFT 0
+#define I2S_SCLK_SOURCE_ENABLE_HI 0
+#define I2S_SCLK_SOURCE_ENABLE_SZ 1
+#define I2S_SCLK_GATE_MSK 0x00000007
+#define I2S_SCLK_GATE_I_MSK 0xfffffff8
+#define I2S_SCLK_GATE_SFT 0
+#define I2S_SCLK_GATE_HI 2
+#define I2S_SCLK_GATE_SZ 3
+#define I2S_WS_LENGTH_MSK 0x00000018
+#define I2S_WS_LENGTH_I_MSK 0xffffffe7
+#define I2S_WS_LENGTH_SFT 3
+#define I2S_WS_LENGTH_HI 4
+#define I2S_WS_LENGTH_SZ 2
+#define I2S_RST_RXFIFO_MSK 0x00000001
+#define I2S_RST_RXFIFO_I_MSK 0xfffffffe
+#define I2S_RST_RXFIFO_SFT 0
+#define I2S_RST_RXFIFO_HI 0
+#define I2S_RST_RXFIFO_SZ 1
+#define I2S_RST_TXFIFO_MSK 0x00000001
+#define I2S_RST_TXFIFO_I_MSK 0xfffffffe
+#define I2S_RST_TXFIFO_SFT 0
+#define I2S_RST_TXFIFO_HI 0
+#define I2S_RST_TXFIFO_SZ 1
+#define I2S_L_TRX_DATA_MSK 0xffffffff
+#define I2S_L_TRX_DATA_I_MSK 0x00000000
+#define I2S_L_TRX_DATA_SFT 0
+#define I2S_L_TRX_DATA_HI 31
+#define I2S_L_TRX_DATA_SZ 32
+#define I2S_R_TRX_DATA_MSK 0xffffffff
+#define I2S_R_TRX_DATA_I_MSK 0x00000000
+#define I2S_R_TRX_DATA_SFT 0
+#define I2S_R_TRX_DATA_HI 31
+#define I2S_R_TRX_DATA_SZ 32
+#define I2S_RX_CH_ENABLE_MSK 0x00000001
+#define I2S_RX_CH_ENABLE_I_MSK 0xfffffffe
+#define I2S_RX_CH_ENABLE_SFT 0
+#define I2S_RX_CH_ENABLE_HI 0
+#define I2S_RX_CH_ENABLE_SZ 1
+#define I2S_TX_CH_ENABLE_MSK 0x00000001
+#define I2S_TX_CH_ENABLE_I_MSK 0xfffffffe
+#define I2S_TX_CH_ENABLE_SFT 0
+#define I2S_TX_CH_ENABLE_HI 0
+#define I2S_TX_CH_ENABLE_SZ 1
+#define I2S_RX_WD_RES_MSK 0x00000007
+#define I2S_RX_WD_RES_I_MSK 0xfffffff8
+#define I2S_RX_WD_RES_SFT 0
+#define I2S_RX_WD_RES_HI 2
+#define I2S_RX_WD_RES_SZ 3
+#define I2S_TX_WD_RES_MSK 0x00000007
+#define I2S_TX_WD_RES_I_MSK 0xfffffff8
+#define I2S_TX_WD_RES_SFT 0
+#define I2S_TX_WD_RES_HI 2
+#define I2S_TX_WD_RES_SZ 3
+#define I2S_INTR_RXDA_MSK 0x00000001
+#define I2S_INTR_RXDA_I_MSK 0xfffffffe
+#define I2S_INTR_RXDA_SFT 0
+#define I2S_INTR_RXDA_HI 0
+#define I2S_INTR_RXDA_SZ 1
+#define I2S_INTR_RXFO_MSK 0x00000002
+#define I2S_INTR_RXFO_I_MSK 0xfffffffd
+#define I2S_INTR_RXFO_SFT 1
+#define I2S_INTR_RXFO_HI 1
+#define I2S_INTR_RXFO_SZ 1
+#define I2S_INTR_RXFE_MSK 0x00000010
+#define I2S_INTR_RXFE_I_MSK 0xffffffef
+#define I2S_INTR_RXFE_SFT 4
+#define I2S_INTR_RXFE_HI 4
+#define I2S_INTR_RXFE_SZ 1
+#define I2S_INTR_TXFO_MSK 0x00000020
+#define I2S_INTR_TXFO_I_MSK 0xffffffdf
+#define I2S_INTR_TXFO_SFT 5
+#define I2S_INTR_TXFO_HI 5
+#define I2S_INTR_TXFO_SZ 1
+#define I2S_INTR_RXFA_MASK_MSK 0x00000001
+#define I2S_INTR_RXFA_MASK_I_MSK 0xfffffffe
+#define I2S_INTR_RXFA_MASK_SFT 0
+#define I2S_INTR_RXFA_MASK_HI 0
+#define I2S_INTR_RXFA_MASK_SZ 1
+#define I2S_INTR_RXFO_MASK_MSK 0x00000002
+#define I2S_INTR_RXFO_MASK_I_MSK 0xfffffffd
+#define I2S_INTR_RXFO_MASK_SFT 1
+#define I2S_INTR_RXFO_MASK_HI 1
+#define I2S_INTR_RXFO_MASK_SZ 1
+#define I2S_INTR_TXFE_MASK_MSK 0x00000010
+#define I2S_INTR_TXFE_MASK_I_MSK 0xffffffef
+#define I2S_INTR_TXFE_MASK_SFT 4
+#define I2S_INTR_TXFE_MASK_HI 4
+#define I2S_INTR_TXFE_MASK_SZ 1
+#define I2S_INTR_TXFO_MASK_MSK 0x00000020
+#define I2S_INTR_TXFO_MASK_I_MSK 0xffffffdf
+#define I2S_INTR_TXFO_MASK_SFT 5
+#define I2S_INTR_TXFO_MASK_HI 5
+#define I2S_INTR_TXFO_MASK_SZ 1
+#define I2S_RXFO_MSK 0x00000001
+#define I2S_RXFO_I_MSK 0xfffffffe
+#define I2S_RXFO_SFT 0
+#define I2S_RXFO_HI 0
+#define I2S_RXFO_SZ 1
+#define I2S_TXFO_MSK 0x00000001
+#define I2S_TXFO_I_MSK 0xfffffffe
+#define I2S_TXFO_SFT 0
+#define I2S_TXFO_HI 0
+#define I2S_TXFO_SZ 1
+#define I2S_RX_FIFO_TH_MSK 0x00000007
+#define I2S_RX_FIFO_TH_I_MSK 0xfffffff8
+#define I2S_RX_FIFO_TH_SFT 0
+#define I2S_RX_FIFO_TH_HI 2
+#define I2S_RX_FIFO_TH_SZ 3
+#define I2S_TX_FIFO_TH_MSK 0x00000007
+#define I2S_TX_FIFO_TH_I_MSK 0xfffffff8
+#define I2S_TX_FIFO_TH_SFT 0
+#define I2S_TX_FIFO_TH_HI 2
+#define I2S_TX_FIFO_TH_SZ 3
+#define I2S_RX_FIFO_FLUSH_MSK 0x00000001
+#define I2S_RX_FIFO_FLUSH_I_MSK 0xfffffffe
+#define I2S_RX_FIFO_FLUSH_SFT 0
+#define I2S_RX_FIFO_FLUSH_HI 0
+#define I2S_RX_FIFO_FLUSH_SZ 1
+#define I2S_TX_FIFO_FLUSH_MSK 0x00000001
+#define I2S_TX_FIFO_FLUSH_I_MSK 0xfffffffe
+#define I2S_TX_FIFO_FLUSH_SFT 0
+#define I2S_TX_FIFO_FLUSH_HI 0
+#define I2S_TX_FIFO_FLUSH_SZ 1
+#define I2S_RX_DMA_MSK 0xffffffff
+#define I2S_RX_DMA_I_MSK 0x00000000
+#define I2S_RX_DMA_SFT 0
+#define I2S_RX_DMA_HI 31
+#define I2S_RX_DMA_SZ 32
+#define I2S_TX_DMA_MSK 0xffffffff
+#define I2S_TX_DMA_I_MSK 0x00000000
+#define I2S_TX_DMA_SFT 0
+#define I2S_TX_DMA_HI 31
+#define I2S_TX_DMA_SZ 32
+#define I2CMST_ENABLE_MASTER_MSK 0x00000001
+#define I2CMST_ENABLE_MASTER_I_MSK 0xfffffffe
+#define I2CMST_ENABLE_MASTER_SFT 0
+#define I2CMST_ENABLE_MASTER_HI 0
+#define I2CMST_ENABLE_MASTER_SZ 1
+#define I2CMST_SPEED_MSK 0x00000006
+#define I2CMST_SPEED_I_MSK 0xfffffff9
+#define I2CMST_SPEED_SFT 1
+#define I2CMST_SPEED_HI 2
+#define I2CMST_SPEED_SZ 2
+#define I2CMST_RESTART_EN_MSK 0x00000020
+#define I2CMST_RESTART_EN_I_MSK 0xffffffdf
+#define I2CMST_RESTART_EN_SFT 5
+#define I2CMST_RESTART_EN_HI 5
+#define I2CMST_RESTART_EN_SZ 1
+#define I2CMST_DISABLE_SLAVE_MSK 0x00000040
+#define I2CMST_DISABLE_SLAVE_I_MSK 0xffffffbf
+#define I2CMST_DISABLE_SLAVE_SFT 6
+#define I2CMST_DISABLE_SLAVE_HI 6
+#define I2CMST_DISABLE_SLAVE_SZ 1
+#define I2CMST_TAR_MSK 0x000003ff
+#define I2CMST_TAR_I_MSK 0xfffffc00
+#define I2CMST_TAR_SFT 0
+#define I2CMST_TAR_HI 9
+#define I2CMST_TAR_SZ 10
+#define I2CMST_TRX_DATA_MSK 0x000000ff
+#define I2CMST_TRX_DATA_I_MSK 0xffffff00
+#define I2CMST_TRX_DATA_SFT 0
+#define I2CMST_TRX_DATA_HI 7
+#define I2CMST_TRX_DATA_SZ 8
+#define I2CMST_TRX_CMDW_MSK 0x00000100
+#define I2CMST_TRX_CMDW_I_MSK 0xfffffeff
+#define I2CMST_TRX_CMDW_SFT 8
+#define I2CMST_TRX_CMDW_HI 8
+#define I2CMST_TRX_CMDW_SZ 1
+#define I2CMST_TRX_STOPW_MSK 0x00000200
+#define I2CMST_TRX_STOPW_I_MSK 0xfffffdff
+#define I2CMST_TRX_STOPW_SFT 9
+#define I2CMST_TRX_STOPW_HI 9
+#define I2CMST_TRX_STOPW_SZ 1
+#define I2CMST_TRX_RESTARTW_MSK 0x00000400
+#define I2CMST_TRX_RESTARTW_I_MSK 0xfffffbff
+#define I2CMST_TRX_RESTARTW_SFT 10
+#define I2CMST_TRX_RESTARTW_HI 10
+#define I2CMST_TRX_RESTARTW_SZ 1
+#define I2CMST_RX_1STBRDYR_MSK 0x00000800
+#define I2CMST_RX_1STBRDYR_I_MSK 0xfffff7ff
+#define I2CMST_RX_1STBRDYR_SFT 11
+#define I2CMST_RX_1STBRDYR_HI 11
+#define I2CMST_RX_1STBRDYR_SZ 1
+#define I2CMST_SCLK_H_WIDTH_MSK 0x0000ffff
+#define I2CMST_SCLK_H_WIDTH_I_MSK 0xffff0000
+#define I2CMST_SCLK_H_WIDTH_SFT 0
+#define I2CMST_SCLK_H_WIDTH_HI 15
+#define I2CMST_SCLK_H_WIDTH_SZ 16
+#define I2CMST_SCLK_L_WIDTH_MSK 0x0000ffff
+#define I2CMST_SCLK_L_WIDTH_I_MSK 0xffff0000
+#define I2CMST_SCLK_L_WIDTH_SFT 0
+#define I2CMST_SCLK_L_WIDTH_HI 15
+#define I2CMST_SCLK_L_WIDTH_SZ 16
+#define I2CMST_RXU_INT_MSK 0x00000001
+#define I2CMST_RXU_INT_I_MSK 0xfffffffe
+#define I2CMST_RXU_INT_SFT 0
+#define I2CMST_RXU_INT_HI 0
+#define I2CMST_RXU_INT_SZ 1
+#define I2CMST_RXO_INT_MSK 0x00000002
+#define I2CMST_RXO_INT_I_MSK 0xfffffffd
+#define I2CMST_RXO_INT_SFT 1
+#define I2CMST_RXO_INT_HI 1
+#define I2CMST_RXO_INT_SZ 1
+#define I2CMST_RXF_INT_MSK 0x00000004
+#define I2CMST_RXF_INT_I_MSK 0xfffffffb
+#define I2CMST_RXF_INT_SFT 2
+#define I2CMST_RXF_INT_HI 2
+#define I2CMST_RXF_INT_SZ 1
+#define I2CMST_TXO_INT_MSK 0x00000008
+#define I2CMST_TXO_INT_I_MSK 0xfffffff7
+#define I2CMST_TXO_INT_SFT 3
+#define I2CMST_TXO_INT_HI 3
+#define I2CMST_TXO_INT_SZ 1
+#define I2CMST_TXE_INT_MSK 0x00000010
+#define I2CMST_TXE_INT_I_MSK 0xffffffef
+#define I2CMST_TXE_INT_SFT 4
+#define I2CMST_TXE_INT_HI 4
+#define I2CMST_TXE_INT_SZ 1
+#define I2CMST_RXDONE_INT_MSK 0x00000080
+#define I2CMST_RXDONE_INT_I_MSK 0xffffff7f
+#define I2CMST_RXDONE_INT_SFT 7
+#define I2CMST_RXDONE_INT_HI 7
+#define I2CMST_RXDONE_INT_SZ 1
+#define I2CMST_RXU_INT_MASK_MSK 0x00000001
+#define I2CMST_RXU_INT_MASK_I_MSK 0xfffffffe
+#define I2CMST_RXU_INT_MASK_SFT 0
+#define I2CMST_RXU_INT_MASK_HI 0
+#define I2CMST_RXU_INT_MASK_SZ 1
+#define I2CMST_RXO_INT_MASK_MSK 0x00000002
+#define I2CMST_RXO_INT_MASK_I_MSK 0xfffffffd
+#define I2CMST_RXO_INT_MASK_SFT 1
+#define I2CMST_RXO_INT_MASK_HI 1
+#define I2CMST_RXO_INT_MASK_SZ 1
+#define I2CMST_RXF_INT_MASK_MSK 0x00000004
+#define I2CMST_RXF_INT_MASK_I_MSK 0xfffffffb
+#define I2CMST_RXF_INT_MASK_SFT 2
+#define I2CMST_RXF_INT_MASK_HI 2
+#define I2CMST_RXF_INT_MASK_SZ 1
+#define I2CMST_TXO_INT_MASK_MSK 0x00000008
+#define I2CMST_TXO_INT_MASK_I_MSK 0xfffffff7
+#define I2CMST_TXO_INT_MASK_SFT 3
+#define I2CMST_TXO_INT_MASK_HI 3
+#define I2CMST_TXO_INT_MASK_SZ 1
+#define I2CMST_TXE_INT_MASK_MSK 0x00000010
+#define I2CMST_TXE_INT_MASK_I_MSK 0xffffffef
+#define I2CMST_TXE_INT_MASK_SFT 4
+#define I2CMST_TXE_INT_MASK_HI 4
+#define I2CMST_TXE_INT_MASK_SZ 1
+#define I2CMST_RXDONE_INT_MASK_MSK 0x00000080
+#define I2CMST_RXDONE_INT_MASK_I_MSK 0xffffff7f
+#define I2CMST_RXDONE_INT_MASK_SFT 7
+#define I2CMST_RXDONE_INT_MASK_HI 7
+#define I2CMST_RXDONE_INT_MASK_SZ 1
+#define I2CMST_RXU_INT_STAR_MSK 0x00000001
+#define I2CMST_RXU_INT_STAR_I_MSK 0xfffffffe
+#define I2CMST_RXU_INT_STAR_SFT 0
+#define I2CMST_RXU_INT_STAR_HI 0
+#define I2CMST_RXU_INT_STAR_SZ 1
+#define I2CMST_RXO_INT_STAR_MSK 0x00000002
+#define I2CMST_RXO_INT_STAR_I_MSK 0xfffffffd
+#define I2CMST_RXO_INT_STAR_SFT 1
+#define I2CMST_RXO_INT_STAR_HI 1
+#define I2CMST_RXO_INT_STAR_SZ 1
+#define I2CMST_RXF_INT_STAR_MSK 0x00000004
+#define I2CMST_RXF_INT_STAR_I_MSK 0xfffffffb
+#define I2CMST_RXF_INT_STAR_SFT 2
+#define I2CMST_RXF_INT_STAR_HI 2
+#define I2CMST_RXF_INT_STAR_SZ 1
+#define I2CMST_TXO_INT_STAR_MSK 0x00000008
+#define I2CMST_TXO_INT_STAR_I_MSK 0xfffffff7
+#define I2CMST_TXO_INT_STAR_SFT 3
+#define I2CMST_TXO_INT_STAR_HI 3
+#define I2CMST_TXO_INT_STAR_SZ 1
+#define I2CMST_TXE_INT_STAR_MSK 0x00000010
+#define I2CMST_TXE_INT_STAR_I_MSK 0xffffffef
+#define I2CMST_TXE_INT_STAR_SFT 4
+#define I2CMST_TXE_INT_STAR_HI 4
+#define I2CMST_TXE_INT_STAR_SZ 1
+#define I2CMST_RXDONE_INT_STAR_MSK 0x00000080
+#define I2CMST_RXDONE_INT_STAR_I_MSK 0xffffff7f
+#define I2CMST_RXDONE_INT_STAR_SFT 7
+#define I2CMST_RXDONE_INT_STAR_HI 7
+#define I2CMST_RXDONE_INT_STAR_SZ 1
+#define I2CMST_RX_FIFO_TH_MSK 0x0000ffff
+#define I2CMST_RX_FIFO_TH_I_MSK 0xffff0000
+#define I2CMST_RX_FIFO_TH_SFT 0
+#define I2CMST_RX_FIFO_TH_HI 15
+#define I2CMST_RX_FIFO_TH_SZ 16
+#define I2CMST_TX_FIFO_TH_MSK 0x0000ffff
+#define I2CMST_TX_FIFO_TH_I_MSK 0xffff0000
+#define I2CMST_TX_FIFO_TH_SFT 0
+#define I2CMST_TX_FIFO_TH_HI 15
+#define I2CMST_TX_FIFO_TH_SZ 16
+#define I2CMST_EN_MSK 0x00000001
+#define I2CMST_EN_I_MSK 0xfffffffe
+#define I2CMST_EN_SFT 0
+#define I2CMST_EN_HI 0
+#define I2CMST_EN_SZ 1
+#define SPIMST_DATA_LEN_MSK 0x0000000f
+#define SPIMST_DATA_LEN_I_MSK 0xfffffff0
+#define SPIMST_DATA_LEN_SFT 0
+#define SPIMST_DATA_LEN_HI 3
+#define SPIMST_DATA_LEN_SZ 4
+#define SPIMST_CPHA_MSK 0x00000040
+#define SPIMST_CPHA_I_MSK 0xffffffbf
+#define SPIMST_CPHA_SFT 6
+#define SPIMST_CPHA_HI 6
+#define SPIMST_CPHA_SZ 1
+#define SPIMST_CPOL_MSK 0x00000080
+#define SPIMST_CPOL_I_MSK 0xffffff7f
+#define SPIMST_CPOL_SFT 7
+#define SPIMST_CPOL_HI 7
+#define SPIMST_CPOL_SZ 1
+#define TRX_MODE_MSK 0x00000300
+#define TRX_MODE_I_MSK 0xfffffcff
+#define TRX_MODE_SFT 8
+#define TRX_MODE_HI 9
+#define TRX_MODE_SZ 2
+#define DATA_FRAMES_MSK 0x0000ffff
+#define DATA_FRAMES_I_MSK 0xffff0000
+#define DATA_FRAMES_SFT 0
+#define DATA_FRAMES_HI 15
+#define DATA_FRAMES_SZ 16
+#define SPIMST_ENABLE_MSK 0x00000001
+#define SPIMST_ENABLE_I_MSK 0xfffffffe
+#define SPIMST_ENABLE_SFT 0
+#define SPIMST_ENABLE_HI 0
+#define SPIMST_ENABLE_SZ 1
+#define SPIMST_CEN_ENABLE_MSK 0x00000001
+#define SPIMST_CEN_ENABLE_I_MSK 0xfffffffe
+#define SPIMST_CEN_ENABLE_SFT 0
+#define SPIMST_CEN_ENABLE_HI 0
+#define SPIMST_CEN_ENABLE_SZ 1
+#define SPIMST_SCLK_RATE_MSK 0x0000ffff
+#define SPIMST_SCLK_RATE_I_MSK 0xffff0000
+#define SPIMST_SCLK_RATE_SFT 0
+#define SPIMST_SCLK_RATE_HI 15
+#define SPIMST_SCLK_RATE_SZ 16
+#define SPIMST_TXFIFO_TH_MSK 0x0000000f
+#define SPIMST_TXFIFO_TH_I_MSK 0xfffffff0
+#define SPIMST_TXFIFO_TH_SFT 0
+#define SPIMST_TXFIFO_TH_HI 3
+#define SPIMST_TXFIFO_TH_SZ 4
+#define SPIMST_RXFIFO_TH_MSK 0x0000000f
+#define SPIMST_RXFIFO_TH_I_MSK 0xfffffff0
+#define SPIMST_RXFIFO_TH_SFT 0
+#define SPIMST_RXFIFO_TH_HI 3
+#define SPIMST_RXFIFO_TH_SZ 4
+#define TRXBUSYFLAG_MSK 0x00000001
+#define TRXBUSYFLAG_I_MSK 0xfffffffe
+#define TRXBUSYFLAG_SFT 0
+#define TRXBUSYFLAG_HI 0
+#define TRXBUSYFLAG_SZ 1
+#define TXNOTFULLFLAG_MSK 0x00000002
+#define TXNOTFULLFLAG_I_MSK 0xfffffffd
+#define TXNOTFULLFLAG_SFT 1
+#define TXNOTFULLFLAG_HI 1
+#define TXNOTFULLFLAG_SZ 1
+#define TXEMPTYFLAG_MSK 0x00000004
+#define TXEMPTYFLAG_I_MSK 0xfffffffb
+#define TXEMPTYFLAG_SFT 2
+#define TXEMPTYFLAG_HI 2
+#define TXEMPTYFLAG_SZ 1
+#define RXNOTEMPTYFLAG_MSK 0x00000008
+#define RXNOTEMPTYFLAG_I_MSK 0xfffffff7
+#define RXNOTEMPTYFLAG_SFT 3
+#define RXNOTEMPTYFLAG_HI 3
+#define RXNOTEMPTYFLAG_SZ 1
+#define RXFULLFLAG_MSK 0x00000010
+#define RXFULLFLAG_I_MSK 0xffffffef
+#define RXFULLFLAG_SFT 4
+#define RXFULLFLAG_HI 4
+#define RXFULLFLAG_SZ 1
+#define TXERRORFLAG_MSK 0x00000020
+#define TXERRORFLAG_I_MSK 0xffffffdf
+#define TXERRORFLAG_SFT 5
+#define TXERRORFLAG_HI 5
+#define TXERRORFLAG_SZ 1
+#define SPIMST_TXE_INT_UNMASK_MSK 0x00000001
+#define SPIMST_TXE_INT_UNMASK_I_MSK 0xfffffffe
+#define SPIMST_TXE_INT_UNMASK_SFT 0
+#define SPIMST_TXE_INT_UNMASK_HI 0
+#define SPIMST_TXE_INT_UNMASK_SZ 1
+#define SPIMST_TXO_INT_UNMASK_MSK 0x00000002
+#define SPIMST_TXO_INT_UNMASK_I_MSK 0xfffffffd
+#define SPIMST_TXO_INT_UNMASK_SFT 1
+#define SPIMST_TXO_INT_UNMASK_HI 1
+#define SPIMST_TXO_INT_UNMASK_SZ 1
+#define SPIMST_RXU_INT_UNMASK_MSK 0x00000004
+#define SPIMST_RXU_INT_UNMASK_I_MSK 0xfffffffb
+#define SPIMST_RXU_INT_UNMASK_SFT 2
+#define SPIMST_RXU_INT_UNMASK_HI 2
+#define SPIMST_RXU_INT_UNMASK_SZ 1
+#define SPIMST_RXO_INT_UNMASK_MSK 0x00000008
+#define SPIMST_RXO_INT_UNMASK_I_MSK 0xfffffff7
+#define SPIMST_RXO_INT_UNMASK_SFT 3
+#define SPIMST_RXO_INT_UNMASK_HI 3
+#define SPIMST_RXO_INT_UNMASK_SZ 1
+#define SPIMST_RXF_INT_UNMASK_MSK 0x00000010
+#define SPIMST_RXF_INT_UNMASK_I_MSK 0xffffffef
+#define SPIMST_RXF_INT_UNMASK_SFT 4
+#define SPIMST_RXF_INT_UNMASK_HI 4
+#define SPIMST_RXF_INT_UNMASK_SZ 1
+#define SPIMST_TXE_INT_MSK 0x00000001
+#define SPIMST_TXE_INT_I_MSK 0xfffffffe
+#define SPIMST_TXE_INT_SFT 0
+#define SPIMST_TXE_INT_HI 0
+#define SPIMST_TXE_INT_SZ 1
+#define SPIMST_TXO_INT_MSK 0x00000002
+#define SPIMST_TXO_INT_I_MSK 0xfffffffd
+#define SPIMST_TXO_INT_SFT 1
+#define SPIMST_TXO_INT_HI 1
+#define SPIMST_TXO_INT_SZ 1
+#define SPIMST_RXU_INT_MSK 0x00000004
+#define SPIMST_RXU_INT_I_MSK 0xfffffffb
+#define SPIMST_RXU_INT_SFT 2
+#define SPIMST_RXU_INT_HI 2
+#define SPIMST_RXU_INT_SZ 1
+#define SPIMST_RXO_INT_MSK 0x00000008
+#define SPIMST_RXO_INT_I_MSK 0xfffffff7
+#define SPIMST_RXO_INT_SFT 3
+#define SPIMST_RXO_INT_HI 3
+#define SPIMST_RXO_INT_SZ 1
+#define SPIMST_RXF_INT_MSK 0x00000010
+#define SPIMST_RXF_INT_I_MSK 0xffffffef
+#define SPIMST_RXF_INT_SFT 4
+#define SPIMST_RXF_INT_HI 4
+#define SPIMST_RXF_INT_SZ 1
+#define SPIMST_TRX_DATA_MSK 0xffffffff
+#define SPIMST_TRX_DATA_I_MSK 0x00000000
+#define SPIMST_TRX_DATA_SFT 0
+#define SPIMST_TRX_DATA_HI 31
+#define SPIMST_TRX_DATA_SZ 32
+#define SPIMST_RX_SAMPLE_DLY_MSK 0x000000ff
+#define SPIMST_RX_SAMPLE_DLY_I_MSK 0xffffff00
+#define SPIMST_RX_SAMPLE_DLY_SFT 0
+#define SPIMST_RX_SAMPLE_DLY_HI 7
+#define SPIMST_RX_SAMPLE_DLY_SZ 8
+#define MCU_ENABLE_MSK 0x00000001
+#define MCU_ENABLE_I_MSK 0xfffffffe
+#define MCU_ENABLE_SFT 0
+#define MCU_ENABLE_HI 0
+#define MCU_ENABLE_SZ 1
+#define MAC_SW_RST_MSK 0x00000002
+#define MAC_SW_RST_I_MSK 0xfffffffd
+#define MAC_SW_RST_SFT 1
+#define MAC_SW_RST_HI 1
+#define MAC_SW_RST_SZ 1
+#define USB_SW_RST_MSK 0x00000004
+#define USB_SW_RST_I_MSK 0xfffffffb
+#define USB_SW_RST_SFT 2
+#define USB_SW_RST_HI 2
+#define USB_SW_RST_SZ 1
+#define SDIO_SW_RST_MSK 0x00000008
+#define SDIO_SW_RST_I_MSK 0xfffffff7
+#define SDIO_SW_RST_SFT 3
+#define SDIO_SW_RST_HI 3
+#define SDIO_SW_RST_SZ 1
+#define SPI_SLV_SW_RST_MSK 0x00000010
+#define SPI_SLV_SW_RST_I_MSK 0xffffffef
+#define SPI_SLV_SW_RST_SFT 4
+#define SPI_SLV_SW_RST_HI 4
+#define SPI_SLV_SW_RST_SZ 1
+#define UART_SW_RST_MSK 0x00000020
+#define UART_SW_RST_I_MSK 0xffffffdf
+#define UART_SW_RST_SFT 5
+#define UART_SW_RST_HI 5
+#define UART_SW_RST_SZ 1
+#define DMA_SW_RST_MSK 0x00000040
+#define DMA_SW_RST_I_MSK 0xffffffbf
+#define DMA_SW_RST_SFT 6
+#define DMA_SW_RST_HI 6
+#define DMA_SW_RST_SZ 1
+#define WDT_SW_RST_MSK 0x00000080
+#define WDT_SW_RST_I_MSK 0xffffff7f
+#define WDT_SW_RST_SFT 7
+#define WDT_SW_RST_HI 7
+#define WDT_SW_RST_SZ 1
+#define I2C_SLV_SW_RST_MSK 0x00000100
+#define I2C_SLV_SW_RST_I_MSK 0xfffffeff
+#define I2C_SLV_SW_RST_SFT 8
+#define I2C_SLV_SW_RST_HI 8
+#define I2C_SLV_SW_RST_SZ 1
+#define INT_CTL_SW_RST_MSK 0x00000200
+#define INT_CTL_SW_RST_I_MSK 0xfffffdff
+#define INT_CTL_SW_RST_SFT 9
+#define INT_CTL_SW_RST_HI 9
+#define INT_CTL_SW_RST_SZ 1
+#define BTCX_SW_RST_MSK 0x00000400
+#define BTCX_SW_RST_I_MSK 0xfffffbff
+#define BTCX_SW_RST_SFT 10
+#define BTCX_SW_RST_HI 10
+#define BTCX_SW_RST_SZ 1
+#define US0TMR_SW_RST_MSK 0x00001000
+#define US0TMR_SW_RST_I_MSK 0xffffefff
+#define US0TMR_SW_RST_SFT 12
+#define US0TMR_SW_RST_HI 12
+#define US0TMR_SW_RST_SZ 1
+#define US1TMR_SW_RST_MSK 0x00002000
+#define US1TMR_SW_RST_I_MSK 0xffffdfff
+#define US1TMR_SW_RST_SFT 13
+#define US1TMR_SW_RST_HI 13
+#define US1TMR_SW_RST_SZ 1
+#define US2TMR_SW_RST_MSK 0x00004000
+#define US2TMR_SW_RST_I_MSK 0xffffbfff
+#define US2TMR_SW_RST_SFT 14
+#define US2TMR_SW_RST_HI 14
+#define US2TMR_SW_RST_SZ 1
+#define US3TMR_SW_RST_MSK 0x00008000
+#define US3TMR_SW_RST_I_MSK 0xffff7fff
+#define US3TMR_SW_RST_SFT 15
+#define US3TMR_SW_RST_HI 15
+#define US3TMR_SW_RST_SZ 1
+#define MS0TMR_SW_RST_MSK 0x00010000
+#define MS0TMR_SW_RST_I_MSK 0xfffeffff
+#define MS0TMR_SW_RST_SFT 16
+#define MS0TMR_SW_RST_HI 16
+#define MS0TMR_SW_RST_SZ 1
+#define MS1TMR_SW_RST_MSK 0x00020000
+#define MS1TMR_SW_RST_I_MSK 0xfffdffff
+#define MS1TMR_SW_RST_SFT 17
+#define MS1TMR_SW_RST_HI 17
+#define MS1TMR_SW_RST_SZ 1
+#define MS2TMR_SW_RST_MSK 0x00040000
+#define MS2TMR_SW_RST_I_MSK 0xfffbffff
+#define MS2TMR_SW_RST_SFT 18
+#define MS2TMR_SW_RST_HI 18
+#define MS2TMR_SW_RST_SZ 1
+#define MS3TMR_SW_RST_MSK 0x00080000
+#define MS3TMR_SW_RST_I_MSK 0xfff7ffff
+#define MS3TMR_SW_RST_SFT 19
+#define MS3TMR_SW_RST_HI 19
+#define MS3TMR_SW_RST_SZ 1
+#define PLF_SW_RST_MSK 0x00100000
+#define PLF_SW_RST_I_MSK 0xffefffff
+#define PLF_SW_RST_SFT 20
+#define PLF_SW_RST_HI 20
+#define PLF_SW_RST_SZ 1
+#define ALL_SW_RST_MSK 0x00200000
+#define ALL_SW_RST_I_MSK 0xffdfffff
+#define ALL_SW_RST_SFT 21
+#define ALL_SW_RST_HI 21
+#define ALL_SW_RST_SZ 1
+#define DAT_UART_SW_RST_MSK 0x00400000
+#define DAT_UART_SW_RST_I_MSK 0xffbfffff
+#define DAT_UART_SW_RST_SFT 22
+#define DAT_UART_SW_RST_HI 22
+#define DAT_UART_SW_RST_SZ 1
+#define I2C_MST_SW_RST_MSK 0x00800000
+#define I2C_MST_SW_RST_I_MSK 0xff7fffff
+#define I2C_MST_SW_RST_SFT 23
+#define I2C_MST_SW_RST_HI 23
+#define I2C_MST_SW_RST_SZ 1
+#define RG_REBOOT_MSK 0x00000001
+#define RG_REBOOT_I_MSK 0xfffffffe
+#define RG_REBOOT_SFT 0
+#define RG_REBOOT_HI 0
+#define RG_REBOOT_SZ 1
+#define TRAP_IMG_FLS_MSK 0x00010000
+#define TRAP_IMG_FLS_I_MSK 0xfffeffff
+#define TRAP_IMG_FLS_SFT 16
+#define TRAP_IMG_FLS_HI 16
+#define TRAP_IMG_FLS_SZ 1
+#define TRAP_REBOOT_MSK 0x00020000
+#define TRAP_REBOOT_I_MSK 0xfffdffff
+#define TRAP_REBOOT_SFT 17
+#define TRAP_REBOOT_HI 17
+#define TRAP_REBOOT_SZ 1
+#define TRAP_BOOT_FLS_MSK 0x00040000
+#define TRAP_BOOT_FLS_I_MSK 0xfffbffff
+#define TRAP_BOOT_FLS_SFT 18
+#define TRAP_BOOT_FLS_HI 18
+#define TRAP_BOOT_FLS_SZ 1
+#define CHIP_ID_31_0_MSK 0xffffffff
+#define CHIP_ID_31_0_I_MSK 0x00000000
+#define CHIP_ID_31_0_SFT 0
+#define CHIP_ID_31_0_HI 31
+#define CHIP_ID_31_0_SZ 32
+#define CHIP_ID_63_32_MSK 0xffffffff
+#define CHIP_ID_63_32_I_MSK 0x00000000
+#define CHIP_ID_63_32_SFT 0
+#define CHIP_ID_63_32_HI 31
+#define CHIP_ID_63_32_SZ 32
+#define CHIP_ID_95_64_MSK 0xffffffff
+#define CHIP_ID_95_64_I_MSK 0x00000000
+#define CHIP_ID_95_64_SFT 0
+#define CHIP_ID_95_64_HI 31
+#define CHIP_ID_95_64_SZ 32
+#define CHIP_ID_127_96_MSK 0xffffffff
+#define CHIP_ID_127_96_I_MSK 0x00000000
+#define CHIP_ID_127_96_SFT 0
+#define CHIP_ID_127_96_HI 31
+#define CHIP_ID_127_96_SZ 32
+#define CLK_DIGI_SEL_MSK 0x0000000f
+#define CLK_DIGI_SEL_I_MSK 0xfffffff0
+#define CLK_DIGI_SEL_SFT 0
+#define CLK_DIGI_SEL_HI 3
+#define CLK_DIGI_SEL_SZ 4
+#define CLK_USB_PHY30M_SEL_MSK 0x00000010
+#define CLK_USB_PHY30M_SEL_I_MSK 0xffffffef
+#define CLK_USB_PHY30M_SEL_SFT 4
+#define CLK_USB_PHY30M_SEL_HI 4
+#define CLK_USB_PHY30M_SEL_SZ 1
+#define SYS_CLK_EN_MSK 0x00000001
+#define SYS_CLK_EN_I_MSK 0xfffffffe
+#define SYS_CLK_EN_SFT 0
+#define SYS_CLK_EN_HI 0
+#define SYS_CLK_EN_SZ 1
+#define MAC_CLK_EN_MSK 0x00000002
+#define MAC_CLK_EN_I_MSK 0xfffffffd
+#define MAC_CLK_EN_SFT 1
+#define MAC_CLK_EN_HI 1
+#define MAC_CLK_EN_SZ 1
+#define FLASH_CLK_EN_MSK 0x00000004
+#define FLASH_CLK_EN_I_MSK 0xfffffffb
+#define FLASH_CLK_EN_SFT 2
+#define FLASH_CLK_EN_HI 2
+#define FLASH_CLK_EN_SZ 1
+#define SDIO_CLK_EN_MSK 0x00000008
+#define SDIO_CLK_EN_I_MSK 0xfffffff7
+#define SDIO_CLK_EN_SFT 3
+#define SDIO_CLK_EN_HI 3
+#define SDIO_CLK_EN_SZ 1
+#define SPI_SLV_CLK_EN_MSK 0x00000010
+#define SPI_SLV_CLK_EN_I_MSK 0xffffffef
+#define SPI_SLV_CLK_EN_SFT 4
+#define SPI_SLV_CLK_EN_HI 4
+#define SPI_SLV_CLK_EN_SZ 1
+#define UART_CLK_EN_MSK 0x00000020
+#define UART_CLK_EN_I_MSK 0xffffffdf
+#define UART_CLK_EN_SFT 5
+#define UART_CLK_EN_HI 5
+#define UART_CLK_EN_SZ 1
+#define DMA_CLK_EN_MSK 0x00000040
+#define DMA_CLK_EN_I_MSK 0xffffffbf
+#define DMA_CLK_EN_SFT 6
+#define DMA_CLK_EN_HI 6
+#define DMA_CLK_EN_SZ 1
+#define WDT_CLK_EN_MSK 0x00000080
+#define WDT_CLK_EN_I_MSK 0xffffff7f
+#define WDT_CLK_EN_SFT 7
+#define WDT_CLK_EN_HI 7
+#define WDT_CLK_EN_SZ 1
+#define I2C_SLV_CLK_EN_MSK 0x00000100
+#define I2C_SLV_CLK_EN_I_MSK 0xfffffeff
+#define I2C_SLV_CLK_EN_SFT 8
+#define I2C_SLV_CLK_EN_HI 8
+#define I2C_SLV_CLK_EN_SZ 1
+#define INT_CTL_CLK_EN_MSK 0x00000200
+#define INT_CTL_CLK_EN_I_MSK 0xfffffdff
+#define INT_CTL_CLK_EN_SFT 9
+#define INT_CTL_CLK_EN_HI 9
+#define INT_CTL_CLK_EN_SZ 1
+#define BTCX_CLK_EN_MSK 0x00000400
+#define BTCX_CLK_EN_I_MSK 0xfffffbff
+#define BTCX_CLK_EN_SFT 10
+#define BTCX_CLK_EN_HI 10
+#define BTCX_CLK_EN_SZ 1
+#define EFS_CLK_EN_MSK 0x00000800
+#define EFS_CLK_EN_I_MSK 0xfffff7ff
+#define EFS_CLK_EN_SFT 11
+#define EFS_CLK_EN_HI 11
+#define EFS_CLK_EN_SZ 1
+#define US0TMR_CLK_EN_MSK 0x00001000
+#define US0TMR_CLK_EN_I_MSK 0xffffefff
+#define US0TMR_CLK_EN_SFT 12
+#define US0TMR_CLK_EN_HI 12
+#define US0TMR_CLK_EN_SZ 1
+#define US1TMR_CLK_EN_MSK 0x00002000
+#define US1TMR_CLK_EN_I_MSK 0xffffdfff
+#define US1TMR_CLK_EN_SFT 13
+#define US1TMR_CLK_EN_HI 13
+#define US1TMR_CLK_EN_SZ 1
+#define US2TMR_CLK_EN_MSK 0x00004000
+#define US2TMR_CLK_EN_I_MSK 0xffffbfff
+#define US2TMR_CLK_EN_SFT 14
+#define US2TMR_CLK_EN_HI 14
+#define US2TMR_CLK_EN_SZ 1
+#define US3TMR_CLK_EN_MSK 0x00008000
+#define US3TMR_CLK_EN_I_MSK 0xffff7fff
+#define US3TMR_CLK_EN_SFT 15
+#define US3TMR_CLK_EN_HI 15
+#define US3TMR_CLK_EN_SZ 1
+#define MS0TMR_CLK_EN_MSK 0x00010000
+#define MS0TMR_CLK_EN_I_MSK 0xfffeffff
+#define MS0TMR_CLK_EN_SFT 16
+#define MS0TMR_CLK_EN_HI 16
+#define MS0TMR_CLK_EN_SZ 1
+#define MS1TMR_CLK_EN_MSK 0x00020000
+#define MS1TMR_CLK_EN_I_MSK 0xfffdffff
+#define MS1TMR_CLK_EN_SFT 17
+#define MS1TMR_CLK_EN_HI 17
+#define MS1TMR_CLK_EN_SZ 1
+#define MS2TMR_CLK_EN_MSK 0x00040000
+#define MS2TMR_CLK_EN_I_MSK 0xfffbffff
+#define MS2TMR_CLK_EN_SFT 18
+#define MS2TMR_CLK_EN_HI 18
+#define MS2TMR_CLK_EN_SZ 1
+#define MS3TMR_CLK_EN_MSK 0x00080000
+#define MS3TMR_CLK_EN_I_MSK 0xfff7ffff
+#define MS3TMR_CLK_EN_SFT 19
+#define MS3TMR_CLK_EN_HI 19
+#define MS3TMR_CLK_EN_SZ 1
+#define SPI_MST2CBRA_CLK_EN_MSK 0x00100000
+#define SPI_MST2CBRA_CLK_EN_I_MSK 0xffefffff
+#define SPI_MST2CBRA_CLK_EN_SFT 20
+#define SPI_MST2CBRA_CLK_EN_HI 20
+#define SPI_MST2CBRA_CLK_EN_SZ 1
+#define AHB2PKT_CLK_EN_MSK 0x00200000
+#define AHB2PKT_CLK_EN_I_MSK 0xffdfffff
+#define AHB2PKT_CLK_EN_SFT 21
+#define AHB2PKT_CLK_EN_HI 21
+#define AHB2PKT_CLK_EN_SZ 1
+#define PWM_CLK_EN_MSK 0x00400000
+#define PWM_CLK_EN_I_MSK 0xffbfffff
+#define PWM_CLK_EN_SFT 22
+#define PWM_CLK_EN_HI 22
+#define PWM_CLK_EN_SZ 1
+#define I2C_MST_CLK_EN_MSK 0x00800000
+#define I2C_MST_CLK_EN_I_MSK 0xff7fffff
+#define I2C_MST_CLK_EN_SFT 23
+#define I2C_MST_CLK_EN_HI 23
+#define I2C_MST_CLK_EN_SZ 1
+#define RESET_N_CPUN10_MSK 0x01000000
+#define RESET_N_CPUN10_I_MSK 0xfeffffff
+#define RESET_N_CPUN10_SFT 24
+#define RESET_N_CPUN10_HI 24
+#define RESET_N_CPUN10_SZ 1
+#define USB_CLK_EN_MSK 0x02000000
+#define USB_CLK_EN_I_MSK 0xfdffffff
+#define USB_CLK_EN_SFT 25
+#define USB_CLK_EN_HI 25
+#define USB_CLK_EN_SZ 1
+#define CLK_EN_USB_PHY30M_MSK 0x04000000
+#define CLK_EN_USB_PHY30M_I_MSK 0xfbffffff
+#define CLK_EN_USB_PHY30M_SFT 26
+#define CLK_EN_USB_PHY30M_HI 26
+#define CLK_EN_USB_PHY30M_SZ 1
+#define CLK_EN_USB_CTRLUTMI_MSK 0x08000000
+#define CLK_EN_USB_CTRLUTMI_I_MSK 0xf7ffffff
+#define CLK_EN_USB_CTRLUTMI_SFT 27
+#define CLK_EN_USB_CTRLUTMI_HI 27
+#define CLK_EN_USB_CTRLUTMI_SZ 1
+#define PHY_IQ_LOG_CLK_EN_MSK 0x10000000
+#define PHY_IQ_LOG_CLK_EN_I_MSK 0xefffffff
+#define PHY_IQ_LOG_CLK_EN_SFT 28
+#define PHY_IQ_LOG_CLK_EN_HI 28
+#define PHY_IQ_LOG_CLK_EN_SZ 1
+#define SPIMAS_CLK_EN_MSK 0x20000000
+#define SPIMAS_CLK_EN_I_MSK 0xdfffffff
+#define SPIMAS_CLK_EN_SFT 29
+#define SPIMAS_CLK_EN_HI 29
+#define SPIMAS_CLK_EN_SZ 1
+#define I2S_PCLK_EN_MSK 0x40000000
+#define I2S_PCLK_EN_I_MSK 0xbfffffff
+#define I2S_PCLK_EN_SFT 30
+#define I2S_PCLK_EN_HI 30
+#define I2S_PCLK_EN_SZ 1
+#define CLK_EN_PHYRF40M_MSK 0x00000001
+#define CLK_EN_PHYRF40M_I_MSK 0xfffffffe
+#define CLK_EN_PHYRF40M_SFT 0
+#define CLK_EN_PHYRF40M_HI 0
+#define CLK_EN_PHYRF40M_SZ 1
+#define CLK_EN_PHYRF80M_MSK 0x00000002
+#define CLK_EN_PHYRF80M_I_MSK 0xfffffffd
+#define CLK_EN_PHYRF80M_SFT 1
+#define CLK_EN_PHYRF80M_HI 1
+#define CLK_EN_PHYRF80M_SZ 1
+#define CLK_EN_160M_PHY_MSK 0x00000004
+#define CLK_EN_160M_PHY_I_MSK 0xfffffffb
+#define CLK_EN_160M_PHY_SFT 2
+#define CLK_EN_160M_PHY_HI 2
+#define CLK_EN_160M_PHY_SZ 1
+#define BTCX_CSR_CLK_EN_MSK 0x00000400
+#define BTCX_CSR_CLK_EN_I_MSK 0xfffffbff
+#define BTCX_CSR_CLK_EN_SFT 10
+#define BTCX_CSR_CLK_EN_HI 10
+#define BTCX_CSR_CLK_EN_SZ 1
+#define CLK_EN_MBIST_MSK 0x00000800
+#define CLK_EN_MBIST_I_MSK 0xfffff7ff
+#define CLK_EN_MBIST_SFT 11
+#define CLK_EN_MBIST_HI 11
+#define CLK_EN_MBIST_SZ 1
+#define R_BOOTSTRAP_SAMPLE_MSK 0x0000000f
+#define R_BOOTSTRAP_SAMPLE_I_MSK 0xfffffff0
+#define R_BOOTSTRAP_SAMPLE_SFT 0
+#define R_BOOTSTRAP_SAMPLE_HI 3
+#define R_BOOTSTRAP_SAMPLE_SZ 4
+#define N10_CORE_CURRENT_PC_MSK 0xffffffff
+#define N10_CORE_CURRENT_PC_I_MSK 0x00000000
+#define N10_CORE_CURRENT_PC_SFT 0
+#define N10_CORE_CURRENT_PC_HI 31
+#define N10_CORE_CURRENT_PC_SZ 32
+#define N10_STANDBY_REQ_MSK 0x08000000
+#define N10_STANDBY_REQ_I_MSK 0xf7ffffff
+#define N10_STANDBY_REQ_SFT 27
+#define N10_STANDBY_REQ_HI 27
+#define N10_STANDBY_REQ_SZ 1
+#define N10_CORE_STANDBY_MODE_MSK 0x10000000
+#define N10_CORE_STANDBY_MODE_I_MSK 0xefffffff
+#define N10_CORE_STANDBY_MODE_SFT 28
+#define N10_CORE_STANDBY_MODE_HI 28
+#define N10_CORE_STANDBY_MODE_SZ 1
+#define N10_CORE_DEBUG_MODE_MSK 0x20000000
+#define N10_CORE_DEBUG_MODE_I_MSK 0xdfffffff
+#define N10_CORE_DEBUG_MODE_SFT 29
+#define N10_CORE_DEBUG_MODE_HI 29
+#define N10_CORE_DEBUG_MODE_SZ 1
+#define N10_STANDBY_MSK 0x40000000
+#define N10_STANDBY_I_MSK 0xbfffffff
+#define N10_STANDBY_SFT 30
+#define N10_STANDBY_HI 30
+#define N10_STANDBY_SZ 1
+#define N10_WAKEUP_OK_MSK 0x80000000
+#define N10_WAKEUP_OK_I_MSK 0x7fffffff
+#define N10_WAKEUP_OK_SFT 31
+#define N10_WAKEUP_OK_HI 31
+#define N10_WAKEUP_OK_SZ 1
+#define SYS_CLOCK_STATE_MSK 0x00000007
+#define SYS_CLOCK_STATE_I_MSK 0xfffffff8
+#define SYS_CLOCK_STATE_SFT 0
+#define SYS_CLOCK_STATE_HI 2
+#define SYS_CLOCK_STATE_SZ 3
+#define ROM_READ_PROT_MSK 0x00000001
+#define ROM_READ_PROT_I_MSK 0xfffffffe
+#define ROM_READ_PROT_SFT 0
+#define ROM_READ_PROT_HI 0
+#define ROM_READ_PROT_SZ 1
+#define GPIO_STOP_SEL_MSK 0x007fffff
+#define GPIO_STOP_SEL_I_MSK 0xff800000
+#define GPIO_STOP_SEL_SFT 0
+#define GPIO_STOP_SEL_HI 22
+#define GPIO_STOP_SEL_SZ 23
+#define GPIO_STOP_POL_MSK 0x40000000
+#define GPIO_STOP_POL_I_MSK 0xbfffffff
+#define GPIO_STOP_POL_SFT 30
+#define GPIO_STOP_POL_HI 30
+#define GPIO_STOP_POL_SZ 1
+#define GPIO_STOP_EN_MSK 0x80000000
+#define GPIO_STOP_EN_I_MSK 0x7fffffff
+#define GPIO_STOP_EN_SFT 31
+#define GPIO_STOP_EN_HI 31
+#define GPIO_STOP_EN_SZ 1
+#define TB_ADR_SEL_MSK 0x0000ffff
+#define TB_ADR_SEL_I_MSK 0xffff0000
+#define TB_ADR_SEL_SFT 0
+#define TB_ADR_SEL_HI 15
+#define TB_ADR_SEL_SZ 16
+#define TB_CS_MSK 0x80000000
+#define TB_CS_I_MSK 0x7fffffff
+#define TB_CS_SFT 31
+#define TB_CS_HI 31
+#define TB_CS_SZ 1
+#define TB_RDATA_MSK 0xffffffff
+#define TB_RDATA_I_MSK 0x00000000
+#define TB_RDATA_SFT 0
+#define TB_RDATA_HI 31
+#define TB_RDATA_SZ 32
+#define UART_W2B_EN_MSK 0x00000001
+#define UART_W2B_EN_I_MSK 0xfffffffe
+#define UART_W2B_EN_SFT 0
+#define UART_W2B_EN_HI 0
+#define UART_W2B_EN_SZ 1
+#define SYSCTRL_CMD_MSK 0xffffffff
+#define SYSCTRL_CMD_I_MSK 0x00000000
+#define SYSCTRL_CMD_SFT 0
+#define SYSCTRL_CMD_HI 31
+#define SYSCTRL_CMD_SZ 32
+#define CLK_FBUS_SEL_MSK 0x0000000f
+#define CLK_FBUS_SEL_I_MSK 0xfffffff0
+#define CLK_FBUS_SEL_SFT 0
+#define CLK_FBUS_SEL_HI 3
+#define CLK_FBUS_SEL_SZ 4
+#define SYS_XOSC_ON_MSK 0x00000001
+#define SYS_XOSC_ON_I_MSK 0xfffffffe
+#define SYS_XOSC_ON_SFT 0
+#define SYS_XOSC_ON_HI 0
+#define SYS_XOSC_ON_SZ 1
+#define SYS_DPLL_ON_MSK 0x00000002
+#define SYS_DPLL_ON_I_MSK 0xfffffffd
+#define SYS_DPLL_ON_SFT 1
+#define SYS_DPLL_ON_HI 1
+#define SYS_DPLL_ON_SZ 1
+#define FSM_SYSCTRL_MSK 0x00001f00
+#define FSM_SYSCTRL_I_MSK 0xffffe0ff
+#define FSM_SYSCTRL_SFT 8
+#define FSM_SYSCTRL_HI 12
+#define FSM_SYSCTRL_SZ 5
+#define I2SMAS_CLK_DIV_MSK 0x00003fff
+#define I2SMAS_CLK_DIV_I_MSK 0xffffc000
+#define I2SMAS_CLK_DIV_SFT 0
+#define I2SMAS_CLK_DIV_HI 13
+#define I2SMAS_CLK_DIV_SZ 14
+#define I2S_MCLK_DIV_MSK 0x00030000
+#define I2S_MCLK_DIV_I_MSK 0xfffcffff
+#define I2S_MCLK_DIV_SFT 16
+#define I2S_MCLK_DIV_HI 17
+#define I2S_MCLK_DIV_SZ 2
+#define I2S_MASTER_MSK 0x80000000
+#define I2S_MASTER_I_MSK 0x7fffffff
+#define I2S_MASTER_SFT 31
+#define I2S_MASTER_HI 31
+#define I2S_MASTER_SZ 1
+#define HBUSREQ_LOCK_MSK 0x00001fff
+#define HBUSREQ_LOCK_I_MSK 0xffffe000
+#define HBUSREQ_LOCK_SFT 0
+#define HBUSREQ_LOCK_HI 12
+#define HBUSREQ_LOCK_SZ 13
+#define HBURST_LOCK_MSK 0x00001fff
+#define HBURST_LOCK_I_MSK 0xffffe000
+#define HBURST_LOCK_SFT 0
+#define HBURST_LOCK_HI 12
+#define HBURST_LOCK_SZ 13
+#define FENCE_HIT_ADR_MSK 0x001fffff
+#define FENCE_HIT_ADR_I_MSK 0xffe00000
+#define FENCE_HIT_ADR_SFT 0
+#define FENCE_HIT_ADR_HI 20
+#define FENCE_HIT_ADR_SZ 21
+#define EDLM_SRAM_ERRCK_EN_MSK 0x08000000
+#define EDLM_SRAM_ERRCK_EN_I_MSK 0xf7ffffff
+#define EDLM_SRAM_ERRCK_EN_SFT 27
+#define EDLM_SRAM_ERRCK_EN_HI 27
+#define EDLM_SRAM_ERRCK_EN_SZ 1
+#define EILM_ROM_ERRCK_EN_MSK 0x10000000
+#define EILM_ROM_ERRCK_EN_I_MSK 0xefffffff
+#define EILM_ROM_ERRCK_EN_SFT 28
+#define EILM_ROM_ERRCK_EN_HI 28
+#define EILM_ROM_ERRCK_EN_SZ 1
+#define EILM_SRAM_ERRCK_EN_MSK 0x20000000
+#define EILM_SRAM_ERRCK_EN_I_MSK 0xdfffffff
+#define EILM_SRAM_ERRCK_EN_SFT 29
+#define EILM_SRAM_ERRCK_EN_HI 29
+#define EILM_SRAM_ERRCK_EN_SZ 1
+#define FBUS_SRAM_ERRCK_EN_MSK 0x40000000
+#define FBUS_SRAM_ERRCK_EN_I_MSK 0xbfffffff
+#define FBUS_SRAM_ERRCK_EN_SFT 30
+#define FBUS_SRAM_ERRCK_EN_HI 30
+#define FBUS_SRAM_ERRCK_EN_SZ 1
+#define FENCE_HIT_EN_MSK 0x80000000
+#define FENCE_HIT_EN_I_MSK 0x7fffffff
+#define FENCE_HIT_EN_SFT 31
+#define FENCE_HIT_EN_HI 31
+#define FENCE_HIT_EN_SZ 1
+#define EDLM_SRAM_ERR_INT_MSK 0x00000001
+#define EDLM_SRAM_ERR_INT_I_MSK 0xfffffffe
+#define EDLM_SRAM_ERR_INT_SFT 0
+#define EDLM_SRAM_ERR_INT_HI 0
+#define EDLM_SRAM_ERR_INT_SZ 1
+#define EILM_ROM_ERR_INT_MSK 0x00000002
+#define EILM_ROM_ERR_INT_I_MSK 0xfffffffd
+#define EILM_ROM_ERR_INT_SFT 1
+#define EILM_ROM_ERR_INT_HI 1
+#define EILM_ROM_ERR_INT_SZ 1
+#define EILM_SRAM_ERR_INT_MSK 0x00000004
+#define EILM_SRAM_ERR_INT_I_MSK 0xfffffffb
+#define EILM_SRAM_ERR_INT_SFT 2
+#define EILM_SRAM_ERR_INT_HI 2
+#define EILM_SRAM_ERR_INT_SZ 1
+#define FBUS_SRAM_ERR_INT_MSK 0x00000008
+#define FBUS_SRAM_ERR_INT_I_MSK 0xfffffff7
+#define FBUS_SRAM_ERR_INT_SFT 3
+#define FBUS_SRAM_ERR_INT_HI 3
+#define FBUS_SRAM_ERR_INT_SZ 1
+#define FENCE_HIT_INT_MSK 0x00000010
+#define FENCE_HIT_INT_I_MSK 0xffffffef
+#define FENCE_HIT_INT_SFT 4
+#define FENCE_HIT_INT_HI 4
+#define FENCE_HIT_INT_SZ 1
+#define TOP_SW_PWR_ON1_OUTPUT_PWR_ON1_1_0_0_MSK 0x00000001
+#define TOP_SW_PWR_ON1_OUTPUT_PWR_ON1_1_0_0_I_MSK 0xfffffffe
+#define TOP_SW_PWR_ON1_OUTPUT_PWR_ON1_1_0_0_SFT 0
+#define TOP_SW_PWR_ON1_OUTPUT_PWR_ON1_1_0_0_HI 0
+#define TOP_SW_PWR_ON1_OUTPUT_PWR_ON1_1_0_0_SZ 1
+#define TOP_SW_PWR_ON2_OUTPUT_PWR_ON2_1_0_0_MSK 0x00000002
+#define TOP_SW_PWR_ON2_OUTPUT_PWR_ON2_1_0_0_I_MSK 0xfffffffd
+#define TOP_SW_PWR_ON2_OUTPUT_PWR_ON2_1_0_0_SFT 1
+#define TOP_SW_PWR_ON2_OUTPUT_PWR_ON2_1_0_0_HI 1
+#define TOP_SW_PWR_ON2_OUTPUT_PWR_ON2_1_0_0_SZ 1
+#define TOP_SW_PWR_ON3_OUTPUT_PWR_ON3_1_0_0_MSK 0x00000004
+#define TOP_SW_PWR_ON3_OUTPUT_PWR_ON3_1_0_0_I_MSK 0xfffffffb
+#define TOP_SW_PWR_ON3_OUTPUT_PWR_ON3_1_0_0_SFT 2
+#define TOP_SW_PWR_ON3_OUTPUT_PWR_ON3_1_0_0_HI 2
+#define TOP_SW_PWR_ON3_OUTPUT_PWR_ON3_1_0_0_SZ 1
+#define VIAROM_EMA_MSK 0x00000007
+#define VIAROM_EMA_I_MSK 0xfffffff8
+#define VIAROM_EMA_SFT 0
+#define VIAROM_EMA_HI 2
+#define VIAROM_EMA_SZ 3
+#define TEST_MODE0_MSK 0x00000001
+#define TEST_MODE0_I_MSK 0xfffffffe
+#define TEST_MODE0_SFT 0
+#define TEST_MODE0_HI 0
+#define TEST_MODE0_SZ 1
+#define TEST_MODE1_MSK 0x00000002
+#define TEST_MODE1_I_MSK 0xfffffffd
+#define TEST_MODE1_SFT 1
+#define TEST_MODE1_HI 1
+#define TEST_MODE1_SZ 1
+#define TEST_MODE2_MSK 0x00000004
+#define TEST_MODE2_I_MSK 0xfffffffb
+#define TEST_MODE2_SFT 2
+#define TEST_MODE2_HI 2
+#define TEST_MODE2_SZ 1
+#define TEST_MODE3_MSK 0x00000008
+#define TEST_MODE3_I_MSK 0xfffffff7
+#define TEST_MODE3_SFT 3
+#define TEST_MODE3_HI 3
+#define TEST_MODE3_SZ 1
+#define TEST_MODE4_MSK 0x00000010
+#define TEST_MODE4_I_MSK 0xffffffef
+#define TEST_MODE4_SFT 4
+#define TEST_MODE4_HI 4
+#define TEST_MODE4_SZ 1
+#define TEST_MODE_ALL_MSK 0x00000020
+#define TEST_MODE_ALL_I_MSK 0xffffffdf
+#define TEST_MODE_ALL_SFT 5
+#define TEST_MODE_ALL_HI 5
+#define TEST_MODE_ALL_SZ 1
+#define CLK_EN_CPUN10_MSK 0x00000002
+#define CLK_EN_CPUN10_I_MSK 0xfffffffd
+#define CLK_EN_CPUN10_SFT 1
+#define CLK_EN_CPUN10_HI 1
+#define CLK_EN_CPUN10_SZ 1
+#define N10_WARM_RESET_N_MSK 0x00000004
+#define N10_WARM_RESET_N_I_MSK 0xfffffffb
+#define N10_WARM_RESET_N_SFT 2
+#define N10_WARM_RESET_N_HI 2
+#define N10_WARM_RESET_N_SZ 1
+#define FW_EVENT_MSK 0xffffffff
+#define FW_EVENT_I_MSK 0x00000000
+#define FW_EVENT_SFT 0
+#define FW_EVENT_HI 31
+#define FW_EVENT_SZ 32
+#define HOST_EVENT_MSK 0xffffffff
+#define HOST_EVENT_I_MSK 0x00000000
+#define HOST_EVENT_SFT 0
+#define HOST_EVENT_HI 31
+#define HOST_EVENT_SZ 32
+#define CHIP_INFO_ID_31_0_MSK 0xffffffff
+#define CHIP_INFO_ID_31_0_I_MSK 0x00000000
+#define CHIP_INFO_ID_31_0_SFT 0
+#define CHIP_INFO_ID_31_0_HI 31
+#define CHIP_INFO_ID_31_0_SZ 32
+#define CHIP_INFO_ID_63_32_MSK 0xffffffff
+#define CHIP_INFO_ID_63_32_I_MSK 0x00000000
+#define CHIP_INFO_ID_63_32_SFT 0
+#define CHIP_INFO_ID_63_32_HI 31
+#define CHIP_INFO_ID_63_32_SZ 32
+#define CHIP_VER_MSK 0x00ffffff
+#define CHIP_VER_I_MSK 0xff000000
+#define CHIP_VER_SFT 0
+#define CHIP_VER_HI 23
+#define CHIP_VER_SZ 24
+#define CHIP_TYPE_MSK 0xff000000
+#define CHIP_TYPE_I_MSK 0x00ffffff
+#define CHIP_TYPE_SFT 24
+#define CHIP_TYPE_HI 31
+#define CHIP_TYPE_SZ 8
+#define CHIP_DATE_YYYYMMDD_MSK 0xffffffff
+#define CHIP_DATE_YYYYMMDD_I_MSK 0x00000000
+#define CHIP_DATE_YYYYMMDD_SFT 0
+#define CHIP_DATE_YYYYMMDD_HI 31
+#define CHIP_DATE_YYYYMMDD_SZ 32
+#define CHIP_DATE_00HHMMSS_MSK 0x00ffffff
+#define CHIP_DATE_00HHMMSS_I_MSK 0xff000000
+#define CHIP_DATE_00HHMMSS_SFT 0
+#define CHIP_DATE_00HHMMSS_HI 23
+#define CHIP_DATE_00HHMMSS_SZ 24
+#define CHIP_GITSHA_31_0_MSK 0xffffffff
+#define CHIP_GITSHA_31_0_I_MSK 0x00000000
+#define CHIP_GITSHA_31_0_SFT 0
+#define CHIP_GITSHA_31_0_HI 31
+#define CHIP_GITSHA_31_0_SZ 32
+#define CHIP_GITSHA_63_32_MSK 0xffffffff
+#define CHIP_GITSHA_63_32_I_MSK 0x00000000
+#define CHIP_GITSHA_63_32_SFT 0
+#define CHIP_GITSHA_63_32_HI 31
+#define CHIP_GITSHA_63_32_SZ 32
+#define CHIP_GITSHA_95_64_MSK 0xffffffff
+#define CHIP_GITSHA_95_64_I_MSK 0x00000000
+#define CHIP_GITSHA_95_64_SFT 0
+#define CHIP_GITSHA_95_64_HI 31
+#define CHIP_GITSHA_95_64_SZ 32
+#define CHIP_GITSHA_127_96_MSK 0xffffffff
+#define CHIP_GITSHA_127_96_I_MSK 0x00000000
+#define CHIP_GITSHA_127_96_SFT 0
+#define CHIP_GITSHA_127_96_HI 31
+#define CHIP_GITSHA_127_96_SZ 32
+#define CHIP_GITSHA_159_128_MSK 0xffffffff
+#define CHIP_GITSHA_159_128_I_MSK 0x00000000
+#define CHIP_GITSHA_159_128_SFT 0
+#define CHIP_GITSHA_159_128_HI 31
+#define CHIP_GITSHA_159_128_SZ 32
+#define N10CFG_DEFAULT_IVB_MSK 0x0000ffff
+#define N10CFG_DEFAULT_IVB_I_MSK 0xffff0000
+#define N10CFG_DEFAULT_IVB_SFT 0
+#define N10CFG_DEFAULT_IVB_HI 15
+#define N10CFG_DEFAULT_IVB_SZ 16
+#define SYS_N10_IVB_VAL_MSK 0xffff0000
+#define SYS_N10_IVB_VAL_I_MSK 0x0000ffff
+#define SYS_N10_IVB_VAL_SFT 16
+#define SYS_N10_IVB_VAL_HI 31
+#define SYS_N10_IVB_VAL_SZ 16
+#define USB20_HOST_SELRW_MSK 0x00000001
+#define USB20_HOST_SELRW_I_MSK 0xfffffffe
+#define USB20_HOST_SELRW_SFT 0
+#define USB20_HOST_SELRW_HI 0
+#define USB20_HOST_SELRW_SZ 1
+#define CHIP_INFO_FPGA_TAG_MSK 0xffffffff
+#define CHIP_INFO_FPGA_TAG_I_MSK 0x00000000
+#define CHIP_INFO_FPGA_TAG_SFT 0
+#define CHIP_INFO_FPGA_TAG_HI 31
+#define CHIP_INFO_FPGA_TAG_SZ 32
+#define SYS_PMU_MODE_TRAN_INT_MSK 0x00000001
+#define SYS_PMU_MODE_TRAN_INT_I_MSK 0xfffffffe
+#define SYS_PMU_MODE_TRAN_INT_SFT 0
+#define SYS_PMU_MODE_TRAN_INT_HI 0
+#define SYS_PMU_MODE_TRAN_INT_SZ 1
+#define DBG_WRITE_TO_FINISH_SIM_MSK 0x00000001
+#define DBG_WRITE_TO_FINISH_SIM_I_MSK 0xfffffffe
+#define DBG_WRITE_TO_FINISH_SIM_SFT 0
+#define DBG_WRITE_TO_FINISH_SIM_HI 0
+#define DBG_WRITE_TO_FINISH_SIM_SZ 1
+#define DATA_SPI_WAKEUP_MSK 0x00000001
+#define DATA_SPI_WAKEUP_I_MSK 0xfffffffe
+#define DATA_SPI_WAKEUP_SFT 0
+#define DATA_SPI_WAKEUP_HI 0
+#define DATA_SPI_WAKEUP_SZ 1
+#define WAKE_SOON_WITH_SCK_MSK 0x00000001
+#define WAKE_SOON_WITH_SCK_I_MSK 0xfffffffe
+#define WAKE_SOON_WITH_SCK_SFT 0
+#define WAKE_SOON_WITH_SCK_HI 0
+#define WAKE_SOON_WITH_SCK_SZ 1
+#define ALLOW_SD_SPI_RESET_MSK 0x00000002
+#define ALLOW_SD_SPI_RESET_I_MSK 0xfffffffd
+#define ALLOW_SD_SPI_RESET_SFT 1
+#define ALLOW_SD_SPI_RESET_HI 1
+#define ALLOW_SD_SPI_RESET_SZ 1
+#define WDT_MCU_RESET_MSK 0x00000001
+#define WDT_MCU_RESET_I_MSK 0xfffffffe
+#define WDT_MCU_RESET_SFT 0
+#define WDT_MCU_RESET_HI 0
+#define WDT_MCU_RESET_SZ 1
+#define WDT_SYS_RESET_MSK 0x00000002
+#define WDT_SYS_RESET_I_MSK 0xfffffffd
+#define WDT_SYS_RESET_SFT 1
+#define WDT_SYS_RESET_HI 1
+#define WDT_SYS_RESET_SZ 1
+#define SDIO_CMD52_06H_RESET_MSK 0x00000004
+#define SDIO_CMD52_06H_RESET_I_MSK 0xfffffffb
+#define SDIO_CMD52_06H_RESET_SFT 2
+#define SDIO_CMD52_06H_RESET_HI 2
+#define SDIO_CMD52_06H_RESET_SZ 1
+#define DATA_SPI_RESET_MSK 0x00000008
+#define DATA_SPI_RESET_I_MSK 0xfffffff7
+#define DATA_SPI_RESET_SFT 3
+#define DATA_SPI_RESET_HI 3
+#define DATA_SPI_RESET_SZ 1
+#define UART_NRTS_MSK 0x00000001
+#define UART_NRTS_I_MSK 0xfffffffe
+#define UART_NRTS_SFT 0
+#define UART_NRTS_HI 0
+#define UART_NRTS_SZ 1
+#define UART_NCTS_MSK 0x00000002
+#define UART_NCTS_I_MSK 0xfffffffd
+#define UART_NCTS_SFT 1
+#define UART_NCTS_HI 1
+#define UART_NCTS_SZ 1
+#define NORMAL_PWR_ON1_MSK 0x00000001
+#define NORMAL_PWR_ON1_I_MSK 0xfffffffe
+#define NORMAL_PWR_ON1_SFT 0
+#define NORMAL_PWR_ON1_HI 0
+#define NORMAL_PWR_ON1_SZ 1
+#define NORMAL_PWR_ON2_MSK 0x00000002
+#define NORMAL_PWR_ON2_I_MSK 0xfffffffd
+#define NORMAL_PWR_ON2_SFT 1
+#define NORMAL_PWR_ON2_HI 1
+#define NORMAL_PWR_ON2_SZ 1
+#define NORMAL_PWR_ON3_MSK 0x00000004
+#define NORMAL_PWR_ON3_I_MSK 0xfffffffb
+#define NORMAL_PWR_ON3_SFT 2
+#define NORMAL_PWR_ON3_HI 2
+#define NORMAL_PWR_ON3_SZ 1
+#define SUSPEND_PWR_ON1_MSK 0x00000010
+#define SUSPEND_PWR_ON1_I_MSK 0xffffffef
+#define SUSPEND_PWR_ON1_SFT 4
+#define SUSPEND_PWR_ON1_HI 4
+#define SUSPEND_PWR_ON1_SZ 1
+#define SUSPEND_PWR_ON2_MSK 0x00000020
+#define SUSPEND_PWR_ON2_I_MSK 0xffffffdf
+#define SUSPEND_PWR_ON2_SFT 5
+#define SUSPEND_PWR_ON2_HI 5
+#define SUSPEND_PWR_ON2_SZ 1
+#define SUSPEND_PWR_ON3_MSK 0x00000040
+#define SUSPEND_PWR_ON3_I_MSK 0xffffffbf
+#define SUSPEND_PWR_ON3_SFT 6
+#define SUSPEND_PWR_ON3_HI 6
+#define SUSPEND_PWR_ON3_SZ 1
+#define NORMAL_ISO_ON1_MSK 0x00000100
+#define NORMAL_ISO_ON1_I_MSK 0xfffffeff
+#define NORMAL_ISO_ON1_SFT 8
+#define NORMAL_ISO_ON1_HI 8
+#define NORMAL_ISO_ON1_SZ 1
+#define NORMAL_ISO_ON2_MSK 0x00000200
+#define NORMAL_ISO_ON2_I_MSK 0xfffffdff
+#define NORMAL_ISO_ON2_SFT 9
+#define NORMAL_ISO_ON2_HI 9
+#define NORMAL_ISO_ON2_SZ 1
+#define NORMAL_ISO_ON3_MSK 0x00000400
+#define NORMAL_ISO_ON3_I_MSK 0xfffffbff
+#define NORMAL_ISO_ON3_SFT 10
+#define NORMAL_ISO_ON3_HI 10
+#define NORMAL_ISO_ON3_SZ 1
+#define TOP_ON1_RST_N_MSK 0x00001000
+#define TOP_ON1_RST_N_I_MSK 0xffffefff
+#define TOP_ON1_RST_N_SFT 12
+#define TOP_ON1_RST_N_HI 12
+#define TOP_ON1_RST_N_SZ 1
+#define TOP_ON2_RST_N_MSK 0x00002000
+#define TOP_ON2_RST_N_I_MSK 0xffffdfff
+#define TOP_ON2_RST_N_SFT 13
+#define TOP_ON2_RST_N_HI 13
+#define TOP_ON2_RST_N_SZ 1
+#define TOP_ON3_RST_N_MSK 0x00004000
+#define TOP_ON3_RST_N_I_MSK 0xffffbfff
+#define TOP_ON3_RST_N_SFT 14
+#define TOP_ON3_RST_N_HI 14
+#define TOP_ON3_RST_N_SZ 1
+#define HOST_WAKE_WIFI_MSK 0x007fffff
+#define HOST_WAKE_WIFI_I_MSK 0xff800000
+#define HOST_WAKE_WIFI_SFT 0
+#define HOST_WAKE_WIFI_HI 22
+#define HOST_WAKE_WIFI_SZ 23
+#define HOST_WAKE_WIFI_POL_MSK 0x80000000
+#define HOST_WAKE_WIFI_POL_I_MSK 0x7fffffff
+#define HOST_WAKE_WIFI_POL_SFT 31
+#define HOST_WAKE_WIFI_POL_HI 31
+#define HOST_WAKE_WIFI_POL_SZ 1
+#define PRESCALER_US_MSK 0x000001ff
+#define PRESCALER_US_I_MSK 0xfffffe00
+#define PRESCALER_US_SFT 0
+#define PRESCALER_US_HI 8
+#define PRESCALER_US_SZ 9
+#define RTC_TIMER_WAKE_PMU_EN_MSK 0x00000001
+#define RTC_TIMER_WAKE_PMU_EN_I_MSK 0xfffffffe
+#define RTC_TIMER_WAKE_PMU_EN_SFT 0
+#define RTC_TIMER_WAKE_PMU_EN_HI 0
+#define RTC_TIMER_WAKE_PMU_EN_SZ 1
+#define USB_WAKE_PMU_EN_MSK 0x00000002
+#define USB_WAKE_PMU_EN_I_MSK 0xfffffffd
+#define USB_WAKE_PMU_EN_SFT 1
+#define USB_WAKE_PMU_EN_HI 1
+#define USB_WAKE_PMU_EN_SZ 1
+#define ILM160KB_EN_MSK 0x00000002
+#define ILM160KB_EN_I_MSK 0xfffffffd
+#define ILM160KB_EN_SFT 1
+#define ILM160KB_EN_HI 1
+#define ILM160KB_EN_SZ 1
+#define PATCH00_EN_MSK 0x00000001
+#define PATCH00_EN_I_MSK 0xfffffffe
+#define PATCH00_EN_SFT 0
+#define PATCH00_EN_HI 0
+#define PATCH00_EN_SZ 1
+#define PATCH00_ADDR_MSK 0x0001fffc
+#define PATCH00_ADDR_I_MSK 0xfffe0003
+#define PATCH00_ADDR_SFT 2
+#define PATCH00_ADDR_HI 16
+#define PATCH00_ADDR_SZ 15
+#define PATCH00_DATA_MSK 0xffffffff
+#define PATCH00_DATA_I_MSK 0x00000000
+#define PATCH00_DATA_SFT 0
+#define PATCH00_DATA_HI 31
+#define PATCH00_DATA_SZ 32
+#define PATCH01_EN_MSK 0x00000001
+#define PATCH01_EN_I_MSK 0xfffffffe
+#define PATCH01_EN_SFT 0
+#define PATCH01_EN_HI 0
+#define PATCH01_EN_SZ 1
+#define PATCH01_ADDR_MSK 0x0001fffc
+#define PATCH01_ADDR_I_MSK 0xfffe0003
+#define PATCH01_ADDR_SFT 2
+#define PATCH01_ADDR_HI 16
+#define PATCH01_ADDR_SZ 15
+#define PATCH01_DATA_MSK 0xffffffff
+#define PATCH01_DATA_I_MSK 0x00000000
+#define PATCH01_DATA_SFT 0
+#define PATCH01_DATA_HI 31
+#define PATCH01_DATA_SZ 32
+#define TU0_TM_INIT_VALUE_MSK 0x0000ffff
+#define TU0_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TU0_TM_INIT_VALUE_SFT 0
+#define TU0_TM_INIT_VALUE_HI 15
+#define TU0_TM_INIT_VALUE_SZ 16
+#define TU0_TM_MODE_MSK 0x00010000
+#define TU0_TM_MODE_I_MSK 0xfffeffff
+#define TU0_TM_MODE_SFT 16
+#define TU0_TM_MODE_HI 16
+#define TU0_TM_MODE_SZ 1
+#define TU0_TM_INT_STS_DONE_MSK 0x00020000
+#define TU0_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TU0_TM_INT_STS_DONE_SFT 17
+#define TU0_TM_INT_STS_DONE_HI 17
+#define TU0_TM_INT_STS_DONE_SZ 1
+#define TU0_TM_INT_MASK_MSK 0x00040000
+#define TU0_TM_INT_MASK_I_MSK 0xfffbffff
+#define TU0_TM_INT_MASK_SFT 18
+#define TU0_TM_INT_MASK_HI 18
+#define TU0_TM_INT_MASK_SZ 1
+#define TU0_TM_CUR_VALUE_MSK 0x0000ffff
+#define TU0_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TU0_TM_CUR_VALUE_SFT 0
+#define TU0_TM_CUR_VALUE_HI 15
+#define TU0_TM_CUR_VALUE_SZ 16
+#define TU0_PRESCALER_USTIMER_LOCAL_MSK 0x000001ff
+#define TU0_PRESCALER_USTIMER_LOCAL_I_MSK 0xfffffe00
+#define TU0_PRESCALER_USTIMER_LOCAL_SFT 0
+#define TU0_PRESCALER_USTIMER_LOCAL_HI 8
+#define TU0_PRESCALER_USTIMER_LOCAL_SZ 9
+#define TU1_TM_INIT_VALUE_MSK 0x0000ffff
+#define TU1_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TU1_TM_INIT_VALUE_SFT 0
+#define TU1_TM_INIT_VALUE_HI 15
+#define TU1_TM_INIT_VALUE_SZ 16
+#define TU1_TM_MODE_MSK 0x00010000
+#define TU1_TM_MODE_I_MSK 0xfffeffff
+#define TU1_TM_MODE_SFT 16
+#define TU1_TM_MODE_HI 16
+#define TU1_TM_MODE_SZ 1
+#define TU1_TM_INT_STS_DONE_MSK 0x00020000
+#define TU1_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TU1_TM_INT_STS_DONE_SFT 17
+#define TU1_TM_INT_STS_DONE_HI 17
+#define TU1_TM_INT_STS_DONE_SZ 1
+#define TU1_TM_INT_MASK_MSK 0x00040000
+#define TU1_TM_INT_MASK_I_MSK 0xfffbffff
+#define TU1_TM_INT_MASK_SFT 18
+#define TU1_TM_INT_MASK_HI 18
+#define TU1_TM_INT_MASK_SZ 1
+#define TU1_TM_CUR_VALUE_MSK 0x0000ffff
+#define TU1_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TU1_TM_CUR_VALUE_SFT 0
+#define TU1_TM_CUR_VALUE_HI 15
+#define TU1_TM_CUR_VALUE_SZ 16
+#define TU1_PRESCALER_USTIMER_LOCAL_MSK 0x000001ff
+#define TU1_PRESCALER_USTIMER_LOCAL_I_MSK 0xfffffe00
+#define TU1_PRESCALER_USTIMER_LOCAL_SFT 0
+#define TU1_PRESCALER_USTIMER_LOCAL_HI 8
+#define TU1_PRESCALER_USTIMER_LOCAL_SZ 9
+#define TU2_TM_INIT_VALUE_MSK 0x0000ffff
+#define TU2_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TU2_TM_INIT_VALUE_SFT 0
+#define TU2_TM_INIT_VALUE_HI 15
+#define TU2_TM_INIT_VALUE_SZ 16
+#define TU2_TM_MODE_MSK 0x00010000
+#define TU2_TM_MODE_I_MSK 0xfffeffff
+#define TU2_TM_MODE_SFT 16
+#define TU2_TM_MODE_HI 16
+#define TU2_TM_MODE_SZ 1
+#define TU2_TM_INT_STS_DONE_MSK 0x00020000
+#define TU2_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TU2_TM_INT_STS_DONE_SFT 17
+#define TU2_TM_INT_STS_DONE_HI 17
+#define TU2_TM_INT_STS_DONE_SZ 1
+#define TU2_TM_INT_MASK_MSK 0x00040000
+#define TU2_TM_INT_MASK_I_MSK 0xfffbffff
+#define TU2_TM_INT_MASK_SFT 18
+#define TU2_TM_INT_MASK_HI 18
+#define TU2_TM_INT_MASK_SZ 1
+#define TU2_TM_CUR_VALUE_MSK 0x0000ffff
+#define TU2_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TU2_TM_CUR_VALUE_SFT 0
+#define TU2_TM_CUR_VALUE_HI 15
+#define TU2_TM_CUR_VALUE_SZ 16
+#define TU2_PRESCALER_USTIMER_LOCAL_MSK 0x000001ff
+#define TU2_PRESCALER_USTIMER_LOCAL_I_MSK 0xfffffe00
+#define TU2_PRESCALER_USTIMER_LOCAL_SFT 0
+#define TU2_PRESCALER_USTIMER_LOCAL_HI 8
+#define TU2_PRESCALER_USTIMER_LOCAL_SZ 9
+#define TU3_TM_INIT_VALUE_MSK 0x0000ffff
+#define TU3_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TU3_TM_INIT_VALUE_SFT 0
+#define TU3_TM_INIT_VALUE_HI 15
+#define TU3_TM_INIT_VALUE_SZ 16
+#define TU3_TM_MODE_MSK 0x00010000
+#define TU3_TM_MODE_I_MSK 0xfffeffff
+#define TU3_TM_MODE_SFT 16
+#define TU3_TM_MODE_HI 16
+#define TU3_TM_MODE_SZ 1
+#define TU3_TM_INT_STS_DONE_MSK 0x00020000
+#define TU3_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TU3_TM_INT_STS_DONE_SFT 17
+#define TU3_TM_INT_STS_DONE_HI 17
+#define TU3_TM_INT_STS_DONE_SZ 1
+#define TU3_TM_INT_MASK_MSK 0x00040000
+#define TU3_TM_INT_MASK_I_MSK 0xfffbffff
+#define TU3_TM_INT_MASK_SFT 18
+#define TU3_TM_INT_MASK_HI 18
+#define TU3_TM_INT_MASK_SZ 1
+#define TU3_TM_CUR_VALUE_MSK 0x0000ffff
+#define TU3_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TU3_TM_CUR_VALUE_SFT 0
+#define TU3_TM_CUR_VALUE_HI 15
+#define TU3_TM_CUR_VALUE_SZ 16
+#define TU3_PRESCALER_USTIMER_LOCAL_MSK 0x000001ff
+#define TU3_PRESCALER_USTIMER_LOCAL_I_MSK 0xfffffe00
+#define TU3_PRESCALER_USTIMER_LOCAL_SFT 0
+#define TU3_PRESCALER_USTIMER_LOCAL_HI 8
+#define TU3_PRESCALER_USTIMER_LOCAL_SZ 9
+#define TM0_TM_INIT_VALUE_MSK 0x0000ffff
+#define TM0_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TM0_TM_INIT_VALUE_SFT 0
+#define TM0_TM_INIT_VALUE_HI 15
+#define TM0_TM_INIT_VALUE_SZ 16
+#define TM0_TM_MODE_MSK 0x00010000
+#define TM0_TM_MODE_I_MSK 0xfffeffff
+#define TM0_TM_MODE_SFT 16
+#define TM0_TM_MODE_HI 16
+#define TM0_TM_MODE_SZ 1
+#define TM0_TM_INT_STS_DONE_MSK 0x00020000
+#define TM0_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TM0_TM_INT_STS_DONE_SFT 17
+#define TM0_TM_INT_STS_DONE_HI 17
+#define TM0_TM_INT_STS_DONE_SZ 1
+#define TM0_TM_INT_MASK_MSK 0x00040000
+#define TM0_TM_INT_MASK_I_MSK 0xfffbffff
+#define TM0_TM_INT_MASK_SFT 18
+#define TM0_TM_INT_MASK_HI 18
+#define TM0_TM_INT_MASK_SZ 1
+#define TM0_TM_CUR_VALUE_MSK 0x0000ffff
+#define TM0_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TM0_TM_CUR_VALUE_SFT 0
+#define TM0_TM_CUR_VALUE_HI 15
+#define TM0_TM_CUR_VALUE_SZ 16
+#define TM0_PRESCALER_USTIMER_LOCAL_MSK 0x000001ff
+#define TM0_PRESCALER_USTIMER_LOCAL_I_MSK 0xfffffe00
+#define TM0_PRESCALER_USTIMER_LOCAL_SFT 0
+#define TM0_PRESCALER_USTIMER_LOCAL_HI 8
+#define TM0_PRESCALER_USTIMER_LOCAL_SZ 9
+#define TM1_TM_INIT_VALUE_MSK 0x0000ffff
+#define TM1_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TM1_TM_INIT_VALUE_SFT 0
+#define TM1_TM_INIT_VALUE_HI 15
+#define TM1_TM_INIT_VALUE_SZ 16
+#define TM1_TM_MODE_MSK 0x00010000
+#define TM1_TM_MODE_I_MSK 0xfffeffff
+#define TM1_TM_MODE_SFT 16
+#define TM1_TM_MODE_HI 16
+#define TM1_TM_MODE_SZ 1
+#define TM1_TM_INT_STS_DONE_MSK 0x00020000
+#define TM1_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TM1_TM_INT_STS_DONE_SFT 17
+#define TM1_TM_INT_STS_DONE_HI 17
+#define TM1_TM_INT_STS_DONE_SZ 1
+#define TM1_TM_INT_MASK_MSK 0x00040000
+#define TM1_TM_INT_MASK_I_MSK 0xfffbffff
+#define TM1_TM_INT_MASK_SFT 18
+#define TM1_TM_INT_MASK_HI 18
+#define TM1_TM_INT_MASK_SZ 1
+#define TM1_TM_CUR_VALUE_MSK 0x0000ffff
+#define TM1_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TM1_TM_CUR_VALUE_SFT 0
+#define TM1_TM_CUR_VALUE_HI 15
+#define TM1_TM_CUR_VALUE_SZ 16
+#define TM1_PRESCALER_USTIMER_LOCAL_MSK 0x000001ff
+#define TM1_PRESCALER_USTIMER_LOCAL_I_MSK 0xfffffe00
+#define TM1_PRESCALER_USTIMER_LOCAL_SFT 0
+#define TM1_PRESCALER_USTIMER_LOCAL_HI 8
+#define TM1_PRESCALER_USTIMER_LOCAL_SZ 9
+#define TM2_TM_INIT_VALUE_MSK 0x0000ffff
+#define TM2_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TM2_TM_INIT_VALUE_SFT 0
+#define TM2_TM_INIT_VALUE_HI 15
+#define TM2_TM_INIT_VALUE_SZ 16
+#define TM2_TM_MODE_MSK 0x00010000
+#define TM2_TM_MODE_I_MSK 0xfffeffff
+#define TM2_TM_MODE_SFT 16
+#define TM2_TM_MODE_HI 16
+#define TM2_TM_MODE_SZ 1
+#define TM2_TM_INT_STS_DONE_MSK 0x00020000
+#define TM2_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TM2_TM_INT_STS_DONE_SFT 17
+#define TM2_TM_INT_STS_DONE_HI 17
+#define TM2_TM_INT_STS_DONE_SZ 1
+#define TM2_TM_INT_MASK_MSK 0x00040000
+#define TM2_TM_INT_MASK_I_MSK 0xfffbffff
+#define TM2_TM_INT_MASK_SFT 18
+#define TM2_TM_INT_MASK_HI 18
+#define TM2_TM_INT_MASK_SZ 1
+#define TM2_TM_CUR_VALUE_MSK 0x0000ffff
+#define TM2_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TM2_TM_CUR_VALUE_SFT 0
+#define TM2_TM_CUR_VALUE_HI 15
+#define TM2_TM_CUR_VALUE_SZ 16
+#define TM2_PRESCALER_USTIMER_LOCAL_MSK 0x000001ff
+#define TM2_PRESCALER_USTIMER_LOCAL_I_MSK 0xfffffe00
+#define TM2_PRESCALER_USTIMER_LOCAL_SFT 0
+#define TM2_PRESCALER_USTIMER_LOCAL_HI 8
+#define TM2_PRESCALER_USTIMER_LOCAL_SZ 9
+#define TM3_TM_INIT_VALUE_MSK 0x0000ffff
+#define TM3_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TM3_TM_INIT_VALUE_SFT 0
+#define TM3_TM_INIT_VALUE_HI 15
+#define TM3_TM_INIT_VALUE_SZ 16
+#define TM3_TM_MODE_MSK 0x00010000
+#define TM3_TM_MODE_I_MSK 0xfffeffff
+#define TM3_TM_MODE_SFT 16
+#define TM3_TM_MODE_HI 16
+#define TM3_TM_MODE_SZ 1
+#define TM3_TM_INT_STS_DONE_MSK 0x00020000
+#define TM3_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TM3_TM_INT_STS_DONE_SFT 17
+#define TM3_TM_INT_STS_DONE_HI 17
+#define TM3_TM_INT_STS_DONE_SZ 1
+#define TM3_TM_INT_MASK_MSK 0x00040000
+#define TM3_TM_INT_MASK_I_MSK 0xfffbffff
+#define TM3_TM_INT_MASK_SFT 18
+#define TM3_TM_INT_MASK_HI 18
+#define TM3_TM_INT_MASK_SZ 1
+#define TM3_TM_CUR_VALUE_MSK 0x0000ffff
+#define TM3_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TM3_TM_CUR_VALUE_SFT 0
+#define TM3_TM_CUR_VALUE_HI 15
+#define TM3_TM_CUR_VALUE_SZ 16
+#define TM3_PRESCALER_USTIMER_LOCAL_MSK 0x000001ff
+#define TM3_PRESCALER_USTIMER_LOCAL_I_MSK 0xfffffe00
+#define TM3_PRESCALER_USTIMER_LOCAL_SFT 0
+#define TM3_PRESCALER_USTIMER_LOCAL_HI 8
+#define TM3_PRESCALER_USTIMER_LOCAL_SZ 9
+#define MCU_WDT_TIME_CNT_MSK 0x0000ffff
+#define MCU_WDT_TIME_CNT_I_MSK 0xffff0000
+#define MCU_WDT_TIME_CNT_SFT 0
+#define MCU_WDT_TIME_CNT_HI 15
+#define MCU_WDT_TIME_CNT_SZ 16
+#define MCU_WDT_INT_CNT_OFS_MSK 0x00ff0000
+#define MCU_WDT_INT_CNT_OFS_I_MSK 0xff00ffff
+#define MCU_WDT_INT_CNT_OFS_SFT 16
+#define MCU_WDT_INT_CNT_OFS_HI 23
+#define MCU_WDT_INT_CNT_OFS_SZ 8
+#define MCU_WDT_STATUS_MSK 0x40000000
+#define MCU_WDT_STATUS_I_MSK 0xbfffffff
+#define MCU_WDT_STATUS_SFT 30
+#define MCU_WDT_STATUS_HI 30
+#define MCU_WDT_STATUS_SZ 1
+#define MCU_WDOG_ENA_MSK 0x80000000
+#define MCU_WDOG_ENA_I_MSK 0x7fffffff
+#define MCU_WDOG_ENA_SFT 31
+#define MCU_WDOG_ENA_HI 31
+#define MCU_WDOG_ENA_SZ 1
+#define SYS_WDT_TIME_CNT_MSK 0x0000ffff
+#define SYS_WDT_TIME_CNT_I_MSK 0xffff0000
+#define SYS_WDT_TIME_CNT_SFT 0
+#define SYS_WDT_TIME_CNT_HI 15
+#define SYS_WDT_TIME_CNT_SZ 16
+#define SYS_WDT_INT_CNT_OFS_MSK 0x00ff0000
+#define SYS_WDT_INT_CNT_OFS_I_MSK 0xff00ffff
+#define SYS_WDT_INT_CNT_OFS_SFT 16
+#define SYS_WDT_INT_CNT_OFS_HI 23
+#define SYS_WDT_INT_CNT_OFS_SZ 8
+#define SYS_WDT_STATUS_MSK 0x40000000
+#define SYS_WDT_STATUS_I_MSK 0xbfffffff
+#define SYS_WDT_STATUS_SFT 30
+#define SYS_WDT_STATUS_HI 30
+#define SYS_WDT_STATUS_SZ 1
+#define SYS_WDOG_ENA_MSK 0x80000000
+#define SYS_WDOG_ENA_I_MSK 0x7fffffff
+#define SYS_WDOG_ENA_SFT 31
+#define SYS_WDOG_ENA_HI 31
+#define SYS_WDOG_ENA_SZ 1
+#define PWM_POST_SCALER_0_MSK 0x000000ff
+#define PWM_POST_SCALER_0_I_MSK 0xffffff00
+#define PWM_POST_SCALER_0_SFT 0
+#define PWM_POST_SCALER_0_HI 7
+#define PWM_POST_SCALER_0_SZ 8
+#define PWM_SETTING_UPDATE_0_MSK 0x10000000
+#define PWM_SETTING_UPDATE_0_I_MSK 0xefffffff
+#define PWM_SETTING_UPDATE_0_SFT 28
+#define PWM_SETTING_UPDATE_0_HI 28
+#define PWM_SETTING_UPDATE_0_SZ 1
+#define PWM_ALWAYSON_0_MSK 0x20000000
+#define PWM_ALWAYSON_0_I_MSK 0xdfffffff
+#define PWM_ALWAYSON_0_SFT 29
+#define PWM_ALWAYSON_0_HI 29
+#define PWM_ALWAYSON_0_SZ 1
+#define PWM_INVERT_0_MSK 0x40000000
+#define PWM_INVERT_0_I_MSK 0xbfffffff
+#define PWM_INVERT_0_SFT 30
+#define PWM_INVERT_0_HI 30
+#define PWM_INVERT_0_SZ 1
+#define PWM_ENABLE_0_MSK 0x80000000
+#define PWM_ENABLE_0_I_MSK 0x7fffffff
+#define PWM_ENABLE_0_SFT 31
+#define PWM_ENABLE_0_HI 31
+#define PWM_ENABLE_0_SZ 1
+#define PWM_INI_VALUE_PERIOD_0_MSK 0x0000ffff
+#define PWM_INI_VALUE_PERIOD_0_I_MSK 0xffff0000
+#define PWM_INI_VALUE_PERIOD_0_SFT 0
+#define PWM_INI_VALUE_PERIOD_0_HI 15
+#define PWM_INI_VALUE_PERIOD_0_SZ 16
+#define PWM_INI_VALUE_P_0_MSK 0xffff0000
+#define PWM_INI_VALUE_P_0_I_MSK 0x0000ffff
+#define PWM_INI_VALUE_P_0_SFT 16
+#define PWM_INI_VALUE_P_0_HI 31
+#define PWM_INI_VALUE_P_0_SZ 16
+#define PWM_POST_SCALER_1_MSK 0x000000ff
+#define PWM_POST_SCALER_1_I_MSK 0xffffff00
+#define PWM_POST_SCALER_1_SFT 0
+#define PWM_POST_SCALER_1_HI 7
+#define PWM_POST_SCALER_1_SZ 8
+#define PWM_SETTING_UPDATE_1_MSK 0x10000000
+#define PWM_SETTING_UPDATE_1_I_MSK 0xefffffff
+#define PWM_SETTING_UPDATE_1_SFT 28
+#define PWM_SETTING_UPDATE_1_HI 28
+#define PWM_SETTING_UPDATE_1_SZ 1
+#define PWM_ALWAYSON_1_MSK 0x20000000
+#define PWM_ALWAYSON_1_I_MSK 0xdfffffff
+#define PWM_ALWAYSON_1_SFT 29
+#define PWM_ALWAYSON_1_HI 29
+#define PWM_ALWAYSON_1_SZ 1
+#define PWM_INVERT_1_MSK 0x40000000
+#define PWM_INVERT_1_I_MSK 0xbfffffff
+#define PWM_INVERT_1_SFT 30
+#define PWM_INVERT_1_HI 30
+#define PWM_INVERT_1_SZ 1
+#define PWM_ENABLE_1_MSK 0x80000000
+#define PWM_ENABLE_1_I_MSK 0x7fffffff
+#define PWM_ENABLE_1_SFT 31
+#define PWM_ENABLE_1_HI 31
+#define PWM_ENABLE_1_SZ 1
+#define PWM_INI_VALUE_PERIOD_1_MSK 0x0000ffff
+#define PWM_INI_VALUE_PERIOD_1_I_MSK 0xffff0000
+#define PWM_INI_VALUE_PERIOD_1_SFT 0
+#define PWM_INI_VALUE_PERIOD_1_HI 15
+#define PWM_INI_VALUE_PERIOD_1_SZ 16
+#define PWM_INI_VALUE_P_1_MSK 0xffff0000
+#define PWM_INI_VALUE_P_1_I_MSK 0x0000ffff
+#define PWM_INI_VALUE_P_1_SFT 16
+#define PWM_INI_VALUE_P_1_HI 31
+#define PWM_INI_VALUE_P_1_SZ 16
+#define PWM_POST_SCALER_2_MSK 0x000000ff
+#define PWM_POST_SCALER_2_I_MSK 0xffffff00
+#define PWM_POST_SCALER_2_SFT 0
+#define PWM_POST_SCALER_2_HI 7
+#define PWM_POST_SCALER_2_SZ 8
+#define PWM_SETTING_UPDATE_2_MSK 0x10000000
+#define PWM_SETTING_UPDATE_2_I_MSK 0xefffffff
+#define PWM_SETTING_UPDATE_2_SFT 28
+#define PWM_SETTING_UPDATE_2_HI 28
+#define PWM_SETTING_UPDATE_2_SZ 1
+#define PWM_ALWAYSON_2_MSK 0x20000000
+#define PWM_ALWAYSON_2_I_MSK 0xdfffffff
+#define PWM_ALWAYSON_2_SFT 29
+#define PWM_ALWAYSON_2_HI 29
+#define PWM_ALWAYSON_2_SZ 1
+#define PWM_INVERT_2_MSK 0x40000000
+#define PWM_INVERT_2_I_MSK 0xbfffffff
+#define PWM_INVERT_2_SFT 30
+#define PWM_INVERT_2_HI 30
+#define PWM_INVERT_2_SZ 1
+#define PWM_ENABLE_2_MSK 0x80000000
+#define PWM_ENABLE_2_I_MSK 0x7fffffff
+#define PWM_ENABLE_2_SFT 31
+#define PWM_ENABLE_2_HI 31
+#define PWM_ENABLE_2_SZ 1
+#define PWM_INI_VALUE_PERIOD_2_MSK 0x0000ffff
+#define PWM_INI_VALUE_PERIOD_2_I_MSK 0xffff0000
+#define PWM_INI_VALUE_PERIOD_2_SFT 0
+#define PWM_INI_VALUE_PERIOD_2_HI 15
+#define PWM_INI_VALUE_PERIOD_2_SZ 16
+#define PWM_INI_VALUE_P_2_MSK 0xffff0000
+#define PWM_INI_VALUE_P_2_I_MSK 0x0000ffff
+#define PWM_INI_VALUE_P_2_SFT 16
+#define PWM_INI_VALUE_P_2_HI 31
+#define PWM_INI_VALUE_P_2_SZ 16
+#define PWM_POST_SCALER_3_MSK 0x000000ff
+#define PWM_POST_SCALER_3_I_MSK 0xffffff00
+#define PWM_POST_SCALER_3_SFT 0
+#define PWM_POST_SCALER_3_HI 7
+#define PWM_POST_SCALER_3_SZ 8
+#define PWM_SETTING_UPDATE_3_MSK 0x10000000
+#define PWM_SETTING_UPDATE_3_I_MSK 0xefffffff
+#define PWM_SETTING_UPDATE_3_SFT 28
+#define PWM_SETTING_UPDATE_3_HI 28
+#define PWM_SETTING_UPDATE_3_SZ 1
+#define PWM_ALWAYSON_3_MSK 0x20000000
+#define PWM_ALWAYSON_3_I_MSK 0xdfffffff
+#define PWM_ALWAYSON_3_SFT 29
+#define PWM_ALWAYSON_3_HI 29
+#define PWM_ALWAYSON_3_SZ 1
+#define PWM_INVERT_3_MSK 0x40000000
+#define PWM_INVERT_3_I_MSK 0xbfffffff
+#define PWM_INVERT_3_SFT 30
+#define PWM_INVERT_3_HI 30
+#define PWM_INVERT_3_SZ 1
+#define PWM_ENABLE_3_MSK 0x80000000
+#define PWM_ENABLE_3_I_MSK 0x7fffffff
+#define PWM_ENABLE_3_SFT 31
+#define PWM_ENABLE_3_HI 31
+#define PWM_ENABLE_3_SZ 1
+#define PWM_INI_VALUE_PERIOD_3_MSK 0x0000ffff
+#define PWM_INI_VALUE_PERIOD_3_I_MSK 0xffff0000
+#define PWM_INI_VALUE_PERIOD_3_SFT 0
+#define PWM_INI_VALUE_PERIOD_3_HI 15
+#define PWM_INI_VALUE_PERIOD_3_SZ 16
+#define PWM_INI_VALUE_P_3_MSK 0xffff0000
+#define PWM_INI_VALUE_P_3_I_MSK 0x0000ffff
+#define PWM_INI_VALUE_P_3_SFT 16
+#define PWM_INI_VALUE_P_3_HI 31
+#define PWM_INI_VALUE_P_3_SZ 16
+#define PWM_POST_SCALER_4_MSK 0x000000ff
+#define PWM_POST_SCALER_4_I_MSK 0xffffff00
+#define PWM_POST_SCALER_4_SFT 0
+#define PWM_POST_SCALER_4_HI 7
+#define PWM_POST_SCALER_4_SZ 8
+#define PWM_SETTING_UPDATE_4_MSK 0x10000000
+#define PWM_SETTING_UPDATE_4_I_MSK 0xefffffff
+#define PWM_SETTING_UPDATE_4_SFT 28
+#define PWM_SETTING_UPDATE_4_HI 28
+#define PWM_SETTING_UPDATE_4_SZ 1
+#define PWM_ALWAYSON_4_MSK 0x20000000
+#define PWM_ALWAYSON_4_I_MSK 0xdfffffff
+#define PWM_ALWAYSON_4_SFT 29
+#define PWM_ALWAYSON_4_HI 29
+#define PWM_ALWAYSON_4_SZ 1
+#define PWM_INVERT_4_MSK 0x40000000
+#define PWM_INVERT_4_I_MSK 0xbfffffff
+#define PWM_INVERT_4_SFT 30
+#define PWM_INVERT_4_HI 30
+#define PWM_INVERT_4_SZ 1
+#define PWM_ENABLE_4_MSK 0x80000000
+#define PWM_ENABLE_4_I_MSK 0x7fffffff
+#define PWM_ENABLE_4_SFT 31
+#define PWM_ENABLE_4_HI 31
+#define PWM_ENABLE_4_SZ 1
+#define PWM_INI_VALUE_PERIOD_4_MSK 0x0000ffff
+#define PWM_INI_VALUE_PERIOD_4_I_MSK 0xffff0000
+#define PWM_INI_VALUE_PERIOD_4_SFT 0
+#define PWM_INI_VALUE_PERIOD_4_HI 15
+#define PWM_INI_VALUE_PERIOD_4_SZ 16
+#define PWM_INI_VALUE_P_4_MSK 0xffff0000
+#define PWM_INI_VALUE_P_4_I_MSK 0x0000ffff
+#define PWM_INI_VALUE_P_4_SFT 16
+#define PWM_INI_VALUE_P_4_HI 31
+#define PWM_INI_VALUE_P_4_SZ 16
+#define MANUAL_IO_MSK 0x007fffff
+#define MANUAL_IO_I_MSK 0xff800000
+#define MANUAL_IO_SFT 0
+#define MANUAL_IO_HI 22
+#define MANUAL_IO_SZ 23
+#define MANUAL_PU_MSK 0x007fffff
+#define MANUAL_PU_I_MSK 0xff800000
+#define MANUAL_PU_SFT 0
+#define MANUAL_PU_HI 22
+#define MANUAL_PU_SZ 23
+#define MANUAL_PD_MSK 0x007fffff
+#define MANUAL_PD_I_MSK 0xff800000
+#define MANUAL_PD_SFT 0
+#define MANUAL_PD_HI 22
+#define MANUAL_PD_SZ 23
+#define MANUAL_DS_MSK 0x007fffff
+#define MANUAL_DS_I_MSK 0xff800000
+#define MANUAL_DS_SFT 0
+#define MANUAL_DS_HI 22
+#define MANUAL_DS_SZ 23
+#define IO_PO_MSK 0x007fffff
+#define IO_PO_I_MSK 0xff800000
+#define IO_PO_SFT 0
+#define IO_PO_HI 22
+#define IO_PO_SZ 23
+#define IO_PI_MSK 0x007fffff
+#define IO_PI_I_MSK 0xff800000
+#define IO_PI_SFT 0
+#define IO_PI_HI 22
+#define IO_PI_SZ 23
+#define IO_PIE_MSK 0x007fffff
+#define IO_PIE_I_MSK 0xff800000
+#define IO_PIE_SFT 0
+#define IO_PIE_HI 22
+#define IO_PIE_SZ 23
+#define IO_POEN_MSK 0x007fffff
+#define IO_POEN_I_MSK 0xff800000
+#define IO_POEN_SFT 0
+#define IO_POEN_HI 22
+#define IO_POEN_SZ 23
+#define IO_PUE_MSK 0x007fffff
+#define IO_PUE_I_MSK 0xff800000
+#define IO_PUE_SFT 0
+#define IO_PUE_HI 22
+#define IO_PUE_SZ 23
+#define IO_PDE_MSK 0x007fffff
+#define IO_PDE_I_MSK 0xff800000
+#define IO_PDE_SFT 0
+#define IO_PDE_HI 22
+#define IO_PDE_SZ 23
+#define IO_DS_MSK 0x007fffff
+#define IO_DS_I_MSK 0xff800000
+#define IO_DS_SFT 0
+#define IO_DS_HI 22
+#define IO_DS_SZ 23
+#define SEL_I2STRX_II_MSK 0x00000001
+#define SEL_I2STRX_II_I_MSK 0xfffffffe
+#define SEL_I2STRX_II_SFT 0
+#define SEL_I2STRX_II_HI 0
+#define SEL_I2STRX_II_SZ 1
+#define SEL_I2STRX_I_MSK 0x00000002
+#define SEL_I2STRX_I_I_MSK 0xfffffffd
+#define SEL_I2STRX_I_SFT 1
+#define SEL_I2STRX_I_HI 1
+#define SEL_I2STRX_I_SZ 1
+#define SEL_SPI_SLV_MSK 0x00000004
+#define SEL_SPI_SLV_I_MSK 0xfffffffb
+#define SEL_SPI_SLV_SFT 2
+#define SEL_SPI_SLV_HI 2
+#define SEL_SPI_SLV_SZ 1
+#define SEL_SPI_MST_MSK 0x00000008
+#define SEL_SPI_MST_I_MSK 0xfffffff7
+#define SEL_SPI_MST_SFT 3
+#define SEL_SPI_MST_HI 3
+#define SEL_SPI_MST_SZ 1
+#define SEL_I2C_SLV_MSK 0x00000010
+#define SEL_I2C_SLV_I_MSK 0xffffffef
+#define SEL_I2C_SLV_SFT 4
+#define SEL_I2C_SLV_HI 4
+#define SEL_I2C_SLV_SZ 1
+#define SEL_I2C_MST_II_MSK 0x00000020
+#define SEL_I2C_MST_II_I_MSK 0xffffffdf
+#define SEL_I2C_MST_II_SFT 5
+#define SEL_I2C_MST_II_HI 5
+#define SEL_I2C_MST_II_SZ 1
+#define SEL_I2C_MST_I_MSK 0x00000040
+#define SEL_I2C_MST_I_I_MSK 0xffffffbf
+#define SEL_I2C_MST_I_SFT 6
+#define SEL_I2C_MST_I_HI 6
+#define SEL_I2C_MST_I_SZ 1
+#define SEL_UART0_II_MSK 0x00000080
+#define SEL_UART0_II_I_MSK 0xffffff7f
+#define SEL_UART0_II_SFT 7
+#define SEL_UART0_II_HI 7
+#define SEL_UART0_II_SZ 1
+#define SEL_UART0_I_MSK 0x00000100
+#define SEL_UART0_I_I_MSK 0xfffffeff
+#define SEL_UART0_I_SFT 8
+#define SEL_UART0_I_HI 8
+#define SEL_UART0_I_SZ 1
+#define SEL_BTCX_MSK 0x00000200
+#define SEL_BTCX_I_MSK 0xfffffdff
+#define SEL_BTCX_SFT 9
+#define SEL_BTCX_HI 9
+#define SEL_BTCX_SZ 1
+#define SEL_FLASH_MSK 0x00000400
+#define SEL_FLASH_I_MSK 0xfffffbff
+#define SEL_FLASH_SFT 10
+#define SEL_FLASH_HI 10
+#define SEL_FLASH_SZ 1
+#define SEL_RF_MSK 0x00000800
+#define SEL_RF_I_MSK 0xfffff7ff
+#define SEL_RF_SFT 11
+#define SEL_RF_HI 11
+#define SEL_RF_SZ 1
+#define SEL_PWM_MSK 0x0001f000
+#define SEL_PWM_I_MSK 0xfffe0fff
+#define SEL_PWM_SFT 12
+#define SEL_PWM_HI 16
+#define SEL_PWM_SZ 5
+#define SEL_DEBUG_I_MSK 0x00020000
+#define SEL_DEBUG_I_I_MSK 0xfffdffff
+#define SEL_DEBUG_I_SFT 17
+#define SEL_DEBUG_I_HI 17
+#define SEL_DEBUG_I_SZ 1
+#define SEL_DEBUG_II_MSK 0x00040000
+#define SEL_DEBUG_II_I_MSK 0xfffbffff
+#define SEL_DEBUG_II_SFT 18
+#define SEL_DEBUG_II_HI 18
+#define SEL_DEBUG_II_SZ 1
+#define SEL_MEM_BIST_MSK 0x00080000
+#define SEL_MEM_BIST_I_MSK 0xfff7ffff
+#define SEL_MEM_BIST_SFT 19
+#define SEL_MEM_BIST_HI 19
+#define SEL_MEM_BIST_SZ 1
+#define SEL_USB_BIST_MSK 0x00100000
+#define SEL_USB_BIST_I_MSK 0xffefffff
+#define SEL_USB_BIST_SFT 20
+#define SEL_USB_BIST_HI 20
+#define SEL_USB_BIST_SZ 1
+#define SEL_USB_TEST_MSK 0x00200000
+#define SEL_USB_TEST_I_MSK 0xffdfffff
+#define SEL_USB_TEST_SFT 21
+#define SEL_USB_TEST_HI 21
+#define SEL_USB_TEST_SZ 1
+#define SEL_USB_IDDQ_MSK 0x00400000
+#define SEL_USB_IDDQ_I_MSK 0xffbfffff
+#define SEL_USB_IDDQ_SFT 22
+#define SEL_USB_IDDQ_HI 22
+#define SEL_USB_IDDQ_SZ 1
+#define I2S_RAW_DATA_MSK 0x40000000
+#define I2S_RAW_DATA_I_MSK 0xbfffffff
+#define I2S_RAW_DATA_SFT 30
+#define I2S_RAW_DATA_HI 30
+#define I2S_RAW_DATA_SZ 1
+#define SPI_RAW_DATA_MSK 0x80000000
+#define SPI_RAW_DATA_I_MSK 0x7fffffff
+#define SPI_RAW_DATA_SFT 31
+#define SPI_RAW_DATA_HI 31
+#define SPI_RAW_DATA_SZ 1
+#define SEL_GPO_INT_MSK 0x007fffff
+#define SEL_GPO_INT_I_MSK 0xff800000
+#define SEL_GPO_INT_SFT 0
+#define SEL_GPO_INT_HI 22
+#define SEL_GPO_INT_SZ 23
+#define ROM_START_INDEX_MSK 0x0000000f
+#define ROM_START_INDEX_I_MSK 0xfffffff0
+#define ROM_START_INDEX_SFT 0
+#define ROM_START_INDEX_HI 3
+#define ROM_START_INDEX_SZ 4
+#define ROM_END_INDEX_MSK 0x000000f0
+#define ROM_END_INDEX_I_MSK 0xffffff0f
+#define ROM_END_INDEX_SFT 4
+#define ROM_END_INDEX_HI 7
+#define ROM_END_INDEX_SZ 4
+#define ROMCRC32_GOLDEN_MSK 0xffffffff
+#define ROMCRC32_GOLDEN_I_MSK 0x00000000
+#define ROMCRC32_GOLDEN_SFT 0
+#define ROMCRC32_GOLDEN_HI 31
+#define ROMCRC32_GOLDEN_SZ 32
+#define ROMCRC32_RESULT_MSK 0xffffffff
+#define ROMCRC32_RESULT_I_MSK 0x00000000
+#define ROMCRC32_RESULT_SFT 0
+#define ROMCRC32_RESULT_HI 31
+#define ROMCRC32_RESULT_SZ 32
+#define I2CS_ADDR_DC_MSK 0x00000001
+#define I2CS_ADDR_DC_I_MSK 0xfffffffe
+#define I2CS_ADDR_DC_SFT 0
+#define I2CS_ADDR_DC_HI 0
+#define I2CS_ADDR_DC_SZ 1
+#define I2CS_ADDR_MSK 0x000000fe
+#define I2CS_ADDR_I_MSK 0xffffff01
+#define I2CS_ADDR_SFT 1
+#define I2CS_ADDR_HI 7
+#define I2CS_ADDR_SZ 7
+#define I2CS_INT_MSK 0x0000001f
+#define I2CS_INT_I_MSK 0xffffffe0
+#define I2CS_INT_SFT 0
+#define I2CS_INT_HI 4
+#define I2CS_INT_SZ 5
+#define I2CS_IDLE_MSK 0x00000400
+#define I2CS_IDLE_I_MSK 0xfffffbff
+#define I2CS_IDLE_SFT 10
+#define I2CS_IDLE_HI 10
+#define I2CS_IDLE_SZ 1
+#define I2CS_TIME_OUT_CNT_MSK 0x0000ffff
+#define I2CS_TIME_OUT_CNT_I_MSK 0xffff0000
+#define I2CS_TIME_OUT_CNT_SFT 0
+#define I2CS_TIME_OUT_CNT_HI 15
+#define I2CS_TIME_OUT_CNT_SZ 16
+#define I2CS_STATE_MSK 0x000000ff
+#define I2CS_STATE_I_MSK 0xffffff00
+#define I2CS_STATE_SFT 0
+#define I2CS_STATE_HI 7
+#define I2CS_STATE_SZ 8
+#define I2CS_DATA_CONFIG_MSK 0x00000001
+#define I2CS_DATA_CONFIG_I_MSK 0xfffffffe
+#define I2CS_DATA_CONFIG_SFT 0
+#define I2CS_DATA_CONFIG_HI 0
+#define I2CS_DATA_CONFIG_SZ 1
+#define I2CS_HOLD_BUS_EN_MSK 0x00000002
+#define I2CS_HOLD_BUS_EN_I_MSK 0xfffffffd
+#define I2CS_HOLD_BUS_EN_SFT 1
+#define I2CS_HOLD_BUS_EN_HI 1
+#define I2CS_HOLD_BUS_EN_SZ 1
+#define IO_PORT_REG_MSK 0x0001ffff
+#define IO_PORT_REG_I_MSK 0xfffe0000
+#define IO_PORT_REG_SFT 0
+#define IO_PORT_REG_HI 16
+#define IO_PORT_REG_SZ 17
+#define MASK_RX_INT_MSK 0x00000001
+#define MASK_RX_INT_I_MSK 0xfffffffe
+#define MASK_RX_INT_SFT 0
+#define MASK_RX_INT_HI 0
+#define MASK_RX_INT_SZ 1
+#define EDCA4_LOW_THR_INT_MASK_MSK 0x00000002
+#define EDCA4_LOW_THR_INT_MASK_I_MSK 0xfffffffd
+#define EDCA4_LOW_THR_INT_MASK_SFT 1
+#define EDCA4_LOW_THR_INT_MASK_HI 1
+#define EDCA4_LOW_THR_INT_MASK_SZ 1
+#define MASK_SOC_SYSTEM_INT_MSK 0x00000004
+#define MASK_SOC_SYSTEM_INT_I_MSK 0xfffffffb
+#define MASK_SOC_SYSTEM_INT_SFT 2
+#define MASK_SOC_SYSTEM_INT_HI 2
+#define MASK_SOC_SYSTEM_INT_SZ 1
+#define EDCA0_LOW_THR_INT_MASK_MSK 0x00000008
+#define EDCA0_LOW_THR_INT_MASK_I_MSK 0xfffffff7
+#define EDCA0_LOW_THR_INT_MASK_SFT 3
+#define EDCA0_LOW_THR_INT_MASK_HI 3
+#define EDCA0_LOW_THR_INT_MASK_SZ 1
+#define EDCA1_LOW_THR_INT_MASK_MSK 0x00000010
+#define EDCA1_LOW_THR_INT_MASK_I_MSK 0xffffffef
+#define EDCA1_LOW_THR_INT_MASK_SFT 4
+#define EDCA1_LOW_THR_INT_MASK_HI 4
+#define EDCA1_LOW_THR_INT_MASK_SZ 1
+#define EDCA2_LOW_THR_INT_MASK_MSK 0x00000020
+#define EDCA2_LOW_THR_INT_MASK_I_MSK 0xffffffdf
+#define EDCA2_LOW_THR_INT_MASK_SFT 5
+#define EDCA2_LOW_THR_INT_MASK_HI 5
+#define EDCA2_LOW_THR_INT_MASK_SZ 1
+#define EDCA3_LOW_THR_INT_MASK_MSK 0x00000040
+#define EDCA3_LOW_THR_INT_MASK_I_MSK 0xffffffbf
+#define EDCA3_LOW_THR_INT_MASK_SFT 6
+#define EDCA3_LOW_THR_INT_MASK_HI 6
+#define EDCA3_LOW_THR_INT_MASK_SZ 1
+#define TX_LIMIT_INT_MASK_MSK 0x00000080
+#define TX_LIMIT_INT_MASK_I_MSK 0xffffff7f
+#define TX_LIMIT_INT_MASK_SFT 7
+#define TX_LIMIT_INT_MASK_HI 7
+#define TX_LIMIT_INT_MASK_SZ 1
+#define RX_INT_MSK 0x00000001
+#define RX_INT_I_MSK 0xfffffffe
+#define RX_INT_SFT 0
+#define RX_INT_HI 0
+#define RX_INT_SZ 1
+#define EDCA4_LOW_THR_INT_STS_MSK 0x00000002
+#define EDCA4_LOW_THR_INT_STS_I_MSK 0xfffffffd
+#define EDCA4_LOW_THR_INT_STS_SFT 1
+#define EDCA4_LOW_THR_INT_STS_HI 1
+#define EDCA4_LOW_THR_INT_STS_SZ 1
+#define SOC_SYSTEM_INT_STATUS_MSK 0x00000004
+#define SOC_SYSTEM_INT_STATUS_I_MSK 0xfffffffb
+#define SOC_SYSTEM_INT_STATUS_SFT 2
+#define SOC_SYSTEM_INT_STATUS_HI 2
+#define SOC_SYSTEM_INT_STATUS_SZ 1
+#define EDCA0_LOW_THR_INT_STS_MSK 0x00000008
+#define EDCA0_LOW_THR_INT_STS_I_MSK 0xfffffff7
+#define EDCA0_LOW_THR_INT_STS_SFT 3
+#define EDCA0_LOW_THR_INT_STS_HI 3
+#define EDCA0_LOW_THR_INT_STS_SZ 1
+#define EDCA1_LOW_THR_INT_STS_MSK 0x00000010
+#define EDCA1_LOW_THR_INT_STS_I_MSK 0xffffffef
+#define EDCA1_LOW_THR_INT_STS_SFT 4
+#define EDCA1_LOW_THR_INT_STS_HI 4
+#define EDCA1_LOW_THR_INT_STS_SZ 1
+#define EDCA2_LOW_THR_INT_STS_MSK 0x00000020
+#define EDCA2_LOW_THR_INT_STS_I_MSK 0xffffffdf
+#define EDCA2_LOW_THR_INT_STS_SFT 5
+#define EDCA2_LOW_THR_INT_STS_HI 5
+#define EDCA2_LOW_THR_INT_STS_SZ 1
+#define EDCA3_LOW_THR_INT_STS_MSK 0x00000040
+#define EDCA3_LOW_THR_INT_STS_I_MSK 0xffffffbf
+#define EDCA3_LOW_THR_INT_STS_SFT 6
+#define EDCA3_LOW_THR_INT_STS_HI 6
+#define EDCA3_LOW_THR_INT_STS_SZ 1
+#define TX_LIMIT_INT_STS_MSK 0x00000080
+#define TX_LIMIT_INT_STS_I_MSK 0xffffff7f
+#define TX_LIMIT_INT_STS_SFT 7
+#define TX_LIMIT_INT_STS_HI 7
+#define TX_LIMIT_INT_STS_SZ 1
+#define HOST_TRIGGERED_RX_INT_MSK 0x00000100
+#define HOST_TRIGGERED_RX_INT_I_MSK 0xfffffeff
+#define HOST_TRIGGERED_RX_INT_SFT 8
+#define HOST_TRIGGERED_RX_INT_HI 8
+#define HOST_TRIGGERED_RX_INT_SZ 1
+#define HOST_TRIGGERED_TX_INT_MSK 0x00000200
+#define HOST_TRIGGERED_TX_INT_I_MSK 0xfffffdff
+#define HOST_TRIGGERED_TX_INT_SFT 9
+#define HOST_TRIGGERED_TX_INT_HI 9
+#define HOST_TRIGGERED_TX_INT_SZ 1
+#define SOC_TRIGGER_RX_INT_MSK 0x00000400
+#define SOC_TRIGGER_RX_INT_I_MSK 0xfffffbff
+#define SOC_TRIGGER_RX_INT_SFT 10
+#define SOC_TRIGGER_RX_INT_HI 10
+#define SOC_TRIGGER_RX_INT_SZ 1
+#define SOC_TRIGGER_TX_INT_MSK 0x00000800
+#define SOC_TRIGGER_TX_INT_I_MSK 0xfffff7ff
+#define SOC_TRIGGER_TX_INT_SFT 11
+#define SOC_TRIGGER_TX_INT_HI 11
+#define SOC_TRIGGER_TX_INT_SZ 1
+#define RDY_FOR_TX_RX_MSK 0x00000001
+#define RDY_FOR_TX_RX_I_MSK 0xfffffffe
+#define RDY_FOR_TX_RX_SFT 0
+#define RDY_FOR_TX_RX_HI 0
+#define RDY_FOR_TX_RX_SZ 1
+#define RDY_FOR_FW_DOWNLOAD_MSK 0x00000002
+#define RDY_FOR_FW_DOWNLOAD_I_MSK 0xfffffffd
+#define RDY_FOR_FW_DOWNLOAD_SFT 1
+#define RDY_FOR_FW_DOWNLOAD_HI 1
+#define RDY_FOR_FW_DOWNLOAD_SZ 1
+#define ILLEGAL_CMD_RESP_OPTION_MSK 0x00000004
+#define ILLEGAL_CMD_RESP_OPTION_I_MSK 0xfffffffb
+#define ILLEGAL_CMD_RESP_OPTION_SFT 2
+#define ILLEGAL_CMD_RESP_OPTION_HI 2
+#define ILLEGAL_CMD_RESP_OPTION_SZ 1
+#define SDIO_TRX_DATA_SEQUENCE_MSK 0x00000008
+#define SDIO_TRX_DATA_SEQUENCE_I_MSK 0xfffffff7
+#define SDIO_TRX_DATA_SEQUENCE_SFT 3
+#define SDIO_TRX_DATA_SEQUENCE_HI 3
+#define SDIO_TRX_DATA_SEQUENCE_SZ 1
+#define GPIO_INT_TRIGGER_OPTION_MSK 0x00000010
+#define GPIO_INT_TRIGGER_OPTION_I_MSK 0xffffffef
+#define GPIO_INT_TRIGGER_OPTION_SFT 4
+#define GPIO_INT_TRIGGER_OPTION_HI 4
+#define GPIO_INT_TRIGGER_OPTION_SZ 1
+#define TRIGGER_FUNCTION_SETTING_MSK 0x00000060
+#define TRIGGER_FUNCTION_SETTING_I_MSK 0xffffff9f
+#define TRIGGER_FUNCTION_SETTING_SFT 5
+#define TRIGGER_FUNCTION_SETTING_HI 6
+#define TRIGGER_FUNCTION_SETTING_SZ 2
+#define CMD52_ABORT_RESPONSE_MSK 0x00000080
+#define CMD52_ABORT_RESPONSE_I_MSK 0xffffff7f
+#define CMD52_ABORT_RESPONSE_SFT 7
+#define CMD52_ABORT_RESPONSE_HI 7
+#define CMD52_ABORT_RESPONSE_SZ 1
+#define CARD_RCA_REG_MSK 0x0000ffff
+#define CARD_RCA_REG_I_MSK 0xffff0000
+#define CARD_RCA_REG_SFT 0
+#define CARD_RCA_REG_HI 15
+#define CARD_RCA_REG_SZ 16
+#define SDIO_BYTE_MODE_BATCH_SIZE_REG_MSK 0x000000ff
+#define SDIO_BYTE_MODE_BATCH_SIZE_REG_I_MSK 0xffffff00
+#define SDIO_BYTE_MODE_BATCH_SIZE_REG_SFT 0
+#define SDIO_BYTE_MODE_BATCH_SIZE_REG_HI 7
+#define SDIO_BYTE_MODE_BATCH_SIZE_REG_SZ 8
+#define SDIO_CARD_STATUS_REG_MSK 0xffffffff
+#define SDIO_CARD_STATUS_REG_I_MSK 0x00000000
+#define SDIO_CARD_STATUS_REG_SFT 0
+#define SDIO_CARD_STATUS_REG_HI 31
+#define SDIO_CARD_STATUS_REG_SZ 32
+#define R5_RESPONSE_FLAG_MSK 0x000000ff
+#define R5_RESPONSE_FLAG_I_MSK 0xffffff00
+#define R5_RESPONSE_FLAG_SFT 0
+#define R5_RESPONSE_FLAG_HI 7
+#define R5_RESPONSE_FLAG_SZ 8
+#define MCU_TO_SDIO_INFO_MASK_MSK 0x00010000
+#define MCU_TO_SDIO_INFO_MASK_I_MSK 0xfffeffff
+#define MCU_TO_SDIO_INFO_MASK_SFT 16
+#define MCU_TO_SDIO_INFO_MASK_HI 16
+#define MCU_TO_SDIO_INFO_MASK_SZ 1
+#define INT_THROUGH_PIN_MSK 0x00020000
+#define INT_THROUGH_PIN_I_MSK 0xfffdffff
+#define INT_THROUGH_PIN_SFT 17
+#define INT_THROUGH_PIN_HI 17
+#define INT_THROUGH_PIN_SZ 1
+#define DIRECT_INT_MUX_MODE_MSK 0x00040000
+#define DIRECT_INT_MUX_MODE_I_MSK 0xfffbffff
+#define DIRECT_INT_MUX_MODE_SFT 18
+#define DIRECT_INT_MUX_MODE_HI 18
+#define DIRECT_INT_MUX_MODE_SZ 1
+#define SD_CMD_IN_DLY_SEL_MSK 0x00000007
+#define SD_CMD_IN_DLY_SEL_I_MSK 0xfffffff8
+#define SD_CMD_IN_DLY_SEL_SFT 0
+#define SD_CMD_IN_DLY_SEL_HI 2
+#define SD_CMD_IN_DLY_SEL_SZ 3
+#define SD_CMD_OUT_DLY_SEL_MSK 0x00000070
+#define SD_CMD_OUT_DLY_SEL_I_MSK 0xffffff8f
+#define SD_CMD_OUT_DLY_SEL_SFT 4
+#define SD_CMD_OUT_DLY_SEL_HI 6
+#define SD_CMD_OUT_DLY_SEL_SZ 3
+#define SD_DAT_3_IN_DLY_SEL_MSK 0x00000700
+#define SD_DAT_3_IN_DLY_SEL_I_MSK 0xfffff8ff
+#define SD_DAT_3_IN_DLY_SEL_SFT 8
+#define SD_DAT_3_IN_DLY_SEL_HI 10
+#define SD_DAT_3_IN_DLY_SEL_SZ 3
+#define SD_DAT_3_OUT_DLY_SEL_MSK 0x00007000
+#define SD_DAT_3_OUT_DLY_SEL_I_MSK 0xffff8fff
+#define SD_DAT_3_OUT_DLY_SEL_SFT 12
+#define SD_DAT_3_OUT_DLY_SEL_HI 14
+#define SD_DAT_3_OUT_DLY_SEL_SZ 3
+#define SD_DAT_2_IN_DLY_SEL_MSK 0x00070000
+#define SD_DAT_2_IN_DLY_SEL_I_MSK 0xfff8ffff
+#define SD_DAT_2_IN_DLY_SEL_SFT 16
+#define SD_DAT_2_IN_DLY_SEL_HI 18
+#define SD_DAT_2_IN_DLY_SEL_SZ 3
+#define SD_DAT_2_OUT_DLY_SEL_MSK 0x00700000
+#define SD_DAT_2_OUT_DLY_SEL_I_MSK 0xff8fffff
+#define SD_DAT_2_OUT_DLY_SEL_SFT 20
+#define SD_DAT_2_OUT_DLY_SEL_HI 22
+#define SD_DAT_2_OUT_DLY_SEL_SZ 3
+#define SD_DAT_1_IN_DLY_SEL_MSK 0x07000000
+#define SD_DAT_1_IN_DLY_SEL_I_MSK 0xf8ffffff
+#define SD_DAT_1_IN_DLY_SEL_SFT 24
+#define SD_DAT_1_IN_DLY_SEL_HI 26
+#define SD_DAT_1_IN_DLY_SEL_SZ 3
+#define SD_DAT_1_OUT_DLY_SEL_MSK 0x70000000
+#define SD_DAT_1_OUT_DLY_SEL_I_MSK 0x8fffffff
+#define SD_DAT_1_OUT_DLY_SEL_SFT 28
+#define SD_DAT_1_OUT_DLY_SEL_HI 30
+#define SD_DAT_1_OUT_DLY_SEL_SZ 3
+#define SD_DAT_0_IN_DLY_SEL_MSK 0x00000007
+#define SD_DAT_0_IN_DLY_SEL_I_MSK 0xfffffff8
+#define SD_DAT_0_IN_DLY_SEL_SFT 0
+#define SD_DAT_0_IN_DLY_SEL_HI 2
+#define SD_DAT_0_IN_DLY_SEL_SZ 3
+#define SD_DAT_0_OUT_DLY_SEL_MSK 0x00000070
+#define SD_DAT_0_OUT_DLY_SEL_I_MSK 0xffffff8f
+#define SD_DAT_0_OUT_DLY_SEL_SFT 4
+#define SD_DAT_0_OUT_DLY_SEL_HI 6
+#define SD_DAT_0_OUT_DLY_SEL_SZ 3
+#define FN1_DMA_START_ADDR_REG_MSK 0xffffffff
+#define FN1_DMA_START_ADDR_REG_I_MSK 0x00000000
+#define FN1_DMA_START_ADDR_REG_SFT 0
+#define FN1_DMA_START_ADDR_REG_HI 31
+#define FN1_DMA_START_ADDR_REG_SZ 32
+#define SDIO_TO_MCU_INFO_MSK 0x000000ff
+#define SDIO_TO_MCU_INFO_I_MSK 0xffffff00
+#define SDIO_TO_MCU_INFO_SFT 0
+#define SDIO_TO_MCU_INFO_HI 7
+#define SDIO_TO_MCU_INFO_SZ 8
+#define SDIO_PARTIAL_RESET_MSK 0x00000100
+#define SDIO_PARTIAL_RESET_I_MSK 0xfffffeff
+#define SDIO_PARTIAL_RESET_SFT 8
+#define SDIO_PARTIAL_RESET_HI 8
+#define SDIO_PARTIAL_RESET_SZ 1
+#define SDIO_ALL_RESET_MSK 0x00000200
+#define SDIO_ALL_RESET_I_MSK 0xfffffdff
+#define SDIO_ALL_RESET_SFT 9
+#define SDIO_ALL_RESET_HI 9
+#define SDIO_ALL_RESET_SZ 1
+#define PERI_MAC_ALL_RESET_MSK 0x00000400
+#define PERI_MAC_ALL_RESET_I_MSK 0xfffffbff
+#define PERI_MAC_ALL_RESET_SFT 10
+#define PERI_MAC_ALL_RESET_HI 10
+#define PERI_MAC_ALL_RESET_SZ 1
+#define MAC_ALL_RESET_MSK 0x00000800
+#define MAC_ALL_RESET_I_MSK 0xfffff7ff
+#define MAC_ALL_RESET_SFT 11
+#define MAC_ALL_RESET_HI 11
+#define MAC_ALL_RESET_SZ 1
+#define AHB_BRIDGE_RESET_MSK 0x00001000
+#define AHB_BRIDGE_RESET_I_MSK 0xffffefff
+#define AHB_BRIDGE_RESET_SFT 12
+#define AHB_BRIDGE_RESET_HI 12
+#define AHB_BRIDGE_RESET_SZ 1
+#define MCU_TO_SDIO_INFO_MSK 0x000000ff
+#define MCU_TO_SDIO_INFO_I_MSK 0xffffff00
+#define MCU_TO_SDIO_INFO_SFT 0
+#define MCU_TO_SDIO_INFO_HI 7
+#define MCU_TO_SDIO_INFO_SZ 8
+#define FN1_DMA_RD_START_ADDR_REG_MSK 0xffffffff
+#define FN1_DMA_RD_START_ADDR_REG_I_MSK 0x00000000
+#define FN1_DMA_RD_START_ADDR_REG_SFT 0
+#define FN1_DMA_RD_START_ADDR_REG_HI 31
+#define FN1_DMA_RD_START_ADDR_REG_SZ 32
+#define CCCR_00H_REG_MSK 0x000000ff
+#define CCCR_00H_REG_I_MSK 0xffffff00
+#define CCCR_00H_REG_SFT 0
+#define CCCR_00H_REG_HI 7
+#define CCCR_00H_REG_SZ 8
+#define CCCR_02H_REG_MSK 0x00ff0000
+#define CCCR_02H_REG_I_MSK 0xff00ffff
+#define CCCR_02H_REG_SFT 16
+#define CCCR_02H_REG_HI 23
+#define CCCR_02H_REG_SZ 8
+#define CCCR_03H_REG_MSK 0xff000000
+#define CCCR_03H_REG_I_MSK 0x00ffffff
+#define CCCR_03H_REG_SFT 24
+#define CCCR_03H_REG_HI 31
+#define CCCR_03H_REG_SZ 8
+#define CCCR_04H_REG_MSK 0x000000ff
+#define CCCR_04H_REG_I_MSK 0xffffff00
+#define CCCR_04H_REG_SFT 0
+#define CCCR_04H_REG_HI 7
+#define CCCR_04H_REG_SZ 8
+#define CCCR_05H_REG_MSK 0x0000ff00
+#define CCCR_05H_REG_I_MSK 0xffff00ff
+#define CCCR_05H_REG_SFT 8
+#define CCCR_05H_REG_HI 15
+#define CCCR_05H_REG_SZ 8
+#define CCCR_06H_REG_MSK 0x000f0000
+#define CCCR_06H_REG_I_MSK 0xfff0ffff
+#define CCCR_06H_REG_SFT 16
+#define CCCR_06H_REG_HI 19
+#define CCCR_06H_REG_SZ 4
+#define CCCR_07H_REG_MSK 0xff000000
+#define CCCR_07H_REG_I_MSK 0x00ffffff
+#define CCCR_07H_REG_SFT 24
+#define CCCR_07H_REG_HI 31
+#define CCCR_07H_REG_SZ 8
+#define SUPPORT_DIRECT_COMMAND_SDIO_MSK 0x00000001
+#define SUPPORT_DIRECT_COMMAND_SDIO_I_MSK 0xfffffffe
+#define SUPPORT_DIRECT_COMMAND_SDIO_SFT 0
+#define SUPPORT_DIRECT_COMMAND_SDIO_HI 0
+#define SUPPORT_DIRECT_COMMAND_SDIO_SZ 1
+#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_MSK 0x00000002
+#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_I_MSK 0xfffffffd
+#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_SFT 1
+#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_HI 1
+#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_SZ 1
+#define SUPPORT_READ_WAIT_MSK 0x00000004
+#define SUPPORT_READ_WAIT_I_MSK 0xfffffffb
+#define SUPPORT_READ_WAIT_SFT 2
+#define SUPPORT_READ_WAIT_HI 2
+#define SUPPORT_READ_WAIT_SZ 1
+#define SUPPORT_BUS_CONTROL_MSK 0x00000008
+#define SUPPORT_BUS_CONTROL_I_MSK 0xfffffff7
+#define SUPPORT_BUS_CONTROL_SFT 3
+#define SUPPORT_BUS_CONTROL_HI 3
+#define SUPPORT_BUS_CONTROL_SZ 1
+#define SUPPORT_BLOCK_GAP_INTERRUPT_MSK 0x00000010
+#define SUPPORT_BLOCK_GAP_INTERRUPT_I_MSK 0xffffffef
+#define SUPPORT_BLOCK_GAP_INTERRUPT_SFT 4
+#define SUPPORT_BLOCK_GAP_INTERRUPT_HI 4
+#define SUPPORT_BLOCK_GAP_INTERRUPT_SZ 1
+#define ENABLE_BLOCK_GAP_INTERRUPT_MSK 0x00000020
+#define ENABLE_BLOCK_GAP_INTERRUPT_I_MSK 0xffffffdf
+#define ENABLE_BLOCK_GAP_INTERRUPT_SFT 5
+#define ENABLE_BLOCK_GAP_INTERRUPT_HI 5
+#define ENABLE_BLOCK_GAP_INTERRUPT_SZ 1
+#define LOW_SPEED_CARD_MSK 0x00000040
+#define LOW_SPEED_CARD_I_MSK 0xffffffbf
+#define LOW_SPEED_CARD_SFT 6
+#define LOW_SPEED_CARD_HI 6
+#define LOW_SPEED_CARD_SZ 1
+#define LOW_SPEED_CARD_4BIT_MSK 0x00000080
+#define LOW_SPEED_CARD_4BIT_I_MSK 0xffffff7f
+#define LOW_SPEED_CARD_4BIT_SFT 7
+#define LOW_SPEED_CARD_4BIT_HI 7
+#define LOW_SPEED_CARD_4BIT_SZ 1
+#define COMMON_CIS_PONTER_MSK 0x01ffff00
+#define COMMON_CIS_PONTER_I_MSK 0xfe0000ff
+#define COMMON_CIS_PONTER_SFT 8
+#define COMMON_CIS_PONTER_HI 24
+#define COMMON_CIS_PONTER_SZ 17
+#define SD_SSDR50_MSK 0x01000000
+#define SD_SSDR50_I_MSK 0xfeffffff
+#define SD_SSDR50_SFT 24
+#define SD_SSDR50_HI 24
+#define SD_SSDR50_SZ 1
+#define SD_SSDR104_MSK 0x02000000
+#define SD_SSDR104_I_MSK 0xfdffffff
+#define SD_SSDR104_SFT 25
+#define SD_SSDR104_HI 25
+#define SD_SSDR104_SZ 1
+#define SUPPORT_HIGH_SPEED_MSK 0x01000000
+#define SUPPORT_HIGH_SPEED_I_MSK 0xfeffffff
+#define SUPPORT_HIGH_SPEED_SFT 24
+#define SUPPORT_HIGH_SPEED_HI 24
+#define SUPPORT_HIGH_SPEED_SZ 1
+#define BSS_MSK 0x0e000000
+#define BSS_I_MSK 0xf1ffffff
+#define BSS_SFT 25
+#define BSS_HI 27
+#define BSS_SZ 3
+#define FBR_100H_REG_MSK 0x0000000f
+#define FBR_100H_REG_I_MSK 0xfffffff0
+#define FBR_100H_REG_SFT 0
+#define FBR_100H_REG_HI 3
+#define FBR_100H_REG_SZ 4
+#define CSASUPPORT_MSK 0x00000040
+#define CSASUPPORT_I_MSK 0xffffffbf
+#define CSASUPPORT_SFT 6
+#define CSASUPPORT_HI 6
+#define CSASUPPORT_SZ 1
+#define ENABLECSA_MSK 0x00000080
+#define ENABLECSA_I_MSK 0xffffff7f
+#define ENABLECSA_SFT 7
+#define ENABLECSA_HI 7
+#define ENABLECSA_SZ 1
+#define FBR_101H_REG_MSK 0x0000ff00
+#define FBR_101H_REG_I_MSK 0xffff00ff
+#define FBR_101H_REG_SFT 8
+#define FBR_101H_REG_HI 15
+#define FBR_101H_REG_SZ 8
+#define FBR_109H_REG_MSK 0x01ffff00
+#define FBR_109H_REG_I_MSK 0xfe0000ff
+#define FBR_109H_REG_SFT 8
+#define FBR_109H_REG_HI 24
+#define FBR_109H_REG_SZ 17
+#define F0_CIS_CONTENT_REG_31_0_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_31_0_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_31_0_SFT 0
+#define F0_CIS_CONTENT_REG_31_0_HI 31
+#define F0_CIS_CONTENT_REG_31_0_SZ 32
+#define F0_CIS_CONTENT_REG_63_32_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_63_32_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_63_32_SFT 0
+#define F0_CIS_CONTENT_REG_63_32_HI 31
+#define F0_CIS_CONTENT_REG_63_32_SZ 32
+#define F0_CIS_CONTENT_REG_95_64_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_95_64_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_95_64_SFT 0
+#define F0_CIS_CONTENT_REG_95_64_HI 31
+#define F0_CIS_CONTENT_REG_95_64_SZ 32
+#define F0_CIS_CONTENT_REG_127_96_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_127_96_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_127_96_SFT 0
+#define F0_CIS_CONTENT_REG_127_96_HI 31
+#define F0_CIS_CONTENT_REG_127_96_SZ 32
+#define F0_CIS_CONTENT_REG_159_128_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_159_128_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_159_128_SFT 0
+#define F0_CIS_CONTENT_REG_159_128_HI 31
+#define F0_CIS_CONTENT_REG_159_128_SZ 32
+#define F0_CIS_CONTENT_REG_191_160_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_191_160_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_191_160_SFT 0
+#define F0_CIS_CONTENT_REG_191_160_HI 31
+#define F0_CIS_CONTENT_REG_191_160_SZ 32
+#define F0_CIS_CONTENT_REG_223_192_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_223_192_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_223_192_SFT 0
+#define F0_CIS_CONTENT_REG_223_192_HI 31
+#define F0_CIS_CONTENT_REG_223_192_SZ 32
+#define F0_CIS_CONTENT_REG_255_224_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_255_224_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_255_224_SFT 0
+#define F0_CIS_CONTENT_REG_255_224_HI 31
+#define F0_CIS_CONTENT_REG_255_224_SZ 32
+#define F0_CIS_CONTENT_REG_287_256_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_287_256_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_287_256_SFT 0
+#define F0_CIS_CONTENT_REG_287_256_HI 31
+#define F0_CIS_CONTENT_REG_287_256_SZ 32
+#define F0_CIS_CONTENT_REG_319_288_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_319_288_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_319_288_SFT 0
+#define F0_CIS_CONTENT_REG_319_288_HI 31
+#define F0_CIS_CONTENT_REG_319_288_SZ 32
+#define F0_CIS_CONTENT_REG_351_320_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_351_320_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_351_320_SFT 0
+#define F0_CIS_CONTENT_REG_351_320_HI 31
+#define F0_CIS_CONTENT_REG_351_320_SZ 32
+#define F0_CIS_CONTENT_REG_383_352_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_383_352_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_383_352_SFT 0
+#define F0_CIS_CONTENT_REG_383_352_HI 31
+#define F0_CIS_CONTENT_REG_383_352_SZ 32
+#define F0_CIS_CONTENT_REG_415_384_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_415_384_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_415_384_SFT 0
+#define F0_CIS_CONTENT_REG_415_384_HI 31
+#define F0_CIS_CONTENT_REG_415_384_SZ 32
+#define F0_CIS_CONTENT_REG_447_416_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_447_416_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_447_416_SFT 0
+#define F0_CIS_CONTENT_REG_447_416_HI 31
+#define F0_CIS_CONTENT_REG_447_416_SZ 32
+#define F0_CIS_CONTENT_REG_479_448_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_479_448_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_479_448_SFT 0
+#define F0_CIS_CONTENT_REG_479_448_HI 31
+#define F0_CIS_CONTENT_REG_479_448_SZ 32
+#define F0_CIS_CONTENT_REG_511_480_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_511_480_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_511_480_SFT 0
+#define F0_CIS_CONTENT_REG_511_480_HI 31
+#define F0_CIS_CONTENT_REG_511_480_SZ 32
+#define F1_CIS_CONTENT_REG_31_0_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_31_0_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_31_0_SFT 0
+#define F1_CIS_CONTENT_REG_31_0_HI 31
+#define F1_CIS_CONTENT_REG_31_0_SZ 32
+#define F1_CIS_CONTENT_REG_63_32_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_63_32_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_63_32_SFT 0
+#define F1_CIS_CONTENT_REG_63_32_HI 31
+#define F1_CIS_CONTENT_REG_63_32_SZ 32
+#define F1_CIS_CONTENT_REG_95_64_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_95_64_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_95_64_SFT 0
+#define F1_CIS_CONTENT_REG_95_64_HI 31
+#define F1_CIS_CONTENT_REG_95_64_SZ 32
+#define F1_CIS_CONTENT_REG_127_96_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_127_96_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_127_96_SFT 0
+#define F1_CIS_CONTENT_REG_127_96_HI 31
+#define F1_CIS_CONTENT_REG_127_96_SZ 32
+#define F1_CIS_CONTENT_REG_159_128_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_159_128_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_159_128_SFT 0
+#define F1_CIS_CONTENT_REG_159_128_HI 31
+#define F1_CIS_CONTENT_REG_159_128_SZ 32
+#define F1_CIS_CONTENT_REG_191_160_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_191_160_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_191_160_SFT 0
+#define F1_CIS_CONTENT_REG_191_160_HI 31
+#define F1_CIS_CONTENT_REG_191_160_SZ 32
+#define F1_CIS_CONTENT_REG_223_192_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_223_192_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_223_192_SFT 0
+#define F1_CIS_CONTENT_REG_223_192_HI 31
+#define F1_CIS_CONTENT_REG_223_192_SZ 32
+#define F1_CIS_CONTENT_REG_255_224_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_255_224_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_255_224_SFT 0
+#define F1_CIS_CONTENT_REG_255_224_HI 31
+#define F1_CIS_CONTENT_REG_255_224_SZ 32
+#define F1_CIS_CONTENT_REG_287_256_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_287_256_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_287_256_SFT 0
+#define F1_CIS_CONTENT_REG_287_256_HI 31
+#define F1_CIS_CONTENT_REG_287_256_SZ 32
+#define F1_CIS_CONTENT_REG_319_288_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_319_288_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_319_288_SFT 0
+#define F1_CIS_CONTENT_REG_319_288_HI 31
+#define F1_CIS_CONTENT_REG_319_288_SZ 32
+#define F1_CIS_CONTENT_REG_351_320_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_351_320_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_351_320_SFT 0
+#define F1_CIS_CONTENT_REG_351_320_HI 31
+#define F1_CIS_CONTENT_REG_351_320_SZ 32
+#define F1_CIS_CONTENT_REG_383_352_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_383_352_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_383_352_SFT 0
+#define F1_CIS_CONTENT_REG_383_352_HI 31
+#define F1_CIS_CONTENT_REG_383_352_SZ 32
+#define F1_CIS_CONTENT_REG_415_384_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_415_384_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_415_384_SFT 0
+#define F1_CIS_CONTENT_REG_415_384_HI 31
+#define F1_CIS_CONTENT_REG_415_384_SZ 32
+#define F1_CIS_CONTENT_REG_447_416_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_447_416_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_447_416_SFT 0
+#define F1_CIS_CONTENT_REG_447_416_HI 31
+#define F1_CIS_CONTENT_REG_447_416_SZ 32
+#define F1_CIS_CONTENT_REG_479_448_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_479_448_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_479_448_SFT 0
+#define F1_CIS_CONTENT_REG_479_448_HI 31
+#define F1_CIS_CONTENT_REG_479_448_SZ 32
+#define F1_CIS_CONTENT_REG_511_480_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_511_480_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_511_480_SFT 0
+#define F1_CIS_CONTENT_REG_511_480_HI 31
+#define F1_CIS_CONTENT_REG_511_480_SZ 32
+#define SPARE_MEM_MSK 0x000000ff
+#define SPARE_MEM_I_MSK 0xffffff00
+#define SPARE_MEM_SFT 0
+#define SPARE_MEM_HI 7
+#define SPARE_MEM_SZ 8
+#define TX_SEG_MSK 0xffffffff
+#define TX_SEG_I_MSK 0x00000000
+#define TX_SEG_SFT 0
+#define TX_SEG_HI 31
+#define TX_SEG_SZ 32
+#define CLK_WIDTH_MSK 0x0000ffff
+#define CLK_WIDTH_I_MSK 0xffff0000
+#define CLK_WIDTH_SFT 0
+#define CLK_WIDTH_HI 15
+#define CLK_WIDTH_SZ 16
+#define CSN_INTER_MSK 0xffff0000
+#define CSN_INTER_I_MSK 0x0000ffff
+#define CSN_INTER_SFT 16
+#define CSN_INTER_HI 31
+#define CSN_INTER_SZ 16
+#define BACK_DLY_MSK 0x0000ffff
+#define BACK_DLY_I_MSK 0xffff0000
+#define BACK_DLY_SFT 0
+#define BACK_DLY_HI 15
+#define BACK_DLY_SZ 16
+#define FRONT_DLY_MSK 0xffff0000
+#define FRONT_DLY_I_MSK 0x0000ffff
+#define FRONT_DLY_SFT 16
+#define FRONT_DLY_HI 31
+#define FRONT_DLY_SZ 16
+#define TWI_START_TRIG_MSK 0x00000001
+#define TWI_START_TRIG_I_MSK 0xfffffffe
+#define TWI_START_TRIG_SFT 0
+#define TWI_START_TRIG_HI 0
+#define TWI_START_TRIG_SZ 1
+#define TWI_STOP_TRIG_MSK 0x00000002
+#define TWI_STOP_TRIG_I_MSK 0xfffffffd
+#define TWI_STOP_TRIG_SFT 1
+#define TWI_STOP_TRIG_HI 1
+#define TWI_STOP_TRIG_SZ 1
+#define TWI_TRANS_CONTINUE_MSK 0x00000004
+#define TWI_TRANS_CONTINUE_I_MSK 0xfffffffb
+#define TWI_TRANS_CONTINUE_SFT 2
+#define TWI_TRANS_CONTINUE_HI 2
+#define TWI_TRANS_CONTINUE_SZ 1
+#define TWI_DEV_A_10B_MSK 0x00000001
+#define TWI_DEV_A_10B_I_MSK 0xfffffffe
+#define TWI_DEV_A_10B_SFT 0
+#define TWI_DEV_A_10B_HI 0
+#define TWI_DEV_A_10B_SZ 1
+#define TWI_MODE_MSK 0x00000002
+#define TWI_MODE_I_MSK 0xfffffffd
+#define TWI_MODE_SFT 1
+#define TWI_MODE_HI 1
+#define TWI_MODE_SZ 1
+#define SCL_MSK 0x00010000
+#define SCL_I_MSK 0xfffeffff
+#define SCL_SFT 16
+#define SCL_HI 16
+#define SCL_SZ 1
+#define SDA_MSK 0x00020000
+#define SDA_I_MSK 0xfffdffff
+#define SDA_SFT 17
+#define SDA_HI 17
+#define SDA_SZ 1
+#define TWI_INT_TXD_STALL_EN_MSK 0x00000001
+#define TWI_INT_TXD_STALL_EN_I_MSK 0xfffffffe
+#define TWI_INT_TXD_STALL_EN_SFT 0
+#define TWI_INT_TXD_STALL_EN_HI 0
+#define TWI_INT_TXD_STALL_EN_SZ 1
+#define TWI_INT_RXD_STALL_EN_MSK 0x00000002
+#define TWI_INT_RXD_STALL_EN_I_MSK 0xfffffffd
+#define TWI_INT_RXD_STALL_EN_SFT 1
+#define TWI_INT_RXD_STALL_EN_HI 1
+#define TWI_INT_RXD_STALL_EN_SZ 1
+#define TWI_INT_TRANS_FINISH_EN_MSK 0x00000004
+#define TWI_INT_TRANS_FINISH_EN_I_MSK 0xfffffffb
+#define TWI_INT_TRANS_FINISH_EN_SFT 2
+#define TWI_INT_TRANS_FINISH_EN_HI 2
+#define TWI_INT_TRANS_FINISH_EN_SZ 1
+#define TWI_INT_MISMATCH_EN_MSK 0x00000008
+#define TWI_INT_MISMATCH_EN_I_MSK 0xfffffff7
+#define TWI_INT_MISMATCH_EN_SFT 3
+#define TWI_INT_MISMATCH_EN_HI 3
+#define TWI_INT_MISMATCH_EN_SZ 1
+#define TWI_INT_TRANS_FAIL_EN_MSK 0x00000010
+#define TWI_INT_TRANS_FAIL_EN_I_MSK 0xffffffef
+#define TWI_INT_TRANS_FAIL_EN_SFT 4
+#define TWI_INT_TRANS_FAIL_EN_HI 4
+#define TWI_INT_TRANS_FAIL_EN_SZ 1
+#define TWI_INT_HOLD_BUS_EN_MSK 0x00000020
+#define TWI_INT_HOLD_BUS_EN_I_MSK 0xffffffdf
+#define TWI_INT_HOLD_BUS_EN_SFT 5
+#define TWI_INT_HOLD_BUS_EN_HI 5
+#define TWI_INT_HOLD_BUS_EN_SZ 1
+#define TWI_INT_TXD_STALL_MSK 0x00000001
+#define TWI_INT_TXD_STALL_I_MSK 0xfffffffe
+#define TWI_INT_TXD_STALL_SFT 0
+#define TWI_INT_TXD_STALL_HI 0
+#define TWI_INT_TXD_STALL_SZ 1
+#define TWI_INT_RXD_STALL_MSK 0x00000002
+#define TWI_INT_RXD_STALL_I_MSK 0xfffffffd
+#define TWI_INT_RXD_STALL_SFT 1
+#define TWI_INT_RXD_STALL_HI 1
+#define TWI_INT_RXD_STALL_SZ 1
+#define TWI_INT_TRANS_FINISH_MSK 0x00000004
+#define TWI_INT_TRANS_FINISH_I_MSK 0xfffffffb
+#define TWI_INT_TRANS_FINISH_SFT 2
+#define TWI_INT_TRANS_FINISH_HI 2
+#define TWI_INT_TRANS_FINISH_SZ 1
+#define TWI_INT_MISMATCH_MSK 0x00000008
+#define TWI_INT_MISMATCH_I_MSK 0xfffffff7
+#define TWI_INT_MISMATCH_SFT 3
+#define TWI_INT_MISMATCH_HI 3
+#define TWI_INT_MISMATCH_SZ 1
+#define TWI_INT_TRANS_FAIL_MSK 0x00000010
+#define TWI_INT_TRANS_FAIL_I_MSK 0xffffffef
+#define TWI_INT_TRANS_FAIL_SFT 4
+#define TWI_INT_TRANS_FAIL_HI 4
+#define TWI_INT_TRANS_FAIL_SZ 1
+#define TWI_INT_HOLD_BUS_MSK 0x00000020
+#define TWI_INT_HOLD_BUS_I_MSK 0xffffffdf
+#define TWI_INT_HOLD_BUS_SFT 5
+#define TWI_INT_HOLD_BUS_HI 5
+#define TWI_INT_HOLD_BUS_SZ 1
+#define TWI_INT_TXD_STALL_ST_MSK 0x00000001
+#define TWI_INT_TXD_STALL_ST_I_MSK 0xfffffffe
+#define TWI_INT_TXD_STALL_ST_SFT 0
+#define TWI_INT_TXD_STALL_ST_HI 0
+#define TWI_INT_TXD_STALL_ST_SZ 1
+#define TWI_INT_RXD_STALL_ST_MSK 0x00000002
+#define TWI_INT_RXD_STALL_ST_I_MSK 0xfffffffd
+#define TWI_INT_RXD_STALL_ST_SFT 1
+#define TWI_INT_RXD_STALL_ST_HI 1
+#define TWI_INT_RXD_STALL_ST_SZ 1
+#define TWI_INT_TRANS_FINISH_ST_MSK 0x00000004
+#define TWI_INT_TRANS_FINISH_ST_I_MSK 0xfffffffb
+#define TWI_INT_TRANS_FINISH_ST_SFT 2
+#define TWI_INT_TRANS_FINISH_ST_HI 2
+#define TWI_INT_TRANS_FINISH_ST_SZ 1
+#define TWI_INT_MISMATCH_ST_MSK 0x00000008
+#define TWI_INT_MISMATCH_ST_I_MSK 0xfffffff7
+#define TWI_INT_MISMATCH_ST_SFT 3
+#define TWI_INT_MISMATCH_ST_HI 3
+#define TWI_INT_MISMATCH_ST_SZ 1
+#define TWI_INT_TRANS_FAIL_ST_MSK 0x00000010
+#define TWI_INT_TRANS_FAIL_ST_I_MSK 0xffffffef
+#define TWI_INT_TRANS_FAIL_ST_SFT 4
+#define TWI_INT_TRANS_FAIL_ST_HI 4
+#define TWI_INT_TRANS_FAIL_ST_SZ 1
+#define TWI_INT_HOLD_BUS_ST_MSK 0x00000020
+#define TWI_INT_HOLD_BUS_ST_I_MSK 0xffffffdf
+#define TWI_INT_HOLD_BUS_ST_SFT 5
+#define TWI_INT_HOLD_BUS_ST_HI 5
+#define TWI_INT_HOLD_BUS_ST_SZ 1
+#define TWI_STATUS_RECORD_0_MSK 0xffffffff
+#define TWI_STATUS_RECORD_0_I_MSK 0x00000000
+#define TWI_STATUS_RECORD_0_SFT 0
+#define TWI_STATUS_RECORD_0_HI 31
+#define TWI_STATUS_RECORD_0_SZ 32
+#define TWI_STATUS_RECORD_1_MSK 0xffffffff
+#define TWI_STATUS_RECORD_1_I_MSK 0x00000000
+#define TWI_STATUS_RECORD_1_SFT 0
+#define TWI_STATUS_RECORD_1_HI 31
+#define TWI_STATUS_RECORD_1_SZ 32
+#define TWI_RX_MSK 0x00000001
+#define TWI_RX_I_MSK 0xfffffffe
+#define TWI_RX_SFT 0
+#define TWI_RX_HI 0
+#define TWI_RX_SZ 1
+#define TWI_DEV_A10B_MSK 0x000007fe
+#define TWI_DEV_A10B_I_MSK 0xfffff801
+#define TWI_DEV_A10B_SFT 1
+#define TWI_DEV_A10B_HI 10
+#define TWI_DEV_A10B_SZ 10
+#define TWI_TXD_DATA_MSK 0x000000ff
+#define TWI_TXD_DATA_I_MSK 0xffffff00
+#define TWI_TXD_DATA_SFT 0
+#define TWI_TXD_DATA_HI 7
+#define TWI_TXD_DATA_SZ 8
+#define TWI_RXD_DATA_MSK 0x000000ff
+#define TWI_RXD_DATA_I_MSK 0xffffff00
+#define TWI_RXD_DATA_SFT 0
+#define TWI_RXD_DATA_HI 7
+#define TWI_RXD_DATA_SZ 8
+#define TWI_PSCL_MSK 0x000003ff
+#define TWI_PSCL_I_MSK 0xfffffc00
+#define TWI_PSCL_SFT 0
+#define TWI_PSCL_HI 9
+#define TWI_PSCL_SZ 10
+#define TWI_STA_STO_PSCL_MSK 0x03ff0000
+#define TWI_STA_STO_PSCL_I_MSK 0xfc00ffff
+#define TWI_STA_STO_PSCL_SFT 16
+#define TWI_STA_STO_PSCL_HI 25
+#define TWI_STA_STO_PSCL_SZ 10
+#define TWI_TRANS_PSDA_MSK 0x000003ff
+#define TWI_TRANS_PSDA_I_MSK 0xfffffc00
+#define TWI_TRANS_PSDA_SFT 0
+#define TWI_TRANS_PSDA_HI 9
+#define TWI_TRANS_PSDA_SZ 10
+#define TWI_DELAY_ACK_MSK 0x000003ff
+#define TWI_DELAY_ACK_I_MSK 0xfffffc00
+#define TWI_DELAY_ACK_SFT 0
+#define TWI_DELAY_ACK_HI 9
+#define TWI_DELAY_ACK_SZ 10
+#define I2CM_INT_WDONE_MSK 0x00000001
+#define I2CM_INT_WDONE_I_MSK 0xfffffffe
+#define I2CM_INT_WDONE_SFT 0
+#define I2CM_INT_WDONE_HI 0
+#define I2CM_INT_WDONE_SZ 1
+#define I2CM_INT_RDONE_MSK 0x00000002
+#define I2CM_INT_RDONE_I_MSK 0xfffffffd
+#define I2CM_INT_RDONE_SFT 1
+#define I2CM_INT_RDONE_HI 1
+#define I2CM_INT_RDONE_SZ 1
+#define I2CM_IDLE_MSK 0x00000004
+#define I2CM_IDLE_I_MSK 0xfffffffb
+#define I2CM_IDLE_SFT 2
+#define I2CM_IDLE_HI 2
+#define I2CM_IDLE_SZ 1
+#define I2CM_INT_MISMATCH_MSK 0x00000008
+#define I2CM_INT_MISMATCH_I_MSK 0xfffffff7
+#define I2CM_INT_MISMATCH_SFT 3
+#define I2CM_INT_MISMATCH_HI 3
+#define I2CM_INT_MISMATCH_SZ 1
+#define I2CM_PSCL_MSK 0x00003ff0
+#define I2CM_PSCL_I_MSK 0xffffc00f
+#define I2CM_PSCL_SFT 4
+#define I2CM_PSCL_HI 13
+#define I2CM_PSCL_SZ 10
+#define I2CM_MANUAL_MODE_MSK 0x00010000
+#define I2CM_MANUAL_MODE_I_MSK 0xfffeffff
+#define I2CM_MANUAL_MODE_SFT 16
+#define I2CM_MANUAL_MODE_HI 16
+#define I2CM_MANUAL_MODE_SZ 1
+#define I2CM_INT_WDATA_NEED_MSK 0x00020000
+#define I2CM_INT_WDATA_NEED_I_MSK 0xfffdffff
+#define I2CM_INT_WDATA_NEED_SFT 17
+#define I2CM_INT_WDATA_NEED_HI 17
+#define I2CM_INT_WDATA_NEED_SZ 1
+#define I2CM_INT_RDATA_NEED_MSK 0x00040000
+#define I2CM_INT_RDATA_NEED_I_MSK 0xfffbffff
+#define I2CM_INT_RDATA_NEED_SFT 18
+#define I2CM_INT_RDATA_NEED_HI 18
+#define I2CM_INT_RDATA_NEED_SZ 1
+#define I2CM_DEV_A_MSK 0x000003ff
+#define I2CM_DEV_A_I_MSK 0xfffffc00
+#define I2CM_DEV_A_SFT 0
+#define I2CM_DEV_A_HI 9
+#define I2CM_DEV_A_SZ 10
+#define I2CM_DEV_A10B_MSK 0x00004000
+#define I2CM_DEV_A10B_I_MSK 0xffffbfff
+#define I2CM_DEV_A10B_SFT 14
+#define I2CM_DEV_A10B_HI 14
+#define I2CM_DEV_A10B_SZ 1
+#define I2CM_RX_MSK 0x00008000
+#define I2CM_RX_I_MSK 0xffff7fff
+#define I2CM_RX_SFT 15
+#define I2CM_RX_HI 15
+#define I2CM_RX_SZ 1
+#define I2CM_LEN_MSK 0x0000ffff
+#define I2CM_LEN_I_MSK 0xffff0000
+#define I2CM_LEN_SFT 0
+#define I2CM_LEN_HI 15
+#define I2CM_LEN_SZ 16
+#define I2CM_T_LEFT_MSK 0x00070000
+#define I2CM_T_LEFT_I_MSK 0xfff8ffff
+#define I2CM_T_LEFT_SFT 16
+#define I2CM_T_LEFT_HI 18
+#define I2CM_T_LEFT_SZ 3
+#define I2CM_R_GET_MSK 0x07000000
+#define I2CM_R_GET_I_MSK 0xf8ffffff
+#define I2CM_R_GET_SFT 24
+#define I2CM_R_GET_HI 26
+#define I2CM_R_GET_SZ 3
+#define I2CM_WDAT_MSK 0xffffffff
+#define I2CM_WDAT_I_MSK 0x00000000
+#define I2CM_WDAT_SFT 0
+#define I2CM_WDAT_HI 31
+#define I2CM_WDAT_SZ 32
+#define I2CM_RDAT_MSK 0xffffffff
+#define I2CM_RDAT_I_MSK 0x00000000
+#define I2CM_RDAT_SFT 0
+#define I2CM_RDAT_HI 31
+#define I2CM_RDAT_SZ 32
+#define I2CM_SR_LEN_MSK 0x0000ffff
+#define I2CM_SR_LEN_I_MSK 0xffff0000
+#define I2CM_SR_LEN_SFT 0
+#define I2CM_SR_LEN_HI 15
+#define I2CM_SR_LEN_SZ 16
+#define I2CM_SR_RX_MSK 0x00010000
+#define I2CM_SR_RX_I_MSK 0xfffeffff
+#define I2CM_SR_RX_SFT 16
+#define I2CM_SR_RX_HI 16
+#define I2CM_SR_RX_SZ 1
+#define I2CM_REPEAT_START_MSK 0x00020000
+#define I2CM_REPEAT_START_I_MSK 0xfffdffff
+#define I2CM_REPEAT_START_SFT 17
+#define I2CM_REPEAT_START_HI 17
+#define I2CM_REPEAT_START_SZ 1
+#define I2CM_STA_STO_PSCL_MSK 0x000003ff
+#define I2CM_STA_STO_PSCL_I_MSK 0xfffffc00
+#define I2CM_STA_STO_PSCL_SFT 0
+#define I2CM_STA_STO_PSCL_HI 9
+#define I2CM_STA_STO_PSCL_SZ 10
+#define UART_DATA_MSK 0x000000ff
+#define UART_DATA_I_MSK 0xffffff00
+#define UART_DATA_SFT 0
+#define UART_DATA_HI 7
+#define UART_DATA_SZ 8
+#define DATA_RDY_IE_MSK 0x00000001
+#define DATA_RDY_IE_I_MSK 0xfffffffe
+#define DATA_RDY_IE_SFT 0
+#define DATA_RDY_IE_HI 0
+#define DATA_RDY_IE_SZ 1
+#define THR_EMPTY_IE_MSK 0x00000002
+#define THR_EMPTY_IE_I_MSK 0xfffffffd
+#define THR_EMPTY_IE_SFT 1
+#define THR_EMPTY_IE_HI 1
+#define THR_EMPTY_IE_SZ 1
+#define RX_LINESTS_IE_MSK 0x00000004
+#define RX_LINESTS_IE_I_MSK 0xfffffffb
+#define RX_LINESTS_IE_SFT 2
+#define RX_LINESTS_IE_HI 2
+#define RX_LINESTS_IE_SZ 1
+#define MDM_STS_IE_MSK 0x00000008
+#define MDM_STS_IE_I_MSK 0xfffffff7
+#define MDM_STS_IE_SFT 3
+#define MDM_STS_IE_HI 3
+#define MDM_STS_IE_SZ 1
+#define TX_THRH_IE_MSK 0x00000010
+#define TX_THRH_IE_I_MSK 0xffffffef
+#define TX_THRH_IE_SFT 4
+#define TX_THRH_IE_HI 4
+#define TX_THRH_IE_SZ 1
+#define TX_THRL_IE_MSK 0x00000020
+#define TX_THRL_IE_I_MSK 0xffffffdf
+#define TX_THRL_IE_SFT 5
+#define TX_THRL_IE_HI 5
+#define TX_THRL_IE_SZ 1
+#define FIFO_EN_MSK 0x00000001
+#define FIFO_EN_I_MSK 0xfffffffe
+#define FIFO_EN_SFT 0
+#define FIFO_EN_HI 0
+#define FIFO_EN_SZ 1
+#define RXFIFO_RST_MSK 0x00000002
+#define RXFIFO_RST_I_MSK 0xfffffffd
+#define RXFIFO_RST_SFT 1
+#define RXFIFO_RST_HI 1
+#define RXFIFO_RST_SZ 1
+#define TXFIFO_RST_MSK 0x00000004
+#define TXFIFO_RST_I_MSK 0xfffffffb
+#define TXFIFO_RST_SFT 2
+#define TXFIFO_RST_HI 2
+#define TXFIFO_RST_SZ 1
+#define DMA_MODE_MSK 0x00000008
+#define DMA_MODE_I_MSK 0xfffffff7
+#define DMA_MODE_SFT 3
+#define DMA_MODE_HI 3
+#define DMA_MODE_SZ 1
+#define EN_AUTO_RTS_MSK 0x00000010
+#define EN_AUTO_RTS_I_MSK 0xffffffef
+#define EN_AUTO_RTS_SFT 4
+#define EN_AUTO_RTS_HI 4
+#define EN_AUTO_RTS_SZ 1
+#define EN_AUTO_CTS_MSK 0x00000020
+#define EN_AUTO_CTS_I_MSK 0xffffffdf
+#define EN_AUTO_CTS_SFT 5
+#define EN_AUTO_CTS_HI 5
+#define EN_AUTO_CTS_SZ 1
+#define RXFIFO_TRGLVL_MSK 0x000000c0
+#define RXFIFO_TRGLVL_I_MSK 0xffffff3f
+#define RXFIFO_TRGLVL_SFT 6
+#define RXFIFO_TRGLVL_HI 7
+#define RXFIFO_TRGLVL_SZ 2
+#define WORD_LEN_MSK 0x00000003
+#define WORD_LEN_I_MSK 0xfffffffc
+#define WORD_LEN_SFT 0
+#define WORD_LEN_HI 1
+#define WORD_LEN_SZ 2
+#define STOP_BIT_MSK 0x00000004
+#define STOP_BIT_I_MSK 0xfffffffb
+#define STOP_BIT_SFT 2
+#define STOP_BIT_HI 2
+#define STOP_BIT_SZ 1
+#define PARITY_EN_MSK 0x00000008
+#define PARITY_EN_I_MSK 0xfffffff7
+#define PARITY_EN_SFT 3
+#define PARITY_EN_HI 3
+#define PARITY_EN_SZ 1
+#define EVEN_PARITY_MSK 0x00000010
+#define EVEN_PARITY_I_MSK 0xffffffef
+#define EVEN_PARITY_SFT 4
+#define EVEN_PARITY_HI 4
+#define EVEN_PARITY_SZ 1
+#define FORCE_PARITY_MSK 0x00000020
+#define FORCE_PARITY_I_MSK 0xffffffdf
+#define FORCE_PARITY_SFT 5
+#define FORCE_PARITY_HI 5
+#define FORCE_PARITY_SZ 1
+#define SET_BREAK_MSK 0x00000040
+#define SET_BREAK_I_MSK 0xffffffbf
+#define SET_BREAK_SFT 6
+#define SET_BREAK_HI 6
+#define SET_BREAK_SZ 1
+#define DLAB_MSK 0x00000080
+#define DLAB_I_MSK 0xffffff7f
+#define DLAB_SFT 7
+#define DLAB_HI 7
+#define DLAB_SZ 1
+#define DTR_MSK 0x00000001
+#define DTR_I_MSK 0xfffffffe
+#define DTR_SFT 0
+#define DTR_HI 0
+#define DTR_SZ 1
+#define RTS_MSK 0x00000002
+#define RTS_I_MSK 0xfffffffd
+#define RTS_SFT 1
+#define RTS_HI 1
+#define RTS_SZ 1
+#define OUT_1_MSK 0x00000004
+#define OUT_1_I_MSK 0xfffffffb
+#define OUT_1_SFT 2
+#define OUT_1_HI 2
+#define OUT_1_SZ 1
+#define OUT_2_MSK 0x00000008
+#define OUT_2_I_MSK 0xfffffff7
+#define OUT_2_SFT 3
+#define OUT_2_HI 3
+#define OUT_2_SZ 1
+#define LOOP_BACK_MSK 0x00000010
+#define LOOP_BACK_I_MSK 0xffffffef
+#define LOOP_BACK_SFT 4
+#define LOOP_BACK_HI 4
+#define LOOP_BACK_SZ 1
+#define DE_RTS_MSK 0x00000020
+#define DE_RTS_I_MSK 0xffffffdf
+#define DE_RTS_SFT 5
+#define DE_RTS_HI 5
+#define DE_RTS_SZ 1
+#define DATA_RDY_MSK 0x00000001
+#define DATA_RDY_I_MSK 0xfffffffe
+#define DATA_RDY_SFT 0
+#define DATA_RDY_HI 0
+#define DATA_RDY_SZ 1
+#define OVERRUN_ERR_MSK 0x00000002
+#define OVERRUN_ERR_I_MSK 0xfffffffd
+#define OVERRUN_ERR_SFT 1
+#define OVERRUN_ERR_HI 1
+#define OVERRUN_ERR_SZ 1
+#define PARITY_ERR_MSK 0x00000004
+#define PARITY_ERR_I_MSK 0xfffffffb
+#define PARITY_ERR_SFT 2
+#define PARITY_ERR_HI 2
+#define PARITY_ERR_SZ 1
+#define FRAMING_ERR_MSK 0x00000008
+#define FRAMING_ERR_I_MSK 0xfffffff7
+#define FRAMING_ERR_SFT 3
+#define FRAMING_ERR_HI 3
+#define FRAMING_ERR_SZ 1
+#define BREAK_INT_MSK 0x00000010
+#define BREAK_INT_I_MSK 0xffffffef
+#define BREAK_INT_SFT 4
+#define BREAK_INT_HI 4
+#define BREAK_INT_SZ 1
+#define THR_EMPTY_MSK 0x00000020
+#define THR_EMPTY_I_MSK 0xffffffdf
+#define THR_EMPTY_SFT 5
+#define THR_EMPTY_HI 5
+#define THR_EMPTY_SZ 1
+#define TX_EMPTY_MSK 0x00000040
+#define TX_EMPTY_I_MSK 0xffffffbf
+#define TX_EMPTY_SFT 6
+#define TX_EMPTY_HI 6
+#define TX_EMPTY_SZ 1
+#define FIFODATA_ERR_MSK 0x00000080
+#define FIFODATA_ERR_I_MSK 0xffffff7f
+#define FIFODATA_ERR_SFT 7
+#define FIFODATA_ERR_HI 7
+#define FIFODATA_ERR_SZ 1
+#define DELTA_CTS_MSK 0x00000001
+#define DELTA_CTS_I_MSK 0xfffffffe
+#define DELTA_CTS_SFT 0
+#define DELTA_CTS_HI 0
+#define DELTA_CTS_SZ 1
+#define DELTA_DSR_MSK 0x00000002
+#define DELTA_DSR_I_MSK 0xfffffffd
+#define DELTA_DSR_SFT 1
+#define DELTA_DSR_HI 1
+#define DELTA_DSR_SZ 1
+#define TRAILEDGE_RI_MSK 0x00000004
+#define TRAILEDGE_RI_I_MSK 0xfffffffb
+#define TRAILEDGE_RI_SFT 2
+#define TRAILEDGE_RI_HI 2
+#define TRAILEDGE_RI_SZ 1
+#define DELTA_CD_MSK 0x00000008
+#define DELTA_CD_I_MSK 0xfffffff7
+#define DELTA_CD_SFT 3
+#define DELTA_CD_HI 3
+#define DELTA_CD_SZ 1
+#define CTS_MSK 0x00000010
+#define CTS_I_MSK 0xffffffef
+#define CTS_SFT 4
+#define CTS_HI 4
+#define CTS_SZ 1
+#define DSR_MSK 0x00000020
+#define DSR_I_MSK 0xffffffdf
+#define DSR_SFT 5
+#define DSR_HI 5
+#define DSR_SZ 1
+#define RI_MSK 0x00000040
+#define RI_I_MSK 0xffffffbf
+#define RI_SFT 6
+#define RI_HI 6
+#define RI_SZ 1
+#define CD_MSK 0x00000080
+#define CD_I_MSK 0xffffff7f
+#define CD_SFT 7
+#define CD_HI 7
+#define CD_SZ 1
+#define BRDC_DIV_MSK 0x0000ffff
+#define BRDC_DIV_I_MSK 0xffff0000
+#define BRDC_DIV_SFT 0
+#define BRDC_DIV_HI 15
+#define BRDC_DIV_SZ 16
+#define RTHR_L_MSK 0x0000000f
+#define RTHR_L_I_MSK 0xfffffff0
+#define RTHR_L_SFT 0
+#define RTHR_L_HI 3
+#define RTHR_L_SZ 4
+#define RTHR_H_MSK 0x000000f0
+#define RTHR_H_I_MSK 0xffffff0f
+#define RTHR_H_SFT 4
+#define RTHR_H_HI 7
+#define RTHR_H_SZ 4
+#define INT_IDCODE_MSK 0x0000000f
+#define INT_IDCODE_I_MSK 0xfffffff0
+#define INT_IDCODE_SFT 0
+#define INT_IDCODE_HI 3
+#define INT_IDCODE_SZ 4
+#define RX_IDLE_MSK 0x00000010
+#define RX_IDLE_I_MSK 0xffffffef
+#define RX_IDLE_SFT 4
+#define RX_IDLE_HI 4
+#define RX_IDLE_SZ 1
+#define TX_IDLE_MSK 0x00000020
+#define TX_IDLE_I_MSK 0xffffffdf
+#define TX_IDLE_SFT 5
+#define TX_IDLE_HI 5
+#define TX_IDLE_SZ 1
+#define FIFOS_ENABLED_MSK 0x000000c0
+#define FIFOS_ENABLED_I_MSK 0xffffff3f
+#define FIFOS_ENABLED_SFT 6
+#define FIFOS_ENABLED_HI 7
+#define FIFOS_ENABLED_SZ 2
+#define TTHR_L_MSK 0x0000000f
+#define TTHR_L_I_MSK 0xfffffff0
+#define TTHR_L_SFT 0
+#define TTHR_L_HI 3
+#define TTHR_L_SZ 4
+#define TTHR_H_MSK 0x000000f0
+#define TTHR_H_I_MSK 0xffffff0f
+#define TTHR_H_SFT 4
+#define TTHR_H_HI 7
+#define TTHR_H_SZ 4
+#define RX_RECIEVED_MSK 0x00000001
+#define RX_RECIEVED_I_MSK 0xfffffffe
+#define RX_RECIEVED_SFT 0
+#define RX_RECIEVED_HI 0
+#define RX_RECIEVED_SZ 1
+#define RX_FIFO_TO_MSK 0x00000002
+#define RX_FIFO_TO_I_MSK 0xfffffffd
+#define RX_FIFO_TO_SFT 1
+#define RX_FIFO_TO_HI 1
+#define RX_FIFO_TO_SZ 1
+#define TX_L_MSK 0x00000004
+#define TX_L_I_MSK 0xfffffffb
+#define TX_L_SFT 2
+#define TX_L_HI 2
+#define TX_L_SZ 1
+#define TX_H_MSK 0x00000008
+#define TX_H_I_MSK 0xfffffff7
+#define TX_H_SFT 3
+#define TX_H_HI 3
+#define TX_H_SZ 1
+#define TX_EMPTY2_MSK 0x00000010
+#define TX_EMPTY2_I_MSK 0xffffffef
+#define TX_EMPTY2_SFT 4
+#define TX_EMPTY2_HI 4
+#define TX_EMPTY2_SZ 1
+#define OVERRUN_MSK 0x00000020
+#define OVERRUN_I_MSK 0xffffffdf
+#define OVERRUN_SFT 5
+#define OVERRUN_HI 5
+#define OVERRUN_SZ 1
+#define FRAMING_MSK 0x00000040
+#define FRAMING_I_MSK 0xffffffbf
+#define FRAMING_SFT 6
+#define FRAMING_HI 6
+#define FRAMING_SZ 1
+#define BREAK_MSK 0x00000080
+#define BREAK_I_MSK 0xffffff7f
+#define BREAK_SFT 7
+#define BREAK_HI 7
+#define BREAK_SZ 1
+#define PARITY_MSK 0x00000100
+#define PARITY_I_MSK 0xfffffeff
+#define PARITY_SFT 8
+#define PARITY_HI 8
+#define PARITY_SZ 1
+#define MODEN_INT_MSK 0x00000200
+#define MODEN_INT_I_MSK 0xfffffdff
+#define MODEN_INT_SFT 9
+#define MODEN_INT_HI 9
+#define MODEN_INT_SZ 1
+#define ROP_A_MSK 0x0000000f
+#define ROP_A_I_MSK 0xfffffff0
+#define ROP_A_SFT 0
+#define ROP_A_HI 3
+#define ROP_A_SZ 4
+#define RIP_A_MSK 0x000000f0
+#define RIP_A_I_MSK 0xffffff0f
+#define RIP_A_SFT 4
+#define RIP_A_HI 7
+#define RIP_A_SZ 4
+#define TOP_A_MSK 0x00000f00
+#define TOP_A_I_MSK 0xfffff0ff
+#define TOP_A_SFT 8
+#define TOP_A_HI 11
+#define TOP_A_SZ 4
+#define TIP_A_MSK 0x0000f000
+#define TIP_A_I_MSK 0xffff0fff
+#define TIP_A_SFT 12
+#define TIP_A_HI 15
+#define TIP_A_SZ 4
+#define HSUART_RXD_MSK 0x000000ff
+#define HSUART_RXD_I_MSK 0xffffff00
+#define HSUART_RXD_SFT 0
+#define HSUART_RXD_HI 7
+#define HSUART_RXD_SZ 8
+#define HSUART_ENABRXBUFF_MSK 0x00000001
+#define HSUART_ENABRXBUFF_I_MSK 0xfffffffe
+#define HSUART_ENABRXBUFF_SFT 0
+#define HSUART_ENABRXBUFF_HI 0
+#define HSUART_ENABRXBUFF_SZ 1
+#define HSUART_ENABTXBUFF_MSK 0x00000002
+#define HSUART_ENABTXBUFF_I_MSK 0xfffffffd
+#define HSUART_ENABTXBUFF_SFT 1
+#define HSUART_ENABTXBUFF_HI 1
+#define HSUART_ENABTXBUFF_SZ 1
+#define HSUART_ENABLNSTAT_MSK 0x00000004
+#define HSUART_ENABLNSTAT_I_MSK 0xfffffffb
+#define HSUART_ENABLNSTAT_SFT 2
+#define HSUART_ENABLNSTAT_HI 2
+#define HSUART_ENABLNSTAT_SZ 1
+#define HSUART_ENABMDSTAT_MSK 0x00000008
+#define HSUART_ENABMDSTAT_I_MSK 0xfffffff7
+#define HSUART_ENABMDSTAT_SFT 3
+#define HSUART_ENABMDSTAT_HI 3
+#define HSUART_ENABMDSTAT_SZ 1
+#define HSUART_ENABCTXTHR_MSK 0x00000010
+#define HSUART_ENABCTXTHR_I_MSK 0xffffffef
+#define HSUART_ENABCTXTHR_SFT 4
+#define HSUART_ENABCTXTHR_HI 4
+#define HSUART_ENABCTXTHR_SZ 1
+#define HSUART_ENABDMARXEND_MSK 0x00000040
+#define HSUART_ENABDMARXEND_I_MSK 0xffffffbf
+#define HSUART_ENABDMARXEND_SFT 6
+#define HSUART_ENABDMARXEND_HI 6
+#define HSUART_ENABDMARXEND_SZ 1
+#define HSUART_ENABDMATXEND_MSK 0x00000080
+#define HSUART_ENABDMATXEND_I_MSK 0xffffff7f
+#define HSUART_ENABDMATXEND_SFT 7
+#define HSUART_ENABDMATXEND_HI 7
+#define HSUART_ENABDMATXEND_SZ 1
+#define HSUART_FIFOE_MSK 0x00000001
+#define HSUART_FIFOE_I_MSK 0xfffffffe
+#define HSUART_FIFOE_SFT 0
+#define HSUART_FIFOE_HI 0
+#define HSUART_FIFOE_SZ 1
+#define HSUART_RX_FIFO_RST_MSK 0x00000002
+#define HSUART_RX_FIFO_RST_I_MSK 0xfffffffd
+#define HSUART_RX_FIFO_RST_SFT 1
+#define HSUART_RX_FIFO_RST_HI 1
+#define HSUART_RX_FIFO_RST_SZ 1
+#define HSUART_TX_FIFO_RST_MSK 0x00000004
+#define HSUART_TX_FIFO_RST_I_MSK 0xfffffffb
+#define HSUART_TX_FIFO_RST_SFT 2
+#define HSUART_TX_FIFO_RST_HI 2
+#define HSUART_TX_FIFO_RST_SZ 1
+#define HSUART_DMA_MSK 0x00000008
+#define HSUART_DMA_I_MSK 0xfffffff7
+#define HSUART_DMA_SFT 3
+#define HSUART_DMA_HI 3
+#define HSUART_DMA_SZ 1
+#define HSUART_RX_TRIG_LV_MSK 0x000000c0
+#define HSUART_RX_TRIG_LV_I_MSK 0xffffff3f
+#define HSUART_RX_TRIG_LV_SFT 6
+#define HSUART_RX_TRIG_LV_HI 7
+#define HSUART_RX_TRIG_LV_SZ 2
+#define HSUART_WLS_MSK 0x00000003
+#define HSUART_WLS_I_MSK 0xfffffffc
+#define HSUART_WLS_SFT 0
+#define HSUART_WLS_HI 1
+#define HSUART_WLS_SZ 2
+#define HSUART_STB_MSK 0x00000004
+#define HSUART_STB_I_MSK 0xfffffffb
+#define HSUART_STB_SFT 2
+#define HSUART_STB_HI 2
+#define HSUART_STB_SZ 1
+#define HSUART_PEN_MSK 0x00000008
+#define HSUART_PEN_I_MSK 0xfffffff7
+#define HSUART_PEN_SFT 3
+#define HSUART_PEN_HI 3
+#define HSUART_PEN_SZ 1
+#define HSUART_SP_EPS_MSK 0x00000030
+#define HSUART_SP_EPS_I_MSK 0xffffffcf
+#define HSUART_SP_EPS_SFT 4
+#define HSUART_SP_EPS_HI 5
+#define HSUART_SP_EPS_SZ 2
+#define HSUART_SB_MSK 0x00000040
+#define HSUART_SB_I_MSK 0xffffffbf
+#define HSUART_SB_SFT 6
+#define HSUART_SB_HI 6
+#define HSUART_SB_SZ 1
+#define HSUART_DLAB_MSK 0x00000080
+#define HSUART_DLAB_I_MSK 0xffffff7f
+#define HSUART_DLAB_SFT 7
+#define HSUART_DLAB_HI 7
+#define HSUART_DLAB_SZ 1
+#define HSUART_DTS_MSK 0x00000001
+#define HSUART_DTS_I_MSK 0xfffffffe
+#define HSUART_DTS_SFT 0
+#define HSUART_DTS_HI 0
+#define HSUART_DTS_SZ 1
+#define HSUART_RTS_MSK 0x00000002
+#define HSUART_RTS_I_MSK 0xfffffffd
+#define HSUART_RTS_SFT 1
+#define HSUART_RTS_HI 1
+#define HSUART_RTS_SZ 1
+#define HSUART_OUT1_MSK 0x00000004
+#define HSUART_OUT1_I_MSK 0xfffffffb
+#define HSUART_OUT1_SFT 2
+#define HSUART_OUT1_HI 2
+#define HSUART_OUT1_SZ 1
+#define HSUART_OUT2_MSK 0x00000008
+#define HSUART_OUT2_I_MSK 0xfffffff7
+#define HSUART_OUT2_SFT 3
+#define HSUART_OUT2_HI 3
+#define HSUART_OUT2_SZ 1
+#define HSUART_LOOP1_MSK 0x00000010
+#define HSUART_LOOP1_I_MSK 0xffffffef
+#define HSUART_LOOP1_SFT 4
+#define HSUART_LOOP1_HI 4
+#define HSUART_LOOP1_SZ 1
+#define HSUART_ARTS_MSK 0x00000040
+#define HSUART_ARTS_I_MSK 0xffffffbf
+#define HSUART_ARTS_SFT 6
+#define HSUART_ARTS_HI 6
+#define HSUART_ARTS_SZ 1
+#define HSUART_ACTS_MSK 0x00000080
+#define HSUART_ACTS_I_MSK 0xffffff7f
+#define HSUART_ACTS_SFT 7
+#define HSUART_ACTS_HI 7
+#define HSUART_ACTS_SZ 1
+#define HSUART_DR_MSK 0x00000001
+#define HSUART_DR_I_MSK 0xfffffffe
+#define HSUART_DR_SFT 0
+#define HSUART_DR_HI 0
+#define HSUART_DR_SZ 1
+#define HSUART_OE_MSK 0x00000002
+#define HSUART_OE_I_MSK 0xfffffffd
+#define HSUART_OE_SFT 1
+#define HSUART_OE_HI 1
+#define HSUART_OE_SZ 1
+#define HSUART_PE_MSK 0x00000004
+#define HSUART_PE_I_MSK 0xfffffffb
+#define HSUART_PE_SFT 2
+#define HSUART_PE_HI 2
+#define HSUART_PE_SZ 1
+#define HSUART_FE_MSK 0x00000008
+#define HSUART_FE_I_MSK 0xfffffff7
+#define HSUART_FE_SFT 3
+#define HSUART_FE_HI 3
+#define HSUART_FE_SZ 1
+#define HSUART_BI_MSK 0x00000010
+#define HSUART_BI_I_MSK 0xffffffef
+#define HSUART_BI_SFT 4
+#define HSUART_BI_HI 4
+#define HSUART_BI_SZ 1
+#define HSUART_THRE_MSK 0x00000020
+#define HSUART_THRE_I_MSK 0xffffffdf
+#define HSUART_THRE_SFT 5
+#define HSUART_THRE_HI 5
+#define HSUART_THRE_SZ 1
+#define HSUART_TSRE_MSK 0x00000040
+#define HSUART_TSRE_I_MSK 0xffffffbf
+#define HSUART_TSRE_SFT 6
+#define HSUART_TSRE_HI 6
+#define HSUART_TSRE_SZ 1
+#define HSUART_ERF_MSK 0x00000080
+#define HSUART_ERF_I_MSK 0xffffff7f
+#define HSUART_ERF_SFT 7
+#define HSUART_ERF_HI 7
+#define HSUART_ERF_SZ 1
+#define HSUART_DCTS_MSK 0x00000001
+#define HSUART_DCTS_I_MSK 0xfffffffe
+#define HSUART_DCTS_SFT 0
+#define HSUART_DCTS_HI 0
+#define HSUART_DCTS_SZ 1
+#define HSUART_DDSR_MSK 0x00000002
+#define HSUART_DDSR_I_MSK 0xfffffffd
+#define HSUART_DDSR_SFT 1
+#define HSUART_DDSR_HI 1
+#define HSUART_DDSR_SZ 1
+#define HSUART_TERI_MSK 0x00000004
+#define HSUART_TERI_I_MSK 0xfffffffb
+#define HSUART_TERI_SFT 2
+#define HSUART_TERI_HI 2
+#define HSUART_TERI_SZ 1
+#define HSUART_DDCD_MSK 0x00000008
+#define HSUART_DDCD_I_MSK 0xfffffff7
+#define HSUART_DDCD_SFT 3
+#define HSUART_DDCD_HI 3
+#define HSUART_DDCD_SZ 1
+#define HSUART_CTS_MSK 0x00000010
+#define HSUART_CTS_I_MSK 0xffffffef
+#define HSUART_CTS_SFT 4
+#define HSUART_CTS_HI 4
+#define HSUART_CTS_SZ 1
+#define HSUART_DSR_MSK 0x00000020
+#define HSUART_DSR_I_MSK 0xffffffdf
+#define HSUART_DSR_SFT 5
+#define HSUART_DSR_HI 5
+#define HSUART_DSR_SZ 1
+#define HSUART_RI_MSK 0x00000040
+#define HSUART_RI_I_MSK 0xffffffbf
+#define HSUART_RI_SFT 6
+#define HSUART_RI_HI 6
+#define HSUART_RI_SZ 1
+#define HSUART_DCR_MSK 0x00000080
+#define HSUART_DCR_I_MSK 0xffffff7f
+#define HSUART_DCR_SFT 7
+#define HSUART_DCR_HI 7
+#define HSUART_DCR_SZ 1
+#define HSUART_SCR_MSK 0x000000ff
+#define HSUART_SCR_I_MSK 0xffffff00
+#define HSUART_SCR_SFT 0
+#define HSUART_SCR_HI 7
+#define HSUART_SCR_SZ 8
+#define HSUART_RTS_AUTO_TH_L_MSK 0x0000001f
+#define HSUART_RTS_AUTO_TH_L_I_MSK 0xffffffe0
+#define HSUART_RTS_AUTO_TH_L_SFT 0
+#define HSUART_RTS_AUTO_TH_L_HI 4
+#define HSUART_RTS_AUTO_TH_L_SZ 5
+#define HSUART_RTS_AUTO_TH_H_MSK 0x00001f00
+#define HSUART_RTS_AUTO_TH_H_I_MSK 0xffffe0ff
+#define HSUART_RTS_AUTO_TH_H_SFT 8
+#define HSUART_RTS_AUTO_TH_H_HI 12
+#define HSUART_RTS_AUTO_TH_H_SZ 5
+#define HSUART_TX_THR_L_MSK 0x001f0000
+#define HSUART_TX_THR_L_I_MSK 0xffe0ffff
+#define HSUART_TX_THR_L_SFT 16
+#define HSUART_TX_THR_L_HI 20
+#define HSUART_TX_THR_L_SZ 5
+#define HSUART_TX_THR_H_MSK 0x1f000000
+#define HSUART_TX_THR_H_I_MSK 0xe0ffffff
+#define HSUART_TX_THR_H_SFT 24
+#define HSUART_TX_THR_H_HI 28
+#define HSUART_TX_THR_H_SZ 5
+#define HSUART_IIR_MSK 0x0000000f
+#define HSUART_IIR_I_MSK 0xfffffff0
+#define HSUART_IIR_SFT 0
+#define HSUART_IIR_HI 3
+#define HSUART_IIR_SZ 4
+#define HSUART_TXDMA_DONE_MSK 0x00000020
+#define HSUART_TXDMA_DONE_I_MSK 0xffffffdf
+#define HSUART_TXDMA_DONE_SFT 5
+#define HSUART_TXDMA_DONE_HI 5
+#define HSUART_TXDMA_DONE_SZ 1
+#define HSUART_IFOFOE0_MSK 0x00000040
+#define HSUART_IFOFOE0_I_MSK 0xffffffbf
+#define HSUART_IFOFOE0_SFT 6
+#define HSUART_IFOFOE0_HI 6
+#define HSUART_IFOFOE0_SZ 1
+#define HSUART_IFIFOE1_MSK 0x00000080
+#define HSUART_IFIFOE1_I_MSK 0xffffff7f
+#define HSUART_IFIFOE1_SFT 7
+#define HSUART_IFIFOE1_HI 7
+#define HSUART_IFIFOE1_SZ 1
+#define HSUART_DIV_MSK 0x0000ffff
+#define HSUART_DIV_I_MSK 0xffff0000
+#define HSUART_DIV_SFT 0
+#define HSUART_DIV_HI 15
+#define HSUART_DIV_SZ 16
+#define HSUART_FRAC_MSK 0x00ff0000
+#define HSUART_FRAC_I_MSK 0xff00ffff
+#define HSUART_FRAC_SFT 16
+#define HSUART_FRAC_HI 23
+#define HSUART_FRAC_SZ 8
+#define HSUART_INT_MSK 0x0000ffff
+#define HSUART_INT_I_MSK 0xffff0000
+#define HSUART_INT_SFT 0
+#define HSUART_INT_HI 15
+#define HSUART_INT_SZ 16
+#define HSUART_DMA_RX_STR_ADDR_MSK 0xffffffff
+#define HSUART_DMA_RX_STR_ADDR_I_MSK 0x00000000
+#define HSUART_DMA_RX_STR_ADDR_SFT 0
+#define HSUART_DMA_RX_STR_ADDR_HI 31
+#define HSUART_DMA_RX_STR_ADDR_SZ 32
+#define HSUART_DMA_RX_END_ADDR_MSK 0xffffffff
+#define HSUART_DMA_RX_END_ADDR_I_MSK 0x00000000
+#define HSUART_DMA_RX_END_ADDR_SFT 0
+#define HSUART_DMA_RX_END_ADDR_HI 31
+#define HSUART_DMA_RX_END_ADDR_SZ 32
+#define HSUART_DMA_RX_WPT_MSK 0xffffffff
+#define HSUART_DMA_RX_WPT_I_MSK 0x00000000
+#define HSUART_DMA_RX_WPT_SFT 0
+#define HSUART_DMA_RX_WPT_HI 31
+#define HSUART_DMA_RX_WPT_SZ 32
+#define HSUART_DMA_RX_RPT_MSK 0xffffffff
+#define HSUART_DMA_RX_RPT_I_MSK 0x00000000
+#define HSUART_DMA_RX_RPT_SFT 0
+#define HSUART_DMA_RX_RPT_HI 31
+#define HSUART_DMA_RX_RPT_SZ 32
+#define HSUART_DMA_TX_STR_ADDR_MSK 0xffffffff
+#define HSUART_DMA_TX_STR_ADDR_I_MSK 0x00000000
+#define HSUART_DMA_TX_STR_ADDR_SFT 0
+#define HSUART_DMA_TX_STR_ADDR_HI 31
+#define HSUART_DMA_TX_STR_ADDR_SZ 32
+#define HSUART_DMA_TX_END_ADDR_MSK 0xffffffff
+#define HSUART_DMA_TX_END_ADDR_I_MSK 0x00000000
+#define HSUART_DMA_TX_END_ADDR_SFT 0
+#define HSUART_DMA_TX_END_ADDR_HI 31
+#define HSUART_DMA_TX_END_ADDR_SZ 32
+#define HSUART_DMA_TX_WPT_MSK 0xffffffff
+#define HSUART_DMA_TX_WPT_I_MSK 0x00000000
+#define HSUART_DMA_TX_WPT_SFT 0
+#define HSUART_DMA_TX_WPT_HI 31
+#define HSUART_DMA_TX_WPT_SZ 32
+#define HSUART_DMA_TX_RPT_MSK 0xffffffff
+#define HSUART_DMA_TX_RPT_I_MSK 0x00000000
+#define HSUART_DMA_TX_RPT_SFT 0
+#define HSUART_DMA_TX_RPT_HI 31
+#define HSUART_DMA_TX_RPT_SZ 32
+#define MANUAL_T_ADDR_MSK 0xffffffff
+#define MANUAL_T_ADDR_I_MSK 0x00000000
+#define MANUAL_T_ADDR_SFT 0
+#define MANUAL_T_ADDR_HI 31
+#define MANUAL_T_ADDR_SZ 32
+#define MANUAL_R_ADDR_MSK 0xffffffff
+#define MANUAL_R_ADDR_I_MSK 0x00000000
+#define MANUAL_R_ADDR_SFT 0
+#define MANUAL_R_ADDR_HI 31
+#define MANUAL_R_ADDR_SZ 32
+#define FLASH_FRONT_DLY_MSK 0x0000000f
+#define FLASH_FRONT_DLY_I_MSK 0xfffffff0
+#define FLASH_FRONT_DLY_SFT 0
+#define FLASH_FRONT_DLY_HI 3
+#define FLASH_FRONT_DLY_SZ 4
+#define FLASH_BACK_DLY_MSK 0x000000f0
+#define FLASH_BACK_DLY_I_MSK 0xffffff0f
+#define FLASH_BACK_DLY_SFT 4
+#define FLASH_BACK_DLY_HI 7
+#define FLASH_BACK_DLY_SZ 4
+#define CSN_DLY_MSK 0x00000f00
+#define CSN_DLY_I_MSK 0xfffff0ff
+#define CSN_DLY_SFT 8
+#define CSN_DLY_HI 11
+#define CSN_DLY_SZ 4
+#define INDICATOR_MSK 0x000ff000
+#define INDICATOR_I_MSK 0xfff00fff
+#define INDICATOR_SFT 12
+#define INDICATOR_HI 19
+#define INDICATOR_SZ 8
+#define DUMY_DLY_MSK 0x00f00000
+#define DUMY_DLY_I_MSK 0xff0fffff
+#define DUMY_DLY_SFT 20
+#define DUMY_DLY_HI 23
+#define DUMY_DLY_SZ 4
+#define MEM_SEL_MSK 0x01000000
+#define MEM_SEL_I_MSK 0xfeffffff
+#define MEM_SEL_SFT 24
+#define MEM_SEL_HI 24
+#define MEM_SEL_SZ 1
+#define SPI_BUSY_MSK 0x00000001
+#define SPI_BUSY_I_MSK 0xfffffffe
+#define SPI_BUSY_SFT 0
+#define SPI_BUSY_HI 0
+#define SPI_BUSY_SZ 1
+#define SPI_FLASH_MODE_MSK 0x00000006
+#define SPI_FLASH_MODE_I_MSK 0xfffffff9
+#define SPI_FLASH_MODE_SFT 1
+#define SPI_FLASH_MODE_HI 2
+#define SPI_FLASH_MODE_SZ 2
+#define MANUAL_MODE_BUSY_MSK 0x00000008
+#define MANUAL_MODE_BUSY_I_MSK 0xfffffff7
+#define MANUAL_MODE_BUSY_SFT 3
+#define MANUAL_MODE_BUSY_HI 3
+#define MANUAL_MODE_BUSY_SZ 1
+#define PREFETCH_EN_MSK 0x00000010
+#define PREFETCH_EN_I_MSK 0xffffffef
+#define PREFETCH_EN_SFT 4
+#define PREFETCH_EN_HI 4
+#define PREFETCH_EN_SZ 1
+#define WRAP_EN_MSK 0x00000020
+#define WRAP_EN_I_MSK 0xffffffdf
+#define WRAP_EN_SFT 5
+#define WRAP_EN_HI 5
+#define WRAP_EN_SZ 1
+#define CONTINUE_R_EN_MSK 0x00000040
+#define CONTINUE_R_EN_I_MSK 0xffffffbf
+#define CONTINUE_R_EN_SFT 6
+#define CONTINUE_R_EN_HI 6
+#define CONTINUE_R_EN_SZ 1
+#define MANUAL_T_LEN_MSK 0x0000ffff
+#define MANUAL_T_LEN_I_MSK 0xffff0000
+#define MANUAL_T_LEN_SFT 0
+#define MANUAL_T_LEN_HI 15
+#define MANUAL_T_LEN_SZ 16
+#define MANUAL_R_LEN_MSK 0x0000ffff
+#define MANUAL_R_LEN_I_MSK 0xffff0000
+#define MANUAL_R_LEN_SFT 0
+#define MANUAL_R_LEN_HI 15
+#define MANUAL_R_LEN_SZ 16
+#define BIT1_WR_CMD_MSK 0x000000ff
+#define BIT1_WR_CMD_I_MSK 0xffffff00
+#define BIT1_WR_CMD_SFT 0
+#define BIT1_WR_CMD_HI 7
+#define BIT1_WR_CMD_SZ 8
+#define BIT1_RD_CMD_MSK 0x0000ff00
+#define BIT1_RD_CMD_I_MSK 0xffff00ff
+#define BIT1_RD_CMD_SFT 8
+#define BIT1_RD_CMD_HI 15
+#define BIT1_RD_CMD_SZ 8
+#define BIT2_RD_CMD_MSK 0x00ff0000
+#define BIT2_RD_CMD_I_MSK 0xff00ffff
+#define BIT2_RD_CMD_SFT 16
+#define BIT2_RD_CMD_HI 23
+#define BIT2_RD_CMD_SZ 8
+#define BIT4_RD_CMD_MSK 0xff000000
+#define BIT4_RD_CMD_I_MSK 0x00ffffff
+#define BIT4_RD_CMD_SFT 24
+#define BIT4_RD_CMD_HI 31
+#define BIT4_RD_CMD_SZ 8
+#define BIT4_WR_CMD_MSK 0x000000ff
+#define BIT4_WR_CMD_I_MSK 0xffffff00
+#define BIT4_WR_CMD_SFT 0
+#define BIT4_WR_CMD_HI 7
+#define BIT4_WR_CMD_SZ 8
+#define FLS_CLK_IN_DLY_SEL_MSK 0x00000007
+#define FLS_CLK_IN_DLY_SEL_I_MSK 0xfffffff8
+#define FLS_CLK_IN_DLY_SEL_SFT 0
+#define FLS_CLK_IN_DLY_SEL_HI 2
+#define FLS_CLK_IN_DLY_SEL_SZ 3
+#define FLS_CLK_OUT_DLY_SEL_MSK 0x00000070
+#define FLS_CLK_OUT_DLY_SEL_I_MSK 0xffffff8f
+#define FLS_CLK_OUT_DLY_SEL_SFT 4
+#define FLS_CLK_OUT_DLY_SEL_HI 6
+#define FLS_CLK_OUT_DLY_SEL_SZ 3
+#define FLS_MOSI_IN_DLY_SEL_MSK 0x00000700
+#define FLS_MOSI_IN_DLY_SEL_I_MSK 0xfffff8ff
+#define FLS_MOSI_IN_DLY_SEL_SFT 8
+#define FLS_MOSI_IN_DLY_SEL_HI 10
+#define FLS_MOSI_IN_DLY_SEL_SZ 3
+#define FLS_MOSI_OUT_DLY_SEL_MSK 0x00007000
+#define FLS_MOSI_OUT_DLY_SEL_I_MSK 0xffff8fff
+#define FLS_MOSI_OUT_DLY_SEL_SFT 12
+#define FLS_MOSI_OUT_DLY_SEL_HI 14
+#define FLS_MOSI_OUT_DLY_SEL_SZ 3
+#define FLS_MISO_IN_DLY_SEL_MSK 0x00070000
+#define FLS_MISO_IN_DLY_SEL_I_MSK 0xfff8ffff
+#define FLS_MISO_IN_DLY_SEL_SFT 16
+#define FLS_MISO_IN_DLY_SEL_HI 18
+#define FLS_MISO_IN_DLY_SEL_SZ 3
+#define FLS_MISO_OUT_DLY_SEL_MSK 0x00700000
+#define FLS_MISO_OUT_DLY_SEL_I_MSK 0xff8fffff
+#define FLS_MISO_OUT_DLY_SEL_SFT 20
+#define FLS_MISO_OUT_DLY_SEL_HI 22
+#define FLS_MISO_OUT_DLY_SEL_SZ 3
+#define FLS_WP_IN_DLY_SEL_MSK 0x07000000
+#define FLS_WP_IN_DLY_SEL_I_MSK 0xf8ffffff
+#define FLS_WP_IN_DLY_SEL_SFT 24
+#define FLS_WP_IN_DLY_SEL_HI 26
+#define FLS_WP_IN_DLY_SEL_SZ 3
+#define FLS_WP_OUT_DLY_SEL_MSK 0x70000000
+#define FLS_WP_OUT_DLY_SEL_I_MSK 0x8fffffff
+#define FLS_WP_OUT_DLY_SEL_SFT 28
+#define FLS_WP_OUT_DLY_SEL_HI 30
+#define FLS_WP_OUT_DLY_SEL_SZ 3
+#define FLS_NC_IN_DLY_SEL_MSK 0x00000007
+#define FLS_NC_IN_DLY_SEL_I_MSK 0xfffffff8
+#define FLS_NC_IN_DLY_SEL_SFT 0
+#define FLS_NC_IN_DLY_SEL_HI 2
+#define FLS_NC_IN_DLY_SEL_SZ 3
+#define FLS_NC_OUT_DLY_SEL_MSK 0x00000070
+#define FLS_NC_OUT_DLY_SEL_I_MSK 0xffffff8f
+#define FLS_NC_OUT_DLY_SEL_SFT 4
+#define FLS_NC_OUT_DLY_SEL_HI 6
+#define FLS_NC_OUT_DLY_SEL_SZ 3
+#define SPI_F_MISO_CLK_SEL_MSK 0x00000100
+#define SPI_F_MISO_CLK_SEL_I_MSK 0xfffffeff
+#define SPI_F_MISO_CLK_SEL_SFT 8
+#define SPI_F_MISO_CLK_SEL_HI 8
+#define SPI_F_MISO_CLK_SEL_SZ 1
+#define INS_START_ADDR_MSK 0x00ffffff
+#define INS_START_ADDR_I_MSK 0xff000000
+#define INS_START_ADDR_SFT 0
+#define INS_START_ADDR_HI 23
+#define INS_START_ADDR_SZ 24
+#define INS_END_ADDR_MSK 0x00ffffff
+#define INS_END_ADDR_I_MSK 0xff000000
+#define INS_END_ADDR_SFT 0
+#define INS_END_ADDR_HI 23
+#define INS_END_ADDR_SZ 24
+#define INS_BUF_CLR_MSK 0x00000001
+#define INS_BUF_CLR_I_MSK 0xfffffffe
+#define INS_BUF_CLR_SFT 0
+#define INS_BUF_CLR_HI 0
+#define INS_BUF_CLR_SZ 1
+#define RW_BUF_CLR_MSK 0x00000002
+#define RW_BUF_CLR_I_MSK 0xfffffffd
+#define RW_BUF_CLR_SFT 1
+#define RW_BUF_CLR_HI 1
+#define RW_BUF_CLR_SZ 1
+#define ERR_FLAG_CLR_MSK 0x00000004
+#define ERR_FLAG_CLR_I_MSK 0xfffffffb
+#define ERR_FLAG_CLR_SFT 2
+#define ERR_FLAG_CLR_HI 2
+#define ERR_FLAG_CLR_SZ 1
+#define DMA_ADR_SRC_MSK 0xffffffff
+#define DMA_ADR_SRC_I_MSK 0x00000000
+#define DMA_ADR_SRC_SFT 0
+#define DMA_ADR_SRC_HI 31
+#define DMA_ADR_SRC_SZ 32
+#define DMA_ADR_DST_MSK 0xffffffff
+#define DMA_ADR_DST_I_MSK 0x00000000
+#define DMA_ADR_DST_SFT 0
+#define DMA_ADR_DST_HI 31
+#define DMA_ADR_DST_SZ 32
+#define DMA_SRC_SIZE_MSK 0x00000007
+#define DMA_SRC_SIZE_I_MSK 0xfffffff8
+#define DMA_SRC_SIZE_SFT 0
+#define DMA_SRC_SIZE_HI 2
+#define DMA_SRC_SIZE_SZ 3
+#define DMA_SRC_INC_MSK 0x00000008
+#define DMA_SRC_INC_I_MSK 0xfffffff7
+#define DMA_SRC_INC_SFT 3
+#define DMA_SRC_INC_HI 3
+#define DMA_SRC_INC_SZ 1
+#define DMA_DST_SIZE_MSK 0x00000070
+#define DMA_DST_SIZE_I_MSK 0xffffff8f
+#define DMA_DST_SIZE_SFT 4
+#define DMA_DST_SIZE_HI 6
+#define DMA_DST_SIZE_SZ 3
+#define DMA_DST_INC_MSK 0x00000080
+#define DMA_DST_INC_I_MSK 0xffffff7f
+#define DMA_DST_INC_SFT 7
+#define DMA_DST_INC_HI 7
+#define DMA_DST_INC_SZ 1
+#define DMA_FAST_FILL_MSK 0x00000100
+#define DMA_FAST_FILL_I_MSK 0xfffffeff
+#define DMA_FAST_FILL_SFT 8
+#define DMA_FAST_FILL_HI 8
+#define DMA_FAST_FILL_SZ 1
+#define DMA_SDIO_KICK_MSK 0x00001000
+#define DMA_SDIO_KICK_I_MSK 0xffffefff
+#define DMA_SDIO_KICK_SFT 12
+#define DMA_SDIO_KICK_HI 12
+#define DMA_SDIO_KICK_SZ 1
+#define DMA_BADR_EN_MSK 0x00002000
+#define DMA_BADR_EN_I_MSK 0xffffdfff
+#define DMA_BADR_EN_SFT 13
+#define DMA_BADR_EN_HI 13
+#define DMA_BADR_EN_SZ 1
+#define DMA_LEN_MSK 0xffff0000
+#define DMA_LEN_I_MSK 0x0000ffff
+#define DMA_LEN_SFT 16
+#define DMA_LEN_HI 31
+#define DMA_LEN_SZ 16
+#define DMA_INT_MASK_MSK 0x00000001
+#define DMA_INT_MASK_I_MSK 0xfffffffe
+#define DMA_INT_MASK_SFT 0
+#define DMA_INT_MASK_HI 0
+#define DMA_INT_MASK_SZ 1
+#define DMA_STS_MSK 0x00000100
+#define DMA_STS_I_MSK 0xfffffeff
+#define DMA_STS_SFT 8
+#define DMA_STS_HI 8
+#define DMA_STS_SZ 1
+#define DMA_FINISH_MSK 0x80000000
+#define DMA_FINISH_I_MSK 0x7fffffff
+#define DMA_FINISH_SFT 31
+#define DMA_FINISH_HI 31
+#define DMA_FINISH_SZ 1
+#define DMA_CONST_MSK 0xffffffff
+#define DMA_CONST_I_MSK 0x00000000
+#define DMA_CONST_SFT 0
+#define DMA_CONST_HI 31
+#define DMA_CONST_SZ 32
+#define D2_DMA_ADR_SRC_MSK 0xffffffff
+#define D2_DMA_ADR_SRC_I_MSK 0x00000000
+#define D2_DMA_ADR_SRC_SFT 0
+#define D2_DMA_ADR_SRC_HI 31
+#define D2_DMA_ADR_SRC_SZ 32
+#define D2_DMA_ADR_DST_MSK 0xffffffff
+#define D2_DMA_ADR_DST_I_MSK 0x00000000
+#define D2_DMA_ADR_DST_SFT 0
+#define D2_DMA_ADR_DST_HI 31
+#define D2_DMA_ADR_DST_SZ 32
+#define D2_DMA_SRC_SIZE_MSK 0x00000007
+#define D2_DMA_SRC_SIZE_I_MSK 0xfffffff8
+#define D2_DMA_SRC_SIZE_SFT 0
+#define D2_DMA_SRC_SIZE_HI 2
+#define D2_DMA_SRC_SIZE_SZ 3
+#define D2_DMA_SRC_INC_MSK 0x00000008
+#define D2_DMA_SRC_INC_I_MSK 0xfffffff7
+#define D2_DMA_SRC_INC_SFT 3
+#define D2_DMA_SRC_INC_HI 3
+#define D2_DMA_SRC_INC_SZ 1
+#define D2_DMA_DST_SIZE_MSK 0x00000070
+#define D2_DMA_DST_SIZE_I_MSK 0xffffff8f
+#define D2_DMA_DST_SIZE_SFT 4
+#define D2_DMA_DST_SIZE_HI 6
+#define D2_DMA_DST_SIZE_SZ 3
+#define D2_DMA_DST_INC_MSK 0x00000080
+#define D2_DMA_DST_INC_I_MSK 0xffffff7f
+#define D2_DMA_DST_INC_SFT 7
+#define D2_DMA_DST_INC_HI 7
+#define D2_DMA_DST_INC_SZ 1
+#define D2_DMA_FAST_FILL_MSK 0x00000100
+#define D2_DMA_FAST_FILL_I_MSK 0xfffffeff
+#define D2_DMA_FAST_FILL_SFT 8
+#define D2_DMA_FAST_FILL_HI 8
+#define D2_DMA_FAST_FILL_SZ 1
+#define D2_DMA_SDIO_KICK_MSK 0x00001000
+#define D2_DMA_SDIO_KICK_I_MSK 0xffffefff
+#define D2_DMA_SDIO_KICK_SFT 12
+#define D2_DMA_SDIO_KICK_HI 12
+#define D2_DMA_SDIO_KICK_SZ 1
+#define D2_DMA_BADR_EN_MSK 0x00002000
+#define D2_DMA_BADR_EN_I_MSK 0xffffdfff
+#define D2_DMA_BADR_EN_SFT 13
+#define D2_DMA_BADR_EN_HI 13
+#define D2_DMA_BADR_EN_SZ 1
+#define D2_DMA_LEN_MSK 0xffff0000
+#define D2_DMA_LEN_I_MSK 0x0000ffff
+#define D2_DMA_LEN_SFT 16
+#define D2_DMA_LEN_HI 31
+#define D2_DMA_LEN_SZ 16
+#define D2_DMA_INT_MASK_MSK 0x00000001
+#define D2_DMA_INT_MASK_I_MSK 0xfffffffe
+#define D2_DMA_INT_MASK_SFT 0
+#define D2_DMA_INT_MASK_HI 0
+#define D2_DMA_INT_MASK_SZ 1
+#define D2_DMA_STS_MSK 0x00000100
+#define D2_DMA_STS_I_MSK 0xfffffeff
+#define D2_DMA_STS_SFT 8
+#define D2_DMA_STS_HI 8
+#define D2_DMA_STS_SZ 1
+#define D2_DMA_FINISH_MSK 0x80000000
+#define D2_DMA_FINISH_I_MSK 0x7fffffff
+#define D2_DMA_FINISH_SFT 31
+#define D2_DMA_FINISH_HI 31
+#define D2_DMA_FINISH_SZ 1
+#define D2_DMA_CONST_MSK 0xffffffff
+#define D2_DMA_CONST_I_MSK 0x00000000
+#define D2_DMA_CONST_SFT 0
+#define D2_DMA_CONST_HI 31
+#define D2_DMA_CONST_SZ 32
+#define MASK_TYPHOST_INT_MAP_02_MSK 0xffffffff
+#define MASK_TYPHOST_INT_MAP_02_I_MSK 0x00000000
+#define MASK_TYPHOST_INT_MAP_02_SFT 0
+#define MASK_TYPHOST_INT_MAP_02_HI 31
+#define MASK_TYPHOST_INT_MAP_02_SZ 32
+#define RAW_TYPHOST_INT_MAP_02_MSK 0xffffffff
+#define RAW_TYPHOST_INT_MAP_02_I_MSK 0x00000000
+#define RAW_TYPHOST_INT_MAP_02_SFT 0
+#define RAW_TYPHOST_INT_MAP_02_HI 31
+#define RAW_TYPHOST_INT_MAP_02_SZ 32
+#define POSTMASK_TYPHOST_INT_MAP_02_MSK 0xffffffff
+#define POSTMASK_TYPHOST_INT_MAP_02_I_MSK 0x00000000
+#define POSTMASK_TYPHOST_INT_MAP_02_SFT 0
+#define POSTMASK_TYPHOST_INT_MAP_02_HI 31
+#define POSTMASK_TYPHOST_INT_MAP_02_SZ 32
+#define MASK_TYPHOST_INT_MAP_15_MSK 0xffffffff
+#define MASK_TYPHOST_INT_MAP_15_I_MSK 0x00000000
+#define MASK_TYPHOST_INT_MAP_15_SFT 0
+#define MASK_TYPHOST_INT_MAP_15_HI 31
+#define MASK_TYPHOST_INT_MAP_15_SZ 32
+#define RAW_TYPHOST_INT_MAP_15_MSK 0xffffffff
+#define RAW_TYPHOST_INT_MAP_15_I_MSK 0x00000000
+#define RAW_TYPHOST_INT_MAP_15_SFT 0
+#define RAW_TYPHOST_INT_MAP_15_HI 31
+#define RAW_TYPHOST_INT_MAP_15_SZ 32
+#define POSTMASK_TYPHOST_INT_MAP_15_MSK 0xffffffff
+#define POSTMASK_TYPHOST_INT_MAP_15_I_MSK 0x00000000
+#define POSTMASK_TYPHOST_INT_MAP_15_SFT 0
+#define POSTMASK_TYPHOST_INT_MAP_15_HI 31
+#define POSTMASK_TYPHOST_INT_MAP_15_SZ 32
+#define MASK_TYPHOST_INT_MAP_31_MSK 0xffffffff
+#define MASK_TYPHOST_INT_MAP_31_I_MSK 0x00000000
+#define MASK_TYPHOST_INT_MAP_31_SFT 0
+#define MASK_TYPHOST_INT_MAP_31_HI 31
+#define MASK_TYPHOST_INT_MAP_31_SZ 32
+#define RAW_TYPHOST_INT_MAP_31_MSK 0xffffffff
+#define RAW_TYPHOST_INT_MAP_31_I_MSK 0x00000000
+#define RAW_TYPHOST_INT_MAP_31_SFT 0
+#define RAW_TYPHOST_INT_MAP_31_HI 31
+#define RAW_TYPHOST_INT_MAP_31_SZ 32
+#define POSTMASK_TYPHOST_INT_MAP_31_MSK 0xffffffff
+#define POSTMASK_TYPHOST_INT_MAP_31_I_MSK 0x00000000
+#define POSTMASK_TYPHOST_INT_MAP_31_SFT 0
+#define POSTMASK_TYPHOST_INT_MAP_31_HI 31
+#define POSTMASK_TYPHOST_INT_MAP_31_SZ 32
+#define MASK_TYPHOST_INT_MAP_MSK 0xffffffff
+#define MASK_TYPHOST_INT_MAP_I_MSK 0x00000000
+#define MASK_TYPHOST_INT_MAP_SFT 0
+#define MASK_TYPHOST_INT_MAP_HI 31
+#define MASK_TYPHOST_INT_MAP_SZ 32
+#define RAW_TYPHOST_INT_MAP_MSK 0xffffffff
+#define RAW_TYPHOST_INT_MAP_I_MSK 0x00000000
+#define RAW_TYPHOST_INT_MAP_SFT 0
+#define RAW_TYPHOST_INT_MAP_HI 31
+#define RAW_TYPHOST_INT_MAP_SZ 32
+#define POSTMASK_TYPHOST_INT_MAP_MSK 0xffffffff
+#define POSTMASK_TYPHOST_INT_MAP_I_MSK 0x00000000
+#define POSTMASK_TYPHOST_INT_MAP_SFT 0
+#define POSTMASK_TYPHOST_INT_MAP_HI 31
+#define POSTMASK_TYPHOST_INT_MAP_SZ 32
+#define SUMMARY_TYPHOST_INT_MAP_MSK 0x00000001
+#define SUMMARY_TYPHOST_INT_MAP_I_MSK 0xfffffffe
+#define SUMMARY_TYPHOST_INT_MAP_SFT 0
+#define SUMMARY_TYPHOST_INT_MAP_HI 0
+#define SUMMARY_TYPHOST_INT_MAP_SZ 1
+#define MASK_TYPMCU_INT_MAP_02_MSK 0xffffffff
+#define MASK_TYPMCU_INT_MAP_02_I_MSK 0x00000000
+#define MASK_TYPMCU_INT_MAP_02_SFT 0
+#define MASK_TYPMCU_INT_MAP_02_HI 31
+#define MASK_TYPMCU_INT_MAP_02_SZ 32
+#define RAW_TYPMCU_INT_MAP_02_MSK 0xffffffff
+#define RAW_TYPMCU_INT_MAP_02_I_MSK 0x00000000
+#define RAW_TYPMCU_INT_MAP_02_SFT 0
+#define RAW_TYPMCU_INT_MAP_02_HI 31
+#define RAW_TYPMCU_INT_MAP_02_SZ 32
+#define POSTMASK_TYPMCU_INT_MAP_02_MSK 0xffffffff
+#define POSTMASK_TYPMCU_INT_MAP_02_I_MSK 0x00000000
+#define POSTMASK_TYPMCU_INT_MAP_02_SFT 0
+#define POSTMASK_TYPMCU_INT_MAP_02_HI 31
+#define POSTMASK_TYPMCU_INT_MAP_02_SZ 32
+#define MASK_TYPMCU_INT_MAP_15_MSK 0xffffffff
+#define MASK_TYPMCU_INT_MAP_15_I_MSK 0x00000000
+#define MASK_TYPMCU_INT_MAP_15_SFT 0
+#define MASK_TYPMCU_INT_MAP_15_HI 31
+#define MASK_TYPMCU_INT_MAP_15_SZ 32
+#define RAW_TYPMCU_INT_MAP_15_MSK 0xffffffff
+#define RAW_TYPMCU_INT_MAP_15_I_MSK 0x00000000
+#define RAW_TYPMCU_INT_MAP_15_SFT 0
+#define RAW_TYPMCU_INT_MAP_15_HI 31
+#define RAW_TYPMCU_INT_MAP_15_SZ 32
+#define POSTMASK_TYPMCU_INT_MAP_15_MSK 0xffffffff
+#define POSTMASK_TYPMCU_INT_MAP_15_I_MSK 0x00000000
+#define POSTMASK_TYPMCU_INT_MAP_15_SFT 0
+#define POSTMASK_TYPMCU_INT_MAP_15_HI 31
+#define POSTMASK_TYPMCU_INT_MAP_15_SZ 32
+#define MASK_TYPMCU_INT_MAP_31_MSK 0xffffffff
+#define MASK_TYPMCU_INT_MAP_31_I_MSK 0x00000000
+#define MASK_TYPMCU_INT_MAP_31_SFT 0
+#define MASK_TYPMCU_INT_MAP_31_HI 31
+#define MASK_TYPMCU_INT_MAP_31_SZ 32
+#define RAW_TYPMCU_INT_MAP_31_MSK 0xffffffff
+#define RAW_TYPMCU_INT_MAP_31_I_MSK 0x00000000
+#define RAW_TYPMCU_INT_MAP_31_SFT 0
+#define RAW_TYPMCU_INT_MAP_31_HI 31
+#define RAW_TYPMCU_INT_MAP_31_SZ 32
+#define POSTMASK_TYPMCU_INT_MAP_31_MSK 0xffffffff
+#define POSTMASK_TYPMCU_INT_MAP_31_I_MSK 0x00000000
+#define POSTMASK_TYPMCU_INT_MAP_31_SFT 0
+#define POSTMASK_TYPMCU_INT_MAP_31_HI 31
+#define POSTMASK_TYPMCU_INT_MAP_31_SZ 32
+#define MASK_TYPMCU_INT_MAP_MSK 0xffffffff
+#define MASK_TYPMCU_INT_MAP_I_MSK 0x00000000
+#define MASK_TYPMCU_INT_MAP_SFT 0
+#define MASK_TYPMCU_INT_MAP_HI 31
+#define MASK_TYPMCU_INT_MAP_SZ 32
+#define RAW_TYPMCU_INT_MAP_MSK 0xffffffff
+#define RAW_TYPMCU_INT_MAP_I_MSK 0x00000000
+#define RAW_TYPMCU_INT_MAP_SFT 0
+#define RAW_TYPMCU_INT_MAP_HI 31
+#define RAW_TYPMCU_INT_MAP_SZ 32
+#define POSTMASK_TYPMCU_INT_MAP_MSK 0xffffffff
+#define POSTMASK_TYPMCU_INT_MAP_I_MSK 0x00000000
+#define POSTMASK_TYPMCU_INT_MAP_SFT 0
+#define POSTMASK_TYPMCU_INT_MAP_HI 31
+#define POSTMASK_TYPMCU_INT_MAP_SZ 32
+#define SUMMARY_TYPMCU_INT_MAP_MSK 0x00000001
+#define SUMMARY_TYPMCU_INT_MAP_I_MSK 0xfffffffe
+#define SUMMARY_TYPMCU_INT_MAP_SFT 0
+#define SUMMARY_TYPMCU_INT_MAP_HI 0
+#define SUMMARY_TYPMCU_INT_MAP_SZ 1
+#define INT_GPI_SUB_00_MSK 0x0000000f
+#define INT_GPI_SUB_00_I_MSK 0xfffffff0
+#define INT_GPI_SUB_00_SFT 0
+#define INT_GPI_SUB_00_HI 3
+#define INT_GPI_SUB_00_SZ 4
+#define INT_GPI_SUB_01_MSK 0x000000f0
+#define INT_GPI_SUB_01_I_MSK 0xffffff0f
+#define INT_GPI_SUB_01_SFT 4
+#define INT_GPI_SUB_01_HI 7
+#define INT_GPI_SUB_01_SZ 4
+#define INT_GPI_SUB_02_MSK 0x00000f00
+#define INT_GPI_SUB_02_I_MSK 0xfffff0ff
+#define INT_GPI_SUB_02_SFT 8
+#define INT_GPI_SUB_02_HI 11
+#define INT_GPI_SUB_02_SZ 4
+#define INT_GPI_SUB_03_MSK 0x0000f000
+#define INT_GPI_SUB_03_I_MSK 0xffff0fff
+#define INT_GPI_SUB_03_SFT 12
+#define INT_GPI_SUB_03_HI 15
+#define INT_GPI_SUB_03_SZ 4
+#define INT_GPI_SUB_04_MSK 0x000f0000
+#define INT_GPI_SUB_04_I_MSK 0xfff0ffff
+#define INT_GPI_SUB_04_SFT 16
+#define INT_GPI_SUB_04_HI 19
+#define INT_GPI_SUB_04_SZ 4
+#define INT_GPI_SUB_05_MSK 0x00f00000
+#define INT_GPI_SUB_05_I_MSK 0xff0fffff
+#define INT_GPI_SUB_05_SFT 20
+#define INT_GPI_SUB_05_HI 23
+#define INT_GPI_SUB_05_SZ 4
+#define INT_GPI_SUB_06_MSK 0x0f000000
+#define INT_GPI_SUB_06_I_MSK 0xf0ffffff
+#define INT_GPI_SUB_06_SFT 24
+#define INT_GPI_SUB_06_HI 27
+#define INT_GPI_SUB_06_SZ 4
+#define INT_GPI_SUB_07_MSK 0xf0000000
+#define INT_GPI_SUB_07_I_MSK 0x0fffffff
+#define INT_GPI_SUB_07_SFT 28
+#define INT_GPI_SUB_07_HI 31
+#define INT_GPI_SUB_07_SZ 4
+#define INT_GPI_SUB_08_MSK 0x0000000f
+#define INT_GPI_SUB_08_I_MSK 0xfffffff0
+#define INT_GPI_SUB_08_SFT 0
+#define INT_GPI_SUB_08_HI 3
+#define INT_GPI_SUB_08_SZ 4
+#define INT_GPI_SUB_09_MSK 0x000000f0
+#define INT_GPI_SUB_09_I_MSK 0xffffff0f
+#define INT_GPI_SUB_09_SFT 4
+#define INT_GPI_SUB_09_HI 7
+#define INT_GPI_SUB_09_SZ 4
+#define INT_GPI_SUB_10_MSK 0x00000f00
+#define INT_GPI_SUB_10_I_MSK 0xfffff0ff
+#define INT_GPI_SUB_10_SFT 8
+#define INT_GPI_SUB_10_HI 11
+#define INT_GPI_SUB_10_SZ 4
+#define INT_GPI_SUB_11_MSK 0x0000f000
+#define INT_GPI_SUB_11_I_MSK 0xffff0fff
+#define INT_GPI_SUB_11_SFT 12
+#define INT_GPI_SUB_11_HI 15
+#define INT_GPI_SUB_11_SZ 4
+#define INT_GPI_SUB_12_MSK 0x000f0000
+#define INT_GPI_SUB_12_I_MSK 0xfff0ffff
+#define INT_GPI_SUB_12_SFT 16
+#define INT_GPI_SUB_12_HI 19
+#define INT_GPI_SUB_12_SZ 4
+#define INT_GPI_SUB_13_MSK 0x00f00000
+#define INT_GPI_SUB_13_I_MSK 0xff0fffff
+#define INT_GPI_SUB_13_SFT 20
+#define INT_GPI_SUB_13_HI 23
+#define INT_GPI_SUB_13_SZ 4
+#define INT_GPI_SUB_14_MSK 0x0f000000
+#define INT_GPI_SUB_14_I_MSK 0xf0ffffff
+#define INT_GPI_SUB_14_SFT 24
+#define INT_GPI_SUB_14_HI 27
+#define INT_GPI_SUB_14_SZ 4
+#define INT_GPI_SUB_15_MSK 0xf0000000
+#define INT_GPI_SUB_15_I_MSK 0x0fffffff
+#define INT_GPI_SUB_15_SFT 28
+#define INT_GPI_SUB_15_HI 31
+#define INT_GPI_SUB_15_SZ 4
+#define INT_GPI_SUB_16_MSK 0x0000000f
+#define INT_GPI_SUB_16_I_MSK 0xfffffff0
+#define INT_GPI_SUB_16_SFT 0
+#define INT_GPI_SUB_16_HI 3
+#define INT_GPI_SUB_16_SZ 4
+#define INT_GPI_SUB_17_MSK 0x000000f0
+#define INT_GPI_SUB_17_I_MSK 0xffffff0f
+#define INT_GPI_SUB_17_SFT 4
+#define INT_GPI_SUB_17_HI 7
+#define INT_GPI_SUB_17_SZ 4
+#define INT_GPI_SUB_18_MSK 0x00000f00
+#define INT_GPI_SUB_18_I_MSK 0xfffff0ff
+#define INT_GPI_SUB_18_SFT 8
+#define INT_GPI_SUB_18_HI 11
+#define INT_GPI_SUB_18_SZ 4
+#define INT_GPI_SUB_19_MSK 0x0000f000
+#define INT_GPI_SUB_19_I_MSK 0xffff0fff
+#define INT_GPI_SUB_19_SFT 12
+#define INT_GPI_SUB_19_HI 15
+#define INT_GPI_SUB_19_SZ 4
+#define INT_GPI_SUB_20_MSK 0x000f0000
+#define INT_GPI_SUB_20_I_MSK 0xfff0ffff
+#define INT_GPI_SUB_20_SFT 16
+#define INT_GPI_SUB_20_HI 19
+#define INT_GPI_SUB_20_SZ 4
+#define INT_GPI_SUB_21_MSK 0x00f00000
+#define INT_GPI_SUB_21_I_MSK 0xff0fffff
+#define INT_GPI_SUB_21_SFT 20
+#define INT_GPI_SUB_21_HI 23
+#define INT_GPI_SUB_21_SZ 4
+#define INT_GPI_SUB_22_MSK 0x0f000000
+#define INT_GPI_SUB_22_I_MSK 0xf0ffffff
+#define INT_GPI_SUB_22_SFT 24
+#define INT_GPI_SUB_22_HI 27
+#define INT_GPI_SUB_22_SZ 4
+#define INT_GPI_MODE_00_MSK 0x00000007
+#define INT_GPI_MODE_00_I_MSK 0xfffffff8
+#define INT_GPI_MODE_00_SFT 0
+#define INT_GPI_MODE_00_HI 2
+#define INT_GPI_MODE_00_SZ 3
+#define INT_GPI_MODE_01_MSK 0x00000070
+#define INT_GPI_MODE_01_I_MSK 0xffffff8f
+#define INT_GPI_MODE_01_SFT 4
+#define INT_GPI_MODE_01_HI 6
+#define INT_GPI_MODE_01_SZ 3
+#define INT_GPI_MODE_02_MSK 0x00000700
+#define INT_GPI_MODE_02_I_MSK 0xfffff8ff
+#define INT_GPI_MODE_02_SFT 8
+#define INT_GPI_MODE_02_HI 10
+#define INT_GPI_MODE_02_SZ 3
+#define INT_GPI_MODE_03_MSK 0x00007000
+#define INT_GPI_MODE_03_I_MSK 0xffff8fff
+#define INT_GPI_MODE_03_SFT 12
+#define INT_GPI_MODE_03_HI 14
+#define INT_GPI_MODE_03_SZ 3
+#define INT_GPI_MODE_04_MSK 0x00070000
+#define INT_GPI_MODE_04_I_MSK 0xfff8ffff
+#define INT_GPI_MODE_04_SFT 16
+#define INT_GPI_MODE_04_HI 18
+#define INT_GPI_MODE_04_SZ 3
+#define INT_GPI_MODE_05_MSK 0x00700000
+#define INT_GPI_MODE_05_I_MSK 0xff8fffff
+#define INT_GPI_MODE_05_SFT 20
+#define INT_GPI_MODE_05_HI 22
+#define INT_GPI_MODE_05_SZ 3
+#define INT_GPI_MODE_06_MSK 0x07000000
+#define INT_GPI_MODE_06_I_MSK 0xf8ffffff
+#define INT_GPI_MODE_06_SFT 24
+#define INT_GPI_MODE_06_HI 26
+#define INT_GPI_MODE_06_SZ 3
+#define INT_GPI_MODE_07_MSK 0x70000000
+#define INT_GPI_MODE_07_I_MSK 0x8fffffff
+#define INT_GPI_MODE_07_SFT 28
+#define INT_GPI_MODE_07_HI 30
+#define INT_GPI_MODE_07_SZ 3
+#define INT_GPI_MODE_08_MSK 0x00000007
+#define INT_GPI_MODE_08_I_MSK 0xfffffff8
+#define INT_GPI_MODE_08_SFT 0
+#define INT_GPI_MODE_08_HI 2
+#define INT_GPI_MODE_08_SZ 3
+#define INT_GPI_MODE_09_MSK 0x00000070
+#define INT_GPI_MODE_09_I_MSK 0xffffff8f
+#define INT_GPI_MODE_09_SFT 4
+#define INT_GPI_MODE_09_HI 6
+#define INT_GPI_MODE_09_SZ 3
+#define INT_GPI_MODE_10_MSK 0x00000700
+#define INT_GPI_MODE_10_I_MSK 0xfffff8ff
+#define INT_GPI_MODE_10_SFT 8
+#define INT_GPI_MODE_10_HI 10
+#define INT_GPI_MODE_10_SZ 3
+#define INT_GPI_MODE_11_MSK 0x00007000
+#define INT_GPI_MODE_11_I_MSK 0xffff8fff
+#define INT_GPI_MODE_11_SFT 12
+#define INT_GPI_MODE_11_HI 14
+#define INT_GPI_MODE_11_SZ 3
+#define INT_GPI_MODE_12_MSK 0x00070000
+#define INT_GPI_MODE_12_I_MSK 0xfff8ffff
+#define INT_GPI_MODE_12_SFT 16
+#define INT_GPI_MODE_12_HI 18
+#define INT_GPI_MODE_12_SZ 3
+#define INT_GPI_MODE_13_MSK 0x00700000
+#define INT_GPI_MODE_13_I_MSK 0xff8fffff
+#define INT_GPI_MODE_13_SFT 20
+#define INT_GPI_MODE_13_HI 22
+#define INT_GPI_MODE_13_SZ 3
+#define INT_GPI_MODE_14_MSK 0x07000000
+#define INT_GPI_MODE_14_I_MSK 0xf8ffffff
+#define INT_GPI_MODE_14_SFT 24
+#define INT_GPI_MODE_14_HI 26
+#define INT_GPI_MODE_14_SZ 3
+#define INT_GPI_MODE_15_MSK 0x70000000
+#define INT_GPI_MODE_15_I_MSK 0x8fffffff
+#define INT_GPI_MODE_15_SFT 28
+#define INT_GPI_MODE_15_HI 30
+#define INT_GPI_MODE_15_SZ 3
+#define INT_GPI_MODE_16_MSK 0x00000007
+#define INT_GPI_MODE_16_I_MSK 0xfffffff8
+#define INT_GPI_MODE_16_SFT 0
+#define INT_GPI_MODE_16_HI 2
+#define INT_GPI_MODE_16_SZ 3
+#define INT_GPI_MODE_17_MSK 0x00000070
+#define INT_GPI_MODE_17_I_MSK 0xffffff8f
+#define INT_GPI_MODE_17_SFT 4
+#define INT_GPI_MODE_17_HI 6
+#define INT_GPI_MODE_17_SZ 3
+#define INT_GPI_MODE_18_MSK 0x00000700
+#define INT_GPI_MODE_18_I_MSK 0xfffff8ff
+#define INT_GPI_MODE_18_SFT 8
+#define INT_GPI_MODE_18_HI 10
+#define INT_GPI_MODE_18_SZ 3
+#define INT_GPI_MODE_19_MSK 0x00007000
+#define INT_GPI_MODE_19_I_MSK 0xffff8fff
+#define INT_GPI_MODE_19_SFT 12
+#define INT_GPI_MODE_19_HI 14
+#define INT_GPI_MODE_19_SZ 3
+#define INT_GPI_MODE_20_MSK 0x00070000
+#define INT_GPI_MODE_20_I_MSK 0xfff8ffff
+#define INT_GPI_MODE_20_SFT 16
+#define INT_GPI_MODE_20_HI 18
+#define INT_GPI_MODE_20_SZ 3
+#define INT_GPI_MODE_21_MSK 0x00700000
+#define INT_GPI_MODE_21_I_MSK 0xff8fffff
+#define INT_GPI_MODE_21_SFT 20
+#define INT_GPI_MODE_21_HI 22
+#define INT_GPI_MODE_21_SZ 3
+#define INT_GPI_MODE_22_MSK 0x07000000
+#define INT_GPI_MODE_22_I_MSK 0xf8ffffff
+#define INT_GPI_MODE_22_SFT 24
+#define INT_GPI_MODE_22_HI 26
+#define INT_GPI_MODE_22_SZ 3
+#define GPO_INT_POL_MSK 0x80000000
+#define GPO_INT_POL_I_MSK 0x7fffffff
+#define GPO_INT_POL_SFT 31
+#define GPO_INT_POL_HI 31
+#define GPO_INT_POL_SZ 1
+#define INT_IPC_RAW_MSK 0xffffffff
+#define INT_IPC_RAW_I_MSK 0x00000000
+#define INT_IPC_RAW_SFT 0
+#define INT_IPC_RAW_HI 31
+#define INT_IPC_RAW_SZ 32
+#define INT_WIFI_PHY_MSK 0x00800000
+#define INT_WIFI_PHY_I_MSK 0xff7fffff
+#define INT_WIFI_PHY_SFT 23
+#define INT_WIFI_PHY_HI 23
+#define INT_WIFI_PHY_SZ 1
+#define INT_UART_DBG_RX_TOUT_MSK 0x04000000
+#define INT_UART_DBG_RX_TOUT_I_MSK 0xfbffffff
+#define INT_UART_DBG_RX_TOUT_SFT 26
+#define INT_UART_DBG_RX_TOUT_HI 26
+#define INT_UART_DBG_RX_TOUT_SZ 1
+#define INT_UART_DATA_RX_TOUT_MSK 0x40000000
+#define INT_UART_DATA_RX_TOUT_I_MSK 0xbfffffff
+#define INT_UART_DATA_RX_TOUT_SFT 30
+#define INT_UART_DATA_RX_TOUT_HI 30
+#define INT_UART_DATA_RX_TOUT_SZ 1
+#define INT_ALC_TIMEOUT_MSK 0x00000100
+#define INT_ALC_TIMEOUT_I_MSK 0xfffffeff
+#define INT_ALC_TIMEOUT_SFT 8
+#define INT_ALC_TIMEOUT_HI 8
+#define INT_ALC_TIMEOUT_SZ 1
+#define INT_REQ_LOCK_MSK 0x00000200
+#define INT_REQ_LOCK_I_MSK 0xfffffdff
+#define INT_REQ_LOCK_SFT 9
+#define INT_REQ_LOCK_HI 9
+#define INT_REQ_LOCK_SZ 1
+#define INT_TX_LIMIT_MSK 0x00000400
+#define INT_TX_LIMIT_I_MSK 0xfffffbff
+#define INT_TX_LIMIT_SFT 10
+#define INT_TX_LIMIT_HI 10
+#define INT_TX_LIMIT_SZ 1
+#define INT_ID_THOLD_RX_MSK 0x00000800
+#define INT_ID_THOLD_RX_I_MSK 0xfffff7ff
+#define INT_ID_THOLD_RX_SFT 11
+#define INT_ID_THOLD_RX_HI 11
+#define INT_ID_THOLD_RX_SZ 1
+#define INT_ID_THOLD_TX_MSK 0x00001000
+#define INT_ID_THOLD_TX_I_MSK 0xffffefff
+#define INT_ID_THOLD_TX_SFT 12
+#define INT_ID_THOLD_TX_HI 12
+#define INT_ID_THOLD_TX_SZ 1
+#define INT_ID_DOUBLE_RLS_MSK 0x00002000
+#define INT_ID_DOUBLE_RLS_I_MSK 0xffffdfff
+#define INT_ID_DOUBLE_RLS_SFT 13
+#define INT_ID_DOUBLE_RLS_HI 13
+#define INT_ID_DOUBLE_RLS_SZ 1
+#define INT_RX_ID_LEN_THOLD_MSK 0x00004000
+#define INT_RX_ID_LEN_THOLD_I_MSK 0xffffbfff
+#define INT_RX_ID_LEN_THOLD_SFT 14
+#define INT_RX_ID_LEN_THOLD_HI 14
+#define INT_RX_ID_LEN_THOLD_SZ 1
+#define INT_TX_ID_LEN_THOLD_MSK 0x00008000
+#define INT_TX_ID_LEN_THOLD_I_MSK 0xffff7fff
+#define INT_TX_ID_LEN_THOLD_SFT 15
+#define INT_TX_ID_LEN_THOLD_HI 15
+#define INT_TX_ID_LEN_THOLD_SZ 1
+#define INT_ALL_ID_LEN_THOLD_MSK 0x00010000
+#define INT_ALL_ID_LEN_THOLD_I_MSK 0xfffeffff
+#define INT_ALL_ID_LEN_THOLD_SFT 16
+#define INT_ALL_ID_LEN_THOLD_HI 16
+#define INT_ALL_ID_LEN_THOLD_SZ 1
+#define INT_TRASH_CAN_MSK 0x00020000
+#define INT_TRASH_CAN_I_MSK 0xfffdffff
+#define INT_TRASH_CAN_SFT 17
+#define INT_TRASH_CAN_HI 17
+#define INT_TRASH_CAN_SZ 1
+#define INT_MB_LOWTHOLD_MSK 0x00040000
+#define INT_MB_LOWTHOLD_I_MSK 0xfffbffff
+#define INT_MB_LOWTHOLD_SFT 18
+#define INT_MB_LOWTHOLD_HI 18
+#define INT_MB_LOWTHOLD_SZ 1
+#define INT_EDCA0_LOWTHOLD_MSK 0x00100000
+#define INT_EDCA0_LOWTHOLD_I_MSK 0xffefffff
+#define INT_EDCA0_LOWTHOLD_SFT 20
+#define INT_EDCA0_LOWTHOLD_HI 20
+#define INT_EDCA0_LOWTHOLD_SZ 1
+#define INT_EDCA1_LOWTHOLD_MSK 0x00200000
+#define INT_EDCA1_LOWTHOLD_I_MSK 0xffdfffff
+#define INT_EDCA1_LOWTHOLD_SFT 21
+#define INT_EDCA1_LOWTHOLD_HI 21
+#define INT_EDCA1_LOWTHOLD_SZ 1
+#define INT_EDCA2_LOWTHOLD_MSK 0x00400000
+#define INT_EDCA2_LOWTHOLD_I_MSK 0xffbfffff
+#define INT_EDCA2_LOWTHOLD_SFT 22
+#define INT_EDCA2_LOWTHOLD_HI 22
+#define INT_EDCA2_LOWTHOLD_SZ 1
+#define INT_EDCA3_LOWTHOLD_MSK 0x00800000
+#define INT_EDCA3_LOWTHOLD_I_MSK 0xff7fffff
+#define INT_EDCA3_LOWTHOLD_SFT 23
+#define INT_EDCA3_LOWTHOLD_HI 23
+#define INT_EDCA3_LOWTHOLD_SZ 1
+#define INT_SDIO_WAKE_MSK 0x00000004
+#define INT_SDIO_WAKE_I_MSK 0xfffffffb
+#define INT_SDIO_WAKE_SFT 2
+#define INT_SDIO_WAKE_HI 2
+#define INT_SDIO_WAKE_SZ 1
+#define INT_SPI_M_DONE_MSK 0x00000008
+#define INT_SPI_M_DONE_I_MSK 0xfffffff7
+#define INT_SPI_M_DONE_SFT 3
+#define INT_SPI_M_DONE_HI 3
+#define INT_SPI_M_DONE_SZ 1
+#define INT_FLASH_DMA_DONE_MSK 0x00000040
+#define INT_FLASH_DMA_DONE_I_MSK 0xffffffbf
+#define INT_FLASH_DMA_DONE_SFT 6
+#define INT_FLASH_DMA_DONE_HI 6
+#define INT_FLASH_DMA_DONE_SZ 1
+#define INT_FBUSDMAC_INT_COMBINED_MSK 0x00000200
+#define INT_FBUSDMAC_INT_COMBINED_I_MSK 0xfffffdff
+#define INT_FBUSDMAC_INT_COMBINED_SFT 9
+#define INT_FBUSDMAC_INT_COMBINED_HI 9
+#define INT_FBUSDMAC_INT_COMBINED_SZ 1
+#define INT_DMAC_INT_COMBINED_MSK 0x00000400
+#define INT_DMAC_INT_COMBINED_I_MSK 0xfffffbff
+#define INT_DMAC_INT_COMBINED_SFT 10
+#define INT_DMAC_INT_COMBINED_HI 10
+#define INT_DMAC_INT_COMBINED_SZ 1
+#define INT_I2S_MSK 0x00010000
+#define INT_I2S_I_MSK 0xfffeffff
+#define INT_I2S_SFT 16
+#define INT_I2S_HI 16
+#define INT_I2S_SZ 1
+#define INT_CPU_ALT_MSK 0x00040000
+#define INT_CPU_ALT_I_MSK 0xfffbffff
+#define INT_CPU_ALT_SFT 18
+#define INT_CPU_ALT_HI 18
+#define INT_CPU_ALT_SZ 1
+#define INT_CPU_MSK 0x00080000
+#define INT_CPU_I_MSK 0xfff7ffff
+#define INT_CPU_SFT 19
+#define INT_CPU_HI 19
+#define INT_CPU_SZ 1
+#define INT_US_TIMER_0_MSK 0x00100000
+#define INT_US_TIMER_0_I_MSK 0xffefffff
+#define INT_US_TIMER_0_SFT 20
+#define INT_US_TIMER_0_HI 20
+#define INT_US_TIMER_0_SZ 1
+#define INT_US_TIMER_1_MSK 0x00200000
+#define INT_US_TIMER_1_I_MSK 0xffdfffff
+#define INT_US_TIMER_1_SFT 21
+#define INT_US_TIMER_1_HI 21
+#define INT_US_TIMER_1_SZ 1
+#define INT_US_TIMER_2_MSK 0x00400000
+#define INT_US_TIMER_2_I_MSK 0xffbfffff
+#define INT_US_TIMER_2_SFT 22
+#define INT_US_TIMER_2_HI 22
+#define INT_US_TIMER_2_SZ 1
+#define INT_US_TIMER_3_MSK 0x00800000
+#define INT_US_TIMER_3_I_MSK 0xff7fffff
+#define INT_US_TIMER_3_SFT 23
+#define INT_US_TIMER_3_HI 23
+#define INT_US_TIMER_3_SZ 1
+#define INT_MS_TIMER_0_MSK 0x01000000
+#define INT_MS_TIMER_0_I_MSK 0xfeffffff
+#define INT_MS_TIMER_0_SFT 24
+#define INT_MS_TIMER_0_HI 24
+#define INT_MS_TIMER_0_SZ 1
+#define INT_MS_TIMER_1_MSK 0x02000000
+#define INT_MS_TIMER_1_I_MSK 0xfdffffff
+#define INT_MS_TIMER_1_SFT 25
+#define INT_MS_TIMER_1_HI 25
+#define INT_MS_TIMER_1_SZ 1
+#define INT_MS_TIMER_2_MSK 0x04000000
+#define INT_MS_TIMER_2_I_MSK 0xfbffffff
+#define INT_MS_TIMER_2_SFT 26
+#define INT_MS_TIMER_2_HI 26
+#define INT_MS_TIMER_2_SZ 1
+#define INT_MS_TIMER_3_MSK 0x08000000
+#define INT_MS_TIMER_3_I_MSK 0xf7ffffff
+#define INT_MS_TIMER_3_SFT 27
+#define INT_MS_TIMER_3_HI 27
+#define INT_MS_TIMER_3_SZ 1
+#define INT_I2CMST_MSK 0x10000000
+#define INT_I2CMST_I_MSK 0xefffffff
+#define INT_I2CMST_SFT 28
+#define INT_I2CMST_HI 28
+#define INT_I2CMST_SZ 1
+#define INT_HCI_MSK 0x20000000
+#define INT_HCI_I_MSK 0xdfffffff
+#define INT_HCI_SFT 29
+#define INT_HCI_HI 29
+#define INT_HCI_SZ 1
+#define INT_CO_DMA_MSK 0x40000000
+#define INT_CO_DMA_I_MSK 0xbfffffff
+#define INT_CO_DMA_SFT 30
+#define INT_CO_DMA_HI 30
+#define INT_CO_DMA_SZ 1
+#define PATCH02_EN_MSK 0x00000001
+#define PATCH02_EN_I_MSK 0xfffffffe
+#define PATCH02_EN_SFT 0
+#define PATCH02_EN_HI 0
+#define PATCH02_EN_SZ 1
+#define PATCH02_ADDR_MSK 0x0001fffc
+#define PATCH02_ADDR_I_MSK 0xfffe0003
+#define PATCH02_ADDR_SFT 2
+#define PATCH02_ADDR_HI 16
+#define PATCH02_ADDR_SZ 15
+#define PATCH02_DATA_MSK 0xffffffff
+#define PATCH02_DATA_I_MSK 0x00000000
+#define PATCH02_DATA_SFT 0
+#define PATCH02_DATA_HI 31
+#define PATCH02_DATA_SZ 32
+#define PATCH03_EN_MSK 0x00000001
+#define PATCH03_EN_I_MSK 0xfffffffe
+#define PATCH03_EN_SFT 0
+#define PATCH03_EN_HI 0
+#define PATCH03_EN_SZ 1
+#define PATCH03_ADDR_MSK 0x0001fffc
+#define PATCH03_ADDR_I_MSK 0xfffe0003
+#define PATCH03_ADDR_SFT 2
+#define PATCH03_ADDR_HI 16
+#define PATCH03_ADDR_SZ 15
+#define PATCH03_DATA_MSK 0xffffffff
+#define PATCH03_DATA_I_MSK 0x00000000
+#define PATCH03_DATA_SFT 0
+#define PATCH03_DATA_HI 31
+#define PATCH03_DATA_SZ 32
+#define PATCH04_EN_MSK 0x00000001
+#define PATCH04_EN_I_MSK 0xfffffffe
+#define PATCH04_EN_SFT 0
+#define PATCH04_EN_HI 0
+#define PATCH04_EN_SZ 1
+#define PATCH04_ADDR_MSK 0x0001fffc
+#define PATCH04_ADDR_I_MSK 0xfffe0003
+#define PATCH04_ADDR_SFT 2
+#define PATCH04_ADDR_HI 16
+#define PATCH04_ADDR_SZ 15
+#define PATCH04_DATA_MSK 0xffffffff
+#define PATCH04_DATA_I_MSK 0x00000000
+#define PATCH04_DATA_SFT 0
+#define PATCH04_DATA_HI 31
+#define PATCH04_DATA_SZ 32
+#define PATCH05_EN_MSK 0x00000001
+#define PATCH05_EN_I_MSK 0xfffffffe
+#define PATCH05_EN_SFT 0
+#define PATCH05_EN_HI 0
+#define PATCH05_EN_SZ 1
+#define PATCH05_ADDR_MSK 0x0001fffc
+#define PATCH05_ADDR_I_MSK 0xfffe0003
+#define PATCH05_ADDR_SFT 2
+#define PATCH05_ADDR_HI 16
+#define PATCH05_ADDR_SZ 15
+#define PATCH05_DATA_MSK 0xffffffff
+#define PATCH05_DATA_I_MSK 0x00000000
+#define PATCH05_DATA_SFT 0
+#define PATCH05_DATA_HI 31
+#define PATCH05_DATA_SZ 32
+#define PATCH06_EN_MSK 0x00000001
+#define PATCH06_EN_I_MSK 0xfffffffe
+#define PATCH06_EN_SFT 0
+#define PATCH06_EN_HI 0
+#define PATCH06_EN_SZ 1
+#define PATCH06_ADDR_MSK 0x0001fffc
+#define PATCH06_ADDR_I_MSK 0xfffe0003
+#define PATCH06_ADDR_SFT 2
+#define PATCH06_ADDR_HI 16
+#define PATCH06_ADDR_SZ 15
+#define PATCH06_DATA_MSK 0xffffffff
+#define PATCH06_DATA_I_MSK 0x00000000
+#define PATCH06_DATA_SFT 0
+#define PATCH06_DATA_HI 31
+#define PATCH06_DATA_SZ 32
+#define PATCH07_EN_MSK 0x00000001
+#define PATCH07_EN_I_MSK 0xfffffffe
+#define PATCH07_EN_SFT 0
+#define PATCH07_EN_HI 0
+#define PATCH07_EN_SZ 1
+#define PATCH07_ADDR_MSK 0x0001fffc
+#define PATCH07_ADDR_I_MSK 0xfffe0003
+#define PATCH07_ADDR_SFT 2
+#define PATCH07_ADDR_HI 16
+#define PATCH07_ADDR_SZ 15
+#define PATCH07_DATA_MSK 0xffffffff
+#define PATCH07_DATA_I_MSK 0x00000000
+#define PATCH07_DATA_SFT 0
+#define PATCH07_DATA_HI 31
+#define PATCH07_DATA_SZ 32
+#define PATCH08_EN_MSK 0x00000001
+#define PATCH08_EN_I_MSK 0xfffffffe
+#define PATCH08_EN_SFT 0
+#define PATCH08_EN_HI 0
+#define PATCH08_EN_SZ 1
+#define PATCH08_ADDR_MSK 0x0001fffc
+#define PATCH08_ADDR_I_MSK 0xfffe0003
+#define PATCH08_ADDR_SFT 2
+#define PATCH08_ADDR_HI 16
+#define PATCH08_ADDR_SZ 15
+#define PATCH08_DATA_MSK 0xffffffff
+#define PATCH08_DATA_I_MSK 0x00000000
+#define PATCH08_DATA_SFT 0
+#define PATCH08_DATA_HI 31
+#define PATCH08_DATA_SZ 32
+#define PATCH09_EN_MSK 0x00000001
+#define PATCH09_EN_I_MSK 0xfffffffe
+#define PATCH09_EN_SFT 0
+#define PATCH09_EN_HI 0
+#define PATCH09_EN_SZ 1
+#define PATCH09_ADDR_MSK 0x0001fffc
+#define PATCH09_ADDR_I_MSK 0xfffe0003
+#define PATCH09_ADDR_SFT 2
+#define PATCH09_ADDR_HI 16
+#define PATCH09_ADDR_SZ 15
+#define PATCH09_DATA_MSK 0xffffffff
+#define PATCH09_DATA_I_MSK 0x00000000
+#define PATCH09_DATA_SFT 0
+#define PATCH09_DATA_HI 31
+#define PATCH09_DATA_SZ 32
+#define PATCH10_EN_MSK 0x00000001
+#define PATCH10_EN_I_MSK 0xfffffffe
+#define PATCH10_EN_SFT 0
+#define PATCH10_EN_HI 0
+#define PATCH10_EN_SZ 1
+#define PATCH10_ADDR_MSK 0x0001fffc
+#define PATCH10_ADDR_I_MSK 0xfffe0003
+#define PATCH10_ADDR_SFT 2
+#define PATCH10_ADDR_HI 16
+#define PATCH10_ADDR_SZ 15
+#define PATCH10_DATA_MSK 0xffffffff
+#define PATCH10_DATA_I_MSK 0x00000000
+#define PATCH10_DATA_SFT 0
+#define PATCH10_DATA_HI 31
+#define PATCH10_DATA_SZ 32
+#define PATCH11_EN_MSK 0x00000001
+#define PATCH11_EN_I_MSK 0xfffffffe
+#define PATCH11_EN_SFT 0
+#define PATCH11_EN_HI 0
+#define PATCH11_EN_SZ 1
+#define PATCH11_ADDR_MSK 0x0001fffc
+#define PATCH11_ADDR_I_MSK 0xfffe0003
+#define PATCH11_ADDR_SFT 2
+#define PATCH11_ADDR_HI 16
+#define PATCH11_ADDR_SZ 15
+#define PATCH11_DATA_MSK 0xffffffff
+#define PATCH11_DATA_I_MSK 0x00000000
+#define PATCH11_DATA_SFT 0
+#define PATCH11_DATA_HI 31
+#define PATCH11_DATA_SZ 32
+#define PATCH12_EN_MSK 0x00000001
+#define PATCH12_EN_I_MSK 0xfffffffe
+#define PATCH12_EN_SFT 0
+#define PATCH12_EN_HI 0
+#define PATCH12_EN_SZ 1
+#define PATCH12_ADDR_MSK 0x0001fffc
+#define PATCH12_ADDR_I_MSK 0xfffe0003
+#define PATCH12_ADDR_SFT 2
+#define PATCH12_ADDR_HI 16
+#define PATCH12_ADDR_SZ 15
+#define PATCH12_DATA_MSK 0xffffffff
+#define PATCH12_DATA_I_MSK 0x00000000
+#define PATCH12_DATA_SFT 0
+#define PATCH12_DATA_HI 31
+#define PATCH12_DATA_SZ 32
+#define PATCH13_EN_MSK 0x00000001
+#define PATCH13_EN_I_MSK 0xfffffffe
+#define PATCH13_EN_SFT 0
+#define PATCH13_EN_HI 0
+#define PATCH13_EN_SZ 1
+#define PATCH13_ADDR_MSK 0x0001fffc
+#define PATCH13_ADDR_I_MSK 0xfffe0003
+#define PATCH13_ADDR_SFT 2
+#define PATCH13_ADDR_HI 16
+#define PATCH13_ADDR_SZ 15
+#define PATCH13_DATA_MSK 0xffffffff
+#define PATCH13_DATA_I_MSK 0x00000000
+#define PATCH13_DATA_SFT 0
+#define PATCH13_DATA_HI 31
+#define PATCH13_DATA_SZ 32
+#define PATCH14_EN_MSK 0x00000001
+#define PATCH14_EN_I_MSK 0xfffffffe
+#define PATCH14_EN_SFT 0
+#define PATCH14_EN_HI 0
+#define PATCH14_EN_SZ 1
+#define PATCH14_ADDR_MSK 0x0001fffc
+#define PATCH14_ADDR_I_MSK 0xfffe0003
+#define PATCH14_ADDR_SFT 2
+#define PATCH14_ADDR_HI 16
+#define PATCH14_ADDR_SZ 15
+#define PATCH14_DATA_MSK 0xffffffff
+#define PATCH14_DATA_I_MSK 0x00000000
+#define PATCH14_DATA_SFT 0
+#define PATCH14_DATA_HI 31
+#define PATCH14_DATA_SZ 32
+#define PATCH15_EN_MSK 0x00000001
+#define PATCH15_EN_I_MSK 0xfffffffe
+#define PATCH15_EN_SFT 0
+#define PATCH15_EN_HI 0
+#define PATCH15_EN_SZ 1
+#define PATCH15_ADDR_MSK 0x0001fffc
+#define PATCH15_ADDR_I_MSK 0xfffe0003
+#define PATCH15_ADDR_SFT 2
+#define PATCH15_ADDR_HI 16
+#define PATCH15_ADDR_SZ 15
+#define PATCH15_DATA_MSK 0xffffffff
+#define PATCH15_DATA_I_MSK 0x00000000
+#define PATCH15_DATA_SFT 0
+#define PATCH15_DATA_HI 31
+#define PATCH15_DATA_SZ 32
+#define INT_BROWNOUT_LOWBATTERY_MSK 0x00000001
+#define INT_BROWNOUT_LOWBATTERY_I_MSK 0xfffffffe
+#define INT_BROWNOUT_LOWBATTERY_SFT 0
+#define INT_BROWNOUT_LOWBATTERY_HI 0
+#define INT_BROWNOUT_LOWBATTERY_SZ 1
+#define LOWBATTERY_SAMPLE_MIN_COUNT_MSK 0x0000000f
+#define LOWBATTERY_SAMPLE_MIN_COUNT_I_MSK 0xfffffff0
+#define LOWBATTERY_SAMPLE_MIN_COUNT_SFT 0
+#define LOWBATTERY_SAMPLE_MIN_COUNT_HI 3
+#define LOWBATTERY_SAMPLE_MIN_COUNT_SZ 4
+#define TX_ON_DEMAND_ENA_MSK 0x00000002
+#define TX_ON_DEMAND_ENA_I_MSK 0xfffffffd
+#define TX_ON_DEMAND_ENA_SFT 1
+#define TX_ON_DEMAND_ENA_HI 1
+#define TX_ON_DEMAND_ENA_SZ 1
+#define RX_2_HOST_MSK 0x00000004
+#define RX_2_HOST_I_MSK 0xfffffffb
+#define RX_2_HOST_SFT 2
+#define RX_2_HOST_HI 2
+#define RX_2_HOST_SZ 1
+#define AUTO_SEQNO_MSK 0x00000008
+#define AUTO_SEQNO_I_MSK 0xfffffff7
+#define AUTO_SEQNO_SFT 3
+#define AUTO_SEQNO_HI 3
+#define AUTO_SEQNO_SZ 1
+#define BYPASS_TX_PARSER_ENCAP_MSK 0x00000010
+#define BYPASS_TX_PARSER_ENCAP_I_MSK 0xffffffef
+#define BYPASS_TX_PARSER_ENCAP_SFT 4
+#define BYPASS_TX_PARSER_ENCAP_HI 4
+#define BYPASS_TX_PARSER_ENCAP_SZ 1
+#define HDR_STRIP_MSK 0x00000020
+#define HDR_STRIP_I_MSK 0xffffffdf
+#define HDR_STRIP_SFT 5
+#define HDR_STRIP_HI 5
+#define HDR_STRIP_SZ 1
+#define ERP_PROTECT_MSK 0x000000c0
+#define ERP_PROTECT_I_MSK 0xffffff3f
+#define ERP_PROTECT_SFT 6
+#define ERP_PROTECT_HI 7
+#define ERP_PROTECT_SZ 2
+#define PRO_VER_MSK 0x00000300
+#define PRO_VER_I_MSK 0xfffffcff
+#define PRO_VER_SFT 8
+#define PRO_VER_HI 9
+#define PRO_VER_SZ 2
+#define TXQ_ID0_MSK 0x00007000
+#define TXQ_ID0_I_MSK 0xffff8fff
+#define TXQ_ID0_SFT 12
+#define TXQ_ID0_HI 14
+#define TXQ_ID0_SZ 3
+#define TXQ_ID1_MSK 0x00070000
+#define TXQ_ID1_I_MSK 0xfff8ffff
+#define TXQ_ID1_SFT 16
+#define TXQ_ID1_HI 18
+#define TXQ_ID1_SZ 3
+#define TX_ETHER_TRAP_EN_MSK 0x00100000
+#define TX_ETHER_TRAP_EN_I_MSK 0xffefffff
+#define TX_ETHER_TRAP_EN_SFT 20
+#define TX_ETHER_TRAP_EN_HI 20
+#define TX_ETHER_TRAP_EN_SZ 1
+#define RX_ETHER_TRAP_EN_MSK 0x00200000
+#define RX_ETHER_TRAP_EN_I_MSK 0xffdfffff
+#define RX_ETHER_TRAP_EN_SFT 21
+#define RX_ETHER_TRAP_EN_HI 21
+#define RX_ETHER_TRAP_EN_SZ 1
+#define RX_NULL_TRAP_EN_MSK 0x00400000
+#define RX_NULL_TRAP_EN_I_MSK 0xffbfffff
+#define RX_NULL_TRAP_EN_SFT 22
+#define RX_NULL_TRAP_EN_HI 22
+#define RX_NULL_TRAP_EN_SZ 1
+#define TRX_DEBUG_CNT_ENA_MSK 0x10000000
+#define TRX_DEBUG_CNT_ENA_I_MSK 0xefffffff
+#define TRX_DEBUG_CNT_ENA_SFT 28
+#define TRX_DEBUG_CNT_ENA_HI 28
+#define TRX_DEBUG_CNT_ENA_SZ 1
+#define HCI_TX_AGG_EN_MSK 0x00000001
+#define HCI_TX_AGG_EN_I_MSK 0xfffffffe
+#define HCI_TX_AGG_EN_SFT 0
+#define HCI_TX_AGG_EN_HI 0
+#define HCI_TX_AGG_EN_SZ 1
+#define HCI_RX_EN_MSK 0x00000002
+#define HCI_RX_EN_I_MSK 0xfffffffd
+#define HCI_RX_EN_SFT 1
+#define HCI_RX_EN_HI 1
+#define HCI_RX_EN_SZ 1
+#define HCI_RX_FORM_1_MSK 0x40000000
+#define HCI_RX_FORM_1_I_MSK 0xbfffffff
+#define HCI_RX_FORM_1_SFT 30
+#define HCI_RX_FORM_1_HI 30
+#define HCI_RX_FORM_1_SZ 1
+#define HCI_RX_FORM_0_MSK 0x80000000
+#define HCI_RX_FORM_0_I_MSK 0x7fffffff
+#define HCI_RX_FORM_0_SFT 31
+#define HCI_RX_FORM_0_HI 31
+#define HCI_RX_FORM_0_SZ 1
+#define TX_FLOW_CTRL_MSK 0x0000ffff
+#define TX_FLOW_CTRL_I_MSK 0xffff0000
+#define TX_FLOW_CTRL_SFT 0
+#define TX_FLOW_CTRL_HI 15
+#define TX_FLOW_CTRL_SZ 16
+#define TX_FLOW_MGMT_MSK 0xffff0000
+#define TX_FLOW_MGMT_I_MSK 0x0000ffff
+#define TX_FLOW_MGMT_SFT 16
+#define TX_FLOW_MGMT_HI 31
+#define TX_FLOW_MGMT_SZ 16
+#define TX_FLOW_DATA_MSK 0xffffffff
+#define TX_FLOW_DATA_I_MSK 0x00000000
+#define TX_FLOW_DATA_SFT 0
+#define TX_FLOW_DATA_HI 31
+#define TX_FLOW_DATA_SZ 32
+#define SD_RX_LEN_MSK 0x0000ffff
+#define SD_RX_LEN_I_MSK 0xffff0000
+#define SD_RX_LEN_SFT 0
+#define SD_RX_LEN_HI 15
+#define SD_RX_LEN_SZ 16
+#define RX_ACCU_LEN_MSK 0x0000ffff
+#define RX_ACCU_LEN_I_MSK 0xffff0000
+#define RX_ACCU_LEN_SFT 0
+#define RX_ACCU_LEN_HI 15
+#define RX_ACCU_LEN_SZ 16
+#define HCI_RX_LEN_MSK 0xffff0000
+#define HCI_RX_LEN_I_MSK 0x0000ffff
+#define HCI_RX_LEN_SFT 16
+#define HCI_RX_LEN_HI 31
+#define HCI_RX_LEN_SZ 16
+#define DOT11RTSTHRESHOLD_MSK 0xffff0000
+#define DOT11RTSTHRESHOLD_I_MSK 0x0000ffff
+#define DOT11RTSTHRESHOLD_SFT 16
+#define DOT11RTSTHRESHOLD_HI 31
+#define DOT11RTSTHRESHOLD_SZ 16
+#define TX_ERR_RECOVER_MSK 0x00000001
+#define TX_ERR_RECOVER_I_MSK 0xfffffffe
+#define TX_ERR_RECOVER_SFT 0
+#define TX_ERR_RECOVER_HI 0
+#define TX_ERR_RECOVER_SZ 1
+#define TX_ERR_FIRST_4B_EN_MSK 0x00000002
+#define TX_ERR_FIRST_4B_EN_I_MSK 0xfffffffd
+#define TX_ERR_FIRST_4B_EN_SFT 1
+#define TX_ERR_FIRST_4B_EN_HI 1
+#define TX_ERR_FIRST_4B_EN_SZ 1
+#define RX_INT_TIMEOUT_MSK 0xffff0000
+#define RX_INT_TIMEOUT_I_MSK 0x0000ffff
+#define RX_INT_TIMEOUT_SFT 16
+#define RX_INT_TIMEOUT_HI 31
+#define RX_INT_TIMEOUT_SZ 16
+#define TXF_ID_MSK 0x0000003f
+#define TXF_ID_I_MSK 0xffffffc0
+#define TXF_ID_SFT 0
+#define TXF_ID_HI 5
+#define TXF_ID_SZ 6
+#define SEQ_CTRL_MSK 0x0000ffff
+#define SEQ_CTRL_I_MSK 0xffff0000
+#define SEQ_CTRL_SFT 0
+#define SEQ_CTRL_HI 15
+#define SEQ_CTRL_SZ 16
+#define DBG_ADDR_EN_MSK 0x00000001
+#define DBG_ADDR_EN_I_MSK 0xfffffffe
+#define DBG_ADDR_EN_SFT 0
+#define DBG_ADDR_EN_HI 0
+#define DBG_ADDR_EN_SZ 1
+#define DBG_ADDR_FENCE_MSK 0x0000ff00
+#define DBG_ADDR_FENCE_I_MSK 0xffff00ff
+#define DBG_ADDR_FENCE_SFT 8
+#define DBG_ADDR_FENCE_HI 15
+#define DBG_ADDR_FENCE_SZ 8
+#define TX_PBOFFSET_MSK 0x000000ff
+#define TX_PBOFFSET_I_MSK 0xffffff00
+#define TX_PBOFFSET_SFT 0
+#define TX_PBOFFSET_HI 7
+#define TX_PBOFFSET_SZ 8
+#define TX_INFO_SIZE_MSK 0x0000ff00
+#define TX_INFO_SIZE_I_MSK 0xffff00ff
+#define TX_INFO_SIZE_SFT 8
+#define TX_INFO_SIZE_HI 15
+#define TX_INFO_SIZE_SZ 8
+#define RX_INFO_SIZE_MSK 0x00ff0000
+#define RX_INFO_SIZE_I_MSK 0xff00ffff
+#define RX_INFO_SIZE_SFT 16
+#define RX_INFO_SIZE_HI 23
+#define RX_INFO_SIZE_SZ 8
+#define RX_LAST_PHY_SIZE_MSK 0xff000000
+#define RX_LAST_PHY_SIZE_I_MSK 0x00ffffff
+#define RX_LAST_PHY_SIZE_SFT 24
+#define RX_LAST_PHY_SIZE_HI 31
+#define RX_LAST_PHY_SIZE_SZ 8
+#define TX_INFO_CLEAR_SIZE_MSK 0x0000003f
+#define TX_INFO_CLEAR_SIZE_I_MSK 0xffffffc0
+#define TX_INFO_CLEAR_SIZE_SFT 0
+#define TX_INFO_CLEAR_SIZE_HI 5
+#define TX_INFO_CLEAR_SIZE_SZ 6
+#define TX_INFO_CLEAR_ENABLE_MSK 0x00000100
+#define TX_INFO_CLEAR_ENABLE_I_MSK 0xfffffeff
+#define TX_INFO_CLEAR_ENABLE_SFT 8
+#define TX_INFO_CLEAR_ENABLE_HI 8
+#define TX_INFO_CLEAR_ENABLE_SZ 1
+#define RX_PER_RD_LEN_MSK 0x0000003f
+#define RX_PER_RD_LEN_I_MSK 0xffffffc0
+#define RX_PER_RD_LEN_SFT 0
+#define RX_PER_RD_LEN_HI 5
+#define RX_PER_RD_LEN_SZ 6
+#define BACKUP_PG_CNT_MSK 0x00000f00
+#define BACKUP_PG_CNT_I_MSK 0xfffff0ff
+#define BACKUP_PG_CNT_SFT 8
+#define BACKUP_PG_CNT_HI 11
+#define BACKUP_PG_CNT_SZ 4
+#define MANUAL_HCI_ALLOC_EN_MSK 0x00000001
+#define MANUAL_HCI_ALLOC_EN_I_MSK 0xfffffffe
+#define MANUAL_HCI_ALLOC_EN_SFT 0
+#define MANUAL_HCI_ALLOC_EN_HI 0
+#define MANUAL_HCI_ALLOC_EN_SZ 1
+#define MANUAL_HCI_ALLOC_SIZE_MSK 0x0000ffff
+#define MANUAL_HCI_ALLOC_SIZE_I_MSK 0xffff0000
+#define MANUAL_HCI_ALLOC_SIZE_SFT 0
+#define MANUAL_HCI_ALLOC_SIZE_HI 15
+#define MANUAL_HCI_ALLOC_SIZE_SZ 16
+#define MANUAL_ALLOC_ID_MSK 0x0000007f
+#define MANUAL_ALLOC_ID_I_MSK 0xffffff80
+#define MANUAL_ALLOC_ID_SFT 0
+#define MANUAL_ALLOC_ID_HI 6
+#define MANUAL_ALLOC_ID_SZ 7
+#define HAS_MANUAL_BUF_MSK 0x00000080
+#define HAS_MANUAL_BUF_I_MSK 0xffffff7f
+#define HAS_MANUAL_BUF_SFT 7
+#define HAS_MANUAL_BUF_HI 7
+#define HAS_MANUAL_BUF_SZ 1
+#define DOUBLE_ALLOC_ERR_MSK 0x00000100
+#define DOUBLE_ALLOC_ERR_I_MSK 0xfffffeff
+#define DOUBLE_ALLOC_ERR_SFT 8
+#define DOUBLE_ALLOC_ERR_HI 8
+#define DOUBLE_ALLOC_ERR_SZ 1
+#define NO_ALLOC_ERR_MSK 0x00000200
+#define NO_ALLOC_ERR_I_MSK 0xfffffdff
+#define NO_ALLOC_ERR_SFT 9
+#define NO_ALLOC_ERR_HI 9
+#define NO_ALLOC_ERR_SZ 1
+#define TXTRAP_ETHTYPE1_MSK 0x0000ffff
+#define TXTRAP_ETHTYPE1_I_MSK 0xffff0000
+#define TXTRAP_ETHTYPE1_SFT 0
+#define TXTRAP_ETHTYPE1_HI 15
+#define TXTRAP_ETHTYPE1_SZ 16
+#define TXTRAP_ETHTYPE0_MSK 0xffff0000
+#define TXTRAP_ETHTYPE0_I_MSK 0x0000ffff
+#define TXTRAP_ETHTYPE0_SFT 16
+#define TXTRAP_ETHTYPE0_HI 31
+#define TXTRAP_ETHTYPE0_SZ 16
+#define RXTRAP_ETHTYPE1_MSK 0x0000ffff
+#define RXTRAP_ETHTYPE1_I_MSK 0xffff0000
+#define RXTRAP_ETHTYPE1_SFT 0
+#define RXTRAP_ETHTYPE1_HI 15
+#define RXTRAP_ETHTYPE1_SZ 16
+#define RXTRAP_ETHTYPE0_MSK 0xffff0000
+#define RXTRAP_ETHTYPE0_I_MSK 0x0000ffff
+#define RXTRAP_ETHTYPE0_SFT 16
+#define RXTRAP_ETHTYPE0_HI 31
+#define RXTRAP_ETHTYPE0_SZ 16
+#define TX_PKT_SEND_LEN_MSK 0x0000ffff
+#define TX_PKT_SEND_LEN_I_MSK 0xffff0000
+#define TX_PKT_SEND_LEN_SFT 0
+#define TX_PKT_SEND_LEN_HI 15
+#define TX_PKT_SEND_LEN_SZ 16
+#define TX_SDIO_PKT_LEN_MSK 0xffff0000
+#define TX_SDIO_PKT_LEN_I_MSK 0x0000ffff
+#define TX_SDIO_PKT_LEN_SFT 16
+#define TX_SDIO_PKT_LEN_HI 31
+#define TX_SDIO_PKT_LEN_SZ 16
+#define TX_PKT_SEND_ID_MSK 0x0000007f
+#define TX_PKT_SEND_ID_I_MSK 0xffffff80
+#define TX_PKT_SEND_ID_SFT 0
+#define TX_PKT_SEND_ID_HI 6
+#define TX_PKT_SEND_ID_SZ 7
+#define HCI_PENDING_RX_MPDU_CNT_MSK 0x0000001f
+#define HCI_PENDING_RX_MPDU_CNT_I_MSK 0xffffffe0
+#define HCI_PENDING_RX_MPDU_CNT_SFT 0
+#define HCI_PENDING_RX_MPDU_CNT_HI 4
+#define HCI_PENDING_RX_MPDU_CNT_SZ 5
+#define HCI_RX_HALT_MSK 0x00000100
+#define HCI_RX_HALT_I_MSK 0xfffffeff
+#define HCI_RX_HALT_SFT 8
+#define HCI_RX_HALT_HI 8
+#define HCI_RX_HALT_SZ 1
+#define HIF_LOOP_BACK_MSK 0x00000200
+#define HIF_LOOP_BACK_I_MSK 0xfffffdff
+#define HIF_LOOP_BACK_SFT 9
+#define HIF_LOOP_BACK_HI 9
+#define HIF_LOOP_BACK_SZ 1
+#define USB_BULK_IN_LEN_INIT_MSK 0x40000000
+#define USB_BULK_IN_LEN_INIT_I_MSK 0xbfffffff
+#define USB_BULK_IN_LEN_INIT_SFT 30
+#define USB_BULK_IN_LEN_INIT_HI 30
+#define USB_BULK_IN_LEN_INIT_SZ 1
+#define HCI_RX_MPDU_DEQUE_MSK 0x80000000
+#define HCI_RX_MPDU_DEQUE_I_MSK 0x7fffffff
+#define HCI_RX_MPDU_DEQUE_SFT 31
+#define HCI_RX_MPDU_DEQUE_HI 31
+#define HCI_RX_MPDU_DEQUE_SZ 1
+#define HCI_BULK_IN_HOST_SIZE_MSK 0x0001ffff
+#define HCI_BULK_IN_HOST_SIZE_I_MSK 0xfffe0000
+#define HCI_BULK_IN_HOST_SIZE_SFT 0
+#define HCI_BULK_IN_HOST_SIZE_HI 16
+#define HCI_BULK_IN_HOST_SIZE_SZ 17
+#define HCI_BULK_IN_TIME_OUT_MSK 0xffffffff
+#define HCI_BULK_IN_TIME_OUT_I_MSK 0x00000000
+#define HCI_BULK_IN_TIME_OUT_SFT 0
+#define HCI_BULK_IN_TIME_OUT_HI 31
+#define HCI_BULK_IN_TIME_OUT_SZ 32
+#define HCI_MONITOR_REG0_MSK 0xffffffff
+#define HCI_MONITOR_REG0_I_MSK 0x00000000
+#define HCI_MONITOR_REG0_SFT 0
+#define HCI_MONITOR_REG0_HI 31
+#define HCI_MONITOR_REG0_SZ 32
+#define HCI_MONITOR_REG2_MSK 0xffffffff
+#define HCI_MONITOR_REG2_I_MSK 0x00000000
+#define HCI_MONITOR_REG2_SFT 0
+#define HCI_MONITOR_REG2_HI 31
+#define HCI_MONITOR_REG2_SZ 32
+#define HCI_MONITOR_REG3_MSK 0xffffffff
+#define HCI_MONITOR_REG3_I_MSK 0x00000000
+#define HCI_MONITOR_REG3_SFT 0
+#define HCI_MONITOR_REG3_HI 31
+#define HCI_MONITOR_REG3_SZ 32
+#define HCI_MONITOR_REG4_MSK 0xffffffff
+#define HCI_MONITOR_REG4_I_MSK 0x00000000
+#define HCI_MONITOR_REG4_SFT 0
+#define HCI_MONITOR_REG4_HI 31
+#define HCI_MONITOR_REG4_SZ 32
+#define HCI_MONITOR_REG5_MSK 0xffffffff
+#define HCI_MONITOR_REG5_I_MSK 0x00000000
+#define HCI_MONITOR_REG5_SFT 0
+#define HCI_MONITOR_REG5_HI 31
+#define HCI_MONITOR_REG5_SZ 32
+#define SDIO_TX_INVALID_CNT_MSK 0xffffffff
+#define SDIO_TX_INVALID_CNT_I_MSK 0x00000000
+#define SDIO_TX_INVALID_CNT_SFT 0
+#define SDIO_TX_INVALID_CNT_HI 31
+#define SDIO_TX_INVALID_CNT_SZ 32
+#define HCI_MB_MAX_CNT_MSK 0x000000ff
+#define HCI_MB_MAX_CNT_I_MSK 0xffffff00
+#define HCI_MB_MAX_CNT_SFT 0
+#define HCI_MB_MAX_CNT_HI 7
+#define HCI_MB_MAX_CNT_SZ 8
+#define HCI_PROC_CNT_MSK 0x0000ff00
+#define HCI_PROC_CNT_I_MSK 0xffff00ff
+#define HCI_PROC_CNT_SFT 8
+#define HCI_PROC_CNT_HI 15
+#define HCI_PROC_CNT_SZ 8
+#define SDIO_TRANS_CNT_MSK 0x00ff0000
+#define SDIO_TRANS_CNT_I_MSK 0xff00ffff
+#define SDIO_TRANS_CNT_SFT 16
+#define SDIO_TRANS_CNT_HI 23
+#define SDIO_TRANS_CNT_SZ 8
+#define TX_ON_DEMAND_LENGTH_MSK 0xffffffff
+#define TX_ON_DEMAND_LENGTH_I_MSK 0x00000000
+#define TX_ON_DEMAND_LENGTH_SFT 0
+#define TX_ON_DEMAND_LENGTH_HI 31
+#define TX_ON_DEMAND_LENGTH_SZ 32
+#define HCI_TX_ALLOC_CNT_MSK 0xffffffff
+#define HCI_TX_ALLOC_CNT_I_MSK 0x00000000
+#define HCI_TX_ALLOC_CNT_SFT 0
+#define HCI_TX_ALLOC_CNT_HI 31
+#define HCI_TX_ALLOC_CNT_SZ 32
+#define HCI_TX_ALLOC_TIME_MSK 0xffffffff
+#define HCI_TX_ALLOC_TIME_I_MSK 0x00000000
+#define HCI_TX_ALLOC_TIME_SFT 0
+#define HCI_TX_ALLOC_TIME_HI 31
+#define HCI_TX_ALLOC_TIME_SZ 32
+#define RX_PKT_TRAP_COUNTER_MSK 0xffffffff
+#define RX_PKT_TRAP_COUNTER_I_MSK 0x00000000
+#define RX_PKT_TRAP_COUNTER_SFT 0
+#define RX_PKT_TRAP_COUNTER_HI 31
+#define RX_PKT_TRAP_COUNTER_SZ 32
+#define TX_PKT_TRAP_COUNTER_MSK 0xffffffff
+#define TX_PKT_TRAP_COUNTER_I_MSK 0x00000000
+#define TX_PKT_TRAP_COUNTER_SFT 0
+#define TX_PKT_TRAP_COUNTER_HI 31
+#define TX_PKT_TRAP_COUNTER_SZ 32
+#define RX_PKT_DROP_COUNTER_MSK 0xffffffff
+#define RX_PKT_DROP_COUNTER_I_MSK 0x00000000
+#define RX_PKT_DROP_COUNTER_SFT 0
+#define RX_PKT_DROP_COUNTER_HI 31
+#define RX_PKT_DROP_COUNTER_SZ 32
+#define TX_PKT_DROP_COUNTER_MSK 0xffffffff
+#define TX_PKT_DROP_COUNTER_I_MSK 0x00000000
+#define TX_PKT_DROP_COUNTER_SFT 0
+#define TX_PKT_DROP_COUNTER_HI 31
+#define TX_PKT_DROP_COUNTER_SZ 32
+#define HOST_EVENT_COUNTER_MSK 0xffffffff
+#define HOST_EVENT_COUNTER_I_MSK 0x00000000
+#define HOST_EVENT_COUNTER_SFT 0
+#define HOST_EVENT_COUNTER_HI 31
+#define HOST_EVENT_COUNTER_SZ 32
+#define HOST_CMD_COUNTER_MSK 0xffffffff
+#define HOST_CMD_COUNTER_I_MSK 0x00000000
+#define HOST_CMD_COUNTER_SFT 0
+#define HOST_CMD_COUNTER_HI 31
+#define HOST_CMD_COUNTER_SZ 32
+#define RX_PKT_COUNTER_MSK 0xffffffff
+#define RX_PKT_COUNTER_I_MSK 0x00000000
+#define RX_PKT_COUNTER_SFT 0
+#define RX_PKT_COUNTER_HI 31
+#define RX_PKT_COUNTER_SZ 32
+#define TX_PKT_COUNTER_MSK 0xffffffff
+#define TX_PKT_COUNTER_I_MSK 0x00000000
+#define TX_PKT_COUNTER_SFT 0
+#define TX_PKT_COUNTER_HI 31
+#define TX_PKT_COUNTER_SZ 32
+#define HOST_RX_FAIL_COUNTER_MSK 0xffffffff
+#define HOST_RX_FAIL_COUNTER_I_MSK 0x00000000
+#define HOST_RX_FAIL_COUNTER_SFT 0
+#define HOST_RX_FAIL_COUNTER_HI 31
+#define HOST_RX_FAIL_COUNTER_SZ 32
+#define HOST_TX_FAIL_COUNTER_MSK 0xffffffff
+#define HOST_TX_FAIL_COUNTER_I_MSK 0x00000000
+#define HOST_TX_FAIL_COUNTER_SFT 0
+#define HOST_TX_FAIL_COUNTER_HI 31
+#define HOST_TX_FAIL_COUNTER_SZ 32
+#define CORRECT_RATE_REP_LEN_MSK 0x00000001
+#define CORRECT_RATE_REP_LEN_I_MSK 0xfffffffe
+#define CORRECT_RATE_REP_LEN_SFT 0
+#define CORRECT_RATE_REP_LEN_HI 0
+#define CORRECT_RATE_REP_LEN_SZ 1
+#define TX_PKT_SEND_TO_RX_MSK 0x00000001
+#define TX_PKT_SEND_TO_RX_I_MSK 0xfffffffe
+#define TX_PKT_SEND_TO_RX_SFT 0
+#define TX_PKT_SEND_TO_RX_HI 0
+#define TX_PKT_SEND_TO_RX_SZ 1
+#define PEERPS_REJECT_ENABLE_MSK 0x00000001
+#define PEERPS_REJECT_ENABLE_I_MSK 0xfffffffe
+#define PEERPS_REJECT_ENABLE_SFT 0
+#define PEERPS_REJECT_ENABLE_HI 0
+#define PEERPS_REJECT_ENABLE_SZ 1
+#define TRANS_FULL_PKT_AMPDU1P2_MSK 0x00000010
+#define TRANS_FULL_PKT_AMPDU1P2_I_MSK 0xffffffef
+#define TRANS_FULL_PKT_AMPDU1P2_SFT 4
+#define TRANS_FULL_PKT_AMPDU1P2_HI 4
+#define TRANS_FULL_PKT_AMPDU1P2_SZ 1
+#define TX_RX_TRAP_HW_ID_SELECT_ENABLE_MSK 0x00000001
+#define TX_RX_TRAP_HW_ID_SELECT_ENABLE_I_MSK 0xfffffffe
+#define TX_RX_TRAP_HW_ID_SELECT_ENABLE_SFT 0
+#define TX_RX_TRAP_HW_ID_SELECT_ENABLE_HI 0
+#define TX_RX_TRAP_HW_ID_SELECT_ENABLE_SZ 1
+#define TX_TRAP_HW_ID_MSK 0x000000f0
+#define TX_TRAP_HW_ID_I_MSK 0xffffff0f
+#define TX_TRAP_HW_ID_SFT 4
+#define TX_TRAP_HW_ID_HI 7
+#define TX_TRAP_HW_ID_SZ 4
+#define RX_TRAP_HW_ID_MSK 0x00000f00
+#define RX_TRAP_HW_ID_I_MSK 0xfffff0ff
+#define RX_TRAP_HW_ID_SFT 8
+#define RX_TRAP_HW_ID_HI 11
+#define RX_TRAP_HW_ID_SZ 4
+#define RX_DEBUG_HCI_EXP_0_MSK 0x00000001
+#define RX_DEBUG_HCI_EXP_0_I_MSK 0xfffffffe
+#define RX_DEBUG_HCI_EXP_0_SFT 0
+#define RX_DEBUG_HCI_EXP_0_HI 0
+#define RX_DEBUG_HCI_EXP_0_SZ 1
+#define RX_DEBUG_HCI_EXP_0_RND_MODE_MSK 0x00000030
+#define RX_DEBUG_HCI_EXP_0_RND_MODE_I_MSK 0xffffffcf
+#define RX_DEBUG_HCI_EXP_0_RND_MODE_SFT 4
+#define RX_DEBUG_HCI_EXP_0_RND_MODE_HI 5
+#define RX_DEBUG_HCI_EXP_0_RND_MODE_SZ 2
+#define RX_DEBUG_HCI_EXP_0_LENGHT_LIMIT_MIN_MSK 0x0000ffff
+#define RX_DEBUG_HCI_EXP_0_LENGHT_LIMIT_MIN_I_MSK 0xffff0000
+#define RX_DEBUG_HCI_EXP_0_LENGHT_LIMIT_MIN_SFT 0
+#define RX_DEBUG_HCI_EXP_0_LENGHT_LIMIT_MIN_HI 15
+#define RX_DEBUG_HCI_EXP_0_LENGHT_LIMIT_MIN_SZ 16
+#define RX_DEBUG_HCI_EXP_0_LENGHT_LIMIT_MAX_MSK 0xffff0000
+#define RX_DEBUG_HCI_EXP_0_LENGHT_LIMIT_MAX_I_MSK 0x0000ffff
+#define RX_DEBUG_HCI_EXP_0_LENGHT_LIMIT_MAX_SFT 16
+#define RX_DEBUG_HCI_EXP_0_LENGHT_LIMIT_MAX_HI 31
+#define RX_DEBUG_HCI_EXP_0_LENGHT_LIMIT_MAX_SZ 16
+#define RX_AGG_CNT_MSK 0x0000000f
+#define RX_AGG_CNT_I_MSK 0xfffffff0
+#define RX_AGG_CNT_SFT 0
+#define RX_AGG_CNT_HI 3
+#define RX_AGG_CNT_SZ 4
+#define RX_AGG_METHOD_3_MSK 0x00000080
+#define RX_AGG_METHOD_3_I_MSK 0xffffff7f
+#define RX_AGG_METHOD_3_SFT 7
+#define RX_AGG_METHOD_3_HI 7
+#define RX_AGG_METHOD_3_SZ 1
+#define RX_AGG_TIMER_RELOAD_VALUE_MSK 0xffff0000
+#define RX_AGG_TIMER_RELOAD_VALUE_I_MSK 0x0000ffff
+#define RX_AGG_TIMER_RELOAD_VALUE_SFT 16
+#define RX_AGG_TIMER_RELOAD_VALUE_HI 31
+#define RX_AGG_TIMER_RELOAD_VALUE_SZ 16
+#define CS_START_ADDR_MSK 0x0000ffff
+#define CS_START_ADDR_I_MSK 0xffff0000
+#define CS_START_ADDR_SFT 0
+#define CS_START_ADDR_HI 15
+#define CS_START_ADDR_SZ 16
+#define CS_PKT_ID_MSK 0x007f0000
+#define CS_PKT_ID_I_MSK 0xff80ffff
+#define CS_PKT_ID_SFT 16
+#define CS_PKT_ID_HI 22
+#define CS_PKT_ID_SZ 7
+#define ADD_LEN_MSK 0x0000ffff
+#define ADD_LEN_I_MSK 0xffff0000
+#define ADD_LEN_SFT 0
+#define ADD_LEN_HI 15
+#define ADD_LEN_SZ 16
+#define CS_ADDER_EN_MSK 0x00000001
+#define CS_ADDER_EN_I_MSK 0xfffffffe
+#define CS_ADDER_EN_SFT 0
+#define CS_ADDER_EN_HI 0
+#define CS_ADDER_EN_SZ 1
+#define PSEUDO_MSK 0x00000002
+#define PSEUDO_I_MSK 0xfffffffd
+#define PSEUDO_SFT 1
+#define PSEUDO_HI 1
+#define PSEUDO_SZ 1
+#define CALCULATE_MSK 0xffffffff
+#define CALCULATE_I_MSK 0x00000000
+#define CALCULATE_SFT 0
+#define CALCULATE_HI 31
+#define CALCULATE_SZ 32
+#define L4_LEN_MSK 0x0000ffff
+#define L4_LEN_I_MSK 0xffff0000
+#define L4_LEN_SFT 0
+#define L4_LEN_HI 15
+#define L4_LEN_SZ 16
+#define L4_PROTOL_MSK 0x00ff0000
+#define L4_PROTOL_I_MSK 0xff00ffff
+#define L4_PROTOL_SFT 16
+#define L4_PROTOL_HI 23
+#define L4_PROTOL_SZ 8
+#define CHECK_SUM_MSK 0x0000ffff
+#define CHECK_SUM_I_MSK 0xffff0000
+#define CHECK_SUM_SFT 0
+#define CHECK_SUM_HI 15
+#define CHECK_SUM_SZ 16
+#define RAND_EN_MSK 0x00000001
+#define RAND_EN_I_MSK 0xfffffffe
+#define RAND_EN_SFT 0
+#define RAND_EN_HI 0
+#define RAND_EN_SZ 1
+#define RAND_NUM_MSK 0xffffffff
+#define RAND_NUM_I_MSK 0x00000000
+#define RAND_NUM_SFT 0
+#define RAND_NUM_HI 31
+#define RAND_NUM_SZ 32
+#define MUL_OP1_MSK 0xffffffff
+#define MUL_OP1_I_MSK 0x00000000
+#define MUL_OP1_SFT 0
+#define MUL_OP1_HI 31
+#define MUL_OP1_SZ 32
+#define MUL_OP2_MSK 0xffffffff
+#define MUL_OP2_I_MSK 0x00000000
+#define MUL_OP2_SFT 0
+#define MUL_OP2_HI 31
+#define MUL_OP2_SZ 32
+#define MUL_ANS0_MSK 0xffffffff
+#define MUL_ANS0_I_MSK 0x00000000
+#define MUL_ANS0_SFT 0
+#define MUL_ANS0_HI 31
+#define MUL_ANS0_SZ 32
+#define MUL_ANS1_MSK 0xffffffff
+#define MUL_ANS1_I_MSK 0x00000000
+#define MUL_ANS1_SFT 0
+#define MUL_ANS1_HI 31
+#define MUL_ANS1_SZ 32
+#define RD_ADDR_MSK 0x0000ffff
+#define RD_ADDR_I_MSK 0xffff0000
+#define RD_ADDR_SFT 0
+#define RD_ADDR_HI 15
+#define RD_ADDR_SZ 16
+#define RD_ID_MSK 0x007f0000
+#define RD_ID_I_MSK 0xff80ffff
+#define RD_ID_SFT 16
+#define RD_ID_HI 22
+#define RD_ID_SZ 7
+#define WR_ADDR_MSK 0x0000ffff
+#define WR_ADDR_I_MSK 0xffff0000
+#define WR_ADDR_SFT 0
+#define WR_ADDR_HI 15
+#define WR_ADDR_SZ 16
+#define WR_ID_MSK 0x007f0000
+#define WR_ID_I_MSK 0xff80ffff
+#define WR_ID_SFT 16
+#define WR_ID_HI 22
+#define WR_ID_SZ 7
+#define LEN_MSK 0x0000ffff
+#define LEN_I_MSK 0xffff0000
+#define LEN_SFT 0
+#define LEN_HI 15
+#define LEN_SZ 16
+#define CLR_MSK 0x00000001
+#define CLR_I_MSK 0xfffffffe
+#define CLR_SFT 0
+#define CLR_HI 0
+#define CLR_SZ 1
+#define PHY_MODE_MSK 0x00000003
+#define PHY_MODE_I_MSK 0xfffffffc
+#define PHY_MODE_SFT 0
+#define PHY_MODE_HI 1
+#define PHY_MODE_SZ 2
+#define SHRT_PREAM_MSK 0x00000004
+#define SHRT_PREAM_I_MSK 0xfffffffb
+#define SHRT_PREAM_SFT 2
+#define SHRT_PREAM_HI 2
+#define SHRT_PREAM_SZ 1
+#define SHRT_GI_MSK 0x00000008
+#define SHRT_GI_I_MSK 0xfffffff7
+#define SHRT_GI_SFT 3
+#define SHRT_GI_HI 3
+#define SHRT_GI_SZ 1
+#define DATA_RATE_MSK 0x000007f0
+#define DATA_RATE_I_MSK 0xfffff80f
+#define DATA_RATE_SFT 4
+#define DATA_RATE_HI 10
+#define DATA_RATE_SZ 7
+#define MCS_MSK 0x00007000
+#define MCS_I_MSK 0xffff8fff
+#define MCS_SFT 12
+#define MCS_HI 14
+#define MCS_SZ 3
+#define FRAME_LEN_MSK 0xffff0000
+#define FRAME_LEN_I_MSK 0x0000ffff
+#define FRAME_LEN_SFT 16
+#define FRAME_LEN_HI 31
+#define FRAME_LEN_SZ 16
+#define DURATION_MSK 0x0000ffff
+#define DURATION_I_MSK 0xffff0000
+#define DURATION_SFT 0
+#define DURATION_HI 15
+#define DURATION_SZ 16
+#define SHA_DST_ADDR_MSK 0xffffffff
+#define SHA_DST_ADDR_I_MSK 0x00000000
+#define SHA_DST_ADDR_SFT 0
+#define SHA_DST_ADDR_HI 31
+#define SHA_DST_ADDR_SZ 32
+#define SHA_SRC_ADDR_MSK 0xffffffff
+#define SHA_SRC_ADDR_I_MSK 0x00000000
+#define SHA_SRC_ADDR_SFT 0
+#define SHA_SRC_ADDR_HI 31
+#define SHA_SRC_ADDR_SZ 32
+#define SHA_BUSY_MSK 0x00000001
+#define SHA_BUSY_I_MSK 0xfffffffe
+#define SHA_BUSY_SFT 0
+#define SHA_BUSY_HI 0
+#define SHA_BUSY_SZ 1
+#define SHA_ENDIAN_MSK 0x00000002
+#define SHA_ENDIAN_I_MSK 0xfffffffd
+#define SHA_ENDIAN_SFT 1
+#define SHA_ENDIAN_HI 1
+#define SHA_ENDIAN_SZ 1
+#define EFS_CLKFREQ_MSK 0x00000fff
+#define EFS_CLKFREQ_I_MSK 0xfffff000
+#define EFS_CLKFREQ_SFT 0
+#define EFS_CLKFREQ_HI 11
+#define EFS_CLKFREQ_SZ 12
+#define EFS_VDDQ_EN_LOW_ACTIVE_MSK 0x00010000
+#define EFS_VDDQ_EN_LOW_ACTIVE_I_MSK 0xfffeffff
+#define EFS_VDDQ_EN_LOW_ACTIVE_SFT 16
+#define EFS_VDDQ_EN_LOW_ACTIVE_HI 16
+#define EFS_VDDQ_EN_LOW_ACTIVE_SZ 1
+#define EFS_CLKFREQ_RD_MSK 0x0ff00000
+#define EFS_CLKFREQ_RD_I_MSK 0xf00fffff
+#define EFS_CLKFREQ_RD_SFT 20
+#define EFS_CLKFREQ_RD_HI 27
+#define EFS_CLKFREQ_RD_SZ 8
+#define EFS_PRE_RD_MSK 0xf0000000
+#define EFS_PRE_RD_I_MSK 0x0fffffff
+#define EFS_PRE_RD_SFT 28
+#define EFS_PRE_RD_HI 31
+#define EFS_PRE_RD_SZ 4
+#define EFS_LDO_ON_MSK 0x0000ffff
+#define EFS_LDO_ON_I_MSK 0xffff0000
+#define EFS_LDO_ON_SFT 0
+#define EFS_LDO_ON_HI 15
+#define EFS_LDO_ON_SZ 16
+#define EFS_LDO_OFF_MSK 0xffff0000
+#define EFS_LDO_OFF_I_MSK 0x0000ffff
+#define EFS_LDO_OFF_SFT 16
+#define EFS_LDO_OFF_HI 31
+#define EFS_LDO_OFF_SZ 16
+#define EFS_RD_FLAG_MSK 0x00000001
+#define EFS_RD_FLAG_I_MSK 0xfffffffe
+#define EFS_RD_FLAG_SFT 0
+#define EFS_RD_FLAG_HI 0
+#define EFS_RD_FLAG_SZ 1
+#define EFS_PROGRESS_DONE_MSK 0x00000001
+#define EFS_PROGRESS_DONE_I_MSK 0xfffffffe
+#define EFS_PROGRESS_DONE_SFT 0
+#define EFS_PROGRESS_DONE_HI 0
+#define EFS_PROGRESS_DONE_SZ 1
+#define EFS_WR_KICK_MSK 0x00000001
+#define EFS_WR_KICK_I_MSK 0xfffffffe
+#define EFS_WR_KICK_SFT 0
+#define EFS_WR_KICK_HI 0
+#define EFS_WR_KICK_SZ 1
+#define EFS_RD_KICK_MSK 0x00000001
+#define EFS_RD_KICK_I_MSK 0xfffffffe
+#define EFS_RD_KICK_SFT 0
+#define EFS_RD_KICK_HI 0
+#define EFS_RD_KICK_SZ 1
+#define EFS_VDDQ_EN_MSK 0x00000001
+#define EFS_VDDQ_EN_I_MSK 0xfffffffe
+#define EFS_VDDQ_EN_SFT 0
+#define EFS_VDDQ_EN_HI 0
+#define EFS_VDDQ_EN_SZ 1
+#define EFS_BYTE_0_MSK 0x000000ff
+#define EFS_BYTE_0_I_MSK 0xffffff00
+#define EFS_BYTE_0_SFT 0
+#define EFS_BYTE_0_HI 7
+#define EFS_BYTE_0_SZ 8
+#define EFS_BYTE_1_MSK 0x0000ff00
+#define EFS_BYTE_1_I_MSK 0xffff00ff
+#define EFS_BYTE_1_SFT 8
+#define EFS_BYTE_1_HI 15
+#define EFS_BYTE_1_SZ 8
+#define EFS_BYTE_2_MSK 0x00ff0000
+#define EFS_BYTE_2_I_MSK 0xff00ffff
+#define EFS_BYTE_2_SFT 16
+#define EFS_BYTE_2_HI 23
+#define EFS_BYTE_2_SZ 8
+#define EFS_BYTE_3_MSK 0xff000000
+#define EFS_BYTE_3_I_MSK 0x00ffffff
+#define EFS_BYTE_3_SFT 24
+#define EFS_BYTE_3_HI 31
+#define EFS_BYTE_3_SZ 8
+#define EFS_BYTE_4_MSK 0x000000ff
+#define EFS_BYTE_4_I_MSK 0xffffff00
+#define EFS_BYTE_4_SFT 0
+#define EFS_BYTE_4_HI 7
+#define EFS_BYTE_4_SZ 8
+#define EFS_BYTE_5_MSK 0x0000ff00
+#define EFS_BYTE_5_I_MSK 0xffff00ff
+#define EFS_BYTE_5_SFT 8
+#define EFS_BYTE_5_HI 15
+#define EFS_BYTE_5_SZ 8
+#define EFS_BYTE_6_MSK 0x00ff0000
+#define EFS_BYTE_6_I_MSK 0xff00ffff
+#define EFS_BYTE_6_SFT 16
+#define EFS_BYTE_6_HI 23
+#define EFS_BYTE_6_SZ 8
+#define EFS_BYTE_7_MSK 0xff000000
+#define EFS_BYTE_7_I_MSK 0x00ffffff
+#define EFS_BYTE_7_SFT 24
+#define EFS_BYTE_7_HI 31
+#define EFS_BYTE_7_SZ 8
+#define EFS_BYTE_8_MSK 0x000000ff
+#define EFS_BYTE_8_I_MSK 0xffffff00
+#define EFS_BYTE_8_SFT 0
+#define EFS_BYTE_8_HI 7
+#define EFS_BYTE_8_SZ 8
+#define EFS_BYTE_9_MSK 0x0000ff00
+#define EFS_BYTE_9_I_MSK 0xffff00ff
+#define EFS_BYTE_9_SFT 8
+#define EFS_BYTE_9_HI 15
+#define EFS_BYTE_9_SZ 8
+#define EFS_BYTE_10_MSK 0x00ff0000
+#define EFS_BYTE_10_I_MSK 0xff00ffff
+#define EFS_BYTE_10_SFT 16
+#define EFS_BYTE_10_HI 23
+#define EFS_BYTE_10_SZ 8
+#define EFS_BYTE_11_MSK 0xff000000
+#define EFS_BYTE_11_I_MSK 0x00ffffff
+#define EFS_BYTE_11_SFT 24
+#define EFS_BYTE_11_HI 31
+#define EFS_BYTE_11_SZ 8
+#define EFS_BYTE_12_MSK 0x000000ff
+#define EFS_BYTE_12_I_MSK 0xffffff00
+#define EFS_BYTE_12_SFT 0
+#define EFS_BYTE_12_HI 7
+#define EFS_BYTE_12_SZ 8
+#define EFS_BYTE_13_MSK 0x0000ff00
+#define EFS_BYTE_13_I_MSK 0xffff00ff
+#define EFS_BYTE_13_SFT 8
+#define EFS_BYTE_13_HI 15
+#define EFS_BYTE_13_SZ 8
+#define EFS_BYTE_14_MSK 0x00ff0000
+#define EFS_BYTE_14_I_MSK 0xff00ffff
+#define EFS_BYTE_14_SFT 16
+#define EFS_BYTE_14_HI 23
+#define EFS_BYTE_14_SZ 8
+#define EFS_BYTE_15_MSK 0xff000000
+#define EFS_BYTE_15_I_MSK 0x00ffffff
+#define EFS_BYTE_15_SFT 24
+#define EFS_BYTE_15_HI 31
+#define EFS_BYTE_15_SZ 8
+#define EFS_BYTE_16_MSK 0x000000ff
+#define EFS_BYTE_16_I_MSK 0xffffff00
+#define EFS_BYTE_16_SFT 0
+#define EFS_BYTE_16_HI 7
+#define EFS_BYTE_16_SZ 8
+#define EFS_BYTE_17_MSK 0x0000ff00
+#define EFS_BYTE_17_I_MSK 0xffff00ff
+#define EFS_BYTE_17_SFT 8
+#define EFS_BYTE_17_HI 15
+#define EFS_BYTE_17_SZ 8
+#define EFS_BYTE_18_MSK 0x00ff0000
+#define EFS_BYTE_18_I_MSK 0xff00ffff
+#define EFS_BYTE_18_SFT 16
+#define EFS_BYTE_18_HI 23
+#define EFS_BYTE_18_SZ 8
+#define EFS_BYTE_19_MSK 0xff000000
+#define EFS_BYTE_19_I_MSK 0x00ffffff
+#define EFS_BYTE_19_SFT 24
+#define EFS_BYTE_19_HI 31
+#define EFS_BYTE_19_SZ 8
+#define EFS_BYTE_20_MSK 0x000000ff
+#define EFS_BYTE_20_I_MSK 0xffffff00
+#define EFS_BYTE_20_SFT 0
+#define EFS_BYTE_20_HI 7
+#define EFS_BYTE_20_SZ 8
+#define EFS_BYTE_21_MSK 0x0000ff00
+#define EFS_BYTE_21_I_MSK 0xffff00ff
+#define EFS_BYTE_21_SFT 8
+#define EFS_BYTE_21_HI 15
+#define EFS_BYTE_21_SZ 8
+#define EFS_BYTE_22_MSK 0x00ff0000
+#define EFS_BYTE_22_I_MSK 0xff00ffff
+#define EFS_BYTE_22_SFT 16
+#define EFS_BYTE_22_HI 23
+#define EFS_BYTE_22_SZ 8
+#define EFS_BYTE_23_MSK 0xff000000
+#define EFS_BYTE_23_I_MSK 0x00ffffff
+#define EFS_BYTE_23_SFT 24
+#define EFS_BYTE_23_HI 31
+#define EFS_BYTE_23_SZ 8
+#define EFS_BYTE_24_MSK 0x000000ff
+#define EFS_BYTE_24_I_MSK 0xffffff00
+#define EFS_BYTE_24_SFT 0
+#define EFS_BYTE_24_HI 7
+#define EFS_BYTE_24_SZ 8
+#define EFS_BYTE_25_MSK 0x0000ff00
+#define EFS_BYTE_25_I_MSK 0xffff00ff
+#define EFS_BYTE_25_SFT 8
+#define EFS_BYTE_25_HI 15
+#define EFS_BYTE_25_SZ 8
+#define EFS_BYTE_26_MSK 0x00ff0000
+#define EFS_BYTE_26_I_MSK 0xff00ffff
+#define EFS_BYTE_26_SFT 16
+#define EFS_BYTE_26_HI 23
+#define EFS_BYTE_26_SZ 8
+#define EFS_BYTE_27_MSK 0xff000000
+#define EFS_BYTE_27_I_MSK 0x00ffffff
+#define EFS_BYTE_27_SFT 24
+#define EFS_BYTE_27_HI 31
+#define EFS_BYTE_27_SZ 8
+#define EFS_BYTE_28_MSK 0x000000ff
+#define EFS_BYTE_28_I_MSK 0xffffff00
+#define EFS_BYTE_28_SFT 0
+#define EFS_BYTE_28_HI 7
+#define EFS_BYTE_28_SZ 8
+#define EFS_BYTE_29_MSK 0x0000ff00
+#define EFS_BYTE_29_I_MSK 0xffff00ff
+#define EFS_BYTE_29_SFT 8
+#define EFS_BYTE_29_HI 15
+#define EFS_BYTE_29_SZ 8
+#define EFS_BYTE_30_MSK 0x00ff0000
+#define EFS_BYTE_30_I_MSK 0xff00ffff
+#define EFS_BYTE_30_SFT 16
+#define EFS_BYTE_30_HI 23
+#define EFS_BYTE_30_SZ 8
+#define EFS_BYTE_31_MSK 0xff000000
+#define EFS_BYTE_31_I_MSK 0x00ffffff
+#define EFS_BYTE_31_SFT 24
+#define EFS_BYTE_31_HI 31
+#define EFS_BYTE_31_SZ 8
+#define SPI_M_FRONT_DLY_MSK 0x0000ffff
+#define SPI_M_FRONT_DLY_I_MSK 0xffff0000
+#define SPI_M_FRONT_DLY_SFT 0
+#define SPI_M_FRONT_DLY_HI 15
+#define SPI_M_FRONT_DLY_SZ 16
+#define SPI_M_BACK_DLY_MSK 0xffff0000
+#define SPI_M_BACK_DLY_I_MSK 0x0000ffff
+#define SPI_M_BACK_DLY_SFT 16
+#define SPI_M_BACK_DLY_HI 31
+#define SPI_M_BACK_DLY_SZ 16
+#define SPI_CLK_DIV_MSK 0x0000ffff
+#define SPI_CLK_DIV_I_MSK 0xffff0000
+#define SPI_CLK_DIV_SFT 0
+#define SPI_CLK_DIV_HI 15
+#define SPI_CLK_DIV_SZ 16
+#define SPI_MASTER_BUSY_MSK 0x00000001
+#define SPI_MASTER_BUSY_I_MSK 0xfffffffe
+#define SPI_MASTER_BUSY_SFT 0
+#define SPI_MASTER_BUSY_HI 0
+#define SPI_MASTER_BUSY_SZ 1
+#define SPI_CLR_MSK 0x00000001
+#define SPI_CLR_I_MSK 0xfffffffe
+#define SPI_CLR_SFT 0
+#define SPI_CLR_HI 0
+#define SPI_CLR_SZ 1
+#define CPOL_MSK 0x00000001
+#define CPOL_I_MSK 0xfffffffe
+#define CPOL_SFT 0
+#define CPOL_HI 0
+#define CPOL_SZ 1
+#define CPHA_MSK 0x00000002
+#define CPHA_I_MSK 0xfffffffd
+#define CPHA_SFT 1
+#define CPHA_HI 1
+#define CPHA_SZ 1
+#define CSPOL_MSK 0x00000001
+#define CSPOL_I_MSK 0xfffffffe
+#define CSPOL_SFT 0
+#define CSPOL_HI 0
+#define CSPOL_SZ 1
+#define INV_DATA_MSK 0x00000002
+#define INV_DATA_I_MSK 0xfffffffd
+#define INV_DATA_SFT 1
+#define INV_DATA_HI 1
+#define INV_DATA_SZ 1
+#define FAST_CLK_MSK 0x00000004
+#define FAST_CLK_I_MSK 0xfffffffb
+#define FAST_CLK_SFT 2
+#define FAST_CLK_HI 2
+#define FAST_CLK_SZ 1
+#define AUTO_CSN_MSK 0x00000008
+#define AUTO_CSN_I_MSK 0xfffffff7
+#define AUTO_CSN_SFT 3
+#define AUTO_CSN_HI 3
+#define AUTO_CSN_SZ 1
+#define THREE_WIRE_MSK 0x000003f0
+#define THREE_WIRE_I_MSK 0xfffffc0f
+#define THREE_WIRE_SFT 4
+#define THREE_WIRE_HI 9
+#define THREE_WIRE_SZ 6
+#define ENDIAN_MSK 0x00000400
+#define ENDIAN_I_MSK 0xfffffbff
+#define ENDIAN_SFT 10
+#define ENDIAN_HI 10
+#define ENDIAN_SZ 1
+#define EARLY_SAMPLE_MSK 0x00000800
+#define EARLY_SAMPLE_I_MSK 0xfffff7ff
+#define EARLY_SAMPLE_SFT 11
+#define EARLY_SAMPLE_HI 11
+#define EARLY_SAMPLE_SZ 1
+#define SPI_CSN_MSK 0x00000001
+#define SPI_CSN_I_MSK 0xfffffffe
+#define SPI_CSN_SFT 0
+#define SPI_CSN_HI 0
+#define SPI_CSN_SZ 1
+#define CMD_LEN_SPIMAS_MSK 0x0000ffff
+#define CMD_LEN_SPIMAS_I_MSK 0xffff0000
+#define CMD_LEN_SPIMAS_SFT 0
+#define CMD_LEN_SPIMAS_HI 15
+#define CMD_LEN_SPIMAS_SZ 16
+#define MRX_MCAST_TB0_31_0_MSK 0xffffffff
+#define MRX_MCAST_TB0_31_0_I_MSK 0x00000000
+#define MRX_MCAST_TB0_31_0_SFT 0
+#define MRX_MCAST_TB0_31_0_HI 31
+#define MRX_MCAST_TB0_31_0_SZ 32
+#define MRX_MCAST_TB0_47_32_MSK 0x0000ffff
+#define MRX_MCAST_TB0_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_TB0_47_32_SFT 0
+#define MRX_MCAST_TB0_47_32_HI 15
+#define MRX_MCAST_TB0_47_32_SZ 16
+#define MRX_MCAST_MASK0_31_0_MSK 0xffffffff
+#define MRX_MCAST_MASK0_31_0_I_MSK 0x00000000
+#define MRX_MCAST_MASK0_31_0_SFT 0
+#define MRX_MCAST_MASK0_31_0_HI 31
+#define MRX_MCAST_MASK0_31_0_SZ 32
+#define MRX_MCAST_MASK0_47_32_MSK 0x0000ffff
+#define MRX_MCAST_MASK0_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_MASK0_47_32_SFT 0
+#define MRX_MCAST_MASK0_47_32_HI 15
+#define MRX_MCAST_MASK0_47_32_SZ 16
+#define MRX_MCAST_CTRL_0_MSK 0x00000003
+#define MRX_MCAST_CTRL_0_I_MSK 0xfffffffc
+#define MRX_MCAST_CTRL_0_SFT 0
+#define MRX_MCAST_CTRL_0_HI 1
+#define MRX_MCAST_CTRL_0_SZ 2
+#define MRX_MCAST_TB1_31_0_MSK 0xffffffff
+#define MRX_MCAST_TB1_31_0_I_MSK 0x00000000
+#define MRX_MCAST_TB1_31_0_SFT 0
+#define MRX_MCAST_TB1_31_0_HI 31
+#define MRX_MCAST_TB1_31_0_SZ 32
+#define MRX_MCAST_TB1_47_32_MSK 0x0000ffff
+#define MRX_MCAST_TB1_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_TB1_47_32_SFT 0
+#define MRX_MCAST_TB1_47_32_HI 15
+#define MRX_MCAST_TB1_47_32_SZ 16
+#define MRX_MCAST_MASK1_31_0_MSK 0xffffffff
+#define MRX_MCAST_MASK1_31_0_I_MSK 0x00000000
+#define MRX_MCAST_MASK1_31_0_SFT 0
+#define MRX_MCAST_MASK1_31_0_HI 31
+#define MRX_MCAST_MASK1_31_0_SZ 32
+#define MRX_MCAST_MASK1_47_32_MSK 0x0000ffff
+#define MRX_MCAST_MASK1_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_MASK1_47_32_SFT 0
+#define MRX_MCAST_MASK1_47_32_HI 15
+#define MRX_MCAST_MASK1_47_32_SZ 16
+#define MRX_MCAST_CTRL_1_MSK 0x00000003
+#define MRX_MCAST_CTRL_1_I_MSK 0xfffffffc
+#define MRX_MCAST_CTRL_1_SFT 0
+#define MRX_MCAST_CTRL_1_HI 1
+#define MRX_MCAST_CTRL_1_SZ 2
+#define MRX_MCAST_TB2_31_0_MSK 0xffffffff
+#define MRX_MCAST_TB2_31_0_I_MSK 0x00000000
+#define MRX_MCAST_TB2_31_0_SFT 0
+#define MRX_MCAST_TB2_31_0_HI 31
+#define MRX_MCAST_TB2_31_0_SZ 32
+#define MRX_MCAST_TB2_47_32_MSK 0x0000ffff
+#define MRX_MCAST_TB2_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_TB2_47_32_SFT 0
+#define MRX_MCAST_TB2_47_32_HI 15
+#define MRX_MCAST_TB2_47_32_SZ 16
+#define MRX_MCAST_MASK2_31_0_MSK 0xffffffff
+#define MRX_MCAST_MASK2_31_0_I_MSK 0x00000000
+#define MRX_MCAST_MASK2_31_0_SFT 0
+#define MRX_MCAST_MASK2_31_0_HI 31
+#define MRX_MCAST_MASK2_31_0_SZ 32
+#define MRX_MCAST_MASK2_47_32_MSK 0x0000ffff
+#define MRX_MCAST_MASK2_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_MASK2_47_32_SFT 0
+#define MRX_MCAST_MASK2_47_32_HI 15
+#define MRX_MCAST_MASK2_47_32_SZ 16
+#define MRX_MCAST_CTRL_2_MSK 0x00000003
+#define MRX_MCAST_CTRL_2_I_MSK 0xfffffffc
+#define MRX_MCAST_CTRL_2_SFT 0
+#define MRX_MCAST_CTRL_2_HI 1
+#define MRX_MCAST_CTRL_2_SZ 2
+#define MRX_MCAST_TB3_31_0_MSK 0xffffffff
+#define MRX_MCAST_TB3_31_0_I_MSK 0x00000000
+#define MRX_MCAST_TB3_31_0_SFT 0
+#define MRX_MCAST_TB3_31_0_HI 31
+#define MRX_MCAST_TB3_31_0_SZ 32
+#define MRX_MCAST_TB3_47_32_MSK 0x0000ffff
+#define MRX_MCAST_TB3_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_TB3_47_32_SFT 0
+#define MRX_MCAST_TB3_47_32_HI 15
+#define MRX_MCAST_TB3_47_32_SZ 16
+#define MRX_MCAST_MASK3_31_0_MSK 0xffffffff
+#define MRX_MCAST_MASK3_31_0_I_MSK 0x00000000
+#define MRX_MCAST_MASK3_31_0_SFT 0
+#define MRX_MCAST_MASK3_31_0_HI 31
+#define MRX_MCAST_MASK3_31_0_SZ 32
+#define MRX_MCAST_MASK3_47_32_MSK 0x0000ffff
+#define MRX_MCAST_MASK3_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_MASK3_47_32_SFT 0
+#define MRX_MCAST_MASK3_47_32_HI 15
+#define MRX_MCAST_MASK3_47_32_SZ 16
+#define MRX_MCAST_CTRL_3_MSK 0x00000003
+#define MRX_MCAST_CTRL_3_I_MSK 0xfffffffc
+#define MRX_MCAST_CTRL_3_SFT 0
+#define MRX_MCAST_CTRL_3_HI 1
+#define MRX_MCAST_CTRL_3_SZ 2
+#define MRX_PHY_INFO_MSK 0xffffffff
+#define MRX_PHY_INFO_I_MSK 0x00000000
+#define MRX_PHY_INFO_SFT 0
+#define MRX_PHY_INFO_HI 31
+#define MRX_PHY_INFO_SZ 32
+#define DBG_BA_TYPE_MSK 0x0000003f
+#define DBG_BA_TYPE_I_MSK 0xffffffc0
+#define DBG_BA_TYPE_SFT 0
+#define DBG_BA_TYPE_HI 5
+#define DBG_BA_TYPE_SZ 6
+#define DBG_BA_SEQ_MSK 0x000fff00
+#define DBG_BA_SEQ_I_MSK 0xfff000ff
+#define DBG_BA_SEQ_SFT 8
+#define DBG_BA_SEQ_HI 19
+#define DBG_BA_SEQ_SZ 12
+#define MRX_FLT_TB0_MSK 0x00007fff
+#define MRX_FLT_TB0_I_MSK 0xffff8000
+#define MRX_FLT_TB0_SFT 0
+#define MRX_FLT_TB0_HI 14
+#define MRX_FLT_TB0_SZ 15
+#define MRX_FLT_TB1_MSK 0x00007fff
+#define MRX_FLT_TB1_I_MSK 0xffff8000
+#define MRX_FLT_TB1_SFT 0
+#define MRX_FLT_TB1_HI 14
+#define MRX_FLT_TB1_SZ 15
+#define MRX_FLT_TB2_MSK 0x00007fff
+#define MRX_FLT_TB2_I_MSK 0xffff8000
+#define MRX_FLT_TB2_SFT 0
+#define MRX_FLT_TB2_HI 14
+#define MRX_FLT_TB2_SZ 15
+#define MRX_FLT_TB3_MSK 0x00007fff
+#define MRX_FLT_TB3_I_MSK 0xffff8000
+#define MRX_FLT_TB3_SFT 0
+#define MRX_FLT_TB3_HI 14
+#define MRX_FLT_TB3_SZ 15
+#define MRX_FLT_TB4_MSK 0x00007fff
+#define MRX_FLT_TB4_I_MSK 0xffff8000
+#define MRX_FLT_TB4_SFT 0
+#define MRX_FLT_TB4_HI 14
+#define MRX_FLT_TB4_SZ 15
+#define MRX_FLT_TB5_MSK 0x00007fff
+#define MRX_FLT_TB5_I_MSK 0xffff8000
+#define MRX_FLT_TB5_SFT 0
+#define MRX_FLT_TB5_HI 14
+#define MRX_FLT_TB5_SZ 15
+#define MRX_FLT_TB6_MSK 0x00007fff
+#define MRX_FLT_TB6_I_MSK 0xffff8000
+#define MRX_FLT_TB6_SFT 0
+#define MRX_FLT_TB6_HI 14
+#define MRX_FLT_TB6_SZ 15
+#define MRX_FLT_TB7_MSK 0x00007fff
+#define MRX_FLT_TB7_I_MSK 0xffff8000
+#define MRX_FLT_TB7_SFT 0
+#define MRX_FLT_TB7_HI 14
+#define MRX_FLT_TB7_SZ 15
+#define MRX_FLT_TB8_MSK 0x00007fff
+#define MRX_FLT_TB8_I_MSK 0xffff8000
+#define MRX_FLT_TB8_SFT 0
+#define MRX_FLT_TB8_HI 14
+#define MRX_FLT_TB8_SZ 15
+#define MRX_FLT_TB9_MSK 0x00007fff
+#define MRX_FLT_TB9_I_MSK 0xffff8000
+#define MRX_FLT_TB9_SFT 0
+#define MRX_FLT_TB9_HI 14
+#define MRX_FLT_TB9_SZ 15
+#define MRX_FLT_TB10_MSK 0x00007fff
+#define MRX_FLT_TB10_I_MSK 0xffff8000
+#define MRX_FLT_TB10_SFT 0
+#define MRX_FLT_TB10_HI 14
+#define MRX_FLT_TB10_SZ 15
+#define MRX_FLT_TB11_MSK 0x00007fff
+#define MRX_FLT_TB11_I_MSK 0xffff8000
+#define MRX_FLT_TB11_SFT 0
+#define MRX_FLT_TB11_HI 14
+#define MRX_FLT_TB11_SZ 15
+#define MRX_FLT_TB12_MSK 0x00007fff
+#define MRX_FLT_TB12_I_MSK 0xffff8000
+#define MRX_FLT_TB12_SFT 0
+#define MRX_FLT_TB12_HI 14
+#define MRX_FLT_TB12_SZ 15
+#define MRX_FLT_TB13_MSK 0x00007fff
+#define MRX_FLT_TB13_I_MSK 0xffff8000
+#define MRX_FLT_TB13_SFT 0
+#define MRX_FLT_TB13_HI 14
+#define MRX_FLT_TB13_SZ 15
+#define MRX_FLT_TB14_MSK 0x00007fff
+#define MRX_FLT_TB14_I_MSK 0xffff8000
+#define MRX_FLT_TB14_SFT 0
+#define MRX_FLT_TB14_HI 14
+#define MRX_FLT_TB14_SZ 15
+#define MRX_FLT_TB15_MSK 0x00007fff
+#define MRX_FLT_TB15_I_MSK 0xffff8000
+#define MRX_FLT_TB15_SFT 0
+#define MRX_FLT_TB15_HI 14
+#define MRX_FLT_TB15_SZ 15
+#define MRX_FLT_EN0_MSK 0x0000ffff
+#define MRX_FLT_EN0_I_MSK 0xffff0000
+#define MRX_FLT_EN0_SFT 0
+#define MRX_FLT_EN0_HI 15
+#define MRX_FLT_EN0_SZ 16
+#define MRX_FLT_EN1_MSK 0x0000ffff
+#define MRX_FLT_EN1_I_MSK 0xffff0000
+#define MRX_FLT_EN1_SFT 0
+#define MRX_FLT_EN1_HI 15
+#define MRX_FLT_EN1_SZ 16
+#define MRX_FLT_EN2_MSK 0x0000ffff
+#define MRX_FLT_EN2_I_MSK 0xffff0000
+#define MRX_FLT_EN2_SFT 0
+#define MRX_FLT_EN2_HI 15
+#define MRX_FLT_EN2_SZ 16
+#define MRX_FLT_EN3_MSK 0x0000ffff
+#define MRX_FLT_EN3_I_MSK 0xffff0000
+#define MRX_FLT_EN3_SFT 0
+#define MRX_FLT_EN3_HI 15
+#define MRX_FLT_EN3_SZ 16
+#define MRX_FLT_EN4_MSK 0x0000ffff
+#define MRX_FLT_EN4_I_MSK 0xffff0000
+#define MRX_FLT_EN4_SFT 0
+#define MRX_FLT_EN4_HI 15
+#define MRX_FLT_EN4_SZ 16
+#define MRX_FLT_EN5_MSK 0x0000ffff
+#define MRX_FLT_EN5_I_MSK 0xffff0000
+#define MRX_FLT_EN5_SFT 0
+#define MRX_FLT_EN5_HI 15
+#define MRX_FLT_EN5_SZ 16
+#define MRX_FLT_EN6_MSK 0x0000ffff
+#define MRX_FLT_EN6_I_MSK 0xffff0000
+#define MRX_FLT_EN6_SFT 0
+#define MRX_FLT_EN6_HI 15
+#define MRX_FLT_EN6_SZ 16
+#define MRX_FLT_EN7_MSK 0x0000ffff
+#define MRX_FLT_EN7_I_MSK 0xffff0000
+#define MRX_FLT_EN7_SFT 0
+#define MRX_FLT_EN7_HI 15
+#define MRX_FLT_EN7_SZ 16
+#define MRX_FLT_EN8_MSK 0x0000ffff
+#define MRX_FLT_EN8_I_MSK 0xffff0000
+#define MRX_FLT_EN8_SFT 0
+#define MRX_FLT_EN8_HI 15
+#define MRX_FLT_EN8_SZ 16
+#define MRX_LEN_FLT_MSK 0x0000ffff
+#define MRX_LEN_FLT_I_MSK 0xffff0000
+#define MRX_LEN_FLT_SFT 0
+#define MRX_LEN_FLT_HI 15
+#define MRX_LEN_FLT_SZ 16
+#define RX_FLOW_DATA_MSK 0xffffffff
+#define RX_FLOW_DATA_I_MSK 0x00000000
+#define RX_FLOW_DATA_SFT 0
+#define RX_FLOW_DATA_HI 31
+#define RX_FLOW_DATA_SZ 32
+#define RX_FLOW_MNG_MSK 0x0000ffff
+#define RX_FLOW_MNG_I_MSK 0xffff0000
+#define RX_FLOW_MNG_SFT 0
+#define RX_FLOW_MNG_HI 15
+#define RX_FLOW_MNG_SZ 16
+#define RX_FLOW_CTRL_MSK 0x0000ffff
+#define RX_FLOW_CTRL_I_MSK 0xffff0000
+#define RX_FLOW_CTRL_SFT 0
+#define RX_FLOW_CTRL_HI 15
+#define RX_FLOW_CTRL_SZ 16
+#define MRX_STP_EN_MSK 0x00000001
+#define MRX_STP_EN_I_MSK 0xfffffffe
+#define MRX_STP_EN_SFT 0
+#define MRX_STP_EN_HI 0
+#define MRX_STP_EN_SZ 1
+#define MRX_STP_OFST_MSK 0x0000ff00
+#define MRX_STP_OFST_I_MSK 0xffff00ff
+#define MRX_STP_OFST_SFT 8
+#define MRX_STP_OFST_HI 15
+#define MRX_STP_OFST_SZ 8
+#define DBG_FF_FULL_MSK 0x0000ffff
+#define DBG_FF_FULL_I_MSK 0xffff0000
+#define DBG_FF_FULL_SFT 0
+#define DBG_FF_FULL_HI 15
+#define DBG_FF_FULL_SZ 16
+#define DBG_FF_FULL_CLR_MSK 0x80000000
+#define DBG_FF_FULL_CLR_I_MSK 0x7fffffff
+#define DBG_FF_FULL_CLR_SFT 31
+#define DBG_FF_FULL_CLR_HI 31
+#define DBG_FF_FULL_CLR_SZ 1
+#define DBG_WFF_FULL_MSK 0x0000ffff
+#define DBG_WFF_FULL_I_MSK 0xffff0000
+#define DBG_WFF_FULL_SFT 0
+#define DBG_WFF_FULL_HI 15
+#define DBG_WFF_FULL_SZ 16
+#define DBG_WFF_FULL_CLR_MSK 0x80000000
+#define DBG_WFF_FULL_CLR_I_MSK 0x7fffffff
+#define DBG_WFF_FULL_CLR_SFT 31
+#define DBG_WFF_FULL_CLR_HI 31
+#define DBG_WFF_FULL_CLR_SZ 1
+#define DBG_MB_FULL_MSK 0x0000ffff
+#define DBG_MB_FULL_I_MSK 0xffff0000
+#define DBG_MB_FULL_SFT 0
+#define DBG_MB_FULL_HI 15
+#define DBG_MB_FULL_SZ 16
+#define DBG_MB_FULL_CLR_MSK 0x80000000
+#define DBG_MB_FULL_CLR_I_MSK 0x7fffffff
+#define DBG_MB_FULL_CLR_SFT 31
+#define DBG_MB_FULL_CLR_HI 31
+#define DBG_MB_FULL_CLR_SZ 1
+#define BA_CTRL_MSK 0x00000003
+#define BA_CTRL_I_MSK 0xfffffffc
+#define BA_CTRL_SFT 0
+#define BA_CTRL_HI 1
+#define BA_CTRL_SZ 2
+#define BA_DBG_EN_MSK 0x00000004
+#define BA_DBG_EN_I_MSK 0xfffffffb
+#define BA_DBG_EN_SFT 2
+#define BA_DBG_EN_HI 2
+#define BA_DBG_EN_SZ 1
+#define BA_AGRE_EN_MSK 0x00000008
+#define BA_AGRE_EN_I_MSK 0xfffffff7
+#define BA_AGRE_EN_SFT 3
+#define BA_AGRE_EN_HI 3
+#define BA_AGRE_EN_SZ 1
+#define BA_TA_31_0_MSK 0xffffffff
+#define BA_TA_31_0_I_MSK 0x00000000
+#define BA_TA_31_0_SFT 0
+#define BA_TA_31_0_HI 31
+#define BA_TA_31_0_SZ 32
+#define BA_TA_47_32_MSK 0x0000ffff
+#define BA_TA_47_32_I_MSK 0xffff0000
+#define BA_TA_47_32_SFT 0
+#define BA_TA_47_32_HI 15
+#define BA_TA_47_32_SZ 16
+#define BA_TID_MSK 0x0000000f
+#define BA_TID_I_MSK 0xfffffff0
+#define BA_TID_SFT 0
+#define BA_TID_HI 3
+#define BA_TID_SZ 4
+#define BA_ST_SEQ_MSK 0x00000fff
+#define BA_ST_SEQ_I_MSK 0xfffff000
+#define BA_ST_SEQ_SFT 0
+#define BA_ST_SEQ_HI 11
+#define BA_ST_SEQ_SZ 12
+#define BA_SB0_MSK 0xffffffff
+#define BA_SB0_I_MSK 0x00000000
+#define BA_SB0_SFT 0
+#define BA_SB0_HI 31
+#define BA_SB0_SZ 32
+#define BA_SB1_MSK 0xffffffff
+#define BA_SB1_I_MSK 0x00000000
+#define BA_SB1_SFT 0
+#define BA_SB1_HI 31
+#define BA_SB1_SZ 32
+#define MRX_WD_MSK 0x0001ffff
+#define MRX_WD_I_MSK 0xfffe0000
+#define MRX_WD_SFT 0
+#define MRX_WD_HI 16
+#define MRX_WD_SZ 17
+#define ACK_GEN_EN_MSK 0x00000001
+#define ACK_GEN_EN_I_MSK 0xfffffffe
+#define ACK_GEN_EN_SFT 0
+#define ACK_GEN_EN_HI 0
+#define ACK_GEN_EN_SZ 1
+#define BA_GEN_EN_MSK 0x00000002
+#define BA_GEN_EN_I_MSK 0xfffffffd
+#define BA_GEN_EN_SFT 1
+#define BA_GEN_EN_HI 1
+#define BA_GEN_EN_SZ 1
+#define ACK_GEN_DUR_MSK 0x0000ffff
+#define ACK_GEN_DUR_I_MSK 0xffff0000
+#define ACK_GEN_DUR_SFT 0
+#define ACK_GEN_DUR_HI 15
+#define ACK_GEN_DUR_SZ 16
+#define ACK_GEN_INFO_MSK 0x00ff0000
+#define ACK_GEN_INFO_I_MSK 0xff00ffff
+#define ACK_GEN_INFO_SFT 16
+#define ACK_GEN_INFO_HI 23
+#define ACK_GEN_INFO_SZ 8
+#define ACK_GEN_RA_31_0_MSK 0xffffffff
+#define ACK_GEN_RA_31_0_I_MSK 0x00000000
+#define ACK_GEN_RA_31_0_SFT 0
+#define ACK_GEN_RA_31_0_HI 31
+#define ACK_GEN_RA_31_0_SZ 32
+#define ACK_GEN_RA_47_32_MSK 0x0000ffff
+#define ACK_GEN_RA_47_32_I_MSK 0xffff0000
+#define ACK_GEN_RA_47_32_SFT 0
+#define ACK_GEN_RA_47_32_HI 15
+#define ACK_GEN_RA_47_32_SZ 16
+#define MIB_LEN_FAIL_MSK 0x0000ffff
+#define MIB_LEN_FAIL_I_MSK 0xffff0000
+#define MIB_LEN_FAIL_SFT 0
+#define MIB_LEN_FAIL_HI 15
+#define MIB_LEN_FAIL_SZ 16
+#define TRAP_HW_ID_MSK 0x0000000f
+#define TRAP_HW_ID_I_MSK 0xfffffff0
+#define TRAP_HW_ID_SFT 0
+#define TRAP_HW_ID_HI 3
+#define TRAP_HW_ID_SZ 4
+#define ID_IN_USE_MSK 0x000000ff
+#define ID_IN_USE_I_MSK 0xffffff00
+#define ID_IN_USE_SFT 0
+#define ID_IN_USE_HI 7
+#define ID_IN_USE_SZ 8
+#define MRX_ERR_MSK 0xffffffff
+#define MRX_ERR_I_MSK 0x00000000
+#define MRX_ERR_SFT 0
+#define MRX_ERR_HI 31
+#define MRX_ERR_SZ 32
+#define GRP_WSID_MSK 0x0000000f
+#define GRP_WSID_I_MSK 0xfffffff0
+#define GRP_WSID_SFT 0
+#define GRP_WSID_HI 3
+#define GRP_WSID_SZ 4
+#define ADDR1A_SEL_MSK 0x00000003
+#define ADDR1A_SEL_I_MSK 0xfffffffc
+#define ADDR1A_SEL_SFT 0
+#define ADDR1A_SEL_HI 1
+#define ADDR1A_SEL_SZ 2
+#define ADDR2A_SEL_MSK 0x0000000c
+#define ADDR2A_SEL_I_MSK 0xfffffff3
+#define ADDR2A_SEL_SFT 2
+#define ADDR2A_SEL_HI 3
+#define ADDR2A_SEL_SZ 2
+#define ADDR3A_SEL_MSK 0x00000030
+#define ADDR3A_SEL_I_MSK 0xffffffcf
+#define ADDR3A_SEL_SFT 4
+#define ADDR3A_SEL_HI 5
+#define ADDR3A_SEL_SZ 2
+#define ADDR1B_SEL_MSK 0x000000c0
+#define ADDR1B_SEL_I_MSK 0xffffff3f
+#define ADDR1B_SEL_SFT 6
+#define ADDR1B_SEL_HI 7
+#define ADDR1B_SEL_SZ 2
+#define ADDR2B_SEL_MSK 0x00000300
+#define ADDR2B_SEL_I_MSK 0xfffffcff
+#define ADDR2B_SEL_SFT 8
+#define ADDR2B_SEL_HI 9
+#define ADDR2B_SEL_SZ 2
+#define ADDR3B_SEL_MSK 0x00000c00
+#define ADDR3B_SEL_I_MSK 0xfffff3ff
+#define ADDR3B_SEL_SFT 10
+#define ADDR3B_SEL_HI 11
+#define ADDR3B_SEL_SZ 2
+#define ADDR3C_SEL_MSK 0x00003000
+#define ADDR3C_SEL_I_MSK 0xffffcfff
+#define ADDR3C_SEL_SFT 12
+#define ADDR3C_SEL_HI 13
+#define ADDR3C_SEL_SZ 2
+#define FRM_CTRL_MSK 0x0000003f
+#define FRM_CTRL_I_MSK 0xffffffc0
+#define FRM_CTRL_SFT 0
+#define FRM_CTRL_HI 5
+#define FRM_CTRL_SZ 6
+#define SCOREBOAD_SIZE_MSK 0x0000007f
+#define SCOREBOAD_SIZE_I_MSK 0xffffff80
+#define SCOREBOAD_SIZE_SFT 0
+#define SCOREBOAD_SIZE_HI 6
+#define SCOREBOAD_SIZE_SZ 7
+#define MASK_ABNORMAL_CRC_MSK 0x00000001
+#define MASK_ABNORMAL_CRC_I_MSK 0xfffffffe
+#define MASK_ABNORMAL_CRC_SFT 0
+#define MASK_ABNORMAL_CRC_HI 0
+#define MASK_ABNORMAL_CRC_SZ 1
+#define PS_EN_MSK 0x00000002
+#define PS_EN_I_MSK 0xfffffffd
+#define PS_EN_SFT 1
+#define PS_EN_HI 1
+#define PS_EN_SZ 1
+#define MULTI_AMPDU_W_EN_MSK 0x00000004
+#define MULTI_AMPDU_W_EN_I_MSK 0xfffffffb
+#define MULTI_AMPDU_W_EN_SFT 2
+#define MULTI_AMPDU_W_EN_HI 2
+#define MULTI_AMPDU_W_EN_SZ 1
+#define BA_H_QUEUE_EN_MSK 0x00000001
+#define BA_H_QUEUE_EN_I_MSK 0xfffffffe
+#define BA_H_QUEUE_EN_SFT 0
+#define BA_H_QUEUE_EN_HI 0
+#define BA_H_QUEUE_EN_SZ 1
+#define EOSP_H_QUEUE_EN_MSK 0x00000002
+#define EOSP_H_QUEUE_EN_I_MSK 0xfffffffd
+#define EOSP_H_QUEUE_EN_SFT 1
+#define EOSP_H_QUEUE_EN_HI 1
+#define EOSP_H_QUEUE_EN_SZ 1
+#define EOSP_HW_ID_MSK 0x0000003c
+#define EOSP_HW_ID_I_MSK 0xffffffc3
+#define EOSP_HW_ID_SFT 2
+#define EOSP_HW_ID_HI 5
+#define EOSP_HW_ID_SZ 4
+#define BA_HW_ID_MSK 0x000003c0
+#define BA_HW_ID_I_MSK 0xfffffc3f
+#define BA_HW_ID_SFT 6
+#define BA_HW_ID_HI 9
+#define BA_HW_ID_SZ 4
+#define IDX_EXTEND_MSK 0x00000001
+#define IDX_EXTEND_I_MSK 0xfffffffe
+#define IDX_EXTEND_SFT 0
+#define IDX_EXTEND_HI 0
+#define IDX_EXTEND_SZ 1
+#define MRX_FLT_EN9_MSK 0x0000ffff
+#define MRX_FLT_EN9_I_MSK 0xffff0000
+#define MRX_FLT_EN9_SFT 0
+#define MRX_FLT_EN9_HI 15
+#define MRX_FLT_EN9_SZ 16
+#define MRX_FLT_EN10_MSK 0x0000ffff
+#define MRX_FLT_EN10_I_MSK 0xffff0000
+#define MRX_FLT_EN10_SFT 0
+#define MRX_FLT_EN10_HI 15
+#define MRX_FLT_EN10_SZ 16
+#define CSR_PHY_INFO_MSK 0x00007fff
+#define CSR_PHY_INFO_I_MSK 0xffff8000
+#define CSR_PHY_INFO_SFT 0
+#define CSR_PHY_INFO_HI 14
+#define CSR_PHY_INFO_SZ 15
+#define AMPDU_SIG_MSK 0x000000ff
+#define AMPDU_SIG_I_MSK 0xffffff00
+#define AMPDU_SIG_SFT 0
+#define AMPDU_SIG_HI 7
+#define AMPDU_SIG_SZ 8
+#define MIB_AMPDU_MSK 0xffffffff
+#define MIB_AMPDU_I_MSK 0x00000000
+#define MIB_AMPDU_SFT 0
+#define MIB_AMPDU_HI 31
+#define MIB_AMPDU_SZ 32
+#define LEN_FLT_MSK 0x0000ffff
+#define LEN_FLT_I_MSK 0xffff0000
+#define LEN_FLT_SFT 0
+#define LEN_FLT_HI 15
+#define LEN_FLT_SZ 16
+#define MIB_DELIMITER_MSK 0x0000ffff
+#define MIB_DELIMITER_I_MSK 0xffff0000
+#define MIB_DELIMITER_SFT 0
+#define MIB_DELIMITER_HI 15
+#define MIB_DELIMITER_SZ 16
+#define MTX_INT_Q0_Q_EMPTY_MSK 0x00010000
+#define MTX_INT_Q0_Q_EMPTY_I_MSK 0xfffeffff
+#define MTX_INT_Q0_Q_EMPTY_SFT 16
+#define MTX_INT_Q0_Q_EMPTY_HI 16
+#define MTX_INT_Q0_Q_EMPTY_SZ 1
+#define MTX_INT_Q0_TXOP_RUNOUT_MSK 0x00020000
+#define MTX_INT_Q0_TXOP_RUNOUT_I_MSK 0xfffdffff
+#define MTX_INT_Q0_TXOP_RUNOUT_SFT 17
+#define MTX_INT_Q0_TXOP_RUNOUT_HI 17
+#define MTX_INT_Q0_TXOP_RUNOUT_SZ 1
+#define MTX_INT_Q1_Q_EMPTY_MSK 0x00040000
+#define MTX_INT_Q1_Q_EMPTY_I_MSK 0xfffbffff
+#define MTX_INT_Q1_Q_EMPTY_SFT 18
+#define MTX_INT_Q1_Q_EMPTY_HI 18
+#define MTX_INT_Q1_Q_EMPTY_SZ 1
+#define MTX_INT_Q1_TXOP_RUNOUT_MSK 0x00080000
+#define MTX_INT_Q1_TXOP_RUNOUT_I_MSK 0xfff7ffff
+#define MTX_INT_Q1_TXOP_RUNOUT_SFT 19
+#define MTX_INT_Q1_TXOP_RUNOUT_HI 19
+#define MTX_INT_Q1_TXOP_RUNOUT_SZ 1
+#define MTX_INT_Q2_Q_EMPTY_MSK 0x00100000
+#define MTX_INT_Q2_Q_EMPTY_I_MSK 0xffefffff
+#define MTX_INT_Q2_Q_EMPTY_SFT 20
+#define MTX_INT_Q2_Q_EMPTY_HI 20
+#define MTX_INT_Q2_Q_EMPTY_SZ 1
+#define MTX_INT_Q2_TXOP_RUNOUT_MSK 0x00200000
+#define MTX_INT_Q2_TXOP_RUNOUT_I_MSK 0xffdfffff
+#define MTX_INT_Q2_TXOP_RUNOUT_SFT 21
+#define MTX_INT_Q2_TXOP_RUNOUT_HI 21
+#define MTX_INT_Q2_TXOP_RUNOUT_SZ 1
+#define MTX_INT_Q3_Q_EMPTY_MSK 0x00400000
+#define MTX_INT_Q3_Q_EMPTY_I_MSK 0xffbfffff
+#define MTX_INT_Q3_Q_EMPTY_SFT 22
+#define MTX_INT_Q3_Q_EMPTY_HI 22
+#define MTX_INT_Q3_Q_EMPTY_SZ 1
+#define MTX_INT_Q3_TXOP_RUNOUT_MSK 0x00800000
+#define MTX_INT_Q3_TXOP_RUNOUT_I_MSK 0xff7fffff
+#define MTX_INT_Q3_TXOP_RUNOUT_SFT 23
+#define MTX_INT_Q3_TXOP_RUNOUT_HI 23
+#define MTX_INT_Q3_TXOP_RUNOUT_SZ 1
+#define MTX_INT_Q4_Q_EMPTY_MSK 0x01000000
+#define MTX_INT_Q4_Q_EMPTY_I_MSK 0xfeffffff
+#define MTX_INT_Q4_Q_EMPTY_SFT 24
+#define MTX_INT_Q4_Q_EMPTY_HI 24
+#define MTX_INT_Q4_Q_EMPTY_SZ 1
+#define MTX_INT_Q4_TXOP_RUNOUT_MSK 0x02000000
+#define MTX_INT_Q4_TXOP_RUNOUT_I_MSK 0xfdffffff
+#define MTX_INT_Q4_TXOP_RUNOUT_SFT 25
+#define MTX_INT_Q4_TXOP_RUNOUT_HI 25
+#define MTX_INT_Q4_TXOP_RUNOUT_SZ 1
+#define MTX_INT_Q5_Q_EMPTY_MSK 0x04000000
+#define MTX_INT_Q5_Q_EMPTY_I_MSK 0xfbffffff
+#define MTX_INT_Q5_Q_EMPTY_SFT 26
+#define MTX_INT_Q5_Q_EMPTY_HI 26
+#define MTX_INT_Q5_Q_EMPTY_SZ 1
+#define MTX_INT_Q5_TXOP_RUNOUT_MSK 0x08000000
+#define MTX_INT_Q5_TXOP_RUNOUT_I_MSK 0xf7ffffff
+#define MTX_INT_Q5_TXOP_RUNOUT_SFT 27
+#define MTX_INT_Q5_TXOP_RUNOUT_HI 27
+#define MTX_INT_Q5_TXOP_RUNOUT_SZ 1
+#define MTX_EN_INT_Q0_Q_EMPTY_MSK 0x00010000
+#define MTX_EN_INT_Q0_Q_EMPTY_I_MSK 0xfffeffff
+#define MTX_EN_INT_Q0_Q_EMPTY_SFT 16
+#define MTX_EN_INT_Q0_Q_EMPTY_HI 16
+#define MTX_EN_INT_Q0_Q_EMPTY_SZ 1
+#define MTX_EN_INT_Q0_TXOP_RUNOUT_MSK 0x00020000
+#define MTX_EN_INT_Q0_TXOP_RUNOUT_I_MSK 0xfffdffff
+#define MTX_EN_INT_Q0_TXOP_RUNOUT_SFT 17
+#define MTX_EN_INT_Q0_TXOP_RUNOUT_HI 17
+#define MTX_EN_INT_Q0_TXOP_RUNOUT_SZ 1
+#define MTX_EN_INT_Q1_Q_EMPTY_MSK 0x00040000
+#define MTX_EN_INT_Q1_Q_EMPTY_I_MSK 0xfffbffff
+#define MTX_EN_INT_Q1_Q_EMPTY_SFT 18
+#define MTX_EN_INT_Q1_Q_EMPTY_HI 18
+#define MTX_EN_INT_Q1_Q_EMPTY_SZ 1
+#define MTX_EN_INT_Q1_TXOP_RUNOUT_MSK 0x00080000
+#define MTX_EN_INT_Q1_TXOP_RUNOUT_I_MSK 0xfff7ffff
+#define MTX_EN_INT_Q1_TXOP_RUNOUT_SFT 19
+#define MTX_EN_INT_Q1_TXOP_RUNOUT_HI 19
+#define MTX_EN_INT_Q1_TXOP_RUNOUT_SZ 1
+#define MTX_EN_INT_Q2_Q_EMPTY_MSK 0x00100000
+#define MTX_EN_INT_Q2_Q_EMPTY_I_MSK 0xffefffff
+#define MTX_EN_INT_Q2_Q_EMPTY_SFT 20
+#define MTX_EN_INT_Q2_Q_EMPTY_HI 20
+#define MTX_EN_INT_Q2_Q_EMPTY_SZ 1
+#define MTX_EN_INT_Q2_TXOP_RUNOUT_MSK 0x00200000
+#define MTX_EN_INT_Q2_TXOP_RUNOUT_I_MSK 0xffdfffff
+#define MTX_EN_INT_Q2_TXOP_RUNOUT_SFT 21
+#define MTX_EN_INT_Q2_TXOP_RUNOUT_HI 21
+#define MTX_EN_INT_Q2_TXOP_RUNOUT_SZ 1
+#define MTX_EN_INT_Q3_Q_EMPTY_MSK 0x00400000
+#define MTX_EN_INT_Q3_Q_EMPTY_I_MSK 0xffbfffff
+#define MTX_EN_INT_Q3_Q_EMPTY_SFT 22
+#define MTX_EN_INT_Q3_Q_EMPTY_HI 22
+#define MTX_EN_INT_Q3_Q_EMPTY_SZ 1
+#define MTX_EN_INT_Q3_TXOP_RUNOUT_MSK 0x00800000
+#define MTX_EN_INT_Q3_TXOP_RUNOUT_I_MSK 0xff7fffff
+#define MTX_EN_INT_Q3_TXOP_RUNOUT_SFT 23
+#define MTX_EN_INT_Q3_TXOP_RUNOUT_HI 23
+#define MTX_EN_INT_Q3_TXOP_RUNOUT_SZ 1
+#define MTX_EN_INT_Q4_Q_EMPTY_MSK 0x01000000
+#define MTX_EN_INT_Q4_Q_EMPTY_I_MSK 0xfeffffff
+#define MTX_EN_INT_Q4_Q_EMPTY_SFT 24
+#define MTX_EN_INT_Q4_Q_EMPTY_HI 24
+#define MTX_EN_INT_Q4_Q_EMPTY_SZ 1
+#define MTX_EN_INT_Q4_TXOP_RUNOUT_MSK 0x02000000
+#define MTX_EN_INT_Q4_TXOP_RUNOUT_I_MSK 0xfdffffff
+#define MTX_EN_INT_Q4_TXOP_RUNOUT_SFT 25
+#define MTX_EN_INT_Q4_TXOP_RUNOUT_HI 25
+#define MTX_EN_INT_Q4_TXOP_RUNOUT_SZ 1
+#define MTX_EN_INT_Q5_Q_EMPTY_MSK 0x04000000
+#define MTX_EN_INT_Q5_Q_EMPTY_I_MSK 0xfbffffff
+#define MTX_EN_INT_Q5_Q_EMPTY_SFT 26
+#define MTX_EN_INT_Q5_Q_EMPTY_HI 26
+#define MTX_EN_INT_Q5_Q_EMPTY_SZ 1
+#define MTX_EN_INT_Q5_TXOP_RUNOUT_MSK 0x08000000
+#define MTX_EN_INT_Q5_TXOP_RUNOUT_I_MSK 0xf7ffffff
+#define MTX_EN_INT_Q5_TXOP_RUNOUT_SFT 27
+#define MTX_EN_INT_Q5_TXOP_RUNOUT_HI 27
+#define MTX_EN_INT_Q5_TXOP_RUNOUT_SZ 1
+#define MTX_MTX2PHY_SLOW_MSK 0x00000001
+#define MTX_MTX2PHY_SLOW_I_MSK 0xfffffffe
+#define MTX_MTX2PHY_SLOW_SFT 0
+#define MTX_MTX2PHY_SLOW_HI 0
+#define MTX_MTX2PHY_SLOW_SZ 1
+#define MTX_M2M_SLOW_PRD_MSK 0x0000000e
+#define MTX_M2M_SLOW_PRD_I_MSK 0xfffffff1
+#define MTX_M2M_SLOW_PRD_SFT 1
+#define MTX_M2M_SLOW_PRD_HI 3
+#define MTX_M2M_SLOW_PRD_SZ 3
+#define MTX_AMPDU_CRC8_AUTO_MSK 0x00000020
+#define MTX_AMPDU_CRC8_AUTO_I_MSK 0xffffffdf
+#define MTX_AMPDU_CRC8_AUTO_SFT 5
+#define MTX_AMPDU_CRC8_AUTO_HI 5
+#define MTX_AMPDU_CRC8_AUTO_SZ 1
+#define MTX_BLOCKTX_IGNORE_BT_BUSY_MSK 0x00000040
+#define MTX_BLOCKTX_IGNORE_BT_BUSY_I_MSK 0xffffffbf
+#define MTX_BLOCKTX_IGNORE_BT_BUSY_SFT 6
+#define MTX_BLOCKTX_IGNORE_BT_BUSY_HI 6
+#define MTX_BLOCKTX_IGNORE_BT_BUSY_SZ 1
+#define MTX_RAW_DATA_MODE_MSK 0x00000080
+#define MTX_RAW_DATA_MODE_I_MSK 0xffffff7f
+#define MTX_RAW_DATA_MODE_SFT 7
+#define MTX_RAW_DATA_MODE_HI 7
+#define MTX_RAW_DATA_MODE_SZ 1
+#define MTX_BLOCKTX_IGNORE_TOMAC_TX_IP_MSK 0x00000800
+#define MTX_BLOCKTX_IGNORE_TOMAC_TX_IP_I_MSK 0xfffff7ff
+#define MTX_BLOCKTX_IGNORE_TOMAC_TX_IP_SFT 11
+#define MTX_BLOCKTX_IGNORE_TOMAC_TX_IP_HI 11
+#define MTX_BLOCKTX_IGNORE_TOMAC_TX_IP_SZ 1
+#define MTX_BLOCKTX_IGNORE_TOMAC_RX_EN_MSK 0x00001000
+#define MTX_BLOCKTX_IGNORE_TOMAC_RX_EN_I_MSK 0xffffefff
+#define MTX_BLOCKTX_IGNORE_TOMAC_RX_EN_SFT 12
+#define MTX_BLOCKTX_IGNORE_TOMAC_RX_EN_HI 12
+#define MTX_BLOCKTX_IGNORE_TOMAC_RX_EN_SZ 1
+#define MTX_BLOCKTX_IGNORE_TOMAC_CCA_CS_MSK 0x00002000
+#define MTX_BLOCKTX_IGNORE_TOMAC_CCA_CS_I_MSK 0xffffdfff
+#define MTX_BLOCKTX_IGNORE_TOMAC_CCA_CS_SFT 13
+#define MTX_BLOCKTX_IGNORE_TOMAC_CCA_CS_HI 13
+#define MTX_BLOCKTX_IGNORE_TOMAC_CCA_CS_SZ 1
+#define MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_SECONDARY_MSK 0x00004000
+#define MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_SECONDARY_I_MSK 0xffffbfff
+#define MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_SECONDARY_SFT 14
+#define MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_SECONDARY_HI 14
+#define MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_SECONDARY_SZ 1
+#define MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_PRIMARY_MSK 0x00008000
+#define MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_PRIMARY_I_MSK 0xffff7fff
+#define MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_PRIMARY_SFT 15
+#define MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_PRIMARY_HI 15
+#define MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_PRIMARY_SZ 1
+#define MTX_HALT_Q_MB_MSK 0x007f0000
+#define MTX_HALT_Q_MB_I_MSK 0xff80ffff
+#define MTX_HALT_Q_MB_SFT 16
+#define MTX_HALT_Q_MB_HI 22
+#define MTX_HALT_Q_MB_SZ 7
+#define MTX_IGNORE_PHYRX_IFS_DELTATIME_MSK 0x01000000
+#define MTX_IGNORE_PHYRX_IFS_DELTATIME_I_MSK 0xfeffffff
+#define MTX_IGNORE_PHYRX_IFS_DELTATIME_SFT 24
+#define MTX_IGNORE_PHYRX_IFS_DELTATIME_HI 24
+#define MTX_IGNORE_PHYRX_IFS_DELTATIME_SZ 1
+#define MTX_SELFSTA_PS_MSK 0x02000000
+#define MTX_SELFSTA_PS_I_MSK 0xfdffffff
+#define MTX_SELFSTA_PS_SFT 25
+#define MTX_SELFSTA_PS_HI 25
+#define MTX_SELFSTA_PS_SZ 1
+#define NO_PKT_BUF_REDUCTION_MSK 0x00000001
+#define NO_PKT_BUF_REDUCTION_I_MSK 0xfffffffe
+#define NO_PKT_BUF_REDUCTION_SFT 0
+#define NO_PKT_BUF_REDUCTION_HI 0
+#define NO_PKT_BUF_REDUCTION_SZ 1
+#define NO_REDUCE_TXALLFAIL_PKT_MSK 0x00000004
+#define NO_REDUCE_TXALLFAIL_PKT_I_MSK 0xfffffffb
+#define NO_REDUCE_TXALLFAIL_PKT_SFT 2
+#define NO_REDUCE_TXALLFAIL_PKT_HI 2
+#define NO_REDUCE_TXALLFAIL_PKT_SZ 1
+#define NO_REDUCE_PKT_PEERPS_MPDU_MSK 0x00000010
+#define NO_REDUCE_PKT_PEERPS_MPDU_I_MSK 0xffffffef
+#define NO_REDUCE_PKT_PEERPS_MPDU_SFT 4
+#define NO_REDUCE_PKT_PEERPS_MPDU_HI 4
+#define NO_REDUCE_PKT_PEERPS_MPDU_SZ 1
+#define NO_REDUCE_PKT_PEERPS_AMPDUV1P2_MSK 0x00000040
+#define NO_REDUCE_PKT_PEERPS_AMPDUV1P2_I_MSK 0xffffffbf
+#define NO_REDUCE_PKT_PEERPS_AMPDUV1P2_SFT 6
+#define NO_REDUCE_PKT_PEERPS_AMPDUV1P2_HI 6
+#define NO_REDUCE_PKT_PEERPS_AMPDUV1P2_SZ 1
+#define NO_REDUCE_PKT_PEERPS_AMPDUV1P3_MSK 0x00000080
+#define NO_REDUCE_PKT_PEERPS_AMPDUV1P3_I_MSK 0xffffff7f
+#define NO_REDUCE_PKT_PEERPS_AMPDUV1P3_SFT 7
+#define NO_REDUCE_PKT_PEERPS_AMPDUV1P3_HI 7
+#define NO_REDUCE_PKT_PEERPS_AMPDUV1P3_SZ 1
+#define RO_PTC_SCHEDULE_MSK 0x0000000f
+#define RO_PTC_SCHEDULE_I_MSK 0xfffffff0
+#define RO_PTC_SCHEDULE_SFT 0
+#define RO_PTC_SCHEDULE_HI 3
+#define RO_PTC_SCHEDULE_SZ 4
+#define RO_FSM_MTXPTC_MSK 0x00000070
+#define RO_FSM_MTXPTC_I_MSK 0xffffff8f
+#define RO_FSM_MTXPTC_SFT 4
+#define RO_FSM_MTXPTC_HI 6
+#define RO_FSM_MTXPTC_SZ 3
+#define RO_ACT_MASK_MSK 0x00007f00
+#define RO_ACT_MASK_I_MSK 0xffff80ff
+#define RO_ACT_MASK_SFT 8
+#define RO_ACT_MASK_HI 14
+#define RO_ACT_MASK_SZ 7
+#define RO_CAND_MASK_MSK 0x007f0000
+#define RO_CAND_MASK_I_MSK 0xff80ffff
+#define RO_CAND_MASK_SFT 16
+#define RO_CAND_MASK_HI 22
+#define RO_CAND_MASK_SZ 7
+#define RO_WAIT_RESPONSE_PHASE_MSK 0x03000000
+#define RO_WAIT_RESPONSE_PHASE_I_MSK 0xfcffffff
+#define RO_WAIT_RESPONSE_PHASE_SFT 24
+#define RO_WAIT_RESPONSE_PHASE_HI 25
+#define RO_WAIT_RESPONSE_PHASE_SZ 2
+#define RO_FSM_MTXHALT_MSK 0x30000000
+#define RO_FSM_MTXHALT_I_MSK 0xcfffffff
+#define RO_FSM_MTXHALT_SFT 28
+#define RO_FSM_MTXHALT_HI 29
+#define RO_FSM_MTXHALT_SZ 2
+#define RO_FSM_MTXDMA_MSK 0x00000007
+#define RO_FSM_MTXDMA_I_MSK 0xfffffff8
+#define RO_FSM_MTXDMA_SFT 0
+#define RO_FSM_MTXDMA_HI 2
+#define RO_FSM_MTXDMA_SZ 3
+#define RO_FSM_MTXPHYTX_MSK 0x00000070
+#define RO_FSM_MTXPHYTX_I_MSK 0xffffff8f
+#define RO_FSM_MTXPHYTX_SFT 4
+#define RO_FSM_MTXPHYTX_HI 6
+#define RO_FSM_MTXPHYTX_SZ 3
+#define RO_MTXDMA_CMD_MSK 0x00003f00
+#define RO_MTXDMA_CMD_I_MSK 0xffffc0ff
+#define RO_MTXDMA_CMD_SFT 8
+#define RO_MTXDMA_CMD_HI 13
+#define RO_MTXDMA_CMD_SZ 6
+#define RO_TXOP_INTERVAL_MSK 0xffff0000
+#define RO_TXOP_INTERVAL_I_MSK 0x0000ffff
+#define RO_TXOP_INTERVAL_SFT 16
+#define RO_TXOP_INTERVAL_HI 31
+#define RO_TXOP_INTERVAL_SZ 16
+#define MTX_HALT_MODE0_MSK 0x00000001
+#define MTX_HALT_MODE0_I_MSK 0xfffffffe
+#define MTX_HALT_MODE0_SFT 0
+#define MTX_HALT_MODE0_HI 0
+#define MTX_HALT_MODE0_SZ 1
+#define BLOCK_TXQ_MSK 0x007f0000
+#define BLOCK_TXQ_I_MSK 0xff80ffff
+#define BLOCK_TXQ_SFT 16
+#define BLOCK_TXQ_HI 22
+#define BLOCK_TXQ_SZ 7
+#define MTX_HALT_IGNORE_TXREQ_EN_MSK 0x01000000
+#define MTX_HALT_IGNORE_TXREQ_EN_I_MSK 0xfeffffff
+#define MTX_HALT_IGNORE_TXREQ_EN_SFT 24
+#define MTX_HALT_IGNORE_TXREQ_EN_HI 24
+#define MTX_HALT_IGNORE_TXREQ_EN_SZ 1
+#define MTX_HALT_IGNORE_RXREQ_EN_MSK 0x02000000
+#define MTX_HALT_IGNORE_RXREQ_EN_I_MSK 0xfdffffff
+#define MTX_HALT_IGNORE_RXREQ_EN_SFT 25
+#define MTX_HALT_IGNORE_RXREQ_EN_HI 25
+#define MTX_HALT_IGNORE_RXREQ_EN_SZ 1
+#define DBG_PHYTX_PROCEED_MSK 0x00000001
+#define DBG_PHYTX_PROCEED_I_MSK 0xfffffffe
+#define DBG_PHYTX_PROCEED_SFT 0
+#define DBG_PHYTX_PROCEED_HI 0
+#define DBG_PHYTX_PROCEED_SZ 1
+#define MTX_MIB_CNT0_MSK 0x3fffffff
+#define MTX_MIB_CNT0_I_MSK 0xc0000000
+#define MTX_MIB_CNT0_SFT 0
+#define MTX_MIB_CNT0_HI 29
+#define MTX_MIB_CNT0_SZ 30
+#define MTX_MIB_CNT0_FRAME_MSK 0x000003ff
+#define MTX_MIB_CNT0_FRAME_I_MSK 0xfffffc00
+#define MTX_MIB_CNT0_FRAME_SFT 0
+#define MTX_MIB_CNT0_FRAME_HI 9
+#define MTX_MIB_CNT0_FRAME_SZ 10
+#define MTX_MIB_CNT0_ATTEMPT_MSK 0x000ffc00
+#define MTX_MIB_CNT0_ATTEMPT_I_MSK 0xfff003ff
+#define MTX_MIB_CNT0_ATTEMPT_SFT 10
+#define MTX_MIB_CNT0_ATTEMPT_HI 19
+#define MTX_MIB_CNT0_ATTEMPT_SZ 10
+#define MTX_MIB_CNT0_SUCC_MSK 0x3ff00000
+#define MTX_MIB_CNT0_SUCC_I_MSK 0xc00fffff
+#define MTX_MIB_CNT0_SUCC_SFT 20
+#define MTX_MIB_CNT0_SUCC_HI 29
+#define MTX_MIB_CNT0_SUCC_SZ 10
+#define MTX_MIB_EN0_MSK 0x40000000
+#define MTX_MIB_EN0_I_MSK 0xbfffffff
+#define MTX_MIB_EN0_SFT 30
+#define MTX_MIB_EN0_HI 30
+#define MTX_MIB_EN0_SZ 1
+#define MTX_MIB_CNT1_MSK 0x3fffffff
+#define MTX_MIB_CNT1_I_MSK 0xc0000000
+#define MTX_MIB_CNT1_SFT 0
+#define MTX_MIB_CNT1_HI 29
+#define MTX_MIB_CNT1_SZ 30
+#define MTX_MIB_CNT1_FRAME_MSK 0x000003ff
+#define MTX_MIB_CNT1_FRAME_I_MSK 0xfffffc00
+#define MTX_MIB_CNT1_FRAME_SFT 0
+#define MTX_MIB_CNT1_FRAME_HI 9
+#define MTX_MIB_CNT1_FRAME_SZ 10
+#define MTX_MIB_CNT1_ATTEMPT_MSK 0x000ffc00
+#define MTX_MIB_CNT1_ATTEMPT_I_MSK 0xfff003ff
+#define MTX_MIB_CNT1_ATTEMPT_SFT 10
+#define MTX_MIB_CNT1_ATTEMPT_HI 19
+#define MTX_MIB_CNT1_ATTEMPT_SZ 10
+#define MTX_MIB_CNT1_SUCC_MSK 0x3ff00000
+#define MTX_MIB_CNT1_SUCC_I_MSK 0xc00fffff
+#define MTX_MIB_CNT1_SUCC_SFT 20
+#define MTX_MIB_CNT1_SUCC_HI 29
+#define MTX_MIB_CNT1_SUCC_SZ 10
+#define MTX_MIB_EN1_MSK 0x40000000
+#define MTX_MIB_EN1_I_MSK 0xbfffffff
+#define MTX_MIB_EN1_SFT 30
+#define MTX_MIB_EN1_HI 30
+#define MTX_MIB_EN1_SZ 1
+#define MTX_MIB_CNT2_MSK 0x3fffffff
+#define MTX_MIB_CNT2_I_MSK 0xc0000000
+#define MTX_MIB_CNT2_SFT 0
+#define MTX_MIB_CNT2_HI 29
+#define MTX_MIB_CNT2_SZ 30
+#define MTX_MIB_CNT2_FRAME_MSK 0x000003ff
+#define MTX_MIB_CNT2_FRAME_I_MSK 0xfffffc00
+#define MTX_MIB_CNT2_FRAME_SFT 0
+#define MTX_MIB_CNT2_FRAME_HI 9
+#define MTX_MIB_CNT2_FRAME_SZ 10
+#define MTX_MIB_CNT2_ATTEMPT_MSK 0x000ffc00
+#define MTX_MIB_CNT2_ATTEMPT_I_MSK 0xfff003ff
+#define MTX_MIB_CNT2_ATTEMPT_SFT 10
+#define MTX_MIB_CNT2_ATTEMPT_HI 19
+#define MTX_MIB_CNT2_ATTEMPT_SZ 10
+#define MTX_MIB_CNT2_SUCC_MSK 0x3ff00000
+#define MTX_MIB_CNT2_SUCC_I_MSK 0xc00fffff
+#define MTX_MIB_CNT2_SUCC_SFT 20
+#define MTX_MIB_CNT2_SUCC_HI 29
+#define MTX_MIB_CNT2_SUCC_SZ 10
+#define MTX_MIB_EN2_MSK 0x40000000
+#define MTX_MIB_EN2_I_MSK 0xbfffffff
+#define MTX_MIB_EN2_SFT 30
+#define MTX_MIB_EN2_HI 30
+#define MTX_MIB_EN2_SZ 1
+#define MTX_MIB_CNT3_MSK 0x3fffffff
+#define MTX_MIB_CNT3_I_MSK 0xc0000000
+#define MTX_MIB_CNT3_SFT 0
+#define MTX_MIB_CNT3_HI 29
+#define MTX_MIB_CNT3_SZ 30
+#define MTX_MIB_CNT3_FRAME_MSK 0x000003ff
+#define MTX_MIB_CNT3_FRAME_I_MSK 0xfffffc00
+#define MTX_MIB_CNT3_FRAME_SFT 0
+#define MTX_MIB_CNT3_FRAME_HI 9
+#define MTX_MIB_CNT3_FRAME_SZ 10
+#define MTX_MIB_CNT3_ATTEMPT_MSK 0x000ffc00
+#define MTX_MIB_CNT3_ATTEMPT_I_MSK 0xfff003ff
+#define MTX_MIB_CNT3_ATTEMPT_SFT 10
+#define MTX_MIB_CNT3_ATTEMPT_HI 19
+#define MTX_MIB_CNT3_ATTEMPT_SZ 10
+#define MTX_MIB_CNT3_SUCC_MSK 0x3ff00000
+#define MTX_MIB_CNT3_SUCC_I_MSK 0xc00fffff
+#define MTX_MIB_CNT3_SUCC_SFT 20
+#define MTX_MIB_CNT3_SUCC_HI 29
+#define MTX_MIB_CNT3_SUCC_SZ 10
+#define MTX_MIB_EN3_MSK 0x40000000
+#define MTX_MIB_EN3_I_MSK 0xbfffffff
+#define MTX_MIB_EN3_SFT 30
+#define MTX_MIB_EN3_HI 30
+#define MTX_MIB_EN3_SZ 1
+#define MTX_MIB_CNT4_MSK 0x3fffffff
+#define MTX_MIB_CNT4_I_MSK 0xc0000000
+#define MTX_MIB_CNT4_SFT 0
+#define MTX_MIB_CNT4_HI 29
+#define MTX_MIB_CNT4_SZ 30
+#define MTX_MIB_CNT4_FRAME_MSK 0x000003ff
+#define MTX_MIB_CNT4_FRAME_I_MSK 0xfffffc00
+#define MTX_MIB_CNT4_FRAME_SFT 0
+#define MTX_MIB_CNT4_FRAME_HI 9
+#define MTX_MIB_CNT4_FRAME_SZ 10
+#define MTX_MIB_CNT4_ATTEMPT_MSK 0x000ffc00
+#define MTX_MIB_CNT4_ATTEMPT_I_MSK 0xfff003ff
+#define MTX_MIB_CNT4_ATTEMPT_SFT 10
+#define MTX_MIB_CNT4_ATTEMPT_HI 19
+#define MTX_MIB_CNT4_ATTEMPT_SZ 10
+#define MTX_MIB_CNT4_SUCC_MSK 0x3ff00000
+#define MTX_MIB_CNT4_SUCC_I_MSK 0xc00fffff
+#define MTX_MIB_CNT4_SUCC_SFT 20
+#define MTX_MIB_CNT4_SUCC_HI 29
+#define MTX_MIB_CNT4_SUCC_SZ 10
+#define MTX_MIB_EN4_MSK 0x40000000
+#define MTX_MIB_EN4_I_MSK 0xbfffffff
+#define MTX_MIB_EN4_SFT 30
+#define MTX_MIB_EN4_HI 30
+#define MTX_MIB_EN4_SZ 1
+#define MTX_MIB_CNT5_MSK 0x3fffffff
+#define MTX_MIB_CNT5_I_MSK 0xc0000000
+#define MTX_MIB_CNT5_SFT 0
+#define MTX_MIB_CNT5_HI 29
+#define MTX_MIB_CNT5_SZ 30
+#define MTX_MIB_CNT5_FRAME_MSK 0x000003ff
+#define MTX_MIB_CNT5_FRAME_I_MSK 0xfffffc00
+#define MTX_MIB_CNT5_FRAME_SFT 0
+#define MTX_MIB_CNT5_FRAME_HI 9
+#define MTX_MIB_CNT5_FRAME_SZ 10
+#define MTX_MIB_CNT5_ATTEMPT_MSK 0x000ffc00
+#define MTX_MIB_CNT5_ATTEMPT_I_MSK 0xfff003ff
+#define MTX_MIB_CNT5_ATTEMPT_SFT 10
+#define MTX_MIB_CNT5_ATTEMPT_HI 19
+#define MTX_MIB_CNT5_ATTEMPT_SZ 10
+#define MTX_MIB_CNT5_SUCC_MSK 0x3ff00000
+#define MTX_MIB_CNT5_SUCC_I_MSK 0xc00fffff
+#define MTX_MIB_CNT5_SUCC_SFT 20
+#define MTX_MIB_CNT5_SUCC_HI 29
+#define MTX_MIB_CNT5_SUCC_SZ 10
+#define MTX_MIB_EN5_MSK 0x40000000
+#define MTX_MIB_EN5_I_MSK 0xbfffffff
+#define MTX_MIB_EN5_SFT 30
+#define MTX_MIB_EN5_HI 30
+#define MTX_MIB_EN5_SZ 1
+#define MTX_MIB_CNT6_MSK 0x3fffffff
+#define MTX_MIB_CNT6_I_MSK 0xc0000000
+#define MTX_MIB_CNT6_SFT 0
+#define MTX_MIB_CNT6_HI 29
+#define MTX_MIB_CNT6_SZ 30
+#define MTX_MIB_CNT6_FRAME_MSK 0x000003ff
+#define MTX_MIB_CNT6_FRAME_I_MSK 0xfffffc00
+#define MTX_MIB_CNT6_FRAME_SFT 0
+#define MTX_MIB_CNT6_FRAME_HI 9
+#define MTX_MIB_CNT6_FRAME_SZ 10
+#define MTX_MIB_CNT6_ATTEMPT_MSK 0x000ffc00
+#define MTX_MIB_CNT6_ATTEMPT_I_MSK 0xfff003ff
+#define MTX_MIB_CNT6_ATTEMPT_SFT 10
+#define MTX_MIB_CNT6_ATTEMPT_HI 19
+#define MTX_MIB_CNT6_ATTEMPT_SZ 10
+#define MTX_MIB_CNT6_SUCC_MSK 0x3ff00000
+#define MTX_MIB_CNT6_SUCC_I_MSK 0xc00fffff
+#define MTX_MIB_CNT6_SUCC_SFT 20
+#define MTX_MIB_CNT6_SUCC_HI 29
+#define MTX_MIB_CNT6_SUCC_SZ 10
+#define MTX_MIB_EN6_MSK 0x40000000
+#define MTX_MIB_EN6_I_MSK 0xbfffffff
+#define MTX_MIB_EN6_SFT 30
+#define MTX_MIB_EN6_HI 30
+#define MTX_MIB_EN6_SZ 1
+#define MTX_MIB_CNT7_MSK 0x3fffffff
+#define MTX_MIB_CNT7_I_MSK 0xc0000000
+#define MTX_MIB_CNT7_SFT 0
+#define MTX_MIB_CNT7_HI 29
+#define MTX_MIB_CNT7_SZ 30
+#define MTX_MIB_CNT7_FRAME_MSK 0x000003ff
+#define MTX_MIB_CNT7_FRAME_I_MSK 0xfffffc00
+#define MTX_MIB_CNT7_FRAME_SFT 0
+#define MTX_MIB_CNT7_FRAME_HI 9
+#define MTX_MIB_CNT7_FRAME_SZ 10
+#define MTX_MIB_CNT7_ATTEMPT_MSK 0x000ffc00
+#define MTX_MIB_CNT7_ATTEMPT_I_MSK 0xfff003ff
+#define MTX_MIB_CNT7_ATTEMPT_SFT 10
+#define MTX_MIB_CNT7_ATTEMPT_HI 19
+#define MTX_MIB_CNT7_ATTEMPT_SZ 10
+#define MTX_MIB_CNT7_SUCC_MSK 0x3ff00000
+#define MTX_MIB_CNT7_SUCC_I_MSK 0xc00fffff
+#define MTX_MIB_CNT7_SUCC_SFT 20
+#define MTX_MIB_CNT7_SUCC_HI 29
+#define MTX_MIB_CNT7_SUCC_SZ 10
+#define MTX_MIB_EN7_MSK 0x40000000
+#define MTX_MIB_EN7_I_MSK 0xbfffffff
+#define MTX_MIB_EN7_SFT 30
+#define MTX_MIB_EN7_HI 30
+#define MTX_MIB_EN7_SZ 1
+#define EN_UNEXPECT_WSID_MSK 0x00000001
+#define EN_UNEXPECT_WSID_I_MSK 0xfffffffe
+#define EN_UNEXPECT_WSID_SFT 0
+#define EN_UNEXPECT_WSID_HI 0
+#define EN_UNEXPECT_WSID_SZ 1
+#define EN_STAT_FINISH_INT_MSK 0x00000002
+#define EN_STAT_FINISH_INT_I_MSK 0xfffffffd
+#define EN_STAT_FINISH_INT_SFT 1
+#define EN_STAT_FINISH_INT_HI 1
+#define EN_STAT_FINISH_INT_SZ 1
+#define STAT_EN_MB_MSK 0x00000040
+#define STAT_EN_MB_I_MSK 0xffffffbf
+#define STAT_EN_MB_SFT 6
+#define STAT_EN_MB_HI 6
+#define STAT_EN_MB_SZ 1
+#define STAT_MB_TARGET_MSK 0x00000080
+#define STAT_MB_TARGET_I_MSK 0xffffff7f
+#define STAT_MB_TARGET_SFT 7
+#define STAT_MB_TARGET_HI 7
+#define STAT_MB_TARGET_SZ 1
+#define STAT_UNEXPECT_WSID_MSK 0x00000100
+#define STAT_UNEXPECT_WSID_I_MSK 0xfffffeff
+#define STAT_UNEXPECT_WSID_SFT 8
+#define STAT_UNEXPECT_WSID_HI 8
+#define STAT_UNEXPECT_WSID_SZ 1
+#define STAT_FINISH_MSK 0x00000200
+#define STAT_FINISH_I_MSK 0xfffffdff
+#define STAT_FINISH_SFT 9
+#define STAT_FINISH_HI 9
+#define STAT_FINISH_SZ 1
+#define STAT_PKT_ID_MSK 0x007f0000
+#define STAT_PKT_ID_I_MSK 0xff80ffff
+#define STAT_PKT_ID_SFT 16
+#define STAT_PKT_ID_HI 22
+#define STAT_PKT_ID_SZ 7
+#define STAT_FSM_MSK 0x1f000000
+#define STAT_FSM_I_MSK 0xe0ffffff
+#define STAT_FSM_SFT 24
+#define STAT_FSM_HI 28
+#define STAT_FSM_SZ 5
+#define STAT_ENABLE_MSK 0x20000000
+#define STAT_ENABLE_I_MSK 0xdfffffff
+#define STAT_ENABLE_SFT 29
+#define STAT_ENABLE_HI 29
+#define STAT_ENABLE_SZ 1
+#define STAT_WSID_MSK 0x00000007
+#define STAT_WSID_I_MSK 0xfffffff8
+#define STAT_WSID_SFT 0
+#define STAT_WSID_HI 2
+#define STAT_WSID_SZ 3
+#define STAT_FREEZE_MSK 0x00000100
+#define STAT_FREEZE_I_MSK 0xfffffeff
+#define STAT_FREEZE_SFT 8
+#define STAT_FREEZE_HI 8
+#define STAT_FREEZE_SZ 1
+#define STAT_CLR_MSK 0x00000200
+#define STAT_CLR_I_MSK 0xfffffdff
+#define STAT_CLR_SFT 9
+#define STAT_CLR_HI 9
+#define STAT_CLR_SZ 1
+#define STAT_CLR_DONE_MSK 0x00000400
+#define STAT_CLR_DONE_I_MSK 0xfffffbff
+#define STAT_CLR_DONE_SFT 10
+#define STAT_CLR_DONE_HI 10
+#define STAT_CLR_DONE_SZ 1
+#define MAC_TX_PS_UNLOCK_MSK 0x000000ff
+#define MAC_TX_PS_UNLOCK_I_MSK 0xffffff00
+#define MAC_TX_PS_UNLOCK_SFT 0
+#define MAC_TX_PS_UNLOCK_HI 7
+#define MAC_TX_PS_UNLOCK_SZ 8
+#define MAC_TX_PEER_PS_LOCK_EN_MSK 0x00000100
+#define MAC_TX_PEER_PS_LOCK_EN_I_MSK 0xfffffeff
+#define MAC_TX_PEER_PS_LOCK_EN_SFT 8
+#define MAC_TX_PEER_PS_LOCK_EN_HI 8
+#define MAC_TX_PEER_PS_LOCK_EN_SZ 1
+#define MAC_TX_PEER_PS_LOCK_AUTOLOCK_EN_MSK 0x00000200
+#define MAC_TX_PEER_PS_LOCK_AUTOLOCK_EN_I_MSK 0xfffffdff
+#define MAC_TX_PEER_PS_LOCK_AUTOLOCK_EN_SFT 9
+#define MAC_TX_PEER_PS_LOCK_AUTOLOCK_EN_HI 9
+#define MAC_TX_PEER_PS_LOCK_AUTOLOCK_EN_SZ 1
+#define MAC_TX_PS_LOCK_MSK 0xff000000
+#define MAC_TX_PS_LOCK_I_MSK 0x00ffffff
+#define MAC_TX_PS_LOCK_SFT 24
+#define MAC_TX_PS_LOCK_HI 31
+#define MAC_TX_PS_LOCK_SZ 8
+#define MAC_TX_PS_LOCK_STATUS_MSK 0x000000ff
+#define MAC_TX_PS_LOCK_STATUS_I_MSK 0xffffff00
+#define MAC_TX_PS_LOCK_STATUS_SFT 0
+#define MAC_TX_PS_LOCK_STATUS_HI 7
+#define MAC_TX_PS_LOCK_STATUS_SZ 8
+#define MTX_RATERPT_HWID_MSK 0x0000000f
+#define MTX_RATERPT_HWID_I_MSK 0xfffffff0
+#define MTX_RATERPT_HWID_SFT 0
+#define MTX_RATERPT_HWID_HI 3
+#define MTX_RATERPT_HWID_SZ 4
+#define CTYPE_RATE_RPT_MSK 0x00000070
+#define CTYPE_RATE_RPT_I_MSK 0xffffff8f
+#define CTYPE_RATE_RPT_SFT 4
+#define CTYPE_RATE_RPT_HI 6
+#define CTYPE_RATE_RPT_SZ 3
+#define MTX_DBGOPT_FORCE_TXMAJOR_RATE_MSK 0x000000ff
+#define MTX_DBGOPT_FORCE_TXMAJOR_RATE_I_MSK 0xffffff00
+#define MTX_DBGOPT_FORCE_TXMAJOR_RATE_SFT 0
+#define MTX_DBGOPT_FORCE_TXMAJOR_RATE_HI 7
+#define MTX_DBGOPT_FORCE_TXMAJOR_RATE_SZ 8
+#define MTX_DBGOPT_FORCE_TXCTRL_RATE_MSK 0x0000ff00
+#define MTX_DBGOPT_FORCE_TXCTRL_RATE_I_MSK 0xffff00ff
+#define MTX_DBGOPT_FORCE_TXCTRL_RATE_SFT 8
+#define MTX_DBGOPT_FORCE_TXCTRL_RATE_HI 15
+#define MTX_DBGOPT_FORCE_TXCTRL_RATE_SZ 8
+#define MTX_DBGOPT_FORCE_DO_RTS_CTS_MODE_MSK 0x00030000
+#define MTX_DBGOPT_FORCE_DO_RTS_CTS_MODE_I_MSK 0xfffcffff
+#define MTX_DBGOPT_FORCE_DO_RTS_CTS_MODE_SFT 16
+#define MTX_DBGOPT_FORCE_DO_RTS_CTS_MODE_HI 17
+#define MTX_DBGOPT_FORCE_DO_RTS_CTS_MODE_SZ 2
+#define MTX_DBGOPT_FORCE_TXMAJOR_RATE_EN_MSK 0x00000001
+#define MTX_DBGOPT_FORCE_TXMAJOR_RATE_EN_I_MSK 0xfffffffe
+#define MTX_DBGOPT_FORCE_TXMAJOR_RATE_EN_SFT 0
+#define MTX_DBGOPT_FORCE_TXMAJOR_RATE_EN_HI 0
+#define MTX_DBGOPT_FORCE_TXMAJOR_RATE_EN_SZ 1
+#define MTX_DBGOPT_FORCE_TXCTRL_RATE_EN_MSK 0x00000004
+#define MTX_DBGOPT_FORCE_TXCTRL_RATE_EN_I_MSK 0xfffffffb
+#define MTX_DBGOPT_FORCE_TXCTRL_RATE_EN_SFT 2
+#define MTX_DBGOPT_FORCE_TXCTRL_RATE_EN_HI 2
+#define MTX_DBGOPT_FORCE_TXCTRL_RATE_EN_SZ 1
+#define MTX_DBGOPT_FORCE_DO_RTS_CTS_MODE_EN_MSK 0x00000010
+#define MTX_DBGOPT_FORCE_DO_RTS_CTS_MODE_EN_I_MSK 0xffffffef
+#define MTX_DBGOPT_FORCE_DO_RTS_CTS_MODE_EN_SFT 4
+#define MTX_DBGOPT_FORCE_DO_RTS_CTS_MODE_EN_HI 4
+#define MTX_DBGOPT_FORCE_DO_RTS_CTS_MODE_EN_SZ 1
+#define RO_PHYTXIP_TIMEOUT_CNT_MSK 0x0000000f
+#define RO_PHYTXIP_TIMEOUT_CNT_I_MSK 0xfffffff0
+#define RO_PHYTXIP_TIMEOUT_CNT_SFT 0
+#define RO_PHYTXIP_TIMEOUT_CNT_HI 3
+#define RO_PHYTXIP_TIMEOUT_CNT_SZ 4
+#define DBG_PHYTXIP_TIMEOUT_RECOVERY_MSK 0x00000100
+#define DBG_PHYTXIP_TIMEOUT_RECOVERY_I_MSK 0xfffffeff
+#define DBG_PHYTXIP_TIMEOUT_RECOVERY_SFT 8
+#define DBG_PHYTXIP_TIMEOUT_RECOVERY_HI 8
+#define DBG_PHYTXIP_TIMEOUT_RECOVERY_SZ 1
+#define DBG_MTX_IGNORE_NAV_MSK 0x00000001
+#define DBG_MTX_IGNORE_NAV_I_MSK 0xfffffffe
+#define DBG_MTX_IGNORE_NAV_SFT 0
+#define DBG_MTX_IGNORE_NAV_HI 0
+#define DBG_MTX_IGNORE_NAV_SZ 1
+#define RO_IFSAIR1_MSK 0xffffffff
+#define RO_IFSAIR1_I_MSK 0x00000000
+#define RO_IFSAIR1_SFT 0
+#define RO_IFSAIR1_HI 31
+#define RO_IFSAIR1_SZ 32
+#define RO_IFSAIR2_MSK 0xffffffff
+#define RO_IFSAIR2_I_MSK 0x00000000
+#define RO_IFSAIR2_SFT 0
+#define RO_IFSAIR2_HI 31
+#define RO_IFSAIR2_SZ 32
+#define MTX_BCN_PKT_ID0_MSK 0x0000007f
+#define MTX_BCN_PKT_ID0_I_MSK 0xffffff80
+#define MTX_BCN_PKT_ID0_SFT 0
+#define MTX_BCN_PKT_ID0_HI 6
+#define MTX_BCN_PKT_ID0_SZ 7
+#define MTX_BCN_PKT_ID1_MSK 0x0000007f
+#define MTX_BCN_PKT_ID1_I_MSK 0xffffff80
+#define MTX_BCN_PKT_ID1_SFT 0
+#define MTX_BCN_PKT_ID1_HI 6
+#define MTX_BCN_PKT_ID1_SZ 7
+#define MTX_DTIM_OFST0_MSK 0x000003ff
+#define MTX_DTIM_OFST0_I_MSK 0xfffffc00
+#define MTX_DTIM_OFST0_SFT 0
+#define MTX_DTIM_OFST0_HI 9
+#define MTX_DTIM_OFST0_SZ 10
+#define MTX_DTIM_OFST1_MSK 0x000003ff
+#define MTX_DTIM_OFST1_I_MSK 0xfffffc00
+#define MTX_DTIM_OFST1_SFT 0
+#define MTX_DTIM_OFST1_HI 9
+#define MTX_DTIM_OFST1_SZ 10
+#define MTX_DTIM_NUM_MSK 0x000000ff
+#define MTX_DTIM_NUM_I_MSK 0xffffff00
+#define MTX_DTIM_NUM_SFT 0
+#define MTX_DTIM_NUM_HI 7
+#define MTX_DTIM_NUM_SZ 8
+#define MTX_INT_DTIM_NUM_MSK 0x0000ff00
+#define MTX_INT_DTIM_NUM_I_MSK 0xffff00ff
+#define MTX_INT_DTIM_NUM_SFT 8
+#define MTX_INT_DTIM_NUM_HI 15
+#define MTX_INT_DTIM_NUM_SZ 8
+#define MTX_INT_DTIM_MSK 0x00000001
+#define MTX_INT_DTIM_I_MSK 0xfffffffe
+#define MTX_INT_DTIM_SFT 0
+#define MTX_INT_DTIM_HI 0
+#define MTX_INT_DTIM_SZ 1
+#define MTX_INT_BCN_MSK 0x00000001
+#define MTX_INT_BCN_I_MSK 0xfffffffe
+#define MTX_INT_BCN_SFT 0
+#define MTX_INT_BCN_HI 0
+#define MTX_INT_BCN_SZ 1
+#define MTX_EN_INT_BCN_MSK 0x00000002
+#define MTX_EN_INT_BCN_I_MSK 0xfffffffd
+#define MTX_EN_INT_BCN_SFT 1
+#define MTX_EN_INT_BCN_HI 1
+#define MTX_EN_INT_BCN_SZ 1
+#define MTX_EN_INT_DTIM_MSK 0x00000008
+#define MTX_EN_INT_DTIM_I_MSK 0xfffffff7
+#define MTX_EN_INT_DTIM_SFT 3
+#define MTX_EN_INT_DTIM_HI 3
+#define MTX_EN_INT_DTIM_SZ 1
+#define MTX_BCN_TIMER_EN_MSK 0x00000001
+#define MTX_BCN_TIMER_EN_I_MSK 0xfffffffe
+#define MTX_BCN_TIMER_EN_SFT 0
+#define MTX_BCN_TIMER_EN_HI 0
+#define MTX_BCN_TIMER_EN_SZ 1
+#define MTX_TIME_STAMP_AUTO_FILL_MSK 0x00000002
+#define MTX_TIME_STAMP_AUTO_FILL_I_MSK 0xfffffffd
+#define MTX_TIME_STAMP_AUTO_FILL_SFT 1
+#define MTX_TIME_STAMP_AUTO_FILL_HI 1
+#define MTX_TIME_STAMP_AUTO_FILL_SZ 1
+#define MTX_DTIM_CNT_AUTO_FILL_MSK 0x00000008
+#define MTX_DTIM_CNT_AUTO_FILL_I_MSK 0xfffffff7
+#define MTX_DTIM_CNT_AUTO_FILL_SFT 3
+#define MTX_DTIM_CNT_AUTO_FILL_HI 3
+#define MTX_DTIM_CNT_AUTO_FILL_SZ 1
+#define MTX_TSF_TIMER_EN_MSK 0x00000020
+#define MTX_TSF_TIMER_EN_I_MSK 0xffffffdf
+#define MTX_TSF_TIMER_EN_SFT 5
+#define MTX_TSF_TIMER_EN_HI 5
+#define MTX_TSF_TIMER_EN_SZ 1
+#define TXQ5_DTIM_BEACON_BURST_MNG_MSK 0x00010000
+#define TXQ5_DTIM_BEACON_BURST_MNG_I_MSK 0xfffeffff
+#define TXQ5_DTIM_BEACON_BURST_MNG_SFT 16
+#define TXQ5_DTIM_BEACON_BURST_MNG_HI 16
+#define TXQ5_DTIM_BEACON_BURST_MNG_SZ 1
+#define MTX_BCN_AUTO_SEQ_NO_MSK 0x00020000
+#define MTX_BCN_AUTO_SEQ_NO_I_MSK 0xfffdffff
+#define MTX_BCN_AUTO_SEQ_NO_SFT 17
+#define MTX_BCN_AUTO_SEQ_NO_HI 17
+#define MTX_BCN_AUTO_SEQ_NO_SZ 1
+#define MTX_BCN_PKTID_CH_LOCK_MSK 0x00000001
+#define MTX_BCN_PKTID_CH_LOCK_I_MSK 0xfffffffe
+#define MTX_BCN_PKTID_CH_LOCK_SFT 0
+#define MTX_BCN_PKTID_CH_LOCK_HI 0
+#define MTX_BCN_PKTID_CH_LOCK_SZ 1
+#define MTX_BCN_CFG_VLD_MSK 0x00000006
+#define MTX_BCN_CFG_VLD_I_MSK 0xfffffff9
+#define MTX_BCN_CFG_VLD_SFT 1
+#define MTX_BCN_CFG_VLD_HI 2
+#define MTX_BCN_CFG_VLD_SZ 2
+#define MTX_AUTO_BCN_ONGOING_MSK 0x00000008
+#define MTX_AUTO_BCN_ONGOING_I_MSK 0xfffffff7
+#define MTX_AUTO_BCN_ONGOING_SFT 3
+#define MTX_AUTO_BCN_ONGOING_HI 3
+#define MTX_AUTO_BCN_ONGOING_SZ 1
+#define MTX_BCN_TIMER_MSK 0xffff0000
+#define MTX_BCN_TIMER_I_MSK 0x0000ffff
+#define MTX_BCN_TIMER_SFT 16
+#define MTX_BCN_TIMER_HI 31
+#define MTX_BCN_TIMER_SZ 16
+#define MTX_BCN_PERIOD_MSK 0x0000ffff
+#define MTX_BCN_PERIOD_I_MSK 0xffff0000
+#define MTX_BCN_PERIOD_SFT 0
+#define MTX_BCN_PERIOD_HI 15
+#define MTX_BCN_PERIOD_SZ 16
+#define MTX_BCN_TSF_L_MSK 0xffffffff
+#define MTX_BCN_TSF_L_I_MSK 0x00000000
+#define MTX_BCN_TSF_L_SFT 0
+#define MTX_BCN_TSF_L_HI 31
+#define MTX_BCN_TSF_L_SZ 32
+#define MTX_BCN_TSF_U_MSK 0xffffffff
+#define MTX_BCN_TSF_U_I_MSK 0x00000000
+#define MTX_BCN_TSF_U_SFT 0
+#define MTX_BCN_TSF_U_HI 31
+#define MTX_BCN_TSF_U_SZ 32
+#define TOUT_B_MSK 0x000000ff
+#define TOUT_B_I_MSK 0xffffff00
+#define TOUT_B_SFT 0
+#define TOUT_B_HI 7
+#define TOUT_B_SZ 8
+#define TOUT_AGN_MSK 0x0000ff00
+#define TOUT_AGN_I_MSK 0xffff00ff
+#define TOUT_AGN_SFT 8
+#define TOUT_AGN_HI 15
+#define TOUT_AGN_SZ 8
+#define EIFS_IN_SLOT_MSK 0x003f0000
+#define EIFS_IN_SLOT_I_MSK 0xffc0ffff
+#define EIFS_IN_SLOT_SFT 16
+#define EIFS_IN_SLOT_HI 21
+#define EIFS_IN_SLOT_SZ 6
+#define TXSIFS_SUB_MIN_MSK 0x0000000f
+#define TXSIFS_SUB_MIN_I_MSK 0xfffffff0
+#define TXSIFS_SUB_MIN_SFT 0
+#define TXSIFS_SUB_MIN_HI 3
+#define TXSIFS_SUB_MIN_SZ 4
+#define TXSIFS_SUB_MAX_MSK 0x000000f0
+#define TXSIFS_SUB_MAX_I_MSK 0xffffff0f
+#define TXSIFS_SUB_MAX_SFT 4
+#define TXSIFS_SUB_MAX_HI 7
+#define TXSIFS_SUB_MAX_SZ 4
+#define SLOTTIME_MSK 0x00001f00
+#define SLOTTIME_I_MSK 0xffffe0ff
+#define SLOTTIME_SFT 8
+#define SLOTTIME_HI 12
+#define SLOTTIME_SZ 5
+#define SIFS_MSK 0x001f0000
+#define SIFS_I_MSK 0xffe0ffff
+#define SIFS_SFT 16
+#define SIFS_HI 20
+#define SIFS_SZ 5
+#define NAVCS_PHYCS_FALL_OFFSET_STEP_MSK 0x0000007f
+#define NAVCS_PHYCS_FALL_OFFSET_STEP_I_MSK 0xffffff80
+#define NAVCS_PHYCS_FALL_OFFSET_STEP_SFT 0
+#define NAVCS_PHYCS_FALL_OFFSET_STEP_HI 6
+#define NAVCS_PHYCS_FALL_OFFSET_STEP_SZ 7
+#define TX_IP_FALL_OFFSET_STEP_MSK 0x00007f00
+#define TX_IP_FALL_OFFSET_STEP_I_MSK 0xffff80ff
+#define TX_IP_FALL_OFFSET_STEP_SFT 8
+#define TX_IP_FALL_OFFSET_STEP_HI 14
+#define TX_IP_FALL_OFFSET_STEP_SZ 7
+#define PHYTXSTART_NCYCLE_MSK 0x007f0000
+#define PHYTXSTART_NCYCLE_I_MSK 0xff80ffff
+#define PHYTXSTART_NCYCLE_SFT 16
+#define PHYTXSTART_NCYCLE_HI 22
+#define PHYTXSTART_NCYCLE_SZ 7
+#define SIGEXT_MSK 0x0f000000
+#define SIGEXT_I_MSK 0xf0ffffff
+#define SIGEXT_SFT 24
+#define SIGEXT_HI 27
+#define SIGEXT_SZ 4
+#define MAC_CLK_80M_MSK 0x10000000
+#define MAC_CLK_80M_I_MSK 0xefffffff
+#define MAC_CLK_80M_SFT 28
+#define MAC_CLK_80M_HI 28
+#define MAC_CLK_80M_SZ 1
+#define RO_MTX_TX_EN_MSK 0x00100000
+#define RO_MTX_TX_EN_I_MSK 0xffefffff
+#define RO_MTX_TX_EN_SFT 20
+#define RO_MTX_TX_EN_HI 20
+#define RO_MTX_TX_EN_SZ 1
+#define RO_MAC_TX_FIFO_WINC_MSK 0x00200000
+#define RO_MAC_TX_FIFO_WINC_I_MSK 0xffdfffff
+#define RO_MAC_TX_FIFO_WINC_SFT 21
+#define RO_MAC_TX_FIFO_WINC_HI 21
+#define RO_MAC_TX_FIFO_WINC_SZ 1
+#define RO_MAC_TX_FIFO_WFULL_MX_MSK 0x00400000
+#define RO_MAC_TX_FIFO_WFULL_MX_I_MSK 0xffbfffff
+#define RO_MAC_TX_FIFO_WFULL_MX_SFT 22
+#define RO_MAC_TX_FIFO_WFULL_MX_HI 22
+#define RO_MAC_TX_FIFO_WFULL_MX_SZ 1
+#define RO_MAC_TX_FIFO_WEMPTY_MSK 0x00800000
+#define RO_MAC_TX_FIFO_WEMPTY_I_MSK 0xff7fffff
+#define RO_MAC_TX_FIFO_WEMPTY_SFT 23
+#define RO_MAC_TX_FIFO_WEMPTY_HI 23
+#define RO_MAC_TX_FIFO_WEMPTY_SZ 1
+#define TOMAC_TX_IP_MSK 0x01000000
+#define TOMAC_TX_IP_I_MSK 0xfeffffff
+#define TOMAC_TX_IP_SFT 24
+#define TOMAC_TX_IP_HI 24
+#define TOMAC_TX_IP_SZ 1
+#define TOMAC_ED_CCA_PRIMARY_MX_MSK 0x10000000
+#define TOMAC_ED_CCA_PRIMARY_MX_I_MSK 0xefffffff
+#define TOMAC_ED_CCA_PRIMARY_MX_SFT 28
+#define TOMAC_ED_CCA_PRIMARY_MX_HI 28
+#define TOMAC_ED_CCA_PRIMARY_MX_SZ 1
+#define TOMAC_ED_CCA_SECONDARY_MX_MSK 0x20000000
+#define TOMAC_ED_CCA_SECONDARY_MX_I_MSK 0xdfffffff
+#define TOMAC_ED_CCA_SECONDARY_MX_SFT 29
+#define TOMAC_ED_CCA_SECONDARY_MX_HI 29
+#define TOMAC_ED_CCA_SECONDARY_MX_SZ 1
+#define TOMAC_CS_CCA_MX_MSK 0x40000000
+#define TOMAC_CS_CCA_MX_I_MSK 0xbfffffff
+#define TOMAC_CS_CCA_MX_SFT 30
+#define TOMAC_CS_CCA_MX_HI 30
+#define TOMAC_CS_CCA_MX_SZ 1
+#define BT_BUSY_MSK 0x80000000
+#define BT_BUSY_I_MSK 0x7fffffff
+#define BT_BUSY_SFT 31
+#define BT_BUSY_HI 31
+#define BT_BUSY_SZ 1
+#define MTX_DBG_PHYRX_IFS_DELTATIME_MSK 0x000007ff
+#define MTX_DBG_PHYRX_IFS_DELTATIME_I_MSK 0xfffff800
+#define MTX_DBG_PHYRX_IFS_DELTATIME_SFT 0
+#define MTX_DBG_PHYRX_IFS_DELTATIME_HI 10
+#define MTX_DBG_PHYRX_IFS_DELTATIME_SZ 11
+#define RO_IFSST0_MSK 0xffffffff
+#define RO_IFSST0_I_MSK 0x00000000
+#define RO_IFSST0_SFT 0
+#define RO_IFSST0_HI 31
+#define RO_IFSST0_SZ 32
+#define RO_IFSST1_MSK 0xffffffff
+#define RO_IFSST1_I_MSK 0x00000000
+#define RO_IFSST1_SFT 0
+#define RO_IFSST1_HI 31
+#define RO_IFSST1_SZ 32
+#define RO_IFSST2_MSK 0xffffffff
+#define RO_IFSST2_I_MSK 0x00000000
+#define RO_IFSST2_SFT 0
+#define RO_IFSST2_HI 31
+#define RO_IFSST2_SZ 32
+#define RO_IFSST3_MSK 0xffffffff
+#define RO_IFSST3_I_MSK 0x00000000
+#define RO_IFSST3_SFT 0
+#define RO_IFSST3_HI 31
+#define RO_IFSST3_SZ 32
+#define MTX_NAV_MSK 0x0000ffff
+#define MTX_NAV_I_MSK 0xffff0000
+#define MTX_NAV_SFT 0
+#define MTX_NAV_HI 15
+#define MTX_NAV_SZ 16
+#define RO_MTX_BASE1_MSK 0xffffffff
+#define RO_MTX_BASE1_I_MSK 0x00000000
+#define RO_MTX_BASE1_SFT 0
+#define RO_MTX_BASE1_HI 31
+#define RO_MTX_BASE1_SZ 32
+#define RO_MTX_BASE2_MSK 0xffffffff
+#define RO_MTX_BASE2_I_MSK 0x00000000
+#define RO_MTX_BASE2_SFT 0
+#define RO_MTX_BASE2_HI 31
+#define RO_MTX_BASE2_SZ 32
+#define RO_MTX_BASE3_MSK 0xffffffff
+#define RO_MTX_BASE3_I_MSK 0x00000000
+#define RO_MTX_BASE3_SFT 0
+#define RO_MTX_BASE3_HI 31
+#define RO_MTX_BASE3_SZ 32
+#define TXQ0_MTX_Q_RND_MODE_MSK 0x00000007
+#define TXQ0_MTX_Q_RND_MODE_I_MSK 0xfffffff8
+#define TXQ0_MTX_Q_RND_MODE_SFT 0
+#define TXQ0_MTX_Q_RND_MODE_HI 2
+#define TXQ0_MTX_Q_RND_MODE_SZ 3
+#define TXQ0_MTX_Q_MB_NO_RLS_MSK 0x00000010
+#define TXQ0_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
+#define TXQ0_MTX_Q_MB_NO_RLS_SFT 4
+#define TXQ0_MTX_Q_MB_NO_RLS_HI 4
+#define TXQ0_MTX_Q_MB_NO_RLS_SZ 1
+#define TXQ0_Q_NULLDATAFRAME_GEN_EN_MSK 0x80000000
+#define TXQ0_Q_NULLDATAFRAME_GEN_EN_I_MSK 0x7fffffff
+#define TXQ0_Q_NULLDATAFRAME_GEN_EN_SFT 31
+#define TXQ0_Q_NULLDATAFRAME_GEN_EN_HI 31
+#define TXQ0_Q_NULLDATAFRAME_GEN_EN_SZ 1
+#define TXQ0_MTX_Q_AIFSN_MSK 0x0000000f
+#define TXQ0_MTX_Q_AIFSN_I_MSK 0xfffffff0
+#define TXQ0_MTX_Q_AIFSN_SFT 0
+#define TXQ0_MTX_Q_AIFSN_HI 3
+#define TXQ0_MTX_Q_AIFSN_SZ 4
+#define TXQ0_MTX_Q_ECWMIN_MSK 0x00000f00
+#define TXQ0_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
+#define TXQ0_MTX_Q_ECWMIN_SFT 8
+#define TXQ0_MTX_Q_ECWMIN_HI 11
+#define TXQ0_MTX_Q_ECWMIN_SZ 4
+#define TXQ0_MTX_Q_ECWMAX_MSK 0x0000f000
+#define TXQ0_MTX_Q_ECWMAX_I_MSK 0xffff0fff
+#define TXQ0_MTX_Q_ECWMAX_SFT 12
+#define TXQ0_MTX_Q_ECWMAX_HI 15
+#define TXQ0_MTX_Q_ECWMAX_SZ 4
+#define TXQ0_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
+#define TXQ0_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
+#define TXQ0_MTX_Q_TXOP_LIMIT_SFT 16
+#define TXQ0_MTX_Q_TXOP_LIMIT_HI 31
+#define TXQ0_MTX_Q_TXOP_LIMIT_SZ 16
+#define TXQ0_MTX_Q_BKF_CNT_FIX_MSK 0x0000ffff
+#define TXQ0_MTX_Q_BKF_CNT_FIX_I_MSK 0xffff0000
+#define TXQ0_MTX_Q_BKF_CNT_FIX_SFT 0
+#define TXQ0_MTX_Q_BKF_CNT_FIX_HI 15
+#define TXQ0_MTX_Q_BKF_CNT_FIX_SZ 16
+#define TXQ0_RO_FSM_TXQ_MSK 0x00000003
+#define TXQ0_RO_FSM_TXQ_I_MSK 0xfffffffc
+#define TXQ0_RO_FSM_TXQ_SFT 0
+#define TXQ0_RO_FSM_TXQ_HI 1
+#define TXQ0_RO_FSM_TXQ_SZ 2
+#define TXQ0_RO_TRY_CNT_MSK 0x000000f0
+#define TXQ0_RO_TRY_CNT_I_MSK 0xffffff0f
+#define TXQ0_RO_TRY_CNT_SFT 4
+#define TXQ0_RO_TRY_CNT_HI 7
+#define TXQ0_RO_TRY_CNT_SZ 4
+#define TXQ0_RO_RATESET_IDX_MSK 0x00000300
+#define TXQ0_RO_RATESET_IDX_I_MSK 0xfffffcff
+#define TXQ0_RO_RATESET_IDX_SFT 8
+#define TXQ0_RO_RATESET_IDX_HI 9
+#define TXQ0_RO_RATESET_IDX_SZ 2
+#define TXQ0_RO_AIFS_CNT_MSK 0x0000f000
+#define TXQ0_RO_AIFS_CNT_I_MSK 0xffff0fff
+#define TXQ0_RO_AIFS_CNT_SFT 12
+#define TXQ0_RO_AIFS_CNT_HI 15
+#define TXQ0_RO_AIFS_CNT_SZ 4
+#define TXQ0_RO_BKF_CNT_MSK 0xffff0000
+#define TXQ0_RO_BKF_CNT_I_MSK 0x0000ffff
+#define TXQ0_RO_BKF_CNT_SFT 16
+#define TXQ0_RO_BKF_CNT_HI 31
+#define TXQ0_RO_BKF_CNT_SZ 16
+#define TXQ0_RO_PKTID_MSK 0x0000007f
+#define TXQ0_RO_PKTID_I_MSK 0xffffff80
+#define TXQ0_RO_PKTID_SFT 0
+#define TXQ0_RO_PKTID_HI 6
+#define TXQ0_RO_PKTID_SZ 7
+#define TXQ1_MTX_Q_RND_MODE_MSK 0x00000007
+#define TXQ1_MTX_Q_RND_MODE_I_MSK 0xfffffff8
+#define TXQ1_MTX_Q_RND_MODE_SFT 0
+#define TXQ1_MTX_Q_RND_MODE_HI 2
+#define TXQ1_MTX_Q_RND_MODE_SZ 3
+#define TXQ1_MTX_Q_MB_NO_RLS_MSK 0x00000010
+#define TXQ1_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
+#define TXQ1_MTX_Q_MB_NO_RLS_SFT 4
+#define TXQ1_MTX_Q_MB_NO_RLS_HI 4
+#define TXQ1_MTX_Q_MB_NO_RLS_SZ 1
+#define TXQ1_Q_NULLDATAFRAME_GEN_EN_MSK 0x80000000
+#define TXQ1_Q_NULLDATAFRAME_GEN_EN_I_MSK 0x7fffffff
+#define TXQ1_Q_NULLDATAFRAME_GEN_EN_SFT 31
+#define TXQ1_Q_NULLDATAFRAME_GEN_EN_HI 31
+#define TXQ1_Q_NULLDATAFRAME_GEN_EN_SZ 1
+#define TXQ1_MTX_Q_AIFSN_MSK 0x0000000f
+#define TXQ1_MTX_Q_AIFSN_I_MSK 0xfffffff0
+#define TXQ1_MTX_Q_AIFSN_SFT 0
+#define TXQ1_MTX_Q_AIFSN_HI 3
+#define TXQ1_MTX_Q_AIFSN_SZ 4
+#define TXQ1_MTX_Q_ECWMIN_MSK 0x00000f00
+#define TXQ1_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
+#define TXQ1_MTX_Q_ECWMIN_SFT 8
+#define TXQ1_MTX_Q_ECWMIN_HI 11
+#define TXQ1_MTX_Q_ECWMIN_SZ 4
+#define TXQ1_MTX_Q_ECWMAX_MSK 0x0000f000
+#define TXQ1_MTX_Q_ECWMAX_I_MSK 0xffff0fff
+#define TXQ1_MTX_Q_ECWMAX_SFT 12
+#define TXQ1_MTX_Q_ECWMAX_HI 15
+#define TXQ1_MTX_Q_ECWMAX_SZ 4
+#define TXQ1_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
+#define TXQ1_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
+#define TXQ1_MTX_Q_TXOP_LIMIT_SFT 16
+#define TXQ1_MTX_Q_TXOP_LIMIT_HI 31
+#define TXQ1_MTX_Q_TXOP_LIMIT_SZ 16
+#define TXQ1_MTX_Q_BKF_CNT_FIX_MSK 0x0000ffff
+#define TXQ1_MTX_Q_BKF_CNT_FIX_I_MSK 0xffff0000
+#define TXQ1_MTX_Q_BKF_CNT_FIX_SFT 0
+#define TXQ1_MTX_Q_BKF_CNT_FIX_HI 15
+#define TXQ1_MTX_Q_BKF_CNT_FIX_SZ 16
+#define TXQ1_RO_FSM_TXQ_MSK 0x00000003
+#define TXQ1_RO_FSM_TXQ_I_MSK 0xfffffffc
+#define TXQ1_RO_FSM_TXQ_SFT 0
+#define TXQ1_RO_FSM_TXQ_HI 1
+#define TXQ1_RO_FSM_TXQ_SZ 2
+#define TXQ1_RO_TRY_CNT_MSK 0x000000f0
+#define TXQ1_RO_TRY_CNT_I_MSK 0xffffff0f
+#define TXQ1_RO_TRY_CNT_SFT 4
+#define TXQ1_RO_TRY_CNT_HI 7
+#define TXQ1_RO_TRY_CNT_SZ 4
+#define TXQ1_RO_RATESET_IDX_MSK 0x00000300
+#define TXQ1_RO_RATESET_IDX_I_MSK 0xfffffcff
+#define TXQ1_RO_RATESET_IDX_SFT 8
+#define TXQ1_RO_RATESET_IDX_HI 9
+#define TXQ1_RO_RATESET_IDX_SZ 2
+#define TXQ1_RO_AIFS_CNT_MSK 0x0000f000
+#define TXQ1_RO_AIFS_CNT_I_MSK 0xffff0fff
+#define TXQ1_RO_AIFS_CNT_SFT 12
+#define TXQ1_RO_AIFS_CNT_HI 15
+#define TXQ1_RO_AIFS_CNT_SZ 4
+#define TXQ1_RO_BKF_CNT_MSK 0xffff0000
+#define TXQ1_RO_BKF_CNT_I_MSK 0x0000ffff
+#define TXQ1_RO_BKF_CNT_SFT 16
+#define TXQ1_RO_BKF_CNT_HI 31
+#define TXQ1_RO_BKF_CNT_SZ 16
+#define TXQ1_RO_PKTID_MSK 0x0000007f
+#define TXQ1_RO_PKTID_I_MSK 0xffffff80
+#define TXQ1_RO_PKTID_SFT 0
+#define TXQ1_RO_PKTID_HI 6
+#define TXQ1_RO_PKTID_SZ 7
+#define TXQ2_MTX_Q_RND_MODE_MSK 0x00000007
+#define TXQ2_MTX_Q_RND_MODE_I_MSK 0xfffffff8
+#define TXQ2_MTX_Q_RND_MODE_SFT 0
+#define TXQ2_MTX_Q_RND_MODE_HI 2
+#define TXQ2_MTX_Q_RND_MODE_SZ 3
+#define TXQ2_MTX_Q_MB_NO_RLS_MSK 0x00000010
+#define TXQ2_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
+#define TXQ2_MTX_Q_MB_NO_RLS_SFT 4
+#define TXQ2_MTX_Q_MB_NO_RLS_HI 4
+#define TXQ2_MTX_Q_MB_NO_RLS_SZ 1
+#define TXQ2_Q_NULLDATAFRAME_GEN_EN_MSK 0x80000000
+#define TXQ2_Q_NULLDATAFRAME_GEN_EN_I_MSK 0x7fffffff
+#define TXQ2_Q_NULLDATAFRAME_GEN_EN_SFT 31
+#define TXQ2_Q_NULLDATAFRAME_GEN_EN_HI 31
+#define TXQ2_Q_NULLDATAFRAME_GEN_EN_SZ 1
+#define TXQ2_MTX_Q_AIFSN_MSK 0x0000000f
+#define TXQ2_MTX_Q_AIFSN_I_MSK 0xfffffff0
+#define TXQ2_MTX_Q_AIFSN_SFT 0
+#define TXQ2_MTX_Q_AIFSN_HI 3
+#define TXQ2_MTX_Q_AIFSN_SZ 4
+#define TXQ2_MTX_Q_ECWMIN_MSK 0x00000f00
+#define TXQ2_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
+#define TXQ2_MTX_Q_ECWMIN_SFT 8
+#define TXQ2_MTX_Q_ECWMIN_HI 11
+#define TXQ2_MTX_Q_ECWMIN_SZ 4
+#define TXQ2_MTX_Q_ECWMAX_MSK 0x0000f000
+#define TXQ2_MTX_Q_ECWMAX_I_MSK 0xffff0fff
+#define TXQ2_MTX_Q_ECWMAX_SFT 12
+#define TXQ2_MTX_Q_ECWMAX_HI 15
+#define TXQ2_MTX_Q_ECWMAX_SZ 4
+#define TXQ2_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
+#define TXQ2_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
+#define TXQ2_MTX_Q_TXOP_LIMIT_SFT 16
+#define TXQ2_MTX_Q_TXOP_LIMIT_HI 31
+#define TXQ2_MTX_Q_TXOP_LIMIT_SZ 16
+#define TXQ2_MTX_Q_BKF_CNT_FIX_MSK 0x0000ffff
+#define TXQ2_MTX_Q_BKF_CNT_FIX_I_MSK 0xffff0000
+#define TXQ2_MTX_Q_BKF_CNT_FIX_SFT 0
+#define TXQ2_MTX_Q_BKF_CNT_FIX_HI 15
+#define TXQ2_MTX_Q_BKF_CNT_FIX_SZ 16
+#define TXQ2_RO_FSM_TXQ_MSK 0x00000003
+#define TXQ2_RO_FSM_TXQ_I_MSK 0xfffffffc
+#define TXQ2_RO_FSM_TXQ_SFT 0
+#define TXQ2_RO_FSM_TXQ_HI 1
+#define TXQ2_RO_FSM_TXQ_SZ 2
+#define TXQ2_RO_TRY_CNT_MSK 0x000000f0
+#define TXQ2_RO_TRY_CNT_I_MSK 0xffffff0f
+#define TXQ2_RO_TRY_CNT_SFT 4
+#define TXQ2_RO_TRY_CNT_HI 7
+#define TXQ2_RO_TRY_CNT_SZ 4
+#define TXQ2_RO_RATESET_IDX_MSK 0x00000300
+#define TXQ2_RO_RATESET_IDX_I_MSK 0xfffffcff
+#define TXQ2_RO_RATESET_IDX_SFT 8
+#define TXQ2_RO_RATESET_IDX_HI 9
+#define TXQ2_RO_RATESET_IDX_SZ 2
+#define TXQ2_RO_AIFS_CNT_MSK 0x0000f000
+#define TXQ2_RO_AIFS_CNT_I_MSK 0xffff0fff
+#define TXQ2_RO_AIFS_CNT_SFT 12
+#define TXQ2_RO_AIFS_CNT_HI 15
+#define TXQ2_RO_AIFS_CNT_SZ 4
+#define TXQ2_RO_BKF_CNT_MSK 0xffff0000
+#define TXQ2_RO_BKF_CNT_I_MSK 0x0000ffff
+#define TXQ2_RO_BKF_CNT_SFT 16
+#define TXQ2_RO_BKF_CNT_HI 31
+#define TXQ2_RO_BKF_CNT_SZ 16
+#define TXQ2_RO_PKTID_MSK 0x0000007f
+#define TXQ2_RO_PKTID_I_MSK 0xffffff80
+#define TXQ2_RO_PKTID_SFT 0
+#define TXQ2_RO_PKTID_HI 6
+#define TXQ2_RO_PKTID_SZ 7
+#define TXQ3_MTX_Q_RND_MODE_MSK 0x00000007
+#define TXQ3_MTX_Q_RND_MODE_I_MSK 0xfffffff8
+#define TXQ3_MTX_Q_RND_MODE_SFT 0
+#define TXQ3_MTX_Q_RND_MODE_HI 2
+#define TXQ3_MTX_Q_RND_MODE_SZ 3
+#define TXQ3_MTX_Q_MB_NO_RLS_MSK 0x00000010
+#define TXQ3_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
+#define TXQ3_MTX_Q_MB_NO_RLS_SFT 4
+#define TXQ3_MTX_Q_MB_NO_RLS_HI 4
+#define TXQ3_MTX_Q_MB_NO_RLS_SZ 1
+#define TXQ3_Q_NULLDATAFRAME_GEN_EN_MSK 0x80000000
+#define TXQ3_Q_NULLDATAFRAME_GEN_EN_I_MSK 0x7fffffff
+#define TXQ3_Q_NULLDATAFRAME_GEN_EN_SFT 31
+#define TXQ3_Q_NULLDATAFRAME_GEN_EN_HI 31
+#define TXQ3_Q_NULLDATAFRAME_GEN_EN_SZ 1
+#define TXQ3_MTX_Q_AIFSN_MSK 0x0000000f
+#define TXQ3_MTX_Q_AIFSN_I_MSK 0xfffffff0
+#define TXQ3_MTX_Q_AIFSN_SFT 0
+#define TXQ3_MTX_Q_AIFSN_HI 3
+#define TXQ3_MTX_Q_AIFSN_SZ 4
+#define TXQ3_MTX_Q_ECWMIN_MSK 0x00000f00
+#define TXQ3_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
+#define TXQ3_MTX_Q_ECWMIN_SFT 8
+#define TXQ3_MTX_Q_ECWMIN_HI 11
+#define TXQ3_MTX_Q_ECWMIN_SZ 4
+#define TXQ3_MTX_Q_ECWMAX_MSK 0x0000f000
+#define TXQ3_MTX_Q_ECWMAX_I_MSK 0xffff0fff
+#define TXQ3_MTX_Q_ECWMAX_SFT 12
+#define TXQ3_MTX_Q_ECWMAX_HI 15
+#define TXQ3_MTX_Q_ECWMAX_SZ 4
+#define TXQ3_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
+#define TXQ3_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
+#define TXQ3_MTX_Q_TXOP_LIMIT_SFT 16
+#define TXQ3_MTX_Q_TXOP_LIMIT_HI 31
+#define TXQ3_MTX_Q_TXOP_LIMIT_SZ 16
+#define TXQ3_MTX_Q_BKF_CNT_FIX_MSK 0x0000ffff
+#define TXQ3_MTX_Q_BKF_CNT_FIX_I_MSK 0xffff0000
+#define TXQ3_MTX_Q_BKF_CNT_FIX_SFT 0
+#define TXQ3_MTX_Q_BKF_CNT_FIX_HI 15
+#define TXQ3_MTX_Q_BKF_CNT_FIX_SZ 16
+#define TXQ3_RO_FSM_TXQ_MSK 0x00000003
+#define TXQ3_RO_FSM_TXQ_I_MSK 0xfffffffc
+#define TXQ3_RO_FSM_TXQ_SFT 0
+#define TXQ3_RO_FSM_TXQ_HI 1
+#define TXQ3_RO_FSM_TXQ_SZ 2
+#define TXQ3_RO_TRY_CNT_MSK 0x000000f0
+#define TXQ3_RO_TRY_CNT_I_MSK 0xffffff0f
+#define TXQ3_RO_TRY_CNT_SFT 4
+#define TXQ3_RO_TRY_CNT_HI 7
+#define TXQ3_RO_TRY_CNT_SZ 4
+#define TXQ3_RO_RATESET_IDX_MSK 0x00000300
+#define TXQ3_RO_RATESET_IDX_I_MSK 0xfffffcff
+#define TXQ3_RO_RATESET_IDX_SFT 8
+#define TXQ3_RO_RATESET_IDX_HI 9
+#define TXQ3_RO_RATESET_IDX_SZ 2
+#define TXQ3_RO_AIFS_CNT_MSK 0x0000f000
+#define TXQ3_RO_AIFS_CNT_I_MSK 0xffff0fff
+#define TXQ3_RO_AIFS_CNT_SFT 12
+#define TXQ3_RO_AIFS_CNT_HI 15
+#define TXQ3_RO_AIFS_CNT_SZ 4
+#define TXQ3_RO_BKF_CNT_MSK 0xffff0000
+#define TXQ3_RO_BKF_CNT_I_MSK 0x0000ffff
+#define TXQ3_RO_BKF_CNT_SFT 16
+#define TXQ3_RO_BKF_CNT_HI 31
+#define TXQ3_RO_BKF_CNT_SZ 16
+#define TXQ3_RO_PKTID_MSK 0x0000007f
+#define TXQ3_RO_PKTID_I_MSK 0xffffff80
+#define TXQ3_RO_PKTID_SFT 0
+#define TXQ3_RO_PKTID_HI 6
+#define TXQ3_RO_PKTID_SZ 7
+#define TXQ4_MTX_Q_RND_MODE_MSK 0x00000007
+#define TXQ4_MTX_Q_RND_MODE_I_MSK 0xfffffff8
+#define TXQ4_MTX_Q_RND_MODE_SFT 0
+#define TXQ4_MTX_Q_RND_MODE_HI 2
+#define TXQ4_MTX_Q_RND_MODE_SZ 3
+#define TXQ4_MTX_Q_MB_NO_RLS_MSK 0x00000010
+#define TXQ4_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
+#define TXQ4_MTX_Q_MB_NO_RLS_SFT 4
+#define TXQ4_MTX_Q_MB_NO_RLS_HI 4
+#define TXQ4_MTX_Q_MB_NO_RLS_SZ 1
+#define TXQ4_Q_NULLDATAFRAME_GEN_EN_MSK 0x80000000
+#define TXQ4_Q_NULLDATAFRAME_GEN_EN_I_MSK 0x7fffffff
+#define TXQ4_Q_NULLDATAFRAME_GEN_EN_SFT 31
+#define TXQ4_Q_NULLDATAFRAME_GEN_EN_HI 31
+#define TXQ4_Q_NULLDATAFRAME_GEN_EN_SZ 1
+#define TXQ4_MTX_Q_AIFSN_MSK 0x0000000f
+#define TXQ4_MTX_Q_AIFSN_I_MSK 0xfffffff0
+#define TXQ4_MTX_Q_AIFSN_SFT 0
+#define TXQ4_MTX_Q_AIFSN_HI 3
+#define TXQ4_MTX_Q_AIFSN_SZ 4
+#define TXQ4_MTX_Q_ECWMIN_MSK 0x00000f00
+#define TXQ4_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
+#define TXQ4_MTX_Q_ECWMIN_SFT 8
+#define TXQ4_MTX_Q_ECWMIN_HI 11
+#define TXQ4_MTX_Q_ECWMIN_SZ 4
+#define TXQ4_MTX_Q_ECWMAX_MSK 0x0000f000
+#define TXQ4_MTX_Q_ECWMAX_I_MSK 0xffff0fff
+#define TXQ4_MTX_Q_ECWMAX_SFT 12
+#define TXQ4_MTX_Q_ECWMAX_HI 15
+#define TXQ4_MTX_Q_ECWMAX_SZ 4
+#define TXQ4_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
+#define TXQ4_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
+#define TXQ4_MTX_Q_TXOP_LIMIT_SFT 16
+#define TXQ4_MTX_Q_TXOP_LIMIT_HI 31
+#define TXQ4_MTX_Q_TXOP_LIMIT_SZ 16
+#define TXQ4_MTX_Q_BKF_CNT_FIX_MSK 0x0000ffff
+#define TXQ4_MTX_Q_BKF_CNT_FIX_I_MSK 0xffff0000
+#define TXQ4_MTX_Q_BKF_CNT_FIX_SFT 0
+#define TXQ4_MTX_Q_BKF_CNT_FIX_HI 15
+#define TXQ4_MTX_Q_BKF_CNT_FIX_SZ 16
+#define TXQ4_RO_FSM_TXQ_MSK 0x00000003
+#define TXQ4_RO_FSM_TXQ_I_MSK 0xfffffffc
+#define TXQ4_RO_FSM_TXQ_SFT 0
+#define TXQ4_RO_FSM_TXQ_HI 1
+#define TXQ4_RO_FSM_TXQ_SZ 2
+#define TXQ4_RO_TRY_CNT_MSK 0x000000f0
+#define TXQ4_RO_TRY_CNT_I_MSK 0xffffff0f
+#define TXQ4_RO_TRY_CNT_SFT 4
+#define TXQ4_RO_TRY_CNT_HI 7
+#define TXQ4_RO_TRY_CNT_SZ 4
+#define TXQ4_RO_RATESET_IDX_MSK 0x00000300
+#define TXQ4_RO_RATESET_IDX_I_MSK 0xfffffcff
+#define TXQ4_RO_RATESET_IDX_SFT 8
+#define TXQ4_RO_RATESET_IDX_HI 9
+#define TXQ4_RO_RATESET_IDX_SZ 2
+#define TXQ4_RO_AIFS_CNT_MSK 0x0000f000
+#define TXQ4_RO_AIFS_CNT_I_MSK 0xffff0fff
+#define TXQ4_RO_AIFS_CNT_SFT 12
+#define TXQ4_RO_AIFS_CNT_HI 15
+#define TXQ4_RO_AIFS_CNT_SZ 4
+#define TXQ4_RO_BKF_CNT_MSK 0xffff0000
+#define TXQ4_RO_BKF_CNT_I_MSK 0x0000ffff
+#define TXQ4_RO_BKF_CNT_SFT 16
+#define TXQ4_RO_BKF_CNT_HI 31
+#define TXQ4_RO_BKF_CNT_SZ 16
+#define TXQ4_RO_PKTID_MSK 0x0000007f
+#define TXQ4_RO_PKTID_I_MSK 0xffffff80
+#define TXQ4_RO_PKTID_SFT 0
+#define TXQ4_RO_PKTID_HI 6
+#define TXQ4_RO_PKTID_SZ 7
+#define TXQ5_MTX_Q_RND_MODE_MSK 0x00000007
+#define TXQ5_MTX_Q_RND_MODE_I_MSK 0xfffffff8
+#define TXQ5_MTX_Q_RND_MODE_SFT 0
+#define TXQ5_MTX_Q_RND_MODE_HI 2
+#define TXQ5_MTX_Q_RND_MODE_SZ 3
+#define TXQ5_MTX_Q_MB_NO_RLS_MSK 0x00000010
+#define TXQ5_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
+#define TXQ5_MTX_Q_MB_NO_RLS_SFT 4
+#define TXQ5_MTX_Q_MB_NO_RLS_HI 4
+#define TXQ5_MTX_Q_MB_NO_RLS_SZ 1
+#define TXQ5_Q_NULLDATAFRAME_GEN_EN_MSK 0x80000000
+#define TXQ5_Q_NULLDATAFRAME_GEN_EN_I_MSK 0x7fffffff
+#define TXQ5_Q_NULLDATAFRAME_GEN_EN_SFT 31
+#define TXQ5_Q_NULLDATAFRAME_GEN_EN_HI 31
+#define TXQ5_Q_NULLDATAFRAME_GEN_EN_SZ 1
+#define TXQ5_MTX_Q_AIFSN_MSK 0x0000000f
+#define TXQ5_MTX_Q_AIFSN_I_MSK 0xfffffff0
+#define TXQ5_MTX_Q_AIFSN_SFT 0
+#define TXQ5_MTX_Q_AIFSN_HI 3
+#define TXQ5_MTX_Q_AIFSN_SZ 4
+#define TXQ5_MTX_Q_ECWMIN_MSK 0x00000f00
+#define TXQ5_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
+#define TXQ5_MTX_Q_ECWMIN_SFT 8
+#define TXQ5_MTX_Q_ECWMIN_HI 11
+#define TXQ5_MTX_Q_ECWMIN_SZ 4
+#define TXQ5_MTX_Q_ECWMAX_MSK 0x0000f000
+#define TXQ5_MTX_Q_ECWMAX_I_MSK 0xffff0fff
+#define TXQ5_MTX_Q_ECWMAX_SFT 12
+#define TXQ5_MTX_Q_ECWMAX_HI 15
+#define TXQ5_MTX_Q_ECWMAX_SZ 4
+#define TXQ5_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
+#define TXQ5_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
+#define TXQ5_MTX_Q_TXOP_LIMIT_SFT 16
+#define TXQ5_MTX_Q_TXOP_LIMIT_HI 31
+#define TXQ5_MTX_Q_TXOP_LIMIT_SZ 16
+#define TXQ5_MTX_Q_BKF_CNT_FIX_MSK 0x0000ffff
+#define TXQ5_MTX_Q_BKF_CNT_FIX_I_MSK 0xffff0000
+#define TXQ5_MTX_Q_BKF_CNT_FIX_SFT 0
+#define TXQ5_MTX_Q_BKF_CNT_FIX_HI 15
+#define TXQ5_MTX_Q_BKF_CNT_FIX_SZ 16
+#define TXQ5_RO_FSM_TXQ_MSK 0x00000003
+#define TXQ5_RO_FSM_TXQ_I_MSK 0xfffffffc
+#define TXQ5_RO_FSM_TXQ_SFT 0
+#define TXQ5_RO_FSM_TXQ_HI 1
+#define TXQ5_RO_FSM_TXQ_SZ 2
+#define TXQ5_RO_TRY_CNT_MSK 0x000000f0
+#define TXQ5_RO_TRY_CNT_I_MSK 0xffffff0f
+#define TXQ5_RO_TRY_CNT_SFT 4
+#define TXQ5_RO_TRY_CNT_HI 7
+#define TXQ5_RO_TRY_CNT_SZ 4
+#define TXQ5_RO_RATESET_IDX_MSK 0x00000300
+#define TXQ5_RO_RATESET_IDX_I_MSK 0xfffffcff
+#define TXQ5_RO_RATESET_IDX_SFT 8
+#define TXQ5_RO_RATESET_IDX_HI 9
+#define TXQ5_RO_RATESET_IDX_SZ 2
+#define TXQ5_RO_AIFS_CNT_MSK 0x0000f000
+#define TXQ5_RO_AIFS_CNT_I_MSK 0xffff0fff
+#define TXQ5_RO_AIFS_CNT_SFT 12
+#define TXQ5_RO_AIFS_CNT_HI 15
+#define TXQ5_RO_AIFS_CNT_SZ 4
+#define TXQ5_RO_BKF_CNT_MSK 0xffff0000
+#define TXQ5_RO_BKF_CNT_I_MSK 0x0000ffff
+#define TXQ5_RO_BKF_CNT_SFT 16
+#define TXQ5_RO_BKF_CNT_HI 31
+#define TXQ5_RO_BKF_CNT_SZ 16
+#define TXQ5_RO_PKTID_MSK 0x0000007f
+#define TXQ5_RO_PKTID_I_MSK 0xffffff80
+#define TXQ5_RO_PKTID_SFT 0
+#define TXQ5_RO_PKTID_HI 6
+#define TXQ5_RO_PKTID_SZ 7
+#define MTX_RESPFRM_RATE_EXCEPTION_MSK 0x0000ffff
+#define MTX_RESPFRM_RATE_EXCEPTION_I_MSK 0xffff0000
+#define MTX_RESPFRM_RATE_EXCEPTION_SFT 0
+#define MTX_RESPFRM_RATE_EXCEPTION_HI 15
+#define MTX_RESPFRM_RATE_EXCEPTION_SZ 16
+#define MTX_RESPFRM_RATE_00_MSK 0x0000ffff
+#define MTX_RESPFRM_RATE_00_I_MSK 0xffff0000
+#define MTX_RESPFRM_RATE_00_SFT 0
+#define MTX_RESPFRM_RATE_00_HI 15
+#define MTX_RESPFRM_RATE_00_SZ 16
+#define MTX_RESPFRM_RATE_01_MSK 0x0000ffff
+#define MTX_RESPFRM_RATE_01_I_MSK 0xffff0000
+#define MTX_RESPFRM_RATE_01_SFT 0
+#define MTX_RESPFRM_RATE_01_HI 15
+#define MTX_RESPFRM_RATE_01_SZ 16
+#define MTX_RESPFRM_RATE_02_MSK 0x0000ffff
+#define MTX_RESPFRM_RATE_02_I_MSK 0xffff0000
+#define MTX_RESPFRM_RATE_02_SFT 0
+#define MTX_RESPFRM_RATE_02_HI 15
+#define MTX_RESPFRM_RATE_02_SZ 16
+#define MTX_RESPFRM_RATE_03_MSK 0x0000ffff
+#define MTX_RESPFRM_RATE_03_I_MSK 0xffff0000
+#define MTX_RESPFRM_RATE_03_SFT 0
+#define MTX_RESPFRM_RATE_03_HI 15
+#define MTX_RESPFRM_RATE_03_SZ 16
+#define MTX_RESPFRM_RATE_11_MSK 0x0000ffff
+#define MTX_RESPFRM_RATE_11_I_MSK 0xffff0000
+#define MTX_RESPFRM_RATE_11_SFT 0
+#define MTX_RESPFRM_RATE_11_HI 15
+#define MTX_RESPFRM_RATE_11_SZ 16
+#define MTX_RESPFRM_RATE_12_MSK 0x0000ffff
+#define MTX_RESPFRM_RATE_12_I_MSK 0xffff0000
+#define MTX_RESPFRM_RATE_12_SFT 0
+#define MTX_RESPFRM_RATE_12_HI 15
+#define MTX_RESPFRM_RATE_12_SZ 16
+#define MTX_RESPFRM_RATE_13_MSK 0x0000ffff
+#define MTX_RESPFRM_RATE_13_I_MSK 0xffff0000
+#define MTX_RESPFRM_RATE_13_SFT 0
+#define MTX_RESPFRM_RATE_13_HI 15
+#define MTX_RESPFRM_RATE_13_SZ 16
+#define MTX_RESPFRM_RATE_90_B0_MSK 0x0000ffff
+#define MTX_RESPFRM_RATE_90_B0_I_MSK 0xffff0000
+#define MTX_RESPFRM_RATE_90_B0_SFT 0
+#define MTX_RESPFRM_RATE_90_B0_HI 15
+#define MTX_RESPFRM_RATE_90_B0_SZ 16
+#define MTX_RESPFRM_RATE_91_B1_MSK 0x0000ffff
+#define MTX_RESPFRM_RATE_91_B1_I_MSK 0xffff0000
+#define MTX_RESPFRM_RATE_91_B1_SFT 0
+#define MTX_RESPFRM_RATE_91_B1_HI 15
+#define MTX_RESPFRM_RATE_91_B1_SZ 16
+#define MTX_RESPFRM_RATE_92_B2_MSK 0x0000ffff
+#define MTX_RESPFRM_RATE_92_B2_I_MSK 0xffff0000
+#define MTX_RESPFRM_RATE_92_B2_SFT 0
+#define MTX_RESPFRM_RATE_92_B2_HI 15
+#define MTX_RESPFRM_RATE_92_B2_SZ 16
+#define MTX_RESPFRM_RATE_93_B3_MSK 0x0000ffff
+#define MTX_RESPFRM_RATE_93_B3_I_MSK 0xffff0000
+#define MTX_RESPFRM_RATE_93_B3_SFT 0
+#define MTX_RESPFRM_RATE_93_B3_HI 15
+#define MTX_RESPFRM_RATE_93_B3_SZ 16
+#define MTX_RESPFRM_RATE_94_B4_MSK 0x0000ffff
+#define MTX_RESPFRM_RATE_94_B4_I_MSK 0xffff0000
+#define MTX_RESPFRM_RATE_94_B4_SFT 0
+#define MTX_RESPFRM_RATE_94_B4_HI 15
+#define MTX_RESPFRM_RATE_94_B4_SZ 16
+#define MTX_RESPFRM_RATE_95_B5_MSK 0x0000ffff
+#define MTX_RESPFRM_RATE_95_B5_I_MSK 0xffff0000
+#define MTX_RESPFRM_RATE_95_B5_SFT 0
+#define MTX_RESPFRM_RATE_95_B5_HI 15
+#define MTX_RESPFRM_RATE_95_B5_SZ 16
+#define MTX_RESPFRM_RATE_96_B6_MSK 0x0000ffff
+#define MTX_RESPFRM_RATE_96_B6_I_MSK 0xffff0000
+#define MTX_RESPFRM_RATE_96_B6_SFT 0
+#define MTX_RESPFRM_RATE_96_B6_HI 15
+#define MTX_RESPFRM_RATE_96_B6_SZ 16
+#define MTX_RESPFRM_RATE_97_B7_MSK 0x0000ffff
+#define MTX_RESPFRM_RATE_97_B7_I_MSK 0xffff0000
+#define MTX_RESPFRM_RATE_97_B7_SFT 0
+#define MTX_RESPFRM_RATE_97_B7_HI 15
+#define MTX_RESPFRM_RATE_97_B7_SZ 16
+#define MTX_RESPFRM_RATE_C0_E0_MSK 0x0000ffff
+#define MTX_RESPFRM_RATE_C0_E0_I_MSK 0xffff0000
+#define MTX_RESPFRM_RATE_C0_E0_SFT 0
+#define MTX_RESPFRM_RATE_C0_E0_HI 15
+#define MTX_RESPFRM_RATE_C0_E0_SZ 16
+#define MTX_RESPFRM_RATE_C1_E1_MSK 0x0000ffff
+#define MTX_RESPFRM_RATE_C1_E1_I_MSK 0xffff0000
+#define MTX_RESPFRM_RATE_C1_E1_SFT 0
+#define MTX_RESPFRM_RATE_C1_E1_HI 15
+#define MTX_RESPFRM_RATE_C1_E1_SZ 16
+#define MTX_RESPFRM_RATE_C2_E2_MSK 0x0000ffff
+#define MTX_RESPFRM_RATE_C2_E2_I_MSK 0xffff0000
+#define MTX_RESPFRM_RATE_C2_E2_SFT 0
+#define MTX_RESPFRM_RATE_C2_E2_HI 15
+#define MTX_RESPFRM_RATE_C2_E2_SZ 16
+#define MTX_RESPFRM_RATE_C3_E3_MSK 0x0000ffff
+#define MTX_RESPFRM_RATE_C3_E3_I_MSK 0xffff0000
+#define MTX_RESPFRM_RATE_C3_E3_SFT 0
+#define MTX_RESPFRM_RATE_C3_E3_HI 15
+#define MTX_RESPFRM_RATE_C3_E3_SZ 16
+#define MTX_RESPFRM_RATE_C4_E4_MSK 0x0000ffff
+#define MTX_RESPFRM_RATE_C4_E4_I_MSK 0xffff0000
+#define MTX_RESPFRM_RATE_C4_E4_SFT 0
+#define MTX_RESPFRM_RATE_C4_E4_HI 15
+#define MTX_RESPFRM_RATE_C4_E4_SZ 16
+#define MTX_RESPFRM_RATE_C5_E5_MSK 0x0000ffff
+#define MTX_RESPFRM_RATE_C5_E5_I_MSK 0xffff0000
+#define MTX_RESPFRM_RATE_C5_E5_SFT 0
+#define MTX_RESPFRM_RATE_C5_E5_HI 15
+#define MTX_RESPFRM_RATE_C5_E5_SZ 16
+#define MTX_RESPFRM_RATE_C6_E6_MSK 0x0000ffff
+#define MTX_RESPFRM_RATE_C6_E6_I_MSK 0xffff0000
+#define MTX_RESPFRM_RATE_C6_E6_SFT 0
+#define MTX_RESPFRM_RATE_C6_E6_HI 15
+#define MTX_RESPFRM_RATE_C6_E6_SZ 16
+#define MTX_RESPFRM_RATE_C7_E7_MSK 0x0000ffff
+#define MTX_RESPFRM_RATE_C7_E7_I_MSK 0xffff0000
+#define MTX_RESPFRM_RATE_C7_E7_SFT 0
+#define MTX_RESPFRM_RATE_C7_E7_HI 15
+#define MTX_RESPFRM_RATE_C7_E7_SZ 16
+#define MTX_RESPFRM_RATE_D0_F0_MSK 0x0000ffff
+#define MTX_RESPFRM_RATE_D0_F0_I_MSK 0xffff0000
+#define MTX_RESPFRM_RATE_D0_F0_SFT 0
+#define MTX_RESPFRM_RATE_D0_F0_HI 15
+#define MTX_RESPFRM_RATE_D0_F0_SZ 16
+#define MTX_RESPFRM_RATE_D1_F1_MSK 0x0000ffff
+#define MTX_RESPFRM_RATE_D1_F1_I_MSK 0xffff0000
+#define MTX_RESPFRM_RATE_D1_F1_SFT 0
+#define MTX_RESPFRM_RATE_D1_F1_HI 15
+#define MTX_RESPFRM_RATE_D1_F1_SZ 16
+#define MTX_RESPFRM_RATE_D2_F2_MSK 0x0000ffff
+#define MTX_RESPFRM_RATE_D2_F2_I_MSK 0xffff0000
+#define MTX_RESPFRM_RATE_D2_F2_SFT 0
+#define MTX_RESPFRM_RATE_D2_F2_HI 15
+#define MTX_RESPFRM_RATE_D2_F2_SZ 16
+#define MTX_RESPFRM_RATE_D3_F3_MSK 0x0000ffff
+#define MTX_RESPFRM_RATE_D3_F3_I_MSK 0xffff0000
+#define MTX_RESPFRM_RATE_D3_F3_SFT 0
+#define MTX_RESPFRM_RATE_D3_F3_HI 15
+#define MTX_RESPFRM_RATE_D3_F3_SZ 16
+#define MTX_RESPFRM_RATE_D4_F4_MSK 0x0000ffff
+#define MTX_RESPFRM_RATE_D4_F4_I_MSK 0xffff0000
+#define MTX_RESPFRM_RATE_D4_F4_SFT 0
+#define MTX_RESPFRM_RATE_D4_F4_HI 15
+#define MTX_RESPFRM_RATE_D4_F4_SZ 16
+#define MTX_RESPFRM_RATE_D5_F5_MSK 0x0000ffff
+#define MTX_RESPFRM_RATE_D5_F5_I_MSK 0xffff0000
+#define MTX_RESPFRM_RATE_D5_F5_SFT 0
+#define MTX_RESPFRM_RATE_D5_F5_HI 15
+#define MTX_RESPFRM_RATE_D5_F5_SZ 16
+#define MTX_RESPFRM_RATE_D6_F6_MSK 0x0000ffff
+#define MTX_RESPFRM_RATE_D6_F6_I_MSK 0xffff0000
+#define MTX_RESPFRM_RATE_D6_F6_SFT 0
+#define MTX_RESPFRM_RATE_D6_F6_HI 15
+#define MTX_RESPFRM_RATE_D6_F6_SZ 16
+#define MTX_RESPFRM_RATE_D7_F7_MSK 0x0000ffff
+#define MTX_RESPFRM_RATE_D7_F7_I_MSK 0xffff0000
+#define MTX_RESPFRM_RATE_D7_F7_SFT 0
+#define MTX_RESPFRM_RATE_D7_F7_HI 15
+#define MTX_RESPFRM_RATE_D7_F7_SZ 16
+#define MTX_RESPFRM_RATE_D8_F8_MSK 0x0000ffff
+#define MTX_RESPFRM_RATE_D8_F8_I_MSK 0xffff0000
+#define MTX_RESPFRM_RATE_D8_F8_SFT 0
+#define MTX_RESPFRM_RATE_D8_F8_HI 15
+#define MTX_RESPFRM_RATE_D8_F8_SZ 16
+#define MTX_RESPFRM_RATE_D9_F9_MSK 0x0000ffff
+#define MTX_RESPFRM_RATE_D9_F9_I_MSK 0xffff0000
+#define MTX_RESPFRM_RATE_D9_F9_SFT 0
+#define MTX_RESPFRM_RATE_D9_F9_HI 15
+#define MTX_RESPFRM_RATE_D9_F9_SZ 16
+#define MTX_RESPFRM_RATE_DA_FA_MSK 0x0000ffff
+#define MTX_RESPFRM_RATE_DA_FA_I_MSK 0xffff0000
+#define MTX_RESPFRM_RATE_DA_FA_SFT 0
+#define MTX_RESPFRM_RATE_DA_FA_HI 15
+#define MTX_RESPFRM_RATE_DA_FA_SZ 16
+#define MTX_RESPFRM_RATE_DB_FB_MSK 0x0000ffff
+#define MTX_RESPFRM_RATE_DB_FB_I_MSK 0xffff0000
+#define MTX_RESPFRM_RATE_DB_FB_SFT 0
+#define MTX_RESPFRM_RATE_DB_FB_HI 15
+#define MTX_RESPFRM_RATE_DB_FB_SZ 16
+#define MTX_RESPFRM_RATE_DC_FC_MSK 0x0000ffff
+#define MTX_RESPFRM_RATE_DC_FC_I_MSK 0xffff0000
+#define MTX_RESPFRM_RATE_DC_FC_SFT 0
+#define MTX_RESPFRM_RATE_DC_FC_HI 15
+#define MTX_RESPFRM_RATE_DC_FC_SZ 16
+#define MTX_RESPFRM_RATE_DD_FD_MSK 0x0000ffff
+#define MTX_RESPFRM_RATE_DD_FD_I_MSK 0xffff0000
+#define MTX_RESPFRM_RATE_DD_FD_SFT 0
+#define MTX_RESPFRM_RATE_DD_FD_HI 15
+#define MTX_RESPFRM_RATE_DD_FD_SZ 16
+#define MTX_RESPFRM_RATE_DE_FE_MSK 0x0000ffff
+#define MTX_RESPFRM_RATE_DE_FE_I_MSK 0xffff0000
+#define MTX_RESPFRM_RATE_DE_FE_SFT 0
+#define MTX_RESPFRM_RATE_DE_FE_HI 15
+#define MTX_RESPFRM_RATE_DE_FE_SZ 16
+#define MTX_RESPFRM_RATE_DF_FF_MSK 0x0000ffff
+#define MTX_RESPFRM_RATE_DF_FF_I_MSK 0xffff0000
+#define MTX_RESPFRM_RATE_DF_FF_SFT 0
+#define MTX_RESPFRM_RATE_DF_FF_HI 15
+#define MTX_RESPFRM_RATE_DF_FF_SZ 16
+#define MTX_RESPFRM_INFO_EXCEPTION_MSK 0x001fffff
+#define MTX_RESPFRM_INFO_EXCEPTION_I_MSK 0xffe00000
+#define MTX_RESPFRM_INFO_EXCEPTION_SFT 0
+#define MTX_RESPFRM_INFO_EXCEPTION_HI 20
+#define MTX_RESPFRM_INFO_EXCEPTION_SZ 21
+#define MTX_RESPFRM_INFO_00_MSK 0x001fffff
+#define MTX_RESPFRM_INFO_00_I_MSK 0xffe00000
+#define MTX_RESPFRM_INFO_00_SFT 0
+#define MTX_RESPFRM_INFO_00_HI 20
+#define MTX_RESPFRM_INFO_00_SZ 21
+#define MTX_RESPFRM_INFO_01_MSK 0x001fffff
+#define MTX_RESPFRM_INFO_01_I_MSK 0xffe00000
+#define MTX_RESPFRM_INFO_01_SFT 0
+#define MTX_RESPFRM_INFO_01_HI 20
+#define MTX_RESPFRM_INFO_01_SZ 21
+#define MTX_RESPFRM_INFO_02_MSK 0x001fffff
+#define MTX_RESPFRM_INFO_02_I_MSK 0xffe00000
+#define MTX_RESPFRM_INFO_02_SFT 0
+#define MTX_RESPFRM_INFO_02_HI 20
+#define MTX_RESPFRM_INFO_02_SZ 21
+#define MTX_RESPFRM_INFO_03_MSK 0x001fffff
+#define MTX_RESPFRM_INFO_03_I_MSK 0xffe00000
+#define MTX_RESPFRM_INFO_03_SFT 0
+#define MTX_RESPFRM_INFO_03_HI 20
+#define MTX_RESPFRM_INFO_03_SZ 21
+#define MTX_RESPFRM_INFO_11_MSK 0x001fffff
+#define MTX_RESPFRM_INFO_11_I_MSK 0xffe00000
+#define MTX_RESPFRM_INFO_11_SFT 0
+#define MTX_RESPFRM_INFO_11_HI 20
+#define MTX_RESPFRM_INFO_11_SZ 21
+#define MTX_RESPFRM_INFO_12_MSK 0x001fffff
+#define MTX_RESPFRM_INFO_12_I_MSK 0xffe00000
+#define MTX_RESPFRM_INFO_12_SFT 0
+#define MTX_RESPFRM_INFO_12_HI 20
+#define MTX_RESPFRM_INFO_12_SZ 21
+#define MTX_RESPFRM_INFO_13_MSK 0x001fffff
+#define MTX_RESPFRM_INFO_13_I_MSK 0xffe00000
+#define MTX_RESPFRM_INFO_13_SFT 0
+#define MTX_RESPFRM_INFO_13_HI 20
+#define MTX_RESPFRM_INFO_13_SZ 21
+#define MTX_RESPFRM_INFO_90_B0_MSK 0x001fffff
+#define MTX_RESPFRM_INFO_90_B0_I_MSK 0xffe00000
+#define MTX_RESPFRM_INFO_90_B0_SFT 0
+#define MTX_RESPFRM_INFO_90_B0_HI 20
+#define MTX_RESPFRM_INFO_90_B0_SZ 21
+#define MTX_RESPFRM_INFO_91_B1_MSK 0x001fffff
+#define MTX_RESPFRM_INFO_91_B1_I_MSK 0xffe00000
+#define MTX_RESPFRM_INFO_91_B1_SFT 0
+#define MTX_RESPFRM_INFO_91_B1_HI 20
+#define MTX_RESPFRM_INFO_91_B1_SZ 21
+#define MTX_RESPFRM_INFO_92_B2_MSK 0x001fffff
+#define MTX_RESPFRM_INFO_92_B2_I_MSK 0xffe00000
+#define MTX_RESPFRM_INFO_92_B2_SFT 0
+#define MTX_RESPFRM_INFO_92_B2_HI 20
+#define MTX_RESPFRM_INFO_92_B2_SZ 21
+#define MTX_RESPFRM_INFO_93_B3_MSK 0x001fffff
+#define MTX_RESPFRM_INFO_93_B3_I_MSK 0xffe00000
+#define MTX_RESPFRM_INFO_93_B3_SFT 0
+#define MTX_RESPFRM_INFO_93_B3_HI 20
+#define MTX_RESPFRM_INFO_93_B3_SZ 21
+#define MTX_RESPFRM_INFO_94_B4_MSK 0x001fffff
+#define MTX_RESPFRM_INFO_94_B4_I_MSK 0xffe00000
+#define MTX_RESPFRM_INFO_94_B4_SFT 0
+#define MTX_RESPFRM_INFO_94_B4_HI 20
+#define MTX_RESPFRM_INFO_94_B4_SZ 21
+#define MTX_RESPFRM_INFO_95_B5_MSK 0x001fffff
+#define MTX_RESPFRM_INFO_95_B5_I_MSK 0xffe00000
+#define MTX_RESPFRM_INFO_95_B5_SFT 0
+#define MTX_RESPFRM_INFO_95_B5_HI 20
+#define MTX_RESPFRM_INFO_95_B5_SZ 21
+#define MTX_RESPFRM_INFO_96_B6_MSK 0x001fffff
+#define MTX_RESPFRM_INFO_96_B6_I_MSK 0xffe00000
+#define MTX_RESPFRM_INFO_96_B6_SFT 0
+#define MTX_RESPFRM_INFO_96_B6_HI 20
+#define MTX_RESPFRM_INFO_96_B6_SZ 21
+#define MTX_RESPFRM_INFO_97_B7_MSK 0x001fffff
+#define MTX_RESPFRM_INFO_97_B7_I_MSK 0xffe00000
+#define MTX_RESPFRM_INFO_97_B7_SFT 0
+#define MTX_RESPFRM_INFO_97_B7_HI 20
+#define MTX_RESPFRM_INFO_97_B7_SZ 21
+#define MTX_RESPFRM_INFO_C0_MSK 0x001fffff
+#define MTX_RESPFRM_INFO_C0_I_MSK 0xffe00000
+#define MTX_RESPFRM_INFO_C0_SFT 0
+#define MTX_RESPFRM_INFO_C0_HI 20
+#define MTX_RESPFRM_INFO_C0_SZ 21
+#define MTX_RESPFRM_INFO_C1_MSK 0x001fffff
+#define MTX_RESPFRM_INFO_C1_I_MSK 0xffe00000
+#define MTX_RESPFRM_INFO_C1_SFT 0
+#define MTX_RESPFRM_INFO_C1_HI 20
+#define MTX_RESPFRM_INFO_C1_SZ 21
+#define MTX_RESPFRM_INFO_C2_MSK 0x001fffff
+#define MTX_RESPFRM_INFO_C2_I_MSK 0xffe00000
+#define MTX_RESPFRM_INFO_C2_SFT 0
+#define MTX_RESPFRM_INFO_C2_HI 20
+#define MTX_RESPFRM_INFO_C2_SZ 21
+#define MTX_RESPFRM_INFO_C3_MSK 0x001fffff
+#define MTX_RESPFRM_INFO_C3_I_MSK 0xffe00000
+#define MTX_RESPFRM_INFO_C3_SFT 0
+#define MTX_RESPFRM_INFO_C3_HI 20
+#define MTX_RESPFRM_INFO_C3_SZ 21
+#define MTX_RESPFRM_INFO_C4_MSK 0x001fffff
+#define MTX_RESPFRM_INFO_C4_I_MSK 0xffe00000
+#define MTX_RESPFRM_INFO_C4_SFT 0
+#define MTX_RESPFRM_INFO_C4_HI 20
+#define MTX_RESPFRM_INFO_C4_SZ 21
+#define MTX_RESPFRM_INFO_C5_MSK 0x001fffff
+#define MTX_RESPFRM_INFO_C5_I_MSK 0xffe00000
+#define MTX_RESPFRM_INFO_C5_SFT 0
+#define MTX_RESPFRM_INFO_C5_HI 20
+#define MTX_RESPFRM_INFO_C5_SZ 21
+#define MTX_RESPFRM_INFO_C6_MSK 0x001fffff
+#define MTX_RESPFRM_INFO_C6_I_MSK 0xffe00000
+#define MTX_RESPFRM_INFO_C6_SFT 0
+#define MTX_RESPFRM_INFO_C6_HI 20
+#define MTX_RESPFRM_INFO_C6_SZ 21
+#define MTX_RESPFRM_INFO_C7_MSK 0x001fffff
+#define MTX_RESPFRM_INFO_C7_I_MSK 0xffe00000
+#define MTX_RESPFRM_INFO_C7_SFT 0
+#define MTX_RESPFRM_INFO_C7_HI 20
+#define MTX_RESPFRM_INFO_C7_SZ 21
+#define MTX_RESPFRM_INFO_D0_MSK 0x001fffff
+#define MTX_RESPFRM_INFO_D0_I_MSK 0xffe00000
+#define MTX_RESPFRM_INFO_D0_SFT 0
+#define MTX_RESPFRM_INFO_D0_HI 20
+#define MTX_RESPFRM_INFO_D0_SZ 21
+#define MTX_RESPFRM_INFO_D1_MSK 0x001fffff
+#define MTX_RESPFRM_INFO_D1_I_MSK 0xffe00000
+#define MTX_RESPFRM_INFO_D1_SFT 0
+#define MTX_RESPFRM_INFO_D1_HI 20
+#define MTX_RESPFRM_INFO_D1_SZ 21
+#define MTX_RESPFRM_INFO_D2_MSK 0x001fffff
+#define MTX_RESPFRM_INFO_D2_I_MSK 0xffe00000
+#define MTX_RESPFRM_INFO_D2_SFT 0
+#define MTX_RESPFRM_INFO_D2_HI 20
+#define MTX_RESPFRM_INFO_D2_SZ 21
+#define MTX_RESPFRM_INFO_D3_MSK 0x001fffff
+#define MTX_RESPFRM_INFO_D3_I_MSK 0xffe00000
+#define MTX_RESPFRM_INFO_D3_SFT 0
+#define MTX_RESPFRM_INFO_D3_HI 20
+#define MTX_RESPFRM_INFO_D3_SZ 21
+#define MTX_RESPFRM_INFO_D4_MSK 0x001fffff
+#define MTX_RESPFRM_INFO_D4_I_MSK 0xffe00000
+#define MTX_RESPFRM_INFO_D4_SFT 0
+#define MTX_RESPFRM_INFO_D4_HI 20
+#define MTX_RESPFRM_INFO_D4_SZ 21
+#define MTX_RESPFRM_INFO_D5_MSK 0x001fffff
+#define MTX_RESPFRM_INFO_D5_I_MSK 0xffe00000
+#define MTX_RESPFRM_INFO_D5_SFT 0
+#define MTX_RESPFRM_INFO_D5_HI 20
+#define MTX_RESPFRM_INFO_D5_SZ 21
+#define MTX_RESPFRM_INFO_D6_MSK 0x001fffff
+#define MTX_RESPFRM_INFO_D6_I_MSK 0xffe00000
+#define MTX_RESPFRM_INFO_D6_SFT 0
+#define MTX_RESPFRM_INFO_D6_HI 20
+#define MTX_RESPFRM_INFO_D6_SZ 21
+#define MTX_RESPFRM_INFO_D7_MSK 0x001fffff
+#define MTX_RESPFRM_INFO_D7_I_MSK 0xffe00000
+#define MTX_RESPFRM_INFO_D7_SFT 0
+#define MTX_RESPFRM_INFO_D7_HI 20
+#define MTX_RESPFRM_INFO_D7_SZ 21
+#define MTX_RESPFRM_INFO_D8_MSK 0x001fffff
+#define MTX_RESPFRM_INFO_D8_I_MSK 0xffe00000
+#define MTX_RESPFRM_INFO_D8_SFT 0
+#define MTX_RESPFRM_INFO_D8_HI 20
+#define MTX_RESPFRM_INFO_D8_SZ 21
+#define MTX_RESPFRM_INFO_D9_MSK 0x001fffff
+#define MTX_RESPFRM_INFO_D9_I_MSK 0xffe00000
+#define MTX_RESPFRM_INFO_D9_SFT 0
+#define MTX_RESPFRM_INFO_D9_HI 20
+#define MTX_RESPFRM_INFO_D9_SZ 21
+#define MTX_RESPFRM_INFO_DA_MSK 0x001fffff
+#define MTX_RESPFRM_INFO_DA_I_MSK 0xffe00000
+#define MTX_RESPFRM_INFO_DA_SFT 0
+#define MTX_RESPFRM_INFO_DA_HI 20
+#define MTX_RESPFRM_INFO_DA_SZ 21
+#define MTX_RESPFRM_INFO_DB_MSK 0x001fffff
+#define MTX_RESPFRM_INFO_DB_I_MSK 0xffe00000
+#define MTX_RESPFRM_INFO_DB_SFT 0
+#define MTX_RESPFRM_INFO_DB_HI 20
+#define MTX_RESPFRM_INFO_DB_SZ 21
+#define MTX_RESPFRM_INFO_DC_MSK 0x001fffff
+#define MTX_RESPFRM_INFO_DC_I_MSK 0xffe00000
+#define MTX_RESPFRM_INFO_DC_SFT 0
+#define MTX_RESPFRM_INFO_DC_HI 20
+#define MTX_RESPFRM_INFO_DC_SZ 21
+#define MTX_RESPFRM_INFO_DD_MSK 0x001fffff
+#define MTX_RESPFRM_INFO_DD_I_MSK 0xffe00000
+#define MTX_RESPFRM_INFO_DD_SFT 0
+#define MTX_RESPFRM_INFO_DD_HI 20
+#define MTX_RESPFRM_INFO_DD_SZ 21
+#define MTX_RESPFRM_INFO_DE_MSK 0x001fffff
+#define MTX_RESPFRM_INFO_DE_I_MSK 0xffe00000
+#define MTX_RESPFRM_INFO_DE_SFT 0
+#define MTX_RESPFRM_INFO_DE_HI 20
+#define MTX_RESPFRM_INFO_DE_SZ 21
+#define MTX_RESPFRM_INFO_DF_MSK 0x001fffff
+#define MTX_RESPFRM_INFO_DF_I_MSK 0xffe00000
+#define MTX_RESPFRM_INFO_DF_SFT 0
+#define MTX_RESPFRM_INFO_DF_HI 20
+#define MTX_RESPFRM_INFO_DF_SZ 21
+#define VALID0_MSK 0x00000001
+#define VALID0_I_MSK 0xfffffffe
+#define VALID0_SFT 0
+#define VALID0_HI 0
+#define VALID0_SZ 1
+#define PEER_QOS_EN0_MSK 0x00000002
+#define PEER_QOS_EN0_I_MSK 0xfffffffd
+#define PEER_QOS_EN0_SFT 1
+#define PEER_QOS_EN0_HI 1
+#define PEER_QOS_EN0_SZ 1
+#define PEER_OP_MODE0_MSK 0x0000000c
+#define PEER_OP_MODE0_I_MSK 0xfffffff3
+#define PEER_OP_MODE0_SFT 2
+#define PEER_OP_MODE0_HI 3
+#define PEER_OP_MODE0_SZ 2
+#define PEER_HT_MODE0_MSK 0x00000030
+#define PEER_HT_MODE0_I_MSK 0xffffffcf
+#define PEER_HT_MODE0_SFT 4
+#define PEER_HT_MODE0_HI 5
+#define PEER_HT_MODE0_SZ 2
+#define PEER_MAC0_31_0_MSK 0xffffffff
+#define PEER_MAC0_31_0_I_MSK 0x00000000
+#define PEER_MAC0_31_0_SFT 0
+#define PEER_MAC0_31_0_HI 31
+#define PEER_MAC0_31_0_SZ 32
+#define PEER_MAC0_47_32_MSK 0x0000ffff
+#define PEER_MAC0_47_32_I_MSK 0xffff0000
+#define PEER_MAC0_47_32_SFT 0
+#define PEER_MAC0_47_32_HI 15
+#define PEER_MAC0_47_32_SZ 16
+#define TX_ACK_POLICY_0_0_MSK 0x00000003
+#define TX_ACK_POLICY_0_0_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_0_SFT 0
+#define TX_ACK_POLICY_0_0_HI 1
+#define TX_ACK_POLICY_0_0_SZ 2
+#define TX_SEQ_CTRL_0_0_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_0_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_0_SFT 0
+#define TX_SEQ_CTRL_0_0_HI 11
+#define TX_SEQ_CTRL_0_0_SZ 12
+#define TX_ACK_POLICY_0_1_MSK 0x00000003
+#define TX_ACK_POLICY_0_1_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_1_SFT 0
+#define TX_ACK_POLICY_0_1_HI 1
+#define TX_ACK_POLICY_0_1_SZ 2
+#define TX_SEQ_CTRL_0_1_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_1_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_1_SFT 0
+#define TX_SEQ_CTRL_0_1_HI 11
+#define TX_SEQ_CTRL_0_1_SZ 12
+#define TX_ACK_POLICY_0_2_MSK 0x00000003
+#define TX_ACK_POLICY_0_2_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_2_SFT 0
+#define TX_ACK_POLICY_0_2_HI 1
+#define TX_ACK_POLICY_0_2_SZ 2
+#define TX_SEQ_CTRL_0_2_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_2_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_2_SFT 0
+#define TX_SEQ_CTRL_0_2_HI 11
+#define TX_SEQ_CTRL_0_2_SZ 12
+#define TX_ACK_POLICY_0_3_MSK 0x00000003
+#define TX_ACK_POLICY_0_3_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_3_SFT 0
+#define TX_ACK_POLICY_0_3_HI 1
+#define TX_ACK_POLICY_0_3_SZ 2
+#define TX_SEQ_CTRL_0_3_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_3_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_3_SFT 0
+#define TX_SEQ_CTRL_0_3_HI 11
+#define TX_SEQ_CTRL_0_3_SZ 12
+#define TX_ACK_POLICY_0_4_MSK 0x00000003
+#define TX_ACK_POLICY_0_4_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_4_SFT 0
+#define TX_ACK_POLICY_0_4_HI 1
+#define TX_ACK_POLICY_0_4_SZ 2
+#define TX_SEQ_CTRL_0_4_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_4_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_4_SFT 0
+#define TX_SEQ_CTRL_0_4_HI 11
+#define TX_SEQ_CTRL_0_4_SZ 12
+#define TX_ACK_POLICY_0_5_MSK 0x00000003
+#define TX_ACK_POLICY_0_5_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_5_SFT 0
+#define TX_ACK_POLICY_0_5_HI 1
+#define TX_ACK_POLICY_0_5_SZ 2
+#define TX_SEQ_CTRL_0_5_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_5_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_5_SFT 0
+#define TX_SEQ_CTRL_0_5_HI 11
+#define TX_SEQ_CTRL_0_5_SZ 12
+#define TX_ACK_POLICY_0_6_MSK 0x00000003
+#define TX_ACK_POLICY_0_6_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_6_SFT 0
+#define TX_ACK_POLICY_0_6_HI 1
+#define TX_ACK_POLICY_0_6_SZ 2
+#define TX_SEQ_CTRL_0_6_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_6_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_6_SFT 0
+#define TX_SEQ_CTRL_0_6_HI 11
+#define TX_SEQ_CTRL_0_6_SZ 12
+#define TX_ACK_POLICY_0_7_MSK 0x00000003
+#define TX_ACK_POLICY_0_7_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_7_SFT 0
+#define TX_ACK_POLICY_0_7_HI 1
+#define TX_ACK_POLICY_0_7_SZ 2
+#define TX_SEQ_CTRL_0_7_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_7_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_7_SFT 0
+#define TX_SEQ_CTRL_0_7_HI 11
+#define TX_SEQ_CTRL_0_7_SZ 12
+#define VALID1_MSK 0x00000001
+#define VALID1_I_MSK 0xfffffffe
+#define VALID1_SFT 0
+#define VALID1_HI 0
+#define VALID1_SZ 1
+#define PEER_QOS_EN1_MSK 0x00000002
+#define PEER_QOS_EN1_I_MSK 0xfffffffd
+#define PEER_QOS_EN1_SFT 1
+#define PEER_QOS_EN1_HI 1
+#define PEER_QOS_EN1_SZ 1
+#define PEER_OP_MODE1_MSK 0x0000000c
+#define PEER_OP_MODE1_I_MSK 0xfffffff3
+#define PEER_OP_MODE1_SFT 2
+#define PEER_OP_MODE1_HI 3
+#define PEER_OP_MODE1_SZ 2
+#define PEER_HT_MODE1_MSK 0x00000030
+#define PEER_HT_MODE1_I_MSK 0xffffffcf
+#define PEER_HT_MODE1_SFT 4
+#define PEER_HT_MODE1_HI 5
+#define PEER_HT_MODE1_SZ 2
+#define PEER_MAC1_31_0_MSK 0xffffffff
+#define PEER_MAC1_31_0_I_MSK 0x00000000
+#define PEER_MAC1_31_0_SFT 0
+#define PEER_MAC1_31_0_HI 31
+#define PEER_MAC1_31_0_SZ 32
+#define PEER_MAC1_47_32_MSK 0x0000ffff
+#define PEER_MAC1_47_32_I_MSK 0xffff0000
+#define PEER_MAC1_47_32_SFT 0
+#define PEER_MAC1_47_32_HI 15
+#define PEER_MAC1_47_32_SZ 16
+#define TX_ACK_POLICY_1_0_MSK 0x00000003
+#define TX_ACK_POLICY_1_0_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_0_SFT 0
+#define TX_ACK_POLICY_1_0_HI 1
+#define TX_ACK_POLICY_1_0_SZ 2
+#define TX_SEQ_CTRL_1_0_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_0_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_0_SFT 0
+#define TX_SEQ_CTRL_1_0_HI 11
+#define TX_SEQ_CTRL_1_0_SZ 12
+#define TX_ACK_POLICY_1_1_MSK 0x00000003
+#define TX_ACK_POLICY_1_1_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_1_SFT 0
+#define TX_ACK_POLICY_1_1_HI 1
+#define TX_ACK_POLICY_1_1_SZ 2
+#define TX_SEQ_CTRL_1_1_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_1_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_1_SFT 0
+#define TX_SEQ_CTRL_1_1_HI 11
+#define TX_SEQ_CTRL_1_1_SZ 12
+#define TX_ACK_POLICY_1_2_MSK 0x00000003
+#define TX_ACK_POLICY_1_2_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_2_SFT 0
+#define TX_ACK_POLICY_1_2_HI 1
+#define TX_ACK_POLICY_1_2_SZ 2
+#define TX_SEQ_CTRL_1_2_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_2_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_2_SFT 0
+#define TX_SEQ_CTRL_1_2_HI 11
+#define TX_SEQ_CTRL_1_2_SZ 12
+#define TX_ACK_POLICY_1_3_MSK 0x00000003
+#define TX_ACK_POLICY_1_3_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_3_SFT 0
+#define TX_ACK_POLICY_1_3_HI 1
+#define TX_ACK_POLICY_1_3_SZ 2
+#define TX_SEQ_CTRL_1_3_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_3_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_3_SFT 0
+#define TX_SEQ_CTRL_1_3_HI 11
+#define TX_SEQ_CTRL_1_3_SZ 12
+#define TX_ACK_POLICY_1_4_MSK 0x00000003
+#define TX_ACK_POLICY_1_4_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_4_SFT 0
+#define TX_ACK_POLICY_1_4_HI 1
+#define TX_ACK_POLICY_1_4_SZ 2
+#define TX_SEQ_CTRL_1_4_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_4_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_4_SFT 0
+#define TX_SEQ_CTRL_1_4_HI 11
+#define TX_SEQ_CTRL_1_4_SZ 12
+#define TX_ACK_POLICY_1_5_MSK 0x00000003
+#define TX_ACK_POLICY_1_5_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_5_SFT 0
+#define TX_ACK_POLICY_1_5_HI 1
+#define TX_ACK_POLICY_1_5_SZ 2
+#define TX_SEQ_CTRL_1_5_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_5_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_5_SFT 0
+#define TX_SEQ_CTRL_1_5_HI 11
+#define TX_SEQ_CTRL_1_5_SZ 12
+#define TX_ACK_POLICY_1_6_MSK 0x00000003
+#define TX_ACK_POLICY_1_6_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_6_SFT 0
+#define TX_ACK_POLICY_1_6_HI 1
+#define TX_ACK_POLICY_1_6_SZ 2
+#define TX_SEQ_CTRL_1_6_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_6_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_6_SFT 0
+#define TX_SEQ_CTRL_1_6_HI 11
+#define TX_SEQ_CTRL_1_6_SZ 12
+#define TX_ACK_POLICY_1_7_MSK 0x00000003
+#define TX_ACK_POLICY_1_7_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_7_SFT 0
+#define TX_ACK_POLICY_1_7_HI 1
+#define TX_ACK_POLICY_1_7_SZ 2
+#define TX_SEQ_CTRL_1_7_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_7_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_7_SFT 0
+#define TX_SEQ_CTRL_1_7_HI 11
+#define TX_SEQ_CTRL_1_7_SZ 12
+#define CH1_PRI_MSK 0x00000003
+#define CH1_PRI_I_MSK 0xfffffffc
+#define CH1_PRI_SFT 0
+#define CH1_PRI_HI 1
+#define CH1_PRI_SZ 2
+#define CH2_PRI_MSK 0x00000300
+#define CH2_PRI_I_MSK 0xfffffcff
+#define CH2_PRI_SFT 8
+#define CH2_PRI_HI 9
+#define CH2_PRI_SZ 2
+#define CH3_PRI_MSK 0x00030000
+#define CH3_PRI_I_MSK 0xfffcffff
+#define CH3_PRI_SFT 16
+#define CH3_PRI_HI 17
+#define CH3_PRI_SZ 2
+#define RG_MAC_LPBK_MSK 0x00000001
+#define RG_MAC_LPBK_I_MSK 0xfffffffe
+#define RG_MAC_LPBK_SFT 0
+#define RG_MAC_LPBK_HI 0
+#define RG_MAC_LPBK_SZ 1
+#define RG_MAC_M2M_MSK 0x00000002
+#define RG_MAC_M2M_I_MSK 0xfffffffd
+#define RG_MAC_M2M_SFT 1
+#define RG_MAC_M2M_HI 1
+#define RG_MAC_M2M_SZ 1
+#define RG_PHY_LPBK_MSK 0x00000004
+#define RG_PHY_LPBK_I_MSK 0xfffffffb
+#define RG_PHY_LPBK_SFT 2
+#define RG_PHY_LPBK_HI 2
+#define RG_PHY_LPBK_SZ 1
+#define RG_LPBK_RX_EN_MSK 0x00000008
+#define RG_LPBK_RX_EN_I_MSK 0xfffffff7
+#define RG_LPBK_RX_EN_SFT 3
+#define RG_LPBK_RX_EN_HI 3
+#define RG_LPBK_RX_EN_SZ 1
+#define EXT_MAC_MODE_MSK 0x00000010
+#define EXT_MAC_MODE_I_MSK 0xffffffef
+#define EXT_MAC_MODE_SFT 4
+#define EXT_MAC_MODE_HI 4
+#define EXT_MAC_MODE_SZ 1
+#define EXT_PHY_MODE_MSK 0x00000020
+#define EXT_PHY_MODE_I_MSK 0xffffffdf
+#define EXT_PHY_MODE_SFT 5
+#define EXT_PHY_MODE_HI 5
+#define EXT_PHY_MODE_SZ 1
+#define HCI_SW_RST_MSK 0x00000001
+#define HCI_SW_RST_I_MSK 0xfffffffe
+#define HCI_SW_RST_SFT 0
+#define HCI_SW_RST_HI 0
+#define HCI_SW_RST_SZ 1
+#define CO_PROC_SW_RST_MSK 0x00000002
+#define CO_PROC_SW_RST_I_MSK 0xfffffffd
+#define CO_PROC_SW_RST_SFT 1
+#define CO_PROC_SW_RST_HI 1
+#define CO_PROC_SW_RST_SZ 1
+#define MTX_SW_RST_MSK 0x00000004
+#define MTX_SW_RST_I_MSK 0xfffffffb
+#define MTX_SW_RST_SFT 2
+#define MTX_SW_RST_HI 2
+#define MTX_SW_RST_SZ 1
+#define MTX_MISC_SW_RST_MSK 0x00000008
+#define MTX_MISC_SW_RST_I_MSK 0xfffffff7
+#define MTX_MISC_SW_RST_SFT 3
+#define MTX_MISC_SW_RST_HI 3
+#define MTX_MISC_SW_RST_SZ 1
+#define MTX_QUE_SW_RST_MSK 0x00000010
+#define MTX_QUE_SW_RST_I_MSK 0xffffffef
+#define MTX_QUE_SW_RST_SFT 4
+#define MTX_QUE_SW_RST_HI 4
+#define MTX_QUE_SW_RST_SZ 1
+#define MTX_CHST_SW_RST_MSK 0x00000020
+#define MTX_CHST_SW_RST_I_MSK 0xffffffdf
+#define MTX_CHST_SW_RST_SFT 5
+#define MTX_CHST_SW_RST_HI 5
+#define MTX_CHST_SW_RST_SZ 1
+#define MTX_BCN_SW_RST_MSK 0x00000040
+#define MTX_BCN_SW_RST_I_MSK 0xffffffbf
+#define MTX_BCN_SW_RST_SFT 6
+#define MTX_BCN_SW_RST_HI 6
+#define MTX_BCN_SW_RST_SZ 1
+#define MRX_SW_RST_MSK 0x00000080
+#define MRX_SW_RST_I_MSK 0xffffff7f
+#define MRX_SW_RST_SFT 7
+#define MRX_SW_RST_HI 7
+#define MRX_SW_RST_SZ 1
+#define AMPDU_SW_RST_MSK 0x00000100
+#define AMPDU_SW_RST_I_MSK 0xfffffeff
+#define AMPDU_SW_RST_SFT 8
+#define AMPDU_SW_RST_HI 8
+#define AMPDU_SW_RST_SZ 1
+#define MMU_SW_RST_MSK 0x00000200
+#define MMU_SW_RST_I_MSK 0xfffffdff
+#define MMU_SW_RST_SFT 9
+#define MMU_SW_RST_HI 9
+#define MMU_SW_RST_SZ 1
+#define ID_MNG_SW_RST_MSK 0x00000800
+#define ID_MNG_SW_RST_I_MSK 0xfffff7ff
+#define ID_MNG_SW_RST_SFT 11
+#define ID_MNG_SW_RST_HI 11
+#define ID_MNG_SW_RST_SZ 1
+#define MBOX_SW_RST_MSK 0x00001000
+#define MBOX_SW_RST_I_MSK 0xffffefff
+#define MBOX_SW_RST_SFT 12
+#define MBOX_SW_RST_HI 12
+#define MBOX_SW_RST_SZ 1
+#define SCRT_SW_RST_MSK 0x00002000
+#define SCRT_SW_RST_I_MSK 0xffffdfff
+#define SCRT_SW_RST_SFT 13
+#define SCRT_SW_RST_HI 13
+#define SCRT_SW_RST_SZ 1
+#define MIC_SW_RST_MSK 0x00004000
+#define MIC_SW_RST_I_MSK 0xffffbfff
+#define MIC_SW_RST_SFT 14
+#define MIC_SW_RST_HI 14
+#define MIC_SW_RST_SZ 1
+#define CO_PROC_ENG_RST_MSK 0x00000002
+#define CO_PROC_ENG_RST_I_MSK 0xfffffffd
+#define CO_PROC_ENG_RST_SFT 1
+#define CO_PROC_ENG_RST_HI 1
+#define CO_PROC_ENG_RST_SZ 1
+#define MTX_MISC_ENG_RST_MSK 0x00000008
+#define MTX_MISC_ENG_RST_I_MSK 0xfffffff7
+#define MTX_MISC_ENG_RST_SFT 3
+#define MTX_MISC_ENG_RST_HI 3
+#define MTX_MISC_ENG_RST_SZ 1
+#define MTX_QUE_ENG_RST_MSK 0x00000010
+#define MTX_QUE_ENG_RST_I_MSK 0xffffffef
+#define MTX_QUE_ENG_RST_SFT 4
+#define MTX_QUE_ENG_RST_HI 4
+#define MTX_QUE_ENG_RST_SZ 1
+#define MTX_CHST_ENG_RST_MSK 0x00000020
+#define MTX_CHST_ENG_RST_I_MSK 0xffffffdf
+#define MTX_CHST_ENG_RST_SFT 5
+#define MTX_CHST_ENG_RST_HI 5
+#define MTX_CHST_ENG_RST_SZ 1
+#define MTX_BCN_ENG_RST_MSK 0x00000040
+#define MTX_BCN_ENG_RST_I_MSK 0xffffffbf
+#define MTX_BCN_ENG_RST_SFT 6
+#define MTX_BCN_ENG_RST_HI 6
+#define MTX_BCN_ENG_RST_SZ 1
+#define MRX_ENG_RST_MSK 0x00000080
+#define MRX_ENG_RST_I_MSK 0xffffff7f
+#define MRX_ENG_RST_SFT 7
+#define MRX_ENG_RST_HI 7
+#define MRX_ENG_RST_SZ 1
+#define AMPDU_ENG_RST_MSK 0x00000100
+#define AMPDU_ENG_RST_I_MSK 0xfffffeff
+#define AMPDU_ENG_RST_SFT 8
+#define AMPDU_ENG_RST_HI 8
+#define AMPDU_ENG_RST_SZ 1
+#define ID_MNG_ENG_RST_MSK 0x00004000
+#define ID_MNG_ENG_RST_I_MSK 0xffffbfff
+#define ID_MNG_ENG_RST_SFT 14
+#define ID_MNG_ENG_RST_HI 14
+#define ID_MNG_ENG_RST_SZ 1
+#define MBOX_ENG_RST_MSK 0x00008000
+#define MBOX_ENG_RST_I_MSK 0xffff7fff
+#define MBOX_ENG_RST_SFT 15
+#define MBOX_ENG_RST_HI 15
+#define MBOX_ENG_RST_SZ 1
+#define SCRT_ENG_RST_MSK 0x00010000
+#define SCRT_ENG_RST_I_MSK 0xfffeffff
+#define SCRT_ENG_RST_SFT 16
+#define SCRT_ENG_RST_HI 16
+#define SCRT_ENG_RST_SZ 1
+#define MIC_ENG_RST_MSK 0x00020000
+#define MIC_ENG_RST_I_MSK 0xfffdffff
+#define MIC_ENG_RST_SFT 17
+#define MIC_ENG_RST_HI 17
+#define MIC_ENG_RST_SZ 1
+#define CO_PROC_CSR_RST_MSK 0x00000002
+#define CO_PROC_CSR_RST_I_MSK 0xfffffffd
+#define CO_PROC_CSR_RST_SFT 1
+#define CO_PROC_CSR_RST_HI 1
+#define CO_PROC_CSR_RST_SZ 1
+#define MTX_MISC_CSR_RST_MSK 0x00000008
+#define MTX_MISC_CSR_RST_I_MSK 0xfffffff7
+#define MTX_MISC_CSR_RST_SFT 3
+#define MTX_MISC_CSR_RST_HI 3
+#define MTX_MISC_CSR_RST_SZ 1
+#define MTX_QUE0_CSR_RST_MSK 0x00000010
+#define MTX_QUE0_CSR_RST_I_MSK 0xffffffef
+#define MTX_QUE0_CSR_RST_SFT 4
+#define MTX_QUE0_CSR_RST_HI 4
+#define MTX_QUE0_CSR_RST_SZ 1
+#define MTX_QUE1_CSR_RST_MSK 0x00000020
+#define MTX_QUE1_CSR_RST_I_MSK 0xffffffdf
+#define MTX_QUE1_CSR_RST_SFT 5
+#define MTX_QUE1_CSR_RST_HI 5
+#define MTX_QUE1_CSR_RST_SZ 1
+#define MTX_QUE2_CSR_RST_MSK 0x00000040
+#define MTX_QUE2_CSR_RST_I_MSK 0xffffffbf
+#define MTX_QUE2_CSR_RST_SFT 6
+#define MTX_QUE2_CSR_RST_HI 6
+#define MTX_QUE2_CSR_RST_SZ 1
+#define MTX_QUE3_CSR_RST_MSK 0x00000080
+#define MTX_QUE3_CSR_RST_I_MSK 0xffffff7f
+#define MTX_QUE3_CSR_RST_SFT 7
+#define MTX_QUE3_CSR_RST_HI 7
+#define MTX_QUE3_CSR_RST_SZ 1
+#define MTX_QUE4_CSR_RST_MSK 0x00000100
+#define MTX_QUE4_CSR_RST_I_MSK 0xfffffeff
+#define MTX_QUE4_CSR_RST_SFT 8
+#define MTX_QUE4_CSR_RST_HI 8
+#define MTX_QUE4_CSR_RST_SZ 1
+#define MTX_QUE5_CSR_RST_MSK 0x00000200
+#define MTX_QUE5_CSR_RST_I_MSK 0xfffffdff
+#define MTX_QUE5_CSR_RST_SFT 9
+#define MTX_QUE5_CSR_RST_HI 9
+#define MTX_QUE5_CSR_RST_SZ 1
+#define MRX_CSR_RST_MSK 0x00000400
+#define MRX_CSR_RST_I_MSK 0xfffffbff
+#define MRX_CSR_RST_SFT 10
+#define MRX_CSR_RST_HI 10
+#define MRX_CSR_RST_SZ 1
+#define AMPDU_CSR_RST_MSK 0x00000800
+#define AMPDU_CSR_RST_I_MSK 0xfffff7ff
+#define AMPDU_CSR_RST_SFT 11
+#define AMPDU_CSR_RST_HI 11
+#define AMPDU_CSR_RST_SZ 1
+#define SCRT_CSR_RST_MSK 0x00002000
+#define SCRT_CSR_RST_I_MSK 0xffffdfff
+#define SCRT_CSR_RST_SFT 13
+#define SCRT_CSR_RST_HI 13
+#define SCRT_CSR_RST_SZ 1
+#define ID_MNG_CSR_RST_MSK 0x00004000
+#define ID_MNG_CSR_RST_I_MSK 0xffffbfff
+#define ID_MNG_CSR_RST_SFT 14
+#define ID_MNG_CSR_RST_HI 14
+#define ID_MNG_CSR_RST_SZ 1
+#define MBOX_CSR_RST_MSK 0x00008000
+#define MBOX_CSR_RST_I_MSK 0xffff7fff
+#define MBOX_CSR_RST_SFT 15
+#define MBOX_CSR_RST_HI 15
+#define MBOX_CSR_RST_SZ 1
+#define HCI_CLK_EN_MSK 0x00000001
+#define HCI_CLK_EN_I_MSK 0xfffffffe
+#define HCI_CLK_EN_SFT 0
+#define HCI_CLK_EN_HI 0
+#define HCI_CLK_EN_SZ 1
+#define CO_PROC_CLK_EN_MSK 0x00000002
+#define CO_PROC_CLK_EN_I_MSK 0xfffffffd
+#define CO_PROC_CLK_EN_SFT 1
+#define CO_PROC_CLK_EN_HI 1
+#define CO_PROC_CLK_EN_SZ 1
+#define MTX_MISC_CLK_EN_MSK 0x00000008
+#define MTX_MISC_CLK_EN_I_MSK 0xfffffff7
+#define MTX_MISC_CLK_EN_SFT 3
+#define MTX_MISC_CLK_EN_HI 3
+#define MTX_MISC_CLK_EN_SZ 1
+#define MTX_QUE_CLK_EN_MSK 0x00000010
+#define MTX_QUE_CLK_EN_I_MSK 0xffffffef
+#define MTX_QUE_CLK_EN_SFT 4
+#define MTX_QUE_CLK_EN_HI 4
+#define MTX_QUE_CLK_EN_SZ 1
+#define MRX_CLK_EN_MSK 0x00000020
+#define MRX_CLK_EN_I_MSK 0xffffffdf
+#define MRX_CLK_EN_SFT 5
+#define MRX_CLK_EN_HI 5
+#define MRX_CLK_EN_SZ 1
+#define AMPDU_CLK_EN_MSK 0x00000040
+#define AMPDU_CLK_EN_I_MSK 0xffffffbf
+#define AMPDU_CLK_EN_SFT 6
+#define AMPDU_CLK_EN_HI 6
+#define AMPDU_CLK_EN_SZ 1
+#define MMU_CLK_EN_MSK 0x00000080
+#define MMU_CLK_EN_I_MSK 0xffffff7f
+#define MMU_CLK_EN_SFT 7
+#define MMU_CLK_EN_HI 7
+#define MMU_CLK_EN_SZ 1
+#define ID_MNG_CLK_EN_MSK 0x00000200
+#define ID_MNG_CLK_EN_I_MSK 0xfffffdff
+#define ID_MNG_CLK_EN_SFT 9
+#define ID_MNG_CLK_EN_HI 9
+#define ID_MNG_CLK_EN_SZ 1
+#define MBOX_CLK_EN_MSK 0x00000400
+#define MBOX_CLK_EN_I_MSK 0xfffffbff
+#define MBOX_CLK_EN_SFT 10
+#define MBOX_CLK_EN_HI 10
+#define MBOX_CLK_EN_SZ 1
+#define SCRT_CLK_EN_MSK 0x00000800
+#define SCRT_CLK_EN_I_MSK 0xfffff7ff
+#define SCRT_CLK_EN_SFT 11
+#define SCRT_CLK_EN_HI 11
+#define SCRT_CLK_EN_SZ 1
+#define MIC_CLK_EN_MSK 0x00001000
+#define MIC_CLK_EN_I_MSK 0xffffefff
+#define MIC_CLK_EN_SFT 12
+#define MIC_CLK_EN_HI 12
+#define MIC_CLK_EN_SZ 1
+#define MIB_CLK_EN_MSK 0x00002000
+#define MIB_CLK_EN_I_MSK 0xffffdfff
+#define MIB_CLK_EN_SFT 13
+#define MIB_CLK_EN_HI 13
+#define MIB_CLK_EN_SZ 1
+#define HCI_ENG_CLK_EN_MSK 0x00000001
+#define HCI_ENG_CLK_EN_I_MSK 0xfffffffe
+#define HCI_ENG_CLK_EN_SFT 0
+#define HCI_ENG_CLK_EN_HI 0
+#define HCI_ENG_CLK_EN_SZ 1
+#define CO_PROC_ENG_CLK_EN_MSK 0x00000002
+#define CO_PROC_ENG_CLK_EN_I_MSK 0xfffffffd
+#define CO_PROC_ENG_CLK_EN_SFT 1
+#define CO_PROC_ENG_CLK_EN_HI 1
+#define CO_PROC_ENG_CLK_EN_SZ 1
+#define MTX_MISC_ENG_CLK_EN_MSK 0x00000008
+#define MTX_MISC_ENG_CLK_EN_I_MSK 0xfffffff7
+#define MTX_MISC_ENG_CLK_EN_SFT 3
+#define MTX_MISC_ENG_CLK_EN_HI 3
+#define MTX_MISC_ENG_CLK_EN_SZ 1
+#define MTX_QUE_ENG_CLK_EN_MSK 0x00000010
+#define MTX_QUE_ENG_CLK_EN_I_MSK 0xffffffef
+#define MTX_QUE_ENG_CLK_EN_SFT 4
+#define MTX_QUE_ENG_CLK_EN_HI 4
+#define MTX_QUE_ENG_CLK_EN_SZ 1
+#define MRX_ENG_CLK_EN_MSK 0x00000020
+#define MRX_ENG_CLK_EN_I_MSK 0xffffffdf
+#define MRX_ENG_CLK_EN_SFT 5
+#define MRX_ENG_CLK_EN_HI 5
+#define MRX_ENG_CLK_EN_SZ 1
+#define AMPDU_ENG_CLK_EN_MSK 0x00000040
+#define AMPDU_ENG_CLK_EN_I_MSK 0xffffffbf
+#define AMPDU_ENG_CLK_EN_SFT 6
+#define AMPDU_ENG_CLK_EN_HI 6
+#define AMPDU_ENG_CLK_EN_SZ 1
+#define ID_MNG_ENG_CLK_EN_MSK 0x00001000
+#define ID_MNG_ENG_CLK_EN_I_MSK 0xffffefff
+#define ID_MNG_ENG_CLK_EN_SFT 12
+#define ID_MNG_ENG_CLK_EN_HI 12
+#define ID_MNG_ENG_CLK_EN_SZ 1
+#define MBOX_ENG_CLK_EN_MSK 0x00002000
+#define MBOX_ENG_CLK_EN_I_MSK 0xffffdfff
+#define MBOX_ENG_CLK_EN_SFT 13
+#define MBOX_ENG_CLK_EN_HI 13
+#define MBOX_ENG_CLK_EN_SZ 1
+#define SCRT_ENG_CLK_EN_MSK 0x00004000
+#define SCRT_ENG_CLK_EN_I_MSK 0xffffbfff
+#define SCRT_ENG_CLK_EN_SFT 14
+#define SCRT_ENG_CLK_EN_HI 14
+#define SCRT_ENG_CLK_EN_SZ 1
+#define MIC_ENG_CLK_EN_MSK 0x00008000
+#define MIC_ENG_CLK_EN_I_MSK 0xffff7fff
+#define MIC_ENG_CLK_EN_SFT 15
+#define MIC_ENG_CLK_EN_HI 15
+#define MIC_ENG_CLK_EN_SZ 1
+#define CO_PROC_CSR_CLK_EN_MSK 0x00000002
+#define CO_PROC_CSR_CLK_EN_I_MSK 0xfffffffd
+#define CO_PROC_CSR_CLK_EN_SFT 1
+#define CO_PROC_CSR_CLK_EN_HI 1
+#define CO_PROC_CSR_CLK_EN_SZ 1
+#define MRX_CSR_CLK_EN_MSK 0x00000400
+#define MRX_CSR_CLK_EN_I_MSK 0xfffffbff
+#define MRX_CSR_CLK_EN_SFT 10
+#define MRX_CSR_CLK_EN_HI 10
+#define MRX_CSR_CLK_EN_SZ 1
+#define AMPDU_CSR_CLK_EN_MSK 0x00000800
+#define AMPDU_CSR_CLK_EN_I_MSK 0xfffff7ff
+#define AMPDU_CSR_CLK_EN_SFT 11
+#define AMPDU_CSR_CLK_EN_HI 11
+#define AMPDU_CSR_CLK_EN_SZ 1
+#define SCRT_CSR_CLK_EN_MSK 0x00002000
+#define SCRT_CSR_CLK_EN_I_MSK 0xffffdfff
+#define SCRT_CSR_CLK_EN_SFT 13
+#define SCRT_CSR_CLK_EN_HI 13
+#define SCRT_CSR_CLK_EN_SZ 1
+#define ID_MNG_CSR_CLK_EN_MSK 0x00004000
+#define ID_MNG_CSR_CLK_EN_I_MSK 0xffffbfff
+#define ID_MNG_CSR_CLK_EN_SFT 14
+#define ID_MNG_CSR_CLK_EN_HI 14
+#define ID_MNG_CSR_CLK_EN_SZ 1
+#define MBOX_CSR_CLK_EN_MSK 0x00008000
+#define MBOX_CSR_CLK_EN_I_MSK 0xffff7fff
+#define MBOX_CSR_CLK_EN_SFT 15
+#define MBOX_CSR_CLK_EN_HI 15
+#define MBOX_CSR_CLK_EN_SZ 1
+#define OP_MODE_MSK 0x00000003
+#define OP_MODE_I_MSK 0xfffffffc
+#define OP_MODE_SFT 0
+#define OP_MODE_HI 1
+#define OP_MODE_SZ 2
+#define HT_MODE_MSK 0x0000000c
+#define HT_MODE_I_MSK 0xfffffff3
+#define HT_MODE_SFT 2
+#define HT_MODE_HI 3
+#define HT_MODE_SZ 2
+#define QOS_EN_MSK 0x00000010
+#define QOS_EN_I_MSK 0xffffffef
+#define QOS_EN_SFT 4
+#define QOS_EN_HI 4
+#define QOS_EN_SZ 1
+#define PB_OFFSET_MSK 0x0000ff00
+#define PB_OFFSET_I_MSK 0xffff00ff
+#define PB_OFFSET_SFT 8
+#define PB_OFFSET_HI 15
+#define PB_OFFSET_SZ 8
+#define SNIFFER_MODE_MSK 0x00010000
+#define SNIFFER_MODE_I_MSK 0xfffeffff
+#define SNIFFER_MODE_SFT 16
+#define SNIFFER_MODE_HI 16
+#define SNIFFER_MODE_SZ 1
+#define DUP_FLT_MSK 0x00020000
+#define DUP_FLT_I_MSK 0xfffdffff
+#define DUP_FLT_SFT 17
+#define DUP_FLT_HI 17
+#define DUP_FLT_SZ 1
+#define TX_PKT_RSVD_MSK 0x001c0000
+#define TX_PKT_RSVD_I_MSK 0xffe3ffff
+#define TX_PKT_RSVD_SFT 18
+#define TX_PKT_RSVD_HI 20
+#define TX_PKT_RSVD_SZ 3
+#define AMPDU_SNIFFER_MSK 0x00200000
+#define AMPDU_SNIFFER_I_MSK 0xffdfffff
+#define AMPDU_SNIFFER_SFT 21
+#define AMPDU_SNIFFER_HI 21
+#define AMPDU_SNIFFER_SZ 1
+#define CCMP_H_SEL_MSK 0x00400000
+#define CCMP_H_SEL_I_MSK 0xffbfffff
+#define CCMP_H_SEL_SFT 22
+#define CCMP_H_SEL_HI 22
+#define CCMP_H_SEL_SZ 1
+#define LUT_SEL_V2_MSK 0x00800000
+#define LUT_SEL_V2_I_MSK 0xff7fffff
+#define LUT_SEL_V2_SFT 23
+#define LUT_SEL_V2_HI 23
+#define LUT_SEL_V2_SZ 1
+#define REASON_TRAP0_MSK 0xffffffff
+#define REASON_TRAP0_I_MSK 0x00000000
+#define REASON_TRAP0_SFT 0
+#define REASON_TRAP0_HI 31
+#define REASON_TRAP0_SZ 32
+#define REASON_TRAP1_MSK 0xffffffff
+#define REASON_TRAP1_I_MSK 0x00000000
+#define REASON_TRAP1_SFT 0
+#define REASON_TRAP1_HI 31
+#define REASON_TRAP1_SZ 32
+#define BSSID_31_0_MSK 0xffffffff
+#define BSSID_31_0_I_MSK 0x00000000
+#define BSSID_31_0_SFT 0
+#define BSSID_31_0_HI 31
+#define BSSID_31_0_SZ 32
+#define BSSID_47_32_MSK 0x0000ffff
+#define BSSID_47_32_I_MSK 0xffff0000
+#define BSSID_47_32_SFT 0
+#define BSSID_47_32_HI 15
+#define BSSID_47_32_SZ 16
+#define STA_MAC_31_0_MSK 0xffffffff
+#define STA_MAC_31_0_I_MSK 0x00000000
+#define STA_MAC_31_0_SFT 0
+#define STA_MAC_31_0_HI 31
+#define STA_MAC_31_0_SZ 32
+#define STA_MAC_47_32_MSK 0x0000ffff
+#define STA_MAC_47_32_I_MSK 0xffff0000
+#define STA_MAC_47_32_SFT 0
+#define STA_MAC_47_32_HI 15
+#define STA_MAC_47_32_SZ 16
+#define PAIR_SCRT_MSK 0x00000007
+#define PAIR_SCRT_I_MSK 0xfffffff8
+#define PAIR_SCRT_SFT 0
+#define PAIR_SCRT_HI 2
+#define PAIR_SCRT_SZ 3
+#define GRP_SCRT_MSK 0x00000038
+#define GRP_SCRT_I_MSK 0xffffffc7
+#define GRP_SCRT_SFT 3
+#define GRP_SCRT_HI 5
+#define GRP_SCRT_SZ 3
+#define SCRT_PKT_ID_MSK 0x00001fc0
+#define SCRT_PKT_ID_I_MSK 0xffffe03f
+#define SCRT_PKT_ID_SFT 6
+#define SCRT_PKT_ID_HI 12
+#define SCRT_PKT_ID_SZ 7
+#define SCRT_RPLY_IGNORE_MSK 0x00010000
+#define SCRT_RPLY_IGNORE_I_MSK 0xfffeffff
+#define SCRT_RPLY_IGNORE_SFT 16
+#define SCRT_RPLY_IGNORE_HI 16
+#define SCRT_RPLY_IGNORE_SZ 1
+#define SCRT_STATE_MSK 0x0000000f
+#define SCRT_STATE_I_MSK 0xfffffff0
+#define SCRT_STATE_SFT 0
+#define SCRT_STATE_HI 3
+#define SCRT_STATE_SZ 4
+#define BSSID1_31_0_MSK 0xffffffff
+#define BSSID1_31_0_I_MSK 0x00000000
+#define BSSID1_31_0_SFT 0
+#define BSSID1_31_0_HI 31
+#define BSSID1_31_0_SZ 32
+#define BSSID1_47_32_MSK 0x0000ffff
+#define BSSID1_47_32_I_MSK 0xffff0000
+#define BSSID1_47_32_SFT 0
+#define BSSID1_47_32_HI 15
+#define BSSID1_47_32_SZ 16
+#define STA_MAC1_31_0_MSK 0xffffffff
+#define STA_MAC1_31_0_I_MSK 0x00000000
+#define STA_MAC1_31_0_SFT 0
+#define STA_MAC1_31_0_HI 31
+#define STA_MAC1_31_0_SZ 32
+#define STA_MAC1_47_32_MSK 0x0000ffff
+#define STA_MAC1_47_32_I_MSK 0xffff0000
+#define STA_MAC1_47_32_SFT 0
+#define STA_MAC1_47_32_HI 15
+#define STA_MAC1_47_32_SZ 16
+#define OP_MODE1_MSK 0x00000003
+#define OP_MODE1_I_MSK 0xfffffffc
+#define OP_MODE1_SFT 0
+#define OP_MODE1_HI 1
+#define OP_MODE1_SZ 2
+#define COEXIST_EN_MSK 0x00000001
+#define COEXIST_EN_I_MSK 0xfffffffe
+#define COEXIST_EN_SFT 0
+#define COEXIST_EN_HI 0
+#define COEXIST_EN_SZ 1
+#define WIRE_MODE_MSK 0x0000000e
+#define WIRE_MODE_I_MSK 0xfffffff1
+#define WIRE_MODE_SFT 1
+#define WIRE_MODE_HI 3
+#define WIRE_MODE_SZ 3
+#define WL_RX_PRI_MSK 0x00000010
+#define WL_RX_PRI_I_MSK 0xffffffef
+#define WL_RX_PRI_SFT 4
+#define WL_RX_PRI_HI 4
+#define WL_RX_PRI_SZ 1
+#define WL_TX_PRI_MSK 0x00000020
+#define WL_TX_PRI_I_MSK 0xffffffdf
+#define WL_TX_PRI_SFT 5
+#define WL_TX_PRI_HI 5
+#define WL_TX_PRI_SZ 1
+#define GURAN_USE_EN_MSK 0x00000100
+#define GURAN_USE_EN_I_MSK 0xfffffeff
+#define GURAN_USE_EN_SFT 8
+#define GURAN_USE_EN_HI 8
+#define GURAN_USE_EN_SZ 1
+#define GURAN_USE_CTRL_MSK 0x00000200
+#define GURAN_USE_CTRL_I_MSK 0xfffffdff
+#define GURAN_USE_CTRL_SFT 9
+#define GURAN_USE_CTRL_HI 9
+#define GURAN_USE_CTRL_SZ 1
+#define BEACON_TIMEOUT_EN_MSK 0x00000400
+#define BEACON_TIMEOUT_EN_I_MSK 0xfffffbff
+#define BEACON_TIMEOUT_EN_SFT 10
+#define BEACON_TIMEOUT_EN_HI 10
+#define BEACON_TIMEOUT_EN_SZ 1
+#define WLAN_ACT_POL_MSK 0x00000800
+#define WLAN_ACT_POL_I_MSK 0xfffff7ff
+#define WLAN_ACT_POL_SFT 11
+#define WLAN_ACT_POL_HI 11
+#define WLAN_ACT_POL_SZ 1
+#define DUAL_ANT_EN_MSK 0x00001000
+#define DUAL_ANT_EN_I_MSK 0xffffefff
+#define DUAL_ANT_EN_SFT 12
+#define DUAL_ANT_EN_HI 12
+#define DUAL_ANT_EN_SZ 1
+#define TRSW_PHY_POL_MSK 0x00010000
+#define TRSW_PHY_POL_I_MSK 0xfffeffff
+#define TRSW_PHY_POL_SFT 16
+#define TRSW_PHY_POL_HI 16
+#define TRSW_PHY_POL_SZ 1
+#define WIFI_TX_SW_POL_MSK 0x00020000
+#define WIFI_TX_SW_POL_I_MSK 0xfffdffff
+#define WIFI_TX_SW_POL_SFT 17
+#define WIFI_TX_SW_POL_HI 17
+#define WIFI_TX_SW_POL_SZ 1
+#define WIFI_RX_SW_POL_MSK 0x00040000
+#define WIFI_RX_SW_POL_I_MSK 0xfffbffff
+#define WIFI_RX_SW_POL_SFT 18
+#define WIFI_RX_SW_POL_HI 18
+#define WIFI_RX_SW_POL_SZ 1
+#define BT_SW_POL_MSK 0x00080000
+#define BT_SW_POL_I_MSK 0xfff7ffff
+#define BT_SW_POL_SFT 19
+#define BT_SW_POL_HI 19
+#define BT_SW_POL_SZ 1
+#define BT_PRI_SMP_TIME_MSK 0x000000ff
+#define BT_PRI_SMP_TIME_I_MSK 0xffffff00
+#define BT_PRI_SMP_TIME_SFT 0
+#define BT_PRI_SMP_TIME_HI 7
+#define BT_PRI_SMP_TIME_SZ 8
+#define BT_STA_SMP_TIME_MSK 0x0000ff00
+#define BT_STA_SMP_TIME_I_MSK 0xffff00ff
+#define BT_STA_SMP_TIME_SFT 8
+#define BT_STA_SMP_TIME_HI 15
+#define BT_STA_SMP_TIME_SZ 8
+#define BEACON_TIMEOUT_MSK 0x00ff0000
+#define BEACON_TIMEOUT_I_MSK 0xff00ffff
+#define BEACON_TIMEOUT_SFT 16
+#define BEACON_TIMEOUT_HI 23
+#define BEACON_TIMEOUT_SZ 8
+#define WLAN_REMAIN_TIME_MSK 0xff000000
+#define WLAN_REMAIN_TIME_I_MSK 0x00ffffff
+#define WLAN_REMAIN_TIME_SFT 24
+#define WLAN_REMAIN_TIME_HI 31
+#define WLAN_REMAIN_TIME_SZ 8
+#define SW_MANUAL_EN_MSK 0x00000001
+#define SW_MANUAL_EN_I_MSK 0xfffffffe
+#define SW_MANUAL_EN_SFT 0
+#define SW_MANUAL_EN_HI 0
+#define SW_MANUAL_EN_SZ 1
+#define SW_WL_TX_MSK 0x00000002
+#define SW_WL_TX_I_MSK 0xfffffffd
+#define SW_WL_TX_SFT 1
+#define SW_WL_TX_HI 1
+#define SW_WL_TX_SZ 1
+#define SW_WL_RX_MSK 0x00000004
+#define SW_WL_RX_I_MSK 0xfffffffb
+#define SW_WL_RX_SFT 2
+#define SW_WL_RX_HI 2
+#define SW_WL_RX_SZ 1
+#define SW_BT_TRX_MSK 0x00000008
+#define SW_BT_TRX_I_MSK 0xfffffff7
+#define SW_BT_TRX_SFT 3
+#define SW_BT_TRX_HI 3
+#define SW_BT_TRX_SZ 1
+#define BT_TXBAR_MANUAL_EN_MSK 0x00000010
+#define BT_TXBAR_MANUAL_EN_I_MSK 0xffffffef
+#define BT_TXBAR_MANUAL_EN_SFT 4
+#define BT_TXBAR_MANUAL_EN_HI 4
+#define BT_TXBAR_MANUAL_EN_SZ 1
+#define BT_TXBAR_SET_MSK 0x00000020
+#define BT_TXBAR_SET_I_MSK 0xffffffdf
+#define BT_TXBAR_SET_SFT 5
+#define BT_TXBAR_SET_HI 5
+#define BT_TXBAR_SET_SZ 1
+#define BT_BUSY_MANUAL_EN_MSK 0x00000100
+#define BT_BUSY_MANUAL_EN_I_MSK 0xfffffeff
+#define BT_BUSY_MANUAL_EN_SFT 8
+#define BT_BUSY_MANUAL_EN_HI 8
+#define BT_BUSY_MANUAL_EN_SZ 1
+#define BT_BUSY_SET_MSK 0x00000200
+#define BT_BUSY_SET_I_MSK 0xfffffdff
+#define BT_BUSY_SET_SFT 9
+#define BT_BUSY_SET_HI 9
+#define BT_BUSY_SET_SZ 1
+#define SWITCH_2WIRE_EN_MSK 0x00000400
+#define SWITCH_2WIRE_EN_I_MSK 0xfffffbff
+#define SWITCH_2WIRE_EN_SFT 10
+#define SWITCH_2WIRE_EN_HI 10
+#define SWITCH_2WIRE_EN_SZ 1
+#define RANDOM_SEED3_MSK 0x000000ff
+#define RANDOM_SEED3_I_MSK 0xffffff00
+#define RANDOM_SEED3_SFT 0
+#define RANDOM_SEED3_HI 7
+#define RANDOM_SEED3_SZ 8
+#define RANDOM_SEED2_MSK 0x0000ff00
+#define RANDOM_SEED2_I_MSK 0xffff00ff
+#define RANDOM_SEED2_SFT 8
+#define RANDOM_SEED2_HI 15
+#define RANDOM_SEED2_SZ 8
+#define RANDOM_SEED1_MSK 0x00ff0000
+#define RANDOM_SEED1_I_MSK 0xff00ffff
+#define RANDOM_SEED1_SFT 16
+#define RANDOM_SEED1_HI 23
+#define RANDOM_SEED1_SZ 8
+#define BT_TRX_SMP_TIME_MSK 0xff000000
+#define BT_TRX_SMP_TIME_I_MSK 0x00ffffff
+#define BT_TRX_SMP_TIME_SFT 24
+#define BT_TRX_SMP_TIME_HI 31
+#define BT_TRX_SMP_TIME_SZ 8
+#define BTCX_INT_MASK_MSK 0x0000001f
+#define BTCX_INT_MASK_I_MSK 0xffffffe0
+#define BTCX_INT_MASK_SFT 0
+#define BTCX_INT_MASK_HI 4
+#define BTCX_INT_MASK_SZ 5
+#define BTCX_INTR_MSK 0x00000020
+#define BTCX_INTR_I_MSK 0xffffffdf
+#define BTCX_INTR_SFT 5
+#define BTCX_INTR_HI 5
+#define BTCX_INTR_SZ 1
+#define AUTO_REMAIN_MSK 0x00000040
+#define AUTO_REMAIN_I_MSK 0xffffffbf
+#define AUTO_REMAIN_SFT 6
+#define AUTO_REMAIN_HI 6
+#define AUTO_REMAIN_SZ 1
+#define PREDE_BT_TX_MSK 0x00000080
+#define PREDE_BT_TX_I_MSK 0xffffff7f
+#define PREDE_BT_TX_SFT 7
+#define PREDE_BT_TX_HI 7
+#define PREDE_BT_TX_SZ 1
+#define G0_PKT_CLS_MIB_EN_MSK 0x00000004
+#define G0_PKT_CLS_MIB_EN_I_MSK 0xfffffffb
+#define G0_PKT_CLS_MIB_EN_SFT 2
+#define G0_PKT_CLS_MIB_EN_HI 2
+#define G0_PKT_CLS_MIB_EN_SZ 1
+#define G0_PKT_CLS_ONGOING_MSK 0x00000008
+#define G0_PKT_CLS_ONGOING_I_MSK 0xfffffff7
+#define G0_PKT_CLS_ONGOING_SFT 3
+#define G0_PKT_CLS_ONGOING_HI 3
+#define G0_PKT_CLS_ONGOING_SZ 1
+#define G1_PKT_CLS_MIB_EN_MSK 0x00000010
+#define G1_PKT_CLS_MIB_EN_I_MSK 0xffffffef
+#define G1_PKT_CLS_MIB_EN_SFT 4
+#define G1_PKT_CLS_MIB_EN_HI 4
+#define G1_PKT_CLS_MIB_EN_SZ 1
+#define G1_PKT_CLS_ONGOING_MSK 0x00000020
+#define G1_PKT_CLS_ONGOING_I_MSK 0xffffffdf
+#define G1_PKT_CLS_ONGOING_SFT 5
+#define G1_PKT_CLS_ONGOING_HI 5
+#define G1_PKT_CLS_ONGOING_SZ 1
+#define Q0_PKT_CLS_MIB_EN_MSK 0x00000040
+#define Q0_PKT_CLS_MIB_EN_I_MSK 0xffffffbf
+#define Q0_PKT_CLS_MIB_EN_SFT 6
+#define Q0_PKT_CLS_MIB_EN_HI 6
+#define Q0_PKT_CLS_MIB_EN_SZ 1
+#define Q0_PKT_CLS_ONGOING_MSK 0x00000080
+#define Q0_PKT_CLS_ONGOING_I_MSK 0xffffff7f
+#define Q0_PKT_CLS_ONGOING_SFT 7
+#define Q0_PKT_CLS_ONGOING_HI 7
+#define Q0_PKT_CLS_ONGOING_SZ 1
+#define Q1_PKT_CLS_MIB_EN_MSK 0x00000100
+#define Q1_PKT_CLS_MIB_EN_I_MSK 0xfffffeff
+#define Q1_PKT_CLS_MIB_EN_SFT 8
+#define Q1_PKT_CLS_MIB_EN_HI 8
+#define Q1_PKT_CLS_MIB_EN_SZ 1
+#define Q1_PKT_CLS_ONGOING_MSK 0x00000200
+#define Q1_PKT_CLS_ONGOING_I_MSK 0xfffffdff
+#define Q1_PKT_CLS_ONGOING_SFT 9
+#define Q1_PKT_CLS_ONGOING_HI 9
+#define Q1_PKT_CLS_ONGOING_SZ 1
+#define Q2_PKT_CLS_MIB_EN_MSK 0x00000400
+#define Q2_PKT_CLS_MIB_EN_I_MSK 0xfffffbff
+#define Q2_PKT_CLS_MIB_EN_SFT 10
+#define Q2_PKT_CLS_MIB_EN_HI 10
+#define Q2_PKT_CLS_MIB_EN_SZ 1
+#define Q2_PKT_CLS_ONGOING_MSK 0x00000800
+#define Q2_PKT_CLS_ONGOING_I_MSK 0xfffff7ff
+#define Q2_PKT_CLS_ONGOING_SFT 11
+#define Q2_PKT_CLS_ONGOING_HI 11
+#define Q2_PKT_CLS_ONGOING_SZ 1
+#define Q3_PKT_CLS_MIB_EN_MSK 0x00001000
+#define Q3_PKT_CLS_MIB_EN_I_MSK 0xffffefff
+#define Q3_PKT_CLS_MIB_EN_SFT 12
+#define Q3_PKT_CLS_MIB_EN_HI 12
+#define Q3_PKT_CLS_MIB_EN_SZ 1
+#define Q3_PKT_CLS_ONGOING_MSK 0x00002000
+#define Q3_PKT_CLS_ONGOING_I_MSK 0xffffdfff
+#define Q3_PKT_CLS_ONGOING_SFT 13
+#define Q3_PKT_CLS_ONGOING_HI 13
+#define Q3_PKT_CLS_ONGOING_SZ 1
+#define SCRT_PKT_CLS_MIB_EN_MSK 0x00004000
+#define SCRT_PKT_CLS_MIB_EN_I_MSK 0xffffbfff
+#define SCRT_PKT_CLS_MIB_EN_SFT 14
+#define SCRT_PKT_CLS_MIB_EN_HI 14
+#define SCRT_PKT_CLS_MIB_EN_SZ 1
+#define SCRT_PKT_CLS_ONGOING_MSK 0x00008000
+#define SCRT_PKT_CLS_ONGOING_I_MSK 0xffff7fff
+#define SCRT_PKT_CLS_ONGOING_SFT 15
+#define SCRT_PKT_CLS_ONGOING_HI 15
+#define SCRT_PKT_CLS_ONGOING_SZ 1
+#define MISC_PKT_CLS_MIB_EN_MSK 0x00010000
+#define MISC_PKT_CLS_MIB_EN_I_MSK 0xfffeffff
+#define MISC_PKT_CLS_MIB_EN_SFT 16
+#define MISC_PKT_CLS_MIB_EN_HI 16
+#define MISC_PKT_CLS_MIB_EN_SZ 1
+#define MISC_PKT_CLS_ONGOING_MSK 0x00020000
+#define MISC_PKT_CLS_ONGOING_I_MSK 0xfffdffff
+#define MISC_PKT_CLS_ONGOING_SFT 17
+#define MISC_PKT_CLS_ONGOING_HI 17
+#define MISC_PKT_CLS_ONGOING_SZ 1
+#define MTX_WSID0_SUCC_MSK 0x0000ffff
+#define MTX_WSID0_SUCC_I_MSK 0xffff0000
+#define MTX_WSID0_SUCC_SFT 0
+#define MTX_WSID0_SUCC_HI 15
+#define MTX_WSID0_SUCC_SZ 16
+#define MTX_WSID0_FRM_MSK 0x0000ffff
+#define MTX_WSID0_FRM_I_MSK 0xffff0000
+#define MTX_WSID0_FRM_SFT 0
+#define MTX_WSID0_FRM_HI 15
+#define MTX_WSID0_FRM_SZ 16
+#define MTX_WSID0_RETRY_MSK 0x0000ffff
+#define MTX_WSID0_RETRY_I_MSK 0xffff0000
+#define MTX_WSID0_RETRY_SFT 0
+#define MTX_WSID0_RETRY_HI 15
+#define MTX_WSID0_RETRY_SZ 16
+#define MTX_WSID0_TOTAL_MSK 0x0000ffff
+#define MTX_WSID0_TOTAL_I_MSK 0xffff0000
+#define MTX_WSID0_TOTAL_SFT 0
+#define MTX_WSID0_TOTAL_HI 15
+#define MTX_WSID0_TOTAL_SZ 16
+#define MTX_GRP_MSK 0x000fffff
+#define MTX_GRP_I_MSK 0xfff00000
+#define MTX_GRP_SFT 0
+#define MTX_GRP_HI 19
+#define MTX_GRP_SZ 20
+#define MTX_FAIL_MSK 0x0000ffff
+#define MTX_FAIL_I_MSK 0xffff0000
+#define MTX_FAIL_SFT 0
+#define MTX_FAIL_HI 15
+#define MTX_FAIL_SZ 16
+#define MTX_RETRY_MSK 0x000fffff
+#define MTX_RETRY_I_MSK 0xfff00000
+#define MTX_RETRY_SFT 0
+#define MTX_RETRY_HI 19
+#define MTX_RETRY_SZ 20
+#define MTX_MULTI_RETRY_MSK 0x000fffff
+#define MTX_MULTI_RETRY_I_MSK 0xfff00000
+#define MTX_MULTI_RETRY_SFT 0
+#define MTX_MULTI_RETRY_HI 19
+#define MTX_MULTI_RETRY_SZ 20
+#define MTX_RTS_SUCC_MSK 0x0000ffff
+#define MTX_RTS_SUCC_I_MSK 0xffff0000
+#define MTX_RTS_SUCC_SFT 0
+#define MTX_RTS_SUCC_HI 15
+#define MTX_RTS_SUCC_SZ 16
+#define MTX_RTS_FAIL_MSK 0x0000ffff
+#define MTX_RTS_FAIL_I_MSK 0xffff0000
+#define MTX_RTS_FAIL_SFT 0
+#define MTX_RTS_FAIL_HI 15
+#define MTX_RTS_FAIL_SZ 16
+#define MTX_ACK_FAIL_MSK 0x0000ffff
+#define MTX_ACK_FAIL_I_MSK 0xffff0000
+#define MTX_ACK_FAIL_SFT 0
+#define MTX_ACK_FAIL_HI 15
+#define MTX_ACK_FAIL_SZ 16
+#define MTX_FRM_MSK 0x000fffff
+#define MTX_FRM_I_MSK 0xfff00000
+#define MTX_FRM_SFT 0
+#define MTX_FRM_HI 19
+#define MTX_FRM_SZ 20
+#define MTX_ACK_TX_MSK 0x0000ffff
+#define MTX_ACK_TX_I_MSK 0xffff0000
+#define MTX_ACK_TX_SFT 0
+#define MTX_ACK_TX_HI 15
+#define MTX_ACK_TX_SZ 16
+#define MTX_CTS_TX_MSK 0x0000ffff
+#define MTX_CTS_TX_I_MSK 0xffff0000
+#define MTX_CTS_TX_SFT 0
+#define MTX_CTS_TX_HI 15
+#define MTX_CTS_TX_SZ 16
+#define MRX_DUP_MSK 0x0000ffff
+#define MRX_DUP_I_MSK 0xffff0000
+#define MRX_DUP_SFT 0
+#define MRX_DUP_HI 15
+#define MRX_DUP_SZ 16
+#define MRX_FRG_MSK 0x000fffff
+#define MRX_FRG_I_MSK 0xfff00000
+#define MRX_FRG_SFT 0
+#define MRX_FRG_HI 19
+#define MRX_FRG_SZ 20
+#define MRX_GRP_MSK 0x000fffff
+#define MRX_GRP_I_MSK 0xfff00000
+#define MRX_GRP_SFT 0
+#define MRX_GRP_HI 19
+#define MRX_GRP_SZ 20
+#define MRX_FCS_ERR_MSK 0x0000ffff
+#define MRX_FCS_ERR_I_MSK 0xffff0000
+#define MRX_FCS_ERR_SFT 0
+#define MRX_FCS_ERR_HI 15
+#define MRX_FCS_ERR_SZ 16
+#define MRX_FCS_SUC_MSK 0x0000ffff
+#define MRX_FCS_SUC_I_MSK 0xffff0000
+#define MRX_FCS_SUC_SFT 0
+#define MRX_FCS_SUC_HI 15
+#define MRX_FCS_SUC_SZ 16
+#define MRX_MISS_MSK 0x0000ffff
+#define MRX_MISS_I_MSK 0xffff0000
+#define MRX_MISS_SFT 0
+#define MRX_MISS_HI 15
+#define MRX_MISS_SZ 16
+#define MRX_ALC_FAIL_MSK 0x0000ffff
+#define MRX_ALC_FAIL_I_MSK 0xffff0000
+#define MRX_ALC_FAIL_SFT 0
+#define MRX_ALC_FAIL_HI 15
+#define MRX_ALC_FAIL_SZ 16
+#define MRX_DAT_NTF_MSK 0x0000ffff
+#define MRX_DAT_NTF_I_MSK 0xffff0000
+#define MRX_DAT_NTF_SFT 0
+#define MRX_DAT_NTF_HI 15
+#define MRX_DAT_NTF_SZ 16
+#define MRX_RTS_NTF_MSK 0x0000ffff
+#define MRX_RTS_NTF_I_MSK 0xffff0000
+#define MRX_RTS_NTF_SFT 0
+#define MRX_RTS_NTF_HI 15
+#define MRX_RTS_NTF_SZ 16
+#define MRX_CTS_NTF_MSK 0x0000ffff
+#define MRX_CTS_NTF_I_MSK 0xffff0000
+#define MRX_CTS_NTF_SFT 0
+#define MRX_CTS_NTF_HI 15
+#define MRX_CTS_NTF_SZ 16
+#define MRX_ACK_NTF_MSK 0x0000ffff
+#define MRX_ACK_NTF_I_MSK 0xffff0000
+#define MRX_ACK_NTF_SFT 0
+#define MRX_ACK_NTF_HI 15
+#define MRX_ACK_NTF_SZ 16
+#define MRX_BA_NTF_MSK 0x0000ffff
+#define MRX_BA_NTF_I_MSK 0xffff0000
+#define MRX_BA_NTF_SFT 0
+#define MRX_BA_NTF_HI 15
+#define MRX_BA_NTF_SZ 16
+#define MRX_DATA_NTF_MSK 0x0000ffff
+#define MRX_DATA_NTF_I_MSK 0xffff0000
+#define MRX_DATA_NTF_SFT 0
+#define MRX_DATA_NTF_HI 15
+#define MRX_DATA_NTF_SZ 16
+#define MRX_MNG_NTF_MSK 0x0000ffff
+#define MRX_MNG_NTF_I_MSK 0xffff0000
+#define MRX_MNG_NTF_SFT 0
+#define MRX_MNG_NTF_HI 15
+#define MRX_MNG_NTF_SZ 16
+#define MRX_DAT_CRC_NTF_MSK 0x0000ffff
+#define MRX_DAT_CRC_NTF_I_MSK 0xffff0000
+#define MRX_DAT_CRC_NTF_SFT 0
+#define MRX_DAT_CRC_NTF_HI 15
+#define MRX_DAT_CRC_NTF_SZ 16
+#define MRX_BAR_NTF_MSK 0x0000ffff
+#define MRX_BAR_NTF_I_MSK 0xffff0000
+#define MRX_BAR_NTF_SFT 0
+#define MRX_BAR_NTF_HI 15
+#define MRX_BAR_NTF_SZ 16
+#define MRX_MB_MISS_MSK 0x0000ffff
+#define MRX_MB_MISS_I_MSK 0xffff0000
+#define MRX_MB_MISS_SFT 0
+#define MRX_MB_MISS_HI 15
+#define MRX_MB_MISS_SZ 16
+#define MRX_NIDLE_MISS_MSK 0x0000ffff
+#define MRX_NIDLE_MISS_I_MSK 0xffff0000
+#define MRX_NIDLE_MISS_SFT 0
+#define MRX_NIDLE_MISS_HI 15
+#define MRX_NIDLE_MISS_SZ 16
+#define MRX_CSR_NTF_MSK 0x0000ffff
+#define MRX_CSR_NTF_I_MSK 0xffff0000
+#define MRX_CSR_NTF_SFT 0
+#define MRX_CSR_NTF_HI 15
+#define MRX_CSR_NTF_SZ 16
+#define DBG_Q0_SUCC_MSK 0x0000ffff
+#define DBG_Q0_SUCC_I_MSK 0xffff0000
+#define DBG_Q0_SUCC_SFT 0
+#define DBG_Q0_SUCC_HI 15
+#define DBG_Q0_SUCC_SZ 16
+#define DBG_Q0_FAIL_MSK 0x0000ffff
+#define DBG_Q0_FAIL_I_MSK 0xffff0000
+#define DBG_Q0_FAIL_SFT 0
+#define DBG_Q0_FAIL_HI 15
+#define DBG_Q0_FAIL_SZ 16
+#define DBG_Q0_ACK_SUCC_MSK 0x0000ffff
+#define DBG_Q0_ACK_SUCC_I_MSK 0xffff0000
+#define DBG_Q0_ACK_SUCC_SFT 0
+#define DBG_Q0_ACK_SUCC_HI 15
+#define DBG_Q0_ACK_SUCC_SZ 16
+#define DBG_Q0_ACK_FAIL_MSK 0x0000ffff
+#define DBG_Q0_ACK_FAIL_I_MSK 0xffff0000
+#define DBG_Q0_ACK_FAIL_SFT 0
+#define DBG_Q0_ACK_FAIL_HI 15
+#define DBG_Q0_ACK_FAIL_SZ 16
+#define DBG_Q1_SUCC_MSK 0x0000ffff
+#define DBG_Q1_SUCC_I_MSK 0xffff0000
+#define DBG_Q1_SUCC_SFT 0
+#define DBG_Q1_SUCC_HI 15
+#define DBG_Q1_SUCC_SZ 16
+#define DBG_Q1_FAIL_MSK 0x0000ffff
+#define DBG_Q1_FAIL_I_MSK 0xffff0000
+#define DBG_Q1_FAIL_SFT 0
+#define DBG_Q1_FAIL_HI 15
+#define DBG_Q1_FAIL_SZ 16
+#define DBG_Q1_ACK_SUCC_MSK 0x0000ffff
+#define DBG_Q1_ACK_SUCC_I_MSK 0xffff0000
+#define DBG_Q1_ACK_SUCC_SFT 0
+#define DBG_Q1_ACK_SUCC_HI 15
+#define DBG_Q1_ACK_SUCC_SZ 16
+#define DBG_Q1_ACK_FAIL_MSK 0x0000ffff
+#define DBG_Q1_ACK_FAIL_I_MSK 0xffff0000
+#define DBG_Q1_ACK_FAIL_SFT 0
+#define DBG_Q1_ACK_FAIL_HI 15
+#define DBG_Q1_ACK_FAIL_SZ 16
+#define DBG_Q2_SUCC_MSK 0x0000ffff
+#define DBG_Q2_SUCC_I_MSK 0xffff0000
+#define DBG_Q2_SUCC_SFT 0
+#define DBG_Q2_SUCC_HI 15
+#define DBG_Q2_SUCC_SZ 16
+#define DBG_Q2_FAIL_MSK 0x0000ffff
+#define DBG_Q2_FAIL_I_MSK 0xffff0000
+#define DBG_Q2_FAIL_SFT 0
+#define DBG_Q2_FAIL_HI 15
+#define DBG_Q2_FAIL_SZ 16
+#define DBG_Q2_ACK_SUCC_MSK 0x0000ffff
+#define DBG_Q2_ACK_SUCC_I_MSK 0xffff0000
+#define DBG_Q2_ACK_SUCC_SFT 0
+#define DBG_Q2_ACK_SUCC_HI 15
+#define DBG_Q2_ACK_SUCC_SZ 16
+#define DBG_Q2_ACK_FAIL_MSK 0x0000ffff
+#define DBG_Q2_ACK_FAIL_I_MSK 0xffff0000
+#define DBG_Q2_ACK_FAIL_SFT 0
+#define DBG_Q2_ACK_FAIL_HI 15
+#define DBG_Q2_ACK_FAIL_SZ 16
+#define DBG_Q3_SUCC_MSK 0x0000ffff
+#define DBG_Q3_SUCC_I_MSK 0xffff0000
+#define DBG_Q3_SUCC_SFT 0
+#define DBG_Q3_SUCC_HI 15
+#define DBG_Q3_SUCC_SZ 16
+#define DBG_Q3_FAIL_MSK 0x0000ffff
+#define DBG_Q3_FAIL_I_MSK 0xffff0000
+#define DBG_Q3_FAIL_SFT 0
+#define DBG_Q3_FAIL_HI 15
+#define DBG_Q3_FAIL_SZ 16
+#define DBG_Q3_ACK_SUCC_MSK 0x0000ffff
+#define DBG_Q3_ACK_SUCC_I_MSK 0xffff0000
+#define DBG_Q3_ACK_SUCC_SFT 0
+#define DBG_Q3_ACK_SUCC_HI 15
+#define DBG_Q3_ACK_SUCC_SZ 16
+#define DBG_Q3_ACK_FAIL_MSK 0x0000ffff
+#define DBG_Q3_ACK_FAIL_I_MSK 0xffff0000
+#define DBG_Q3_ACK_FAIL_SFT 0
+#define DBG_Q3_ACK_FAIL_HI 15
+#define DBG_Q3_ACK_FAIL_SZ 16
+#define SCRT_TKIP_CERR_MSK 0x000fffff
+#define SCRT_TKIP_CERR_I_MSK 0xfff00000
+#define SCRT_TKIP_CERR_SFT 0
+#define SCRT_TKIP_CERR_HI 19
+#define SCRT_TKIP_CERR_SZ 20
+#define SCRT_TKIP_MIC_ERR_MSK 0x000fffff
+#define SCRT_TKIP_MIC_ERR_I_MSK 0xfff00000
+#define SCRT_TKIP_MIC_ERR_SFT 0
+#define SCRT_TKIP_MIC_ERR_HI 19
+#define SCRT_TKIP_MIC_ERR_SZ 20
+#define SCRT_TKIP_RPLY_MSK 0x000fffff
+#define SCRT_TKIP_RPLY_I_MSK 0xfff00000
+#define SCRT_TKIP_RPLY_SFT 0
+#define SCRT_TKIP_RPLY_HI 19
+#define SCRT_TKIP_RPLY_SZ 20
+#define SCRT_CCMP_RPLY_MSK 0x000fffff
+#define SCRT_CCMP_RPLY_I_MSK 0xfff00000
+#define SCRT_CCMP_RPLY_SFT 0
+#define SCRT_CCMP_RPLY_HI 19
+#define SCRT_CCMP_RPLY_SZ 20
+#define SCRT_CCMP_CERR_MSK 0x000fffff
+#define SCRT_CCMP_CERR_I_MSK 0xfff00000
+#define SCRT_CCMP_CERR_SFT 0
+#define SCRT_CCMP_CERR_HI 19
+#define SCRT_CCMP_CERR_SZ 20
+#define DBG_LEN_CRC_FAIL_MSK 0x0000ffff
+#define DBG_LEN_CRC_FAIL_I_MSK 0xffff0000
+#define DBG_LEN_CRC_FAIL_SFT 0
+#define DBG_LEN_CRC_FAIL_HI 15
+#define DBG_LEN_CRC_FAIL_SZ 16
+#define DBG_LEN_ALC_FAIL_MSK 0x0000ffff
+#define DBG_LEN_ALC_FAIL_I_MSK 0xffff0000
+#define DBG_LEN_ALC_FAIL_SFT 0
+#define DBG_LEN_ALC_FAIL_HI 15
+#define DBG_LEN_ALC_FAIL_SZ 16
+#define DBG_AMPDU_PASS_MSK 0x0000ffff
+#define DBG_AMPDU_PASS_I_MSK 0xffff0000
+#define DBG_AMPDU_PASS_SFT 0
+#define DBG_AMPDU_PASS_HI 15
+#define DBG_AMPDU_PASS_SZ 16
+#define DBG_AMPDU_FAIL_MSK 0x0000ffff
+#define DBG_AMPDU_FAIL_I_MSK 0xffff0000
+#define DBG_AMPDU_FAIL_SFT 0
+#define DBG_AMPDU_FAIL_HI 15
+#define DBG_AMPDU_FAIL_SZ 16
+#define RXID_ALC_CNT_FAIL_MSK 0x0000ffff
+#define RXID_ALC_CNT_FAIL_I_MSK 0xffff0000
+#define RXID_ALC_CNT_FAIL_SFT 0
+#define RXID_ALC_CNT_FAIL_HI 15
+#define RXID_ALC_CNT_FAIL_SZ 16
+#define RXID_ALC_LEN_FAIL_MSK 0x0000ffff
+#define RXID_ALC_LEN_FAIL_I_MSK 0xffff0000
+#define RXID_ALC_LEN_FAIL_SFT 0
+#define RXID_ALC_LEN_FAIL_HI 15
+#define RXID_ALC_LEN_FAIL_SZ 16
+#define VALID2_MSK 0x00000001
+#define VALID2_I_MSK 0xfffffffe
+#define VALID2_SFT 0
+#define VALID2_HI 0
+#define VALID2_SZ 1
+#define PEER_QOS_EN2_MSK 0x00000002
+#define PEER_QOS_EN2_I_MSK 0xfffffffd
+#define PEER_QOS_EN2_SFT 1
+#define PEER_QOS_EN2_HI 1
+#define PEER_QOS_EN2_SZ 1
+#define PEER_OP_MODE2_MSK 0x0000000c
+#define PEER_OP_MODE2_I_MSK 0xfffffff3
+#define PEER_OP_MODE2_SFT 2
+#define PEER_OP_MODE2_HI 3
+#define PEER_OP_MODE2_SZ 2
+#define PEER_HT_MODE2_MSK 0x00000030
+#define PEER_HT_MODE2_I_MSK 0xffffffcf
+#define PEER_HT_MODE2_SFT 4
+#define PEER_HT_MODE2_HI 5
+#define PEER_HT_MODE2_SZ 2
+#define PEER_MAC2_31_0_MSK 0xffffffff
+#define PEER_MAC2_31_0_I_MSK 0x00000000
+#define PEER_MAC2_31_0_SFT 0
+#define PEER_MAC2_31_0_HI 31
+#define PEER_MAC2_31_0_SZ 32
+#define PEER_MAC2_47_32_MSK 0x0000ffff
+#define PEER_MAC2_47_32_I_MSK 0xffff0000
+#define PEER_MAC2_47_32_SFT 0
+#define PEER_MAC2_47_32_HI 15
+#define PEER_MAC2_47_32_SZ 16
+#define TX_ACK_POLICY_2_0_MSK 0x00000003
+#define TX_ACK_POLICY_2_0_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_2_0_SFT 0
+#define TX_ACK_POLICY_2_0_HI 1
+#define TX_ACK_POLICY_2_0_SZ 2
+#define TX_SEQ_CTRL_2_0_MSK 0x00000fff
+#define TX_SEQ_CTRL_2_0_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_2_0_SFT 0
+#define TX_SEQ_CTRL_2_0_HI 11
+#define TX_SEQ_CTRL_2_0_SZ 12
+#define TX_ACK_POLICY_2_1_MSK 0x00000003
+#define TX_ACK_POLICY_2_1_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_2_1_SFT 0
+#define TX_ACK_POLICY_2_1_HI 1
+#define TX_ACK_POLICY_2_1_SZ 2
+#define TX_SEQ_CTRL_2_1_MSK 0x00000fff
+#define TX_SEQ_CTRL_2_1_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_2_1_SFT 0
+#define TX_SEQ_CTRL_2_1_HI 11
+#define TX_SEQ_CTRL_2_1_SZ 12
+#define TX_ACK_POLICY_2_2_MSK 0x00000003
+#define TX_ACK_POLICY_2_2_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_2_2_SFT 0
+#define TX_ACK_POLICY_2_2_HI 1
+#define TX_ACK_POLICY_2_2_SZ 2
+#define TX_SEQ_CTRL_2_2_MSK 0x00000fff
+#define TX_SEQ_CTRL_2_2_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_2_2_SFT 0
+#define TX_SEQ_CTRL_2_2_HI 11
+#define TX_SEQ_CTRL_2_2_SZ 12
+#define TX_ACK_POLICY_2_3_MSK 0x00000003
+#define TX_ACK_POLICY_2_3_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_2_3_SFT 0
+#define TX_ACK_POLICY_2_3_HI 1
+#define TX_ACK_POLICY_2_3_SZ 2
+#define TX_SEQ_CTRL_2_3_MSK 0x00000fff
+#define TX_SEQ_CTRL_2_3_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_2_3_SFT 0
+#define TX_SEQ_CTRL_2_3_HI 11
+#define TX_SEQ_CTRL_2_3_SZ 12
+#define TX_ACK_POLICY_2_4_MSK 0x00000003
+#define TX_ACK_POLICY_2_4_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_2_4_SFT 0
+#define TX_ACK_POLICY_2_4_HI 1
+#define TX_ACK_POLICY_2_4_SZ 2
+#define TX_SEQ_CTRL_2_4_MSK 0x00000fff
+#define TX_SEQ_CTRL_2_4_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_2_4_SFT 0
+#define TX_SEQ_CTRL_2_4_HI 11
+#define TX_SEQ_CTRL_2_4_SZ 12
+#define TX_ACK_POLICY_2_5_MSK 0x00000003
+#define TX_ACK_POLICY_2_5_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_2_5_SFT 0
+#define TX_ACK_POLICY_2_5_HI 1
+#define TX_ACK_POLICY_2_5_SZ 2
+#define TX_SEQ_CTRL_2_5_MSK 0x00000fff
+#define TX_SEQ_CTRL_2_5_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_2_5_SFT 0
+#define TX_SEQ_CTRL_2_5_HI 11
+#define TX_SEQ_CTRL_2_5_SZ 12
+#define TX_ACK_POLICY_2_6_MSK 0x00000003
+#define TX_ACK_POLICY_2_6_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_2_6_SFT 0
+#define TX_ACK_POLICY_2_6_HI 1
+#define TX_ACK_POLICY_2_6_SZ 2
+#define TX_SEQ_CTRL_2_6_MSK 0x00000fff
+#define TX_SEQ_CTRL_2_6_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_2_6_SFT 0
+#define TX_SEQ_CTRL_2_6_HI 11
+#define TX_SEQ_CTRL_2_6_SZ 12
+#define TX_ACK_POLICY_2_7_MSK 0x00000003
+#define TX_ACK_POLICY_2_7_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_2_7_SFT 0
+#define TX_ACK_POLICY_2_7_HI 1
+#define TX_ACK_POLICY_2_7_SZ 2
+#define TX_SEQ_CTRL_2_7_MSK 0x00000fff
+#define TX_SEQ_CTRL_2_7_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_2_7_SFT 0
+#define TX_SEQ_CTRL_2_7_HI 11
+#define TX_SEQ_CTRL_2_7_SZ 12
+#define VALID3_MSK 0x00000001
+#define VALID3_I_MSK 0xfffffffe
+#define VALID3_SFT 0
+#define VALID3_HI 0
+#define VALID3_SZ 1
+#define PEER_QOS_EN3_MSK 0x00000002
+#define PEER_QOS_EN3_I_MSK 0xfffffffd
+#define PEER_QOS_EN3_SFT 1
+#define PEER_QOS_EN3_HI 1
+#define PEER_QOS_EN3_SZ 1
+#define PEER_OP_MODE3_MSK 0x0000000c
+#define PEER_OP_MODE3_I_MSK 0xfffffff3
+#define PEER_OP_MODE3_SFT 2
+#define PEER_OP_MODE3_HI 3
+#define PEER_OP_MODE3_SZ 2
+#define PEER_HT_MODE3_MSK 0x00000030
+#define PEER_HT_MODE3_I_MSK 0xffffffcf
+#define PEER_HT_MODE3_SFT 4
+#define PEER_HT_MODE3_HI 5
+#define PEER_HT_MODE3_SZ 2
+#define PEER_MAC3_31_0_MSK 0xffffffff
+#define PEER_MAC3_31_0_I_MSK 0x00000000
+#define PEER_MAC3_31_0_SFT 0
+#define PEER_MAC3_31_0_HI 31
+#define PEER_MAC3_31_0_SZ 32
+#define PEER_MAC3_47_32_MSK 0x0000ffff
+#define PEER_MAC3_47_32_I_MSK 0xffff0000
+#define PEER_MAC3_47_32_SFT 0
+#define PEER_MAC3_47_32_HI 15
+#define PEER_MAC3_47_32_SZ 16
+#define TX_ACK_POLICY_3_0_MSK 0x00000003
+#define TX_ACK_POLICY_3_0_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_3_0_SFT 0
+#define TX_ACK_POLICY_3_0_HI 1
+#define TX_ACK_POLICY_3_0_SZ 2
+#define TX_SEQ_CTRL_3_0_MSK 0x00000fff
+#define TX_SEQ_CTRL_3_0_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_3_0_SFT 0
+#define TX_SEQ_CTRL_3_0_HI 11
+#define TX_SEQ_CTRL_3_0_SZ 12
+#define TX_ACK_POLICY_3_1_MSK 0x00000003
+#define TX_ACK_POLICY_3_1_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_3_1_SFT 0
+#define TX_ACK_POLICY_3_1_HI 1
+#define TX_ACK_POLICY_3_1_SZ 2
+#define TX_SEQ_CTRL_3_1_MSK 0x00000fff
+#define TX_SEQ_CTRL_3_1_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_3_1_SFT 0
+#define TX_SEQ_CTRL_3_1_HI 11
+#define TX_SEQ_CTRL_3_1_SZ 12
+#define TX_ACK_POLICY_3_2_MSK 0x00000003
+#define TX_ACK_POLICY_3_2_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_3_2_SFT 0
+#define TX_ACK_POLICY_3_2_HI 1
+#define TX_ACK_POLICY_3_2_SZ 2
+#define TX_SEQ_CTRL_3_2_MSK 0x00000fff
+#define TX_SEQ_CTRL_3_2_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_3_2_SFT 0
+#define TX_SEQ_CTRL_3_2_HI 11
+#define TX_SEQ_CTRL_3_2_SZ 12
+#define TX_ACK_POLICY_3_3_MSK 0x00000003
+#define TX_ACK_POLICY_3_3_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_3_3_SFT 0
+#define TX_ACK_POLICY_3_3_HI 1
+#define TX_ACK_POLICY_3_3_SZ 2
+#define TX_SEQ_CTRL_3_3_MSK 0x00000fff
+#define TX_SEQ_CTRL_3_3_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_3_3_SFT 0
+#define TX_SEQ_CTRL_3_3_HI 11
+#define TX_SEQ_CTRL_3_3_SZ 12
+#define TX_ACK_POLICY_3_4_MSK 0x00000003
+#define TX_ACK_POLICY_3_4_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_3_4_SFT 0
+#define TX_ACK_POLICY_3_4_HI 1
+#define TX_ACK_POLICY_3_4_SZ 2
+#define TX_SEQ_CTRL_3_4_MSK 0x00000fff
+#define TX_SEQ_CTRL_3_4_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_3_4_SFT 0
+#define TX_SEQ_CTRL_3_4_HI 11
+#define TX_SEQ_CTRL_3_4_SZ 12
+#define TX_ACK_POLICY_3_5_MSK 0x00000003
+#define TX_ACK_POLICY_3_5_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_3_5_SFT 0
+#define TX_ACK_POLICY_3_5_HI 1
+#define TX_ACK_POLICY_3_5_SZ 2
+#define TX_SEQ_CTRL_3_5_MSK 0x00000fff
+#define TX_SEQ_CTRL_3_5_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_3_5_SFT 0
+#define TX_SEQ_CTRL_3_5_HI 11
+#define TX_SEQ_CTRL_3_5_SZ 12
+#define TX_ACK_POLICY_3_6_MSK 0x00000003
+#define TX_ACK_POLICY_3_6_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_3_6_SFT 0
+#define TX_ACK_POLICY_3_6_HI 1
+#define TX_ACK_POLICY_3_6_SZ 2
+#define TX_SEQ_CTRL_3_6_MSK 0x00000fff
+#define TX_SEQ_CTRL_3_6_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_3_6_SFT 0
+#define TX_SEQ_CTRL_3_6_HI 11
+#define TX_SEQ_CTRL_3_6_SZ 12
+#define TX_ACK_POLICY_3_7_MSK 0x00000003
+#define TX_ACK_POLICY_3_7_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_3_7_SFT 0
+#define TX_ACK_POLICY_3_7_HI 1
+#define TX_ACK_POLICY_3_7_SZ 2
+#define TX_SEQ_CTRL_3_7_MSK 0x00000fff
+#define TX_SEQ_CTRL_3_7_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_3_7_SFT 0
+#define TX_SEQ_CTRL_3_7_HI 11
+#define TX_SEQ_CTRL_3_7_SZ 12
+#define VALID4_MSK 0x00000001
+#define VALID4_I_MSK 0xfffffffe
+#define VALID4_SFT 0
+#define VALID4_HI 0
+#define VALID4_SZ 1
+#define PEER_QOS_EN4_MSK 0x00000002
+#define PEER_QOS_EN4_I_MSK 0xfffffffd
+#define PEER_QOS_EN4_SFT 1
+#define PEER_QOS_EN4_HI 1
+#define PEER_QOS_EN4_SZ 1
+#define PEER_OP_MODE4_MSK 0x0000000c
+#define PEER_OP_MODE4_I_MSK 0xfffffff3
+#define PEER_OP_MODE4_SFT 2
+#define PEER_OP_MODE4_HI 3
+#define PEER_OP_MODE4_SZ 2
+#define PEER_HT_MODE4_MSK 0x00000030
+#define PEER_HT_MODE4_I_MSK 0xffffffcf
+#define PEER_HT_MODE4_SFT 4
+#define PEER_HT_MODE4_HI 5
+#define PEER_HT_MODE4_SZ 2
+#define PEER_MAC4_31_0_MSK 0xffffffff
+#define PEER_MAC4_31_0_I_MSK 0x00000000
+#define PEER_MAC4_31_0_SFT 0
+#define PEER_MAC4_31_0_HI 31
+#define PEER_MAC4_31_0_SZ 32
+#define PEER_MAC4_47_32_MSK 0x0000ffff
+#define PEER_MAC4_47_32_I_MSK 0xffff0000
+#define PEER_MAC4_47_32_SFT 0
+#define PEER_MAC4_47_32_HI 15
+#define PEER_MAC4_47_32_SZ 16
+#define TX_ACK_POLICY_4_0_MSK 0x00000003
+#define TX_ACK_POLICY_4_0_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_4_0_SFT 0
+#define TX_ACK_POLICY_4_0_HI 1
+#define TX_ACK_POLICY_4_0_SZ 2
+#define TX_SEQ_CTRL_4_0_MSK 0x00000fff
+#define TX_SEQ_CTRL_4_0_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_4_0_SFT 0
+#define TX_SEQ_CTRL_4_0_HI 11
+#define TX_SEQ_CTRL_4_0_SZ 12
+#define TX_ACK_POLICY_4_1_MSK 0x00000003
+#define TX_ACK_POLICY_4_1_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_4_1_SFT 0
+#define TX_ACK_POLICY_4_1_HI 1
+#define TX_ACK_POLICY_4_1_SZ 2
+#define TX_SEQ_CTRL_4_1_MSK 0x00000fff
+#define TX_SEQ_CTRL_4_1_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_4_1_SFT 0
+#define TX_SEQ_CTRL_4_1_HI 11
+#define TX_SEQ_CTRL_4_1_SZ 12
+#define TX_ACK_POLICY_4_2_MSK 0x00000003
+#define TX_ACK_POLICY_4_2_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_4_2_SFT 0
+#define TX_ACK_POLICY_4_2_HI 1
+#define TX_ACK_POLICY_4_2_SZ 2
+#define TX_SEQ_CTRL_4_2_MSK 0x00000fff
+#define TX_SEQ_CTRL_4_2_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_4_2_SFT 0
+#define TX_SEQ_CTRL_4_2_HI 11
+#define TX_SEQ_CTRL_4_2_SZ 12
+#define TX_ACK_POLICY_4_3_MSK 0x00000003
+#define TX_ACK_POLICY_4_3_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_4_3_SFT 0
+#define TX_ACK_POLICY_4_3_HI 1
+#define TX_ACK_POLICY_4_3_SZ 2
+#define TX_SEQ_CTRL_4_3_MSK 0x00000fff
+#define TX_SEQ_CTRL_4_3_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_4_3_SFT 0
+#define TX_SEQ_CTRL_4_3_HI 11
+#define TX_SEQ_CTRL_4_3_SZ 12
+#define TX_ACK_POLICY_4_4_MSK 0x00000003
+#define TX_ACK_POLICY_4_4_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_4_4_SFT 0
+#define TX_ACK_POLICY_4_4_HI 1
+#define TX_ACK_POLICY_4_4_SZ 2
+#define TX_SEQ_CTRL_4_4_MSK 0x00000fff
+#define TX_SEQ_CTRL_4_4_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_4_4_SFT 0
+#define TX_SEQ_CTRL_4_4_HI 11
+#define TX_SEQ_CTRL_4_4_SZ 12
+#define TX_ACK_POLICY_4_5_MSK 0x00000003
+#define TX_ACK_POLICY_4_5_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_4_5_SFT 0
+#define TX_ACK_POLICY_4_5_HI 1
+#define TX_ACK_POLICY_4_5_SZ 2
+#define TX_SEQ_CTRL_4_5_MSK 0x00000fff
+#define TX_SEQ_CTRL_4_5_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_4_5_SFT 0
+#define TX_SEQ_CTRL_4_5_HI 11
+#define TX_SEQ_CTRL_4_5_SZ 12
+#define TX_ACK_POLICY_4_6_MSK 0x00000003
+#define TX_ACK_POLICY_4_6_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_4_6_SFT 0
+#define TX_ACK_POLICY_4_6_HI 1
+#define TX_ACK_POLICY_4_6_SZ 2
+#define TX_SEQ_CTRL_4_6_MSK 0x00000fff
+#define TX_SEQ_CTRL_4_6_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_4_6_SFT 0
+#define TX_SEQ_CTRL_4_6_HI 11
+#define TX_SEQ_CTRL_4_6_SZ 12
+#define TX_ACK_POLICY_4_7_MSK 0x00000003
+#define TX_ACK_POLICY_4_7_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_4_7_SFT 0
+#define TX_ACK_POLICY_4_7_HI 1
+#define TX_ACK_POLICY_4_7_SZ 2
+#define TX_SEQ_CTRL_4_7_MSK 0x00000fff
+#define TX_SEQ_CTRL_4_7_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_4_7_SFT 0
+#define TX_SEQ_CTRL_4_7_HI 11
+#define TX_SEQ_CTRL_4_7_SZ 12
+#define VALID5_MSK 0x00000001
+#define VALID5_I_MSK 0xfffffffe
+#define VALID5_SFT 0
+#define VALID5_HI 0
+#define VALID5_SZ 1
+#define PEER_QOS_EN5_MSK 0x00000002
+#define PEER_QOS_EN5_I_MSK 0xfffffffd
+#define PEER_QOS_EN5_SFT 1
+#define PEER_QOS_EN5_HI 1
+#define PEER_QOS_EN5_SZ 1
+#define PEER_OP_MODE5_MSK 0x0000000c
+#define PEER_OP_MODE5_I_MSK 0xfffffff3
+#define PEER_OP_MODE5_SFT 2
+#define PEER_OP_MODE5_HI 3
+#define PEER_OP_MODE5_SZ 2
+#define PEER_HT_MODE5_MSK 0x00000030
+#define PEER_HT_MODE5_I_MSK 0xffffffcf
+#define PEER_HT_MODE5_SFT 4
+#define PEER_HT_MODE5_HI 5
+#define PEER_HT_MODE5_SZ 2
+#define PEER_MAC5_31_0_MSK 0xffffffff
+#define PEER_MAC5_31_0_I_MSK 0x00000000
+#define PEER_MAC5_31_0_SFT 0
+#define PEER_MAC5_31_0_HI 31
+#define PEER_MAC5_31_0_SZ 32
+#define PEER_MAC5_47_32_MSK 0x0000ffff
+#define PEER_MAC5_47_32_I_MSK 0xffff0000
+#define PEER_MAC5_47_32_SFT 0
+#define PEER_MAC5_47_32_HI 15
+#define PEER_MAC5_47_32_SZ 16
+#define TX_ACK_POLICY_5_0_MSK 0x00000003
+#define TX_ACK_POLICY_5_0_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_5_0_SFT 0
+#define TX_ACK_POLICY_5_0_HI 1
+#define TX_ACK_POLICY_5_0_SZ 2
+#define TX_SEQ_CTRL_5_0_MSK 0x00000fff
+#define TX_SEQ_CTRL_5_0_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_5_0_SFT 0
+#define TX_SEQ_CTRL_5_0_HI 11
+#define TX_SEQ_CTRL_5_0_SZ 12
+#define TX_ACK_POLICY_5_1_MSK 0x00000003
+#define TX_ACK_POLICY_5_1_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_5_1_SFT 0
+#define TX_ACK_POLICY_5_1_HI 1
+#define TX_ACK_POLICY_5_1_SZ 2
+#define TX_SEQ_CTRL_5_1_MSK 0x00000fff
+#define TX_SEQ_CTRL_5_1_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_5_1_SFT 0
+#define TX_SEQ_CTRL_5_1_HI 11
+#define TX_SEQ_CTRL_5_1_SZ 12
+#define TX_ACK_POLICY_5_2_MSK 0x00000003
+#define TX_ACK_POLICY_5_2_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_5_2_SFT 0
+#define TX_ACK_POLICY_5_2_HI 1
+#define TX_ACK_POLICY_5_2_SZ 2
+#define TX_SEQ_CTRL_5_2_MSK 0x00000fff
+#define TX_SEQ_CTRL_5_2_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_5_2_SFT 0
+#define TX_SEQ_CTRL_5_2_HI 11
+#define TX_SEQ_CTRL_5_2_SZ 12
+#define TX_ACK_POLICY_5_3_MSK 0x00000003
+#define TX_ACK_POLICY_5_3_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_5_3_SFT 0
+#define TX_ACK_POLICY_5_3_HI 1
+#define TX_ACK_POLICY_5_3_SZ 2
+#define TX_SEQ_CTRL_5_3_MSK 0x00000fff
+#define TX_SEQ_CTRL_5_3_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_5_3_SFT 0
+#define TX_SEQ_CTRL_5_3_HI 11
+#define TX_SEQ_CTRL_5_3_SZ 12
+#define TX_ACK_POLICY_5_4_MSK 0x00000003
+#define TX_ACK_POLICY_5_4_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_5_4_SFT 0
+#define TX_ACK_POLICY_5_4_HI 1
+#define TX_ACK_POLICY_5_4_SZ 2
+#define TX_SEQ_CTRL_5_4_MSK 0x00000fff
+#define TX_SEQ_CTRL_5_4_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_5_4_SFT 0
+#define TX_SEQ_CTRL_5_4_HI 11
+#define TX_SEQ_CTRL_5_4_SZ 12
+#define TX_ACK_POLICY_5_5_MSK 0x00000003
+#define TX_ACK_POLICY_5_5_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_5_5_SFT 0
+#define TX_ACK_POLICY_5_5_HI 1
+#define TX_ACK_POLICY_5_5_SZ 2
+#define TX_SEQ_CTRL_5_5_MSK 0x00000fff
+#define TX_SEQ_CTRL_5_5_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_5_5_SFT 0
+#define TX_SEQ_CTRL_5_5_HI 11
+#define TX_SEQ_CTRL_5_5_SZ 12
+#define TX_ACK_POLICY_5_6_MSK 0x00000003
+#define TX_ACK_POLICY_5_6_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_5_6_SFT 0
+#define TX_ACK_POLICY_5_6_HI 1
+#define TX_ACK_POLICY_5_6_SZ 2
+#define TX_SEQ_CTRL_5_6_MSK 0x00000fff
+#define TX_SEQ_CTRL_5_6_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_5_6_SFT 0
+#define TX_SEQ_CTRL_5_6_HI 11
+#define TX_SEQ_CTRL_5_6_SZ 12
+#define TX_ACK_POLICY_5_7_MSK 0x00000003
+#define TX_ACK_POLICY_5_7_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_5_7_SFT 0
+#define TX_ACK_POLICY_5_7_HI 1
+#define TX_ACK_POLICY_5_7_SZ 2
+#define TX_SEQ_CTRL_5_7_MSK 0x00000fff
+#define TX_SEQ_CTRL_5_7_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_5_7_SFT 0
+#define TX_SEQ_CTRL_5_7_HI 11
+#define TX_SEQ_CTRL_5_7_SZ 12
+#define VALID6_MSK 0x00000001
+#define VALID6_I_MSK 0xfffffffe
+#define VALID6_SFT 0
+#define VALID6_HI 0
+#define VALID6_SZ 1
+#define PEER_QOS_EN6_MSK 0x00000002
+#define PEER_QOS_EN6_I_MSK 0xfffffffd
+#define PEER_QOS_EN6_SFT 1
+#define PEER_QOS_EN6_HI 1
+#define PEER_QOS_EN6_SZ 1
+#define PEER_OP_MODE6_MSK 0x0000000c
+#define PEER_OP_MODE6_I_MSK 0xfffffff3
+#define PEER_OP_MODE6_SFT 2
+#define PEER_OP_MODE6_HI 3
+#define PEER_OP_MODE6_SZ 2
+#define PEER_HT_MODE6_MSK 0x00000030
+#define PEER_HT_MODE6_I_MSK 0xffffffcf
+#define PEER_HT_MODE6_SFT 4
+#define PEER_HT_MODE6_HI 5
+#define PEER_HT_MODE6_SZ 2
+#define PEER_MAC6_31_0_MSK 0xffffffff
+#define PEER_MAC6_31_0_I_MSK 0x00000000
+#define PEER_MAC6_31_0_SFT 0
+#define PEER_MAC6_31_0_HI 31
+#define PEER_MAC6_31_0_SZ 32
+#define PEER_MAC6_47_32_MSK 0x0000ffff
+#define PEER_MAC6_47_32_I_MSK 0xffff0000
+#define PEER_MAC6_47_32_SFT 0
+#define PEER_MAC6_47_32_HI 15
+#define PEER_MAC6_47_32_SZ 16
+#define TX_ACK_POLICY_6_0_MSK 0x00000003
+#define TX_ACK_POLICY_6_0_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_6_0_SFT 0
+#define TX_ACK_POLICY_6_0_HI 1
+#define TX_ACK_POLICY_6_0_SZ 2
+#define TX_SEQ_CTRL_6_0_MSK 0x00000fff
+#define TX_SEQ_CTRL_6_0_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_6_0_SFT 0
+#define TX_SEQ_CTRL_6_0_HI 11
+#define TX_SEQ_CTRL_6_0_SZ 12
+#define TX_ACK_POLICY_6_1_MSK 0x00000003
+#define TX_ACK_POLICY_6_1_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_6_1_SFT 0
+#define TX_ACK_POLICY_6_1_HI 1
+#define TX_ACK_POLICY_6_1_SZ 2
+#define TX_SEQ_CTRL_6_1_MSK 0x00000fff
+#define TX_SEQ_CTRL_6_1_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_6_1_SFT 0
+#define TX_SEQ_CTRL_6_1_HI 11
+#define TX_SEQ_CTRL_6_1_SZ 12
+#define TX_ACK_POLICY_6_2_MSK 0x00000003
+#define TX_ACK_POLICY_6_2_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_6_2_SFT 0
+#define TX_ACK_POLICY_6_2_HI 1
+#define TX_ACK_POLICY_6_2_SZ 2
+#define TX_SEQ_CTRL_6_2_MSK 0x00000fff
+#define TX_SEQ_CTRL_6_2_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_6_2_SFT 0
+#define TX_SEQ_CTRL_6_2_HI 11
+#define TX_SEQ_CTRL_6_2_SZ 12
+#define TX_ACK_POLICY_6_3_MSK 0x00000003
+#define TX_ACK_POLICY_6_3_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_6_3_SFT 0
+#define TX_ACK_POLICY_6_3_HI 1
+#define TX_ACK_POLICY_6_3_SZ 2
+#define TX_SEQ_CTRL_6_3_MSK 0x00000fff
+#define TX_SEQ_CTRL_6_3_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_6_3_SFT 0
+#define TX_SEQ_CTRL_6_3_HI 11
+#define TX_SEQ_CTRL_6_3_SZ 12
+#define TX_ACK_POLICY_6_4_MSK 0x00000003
+#define TX_ACK_POLICY_6_4_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_6_4_SFT 0
+#define TX_ACK_POLICY_6_4_HI 1
+#define TX_ACK_POLICY_6_4_SZ 2
+#define TX_SEQ_CTRL_6_4_MSK 0x00000fff
+#define TX_SEQ_CTRL_6_4_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_6_4_SFT 0
+#define TX_SEQ_CTRL_6_4_HI 11
+#define TX_SEQ_CTRL_6_4_SZ 12
+#define TX_ACK_POLICY_6_5_MSK 0x00000003
+#define TX_ACK_POLICY_6_5_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_6_5_SFT 0
+#define TX_ACK_POLICY_6_5_HI 1
+#define TX_ACK_POLICY_6_5_SZ 2
+#define TX_SEQ_CTRL_6_5_MSK 0x00000fff
+#define TX_SEQ_CTRL_6_5_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_6_5_SFT 0
+#define TX_SEQ_CTRL_6_5_HI 11
+#define TX_SEQ_CTRL_6_5_SZ 12
+#define TX_ACK_POLICY_6_6_MSK 0x00000003
+#define TX_ACK_POLICY_6_6_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_6_6_SFT 0
+#define TX_ACK_POLICY_6_6_HI 1
+#define TX_ACK_POLICY_6_6_SZ 2
+#define TX_SEQ_CTRL_6_6_MSK 0x00000fff
+#define TX_SEQ_CTRL_6_6_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_6_6_SFT 0
+#define TX_SEQ_CTRL_6_6_HI 11
+#define TX_SEQ_CTRL_6_6_SZ 12
+#define TX_ACK_POLICY_6_7_MSK 0x00000003
+#define TX_ACK_POLICY_6_7_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_6_7_SFT 0
+#define TX_ACK_POLICY_6_7_HI 1
+#define TX_ACK_POLICY_6_7_SZ 2
+#define TX_SEQ_CTRL_6_7_MSK 0x00000fff
+#define TX_SEQ_CTRL_6_7_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_6_7_SFT 0
+#define TX_SEQ_CTRL_6_7_HI 11
+#define TX_SEQ_CTRL_6_7_SZ 12
+#define VALID7_MSK 0x00000001
+#define VALID7_I_MSK 0xfffffffe
+#define VALID7_SFT 0
+#define VALID7_HI 0
+#define VALID7_SZ 1
+#define PEER_QOS_EN7_MSK 0x00000002
+#define PEER_QOS_EN7_I_MSK 0xfffffffd
+#define PEER_QOS_EN7_SFT 1
+#define PEER_QOS_EN7_HI 1
+#define PEER_QOS_EN7_SZ 1
+#define PEER_OP_MODE7_MSK 0x0000000c
+#define PEER_OP_MODE7_I_MSK 0xfffffff3
+#define PEER_OP_MODE7_SFT 2
+#define PEER_OP_MODE7_HI 3
+#define PEER_OP_MODE7_SZ 2
+#define PEER_HT_MODE7_MSK 0x00000030
+#define PEER_HT_MODE7_I_MSK 0xffffffcf
+#define PEER_HT_MODE7_SFT 4
+#define PEER_HT_MODE7_HI 5
+#define PEER_HT_MODE7_SZ 2
+#define PEER_MAC7_31_0_MSK 0xffffffff
+#define PEER_MAC7_31_0_I_MSK 0x00000000
+#define PEER_MAC7_31_0_SFT 0
+#define PEER_MAC7_31_0_HI 31
+#define PEER_MAC7_31_0_SZ 32
+#define PEER_MAC7_47_32_MSK 0x0000ffff
+#define PEER_MAC7_47_32_I_MSK 0xffff0000
+#define PEER_MAC7_47_32_SFT 0
+#define PEER_MAC7_47_32_HI 15
+#define PEER_MAC7_47_32_SZ 16
+#define TX_ACK_POLICY_7_0_MSK 0x00000003
+#define TX_ACK_POLICY_7_0_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_7_0_SFT 0
+#define TX_ACK_POLICY_7_0_HI 1
+#define TX_ACK_POLICY_7_0_SZ 2
+#define TX_SEQ_CTRL_7_0_MSK 0x00000fff
+#define TX_SEQ_CTRL_7_0_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_7_0_SFT 0
+#define TX_SEQ_CTRL_7_0_HI 11
+#define TX_SEQ_CTRL_7_0_SZ 12
+#define TX_ACK_POLICY_7_1_MSK 0x00000003
+#define TX_ACK_POLICY_7_1_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_7_1_SFT 0
+#define TX_ACK_POLICY_7_1_HI 1
+#define TX_ACK_POLICY_7_1_SZ 2
+#define TX_SEQ_CTRL_7_1_MSK 0x00000fff
+#define TX_SEQ_CTRL_7_1_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_7_1_SFT 0
+#define TX_SEQ_CTRL_7_1_HI 11
+#define TX_SEQ_CTRL_7_1_SZ 12
+#define TX_ACK_POLICY_7_2_MSK 0x00000003
+#define TX_ACK_POLICY_7_2_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_7_2_SFT 0
+#define TX_ACK_POLICY_7_2_HI 1
+#define TX_ACK_POLICY_7_2_SZ 2
+#define TX_SEQ_CTRL_7_2_MSK 0x00000fff
+#define TX_SEQ_CTRL_7_2_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_7_2_SFT 0
+#define TX_SEQ_CTRL_7_2_HI 11
+#define TX_SEQ_CTRL_7_2_SZ 12
+#define TX_ACK_POLICY_7_3_MSK 0x00000003
+#define TX_ACK_POLICY_7_3_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_7_3_SFT 0
+#define TX_ACK_POLICY_7_3_HI 1
+#define TX_ACK_POLICY_7_3_SZ 2
+#define TX_SEQ_CTRL_7_3_MSK 0x00000fff
+#define TX_SEQ_CTRL_7_3_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_7_3_SFT 0
+#define TX_SEQ_CTRL_7_3_HI 11
+#define TX_SEQ_CTRL_7_3_SZ 12
+#define TX_ACK_POLICY_7_4_MSK 0x00000003
+#define TX_ACK_POLICY_7_4_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_7_4_SFT 0
+#define TX_ACK_POLICY_7_4_HI 1
+#define TX_ACK_POLICY_7_4_SZ 2
+#define TX_SEQ_CTRL_7_4_MSK 0x00000fff
+#define TX_SEQ_CTRL_7_4_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_7_4_SFT 0
+#define TX_SEQ_CTRL_7_4_HI 11
+#define TX_SEQ_CTRL_7_4_SZ 12
+#define TX_ACK_POLICY_7_5_MSK 0x00000003
+#define TX_ACK_POLICY_7_5_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_7_5_SFT 0
+#define TX_ACK_POLICY_7_5_HI 1
+#define TX_ACK_POLICY_7_5_SZ 2
+#define TX_SEQ_CTRL_7_5_MSK 0x00000fff
+#define TX_SEQ_CTRL_7_5_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_7_5_SFT 0
+#define TX_SEQ_CTRL_7_5_HI 11
+#define TX_SEQ_CTRL_7_5_SZ 12
+#define TX_ACK_POLICY_7_6_MSK 0x00000003
+#define TX_ACK_POLICY_7_6_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_7_6_SFT 0
+#define TX_ACK_POLICY_7_6_HI 1
+#define TX_ACK_POLICY_7_6_SZ 2
+#define TX_SEQ_CTRL_7_6_MSK 0x00000fff
+#define TX_SEQ_CTRL_7_6_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_7_6_SFT 0
+#define TX_SEQ_CTRL_7_6_HI 11
+#define TX_SEQ_CTRL_7_6_SZ 12
+#define TX_ACK_POLICY_7_7_MSK 0x00000003
+#define TX_ACK_POLICY_7_7_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_7_7_SFT 0
+#define TX_ACK_POLICY_7_7_HI 1
+#define TX_ACK_POLICY_7_7_SZ 2
+#define TX_SEQ_CTRL_7_7_MSK 0x00000fff
+#define TX_SEQ_CTRL_7_7_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_7_7_SFT 0
+#define TX_SEQ_CTRL_7_7_HI 11
+#define TX_SEQ_CTRL_7_7_SZ 12
+#define RG_GEMINIA_HW_PINSEL_MSK 0x00000001
+#define RG_GEMINIA_HW_PINSEL_I_MSK 0xfffffffe
+#define RG_GEMINIA_HW_PINSEL_SFT 0
+#define RG_GEMINIA_HW_PINSEL_HI 0
+#define RG_GEMINIA_HW_PINSEL_SZ 1
+#define RG_GEMINIA_HS_3WIRE_MANUAL_MSK 0x00000002
+#define RG_GEMINIA_HS_3WIRE_MANUAL_I_MSK 0xfffffffd
+#define RG_GEMINIA_HS_3WIRE_MANUAL_SFT 1
+#define RG_GEMINIA_HS_3WIRE_MANUAL_HI 1
+#define RG_GEMINIA_HS_3WIRE_MANUAL_SZ 1
+#define RG_GEMINIA_MODE_MANUAL_MSK 0x00000004
+#define RG_GEMINIA_MODE_MANUAL_I_MSK 0xfffffffb
+#define RG_GEMINIA_MODE_MANUAL_SFT 2
+#define RG_GEMINIA_MODE_MANUAL_HI 2
+#define RG_GEMINIA_MODE_MANUAL_SZ 1
+#define RG_GEMINIA_RX_GAIN_MANUAL_MSK 0x00000008
+#define RG_GEMINIA_RX_GAIN_MANUAL_I_MSK 0xfffffff7
+#define RG_GEMINIA_RX_GAIN_MANUAL_SFT 3
+#define RG_GEMINIA_RX_GAIN_MANUAL_HI 3
+#define RG_GEMINIA_RX_GAIN_MANUAL_SZ 1
+#define RG_GEMINIA_TX_GAIN_MANUAL_MSK 0x00000010
+#define RG_GEMINIA_TX_GAIN_MANUAL_I_MSK 0xffffffef
+#define RG_GEMINIA_TX_GAIN_MANUAL_SFT 4
+#define RG_GEMINIA_TX_GAIN_MANUAL_HI 4
+#define RG_GEMINIA_TX_GAIN_MANUAL_SZ 1
+#define RG_GEMINIA_TXGAIN_PHYCTRL_MSK 0x00000020
+#define RG_GEMINIA_TXGAIN_PHYCTRL_I_MSK 0xffffffdf
+#define RG_GEMINIA_TXGAIN_PHYCTRL_SFT 5
+#define RG_GEMINIA_TXGAIN_PHYCTRL_HI 5
+#define RG_GEMINIA_TXGAIN_PHYCTRL_SZ 1
+#define RG_GEMINIA_RX_AGC_MSK 0x00000040
+#define RG_GEMINIA_RX_AGC_I_MSK 0xffffffbf
+#define RG_GEMINIA_RX_AGC_SFT 6
+#define RG_GEMINIA_RX_AGC_HI 6
+#define RG_GEMINIA_RX_AGC_SZ 1
+#define RG_GEMINIA_MODE_MSK 0x00000700
+#define RG_GEMINIA_MODE_I_MSK 0xfffff8ff
+#define RG_GEMINIA_MODE_SFT 8
+#define RG_GEMINIA_MODE_HI 10
+#define RG_GEMINIA_MODE_SZ 3
+#define RG_GEMINIA_CAL_INDEX_MSK 0x00007000
+#define RG_GEMINIA_CAL_INDEX_I_MSK 0xffff8fff
+#define RG_GEMINIA_CAL_INDEX_SFT 12
+#define RG_GEMINIA_CAL_INDEX_HI 14
+#define RG_GEMINIA_CAL_INDEX_SZ 3
+#define RG_GEMINIA_RFG_MSK 0x00030000
+#define RG_GEMINIA_RFG_I_MSK 0xfffcffff
+#define RG_GEMINIA_RFG_SFT 16
+#define RG_GEMINIA_RFG_HI 17
+#define RG_GEMINIA_RFG_SZ 2
+#define RG_GEMINIA_PGAG_MSK 0x003c0000
+#define RG_GEMINIA_PGAG_I_MSK 0xffc3ffff
+#define RG_GEMINIA_PGAG_SFT 18
+#define RG_GEMINIA_PGAG_HI 21
+#define RG_GEMINIA_PGAG_SZ 4
+#define RG_GEMINIA_TX_GAIN_MSK 0x7f000000
+#define RG_GEMINIA_TX_GAIN_I_MSK 0x80ffffff
+#define RG_GEMINIA_TX_GAIN_SFT 24
+#define RG_GEMINIA_TX_GAIN_HI 30
+#define RG_GEMINIA_TX_GAIN_SZ 7
+#define RG_GEMINIA_TX_TRSW_MANUAL_MSK 0x00000001
+#define RG_GEMINIA_TX_TRSW_MANUAL_I_MSK 0xfffffffe
+#define RG_GEMINIA_TX_TRSW_MANUAL_SFT 0
+#define RG_GEMINIA_TX_TRSW_MANUAL_HI 0
+#define RG_GEMINIA_TX_TRSW_MANUAL_SZ 1
+#define RG_GEMINIA_EN_TX_TRSW_MSK 0x00000002
+#define RG_GEMINIA_EN_TX_TRSW_I_MSK 0xfffffffd
+#define RG_GEMINIA_EN_TX_TRSW_SFT 1
+#define RG_GEMINIA_EN_TX_TRSW_HI 1
+#define RG_GEMINIA_EN_TX_TRSW_SZ 1
+#define RG_GEMINIA_RX_LNA_MANUAL_MSK 0x00000004
+#define RG_GEMINIA_RX_LNA_MANUAL_I_MSK 0xfffffffb
+#define RG_GEMINIA_RX_LNA_MANUAL_SFT 2
+#define RG_GEMINIA_RX_LNA_MANUAL_HI 2
+#define RG_GEMINIA_RX_LNA_MANUAL_SZ 1
+#define RG_GEMINIA_EN_RX_LNA_MSK 0x00000008
+#define RG_GEMINIA_EN_RX_LNA_I_MSK 0xfffffff7
+#define RG_GEMINIA_EN_RX_LNA_SFT 3
+#define RG_GEMINIA_EN_RX_LNA_HI 3
+#define RG_GEMINIA_EN_RX_LNA_SZ 1
+#define RG_GEMINIA_RX_MIXER_MANUAL_MSK 0x00000010
+#define RG_GEMINIA_RX_MIXER_MANUAL_I_MSK 0xffffffef
+#define RG_GEMINIA_RX_MIXER_MANUAL_SFT 4
+#define RG_GEMINIA_RX_MIXER_MANUAL_HI 4
+#define RG_GEMINIA_RX_MIXER_MANUAL_SZ 1
+#define RG_GEMINIA_EN_RX_MIXER_MSK 0x00000020
+#define RG_GEMINIA_EN_RX_MIXER_I_MSK 0xffffffdf
+#define RG_GEMINIA_EN_RX_MIXER_SFT 5
+#define RG_GEMINIA_EN_RX_MIXER_HI 5
+#define RG_GEMINIA_EN_RX_MIXER_SZ 1
+#define RG_GEMINIA_RX_DIV2_MANUAL_MSK 0x00000040
+#define RG_GEMINIA_RX_DIV2_MANUAL_I_MSK 0xffffffbf
+#define RG_GEMINIA_RX_DIV2_MANUAL_SFT 6
+#define RG_GEMINIA_RX_DIV2_MANUAL_HI 6
+#define RG_GEMINIA_RX_DIV2_MANUAL_SZ 1
+#define RG_GEMINIA_EN_RX_DIV2_MSK 0x00000080
+#define RG_GEMINIA_EN_RX_DIV2_I_MSK 0xffffff7f
+#define RG_GEMINIA_EN_RX_DIV2_SFT 7
+#define RG_GEMINIA_EN_RX_DIV2_HI 7
+#define RG_GEMINIA_EN_RX_DIV2_SZ 1
+#define RG_GEMINIA_RX_LOBUF_MANUAL_MSK 0x00000100
+#define RG_GEMINIA_RX_LOBUF_MANUAL_I_MSK 0xfffffeff
+#define RG_GEMINIA_RX_LOBUF_MANUAL_SFT 8
+#define RG_GEMINIA_RX_LOBUF_MANUAL_HI 8
+#define RG_GEMINIA_RX_LOBUF_MANUAL_SZ 1
+#define RG_GEMINIA_EN_RX_LOBUF_MSK 0x00000200
+#define RG_GEMINIA_EN_RX_LOBUF_I_MSK 0xfffffdff
+#define RG_GEMINIA_EN_RX_LOBUF_SFT 9
+#define RG_GEMINIA_EN_RX_LOBUF_HI 9
+#define RG_GEMINIA_EN_RX_LOBUF_SZ 1
+#define RG_GEMINIA_RX_TZ_MANUAL_MSK 0x00000400
+#define RG_GEMINIA_RX_TZ_MANUAL_I_MSK 0xfffffbff
+#define RG_GEMINIA_RX_TZ_MANUAL_SFT 10
+#define RG_GEMINIA_RX_TZ_MANUAL_HI 10
+#define RG_GEMINIA_RX_TZ_MANUAL_SZ 1
+#define RG_GEMINIA_EN_RX_TZ_MSK 0x00000800
+#define RG_GEMINIA_EN_RX_TZ_I_MSK 0xfffff7ff
+#define RG_GEMINIA_EN_RX_TZ_SFT 11
+#define RG_GEMINIA_EN_RX_TZ_HI 11
+#define RG_GEMINIA_EN_RX_TZ_SZ 1
+#define RG_GEMINIA_RX_FILTER_MANUAL_MSK 0x00001000
+#define RG_GEMINIA_RX_FILTER_MANUAL_I_MSK 0xffffefff
+#define RG_GEMINIA_RX_FILTER_MANUAL_SFT 12
+#define RG_GEMINIA_RX_FILTER_MANUAL_HI 12
+#define RG_GEMINIA_RX_FILTER_MANUAL_SZ 1
+#define RG_GEMINIA_EN_RX_FILTER_MSK 0x00002000
+#define RG_GEMINIA_EN_RX_FILTER_I_MSK 0xffffdfff
+#define RG_GEMINIA_EN_RX_FILTER_SFT 13
+#define RG_GEMINIA_EN_RX_FILTER_HI 13
+#define RG_GEMINIA_EN_RX_FILTER_SZ 1
+#define RG_GEMINIA_RX_ADC_MANUAL_MSK 0x00004000
+#define RG_GEMINIA_RX_ADC_MANUAL_I_MSK 0xffffbfff
+#define RG_GEMINIA_RX_ADC_MANUAL_SFT 14
+#define RG_GEMINIA_RX_ADC_MANUAL_HI 14
+#define RG_GEMINIA_RX_ADC_MANUAL_SZ 1
+#define RG_GEMINIA_EN_RX_ADC_MSK 0x00008000
+#define RG_GEMINIA_EN_RX_ADC_I_MSK 0xffff7fff
+#define RG_GEMINIA_EN_RX_ADC_SFT 15
+#define RG_GEMINIA_EN_RX_ADC_HI 15
+#define RG_GEMINIA_EN_RX_ADC_SZ 1
+#define RG_GEMINIA_RX_RSSI_MANUAL_MSK 0x00010000
+#define RG_GEMINIA_RX_RSSI_MANUAL_I_MSK 0xfffeffff
+#define RG_GEMINIA_RX_RSSI_MANUAL_SFT 16
+#define RG_GEMINIA_RX_RSSI_MANUAL_HI 16
+#define RG_GEMINIA_RX_RSSI_MANUAL_SZ 1
+#define RG_GEMINIA_EN_RX_RSSI_MSK 0x00020000
+#define RG_GEMINIA_EN_RX_RSSI_I_MSK 0xfffdffff
+#define RG_GEMINIA_EN_RX_RSSI_SFT 17
+#define RG_GEMINIA_EN_RX_RSSI_HI 17
+#define RG_GEMINIA_EN_RX_RSSI_SZ 1
+#define RG_GEMINIA_TX_PA_MANUAL_MSK 0x00040000
+#define RG_GEMINIA_TX_PA_MANUAL_I_MSK 0xfffbffff
+#define RG_GEMINIA_TX_PA_MANUAL_SFT 18
+#define RG_GEMINIA_TX_PA_MANUAL_HI 18
+#define RG_GEMINIA_TX_PA_MANUAL_SZ 1
+#define RG_GEMINIA_EN_TX_PA_MSK 0x00080000
+#define RG_GEMINIA_EN_TX_PA_I_MSK 0xfff7ffff
+#define RG_GEMINIA_EN_TX_PA_SFT 19
+#define RG_GEMINIA_EN_TX_PA_HI 19
+#define RG_GEMINIA_EN_TX_PA_SZ 1
+#define RG_GEMINIA_TX_MOD_MANUAL_MSK 0x00100000
+#define RG_GEMINIA_TX_MOD_MANUAL_I_MSK 0xffefffff
+#define RG_GEMINIA_TX_MOD_MANUAL_SFT 20
+#define RG_GEMINIA_TX_MOD_MANUAL_HI 20
+#define RG_GEMINIA_TX_MOD_MANUAL_SZ 1
+#define RG_GEMINIA_EN_TX_MOD_MSK 0x00200000
+#define RG_GEMINIA_EN_TX_MOD_I_MSK 0xffdfffff
+#define RG_GEMINIA_EN_TX_MOD_SFT 21
+#define RG_GEMINIA_EN_TX_MOD_HI 21
+#define RG_GEMINIA_EN_TX_MOD_SZ 1
+#define RG_GEMINIA_TX_DAC_MANUAL_MSK 0x00400000
+#define RG_GEMINIA_TX_DAC_MANUAL_I_MSK 0xffbfffff
+#define RG_GEMINIA_TX_DAC_MANUAL_SFT 22
+#define RG_GEMINIA_TX_DAC_MANUAL_HI 22
+#define RG_GEMINIA_TX_DAC_MANUAL_SZ 1
+#define RG_GEMINIA_EN_TX_DAC_MSK 0x00800000
+#define RG_GEMINIA_EN_TX_DAC_I_MSK 0xff7fffff
+#define RG_GEMINIA_EN_TX_DAC_SFT 23
+#define RG_GEMINIA_EN_TX_DAC_HI 23
+#define RG_GEMINIA_EN_TX_DAC_SZ 1
+#define RG_GEMINIA_TX_DIV2_MANUAL_MSK 0x01000000
+#define RG_GEMINIA_TX_DIV2_MANUAL_I_MSK 0xfeffffff
+#define RG_GEMINIA_TX_DIV2_MANUAL_SFT 24
+#define RG_GEMINIA_TX_DIV2_MANUAL_HI 24
+#define RG_GEMINIA_TX_DIV2_MANUAL_SZ 1
+#define RG_GEMINIA_EN_TX_DIV2_MSK 0x02000000
+#define RG_GEMINIA_EN_TX_DIV2_I_MSK 0xfdffffff
+#define RG_GEMINIA_EN_TX_DIV2_SFT 25
+#define RG_GEMINIA_EN_TX_DIV2_HI 25
+#define RG_GEMINIA_EN_TX_DIV2_SZ 1
+#define RG_GEMINIA_TX_DIV2_BUF_MANUAL_MSK 0x04000000
+#define RG_GEMINIA_TX_DIV2_BUF_MANUAL_I_MSK 0xfbffffff
+#define RG_GEMINIA_TX_DIV2_BUF_MANUAL_SFT 26
+#define RG_GEMINIA_TX_DIV2_BUF_MANUAL_HI 26
+#define RG_GEMINIA_TX_DIV2_BUF_MANUAL_SZ 1
+#define RG_GEMINIA_EN_TX_DIV2_BUF_MSK 0x08000000
+#define RG_GEMINIA_EN_TX_DIV2_BUF_I_MSK 0xf7ffffff
+#define RG_GEMINIA_EN_TX_DIV2_BUF_SFT 27
+#define RG_GEMINIA_EN_TX_DIV2_BUF_HI 27
+#define RG_GEMINIA_EN_TX_DIV2_BUF_SZ 1
+#define RG_GEMINIA_TX_BT_PA_MANUAL_MSK 0x10000000
+#define RG_GEMINIA_TX_BT_PA_MANUAL_I_MSK 0xefffffff
+#define RG_GEMINIA_TX_BT_PA_MANUAL_SFT 28
+#define RG_GEMINIA_TX_BT_PA_MANUAL_HI 28
+#define RG_GEMINIA_TX_BT_PA_MANUAL_SZ 1
+#define RG_GEMINIA_EN_TX_BT_PA_MSK 0x20000000
+#define RG_GEMINIA_EN_TX_BT_PA_I_MSK 0xdfffffff
+#define RG_GEMINIA_EN_TX_BT_PA_SFT 29
+#define RG_GEMINIA_EN_TX_BT_PA_HI 29
+#define RG_GEMINIA_EN_TX_BT_PA_SZ 1
+#define RG_GEMINIA_EN_LDO_RX_FE_MSK 0x00000001
+#define RG_GEMINIA_EN_LDO_RX_FE_I_MSK 0xfffffffe
+#define RG_GEMINIA_EN_LDO_RX_FE_SFT 0
+#define RG_GEMINIA_EN_LDO_RX_FE_HI 0
+#define RG_GEMINIA_EN_LDO_RX_FE_SZ 1
+#define RG_GEMINIA_EN_LDO_ABB_MSK 0x00000002
+#define RG_GEMINIA_EN_LDO_ABB_I_MSK 0xfffffffd
+#define RG_GEMINIA_EN_LDO_ABB_SFT 1
+#define RG_GEMINIA_EN_LDO_ABB_HI 1
+#define RG_GEMINIA_EN_LDO_ABB_SZ 1
+#define RG_GEMINIA_EN_LDO_ADC_MSK 0x00000004
+#define RG_GEMINIA_EN_LDO_ADC_I_MSK 0xfffffffb
+#define RG_GEMINIA_EN_LDO_ADC_SFT 2
+#define RG_GEMINIA_EN_LDO_ADC_HI 2
+#define RG_GEMINIA_EN_LDO_ADC_SZ 1
+#define RG_GEMINIA_EN_LDO_DAC_MSK 0x00000008
+#define RG_GEMINIA_EN_LDO_DAC_I_MSK 0xfffffff7
+#define RG_GEMINIA_EN_LDO_DAC_SFT 3
+#define RG_GEMINIA_EN_LDO_DAC_HI 3
+#define RG_GEMINIA_EN_LDO_DAC_SZ 1
+#define RG_GEMINIA_EN_IREF_RX_MSK 0x00000010
+#define RG_GEMINIA_EN_IREF_RX_I_MSK 0xffffffef
+#define RG_GEMINIA_EN_IREF_RX_SFT 4
+#define RG_GEMINIA_EN_IREF_RX_HI 4
+#define RG_GEMINIA_EN_IREF_RX_SZ 1
+#define RG_GEMINIA_TX_DAC_CAL_MANUAL_MSK 0x00000040
+#define RG_GEMINIA_TX_DAC_CAL_MANUAL_I_MSK 0xffffffbf
+#define RG_GEMINIA_TX_DAC_CAL_MANUAL_SFT 6
+#define RG_GEMINIA_TX_DAC_CAL_MANUAL_HI 6
+#define RG_GEMINIA_TX_DAC_CAL_MANUAL_SZ 1
+#define RG_GEMINIA_EN_TX_DAC_CAL_MSK 0x00000080
+#define RG_GEMINIA_EN_TX_DAC_CAL_I_MSK 0xffffff7f
+#define RG_GEMINIA_EN_TX_DAC_CAL_SFT 7
+#define RG_GEMINIA_EN_TX_DAC_CAL_HI 7
+#define RG_GEMINIA_EN_TX_DAC_CAL_SZ 1
+#define RG_GEMINIA_RX_TZ_OUT_TRISTATE_MANUAL_MSK 0x00000100
+#define RG_GEMINIA_RX_TZ_OUT_TRISTATE_MANUAL_I_MSK 0xfffffeff
+#define RG_GEMINIA_RX_TZ_OUT_TRISTATE_MANUAL_SFT 8
+#define RG_GEMINIA_RX_TZ_OUT_TRISTATE_MANUAL_HI 8
+#define RG_GEMINIA_RX_TZ_OUT_TRISTATE_MANUAL_SZ 1
+#define RG_GEMINIA_RX_TZ_OUT_TRISTATE_MSK 0x00000200
+#define RG_GEMINIA_RX_TZ_OUT_TRISTATE_I_MSK 0xfffffdff
+#define RG_GEMINIA_RX_TZ_OUT_TRISTATE_SFT 9
+#define RG_GEMINIA_RX_TZ_OUT_TRISTATE_HI 9
+#define RG_GEMINIA_RX_TZ_OUT_TRISTATE_SZ 1
+#define RG_GEMINIA_TX_SELF_MIXER_MANUAL_MSK 0x00000400
+#define RG_GEMINIA_TX_SELF_MIXER_MANUAL_I_MSK 0xfffffbff
+#define RG_GEMINIA_TX_SELF_MIXER_MANUAL_SFT 10
+#define RG_GEMINIA_TX_SELF_MIXER_MANUAL_HI 10
+#define RG_GEMINIA_TX_SELF_MIXER_MANUAL_SZ 1
+#define RG_GEMINIA_EN_TX_SELF_MIXER_MSK 0x00000800
+#define RG_GEMINIA_EN_TX_SELF_MIXER_I_MSK 0xfffff7ff
+#define RG_GEMINIA_EN_TX_SELF_MIXER_SFT 11
+#define RG_GEMINIA_EN_TX_SELF_MIXER_HI 11
+#define RG_GEMINIA_EN_TX_SELF_MIXER_SZ 1
+#define RG_GEMINIA_RX_IQCAL_MANUAL_MSK 0x00001000
+#define RG_GEMINIA_RX_IQCAL_MANUAL_I_MSK 0xffffefff
+#define RG_GEMINIA_RX_IQCAL_MANUAL_SFT 12
+#define RG_GEMINIA_RX_IQCAL_MANUAL_HI 12
+#define RG_GEMINIA_RX_IQCAL_MANUAL_SZ 1
+#define RG_GEMINIA_EN_RX_IQCAL_MSK 0x00002000
+#define RG_GEMINIA_EN_RX_IQCAL_I_MSK 0xffffdfff
+#define RG_GEMINIA_EN_RX_IQCAL_SFT 13
+#define RG_GEMINIA_EN_RX_IQCAL_HI 13
+#define RG_GEMINIA_EN_RX_IQCAL_SZ 1
+#define RG_GEMINIA_TX_DPD_MANUAL_MSK 0x00004000
+#define RG_GEMINIA_TX_DPD_MANUAL_I_MSK 0xffffbfff
+#define RG_GEMINIA_TX_DPD_MANUAL_SFT 14
+#define RG_GEMINIA_TX_DPD_MANUAL_HI 14
+#define RG_GEMINIA_TX_DPD_MANUAL_SZ 1
+#define RG_GEMINIA_EN_TX_DPD_MSK 0x00008000
+#define RG_GEMINIA_EN_TX_DPD_I_MSK 0xffff7fff
+#define RG_GEMINIA_EN_TX_DPD_SFT 15
+#define RG_GEMINIA_EN_TX_DPD_HI 15
+#define RG_GEMINIA_EN_TX_DPD_SZ 1
+#define RG_GEMINIA_RXRCCALQ_EN_BYP_MSK 0x00010000
+#define RG_GEMINIA_RXRCCALQ_EN_BYP_I_MSK 0xfffeffff
+#define RG_GEMINIA_RXRCCALQ_EN_BYP_SFT 16
+#define RG_GEMINIA_RXRCCALQ_EN_BYP_HI 16
+#define RG_GEMINIA_RXRCCALQ_EN_BYP_SZ 1
+#define RG_GEMINIA_EN_TX_TSSI_MSK 0x00020000
+#define RG_GEMINIA_EN_TX_TSSI_I_MSK 0xfffdffff
+#define RG_GEMINIA_EN_TX_TSSI_SFT 17
+#define RG_GEMINIA_EN_TX_TSSI_HI 17
+#define RG_GEMINIA_EN_TX_TSSI_SZ 1
+#define RG_GEMINIA_EN_SARADC_MSK 0x00040000
+#define RG_GEMINIA_EN_SARADC_I_MSK 0xfffbffff
+#define RG_GEMINIA_EN_SARADC_SFT 18
+#define RG_GEMINIA_EN_SARADC_HI 18
+#define RG_GEMINIA_EN_SARADC_SZ 1
+#define RG_GEMINIA_EN_TX_VTOI_2ND_MSK 0x00080000
+#define RG_GEMINIA_EN_TX_VTOI_2ND_I_MSK 0xfff7ffff
+#define RG_GEMINIA_EN_TX_VTOI_2ND_SFT 19
+#define RG_GEMINIA_EN_TX_VTOI_2ND_HI 19
+#define RG_GEMINIA_EN_TX_VTOI_2ND_SZ 1
+#define RG_GEMINIA_TXLPF_BYPASS_MSK 0x00100000
+#define RG_GEMINIA_TXLPF_BYPASS_I_MSK 0xffefffff
+#define RG_GEMINIA_TXLPF_BYPASS_SFT 20
+#define RG_GEMINIA_TXLPF_BYPASS_HI 20
+#define RG_GEMINIA_TXLPF_BYPASS_SZ 1
+#define RG_GEMINIA_TX_EN_VOLTAGE_IN_MSK 0x00200000
+#define RG_GEMINIA_TX_EN_VOLTAGE_IN_I_MSK 0xffdfffff
+#define RG_GEMINIA_TX_EN_VOLTAGE_IN_SFT 21
+#define RG_GEMINIA_TX_EN_VOLTAGE_IN_HI 21
+#define RG_GEMINIA_TX_EN_VOLTAGE_IN_SZ 1
+#define RG_GEMINIA_EN_TX_DAC_OUT_MSK 0x00400000
+#define RG_GEMINIA_EN_TX_DAC_OUT_I_MSK 0xffbfffff
+#define RG_GEMINIA_EN_TX_DAC_OUT_SFT 22
+#define RG_GEMINIA_EN_TX_DAC_OUT_HI 22
+#define RG_GEMINIA_EN_TX_DAC_OUT_SZ 1
+#define RG_GEMINIA_EN_TX_DAC_VOUT_MSK 0x00800000
+#define RG_GEMINIA_EN_TX_DAC_VOUT_I_MSK 0xff7fffff
+#define RG_GEMINIA_EN_TX_DAC_VOUT_SFT 23
+#define RG_GEMINIA_EN_TX_DAC_VOUT_HI 23
+#define RG_GEMINIA_EN_TX_DAC_VOUT_SZ 1
+#define RG_GEMINIA_RX_ABBOUT_TRI_STATE_MSK 0x01000000
+#define RG_GEMINIA_RX_ABBOUT_TRI_STATE_I_MSK 0xfeffffff
+#define RG_GEMINIA_RX_ABBOUT_TRI_STATE_SFT 24
+#define RG_GEMINIA_RX_ABBOUT_TRI_STATE_HI 24
+#define RG_GEMINIA_RX_ABBOUT_TRI_STATE_SZ 1
+#define RG_GEMINIA_EN_RX_TESTNODE_MSK 0x02000000
+#define RG_GEMINIA_EN_RX_TESTNODE_I_MSK 0xfdffffff
+#define RG_GEMINIA_EN_RX_TESTNODE_SFT 25
+#define RG_GEMINIA_EN_RX_TESTNODE_HI 25
+#define RG_GEMINIA_EN_RX_TESTNODE_SZ 1
+#define RG_GEMINIA_EN_RX_PADSW_MSK 0x04000000
+#define RG_GEMINIA_EN_RX_PADSW_I_MSK 0xfbffffff
+#define RG_GEMINIA_EN_RX_PADSW_SFT 26
+#define RG_GEMINIA_EN_RX_PADSW_HI 26
+#define RG_GEMINIA_EN_RX_PADSW_SZ 1
+#define RG_GEMINIA_LDO_RX_FE_EN_BYP_MSK 0x08000000
+#define RG_GEMINIA_LDO_RX_FE_EN_BYP_I_MSK 0xf7ffffff
+#define RG_GEMINIA_LDO_RX_FE_EN_BYP_SFT 27
+#define RG_GEMINIA_LDO_RX_FE_EN_BYP_HI 27
+#define RG_GEMINIA_LDO_RX_FE_EN_BYP_SZ 1
+#define RG_GEMINIA_LDO_RX_ABB_EN_BYP_MSK 0x10000000
+#define RG_GEMINIA_LDO_RX_ABB_EN_BYP_I_MSK 0xefffffff
+#define RG_GEMINIA_LDO_RX_ABB_EN_BYP_SFT 28
+#define RG_GEMINIA_LDO_RX_ABB_EN_BYP_HI 28
+#define RG_GEMINIA_LDO_RX_ABB_EN_BYP_SZ 1
+#define RG_GEMINIA_LDO_RX_ADC_EN_BYP_MSK 0x20000000
+#define RG_GEMINIA_LDO_RX_ADC_EN_BYP_I_MSK 0xdfffffff
+#define RG_GEMINIA_LDO_RX_ADC_EN_BYP_SFT 29
+#define RG_GEMINIA_LDO_RX_ADC_EN_BYP_HI 29
+#define RG_GEMINIA_LDO_RX_ADC_EN_BYP_SZ 1
+#define RG_GEMINIA_LDO_TX_DAC_EN_BYP_MSK 0x40000000
+#define RG_GEMINIA_LDO_TX_DAC_EN_BYP_I_MSK 0xbfffffff
+#define RG_GEMINIA_LDO_TX_DAC_EN_BYP_SFT 30
+#define RG_GEMINIA_LDO_TX_DAC_EN_BYP_HI 30
+#define RG_GEMINIA_LDO_TX_DAC_EN_BYP_SZ 1
+#define RG_GEMINIA_EN_LDO_RX_ADC_IQUP_MSK 0x80000000
+#define RG_GEMINIA_EN_LDO_RX_ADC_IQUP_I_MSK 0x7fffffff
+#define RG_GEMINIA_EN_LDO_RX_ADC_IQUP_SFT 31
+#define RG_GEMINIA_EN_LDO_RX_ADC_IQUP_HI 31
+#define RG_GEMINIA_EN_LDO_RX_ADC_IQUP_SZ 1
+#define RG_GEMINIA_LDO_LEVEL_RX_FE_MSK 0x00000007
+#define RG_GEMINIA_LDO_LEVEL_RX_FE_I_MSK 0xfffffff8
+#define RG_GEMINIA_LDO_LEVEL_RX_FE_SFT 0
+#define RG_GEMINIA_LDO_LEVEL_RX_FE_HI 2
+#define RG_GEMINIA_LDO_LEVEL_RX_FE_SZ 3
+#define RG_GEMINIA_LDO_LEVEL_ABB_MSK 0x00000038
+#define RG_GEMINIA_LDO_LEVEL_ABB_I_MSK 0xffffffc7
+#define RG_GEMINIA_LDO_LEVEL_ABB_SFT 3
+#define RG_GEMINIA_LDO_LEVEL_ABB_HI 5
+#define RG_GEMINIA_LDO_LEVEL_ABB_SZ 3
+#define RG_GEMINIA_LDO_LEVEL_ADC_MSK 0x000001c0
+#define RG_GEMINIA_LDO_LEVEL_ADC_I_MSK 0xfffffe3f
+#define RG_GEMINIA_LDO_LEVEL_ADC_SFT 6
+#define RG_GEMINIA_LDO_LEVEL_ADC_HI 8
+#define RG_GEMINIA_LDO_LEVEL_ADC_SZ 3
+#define RG_GEMINIA_LDO_LEVEL_DAC_MSK 0x00000e00
+#define RG_GEMINIA_LDO_LEVEL_DAC_I_MSK 0xfffff1ff
+#define RG_GEMINIA_LDO_LEVEL_DAC_SFT 9
+#define RG_GEMINIA_LDO_LEVEL_DAC_HI 11
+#define RG_GEMINIA_LDO_LEVEL_DAC_SZ 3
+#define RG_GEMINIA_SX_LDO_CP_LEVEL_MSK 0x00007000
+#define RG_GEMINIA_SX_LDO_CP_LEVEL_I_MSK 0xffff8fff
+#define RG_GEMINIA_SX_LDO_CP_LEVEL_SFT 12
+#define RG_GEMINIA_SX_LDO_CP_LEVEL_HI 14
+#define RG_GEMINIA_SX_LDO_CP_LEVEL_SZ 3
+#define RG_GEMINIA_SX_LDO_LO_LEVEL_MSK 0x00038000
+#define RG_GEMINIA_SX_LDO_LO_LEVEL_I_MSK 0xfffc7fff
+#define RG_GEMINIA_SX_LDO_LO_LEVEL_SFT 15
+#define RG_GEMINIA_SX_LDO_LO_LEVEL_HI 17
+#define RG_GEMINIA_SX_LDO_LO_LEVEL_SZ 3
+#define RG_GEMINIA_DP_LDO_LEVEL_MSK 0x00e00000
+#define RG_GEMINIA_DP_LDO_LEVEL_I_MSK 0xff1fffff
+#define RG_GEMINIA_DP_LDO_LEVEL_SFT 21
+#define RG_GEMINIA_DP_LDO_LEVEL_HI 23
+#define RG_GEMINIA_DP_LDO_LEVEL_SZ 3
+#define RG_GEMINIA_SX_LDO_VCO_LEVEL_MSK 0x07000000
+#define RG_GEMINIA_SX_LDO_VCO_LEVEL_I_MSK 0xf8ffffff
+#define RG_GEMINIA_SX_LDO_VCO_LEVEL_SFT 24
+#define RG_GEMINIA_SX_LDO_VCO_LEVEL_HI 26
+#define RG_GEMINIA_SX_LDO_VCO_LEVEL_SZ 3
+#define RG_GEMINIA_SX_LDO_DIV_LEVEL_MSK 0x38000000
+#define RG_GEMINIA_SX_LDO_DIV_LEVEL_I_MSK 0xc7ffffff
+#define RG_GEMINIA_SX_LDO_DIV_LEVEL_SFT 27
+#define RG_GEMINIA_SX_LDO_DIV_LEVEL_HI 29
+#define RG_GEMINIA_SX_LDO_DIV_LEVEL_SZ 3
+#define RG_GEMINIA_WF_RX_ABBCTUNEI_MSK 0x0000003f
+#define RG_GEMINIA_WF_RX_ABBCTUNEI_I_MSK 0xffffffc0
+#define RG_GEMINIA_WF_RX_ABBCTUNEI_SFT 0
+#define RG_GEMINIA_WF_RX_ABBCTUNEI_HI 5
+#define RG_GEMINIA_WF_RX_ABBCTUNEI_SZ 6
+#define RG_GEMINIA_WF_RX_ABBCTUNEQ_MSK 0x00000fc0
+#define RG_GEMINIA_WF_RX_ABBCTUNEQ_I_MSK 0xfffff03f
+#define RG_GEMINIA_WF_RX_ABBCTUNEQ_SFT 6
+#define RG_GEMINIA_WF_RX_ABBCTUNEQ_HI 11
+#define RG_GEMINIA_WF_RX_ABBCTUNEQ_SZ 6
+#define RG_GEMINIA_WF_RX_FILTERI_COARSE_MSK 0x00003000
+#define RG_GEMINIA_WF_RX_FILTERI_COARSE_I_MSK 0xffffcfff
+#define RG_GEMINIA_WF_RX_FILTERI_COARSE_SFT 12
+#define RG_GEMINIA_WF_RX_FILTERI_COARSE_HI 13
+#define RG_GEMINIA_WF_RX_FILTERI_COARSE_SZ 2
+#define RG_GEMINIA_WF_RX_FILTERI1ST_MSK 0x0000c000
+#define RG_GEMINIA_WF_RX_FILTERI1ST_I_MSK 0xffff3fff
+#define RG_GEMINIA_WF_RX_FILTERI1ST_SFT 14
+#define RG_GEMINIA_WF_RX_FILTERI1ST_HI 15
+#define RG_GEMINIA_WF_RX_FILTERI1ST_SZ 2
+#define RG_GEMINIA_WF_RX_FILTERI2ND_MSK 0x00030000
+#define RG_GEMINIA_WF_RX_FILTERI2ND_I_MSK 0xfffcffff
+#define RG_GEMINIA_WF_RX_FILTERI2ND_SFT 16
+#define RG_GEMINIA_WF_RX_FILTERI2ND_HI 17
+#define RG_GEMINIA_WF_RX_FILTERI2ND_SZ 2
+#define RG_GEMINIA_WF_RX_FILTERI3RD_MSK 0x000c0000
+#define RG_GEMINIA_WF_RX_FILTERI3RD_I_MSK 0xfff3ffff
+#define RG_GEMINIA_WF_RX_FILTERI3RD_SFT 18
+#define RG_GEMINIA_WF_RX_FILTERI3RD_HI 19
+#define RG_GEMINIA_WF_RX_FILTERI3RD_SZ 2
+#define RG_GEMINIA_WF_RX_ABBCFIX_MSK 0x00100000
+#define RG_GEMINIA_WF_RX_ABBCFIX_I_MSK 0xffefffff
+#define RG_GEMINIA_WF_RX_ABBCFIX_SFT 20
+#define RG_GEMINIA_WF_RX_ABBCFIX_HI 20
+#define RG_GEMINIA_WF_RX_ABBCFIX_SZ 1
+#define RG_GEMINIA_WF_RX_ABB_N_MODE_MSK 0x00200000
+#define RG_GEMINIA_WF_RX_ABB_N_MODE_I_MSK 0xffdfffff
+#define RG_GEMINIA_WF_RX_ABB_N_MODE_SFT 21
+#define RG_GEMINIA_WF_RX_ABB_N_MODE_HI 21
+#define RG_GEMINIA_WF_RX_ABB_N_MODE_SZ 1
+#define RG_GEMINIA_WF_RX_ABB_BT_MODE_MSK 0x00400000
+#define RG_GEMINIA_WF_RX_ABB_BT_MODE_I_MSK 0xffbfffff
+#define RG_GEMINIA_WF_RX_ABB_BT_MODE_SFT 22
+#define RG_GEMINIA_WF_RX_ABB_BT_MODE_HI 22
+#define RG_GEMINIA_WF_RX_ABB_BT_MODE_SZ 1
+#define RG_GEMINIA_WF_RX_ABB_IDIV3_MSK 0x00800000
+#define RG_GEMINIA_WF_RX_ABB_IDIV3_I_MSK 0xff7fffff
+#define RG_GEMINIA_WF_RX_ABB_IDIV3_SFT 23
+#define RG_GEMINIA_WF_RX_ABB_IDIV3_HI 23
+#define RG_GEMINIA_WF_RX_ABB_IDIV3_SZ 1
+#define RG_GEMINIA_WF_RX_EN_IDACA_COARSE_MSK 0x01000000
+#define RG_GEMINIA_WF_RX_EN_IDACA_COARSE_I_MSK 0xfeffffff
+#define RG_GEMINIA_WF_RX_EN_IDACA_COARSE_SFT 24
+#define RG_GEMINIA_WF_RX_EN_IDACA_COARSE_HI 24
+#define RG_GEMINIA_WF_RX_EN_IDACA_COARSE_SZ 1
+#define RG_GEMINIA_WF_RX_EN_LOOPA_MSK 0x02000000
+#define RG_GEMINIA_WF_RX_EN_LOOPA_I_MSK 0xfdffffff
+#define RG_GEMINIA_WF_RX_EN_LOOPA_SFT 25
+#define RG_GEMINIA_WF_RX_EN_LOOPA_HI 25
+#define RG_GEMINIA_WF_RX_EN_LOOPA_SZ 1
+#define RG_GEMINIA_WF_RX_FILTERVCM_MSK 0x0c000000
+#define RG_GEMINIA_WF_RX_FILTERVCM_I_MSK 0xf3ffffff
+#define RG_GEMINIA_WF_RX_FILTERVCM_SFT 26
+#define RG_GEMINIA_WF_RX_FILTERVCM_HI 27
+#define RG_GEMINIA_WF_RX_FILTERVCM_SZ 2
+#define RG_GEMINIA_WF_RX_OUTVCM_MSK 0x30000000
+#define RG_GEMINIA_WF_RX_OUTVCM_I_MSK 0xcfffffff
+#define RG_GEMINIA_WF_RX_OUTVCM_SFT 28
+#define RG_GEMINIA_WF_RX_OUTVCM_HI 29
+#define RG_GEMINIA_WF_RX_OUTVCM_SZ 2
+#define RG_GEMINIA_BT_RX_ABBCTUNEI_MSK 0x0000003f
+#define RG_GEMINIA_BT_RX_ABBCTUNEI_I_MSK 0xffffffc0
+#define RG_GEMINIA_BT_RX_ABBCTUNEI_SFT 0
+#define RG_GEMINIA_BT_RX_ABBCTUNEI_HI 5
+#define RG_GEMINIA_BT_RX_ABBCTUNEI_SZ 6
+#define RG_GEMINIA_BT_RX_ABBCTUNEQ_MSK 0x00000fc0
+#define RG_GEMINIA_BT_RX_ABBCTUNEQ_I_MSK 0xfffff03f
+#define RG_GEMINIA_BT_RX_ABBCTUNEQ_SFT 6
+#define RG_GEMINIA_BT_RX_ABBCTUNEQ_HI 11
+#define RG_GEMINIA_BT_RX_ABBCTUNEQ_SZ 6
+#define RG_GEMINIA_BT_RX_FILTERI_COARSE_MSK 0x00003000
+#define RG_GEMINIA_BT_RX_FILTERI_COARSE_I_MSK 0xffffcfff
+#define RG_GEMINIA_BT_RX_FILTERI_COARSE_SFT 12
+#define RG_GEMINIA_BT_RX_FILTERI_COARSE_HI 13
+#define RG_GEMINIA_BT_RX_FILTERI_COARSE_SZ 2
+#define RG_GEMINIA_BT_RX_FILTERI1ST_MSK 0x0000c000
+#define RG_GEMINIA_BT_RX_FILTERI1ST_I_MSK 0xffff3fff
+#define RG_GEMINIA_BT_RX_FILTERI1ST_SFT 14
+#define RG_GEMINIA_BT_RX_FILTERI1ST_HI 15
+#define RG_GEMINIA_BT_RX_FILTERI1ST_SZ 2
+#define RG_GEMINIA_BT_RX_FILTERI2ND_MSK 0x00030000
+#define RG_GEMINIA_BT_RX_FILTERI2ND_I_MSK 0xfffcffff
+#define RG_GEMINIA_BT_RX_FILTERI2ND_SFT 16
+#define RG_GEMINIA_BT_RX_FILTERI2ND_HI 17
+#define RG_GEMINIA_BT_RX_FILTERI2ND_SZ 2
+#define RG_GEMINIA_BT_RX_FILTERI3RD_MSK 0x000c0000
+#define RG_GEMINIA_BT_RX_FILTERI3RD_I_MSK 0xfff3ffff
+#define RG_GEMINIA_BT_RX_FILTERI3RD_SFT 18
+#define RG_GEMINIA_BT_RX_FILTERI3RD_HI 19
+#define RG_GEMINIA_BT_RX_FILTERI3RD_SZ 2
+#define RG_GEMINIA_BT_RX_ABBCFIX_MSK 0x00100000
+#define RG_GEMINIA_BT_RX_ABBCFIX_I_MSK 0xffefffff
+#define RG_GEMINIA_BT_RX_ABBCFIX_SFT 20
+#define RG_GEMINIA_BT_RX_ABBCFIX_HI 20
+#define RG_GEMINIA_BT_RX_ABBCFIX_SZ 1
+#define RG_GEMINIA_BT_RX_ABB_N_MODE_MSK 0x00200000
+#define RG_GEMINIA_BT_RX_ABB_N_MODE_I_MSK 0xffdfffff
+#define RG_GEMINIA_BT_RX_ABB_N_MODE_SFT 21
+#define RG_GEMINIA_BT_RX_ABB_N_MODE_HI 21
+#define RG_GEMINIA_BT_RX_ABB_N_MODE_SZ 1
+#define RG_GEMINIA_BT_RX_ABB_BT_MODE_MSK 0x00400000
+#define RG_GEMINIA_BT_RX_ABB_BT_MODE_I_MSK 0xffbfffff
+#define RG_GEMINIA_BT_RX_ABB_BT_MODE_SFT 22
+#define RG_GEMINIA_BT_RX_ABB_BT_MODE_HI 22
+#define RG_GEMINIA_BT_RX_ABB_BT_MODE_SZ 1
+#define RG_GEMINIA_BT_RX_ABB_IDIV3_MSK 0x00800000
+#define RG_GEMINIA_BT_RX_ABB_IDIV3_I_MSK 0xff7fffff
+#define RG_GEMINIA_BT_RX_ABB_IDIV3_SFT 23
+#define RG_GEMINIA_BT_RX_ABB_IDIV3_HI 23
+#define RG_GEMINIA_BT_RX_ABB_IDIV3_SZ 1
+#define RG_GEMINIA_BT_RX_EN_IDACA_COARSE_MSK 0x01000000
+#define RG_GEMINIA_BT_RX_EN_IDACA_COARSE_I_MSK 0xfeffffff
+#define RG_GEMINIA_BT_RX_EN_IDACA_COARSE_SFT 24
+#define RG_GEMINIA_BT_RX_EN_IDACA_COARSE_HI 24
+#define RG_GEMINIA_BT_RX_EN_IDACA_COARSE_SZ 1
+#define RG_GEMINIA_BT_RX_EN_LOOPA_MSK 0x02000000
+#define RG_GEMINIA_BT_RX_EN_LOOPA_I_MSK 0xfdffffff
+#define RG_GEMINIA_BT_RX_EN_LOOPA_SFT 25
+#define RG_GEMINIA_BT_RX_EN_LOOPA_HI 25
+#define RG_GEMINIA_BT_RX_EN_LOOPA_SZ 1
+#define RG_GEMINIA_BT_RX_FILTERVCM_MSK 0x0c000000
+#define RG_GEMINIA_BT_RX_FILTERVCM_I_MSK 0xf3ffffff
+#define RG_GEMINIA_BT_RX_FILTERVCM_SFT 26
+#define RG_GEMINIA_BT_RX_FILTERVCM_HI 27
+#define RG_GEMINIA_BT_RX_FILTERVCM_SZ 2
+#define RG_GEMINIA_BT_RX_OUTVCM_MSK 0x30000000
+#define RG_GEMINIA_BT_RX_OUTVCM_I_MSK 0xcfffffff
+#define RG_GEMINIA_BT_RX_OUTVCM_SFT 28
+#define RG_GEMINIA_BT_RX_OUTVCM_HI 29
+#define RG_GEMINIA_BT_RX_OUTVCM_SZ 2
+#define RG_GEMINIA_RX_ADCRSSI_VCM_MSK 0x00000003
+#define RG_GEMINIA_RX_ADCRSSI_VCM_I_MSK 0xfffffffc
+#define RG_GEMINIA_RX_ADCRSSI_VCM_SFT 0
+#define RG_GEMINIA_RX_ADCRSSI_VCM_HI 1
+#define RG_GEMINIA_RX_ADCRSSI_VCM_SZ 2
+#define RG_GEMINIA_RX_REC_LPFCORNER_MSK 0x0000000c
+#define RG_GEMINIA_RX_REC_LPFCORNER_I_MSK 0xfffffff3
+#define RG_GEMINIA_RX_REC_LPFCORNER_SFT 2
+#define RG_GEMINIA_RX_REC_LPFCORNER_HI 3
+#define RG_GEMINIA_RX_REC_LPFCORNER_SZ 2
+#define RG_GEMINIA_RX_ADCRSSI_CLKSEL_MSK 0x00000010
+#define RG_GEMINIA_RX_ADCRSSI_CLKSEL_I_MSK 0xffffffef
+#define RG_GEMINIA_RX_ADCRSSI_CLKSEL_SFT 4
+#define RG_GEMINIA_RX_ADCRSSI_CLKSEL_HI 4
+#define RG_GEMINIA_RX_ADCRSSI_CLKSEL_SZ 1
+#define RG_GEMINIA_RSSI_CLOCK_GATING_MSK 0x00000020
+#define RG_GEMINIA_RSSI_CLOCK_GATING_I_MSK 0xffffffdf
+#define RG_GEMINIA_RSSI_CLOCK_GATING_SFT 5
+#define RG_GEMINIA_RSSI_CLOCK_GATING_HI 5
+#define RG_GEMINIA_RSSI_CLOCK_GATING_SZ 1
+#define RG_GEMINIA_TX_DPDGM_BIAS_MSK 0x00000f00
+#define RG_GEMINIA_TX_DPDGM_BIAS_I_MSK 0xfffff0ff
+#define RG_GEMINIA_TX_DPDGM_BIAS_SFT 8
+#define RG_GEMINIA_TX_DPDGM_BIAS_HI 11
+#define RG_GEMINIA_TX_DPDGM_BIAS_SZ 4
+#define RG_GEMINIA_TX_DPD_DIV_MSK 0x0000f000
+#define RG_GEMINIA_TX_DPD_DIV_I_MSK 0xffff0fff
+#define RG_GEMINIA_TX_DPD_DIV_SFT 12
+#define RG_GEMINIA_TX_DPD_DIV_HI 15
+#define RG_GEMINIA_TX_DPD_DIV_SZ 4
+#define RG_GEMINIA_TX_TSSI_BIAS_MSK 0x00070000
+#define RG_GEMINIA_TX_TSSI_BIAS_I_MSK 0xfff8ffff
+#define RG_GEMINIA_TX_TSSI_BIAS_SFT 16
+#define RG_GEMINIA_TX_TSSI_BIAS_HI 18
+#define RG_GEMINIA_TX_TSSI_BIAS_SZ 3
+#define RG_GEMINIA_TX_TSSI_DIV_MSK 0x00380000
+#define RG_GEMINIA_TX_TSSI_DIV_I_MSK 0xffc7ffff
+#define RG_GEMINIA_TX_TSSI_DIV_SFT 19
+#define RG_GEMINIA_TX_TSSI_DIV_HI 21
+#define RG_GEMINIA_TX_TSSI_DIV_SZ 3
+#define RG_GEMINIA_TX_TSSI_TEST_MSK 0x00c00000
+#define RG_GEMINIA_TX_TSSI_TEST_I_MSK 0xff3fffff
+#define RG_GEMINIA_TX_TSSI_TEST_SFT 22
+#define RG_GEMINIA_TX_TSSI_TEST_HI 23
+#define RG_GEMINIA_TX_TSSI_TEST_SZ 2
+#define RG_GEMINIA_TX_TSSI_TESTMODE_MSK 0x01000000
+#define RG_GEMINIA_TX_TSSI_TESTMODE_I_MSK 0xfeffffff
+#define RG_GEMINIA_TX_TSSI_TESTMODE_SFT 24
+#define RG_GEMINIA_TX_TSSI_TESTMODE_HI 24
+#define RG_GEMINIA_TX_TSSI_TESTMODE_SZ 1
+#define RG_GEMINIA_EN_RX_RSSI_TESTNODE_MSK 0x0e000000
+#define RG_GEMINIA_EN_RX_RSSI_TESTNODE_I_MSK 0xf1ffffff
+#define RG_GEMINIA_EN_RX_RSSI_TESTNODE_SFT 25
+#define RG_GEMINIA_EN_RX_RSSI_TESTNODE_HI 27
+#define RG_GEMINIA_EN_RX_RSSI_TESTNODE_SZ 3
+#define RG_GEMINIA_RX_LNA_TRI_SEL_MSK 0x30000000
+#define RG_GEMINIA_RX_LNA_TRI_SEL_I_MSK 0xcfffffff
+#define RG_GEMINIA_RX_LNA_TRI_SEL_SFT 28
+#define RG_GEMINIA_RX_LNA_TRI_SEL_HI 29
+#define RG_GEMINIA_RX_LNA_TRI_SEL_SZ 2
+#define RG_GEMINIA_RX_LNA_SETTLE_MSK 0xc0000000
+#define RG_GEMINIA_RX_LNA_SETTLE_I_MSK 0x3fffffff
+#define RG_GEMINIA_RX_LNA_SETTLE_SFT 30
+#define RG_GEMINIA_RX_LNA_SETTLE_HI 31
+#define RG_GEMINIA_RX_LNA_SETTLE_SZ 2
+#define RG_GEMINIA_WF_TXPGA_CAPSW_MSK 0x00000003
+#define RG_GEMINIA_WF_TXPGA_CAPSW_I_MSK 0xfffffffc
+#define RG_GEMINIA_WF_TXPGA_CAPSW_SFT 0
+#define RG_GEMINIA_WF_TXPGA_CAPSW_HI 1
+#define RG_GEMINIA_WF_TXPGA_CAPSW_SZ 2
+#define RG_GEMINIA_WF_TX_DIV_VSET_MSK 0x0000000c
+#define RG_GEMINIA_WF_TX_DIV_VSET_I_MSK 0xfffffff3
+#define RG_GEMINIA_WF_TX_DIV_VSET_SFT 2
+#define RG_GEMINIA_WF_TX_DIV_VSET_HI 3
+#define RG_GEMINIA_WF_TX_DIV_VSET_SZ 2
+#define RG_GEMINIA_WF_TX_LOBUF_VSET_MSK 0x00000030
+#define RG_GEMINIA_WF_TX_LOBUF_VSET_I_MSK 0xffffffcf
+#define RG_GEMINIA_WF_TX_LOBUF_VSET_SFT 4
+#define RG_GEMINIA_WF_TX_LOBUF_VSET_HI 5
+#define RG_GEMINIA_WF_TX_LOBUF_VSET_SZ 2
+#define RG_GEMINIA_WF_TX_VDDSW_MSK 0x00000040
+#define RG_GEMINIA_WF_TX_VDDSW_I_MSK 0xffffffbf
+#define RG_GEMINIA_WF_TX_VDDSW_SFT 6
+#define RG_GEMINIA_WF_TX_VDDSW_HI 6
+#define RG_GEMINIA_WF_TX_VDDSW_SZ 1
+#define RG_GEMINIA_BT_TXPGA_CAPSW_MSK 0x00000300
+#define RG_GEMINIA_BT_TXPGA_CAPSW_I_MSK 0xfffffcff
+#define RG_GEMINIA_BT_TXPGA_CAPSW_SFT 8
+#define RG_GEMINIA_BT_TXPGA_CAPSW_HI 9
+#define RG_GEMINIA_BT_TXPGA_CAPSW_SZ 2
+#define RG_GEMINIA_BT_TX_DIV_VSET_MSK 0x00000c00
+#define RG_GEMINIA_BT_TX_DIV_VSET_I_MSK 0xfffff3ff
+#define RG_GEMINIA_BT_TX_DIV_VSET_SFT 10
+#define RG_GEMINIA_BT_TX_DIV_VSET_HI 11
+#define RG_GEMINIA_BT_TX_DIV_VSET_SZ 2
+#define RG_GEMINIA_BT_TX_LOBUF_VSET_MSK 0x00003000
+#define RG_GEMINIA_BT_TX_LOBUF_VSET_I_MSK 0xffffcfff
+#define RG_GEMINIA_BT_TX_LOBUF_VSET_SFT 12
+#define RG_GEMINIA_BT_TX_LOBUF_VSET_HI 13
+#define RG_GEMINIA_BT_TX_LOBUF_VSET_SZ 2
+#define RG_GEMINIA_BT_TX_VDDSW_MSK 0x00004000
+#define RG_GEMINIA_BT_TX_VDDSW_I_MSK 0xffffbfff
+#define RG_GEMINIA_BT_TX_VDDSW_SFT 14
+#define RG_GEMINIA_BT_TX_VDDSW_HI 14
+#define RG_GEMINIA_BT_TX_VDDSW_SZ 1
+#define RG_GEMINIA_WF_PACELL_EN_MSK 0x00000007
+#define RG_GEMINIA_WF_PACELL_EN_I_MSK 0xfffffff8
+#define RG_GEMINIA_WF_PACELL_EN_SFT 0
+#define RG_GEMINIA_WF_PACELL_EN_HI 2
+#define RG_GEMINIA_WF_PACELL_EN_SZ 3
+#define RG_GEMINIA_WF_PABIAS_CTRL_MSK 0x000000f0
+#define RG_GEMINIA_WF_PABIAS_CTRL_I_MSK 0xffffff0f
+#define RG_GEMINIA_WF_PABIAS_CTRL_SFT 4
+#define RG_GEMINIA_WF_PABIAS_CTRL_HI 7
+#define RG_GEMINIA_WF_PABIAS_CTRL_SZ 4
+#define RG_GEMINIA_WF_TX_PA1_VCAS_MSK 0x00000700
+#define RG_GEMINIA_WF_TX_PA1_VCAS_I_MSK 0xfffff8ff
+#define RG_GEMINIA_WF_TX_PA1_VCAS_SFT 8
+#define RG_GEMINIA_WF_TX_PA1_VCAS_HI 10
+#define RG_GEMINIA_WF_TX_PA1_VCAS_SZ 3
+#define RG_GEMINIA_WF_TX_PA2_VCAS_MSK 0x00007000
+#define RG_GEMINIA_WF_TX_PA2_VCAS_I_MSK 0xffff8fff
+#define RG_GEMINIA_WF_TX_PA2_VCAS_SFT 12
+#define RG_GEMINIA_WF_TX_PA2_VCAS_HI 14
+#define RG_GEMINIA_WF_TX_PA2_VCAS_SZ 3
+#define RG_GEMINIA_WF_TX_PA3_VCAS_MSK 0x00070000
+#define RG_GEMINIA_WF_TX_PA3_VCAS_I_MSK 0xfff8ffff
+#define RG_GEMINIA_WF_TX_PA3_VCAS_SFT 16
+#define RG_GEMINIA_WF_TX_PA3_VCAS_HI 18
+#define RG_GEMINIA_WF_TX_PA3_VCAS_SZ 3
+#define RG_GEMINIA_BT_PA_CAPSEL_MSK 0x00700000
+#define RG_GEMINIA_BT_PA_CAPSEL_I_MSK 0xff8fffff
+#define RG_GEMINIA_BT_PA_CAPSEL_SFT 20
+#define RG_GEMINIA_BT_PA_CAPSEL_HI 22
+#define RG_GEMINIA_BT_PA_CAPSEL_SZ 3
+#define RG_GEMINIA_BT_PABIAS_2X_MSK 0x00800000
+#define RG_GEMINIA_BT_PABIAS_2X_I_MSK 0xff7fffff
+#define RG_GEMINIA_BT_PABIAS_2X_SFT 23
+#define RG_GEMINIA_BT_PABIAS_2X_HI 23
+#define RG_GEMINIA_BT_PABIAS_2X_SZ 1
+#define RG_GEMINIA_BT_PABIAS_CTRL_MSK 0x0f000000
+#define RG_GEMINIA_BT_PABIAS_CTRL_I_MSK 0xf0ffffff
+#define RG_GEMINIA_BT_PABIAS_CTRL_SFT 24
+#define RG_GEMINIA_BT_PABIAS_CTRL_HI 27
+#define RG_GEMINIA_BT_PABIAS_CTRL_SZ 4
+#define RG_GEMINIA_BT_TX_PA_VCAS_MSK 0x70000000
+#define RG_GEMINIA_BT_TX_PA_VCAS_I_MSK 0x8fffffff
+#define RG_GEMINIA_BT_TX_PA_VCAS_SFT 28
+#define RG_GEMINIA_BT_TX_PA_VCAS_HI 30
+#define RG_GEMINIA_BT_TX_PA_VCAS_SZ 3
+#define RG_GEMINIA_TXPGA_MAIN_MSK 0x0000003f
+#define RG_GEMINIA_TXPGA_MAIN_I_MSK 0xffffffc0
+#define RG_GEMINIA_TXPGA_MAIN_SFT 0
+#define RG_GEMINIA_TXPGA_MAIN_HI 5
+#define RG_GEMINIA_TXPGA_MAIN_SZ 6
+#define RG_GEMINIA_TXPGA_STEER_MSK 0x00000fc0
+#define RG_GEMINIA_TXPGA_STEER_I_MSK 0xfffff03f
+#define RG_GEMINIA_TXPGA_STEER_SFT 6
+#define RG_GEMINIA_TXPGA_STEER_HI 11
+#define RG_GEMINIA_TXPGA_STEER_SZ 6
+#define RG_GEMINIA_TXMOD_GMCELL_MSK 0x00003000
+#define RG_GEMINIA_TXMOD_GMCELL_I_MSK 0xffffcfff
+#define RG_GEMINIA_TXMOD_GMCELL_SFT 12
+#define RG_GEMINIA_TXMOD_GMCELL_HI 13
+#define RG_GEMINIA_TXMOD_GMCELL_SZ 2
+#define RG_GEMINIA_TXLPF_GMCELL_MSK 0x0000c000
+#define RG_GEMINIA_TXLPF_GMCELL_I_MSK 0xffff3fff
+#define RG_GEMINIA_TXLPF_GMCELL_SFT 14
+#define RG_GEMINIA_TXLPF_GMCELL_HI 15
+#define RG_GEMINIA_TXLPF_GMCELL_SZ 2
+#define RG_GEMINIA_WF_TX_GAIN_OFFSET_MSK 0x000f0000
+#define RG_GEMINIA_WF_TX_GAIN_OFFSET_I_MSK 0xfff0ffff
+#define RG_GEMINIA_WF_TX_GAIN_OFFSET_SFT 16
+#define RG_GEMINIA_WF_TX_GAIN_OFFSET_HI 19
+#define RG_GEMINIA_WF_TX_GAIN_OFFSET_SZ 4
+#define RG_GEMINIA_BT_TX_GAIN_OFFSET_MSK 0x00f00000
+#define RG_GEMINIA_BT_TX_GAIN_OFFSET_I_MSK 0xff0fffff
+#define RG_GEMINIA_BT_TX_GAIN_OFFSET_SFT 20
+#define RG_GEMINIA_BT_TX_GAIN_OFFSET_HI 23
+#define RG_GEMINIA_BT_TX_GAIN_OFFSET_SZ 4
+#define RG_GEMINIA_TX_VTOI_CURRENT_MSK 0x03000000
+#define RG_GEMINIA_TX_VTOI_CURRENT_I_MSK 0xfcffffff
+#define RG_GEMINIA_TX_VTOI_CURRENT_SFT 24
+#define RG_GEMINIA_TX_VTOI_CURRENT_HI 25
+#define RG_GEMINIA_TX_VTOI_CURRENT_SZ 2
+#define RG_GEMINIA_TX_VTOI_GM_MSK 0x0c000000
+#define RG_GEMINIA_TX_VTOI_GM_I_MSK 0xf3ffffff
+#define RG_GEMINIA_TX_VTOI_GM_SFT 26
+#define RG_GEMINIA_TX_VTOI_GM_HI 27
+#define RG_GEMINIA_TX_VTOI_GM_SZ 2
+#define RG_GEMINIA_TX_VTOI_OPTION_MSK 0x30000000
+#define RG_GEMINIA_TX_VTOI_OPTION_I_MSK 0xcfffffff
+#define RG_GEMINIA_TX_VTOI_OPTION_SFT 28
+#define RG_GEMINIA_TX_VTOI_OPTION_HI 29
+#define RG_GEMINIA_TX_VTOI_OPTION_SZ 2
+#define RG_GEMINIA_TX_VTOI_FS_MSK 0x40000000
+#define RG_GEMINIA_TX_VTOI_FS_I_MSK 0xbfffffff
+#define RG_GEMINIA_TX_VTOI_FS_SFT 30
+#define RG_GEMINIA_TX_VTOI_FS_HI 30
+#define RG_GEMINIA_TX_VTOI_FS_SZ 1
+#define RG_GEMINIA_WF_RX_HG_LNA_GC_MSK 0x00000003
+#define RG_GEMINIA_WF_RX_HG_LNA_GC_I_MSK 0xfffffffc
+#define RG_GEMINIA_WF_RX_HG_LNA_GC_SFT 0
+#define RG_GEMINIA_WF_RX_HG_LNA_GC_HI 1
+#define RG_GEMINIA_WF_RX_HG_LNA_GC_SZ 2
+#define RG_GEMINIA_WF_RX_HG_TZ_GC_MSK 0x0000000c
+#define RG_GEMINIA_WF_RX_HG_TZ_GC_I_MSK 0xfffffff3
+#define RG_GEMINIA_WF_RX_HG_TZ_GC_SFT 2
+#define RG_GEMINIA_WF_RX_HG_TZ_GC_HI 3
+#define RG_GEMINIA_WF_RX_HG_TZ_GC_SZ 2
+#define RG_GEMINIA_WF_RX_HG_LNAHGN_BIAS_MSK 0x000000f0
+#define RG_GEMINIA_WF_RX_HG_LNAHGN_BIAS_I_MSK 0xffffff0f
+#define RG_GEMINIA_WF_RX_HG_LNAHGN_BIAS_SFT 4
+#define RG_GEMINIA_WF_RX_HG_LNAHGN_BIAS_HI 7
+#define RG_GEMINIA_WF_RX_HG_LNAHGN_BIAS_SZ 4
+#define RG_GEMINIA_WF_RX_HG_LNAHGP_BIAS_MSK 0x00000f00
+#define RG_GEMINIA_WF_RX_HG_LNAHGP_BIAS_I_MSK 0xfffff0ff
+#define RG_GEMINIA_WF_RX_HG_LNAHGP_BIAS_SFT 8
+#define RG_GEMINIA_WF_RX_HG_LNAHGP_BIAS_HI 11
+#define RG_GEMINIA_WF_RX_HG_LNAHGP_BIAS_SZ 4
+#define RG_GEMINIA_WF_RX_HG_LNALG_BIAS_MSK 0x0000f000
+#define RG_GEMINIA_WF_RX_HG_LNALG_BIAS_I_MSK 0xffff0fff
+#define RG_GEMINIA_WF_RX_HG_LNALG_BIAS_SFT 12
+#define RG_GEMINIA_WF_RX_HG_LNALG_BIAS_HI 15
+#define RG_GEMINIA_WF_RX_HG_LNALG_BIAS_SZ 4
+#define RG_GEMINIA_WF_RX_HG_TZ_CAP_MSK 0x00070000
+#define RG_GEMINIA_WF_RX_HG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_GEMINIA_WF_RX_HG_TZ_CAP_SFT 16
+#define RG_GEMINIA_WF_RX_HG_TZ_CAP_HI 18
+#define RG_GEMINIA_WF_RX_HG_TZ_CAP_SZ 3
+#define RG_GEMINIA_WF_RX_HG_SQDC_MSK 0x00700000
+#define RG_GEMINIA_WF_RX_HG_SQDC_I_MSK 0xff8fffff
+#define RG_GEMINIA_WF_RX_HG_SQDC_SFT 20
+#define RG_GEMINIA_WF_RX_HG_SQDC_HI 22
+#define RG_GEMINIA_WF_RX_HG_SQDC_SZ 3
+#define RG_GEMINIA_WF_RX_HG_DIV2_CORE_MSK 0x01800000
+#define RG_GEMINIA_WF_RX_HG_DIV2_CORE_I_MSK 0xfe7fffff
+#define RG_GEMINIA_WF_RX_HG_DIV2_CORE_SFT 23
+#define RG_GEMINIA_WF_RX_HG_DIV2_CORE_HI 24
+#define RG_GEMINIA_WF_RX_HG_DIV2_CORE_SZ 2
+#define RG_GEMINIA_WF_RX_HG_LOBUF_MSK 0x06000000
+#define RG_GEMINIA_WF_RX_HG_LOBUF_I_MSK 0xf9ffffff
+#define RG_GEMINIA_WF_RX_HG_LOBUF_SFT 25
+#define RG_GEMINIA_WF_RX_HG_LOBUF_HI 26
+#define RG_GEMINIA_WF_RX_HG_LOBUF_SZ 2
+#define RG_GEMINIA_WF_RX_HG_TZI_MSK 0x38000000
+#define RG_GEMINIA_WF_RX_HG_TZI_I_MSK 0xc7ffffff
+#define RG_GEMINIA_WF_RX_HG_TZI_SFT 27
+#define RG_GEMINIA_WF_RX_HG_TZI_HI 29
+#define RG_GEMINIA_WF_RX_HG_TZI_SZ 3
+#define RG_GEMINIA_WF_RX_HG_TZ_VCM_MSK 0xc0000000
+#define RG_GEMINIA_WF_RX_HG_TZ_VCM_I_MSK 0x3fffffff
+#define RG_GEMINIA_WF_RX_HG_TZ_VCM_SFT 30
+#define RG_GEMINIA_WF_RX_HG_TZ_VCM_HI 31
+#define RG_GEMINIA_WF_RX_HG_TZ_VCM_SZ 2
+#define RG_GEMINIA_WF_RX_MG_LNA_GC_MSK 0x00000003
+#define RG_GEMINIA_WF_RX_MG_LNA_GC_I_MSK 0xfffffffc
+#define RG_GEMINIA_WF_RX_MG_LNA_GC_SFT 0
+#define RG_GEMINIA_WF_RX_MG_LNA_GC_HI 1
+#define RG_GEMINIA_WF_RX_MG_LNA_GC_SZ 2
+#define RG_GEMINIA_WF_RX_MG_TZ_GC_MSK 0x0000000c
+#define RG_GEMINIA_WF_RX_MG_TZ_GC_I_MSK 0xfffffff3
+#define RG_GEMINIA_WF_RX_MG_TZ_GC_SFT 2
+#define RG_GEMINIA_WF_RX_MG_TZ_GC_HI 3
+#define RG_GEMINIA_WF_RX_MG_TZ_GC_SZ 2
+#define RG_GEMINIA_WF_RX_MG_LNAHGN_BIAS_MSK 0x000000f0
+#define RG_GEMINIA_WF_RX_MG_LNAHGN_BIAS_I_MSK 0xffffff0f
+#define RG_GEMINIA_WF_RX_MG_LNAHGN_BIAS_SFT 4
+#define RG_GEMINIA_WF_RX_MG_LNAHGN_BIAS_HI 7
+#define RG_GEMINIA_WF_RX_MG_LNAHGN_BIAS_SZ 4
+#define RG_GEMINIA_WF_RX_MG_LNAHGP_BIAS_MSK 0x00000f00
+#define RG_GEMINIA_WF_RX_MG_LNAHGP_BIAS_I_MSK 0xfffff0ff
+#define RG_GEMINIA_WF_RX_MG_LNAHGP_BIAS_SFT 8
+#define RG_GEMINIA_WF_RX_MG_LNAHGP_BIAS_HI 11
+#define RG_GEMINIA_WF_RX_MG_LNAHGP_BIAS_SZ 4
+#define RG_GEMINIA_WF_RX_MG_LNALG_BIAS_MSK 0x0000f000
+#define RG_GEMINIA_WF_RX_MG_LNALG_BIAS_I_MSK 0xffff0fff
+#define RG_GEMINIA_WF_RX_MG_LNALG_BIAS_SFT 12
+#define RG_GEMINIA_WF_RX_MG_LNALG_BIAS_HI 15
+#define RG_GEMINIA_WF_RX_MG_LNALG_BIAS_SZ 4
+#define RG_GEMINIA_WF_RX_MG_TZ_CAP_MSK 0x00070000
+#define RG_GEMINIA_WF_RX_MG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_GEMINIA_WF_RX_MG_TZ_CAP_SFT 16
+#define RG_GEMINIA_WF_RX_MG_TZ_CAP_HI 18
+#define RG_GEMINIA_WF_RX_MG_TZ_CAP_SZ 3
+#define RG_GEMINIA_WF_RX_MG_SQDC_MSK 0x00700000
+#define RG_GEMINIA_WF_RX_MG_SQDC_I_MSK 0xff8fffff
+#define RG_GEMINIA_WF_RX_MG_SQDC_SFT 20
+#define RG_GEMINIA_WF_RX_MG_SQDC_HI 22
+#define RG_GEMINIA_WF_RX_MG_SQDC_SZ 3
+#define RG_GEMINIA_WF_RX_MG_DIV2_CORE_MSK 0x01800000
+#define RG_GEMINIA_WF_RX_MG_DIV2_CORE_I_MSK 0xfe7fffff
+#define RG_GEMINIA_WF_RX_MG_DIV2_CORE_SFT 23
+#define RG_GEMINIA_WF_RX_MG_DIV2_CORE_HI 24
+#define RG_GEMINIA_WF_RX_MG_DIV2_CORE_SZ 2
+#define RG_GEMINIA_WF_RX_MG_LOBUF_MSK 0x06000000
+#define RG_GEMINIA_WF_RX_MG_LOBUF_I_MSK 0xf9ffffff
+#define RG_GEMINIA_WF_RX_MG_LOBUF_SFT 25
+#define RG_GEMINIA_WF_RX_MG_LOBUF_HI 26
+#define RG_GEMINIA_WF_RX_MG_LOBUF_SZ 2
+#define RG_GEMINIA_WF_RX_MG_TZI_MSK 0x38000000
+#define RG_GEMINIA_WF_RX_MG_TZI_I_MSK 0xc7ffffff
+#define RG_GEMINIA_WF_RX_MG_TZI_SFT 27
+#define RG_GEMINIA_WF_RX_MG_TZI_HI 29
+#define RG_GEMINIA_WF_RX_MG_TZI_SZ 3
+#define RG_GEMINIA_WF_RX_MG_TZ_VCM_MSK 0xc0000000
+#define RG_GEMINIA_WF_RX_MG_TZ_VCM_I_MSK 0x3fffffff
+#define RG_GEMINIA_WF_RX_MG_TZ_VCM_SFT 30
+#define RG_GEMINIA_WF_RX_MG_TZ_VCM_HI 31
+#define RG_GEMINIA_WF_RX_MG_TZ_VCM_SZ 2
+#define RG_GEMINIA_WF_RX_LG_LNA_GC_MSK 0x00000003
+#define RG_GEMINIA_WF_RX_LG_LNA_GC_I_MSK 0xfffffffc
+#define RG_GEMINIA_WF_RX_LG_LNA_GC_SFT 0
+#define RG_GEMINIA_WF_RX_LG_LNA_GC_HI 1
+#define RG_GEMINIA_WF_RX_LG_LNA_GC_SZ 2
+#define RG_GEMINIA_WF_RX_LG_TZ_GC_MSK 0x0000000c
+#define RG_GEMINIA_WF_RX_LG_TZ_GC_I_MSK 0xfffffff3
+#define RG_GEMINIA_WF_RX_LG_TZ_GC_SFT 2
+#define RG_GEMINIA_WF_RX_LG_TZ_GC_HI 3
+#define RG_GEMINIA_WF_RX_LG_TZ_GC_SZ 2
+#define RG_GEMINIA_WF_RX_LG_LNAHGN_BIAS_MSK 0x000000f0
+#define RG_GEMINIA_WF_RX_LG_LNAHGN_BIAS_I_MSK 0xffffff0f
+#define RG_GEMINIA_WF_RX_LG_LNAHGN_BIAS_SFT 4
+#define RG_GEMINIA_WF_RX_LG_LNAHGN_BIAS_HI 7
+#define RG_GEMINIA_WF_RX_LG_LNAHGN_BIAS_SZ 4
+#define RG_GEMINIA_WF_RX_LG_LNAHGP_BIAS_MSK 0x00000f00
+#define RG_GEMINIA_WF_RX_LG_LNAHGP_BIAS_I_MSK 0xfffff0ff
+#define RG_GEMINIA_WF_RX_LG_LNAHGP_BIAS_SFT 8
+#define RG_GEMINIA_WF_RX_LG_LNAHGP_BIAS_HI 11
+#define RG_GEMINIA_WF_RX_LG_LNAHGP_BIAS_SZ 4
+#define RG_GEMINIA_WF_RX_LG_LNALG_BIAS_MSK 0x0000f000
+#define RG_GEMINIA_WF_RX_LG_LNALG_BIAS_I_MSK 0xffff0fff
+#define RG_GEMINIA_WF_RX_LG_LNALG_BIAS_SFT 12
+#define RG_GEMINIA_WF_RX_LG_LNALG_BIAS_HI 15
+#define RG_GEMINIA_WF_RX_LG_LNALG_BIAS_SZ 4
+#define RG_GEMINIA_WF_RX_LG_TZ_CAP_MSK 0x00070000
+#define RG_GEMINIA_WF_RX_LG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_GEMINIA_WF_RX_LG_TZ_CAP_SFT 16
+#define RG_GEMINIA_WF_RX_LG_TZ_CAP_HI 18
+#define RG_GEMINIA_WF_RX_LG_TZ_CAP_SZ 3
+#define RG_GEMINIA_WF_RX_LG_SQDC_MSK 0x00700000
+#define RG_GEMINIA_WF_RX_LG_SQDC_I_MSK 0xff8fffff
+#define RG_GEMINIA_WF_RX_LG_SQDC_SFT 20
+#define RG_GEMINIA_WF_RX_LG_SQDC_HI 22
+#define RG_GEMINIA_WF_RX_LG_SQDC_SZ 3
+#define RG_GEMINIA_WF_RX_LG_DIV2_CORE_MSK 0x01800000
+#define RG_GEMINIA_WF_RX_LG_DIV2_CORE_I_MSK 0xfe7fffff
+#define RG_GEMINIA_WF_RX_LG_DIV2_CORE_SFT 23
+#define RG_GEMINIA_WF_RX_LG_DIV2_CORE_HI 24
+#define RG_GEMINIA_WF_RX_LG_DIV2_CORE_SZ 2
+#define RG_GEMINIA_WF_RX_LG_LOBUF_MSK 0x06000000
+#define RG_GEMINIA_WF_RX_LG_LOBUF_I_MSK 0xf9ffffff
+#define RG_GEMINIA_WF_RX_LG_LOBUF_SFT 25
+#define RG_GEMINIA_WF_RX_LG_LOBUF_HI 26
+#define RG_GEMINIA_WF_RX_LG_LOBUF_SZ 2
+#define RG_GEMINIA_WF_RX_LG_TZI_MSK 0x38000000
+#define RG_GEMINIA_WF_RX_LG_TZI_I_MSK 0xc7ffffff
+#define RG_GEMINIA_WF_RX_LG_TZI_SFT 27
+#define RG_GEMINIA_WF_RX_LG_TZI_HI 29
+#define RG_GEMINIA_WF_RX_LG_TZI_SZ 3
+#define RG_GEMINIA_WF_RX_LG_TZ_VCM_MSK 0xc0000000
+#define RG_GEMINIA_WF_RX_LG_TZ_VCM_I_MSK 0x3fffffff
+#define RG_GEMINIA_WF_RX_LG_TZ_VCM_SFT 30
+#define RG_GEMINIA_WF_RX_LG_TZ_VCM_HI 31
+#define RG_GEMINIA_WF_RX_LG_TZ_VCM_SZ 2
+#define RG_GEMINIA_WF_RX_ULG_LNA_GC_MSK 0x00000003
+#define RG_GEMINIA_WF_RX_ULG_LNA_GC_I_MSK 0xfffffffc
+#define RG_GEMINIA_WF_RX_ULG_LNA_GC_SFT 0
+#define RG_GEMINIA_WF_RX_ULG_LNA_GC_HI 1
+#define RG_GEMINIA_WF_RX_ULG_LNA_GC_SZ 2
+#define RG_GEMINIA_WF_RX_ULG_TZ_GC_MSK 0x0000000c
+#define RG_GEMINIA_WF_RX_ULG_TZ_GC_I_MSK 0xfffffff3
+#define RG_GEMINIA_WF_RX_ULG_TZ_GC_SFT 2
+#define RG_GEMINIA_WF_RX_ULG_TZ_GC_HI 3
+#define RG_GEMINIA_WF_RX_ULG_TZ_GC_SZ 2
+#define RG_GEMINIA_WF_RX_ULG_LNAHGN_BIAS_MSK 0x000000f0
+#define RG_GEMINIA_WF_RX_ULG_LNAHGN_BIAS_I_MSK 0xffffff0f
+#define RG_GEMINIA_WF_RX_ULG_LNAHGN_BIAS_SFT 4
+#define RG_GEMINIA_WF_RX_ULG_LNAHGN_BIAS_HI 7
+#define RG_GEMINIA_WF_RX_ULG_LNAHGN_BIAS_SZ 4
+#define RG_GEMINIA_WF_RX_ULG_LNAHGP_BIAS_MSK 0x00000f00
+#define RG_GEMINIA_WF_RX_ULG_LNAHGP_BIAS_I_MSK 0xfffff0ff
+#define RG_GEMINIA_WF_RX_ULG_LNAHGP_BIAS_SFT 8
+#define RG_GEMINIA_WF_RX_ULG_LNAHGP_BIAS_HI 11
+#define RG_GEMINIA_WF_RX_ULG_LNAHGP_BIAS_SZ 4
+#define RG_GEMINIA_WF_RX_ULG_LNALG_BIAS_MSK 0x0000f000
+#define RG_GEMINIA_WF_RX_ULG_LNALG_BIAS_I_MSK 0xffff0fff
+#define RG_GEMINIA_WF_RX_ULG_LNALG_BIAS_SFT 12
+#define RG_GEMINIA_WF_RX_ULG_LNALG_BIAS_HI 15
+#define RG_GEMINIA_WF_RX_ULG_LNALG_BIAS_SZ 4
+#define RG_GEMINIA_WF_RX_ULG_TZ_CAP_MSK 0x00070000
+#define RG_GEMINIA_WF_RX_ULG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_GEMINIA_WF_RX_ULG_TZ_CAP_SFT 16
+#define RG_GEMINIA_WF_RX_ULG_TZ_CAP_HI 18
+#define RG_GEMINIA_WF_RX_ULG_TZ_CAP_SZ 3
+#define RG_GEMINIA_WF_RX_ULG_SQDC_MSK 0x00700000
+#define RG_GEMINIA_WF_RX_ULG_SQDC_I_MSK 0xff8fffff
+#define RG_GEMINIA_WF_RX_ULG_SQDC_SFT 20
+#define RG_GEMINIA_WF_RX_ULG_SQDC_HI 22
+#define RG_GEMINIA_WF_RX_ULG_SQDC_SZ 3
+#define RG_GEMINIA_WF_RX_ULG_DIV2_CORE_MSK 0x01800000
+#define RG_GEMINIA_WF_RX_ULG_DIV2_CORE_I_MSK 0xfe7fffff
+#define RG_GEMINIA_WF_RX_ULG_DIV2_CORE_SFT 23
+#define RG_GEMINIA_WF_RX_ULG_DIV2_CORE_HI 24
+#define RG_GEMINIA_WF_RX_ULG_DIV2_CORE_SZ 2
+#define RG_GEMINIA_WF_RX_ULG_LOBUF_MSK 0x06000000
+#define RG_GEMINIA_WF_RX_ULG_LOBUF_I_MSK 0xf9ffffff
+#define RG_GEMINIA_WF_RX_ULG_LOBUF_SFT 25
+#define RG_GEMINIA_WF_RX_ULG_LOBUF_HI 26
+#define RG_GEMINIA_WF_RX_ULG_LOBUF_SZ 2
+#define RG_GEMINIA_WF_RX_ULG_TZI_MSK 0x38000000
+#define RG_GEMINIA_WF_RX_ULG_TZI_I_MSK 0xc7ffffff
+#define RG_GEMINIA_WF_RX_ULG_TZI_SFT 27
+#define RG_GEMINIA_WF_RX_ULG_TZI_HI 29
+#define RG_GEMINIA_WF_RX_ULG_TZI_SZ 3
+#define RG_GEMINIA_WF_RX_ULG_TZ_VCM_MSK 0xc0000000
+#define RG_GEMINIA_WF_RX_ULG_TZ_VCM_I_MSK 0x3fffffff
+#define RG_GEMINIA_WF_RX_ULG_TZ_VCM_SFT 30
+#define RG_GEMINIA_WF_RX_ULG_TZ_VCM_HI 31
+#define RG_GEMINIA_WF_RX_ULG_TZ_VCM_SZ 2
+#define RG_GEMINIA_BT_RX_HG_LNA_GC_MSK 0x00000003
+#define RG_GEMINIA_BT_RX_HG_LNA_GC_I_MSK 0xfffffffc
+#define RG_GEMINIA_BT_RX_HG_LNA_GC_SFT 0
+#define RG_GEMINIA_BT_RX_HG_LNA_GC_HI 1
+#define RG_GEMINIA_BT_RX_HG_LNA_GC_SZ 2
+#define RG_GEMINIA_BT_RX_HG_TZ_GC_MSK 0x0000000c
+#define RG_GEMINIA_BT_RX_HG_TZ_GC_I_MSK 0xfffffff3
+#define RG_GEMINIA_BT_RX_HG_TZ_GC_SFT 2
+#define RG_GEMINIA_BT_RX_HG_TZ_GC_HI 3
+#define RG_GEMINIA_BT_RX_HG_TZ_GC_SZ 2
+#define RG_GEMINIA_BT_RX_HG_LNAHGN_BIAS_MSK 0x000000f0
+#define RG_GEMINIA_BT_RX_HG_LNAHGN_BIAS_I_MSK 0xffffff0f
+#define RG_GEMINIA_BT_RX_HG_LNAHGN_BIAS_SFT 4
+#define RG_GEMINIA_BT_RX_HG_LNAHGN_BIAS_HI 7
+#define RG_GEMINIA_BT_RX_HG_LNAHGN_BIAS_SZ 4
+#define RG_GEMINIA_BT_RX_HG_LNAHGP_BIAS_MSK 0x00000f00
+#define RG_GEMINIA_BT_RX_HG_LNAHGP_BIAS_I_MSK 0xfffff0ff
+#define RG_GEMINIA_BT_RX_HG_LNAHGP_BIAS_SFT 8
+#define RG_GEMINIA_BT_RX_HG_LNAHGP_BIAS_HI 11
+#define RG_GEMINIA_BT_RX_HG_LNAHGP_BIAS_SZ 4
+#define RG_GEMINIA_BT_RX_HG_LNALG_BIAS_MSK 0x0000f000
+#define RG_GEMINIA_BT_RX_HG_LNALG_BIAS_I_MSK 0xffff0fff
+#define RG_GEMINIA_BT_RX_HG_LNALG_BIAS_SFT 12
+#define RG_GEMINIA_BT_RX_HG_LNALG_BIAS_HI 15
+#define RG_GEMINIA_BT_RX_HG_LNALG_BIAS_SZ 4
+#define RG_GEMINIA_BT_RX_HG_TZ_CAP_MSK 0x00070000
+#define RG_GEMINIA_BT_RX_HG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_GEMINIA_BT_RX_HG_TZ_CAP_SFT 16
+#define RG_GEMINIA_BT_RX_HG_TZ_CAP_HI 18
+#define RG_GEMINIA_BT_RX_HG_TZ_CAP_SZ 3
+#define RG_GEMINIA_BT_RX_HG_SQDC_MSK 0x00700000
+#define RG_GEMINIA_BT_RX_HG_SQDC_I_MSK 0xff8fffff
+#define RG_GEMINIA_BT_RX_HG_SQDC_SFT 20
+#define RG_GEMINIA_BT_RX_HG_SQDC_HI 22
+#define RG_GEMINIA_BT_RX_HG_SQDC_SZ 3
+#define RG_GEMINIA_BT_RX_HG_DIV2_CORE_MSK 0x01800000
+#define RG_GEMINIA_BT_RX_HG_DIV2_CORE_I_MSK 0xfe7fffff
+#define RG_GEMINIA_BT_RX_HG_DIV2_CORE_SFT 23
+#define RG_GEMINIA_BT_RX_HG_DIV2_CORE_HI 24
+#define RG_GEMINIA_BT_RX_HG_DIV2_CORE_SZ 2
+#define RG_GEMINIA_BT_RX_HG_LOBUF_MSK 0x06000000
+#define RG_GEMINIA_BT_RX_HG_LOBUF_I_MSK 0xf9ffffff
+#define RG_GEMINIA_BT_RX_HG_LOBUF_SFT 25
+#define RG_GEMINIA_BT_RX_HG_LOBUF_HI 26
+#define RG_GEMINIA_BT_RX_HG_LOBUF_SZ 2
+#define RG_GEMINIA_BT_RX_HG_TZI_MSK 0x38000000
+#define RG_GEMINIA_BT_RX_HG_TZI_I_MSK 0xc7ffffff
+#define RG_GEMINIA_BT_RX_HG_TZI_SFT 27
+#define RG_GEMINIA_BT_RX_HG_TZI_HI 29
+#define RG_GEMINIA_BT_RX_HG_TZI_SZ 3
+#define RG_GEMINIA_BT_RX_HG_TZ_VCM_MSK 0xc0000000
+#define RG_GEMINIA_BT_RX_HG_TZ_VCM_I_MSK 0x3fffffff
+#define RG_GEMINIA_BT_RX_HG_TZ_VCM_SFT 30
+#define RG_GEMINIA_BT_RX_HG_TZ_VCM_HI 31
+#define RG_GEMINIA_BT_RX_HG_TZ_VCM_SZ 2
+#define RG_GEMINIA_BT_RX_MG_LNA_GC_MSK 0x00000003
+#define RG_GEMINIA_BT_RX_MG_LNA_GC_I_MSK 0xfffffffc
+#define RG_GEMINIA_BT_RX_MG_LNA_GC_SFT 0
+#define RG_GEMINIA_BT_RX_MG_LNA_GC_HI 1
+#define RG_GEMINIA_BT_RX_MG_LNA_GC_SZ 2
+#define RG_GEMINIA_BT_RX_MG_TZ_GC_MSK 0x0000000c
+#define RG_GEMINIA_BT_RX_MG_TZ_GC_I_MSK 0xfffffff3
+#define RG_GEMINIA_BT_RX_MG_TZ_GC_SFT 2
+#define RG_GEMINIA_BT_RX_MG_TZ_GC_HI 3
+#define RG_GEMINIA_BT_RX_MG_TZ_GC_SZ 2
+#define RG_GEMINIA_BT_RX_MG_LNAHGN_BIAS_MSK 0x000000f0
+#define RG_GEMINIA_BT_RX_MG_LNAHGN_BIAS_I_MSK 0xffffff0f
+#define RG_GEMINIA_BT_RX_MG_LNAHGN_BIAS_SFT 4
+#define RG_GEMINIA_BT_RX_MG_LNAHGN_BIAS_HI 7
+#define RG_GEMINIA_BT_RX_MG_LNAHGN_BIAS_SZ 4
+#define RG_GEMINIA_BT_RX_MG_LNAHGP_BIAS_MSK 0x00000f00
+#define RG_GEMINIA_BT_RX_MG_LNAHGP_BIAS_I_MSK 0xfffff0ff
+#define RG_GEMINIA_BT_RX_MG_LNAHGP_BIAS_SFT 8
+#define RG_GEMINIA_BT_RX_MG_LNAHGP_BIAS_HI 11
+#define RG_GEMINIA_BT_RX_MG_LNAHGP_BIAS_SZ 4
+#define RG_GEMINIA_BT_RX_MG_LNALG_BIAS_MSK 0x0000f000
+#define RG_GEMINIA_BT_RX_MG_LNALG_BIAS_I_MSK 0xffff0fff
+#define RG_GEMINIA_BT_RX_MG_LNALG_BIAS_SFT 12
+#define RG_GEMINIA_BT_RX_MG_LNALG_BIAS_HI 15
+#define RG_GEMINIA_BT_RX_MG_LNALG_BIAS_SZ 4
+#define RG_GEMINIA_BT_RX_MG_TZ_CAP_MSK 0x00070000
+#define RG_GEMINIA_BT_RX_MG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_GEMINIA_BT_RX_MG_TZ_CAP_SFT 16
+#define RG_GEMINIA_BT_RX_MG_TZ_CAP_HI 18
+#define RG_GEMINIA_BT_RX_MG_TZ_CAP_SZ 3
+#define RG_GEMINIA_BT_RX_MG_SQDC_MSK 0x00700000
+#define RG_GEMINIA_BT_RX_MG_SQDC_I_MSK 0xff8fffff
+#define RG_GEMINIA_BT_RX_MG_SQDC_SFT 20
+#define RG_GEMINIA_BT_RX_MG_SQDC_HI 22
+#define RG_GEMINIA_BT_RX_MG_SQDC_SZ 3
+#define RG_GEMINIA_BT_RX_MG_DIV2_CORE_MSK 0x01800000
+#define RG_GEMINIA_BT_RX_MG_DIV2_CORE_I_MSK 0xfe7fffff
+#define RG_GEMINIA_BT_RX_MG_DIV2_CORE_SFT 23
+#define RG_GEMINIA_BT_RX_MG_DIV2_CORE_HI 24
+#define RG_GEMINIA_BT_RX_MG_DIV2_CORE_SZ 2
+#define RG_GEMINIA_BT_RX_MG_LOBUF_MSK 0x06000000
+#define RG_GEMINIA_BT_RX_MG_LOBUF_I_MSK 0xf9ffffff
+#define RG_GEMINIA_BT_RX_MG_LOBUF_SFT 25
+#define RG_GEMINIA_BT_RX_MG_LOBUF_HI 26
+#define RG_GEMINIA_BT_RX_MG_LOBUF_SZ 2
+#define RG_GEMINIA_BT_RX_MG_TZI_MSK 0x38000000
+#define RG_GEMINIA_BT_RX_MG_TZI_I_MSK 0xc7ffffff
+#define RG_GEMINIA_BT_RX_MG_TZI_SFT 27
+#define RG_GEMINIA_BT_RX_MG_TZI_HI 29
+#define RG_GEMINIA_BT_RX_MG_TZI_SZ 3
+#define RG_GEMINIA_BT_RX_MG_TZ_VCM_MSK 0xc0000000
+#define RG_GEMINIA_BT_RX_MG_TZ_VCM_I_MSK 0x3fffffff
+#define RG_GEMINIA_BT_RX_MG_TZ_VCM_SFT 30
+#define RG_GEMINIA_BT_RX_MG_TZ_VCM_HI 31
+#define RG_GEMINIA_BT_RX_MG_TZ_VCM_SZ 2
+#define RG_GEMINIA_BT_RX_LG_LNA_GC_MSK 0x00000003
+#define RG_GEMINIA_BT_RX_LG_LNA_GC_I_MSK 0xfffffffc
+#define RG_GEMINIA_BT_RX_LG_LNA_GC_SFT 0
+#define RG_GEMINIA_BT_RX_LG_LNA_GC_HI 1
+#define RG_GEMINIA_BT_RX_LG_LNA_GC_SZ 2
+#define RG_GEMINIA_BT_RX_LG_TZ_GC_MSK 0x0000000c
+#define RG_GEMINIA_BT_RX_LG_TZ_GC_I_MSK 0xfffffff3
+#define RG_GEMINIA_BT_RX_LG_TZ_GC_SFT 2
+#define RG_GEMINIA_BT_RX_LG_TZ_GC_HI 3
+#define RG_GEMINIA_BT_RX_LG_TZ_GC_SZ 2
+#define RG_GEMINIA_BT_RX_LG_LNAHGN_BIAS_MSK 0x000000f0
+#define RG_GEMINIA_BT_RX_LG_LNAHGN_BIAS_I_MSK 0xffffff0f
+#define RG_GEMINIA_BT_RX_LG_LNAHGN_BIAS_SFT 4
+#define RG_GEMINIA_BT_RX_LG_LNAHGN_BIAS_HI 7
+#define RG_GEMINIA_BT_RX_LG_LNAHGN_BIAS_SZ 4
+#define RG_GEMINIA_BT_RX_LG_LNAHGP_BIAS_MSK 0x00000f00
+#define RG_GEMINIA_BT_RX_LG_LNAHGP_BIAS_I_MSK 0xfffff0ff
+#define RG_GEMINIA_BT_RX_LG_LNAHGP_BIAS_SFT 8
+#define RG_GEMINIA_BT_RX_LG_LNAHGP_BIAS_HI 11
+#define RG_GEMINIA_BT_RX_LG_LNAHGP_BIAS_SZ 4
+#define RG_GEMINIA_BT_RX_LG_LNALG_BIAS_MSK 0x0000f000
+#define RG_GEMINIA_BT_RX_LG_LNALG_BIAS_I_MSK 0xffff0fff
+#define RG_GEMINIA_BT_RX_LG_LNALG_BIAS_SFT 12
+#define RG_GEMINIA_BT_RX_LG_LNALG_BIAS_HI 15
+#define RG_GEMINIA_BT_RX_LG_LNALG_BIAS_SZ 4
+#define RG_GEMINIA_BT_RX_LG_TZ_CAP_MSK 0x00070000
+#define RG_GEMINIA_BT_RX_LG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_GEMINIA_BT_RX_LG_TZ_CAP_SFT 16
+#define RG_GEMINIA_BT_RX_LG_TZ_CAP_HI 18
+#define RG_GEMINIA_BT_RX_LG_TZ_CAP_SZ 3
+#define RG_GEMINIA_BT_RX_LG_SQDC_MSK 0x00700000
+#define RG_GEMINIA_BT_RX_LG_SQDC_I_MSK 0xff8fffff
+#define RG_GEMINIA_BT_RX_LG_SQDC_SFT 20
+#define RG_GEMINIA_BT_RX_LG_SQDC_HI 22
+#define RG_GEMINIA_BT_RX_LG_SQDC_SZ 3
+#define RG_GEMINIA_BT_RX_LG_DIV2_CORE_MSK 0x01800000
+#define RG_GEMINIA_BT_RX_LG_DIV2_CORE_I_MSK 0xfe7fffff
+#define RG_GEMINIA_BT_RX_LG_DIV2_CORE_SFT 23
+#define RG_GEMINIA_BT_RX_LG_DIV2_CORE_HI 24
+#define RG_GEMINIA_BT_RX_LG_DIV2_CORE_SZ 2
+#define RG_GEMINIA_BT_RX_LG_LOBUF_MSK 0x06000000
+#define RG_GEMINIA_BT_RX_LG_LOBUF_I_MSK 0xf9ffffff
+#define RG_GEMINIA_BT_RX_LG_LOBUF_SFT 25
+#define RG_GEMINIA_BT_RX_LG_LOBUF_HI 26
+#define RG_GEMINIA_BT_RX_LG_LOBUF_SZ 2
+#define RG_GEMINIA_BT_RX_LG_TZI_MSK 0x38000000
+#define RG_GEMINIA_BT_RX_LG_TZI_I_MSK 0xc7ffffff
+#define RG_GEMINIA_BT_RX_LG_TZI_SFT 27
+#define RG_GEMINIA_BT_RX_LG_TZI_HI 29
+#define RG_GEMINIA_BT_RX_LG_TZI_SZ 3
+#define RG_GEMINIA_BT_RX_LG_TZ_VCM_MSK 0xc0000000
+#define RG_GEMINIA_BT_RX_LG_TZ_VCM_I_MSK 0x3fffffff
+#define RG_GEMINIA_BT_RX_LG_TZ_VCM_SFT 30
+#define RG_GEMINIA_BT_RX_LG_TZ_VCM_HI 31
+#define RG_GEMINIA_BT_RX_LG_TZ_VCM_SZ 2
+#define RG_GEMINIA_BT_RX_ULG_LNA_GC_MSK 0x00000003
+#define RG_GEMINIA_BT_RX_ULG_LNA_GC_I_MSK 0xfffffffc
+#define RG_GEMINIA_BT_RX_ULG_LNA_GC_SFT 0
+#define RG_GEMINIA_BT_RX_ULG_LNA_GC_HI 1
+#define RG_GEMINIA_BT_RX_ULG_LNA_GC_SZ 2
+#define RG_GEMINIA_BT_RX_ULG_TZ_GC_MSK 0x0000000c
+#define RG_GEMINIA_BT_RX_ULG_TZ_GC_I_MSK 0xfffffff3
+#define RG_GEMINIA_BT_RX_ULG_TZ_GC_SFT 2
+#define RG_GEMINIA_BT_RX_ULG_TZ_GC_HI 3
+#define RG_GEMINIA_BT_RX_ULG_TZ_GC_SZ 2
+#define RG_GEMINIA_BT_RX_ULG_LNAHGN_BIAS_MSK 0x000000f0
+#define RG_GEMINIA_BT_RX_ULG_LNAHGN_BIAS_I_MSK 0xffffff0f
+#define RG_GEMINIA_BT_RX_ULG_LNAHGN_BIAS_SFT 4
+#define RG_GEMINIA_BT_RX_ULG_LNAHGN_BIAS_HI 7
+#define RG_GEMINIA_BT_RX_ULG_LNAHGN_BIAS_SZ 4
+#define RG_GEMINIA_BT_RX_ULG_LNAHGP_BIAS_MSK 0x00000f00
+#define RG_GEMINIA_BT_RX_ULG_LNAHGP_BIAS_I_MSK 0xfffff0ff
+#define RG_GEMINIA_BT_RX_ULG_LNAHGP_BIAS_SFT 8
+#define RG_GEMINIA_BT_RX_ULG_LNAHGP_BIAS_HI 11
+#define RG_GEMINIA_BT_RX_ULG_LNAHGP_BIAS_SZ 4
+#define RG_GEMINIA_BT_RX_ULG_LNALG_BIAS_MSK 0x0000f000
+#define RG_GEMINIA_BT_RX_ULG_LNALG_BIAS_I_MSK 0xffff0fff
+#define RG_GEMINIA_BT_RX_ULG_LNALG_BIAS_SFT 12
+#define RG_GEMINIA_BT_RX_ULG_LNALG_BIAS_HI 15
+#define RG_GEMINIA_BT_RX_ULG_LNALG_BIAS_SZ 4
+#define RG_GEMINIA_BT_RX_ULG_TZ_CAP_MSK 0x00070000
+#define RG_GEMINIA_BT_RX_ULG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_GEMINIA_BT_RX_ULG_TZ_CAP_SFT 16
+#define RG_GEMINIA_BT_RX_ULG_TZ_CAP_HI 18
+#define RG_GEMINIA_BT_RX_ULG_TZ_CAP_SZ 3
+#define RG_GEMINIA_BT_RX_ULG_SQDC_MSK 0x00700000
+#define RG_GEMINIA_BT_RX_ULG_SQDC_I_MSK 0xff8fffff
+#define RG_GEMINIA_BT_RX_ULG_SQDC_SFT 20
+#define RG_GEMINIA_BT_RX_ULG_SQDC_HI 22
+#define RG_GEMINIA_BT_RX_ULG_SQDC_SZ 3
+#define RG_GEMINIA_BT_RX_ULG_DIV2_CORE_MSK 0x01800000
+#define RG_GEMINIA_BT_RX_ULG_DIV2_CORE_I_MSK 0xfe7fffff
+#define RG_GEMINIA_BT_RX_ULG_DIV2_CORE_SFT 23
+#define RG_GEMINIA_BT_RX_ULG_DIV2_CORE_HI 24
+#define RG_GEMINIA_BT_RX_ULG_DIV2_CORE_SZ 2
+#define RG_GEMINIA_BT_RX_ULG_LOBUF_MSK 0x06000000
+#define RG_GEMINIA_BT_RX_ULG_LOBUF_I_MSK 0xf9ffffff
+#define RG_GEMINIA_BT_RX_ULG_LOBUF_SFT 25
+#define RG_GEMINIA_BT_RX_ULG_LOBUF_HI 26
+#define RG_GEMINIA_BT_RX_ULG_LOBUF_SZ 2
+#define RG_GEMINIA_BT_RX_ULG_TZI_MSK 0x38000000
+#define RG_GEMINIA_BT_RX_ULG_TZI_I_MSK 0xc7ffffff
+#define RG_GEMINIA_BT_RX_ULG_TZI_SFT 27
+#define RG_GEMINIA_BT_RX_ULG_TZI_HI 29
+#define RG_GEMINIA_BT_RX_ULG_TZI_SZ 3
+#define RG_GEMINIA_BT_RX_ULG_TZ_VCM_MSK 0xc0000000
+#define RG_GEMINIA_BT_RX_ULG_TZ_VCM_I_MSK 0x3fffffff
+#define RG_GEMINIA_BT_RX_ULG_TZ_VCM_SFT 30
+#define RG_GEMINIA_BT_RX_ULG_TZ_VCM_HI 31
+#define RG_GEMINIA_BT_RX_ULG_TZ_VCM_SZ 2
+#define RG_GEMINIA_RX_ADC_CLKSEL_MSK 0x00000001
+#define RG_GEMINIA_RX_ADC_CLKSEL_I_MSK 0xfffffffe
+#define RG_GEMINIA_RX_ADC_CLKSEL_SFT 0
+#define RG_GEMINIA_RX_ADC_CLKSEL_HI 0
+#define RG_GEMINIA_RX_ADC_CLKSEL_SZ 1
+#define RG_GEMINIA_RX_ADC_DNLEN_MSK 0x00000002
+#define RG_GEMINIA_RX_ADC_DNLEN_I_MSK 0xfffffffd
+#define RG_GEMINIA_RX_ADC_DNLEN_SFT 1
+#define RG_GEMINIA_RX_ADC_DNLEN_HI 1
+#define RG_GEMINIA_RX_ADC_DNLEN_SZ 1
+#define RG_GEMINIA_RX_ADC_METAEN_MSK 0x00000004
+#define RG_GEMINIA_RX_ADC_METAEN_I_MSK 0xfffffffb
+#define RG_GEMINIA_RX_ADC_METAEN_SFT 2
+#define RG_GEMINIA_RX_ADC_METAEN_HI 2
+#define RG_GEMINIA_RX_ADC_METAEN_SZ 1
+#define RG_GEMINIA_RX_ADC_TFLAG_MSK 0x00000008
+#define RG_GEMINIA_RX_ADC_TFLAG_I_MSK 0xfffffff7
+#define RG_GEMINIA_RX_ADC_TFLAG_SFT 3
+#define RG_GEMINIA_RX_ADC_TFLAG_HI 3
+#define RG_GEMINIA_RX_ADC_TFLAG_SZ 1
+#define RG_GEMINIA_RX_ADC_TSEL_MSK 0x000000f0
+#define RG_GEMINIA_RX_ADC_TSEL_I_MSK 0xffffff0f
+#define RG_GEMINIA_RX_ADC_TSEL_SFT 4
+#define RG_GEMINIA_RX_ADC_TSEL_HI 7
+#define RG_GEMINIA_RX_ADC_TSEL_SZ 4
+#define RG_GEMINIA_WF_RX_ADC_ICMP_MSK 0x00000300
+#define RG_GEMINIA_WF_RX_ADC_ICMP_I_MSK 0xfffffcff
+#define RG_GEMINIA_WF_RX_ADC_ICMP_SFT 8
+#define RG_GEMINIA_WF_RX_ADC_ICMP_HI 9
+#define RG_GEMINIA_WF_RX_ADC_ICMP_SZ 2
+#define RG_GEMINIA_WF_RX_ADC_VCMI_MSK 0x00000c00
+#define RG_GEMINIA_WF_RX_ADC_VCMI_I_MSK 0xfffff3ff
+#define RG_GEMINIA_WF_RX_ADC_VCMI_SFT 10
+#define RG_GEMINIA_WF_RX_ADC_VCMI_HI 11
+#define RG_GEMINIA_WF_RX_ADC_VCMI_SZ 2
+#define RG_GEMINIA_WF_RX_ADC_CLOAD_MSK 0x00003000
+#define RG_GEMINIA_WF_RX_ADC_CLOAD_I_MSK 0xffffcfff
+#define RG_GEMINIA_WF_RX_ADC_CLOAD_SFT 12
+#define RG_GEMINIA_WF_RX_ADC_CLOAD_HI 13
+#define RG_GEMINIA_WF_RX_ADC_CLOAD_SZ 2
+#define RG_GEMINIA_BT_RX_ADC_ICMP_MSK 0x00030000
+#define RG_GEMINIA_BT_RX_ADC_ICMP_I_MSK 0xfffcffff
+#define RG_GEMINIA_BT_RX_ADC_ICMP_SFT 16
+#define RG_GEMINIA_BT_RX_ADC_ICMP_HI 17
+#define RG_GEMINIA_BT_RX_ADC_ICMP_SZ 2
+#define RG_GEMINIA_BT_RX_ADC_VCMI_MSK 0x000c0000
+#define RG_GEMINIA_BT_RX_ADC_VCMI_I_MSK 0xfff3ffff
+#define RG_GEMINIA_BT_RX_ADC_VCMI_SFT 18
+#define RG_GEMINIA_BT_RX_ADC_VCMI_HI 19
+#define RG_GEMINIA_BT_RX_ADC_VCMI_SZ 2
+#define RG_GEMINIA_BT_RX_ADC_CLOAD_MSK 0x00300000
+#define RG_GEMINIA_BT_RX_ADC_CLOAD_I_MSK 0xffcfffff
+#define RG_GEMINIA_BT_RX_ADC_CLOAD_SFT 20
+#define RG_GEMINIA_BT_RX_ADC_CLOAD_HI 21
+#define RG_GEMINIA_BT_RX_ADC_CLOAD_SZ 2
+#define RG_GEMINIA_SARADC_VRSEL_MSK 0x03000000
+#define RG_GEMINIA_SARADC_VRSEL_I_MSK 0xfcffffff
+#define RG_GEMINIA_SARADC_VRSEL_SFT 24
+#define RG_GEMINIA_SARADC_VRSEL_HI 25
+#define RG_GEMINIA_SARADC_VRSEL_SZ 2
+#define RG_GEMINIA_EN_SAR_TEST_MSK 0x0c000000
+#define RG_GEMINIA_EN_SAR_TEST_I_MSK 0xf3ffffff
+#define RG_GEMINIA_EN_SAR_TEST_SFT 26
+#define RG_GEMINIA_EN_SAR_TEST_HI 27
+#define RG_GEMINIA_EN_SAR_TEST_SZ 2
+#define RG_GEMINIA_SARADC_THERMAL_MSK 0x10000000
+#define RG_GEMINIA_SARADC_THERMAL_I_MSK 0xefffffff
+#define RG_GEMINIA_SARADC_THERMAL_SFT 28
+#define RG_GEMINIA_SARADC_THERMAL_HI 28
+#define RG_GEMINIA_SARADC_THERMAL_SZ 1
+#define RG_GEMINIA_SARADC_TSSI_MSK 0x20000000
+#define RG_GEMINIA_SARADC_TSSI_I_MSK 0xdfffffff
+#define RG_GEMINIA_SARADC_TSSI_SFT 29
+#define RG_GEMINIA_SARADC_TSSI_HI 29
+#define RG_GEMINIA_SARADC_TSSI_SZ 1
+#define RG_GEMINIA_CLK_SAR_SEL_MSK 0xc0000000
+#define RG_GEMINIA_CLK_SAR_SEL_I_MSK 0x3fffffff
+#define RG_GEMINIA_CLK_SAR_SEL_SFT 30
+#define RG_GEMINIA_CLK_SAR_SEL_HI 31
+#define RG_GEMINIA_CLK_SAR_SEL_SZ 2
+#define RG_GEMINIA_WF_TX_DACI1ST_MSK 0x00000003
+#define RG_GEMINIA_WF_TX_DACI1ST_I_MSK 0xfffffffc
+#define RG_GEMINIA_WF_TX_DACI1ST_SFT 0
+#define RG_GEMINIA_WF_TX_DACI1ST_HI 1
+#define RG_GEMINIA_WF_TX_DACI1ST_SZ 2
+#define RG_GEMINIA_WF_TX_DACLPF_ICOARSE_MSK 0x0000000c
+#define RG_GEMINIA_WF_TX_DACLPF_ICOARSE_I_MSK 0xfffffff3
+#define RG_GEMINIA_WF_TX_DACLPF_ICOARSE_SFT 2
+#define RG_GEMINIA_WF_TX_DACLPF_ICOARSE_HI 3
+#define RG_GEMINIA_WF_TX_DACLPF_ICOARSE_SZ 2
+#define RG_GEMINIA_WF_TX_DACLPF_IFINE_MSK 0x00000030
+#define RG_GEMINIA_WF_TX_DACLPF_IFINE_I_MSK 0xffffffcf
+#define RG_GEMINIA_WF_TX_DACLPF_IFINE_SFT 4
+#define RG_GEMINIA_WF_TX_DACLPF_IFINE_HI 5
+#define RG_GEMINIA_WF_TX_DACLPF_IFINE_SZ 2
+#define RG_GEMINIA_WF_TX_DACLPF_VCM_MSK 0x000000c0
+#define RG_GEMINIA_WF_TX_DACLPF_VCM_I_MSK 0xffffff3f
+#define RG_GEMINIA_WF_TX_DACLPF_VCM_SFT 6
+#define RG_GEMINIA_WF_TX_DACLPF_VCM_HI 7
+#define RG_GEMINIA_WF_TX_DACLPF_VCM_SZ 2
+#define RG_GEMINIA_WF_TX_DAC_IBIAS_MSK 0x00000300
+#define RG_GEMINIA_WF_TX_DAC_IBIAS_I_MSK 0xfffffcff
+#define RG_GEMINIA_WF_TX_DAC_IBIAS_SFT 8
+#define RG_GEMINIA_WF_TX_DAC_IBIAS_HI 9
+#define RG_GEMINIA_WF_TX_DAC_IBIAS_SZ 2
+#define RG_GEMINIA_WF_TX_DAC_IATTN_MSK 0x00000400
+#define RG_GEMINIA_WF_TX_DAC_IATTN_I_MSK 0xfffffbff
+#define RG_GEMINIA_WF_TX_DAC_IATTN_SFT 10
+#define RG_GEMINIA_WF_TX_DAC_IATTN_HI 10
+#define RG_GEMINIA_WF_TX_DAC_IATTN_SZ 1
+#define RG_GEMINIA_WF_TXLPF_BOOSTI_MSK 0x00000800
+#define RG_GEMINIA_WF_TXLPF_BOOSTI_I_MSK 0xfffff7ff
+#define RG_GEMINIA_WF_TXLPF_BOOSTI_SFT 11
+#define RG_GEMINIA_WF_TXLPF_BOOSTI_HI 11
+#define RG_GEMINIA_WF_TXLPF_BOOSTI_SZ 1
+#define RG_GEMINIA_WF_TX_DAC_RCAL_MSK 0x00003000
+#define RG_GEMINIA_WF_TX_DAC_RCAL_I_MSK 0xffffcfff
+#define RG_GEMINIA_WF_TX_DAC_RCAL_SFT 12
+#define RG_GEMINIA_WF_TX_DAC_RCAL_HI 13
+#define RG_GEMINIA_WF_TX_DAC_RCAL_SZ 2
+#define RG_GEMINIA_WF_TX_DAC_CKEDGE_SEL_MSK 0x00004000
+#define RG_GEMINIA_WF_TX_DAC_CKEDGE_SEL_I_MSK 0xffffbfff
+#define RG_GEMINIA_WF_TX_DAC_CKEDGE_SEL_SFT 14
+#define RG_GEMINIA_WF_TX_DAC_CKEDGE_SEL_HI 14
+#define RG_GEMINIA_WF_TX_DAC_CKEDGE_SEL_SZ 1
+#define RG_GEMINIA_WF_TX_DAC_OS_MSK 0x00070000
+#define RG_GEMINIA_WF_TX_DAC_OS_I_MSK 0xfff8ffff
+#define RG_GEMINIA_WF_TX_DAC_OS_SFT 16
+#define RG_GEMINIA_WF_TX_DAC_OS_HI 18
+#define RG_GEMINIA_WF_TX_DAC_OS_SZ 3
+#define RG_GEMINIA_WF_TX_DAC_IOFFSET_MSK 0x00f00000
+#define RG_GEMINIA_WF_TX_DAC_IOFFSET_I_MSK 0xff0fffff
+#define RG_GEMINIA_WF_TX_DAC_IOFFSET_SFT 20
+#define RG_GEMINIA_WF_TX_DAC_IOFFSET_HI 23
+#define RG_GEMINIA_WF_TX_DAC_IOFFSET_SZ 4
+#define RG_GEMINIA_WF_TX_DAC_QOFFSET_MSK 0x0f000000
+#define RG_GEMINIA_WF_TX_DAC_QOFFSET_I_MSK 0xf0ffffff
+#define RG_GEMINIA_WF_TX_DAC_QOFFSET_SFT 24
+#define RG_GEMINIA_WF_TX_DAC_QOFFSET_HI 27
+#define RG_GEMINIA_WF_TX_DAC_QOFFSET_SZ 4
+#define RG_GEMINIA_TX_DAC_TSEL_MSK 0xf0000000
+#define RG_GEMINIA_TX_DAC_TSEL_I_MSK 0x0fffffff
+#define RG_GEMINIA_TX_DAC_TSEL_SFT 28
+#define RG_GEMINIA_TX_DAC_TSEL_HI 31
+#define RG_GEMINIA_TX_DAC_TSEL_SZ 4
+#define RG_GEMINIA_BT_TX_DACI1ST_MSK 0x00000003
+#define RG_GEMINIA_BT_TX_DACI1ST_I_MSK 0xfffffffc
+#define RG_GEMINIA_BT_TX_DACI1ST_SFT 0
+#define RG_GEMINIA_BT_TX_DACI1ST_HI 1
+#define RG_GEMINIA_BT_TX_DACI1ST_SZ 2
+#define RG_GEMINIA_BT_TX_DACLPF_ICOARSE_MSK 0x0000000c
+#define RG_GEMINIA_BT_TX_DACLPF_ICOARSE_I_MSK 0xfffffff3
+#define RG_GEMINIA_BT_TX_DACLPF_ICOARSE_SFT 2
+#define RG_GEMINIA_BT_TX_DACLPF_ICOARSE_HI 3
+#define RG_GEMINIA_BT_TX_DACLPF_ICOARSE_SZ 2
+#define RG_GEMINIA_BT_TX_DACLPF_IFINE_MSK 0x00000030
+#define RG_GEMINIA_BT_TX_DACLPF_IFINE_I_MSK 0xffffffcf
+#define RG_GEMINIA_BT_TX_DACLPF_IFINE_SFT 4
+#define RG_GEMINIA_BT_TX_DACLPF_IFINE_HI 5
+#define RG_GEMINIA_BT_TX_DACLPF_IFINE_SZ 2
+#define RG_GEMINIA_BT_TX_DACLPF_VCM_MSK 0x000000c0
+#define RG_GEMINIA_BT_TX_DACLPF_VCM_I_MSK 0xffffff3f
+#define RG_GEMINIA_BT_TX_DACLPF_VCM_SFT 6
+#define RG_GEMINIA_BT_TX_DACLPF_VCM_HI 7
+#define RG_GEMINIA_BT_TX_DACLPF_VCM_SZ 2
+#define RG_GEMINIA_BT_TX_DAC_IBIAS_MSK 0x00000300
+#define RG_GEMINIA_BT_TX_DAC_IBIAS_I_MSK 0xfffffcff
+#define RG_GEMINIA_BT_TX_DAC_IBIAS_SFT 8
+#define RG_GEMINIA_BT_TX_DAC_IBIAS_HI 9
+#define RG_GEMINIA_BT_TX_DAC_IBIAS_SZ 2
+#define RG_GEMINIA_BT_TX_DAC_IATTN_MSK 0x00000400
+#define RG_GEMINIA_BT_TX_DAC_IATTN_I_MSK 0xfffffbff
+#define RG_GEMINIA_BT_TX_DAC_IATTN_SFT 10
+#define RG_GEMINIA_BT_TX_DAC_IATTN_HI 10
+#define RG_GEMINIA_BT_TX_DAC_IATTN_SZ 1
+#define RG_GEMINIA_BT_TXLPF_BOOSTI_MSK 0x00000800
+#define RG_GEMINIA_BT_TXLPF_BOOSTI_I_MSK 0xfffff7ff
+#define RG_GEMINIA_BT_TXLPF_BOOSTI_SFT 11
+#define RG_GEMINIA_BT_TXLPF_BOOSTI_HI 11
+#define RG_GEMINIA_BT_TXLPF_BOOSTI_SZ 1
+#define RG_GEMINIA_BT_TX_DAC_RCAL_MSK 0x00003000
+#define RG_GEMINIA_BT_TX_DAC_RCAL_I_MSK 0xffffcfff
+#define RG_GEMINIA_BT_TX_DAC_RCAL_SFT 12
+#define RG_GEMINIA_BT_TX_DAC_RCAL_HI 13
+#define RG_GEMINIA_BT_TX_DAC_RCAL_SZ 2
+#define RG_GEMINIA_BT_TX_DAC_CKEDGE_SEL_MSK 0x00004000
+#define RG_GEMINIA_BT_TX_DAC_CKEDGE_SEL_I_MSK 0xffffbfff
+#define RG_GEMINIA_BT_TX_DAC_CKEDGE_SEL_SFT 14
+#define RG_GEMINIA_BT_TX_DAC_CKEDGE_SEL_HI 14
+#define RG_GEMINIA_BT_TX_DAC_CKEDGE_SEL_SZ 1
+#define RG_GEMINIA_BT_TX_DAC_OS_MSK 0x00070000
+#define RG_GEMINIA_BT_TX_DAC_OS_I_MSK 0xfff8ffff
+#define RG_GEMINIA_BT_TX_DAC_OS_SFT 16
+#define RG_GEMINIA_BT_TX_DAC_OS_HI 18
+#define RG_GEMINIA_BT_TX_DAC_OS_SZ 3
+#define RG_GEMINIA_BT_TX_DAC_IOFFSET_MSK 0x00f00000
+#define RG_GEMINIA_BT_TX_DAC_IOFFSET_I_MSK 0xff0fffff
+#define RG_GEMINIA_BT_TX_DAC_IOFFSET_SFT 20
+#define RG_GEMINIA_BT_TX_DAC_IOFFSET_HI 23
+#define RG_GEMINIA_BT_TX_DAC_IOFFSET_SZ 4
+#define RG_GEMINIA_BT_TX_DAC_QOFFSET_MSK 0x0f000000
+#define RG_GEMINIA_BT_TX_DAC_QOFFSET_I_MSK 0xf0ffffff
+#define RG_GEMINIA_BT_TX_DAC_QOFFSET_SFT 24
+#define RG_GEMINIA_BT_TX_DAC_QOFFSET_HI 27
+#define RG_GEMINIA_BT_TX_DAC_QOFFSET_SZ 4
+#define RG_GEMINIA_SX_EN_MAN_MSK 0x00000001
+#define RG_GEMINIA_SX_EN_MAN_I_MSK 0xfffffffe
+#define RG_GEMINIA_SX_EN_MAN_SFT 0
+#define RG_GEMINIA_SX_EN_MAN_HI 0
+#define RG_GEMINIA_SX_EN_MAN_SZ 1
+#define RG_GEMINIA_SX_EN_MSK 0x00000002
+#define RG_GEMINIA_SX_EN_I_MSK 0xfffffffd
+#define RG_GEMINIA_SX_EN_SFT 1
+#define RG_GEMINIA_SX_EN_HI 1
+#define RG_GEMINIA_SX_EN_SZ 1
+#define RG_GEMINIA_EN_SX_CP_MAN_MSK 0x00000004
+#define RG_GEMINIA_EN_SX_CP_MAN_I_MSK 0xfffffffb
+#define RG_GEMINIA_EN_SX_CP_MAN_SFT 2
+#define RG_GEMINIA_EN_SX_CP_MAN_HI 2
+#define RG_GEMINIA_EN_SX_CP_MAN_SZ 1
+#define RG_GEMINIA_EN_SX_CP_MSK 0x00000008
+#define RG_GEMINIA_EN_SX_CP_I_MSK 0xfffffff7
+#define RG_GEMINIA_EN_SX_CP_SFT 3
+#define RG_GEMINIA_EN_SX_CP_HI 3
+#define RG_GEMINIA_EN_SX_CP_SZ 1
+#define RG_GEMINIA_EN_SX_DIV_MAN_MSK 0x00000010
+#define RG_GEMINIA_EN_SX_DIV_MAN_I_MSK 0xffffffef
+#define RG_GEMINIA_EN_SX_DIV_MAN_SFT 4
+#define RG_GEMINIA_EN_SX_DIV_MAN_HI 4
+#define RG_GEMINIA_EN_SX_DIV_MAN_SZ 1
+#define RG_GEMINIA_EN_SX_DIV_MSK 0x00000020
+#define RG_GEMINIA_EN_SX_DIV_I_MSK 0xffffffdf
+#define RG_GEMINIA_EN_SX_DIV_SFT 5
+#define RG_GEMINIA_EN_SX_DIV_HI 5
+#define RG_GEMINIA_EN_SX_DIV_SZ 1
+#define RG_GEMINIA_EN_SX_VCO_MAN_MSK 0x00000040
+#define RG_GEMINIA_EN_SX_VCO_MAN_I_MSK 0xffffffbf
+#define RG_GEMINIA_EN_SX_VCO_MAN_SFT 6
+#define RG_GEMINIA_EN_SX_VCO_MAN_HI 6
+#define RG_GEMINIA_EN_SX_VCO_MAN_SZ 1
+#define RG_GEMINIA_EN_SX_VCO_MSK 0x00000080
+#define RG_GEMINIA_EN_SX_VCO_I_MSK 0xffffff7f
+#define RG_GEMINIA_EN_SX_VCO_SFT 7
+#define RG_GEMINIA_EN_SX_VCO_HI 7
+#define RG_GEMINIA_EN_SX_VCO_SZ 1
+#define RG_GEMINIA_SX_PFD_RST_MAN_MSK 0x00000100
+#define RG_GEMINIA_SX_PFD_RST_MAN_I_MSK 0xfffffeff
+#define RG_GEMINIA_SX_PFD_RST_MAN_SFT 8
+#define RG_GEMINIA_SX_PFD_RST_MAN_HI 8
+#define RG_GEMINIA_SX_PFD_RST_MAN_SZ 1
+#define RG_GEMINIA_SX_PFD_RST_MSK 0x00000200
+#define RG_GEMINIA_SX_PFD_RST_I_MSK 0xfffffdff
+#define RG_GEMINIA_SX_PFD_RST_SFT 9
+#define RG_GEMINIA_SX_PFD_RST_HI 9
+#define RG_GEMINIA_SX_PFD_RST_SZ 1
+#define RG_GEMINIA_SX_UOP_MAN_MSK 0x00000400
+#define RG_GEMINIA_SX_UOP_MAN_I_MSK 0xfffffbff
+#define RG_GEMINIA_SX_UOP_MAN_SFT 10
+#define RG_GEMINIA_SX_UOP_MAN_HI 10
+#define RG_GEMINIA_SX_UOP_MAN_SZ 1
+#define RG_GEMINIA_SX_UOP_EN_MSK 0x00000800
+#define RG_GEMINIA_SX_UOP_EN_I_MSK 0xfffff7ff
+#define RG_GEMINIA_SX_UOP_EN_SFT 11
+#define RG_GEMINIA_SX_UOP_EN_HI 11
+#define RG_GEMINIA_SX_UOP_EN_SZ 1
+#define RG_GEMINIA_EN_VCOBF_TXMB_MAN_MSK 0x00001000
+#define RG_GEMINIA_EN_VCOBF_TXMB_MAN_I_MSK 0xffffefff
+#define RG_GEMINIA_EN_VCOBF_TXMB_MAN_SFT 12
+#define RG_GEMINIA_EN_VCOBF_TXMB_MAN_HI 12
+#define RG_GEMINIA_EN_VCOBF_TXMB_MAN_SZ 1
+#define RG_GEMINIA_EN_VCOBF_TXMB_MSK 0x00002000
+#define RG_GEMINIA_EN_VCOBF_TXMB_I_MSK 0xffffdfff
+#define RG_GEMINIA_EN_VCOBF_TXMB_SFT 13
+#define RG_GEMINIA_EN_VCOBF_TXMB_HI 13
+#define RG_GEMINIA_EN_VCOBF_TXMB_SZ 1
+#define RG_GEMINIA_EN_VCOBF_TXOB_MAN_MSK 0x00004000
+#define RG_GEMINIA_EN_VCOBF_TXOB_MAN_I_MSK 0xffffbfff
+#define RG_GEMINIA_EN_VCOBF_TXOB_MAN_SFT 14
+#define RG_GEMINIA_EN_VCOBF_TXOB_MAN_HI 14
+#define RG_GEMINIA_EN_VCOBF_TXOB_MAN_SZ 1
+#define RG_GEMINIA_EN_VCOBF_TXOB_MSK 0x00008000
+#define RG_GEMINIA_EN_VCOBF_TXOB_I_MSK 0xffff7fff
+#define RG_GEMINIA_EN_VCOBF_TXOB_SFT 15
+#define RG_GEMINIA_EN_VCOBF_TXOB_HI 15
+#define RG_GEMINIA_EN_VCOBF_TXOB_SZ 1
+#define RG_GEMINIA_EN_VCOBF_RXMB_MAN_MSK 0x00010000
+#define RG_GEMINIA_EN_VCOBF_RXMB_MAN_I_MSK 0xfffeffff
+#define RG_GEMINIA_EN_VCOBF_RXMB_MAN_SFT 16
+#define RG_GEMINIA_EN_VCOBF_RXMB_MAN_HI 16
+#define RG_GEMINIA_EN_VCOBF_RXMB_MAN_SZ 1
+#define RG_GEMINIA_EN_VCOBF_RXMB_MSK 0x00020000
+#define RG_GEMINIA_EN_VCOBF_RXMB_I_MSK 0xfffdffff
+#define RG_GEMINIA_EN_VCOBF_RXMB_SFT 17
+#define RG_GEMINIA_EN_VCOBF_RXMB_HI 17
+#define RG_GEMINIA_EN_VCOBF_RXMB_SZ 1
+#define RG_GEMINIA_EN_VCOBF_RXOB_MAN_MSK 0x00040000
+#define RG_GEMINIA_EN_VCOBF_RXOB_MAN_I_MSK 0xfffbffff
+#define RG_GEMINIA_EN_VCOBF_RXOB_MAN_SFT 18
+#define RG_GEMINIA_EN_VCOBF_RXOB_MAN_HI 18
+#define RG_GEMINIA_EN_VCOBF_RXOB_MAN_SZ 1
+#define RG_GEMINIA_EN_VCOBF_RXOB_MSK 0x00080000
+#define RG_GEMINIA_EN_VCOBF_RXOB_I_MSK 0xfff7ffff
+#define RG_GEMINIA_EN_VCOBF_RXOB_SFT 19
+#define RG_GEMINIA_EN_VCOBF_RXOB_HI 19
+#define RG_GEMINIA_EN_VCOBF_RXOB_SZ 1
+#define RG_GEMINIA_EN_VCOBF_DIVCK_MAN_MSK 0x00100000
+#define RG_GEMINIA_EN_VCOBF_DIVCK_MAN_I_MSK 0xffefffff
+#define RG_GEMINIA_EN_VCOBF_DIVCK_MAN_SFT 20
+#define RG_GEMINIA_EN_VCOBF_DIVCK_MAN_HI 20
+#define RG_GEMINIA_EN_VCOBF_DIVCK_MAN_SZ 1
+#define RG_GEMINIA_EN_VCOBF_DIVCK_MSK 0x00200000
+#define RG_GEMINIA_EN_VCOBF_DIVCK_I_MSK 0xffdfffff
+#define RG_GEMINIA_EN_VCOBF_DIVCK_SFT 21
+#define RG_GEMINIA_EN_VCOBF_DIVCK_HI 21
+#define RG_GEMINIA_EN_VCOBF_DIVCK_SZ 1
+#define RG_GEMINIA_SX_SBCAL_DIS_MSK 0x00800000
+#define RG_GEMINIA_SX_SBCAL_DIS_I_MSK 0xff7fffff
+#define RG_GEMINIA_SX_SBCAL_DIS_SFT 23
+#define RG_GEMINIA_SX_SBCAL_DIS_HI 23
+#define RG_GEMINIA_SX_SBCAL_DIS_SZ 1
+#define RG_GEMINIA_SX_SBCAL_AW_MSK 0x01000000
+#define RG_GEMINIA_SX_SBCAL_AW_I_MSK 0xfeffffff
+#define RG_GEMINIA_SX_SBCAL_AW_SFT 24
+#define RG_GEMINIA_SX_SBCAL_AW_HI 24
+#define RG_GEMINIA_SX_SBCAL_AW_SZ 1
+#define RG_GEMINIA_SX_AAC_DIS_MSK 0x04000000
+#define RG_GEMINIA_SX_AAC_DIS_I_MSK 0xfbffffff
+#define RG_GEMINIA_SX_AAC_DIS_SFT 26
+#define RG_GEMINIA_SX_AAC_DIS_HI 26
+#define RG_GEMINIA_SX_AAC_DIS_SZ 1
+#define RG_GEMINIA_SX_TTL_DIS_MSK 0x08000000
+#define RG_GEMINIA_SX_TTL_DIS_I_MSK 0xf7ffffff
+#define RG_GEMINIA_SX_TTL_DIS_SFT 27
+#define RG_GEMINIA_SX_TTL_DIS_HI 27
+#define RG_GEMINIA_SX_TTL_DIS_SZ 1
+#define RG_GEMINIA_SX_CAL_INIT_MSK 0xe0000000
+#define RG_GEMINIA_SX_CAL_INIT_I_MSK 0x1fffffff
+#define RG_GEMINIA_SX_CAL_INIT_SFT 29
+#define RG_GEMINIA_SX_CAL_INIT_HI 31
+#define RG_GEMINIA_SX_CAL_INIT_SZ 3
+#define RG_GEMINIA_EN_SX_LDO_MAN_MSK 0x00000001
+#define RG_GEMINIA_EN_SX_LDO_MAN_I_MSK 0xfffffffe
+#define RG_GEMINIA_EN_SX_LDO_MAN_SFT 0
+#define RG_GEMINIA_EN_SX_LDO_MAN_HI 0
+#define RG_GEMINIA_EN_SX_LDO_MAN_SZ 1
+#define RG_GEMINIA_EN_LDO_CP_MSK 0x00000002
+#define RG_GEMINIA_EN_LDO_CP_I_MSK 0xfffffffd
+#define RG_GEMINIA_EN_LDO_CP_SFT 1
+#define RG_GEMINIA_EN_LDO_CP_HI 1
+#define RG_GEMINIA_EN_LDO_CP_SZ 1
+#define RG_GEMINIA_EN_LDO_DIV_MSK 0x00000004
+#define RG_GEMINIA_EN_LDO_DIV_I_MSK 0xfffffffb
+#define RG_GEMINIA_EN_LDO_DIV_SFT 2
+#define RG_GEMINIA_EN_LDO_DIV_HI 2
+#define RG_GEMINIA_EN_LDO_DIV_SZ 1
+#define RG_GEMINIA_EN_LDO_LO_MSK 0x00000008
+#define RG_GEMINIA_EN_LDO_LO_I_MSK 0xfffffff7
+#define RG_GEMINIA_EN_LDO_LO_SFT 3
+#define RG_GEMINIA_EN_LDO_LO_HI 3
+#define RG_GEMINIA_EN_LDO_LO_SZ 1
+#define RG_GEMINIA_EN_LDO_VCO_MSK 0x00000010
+#define RG_GEMINIA_EN_LDO_VCO_I_MSK 0xffffffef
+#define RG_GEMINIA_EN_LDO_VCO_SFT 4
+#define RG_GEMINIA_EN_LDO_VCO_HI 4
+#define RG_GEMINIA_EN_LDO_VCO_SZ 1
+#define RG_GEMINIA_EN_LDO_CP_BYP_MSK 0x00000040
+#define RG_GEMINIA_EN_LDO_CP_BYP_I_MSK 0xffffffbf
+#define RG_GEMINIA_EN_LDO_CP_BYP_SFT 6
+#define RG_GEMINIA_EN_LDO_CP_BYP_HI 6
+#define RG_GEMINIA_EN_LDO_CP_BYP_SZ 1
+#define RG_GEMINIA_EN_LDO_DIV_BYP_MSK 0x00000080
+#define RG_GEMINIA_EN_LDO_DIV_BYP_I_MSK 0xffffff7f
+#define RG_GEMINIA_EN_LDO_DIV_BYP_SFT 7
+#define RG_GEMINIA_EN_LDO_DIV_BYP_HI 7
+#define RG_GEMINIA_EN_LDO_DIV_BYP_SZ 1
+#define RG_GEMINIA_EN_LDO_LO_BYP_MSK 0x00000100
+#define RG_GEMINIA_EN_LDO_LO_BYP_I_MSK 0xfffffeff
+#define RG_GEMINIA_EN_LDO_LO_BYP_SFT 8
+#define RG_GEMINIA_EN_LDO_LO_BYP_HI 8
+#define RG_GEMINIA_EN_LDO_LO_BYP_SZ 1
+#define RG_GEMINIA_EN_LDO_VCO_PSW_MSK 0x00000200
+#define RG_GEMINIA_EN_LDO_VCO_PSW_I_MSK 0xfffffdff
+#define RG_GEMINIA_EN_LDO_VCO_PSW_SFT 9
+#define RG_GEMINIA_EN_LDO_VCO_PSW_HI 9
+#define RG_GEMINIA_EN_LDO_VCO_PSW_SZ 1
+#define RG_GEMINIA_EN_LDO_VCO_VDD33_MSK 0x00000400
+#define RG_GEMINIA_EN_LDO_VCO_VDD33_I_MSK 0xfffffbff
+#define RG_GEMINIA_EN_LDO_VCO_VDD33_SFT 10
+#define RG_GEMINIA_EN_LDO_VCO_VDD33_HI 10
+#define RG_GEMINIA_EN_LDO_VCO_VDD33_SZ 1
+#define RG_GEMINIA_EN_LDO_CP_IQUP_MSK 0x00000800
+#define RG_GEMINIA_EN_LDO_CP_IQUP_I_MSK 0xfffff7ff
+#define RG_GEMINIA_EN_LDO_CP_IQUP_SFT 11
+#define RG_GEMINIA_EN_LDO_CP_IQUP_HI 11
+#define RG_GEMINIA_EN_LDO_CP_IQUP_SZ 1
+#define RG_GEMINIA_EN_LDO_DIV_IQUP_MSK 0x00001000
+#define RG_GEMINIA_EN_LDO_DIV_IQUP_I_MSK 0xffffefff
+#define RG_GEMINIA_EN_LDO_DIV_IQUP_SFT 12
+#define RG_GEMINIA_EN_LDO_DIV_IQUP_HI 12
+#define RG_GEMINIA_EN_LDO_DIV_IQUP_SZ 1
+#define RG_GEMINIA_EN_LDO_LO_IQUP_MSK 0x00002000
+#define RG_GEMINIA_EN_LDO_LO_IQUP_I_MSK 0xffffdfff
+#define RG_GEMINIA_EN_LDO_LO_IQUP_SFT 13
+#define RG_GEMINIA_EN_LDO_LO_IQUP_HI 13
+#define RG_GEMINIA_EN_LDO_LO_IQUP_SZ 1
+#define RG_GEMINIA_EN_LDO_VCO_IQUP_MSK 0x00004000
+#define RG_GEMINIA_EN_LDO_VCO_IQUP_I_MSK 0xffffbfff
+#define RG_GEMINIA_EN_LDO_VCO_IQUP_SFT 14
+#define RG_GEMINIA_EN_LDO_VCO_IQUP_HI 14
+#define RG_GEMINIA_EN_LDO_VCO_IQUP_SZ 1
+#define RG_GEMINIA_SX_LDO_FCOFFT_MSK 0x00380000
+#define RG_GEMINIA_SX_LDO_FCOFFT_I_MSK 0xffc7ffff
+#define RG_GEMINIA_SX_LDO_FCOFFT_SFT 19
+#define RG_GEMINIA_SX_LDO_FCOFFT_HI 21
+#define RG_GEMINIA_SX_LDO_FCOFFT_SZ 3
+#define RG_GEMINIA_LDO_CP_FC_MAN_MSK 0x00400000
+#define RG_GEMINIA_LDO_CP_FC_MAN_I_MSK 0xffbfffff
+#define RG_GEMINIA_LDO_CP_FC_MAN_SFT 22
+#define RG_GEMINIA_LDO_CP_FC_MAN_HI 22
+#define RG_GEMINIA_LDO_CP_FC_MAN_SZ 1
+#define RG_GEMINIA_LDO_CP_FC_MSK 0x00800000
+#define RG_GEMINIA_LDO_CP_FC_I_MSK 0xff7fffff
+#define RG_GEMINIA_LDO_CP_FC_SFT 23
+#define RG_GEMINIA_LDO_CP_FC_HI 23
+#define RG_GEMINIA_LDO_CP_FC_SZ 1
+#define RG_GEMINIA_LDO_DIV_FC_MAN_MSK 0x01000000
+#define RG_GEMINIA_LDO_DIV_FC_MAN_I_MSK 0xfeffffff
+#define RG_GEMINIA_LDO_DIV_FC_MAN_SFT 24
+#define RG_GEMINIA_LDO_DIV_FC_MAN_HI 24
+#define RG_GEMINIA_LDO_DIV_FC_MAN_SZ 1
+#define RG_GEMINIA_LDO_DIV_FC_MSK 0x02000000
+#define RG_GEMINIA_LDO_DIV_FC_I_MSK 0xfdffffff
+#define RG_GEMINIA_LDO_DIV_FC_SFT 25
+#define RG_GEMINIA_LDO_DIV_FC_HI 25
+#define RG_GEMINIA_LDO_DIV_FC_SZ 1
+#define RG_GEMINIA_LDO_LO_FC_MAN_MSK 0x04000000
+#define RG_GEMINIA_LDO_LO_FC_MAN_I_MSK 0xfbffffff
+#define RG_GEMINIA_LDO_LO_FC_MAN_SFT 26
+#define RG_GEMINIA_LDO_LO_FC_MAN_HI 26
+#define RG_GEMINIA_LDO_LO_FC_MAN_SZ 1
+#define RG_GEMINIA_LDO_LO_FC_MSK 0x08000000
+#define RG_GEMINIA_LDO_LO_FC_I_MSK 0xf7ffffff
+#define RG_GEMINIA_LDO_LO_FC_SFT 27
+#define RG_GEMINIA_LDO_LO_FC_HI 27
+#define RG_GEMINIA_LDO_LO_FC_SZ 1
+#define RG_GEMINIA_LDO_VCO_FC_MAN_MSK 0x10000000
+#define RG_GEMINIA_LDO_VCO_FC_MAN_I_MSK 0xefffffff
+#define RG_GEMINIA_LDO_VCO_FC_MAN_SFT 28
+#define RG_GEMINIA_LDO_VCO_FC_MAN_HI 28
+#define RG_GEMINIA_LDO_VCO_FC_MAN_SZ 1
+#define RG_GEMINIA_LDO_VCO_FC_MSK 0x20000000
+#define RG_GEMINIA_LDO_VCO_FC_I_MSK 0xdfffffff
+#define RG_GEMINIA_LDO_VCO_FC_SFT 29
+#define RG_GEMINIA_LDO_VCO_FC_HI 29
+#define RG_GEMINIA_LDO_VCO_FC_SZ 1
+#define RG_GEMINIA_LDO_VCO_RCF_MSK 0xc0000000
+#define RG_GEMINIA_LDO_VCO_RCF_I_MSK 0x3fffffff
+#define RG_GEMINIA_LDO_VCO_RCF_SFT 30
+#define RG_GEMINIA_LDO_VCO_RCF_HI 31
+#define RG_GEMINIA_LDO_VCO_RCF_SZ 2
+#define RG_GEMINIA_SX_RFCTRL_F_MSK 0x00ffffff
+#define RG_GEMINIA_SX_RFCTRL_F_I_MSK 0xff000000
+#define RG_GEMINIA_SX_RFCTRL_F_SFT 0
+#define RG_GEMINIA_SX_RFCTRL_F_HI 23
+#define RG_GEMINIA_SX_RFCTRL_F_SZ 24
+#define RG_GEMINIA_SX_RFCTRL_CH_7_0_MSK 0xff000000
+#define RG_GEMINIA_SX_RFCTRL_CH_7_0_I_MSK 0x00ffffff
+#define RG_GEMINIA_SX_RFCTRL_CH_7_0_SFT 24
+#define RG_GEMINIA_SX_RFCTRL_CH_7_0_HI 31
+#define RG_GEMINIA_SX_RFCTRL_CH_7_0_SZ 8
+#define RG_GEMINIA_SX_RFCTRL_CH_10_8_MSK 0x00000007
+#define RG_GEMINIA_SX_RFCTRL_CH_10_8_I_MSK 0xfffffff8
+#define RG_GEMINIA_SX_RFCTRL_CH_10_8_SFT 0
+#define RG_GEMINIA_SX_RFCTRL_CH_10_8_HI 2
+#define RG_GEMINIA_SX_RFCTRL_CH_10_8_SZ 3
+#define RG_GEMINIA_SX_RFCH_MAP_EN_MSK 0x00000010
+#define RG_GEMINIA_SX_RFCH_MAP_EN_I_MSK 0xffffffef
+#define RG_GEMINIA_SX_RFCH_MAP_EN_SFT 4
+#define RG_GEMINIA_SX_RFCH_MAP_EN_HI 4
+#define RG_GEMINIA_SX_RFCH_MAP_EN_SZ 1
+#define RG_GEMINIA_SX_XTAL_FREQ_MSK 0x00000060
+#define RG_GEMINIA_SX_XTAL_FREQ_I_MSK 0xffffff9f
+#define RG_GEMINIA_SX_XTAL_FREQ_SFT 5
+#define RG_GEMINIA_SX_XTAL_FREQ_HI 6
+#define RG_GEMINIA_SX_XTAL_FREQ_SZ 2
+#define RG_GEMINIA_SX_FREF_DOUB_MSK 0x00000080
+#define RG_GEMINIA_SX_FREF_DOUB_I_MSK 0xffffff7f
+#define RG_GEMINIA_SX_FREF_DOUB_SFT 7
+#define RG_GEMINIA_SX_FREF_DOUB_HI 7
+#define RG_GEMINIA_SX_FREF_DOUB_SZ 1
+#define RG_GEMINIA_SX_BTRX_SIDE_MSK 0x00000100
+#define RG_GEMINIA_SX_BTRX_SIDE_I_MSK 0xfffffeff
+#define RG_GEMINIA_SX_BTRX_SIDE_SFT 8
+#define RG_GEMINIA_SX_BTRX_SIDE_HI 8
+#define RG_GEMINIA_SX_BTRX_SIDE_SZ 1
+#define RG_GEMINIA_SX_LO_TIMES_MSK 0x00000200
+#define RG_GEMINIA_SX_LO_TIMES_I_MSK 0xfffffdff
+#define RG_GEMINIA_SX_LO_TIMES_SFT 9
+#define RG_GEMINIA_SX_LO_TIMES_HI 9
+#define RG_GEMINIA_SX_LO_TIMES_SZ 1
+#define RG_GEMINIA_SX_CHANNEL_MSK 0x0007f800
+#define RG_GEMINIA_SX_CHANNEL_I_MSK 0xfff807ff
+#define RG_GEMINIA_SX_CHANNEL_SFT 11
+#define RG_GEMINIA_SX_CHANNEL_HI 18
+#define RG_GEMINIA_SX_CHANNEL_SZ 8
+#define RG_GEMINIA_SX_CP_ISEL_BT_MSK 0x0000000f
+#define RG_GEMINIA_SX_CP_ISEL_BT_I_MSK 0xfffffff0
+#define RG_GEMINIA_SX_CP_ISEL_BT_SFT 0
+#define RG_GEMINIA_SX_CP_ISEL_BT_HI 3
+#define RG_GEMINIA_SX_CP_ISEL_BT_SZ 4
+#define RG_GEMINIA_SX_CP_ISEL50U_BT_MSK 0x00000010
+#define RG_GEMINIA_SX_CP_ISEL50U_BT_I_MSK 0xffffffef
+#define RG_GEMINIA_SX_CP_ISEL50U_BT_SFT 4
+#define RG_GEMINIA_SX_CP_ISEL50U_BT_HI 4
+#define RG_GEMINIA_SX_CP_ISEL50U_BT_SZ 1
+#define RG_GEMINIA_SX_CP_KP_DOUB_BT_MSK 0x00000020
+#define RG_GEMINIA_SX_CP_KP_DOUB_BT_I_MSK 0xffffffdf
+#define RG_GEMINIA_SX_CP_KP_DOUB_BT_SFT 5
+#define RG_GEMINIA_SX_CP_KP_DOUB_BT_HI 5
+#define RG_GEMINIA_SX_CP_KP_DOUB_BT_SZ 1
+#define RG_GEMINIA_SX_CP_ISEL_WF_MSK 0x00000780
+#define RG_GEMINIA_SX_CP_ISEL_WF_I_MSK 0xfffff87f
+#define RG_GEMINIA_SX_CP_ISEL_WF_SFT 7
+#define RG_GEMINIA_SX_CP_ISEL_WF_HI 10
+#define RG_GEMINIA_SX_CP_ISEL_WF_SZ 4
+#define RG_GEMINIA_SX_CP_ISEL50U_WF_MSK 0x00000800
+#define RG_GEMINIA_SX_CP_ISEL50U_WF_I_MSK 0xfffff7ff
+#define RG_GEMINIA_SX_CP_ISEL50U_WF_SFT 11
+#define RG_GEMINIA_SX_CP_ISEL50U_WF_HI 11
+#define RG_GEMINIA_SX_CP_ISEL50U_WF_SZ 1
+#define RG_GEMINIA_SX_CP_KP_DOUB_WF_MSK 0x00001000
+#define RG_GEMINIA_SX_CP_KP_DOUB_WF_I_MSK 0xffffefff
+#define RG_GEMINIA_SX_CP_KP_DOUB_WF_SFT 12
+#define RG_GEMINIA_SX_CP_KP_DOUB_WF_HI 12
+#define RG_GEMINIA_SX_CP_KP_DOUB_WF_SZ 1
+#define RG_GEMINIA_SX_CP_IOST_POL_MSK 0x00008000
+#define RG_GEMINIA_SX_CP_IOST_POL_I_MSK 0xffff7fff
+#define RG_GEMINIA_SX_CP_IOST_POL_SFT 15
+#define RG_GEMINIA_SX_CP_IOST_POL_HI 15
+#define RG_GEMINIA_SX_CP_IOST_POL_SZ 1
+#define RG_GEMINIA_SX_CP_IOST_MSK 0x00070000
+#define RG_GEMINIA_SX_CP_IOST_I_MSK 0xfff8ffff
+#define RG_GEMINIA_SX_CP_IOST_SFT 16
+#define RG_GEMINIA_SX_CP_IOST_HI 18
+#define RG_GEMINIA_SX_CP_IOST_SZ 3
+#define RG_GEMINIA_SX_PFD_SEL_MSK 0x00400000
+#define RG_GEMINIA_SX_PFD_SEL_I_MSK 0xffbfffff
+#define RG_GEMINIA_SX_PFD_SEL_SFT 22
+#define RG_GEMINIA_SX_PFD_SEL_HI 22
+#define RG_GEMINIA_SX_PFD_SEL_SZ 1
+#define RG_GEMINIA_SX_PFD_SET_MSK 0x00800000
+#define RG_GEMINIA_SX_PFD_SET_I_MSK 0xff7fffff
+#define RG_GEMINIA_SX_PFD_SET_SFT 23
+#define RG_GEMINIA_SX_PFD_SET_HI 23
+#define RG_GEMINIA_SX_PFD_SET_SZ 1
+#define RG_GEMINIA_SX_PFD_SET1_MSK 0x01000000
+#define RG_GEMINIA_SX_PFD_SET1_I_MSK 0xfeffffff
+#define RG_GEMINIA_SX_PFD_SET1_SFT 24
+#define RG_GEMINIA_SX_PFD_SET1_HI 24
+#define RG_GEMINIA_SX_PFD_SET1_SZ 1
+#define RG_GEMINIA_SX_PFD_SET2_MSK 0x02000000
+#define RG_GEMINIA_SX_PFD_SET2_I_MSK 0xfdffffff
+#define RG_GEMINIA_SX_PFD_SET2_SFT 25
+#define RG_GEMINIA_SX_PFD_SET2_HI 25
+#define RG_GEMINIA_SX_PFD_SET2_SZ 1
+#define RG_GEMINIA_SX_PFD_TRUP_MSK 0x10000000
+#define RG_GEMINIA_SX_PFD_TRUP_I_MSK 0xefffffff
+#define RG_GEMINIA_SX_PFD_TRUP_SFT 28
+#define RG_GEMINIA_SX_PFD_TRUP_HI 28
+#define RG_GEMINIA_SX_PFD_TRUP_SZ 1
+#define RG_GEMINIA_SX_PFD_TRDN_MSK 0x20000000
+#define RG_GEMINIA_SX_PFD_TRDN_I_MSK 0xdfffffff
+#define RG_GEMINIA_SX_PFD_TRDN_SFT 29
+#define RG_GEMINIA_SX_PFD_TRDN_HI 29
+#define RG_GEMINIA_SX_PFD_TRDN_SZ 1
+#define RG_GEMINIA_SX_PFD_TLSEL_MSK 0x40000000
+#define RG_GEMINIA_SX_PFD_TLSEL_I_MSK 0xbfffffff
+#define RG_GEMINIA_SX_PFD_TLSEL_SFT 30
+#define RG_GEMINIA_SX_PFD_TLSEL_HI 30
+#define RG_GEMINIA_SX_PFD_TLSEL_SZ 1
+#define RG_GEMINIA_SX_LPF_C1_BT_MSK 0x0000000f
+#define RG_GEMINIA_SX_LPF_C1_BT_I_MSK 0xfffffff0
+#define RG_GEMINIA_SX_LPF_C1_BT_SFT 0
+#define RG_GEMINIA_SX_LPF_C1_BT_HI 3
+#define RG_GEMINIA_SX_LPF_C1_BT_SZ 4
+#define RG_GEMINIA_SX_LPF_C2_BT_MSK 0x000000f0
+#define RG_GEMINIA_SX_LPF_C2_BT_I_MSK 0xffffff0f
+#define RG_GEMINIA_SX_LPF_C2_BT_SFT 4
+#define RG_GEMINIA_SX_LPF_C2_BT_HI 7
+#define RG_GEMINIA_SX_LPF_C2_BT_SZ 4
+#define RG_GEMINIA_SX_LPF_C3_BT_MSK 0x00000100
+#define RG_GEMINIA_SX_LPF_C3_BT_I_MSK 0xfffffeff
+#define RG_GEMINIA_SX_LPF_C3_BT_SFT 8
+#define RG_GEMINIA_SX_LPF_C3_BT_HI 8
+#define RG_GEMINIA_SX_LPF_C3_BT_SZ 1
+#define RG_GEMINIA_SX_LPF_R2_BT_MSK 0x00001e00
+#define RG_GEMINIA_SX_LPF_R2_BT_I_MSK 0xffffe1ff
+#define RG_GEMINIA_SX_LPF_R2_BT_SFT 9
+#define RG_GEMINIA_SX_LPF_R2_BT_HI 12
+#define RG_GEMINIA_SX_LPF_R2_BT_SZ 4
+#define RG_GEMINIA_SX_LPF_R3_BT_MSK 0x0000e000
+#define RG_GEMINIA_SX_LPF_R3_BT_I_MSK 0xffff1fff
+#define RG_GEMINIA_SX_LPF_R3_BT_SFT 13
+#define RG_GEMINIA_SX_LPF_R3_BT_HI 15
+#define RG_GEMINIA_SX_LPF_R3_BT_SZ 3
+#define RG_GEMINIA_SX_LPF_C1_WF_MSK 0x000f0000
+#define RG_GEMINIA_SX_LPF_C1_WF_I_MSK 0xfff0ffff
+#define RG_GEMINIA_SX_LPF_C1_WF_SFT 16
+#define RG_GEMINIA_SX_LPF_C1_WF_HI 19
+#define RG_GEMINIA_SX_LPF_C1_WF_SZ 4
+#define RG_GEMINIA_SX_LPF_C2_WF_MSK 0x00f00000
+#define RG_GEMINIA_SX_LPF_C2_WF_I_MSK 0xff0fffff
+#define RG_GEMINIA_SX_LPF_C2_WF_SFT 20
+#define RG_GEMINIA_SX_LPF_C2_WF_HI 23
+#define RG_GEMINIA_SX_LPF_C2_WF_SZ 4
+#define RG_GEMINIA_SX_LPF_C3_WF_MSK 0x01000000
+#define RG_GEMINIA_SX_LPF_C3_WF_I_MSK 0xfeffffff
+#define RG_GEMINIA_SX_LPF_C3_WF_SFT 24
+#define RG_GEMINIA_SX_LPF_C3_WF_HI 24
+#define RG_GEMINIA_SX_LPF_C3_WF_SZ 1
+#define RG_GEMINIA_SX_LPF_R2_WF_MSK 0x1e000000
+#define RG_GEMINIA_SX_LPF_R2_WF_I_MSK 0xe1ffffff
+#define RG_GEMINIA_SX_LPF_R2_WF_SFT 25
+#define RG_GEMINIA_SX_LPF_R2_WF_HI 28
+#define RG_GEMINIA_SX_LPF_R2_WF_SZ 4
+#define RG_GEMINIA_SX_LPF_R3_WF_MSK 0xe0000000
+#define RG_GEMINIA_SX_LPF_R3_WF_I_MSK 0x1fffffff
+#define RG_GEMINIA_SX_LPF_R3_WF_SFT 29
+#define RG_GEMINIA_SX_LPF_R3_WF_HI 31
+#define RG_GEMINIA_SX_LPF_R3_WF_SZ 3
+#define RG_GEMINIA_SX_VCO_ISEL_MAN_MSK 0x00000001
+#define RG_GEMINIA_SX_VCO_ISEL_MAN_I_MSK 0xfffffffe
+#define RG_GEMINIA_SX_VCO_ISEL_MAN_SFT 0
+#define RG_GEMINIA_SX_VCO_ISEL_MAN_HI 0
+#define RG_GEMINIA_SX_VCO_ISEL_MAN_SZ 1
+#define RG_GEMINIA_SX_VCO_ISEL_BT_MSK 0x0000001e
+#define RG_GEMINIA_SX_VCO_ISEL_BT_I_MSK 0xffffffe1
+#define RG_GEMINIA_SX_VCO_ISEL_BT_SFT 1
+#define RG_GEMINIA_SX_VCO_ISEL_BT_HI 4
+#define RG_GEMINIA_SX_VCO_ISEL_BT_SZ 4
+#define RG_GEMINIA_SX_VCO_LPM_BT_MSK 0x00000020
+#define RG_GEMINIA_SX_VCO_LPM_BT_I_MSK 0xffffffdf
+#define RG_GEMINIA_SX_VCO_LPM_BT_SFT 5
+#define RG_GEMINIA_SX_VCO_LPM_BT_HI 5
+#define RG_GEMINIA_SX_VCO_LPM_BT_SZ 1
+#define RG_GEMINIA_SX_VCO_VCCBSEL_BT_MSK 0x000001c0
+#define RG_GEMINIA_SX_VCO_VCCBSEL_BT_I_MSK 0xfffffe3f
+#define RG_GEMINIA_SX_VCO_VCCBSEL_BT_SFT 6
+#define RG_GEMINIA_SX_VCO_VCCBSEL_BT_HI 8
+#define RG_GEMINIA_SX_VCO_VCCBSEL_BT_SZ 3
+#define RG_GEMINIA_SX_VCO_KVDOUB_BT_MSK 0x00000200
+#define RG_GEMINIA_SX_VCO_KVDOUB_BT_I_MSK 0xfffffdff
+#define RG_GEMINIA_SX_VCO_KVDOUB_BT_SFT 9
+#define RG_GEMINIA_SX_VCO_KVDOUB_BT_HI 9
+#define RG_GEMINIA_SX_VCO_KVDOUB_BT_SZ 1
+#define RG_GEMINIA_SX_VCO_ISEL_WF_MSK 0x00003c00
+#define RG_GEMINIA_SX_VCO_ISEL_WF_I_MSK 0xffffc3ff
+#define RG_GEMINIA_SX_VCO_ISEL_WF_SFT 10
+#define RG_GEMINIA_SX_VCO_ISEL_WF_HI 13
+#define RG_GEMINIA_SX_VCO_ISEL_WF_SZ 4
+#define RG_GEMINIA_SX_VCO_LPM_WF_MSK 0x00004000
+#define RG_GEMINIA_SX_VCO_LPM_WF_I_MSK 0xffffbfff
+#define RG_GEMINIA_SX_VCO_LPM_WF_SFT 14
+#define RG_GEMINIA_SX_VCO_LPM_WF_HI 14
+#define RG_GEMINIA_SX_VCO_LPM_WF_SZ 1
+#define RG_GEMINIA_SX_VCO_VCCBSEL_WF_MSK 0x00038000
+#define RG_GEMINIA_SX_VCO_VCCBSEL_WF_I_MSK 0xfffc7fff
+#define RG_GEMINIA_SX_VCO_VCCBSEL_WF_SFT 15
+#define RG_GEMINIA_SX_VCO_VCCBSEL_WF_HI 17
+#define RG_GEMINIA_SX_VCO_VCCBSEL_WF_SZ 3
+#define RG_GEMINIA_SX_VCO_KVDOUB_WF_MSK 0x00040000
+#define RG_GEMINIA_SX_VCO_KVDOUB_WF_I_MSK 0xfffbffff
+#define RG_GEMINIA_SX_VCO_KVDOUB_WF_SFT 18
+#define RG_GEMINIA_SX_VCO_KVDOUB_WF_HI 18
+#define RG_GEMINIA_SX_VCO_KVDOUB_WF_SZ 1
+#define RG_GEMINIA_SX_VCO_VARBSEL_MSK 0x00600000
+#define RG_GEMINIA_SX_VCO_VARBSEL_I_MSK 0xff9fffff
+#define RG_GEMINIA_SX_VCO_VARBSEL_SFT 21
+#define RG_GEMINIA_SX_VCO_VARBSEL_HI 22
+#define RG_GEMINIA_SX_VCO_VARBSEL_SZ 2
+#define RG_GEMINIA_SX_VCO_RTAIL_SHIFT_MSK 0x00800000
+#define RG_GEMINIA_SX_VCO_RTAIL_SHIFT_I_MSK 0xff7fffff
+#define RG_GEMINIA_SX_VCO_RTAIL_SHIFT_SFT 23
+#define RG_GEMINIA_SX_VCO_RTAIL_SHIFT_HI 23
+#define RG_GEMINIA_SX_VCO_RTAIL_SHIFT_SZ 1
+#define RG_GEMINIA_SX_VCO_CS_AWH_MSK 0x01000000
+#define RG_GEMINIA_SX_VCO_CS_AWH_I_MSK 0xfeffffff
+#define RG_GEMINIA_SX_VCO_CS_AWH_SFT 24
+#define RG_GEMINIA_SX_VCO_CS_AWH_HI 24
+#define RG_GEMINIA_SX_VCO_CS_AWH_SZ 1
+#define RG_GEMINIA_VOBF_TXMBSEL_BT_MSK 0x00000003
+#define RG_GEMINIA_VOBF_TXMBSEL_BT_I_MSK 0xfffffffc
+#define RG_GEMINIA_VOBF_TXMBSEL_BT_SFT 0
+#define RG_GEMINIA_VOBF_TXMBSEL_BT_HI 1
+#define RG_GEMINIA_VOBF_TXMBSEL_BT_SZ 2
+#define RG_GEMINIA_VOBF_TXOBSEL_BT_MSK 0x0000000c
+#define RG_GEMINIA_VOBF_TXOBSEL_BT_I_MSK 0xfffffff3
+#define RG_GEMINIA_VOBF_TXOBSEL_BT_SFT 2
+#define RG_GEMINIA_VOBF_TXOBSEL_BT_HI 3
+#define RG_GEMINIA_VOBF_TXOBSEL_BT_SZ 2
+#define RG_GEMINIA_VOBF_RXMBSEL_BT_MSK 0x00000030
+#define RG_GEMINIA_VOBF_RXMBSEL_BT_I_MSK 0xffffffcf
+#define RG_GEMINIA_VOBF_RXMBSEL_BT_SFT 4
+#define RG_GEMINIA_VOBF_RXMBSEL_BT_HI 5
+#define RG_GEMINIA_VOBF_RXMBSEL_BT_SZ 2
+#define RG_GEMINIA_VOBF_RXOBSEL_BT_MSK 0x000000c0
+#define RG_GEMINIA_VOBF_RXOBSEL_BT_I_MSK 0xffffff3f
+#define RG_GEMINIA_VOBF_RXOBSEL_BT_SFT 6
+#define RG_GEMINIA_VOBF_RXOBSEL_BT_HI 7
+#define RG_GEMINIA_VOBF_RXOBSEL_BT_SZ 2
+#define RG_GEMINIA_VOBF_TXMBSEL_WF_MSK 0x00000c00
+#define RG_GEMINIA_VOBF_TXMBSEL_WF_I_MSK 0xfffff3ff
+#define RG_GEMINIA_VOBF_TXMBSEL_WF_SFT 10
+#define RG_GEMINIA_VOBF_TXMBSEL_WF_HI 11
+#define RG_GEMINIA_VOBF_TXMBSEL_WF_SZ 2
+#define RG_GEMINIA_VOBF_TXOBSEL_WF_MSK 0x00003000
+#define RG_GEMINIA_VOBF_TXOBSEL_WF_I_MSK 0xffffcfff
+#define RG_GEMINIA_VOBF_TXOBSEL_WF_SFT 12
+#define RG_GEMINIA_VOBF_TXOBSEL_WF_HI 13
+#define RG_GEMINIA_VOBF_TXOBSEL_WF_SZ 2
+#define RG_GEMINIA_VOBF_RXMBSEL_WF_MSK 0x0000c000
+#define RG_GEMINIA_VOBF_RXMBSEL_WF_I_MSK 0xffff3fff
+#define RG_GEMINIA_VOBF_RXMBSEL_WF_SFT 14
+#define RG_GEMINIA_VOBF_RXMBSEL_WF_HI 15
+#define RG_GEMINIA_VOBF_RXMBSEL_WF_SZ 2
+#define RG_GEMINIA_VOBF_RXOBSEL_WF_MSK 0x00030000
+#define RG_GEMINIA_VOBF_RXOBSEL_WF_I_MSK 0xfffcffff
+#define RG_GEMINIA_VOBF_RXOBSEL_WF_SFT 16
+#define RG_GEMINIA_VOBF_RXOBSEL_WF_HI 17
+#define RG_GEMINIA_VOBF_RXOBSEL_WF_SZ 2
+#define RG_GEMINIA_VOBF_DIVBFSEL_MSK 0x00080000
+#define RG_GEMINIA_VOBF_DIVBFSEL_I_MSK 0xfff7ffff
+#define RG_GEMINIA_VOBF_DIVBFSEL_SFT 19
+#define RG_GEMINIA_VOBF_DIVBFSEL_HI 19
+#define RG_GEMINIA_VOBF_DIVBFSEL_SZ 1
+#define RG_GEMINIA_SX_VCO_TXOB_AW_MSK 0x00100000
+#define RG_GEMINIA_SX_VCO_TXOB_AW_I_MSK 0xffefffff
+#define RG_GEMINIA_SX_VCO_TXOB_AW_SFT 20
+#define RG_GEMINIA_SX_VCO_TXOB_AW_HI 20
+#define RG_GEMINIA_SX_VCO_TXOB_AW_SZ 1
+#define RG_GEMINIA_SX_VCO_RXOB_AW_MSK 0x00200000
+#define RG_GEMINIA_SX_VCO_RXOB_AW_I_MSK 0xffdfffff
+#define RG_GEMINIA_SX_VCO_RXOB_AW_SFT 21
+#define RG_GEMINIA_SX_VCO_RXOB_AW_HI 21
+#define RG_GEMINIA_SX_VCO_RXOB_AW_SZ 1
+#define RG_GEMINIA_VOBF_CAPIMB_POL_MSK 0x04000000
+#define RG_GEMINIA_VOBF_CAPIMB_POL_I_MSK 0xfbffffff
+#define RG_GEMINIA_VOBF_CAPIMB_POL_SFT 26
+#define RG_GEMINIA_VOBF_CAPIMB_POL_HI 26
+#define RG_GEMINIA_VOBF_CAPIMB_POL_SZ 1
+#define RG_GEMINIA_VOBF_CAPIMB_MSK 0x38000000
+#define RG_GEMINIA_VOBF_CAPIMB_I_MSK 0xc7ffffff
+#define RG_GEMINIA_VOBF_CAPIMB_SFT 27
+#define RG_GEMINIA_VOBF_CAPIMB_HI 29
+#define RG_GEMINIA_VOBF_CAPIMB_SZ 3
+#define RG_GEMINIA_EN_SX_VCOMON_MSK 0x80000000
+#define RG_GEMINIA_EN_SX_VCOMON_I_MSK 0x7fffffff
+#define RG_GEMINIA_EN_SX_VCOMON_SFT 31
+#define RG_GEMINIA_EN_SX_VCOMON_HI 31
+#define RG_GEMINIA_EN_SX_VCOMON_SZ 1
+#define RG_GEMINIA_SX_DIV_PREVDD_MSK 0x0000000f
+#define RG_GEMINIA_SX_DIV_PREVDD_I_MSK 0xfffffff0
+#define RG_GEMINIA_SX_DIV_PREVDD_SFT 0
+#define RG_GEMINIA_SX_DIV_PREVDD_HI 3
+#define RG_GEMINIA_SX_DIV_PREVDD_SZ 4
+#define RG_GEMINIA_SX_DIV_PSCVDD_MSK 0x000000f0
+#define RG_GEMINIA_SX_DIV_PSCVDD_I_MSK 0xffffff0f
+#define RG_GEMINIA_SX_DIV_PSCVDD_SFT 4
+#define RG_GEMINIA_SX_DIV_PSCVDD_HI 7
+#define RG_GEMINIA_SX_DIV_PSCVDD_SZ 4
+#define RG_GEMINIA_SX_DIV_RST_H_MSK 0x00000200
+#define RG_GEMINIA_SX_DIV_RST_H_I_MSK 0xfffffdff
+#define RG_GEMINIA_SX_DIV_RST_H_SFT 9
+#define RG_GEMINIA_SX_DIV_RST_H_HI 9
+#define RG_GEMINIA_SX_DIV_RST_H_SZ 1
+#define RG_GEMINIA_SX_DIV_SDM_EDGE_MSK 0x00000400
+#define RG_GEMINIA_SX_DIV_SDM_EDGE_I_MSK 0xfffffbff
+#define RG_GEMINIA_SX_DIV_SDM_EDGE_SFT 10
+#define RG_GEMINIA_SX_DIV_SDM_EDGE_HI 10
+#define RG_GEMINIA_SX_DIV_SDM_EDGE_SZ 1
+#define RG_GEMINIA_SX_DIV_DMYBUF_EN_MSK 0x00000800
+#define RG_GEMINIA_SX_DIV_DMYBUF_EN_I_MSK 0xfffff7ff
+#define RG_GEMINIA_SX_DIV_DMYBUF_EN_SFT 11
+#define RG_GEMINIA_SX_DIV_DMYBUF_EN_HI 11
+#define RG_GEMINIA_SX_DIV_DMYBUF_EN_SZ 1
+#define RG_GEMINIA_EN_SX_MOD_MSK 0x00020000
+#define RG_GEMINIA_EN_SX_MOD_I_MSK 0xfffdffff
+#define RG_GEMINIA_EN_SX_MOD_SFT 17
+#define RG_GEMINIA_EN_SX_MOD_HI 17
+#define RG_GEMINIA_EN_SX_MOD_SZ 1
+#define RG_GEMINIA_EN_SX_DITHER_MSK 0x00040000
+#define RG_GEMINIA_EN_SX_DITHER_I_MSK 0xfffbffff
+#define RG_GEMINIA_EN_SX_DITHER_SFT 18
+#define RG_GEMINIA_EN_SX_DITHER_HI 18
+#define RG_GEMINIA_EN_SX_DITHER_SZ 1
+#define RG_GEMINIA_SX_MOD_ORDER_MSK 0x00180000
+#define RG_GEMINIA_SX_MOD_ORDER_I_MSK 0xffe7ffff
+#define RG_GEMINIA_SX_MOD_ORDER_SFT 19
+#define RG_GEMINIA_SX_MOD_ORDER_HI 20
+#define RG_GEMINIA_SX_MOD_ORDER_SZ 2
+#define RG_GEMINIA_SX_DITHER_WEIGHT_MSK 0x00600000
+#define RG_GEMINIA_SX_DITHER_WEIGHT_I_MSK 0xff9fffff
+#define RG_GEMINIA_SX_DITHER_WEIGHT_SFT 21
+#define RG_GEMINIA_SX_DITHER_WEIGHT_HI 22
+#define RG_GEMINIA_SX_DITHER_WEIGHT_SZ 2
+#define RG_GEMINIA_SX_SUB_SEL_MAN_MSK 0x00000001
+#define RG_GEMINIA_SX_SUB_SEL_MAN_I_MSK 0xfffffffe
+#define RG_GEMINIA_SX_SUB_SEL_MAN_SFT 0
+#define RG_GEMINIA_SX_SUB_SEL_MAN_HI 0
+#define RG_GEMINIA_SX_SUB_SEL_MAN_SZ 1
+#define RG_GEMINIA_SX_SUB_SEL_MSK 0x000001fe
+#define RG_GEMINIA_SX_SUB_SEL_I_MSK 0xfffffe01
+#define RG_GEMINIA_SX_SUB_SEL_SFT 1
+#define RG_GEMINIA_SX_SUB_SEL_HI 8
+#define RG_GEMINIA_SX_SUB_SEL_SZ 8
+#define RG_GEMINIA_SX_SUB_C0P5_DIS_MSK 0x00000200
+#define RG_GEMINIA_SX_SUB_C0P5_DIS_I_MSK 0xfffffdff
+#define RG_GEMINIA_SX_SUB_C0P5_DIS_SFT 9
+#define RG_GEMINIA_SX_SUB_C0P5_DIS_HI 9
+#define RG_GEMINIA_SX_SUB_C0P5_DIS_SZ 1
+#define RG_GEMINIA_SX_SBCAL_CT_MSK 0x00000c00
+#define RG_GEMINIA_SX_SBCAL_CT_I_MSK 0xfffff3ff
+#define RG_GEMINIA_SX_SBCAL_CT_SFT 10
+#define RG_GEMINIA_SX_SBCAL_CT_HI 11
+#define RG_GEMINIA_SX_SBCAL_CT_SZ 2
+#define RG_GEMINIA_SX_SBCAL_WT_MSK 0x00001000
+#define RG_GEMINIA_SX_SBCAL_WT_I_MSK 0xffffefff
+#define RG_GEMINIA_SX_SBCAL_WT_SFT 12
+#define RG_GEMINIA_SX_SBCAL_WT_HI 12
+#define RG_GEMINIA_SX_SBCAL_WT_SZ 1
+#define RG_GEMINIA_SX_SBCAL_DIFFMIN_MSK 0x00002000
+#define RG_GEMINIA_SX_SBCAL_DIFFMIN_I_MSK 0xffffdfff
+#define RG_GEMINIA_SX_SBCAL_DIFFMIN_SFT 13
+#define RG_GEMINIA_SX_SBCAL_DIFFMIN_HI 13
+#define RG_GEMINIA_SX_SBCAL_DIFFMIN_SZ 1
+#define RG_GEMINIA_SX_SBCAL_NTARG_MAN_MSK 0x00008000
+#define RG_GEMINIA_SX_SBCAL_NTARG_MAN_I_MSK 0xffff7fff
+#define RG_GEMINIA_SX_SBCAL_NTARG_MAN_SFT 15
+#define RG_GEMINIA_SX_SBCAL_NTARG_MAN_HI 15
+#define RG_GEMINIA_SX_SBCAL_NTARG_MAN_SZ 1
+#define RG_GEMINIA_SX_SBCAL_NTARG_MSK 0xffff0000
+#define RG_GEMINIA_SX_SBCAL_NTARG_I_MSK 0x0000ffff
+#define RG_GEMINIA_SX_SBCAL_NTARG_SFT 16
+#define RG_GEMINIA_SX_SBCAL_NTARG_HI 31
+#define RG_GEMINIA_SX_SBCAL_NTARG_SZ 16
+#define RG_GEMINIA_VO_AAC_TAR_BT_MSK 0x0000000f
+#define RG_GEMINIA_VO_AAC_TAR_BT_I_MSK 0xfffffff0
+#define RG_GEMINIA_VO_AAC_TAR_BT_SFT 0
+#define RG_GEMINIA_VO_AAC_TAR_BT_HI 3
+#define RG_GEMINIA_VO_AAC_TAR_BT_SZ 4
+#define RG_GEMINIA_VO_AAC_IOST_BT_MSK 0x00000030
+#define RG_GEMINIA_VO_AAC_IOST_BT_I_MSK 0xffffffcf
+#define RG_GEMINIA_VO_AAC_IOST_BT_SFT 4
+#define RG_GEMINIA_VO_AAC_IOST_BT_HI 5
+#define RG_GEMINIA_VO_AAC_IOST_BT_SZ 2
+#define RG_GEMINIA_VO_AAC_TAR_WF_MSK 0x00000780
+#define RG_GEMINIA_VO_AAC_TAR_WF_I_MSK 0xfffff87f
+#define RG_GEMINIA_VO_AAC_TAR_WF_SFT 7
+#define RG_GEMINIA_VO_AAC_TAR_WF_HI 10
+#define RG_GEMINIA_VO_AAC_TAR_WF_SZ 4
+#define RG_GEMINIA_VO_AAC_IOST_WF_MSK 0x00001800
+#define RG_GEMINIA_VO_AAC_IOST_WF_I_MSK 0xffffe7ff
+#define RG_GEMINIA_VO_AAC_IOST_WF_SFT 11
+#define RG_GEMINIA_VO_AAC_IOST_WF_HI 12
+#define RG_GEMINIA_VO_AAC_IOST_WF_SZ 2
+#define RG_GEMINIA_VO_AAC_IMAX_MSK 0x0003c000
+#define RG_GEMINIA_VO_AAC_IMAX_I_MSK 0xfffc3fff
+#define RG_GEMINIA_VO_AAC_IMAX_SFT 14
+#define RG_GEMINIA_VO_AAC_IMAX_HI 17
+#define RG_GEMINIA_VO_AAC_IMAX_SZ 4
+#define RG_GEMINIA_VO_AAC_INIT_MSK 0x000c0000
+#define RG_GEMINIA_VO_AAC_INIT_I_MSK 0xfff3ffff
+#define RG_GEMINIA_VO_AAC_INIT_SFT 18
+#define RG_GEMINIA_VO_AAC_INIT_HI 19
+#define RG_GEMINIA_VO_AAC_INIT_SZ 2
+#define RG_GEMINIA_VO_AAC_EVA_TS_MSK 0x00300000
+#define RG_GEMINIA_VO_AAC_EVA_TS_I_MSK 0xffcfffff
+#define RG_GEMINIA_VO_AAC_EVA_TS_SFT 20
+#define RG_GEMINIA_VO_AAC_EVA_TS_HI 21
+#define RG_GEMINIA_VO_AAC_EVA_TS_SZ 2
+#define RG_GEMINIA_VO_AAC_EN_MAN_MSK 0x00800000
+#define RG_GEMINIA_VO_AAC_EN_MAN_I_MSK 0xff7fffff
+#define RG_GEMINIA_VO_AAC_EN_MAN_SFT 23
+#define RG_GEMINIA_VO_AAC_EN_MAN_HI 23
+#define RG_GEMINIA_VO_AAC_EN_MAN_SZ 1
+#define RG_GEMINIA_VO_AAC_EN_MSK 0x01000000
+#define RG_GEMINIA_VO_AAC_EN_I_MSK 0xfeffffff
+#define RG_GEMINIA_VO_AAC_EN_SFT 24
+#define RG_GEMINIA_VO_AAC_EN_HI 24
+#define RG_GEMINIA_VO_AAC_EN_SZ 1
+#define RG_GEMINIA_VO_AAC_EVA_MAN_MSK 0x02000000
+#define RG_GEMINIA_VO_AAC_EVA_MAN_I_MSK 0xfdffffff
+#define RG_GEMINIA_VO_AAC_EVA_MAN_SFT 25
+#define RG_GEMINIA_VO_AAC_EVA_MAN_HI 25
+#define RG_GEMINIA_VO_AAC_EVA_MAN_SZ 1
+#define RG_GEMINIA_VO_AAC_EVA_MSK 0x04000000
+#define RG_GEMINIA_VO_AAC_EVA_I_MSK 0xfbffffff
+#define RG_GEMINIA_VO_AAC_EVA_SFT 26
+#define RG_GEMINIA_VO_AAC_EVA_HI 26
+#define RG_GEMINIA_VO_AAC_EVA_SZ 1
+#define RG_GEMINIA_VO_AAC_TEST_EN_MSK 0x10000000
+#define RG_GEMINIA_VO_AAC_TEST_EN_I_MSK 0xefffffff
+#define RG_GEMINIA_VO_AAC_TEST_EN_SFT 28
+#define RG_GEMINIA_VO_AAC_TEST_EN_HI 28
+#define RG_GEMINIA_VO_AAC_TEST_EN_SZ 1
+#define RG_GEMINIA_VO_AAC_TEST_SEL_MSK 0x20000000
+#define RG_GEMINIA_VO_AAC_TEST_SEL_I_MSK 0xdfffffff
+#define RG_GEMINIA_VO_AAC_TEST_SEL_SFT 29
+#define RG_GEMINIA_VO_AAC_TEST_SEL_HI 29
+#define RG_GEMINIA_VO_AAC_TEST_SEL_SZ 1
+#define RG_GEMINIA_SX_TTL_INIT_MSK 0x00000003
+#define RG_GEMINIA_SX_TTL_INIT_I_MSK 0xfffffffc
+#define RG_GEMINIA_SX_TTL_INIT_SFT 0
+#define RG_GEMINIA_SX_TTL_INIT_HI 1
+#define RG_GEMINIA_SX_TTL_INIT_SZ 2
+#define RG_GEMINIA_SX_TTL_FPT_MSK 0x0000000c
+#define RG_GEMINIA_SX_TTL_FPT_I_MSK 0xfffffff3
+#define RG_GEMINIA_SX_TTL_FPT_SFT 2
+#define RG_GEMINIA_SX_TTL_FPT_HI 3
+#define RG_GEMINIA_SX_TTL_FPT_SZ 2
+#define RG_GEMINIA_SX_TTL_CPT_MSK 0x00000030
+#define RG_GEMINIA_SX_TTL_CPT_I_MSK 0xffffffcf
+#define RG_GEMINIA_SX_TTL_CPT_SFT 4
+#define RG_GEMINIA_SX_TTL_CPT_HI 5
+#define RG_GEMINIA_SX_TTL_CPT_SZ 2
+#define RG_GEMINIA_SX_TTL_ACCUM_MSK 0x00000180
+#define RG_GEMINIA_SX_TTL_ACCUM_I_MSK 0xfffffe7f
+#define RG_GEMINIA_SX_TTL_ACCUM_SFT 7
+#define RG_GEMINIA_SX_TTL_ACCUM_HI 8
+#define RG_GEMINIA_SX_TTL_ACCUM_SZ 2
+#define RG_GEMINIA_SX_TTL_SUB_MSK 0x00000c00
+#define RG_GEMINIA_SX_TTL_SUB_I_MSK 0xfffff3ff
+#define RG_GEMINIA_SX_TTL_SUB_SFT 10
+#define RG_GEMINIA_SX_TTL_SUB_HI 11
+#define RG_GEMINIA_SX_TTL_SUB_SZ 2
+#define RG_GEMINIA_SX_TTL_SUB_INV_MSK 0x00001000
+#define RG_GEMINIA_SX_TTL_SUB_INV_I_MSK 0xffffefff
+#define RG_GEMINIA_SX_TTL_SUB_INV_SFT 12
+#define RG_GEMINIA_SX_TTL_SUB_INV_HI 12
+#define RG_GEMINIA_SX_TTL_SUB_INV_SZ 1
+#define RG_GEMINIA_SX_TTL_VH_MSK 0x0000c000
+#define RG_GEMINIA_SX_TTL_VH_I_MSK 0xffff3fff
+#define RG_GEMINIA_SX_TTL_VH_SFT 14
+#define RG_GEMINIA_SX_TTL_VH_HI 15
+#define RG_GEMINIA_SX_TTL_VH_SZ 2
+#define RG_GEMINIA_SX_TTL_VL_MSK 0x00030000
+#define RG_GEMINIA_SX_TTL_VL_I_MSK 0xfffcffff
+#define RG_GEMINIA_SX_TTL_VL_SFT 16
+#define RG_GEMINIA_SX_TTL_VL_HI 17
+#define RG_GEMINIA_SX_TTL_VL_SZ 2
+#define RG_GEMINIA_SX_LPF_VTUNE_TEST_MSK 0x00080000
+#define RG_GEMINIA_SX_LPF_VTUNE_TEST_I_MSK 0xfff7ffff
+#define RG_GEMINIA_SX_LPF_VTUNE_TEST_SFT 19
+#define RG_GEMINIA_SX_LPF_VTUNE_TEST_HI 19
+#define RG_GEMINIA_SX_LPF_VTUNE_TEST_SZ 1
+#define RG_GEMINIA_DP_BBPLL_PD_MSK 0x00000001
+#define RG_GEMINIA_DP_BBPLL_PD_I_MSK 0xfffffffe
+#define RG_GEMINIA_DP_BBPLL_PD_SFT 0
+#define RG_GEMINIA_DP_BBPLL_PD_HI 0
+#define RG_GEMINIA_DP_BBPLL_PD_SZ 1
+#define RG_GEMINIA_DP_BBPLL_BP_MSK 0x00000002
+#define RG_GEMINIA_DP_BBPLL_BP_I_MSK 0xfffffffd
+#define RG_GEMINIA_DP_BBPLL_BP_SFT 1
+#define RG_GEMINIA_DP_BBPLL_BP_HI 1
+#define RG_GEMINIA_DP_BBPLL_BP_SZ 1
+#define RG_GEMINIA_EN_DP_MANUAL_MSK 0x00000004
+#define RG_GEMINIA_EN_DP_MANUAL_I_MSK 0xfffffffb
+#define RG_GEMINIA_EN_DP_MANUAL_SFT 2
+#define RG_GEMINIA_EN_DP_MANUAL_HI 2
+#define RG_GEMINIA_EN_DP_MANUAL_SZ 1
+#define RG_GEMINIA_DP_FREF_DOUB_MSK 0x00000008
+#define RG_GEMINIA_DP_FREF_DOUB_I_MSK 0xfffffff7
+#define RG_GEMINIA_DP_FREF_DOUB_SFT 3
+#define RG_GEMINIA_DP_FREF_DOUB_HI 3
+#define RG_GEMINIA_DP_FREF_DOUB_SZ 1
+#define RG_GEMINIA_DP_DAC320_DIVBY2_MSK 0x00000010
+#define RG_GEMINIA_DP_DAC320_DIVBY2_I_MSK 0xffffffef
+#define RG_GEMINIA_DP_DAC320_DIVBY2_SFT 4
+#define RG_GEMINIA_DP_DAC320_DIVBY2_HI 4
+#define RG_GEMINIA_DP_DAC320_DIVBY2_SZ 1
+#define RG_GEMINIA_DP_ADC320_DIVBY2_BT_MSK 0x00000020
+#define RG_GEMINIA_DP_ADC320_DIVBY2_BT_I_MSK 0xffffffdf
+#define RG_GEMINIA_DP_ADC320_DIVBY2_BT_SFT 5
+#define RG_GEMINIA_DP_ADC320_DIVBY2_BT_HI 5
+#define RG_GEMINIA_DP_ADC320_DIVBY2_BT_SZ 1
+#define RG_GEMINIA_DP_ADC320_DIVBY2_WF_MSK 0x00000040
+#define RG_GEMINIA_DP_ADC320_DIVBY2_WF_I_MSK 0xffffffbf
+#define RG_GEMINIA_DP_ADC320_DIVBY2_WF_SFT 6
+#define RG_GEMINIA_DP_ADC320_DIVBY2_WF_HI 6
+#define RG_GEMINIA_DP_ADC320_DIVBY2_WF_SZ 1
+#define RG_GEMINIA_EN_DPL_MOD_MSK 0x00000100
+#define RG_GEMINIA_EN_DPL_MOD_I_MSK 0xfffffeff
+#define RG_GEMINIA_EN_DPL_MOD_SFT 8
+#define RG_GEMINIA_EN_DPL_MOD_HI 8
+#define RG_GEMINIA_EN_DPL_MOD_SZ 1
+#define RG_GEMINIA_DPL_MOD_ORDER_MSK 0x00000600
+#define RG_GEMINIA_DPL_MOD_ORDER_I_MSK 0xfffff9ff
+#define RG_GEMINIA_DPL_MOD_ORDER_SFT 9
+#define RG_GEMINIA_DPL_MOD_ORDER_HI 10
+#define RG_GEMINIA_DPL_MOD_ORDER_SZ 2
+#define RG_GEMINIA_DP_REFDIV_MSK 0x0003f800
+#define RG_GEMINIA_DP_REFDIV_I_MSK 0xfffc07ff
+#define RG_GEMINIA_DP_REFDIV_SFT 11
+#define RG_GEMINIA_DP_REFDIV_HI 17
+#define RG_GEMINIA_DP_REFDIV_SZ 7
+#define RG_GEMINIA_DP_FODIV_MSK 0x01fc0000
+#define RG_GEMINIA_DP_FODIV_I_MSK 0xfe03ffff
+#define RG_GEMINIA_DP_FODIV_SFT 18
+#define RG_GEMINIA_DP_FODIV_HI 24
+#define RG_GEMINIA_DP_FODIV_SZ 7
+#define RG_GEMINIA_EN_LDO_DP_BYP_MSK 0x02000000
+#define RG_GEMINIA_EN_LDO_DP_BYP_I_MSK 0xfdffffff
+#define RG_GEMINIA_EN_LDO_DP_BYP_SFT 25
+#define RG_GEMINIA_EN_LDO_DP_BYP_HI 25
+#define RG_GEMINIA_EN_LDO_DP_BYP_SZ 1
+#define RG_GEMINIA_EN_LDO_DP_IQUP_MSK 0x04000000
+#define RG_GEMINIA_EN_LDO_DP_IQUP_I_MSK 0xfbffffff
+#define RG_GEMINIA_EN_LDO_DP_IQUP_SFT 26
+#define RG_GEMINIA_EN_LDO_DP_IQUP_HI 26
+#define RG_GEMINIA_EN_LDO_DP_IQUP_SZ 1
+#define RG_GEMINIA_DP_OD_TEST_MSK 0x08000000
+#define RG_GEMINIA_DP_OD_TEST_I_MSK 0xf7ffffff
+#define RG_GEMINIA_DP_OD_TEST_SFT 27
+#define RG_GEMINIA_DP_OD_TEST_HI 27
+#define RG_GEMINIA_DP_OD_TEST_SZ 1
+#define RG_GEMINIA_DP_BBPLL_TESTSEL_MSK 0x70000000
+#define RG_GEMINIA_DP_BBPLL_TESTSEL_I_MSK 0x8fffffff
+#define RG_GEMINIA_DP_BBPLL_TESTSEL_SFT 28
+#define RG_GEMINIA_DP_BBPLL_TESTSEL_HI 30
+#define RG_GEMINIA_DP_BBPLL_TESTSEL_SZ 3
+#define RG_GEMINIA_DP_BBPLL_ICP_MSK 0x00000003
+#define RG_GEMINIA_DP_BBPLL_ICP_I_MSK 0xfffffffc
+#define RG_GEMINIA_DP_BBPLL_ICP_SFT 0
+#define RG_GEMINIA_DP_BBPLL_ICP_HI 1
+#define RG_GEMINIA_DP_BBPLL_ICP_SZ 2
+#define RG_GEMINIA_DP_BBPLL_IDUAL_MSK 0x0000000c
+#define RG_GEMINIA_DP_BBPLL_IDUAL_I_MSK 0xfffffff3
+#define RG_GEMINIA_DP_BBPLL_IDUAL_SFT 2
+#define RG_GEMINIA_DP_BBPLL_IDUAL_HI 3
+#define RG_GEMINIA_DP_BBPLL_IDUAL_SZ 2
+#define RG_GEMINIA_DP_CP_IOSTPOL_MSK 0x00000010
+#define RG_GEMINIA_DP_CP_IOSTPOL_I_MSK 0xffffffef
+#define RG_GEMINIA_DP_CP_IOSTPOL_SFT 4
+#define RG_GEMINIA_DP_CP_IOSTPOL_HI 4
+#define RG_GEMINIA_DP_CP_IOSTPOL_SZ 1
+#define RG_GEMINIA_DP_CP_IOST_MSK 0x00000060
+#define RG_GEMINIA_DP_CP_IOST_I_MSK 0xffffff9f
+#define RG_GEMINIA_DP_CP_IOST_SFT 5
+#define RG_GEMINIA_DP_CP_IOST_HI 6
+#define RG_GEMINIA_DP_CP_IOST_SZ 2
+#define RG_GEMINIA_DP_PFD_PFDSEL_MSK 0x00000080
+#define RG_GEMINIA_DP_PFD_PFDSEL_I_MSK 0xffffff7f
+#define RG_GEMINIA_DP_PFD_PFDSEL_SFT 7
+#define RG_GEMINIA_DP_PFD_PFDSEL_HI 7
+#define RG_GEMINIA_DP_PFD_PFDSEL_SZ 1
+#define RG_GEMINIA_DP_BBPLL_PFD_DLY_MSK 0x00000300
+#define RG_GEMINIA_DP_BBPLL_PFD_DLY_I_MSK 0xfffffcff
+#define RG_GEMINIA_DP_BBPLL_PFD_DLY_SFT 8
+#define RG_GEMINIA_DP_BBPLL_PFD_DLY_HI 9
+#define RG_GEMINIA_DP_BBPLL_PFD_DLY_SZ 2
+#define RG_GEMINIA_DP_RP_MSK 0x00003800
+#define RG_GEMINIA_DP_RP_I_MSK 0xffffc7ff
+#define RG_GEMINIA_DP_RP_SFT 11
+#define RG_GEMINIA_DP_RP_HI 13
+#define RG_GEMINIA_DP_RP_SZ 3
+#define RG_GEMINIA_DP_RHP_MSK 0x0000c000
+#define RG_GEMINIA_DP_RHP_I_MSK 0xffff3fff
+#define RG_GEMINIA_DP_RHP_SFT 14
+#define RG_GEMINIA_DP_RHP_HI 15
+#define RG_GEMINIA_DP_RHP_SZ 2
+#define RG_GEMINIA_EN_DP_VT_MON_MSK 0x00020000
+#define RG_GEMINIA_EN_DP_VT_MON_I_MSK 0xfffdffff
+#define RG_GEMINIA_EN_DP_VT_MON_SFT 17
+#define RG_GEMINIA_EN_DP_VT_MON_HI 17
+#define RG_GEMINIA_EN_DP_VT_MON_SZ 1
+#define RG_GEMINIA_DP_VT_TH_HI_MSK 0x000c0000
+#define RG_GEMINIA_DP_VT_TH_HI_I_MSK 0xfff3ffff
+#define RG_GEMINIA_DP_VT_TH_HI_SFT 18
+#define RG_GEMINIA_DP_VT_TH_HI_HI 19
+#define RG_GEMINIA_DP_VT_TH_HI_SZ 2
+#define RG_GEMINIA_DP_VT_TH_LO_MSK 0x00300000
+#define RG_GEMINIA_DP_VT_TH_LO_I_MSK 0xffcfffff
+#define RG_GEMINIA_DP_VT_TH_LO_SFT 20
+#define RG_GEMINIA_DP_VT_TH_LO_HI 21
+#define RG_GEMINIA_DP_VT_TH_LO_SZ 2
+#define RG_GEMINIA_DP_BBPLL_BS_MSK 0x1f800000
+#define RG_GEMINIA_DP_BBPLL_BS_I_MSK 0xe07fffff
+#define RG_GEMINIA_DP_BBPLL_BS_SFT 23
+#define RG_GEMINIA_DP_BBPLL_BS_HI 28
+#define RG_GEMINIA_DP_BBPLL_BS_SZ 6
+#define RG_GEMINIA_DP_BBPLL_SDM_EDGE_MSK 0x80000000
+#define RG_GEMINIA_DP_BBPLL_SDM_EDGE_I_MSK 0x7fffffff
+#define RG_GEMINIA_DP_BBPLL_SDM_EDGE_SFT 31
+#define RG_GEMINIA_DP_BBPLL_SDM_EDGE_HI 31
+#define RG_GEMINIA_DP_BBPLL_SDM_EDGE_SZ 1
+#define RG_GEMINIA_DPL_RFCTRL_F_MSK 0x00ffffff
+#define RG_GEMINIA_DPL_RFCTRL_F_I_MSK 0xff000000
+#define RG_GEMINIA_DPL_RFCTRL_F_SFT 0
+#define RG_GEMINIA_DPL_RFCTRL_F_HI 23
+#define RG_GEMINIA_DPL_RFCTRL_F_SZ 24
+#define RG_GEMINIA_DPL_RFCTRL_CH_MSK 0xff000000
+#define RG_GEMINIA_DPL_RFCTRL_CH_I_MSK 0x00ffffff
+#define RG_GEMINIA_DPL_RFCTRL_CH_SFT 24
+#define RG_GEMINIA_DPL_RFCTRL_CH_HI 31
+#define RG_GEMINIA_DPL_RFCTRL_CH_SZ 8
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG15_MSK 0x0000003f
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG15_I_MSK 0xffffffc0
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG15_SFT 0
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG15_HI 5
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG15_SZ 6
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG15_MSK 0x00003f00
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG15_I_MSK 0xffffc0ff
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG15_SFT 8
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG15_HI 13
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG15_SZ 6
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG14_MSK 0x003f0000
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG14_I_MSK 0xffc0ffff
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG14_SFT 16
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG14_HI 21
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG14_SZ 6
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG14_MSK 0x3f000000
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG14_I_MSK 0xc0ffffff
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG14_SFT 24
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG14_HI 29
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG14_SZ 6
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG13_MSK 0x0000003f
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG13_I_MSK 0xffffffc0
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG13_SFT 0
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG13_HI 5
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG13_SZ 6
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG13_MSK 0x00003f00
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG13_I_MSK 0xffffc0ff
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG13_SFT 8
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG13_HI 13
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG13_SZ 6
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG12_MSK 0x003f0000
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG12_I_MSK 0xffc0ffff
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG12_SFT 16
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG12_HI 21
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG12_SZ 6
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG12_MSK 0x3f000000
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG12_I_MSK 0xc0ffffff
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG12_SFT 24
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG12_HI 29
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG12_SZ 6
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG11_MSK 0x0000003f
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG11_I_MSK 0xffffffc0
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG11_SFT 0
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG11_HI 5
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG11_SZ 6
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG11_MSK 0x00003f00
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG11_I_MSK 0xffffc0ff
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG11_SFT 8
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG11_HI 13
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG11_SZ 6
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG10_MSK 0x003f0000
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG10_I_MSK 0xffc0ffff
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG10_SFT 16
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG10_HI 21
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG10_SZ 6
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG10_MSK 0x3f000000
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG10_I_MSK 0xc0ffffff
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG10_SFT 24
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG10_HI 29
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG10_SZ 6
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG9_MSK 0x0000003f
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG9_I_MSK 0xffffffc0
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG9_SFT 0
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG9_HI 5
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG9_SZ 6
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG9_MSK 0x00003f00
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG9_I_MSK 0xffffc0ff
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG9_SFT 8
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG9_HI 13
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG9_SZ 6
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG8_MSK 0x003f0000
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG8_I_MSK 0xffc0ffff
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG8_SFT 16
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG8_HI 21
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG8_SZ 6
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG8_MSK 0x3f000000
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG8_I_MSK 0xc0ffffff
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG8_SFT 24
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG8_HI 29
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG8_SZ 6
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG7_MSK 0x0000003f
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG7_I_MSK 0xffffffc0
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG7_SFT 0
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG7_HI 5
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG7_SZ 6
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG7_MSK 0x00003f00
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG7_I_MSK 0xffffc0ff
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG7_SFT 8
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG7_HI 13
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG7_SZ 6
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG6_MSK 0x003f0000
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG6_I_MSK 0xffc0ffff
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG6_SFT 16
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG6_HI 21
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG6_SZ 6
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG6_MSK 0x3f000000
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG6_I_MSK 0xc0ffffff
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG6_SFT 24
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG6_HI 29
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG6_SZ 6
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG5_MSK 0x0000003f
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG5_I_MSK 0xffffffc0
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG5_SFT 0
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG5_HI 5
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG5_SZ 6
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG5_MSK 0x00003f00
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG5_I_MSK 0xffffc0ff
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG5_SFT 8
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG5_HI 13
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG5_SZ 6
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG4_MSK 0x003f0000
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG4_I_MSK 0xffc0ffff
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG4_SFT 16
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG4_HI 21
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG4_SZ 6
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG4_MSK 0x3f000000
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG4_I_MSK 0xc0ffffff
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG4_SFT 24
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG4_HI 29
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG4_SZ 6
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG3_MSK 0x0000003f
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG3_I_MSK 0xffffffc0
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG3_SFT 0
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG3_HI 5
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG3_SZ 6
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG3_MSK 0x00003f00
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG3_I_MSK 0xffffc0ff
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG3_SFT 8
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG3_HI 13
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG3_SZ 6
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG2_MSK 0x003f0000
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG2_I_MSK 0xffc0ffff
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG2_SFT 16
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG2_HI 21
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG2_SZ 6
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG2_MSK 0x3f000000
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG2_I_MSK 0xc0ffffff
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG2_SFT 24
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG2_HI 29
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG2_SZ 6
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG1_MSK 0x0000003f
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG1_I_MSK 0xffffffc0
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG1_SFT 0
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG1_HI 5
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG1_SZ 6
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG1_MSK 0x00003f00
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG1_I_MSK 0xffffc0ff
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG1_SFT 8
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG1_HI 13
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG1_SZ 6
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG0_MSK 0x003f0000
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG0_I_MSK 0xffc0ffff
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG0_SFT 16
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG0_HI 21
+#define RG_GEMINIA_WF_IDACAI_TZ0_PGAG0_SZ 6
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG0_MSK 0x3f000000
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG0_I_MSK 0xc0ffffff
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG0_SFT 24
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG0_HI 29
+#define RG_GEMINIA_WF_IDACAQ_TZ0_PGAG0_SZ 6
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG15_MSK 0x0000003f
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG15_I_MSK 0xffffffc0
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG15_SFT 0
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG15_HI 5
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG15_SZ 6
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG15_MSK 0x00003f00
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG15_I_MSK 0xffffc0ff
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG15_SFT 8
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG15_HI 13
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG15_SZ 6
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG14_MSK 0x003f0000
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG14_I_MSK 0xffc0ffff
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG14_SFT 16
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG14_HI 21
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG14_SZ 6
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG14_MSK 0x3f000000
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG14_I_MSK 0xc0ffffff
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG14_SFT 24
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG14_HI 29
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG14_SZ 6
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG13_MSK 0x0000003f
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG13_I_MSK 0xffffffc0
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG13_SFT 0
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG13_HI 5
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG13_SZ 6
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG13_MSK 0x00003f00
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG13_I_MSK 0xffffc0ff
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG13_SFT 8
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG13_HI 13
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG13_SZ 6
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG12_MSK 0x003f0000
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG12_I_MSK 0xffc0ffff
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG12_SFT 16
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG12_HI 21
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG12_SZ 6
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG12_MSK 0x3f000000
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG12_I_MSK 0xc0ffffff
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG12_SFT 24
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG12_HI 29
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG12_SZ 6
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG11_MSK 0x0000003f
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG11_I_MSK 0xffffffc0
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG11_SFT 0
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG11_HI 5
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG11_SZ 6
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG11_MSK 0x00003f00
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG11_I_MSK 0xffffc0ff
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG11_SFT 8
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG11_HI 13
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG11_SZ 6
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG10_MSK 0x003f0000
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG10_I_MSK 0xffc0ffff
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG10_SFT 16
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG10_HI 21
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG10_SZ 6
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG10_MSK 0x3f000000
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG10_I_MSK 0xc0ffffff
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG10_SFT 24
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG10_HI 29
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG10_SZ 6
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG9_MSK 0x0000003f
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG9_I_MSK 0xffffffc0
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG9_SFT 0
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG9_HI 5
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG9_SZ 6
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG9_MSK 0x00003f00
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG9_I_MSK 0xffffc0ff
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG9_SFT 8
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG9_HI 13
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG9_SZ 6
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG8_MSK 0x003f0000
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG8_I_MSK 0xffc0ffff
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG8_SFT 16
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG8_HI 21
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG8_SZ 6
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG8_MSK 0x3f000000
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG8_I_MSK 0xc0ffffff
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG8_SFT 24
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG8_HI 29
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG8_SZ 6
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG7_MSK 0x0000003f
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG7_I_MSK 0xffffffc0
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG7_SFT 0
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG7_HI 5
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG7_SZ 6
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG7_MSK 0x00003f00
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG7_I_MSK 0xffffc0ff
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG7_SFT 8
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG7_HI 13
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG7_SZ 6
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG6_MSK 0x003f0000
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG6_I_MSK 0xffc0ffff
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG6_SFT 16
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG6_HI 21
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG6_SZ 6
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG6_MSK 0x3f000000
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG6_I_MSK 0xc0ffffff
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG6_SFT 24
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG6_HI 29
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG6_SZ 6
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG5_MSK 0x0000003f
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG5_I_MSK 0xffffffc0
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG5_SFT 0
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG5_HI 5
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG5_SZ 6
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG5_MSK 0x00003f00
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG5_I_MSK 0xffffc0ff
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG5_SFT 8
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG5_HI 13
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG5_SZ 6
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG4_MSK 0x003f0000
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG4_I_MSK 0xffc0ffff
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG4_SFT 16
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG4_HI 21
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG4_SZ 6
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG4_MSK 0x3f000000
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG4_I_MSK 0xc0ffffff
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG4_SFT 24
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG4_HI 29
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG4_SZ 6
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG3_MSK 0x0000003f
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG3_I_MSK 0xffffffc0
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG3_SFT 0
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG3_HI 5
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG3_SZ 6
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG3_MSK 0x00003f00
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG3_I_MSK 0xffffc0ff
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG3_SFT 8
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG3_HI 13
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG3_SZ 6
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG2_MSK 0x003f0000
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG2_I_MSK 0xffc0ffff
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG2_SFT 16
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG2_HI 21
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG2_SZ 6
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG2_MSK 0x3f000000
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG2_I_MSK 0xc0ffffff
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG2_SFT 24
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG2_HI 29
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG2_SZ 6
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG1_MSK 0x0000003f
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG1_I_MSK 0xffffffc0
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG1_SFT 0
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG1_HI 5
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG1_SZ 6
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG1_MSK 0x00003f00
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG1_I_MSK 0xffffc0ff
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG1_SFT 8
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG1_HI 13
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG1_SZ 6
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG0_MSK 0x003f0000
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG0_I_MSK 0xffc0ffff
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG0_SFT 16
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG0_HI 21
+#define RG_GEMINIA_WF_IDACAI_TZ1_PGAG0_SZ 6
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG0_MSK 0x3f000000
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG0_I_MSK 0xc0ffffff
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG0_SFT 24
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG0_HI 29
+#define RG_GEMINIA_WF_IDACAQ_TZ1_PGAG0_SZ 6
+#define RG_GEMINIA_IDACAI_TZ0_COARSE4_MSK 0x0000003f
+#define RG_GEMINIA_IDACAI_TZ0_COARSE4_I_MSK 0xffffffc0
+#define RG_GEMINIA_IDACAI_TZ0_COARSE4_SFT 0
+#define RG_GEMINIA_IDACAI_TZ0_COARSE4_HI 5
+#define RG_GEMINIA_IDACAI_TZ0_COARSE4_SZ 6
+#define RG_GEMINIA_IDACAQ_TZ0_COARSE4_MSK 0x00003f00
+#define RG_GEMINIA_IDACAQ_TZ0_COARSE4_I_MSK 0xffffc0ff
+#define RG_GEMINIA_IDACAQ_TZ0_COARSE4_SFT 8
+#define RG_GEMINIA_IDACAQ_TZ0_COARSE4_HI 13
+#define RG_GEMINIA_IDACAQ_TZ0_COARSE4_SZ 6
+#define RG_GEMINIA_IDACAI_TZ0_COARSE3_MSK 0x003f0000
+#define RG_GEMINIA_IDACAI_TZ0_COARSE3_I_MSK 0xffc0ffff
+#define RG_GEMINIA_IDACAI_TZ0_COARSE3_SFT 16
+#define RG_GEMINIA_IDACAI_TZ0_COARSE3_HI 21
+#define RG_GEMINIA_IDACAI_TZ0_COARSE3_SZ 6
+#define RG_GEMINIA_IDACAQ_TZ0_COARSE3_MSK 0x3f000000
+#define RG_GEMINIA_IDACAQ_TZ0_COARSE3_I_MSK 0xc0ffffff
+#define RG_GEMINIA_IDACAQ_TZ0_COARSE3_SFT 24
+#define RG_GEMINIA_IDACAQ_TZ0_COARSE3_HI 29
+#define RG_GEMINIA_IDACAQ_TZ0_COARSE3_SZ 6
+#define RG_GEMINIA_IDACAI_TZ0_COARSE2_MSK 0x0000003f
+#define RG_GEMINIA_IDACAI_TZ0_COARSE2_I_MSK 0xffffffc0
+#define RG_GEMINIA_IDACAI_TZ0_COARSE2_SFT 0
+#define RG_GEMINIA_IDACAI_TZ0_COARSE2_HI 5
+#define RG_GEMINIA_IDACAI_TZ0_COARSE2_SZ 6
+#define RG_GEMINIA_IDACAQ_TZ0_COARSE2_MSK 0x00003f00
+#define RG_GEMINIA_IDACAQ_TZ0_COARSE2_I_MSK 0xffffc0ff
+#define RG_GEMINIA_IDACAQ_TZ0_COARSE2_SFT 8
+#define RG_GEMINIA_IDACAQ_TZ0_COARSE2_HI 13
+#define RG_GEMINIA_IDACAQ_TZ0_COARSE2_SZ 6
+#define RG_GEMINIA_IDACAI_TZ0_COARSE1_MSK 0x003f0000
+#define RG_GEMINIA_IDACAI_TZ0_COARSE1_I_MSK 0xffc0ffff
+#define RG_GEMINIA_IDACAI_TZ0_COARSE1_SFT 16
+#define RG_GEMINIA_IDACAI_TZ0_COARSE1_HI 21
+#define RG_GEMINIA_IDACAI_TZ0_COARSE1_SZ 6
+#define RG_GEMINIA_IDACAQ_TZ0_COARSE1_MSK 0x3f000000
+#define RG_GEMINIA_IDACAQ_TZ0_COARSE1_I_MSK 0xc0ffffff
+#define RG_GEMINIA_IDACAQ_TZ0_COARSE1_SFT 24
+#define RG_GEMINIA_IDACAQ_TZ0_COARSE1_HI 29
+#define RG_GEMINIA_IDACAQ_TZ0_COARSE1_SZ 6
+#define RG_GEMINIA_IDACAI_TZ0_COARSE0_MSK 0x0000003f
+#define RG_GEMINIA_IDACAI_TZ0_COARSE0_I_MSK 0xffffffc0
+#define RG_GEMINIA_IDACAI_TZ0_COARSE0_SFT 0
+#define RG_GEMINIA_IDACAI_TZ0_COARSE0_HI 5
+#define RG_GEMINIA_IDACAI_TZ0_COARSE0_SZ 6
+#define RG_GEMINIA_IDACAQ_TZ0_COARSE0_MSK 0x00003f00
+#define RG_GEMINIA_IDACAQ_TZ0_COARSE0_I_MSK 0xffffc0ff
+#define RG_GEMINIA_IDACAQ_TZ0_COARSE0_SFT 8
+#define RG_GEMINIA_IDACAQ_TZ0_COARSE0_HI 13
+#define RG_GEMINIA_IDACAQ_TZ0_COARSE0_SZ 6
+#define RG_GEMINIA_IDACAI_TZ1_COARSE4_MSK 0x0000003f
+#define RG_GEMINIA_IDACAI_TZ1_COARSE4_I_MSK 0xffffffc0
+#define RG_GEMINIA_IDACAI_TZ1_COARSE4_SFT 0
+#define RG_GEMINIA_IDACAI_TZ1_COARSE4_HI 5
+#define RG_GEMINIA_IDACAI_TZ1_COARSE4_SZ 6
+#define RG_GEMINIA_IDACAQ_TZ1_COARSE4_MSK 0x00003f00
+#define RG_GEMINIA_IDACAQ_TZ1_COARSE4_I_MSK 0xffffc0ff
+#define RG_GEMINIA_IDACAQ_TZ1_COARSE4_SFT 8
+#define RG_GEMINIA_IDACAQ_TZ1_COARSE4_HI 13
+#define RG_GEMINIA_IDACAQ_TZ1_COARSE4_SZ 6
+#define RG_GEMINIA_IDACAI_TZ1_COARSE3_MSK 0x003f0000
+#define RG_GEMINIA_IDACAI_TZ1_COARSE3_I_MSK 0xffc0ffff
+#define RG_GEMINIA_IDACAI_TZ1_COARSE3_SFT 16
+#define RG_GEMINIA_IDACAI_TZ1_COARSE3_HI 21
+#define RG_GEMINIA_IDACAI_TZ1_COARSE3_SZ 6
+#define RG_GEMINIA_IDACAQ_TZ1_COARSE3_MSK 0x3f000000
+#define RG_GEMINIA_IDACAQ_TZ1_COARSE3_I_MSK 0xc0ffffff
+#define RG_GEMINIA_IDACAQ_TZ1_COARSE3_SFT 24
+#define RG_GEMINIA_IDACAQ_TZ1_COARSE3_HI 29
+#define RG_GEMINIA_IDACAQ_TZ1_COARSE3_SZ 6
+#define RG_GEMINIA_IDACAI_TZ1_COARSE2_MSK 0x0000003f
+#define RG_GEMINIA_IDACAI_TZ1_COARSE2_I_MSK 0xffffffc0
+#define RG_GEMINIA_IDACAI_TZ1_COARSE2_SFT 0
+#define RG_GEMINIA_IDACAI_TZ1_COARSE2_HI 5
+#define RG_GEMINIA_IDACAI_TZ1_COARSE2_SZ 6
+#define RG_GEMINIA_IDACAQ_TZ1_COARSE2_MSK 0x00003f00
+#define RG_GEMINIA_IDACAQ_TZ1_COARSE2_I_MSK 0xffffc0ff
+#define RG_GEMINIA_IDACAQ_TZ1_COARSE2_SFT 8
+#define RG_GEMINIA_IDACAQ_TZ1_COARSE2_HI 13
+#define RG_GEMINIA_IDACAQ_TZ1_COARSE2_SZ 6
+#define RG_GEMINIA_IDACAI_TZ1_COARSE1_MSK 0x003f0000
+#define RG_GEMINIA_IDACAI_TZ1_COARSE1_I_MSK 0xffc0ffff
+#define RG_GEMINIA_IDACAI_TZ1_COARSE1_SFT 16
+#define RG_GEMINIA_IDACAI_TZ1_COARSE1_HI 21
+#define RG_GEMINIA_IDACAI_TZ1_COARSE1_SZ 6
+#define RG_GEMINIA_IDACAQ_TZ1_COARSE1_MSK 0x3f000000
+#define RG_GEMINIA_IDACAQ_TZ1_COARSE1_I_MSK 0xc0ffffff
+#define RG_GEMINIA_IDACAQ_TZ1_COARSE1_SFT 24
+#define RG_GEMINIA_IDACAQ_TZ1_COARSE1_HI 29
+#define RG_GEMINIA_IDACAQ_TZ1_COARSE1_SZ 6
+#define RG_GEMINIA_IDACAI_TZ1_COARSE0_MSK 0x0000003f
+#define RG_GEMINIA_IDACAI_TZ1_COARSE0_I_MSK 0xffffffc0
+#define RG_GEMINIA_IDACAI_TZ1_COARSE0_SFT 0
+#define RG_GEMINIA_IDACAI_TZ1_COARSE0_HI 5
+#define RG_GEMINIA_IDACAI_TZ1_COARSE0_SZ 6
+#define RG_GEMINIA_IDACAQ_TZ1_COARSE0_MSK 0x00003f00
+#define RG_GEMINIA_IDACAQ_TZ1_COARSE0_I_MSK 0xffffc0ff
+#define RG_GEMINIA_IDACAQ_TZ1_COARSE0_SFT 8
+#define RG_GEMINIA_IDACAQ_TZ1_COARSE0_HI 13
+#define RG_GEMINIA_IDACAQ_TZ1_COARSE0_SZ 6
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG15_MSK 0x0000003f
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG15_I_MSK 0xffffffc0
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG15_SFT 0
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG15_HI 5
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG15_SZ 6
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG15_MSK 0x00003f00
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG15_I_MSK 0xffffc0ff
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG15_SFT 8
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG15_HI 13
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG15_SZ 6
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG14_MSK 0x003f0000
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG14_I_MSK 0xffc0ffff
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG14_SFT 16
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG14_HI 21
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG14_SZ 6
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG14_MSK 0x3f000000
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG14_I_MSK 0xc0ffffff
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG14_SFT 24
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG14_HI 29
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG14_SZ 6
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG13_MSK 0x0000003f
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG13_I_MSK 0xffffffc0
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG13_SFT 0
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG13_HI 5
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG13_SZ 6
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG13_MSK 0x00003f00
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG13_I_MSK 0xffffc0ff
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG13_SFT 8
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG13_HI 13
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG13_SZ 6
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG12_MSK 0x003f0000
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG12_I_MSK 0xffc0ffff
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG12_SFT 16
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG12_HI 21
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG12_SZ 6
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG12_MSK 0x3f000000
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG12_I_MSK 0xc0ffffff
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG12_SFT 24
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG12_HI 29
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG12_SZ 6
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG11_MSK 0x0000003f
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG11_I_MSK 0xffffffc0
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG11_SFT 0
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG11_HI 5
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG11_SZ 6
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG11_MSK 0x00003f00
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG11_I_MSK 0xffffc0ff
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG11_SFT 8
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG11_HI 13
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG11_SZ 6
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG10_MSK 0x003f0000
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG10_I_MSK 0xffc0ffff
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG10_SFT 16
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG10_HI 21
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG10_SZ 6
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG10_MSK 0x3f000000
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG10_I_MSK 0xc0ffffff
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG10_SFT 24
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG10_HI 29
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG10_SZ 6
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG9_MSK 0x0000003f
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG9_I_MSK 0xffffffc0
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG9_SFT 0
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG9_HI 5
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG9_SZ 6
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG9_MSK 0x00003f00
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG9_I_MSK 0xffffc0ff
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG9_SFT 8
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG9_HI 13
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG9_SZ 6
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG8_MSK 0x003f0000
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG8_I_MSK 0xffc0ffff
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG8_SFT 16
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG8_HI 21
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG8_SZ 6
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG8_MSK 0x3f000000
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG8_I_MSK 0xc0ffffff
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG8_SFT 24
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG8_HI 29
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG8_SZ 6
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG7_MSK 0x0000003f
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG7_I_MSK 0xffffffc0
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG7_SFT 0
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG7_HI 5
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG7_SZ 6
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG7_MSK 0x00003f00
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG7_I_MSK 0xffffc0ff
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG7_SFT 8
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG7_HI 13
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG7_SZ 6
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG6_MSK 0x003f0000
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG6_I_MSK 0xffc0ffff
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG6_SFT 16
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG6_HI 21
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG6_SZ 6
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG6_MSK 0x3f000000
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG6_I_MSK 0xc0ffffff
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG6_SFT 24
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG6_HI 29
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG6_SZ 6
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG5_MSK 0x0000003f
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG5_I_MSK 0xffffffc0
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG5_SFT 0
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG5_HI 5
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG5_SZ 6
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG5_MSK 0x00003f00
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG5_I_MSK 0xffffc0ff
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG5_SFT 8
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG5_HI 13
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG5_SZ 6
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG4_MSK 0x003f0000
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG4_I_MSK 0xffc0ffff
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG4_SFT 16
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG4_HI 21
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG4_SZ 6
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG4_MSK 0x3f000000
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG4_I_MSK 0xc0ffffff
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG4_SFT 24
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG4_HI 29
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG4_SZ 6
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG3_MSK 0x0000003f
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG3_I_MSK 0xffffffc0
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG3_SFT 0
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG3_HI 5
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG3_SZ 6
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG3_MSK 0x00003f00
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG3_I_MSK 0xffffc0ff
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG3_SFT 8
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG3_HI 13
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG3_SZ 6
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG2_MSK 0x003f0000
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG2_I_MSK 0xffc0ffff
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG2_SFT 16
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG2_HI 21
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG2_SZ 6
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG2_MSK 0x3f000000
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG2_I_MSK 0xc0ffffff
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG2_SFT 24
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG2_HI 29
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG2_SZ 6
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG1_MSK 0x0000003f
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG1_I_MSK 0xffffffc0
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG1_SFT 0
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG1_HI 5
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG1_SZ 6
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG1_MSK 0x00003f00
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG1_I_MSK 0xffffc0ff
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG1_SFT 8
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG1_HI 13
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG1_SZ 6
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG0_MSK 0x003f0000
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG0_I_MSK 0xffc0ffff
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG0_SFT 16
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG0_HI 21
+#define RG_GEMINIA_BT_IDACAI_TZ0_PGAG0_SZ 6
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG0_MSK 0x3f000000
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG0_I_MSK 0xc0ffffff
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG0_SFT 24
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG0_HI 29
+#define RG_GEMINIA_BT_IDACAQ_TZ0_PGAG0_SZ 6
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG15_MSK 0x0000003f
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG15_I_MSK 0xffffffc0
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG15_SFT 0
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG15_HI 5
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG15_SZ 6
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG15_MSK 0x00003f00
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG15_I_MSK 0xffffc0ff
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG15_SFT 8
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG15_HI 13
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG15_SZ 6
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG14_MSK 0x003f0000
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG14_I_MSK 0xffc0ffff
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG14_SFT 16
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG14_HI 21
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG14_SZ 6
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG14_MSK 0x3f000000
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG14_I_MSK 0xc0ffffff
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG14_SFT 24
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG14_HI 29
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG14_SZ 6
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG13_MSK 0x0000003f
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG13_I_MSK 0xffffffc0
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG13_SFT 0
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG13_HI 5
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG13_SZ 6
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG13_MSK 0x00003f00
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG13_I_MSK 0xffffc0ff
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG13_SFT 8
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG13_HI 13
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG13_SZ 6
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG12_MSK 0x003f0000
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG12_I_MSK 0xffc0ffff
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG12_SFT 16
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG12_HI 21
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG12_SZ 6
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG12_MSK 0x3f000000
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG12_I_MSK 0xc0ffffff
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG12_SFT 24
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG12_HI 29
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG12_SZ 6
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG11_MSK 0x0000003f
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG11_I_MSK 0xffffffc0
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG11_SFT 0
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG11_HI 5
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG11_SZ 6
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG11_MSK 0x00003f00
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG11_I_MSK 0xffffc0ff
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG11_SFT 8
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG11_HI 13
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG11_SZ 6
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG10_MSK 0x003f0000
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG10_I_MSK 0xffc0ffff
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG10_SFT 16
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG10_HI 21
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG10_SZ 6
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG10_MSK 0x3f000000
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG10_I_MSK 0xc0ffffff
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG10_SFT 24
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG10_HI 29
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG10_SZ 6
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG9_MSK 0x0000003f
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG9_I_MSK 0xffffffc0
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG9_SFT 0
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG9_HI 5
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG9_SZ 6
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG9_MSK 0x00003f00
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG9_I_MSK 0xffffc0ff
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG9_SFT 8
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG9_HI 13
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG9_SZ 6
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG8_MSK 0x003f0000
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG8_I_MSK 0xffc0ffff
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG8_SFT 16
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG8_HI 21
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG8_SZ 6
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG8_MSK 0x3f000000
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG8_I_MSK 0xc0ffffff
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG8_SFT 24
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG8_HI 29
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG8_SZ 6
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG7_MSK 0x0000003f
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG7_I_MSK 0xffffffc0
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG7_SFT 0
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG7_HI 5
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG7_SZ 6
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG7_MSK 0x00003f00
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG7_I_MSK 0xffffc0ff
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG7_SFT 8
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG7_HI 13
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG7_SZ 6
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG6_MSK 0x003f0000
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG6_I_MSK 0xffc0ffff
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG6_SFT 16
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG6_HI 21
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG6_SZ 6
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG6_MSK 0x3f000000
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG6_I_MSK 0xc0ffffff
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG6_SFT 24
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG6_HI 29
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG6_SZ 6
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG5_MSK 0x0000003f
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG5_I_MSK 0xffffffc0
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG5_SFT 0
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG5_HI 5
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG5_SZ 6
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG5_MSK 0x00003f00
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG5_I_MSK 0xffffc0ff
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG5_SFT 8
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG5_HI 13
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG5_SZ 6
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG4_MSK 0x003f0000
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG4_I_MSK 0xffc0ffff
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG4_SFT 16
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG4_HI 21
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG4_SZ 6
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG4_MSK 0x3f000000
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG4_I_MSK 0xc0ffffff
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG4_SFT 24
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG4_HI 29
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG4_SZ 6
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG3_MSK 0x0000003f
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG3_I_MSK 0xffffffc0
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG3_SFT 0
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG3_HI 5
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG3_SZ 6
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG3_MSK 0x00003f00
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG3_I_MSK 0xffffc0ff
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG3_SFT 8
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG3_HI 13
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG3_SZ 6
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG2_MSK 0x003f0000
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG2_I_MSK 0xffc0ffff
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG2_SFT 16
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG2_HI 21
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG2_SZ 6
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG2_MSK 0x3f000000
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG2_I_MSK 0xc0ffffff
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG2_SFT 24
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG2_HI 29
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG2_SZ 6
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG1_MSK 0x0000003f
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG1_I_MSK 0xffffffc0
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG1_SFT 0
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG1_HI 5
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG1_SZ 6
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG1_MSK 0x00003f00
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG1_I_MSK 0xffffc0ff
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG1_SFT 8
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG1_HI 13
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG1_SZ 6
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG0_MSK 0x003f0000
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG0_I_MSK 0xffc0ffff
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG0_SFT 16
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG0_HI 21
+#define RG_GEMINIA_BT_IDACAI_TZ1_PGAG0_SZ 6
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG0_MSK 0x3f000000
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG0_I_MSK 0xc0ffffff
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG0_SFT 24
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG0_HI 29
+#define RG_GEMINIA_BT_IDACAQ_TZ1_PGAG0_SZ 6
+#define RG_GEMINIA_SX_DELAY_MSK 0x0000000f
+#define RG_GEMINIA_SX_DELAY_I_MSK 0xfffffff0
+#define RG_GEMINIA_SX_DELAY_SFT 0
+#define RG_GEMINIA_SX_DELAY_HI 3
+#define RG_GEMINIA_SX_DELAY_SZ 4
+#define RG_GEMINIA_TXDAC_DELAY_MSK 0x000000f0
+#define RG_GEMINIA_TXDAC_DELAY_I_MSK 0xffffff0f
+#define RG_GEMINIA_TXDAC_DELAY_SFT 4
+#define RG_GEMINIA_TXDAC_DELAY_HI 7
+#define RG_GEMINIA_TXDAC_DELAY_SZ 4
+#define RG_GEMINIA_TXRF_DELAY_MSK 0x00000f00
+#define RG_GEMINIA_TXRF_DELAY_I_MSK 0xfffff0ff
+#define RG_GEMINIA_TXRF_DELAY_SFT 8
+#define RG_GEMINIA_TXRF_DELAY_HI 11
+#define RG_GEMINIA_TXRF_DELAY_SZ 4
+#define RG_GEMINIA_TXPA_DELAY_MSK 0x0000f000
+#define RG_GEMINIA_TXPA_DELAY_I_MSK 0xffff0fff
+#define RG_GEMINIA_TXPA_DELAY_SFT 12
+#define RG_GEMINIA_TXPA_DELAY_HI 15
+#define RG_GEMINIA_TXPA_DELAY_SZ 4
+#define RG_GEMINIA_RXRF_DELAY_MSK 0x000f0000
+#define RG_GEMINIA_RXRF_DELAY_I_MSK 0xfff0ffff
+#define RG_GEMINIA_RXRF_DELAY_SFT 16
+#define RG_GEMINIA_RXRF_DELAY_HI 19
+#define RG_GEMINIA_RXRF_DELAY_SZ 4
+#define RG_GEMINIA_TXBTPA_DELAY_MSK 0x00f00000
+#define RG_GEMINIA_TXBTPA_DELAY_I_MSK 0xff0fffff
+#define RG_GEMINIA_TXBTPA_DELAY_SFT 20
+#define RG_GEMINIA_TXBTPA_DELAY_HI 23
+#define RG_GEMINIA_TXBTPA_DELAY_SZ 4
+#define RG_GEMINIA_TXDAC_T2R_DELAY_MSK 0x0000001f
+#define RG_GEMINIA_TXDAC_T2R_DELAY_I_MSK 0xffffffe0
+#define RG_GEMINIA_TXDAC_T2R_DELAY_SFT 0
+#define RG_GEMINIA_TXDAC_T2R_DELAY_HI 4
+#define RG_GEMINIA_TXDAC_T2R_DELAY_SZ 5
+#define RG_GEMINIA_TXRF_T2R_DELAY_MSK 0x00001f00
+#define RG_GEMINIA_TXRF_T2R_DELAY_I_MSK 0xffffe0ff
+#define RG_GEMINIA_TXRF_T2R_DELAY_SFT 8
+#define RG_GEMINIA_TXRF_T2R_DELAY_HI 12
+#define RG_GEMINIA_TXRF_T2R_DELAY_SZ 5
+#define RG_GEMINIA_TXPA_T2R_DELAY_MSK 0x001f0000
+#define RG_GEMINIA_TXPA_T2R_DELAY_I_MSK 0xffe0ffff
+#define RG_GEMINIA_TXPA_T2R_DELAY_SFT 16
+#define RG_GEMINIA_TXPA_T2R_DELAY_HI 20
+#define RG_GEMINIA_TXPA_T2R_DELAY_SZ 5
+#define RG_GEMINIA_RXRF_T2R_DELAY_MSK 0x1f000000
+#define RG_GEMINIA_RXRF_T2R_DELAY_I_MSK 0xe0ffffff
+#define RG_GEMINIA_RXRF_T2R_DELAY_SFT 24
+#define RG_GEMINIA_RXRF_T2R_DELAY_HI 28
+#define RG_GEMINIA_RXRF_T2R_DELAY_SZ 5
+#define RG_GEMINIA_TXDAC_R2T_DELAY_MSK 0x0000001f
+#define RG_GEMINIA_TXDAC_R2T_DELAY_I_MSK 0xffffffe0
+#define RG_GEMINIA_TXDAC_R2T_DELAY_SFT 0
+#define RG_GEMINIA_TXDAC_R2T_DELAY_HI 4
+#define RG_GEMINIA_TXDAC_R2T_DELAY_SZ 5
+#define RG_GEMINIA_TXRF_R2T_DELAY_MSK 0x00001f00
+#define RG_GEMINIA_TXRF_R2T_DELAY_I_MSK 0xffffe0ff
+#define RG_GEMINIA_TXRF_R2T_DELAY_SFT 8
+#define RG_GEMINIA_TXRF_R2T_DELAY_HI 12
+#define RG_GEMINIA_TXRF_R2T_DELAY_SZ 5
+#define RG_GEMINIA_TXPA_R2T_DELAY_MSK 0x001f0000
+#define RG_GEMINIA_TXPA_R2T_DELAY_I_MSK 0xffe0ffff
+#define RG_GEMINIA_TXPA_R2T_DELAY_SFT 16
+#define RG_GEMINIA_TXPA_R2T_DELAY_HI 20
+#define RG_GEMINIA_TXPA_R2T_DELAY_SZ 5
+#define RG_GEMINIA_RXRF_R2T_DELAY_MSK 0x1f000000
+#define RG_GEMINIA_RXRF_R2T_DELAY_I_MSK 0xe0ffffff
+#define RG_GEMINIA_RXRF_R2T_DELAY_SFT 24
+#define RG_GEMINIA_RXRF_R2T_DELAY_HI 28
+#define RG_GEMINIA_RXRF_R2T_DELAY_SZ 5
+#define RG_GEMINIA_WF_RX_DCCAL_DELAY_MSK 0x00000007
+#define RG_GEMINIA_WF_RX_DCCAL_DELAY_I_MSK 0xfffffff8
+#define RG_GEMINIA_WF_RX_DCCAL_DELAY_SFT 0
+#define RG_GEMINIA_WF_RX_DCCAL_DELAY_HI 2
+#define RG_GEMINIA_WF_RX_DCCAL_DELAY_SZ 3
+#define RG_GEMINIA_BT_RX_DCCAL_DELAY_MSK 0x00000070
+#define RG_GEMINIA_BT_RX_DCCAL_DELAY_I_MSK 0xffffff8f
+#define RG_GEMINIA_BT_RX_DCCAL_DELAY_SFT 4
+#define RG_GEMINIA_BT_RX_DCCAL_DELAY_HI 6
+#define RG_GEMINIA_BT_RX_DCCAL_DELAY_SZ 3
+#define RG_GEMINIA_RX_RCCAL_DELAY_MSK 0x00000700
+#define RG_GEMINIA_RX_RCCAL_DELAY_I_MSK 0xfffff8ff
+#define RG_GEMINIA_RX_RCCAL_DELAY_SFT 8
+#define RG_GEMINIA_RX_RCCAL_DELAY_HI 10
+#define RG_GEMINIA_RX_RCCAL_DELAY_SZ 3
+#define RG_GEMINIA_TX_LOCAL_DELAY_MSK 0x00007000
+#define RG_GEMINIA_TX_LOCAL_DELAY_I_MSK 0xffff8fff
+#define RG_GEMINIA_TX_LOCAL_DELAY_SFT 12
+#define RG_GEMINIA_TX_LOCAL_DELAY_HI 14
+#define RG_GEMINIA_TX_LOCAL_DELAY_SZ 3
+#define RG_GEMINIA_TX_IQCAL_DELAY_MSK 0x00070000
+#define RG_GEMINIA_TX_IQCAL_DELAY_I_MSK 0xfff8ffff
+#define RG_GEMINIA_TX_IQCAL_DELAY_SFT 16
+#define RG_GEMINIA_TX_IQCAL_DELAY_HI 18
+#define RG_GEMINIA_TX_IQCAL_DELAY_SZ 3
+#define RG_GEMINIA_RX_IQCAL_DELAY_MSK 0x00700000
+#define RG_GEMINIA_RX_IQCAL_DELAY_I_MSK 0xff8fffff
+#define RG_GEMINIA_RX_IQCAL_DELAY_SFT 20
+#define RG_GEMINIA_RX_IQCAL_DELAY_HI 22
+#define RG_GEMINIA_RX_IQCAL_DELAY_SZ 3
+#define RG_GEMINIA_PGAG_RCCAL_MSK 0x0000000f
+#define RG_GEMINIA_PGAG_RCCAL_I_MSK 0xfffffff0
+#define RG_GEMINIA_PGAG_RCCAL_SFT 0
+#define RG_GEMINIA_PGAG_RCCAL_HI 3
+#define RG_GEMINIA_PGAG_RCCAL_SZ 4
+#define RG_GEMINIA_PGAG_TXCAL_MSK 0x000000f0
+#define RG_GEMINIA_PGAG_TXCAL_I_MSK 0xffffff0f
+#define RG_GEMINIA_PGAG_TXCAL_SFT 4
+#define RG_GEMINIA_PGAG_TXCAL_HI 7
+#define RG_GEMINIA_PGAG_TXCAL_SZ 4
+#define RG_GEMINIA_TX_GAIN_TXCAL_MSK 0x00007f00
+#define RG_GEMINIA_TX_GAIN_TXCAL_I_MSK 0xffff80ff
+#define RG_GEMINIA_TX_GAIN_TXCAL_SFT 8
+#define RG_GEMINIA_TX_GAIN_TXCAL_HI 14
+#define RG_GEMINIA_TX_GAIN_TXCAL_SZ 7
+#define RG_GEMINIA_RFG_RXIQCAL_MSK 0x00030000
+#define RG_GEMINIA_RFG_RXIQCAL_I_MSK 0xfffcffff
+#define RG_GEMINIA_RFG_RXIQCAL_SFT 16
+#define RG_GEMINIA_RFG_RXIQCAL_HI 17
+#define RG_GEMINIA_RFG_RXIQCAL_SZ 2
+#define RG_GEMINIA_PGAG_RXIQCAL_MSK 0x003c0000
+#define RG_GEMINIA_PGAG_RXIQCAL_I_MSK 0xffc3ffff
+#define RG_GEMINIA_PGAG_RXIQCAL_SFT 18
+#define RG_GEMINIA_PGAG_RXIQCAL_HI 21
+#define RG_GEMINIA_PGAG_RXIQCAL_SZ 4
+#define RG_GEMINIA_TX_GAIN_RXIQCAL_MSK 0x1fc00000
+#define RG_GEMINIA_TX_GAIN_RXIQCAL_I_MSK 0xe03fffff
+#define RG_GEMINIA_TX_GAIN_RXIQCAL_SFT 22
+#define RG_GEMINIA_TX_GAIN_RXIQCAL_HI 28
+#define RG_GEMINIA_TX_GAIN_RXIQCAL_SZ 7
+#define RG_GEMINIA_RFG_DPDCAL_MSK 0x00000003
+#define RG_GEMINIA_RFG_DPDCAL_I_MSK 0xfffffffc
+#define RG_GEMINIA_RFG_DPDCAL_SFT 0
+#define RG_GEMINIA_RFG_DPDCAL_HI 1
+#define RG_GEMINIA_RFG_DPDCAL_SZ 2
+#define RG_GEMINIA_PGAG_DPDCAL_MSK 0x0000003c
+#define RG_GEMINIA_PGAG_DPDCAL_I_MSK 0xffffffc3
+#define RG_GEMINIA_PGAG_DPDCAL_SFT 2
+#define RG_GEMINIA_PGAG_DPDCAL_HI 5
+#define RG_GEMINIA_PGAG_DPDCAL_SZ 4
+#define RG_GEMINIA_TX_GAIN_DPDCAL_MSK 0x00001fc0
+#define RG_GEMINIA_TX_GAIN_DPDCAL_I_MSK 0xffffe03f
+#define RG_GEMINIA_TX_GAIN_DPDCAL_SFT 6
+#define RG_GEMINIA_TX_GAIN_DPDCAL_HI 12
+#define RG_GEMINIA_TX_GAIN_DPDCAL_SZ 7
+#define DB_GEMINIA_AD_ADC_I_OUT_MSK 0x000003ff
+#define DB_GEMINIA_AD_ADC_I_OUT_I_MSK 0xfffffc00
+#define DB_GEMINIA_AD_ADC_I_OUT_SFT 0
+#define DB_GEMINIA_AD_ADC_I_OUT_HI 9
+#define DB_GEMINIA_AD_ADC_I_OUT_SZ 10
+#define DB_GEMINIA_AD_ADC_Q_OUT_MSK 0x000ffc00
+#define DB_GEMINIA_AD_ADC_Q_OUT_I_MSK 0xfff003ff
+#define DB_GEMINIA_AD_ADC_Q_OUT_SFT 10
+#define DB_GEMINIA_AD_ADC_Q_OUT_HI 19
+#define DB_GEMINIA_AD_ADC_Q_OUT_SZ 10
+#define DB_GEMINIA_AD_RX_RSSIADC_MSK 0x00f00000
+#define DB_GEMINIA_AD_RX_RSSIADC_I_MSK 0xff0fffff
+#define DB_GEMINIA_AD_RX_RSSIADC_SFT 20
+#define DB_GEMINIA_AD_RX_RSSIADC_HI 23
+#define DB_GEMINIA_AD_RX_RSSIADC_SZ 4
+#define DB_GEMINIA_DA_SARADC_BIT_MSK 0x3f000000
+#define DB_GEMINIA_DA_SARADC_BIT_I_MSK 0xc0ffffff
+#define DB_GEMINIA_DA_SARADC_BIT_SFT 24
+#define DB_GEMINIA_DA_SARADC_BIT_HI 29
+#define DB_GEMINIA_DA_SARADC_BIT_SZ 6
+#define GEMINIA_SAR_ADC_FSM_RDY_MSK 0x40000000
+#define GEMINIA_SAR_ADC_FSM_RDY_I_MSK 0xbfffffff
+#define GEMINIA_SAR_ADC_FSM_RDY_SFT 30
+#define GEMINIA_SAR_ADC_FSM_RDY_HI 30
+#define GEMINIA_SAR_ADC_FSM_RDY_SZ 1
+#define DB_GEMINIA_DA_SX_SUB_SEL_MSK 0x000000ff
+#define DB_GEMINIA_DA_SX_SUB_SEL_I_MSK 0xffffff00
+#define DB_GEMINIA_DA_SX_SUB_SEL_SFT 0
+#define DB_GEMINIA_DA_SX_SUB_SEL_HI 7
+#define DB_GEMINIA_DA_SX_SUB_SEL_SZ 8
+#define DB_GEMINIA_DA_SX_VCO_ISEL_MSK 0x00001e00
+#define DB_GEMINIA_DA_SX_VCO_ISEL_I_MSK 0xffffe1ff
+#define DB_GEMINIA_DA_SX_VCO_ISEL_SFT 9
+#define DB_GEMINIA_DA_SX_VCO_ISEL_HI 12
+#define DB_GEMINIA_DA_SX_VCO_ISEL_SZ 4
+#define DB_GEMINIA_VO_AAC_COMPOUT_MSK 0x00002000
+#define DB_GEMINIA_VO_AAC_COMPOUT_I_MSK 0xffffdfff
+#define DB_GEMINIA_VO_AAC_COMPOUT_SFT 13
+#define DB_GEMINIA_VO_AAC_COMPOUT_HI 13
+#define DB_GEMINIA_VO_AAC_COMPOUT_SZ 1
+#define DB_GEMINIA_SX_TTL_VT_DET_MSK 0x00018000
+#define DB_GEMINIA_SX_TTL_VT_DET_I_MSK 0xfffe7fff
+#define DB_GEMINIA_SX_TTL_VT_DET_SFT 15
+#define DB_GEMINIA_SX_TTL_VT_DET_HI 16
+#define DB_GEMINIA_SX_TTL_VT_DET_SZ 2
+#define DB_GEMINIA_AD_DP_VT_MON_Q_MSK 0x60000000
+#define DB_GEMINIA_AD_DP_VT_MON_Q_I_MSK 0x9fffffff
+#define DB_GEMINIA_AD_DP_VT_MON_Q_SFT 29
+#define DB_GEMINIA_AD_DP_VT_MON_Q_HI 30
+#define DB_GEMINIA_AD_DP_VT_MON_Q_SZ 2
+#define DB_GEMINIA_SX_SBCAL_NCOUNT_MSK 0x0000ffff
+#define DB_GEMINIA_SX_SBCAL_NCOUNT_I_MSK 0xffff0000
+#define DB_GEMINIA_SX_SBCAL_NCOUNT_SFT 0
+#define DB_GEMINIA_SX_SBCAL_NCOUNT_HI 15
+#define DB_GEMINIA_SX_SBCAL_NCOUNT_SZ 16
+#define DB_GEMINIA_SX_SBCAL_NTARGET_MSK 0xffff0000
+#define DB_GEMINIA_SX_SBCAL_NTARGET_I_MSK 0x0000ffff
+#define DB_GEMINIA_SX_SBCAL_NTARGET_SFT 16
+#define DB_GEMINIA_SX_SBCAL_NTARGET_HI 31
+#define DB_GEMINIA_SX_SBCAL_NTARGET_SZ 16
+#define RG_GEMINIA_NFRAC_DELTA_MSK 0x00ffffff
+#define RG_GEMINIA_NFRAC_DELTA_I_MSK 0xff000000
+#define RG_GEMINIA_NFRAC_DELTA_SFT 0
+#define RG_GEMINIA_NFRAC_DELTA_HI 23
+#define RG_GEMINIA_NFRAC_DELTA_SZ 24
+#define RG_GEMINIA_40M_MODE_MSK 0x01000000
+#define RG_GEMINIA_40M_MODE_I_MSK 0xfeffffff
+#define RG_GEMINIA_40M_MODE_SFT 24
+#define RG_GEMINIA_40M_MODE_HI 24
+#define RG_GEMINIA_40M_MODE_SZ 1
+#define RG_GEMINIA_LO_UP_CH_MSK 0x10000000
+#define RG_GEMINIA_LO_UP_CH_I_MSK 0xefffffff
+#define RG_GEMINIA_LO_UP_CH_SFT 28
+#define RG_GEMINIA_LO_UP_CH_HI 28
+#define RG_GEMINIA_LO_UP_CH_SZ 1
+#define RG_GEMINIA_RX_IQ_ALPHA_MSK 0x0000001f
+#define RG_GEMINIA_RX_IQ_ALPHA_I_MSK 0xffffffe0
+#define RG_GEMINIA_RX_IQ_ALPHA_SFT 0
+#define RG_GEMINIA_RX_IQ_ALPHA_HI 4
+#define RG_GEMINIA_RX_IQ_ALPHA_SZ 5
+#define RG_GEMINIA_RX_IQ_THETA_MSK 0x00001f00
+#define RG_GEMINIA_RX_IQ_THETA_I_MSK 0xffffe0ff
+#define RG_GEMINIA_RX_IQ_THETA_SFT 8
+#define RG_GEMINIA_RX_IQ_THETA_HI 12
+#define RG_GEMINIA_RX_IQ_THETA_SZ 5
+#define RG_GEMINIA_RX_IQ_MANUAL_MSK 0x00010000
+#define RG_GEMINIA_RX_IQ_MANUAL_I_MSK 0xfffeffff
+#define RG_GEMINIA_RX_IQ_MANUAL_SFT 16
+#define RG_GEMINIA_RX_IQ_MANUAL_HI 16
+#define RG_GEMINIA_RX_IQ_MANUAL_SZ 1
+#define RG_GEMINIA_RXIQ_NOSHRK_MSK 0x00020000
+#define RG_GEMINIA_RXIQ_NOSHRK_I_MSK 0xfffdffff
+#define RG_GEMINIA_RXIQ_NOSHRK_SFT 17
+#define RG_GEMINIA_RXIQ_NOSHRK_HI 17
+#define RG_GEMINIA_RXIQ_NOSHRK_SZ 1
+#define RG_GEMINIA_RX_RSSIADC_TH_MSK 0x00f00000
+#define RG_GEMINIA_RX_RSSIADC_TH_I_MSK 0xff0fffff
+#define RG_GEMINIA_RX_RSSIADC_TH_SFT 20
+#define RG_GEMINIA_RX_RSSIADC_TH_HI 23
+#define RG_GEMINIA_RX_RSSIADC_TH_SZ 4
+#define RG_GEMINIA_RSSI_EDGE_SEL_MSK 0x04000000
+#define RG_GEMINIA_RSSI_EDGE_SEL_I_MSK 0xfbffffff
+#define RG_GEMINIA_RSSI_EDGE_SEL_SFT 26
+#define RG_GEMINIA_RSSI_EDGE_SEL_HI 26
+#define RG_GEMINIA_RSSI_EDGE_SEL_SZ 1
+#define RG_GEMINIA_ADC_EDGE_SEL_MSK 0x08000000
+#define RG_GEMINIA_ADC_EDGE_SEL_I_MSK 0xf7ffffff
+#define RG_GEMINIA_ADC_EDGE_SEL_SFT 27
+#define RG_GEMINIA_ADC_EDGE_SEL_HI 27
+#define RG_GEMINIA_ADC_EDGE_SEL_SZ 1
+#define RG_GEMINIA_Q_INV_MSK 0x10000000
+#define RG_GEMINIA_Q_INV_I_MSK 0xefffffff
+#define RG_GEMINIA_Q_INV_SFT 28
+#define RG_GEMINIA_Q_INV_HI 28
+#define RG_GEMINIA_Q_INV_SZ 1
+#define RG_GEMINIA_I_INV_MSK 0x20000000
+#define RG_GEMINIA_I_INV_I_MSK 0xdfffffff
+#define RG_GEMINIA_I_INV_SFT 29
+#define RG_GEMINIA_I_INV_HI 29
+#define RG_GEMINIA_I_INV_SZ 1
+#define RG_GEMINIA_IQ_SWAP_MSK 0x40000000
+#define RG_GEMINIA_IQ_SWAP_I_MSK 0xbfffffff
+#define RG_GEMINIA_IQ_SWAP_SFT 30
+#define RG_GEMINIA_IQ_SWAP_HI 30
+#define RG_GEMINIA_IQ_SWAP_SZ 1
+#define RG_GEMINIA_SIGN_SWAP_MSK 0x80000000
+#define RG_GEMINIA_SIGN_SWAP_I_MSK 0x7fffffff
+#define RG_GEMINIA_SIGN_SWAP_SFT 31
+#define RG_GEMINIA_SIGN_SWAP_HI 31
+#define RG_GEMINIA_SIGN_SWAP_SZ 1
+#define RG_GEMINIA_TX_IQ_ALPHA_MSK 0x0000001f
+#define RG_GEMINIA_TX_IQ_ALPHA_I_MSK 0xffffffe0
+#define RG_GEMINIA_TX_IQ_ALPHA_SFT 0
+#define RG_GEMINIA_TX_IQ_ALPHA_HI 4
+#define RG_GEMINIA_TX_IQ_ALPHA_SZ 5
+#define RG_GEMINIA_TX_IQ_THETA_MSK 0x00001f00
+#define RG_GEMINIA_TX_IQ_THETA_I_MSK 0xffffe0ff
+#define RG_GEMINIA_TX_IQ_THETA_SFT 8
+#define RG_GEMINIA_TX_IQ_THETA_HI 12
+#define RG_GEMINIA_TX_IQ_THETA_SZ 5
+#define RG_GEMINIA_TX_IQ_MANUAL_MSK 0x00010000
+#define RG_GEMINIA_TX_IQ_MANUAL_I_MSK 0xfffeffff
+#define RG_GEMINIA_TX_IQ_MANUAL_SFT 16
+#define RG_GEMINIA_TX_IQ_MANUAL_HI 16
+#define RG_GEMINIA_TX_IQ_MANUAL_SZ 1
+#define RG_GEMINIA_TXIQ_NOSHRK_MSK 0x00020000
+#define RG_GEMINIA_TXIQ_NOSHRK_I_MSK 0xfffdffff
+#define RG_GEMINIA_TXIQ_NOSHRK_SFT 17
+#define RG_GEMINIA_TXIQ_NOSHRK_HI 17
+#define RG_GEMINIA_TXIQ_NOSHRK_SZ 1
+#define RG_GEMINIA_TX_FREQ_OFFSET_MSK 0x0000ffff
+#define RG_GEMINIA_TX_FREQ_OFFSET_I_MSK 0xffff0000
+#define RG_GEMINIA_TX_FREQ_OFFSET_SFT 0
+#define RG_GEMINIA_TX_FREQ_OFFSET_HI 15
+#define RG_GEMINIA_TX_FREQ_OFFSET_SZ 16
+#define RG_GEMINIA_TONE_SCALE_MSK 0x01ff0000
+#define RG_GEMINIA_TONE_SCALE_I_MSK 0xfe00ffff
+#define RG_GEMINIA_TONE_SCALE_SFT 16
+#define RG_GEMINIA_TONE_SCALE_HI 24
+#define RG_GEMINIA_TONE_SCALE_SZ 9
+#define RG_GEMINIA_TX_UP8X_MAN_EN_MSK 0x08000000
+#define RG_GEMINIA_TX_UP8X_MAN_EN_I_MSK 0xf7ffffff
+#define RG_GEMINIA_TX_UP8X_MAN_EN_SFT 27
+#define RG_GEMINIA_TX_UP8X_MAN_EN_HI 27
+#define RG_GEMINIA_TX_UP8X_MAN_EN_SZ 1
+#define RG_GEMINIA_DIS_DAC_OFFSET_MSK 0x10000000
+#define RG_GEMINIA_DIS_DAC_OFFSET_I_MSK 0xefffffff
+#define RG_GEMINIA_DIS_DAC_OFFSET_SFT 28
+#define RG_GEMINIA_DIS_DAC_OFFSET_HI 28
+#define RG_GEMINIA_DIS_DAC_OFFSET_SZ 1
+#define RG_GEMINIA_EXT_DAC_EN_MSK 0x20000000
+#define RG_GEMINIA_EXT_DAC_EN_I_MSK 0xdfffffff
+#define RG_GEMINIA_EXT_DAC_EN_SFT 29
+#define RG_GEMINIA_EXT_DAC_EN_HI 29
+#define RG_GEMINIA_EXT_DAC_EN_SZ 1
+#define RG_GEMINIA_DPLL_CLK320BY2_MSK 0x40000000
+#define RG_GEMINIA_DPLL_CLK320BY2_I_MSK 0xbfffffff
+#define RG_GEMINIA_DPLL_CLK320BY2_SFT 30
+#define RG_GEMINIA_DPLL_CLK320BY2_HI 30
+#define RG_GEMINIA_DPLL_CLK320BY2_SZ 1
+#define RG_GEMINIA_CBW_20_40_MSK 0x80000000
+#define RG_GEMINIA_CBW_20_40_I_MSK 0x7fffffff
+#define RG_GEMINIA_CBW_20_40_SFT 31
+#define RG_GEMINIA_CBW_20_40_HI 31
+#define RG_GEMINIA_CBW_20_40_SZ 1
+#define RG_GEMINIA_DAC_DC_Q_MSK 0x000003ff
+#define RG_GEMINIA_DAC_DC_Q_I_MSK 0xfffffc00
+#define RG_GEMINIA_DAC_DC_Q_SFT 0
+#define RG_GEMINIA_DAC_DC_Q_HI 9
+#define RG_GEMINIA_DAC_DC_Q_SZ 10
+#define RG_GEMINIA_DAC_DC_I_MSK 0x03ff0000
+#define RG_GEMINIA_DAC_DC_I_I_MSK 0xfc00ffff
+#define RG_GEMINIA_DAC_DC_I_SFT 16
+#define RG_GEMINIA_DAC_DC_I_HI 25
+#define RG_GEMINIA_DAC_DC_I_SZ 10
+#define RG_GEMINIA_DAC_Q_SET_MSK 0x000003ff
+#define RG_GEMINIA_DAC_Q_SET_I_MSK 0xfffffc00
+#define RG_GEMINIA_DAC_Q_SET_SFT 0
+#define RG_GEMINIA_DAC_Q_SET_HI 9
+#define RG_GEMINIA_DAC_Q_SET_SZ 10
+#define RG_GEMINIA_DAC_MAN_Q_EN_MSK 0x00001000
+#define RG_GEMINIA_DAC_MAN_Q_EN_I_MSK 0xffffefff
+#define RG_GEMINIA_DAC_MAN_Q_EN_SFT 12
+#define RG_GEMINIA_DAC_MAN_Q_EN_HI 12
+#define RG_GEMINIA_DAC_MAN_Q_EN_SZ 1
+#define RG_GEMINIA_DAC_I_SET_MSK 0x03ff0000
+#define RG_GEMINIA_DAC_I_SET_I_MSK 0xfc00ffff
+#define RG_GEMINIA_DAC_I_SET_SFT 16
+#define RG_GEMINIA_DAC_I_SET_HI 25
+#define RG_GEMINIA_DAC_I_SET_SZ 10
+#define RG_GEMINIA_DAC_MAN_I_EN_MSK 0x10000000
+#define RG_GEMINIA_DAC_MAN_I_EN_I_MSK 0xefffffff
+#define RG_GEMINIA_DAC_MAN_I_EN_SFT 28
+#define RG_GEMINIA_DAC_MAN_I_EN_HI 28
+#define RG_GEMINIA_DAC_MAN_I_EN_SZ 1
+#define RG_GEMINIA_BW20_HB_COEF_01_MSK 0x00001fff
+#define RG_GEMINIA_BW20_HB_COEF_01_I_MSK 0xffffe000
+#define RG_GEMINIA_BW20_HB_COEF_01_SFT 0
+#define RG_GEMINIA_BW20_HB_COEF_01_HI 12
+#define RG_GEMINIA_BW20_HB_COEF_01_SZ 13
+#define RG_GEMINIA_BW20_HB_COEF_00_MSK 0x1fff0000
+#define RG_GEMINIA_BW20_HB_COEF_00_I_MSK 0xe000ffff
+#define RG_GEMINIA_BW20_HB_COEF_00_SFT 16
+#define RG_GEMINIA_BW20_HB_COEF_00_HI 28
+#define RG_GEMINIA_BW20_HB_COEF_00_SZ 13
+#define RG_GEMINIA_BW20_HB_COEF_03_MSK 0x00001fff
+#define RG_GEMINIA_BW20_HB_COEF_03_I_MSK 0xffffe000
+#define RG_GEMINIA_BW20_HB_COEF_03_SFT 0
+#define RG_GEMINIA_BW20_HB_COEF_03_HI 12
+#define RG_GEMINIA_BW20_HB_COEF_03_SZ 13
+#define RG_GEMINIA_BW20_HB_COEF_02_MSK 0x1fff0000
+#define RG_GEMINIA_BW20_HB_COEF_02_I_MSK 0xe000ffff
+#define RG_GEMINIA_BW20_HB_COEF_02_SFT 16
+#define RG_GEMINIA_BW20_HB_COEF_02_HI 28
+#define RG_GEMINIA_BW20_HB_COEF_02_SZ 13
+#define RG_GEMINIA_BW20_HB_COEF_05_MSK 0x00001fff
+#define RG_GEMINIA_BW20_HB_COEF_05_I_MSK 0xffffe000
+#define RG_GEMINIA_BW20_HB_COEF_05_SFT 0
+#define RG_GEMINIA_BW20_HB_COEF_05_HI 12
+#define RG_GEMINIA_BW20_HB_COEF_05_SZ 13
+#define RG_GEMINIA_BW20_HB_COEF_04_MSK 0x1fff0000
+#define RG_GEMINIA_BW20_HB_COEF_04_I_MSK 0xe000ffff
+#define RG_GEMINIA_BW20_HB_COEF_04_SFT 16
+#define RG_GEMINIA_BW20_HB_COEF_04_HI 28
+#define RG_GEMINIA_BW20_HB_COEF_04_SZ 13
+#define RG_GEMINIA_BW20_HB_COEF_07_MSK 0x00001fff
+#define RG_GEMINIA_BW20_HB_COEF_07_I_MSK 0xffffe000
+#define RG_GEMINIA_BW20_HB_COEF_07_SFT 0
+#define RG_GEMINIA_BW20_HB_COEF_07_HI 12
+#define RG_GEMINIA_BW20_HB_COEF_07_SZ 13
+#define RG_GEMINIA_BW20_HB_COEF_06_MSK 0x1fff0000
+#define RG_GEMINIA_BW20_HB_COEF_06_I_MSK 0xe000ffff
+#define RG_GEMINIA_BW20_HB_COEF_06_SFT 16
+#define RG_GEMINIA_BW20_HB_COEF_06_HI 28
+#define RG_GEMINIA_BW20_HB_COEF_06_SZ 13
+#define RG_GEMINIA_BW20_HB_COEF_09_MSK 0x00001fff
+#define RG_GEMINIA_BW20_HB_COEF_09_I_MSK 0xffffe000
+#define RG_GEMINIA_BW20_HB_COEF_09_SFT 0
+#define RG_GEMINIA_BW20_HB_COEF_09_HI 12
+#define RG_GEMINIA_BW20_HB_COEF_09_SZ 13
+#define RG_GEMINIA_BW20_HB_COEF_08_MSK 0x1fff0000
+#define RG_GEMINIA_BW20_HB_COEF_08_I_MSK 0xe000ffff
+#define RG_GEMINIA_BW20_HB_COEF_08_SFT 16
+#define RG_GEMINIA_BW20_HB_COEF_08_HI 28
+#define RG_GEMINIA_BW20_HB_COEF_08_SZ 13
+#define RG_GEMINIA_BW20_HB_COEF_11_MSK 0x00001fff
+#define RG_GEMINIA_BW20_HB_COEF_11_I_MSK 0xffffe000
+#define RG_GEMINIA_BW20_HB_COEF_11_SFT 0
+#define RG_GEMINIA_BW20_HB_COEF_11_HI 12
+#define RG_GEMINIA_BW20_HB_COEF_11_SZ 13
+#define RG_GEMINIA_BW20_HB_COEF_10_MSK 0x1fff0000
+#define RG_GEMINIA_BW20_HB_COEF_10_I_MSK 0xe000ffff
+#define RG_GEMINIA_BW20_HB_COEF_10_SFT 16
+#define RG_GEMINIA_BW20_HB_COEF_10_HI 28
+#define RG_GEMINIA_BW20_HB_COEF_10_SZ 13
+#define RG_GEMINIA_PHASE_STEP_VALUE_MSK 0x0000ffff
+#define RG_GEMINIA_PHASE_STEP_VALUE_I_MSK 0xffff0000
+#define RG_GEMINIA_PHASE_STEP_VALUE_SFT 0
+#define RG_GEMINIA_PHASE_STEP_VALUE_HI 15
+#define RG_GEMINIA_PHASE_STEP_VALUE_SZ 16
+#define RG_GEMINIA_PHASE_MANUAL_MSK 0x00010000
+#define RG_GEMINIA_PHASE_MANUAL_I_MSK 0xfffeffff
+#define RG_GEMINIA_PHASE_MANUAL_SFT 16
+#define RG_GEMINIA_PHASE_MANUAL_HI 16
+#define RG_GEMINIA_PHASE_MANUAL_SZ 1
+#define RG_GEMINIA_ALPHA_SEL_MSK 0x00300000
+#define RG_GEMINIA_ALPHA_SEL_I_MSK 0xffcfffff
+#define RG_GEMINIA_ALPHA_SEL_SFT 20
+#define RG_GEMINIA_ALPHA_SEL_HI 21
+#define RG_GEMINIA_ALPHA_SEL_SZ 2
+#define RG_GEMINIA_SPECTRUM_BW_MSK 0x03000000
+#define RG_GEMINIA_SPECTRUM_BW_I_MSK 0xfcffffff
+#define RG_GEMINIA_SPECTRUM_BW_SFT 24
+#define RG_GEMINIA_SPECTRUM_BW_HI 25
+#define RG_GEMINIA_SPECTRUM_BW_SZ 2
+#define RG_GEMINIA_SPECTRUM_EN_MSK 0x10000000
+#define RG_GEMINIA_SPECTRUM_EN_I_MSK 0xefffffff
+#define RG_GEMINIA_SPECTRUM_EN_SFT 28
+#define RG_GEMINIA_SPECTRUM_EN_HI 28
+#define RG_GEMINIA_SPECTRUM_EN_SZ 1
+#define RG_GEMINIA_RX_RCCAL_TARG_MSK 0x000003ff
+#define RG_GEMINIA_RX_RCCAL_TARG_I_MSK 0xfffffc00
+#define RG_GEMINIA_RX_RCCAL_TARG_SFT 0
+#define RG_GEMINIA_RX_RCCAL_TARG_HI 9
+#define RG_GEMINIA_RX_RCCAL_TARG_SZ 10
+#define RG_GEMINIA_RX_DC_POLAR_INV_MSK 0x00001000
+#define RG_GEMINIA_RX_DC_POLAR_INV_I_MSK 0xffffefff
+#define RG_GEMINIA_RX_DC_POLAR_INV_SFT 12
+#define RG_GEMINIA_RX_DC_POLAR_INV_HI 12
+#define RG_GEMINIA_RX_DC_POLAR_INV_SZ 1
+#define RG_GEMINIA_RCCAL_POLAR_INV_MSK 0x00002000
+#define RG_GEMINIA_RCCAL_POLAR_INV_I_MSK 0xffffdfff
+#define RG_GEMINIA_RCCAL_POLAR_INV_SFT 13
+#define RG_GEMINIA_RCCAL_POLAR_INV_HI 13
+#define RG_GEMINIA_RCCAL_POLAR_INV_SZ 1
+#define RO_GEMINIA_WF_DCCAL_DONE_MSK 0x00010000
+#define RO_GEMINIA_WF_DCCAL_DONE_I_MSK 0xfffeffff
+#define RO_GEMINIA_WF_DCCAL_DONE_SFT 16
+#define RO_GEMINIA_WF_DCCAL_DONE_HI 16
+#define RO_GEMINIA_WF_DCCAL_DONE_SZ 1
+#define RO_GEMINIA_BT_DCCAL_DONE_MSK 0x00020000
+#define RO_GEMINIA_BT_DCCAL_DONE_I_MSK 0xfffdffff
+#define RO_GEMINIA_BT_DCCAL_DONE_SFT 17
+#define RO_GEMINIA_BT_DCCAL_DONE_HI 17
+#define RO_GEMINIA_BT_DCCAL_DONE_SZ 1
+#define RO_GEMINIA_RCCAL_DONE_MSK 0x00040000
+#define RO_GEMINIA_RCCAL_DONE_I_MSK 0xfffbffff
+#define RO_GEMINIA_RCCAL_DONE_SFT 18
+#define RO_GEMINIA_RCCAL_DONE_HI 18
+#define RO_GEMINIA_RCCAL_DONE_SZ 1
+#define RO_GEMINIA_TXDC_DONE_MSK 0x00080000
+#define RO_GEMINIA_TXDC_DONE_I_MSK 0xfff7ffff
+#define RO_GEMINIA_TXDC_DONE_SFT 19
+#define RO_GEMINIA_TXDC_DONE_HI 19
+#define RO_GEMINIA_TXDC_DONE_SZ 1
+#define RO_GEMINIA_TXIQ_DONE_MSK 0x00100000
+#define RO_GEMINIA_TXIQ_DONE_I_MSK 0xffefffff
+#define RO_GEMINIA_TXIQ_DONE_SFT 20
+#define RO_GEMINIA_TXIQ_DONE_HI 20
+#define RO_GEMINIA_TXIQ_DONE_SZ 1
+#define RO_GEMINIA_RXIQ_DONE_MSK 0x00200000
+#define RO_GEMINIA_RXIQ_DONE_I_MSK 0xffdfffff
+#define RO_GEMINIA_RXIQ_DONE_SFT 21
+#define RO_GEMINIA_RXIQ_DONE_HI 21
+#define RO_GEMINIA_RXIQ_DONE_SZ 1
+#define RG_GEMINIA_PHASE_17P5M_MSK 0x0000ffff
+#define RG_GEMINIA_PHASE_17P5M_I_MSK 0xffff0000
+#define RG_GEMINIA_PHASE_17P5M_SFT 0
+#define RG_GEMINIA_PHASE_17P5M_HI 15
+#define RG_GEMINIA_PHASE_17P5M_SZ 16
+#define RG_GEMINIA_PHASE_2P5M_MSK 0xffff0000
+#define RG_GEMINIA_PHASE_2P5M_I_MSK 0x0000ffff
+#define RG_GEMINIA_PHASE_2P5M_SFT 16
+#define RG_GEMINIA_PHASE_2P5M_HI 31
+#define RG_GEMINIA_PHASE_2P5M_SZ 16
+#define RG_GEMINIA_PHASE_RXIQ_1M_MSK 0x0000ffff
+#define RG_GEMINIA_PHASE_RXIQ_1M_I_MSK 0xffff0000
+#define RG_GEMINIA_PHASE_RXIQ_1M_SFT 0
+#define RG_GEMINIA_PHASE_RXIQ_1M_HI 15
+#define RG_GEMINIA_PHASE_RXIQ_1M_SZ 16
+#define RG_GEMINIA_PHASE_1M_MSK 0xffff0000
+#define RG_GEMINIA_PHASE_1M_I_MSK 0x0000ffff
+#define RG_GEMINIA_PHASE_1M_SFT 16
+#define RG_GEMINIA_PHASE_1M_HI 31
+#define RG_GEMINIA_PHASE_1M_SZ 16
+#define RG_GEMINIA_EN_LDO_XO_BYP_MSK 0x00000001
+#define RG_GEMINIA_EN_LDO_XO_BYP_I_MSK 0xfffffffe
+#define RG_GEMINIA_EN_LDO_XO_BYP_SFT 0
+#define RG_GEMINIA_EN_LDO_XO_BYP_HI 0
+#define RG_GEMINIA_EN_LDO_XO_BYP_SZ 1
+#define RG_GEMINIA_EN_LDO_XO_IQUP_MSK 0x00000002
+#define RG_GEMINIA_EN_LDO_XO_IQUP_I_MSK 0xfffffffd
+#define RG_GEMINIA_EN_LDO_XO_IQUP_SFT 1
+#define RG_GEMINIA_EN_LDO_XO_IQUP_HI 1
+#define RG_GEMINIA_EN_LDO_XO_IQUP_SZ 1
+#define RG_GEMINIA_XO_LDO_LEVEL_MSK 0x0000001c
+#define RG_GEMINIA_XO_LDO_LEVEL_I_MSK 0xffffffe3
+#define RG_GEMINIA_XO_LDO_LEVEL_SFT 2
+#define RG_GEMINIA_XO_LDO_LEVEL_HI 4
+#define RG_GEMINIA_XO_LDO_LEVEL_SZ 3
+#define RG_GEMINIA_XO_CBANKI_MSK 0x00001fe0
+#define RG_GEMINIA_XO_CBANKI_I_MSK 0xffffe01f
+#define RG_GEMINIA_XO_CBANKI_SFT 5
+#define RG_GEMINIA_XO_CBANKI_HI 12
+#define RG_GEMINIA_XO_CBANKI_SZ 8
+#define RG_GEMINIA_XO_CBANKO_MSK 0x001fe000
+#define RG_GEMINIA_XO_CBANKO_I_MSK 0xffe01fff
+#define RG_GEMINIA_XO_CBANKO_SFT 13
+#define RG_GEMINIA_XO_CBANKO_HI 20
+#define RG_GEMINIA_XO_CBANKO_SZ 8
+#define RG_GEMINIA_EN_FDB_MSK 0x00200000
+#define RG_GEMINIA_EN_FDB_I_MSK 0xffdfffff
+#define RG_GEMINIA_EN_FDB_SFT 21
+#define RG_GEMINIA_EN_FDB_HI 21
+#define RG_GEMINIA_EN_FDB_SZ 1
+#define RG_GEMINIA_FDB_BYPASS_MSK 0x00400000
+#define RG_GEMINIA_FDB_BYPASS_I_MSK 0xffbfffff
+#define RG_GEMINIA_FDB_BYPASS_SFT 22
+#define RG_GEMINIA_FDB_BYPASS_HI 22
+#define RG_GEMINIA_FDB_BYPASS_SZ 1
+#define RG_GEMINIA_FDB_DUTY_LTH_MSK 0x01800000
+#define RG_GEMINIA_FDB_DUTY_LTH_I_MSK 0xfe7fffff
+#define RG_GEMINIA_FDB_DUTY_LTH_SFT 23
+#define RG_GEMINIA_FDB_DUTY_LTH_HI 24
+#define RG_GEMINIA_FDB_DUTY_LTH_SZ 2
+#define RG_GEMINIA_EN_XOTEST_MSK 0x02000000
+#define RG_GEMINIA_EN_XOTEST_I_MSK 0xfdffffff
+#define RG_GEMINIA_EN_XOTEST_SFT 25
+#define RG_GEMINIA_EN_XOTEST_HI 25
+#define RG_GEMINIA_EN_XOTEST_SZ 1
+#define RG_GEMINIA_EN_FDB_DCC_MUAL_MSK 0x00000001
+#define RG_GEMINIA_EN_FDB_DCC_MUAL_I_MSK 0xfffffffe
+#define RG_GEMINIA_EN_FDB_DCC_MUAL_SFT 0
+#define RG_GEMINIA_EN_FDB_DCC_MUAL_HI 0
+#define RG_GEMINIA_EN_FDB_DCC_MUAL_SZ 1
+#define RG_GEMINIA_EN_FDB_DELAYC_MUAL_MSK 0x00000002
+#define RG_GEMINIA_EN_FDB_DELAYC_MUAL_I_MSK 0xfffffffd
+#define RG_GEMINIA_EN_FDB_DELAYC_MUAL_SFT 1
+#define RG_GEMINIA_EN_FDB_DELAYC_MUAL_HI 1
+#define RG_GEMINIA_EN_FDB_DELAYC_MUAL_SZ 1
+#define RG_GEMINIA_EN_FDB_DELAYF_MUAL_MSK 0x00000004
+#define RG_GEMINIA_EN_FDB_DELAYF_MUAL_I_MSK 0xfffffffb
+#define RG_GEMINIA_EN_FDB_DELAYF_MUAL_SFT 2
+#define RG_GEMINIA_EN_FDB_DELAYF_MUAL_HI 2
+#define RG_GEMINIA_EN_FDB_DELAYF_MUAL_SZ 1
+#define RG_GEMINIA_EN_FDB_PHASESWAP_MUAL_MSK 0x00000008
+#define RG_GEMINIA_EN_FDB_PHASESWAP_MUAL_I_MSK 0xfffffff7
+#define RG_GEMINIA_EN_FDB_PHASESWAP_MUAL_SFT 3
+#define RG_GEMINIA_EN_FDB_PHASESWAP_MUAL_HI 3
+#define RG_GEMINIA_EN_FDB_PHASESWAP_MUAL_SZ 1
+#define RG_GEMINIA_FDB_PHASESWAP_MUAL_MSK 0x00000010
+#define RG_GEMINIA_FDB_PHASESWAP_MUAL_I_MSK 0xffffffef
+#define RG_GEMINIA_FDB_PHASESWAP_MUAL_SFT 4
+#define RG_GEMINIA_FDB_PHASESWAP_MUAL_HI 4
+#define RG_GEMINIA_FDB_PHASESWAP_MUAL_SZ 1
+#define RG_GEMINIA_FDB_CDELAY_MUAL_MSK 0x00000f00
+#define RG_GEMINIA_FDB_CDELAY_MUAL_I_MSK 0xfffff0ff
+#define RG_GEMINIA_FDB_CDELAY_MUAL_SFT 8
+#define RG_GEMINIA_FDB_CDELAY_MUAL_HI 11
+#define RG_GEMINIA_FDB_CDELAY_MUAL_SZ 4
+#define RG_GEMINIA_FDB_FDELAY_MUAL_MSK 0x0000f000
+#define RG_GEMINIA_FDB_FDELAY_MUAL_I_MSK 0xffff0fff
+#define RG_GEMINIA_FDB_FDELAY_MUAL_SFT 12
+#define RG_GEMINIA_FDB_FDELAY_MUAL_HI 15
+#define RG_GEMINIA_FDB_FDELAY_MUAL_SZ 4
+#define RG_GEMINIA_XO_TIMMER_MSK 0x003f0000
+#define RG_GEMINIA_XO_TIMMER_I_MSK 0xffc0ffff
+#define RG_GEMINIA_XO_TIMMER_SFT 16
+#define RG_GEMINIA_XO_TIMMER_HI 21
+#define RG_GEMINIA_XO_TIMMER_SZ 6
+#define RG_GEMINIA_DPL_SETTLING_TIMMER_MSK 0x00c00000
+#define RG_GEMINIA_DPL_SETTLING_TIMMER_I_MSK 0xff3fffff
+#define RG_GEMINIA_DPL_SETTLING_TIMMER_SFT 22
+#define RG_GEMINIA_DPL_SETTLING_TIMMER_HI 23
+#define RG_GEMINIA_DPL_SETTLING_TIMMER_SZ 2
+#define RG_GEMINIA_FDB_RDELAYF_MSK 0x03000000
+#define RG_GEMINIA_FDB_RDELAYF_I_MSK 0xfcffffff
+#define RG_GEMINIA_FDB_RDELAYF_SFT 24
+#define RG_GEMINIA_FDB_RDELAYF_HI 25
+#define RG_GEMINIA_FDB_RDELAYF_SZ 2
+#define RG_GEMINIA_FDB_RDELAYS_MSK 0x0c000000
+#define RG_GEMINIA_FDB_RDELAYS_I_MSK 0xf3ffffff
+#define RG_GEMINIA_FDB_RDELAYS_SFT 26
+#define RG_GEMINIA_FDB_RDELAYS_HI 27
+#define RG_GEMINIA_FDB_RDELAYS_SZ 2
+#define RG_GEMINIA_FDB_RECAL_TIMMER_MSK 0x30000000
+#define RG_GEMINIA_FDB_RECAL_TIMMER_I_MSK 0xcfffffff
+#define RG_GEMINIA_FDB_RECAL_TIMMER_SFT 28
+#define RG_GEMINIA_FDB_RECAL_TIMMER_HI 29
+#define RG_GEMINIA_FDB_RECAL_TIMMER_SZ 2
+#define RG_GEMINIA_EN_FDB_RECAL_MSK 0x40000000
+#define RG_GEMINIA_EN_FDB_RECAL_I_MSK 0xbfffffff
+#define RG_GEMINIA_EN_FDB_RECAL_SFT 30
+#define RG_GEMINIA_EN_FDB_RECAL_HI 30
+#define RG_GEMINIA_EN_FDB_RECAL_SZ 1
+#define RG_GEMINIA_LOAD_RFTABLE_RDY_MSK 0x80000000
+#define RG_GEMINIA_LOAD_RFTABLE_RDY_I_MSK 0x7fffffff
+#define RG_GEMINIA_LOAD_RFTABLE_RDY_SFT 31
+#define RG_GEMINIA_LOAD_RFTABLE_RDY_HI 31
+#define RG_GEMINIA_LOAD_RFTABLE_RDY_SZ 1
+#define RG_GEMINIA_DCDC_MODE_MSK 0x00000001
+#define RG_GEMINIA_DCDC_MODE_I_MSK 0xfffffffe
+#define RG_GEMINIA_DCDC_MODE_SFT 0
+#define RG_GEMINIA_DCDC_MODE_HI 0
+#define RG_GEMINIA_DCDC_MODE_SZ 1
+#define RG_GEMINIA_BUCK_LEVEL_MSK 0x0000000e
+#define RG_GEMINIA_BUCK_LEVEL_I_MSK 0xfffffff1
+#define RG_GEMINIA_BUCK_LEVEL_SFT 1
+#define RG_GEMINIA_BUCK_LEVEL_HI 3
+#define RG_GEMINIA_BUCK_LEVEL_SZ 3
+#define RG_GEMINIA_DLDO_LEVEL_MSK 0x00000070
+#define RG_GEMINIA_DLDO_LEVEL_I_MSK 0xffffff8f
+#define RG_GEMINIA_DLDO_LEVEL_SFT 4
+#define RG_GEMINIA_DLDO_LEVEL_HI 6
+#define RG_GEMINIA_DLDO_LEVEL_SZ 3
+#define RG_GEMINIA_DLDO_BOOST_IQ_MSK 0x00000100
+#define RG_GEMINIA_DLDO_BOOST_IQ_I_MSK 0xfffffeff
+#define RG_GEMINIA_DLDO_BOOST_IQ_SFT 8
+#define RG_GEMINIA_DLDO_BOOST_IQ_HI 8
+#define RG_GEMINIA_DLDO_BOOST_IQ_SZ 1
+#define RG_GEMINIA_BUCK_EN_PSM_MSK 0x00000200
+#define RG_GEMINIA_BUCK_EN_PSM_I_MSK 0xfffffdff
+#define RG_GEMINIA_BUCK_EN_PSM_SFT 9
+#define RG_GEMINIA_BUCK_EN_PSM_HI 9
+#define RG_GEMINIA_BUCK_EN_PSM_SZ 1
+#define RG_GEMINIA_BUCK_PSM_VTH_MSK 0x00000400
+#define RG_GEMINIA_BUCK_PSM_VTH_I_MSK 0xfffffbff
+#define RG_GEMINIA_BUCK_PSM_VTH_SFT 10
+#define RG_GEMINIA_BUCK_PSM_VTH_HI 10
+#define RG_GEMINIA_BUCK_PSM_VTH_SZ 1
+#define RG_GEMINIA_BUCK_VREF_SEL_MSK 0x00000800
+#define RG_GEMINIA_BUCK_VREF_SEL_I_MSK 0xfffff7ff
+#define RG_GEMINIA_BUCK_VREF_SEL_SFT 11
+#define RG_GEMINIA_BUCK_VREF_SEL_HI 11
+#define RG_GEMINIA_BUCK_VREF_SEL_SZ 1
+#define RG_GEMINIA_LDO_LEVEL_EFUSE_MSK 0x00007000
+#define RG_GEMINIA_LDO_LEVEL_EFUSE_I_MSK 0xffff8fff
+#define RG_GEMINIA_LDO_LEVEL_EFUSE_SFT 12
+#define RG_GEMINIA_LDO_LEVEL_EFUSE_HI 14
+#define RG_GEMINIA_LDO_LEVEL_EFUSE_SZ 3
+#define RG_GEMINIA_EN_LDO_EFUSE_MSK 0x00010000
+#define RG_GEMINIA_EN_LDO_EFUSE_I_MSK 0xfffeffff
+#define RG_GEMINIA_EN_LDO_EFUSE_SFT 16
+#define RG_GEMINIA_EN_LDO_EFUSE_HI 16
+#define RG_GEMINIA_EN_LDO_EFUSE_SZ 1
+#define RG_GEMINIA_DCDC_PULLLOW_CON_MSK 0x00040000
+#define RG_GEMINIA_DCDC_PULLLOW_CON_I_MSK 0xfffbffff
+#define RG_GEMINIA_DCDC_PULLLOW_CON_SFT 18
+#define RG_GEMINIA_DCDC_PULLLOW_CON_HI 18
+#define RG_GEMINIA_DCDC_PULLLOW_CON_SZ 1
+#define RG_GEMINIA_DCDC_RES2_CON_MSK 0x00080000
+#define RG_GEMINIA_DCDC_RES2_CON_I_MSK 0xfff7ffff
+#define RG_GEMINIA_DCDC_RES2_CON_SFT 19
+#define RG_GEMINIA_DCDC_RES2_CON_HI 19
+#define RG_GEMINIA_DCDC_RES2_CON_SZ 1
+#define RG_GEMINIA_DCDC_RES_CON_MSK 0x00100000
+#define RG_GEMINIA_DCDC_RES_CON_I_MSK 0xffefffff
+#define RG_GEMINIA_DCDC_RES_CON_SFT 20
+#define RG_GEMINIA_DCDC_RES_CON_HI 20
+#define RG_GEMINIA_DCDC_RES_CON_SZ 1
+#define RG_GEMINIA_RTC_RS1_MSK 0x00200000
+#define RG_GEMINIA_RTC_RS1_I_MSK 0xffdfffff
+#define RG_GEMINIA_RTC_RS1_SFT 21
+#define RG_GEMINIA_RTC_RS1_HI 21
+#define RG_GEMINIA_RTC_RS1_SZ 1
+#define RG_GEMINIA_RTC_RS2_MSK 0x00400000
+#define RG_GEMINIA_RTC_RS2_I_MSK 0xffbfffff
+#define RG_GEMINIA_RTC_RS2_SFT 22
+#define RG_GEMINIA_RTC_RS2_HI 22
+#define RG_GEMINIA_RTC_RS2_SZ 1
+#define RG_GEMINIA_DCDC_CLK_MSK 0x03000000
+#define RG_GEMINIA_DCDC_CLK_I_MSK 0xfcffffff
+#define RG_GEMINIA_DCDC_CLK_SFT 24
+#define RG_GEMINIA_DCDC_CLK_HI 25
+#define RG_GEMINIA_DCDC_CLK_SZ 2
+#define RG_GEMINIA_RTC_OFFSET_MSK 0x000000ff
+#define RG_GEMINIA_RTC_OFFSET_I_MSK 0xffffff00
+#define RG_GEMINIA_RTC_OFFSET_SFT 0
+#define RG_GEMINIA_RTC_OFFSET_HI 7
+#define RG_GEMINIA_RTC_OFFSET_SZ 8
+#define RG_GEMINIA_RTC_CAL_TARGET_COUNT_MSK 0x000fff00
+#define RG_GEMINIA_RTC_CAL_TARGET_COUNT_I_MSK 0xfff000ff
+#define RG_GEMINIA_RTC_CAL_TARGET_COUNT_SFT 8
+#define RG_GEMINIA_RTC_CAL_TARGET_COUNT_HI 19
+#define RG_GEMINIA_RTC_CAL_TARGET_COUNT_SZ 12
+#define RG_GEMINIA_RTC_OSC_RES_SW_MANUAL_MSK 0x3ff00000
+#define RG_GEMINIA_RTC_OSC_RES_SW_MANUAL_I_MSK 0xc00fffff
+#define RG_GEMINIA_RTC_OSC_RES_SW_MANUAL_SFT 20
+#define RG_GEMINIA_RTC_OSC_RES_SW_MANUAL_HI 29
+#define RG_GEMINIA_RTC_OSC_RES_SW_MANUAL_SZ 10
+#define RG_GEMINIA_RTC_CAL_MODE_MSK 0x40000000
+#define RG_GEMINIA_RTC_CAL_MODE_I_MSK 0xbfffffff
+#define RG_GEMINIA_RTC_CAL_MODE_SFT 30
+#define RG_GEMINIA_RTC_CAL_MODE_HI 30
+#define RG_GEMINIA_RTC_CAL_MODE_SZ 1
+#define RG_GEMINIA_SEL_DPLL_CLK_MSK 0x80000000
+#define RG_GEMINIA_SEL_DPLL_CLK_I_MSK 0x7fffffff
+#define RG_GEMINIA_SEL_DPLL_CLK_SFT 31
+#define RG_GEMINIA_SEL_DPLL_CLK_HI 31
+#define RG_GEMINIA_SEL_DPLL_CLK_SZ 1
+#define RG_GEMINIA_RTC_OSC_RES_SW_MANUAL_EN_MSK 0x00000001
+#define RG_GEMINIA_RTC_OSC_RES_SW_MANUAL_EN_I_MSK 0xfffffffe
+#define RG_GEMINIA_RTC_OSC_RES_SW_MANUAL_EN_SFT 0
+#define RG_GEMINIA_RTC_OSC_RES_SW_MANUAL_EN_HI 0
+#define RG_GEMINIA_RTC_OSC_RES_SW_MANUAL_EN_SZ 1
+#define RG_GEMINIA_EN_RTC_CAL_MSK 0x00000002
+#define RG_GEMINIA_EN_RTC_CAL_I_MSK 0xfffffffd
+#define RG_GEMINIA_EN_RTC_CAL_SFT 1
+#define RG_GEMINIA_EN_RTC_CAL_HI 1
+#define RG_GEMINIA_EN_RTC_CAL_SZ 1
+#define RO_GEMINIA_RTC_OSC_RES_SW_MSK 0x03ff0000
+#define RO_GEMINIA_RTC_OSC_RES_SW_I_MSK 0xfc00ffff
+#define RO_GEMINIA_RTC_OSC_RES_SW_SFT 16
+#define RO_GEMINIA_RTC_OSC_RES_SW_HI 25
+#define RO_GEMINIA_RTC_OSC_RES_SW_SZ 10
+#define RO_GEMINIA_RTC_OSC_CAL_RES_RDY_MSK 0x80000000
+#define RO_GEMINIA_RTC_OSC_CAL_RES_RDY_I_MSK 0x7fffffff
+#define RO_GEMINIA_RTC_OSC_CAL_RES_RDY_SFT 31
+#define RO_GEMINIA_RTC_OSC_CAL_RES_RDY_HI 31
+#define RO_GEMINIA_RTC_OSC_CAL_RES_RDY_SZ 1
+#define RG_GEMINIA_BT_CLK_SW_MSK 0x00000001
+#define RG_GEMINIA_BT_CLK_SW_I_MSK 0xfffffffe
+#define RG_GEMINIA_BT_CLK_SW_SFT 0
+#define RG_GEMINIA_BT_CLK_SW_HI 0
+#define RG_GEMINIA_BT_CLK_SW_SZ 1
+#define RG_GEMINIA_BT_CLK32K_CAL_DONE_MSK 0x00000002
+#define RG_GEMINIA_BT_CLK32K_CAL_DONE_I_MSK 0xfffffffd
+#define RG_GEMINIA_BT_CLK32K_CAL_DONE_SFT 1
+#define RG_GEMINIA_BT_CLK32K_CAL_DONE_HI 1
+#define RG_GEMINIA_BT_CLK32K_CAL_DONE_SZ 1
+#define RG_GEMINIA_SLEEP_WAKE_CNT_MSK 0x00ffffff
+#define RG_GEMINIA_SLEEP_WAKE_CNT_I_MSK 0xff000000
+#define RG_GEMINIA_SLEEP_WAKE_CNT_SFT 0
+#define RG_GEMINIA_SLEEP_WAKE_CNT_HI 23
+#define RG_GEMINIA_SLEEP_WAKE_CNT_SZ 24
+#define RG_GEMINIA_PMU_ENTER_SLEEP_MODE_MSK 0x01000000
+#define RG_GEMINIA_PMU_ENTER_SLEEP_MODE_I_MSK 0xfeffffff
+#define RG_GEMINIA_PMU_ENTER_SLEEP_MODE_SFT 24
+#define RG_GEMINIA_PMU_ENTER_SLEEP_MODE_HI 24
+#define RG_GEMINIA_PMU_ENTER_SLEEP_MODE_SZ 1
+#define RG_GEMINIA_RTC_EN_MSK 0x00000001
+#define RG_GEMINIA_RTC_EN_I_MSK 0xfffffffe
+#define RG_GEMINIA_RTC_EN_SFT 0
+#define RG_GEMINIA_RTC_EN_HI 0
+#define RG_GEMINIA_RTC_EN_SZ 1
+#define RG_GEMINIA_CLK_RTC_SW_MSK 0x00000002
+#define RG_GEMINIA_CLK_RTC_SW_I_MSK 0xfffffffd
+#define RG_GEMINIA_CLK_RTC_SW_SFT 1
+#define RG_GEMINIA_CLK_RTC_SW_HI 1
+#define RG_GEMINIA_CLK_RTC_SW_SZ 1
+#define RO_GEMINIA_PMU_WAKE_TRIG_EVENT_MSK 0x00003000
+#define RO_GEMINIA_PMU_WAKE_TRIG_EVENT_I_MSK 0xffffcfff
+#define RO_GEMINIA_PMU_WAKE_TRIG_EVENT_SFT 12
+#define RO_GEMINIA_PMU_WAKE_TRIG_EVENT_HI 13
+#define RO_GEMINIA_PMU_WAKE_TRIG_EVENT_SZ 2
+#define RO_GEMINIA_RTC_TICK_CNT_MSK 0x7fff0000
+#define RO_GEMINIA_RTC_TICK_CNT_I_MSK 0x8000ffff
+#define RO_GEMINIA_RTC_TICK_CNT_SFT 16
+#define RO_GEMINIA_RTC_TICK_CNT_HI 30
+#define RO_GEMINIA_RTC_TICK_CNT_SZ 15
+#define RG_GEMINIA_RTC_INT_SEC_MASK_MSK 0x00000001
+#define RG_GEMINIA_RTC_INT_SEC_MASK_I_MSK 0xfffffffe
+#define RG_GEMINIA_RTC_INT_SEC_MASK_SFT 0
+#define RG_GEMINIA_RTC_INT_SEC_MASK_HI 0
+#define RG_GEMINIA_RTC_INT_SEC_MASK_SZ 1
+#define RG_GEMINIA_RTC_INT_ALARM_MASK_MSK 0x00000002
+#define RG_GEMINIA_RTC_INT_ALARM_MASK_I_MSK 0xfffffffd
+#define RG_GEMINIA_RTC_INT_ALARM_MASK_SFT 1
+#define RG_GEMINIA_RTC_INT_ALARM_MASK_HI 1
+#define RG_GEMINIA_RTC_INT_ALARM_MASK_SZ 1
+#define RO_GEMINIA_RTC_INT_SEC_MSK 0x00010000
+#define RO_GEMINIA_RTC_INT_SEC_I_MSK 0xfffeffff
+#define RO_GEMINIA_RTC_INT_SEC_SFT 16
+#define RO_GEMINIA_RTC_INT_SEC_HI 16
+#define RO_GEMINIA_RTC_INT_SEC_SZ 1
+#define RO_GEMINIA_RTC_INT_ALARM_MSK 0x00020000
+#define RO_GEMINIA_RTC_INT_ALARM_I_MSK 0xfffdffff
+#define RO_GEMINIA_RTC_INT_ALARM_SFT 17
+#define RO_GEMINIA_RTC_INT_ALARM_HI 17
+#define RO_GEMINIA_RTC_INT_ALARM_SZ 1
+#define RG_GEMINIA_RTC_SEC_START_CNT_MSK 0xffffffff
+#define RG_GEMINIA_RTC_SEC_START_CNT_I_MSK 0x00000000
+#define RG_GEMINIA_RTC_SEC_START_CNT_SFT 0
+#define RG_GEMINIA_RTC_SEC_START_CNT_HI 31
+#define RG_GEMINIA_RTC_SEC_START_CNT_SZ 32
+#define RG_GEMINIA_RTC_SEC_ALARM_VALUE_MSK 0xffffffff
+#define RG_GEMINIA_RTC_SEC_ALARM_VALUE_I_MSK 0x00000000
+#define RG_GEMINIA_RTC_SEC_ALARM_VALUE_SFT 0
+#define RG_GEMINIA_RTC_SEC_ALARM_VALUE_HI 31
+#define RG_GEMINIA_RTC_SEC_ALARM_VALUE_SZ 32
+#define RO_GEMINIA_FDB_CDELAY_MSK 0x00f00000
+#define RO_GEMINIA_FDB_CDELAY_I_MSK 0xff0fffff
+#define RO_GEMINIA_FDB_CDELAY_SFT 20
+#define RO_GEMINIA_FDB_CDELAY_HI 23
+#define RO_GEMINIA_FDB_CDELAY_SZ 4
+#define RO_GEMINIA_FDB_FDELAY_MSK 0x0f000000
+#define RO_GEMINIA_FDB_FDELAY_I_MSK 0xf0ffffff
+#define RO_GEMINIA_FDB_FDELAY_SFT 24
+#define RO_GEMINIA_FDB_FDELAY_HI 27
+#define RO_GEMINIA_FDB_FDELAY_SZ 4
+#define RO_GEMINIA_FDB_PHASESWAP_MSK 0x80000000
+#define RO_GEMINIA_FDB_PHASESWAP_I_MSK 0x7fffffff
+#define RO_GEMINIA_FDB_PHASESWAP_SFT 31
+#define RO_GEMINIA_FDB_PHASESWAP_HI 31
+#define RO_GEMINIA_FDB_PHASESWAP_SZ 1
+#define RG_GEMINIA_GPIO16_DS_MSK 0x00000001
+#define RG_GEMINIA_GPIO16_DS_I_MSK 0xfffffffe
+#define RG_GEMINIA_GPIO16_DS_SFT 0
+#define RG_GEMINIA_GPIO16_DS_HI 0
+#define RG_GEMINIA_GPIO16_DS_SZ 1
+#define RG_GEMINIA_GPIO16_PD_MSK 0x00000002
+#define RG_GEMINIA_GPIO16_PD_I_MSK 0xfffffffd
+#define RG_GEMINIA_GPIO16_PD_SFT 1
+#define RG_GEMINIA_GPIO16_PD_HI 1
+#define RG_GEMINIA_GPIO16_PD_SZ 1
+#define RG_GEMINIA_GPIO16_OE_MSK 0x00000004
+#define RG_GEMINIA_GPIO16_OE_I_MSK 0xfffffffb
+#define RG_GEMINIA_GPIO16_OE_SFT 2
+#define RG_GEMINIA_GPIO16_OE_HI 2
+#define RG_GEMINIA_GPIO16_OE_SZ 1
+#define RG_GEMINIA_GPIO17_DS_MSK 0x00000010
+#define RG_GEMINIA_GPIO17_DS_I_MSK 0xffffffef
+#define RG_GEMINIA_GPIO17_DS_SFT 4
+#define RG_GEMINIA_GPIO17_DS_HI 4
+#define RG_GEMINIA_GPIO17_DS_SZ 1
+#define RG_GEMINIA_GPIO17_PD_MSK 0x00000020
+#define RG_GEMINIA_GPIO17_PD_I_MSK 0xffffffdf
+#define RG_GEMINIA_GPIO17_PD_SFT 5
+#define RG_GEMINIA_GPIO17_PD_HI 5
+#define RG_GEMINIA_GPIO17_PD_SZ 1
+#define RG_GEMINIA_GPIO17_OE_MSK 0x00000040
+#define RG_GEMINIA_GPIO17_OE_I_MSK 0xffffffbf
+#define RG_GEMINIA_GPIO17_OE_SFT 6
+#define RG_GEMINIA_GPIO17_OE_HI 6
+#define RG_GEMINIA_GPIO17_OE_SZ 1
+#define RG_GEMINIA_GPIO18_DS_MSK 0x00000100
+#define RG_GEMINIA_GPIO18_DS_I_MSK 0xfffffeff
+#define RG_GEMINIA_GPIO18_DS_SFT 8
+#define RG_GEMINIA_GPIO18_DS_HI 8
+#define RG_GEMINIA_GPIO18_DS_SZ 1
+#define RG_GEMINIA_GPIO18_PD_MSK 0x00000200
+#define RG_GEMINIA_GPIO18_PD_I_MSK 0xfffffdff
+#define RG_GEMINIA_GPIO18_PD_SFT 9
+#define RG_GEMINIA_GPIO18_PD_HI 9
+#define RG_GEMINIA_GPIO18_PD_SZ 1
+#define RG_GEMINIA_GPIO18_OE_MSK 0x00000400
+#define RG_GEMINIA_GPIO18_OE_I_MSK 0xfffffbff
+#define RG_GEMINIA_GPIO18_OE_SFT 10
+#define RG_GEMINIA_GPIO18_OE_HI 10
+#define RG_GEMINIA_GPIO18_OE_SZ 1
+#define RG_GEMINIA_GPIO19_DS_MSK 0x00001000
+#define RG_GEMINIA_GPIO19_DS_I_MSK 0xffffefff
+#define RG_GEMINIA_GPIO19_DS_SFT 12
+#define RG_GEMINIA_GPIO19_DS_HI 12
+#define RG_GEMINIA_GPIO19_DS_SZ 1
+#define RG_GEMINIA_GPIO19_PD_MSK 0x00002000
+#define RG_GEMINIA_GPIO19_PD_I_MSK 0xffffdfff
+#define RG_GEMINIA_GPIO19_PD_SFT 13
+#define RG_GEMINIA_GPIO19_PD_HI 13
+#define RG_GEMINIA_GPIO19_PD_SZ 1
+#define RG_GEMINIA_GPIO19_OE_MSK 0x00004000
+#define RG_GEMINIA_GPIO19_OE_I_MSK 0xffffbfff
+#define RG_GEMINIA_GPIO19_OE_SFT 14
+#define RG_GEMINIA_GPIO19_OE_HI 14
+#define RG_GEMINIA_GPIO19_OE_SZ 1
+#define RG_GEMINIA_GPIO20_DS_MSK 0x00010000
+#define RG_GEMINIA_GPIO20_DS_I_MSK 0xfffeffff
+#define RG_GEMINIA_GPIO20_DS_SFT 16
+#define RG_GEMINIA_GPIO20_DS_HI 16
+#define RG_GEMINIA_GPIO20_DS_SZ 1
+#define RG_GEMINIA_GPIO20_PD_MSK 0x00020000
+#define RG_GEMINIA_GPIO20_PD_I_MSK 0xfffdffff
+#define RG_GEMINIA_GPIO20_PD_SFT 17
+#define RG_GEMINIA_GPIO20_PD_HI 17
+#define RG_GEMINIA_GPIO20_PD_SZ 1
+#define RG_GEMINIA_GPIO20_OE_MSK 0x00040000
+#define RG_GEMINIA_GPIO20_OE_I_MSK 0xfffbffff
+#define RG_GEMINIA_GPIO20_OE_SFT 18
+#define RG_GEMINIA_GPIO20_OE_HI 18
+#define RG_GEMINIA_GPIO20_OE_SZ 1
+#define RG_GEMINIA_SPIS_MISO_DS_MSK 0x01000000
+#define RG_GEMINIA_SPIS_MISO_DS_I_MSK 0xfeffffff
+#define RG_GEMINIA_SPIS_MISO_DS_SFT 24
+#define RG_GEMINIA_SPIS_MISO_DS_HI 24
+#define RG_GEMINIA_SPIS_MISO_DS_SZ 1
+#define RG_GEMINIA_FPGA_CLK_REF_40M_DS_MSK 0x10000000
+#define RG_GEMINIA_FPGA_CLK_REF_40M_DS_I_MSK 0xefffffff
+#define RG_GEMINIA_FPGA_CLK_REF_40M_DS_SFT 28
+#define RG_GEMINIA_FPGA_CLK_REF_40M_DS_HI 28
+#define RG_GEMINIA_FPGA_CLK_REF_40M_DS_SZ 1
+#define RG_GEMINIA_FPGA_CLK_REF_40M_PD_MSK 0x20000000
+#define RG_GEMINIA_FPGA_CLK_REF_40M_PD_I_MSK 0xdfffffff
+#define RG_GEMINIA_FPGA_CLK_REF_40M_PD_SFT 29
+#define RG_GEMINIA_FPGA_CLK_REF_40M_PD_HI 29
+#define RG_GEMINIA_FPGA_CLK_REF_40M_PD_SZ 1
+#define RG_GEMINIA_FPGA_CLK_REF_40M_OE_MSK 0x40000000
+#define RG_GEMINIA_FPGA_CLK_REF_40M_OE_I_MSK 0xbfffffff
+#define RG_GEMINIA_FPGA_CLK_REF_40M_OE_SFT 30
+#define RG_GEMINIA_FPGA_CLK_REF_40M_OE_HI 30
+#define RG_GEMINIA_FPGA_CLK_REF_40M_OE_SZ 1
+#define RG_GEMINIA_GPIO08_DS_MSK 0x00000001
+#define RG_GEMINIA_GPIO08_DS_I_MSK 0xfffffffe
+#define RG_GEMINIA_GPIO08_DS_SFT 0
+#define RG_GEMINIA_GPIO08_DS_HI 0
+#define RG_GEMINIA_GPIO08_DS_SZ 1
+#define RG_GEMINIA_GPIO08_PD_MSK 0x00000002
+#define RG_GEMINIA_GPIO08_PD_I_MSK 0xfffffffd
+#define RG_GEMINIA_GPIO08_PD_SFT 1
+#define RG_GEMINIA_GPIO08_PD_HI 1
+#define RG_GEMINIA_GPIO08_PD_SZ 1
+#define RG_GEMINIA_GPIO08_OE_MSK 0x00000004
+#define RG_GEMINIA_GPIO08_OE_I_MSK 0xfffffffb
+#define RG_GEMINIA_GPIO08_OE_SFT 2
+#define RG_GEMINIA_GPIO08_OE_HI 2
+#define RG_GEMINIA_GPIO08_OE_SZ 1
+#define RG_GEMINIA_GPIO09_DS_MSK 0x00000010
+#define RG_GEMINIA_GPIO09_DS_I_MSK 0xffffffef
+#define RG_GEMINIA_GPIO09_DS_SFT 4
+#define RG_GEMINIA_GPIO09_DS_HI 4
+#define RG_GEMINIA_GPIO09_DS_SZ 1
+#define RG_GEMINIA_GPIO09_PD_MSK 0x00000020
+#define RG_GEMINIA_GPIO09_PD_I_MSK 0xffffffdf
+#define RG_GEMINIA_GPIO09_PD_SFT 5
+#define RG_GEMINIA_GPIO09_PD_HI 5
+#define RG_GEMINIA_GPIO09_PD_SZ 1
+#define RG_GEMINIA_GPIO09_OE_MSK 0x00000040
+#define RG_GEMINIA_GPIO09_OE_I_MSK 0xffffffbf
+#define RG_GEMINIA_GPIO09_OE_SFT 6
+#define RG_GEMINIA_GPIO09_OE_HI 6
+#define RG_GEMINIA_GPIO09_OE_SZ 1
+#define RG_GEMINIA_GPIO10_DS_MSK 0x00000100
+#define RG_GEMINIA_GPIO10_DS_I_MSK 0xfffffeff
+#define RG_GEMINIA_GPIO10_DS_SFT 8
+#define RG_GEMINIA_GPIO10_DS_HI 8
+#define RG_GEMINIA_GPIO10_DS_SZ 1
+#define RG_GEMINIA_GPIO10_PD_MSK 0x00000200
+#define RG_GEMINIA_GPIO10_PD_I_MSK 0xfffffdff
+#define RG_GEMINIA_GPIO10_PD_SFT 9
+#define RG_GEMINIA_GPIO10_PD_HI 9
+#define RG_GEMINIA_GPIO10_PD_SZ 1
+#define RG_GEMINIA_GPIO10_OE_MSK 0x00000400
+#define RG_GEMINIA_GPIO10_OE_I_MSK 0xfffffbff
+#define RG_GEMINIA_GPIO10_OE_SFT 10
+#define RG_GEMINIA_GPIO10_OE_HI 10
+#define RG_GEMINIA_GPIO10_OE_SZ 1
+#define RG_GEMINIA_GPIO11_DS_MSK 0x00001000
+#define RG_GEMINIA_GPIO11_DS_I_MSK 0xffffefff
+#define RG_GEMINIA_GPIO11_DS_SFT 12
+#define RG_GEMINIA_GPIO11_DS_HI 12
+#define RG_GEMINIA_GPIO11_DS_SZ 1
+#define RG_GEMINIA_GPIO11_PD_MSK 0x00002000
+#define RG_GEMINIA_GPIO11_PD_I_MSK 0xffffdfff
+#define RG_GEMINIA_GPIO11_PD_SFT 13
+#define RG_GEMINIA_GPIO11_PD_HI 13
+#define RG_GEMINIA_GPIO11_PD_SZ 1
+#define RG_GEMINIA_GPIO11_OE_MSK 0x00004000
+#define RG_GEMINIA_GPIO11_OE_I_MSK 0xffffbfff
+#define RG_GEMINIA_GPIO11_OE_SFT 14
+#define RG_GEMINIA_GPIO11_OE_HI 14
+#define RG_GEMINIA_GPIO11_OE_SZ 1
+#define RG_GEMINIA_GPIO12_DS_MSK 0x00010000
+#define RG_GEMINIA_GPIO12_DS_I_MSK 0xfffeffff
+#define RG_GEMINIA_GPIO12_DS_SFT 16
+#define RG_GEMINIA_GPIO12_DS_HI 16
+#define RG_GEMINIA_GPIO12_DS_SZ 1
+#define RG_GEMINIA_GPIO12_PD_MSK 0x00020000
+#define RG_GEMINIA_GPIO12_PD_I_MSK 0xfffdffff
+#define RG_GEMINIA_GPIO12_PD_SFT 17
+#define RG_GEMINIA_GPIO12_PD_HI 17
+#define RG_GEMINIA_GPIO12_PD_SZ 1
+#define RG_GEMINIA_GPIO12_OE_MSK 0x00040000
+#define RG_GEMINIA_GPIO12_OE_I_MSK 0xfffbffff
+#define RG_GEMINIA_GPIO12_OE_SFT 18
+#define RG_GEMINIA_GPIO12_OE_HI 18
+#define RG_GEMINIA_GPIO12_OE_SZ 1
+#define RG_GEMINIA_GPIO13_DS_MSK 0x00100000
+#define RG_GEMINIA_GPIO13_DS_I_MSK 0xffefffff
+#define RG_GEMINIA_GPIO13_DS_SFT 20
+#define RG_GEMINIA_GPIO13_DS_HI 20
+#define RG_GEMINIA_GPIO13_DS_SZ 1
+#define RG_GEMINIA_GPIO13_PD_MSK 0x00200000
+#define RG_GEMINIA_GPIO13_PD_I_MSK 0xffdfffff
+#define RG_GEMINIA_GPIO13_PD_SFT 21
+#define RG_GEMINIA_GPIO13_PD_HI 21
+#define RG_GEMINIA_GPIO13_PD_SZ 1
+#define RG_GEMINIA_GPIO13_OE_MSK 0x00400000
+#define RG_GEMINIA_GPIO13_OE_I_MSK 0xffbfffff
+#define RG_GEMINIA_GPIO13_OE_SFT 22
+#define RG_GEMINIA_GPIO13_OE_HI 22
+#define RG_GEMINIA_GPIO13_OE_SZ 1
+#define RG_GEMINIA_GPIO14_DS_MSK 0x01000000
+#define RG_GEMINIA_GPIO14_DS_I_MSK 0xfeffffff
+#define RG_GEMINIA_GPIO14_DS_SFT 24
+#define RG_GEMINIA_GPIO14_DS_HI 24
+#define RG_GEMINIA_GPIO14_DS_SZ 1
+#define RG_GEMINIA_GPIO14_PD_MSK 0x02000000
+#define RG_GEMINIA_GPIO14_PD_I_MSK 0xfdffffff
+#define RG_GEMINIA_GPIO14_PD_SFT 25
+#define RG_GEMINIA_GPIO14_PD_HI 25
+#define RG_GEMINIA_GPIO14_PD_SZ 1
+#define RG_GEMINIA_GPIO14_OE_MSK 0x04000000
+#define RG_GEMINIA_GPIO14_OE_I_MSK 0xfbffffff
+#define RG_GEMINIA_GPIO14_OE_SFT 26
+#define RG_GEMINIA_GPIO14_OE_HI 26
+#define RG_GEMINIA_GPIO14_OE_SZ 1
+#define RG_GEMINIA_GPIO15_DS_MSK 0x10000000
+#define RG_GEMINIA_GPIO15_DS_I_MSK 0xefffffff
+#define RG_GEMINIA_GPIO15_DS_SFT 28
+#define RG_GEMINIA_GPIO15_DS_HI 28
+#define RG_GEMINIA_GPIO15_DS_SZ 1
+#define RG_GEMINIA_GPIO15_PD_MSK 0x20000000
+#define RG_GEMINIA_GPIO15_PD_I_MSK 0xdfffffff
+#define RG_GEMINIA_GPIO15_PD_SFT 29
+#define RG_GEMINIA_GPIO15_PD_HI 29
+#define RG_GEMINIA_GPIO15_PD_SZ 1
+#define RG_GEMINIA_GPIO15_OE_MSK 0x40000000
+#define RG_GEMINIA_GPIO15_OE_I_MSK 0xbfffffff
+#define RG_GEMINIA_GPIO15_OE_SFT 30
+#define RG_GEMINIA_GPIO15_OE_HI 30
+#define RG_GEMINIA_GPIO15_OE_SZ 1
+#define RG_GEMINIA_GPIO00_DS_MSK 0x00000001
+#define RG_GEMINIA_GPIO00_DS_I_MSK 0xfffffffe
+#define RG_GEMINIA_GPIO00_DS_SFT 0
+#define RG_GEMINIA_GPIO00_DS_HI 0
+#define RG_GEMINIA_GPIO00_DS_SZ 1
+#define RG_GEMINIA_GPIO00_PD_MSK 0x00000002
+#define RG_GEMINIA_GPIO00_PD_I_MSK 0xfffffffd
+#define RG_GEMINIA_GPIO00_PD_SFT 1
+#define RG_GEMINIA_GPIO00_PD_HI 1
+#define RG_GEMINIA_GPIO00_PD_SZ 1
+#define RG_GEMINIA_GPIO00_OE_MSK 0x00000004
+#define RG_GEMINIA_GPIO00_OE_I_MSK 0xfffffffb
+#define RG_GEMINIA_GPIO00_OE_SFT 2
+#define RG_GEMINIA_GPIO00_OE_HI 2
+#define RG_GEMINIA_GPIO00_OE_SZ 1
+#define RG_GEMINIA_GPIO01_DS_MSK 0x00000010
+#define RG_GEMINIA_GPIO01_DS_I_MSK 0xffffffef
+#define RG_GEMINIA_GPIO01_DS_SFT 4
+#define RG_GEMINIA_GPIO01_DS_HI 4
+#define RG_GEMINIA_GPIO01_DS_SZ 1
+#define RG_GEMINIA_GPIO01_PD_MSK 0x00000020
+#define RG_GEMINIA_GPIO01_PD_I_MSK 0xffffffdf
+#define RG_GEMINIA_GPIO01_PD_SFT 5
+#define RG_GEMINIA_GPIO01_PD_HI 5
+#define RG_GEMINIA_GPIO01_PD_SZ 1
+#define RG_GEMINIA_GPIO01_OE_MSK 0x00000040
+#define RG_GEMINIA_GPIO01_OE_I_MSK 0xffffffbf
+#define RG_GEMINIA_GPIO01_OE_SFT 6
+#define RG_GEMINIA_GPIO01_OE_HI 6
+#define RG_GEMINIA_GPIO01_OE_SZ 1
+#define RG_GEMINIA_GPIO02_DS_MSK 0x00000100
+#define RG_GEMINIA_GPIO02_DS_I_MSK 0xfffffeff
+#define RG_GEMINIA_GPIO02_DS_SFT 8
+#define RG_GEMINIA_GPIO02_DS_HI 8
+#define RG_GEMINIA_GPIO02_DS_SZ 1
+#define RG_GEMINIA_GPIO02_PD_MSK 0x00000200
+#define RG_GEMINIA_GPIO02_PD_I_MSK 0xfffffdff
+#define RG_GEMINIA_GPIO02_PD_SFT 9
+#define RG_GEMINIA_GPIO02_PD_HI 9
+#define RG_GEMINIA_GPIO02_PD_SZ 1
+#define RG_GEMINIA_GPIO02_OE_MSK 0x00000400
+#define RG_GEMINIA_GPIO02_OE_I_MSK 0xfffffbff
+#define RG_GEMINIA_GPIO02_OE_SFT 10
+#define RG_GEMINIA_GPIO02_OE_HI 10
+#define RG_GEMINIA_GPIO02_OE_SZ 1
+#define RG_GEMINIA_GPIO03_DS_MSK 0x00001000
+#define RG_GEMINIA_GPIO03_DS_I_MSK 0xffffefff
+#define RG_GEMINIA_GPIO03_DS_SFT 12
+#define RG_GEMINIA_GPIO03_DS_HI 12
+#define RG_GEMINIA_GPIO03_DS_SZ 1
+#define RG_GEMINIA_GPIO03_PD_MSK 0x00002000
+#define RG_GEMINIA_GPIO03_PD_I_MSK 0xffffdfff
+#define RG_GEMINIA_GPIO03_PD_SFT 13
+#define RG_GEMINIA_GPIO03_PD_HI 13
+#define RG_GEMINIA_GPIO03_PD_SZ 1
+#define RG_GEMINIA_GPIO03_OE_MSK 0x00004000
+#define RG_GEMINIA_GPIO03_OE_I_MSK 0xffffbfff
+#define RG_GEMINIA_GPIO03_OE_SFT 14
+#define RG_GEMINIA_GPIO03_OE_HI 14
+#define RG_GEMINIA_GPIO03_OE_SZ 1
+#define RG_GEMINIA_GPIO04_DS_MSK 0x00010000
+#define RG_GEMINIA_GPIO04_DS_I_MSK 0xfffeffff
+#define RG_GEMINIA_GPIO04_DS_SFT 16
+#define RG_GEMINIA_GPIO04_DS_HI 16
+#define RG_GEMINIA_GPIO04_DS_SZ 1
+#define RG_GEMINIA_GPIO04_PD_MSK 0x00020000
+#define RG_GEMINIA_GPIO04_PD_I_MSK 0xfffdffff
+#define RG_GEMINIA_GPIO04_PD_SFT 17
+#define RG_GEMINIA_GPIO04_PD_HI 17
+#define RG_GEMINIA_GPIO04_PD_SZ 1
+#define RG_GEMINIA_GPIO04_OE_MSK 0x00040000
+#define RG_GEMINIA_GPIO04_OE_I_MSK 0xfffbffff
+#define RG_GEMINIA_GPIO04_OE_SFT 18
+#define RG_GEMINIA_GPIO04_OE_HI 18
+#define RG_GEMINIA_GPIO04_OE_SZ 1
+#define RG_GEMINIA_GPIO05_DS_MSK 0x00100000
+#define RG_GEMINIA_GPIO05_DS_I_MSK 0xffefffff
+#define RG_GEMINIA_GPIO05_DS_SFT 20
+#define RG_GEMINIA_GPIO05_DS_HI 20
+#define RG_GEMINIA_GPIO05_DS_SZ 1
+#define RG_GEMINIA_GPIO05_PD_MSK 0x00200000
+#define RG_GEMINIA_GPIO05_PD_I_MSK 0xffdfffff
+#define RG_GEMINIA_GPIO05_PD_SFT 21
+#define RG_GEMINIA_GPIO05_PD_HI 21
+#define RG_GEMINIA_GPIO05_PD_SZ 1
+#define RG_GEMINIA_GPIO05_OE_MSK 0x00400000
+#define RG_GEMINIA_GPIO05_OE_I_MSK 0xffbfffff
+#define RG_GEMINIA_GPIO05_OE_SFT 22
+#define RG_GEMINIA_GPIO05_OE_HI 22
+#define RG_GEMINIA_GPIO05_OE_SZ 1
+#define RG_GEMINIA_GPIO06_DS_MSK 0x01000000
+#define RG_GEMINIA_GPIO06_DS_I_MSK 0xfeffffff
+#define RG_GEMINIA_GPIO06_DS_SFT 24
+#define RG_GEMINIA_GPIO06_DS_HI 24
+#define RG_GEMINIA_GPIO06_DS_SZ 1
+#define RG_GEMINIA_GPIO06_PD_MSK 0x02000000
+#define RG_GEMINIA_GPIO06_PD_I_MSK 0xfdffffff
+#define RG_GEMINIA_GPIO06_PD_SFT 25
+#define RG_GEMINIA_GPIO06_PD_HI 25
+#define RG_GEMINIA_GPIO06_PD_SZ 1
+#define RG_GEMINIA_GPIO06_OE_MSK 0x04000000
+#define RG_GEMINIA_GPIO06_OE_I_MSK 0xfbffffff
+#define RG_GEMINIA_GPIO06_OE_SFT 26
+#define RG_GEMINIA_GPIO06_OE_HI 26
+#define RG_GEMINIA_GPIO06_OE_SZ 1
+#define RG_GEMINIA_GPIO07_DS_MSK 0x10000000
+#define RG_GEMINIA_GPIO07_DS_I_MSK 0xefffffff
+#define RG_GEMINIA_GPIO07_DS_SFT 28
+#define RG_GEMINIA_GPIO07_DS_HI 28
+#define RG_GEMINIA_GPIO07_DS_SZ 1
+#define RG_GEMINIA_GPIO07_PD_MSK 0x20000000
+#define RG_GEMINIA_GPIO07_PD_I_MSK 0xdfffffff
+#define RG_GEMINIA_GPIO07_PD_SFT 29
+#define RG_GEMINIA_GPIO07_PD_HI 29
+#define RG_GEMINIA_GPIO07_PD_SZ 1
+#define RG_GEMINIA_GPIO07_OE_MSK 0x40000000
+#define RG_GEMINIA_GPIO07_OE_I_MSK 0xbfffffff
+#define RG_GEMINIA_GPIO07_OE_SFT 30
+#define RG_GEMINIA_GPIO07_OE_HI 30
+#define RG_GEMINIA_GPIO07_OE_SZ 1
+#define RG_GEMINIA_RF_PHY_MODE_SEL_MSK 0x00000003
+#define RG_GEMINIA_RF_PHY_MODE_SEL_I_MSK 0xfffffffc
+#define RG_GEMINIA_RF_PHY_MODE_SEL_SFT 0
+#define RG_GEMINIA_RF_PHY_MODE_SEL_HI 1
+#define RG_GEMINIA_RF_PHY_MODE_SEL_SZ 2
+#define RG_GEMINIA_RF_PHY_MODE_WIFI_MAC_MSK 0x00000070
+#define RG_GEMINIA_RF_PHY_MODE_WIFI_MAC_I_MSK 0xffffff8f
+#define RG_GEMINIA_RF_PHY_MODE_WIFI_MAC_SFT 4
+#define RG_GEMINIA_RF_PHY_MODE_WIFI_MAC_HI 6
+#define RG_GEMINIA_RF_PHY_MODE_WIFI_MAC_SZ 3
+#define RG_GEMINIA_PAD_MUX_SEL_MSK 0x00000f00
+#define RG_GEMINIA_PAD_MUX_SEL_I_MSK 0xfffff0ff
+#define RG_GEMINIA_PAD_MUX_SEL_SFT 8
+#define RG_GEMINIA_PAD_MUX_SEL_HI 11
+#define RG_GEMINIA_PAD_MUX_SEL_SZ 4
+#define RG_GEMINIA_MODE_LATCH_LMT_MSK 0x00007000
+#define RG_GEMINIA_MODE_LATCH_LMT_I_MSK 0xffff8fff
+#define RG_GEMINIA_MODE_LATCH_LMT_SFT 12
+#define RG_GEMINIA_MODE_LATCH_LMT_HI 14
+#define RG_GEMINIA_MODE_LATCH_LMT_SZ 3
+#define RG_GEMINIA_EXT_MCU_PWRUP_MSK 0x80000000
+#define RG_GEMINIA_EXT_MCU_PWRUP_I_MSK 0x7fffffff
+#define RG_GEMINIA_EXT_MCU_PWRUP_SFT 31
+#define RG_GEMINIA_EXT_MCU_PWRUP_HI 31
+#define RG_GEMINIA_EXT_MCU_PWRUP_SZ 1
+#define RG_GEMINIA_RAM_00_MSK 0xffffffff
+#define RG_GEMINIA_RAM_00_I_MSK 0x00000000
+#define RG_GEMINIA_RAM_00_SFT 0
+#define RG_GEMINIA_RAM_00_HI 31
+#define RG_GEMINIA_RAM_00_SZ 32
+#define RG_GEMINIA_RAM_01_MSK 0xffffffff
+#define RG_GEMINIA_RAM_01_I_MSK 0x00000000
+#define RG_GEMINIA_RAM_01_SFT 0
+#define RG_GEMINIA_RAM_01_HI 31
+#define RG_GEMINIA_RAM_01_SZ 32
+#define RG_GEMINIA_RAM_02_MSK 0xffffffff
+#define RG_GEMINIA_RAM_02_I_MSK 0x00000000
+#define RG_GEMINIA_RAM_02_SFT 0
+#define RG_GEMINIA_RAM_02_HI 31
+#define RG_GEMINIA_RAM_02_SZ 32
+#define RG_GEMINIA_RAM_03_MSK 0xffffffff
+#define RG_GEMINIA_RAM_03_I_MSK 0x00000000
+#define RG_GEMINIA_RAM_03_SFT 0
+#define RG_GEMINIA_RAM_03_HI 31
+#define RG_GEMINIA_RAM_03_SZ 32
+#define RG_GEMINIA_RAM_04_MSK 0xffffffff
+#define RG_GEMINIA_RAM_04_I_MSK 0x00000000
+#define RG_GEMINIA_RAM_04_SFT 0
+#define RG_GEMINIA_RAM_04_HI 31
+#define RG_GEMINIA_RAM_04_SZ 32
+#define RG_GEMINIA_RAM_05_MSK 0xffffffff
+#define RG_GEMINIA_RAM_05_I_MSK 0x00000000
+#define RG_GEMINIA_RAM_05_SFT 0
+#define RG_GEMINIA_RAM_05_HI 31
+#define RG_GEMINIA_RAM_05_SZ 32
+#define RG_GEMINIA_RAM_06_MSK 0xffffffff
+#define RG_GEMINIA_RAM_06_I_MSK 0x00000000
+#define RG_GEMINIA_RAM_06_SFT 0
+#define RG_GEMINIA_RAM_06_HI 31
+#define RG_GEMINIA_RAM_06_SZ 32
+#define RG_GEMINIA_RAM_07_MSK 0xffffffff
+#define RG_GEMINIA_RAM_07_I_MSK 0x00000000
+#define RG_GEMINIA_RAM_07_SFT 0
+#define RG_GEMINIA_RAM_07_HI 31
+#define RG_GEMINIA_RAM_07_SZ 32
+#define RG_GEMINIA_RAM_08_MSK 0xffffffff
+#define RG_GEMINIA_RAM_08_I_MSK 0x00000000
+#define RG_GEMINIA_RAM_08_SFT 0
+#define RG_GEMINIA_RAM_08_HI 31
+#define RG_GEMINIA_RAM_08_SZ 32
+#define RG_GEMINIA_RAM_09_MSK 0xffffffff
+#define RG_GEMINIA_RAM_09_I_MSK 0x00000000
+#define RG_GEMINIA_RAM_09_SFT 0
+#define RG_GEMINIA_RAM_09_HI 31
+#define RG_GEMINIA_RAM_09_SZ 32
+#define RG_GEMINIA_RAM_10_MSK 0xffffffff
+#define RG_GEMINIA_RAM_10_I_MSK 0x00000000
+#define RG_GEMINIA_RAM_10_SFT 0
+#define RG_GEMINIA_RAM_10_HI 31
+#define RG_GEMINIA_RAM_10_SZ 32
+#define RG_GEMINIA_RAM_11_MSK 0xffffffff
+#define RG_GEMINIA_RAM_11_I_MSK 0x00000000
+#define RG_GEMINIA_RAM_11_SFT 0
+#define RG_GEMINIA_RAM_11_HI 31
+#define RG_GEMINIA_RAM_11_SZ 32
+#define RG_GEMINIA_RAM_12_MSK 0xffffffff
+#define RG_GEMINIA_RAM_12_I_MSK 0x00000000
+#define RG_GEMINIA_RAM_12_SFT 0
+#define RG_GEMINIA_RAM_12_HI 31
+#define RG_GEMINIA_RAM_12_SZ 32
+#define RG_GEMINIA_RAM_13_MSK 0xffffffff
+#define RG_GEMINIA_RAM_13_I_MSK 0x00000000
+#define RG_GEMINIA_RAM_13_SFT 0
+#define RG_GEMINIA_RAM_13_HI 31
+#define RG_GEMINIA_RAM_13_SZ 32
+#define RG_GEMINIA_RAM_14_MSK 0xffffffff
+#define RG_GEMINIA_RAM_14_I_MSK 0x00000000
+#define RG_GEMINIA_RAM_14_SFT 0
+#define RG_GEMINIA_RAM_14_HI 31
+#define RG_GEMINIA_RAM_14_SZ 32
+#define RG_GEMINIA_RAM_15_MSK 0xffffffff
+#define RG_GEMINIA_RAM_15_I_MSK 0x00000000
+#define RG_GEMINIA_RAM_15_SFT 0
+#define RG_GEMINIA_RAM_15_HI 31
+#define RG_GEMINIA_RAM_15_SZ 32
+#define RG_GEMINIA_RAM_16_MSK 0xffffffff
+#define RG_GEMINIA_RAM_16_I_MSK 0x00000000
+#define RG_GEMINIA_RAM_16_SFT 0
+#define RG_GEMINIA_RAM_16_HI 31
+#define RG_GEMINIA_RAM_16_SZ 32
+#define RG_GEMINIA_RAM_17_MSK 0xffffffff
+#define RG_GEMINIA_RAM_17_I_MSK 0x00000000
+#define RG_GEMINIA_RAM_17_SFT 0
+#define RG_GEMINIA_RAM_17_HI 31
+#define RG_GEMINIA_RAM_17_SZ 32
+#define RG_GEMINIA_RAM_18_MSK 0xffffffff
+#define RG_GEMINIA_RAM_18_I_MSK 0x00000000
+#define RG_GEMINIA_RAM_18_SFT 0
+#define RG_GEMINIA_RAM_18_HI 31
+#define RG_GEMINIA_RAM_18_SZ 32
+#define RG_GEMINIA_RAM_19_MSK 0xffffffff
+#define RG_GEMINIA_RAM_19_I_MSK 0x00000000
+#define RG_GEMINIA_RAM_19_SFT 0
+#define RG_GEMINIA_RAM_19_HI 31
+#define RG_GEMINIA_RAM_19_SZ 32
+#define RG_GEMINIA_RAM_20_MSK 0xffffffff
+#define RG_GEMINIA_RAM_20_I_MSK 0x00000000
+#define RG_GEMINIA_RAM_20_SFT 0
+#define RG_GEMINIA_RAM_20_HI 31
+#define RG_GEMINIA_RAM_20_SZ 32
+#define RG_GEMINIA_RAM_21_MSK 0xffffffff
+#define RG_GEMINIA_RAM_21_I_MSK 0x00000000
+#define RG_GEMINIA_RAM_21_SFT 0
+#define RG_GEMINIA_RAM_21_HI 31
+#define RG_GEMINIA_RAM_21_SZ 32
+#define RG_GEMINIA_RAM_22_MSK 0xffffffff
+#define RG_GEMINIA_RAM_22_I_MSK 0x00000000
+#define RG_GEMINIA_RAM_22_SFT 0
+#define RG_GEMINIA_RAM_22_HI 31
+#define RG_GEMINIA_RAM_22_SZ 32
+#define RG_GEMINIA_RAM_23_MSK 0xffffffff
+#define RG_GEMINIA_RAM_23_I_MSK 0x00000000
+#define RG_GEMINIA_RAM_23_SFT 0
+#define RG_GEMINIA_RAM_23_HI 31
+#define RG_GEMINIA_RAM_23_SZ 32
+#define RG_GEMINIA_RAM_24_MSK 0xffffffff
+#define RG_GEMINIA_RAM_24_I_MSK 0x00000000
+#define RG_GEMINIA_RAM_24_SFT 0
+#define RG_GEMINIA_RAM_24_HI 31
+#define RG_GEMINIA_RAM_24_SZ 32
+#define RG_GEMINIA_RAM_25_MSK 0xffffffff
+#define RG_GEMINIA_RAM_25_I_MSK 0x00000000
+#define RG_GEMINIA_RAM_25_SFT 0
+#define RG_GEMINIA_RAM_25_HI 31
+#define RG_GEMINIA_RAM_25_SZ 32
+#define RG_GEMINIA_RAM_26_MSK 0xffffffff
+#define RG_GEMINIA_RAM_26_I_MSK 0x00000000
+#define RG_GEMINIA_RAM_26_SFT 0
+#define RG_GEMINIA_RAM_26_HI 31
+#define RG_GEMINIA_RAM_26_SZ 32
+#define RG_GEMINIA_RAM_27_MSK 0xffffffff
+#define RG_GEMINIA_RAM_27_I_MSK 0x00000000
+#define RG_GEMINIA_RAM_27_SFT 0
+#define RG_GEMINIA_RAM_27_HI 31
+#define RG_GEMINIA_RAM_27_SZ 32
+#define RG_GEMINIA_RAM_28_MSK 0xffffffff
+#define RG_GEMINIA_RAM_28_I_MSK 0x00000000
+#define RG_GEMINIA_RAM_28_SFT 0
+#define RG_GEMINIA_RAM_28_HI 31
+#define RG_GEMINIA_RAM_28_SZ 32
+#define RG_GEMINIA_RAM_29_MSK 0xffffffff
+#define RG_GEMINIA_RAM_29_I_MSK 0x00000000
+#define RG_GEMINIA_RAM_29_SFT 0
+#define RG_GEMINIA_RAM_29_HI 31
+#define RG_GEMINIA_RAM_29_SZ 32
+#define RG_GEMINIA_RAM_30_MSK 0xffffffff
+#define RG_GEMINIA_RAM_30_I_MSK 0x00000000
+#define RG_GEMINIA_RAM_30_SFT 0
+#define RG_GEMINIA_RAM_30_HI 31
+#define RG_GEMINIA_RAM_30_SZ 32
+#define RG_GEMINIA_RAM_31_MSK 0xffffffff
+#define RG_GEMINIA_RAM_31_I_MSK 0x00000000
+#define RG_GEMINIA_RAM_31_SFT 0
+#define RG_GEMINIA_RAM_31_HI 31
+#define RG_GEMINIA_RAM_31_SZ 32
+#define RG_TURISMO_TRX_HW_PINSEL_MSK 0x00000001
+#define RG_TURISMO_TRX_HW_PINSEL_I_MSK 0xfffffffe
+#define RG_TURISMO_TRX_HW_PINSEL_SFT 0
+#define RG_TURISMO_TRX_HW_PINSEL_HI 0
+#define RG_TURISMO_TRX_HW_PINSEL_SZ 1
+#define RG_TURISMO_TRX_HS_3WIRE_MANUAL_MSK 0x00000002
+#define RG_TURISMO_TRX_HS_3WIRE_MANUAL_I_MSK 0xfffffffd
+#define RG_TURISMO_TRX_HS_3WIRE_MANUAL_SFT 1
+#define RG_TURISMO_TRX_HS_3WIRE_MANUAL_HI 1
+#define RG_TURISMO_TRX_HS_3WIRE_MANUAL_SZ 1
+#define RG_TURISMO_TRX_MODE_MANUAL_MSK 0x00000004
+#define RG_TURISMO_TRX_MODE_MANUAL_I_MSK 0xfffffffb
+#define RG_TURISMO_TRX_MODE_MANUAL_SFT 2
+#define RG_TURISMO_TRX_MODE_MANUAL_HI 2
+#define RG_TURISMO_TRX_MODE_MANUAL_SZ 1
+#define RG_TURISMO_TRX_RX_GAIN_MANUAL_MSK 0x00000010
+#define RG_TURISMO_TRX_RX_GAIN_MANUAL_I_MSK 0xffffffef
+#define RG_TURISMO_TRX_RX_GAIN_MANUAL_SFT 4
+#define RG_TURISMO_TRX_RX_GAIN_MANUAL_HI 4
+#define RG_TURISMO_TRX_RX_GAIN_MANUAL_SZ 1
+#define RG_TURISMO_TRX_TX_GAIN_MANUAL_MSK 0x00000020
+#define RG_TURISMO_TRX_TX_GAIN_MANUAL_I_MSK 0xffffffdf
+#define RG_TURISMO_TRX_TX_GAIN_MANUAL_SFT 5
+#define RG_TURISMO_TRX_TX_GAIN_MANUAL_HI 5
+#define RG_TURISMO_TRX_TX_GAIN_MANUAL_SZ 1
+#define RG_TURISMO_TRX_TXGAIN_PHYCTRL_MSK 0x00000040
+#define RG_TURISMO_TRX_TXGAIN_PHYCTRL_I_MSK 0xffffffbf
+#define RG_TURISMO_TRX_TXGAIN_PHYCTRL_SFT 6
+#define RG_TURISMO_TRX_TXGAIN_PHYCTRL_HI 6
+#define RG_TURISMO_TRX_TXGAIN_PHYCTRL_SZ 1
+#define RG_TURISMO_TRX_RX_AGC_MSK 0x00000080
+#define RG_TURISMO_TRX_RX_AGC_I_MSK 0xffffff7f
+#define RG_TURISMO_TRX_RX_AGC_SFT 7
+#define RG_TURISMO_TRX_RX_AGC_HI 7
+#define RG_TURISMO_TRX_RX_AGC_SZ 1
+#define RG_TURISMO_TRX_MODE_MSK 0x00000700
+#define RG_TURISMO_TRX_MODE_I_MSK 0xfffff8ff
+#define RG_TURISMO_TRX_MODE_SFT 8
+#define RG_TURISMO_TRX_MODE_HI 10
+#define RG_TURISMO_TRX_MODE_SZ 3
+#define RG_TURISMO_TRX_CAL_INDEX_MSK 0x0000f000
+#define RG_TURISMO_TRX_CAL_INDEX_I_MSK 0xffff0fff
+#define RG_TURISMO_TRX_CAL_INDEX_SFT 12
+#define RG_TURISMO_TRX_CAL_INDEX_HI 15
+#define RG_TURISMO_TRX_CAL_INDEX_SZ 4
+#define RG_TURISMO_TRX_RFG_MSK 0x00030000
+#define RG_TURISMO_TRX_RFG_I_MSK 0xfffcffff
+#define RG_TURISMO_TRX_RFG_SFT 16
+#define RG_TURISMO_TRX_RFG_HI 17
+#define RG_TURISMO_TRX_RFG_SZ 2
+#define RG_TURISMO_TRX_PGAG_MSK 0x003c0000
+#define RG_TURISMO_TRX_PGAG_I_MSK 0xffc3ffff
+#define RG_TURISMO_TRX_PGAG_SFT 18
+#define RG_TURISMO_TRX_PGAG_HI 21
+#define RG_TURISMO_TRX_PGAG_SZ 4
+#define RG_TURISMO_TRX_BW_HT40_MSK 0x00400000
+#define RG_TURISMO_TRX_BW_HT40_I_MSK 0xffbfffff
+#define RG_TURISMO_TRX_BW_HT40_SFT 22
+#define RG_TURISMO_TRX_BW_HT40_HI 22
+#define RG_TURISMO_TRX_BW_HT40_SZ 1
+#define RG_TURISMO_TRX_BW_MANUAL_MSK 0x00800000
+#define RG_TURISMO_TRX_BW_MANUAL_I_MSK 0xff7fffff
+#define RG_TURISMO_TRX_BW_MANUAL_SFT 23
+#define RG_TURISMO_TRX_BW_MANUAL_HI 23
+#define RG_TURISMO_TRX_BW_MANUAL_SZ 1
+#define RG_TURISMO_TRX_TX_GAIN_MSK 0x7f000000
+#define RG_TURISMO_TRX_TX_GAIN_I_MSK 0x80ffffff
+#define RG_TURISMO_TRX_TX_GAIN_SFT 24
+#define RG_TURISMO_TRX_TX_GAIN_HI 30
+#define RG_TURISMO_TRX_TX_GAIN_SZ 7
+#define RG_TURISMO_TRX_TX_TRSW_MANUAL_MSK 0x00000001
+#define RG_TURISMO_TRX_TX_TRSW_MANUAL_I_MSK 0xfffffffe
+#define RG_TURISMO_TRX_TX_TRSW_MANUAL_SFT 0
+#define RG_TURISMO_TRX_TX_TRSW_MANUAL_HI 0
+#define RG_TURISMO_TRX_TX_TRSW_MANUAL_SZ 1
+#define RG_TURISMO_TRX_EN_TX_TRSW_MSK 0x00000002
+#define RG_TURISMO_TRX_EN_TX_TRSW_I_MSK 0xfffffffd
+#define RG_TURISMO_TRX_EN_TX_TRSW_SFT 1
+#define RG_TURISMO_TRX_EN_TX_TRSW_HI 1
+#define RG_TURISMO_TRX_EN_TX_TRSW_SZ 1
+#define RG_TURISMO_TRX_RX_LNA_MANUAL_MSK 0x00000004
+#define RG_TURISMO_TRX_RX_LNA_MANUAL_I_MSK 0xfffffffb
+#define RG_TURISMO_TRX_RX_LNA_MANUAL_SFT 2
+#define RG_TURISMO_TRX_RX_LNA_MANUAL_HI 2
+#define RG_TURISMO_TRX_RX_LNA_MANUAL_SZ 1
+#define RG_TURISMO_TRX_EN_RX_LNA_MSK 0x00000008
+#define RG_TURISMO_TRX_EN_RX_LNA_I_MSK 0xfffffff7
+#define RG_TURISMO_TRX_EN_RX_LNA_SFT 3
+#define RG_TURISMO_TRX_EN_RX_LNA_HI 3
+#define RG_TURISMO_TRX_EN_RX_LNA_SZ 1
+#define RG_TURISMO_TRX_RX_MIXER_MANUAL_MSK 0x00000010
+#define RG_TURISMO_TRX_RX_MIXER_MANUAL_I_MSK 0xffffffef
+#define RG_TURISMO_TRX_RX_MIXER_MANUAL_SFT 4
+#define RG_TURISMO_TRX_RX_MIXER_MANUAL_HI 4
+#define RG_TURISMO_TRX_RX_MIXER_MANUAL_SZ 1
+#define RG_TURISMO_TRX_EN_RX_MIXER_MSK 0x00000020
+#define RG_TURISMO_TRX_EN_RX_MIXER_I_MSK 0xffffffdf
+#define RG_TURISMO_TRX_EN_RX_MIXER_SFT 5
+#define RG_TURISMO_TRX_EN_RX_MIXER_HI 5
+#define RG_TURISMO_TRX_EN_RX_MIXER_SZ 1
+#define RG_TURISMO_TRX_RX_DIV2_MANUAL_MSK 0x00000040
+#define RG_TURISMO_TRX_RX_DIV2_MANUAL_I_MSK 0xffffffbf
+#define RG_TURISMO_TRX_RX_DIV2_MANUAL_SFT 6
+#define RG_TURISMO_TRX_RX_DIV2_MANUAL_HI 6
+#define RG_TURISMO_TRX_RX_DIV2_MANUAL_SZ 1
+#define RG_TURISMO_TRX_EN_RX_DIV2_MSK 0x00000080
+#define RG_TURISMO_TRX_EN_RX_DIV2_I_MSK 0xffffff7f
+#define RG_TURISMO_TRX_EN_RX_DIV2_SFT 7
+#define RG_TURISMO_TRX_EN_RX_DIV2_HI 7
+#define RG_TURISMO_TRX_EN_RX_DIV2_SZ 1
+#define RG_TURISMO_TRX_RX_LOBUF_MANUAL_MSK 0x00000100
+#define RG_TURISMO_TRX_RX_LOBUF_MANUAL_I_MSK 0xfffffeff
+#define RG_TURISMO_TRX_RX_LOBUF_MANUAL_SFT 8
+#define RG_TURISMO_TRX_RX_LOBUF_MANUAL_HI 8
+#define RG_TURISMO_TRX_RX_LOBUF_MANUAL_SZ 1
+#define RG_TURISMO_TRX_EN_RX_LOBUF_MSK 0x00000200
+#define RG_TURISMO_TRX_EN_RX_LOBUF_I_MSK 0xfffffdff
+#define RG_TURISMO_TRX_EN_RX_LOBUF_SFT 9
+#define RG_TURISMO_TRX_EN_RX_LOBUF_HI 9
+#define RG_TURISMO_TRX_EN_RX_LOBUF_SZ 1
+#define RG_TURISMO_TRX_RX_TZ_MANUAL_MSK 0x00000400
+#define RG_TURISMO_TRX_RX_TZ_MANUAL_I_MSK 0xfffffbff
+#define RG_TURISMO_TRX_RX_TZ_MANUAL_SFT 10
+#define RG_TURISMO_TRX_RX_TZ_MANUAL_HI 10
+#define RG_TURISMO_TRX_RX_TZ_MANUAL_SZ 1
+#define RG_TURISMO_TRX_EN_RX_TZ_MSK 0x00000800
+#define RG_TURISMO_TRX_EN_RX_TZ_I_MSK 0xfffff7ff
+#define RG_TURISMO_TRX_EN_RX_TZ_SFT 11
+#define RG_TURISMO_TRX_EN_RX_TZ_HI 11
+#define RG_TURISMO_TRX_EN_RX_TZ_SZ 1
+#define RG_TURISMO_TRX_RX_FILTER_MANUAL_MSK 0x00001000
+#define RG_TURISMO_TRX_RX_FILTER_MANUAL_I_MSK 0xffffefff
+#define RG_TURISMO_TRX_RX_FILTER_MANUAL_SFT 12
+#define RG_TURISMO_TRX_RX_FILTER_MANUAL_HI 12
+#define RG_TURISMO_TRX_RX_FILTER_MANUAL_SZ 1
+#define RG_TURISMO_TRX_EN_RX_FILTER_MSK 0x00002000
+#define RG_TURISMO_TRX_EN_RX_FILTER_I_MSK 0xffffdfff
+#define RG_TURISMO_TRX_EN_RX_FILTER_SFT 13
+#define RG_TURISMO_TRX_EN_RX_FILTER_HI 13
+#define RG_TURISMO_TRX_EN_RX_FILTER_SZ 1
+#define RG_TURISMO_TRX_RX_ADC_MANUAL_MSK 0x00004000
+#define RG_TURISMO_TRX_RX_ADC_MANUAL_I_MSK 0xffffbfff
+#define RG_TURISMO_TRX_RX_ADC_MANUAL_SFT 14
+#define RG_TURISMO_TRX_RX_ADC_MANUAL_HI 14
+#define RG_TURISMO_TRX_RX_ADC_MANUAL_SZ 1
+#define RG_TURISMO_TRX_EN_RX_ADC_MSK 0x00008000
+#define RG_TURISMO_TRX_EN_RX_ADC_I_MSK 0xffff7fff
+#define RG_TURISMO_TRX_EN_RX_ADC_SFT 15
+#define RG_TURISMO_TRX_EN_RX_ADC_HI 15
+#define RG_TURISMO_TRX_EN_RX_ADC_SZ 1
+#define RG_TURISMO_TRX_RX_RSSI_MANUAL_MSK 0x00010000
+#define RG_TURISMO_TRX_RX_RSSI_MANUAL_I_MSK 0xfffeffff
+#define RG_TURISMO_TRX_RX_RSSI_MANUAL_SFT 16
+#define RG_TURISMO_TRX_RX_RSSI_MANUAL_HI 16
+#define RG_TURISMO_TRX_RX_RSSI_MANUAL_SZ 1
+#define RG_TURISMO_TRX_EN_RX_RSSI_MSK 0x00020000
+#define RG_TURISMO_TRX_EN_RX_RSSI_I_MSK 0xfffdffff
+#define RG_TURISMO_TRX_EN_RX_RSSI_SFT 17
+#define RG_TURISMO_TRX_EN_RX_RSSI_HI 17
+#define RG_TURISMO_TRX_EN_RX_RSSI_SZ 1
+#define RG_TURISMO_TRX_TX_PA_MANUAL_MSK 0x00040000
+#define RG_TURISMO_TRX_TX_PA_MANUAL_I_MSK 0xfffbffff
+#define RG_TURISMO_TRX_TX_PA_MANUAL_SFT 18
+#define RG_TURISMO_TRX_TX_PA_MANUAL_HI 18
+#define RG_TURISMO_TRX_TX_PA_MANUAL_SZ 1
+#define RG_TURISMO_TRX_EN_TX_PA_MSK 0x00080000
+#define RG_TURISMO_TRX_EN_TX_PA_I_MSK 0xfff7ffff
+#define RG_TURISMO_TRX_EN_TX_PA_SFT 19
+#define RG_TURISMO_TRX_EN_TX_PA_HI 19
+#define RG_TURISMO_TRX_EN_TX_PA_SZ 1
+#define RG_TURISMO_TRX_TX_MOD_MANUAL_MSK 0x00100000
+#define RG_TURISMO_TRX_TX_MOD_MANUAL_I_MSK 0xffefffff
+#define RG_TURISMO_TRX_TX_MOD_MANUAL_SFT 20
+#define RG_TURISMO_TRX_TX_MOD_MANUAL_HI 20
+#define RG_TURISMO_TRX_TX_MOD_MANUAL_SZ 1
+#define RG_TURISMO_TRX_EN_TX_MOD_MSK 0x00200000
+#define RG_TURISMO_TRX_EN_TX_MOD_I_MSK 0xffdfffff
+#define RG_TURISMO_TRX_EN_TX_MOD_SFT 21
+#define RG_TURISMO_TRX_EN_TX_MOD_HI 21
+#define RG_TURISMO_TRX_EN_TX_MOD_SZ 1
+#define RG_TURISMO_TRX_TX_DAC_MANUAL_MSK 0x00400000
+#define RG_TURISMO_TRX_TX_DAC_MANUAL_I_MSK 0xffbfffff
+#define RG_TURISMO_TRX_TX_DAC_MANUAL_SFT 22
+#define RG_TURISMO_TRX_TX_DAC_MANUAL_HI 22
+#define RG_TURISMO_TRX_TX_DAC_MANUAL_SZ 1
+#define RG_TURISMO_TRX_EN_TX_DAC_MSK 0x00800000
+#define RG_TURISMO_TRX_EN_TX_DAC_I_MSK 0xff7fffff
+#define RG_TURISMO_TRX_EN_TX_DAC_SFT 23
+#define RG_TURISMO_TRX_EN_TX_DAC_HI 23
+#define RG_TURISMO_TRX_EN_TX_DAC_SZ 1
+#define RG_TURISMO_TRX_TX_DIV2_MANUAL_MSK 0x01000000
+#define RG_TURISMO_TRX_TX_DIV2_MANUAL_I_MSK 0xfeffffff
+#define RG_TURISMO_TRX_TX_DIV2_MANUAL_SFT 24
+#define RG_TURISMO_TRX_TX_DIV2_MANUAL_HI 24
+#define RG_TURISMO_TRX_TX_DIV2_MANUAL_SZ 1
+#define RG_TURISMO_TRX_EN_TX_DIV2_MSK 0x02000000
+#define RG_TURISMO_TRX_EN_TX_DIV2_I_MSK 0xfdffffff
+#define RG_TURISMO_TRX_EN_TX_DIV2_SFT 25
+#define RG_TURISMO_TRX_EN_TX_DIV2_HI 25
+#define RG_TURISMO_TRX_EN_TX_DIV2_SZ 1
+#define RG_TURISMO_TRX_TX_DIV2_BUF_MANUAL_MSK 0x04000000
+#define RG_TURISMO_TRX_TX_DIV2_BUF_MANUAL_I_MSK 0xfbffffff
+#define RG_TURISMO_TRX_TX_DIV2_BUF_MANUAL_SFT 26
+#define RG_TURISMO_TRX_TX_DIV2_BUF_MANUAL_HI 26
+#define RG_TURISMO_TRX_TX_DIV2_BUF_MANUAL_SZ 1
+#define RG_TURISMO_TRX_EN_TX_DIV2_BUF_MSK 0x08000000
+#define RG_TURISMO_TRX_EN_TX_DIV2_BUF_I_MSK 0xf7ffffff
+#define RG_TURISMO_TRX_EN_TX_DIV2_BUF_SFT 27
+#define RG_TURISMO_TRX_EN_TX_DIV2_BUF_HI 27
+#define RG_TURISMO_TRX_EN_TX_DIV2_BUF_SZ 1
+#define RG_TURISMO_TRX_TX_BT_PA_MANUAL_MSK 0x10000000
+#define RG_TURISMO_TRX_TX_BT_PA_MANUAL_I_MSK 0xefffffff
+#define RG_TURISMO_TRX_TX_BT_PA_MANUAL_SFT 28
+#define RG_TURISMO_TRX_TX_BT_PA_MANUAL_HI 28
+#define RG_TURISMO_TRX_TX_BT_PA_MANUAL_SZ 1
+#define RG_TURISMO_TRX_EN_TX_BT_PA_MSK 0x20000000
+#define RG_TURISMO_TRX_EN_TX_BT_PA_I_MSK 0xdfffffff
+#define RG_TURISMO_TRX_EN_TX_BT_PA_SFT 29
+#define RG_TURISMO_TRX_EN_TX_BT_PA_HI 29
+#define RG_TURISMO_TRX_EN_TX_BT_PA_SZ 1
+#define RG_TURISMO_TRX_EN_IOT_ADC_BUF_MSK 0x40000000
+#define RG_TURISMO_TRX_EN_IOT_ADC_BUF_I_MSK 0xbfffffff
+#define RG_TURISMO_TRX_EN_IOT_ADC_BUF_SFT 30
+#define RG_TURISMO_TRX_EN_IOT_ADC_BUF_HI 30
+#define RG_TURISMO_TRX_EN_IOT_ADC_BUF_SZ 1
+#define RG_TURISMO_TRX_EN_IOT_ADC_MSK 0x80000000
+#define RG_TURISMO_TRX_EN_IOT_ADC_I_MSK 0x7fffffff
+#define RG_TURISMO_TRX_EN_IOT_ADC_SFT 31
+#define RG_TURISMO_TRX_EN_IOT_ADC_HI 31
+#define RG_TURISMO_TRX_EN_IOT_ADC_SZ 1
+#define RG_TURISMO_TRX_EN_LDO_RX_FE_MSK 0x00000001
+#define RG_TURISMO_TRX_EN_LDO_RX_FE_I_MSK 0xfffffffe
+#define RG_TURISMO_TRX_EN_LDO_RX_FE_SFT 0
+#define RG_TURISMO_TRX_EN_LDO_RX_FE_HI 0
+#define RG_TURISMO_TRX_EN_LDO_RX_FE_SZ 1
+#define RG_TURISMO_TRX_EN_LDO_AFE_MSK 0x00000002
+#define RG_TURISMO_TRX_EN_LDO_AFE_I_MSK 0xfffffffd
+#define RG_TURISMO_TRX_EN_LDO_AFE_SFT 1
+#define RG_TURISMO_TRX_EN_LDO_AFE_HI 1
+#define RG_TURISMO_TRX_EN_LDO_AFE_SZ 1
+#define RG_TURISMO_TRX_EN_IREF_RX_MSK 0x00000004
+#define RG_TURISMO_TRX_EN_IREF_RX_I_MSK 0xfffffffb
+#define RG_TURISMO_TRX_EN_IREF_RX_SFT 2
+#define RG_TURISMO_TRX_EN_IREF_RX_HI 2
+#define RG_TURISMO_TRX_EN_IREF_RX_SZ 1
+#define RG_TURISMO_TRX_TX_DAC_CAL_MANUAL_MSK 0x00000008
+#define RG_TURISMO_TRX_TX_DAC_CAL_MANUAL_I_MSK 0xfffffff7
+#define RG_TURISMO_TRX_TX_DAC_CAL_MANUAL_SFT 3
+#define RG_TURISMO_TRX_TX_DAC_CAL_MANUAL_HI 3
+#define RG_TURISMO_TRX_TX_DAC_CAL_MANUAL_SZ 1
+#define RG_TURISMO_TRX_EN_TX_DAC_CAL_MSK 0x00000010
+#define RG_TURISMO_TRX_EN_TX_DAC_CAL_I_MSK 0xffffffef
+#define RG_TURISMO_TRX_EN_TX_DAC_CAL_SFT 4
+#define RG_TURISMO_TRX_EN_TX_DAC_CAL_HI 4
+#define RG_TURISMO_TRX_EN_TX_DAC_CAL_SZ 1
+#define RG_TURISMO_TRX_RX_TZ_OUT_TRISTATE_MANUAL_MSK 0x00000020
+#define RG_TURISMO_TRX_RX_TZ_OUT_TRISTATE_MANUAL_I_MSK 0xffffffdf
+#define RG_TURISMO_TRX_RX_TZ_OUT_TRISTATE_MANUAL_SFT 5
+#define RG_TURISMO_TRX_RX_TZ_OUT_TRISTATE_MANUAL_HI 5
+#define RG_TURISMO_TRX_RX_TZ_OUT_TRISTATE_MANUAL_SZ 1
+#define RG_TURISMO_TRX_RX_TZ_OUT_TRISTATE_MSK 0x00000040
+#define RG_TURISMO_TRX_RX_TZ_OUT_TRISTATE_I_MSK 0xffffffbf
+#define RG_TURISMO_TRX_RX_TZ_OUT_TRISTATE_SFT 6
+#define RG_TURISMO_TRX_RX_TZ_OUT_TRISTATE_HI 6
+#define RG_TURISMO_TRX_RX_TZ_OUT_TRISTATE_SZ 1
+#define RG_TURISMO_TRX_TX_SELF_MIXER_MANUAL_MSK 0x00000080
+#define RG_TURISMO_TRX_TX_SELF_MIXER_MANUAL_I_MSK 0xffffff7f
+#define RG_TURISMO_TRX_TX_SELF_MIXER_MANUAL_SFT 7
+#define RG_TURISMO_TRX_TX_SELF_MIXER_MANUAL_HI 7
+#define RG_TURISMO_TRX_TX_SELF_MIXER_MANUAL_SZ 1
+#define RG_TURISMO_TRX_EN_TX_SELF_MIXER_MSK 0x00000100
+#define RG_TURISMO_TRX_EN_TX_SELF_MIXER_I_MSK 0xfffffeff
+#define RG_TURISMO_TRX_EN_TX_SELF_MIXER_SFT 8
+#define RG_TURISMO_TRX_EN_TX_SELF_MIXER_HI 8
+#define RG_TURISMO_TRX_EN_TX_SELF_MIXER_SZ 1
+#define RG_TURISMO_TRX_RX_IQCAL_MANUAL_MSK 0x00000200
+#define RG_TURISMO_TRX_RX_IQCAL_MANUAL_I_MSK 0xfffffdff
+#define RG_TURISMO_TRX_RX_IQCAL_MANUAL_SFT 9
+#define RG_TURISMO_TRX_RX_IQCAL_MANUAL_HI 9
+#define RG_TURISMO_TRX_RX_IQCAL_MANUAL_SZ 1
+#define RG_TURISMO_TRX_EN_RX_IQCAL_MSK 0x00000400
+#define RG_TURISMO_TRX_EN_RX_IQCAL_I_MSK 0xfffffbff
+#define RG_TURISMO_TRX_EN_RX_IQCAL_SFT 10
+#define RG_TURISMO_TRX_EN_RX_IQCAL_HI 10
+#define RG_TURISMO_TRX_EN_RX_IQCAL_SZ 1
+#define RG_TURISMO_TRX_TX_DPD_MANUAL_MSK 0x00000800
+#define RG_TURISMO_TRX_TX_DPD_MANUAL_I_MSK 0xfffff7ff
+#define RG_TURISMO_TRX_TX_DPD_MANUAL_SFT 11
+#define RG_TURISMO_TRX_TX_DPD_MANUAL_HI 11
+#define RG_TURISMO_TRX_TX_DPD_MANUAL_SZ 1
+#define RG_TURISMO_TRX_EN_TX_DPD_MSK 0x00001000
+#define RG_TURISMO_TRX_EN_TX_DPD_I_MSK 0xffffefff
+#define RG_TURISMO_TRX_EN_TX_DPD_SFT 12
+#define RG_TURISMO_TRX_EN_TX_DPD_HI 12
+#define RG_TURISMO_TRX_EN_TX_DPD_SZ 1
+#define RG_TURISMO_TRX_EN_TX_TSSI_MSK 0x00004000
+#define RG_TURISMO_TRX_EN_TX_TSSI_I_MSK 0xffffbfff
+#define RG_TURISMO_TRX_EN_TX_TSSI_SFT 14
+#define RG_TURISMO_TRX_EN_TX_TSSI_HI 14
+#define RG_TURISMO_TRX_EN_TX_TSSI_SZ 1
+#define RG_TURISMO_TRX_EN_SARADC_MSK 0x00008000
+#define RG_TURISMO_TRX_EN_SARADC_I_MSK 0xffff7fff
+#define RG_TURISMO_TRX_EN_SARADC_SFT 15
+#define RG_TURISMO_TRX_EN_SARADC_HI 15
+#define RG_TURISMO_TRX_EN_SARADC_SZ 1
+#define RG_TURISMO_TRX_EN_TX_VTOI_2ND_MSK 0x00010000
+#define RG_TURISMO_TRX_EN_TX_VTOI_2ND_I_MSK 0xfffeffff
+#define RG_TURISMO_TRX_EN_TX_VTOI_2ND_SFT 16
+#define RG_TURISMO_TRX_EN_TX_VTOI_2ND_HI 16
+#define RG_TURISMO_TRX_EN_TX_VTOI_2ND_SZ 1
+#define RG_TURISMO_TRX_TXLPF_BYPASS_MSK 0x00020000
+#define RG_TURISMO_TRX_TXLPF_BYPASS_I_MSK 0xfffdffff
+#define RG_TURISMO_TRX_TXLPF_BYPASS_SFT 17
+#define RG_TURISMO_TRX_TXLPF_BYPASS_HI 17
+#define RG_TURISMO_TRX_TXLPF_BYPASS_SZ 1
+#define RG_TURISMO_TRX_TX_EN_VOLTAGE_IN_MSK 0x00040000
+#define RG_TURISMO_TRX_TX_EN_VOLTAGE_IN_I_MSK 0xfffbffff
+#define RG_TURISMO_TRX_TX_EN_VOLTAGE_IN_SFT 18
+#define RG_TURISMO_TRX_TX_EN_VOLTAGE_IN_HI 18
+#define RG_TURISMO_TRX_TX_EN_VOLTAGE_IN_SZ 1
+#define RG_TURISMO_TRX_EN_TX_DAC_OUT_MSK 0x00080000
+#define RG_TURISMO_TRX_EN_TX_DAC_OUT_I_MSK 0xfff7ffff
+#define RG_TURISMO_TRX_EN_TX_DAC_OUT_SFT 19
+#define RG_TURISMO_TRX_EN_TX_DAC_OUT_HI 19
+#define RG_TURISMO_TRX_EN_TX_DAC_OUT_SZ 1
+#define RG_TURISMO_TRX_EN_TX_DAC_VOUT_MSK 0x00100000
+#define RG_TURISMO_TRX_EN_TX_DAC_VOUT_I_MSK 0xffefffff
+#define RG_TURISMO_TRX_EN_TX_DAC_VOUT_SFT 20
+#define RG_TURISMO_TRX_EN_TX_DAC_VOUT_HI 20
+#define RG_TURISMO_TRX_EN_TX_DAC_VOUT_SZ 1
+#define RG_TURISMO_TRX_RX_ABBOUT_TRI_STATE_MSK 0x00200000
+#define RG_TURISMO_TRX_RX_ABBOUT_TRI_STATE_I_MSK 0xffdfffff
+#define RG_TURISMO_TRX_RX_ABBOUT_TRI_STATE_SFT 21
+#define RG_TURISMO_TRX_RX_ABBOUT_TRI_STATE_HI 21
+#define RG_TURISMO_TRX_RX_ABBOUT_TRI_STATE_SZ 1
+#define RG_TURISMO_TRX_EN_RX_TESTNODE_MSK 0x00400000
+#define RG_TURISMO_TRX_EN_RX_TESTNODE_I_MSK 0xffbfffff
+#define RG_TURISMO_TRX_EN_RX_TESTNODE_SFT 22
+#define RG_TURISMO_TRX_EN_RX_TESTNODE_HI 22
+#define RG_TURISMO_TRX_EN_RX_TESTNODE_SZ 1
+#define RG_TURISMO_TRX_EN_RX_PADSW_MSK 0x00800000
+#define RG_TURISMO_TRX_EN_RX_PADSW_I_MSK 0xff7fffff
+#define RG_TURISMO_TRX_EN_RX_PADSW_SFT 23
+#define RG_TURISMO_TRX_EN_RX_PADSW_HI 23
+#define RG_TURISMO_TRX_EN_RX_PADSW_SZ 1
+#define RG_TURISMO_TRX_EN_LDO_RX_FE_FC_MSK 0x02000000
+#define RG_TURISMO_TRX_EN_LDO_RX_FE_FC_I_MSK 0xfdffffff
+#define RG_TURISMO_TRX_EN_LDO_RX_FE_FC_SFT 25
+#define RG_TURISMO_TRX_EN_LDO_RX_FE_FC_HI 25
+#define RG_TURISMO_TRX_EN_LDO_RX_FE_FC_SZ 1
+#define RG_TURISMO_TRX_EN_LDO_RX_AFE_FC_MSK 0x04000000
+#define RG_TURISMO_TRX_EN_LDO_RX_AFE_FC_I_MSK 0xfbffffff
+#define RG_TURISMO_TRX_EN_LDO_RX_AFE_FC_SFT 26
+#define RG_TURISMO_TRX_EN_LDO_RX_AFE_FC_HI 26
+#define RG_TURISMO_TRX_EN_LDO_RX_AFE_FC_SZ 1
+#define RG_TURISMO_TRX_EN_LDO_RX_FE_IQUP_MSK 0x08000000
+#define RG_TURISMO_TRX_EN_LDO_RX_FE_IQUP_I_MSK 0xf7ffffff
+#define RG_TURISMO_TRX_EN_LDO_RX_FE_IQUP_SFT 27
+#define RG_TURISMO_TRX_EN_LDO_RX_FE_IQUP_HI 27
+#define RG_TURISMO_TRX_EN_LDO_RX_FE_IQUP_SZ 1
+#define RG_TURISMO_TRX_EN_LDO_RX_AFE_IQUP_MSK 0x10000000
+#define RG_TURISMO_TRX_EN_LDO_RX_AFE_IQUP_I_MSK 0xefffffff
+#define RG_TURISMO_TRX_EN_LDO_RX_AFE_IQUP_SFT 28
+#define RG_TURISMO_TRX_EN_LDO_RX_AFE_IQUP_HI 28
+#define RG_TURISMO_TRX_EN_LDO_RX_AFE_IQUP_SZ 1
+#define RG_TURISMO_TRX_RX_SQDC_MSK 0xe0000000
+#define RG_TURISMO_TRX_RX_SQDC_I_MSK 0x1fffffff
+#define RG_TURISMO_TRX_RX_SQDC_SFT 29
+#define RG_TURISMO_TRX_RX_SQDC_HI 31
+#define RG_TURISMO_TRX_RX_SQDC_SZ 3
+#define RG_TURISMO_TRX_LDO_LEVEL_RX_FE_MSK 0x00000007
+#define RG_TURISMO_TRX_LDO_LEVEL_RX_FE_I_MSK 0xfffffff8
+#define RG_TURISMO_TRX_LDO_LEVEL_RX_FE_SFT 0
+#define RG_TURISMO_TRX_LDO_LEVEL_RX_FE_HI 2
+#define RG_TURISMO_TRX_LDO_LEVEL_RX_FE_SZ 3
+#define RG_TURISMO_TRX_EN_LDO_RX_FE_BYP_MSK 0x00000008
+#define RG_TURISMO_TRX_EN_LDO_RX_FE_BYP_I_MSK 0xfffffff7
+#define RG_TURISMO_TRX_EN_LDO_RX_FE_BYP_SFT 3
+#define RG_TURISMO_TRX_EN_LDO_RX_FE_BYP_HI 3
+#define RG_TURISMO_TRX_EN_LDO_RX_FE_BYP_SZ 1
+#define RG_TURISMO_TRX_LDO_LEVEL_AFE_MSK 0x00000070
+#define RG_TURISMO_TRX_LDO_LEVEL_AFE_I_MSK 0xffffff8f
+#define RG_TURISMO_TRX_LDO_LEVEL_AFE_SFT 4
+#define RG_TURISMO_TRX_LDO_LEVEL_AFE_HI 6
+#define RG_TURISMO_TRX_LDO_LEVEL_AFE_SZ 3
+#define RG_TURISMO_TRX_EN_LDO_RX_AFE_BYP_MSK 0x00000080
+#define RG_TURISMO_TRX_EN_LDO_RX_AFE_BYP_I_MSK 0xffffff7f
+#define RG_TURISMO_TRX_EN_LDO_RX_AFE_BYP_SFT 7
+#define RG_TURISMO_TRX_EN_LDO_RX_AFE_BYP_HI 7
+#define RG_TURISMO_TRX_EN_LDO_RX_AFE_BYP_SZ 1
+#define RG_TURISMO_TRX_TX_PA_LDO_LEVEL_MSK 0x00000700
+#define RG_TURISMO_TRX_TX_PA_LDO_LEVEL_I_MSK 0xfffff8ff
+#define RG_TURISMO_TRX_TX_PA_LDO_LEVEL_SFT 8
+#define RG_TURISMO_TRX_TX_PA_LDO_LEVEL_HI 10
+#define RG_TURISMO_TRX_TX_PA_LDO_LEVEL_SZ 3
+#define RG_TURISMO_TRX_DP_LDO_LEVEL_MSK 0x00007000
+#define RG_TURISMO_TRX_DP_LDO_LEVEL_I_MSK 0xffff8fff
+#define RG_TURISMO_TRX_DP_LDO_LEVEL_SFT 12
+#define RG_TURISMO_TRX_DP_LDO_LEVEL_HI 14
+#define RG_TURISMO_TRX_DP_LDO_LEVEL_SZ 3
+#define RG_TURISMO_TRX_EN_LDO_DP_BYP_MSK 0x00008000
+#define RG_TURISMO_TRX_EN_LDO_DP_BYP_I_MSK 0xffff7fff
+#define RG_TURISMO_TRX_EN_LDO_DP_BYP_SFT 15
+#define RG_TURISMO_TRX_EN_LDO_DP_BYP_HI 15
+#define RG_TURISMO_TRX_EN_LDO_DP_BYP_SZ 1
+#define RG_TURISMO_TRX_SX_LDO_CP_LEVEL_MSK 0x00070000
+#define RG_TURISMO_TRX_SX_LDO_CP_LEVEL_I_MSK 0xfff8ffff
+#define RG_TURISMO_TRX_SX_LDO_CP_LEVEL_SFT 16
+#define RG_TURISMO_TRX_SX_LDO_CP_LEVEL_HI 18
+#define RG_TURISMO_TRX_SX_LDO_CP_LEVEL_SZ 3
+#define RG_TURISMO_TRX_EN_LDO_CP_BYP_MSK 0x00080000
+#define RG_TURISMO_TRX_EN_LDO_CP_BYP_I_MSK 0xfff7ffff
+#define RG_TURISMO_TRX_EN_LDO_CP_BYP_SFT 19
+#define RG_TURISMO_TRX_EN_LDO_CP_BYP_HI 19
+#define RG_TURISMO_TRX_EN_LDO_CP_BYP_SZ 1
+#define RG_TURISMO_TRX_SX_LDO_LO_LEVEL_MSK 0x00700000
+#define RG_TURISMO_TRX_SX_LDO_LO_LEVEL_I_MSK 0xff8fffff
+#define RG_TURISMO_TRX_SX_LDO_LO_LEVEL_SFT 20
+#define RG_TURISMO_TRX_SX_LDO_LO_LEVEL_HI 22
+#define RG_TURISMO_TRX_SX_LDO_LO_LEVEL_SZ 3
+#define RG_TURISMO_TRX_EN_LDO_LO_BYP_MSK 0x00800000
+#define RG_TURISMO_TRX_EN_LDO_LO_BYP_I_MSK 0xff7fffff
+#define RG_TURISMO_TRX_EN_LDO_LO_BYP_SFT 23
+#define RG_TURISMO_TRX_EN_LDO_LO_BYP_HI 23
+#define RG_TURISMO_TRX_EN_LDO_LO_BYP_SZ 1
+#define RG_TURISMO_TRX_SX_LDO_VCO_LEVEL_MSK 0x07000000
+#define RG_TURISMO_TRX_SX_LDO_VCO_LEVEL_I_MSK 0xf8ffffff
+#define RG_TURISMO_TRX_SX_LDO_VCO_LEVEL_SFT 24
+#define RG_TURISMO_TRX_SX_LDO_VCO_LEVEL_HI 26
+#define RG_TURISMO_TRX_SX_LDO_VCO_LEVEL_SZ 3
+#define RG_TURISMO_TRX_SX_LDO_DIV_LEVEL_MSK 0x70000000
+#define RG_TURISMO_TRX_SX_LDO_DIV_LEVEL_I_MSK 0x8fffffff
+#define RG_TURISMO_TRX_SX_LDO_DIV_LEVEL_SFT 28
+#define RG_TURISMO_TRX_SX_LDO_DIV_LEVEL_HI 30
+#define RG_TURISMO_TRX_SX_LDO_DIV_LEVEL_SZ 3
+#define RG_TURISMO_TRX_EN_LDO_DIV_BYP_MSK 0x80000000
+#define RG_TURISMO_TRX_EN_LDO_DIV_BYP_I_MSK 0x7fffffff
+#define RG_TURISMO_TRX_EN_LDO_DIV_BYP_SFT 31
+#define RG_TURISMO_TRX_EN_LDO_DIV_BYP_HI 31
+#define RG_TURISMO_TRX_EN_LDO_DIV_BYP_SZ 1
+#define RG_TURISMO_TRX_WF_RX_ABBCTUNE_MSK 0x0000003f
+#define RG_TURISMO_TRX_WF_RX_ABBCTUNE_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_WF_RX_ABBCTUNE_SFT 0
+#define RG_TURISMO_TRX_WF_RX_ABBCTUNE_HI 5
+#define RG_TURISMO_TRX_WF_RX_ABBCTUNE_SZ 6
+#define RG_TURISMO_TRX_WF_RX_FILTERI_COARSE_MSK 0x00000300
+#define RG_TURISMO_TRX_WF_RX_FILTERI_COARSE_I_MSK 0xfffffcff
+#define RG_TURISMO_TRX_WF_RX_FILTERI_COARSE_SFT 8
+#define RG_TURISMO_TRX_WF_RX_FILTERI_COARSE_HI 9
+#define RG_TURISMO_TRX_WF_RX_FILTERI_COARSE_SZ 2
+#define RG_TURISMO_TRX_WF_RX_FILTERI1ST_MSK 0x00000c00
+#define RG_TURISMO_TRX_WF_RX_FILTERI1ST_I_MSK 0xfffff3ff
+#define RG_TURISMO_TRX_WF_RX_FILTERI1ST_SFT 10
+#define RG_TURISMO_TRX_WF_RX_FILTERI1ST_HI 11
+#define RG_TURISMO_TRX_WF_RX_FILTERI1ST_SZ 2
+#define RG_TURISMO_TRX_WF_RX_FILTERI2ND_MSK 0x00003000
+#define RG_TURISMO_TRX_WF_RX_FILTERI2ND_I_MSK 0xffffcfff
+#define RG_TURISMO_TRX_WF_RX_FILTERI2ND_SFT 12
+#define RG_TURISMO_TRX_WF_RX_FILTERI2ND_HI 13
+#define RG_TURISMO_TRX_WF_RX_FILTERI2ND_SZ 2
+#define RG_TURISMO_TRX_WF_RX_FILTERI3RD_MSK 0x0000c000
+#define RG_TURISMO_TRX_WF_RX_FILTERI3RD_I_MSK 0xffff3fff
+#define RG_TURISMO_TRX_WF_RX_FILTERI3RD_SFT 14
+#define RG_TURISMO_TRX_WF_RX_FILTERI3RD_HI 15
+#define RG_TURISMO_TRX_WF_RX_FILTERI3RD_SZ 2
+#define RG_TURISMO_TRX_WF_RX_ABBCFIX_MSK 0x00010000
+#define RG_TURISMO_TRX_WF_RX_ABBCFIX_I_MSK 0xfffeffff
+#define RG_TURISMO_TRX_WF_RX_ABBCFIX_SFT 16
+#define RG_TURISMO_TRX_WF_RX_ABBCFIX_HI 16
+#define RG_TURISMO_TRX_WF_RX_ABBCFIX_SZ 1
+#define RG_TURISMO_TRX_WF_RX_ABB_N_MODE_MSK 0x00020000
+#define RG_TURISMO_TRX_WF_RX_ABB_N_MODE_I_MSK 0xfffdffff
+#define RG_TURISMO_TRX_WF_RX_ABB_N_MODE_SFT 17
+#define RG_TURISMO_TRX_WF_RX_ABB_N_MODE_HI 17
+#define RG_TURISMO_TRX_WF_RX_ABB_N_MODE_SZ 1
+#define RG_TURISMO_TRX_WF_RX_ABB_BT_MODE_MSK 0x00040000
+#define RG_TURISMO_TRX_WF_RX_ABB_BT_MODE_I_MSK 0xfffbffff
+#define RG_TURISMO_TRX_WF_RX_ABB_BT_MODE_SFT 18
+#define RG_TURISMO_TRX_WF_RX_ABB_BT_MODE_HI 18
+#define RG_TURISMO_TRX_WF_RX_ABB_BT_MODE_SZ 1
+#define RG_TURISMO_TRX_WF_RX_ABB_IDIV3_MSK 0x00080000
+#define RG_TURISMO_TRX_WF_RX_ABB_IDIV3_I_MSK 0xfff7ffff
+#define RG_TURISMO_TRX_WF_RX_ABB_IDIV3_SFT 19
+#define RG_TURISMO_TRX_WF_RX_ABB_IDIV3_HI 19
+#define RG_TURISMO_TRX_WF_RX_ABB_IDIV3_SZ 1
+#define RG_TURISMO_TRX_WF_RX_EN_IDACA_COARSE_MSK 0x00100000
+#define RG_TURISMO_TRX_WF_RX_EN_IDACA_COARSE_I_MSK 0xffefffff
+#define RG_TURISMO_TRX_WF_RX_EN_IDACA_COARSE_SFT 20
+#define RG_TURISMO_TRX_WF_RX_EN_IDACA_COARSE_HI 20
+#define RG_TURISMO_TRX_WF_RX_EN_IDACA_COARSE_SZ 1
+#define RG_TURISMO_TRX_WF_RX_EN_LOOPA_MSK 0x00200000
+#define RG_TURISMO_TRX_WF_RX_EN_LOOPA_I_MSK 0xffdfffff
+#define RG_TURISMO_TRX_WF_RX_EN_LOOPA_SFT 21
+#define RG_TURISMO_TRX_WF_RX_EN_LOOPA_HI 21
+#define RG_TURISMO_TRX_WF_RX_EN_LOOPA_SZ 1
+#define RG_TURISMO_TRX_WF_RX_FILTERVCM_MSK 0x07000000
+#define RG_TURISMO_TRX_WF_RX_FILTERVCM_I_MSK 0xf8ffffff
+#define RG_TURISMO_TRX_WF_RX_FILTERVCM_SFT 24
+#define RG_TURISMO_TRX_WF_RX_FILTERVCM_HI 26
+#define RG_TURISMO_TRX_WF_RX_FILTERVCM_SZ 3
+#define RG_TURISMO_TRX_WF_RX_OUTVCM_MSK 0x70000000
+#define RG_TURISMO_TRX_WF_RX_OUTVCM_I_MSK 0x8fffffff
+#define RG_TURISMO_TRX_WF_RX_OUTVCM_SFT 28
+#define RG_TURISMO_TRX_WF_RX_OUTVCM_HI 30
+#define RG_TURISMO_TRX_WF_RX_OUTVCM_SZ 3
+#define RG_TURISMO_TRX_WF_N_RX_ABBCTUNE_MSK 0x0000003f
+#define RG_TURISMO_TRX_WF_N_RX_ABBCTUNE_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_WF_N_RX_ABBCTUNE_SFT 0
+#define RG_TURISMO_TRX_WF_N_RX_ABBCTUNE_HI 5
+#define RG_TURISMO_TRX_WF_N_RX_ABBCTUNE_SZ 6
+#define RG_TURISMO_TRX_WF_N_RX_FILTERI_COARSE_MSK 0x00000300
+#define RG_TURISMO_TRX_WF_N_RX_FILTERI_COARSE_I_MSK 0xfffffcff
+#define RG_TURISMO_TRX_WF_N_RX_FILTERI_COARSE_SFT 8
+#define RG_TURISMO_TRX_WF_N_RX_FILTERI_COARSE_HI 9
+#define RG_TURISMO_TRX_WF_N_RX_FILTERI_COARSE_SZ 2
+#define RG_TURISMO_TRX_WF_N_RX_FILTERI1ST_MSK 0x00000c00
+#define RG_TURISMO_TRX_WF_N_RX_FILTERI1ST_I_MSK 0xfffff3ff
+#define RG_TURISMO_TRX_WF_N_RX_FILTERI1ST_SFT 10
+#define RG_TURISMO_TRX_WF_N_RX_FILTERI1ST_HI 11
+#define RG_TURISMO_TRX_WF_N_RX_FILTERI1ST_SZ 2
+#define RG_TURISMO_TRX_WF_N_RX_FILTERI2ND_MSK 0x00003000
+#define RG_TURISMO_TRX_WF_N_RX_FILTERI2ND_I_MSK 0xffffcfff
+#define RG_TURISMO_TRX_WF_N_RX_FILTERI2ND_SFT 12
+#define RG_TURISMO_TRX_WF_N_RX_FILTERI2ND_HI 13
+#define RG_TURISMO_TRX_WF_N_RX_FILTERI2ND_SZ 2
+#define RG_TURISMO_TRX_WF_N_RX_FILTERI3RD_MSK 0x0000c000
+#define RG_TURISMO_TRX_WF_N_RX_FILTERI3RD_I_MSK 0xffff3fff
+#define RG_TURISMO_TRX_WF_N_RX_FILTERI3RD_SFT 14
+#define RG_TURISMO_TRX_WF_N_RX_FILTERI3RD_HI 15
+#define RG_TURISMO_TRX_WF_N_RX_FILTERI3RD_SZ 2
+#define RG_TURISMO_TRX_WF_N_RX_ABBCFIX_MSK 0x00010000
+#define RG_TURISMO_TRX_WF_N_RX_ABBCFIX_I_MSK 0xfffeffff
+#define RG_TURISMO_TRX_WF_N_RX_ABBCFIX_SFT 16
+#define RG_TURISMO_TRX_WF_N_RX_ABBCFIX_HI 16
+#define RG_TURISMO_TRX_WF_N_RX_ABBCFIX_SZ 1
+#define RG_TURISMO_TRX_WF_N_RX_ABB_N_MODE_MSK 0x00020000
+#define RG_TURISMO_TRX_WF_N_RX_ABB_N_MODE_I_MSK 0xfffdffff
+#define RG_TURISMO_TRX_WF_N_RX_ABB_N_MODE_SFT 17
+#define RG_TURISMO_TRX_WF_N_RX_ABB_N_MODE_HI 17
+#define RG_TURISMO_TRX_WF_N_RX_ABB_N_MODE_SZ 1
+#define RG_TURISMO_TRX_WF_N_RX_ABB_BT_MODE_MSK 0x00040000
+#define RG_TURISMO_TRX_WF_N_RX_ABB_BT_MODE_I_MSK 0xfffbffff
+#define RG_TURISMO_TRX_WF_N_RX_ABB_BT_MODE_SFT 18
+#define RG_TURISMO_TRX_WF_N_RX_ABB_BT_MODE_HI 18
+#define RG_TURISMO_TRX_WF_N_RX_ABB_BT_MODE_SZ 1
+#define RG_TURISMO_TRX_WF_N_RX_ABB_IDIV3_MSK 0x00080000
+#define RG_TURISMO_TRX_WF_N_RX_ABB_IDIV3_I_MSK 0xfff7ffff
+#define RG_TURISMO_TRX_WF_N_RX_ABB_IDIV3_SFT 19
+#define RG_TURISMO_TRX_WF_N_RX_ABB_IDIV3_HI 19
+#define RG_TURISMO_TRX_WF_N_RX_ABB_IDIV3_SZ 1
+#define RG_TURISMO_TRX_WF_N_RX_EN_IDACA_COARSE_MSK 0x00100000
+#define RG_TURISMO_TRX_WF_N_RX_EN_IDACA_COARSE_I_MSK 0xffefffff
+#define RG_TURISMO_TRX_WF_N_RX_EN_IDACA_COARSE_SFT 20
+#define RG_TURISMO_TRX_WF_N_RX_EN_IDACA_COARSE_HI 20
+#define RG_TURISMO_TRX_WF_N_RX_EN_IDACA_COARSE_SZ 1
+#define RG_TURISMO_TRX_WF_N_RX_EN_LOOPA_MSK 0x00200000
+#define RG_TURISMO_TRX_WF_N_RX_EN_LOOPA_I_MSK 0xffdfffff
+#define RG_TURISMO_TRX_WF_N_RX_EN_LOOPA_SFT 21
+#define RG_TURISMO_TRX_WF_N_RX_EN_LOOPA_HI 21
+#define RG_TURISMO_TRX_WF_N_RX_EN_LOOPA_SZ 1
+#define RG_TURISMO_TRX_WF_N_RX_FILTERVCM_MSK 0x07000000
+#define RG_TURISMO_TRX_WF_N_RX_FILTERVCM_I_MSK 0xf8ffffff
+#define RG_TURISMO_TRX_WF_N_RX_FILTERVCM_SFT 24
+#define RG_TURISMO_TRX_WF_N_RX_FILTERVCM_HI 26
+#define RG_TURISMO_TRX_WF_N_RX_FILTERVCM_SZ 3
+#define RG_TURISMO_TRX_WF_N_RX_OUTVCM_MSK 0x70000000
+#define RG_TURISMO_TRX_WF_N_RX_OUTVCM_I_MSK 0x8fffffff
+#define RG_TURISMO_TRX_WF_N_RX_OUTVCM_SFT 28
+#define RG_TURISMO_TRX_WF_N_RX_OUTVCM_HI 30
+#define RG_TURISMO_TRX_WF_N_RX_OUTVCM_SZ 3
+#define RG_TURISMO_TRX_BT_RX_ABBCTUNE_MSK 0x0000003f
+#define RG_TURISMO_TRX_BT_RX_ABBCTUNE_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_BT_RX_ABBCTUNE_SFT 0
+#define RG_TURISMO_TRX_BT_RX_ABBCTUNE_HI 5
+#define RG_TURISMO_TRX_BT_RX_ABBCTUNE_SZ 6
+#define RG_TURISMO_TRX_BT_RX_FILTERI_COARSE_MSK 0x00000300
+#define RG_TURISMO_TRX_BT_RX_FILTERI_COARSE_I_MSK 0xfffffcff
+#define RG_TURISMO_TRX_BT_RX_FILTERI_COARSE_SFT 8
+#define RG_TURISMO_TRX_BT_RX_FILTERI_COARSE_HI 9
+#define RG_TURISMO_TRX_BT_RX_FILTERI_COARSE_SZ 2
+#define RG_TURISMO_TRX_BT_RX_FILTERI1ST_MSK 0x00000c00
+#define RG_TURISMO_TRX_BT_RX_FILTERI1ST_I_MSK 0xfffff3ff
+#define RG_TURISMO_TRX_BT_RX_FILTERI1ST_SFT 10
+#define RG_TURISMO_TRX_BT_RX_FILTERI1ST_HI 11
+#define RG_TURISMO_TRX_BT_RX_FILTERI1ST_SZ 2
+#define RG_TURISMO_TRX_BT_RX_FILTERI2ND_MSK 0x00003000
+#define RG_TURISMO_TRX_BT_RX_FILTERI2ND_I_MSK 0xffffcfff
+#define RG_TURISMO_TRX_BT_RX_FILTERI2ND_SFT 12
+#define RG_TURISMO_TRX_BT_RX_FILTERI2ND_HI 13
+#define RG_TURISMO_TRX_BT_RX_FILTERI2ND_SZ 2
+#define RG_TURISMO_TRX_BT_RX_FILTERI3RD_MSK 0x0000c000
+#define RG_TURISMO_TRX_BT_RX_FILTERI3RD_I_MSK 0xffff3fff
+#define RG_TURISMO_TRX_BT_RX_FILTERI3RD_SFT 14
+#define RG_TURISMO_TRX_BT_RX_FILTERI3RD_HI 15
+#define RG_TURISMO_TRX_BT_RX_FILTERI3RD_SZ 2
+#define RG_TURISMO_TRX_BT_RX_ABBCFIX_MSK 0x00010000
+#define RG_TURISMO_TRX_BT_RX_ABBCFIX_I_MSK 0xfffeffff
+#define RG_TURISMO_TRX_BT_RX_ABBCFIX_SFT 16
+#define RG_TURISMO_TRX_BT_RX_ABBCFIX_HI 16
+#define RG_TURISMO_TRX_BT_RX_ABBCFIX_SZ 1
+#define RG_TURISMO_TRX_BT_RX_ABB_N_MODE_MSK 0x00020000
+#define RG_TURISMO_TRX_BT_RX_ABB_N_MODE_I_MSK 0xfffdffff
+#define RG_TURISMO_TRX_BT_RX_ABB_N_MODE_SFT 17
+#define RG_TURISMO_TRX_BT_RX_ABB_N_MODE_HI 17
+#define RG_TURISMO_TRX_BT_RX_ABB_N_MODE_SZ 1
+#define RG_TURISMO_TRX_BT_RX_ABB_BT_MODE_MSK 0x00040000
+#define RG_TURISMO_TRX_BT_RX_ABB_BT_MODE_I_MSK 0xfffbffff
+#define RG_TURISMO_TRX_BT_RX_ABB_BT_MODE_SFT 18
+#define RG_TURISMO_TRX_BT_RX_ABB_BT_MODE_HI 18
+#define RG_TURISMO_TRX_BT_RX_ABB_BT_MODE_SZ 1
+#define RG_TURISMO_TRX_BT_RX_ABB_IDIV3_MSK 0x00080000
+#define RG_TURISMO_TRX_BT_RX_ABB_IDIV3_I_MSK 0xfff7ffff
+#define RG_TURISMO_TRX_BT_RX_ABB_IDIV3_SFT 19
+#define RG_TURISMO_TRX_BT_RX_ABB_IDIV3_HI 19
+#define RG_TURISMO_TRX_BT_RX_ABB_IDIV3_SZ 1
+#define RG_TURISMO_TRX_BT_RX_EN_IDACA_COARSE_MSK 0x00100000
+#define RG_TURISMO_TRX_BT_RX_EN_IDACA_COARSE_I_MSK 0xffefffff
+#define RG_TURISMO_TRX_BT_RX_EN_IDACA_COARSE_SFT 20
+#define RG_TURISMO_TRX_BT_RX_EN_IDACA_COARSE_HI 20
+#define RG_TURISMO_TRX_BT_RX_EN_IDACA_COARSE_SZ 1
+#define RG_TURISMO_TRX_BT_RX_EN_LOOPA_MSK 0x00200000
+#define RG_TURISMO_TRX_BT_RX_EN_LOOPA_I_MSK 0xffdfffff
+#define RG_TURISMO_TRX_BT_RX_EN_LOOPA_SFT 21
+#define RG_TURISMO_TRX_BT_RX_EN_LOOPA_HI 21
+#define RG_TURISMO_TRX_BT_RX_EN_LOOPA_SZ 1
+#define RG_TURISMO_TRX_BT_RX_FILTERVCM_MSK 0x07000000
+#define RG_TURISMO_TRX_BT_RX_FILTERVCM_I_MSK 0xf8ffffff
+#define RG_TURISMO_TRX_BT_RX_FILTERVCM_SFT 24
+#define RG_TURISMO_TRX_BT_RX_FILTERVCM_HI 26
+#define RG_TURISMO_TRX_BT_RX_FILTERVCM_SZ 3
+#define RG_TURISMO_TRX_BT_RX_OUTVCM_MSK 0x70000000
+#define RG_TURISMO_TRX_BT_RX_OUTVCM_I_MSK 0x8fffffff
+#define RG_TURISMO_TRX_BT_RX_OUTVCM_SFT 28
+#define RG_TURISMO_TRX_BT_RX_OUTVCM_HI 30
+#define RG_TURISMO_TRX_BT_RX_OUTVCM_SZ 3
+#define RG_TURISMO_TRX_RX_ADCRSSI_VCM_MSK 0x00000003
+#define RG_TURISMO_TRX_RX_ADCRSSI_VCM_I_MSK 0xfffffffc
+#define RG_TURISMO_TRX_RX_ADCRSSI_VCM_SFT 0
+#define RG_TURISMO_TRX_RX_ADCRSSI_VCM_HI 1
+#define RG_TURISMO_TRX_RX_ADCRSSI_VCM_SZ 2
+#define RG_TURISMO_TRX_RX_REC_LPFCORNER_MSK 0x0000000c
+#define RG_TURISMO_TRX_RX_REC_LPFCORNER_I_MSK 0xfffffff3
+#define RG_TURISMO_TRX_RX_REC_LPFCORNER_SFT 2
+#define RG_TURISMO_TRX_RX_REC_LPFCORNER_HI 3
+#define RG_TURISMO_TRX_RX_REC_LPFCORNER_SZ 2
+#define RG_TURISMO_TRX_RX_ADCRSSI_CLKSEL_MSK 0x00000010
+#define RG_TURISMO_TRX_RX_ADCRSSI_CLKSEL_I_MSK 0xffffffef
+#define RG_TURISMO_TRX_RX_ADCRSSI_CLKSEL_SFT 4
+#define RG_TURISMO_TRX_RX_ADCRSSI_CLKSEL_HI 4
+#define RG_TURISMO_TRX_RX_ADCRSSI_CLKSEL_SZ 1
+#define RG_TURISMO_TRX_RSSI_CLOCK_GATING_MSK 0x00000020
+#define RG_TURISMO_TRX_RSSI_CLOCK_GATING_I_MSK 0xffffffdf
+#define RG_TURISMO_TRX_RSSI_CLOCK_GATING_SFT 5
+#define RG_TURISMO_TRX_RSSI_CLOCK_GATING_HI 5
+#define RG_TURISMO_TRX_RSSI_CLOCK_GATING_SZ 1
+#define RG_TURISMO_TRX_RX_IDACA_COARSE_PMOS_ON_MSK 0x00000040
+#define RG_TURISMO_TRX_RX_IDACA_COARSE_PMOS_ON_I_MSK 0xffffffbf
+#define RG_TURISMO_TRX_RX_IDACA_COARSE_PMOS_ON_SFT 6
+#define RG_TURISMO_TRX_RX_IDACA_COARSE_PMOS_ON_HI 6
+#define RG_TURISMO_TRX_RX_IDACA_COARSE_PMOS_ON_SZ 1
+#define RG_TURISMO_TRX_TX_DPDGM_BIAS_MSK 0x00000f00
+#define RG_TURISMO_TRX_TX_DPDGM_BIAS_I_MSK 0xfffff0ff
+#define RG_TURISMO_TRX_TX_DPDGM_BIAS_SFT 8
+#define RG_TURISMO_TRX_TX_DPDGM_BIAS_HI 11
+#define RG_TURISMO_TRX_TX_DPDGM_BIAS_SZ 4
+#define RG_TURISMO_TRX_TX_DPD_DIV_MSK 0x0000f000
+#define RG_TURISMO_TRX_TX_DPD_DIV_I_MSK 0xffff0fff
+#define RG_TURISMO_TRX_TX_DPD_DIV_SFT 12
+#define RG_TURISMO_TRX_TX_DPD_DIV_HI 15
+#define RG_TURISMO_TRX_TX_DPD_DIV_SZ 4
+#define RG_TURISMO_TRX_TX_TSSI_BIAS_MSK 0x00070000
+#define RG_TURISMO_TRX_TX_TSSI_BIAS_I_MSK 0xfff8ffff
+#define RG_TURISMO_TRX_TX_TSSI_BIAS_SFT 16
+#define RG_TURISMO_TRX_TX_TSSI_BIAS_HI 18
+#define RG_TURISMO_TRX_TX_TSSI_BIAS_SZ 3
+#define RG_TURISMO_TRX_TX_TSSI_DIV_MSK 0x00380000
+#define RG_TURISMO_TRX_TX_TSSI_DIV_I_MSK 0xffc7ffff
+#define RG_TURISMO_TRX_TX_TSSI_DIV_SFT 19
+#define RG_TURISMO_TRX_TX_TSSI_DIV_HI 21
+#define RG_TURISMO_TRX_TX_TSSI_DIV_SZ 3
+#define RG_TURISMO_TRX_TX_TSSI_TEST_MSK 0x00c00000
+#define RG_TURISMO_TRX_TX_TSSI_TEST_I_MSK 0xff3fffff
+#define RG_TURISMO_TRX_TX_TSSI_TEST_SFT 22
+#define RG_TURISMO_TRX_TX_TSSI_TEST_HI 23
+#define RG_TURISMO_TRX_TX_TSSI_TEST_SZ 2
+#define RG_TURISMO_TRX_TX_TSSI_TESTMODE_MSK 0x01000000
+#define RG_TURISMO_TRX_TX_TSSI_TESTMODE_I_MSK 0xfeffffff
+#define RG_TURISMO_TRX_TX_TSSI_TESTMODE_SFT 24
+#define RG_TURISMO_TRX_TX_TSSI_TESTMODE_HI 24
+#define RG_TURISMO_TRX_TX_TSSI_TESTMODE_SZ 1
+#define RG_TURISMO_TRX_EN_RX_RSSI_TESTNODE_MSK 0x0e000000
+#define RG_TURISMO_TRX_EN_RX_RSSI_TESTNODE_I_MSK 0xf1ffffff
+#define RG_TURISMO_TRX_EN_RX_RSSI_TESTNODE_SFT 25
+#define RG_TURISMO_TRX_EN_RX_RSSI_TESTNODE_HI 27
+#define RG_TURISMO_TRX_EN_RX_RSSI_TESTNODE_SZ 3
+#define RG_TURISMO_TRX_RX_LNA_TRI_SEL_MSK 0x30000000
+#define RG_TURISMO_TRX_RX_LNA_TRI_SEL_I_MSK 0xcfffffff
+#define RG_TURISMO_TRX_RX_LNA_TRI_SEL_SFT 28
+#define RG_TURISMO_TRX_RX_LNA_TRI_SEL_HI 29
+#define RG_TURISMO_TRX_RX_LNA_TRI_SEL_SZ 2
+#define RG_TURISMO_TRX_RX_LNA_SETTLE_MSK 0xc0000000
+#define RG_TURISMO_TRX_RX_LNA_SETTLE_I_MSK 0x3fffffff
+#define RG_TURISMO_TRX_RX_LNA_SETTLE_SFT 30
+#define RG_TURISMO_TRX_RX_LNA_SETTLE_HI 31
+#define RG_TURISMO_TRX_RX_LNA_SETTLE_SZ 2
+#define RG_TURISMO_TRX_WF_TXPGA_CAPSW_MSK 0x00000003
+#define RG_TURISMO_TRX_WF_TXPGA_CAPSW_I_MSK 0xfffffffc
+#define RG_TURISMO_TRX_WF_TXPGA_CAPSW_SFT 0
+#define RG_TURISMO_TRX_WF_TXPGA_CAPSW_HI 1
+#define RG_TURISMO_TRX_WF_TXPGA_CAPSW_SZ 2
+#define RG_TURISMO_TRX_WF_TX_DIV_VSET_MSK 0x0000000c
+#define RG_TURISMO_TRX_WF_TX_DIV_VSET_I_MSK 0xfffffff3
+#define RG_TURISMO_TRX_WF_TX_DIV_VSET_SFT 2
+#define RG_TURISMO_TRX_WF_TX_DIV_VSET_HI 3
+#define RG_TURISMO_TRX_WF_TX_DIV_VSET_SZ 2
+#define RG_TURISMO_TRX_WF_TX_LOBUF_VSET_MSK 0x00000030
+#define RG_TURISMO_TRX_WF_TX_LOBUF_VSET_I_MSK 0xffffffcf
+#define RG_TURISMO_TRX_WF_TX_LOBUF_VSET_SFT 4
+#define RG_TURISMO_TRX_WF_TX_LOBUF_VSET_HI 5
+#define RG_TURISMO_TRX_WF_TX_LOBUF_VSET_SZ 2
+#define RG_TURISMO_TRX_WF_TX_BTPASW_MSK 0x00000040
+#define RG_TURISMO_TRX_WF_TX_BTPASW_I_MSK 0xffffffbf
+#define RG_TURISMO_TRX_WF_TX_BTPASW_SFT 6
+#define RG_TURISMO_TRX_WF_TX_BTPASW_HI 6
+#define RG_TURISMO_TRX_WF_TX_BTPASW_SZ 1
+#define RG_TURISMO_TRX_WF_EN_TX_PA_VIN33_MSK 0x00000080
+#define RG_TURISMO_TRX_WF_EN_TX_PA_VIN33_I_MSK 0xffffff7f
+#define RG_TURISMO_TRX_WF_EN_TX_PA_VIN33_SFT 7
+#define RG_TURISMO_TRX_WF_EN_TX_PA_VIN33_HI 7
+#define RG_TURISMO_TRX_WF_EN_TX_PA_VIN33_SZ 1
+#define RG_TURISMO_TRX_BT_TXPGA_CAPSW_MSK 0x00003000
+#define RG_TURISMO_TRX_BT_TXPGA_CAPSW_I_MSK 0xffffcfff
+#define RG_TURISMO_TRX_BT_TXPGA_CAPSW_SFT 12
+#define RG_TURISMO_TRX_BT_TXPGA_CAPSW_HI 13
+#define RG_TURISMO_TRX_BT_TXPGA_CAPSW_SZ 2
+#define RG_TURISMO_TRX_BT_TX_DIV_VSET_MSK 0x0000c000
+#define RG_TURISMO_TRX_BT_TX_DIV_VSET_I_MSK 0xffff3fff
+#define RG_TURISMO_TRX_BT_TX_DIV_VSET_SFT 14
+#define RG_TURISMO_TRX_BT_TX_DIV_VSET_HI 15
+#define RG_TURISMO_TRX_BT_TX_DIV_VSET_SZ 2
+#define RG_TURISMO_TRX_BT_TX_LOBUF_VSET_MSK 0x00030000
+#define RG_TURISMO_TRX_BT_TX_LOBUF_VSET_I_MSK 0xfffcffff
+#define RG_TURISMO_TRX_BT_TX_LOBUF_VSET_SFT 16
+#define RG_TURISMO_TRX_BT_TX_LOBUF_VSET_HI 17
+#define RG_TURISMO_TRX_BT_TX_LOBUF_VSET_SZ 2
+#define RG_TURISMO_TRX_BT_TX_BTPASW_MSK 0x00040000
+#define RG_TURISMO_TRX_BT_TX_BTPASW_I_MSK 0xfffbffff
+#define RG_TURISMO_TRX_BT_TX_BTPASW_SFT 18
+#define RG_TURISMO_TRX_BT_TX_BTPASW_HI 18
+#define RG_TURISMO_TRX_BT_TX_BTPASW_SZ 1
+#define RG_TURISMO_TRX_BT_EN_TX_PA_VIN33_MSK 0x00080000
+#define RG_TURISMO_TRX_BT_EN_TX_PA_VIN33_I_MSK 0xfff7ffff
+#define RG_TURISMO_TRX_BT_EN_TX_PA_VIN33_SFT 19
+#define RG_TURISMO_TRX_BT_EN_TX_PA_VIN33_HI 19
+#define RG_TURISMO_TRX_BT_EN_TX_PA_VIN33_SZ 1
+#define RG_TURISMO_TRX_TX_PA_LDO_SEL_RES_MSK 0x03000000
+#define RG_TURISMO_TRX_TX_PA_LDO_SEL_RES_I_MSK 0xfcffffff
+#define RG_TURISMO_TRX_TX_PA_LDO_SEL_RES_SFT 24
+#define RG_TURISMO_TRX_TX_PA_LDO_SEL_RES_HI 25
+#define RG_TURISMO_TRX_TX_PA_LDO_SEL_RES_SZ 2
+#define RG_TURISMO_TRX_EN_LDO_TX_PA_MSK 0x04000000
+#define RG_TURISMO_TRX_EN_LDO_TX_PA_I_MSK 0xfbffffff
+#define RG_TURISMO_TRX_EN_LDO_TX_PA_SFT 26
+#define RG_TURISMO_TRX_EN_LDO_TX_PA_HI 26
+#define RG_TURISMO_TRX_EN_LDO_TX_PA_SZ 1
+#define RG_TURISMO_TRX_EN_TX_PA_LDO_FC_MSK 0x08000000
+#define RG_TURISMO_TRX_EN_TX_PA_LDO_FC_I_MSK 0xf7ffffff
+#define RG_TURISMO_TRX_EN_TX_PA_LDO_FC_SFT 27
+#define RG_TURISMO_TRX_EN_TX_PA_LDO_FC_HI 27
+#define RG_TURISMO_TRX_EN_TX_PA_LDO_FC_SZ 1
+#define RG_TURISMO_TRX_EN_TX_PA_LDO_IQUP_MSK 0x10000000
+#define RG_TURISMO_TRX_EN_TX_PA_LDO_IQUP_I_MSK 0xefffffff
+#define RG_TURISMO_TRX_EN_TX_PA_LDO_IQUP_SFT 28
+#define RG_TURISMO_TRX_EN_TX_PA_LDO_IQUP_HI 28
+#define RG_TURISMO_TRX_EN_TX_PA_LDO_IQUP_SZ 1
+#define RG_TURISMO_TRX_EN_TX_PA_LDO_VTH_MSK 0x20000000
+#define RG_TURISMO_TRX_EN_TX_PA_LDO_VTH_I_MSK 0xdfffffff
+#define RG_TURISMO_TRX_EN_TX_PA_LDO_VTH_SFT 29
+#define RG_TURISMO_TRX_EN_TX_PA_LDO_VTH_HI 29
+#define RG_TURISMO_TRX_EN_TX_PA_LDO_VTH_SZ 1
+#define RG_TURISMO_TRX_WF_PACELL_EN_MSK 0x00000007
+#define RG_TURISMO_TRX_WF_PACELL_EN_I_MSK 0xfffffff8
+#define RG_TURISMO_TRX_WF_PACELL_EN_SFT 0
+#define RG_TURISMO_TRX_WF_PACELL_EN_HI 2
+#define RG_TURISMO_TRX_WF_PACELL_EN_SZ 3
+#define RG_TURISMO_TRX_WF_PABIAS_CTRL_MSK 0x000000f0
+#define RG_TURISMO_TRX_WF_PABIAS_CTRL_I_MSK 0xffffff0f
+#define RG_TURISMO_TRX_WF_PABIAS_CTRL_SFT 4
+#define RG_TURISMO_TRX_WF_PABIAS_CTRL_HI 7
+#define RG_TURISMO_TRX_WF_PABIAS_CTRL_SZ 4
+#define RG_TURISMO_TRX_WF_TX_PA1_VCAS_MSK 0x00000700
+#define RG_TURISMO_TRX_WF_TX_PA1_VCAS_I_MSK 0xfffff8ff
+#define RG_TURISMO_TRX_WF_TX_PA1_VCAS_SFT 8
+#define RG_TURISMO_TRX_WF_TX_PA1_VCAS_HI 10
+#define RG_TURISMO_TRX_WF_TX_PA1_VCAS_SZ 3
+#define RG_TURISMO_TRX_WF_TX_PA2_VCAS_MSK 0x00007000
+#define RG_TURISMO_TRX_WF_TX_PA2_VCAS_I_MSK 0xffff8fff
+#define RG_TURISMO_TRX_WF_TX_PA2_VCAS_SFT 12
+#define RG_TURISMO_TRX_WF_TX_PA2_VCAS_HI 14
+#define RG_TURISMO_TRX_WF_TX_PA2_VCAS_SZ 3
+#define RG_TURISMO_TRX_WF_TX_PA3_VCAS_MSK 0x00070000
+#define RG_TURISMO_TRX_WF_TX_PA3_VCAS_I_MSK 0xfff8ffff
+#define RG_TURISMO_TRX_WF_TX_PA3_VCAS_SFT 16
+#define RG_TURISMO_TRX_WF_TX_PA3_VCAS_HI 18
+#define RG_TURISMO_TRX_WF_TX_PA3_VCAS_SZ 3
+#define RG_TURISMO_TRX_BT_PABIAS_2X_MSK 0x00800000
+#define RG_TURISMO_TRX_BT_PABIAS_2X_I_MSK 0xff7fffff
+#define RG_TURISMO_TRX_BT_PABIAS_2X_SFT 23
+#define RG_TURISMO_TRX_BT_PABIAS_2X_HI 23
+#define RG_TURISMO_TRX_BT_PABIAS_2X_SZ 1
+#define RG_TURISMO_TRX_BT_PABIAS_CTRL_MSK 0x0f000000
+#define RG_TURISMO_TRX_BT_PABIAS_CTRL_I_MSK 0xf0ffffff
+#define RG_TURISMO_TRX_BT_PABIAS_CTRL_SFT 24
+#define RG_TURISMO_TRX_BT_PABIAS_CTRL_HI 27
+#define RG_TURISMO_TRX_BT_PABIAS_CTRL_SZ 4
+#define RG_TURISMO_TRX_BT_TX_PA_VCAS_MSK 0x30000000
+#define RG_TURISMO_TRX_BT_TX_PA_VCAS_I_MSK 0xcfffffff
+#define RG_TURISMO_TRX_BT_TX_PA_VCAS_SFT 28
+#define RG_TURISMO_TRX_BT_TX_PA_VCAS_HI 29
+#define RG_TURISMO_TRX_BT_TX_PA_VCAS_SZ 2
+#define RG_TURISMO_TRX_BT_TX_MOD_CS_MSK 0xc0000000
+#define RG_TURISMO_TRX_BT_TX_MOD_CS_I_MSK 0x3fffffff
+#define RG_TURISMO_TRX_BT_TX_MOD_CS_SFT 30
+#define RG_TURISMO_TRX_BT_TX_MOD_CS_HI 31
+#define RG_TURISMO_TRX_BT_TX_MOD_CS_SZ 2
+#define RG_TURISMO_TRX_TXPGA_MAIN_MSK 0x0000003f
+#define RG_TURISMO_TRX_TXPGA_MAIN_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_TXPGA_MAIN_SFT 0
+#define RG_TURISMO_TRX_TXPGA_MAIN_HI 5
+#define RG_TURISMO_TRX_TXPGA_MAIN_SZ 6
+#define RG_TURISMO_TRX_TXPGA_STEER_MSK 0x00000fc0
+#define RG_TURISMO_TRX_TXPGA_STEER_I_MSK 0xfffff03f
+#define RG_TURISMO_TRX_TXPGA_STEER_SFT 6
+#define RG_TURISMO_TRX_TXPGA_STEER_HI 11
+#define RG_TURISMO_TRX_TXPGA_STEER_SZ 6
+#define RG_TURISMO_TRX_TXMOD_GMCELL_MSK 0x00003000
+#define RG_TURISMO_TRX_TXMOD_GMCELL_I_MSK 0xffffcfff
+#define RG_TURISMO_TRX_TXMOD_GMCELL_SFT 12
+#define RG_TURISMO_TRX_TXMOD_GMCELL_HI 13
+#define RG_TURISMO_TRX_TXMOD_GMCELL_SZ 2
+#define RG_TURISMO_TRX_TXLPF_GMCELL_MSK 0x0000c000
+#define RG_TURISMO_TRX_TXLPF_GMCELL_I_MSK 0xffff3fff
+#define RG_TURISMO_TRX_TXLPF_GMCELL_SFT 14
+#define RG_TURISMO_TRX_TXLPF_GMCELL_HI 15
+#define RG_TURISMO_TRX_TXLPF_GMCELL_SZ 2
+#define RG_TURISMO_TRX_WF_TX_GAIN_OFFSET_MSK 0x000f0000
+#define RG_TURISMO_TRX_WF_TX_GAIN_OFFSET_I_MSK 0xfff0ffff
+#define RG_TURISMO_TRX_WF_TX_GAIN_OFFSET_SFT 16
+#define RG_TURISMO_TRX_WF_TX_GAIN_OFFSET_HI 19
+#define RG_TURISMO_TRX_WF_TX_GAIN_OFFSET_SZ 4
+#define RG_TURISMO_TRX_BT_TX_GAIN_OFFSET_MSK 0x00f00000
+#define RG_TURISMO_TRX_BT_TX_GAIN_OFFSET_I_MSK 0xff0fffff
+#define RG_TURISMO_TRX_BT_TX_GAIN_OFFSET_SFT 20
+#define RG_TURISMO_TRX_BT_TX_GAIN_OFFSET_HI 23
+#define RG_TURISMO_TRX_BT_TX_GAIN_OFFSET_SZ 4
+#define RG_TURISMO_TRX_TX_VTOI_CURRENT_MSK 0x03000000
+#define RG_TURISMO_TRX_TX_VTOI_CURRENT_I_MSK 0xfcffffff
+#define RG_TURISMO_TRX_TX_VTOI_CURRENT_SFT 24
+#define RG_TURISMO_TRX_TX_VTOI_CURRENT_HI 25
+#define RG_TURISMO_TRX_TX_VTOI_CURRENT_SZ 2
+#define RG_TURISMO_TRX_TX_VTOI_GM_MSK 0x0c000000
+#define RG_TURISMO_TRX_TX_VTOI_GM_I_MSK 0xf3ffffff
+#define RG_TURISMO_TRX_TX_VTOI_GM_SFT 26
+#define RG_TURISMO_TRX_TX_VTOI_GM_HI 27
+#define RG_TURISMO_TRX_TX_VTOI_GM_SZ 2
+#define RG_TURISMO_TRX_TX_VTOI_OPTION_MSK 0x30000000
+#define RG_TURISMO_TRX_TX_VTOI_OPTION_I_MSK 0xcfffffff
+#define RG_TURISMO_TRX_TX_VTOI_OPTION_SFT 28
+#define RG_TURISMO_TRX_TX_VTOI_OPTION_HI 29
+#define RG_TURISMO_TRX_TX_VTOI_OPTION_SZ 2
+#define RG_TURISMO_TRX_TX_VTOI_FS_MSK 0x40000000
+#define RG_TURISMO_TRX_TX_VTOI_FS_I_MSK 0xbfffffff
+#define RG_TURISMO_TRX_TX_VTOI_FS_SFT 30
+#define RG_TURISMO_TRX_TX_VTOI_FS_HI 30
+#define RG_TURISMO_TRX_TX_VTOI_FS_SZ 1
+#define RG_TURISMO_TRX_WF_RX_HG_LNA_GC_MSK 0x00000003
+#define RG_TURISMO_TRX_WF_RX_HG_LNA_GC_I_MSK 0xfffffffc
+#define RG_TURISMO_TRX_WF_RX_HG_LNA_GC_SFT 0
+#define RG_TURISMO_TRX_WF_RX_HG_LNA_GC_HI 1
+#define RG_TURISMO_TRX_WF_RX_HG_LNA_GC_SZ 2
+#define RG_TURISMO_TRX_WF_RX_HG_TZ_GC_MSK 0x0000000c
+#define RG_TURISMO_TRX_WF_RX_HG_TZ_GC_I_MSK 0xfffffff3
+#define RG_TURISMO_TRX_WF_RX_HG_TZ_GC_SFT 2
+#define RG_TURISMO_TRX_WF_RX_HG_TZ_GC_HI 3
+#define RG_TURISMO_TRX_WF_RX_HG_TZ_GC_SZ 2
+#define RG_TURISMO_TRX_WF_RX_HG_LNAHGN_BIAS_MSK 0x000000f0
+#define RG_TURISMO_TRX_WF_RX_HG_LNAHGN_BIAS_I_MSK 0xffffff0f
+#define RG_TURISMO_TRX_WF_RX_HG_LNAHGN_BIAS_SFT 4
+#define RG_TURISMO_TRX_WF_RX_HG_LNAHGN_BIAS_HI 7
+#define RG_TURISMO_TRX_WF_RX_HG_LNAHGN_BIAS_SZ 4
+#define RG_TURISMO_TRX_WF_RX_HG_LNAHGP_BIAS_MSK 0x00000f00
+#define RG_TURISMO_TRX_WF_RX_HG_LNAHGP_BIAS_I_MSK 0xfffff0ff
+#define RG_TURISMO_TRX_WF_RX_HG_LNAHGP_BIAS_SFT 8
+#define RG_TURISMO_TRX_WF_RX_HG_LNAHGP_BIAS_HI 11
+#define RG_TURISMO_TRX_WF_RX_HG_LNAHGP_BIAS_SZ 4
+#define RG_TURISMO_TRX_WF_RX_HG_LNALG_BIAS_MSK 0x0000f000
+#define RG_TURISMO_TRX_WF_RX_HG_LNALG_BIAS_I_MSK 0xffff0fff
+#define RG_TURISMO_TRX_WF_RX_HG_LNALG_BIAS_SFT 12
+#define RG_TURISMO_TRX_WF_RX_HG_LNALG_BIAS_HI 15
+#define RG_TURISMO_TRX_WF_RX_HG_LNALG_BIAS_SZ 4
+#define RG_TURISMO_TRX_WF_RX_HG_TZ_CAP_MSK 0x00070000
+#define RG_TURISMO_TRX_WF_RX_HG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_TURISMO_TRX_WF_RX_HG_TZ_CAP_SFT 16
+#define RG_TURISMO_TRX_WF_RX_HG_TZ_CAP_HI 18
+#define RG_TURISMO_TRX_WF_RX_HG_TZ_CAP_SZ 3
+#define RG_TURISMO_TRX_WF_RX_HG_TZ_GC_BOOST_MSK 0x00300000
+#define RG_TURISMO_TRX_WF_RX_HG_TZ_GC_BOOST_I_MSK 0xffcfffff
+#define RG_TURISMO_TRX_WF_RX_HG_TZ_GC_BOOST_SFT 20
+#define RG_TURISMO_TRX_WF_RX_HG_TZ_GC_BOOST_HI 21
+#define RG_TURISMO_TRX_WF_RX_HG_TZ_GC_BOOST_SZ 2
+#define RG_TURISMO_TRX_WF_RX_HG_DIV2_CORE_MSK 0x00c00000
+#define RG_TURISMO_TRX_WF_RX_HG_DIV2_CORE_I_MSK 0xff3fffff
+#define RG_TURISMO_TRX_WF_RX_HG_DIV2_CORE_SFT 22
+#define RG_TURISMO_TRX_WF_RX_HG_DIV2_CORE_HI 23
+#define RG_TURISMO_TRX_WF_RX_HG_DIV2_CORE_SZ 2
+#define RG_TURISMO_TRX_WF_RX_HG_LOBUF_MSK 0x03000000
+#define RG_TURISMO_TRX_WF_RX_HG_LOBUF_I_MSK 0xfcffffff
+#define RG_TURISMO_TRX_WF_RX_HG_LOBUF_SFT 24
+#define RG_TURISMO_TRX_WF_RX_HG_LOBUF_HI 25
+#define RG_TURISMO_TRX_WF_RX_HG_LOBUF_SZ 2
+#define RG_TURISMO_TRX_WF_RX_HG_TZI_MSK 0x1c000000
+#define RG_TURISMO_TRX_WF_RX_HG_TZI_I_MSK 0xe3ffffff
+#define RG_TURISMO_TRX_WF_RX_HG_TZI_SFT 26
+#define RG_TURISMO_TRX_WF_RX_HG_TZI_HI 28
+#define RG_TURISMO_TRX_WF_RX_HG_TZI_SZ 3
+#define RG_TURISMO_TRX_WF_RX_HG_TZ_VCM_MSK 0xe0000000
+#define RG_TURISMO_TRX_WF_RX_HG_TZ_VCM_I_MSK 0x1fffffff
+#define RG_TURISMO_TRX_WF_RX_HG_TZ_VCM_SFT 29
+#define RG_TURISMO_TRX_WF_RX_HG_TZ_VCM_HI 31
+#define RG_TURISMO_TRX_WF_RX_HG_TZ_VCM_SZ 3
+#define RG_TURISMO_TRX_WF_RX_MG_LNA_GC_MSK 0x00000003
+#define RG_TURISMO_TRX_WF_RX_MG_LNA_GC_I_MSK 0xfffffffc
+#define RG_TURISMO_TRX_WF_RX_MG_LNA_GC_SFT 0
+#define RG_TURISMO_TRX_WF_RX_MG_LNA_GC_HI 1
+#define RG_TURISMO_TRX_WF_RX_MG_LNA_GC_SZ 2
+#define RG_TURISMO_TRX_WF_RX_MG_TZ_GC_MSK 0x0000000c
+#define RG_TURISMO_TRX_WF_RX_MG_TZ_GC_I_MSK 0xfffffff3
+#define RG_TURISMO_TRX_WF_RX_MG_TZ_GC_SFT 2
+#define RG_TURISMO_TRX_WF_RX_MG_TZ_GC_HI 3
+#define RG_TURISMO_TRX_WF_RX_MG_TZ_GC_SZ 2
+#define RG_TURISMO_TRX_WF_RX_MG_LNAHGN_BIAS_MSK 0x000000f0
+#define RG_TURISMO_TRX_WF_RX_MG_LNAHGN_BIAS_I_MSK 0xffffff0f
+#define RG_TURISMO_TRX_WF_RX_MG_LNAHGN_BIAS_SFT 4
+#define RG_TURISMO_TRX_WF_RX_MG_LNAHGN_BIAS_HI 7
+#define RG_TURISMO_TRX_WF_RX_MG_LNAHGN_BIAS_SZ 4
+#define RG_TURISMO_TRX_WF_RX_MG_LNAHGP_BIAS_MSK 0x00000f00
+#define RG_TURISMO_TRX_WF_RX_MG_LNAHGP_BIAS_I_MSK 0xfffff0ff
+#define RG_TURISMO_TRX_WF_RX_MG_LNAHGP_BIAS_SFT 8
+#define RG_TURISMO_TRX_WF_RX_MG_LNAHGP_BIAS_HI 11
+#define RG_TURISMO_TRX_WF_RX_MG_LNAHGP_BIAS_SZ 4
+#define RG_TURISMO_TRX_WF_RX_MG_LNALG_BIAS_MSK 0x0000f000
+#define RG_TURISMO_TRX_WF_RX_MG_LNALG_BIAS_I_MSK 0xffff0fff
+#define RG_TURISMO_TRX_WF_RX_MG_LNALG_BIAS_SFT 12
+#define RG_TURISMO_TRX_WF_RX_MG_LNALG_BIAS_HI 15
+#define RG_TURISMO_TRX_WF_RX_MG_LNALG_BIAS_SZ 4
+#define RG_TURISMO_TRX_WF_RX_MG_TZ_CAP_MSK 0x00070000
+#define RG_TURISMO_TRX_WF_RX_MG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_TURISMO_TRX_WF_RX_MG_TZ_CAP_SFT 16
+#define RG_TURISMO_TRX_WF_RX_MG_TZ_CAP_HI 18
+#define RG_TURISMO_TRX_WF_RX_MG_TZ_CAP_SZ 3
+#define RG_TURISMO_TRX_WF_RX_MG_TZ_GC_BOOST_MSK 0x00300000
+#define RG_TURISMO_TRX_WF_RX_MG_TZ_GC_BOOST_I_MSK 0xffcfffff
+#define RG_TURISMO_TRX_WF_RX_MG_TZ_GC_BOOST_SFT 20
+#define RG_TURISMO_TRX_WF_RX_MG_TZ_GC_BOOST_HI 21
+#define RG_TURISMO_TRX_WF_RX_MG_TZ_GC_BOOST_SZ 2
+#define RG_TURISMO_TRX_WF_RX_MG_DIV2_CORE_MSK 0x00c00000
+#define RG_TURISMO_TRX_WF_RX_MG_DIV2_CORE_I_MSK 0xff3fffff
+#define RG_TURISMO_TRX_WF_RX_MG_DIV2_CORE_SFT 22
+#define RG_TURISMO_TRX_WF_RX_MG_DIV2_CORE_HI 23
+#define RG_TURISMO_TRX_WF_RX_MG_DIV2_CORE_SZ 2
+#define RG_TURISMO_TRX_WF_RX_MG_LOBUF_MSK 0x03000000
+#define RG_TURISMO_TRX_WF_RX_MG_LOBUF_I_MSK 0xfcffffff
+#define RG_TURISMO_TRX_WF_RX_MG_LOBUF_SFT 24
+#define RG_TURISMO_TRX_WF_RX_MG_LOBUF_HI 25
+#define RG_TURISMO_TRX_WF_RX_MG_LOBUF_SZ 2
+#define RG_TURISMO_TRX_WF_RX_MG_TZI_MSK 0x1c000000
+#define RG_TURISMO_TRX_WF_RX_MG_TZI_I_MSK 0xe3ffffff
+#define RG_TURISMO_TRX_WF_RX_MG_TZI_SFT 26
+#define RG_TURISMO_TRX_WF_RX_MG_TZI_HI 28
+#define RG_TURISMO_TRX_WF_RX_MG_TZI_SZ 3
+#define RG_TURISMO_TRX_WF_RX_MG_TZ_VCM_MSK 0xe0000000
+#define RG_TURISMO_TRX_WF_RX_MG_TZ_VCM_I_MSK 0x1fffffff
+#define RG_TURISMO_TRX_WF_RX_MG_TZ_VCM_SFT 29
+#define RG_TURISMO_TRX_WF_RX_MG_TZ_VCM_HI 31
+#define RG_TURISMO_TRX_WF_RX_MG_TZ_VCM_SZ 3
+#define RG_TURISMO_TRX_WF_RX_LG_LNA_GC_MSK 0x00000003
+#define RG_TURISMO_TRX_WF_RX_LG_LNA_GC_I_MSK 0xfffffffc
+#define RG_TURISMO_TRX_WF_RX_LG_LNA_GC_SFT 0
+#define RG_TURISMO_TRX_WF_RX_LG_LNA_GC_HI 1
+#define RG_TURISMO_TRX_WF_RX_LG_LNA_GC_SZ 2
+#define RG_TURISMO_TRX_WF_RX_LG_TZ_GC_MSK 0x0000000c
+#define RG_TURISMO_TRX_WF_RX_LG_TZ_GC_I_MSK 0xfffffff3
+#define RG_TURISMO_TRX_WF_RX_LG_TZ_GC_SFT 2
+#define RG_TURISMO_TRX_WF_RX_LG_TZ_GC_HI 3
+#define RG_TURISMO_TRX_WF_RX_LG_TZ_GC_SZ 2
+#define RG_TURISMO_TRX_WF_RX_LG_LNAHGN_BIAS_MSK 0x000000f0
+#define RG_TURISMO_TRX_WF_RX_LG_LNAHGN_BIAS_I_MSK 0xffffff0f
+#define RG_TURISMO_TRX_WF_RX_LG_LNAHGN_BIAS_SFT 4
+#define RG_TURISMO_TRX_WF_RX_LG_LNAHGN_BIAS_HI 7
+#define RG_TURISMO_TRX_WF_RX_LG_LNAHGN_BIAS_SZ 4
+#define RG_TURISMO_TRX_WF_RX_LG_LNAHGP_BIAS_MSK 0x00000f00
+#define RG_TURISMO_TRX_WF_RX_LG_LNAHGP_BIAS_I_MSK 0xfffff0ff
+#define RG_TURISMO_TRX_WF_RX_LG_LNAHGP_BIAS_SFT 8
+#define RG_TURISMO_TRX_WF_RX_LG_LNAHGP_BIAS_HI 11
+#define RG_TURISMO_TRX_WF_RX_LG_LNAHGP_BIAS_SZ 4
+#define RG_TURISMO_TRX_WF_RX_LG_LNALG_BIAS_MSK 0x0000f000
+#define RG_TURISMO_TRX_WF_RX_LG_LNALG_BIAS_I_MSK 0xffff0fff
+#define RG_TURISMO_TRX_WF_RX_LG_LNALG_BIAS_SFT 12
+#define RG_TURISMO_TRX_WF_RX_LG_LNALG_BIAS_HI 15
+#define RG_TURISMO_TRX_WF_RX_LG_LNALG_BIAS_SZ 4
+#define RG_TURISMO_TRX_WF_RX_LG_TZ_CAP_MSK 0x00070000
+#define RG_TURISMO_TRX_WF_RX_LG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_TURISMO_TRX_WF_RX_LG_TZ_CAP_SFT 16
+#define RG_TURISMO_TRX_WF_RX_LG_TZ_CAP_HI 18
+#define RG_TURISMO_TRX_WF_RX_LG_TZ_CAP_SZ 3
+#define RG_TURISMO_TRX_WF_RX_LG_TZ_GC_BOOST_MSK 0x00300000
+#define RG_TURISMO_TRX_WF_RX_LG_TZ_GC_BOOST_I_MSK 0xffcfffff
+#define RG_TURISMO_TRX_WF_RX_LG_TZ_GC_BOOST_SFT 20
+#define RG_TURISMO_TRX_WF_RX_LG_TZ_GC_BOOST_HI 21
+#define RG_TURISMO_TRX_WF_RX_LG_TZ_GC_BOOST_SZ 2
+#define RG_TURISMO_TRX_WF_RX_LG_DIV2_CORE_MSK 0x00c00000
+#define RG_TURISMO_TRX_WF_RX_LG_DIV2_CORE_I_MSK 0xff3fffff
+#define RG_TURISMO_TRX_WF_RX_LG_DIV2_CORE_SFT 22
+#define RG_TURISMO_TRX_WF_RX_LG_DIV2_CORE_HI 23
+#define RG_TURISMO_TRX_WF_RX_LG_DIV2_CORE_SZ 2
+#define RG_TURISMO_TRX_WF_RX_LG_LOBUF_MSK 0x03000000
+#define RG_TURISMO_TRX_WF_RX_LG_LOBUF_I_MSK 0xfcffffff
+#define RG_TURISMO_TRX_WF_RX_LG_LOBUF_SFT 24
+#define RG_TURISMO_TRX_WF_RX_LG_LOBUF_HI 25
+#define RG_TURISMO_TRX_WF_RX_LG_LOBUF_SZ 2
+#define RG_TURISMO_TRX_WF_RX_LG_TZI_MSK 0x1c000000
+#define RG_TURISMO_TRX_WF_RX_LG_TZI_I_MSK 0xe3ffffff
+#define RG_TURISMO_TRX_WF_RX_LG_TZI_SFT 26
+#define RG_TURISMO_TRX_WF_RX_LG_TZI_HI 28
+#define RG_TURISMO_TRX_WF_RX_LG_TZI_SZ 3
+#define RG_TURISMO_TRX_WF_RX_LG_TZ_VCM_MSK 0xe0000000
+#define RG_TURISMO_TRX_WF_RX_LG_TZ_VCM_I_MSK 0x1fffffff
+#define RG_TURISMO_TRX_WF_RX_LG_TZ_VCM_SFT 29
+#define RG_TURISMO_TRX_WF_RX_LG_TZ_VCM_HI 31
+#define RG_TURISMO_TRX_WF_RX_LG_TZ_VCM_SZ 3
+#define RG_TURISMO_TRX_WF_RX_ULG_LNA_GC_MSK 0x00000003
+#define RG_TURISMO_TRX_WF_RX_ULG_LNA_GC_I_MSK 0xfffffffc
+#define RG_TURISMO_TRX_WF_RX_ULG_LNA_GC_SFT 0
+#define RG_TURISMO_TRX_WF_RX_ULG_LNA_GC_HI 1
+#define RG_TURISMO_TRX_WF_RX_ULG_LNA_GC_SZ 2
+#define RG_TURISMO_TRX_WF_RX_ULG_TZ_GC_MSK 0x0000000c
+#define RG_TURISMO_TRX_WF_RX_ULG_TZ_GC_I_MSK 0xfffffff3
+#define RG_TURISMO_TRX_WF_RX_ULG_TZ_GC_SFT 2
+#define RG_TURISMO_TRX_WF_RX_ULG_TZ_GC_HI 3
+#define RG_TURISMO_TRX_WF_RX_ULG_TZ_GC_SZ 2
+#define RG_TURISMO_TRX_WF_RX_ULG_LNAHGN_BIAS_MSK 0x000000f0
+#define RG_TURISMO_TRX_WF_RX_ULG_LNAHGN_BIAS_I_MSK 0xffffff0f
+#define RG_TURISMO_TRX_WF_RX_ULG_LNAHGN_BIAS_SFT 4
+#define RG_TURISMO_TRX_WF_RX_ULG_LNAHGN_BIAS_HI 7
+#define RG_TURISMO_TRX_WF_RX_ULG_LNAHGN_BIAS_SZ 4
+#define RG_TURISMO_TRX_WF_RX_ULG_LNAHGP_BIAS_MSK 0x00000f00
+#define RG_TURISMO_TRX_WF_RX_ULG_LNAHGP_BIAS_I_MSK 0xfffff0ff
+#define RG_TURISMO_TRX_WF_RX_ULG_LNAHGP_BIAS_SFT 8
+#define RG_TURISMO_TRX_WF_RX_ULG_LNAHGP_BIAS_HI 11
+#define RG_TURISMO_TRX_WF_RX_ULG_LNAHGP_BIAS_SZ 4
+#define RG_TURISMO_TRX_WF_RX_ULG_LNALG_BIAS_MSK 0x0000f000
+#define RG_TURISMO_TRX_WF_RX_ULG_LNALG_BIAS_I_MSK 0xffff0fff
+#define RG_TURISMO_TRX_WF_RX_ULG_LNALG_BIAS_SFT 12
+#define RG_TURISMO_TRX_WF_RX_ULG_LNALG_BIAS_HI 15
+#define RG_TURISMO_TRX_WF_RX_ULG_LNALG_BIAS_SZ 4
+#define RG_TURISMO_TRX_WF_RX_ULG_TZ_CAP_MSK 0x00070000
+#define RG_TURISMO_TRX_WF_RX_ULG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_TURISMO_TRX_WF_RX_ULG_TZ_CAP_SFT 16
+#define RG_TURISMO_TRX_WF_RX_ULG_TZ_CAP_HI 18
+#define RG_TURISMO_TRX_WF_RX_ULG_TZ_CAP_SZ 3
+#define RG_TURISMO_TRX_WF_RX_ULG_TZ_GC_BOOST_MSK 0x00300000
+#define RG_TURISMO_TRX_WF_RX_ULG_TZ_GC_BOOST_I_MSK 0xffcfffff
+#define RG_TURISMO_TRX_WF_RX_ULG_TZ_GC_BOOST_SFT 20
+#define RG_TURISMO_TRX_WF_RX_ULG_TZ_GC_BOOST_HI 21
+#define RG_TURISMO_TRX_WF_RX_ULG_TZ_GC_BOOST_SZ 2
+#define RG_TURISMO_TRX_WF_RX_ULG_DIV2_CORE_MSK 0x00c00000
+#define RG_TURISMO_TRX_WF_RX_ULG_DIV2_CORE_I_MSK 0xff3fffff
+#define RG_TURISMO_TRX_WF_RX_ULG_DIV2_CORE_SFT 22
+#define RG_TURISMO_TRX_WF_RX_ULG_DIV2_CORE_HI 23
+#define RG_TURISMO_TRX_WF_RX_ULG_DIV2_CORE_SZ 2
+#define RG_TURISMO_TRX_WF_RX_ULG_LOBUF_MSK 0x03000000
+#define RG_TURISMO_TRX_WF_RX_ULG_LOBUF_I_MSK 0xfcffffff
+#define RG_TURISMO_TRX_WF_RX_ULG_LOBUF_SFT 24
+#define RG_TURISMO_TRX_WF_RX_ULG_LOBUF_HI 25
+#define RG_TURISMO_TRX_WF_RX_ULG_LOBUF_SZ 2
+#define RG_TURISMO_TRX_WF_RX_ULG_TZI_MSK 0x1c000000
+#define RG_TURISMO_TRX_WF_RX_ULG_TZI_I_MSK 0xe3ffffff
+#define RG_TURISMO_TRX_WF_RX_ULG_TZI_SFT 26
+#define RG_TURISMO_TRX_WF_RX_ULG_TZI_HI 28
+#define RG_TURISMO_TRX_WF_RX_ULG_TZI_SZ 3
+#define RG_TURISMO_TRX_WF_RX_ULG_TZ_VCM_MSK 0xe0000000
+#define RG_TURISMO_TRX_WF_RX_ULG_TZ_VCM_I_MSK 0x1fffffff
+#define RG_TURISMO_TRX_WF_RX_ULG_TZ_VCM_SFT 29
+#define RG_TURISMO_TRX_WF_RX_ULG_TZ_VCM_HI 31
+#define RG_TURISMO_TRX_WF_RX_ULG_TZ_VCM_SZ 3
+#define RG_TURISMO_TRX_BT_RX_HG_LNA_GC_MSK 0x00000003
+#define RG_TURISMO_TRX_BT_RX_HG_LNA_GC_I_MSK 0xfffffffc
+#define RG_TURISMO_TRX_BT_RX_HG_LNA_GC_SFT 0
+#define RG_TURISMO_TRX_BT_RX_HG_LNA_GC_HI 1
+#define RG_TURISMO_TRX_BT_RX_HG_LNA_GC_SZ 2
+#define RG_TURISMO_TRX_BT_RX_HG_TZ_GC_MSK 0x0000000c
+#define RG_TURISMO_TRX_BT_RX_HG_TZ_GC_I_MSK 0xfffffff3
+#define RG_TURISMO_TRX_BT_RX_HG_TZ_GC_SFT 2
+#define RG_TURISMO_TRX_BT_RX_HG_TZ_GC_HI 3
+#define RG_TURISMO_TRX_BT_RX_HG_TZ_GC_SZ 2
+#define RG_TURISMO_TRX_BT_RX_HG_LNAHGN_BIAS_MSK 0x000000f0
+#define RG_TURISMO_TRX_BT_RX_HG_LNAHGN_BIAS_I_MSK 0xffffff0f
+#define RG_TURISMO_TRX_BT_RX_HG_LNAHGN_BIAS_SFT 4
+#define RG_TURISMO_TRX_BT_RX_HG_LNAHGN_BIAS_HI 7
+#define RG_TURISMO_TRX_BT_RX_HG_LNAHGN_BIAS_SZ 4
+#define RG_TURISMO_TRX_BT_RX_HG_LNAHGP_BIAS_MSK 0x00000f00
+#define RG_TURISMO_TRX_BT_RX_HG_LNAHGP_BIAS_I_MSK 0xfffff0ff
+#define RG_TURISMO_TRX_BT_RX_HG_LNAHGP_BIAS_SFT 8
+#define RG_TURISMO_TRX_BT_RX_HG_LNAHGP_BIAS_HI 11
+#define RG_TURISMO_TRX_BT_RX_HG_LNAHGP_BIAS_SZ 4
+#define RG_TURISMO_TRX_BT_RX_HG_LNALG_BIAS_MSK 0x0000f000
+#define RG_TURISMO_TRX_BT_RX_HG_LNALG_BIAS_I_MSK 0xffff0fff
+#define RG_TURISMO_TRX_BT_RX_HG_LNALG_BIAS_SFT 12
+#define RG_TURISMO_TRX_BT_RX_HG_LNALG_BIAS_HI 15
+#define RG_TURISMO_TRX_BT_RX_HG_LNALG_BIAS_SZ 4
+#define RG_TURISMO_TRX_BT_RX_HG_TZ_CAP_MSK 0x00070000
+#define RG_TURISMO_TRX_BT_RX_HG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_TURISMO_TRX_BT_RX_HG_TZ_CAP_SFT 16
+#define RG_TURISMO_TRX_BT_RX_HG_TZ_CAP_HI 18
+#define RG_TURISMO_TRX_BT_RX_HG_TZ_CAP_SZ 3
+#define RG_TURISMO_TRX_BT_RX_HG_TZ_GC_BOOST_MSK 0x00300000
+#define RG_TURISMO_TRX_BT_RX_HG_TZ_GC_BOOST_I_MSK 0xffcfffff
+#define RG_TURISMO_TRX_BT_RX_HG_TZ_GC_BOOST_SFT 20
+#define RG_TURISMO_TRX_BT_RX_HG_TZ_GC_BOOST_HI 21
+#define RG_TURISMO_TRX_BT_RX_HG_TZ_GC_BOOST_SZ 2
+#define RG_TURISMO_TRX_BT_RX_HG_DIV2_CORE_MSK 0x00c00000
+#define RG_TURISMO_TRX_BT_RX_HG_DIV2_CORE_I_MSK 0xff3fffff
+#define RG_TURISMO_TRX_BT_RX_HG_DIV2_CORE_SFT 22
+#define RG_TURISMO_TRX_BT_RX_HG_DIV2_CORE_HI 23
+#define RG_TURISMO_TRX_BT_RX_HG_DIV2_CORE_SZ 2
+#define RG_TURISMO_TRX_BT_RX_HG_LOBUF_MSK 0x03000000
+#define RG_TURISMO_TRX_BT_RX_HG_LOBUF_I_MSK 0xfcffffff
+#define RG_TURISMO_TRX_BT_RX_HG_LOBUF_SFT 24
+#define RG_TURISMO_TRX_BT_RX_HG_LOBUF_HI 25
+#define RG_TURISMO_TRX_BT_RX_HG_LOBUF_SZ 2
+#define RG_TURISMO_TRX_BT_RX_HG_TZI_MSK 0x1c000000
+#define RG_TURISMO_TRX_BT_RX_HG_TZI_I_MSK 0xe3ffffff
+#define RG_TURISMO_TRX_BT_RX_HG_TZI_SFT 26
+#define RG_TURISMO_TRX_BT_RX_HG_TZI_HI 28
+#define RG_TURISMO_TRX_BT_RX_HG_TZI_SZ 3
+#define RG_TURISMO_TRX_BT_RX_HG_TZ_VCM_MSK 0xe0000000
+#define RG_TURISMO_TRX_BT_RX_HG_TZ_VCM_I_MSK 0x1fffffff
+#define RG_TURISMO_TRX_BT_RX_HG_TZ_VCM_SFT 29
+#define RG_TURISMO_TRX_BT_RX_HG_TZ_VCM_HI 31
+#define RG_TURISMO_TRX_BT_RX_HG_TZ_VCM_SZ 3
+#define RG_TURISMO_TRX_BT_RX_MG_LNA_GC_MSK 0x00000003
+#define RG_TURISMO_TRX_BT_RX_MG_LNA_GC_I_MSK 0xfffffffc
+#define RG_TURISMO_TRX_BT_RX_MG_LNA_GC_SFT 0
+#define RG_TURISMO_TRX_BT_RX_MG_LNA_GC_HI 1
+#define RG_TURISMO_TRX_BT_RX_MG_LNA_GC_SZ 2
+#define RG_TURISMO_TRX_BT_RX_MG_TZ_GC_MSK 0x0000000c
+#define RG_TURISMO_TRX_BT_RX_MG_TZ_GC_I_MSK 0xfffffff3
+#define RG_TURISMO_TRX_BT_RX_MG_TZ_GC_SFT 2
+#define RG_TURISMO_TRX_BT_RX_MG_TZ_GC_HI 3
+#define RG_TURISMO_TRX_BT_RX_MG_TZ_GC_SZ 2
+#define RG_TURISMO_TRX_BT_RX_MG_LNAHGN_BIAS_MSK 0x000000f0
+#define RG_TURISMO_TRX_BT_RX_MG_LNAHGN_BIAS_I_MSK 0xffffff0f
+#define RG_TURISMO_TRX_BT_RX_MG_LNAHGN_BIAS_SFT 4
+#define RG_TURISMO_TRX_BT_RX_MG_LNAHGN_BIAS_HI 7
+#define RG_TURISMO_TRX_BT_RX_MG_LNAHGN_BIAS_SZ 4
+#define RG_TURISMO_TRX_BT_RX_MG_LNAHGP_BIAS_MSK 0x00000f00
+#define RG_TURISMO_TRX_BT_RX_MG_LNAHGP_BIAS_I_MSK 0xfffff0ff
+#define RG_TURISMO_TRX_BT_RX_MG_LNAHGP_BIAS_SFT 8
+#define RG_TURISMO_TRX_BT_RX_MG_LNAHGP_BIAS_HI 11
+#define RG_TURISMO_TRX_BT_RX_MG_LNAHGP_BIAS_SZ 4
+#define RG_TURISMO_TRX_BT_RX_MG_LNALG_BIAS_MSK 0x0000f000
+#define RG_TURISMO_TRX_BT_RX_MG_LNALG_BIAS_I_MSK 0xffff0fff
+#define RG_TURISMO_TRX_BT_RX_MG_LNALG_BIAS_SFT 12
+#define RG_TURISMO_TRX_BT_RX_MG_LNALG_BIAS_HI 15
+#define RG_TURISMO_TRX_BT_RX_MG_LNALG_BIAS_SZ 4
+#define RG_TURISMO_TRX_BT_RX_MG_TZ_CAP_MSK 0x00070000
+#define RG_TURISMO_TRX_BT_RX_MG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_TURISMO_TRX_BT_RX_MG_TZ_CAP_SFT 16
+#define RG_TURISMO_TRX_BT_RX_MG_TZ_CAP_HI 18
+#define RG_TURISMO_TRX_BT_RX_MG_TZ_CAP_SZ 3
+#define RG_TURISMO_TRX_BT_RX_MG_TZ_GC_BOOST_MSK 0x00300000
+#define RG_TURISMO_TRX_BT_RX_MG_TZ_GC_BOOST_I_MSK 0xffcfffff
+#define RG_TURISMO_TRX_BT_RX_MG_TZ_GC_BOOST_SFT 20
+#define RG_TURISMO_TRX_BT_RX_MG_TZ_GC_BOOST_HI 21
+#define RG_TURISMO_TRX_BT_RX_MG_TZ_GC_BOOST_SZ 2
+#define RG_TURISMO_TRX_BT_RX_MG_DIV2_CORE_MSK 0x00c00000
+#define RG_TURISMO_TRX_BT_RX_MG_DIV2_CORE_I_MSK 0xff3fffff
+#define RG_TURISMO_TRX_BT_RX_MG_DIV2_CORE_SFT 22
+#define RG_TURISMO_TRX_BT_RX_MG_DIV2_CORE_HI 23
+#define RG_TURISMO_TRX_BT_RX_MG_DIV2_CORE_SZ 2
+#define RG_TURISMO_TRX_BT_RX_MG_LOBUF_MSK 0x03000000
+#define RG_TURISMO_TRX_BT_RX_MG_LOBUF_I_MSK 0xfcffffff
+#define RG_TURISMO_TRX_BT_RX_MG_LOBUF_SFT 24
+#define RG_TURISMO_TRX_BT_RX_MG_LOBUF_HI 25
+#define RG_TURISMO_TRX_BT_RX_MG_LOBUF_SZ 2
+#define RG_TURISMO_TRX_BT_RX_MG_TZI_MSK 0x1c000000
+#define RG_TURISMO_TRX_BT_RX_MG_TZI_I_MSK 0xe3ffffff
+#define RG_TURISMO_TRX_BT_RX_MG_TZI_SFT 26
+#define RG_TURISMO_TRX_BT_RX_MG_TZI_HI 28
+#define RG_TURISMO_TRX_BT_RX_MG_TZI_SZ 3
+#define RG_TURISMO_TRX_BT_RX_MG_TZ_VCM_MSK 0xe0000000
+#define RG_TURISMO_TRX_BT_RX_MG_TZ_VCM_I_MSK 0x1fffffff
+#define RG_TURISMO_TRX_BT_RX_MG_TZ_VCM_SFT 29
+#define RG_TURISMO_TRX_BT_RX_MG_TZ_VCM_HI 31
+#define RG_TURISMO_TRX_BT_RX_MG_TZ_VCM_SZ 3
+#define RG_TURISMO_TRX_BT_RX_LG_LNA_GC_MSK 0x00000003
+#define RG_TURISMO_TRX_BT_RX_LG_LNA_GC_I_MSK 0xfffffffc
+#define RG_TURISMO_TRX_BT_RX_LG_LNA_GC_SFT 0
+#define RG_TURISMO_TRX_BT_RX_LG_LNA_GC_HI 1
+#define RG_TURISMO_TRX_BT_RX_LG_LNA_GC_SZ 2
+#define RG_TURISMO_TRX_BT_RX_LG_TZ_GC_MSK 0x0000000c
+#define RG_TURISMO_TRX_BT_RX_LG_TZ_GC_I_MSK 0xfffffff3
+#define RG_TURISMO_TRX_BT_RX_LG_TZ_GC_SFT 2
+#define RG_TURISMO_TRX_BT_RX_LG_TZ_GC_HI 3
+#define RG_TURISMO_TRX_BT_RX_LG_TZ_GC_SZ 2
+#define RG_TURISMO_TRX_BT_RX_LG_LNAHGN_BIAS_MSK 0x000000f0
+#define RG_TURISMO_TRX_BT_RX_LG_LNAHGN_BIAS_I_MSK 0xffffff0f
+#define RG_TURISMO_TRX_BT_RX_LG_LNAHGN_BIAS_SFT 4
+#define RG_TURISMO_TRX_BT_RX_LG_LNAHGN_BIAS_HI 7
+#define RG_TURISMO_TRX_BT_RX_LG_LNAHGN_BIAS_SZ 4
+#define RG_TURISMO_TRX_BT_RX_LG_LNAHGP_BIAS_MSK 0x00000f00
+#define RG_TURISMO_TRX_BT_RX_LG_LNAHGP_BIAS_I_MSK 0xfffff0ff
+#define RG_TURISMO_TRX_BT_RX_LG_LNAHGP_BIAS_SFT 8
+#define RG_TURISMO_TRX_BT_RX_LG_LNAHGP_BIAS_HI 11
+#define RG_TURISMO_TRX_BT_RX_LG_LNAHGP_BIAS_SZ 4
+#define RG_TURISMO_TRX_BT_RX_LG_LNALG_BIAS_MSK 0x0000f000
+#define RG_TURISMO_TRX_BT_RX_LG_LNALG_BIAS_I_MSK 0xffff0fff
+#define RG_TURISMO_TRX_BT_RX_LG_LNALG_BIAS_SFT 12
+#define RG_TURISMO_TRX_BT_RX_LG_LNALG_BIAS_HI 15
+#define RG_TURISMO_TRX_BT_RX_LG_LNALG_BIAS_SZ 4
+#define RG_TURISMO_TRX_BT_RX_LG_TZ_CAP_MSK 0x00070000
+#define RG_TURISMO_TRX_BT_RX_LG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_TURISMO_TRX_BT_RX_LG_TZ_CAP_SFT 16
+#define RG_TURISMO_TRX_BT_RX_LG_TZ_CAP_HI 18
+#define RG_TURISMO_TRX_BT_RX_LG_TZ_CAP_SZ 3
+#define RG_TURISMO_TRX_BT_RX_LG_TZ_GC_BOOST_MSK 0x00300000
+#define RG_TURISMO_TRX_BT_RX_LG_TZ_GC_BOOST_I_MSK 0xffcfffff
+#define RG_TURISMO_TRX_BT_RX_LG_TZ_GC_BOOST_SFT 20
+#define RG_TURISMO_TRX_BT_RX_LG_TZ_GC_BOOST_HI 21
+#define RG_TURISMO_TRX_BT_RX_LG_TZ_GC_BOOST_SZ 2
+#define RG_TURISMO_TRX_BT_RX_LG_DIV2_CORE_MSK 0x00c00000
+#define RG_TURISMO_TRX_BT_RX_LG_DIV2_CORE_I_MSK 0xff3fffff
+#define RG_TURISMO_TRX_BT_RX_LG_DIV2_CORE_SFT 22
+#define RG_TURISMO_TRX_BT_RX_LG_DIV2_CORE_HI 23
+#define RG_TURISMO_TRX_BT_RX_LG_DIV2_CORE_SZ 2
+#define RG_TURISMO_TRX_BT_RX_LG_LOBUF_MSK 0x03000000
+#define RG_TURISMO_TRX_BT_RX_LG_LOBUF_I_MSK 0xfcffffff
+#define RG_TURISMO_TRX_BT_RX_LG_LOBUF_SFT 24
+#define RG_TURISMO_TRX_BT_RX_LG_LOBUF_HI 25
+#define RG_TURISMO_TRX_BT_RX_LG_LOBUF_SZ 2
+#define RG_TURISMO_TRX_BT_RX_LG_TZI_MSK 0x1c000000
+#define RG_TURISMO_TRX_BT_RX_LG_TZI_I_MSK 0xe3ffffff
+#define RG_TURISMO_TRX_BT_RX_LG_TZI_SFT 26
+#define RG_TURISMO_TRX_BT_RX_LG_TZI_HI 28
+#define RG_TURISMO_TRX_BT_RX_LG_TZI_SZ 3
+#define RG_TURISMO_TRX_BT_RX_LG_TZ_VCM_MSK 0xe0000000
+#define RG_TURISMO_TRX_BT_RX_LG_TZ_VCM_I_MSK 0x1fffffff
+#define RG_TURISMO_TRX_BT_RX_LG_TZ_VCM_SFT 29
+#define RG_TURISMO_TRX_BT_RX_LG_TZ_VCM_HI 31
+#define RG_TURISMO_TRX_BT_RX_LG_TZ_VCM_SZ 3
+#define RG_TURISMO_TRX_BT_RX_ULG_LNA_GC_MSK 0x00000003
+#define RG_TURISMO_TRX_BT_RX_ULG_LNA_GC_I_MSK 0xfffffffc
+#define RG_TURISMO_TRX_BT_RX_ULG_LNA_GC_SFT 0
+#define RG_TURISMO_TRX_BT_RX_ULG_LNA_GC_HI 1
+#define RG_TURISMO_TRX_BT_RX_ULG_LNA_GC_SZ 2
+#define RG_TURISMO_TRX_BT_RX_ULG_TZ_GC_MSK 0x0000000c
+#define RG_TURISMO_TRX_BT_RX_ULG_TZ_GC_I_MSK 0xfffffff3
+#define RG_TURISMO_TRX_BT_RX_ULG_TZ_GC_SFT 2
+#define RG_TURISMO_TRX_BT_RX_ULG_TZ_GC_HI 3
+#define RG_TURISMO_TRX_BT_RX_ULG_TZ_GC_SZ 2
+#define RG_TURISMO_TRX_BT_RX_ULG_LNAHGN_BIAS_MSK 0x000000f0
+#define RG_TURISMO_TRX_BT_RX_ULG_LNAHGN_BIAS_I_MSK 0xffffff0f
+#define RG_TURISMO_TRX_BT_RX_ULG_LNAHGN_BIAS_SFT 4
+#define RG_TURISMO_TRX_BT_RX_ULG_LNAHGN_BIAS_HI 7
+#define RG_TURISMO_TRX_BT_RX_ULG_LNAHGN_BIAS_SZ 4
+#define RG_TURISMO_TRX_BT_RX_ULG_LNAHGP_BIAS_MSK 0x00000f00
+#define RG_TURISMO_TRX_BT_RX_ULG_LNAHGP_BIAS_I_MSK 0xfffff0ff
+#define RG_TURISMO_TRX_BT_RX_ULG_LNAHGP_BIAS_SFT 8
+#define RG_TURISMO_TRX_BT_RX_ULG_LNAHGP_BIAS_HI 11
+#define RG_TURISMO_TRX_BT_RX_ULG_LNAHGP_BIAS_SZ 4
+#define RG_TURISMO_TRX_BT_RX_ULG_LNALG_BIAS_MSK 0x0000f000
+#define RG_TURISMO_TRX_BT_RX_ULG_LNALG_BIAS_I_MSK 0xffff0fff
+#define RG_TURISMO_TRX_BT_RX_ULG_LNALG_BIAS_SFT 12
+#define RG_TURISMO_TRX_BT_RX_ULG_LNALG_BIAS_HI 15
+#define RG_TURISMO_TRX_BT_RX_ULG_LNALG_BIAS_SZ 4
+#define RG_TURISMO_TRX_BT_RX_ULG_TZ_CAP_MSK 0x00070000
+#define RG_TURISMO_TRX_BT_RX_ULG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_TURISMO_TRX_BT_RX_ULG_TZ_CAP_SFT 16
+#define RG_TURISMO_TRX_BT_RX_ULG_TZ_CAP_HI 18
+#define RG_TURISMO_TRX_BT_RX_ULG_TZ_CAP_SZ 3
+#define RG_TURISMO_TRX_BT_RX_ULG_TZ_GC_BOOST_MSK 0x00300000
+#define RG_TURISMO_TRX_BT_RX_ULG_TZ_GC_BOOST_I_MSK 0xffcfffff
+#define RG_TURISMO_TRX_BT_RX_ULG_TZ_GC_BOOST_SFT 20
+#define RG_TURISMO_TRX_BT_RX_ULG_TZ_GC_BOOST_HI 21
+#define RG_TURISMO_TRX_BT_RX_ULG_TZ_GC_BOOST_SZ 2
+#define RG_TURISMO_TRX_BT_RX_ULG_DIV2_CORE_MSK 0x00c00000
+#define RG_TURISMO_TRX_BT_RX_ULG_DIV2_CORE_I_MSK 0xff3fffff
+#define RG_TURISMO_TRX_BT_RX_ULG_DIV2_CORE_SFT 22
+#define RG_TURISMO_TRX_BT_RX_ULG_DIV2_CORE_HI 23
+#define RG_TURISMO_TRX_BT_RX_ULG_DIV2_CORE_SZ 2
+#define RG_TURISMO_TRX_BT_RX_ULG_LOBUF_MSK 0x03000000
+#define RG_TURISMO_TRX_BT_RX_ULG_LOBUF_I_MSK 0xfcffffff
+#define RG_TURISMO_TRX_BT_RX_ULG_LOBUF_SFT 24
+#define RG_TURISMO_TRX_BT_RX_ULG_LOBUF_HI 25
+#define RG_TURISMO_TRX_BT_RX_ULG_LOBUF_SZ 2
+#define RG_TURISMO_TRX_BT_RX_ULG_TZI_MSK 0x1c000000
+#define RG_TURISMO_TRX_BT_RX_ULG_TZI_I_MSK 0xe3ffffff
+#define RG_TURISMO_TRX_BT_RX_ULG_TZI_SFT 26
+#define RG_TURISMO_TRX_BT_RX_ULG_TZI_HI 28
+#define RG_TURISMO_TRX_BT_RX_ULG_TZI_SZ 3
+#define RG_TURISMO_TRX_BT_RX_ULG_TZ_VCM_MSK 0xe0000000
+#define RG_TURISMO_TRX_BT_RX_ULG_TZ_VCM_I_MSK 0x1fffffff
+#define RG_TURISMO_TRX_BT_RX_ULG_TZ_VCM_SFT 29
+#define RG_TURISMO_TRX_BT_RX_ULG_TZ_VCM_HI 31
+#define RG_TURISMO_TRX_BT_RX_ULG_TZ_VCM_SZ 3
+#define RG_TURISMO_TRX_RX_ADC_CLKSEL_MSK 0x00000001
+#define RG_TURISMO_TRX_RX_ADC_CLKSEL_I_MSK 0xfffffffe
+#define RG_TURISMO_TRX_RX_ADC_CLKSEL_SFT 0
+#define RG_TURISMO_TRX_RX_ADC_CLKSEL_HI 0
+#define RG_TURISMO_TRX_RX_ADC_CLKSEL_SZ 1
+#define RG_TURISMO_TRX_RX_ADC_DNLEN_MSK 0x00000002
+#define RG_TURISMO_TRX_RX_ADC_DNLEN_I_MSK 0xfffffffd
+#define RG_TURISMO_TRX_RX_ADC_DNLEN_SFT 1
+#define RG_TURISMO_TRX_RX_ADC_DNLEN_HI 1
+#define RG_TURISMO_TRX_RX_ADC_DNLEN_SZ 1
+#define RG_TURISMO_TRX_RX_ADC_METAEN_MSK 0x00000004
+#define RG_TURISMO_TRX_RX_ADC_METAEN_I_MSK 0xfffffffb
+#define RG_TURISMO_TRX_RX_ADC_METAEN_SFT 2
+#define RG_TURISMO_TRX_RX_ADC_METAEN_HI 2
+#define RG_TURISMO_TRX_RX_ADC_METAEN_SZ 1
+#define RG_TURISMO_TRX_RX_ADC_TFLAG_MSK 0x00000008
+#define RG_TURISMO_TRX_RX_ADC_TFLAG_I_MSK 0xfffffff7
+#define RG_TURISMO_TRX_RX_ADC_TFLAG_SFT 3
+#define RG_TURISMO_TRX_RX_ADC_TFLAG_HI 3
+#define RG_TURISMO_TRX_RX_ADC_TFLAG_SZ 1
+#define RG_TURISMO_TRX_RX_ADC_TSEL_MSK 0x000000f0
+#define RG_TURISMO_TRX_RX_ADC_TSEL_I_MSK 0xffffff0f
+#define RG_TURISMO_TRX_RX_ADC_TSEL_SFT 4
+#define RG_TURISMO_TRX_RX_ADC_TSEL_HI 7
+#define RG_TURISMO_TRX_RX_ADC_TSEL_SZ 4
+#define RG_TURISMO_TRX_WF_RX_ADC_ICMP_MSK 0x00000300
+#define RG_TURISMO_TRX_WF_RX_ADC_ICMP_I_MSK 0xfffffcff
+#define RG_TURISMO_TRX_WF_RX_ADC_ICMP_SFT 8
+#define RG_TURISMO_TRX_WF_RX_ADC_ICMP_HI 9
+#define RG_TURISMO_TRX_WF_RX_ADC_ICMP_SZ 2
+#define RG_TURISMO_TRX_WF_RX_ADC_VCMI_MSK 0x00000c00
+#define RG_TURISMO_TRX_WF_RX_ADC_VCMI_I_MSK 0xfffff3ff
+#define RG_TURISMO_TRX_WF_RX_ADC_VCMI_SFT 10
+#define RG_TURISMO_TRX_WF_RX_ADC_VCMI_HI 11
+#define RG_TURISMO_TRX_WF_RX_ADC_VCMI_SZ 2
+#define RG_TURISMO_TRX_WF_RX_ADC_CLOAD_MSK 0x00003000
+#define RG_TURISMO_TRX_WF_RX_ADC_CLOAD_I_MSK 0xffffcfff
+#define RG_TURISMO_TRX_WF_RX_ADC_CLOAD_SFT 12
+#define RG_TURISMO_TRX_WF_RX_ADC_CLOAD_HI 13
+#define RG_TURISMO_TRX_WF_RX_ADC_CLOAD_SZ 2
+#define RG_TURISMO_TRX_BT_RX_ADC_ICMP_MSK 0x00030000
+#define RG_TURISMO_TRX_BT_RX_ADC_ICMP_I_MSK 0xfffcffff
+#define RG_TURISMO_TRX_BT_RX_ADC_ICMP_SFT 16
+#define RG_TURISMO_TRX_BT_RX_ADC_ICMP_HI 17
+#define RG_TURISMO_TRX_BT_RX_ADC_ICMP_SZ 2
+#define RG_TURISMO_TRX_BT_RX_ADC_VCMI_MSK 0x000c0000
+#define RG_TURISMO_TRX_BT_RX_ADC_VCMI_I_MSK 0xfff3ffff
+#define RG_TURISMO_TRX_BT_RX_ADC_VCMI_SFT 18
+#define RG_TURISMO_TRX_BT_RX_ADC_VCMI_HI 19
+#define RG_TURISMO_TRX_BT_RX_ADC_VCMI_SZ 2
+#define RG_TURISMO_TRX_BT_RX_ADC_CLOAD_MSK 0x00300000
+#define RG_TURISMO_TRX_BT_RX_ADC_CLOAD_I_MSK 0xffcfffff
+#define RG_TURISMO_TRX_BT_RX_ADC_CLOAD_SFT 20
+#define RG_TURISMO_TRX_BT_RX_ADC_CLOAD_HI 21
+#define RG_TURISMO_TRX_BT_RX_ADC_CLOAD_SZ 2
+#define RG_TURISMO_TRX_SARADC_5G_TSSI_MSK 0x00800000
+#define RG_TURISMO_TRX_SARADC_5G_TSSI_I_MSK 0xff7fffff
+#define RG_TURISMO_TRX_SARADC_5G_TSSI_SFT 23
+#define RG_TURISMO_TRX_SARADC_5G_TSSI_HI 23
+#define RG_TURISMO_TRX_SARADC_5G_TSSI_SZ 1
+#define RG_TURISMO_TRX_SARADC_VRSEL_MSK 0x03000000
+#define RG_TURISMO_TRX_SARADC_VRSEL_I_MSK 0xfcffffff
+#define RG_TURISMO_TRX_SARADC_VRSEL_SFT 24
+#define RG_TURISMO_TRX_SARADC_VRSEL_HI 25
+#define RG_TURISMO_TRX_SARADC_VRSEL_SZ 2
+#define RG_TURISMO_TRX_EN_SAR_TEST_MSK 0x0c000000
+#define RG_TURISMO_TRX_EN_SAR_TEST_I_MSK 0xf3ffffff
+#define RG_TURISMO_TRX_EN_SAR_TEST_SFT 26
+#define RG_TURISMO_TRX_EN_SAR_TEST_HI 27
+#define RG_TURISMO_TRX_EN_SAR_TEST_SZ 2
+#define RG_TURISMO_TRX_SARADC_THERMAL_MSK 0x10000000
+#define RG_TURISMO_TRX_SARADC_THERMAL_I_MSK 0xefffffff
+#define RG_TURISMO_TRX_SARADC_THERMAL_SFT 28
+#define RG_TURISMO_TRX_SARADC_THERMAL_HI 28
+#define RG_TURISMO_TRX_SARADC_THERMAL_SZ 1
+#define RG_TURISMO_TRX_SARADC_TSSI_MSK 0x20000000
+#define RG_TURISMO_TRX_SARADC_TSSI_I_MSK 0xdfffffff
+#define RG_TURISMO_TRX_SARADC_TSSI_SFT 29
+#define RG_TURISMO_TRX_SARADC_TSSI_HI 29
+#define RG_TURISMO_TRX_SARADC_TSSI_SZ 1
+#define RG_TURISMO_TRX_CLK_SAR_SEL_MSK 0xc0000000
+#define RG_TURISMO_TRX_CLK_SAR_SEL_I_MSK 0x3fffffff
+#define RG_TURISMO_TRX_CLK_SAR_SEL_SFT 30
+#define RG_TURISMO_TRX_CLK_SAR_SEL_HI 31
+#define RG_TURISMO_TRX_CLK_SAR_SEL_SZ 2
+#define RG_TURISMO_TRX_WF_TX_DACI1ST_MSK 0x00000003
+#define RG_TURISMO_TRX_WF_TX_DACI1ST_I_MSK 0xfffffffc
+#define RG_TURISMO_TRX_WF_TX_DACI1ST_SFT 0
+#define RG_TURISMO_TRX_WF_TX_DACI1ST_HI 1
+#define RG_TURISMO_TRX_WF_TX_DACI1ST_SZ 2
+#define RG_TURISMO_TRX_WF_TX_DACLPF_ICOARSE_MSK 0x0000000c
+#define RG_TURISMO_TRX_WF_TX_DACLPF_ICOARSE_I_MSK 0xfffffff3
+#define RG_TURISMO_TRX_WF_TX_DACLPF_ICOARSE_SFT 2
+#define RG_TURISMO_TRX_WF_TX_DACLPF_ICOARSE_HI 3
+#define RG_TURISMO_TRX_WF_TX_DACLPF_ICOARSE_SZ 2
+#define RG_TURISMO_TRX_WF_TX_DACLPF_IFINE_MSK 0x00000030
+#define RG_TURISMO_TRX_WF_TX_DACLPF_IFINE_I_MSK 0xffffffcf
+#define RG_TURISMO_TRX_WF_TX_DACLPF_IFINE_SFT 4
+#define RG_TURISMO_TRX_WF_TX_DACLPF_IFINE_HI 5
+#define RG_TURISMO_TRX_WF_TX_DACLPF_IFINE_SZ 2
+#define RG_TURISMO_TRX_WF_TX_DACLPF_VCM_MSK 0x000000c0
+#define RG_TURISMO_TRX_WF_TX_DACLPF_VCM_I_MSK 0xffffff3f
+#define RG_TURISMO_TRX_WF_TX_DACLPF_VCM_SFT 6
+#define RG_TURISMO_TRX_WF_TX_DACLPF_VCM_HI 7
+#define RG_TURISMO_TRX_WF_TX_DACLPF_VCM_SZ 2
+#define RG_TURISMO_TRX_WF_TX_DAC_IBIAS_MSK 0x00000300
+#define RG_TURISMO_TRX_WF_TX_DAC_IBIAS_I_MSK 0xfffffcff
+#define RG_TURISMO_TRX_WF_TX_DAC_IBIAS_SFT 8
+#define RG_TURISMO_TRX_WF_TX_DAC_IBIAS_HI 9
+#define RG_TURISMO_TRX_WF_TX_DAC_IBIAS_SZ 2
+#define RG_TURISMO_TRX_WF_TX_DAC_IATTN_MSK 0x00000400
+#define RG_TURISMO_TRX_WF_TX_DAC_IATTN_I_MSK 0xfffffbff
+#define RG_TURISMO_TRX_WF_TX_DAC_IATTN_SFT 10
+#define RG_TURISMO_TRX_WF_TX_DAC_IATTN_HI 10
+#define RG_TURISMO_TRX_WF_TX_DAC_IATTN_SZ 1
+#define RG_TURISMO_TRX_WF_TXLPF_BOOSTI_MSK 0x00000800
+#define RG_TURISMO_TRX_WF_TXLPF_BOOSTI_I_MSK 0xfffff7ff
+#define RG_TURISMO_TRX_WF_TXLPF_BOOSTI_SFT 11
+#define RG_TURISMO_TRX_WF_TXLPF_BOOSTI_HI 11
+#define RG_TURISMO_TRX_WF_TXLPF_BOOSTI_SZ 1
+#define RG_TURISMO_TRX_WF_TX_DAC_RCAL_MSK 0x00003000
+#define RG_TURISMO_TRX_WF_TX_DAC_RCAL_I_MSK 0xffffcfff
+#define RG_TURISMO_TRX_WF_TX_DAC_RCAL_SFT 12
+#define RG_TURISMO_TRX_WF_TX_DAC_RCAL_HI 13
+#define RG_TURISMO_TRX_WF_TX_DAC_RCAL_SZ 2
+#define RG_TURISMO_TRX_WF_TX_DAC_CKEDGE_SEL_MSK 0x00004000
+#define RG_TURISMO_TRX_WF_TX_DAC_CKEDGE_SEL_I_MSK 0xffffbfff
+#define RG_TURISMO_TRX_WF_TX_DAC_CKEDGE_SEL_SFT 14
+#define RG_TURISMO_TRX_WF_TX_DAC_CKEDGE_SEL_HI 14
+#define RG_TURISMO_TRX_WF_TX_DAC_CKEDGE_SEL_SZ 1
+#define RG_TURISMO_TRX_WF_TX_DAC_OS_MSK 0x00070000
+#define RG_TURISMO_TRX_WF_TX_DAC_OS_I_MSK 0xfff8ffff
+#define RG_TURISMO_TRX_WF_TX_DAC_OS_SFT 16
+#define RG_TURISMO_TRX_WF_TX_DAC_OS_HI 18
+#define RG_TURISMO_TRX_WF_TX_DAC_OS_SZ 3
+#define RG_TURISMO_TRX_WF_TX_DAC_IOFFSET_MSK 0x00f00000
+#define RG_TURISMO_TRX_WF_TX_DAC_IOFFSET_I_MSK 0xff0fffff
+#define RG_TURISMO_TRX_WF_TX_DAC_IOFFSET_SFT 20
+#define RG_TURISMO_TRX_WF_TX_DAC_IOFFSET_HI 23
+#define RG_TURISMO_TRX_WF_TX_DAC_IOFFSET_SZ 4
+#define RG_TURISMO_TRX_WF_TX_DAC_QOFFSET_MSK 0x0f000000
+#define RG_TURISMO_TRX_WF_TX_DAC_QOFFSET_I_MSK 0xf0ffffff
+#define RG_TURISMO_TRX_WF_TX_DAC_QOFFSET_SFT 24
+#define RG_TURISMO_TRX_WF_TX_DAC_QOFFSET_HI 27
+#define RG_TURISMO_TRX_WF_TX_DAC_QOFFSET_SZ 4
+#define RG_TURISMO_TRX_TX_DAC_TSEL_MSK 0xf0000000
+#define RG_TURISMO_TRX_TX_DAC_TSEL_I_MSK 0x0fffffff
+#define RG_TURISMO_TRX_TX_DAC_TSEL_SFT 28
+#define RG_TURISMO_TRX_TX_DAC_TSEL_HI 31
+#define RG_TURISMO_TRX_TX_DAC_TSEL_SZ 4
+#define RG_TURISMO_TRX_BT_TX_DACI1ST_MSK 0x00000003
+#define RG_TURISMO_TRX_BT_TX_DACI1ST_I_MSK 0xfffffffc
+#define RG_TURISMO_TRX_BT_TX_DACI1ST_SFT 0
+#define RG_TURISMO_TRX_BT_TX_DACI1ST_HI 1
+#define RG_TURISMO_TRX_BT_TX_DACI1ST_SZ 2
+#define RG_TURISMO_TRX_BT_TX_DACLPF_ICOARSE_MSK 0x0000000c
+#define RG_TURISMO_TRX_BT_TX_DACLPF_ICOARSE_I_MSK 0xfffffff3
+#define RG_TURISMO_TRX_BT_TX_DACLPF_ICOARSE_SFT 2
+#define RG_TURISMO_TRX_BT_TX_DACLPF_ICOARSE_HI 3
+#define RG_TURISMO_TRX_BT_TX_DACLPF_ICOARSE_SZ 2
+#define RG_TURISMO_TRX_BT_TX_DACLPF_IFINE_MSK 0x00000030
+#define RG_TURISMO_TRX_BT_TX_DACLPF_IFINE_I_MSK 0xffffffcf
+#define RG_TURISMO_TRX_BT_TX_DACLPF_IFINE_SFT 4
+#define RG_TURISMO_TRX_BT_TX_DACLPF_IFINE_HI 5
+#define RG_TURISMO_TRX_BT_TX_DACLPF_IFINE_SZ 2
+#define RG_TURISMO_TRX_BT_TX_DACLPF_VCM_MSK 0x000000c0
+#define RG_TURISMO_TRX_BT_TX_DACLPF_VCM_I_MSK 0xffffff3f
+#define RG_TURISMO_TRX_BT_TX_DACLPF_VCM_SFT 6
+#define RG_TURISMO_TRX_BT_TX_DACLPF_VCM_HI 7
+#define RG_TURISMO_TRX_BT_TX_DACLPF_VCM_SZ 2
+#define RG_TURISMO_TRX_BT_TX_DAC_IBIAS_MSK 0x00000300
+#define RG_TURISMO_TRX_BT_TX_DAC_IBIAS_I_MSK 0xfffffcff
+#define RG_TURISMO_TRX_BT_TX_DAC_IBIAS_SFT 8
+#define RG_TURISMO_TRX_BT_TX_DAC_IBIAS_HI 9
+#define RG_TURISMO_TRX_BT_TX_DAC_IBIAS_SZ 2
+#define RG_TURISMO_TRX_BT_TX_DAC_IATTN_MSK 0x00000400
+#define RG_TURISMO_TRX_BT_TX_DAC_IATTN_I_MSK 0xfffffbff
+#define RG_TURISMO_TRX_BT_TX_DAC_IATTN_SFT 10
+#define RG_TURISMO_TRX_BT_TX_DAC_IATTN_HI 10
+#define RG_TURISMO_TRX_BT_TX_DAC_IATTN_SZ 1
+#define RG_TURISMO_TRX_BT_TXLPF_BOOSTI_MSK 0x00000800
+#define RG_TURISMO_TRX_BT_TXLPF_BOOSTI_I_MSK 0xfffff7ff
+#define RG_TURISMO_TRX_BT_TXLPF_BOOSTI_SFT 11
+#define RG_TURISMO_TRX_BT_TXLPF_BOOSTI_HI 11
+#define RG_TURISMO_TRX_BT_TXLPF_BOOSTI_SZ 1
+#define RG_TURISMO_TRX_BT_TX_DAC_RCAL_MSK 0x00003000
+#define RG_TURISMO_TRX_BT_TX_DAC_RCAL_I_MSK 0xffffcfff
+#define RG_TURISMO_TRX_BT_TX_DAC_RCAL_SFT 12
+#define RG_TURISMO_TRX_BT_TX_DAC_RCAL_HI 13
+#define RG_TURISMO_TRX_BT_TX_DAC_RCAL_SZ 2
+#define RG_TURISMO_TRX_BT_TX_DAC_CKEDGE_SEL_MSK 0x00004000
+#define RG_TURISMO_TRX_BT_TX_DAC_CKEDGE_SEL_I_MSK 0xffffbfff
+#define RG_TURISMO_TRX_BT_TX_DAC_CKEDGE_SEL_SFT 14
+#define RG_TURISMO_TRX_BT_TX_DAC_CKEDGE_SEL_HI 14
+#define RG_TURISMO_TRX_BT_TX_DAC_CKEDGE_SEL_SZ 1
+#define RG_TURISMO_TRX_BT_TX_DAC_OS_MSK 0x00070000
+#define RG_TURISMO_TRX_BT_TX_DAC_OS_I_MSK 0xfff8ffff
+#define RG_TURISMO_TRX_BT_TX_DAC_OS_SFT 16
+#define RG_TURISMO_TRX_BT_TX_DAC_OS_HI 18
+#define RG_TURISMO_TRX_BT_TX_DAC_OS_SZ 3
+#define RG_TURISMO_TRX_BT_TX_DAC_IOFFSET_MSK 0x00f00000
+#define RG_TURISMO_TRX_BT_TX_DAC_IOFFSET_I_MSK 0xff0fffff
+#define RG_TURISMO_TRX_BT_TX_DAC_IOFFSET_SFT 20
+#define RG_TURISMO_TRX_BT_TX_DAC_IOFFSET_HI 23
+#define RG_TURISMO_TRX_BT_TX_DAC_IOFFSET_SZ 4
+#define RG_TURISMO_TRX_BT_TX_DAC_QOFFSET_MSK 0x0f000000
+#define RG_TURISMO_TRX_BT_TX_DAC_QOFFSET_I_MSK 0xf0ffffff
+#define RG_TURISMO_TRX_BT_TX_DAC_QOFFSET_SFT 24
+#define RG_TURISMO_TRX_BT_TX_DAC_QOFFSET_HI 27
+#define RG_TURISMO_TRX_BT_TX_DAC_QOFFSET_SZ 4
+#define RG_TURISMO_TRX_SX_EN_MAN_MSK 0x00000001
+#define RG_TURISMO_TRX_SX_EN_MAN_I_MSK 0xfffffffe
+#define RG_TURISMO_TRX_SX_EN_MAN_SFT 0
+#define RG_TURISMO_TRX_SX_EN_MAN_HI 0
+#define RG_TURISMO_TRX_SX_EN_MAN_SZ 1
+#define RG_TURISMO_TRX_SX_EN_MSK 0x00000002
+#define RG_TURISMO_TRX_SX_EN_I_MSK 0xfffffffd
+#define RG_TURISMO_TRX_SX_EN_SFT 1
+#define RG_TURISMO_TRX_SX_EN_HI 1
+#define RG_TURISMO_TRX_SX_EN_SZ 1
+#define RG_TURISMO_TRX_EN_SX_CP_MAN_MSK 0x00000004
+#define RG_TURISMO_TRX_EN_SX_CP_MAN_I_MSK 0xfffffffb
+#define RG_TURISMO_TRX_EN_SX_CP_MAN_SFT 2
+#define RG_TURISMO_TRX_EN_SX_CP_MAN_HI 2
+#define RG_TURISMO_TRX_EN_SX_CP_MAN_SZ 1
+#define RG_TURISMO_TRX_EN_SX_CP_MSK 0x00000008
+#define RG_TURISMO_TRX_EN_SX_CP_I_MSK 0xfffffff7
+#define RG_TURISMO_TRX_EN_SX_CP_SFT 3
+#define RG_TURISMO_TRX_EN_SX_CP_HI 3
+#define RG_TURISMO_TRX_EN_SX_CP_SZ 1
+#define RG_TURISMO_TRX_EN_SX_DIV_MAN_MSK 0x00000010
+#define RG_TURISMO_TRX_EN_SX_DIV_MAN_I_MSK 0xffffffef
+#define RG_TURISMO_TRX_EN_SX_DIV_MAN_SFT 4
+#define RG_TURISMO_TRX_EN_SX_DIV_MAN_HI 4
+#define RG_TURISMO_TRX_EN_SX_DIV_MAN_SZ 1
+#define RG_TURISMO_TRX_EN_SX_DIV_MSK 0x00000020
+#define RG_TURISMO_TRX_EN_SX_DIV_I_MSK 0xffffffdf
+#define RG_TURISMO_TRX_EN_SX_DIV_SFT 5
+#define RG_TURISMO_TRX_EN_SX_DIV_HI 5
+#define RG_TURISMO_TRX_EN_SX_DIV_SZ 1
+#define RG_TURISMO_TRX_EN_SX_VCO_MAN_MSK 0x00000040
+#define RG_TURISMO_TRX_EN_SX_VCO_MAN_I_MSK 0xffffffbf
+#define RG_TURISMO_TRX_EN_SX_VCO_MAN_SFT 6
+#define RG_TURISMO_TRX_EN_SX_VCO_MAN_HI 6
+#define RG_TURISMO_TRX_EN_SX_VCO_MAN_SZ 1
+#define RG_TURISMO_TRX_EN_SX_VCO_MSK 0x00000080
+#define RG_TURISMO_TRX_EN_SX_VCO_I_MSK 0xffffff7f
+#define RG_TURISMO_TRX_EN_SX_VCO_SFT 7
+#define RG_TURISMO_TRX_EN_SX_VCO_HI 7
+#define RG_TURISMO_TRX_EN_SX_VCO_SZ 1
+#define RG_TURISMO_TRX_SX_PFD_RST_MAN_MSK 0x00000100
+#define RG_TURISMO_TRX_SX_PFD_RST_MAN_I_MSK 0xfffffeff
+#define RG_TURISMO_TRX_SX_PFD_RST_MAN_SFT 8
+#define RG_TURISMO_TRX_SX_PFD_RST_MAN_HI 8
+#define RG_TURISMO_TRX_SX_PFD_RST_MAN_SZ 1
+#define RG_TURISMO_TRX_SX_PFD_RST_MSK 0x00000200
+#define RG_TURISMO_TRX_SX_PFD_RST_I_MSK 0xfffffdff
+#define RG_TURISMO_TRX_SX_PFD_RST_SFT 9
+#define RG_TURISMO_TRX_SX_PFD_RST_HI 9
+#define RG_TURISMO_TRX_SX_PFD_RST_SZ 1
+#define RG_TURISMO_TRX_SX_UOP_MAN_MSK 0x00000400
+#define RG_TURISMO_TRX_SX_UOP_MAN_I_MSK 0xfffffbff
+#define RG_TURISMO_TRX_SX_UOP_MAN_SFT 10
+#define RG_TURISMO_TRX_SX_UOP_MAN_HI 10
+#define RG_TURISMO_TRX_SX_UOP_MAN_SZ 1
+#define RG_TURISMO_TRX_SX_UOP_EN_MSK 0x00000800
+#define RG_TURISMO_TRX_SX_UOP_EN_I_MSK 0xfffff7ff
+#define RG_TURISMO_TRX_SX_UOP_EN_SFT 11
+#define RG_TURISMO_TRX_SX_UOP_EN_HI 11
+#define RG_TURISMO_TRX_SX_UOP_EN_SZ 1
+#define RG_TURISMO_TRX_EN_VCOBF_TXMB_MAN_MSK 0x00001000
+#define RG_TURISMO_TRX_EN_VCOBF_TXMB_MAN_I_MSK 0xffffefff
+#define RG_TURISMO_TRX_EN_VCOBF_TXMB_MAN_SFT 12
+#define RG_TURISMO_TRX_EN_VCOBF_TXMB_MAN_HI 12
+#define RG_TURISMO_TRX_EN_VCOBF_TXMB_MAN_SZ 1
+#define RG_TURISMO_TRX_EN_VCOBF_TXMB_MSK 0x00002000
+#define RG_TURISMO_TRX_EN_VCOBF_TXMB_I_MSK 0xffffdfff
+#define RG_TURISMO_TRX_EN_VCOBF_TXMB_SFT 13
+#define RG_TURISMO_TRX_EN_VCOBF_TXMB_HI 13
+#define RG_TURISMO_TRX_EN_VCOBF_TXMB_SZ 1
+#define RG_TURISMO_TRX_EN_VCOBF_TXOB_MAN_MSK 0x00004000
+#define RG_TURISMO_TRX_EN_VCOBF_TXOB_MAN_I_MSK 0xffffbfff
+#define RG_TURISMO_TRX_EN_VCOBF_TXOB_MAN_SFT 14
+#define RG_TURISMO_TRX_EN_VCOBF_TXOB_MAN_HI 14
+#define RG_TURISMO_TRX_EN_VCOBF_TXOB_MAN_SZ 1
+#define RG_TURISMO_TRX_EN_VCOBF_TXOB_MSK 0x00008000
+#define RG_TURISMO_TRX_EN_VCOBF_TXOB_I_MSK 0xffff7fff
+#define RG_TURISMO_TRX_EN_VCOBF_TXOB_SFT 15
+#define RG_TURISMO_TRX_EN_VCOBF_TXOB_HI 15
+#define RG_TURISMO_TRX_EN_VCOBF_TXOB_SZ 1
+#define RG_TURISMO_TRX_EN_VCOBF_RXMB_MAN_MSK 0x00010000
+#define RG_TURISMO_TRX_EN_VCOBF_RXMB_MAN_I_MSK 0xfffeffff
+#define RG_TURISMO_TRX_EN_VCOBF_RXMB_MAN_SFT 16
+#define RG_TURISMO_TRX_EN_VCOBF_RXMB_MAN_HI 16
+#define RG_TURISMO_TRX_EN_VCOBF_RXMB_MAN_SZ 1
+#define RG_TURISMO_TRX_EN_VCOBF_RXMB_MSK 0x00020000
+#define RG_TURISMO_TRX_EN_VCOBF_RXMB_I_MSK 0xfffdffff
+#define RG_TURISMO_TRX_EN_VCOBF_RXMB_SFT 17
+#define RG_TURISMO_TRX_EN_VCOBF_RXMB_HI 17
+#define RG_TURISMO_TRX_EN_VCOBF_RXMB_SZ 1
+#define RG_TURISMO_TRX_EN_VCOBF_RXOB_MAN_MSK 0x00040000
+#define RG_TURISMO_TRX_EN_VCOBF_RXOB_MAN_I_MSK 0xfffbffff
+#define RG_TURISMO_TRX_EN_VCOBF_RXOB_MAN_SFT 18
+#define RG_TURISMO_TRX_EN_VCOBF_RXOB_MAN_HI 18
+#define RG_TURISMO_TRX_EN_VCOBF_RXOB_MAN_SZ 1
+#define RG_TURISMO_TRX_EN_VCOBF_RXOB_MSK 0x00080000
+#define RG_TURISMO_TRX_EN_VCOBF_RXOB_I_MSK 0xfff7ffff
+#define RG_TURISMO_TRX_EN_VCOBF_RXOB_SFT 19
+#define RG_TURISMO_TRX_EN_VCOBF_RXOB_HI 19
+#define RG_TURISMO_TRX_EN_VCOBF_RXOB_SZ 1
+#define RG_TURISMO_TRX_EN_VCOBF_DIVCK_MAN_MSK 0x00100000
+#define RG_TURISMO_TRX_EN_VCOBF_DIVCK_MAN_I_MSK 0xffefffff
+#define RG_TURISMO_TRX_EN_VCOBF_DIVCK_MAN_SFT 20
+#define RG_TURISMO_TRX_EN_VCOBF_DIVCK_MAN_HI 20
+#define RG_TURISMO_TRX_EN_VCOBF_DIVCK_MAN_SZ 1
+#define RG_TURISMO_TRX_EN_VCOBF_DIVCK_MSK 0x00200000
+#define RG_TURISMO_TRX_EN_VCOBF_DIVCK_I_MSK 0xffdfffff
+#define RG_TURISMO_TRX_EN_VCOBF_DIVCK_SFT 21
+#define RG_TURISMO_TRX_EN_VCOBF_DIVCK_HI 21
+#define RG_TURISMO_TRX_EN_VCOBF_DIVCK_SZ 1
+#define RG_TURISMO_TRX_SX_SBCAL_DIS_MSK 0x00800000
+#define RG_TURISMO_TRX_SX_SBCAL_DIS_I_MSK 0xff7fffff
+#define RG_TURISMO_TRX_SX_SBCAL_DIS_SFT 23
+#define RG_TURISMO_TRX_SX_SBCAL_DIS_HI 23
+#define RG_TURISMO_TRX_SX_SBCAL_DIS_SZ 1
+#define RG_TURISMO_TRX_SX_SBCAL_AW_MSK 0x01000000
+#define RG_TURISMO_TRX_SX_SBCAL_AW_I_MSK 0xfeffffff
+#define RG_TURISMO_TRX_SX_SBCAL_AW_SFT 24
+#define RG_TURISMO_TRX_SX_SBCAL_AW_HI 24
+#define RG_TURISMO_TRX_SX_SBCAL_AW_SZ 1
+#define RG_TURISMO_TRX_SX_AAC_DIS_MSK 0x04000000
+#define RG_TURISMO_TRX_SX_AAC_DIS_I_MSK 0xfbffffff
+#define RG_TURISMO_TRX_SX_AAC_DIS_SFT 26
+#define RG_TURISMO_TRX_SX_AAC_DIS_HI 26
+#define RG_TURISMO_TRX_SX_AAC_DIS_SZ 1
+#define RG_TURISMO_TRX_SX_TTL_DIS_MSK 0x08000000
+#define RG_TURISMO_TRX_SX_TTL_DIS_I_MSK 0xf7ffffff
+#define RG_TURISMO_TRX_SX_TTL_DIS_SFT 27
+#define RG_TURISMO_TRX_SX_TTL_DIS_HI 27
+#define RG_TURISMO_TRX_SX_TTL_DIS_SZ 1
+#define RG_TURISMO_TRX_SX_CAL_INIT_MSK 0xe0000000
+#define RG_TURISMO_TRX_SX_CAL_INIT_I_MSK 0x1fffffff
+#define RG_TURISMO_TRX_SX_CAL_INIT_SFT 29
+#define RG_TURISMO_TRX_SX_CAL_INIT_HI 31
+#define RG_TURISMO_TRX_SX_CAL_INIT_SZ 3
+#define RG_TURISMO_TRX_EN_SX_LDO_MAN_MSK 0x00000001
+#define RG_TURISMO_TRX_EN_SX_LDO_MAN_I_MSK 0xfffffffe
+#define RG_TURISMO_TRX_EN_SX_LDO_MAN_SFT 0
+#define RG_TURISMO_TRX_EN_SX_LDO_MAN_HI 0
+#define RG_TURISMO_TRX_EN_SX_LDO_MAN_SZ 1
+#define RG_TURISMO_TRX_EN_LDO_CP_MSK 0x00000002
+#define RG_TURISMO_TRX_EN_LDO_CP_I_MSK 0xfffffffd
+#define RG_TURISMO_TRX_EN_LDO_CP_SFT 1
+#define RG_TURISMO_TRX_EN_LDO_CP_HI 1
+#define RG_TURISMO_TRX_EN_LDO_CP_SZ 1
+#define RG_TURISMO_TRX_EN_LDO_DIV_MSK 0x00000004
+#define RG_TURISMO_TRX_EN_LDO_DIV_I_MSK 0xfffffffb
+#define RG_TURISMO_TRX_EN_LDO_DIV_SFT 2
+#define RG_TURISMO_TRX_EN_LDO_DIV_HI 2
+#define RG_TURISMO_TRX_EN_LDO_DIV_SZ 1
+#define RG_TURISMO_TRX_EN_LDO_LO_MSK 0x00000008
+#define RG_TURISMO_TRX_EN_LDO_LO_I_MSK 0xfffffff7
+#define RG_TURISMO_TRX_EN_LDO_LO_SFT 3
+#define RG_TURISMO_TRX_EN_LDO_LO_HI 3
+#define RG_TURISMO_TRX_EN_LDO_LO_SZ 1
+#define RG_TURISMO_TRX_EN_LDO_VCO_MSK 0x00000010
+#define RG_TURISMO_TRX_EN_LDO_VCO_I_MSK 0xffffffef
+#define RG_TURISMO_TRX_EN_LDO_VCO_SFT 4
+#define RG_TURISMO_TRX_EN_LDO_VCO_HI 4
+#define RG_TURISMO_TRX_EN_LDO_VCO_SZ 1
+#define RG_TURISMO_TRX_EN_LDO_VCO_PSW_MSK 0x00000200
+#define RG_TURISMO_TRX_EN_LDO_VCO_PSW_I_MSK 0xfffffdff
+#define RG_TURISMO_TRX_EN_LDO_VCO_PSW_SFT 9
+#define RG_TURISMO_TRX_EN_LDO_VCO_PSW_HI 9
+#define RG_TURISMO_TRX_EN_LDO_VCO_PSW_SZ 1
+#define RG_TURISMO_TRX_EN_LDO_VCO_VDD33_MSK 0x00000400
+#define RG_TURISMO_TRX_EN_LDO_VCO_VDD33_I_MSK 0xfffffbff
+#define RG_TURISMO_TRX_EN_LDO_VCO_VDD33_SFT 10
+#define RG_TURISMO_TRX_EN_LDO_VCO_VDD33_HI 10
+#define RG_TURISMO_TRX_EN_LDO_VCO_VDD33_SZ 1
+#define RG_TURISMO_TRX_EN_LDO_CP_IQUP_MSK 0x00000800
+#define RG_TURISMO_TRX_EN_LDO_CP_IQUP_I_MSK 0xfffff7ff
+#define RG_TURISMO_TRX_EN_LDO_CP_IQUP_SFT 11
+#define RG_TURISMO_TRX_EN_LDO_CP_IQUP_HI 11
+#define RG_TURISMO_TRX_EN_LDO_CP_IQUP_SZ 1
+#define RG_TURISMO_TRX_EN_LDO_DIV_IQUP_MSK 0x00001000
+#define RG_TURISMO_TRX_EN_LDO_DIV_IQUP_I_MSK 0xffffefff
+#define RG_TURISMO_TRX_EN_LDO_DIV_IQUP_SFT 12
+#define RG_TURISMO_TRX_EN_LDO_DIV_IQUP_HI 12
+#define RG_TURISMO_TRX_EN_LDO_DIV_IQUP_SZ 1
+#define RG_TURISMO_TRX_EN_LDO_LO_IQUP_MSK 0x00002000
+#define RG_TURISMO_TRX_EN_LDO_LO_IQUP_I_MSK 0xffffdfff
+#define RG_TURISMO_TRX_EN_LDO_LO_IQUP_SFT 13
+#define RG_TURISMO_TRX_EN_LDO_LO_IQUP_HI 13
+#define RG_TURISMO_TRX_EN_LDO_LO_IQUP_SZ 1
+#define RG_TURISMO_TRX_EN_LDO_VCO_IQUP_MSK 0x00004000
+#define RG_TURISMO_TRX_EN_LDO_VCO_IQUP_I_MSK 0xffffbfff
+#define RG_TURISMO_TRX_EN_LDO_VCO_IQUP_SFT 14
+#define RG_TURISMO_TRX_EN_LDO_VCO_IQUP_HI 14
+#define RG_TURISMO_TRX_EN_LDO_VCO_IQUP_SZ 1
+#define RG_TURISMO_TRX_SX_LDO_FCOFFT_MSK 0x00380000
+#define RG_TURISMO_TRX_SX_LDO_FCOFFT_I_MSK 0xffc7ffff
+#define RG_TURISMO_TRX_SX_LDO_FCOFFT_SFT 19
+#define RG_TURISMO_TRX_SX_LDO_FCOFFT_HI 21
+#define RG_TURISMO_TRX_SX_LDO_FCOFFT_SZ 3
+#define RG_TURISMO_TRX_LDO_CP_FC_MAN_MSK 0x00400000
+#define RG_TURISMO_TRX_LDO_CP_FC_MAN_I_MSK 0xffbfffff
+#define RG_TURISMO_TRX_LDO_CP_FC_MAN_SFT 22
+#define RG_TURISMO_TRX_LDO_CP_FC_MAN_HI 22
+#define RG_TURISMO_TRX_LDO_CP_FC_MAN_SZ 1
+#define RG_TURISMO_TRX_LDO_CP_FC_MSK 0x00800000
+#define RG_TURISMO_TRX_LDO_CP_FC_I_MSK 0xff7fffff
+#define RG_TURISMO_TRX_LDO_CP_FC_SFT 23
+#define RG_TURISMO_TRX_LDO_CP_FC_HI 23
+#define RG_TURISMO_TRX_LDO_CP_FC_SZ 1
+#define RG_TURISMO_TRX_LDO_DIV_FC_MAN_MSK 0x01000000
+#define RG_TURISMO_TRX_LDO_DIV_FC_MAN_I_MSK 0xfeffffff
+#define RG_TURISMO_TRX_LDO_DIV_FC_MAN_SFT 24
+#define RG_TURISMO_TRX_LDO_DIV_FC_MAN_HI 24
+#define RG_TURISMO_TRX_LDO_DIV_FC_MAN_SZ 1
+#define RG_TURISMO_TRX_LDO_DIV_FC_MSK 0x02000000
+#define RG_TURISMO_TRX_LDO_DIV_FC_I_MSK 0xfdffffff
+#define RG_TURISMO_TRX_LDO_DIV_FC_SFT 25
+#define RG_TURISMO_TRX_LDO_DIV_FC_HI 25
+#define RG_TURISMO_TRX_LDO_DIV_FC_SZ 1
+#define RG_TURISMO_TRX_LDO_LO_FC_MAN_MSK 0x04000000
+#define RG_TURISMO_TRX_LDO_LO_FC_MAN_I_MSK 0xfbffffff
+#define RG_TURISMO_TRX_LDO_LO_FC_MAN_SFT 26
+#define RG_TURISMO_TRX_LDO_LO_FC_MAN_HI 26
+#define RG_TURISMO_TRX_LDO_LO_FC_MAN_SZ 1
+#define RG_TURISMO_TRX_LDO_LO_FC_MSK 0x08000000
+#define RG_TURISMO_TRX_LDO_LO_FC_I_MSK 0xf7ffffff
+#define RG_TURISMO_TRX_LDO_LO_FC_SFT 27
+#define RG_TURISMO_TRX_LDO_LO_FC_HI 27
+#define RG_TURISMO_TRX_LDO_LO_FC_SZ 1
+#define RG_TURISMO_TRX_LDO_VCO_FC_MAN_MSK 0x10000000
+#define RG_TURISMO_TRX_LDO_VCO_FC_MAN_I_MSK 0xefffffff
+#define RG_TURISMO_TRX_LDO_VCO_FC_MAN_SFT 28
+#define RG_TURISMO_TRX_LDO_VCO_FC_MAN_HI 28
+#define RG_TURISMO_TRX_LDO_VCO_FC_MAN_SZ 1
+#define RG_TURISMO_TRX_LDO_VCO_FC_MSK 0x20000000
+#define RG_TURISMO_TRX_LDO_VCO_FC_I_MSK 0xdfffffff
+#define RG_TURISMO_TRX_LDO_VCO_FC_SFT 29
+#define RG_TURISMO_TRX_LDO_VCO_FC_HI 29
+#define RG_TURISMO_TRX_LDO_VCO_FC_SZ 1
+#define RG_TURISMO_TRX_LDO_VCO_RCF_MSK 0xc0000000
+#define RG_TURISMO_TRX_LDO_VCO_RCF_I_MSK 0x3fffffff
+#define RG_TURISMO_TRX_LDO_VCO_RCF_SFT 30
+#define RG_TURISMO_TRX_LDO_VCO_RCF_HI 31
+#define RG_TURISMO_TRX_LDO_VCO_RCF_SZ 2
+#define RG_TURISMO_TRX_SX_RFCTRL_F_MSK 0x00ffffff
+#define RG_TURISMO_TRX_SX_RFCTRL_F_I_MSK 0xff000000
+#define RG_TURISMO_TRX_SX_RFCTRL_F_SFT 0
+#define RG_TURISMO_TRX_SX_RFCTRL_F_HI 23
+#define RG_TURISMO_TRX_SX_RFCTRL_F_SZ 24
+#define RG_TURISMO_TRX_SX_RFCTRL_CH_7_0_MSK 0xff000000
+#define RG_TURISMO_TRX_SX_RFCTRL_CH_7_0_I_MSK 0x00ffffff
+#define RG_TURISMO_TRX_SX_RFCTRL_CH_7_0_SFT 24
+#define RG_TURISMO_TRX_SX_RFCTRL_CH_7_0_HI 31
+#define RG_TURISMO_TRX_SX_RFCTRL_CH_7_0_SZ 8
+#define RG_TURISMO_TRX_SX_RFCTRL_CH_10_8_MSK 0x00000007
+#define RG_TURISMO_TRX_SX_RFCTRL_CH_10_8_I_MSK 0xfffffff8
+#define RG_TURISMO_TRX_SX_RFCTRL_CH_10_8_SFT 0
+#define RG_TURISMO_TRX_SX_RFCTRL_CH_10_8_HI 2
+#define RG_TURISMO_TRX_SX_RFCTRL_CH_10_8_SZ 3
+#define RG_TURISMO_TRX_SX_RFCH_MAP_EN_MSK 0x00000008
+#define RG_TURISMO_TRX_SX_RFCH_MAP_EN_I_MSK 0xfffffff7
+#define RG_TURISMO_TRX_SX_RFCH_MAP_EN_SFT 3
+#define RG_TURISMO_TRX_SX_RFCH_MAP_EN_HI 3
+#define RG_TURISMO_TRX_SX_RFCH_MAP_EN_SZ 1
+#define RG_TURISMO_TRX_SX_XTAL_FREQ_MSK 0x00000060
+#define RG_TURISMO_TRX_SX_XTAL_FREQ_I_MSK 0xffffff9f
+#define RG_TURISMO_TRX_SX_XTAL_FREQ_SFT 5
+#define RG_TURISMO_TRX_SX_XTAL_FREQ_HI 6
+#define RG_TURISMO_TRX_SX_XTAL_FREQ_SZ 2
+#define RG_TURISMO_TRX_SX_FREF_DOUB_MSK 0x00000080
+#define RG_TURISMO_TRX_SX_FREF_DOUB_I_MSK 0xffffff7f
+#define RG_TURISMO_TRX_SX_FREF_DOUB_SFT 7
+#define RG_TURISMO_TRX_SX_FREF_DOUB_HI 7
+#define RG_TURISMO_TRX_SX_FREF_DOUB_SZ 1
+#define RG_TURISMO_TRX_SX_BTRX_SIDE_MSK 0x00000100
+#define RG_TURISMO_TRX_SX_BTRX_SIDE_I_MSK 0xfffffeff
+#define RG_TURISMO_TRX_SX_BTRX_SIDE_SFT 8
+#define RG_TURISMO_TRX_SX_BTRX_SIDE_HI 8
+#define RG_TURISMO_TRX_SX_BTRX_SIDE_SZ 1
+#define RG_TURISMO_TRX_SX_LO_TIMES_MSK 0x00000200
+#define RG_TURISMO_TRX_SX_LO_TIMES_I_MSK 0xfffffdff
+#define RG_TURISMO_TRX_SX_LO_TIMES_SFT 9
+#define RG_TURISMO_TRX_SX_LO_TIMES_HI 9
+#define RG_TURISMO_TRX_SX_LO_TIMES_SZ 1
+#define RG_TURISMO_TRX_SX_CHANNEL_MSK 0x0007f800
+#define RG_TURISMO_TRX_SX_CHANNEL_I_MSK 0xfff807ff
+#define RG_TURISMO_TRX_SX_CHANNEL_SFT 11
+#define RG_TURISMO_TRX_SX_CHANNEL_HI 18
+#define RG_TURISMO_TRX_SX_CHANNEL_SZ 8
+#define RG_TURISMO_TRX_SX_CP_ISEL_BT_MSK 0x0000000f
+#define RG_TURISMO_TRX_SX_CP_ISEL_BT_I_MSK 0xfffffff0
+#define RG_TURISMO_TRX_SX_CP_ISEL_BT_SFT 0
+#define RG_TURISMO_TRX_SX_CP_ISEL_BT_HI 3
+#define RG_TURISMO_TRX_SX_CP_ISEL_BT_SZ 4
+#define RG_TURISMO_TRX_SX_CP_ISEL50U_BT_MSK 0x00000010
+#define RG_TURISMO_TRX_SX_CP_ISEL50U_BT_I_MSK 0xffffffef
+#define RG_TURISMO_TRX_SX_CP_ISEL50U_BT_SFT 4
+#define RG_TURISMO_TRX_SX_CP_ISEL50U_BT_HI 4
+#define RG_TURISMO_TRX_SX_CP_ISEL50U_BT_SZ 1
+#define RG_TURISMO_TRX_SX_CP_KP_DOUB_BT_MSK 0x00000020
+#define RG_TURISMO_TRX_SX_CP_KP_DOUB_BT_I_MSK 0xffffffdf
+#define RG_TURISMO_TRX_SX_CP_KP_DOUB_BT_SFT 5
+#define RG_TURISMO_TRX_SX_CP_KP_DOUB_BT_HI 5
+#define RG_TURISMO_TRX_SX_CP_KP_DOUB_BT_SZ 1
+#define RG_TURISMO_TRX_SX_CP_ISEL_WF_MSK 0x00000780
+#define RG_TURISMO_TRX_SX_CP_ISEL_WF_I_MSK 0xfffff87f
+#define RG_TURISMO_TRX_SX_CP_ISEL_WF_SFT 7
+#define RG_TURISMO_TRX_SX_CP_ISEL_WF_HI 10
+#define RG_TURISMO_TRX_SX_CP_ISEL_WF_SZ 4
+#define RG_TURISMO_TRX_SX_CP_ISEL50U_WF_MSK 0x00000800
+#define RG_TURISMO_TRX_SX_CP_ISEL50U_WF_I_MSK 0xfffff7ff
+#define RG_TURISMO_TRX_SX_CP_ISEL50U_WF_SFT 11
+#define RG_TURISMO_TRX_SX_CP_ISEL50U_WF_HI 11
+#define RG_TURISMO_TRX_SX_CP_ISEL50U_WF_SZ 1
+#define RG_TURISMO_TRX_SX_CP_KP_DOUB_WF_MSK 0x00001000
+#define RG_TURISMO_TRX_SX_CP_KP_DOUB_WF_I_MSK 0xffffefff
+#define RG_TURISMO_TRX_SX_CP_KP_DOUB_WF_SFT 12
+#define RG_TURISMO_TRX_SX_CP_KP_DOUB_WF_HI 12
+#define RG_TURISMO_TRX_SX_CP_KP_DOUB_WF_SZ 1
+#define RG_TURISMO_TRX_SX_CP_IOST_POL_MSK 0x00008000
+#define RG_TURISMO_TRX_SX_CP_IOST_POL_I_MSK 0xffff7fff
+#define RG_TURISMO_TRX_SX_CP_IOST_POL_SFT 15
+#define RG_TURISMO_TRX_SX_CP_IOST_POL_HI 15
+#define RG_TURISMO_TRX_SX_CP_IOST_POL_SZ 1
+#define RG_TURISMO_TRX_SX_CP_IOST_MSK 0x00070000
+#define RG_TURISMO_TRX_SX_CP_IOST_I_MSK 0xfff8ffff
+#define RG_TURISMO_TRX_SX_CP_IOST_SFT 16
+#define RG_TURISMO_TRX_SX_CP_IOST_HI 18
+#define RG_TURISMO_TRX_SX_CP_IOST_SZ 3
+#define RG_TURISMO_TRX_SX_PFD_SEL_MSK 0x00400000
+#define RG_TURISMO_TRX_SX_PFD_SEL_I_MSK 0xffbfffff
+#define RG_TURISMO_TRX_SX_PFD_SEL_SFT 22
+#define RG_TURISMO_TRX_SX_PFD_SEL_HI 22
+#define RG_TURISMO_TRX_SX_PFD_SEL_SZ 1
+#define RG_TURISMO_TRX_SX_PFD_SET_MSK 0x00800000
+#define RG_TURISMO_TRX_SX_PFD_SET_I_MSK 0xff7fffff
+#define RG_TURISMO_TRX_SX_PFD_SET_SFT 23
+#define RG_TURISMO_TRX_SX_PFD_SET_HI 23
+#define RG_TURISMO_TRX_SX_PFD_SET_SZ 1
+#define RG_TURISMO_TRX_SX_PFD_SET1_MSK 0x01000000
+#define RG_TURISMO_TRX_SX_PFD_SET1_I_MSK 0xfeffffff
+#define RG_TURISMO_TRX_SX_PFD_SET1_SFT 24
+#define RG_TURISMO_TRX_SX_PFD_SET1_HI 24
+#define RG_TURISMO_TRX_SX_PFD_SET1_SZ 1
+#define RG_TURISMO_TRX_SX_PFD_SET2_MSK 0x02000000
+#define RG_TURISMO_TRX_SX_PFD_SET2_I_MSK 0xfdffffff
+#define RG_TURISMO_TRX_SX_PFD_SET2_SFT 25
+#define RG_TURISMO_TRX_SX_PFD_SET2_HI 25
+#define RG_TURISMO_TRX_SX_PFD_SET2_SZ 1
+#define RG_TURISMO_TRX_SX_PFD_REF_EDGE_MSK 0x04000000
+#define RG_TURISMO_TRX_SX_PFD_REF_EDGE_I_MSK 0xfbffffff
+#define RG_TURISMO_TRX_SX_PFD_REF_EDGE_SFT 26
+#define RG_TURISMO_TRX_SX_PFD_REF_EDGE_HI 26
+#define RG_TURISMO_TRX_SX_PFD_REF_EDGE_SZ 1
+#define RG_TURISMO_TRX_SX_PFD_DIV_EDGE_MSK 0x08000000
+#define RG_TURISMO_TRX_SX_PFD_DIV_EDGE_I_MSK 0xf7ffffff
+#define RG_TURISMO_TRX_SX_PFD_DIV_EDGE_SFT 27
+#define RG_TURISMO_TRX_SX_PFD_DIV_EDGE_HI 27
+#define RG_TURISMO_TRX_SX_PFD_DIV_EDGE_SZ 1
+#define RG_TURISMO_TRX_SX_PFD_TRUP_MSK 0x10000000
+#define RG_TURISMO_TRX_SX_PFD_TRUP_I_MSK 0xefffffff
+#define RG_TURISMO_TRX_SX_PFD_TRUP_SFT 28
+#define RG_TURISMO_TRX_SX_PFD_TRUP_HI 28
+#define RG_TURISMO_TRX_SX_PFD_TRUP_SZ 1
+#define RG_TURISMO_TRX_SX_PFD_TRDN_MSK 0x20000000
+#define RG_TURISMO_TRX_SX_PFD_TRDN_I_MSK 0xdfffffff
+#define RG_TURISMO_TRX_SX_PFD_TRDN_SFT 29
+#define RG_TURISMO_TRX_SX_PFD_TRDN_HI 29
+#define RG_TURISMO_TRX_SX_PFD_TRDN_SZ 1
+#define RG_TURISMO_TRX_SX_PFD_TLSEL_MSK 0x40000000
+#define RG_TURISMO_TRX_SX_PFD_TLSEL_I_MSK 0xbfffffff
+#define RG_TURISMO_TRX_SX_PFD_TLSEL_SFT 30
+#define RG_TURISMO_TRX_SX_PFD_TLSEL_HI 30
+#define RG_TURISMO_TRX_SX_PFD_TLSEL_SZ 1
+#define RG_TURISMO_TRX_SX_LPF_C1_BT_MSK 0x0000000f
+#define RG_TURISMO_TRX_SX_LPF_C1_BT_I_MSK 0xfffffff0
+#define RG_TURISMO_TRX_SX_LPF_C1_BT_SFT 0
+#define RG_TURISMO_TRX_SX_LPF_C1_BT_HI 3
+#define RG_TURISMO_TRX_SX_LPF_C1_BT_SZ 4
+#define RG_TURISMO_TRX_SX_LPF_C2_BT_MSK 0x000000f0
+#define RG_TURISMO_TRX_SX_LPF_C2_BT_I_MSK 0xffffff0f
+#define RG_TURISMO_TRX_SX_LPF_C2_BT_SFT 4
+#define RG_TURISMO_TRX_SX_LPF_C2_BT_HI 7
+#define RG_TURISMO_TRX_SX_LPF_C2_BT_SZ 4
+#define RG_TURISMO_TRX_SX_LPF_C3_BT_MSK 0x00000100
+#define RG_TURISMO_TRX_SX_LPF_C3_BT_I_MSK 0xfffffeff
+#define RG_TURISMO_TRX_SX_LPF_C3_BT_SFT 8
+#define RG_TURISMO_TRX_SX_LPF_C3_BT_HI 8
+#define RG_TURISMO_TRX_SX_LPF_C3_BT_SZ 1
+#define RG_TURISMO_TRX_SX_LPF_R2_BT_MSK 0x00001e00
+#define RG_TURISMO_TRX_SX_LPF_R2_BT_I_MSK 0xffffe1ff
+#define RG_TURISMO_TRX_SX_LPF_R2_BT_SFT 9
+#define RG_TURISMO_TRX_SX_LPF_R2_BT_HI 12
+#define RG_TURISMO_TRX_SX_LPF_R2_BT_SZ 4
+#define RG_TURISMO_TRX_SX_LPF_R3_BT_MSK 0x0000e000
+#define RG_TURISMO_TRX_SX_LPF_R3_BT_I_MSK 0xffff1fff
+#define RG_TURISMO_TRX_SX_LPF_R3_BT_SFT 13
+#define RG_TURISMO_TRX_SX_LPF_R3_BT_HI 15
+#define RG_TURISMO_TRX_SX_LPF_R3_BT_SZ 3
+#define RG_TURISMO_TRX_SX_LPF_C1_WF_MSK 0x000f0000
+#define RG_TURISMO_TRX_SX_LPF_C1_WF_I_MSK 0xfff0ffff
+#define RG_TURISMO_TRX_SX_LPF_C1_WF_SFT 16
+#define RG_TURISMO_TRX_SX_LPF_C1_WF_HI 19
+#define RG_TURISMO_TRX_SX_LPF_C1_WF_SZ 4
+#define RG_TURISMO_TRX_SX_LPF_C2_WF_MSK 0x00f00000
+#define RG_TURISMO_TRX_SX_LPF_C2_WF_I_MSK 0xff0fffff
+#define RG_TURISMO_TRX_SX_LPF_C2_WF_SFT 20
+#define RG_TURISMO_TRX_SX_LPF_C2_WF_HI 23
+#define RG_TURISMO_TRX_SX_LPF_C2_WF_SZ 4
+#define RG_TURISMO_TRX_SX_LPF_C3_WF_MSK 0x01000000
+#define RG_TURISMO_TRX_SX_LPF_C3_WF_I_MSK 0xfeffffff
+#define RG_TURISMO_TRX_SX_LPF_C3_WF_SFT 24
+#define RG_TURISMO_TRX_SX_LPF_C3_WF_HI 24
+#define RG_TURISMO_TRX_SX_LPF_C3_WF_SZ 1
+#define RG_TURISMO_TRX_SX_LPF_R2_WF_MSK 0x1e000000
+#define RG_TURISMO_TRX_SX_LPF_R2_WF_I_MSK 0xe1ffffff
+#define RG_TURISMO_TRX_SX_LPF_R2_WF_SFT 25
+#define RG_TURISMO_TRX_SX_LPF_R2_WF_HI 28
+#define RG_TURISMO_TRX_SX_LPF_R2_WF_SZ 4
+#define RG_TURISMO_TRX_SX_LPF_R3_WF_MSK 0xe0000000
+#define RG_TURISMO_TRX_SX_LPF_R3_WF_I_MSK 0x1fffffff
+#define RG_TURISMO_TRX_SX_LPF_R3_WF_SFT 29
+#define RG_TURISMO_TRX_SX_LPF_R3_WF_HI 31
+#define RG_TURISMO_TRX_SX_LPF_R3_WF_SZ 3
+#define RG_TURISMO_TRX_SX_VCO_ISEL_MAN_MSK 0x00000001
+#define RG_TURISMO_TRX_SX_VCO_ISEL_MAN_I_MSK 0xfffffffe
+#define RG_TURISMO_TRX_SX_VCO_ISEL_MAN_SFT 0
+#define RG_TURISMO_TRX_SX_VCO_ISEL_MAN_HI 0
+#define RG_TURISMO_TRX_SX_VCO_ISEL_MAN_SZ 1
+#define RG_TURISMO_TRX_SX_VCO_ISEL_BT_MSK 0x0000001e
+#define RG_TURISMO_TRX_SX_VCO_ISEL_BT_I_MSK 0xffffffe1
+#define RG_TURISMO_TRX_SX_VCO_ISEL_BT_SFT 1
+#define RG_TURISMO_TRX_SX_VCO_ISEL_BT_HI 4
+#define RG_TURISMO_TRX_SX_VCO_ISEL_BT_SZ 4
+#define RG_TURISMO_TRX_SX_VCO_LPM_BT_MSK 0x00000020
+#define RG_TURISMO_TRX_SX_VCO_LPM_BT_I_MSK 0xffffffdf
+#define RG_TURISMO_TRX_SX_VCO_LPM_BT_SFT 5
+#define RG_TURISMO_TRX_SX_VCO_LPM_BT_HI 5
+#define RG_TURISMO_TRX_SX_VCO_LPM_BT_SZ 1
+#define RG_TURISMO_TRX_SX_VCO_VCCBSEL_BT_MSK 0x000001c0
+#define RG_TURISMO_TRX_SX_VCO_VCCBSEL_BT_I_MSK 0xfffffe3f
+#define RG_TURISMO_TRX_SX_VCO_VCCBSEL_BT_SFT 6
+#define RG_TURISMO_TRX_SX_VCO_VCCBSEL_BT_HI 8
+#define RG_TURISMO_TRX_SX_VCO_VCCBSEL_BT_SZ 3
+#define RG_TURISMO_TRX_SX_VCO_KVDOUB_BT_MSK 0x00000200
+#define RG_TURISMO_TRX_SX_VCO_KVDOUB_BT_I_MSK 0xfffffdff
+#define RG_TURISMO_TRX_SX_VCO_KVDOUB_BT_SFT 9
+#define RG_TURISMO_TRX_SX_VCO_KVDOUB_BT_HI 9
+#define RG_TURISMO_TRX_SX_VCO_KVDOUB_BT_SZ 1
+#define RG_TURISMO_TRX_SX_VCO_ISEL_WF_MSK 0x00003c00
+#define RG_TURISMO_TRX_SX_VCO_ISEL_WF_I_MSK 0xffffc3ff
+#define RG_TURISMO_TRX_SX_VCO_ISEL_WF_SFT 10
+#define RG_TURISMO_TRX_SX_VCO_ISEL_WF_HI 13
+#define RG_TURISMO_TRX_SX_VCO_ISEL_WF_SZ 4
+#define RG_TURISMO_TRX_SX_VCO_LPM_WF_MSK 0x00004000
+#define RG_TURISMO_TRX_SX_VCO_LPM_WF_I_MSK 0xffffbfff
+#define RG_TURISMO_TRX_SX_VCO_LPM_WF_SFT 14
+#define RG_TURISMO_TRX_SX_VCO_LPM_WF_HI 14
+#define RG_TURISMO_TRX_SX_VCO_LPM_WF_SZ 1
+#define RG_TURISMO_TRX_SX_VCO_VCCBSEL_WF_MSK 0x00038000
+#define RG_TURISMO_TRX_SX_VCO_VCCBSEL_WF_I_MSK 0xfffc7fff
+#define RG_TURISMO_TRX_SX_VCO_VCCBSEL_WF_SFT 15
+#define RG_TURISMO_TRX_SX_VCO_VCCBSEL_WF_HI 17
+#define RG_TURISMO_TRX_SX_VCO_VCCBSEL_WF_SZ 3
+#define RG_TURISMO_TRX_SX_VCO_KVDOUB_WF_MSK 0x00040000
+#define RG_TURISMO_TRX_SX_VCO_KVDOUB_WF_I_MSK 0xfffbffff
+#define RG_TURISMO_TRX_SX_VCO_KVDOUB_WF_SFT 18
+#define RG_TURISMO_TRX_SX_VCO_KVDOUB_WF_HI 18
+#define RG_TURISMO_TRX_SX_VCO_KVDOUB_WF_SZ 1
+#define RG_TURISMO_TRX_SX_VCO_VARBSEL_MSK 0x00600000
+#define RG_TURISMO_TRX_SX_VCO_VARBSEL_I_MSK 0xff9fffff
+#define RG_TURISMO_TRX_SX_VCO_VARBSEL_SFT 21
+#define RG_TURISMO_TRX_SX_VCO_VARBSEL_HI 22
+#define RG_TURISMO_TRX_SX_VCO_VARBSEL_SZ 2
+#define RG_TURISMO_TRX_SX_VCO_RTAIL_SHIFT_MSK 0x00800000
+#define RG_TURISMO_TRX_SX_VCO_RTAIL_SHIFT_I_MSK 0xff7fffff
+#define RG_TURISMO_TRX_SX_VCO_RTAIL_SHIFT_SFT 23
+#define RG_TURISMO_TRX_SX_VCO_RTAIL_SHIFT_HI 23
+#define RG_TURISMO_TRX_SX_VCO_RTAIL_SHIFT_SZ 1
+#define RG_TURISMO_TRX_SX_VCO_CS_AWH_MSK 0x01000000
+#define RG_TURISMO_TRX_SX_VCO_CS_AWH_I_MSK 0xfeffffff
+#define RG_TURISMO_TRX_SX_VCO_CS_AWH_SFT 24
+#define RG_TURISMO_TRX_SX_VCO_CS_AWH_HI 24
+#define RG_TURISMO_TRX_SX_VCO_CS_AWH_SZ 1
+#define RG_TURISMO_TRX_VOBF_TXMBSEL_BT_MSK 0x00000003
+#define RG_TURISMO_TRX_VOBF_TXMBSEL_BT_I_MSK 0xfffffffc
+#define RG_TURISMO_TRX_VOBF_TXMBSEL_BT_SFT 0
+#define RG_TURISMO_TRX_VOBF_TXMBSEL_BT_HI 1
+#define RG_TURISMO_TRX_VOBF_TXMBSEL_BT_SZ 2
+#define RG_TURISMO_TRX_VOBF_TXOBSEL_BT_MSK 0x0000000c
+#define RG_TURISMO_TRX_VOBF_TXOBSEL_BT_I_MSK 0xfffffff3
+#define RG_TURISMO_TRX_VOBF_TXOBSEL_BT_SFT 2
+#define RG_TURISMO_TRX_VOBF_TXOBSEL_BT_HI 3
+#define RG_TURISMO_TRX_VOBF_TXOBSEL_BT_SZ 2
+#define RG_TURISMO_TRX_VOBF_RXMBSEL_BT_MSK 0x00000030
+#define RG_TURISMO_TRX_VOBF_RXMBSEL_BT_I_MSK 0xffffffcf
+#define RG_TURISMO_TRX_VOBF_RXMBSEL_BT_SFT 4
+#define RG_TURISMO_TRX_VOBF_RXMBSEL_BT_HI 5
+#define RG_TURISMO_TRX_VOBF_RXMBSEL_BT_SZ 2
+#define RG_TURISMO_TRX_VOBF_RXOBSEL_BT_MSK 0x000000c0
+#define RG_TURISMO_TRX_VOBF_RXOBSEL_BT_I_MSK 0xffffff3f
+#define RG_TURISMO_TRX_VOBF_RXOBSEL_BT_SFT 6
+#define RG_TURISMO_TRX_VOBF_RXOBSEL_BT_HI 7
+#define RG_TURISMO_TRX_VOBF_RXOBSEL_BT_SZ 2
+#define RG_TURISMO_TRX_VOBF_TXMBSEL_WF_MSK 0x00000c00
+#define RG_TURISMO_TRX_VOBF_TXMBSEL_WF_I_MSK 0xfffff3ff
+#define RG_TURISMO_TRX_VOBF_TXMBSEL_WF_SFT 10
+#define RG_TURISMO_TRX_VOBF_TXMBSEL_WF_HI 11
+#define RG_TURISMO_TRX_VOBF_TXMBSEL_WF_SZ 2
+#define RG_TURISMO_TRX_VOBF_TXOBSEL_WF_MSK 0x00003000
+#define RG_TURISMO_TRX_VOBF_TXOBSEL_WF_I_MSK 0xffffcfff
+#define RG_TURISMO_TRX_VOBF_TXOBSEL_WF_SFT 12
+#define RG_TURISMO_TRX_VOBF_TXOBSEL_WF_HI 13
+#define RG_TURISMO_TRX_VOBF_TXOBSEL_WF_SZ 2
+#define RG_TURISMO_TRX_VOBF_RXMBSEL_WF_MSK 0x0000c000
+#define RG_TURISMO_TRX_VOBF_RXMBSEL_WF_I_MSK 0xffff3fff
+#define RG_TURISMO_TRX_VOBF_RXMBSEL_WF_SFT 14
+#define RG_TURISMO_TRX_VOBF_RXMBSEL_WF_HI 15
+#define RG_TURISMO_TRX_VOBF_RXMBSEL_WF_SZ 2
+#define RG_TURISMO_TRX_VOBF_RXOBSEL_WF_MSK 0x00030000
+#define RG_TURISMO_TRX_VOBF_RXOBSEL_WF_I_MSK 0xfffcffff
+#define RG_TURISMO_TRX_VOBF_RXOBSEL_WF_SFT 16
+#define RG_TURISMO_TRX_VOBF_RXOBSEL_WF_HI 17
+#define RG_TURISMO_TRX_VOBF_RXOBSEL_WF_SZ 2
+#define RG_TURISMO_TRX_VOBF_DIVBFSEL_MSK 0x00080000
+#define RG_TURISMO_TRX_VOBF_DIVBFSEL_I_MSK 0xfff7ffff
+#define RG_TURISMO_TRX_VOBF_DIVBFSEL_SFT 19
+#define RG_TURISMO_TRX_VOBF_DIVBFSEL_HI 19
+#define RG_TURISMO_TRX_VOBF_DIVBFSEL_SZ 1
+#define RG_TURISMO_TRX_SX_VCO_TXOB_AW_MSK 0x00100000
+#define RG_TURISMO_TRX_SX_VCO_TXOB_AW_I_MSK 0xffefffff
+#define RG_TURISMO_TRX_SX_VCO_TXOB_AW_SFT 20
+#define RG_TURISMO_TRX_SX_VCO_TXOB_AW_HI 20
+#define RG_TURISMO_TRX_SX_VCO_TXOB_AW_SZ 1
+#define RG_TURISMO_TRX_SX_VCO_RXOB_AW_MSK 0x00200000
+#define RG_TURISMO_TRX_SX_VCO_RXOB_AW_I_MSK 0xffdfffff
+#define RG_TURISMO_TRX_SX_VCO_RXOB_AW_SFT 21
+#define RG_TURISMO_TRX_SX_VCO_RXOB_AW_HI 21
+#define RG_TURISMO_TRX_SX_VCO_RXOB_AW_SZ 1
+#define RG_TURISMO_TRX_VOBF_CAPIMB_POL_MSK 0x04000000
+#define RG_TURISMO_TRX_VOBF_CAPIMB_POL_I_MSK 0xfbffffff
+#define RG_TURISMO_TRX_VOBF_CAPIMB_POL_SFT 26
+#define RG_TURISMO_TRX_VOBF_CAPIMB_POL_HI 26
+#define RG_TURISMO_TRX_VOBF_CAPIMB_POL_SZ 1
+#define RG_TURISMO_TRX_VOBF_CAPIMB_MSK 0x38000000
+#define RG_TURISMO_TRX_VOBF_CAPIMB_I_MSK 0xc7ffffff
+#define RG_TURISMO_TRX_VOBF_CAPIMB_SFT 27
+#define RG_TURISMO_TRX_VOBF_CAPIMB_HI 29
+#define RG_TURISMO_TRX_VOBF_CAPIMB_SZ 3
+#define RG_TURISMO_TRX_EN_SX_VCOMON_MSK 0x80000000
+#define RG_TURISMO_TRX_EN_SX_VCOMON_I_MSK 0x7fffffff
+#define RG_TURISMO_TRX_EN_SX_VCOMON_SFT 31
+#define RG_TURISMO_TRX_EN_SX_VCOMON_HI 31
+#define RG_TURISMO_TRX_EN_SX_VCOMON_SZ 1
+#define RG_TURISMO_TRX_SX_DIV_PREVDD_MSK 0x0000000f
+#define RG_TURISMO_TRX_SX_DIV_PREVDD_I_MSK 0xfffffff0
+#define RG_TURISMO_TRX_SX_DIV_PREVDD_SFT 0
+#define RG_TURISMO_TRX_SX_DIV_PREVDD_HI 3
+#define RG_TURISMO_TRX_SX_DIV_PREVDD_SZ 4
+#define RG_TURISMO_TRX_SX_DIV_PSCVDD_MSK 0x000000f0
+#define RG_TURISMO_TRX_SX_DIV_PSCVDD_I_MSK 0xffffff0f
+#define RG_TURISMO_TRX_SX_DIV_PSCVDD_SFT 4
+#define RG_TURISMO_TRX_SX_DIV_PSCVDD_HI 7
+#define RG_TURISMO_TRX_SX_DIV_PSCVDD_SZ 4
+#define RG_TURISMO_TRX_SX_DIV_RST_H_MSK 0x00000200
+#define RG_TURISMO_TRX_SX_DIV_RST_H_I_MSK 0xfffffdff
+#define RG_TURISMO_TRX_SX_DIV_RST_H_SFT 9
+#define RG_TURISMO_TRX_SX_DIV_RST_H_HI 9
+#define RG_TURISMO_TRX_SX_DIV_RST_H_SZ 1
+#define RG_TURISMO_TRX_SX_DIV_SDM_EDGE_MSK 0x00000400
+#define RG_TURISMO_TRX_SX_DIV_SDM_EDGE_I_MSK 0xfffffbff
+#define RG_TURISMO_TRX_SX_DIV_SDM_EDGE_SFT 10
+#define RG_TURISMO_TRX_SX_DIV_SDM_EDGE_HI 10
+#define RG_TURISMO_TRX_SX_DIV_SDM_EDGE_SZ 1
+#define RG_TURISMO_TRX_SX_DIV_DMYBUF_EN_MSK 0x00000800
+#define RG_TURISMO_TRX_SX_DIV_DMYBUF_EN_I_MSK 0xfffff7ff
+#define RG_TURISMO_TRX_SX_DIV_DMYBUF_EN_SFT 11
+#define RG_TURISMO_TRX_SX_DIV_DMYBUF_EN_HI 11
+#define RG_TURISMO_TRX_SX_DIV_DMYBUF_EN_SZ 1
+#define RG_TURISMO_TRX_EN_SX_MOD_MSK 0x00020000
+#define RG_TURISMO_TRX_EN_SX_MOD_I_MSK 0xfffdffff
+#define RG_TURISMO_TRX_EN_SX_MOD_SFT 17
+#define RG_TURISMO_TRX_EN_SX_MOD_HI 17
+#define RG_TURISMO_TRX_EN_SX_MOD_SZ 1
+#define RG_TURISMO_TRX_EN_SX_DITHER_MSK 0x00040000
+#define RG_TURISMO_TRX_EN_SX_DITHER_I_MSK 0xfffbffff
+#define RG_TURISMO_TRX_EN_SX_DITHER_SFT 18
+#define RG_TURISMO_TRX_EN_SX_DITHER_HI 18
+#define RG_TURISMO_TRX_EN_SX_DITHER_SZ 1
+#define RG_TURISMO_TRX_SX_MOD_ORDER_MSK 0x00180000
+#define RG_TURISMO_TRX_SX_MOD_ORDER_I_MSK 0xffe7ffff
+#define RG_TURISMO_TRX_SX_MOD_ORDER_SFT 19
+#define RG_TURISMO_TRX_SX_MOD_ORDER_HI 20
+#define RG_TURISMO_TRX_SX_MOD_ORDER_SZ 2
+#define RG_TURISMO_TRX_SX_DITHER_WEIGHT_MSK 0x00600000
+#define RG_TURISMO_TRX_SX_DITHER_WEIGHT_I_MSK 0xff9fffff
+#define RG_TURISMO_TRX_SX_DITHER_WEIGHT_SFT 21
+#define RG_TURISMO_TRX_SX_DITHER_WEIGHT_HI 22
+#define RG_TURISMO_TRX_SX_DITHER_WEIGHT_SZ 2
+#define RG_TURISMO_TRX_SX_SUB_SEL_MAN_MSK 0x00000001
+#define RG_TURISMO_TRX_SX_SUB_SEL_MAN_I_MSK 0xfffffffe
+#define RG_TURISMO_TRX_SX_SUB_SEL_MAN_SFT 0
+#define RG_TURISMO_TRX_SX_SUB_SEL_MAN_HI 0
+#define RG_TURISMO_TRX_SX_SUB_SEL_MAN_SZ 1
+#define RG_TURISMO_TRX_SX_SUB_SEL_MSK 0x000001fe
+#define RG_TURISMO_TRX_SX_SUB_SEL_I_MSK 0xfffffe01
+#define RG_TURISMO_TRX_SX_SUB_SEL_SFT 1
+#define RG_TURISMO_TRX_SX_SUB_SEL_HI 8
+#define RG_TURISMO_TRX_SX_SUB_SEL_SZ 8
+#define RG_TURISMO_TRX_SX_SUB_C0P5_DIS_MSK 0x00000200
+#define RG_TURISMO_TRX_SX_SUB_C0P5_DIS_I_MSK 0xfffffdff
+#define RG_TURISMO_TRX_SX_SUB_C0P5_DIS_SFT 9
+#define RG_TURISMO_TRX_SX_SUB_C0P5_DIS_HI 9
+#define RG_TURISMO_TRX_SX_SUB_C0P5_DIS_SZ 1
+#define RG_TURISMO_TRX_SX_SBCAL_CT_MSK 0x00000c00
+#define RG_TURISMO_TRX_SX_SBCAL_CT_I_MSK 0xfffff3ff
+#define RG_TURISMO_TRX_SX_SBCAL_CT_SFT 10
+#define RG_TURISMO_TRX_SX_SBCAL_CT_HI 11
+#define RG_TURISMO_TRX_SX_SBCAL_CT_SZ 2
+#define RG_TURISMO_TRX_SX_SBCAL_WT_MSK 0x00001000
+#define RG_TURISMO_TRX_SX_SBCAL_WT_I_MSK 0xffffefff
+#define RG_TURISMO_TRX_SX_SBCAL_WT_SFT 12
+#define RG_TURISMO_TRX_SX_SBCAL_WT_HI 12
+#define RG_TURISMO_TRX_SX_SBCAL_WT_SZ 1
+#define RG_TURISMO_TRX_SX_SBCAL_DIFFMIN_MSK 0x00002000
+#define RG_TURISMO_TRX_SX_SBCAL_DIFFMIN_I_MSK 0xffffdfff
+#define RG_TURISMO_TRX_SX_SBCAL_DIFFMIN_SFT 13
+#define RG_TURISMO_TRX_SX_SBCAL_DIFFMIN_HI 13
+#define RG_TURISMO_TRX_SX_SBCAL_DIFFMIN_SZ 1
+#define RG_TURISMO_TRX_SX_SBCAL_NTARG_MAN_MSK 0x00008000
+#define RG_TURISMO_TRX_SX_SBCAL_NTARG_MAN_I_MSK 0xffff7fff
+#define RG_TURISMO_TRX_SX_SBCAL_NTARG_MAN_SFT 15
+#define RG_TURISMO_TRX_SX_SBCAL_NTARG_MAN_HI 15
+#define RG_TURISMO_TRX_SX_SBCAL_NTARG_MAN_SZ 1
+#define RG_TURISMO_TRX_SX_SBCAL_NTARG_MSK 0xffff0000
+#define RG_TURISMO_TRX_SX_SBCAL_NTARG_I_MSK 0x0000ffff
+#define RG_TURISMO_TRX_SX_SBCAL_NTARG_SFT 16
+#define RG_TURISMO_TRX_SX_SBCAL_NTARG_HI 31
+#define RG_TURISMO_TRX_SX_SBCAL_NTARG_SZ 16
+#define RG_TURISMO_TRX_VO_AAC_TAR_BT_MSK 0x0000000f
+#define RG_TURISMO_TRX_VO_AAC_TAR_BT_I_MSK 0xfffffff0
+#define RG_TURISMO_TRX_VO_AAC_TAR_BT_SFT 0
+#define RG_TURISMO_TRX_VO_AAC_TAR_BT_HI 3
+#define RG_TURISMO_TRX_VO_AAC_TAR_BT_SZ 4
+#define RG_TURISMO_TRX_VO_AAC_IOST_BT_MSK 0x00000030
+#define RG_TURISMO_TRX_VO_AAC_IOST_BT_I_MSK 0xffffffcf
+#define RG_TURISMO_TRX_VO_AAC_IOST_BT_SFT 4
+#define RG_TURISMO_TRX_VO_AAC_IOST_BT_HI 5
+#define RG_TURISMO_TRX_VO_AAC_IOST_BT_SZ 2
+#define RG_TURISMO_TRX_VO_AAC_TAR_WF_MSK 0x00000780
+#define RG_TURISMO_TRX_VO_AAC_TAR_WF_I_MSK 0xfffff87f
+#define RG_TURISMO_TRX_VO_AAC_TAR_WF_SFT 7
+#define RG_TURISMO_TRX_VO_AAC_TAR_WF_HI 10
+#define RG_TURISMO_TRX_VO_AAC_TAR_WF_SZ 4
+#define RG_TURISMO_TRX_VO_AAC_IOST_WF_MSK 0x00001800
+#define RG_TURISMO_TRX_VO_AAC_IOST_WF_I_MSK 0xffffe7ff
+#define RG_TURISMO_TRX_VO_AAC_IOST_WF_SFT 11
+#define RG_TURISMO_TRX_VO_AAC_IOST_WF_HI 12
+#define RG_TURISMO_TRX_VO_AAC_IOST_WF_SZ 2
+#define RG_TURISMO_TRX_VO_AAC_IMAX_MSK 0x0003c000
+#define RG_TURISMO_TRX_VO_AAC_IMAX_I_MSK 0xfffc3fff
+#define RG_TURISMO_TRX_VO_AAC_IMAX_SFT 14
+#define RG_TURISMO_TRX_VO_AAC_IMAX_HI 17
+#define RG_TURISMO_TRX_VO_AAC_IMAX_SZ 4
+#define RG_TURISMO_TRX_VO_AAC_INIT_MSK 0x000c0000
+#define RG_TURISMO_TRX_VO_AAC_INIT_I_MSK 0xfff3ffff
+#define RG_TURISMO_TRX_VO_AAC_INIT_SFT 18
+#define RG_TURISMO_TRX_VO_AAC_INIT_HI 19
+#define RG_TURISMO_TRX_VO_AAC_INIT_SZ 2
+#define RG_TURISMO_TRX_VO_AAC_EVA_TS_MSK 0x00300000
+#define RG_TURISMO_TRX_VO_AAC_EVA_TS_I_MSK 0xffcfffff
+#define RG_TURISMO_TRX_VO_AAC_EVA_TS_SFT 20
+#define RG_TURISMO_TRX_VO_AAC_EVA_TS_HI 21
+#define RG_TURISMO_TRX_VO_AAC_EVA_TS_SZ 2
+#define RG_TURISMO_TRX_VO_AAC_EN_MAN_MSK 0x00800000
+#define RG_TURISMO_TRX_VO_AAC_EN_MAN_I_MSK 0xff7fffff
+#define RG_TURISMO_TRX_VO_AAC_EN_MAN_SFT 23
+#define RG_TURISMO_TRX_VO_AAC_EN_MAN_HI 23
+#define RG_TURISMO_TRX_VO_AAC_EN_MAN_SZ 1
+#define RG_TURISMO_TRX_VO_AAC_EN_MSK 0x01000000
+#define RG_TURISMO_TRX_VO_AAC_EN_I_MSK 0xfeffffff
+#define RG_TURISMO_TRX_VO_AAC_EN_SFT 24
+#define RG_TURISMO_TRX_VO_AAC_EN_HI 24
+#define RG_TURISMO_TRX_VO_AAC_EN_SZ 1
+#define RG_TURISMO_TRX_VO_AAC_EVA_MAN_MSK 0x02000000
+#define RG_TURISMO_TRX_VO_AAC_EVA_MAN_I_MSK 0xfdffffff
+#define RG_TURISMO_TRX_VO_AAC_EVA_MAN_SFT 25
+#define RG_TURISMO_TRX_VO_AAC_EVA_MAN_HI 25
+#define RG_TURISMO_TRX_VO_AAC_EVA_MAN_SZ 1
+#define RG_TURISMO_TRX_VO_AAC_EVA_MSK 0x04000000
+#define RG_TURISMO_TRX_VO_AAC_EVA_I_MSK 0xfbffffff
+#define RG_TURISMO_TRX_VO_AAC_EVA_SFT 26
+#define RG_TURISMO_TRX_VO_AAC_EVA_HI 26
+#define RG_TURISMO_TRX_VO_AAC_EVA_SZ 1
+#define RG_TURISMO_TRX_VO_AAC_TEST_EN_MSK 0x10000000
+#define RG_TURISMO_TRX_VO_AAC_TEST_EN_I_MSK 0xefffffff
+#define RG_TURISMO_TRX_VO_AAC_TEST_EN_SFT 28
+#define RG_TURISMO_TRX_VO_AAC_TEST_EN_HI 28
+#define RG_TURISMO_TRX_VO_AAC_TEST_EN_SZ 1
+#define RG_TURISMO_TRX_VO_AAC_TEST_SEL_MSK 0x20000000
+#define RG_TURISMO_TRX_VO_AAC_TEST_SEL_I_MSK 0xdfffffff
+#define RG_TURISMO_TRX_VO_AAC_TEST_SEL_SFT 29
+#define RG_TURISMO_TRX_VO_AAC_TEST_SEL_HI 29
+#define RG_TURISMO_TRX_VO_AAC_TEST_SEL_SZ 1
+#define RG_TURISMO_TRX_SX_TTL_INIT_MSK 0x00000003
+#define RG_TURISMO_TRX_SX_TTL_INIT_I_MSK 0xfffffffc
+#define RG_TURISMO_TRX_SX_TTL_INIT_SFT 0
+#define RG_TURISMO_TRX_SX_TTL_INIT_HI 1
+#define RG_TURISMO_TRX_SX_TTL_INIT_SZ 2
+#define RG_TURISMO_TRX_SX_TTL_FPT_MSK 0x0000000c
+#define RG_TURISMO_TRX_SX_TTL_FPT_I_MSK 0xfffffff3
+#define RG_TURISMO_TRX_SX_TTL_FPT_SFT 2
+#define RG_TURISMO_TRX_SX_TTL_FPT_HI 3
+#define RG_TURISMO_TRX_SX_TTL_FPT_SZ 2
+#define RG_TURISMO_TRX_SX_TTL_CPT_MSK 0x00000030
+#define RG_TURISMO_TRX_SX_TTL_CPT_I_MSK 0xffffffcf
+#define RG_TURISMO_TRX_SX_TTL_CPT_SFT 4
+#define RG_TURISMO_TRX_SX_TTL_CPT_HI 5
+#define RG_TURISMO_TRX_SX_TTL_CPT_SZ 2
+#define RG_TURISMO_TRX_SX_TTL_ACCUM_MSK 0x00000180
+#define RG_TURISMO_TRX_SX_TTL_ACCUM_I_MSK 0xfffffe7f
+#define RG_TURISMO_TRX_SX_TTL_ACCUM_SFT 7
+#define RG_TURISMO_TRX_SX_TTL_ACCUM_HI 8
+#define RG_TURISMO_TRX_SX_TTL_ACCUM_SZ 2
+#define RG_TURISMO_TRX_SX_TTL_SUB_MSK 0x00000c00
+#define RG_TURISMO_TRX_SX_TTL_SUB_I_MSK 0xfffff3ff
+#define RG_TURISMO_TRX_SX_TTL_SUB_SFT 10
+#define RG_TURISMO_TRX_SX_TTL_SUB_HI 11
+#define RG_TURISMO_TRX_SX_TTL_SUB_SZ 2
+#define RG_TURISMO_TRX_SX_TTL_SUB_INV_MSK 0x00001000
+#define RG_TURISMO_TRX_SX_TTL_SUB_INV_I_MSK 0xffffefff
+#define RG_TURISMO_TRX_SX_TTL_SUB_INV_SFT 12
+#define RG_TURISMO_TRX_SX_TTL_SUB_INV_HI 12
+#define RG_TURISMO_TRX_SX_TTL_SUB_INV_SZ 1
+#define RG_TURISMO_TRX_SX_TTL_VH_MSK 0x0000c000
+#define RG_TURISMO_TRX_SX_TTL_VH_I_MSK 0xffff3fff
+#define RG_TURISMO_TRX_SX_TTL_VH_SFT 14
+#define RG_TURISMO_TRX_SX_TTL_VH_HI 15
+#define RG_TURISMO_TRX_SX_TTL_VH_SZ 2
+#define RG_TURISMO_TRX_SX_TTL_VL_MSK 0x00030000
+#define RG_TURISMO_TRX_SX_TTL_VL_I_MSK 0xfffcffff
+#define RG_TURISMO_TRX_SX_TTL_VL_SFT 16
+#define RG_TURISMO_TRX_SX_TTL_VL_HI 17
+#define RG_TURISMO_TRX_SX_TTL_VL_SZ 2
+#define RG_TURISMO_TRX_SX_LPF_VTUNE_TEST_MSK 0x00080000
+#define RG_TURISMO_TRX_SX_LPF_VTUNE_TEST_I_MSK 0xfff7ffff
+#define RG_TURISMO_TRX_SX_LPF_VTUNE_TEST_SFT 19
+#define RG_TURISMO_TRX_SX_LPF_VTUNE_TEST_HI 19
+#define RG_TURISMO_TRX_SX_LPF_VTUNE_TEST_SZ 1
+#define RG_TURISMO_TRX_DP_BBPLL_PD_MSK 0x00000001
+#define RG_TURISMO_TRX_DP_BBPLL_PD_I_MSK 0xfffffffe
+#define RG_TURISMO_TRX_DP_BBPLL_PD_SFT 0
+#define RG_TURISMO_TRX_DP_BBPLL_PD_HI 0
+#define RG_TURISMO_TRX_DP_BBPLL_PD_SZ 1
+#define RG_TURISMO_TRX_DP_BBPLL_BP_MSK 0x00000002
+#define RG_TURISMO_TRX_DP_BBPLL_BP_I_MSK 0xfffffffd
+#define RG_TURISMO_TRX_DP_BBPLL_BP_SFT 1
+#define RG_TURISMO_TRX_DP_BBPLL_BP_HI 1
+#define RG_TURISMO_TRX_DP_BBPLL_BP_SZ 1
+#define RG_TURISMO_TRX_EN_DP_MANUAL_MSK 0x00000004
+#define RG_TURISMO_TRX_EN_DP_MANUAL_I_MSK 0xfffffffb
+#define RG_TURISMO_TRX_EN_DP_MANUAL_SFT 2
+#define RG_TURISMO_TRX_EN_DP_MANUAL_HI 2
+#define RG_TURISMO_TRX_EN_DP_MANUAL_SZ 1
+#define RG_TURISMO_TRX_DP_FREF_DOUB_MSK 0x00000008
+#define RG_TURISMO_TRX_DP_FREF_DOUB_I_MSK 0xfffffff7
+#define RG_TURISMO_TRX_DP_FREF_DOUB_SFT 3
+#define RG_TURISMO_TRX_DP_FREF_DOUB_HI 3
+#define RG_TURISMO_TRX_DP_FREF_DOUB_SZ 1
+#define RG_TURISMO_TRX_DP_DAC320_DIVBY2_MSK 0x00000010
+#define RG_TURISMO_TRX_DP_DAC320_DIVBY2_I_MSK 0xffffffef
+#define RG_TURISMO_TRX_DP_DAC320_DIVBY2_SFT 4
+#define RG_TURISMO_TRX_DP_DAC320_DIVBY2_HI 4
+#define RG_TURISMO_TRX_DP_DAC320_DIVBY2_SZ 1
+#define RG_TURISMO_TRX_DP_ADC320_DIVBY2_BT_MSK 0x00000020
+#define RG_TURISMO_TRX_DP_ADC320_DIVBY2_BT_I_MSK 0xffffffdf
+#define RG_TURISMO_TRX_DP_ADC320_DIVBY2_BT_SFT 5
+#define RG_TURISMO_TRX_DP_ADC320_DIVBY2_BT_HI 5
+#define RG_TURISMO_TRX_DP_ADC320_DIVBY2_BT_SZ 1
+#define RG_TURISMO_TRX_DP_ADC320_DIVBY2_WF_MSK 0x00000040
+#define RG_TURISMO_TRX_DP_ADC320_DIVBY2_WF_I_MSK 0xffffffbf
+#define RG_TURISMO_TRX_DP_ADC320_DIVBY2_WF_SFT 6
+#define RG_TURISMO_TRX_DP_ADC320_DIVBY2_WF_HI 6
+#define RG_TURISMO_TRX_DP_ADC320_DIVBY2_WF_SZ 1
+#define RG_TURISMO_TRX_EN_DPL_MOD_MSK 0x00000100
+#define RG_TURISMO_TRX_EN_DPL_MOD_I_MSK 0xfffffeff
+#define RG_TURISMO_TRX_EN_DPL_MOD_SFT 8
+#define RG_TURISMO_TRX_EN_DPL_MOD_HI 8
+#define RG_TURISMO_TRX_EN_DPL_MOD_SZ 1
+#define RG_TURISMO_TRX_DPL_MOD_ORDER_MSK 0x00000600
+#define RG_TURISMO_TRX_DPL_MOD_ORDER_I_MSK 0xfffff9ff
+#define RG_TURISMO_TRX_DPL_MOD_ORDER_SFT 9
+#define RG_TURISMO_TRX_DPL_MOD_ORDER_HI 10
+#define RG_TURISMO_TRX_DPL_MOD_ORDER_SZ 2
+#define RG_TURISMO_TRX_DP_REFDIV_MSK 0x0003f800
+#define RG_TURISMO_TRX_DP_REFDIV_I_MSK 0xfffc07ff
+#define RG_TURISMO_TRX_DP_REFDIV_SFT 11
+#define RG_TURISMO_TRX_DP_REFDIV_HI 17
+#define RG_TURISMO_TRX_DP_REFDIV_SZ 7
+#define RG_TURISMO_TRX_DP_FODIV_MSK 0x01fc0000
+#define RG_TURISMO_TRX_DP_FODIV_I_MSK 0xfe03ffff
+#define RG_TURISMO_TRX_DP_FODIV_SFT 18
+#define RG_TURISMO_TRX_DP_FODIV_HI 24
+#define RG_TURISMO_TRX_DP_FODIV_SZ 7
+#define RG_TURISMO_TRX_EN_LDO_DP_IQUP_MSK 0x04000000
+#define RG_TURISMO_TRX_EN_LDO_DP_IQUP_I_MSK 0xfbffffff
+#define RG_TURISMO_TRX_EN_LDO_DP_IQUP_SFT 26
+#define RG_TURISMO_TRX_EN_LDO_DP_IQUP_HI 26
+#define RG_TURISMO_TRX_EN_LDO_DP_IQUP_SZ 1
+#define RG_TURISMO_TRX_DP_OD_TEST_MSK 0x08000000
+#define RG_TURISMO_TRX_DP_OD_TEST_I_MSK 0xf7ffffff
+#define RG_TURISMO_TRX_DP_OD_TEST_SFT 27
+#define RG_TURISMO_TRX_DP_OD_TEST_HI 27
+#define RG_TURISMO_TRX_DP_OD_TEST_SZ 1
+#define RG_TURISMO_TRX_DP_BBPLL_TESTSEL_MSK 0x70000000
+#define RG_TURISMO_TRX_DP_BBPLL_TESTSEL_I_MSK 0x8fffffff
+#define RG_TURISMO_TRX_DP_BBPLL_TESTSEL_SFT 28
+#define RG_TURISMO_TRX_DP_BBPLL_TESTSEL_HI 30
+#define RG_TURISMO_TRX_DP_BBPLL_TESTSEL_SZ 3
+#define RG_TURISMO_TRX_DP_BBPLL_ICP_MSK 0x00000003
+#define RG_TURISMO_TRX_DP_BBPLL_ICP_I_MSK 0xfffffffc
+#define RG_TURISMO_TRX_DP_BBPLL_ICP_SFT 0
+#define RG_TURISMO_TRX_DP_BBPLL_ICP_HI 1
+#define RG_TURISMO_TRX_DP_BBPLL_ICP_SZ 2
+#define RG_TURISMO_TRX_DP_BBPLL_IDUAL_MSK 0x0000000c
+#define RG_TURISMO_TRX_DP_BBPLL_IDUAL_I_MSK 0xfffffff3
+#define RG_TURISMO_TRX_DP_BBPLL_IDUAL_SFT 2
+#define RG_TURISMO_TRX_DP_BBPLL_IDUAL_HI 3
+#define RG_TURISMO_TRX_DP_BBPLL_IDUAL_SZ 2
+#define RG_TURISMO_TRX_DP_CP_IOSTPOL_MSK 0x00000010
+#define RG_TURISMO_TRX_DP_CP_IOSTPOL_I_MSK 0xffffffef
+#define RG_TURISMO_TRX_DP_CP_IOSTPOL_SFT 4
+#define RG_TURISMO_TRX_DP_CP_IOSTPOL_HI 4
+#define RG_TURISMO_TRX_DP_CP_IOSTPOL_SZ 1
+#define RG_TURISMO_TRX_DP_CP_IOST_MSK 0x00000060
+#define RG_TURISMO_TRX_DP_CP_IOST_I_MSK 0xffffff9f
+#define RG_TURISMO_TRX_DP_CP_IOST_SFT 5
+#define RG_TURISMO_TRX_DP_CP_IOST_HI 6
+#define RG_TURISMO_TRX_DP_CP_IOST_SZ 2
+#define RG_TURISMO_TRX_DP_PFD_PFDSEL_MSK 0x00000080
+#define RG_TURISMO_TRX_DP_PFD_PFDSEL_I_MSK 0xffffff7f
+#define RG_TURISMO_TRX_DP_PFD_PFDSEL_SFT 7
+#define RG_TURISMO_TRX_DP_PFD_PFDSEL_HI 7
+#define RG_TURISMO_TRX_DP_PFD_PFDSEL_SZ 1
+#define RG_TURISMO_TRX_DP_BBPLL_PFD_DLY_MSK 0x00000300
+#define RG_TURISMO_TRX_DP_BBPLL_PFD_DLY_I_MSK 0xfffffcff
+#define RG_TURISMO_TRX_DP_BBPLL_PFD_DLY_SFT 8
+#define RG_TURISMO_TRX_DP_BBPLL_PFD_DLY_HI 9
+#define RG_TURISMO_TRX_DP_BBPLL_PFD_DLY_SZ 2
+#define RG_TURISMO_TRX_DP_RP_MSK 0x00003800
+#define RG_TURISMO_TRX_DP_RP_I_MSK 0xffffc7ff
+#define RG_TURISMO_TRX_DP_RP_SFT 11
+#define RG_TURISMO_TRX_DP_RP_HI 13
+#define RG_TURISMO_TRX_DP_RP_SZ 3
+#define RG_TURISMO_TRX_DP_RHP_MSK 0x0000c000
+#define RG_TURISMO_TRX_DP_RHP_I_MSK 0xffff3fff
+#define RG_TURISMO_TRX_DP_RHP_SFT 14
+#define RG_TURISMO_TRX_DP_RHP_HI 15
+#define RG_TURISMO_TRX_DP_RHP_SZ 2
+#define RG_TURISMO_TRX_EN_DP_VT_MON_MSK 0x00020000
+#define RG_TURISMO_TRX_EN_DP_VT_MON_I_MSK 0xfffdffff
+#define RG_TURISMO_TRX_EN_DP_VT_MON_SFT 17
+#define RG_TURISMO_TRX_EN_DP_VT_MON_HI 17
+#define RG_TURISMO_TRX_EN_DP_VT_MON_SZ 1
+#define RG_TURISMO_TRX_DP_VT_TH_HI_MSK 0x000c0000
+#define RG_TURISMO_TRX_DP_VT_TH_HI_I_MSK 0xfff3ffff
+#define RG_TURISMO_TRX_DP_VT_TH_HI_SFT 18
+#define RG_TURISMO_TRX_DP_VT_TH_HI_HI 19
+#define RG_TURISMO_TRX_DP_VT_TH_HI_SZ 2
+#define RG_TURISMO_TRX_DP_VT_TH_LO_MSK 0x00300000
+#define RG_TURISMO_TRX_DP_VT_TH_LO_I_MSK 0xffcfffff
+#define RG_TURISMO_TRX_DP_VT_TH_LO_SFT 20
+#define RG_TURISMO_TRX_DP_VT_TH_LO_HI 21
+#define RG_TURISMO_TRX_DP_VT_TH_LO_SZ 2
+#define RG_TURISMO_TRX_DP_BBPLL_BS_MSK 0x1f800000
+#define RG_TURISMO_TRX_DP_BBPLL_BS_I_MSK 0xe07fffff
+#define RG_TURISMO_TRX_DP_BBPLL_BS_SFT 23
+#define RG_TURISMO_TRX_DP_BBPLL_BS_HI 28
+#define RG_TURISMO_TRX_DP_BBPLL_BS_SZ 6
+#define RG_TURISMO_TRX_DP_BBPLL_SDM_EDGE_MSK 0x80000000
+#define RG_TURISMO_TRX_DP_BBPLL_SDM_EDGE_I_MSK 0x7fffffff
+#define RG_TURISMO_TRX_DP_BBPLL_SDM_EDGE_SFT 31
+#define RG_TURISMO_TRX_DP_BBPLL_SDM_EDGE_HI 31
+#define RG_TURISMO_TRX_DP_BBPLL_SDM_EDGE_SZ 1
+#define RG_TURISMO_TRX_DPL_RFCTRL_F_MSK 0x00ffffff
+#define RG_TURISMO_TRX_DPL_RFCTRL_F_I_MSK 0xff000000
+#define RG_TURISMO_TRX_DPL_RFCTRL_F_SFT 0
+#define RG_TURISMO_TRX_DPL_RFCTRL_F_HI 23
+#define RG_TURISMO_TRX_DPL_RFCTRL_F_SZ 24
+#define RG_TURISMO_TRX_DPL_RFCTRL_CH_MSK 0xff000000
+#define RG_TURISMO_TRX_DPL_RFCTRL_CH_I_MSK 0x00ffffff
+#define RG_TURISMO_TRX_DPL_RFCTRL_CH_SFT 24
+#define RG_TURISMO_TRX_DPL_RFCTRL_CH_HI 31
+#define RG_TURISMO_TRX_DPL_RFCTRL_CH_SZ 8
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG15_MSK 0x0000003f
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG15_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG15_SFT 0
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG15_HI 5
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG15_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG15_MSK 0x00003f00
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG15_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG15_SFT 8
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG15_HI 13
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG15_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG14_MSK 0x003f0000
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG14_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG14_SFT 16
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG14_HI 21
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG14_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG14_MSK 0x3f000000
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG14_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG14_SFT 24
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG14_HI 29
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG14_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG13_MSK 0x0000003f
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG13_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG13_SFT 0
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG13_HI 5
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG13_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG13_MSK 0x00003f00
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG13_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG13_SFT 8
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG13_HI 13
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG13_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG12_MSK 0x003f0000
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG12_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG12_SFT 16
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG12_HI 21
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG12_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG12_MSK 0x3f000000
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG12_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG12_SFT 24
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG12_HI 29
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG12_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG11_MSK 0x0000003f
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG11_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG11_SFT 0
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG11_HI 5
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG11_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG11_MSK 0x00003f00
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG11_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG11_SFT 8
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG11_HI 13
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG11_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG10_MSK 0x003f0000
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG10_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG10_SFT 16
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG10_HI 21
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG10_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG10_MSK 0x3f000000
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG10_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG10_SFT 24
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG10_HI 29
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG10_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG9_MSK 0x0000003f
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG9_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG9_SFT 0
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG9_HI 5
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG9_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG9_MSK 0x00003f00
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG9_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG9_SFT 8
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG9_HI 13
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG9_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG8_MSK 0x003f0000
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG8_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG8_SFT 16
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG8_HI 21
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG8_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG8_MSK 0x3f000000
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG8_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG8_SFT 24
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG8_HI 29
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG8_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG7_MSK 0x0000003f
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG7_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG7_SFT 0
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG7_HI 5
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG7_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG7_MSK 0x00003f00
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG7_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG7_SFT 8
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG7_HI 13
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG7_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG6_MSK 0x003f0000
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG6_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG6_SFT 16
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG6_HI 21
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG6_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG6_MSK 0x3f000000
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG6_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG6_SFT 24
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG6_HI 29
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG6_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG5_MSK 0x0000003f
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG5_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG5_SFT 0
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG5_HI 5
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG5_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG5_MSK 0x00003f00
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG5_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG5_SFT 8
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG5_HI 13
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG5_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG4_MSK 0x003f0000
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG4_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG4_SFT 16
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG4_HI 21
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG4_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG4_MSK 0x3f000000
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG4_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG4_SFT 24
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG4_HI 29
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG4_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG3_MSK 0x0000003f
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG3_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG3_SFT 0
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG3_HI 5
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG3_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG3_MSK 0x00003f00
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG3_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG3_SFT 8
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG3_HI 13
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG3_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG2_MSK 0x003f0000
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG2_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG2_SFT 16
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG2_HI 21
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG2_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG2_MSK 0x3f000000
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG2_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG2_SFT 24
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG2_HI 29
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG2_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG1_MSK 0x0000003f
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG1_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG1_SFT 0
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG1_HI 5
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG1_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG1_MSK 0x00003f00
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG1_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG1_SFT 8
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG1_HI 13
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG1_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG0_MSK 0x003f0000
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG0_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG0_SFT 16
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG0_HI 21
+#define RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG0_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG0_MSK 0x3f000000
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG0_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG0_SFT 24
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG0_HI 29
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG0_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG15_MSK 0x0000003f
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG15_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG15_SFT 0
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG15_HI 5
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG15_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG15_MSK 0x00003f00
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG15_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG15_SFT 8
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG15_HI 13
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG15_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG14_MSK 0x003f0000
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG14_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG14_SFT 16
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG14_HI 21
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG14_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG14_MSK 0x3f000000
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG14_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG14_SFT 24
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG14_HI 29
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG14_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG13_MSK 0x0000003f
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG13_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG13_SFT 0
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG13_HI 5
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG13_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG13_MSK 0x00003f00
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG13_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG13_SFT 8
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG13_HI 13
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG13_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG12_MSK 0x003f0000
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG12_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG12_SFT 16
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG12_HI 21
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG12_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG12_MSK 0x3f000000
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG12_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG12_SFT 24
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG12_HI 29
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG12_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG11_MSK 0x0000003f
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG11_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG11_SFT 0
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG11_HI 5
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG11_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG11_MSK 0x00003f00
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG11_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG11_SFT 8
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG11_HI 13
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG11_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG10_MSK 0x003f0000
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG10_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG10_SFT 16
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG10_HI 21
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG10_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG10_MSK 0x3f000000
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG10_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG10_SFT 24
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG10_HI 29
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG10_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG9_MSK 0x0000003f
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG9_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG9_SFT 0
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG9_HI 5
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG9_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG9_MSK 0x00003f00
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG9_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG9_SFT 8
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG9_HI 13
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG9_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG8_MSK 0x003f0000
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG8_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG8_SFT 16
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG8_HI 21
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG8_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG8_MSK 0x3f000000
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG8_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG8_SFT 24
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG8_HI 29
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG8_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG7_MSK 0x0000003f
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG7_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG7_SFT 0
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG7_HI 5
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG7_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG7_MSK 0x00003f00
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG7_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG7_SFT 8
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG7_HI 13
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG7_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG6_MSK 0x003f0000
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG6_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG6_SFT 16
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG6_HI 21
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG6_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG6_MSK 0x3f000000
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG6_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG6_SFT 24
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG6_HI 29
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG6_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG5_MSK 0x0000003f
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG5_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG5_SFT 0
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG5_HI 5
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG5_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG5_MSK 0x00003f00
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG5_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG5_SFT 8
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG5_HI 13
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG5_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG4_MSK 0x003f0000
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG4_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG4_SFT 16
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG4_HI 21
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG4_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG4_MSK 0x3f000000
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG4_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG4_SFT 24
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG4_HI 29
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG4_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG3_MSK 0x0000003f
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG3_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG3_SFT 0
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG3_HI 5
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG3_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG3_MSK 0x00003f00
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG3_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG3_SFT 8
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG3_HI 13
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG3_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG2_MSK 0x003f0000
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG2_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG2_SFT 16
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG2_HI 21
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG2_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG2_MSK 0x3f000000
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG2_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG2_SFT 24
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG2_HI 29
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG2_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG1_MSK 0x0000003f
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG1_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG1_SFT 0
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG1_HI 5
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG1_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG1_MSK 0x00003f00
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG1_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG1_SFT 8
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG1_HI 13
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG1_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG0_MSK 0x003f0000
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG0_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG0_SFT 16
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG0_HI 21
+#define RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG0_SZ 6
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG0_MSK 0x3f000000
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG0_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG0_SFT 24
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG0_HI 29
+#define RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG0_SZ 6
+#define RG_TURISMO_TRX_IDACAI_TZ0_COARSE4_MSK 0x0000003f
+#define RG_TURISMO_TRX_IDACAI_TZ0_COARSE4_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_IDACAI_TZ0_COARSE4_SFT 0
+#define RG_TURISMO_TRX_IDACAI_TZ0_COARSE4_HI 5
+#define RG_TURISMO_TRX_IDACAI_TZ0_COARSE4_SZ 6
+#define RG_TURISMO_TRX_IDACAQ_TZ0_COARSE4_MSK 0x00003f00
+#define RG_TURISMO_TRX_IDACAQ_TZ0_COARSE4_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_IDACAQ_TZ0_COARSE4_SFT 8
+#define RG_TURISMO_TRX_IDACAQ_TZ0_COARSE4_HI 13
+#define RG_TURISMO_TRX_IDACAQ_TZ0_COARSE4_SZ 6
+#define RG_TURISMO_TRX_IDACAI_TZ0_COARSE3_MSK 0x003f0000
+#define RG_TURISMO_TRX_IDACAI_TZ0_COARSE3_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_IDACAI_TZ0_COARSE3_SFT 16
+#define RG_TURISMO_TRX_IDACAI_TZ0_COARSE3_HI 21
+#define RG_TURISMO_TRX_IDACAI_TZ0_COARSE3_SZ 6
+#define RG_TURISMO_TRX_IDACAQ_TZ0_COARSE3_MSK 0x3f000000
+#define RG_TURISMO_TRX_IDACAQ_TZ0_COARSE3_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_IDACAQ_TZ0_COARSE3_SFT 24
+#define RG_TURISMO_TRX_IDACAQ_TZ0_COARSE3_HI 29
+#define RG_TURISMO_TRX_IDACAQ_TZ0_COARSE3_SZ 6
+#define RG_TURISMO_TRX_IDACAI_TZ0_COARSE2_MSK 0x0000003f
+#define RG_TURISMO_TRX_IDACAI_TZ0_COARSE2_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_IDACAI_TZ0_COARSE2_SFT 0
+#define RG_TURISMO_TRX_IDACAI_TZ0_COARSE2_HI 5
+#define RG_TURISMO_TRX_IDACAI_TZ0_COARSE2_SZ 6
+#define RG_TURISMO_TRX_IDACAQ_TZ0_COARSE2_MSK 0x00003f00
+#define RG_TURISMO_TRX_IDACAQ_TZ0_COARSE2_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_IDACAQ_TZ0_COARSE2_SFT 8
+#define RG_TURISMO_TRX_IDACAQ_TZ0_COARSE2_HI 13
+#define RG_TURISMO_TRX_IDACAQ_TZ0_COARSE2_SZ 6
+#define RG_TURISMO_TRX_IDACAI_TZ0_COARSE1_MSK 0x003f0000
+#define RG_TURISMO_TRX_IDACAI_TZ0_COARSE1_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_IDACAI_TZ0_COARSE1_SFT 16
+#define RG_TURISMO_TRX_IDACAI_TZ0_COARSE1_HI 21
+#define RG_TURISMO_TRX_IDACAI_TZ0_COARSE1_SZ 6
+#define RG_TURISMO_TRX_IDACAQ_TZ0_COARSE1_MSK 0x3f000000
+#define RG_TURISMO_TRX_IDACAQ_TZ0_COARSE1_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_IDACAQ_TZ0_COARSE1_SFT 24
+#define RG_TURISMO_TRX_IDACAQ_TZ0_COARSE1_HI 29
+#define RG_TURISMO_TRX_IDACAQ_TZ0_COARSE1_SZ 6
+#define RG_TURISMO_TRX_IDACAI_TZ0_COARSE0_MSK 0x0000003f
+#define RG_TURISMO_TRX_IDACAI_TZ0_COARSE0_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_IDACAI_TZ0_COARSE0_SFT 0
+#define RG_TURISMO_TRX_IDACAI_TZ0_COARSE0_HI 5
+#define RG_TURISMO_TRX_IDACAI_TZ0_COARSE0_SZ 6
+#define RG_TURISMO_TRX_IDACAQ_TZ0_COARSE0_MSK 0x00003f00
+#define RG_TURISMO_TRX_IDACAQ_TZ0_COARSE0_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_IDACAQ_TZ0_COARSE0_SFT 8
+#define RG_TURISMO_TRX_IDACAQ_TZ0_COARSE0_HI 13
+#define RG_TURISMO_TRX_IDACAQ_TZ0_COARSE0_SZ 6
+#define RG_TURISMO_TRX_IDACAI_TZ1_COARSE4_MSK 0x003f0000
+#define RG_TURISMO_TRX_IDACAI_TZ1_COARSE4_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_IDACAI_TZ1_COARSE4_SFT 16
+#define RG_TURISMO_TRX_IDACAI_TZ1_COARSE4_HI 21
+#define RG_TURISMO_TRX_IDACAI_TZ1_COARSE4_SZ 6
+#define RG_TURISMO_TRX_IDACAQ_TZ1_COARSE4_MSK 0x3f000000
+#define RG_TURISMO_TRX_IDACAQ_TZ1_COARSE4_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_IDACAQ_TZ1_COARSE4_SFT 24
+#define RG_TURISMO_TRX_IDACAQ_TZ1_COARSE4_HI 29
+#define RG_TURISMO_TRX_IDACAQ_TZ1_COARSE4_SZ 6
+#define RG_TURISMO_TRX_IDACAI_TZ1_COARSE3_MSK 0x0000003f
+#define RG_TURISMO_TRX_IDACAI_TZ1_COARSE3_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_IDACAI_TZ1_COARSE3_SFT 0
+#define RG_TURISMO_TRX_IDACAI_TZ1_COARSE3_HI 5
+#define RG_TURISMO_TRX_IDACAI_TZ1_COARSE3_SZ 6
+#define RG_TURISMO_TRX_IDACAQ_TZ1_COARSE3_MSK 0x00003f00
+#define RG_TURISMO_TRX_IDACAQ_TZ1_COARSE3_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_IDACAQ_TZ1_COARSE3_SFT 8
+#define RG_TURISMO_TRX_IDACAQ_TZ1_COARSE3_HI 13
+#define RG_TURISMO_TRX_IDACAQ_TZ1_COARSE3_SZ 6
+#define RG_TURISMO_TRX_IDACAI_TZ1_COARSE2_MSK 0x003f0000
+#define RG_TURISMO_TRX_IDACAI_TZ1_COARSE2_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_IDACAI_TZ1_COARSE2_SFT 16
+#define RG_TURISMO_TRX_IDACAI_TZ1_COARSE2_HI 21
+#define RG_TURISMO_TRX_IDACAI_TZ1_COARSE2_SZ 6
+#define RG_TURISMO_TRX_IDACAQ_TZ1_COARSE2_MSK 0x3f000000
+#define RG_TURISMO_TRX_IDACAQ_TZ1_COARSE2_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_IDACAQ_TZ1_COARSE2_SFT 24
+#define RG_TURISMO_TRX_IDACAQ_TZ1_COARSE2_HI 29
+#define RG_TURISMO_TRX_IDACAQ_TZ1_COARSE2_SZ 6
+#define RG_TURISMO_TRX_IDACAI_TZ1_COARSE1_MSK 0x0000003f
+#define RG_TURISMO_TRX_IDACAI_TZ1_COARSE1_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_IDACAI_TZ1_COARSE1_SFT 0
+#define RG_TURISMO_TRX_IDACAI_TZ1_COARSE1_HI 5
+#define RG_TURISMO_TRX_IDACAI_TZ1_COARSE1_SZ 6
+#define RG_TURISMO_TRX_IDACAQ_TZ1_COARSE1_MSK 0x00003f00
+#define RG_TURISMO_TRX_IDACAQ_TZ1_COARSE1_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_IDACAQ_TZ1_COARSE1_SFT 8
+#define RG_TURISMO_TRX_IDACAQ_TZ1_COARSE1_HI 13
+#define RG_TURISMO_TRX_IDACAQ_TZ1_COARSE1_SZ 6
+#define RG_TURISMO_TRX_IDACAI_TZ1_COARSE0_MSK 0x003f0000
+#define RG_TURISMO_TRX_IDACAI_TZ1_COARSE0_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_IDACAI_TZ1_COARSE0_SFT 16
+#define RG_TURISMO_TRX_IDACAI_TZ1_COARSE0_HI 21
+#define RG_TURISMO_TRX_IDACAI_TZ1_COARSE0_SZ 6
+#define RG_TURISMO_TRX_IDACAQ_TZ1_COARSE0_MSK 0x3f000000
+#define RG_TURISMO_TRX_IDACAQ_TZ1_COARSE0_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_IDACAQ_TZ1_COARSE0_SFT 24
+#define RG_TURISMO_TRX_IDACAQ_TZ1_COARSE0_HI 29
+#define RG_TURISMO_TRX_IDACAQ_TZ1_COARSE0_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG15_MSK 0x0000003f
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG15_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG15_SFT 0
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG15_HI 5
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG15_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG15_MSK 0x00003f00
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG15_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG15_SFT 8
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG15_HI 13
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG15_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG14_MSK 0x003f0000
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG14_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG14_SFT 16
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG14_HI 21
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG14_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG14_MSK 0x3f000000
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG14_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG14_SFT 24
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG14_HI 29
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG14_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG13_MSK 0x0000003f
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG13_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG13_SFT 0
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG13_HI 5
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG13_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG13_MSK 0x00003f00
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG13_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG13_SFT 8
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG13_HI 13
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG13_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG12_MSK 0x003f0000
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG12_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG12_SFT 16
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG12_HI 21
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG12_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG12_MSK 0x3f000000
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG12_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG12_SFT 24
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG12_HI 29
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG12_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG11_MSK 0x0000003f
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG11_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG11_SFT 0
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG11_HI 5
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG11_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG11_MSK 0x00003f00
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG11_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG11_SFT 8
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG11_HI 13
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG11_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG10_MSK 0x003f0000
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG10_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG10_SFT 16
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG10_HI 21
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG10_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG10_MSK 0x3f000000
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG10_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG10_SFT 24
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG10_HI 29
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG10_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG9_MSK 0x0000003f
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG9_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG9_SFT 0
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG9_HI 5
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG9_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG9_MSK 0x00003f00
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG9_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG9_SFT 8
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG9_HI 13
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG9_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG8_MSK 0x003f0000
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG8_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG8_SFT 16
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG8_HI 21
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG8_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG8_MSK 0x3f000000
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG8_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG8_SFT 24
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG8_HI 29
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG8_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG7_MSK 0x0000003f
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG7_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG7_SFT 0
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG7_HI 5
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG7_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG7_MSK 0x00003f00
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG7_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG7_SFT 8
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG7_HI 13
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG7_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG6_MSK 0x003f0000
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG6_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG6_SFT 16
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG6_HI 21
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG6_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG6_MSK 0x3f000000
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG6_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG6_SFT 24
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG6_HI 29
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG6_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG5_MSK 0x0000003f
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG5_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG5_SFT 0
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG5_HI 5
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG5_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG5_MSK 0x00003f00
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG5_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG5_SFT 8
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG5_HI 13
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG5_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG4_MSK 0x003f0000
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG4_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG4_SFT 16
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG4_HI 21
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG4_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG4_MSK 0x3f000000
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG4_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG4_SFT 24
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG4_HI 29
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG4_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG3_MSK 0x0000003f
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG3_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG3_SFT 0
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG3_HI 5
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG3_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG3_MSK 0x00003f00
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG3_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG3_SFT 8
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG3_HI 13
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG3_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG2_MSK 0x003f0000
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG2_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG2_SFT 16
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG2_HI 21
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG2_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG2_MSK 0x3f000000
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG2_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG2_SFT 24
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG2_HI 29
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG2_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG1_MSK 0x0000003f
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG1_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG1_SFT 0
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG1_HI 5
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG1_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG1_MSK 0x00003f00
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG1_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG1_SFT 8
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG1_HI 13
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG1_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG0_MSK 0x003f0000
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG0_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG0_SFT 16
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG0_HI 21
+#define RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG0_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG0_MSK 0x3f000000
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG0_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG0_SFT 24
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG0_HI 29
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG0_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG15_MSK 0x0000003f
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG15_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG15_SFT 0
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG15_HI 5
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG15_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG15_MSK 0x00003f00
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG15_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG15_SFT 8
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG15_HI 13
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG15_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG14_MSK 0x003f0000
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG14_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG14_SFT 16
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG14_HI 21
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG14_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG14_MSK 0x3f000000
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG14_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG14_SFT 24
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG14_HI 29
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG14_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG13_MSK 0x0000003f
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG13_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG13_SFT 0
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG13_HI 5
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG13_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG13_MSK 0x00003f00
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG13_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG13_SFT 8
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG13_HI 13
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG13_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG12_MSK 0x003f0000
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG12_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG12_SFT 16
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG12_HI 21
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG12_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG12_MSK 0x3f000000
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG12_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG12_SFT 24
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG12_HI 29
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG12_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG11_MSK 0x0000003f
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG11_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG11_SFT 0
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG11_HI 5
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG11_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG11_MSK 0x00003f00
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG11_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG11_SFT 8
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG11_HI 13
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG11_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG10_MSK 0x003f0000
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG10_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG10_SFT 16
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG10_HI 21
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG10_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG10_MSK 0x3f000000
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG10_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG10_SFT 24
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG10_HI 29
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG10_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG9_MSK 0x0000003f
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG9_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG9_SFT 0
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG9_HI 5
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG9_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG9_MSK 0x00003f00
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG9_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG9_SFT 8
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG9_HI 13
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG9_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG8_MSK 0x003f0000
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG8_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG8_SFT 16
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG8_HI 21
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG8_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG8_MSK 0x3f000000
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG8_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG8_SFT 24
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG8_HI 29
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG8_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG7_MSK 0x0000003f
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG7_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG7_SFT 0
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG7_HI 5
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG7_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG7_MSK 0x00003f00
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG7_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG7_SFT 8
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG7_HI 13
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG7_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG6_MSK 0x003f0000
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG6_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG6_SFT 16
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG6_HI 21
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG6_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG6_MSK 0x3f000000
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG6_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG6_SFT 24
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG6_HI 29
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG6_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG5_MSK 0x0000003f
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG5_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG5_SFT 0
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG5_HI 5
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG5_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG5_MSK 0x00003f00
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG5_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG5_SFT 8
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG5_HI 13
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG5_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG4_MSK 0x003f0000
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG4_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG4_SFT 16
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG4_HI 21
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG4_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG4_MSK 0x3f000000
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG4_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG4_SFT 24
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG4_HI 29
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG4_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG3_MSK 0x0000003f
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG3_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG3_SFT 0
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG3_HI 5
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG3_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG3_MSK 0x00003f00
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG3_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG3_SFT 8
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG3_HI 13
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG3_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG2_MSK 0x003f0000
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG2_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG2_SFT 16
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG2_HI 21
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG2_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG2_MSK 0x3f000000
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG2_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG2_SFT 24
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG2_HI 29
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG2_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG1_MSK 0x0000003f
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG1_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG1_SFT 0
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG1_HI 5
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG1_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG1_MSK 0x00003f00
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG1_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG1_SFT 8
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG1_HI 13
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG1_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG0_MSK 0x003f0000
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG0_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG0_SFT 16
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG0_HI 21
+#define RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG0_SZ 6
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG0_MSK 0x3f000000
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG0_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG0_SFT 24
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG0_HI 29
+#define RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG0_SZ 6
+#define RG_TURISMO_TRX_SX_DELAY_MSK 0x0000000f
+#define RG_TURISMO_TRX_SX_DELAY_I_MSK 0xfffffff0
+#define RG_TURISMO_TRX_SX_DELAY_SFT 0
+#define RG_TURISMO_TRX_SX_DELAY_HI 3
+#define RG_TURISMO_TRX_SX_DELAY_SZ 4
+#define RG_TURISMO_TRX_TXDAC_DELAY_MSK 0x000000f0
+#define RG_TURISMO_TRX_TXDAC_DELAY_I_MSK 0xffffff0f
+#define RG_TURISMO_TRX_TXDAC_DELAY_SFT 4
+#define RG_TURISMO_TRX_TXDAC_DELAY_HI 7
+#define RG_TURISMO_TRX_TXDAC_DELAY_SZ 4
+#define RG_TURISMO_TRX_TXRF_DELAY_MSK 0x00000f00
+#define RG_TURISMO_TRX_TXRF_DELAY_I_MSK 0xfffff0ff
+#define RG_TURISMO_TRX_TXRF_DELAY_SFT 8
+#define RG_TURISMO_TRX_TXRF_DELAY_HI 11
+#define RG_TURISMO_TRX_TXRF_DELAY_SZ 4
+#define RG_TURISMO_TRX_TXPA_DELAY_MSK 0x0000f000
+#define RG_TURISMO_TRX_TXPA_DELAY_I_MSK 0xffff0fff
+#define RG_TURISMO_TRX_TXPA_DELAY_SFT 12
+#define RG_TURISMO_TRX_TXPA_DELAY_HI 15
+#define RG_TURISMO_TRX_TXPA_DELAY_SZ 4
+#define RG_TURISMO_TRX_RXRF_DELAY_MSK 0x000f0000
+#define RG_TURISMO_TRX_RXRF_DELAY_I_MSK 0xfff0ffff
+#define RG_TURISMO_TRX_RXRF_DELAY_SFT 16
+#define RG_TURISMO_TRX_RXRF_DELAY_HI 19
+#define RG_TURISMO_TRX_RXRF_DELAY_SZ 4
+#define RG_TURISMO_TRX_TXBTPA_DELAY_MSK 0x00f00000
+#define RG_TURISMO_TRX_TXBTPA_DELAY_I_MSK 0xff0fffff
+#define RG_TURISMO_TRX_TXBTPA_DELAY_SFT 20
+#define RG_TURISMO_TRX_TXBTPA_DELAY_HI 23
+#define RG_TURISMO_TRX_TXBTPA_DELAY_SZ 4
+#define RG_TURISMO_TRX_TXDAC_T2R_DELAY_MSK 0x0000001f
+#define RG_TURISMO_TRX_TXDAC_T2R_DELAY_I_MSK 0xffffffe0
+#define RG_TURISMO_TRX_TXDAC_T2R_DELAY_SFT 0
+#define RG_TURISMO_TRX_TXDAC_T2R_DELAY_HI 4
+#define RG_TURISMO_TRX_TXDAC_T2R_DELAY_SZ 5
+#define RG_TURISMO_TRX_TXRF_T2R_DELAY_MSK 0x00001f00
+#define RG_TURISMO_TRX_TXRF_T2R_DELAY_I_MSK 0xffffe0ff
+#define RG_TURISMO_TRX_TXRF_T2R_DELAY_SFT 8
+#define RG_TURISMO_TRX_TXRF_T2R_DELAY_HI 12
+#define RG_TURISMO_TRX_TXRF_T2R_DELAY_SZ 5
+#define RG_TURISMO_TRX_TXPA_T2R_DELAY_MSK 0x001f0000
+#define RG_TURISMO_TRX_TXPA_T2R_DELAY_I_MSK 0xffe0ffff
+#define RG_TURISMO_TRX_TXPA_T2R_DELAY_SFT 16
+#define RG_TURISMO_TRX_TXPA_T2R_DELAY_HI 20
+#define RG_TURISMO_TRX_TXPA_T2R_DELAY_SZ 5
+#define RG_TURISMO_TRX_RXRF_T2R_DELAY_MSK 0x1f000000
+#define RG_TURISMO_TRX_RXRF_T2R_DELAY_I_MSK 0xe0ffffff
+#define RG_TURISMO_TRX_RXRF_T2R_DELAY_SFT 24
+#define RG_TURISMO_TRX_RXRF_T2R_DELAY_HI 28
+#define RG_TURISMO_TRX_RXRF_T2R_DELAY_SZ 5
+#define RG_TURISMO_TRX_TXDAC_R2T_DELAY_MSK 0x0000001f
+#define RG_TURISMO_TRX_TXDAC_R2T_DELAY_I_MSK 0xffffffe0
+#define RG_TURISMO_TRX_TXDAC_R2T_DELAY_SFT 0
+#define RG_TURISMO_TRX_TXDAC_R2T_DELAY_HI 4
+#define RG_TURISMO_TRX_TXDAC_R2T_DELAY_SZ 5
+#define RG_TURISMO_TRX_TXRF_R2T_DELAY_MSK 0x00001f00
+#define RG_TURISMO_TRX_TXRF_R2T_DELAY_I_MSK 0xffffe0ff
+#define RG_TURISMO_TRX_TXRF_R2T_DELAY_SFT 8
+#define RG_TURISMO_TRX_TXRF_R2T_DELAY_HI 12
+#define RG_TURISMO_TRX_TXRF_R2T_DELAY_SZ 5
+#define RG_TURISMO_TRX_TXPA_R2T_DELAY_MSK 0x001f0000
+#define RG_TURISMO_TRX_TXPA_R2T_DELAY_I_MSK 0xffe0ffff
+#define RG_TURISMO_TRX_TXPA_R2T_DELAY_SFT 16
+#define RG_TURISMO_TRX_TXPA_R2T_DELAY_HI 20
+#define RG_TURISMO_TRX_TXPA_R2T_DELAY_SZ 5
+#define RG_TURISMO_TRX_RXRF_R2T_DELAY_MSK 0x1f000000
+#define RG_TURISMO_TRX_RXRF_R2T_DELAY_I_MSK 0xe0ffffff
+#define RG_TURISMO_TRX_RXRF_R2T_DELAY_SFT 24
+#define RG_TURISMO_TRX_RXRF_R2T_DELAY_HI 28
+#define RG_TURISMO_TRX_RXRF_R2T_DELAY_SZ 5
+#define RG_TURISMO_TRX_WF_RX_DCCAL_DELAY_MSK 0x00000007
+#define RG_TURISMO_TRX_WF_RX_DCCAL_DELAY_I_MSK 0xfffffff8
+#define RG_TURISMO_TRX_WF_RX_DCCAL_DELAY_SFT 0
+#define RG_TURISMO_TRX_WF_RX_DCCAL_DELAY_HI 2
+#define RG_TURISMO_TRX_WF_RX_DCCAL_DELAY_SZ 3
+#define RG_TURISMO_TRX_BT_RX_DCCAL_DELAY_MSK 0x00000070
+#define RG_TURISMO_TRX_BT_RX_DCCAL_DELAY_I_MSK 0xffffff8f
+#define RG_TURISMO_TRX_BT_RX_DCCAL_DELAY_SFT 4
+#define RG_TURISMO_TRX_BT_RX_DCCAL_DELAY_HI 6
+#define RG_TURISMO_TRX_BT_RX_DCCAL_DELAY_SZ 3
+#define RG_TURISMO_TRX_RX_RCCAL_DELAY_MSK 0x00000700
+#define RG_TURISMO_TRX_RX_RCCAL_DELAY_I_MSK 0xfffff8ff
+#define RG_TURISMO_TRX_RX_RCCAL_DELAY_SFT 8
+#define RG_TURISMO_TRX_RX_RCCAL_DELAY_HI 10
+#define RG_TURISMO_TRX_RX_RCCAL_DELAY_SZ 3
+#define RG_TURISMO_TRX_TX_DCCAL_DELAY_MSK 0x00007000
+#define RG_TURISMO_TRX_TX_DCCAL_DELAY_I_MSK 0xffff8fff
+#define RG_TURISMO_TRX_TX_DCCAL_DELAY_SFT 12
+#define RG_TURISMO_TRX_TX_DCCAL_DELAY_HI 14
+#define RG_TURISMO_TRX_TX_DCCAL_DELAY_SZ 3
+#define RG_TURISMO_TRX_TX_IQCAL_DELAY_MSK 0x00070000
+#define RG_TURISMO_TRX_TX_IQCAL_DELAY_I_MSK 0xfff8ffff
+#define RG_TURISMO_TRX_TX_IQCAL_DELAY_SFT 16
+#define RG_TURISMO_TRX_TX_IQCAL_DELAY_HI 18
+#define RG_TURISMO_TRX_TX_IQCAL_DELAY_SZ 3
+#define RG_TURISMO_TRX_RX_IQCAL_DELAY_MSK 0x00700000
+#define RG_TURISMO_TRX_RX_IQCAL_DELAY_I_MSK 0xff8fffff
+#define RG_TURISMO_TRX_RX_IQCAL_DELAY_SFT 20
+#define RG_TURISMO_TRX_RX_IQCAL_DELAY_HI 22
+#define RG_TURISMO_TRX_RX_IQCAL_DELAY_SZ 3
+#define RG_TURISMO_TRX_RX_N_RCCAL_DELAY_MSK 0x07000000
+#define RG_TURISMO_TRX_RX_N_RCCAL_DELAY_I_MSK 0xf8ffffff
+#define RG_TURISMO_TRX_RX_N_RCCAL_DELAY_SFT 24
+#define RG_TURISMO_TRX_RX_N_RCCAL_DELAY_HI 26
+#define RG_TURISMO_TRX_RX_N_RCCAL_DELAY_SZ 3
+#define RG_TURISMO_TRX_PGAG_RCCAL_MSK 0x0000000f
+#define RG_TURISMO_TRX_PGAG_RCCAL_I_MSK 0xfffffff0
+#define RG_TURISMO_TRX_PGAG_RCCAL_SFT 0
+#define RG_TURISMO_TRX_PGAG_RCCAL_HI 3
+#define RG_TURISMO_TRX_PGAG_RCCAL_SZ 4
+#define RG_TURISMO_TRX_PGAG_TXCAL_MSK 0x000000f0
+#define RG_TURISMO_TRX_PGAG_TXCAL_I_MSK 0xffffff0f
+#define RG_TURISMO_TRX_PGAG_TXCAL_SFT 4
+#define RG_TURISMO_TRX_PGAG_TXCAL_HI 7
+#define RG_TURISMO_TRX_PGAG_TXCAL_SZ 4
+#define RG_TURISMO_TRX_TX_GAIN_TXCAL_MSK 0x00007f00
+#define RG_TURISMO_TRX_TX_GAIN_TXCAL_I_MSK 0xffff80ff
+#define RG_TURISMO_TRX_TX_GAIN_TXCAL_SFT 8
+#define RG_TURISMO_TRX_TX_GAIN_TXCAL_HI 14
+#define RG_TURISMO_TRX_TX_GAIN_TXCAL_SZ 7
+#define RG_TURISMO_TRX_RFG_RXIQCAL_MSK 0x00030000
+#define RG_TURISMO_TRX_RFG_RXIQCAL_I_MSK 0xfffcffff
+#define RG_TURISMO_TRX_RFG_RXIQCAL_SFT 16
+#define RG_TURISMO_TRX_RFG_RXIQCAL_HI 17
+#define RG_TURISMO_TRX_RFG_RXIQCAL_SZ 2
+#define RG_TURISMO_TRX_PGAG_RXIQCAL_MSK 0x003c0000
+#define RG_TURISMO_TRX_PGAG_RXIQCAL_I_MSK 0xffc3ffff
+#define RG_TURISMO_TRX_PGAG_RXIQCAL_SFT 18
+#define RG_TURISMO_TRX_PGAG_RXIQCAL_HI 21
+#define RG_TURISMO_TRX_PGAG_RXIQCAL_SZ 4
+#define RG_TURISMO_TRX_TX_GAIN_RXIQCAL_MSK 0x1fc00000
+#define RG_TURISMO_TRX_TX_GAIN_RXIQCAL_I_MSK 0xe03fffff
+#define RG_TURISMO_TRX_TX_GAIN_RXIQCAL_SFT 22
+#define RG_TURISMO_TRX_TX_GAIN_RXIQCAL_HI 28
+#define RG_TURISMO_TRX_TX_GAIN_RXIQCAL_SZ 7
+#define RG_TURISMO_TRX_RFG_DPDCAL_MSK 0x00000003
+#define RG_TURISMO_TRX_RFG_DPDCAL_I_MSK 0xfffffffc
+#define RG_TURISMO_TRX_RFG_DPDCAL_SFT 0
+#define RG_TURISMO_TRX_RFG_DPDCAL_HI 1
+#define RG_TURISMO_TRX_RFG_DPDCAL_SZ 2
+#define RG_TURISMO_TRX_PGAG_DPDCAL_MSK 0x0000003c
+#define RG_TURISMO_TRX_PGAG_DPDCAL_I_MSK 0xffffffc3
+#define RG_TURISMO_TRX_PGAG_DPDCAL_SFT 2
+#define RG_TURISMO_TRX_PGAG_DPDCAL_HI 5
+#define RG_TURISMO_TRX_PGAG_DPDCAL_SZ 4
+#define RG_TURISMO_TRX_TX_GAIN_DPDCAL_MSK 0x00001fc0
+#define RG_TURISMO_TRX_TX_GAIN_DPDCAL_I_MSK 0xffffe03f
+#define RG_TURISMO_TRX_TX_GAIN_DPDCAL_SFT 6
+#define RG_TURISMO_TRX_TX_GAIN_DPDCAL_HI 12
+#define RG_TURISMO_TRX_TX_GAIN_DPDCAL_SZ 7
+#define RG_TURISMO_TRX_IOT_ADC_CLKSEL_MSK 0x00010000
+#define RG_TURISMO_TRX_IOT_ADC_CLKSEL_I_MSK 0xfffeffff
+#define RG_TURISMO_TRX_IOT_ADC_CLKSEL_SFT 16
+#define RG_TURISMO_TRX_IOT_ADC_CLKSEL_HI 16
+#define RG_TURISMO_TRX_IOT_ADC_CLKSEL_SZ 1
+#define RG_TURISMO_TRX_IOT_ADC_DNLEN_MSK 0x00020000
+#define RG_TURISMO_TRX_IOT_ADC_DNLEN_I_MSK 0xfffdffff
+#define RG_TURISMO_TRX_IOT_ADC_DNLEN_SFT 17
+#define RG_TURISMO_TRX_IOT_ADC_DNLEN_HI 17
+#define RG_TURISMO_TRX_IOT_ADC_DNLEN_SZ 1
+#define RG_TURISMO_TRX_IOT_ADC_METAEN_MSK 0x00040000
+#define RG_TURISMO_TRX_IOT_ADC_METAEN_I_MSK 0xfffbffff
+#define RG_TURISMO_TRX_IOT_ADC_METAEN_SFT 18
+#define RG_TURISMO_TRX_IOT_ADC_METAEN_HI 18
+#define RG_TURISMO_TRX_IOT_ADC_METAEN_SZ 1
+#define RG_TURISMO_TRX_IOT_ADC_TFLAG_MSK 0x00080000
+#define RG_TURISMO_TRX_IOT_ADC_TFLAG_I_MSK 0xfff7ffff
+#define RG_TURISMO_TRX_IOT_ADC_TFLAG_SFT 19
+#define RG_TURISMO_TRX_IOT_ADC_TFLAG_HI 19
+#define RG_TURISMO_TRX_IOT_ADC_TFLAG_SZ 1
+#define RG_TURISMO_TRX_IOT_ADC_ICMP_MSK 0x00300000
+#define RG_TURISMO_TRX_IOT_ADC_ICMP_I_MSK 0xffcfffff
+#define RG_TURISMO_TRX_IOT_ADC_ICMP_SFT 20
+#define RG_TURISMO_TRX_IOT_ADC_ICMP_HI 21
+#define RG_TURISMO_TRX_IOT_ADC_ICMP_SZ 2
+#define RG_TURISMO_TRX_IOT_ADC_VCMI_MSK 0x00c00000
+#define RG_TURISMO_TRX_IOT_ADC_VCMI_I_MSK 0xff3fffff
+#define RG_TURISMO_TRX_IOT_ADC_VCMI_SFT 22
+#define RG_TURISMO_TRX_IOT_ADC_VCMI_HI 23
+#define RG_TURISMO_TRX_IOT_ADC_VCMI_SZ 2
+#define RG_TURISMO_TRX_IOT_ADC_CLOAD_MSK 0x03000000
+#define RG_TURISMO_TRX_IOT_ADC_CLOAD_I_MSK 0xfcffffff
+#define RG_TURISMO_TRX_IOT_ADC_CLOAD_SFT 24
+#define RG_TURISMO_TRX_IOT_ADC_CLOAD_HI 25
+#define RG_TURISMO_TRX_IOT_ADC_CLOAD_SZ 2
+#define RG_TURISMO_TRX_IOT_ADC_CLK_DIV_MSK 0x0c000000
+#define RG_TURISMO_TRX_IOT_ADC_CLK_DIV_I_MSK 0xf3ffffff
+#define RG_TURISMO_TRX_IOT_ADC_CLK_DIV_SFT 26
+#define RG_TURISMO_TRX_IOT_ADC_CLK_DIV_HI 27
+#define RG_TURISMO_TRX_IOT_ADC_CLK_DIV_SZ 2
+#define RG_TURISMO_TRX_IOT_ADC_CLK_SH_DUTY_MSK 0x10000000
+#define RG_TURISMO_TRX_IOT_ADC_CLK_SH_DUTY_I_MSK 0xefffffff
+#define RG_TURISMO_TRX_IOT_ADC_CLK_SH_DUTY_SFT 28
+#define RG_TURISMO_TRX_IOT_ADC_CLK_SH_DUTY_HI 28
+#define RG_TURISMO_TRX_IOT_ADC_CLK_SH_DUTY_SZ 1
+#define DB_TURISMO_TRX_AD_ADC_I_OUT_MSK 0x000003ff
+#define DB_TURISMO_TRX_AD_ADC_I_OUT_I_MSK 0xfffffc00
+#define DB_TURISMO_TRX_AD_ADC_I_OUT_SFT 0
+#define DB_TURISMO_TRX_AD_ADC_I_OUT_HI 9
+#define DB_TURISMO_TRX_AD_ADC_I_OUT_SZ 10
+#define DB_TURISMO_TRX_AD_ADC_Q_OUT_MSK 0x000ffc00
+#define DB_TURISMO_TRX_AD_ADC_Q_OUT_I_MSK 0xfff003ff
+#define DB_TURISMO_TRX_AD_ADC_Q_OUT_SFT 10
+#define DB_TURISMO_TRX_AD_ADC_Q_OUT_HI 19
+#define DB_TURISMO_TRX_AD_ADC_Q_OUT_SZ 10
+#define DB_TURISMO_TRX_AD_RX_RSSIADC_MSK 0x00f00000
+#define DB_TURISMO_TRX_AD_RX_RSSIADC_I_MSK 0xff0fffff
+#define DB_TURISMO_TRX_AD_RX_RSSIADC_SFT 20
+#define DB_TURISMO_TRX_AD_RX_RSSIADC_HI 23
+#define DB_TURISMO_TRX_AD_RX_RSSIADC_SZ 4
+#define DB_TURISMO_TRX_DA_SARADC_BIT_MSK 0x3f000000
+#define DB_TURISMO_TRX_DA_SARADC_BIT_I_MSK 0xc0ffffff
+#define DB_TURISMO_TRX_DA_SARADC_BIT_SFT 24
+#define DB_TURISMO_TRX_DA_SARADC_BIT_HI 29
+#define DB_TURISMO_TRX_DA_SARADC_BIT_SZ 6
+#define TURISMO_TRX_SAR_ADC_FSM_RDY_MSK 0x40000000
+#define TURISMO_TRX_SAR_ADC_FSM_RDY_I_MSK 0xbfffffff
+#define TURISMO_TRX_SAR_ADC_FSM_RDY_SFT 30
+#define TURISMO_TRX_SAR_ADC_FSM_RDY_HI 30
+#define TURISMO_TRX_SAR_ADC_FSM_RDY_SZ 1
+#define DB_TURISMO_TRX_DA_SX_SUB_SEL_MSK 0x000000ff
+#define DB_TURISMO_TRX_DA_SX_SUB_SEL_I_MSK 0xffffff00
+#define DB_TURISMO_TRX_DA_SX_SUB_SEL_SFT 0
+#define DB_TURISMO_TRX_DA_SX_SUB_SEL_HI 7
+#define DB_TURISMO_TRX_DA_SX_SUB_SEL_SZ 8
+#define DB_TURISMO_TRX_DA_SX_VCO_ISEL_MSK 0x00000f00
+#define DB_TURISMO_TRX_DA_SX_VCO_ISEL_I_MSK 0xfffff0ff
+#define DB_TURISMO_TRX_DA_SX_VCO_ISEL_SFT 8
+#define DB_TURISMO_TRX_DA_SX_VCO_ISEL_HI 11
+#define DB_TURISMO_TRX_DA_SX_VCO_ISEL_SZ 4
+#define DB_TURISMO_TRX_VO_AAC_COMPOUT_MSK 0x00001000
+#define DB_TURISMO_TRX_VO_AAC_COMPOUT_I_MSK 0xffffefff
+#define DB_TURISMO_TRX_VO_AAC_COMPOUT_SFT 12
+#define DB_TURISMO_TRX_VO_AAC_COMPOUT_HI 12
+#define DB_TURISMO_TRX_VO_AAC_COMPOUT_SZ 1
+#define DB_TURISMO_TRX_SX_TTL_VT_DET_MSK 0x0000c000
+#define DB_TURISMO_TRX_SX_TTL_VT_DET_I_MSK 0xffff3fff
+#define DB_TURISMO_TRX_SX_TTL_VT_DET_SFT 14
+#define DB_TURISMO_TRX_SX_TTL_VT_DET_HI 15
+#define DB_TURISMO_TRX_SX_TTL_VT_DET_SZ 2
+#define DB_TURISMO_TRX_AD_DP_VT_MON_Q_MSK 0x00030000
+#define DB_TURISMO_TRX_AD_DP_VT_MON_Q_I_MSK 0xfffcffff
+#define DB_TURISMO_TRX_AD_DP_VT_MON_Q_SFT 16
+#define DB_TURISMO_TRX_AD_DP_VT_MON_Q_HI 17
+#define DB_TURISMO_TRX_AD_DP_VT_MON_Q_SZ 2
+#define DB_TURISMO_TRX_AD_IOT_ADC_OUT_MSK 0x3ff00000
+#define DB_TURISMO_TRX_AD_IOT_ADC_OUT_I_MSK 0xc00fffff
+#define DB_TURISMO_TRX_AD_IOT_ADC_OUT_SFT 20
+#define DB_TURISMO_TRX_AD_IOT_ADC_OUT_HI 29
+#define DB_TURISMO_TRX_AD_IOT_ADC_OUT_SZ 10
+#define DB_TURISMO_TRX_SX_SBCAL_NCOUNT_MSK 0x0000ffff
+#define DB_TURISMO_TRX_SX_SBCAL_NCOUNT_I_MSK 0xffff0000
+#define DB_TURISMO_TRX_SX_SBCAL_NCOUNT_SFT 0
+#define DB_TURISMO_TRX_SX_SBCAL_NCOUNT_HI 15
+#define DB_TURISMO_TRX_SX_SBCAL_NCOUNT_SZ 16
+#define DB_TURISMO_TRX_SX_SBCAL_NTARGET_MSK 0xffff0000
+#define DB_TURISMO_TRX_SX_SBCAL_NTARGET_I_MSK 0x0000ffff
+#define DB_TURISMO_TRX_SX_SBCAL_NTARGET_SFT 16
+#define DB_TURISMO_TRX_SX_SBCAL_NTARGET_HI 31
+#define DB_TURISMO_TRX_SX_SBCAL_NTARGET_SZ 16
+#define RG_TURISMO_TRX_5G_TX_TRSW_MANUAL_MSK 0x00000001
+#define RG_TURISMO_TRX_5G_TX_TRSW_MANUAL_I_MSK 0xfffffffe
+#define RG_TURISMO_TRX_5G_TX_TRSW_MANUAL_SFT 0
+#define RG_TURISMO_TRX_5G_TX_TRSW_MANUAL_HI 0
+#define RG_TURISMO_TRX_5G_TX_TRSW_MANUAL_SZ 1
+#define RG_TURISMO_TRX_5G_EN_TX_TRSW_MSK 0x00000002
+#define RG_TURISMO_TRX_5G_EN_TX_TRSW_I_MSK 0xfffffffd
+#define RG_TURISMO_TRX_5G_EN_TX_TRSW_SFT 1
+#define RG_TURISMO_TRX_5G_EN_TX_TRSW_HI 1
+#define RG_TURISMO_TRX_5G_EN_TX_TRSW_SZ 1
+#define RG_TURISMO_TRX_5G_RX_LNA_MANUAL_MSK 0x00000004
+#define RG_TURISMO_TRX_5G_RX_LNA_MANUAL_I_MSK 0xfffffffb
+#define RG_TURISMO_TRX_5G_RX_LNA_MANUAL_SFT 2
+#define RG_TURISMO_TRX_5G_RX_LNA_MANUAL_HI 2
+#define RG_TURISMO_TRX_5G_RX_LNA_MANUAL_SZ 1
+#define RG_TURISMO_TRX_5G_EN_RX_LNA_MSK 0x00000008
+#define RG_TURISMO_TRX_5G_EN_RX_LNA_I_MSK 0xfffffff7
+#define RG_TURISMO_TRX_5G_EN_RX_LNA_SFT 3
+#define RG_TURISMO_TRX_5G_EN_RX_LNA_HI 3
+#define RG_TURISMO_TRX_5G_EN_RX_LNA_SZ 1
+#define RG_TURISMO_TRX_5G_RX_MIXER_MANUAL_MSK 0x00000010
+#define RG_TURISMO_TRX_5G_RX_MIXER_MANUAL_I_MSK 0xffffffef
+#define RG_TURISMO_TRX_5G_RX_MIXER_MANUAL_SFT 4
+#define RG_TURISMO_TRX_5G_RX_MIXER_MANUAL_HI 4
+#define RG_TURISMO_TRX_5G_RX_MIXER_MANUAL_SZ 1
+#define RG_TURISMO_TRX_5G_EN_RX_MIXER_MSK 0x00000020
+#define RG_TURISMO_TRX_5G_EN_RX_MIXER_I_MSK 0xffffffdf
+#define RG_TURISMO_TRX_5G_EN_RX_MIXER_SFT 5
+#define RG_TURISMO_TRX_5G_EN_RX_MIXER_HI 5
+#define RG_TURISMO_TRX_5G_EN_RX_MIXER_SZ 1
+#define RG_TURISMO_TRX_5G_RX_DIV2_MANUAL_MSK 0x00000040
+#define RG_TURISMO_TRX_5G_RX_DIV2_MANUAL_I_MSK 0xffffffbf
+#define RG_TURISMO_TRX_5G_RX_DIV2_MANUAL_SFT 6
+#define RG_TURISMO_TRX_5G_RX_DIV2_MANUAL_HI 6
+#define RG_TURISMO_TRX_5G_RX_DIV2_MANUAL_SZ 1
+#define RG_TURISMO_TRX_5G_EN_RX_DIV2_MSK 0x00000080
+#define RG_TURISMO_TRX_5G_EN_RX_DIV2_I_MSK 0xffffff7f
+#define RG_TURISMO_TRX_5G_EN_RX_DIV2_SFT 7
+#define RG_TURISMO_TRX_5G_EN_RX_DIV2_HI 7
+#define RG_TURISMO_TRX_5G_EN_RX_DIV2_SZ 1
+#define RG_TURISMO_TRX_5G_RX_LOBUF_MANUAL_MSK 0x00000100
+#define RG_TURISMO_TRX_5G_RX_LOBUF_MANUAL_I_MSK 0xfffffeff
+#define RG_TURISMO_TRX_5G_RX_LOBUF_MANUAL_SFT 8
+#define RG_TURISMO_TRX_5G_RX_LOBUF_MANUAL_HI 8
+#define RG_TURISMO_TRX_5G_RX_LOBUF_MANUAL_SZ 1
+#define RG_TURISMO_TRX_5G_EN_RX_LOBUF_MSK 0x00000200
+#define RG_TURISMO_TRX_5G_EN_RX_LOBUF_I_MSK 0xfffffdff
+#define RG_TURISMO_TRX_5G_EN_RX_LOBUF_SFT 9
+#define RG_TURISMO_TRX_5G_EN_RX_LOBUF_HI 9
+#define RG_TURISMO_TRX_5G_EN_RX_LOBUF_SZ 1
+#define RG_TURISMO_TRX_5G_RX_TZ_MANUAL_MSK 0x00000400
+#define RG_TURISMO_TRX_5G_RX_TZ_MANUAL_I_MSK 0xfffffbff
+#define RG_TURISMO_TRX_5G_RX_TZ_MANUAL_SFT 10
+#define RG_TURISMO_TRX_5G_RX_TZ_MANUAL_HI 10
+#define RG_TURISMO_TRX_5G_RX_TZ_MANUAL_SZ 1
+#define RG_TURISMO_TRX_5G_EN_RX_TZ_MSK 0x00000800
+#define RG_TURISMO_TRX_5G_EN_RX_TZ_I_MSK 0xfffff7ff
+#define RG_TURISMO_TRX_5G_EN_RX_TZ_SFT 11
+#define RG_TURISMO_TRX_5G_EN_RX_TZ_HI 11
+#define RG_TURISMO_TRX_5G_EN_RX_TZ_SZ 1
+#define RG_TURISMO_TRX_5G_TX_PA_MANUAL_MSK 0x00001000
+#define RG_TURISMO_TRX_5G_TX_PA_MANUAL_I_MSK 0xffffefff
+#define RG_TURISMO_TRX_5G_TX_PA_MANUAL_SFT 12
+#define RG_TURISMO_TRX_5G_TX_PA_MANUAL_HI 12
+#define RG_TURISMO_TRX_5G_TX_PA_MANUAL_SZ 1
+#define RG_TURISMO_TRX_5G_EN_TX_PA_MSK 0x00002000
+#define RG_TURISMO_TRX_5G_EN_TX_PA_I_MSK 0xffffdfff
+#define RG_TURISMO_TRX_5G_EN_TX_PA_SFT 13
+#define RG_TURISMO_TRX_5G_EN_TX_PA_HI 13
+#define RG_TURISMO_TRX_5G_EN_TX_PA_SZ 1
+#define RG_TURISMO_TRX_5G_TX_MOD_MANUAL_MSK 0x00004000
+#define RG_TURISMO_TRX_5G_TX_MOD_MANUAL_I_MSK 0xffffbfff
+#define RG_TURISMO_TRX_5G_TX_MOD_MANUAL_SFT 14
+#define RG_TURISMO_TRX_5G_TX_MOD_MANUAL_HI 14
+#define RG_TURISMO_TRX_5G_TX_MOD_MANUAL_SZ 1
+#define RG_TURISMO_TRX_5G_EN_TX_MOD_MSK 0x00008000
+#define RG_TURISMO_TRX_5G_EN_TX_MOD_I_MSK 0xffff7fff
+#define RG_TURISMO_TRX_5G_EN_TX_MOD_SFT 15
+#define RG_TURISMO_TRX_5G_EN_TX_MOD_HI 15
+#define RG_TURISMO_TRX_5G_EN_TX_MOD_SZ 1
+#define RG_TURISMO_TRX_5G_TX_DIV2_MANUAL_MSK 0x00040000
+#define RG_TURISMO_TRX_5G_TX_DIV2_MANUAL_I_MSK 0xfffbffff
+#define RG_TURISMO_TRX_5G_TX_DIV2_MANUAL_SFT 18
+#define RG_TURISMO_TRX_5G_TX_DIV2_MANUAL_HI 18
+#define RG_TURISMO_TRX_5G_TX_DIV2_MANUAL_SZ 1
+#define RG_TURISMO_TRX_5G_EN_TX_DIV2_MSK 0x00080000
+#define RG_TURISMO_TRX_5G_EN_TX_DIV2_I_MSK 0xfff7ffff
+#define RG_TURISMO_TRX_5G_EN_TX_DIV2_SFT 19
+#define RG_TURISMO_TRX_5G_EN_TX_DIV2_HI 19
+#define RG_TURISMO_TRX_5G_EN_TX_DIV2_SZ 1
+#define RG_TURISMO_TRX_5G_TX_DIV2_BUF_MANUAL_MSK 0x00100000
+#define RG_TURISMO_TRX_5G_TX_DIV2_BUF_MANUAL_I_MSK 0xffefffff
+#define RG_TURISMO_TRX_5G_TX_DIV2_BUF_MANUAL_SFT 20
+#define RG_TURISMO_TRX_5G_TX_DIV2_BUF_MANUAL_HI 20
+#define RG_TURISMO_TRX_5G_TX_DIV2_BUF_MANUAL_SZ 1
+#define RG_TURISMO_TRX_5G_EN_TX_DIV2_BUF_MSK 0x00200000
+#define RG_TURISMO_TRX_5G_EN_TX_DIV2_BUF_I_MSK 0xffdfffff
+#define RG_TURISMO_TRX_5G_EN_TX_DIV2_BUF_SFT 21
+#define RG_TURISMO_TRX_5G_EN_TX_DIV2_BUF_HI 21
+#define RG_TURISMO_TRX_5G_EN_TX_DIV2_BUF_SZ 1
+#define RG_TURISMO_TRX_5G_RX_TZ_OUT_TRISTATE_MANUAL_MSK 0x00400000
+#define RG_TURISMO_TRX_5G_RX_TZ_OUT_TRISTATE_MANUAL_I_MSK 0xffbfffff
+#define RG_TURISMO_TRX_5G_RX_TZ_OUT_TRISTATE_MANUAL_SFT 22
+#define RG_TURISMO_TRX_5G_RX_TZ_OUT_TRISTATE_MANUAL_HI 22
+#define RG_TURISMO_TRX_5G_RX_TZ_OUT_TRISTATE_MANUAL_SZ 1
+#define RG_TURISMO_TRX_5G_RX_TZ_OUT_TRISTATE_MSK 0x00800000
+#define RG_TURISMO_TRX_5G_RX_TZ_OUT_TRISTATE_I_MSK 0xff7fffff
+#define RG_TURISMO_TRX_5G_RX_TZ_OUT_TRISTATE_SFT 23
+#define RG_TURISMO_TRX_5G_RX_TZ_OUT_TRISTATE_HI 23
+#define RG_TURISMO_TRX_5G_RX_TZ_OUT_TRISTATE_SZ 1
+#define RG_TURISMO_TRX_5G_TX_SELF_MIXER_MANUAL_MSK 0x01000000
+#define RG_TURISMO_TRX_5G_TX_SELF_MIXER_MANUAL_I_MSK 0xfeffffff
+#define RG_TURISMO_TRX_5G_TX_SELF_MIXER_MANUAL_SFT 24
+#define RG_TURISMO_TRX_5G_TX_SELF_MIXER_MANUAL_HI 24
+#define RG_TURISMO_TRX_5G_TX_SELF_MIXER_MANUAL_SZ 1
+#define RG_TURISMO_TRX_5G_EN_TX_SELF_MIXER_MSK 0x02000000
+#define RG_TURISMO_TRX_5G_EN_TX_SELF_MIXER_I_MSK 0xfdffffff
+#define RG_TURISMO_TRX_5G_EN_TX_SELF_MIXER_SFT 25
+#define RG_TURISMO_TRX_5G_EN_TX_SELF_MIXER_HI 25
+#define RG_TURISMO_TRX_5G_EN_TX_SELF_MIXER_SZ 1
+#define RG_TURISMO_TRX_5G_RX_IQCAL_MANUAL_MSK 0x04000000
+#define RG_TURISMO_TRX_5G_RX_IQCAL_MANUAL_I_MSK 0xfbffffff
+#define RG_TURISMO_TRX_5G_RX_IQCAL_MANUAL_SFT 26
+#define RG_TURISMO_TRX_5G_RX_IQCAL_MANUAL_HI 26
+#define RG_TURISMO_TRX_5G_RX_IQCAL_MANUAL_SZ 1
+#define RG_TURISMO_TRX_5G_EN_RX_IQCAL_MSK 0x08000000
+#define RG_TURISMO_TRX_5G_EN_RX_IQCAL_I_MSK 0xf7ffffff
+#define RG_TURISMO_TRX_5G_EN_RX_IQCAL_SFT 27
+#define RG_TURISMO_TRX_5G_EN_RX_IQCAL_HI 27
+#define RG_TURISMO_TRX_5G_EN_RX_IQCAL_SZ 1
+#define RG_TURISMO_TRX_5G_TX_DPD_MANUAL_MSK 0x10000000
+#define RG_TURISMO_TRX_5G_TX_DPD_MANUAL_I_MSK 0xefffffff
+#define RG_TURISMO_TRX_5G_TX_DPD_MANUAL_SFT 28
+#define RG_TURISMO_TRX_5G_TX_DPD_MANUAL_HI 28
+#define RG_TURISMO_TRX_5G_TX_DPD_MANUAL_SZ 1
+#define RG_TURISMO_TRX_5G_EN_TX_DPD_MSK 0x20000000
+#define RG_TURISMO_TRX_5G_EN_TX_DPD_I_MSK 0xdfffffff
+#define RG_TURISMO_TRX_5G_EN_TX_DPD_SFT 29
+#define RG_TURISMO_TRX_5G_EN_TX_DPD_HI 29
+#define RG_TURISMO_TRX_5G_EN_TX_DPD_SZ 1
+#define RG_TURISMO_TRX_5G_EN_TX_TSSI_MSK 0x40000000
+#define RG_TURISMO_TRX_5G_EN_TX_TSSI_I_MSK 0xbfffffff
+#define RG_TURISMO_TRX_5G_EN_TX_TSSI_SFT 30
+#define RG_TURISMO_TRX_5G_EN_TX_TSSI_HI 30
+#define RG_TURISMO_TRX_5G_EN_TX_TSSI_SZ 1
+#define RG_TURISMO_TRX_5G_LDO_LEVEL_RX_FE_MSK 0x00000007
+#define RG_TURISMO_TRX_5G_LDO_LEVEL_RX_FE_I_MSK 0xfffffff8
+#define RG_TURISMO_TRX_5G_LDO_LEVEL_RX_FE_SFT 0
+#define RG_TURISMO_TRX_5G_LDO_LEVEL_RX_FE_HI 2
+#define RG_TURISMO_TRX_5G_LDO_LEVEL_RX_FE_SZ 3
+#define RG_TURISMO_TRX_5G_EN_LDO_RX_FE_BYP_MSK 0x00000008
+#define RG_TURISMO_TRX_5G_EN_LDO_RX_FE_BYP_I_MSK 0xfffffff7
+#define RG_TURISMO_TRX_5G_EN_LDO_RX_FE_BYP_SFT 3
+#define RG_TURISMO_TRX_5G_EN_LDO_RX_FE_BYP_HI 3
+#define RG_TURISMO_TRX_5G_EN_LDO_RX_FE_BYP_SZ 1
+#define RG_TURISMO_TRX_SX5GB_LDO_CP_LEVEL_MSK 0x00000070
+#define RG_TURISMO_TRX_SX5GB_LDO_CP_LEVEL_I_MSK 0xffffff8f
+#define RG_TURISMO_TRX_SX5GB_LDO_CP_LEVEL_SFT 4
+#define RG_TURISMO_TRX_SX5GB_LDO_CP_LEVEL_HI 6
+#define RG_TURISMO_TRX_SX5GB_LDO_CP_LEVEL_SZ 3
+#define RG_TURISMO_TRX_EN_LDO_5G_CP_BYP_MSK 0x00000080
+#define RG_TURISMO_TRX_EN_LDO_5G_CP_BYP_I_MSK 0xffffff7f
+#define RG_TURISMO_TRX_EN_LDO_5G_CP_BYP_SFT 7
+#define RG_TURISMO_TRX_EN_LDO_5G_CP_BYP_HI 7
+#define RG_TURISMO_TRX_EN_LDO_5G_CP_BYP_SZ 1
+#define RG_TURISMO_TRX_SX5GB_LDO_LO_LEVEL_MSK 0x00000700
+#define RG_TURISMO_TRX_SX5GB_LDO_LO_LEVEL_I_MSK 0xfffff8ff
+#define RG_TURISMO_TRX_SX5GB_LDO_LO_LEVEL_SFT 8
+#define RG_TURISMO_TRX_SX5GB_LDO_LO_LEVEL_HI 10
+#define RG_TURISMO_TRX_SX5GB_LDO_LO_LEVEL_SZ 3
+#define RG_TURISMO_TRX_EN_LDO_5G_LO_BYP_MSK 0x00000800
+#define RG_TURISMO_TRX_EN_LDO_5G_LO_BYP_I_MSK 0xfffff7ff
+#define RG_TURISMO_TRX_EN_LDO_5G_LO_BYP_SFT 11
+#define RG_TURISMO_TRX_EN_LDO_5G_LO_BYP_HI 11
+#define RG_TURISMO_TRX_EN_LDO_5G_LO_BYP_SZ 1
+#define RG_TURISMO_TRX_SX5GB_LDO_VCO_LEVEL_MSK 0x00007000
+#define RG_TURISMO_TRX_SX5GB_LDO_VCO_LEVEL_I_MSK 0xffff8fff
+#define RG_TURISMO_TRX_SX5GB_LDO_VCO_LEVEL_SFT 12
+#define RG_TURISMO_TRX_SX5GB_LDO_VCO_LEVEL_HI 14
+#define RG_TURISMO_TRX_SX5GB_LDO_VCO_LEVEL_SZ 3
+#define RG_TURISMO_TRX_SX5GB_LDO_DIV_LEVEL_MSK 0x00070000
+#define RG_TURISMO_TRX_SX5GB_LDO_DIV_LEVEL_I_MSK 0xfff8ffff
+#define RG_TURISMO_TRX_SX5GB_LDO_DIV_LEVEL_SFT 16
+#define RG_TURISMO_TRX_SX5GB_LDO_DIV_LEVEL_HI 18
+#define RG_TURISMO_TRX_SX5GB_LDO_DIV_LEVEL_SZ 3
+#define RG_TURISMO_TRX_EN_LDO_5G_DIV_BYP_MSK 0x00080000
+#define RG_TURISMO_TRX_EN_LDO_5G_DIV_BYP_I_MSK 0xfff7ffff
+#define RG_TURISMO_TRX_EN_LDO_5G_DIV_BYP_SFT 19
+#define RG_TURISMO_TRX_EN_LDO_5G_DIV_BYP_HI 19
+#define RG_TURISMO_TRX_EN_LDO_5G_DIV_BYP_SZ 1
+#define RG_TURISMO_TRX_5G_EN_LDO_RX_FE_MSK 0x01000000
+#define RG_TURISMO_TRX_5G_EN_LDO_RX_FE_I_MSK 0xfeffffff
+#define RG_TURISMO_TRX_5G_EN_LDO_RX_FE_SFT 24
+#define RG_TURISMO_TRX_5G_EN_LDO_RX_FE_HI 24
+#define RG_TURISMO_TRX_5G_EN_LDO_RX_FE_SZ 1
+#define RG_TURISMO_TRX_5G_EN_IREF_RX_MSK 0x02000000
+#define RG_TURISMO_TRX_5G_EN_IREF_RX_I_MSK 0xfdffffff
+#define RG_TURISMO_TRX_5G_EN_IREF_RX_SFT 25
+#define RG_TURISMO_TRX_5G_EN_IREF_RX_HI 25
+#define RG_TURISMO_TRX_5G_EN_IREF_RX_SZ 1
+#define RG_TURISMO_TRX_5G_EN_LDO_RX_FE_FC_MSK 0x04000000
+#define RG_TURISMO_TRX_5G_EN_LDO_RX_FE_FC_I_MSK 0xfbffffff
+#define RG_TURISMO_TRX_5G_EN_LDO_RX_FE_FC_SFT 26
+#define RG_TURISMO_TRX_5G_EN_LDO_RX_FE_FC_HI 26
+#define RG_TURISMO_TRX_5G_EN_LDO_RX_FE_FC_SZ 1
+#define RG_TURISMO_TRX_5G_EN_LDO_RX_FE_IQUP_MSK 0x08000000
+#define RG_TURISMO_TRX_5G_EN_LDO_RX_FE_IQUP_I_MSK 0xf7ffffff
+#define RG_TURISMO_TRX_5G_EN_LDO_RX_FE_IQUP_SFT 27
+#define RG_TURISMO_TRX_5G_EN_LDO_RX_FE_IQUP_HI 27
+#define RG_TURISMO_TRX_5G_EN_LDO_RX_FE_IQUP_SZ 1
+#define RG_TURISMO_TRX_5G_RX_SCA_MANUAL_MSK 0x00000001
+#define RG_TURISMO_TRX_5G_RX_SCA_MANUAL_I_MSK 0xfffffffe
+#define RG_TURISMO_TRX_5G_RX_SCA_MANUAL_SFT 0
+#define RG_TURISMO_TRX_5G_RX_SCA_MANUAL_HI 0
+#define RG_TURISMO_TRX_5G_RX_SCA_MANUAL_SZ 1
+#define RG_TURISMO_TRX_5G_RX_SCA_MA_MSK 0x0000000e
+#define RG_TURISMO_TRX_5G_RX_SCA_MA_I_MSK 0xfffffff1
+#define RG_TURISMO_TRX_5G_RX_SCA_MA_SFT 1
+#define RG_TURISMO_TRX_5G_RX_SCA_MA_HI 3
+#define RG_TURISMO_TRX_5G_RX_SCA_MA_SZ 3
+#define RG_TURISMO_TRX_5G_RX_SCA_LOAD_MSK 0x00000070
+#define RG_TURISMO_TRX_5G_RX_SCA_LOAD_I_MSK 0xffffff8f
+#define RG_TURISMO_TRX_5G_RX_SCA_LOAD_SFT 4
+#define RG_TURISMO_TRX_5G_RX_SCA_LOAD_HI 6
+#define RG_TURISMO_TRX_5G_RX_SCA_LOAD_SZ 3
+#define RG_TURISMO_TRX_5G_RX_LNA_TRI_SEL_MSK 0x00000300
+#define RG_TURISMO_TRX_5G_RX_LNA_TRI_SEL_I_MSK 0xfffffcff
+#define RG_TURISMO_TRX_5G_RX_LNA_TRI_SEL_SFT 8
+#define RG_TURISMO_TRX_5G_RX_LNA_TRI_SEL_HI 9
+#define RG_TURISMO_TRX_5G_RX_LNA_TRI_SEL_SZ 2
+#define RG_TURISMO_TRX_5G_RX_LNA_SETTLE_MSK 0x00000c00
+#define RG_TURISMO_TRX_5G_RX_LNA_SETTLE_I_MSK 0xfffff3ff
+#define RG_TURISMO_TRX_5G_RX_LNA_SETTLE_SFT 10
+#define RG_TURISMO_TRX_5G_RX_LNA_SETTLE_HI 11
+#define RG_TURISMO_TRX_5G_RX_LNA_SETTLE_SZ 2
+#define RG_TURISMO_TRX_5G_RX_GM_IDB_MSK 0x00001000
+#define RG_TURISMO_TRX_5G_RX_GM_IDB_I_MSK 0xffffefff
+#define RG_TURISMO_TRX_5G_RX_GM_IDB_SFT 12
+#define RG_TURISMO_TRX_5G_RX_GM_IDB_HI 12
+#define RG_TURISMO_TRX_5G_RX_GM_IDB_SZ 1
+#define RG_TURISMO_TRX_5G_GM_BIAS_MSK 0x00006000
+#define RG_TURISMO_TRX_5G_GM_BIAS_I_MSK 0xffff9fff
+#define RG_TURISMO_TRX_5G_GM_BIAS_SFT 13
+#define RG_TURISMO_TRX_5G_GM_BIAS_HI 14
+#define RG_TURISMO_TRX_5G_GM_BIAS_SZ 2
+#define RG_TURISMO_TRX_5G_RX_DIV2_BUF_MSK 0x00030000
+#define RG_TURISMO_TRX_5G_RX_DIV2_BUF_I_MSK 0xfffcffff
+#define RG_TURISMO_TRX_5G_RX_DIV2_BUF_SFT 16
+#define RG_TURISMO_TRX_5G_RX_DIV2_BUF_HI 17
+#define RG_TURISMO_TRX_5G_RX_DIV2_BUF_SZ 2
+#define RG_TURISMO_TRX_5G_RX_DIV2_CML_MSK 0x000c0000
+#define RG_TURISMO_TRX_5G_RX_DIV2_CML_I_MSK 0xfff3ffff
+#define RG_TURISMO_TRX_5G_RX_DIV2_CML_SFT 18
+#define RG_TURISMO_TRX_5G_RX_DIV2_CML_HI 19
+#define RG_TURISMO_TRX_5G_RX_DIV2_CML_SZ 2
+#define RG_TURISMO_TRX_5G_RX_DIV_CMLISEL_MSK 0x00300000
+#define RG_TURISMO_TRX_5G_RX_DIV_CMLISEL_I_MSK 0xffcfffff
+#define RG_TURISMO_TRX_5G_RX_DIV_CMLISEL_SFT 20
+#define RG_TURISMO_TRX_5G_RX_DIV_CMLISEL_HI 21
+#define RG_TURISMO_TRX_5G_RX_DIV_CMLISEL_SZ 2
+#define RG_TURISMO_TRX_5G_RX_DIV_PREBUFS2_MSK 0x00400000
+#define RG_TURISMO_TRX_5G_RX_DIV_PREBUFS2_I_MSK 0xffbfffff
+#define RG_TURISMO_TRX_5G_RX_DIV_PREBUFS2_SFT 22
+#define RG_TURISMO_TRX_5G_RX_DIV_PREBUFS2_HI 22
+#define RG_TURISMO_TRX_5G_RX_DIV_PREBUFS2_SZ 1
+#define RG_TURISMO_TRX_5G_RX_TZ_COURSE_MSK 0x03000000
+#define RG_TURISMO_TRX_5G_RX_TZ_COURSE_I_MSK 0xfcffffff
+#define RG_TURISMO_TRX_5G_RX_TZ_COURSE_SFT 24
+#define RG_TURISMO_TRX_5G_RX_TZ_COURSE_HI 25
+#define RG_TURISMO_TRX_5G_RX_TZ_COURSE_SZ 2
+#define RG_TURISMO_TRX_5G_TX_DPDGM_BIAS_MSK 0xf0000000
+#define RG_TURISMO_TRX_5G_TX_DPDGM_BIAS_I_MSK 0x0fffffff
+#define RG_TURISMO_TRX_5G_TX_DPDGM_BIAS_SFT 28
+#define RG_TURISMO_TRX_5G_TX_DPDGM_BIAS_HI 31
+#define RG_TURISMO_TRX_5G_TX_DPDGM_BIAS_SZ 4
+#define RG_TURISMO_TRX_5G_TX_DPD_DIV_MSK 0x0000000f
+#define RG_TURISMO_TRX_5G_TX_DPD_DIV_I_MSK 0xfffffff0
+#define RG_TURISMO_TRX_5G_TX_DPD_DIV_SFT 0
+#define RG_TURISMO_TRX_5G_TX_DPD_DIV_HI 3
+#define RG_TURISMO_TRX_5G_TX_DPD_DIV_SZ 4
+#define RG_TURISMO_TRX_5G_TX_TSSI_BIAS_MSK 0x00000070
+#define RG_TURISMO_TRX_5G_TX_TSSI_BIAS_I_MSK 0xffffff8f
+#define RG_TURISMO_TRX_5G_TX_TSSI_BIAS_SFT 4
+#define RG_TURISMO_TRX_5G_TX_TSSI_BIAS_HI 6
+#define RG_TURISMO_TRX_5G_TX_TSSI_BIAS_SZ 3
+#define RG_TURISMO_TRX_5G_TX_TSSI_DIV_MSK 0x00000700
+#define RG_TURISMO_TRX_5G_TX_TSSI_DIV_I_MSK 0xfffff8ff
+#define RG_TURISMO_TRX_5G_TX_TSSI_DIV_SFT 8
+#define RG_TURISMO_TRX_5G_TX_TSSI_DIV_HI 10
+#define RG_TURISMO_TRX_5G_TX_TSSI_DIV_SZ 3
+#define RG_TURISMO_TRX_5G_TX_TSSI_TEST_MSK 0x00003000
+#define RG_TURISMO_TRX_5G_TX_TSSI_TEST_I_MSK 0xffffcfff
+#define RG_TURISMO_TRX_5G_TX_TSSI_TEST_SFT 12
+#define RG_TURISMO_TRX_5G_TX_TSSI_TEST_HI 13
+#define RG_TURISMO_TRX_5G_TX_TSSI_TEST_SZ 2
+#define RG_TURISMO_TRX_5G_TX_TSSI_TESTMODE_MSK 0x00004000
+#define RG_TURISMO_TRX_5G_TX_TSSI_TESTMODE_I_MSK 0xffffbfff
+#define RG_TURISMO_TRX_5G_TX_TSSI_TESTMODE_SFT 14
+#define RG_TURISMO_TRX_5G_TX_TSSI_TESTMODE_HI 14
+#define RG_TURISMO_TRX_5G_TX_TSSI_TESTMODE_SZ 1
+#define RG_TURISMO_TRX_5G_RX_ADC_ICMP_MSK 0x00030000
+#define RG_TURISMO_TRX_5G_RX_ADC_ICMP_I_MSK 0xfffcffff
+#define RG_TURISMO_TRX_5G_RX_ADC_ICMP_SFT 16
+#define RG_TURISMO_TRX_5G_RX_ADC_ICMP_HI 17
+#define RG_TURISMO_TRX_5G_RX_ADC_ICMP_SZ 2
+#define RG_TURISMO_TRX_5G_RX_ADC_VCMI_MSK 0x000c0000
+#define RG_TURISMO_TRX_5G_RX_ADC_VCMI_I_MSK 0xfff3ffff
+#define RG_TURISMO_TRX_5G_RX_ADC_VCMI_SFT 18
+#define RG_TURISMO_TRX_5G_RX_ADC_VCMI_HI 19
+#define RG_TURISMO_TRX_5G_RX_ADC_VCMI_SZ 2
+#define RG_TURISMO_TRX_5G_RX_ADC_CLOAD_MSK 0x00300000
+#define RG_TURISMO_TRX_5G_RX_ADC_CLOAD_I_MSK 0xffcfffff
+#define RG_TURISMO_TRX_5G_RX_ADC_CLOAD_SFT 20
+#define RG_TURISMO_TRX_5G_RX_ADC_CLOAD_HI 21
+#define RG_TURISMO_TRX_5G_RX_ADC_CLOAD_SZ 2
+#define RG_TURISMO_TRX_5G_TXPGA_CAPSW_MANUAL_MSK 0x00000001
+#define RG_TURISMO_TRX_5G_TXPGA_CAPSW_MANUAL_I_MSK 0xfffffffe
+#define RG_TURISMO_TRX_5G_TXPGA_CAPSW_MANUAL_SFT 0
+#define RG_TURISMO_TRX_5G_TXPGA_CAPSW_MANUAL_HI 0
+#define RG_TURISMO_TRX_5G_TXPGA_CAPSW_MANUAL_SZ 1
+#define RG_TURISMO_TRX_5G_TXPGA_CAPSW_MSK 0x0000000e
+#define RG_TURISMO_TRX_5G_TXPGA_CAPSW_I_MSK 0xfffffff1
+#define RG_TURISMO_TRX_5G_TXPGA_CAPSW_SFT 1
+#define RG_TURISMO_TRX_5G_TXPGA_CAPSW_HI 3
+#define RG_TURISMO_TRX_5G_TXPGA_CAPSW_SZ 3
+#define RG_TURISMO_TRX_5G_TX_ADDGMCELL_MSK 0x00000010
+#define RG_TURISMO_TRX_5G_TX_ADDGMCELL_I_MSK 0xffffffef
+#define RG_TURISMO_TRX_5G_TX_ADDGMCELL_SFT 4
+#define RG_TURISMO_TRX_5G_TX_ADDGMCELL_HI 4
+#define RG_TURISMO_TRX_5G_TX_ADDGMCELL_SZ 1
+#define RG_TURISMO_TRX_5G_PACELL_EN_MSK 0x000000e0
+#define RG_TURISMO_TRX_5G_PACELL_EN_I_MSK 0xffffff1f
+#define RG_TURISMO_TRX_5G_PACELL_EN_SFT 5
+#define RG_TURISMO_TRX_5G_PACELL_EN_HI 7
+#define RG_TURISMO_TRX_5G_PACELL_EN_SZ 3
+#define RG_TURISMO_TRX_5G_PABIAS_CTRL_MSK 0x00000f00
+#define RG_TURISMO_TRX_5G_PABIAS_CTRL_I_MSK 0xfffff0ff
+#define RG_TURISMO_TRX_5G_PABIAS_CTRL_SFT 8
+#define RG_TURISMO_TRX_5G_PABIAS_CTRL_HI 11
+#define RG_TURISMO_TRX_5G_PABIAS_CTRL_SZ 4
+#define RG_TURISMO_TRX_5G_TX_PAFB_EN_MSK 0x00001000
+#define RG_TURISMO_TRX_5G_TX_PAFB_EN_I_MSK 0xffffefff
+#define RG_TURISMO_TRX_5G_TX_PAFB_EN_SFT 12
+#define RG_TURISMO_TRX_5G_TX_PAFB_EN_HI 12
+#define RG_TURISMO_TRX_5G_TX_PAFB_EN_SZ 1
+#define RG_TURISMO_TRX_5G_TX_PA1_VCAS_MSK 0x0000e000
+#define RG_TURISMO_TRX_5G_TX_PA1_VCAS_I_MSK 0xffff1fff
+#define RG_TURISMO_TRX_5G_TX_PA1_VCAS_SFT 13
+#define RG_TURISMO_TRX_5G_TX_PA1_VCAS_HI 15
+#define RG_TURISMO_TRX_5G_TX_PA1_VCAS_SZ 3
+#define RG_TURISMO_TRX_5G_TX_PA2_VCAS_MSK 0x00070000
+#define RG_TURISMO_TRX_5G_TX_PA2_VCAS_I_MSK 0xfff8ffff
+#define RG_TURISMO_TRX_5G_TX_PA2_VCAS_SFT 16
+#define RG_TURISMO_TRX_5G_TX_PA2_VCAS_HI 18
+#define RG_TURISMO_TRX_5G_TX_PA2_VCAS_SZ 3
+#define RG_TURISMO_TRX_5G_TX_PA3_VCAS_MSK 0x00700000
+#define RG_TURISMO_TRX_5G_TX_PA3_VCAS_I_MSK 0xff8fffff
+#define RG_TURISMO_TRX_5G_TX_PA3_VCAS_SFT 20
+#define RG_TURISMO_TRX_5G_TX_PA3_VCAS_HI 22
+#define RG_TURISMO_TRX_5G_TX_PA3_VCAS_SZ 3
+#define RG_TURISMO_TRX_5G_TX_DIV_PREBUFS2_MSK 0x00800000
+#define RG_TURISMO_TRX_5G_TX_DIV_PREBUFS2_I_MSK 0xff7fffff
+#define RG_TURISMO_TRX_5G_TX_DIV_PREBUFS2_SFT 23
+#define RG_TURISMO_TRX_5G_TX_DIV_PREBUFS2_HI 23
+#define RG_TURISMO_TRX_5G_TX_DIV_PREBUFS2_SZ 1
+#define RG_TURISMO_TRX_5G_TX_DIV_CMLISEL_MSK 0x03000000
+#define RG_TURISMO_TRX_5G_TX_DIV_CMLISEL_I_MSK 0xfcffffff
+#define RG_TURISMO_TRX_5G_TX_DIV_CMLISEL_SFT 24
+#define RG_TURISMO_TRX_5G_TX_DIV_CMLISEL_HI 25
+#define RG_TURISMO_TRX_5G_TX_DIV_CMLISEL_SZ 2
+#define RG_TURISMO_TRX_5G_TX_DIV_CMLVSEL_MSK 0x0c000000
+#define RG_TURISMO_TRX_5G_TX_DIV_CMLVSEL_I_MSK 0xf3ffffff
+#define RG_TURISMO_TRX_5G_TX_DIV_CMLVSEL_SFT 26
+#define RG_TURISMO_TRX_5G_TX_DIV_CMLVSEL_HI 27
+#define RG_TURISMO_TRX_5G_TX_DIV_CMLVSEL_SZ 2
+#define RG_TURISMO_TRX_5G_TX_DIV_VSET_MSK 0x30000000
+#define RG_TURISMO_TRX_5G_TX_DIV_VSET_I_MSK 0xcfffffff
+#define RG_TURISMO_TRX_5G_TX_DIV_VSET_SFT 28
+#define RG_TURISMO_TRX_5G_TX_DIV_VSET_HI 29
+#define RG_TURISMO_TRX_5G_TX_DIV_VSET_SZ 2
+#define RG_TURISMO_TRX_5G_TX_LOBUF_VSET_MSK 0xc0000000
+#define RG_TURISMO_TRX_5G_TX_LOBUF_VSET_I_MSK 0x3fffffff
+#define RG_TURISMO_TRX_5G_TX_LOBUF_VSET_SFT 30
+#define RG_TURISMO_TRX_5G_TX_LOBUF_VSET_HI 31
+#define RG_TURISMO_TRX_5G_TX_LOBUF_VSET_SZ 2
+#define RG_TURISMO_TRX_5G_TXPGA_MAIN_MSK 0x0000003f
+#define RG_TURISMO_TRX_5G_TXPGA_MAIN_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_5G_TXPGA_MAIN_SFT 0
+#define RG_TURISMO_TRX_5G_TXPGA_MAIN_HI 5
+#define RG_TURISMO_TRX_5G_TXPGA_MAIN_SZ 6
+#define RG_TURISMO_TRX_5G_TXPGA_STEER_MSK 0x00000fc0
+#define RG_TURISMO_TRX_5G_TXPGA_STEER_I_MSK 0xfffff03f
+#define RG_TURISMO_TRX_5G_TXPGA_STEER_SFT 6
+#define RG_TURISMO_TRX_5G_TXPGA_STEER_HI 11
+#define RG_TURISMO_TRX_5G_TXPGA_STEER_SZ 6
+#define RG_TURISMO_TRX_5G_TXMOD_GMCELL_MSK 0x00003000
+#define RG_TURISMO_TRX_5G_TXMOD_GMCELL_I_MSK 0xffffcfff
+#define RG_TURISMO_TRX_5G_TXMOD_GMCELL_SFT 12
+#define RG_TURISMO_TRX_5G_TXMOD_GMCELL_HI 13
+#define RG_TURISMO_TRX_5G_TXMOD_GMCELL_SZ 2
+#define RG_TURISMO_TRX_5G_TX_GAIN_OFFSET_MSK 0x000f0000
+#define RG_TURISMO_TRX_5G_TX_GAIN_OFFSET_I_MSK 0xfff0ffff
+#define RG_TURISMO_TRX_5G_TX_GAIN_OFFSET_SFT 16
+#define RG_TURISMO_TRX_5G_TX_GAIN_OFFSET_HI 19
+#define RG_TURISMO_TRX_5G_TX_GAIN_OFFSET_SZ 4
+#define RG_TURISMO_TRX_5G_TX_GAIN_MSK 0x07f00000
+#define RG_TURISMO_TRX_5G_TX_GAIN_I_MSK 0xf80fffff
+#define RG_TURISMO_TRX_5G_TX_GAIN_SFT 20
+#define RG_TURISMO_TRX_5G_TX_GAIN_HI 26
+#define RG_TURISMO_TRX_5G_TX_GAIN_SZ 7
+#define RG_TURISMO_TRX_5G_RX_HG_LNA_GC_MSK 0x00000003
+#define RG_TURISMO_TRX_5G_RX_HG_LNA_GC_I_MSK 0xfffffffc
+#define RG_TURISMO_TRX_5G_RX_HG_LNA_GC_SFT 0
+#define RG_TURISMO_TRX_5G_RX_HG_LNA_GC_HI 1
+#define RG_TURISMO_TRX_5G_RX_HG_LNA_GC_SZ 2
+#define RG_TURISMO_TRX_5G_RX_HG_TZ_GC_MSK 0x0000000c
+#define RG_TURISMO_TRX_5G_RX_HG_TZ_GC_I_MSK 0xfffffff3
+#define RG_TURISMO_TRX_5G_RX_HG_TZ_GC_SFT 2
+#define RG_TURISMO_TRX_5G_RX_HG_TZ_GC_HI 3
+#define RG_TURISMO_TRX_5G_RX_HG_TZ_GC_SZ 2
+#define RG_TURISMO_TRX_5G_RX_HG_LNAHGN_BIAS_MSK 0x000000f0
+#define RG_TURISMO_TRX_5G_RX_HG_LNAHGN_BIAS_I_MSK 0xffffff0f
+#define RG_TURISMO_TRX_5G_RX_HG_LNAHGN_BIAS_SFT 4
+#define RG_TURISMO_TRX_5G_RX_HG_LNAHGN_BIAS_HI 7
+#define RG_TURISMO_TRX_5G_RX_HG_LNAHGN_BIAS_SZ 4
+#define RG_TURISMO_TRX_5G_RX_HG_LNAHGP_BIAS_MSK 0x00000f00
+#define RG_TURISMO_TRX_5G_RX_HG_LNAHGP_BIAS_I_MSK 0xfffff0ff
+#define RG_TURISMO_TRX_5G_RX_HG_LNAHGP_BIAS_SFT 8
+#define RG_TURISMO_TRX_5G_RX_HG_LNAHGP_BIAS_HI 11
+#define RG_TURISMO_TRX_5G_RX_HG_LNAHGP_BIAS_SZ 4
+#define RG_TURISMO_TRX_5G_RX_HG_LNALG_BIAS_MSK 0x0000f000
+#define RG_TURISMO_TRX_5G_RX_HG_LNALG_BIAS_I_MSK 0xffff0fff
+#define RG_TURISMO_TRX_5G_RX_HG_LNALG_BIAS_SFT 12
+#define RG_TURISMO_TRX_5G_RX_HG_LNALG_BIAS_HI 15
+#define RG_TURISMO_TRX_5G_RX_HG_LNALG_BIAS_SZ 4
+#define RG_TURISMO_TRX_5G_RX_HG_TZ_CAP_MSK 0x00070000
+#define RG_TURISMO_TRX_5G_RX_HG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_TURISMO_TRX_5G_RX_HG_TZ_CAP_SFT 16
+#define RG_TURISMO_TRX_5G_RX_HG_TZ_CAP_HI 18
+#define RG_TURISMO_TRX_5G_RX_HG_TZ_CAP_SZ 3
+#define RG_TURISMO_TRX_5G_RX_HG_SQDC_MSK 0x00380000
+#define RG_TURISMO_TRX_5G_RX_HG_SQDC_I_MSK 0xffc7ffff
+#define RG_TURISMO_TRX_5G_RX_HG_SQDC_SFT 19
+#define RG_TURISMO_TRX_5G_RX_HG_SQDC_HI 21
+#define RG_TURISMO_TRX_5G_RX_HG_SQDC_SZ 3
+#define RG_TURISMO_TRX_5G_RX_HG_DIV2_CORE_MSK 0x00c00000
+#define RG_TURISMO_TRX_5G_RX_HG_DIV2_CORE_I_MSK 0xff3fffff
+#define RG_TURISMO_TRX_5G_RX_HG_DIV2_CORE_SFT 22
+#define RG_TURISMO_TRX_5G_RX_HG_DIV2_CORE_HI 23
+#define RG_TURISMO_TRX_5G_RX_HG_DIV2_CORE_SZ 2
+#define RG_TURISMO_TRX_5G_RX_HG_TZ_GC_BOOST_MSK 0x03000000
+#define RG_TURISMO_TRX_5G_RX_HG_TZ_GC_BOOST_I_MSK 0xfcffffff
+#define RG_TURISMO_TRX_5G_RX_HG_TZ_GC_BOOST_SFT 24
+#define RG_TURISMO_TRX_5G_RX_HG_TZ_GC_BOOST_HI 25
+#define RG_TURISMO_TRX_5G_RX_HG_TZ_GC_BOOST_SZ 2
+#define RG_TURISMO_TRX_5G_RX_HG_TZI_MSK 0x1c000000
+#define RG_TURISMO_TRX_5G_RX_HG_TZI_I_MSK 0xe3ffffff
+#define RG_TURISMO_TRX_5G_RX_HG_TZI_SFT 26
+#define RG_TURISMO_TRX_5G_RX_HG_TZI_HI 28
+#define RG_TURISMO_TRX_5G_RX_HG_TZI_SZ 3
+#define RG_TURISMO_TRX_5G_RX_HG_TZ_VCM_MSK 0xe0000000
+#define RG_TURISMO_TRX_5G_RX_HG_TZ_VCM_I_MSK 0x1fffffff
+#define RG_TURISMO_TRX_5G_RX_HG_TZ_VCM_SFT 29
+#define RG_TURISMO_TRX_5G_RX_HG_TZ_VCM_HI 31
+#define RG_TURISMO_TRX_5G_RX_HG_TZ_VCM_SZ 3
+#define RG_TURISMO_TRX_5G_RX_MG_LNA_GC_MSK 0x00000003
+#define RG_TURISMO_TRX_5G_RX_MG_LNA_GC_I_MSK 0xfffffffc
+#define RG_TURISMO_TRX_5G_RX_MG_LNA_GC_SFT 0
+#define RG_TURISMO_TRX_5G_RX_MG_LNA_GC_HI 1
+#define RG_TURISMO_TRX_5G_RX_MG_LNA_GC_SZ 2
+#define RG_TURISMO_TRX_5G_RX_MG_TZ_GC_MSK 0x0000000c
+#define RG_TURISMO_TRX_5G_RX_MG_TZ_GC_I_MSK 0xfffffff3
+#define RG_TURISMO_TRX_5G_RX_MG_TZ_GC_SFT 2
+#define RG_TURISMO_TRX_5G_RX_MG_TZ_GC_HI 3
+#define RG_TURISMO_TRX_5G_RX_MG_TZ_GC_SZ 2
+#define RG_TURISMO_TRX_5G_RX_MG_LNAHGN_BIAS_MSK 0x000000f0
+#define RG_TURISMO_TRX_5G_RX_MG_LNAHGN_BIAS_I_MSK 0xffffff0f
+#define RG_TURISMO_TRX_5G_RX_MG_LNAHGN_BIAS_SFT 4
+#define RG_TURISMO_TRX_5G_RX_MG_LNAHGN_BIAS_HI 7
+#define RG_TURISMO_TRX_5G_RX_MG_LNAHGN_BIAS_SZ 4
+#define RG_TURISMO_TRX_5G_RX_MG_LNAHGP_BIAS_MSK 0x00000f00
+#define RG_TURISMO_TRX_5G_RX_MG_LNAHGP_BIAS_I_MSK 0xfffff0ff
+#define RG_TURISMO_TRX_5G_RX_MG_LNAHGP_BIAS_SFT 8
+#define RG_TURISMO_TRX_5G_RX_MG_LNAHGP_BIAS_HI 11
+#define RG_TURISMO_TRX_5G_RX_MG_LNAHGP_BIAS_SZ 4
+#define RG_TURISMO_TRX_5G_RX_MG_LNALG_BIAS_MSK 0x0000f000
+#define RG_TURISMO_TRX_5G_RX_MG_LNALG_BIAS_I_MSK 0xffff0fff
+#define RG_TURISMO_TRX_5G_RX_MG_LNALG_BIAS_SFT 12
+#define RG_TURISMO_TRX_5G_RX_MG_LNALG_BIAS_HI 15
+#define RG_TURISMO_TRX_5G_RX_MG_LNALG_BIAS_SZ 4
+#define RG_TURISMO_TRX_5G_RX_MG_TZ_CAP_MSK 0x00070000
+#define RG_TURISMO_TRX_5G_RX_MG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_TURISMO_TRX_5G_RX_MG_TZ_CAP_SFT 16
+#define RG_TURISMO_TRX_5G_RX_MG_TZ_CAP_HI 18
+#define RG_TURISMO_TRX_5G_RX_MG_TZ_CAP_SZ 3
+#define RG_TURISMO_TRX_5G_RX_MG_SQDC_MSK 0x00380000
+#define RG_TURISMO_TRX_5G_RX_MG_SQDC_I_MSK 0xffc7ffff
+#define RG_TURISMO_TRX_5G_RX_MG_SQDC_SFT 19
+#define RG_TURISMO_TRX_5G_RX_MG_SQDC_HI 21
+#define RG_TURISMO_TRX_5G_RX_MG_SQDC_SZ 3
+#define RG_TURISMO_TRX_5G_RX_MG_DIV2_CORE_MSK 0x00c00000
+#define RG_TURISMO_TRX_5G_RX_MG_DIV2_CORE_I_MSK 0xff3fffff
+#define RG_TURISMO_TRX_5G_RX_MG_DIV2_CORE_SFT 22
+#define RG_TURISMO_TRX_5G_RX_MG_DIV2_CORE_HI 23
+#define RG_TURISMO_TRX_5G_RX_MG_DIV2_CORE_SZ 2
+#define RG_TURISMO_TRX_5G_RX_MG_TZ_GC_BOOST_MSK 0x03000000
+#define RG_TURISMO_TRX_5G_RX_MG_TZ_GC_BOOST_I_MSK 0xfcffffff
+#define RG_TURISMO_TRX_5G_RX_MG_TZ_GC_BOOST_SFT 24
+#define RG_TURISMO_TRX_5G_RX_MG_TZ_GC_BOOST_HI 25
+#define RG_TURISMO_TRX_5G_RX_MG_TZ_GC_BOOST_SZ 2
+#define RG_TURISMO_TRX_5G_RX_MG_TZI_MSK 0x1c000000
+#define RG_TURISMO_TRX_5G_RX_MG_TZI_I_MSK 0xe3ffffff
+#define RG_TURISMO_TRX_5G_RX_MG_TZI_SFT 26
+#define RG_TURISMO_TRX_5G_RX_MG_TZI_HI 28
+#define RG_TURISMO_TRX_5G_RX_MG_TZI_SZ 3
+#define RG_TURISMO_TRX_5G_RX_MG_TZ_VCM_MSK 0xe0000000
+#define RG_TURISMO_TRX_5G_RX_MG_TZ_VCM_I_MSK 0x1fffffff
+#define RG_TURISMO_TRX_5G_RX_MG_TZ_VCM_SFT 29
+#define RG_TURISMO_TRX_5G_RX_MG_TZ_VCM_HI 31
+#define RG_TURISMO_TRX_5G_RX_MG_TZ_VCM_SZ 3
+#define RG_TURISMO_TRX_5G_RX_LG_LNA_GC_MSK 0x00000003
+#define RG_TURISMO_TRX_5G_RX_LG_LNA_GC_I_MSK 0xfffffffc
+#define RG_TURISMO_TRX_5G_RX_LG_LNA_GC_SFT 0
+#define RG_TURISMO_TRX_5G_RX_LG_LNA_GC_HI 1
+#define RG_TURISMO_TRX_5G_RX_LG_LNA_GC_SZ 2
+#define RG_TURISMO_TRX_5G_RX_LG_TZ_GC_MSK 0x0000000c
+#define RG_TURISMO_TRX_5G_RX_LG_TZ_GC_I_MSK 0xfffffff3
+#define RG_TURISMO_TRX_5G_RX_LG_TZ_GC_SFT 2
+#define RG_TURISMO_TRX_5G_RX_LG_TZ_GC_HI 3
+#define RG_TURISMO_TRX_5G_RX_LG_TZ_GC_SZ 2
+#define RG_TURISMO_TRX_5G_RX_LG_LNAHGN_BIAS_MSK 0x000000f0
+#define RG_TURISMO_TRX_5G_RX_LG_LNAHGN_BIAS_I_MSK 0xffffff0f
+#define RG_TURISMO_TRX_5G_RX_LG_LNAHGN_BIAS_SFT 4
+#define RG_TURISMO_TRX_5G_RX_LG_LNAHGN_BIAS_HI 7
+#define RG_TURISMO_TRX_5G_RX_LG_LNAHGN_BIAS_SZ 4
+#define RG_TURISMO_TRX_5G_RX_LG_LNAHGP_BIAS_MSK 0x00000f00
+#define RG_TURISMO_TRX_5G_RX_LG_LNAHGP_BIAS_I_MSK 0xfffff0ff
+#define RG_TURISMO_TRX_5G_RX_LG_LNAHGP_BIAS_SFT 8
+#define RG_TURISMO_TRX_5G_RX_LG_LNAHGP_BIAS_HI 11
+#define RG_TURISMO_TRX_5G_RX_LG_LNAHGP_BIAS_SZ 4
+#define RG_TURISMO_TRX_5G_RX_LG_LNALG_BIAS_MSK 0x0000f000
+#define RG_TURISMO_TRX_5G_RX_LG_LNALG_BIAS_I_MSK 0xffff0fff
+#define RG_TURISMO_TRX_5G_RX_LG_LNALG_BIAS_SFT 12
+#define RG_TURISMO_TRX_5G_RX_LG_LNALG_BIAS_HI 15
+#define RG_TURISMO_TRX_5G_RX_LG_LNALG_BIAS_SZ 4
+#define RG_TURISMO_TRX_5G_RX_LG_TZ_CAP_MSK 0x00070000
+#define RG_TURISMO_TRX_5G_RX_LG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_TURISMO_TRX_5G_RX_LG_TZ_CAP_SFT 16
+#define RG_TURISMO_TRX_5G_RX_LG_TZ_CAP_HI 18
+#define RG_TURISMO_TRX_5G_RX_LG_TZ_CAP_SZ 3
+#define RG_TURISMO_TRX_5G_RX_LG_SQDC_MSK 0x00380000
+#define RG_TURISMO_TRX_5G_RX_LG_SQDC_I_MSK 0xffc7ffff
+#define RG_TURISMO_TRX_5G_RX_LG_SQDC_SFT 19
+#define RG_TURISMO_TRX_5G_RX_LG_SQDC_HI 21
+#define RG_TURISMO_TRX_5G_RX_LG_SQDC_SZ 3
+#define RG_TURISMO_TRX_5G_RX_LG_DIV2_CORE_MSK 0x00c00000
+#define RG_TURISMO_TRX_5G_RX_LG_DIV2_CORE_I_MSK 0xff3fffff
+#define RG_TURISMO_TRX_5G_RX_LG_DIV2_CORE_SFT 22
+#define RG_TURISMO_TRX_5G_RX_LG_DIV2_CORE_HI 23
+#define RG_TURISMO_TRX_5G_RX_LG_DIV2_CORE_SZ 2
+#define RG_TURISMO_TRX_5G_RX_LG_TZ_GC_BOOST_MSK 0x03000000
+#define RG_TURISMO_TRX_5G_RX_LG_TZ_GC_BOOST_I_MSK 0xfcffffff
+#define RG_TURISMO_TRX_5G_RX_LG_TZ_GC_BOOST_SFT 24
+#define RG_TURISMO_TRX_5G_RX_LG_TZ_GC_BOOST_HI 25
+#define RG_TURISMO_TRX_5G_RX_LG_TZ_GC_BOOST_SZ 2
+#define RG_TURISMO_TRX_5G_RX_LG_TZI_MSK 0x1c000000
+#define RG_TURISMO_TRX_5G_RX_LG_TZI_I_MSK 0xe3ffffff
+#define RG_TURISMO_TRX_5G_RX_LG_TZI_SFT 26
+#define RG_TURISMO_TRX_5G_RX_LG_TZI_HI 28
+#define RG_TURISMO_TRX_5G_RX_LG_TZI_SZ 3
+#define RG_TURISMO_TRX_5G_RX_LG_TZ_VCM_MSK 0xe0000000
+#define RG_TURISMO_TRX_5G_RX_LG_TZ_VCM_I_MSK 0x1fffffff
+#define RG_TURISMO_TRX_5G_RX_LG_TZ_VCM_SFT 29
+#define RG_TURISMO_TRX_5G_RX_LG_TZ_VCM_HI 31
+#define RG_TURISMO_TRX_5G_RX_LG_TZ_VCM_SZ 3
+#define RG_TURISMO_TRX_5G_RX_ULG_LNA_GC_MSK 0x00000003
+#define RG_TURISMO_TRX_5G_RX_ULG_LNA_GC_I_MSK 0xfffffffc
+#define RG_TURISMO_TRX_5G_RX_ULG_LNA_GC_SFT 0
+#define RG_TURISMO_TRX_5G_RX_ULG_LNA_GC_HI 1
+#define RG_TURISMO_TRX_5G_RX_ULG_LNA_GC_SZ 2
+#define RG_TURISMO_TRX_5G_RX_ULG_TZ_GC_MSK 0x0000000c
+#define RG_TURISMO_TRX_5G_RX_ULG_TZ_GC_I_MSK 0xfffffff3
+#define RG_TURISMO_TRX_5G_RX_ULG_TZ_GC_SFT 2
+#define RG_TURISMO_TRX_5G_RX_ULG_TZ_GC_HI 3
+#define RG_TURISMO_TRX_5G_RX_ULG_TZ_GC_SZ 2
+#define RG_TURISMO_TRX_5G_RX_ULG_LNAHGN_BIAS_MSK 0x000000f0
+#define RG_TURISMO_TRX_5G_RX_ULG_LNAHGN_BIAS_I_MSK 0xffffff0f
+#define RG_TURISMO_TRX_5G_RX_ULG_LNAHGN_BIAS_SFT 4
+#define RG_TURISMO_TRX_5G_RX_ULG_LNAHGN_BIAS_HI 7
+#define RG_TURISMO_TRX_5G_RX_ULG_LNAHGN_BIAS_SZ 4
+#define RG_TURISMO_TRX_5G_RX_ULG_LNAHGP_BIAS_MSK 0x00000f00
+#define RG_TURISMO_TRX_5G_RX_ULG_LNAHGP_BIAS_I_MSK 0xfffff0ff
+#define RG_TURISMO_TRX_5G_RX_ULG_LNAHGP_BIAS_SFT 8
+#define RG_TURISMO_TRX_5G_RX_ULG_LNAHGP_BIAS_HI 11
+#define RG_TURISMO_TRX_5G_RX_ULG_LNAHGP_BIAS_SZ 4
+#define RG_TURISMO_TRX_5G_RX_ULG_LNALG_BIAS_MSK 0x0000f000
+#define RG_TURISMO_TRX_5G_RX_ULG_LNALG_BIAS_I_MSK 0xffff0fff
+#define RG_TURISMO_TRX_5G_RX_ULG_LNALG_BIAS_SFT 12
+#define RG_TURISMO_TRX_5G_RX_ULG_LNALG_BIAS_HI 15
+#define RG_TURISMO_TRX_5G_RX_ULG_LNALG_BIAS_SZ 4
+#define RG_TURISMO_TRX_5G_RX_ULG_TZ_CAP_MSK 0x00070000
+#define RG_TURISMO_TRX_5G_RX_ULG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_TURISMO_TRX_5G_RX_ULG_TZ_CAP_SFT 16
+#define RG_TURISMO_TRX_5G_RX_ULG_TZ_CAP_HI 18
+#define RG_TURISMO_TRX_5G_RX_ULG_TZ_CAP_SZ 3
+#define RG_TURISMO_TRX_5G_RX_ULG_SQDC_MSK 0x00380000
+#define RG_TURISMO_TRX_5G_RX_ULG_SQDC_I_MSK 0xffc7ffff
+#define RG_TURISMO_TRX_5G_RX_ULG_SQDC_SFT 19
+#define RG_TURISMO_TRX_5G_RX_ULG_SQDC_HI 21
+#define RG_TURISMO_TRX_5G_RX_ULG_SQDC_SZ 3
+#define RG_TURISMO_TRX_5G_RX_ULG_DIV2_CORE_MSK 0x00c00000
+#define RG_TURISMO_TRX_5G_RX_ULG_DIV2_CORE_I_MSK 0xff3fffff
+#define RG_TURISMO_TRX_5G_RX_ULG_DIV2_CORE_SFT 22
+#define RG_TURISMO_TRX_5G_RX_ULG_DIV2_CORE_HI 23
+#define RG_TURISMO_TRX_5G_RX_ULG_DIV2_CORE_SZ 2
+#define RG_TURISMO_TRX_5G_RX_ULG_TZ_GC_BOOST_MSK 0x03000000
+#define RG_TURISMO_TRX_5G_RX_ULG_TZ_GC_BOOST_I_MSK 0xfcffffff
+#define RG_TURISMO_TRX_5G_RX_ULG_TZ_GC_BOOST_SFT 24
+#define RG_TURISMO_TRX_5G_RX_ULG_TZ_GC_BOOST_HI 25
+#define RG_TURISMO_TRX_5G_RX_ULG_TZ_GC_BOOST_SZ 2
+#define RG_TURISMO_TRX_5G_RX_ULG_TZI_MSK 0x1c000000
+#define RG_TURISMO_TRX_5G_RX_ULG_TZI_I_MSK 0xe3ffffff
+#define RG_TURISMO_TRX_5G_RX_ULG_TZI_SFT 26
+#define RG_TURISMO_TRX_5G_RX_ULG_TZI_HI 28
+#define RG_TURISMO_TRX_5G_RX_ULG_TZI_SZ 3
+#define RG_TURISMO_TRX_5G_RX_ULG_TZ_VCM_MSK 0xe0000000
+#define RG_TURISMO_TRX_5G_RX_ULG_TZ_VCM_I_MSK 0x1fffffff
+#define RG_TURISMO_TRX_5G_RX_ULG_TZ_VCM_SFT 29
+#define RG_TURISMO_TRX_5G_RX_ULG_TZ_VCM_HI 31
+#define RG_TURISMO_TRX_5G_RX_ULG_TZ_VCM_SZ 3
+#define RG_TURISMO_TRX_5G_TX_DACI1ST_MSK 0x00000003
+#define RG_TURISMO_TRX_5G_TX_DACI1ST_I_MSK 0xfffffffc
+#define RG_TURISMO_TRX_5G_TX_DACI1ST_SFT 0
+#define RG_TURISMO_TRX_5G_TX_DACI1ST_HI 1
+#define RG_TURISMO_TRX_5G_TX_DACI1ST_SZ 2
+#define RG_TURISMO_TRX_5G_TX_DACLPF_ICOARSE_MSK 0x0000000c
+#define RG_TURISMO_TRX_5G_TX_DACLPF_ICOARSE_I_MSK 0xfffffff3
+#define RG_TURISMO_TRX_5G_TX_DACLPF_ICOARSE_SFT 2
+#define RG_TURISMO_TRX_5G_TX_DACLPF_ICOARSE_HI 3
+#define RG_TURISMO_TRX_5G_TX_DACLPF_ICOARSE_SZ 2
+#define RG_TURISMO_TRX_5G_TX_DACLPF_IFINE_MSK 0x00000030
+#define RG_TURISMO_TRX_5G_TX_DACLPF_IFINE_I_MSK 0xffffffcf
+#define RG_TURISMO_TRX_5G_TX_DACLPF_IFINE_SFT 4
+#define RG_TURISMO_TRX_5G_TX_DACLPF_IFINE_HI 5
+#define RG_TURISMO_TRX_5G_TX_DACLPF_IFINE_SZ 2
+#define RG_TURISMO_TRX_5G_TX_DACLPF_VCM_MSK 0x000000c0
+#define RG_TURISMO_TRX_5G_TX_DACLPF_VCM_I_MSK 0xffffff3f
+#define RG_TURISMO_TRX_5G_TX_DACLPF_VCM_SFT 6
+#define RG_TURISMO_TRX_5G_TX_DACLPF_VCM_HI 7
+#define RG_TURISMO_TRX_5G_TX_DACLPF_VCM_SZ 2
+#define RG_TURISMO_TRX_5G_TX_DAC_IBIAS_MSK 0x00000300
+#define RG_TURISMO_TRX_5G_TX_DAC_IBIAS_I_MSK 0xfffffcff
+#define RG_TURISMO_TRX_5G_TX_DAC_IBIAS_SFT 8
+#define RG_TURISMO_TRX_5G_TX_DAC_IBIAS_HI 9
+#define RG_TURISMO_TRX_5G_TX_DAC_IBIAS_SZ 2
+#define RG_TURISMO_TRX_5G_TX_DAC_IATTN_MSK 0x00000400
+#define RG_TURISMO_TRX_5G_TX_DAC_IATTN_I_MSK 0xfffffbff
+#define RG_TURISMO_TRX_5G_TX_DAC_IATTN_SFT 10
+#define RG_TURISMO_TRX_5G_TX_DAC_IATTN_HI 10
+#define RG_TURISMO_TRX_5G_TX_DAC_IATTN_SZ 1
+#define RG_TURISMO_TRX_5G_TXLPF_BOOSTI_MSK 0x00000800
+#define RG_TURISMO_TRX_5G_TXLPF_BOOSTI_I_MSK 0xfffff7ff
+#define RG_TURISMO_TRX_5G_TXLPF_BOOSTI_SFT 11
+#define RG_TURISMO_TRX_5G_TXLPF_BOOSTI_HI 11
+#define RG_TURISMO_TRX_5G_TXLPF_BOOSTI_SZ 1
+#define RG_TURISMO_TRX_5G_TX_DAC_RCAL_MSK 0x00003000
+#define RG_TURISMO_TRX_5G_TX_DAC_RCAL_I_MSK 0xffffcfff
+#define RG_TURISMO_TRX_5G_TX_DAC_RCAL_SFT 12
+#define RG_TURISMO_TRX_5G_TX_DAC_RCAL_HI 13
+#define RG_TURISMO_TRX_5G_TX_DAC_RCAL_SZ 2
+#define RG_TURISMO_TRX_5G_TX_DAC_CKEDGE_SEL_MSK 0x00004000
+#define RG_TURISMO_TRX_5G_TX_DAC_CKEDGE_SEL_I_MSK 0xffffbfff
+#define RG_TURISMO_TRX_5G_TX_DAC_CKEDGE_SEL_SFT 14
+#define RG_TURISMO_TRX_5G_TX_DAC_CKEDGE_SEL_HI 14
+#define RG_TURISMO_TRX_5G_TX_DAC_CKEDGE_SEL_SZ 1
+#define RG_TURISMO_TRX_5G_TX_DAC_OS_MSK 0x00070000
+#define RG_TURISMO_TRX_5G_TX_DAC_OS_I_MSK 0xfff8ffff
+#define RG_TURISMO_TRX_5G_TX_DAC_OS_SFT 16
+#define RG_TURISMO_TRX_5G_TX_DAC_OS_HI 18
+#define RG_TURISMO_TRX_5G_TX_DAC_OS_SZ 3
+#define RG_TURISMO_TRX_5G_TX_DAC_IOFFSET_MSK 0x00f00000
+#define RG_TURISMO_TRX_5G_TX_DAC_IOFFSET_I_MSK 0xff0fffff
+#define RG_TURISMO_TRX_5G_TX_DAC_IOFFSET_SFT 20
+#define RG_TURISMO_TRX_5G_TX_DAC_IOFFSET_HI 23
+#define RG_TURISMO_TRX_5G_TX_DAC_IOFFSET_SZ 4
+#define RG_TURISMO_TRX_5G_TX_DAC_QOFFSET_MSK 0x0f000000
+#define RG_TURISMO_TRX_5G_TX_DAC_QOFFSET_I_MSK 0xf0ffffff
+#define RG_TURISMO_TRX_5G_TX_DAC_QOFFSET_SFT 24
+#define RG_TURISMO_TRX_5G_TX_DAC_QOFFSET_HI 27
+#define RG_TURISMO_TRX_5G_TX_DAC_QOFFSET_SZ 4
+#define RG_TURISMO_TRX_SX5GB_RFCTRL_F_MSK 0x00ffffff
+#define RG_TURISMO_TRX_SX5GB_RFCTRL_F_I_MSK 0xff000000
+#define RG_TURISMO_TRX_SX5GB_RFCTRL_F_SFT 0
+#define RG_TURISMO_TRX_SX5GB_RFCTRL_F_HI 23
+#define RG_TURISMO_TRX_SX5GB_RFCTRL_F_SZ 24
+#define RG_TURISMO_TRX_SX5GB_RFCTRL_CH_7_0_MSK 0xff000000
+#define RG_TURISMO_TRX_SX5GB_RFCTRL_CH_7_0_I_MSK 0x00ffffff
+#define RG_TURISMO_TRX_SX5GB_RFCTRL_CH_7_0_SFT 24
+#define RG_TURISMO_TRX_SX5GB_RFCTRL_CH_7_0_HI 31
+#define RG_TURISMO_TRX_SX5GB_RFCTRL_CH_7_0_SZ 8
+#define RG_TURISMO_TRX_SX5GB_RFCTRL_CH_10_8_MSK 0x00000007
+#define RG_TURISMO_TRX_SX5GB_RFCTRL_CH_10_8_I_MSK 0xfffffff8
+#define RG_TURISMO_TRX_SX5GB_RFCTRL_CH_10_8_SFT 0
+#define RG_TURISMO_TRX_SX5GB_RFCTRL_CH_10_8_HI 2
+#define RG_TURISMO_TRX_SX5GB_RFCTRL_CH_10_8_SZ 3
+#define RG_TURISMO_TRX_SX5GB_RFCH_MAP_EN_MSK 0x00000010
+#define RG_TURISMO_TRX_SX5GB_RFCH_MAP_EN_I_MSK 0xffffffef
+#define RG_TURISMO_TRX_SX5GB_RFCH_MAP_EN_SFT 4
+#define RG_TURISMO_TRX_SX5GB_RFCH_MAP_EN_HI 4
+#define RG_TURISMO_TRX_SX5GB_RFCH_MAP_EN_SZ 1
+#define RG_TURISMO_TRX_SX5GB_LO_TIMES_MSK 0x00000020
+#define RG_TURISMO_TRX_SX5GB_LO_TIMES_I_MSK 0xffffffdf
+#define RG_TURISMO_TRX_SX5GB_LO_TIMES_SFT 5
+#define RG_TURISMO_TRX_SX5GB_LO_TIMES_HI 5
+#define RG_TURISMO_TRX_SX5GB_LO_TIMES_SZ 1
+#define RG_TURISMO_TRX_SX5GB_CHANNEL_MSK 0x0000ff00
+#define RG_TURISMO_TRX_SX5GB_CHANNEL_I_MSK 0xffff00ff
+#define RG_TURISMO_TRX_SX5GB_CHANNEL_SFT 8
+#define RG_TURISMO_TRX_SX5GB_CHANNEL_HI 15
+#define RG_TURISMO_TRX_SX5GB_CHANNEL_SZ 8
+#define RG_TURISMO_TRX_SX_5GB_EN_MAN_MSK 0x00000001
+#define RG_TURISMO_TRX_SX_5GB_EN_MAN_I_MSK 0xfffffffe
+#define RG_TURISMO_TRX_SX_5GB_EN_MAN_SFT 0
+#define RG_TURISMO_TRX_SX_5GB_EN_MAN_HI 0
+#define RG_TURISMO_TRX_SX_5GB_EN_MAN_SZ 1
+#define RG_TURISMO_TRX_SX_5GB_EN_MSK 0x00000002
+#define RG_TURISMO_TRX_SX_5GB_EN_I_MSK 0xfffffffd
+#define RG_TURISMO_TRX_SX_5GB_EN_SFT 1
+#define RG_TURISMO_TRX_SX_5GB_EN_HI 1
+#define RG_TURISMO_TRX_SX_5GB_EN_SZ 1
+#define RG_TURISMO_TRX_EN_SX5GB_CP_MAN_MSK 0x00000004
+#define RG_TURISMO_TRX_EN_SX5GB_CP_MAN_I_MSK 0xfffffffb
+#define RG_TURISMO_TRX_EN_SX5GB_CP_MAN_SFT 2
+#define RG_TURISMO_TRX_EN_SX5GB_CP_MAN_HI 2
+#define RG_TURISMO_TRX_EN_SX5GB_CP_MAN_SZ 1
+#define RG_TURISMO_TRX_EN_SX5GB_CP_MSK 0x00000008
+#define RG_TURISMO_TRX_EN_SX5GB_CP_I_MSK 0xfffffff7
+#define RG_TURISMO_TRX_EN_SX5GB_CP_SFT 3
+#define RG_TURISMO_TRX_EN_SX5GB_CP_HI 3
+#define RG_TURISMO_TRX_EN_SX5GB_CP_SZ 1
+#define RG_TURISMO_TRX_EN_SX5GB_DIV_MAN_MSK 0x00000010
+#define RG_TURISMO_TRX_EN_SX5GB_DIV_MAN_I_MSK 0xffffffef
+#define RG_TURISMO_TRX_EN_SX5GB_DIV_MAN_SFT 4
+#define RG_TURISMO_TRX_EN_SX5GB_DIV_MAN_HI 4
+#define RG_TURISMO_TRX_EN_SX5GB_DIV_MAN_SZ 1
+#define RG_TURISMO_TRX_EN_SX5GB_DIV_MSK 0x00000020
+#define RG_TURISMO_TRX_EN_SX5GB_DIV_I_MSK 0xffffffdf
+#define RG_TURISMO_TRX_EN_SX5GB_DIV_SFT 5
+#define RG_TURISMO_TRX_EN_SX5GB_DIV_HI 5
+#define RG_TURISMO_TRX_EN_SX5GB_DIV_SZ 1
+#define RG_TURISMO_TRX_EN_SX5GB_VCO_MAN_MSK 0x00000040
+#define RG_TURISMO_TRX_EN_SX5GB_VCO_MAN_I_MSK 0xffffffbf
+#define RG_TURISMO_TRX_EN_SX5GB_VCO_MAN_SFT 6
+#define RG_TURISMO_TRX_EN_SX5GB_VCO_MAN_HI 6
+#define RG_TURISMO_TRX_EN_SX5GB_VCO_MAN_SZ 1
+#define RG_TURISMO_TRX_EN_SX5GB_VCO_MSK 0x00000080
+#define RG_TURISMO_TRX_EN_SX5GB_VCO_I_MSK 0xffffff7f
+#define RG_TURISMO_TRX_EN_SX5GB_VCO_SFT 7
+#define RG_TURISMO_TRX_EN_SX5GB_VCO_HI 7
+#define RG_TURISMO_TRX_EN_SX5GB_VCO_SZ 1
+#define RG_TURISMO_TRX_SX5GB_PFD_RST_MAN_MSK 0x00000100
+#define RG_TURISMO_TRX_SX5GB_PFD_RST_MAN_I_MSK 0xfffffeff
+#define RG_TURISMO_TRX_SX5GB_PFD_RST_MAN_SFT 8
+#define RG_TURISMO_TRX_SX5GB_PFD_RST_MAN_HI 8
+#define RG_TURISMO_TRX_SX5GB_PFD_RST_MAN_SZ 1
+#define RG_TURISMO_TRX_SX5GB_PFD_RST_MSK 0x00000200
+#define RG_TURISMO_TRX_SX5GB_PFD_RST_I_MSK 0xfffffdff
+#define RG_TURISMO_TRX_SX5GB_PFD_RST_SFT 9
+#define RG_TURISMO_TRX_SX5GB_PFD_RST_HI 9
+#define RG_TURISMO_TRX_SX5GB_PFD_RST_SZ 1
+#define RG_TURISMO_TRX_SX5GB_UOP_MAN_MSK 0x00000400
+#define RG_TURISMO_TRX_SX5GB_UOP_MAN_I_MSK 0xfffffbff
+#define RG_TURISMO_TRX_SX5GB_UOP_MAN_SFT 10
+#define RG_TURISMO_TRX_SX5GB_UOP_MAN_HI 10
+#define RG_TURISMO_TRX_SX5GB_UOP_MAN_SZ 1
+#define RG_TURISMO_TRX_SX5GB_UOP_EN_MSK 0x00000800
+#define RG_TURISMO_TRX_SX5GB_UOP_EN_I_MSK 0xfffff7ff
+#define RG_TURISMO_TRX_SX5GB_UOP_EN_SFT 11
+#define RG_TURISMO_TRX_SX5GB_UOP_EN_HI 11
+#define RG_TURISMO_TRX_SX5GB_UOP_EN_SZ 1
+#define RG_TURISMO_TRX_EN_SX5GB_HSDIV_MAN_MSK 0x00001000
+#define RG_TURISMO_TRX_EN_SX5GB_HSDIV_MAN_I_MSK 0xffffefff
+#define RG_TURISMO_TRX_EN_SX5GB_HSDIV_MAN_SFT 12
+#define RG_TURISMO_TRX_EN_SX5GB_HSDIV_MAN_HI 12
+#define RG_TURISMO_TRX_EN_SX5GB_HSDIV_MAN_SZ 1
+#define RG_TURISMO_TRX_EN_SX5GB_HSDIV_MSK 0x00002000
+#define RG_TURISMO_TRX_EN_SX5GB_HSDIV_I_MSK 0xffffdfff
+#define RG_TURISMO_TRX_EN_SX5GB_HSDIV_SFT 13
+#define RG_TURISMO_TRX_EN_SX5GB_HSDIV_HI 13
+#define RG_TURISMO_TRX_EN_SX5GB_HSDIV_SZ 1
+#define RG_TURISMO_TRX_EN_HSDIV_OBF_SX_MAN_MSK 0x00004000
+#define RG_TURISMO_TRX_EN_HSDIV_OBF_SX_MAN_I_MSK 0xffffbfff
+#define RG_TURISMO_TRX_EN_HSDIV_OBF_SX_MAN_SFT 14
+#define RG_TURISMO_TRX_EN_HSDIV_OBF_SX_MAN_HI 14
+#define RG_TURISMO_TRX_EN_HSDIV_OBF_SX_MAN_SZ 1
+#define RG_TURISMO_TRX_EN_HSDIV_OBF_SX_MSK 0x00008000
+#define RG_TURISMO_TRX_EN_HSDIV_OBF_SX_I_MSK 0xffff7fff
+#define RG_TURISMO_TRX_EN_HSDIV_OBF_SX_SFT 15
+#define RG_TURISMO_TRX_EN_HSDIV_OBF_SX_HI 15
+#define RG_TURISMO_TRX_EN_HSDIV_OBF_SX_SZ 1
+#define RG_TURISMO_TRX_EN_HSDIV_OBF_MX_MAN_MSK 0x00010000
+#define RG_TURISMO_TRX_EN_HSDIV_OBF_MX_MAN_I_MSK 0xfffeffff
+#define RG_TURISMO_TRX_EN_HSDIV_OBF_MX_MAN_SFT 16
+#define RG_TURISMO_TRX_EN_HSDIV_OBF_MX_MAN_HI 16
+#define RG_TURISMO_TRX_EN_HSDIV_OBF_MX_MAN_SZ 1
+#define RG_TURISMO_TRX_EN_HSDIV_OBF_MX_MSK 0x00020000
+#define RG_TURISMO_TRX_EN_HSDIV_OBF_MX_I_MSK 0xfffdffff
+#define RG_TURISMO_TRX_EN_HSDIV_OBF_MX_SFT 17
+#define RG_TURISMO_TRX_EN_HSDIV_OBF_MX_HI 17
+#define RG_TURISMO_TRX_EN_HSDIV_OBF_MX_SZ 1
+#define RG_TURISMO_TRX_EN_SX_MIX_MAN_MSK 0x00040000
+#define RG_TURISMO_TRX_EN_SX_MIX_MAN_I_MSK 0xfffbffff
+#define RG_TURISMO_TRX_EN_SX_MIX_MAN_SFT 18
+#define RG_TURISMO_TRX_EN_SX_MIX_MAN_HI 18
+#define RG_TURISMO_TRX_EN_SX_MIX_MAN_SZ 1
+#define RG_TURISMO_TRX_EN_SX_MIX_MSK 0x00080000
+#define RG_TURISMO_TRX_EN_SX_MIX_I_MSK 0xfff7ffff
+#define RG_TURISMO_TRX_EN_SX_MIX_SFT 19
+#define RG_TURISMO_TRX_EN_SX_MIX_HI 19
+#define RG_TURISMO_TRX_EN_SX_MIX_SZ 1
+#define RG_TURISMO_TRX_EN_SX_REP_MAN_MSK 0x00100000
+#define RG_TURISMO_TRX_EN_SX_REP_MAN_I_MSK 0xffefffff
+#define RG_TURISMO_TRX_EN_SX_REP_MAN_SFT 20
+#define RG_TURISMO_TRX_EN_SX_REP_MAN_HI 20
+#define RG_TURISMO_TRX_EN_SX_REP_MAN_SZ 1
+#define RG_TURISMO_TRX_EN_SX_REP_MSK 0x00200000
+#define RG_TURISMO_TRX_EN_SX_REP_I_MSK 0xffdfffff
+#define RG_TURISMO_TRX_EN_SX_REP_SFT 21
+#define RG_TURISMO_TRX_EN_SX_REP_HI 21
+#define RG_TURISMO_TRX_EN_SX_REP_SZ 1
+#define RG_TURISMO_TRX_SX5GB_SBCAL_DIS_MSK 0x00400000
+#define RG_TURISMO_TRX_SX5GB_SBCAL_DIS_I_MSK 0xffbfffff
+#define RG_TURISMO_TRX_SX5GB_SBCAL_DIS_SFT 22
+#define RG_TURISMO_TRX_SX5GB_SBCAL_DIS_HI 22
+#define RG_TURISMO_TRX_SX5GB_SBCAL_DIS_SZ 1
+#define RG_TURISMO_TRX_SX5GB_SBCAL_2ND_DIS_MSK 0x00800000
+#define RG_TURISMO_TRX_SX5GB_SBCAL_2ND_DIS_I_MSK 0xff7fffff
+#define RG_TURISMO_TRX_SX5GB_SBCAL_2ND_DIS_SFT 23
+#define RG_TURISMO_TRX_SX5GB_SBCAL_2ND_DIS_HI 23
+#define RG_TURISMO_TRX_SX5GB_SBCAL_2ND_DIS_SZ 1
+#define RG_TURISMO_TRX_SX5GB_SBCAL_AW_MSK 0x01000000
+#define RG_TURISMO_TRX_SX5GB_SBCAL_AW_I_MSK 0xfeffffff
+#define RG_TURISMO_TRX_SX5GB_SBCAL_AW_SFT 24
+#define RG_TURISMO_TRX_SX5GB_SBCAL_AW_HI 24
+#define RG_TURISMO_TRX_SX5GB_SBCAL_AW_SZ 1
+#define RG_TURISMO_TRX_SX5GB_VOAAC_DIS_MSK 0x02000000
+#define RG_TURISMO_TRX_SX5GB_VOAAC_DIS_I_MSK 0xfdffffff
+#define RG_TURISMO_TRX_SX5GB_VOAAC_DIS_SFT 25
+#define RG_TURISMO_TRX_SX5GB_VOAAC_DIS_HI 25
+#define RG_TURISMO_TRX_SX5GB_VOAAC_DIS_SZ 1
+#define RG_TURISMO_TRX_SX5GB_MIXAAC_DIS_MSK 0x04000000
+#define RG_TURISMO_TRX_SX5GB_MIXAAC_DIS_I_MSK 0xfbffffff
+#define RG_TURISMO_TRX_SX5GB_MIXAAC_DIS_SFT 26
+#define RG_TURISMO_TRX_SX5GB_MIXAAC_DIS_HI 26
+#define RG_TURISMO_TRX_SX5GB_MIXAAC_DIS_SZ 1
+#define RG_TURISMO_TRX_SX5GB_REPAAC_DIS_MSK 0x08000000
+#define RG_TURISMO_TRX_SX5GB_REPAAC_DIS_I_MSK 0xf7ffffff
+#define RG_TURISMO_TRX_SX5GB_REPAAC_DIS_SFT 27
+#define RG_TURISMO_TRX_SX5GB_REPAAC_DIS_HI 27
+#define RG_TURISMO_TRX_SX5GB_REPAAC_DIS_SZ 1
+#define RG_TURISMO_TRX_SX5GB_TTL_DIS_MSK 0x10000000
+#define RG_TURISMO_TRX_SX5GB_TTL_DIS_I_MSK 0xefffffff
+#define RG_TURISMO_TRX_SX5GB_TTL_DIS_SFT 28
+#define RG_TURISMO_TRX_SX5GB_TTL_DIS_HI 28
+#define RG_TURISMO_TRX_SX5GB_TTL_DIS_SZ 1
+#define RG_TURISMO_TRX_SX5GB_CAL_INIT_MSK 0xe0000000
+#define RG_TURISMO_TRX_SX5GB_CAL_INIT_I_MSK 0x1fffffff
+#define RG_TURISMO_TRX_SX5GB_CAL_INIT_SFT 29
+#define RG_TURISMO_TRX_SX5GB_CAL_INIT_HI 31
+#define RG_TURISMO_TRX_SX5GB_CAL_INIT_SZ 3
+#define RG_TURISMO_TRX_EN_SX5GB_LDO_MAN_MSK 0x00000001
+#define RG_TURISMO_TRX_EN_SX5GB_LDO_MAN_I_MSK 0xfffffffe
+#define RG_TURISMO_TRX_EN_SX5GB_LDO_MAN_SFT 0
+#define RG_TURISMO_TRX_EN_SX5GB_LDO_MAN_HI 0
+#define RG_TURISMO_TRX_EN_SX5GB_LDO_MAN_SZ 1
+#define RG_TURISMO_TRX_EN_LDO_5G_CP_MSK 0x00000002
+#define RG_TURISMO_TRX_EN_LDO_5G_CP_I_MSK 0xfffffffd
+#define RG_TURISMO_TRX_EN_LDO_5G_CP_SFT 1
+#define RG_TURISMO_TRX_EN_LDO_5G_CP_HI 1
+#define RG_TURISMO_TRX_EN_LDO_5G_CP_SZ 1
+#define RG_TURISMO_TRX_EN_LDO_5G_DIV_MSK 0x00000004
+#define RG_TURISMO_TRX_EN_LDO_5G_DIV_I_MSK 0xfffffffb
+#define RG_TURISMO_TRX_EN_LDO_5G_DIV_SFT 2
+#define RG_TURISMO_TRX_EN_LDO_5G_DIV_HI 2
+#define RG_TURISMO_TRX_EN_LDO_5G_DIV_SZ 1
+#define RG_TURISMO_TRX_EN_LDO_5G_LO_MSK 0x00000008
+#define RG_TURISMO_TRX_EN_LDO_5G_LO_I_MSK 0xfffffff7
+#define RG_TURISMO_TRX_EN_LDO_5G_LO_SFT 3
+#define RG_TURISMO_TRX_EN_LDO_5G_LO_HI 3
+#define RG_TURISMO_TRX_EN_LDO_5G_LO_SZ 1
+#define RG_TURISMO_TRX_EN_LDO_5G_VCO_MSK 0x00000010
+#define RG_TURISMO_TRX_EN_LDO_5G_VCO_I_MSK 0xffffffef
+#define RG_TURISMO_TRX_EN_LDO_5G_VCO_SFT 4
+#define RG_TURISMO_TRX_EN_LDO_5G_VCO_HI 4
+#define RG_TURISMO_TRX_EN_LDO_5G_VCO_SZ 1
+#define RG_TURISMO_TRX_EN_LDO_5G_VCO_PSW_MSK 0x00000200
+#define RG_TURISMO_TRX_EN_LDO_5G_VCO_PSW_I_MSK 0xfffffdff
+#define RG_TURISMO_TRX_EN_LDO_5G_VCO_PSW_SFT 9
+#define RG_TURISMO_TRX_EN_LDO_5G_VCO_PSW_HI 9
+#define RG_TURISMO_TRX_EN_LDO_5G_VCO_PSW_SZ 1
+#define RG_TURISMO_TRX_EN_LDO_5G_VCO_VDD33_MSK 0x00000400
+#define RG_TURISMO_TRX_EN_LDO_5G_VCO_VDD33_I_MSK 0xfffffbff
+#define RG_TURISMO_TRX_EN_LDO_5G_VCO_VDD33_SFT 10
+#define RG_TURISMO_TRX_EN_LDO_5G_VCO_VDD33_HI 10
+#define RG_TURISMO_TRX_EN_LDO_5G_VCO_VDD33_SZ 1
+#define RG_TURISMO_TRX_EN_LDO_5G_CP_IQUP_MSK 0x00000800
+#define RG_TURISMO_TRX_EN_LDO_5G_CP_IQUP_I_MSK 0xfffff7ff
+#define RG_TURISMO_TRX_EN_LDO_5G_CP_IQUP_SFT 11
+#define RG_TURISMO_TRX_EN_LDO_5G_CP_IQUP_HI 11
+#define RG_TURISMO_TRX_EN_LDO_5G_CP_IQUP_SZ 1
+#define RG_TURISMO_TRX_EN_LDO_5G_DIV_IQUP_MSK 0x00001000
+#define RG_TURISMO_TRX_EN_LDO_5G_DIV_IQUP_I_MSK 0xffffefff
+#define RG_TURISMO_TRX_EN_LDO_5G_DIV_IQUP_SFT 12
+#define RG_TURISMO_TRX_EN_LDO_5G_DIV_IQUP_HI 12
+#define RG_TURISMO_TRX_EN_LDO_5G_DIV_IQUP_SZ 1
+#define RG_TURISMO_TRX_EN_LDO_5G_LO_IQUP_MSK 0x00002000
+#define RG_TURISMO_TRX_EN_LDO_5G_LO_IQUP_I_MSK 0xffffdfff
+#define RG_TURISMO_TRX_EN_LDO_5G_LO_IQUP_SFT 13
+#define RG_TURISMO_TRX_EN_LDO_5G_LO_IQUP_HI 13
+#define RG_TURISMO_TRX_EN_LDO_5G_LO_IQUP_SZ 1
+#define RG_TURISMO_TRX_EN_LDO_5G_VCO_IQUP_MSK 0x00004000
+#define RG_TURISMO_TRX_EN_LDO_5G_VCO_IQUP_I_MSK 0xffffbfff
+#define RG_TURISMO_TRX_EN_LDO_5G_VCO_IQUP_SFT 14
+#define RG_TURISMO_TRX_EN_LDO_5G_VCO_IQUP_HI 14
+#define RG_TURISMO_TRX_EN_LDO_5G_VCO_IQUP_SZ 1
+#define RG_TURISMO_TRX_SX5GB_LDO_FCOFFT_MSK 0x00380000
+#define RG_TURISMO_TRX_SX5GB_LDO_FCOFFT_I_MSK 0xffc7ffff
+#define RG_TURISMO_TRX_SX5GB_LDO_FCOFFT_SFT 19
+#define RG_TURISMO_TRX_SX5GB_LDO_FCOFFT_HI 21
+#define RG_TURISMO_TRX_SX5GB_LDO_FCOFFT_SZ 3
+#define RG_TURISMO_TRX_LDO_5G_CP_FC_MAN_MSK 0x00400000
+#define RG_TURISMO_TRX_LDO_5G_CP_FC_MAN_I_MSK 0xffbfffff
+#define RG_TURISMO_TRX_LDO_5G_CP_FC_MAN_SFT 22
+#define RG_TURISMO_TRX_LDO_5G_CP_FC_MAN_HI 22
+#define RG_TURISMO_TRX_LDO_5G_CP_FC_MAN_SZ 1
+#define RG_TURISMO_TRX_LDO_5G_CP_FC_MSK 0x00800000
+#define RG_TURISMO_TRX_LDO_5G_CP_FC_I_MSK 0xff7fffff
+#define RG_TURISMO_TRX_LDO_5G_CP_FC_SFT 23
+#define RG_TURISMO_TRX_LDO_5G_CP_FC_HI 23
+#define RG_TURISMO_TRX_LDO_5G_CP_FC_SZ 1
+#define RG_TURISMO_TRX_LDO_5G_DIV_FC_MAN_MSK 0x01000000
+#define RG_TURISMO_TRX_LDO_5G_DIV_FC_MAN_I_MSK 0xfeffffff
+#define RG_TURISMO_TRX_LDO_5G_DIV_FC_MAN_SFT 24
+#define RG_TURISMO_TRX_LDO_5G_DIV_FC_MAN_HI 24
+#define RG_TURISMO_TRX_LDO_5G_DIV_FC_MAN_SZ 1
+#define RG_TURISMO_TRX_LDO_5G_DIV_FC_MSK 0x02000000
+#define RG_TURISMO_TRX_LDO_5G_DIV_FC_I_MSK 0xfdffffff
+#define RG_TURISMO_TRX_LDO_5G_DIV_FC_SFT 25
+#define RG_TURISMO_TRX_LDO_5G_DIV_FC_HI 25
+#define RG_TURISMO_TRX_LDO_5G_DIV_FC_SZ 1
+#define RG_TURISMO_TRX_LDO_5G_LO_FC_MAN_MSK 0x04000000
+#define RG_TURISMO_TRX_LDO_5G_LO_FC_MAN_I_MSK 0xfbffffff
+#define RG_TURISMO_TRX_LDO_5G_LO_FC_MAN_SFT 26
+#define RG_TURISMO_TRX_LDO_5G_LO_FC_MAN_HI 26
+#define RG_TURISMO_TRX_LDO_5G_LO_FC_MAN_SZ 1
+#define RG_TURISMO_TRX_LDO_5G_LO_FC_MSK 0x08000000
+#define RG_TURISMO_TRX_LDO_5G_LO_FC_I_MSK 0xf7ffffff
+#define RG_TURISMO_TRX_LDO_5G_LO_FC_SFT 27
+#define RG_TURISMO_TRX_LDO_5G_LO_FC_HI 27
+#define RG_TURISMO_TRX_LDO_5G_LO_FC_SZ 1
+#define RG_TURISMO_TRX_LDO_5G_VCO_FC_MAN_MSK 0x10000000
+#define RG_TURISMO_TRX_LDO_5G_VCO_FC_MAN_I_MSK 0xefffffff
+#define RG_TURISMO_TRX_LDO_5G_VCO_FC_MAN_SFT 28
+#define RG_TURISMO_TRX_LDO_5G_VCO_FC_MAN_HI 28
+#define RG_TURISMO_TRX_LDO_5G_VCO_FC_MAN_SZ 1
+#define RG_TURISMO_TRX_LDO_5G_VCO_FC_MSK 0x20000000
+#define RG_TURISMO_TRX_LDO_5G_VCO_FC_I_MSK 0xdfffffff
+#define RG_TURISMO_TRX_LDO_5G_VCO_FC_SFT 29
+#define RG_TURISMO_TRX_LDO_5G_VCO_FC_HI 29
+#define RG_TURISMO_TRX_LDO_5G_VCO_FC_SZ 1
+#define RG_TURISMO_TRX_LDO_5G_VCO_RCF_MSK 0xc0000000
+#define RG_TURISMO_TRX_LDO_5G_VCO_RCF_I_MSK 0x3fffffff
+#define RG_TURISMO_TRX_LDO_5G_VCO_RCF_SFT 30
+#define RG_TURISMO_TRX_LDO_5G_VCO_RCF_HI 31
+#define RG_TURISMO_TRX_LDO_5G_VCO_RCF_SZ 2
+#define RG_TURISMO_TRX_SX5GB_CP_ISEL_MSK 0x0000000f
+#define RG_TURISMO_TRX_SX5GB_CP_ISEL_I_MSK 0xfffffff0
+#define RG_TURISMO_TRX_SX5GB_CP_ISEL_SFT 0
+#define RG_TURISMO_TRX_SX5GB_CP_ISEL_HI 3
+#define RG_TURISMO_TRX_SX5GB_CP_ISEL_SZ 4
+#define RG_TURISMO_TRX_SX5GB_CP_ISEL50U_MSK 0x00000010
+#define RG_TURISMO_TRX_SX5GB_CP_ISEL50U_I_MSK 0xffffffef
+#define RG_TURISMO_TRX_SX5GB_CP_ISEL50U_SFT 4
+#define RG_TURISMO_TRX_SX5GB_CP_ISEL50U_HI 4
+#define RG_TURISMO_TRX_SX5GB_CP_ISEL50U_SZ 1
+#define RG_TURISMO_TRX_SX5GB_CP_KP_DOUB_MSK 0x00000020
+#define RG_TURISMO_TRX_SX5GB_CP_KP_DOUB_I_MSK 0xffffffdf
+#define RG_TURISMO_TRX_SX5GB_CP_KP_DOUB_SFT 5
+#define RG_TURISMO_TRX_SX5GB_CP_KP_DOUB_HI 5
+#define RG_TURISMO_TRX_SX5GB_CP_KP_DOUB_SZ 1
+#define RG_TURISMO_TRX_SX5GB_CP_IOST_POL_MSK 0x00000080
+#define RG_TURISMO_TRX_SX5GB_CP_IOST_POL_I_MSK 0xffffff7f
+#define RG_TURISMO_TRX_SX5GB_CP_IOST_POL_SFT 7
+#define RG_TURISMO_TRX_SX5GB_CP_IOST_POL_HI 7
+#define RG_TURISMO_TRX_SX5GB_CP_IOST_POL_SZ 1
+#define RG_TURISMO_TRX_SX5GB_CP_IOST_MSK 0x00000700
+#define RG_TURISMO_TRX_SX5GB_CP_IOST_I_MSK 0xfffff8ff
+#define RG_TURISMO_TRX_SX5GB_CP_IOST_SFT 8
+#define RG_TURISMO_TRX_SX5GB_CP_IOST_HI 10
+#define RG_TURISMO_TRX_SX5GB_CP_IOST_SZ 3
+#define RG_TURISMO_TRX_SX5GB_PFD_SEL_MSK 0x00001000
+#define RG_TURISMO_TRX_SX5GB_PFD_SEL_I_MSK 0xffffefff
+#define RG_TURISMO_TRX_SX5GB_PFD_SEL_SFT 12
+#define RG_TURISMO_TRX_SX5GB_PFD_SEL_HI 12
+#define RG_TURISMO_TRX_SX5GB_PFD_SEL_SZ 1
+#define RG_TURISMO_TRX_SX5GB_PFD_SET_MSK 0x00002000
+#define RG_TURISMO_TRX_SX5GB_PFD_SET_I_MSK 0xffffdfff
+#define RG_TURISMO_TRX_SX5GB_PFD_SET_SFT 13
+#define RG_TURISMO_TRX_SX5GB_PFD_SET_HI 13
+#define RG_TURISMO_TRX_SX5GB_PFD_SET_SZ 1
+#define RG_TURISMO_TRX_SX5GB_PFD_SET1_MSK 0x00004000
+#define RG_TURISMO_TRX_SX5GB_PFD_SET1_I_MSK 0xffffbfff
+#define RG_TURISMO_TRX_SX5GB_PFD_SET1_SFT 14
+#define RG_TURISMO_TRX_SX5GB_PFD_SET1_HI 14
+#define RG_TURISMO_TRX_SX5GB_PFD_SET1_SZ 1
+#define RG_TURISMO_TRX_SX5GB_PFD_SET2_MSK 0x00008000
+#define RG_TURISMO_TRX_SX5GB_PFD_SET2_I_MSK 0xffff7fff
+#define RG_TURISMO_TRX_SX5GB_PFD_SET2_SFT 15
+#define RG_TURISMO_TRX_SX5GB_PFD_SET2_HI 15
+#define RG_TURISMO_TRX_SX5GB_PFD_SET2_SZ 1
+#define RG_TURISMO_TRX_SX5GB_PFD_TRUP_MSK 0x00010000
+#define RG_TURISMO_TRX_SX5GB_PFD_TRUP_I_MSK 0xfffeffff
+#define RG_TURISMO_TRX_SX5GB_PFD_TRUP_SFT 16
+#define RG_TURISMO_TRX_SX5GB_PFD_TRUP_HI 16
+#define RG_TURISMO_TRX_SX5GB_PFD_TRUP_SZ 1
+#define RG_TURISMO_TRX_SX5GB_PFD_TRDN_MSK 0x00020000
+#define RG_TURISMO_TRX_SX5GB_PFD_TRDN_I_MSK 0xfffdffff
+#define RG_TURISMO_TRX_SX5GB_PFD_TRDN_SFT 17
+#define RG_TURISMO_TRX_SX5GB_PFD_TRDN_HI 17
+#define RG_TURISMO_TRX_SX5GB_PFD_TRDN_SZ 1
+#define RG_TURISMO_TRX_SX5GB_PFD_TLSEL_MSK 0x00040000
+#define RG_TURISMO_TRX_SX5GB_PFD_TLSEL_I_MSK 0xfffbffff
+#define RG_TURISMO_TRX_SX5GB_PFD_TLSEL_SFT 18
+#define RG_TURISMO_TRX_SX5GB_PFD_TLSEL_HI 18
+#define RG_TURISMO_TRX_SX5GB_PFD_TLSEL_SZ 1
+#define RG_TURISMO_TRX_SX5GB_PFD_REF_EDGE_MSK 0x00080000
+#define RG_TURISMO_TRX_SX5GB_PFD_REF_EDGE_I_MSK 0xfff7ffff
+#define RG_TURISMO_TRX_SX5GB_PFD_REF_EDGE_SFT 19
+#define RG_TURISMO_TRX_SX5GB_PFD_REF_EDGE_HI 19
+#define RG_TURISMO_TRX_SX5GB_PFD_REF_EDGE_SZ 1
+#define RG_TURISMO_TRX_SX5GB_PFD_DIV_EDGE_MSK 0x00100000
+#define RG_TURISMO_TRX_SX5GB_PFD_DIV_EDGE_I_MSK 0xffefffff
+#define RG_TURISMO_TRX_SX5GB_PFD_DIV_EDGE_SFT 20
+#define RG_TURISMO_TRX_SX5GB_PFD_DIV_EDGE_HI 20
+#define RG_TURISMO_TRX_SX5GB_PFD_DIV_EDGE_SZ 1
+#define RG_TURISMO_TRX_SX5GB_LPF_C1_MSK 0x0000000f
+#define RG_TURISMO_TRX_SX5GB_LPF_C1_I_MSK 0xfffffff0
+#define RG_TURISMO_TRX_SX5GB_LPF_C1_SFT 0
+#define RG_TURISMO_TRX_SX5GB_LPF_C1_HI 3
+#define RG_TURISMO_TRX_SX5GB_LPF_C1_SZ 4
+#define RG_TURISMO_TRX_SX5GB_LPF_C2_MSK 0x000000f0
+#define RG_TURISMO_TRX_SX5GB_LPF_C2_I_MSK 0xffffff0f
+#define RG_TURISMO_TRX_SX5GB_LPF_C2_SFT 4
+#define RG_TURISMO_TRX_SX5GB_LPF_C2_HI 7
+#define RG_TURISMO_TRX_SX5GB_LPF_C2_SZ 4
+#define RG_TURISMO_TRX_SX5GB_LPF_C3_MSK 0x00000100
+#define RG_TURISMO_TRX_SX5GB_LPF_C3_I_MSK 0xfffffeff
+#define RG_TURISMO_TRX_SX5GB_LPF_C3_SFT 8
+#define RG_TURISMO_TRX_SX5GB_LPF_C3_HI 8
+#define RG_TURISMO_TRX_SX5GB_LPF_C3_SZ 1
+#define RG_TURISMO_TRX_SX5GB_LPF_R2_MSK 0x00001e00
+#define RG_TURISMO_TRX_SX5GB_LPF_R2_I_MSK 0xffffe1ff
+#define RG_TURISMO_TRX_SX5GB_LPF_R2_SFT 9
+#define RG_TURISMO_TRX_SX5GB_LPF_R2_HI 12
+#define RG_TURISMO_TRX_SX5GB_LPF_R2_SZ 4
+#define RG_TURISMO_TRX_SX5GB_LPF_R3_MSK 0x0000e000
+#define RG_TURISMO_TRX_SX5GB_LPF_R3_I_MSK 0xffff1fff
+#define RG_TURISMO_TRX_SX5GB_LPF_R3_SFT 13
+#define RG_TURISMO_TRX_SX5GB_LPF_R3_HI 15
+#define RG_TURISMO_TRX_SX5GB_LPF_R3_SZ 3
+#define RG_TURISMO_TRX_SX5GB_TTL_INIT_MSK 0x00030000
+#define RG_TURISMO_TRX_SX5GB_TTL_INIT_I_MSK 0xfffcffff
+#define RG_TURISMO_TRX_SX5GB_TTL_INIT_SFT 16
+#define RG_TURISMO_TRX_SX5GB_TTL_INIT_HI 17
+#define RG_TURISMO_TRX_SX5GB_TTL_INIT_SZ 2
+#define RG_TURISMO_TRX_SX5GB_TTL_FPT_MSK 0x000c0000
+#define RG_TURISMO_TRX_SX5GB_TTL_FPT_I_MSK 0xfff3ffff
+#define RG_TURISMO_TRX_SX5GB_TTL_FPT_SFT 18
+#define RG_TURISMO_TRX_SX5GB_TTL_FPT_HI 19
+#define RG_TURISMO_TRX_SX5GB_TTL_FPT_SZ 2
+#define RG_TURISMO_TRX_SX5GB_TTL_CPT_MSK 0x00300000
+#define RG_TURISMO_TRX_SX5GB_TTL_CPT_I_MSK 0xffcfffff
+#define RG_TURISMO_TRX_SX5GB_TTL_CPT_SFT 20
+#define RG_TURISMO_TRX_SX5GB_TTL_CPT_HI 21
+#define RG_TURISMO_TRX_SX5GB_TTL_CPT_SZ 2
+#define RG_TURISMO_TRX_SX5GB_TTL_ACCUM_MSK 0x00c00000
+#define RG_TURISMO_TRX_SX5GB_TTL_ACCUM_I_MSK 0xff3fffff
+#define RG_TURISMO_TRX_SX5GB_TTL_ACCUM_SFT 22
+#define RG_TURISMO_TRX_SX5GB_TTL_ACCUM_HI 23
+#define RG_TURISMO_TRX_SX5GB_TTL_ACCUM_SZ 2
+#define RG_TURISMO_TRX_SX5GB_TTL_SUB_MSK 0x03000000
+#define RG_TURISMO_TRX_SX5GB_TTL_SUB_I_MSK 0xfcffffff
+#define RG_TURISMO_TRX_SX5GB_TTL_SUB_SFT 24
+#define RG_TURISMO_TRX_SX5GB_TTL_SUB_HI 25
+#define RG_TURISMO_TRX_SX5GB_TTL_SUB_SZ 2
+#define RG_TURISMO_TRX_SX5GB_TTL_SUB_INV_MSK 0x04000000
+#define RG_TURISMO_TRX_SX5GB_TTL_SUB_INV_I_MSK 0xfbffffff
+#define RG_TURISMO_TRX_SX5GB_TTL_SUB_INV_SFT 26
+#define RG_TURISMO_TRX_SX5GB_TTL_SUB_INV_HI 26
+#define RG_TURISMO_TRX_SX5GB_TTL_SUB_INV_SZ 1
+#define RG_TURISMO_TRX_SX5GB_TTL_VH_MSK 0x18000000
+#define RG_TURISMO_TRX_SX5GB_TTL_VH_I_MSK 0xe7ffffff
+#define RG_TURISMO_TRX_SX5GB_TTL_VH_SFT 27
+#define RG_TURISMO_TRX_SX5GB_TTL_VH_HI 28
+#define RG_TURISMO_TRX_SX5GB_TTL_VH_SZ 2
+#define RG_TURISMO_TRX_SX5GB_TTL_VL_MSK 0x60000000
+#define RG_TURISMO_TRX_SX5GB_TTL_VL_I_MSK 0x9fffffff
+#define RG_TURISMO_TRX_SX5GB_TTL_VL_SFT 29
+#define RG_TURISMO_TRX_SX5GB_TTL_VL_HI 30
+#define RG_TURISMO_TRX_SX5GB_TTL_VL_SZ 2
+#define RG_TURISMO_TRX_SX5GB_LPF_VTUNE_TEST_MSK 0x80000000
+#define RG_TURISMO_TRX_SX5GB_LPF_VTUNE_TEST_I_MSK 0x7fffffff
+#define RG_TURISMO_TRX_SX5GB_LPF_VTUNE_TEST_SFT 31
+#define RG_TURISMO_TRX_SX5GB_LPF_VTUNE_TEST_HI 31
+#define RG_TURISMO_TRX_SX5GB_LPF_VTUNE_TEST_SZ 1
+#define RG_TURISMO_TRX_SX5GB_VCO_ISEL_MAN_MSK 0x00000001
+#define RG_TURISMO_TRX_SX5GB_VCO_ISEL_MAN_I_MSK 0xfffffffe
+#define RG_TURISMO_TRX_SX5GB_VCO_ISEL_MAN_SFT 0
+#define RG_TURISMO_TRX_SX5GB_VCO_ISEL_MAN_HI 0
+#define RG_TURISMO_TRX_SX5GB_VCO_ISEL_MAN_SZ 1
+#define RG_TURISMO_TRX_SX5GB_VCO_ISEL_MSK 0x0000001e
+#define RG_TURISMO_TRX_SX5GB_VCO_ISEL_I_MSK 0xffffffe1
+#define RG_TURISMO_TRX_SX5GB_VCO_ISEL_SFT 1
+#define RG_TURISMO_TRX_SX5GB_VCO_ISEL_HI 4
+#define RG_TURISMO_TRX_SX5GB_VCO_ISEL_SZ 4
+#define RG_TURISMO_TRX_SX5GB_VCO_VCCBSEL_MSK 0x000001c0
+#define RG_TURISMO_TRX_SX5GB_VCO_VCCBSEL_I_MSK 0xfffffe3f
+#define RG_TURISMO_TRX_SX5GB_VCO_VCCBSEL_SFT 6
+#define RG_TURISMO_TRX_SX5GB_VCO_VCCBSEL_HI 8
+#define RG_TURISMO_TRX_SX5GB_VCO_VCCBSEL_SZ 3
+#define RG_TURISMO_TRX_SX5GB_VCO_KVDOUB_MSK 0x00000200
+#define RG_TURISMO_TRX_SX5GB_VCO_KVDOUB_I_MSK 0xfffffdff
+#define RG_TURISMO_TRX_SX5GB_VCO_KVDOUB_SFT 9
+#define RG_TURISMO_TRX_SX5GB_VCO_KVDOUB_HI 9
+#define RG_TURISMO_TRX_SX5GB_VCO_KVDOUB_SZ 1
+#define RG_TURISMO_TRX_SX5GB_VCO_VARBSEL_MSK 0x00001800
+#define RG_TURISMO_TRX_SX5GB_VCO_VARBSEL_I_MSK 0xffffe7ff
+#define RG_TURISMO_TRX_SX5GB_VCO_VARBSEL_SFT 11
+#define RG_TURISMO_TRX_SX5GB_VCO_VARBSEL_HI 12
+#define RG_TURISMO_TRX_SX5GB_VCO_VARBSEL_SZ 2
+#define RG_TURISMO_TRX_SX5GB_VCO_RTAIL_SHIFT_MSK 0x00002000
+#define RG_TURISMO_TRX_SX5GB_VCO_RTAIL_SHIFT_I_MSK 0xffffdfff
+#define RG_TURISMO_TRX_SX5GB_VCO_RTAIL_SHIFT_SFT 13
+#define RG_TURISMO_TRX_SX5GB_VCO_RTAIL_SHIFT_HI 13
+#define RG_TURISMO_TRX_SX5GB_VCO_RTAIL_SHIFT_SZ 1
+#define RG_TURISMO_TRX_SX5GB_VCO_CS_AWH_MSK 0x00004000
+#define RG_TURISMO_TRX_SX5GB_VCO_CS_AWH_I_MSK 0xffffbfff
+#define RG_TURISMO_TRX_SX5GB_VCO_CS_AWH_SFT 14
+#define RG_TURISMO_TRX_SX5GB_VCO_CS_AWH_HI 14
+#define RG_TURISMO_TRX_SX5GB_VCO_CS_AWH_SZ 1
+#define RG_TURISMO_TRX_HSDIV_INBFSEL_MSK 0x00018000
+#define RG_TURISMO_TRX_HSDIV_INBFSEL_I_MSK 0xfffe7fff
+#define RG_TURISMO_TRX_HSDIV_INBFSEL_SFT 15
+#define RG_TURISMO_TRX_HSDIV_INBFSEL_HI 16
+#define RG_TURISMO_TRX_HSDIV_INBFSEL_SZ 2
+#define RG_TURISMO_TRX_HSDIV_OBFMX_SEL_MSK 0x00020000
+#define RG_TURISMO_TRX_HSDIV_OBFMX_SEL_I_MSK 0xfffdffff
+#define RG_TURISMO_TRX_HSDIV_OBFMX_SEL_SFT 17
+#define RG_TURISMO_TRX_HSDIV_OBFMX_SEL_HI 17
+#define RG_TURISMO_TRX_HSDIV_OBFMX_SEL_SZ 1
+#define RG_TURISMO_TRX_HSDIV_OBFSX_SEL_MSK 0x00040000
+#define RG_TURISMO_TRX_HSDIV_OBFSX_SEL_I_MSK 0xfffbffff
+#define RG_TURISMO_TRX_HSDIV_OBFSX_SEL_SFT 18
+#define RG_TURISMO_TRX_HSDIV_OBFSX_SEL_HI 18
+#define RG_TURISMO_TRX_HSDIV_OBFSX_SEL_SZ 1
+#define RG_TURISMO_TRX_HSDIV_VRSEL_MSK 0x00180000
+#define RG_TURISMO_TRX_HSDIV_VRSEL_I_MSK 0xffe7ffff
+#define RG_TURISMO_TRX_HSDIV_VRSEL_SFT 19
+#define RG_TURISMO_TRX_HSDIV_VRSEL_HI 20
+#define RG_TURISMO_TRX_HSDIV_VRSEL_SZ 2
+#define RG_TURISMO_TRX_SXMIX_IBIAS_SEL_MSK 0x00600000
+#define RG_TURISMO_TRX_SXMIX_IBIAS_SEL_I_MSK 0xff9fffff
+#define RG_TURISMO_TRX_SXMIX_IBIAS_SEL_SFT 21
+#define RG_TURISMO_TRX_SXMIX_IBIAS_SEL_HI 22
+#define RG_TURISMO_TRX_SXMIX_IBIAS_SEL_SZ 2
+#define RG_TURISMO_TRX_SXMIX_SWB_SEL_MSK 0x01800000
+#define RG_TURISMO_TRX_SXMIX_SWB_SEL_I_MSK 0xfe7fffff
+#define RG_TURISMO_TRX_SXMIX_SWB_SEL_SFT 23
+#define RG_TURISMO_TRX_SXMIX_SWB_SEL_HI 24
+#define RG_TURISMO_TRX_SXMIX_SWB_SEL_SZ 2
+#define RG_TURISMO_TRX_SXMIX_GMSEL_MSK 0x06000000
+#define RG_TURISMO_TRX_SXMIX_GMSEL_I_MSK 0xf9ffffff
+#define RG_TURISMO_TRX_SXMIX_GMSEL_SFT 25
+#define RG_TURISMO_TRX_SXMIX_GMSEL_HI 26
+#define RG_TURISMO_TRX_SXMIX_GMSEL_SZ 2
+#define RG_TURISMO_TRX_SXREP_SWB_SEL_MSK 0x18000000
+#define RG_TURISMO_TRX_SXREP_SWB_SEL_I_MSK 0xe7ffffff
+#define RG_TURISMO_TRX_SXREP_SWB_SEL_SFT 27
+#define RG_TURISMO_TRX_SXREP_SWB_SEL_HI 28
+#define RG_TURISMO_TRX_SXREP_SWB_SEL_SZ 2
+#define RG_TURISMO_TRX_SXREP_CSSEL_MSK 0x60000000
+#define RG_TURISMO_TRX_SXREP_CSSEL_I_MSK 0x9fffffff
+#define RG_TURISMO_TRX_SXREP_CSSEL_SFT 29
+#define RG_TURISMO_TRX_SXREP_CSSEL_HI 30
+#define RG_TURISMO_TRX_SXREP_CSSEL_SZ 2
+#define RG_TURISMO_TRX_EN_SX5GB_VCOMON_MSK 0x80000000
+#define RG_TURISMO_TRX_EN_SX5GB_VCOMON_I_MSK 0x7fffffff
+#define RG_TURISMO_TRX_EN_SX5GB_VCOMON_SFT 31
+#define RG_TURISMO_TRX_EN_SX5GB_VCOMON_HI 31
+#define RG_TURISMO_TRX_EN_SX5GB_VCOMON_SZ 1
+#define RG_TURISMO_TRX_SX5GB_DIV_PREVDD_MSK 0x0000000f
+#define RG_TURISMO_TRX_SX5GB_DIV_PREVDD_I_MSK 0xfffffff0
+#define RG_TURISMO_TRX_SX5GB_DIV_PREVDD_SFT 0
+#define RG_TURISMO_TRX_SX5GB_DIV_PREVDD_HI 3
+#define RG_TURISMO_TRX_SX5GB_DIV_PREVDD_SZ 4
+#define RG_TURISMO_TRX_SX5GB_DIV_PSCVDD_MSK 0x000000f0
+#define RG_TURISMO_TRX_SX5GB_DIV_PSCVDD_I_MSK 0xffffff0f
+#define RG_TURISMO_TRX_SX5GB_DIV_PSCVDD_SFT 4
+#define RG_TURISMO_TRX_SX5GB_DIV_PSCVDD_HI 7
+#define RG_TURISMO_TRX_SX5GB_DIV_PSCVDD_SZ 4
+#define RG_TURISMO_TRX_SX5GB_DIV_RST_H_MSK 0x00000200
+#define RG_TURISMO_TRX_SX5GB_DIV_RST_H_I_MSK 0xfffffdff
+#define RG_TURISMO_TRX_SX5GB_DIV_RST_H_SFT 9
+#define RG_TURISMO_TRX_SX5GB_DIV_RST_H_HI 9
+#define RG_TURISMO_TRX_SX5GB_DIV_RST_H_SZ 1
+#define RG_TURISMO_TRX_SX5GB_DIV_SDM_EDGE_MSK 0x00000400
+#define RG_TURISMO_TRX_SX5GB_DIV_SDM_EDGE_I_MSK 0xfffffbff
+#define RG_TURISMO_TRX_SX5GB_DIV_SDM_EDGE_SFT 10
+#define RG_TURISMO_TRX_SX5GB_DIV_SDM_EDGE_HI 10
+#define RG_TURISMO_TRX_SX5GB_DIV_SDM_EDGE_SZ 1
+#define RG_TURISMO_TRX_SX5GB_DIV_DMYBUF_EN_MSK 0x00000800
+#define RG_TURISMO_TRX_SX5GB_DIV_DMYBUF_EN_I_MSK 0xfffff7ff
+#define RG_TURISMO_TRX_SX5GB_DIV_DMYBUF_EN_SFT 11
+#define RG_TURISMO_TRX_SX5GB_DIV_DMYBUF_EN_HI 11
+#define RG_TURISMO_TRX_SX5GB_DIV_DMYBUF_EN_SZ 1
+#define RG_TURISMO_TRX_EN_SX5GB_MOD_MSK 0x00020000
+#define RG_TURISMO_TRX_EN_SX5GB_MOD_I_MSK 0xfffdffff
+#define RG_TURISMO_TRX_EN_SX5GB_MOD_SFT 17
+#define RG_TURISMO_TRX_EN_SX5GB_MOD_HI 17
+#define RG_TURISMO_TRX_EN_SX5GB_MOD_SZ 1
+#define RG_TURISMO_TRX_EN_SX5GB_DITHER_MSK 0x00040000
+#define RG_TURISMO_TRX_EN_SX5GB_DITHER_I_MSK 0xfffbffff
+#define RG_TURISMO_TRX_EN_SX5GB_DITHER_SFT 18
+#define RG_TURISMO_TRX_EN_SX5GB_DITHER_HI 18
+#define RG_TURISMO_TRX_EN_SX5GB_DITHER_SZ 1
+#define RG_TURISMO_TRX_SX5GB_MOD_ORDER_MSK 0x00180000
+#define RG_TURISMO_TRX_SX5GB_MOD_ORDER_I_MSK 0xffe7ffff
+#define RG_TURISMO_TRX_SX5GB_MOD_ORDER_SFT 19
+#define RG_TURISMO_TRX_SX5GB_MOD_ORDER_HI 20
+#define RG_TURISMO_TRX_SX5GB_MOD_ORDER_SZ 2
+#define RG_TURISMO_TRX_SX5GB_DITHER_WEIGHT_MSK 0x00600000
+#define RG_TURISMO_TRX_SX5GB_DITHER_WEIGHT_I_MSK 0xff9fffff
+#define RG_TURISMO_TRX_SX5GB_DITHER_WEIGHT_SFT 21
+#define RG_TURISMO_TRX_SX5GB_DITHER_WEIGHT_HI 22
+#define RG_TURISMO_TRX_SX5GB_DITHER_WEIGHT_SZ 2
+#define RG_TURISMO_TRX_SX5GB_SUB_SEL_MAN_MSK 0x00000001
+#define RG_TURISMO_TRX_SX5GB_SUB_SEL_MAN_I_MSK 0xfffffffe
+#define RG_TURISMO_TRX_SX5GB_SUB_SEL_MAN_SFT 0
+#define RG_TURISMO_TRX_SX5GB_SUB_SEL_MAN_HI 0
+#define RG_TURISMO_TRX_SX5GB_SUB_SEL_MAN_SZ 1
+#define RG_TURISMO_TRX_SX5GB_SUB_SEL_MSK 0x000001fe
+#define RG_TURISMO_TRX_SX5GB_SUB_SEL_I_MSK 0xfffffe01
+#define RG_TURISMO_TRX_SX5GB_SUB_SEL_SFT 1
+#define RG_TURISMO_TRX_SX5GB_SUB_SEL_HI 8
+#define RG_TURISMO_TRX_SX5GB_SUB_SEL_SZ 8
+#define RG_TURISMO_TRX_SX5GB_SUB_C0P5_DIS_MSK 0x00000200
+#define RG_TURISMO_TRX_SX5GB_SUB_C0P5_DIS_I_MSK 0xfffffdff
+#define RG_TURISMO_TRX_SX5GB_SUB_C0P5_DIS_SFT 9
+#define RG_TURISMO_TRX_SX5GB_SUB_C0P5_DIS_HI 9
+#define RG_TURISMO_TRX_SX5GB_SUB_C0P5_DIS_SZ 1
+#define RG_TURISMO_TRX_SX5GB_SBCAL_CT_MSK 0x00000c00
+#define RG_TURISMO_TRX_SX5GB_SBCAL_CT_I_MSK 0xfffff3ff
+#define RG_TURISMO_TRX_SX5GB_SBCAL_CT_SFT 10
+#define RG_TURISMO_TRX_SX5GB_SBCAL_CT_HI 11
+#define RG_TURISMO_TRX_SX5GB_SBCAL_CT_SZ 2
+#define RG_TURISMO_TRX_SX5GB_SBCAL_WT_MSK 0x00001000
+#define RG_TURISMO_TRX_SX5GB_SBCAL_WT_I_MSK 0xffffefff
+#define RG_TURISMO_TRX_SX5GB_SBCAL_WT_SFT 12
+#define RG_TURISMO_TRX_SX5GB_SBCAL_WT_HI 12
+#define RG_TURISMO_TRX_SX5GB_SBCAL_WT_SZ 1
+#define RG_TURISMO_TRX_SX5GB_SBCAL_DIFFMIN_MSK 0x00002000
+#define RG_TURISMO_TRX_SX5GB_SBCAL_DIFFMIN_I_MSK 0xffffdfff
+#define RG_TURISMO_TRX_SX5GB_SBCAL_DIFFMIN_SFT 13
+#define RG_TURISMO_TRX_SX5GB_SBCAL_DIFFMIN_HI 13
+#define RG_TURISMO_TRX_SX5GB_SBCAL_DIFFMIN_SZ 1
+#define RG_TURISMO_TRX_SX5GB_SBCAL_NTARG_MAN_MSK 0x00008000
+#define RG_TURISMO_TRX_SX5GB_SBCAL_NTARG_MAN_I_MSK 0xffff7fff
+#define RG_TURISMO_TRX_SX5GB_SBCAL_NTARG_MAN_SFT 15
+#define RG_TURISMO_TRX_SX5GB_SBCAL_NTARG_MAN_HI 15
+#define RG_TURISMO_TRX_SX5GB_SBCAL_NTARG_MAN_SZ 1
+#define RG_TURISMO_TRX_SX5GB_SBCAL_NTARG_MSK 0xffff0000
+#define RG_TURISMO_TRX_SX5GB_SBCAL_NTARG_I_MSK 0x0000ffff
+#define RG_TURISMO_TRX_SX5GB_SBCAL_NTARG_SFT 16
+#define RG_TURISMO_TRX_SX5GB_SBCAL_NTARG_HI 31
+#define RG_TURISMO_TRX_SX5GB_SBCAL_NTARG_SZ 16
+#define RG_TURISMO_TRX_SX5GB_VOAAC_TAR_MSK 0x0000000f
+#define RG_TURISMO_TRX_SX5GB_VOAAC_TAR_I_MSK 0xfffffff0
+#define RG_TURISMO_TRX_SX5GB_VOAAC_TAR_SFT 0
+#define RG_TURISMO_TRX_SX5GB_VOAAC_TAR_HI 3
+#define RG_TURISMO_TRX_SX5GB_VOAAC_TAR_SZ 4
+#define RG_TURISMO_TRX_VO5GB_AAC_IOST_MSK 0x00000030
+#define RG_TURISMO_TRX_VO5GB_AAC_IOST_I_MSK 0xffffffcf
+#define RG_TURISMO_TRX_VO5GB_AAC_IOST_SFT 4
+#define RG_TURISMO_TRX_VO5GB_AAC_IOST_HI 5
+#define RG_TURISMO_TRX_VO5GB_AAC_IOST_SZ 2
+#define RG_TURISMO_TRX_VO5GB_AAC_IMAX_MSK 0x000003c0
+#define RG_TURISMO_TRX_VO5GB_AAC_IMAX_I_MSK 0xfffffc3f
+#define RG_TURISMO_TRX_VO5GB_AAC_IMAX_SFT 6
+#define RG_TURISMO_TRX_VO5GB_AAC_IMAX_HI 9
+#define RG_TURISMO_TRX_VO5GB_AAC_IMAX_SZ 4
+#define RG_TURISMO_TRX_SX5GB_AAC_ACCUMH_MSK 0x00000c00
+#define RG_TURISMO_TRX_SX5GB_AAC_ACCUMH_I_MSK 0xfffff3ff
+#define RG_TURISMO_TRX_SX5GB_AAC_ACCUMH_SFT 10
+#define RG_TURISMO_TRX_SX5GB_AAC_ACCUMH_HI 11
+#define RG_TURISMO_TRX_SX5GB_AAC_ACCUMH_SZ 2
+#define RG_TURISMO_TRX_SX5GB_AAC_ACCUML_MSK 0x00003000
+#define RG_TURISMO_TRX_SX5GB_AAC_ACCUML_I_MSK 0xffffcfff
+#define RG_TURISMO_TRX_SX5GB_AAC_ACCUML_SFT 12
+#define RG_TURISMO_TRX_SX5GB_AAC_ACCUML_HI 13
+#define RG_TURISMO_TRX_SX5GB_AAC_ACCUML_SZ 2
+#define RG_TURISMO_TRX_SX5GB_AAC_INIT_MSK 0x0000c000
+#define RG_TURISMO_TRX_SX5GB_AAC_INIT_I_MSK 0xffff3fff
+#define RG_TURISMO_TRX_SX5GB_AAC_INIT_SFT 14
+#define RG_TURISMO_TRX_SX5GB_AAC_INIT_HI 15
+#define RG_TURISMO_TRX_SX5GB_AAC_INIT_SZ 2
+#define RG_TURISMO_TRX_SX5GB_AAC_EVA_TS_MSK 0x00030000
+#define RG_TURISMO_TRX_SX5GB_AAC_EVA_TS_I_MSK 0xfffcffff
+#define RG_TURISMO_TRX_SX5GB_AAC_EVA_TS_SFT 16
+#define RG_TURISMO_TRX_SX5GB_AAC_EVA_TS_HI 17
+#define RG_TURISMO_TRX_SX5GB_AAC_EVA_TS_SZ 2
+#define RG_TURISMO_TRX_SX5GB_AAC_EN_MAN_MSK 0x00040000
+#define RG_TURISMO_TRX_SX5GB_AAC_EN_MAN_I_MSK 0xfffbffff
+#define RG_TURISMO_TRX_SX5GB_AAC_EN_MAN_SFT 18
+#define RG_TURISMO_TRX_SX5GB_AAC_EN_MAN_HI 18
+#define RG_TURISMO_TRX_SX5GB_AAC_EN_MAN_SZ 1
+#define RG_TURISMO_TRX_SX5GB_AAC_EN_MSK 0x00080000
+#define RG_TURISMO_TRX_SX5GB_AAC_EN_I_MSK 0xfff7ffff
+#define RG_TURISMO_TRX_SX5GB_AAC_EN_SFT 19
+#define RG_TURISMO_TRX_SX5GB_AAC_EN_HI 19
+#define RG_TURISMO_TRX_SX5GB_AAC_EN_SZ 1
+#define RG_TURISMO_TRX_SX5GB_AAC_EVA_MAN_MSK 0x00100000
+#define RG_TURISMO_TRX_SX5GB_AAC_EVA_MAN_I_MSK 0xffefffff
+#define RG_TURISMO_TRX_SX5GB_AAC_EVA_MAN_SFT 20
+#define RG_TURISMO_TRX_SX5GB_AAC_EVA_MAN_HI 20
+#define RG_TURISMO_TRX_SX5GB_AAC_EVA_MAN_SZ 1
+#define RG_TURISMO_TRX_SX5GB_AAC_EVA_MSK 0x00200000
+#define RG_TURISMO_TRX_SX5GB_AAC_EVA_I_MSK 0xffdfffff
+#define RG_TURISMO_TRX_SX5GB_AAC_EVA_SFT 21
+#define RG_TURISMO_TRX_SX5GB_AAC_EVA_HI 21
+#define RG_TURISMO_TRX_SX5GB_AAC_EVA_SZ 1
+#define RG_TURISMO_TRX_AAC5GB_TAR_MAN_MSK 0x00400000
+#define RG_TURISMO_TRX_AAC5GB_TAR_MAN_I_MSK 0xffbfffff
+#define RG_TURISMO_TRX_AAC5GB_TAR_MAN_SFT 22
+#define RG_TURISMO_TRX_AAC5GB_TAR_MAN_HI 22
+#define RG_TURISMO_TRX_AAC5GB_TAR_MAN_SZ 1
+#define RG_TURISMO_TRX_AAC5GB_PDSW_EN_MAN_MSK 0x01000000
+#define RG_TURISMO_TRX_AAC5GB_PDSW_EN_MAN_I_MSK 0xfeffffff
+#define RG_TURISMO_TRX_AAC5GB_PDSW_EN_MAN_SFT 24
+#define RG_TURISMO_TRX_AAC5GB_PDSW_EN_MAN_HI 24
+#define RG_TURISMO_TRX_AAC5GB_PDSW_EN_MAN_SZ 1
+#define RG_TURISMO_TRX_EN_AAC5GB_VOPDSW_MSK 0x02000000
+#define RG_TURISMO_TRX_EN_AAC5GB_VOPDSW_I_MSK 0xfdffffff
+#define RG_TURISMO_TRX_EN_AAC5GB_VOPDSW_SFT 25
+#define RG_TURISMO_TRX_EN_AAC5GB_VOPDSW_HI 25
+#define RG_TURISMO_TRX_EN_AAC5GB_VOPDSW_SZ 1
+#define RG_TURISMO_TRX_EN_AAC5GB_MXPDSW_MSK 0x04000000
+#define RG_TURISMO_TRX_EN_AAC5GB_MXPDSW_I_MSK 0xfbffffff
+#define RG_TURISMO_TRX_EN_AAC5GB_MXPDSW_SFT 26
+#define RG_TURISMO_TRX_EN_AAC5GB_MXPDSW_HI 26
+#define RG_TURISMO_TRX_EN_AAC5GB_MXPDSW_SZ 1
+#define RG_TURISMO_TRX_EN_AAC5GB_RPPDSW_MSK 0x08000000
+#define RG_TURISMO_TRX_EN_AAC5GB_RPPDSW_I_MSK 0xf7ffffff
+#define RG_TURISMO_TRX_EN_AAC5GB_RPPDSW_SFT 27
+#define RG_TURISMO_TRX_EN_AAC5GB_RPPDSW_HI 27
+#define RG_TURISMO_TRX_EN_AAC5GB_RPPDSW_SZ 1
+#define RG_TURISMO_TRX_SX5GB_AAC_TEST_EN_MSK 0x40000000
+#define RG_TURISMO_TRX_SX5GB_AAC_TEST_EN_I_MSK 0xbfffffff
+#define RG_TURISMO_TRX_SX5GB_AAC_TEST_EN_SFT 30
+#define RG_TURISMO_TRX_SX5GB_AAC_TEST_EN_HI 30
+#define RG_TURISMO_TRX_SX5GB_AAC_TEST_EN_SZ 1
+#define RG_TURISMO_TRX_SX5GB_AAC_TEST_SEL_MSK 0x80000000
+#define RG_TURISMO_TRX_SX5GB_AAC_TEST_SEL_I_MSK 0x7fffffff
+#define RG_TURISMO_TRX_SX5GB_AAC_TEST_SEL_SFT 31
+#define RG_TURISMO_TRX_SX5GB_AAC_TEST_SEL_HI 31
+#define RG_TURISMO_TRX_SX5GB_AAC_TEST_SEL_SZ 1
+#define RG_TURISMO_TRX_SX5GB_MIXAAC_TAR_MSK 0x0000000f
+#define RG_TURISMO_TRX_SX5GB_MIXAAC_TAR_I_MSK 0xfffffff0
+#define RG_TURISMO_TRX_SX5GB_MIXAAC_TAR_SFT 0
+#define RG_TURISMO_TRX_SX5GB_MIXAAC_TAR_HI 3
+#define RG_TURISMO_TRX_SX5GB_MIXAAC_TAR_SZ 4
+#define RG_TURISMO_TRX_SXMIX_SCA_SEL_MAN_MSK 0x00000020
+#define RG_TURISMO_TRX_SXMIX_SCA_SEL_MAN_I_MSK 0xffffffdf
+#define RG_TURISMO_TRX_SXMIX_SCA_SEL_MAN_SFT 5
+#define RG_TURISMO_TRX_SXMIX_SCA_SEL_MAN_HI 5
+#define RG_TURISMO_TRX_SXMIX_SCA_SEL_MAN_SZ 1
+#define RG_TURISMO_TRX_SXMIX_SCA_SEL_MSK 0x00000fc0
+#define RG_TURISMO_TRX_SXMIX_SCA_SEL_I_MSK 0xfffff03f
+#define RG_TURISMO_TRX_SXMIX_SCA_SEL_SFT 6
+#define RG_TURISMO_TRX_SXMIX_SCA_SEL_HI 11
+#define RG_TURISMO_TRX_SXMIX_SCA_SEL_SZ 6
+#define RG_TURISMO_TRX_SX5GB_REPAAC_TAR_MSK 0x0001e000
+#define RG_TURISMO_TRX_SX5GB_REPAAC_TAR_I_MSK 0xfffe1fff
+#define RG_TURISMO_TRX_SX5GB_REPAAC_TAR_SFT 13
+#define RG_TURISMO_TRX_SX5GB_REPAAC_TAR_HI 16
+#define RG_TURISMO_TRX_SX5GB_REPAAC_TAR_SZ 4
+#define RG_TURISMO_TRX_SXREP_SCA_SEL_MAN_MSK 0x00040000
+#define RG_TURISMO_TRX_SXREP_SCA_SEL_MAN_I_MSK 0xfffbffff
+#define RG_TURISMO_TRX_SXREP_SCA_SEL_MAN_SFT 18
+#define RG_TURISMO_TRX_SXREP_SCA_SEL_MAN_HI 18
+#define RG_TURISMO_TRX_SXREP_SCA_SEL_MAN_SZ 1
+#define RG_TURISMO_TRX_SXREP_SCA_SEL_MSK 0x01f80000
+#define RG_TURISMO_TRX_SXREP_SCA_SEL_I_MSK 0xfe07ffff
+#define RG_TURISMO_TRX_SXREP_SCA_SEL_SFT 19
+#define RG_TURISMO_TRX_SXREP_SCA_SEL_HI 24
+#define RG_TURISMO_TRX_SXREP_SCA_SEL_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG15_MSK 0x0000003f
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG15_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG15_SFT 0
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG15_HI 5
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG15_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG15_MSK 0x00003f00
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG15_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG15_SFT 8
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG15_HI 13
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG15_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG14_MSK 0x003f0000
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG14_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG14_SFT 16
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG14_HI 21
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG14_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG14_MSK 0x3f000000
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG14_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG14_SFT 24
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG14_HI 29
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG14_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG13_MSK 0x0000003f
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG13_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG13_SFT 0
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG13_HI 5
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG13_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG13_MSK 0x00003f00
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG13_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG13_SFT 8
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG13_HI 13
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG13_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG12_MSK 0x003f0000
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG12_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG12_SFT 16
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG12_HI 21
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG12_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG12_MSK 0x3f000000
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG12_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG12_SFT 24
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG12_HI 29
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG12_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG11_MSK 0x0000003f
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG11_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG11_SFT 0
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG11_HI 5
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG11_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG11_MSK 0x00003f00
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG11_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG11_SFT 8
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG11_HI 13
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG11_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG10_MSK 0x003f0000
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG10_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG10_SFT 16
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG10_HI 21
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG10_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG10_MSK 0x3f000000
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG10_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG10_SFT 24
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG10_HI 29
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG10_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG9_MSK 0x0000003f
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG9_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG9_SFT 0
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG9_HI 5
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG9_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG9_MSK 0x00003f00
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG9_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG9_SFT 8
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG9_HI 13
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG9_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG8_MSK 0x003f0000
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG8_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG8_SFT 16
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG8_HI 21
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG8_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG8_MSK 0x3f000000
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG8_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG8_SFT 24
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG8_HI 29
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG8_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG7_MSK 0x0000003f
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG7_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG7_SFT 0
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG7_HI 5
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG7_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG7_MSK 0x00003f00
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG7_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG7_SFT 8
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG7_HI 13
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG7_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG6_MSK 0x003f0000
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG6_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG6_SFT 16
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG6_HI 21
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG6_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG6_MSK 0x3f000000
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG6_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG6_SFT 24
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG6_HI 29
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG6_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG5_MSK 0x0000003f
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG5_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG5_SFT 0
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG5_HI 5
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG5_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG5_MSK 0x00003f00
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG5_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG5_SFT 8
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG5_HI 13
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG5_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG4_MSK 0x003f0000
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG4_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG4_SFT 16
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG4_HI 21
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG4_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG4_MSK 0x3f000000
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG4_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG4_SFT 24
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG4_HI 29
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG4_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG3_MSK 0x0000003f
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG3_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG3_SFT 0
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG3_HI 5
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG3_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG3_MSK 0x00003f00
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG3_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG3_SFT 8
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG3_HI 13
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG3_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG2_MSK 0x003f0000
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG2_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG2_SFT 16
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG2_HI 21
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG2_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG2_MSK 0x3f000000
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG2_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG2_SFT 24
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG2_HI 29
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG2_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG1_MSK 0x0000003f
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG1_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG1_SFT 0
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG1_HI 5
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG1_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG1_MSK 0x00003f00
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG1_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG1_SFT 8
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG1_HI 13
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG1_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG0_MSK 0x003f0000
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG0_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG0_SFT 16
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG0_HI 21
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG0_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG0_MSK 0x3f000000
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG0_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG0_SFT 24
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG0_HI 29
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG0_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG15_MSK 0x0000003f
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG15_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG15_SFT 0
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG15_HI 5
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG15_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG15_MSK 0x00003f00
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG15_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG15_SFT 8
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG15_HI 13
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG15_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG14_MSK 0x003f0000
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG14_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG14_SFT 16
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG14_HI 21
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG14_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG14_MSK 0x3f000000
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG14_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG14_SFT 24
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG14_HI 29
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG14_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG13_MSK 0x0000003f
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG13_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG13_SFT 0
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG13_HI 5
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG13_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG13_MSK 0x00003f00
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG13_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG13_SFT 8
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG13_HI 13
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG13_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG12_MSK 0x003f0000
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG12_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG12_SFT 16
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG12_HI 21
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG12_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG12_MSK 0x3f000000
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG12_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG12_SFT 24
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG12_HI 29
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG12_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG11_MSK 0x0000003f
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG11_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG11_SFT 0
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG11_HI 5
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG11_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG11_MSK 0x00003f00
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG11_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG11_SFT 8
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG11_HI 13
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG11_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG10_MSK 0x003f0000
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG10_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG10_SFT 16
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG10_HI 21
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG10_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG10_MSK 0x3f000000
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG10_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG10_SFT 24
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG10_HI 29
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG10_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG9_MSK 0x0000003f
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG9_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG9_SFT 0
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG9_HI 5
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG9_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG9_MSK 0x00003f00
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG9_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG9_SFT 8
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG9_HI 13
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG9_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG8_MSK 0x003f0000
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG8_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG8_SFT 16
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG8_HI 21
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG8_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG8_MSK 0x3f000000
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG8_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG8_SFT 24
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG8_HI 29
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG8_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG7_MSK 0x0000003f
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG7_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG7_SFT 0
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG7_HI 5
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG7_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG7_MSK 0x00003f00
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG7_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG7_SFT 8
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG7_HI 13
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG7_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG6_MSK 0x003f0000
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG6_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG6_SFT 16
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG6_HI 21
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG6_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG6_MSK 0x3f000000
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG6_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG6_SFT 24
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG6_HI 29
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG6_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG5_MSK 0x0000003f
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG5_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG5_SFT 0
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG5_HI 5
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG5_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG5_MSK 0x00003f00
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG5_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG5_SFT 8
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG5_HI 13
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG5_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG4_MSK 0x003f0000
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG4_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG4_SFT 16
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG4_HI 21
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG4_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG4_MSK 0x3f000000
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG4_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG4_SFT 24
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG4_HI 29
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG4_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG3_MSK 0x0000003f
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG3_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG3_SFT 0
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG3_HI 5
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG3_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG3_MSK 0x00003f00
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG3_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG3_SFT 8
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG3_HI 13
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG3_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG2_MSK 0x003f0000
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG2_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG2_SFT 16
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG2_HI 21
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG2_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG2_MSK 0x3f000000
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG2_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG2_SFT 24
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG2_HI 29
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG2_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG1_MSK 0x0000003f
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG1_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG1_SFT 0
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG1_HI 5
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG1_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG1_MSK 0x00003f00
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG1_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG1_SFT 8
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG1_HI 13
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG1_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG0_MSK 0x003f0000
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG0_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG0_SFT 16
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG0_HI 21
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG0_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG0_MSK 0x3f000000
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG0_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG0_SFT 24
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG0_HI 29
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG0_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE4_MSK 0x0000003f
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE4_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE4_SFT 0
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE4_HI 5
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE4_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE4_MSK 0x00003f00
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE4_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE4_SFT 8
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE4_HI 13
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE4_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE3_MSK 0x003f0000
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE3_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE3_SFT 16
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE3_HI 21
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE3_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE3_MSK 0x3f000000
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE3_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE3_SFT 24
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE3_HI 29
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE3_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE2_MSK 0x0000003f
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE2_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE2_SFT 0
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE2_HI 5
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE2_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE2_MSK 0x00003f00
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE2_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE2_SFT 8
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE2_HI 13
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE2_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE1_MSK 0x003f0000
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE1_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE1_SFT 16
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE1_HI 21
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE1_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE1_MSK 0x3f000000
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE1_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE1_SFT 24
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE1_HI 29
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE1_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE0_MSK 0x0000003f
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE0_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE0_SFT 0
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE0_HI 5
+#define RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE0_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE0_MSK 0x00003f00
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE0_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE0_SFT 8
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE0_HI 13
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE0_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE4_MSK 0x003f0000
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE4_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE4_SFT 16
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE4_HI 21
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE4_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE4_MSK 0x3f000000
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE4_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE4_SFT 24
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE4_HI 29
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE4_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE3_MSK 0x0000003f
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE3_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE3_SFT 0
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE3_HI 5
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE3_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE3_MSK 0x00003f00
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE3_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE3_SFT 8
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE3_HI 13
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE3_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE2_MSK 0x003f0000
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE2_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE2_SFT 16
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE2_HI 21
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE2_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE2_MSK 0x3f000000
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE2_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE2_SFT 24
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE2_HI 29
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE2_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE1_MSK 0x0000003f
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE1_I_MSK 0xffffffc0
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE1_SFT 0
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE1_HI 5
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE1_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE1_MSK 0x00003f00
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE1_I_MSK 0xffffc0ff
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE1_SFT 8
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE1_HI 13
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE1_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE0_MSK 0x003f0000
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE0_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE0_SFT 16
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE0_HI 21
+#define RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE0_SZ 6
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE0_MSK 0x3f000000
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE0_I_MSK 0xc0ffffff
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE0_SFT 24
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE0_HI 29
+#define RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE0_SZ 6
+#define RG_TURISMO_TRX_SX5GB_DELAY_MSK 0x0000000f
+#define RG_TURISMO_TRX_SX5GB_DELAY_I_MSK 0xfffffff0
+#define RG_TURISMO_TRX_SX5GB_DELAY_SFT 0
+#define RG_TURISMO_TRX_SX5GB_DELAY_HI 3
+#define RG_TURISMO_TRX_SX5GB_DELAY_SZ 4
+#define RG_TURISMO_TRX_5G_TXDAC_DELAY_MSK 0x000000f0
+#define RG_TURISMO_TRX_5G_TXDAC_DELAY_I_MSK 0xffffff0f
+#define RG_TURISMO_TRX_5G_TXDAC_DELAY_SFT 4
+#define RG_TURISMO_TRX_5G_TXDAC_DELAY_HI 7
+#define RG_TURISMO_TRX_5G_TXDAC_DELAY_SZ 4
+#define RG_TURISMO_TRX_5G_TXRF_DELAY_MSK 0x00000f00
+#define RG_TURISMO_TRX_5G_TXRF_DELAY_I_MSK 0xfffff0ff
+#define RG_TURISMO_TRX_5G_TXRF_DELAY_SFT 8
+#define RG_TURISMO_TRX_5G_TXRF_DELAY_HI 11
+#define RG_TURISMO_TRX_5G_TXRF_DELAY_SZ 4
+#define RG_TURISMO_TRX_5G_TXPA_DELAY_MSK 0x0000f000
+#define RG_TURISMO_TRX_5G_TXPA_DELAY_I_MSK 0xffff0fff
+#define RG_TURISMO_TRX_5G_TXPA_DELAY_SFT 12
+#define RG_TURISMO_TRX_5G_TXPA_DELAY_HI 15
+#define RG_TURISMO_TRX_5G_TXPA_DELAY_SZ 4
+#define RG_TURISMO_TRX_5G_RXRF_DELAY_MSK 0x000f0000
+#define RG_TURISMO_TRX_5G_RXRF_DELAY_I_MSK 0xfff0ffff
+#define RG_TURISMO_TRX_5G_RXRF_DELAY_SFT 16
+#define RG_TURISMO_TRX_5G_RXRF_DELAY_HI 19
+#define RG_TURISMO_TRX_5G_RXRF_DELAY_SZ 4
+#define RG_TURISMO_TRX_5G_TXDAC_T2R_DELAY_MSK 0x0000001f
+#define RG_TURISMO_TRX_5G_TXDAC_T2R_DELAY_I_MSK 0xffffffe0
+#define RG_TURISMO_TRX_5G_TXDAC_T2R_DELAY_SFT 0
+#define RG_TURISMO_TRX_5G_TXDAC_T2R_DELAY_HI 4
+#define RG_TURISMO_TRX_5G_TXDAC_T2R_DELAY_SZ 5
+#define RG_TURISMO_TRX_5G_TXRF_T2R_DELAY_MSK 0x00001f00
+#define RG_TURISMO_TRX_5G_TXRF_T2R_DELAY_I_MSK 0xffffe0ff
+#define RG_TURISMO_TRX_5G_TXRF_T2R_DELAY_SFT 8
+#define RG_TURISMO_TRX_5G_TXRF_T2R_DELAY_HI 12
+#define RG_TURISMO_TRX_5G_TXRF_T2R_DELAY_SZ 5
+#define RG_TURISMO_TRX_5G_TXPA_T2R_DELAY_MSK 0x001f0000
+#define RG_TURISMO_TRX_5G_TXPA_T2R_DELAY_I_MSK 0xffe0ffff
+#define RG_TURISMO_TRX_5G_TXPA_T2R_DELAY_SFT 16
+#define RG_TURISMO_TRX_5G_TXPA_T2R_DELAY_HI 20
+#define RG_TURISMO_TRX_5G_TXPA_T2R_DELAY_SZ 5
+#define RG_TURISMO_TRX_5G_RXRF_T2R_DELAY_MSK 0x1f000000
+#define RG_TURISMO_TRX_5G_RXRF_T2R_DELAY_I_MSK 0xe0ffffff
+#define RG_TURISMO_TRX_5G_RXRF_T2R_DELAY_SFT 24
+#define RG_TURISMO_TRX_5G_RXRF_T2R_DELAY_HI 28
+#define RG_TURISMO_TRX_5G_RXRF_T2R_DELAY_SZ 5
+#define RG_TURISMO_TRX_5G_TXDAC_R2T_DELAY_MSK 0x0000001f
+#define RG_TURISMO_TRX_5G_TXDAC_R2T_DELAY_I_MSK 0xffffffe0
+#define RG_TURISMO_TRX_5G_TXDAC_R2T_DELAY_SFT 0
+#define RG_TURISMO_TRX_5G_TXDAC_R2T_DELAY_HI 4
+#define RG_TURISMO_TRX_5G_TXDAC_R2T_DELAY_SZ 5
+#define RG_TURISMO_TRX_5G_TXRF_R2T_DELAY_MSK 0x00001f00
+#define RG_TURISMO_TRX_5G_TXRF_R2T_DELAY_I_MSK 0xffffe0ff
+#define RG_TURISMO_TRX_5G_TXRF_R2T_DELAY_SFT 8
+#define RG_TURISMO_TRX_5G_TXRF_R2T_DELAY_HI 12
+#define RG_TURISMO_TRX_5G_TXRF_R2T_DELAY_SZ 5
+#define RG_TURISMO_TRX_5G_TXPA_R2T_DELAY_MSK 0x001f0000
+#define RG_TURISMO_TRX_5G_TXPA_R2T_DELAY_I_MSK 0xffe0ffff
+#define RG_TURISMO_TRX_5G_TXPA_R2T_DELAY_SFT 16
+#define RG_TURISMO_TRX_5G_TXPA_R2T_DELAY_HI 20
+#define RG_TURISMO_TRX_5G_TXPA_R2T_DELAY_SZ 5
+#define RG_TURISMO_TRX_5G_RXRF_R2T_DELAY_MSK 0x1f000000
+#define RG_TURISMO_TRX_5G_RXRF_R2T_DELAY_I_MSK 0xe0ffffff
+#define RG_TURISMO_TRX_5G_RXRF_R2T_DELAY_SFT 24
+#define RG_TURISMO_TRX_5G_RXRF_R2T_DELAY_HI 28
+#define RG_TURISMO_TRX_5G_RXRF_R2T_DELAY_SZ 5
+#define RG_TURISMO_TRX_5G_RX_DCCAL_DELAY_MSK 0x00000007
+#define RG_TURISMO_TRX_5G_RX_DCCAL_DELAY_I_MSK 0xfffffff8
+#define RG_TURISMO_TRX_5G_RX_DCCAL_DELAY_SFT 0
+#define RG_TURISMO_TRX_5G_RX_DCCAL_DELAY_HI 2
+#define RG_TURISMO_TRX_5G_RX_DCCAL_DELAY_SZ 3
+#define RG_TURISMO_TRX_5G_TX_DCCAL_DELAY_MSK 0x00000700
+#define RG_TURISMO_TRX_5G_TX_DCCAL_DELAY_I_MSK 0xfffff8ff
+#define RG_TURISMO_TRX_5G_TX_DCCAL_DELAY_SFT 8
+#define RG_TURISMO_TRX_5G_TX_DCCAL_DELAY_HI 10
+#define RG_TURISMO_TRX_5G_TX_DCCAL_DELAY_SZ 3
+#define RG_TURISMO_TRX_5G_TX_IQCAL_DELAY_MSK 0x00007000
+#define RG_TURISMO_TRX_5G_TX_IQCAL_DELAY_I_MSK 0xffff8fff
+#define RG_TURISMO_TRX_5G_TX_IQCAL_DELAY_SFT 12
+#define RG_TURISMO_TRX_5G_TX_IQCAL_DELAY_HI 14
+#define RG_TURISMO_TRX_5G_TX_IQCAL_DELAY_SZ 3
+#define RG_TURISMO_TRX_5G_RX_IQCAL_DELAY_MSK 0x00070000
+#define RG_TURISMO_TRX_5G_RX_IQCAL_DELAY_I_MSK 0xfff8ffff
+#define RG_TURISMO_TRX_5G_RX_IQCAL_DELAY_SFT 16
+#define RG_TURISMO_TRX_5G_RX_IQCAL_DELAY_HI 18
+#define RG_TURISMO_TRX_5G_RX_IQCAL_DELAY_SZ 3
+#define RG_TURISMO_TRX_5G_PGAG_TXCAL_MSK 0x00f00000
+#define RG_TURISMO_TRX_5G_PGAG_TXCAL_I_MSK 0xff0fffff
+#define RG_TURISMO_TRX_5G_PGAG_TXCAL_SFT 20
+#define RG_TURISMO_TRX_5G_PGAG_TXCAL_HI 23
+#define RG_TURISMO_TRX_5G_PGAG_TXCAL_SZ 4
+#define RG_TURISMO_TRX_5G_TX_GAIN_TXCAL_MSK 0x7f000000
+#define RG_TURISMO_TRX_5G_TX_GAIN_TXCAL_I_MSK 0x80ffffff
+#define RG_TURISMO_TRX_5G_TX_GAIN_TXCAL_SFT 24
+#define RG_TURISMO_TRX_5G_TX_GAIN_TXCAL_HI 30
+#define RG_TURISMO_TRX_5G_TX_GAIN_TXCAL_SZ 7
+#define RG_TURISMO_TRX_5G_PGAG_RCCAL_MSK 0x0000000f
+#define RG_TURISMO_TRX_5G_PGAG_RCCAL_I_MSK 0xfffffff0
+#define RG_TURISMO_TRX_5G_PGAG_RCCAL_SFT 0
+#define RG_TURISMO_TRX_5G_PGAG_RCCAL_HI 3
+#define RG_TURISMO_TRX_5G_PGAG_RCCAL_SZ 4
+#define RG_TURISMO_TRX_5G_RFG_RXIQCAL_MSK 0x00000030
+#define RG_TURISMO_TRX_5G_RFG_RXIQCAL_I_MSK 0xffffffcf
+#define RG_TURISMO_TRX_5G_RFG_RXIQCAL_SFT 4
+#define RG_TURISMO_TRX_5G_RFG_RXIQCAL_HI 5
+#define RG_TURISMO_TRX_5G_RFG_RXIQCAL_SZ 2
+#define RG_TURISMO_TRX_5G_PGAG_RXIQCAL_MSK 0x000003c0
+#define RG_TURISMO_TRX_5G_PGAG_RXIQCAL_I_MSK 0xfffffc3f
+#define RG_TURISMO_TRX_5G_PGAG_RXIQCAL_SFT 6
+#define RG_TURISMO_TRX_5G_PGAG_RXIQCAL_HI 9
+#define RG_TURISMO_TRX_5G_PGAG_RXIQCAL_SZ 4
+#define RG_TURISMO_TRX_5G_TX_GAIN_RXIQCAL_MSK 0x0001fc00
+#define RG_TURISMO_TRX_5G_TX_GAIN_RXIQCAL_I_MSK 0xfffe03ff
+#define RG_TURISMO_TRX_5G_TX_GAIN_RXIQCAL_SFT 10
+#define RG_TURISMO_TRX_5G_TX_GAIN_RXIQCAL_HI 16
+#define RG_TURISMO_TRX_5G_TX_GAIN_RXIQCAL_SZ 7
+#define RG_TURISMO_TRX_5G_RFG_DPDCAL_MSK 0x00060000
+#define RG_TURISMO_TRX_5G_RFG_DPDCAL_I_MSK 0xfff9ffff
+#define RG_TURISMO_TRX_5G_RFG_DPDCAL_SFT 17
+#define RG_TURISMO_TRX_5G_RFG_DPDCAL_HI 18
+#define RG_TURISMO_TRX_5G_RFG_DPDCAL_SZ 2
+#define RG_TURISMO_TRX_5G_PGAG_DPDCAL_MSK 0x00780000
+#define RG_TURISMO_TRX_5G_PGAG_DPDCAL_I_MSK 0xff87ffff
+#define RG_TURISMO_TRX_5G_PGAG_DPDCAL_SFT 19
+#define RG_TURISMO_TRX_5G_PGAG_DPDCAL_HI 22
+#define RG_TURISMO_TRX_5G_PGAG_DPDCAL_SZ 4
+#define RG_TURISMO_TRX_5G_TX_GAIN_DPDCAL_MSK 0x3f800000
+#define RG_TURISMO_TRX_5G_TX_GAIN_DPDCAL_I_MSK 0xc07fffff
+#define RG_TURISMO_TRX_5G_TX_GAIN_DPDCAL_SFT 23
+#define RG_TURISMO_TRX_5G_TX_GAIN_DPDCAL_HI 29
+#define RG_TURISMO_TRX_5G_TX_GAIN_DPDCAL_SZ 7
+#define DB_TURISMO_TRX_DA_SX5GB_SUB_SEL_MSK 0x000000ff
+#define DB_TURISMO_TRX_DA_SX5GB_SUB_SEL_I_MSK 0xffffff00
+#define DB_TURISMO_TRX_DA_SX5GB_SUB_SEL_SFT 0
+#define DB_TURISMO_TRX_DA_SX5GB_SUB_SEL_HI 7
+#define DB_TURISMO_TRX_DA_SX5GB_SUB_SEL_SZ 8
+#define DB_TURISMO_TRX_DA_SX5GB_VCO_ISEL_MSK 0x00000f00
+#define DB_TURISMO_TRX_DA_SX5GB_VCO_ISEL_I_MSK 0xfffff0ff
+#define DB_TURISMO_TRX_DA_SX5GB_VCO_ISEL_SFT 8
+#define DB_TURISMO_TRX_DA_SX5GB_VCO_ISEL_HI 11
+#define DB_TURISMO_TRX_DA_SX5GB_VCO_ISEL_SZ 4
+#define DB_TURISMO_TRX_DA_SXMIX_SCA_SEL_MSK 0x0007e000
+#define DB_TURISMO_TRX_DA_SXMIX_SCA_SEL_I_MSK 0xfff81fff
+#define DB_TURISMO_TRX_DA_SXMIX_SCA_SEL_SFT 13
+#define DB_TURISMO_TRX_DA_SXMIX_SCA_SEL_HI 18
+#define DB_TURISMO_TRX_DA_SXMIX_SCA_SEL_SZ 6
+#define DB_TURISMO_TRX_DA_SXMIX_GMSEL_MSK 0x00180000
+#define DB_TURISMO_TRX_DA_SXMIX_GMSEL_I_MSK 0xffe7ffff
+#define DB_TURISMO_TRX_DA_SXMIX_GMSEL_SFT 19
+#define DB_TURISMO_TRX_DA_SXMIX_GMSEL_HI 20
+#define DB_TURISMO_TRX_DA_SXMIX_GMSEL_SZ 2
+#define DB_TURISMO_TRX_DA_SXREP_SCA_SEL_MSK 0x07e00000
+#define DB_TURISMO_TRX_DA_SXREP_SCA_SEL_I_MSK 0xf81fffff
+#define DB_TURISMO_TRX_DA_SXREP_SCA_SEL_SFT 21
+#define DB_TURISMO_TRX_DA_SXREP_SCA_SEL_HI 26
+#define DB_TURISMO_TRX_DA_SXREP_SCA_SEL_SZ 6
+#define DB_TURISMO_TRX_DA_SXREP_CSSEL_MSK 0x18000000
+#define DB_TURISMO_TRX_DA_SXREP_CSSEL_I_MSK 0xe7ffffff
+#define DB_TURISMO_TRX_DA_SXREP_CSSEL_SFT 27
+#define DB_TURISMO_TRX_DA_SXREP_CSSEL_HI 28
+#define DB_TURISMO_TRX_DA_SXREP_CSSEL_SZ 2
+#define DB_TURISMO_TRX_AD_SX5GB_AAC_COMPOUT_MSK 0x20000000
+#define DB_TURISMO_TRX_AD_SX5GB_AAC_COMPOUT_I_MSK 0xdfffffff
+#define DB_TURISMO_TRX_AD_SX5GB_AAC_COMPOUT_SFT 29
+#define DB_TURISMO_TRX_AD_SX5GB_AAC_COMPOUT_HI 29
+#define DB_TURISMO_TRX_AD_SX5GB_AAC_COMPOUT_SZ 1
+#define DB_TURISMO_TRX_SX5GB_TTL_VT_DET_MSK 0xc0000000
+#define DB_TURISMO_TRX_SX5GB_TTL_VT_DET_I_MSK 0x3fffffff
+#define DB_TURISMO_TRX_SX5GB_TTL_VT_DET_SFT 30
+#define DB_TURISMO_TRX_SX5GB_TTL_VT_DET_HI 31
+#define DB_TURISMO_TRX_SX5GB_TTL_VT_DET_SZ 2
+#define DB_TURISMO_TRX_SXMIX_SCA_SEL_A1_MSK 0x0000003f
+#define DB_TURISMO_TRX_SXMIX_SCA_SEL_A1_I_MSK 0xffffffc0
+#define DB_TURISMO_TRX_SXMIX_SCA_SEL_A1_SFT 0
+#define DB_TURISMO_TRX_SXMIX_SCA_SEL_A1_HI 5
+#define DB_TURISMO_TRX_SXMIX_SCA_SEL_A1_SZ 6
+#define DB_TURISMO_TRX_SXMIX_SCA_SEL_A2_MSK 0x00001f80
+#define DB_TURISMO_TRX_SXMIX_SCA_SEL_A2_I_MSK 0xffffe07f
+#define DB_TURISMO_TRX_SXMIX_SCA_SEL_A2_SFT 7
+#define DB_TURISMO_TRX_SXMIX_SCA_SEL_A2_HI 12
+#define DB_TURISMO_TRX_SXMIX_SCA_SEL_A2_SZ 6
+#define DB_TURISMO_TRX_SXREP_SCA_SEL_B1_MSK 0x000fc000
+#define DB_TURISMO_TRX_SXREP_SCA_SEL_B1_I_MSK 0xfff03fff
+#define DB_TURISMO_TRX_SXREP_SCA_SEL_B1_SFT 14
+#define DB_TURISMO_TRX_SXREP_SCA_SEL_B1_HI 19
+#define DB_TURISMO_TRX_SXREP_SCA_SEL_B1_SZ 6
+#define DB_TURISMO_TRX_SXREP_SCA_SEL_B2_MSK 0x07e00000
+#define DB_TURISMO_TRX_SXREP_SCA_SEL_B2_I_MSK 0xf81fffff
+#define DB_TURISMO_TRX_SXREP_SCA_SEL_B2_SFT 21
+#define DB_TURISMO_TRX_SXREP_SCA_SEL_B2_HI 26
+#define DB_TURISMO_TRX_SXREP_SCA_SEL_B2_SZ 6
+#define DB_TURISMO_TRX_SX5GB_SBCAL_NCOUNT_MSK 0x0000ffff
+#define DB_TURISMO_TRX_SX5GB_SBCAL_NCOUNT_I_MSK 0xffff0000
+#define DB_TURISMO_TRX_SX5GB_SBCAL_NCOUNT_SFT 0
+#define DB_TURISMO_TRX_SX5GB_SBCAL_NCOUNT_HI 15
+#define DB_TURISMO_TRX_SX5GB_SBCAL_NCOUNT_SZ 16
+#define DB_TURISMO_TRX_SX5GB_SBCAL_NTARGET_MSK 0xffff0000
+#define DB_TURISMO_TRX_SX5GB_SBCAL_NTARGET_I_MSK 0x0000ffff
+#define DB_TURISMO_TRX_SX5GB_SBCAL_NTARGET_SFT 16
+#define DB_TURISMO_TRX_SX5GB_SBCAL_NTARGET_HI 31
+#define DB_TURISMO_TRX_SX5GB_SBCAL_NTARGET_SZ 16
+#define RG_TURISMO_TRX_RX_SCAMA_STEP0_MSK 0x0000000f
+#define RG_TURISMO_TRX_RX_SCAMA_STEP0_I_MSK 0xfffffff0
+#define RG_TURISMO_TRX_RX_SCAMA_STEP0_SFT 0
+#define RG_TURISMO_TRX_RX_SCAMA_STEP0_HI 3
+#define RG_TURISMO_TRX_RX_SCAMA_STEP0_SZ 4
+#define RG_TURISMO_TRX_RX_SCAMA_STEP1_MSK 0x000000f0
+#define RG_TURISMO_TRX_RX_SCAMA_STEP1_I_MSK 0xffffff0f
+#define RG_TURISMO_TRX_RX_SCAMA_STEP1_SFT 4
+#define RG_TURISMO_TRX_RX_SCAMA_STEP1_HI 7
+#define RG_TURISMO_TRX_RX_SCAMA_STEP1_SZ 4
+#define RG_TURISMO_TRX_RX_SCAMA_STEP2_MSK 0x00000f00
+#define RG_TURISMO_TRX_RX_SCAMA_STEP2_I_MSK 0xfffff0ff
+#define RG_TURISMO_TRX_RX_SCAMA_STEP2_SFT 8
+#define RG_TURISMO_TRX_RX_SCAMA_STEP2_HI 11
+#define RG_TURISMO_TRX_RX_SCAMA_STEP2_SZ 4
+#define RG_TURISMO_TRX_RX_SCAMA_STEP3_MSK 0x0000f000
+#define RG_TURISMO_TRX_RX_SCAMA_STEP3_I_MSK 0xffff0fff
+#define RG_TURISMO_TRX_RX_SCAMA_STEP3_SFT 12
+#define RG_TURISMO_TRX_RX_SCAMA_STEP3_HI 15
+#define RG_TURISMO_TRX_RX_SCAMA_STEP3_SZ 4
+#define RG_TURISMO_TRX_RX_SCAMA_STEP4_MSK 0x000f0000
+#define RG_TURISMO_TRX_RX_SCAMA_STEP4_I_MSK 0xfff0ffff
+#define RG_TURISMO_TRX_RX_SCAMA_STEP4_SFT 16
+#define RG_TURISMO_TRX_RX_SCAMA_STEP4_HI 19
+#define RG_TURISMO_TRX_RX_SCAMA_STEP4_SZ 4
+#define RG_TURISMO_TRX_RX_SCAMA_STEP5_MSK 0x00f00000
+#define RG_TURISMO_TRX_RX_SCAMA_STEP5_I_MSK 0xff0fffff
+#define RG_TURISMO_TRX_RX_SCAMA_STEP5_SFT 20
+#define RG_TURISMO_TRX_RX_SCAMA_STEP5_HI 23
+#define RG_TURISMO_TRX_RX_SCAMA_STEP5_SZ 4
+#define RG_TURISMO_TRX_RX_SCAMA_STEP6_MSK 0x0f000000
+#define RG_TURISMO_TRX_RX_SCAMA_STEP6_I_MSK 0xf0ffffff
+#define RG_TURISMO_TRX_RX_SCAMA_STEP6_SFT 24
+#define RG_TURISMO_TRX_RX_SCAMA_STEP6_HI 27
+#define RG_TURISMO_TRX_RX_SCAMA_STEP6_SZ 4
+#define RG_TURISMO_TRX_RX_SCALOAD_STEP0_MSK 0x0000000f
+#define RG_TURISMO_TRX_RX_SCALOAD_STEP0_I_MSK 0xfffffff0
+#define RG_TURISMO_TRX_RX_SCALOAD_STEP0_SFT 0
+#define RG_TURISMO_TRX_RX_SCALOAD_STEP0_HI 3
+#define RG_TURISMO_TRX_RX_SCALOAD_STEP0_SZ 4
+#define RG_TURISMO_TRX_RX_SCALOAD_STEP1_MSK 0x000000f0
+#define RG_TURISMO_TRX_RX_SCALOAD_STEP1_I_MSK 0xffffff0f
+#define RG_TURISMO_TRX_RX_SCALOAD_STEP1_SFT 4
+#define RG_TURISMO_TRX_RX_SCALOAD_STEP1_HI 7
+#define RG_TURISMO_TRX_RX_SCALOAD_STEP1_SZ 4
+#define RG_TURISMO_TRX_RX_SCALOAD_STEP2_MSK 0x00000f00
+#define RG_TURISMO_TRX_RX_SCALOAD_STEP2_I_MSK 0xfffff0ff
+#define RG_TURISMO_TRX_RX_SCALOAD_STEP2_SFT 8
+#define RG_TURISMO_TRX_RX_SCALOAD_STEP2_HI 11
+#define RG_TURISMO_TRX_RX_SCALOAD_STEP2_SZ 4
+#define RG_TURISMO_TRX_RX_SCALOAD_STEP3_MSK 0x0000f000
+#define RG_TURISMO_TRX_RX_SCALOAD_STEP3_I_MSK 0xffff0fff
+#define RG_TURISMO_TRX_RX_SCALOAD_STEP3_SFT 12
+#define RG_TURISMO_TRX_RX_SCALOAD_STEP3_HI 15
+#define RG_TURISMO_TRX_RX_SCALOAD_STEP3_SZ 4
+#define RG_TURISMO_TRX_RX_SCALOAD_STEP4_MSK 0x000f0000
+#define RG_TURISMO_TRX_RX_SCALOAD_STEP4_I_MSK 0xfff0ffff
+#define RG_TURISMO_TRX_RX_SCALOAD_STEP4_SFT 16
+#define RG_TURISMO_TRX_RX_SCALOAD_STEP4_HI 19
+#define RG_TURISMO_TRX_RX_SCALOAD_STEP4_SZ 4
+#define RG_TURISMO_TRX_RX_SCALOAD_STEP5_MSK 0x00f00000
+#define RG_TURISMO_TRX_RX_SCALOAD_STEP5_I_MSK 0xff0fffff
+#define RG_TURISMO_TRX_RX_SCALOAD_STEP5_SFT 20
+#define RG_TURISMO_TRX_RX_SCALOAD_STEP5_HI 23
+#define RG_TURISMO_TRX_RX_SCALOAD_STEP5_SZ 4
+#define RG_TURISMO_TRX_RX_SCALOAD_STEP6_MSK 0x0f000000
+#define RG_TURISMO_TRX_RX_SCALOAD_STEP6_I_MSK 0xf0ffffff
+#define RG_TURISMO_TRX_RX_SCALOAD_STEP6_SFT 24
+#define RG_TURISMO_TRX_RX_SCALOAD_STEP6_HI 27
+#define RG_TURISMO_TRX_RX_SCALOAD_STEP6_SZ 4
+#define RG_TURISMO_TRX_TX_CAPSW_STEP0_MSK 0x0000000f
+#define RG_TURISMO_TRX_TX_CAPSW_STEP0_I_MSK 0xfffffff0
+#define RG_TURISMO_TRX_TX_CAPSW_STEP0_SFT 0
+#define RG_TURISMO_TRX_TX_CAPSW_STEP0_HI 3
+#define RG_TURISMO_TRX_TX_CAPSW_STEP0_SZ 4
+#define RG_TURISMO_TRX_TX_CAPSW_STEP1_MSK 0x000000f0
+#define RG_TURISMO_TRX_TX_CAPSW_STEP1_I_MSK 0xffffff0f
+#define RG_TURISMO_TRX_TX_CAPSW_STEP1_SFT 4
+#define RG_TURISMO_TRX_TX_CAPSW_STEP1_HI 7
+#define RG_TURISMO_TRX_TX_CAPSW_STEP1_SZ 4
+#define RG_TURISMO_TRX_TX_CAPSW_STEP2_MSK 0x00000f00
+#define RG_TURISMO_TRX_TX_CAPSW_STEP2_I_MSK 0xfffff0ff
+#define RG_TURISMO_TRX_TX_CAPSW_STEP2_SFT 8
+#define RG_TURISMO_TRX_TX_CAPSW_STEP2_HI 11
+#define RG_TURISMO_TRX_TX_CAPSW_STEP2_SZ 4
+#define RG_TURISMO_TRX_TX_CAPSW_STEP3_MSK 0x0000f000
+#define RG_TURISMO_TRX_TX_CAPSW_STEP3_I_MSK 0xffff0fff
+#define RG_TURISMO_TRX_TX_CAPSW_STEP3_SFT 12
+#define RG_TURISMO_TRX_TX_CAPSW_STEP3_HI 15
+#define RG_TURISMO_TRX_TX_CAPSW_STEP3_SZ 4
+#define RG_TURISMO_TRX_TX_CAPSW_STEP4_MSK 0x000f0000
+#define RG_TURISMO_TRX_TX_CAPSW_STEP4_I_MSK 0xfff0ffff
+#define RG_TURISMO_TRX_TX_CAPSW_STEP4_SFT 16
+#define RG_TURISMO_TRX_TX_CAPSW_STEP4_HI 19
+#define RG_TURISMO_TRX_TX_CAPSW_STEP4_SZ 4
+#define RG_TURISMO_TRX_TX_CAPSW_STEP5_MSK 0x00f00000
+#define RG_TURISMO_TRX_TX_CAPSW_STEP5_I_MSK 0xff0fffff
+#define RG_TURISMO_TRX_TX_CAPSW_STEP5_SFT 20
+#define RG_TURISMO_TRX_TX_CAPSW_STEP5_HI 23
+#define RG_TURISMO_TRX_TX_CAPSW_STEP5_SZ 4
+#define RG_TURISMO_TRX_TX_CAPSW_STEP6_MSK 0x0f000000
+#define RG_TURISMO_TRX_TX_CAPSW_STEP6_I_MSK 0xf0ffffff
+#define RG_TURISMO_TRX_TX_CAPSW_STEP6_SFT 24
+#define RG_TURISMO_TRX_TX_CAPSW_STEP6_HI 27
+#define RG_TURISMO_TRX_TX_CAPSW_STEP6_SZ 4
+#define RG_TURISMO_TRX_NFRAC_DELTA_MSK 0x00ffffff
+#define RG_TURISMO_TRX_NFRAC_DELTA_I_MSK 0xff000000
+#define RG_TURISMO_TRX_NFRAC_DELTA_SFT 0
+#define RG_TURISMO_TRX_NFRAC_DELTA_HI 23
+#define RG_TURISMO_TRX_NFRAC_DELTA_SZ 24
+#define RG_TURISMO_TRX_40M_MODE_MSK 0x01000000
+#define RG_TURISMO_TRX_40M_MODE_I_MSK 0xfeffffff
+#define RG_TURISMO_TRX_40M_MODE_SFT 24
+#define RG_TURISMO_TRX_40M_MODE_HI 24
+#define RG_TURISMO_TRX_40M_MODE_SZ 1
+#define RG_TURISMO_TRX_LO_UP_CH_MSK 0x10000000
+#define RG_TURISMO_TRX_LO_UP_CH_I_MSK 0xefffffff
+#define RG_TURISMO_TRX_LO_UP_CH_SFT 28
+#define RG_TURISMO_TRX_LO_UP_CH_HI 28
+#define RG_TURISMO_TRX_LO_UP_CH_SZ 1
+#define RG_TURISMO_TRX_BT_TRX_IF_MSK 0x07ff0000
+#define RG_TURISMO_TRX_BT_TRX_IF_I_MSK 0xf800ffff
+#define RG_TURISMO_TRX_BT_TRX_IF_SFT 16
+#define RG_TURISMO_TRX_BT_TRX_IF_HI 26
+#define RG_TURISMO_TRX_BT_TRX_IF_SZ 11
+#define RG_TURISMO_TRX_RX_IQ_ALPHA_MSK 0x0000001f
+#define RG_TURISMO_TRX_RX_IQ_ALPHA_I_MSK 0xffffffe0
+#define RG_TURISMO_TRX_RX_IQ_ALPHA_SFT 0
+#define RG_TURISMO_TRX_RX_IQ_ALPHA_HI 4
+#define RG_TURISMO_TRX_RX_IQ_ALPHA_SZ 5
+#define RG_TURISMO_TRX_RX_IQ_THETA_MSK 0x00001f00
+#define RG_TURISMO_TRX_RX_IQ_THETA_I_MSK 0xffffe0ff
+#define RG_TURISMO_TRX_RX_IQ_THETA_SFT 8
+#define RG_TURISMO_TRX_RX_IQ_THETA_HI 12
+#define RG_TURISMO_TRX_RX_IQ_THETA_SZ 5
+#define RG_TURISMO_TRX_RX_IQ_MANUAL_MSK 0x00010000
+#define RG_TURISMO_TRX_RX_IQ_MANUAL_I_MSK 0xfffeffff
+#define RG_TURISMO_TRX_RX_IQ_MANUAL_SFT 16
+#define RG_TURISMO_TRX_RX_IQ_MANUAL_HI 16
+#define RG_TURISMO_TRX_RX_IQ_MANUAL_SZ 1
+#define RG_TURISMO_TRX_RXIQ_NOSHRK_MSK 0x00020000
+#define RG_TURISMO_TRX_RXIQ_NOSHRK_I_MSK 0xfffdffff
+#define RG_TURISMO_TRX_RXIQ_NOSHRK_SFT 17
+#define RG_TURISMO_TRX_RXIQ_NOSHRK_HI 17
+#define RG_TURISMO_TRX_RXIQ_NOSHRK_SZ 1
+#define RG_TURISMO_TRX_RX_RSSIADC_TH_MSK 0x00f00000
+#define RG_TURISMO_TRX_RX_RSSIADC_TH_I_MSK 0xff0fffff
+#define RG_TURISMO_TRX_RX_RSSIADC_TH_SFT 20
+#define RG_TURISMO_TRX_RX_RSSIADC_TH_HI 23
+#define RG_TURISMO_TRX_RX_RSSIADC_TH_SZ 4
+#define RG_TURISMO_TRX_SUB_DC_MSK 0x01000000
+#define RG_TURISMO_TRX_SUB_DC_I_MSK 0xfeffffff
+#define RG_TURISMO_TRX_SUB_DC_SFT 24
+#define RG_TURISMO_TRX_SUB_DC_HI 24
+#define RG_TURISMO_TRX_SUB_DC_SZ 1
+#define RG_TURISMO_TRX_IOT_ADC_EDGE_SEL_MSK 0x02000000
+#define RG_TURISMO_TRX_IOT_ADC_EDGE_SEL_I_MSK 0xfdffffff
+#define RG_TURISMO_TRX_IOT_ADC_EDGE_SEL_SFT 25
+#define RG_TURISMO_TRX_IOT_ADC_EDGE_SEL_HI 25
+#define RG_TURISMO_TRX_IOT_ADC_EDGE_SEL_SZ 1
+#define RG_TURISMO_TRX_RSSI_EDGE_SEL_MSK 0x04000000
+#define RG_TURISMO_TRX_RSSI_EDGE_SEL_I_MSK 0xfbffffff
+#define RG_TURISMO_TRX_RSSI_EDGE_SEL_SFT 26
+#define RG_TURISMO_TRX_RSSI_EDGE_SEL_HI 26
+#define RG_TURISMO_TRX_RSSI_EDGE_SEL_SZ 1
+#define RG_TURISMO_TRX_ADC_EDGE_SEL_MSK 0x08000000
+#define RG_TURISMO_TRX_ADC_EDGE_SEL_I_MSK 0xf7ffffff
+#define RG_TURISMO_TRX_ADC_EDGE_SEL_SFT 27
+#define RG_TURISMO_TRX_ADC_EDGE_SEL_HI 27
+#define RG_TURISMO_TRX_ADC_EDGE_SEL_SZ 1
+#define RG_TURISMO_TRX_Q_INV_MSK 0x10000000
+#define RG_TURISMO_TRX_Q_INV_I_MSK 0xefffffff
+#define RG_TURISMO_TRX_Q_INV_SFT 28
+#define RG_TURISMO_TRX_Q_INV_HI 28
+#define RG_TURISMO_TRX_Q_INV_SZ 1
+#define RG_TURISMO_TRX_I_INV_MSK 0x20000000
+#define RG_TURISMO_TRX_I_INV_I_MSK 0xdfffffff
+#define RG_TURISMO_TRX_I_INV_SFT 29
+#define RG_TURISMO_TRX_I_INV_HI 29
+#define RG_TURISMO_TRX_I_INV_SZ 1
+#define RG_TURISMO_TRX_IQ_SWAP_MSK 0x40000000
+#define RG_TURISMO_TRX_IQ_SWAP_I_MSK 0xbfffffff
+#define RG_TURISMO_TRX_IQ_SWAP_SFT 30
+#define RG_TURISMO_TRX_IQ_SWAP_HI 30
+#define RG_TURISMO_TRX_IQ_SWAP_SZ 1
+#define RG_TURISMO_TRX_SIGN_SWAP_MSK 0x80000000
+#define RG_TURISMO_TRX_SIGN_SWAP_I_MSK 0x7fffffff
+#define RG_TURISMO_TRX_SIGN_SWAP_SFT 31
+#define RG_TURISMO_TRX_SIGN_SWAP_HI 31
+#define RG_TURISMO_TRX_SIGN_SWAP_SZ 1
+#define RG_TURISMO_TRX_TX_IQ_ALPHA_MSK 0x0000001f
+#define RG_TURISMO_TRX_TX_IQ_ALPHA_I_MSK 0xffffffe0
+#define RG_TURISMO_TRX_TX_IQ_ALPHA_SFT 0
+#define RG_TURISMO_TRX_TX_IQ_ALPHA_HI 4
+#define RG_TURISMO_TRX_TX_IQ_ALPHA_SZ 5
+#define RG_TURISMO_TRX_TX_IQ_THETA_MSK 0x00001f00
+#define RG_TURISMO_TRX_TX_IQ_THETA_I_MSK 0xffffe0ff
+#define RG_TURISMO_TRX_TX_IQ_THETA_SFT 8
+#define RG_TURISMO_TRX_TX_IQ_THETA_HI 12
+#define RG_TURISMO_TRX_TX_IQ_THETA_SZ 5
+#define RG_TURISMO_TRX_TX_IQ_MANUAL_MSK 0x00010000
+#define RG_TURISMO_TRX_TX_IQ_MANUAL_I_MSK 0xfffeffff
+#define RG_TURISMO_TRX_TX_IQ_MANUAL_SFT 16
+#define RG_TURISMO_TRX_TX_IQ_MANUAL_HI 16
+#define RG_TURISMO_TRX_TX_IQ_MANUAL_SZ 1
+#define RG_TURISMO_TRX_TXIQ_NOSHRK_MSK 0x00020000
+#define RG_TURISMO_TRX_TXIQ_NOSHRK_I_MSK 0xfffdffff
+#define RG_TURISMO_TRX_TXIQ_NOSHRK_SFT 17
+#define RG_TURISMO_TRX_TXIQ_NOSHRK_HI 17
+#define RG_TURISMO_TRX_TXIQ_NOSHRK_SZ 1
+#define RG_TURISMO_TRX_TX_IQCAL_TIME_MSK 0x00300000
+#define RG_TURISMO_TRX_TX_IQCAL_TIME_I_MSK 0xffcfffff
+#define RG_TURISMO_TRX_TX_IQCAL_TIME_SFT 20
+#define RG_TURISMO_TRX_TX_IQCAL_TIME_HI 21
+#define RG_TURISMO_TRX_TX_IQCAL_TIME_SZ 2
+#define RG_TURISMO_TRX_TX_FREQ_OFFSET_MSK 0x0000ffff
+#define RG_TURISMO_TRX_TX_FREQ_OFFSET_I_MSK 0xffff0000
+#define RG_TURISMO_TRX_TX_FREQ_OFFSET_SFT 0
+#define RG_TURISMO_TRX_TX_FREQ_OFFSET_HI 15
+#define RG_TURISMO_TRX_TX_FREQ_OFFSET_SZ 16
+#define RG_TURISMO_TRX_TONE_SCALE_MSK 0x01ff0000
+#define RG_TURISMO_TRX_TONE_SCALE_I_MSK 0xfe00ffff
+#define RG_TURISMO_TRX_TONE_SCALE_SFT 16
+#define RG_TURISMO_TRX_TONE_SCALE_HI 24
+#define RG_TURISMO_TRX_TONE_SCALE_SZ 9
+#define RG_TURISMO_TRX_BB_SIG_EN_MSK 0x02000000
+#define RG_TURISMO_TRX_BB_SIG_EN_I_MSK 0xfdffffff
+#define RG_TURISMO_TRX_BB_SIG_EN_SFT 25
+#define RG_TURISMO_TRX_BB_SIG_EN_HI 25
+#define RG_TURISMO_TRX_BB_SIG_EN_SZ 1
+#define RG_TURISMO_TRX_TONE_GEN_EN_MSK 0x04000000
+#define RG_TURISMO_TRX_TONE_GEN_EN_I_MSK 0xfbffffff
+#define RG_TURISMO_TRX_TONE_GEN_EN_SFT 26
+#define RG_TURISMO_TRX_TONE_GEN_EN_HI 26
+#define RG_TURISMO_TRX_TONE_GEN_EN_SZ 1
+#define RG_TURISMO_TRX_TX_UP8X_MAN_EN_MSK 0x08000000
+#define RG_TURISMO_TRX_TX_UP8X_MAN_EN_I_MSK 0xf7ffffff
+#define RG_TURISMO_TRX_TX_UP8X_MAN_EN_SFT 27
+#define RG_TURISMO_TRX_TX_UP8X_MAN_EN_HI 27
+#define RG_TURISMO_TRX_TX_UP8X_MAN_EN_SZ 1
+#define RG_TURISMO_TRX_DIS_DAC_OFFSET_MSK 0x10000000
+#define RG_TURISMO_TRX_DIS_DAC_OFFSET_I_MSK 0xefffffff
+#define RG_TURISMO_TRX_DIS_DAC_OFFSET_SFT 28
+#define RG_TURISMO_TRX_DIS_DAC_OFFSET_HI 28
+#define RG_TURISMO_TRX_DIS_DAC_OFFSET_SZ 1
+#define RG_TURISMO_TRX_CLK_320M_INV_MSK 0x20000000
+#define RG_TURISMO_TRX_CLK_320M_INV_I_MSK 0xdfffffff
+#define RG_TURISMO_TRX_CLK_320M_INV_SFT 29
+#define RG_TURISMO_TRX_CLK_320M_INV_HI 29
+#define RG_TURISMO_TRX_CLK_320M_INV_SZ 1
+#define RG_TURISMO_TRX_DPLL_CLK320BY2_MSK 0x40000000
+#define RG_TURISMO_TRX_DPLL_CLK320BY2_I_MSK 0xbfffffff
+#define RG_TURISMO_TRX_DPLL_CLK320BY2_SFT 30
+#define RG_TURISMO_TRX_DPLL_CLK320BY2_HI 30
+#define RG_TURISMO_TRX_DPLL_CLK320BY2_SZ 1
+#define RG_TURISMO_TRX_CBW_20_40_MSK 0x80000000
+#define RG_TURISMO_TRX_CBW_20_40_I_MSK 0x7fffffff
+#define RG_TURISMO_TRX_CBW_20_40_SFT 31
+#define RG_TURISMO_TRX_CBW_20_40_HI 31
+#define RG_TURISMO_TRX_CBW_20_40_SZ 1
+#define RG_TURISMO_TRX_DAC_DC_Q_MSK 0x000003ff
+#define RG_TURISMO_TRX_DAC_DC_Q_I_MSK 0xfffffc00
+#define RG_TURISMO_TRX_DAC_DC_Q_SFT 0
+#define RG_TURISMO_TRX_DAC_DC_Q_HI 9
+#define RG_TURISMO_TRX_DAC_DC_Q_SZ 10
+#define RG_TURISMO_TRX_DAC_DC_I_MSK 0x03ff0000
+#define RG_TURISMO_TRX_DAC_DC_I_I_MSK 0xfc00ffff
+#define RG_TURISMO_TRX_DAC_DC_I_SFT 16
+#define RG_TURISMO_TRX_DAC_DC_I_HI 25
+#define RG_TURISMO_TRX_DAC_DC_I_SZ 10
+#define RG_TURISMO_TRX_DAC_Q_SET_MSK 0x000003ff
+#define RG_TURISMO_TRX_DAC_Q_SET_I_MSK 0xfffffc00
+#define RG_TURISMO_TRX_DAC_Q_SET_SFT 0
+#define RG_TURISMO_TRX_DAC_Q_SET_HI 9
+#define RG_TURISMO_TRX_DAC_Q_SET_SZ 10
+#define RG_TURISMO_TRX_DAC_MAN_Q_EN_MSK 0x00001000
+#define RG_TURISMO_TRX_DAC_MAN_Q_EN_I_MSK 0xffffefff
+#define RG_TURISMO_TRX_DAC_MAN_Q_EN_SFT 12
+#define RG_TURISMO_TRX_DAC_MAN_Q_EN_HI 12
+#define RG_TURISMO_TRX_DAC_MAN_Q_EN_SZ 1
+#define RG_TURISMO_TRX_DAC_I_SET_MSK 0x03ff0000
+#define RG_TURISMO_TRX_DAC_I_SET_I_MSK 0xfc00ffff
+#define RG_TURISMO_TRX_DAC_I_SET_SFT 16
+#define RG_TURISMO_TRX_DAC_I_SET_HI 25
+#define RG_TURISMO_TRX_DAC_I_SET_SZ 10
+#define RG_TURISMO_TRX_DAC_MAN_I_EN_MSK 0x10000000
+#define RG_TURISMO_TRX_DAC_MAN_I_EN_I_MSK 0xefffffff
+#define RG_TURISMO_TRX_DAC_MAN_I_EN_SFT 28
+#define RG_TURISMO_TRX_DAC_MAN_I_EN_HI 28
+#define RG_TURISMO_TRX_DAC_MAN_I_EN_SZ 1
+#define RG_TURISMO_TRX_BW20_HB_COEF_01_MSK 0x00001fff
+#define RG_TURISMO_TRX_BW20_HB_COEF_01_I_MSK 0xffffe000
+#define RG_TURISMO_TRX_BW20_HB_COEF_01_SFT 0
+#define RG_TURISMO_TRX_BW20_HB_COEF_01_HI 12
+#define RG_TURISMO_TRX_BW20_HB_COEF_01_SZ 13
+#define RG_TURISMO_TRX_BW20_HB_COEF_00_MSK 0x1fff0000
+#define RG_TURISMO_TRX_BW20_HB_COEF_00_I_MSK 0xe000ffff
+#define RG_TURISMO_TRX_BW20_HB_COEF_00_SFT 16
+#define RG_TURISMO_TRX_BW20_HB_COEF_00_HI 28
+#define RG_TURISMO_TRX_BW20_HB_COEF_00_SZ 13
+#define RG_TURISMO_TRX_BW20_HB_COEF_03_MSK 0x00001fff
+#define RG_TURISMO_TRX_BW20_HB_COEF_03_I_MSK 0xffffe000
+#define RG_TURISMO_TRX_BW20_HB_COEF_03_SFT 0
+#define RG_TURISMO_TRX_BW20_HB_COEF_03_HI 12
+#define RG_TURISMO_TRX_BW20_HB_COEF_03_SZ 13
+#define RG_TURISMO_TRX_BW20_HB_COEF_02_MSK 0x1fff0000
+#define RG_TURISMO_TRX_BW20_HB_COEF_02_I_MSK 0xe000ffff
+#define RG_TURISMO_TRX_BW20_HB_COEF_02_SFT 16
+#define RG_TURISMO_TRX_BW20_HB_COEF_02_HI 28
+#define RG_TURISMO_TRX_BW20_HB_COEF_02_SZ 13
+#define RG_TURISMO_TRX_BW20_HB_COEF_05_MSK 0x00001fff
+#define RG_TURISMO_TRX_BW20_HB_COEF_05_I_MSK 0xffffe000
+#define RG_TURISMO_TRX_BW20_HB_COEF_05_SFT 0
+#define RG_TURISMO_TRX_BW20_HB_COEF_05_HI 12
+#define RG_TURISMO_TRX_BW20_HB_COEF_05_SZ 13
+#define RG_TURISMO_TRX_BW20_HB_COEF_04_MSK 0x1fff0000
+#define RG_TURISMO_TRX_BW20_HB_COEF_04_I_MSK 0xe000ffff
+#define RG_TURISMO_TRX_BW20_HB_COEF_04_SFT 16
+#define RG_TURISMO_TRX_BW20_HB_COEF_04_HI 28
+#define RG_TURISMO_TRX_BW20_HB_COEF_04_SZ 13
+#define RG_TURISMO_TRX_BW20_HB_COEF_07_MSK 0x00001fff
+#define RG_TURISMO_TRX_BW20_HB_COEF_07_I_MSK 0xffffe000
+#define RG_TURISMO_TRX_BW20_HB_COEF_07_SFT 0
+#define RG_TURISMO_TRX_BW20_HB_COEF_07_HI 12
+#define RG_TURISMO_TRX_BW20_HB_COEF_07_SZ 13
+#define RG_TURISMO_TRX_BW20_HB_COEF_06_MSK 0x1fff0000
+#define RG_TURISMO_TRX_BW20_HB_COEF_06_I_MSK 0xe000ffff
+#define RG_TURISMO_TRX_BW20_HB_COEF_06_SFT 16
+#define RG_TURISMO_TRX_BW20_HB_COEF_06_HI 28
+#define RG_TURISMO_TRX_BW20_HB_COEF_06_SZ 13
+#define RG_TURISMO_TRX_BW20_HB_COEF_09_MSK 0x00001fff
+#define RG_TURISMO_TRX_BW20_HB_COEF_09_I_MSK 0xffffe000
+#define RG_TURISMO_TRX_BW20_HB_COEF_09_SFT 0
+#define RG_TURISMO_TRX_BW20_HB_COEF_09_HI 12
+#define RG_TURISMO_TRX_BW20_HB_COEF_09_SZ 13
+#define RG_TURISMO_TRX_BW20_HB_COEF_08_MSK 0x1fff0000
+#define RG_TURISMO_TRX_BW20_HB_COEF_08_I_MSK 0xe000ffff
+#define RG_TURISMO_TRX_BW20_HB_COEF_08_SFT 16
+#define RG_TURISMO_TRX_BW20_HB_COEF_08_HI 28
+#define RG_TURISMO_TRX_BW20_HB_COEF_08_SZ 13
+#define RG_TURISMO_TRX_BW20_HB_COEF_11_MSK 0x00001fff
+#define RG_TURISMO_TRX_BW20_HB_COEF_11_I_MSK 0xffffe000
+#define RG_TURISMO_TRX_BW20_HB_COEF_11_SFT 0
+#define RG_TURISMO_TRX_BW20_HB_COEF_11_HI 12
+#define RG_TURISMO_TRX_BW20_HB_COEF_11_SZ 13
+#define RG_TURISMO_TRX_BW20_HB_COEF_10_MSK 0x1fff0000
+#define RG_TURISMO_TRX_BW20_HB_COEF_10_I_MSK 0xe000ffff
+#define RG_TURISMO_TRX_BW20_HB_COEF_10_SFT 16
+#define RG_TURISMO_TRX_BW20_HB_COEF_10_HI 28
+#define RG_TURISMO_TRX_BW20_HB_COEF_10_SZ 13
+#define RG_TURISMO_TRX_PHASE_STEP_VALUE_MSK 0x0000ffff
+#define RG_TURISMO_TRX_PHASE_STEP_VALUE_I_MSK 0xffff0000
+#define RG_TURISMO_TRX_PHASE_STEP_VALUE_SFT 0
+#define RG_TURISMO_TRX_PHASE_STEP_VALUE_HI 15
+#define RG_TURISMO_TRX_PHASE_STEP_VALUE_SZ 16
+#define RG_TURISMO_TRX_PHASE_MANUAL_MSK 0x00010000
+#define RG_TURISMO_TRX_PHASE_MANUAL_I_MSK 0xfffeffff
+#define RG_TURISMO_TRX_PHASE_MANUAL_SFT 16
+#define RG_TURISMO_TRX_PHASE_MANUAL_HI 16
+#define RG_TURISMO_TRX_PHASE_MANUAL_SZ 1
+#define RG_TURISMO_TRX_ALPHA_SEL_MSK 0x00300000
+#define RG_TURISMO_TRX_ALPHA_SEL_I_MSK 0xffcfffff
+#define RG_TURISMO_TRX_ALPHA_SEL_SFT 20
+#define RG_TURISMO_TRX_ALPHA_SEL_HI 21
+#define RG_TURISMO_TRX_ALPHA_SEL_SZ 2
+#define RG_TURISMO_TRX_SPECTRUM_BW_MSK 0x03000000
+#define RG_TURISMO_TRX_SPECTRUM_BW_I_MSK 0xfcffffff
+#define RG_TURISMO_TRX_SPECTRUM_BW_SFT 24
+#define RG_TURISMO_TRX_SPECTRUM_BW_HI 25
+#define RG_TURISMO_TRX_SPECTRUM_BW_SZ 2
+#define RG_TURISMO_TRX_SPECTRUM_EN_MSK 0x10000000
+#define RG_TURISMO_TRX_SPECTRUM_EN_I_MSK 0xefffffff
+#define RG_TURISMO_TRX_SPECTRUM_EN_SFT 28
+#define RG_TURISMO_TRX_SPECTRUM_EN_HI 28
+#define RG_TURISMO_TRX_SPECTRUM_EN_SZ 1
+#define RO_TURISMO_TRX_WF_DCCAL_DONE_MSK 0x00010000
+#define RO_TURISMO_TRX_WF_DCCAL_DONE_I_MSK 0xfffeffff
+#define RO_TURISMO_TRX_WF_DCCAL_DONE_SFT 16
+#define RO_TURISMO_TRX_WF_DCCAL_DONE_HI 16
+#define RO_TURISMO_TRX_WF_DCCAL_DONE_SZ 1
+#define RO_TURISMO_TRX_BT_DCCAL_DONE_MSK 0x00020000
+#define RO_TURISMO_TRX_BT_DCCAL_DONE_I_MSK 0xfffdffff
+#define RO_TURISMO_TRX_BT_DCCAL_DONE_SFT 17
+#define RO_TURISMO_TRX_BT_DCCAL_DONE_HI 17
+#define RO_TURISMO_TRX_BT_DCCAL_DONE_SZ 1
+#define RO_TURISMO_TRX_RCCAL_DONE_MSK 0x00040000
+#define RO_TURISMO_TRX_RCCAL_DONE_I_MSK 0xfffbffff
+#define RO_TURISMO_TRX_RCCAL_DONE_SFT 18
+#define RO_TURISMO_TRX_RCCAL_DONE_HI 18
+#define RO_TURISMO_TRX_RCCAL_DONE_SZ 1
+#define RO_TURISMO_TRX_TXDC_DONE_MSK 0x00080000
+#define RO_TURISMO_TRX_TXDC_DONE_I_MSK 0xfff7ffff
+#define RO_TURISMO_TRX_TXDC_DONE_SFT 19
+#define RO_TURISMO_TRX_TXDC_DONE_HI 19
+#define RO_TURISMO_TRX_TXDC_DONE_SZ 1
+#define RO_TURISMO_TRX_TXIQ_DONE_MSK 0x00100000
+#define RO_TURISMO_TRX_TXIQ_DONE_I_MSK 0xffefffff
+#define RO_TURISMO_TRX_TXIQ_DONE_SFT 20
+#define RO_TURISMO_TRX_TXIQ_DONE_HI 20
+#define RO_TURISMO_TRX_TXIQ_DONE_SZ 1
+#define RO_TURISMO_TRX_RXIQ_DONE_MSK 0x00200000
+#define RO_TURISMO_TRX_RXIQ_DONE_I_MSK 0xffdfffff
+#define RO_TURISMO_TRX_RXIQ_DONE_SFT 21
+#define RO_TURISMO_TRX_RXIQ_DONE_HI 21
+#define RO_TURISMO_TRX_RXIQ_DONE_SZ 1
+#define RO_TURISMO_TRX_5G_TXDC_DONE_MSK 0x00400000
+#define RO_TURISMO_TRX_5G_TXDC_DONE_I_MSK 0xffbfffff
+#define RO_TURISMO_TRX_5G_TXDC_DONE_SFT 22
+#define RO_TURISMO_TRX_5G_TXDC_DONE_HI 22
+#define RO_TURISMO_TRX_5G_TXDC_DONE_SZ 1
+#define RO_TURISMO_TRX_5G_TXIQ_DONE_MSK 0x00800000
+#define RO_TURISMO_TRX_5G_TXIQ_DONE_I_MSK 0xff7fffff
+#define RO_TURISMO_TRX_5G_TXIQ_DONE_SFT 23
+#define RO_TURISMO_TRX_5G_TXIQ_DONE_HI 23
+#define RO_TURISMO_TRX_5G_TXIQ_DONE_SZ 1
+#define RO_TURISMO_TRX_5G_RXIQ_DONE_MSK 0x01000000
+#define RO_TURISMO_TRX_5G_RXIQ_DONE_I_MSK 0xfeffffff
+#define RO_TURISMO_TRX_5G_RXIQ_DONE_SFT 24
+#define RO_TURISMO_TRX_5G_RXIQ_DONE_HI 24
+#define RO_TURISMO_TRX_5G_RXIQ_DONE_SZ 1
+#define RO_TURISMO_TRX_5G_DCCAL_DONE_MSK 0x02000000
+#define RO_TURISMO_TRX_5G_DCCAL_DONE_I_MSK 0xfdffffff
+#define RO_TURISMO_TRX_5G_DCCAL_DONE_SFT 25
+#define RO_TURISMO_TRX_5G_DCCAL_DONE_HI 25
+#define RO_TURISMO_TRX_5G_DCCAL_DONE_SZ 1
+#define RO_TURISMO_TRX_PRE_DC_DONE_MSK 0x04000000
+#define RO_TURISMO_TRX_PRE_DC_DONE_I_MSK 0xfbffffff
+#define RO_TURISMO_TRX_PRE_DC_DONE_SFT 26
+#define RO_TURISMO_TRX_PRE_DC_DONE_HI 26
+#define RO_TURISMO_TRX_PRE_DC_DONE_SZ 1
+#define RG_TURISMO_TRX_PHASE_17P5M_MSK 0x0000ffff
+#define RG_TURISMO_TRX_PHASE_17P5M_I_MSK 0xffff0000
+#define RG_TURISMO_TRX_PHASE_17P5M_SFT 0
+#define RG_TURISMO_TRX_PHASE_17P5M_HI 15
+#define RG_TURISMO_TRX_PHASE_17P5M_SZ 16
+#define RG_TURISMO_TRX_PHASE_2P5M_MSK 0xffff0000
+#define RG_TURISMO_TRX_PHASE_2P5M_I_MSK 0x0000ffff
+#define RG_TURISMO_TRX_PHASE_2P5M_SFT 16
+#define RG_TURISMO_TRX_PHASE_2P5M_HI 31
+#define RG_TURISMO_TRX_PHASE_2P5M_SZ 16
+#define RG_TURISMO_TRX_PHASE_RXIQ_1M_MSK 0x0000ffff
+#define RG_TURISMO_TRX_PHASE_RXIQ_1M_I_MSK 0xffff0000
+#define RG_TURISMO_TRX_PHASE_RXIQ_1M_SFT 0
+#define RG_TURISMO_TRX_PHASE_RXIQ_1M_HI 15
+#define RG_TURISMO_TRX_PHASE_RXIQ_1M_SZ 16
+#define RG_TURISMO_TRX_PHASE_1M_MSK 0xffff0000
+#define RG_TURISMO_TRX_PHASE_1M_I_MSK 0x0000ffff
+#define RG_TURISMO_TRX_PHASE_1M_SFT 16
+#define RG_TURISMO_TRX_PHASE_1M_HI 31
+#define RG_TURISMO_TRX_PHASE_1M_SZ 16
+#define RG_TURISMO_TRX_PHASE_PADPD_MSK 0x0000ffff
+#define RG_TURISMO_TRX_PHASE_PADPD_I_MSK 0xffff0000
+#define RG_TURISMO_TRX_PHASE_PADPD_SFT 0
+#define RG_TURISMO_TRX_PHASE_PADPD_HI 15
+#define RG_TURISMO_TRX_PHASE_PADPD_SZ 16
+#define RG_TURISMO_TRX_PHASE_35M_MSK 0xffff0000
+#define RG_TURISMO_TRX_PHASE_35M_I_MSK 0x0000ffff
+#define RG_TURISMO_TRX_PHASE_35M_SFT 16
+#define RG_TURISMO_TRX_PHASE_35M_HI 31
+#define RG_TURISMO_TRX_PHASE_35M_SZ 16
+#define RO_TURISMO_TRX_RX_IQ_THETA_MSK 0x0000001f
+#define RO_TURISMO_TRX_RX_IQ_THETA_I_MSK 0xffffffe0
+#define RO_TURISMO_TRX_RX_IQ_THETA_SFT 0
+#define RO_TURISMO_TRX_RX_IQ_THETA_HI 4
+#define RO_TURISMO_TRX_RX_IQ_THETA_SZ 5
+#define RO_TURISMO_TRX_RX_IQ_ALPHA_MSK 0x00001f00
+#define RO_TURISMO_TRX_RX_IQ_ALPHA_I_MSK 0xffffe0ff
+#define RO_TURISMO_TRX_RX_IQ_ALPHA_SFT 8
+#define RO_TURISMO_TRX_RX_IQ_ALPHA_HI 12
+#define RO_TURISMO_TRX_RX_IQ_ALPHA_SZ 5
+#define RO_TURISMO_TRX_TX_IQ_THETA_MSK 0x001f0000
+#define RO_TURISMO_TRX_TX_IQ_THETA_I_MSK 0xffe0ffff
+#define RO_TURISMO_TRX_TX_IQ_THETA_SFT 16
+#define RO_TURISMO_TRX_TX_IQ_THETA_HI 20
+#define RO_TURISMO_TRX_TX_IQ_THETA_SZ 5
+#define RO_TURISMO_TRX_TX_IQ_ALPHA_MSK 0x1f000000
+#define RO_TURISMO_TRX_TX_IQ_ALPHA_I_MSK 0xe0ffffff
+#define RO_TURISMO_TRX_TX_IQ_ALPHA_SFT 24
+#define RO_TURISMO_TRX_TX_IQ_ALPHA_HI 28
+#define RO_TURISMO_TRX_TX_IQ_ALPHA_SZ 5
+#define RG_TURISMO_TRX_RX_RCCAL_TARG_MSK 0x000003ff
+#define RG_TURISMO_TRX_RX_RCCAL_TARG_I_MSK 0xfffffc00
+#define RG_TURISMO_TRX_RX_RCCAL_TARG_SFT 0
+#define RG_TURISMO_TRX_RX_RCCAL_TARG_HI 9
+#define RG_TURISMO_TRX_RX_RCCAL_TARG_SZ 10
+#define RG_TURISMO_TRX_RX_DC_POLAR_INV_MSK 0x00001000
+#define RG_TURISMO_TRX_RX_DC_POLAR_INV_I_MSK 0xffffefff
+#define RG_TURISMO_TRX_RX_DC_POLAR_INV_SFT 12
+#define RG_TURISMO_TRX_RX_DC_POLAR_INV_HI 12
+#define RG_TURISMO_TRX_RX_DC_POLAR_INV_SZ 1
+#define RG_TURISMO_TRX_RCCAL_POLAR_INV_MSK 0x00002000
+#define RG_TURISMO_TRX_RCCAL_POLAR_INV_I_MSK 0xffffdfff
+#define RG_TURISMO_TRX_RCCAL_POLAR_INV_SFT 13
+#define RG_TURISMO_TRX_RCCAL_POLAR_INV_HI 13
+#define RG_TURISMO_TRX_RCCAL_POLAR_INV_SZ 1
+#define RG_TURISMO_TRX_RX_DC_RESOLUTION_MSK 0x00004000
+#define RG_TURISMO_TRX_RX_DC_RESOLUTION_I_MSK 0xffffbfff
+#define RG_TURISMO_TRX_RX_DC_RESOLUTION_SFT 14
+#define RG_TURISMO_TRX_RX_DC_RESOLUTION_HI 14
+#define RG_TURISMO_TRX_RX_DC_RESOLUTION_SZ 1
+#define RG_TURISMO_TRX_RX_RCCAL_40M_TARG_MSK 0x03ff0000
+#define RG_TURISMO_TRX_RX_RCCAL_40M_TARG_I_MSK 0xfc00ffff
+#define RG_TURISMO_TRX_RX_RCCAL_40M_TARG_SFT 16
+#define RG_TURISMO_TRX_RX_RCCAL_40M_TARG_HI 25
+#define RG_TURISMO_TRX_RX_RCCAL_40M_TARG_SZ 10
+#define RO_TURISMO_TRX_SPECTRUM_IQ_PWR_39_32_MSK 0x000000ff
+#define RO_TURISMO_TRX_SPECTRUM_IQ_PWR_39_32_I_MSK 0xffffff00
+#define RO_TURISMO_TRX_SPECTRUM_IQ_PWR_39_32_SFT 0
+#define RO_TURISMO_TRX_SPECTRUM_IQ_PWR_39_32_HI 7
+#define RO_TURISMO_TRX_SPECTRUM_IQ_PWR_39_32_SZ 8
+#define RG_TURISMO_TRX_SPECTRUM_LO_FIX_MSK 0x00010000
+#define RG_TURISMO_TRX_SPECTRUM_LO_FIX_I_MSK 0xfffeffff
+#define RG_TURISMO_TRX_SPECTRUM_LO_FIX_SFT 16
+#define RG_TURISMO_TRX_SPECTRUM_LO_FIX_HI 16
+#define RG_TURISMO_TRX_SPECTRUM_LO_FIX_SZ 1
+#define RG_TURISMO_TRX_SPECTRUM_PWR_UPDATE_MSK 0x00100000
+#define RG_TURISMO_TRX_SPECTRUM_PWR_UPDATE_I_MSK 0xffefffff
+#define RG_TURISMO_TRX_SPECTRUM_PWR_UPDATE_SFT 20
+#define RG_TURISMO_TRX_SPECTRUM_PWR_UPDATE_HI 20
+#define RG_TURISMO_TRX_SPECTRUM_PWR_UPDATE_SZ 1
+#define RO_TURISMO_TRX_SPECTRUM_IQ_PWR_31_0_MSK 0xffffffff
+#define RO_TURISMO_TRX_SPECTRUM_IQ_PWR_31_0_I_MSK 0x00000000
+#define RO_TURISMO_TRX_SPECTRUM_IQ_PWR_31_0_SFT 0
+#define RO_TURISMO_TRX_SPECTRUM_IQ_PWR_31_0_HI 31
+#define RO_TURISMO_TRX_SPECTRUM_IQ_PWR_31_0_SZ 32
+#define RG_TURISMO_TRX_PROC_DELAY_MSK 0x00000007
+#define RG_TURISMO_TRX_PROC_DELAY_I_MSK 0xfffffff8
+#define RG_TURISMO_TRX_PROC_DELAY_SFT 0
+#define RG_TURISMO_TRX_PROC_DELAY_HI 2
+#define RG_TURISMO_TRX_PROC_DELAY_SZ 3
+#define RG_TURISMO_TRX_PRE_DC_POLA_INV_MSK 0x00000010
+#define RG_TURISMO_TRX_PRE_DC_POLA_INV_I_MSK 0xffffffef
+#define RG_TURISMO_TRX_PRE_DC_POLA_INV_SFT 4
+#define RG_TURISMO_TRX_PRE_DC_POLA_INV_HI 4
+#define RG_TURISMO_TRX_PRE_DC_POLA_INV_SZ 1
+#define RG_TURISMO_TRX_RX_PRE_DC_RESOLUTION_MSK 0x00000020
+#define RG_TURISMO_TRX_RX_PRE_DC_RESOLUTION_I_MSK 0xffffffdf
+#define RG_TURISMO_TRX_RX_PRE_DC_RESOLUTION_SFT 5
+#define RG_TURISMO_TRX_RX_PRE_DC_RESOLUTION_HI 5
+#define RG_TURISMO_TRX_RX_PRE_DC_RESOLUTION_SZ 1
+#define RG_TURISMO_TRX_PRE_DC_AUTO_MSK 0x00000040
+#define RG_TURISMO_TRX_PRE_DC_AUTO_I_MSK 0xffffffbf
+#define RG_TURISMO_TRX_PRE_DC_AUTO_SFT 6
+#define RG_TURISMO_TRX_PRE_DC_AUTO_HI 6
+#define RG_TURISMO_TRX_PRE_DC_AUTO_SZ 1
+#define RG_TURISMO_TRX_HS3W_TX_RF_GAIN_MSK 0x0000007f
+#define RG_TURISMO_TRX_HS3W_TX_RF_GAIN_I_MSK 0xffffff80
+#define RG_TURISMO_TRX_HS3W_TX_RF_GAIN_SFT 0
+#define RG_TURISMO_TRX_HS3W_TX_RF_GAIN_HI 6
+#define RG_TURISMO_TRX_HS3W_TX_RF_GAIN_SZ 7
+#define RG_TURISMO_TRX_HS3W_PGAGC_MSK 0x00000f00
+#define RG_TURISMO_TRX_HS3W_PGAGC_I_MSK 0xfffff0ff
+#define RG_TURISMO_TRX_HS3W_PGAGC_SFT 8
+#define RG_TURISMO_TRX_HS3W_PGAGC_HI 11
+#define RG_TURISMO_TRX_HS3W_PGAGC_SZ 4
+#define RG_TURISMO_TRX_HS3W_RFGC_MSK 0x00003000
+#define RG_TURISMO_TRX_HS3W_RFGC_I_MSK 0xffffcfff
+#define RG_TURISMO_TRX_HS3W_RFGC_SFT 12
+#define RG_TURISMO_TRX_HS3W_RFGC_HI 13
+#define RG_TURISMO_TRX_HS3W_RFGC_SZ 2
+#define RG_TURISMO_TRX_HS3W_RXAGC_MSK 0x00004000
+#define RG_TURISMO_TRX_HS3W_RXAGC_I_MSK 0xffffbfff
+#define RG_TURISMO_TRX_HS3W_RXAGC_SFT 14
+#define RG_TURISMO_TRX_HS3W_RXAGC_HI 14
+#define RG_TURISMO_TRX_HS3W_RXAGC_SZ 1
+#define RG_TURISMO_TRX_HS3W_RF_PHY_MODE_MSK 0x00070000
+#define RG_TURISMO_TRX_HS3W_RF_PHY_MODE_I_MSK 0xfff8ffff
+#define RG_TURISMO_TRX_HS3W_RF_PHY_MODE_SFT 16
+#define RG_TURISMO_TRX_HS3W_RF_PHY_MODE_HI 18
+#define RG_TURISMO_TRX_HS3W_RF_PHY_MODE_SZ 3
+#define RG_TURISMO_TRX_HS3W_MANUAL_MSK 0x00100000
+#define RG_TURISMO_TRX_HS3W_MANUAL_I_MSK 0xffefffff
+#define RG_TURISMO_TRX_HS3W_MANUAL_SFT 20
+#define RG_TURISMO_TRX_HS3W_MANUAL_HI 20
+#define RG_TURISMO_TRX_HS3W_MANUAL_SZ 1
+#define RG_TURISMO_TRX_HS3W_COMM_DATA_MSK 0x07000000
+#define RG_TURISMO_TRX_HS3W_COMM_DATA_I_MSK 0xf8ffffff
+#define RG_TURISMO_TRX_HS3W_COMM_DATA_SFT 24
+#define RG_TURISMO_TRX_HS3W_COMM_DATA_HI 26
+#define RG_TURISMO_TRX_HS3W_COMM_DATA_SZ 3
+#define RG_TURISMO_TRX_HS3W_START_SENT_MSK 0x10000000
+#define RG_TURISMO_TRX_HS3W_START_SENT_I_MSK 0xefffffff
+#define RG_TURISMO_TRX_HS3W_START_SENT_SFT 28
+#define RG_TURISMO_TRX_HS3W_START_SENT_HI 28
+#define RG_TURISMO_TRX_HS3W_START_SENT_SZ 1
+#define RG_TURISMO_TRX_HS3W_SX_RFCTRL_CH_INT_10_8_MSK 0x00000007
+#define RG_TURISMO_TRX_HS3W_SX_RFCTRL_CH_INT_10_8_I_MSK 0xfffffff8
+#define RG_TURISMO_TRX_HS3W_SX_RFCTRL_CH_INT_10_8_SFT 0
+#define RG_TURISMO_TRX_HS3W_SX_RFCTRL_CH_INT_10_8_HI 2
+#define RG_TURISMO_TRX_HS3W_SX_RFCTRL_CH_INT_10_8_SZ 3
+#define RG_TURISMO_TRX_HS3W_SX_RFCH_MAP_EN_INT_MSK 0x00000010
+#define RG_TURISMO_TRX_HS3W_SX_RFCH_MAP_EN_INT_I_MSK 0xffffffef
+#define RG_TURISMO_TRX_HS3W_SX_RFCH_MAP_EN_INT_SFT 4
+#define RG_TURISMO_TRX_HS3W_SX_RFCH_MAP_EN_INT_HI 4
+#define RG_TURISMO_TRX_HS3W_SX_RFCH_MAP_EN_INT_SZ 1
+#define RG_TURISMO_TRX_HS3W_SX_CHANNEL_INT_MSK 0x0007f800
+#define RG_TURISMO_TRX_HS3W_SX_CHANNEL_INT_I_MSK 0xfff807ff
+#define RG_TURISMO_TRX_HS3W_SX_CHANNEL_INT_SFT 11
+#define RG_TURISMO_TRX_HS3W_SX_CHANNEL_INT_HI 18
+#define RG_TURISMO_TRX_HS3W_SX_CHANNEL_INT_SZ 8
+#define RG_TURISMO_TRX_HS3W_SX_RFCTRL_F_INT_MSK 0x00ffffff
+#define RG_TURISMO_TRX_HS3W_SX_RFCTRL_F_INT_I_MSK 0xff000000
+#define RG_TURISMO_TRX_HS3W_SX_RFCTRL_F_INT_SFT 0
+#define RG_TURISMO_TRX_HS3W_SX_RFCTRL_F_INT_HI 23
+#define RG_TURISMO_TRX_HS3W_SX_RFCTRL_F_INT_SZ 24
+#define RG_TURISMO_TRX_HS3W_SX_RFCTRL_CH_INT_7_0_MSK 0xff000000
+#define RG_TURISMO_TRX_HS3W_SX_RFCTRL_CH_INT_7_0_I_MSK 0x00ffffff
+#define RG_TURISMO_TRX_HS3W_SX_RFCTRL_CH_INT_7_0_SFT 24
+#define RG_TURISMO_TRX_HS3W_SX_RFCTRL_CH_INT_7_0_HI 31
+#define RG_TURISMO_TRX_HS3W_SX_RFCTRL_CH_INT_7_0_SZ 8
+#define RG_TURISMO_TRX_MODE_BY_HS_3WIRE_MSK 0x00000001
+#define RG_TURISMO_TRX_MODE_BY_HS_3WIRE_I_MSK 0xfffffffe
+#define RG_TURISMO_TRX_MODE_BY_HS_3WIRE_SFT 0
+#define RG_TURISMO_TRX_MODE_BY_HS_3WIRE_HI 0
+#define RG_TURISMO_TRX_MODE_BY_HS_3WIRE_SZ 1
+#define RO_TURISMO_TRX_DC_CAL_Q_MSK 0x0000007f
+#define RO_TURISMO_TRX_DC_CAL_Q_I_MSK 0xffffff80
+#define RO_TURISMO_TRX_DC_CAL_Q_SFT 0
+#define RO_TURISMO_TRX_DC_CAL_Q_HI 6
+#define RO_TURISMO_TRX_DC_CAL_Q_SZ 7
+#define RO_TURISMO_TRX_DC_CAL_I_MSK 0x007f0000
+#define RO_TURISMO_TRX_DC_CAL_I_I_MSK 0xff80ffff
+#define RO_TURISMO_TRX_DC_CAL_I_SFT 16
+#define RO_TURISMO_TRX_DC_CAL_I_HI 22
+#define RO_TURISMO_TRX_DC_CAL_I_SZ 7
+#define RG_TURISMO_TRX_XO_LDO_LEVEL_MSK 0x00000007
+#define RG_TURISMO_TRX_XO_LDO_LEVEL_I_MSK 0xfffffff8
+#define RG_TURISMO_TRX_XO_LDO_LEVEL_SFT 0
+#define RG_TURISMO_TRX_XO_LDO_LEVEL_HI 2
+#define RG_TURISMO_TRX_XO_LDO_LEVEL_SZ 3
+#define RG_TURISMO_TRX_EN_LDO_XO_IQUP_MSK 0x00000010
+#define RG_TURISMO_TRX_EN_LDO_XO_IQUP_I_MSK 0xffffffef
+#define RG_TURISMO_TRX_EN_LDO_XO_IQUP_SFT 4
+#define RG_TURISMO_TRX_EN_LDO_XO_IQUP_HI 4
+#define RG_TURISMO_TRX_EN_LDO_XO_IQUP_SZ 1
+#define RG_TURISMO_TRX_EN_LDO_XO_BYP_MSK 0x00000020
+#define RG_TURISMO_TRX_EN_LDO_XO_BYP_I_MSK 0xffffffdf
+#define RG_TURISMO_TRX_EN_LDO_XO_BYP_SFT 5
+#define RG_TURISMO_TRX_EN_LDO_XO_BYP_HI 5
+#define RG_TURISMO_TRX_EN_LDO_XO_BYP_SZ 1
+#define RG_TURISMO_TRX_EN_DLDO_BYP_MSK 0x00000040
+#define RG_TURISMO_TRX_EN_DLDO_BYP_I_MSK 0xffffffbf
+#define RG_TURISMO_TRX_EN_DLDO_BYP_SFT 6
+#define RG_TURISMO_TRX_EN_DLDO_BYP_HI 6
+#define RG_TURISMO_TRX_EN_DLDO_BYP_SZ 1
+#define RG_TURISMO_TRX_XO_CBANKI_MSK 0x0001ff00
+#define RG_TURISMO_TRX_XO_CBANKI_I_MSK 0xfffe00ff
+#define RG_TURISMO_TRX_XO_CBANKI_SFT 8
+#define RG_TURISMO_TRX_XO_CBANKI_HI 16
+#define RG_TURISMO_TRX_XO_CBANKI_SZ 9
+#define RG_TURISMO_TRX_XO_CBANKO_MSK 0x03fe0000
+#define RG_TURISMO_TRX_XO_CBANKO_I_MSK 0xfc01ffff
+#define RG_TURISMO_TRX_XO_CBANKO_SFT 17
+#define RG_TURISMO_TRX_XO_CBANKO_HI 25
+#define RG_TURISMO_TRX_XO_CBANKO_SZ 9
+#define RG_TURISMO_TRX_EN_FDB_MSK 0x04000000
+#define RG_TURISMO_TRX_EN_FDB_I_MSK 0xfbffffff
+#define RG_TURISMO_TRX_EN_FDB_SFT 26
+#define RG_TURISMO_TRX_EN_FDB_HI 26
+#define RG_TURISMO_TRX_EN_FDB_SZ 1
+#define RG_TURISMO_TRX_FDB_BYPASS_MSK 0x08000000
+#define RG_TURISMO_TRX_FDB_BYPASS_I_MSK 0xf7ffffff
+#define RG_TURISMO_TRX_FDB_BYPASS_SFT 27
+#define RG_TURISMO_TRX_FDB_BYPASS_HI 27
+#define RG_TURISMO_TRX_FDB_BYPASS_SZ 1
+#define RG_TURISMO_TRX_FDB_DUTY_LTH_MSK 0x30000000
+#define RG_TURISMO_TRX_FDB_DUTY_LTH_I_MSK 0xcfffffff
+#define RG_TURISMO_TRX_FDB_DUTY_LTH_SFT 28
+#define RG_TURISMO_TRX_FDB_DUTY_LTH_HI 29
+#define RG_TURISMO_TRX_FDB_DUTY_LTH_SZ 2
+#define RG_TURISMO_TRX_EN_XOTEST_MSK 0x40000000
+#define RG_TURISMO_TRX_EN_XOTEST_I_MSK 0xbfffffff
+#define RG_TURISMO_TRX_EN_XOTEST_SFT 30
+#define RG_TURISMO_TRX_EN_XOTEST_HI 30
+#define RG_TURISMO_TRX_EN_XOTEST_SZ 1
+#define RG_TURISMO_TRX_EN_FDB_DCC_MUAL_MSK 0x00000001
+#define RG_TURISMO_TRX_EN_FDB_DCC_MUAL_I_MSK 0xfffffffe
+#define RG_TURISMO_TRX_EN_FDB_DCC_MUAL_SFT 0
+#define RG_TURISMO_TRX_EN_FDB_DCC_MUAL_HI 0
+#define RG_TURISMO_TRX_EN_FDB_DCC_MUAL_SZ 1
+#define RG_TURISMO_TRX_EN_FDB_DELAYC_MUAL_MSK 0x00000002
+#define RG_TURISMO_TRX_EN_FDB_DELAYC_MUAL_I_MSK 0xfffffffd
+#define RG_TURISMO_TRX_EN_FDB_DELAYC_MUAL_SFT 1
+#define RG_TURISMO_TRX_EN_FDB_DELAYC_MUAL_HI 1
+#define RG_TURISMO_TRX_EN_FDB_DELAYC_MUAL_SZ 1
+#define RG_TURISMO_TRX_EN_FDB_DELAYF_MUAL_MSK 0x00000004
+#define RG_TURISMO_TRX_EN_FDB_DELAYF_MUAL_I_MSK 0xfffffffb
+#define RG_TURISMO_TRX_EN_FDB_DELAYF_MUAL_SFT 2
+#define RG_TURISMO_TRX_EN_FDB_DELAYF_MUAL_HI 2
+#define RG_TURISMO_TRX_EN_FDB_DELAYF_MUAL_SZ 1
+#define RG_TURISMO_TRX_EN_FDB_PHASESWAP_MUAL_MSK 0x00000008
+#define RG_TURISMO_TRX_EN_FDB_PHASESWAP_MUAL_I_MSK 0xfffffff7
+#define RG_TURISMO_TRX_EN_FDB_PHASESWAP_MUAL_SFT 3
+#define RG_TURISMO_TRX_EN_FDB_PHASESWAP_MUAL_HI 3
+#define RG_TURISMO_TRX_EN_FDB_PHASESWAP_MUAL_SZ 1
+#define RG_TURISMO_TRX_FDB_PHASESWAP_MUAL_MSK 0x00000010
+#define RG_TURISMO_TRX_FDB_PHASESWAP_MUAL_I_MSK 0xffffffef
+#define RG_TURISMO_TRX_FDB_PHASESWAP_MUAL_SFT 4
+#define RG_TURISMO_TRX_FDB_PHASESWAP_MUAL_HI 4
+#define RG_TURISMO_TRX_FDB_PHASESWAP_MUAL_SZ 1
+#define RG_TURISMO_TRX_FDB_CDELAY_MUAL_MSK 0x00000f00
+#define RG_TURISMO_TRX_FDB_CDELAY_MUAL_I_MSK 0xfffff0ff
+#define RG_TURISMO_TRX_FDB_CDELAY_MUAL_SFT 8
+#define RG_TURISMO_TRX_FDB_CDELAY_MUAL_HI 11
+#define RG_TURISMO_TRX_FDB_CDELAY_MUAL_SZ 4
+#define RG_TURISMO_TRX_FDB_FDELAY_MUAL_MSK 0x0000f000
+#define RG_TURISMO_TRX_FDB_FDELAY_MUAL_I_MSK 0xffff0fff
+#define RG_TURISMO_TRX_FDB_FDELAY_MUAL_SFT 12
+#define RG_TURISMO_TRX_FDB_FDELAY_MUAL_HI 15
+#define RG_TURISMO_TRX_FDB_FDELAY_MUAL_SZ 4
+#define RG_TURISMO_TRX_XO_TIMMER_MSK 0x003f0000
+#define RG_TURISMO_TRX_XO_TIMMER_I_MSK 0xffc0ffff
+#define RG_TURISMO_TRX_XO_TIMMER_SFT 16
+#define RG_TURISMO_TRX_XO_TIMMER_HI 21
+#define RG_TURISMO_TRX_XO_TIMMER_SZ 6
+#define RG_TURISMO_TRX_DPL_SETTLING_TIMMER_MSK 0x00c00000
+#define RG_TURISMO_TRX_DPL_SETTLING_TIMMER_I_MSK 0xff3fffff
+#define RG_TURISMO_TRX_DPL_SETTLING_TIMMER_SFT 22
+#define RG_TURISMO_TRX_DPL_SETTLING_TIMMER_HI 23
+#define RG_TURISMO_TRX_DPL_SETTLING_TIMMER_SZ 2
+#define RG_TURISMO_TRX_FDB_RDELAYF_MSK 0x03000000
+#define RG_TURISMO_TRX_FDB_RDELAYF_I_MSK 0xfcffffff
+#define RG_TURISMO_TRX_FDB_RDELAYF_SFT 24
+#define RG_TURISMO_TRX_FDB_RDELAYF_HI 25
+#define RG_TURISMO_TRX_FDB_RDELAYF_SZ 2
+#define RG_TURISMO_TRX_FDB_RDELAYS_MSK 0x0c000000
+#define RG_TURISMO_TRX_FDB_RDELAYS_I_MSK 0xf3ffffff
+#define RG_TURISMO_TRX_FDB_RDELAYS_SFT 26
+#define RG_TURISMO_TRX_FDB_RDELAYS_HI 27
+#define RG_TURISMO_TRX_FDB_RDELAYS_SZ 2
+#define RG_TURISMO_TRX_FDB_RECAL_TIMMER_MSK 0x30000000
+#define RG_TURISMO_TRX_FDB_RECAL_TIMMER_I_MSK 0xcfffffff
+#define RG_TURISMO_TRX_FDB_RECAL_TIMMER_SFT 28
+#define RG_TURISMO_TRX_FDB_RECAL_TIMMER_HI 29
+#define RG_TURISMO_TRX_FDB_RECAL_TIMMER_SZ 2
+#define RG_TURISMO_TRX_EN_FDB_RECAL_MSK 0x40000000
+#define RG_TURISMO_TRX_EN_FDB_RECAL_I_MSK 0xbfffffff
+#define RG_TURISMO_TRX_EN_FDB_RECAL_SFT 30
+#define RG_TURISMO_TRX_EN_FDB_RECAL_HI 30
+#define RG_TURISMO_TRX_EN_FDB_RECAL_SZ 1
+#define RG_TURISMO_TRX_LOAD_RFTABLE_RDY_MSK 0x80000000
+#define RG_TURISMO_TRX_LOAD_RFTABLE_RDY_I_MSK 0x7fffffff
+#define RG_TURISMO_TRX_LOAD_RFTABLE_RDY_SFT 31
+#define RG_TURISMO_TRX_LOAD_RFTABLE_RDY_HI 31
+#define RG_TURISMO_TRX_LOAD_RFTABLE_RDY_SZ 1
+#define RG_TURISMO_TRX_DCDC_MODE_MSK 0x00000001
+#define RG_TURISMO_TRX_DCDC_MODE_I_MSK 0xfffffffe
+#define RG_TURISMO_TRX_DCDC_MODE_SFT 0
+#define RG_TURISMO_TRX_DCDC_MODE_HI 0
+#define RG_TURISMO_TRX_DCDC_MODE_SZ 1
+#define RG_TURISMO_TRX_DLDO_LEVEL_MSK 0x0000000e
+#define RG_TURISMO_TRX_DLDO_LEVEL_I_MSK 0xfffffff1
+#define RG_TURISMO_TRX_DLDO_LEVEL_SFT 1
+#define RG_TURISMO_TRX_DLDO_LEVEL_HI 3
+#define RG_TURISMO_TRX_DLDO_LEVEL_SZ 3
+#define RG_TURISMO_TRX_BUCK_LEVEL_MSK 0x000000f0
+#define RG_TURISMO_TRX_BUCK_LEVEL_I_MSK 0xffffff0f
+#define RG_TURISMO_TRX_BUCK_LEVEL_SFT 4
+#define RG_TURISMO_TRX_BUCK_LEVEL_HI 7
+#define RG_TURISMO_TRX_BUCK_LEVEL_SZ 4
+#define RG_TURISMO_TRX_DLDO_BOOST_IQ_MSK 0x00000100
+#define RG_TURISMO_TRX_DLDO_BOOST_IQ_I_MSK 0xfffffeff
+#define RG_TURISMO_TRX_DLDO_BOOST_IQ_SFT 8
+#define RG_TURISMO_TRX_DLDO_BOOST_IQ_HI 8
+#define RG_TURISMO_TRX_DLDO_BOOST_IQ_SZ 1
+#define RG_TURISMO_TRX_BUCK_EN_PSM_MSK 0x00000200
+#define RG_TURISMO_TRX_BUCK_EN_PSM_I_MSK 0xfffffdff
+#define RG_TURISMO_TRX_BUCK_EN_PSM_SFT 9
+#define RG_TURISMO_TRX_BUCK_EN_PSM_HI 9
+#define RG_TURISMO_TRX_BUCK_EN_PSM_SZ 1
+#define RG_TURISMO_TRX_BUCK_PSM_VTH_MSK 0x00000400
+#define RG_TURISMO_TRX_BUCK_PSM_VTH_I_MSK 0xfffffbff
+#define RG_TURISMO_TRX_BUCK_PSM_VTH_SFT 10
+#define RG_TURISMO_TRX_BUCK_PSM_VTH_HI 10
+#define RG_TURISMO_TRX_BUCK_PSM_VTH_SZ 1
+#define RG_TURISMO_TRX_BUCK_VREF_SEL_MSK 0x00000800
+#define RG_TURISMO_TRX_BUCK_VREF_SEL_I_MSK 0xfffff7ff
+#define RG_TURISMO_TRX_BUCK_VREF_SEL_SFT 11
+#define RG_TURISMO_TRX_BUCK_VREF_SEL_HI 11
+#define RG_TURISMO_TRX_BUCK_VREF_SEL_SZ 1
+#define RG_TURISMO_TRX_LDO_LEVEL_EFUSE_MSK 0x00007000
+#define RG_TURISMO_TRX_LDO_LEVEL_EFUSE_I_MSK 0xffff8fff
+#define RG_TURISMO_TRX_LDO_LEVEL_EFUSE_SFT 12
+#define RG_TURISMO_TRX_LDO_LEVEL_EFUSE_HI 14
+#define RG_TURISMO_TRX_LDO_LEVEL_EFUSE_SZ 3
+#define RG_TURISMO_TRX_EN_LDO_EFUSE_MSK 0x00010000
+#define RG_TURISMO_TRX_EN_LDO_EFUSE_I_MSK 0xfffeffff
+#define RG_TURISMO_TRX_EN_LDO_EFUSE_SFT 16
+#define RG_TURISMO_TRX_EN_LDO_EFUSE_HI 16
+#define RG_TURISMO_TRX_EN_LDO_EFUSE_SZ 1
+#define RG_TURISMO_TRX_DCDC_PULLLOW_CON_MSK 0x00040000
+#define RG_TURISMO_TRX_DCDC_PULLLOW_CON_I_MSK 0xfffbffff
+#define RG_TURISMO_TRX_DCDC_PULLLOW_CON_SFT 18
+#define RG_TURISMO_TRX_DCDC_PULLLOW_CON_HI 18
+#define RG_TURISMO_TRX_DCDC_PULLLOW_CON_SZ 1
+#define RG_TURISMO_TRX_DCDC_RES2_CON_MSK 0x00080000
+#define RG_TURISMO_TRX_DCDC_RES2_CON_I_MSK 0xfff7ffff
+#define RG_TURISMO_TRX_DCDC_RES2_CON_SFT 19
+#define RG_TURISMO_TRX_DCDC_RES2_CON_HI 19
+#define RG_TURISMO_TRX_DCDC_RES2_CON_SZ 1
+#define RG_TURISMO_TRX_DCDC_RES_CON_MSK 0x00100000
+#define RG_TURISMO_TRX_DCDC_RES_CON_I_MSK 0xffefffff
+#define RG_TURISMO_TRX_DCDC_RES_CON_SFT 20
+#define RG_TURISMO_TRX_DCDC_RES_CON_HI 20
+#define RG_TURISMO_TRX_DCDC_RES_CON_SZ 1
+#define RG_TURISMO_TRX_RTC_RS1_MSK 0x00200000
+#define RG_TURISMO_TRX_RTC_RS1_I_MSK 0xffdfffff
+#define RG_TURISMO_TRX_RTC_RS1_SFT 21
+#define RG_TURISMO_TRX_RTC_RS1_HI 21
+#define RG_TURISMO_TRX_RTC_RS1_SZ 1
+#define RG_TURISMO_TRX_RTC_RS2_MSK 0x00400000
+#define RG_TURISMO_TRX_RTC_RS2_I_MSK 0xffbfffff
+#define RG_TURISMO_TRX_RTC_RS2_SFT 22
+#define RG_TURISMO_TRX_RTC_RS2_HI 22
+#define RG_TURISMO_TRX_RTC_RS2_SZ 1
+#define RG_TURISMO_TRX_DCDC_CLK_MSK 0x0f000000
+#define RG_TURISMO_TRX_DCDC_CLK_I_MSK 0xf0ffffff
+#define RG_TURISMO_TRX_DCDC_CLK_SFT 24
+#define RG_TURISMO_TRX_DCDC_CLK_HI 27
+#define RG_TURISMO_TRX_DCDC_CLK_SZ 4
+#define RG_TURISMO_TRX_BUCK_RCZERO_MSK 0x10000000
+#define RG_TURISMO_TRX_BUCK_RCZERO_I_MSK 0xefffffff
+#define RG_TURISMO_TRX_BUCK_RCZERO_SFT 28
+#define RG_TURISMO_TRX_BUCK_RCZERO_HI 28
+#define RG_TURISMO_TRX_BUCK_RCZERO_SZ 1
+#define RG_TURISMO_TRX_BUCK_SLOP_MSK 0x60000000
+#define RG_TURISMO_TRX_BUCK_SLOP_I_MSK 0x9fffffff
+#define RG_TURISMO_TRX_BUCK_SLOP_SFT 29
+#define RG_TURISMO_TRX_BUCK_SLOP_HI 30
+#define RG_TURISMO_TRX_BUCK_SLOP_SZ 2
+#define RG_TURISMO_TRX_RTC_OFFSET_MSK 0x000000ff
+#define RG_TURISMO_TRX_RTC_OFFSET_I_MSK 0xffffff00
+#define RG_TURISMO_TRX_RTC_OFFSET_SFT 0
+#define RG_TURISMO_TRX_RTC_OFFSET_HI 7
+#define RG_TURISMO_TRX_RTC_OFFSET_SZ 8
+#define RG_TURISMO_TRX_RTC_CAL_TARGET_COUNT_MSK 0x000fff00
+#define RG_TURISMO_TRX_RTC_CAL_TARGET_COUNT_I_MSK 0xfff000ff
+#define RG_TURISMO_TRX_RTC_CAL_TARGET_COUNT_SFT 8
+#define RG_TURISMO_TRX_RTC_CAL_TARGET_COUNT_HI 19
+#define RG_TURISMO_TRX_RTC_CAL_TARGET_COUNT_SZ 12
+#define RG_TURISMO_TRX_RTC_OSC_RES_SW_MANUAL_MSK 0x3ff00000
+#define RG_TURISMO_TRX_RTC_OSC_RES_SW_MANUAL_I_MSK 0xc00fffff
+#define RG_TURISMO_TRX_RTC_OSC_RES_SW_MANUAL_SFT 20
+#define RG_TURISMO_TRX_RTC_OSC_RES_SW_MANUAL_HI 29
+#define RG_TURISMO_TRX_RTC_OSC_RES_SW_MANUAL_SZ 10
+#define RG_TURISMO_TRX_RTC_CAL_MODE_MSK 0x40000000
+#define RG_TURISMO_TRX_RTC_CAL_MODE_I_MSK 0xbfffffff
+#define RG_TURISMO_TRX_RTC_CAL_MODE_SFT 30
+#define RG_TURISMO_TRX_RTC_CAL_MODE_HI 30
+#define RG_TURISMO_TRX_RTC_CAL_MODE_SZ 1
+#define RG_TURISMO_TRX_SEL_DPLL_CLK_MSK 0x80000000
+#define RG_TURISMO_TRX_SEL_DPLL_CLK_I_MSK 0x7fffffff
+#define RG_TURISMO_TRX_SEL_DPLL_CLK_SFT 31
+#define RG_TURISMO_TRX_SEL_DPLL_CLK_HI 31
+#define RG_TURISMO_TRX_SEL_DPLL_CLK_SZ 1
+#define RG_TURISMO_TRX_RTC_OSC_RES_SW_MANUAL_EN_MSK 0x00000001
+#define RG_TURISMO_TRX_RTC_OSC_RES_SW_MANUAL_EN_I_MSK 0xfffffffe
+#define RG_TURISMO_TRX_RTC_OSC_RES_SW_MANUAL_EN_SFT 0
+#define RG_TURISMO_TRX_RTC_OSC_RES_SW_MANUAL_EN_HI 0
+#define RG_TURISMO_TRX_RTC_OSC_RES_SW_MANUAL_EN_SZ 1
+#define RG_TURISMO_TRX_EN_RTC_CAL_MSK 0x00000002
+#define RG_TURISMO_TRX_EN_RTC_CAL_I_MSK 0xfffffffd
+#define RG_TURISMO_TRX_EN_RTC_CAL_SFT 1
+#define RG_TURISMO_TRX_EN_RTC_CAL_HI 1
+#define RG_TURISMO_TRX_EN_RTC_CAL_SZ 1
+#define RO_TURISMO_TRX_FDB_CDELAY_MSK 0x0000000f
+#define RO_TURISMO_TRX_FDB_CDELAY_I_MSK 0xfffffff0
+#define RO_TURISMO_TRX_FDB_CDELAY_SFT 0
+#define RO_TURISMO_TRX_FDB_CDELAY_HI 3
+#define RO_TURISMO_TRX_FDB_CDELAY_SZ 4
+#define RO_TURISMO_TRX_FDB_FDELAY_MSK 0x000000f0
+#define RO_TURISMO_TRX_FDB_FDELAY_I_MSK 0xffffff0f
+#define RO_TURISMO_TRX_FDB_FDELAY_SFT 4
+#define RO_TURISMO_TRX_FDB_FDELAY_HI 7
+#define RO_TURISMO_TRX_FDB_FDELAY_SZ 4
+#define RO_TURISMO_TRX_FDB_PHASESWAP_MSK 0x00000100
+#define RO_TURISMO_TRX_FDB_PHASESWAP_I_MSK 0xfffffeff
+#define RO_TURISMO_TRX_FDB_PHASESWAP_SFT 8
+#define RO_TURISMO_TRX_FDB_PHASESWAP_HI 8
+#define RO_TURISMO_TRX_FDB_PHASESWAP_SZ 1
+#define RO_TURISMO_TRX_XO_RDY_MSK 0x00000200
+#define RO_TURISMO_TRX_XO_RDY_I_MSK 0xfffffdff
+#define RO_TURISMO_TRX_XO_RDY_SFT 9
+#define RO_TURISMO_TRX_XO_RDY_HI 9
+#define RO_TURISMO_TRX_XO_RDY_SZ 1
+#define RO_TURISMO_TRX_RTC_OSC_CAL_RES_RDY_MSK 0x00000400
+#define RO_TURISMO_TRX_RTC_OSC_CAL_RES_RDY_I_MSK 0xfffffbff
+#define RO_TURISMO_TRX_RTC_OSC_CAL_RES_RDY_SFT 10
+#define RO_TURISMO_TRX_RTC_OSC_CAL_RES_RDY_HI 10
+#define RO_TURISMO_TRX_RTC_OSC_CAL_RES_RDY_SZ 1
+#define RO_TURISMO_TRX_RTC_OSC_RES_SW_MSK 0x001ff800
+#define RO_TURISMO_TRX_RTC_OSC_RES_SW_I_MSK 0xffe007ff
+#define RO_TURISMO_TRX_RTC_OSC_RES_SW_SFT 11
+#define RO_TURISMO_TRX_RTC_OSC_RES_SW_HI 20
+#define RO_TURISMO_TRX_RTC_OSC_RES_SW_SZ 10
+#define RG_TURISMO_TRX_PMU_ENTER_SLEEP_MODE_MSK 0x00000001
+#define RG_TURISMO_TRX_PMU_ENTER_SLEEP_MODE_I_MSK 0xfffffffe
+#define RG_TURISMO_TRX_PMU_ENTER_SLEEP_MODE_SFT 0
+#define RG_TURISMO_TRX_PMU_ENTER_SLEEP_MODE_HI 0
+#define RG_TURISMO_TRX_PMU_ENTER_SLEEP_MODE_SZ 1
+#define RG_TURISMO_TRX_SLEEP_METHOD_MSK 0x00000002
+#define RG_TURISMO_TRX_SLEEP_METHOD_I_MSK 0xfffffffd
+#define RG_TURISMO_TRX_SLEEP_METHOD_SFT 1
+#define RG_TURISMO_TRX_SLEEP_METHOD_HI 1
+#define RG_TURISMO_TRX_SLEEP_METHOD_SZ 1
+#define RG_TURISMO_TRX_INT_PMU_MASK_MSK 0x00000004
+#define RG_TURISMO_TRX_INT_PMU_MASK_I_MSK 0xfffffffb
+#define RG_TURISMO_TRX_INT_PMU_MASK_SFT 2
+#define RG_TURISMO_TRX_INT_PMU_MASK_HI 2
+#define RG_TURISMO_TRX_INT_PMU_MASK_SZ 1
+#define RG_TURISMO_TRX_SLEEP_WAKE_CNT_MSK 0xffffffff
+#define RG_TURISMO_TRX_SLEEP_WAKE_CNT_I_MSK 0x00000000
+#define RG_TURISMO_TRX_SLEEP_WAKE_CNT_SFT 0
+#define RG_TURISMO_TRX_SLEEP_WAKE_CNT_HI 31
+#define RG_TURISMO_TRX_SLEEP_WAKE_CNT_SZ 32
+#define RG_TURISMO_TRX_SEC_CNT_VALUE_MSK 0x00007fff
+#define RG_TURISMO_TRX_SEC_CNT_VALUE_I_MSK 0xffff8000
+#define RG_TURISMO_TRX_SEC_CNT_VALUE_SFT 0
+#define RG_TURISMO_TRX_SEC_CNT_VALUE_HI 14
+#define RG_TURISMO_TRX_SEC_CNT_VALUE_SZ 15
+#define RG_TURISMO_TRX_RTC_EN_MSK 0x00008000
+#define RG_TURISMO_TRX_RTC_EN_I_MSK 0xffff7fff
+#define RG_TURISMO_TRX_RTC_EN_SFT 15
+#define RG_TURISMO_TRX_RTC_EN_HI 15
+#define RG_TURISMO_TRX_RTC_EN_SZ 1
+#define RO_TURISMO_TRX_RTC_TICK_CNT_MSK 0x7fff0000
+#define RO_TURISMO_TRX_RTC_TICK_CNT_I_MSK 0x8000ffff
+#define RO_TURISMO_TRX_RTC_TICK_CNT_SFT 16
+#define RO_TURISMO_TRX_RTC_TICK_CNT_HI 30
+#define RO_TURISMO_TRX_RTC_TICK_CNT_SZ 15
+#define RG_TURISMO_TRX_RTC_INT_SEC_MASK_MSK 0x00000001
+#define RG_TURISMO_TRX_RTC_INT_SEC_MASK_I_MSK 0xfffffffe
+#define RG_TURISMO_TRX_RTC_INT_SEC_MASK_SFT 0
+#define RG_TURISMO_TRX_RTC_INT_SEC_MASK_HI 0
+#define RG_TURISMO_TRX_RTC_INT_SEC_MASK_SZ 1
+#define RG_TURISMO_TRX_RTC_INT_ALARM_MASK_MSK 0x00000002
+#define RG_TURISMO_TRX_RTC_INT_ALARM_MASK_I_MSK 0xfffffffd
+#define RG_TURISMO_TRX_RTC_INT_ALARM_MASK_SFT 1
+#define RG_TURISMO_TRX_RTC_INT_ALARM_MASK_HI 1
+#define RG_TURISMO_TRX_RTC_INT_ALARM_MASK_SZ 1
+#define RO_TURISMO_TRX_PMU_WAKE_TRIG_EVENT_MSK 0x00007000
+#define RO_TURISMO_TRX_PMU_WAKE_TRIG_EVENT_I_MSK 0xffff8fff
+#define RO_TURISMO_TRX_PMU_WAKE_TRIG_EVENT_SFT 12
+#define RO_TURISMO_TRX_PMU_WAKE_TRIG_EVENT_HI 14
+#define RO_TURISMO_TRX_PMU_WAKE_TRIG_EVENT_SZ 3
+#define RO_TURISMO_TRX_RTC_INT_SEC_MSK 0x00010000
+#define RO_TURISMO_TRX_RTC_INT_SEC_I_MSK 0xfffeffff
+#define RO_TURISMO_TRX_RTC_INT_SEC_SFT 16
+#define RO_TURISMO_TRX_RTC_INT_SEC_HI 16
+#define RO_TURISMO_TRX_RTC_INT_SEC_SZ 1
+#define RO_TURISMO_TRX_RTC_INT_ALARM_MSK 0x00020000
+#define RO_TURISMO_TRX_RTC_INT_ALARM_I_MSK 0xfffdffff
+#define RO_TURISMO_TRX_RTC_INT_ALARM_SFT 17
+#define RO_TURISMO_TRX_RTC_INT_ALARM_HI 17
+#define RO_TURISMO_TRX_RTC_INT_ALARM_SZ 1
+#define RG_TURISMO_TRX_RTC_SEC_START_CNT_MSK 0xffffffff
+#define RG_TURISMO_TRX_RTC_SEC_START_CNT_I_MSK 0x00000000
+#define RG_TURISMO_TRX_RTC_SEC_START_CNT_SFT 0
+#define RG_TURISMO_TRX_RTC_SEC_START_CNT_HI 31
+#define RG_TURISMO_TRX_RTC_SEC_START_CNT_SZ 32
+#define RG_TURISMO_TRX_RTC_SEC_ALARM_VALUE_MSK 0xffffffff
+#define RG_TURISMO_TRX_RTC_SEC_ALARM_VALUE_I_MSK 0x00000000
+#define RG_TURISMO_TRX_RTC_SEC_ALARM_VALUE_SFT 0
+#define RG_TURISMO_TRX_RTC_SEC_ALARM_VALUE_HI 31
+#define RG_TURISMO_TRX_RTC_SEC_ALARM_VALUE_SZ 32
+#define RG_TURISMO_TRX_FPGA_CLK_REF_40M_EN_MSK 0x00000001
+#define RG_TURISMO_TRX_FPGA_CLK_REF_40M_EN_I_MSK 0xfffffffe
+#define RG_TURISMO_TRX_FPGA_CLK_REF_40M_EN_SFT 0
+#define RG_TURISMO_TRX_FPGA_CLK_REF_40M_EN_HI 0
+#define RG_TURISMO_TRX_FPGA_CLK_REF_40M_EN_SZ 1
+#define RG_TURISMO_TRX_CLK_RTC_SW_MSK 0x00000002
+#define RG_TURISMO_TRX_CLK_RTC_SW_I_MSK 0xfffffffd
+#define RG_TURISMO_TRX_CLK_RTC_SW_SFT 1
+#define RG_TURISMO_TRX_CLK_RTC_SW_HI 1
+#define RG_TURISMO_TRX_CLK_RTC_SW_SZ 1
+#define RG_TURISMO_TRX_PHY_RST_N_MSK 0x00000010
+#define RG_TURISMO_TRX_PHY_RST_N_I_MSK 0xffffffef
+#define RG_TURISMO_TRX_PHY_RST_N_SFT 4
+#define RG_TURISMO_TRX_PHY_RST_N_HI 4
+#define RG_TURISMO_TRX_PHY_RST_N_SZ 1
+#define RO_TURISMO_TRX_PMU_STATE_MSK 0x00000007
+#define RO_TURISMO_TRX_PMU_STATE_I_MSK 0xfffffff8
+#define RO_TURISMO_TRX_PMU_STATE_SFT 0
+#define RO_TURISMO_TRX_PMU_STATE_HI 2
+#define RO_TURISMO_TRX_PMU_STATE_SZ 3
+#define RO_TURISMO_TRX_AD_VBAT_OK_MSK 0x00000010
+#define RO_TURISMO_TRX_AD_VBAT_OK_I_MSK 0xffffffef
+#define RO_TURISMO_TRX_AD_VBAT_OK_SFT 4
+#define RO_TURISMO_TRX_AD_VBAT_OK_HI 4
+#define RO_TURISMO_TRX_AD_VBAT_OK_SZ 1
+#define RG_TURISMO_TRX_BT_CLK_SW_MSK 0x00000001
+#define RG_TURISMO_TRX_BT_CLK_SW_I_MSK 0xfffffffe
+#define RG_TURISMO_TRX_BT_CLK_SW_SFT 0
+#define RG_TURISMO_TRX_BT_CLK_SW_HI 0
+#define RG_TURISMO_TRX_BT_CLK_SW_SZ 1
+#define RG_TURISMO_TRX_BT_CLK32K_CAL_DONE_MSK 0x00000002
+#define RG_TURISMO_TRX_BT_CLK32K_CAL_DONE_I_MSK 0xfffffffd
+#define RG_TURISMO_TRX_BT_CLK32K_CAL_DONE_SFT 1
+#define RG_TURISMO_TRX_BT_CLK32K_CAL_DONE_HI 1
+#define RG_TURISMO_TRX_BT_CLK32K_CAL_DONE_SZ 1
+#define RG_TURISMO_TRX_GPIO16_DS_MSK 0x00000001
+#define RG_TURISMO_TRX_GPIO16_DS_I_MSK 0xfffffffe
+#define RG_TURISMO_TRX_GPIO16_DS_SFT 0
+#define RG_TURISMO_TRX_GPIO16_DS_HI 0
+#define RG_TURISMO_TRX_GPIO16_DS_SZ 1
+#define RG_TURISMO_TRX_GPIO16_PD_MSK 0x00000002
+#define RG_TURISMO_TRX_GPIO16_PD_I_MSK 0xfffffffd
+#define RG_TURISMO_TRX_GPIO16_PD_SFT 1
+#define RG_TURISMO_TRX_GPIO16_PD_HI 1
+#define RG_TURISMO_TRX_GPIO16_PD_SZ 1
+#define RG_TURISMO_TRX_GPIO16_OE_MSK 0x00000004
+#define RG_TURISMO_TRX_GPIO16_OE_I_MSK 0xfffffffb
+#define RG_TURISMO_TRX_GPIO16_OE_SFT 2
+#define RG_TURISMO_TRX_GPIO16_OE_HI 2
+#define RG_TURISMO_TRX_GPIO16_OE_SZ 1
+#define RG_TURISMO_TRX_GPIO17_DS_MSK 0x00000010
+#define RG_TURISMO_TRX_GPIO17_DS_I_MSK 0xffffffef
+#define RG_TURISMO_TRX_GPIO17_DS_SFT 4
+#define RG_TURISMO_TRX_GPIO17_DS_HI 4
+#define RG_TURISMO_TRX_GPIO17_DS_SZ 1
+#define RG_TURISMO_TRX_GPIO17_PD_MSK 0x00000020
+#define RG_TURISMO_TRX_GPIO17_PD_I_MSK 0xffffffdf
+#define RG_TURISMO_TRX_GPIO17_PD_SFT 5
+#define RG_TURISMO_TRX_GPIO17_PD_HI 5
+#define RG_TURISMO_TRX_GPIO17_PD_SZ 1
+#define RG_TURISMO_TRX_GPIO17_OE_MSK 0x00000040
+#define RG_TURISMO_TRX_GPIO17_OE_I_MSK 0xffffffbf
+#define RG_TURISMO_TRX_GPIO17_OE_SFT 6
+#define RG_TURISMO_TRX_GPIO17_OE_HI 6
+#define RG_TURISMO_TRX_GPIO17_OE_SZ 1
+#define RG_TURISMO_TRX_GPIO18_DS_MSK 0x00000100
+#define RG_TURISMO_TRX_GPIO18_DS_I_MSK 0xfffffeff
+#define RG_TURISMO_TRX_GPIO18_DS_SFT 8
+#define RG_TURISMO_TRX_GPIO18_DS_HI 8
+#define RG_TURISMO_TRX_GPIO18_DS_SZ 1
+#define RG_TURISMO_TRX_GPIO18_PD_MSK 0x00000200
+#define RG_TURISMO_TRX_GPIO18_PD_I_MSK 0xfffffdff
+#define RG_TURISMO_TRX_GPIO18_PD_SFT 9
+#define RG_TURISMO_TRX_GPIO18_PD_HI 9
+#define RG_TURISMO_TRX_GPIO18_PD_SZ 1
+#define RG_TURISMO_TRX_GPIO18_OE_MSK 0x00000400
+#define RG_TURISMO_TRX_GPIO18_OE_I_MSK 0xfffffbff
+#define RG_TURISMO_TRX_GPIO18_OE_SFT 10
+#define RG_TURISMO_TRX_GPIO18_OE_HI 10
+#define RG_TURISMO_TRX_GPIO18_OE_SZ 1
+#define RG_TURISMO_TRX_GPIO19_DS_MSK 0x00001000
+#define RG_TURISMO_TRX_GPIO19_DS_I_MSK 0xffffefff
+#define RG_TURISMO_TRX_GPIO19_DS_SFT 12
+#define RG_TURISMO_TRX_GPIO19_DS_HI 12
+#define RG_TURISMO_TRX_GPIO19_DS_SZ 1
+#define RG_TURISMO_TRX_GPIO19_PD_MSK 0x00002000
+#define RG_TURISMO_TRX_GPIO19_PD_I_MSK 0xffffdfff
+#define RG_TURISMO_TRX_GPIO19_PD_SFT 13
+#define RG_TURISMO_TRX_GPIO19_PD_HI 13
+#define RG_TURISMO_TRX_GPIO19_PD_SZ 1
+#define RG_TURISMO_TRX_GPIO19_OE_MSK 0x00004000
+#define RG_TURISMO_TRX_GPIO19_OE_I_MSK 0xffffbfff
+#define RG_TURISMO_TRX_GPIO19_OE_SFT 14
+#define RG_TURISMO_TRX_GPIO19_OE_HI 14
+#define RG_TURISMO_TRX_GPIO19_OE_SZ 1
+#define RG_TURISMO_TRX_GPIO20_DS_MSK 0x00010000
+#define RG_TURISMO_TRX_GPIO20_DS_I_MSK 0xfffeffff
+#define RG_TURISMO_TRX_GPIO20_DS_SFT 16
+#define RG_TURISMO_TRX_GPIO20_DS_HI 16
+#define RG_TURISMO_TRX_GPIO20_DS_SZ 1
+#define RG_TURISMO_TRX_GPIO20_PD_MSK 0x00020000
+#define RG_TURISMO_TRX_GPIO20_PD_I_MSK 0xfffdffff
+#define RG_TURISMO_TRX_GPIO20_PD_SFT 17
+#define RG_TURISMO_TRX_GPIO20_PD_HI 17
+#define RG_TURISMO_TRX_GPIO20_PD_SZ 1
+#define RG_TURISMO_TRX_GPIO20_OE_MSK 0x00040000
+#define RG_TURISMO_TRX_GPIO20_OE_I_MSK 0xfffbffff
+#define RG_TURISMO_TRX_GPIO20_OE_SFT 18
+#define RG_TURISMO_TRX_GPIO20_OE_HI 18
+#define RG_TURISMO_TRX_GPIO20_OE_SZ 1
+#define RG_TURISMO_TRX_SPIS_MISO_DS_MSK 0x01000000
+#define RG_TURISMO_TRX_SPIS_MISO_DS_I_MSK 0xfeffffff
+#define RG_TURISMO_TRX_SPIS_MISO_DS_SFT 24
+#define RG_TURISMO_TRX_SPIS_MISO_DS_HI 24
+#define RG_TURISMO_TRX_SPIS_MISO_DS_SZ 1
+#define RG_TURISMO_TRX_FPGA_CLK_REF_40M_DS_MSK 0x10000000
+#define RG_TURISMO_TRX_FPGA_CLK_REF_40M_DS_I_MSK 0xefffffff
+#define RG_TURISMO_TRX_FPGA_CLK_REF_40M_DS_SFT 28
+#define RG_TURISMO_TRX_FPGA_CLK_REF_40M_DS_HI 28
+#define RG_TURISMO_TRX_FPGA_CLK_REF_40M_DS_SZ 1
+#define RG_TURISMO_TRX_FPGA_CLK_REF_40M_PD_MSK 0x20000000
+#define RG_TURISMO_TRX_FPGA_CLK_REF_40M_PD_I_MSK 0xdfffffff
+#define RG_TURISMO_TRX_FPGA_CLK_REF_40M_PD_SFT 29
+#define RG_TURISMO_TRX_FPGA_CLK_REF_40M_PD_HI 29
+#define RG_TURISMO_TRX_FPGA_CLK_REF_40M_PD_SZ 1
+#define RG_TURISMO_TRX_FPGA_CLK_REF_40M_OE_MSK 0x40000000
+#define RG_TURISMO_TRX_FPGA_CLK_REF_40M_OE_I_MSK 0xbfffffff
+#define RG_TURISMO_TRX_FPGA_CLK_REF_40M_OE_SFT 30
+#define RG_TURISMO_TRX_FPGA_CLK_REF_40M_OE_HI 30
+#define RG_TURISMO_TRX_FPGA_CLK_REF_40M_OE_SZ 1
+#define RG_TURISMO_TRX_GPIO08_DS_MSK 0x00000001
+#define RG_TURISMO_TRX_GPIO08_DS_I_MSK 0xfffffffe
+#define RG_TURISMO_TRX_GPIO08_DS_SFT 0
+#define RG_TURISMO_TRX_GPIO08_DS_HI 0
+#define RG_TURISMO_TRX_GPIO08_DS_SZ 1
+#define RG_TURISMO_TRX_GPIO08_PD_MSK 0x00000002
+#define RG_TURISMO_TRX_GPIO08_PD_I_MSK 0xfffffffd
+#define RG_TURISMO_TRX_GPIO08_PD_SFT 1
+#define RG_TURISMO_TRX_GPIO08_PD_HI 1
+#define RG_TURISMO_TRX_GPIO08_PD_SZ 1
+#define RG_TURISMO_TRX_GPIO08_OE_MSK 0x00000004
+#define RG_TURISMO_TRX_GPIO08_OE_I_MSK 0xfffffffb
+#define RG_TURISMO_TRX_GPIO08_OE_SFT 2
+#define RG_TURISMO_TRX_GPIO08_OE_HI 2
+#define RG_TURISMO_TRX_GPIO08_OE_SZ 1
+#define RG_TURISMO_TRX_GPIO09_DS_MSK 0x00000010
+#define RG_TURISMO_TRX_GPIO09_DS_I_MSK 0xffffffef
+#define RG_TURISMO_TRX_GPIO09_DS_SFT 4
+#define RG_TURISMO_TRX_GPIO09_DS_HI 4
+#define RG_TURISMO_TRX_GPIO09_DS_SZ 1
+#define RG_TURISMO_TRX_GPIO09_PD_MSK 0x00000020
+#define RG_TURISMO_TRX_GPIO09_PD_I_MSK 0xffffffdf
+#define RG_TURISMO_TRX_GPIO09_PD_SFT 5
+#define RG_TURISMO_TRX_GPIO09_PD_HI 5
+#define RG_TURISMO_TRX_GPIO09_PD_SZ 1
+#define RG_TURISMO_TRX_GPIO09_OE_MSK 0x00000040
+#define RG_TURISMO_TRX_GPIO09_OE_I_MSK 0xffffffbf
+#define RG_TURISMO_TRX_GPIO09_OE_SFT 6
+#define RG_TURISMO_TRX_GPIO09_OE_HI 6
+#define RG_TURISMO_TRX_GPIO09_OE_SZ 1
+#define RG_TURISMO_TRX_GPIO10_DS_MSK 0x00000100
+#define RG_TURISMO_TRX_GPIO10_DS_I_MSK 0xfffffeff
+#define RG_TURISMO_TRX_GPIO10_DS_SFT 8
+#define RG_TURISMO_TRX_GPIO10_DS_HI 8
+#define RG_TURISMO_TRX_GPIO10_DS_SZ 1
+#define RG_TURISMO_TRX_GPIO10_PD_MSK 0x00000200
+#define RG_TURISMO_TRX_GPIO10_PD_I_MSK 0xfffffdff
+#define RG_TURISMO_TRX_GPIO10_PD_SFT 9
+#define RG_TURISMO_TRX_GPIO10_PD_HI 9
+#define RG_TURISMO_TRX_GPIO10_PD_SZ 1
+#define RG_TURISMO_TRX_GPIO10_OE_MSK 0x00000400
+#define RG_TURISMO_TRX_GPIO10_OE_I_MSK 0xfffffbff
+#define RG_TURISMO_TRX_GPIO10_OE_SFT 10
+#define RG_TURISMO_TRX_GPIO10_OE_HI 10
+#define RG_TURISMO_TRX_GPIO10_OE_SZ 1
+#define RG_TURISMO_TRX_GPIO11_DS_MSK 0x00001000
+#define RG_TURISMO_TRX_GPIO11_DS_I_MSK 0xffffefff
+#define RG_TURISMO_TRX_GPIO11_DS_SFT 12
+#define RG_TURISMO_TRX_GPIO11_DS_HI 12
+#define RG_TURISMO_TRX_GPIO11_DS_SZ 1
+#define RG_TURISMO_TRX_GPIO11_PD_MSK 0x00002000
+#define RG_TURISMO_TRX_GPIO11_PD_I_MSK 0xffffdfff
+#define RG_TURISMO_TRX_GPIO11_PD_SFT 13
+#define RG_TURISMO_TRX_GPIO11_PD_HI 13
+#define RG_TURISMO_TRX_GPIO11_PD_SZ 1
+#define RG_TURISMO_TRX_GPIO11_OE_MSK 0x00004000
+#define RG_TURISMO_TRX_GPIO11_OE_I_MSK 0xffffbfff
+#define RG_TURISMO_TRX_GPIO11_OE_SFT 14
+#define RG_TURISMO_TRX_GPIO11_OE_HI 14
+#define RG_TURISMO_TRX_GPIO11_OE_SZ 1
+#define RG_TURISMO_TRX_GPIO12_DS_MSK 0x00010000
+#define RG_TURISMO_TRX_GPIO12_DS_I_MSK 0xfffeffff
+#define RG_TURISMO_TRX_GPIO12_DS_SFT 16
+#define RG_TURISMO_TRX_GPIO12_DS_HI 16
+#define RG_TURISMO_TRX_GPIO12_DS_SZ 1
+#define RG_TURISMO_TRX_GPIO12_PD_MSK 0x00020000
+#define RG_TURISMO_TRX_GPIO12_PD_I_MSK 0xfffdffff
+#define RG_TURISMO_TRX_GPIO12_PD_SFT 17
+#define RG_TURISMO_TRX_GPIO12_PD_HI 17
+#define RG_TURISMO_TRX_GPIO12_PD_SZ 1
+#define RG_TURISMO_TRX_GPIO12_OE_MSK 0x00040000
+#define RG_TURISMO_TRX_GPIO12_OE_I_MSK 0xfffbffff
+#define RG_TURISMO_TRX_GPIO12_OE_SFT 18
+#define RG_TURISMO_TRX_GPIO12_OE_HI 18
+#define RG_TURISMO_TRX_GPIO12_OE_SZ 1
+#define RG_TURISMO_TRX_GPIO13_DS_MSK 0x00100000
+#define RG_TURISMO_TRX_GPIO13_DS_I_MSK 0xffefffff
+#define RG_TURISMO_TRX_GPIO13_DS_SFT 20
+#define RG_TURISMO_TRX_GPIO13_DS_HI 20
+#define RG_TURISMO_TRX_GPIO13_DS_SZ 1
+#define RG_TURISMO_TRX_GPIO13_PD_MSK 0x00200000
+#define RG_TURISMO_TRX_GPIO13_PD_I_MSK 0xffdfffff
+#define RG_TURISMO_TRX_GPIO13_PD_SFT 21
+#define RG_TURISMO_TRX_GPIO13_PD_HI 21
+#define RG_TURISMO_TRX_GPIO13_PD_SZ 1
+#define RG_TURISMO_TRX_GPIO13_OE_MSK 0x00400000
+#define RG_TURISMO_TRX_GPIO13_OE_I_MSK 0xffbfffff
+#define RG_TURISMO_TRX_GPIO13_OE_SFT 22
+#define RG_TURISMO_TRX_GPIO13_OE_HI 22
+#define RG_TURISMO_TRX_GPIO13_OE_SZ 1
+#define RG_TURISMO_TRX_GPIO14_DS_MSK 0x01000000
+#define RG_TURISMO_TRX_GPIO14_DS_I_MSK 0xfeffffff
+#define RG_TURISMO_TRX_GPIO14_DS_SFT 24
+#define RG_TURISMO_TRX_GPIO14_DS_HI 24
+#define RG_TURISMO_TRX_GPIO14_DS_SZ 1
+#define RG_TURISMO_TRX_GPIO14_PD_MSK 0x02000000
+#define RG_TURISMO_TRX_GPIO14_PD_I_MSK 0xfdffffff
+#define RG_TURISMO_TRX_GPIO14_PD_SFT 25
+#define RG_TURISMO_TRX_GPIO14_PD_HI 25
+#define RG_TURISMO_TRX_GPIO14_PD_SZ 1
+#define RG_TURISMO_TRX_GPIO14_OE_MSK 0x04000000
+#define RG_TURISMO_TRX_GPIO14_OE_I_MSK 0xfbffffff
+#define RG_TURISMO_TRX_GPIO14_OE_SFT 26
+#define RG_TURISMO_TRX_GPIO14_OE_HI 26
+#define RG_TURISMO_TRX_GPIO14_OE_SZ 1
+#define RG_TURISMO_TRX_GPIO15_DS_MSK 0x10000000
+#define RG_TURISMO_TRX_GPIO15_DS_I_MSK 0xefffffff
+#define RG_TURISMO_TRX_GPIO15_DS_SFT 28
+#define RG_TURISMO_TRX_GPIO15_DS_HI 28
+#define RG_TURISMO_TRX_GPIO15_DS_SZ 1
+#define RG_TURISMO_TRX_GPIO15_PD_MSK 0x20000000
+#define RG_TURISMO_TRX_GPIO15_PD_I_MSK 0xdfffffff
+#define RG_TURISMO_TRX_GPIO15_PD_SFT 29
+#define RG_TURISMO_TRX_GPIO15_PD_HI 29
+#define RG_TURISMO_TRX_GPIO15_PD_SZ 1
+#define RG_TURISMO_TRX_GPIO15_OE_MSK 0x40000000
+#define RG_TURISMO_TRX_GPIO15_OE_I_MSK 0xbfffffff
+#define RG_TURISMO_TRX_GPIO15_OE_SFT 30
+#define RG_TURISMO_TRX_GPIO15_OE_HI 30
+#define RG_TURISMO_TRX_GPIO15_OE_SZ 1
+#define RG_TURISMO_TRX_GPIO00_DS_MSK 0x00000001
+#define RG_TURISMO_TRX_GPIO00_DS_I_MSK 0xfffffffe
+#define RG_TURISMO_TRX_GPIO00_DS_SFT 0
+#define RG_TURISMO_TRX_GPIO00_DS_HI 0
+#define RG_TURISMO_TRX_GPIO00_DS_SZ 1
+#define RG_TURISMO_TRX_GPIO00_PD_MSK 0x00000002
+#define RG_TURISMO_TRX_GPIO00_PD_I_MSK 0xfffffffd
+#define RG_TURISMO_TRX_GPIO00_PD_SFT 1
+#define RG_TURISMO_TRX_GPIO00_PD_HI 1
+#define RG_TURISMO_TRX_GPIO00_PD_SZ 1
+#define RG_TURISMO_TRX_GPIO00_OE_MSK 0x00000004
+#define RG_TURISMO_TRX_GPIO00_OE_I_MSK 0xfffffffb
+#define RG_TURISMO_TRX_GPIO00_OE_SFT 2
+#define RG_TURISMO_TRX_GPIO00_OE_HI 2
+#define RG_TURISMO_TRX_GPIO00_OE_SZ 1
+#define RG_TURISMO_TRX_GPIO01_DS_MSK 0x00000010
+#define RG_TURISMO_TRX_GPIO01_DS_I_MSK 0xffffffef
+#define RG_TURISMO_TRX_GPIO01_DS_SFT 4
+#define RG_TURISMO_TRX_GPIO01_DS_HI 4
+#define RG_TURISMO_TRX_GPIO01_DS_SZ 1
+#define RG_TURISMO_TRX_GPIO01_PD_MSK 0x00000020
+#define RG_TURISMO_TRX_GPIO01_PD_I_MSK 0xffffffdf
+#define RG_TURISMO_TRX_GPIO01_PD_SFT 5
+#define RG_TURISMO_TRX_GPIO01_PD_HI 5
+#define RG_TURISMO_TRX_GPIO01_PD_SZ 1
+#define RG_TURISMO_TRX_GPIO01_OE_MSK 0x00000040
+#define RG_TURISMO_TRX_GPIO01_OE_I_MSK 0xffffffbf
+#define RG_TURISMO_TRX_GPIO01_OE_SFT 6
+#define RG_TURISMO_TRX_GPIO01_OE_HI 6
+#define RG_TURISMO_TRX_GPIO01_OE_SZ 1
+#define RG_TURISMO_TRX_GPIO02_DS_MSK 0x00000100
+#define RG_TURISMO_TRX_GPIO02_DS_I_MSK 0xfffffeff
+#define RG_TURISMO_TRX_GPIO02_DS_SFT 8
+#define RG_TURISMO_TRX_GPIO02_DS_HI 8
+#define RG_TURISMO_TRX_GPIO02_DS_SZ 1
+#define RG_TURISMO_TRX_GPIO02_PD_MSK 0x00000200
+#define RG_TURISMO_TRX_GPIO02_PD_I_MSK 0xfffffdff
+#define RG_TURISMO_TRX_GPIO02_PD_SFT 9
+#define RG_TURISMO_TRX_GPIO02_PD_HI 9
+#define RG_TURISMO_TRX_GPIO02_PD_SZ 1
+#define RG_TURISMO_TRX_GPIO02_OE_MSK 0x00000400
+#define RG_TURISMO_TRX_GPIO02_OE_I_MSK 0xfffffbff
+#define RG_TURISMO_TRX_GPIO02_OE_SFT 10
+#define RG_TURISMO_TRX_GPIO02_OE_HI 10
+#define RG_TURISMO_TRX_GPIO02_OE_SZ 1
+#define RG_TURISMO_TRX_GPIO03_DS_MSK 0x00001000
+#define RG_TURISMO_TRX_GPIO03_DS_I_MSK 0xffffefff
+#define RG_TURISMO_TRX_GPIO03_DS_SFT 12
+#define RG_TURISMO_TRX_GPIO03_DS_HI 12
+#define RG_TURISMO_TRX_GPIO03_DS_SZ 1
+#define RG_TURISMO_TRX_GPIO03_PD_MSK 0x00002000
+#define RG_TURISMO_TRX_GPIO03_PD_I_MSK 0xffffdfff
+#define RG_TURISMO_TRX_GPIO03_PD_SFT 13
+#define RG_TURISMO_TRX_GPIO03_PD_HI 13
+#define RG_TURISMO_TRX_GPIO03_PD_SZ 1
+#define RG_TURISMO_TRX_GPIO03_OE_MSK 0x00004000
+#define RG_TURISMO_TRX_GPIO03_OE_I_MSK 0xffffbfff
+#define RG_TURISMO_TRX_GPIO03_OE_SFT 14
+#define RG_TURISMO_TRX_GPIO03_OE_HI 14
+#define RG_TURISMO_TRX_GPIO03_OE_SZ 1
+#define RG_TURISMO_TRX_GPIO04_DS_MSK 0x00010000
+#define RG_TURISMO_TRX_GPIO04_DS_I_MSK 0xfffeffff
+#define RG_TURISMO_TRX_GPIO04_DS_SFT 16
+#define RG_TURISMO_TRX_GPIO04_DS_HI 16
+#define RG_TURISMO_TRX_GPIO04_DS_SZ 1
+#define RG_TURISMO_TRX_GPIO04_PD_MSK 0x00020000
+#define RG_TURISMO_TRX_GPIO04_PD_I_MSK 0xfffdffff
+#define RG_TURISMO_TRX_GPIO04_PD_SFT 17
+#define RG_TURISMO_TRX_GPIO04_PD_HI 17
+#define RG_TURISMO_TRX_GPIO04_PD_SZ 1
+#define RG_TURISMO_TRX_GPIO04_OE_MSK 0x00040000
+#define RG_TURISMO_TRX_GPIO04_OE_I_MSK 0xfffbffff
+#define RG_TURISMO_TRX_GPIO04_OE_SFT 18
+#define RG_TURISMO_TRX_GPIO04_OE_HI 18
+#define RG_TURISMO_TRX_GPIO04_OE_SZ 1
+#define RG_TURISMO_TRX_GPIO05_DS_MSK 0x00100000
+#define RG_TURISMO_TRX_GPIO05_DS_I_MSK 0xffefffff
+#define RG_TURISMO_TRX_GPIO05_DS_SFT 20
+#define RG_TURISMO_TRX_GPIO05_DS_HI 20
+#define RG_TURISMO_TRX_GPIO05_DS_SZ 1
+#define RG_TURISMO_TRX_GPIO05_PD_MSK 0x00200000
+#define RG_TURISMO_TRX_GPIO05_PD_I_MSK 0xffdfffff
+#define RG_TURISMO_TRX_GPIO05_PD_SFT 21
+#define RG_TURISMO_TRX_GPIO05_PD_HI 21
+#define RG_TURISMO_TRX_GPIO05_PD_SZ 1
+#define RG_TURISMO_TRX_GPIO05_OE_MSK 0x00400000
+#define RG_TURISMO_TRX_GPIO05_OE_I_MSK 0xffbfffff
+#define RG_TURISMO_TRX_GPIO05_OE_SFT 22
+#define RG_TURISMO_TRX_GPIO05_OE_HI 22
+#define RG_TURISMO_TRX_GPIO05_OE_SZ 1
+#define RG_TURISMO_TRX_GPIO06_DS_MSK 0x01000000
+#define RG_TURISMO_TRX_GPIO06_DS_I_MSK 0xfeffffff
+#define RG_TURISMO_TRX_GPIO06_DS_SFT 24
+#define RG_TURISMO_TRX_GPIO06_DS_HI 24
+#define RG_TURISMO_TRX_GPIO06_DS_SZ 1
+#define RG_TURISMO_TRX_GPIO06_PD_MSK 0x02000000
+#define RG_TURISMO_TRX_GPIO06_PD_I_MSK 0xfdffffff
+#define RG_TURISMO_TRX_GPIO06_PD_SFT 25
+#define RG_TURISMO_TRX_GPIO06_PD_HI 25
+#define RG_TURISMO_TRX_GPIO06_PD_SZ 1
+#define RG_TURISMO_TRX_GPIO06_OE_MSK 0x04000000
+#define RG_TURISMO_TRX_GPIO06_OE_I_MSK 0xfbffffff
+#define RG_TURISMO_TRX_GPIO06_OE_SFT 26
+#define RG_TURISMO_TRX_GPIO06_OE_HI 26
+#define RG_TURISMO_TRX_GPIO06_OE_SZ 1
+#define RG_TURISMO_TRX_GPIO07_DS_MSK 0x10000000
+#define RG_TURISMO_TRX_GPIO07_DS_I_MSK 0xefffffff
+#define RG_TURISMO_TRX_GPIO07_DS_SFT 28
+#define RG_TURISMO_TRX_GPIO07_DS_HI 28
+#define RG_TURISMO_TRX_GPIO07_DS_SZ 1
+#define RG_TURISMO_TRX_GPIO07_PD_MSK 0x20000000
+#define RG_TURISMO_TRX_GPIO07_PD_I_MSK 0xdfffffff
+#define RG_TURISMO_TRX_GPIO07_PD_SFT 29
+#define RG_TURISMO_TRX_GPIO07_PD_HI 29
+#define RG_TURISMO_TRX_GPIO07_PD_SZ 1
+#define RG_TURISMO_TRX_GPIO07_OE_MSK 0x40000000
+#define RG_TURISMO_TRX_GPIO07_OE_I_MSK 0xbfffffff
+#define RG_TURISMO_TRX_GPIO07_OE_SFT 30
+#define RG_TURISMO_TRX_GPIO07_OE_HI 30
+#define RG_TURISMO_TRX_GPIO07_OE_SZ 1
+#define RG_TURISMO_TRX_RF_PHY_MODE_SEL_MSK 0x00000003
+#define RG_TURISMO_TRX_RF_PHY_MODE_SEL_I_MSK 0xfffffffc
+#define RG_TURISMO_TRX_RF_PHY_MODE_SEL_SFT 0
+#define RG_TURISMO_TRX_RF_PHY_MODE_SEL_HI 1
+#define RG_TURISMO_TRX_RF_PHY_MODE_SEL_SZ 2
+#define RG_TURISMO_TRX_RF_PHY_MODE_WIFI_MAC_MSK 0x00000070
+#define RG_TURISMO_TRX_RF_PHY_MODE_WIFI_MAC_I_MSK 0xffffff8f
+#define RG_TURISMO_TRX_RF_PHY_MODE_WIFI_MAC_SFT 4
+#define RG_TURISMO_TRX_RF_PHY_MODE_WIFI_MAC_HI 6
+#define RG_TURISMO_TRX_RF_PHY_MODE_WIFI_MAC_SZ 3
+#define RG_TURISMO_TRX_PAD_MUX_SEL_MSK 0x00000f00
+#define RG_TURISMO_TRX_PAD_MUX_SEL_I_MSK 0xfffff0ff
+#define RG_TURISMO_TRX_PAD_MUX_SEL_SFT 8
+#define RG_TURISMO_TRX_PAD_MUX_SEL_HI 11
+#define RG_TURISMO_TRX_PAD_MUX_SEL_SZ 4
+#define RG_TURISMO_TRX_MODE_LATCH_LMT_MSK 0x00007000
+#define RG_TURISMO_TRX_MODE_LATCH_LMT_I_MSK 0xffff8fff
+#define RG_TURISMO_TRX_MODE_LATCH_LMT_SFT 12
+#define RG_TURISMO_TRX_MODE_LATCH_LMT_HI 14
+#define RG_TURISMO_TRX_MODE_LATCH_LMT_SZ 3
+#define RG_TURISMO_TRX_CLK_MON_SEL_MSK 0x00070000
+#define RG_TURISMO_TRX_CLK_MON_SEL_I_MSK 0xfff8ffff
+#define RG_TURISMO_TRX_CLK_MON_SEL_SFT 16
+#define RG_TURISMO_TRX_CLK_MON_SEL_HI 18
+#define RG_TURISMO_TRX_CLK_MON_SEL_SZ 3
+#define RG_TURISMO_TRX_EXT_MCU_PWRUP_MSK 0x80000000
+#define RG_TURISMO_TRX_EXT_MCU_PWRUP_I_MSK 0x7fffffff
+#define RG_TURISMO_TRX_EXT_MCU_PWRUP_SFT 31
+#define RG_TURISMO_TRX_EXT_MCU_PWRUP_HI 31
+#define RG_TURISMO_TRX_EXT_MCU_PWRUP_SZ 1
+#define RG_TURISMO_TRX_RAM_00_MSK 0xffffffff
+#define RG_TURISMO_TRX_RAM_00_I_MSK 0x00000000
+#define RG_TURISMO_TRX_RAM_00_SFT 0
+#define RG_TURISMO_TRX_RAM_00_HI 31
+#define RG_TURISMO_TRX_RAM_00_SZ 32
+#define RG_TURISMO_TRX_RAM_01_MSK 0xffffffff
+#define RG_TURISMO_TRX_RAM_01_I_MSK 0x00000000
+#define RG_TURISMO_TRX_RAM_01_SFT 0
+#define RG_TURISMO_TRX_RAM_01_HI 31
+#define RG_TURISMO_TRX_RAM_01_SZ 32
+#define RG_TURISMO_TRX_RAM_02_MSK 0xffffffff
+#define RG_TURISMO_TRX_RAM_02_I_MSK 0x00000000
+#define RG_TURISMO_TRX_RAM_02_SFT 0
+#define RG_TURISMO_TRX_RAM_02_HI 31
+#define RG_TURISMO_TRX_RAM_02_SZ 32
+#define RG_TURISMO_TRX_RAM_03_MSK 0xffffffff
+#define RG_TURISMO_TRX_RAM_03_I_MSK 0x00000000
+#define RG_TURISMO_TRX_RAM_03_SFT 0
+#define RG_TURISMO_TRX_RAM_03_HI 31
+#define RG_TURISMO_TRX_RAM_03_SZ 32
+#define RG_TURISMO_TRX_RAM_04_MSK 0xffffffff
+#define RG_TURISMO_TRX_RAM_04_I_MSK 0x00000000
+#define RG_TURISMO_TRX_RAM_04_SFT 0
+#define RG_TURISMO_TRX_RAM_04_HI 31
+#define RG_TURISMO_TRX_RAM_04_SZ 32
+#define RG_TURISMO_TRX_RAM_05_MSK 0xffffffff
+#define RG_TURISMO_TRX_RAM_05_I_MSK 0x00000000
+#define RG_TURISMO_TRX_RAM_05_SFT 0
+#define RG_TURISMO_TRX_RAM_05_HI 31
+#define RG_TURISMO_TRX_RAM_05_SZ 32
+#define RG_TURISMO_TRX_RAM_06_MSK 0xffffffff
+#define RG_TURISMO_TRX_RAM_06_I_MSK 0x00000000
+#define RG_TURISMO_TRX_RAM_06_SFT 0
+#define RG_TURISMO_TRX_RAM_06_HI 31
+#define RG_TURISMO_TRX_RAM_06_SZ 32
+#define RG_TURISMO_TRX_RAM_07_MSK 0xffffffff
+#define RG_TURISMO_TRX_RAM_07_I_MSK 0x00000000
+#define RG_TURISMO_TRX_RAM_07_SFT 0
+#define RG_TURISMO_TRX_RAM_07_HI 31
+#define RG_TURISMO_TRX_RAM_07_SZ 32
+#define RG_TURISMO_TRX_RAM_08_MSK 0xffffffff
+#define RG_TURISMO_TRX_RAM_08_I_MSK 0x00000000
+#define RG_TURISMO_TRX_RAM_08_SFT 0
+#define RG_TURISMO_TRX_RAM_08_HI 31
+#define RG_TURISMO_TRX_RAM_08_SZ 32
+#define RG_TURISMO_TRX_RAM_09_MSK 0xffffffff
+#define RG_TURISMO_TRX_RAM_09_I_MSK 0x00000000
+#define RG_TURISMO_TRX_RAM_09_SFT 0
+#define RG_TURISMO_TRX_RAM_09_HI 31
+#define RG_TURISMO_TRX_RAM_09_SZ 32
+#define RG_TURISMO_TRX_RAM_10_MSK 0xffffffff
+#define RG_TURISMO_TRX_RAM_10_I_MSK 0x00000000
+#define RG_TURISMO_TRX_RAM_10_SFT 0
+#define RG_TURISMO_TRX_RAM_10_HI 31
+#define RG_TURISMO_TRX_RAM_10_SZ 32
+#define RG_TURISMO_TRX_RAM_11_MSK 0xffffffff
+#define RG_TURISMO_TRX_RAM_11_I_MSK 0x00000000
+#define RG_TURISMO_TRX_RAM_11_SFT 0
+#define RG_TURISMO_TRX_RAM_11_HI 31
+#define RG_TURISMO_TRX_RAM_11_SZ 32
+#define RG_TURISMO_TRX_RAM_12_MSK 0xffffffff
+#define RG_TURISMO_TRX_RAM_12_I_MSK 0x00000000
+#define RG_TURISMO_TRX_RAM_12_SFT 0
+#define RG_TURISMO_TRX_RAM_12_HI 31
+#define RG_TURISMO_TRX_RAM_12_SZ 32
+#define RG_TURISMO_TRX_RAM_13_MSK 0xffffffff
+#define RG_TURISMO_TRX_RAM_13_I_MSK 0x00000000
+#define RG_TURISMO_TRX_RAM_13_SFT 0
+#define RG_TURISMO_TRX_RAM_13_HI 31
+#define RG_TURISMO_TRX_RAM_13_SZ 32
+#define RG_TURISMO_TRX_RAM_14_MSK 0xffffffff
+#define RG_TURISMO_TRX_RAM_14_I_MSK 0x00000000
+#define RG_TURISMO_TRX_RAM_14_SFT 0
+#define RG_TURISMO_TRX_RAM_14_HI 31
+#define RG_TURISMO_TRX_RAM_14_SZ 32
+#define RG_TURISMO_TRX_RAM_15_MSK 0xffffffff
+#define RG_TURISMO_TRX_RAM_15_I_MSK 0x00000000
+#define RG_TURISMO_TRX_RAM_15_SFT 0
+#define RG_TURISMO_TRX_RAM_15_HI 31
+#define RG_TURISMO_TRX_RAM_15_SZ 32
+#define RG_TURISMO_TRX_RAM_16_MSK 0xffffffff
+#define RG_TURISMO_TRX_RAM_16_I_MSK 0x00000000
+#define RG_TURISMO_TRX_RAM_16_SFT 0
+#define RG_TURISMO_TRX_RAM_16_HI 31
+#define RG_TURISMO_TRX_RAM_16_SZ 32
+#define RG_TURISMO_TRX_RAM_17_MSK 0xffffffff
+#define RG_TURISMO_TRX_RAM_17_I_MSK 0x00000000
+#define RG_TURISMO_TRX_RAM_17_SFT 0
+#define RG_TURISMO_TRX_RAM_17_HI 31
+#define RG_TURISMO_TRX_RAM_17_SZ 32
+#define RG_TURISMO_TRX_RAM_18_MSK 0xffffffff
+#define RG_TURISMO_TRX_RAM_18_I_MSK 0x00000000
+#define RG_TURISMO_TRX_RAM_18_SFT 0
+#define RG_TURISMO_TRX_RAM_18_HI 31
+#define RG_TURISMO_TRX_RAM_18_SZ 32
+#define RG_TURISMO_TRX_RAM_19_MSK 0xffffffff
+#define RG_TURISMO_TRX_RAM_19_I_MSK 0x00000000
+#define RG_TURISMO_TRX_RAM_19_SFT 0
+#define RG_TURISMO_TRX_RAM_19_HI 31
+#define RG_TURISMO_TRX_RAM_19_SZ 32
+#define RG_TURISMO_TRX_RAM_20_MSK 0xffffffff
+#define RG_TURISMO_TRX_RAM_20_I_MSK 0x00000000
+#define RG_TURISMO_TRX_RAM_20_SFT 0
+#define RG_TURISMO_TRX_RAM_20_HI 31
+#define RG_TURISMO_TRX_RAM_20_SZ 32
+#define RG_TURISMO_TRX_RAM_21_MSK 0xffffffff
+#define RG_TURISMO_TRX_RAM_21_I_MSK 0x00000000
+#define RG_TURISMO_TRX_RAM_21_SFT 0
+#define RG_TURISMO_TRX_RAM_21_HI 31
+#define RG_TURISMO_TRX_RAM_21_SZ 32
+#define RG_TURISMO_TRX_RAM_22_MSK 0xffffffff
+#define RG_TURISMO_TRX_RAM_22_I_MSK 0x00000000
+#define RG_TURISMO_TRX_RAM_22_SFT 0
+#define RG_TURISMO_TRX_RAM_22_HI 31
+#define RG_TURISMO_TRX_RAM_22_SZ 32
+#define RG_TURISMO_TRX_RAM_23_MSK 0xffffffff
+#define RG_TURISMO_TRX_RAM_23_I_MSK 0x00000000
+#define RG_TURISMO_TRX_RAM_23_SFT 0
+#define RG_TURISMO_TRX_RAM_23_HI 31
+#define RG_TURISMO_TRX_RAM_23_SZ 32
+#define RG_TURISMO_TRX_RAM_24_MSK 0xffffffff
+#define RG_TURISMO_TRX_RAM_24_I_MSK 0x00000000
+#define RG_TURISMO_TRX_RAM_24_SFT 0
+#define RG_TURISMO_TRX_RAM_24_HI 31
+#define RG_TURISMO_TRX_RAM_24_SZ 32
+#define RG_TURISMO_TRX_RAM_25_MSK 0xffffffff
+#define RG_TURISMO_TRX_RAM_25_I_MSK 0x00000000
+#define RG_TURISMO_TRX_RAM_25_SFT 0
+#define RG_TURISMO_TRX_RAM_25_HI 31
+#define RG_TURISMO_TRX_RAM_25_SZ 32
+#define RG_TURISMO_TRX_RAM_26_MSK 0xffffffff
+#define RG_TURISMO_TRX_RAM_26_I_MSK 0x00000000
+#define RG_TURISMO_TRX_RAM_26_SFT 0
+#define RG_TURISMO_TRX_RAM_26_HI 31
+#define RG_TURISMO_TRX_RAM_26_SZ 32
+#define RG_TURISMO_TRX_RAM_27_MSK 0xffffffff
+#define RG_TURISMO_TRX_RAM_27_I_MSK 0x00000000
+#define RG_TURISMO_TRX_RAM_27_SFT 0
+#define RG_TURISMO_TRX_RAM_27_HI 31
+#define RG_TURISMO_TRX_RAM_27_SZ 32
+#define RG_TURISMO_TRX_RAM_28_MSK 0xffffffff
+#define RG_TURISMO_TRX_RAM_28_I_MSK 0x00000000
+#define RG_TURISMO_TRX_RAM_28_SFT 0
+#define RG_TURISMO_TRX_RAM_28_HI 31
+#define RG_TURISMO_TRX_RAM_28_SZ 32
+#define RG_TURISMO_TRX_RAM_29_MSK 0xffffffff
+#define RG_TURISMO_TRX_RAM_29_I_MSK 0x00000000
+#define RG_TURISMO_TRX_RAM_29_SFT 0
+#define RG_TURISMO_TRX_RAM_29_HI 31
+#define RG_TURISMO_TRX_RAM_29_SZ 32
+#define RG_TURISMO_TRX_RAM_30_MSK 0xffffffff
+#define RG_TURISMO_TRX_RAM_30_I_MSK 0x00000000
+#define RG_TURISMO_TRX_RAM_30_SFT 0
+#define RG_TURISMO_TRX_RAM_30_HI 31
+#define RG_TURISMO_TRX_RAM_30_SZ 32
+#define RG_TURISMO_TRX_RAM_31_MSK 0xffffffff
+#define RG_TURISMO_TRX_RAM_31_I_MSK 0x00000000
+#define RG_TURISMO_TRX_RAM_31_SFT 0
+#define RG_TURISMO_TRX_RAM_31_HI 31
+#define RG_TURISMO_TRX_RAM_31_SZ 32
+#define RG_HW_PINSEL_MSK 0x00000001
+#define RG_HW_PINSEL_I_MSK 0xfffffffe
+#define RG_HW_PINSEL_SFT 0
+#define RG_HW_PINSEL_HI 0
+#define RG_HW_PINSEL_SZ 1
+#define RG_HS_3WIRE_MANUAL_MSK 0x00000002
+#define RG_HS_3WIRE_MANUAL_I_MSK 0xfffffffd
+#define RG_HS_3WIRE_MANUAL_SFT 1
+#define RG_HS_3WIRE_MANUAL_HI 1
+#define RG_HS_3WIRE_MANUAL_SZ 1
+#define RG_MODE_MANUAL_MSK 0x00000004
+#define RG_MODE_MANUAL_I_MSK 0xfffffffb
+#define RG_MODE_MANUAL_SFT 2
+#define RG_MODE_MANUAL_HI 2
+#define RG_MODE_MANUAL_SZ 1
+#define RG_5G_TX_GAIN_MANUAL_MSK 0x00000008
+#define RG_5G_TX_GAIN_MANUAL_I_MSK 0xfffffff7
+#define RG_5G_TX_GAIN_MANUAL_SFT 3
+#define RG_5G_TX_GAIN_MANUAL_HI 3
+#define RG_5G_TX_GAIN_MANUAL_SZ 1
+#define RG_RX_GAIN_MANUAL_MSK 0x00000010
+#define RG_RX_GAIN_MANUAL_I_MSK 0xffffffef
+#define RG_RX_GAIN_MANUAL_SFT 4
+#define RG_RX_GAIN_MANUAL_HI 4
+#define RG_RX_GAIN_MANUAL_SZ 1
+#define RG_TX_GAIN_MANUAL_MSK 0x00000020
+#define RG_TX_GAIN_MANUAL_I_MSK 0xffffffdf
+#define RG_TX_GAIN_MANUAL_SFT 5
+#define RG_TX_GAIN_MANUAL_HI 5
+#define RG_TX_GAIN_MANUAL_SZ 1
+#define RG_TXGAIN_PHYCTRL_MSK 0x00000040
+#define RG_TXGAIN_PHYCTRL_I_MSK 0xffffffbf
+#define RG_TXGAIN_PHYCTRL_SFT 6
+#define RG_TXGAIN_PHYCTRL_HI 6
+#define RG_TXGAIN_PHYCTRL_SZ 1
+#define RG_RX_AGC_MSK 0x00000080
+#define RG_RX_AGC_I_MSK 0xffffff7f
+#define RG_RX_AGC_SFT 7
+#define RG_RX_AGC_HI 7
+#define RG_RX_AGC_SZ 1
+#define RG_MODE_MSK 0x00000700
+#define RG_MODE_I_MSK 0xfffff8ff
+#define RG_MODE_SFT 8
+#define RG_MODE_HI 10
+#define RG_MODE_SZ 3
+#define RG_CAL_INDEX_MSK 0x0000f000
+#define RG_CAL_INDEX_I_MSK 0xffff0fff
+#define RG_CAL_INDEX_SFT 12
+#define RG_CAL_INDEX_HI 15
+#define RG_CAL_INDEX_SZ 4
+#define RG_RFG_MSK 0x00030000
+#define RG_RFG_I_MSK 0xfffcffff
+#define RG_RFG_SFT 16
+#define RG_RFG_HI 17
+#define RG_RFG_SZ 2
+#define RG_PGAG_MSK 0x003c0000
+#define RG_PGAG_I_MSK 0xffc3ffff
+#define RG_PGAG_SFT 18
+#define RG_PGAG_HI 21
+#define RG_PGAG_SZ 4
+#define RG_BW_HT40_MSK 0x00400000
+#define RG_BW_HT40_I_MSK 0xffbfffff
+#define RG_BW_HT40_SFT 22
+#define RG_BW_HT40_HI 22
+#define RG_BW_HT40_SZ 1
+#define RG_BW_MANUAL_MSK 0x00800000
+#define RG_BW_MANUAL_I_MSK 0xff7fffff
+#define RG_BW_MANUAL_SFT 23
+#define RG_BW_MANUAL_HI 23
+#define RG_BW_MANUAL_SZ 1
+#define RG_TX_GAIN_MSK 0x7f000000
+#define RG_TX_GAIN_I_MSK 0x80ffffff
+#define RG_TX_GAIN_SFT 24
+#define RG_TX_GAIN_HI 30
+#define RG_TX_GAIN_SZ 7
+#define RG_TX_TRSW_MANUAL_MSK 0x00000001
+#define RG_TX_TRSW_MANUAL_I_MSK 0xfffffffe
+#define RG_TX_TRSW_MANUAL_SFT 0
+#define RG_TX_TRSW_MANUAL_HI 0
+#define RG_TX_TRSW_MANUAL_SZ 1
+#define RG_EN_TX_TRSW_MSK 0x00000002
+#define RG_EN_TX_TRSW_I_MSK 0xfffffffd
+#define RG_EN_TX_TRSW_SFT 1
+#define RG_EN_TX_TRSW_HI 1
+#define RG_EN_TX_TRSW_SZ 1
+#define RG_RX_LNA_MANUAL_MSK 0x00000004
+#define RG_RX_LNA_MANUAL_I_MSK 0xfffffffb
+#define RG_RX_LNA_MANUAL_SFT 2
+#define RG_RX_LNA_MANUAL_HI 2
+#define RG_RX_LNA_MANUAL_SZ 1
+#define RG_EN_RX_LNA_MSK 0x00000008
+#define RG_EN_RX_LNA_I_MSK 0xfffffff7
+#define RG_EN_RX_LNA_SFT 3
+#define RG_EN_RX_LNA_HI 3
+#define RG_EN_RX_LNA_SZ 1
+#define RG_RX_MIXER_MANUAL_MSK 0x00000010
+#define RG_RX_MIXER_MANUAL_I_MSK 0xffffffef
+#define RG_RX_MIXER_MANUAL_SFT 4
+#define RG_RX_MIXER_MANUAL_HI 4
+#define RG_RX_MIXER_MANUAL_SZ 1
+#define RG_EN_RX_MIXER_MSK 0x00000020
+#define RG_EN_RX_MIXER_I_MSK 0xffffffdf
+#define RG_EN_RX_MIXER_SFT 5
+#define RG_EN_RX_MIXER_HI 5
+#define RG_EN_RX_MIXER_SZ 1
+#define RG_RX_DIV2_MANUAL_MSK 0x00000040
+#define RG_RX_DIV2_MANUAL_I_MSK 0xffffffbf
+#define RG_RX_DIV2_MANUAL_SFT 6
+#define RG_RX_DIV2_MANUAL_HI 6
+#define RG_RX_DIV2_MANUAL_SZ 1
+#define RG_EN_RX_DIV2_MSK 0x00000080
+#define RG_EN_RX_DIV2_I_MSK 0xffffff7f
+#define RG_EN_RX_DIV2_SFT 7
+#define RG_EN_RX_DIV2_HI 7
+#define RG_EN_RX_DIV2_SZ 1
+#define RG_RX_LOBUF_MANUAL_MSK 0x00000100
+#define RG_RX_LOBUF_MANUAL_I_MSK 0xfffffeff
+#define RG_RX_LOBUF_MANUAL_SFT 8
+#define RG_RX_LOBUF_MANUAL_HI 8
+#define RG_RX_LOBUF_MANUAL_SZ 1
+#define RG_EN_RX_LOBUF_MSK 0x00000200
+#define RG_EN_RX_LOBUF_I_MSK 0xfffffdff
+#define RG_EN_RX_LOBUF_SFT 9
+#define RG_EN_RX_LOBUF_HI 9
+#define RG_EN_RX_LOBUF_SZ 1
+#define RG_RX_TZ_MANUAL_MSK 0x00000400
+#define RG_RX_TZ_MANUAL_I_MSK 0xfffffbff
+#define RG_RX_TZ_MANUAL_SFT 10
+#define RG_RX_TZ_MANUAL_HI 10
+#define RG_RX_TZ_MANUAL_SZ 1
+#define RG_EN_RX_TZ_MSK 0x00000800
+#define RG_EN_RX_TZ_I_MSK 0xfffff7ff
+#define RG_EN_RX_TZ_SFT 11
+#define RG_EN_RX_TZ_HI 11
+#define RG_EN_RX_TZ_SZ 1
+#define RG_RX_FILTER_MANUAL_MSK 0x00001000
+#define RG_RX_FILTER_MANUAL_I_MSK 0xffffefff
+#define RG_RX_FILTER_MANUAL_SFT 12
+#define RG_RX_FILTER_MANUAL_HI 12
+#define RG_RX_FILTER_MANUAL_SZ 1
+#define RG_EN_RX_FILTER_MSK 0x00002000
+#define RG_EN_RX_FILTER_I_MSK 0xffffdfff
+#define RG_EN_RX_FILTER_SFT 13
+#define RG_EN_RX_FILTER_HI 13
+#define RG_EN_RX_FILTER_SZ 1
+#define RG_RX_ADC_MANUAL_MSK 0x00004000
+#define RG_RX_ADC_MANUAL_I_MSK 0xffffbfff
+#define RG_RX_ADC_MANUAL_SFT 14
+#define RG_RX_ADC_MANUAL_HI 14
+#define RG_RX_ADC_MANUAL_SZ 1
+#define RG_EN_RX_ADC_MSK 0x00008000
+#define RG_EN_RX_ADC_I_MSK 0xffff7fff
+#define RG_EN_RX_ADC_SFT 15
+#define RG_EN_RX_ADC_HI 15
+#define RG_EN_RX_ADC_SZ 1
+#define RG_RX_RSSI_MANUAL_MSK 0x00010000
+#define RG_RX_RSSI_MANUAL_I_MSK 0xfffeffff
+#define RG_RX_RSSI_MANUAL_SFT 16
+#define RG_RX_RSSI_MANUAL_HI 16
+#define RG_RX_RSSI_MANUAL_SZ 1
+#define RG_EN_RX_RSSI_MSK 0x00020000
+#define RG_EN_RX_RSSI_I_MSK 0xfffdffff
+#define RG_EN_RX_RSSI_SFT 17
+#define RG_EN_RX_RSSI_HI 17
+#define RG_EN_RX_RSSI_SZ 1
+#define RG_TX_PA_MANUAL_MSK 0x00040000
+#define RG_TX_PA_MANUAL_I_MSK 0xfffbffff
+#define RG_TX_PA_MANUAL_SFT 18
+#define RG_TX_PA_MANUAL_HI 18
+#define RG_TX_PA_MANUAL_SZ 1
+#define RG_EN_TX_PA_MSK 0x00080000
+#define RG_EN_TX_PA_I_MSK 0xfff7ffff
+#define RG_EN_TX_PA_SFT 19
+#define RG_EN_TX_PA_HI 19
+#define RG_EN_TX_PA_SZ 1
+#define RG_TX_MOD_MANUAL_MSK 0x00100000
+#define RG_TX_MOD_MANUAL_I_MSK 0xffefffff
+#define RG_TX_MOD_MANUAL_SFT 20
+#define RG_TX_MOD_MANUAL_HI 20
+#define RG_TX_MOD_MANUAL_SZ 1
+#define RG_EN_TX_MOD_MSK 0x00200000
+#define RG_EN_TX_MOD_I_MSK 0xffdfffff
+#define RG_EN_TX_MOD_SFT 21
+#define RG_EN_TX_MOD_HI 21
+#define RG_EN_TX_MOD_SZ 1
+#define RG_TX_DAC_MANUAL_MSK 0x00400000
+#define RG_TX_DAC_MANUAL_I_MSK 0xffbfffff
+#define RG_TX_DAC_MANUAL_SFT 22
+#define RG_TX_DAC_MANUAL_HI 22
+#define RG_TX_DAC_MANUAL_SZ 1
+#define RG_EN_TX_DAC_MSK 0x00800000
+#define RG_EN_TX_DAC_I_MSK 0xff7fffff
+#define RG_EN_TX_DAC_SFT 23
+#define RG_EN_TX_DAC_HI 23
+#define RG_EN_TX_DAC_SZ 1
+#define RG_TX_DIV2_MANUAL_MSK 0x01000000
+#define RG_TX_DIV2_MANUAL_I_MSK 0xfeffffff
+#define RG_TX_DIV2_MANUAL_SFT 24
+#define RG_TX_DIV2_MANUAL_HI 24
+#define RG_TX_DIV2_MANUAL_SZ 1
+#define RG_EN_TX_DIV2_MSK 0x02000000
+#define RG_EN_TX_DIV2_I_MSK 0xfdffffff
+#define RG_EN_TX_DIV2_SFT 25
+#define RG_EN_TX_DIV2_HI 25
+#define RG_EN_TX_DIV2_SZ 1
+#define RG_TX_DIV2_BUF_MANUAL_MSK 0x04000000
+#define RG_TX_DIV2_BUF_MANUAL_I_MSK 0xfbffffff
+#define RG_TX_DIV2_BUF_MANUAL_SFT 26
+#define RG_TX_DIV2_BUF_MANUAL_HI 26
+#define RG_TX_DIV2_BUF_MANUAL_SZ 1
+#define RG_EN_TX_DIV2_BUF_MSK 0x08000000
+#define RG_EN_TX_DIV2_BUF_I_MSK 0xf7ffffff
+#define RG_EN_TX_DIV2_BUF_SFT 27
+#define RG_EN_TX_DIV2_BUF_HI 27
+#define RG_EN_TX_DIV2_BUF_SZ 1
+#define RG_TX_BT_PA_MANUAL_MSK 0x10000000
+#define RG_TX_BT_PA_MANUAL_I_MSK 0xefffffff
+#define RG_TX_BT_PA_MANUAL_SFT 28
+#define RG_TX_BT_PA_MANUAL_HI 28
+#define RG_TX_BT_PA_MANUAL_SZ 1
+#define RG_EN_TX_BT_PA_MSK 0x20000000
+#define RG_EN_TX_BT_PA_I_MSK 0xdfffffff
+#define RG_EN_TX_BT_PA_SFT 29
+#define RG_EN_TX_BT_PA_HI 29
+#define RG_EN_TX_BT_PA_SZ 1
+#define RG_EN_IOT_ADC_BUF_MSK 0x40000000
+#define RG_EN_IOT_ADC_BUF_I_MSK 0xbfffffff
+#define RG_EN_IOT_ADC_BUF_SFT 30
+#define RG_EN_IOT_ADC_BUF_HI 30
+#define RG_EN_IOT_ADC_BUF_SZ 1
+#define RG_EN_IOT_ADC_MSK 0x80000000
+#define RG_EN_IOT_ADC_I_MSK 0x7fffffff
+#define RG_EN_IOT_ADC_SFT 31
+#define RG_EN_IOT_ADC_HI 31
+#define RG_EN_IOT_ADC_SZ 1
+#define RG_EN_LDO_RX_FE_MSK 0x00000001
+#define RG_EN_LDO_RX_FE_I_MSK 0xfffffffe
+#define RG_EN_LDO_RX_FE_SFT 0
+#define RG_EN_LDO_RX_FE_HI 0
+#define RG_EN_LDO_RX_FE_SZ 1
+#define RG_EN_LDO_AFE_MSK 0x00000002
+#define RG_EN_LDO_AFE_I_MSK 0xfffffffd
+#define RG_EN_LDO_AFE_SFT 1
+#define RG_EN_LDO_AFE_HI 1
+#define RG_EN_LDO_AFE_SZ 1
+#define RG_EN_IREF_RX_MSK 0x00000004
+#define RG_EN_IREF_RX_I_MSK 0xfffffffb
+#define RG_EN_IREF_RX_SFT 2
+#define RG_EN_IREF_RX_HI 2
+#define RG_EN_IREF_RX_SZ 1
+#define RG_TX_DAC_CAL_MANUAL_MSK 0x00000008
+#define RG_TX_DAC_CAL_MANUAL_I_MSK 0xfffffff7
+#define RG_TX_DAC_CAL_MANUAL_SFT 3
+#define RG_TX_DAC_CAL_MANUAL_HI 3
+#define RG_TX_DAC_CAL_MANUAL_SZ 1
+#define RG_EN_TX_DAC_CAL_MSK 0x00000010
+#define RG_EN_TX_DAC_CAL_I_MSK 0xffffffef
+#define RG_EN_TX_DAC_CAL_SFT 4
+#define RG_EN_TX_DAC_CAL_HI 4
+#define RG_EN_TX_DAC_CAL_SZ 1
+#define RG_RX_TZ_OUT_TRISTATE_MANUAL_MSK 0x00000020
+#define RG_RX_TZ_OUT_TRISTATE_MANUAL_I_MSK 0xffffffdf
+#define RG_RX_TZ_OUT_TRISTATE_MANUAL_SFT 5
+#define RG_RX_TZ_OUT_TRISTATE_MANUAL_HI 5
+#define RG_RX_TZ_OUT_TRISTATE_MANUAL_SZ 1
+#define RG_RX_TZ_OUT_TRISTATE_MSK 0x00000040
+#define RG_RX_TZ_OUT_TRISTATE_I_MSK 0xffffffbf
+#define RG_RX_TZ_OUT_TRISTATE_SFT 6
+#define RG_RX_TZ_OUT_TRISTATE_HI 6
+#define RG_RX_TZ_OUT_TRISTATE_SZ 1
+#define RG_TX_SELF_MIXER_MANUAL_MSK 0x00000080
+#define RG_TX_SELF_MIXER_MANUAL_I_MSK 0xffffff7f
+#define RG_TX_SELF_MIXER_MANUAL_SFT 7
+#define RG_TX_SELF_MIXER_MANUAL_HI 7
+#define RG_TX_SELF_MIXER_MANUAL_SZ 1
+#define RG_EN_TX_SELF_MIXER_MSK 0x00000100
+#define RG_EN_TX_SELF_MIXER_I_MSK 0xfffffeff
+#define RG_EN_TX_SELF_MIXER_SFT 8
+#define RG_EN_TX_SELF_MIXER_HI 8
+#define RG_EN_TX_SELF_MIXER_SZ 1
+#define RG_RX_IQCAL_MANUAL_MSK 0x00000200
+#define RG_RX_IQCAL_MANUAL_I_MSK 0xfffffdff
+#define RG_RX_IQCAL_MANUAL_SFT 9
+#define RG_RX_IQCAL_MANUAL_HI 9
+#define RG_RX_IQCAL_MANUAL_SZ 1
+#define RG_EN_RX_IQCAL_MSK 0x00000400
+#define RG_EN_RX_IQCAL_I_MSK 0xfffffbff
+#define RG_EN_RX_IQCAL_SFT 10
+#define RG_EN_RX_IQCAL_HI 10
+#define RG_EN_RX_IQCAL_SZ 1
+#define RG_TX_DPD_MANUAL_MSK 0x00000800
+#define RG_TX_DPD_MANUAL_I_MSK 0xfffff7ff
+#define RG_TX_DPD_MANUAL_SFT 11
+#define RG_TX_DPD_MANUAL_HI 11
+#define RG_TX_DPD_MANUAL_SZ 1
+#define RG_EN_TX_DPD_MSK 0x00001000
+#define RG_EN_TX_DPD_I_MSK 0xffffefff
+#define RG_EN_TX_DPD_SFT 12
+#define RG_EN_TX_DPD_HI 12
+#define RG_EN_TX_DPD_SZ 1
+#define RG_EN_TX_TSSI_MSK 0x00004000
+#define RG_EN_TX_TSSI_I_MSK 0xffffbfff
+#define RG_EN_TX_TSSI_SFT 14
+#define RG_EN_TX_TSSI_HI 14
+#define RG_EN_TX_TSSI_SZ 1
+#define RG_EN_SARADC_MSK 0x00008000
+#define RG_EN_SARADC_I_MSK 0xffff7fff
+#define RG_EN_SARADC_SFT 15
+#define RG_EN_SARADC_HI 15
+#define RG_EN_SARADC_SZ 1
+#define RG_EN_TX_VTOI_2ND_MSK 0x00010000
+#define RG_EN_TX_VTOI_2ND_I_MSK 0xfffeffff
+#define RG_EN_TX_VTOI_2ND_SFT 16
+#define RG_EN_TX_VTOI_2ND_HI 16
+#define RG_EN_TX_VTOI_2ND_SZ 1
+#define RG_TXLPF_BYPASS_MSK 0x00020000
+#define RG_TXLPF_BYPASS_I_MSK 0xfffdffff
+#define RG_TXLPF_BYPASS_SFT 17
+#define RG_TXLPF_BYPASS_HI 17
+#define RG_TXLPF_BYPASS_SZ 1
+#define RG_TX_EN_VOLTAGE_IN_MSK 0x00040000
+#define RG_TX_EN_VOLTAGE_IN_I_MSK 0xfffbffff
+#define RG_TX_EN_VOLTAGE_IN_SFT 18
+#define RG_TX_EN_VOLTAGE_IN_HI 18
+#define RG_TX_EN_VOLTAGE_IN_SZ 1
+#define RG_EN_TX_DAC_OUT_MSK 0x00080000
+#define RG_EN_TX_DAC_OUT_I_MSK 0xfff7ffff
+#define RG_EN_TX_DAC_OUT_SFT 19
+#define RG_EN_TX_DAC_OUT_HI 19
+#define RG_EN_TX_DAC_OUT_SZ 1
+#define RG_EN_TX_DAC_VOUT_MSK 0x00100000
+#define RG_EN_TX_DAC_VOUT_I_MSK 0xffefffff
+#define RG_EN_TX_DAC_VOUT_SFT 20
+#define RG_EN_TX_DAC_VOUT_HI 20
+#define RG_EN_TX_DAC_VOUT_SZ 1
+#define RG_RX_ABBOUT_TRI_STATE_MSK 0x00200000
+#define RG_RX_ABBOUT_TRI_STATE_I_MSK 0xffdfffff
+#define RG_RX_ABBOUT_TRI_STATE_SFT 21
+#define RG_RX_ABBOUT_TRI_STATE_HI 21
+#define RG_RX_ABBOUT_TRI_STATE_SZ 1
+#define RG_EN_RX_TESTNODE_MSK 0x00400000
+#define RG_EN_RX_TESTNODE_I_MSK 0xffbfffff
+#define RG_EN_RX_TESTNODE_SFT 22
+#define RG_EN_RX_TESTNODE_HI 22
+#define RG_EN_RX_TESTNODE_SZ 1
+#define RG_EN_RX_PADSW_MSK 0x00800000
+#define RG_EN_RX_PADSW_I_MSK 0xff7fffff
+#define RG_EN_RX_PADSW_SFT 23
+#define RG_EN_RX_PADSW_HI 23
+#define RG_EN_RX_PADSW_SZ 1
+#define RG_EN_LDO_RX_FE_FC_MSK 0x02000000
+#define RG_EN_LDO_RX_FE_FC_I_MSK 0xfdffffff
+#define RG_EN_LDO_RX_FE_FC_SFT 25
+#define RG_EN_LDO_RX_FE_FC_HI 25
+#define RG_EN_LDO_RX_FE_FC_SZ 1
+#define RG_EN_LDO_RX_AFE_FC_MSK 0x04000000
+#define RG_EN_LDO_RX_AFE_FC_I_MSK 0xfbffffff
+#define RG_EN_LDO_RX_AFE_FC_SFT 26
+#define RG_EN_LDO_RX_AFE_FC_HI 26
+#define RG_EN_LDO_RX_AFE_FC_SZ 1
+#define RG_EN_LDO_RX_FE_IQUP_MSK 0x08000000
+#define RG_EN_LDO_RX_FE_IQUP_I_MSK 0xf7ffffff
+#define RG_EN_LDO_RX_FE_IQUP_SFT 27
+#define RG_EN_LDO_RX_FE_IQUP_HI 27
+#define RG_EN_LDO_RX_FE_IQUP_SZ 1
+#define RG_EN_LDO_RX_AFE_IQUP_MSK 0x10000000
+#define RG_EN_LDO_RX_AFE_IQUP_I_MSK 0xefffffff
+#define RG_EN_LDO_RX_AFE_IQUP_SFT 28
+#define RG_EN_LDO_RX_AFE_IQUP_HI 28
+#define RG_EN_LDO_RX_AFE_IQUP_SZ 1
+#define RG_RX_SQDC_MSK 0xe0000000
+#define RG_RX_SQDC_I_MSK 0x1fffffff
+#define RG_RX_SQDC_SFT 29
+#define RG_RX_SQDC_HI 31
+#define RG_RX_SQDC_SZ 3
+#define RG_LDO_LEVEL_RX_FE_MSK 0x00000007
+#define RG_LDO_LEVEL_RX_FE_I_MSK 0xfffffff8
+#define RG_LDO_LEVEL_RX_FE_SFT 0
+#define RG_LDO_LEVEL_RX_FE_HI 2
+#define RG_LDO_LEVEL_RX_FE_SZ 3
+#define RG_EN_LDO_RX_FE_BYP_MSK 0x00000008
+#define RG_EN_LDO_RX_FE_BYP_I_MSK 0xfffffff7
+#define RG_EN_LDO_RX_FE_BYP_SFT 3
+#define RG_EN_LDO_RX_FE_BYP_HI 3
+#define RG_EN_LDO_RX_FE_BYP_SZ 1
+#define RG_LDO_LEVEL_AFE_MSK 0x00000070
+#define RG_LDO_LEVEL_AFE_I_MSK 0xffffff8f
+#define RG_LDO_LEVEL_AFE_SFT 4
+#define RG_LDO_LEVEL_AFE_HI 6
+#define RG_LDO_LEVEL_AFE_SZ 3
+#define RG_EN_LDO_RX_AFE_BYP_MSK 0x00000080
+#define RG_EN_LDO_RX_AFE_BYP_I_MSK 0xffffff7f
+#define RG_EN_LDO_RX_AFE_BYP_SFT 7
+#define RG_EN_LDO_RX_AFE_BYP_HI 7
+#define RG_EN_LDO_RX_AFE_BYP_SZ 1
+#define RG_SX_LDO_CP_LEVEL_MSK 0x00070000
+#define RG_SX_LDO_CP_LEVEL_I_MSK 0xfff8ffff
+#define RG_SX_LDO_CP_LEVEL_SFT 16
+#define RG_SX_LDO_CP_LEVEL_HI 18
+#define RG_SX_LDO_CP_LEVEL_SZ 3
+#define RG_EN_LDO_CP_BYP_MSK 0x00080000
+#define RG_EN_LDO_CP_BYP_I_MSK 0xfff7ffff
+#define RG_EN_LDO_CP_BYP_SFT 19
+#define RG_EN_LDO_CP_BYP_HI 19
+#define RG_EN_LDO_CP_BYP_SZ 1
+#define RG_SX_LDO_LO_LEVEL_MSK 0x00700000
+#define RG_SX_LDO_LO_LEVEL_I_MSK 0xff8fffff
+#define RG_SX_LDO_LO_LEVEL_SFT 20
+#define RG_SX_LDO_LO_LEVEL_HI 22
+#define RG_SX_LDO_LO_LEVEL_SZ 3
+#define RG_EN_LDO_LO_BYP_MSK 0x00800000
+#define RG_EN_LDO_LO_BYP_I_MSK 0xff7fffff
+#define RG_EN_LDO_LO_BYP_SFT 23
+#define RG_EN_LDO_LO_BYP_HI 23
+#define RG_EN_LDO_LO_BYP_SZ 1
+#define RG_SX_LDO_VCO_LEVEL_MSK 0x07000000
+#define RG_SX_LDO_VCO_LEVEL_I_MSK 0xf8ffffff
+#define RG_SX_LDO_VCO_LEVEL_SFT 24
+#define RG_SX_LDO_VCO_LEVEL_HI 26
+#define RG_SX_LDO_VCO_LEVEL_SZ 3
+#define RG_SX_LDO_DIV_LEVEL_MSK 0x70000000
+#define RG_SX_LDO_DIV_LEVEL_I_MSK 0x8fffffff
+#define RG_SX_LDO_DIV_LEVEL_SFT 28
+#define RG_SX_LDO_DIV_LEVEL_HI 30
+#define RG_SX_LDO_DIV_LEVEL_SZ 3
+#define RG_EN_LDO_DIV_BYP_MSK 0x80000000
+#define RG_EN_LDO_DIV_BYP_I_MSK 0x7fffffff
+#define RG_EN_LDO_DIV_BYP_SFT 31
+#define RG_EN_LDO_DIV_BYP_HI 31
+#define RG_EN_LDO_DIV_BYP_SZ 1
+#define RG_WF_RX_ABBCTUNE_MSK 0x0000003f
+#define RG_WF_RX_ABBCTUNE_I_MSK 0xffffffc0
+#define RG_WF_RX_ABBCTUNE_SFT 0
+#define RG_WF_RX_ABBCTUNE_HI 5
+#define RG_WF_RX_ABBCTUNE_SZ 6
+#define RG_WF_RX_TZ_CMZ_C_MSK 0x000000c0
+#define RG_WF_RX_TZ_CMZ_C_I_MSK 0xffffff3f
+#define RG_WF_RX_TZ_CMZ_C_SFT 6
+#define RG_WF_RX_TZ_CMZ_C_HI 7
+#define RG_WF_RX_TZ_CMZ_C_SZ 2
+#define RG_WF_RX_FILTERI_COARSE_MSK 0x00000300
+#define RG_WF_RX_FILTERI_COARSE_I_MSK 0xfffffcff
+#define RG_WF_RX_FILTERI_COARSE_SFT 8
+#define RG_WF_RX_FILTERI_COARSE_HI 9
+#define RG_WF_RX_FILTERI_COARSE_SZ 2
+#define RG_WF_RX_FILTERI1ST_MSK 0x00000c00
+#define RG_WF_RX_FILTERI1ST_I_MSK 0xfffff3ff
+#define RG_WF_RX_FILTERI1ST_SFT 10
+#define RG_WF_RX_FILTERI1ST_HI 11
+#define RG_WF_RX_FILTERI1ST_SZ 2
+#define RG_WF_RX_FILTERI2ND_MSK 0x00003000
+#define RG_WF_RX_FILTERI2ND_I_MSK 0xffffcfff
+#define RG_WF_RX_FILTERI2ND_SFT 12
+#define RG_WF_RX_FILTERI2ND_HI 13
+#define RG_WF_RX_FILTERI2ND_SZ 2
+#define RG_WF_RX_FILTERI3RD_MSK 0x0000c000
+#define RG_WF_RX_FILTERI3RD_I_MSK 0xffff3fff
+#define RG_WF_RX_FILTERI3RD_SFT 14
+#define RG_WF_RX_FILTERI3RD_HI 15
+#define RG_WF_RX_FILTERI3RD_SZ 2
+#define RG_WF_RX_ABBCFIX_MSK 0x00010000
+#define RG_WF_RX_ABBCFIX_I_MSK 0xfffeffff
+#define RG_WF_RX_ABBCFIX_SFT 16
+#define RG_WF_RX_ABBCFIX_HI 16
+#define RG_WF_RX_ABBCFIX_SZ 1
+#define RG_WF_RX_ABB_N_MODE_MSK 0x00020000
+#define RG_WF_RX_ABB_N_MODE_I_MSK 0xfffdffff
+#define RG_WF_RX_ABB_N_MODE_SFT 17
+#define RG_WF_RX_ABB_N_MODE_HI 17
+#define RG_WF_RX_ABB_N_MODE_SZ 1
+#define RG_WF_RX_ABB_BT_MODE_MSK 0x00040000
+#define RG_WF_RX_ABB_BT_MODE_I_MSK 0xfffbffff
+#define RG_WF_RX_ABB_BT_MODE_SFT 18
+#define RG_WF_RX_ABB_BT_MODE_HI 18
+#define RG_WF_RX_ABB_BT_MODE_SZ 1
+#define RG_WF_RX_ABB_IDIV3_MSK 0x00080000
+#define RG_WF_RX_ABB_IDIV3_I_MSK 0xfff7ffff
+#define RG_WF_RX_ABB_IDIV3_SFT 19
+#define RG_WF_RX_ABB_IDIV3_HI 19
+#define RG_WF_RX_ABB_IDIV3_SZ 1
+#define RG_WF_RX_EN_IDACA_COARSE_MSK 0x00100000
+#define RG_WF_RX_EN_IDACA_COARSE_I_MSK 0xffefffff
+#define RG_WF_RX_EN_IDACA_COARSE_SFT 20
+#define RG_WF_RX_EN_IDACA_COARSE_HI 20
+#define RG_WF_RX_EN_IDACA_COARSE_SZ 1
+#define RG_WF_RX_EN_LOOPA_MSK 0x00200000
+#define RG_WF_RX_EN_LOOPA_I_MSK 0xffdfffff
+#define RG_WF_RX_EN_LOOPA_SFT 21
+#define RG_WF_RX_EN_LOOPA_HI 21
+#define RG_WF_RX_EN_LOOPA_SZ 1
+#define RG_WF_RX_TZ_CMZ_R_MSK 0x00c00000
+#define RG_WF_RX_TZ_CMZ_R_I_MSK 0xff3fffff
+#define RG_WF_RX_TZ_CMZ_R_SFT 22
+#define RG_WF_RX_TZ_CMZ_R_HI 23
+#define RG_WF_RX_TZ_CMZ_R_SZ 2
+#define RG_WF_RX_FILTERVCM_MSK 0x07000000
+#define RG_WF_RX_FILTERVCM_I_MSK 0xf8ffffff
+#define RG_WF_RX_FILTERVCM_SFT 24
+#define RG_WF_RX_FILTERVCM_HI 26
+#define RG_WF_RX_FILTERVCM_SZ 3
+#define RG_WF_RX_OUTVCM_MSK 0x70000000
+#define RG_WF_RX_OUTVCM_I_MSK 0x8fffffff
+#define RG_WF_RX_OUTVCM_SFT 28
+#define RG_WF_RX_OUTVCM_HI 30
+#define RG_WF_RX_OUTVCM_SZ 3
+#define RG_WF_N_RX_ABBCTUNE_MSK 0x0000003f
+#define RG_WF_N_RX_ABBCTUNE_I_MSK 0xffffffc0
+#define RG_WF_N_RX_ABBCTUNE_SFT 0
+#define RG_WF_N_RX_ABBCTUNE_HI 5
+#define RG_WF_N_RX_ABBCTUNE_SZ 6
+#define RG_WF_N_RX_TZ_CMZ_C_MSK 0x000000c0
+#define RG_WF_N_RX_TZ_CMZ_C_I_MSK 0xffffff3f
+#define RG_WF_N_RX_TZ_CMZ_C_SFT 6
+#define RG_WF_N_RX_TZ_CMZ_C_HI 7
+#define RG_WF_N_RX_TZ_CMZ_C_SZ 2
+#define RG_WF_N_RX_FILTERI_COARSE_MSK 0x00000300
+#define RG_WF_N_RX_FILTERI_COARSE_I_MSK 0xfffffcff
+#define RG_WF_N_RX_FILTERI_COARSE_SFT 8
+#define RG_WF_N_RX_FILTERI_COARSE_HI 9
+#define RG_WF_N_RX_FILTERI_COARSE_SZ 2
+#define RG_WF_N_RX_FILTERI1ST_MSK 0x00000c00
+#define RG_WF_N_RX_FILTERI1ST_I_MSK 0xfffff3ff
+#define RG_WF_N_RX_FILTERI1ST_SFT 10
+#define RG_WF_N_RX_FILTERI1ST_HI 11
+#define RG_WF_N_RX_FILTERI1ST_SZ 2
+#define RG_WF_N_RX_FILTERI2ND_MSK 0x00003000
+#define RG_WF_N_RX_FILTERI2ND_I_MSK 0xffffcfff
+#define RG_WF_N_RX_FILTERI2ND_SFT 12
+#define RG_WF_N_RX_FILTERI2ND_HI 13
+#define RG_WF_N_RX_FILTERI2ND_SZ 2
+#define RG_WF_N_RX_FILTERI3RD_MSK 0x0000c000
+#define RG_WF_N_RX_FILTERI3RD_I_MSK 0xffff3fff
+#define RG_WF_N_RX_FILTERI3RD_SFT 14
+#define RG_WF_N_RX_FILTERI3RD_HI 15
+#define RG_WF_N_RX_FILTERI3RD_SZ 2
+#define RG_WF_N_RX_ABBCFIX_MSK 0x00010000
+#define RG_WF_N_RX_ABBCFIX_I_MSK 0xfffeffff
+#define RG_WF_N_RX_ABBCFIX_SFT 16
+#define RG_WF_N_RX_ABBCFIX_HI 16
+#define RG_WF_N_RX_ABBCFIX_SZ 1
+#define RG_WF_N_RX_ABB_N_MODE_MSK 0x00020000
+#define RG_WF_N_RX_ABB_N_MODE_I_MSK 0xfffdffff
+#define RG_WF_N_RX_ABB_N_MODE_SFT 17
+#define RG_WF_N_RX_ABB_N_MODE_HI 17
+#define RG_WF_N_RX_ABB_N_MODE_SZ 1
+#define RG_WF_N_RX_ABB_BT_MODE_MSK 0x00040000
+#define RG_WF_N_RX_ABB_BT_MODE_I_MSK 0xfffbffff
+#define RG_WF_N_RX_ABB_BT_MODE_SFT 18
+#define RG_WF_N_RX_ABB_BT_MODE_HI 18
+#define RG_WF_N_RX_ABB_BT_MODE_SZ 1
+#define RG_WF_N_RX_ABB_IDIV3_MSK 0x00080000
+#define RG_WF_N_RX_ABB_IDIV3_I_MSK 0xfff7ffff
+#define RG_WF_N_RX_ABB_IDIV3_SFT 19
+#define RG_WF_N_RX_ABB_IDIV3_HI 19
+#define RG_WF_N_RX_ABB_IDIV3_SZ 1
+#define RG_WF_N_RX_EN_IDACA_COARSE_MSK 0x00100000
+#define RG_WF_N_RX_EN_IDACA_COARSE_I_MSK 0xffefffff
+#define RG_WF_N_RX_EN_IDACA_COARSE_SFT 20
+#define RG_WF_N_RX_EN_IDACA_COARSE_HI 20
+#define RG_WF_N_RX_EN_IDACA_COARSE_SZ 1
+#define RG_WF_N_RX_EN_LOOPA_MSK 0x00200000
+#define RG_WF_N_RX_EN_LOOPA_I_MSK 0xffdfffff
+#define RG_WF_N_RX_EN_LOOPA_SFT 21
+#define RG_WF_N_RX_EN_LOOPA_HI 21
+#define RG_WF_N_RX_EN_LOOPA_SZ 1
+#define RG_WF_N_RX_TZ_CMZ_R_MSK 0x00c00000
+#define RG_WF_N_RX_TZ_CMZ_R_I_MSK 0xff3fffff
+#define RG_WF_N_RX_TZ_CMZ_R_SFT 22
+#define RG_WF_N_RX_TZ_CMZ_R_HI 23
+#define RG_WF_N_RX_TZ_CMZ_R_SZ 2
+#define RG_WF_N_RX_FILTERVCM_MSK 0x07000000
+#define RG_WF_N_RX_FILTERVCM_I_MSK 0xf8ffffff
+#define RG_WF_N_RX_FILTERVCM_SFT 24
+#define RG_WF_N_RX_FILTERVCM_HI 26
+#define RG_WF_N_RX_FILTERVCM_SZ 3
+#define RG_WF_N_RX_OUTVCM_MSK 0x70000000
+#define RG_WF_N_RX_OUTVCM_I_MSK 0x8fffffff
+#define RG_WF_N_RX_OUTVCM_SFT 28
+#define RG_WF_N_RX_OUTVCM_HI 30
+#define RG_WF_N_RX_OUTVCM_SZ 3
+#define RG_BT_RX_ABBCTUNE_MSK 0x0000003f
+#define RG_BT_RX_ABBCTUNE_I_MSK 0xffffffc0
+#define RG_BT_RX_ABBCTUNE_SFT 0
+#define RG_BT_RX_ABBCTUNE_HI 5
+#define RG_BT_RX_ABBCTUNE_SZ 6
+#define RG_BT_RX_TZ_CMZ_C_MSK 0x000000c0
+#define RG_BT_RX_TZ_CMZ_C_I_MSK 0xffffff3f
+#define RG_BT_RX_TZ_CMZ_C_SFT 6
+#define RG_BT_RX_TZ_CMZ_C_HI 7
+#define RG_BT_RX_TZ_CMZ_C_SZ 2
+#define RG_BT_RX_FILTERI_COARSE_MSK 0x00000300
+#define RG_BT_RX_FILTERI_COARSE_I_MSK 0xfffffcff
+#define RG_BT_RX_FILTERI_COARSE_SFT 8
+#define RG_BT_RX_FILTERI_COARSE_HI 9
+#define RG_BT_RX_FILTERI_COARSE_SZ 2
+#define RG_BT_RX_FILTERI1ST_MSK 0x00000c00
+#define RG_BT_RX_FILTERI1ST_I_MSK 0xfffff3ff
+#define RG_BT_RX_FILTERI1ST_SFT 10
+#define RG_BT_RX_FILTERI1ST_HI 11
+#define RG_BT_RX_FILTERI1ST_SZ 2
+#define RG_BT_RX_FILTERI2ND_MSK 0x00003000
+#define RG_BT_RX_FILTERI2ND_I_MSK 0xffffcfff
+#define RG_BT_RX_FILTERI2ND_SFT 12
+#define RG_BT_RX_FILTERI2ND_HI 13
+#define RG_BT_RX_FILTERI2ND_SZ 2
+#define RG_BT_RX_FILTERI3RD_MSK 0x0000c000
+#define RG_BT_RX_FILTERI3RD_I_MSK 0xffff3fff
+#define RG_BT_RX_FILTERI3RD_SFT 14
+#define RG_BT_RX_FILTERI3RD_HI 15
+#define RG_BT_RX_FILTERI3RD_SZ 2
+#define RG_BT_RX_ABBCFIX_MSK 0x00010000
+#define RG_BT_RX_ABBCFIX_I_MSK 0xfffeffff
+#define RG_BT_RX_ABBCFIX_SFT 16
+#define RG_BT_RX_ABBCFIX_HI 16
+#define RG_BT_RX_ABBCFIX_SZ 1
+#define RG_BT_RX_ABB_N_MODE_MSK 0x00020000
+#define RG_BT_RX_ABB_N_MODE_I_MSK 0xfffdffff
+#define RG_BT_RX_ABB_N_MODE_SFT 17
+#define RG_BT_RX_ABB_N_MODE_HI 17
+#define RG_BT_RX_ABB_N_MODE_SZ 1
+#define RG_BT_RX_ABB_BT_MODE_MSK 0x00040000
+#define RG_BT_RX_ABB_BT_MODE_I_MSK 0xfffbffff
+#define RG_BT_RX_ABB_BT_MODE_SFT 18
+#define RG_BT_RX_ABB_BT_MODE_HI 18
+#define RG_BT_RX_ABB_BT_MODE_SZ 1
+#define RG_BT_RX_ABB_IDIV3_MSK 0x00080000
+#define RG_BT_RX_ABB_IDIV3_I_MSK 0xfff7ffff
+#define RG_BT_RX_ABB_IDIV3_SFT 19
+#define RG_BT_RX_ABB_IDIV3_HI 19
+#define RG_BT_RX_ABB_IDIV3_SZ 1
+#define RG_BT_RX_EN_IDACA_COARSE_MSK 0x00100000
+#define RG_BT_RX_EN_IDACA_COARSE_I_MSK 0xffefffff
+#define RG_BT_RX_EN_IDACA_COARSE_SFT 20
+#define RG_BT_RX_EN_IDACA_COARSE_HI 20
+#define RG_BT_RX_EN_IDACA_COARSE_SZ 1
+#define RG_BT_RX_EN_LOOPA_MSK 0x00200000
+#define RG_BT_RX_EN_LOOPA_I_MSK 0xffdfffff
+#define RG_BT_RX_EN_LOOPA_SFT 21
+#define RG_BT_RX_EN_LOOPA_HI 21
+#define RG_BT_RX_EN_LOOPA_SZ 1
+#define RG_BT_RX_TZ_CMZ_R_MSK 0x00c00000
+#define RG_BT_RX_TZ_CMZ_R_I_MSK 0xff3fffff
+#define RG_BT_RX_TZ_CMZ_R_SFT 22
+#define RG_BT_RX_TZ_CMZ_R_HI 23
+#define RG_BT_RX_TZ_CMZ_R_SZ 2
+#define RG_BT_RX_FILTERVCM_MSK 0x07000000
+#define RG_BT_RX_FILTERVCM_I_MSK 0xf8ffffff
+#define RG_BT_RX_FILTERVCM_SFT 24
+#define RG_BT_RX_FILTERVCM_HI 26
+#define RG_BT_RX_FILTERVCM_SZ 3
+#define RG_BT_RX_OUTVCM_MSK 0x70000000
+#define RG_BT_RX_OUTVCM_I_MSK 0x8fffffff
+#define RG_BT_RX_OUTVCM_SFT 28
+#define RG_BT_RX_OUTVCM_HI 30
+#define RG_BT_RX_OUTVCM_SZ 3
+#define RG_RX_ADCRSSI_VCM_MSK 0x00000003
+#define RG_RX_ADCRSSI_VCM_I_MSK 0xfffffffc
+#define RG_RX_ADCRSSI_VCM_SFT 0
+#define RG_RX_ADCRSSI_VCM_HI 1
+#define RG_RX_ADCRSSI_VCM_SZ 2
+#define RG_RX_REC_LPFCORNER_MSK 0x0000000c
+#define RG_RX_REC_LPFCORNER_I_MSK 0xfffffff3
+#define RG_RX_REC_LPFCORNER_SFT 2
+#define RG_RX_REC_LPFCORNER_HI 3
+#define RG_RX_REC_LPFCORNER_SZ 2
+#define RG_RX_ADCRSSI_CLKSEL_MSK 0x00000010
+#define RG_RX_ADCRSSI_CLKSEL_I_MSK 0xffffffef
+#define RG_RX_ADCRSSI_CLKSEL_SFT 4
+#define RG_RX_ADCRSSI_CLKSEL_HI 4
+#define RG_RX_ADCRSSI_CLKSEL_SZ 1
+#define RG_RSSI_CLOCK_GATING_MSK 0x00000020
+#define RG_RSSI_CLOCK_GATING_I_MSK 0xffffffdf
+#define RG_RSSI_CLOCK_GATING_SFT 5
+#define RG_RSSI_CLOCK_GATING_HI 5
+#define RG_RSSI_CLOCK_GATING_SZ 1
+#define RG_RX_IDACA_COARSE_PMOS_ON_MSK 0x00000040
+#define RG_RX_IDACA_COARSE_PMOS_ON_I_MSK 0xffffffbf
+#define RG_RX_IDACA_COARSE_PMOS_ON_SFT 6
+#define RG_RX_IDACA_COARSE_PMOS_ON_HI 6
+#define RG_RX_IDACA_COARSE_PMOS_ON_SZ 1
+#define RG_TX_DPDGM_BIAS_MSK 0x00000f00
+#define RG_TX_DPDGM_BIAS_I_MSK 0xfffff0ff
+#define RG_TX_DPDGM_BIAS_SFT 8
+#define RG_TX_DPDGM_BIAS_HI 11
+#define RG_TX_DPDGM_BIAS_SZ 4
+#define RG_TX_DPD_DIV_MSK 0x0000f000
+#define RG_TX_DPD_DIV_I_MSK 0xffff0fff
+#define RG_TX_DPD_DIV_SFT 12
+#define RG_TX_DPD_DIV_HI 15
+#define RG_TX_DPD_DIV_SZ 4
+#define RG_TX_TSSI_BIAS_MSK 0x00070000
+#define RG_TX_TSSI_BIAS_I_MSK 0xfff8ffff
+#define RG_TX_TSSI_BIAS_SFT 16
+#define RG_TX_TSSI_BIAS_HI 18
+#define RG_TX_TSSI_BIAS_SZ 3
+#define RG_TX_TSSI_DIV_MSK 0x00380000
+#define RG_TX_TSSI_DIV_I_MSK 0xffc7ffff
+#define RG_TX_TSSI_DIV_SFT 19
+#define RG_TX_TSSI_DIV_HI 21
+#define RG_TX_TSSI_DIV_SZ 3
+#define RG_TX_TSSI_TEST_MSK 0x00c00000
+#define RG_TX_TSSI_TEST_I_MSK 0xff3fffff
+#define RG_TX_TSSI_TEST_SFT 22
+#define RG_TX_TSSI_TEST_HI 23
+#define RG_TX_TSSI_TEST_SZ 2
+#define RG_TX_TSSI_TESTMODE_MSK 0x01000000
+#define RG_TX_TSSI_TESTMODE_I_MSK 0xfeffffff
+#define RG_TX_TSSI_TESTMODE_SFT 24
+#define RG_TX_TSSI_TESTMODE_HI 24
+#define RG_TX_TSSI_TESTMODE_SZ 1
+#define RG_EN_RX_RSSI_TESTNODE_MSK 0x0e000000
+#define RG_EN_RX_RSSI_TESTNODE_I_MSK 0xf1ffffff
+#define RG_EN_RX_RSSI_TESTNODE_SFT 25
+#define RG_EN_RX_RSSI_TESTNODE_HI 27
+#define RG_EN_RX_RSSI_TESTNODE_SZ 3
+#define RG_RX_LNA_TRI_SEL_MSK 0x30000000
+#define RG_RX_LNA_TRI_SEL_I_MSK 0xcfffffff
+#define RG_RX_LNA_TRI_SEL_SFT 28
+#define RG_RX_LNA_TRI_SEL_HI 29
+#define RG_RX_LNA_TRI_SEL_SZ 2
+#define RG_RX_LNA_SETTLE_MSK 0xc0000000
+#define RG_RX_LNA_SETTLE_I_MSK 0x3fffffff
+#define RG_RX_LNA_SETTLE_SFT 30
+#define RG_RX_LNA_SETTLE_HI 31
+#define RG_RX_LNA_SETTLE_SZ 2
+#define RG_WF_TXPGA_CAPSW_MSK 0x00000003
+#define RG_WF_TXPGA_CAPSW_I_MSK 0xfffffffc
+#define RG_WF_TXPGA_CAPSW_SFT 0
+#define RG_WF_TXPGA_CAPSW_HI 1
+#define RG_WF_TXPGA_CAPSW_SZ 2
+#define RG_WF_TX_DIV_VSET_MSK 0x0000000c
+#define RG_WF_TX_DIV_VSET_I_MSK 0xfffffff3
+#define RG_WF_TX_DIV_VSET_SFT 2
+#define RG_WF_TX_DIV_VSET_HI 3
+#define RG_WF_TX_DIV_VSET_SZ 2
+#define RG_WF_TX_LOBUF_VSET_MSK 0x00000030
+#define RG_WF_TX_LOBUF_VSET_I_MSK 0xffffffcf
+#define RG_WF_TX_LOBUF_VSET_SFT 4
+#define RG_WF_TX_LOBUF_VSET_HI 5
+#define RG_WF_TX_LOBUF_VSET_SZ 2
+#define RG_WF_TXMOD_GMCELL_FINE_MSK 0x00000700
+#define RG_WF_TXMOD_GMCELL_FINE_I_MSK 0xfffff8ff
+#define RG_WF_TXMOD_GMCELL_FINE_SFT 8
+#define RG_WF_TXMOD_GMCELL_FINE_HI 10
+#define RG_WF_TXMOD_GMCELL_FINE_SZ 3
+#define RG_BT_TXPGA_CAPSW_MSK 0x00003000
+#define RG_BT_TXPGA_CAPSW_I_MSK 0xffffcfff
+#define RG_BT_TXPGA_CAPSW_SFT 12
+#define RG_BT_TXPGA_CAPSW_HI 13
+#define RG_BT_TXPGA_CAPSW_SZ 2
+#define RG_BT_TX_DIV_VSET_MSK 0x0000c000
+#define RG_BT_TX_DIV_VSET_I_MSK 0xffff3fff
+#define RG_BT_TX_DIV_VSET_SFT 14
+#define RG_BT_TX_DIV_VSET_HI 15
+#define RG_BT_TX_DIV_VSET_SZ 2
+#define RG_BT_TX_LOBUF_VSET_MSK 0x00030000
+#define RG_BT_TX_LOBUF_VSET_I_MSK 0xfffcffff
+#define RG_BT_TX_LOBUF_VSET_SFT 16
+#define RG_BT_TX_LOBUF_VSET_HI 17
+#define RG_BT_TX_LOBUF_VSET_SZ 2
+#define RG_BT_TXMOD_GMCELL_FINE_MSK 0x00700000
+#define RG_BT_TXMOD_GMCELL_FINE_I_MSK 0xff8fffff
+#define RG_BT_TXMOD_GMCELL_FINE_SFT 20
+#define RG_BT_TXMOD_GMCELL_FINE_HI 22
+#define RG_BT_TXMOD_GMCELL_FINE_SZ 3
+#define RG_WF_PACELL_EN_MSK 0x00000007
+#define RG_WF_PACELL_EN_I_MSK 0xfffffff8
+#define RG_WF_PACELL_EN_SFT 0
+#define RG_WF_PACELL_EN_HI 2
+#define RG_WF_PACELL_EN_SZ 3
+#define RG_WF_PABIAS_CTRL_MSK 0x000000f0
+#define RG_WF_PABIAS_CTRL_I_MSK 0xffffff0f
+#define RG_WF_PABIAS_CTRL_SFT 4
+#define RG_WF_PABIAS_CTRL_HI 7
+#define RG_WF_PABIAS_CTRL_SZ 4
+#define RG_WF_TX_PA1_VCAS_MSK 0x00000700
+#define RG_WF_TX_PA1_VCAS_I_MSK 0xfffff8ff
+#define RG_WF_TX_PA1_VCAS_SFT 8
+#define RG_WF_TX_PA1_VCAS_HI 10
+#define RG_WF_TX_PA1_VCAS_SZ 3
+#define RG_WF_TX_PA2_VCAS_MSK 0x00007000
+#define RG_WF_TX_PA2_VCAS_I_MSK 0xffff8fff
+#define RG_WF_TX_PA2_VCAS_SFT 12
+#define RG_WF_TX_PA2_VCAS_HI 14
+#define RG_WF_TX_PA2_VCAS_SZ 3
+#define RG_WF_TX_PA3_VCAS_MSK 0x00070000
+#define RG_WF_TX_PA3_VCAS_I_MSK 0xfff8ffff
+#define RG_WF_TX_PA3_VCAS_SFT 16
+#define RG_WF_TX_PA3_VCAS_HI 18
+#define RG_WF_TX_PA3_VCAS_SZ 3
+#define RG_WF_BTPASW_MSK 0x00100000
+#define RG_WF_BTPASW_I_MSK 0xffefffff
+#define RG_WF_BTPASW_SFT 20
+#define RG_WF_BTPASW_HI 20
+#define RG_WF_BTPASW_SZ 1
+#define RG_BTRX_BTPASW_MSK 0x00200000
+#define RG_BTRX_BTPASW_I_MSK 0xffdfffff
+#define RG_BTRX_BTPASW_SFT 21
+#define RG_BTRX_BTPASW_HI 21
+#define RG_BTRX_BTPASW_SZ 1
+#define RG_BTTX_BTPASW_MSK 0x00400000
+#define RG_BTTX_BTPASW_I_MSK 0xffbfffff
+#define RG_BTTX_BTPASW_SFT 22
+#define RG_BTTX_BTPASW_HI 22
+#define RG_BTTX_BTPASW_SZ 1
+#define RG_BT_PABIAS_2X_MSK 0x00800000
+#define RG_BT_PABIAS_2X_I_MSK 0xff7fffff
+#define RG_BT_PABIAS_2X_SFT 23
+#define RG_BT_PABIAS_2X_HI 23
+#define RG_BT_PABIAS_2X_SZ 1
+#define RG_BT_PABIAS_CTRL_MSK 0x0f000000
+#define RG_BT_PABIAS_CTRL_I_MSK 0xf0ffffff
+#define RG_BT_PABIAS_CTRL_SFT 24
+#define RG_BT_PABIAS_CTRL_HI 27
+#define RG_BT_PABIAS_CTRL_SZ 4
+#define RG_BT_TX_PA_VCAS_MSK 0x70000000
+#define RG_BT_TX_PA_VCAS_I_MSK 0x8fffffff
+#define RG_BT_TX_PA_VCAS_SFT 28
+#define RG_BT_TX_PA_VCAS_HI 30
+#define RG_BT_TX_PA_VCAS_SZ 3
+#define RG_TXPGA_MAIN_MSK 0x0000003f
+#define RG_TXPGA_MAIN_I_MSK 0xffffffc0
+#define RG_TXPGA_MAIN_SFT 0
+#define RG_TXPGA_MAIN_HI 5
+#define RG_TXPGA_MAIN_SZ 6
+#define RG_TXPGA_STEER_MSK 0x00000fc0
+#define RG_TXPGA_STEER_I_MSK 0xfffff03f
+#define RG_TXPGA_STEER_SFT 6
+#define RG_TXPGA_STEER_HI 11
+#define RG_TXPGA_STEER_SZ 6
+#define RG_TXMOD_GMCELL_MSK 0x00003000
+#define RG_TXMOD_GMCELL_I_MSK 0xffffcfff
+#define RG_TXMOD_GMCELL_SFT 12
+#define RG_TXMOD_GMCELL_HI 13
+#define RG_TXMOD_GMCELL_SZ 2
+#define RG_TXLPF_GMCELL_MSK 0x0000c000
+#define RG_TXLPF_GMCELL_I_MSK 0xffff3fff
+#define RG_TXLPF_GMCELL_SFT 14
+#define RG_TXLPF_GMCELL_HI 15
+#define RG_TXLPF_GMCELL_SZ 2
+#define RG_WF_TX_GAIN_OFFSET_MSK 0x000f0000
+#define RG_WF_TX_GAIN_OFFSET_I_MSK 0xfff0ffff
+#define RG_WF_TX_GAIN_OFFSET_SFT 16
+#define RG_WF_TX_GAIN_OFFSET_HI 19
+#define RG_WF_TX_GAIN_OFFSET_SZ 4
+#define RG_BT_TX_GAIN_OFFSET_MSK 0x00f00000
+#define RG_BT_TX_GAIN_OFFSET_I_MSK 0xff0fffff
+#define RG_BT_TX_GAIN_OFFSET_SFT 20
+#define RG_BT_TX_GAIN_OFFSET_HI 23
+#define RG_BT_TX_GAIN_OFFSET_SZ 4
+#define RG_TX_VTOI_CURRENT_MSK 0x03000000
+#define RG_TX_VTOI_CURRENT_I_MSK 0xfcffffff
+#define RG_TX_VTOI_CURRENT_SFT 24
+#define RG_TX_VTOI_CURRENT_HI 25
+#define RG_TX_VTOI_CURRENT_SZ 2
+#define RG_TX_VTOI_GM_MSK 0x0c000000
+#define RG_TX_VTOI_GM_I_MSK 0xf3ffffff
+#define RG_TX_VTOI_GM_SFT 26
+#define RG_TX_VTOI_GM_HI 27
+#define RG_TX_VTOI_GM_SZ 2
+#define RG_TX_VTOI_OPTION_MSK 0x30000000
+#define RG_TX_VTOI_OPTION_I_MSK 0xcfffffff
+#define RG_TX_VTOI_OPTION_SFT 28
+#define RG_TX_VTOI_OPTION_HI 29
+#define RG_TX_VTOI_OPTION_SZ 2
+#define RG_TX_VTOI_FS_MSK 0x40000000
+#define RG_TX_VTOI_FS_I_MSK 0xbfffffff
+#define RG_TX_VTOI_FS_SFT 30
+#define RG_TX_VTOI_FS_HI 30
+#define RG_TX_VTOI_FS_SZ 1
+#define RG_WF_RX_HG_LNA_GC_MSK 0x00000003
+#define RG_WF_RX_HG_LNA_GC_I_MSK 0xfffffffc
+#define RG_WF_RX_HG_LNA_GC_SFT 0
+#define RG_WF_RX_HG_LNA_GC_HI 1
+#define RG_WF_RX_HG_LNA_GC_SZ 2
+#define RG_WF_RX_HG_TZ_GC_MSK 0x0000000c
+#define RG_WF_RX_HG_TZ_GC_I_MSK 0xfffffff3
+#define RG_WF_RX_HG_TZ_GC_SFT 2
+#define RG_WF_RX_HG_TZ_GC_HI 3
+#define RG_WF_RX_HG_TZ_GC_SZ 2
+#define RG_WF_RX_HG_LNAHGN_BIAS_MSK 0x000000f0
+#define RG_WF_RX_HG_LNAHGN_BIAS_I_MSK 0xffffff0f
+#define RG_WF_RX_HG_LNAHGN_BIAS_SFT 4
+#define RG_WF_RX_HG_LNAHGN_BIAS_HI 7
+#define RG_WF_RX_HG_LNAHGN_BIAS_SZ 4
+#define RG_WF_RX_HG_LNAHGP_BIAS_MSK 0x00000f00
+#define RG_WF_RX_HG_LNAHGP_BIAS_I_MSK 0xfffff0ff
+#define RG_WF_RX_HG_LNAHGP_BIAS_SFT 8
+#define RG_WF_RX_HG_LNAHGP_BIAS_HI 11
+#define RG_WF_RX_HG_LNAHGP_BIAS_SZ 4
+#define RG_WF_RX_HG_LNALG_BIAS_MSK 0x0000f000
+#define RG_WF_RX_HG_LNALG_BIAS_I_MSK 0xffff0fff
+#define RG_WF_RX_HG_LNALG_BIAS_SFT 12
+#define RG_WF_RX_HG_LNALG_BIAS_HI 15
+#define RG_WF_RX_HG_LNALG_BIAS_SZ 4
+#define RG_WF_RX_HG_TZ_CAP_MSK 0x00070000
+#define RG_WF_RX_HG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_WF_RX_HG_TZ_CAP_SFT 16
+#define RG_WF_RX_HG_TZ_CAP_HI 18
+#define RG_WF_RX_HG_TZ_CAP_SZ 3
+#define RG_WF_RX_HG_TZ_GC_BOOST_MSK 0x00300000
+#define RG_WF_RX_HG_TZ_GC_BOOST_I_MSK 0xffcfffff
+#define RG_WF_RX_HG_TZ_GC_BOOST_SFT 20
+#define RG_WF_RX_HG_TZ_GC_BOOST_HI 21
+#define RG_WF_RX_HG_TZ_GC_BOOST_SZ 2
+#define RG_WF_RX_HG_DIV2_CORE_MSK 0x00c00000
+#define RG_WF_RX_HG_DIV2_CORE_I_MSK 0xff3fffff
+#define RG_WF_RX_HG_DIV2_CORE_SFT 22
+#define RG_WF_RX_HG_DIV2_CORE_HI 23
+#define RG_WF_RX_HG_DIV2_CORE_SZ 2
+#define RG_WF_RX_HG_LOBUF_MSK 0x03000000
+#define RG_WF_RX_HG_LOBUF_I_MSK 0xfcffffff
+#define RG_WF_RX_HG_LOBUF_SFT 24
+#define RG_WF_RX_HG_LOBUF_HI 25
+#define RG_WF_RX_HG_LOBUF_SZ 2
+#define RG_WF_RX_HG_TZI_MSK 0x1c000000
+#define RG_WF_RX_HG_TZI_I_MSK 0xe3ffffff
+#define RG_WF_RX_HG_TZI_SFT 26
+#define RG_WF_RX_HG_TZI_HI 28
+#define RG_WF_RX_HG_TZI_SZ 3
+#define RG_WF_RX_HG_TZ_VCM_MSK 0xe0000000
+#define RG_WF_RX_HG_TZ_VCM_I_MSK 0x1fffffff
+#define RG_WF_RX_HG_TZ_VCM_SFT 29
+#define RG_WF_RX_HG_TZ_VCM_HI 31
+#define RG_WF_RX_HG_TZ_VCM_SZ 3
+#define RG_WF_RX_MG_LNA_GC_MSK 0x00000003
+#define RG_WF_RX_MG_LNA_GC_I_MSK 0xfffffffc
+#define RG_WF_RX_MG_LNA_GC_SFT 0
+#define RG_WF_RX_MG_LNA_GC_HI 1
+#define RG_WF_RX_MG_LNA_GC_SZ 2
+#define RG_WF_RX_MG_TZ_GC_MSK 0x0000000c
+#define RG_WF_RX_MG_TZ_GC_I_MSK 0xfffffff3
+#define RG_WF_RX_MG_TZ_GC_SFT 2
+#define RG_WF_RX_MG_TZ_GC_HI 3
+#define RG_WF_RX_MG_TZ_GC_SZ 2
+#define RG_WF_RX_MG_LNAHGN_BIAS_MSK 0x000000f0
+#define RG_WF_RX_MG_LNAHGN_BIAS_I_MSK 0xffffff0f
+#define RG_WF_RX_MG_LNAHGN_BIAS_SFT 4
+#define RG_WF_RX_MG_LNAHGN_BIAS_HI 7
+#define RG_WF_RX_MG_LNAHGN_BIAS_SZ 4
+#define RG_WF_RX_MG_LNAHGP_BIAS_MSK 0x00000f00
+#define RG_WF_RX_MG_LNAHGP_BIAS_I_MSK 0xfffff0ff
+#define RG_WF_RX_MG_LNAHGP_BIAS_SFT 8
+#define RG_WF_RX_MG_LNAHGP_BIAS_HI 11
+#define RG_WF_RX_MG_LNAHGP_BIAS_SZ 4
+#define RG_WF_RX_MG_LNALG_BIAS_MSK 0x0000f000
+#define RG_WF_RX_MG_LNALG_BIAS_I_MSK 0xffff0fff
+#define RG_WF_RX_MG_LNALG_BIAS_SFT 12
+#define RG_WF_RX_MG_LNALG_BIAS_HI 15
+#define RG_WF_RX_MG_LNALG_BIAS_SZ 4
+#define RG_WF_RX_MG_TZ_CAP_MSK 0x00070000
+#define RG_WF_RX_MG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_WF_RX_MG_TZ_CAP_SFT 16
+#define RG_WF_RX_MG_TZ_CAP_HI 18
+#define RG_WF_RX_MG_TZ_CAP_SZ 3
+#define RG_WF_RX_MG_TZ_GC_BOOST_MSK 0x00300000
+#define RG_WF_RX_MG_TZ_GC_BOOST_I_MSK 0xffcfffff
+#define RG_WF_RX_MG_TZ_GC_BOOST_SFT 20
+#define RG_WF_RX_MG_TZ_GC_BOOST_HI 21
+#define RG_WF_RX_MG_TZ_GC_BOOST_SZ 2
+#define RG_WF_RX_MG_DIV2_CORE_MSK 0x00c00000
+#define RG_WF_RX_MG_DIV2_CORE_I_MSK 0xff3fffff
+#define RG_WF_RX_MG_DIV2_CORE_SFT 22
+#define RG_WF_RX_MG_DIV2_CORE_HI 23
+#define RG_WF_RX_MG_DIV2_CORE_SZ 2
+#define RG_WF_RX_MG_LOBUF_MSK 0x03000000
+#define RG_WF_RX_MG_LOBUF_I_MSK 0xfcffffff
+#define RG_WF_RX_MG_LOBUF_SFT 24
+#define RG_WF_RX_MG_LOBUF_HI 25
+#define RG_WF_RX_MG_LOBUF_SZ 2
+#define RG_WF_RX_MG_TZI_MSK 0x1c000000
+#define RG_WF_RX_MG_TZI_I_MSK 0xe3ffffff
+#define RG_WF_RX_MG_TZI_SFT 26
+#define RG_WF_RX_MG_TZI_HI 28
+#define RG_WF_RX_MG_TZI_SZ 3
+#define RG_WF_RX_MG_TZ_VCM_MSK 0xe0000000
+#define RG_WF_RX_MG_TZ_VCM_I_MSK 0x1fffffff
+#define RG_WF_RX_MG_TZ_VCM_SFT 29
+#define RG_WF_RX_MG_TZ_VCM_HI 31
+#define RG_WF_RX_MG_TZ_VCM_SZ 3
+#define RG_WF_RX_LG_LNA_GC_MSK 0x00000003
+#define RG_WF_RX_LG_LNA_GC_I_MSK 0xfffffffc
+#define RG_WF_RX_LG_LNA_GC_SFT 0
+#define RG_WF_RX_LG_LNA_GC_HI 1
+#define RG_WF_RX_LG_LNA_GC_SZ 2
+#define RG_WF_RX_LG_TZ_GC_MSK 0x0000000c
+#define RG_WF_RX_LG_TZ_GC_I_MSK 0xfffffff3
+#define RG_WF_RX_LG_TZ_GC_SFT 2
+#define RG_WF_RX_LG_TZ_GC_HI 3
+#define RG_WF_RX_LG_TZ_GC_SZ 2
+#define RG_WF_RX_LG_LNAHGN_BIAS_MSK 0x000000f0
+#define RG_WF_RX_LG_LNAHGN_BIAS_I_MSK 0xffffff0f
+#define RG_WF_RX_LG_LNAHGN_BIAS_SFT 4
+#define RG_WF_RX_LG_LNAHGN_BIAS_HI 7
+#define RG_WF_RX_LG_LNAHGN_BIAS_SZ 4
+#define RG_WF_RX_LG_LNAHGP_BIAS_MSK 0x00000f00
+#define RG_WF_RX_LG_LNAHGP_BIAS_I_MSK 0xfffff0ff
+#define RG_WF_RX_LG_LNAHGP_BIAS_SFT 8
+#define RG_WF_RX_LG_LNAHGP_BIAS_HI 11
+#define RG_WF_RX_LG_LNAHGP_BIAS_SZ 4
+#define RG_WF_RX_LG_LNALG_BIAS_MSK 0x0000f000
+#define RG_WF_RX_LG_LNALG_BIAS_I_MSK 0xffff0fff
+#define RG_WF_RX_LG_LNALG_BIAS_SFT 12
+#define RG_WF_RX_LG_LNALG_BIAS_HI 15
+#define RG_WF_RX_LG_LNALG_BIAS_SZ 4
+#define RG_WF_RX_LG_TZ_CAP_MSK 0x00070000
+#define RG_WF_RX_LG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_WF_RX_LG_TZ_CAP_SFT 16
+#define RG_WF_RX_LG_TZ_CAP_HI 18
+#define RG_WF_RX_LG_TZ_CAP_SZ 3
+#define RG_WF_RX_LG_TZ_GC_BOOST_MSK 0x00300000
+#define RG_WF_RX_LG_TZ_GC_BOOST_I_MSK 0xffcfffff
+#define RG_WF_RX_LG_TZ_GC_BOOST_SFT 20
+#define RG_WF_RX_LG_TZ_GC_BOOST_HI 21
+#define RG_WF_RX_LG_TZ_GC_BOOST_SZ 2
+#define RG_WF_RX_LG_DIV2_CORE_MSK 0x00c00000
+#define RG_WF_RX_LG_DIV2_CORE_I_MSK 0xff3fffff
+#define RG_WF_RX_LG_DIV2_CORE_SFT 22
+#define RG_WF_RX_LG_DIV2_CORE_HI 23
+#define RG_WF_RX_LG_DIV2_CORE_SZ 2
+#define RG_WF_RX_LG_LOBUF_MSK 0x03000000
+#define RG_WF_RX_LG_LOBUF_I_MSK 0xfcffffff
+#define RG_WF_RX_LG_LOBUF_SFT 24
+#define RG_WF_RX_LG_LOBUF_HI 25
+#define RG_WF_RX_LG_LOBUF_SZ 2
+#define RG_WF_RX_LG_TZI_MSK 0x1c000000
+#define RG_WF_RX_LG_TZI_I_MSK 0xe3ffffff
+#define RG_WF_RX_LG_TZI_SFT 26
+#define RG_WF_RX_LG_TZI_HI 28
+#define RG_WF_RX_LG_TZI_SZ 3
+#define RG_WF_RX_LG_TZ_VCM_MSK 0xe0000000
+#define RG_WF_RX_LG_TZ_VCM_I_MSK 0x1fffffff
+#define RG_WF_RX_LG_TZ_VCM_SFT 29
+#define RG_WF_RX_LG_TZ_VCM_HI 31
+#define RG_WF_RX_LG_TZ_VCM_SZ 3
+#define RG_WF_RX_ULG_LNA_GC_MSK 0x00000003
+#define RG_WF_RX_ULG_LNA_GC_I_MSK 0xfffffffc
+#define RG_WF_RX_ULG_LNA_GC_SFT 0
+#define RG_WF_RX_ULG_LNA_GC_HI 1
+#define RG_WF_RX_ULG_LNA_GC_SZ 2
+#define RG_WF_RX_ULG_TZ_GC_MSK 0x0000000c
+#define RG_WF_RX_ULG_TZ_GC_I_MSK 0xfffffff3
+#define RG_WF_RX_ULG_TZ_GC_SFT 2
+#define RG_WF_RX_ULG_TZ_GC_HI 3
+#define RG_WF_RX_ULG_TZ_GC_SZ 2
+#define RG_WF_RX_ULG_LNAHGN_BIAS_MSK 0x000000f0
+#define RG_WF_RX_ULG_LNAHGN_BIAS_I_MSK 0xffffff0f
+#define RG_WF_RX_ULG_LNAHGN_BIAS_SFT 4
+#define RG_WF_RX_ULG_LNAHGN_BIAS_HI 7
+#define RG_WF_RX_ULG_LNAHGN_BIAS_SZ 4
+#define RG_WF_RX_ULG_LNAHGP_BIAS_MSK 0x00000f00
+#define RG_WF_RX_ULG_LNAHGP_BIAS_I_MSK 0xfffff0ff
+#define RG_WF_RX_ULG_LNAHGP_BIAS_SFT 8
+#define RG_WF_RX_ULG_LNAHGP_BIAS_HI 11
+#define RG_WF_RX_ULG_LNAHGP_BIAS_SZ 4
+#define RG_WF_RX_ULG_LNALG_BIAS_MSK 0x0000f000
+#define RG_WF_RX_ULG_LNALG_BIAS_I_MSK 0xffff0fff
+#define RG_WF_RX_ULG_LNALG_BIAS_SFT 12
+#define RG_WF_RX_ULG_LNALG_BIAS_HI 15
+#define RG_WF_RX_ULG_LNALG_BIAS_SZ 4
+#define RG_WF_RX_ULG_TZ_CAP_MSK 0x00070000
+#define RG_WF_RX_ULG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_WF_RX_ULG_TZ_CAP_SFT 16
+#define RG_WF_RX_ULG_TZ_CAP_HI 18
+#define RG_WF_RX_ULG_TZ_CAP_SZ 3
+#define RG_WF_RX_ULG_TZ_GC_BOOST_MSK 0x00300000
+#define RG_WF_RX_ULG_TZ_GC_BOOST_I_MSK 0xffcfffff
+#define RG_WF_RX_ULG_TZ_GC_BOOST_SFT 20
+#define RG_WF_RX_ULG_TZ_GC_BOOST_HI 21
+#define RG_WF_RX_ULG_TZ_GC_BOOST_SZ 2
+#define RG_WF_RX_ULG_DIV2_CORE_MSK 0x00c00000
+#define RG_WF_RX_ULG_DIV2_CORE_I_MSK 0xff3fffff
+#define RG_WF_RX_ULG_DIV2_CORE_SFT 22
+#define RG_WF_RX_ULG_DIV2_CORE_HI 23
+#define RG_WF_RX_ULG_DIV2_CORE_SZ 2
+#define RG_WF_RX_ULG_LOBUF_MSK 0x03000000
+#define RG_WF_RX_ULG_LOBUF_I_MSK 0xfcffffff
+#define RG_WF_RX_ULG_LOBUF_SFT 24
+#define RG_WF_RX_ULG_LOBUF_HI 25
+#define RG_WF_RX_ULG_LOBUF_SZ 2
+#define RG_WF_RX_ULG_TZI_MSK 0x1c000000
+#define RG_WF_RX_ULG_TZI_I_MSK 0xe3ffffff
+#define RG_WF_RX_ULG_TZI_SFT 26
+#define RG_WF_RX_ULG_TZI_HI 28
+#define RG_WF_RX_ULG_TZI_SZ 3
+#define RG_WF_RX_ULG_TZ_VCM_MSK 0xe0000000
+#define RG_WF_RX_ULG_TZ_VCM_I_MSK 0x1fffffff
+#define RG_WF_RX_ULG_TZ_VCM_SFT 29
+#define RG_WF_RX_ULG_TZ_VCM_HI 31
+#define RG_WF_RX_ULG_TZ_VCM_SZ 3
+#define RG_BT_RX_HG_LNA_GC_MSK 0x00000003
+#define RG_BT_RX_HG_LNA_GC_I_MSK 0xfffffffc
+#define RG_BT_RX_HG_LNA_GC_SFT 0
+#define RG_BT_RX_HG_LNA_GC_HI 1
+#define RG_BT_RX_HG_LNA_GC_SZ 2
+#define RG_BT_RX_HG_TZ_GC_MSK 0x0000000c
+#define RG_BT_RX_HG_TZ_GC_I_MSK 0xfffffff3
+#define RG_BT_RX_HG_TZ_GC_SFT 2
+#define RG_BT_RX_HG_TZ_GC_HI 3
+#define RG_BT_RX_HG_TZ_GC_SZ 2
+#define RG_BT_RX_HG_LNAHGN_BIAS_MSK 0x000000f0
+#define RG_BT_RX_HG_LNAHGN_BIAS_I_MSK 0xffffff0f
+#define RG_BT_RX_HG_LNAHGN_BIAS_SFT 4
+#define RG_BT_RX_HG_LNAHGN_BIAS_HI 7
+#define RG_BT_RX_HG_LNAHGN_BIAS_SZ 4
+#define RG_BT_RX_HG_LNAHGP_BIAS_MSK 0x00000f00
+#define RG_BT_RX_HG_LNAHGP_BIAS_I_MSK 0xfffff0ff
+#define RG_BT_RX_HG_LNAHGP_BIAS_SFT 8
+#define RG_BT_RX_HG_LNAHGP_BIAS_HI 11
+#define RG_BT_RX_HG_LNAHGP_BIAS_SZ 4
+#define RG_BT_RX_HG_LNALG_BIAS_MSK 0x0000f000
+#define RG_BT_RX_HG_LNALG_BIAS_I_MSK 0xffff0fff
+#define RG_BT_RX_HG_LNALG_BIAS_SFT 12
+#define RG_BT_RX_HG_LNALG_BIAS_HI 15
+#define RG_BT_RX_HG_LNALG_BIAS_SZ 4
+#define RG_BT_RX_HG_TZ_CAP_MSK 0x00070000
+#define RG_BT_RX_HG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_BT_RX_HG_TZ_CAP_SFT 16
+#define RG_BT_RX_HG_TZ_CAP_HI 18
+#define RG_BT_RX_HG_TZ_CAP_SZ 3
+#define RG_BT_RX_HG_TZ_GC_BOOST_MSK 0x00300000
+#define RG_BT_RX_HG_TZ_GC_BOOST_I_MSK 0xffcfffff
+#define RG_BT_RX_HG_TZ_GC_BOOST_SFT 20
+#define RG_BT_RX_HG_TZ_GC_BOOST_HI 21
+#define RG_BT_RX_HG_TZ_GC_BOOST_SZ 2
+#define RG_BT_RX_HG_DIV2_CORE_MSK 0x00c00000
+#define RG_BT_RX_HG_DIV2_CORE_I_MSK 0xff3fffff
+#define RG_BT_RX_HG_DIV2_CORE_SFT 22
+#define RG_BT_RX_HG_DIV2_CORE_HI 23
+#define RG_BT_RX_HG_DIV2_CORE_SZ 2
+#define RG_BT_RX_HG_LOBUF_MSK 0x03000000
+#define RG_BT_RX_HG_LOBUF_I_MSK 0xfcffffff
+#define RG_BT_RX_HG_LOBUF_SFT 24
+#define RG_BT_RX_HG_LOBUF_HI 25
+#define RG_BT_RX_HG_LOBUF_SZ 2
+#define RG_BT_RX_HG_TZI_MSK 0x1c000000
+#define RG_BT_RX_HG_TZI_I_MSK 0xe3ffffff
+#define RG_BT_RX_HG_TZI_SFT 26
+#define RG_BT_RX_HG_TZI_HI 28
+#define RG_BT_RX_HG_TZI_SZ 3
+#define RG_BT_RX_HG_TZ_VCM_MSK 0xe0000000
+#define RG_BT_RX_HG_TZ_VCM_I_MSK 0x1fffffff
+#define RG_BT_RX_HG_TZ_VCM_SFT 29
+#define RG_BT_RX_HG_TZ_VCM_HI 31
+#define RG_BT_RX_HG_TZ_VCM_SZ 3
+#define RG_BT_RX_MG_LNA_GC_MSK 0x00000003
+#define RG_BT_RX_MG_LNA_GC_I_MSK 0xfffffffc
+#define RG_BT_RX_MG_LNA_GC_SFT 0
+#define RG_BT_RX_MG_LNA_GC_HI 1
+#define RG_BT_RX_MG_LNA_GC_SZ 2
+#define RG_BT_RX_MG_TZ_GC_MSK 0x0000000c
+#define RG_BT_RX_MG_TZ_GC_I_MSK 0xfffffff3
+#define RG_BT_RX_MG_TZ_GC_SFT 2
+#define RG_BT_RX_MG_TZ_GC_HI 3
+#define RG_BT_RX_MG_TZ_GC_SZ 2
+#define RG_BT_RX_MG_LNAHGN_BIAS_MSK 0x000000f0
+#define RG_BT_RX_MG_LNAHGN_BIAS_I_MSK 0xffffff0f
+#define RG_BT_RX_MG_LNAHGN_BIAS_SFT 4
+#define RG_BT_RX_MG_LNAHGN_BIAS_HI 7
+#define RG_BT_RX_MG_LNAHGN_BIAS_SZ 4
+#define RG_BT_RX_MG_LNAHGP_BIAS_MSK 0x00000f00
+#define RG_BT_RX_MG_LNAHGP_BIAS_I_MSK 0xfffff0ff
+#define RG_BT_RX_MG_LNAHGP_BIAS_SFT 8
+#define RG_BT_RX_MG_LNAHGP_BIAS_HI 11
+#define RG_BT_RX_MG_LNAHGP_BIAS_SZ 4
+#define RG_BT_RX_MG_LNALG_BIAS_MSK 0x0000f000
+#define RG_BT_RX_MG_LNALG_BIAS_I_MSK 0xffff0fff
+#define RG_BT_RX_MG_LNALG_BIAS_SFT 12
+#define RG_BT_RX_MG_LNALG_BIAS_HI 15
+#define RG_BT_RX_MG_LNALG_BIAS_SZ 4
+#define RG_BT_RX_MG_TZ_CAP_MSK 0x00070000
+#define RG_BT_RX_MG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_BT_RX_MG_TZ_CAP_SFT 16
+#define RG_BT_RX_MG_TZ_CAP_HI 18
+#define RG_BT_RX_MG_TZ_CAP_SZ 3
+#define RG_BT_RX_MG_TZ_GC_BOOST_MSK 0x00300000
+#define RG_BT_RX_MG_TZ_GC_BOOST_I_MSK 0xffcfffff
+#define RG_BT_RX_MG_TZ_GC_BOOST_SFT 20
+#define RG_BT_RX_MG_TZ_GC_BOOST_HI 21
+#define RG_BT_RX_MG_TZ_GC_BOOST_SZ 2
+#define RG_BT_RX_MG_DIV2_CORE_MSK 0x00c00000
+#define RG_BT_RX_MG_DIV2_CORE_I_MSK 0xff3fffff
+#define RG_BT_RX_MG_DIV2_CORE_SFT 22
+#define RG_BT_RX_MG_DIV2_CORE_HI 23
+#define RG_BT_RX_MG_DIV2_CORE_SZ 2
+#define RG_BT_RX_MG_LOBUF_MSK 0x03000000
+#define RG_BT_RX_MG_LOBUF_I_MSK 0xfcffffff
+#define RG_BT_RX_MG_LOBUF_SFT 24
+#define RG_BT_RX_MG_LOBUF_HI 25
+#define RG_BT_RX_MG_LOBUF_SZ 2
+#define RG_BT_RX_MG_TZI_MSK 0x1c000000
+#define RG_BT_RX_MG_TZI_I_MSK 0xe3ffffff
+#define RG_BT_RX_MG_TZI_SFT 26
+#define RG_BT_RX_MG_TZI_HI 28
+#define RG_BT_RX_MG_TZI_SZ 3
+#define RG_BT_RX_MG_TZ_VCM_MSK 0xe0000000
+#define RG_BT_RX_MG_TZ_VCM_I_MSK 0x1fffffff
+#define RG_BT_RX_MG_TZ_VCM_SFT 29
+#define RG_BT_RX_MG_TZ_VCM_HI 31
+#define RG_BT_RX_MG_TZ_VCM_SZ 3
+#define RG_BT_RX_LG_LNA_GC_MSK 0x00000003
+#define RG_BT_RX_LG_LNA_GC_I_MSK 0xfffffffc
+#define RG_BT_RX_LG_LNA_GC_SFT 0
+#define RG_BT_RX_LG_LNA_GC_HI 1
+#define RG_BT_RX_LG_LNA_GC_SZ 2
+#define RG_BT_RX_LG_TZ_GC_MSK 0x0000000c
+#define RG_BT_RX_LG_TZ_GC_I_MSK 0xfffffff3
+#define RG_BT_RX_LG_TZ_GC_SFT 2
+#define RG_BT_RX_LG_TZ_GC_HI 3
+#define RG_BT_RX_LG_TZ_GC_SZ 2
+#define RG_BT_RX_LG_LNAHGN_BIAS_MSK 0x000000f0
+#define RG_BT_RX_LG_LNAHGN_BIAS_I_MSK 0xffffff0f
+#define RG_BT_RX_LG_LNAHGN_BIAS_SFT 4
+#define RG_BT_RX_LG_LNAHGN_BIAS_HI 7
+#define RG_BT_RX_LG_LNAHGN_BIAS_SZ 4
+#define RG_BT_RX_LG_LNAHGP_BIAS_MSK 0x00000f00
+#define RG_BT_RX_LG_LNAHGP_BIAS_I_MSK 0xfffff0ff
+#define RG_BT_RX_LG_LNAHGP_BIAS_SFT 8
+#define RG_BT_RX_LG_LNAHGP_BIAS_HI 11
+#define RG_BT_RX_LG_LNAHGP_BIAS_SZ 4
+#define RG_BT_RX_LG_LNALG_BIAS_MSK 0x0000f000
+#define RG_BT_RX_LG_LNALG_BIAS_I_MSK 0xffff0fff
+#define RG_BT_RX_LG_LNALG_BIAS_SFT 12
+#define RG_BT_RX_LG_LNALG_BIAS_HI 15
+#define RG_BT_RX_LG_LNALG_BIAS_SZ 4
+#define RG_BT_RX_LG_TZ_CAP_MSK 0x00070000
+#define RG_BT_RX_LG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_BT_RX_LG_TZ_CAP_SFT 16
+#define RG_BT_RX_LG_TZ_CAP_HI 18
+#define RG_BT_RX_LG_TZ_CAP_SZ 3
+#define RG_BT_RX_LG_TZ_GC_BOOST_MSK 0x00300000
+#define RG_BT_RX_LG_TZ_GC_BOOST_I_MSK 0xffcfffff
+#define RG_BT_RX_LG_TZ_GC_BOOST_SFT 20
+#define RG_BT_RX_LG_TZ_GC_BOOST_HI 21
+#define RG_BT_RX_LG_TZ_GC_BOOST_SZ 2
+#define RG_BT_RX_LG_DIV2_CORE_MSK 0x00c00000
+#define RG_BT_RX_LG_DIV2_CORE_I_MSK 0xff3fffff
+#define RG_BT_RX_LG_DIV2_CORE_SFT 22
+#define RG_BT_RX_LG_DIV2_CORE_HI 23
+#define RG_BT_RX_LG_DIV2_CORE_SZ 2
+#define RG_BT_RX_LG_LOBUF_MSK 0x03000000
+#define RG_BT_RX_LG_LOBUF_I_MSK 0xfcffffff
+#define RG_BT_RX_LG_LOBUF_SFT 24
+#define RG_BT_RX_LG_LOBUF_HI 25
+#define RG_BT_RX_LG_LOBUF_SZ 2
+#define RG_BT_RX_LG_TZI_MSK 0x1c000000
+#define RG_BT_RX_LG_TZI_I_MSK 0xe3ffffff
+#define RG_BT_RX_LG_TZI_SFT 26
+#define RG_BT_RX_LG_TZI_HI 28
+#define RG_BT_RX_LG_TZI_SZ 3
+#define RG_BT_RX_LG_TZ_VCM_MSK 0xe0000000
+#define RG_BT_RX_LG_TZ_VCM_I_MSK 0x1fffffff
+#define RG_BT_RX_LG_TZ_VCM_SFT 29
+#define RG_BT_RX_LG_TZ_VCM_HI 31
+#define RG_BT_RX_LG_TZ_VCM_SZ 3
+#define RG_BT_RX_ULG_LNA_GC_MSK 0x00000003
+#define RG_BT_RX_ULG_LNA_GC_I_MSK 0xfffffffc
+#define RG_BT_RX_ULG_LNA_GC_SFT 0
+#define RG_BT_RX_ULG_LNA_GC_HI 1
+#define RG_BT_RX_ULG_LNA_GC_SZ 2
+#define RG_BT_RX_ULG_TZ_GC_MSK 0x0000000c
+#define RG_BT_RX_ULG_TZ_GC_I_MSK 0xfffffff3
+#define RG_BT_RX_ULG_TZ_GC_SFT 2
+#define RG_BT_RX_ULG_TZ_GC_HI 3
+#define RG_BT_RX_ULG_TZ_GC_SZ 2
+#define RG_BT_RX_ULG_LNAHGN_BIAS_MSK 0x000000f0
+#define RG_BT_RX_ULG_LNAHGN_BIAS_I_MSK 0xffffff0f
+#define RG_BT_RX_ULG_LNAHGN_BIAS_SFT 4
+#define RG_BT_RX_ULG_LNAHGN_BIAS_HI 7
+#define RG_BT_RX_ULG_LNAHGN_BIAS_SZ 4
+#define RG_BT_RX_ULG_LNAHGP_BIAS_MSK 0x00000f00
+#define RG_BT_RX_ULG_LNAHGP_BIAS_I_MSK 0xfffff0ff
+#define RG_BT_RX_ULG_LNAHGP_BIAS_SFT 8
+#define RG_BT_RX_ULG_LNAHGP_BIAS_HI 11
+#define RG_BT_RX_ULG_LNAHGP_BIAS_SZ 4
+#define RG_BT_RX_ULG_LNALG_BIAS_MSK 0x0000f000
+#define RG_BT_RX_ULG_LNALG_BIAS_I_MSK 0xffff0fff
+#define RG_BT_RX_ULG_LNALG_BIAS_SFT 12
+#define RG_BT_RX_ULG_LNALG_BIAS_HI 15
+#define RG_BT_RX_ULG_LNALG_BIAS_SZ 4
+#define RG_BT_RX_ULG_TZ_CAP_MSK 0x00070000
+#define RG_BT_RX_ULG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_BT_RX_ULG_TZ_CAP_SFT 16
+#define RG_BT_RX_ULG_TZ_CAP_HI 18
+#define RG_BT_RX_ULG_TZ_CAP_SZ 3
+#define RG_BT_RX_ULG_TZ_GC_BOOST_MSK 0x00300000
+#define RG_BT_RX_ULG_TZ_GC_BOOST_I_MSK 0xffcfffff
+#define RG_BT_RX_ULG_TZ_GC_BOOST_SFT 20
+#define RG_BT_RX_ULG_TZ_GC_BOOST_HI 21
+#define RG_BT_RX_ULG_TZ_GC_BOOST_SZ 2
+#define RG_BT_RX_ULG_DIV2_CORE_MSK 0x00c00000
+#define RG_BT_RX_ULG_DIV2_CORE_I_MSK 0xff3fffff
+#define RG_BT_RX_ULG_DIV2_CORE_SFT 22
+#define RG_BT_RX_ULG_DIV2_CORE_HI 23
+#define RG_BT_RX_ULG_DIV2_CORE_SZ 2
+#define RG_BT_RX_ULG_LOBUF_MSK 0x03000000
+#define RG_BT_RX_ULG_LOBUF_I_MSK 0xfcffffff
+#define RG_BT_RX_ULG_LOBUF_SFT 24
+#define RG_BT_RX_ULG_LOBUF_HI 25
+#define RG_BT_RX_ULG_LOBUF_SZ 2
+#define RG_BT_RX_ULG_TZI_MSK 0x1c000000
+#define RG_BT_RX_ULG_TZI_I_MSK 0xe3ffffff
+#define RG_BT_RX_ULG_TZI_SFT 26
+#define RG_BT_RX_ULG_TZI_HI 28
+#define RG_BT_RX_ULG_TZI_SZ 3
+#define RG_BT_RX_ULG_TZ_VCM_MSK 0xe0000000
+#define RG_BT_RX_ULG_TZ_VCM_I_MSK 0x1fffffff
+#define RG_BT_RX_ULG_TZ_VCM_SFT 29
+#define RG_BT_RX_ULG_TZ_VCM_HI 31
+#define RG_BT_RX_ULG_TZ_VCM_SZ 3
+#define RG_RX_ADC_CLKSEL_MSK 0x00000001
+#define RG_RX_ADC_CLKSEL_I_MSK 0xfffffffe
+#define RG_RX_ADC_CLKSEL_SFT 0
+#define RG_RX_ADC_CLKSEL_HI 0
+#define RG_RX_ADC_CLKSEL_SZ 1
+#define RG_RX_ADC_DNLEN_MSK 0x00000002
+#define RG_RX_ADC_DNLEN_I_MSK 0xfffffffd
+#define RG_RX_ADC_DNLEN_SFT 1
+#define RG_RX_ADC_DNLEN_HI 1
+#define RG_RX_ADC_DNLEN_SZ 1
+#define RG_RX_ADC_METAEN_MSK 0x00000004
+#define RG_RX_ADC_METAEN_I_MSK 0xfffffffb
+#define RG_RX_ADC_METAEN_SFT 2
+#define RG_RX_ADC_METAEN_HI 2
+#define RG_RX_ADC_METAEN_SZ 1
+#define RG_RX_ADC_TFLAG_MSK 0x00000008
+#define RG_RX_ADC_TFLAG_I_MSK 0xfffffff7
+#define RG_RX_ADC_TFLAG_SFT 3
+#define RG_RX_ADC_TFLAG_HI 3
+#define RG_RX_ADC_TFLAG_SZ 1
+#define RG_RX_ADC_TSEL_MSK 0x000000f0
+#define RG_RX_ADC_TSEL_I_MSK 0xffffff0f
+#define RG_RX_ADC_TSEL_SFT 4
+#define RG_RX_ADC_TSEL_HI 7
+#define RG_RX_ADC_TSEL_SZ 4
+#define RG_WF_RX_ADC_ICMP_MSK 0x00000300
+#define RG_WF_RX_ADC_ICMP_I_MSK 0xfffffcff
+#define RG_WF_RX_ADC_ICMP_SFT 8
+#define RG_WF_RX_ADC_ICMP_HI 9
+#define RG_WF_RX_ADC_ICMP_SZ 2
+#define RG_WF_RX_ADC_VCMI_MSK 0x00000c00
+#define RG_WF_RX_ADC_VCMI_I_MSK 0xfffff3ff
+#define RG_WF_RX_ADC_VCMI_SFT 10
+#define RG_WF_RX_ADC_VCMI_HI 11
+#define RG_WF_RX_ADC_VCMI_SZ 2
+#define RG_WF_RX_ADC_CLOAD_MSK 0x00003000
+#define RG_WF_RX_ADC_CLOAD_I_MSK 0xffffcfff
+#define RG_WF_RX_ADC_CLOAD_SFT 12
+#define RG_WF_RX_ADC_CLOAD_HI 13
+#define RG_WF_RX_ADC_CLOAD_SZ 2
+#define RG_WF_RX_ADC_PSW_MSK 0x00004000
+#define RG_WF_RX_ADC_PSW_I_MSK 0xffffbfff
+#define RG_WF_RX_ADC_PSW_SFT 14
+#define RG_WF_RX_ADC_PSW_HI 14
+#define RG_WF_RX_ADC_PSW_SZ 1
+#define RG_BT_RX_ADC_ICMP_MSK 0x00030000
+#define RG_BT_RX_ADC_ICMP_I_MSK 0xfffcffff
+#define RG_BT_RX_ADC_ICMP_SFT 16
+#define RG_BT_RX_ADC_ICMP_HI 17
+#define RG_BT_RX_ADC_ICMP_SZ 2
+#define RG_BT_RX_ADC_VCMI_MSK 0x000c0000
+#define RG_BT_RX_ADC_VCMI_I_MSK 0xfff3ffff
+#define RG_BT_RX_ADC_VCMI_SFT 18
+#define RG_BT_RX_ADC_VCMI_HI 19
+#define RG_BT_RX_ADC_VCMI_SZ 2
+#define RG_BT_RX_ADC_CLOAD_MSK 0x00300000
+#define RG_BT_RX_ADC_CLOAD_I_MSK 0xffcfffff
+#define RG_BT_RX_ADC_CLOAD_SFT 20
+#define RG_BT_RX_ADC_CLOAD_HI 21
+#define RG_BT_RX_ADC_CLOAD_SZ 2
+#define RG_BT_RX_ADC_PSW_MSK 0x00400000
+#define RG_BT_RX_ADC_PSW_I_MSK 0xffbfffff
+#define RG_BT_RX_ADC_PSW_SFT 22
+#define RG_BT_RX_ADC_PSW_HI 22
+#define RG_BT_RX_ADC_PSW_SZ 1
+#define RG_SARADC_5G_TSSI_MSK 0x00800000
+#define RG_SARADC_5G_TSSI_I_MSK 0xff7fffff
+#define RG_SARADC_5G_TSSI_SFT 23
+#define RG_SARADC_5G_TSSI_HI 23
+#define RG_SARADC_5G_TSSI_SZ 1
+#define RG_SARADC_VRSEL_MSK 0x03000000
+#define RG_SARADC_VRSEL_I_MSK 0xfcffffff
+#define RG_SARADC_VRSEL_SFT 24
+#define RG_SARADC_VRSEL_HI 25
+#define RG_SARADC_VRSEL_SZ 2
+#define RG_EN_SAR_TEST_MSK 0x0c000000
+#define RG_EN_SAR_TEST_I_MSK 0xf3ffffff
+#define RG_EN_SAR_TEST_SFT 26
+#define RG_EN_SAR_TEST_HI 27
+#define RG_EN_SAR_TEST_SZ 2
+#define RG_SARADC_THERMAL_MSK 0x10000000
+#define RG_SARADC_THERMAL_I_MSK 0xefffffff
+#define RG_SARADC_THERMAL_SFT 28
+#define RG_SARADC_THERMAL_HI 28
+#define RG_SARADC_THERMAL_SZ 1
+#define RG_SARADC_TSSI_MSK 0x20000000
+#define RG_SARADC_TSSI_I_MSK 0xdfffffff
+#define RG_SARADC_TSSI_SFT 29
+#define RG_SARADC_TSSI_HI 29
+#define RG_SARADC_TSSI_SZ 1
+#define RG_CLK_SAR_SEL_MSK 0xc0000000
+#define RG_CLK_SAR_SEL_I_MSK 0x3fffffff
+#define RG_CLK_SAR_SEL_SFT 30
+#define RG_CLK_SAR_SEL_HI 31
+#define RG_CLK_SAR_SEL_SZ 2
+#define RG_WF_TX_DACI1ST_MSK 0x00000003
+#define RG_WF_TX_DACI1ST_I_MSK 0xfffffffc
+#define RG_WF_TX_DACI1ST_SFT 0
+#define RG_WF_TX_DACI1ST_HI 1
+#define RG_WF_TX_DACI1ST_SZ 2
+#define RG_WF_TX_DACLPF_ICOARSE_MSK 0x0000000c
+#define RG_WF_TX_DACLPF_ICOARSE_I_MSK 0xfffffff3
+#define RG_WF_TX_DACLPF_ICOARSE_SFT 2
+#define RG_WF_TX_DACLPF_ICOARSE_HI 3
+#define RG_WF_TX_DACLPF_ICOARSE_SZ 2
+#define RG_WF_TX_DACLPF_IFINE_MSK 0x00000030
+#define RG_WF_TX_DACLPF_IFINE_I_MSK 0xffffffcf
+#define RG_WF_TX_DACLPF_IFINE_SFT 4
+#define RG_WF_TX_DACLPF_IFINE_HI 5
+#define RG_WF_TX_DACLPF_IFINE_SZ 2
+#define RG_WF_TX_DACLPF_VCM_MSK 0x000000c0
+#define RG_WF_TX_DACLPF_VCM_I_MSK 0xffffff3f
+#define RG_WF_TX_DACLPF_VCM_SFT 6
+#define RG_WF_TX_DACLPF_VCM_HI 7
+#define RG_WF_TX_DACLPF_VCM_SZ 2
+#define RG_WF_TX_DAC_IBIAS_MSK 0x00000300
+#define RG_WF_TX_DAC_IBIAS_I_MSK 0xfffffcff
+#define RG_WF_TX_DAC_IBIAS_SFT 8
+#define RG_WF_TX_DAC_IBIAS_HI 9
+#define RG_WF_TX_DAC_IBIAS_SZ 2
+#define RG_WF_TX_DAC_IATTN_MSK 0x00000400
+#define RG_WF_TX_DAC_IATTN_I_MSK 0xfffffbff
+#define RG_WF_TX_DAC_IATTN_SFT 10
+#define RG_WF_TX_DAC_IATTN_HI 10
+#define RG_WF_TX_DAC_IATTN_SZ 1
+#define RG_WF_TXLPF_BOOSTI_MSK 0x00000800
+#define RG_WF_TXLPF_BOOSTI_I_MSK 0xfffff7ff
+#define RG_WF_TXLPF_BOOSTI_SFT 11
+#define RG_WF_TXLPF_BOOSTI_HI 11
+#define RG_WF_TXLPF_BOOSTI_SZ 1
+#define RG_WF_TX_DAC_RCAL_MSK 0x00003000
+#define RG_WF_TX_DAC_RCAL_I_MSK 0xffffcfff
+#define RG_WF_TX_DAC_RCAL_SFT 12
+#define RG_WF_TX_DAC_RCAL_HI 13
+#define RG_WF_TX_DAC_RCAL_SZ 2
+#define RG_WF_TX_DAC_CKEDGE_SEL_MSK 0x00004000
+#define RG_WF_TX_DAC_CKEDGE_SEL_I_MSK 0xffffbfff
+#define RG_WF_TX_DAC_CKEDGE_SEL_SFT 14
+#define RG_WF_TX_DAC_CKEDGE_SEL_HI 14
+#define RG_WF_TX_DAC_CKEDGE_SEL_SZ 1
+#define RG_WF_TX_DAC_OS_MSK 0x00070000
+#define RG_WF_TX_DAC_OS_I_MSK 0xfff8ffff
+#define RG_WF_TX_DAC_OS_SFT 16
+#define RG_WF_TX_DAC_OS_HI 18
+#define RG_WF_TX_DAC_OS_SZ 3
+#define RG_WF_TX_DAC_IOFFSET_MSK 0x00f00000
+#define RG_WF_TX_DAC_IOFFSET_I_MSK 0xff0fffff
+#define RG_WF_TX_DAC_IOFFSET_SFT 20
+#define RG_WF_TX_DAC_IOFFSET_HI 23
+#define RG_WF_TX_DAC_IOFFSET_SZ 4
+#define RG_WF_TX_DAC_QOFFSET_MSK 0x0f000000
+#define RG_WF_TX_DAC_QOFFSET_I_MSK 0xf0ffffff
+#define RG_WF_TX_DAC_QOFFSET_SFT 24
+#define RG_WF_TX_DAC_QOFFSET_HI 27
+#define RG_WF_TX_DAC_QOFFSET_SZ 4
+#define RG_TX_DAC_TSEL_MSK 0xf0000000
+#define RG_TX_DAC_TSEL_I_MSK 0x0fffffff
+#define RG_TX_DAC_TSEL_SFT 28
+#define RG_TX_DAC_TSEL_HI 31
+#define RG_TX_DAC_TSEL_SZ 4
+#define RG_BT_TX_DACI1ST_MSK 0x00000003
+#define RG_BT_TX_DACI1ST_I_MSK 0xfffffffc
+#define RG_BT_TX_DACI1ST_SFT 0
+#define RG_BT_TX_DACI1ST_HI 1
+#define RG_BT_TX_DACI1ST_SZ 2
+#define RG_BT_TX_DACLPF_ICOARSE_MSK 0x0000000c
+#define RG_BT_TX_DACLPF_ICOARSE_I_MSK 0xfffffff3
+#define RG_BT_TX_DACLPF_ICOARSE_SFT 2
+#define RG_BT_TX_DACLPF_ICOARSE_HI 3
+#define RG_BT_TX_DACLPF_ICOARSE_SZ 2
+#define RG_BT_TX_DACLPF_IFINE_MSK 0x00000030
+#define RG_BT_TX_DACLPF_IFINE_I_MSK 0xffffffcf
+#define RG_BT_TX_DACLPF_IFINE_SFT 4
+#define RG_BT_TX_DACLPF_IFINE_HI 5
+#define RG_BT_TX_DACLPF_IFINE_SZ 2
+#define RG_BT_TX_DACLPF_VCM_MSK 0x000000c0
+#define RG_BT_TX_DACLPF_VCM_I_MSK 0xffffff3f
+#define RG_BT_TX_DACLPF_VCM_SFT 6
+#define RG_BT_TX_DACLPF_VCM_HI 7
+#define RG_BT_TX_DACLPF_VCM_SZ 2
+#define RG_BT_TX_DAC_IBIAS_MSK 0x00000300
+#define RG_BT_TX_DAC_IBIAS_I_MSK 0xfffffcff
+#define RG_BT_TX_DAC_IBIAS_SFT 8
+#define RG_BT_TX_DAC_IBIAS_HI 9
+#define RG_BT_TX_DAC_IBIAS_SZ 2
+#define RG_BT_TX_DAC_IATTN_MSK 0x00000400
+#define RG_BT_TX_DAC_IATTN_I_MSK 0xfffffbff
+#define RG_BT_TX_DAC_IATTN_SFT 10
+#define RG_BT_TX_DAC_IATTN_HI 10
+#define RG_BT_TX_DAC_IATTN_SZ 1
+#define RG_BT_TXLPF_BOOSTI_MSK 0x00000800
+#define RG_BT_TXLPF_BOOSTI_I_MSK 0xfffff7ff
+#define RG_BT_TXLPF_BOOSTI_SFT 11
+#define RG_BT_TXLPF_BOOSTI_HI 11
+#define RG_BT_TXLPF_BOOSTI_SZ 1
+#define RG_BT_TX_DAC_RCAL_MSK 0x00003000
+#define RG_BT_TX_DAC_RCAL_I_MSK 0xffffcfff
+#define RG_BT_TX_DAC_RCAL_SFT 12
+#define RG_BT_TX_DAC_RCAL_HI 13
+#define RG_BT_TX_DAC_RCAL_SZ 2
+#define RG_BT_TX_DAC_CKEDGE_SEL_MSK 0x00004000
+#define RG_BT_TX_DAC_CKEDGE_SEL_I_MSK 0xffffbfff
+#define RG_BT_TX_DAC_CKEDGE_SEL_SFT 14
+#define RG_BT_TX_DAC_CKEDGE_SEL_HI 14
+#define RG_BT_TX_DAC_CKEDGE_SEL_SZ 1
+#define RG_BT_TX_DAC_OS_MSK 0x00070000
+#define RG_BT_TX_DAC_OS_I_MSK 0xfff8ffff
+#define RG_BT_TX_DAC_OS_SFT 16
+#define RG_BT_TX_DAC_OS_HI 18
+#define RG_BT_TX_DAC_OS_SZ 3
+#define RG_BT_TX_DAC_IOFFSET_MSK 0x00f00000
+#define RG_BT_TX_DAC_IOFFSET_I_MSK 0xff0fffff
+#define RG_BT_TX_DAC_IOFFSET_SFT 20
+#define RG_BT_TX_DAC_IOFFSET_HI 23
+#define RG_BT_TX_DAC_IOFFSET_SZ 4
+#define RG_BT_TX_DAC_QOFFSET_MSK 0x0f000000
+#define RG_BT_TX_DAC_QOFFSET_I_MSK 0xf0ffffff
+#define RG_BT_TX_DAC_QOFFSET_SFT 24
+#define RG_BT_TX_DAC_QOFFSET_HI 27
+#define RG_BT_TX_DAC_QOFFSET_SZ 4
+#define RG_SX_EN_MAN_MSK 0x00000001
+#define RG_SX_EN_MAN_I_MSK 0xfffffffe
+#define RG_SX_EN_MAN_SFT 0
+#define RG_SX_EN_MAN_HI 0
+#define RG_SX_EN_MAN_SZ 1
+#define RG_SX_EN_MSK 0x00000002
+#define RG_SX_EN_I_MSK 0xfffffffd
+#define RG_SX_EN_SFT 1
+#define RG_SX_EN_HI 1
+#define RG_SX_EN_SZ 1
+#define RG_EN_SX_CP_MAN_MSK 0x00000004
+#define RG_EN_SX_CP_MAN_I_MSK 0xfffffffb
+#define RG_EN_SX_CP_MAN_SFT 2
+#define RG_EN_SX_CP_MAN_HI 2
+#define RG_EN_SX_CP_MAN_SZ 1
+#define RG_EN_SX_CP_MSK 0x00000008
+#define RG_EN_SX_CP_I_MSK 0xfffffff7
+#define RG_EN_SX_CP_SFT 3
+#define RG_EN_SX_CP_HI 3
+#define RG_EN_SX_CP_SZ 1
+#define RG_EN_SX_DIV_MAN_MSK 0x00000010
+#define RG_EN_SX_DIV_MAN_I_MSK 0xffffffef
+#define RG_EN_SX_DIV_MAN_SFT 4
+#define RG_EN_SX_DIV_MAN_HI 4
+#define RG_EN_SX_DIV_MAN_SZ 1
+#define RG_EN_SX_DIV_MSK 0x00000020
+#define RG_EN_SX_DIV_I_MSK 0xffffffdf
+#define RG_EN_SX_DIV_SFT 5
+#define RG_EN_SX_DIV_HI 5
+#define RG_EN_SX_DIV_SZ 1
+#define RG_EN_SX_VCO_MAN_MSK 0x00000040
+#define RG_EN_SX_VCO_MAN_I_MSK 0xffffffbf
+#define RG_EN_SX_VCO_MAN_SFT 6
+#define RG_EN_SX_VCO_MAN_HI 6
+#define RG_EN_SX_VCO_MAN_SZ 1
+#define RG_EN_SX_VCO_MSK 0x00000080
+#define RG_EN_SX_VCO_I_MSK 0xffffff7f
+#define RG_EN_SX_VCO_SFT 7
+#define RG_EN_SX_VCO_HI 7
+#define RG_EN_SX_VCO_SZ 1
+#define RG_SX_PFD_RST_MAN_MSK 0x00000100
+#define RG_SX_PFD_RST_MAN_I_MSK 0xfffffeff
+#define RG_SX_PFD_RST_MAN_SFT 8
+#define RG_SX_PFD_RST_MAN_HI 8
+#define RG_SX_PFD_RST_MAN_SZ 1
+#define RG_SX_PFD_RST_MSK 0x00000200
+#define RG_SX_PFD_RST_I_MSK 0xfffffdff
+#define RG_SX_PFD_RST_SFT 9
+#define RG_SX_PFD_RST_HI 9
+#define RG_SX_PFD_RST_SZ 1
+#define RG_SX_UOP_MAN_MSK 0x00000400
+#define RG_SX_UOP_MAN_I_MSK 0xfffffbff
+#define RG_SX_UOP_MAN_SFT 10
+#define RG_SX_UOP_MAN_HI 10
+#define RG_SX_UOP_MAN_SZ 1
+#define RG_SX_UOP_EN_MSK 0x00000800
+#define RG_SX_UOP_EN_I_MSK 0xfffff7ff
+#define RG_SX_UOP_EN_SFT 11
+#define RG_SX_UOP_EN_HI 11
+#define RG_SX_UOP_EN_SZ 1
+#define RG_EN_VCOBF_TXMB_MAN_MSK 0x00001000
+#define RG_EN_VCOBF_TXMB_MAN_I_MSK 0xffffefff
+#define RG_EN_VCOBF_TXMB_MAN_SFT 12
+#define RG_EN_VCOBF_TXMB_MAN_HI 12
+#define RG_EN_VCOBF_TXMB_MAN_SZ 1
+#define RG_EN_VCOBF_TXMB_MSK 0x00002000
+#define RG_EN_VCOBF_TXMB_I_MSK 0xffffdfff
+#define RG_EN_VCOBF_TXMB_SFT 13
+#define RG_EN_VCOBF_TXMB_HI 13
+#define RG_EN_VCOBF_TXMB_SZ 1
+#define RG_EN_VCOBF_TXOB_MAN_MSK 0x00004000
+#define RG_EN_VCOBF_TXOB_MAN_I_MSK 0xffffbfff
+#define RG_EN_VCOBF_TXOB_MAN_SFT 14
+#define RG_EN_VCOBF_TXOB_MAN_HI 14
+#define RG_EN_VCOBF_TXOB_MAN_SZ 1
+#define RG_EN_VCOBF_TXOB_MSK 0x00008000
+#define RG_EN_VCOBF_TXOB_I_MSK 0xffff7fff
+#define RG_EN_VCOBF_TXOB_SFT 15
+#define RG_EN_VCOBF_TXOB_HI 15
+#define RG_EN_VCOBF_TXOB_SZ 1
+#define RG_EN_VCOBF_RXMB_MAN_MSK 0x00010000
+#define RG_EN_VCOBF_RXMB_MAN_I_MSK 0xfffeffff
+#define RG_EN_VCOBF_RXMB_MAN_SFT 16
+#define RG_EN_VCOBF_RXMB_MAN_HI 16
+#define RG_EN_VCOBF_RXMB_MAN_SZ 1
+#define RG_EN_VCOBF_RXMB_MSK 0x00020000
+#define RG_EN_VCOBF_RXMB_I_MSK 0xfffdffff
+#define RG_EN_VCOBF_RXMB_SFT 17
+#define RG_EN_VCOBF_RXMB_HI 17
+#define RG_EN_VCOBF_RXMB_SZ 1
+#define RG_EN_VCOBF_RXOB_MAN_MSK 0x00040000
+#define RG_EN_VCOBF_RXOB_MAN_I_MSK 0xfffbffff
+#define RG_EN_VCOBF_RXOB_MAN_SFT 18
+#define RG_EN_VCOBF_RXOB_MAN_HI 18
+#define RG_EN_VCOBF_RXOB_MAN_SZ 1
+#define RG_EN_VCOBF_RXOB_MSK 0x00080000
+#define RG_EN_VCOBF_RXOB_I_MSK 0xfff7ffff
+#define RG_EN_VCOBF_RXOB_SFT 19
+#define RG_EN_VCOBF_RXOB_HI 19
+#define RG_EN_VCOBF_RXOB_SZ 1
+#define RG_EN_VCOBF_DIVCK_MAN_MSK 0x00100000
+#define RG_EN_VCOBF_DIVCK_MAN_I_MSK 0xffefffff
+#define RG_EN_VCOBF_DIVCK_MAN_SFT 20
+#define RG_EN_VCOBF_DIVCK_MAN_HI 20
+#define RG_EN_VCOBF_DIVCK_MAN_SZ 1
+#define RG_EN_VCOBF_DIVCK_MSK 0x00200000
+#define RG_EN_VCOBF_DIVCK_I_MSK 0xffdfffff
+#define RG_EN_VCOBF_DIVCK_SFT 21
+#define RG_EN_VCOBF_DIVCK_HI 21
+#define RG_EN_VCOBF_DIVCK_SZ 1
+#define RG_SX_SBCAL_DIS_MSK 0x00800000
+#define RG_SX_SBCAL_DIS_I_MSK 0xff7fffff
+#define RG_SX_SBCAL_DIS_SFT 23
+#define RG_SX_SBCAL_DIS_HI 23
+#define RG_SX_SBCAL_DIS_SZ 1
+#define RG_SX_SBCAL_AW_MSK 0x01000000
+#define RG_SX_SBCAL_AW_I_MSK 0xfeffffff
+#define RG_SX_SBCAL_AW_SFT 24
+#define RG_SX_SBCAL_AW_HI 24
+#define RG_SX_SBCAL_AW_SZ 1
+#define RG_SX_AAC_DIS_MSK 0x04000000
+#define RG_SX_AAC_DIS_I_MSK 0xfbffffff
+#define RG_SX_AAC_DIS_SFT 26
+#define RG_SX_AAC_DIS_HI 26
+#define RG_SX_AAC_DIS_SZ 1
+#define RG_SX_TTL_DIS_MSK 0x08000000
+#define RG_SX_TTL_DIS_I_MSK 0xf7ffffff
+#define RG_SX_TTL_DIS_SFT 27
+#define RG_SX_TTL_DIS_HI 27
+#define RG_SX_TTL_DIS_SZ 1
+#define RG_SX_CAL_INIT_MSK 0xe0000000
+#define RG_SX_CAL_INIT_I_MSK 0x1fffffff
+#define RG_SX_CAL_INIT_SFT 29
+#define RG_SX_CAL_INIT_HI 31
+#define RG_SX_CAL_INIT_SZ 3
+#define RG_EN_SX_LDO_MAN_MSK 0x00000001
+#define RG_EN_SX_LDO_MAN_I_MSK 0xfffffffe
+#define RG_EN_SX_LDO_MAN_SFT 0
+#define RG_EN_SX_LDO_MAN_HI 0
+#define RG_EN_SX_LDO_MAN_SZ 1
+#define RG_EN_LDO_CP_MSK 0x00000002
+#define RG_EN_LDO_CP_I_MSK 0xfffffffd
+#define RG_EN_LDO_CP_SFT 1
+#define RG_EN_LDO_CP_HI 1
+#define RG_EN_LDO_CP_SZ 1
+#define RG_EN_LDO_DIV_MSK 0x00000004
+#define RG_EN_LDO_DIV_I_MSK 0xfffffffb
+#define RG_EN_LDO_DIV_SFT 2
+#define RG_EN_LDO_DIV_HI 2
+#define RG_EN_LDO_DIV_SZ 1
+#define RG_EN_LDO_LO_MSK 0x00000008
+#define RG_EN_LDO_LO_I_MSK 0xfffffff7
+#define RG_EN_LDO_LO_SFT 3
+#define RG_EN_LDO_LO_HI 3
+#define RG_EN_LDO_LO_SZ 1
+#define RG_EN_LDO_VCO_MSK 0x00000010
+#define RG_EN_LDO_VCO_I_MSK 0xffffffef
+#define RG_EN_LDO_VCO_SFT 4
+#define RG_EN_LDO_VCO_HI 4
+#define RG_EN_LDO_VCO_SZ 1
+#define RG_EN_LDO_VCO_PSW_MSK 0x00000200
+#define RG_EN_LDO_VCO_PSW_I_MSK 0xfffffdff
+#define RG_EN_LDO_VCO_PSW_SFT 9
+#define RG_EN_LDO_VCO_PSW_HI 9
+#define RG_EN_LDO_VCO_PSW_SZ 1
+#define RG_EN_LDO_VCO_VDD33_MSK 0x00000400
+#define RG_EN_LDO_VCO_VDD33_I_MSK 0xfffffbff
+#define RG_EN_LDO_VCO_VDD33_SFT 10
+#define RG_EN_LDO_VCO_VDD33_HI 10
+#define RG_EN_LDO_VCO_VDD33_SZ 1
+#define RG_EN_LDO_CP_IQUP_MSK 0x00000800
+#define RG_EN_LDO_CP_IQUP_I_MSK 0xfffff7ff
+#define RG_EN_LDO_CP_IQUP_SFT 11
+#define RG_EN_LDO_CP_IQUP_HI 11
+#define RG_EN_LDO_CP_IQUP_SZ 1
+#define RG_EN_LDO_DIV_IQUP_MSK 0x00001000
+#define RG_EN_LDO_DIV_IQUP_I_MSK 0xffffefff
+#define RG_EN_LDO_DIV_IQUP_SFT 12
+#define RG_EN_LDO_DIV_IQUP_HI 12
+#define RG_EN_LDO_DIV_IQUP_SZ 1
+#define RG_EN_LDO_LO_IQUP_MSK 0x00002000
+#define RG_EN_LDO_LO_IQUP_I_MSK 0xffffdfff
+#define RG_EN_LDO_LO_IQUP_SFT 13
+#define RG_EN_LDO_LO_IQUP_HI 13
+#define RG_EN_LDO_LO_IQUP_SZ 1
+#define RG_EN_LDO_VCO_IQUP_MSK 0x00004000
+#define RG_EN_LDO_VCO_IQUP_I_MSK 0xffffbfff
+#define RG_EN_LDO_VCO_IQUP_SFT 14
+#define RG_EN_LDO_VCO_IQUP_HI 14
+#define RG_EN_LDO_VCO_IQUP_SZ 1
+#define RG_SX_LDO_FCOFFT_MSK 0x00380000
+#define RG_SX_LDO_FCOFFT_I_MSK 0xffc7ffff
+#define RG_SX_LDO_FCOFFT_SFT 19
+#define RG_SX_LDO_FCOFFT_HI 21
+#define RG_SX_LDO_FCOFFT_SZ 3
+#define RG_LDO_CP_FC_MAN_MSK 0x00400000
+#define RG_LDO_CP_FC_MAN_I_MSK 0xffbfffff
+#define RG_LDO_CP_FC_MAN_SFT 22
+#define RG_LDO_CP_FC_MAN_HI 22
+#define RG_LDO_CP_FC_MAN_SZ 1
+#define RG_LDO_CP_FC_MSK 0x00800000
+#define RG_LDO_CP_FC_I_MSK 0xff7fffff
+#define RG_LDO_CP_FC_SFT 23
+#define RG_LDO_CP_FC_HI 23
+#define RG_LDO_CP_FC_SZ 1
+#define RG_LDO_DIV_FC_MAN_MSK 0x01000000
+#define RG_LDO_DIV_FC_MAN_I_MSK 0xfeffffff
+#define RG_LDO_DIV_FC_MAN_SFT 24
+#define RG_LDO_DIV_FC_MAN_HI 24
+#define RG_LDO_DIV_FC_MAN_SZ 1
+#define RG_LDO_DIV_FC_MSK 0x02000000
+#define RG_LDO_DIV_FC_I_MSK 0xfdffffff
+#define RG_LDO_DIV_FC_SFT 25
+#define RG_LDO_DIV_FC_HI 25
+#define RG_LDO_DIV_FC_SZ 1
+#define RG_LDO_LO_FC_MAN_MSK 0x04000000
+#define RG_LDO_LO_FC_MAN_I_MSK 0xfbffffff
+#define RG_LDO_LO_FC_MAN_SFT 26
+#define RG_LDO_LO_FC_MAN_HI 26
+#define RG_LDO_LO_FC_MAN_SZ 1
+#define RG_LDO_LO_FC_MSK 0x08000000
+#define RG_LDO_LO_FC_I_MSK 0xf7ffffff
+#define RG_LDO_LO_FC_SFT 27
+#define RG_LDO_LO_FC_HI 27
+#define RG_LDO_LO_FC_SZ 1
+#define RG_LDO_VCO_FC_MAN_MSK 0x10000000
+#define RG_LDO_VCO_FC_MAN_I_MSK 0xefffffff
+#define RG_LDO_VCO_FC_MAN_SFT 28
+#define RG_LDO_VCO_FC_MAN_HI 28
+#define RG_LDO_VCO_FC_MAN_SZ 1
+#define RG_LDO_VCO_FC_MSK 0x20000000
+#define RG_LDO_VCO_FC_I_MSK 0xdfffffff
+#define RG_LDO_VCO_FC_SFT 29
+#define RG_LDO_VCO_FC_HI 29
+#define RG_LDO_VCO_FC_SZ 1
+#define RG_LDO_VCO_RCF_MSK 0xc0000000
+#define RG_LDO_VCO_RCF_I_MSK 0x3fffffff
+#define RG_LDO_VCO_RCF_SFT 30
+#define RG_LDO_VCO_RCF_HI 31
+#define RG_LDO_VCO_RCF_SZ 2
+#define RG_SX_RFCTRL_F_MSK 0x00ffffff
+#define RG_SX_RFCTRL_F_I_MSK 0xff000000
+#define RG_SX_RFCTRL_F_SFT 0
+#define RG_SX_RFCTRL_F_HI 23
+#define RG_SX_RFCTRL_F_SZ 24
+#define RG_SX_RFCTRL_CH_7_0_MSK 0xff000000
+#define RG_SX_RFCTRL_CH_7_0_I_MSK 0x00ffffff
+#define RG_SX_RFCTRL_CH_7_0_SFT 24
+#define RG_SX_RFCTRL_CH_7_0_HI 31
+#define RG_SX_RFCTRL_CH_7_0_SZ 8
+#define RG_SX_RFCTRL_CH_10_8_MSK 0x00000007
+#define RG_SX_RFCTRL_CH_10_8_I_MSK 0xfffffff8
+#define RG_SX_RFCTRL_CH_10_8_SFT 0
+#define RG_SX_RFCTRL_CH_10_8_HI 2
+#define RG_SX_RFCTRL_CH_10_8_SZ 3
+#define RG_SX_RFCH_MAP_EN_MSK 0x00000008
+#define RG_SX_RFCH_MAP_EN_I_MSK 0xfffffff7
+#define RG_SX_RFCH_MAP_EN_SFT 3
+#define RG_SX_RFCH_MAP_EN_HI 3
+#define RG_SX_RFCH_MAP_EN_SZ 1
+#define RG_SX_FREF_DOUB_MAN_MSK 0x00000040
+#define RG_SX_FREF_DOUB_MAN_I_MSK 0xffffffbf
+#define RG_SX_FREF_DOUB_MAN_SFT 6
+#define RG_SX_FREF_DOUB_MAN_HI 6
+#define RG_SX_FREF_DOUB_MAN_SZ 1
+#define RG_SX_FREF_DOUB_MSK 0x00000080
+#define RG_SX_FREF_DOUB_I_MSK 0xffffff7f
+#define RG_SX_FREF_DOUB_SFT 7
+#define RG_SX_FREF_DOUB_HI 7
+#define RG_SX_FREF_DOUB_SZ 1
+#define RG_SX_BTRX_SIDE_MSK 0x00000100
+#define RG_SX_BTRX_SIDE_I_MSK 0xfffffeff
+#define RG_SX_BTRX_SIDE_SFT 8
+#define RG_SX_BTRX_SIDE_HI 8
+#define RG_SX_BTRX_SIDE_SZ 1
+#define RG_SX_LO_TIMES_MSK 0x00000200
+#define RG_SX_LO_TIMES_I_MSK 0xfffffdff
+#define RG_SX_LO_TIMES_SFT 9
+#define RG_SX_LO_TIMES_HI 9
+#define RG_SX_LO_TIMES_SZ 1
+#define RG_SX_CHANNEL_MSK 0x0007f800
+#define RG_SX_CHANNEL_I_MSK 0xfff807ff
+#define RG_SX_CHANNEL_SFT 11
+#define RG_SX_CHANNEL_HI 18
+#define RG_SX_CHANNEL_SZ 8
+#define RG_SX_XTAL_FREQ_MSK 0x00f00000
+#define RG_SX_XTAL_FREQ_I_MSK 0xff0fffff
+#define RG_SX_XTAL_FREQ_SFT 20
+#define RG_SX_XTAL_FREQ_HI 23
+#define RG_SX_XTAL_FREQ_SZ 4
+#define RG_SX_CP_ISEL_BT_MSK 0x0000000f
+#define RG_SX_CP_ISEL_BT_I_MSK 0xfffffff0
+#define RG_SX_CP_ISEL_BT_SFT 0
+#define RG_SX_CP_ISEL_BT_HI 3
+#define RG_SX_CP_ISEL_BT_SZ 4
+#define RG_SX_CP_ISEL50U_BT_MSK 0x00000010
+#define RG_SX_CP_ISEL50U_BT_I_MSK 0xffffffef
+#define RG_SX_CP_ISEL50U_BT_SFT 4
+#define RG_SX_CP_ISEL50U_BT_HI 4
+#define RG_SX_CP_ISEL50U_BT_SZ 1
+#define RG_SX_CP_KP_DOUB_BT_MSK 0x00000020
+#define RG_SX_CP_KP_DOUB_BT_I_MSK 0xffffffdf
+#define RG_SX_CP_KP_DOUB_BT_SFT 5
+#define RG_SX_CP_KP_DOUB_BT_HI 5
+#define RG_SX_CP_KP_DOUB_BT_SZ 1
+#define RG_SX_CP_ISEL_WF_MSK 0x00000780
+#define RG_SX_CP_ISEL_WF_I_MSK 0xfffff87f
+#define RG_SX_CP_ISEL_WF_SFT 7
+#define RG_SX_CP_ISEL_WF_HI 10
+#define RG_SX_CP_ISEL_WF_SZ 4
+#define RG_SX_CP_ISEL50U_WF_MSK 0x00000800
+#define RG_SX_CP_ISEL50U_WF_I_MSK 0xfffff7ff
+#define RG_SX_CP_ISEL50U_WF_SFT 11
+#define RG_SX_CP_ISEL50U_WF_HI 11
+#define RG_SX_CP_ISEL50U_WF_SZ 1
+#define RG_SX_CP_KP_DOUB_WF_MSK 0x00001000
+#define RG_SX_CP_KP_DOUB_WF_I_MSK 0xffffefff
+#define RG_SX_CP_KP_DOUB_WF_SFT 12
+#define RG_SX_CP_KP_DOUB_WF_HI 12
+#define RG_SX_CP_KP_DOUB_WF_SZ 1
+#define RG_SX_CP_IOST_POL_MSK 0x00008000
+#define RG_SX_CP_IOST_POL_I_MSK 0xffff7fff
+#define RG_SX_CP_IOST_POL_SFT 15
+#define RG_SX_CP_IOST_POL_HI 15
+#define RG_SX_CP_IOST_POL_SZ 1
+#define RG_SX_CP_IOST_MSK 0x00070000
+#define RG_SX_CP_IOST_I_MSK 0xfff8ffff
+#define RG_SX_CP_IOST_SFT 16
+#define RG_SX_CP_IOST_HI 18
+#define RG_SX_CP_IOST_SZ 3
+#define RG_SX_PFD_SEL_MSK 0x00400000
+#define RG_SX_PFD_SEL_I_MSK 0xffbfffff
+#define RG_SX_PFD_SEL_SFT 22
+#define RG_SX_PFD_SEL_HI 22
+#define RG_SX_PFD_SEL_SZ 1
+#define RG_SX_PFD_SET_MSK 0x00800000
+#define RG_SX_PFD_SET_I_MSK 0xff7fffff
+#define RG_SX_PFD_SET_SFT 23
+#define RG_SX_PFD_SET_HI 23
+#define RG_SX_PFD_SET_SZ 1
+#define RG_SX_PFD_SET1_MSK 0x01000000
+#define RG_SX_PFD_SET1_I_MSK 0xfeffffff
+#define RG_SX_PFD_SET1_SFT 24
+#define RG_SX_PFD_SET1_HI 24
+#define RG_SX_PFD_SET1_SZ 1
+#define RG_SX_PFD_SET2_MSK 0x02000000
+#define RG_SX_PFD_SET2_I_MSK 0xfdffffff
+#define RG_SX_PFD_SET2_SFT 25
+#define RG_SX_PFD_SET2_HI 25
+#define RG_SX_PFD_SET2_SZ 1
+#define RG_SX_PFD_REF_EDGE_MSK 0x04000000
+#define RG_SX_PFD_REF_EDGE_I_MSK 0xfbffffff
+#define RG_SX_PFD_REF_EDGE_SFT 26
+#define RG_SX_PFD_REF_EDGE_HI 26
+#define RG_SX_PFD_REF_EDGE_SZ 1
+#define RG_SX_PFD_DIV_EDGE_MSK 0x08000000
+#define RG_SX_PFD_DIV_EDGE_I_MSK 0xf7ffffff
+#define RG_SX_PFD_DIV_EDGE_SFT 27
+#define RG_SX_PFD_DIV_EDGE_HI 27
+#define RG_SX_PFD_DIV_EDGE_SZ 1
+#define RG_SX_PFD_TRUP_MSK 0x10000000
+#define RG_SX_PFD_TRUP_I_MSK 0xefffffff
+#define RG_SX_PFD_TRUP_SFT 28
+#define RG_SX_PFD_TRUP_HI 28
+#define RG_SX_PFD_TRUP_SZ 1
+#define RG_SX_PFD_TRDN_MSK 0x20000000
+#define RG_SX_PFD_TRDN_I_MSK 0xdfffffff
+#define RG_SX_PFD_TRDN_SFT 29
+#define RG_SX_PFD_TRDN_HI 29
+#define RG_SX_PFD_TRDN_SZ 1
+#define RG_SX_PFD_TLSEL_MSK 0x40000000
+#define RG_SX_PFD_TLSEL_I_MSK 0xbfffffff
+#define RG_SX_PFD_TLSEL_SFT 30
+#define RG_SX_PFD_TLSEL_HI 30
+#define RG_SX_PFD_TLSEL_SZ 1
+#define RG_SX_LPF_C1_BT_MSK 0x0000000f
+#define RG_SX_LPF_C1_BT_I_MSK 0xfffffff0
+#define RG_SX_LPF_C1_BT_SFT 0
+#define RG_SX_LPF_C1_BT_HI 3
+#define RG_SX_LPF_C1_BT_SZ 4
+#define RG_SX_LPF_C2_BT_MSK 0x000000f0
+#define RG_SX_LPF_C2_BT_I_MSK 0xffffff0f
+#define RG_SX_LPF_C2_BT_SFT 4
+#define RG_SX_LPF_C2_BT_HI 7
+#define RG_SX_LPF_C2_BT_SZ 4
+#define RG_SX_LPF_C3_BT_MSK 0x00000100
+#define RG_SX_LPF_C3_BT_I_MSK 0xfffffeff
+#define RG_SX_LPF_C3_BT_SFT 8
+#define RG_SX_LPF_C3_BT_HI 8
+#define RG_SX_LPF_C3_BT_SZ 1
+#define RG_SX_LPF_R2_BT_MSK 0x00001e00
+#define RG_SX_LPF_R2_BT_I_MSK 0xffffe1ff
+#define RG_SX_LPF_R2_BT_SFT 9
+#define RG_SX_LPF_R2_BT_HI 12
+#define RG_SX_LPF_R2_BT_SZ 4
+#define RG_SX_LPF_R3_BT_MSK 0x0000e000
+#define RG_SX_LPF_R3_BT_I_MSK 0xffff1fff
+#define RG_SX_LPF_R3_BT_SFT 13
+#define RG_SX_LPF_R3_BT_HI 15
+#define RG_SX_LPF_R3_BT_SZ 3
+#define RG_SX_LPF_C1_WF_MSK 0x000f0000
+#define RG_SX_LPF_C1_WF_I_MSK 0xfff0ffff
+#define RG_SX_LPF_C1_WF_SFT 16
+#define RG_SX_LPF_C1_WF_HI 19
+#define RG_SX_LPF_C1_WF_SZ 4
+#define RG_SX_LPF_C2_WF_MSK 0x00f00000
+#define RG_SX_LPF_C2_WF_I_MSK 0xff0fffff
+#define RG_SX_LPF_C2_WF_SFT 20
+#define RG_SX_LPF_C2_WF_HI 23
+#define RG_SX_LPF_C2_WF_SZ 4
+#define RG_SX_LPF_C3_WF_MSK 0x01000000
+#define RG_SX_LPF_C3_WF_I_MSK 0xfeffffff
+#define RG_SX_LPF_C3_WF_SFT 24
+#define RG_SX_LPF_C3_WF_HI 24
+#define RG_SX_LPF_C3_WF_SZ 1
+#define RG_SX_LPF_R2_WF_MSK 0x1e000000
+#define RG_SX_LPF_R2_WF_I_MSK 0xe1ffffff
+#define RG_SX_LPF_R2_WF_SFT 25
+#define RG_SX_LPF_R2_WF_HI 28
+#define RG_SX_LPF_R2_WF_SZ 4
+#define RG_SX_LPF_R3_WF_MSK 0xe0000000
+#define RG_SX_LPF_R3_WF_I_MSK 0x1fffffff
+#define RG_SX_LPF_R3_WF_SFT 29
+#define RG_SX_LPF_R3_WF_HI 31
+#define RG_SX_LPF_R3_WF_SZ 3
+#define RG_SX_VCO_ISEL_MAN_MSK 0x00000001
+#define RG_SX_VCO_ISEL_MAN_I_MSK 0xfffffffe
+#define RG_SX_VCO_ISEL_MAN_SFT 0
+#define RG_SX_VCO_ISEL_MAN_HI 0
+#define RG_SX_VCO_ISEL_MAN_SZ 1
+#define RG_SX_VCO_ISEL_BT_MSK 0x0000001e
+#define RG_SX_VCO_ISEL_BT_I_MSK 0xffffffe1
+#define RG_SX_VCO_ISEL_BT_SFT 1
+#define RG_SX_VCO_ISEL_BT_HI 4
+#define RG_SX_VCO_ISEL_BT_SZ 4
+#define RG_SX_VCO_LPM_BT_MSK 0x00000020
+#define RG_SX_VCO_LPM_BT_I_MSK 0xffffffdf
+#define RG_SX_VCO_LPM_BT_SFT 5
+#define RG_SX_VCO_LPM_BT_HI 5
+#define RG_SX_VCO_LPM_BT_SZ 1
+#define RG_SX_VCO_VCCBSEL_BT_MSK 0x000001c0
+#define RG_SX_VCO_VCCBSEL_BT_I_MSK 0xfffffe3f
+#define RG_SX_VCO_VCCBSEL_BT_SFT 6
+#define RG_SX_VCO_VCCBSEL_BT_HI 8
+#define RG_SX_VCO_VCCBSEL_BT_SZ 3
+#define RG_SX_VCO_KVDOUB_BT_MSK 0x00000200
+#define RG_SX_VCO_KVDOUB_BT_I_MSK 0xfffffdff
+#define RG_SX_VCO_KVDOUB_BT_SFT 9
+#define RG_SX_VCO_KVDOUB_BT_HI 9
+#define RG_SX_VCO_KVDOUB_BT_SZ 1
+#define RG_SX_VCO_ISEL_WF_MSK 0x00003c00
+#define RG_SX_VCO_ISEL_WF_I_MSK 0xffffc3ff
+#define RG_SX_VCO_ISEL_WF_SFT 10
+#define RG_SX_VCO_ISEL_WF_HI 13
+#define RG_SX_VCO_ISEL_WF_SZ 4
+#define RG_SX_VCO_LPM_WF_MSK 0x00004000
+#define RG_SX_VCO_LPM_WF_I_MSK 0xffffbfff
+#define RG_SX_VCO_LPM_WF_SFT 14
+#define RG_SX_VCO_LPM_WF_HI 14
+#define RG_SX_VCO_LPM_WF_SZ 1
+#define RG_SX_VCO_VCCBSEL_WF_MSK 0x00038000
+#define RG_SX_VCO_VCCBSEL_WF_I_MSK 0xfffc7fff
+#define RG_SX_VCO_VCCBSEL_WF_SFT 15
+#define RG_SX_VCO_VCCBSEL_WF_HI 17
+#define RG_SX_VCO_VCCBSEL_WF_SZ 3
+#define RG_SX_VCO_KVDOUB_WF_MSK 0x00040000
+#define RG_SX_VCO_KVDOUB_WF_I_MSK 0xfffbffff
+#define RG_SX_VCO_KVDOUB_WF_SFT 18
+#define RG_SX_VCO_KVDOUB_WF_HI 18
+#define RG_SX_VCO_KVDOUB_WF_SZ 1
+#define RG_SX_VCO_VARBSEL_MSK 0x00600000
+#define RG_SX_VCO_VARBSEL_I_MSK 0xff9fffff
+#define RG_SX_VCO_VARBSEL_SFT 21
+#define RG_SX_VCO_VARBSEL_HI 22
+#define RG_SX_VCO_VARBSEL_SZ 2
+#define RG_SX_VCO_RTAIL_SHIFT_MSK 0x00800000
+#define RG_SX_VCO_RTAIL_SHIFT_I_MSK 0xff7fffff
+#define RG_SX_VCO_RTAIL_SHIFT_SFT 23
+#define RG_SX_VCO_RTAIL_SHIFT_HI 23
+#define RG_SX_VCO_RTAIL_SHIFT_SZ 1
+#define RG_SX_VCO_CS_AWH_MSK 0x01000000
+#define RG_SX_VCO_CS_AWH_I_MSK 0xfeffffff
+#define RG_SX_VCO_CS_AWH_SFT 24
+#define RG_SX_VCO_CS_AWH_HI 24
+#define RG_SX_VCO_CS_AWH_SZ 1
+#define RG_VOBF_TXMBSEL_BT_MSK 0x00000003
+#define RG_VOBF_TXMBSEL_BT_I_MSK 0xfffffffc
+#define RG_VOBF_TXMBSEL_BT_SFT 0
+#define RG_VOBF_TXMBSEL_BT_HI 1
+#define RG_VOBF_TXMBSEL_BT_SZ 2
+#define RG_VOBF_TXOBSEL_BT_MSK 0x0000000c
+#define RG_VOBF_TXOBSEL_BT_I_MSK 0xfffffff3
+#define RG_VOBF_TXOBSEL_BT_SFT 2
+#define RG_VOBF_TXOBSEL_BT_HI 3
+#define RG_VOBF_TXOBSEL_BT_SZ 2
+#define RG_VOBF_RXMBSEL_BT_MSK 0x00000030
+#define RG_VOBF_RXMBSEL_BT_I_MSK 0xffffffcf
+#define RG_VOBF_RXMBSEL_BT_SFT 4
+#define RG_VOBF_RXMBSEL_BT_HI 5
+#define RG_VOBF_RXMBSEL_BT_SZ 2
+#define RG_VOBF_RXOBSEL_BT_MSK 0x000000c0
+#define RG_VOBF_RXOBSEL_BT_I_MSK 0xffffff3f
+#define RG_VOBF_RXOBSEL_BT_SFT 6
+#define RG_VOBF_RXOBSEL_BT_HI 7
+#define RG_VOBF_RXOBSEL_BT_SZ 2
+#define RG_VOBF_TXMBSEL_WF_MSK 0x00000c00
+#define RG_VOBF_TXMBSEL_WF_I_MSK 0xfffff3ff
+#define RG_VOBF_TXMBSEL_WF_SFT 10
+#define RG_VOBF_TXMBSEL_WF_HI 11
+#define RG_VOBF_TXMBSEL_WF_SZ 2
+#define RG_VOBF_TXOBSEL_WF_MSK 0x00003000
+#define RG_VOBF_TXOBSEL_WF_I_MSK 0xffffcfff
+#define RG_VOBF_TXOBSEL_WF_SFT 12
+#define RG_VOBF_TXOBSEL_WF_HI 13
+#define RG_VOBF_TXOBSEL_WF_SZ 2
+#define RG_VOBF_RXMBSEL_WF_MSK 0x0000c000
+#define RG_VOBF_RXMBSEL_WF_I_MSK 0xffff3fff
+#define RG_VOBF_RXMBSEL_WF_SFT 14
+#define RG_VOBF_RXMBSEL_WF_HI 15
+#define RG_VOBF_RXMBSEL_WF_SZ 2
+#define RG_VOBF_RXOBSEL_WF_MSK 0x00030000
+#define RG_VOBF_RXOBSEL_WF_I_MSK 0xfffcffff
+#define RG_VOBF_RXOBSEL_WF_SFT 16
+#define RG_VOBF_RXOBSEL_WF_HI 17
+#define RG_VOBF_RXOBSEL_WF_SZ 2
+#define RG_VOBF_DIVBFSEL_MSK 0x00080000
+#define RG_VOBF_DIVBFSEL_I_MSK 0xfff7ffff
+#define RG_VOBF_DIVBFSEL_SFT 19
+#define RG_VOBF_DIVBFSEL_HI 19
+#define RG_VOBF_DIVBFSEL_SZ 1
+#define RG_SX_VCO_TXOB_AW_MSK 0x00100000
+#define RG_SX_VCO_TXOB_AW_I_MSK 0xffefffff
+#define RG_SX_VCO_TXOB_AW_SFT 20
+#define RG_SX_VCO_TXOB_AW_HI 20
+#define RG_SX_VCO_TXOB_AW_SZ 1
+#define RG_SX_VCO_RXOB_AW_MSK 0x00200000
+#define RG_SX_VCO_RXOB_AW_I_MSK 0xffdfffff
+#define RG_SX_VCO_RXOB_AW_SFT 21
+#define RG_SX_VCO_RXOB_AW_HI 21
+#define RG_SX_VCO_RXOB_AW_SZ 1
+#define RG_VOBF_CAPIMB_POL_MSK 0x04000000
+#define RG_VOBF_CAPIMB_POL_I_MSK 0xfbffffff
+#define RG_VOBF_CAPIMB_POL_SFT 26
+#define RG_VOBF_CAPIMB_POL_HI 26
+#define RG_VOBF_CAPIMB_POL_SZ 1
+#define RG_VOBF_CAPIMB_MSK 0x38000000
+#define RG_VOBF_CAPIMB_I_MSK 0xc7ffffff
+#define RG_VOBF_CAPIMB_SFT 27
+#define RG_VOBF_CAPIMB_HI 29
+#define RG_VOBF_CAPIMB_SZ 3
+#define RG_EN_SX_VCOMON_MSK 0x80000000
+#define RG_EN_SX_VCOMON_I_MSK 0x7fffffff
+#define RG_EN_SX_VCOMON_SFT 31
+#define RG_EN_SX_VCOMON_HI 31
+#define RG_EN_SX_VCOMON_SZ 1
+#define RG_SX_DIV_PREVDD_MSK 0x0000000f
+#define RG_SX_DIV_PREVDD_I_MSK 0xfffffff0
+#define RG_SX_DIV_PREVDD_SFT 0
+#define RG_SX_DIV_PREVDD_HI 3
+#define RG_SX_DIV_PREVDD_SZ 4
+#define RG_SX_DIV_PSCVDD_MSK 0x000000f0
+#define RG_SX_DIV_PSCVDD_I_MSK 0xffffff0f
+#define RG_SX_DIV_PSCVDD_SFT 4
+#define RG_SX_DIV_PSCVDD_HI 7
+#define RG_SX_DIV_PSCVDD_SZ 4
+#define RG_SX_DIV_RST_H_MSK 0x00000200
+#define RG_SX_DIV_RST_H_I_MSK 0xfffffdff
+#define RG_SX_DIV_RST_H_SFT 9
+#define RG_SX_DIV_RST_H_HI 9
+#define RG_SX_DIV_RST_H_SZ 1
+#define RG_SX_DIV_SDM_EDGE_MSK 0x00000400
+#define RG_SX_DIV_SDM_EDGE_I_MSK 0xfffffbff
+#define RG_SX_DIV_SDM_EDGE_SFT 10
+#define RG_SX_DIV_SDM_EDGE_HI 10
+#define RG_SX_DIV_SDM_EDGE_SZ 1
+#define RG_SX_DIV_DMYBUF_EN_MSK 0x00000800
+#define RG_SX_DIV_DMYBUF_EN_I_MSK 0xfffff7ff
+#define RG_SX_DIV_DMYBUF_EN_SFT 11
+#define RG_SX_DIV_DMYBUF_EN_HI 11
+#define RG_SX_DIV_DMYBUF_EN_SZ 1
+#define RG_EN_SX_MOD_MSK 0x00020000
+#define RG_EN_SX_MOD_I_MSK 0xfffdffff
+#define RG_EN_SX_MOD_SFT 17
+#define RG_EN_SX_MOD_HI 17
+#define RG_EN_SX_MOD_SZ 1
+#define RG_EN_SX_DITHER_MSK 0x00040000
+#define RG_EN_SX_DITHER_I_MSK 0xfffbffff
+#define RG_EN_SX_DITHER_SFT 18
+#define RG_EN_SX_DITHER_HI 18
+#define RG_EN_SX_DITHER_SZ 1
+#define RG_SX_MOD_ORDER_MSK 0x00180000
+#define RG_SX_MOD_ORDER_I_MSK 0xffe7ffff
+#define RG_SX_MOD_ORDER_SFT 19
+#define RG_SX_MOD_ORDER_HI 20
+#define RG_SX_MOD_ORDER_SZ 2
+#define RG_SX_DITHER_WEIGHT_MSK 0x00600000
+#define RG_SX_DITHER_WEIGHT_I_MSK 0xff9fffff
+#define RG_SX_DITHER_WEIGHT_SFT 21
+#define RG_SX_DITHER_WEIGHT_HI 22
+#define RG_SX_DITHER_WEIGHT_SZ 2
+#define RG_SX_SUB_SEL_MAN_MSK 0x00000001
+#define RG_SX_SUB_SEL_MAN_I_MSK 0xfffffffe
+#define RG_SX_SUB_SEL_MAN_SFT 0
+#define RG_SX_SUB_SEL_MAN_HI 0
+#define RG_SX_SUB_SEL_MAN_SZ 1
+#define RG_SX_SUB_SEL_MSK 0x000001fe
+#define RG_SX_SUB_SEL_I_MSK 0xfffffe01
+#define RG_SX_SUB_SEL_SFT 1
+#define RG_SX_SUB_SEL_HI 8
+#define RG_SX_SUB_SEL_SZ 8
+#define RG_SX_SUB_C0P5_DIS_MSK 0x00000200
+#define RG_SX_SUB_C0P5_DIS_I_MSK 0xfffffdff
+#define RG_SX_SUB_C0P5_DIS_SFT 9
+#define RG_SX_SUB_C0P5_DIS_HI 9
+#define RG_SX_SUB_C0P5_DIS_SZ 1
+#define RG_SX_SBCAL_CT_MSK 0x00000c00
+#define RG_SX_SBCAL_CT_I_MSK 0xfffff3ff
+#define RG_SX_SBCAL_CT_SFT 10
+#define RG_SX_SBCAL_CT_HI 11
+#define RG_SX_SBCAL_CT_SZ 2
+#define RG_SX_SBCAL_WT_MSK 0x00001000
+#define RG_SX_SBCAL_WT_I_MSK 0xffffefff
+#define RG_SX_SBCAL_WT_SFT 12
+#define RG_SX_SBCAL_WT_HI 12
+#define RG_SX_SBCAL_WT_SZ 1
+#define RG_SX_SBCAL_DIFFMIN_MSK 0x00002000
+#define RG_SX_SBCAL_DIFFMIN_I_MSK 0xffffdfff
+#define RG_SX_SBCAL_DIFFMIN_SFT 13
+#define RG_SX_SBCAL_DIFFMIN_HI 13
+#define RG_SX_SBCAL_DIFFMIN_SZ 1
+#define RG_SX_SBCAL_NTARG_MAN_MSK 0x00008000
+#define RG_SX_SBCAL_NTARG_MAN_I_MSK 0xffff7fff
+#define RG_SX_SBCAL_NTARG_MAN_SFT 15
+#define RG_SX_SBCAL_NTARG_MAN_HI 15
+#define RG_SX_SBCAL_NTARG_MAN_SZ 1
+#define RG_SX_SBCAL_NTARG_MSK 0xffff0000
+#define RG_SX_SBCAL_NTARG_I_MSK 0x0000ffff
+#define RG_SX_SBCAL_NTARG_SFT 16
+#define RG_SX_SBCAL_NTARG_HI 31
+#define RG_SX_SBCAL_NTARG_SZ 16
+#define RG_VO_AAC_TAR_BT_MSK 0x0000000f
+#define RG_VO_AAC_TAR_BT_I_MSK 0xfffffff0
+#define RG_VO_AAC_TAR_BT_SFT 0
+#define RG_VO_AAC_TAR_BT_HI 3
+#define RG_VO_AAC_TAR_BT_SZ 4
+#define RG_VO_AAC_IOST_BT_MSK 0x00000030
+#define RG_VO_AAC_IOST_BT_I_MSK 0xffffffcf
+#define RG_VO_AAC_IOST_BT_SFT 4
+#define RG_VO_AAC_IOST_BT_HI 5
+#define RG_VO_AAC_IOST_BT_SZ 2
+#define RG_VO_AAC_TAR_WF_MSK 0x00000780
+#define RG_VO_AAC_TAR_WF_I_MSK 0xfffff87f
+#define RG_VO_AAC_TAR_WF_SFT 7
+#define RG_VO_AAC_TAR_WF_HI 10
+#define RG_VO_AAC_TAR_WF_SZ 4
+#define RG_VO_AAC_IOST_WF_MSK 0x00001800
+#define RG_VO_AAC_IOST_WF_I_MSK 0xffffe7ff
+#define RG_VO_AAC_IOST_WF_SFT 11
+#define RG_VO_AAC_IOST_WF_HI 12
+#define RG_VO_AAC_IOST_WF_SZ 2
+#define RG_VO_AAC_IMAX_MSK 0x0003c000
+#define RG_VO_AAC_IMAX_I_MSK 0xfffc3fff
+#define RG_VO_AAC_IMAX_SFT 14
+#define RG_VO_AAC_IMAX_HI 17
+#define RG_VO_AAC_IMAX_SZ 4
+#define RG_VO_AAC_INIT_MSK 0x000c0000
+#define RG_VO_AAC_INIT_I_MSK 0xfff3ffff
+#define RG_VO_AAC_INIT_SFT 18
+#define RG_VO_AAC_INIT_HI 19
+#define RG_VO_AAC_INIT_SZ 2
+#define RG_VO_AAC_EVA_TS_MSK 0x00300000
+#define RG_VO_AAC_EVA_TS_I_MSK 0xffcfffff
+#define RG_VO_AAC_EVA_TS_SFT 20
+#define RG_VO_AAC_EVA_TS_HI 21
+#define RG_VO_AAC_EVA_TS_SZ 2
+#define RG_VO_AAC_EN_MAN_MSK 0x00800000
+#define RG_VO_AAC_EN_MAN_I_MSK 0xff7fffff
+#define RG_VO_AAC_EN_MAN_SFT 23
+#define RG_VO_AAC_EN_MAN_HI 23
+#define RG_VO_AAC_EN_MAN_SZ 1
+#define RG_VO_AAC_EN_MSK 0x01000000
+#define RG_VO_AAC_EN_I_MSK 0xfeffffff
+#define RG_VO_AAC_EN_SFT 24
+#define RG_VO_AAC_EN_HI 24
+#define RG_VO_AAC_EN_SZ 1
+#define RG_VO_AAC_EVA_MAN_MSK 0x02000000
+#define RG_VO_AAC_EVA_MAN_I_MSK 0xfdffffff
+#define RG_VO_AAC_EVA_MAN_SFT 25
+#define RG_VO_AAC_EVA_MAN_HI 25
+#define RG_VO_AAC_EVA_MAN_SZ 1
+#define RG_VO_AAC_EVA_MSK 0x04000000
+#define RG_VO_AAC_EVA_I_MSK 0xfbffffff
+#define RG_VO_AAC_EVA_SFT 26
+#define RG_VO_AAC_EVA_HI 26
+#define RG_VO_AAC_EVA_SZ 1
+#define RG_VO_AAC_TEST_EN_MSK 0x10000000
+#define RG_VO_AAC_TEST_EN_I_MSK 0xefffffff
+#define RG_VO_AAC_TEST_EN_SFT 28
+#define RG_VO_AAC_TEST_EN_HI 28
+#define RG_VO_AAC_TEST_EN_SZ 1
+#define RG_VO_AAC_TEST_SEL_MSK 0x20000000
+#define RG_VO_AAC_TEST_SEL_I_MSK 0xdfffffff
+#define RG_VO_AAC_TEST_SEL_SFT 29
+#define RG_VO_AAC_TEST_SEL_HI 29
+#define RG_VO_AAC_TEST_SEL_SZ 1
+#define RG_SX_TTL_INIT_MSK 0x00000003
+#define RG_SX_TTL_INIT_I_MSK 0xfffffffc
+#define RG_SX_TTL_INIT_SFT 0
+#define RG_SX_TTL_INIT_HI 1
+#define RG_SX_TTL_INIT_SZ 2
+#define RG_SX_TTL_FPT_MSK 0x0000000c
+#define RG_SX_TTL_FPT_I_MSK 0xfffffff3
+#define RG_SX_TTL_FPT_SFT 2
+#define RG_SX_TTL_FPT_HI 3
+#define RG_SX_TTL_FPT_SZ 2
+#define RG_SX_TTL_CPT_MSK 0x00000030
+#define RG_SX_TTL_CPT_I_MSK 0xffffffcf
+#define RG_SX_TTL_CPT_SFT 4
+#define RG_SX_TTL_CPT_HI 5
+#define RG_SX_TTL_CPT_SZ 2
+#define RG_SX_TTL_ACCUM_MSK 0x00000180
+#define RG_SX_TTL_ACCUM_I_MSK 0xfffffe7f
+#define RG_SX_TTL_ACCUM_SFT 7
+#define RG_SX_TTL_ACCUM_HI 8
+#define RG_SX_TTL_ACCUM_SZ 2
+#define RG_SX_TTL_SUB_MSK 0x00000c00
+#define RG_SX_TTL_SUB_I_MSK 0xfffff3ff
+#define RG_SX_TTL_SUB_SFT 10
+#define RG_SX_TTL_SUB_HI 11
+#define RG_SX_TTL_SUB_SZ 2
+#define RG_SX_TTL_SUB_INV_MSK 0x00001000
+#define RG_SX_TTL_SUB_INV_I_MSK 0xffffefff
+#define RG_SX_TTL_SUB_INV_SFT 12
+#define RG_SX_TTL_SUB_INV_HI 12
+#define RG_SX_TTL_SUB_INV_SZ 1
+#define RG_SX_TTL_VH_MSK 0x0000c000
+#define RG_SX_TTL_VH_I_MSK 0xffff3fff
+#define RG_SX_TTL_VH_SFT 14
+#define RG_SX_TTL_VH_HI 15
+#define RG_SX_TTL_VH_SZ 2
+#define RG_SX_TTL_VL_MSK 0x00030000
+#define RG_SX_TTL_VL_I_MSK 0xfffcffff
+#define RG_SX_TTL_VL_SFT 16
+#define RG_SX_TTL_VL_HI 17
+#define RG_SX_TTL_VL_SZ 2
+#define RG_SX_LPF_VTUNE_TEST_MSK 0x00080000
+#define RG_SX_LPF_VTUNE_TEST_I_MSK 0xfff7ffff
+#define RG_SX_LPF_VTUNE_TEST_SFT 19
+#define RG_SX_LPF_VTUNE_TEST_HI 19
+#define RG_SX_LPF_VTUNE_TEST_SZ 1
+#define DPLL_TOP_REGISTER_MSK 0xffffffff
+#define DPLL_TOP_REGISTER_I_MSK 0x00000000
+#define DPLL_TOP_REGISTER_SFT 0
+#define DPLL_TOP_REGISTER_HI 31
+#define DPLL_TOP_REGISTER_SZ 32
+#define DPLL_CKT_REGISTER_MSK 0xffffffff
+#define DPLL_CKT_REGISTER_I_MSK 0x00000000
+#define DPLL_CKT_REGISTER_SFT 0
+#define DPLL_CKT_REGISTER_HI 31
+#define DPLL_CKT_REGISTER_SZ 32
+#define DPLL_FB_DIVISION__REGISTERS_MSK 0xffffffff
+#define DPLL_FB_DIVISION__REGISTERS_I_MSK 0x00000000
+#define DPLL_FB_DIVISION__REGISTERS_SFT 0
+#define DPLL_FB_DIVISION__REGISTERS_HI 31
+#define DPLL_FB_DIVISION__REGISTERS_SZ 32
+#define RG_WF_IDACAI_TZ0_PGAG15_MSK 0x0000003f
+#define RG_WF_IDACAI_TZ0_PGAG15_I_MSK 0xffffffc0
+#define RG_WF_IDACAI_TZ0_PGAG15_SFT 0
+#define RG_WF_IDACAI_TZ0_PGAG15_HI 5
+#define RG_WF_IDACAI_TZ0_PGAG15_SZ 6
+#define RG_WF_IDACAQ_TZ0_PGAG15_MSK 0x00003f00
+#define RG_WF_IDACAQ_TZ0_PGAG15_I_MSK 0xffffc0ff
+#define RG_WF_IDACAQ_TZ0_PGAG15_SFT 8
+#define RG_WF_IDACAQ_TZ0_PGAG15_HI 13
+#define RG_WF_IDACAQ_TZ0_PGAG15_SZ 6
+#define RG_WF_IDACAI_TZ0_PGAG14_MSK 0x003f0000
+#define RG_WF_IDACAI_TZ0_PGAG14_I_MSK 0xffc0ffff
+#define RG_WF_IDACAI_TZ0_PGAG14_SFT 16
+#define RG_WF_IDACAI_TZ0_PGAG14_HI 21
+#define RG_WF_IDACAI_TZ0_PGAG14_SZ 6
+#define RG_WF_IDACAQ_TZ0_PGAG14_MSK 0x3f000000
+#define RG_WF_IDACAQ_TZ0_PGAG14_I_MSK 0xc0ffffff
+#define RG_WF_IDACAQ_TZ0_PGAG14_SFT 24
+#define RG_WF_IDACAQ_TZ0_PGAG14_HI 29
+#define RG_WF_IDACAQ_TZ0_PGAG14_SZ 6
+#define RG_WF_IDACAI_TZ0_PGAG13_MSK 0x0000003f
+#define RG_WF_IDACAI_TZ0_PGAG13_I_MSK 0xffffffc0
+#define RG_WF_IDACAI_TZ0_PGAG13_SFT 0
+#define RG_WF_IDACAI_TZ0_PGAG13_HI 5
+#define RG_WF_IDACAI_TZ0_PGAG13_SZ 6
+#define RG_WF_IDACAQ_TZ0_PGAG13_MSK 0x00003f00
+#define RG_WF_IDACAQ_TZ0_PGAG13_I_MSK 0xffffc0ff
+#define RG_WF_IDACAQ_TZ0_PGAG13_SFT 8
+#define RG_WF_IDACAQ_TZ0_PGAG13_HI 13
+#define RG_WF_IDACAQ_TZ0_PGAG13_SZ 6
+#define RG_WF_IDACAI_TZ0_PGAG12_MSK 0x003f0000
+#define RG_WF_IDACAI_TZ0_PGAG12_I_MSK 0xffc0ffff
+#define RG_WF_IDACAI_TZ0_PGAG12_SFT 16
+#define RG_WF_IDACAI_TZ0_PGAG12_HI 21
+#define RG_WF_IDACAI_TZ0_PGAG12_SZ 6
+#define RG_WF_IDACAQ_TZ0_PGAG12_MSK 0x3f000000
+#define RG_WF_IDACAQ_TZ0_PGAG12_I_MSK 0xc0ffffff
+#define RG_WF_IDACAQ_TZ0_PGAG12_SFT 24
+#define RG_WF_IDACAQ_TZ0_PGAG12_HI 29
+#define RG_WF_IDACAQ_TZ0_PGAG12_SZ 6
+#define RG_WF_IDACAI_TZ0_PGAG11_MSK 0x0000003f
+#define RG_WF_IDACAI_TZ0_PGAG11_I_MSK 0xffffffc0
+#define RG_WF_IDACAI_TZ0_PGAG11_SFT 0
+#define RG_WF_IDACAI_TZ0_PGAG11_HI 5
+#define RG_WF_IDACAI_TZ0_PGAG11_SZ 6
+#define RG_WF_IDACAQ_TZ0_PGAG11_MSK 0x00003f00
+#define RG_WF_IDACAQ_TZ0_PGAG11_I_MSK 0xffffc0ff
+#define RG_WF_IDACAQ_TZ0_PGAG11_SFT 8
+#define RG_WF_IDACAQ_TZ0_PGAG11_HI 13
+#define RG_WF_IDACAQ_TZ0_PGAG11_SZ 6
+#define RG_WF_IDACAI_TZ0_PGAG10_MSK 0x003f0000
+#define RG_WF_IDACAI_TZ0_PGAG10_I_MSK 0xffc0ffff
+#define RG_WF_IDACAI_TZ0_PGAG10_SFT 16
+#define RG_WF_IDACAI_TZ0_PGAG10_HI 21
+#define RG_WF_IDACAI_TZ0_PGAG10_SZ 6
+#define RG_WF_IDACAQ_TZ0_PGAG10_MSK 0x3f000000
+#define RG_WF_IDACAQ_TZ0_PGAG10_I_MSK 0xc0ffffff
+#define RG_WF_IDACAQ_TZ0_PGAG10_SFT 24
+#define RG_WF_IDACAQ_TZ0_PGAG10_HI 29
+#define RG_WF_IDACAQ_TZ0_PGAG10_SZ 6
+#define RG_WF_IDACAI_TZ0_PGAG9_MSK 0x0000003f
+#define RG_WF_IDACAI_TZ0_PGAG9_I_MSK 0xffffffc0
+#define RG_WF_IDACAI_TZ0_PGAG9_SFT 0
+#define RG_WF_IDACAI_TZ0_PGAG9_HI 5
+#define RG_WF_IDACAI_TZ0_PGAG9_SZ 6
+#define RG_WF_IDACAQ_TZ0_PGAG9_MSK 0x00003f00
+#define RG_WF_IDACAQ_TZ0_PGAG9_I_MSK 0xffffc0ff
+#define RG_WF_IDACAQ_TZ0_PGAG9_SFT 8
+#define RG_WF_IDACAQ_TZ0_PGAG9_HI 13
+#define RG_WF_IDACAQ_TZ0_PGAG9_SZ 6
+#define RG_WF_IDACAI_TZ0_PGAG8_MSK 0x003f0000
+#define RG_WF_IDACAI_TZ0_PGAG8_I_MSK 0xffc0ffff
+#define RG_WF_IDACAI_TZ0_PGAG8_SFT 16
+#define RG_WF_IDACAI_TZ0_PGAG8_HI 21
+#define RG_WF_IDACAI_TZ0_PGAG8_SZ 6
+#define RG_WF_IDACAQ_TZ0_PGAG8_MSK 0x3f000000
+#define RG_WF_IDACAQ_TZ0_PGAG8_I_MSK 0xc0ffffff
+#define RG_WF_IDACAQ_TZ0_PGAG8_SFT 24
+#define RG_WF_IDACAQ_TZ0_PGAG8_HI 29
+#define RG_WF_IDACAQ_TZ0_PGAG8_SZ 6
+#define RG_WF_IDACAI_TZ0_PGAG7_MSK 0x0000003f
+#define RG_WF_IDACAI_TZ0_PGAG7_I_MSK 0xffffffc0
+#define RG_WF_IDACAI_TZ0_PGAG7_SFT 0
+#define RG_WF_IDACAI_TZ0_PGAG7_HI 5
+#define RG_WF_IDACAI_TZ0_PGAG7_SZ 6
+#define RG_WF_IDACAQ_TZ0_PGAG7_MSK 0x00003f00
+#define RG_WF_IDACAQ_TZ0_PGAG7_I_MSK 0xffffc0ff
+#define RG_WF_IDACAQ_TZ0_PGAG7_SFT 8
+#define RG_WF_IDACAQ_TZ0_PGAG7_HI 13
+#define RG_WF_IDACAQ_TZ0_PGAG7_SZ 6
+#define RG_WF_IDACAI_TZ0_PGAG6_MSK 0x003f0000
+#define RG_WF_IDACAI_TZ0_PGAG6_I_MSK 0xffc0ffff
+#define RG_WF_IDACAI_TZ0_PGAG6_SFT 16
+#define RG_WF_IDACAI_TZ0_PGAG6_HI 21
+#define RG_WF_IDACAI_TZ0_PGAG6_SZ 6
+#define RG_WF_IDACAQ_TZ0_PGAG6_MSK 0x3f000000
+#define RG_WF_IDACAQ_TZ0_PGAG6_I_MSK 0xc0ffffff
+#define RG_WF_IDACAQ_TZ0_PGAG6_SFT 24
+#define RG_WF_IDACAQ_TZ0_PGAG6_HI 29
+#define RG_WF_IDACAQ_TZ0_PGAG6_SZ 6
+#define RG_WF_IDACAI_TZ0_PGAG5_MSK 0x0000003f
+#define RG_WF_IDACAI_TZ0_PGAG5_I_MSK 0xffffffc0
+#define RG_WF_IDACAI_TZ0_PGAG5_SFT 0
+#define RG_WF_IDACAI_TZ0_PGAG5_HI 5
+#define RG_WF_IDACAI_TZ0_PGAG5_SZ 6
+#define RG_WF_IDACAQ_TZ0_PGAG5_MSK 0x00003f00
+#define RG_WF_IDACAQ_TZ0_PGAG5_I_MSK 0xffffc0ff
+#define RG_WF_IDACAQ_TZ0_PGAG5_SFT 8
+#define RG_WF_IDACAQ_TZ0_PGAG5_HI 13
+#define RG_WF_IDACAQ_TZ0_PGAG5_SZ 6
+#define RG_WF_IDACAI_TZ0_PGAG4_MSK 0x003f0000
+#define RG_WF_IDACAI_TZ0_PGAG4_I_MSK 0xffc0ffff
+#define RG_WF_IDACAI_TZ0_PGAG4_SFT 16
+#define RG_WF_IDACAI_TZ0_PGAG4_HI 21
+#define RG_WF_IDACAI_TZ0_PGAG4_SZ 6
+#define RG_WF_IDACAQ_TZ0_PGAG4_MSK 0x3f000000
+#define RG_WF_IDACAQ_TZ0_PGAG4_I_MSK 0xc0ffffff
+#define RG_WF_IDACAQ_TZ0_PGAG4_SFT 24
+#define RG_WF_IDACAQ_TZ0_PGAG4_HI 29
+#define RG_WF_IDACAQ_TZ0_PGAG4_SZ 6
+#define RG_WF_IDACAI_TZ0_PGAG3_MSK 0x0000003f
+#define RG_WF_IDACAI_TZ0_PGAG3_I_MSK 0xffffffc0
+#define RG_WF_IDACAI_TZ0_PGAG3_SFT 0
+#define RG_WF_IDACAI_TZ0_PGAG3_HI 5
+#define RG_WF_IDACAI_TZ0_PGAG3_SZ 6
+#define RG_WF_IDACAQ_TZ0_PGAG3_MSK 0x00003f00
+#define RG_WF_IDACAQ_TZ0_PGAG3_I_MSK 0xffffc0ff
+#define RG_WF_IDACAQ_TZ0_PGAG3_SFT 8
+#define RG_WF_IDACAQ_TZ0_PGAG3_HI 13
+#define RG_WF_IDACAQ_TZ0_PGAG3_SZ 6
+#define RG_WF_IDACAI_TZ0_PGAG2_MSK 0x003f0000
+#define RG_WF_IDACAI_TZ0_PGAG2_I_MSK 0xffc0ffff
+#define RG_WF_IDACAI_TZ0_PGAG2_SFT 16
+#define RG_WF_IDACAI_TZ0_PGAG2_HI 21
+#define RG_WF_IDACAI_TZ0_PGAG2_SZ 6
+#define RG_WF_IDACAQ_TZ0_PGAG2_MSK 0x3f000000
+#define RG_WF_IDACAQ_TZ0_PGAG2_I_MSK 0xc0ffffff
+#define RG_WF_IDACAQ_TZ0_PGAG2_SFT 24
+#define RG_WF_IDACAQ_TZ0_PGAG2_HI 29
+#define RG_WF_IDACAQ_TZ0_PGAG2_SZ 6
+#define RG_WF_IDACAI_TZ0_PGAG1_MSK 0x0000003f
+#define RG_WF_IDACAI_TZ0_PGAG1_I_MSK 0xffffffc0
+#define RG_WF_IDACAI_TZ0_PGAG1_SFT 0
+#define RG_WF_IDACAI_TZ0_PGAG1_HI 5
+#define RG_WF_IDACAI_TZ0_PGAG1_SZ 6
+#define RG_WF_IDACAQ_TZ0_PGAG1_MSK 0x00003f00
+#define RG_WF_IDACAQ_TZ0_PGAG1_I_MSK 0xffffc0ff
+#define RG_WF_IDACAQ_TZ0_PGAG1_SFT 8
+#define RG_WF_IDACAQ_TZ0_PGAG1_HI 13
+#define RG_WF_IDACAQ_TZ0_PGAG1_SZ 6
+#define RG_WF_IDACAI_TZ0_PGAG0_MSK 0x003f0000
+#define RG_WF_IDACAI_TZ0_PGAG0_I_MSK 0xffc0ffff
+#define RG_WF_IDACAI_TZ0_PGAG0_SFT 16
+#define RG_WF_IDACAI_TZ0_PGAG0_HI 21
+#define RG_WF_IDACAI_TZ0_PGAG0_SZ 6
+#define RG_WF_IDACAQ_TZ0_PGAG0_MSK 0x3f000000
+#define RG_WF_IDACAQ_TZ0_PGAG0_I_MSK 0xc0ffffff
+#define RG_WF_IDACAQ_TZ0_PGAG0_SFT 24
+#define RG_WF_IDACAQ_TZ0_PGAG0_HI 29
+#define RG_WF_IDACAQ_TZ0_PGAG0_SZ 6
+#define RG_WF_IDACAI_TZ1_PGAG15_MSK 0x0000003f
+#define RG_WF_IDACAI_TZ1_PGAG15_I_MSK 0xffffffc0
+#define RG_WF_IDACAI_TZ1_PGAG15_SFT 0
+#define RG_WF_IDACAI_TZ1_PGAG15_HI 5
+#define RG_WF_IDACAI_TZ1_PGAG15_SZ 6
+#define RG_WF_IDACAQ_TZ1_PGAG15_MSK 0x00003f00
+#define RG_WF_IDACAQ_TZ1_PGAG15_I_MSK 0xffffc0ff
+#define RG_WF_IDACAQ_TZ1_PGAG15_SFT 8
+#define RG_WF_IDACAQ_TZ1_PGAG15_HI 13
+#define RG_WF_IDACAQ_TZ1_PGAG15_SZ 6
+#define RG_WF_IDACAI_TZ1_PGAG14_MSK 0x003f0000
+#define RG_WF_IDACAI_TZ1_PGAG14_I_MSK 0xffc0ffff
+#define RG_WF_IDACAI_TZ1_PGAG14_SFT 16
+#define RG_WF_IDACAI_TZ1_PGAG14_HI 21
+#define RG_WF_IDACAI_TZ1_PGAG14_SZ 6
+#define RG_WF_IDACAQ_TZ1_PGAG14_MSK 0x3f000000
+#define RG_WF_IDACAQ_TZ1_PGAG14_I_MSK 0xc0ffffff
+#define RG_WF_IDACAQ_TZ1_PGAG14_SFT 24
+#define RG_WF_IDACAQ_TZ1_PGAG14_HI 29
+#define RG_WF_IDACAQ_TZ1_PGAG14_SZ 6
+#define RG_WF_IDACAI_TZ1_PGAG13_MSK 0x0000003f
+#define RG_WF_IDACAI_TZ1_PGAG13_I_MSK 0xffffffc0
+#define RG_WF_IDACAI_TZ1_PGAG13_SFT 0
+#define RG_WF_IDACAI_TZ1_PGAG13_HI 5
+#define RG_WF_IDACAI_TZ1_PGAG13_SZ 6
+#define RG_WF_IDACAQ_TZ1_PGAG13_MSK 0x00003f00
+#define RG_WF_IDACAQ_TZ1_PGAG13_I_MSK 0xffffc0ff
+#define RG_WF_IDACAQ_TZ1_PGAG13_SFT 8
+#define RG_WF_IDACAQ_TZ1_PGAG13_HI 13
+#define RG_WF_IDACAQ_TZ1_PGAG13_SZ 6
+#define RG_WF_IDACAI_TZ1_PGAG12_MSK 0x003f0000
+#define RG_WF_IDACAI_TZ1_PGAG12_I_MSK 0xffc0ffff
+#define RG_WF_IDACAI_TZ1_PGAG12_SFT 16
+#define RG_WF_IDACAI_TZ1_PGAG12_HI 21
+#define RG_WF_IDACAI_TZ1_PGAG12_SZ 6
+#define RG_WF_IDACAQ_TZ1_PGAG12_MSK 0x3f000000
+#define RG_WF_IDACAQ_TZ1_PGAG12_I_MSK 0xc0ffffff
+#define RG_WF_IDACAQ_TZ1_PGAG12_SFT 24
+#define RG_WF_IDACAQ_TZ1_PGAG12_HI 29
+#define RG_WF_IDACAQ_TZ1_PGAG12_SZ 6
+#define RG_WF_IDACAI_TZ1_PGAG11_MSK 0x0000003f
+#define RG_WF_IDACAI_TZ1_PGAG11_I_MSK 0xffffffc0
+#define RG_WF_IDACAI_TZ1_PGAG11_SFT 0
+#define RG_WF_IDACAI_TZ1_PGAG11_HI 5
+#define RG_WF_IDACAI_TZ1_PGAG11_SZ 6
+#define RG_WF_IDACAQ_TZ1_PGAG11_MSK 0x00003f00
+#define RG_WF_IDACAQ_TZ1_PGAG11_I_MSK 0xffffc0ff
+#define RG_WF_IDACAQ_TZ1_PGAG11_SFT 8
+#define RG_WF_IDACAQ_TZ1_PGAG11_HI 13
+#define RG_WF_IDACAQ_TZ1_PGAG11_SZ 6
+#define RG_WF_IDACAI_TZ1_PGAG10_MSK 0x003f0000
+#define RG_WF_IDACAI_TZ1_PGAG10_I_MSK 0xffc0ffff
+#define RG_WF_IDACAI_TZ1_PGAG10_SFT 16
+#define RG_WF_IDACAI_TZ1_PGAG10_HI 21
+#define RG_WF_IDACAI_TZ1_PGAG10_SZ 6
+#define RG_WF_IDACAQ_TZ1_PGAG10_MSK 0x3f000000
+#define RG_WF_IDACAQ_TZ1_PGAG10_I_MSK 0xc0ffffff
+#define RG_WF_IDACAQ_TZ1_PGAG10_SFT 24
+#define RG_WF_IDACAQ_TZ1_PGAG10_HI 29
+#define RG_WF_IDACAQ_TZ1_PGAG10_SZ 6
+#define RG_WF_IDACAI_TZ1_PGAG9_MSK 0x0000003f
+#define RG_WF_IDACAI_TZ1_PGAG9_I_MSK 0xffffffc0
+#define RG_WF_IDACAI_TZ1_PGAG9_SFT 0
+#define RG_WF_IDACAI_TZ1_PGAG9_HI 5
+#define RG_WF_IDACAI_TZ1_PGAG9_SZ 6
+#define RG_WF_IDACAQ_TZ1_PGAG9_MSK 0x00003f00
+#define RG_WF_IDACAQ_TZ1_PGAG9_I_MSK 0xffffc0ff
+#define RG_WF_IDACAQ_TZ1_PGAG9_SFT 8
+#define RG_WF_IDACAQ_TZ1_PGAG9_HI 13
+#define RG_WF_IDACAQ_TZ1_PGAG9_SZ 6
+#define RG_WF_IDACAI_TZ1_PGAG8_MSK 0x003f0000
+#define RG_WF_IDACAI_TZ1_PGAG8_I_MSK 0xffc0ffff
+#define RG_WF_IDACAI_TZ1_PGAG8_SFT 16
+#define RG_WF_IDACAI_TZ1_PGAG8_HI 21
+#define RG_WF_IDACAI_TZ1_PGAG8_SZ 6
+#define RG_WF_IDACAQ_TZ1_PGAG8_MSK 0x3f000000
+#define RG_WF_IDACAQ_TZ1_PGAG8_I_MSK 0xc0ffffff
+#define RG_WF_IDACAQ_TZ1_PGAG8_SFT 24
+#define RG_WF_IDACAQ_TZ1_PGAG8_HI 29
+#define RG_WF_IDACAQ_TZ1_PGAG8_SZ 6
+#define RG_WF_IDACAI_TZ1_PGAG7_MSK 0x0000003f
+#define RG_WF_IDACAI_TZ1_PGAG7_I_MSK 0xffffffc0
+#define RG_WF_IDACAI_TZ1_PGAG7_SFT 0
+#define RG_WF_IDACAI_TZ1_PGAG7_HI 5
+#define RG_WF_IDACAI_TZ1_PGAG7_SZ 6
+#define RG_WF_IDACAQ_TZ1_PGAG7_MSK 0x00003f00
+#define RG_WF_IDACAQ_TZ1_PGAG7_I_MSK 0xffffc0ff
+#define RG_WF_IDACAQ_TZ1_PGAG7_SFT 8
+#define RG_WF_IDACAQ_TZ1_PGAG7_HI 13
+#define RG_WF_IDACAQ_TZ1_PGAG7_SZ 6
+#define RG_WF_IDACAI_TZ1_PGAG6_MSK 0x003f0000
+#define RG_WF_IDACAI_TZ1_PGAG6_I_MSK 0xffc0ffff
+#define RG_WF_IDACAI_TZ1_PGAG6_SFT 16
+#define RG_WF_IDACAI_TZ1_PGAG6_HI 21
+#define RG_WF_IDACAI_TZ1_PGAG6_SZ 6
+#define RG_WF_IDACAQ_TZ1_PGAG6_MSK 0x3f000000
+#define RG_WF_IDACAQ_TZ1_PGAG6_I_MSK 0xc0ffffff
+#define RG_WF_IDACAQ_TZ1_PGAG6_SFT 24
+#define RG_WF_IDACAQ_TZ1_PGAG6_HI 29
+#define RG_WF_IDACAQ_TZ1_PGAG6_SZ 6
+#define RG_WF_IDACAI_TZ1_PGAG5_MSK 0x0000003f
+#define RG_WF_IDACAI_TZ1_PGAG5_I_MSK 0xffffffc0
+#define RG_WF_IDACAI_TZ1_PGAG5_SFT 0
+#define RG_WF_IDACAI_TZ1_PGAG5_HI 5
+#define RG_WF_IDACAI_TZ1_PGAG5_SZ 6
+#define RG_WF_IDACAQ_TZ1_PGAG5_MSK 0x00003f00
+#define RG_WF_IDACAQ_TZ1_PGAG5_I_MSK 0xffffc0ff
+#define RG_WF_IDACAQ_TZ1_PGAG5_SFT 8
+#define RG_WF_IDACAQ_TZ1_PGAG5_HI 13
+#define RG_WF_IDACAQ_TZ1_PGAG5_SZ 6
+#define RG_WF_IDACAI_TZ1_PGAG4_MSK 0x003f0000
+#define RG_WF_IDACAI_TZ1_PGAG4_I_MSK 0xffc0ffff
+#define RG_WF_IDACAI_TZ1_PGAG4_SFT 16
+#define RG_WF_IDACAI_TZ1_PGAG4_HI 21
+#define RG_WF_IDACAI_TZ1_PGAG4_SZ 6
+#define RG_WF_IDACAQ_TZ1_PGAG4_MSK 0x3f000000
+#define RG_WF_IDACAQ_TZ1_PGAG4_I_MSK 0xc0ffffff
+#define RG_WF_IDACAQ_TZ1_PGAG4_SFT 24
+#define RG_WF_IDACAQ_TZ1_PGAG4_HI 29
+#define RG_WF_IDACAQ_TZ1_PGAG4_SZ 6
+#define RG_WF_IDACAI_TZ1_PGAG3_MSK 0x0000003f
+#define RG_WF_IDACAI_TZ1_PGAG3_I_MSK 0xffffffc0
+#define RG_WF_IDACAI_TZ1_PGAG3_SFT 0
+#define RG_WF_IDACAI_TZ1_PGAG3_HI 5
+#define RG_WF_IDACAI_TZ1_PGAG3_SZ 6
+#define RG_WF_IDACAQ_TZ1_PGAG3_MSK 0x00003f00
+#define RG_WF_IDACAQ_TZ1_PGAG3_I_MSK 0xffffc0ff
+#define RG_WF_IDACAQ_TZ1_PGAG3_SFT 8
+#define RG_WF_IDACAQ_TZ1_PGAG3_HI 13
+#define RG_WF_IDACAQ_TZ1_PGAG3_SZ 6
+#define RG_WF_IDACAI_TZ1_PGAG2_MSK 0x003f0000
+#define RG_WF_IDACAI_TZ1_PGAG2_I_MSK 0xffc0ffff
+#define RG_WF_IDACAI_TZ1_PGAG2_SFT 16
+#define RG_WF_IDACAI_TZ1_PGAG2_HI 21
+#define RG_WF_IDACAI_TZ1_PGAG2_SZ 6
+#define RG_WF_IDACAQ_TZ1_PGAG2_MSK 0x3f000000
+#define RG_WF_IDACAQ_TZ1_PGAG2_I_MSK 0xc0ffffff
+#define RG_WF_IDACAQ_TZ1_PGAG2_SFT 24
+#define RG_WF_IDACAQ_TZ1_PGAG2_HI 29
+#define RG_WF_IDACAQ_TZ1_PGAG2_SZ 6
+#define RG_WF_IDACAI_TZ1_PGAG1_MSK 0x0000003f
+#define RG_WF_IDACAI_TZ1_PGAG1_I_MSK 0xffffffc0
+#define RG_WF_IDACAI_TZ1_PGAG1_SFT 0
+#define RG_WF_IDACAI_TZ1_PGAG1_HI 5
+#define RG_WF_IDACAI_TZ1_PGAG1_SZ 6
+#define RG_WF_IDACAQ_TZ1_PGAG1_MSK 0x00003f00
+#define RG_WF_IDACAQ_TZ1_PGAG1_I_MSK 0xffffc0ff
+#define RG_WF_IDACAQ_TZ1_PGAG1_SFT 8
+#define RG_WF_IDACAQ_TZ1_PGAG1_HI 13
+#define RG_WF_IDACAQ_TZ1_PGAG1_SZ 6
+#define RG_WF_IDACAI_TZ1_PGAG0_MSK 0x003f0000
+#define RG_WF_IDACAI_TZ1_PGAG0_I_MSK 0xffc0ffff
+#define RG_WF_IDACAI_TZ1_PGAG0_SFT 16
+#define RG_WF_IDACAI_TZ1_PGAG0_HI 21
+#define RG_WF_IDACAI_TZ1_PGAG0_SZ 6
+#define RG_WF_IDACAQ_TZ1_PGAG0_MSK 0x3f000000
+#define RG_WF_IDACAQ_TZ1_PGAG0_I_MSK 0xc0ffffff
+#define RG_WF_IDACAQ_TZ1_PGAG0_SFT 24
+#define RG_WF_IDACAQ_TZ1_PGAG0_HI 29
+#define RG_WF_IDACAQ_TZ1_PGAG0_SZ 6
+#define RG_IDACAI_TZ0_COARSE4_MSK 0x0000003f
+#define RG_IDACAI_TZ0_COARSE4_I_MSK 0xffffffc0
+#define RG_IDACAI_TZ0_COARSE4_SFT 0
+#define RG_IDACAI_TZ0_COARSE4_HI 5
+#define RG_IDACAI_TZ0_COARSE4_SZ 6
+#define RG_IDACAQ_TZ0_COARSE4_MSK 0x00003f00
+#define RG_IDACAQ_TZ0_COARSE4_I_MSK 0xffffc0ff
+#define RG_IDACAQ_TZ0_COARSE4_SFT 8
+#define RG_IDACAQ_TZ0_COARSE4_HI 13
+#define RG_IDACAQ_TZ0_COARSE4_SZ 6
+#define RG_IDACAI_TZ0_COARSE3_MSK 0x003f0000
+#define RG_IDACAI_TZ0_COARSE3_I_MSK 0xffc0ffff
+#define RG_IDACAI_TZ0_COARSE3_SFT 16
+#define RG_IDACAI_TZ0_COARSE3_HI 21
+#define RG_IDACAI_TZ0_COARSE3_SZ 6
+#define RG_IDACAQ_TZ0_COARSE3_MSK 0x3f000000
+#define RG_IDACAQ_TZ0_COARSE3_I_MSK 0xc0ffffff
+#define RG_IDACAQ_TZ0_COARSE3_SFT 24
+#define RG_IDACAQ_TZ0_COARSE3_HI 29
+#define RG_IDACAQ_TZ0_COARSE3_SZ 6
+#define RG_IDACAI_TZ0_COARSE2_MSK 0x0000003f
+#define RG_IDACAI_TZ0_COARSE2_I_MSK 0xffffffc0
+#define RG_IDACAI_TZ0_COARSE2_SFT 0
+#define RG_IDACAI_TZ0_COARSE2_HI 5
+#define RG_IDACAI_TZ0_COARSE2_SZ 6
+#define RG_IDACAQ_TZ0_COARSE2_MSK 0x00003f00
+#define RG_IDACAQ_TZ0_COARSE2_I_MSK 0xffffc0ff
+#define RG_IDACAQ_TZ0_COARSE2_SFT 8
+#define RG_IDACAQ_TZ0_COARSE2_HI 13
+#define RG_IDACAQ_TZ0_COARSE2_SZ 6
+#define RG_IDACAI_TZ0_COARSE1_MSK 0x003f0000
+#define RG_IDACAI_TZ0_COARSE1_I_MSK 0xffc0ffff
+#define RG_IDACAI_TZ0_COARSE1_SFT 16
+#define RG_IDACAI_TZ0_COARSE1_HI 21
+#define RG_IDACAI_TZ0_COARSE1_SZ 6
+#define RG_IDACAQ_TZ0_COARSE1_MSK 0x3f000000
+#define RG_IDACAQ_TZ0_COARSE1_I_MSK 0xc0ffffff
+#define RG_IDACAQ_TZ0_COARSE1_SFT 24
+#define RG_IDACAQ_TZ0_COARSE1_HI 29
+#define RG_IDACAQ_TZ0_COARSE1_SZ 6
+#define RG_IDACAI_TZ0_COARSE0_MSK 0x0000003f
+#define RG_IDACAI_TZ0_COARSE0_I_MSK 0xffffffc0
+#define RG_IDACAI_TZ0_COARSE0_SFT 0
+#define RG_IDACAI_TZ0_COARSE0_HI 5
+#define RG_IDACAI_TZ0_COARSE0_SZ 6
+#define RG_IDACAQ_TZ0_COARSE0_MSK 0x00003f00
+#define RG_IDACAQ_TZ0_COARSE0_I_MSK 0xffffc0ff
+#define RG_IDACAQ_TZ0_COARSE0_SFT 8
+#define RG_IDACAQ_TZ0_COARSE0_HI 13
+#define RG_IDACAQ_TZ0_COARSE0_SZ 6
+#define RG_IDACAI_TZ1_COARSE4_MSK 0x003f0000
+#define RG_IDACAI_TZ1_COARSE4_I_MSK 0xffc0ffff
+#define RG_IDACAI_TZ1_COARSE4_SFT 16
+#define RG_IDACAI_TZ1_COARSE4_HI 21
+#define RG_IDACAI_TZ1_COARSE4_SZ 6
+#define RG_IDACAQ_TZ1_COARSE4_MSK 0x3f000000
+#define RG_IDACAQ_TZ1_COARSE4_I_MSK 0xc0ffffff
+#define RG_IDACAQ_TZ1_COARSE4_SFT 24
+#define RG_IDACAQ_TZ1_COARSE4_HI 29
+#define RG_IDACAQ_TZ1_COARSE4_SZ 6
+#define RG_IDACAI_TZ1_COARSE3_MSK 0x0000003f
+#define RG_IDACAI_TZ1_COARSE3_I_MSK 0xffffffc0
+#define RG_IDACAI_TZ1_COARSE3_SFT 0
+#define RG_IDACAI_TZ1_COARSE3_HI 5
+#define RG_IDACAI_TZ1_COARSE3_SZ 6
+#define RG_IDACAQ_TZ1_COARSE3_MSK 0x00003f00
+#define RG_IDACAQ_TZ1_COARSE3_I_MSK 0xffffc0ff
+#define RG_IDACAQ_TZ1_COARSE3_SFT 8
+#define RG_IDACAQ_TZ1_COARSE3_HI 13
+#define RG_IDACAQ_TZ1_COARSE3_SZ 6
+#define RG_IDACAI_TZ1_COARSE2_MSK 0x003f0000
+#define RG_IDACAI_TZ1_COARSE2_I_MSK 0xffc0ffff
+#define RG_IDACAI_TZ1_COARSE2_SFT 16
+#define RG_IDACAI_TZ1_COARSE2_HI 21
+#define RG_IDACAI_TZ1_COARSE2_SZ 6
+#define RG_IDACAQ_TZ1_COARSE2_MSK 0x3f000000
+#define RG_IDACAQ_TZ1_COARSE2_I_MSK 0xc0ffffff
+#define RG_IDACAQ_TZ1_COARSE2_SFT 24
+#define RG_IDACAQ_TZ1_COARSE2_HI 29
+#define RG_IDACAQ_TZ1_COARSE2_SZ 6
+#define RG_IDACAI_TZ1_COARSE1_MSK 0x0000003f
+#define RG_IDACAI_TZ1_COARSE1_I_MSK 0xffffffc0
+#define RG_IDACAI_TZ1_COARSE1_SFT 0
+#define RG_IDACAI_TZ1_COARSE1_HI 5
+#define RG_IDACAI_TZ1_COARSE1_SZ 6
+#define RG_IDACAQ_TZ1_COARSE1_MSK 0x00003f00
+#define RG_IDACAQ_TZ1_COARSE1_I_MSK 0xffffc0ff
+#define RG_IDACAQ_TZ1_COARSE1_SFT 8
+#define RG_IDACAQ_TZ1_COARSE1_HI 13
+#define RG_IDACAQ_TZ1_COARSE1_SZ 6
+#define RG_IDACAI_TZ1_COARSE0_MSK 0x003f0000
+#define RG_IDACAI_TZ1_COARSE0_I_MSK 0xffc0ffff
+#define RG_IDACAI_TZ1_COARSE0_SFT 16
+#define RG_IDACAI_TZ1_COARSE0_HI 21
+#define RG_IDACAI_TZ1_COARSE0_SZ 6
+#define RG_IDACAQ_TZ1_COARSE0_MSK 0x3f000000
+#define RG_IDACAQ_TZ1_COARSE0_I_MSK 0xc0ffffff
+#define RG_IDACAQ_TZ1_COARSE0_SFT 24
+#define RG_IDACAQ_TZ1_COARSE0_HI 29
+#define RG_IDACAQ_TZ1_COARSE0_SZ 6
+#define RG_BT_IDACAI_TZ0_PGAG15_MSK 0x0000003f
+#define RG_BT_IDACAI_TZ0_PGAG15_I_MSK 0xffffffc0
+#define RG_BT_IDACAI_TZ0_PGAG15_SFT 0
+#define RG_BT_IDACAI_TZ0_PGAG15_HI 5
+#define RG_BT_IDACAI_TZ0_PGAG15_SZ 6
+#define RG_BT_IDACAQ_TZ0_PGAG15_MSK 0x00003f00
+#define RG_BT_IDACAQ_TZ0_PGAG15_I_MSK 0xffffc0ff
+#define RG_BT_IDACAQ_TZ0_PGAG15_SFT 8
+#define RG_BT_IDACAQ_TZ0_PGAG15_HI 13
+#define RG_BT_IDACAQ_TZ0_PGAG15_SZ 6
+#define RG_BT_IDACAI_TZ0_PGAG14_MSK 0x003f0000
+#define RG_BT_IDACAI_TZ0_PGAG14_I_MSK 0xffc0ffff
+#define RG_BT_IDACAI_TZ0_PGAG14_SFT 16
+#define RG_BT_IDACAI_TZ0_PGAG14_HI 21
+#define RG_BT_IDACAI_TZ0_PGAG14_SZ 6
+#define RG_BT_IDACAQ_TZ0_PGAG14_MSK 0x3f000000
+#define RG_BT_IDACAQ_TZ0_PGAG14_I_MSK 0xc0ffffff
+#define RG_BT_IDACAQ_TZ0_PGAG14_SFT 24
+#define RG_BT_IDACAQ_TZ0_PGAG14_HI 29
+#define RG_BT_IDACAQ_TZ0_PGAG14_SZ 6
+#define RG_BT_IDACAI_TZ0_PGAG13_MSK 0x0000003f
+#define RG_BT_IDACAI_TZ0_PGAG13_I_MSK 0xffffffc0
+#define RG_BT_IDACAI_TZ0_PGAG13_SFT 0
+#define RG_BT_IDACAI_TZ0_PGAG13_HI 5
+#define RG_BT_IDACAI_TZ0_PGAG13_SZ 6
+#define RG_BT_IDACAQ_TZ0_PGAG13_MSK 0x00003f00
+#define RG_BT_IDACAQ_TZ0_PGAG13_I_MSK 0xffffc0ff
+#define RG_BT_IDACAQ_TZ0_PGAG13_SFT 8
+#define RG_BT_IDACAQ_TZ0_PGAG13_HI 13
+#define RG_BT_IDACAQ_TZ0_PGAG13_SZ 6
+#define RG_BT_IDACAI_TZ0_PGAG12_MSK 0x003f0000
+#define RG_BT_IDACAI_TZ0_PGAG12_I_MSK 0xffc0ffff
+#define RG_BT_IDACAI_TZ0_PGAG12_SFT 16
+#define RG_BT_IDACAI_TZ0_PGAG12_HI 21
+#define RG_BT_IDACAI_TZ0_PGAG12_SZ 6
+#define RG_BT_IDACAQ_TZ0_PGAG12_MSK 0x3f000000
+#define RG_BT_IDACAQ_TZ0_PGAG12_I_MSK 0xc0ffffff
+#define RG_BT_IDACAQ_TZ0_PGAG12_SFT 24
+#define RG_BT_IDACAQ_TZ0_PGAG12_HI 29
+#define RG_BT_IDACAQ_TZ0_PGAG12_SZ 6
+#define RG_BT_IDACAI_TZ0_PGAG11_MSK 0x0000003f
+#define RG_BT_IDACAI_TZ0_PGAG11_I_MSK 0xffffffc0
+#define RG_BT_IDACAI_TZ0_PGAG11_SFT 0
+#define RG_BT_IDACAI_TZ0_PGAG11_HI 5
+#define RG_BT_IDACAI_TZ0_PGAG11_SZ 6
+#define RG_BT_IDACAQ_TZ0_PGAG11_MSK 0x00003f00
+#define RG_BT_IDACAQ_TZ0_PGAG11_I_MSK 0xffffc0ff
+#define RG_BT_IDACAQ_TZ0_PGAG11_SFT 8
+#define RG_BT_IDACAQ_TZ0_PGAG11_HI 13
+#define RG_BT_IDACAQ_TZ0_PGAG11_SZ 6
+#define RG_BT_IDACAI_TZ0_PGAG10_MSK 0x003f0000
+#define RG_BT_IDACAI_TZ0_PGAG10_I_MSK 0xffc0ffff
+#define RG_BT_IDACAI_TZ0_PGAG10_SFT 16
+#define RG_BT_IDACAI_TZ0_PGAG10_HI 21
+#define RG_BT_IDACAI_TZ0_PGAG10_SZ 6
+#define RG_BT_IDACAQ_TZ0_PGAG10_MSK 0x3f000000
+#define RG_BT_IDACAQ_TZ0_PGAG10_I_MSK 0xc0ffffff
+#define RG_BT_IDACAQ_TZ0_PGAG10_SFT 24
+#define RG_BT_IDACAQ_TZ0_PGAG10_HI 29
+#define RG_BT_IDACAQ_TZ0_PGAG10_SZ 6
+#define RG_BT_IDACAI_TZ0_PGAG9_MSK 0x0000003f
+#define RG_BT_IDACAI_TZ0_PGAG9_I_MSK 0xffffffc0
+#define RG_BT_IDACAI_TZ0_PGAG9_SFT 0
+#define RG_BT_IDACAI_TZ0_PGAG9_HI 5
+#define RG_BT_IDACAI_TZ0_PGAG9_SZ 6
+#define RG_BT_IDACAQ_TZ0_PGAG9_MSK 0x00003f00
+#define RG_BT_IDACAQ_TZ0_PGAG9_I_MSK 0xffffc0ff
+#define RG_BT_IDACAQ_TZ0_PGAG9_SFT 8
+#define RG_BT_IDACAQ_TZ0_PGAG9_HI 13
+#define RG_BT_IDACAQ_TZ0_PGAG9_SZ 6
+#define RG_BT_IDACAI_TZ0_PGAG8_MSK 0x003f0000
+#define RG_BT_IDACAI_TZ0_PGAG8_I_MSK 0xffc0ffff
+#define RG_BT_IDACAI_TZ0_PGAG8_SFT 16
+#define RG_BT_IDACAI_TZ0_PGAG8_HI 21
+#define RG_BT_IDACAI_TZ0_PGAG8_SZ 6
+#define RG_BT_IDACAQ_TZ0_PGAG8_MSK 0x3f000000
+#define RG_BT_IDACAQ_TZ0_PGAG8_I_MSK 0xc0ffffff
+#define RG_BT_IDACAQ_TZ0_PGAG8_SFT 24
+#define RG_BT_IDACAQ_TZ0_PGAG8_HI 29
+#define RG_BT_IDACAQ_TZ0_PGAG8_SZ 6
+#define RG_BT_IDACAI_TZ0_PGAG7_MSK 0x0000003f
+#define RG_BT_IDACAI_TZ0_PGAG7_I_MSK 0xffffffc0
+#define RG_BT_IDACAI_TZ0_PGAG7_SFT 0
+#define RG_BT_IDACAI_TZ0_PGAG7_HI 5
+#define RG_BT_IDACAI_TZ0_PGAG7_SZ 6
+#define RG_BT_IDACAQ_TZ0_PGAG7_MSK 0x00003f00
+#define RG_BT_IDACAQ_TZ0_PGAG7_I_MSK 0xffffc0ff
+#define RG_BT_IDACAQ_TZ0_PGAG7_SFT 8
+#define RG_BT_IDACAQ_TZ0_PGAG7_HI 13
+#define RG_BT_IDACAQ_TZ0_PGAG7_SZ 6
+#define RG_BT_IDACAI_TZ0_PGAG6_MSK 0x003f0000
+#define RG_BT_IDACAI_TZ0_PGAG6_I_MSK 0xffc0ffff
+#define RG_BT_IDACAI_TZ0_PGAG6_SFT 16
+#define RG_BT_IDACAI_TZ0_PGAG6_HI 21
+#define RG_BT_IDACAI_TZ0_PGAG6_SZ 6
+#define RG_BT_IDACAQ_TZ0_PGAG6_MSK 0x3f000000
+#define RG_BT_IDACAQ_TZ0_PGAG6_I_MSK 0xc0ffffff
+#define RG_BT_IDACAQ_TZ0_PGAG6_SFT 24
+#define RG_BT_IDACAQ_TZ0_PGAG6_HI 29
+#define RG_BT_IDACAQ_TZ0_PGAG6_SZ 6
+#define RG_BT_IDACAI_TZ0_PGAG5_MSK 0x0000003f
+#define RG_BT_IDACAI_TZ0_PGAG5_I_MSK 0xffffffc0
+#define RG_BT_IDACAI_TZ0_PGAG5_SFT 0
+#define RG_BT_IDACAI_TZ0_PGAG5_HI 5
+#define RG_BT_IDACAI_TZ0_PGAG5_SZ 6
+#define RG_BT_IDACAQ_TZ0_PGAG5_MSK 0x00003f00
+#define RG_BT_IDACAQ_TZ0_PGAG5_I_MSK 0xffffc0ff
+#define RG_BT_IDACAQ_TZ0_PGAG5_SFT 8
+#define RG_BT_IDACAQ_TZ0_PGAG5_HI 13
+#define RG_BT_IDACAQ_TZ0_PGAG5_SZ 6
+#define RG_BT_IDACAI_TZ0_PGAG4_MSK 0x003f0000
+#define RG_BT_IDACAI_TZ0_PGAG4_I_MSK 0xffc0ffff
+#define RG_BT_IDACAI_TZ0_PGAG4_SFT 16
+#define RG_BT_IDACAI_TZ0_PGAG4_HI 21
+#define RG_BT_IDACAI_TZ0_PGAG4_SZ 6
+#define RG_BT_IDACAQ_TZ0_PGAG4_MSK 0x3f000000
+#define RG_BT_IDACAQ_TZ0_PGAG4_I_MSK 0xc0ffffff
+#define RG_BT_IDACAQ_TZ0_PGAG4_SFT 24
+#define RG_BT_IDACAQ_TZ0_PGAG4_HI 29
+#define RG_BT_IDACAQ_TZ0_PGAG4_SZ 6
+#define RG_BT_IDACAI_TZ0_PGAG3_MSK 0x0000003f
+#define RG_BT_IDACAI_TZ0_PGAG3_I_MSK 0xffffffc0
+#define RG_BT_IDACAI_TZ0_PGAG3_SFT 0
+#define RG_BT_IDACAI_TZ0_PGAG3_HI 5
+#define RG_BT_IDACAI_TZ0_PGAG3_SZ 6
+#define RG_BT_IDACAQ_TZ0_PGAG3_MSK 0x00003f00
+#define RG_BT_IDACAQ_TZ0_PGAG3_I_MSK 0xffffc0ff
+#define RG_BT_IDACAQ_TZ0_PGAG3_SFT 8
+#define RG_BT_IDACAQ_TZ0_PGAG3_HI 13
+#define RG_BT_IDACAQ_TZ0_PGAG3_SZ 6
+#define RG_BT_IDACAI_TZ0_PGAG2_MSK 0x003f0000
+#define RG_BT_IDACAI_TZ0_PGAG2_I_MSK 0xffc0ffff
+#define RG_BT_IDACAI_TZ0_PGAG2_SFT 16
+#define RG_BT_IDACAI_TZ0_PGAG2_HI 21
+#define RG_BT_IDACAI_TZ0_PGAG2_SZ 6
+#define RG_BT_IDACAQ_TZ0_PGAG2_MSK 0x3f000000
+#define RG_BT_IDACAQ_TZ0_PGAG2_I_MSK 0xc0ffffff
+#define RG_BT_IDACAQ_TZ0_PGAG2_SFT 24
+#define RG_BT_IDACAQ_TZ0_PGAG2_HI 29
+#define RG_BT_IDACAQ_TZ0_PGAG2_SZ 6
+#define RG_BT_IDACAI_TZ0_PGAG1_MSK 0x0000003f
+#define RG_BT_IDACAI_TZ0_PGAG1_I_MSK 0xffffffc0
+#define RG_BT_IDACAI_TZ0_PGAG1_SFT 0
+#define RG_BT_IDACAI_TZ0_PGAG1_HI 5
+#define RG_BT_IDACAI_TZ0_PGAG1_SZ 6
+#define RG_BT_IDACAQ_TZ0_PGAG1_MSK 0x00003f00
+#define RG_BT_IDACAQ_TZ0_PGAG1_I_MSK 0xffffc0ff
+#define RG_BT_IDACAQ_TZ0_PGAG1_SFT 8
+#define RG_BT_IDACAQ_TZ0_PGAG1_HI 13
+#define RG_BT_IDACAQ_TZ0_PGAG1_SZ 6
+#define RG_BT_IDACAI_TZ0_PGAG0_MSK 0x003f0000
+#define RG_BT_IDACAI_TZ0_PGAG0_I_MSK 0xffc0ffff
+#define RG_BT_IDACAI_TZ0_PGAG0_SFT 16
+#define RG_BT_IDACAI_TZ0_PGAG0_HI 21
+#define RG_BT_IDACAI_TZ0_PGAG0_SZ 6
+#define RG_BT_IDACAQ_TZ0_PGAG0_MSK 0x3f000000
+#define RG_BT_IDACAQ_TZ0_PGAG0_I_MSK 0xc0ffffff
+#define RG_BT_IDACAQ_TZ0_PGAG0_SFT 24
+#define RG_BT_IDACAQ_TZ0_PGAG0_HI 29
+#define RG_BT_IDACAQ_TZ0_PGAG0_SZ 6
+#define RG_BT_IDACAI_TZ1_PGAG15_MSK 0x0000003f
+#define RG_BT_IDACAI_TZ1_PGAG15_I_MSK 0xffffffc0
+#define RG_BT_IDACAI_TZ1_PGAG15_SFT 0
+#define RG_BT_IDACAI_TZ1_PGAG15_HI 5
+#define RG_BT_IDACAI_TZ1_PGAG15_SZ 6
+#define RG_BT_IDACAQ_TZ1_PGAG15_MSK 0x00003f00
+#define RG_BT_IDACAQ_TZ1_PGAG15_I_MSK 0xffffc0ff
+#define RG_BT_IDACAQ_TZ1_PGAG15_SFT 8
+#define RG_BT_IDACAQ_TZ1_PGAG15_HI 13
+#define RG_BT_IDACAQ_TZ1_PGAG15_SZ 6
+#define RG_BT_IDACAI_TZ1_PGAG14_MSK 0x003f0000
+#define RG_BT_IDACAI_TZ1_PGAG14_I_MSK 0xffc0ffff
+#define RG_BT_IDACAI_TZ1_PGAG14_SFT 16
+#define RG_BT_IDACAI_TZ1_PGAG14_HI 21
+#define RG_BT_IDACAI_TZ1_PGAG14_SZ 6
+#define RG_BT_IDACAQ_TZ1_PGAG14_MSK 0x3f000000
+#define RG_BT_IDACAQ_TZ1_PGAG14_I_MSK 0xc0ffffff
+#define RG_BT_IDACAQ_TZ1_PGAG14_SFT 24
+#define RG_BT_IDACAQ_TZ1_PGAG14_HI 29
+#define RG_BT_IDACAQ_TZ1_PGAG14_SZ 6
+#define RG_BT_IDACAI_TZ1_PGAG13_MSK 0x0000003f
+#define RG_BT_IDACAI_TZ1_PGAG13_I_MSK 0xffffffc0
+#define RG_BT_IDACAI_TZ1_PGAG13_SFT 0
+#define RG_BT_IDACAI_TZ1_PGAG13_HI 5
+#define RG_BT_IDACAI_TZ1_PGAG13_SZ 6
+#define RG_BT_IDACAQ_TZ1_PGAG13_MSK 0x00003f00
+#define RG_BT_IDACAQ_TZ1_PGAG13_I_MSK 0xffffc0ff
+#define RG_BT_IDACAQ_TZ1_PGAG13_SFT 8
+#define RG_BT_IDACAQ_TZ1_PGAG13_HI 13
+#define RG_BT_IDACAQ_TZ1_PGAG13_SZ 6
+#define RG_BT_IDACAI_TZ1_PGAG12_MSK 0x003f0000
+#define RG_BT_IDACAI_TZ1_PGAG12_I_MSK 0xffc0ffff
+#define RG_BT_IDACAI_TZ1_PGAG12_SFT 16
+#define RG_BT_IDACAI_TZ1_PGAG12_HI 21
+#define RG_BT_IDACAI_TZ1_PGAG12_SZ 6
+#define RG_BT_IDACAQ_TZ1_PGAG12_MSK 0x3f000000
+#define RG_BT_IDACAQ_TZ1_PGAG12_I_MSK 0xc0ffffff
+#define RG_BT_IDACAQ_TZ1_PGAG12_SFT 24
+#define RG_BT_IDACAQ_TZ1_PGAG12_HI 29
+#define RG_BT_IDACAQ_TZ1_PGAG12_SZ 6
+#define RG_BT_IDACAI_TZ1_PGAG11_MSK 0x0000003f
+#define RG_BT_IDACAI_TZ1_PGAG11_I_MSK 0xffffffc0
+#define RG_BT_IDACAI_TZ1_PGAG11_SFT 0
+#define RG_BT_IDACAI_TZ1_PGAG11_HI 5
+#define RG_BT_IDACAI_TZ1_PGAG11_SZ 6
+#define RG_BT_IDACAQ_TZ1_PGAG11_MSK 0x00003f00
+#define RG_BT_IDACAQ_TZ1_PGAG11_I_MSK 0xffffc0ff
+#define RG_BT_IDACAQ_TZ1_PGAG11_SFT 8
+#define RG_BT_IDACAQ_TZ1_PGAG11_HI 13
+#define RG_BT_IDACAQ_TZ1_PGAG11_SZ 6
+#define RG_BT_IDACAI_TZ1_PGAG10_MSK 0x003f0000
+#define RG_BT_IDACAI_TZ1_PGAG10_I_MSK 0xffc0ffff
+#define RG_BT_IDACAI_TZ1_PGAG10_SFT 16
+#define RG_BT_IDACAI_TZ1_PGAG10_HI 21
+#define RG_BT_IDACAI_TZ1_PGAG10_SZ 6
+#define RG_BT_IDACAQ_TZ1_PGAG10_MSK 0x3f000000
+#define RG_BT_IDACAQ_TZ1_PGAG10_I_MSK 0xc0ffffff
+#define RG_BT_IDACAQ_TZ1_PGAG10_SFT 24
+#define RG_BT_IDACAQ_TZ1_PGAG10_HI 29
+#define RG_BT_IDACAQ_TZ1_PGAG10_SZ 6
+#define RG_BT_IDACAI_TZ1_PGAG9_MSK 0x0000003f
+#define RG_BT_IDACAI_TZ1_PGAG9_I_MSK 0xffffffc0
+#define RG_BT_IDACAI_TZ1_PGAG9_SFT 0
+#define RG_BT_IDACAI_TZ1_PGAG9_HI 5
+#define RG_BT_IDACAI_TZ1_PGAG9_SZ 6
+#define RG_BT_IDACAQ_TZ1_PGAG9_MSK 0x00003f00
+#define RG_BT_IDACAQ_TZ1_PGAG9_I_MSK 0xffffc0ff
+#define RG_BT_IDACAQ_TZ1_PGAG9_SFT 8
+#define RG_BT_IDACAQ_TZ1_PGAG9_HI 13
+#define RG_BT_IDACAQ_TZ1_PGAG9_SZ 6
+#define RG_BT_IDACAI_TZ1_PGAG8_MSK 0x003f0000
+#define RG_BT_IDACAI_TZ1_PGAG8_I_MSK 0xffc0ffff
+#define RG_BT_IDACAI_TZ1_PGAG8_SFT 16
+#define RG_BT_IDACAI_TZ1_PGAG8_HI 21
+#define RG_BT_IDACAI_TZ1_PGAG8_SZ 6
+#define RG_BT_IDACAQ_TZ1_PGAG8_MSK 0x3f000000
+#define RG_BT_IDACAQ_TZ1_PGAG8_I_MSK 0xc0ffffff
+#define RG_BT_IDACAQ_TZ1_PGAG8_SFT 24
+#define RG_BT_IDACAQ_TZ1_PGAG8_HI 29
+#define RG_BT_IDACAQ_TZ1_PGAG8_SZ 6
+#define RG_BT_IDACAI_TZ1_PGAG7_MSK 0x0000003f
+#define RG_BT_IDACAI_TZ1_PGAG7_I_MSK 0xffffffc0
+#define RG_BT_IDACAI_TZ1_PGAG7_SFT 0
+#define RG_BT_IDACAI_TZ1_PGAG7_HI 5
+#define RG_BT_IDACAI_TZ1_PGAG7_SZ 6
+#define RG_BT_IDACAQ_TZ1_PGAG7_MSK 0x00003f00
+#define RG_BT_IDACAQ_TZ1_PGAG7_I_MSK 0xffffc0ff
+#define RG_BT_IDACAQ_TZ1_PGAG7_SFT 8
+#define RG_BT_IDACAQ_TZ1_PGAG7_HI 13
+#define RG_BT_IDACAQ_TZ1_PGAG7_SZ 6
+#define RG_BT_IDACAI_TZ1_PGAG6_MSK 0x003f0000
+#define RG_BT_IDACAI_TZ1_PGAG6_I_MSK 0xffc0ffff
+#define RG_BT_IDACAI_TZ1_PGAG6_SFT 16
+#define RG_BT_IDACAI_TZ1_PGAG6_HI 21
+#define RG_BT_IDACAI_TZ1_PGAG6_SZ 6
+#define RG_BT_IDACAQ_TZ1_PGAG6_MSK 0x3f000000
+#define RG_BT_IDACAQ_TZ1_PGAG6_I_MSK 0xc0ffffff
+#define RG_BT_IDACAQ_TZ1_PGAG6_SFT 24
+#define RG_BT_IDACAQ_TZ1_PGAG6_HI 29
+#define RG_BT_IDACAQ_TZ1_PGAG6_SZ 6
+#define RG_BT_IDACAI_TZ1_PGAG5_MSK 0x0000003f
+#define RG_BT_IDACAI_TZ1_PGAG5_I_MSK 0xffffffc0
+#define RG_BT_IDACAI_TZ1_PGAG5_SFT 0
+#define RG_BT_IDACAI_TZ1_PGAG5_HI 5
+#define RG_BT_IDACAI_TZ1_PGAG5_SZ 6
+#define RG_BT_IDACAQ_TZ1_PGAG5_MSK 0x00003f00
+#define RG_BT_IDACAQ_TZ1_PGAG5_I_MSK 0xffffc0ff
+#define RG_BT_IDACAQ_TZ1_PGAG5_SFT 8
+#define RG_BT_IDACAQ_TZ1_PGAG5_HI 13
+#define RG_BT_IDACAQ_TZ1_PGAG5_SZ 6
+#define RG_BT_IDACAI_TZ1_PGAG4_MSK 0x003f0000
+#define RG_BT_IDACAI_TZ1_PGAG4_I_MSK 0xffc0ffff
+#define RG_BT_IDACAI_TZ1_PGAG4_SFT 16
+#define RG_BT_IDACAI_TZ1_PGAG4_HI 21
+#define RG_BT_IDACAI_TZ1_PGAG4_SZ 6
+#define RG_BT_IDACAQ_TZ1_PGAG4_MSK 0x3f000000
+#define RG_BT_IDACAQ_TZ1_PGAG4_I_MSK 0xc0ffffff
+#define RG_BT_IDACAQ_TZ1_PGAG4_SFT 24
+#define RG_BT_IDACAQ_TZ1_PGAG4_HI 29
+#define RG_BT_IDACAQ_TZ1_PGAG4_SZ 6
+#define RG_BT_IDACAI_TZ1_PGAG3_MSK 0x0000003f
+#define RG_BT_IDACAI_TZ1_PGAG3_I_MSK 0xffffffc0
+#define RG_BT_IDACAI_TZ1_PGAG3_SFT 0
+#define RG_BT_IDACAI_TZ1_PGAG3_HI 5
+#define RG_BT_IDACAI_TZ1_PGAG3_SZ 6
+#define RG_BT_IDACAQ_TZ1_PGAG3_MSK 0x00003f00
+#define RG_BT_IDACAQ_TZ1_PGAG3_I_MSK 0xffffc0ff
+#define RG_BT_IDACAQ_TZ1_PGAG3_SFT 8
+#define RG_BT_IDACAQ_TZ1_PGAG3_HI 13
+#define RG_BT_IDACAQ_TZ1_PGAG3_SZ 6
+#define RG_BT_IDACAI_TZ1_PGAG2_MSK 0x003f0000
+#define RG_BT_IDACAI_TZ1_PGAG2_I_MSK 0xffc0ffff
+#define RG_BT_IDACAI_TZ1_PGAG2_SFT 16
+#define RG_BT_IDACAI_TZ1_PGAG2_HI 21
+#define RG_BT_IDACAI_TZ1_PGAG2_SZ 6
+#define RG_BT_IDACAQ_TZ1_PGAG2_MSK 0x3f000000
+#define RG_BT_IDACAQ_TZ1_PGAG2_I_MSK 0xc0ffffff
+#define RG_BT_IDACAQ_TZ1_PGAG2_SFT 24
+#define RG_BT_IDACAQ_TZ1_PGAG2_HI 29
+#define RG_BT_IDACAQ_TZ1_PGAG2_SZ 6
+#define RG_BT_IDACAI_TZ1_PGAG1_MSK 0x0000003f
+#define RG_BT_IDACAI_TZ1_PGAG1_I_MSK 0xffffffc0
+#define RG_BT_IDACAI_TZ1_PGAG1_SFT 0
+#define RG_BT_IDACAI_TZ1_PGAG1_HI 5
+#define RG_BT_IDACAI_TZ1_PGAG1_SZ 6
+#define RG_BT_IDACAQ_TZ1_PGAG1_MSK 0x00003f00
+#define RG_BT_IDACAQ_TZ1_PGAG1_I_MSK 0xffffc0ff
+#define RG_BT_IDACAQ_TZ1_PGAG1_SFT 8
+#define RG_BT_IDACAQ_TZ1_PGAG1_HI 13
+#define RG_BT_IDACAQ_TZ1_PGAG1_SZ 6
+#define RG_BT_IDACAI_TZ1_PGAG0_MSK 0x003f0000
+#define RG_BT_IDACAI_TZ1_PGAG0_I_MSK 0xffc0ffff
+#define RG_BT_IDACAI_TZ1_PGAG0_SFT 16
+#define RG_BT_IDACAI_TZ1_PGAG0_HI 21
+#define RG_BT_IDACAI_TZ1_PGAG0_SZ 6
+#define RG_BT_IDACAQ_TZ1_PGAG0_MSK 0x3f000000
+#define RG_BT_IDACAQ_TZ1_PGAG0_I_MSK 0xc0ffffff
+#define RG_BT_IDACAQ_TZ1_PGAG0_SFT 24
+#define RG_BT_IDACAQ_TZ1_PGAG0_HI 29
+#define RG_BT_IDACAQ_TZ1_PGAG0_SZ 6
+#define RG_SX_DELAY_MSK 0x0000000f
+#define RG_SX_DELAY_I_MSK 0xfffffff0
+#define RG_SX_DELAY_SFT 0
+#define RG_SX_DELAY_HI 3
+#define RG_SX_DELAY_SZ 4
+#define RG_TXDAC_DELAY_MSK 0x000000f0
+#define RG_TXDAC_DELAY_I_MSK 0xffffff0f
+#define RG_TXDAC_DELAY_SFT 4
+#define RG_TXDAC_DELAY_HI 7
+#define RG_TXDAC_DELAY_SZ 4
+#define RG_TXRF_DELAY_MSK 0x00000f00
+#define RG_TXRF_DELAY_I_MSK 0xfffff0ff
+#define RG_TXRF_DELAY_SFT 8
+#define RG_TXRF_DELAY_HI 11
+#define RG_TXRF_DELAY_SZ 4
+#define RG_TXPA_DELAY_MSK 0x0000f000
+#define RG_TXPA_DELAY_I_MSK 0xffff0fff
+#define RG_TXPA_DELAY_SFT 12
+#define RG_TXPA_DELAY_HI 15
+#define RG_TXPA_DELAY_SZ 4
+#define RG_RXRF_DELAY_MSK 0x000f0000
+#define RG_RXRF_DELAY_I_MSK 0xfff0ffff
+#define RG_RXRF_DELAY_SFT 16
+#define RG_RXRF_DELAY_HI 19
+#define RG_RXRF_DELAY_SZ 4
+#define RG_TXBTPA_DELAY_MSK 0x00f00000
+#define RG_TXBTPA_DELAY_I_MSK 0xff0fffff
+#define RG_TXBTPA_DELAY_SFT 20
+#define RG_TXBTPA_DELAY_HI 23
+#define RG_TXBTPA_DELAY_SZ 4
+#define RG_TXDAC_T2R_DELAY_MSK 0x0000001f
+#define RG_TXDAC_T2R_DELAY_I_MSK 0xffffffe0
+#define RG_TXDAC_T2R_DELAY_SFT 0
+#define RG_TXDAC_T2R_DELAY_HI 4
+#define RG_TXDAC_T2R_DELAY_SZ 5
+#define RG_TXRF_T2R_DELAY_MSK 0x00001f00
+#define RG_TXRF_T2R_DELAY_I_MSK 0xffffe0ff
+#define RG_TXRF_T2R_DELAY_SFT 8
+#define RG_TXRF_T2R_DELAY_HI 12
+#define RG_TXRF_T2R_DELAY_SZ 5
+#define RG_TXPA_T2R_DELAY_MSK 0x001f0000
+#define RG_TXPA_T2R_DELAY_I_MSK 0xffe0ffff
+#define RG_TXPA_T2R_DELAY_SFT 16
+#define RG_TXPA_T2R_DELAY_HI 20
+#define RG_TXPA_T2R_DELAY_SZ 5
+#define RG_RXRF_T2R_DELAY_MSK 0x1f000000
+#define RG_RXRF_T2R_DELAY_I_MSK 0xe0ffffff
+#define RG_RXRF_T2R_DELAY_SFT 24
+#define RG_RXRF_T2R_DELAY_HI 28
+#define RG_RXRF_T2R_DELAY_SZ 5
+#define RG_TXDAC_R2T_DELAY_MSK 0x0000001f
+#define RG_TXDAC_R2T_DELAY_I_MSK 0xffffffe0
+#define RG_TXDAC_R2T_DELAY_SFT 0
+#define RG_TXDAC_R2T_DELAY_HI 4
+#define RG_TXDAC_R2T_DELAY_SZ 5
+#define RG_TXRF_R2T_DELAY_MSK 0x00001f00
+#define RG_TXRF_R2T_DELAY_I_MSK 0xffffe0ff
+#define RG_TXRF_R2T_DELAY_SFT 8
+#define RG_TXRF_R2T_DELAY_HI 12
+#define RG_TXRF_R2T_DELAY_SZ 5
+#define RG_TXPA_R2T_DELAY_MSK 0x001f0000
+#define RG_TXPA_R2T_DELAY_I_MSK 0xffe0ffff
+#define RG_TXPA_R2T_DELAY_SFT 16
+#define RG_TXPA_R2T_DELAY_HI 20
+#define RG_TXPA_R2T_DELAY_SZ 5
+#define RG_RXRF_R2T_DELAY_MSK 0x1f000000
+#define RG_RXRF_R2T_DELAY_I_MSK 0xe0ffffff
+#define RG_RXRF_R2T_DELAY_SFT 24
+#define RG_RXRF_R2T_DELAY_HI 28
+#define RG_RXRF_R2T_DELAY_SZ 5
+#define RG_WF_RX_DCCAL_DELAY_MSK 0x00000007
+#define RG_WF_RX_DCCAL_DELAY_I_MSK 0xfffffff8
+#define RG_WF_RX_DCCAL_DELAY_SFT 0
+#define RG_WF_RX_DCCAL_DELAY_HI 2
+#define RG_WF_RX_DCCAL_DELAY_SZ 3
+#define RG_BT_RX_DCCAL_DELAY_MSK 0x00000070
+#define RG_BT_RX_DCCAL_DELAY_I_MSK 0xffffff8f
+#define RG_BT_RX_DCCAL_DELAY_SFT 4
+#define RG_BT_RX_DCCAL_DELAY_HI 6
+#define RG_BT_RX_DCCAL_DELAY_SZ 3
+#define RG_RX_RCCAL_DELAY_MSK 0x00000700
+#define RG_RX_RCCAL_DELAY_I_MSK 0xfffff8ff
+#define RG_RX_RCCAL_DELAY_SFT 8
+#define RG_RX_RCCAL_DELAY_HI 10
+#define RG_RX_RCCAL_DELAY_SZ 3
+#define RG_TX_DCCAL_DELAY_MSK 0x00007000
+#define RG_TX_DCCAL_DELAY_I_MSK 0xffff8fff
+#define RG_TX_DCCAL_DELAY_SFT 12
+#define RG_TX_DCCAL_DELAY_HI 14
+#define RG_TX_DCCAL_DELAY_SZ 3
+#define RG_TX_IQCAL_DELAY_MSK 0x00070000
+#define RG_TX_IQCAL_DELAY_I_MSK 0xfff8ffff
+#define RG_TX_IQCAL_DELAY_SFT 16
+#define RG_TX_IQCAL_DELAY_HI 18
+#define RG_TX_IQCAL_DELAY_SZ 3
+#define RG_RX_IQCAL_DELAY_MSK 0x00700000
+#define RG_RX_IQCAL_DELAY_I_MSK 0xff8fffff
+#define RG_RX_IQCAL_DELAY_SFT 20
+#define RG_RX_IQCAL_DELAY_HI 22
+#define RG_RX_IQCAL_DELAY_SZ 3
+#define RG_RX_N_RCCAL_DELAY_MSK 0x07000000
+#define RG_RX_N_RCCAL_DELAY_I_MSK 0xf8ffffff
+#define RG_RX_N_RCCAL_DELAY_SFT 24
+#define RG_RX_N_RCCAL_DELAY_HI 26
+#define RG_RX_N_RCCAL_DELAY_SZ 3
+#define RG_PGAG_RCCAL_MSK 0x0000000f
+#define RG_PGAG_RCCAL_I_MSK 0xfffffff0
+#define RG_PGAG_RCCAL_SFT 0
+#define RG_PGAG_RCCAL_HI 3
+#define RG_PGAG_RCCAL_SZ 4
+#define RG_PGAG_TXCAL_MSK 0x000000f0
+#define RG_PGAG_TXCAL_I_MSK 0xffffff0f
+#define RG_PGAG_TXCAL_SFT 4
+#define RG_PGAG_TXCAL_HI 7
+#define RG_PGAG_TXCAL_SZ 4
+#define RG_TX_GAIN_TXCAL_MSK 0x00007f00
+#define RG_TX_GAIN_TXCAL_I_MSK 0xffff80ff
+#define RG_TX_GAIN_TXCAL_SFT 8
+#define RG_TX_GAIN_TXCAL_HI 14
+#define RG_TX_GAIN_TXCAL_SZ 7
+#define RG_RFG_RXIQCAL_MSK 0x00030000
+#define RG_RFG_RXIQCAL_I_MSK 0xfffcffff
+#define RG_RFG_RXIQCAL_SFT 16
+#define RG_RFG_RXIQCAL_HI 17
+#define RG_RFG_RXIQCAL_SZ 2
+#define RG_PGAG_RXIQCAL_MSK 0x003c0000
+#define RG_PGAG_RXIQCAL_I_MSK 0xffc3ffff
+#define RG_PGAG_RXIQCAL_SFT 18
+#define RG_PGAG_RXIQCAL_HI 21
+#define RG_PGAG_RXIQCAL_SZ 4
+#define RG_TX_GAIN_RXIQCAL_MSK 0x1fc00000
+#define RG_TX_GAIN_RXIQCAL_I_MSK 0xe03fffff
+#define RG_TX_GAIN_RXIQCAL_SFT 22
+#define RG_TX_GAIN_RXIQCAL_HI 28
+#define RG_TX_GAIN_RXIQCAL_SZ 7
+#define RG_RFG_DPDCAL_MSK 0x00000003
+#define RG_RFG_DPDCAL_I_MSK 0xfffffffc
+#define RG_RFG_DPDCAL_SFT 0
+#define RG_RFG_DPDCAL_HI 1
+#define RG_RFG_DPDCAL_SZ 2
+#define RG_PGAG_DPDCAL_MSK 0x0000003c
+#define RG_PGAG_DPDCAL_I_MSK 0xffffffc3
+#define RG_PGAG_DPDCAL_SFT 2
+#define RG_PGAG_DPDCAL_HI 5
+#define RG_PGAG_DPDCAL_SZ 4
+#define RG_TX_GAIN_DPDCAL_MSK 0x00001fc0
+#define RG_TX_GAIN_DPDCAL_I_MSK 0xffffe03f
+#define RG_TX_GAIN_DPDCAL_SFT 6
+#define RG_TX_GAIN_DPDCAL_HI 12
+#define RG_TX_GAIN_DPDCAL_SZ 7
+#define RG_IOT_ADC_CLKSEL_MSK 0x00010000
+#define RG_IOT_ADC_CLKSEL_I_MSK 0xfffeffff
+#define RG_IOT_ADC_CLKSEL_SFT 16
+#define RG_IOT_ADC_CLKSEL_HI 16
+#define RG_IOT_ADC_CLKSEL_SZ 1
+#define RG_IOT_ADC_DNLEN_MSK 0x00020000
+#define RG_IOT_ADC_DNLEN_I_MSK 0xfffdffff
+#define RG_IOT_ADC_DNLEN_SFT 17
+#define RG_IOT_ADC_DNLEN_HI 17
+#define RG_IOT_ADC_DNLEN_SZ 1
+#define RG_IOT_ADC_METAEN_MSK 0x00040000
+#define RG_IOT_ADC_METAEN_I_MSK 0xfffbffff
+#define RG_IOT_ADC_METAEN_SFT 18
+#define RG_IOT_ADC_METAEN_HI 18
+#define RG_IOT_ADC_METAEN_SZ 1
+#define RG_IOT_ADC_TFLAG_MSK 0x00080000
+#define RG_IOT_ADC_TFLAG_I_MSK 0xfff7ffff
+#define RG_IOT_ADC_TFLAG_SFT 19
+#define RG_IOT_ADC_TFLAG_HI 19
+#define RG_IOT_ADC_TFLAG_SZ 1
+#define RG_IOT_ADC_ICMP_MSK 0x00300000
+#define RG_IOT_ADC_ICMP_I_MSK 0xffcfffff
+#define RG_IOT_ADC_ICMP_SFT 20
+#define RG_IOT_ADC_ICMP_HI 21
+#define RG_IOT_ADC_ICMP_SZ 2
+#define RG_IOT_ADC_VCMI_MSK 0x00c00000
+#define RG_IOT_ADC_VCMI_I_MSK 0xff3fffff
+#define RG_IOT_ADC_VCMI_SFT 22
+#define RG_IOT_ADC_VCMI_HI 23
+#define RG_IOT_ADC_VCMI_SZ 2
+#define RG_IOT_ADC_CLOAD_MSK 0x03000000
+#define RG_IOT_ADC_CLOAD_I_MSK 0xfcffffff
+#define RG_IOT_ADC_CLOAD_SFT 24
+#define RG_IOT_ADC_CLOAD_HI 25
+#define RG_IOT_ADC_CLOAD_SZ 2
+#define RG_IOT_ADC_CLK_DIV_MSK 0x0c000000
+#define RG_IOT_ADC_CLK_DIV_I_MSK 0xf3ffffff
+#define RG_IOT_ADC_CLK_DIV_SFT 26
+#define RG_IOT_ADC_CLK_DIV_HI 27
+#define RG_IOT_ADC_CLK_DIV_SZ 2
+#define RG_IOT_ADC_CLK_SH_DUTY_MSK 0x10000000
+#define RG_IOT_ADC_CLK_SH_DUTY_I_MSK 0xefffffff
+#define RG_IOT_ADC_CLK_SH_DUTY_SFT 28
+#define RG_IOT_ADC_CLK_SH_DUTY_HI 28
+#define RG_IOT_ADC_CLK_SH_DUTY_SZ 1
+#define RG_IOT_ADC_VSEN_SEL_MSK 0x60000000
+#define RG_IOT_ADC_VSEN_SEL_I_MSK 0x9fffffff
+#define RG_IOT_ADC_VSEN_SEL_SFT 29
+#define RG_IOT_ADC_VSEN_SEL_HI 30
+#define RG_IOT_ADC_VSEN_SEL_SZ 2
+#define DB_AD_ADC_I_OUT_MSK 0x000003ff
+#define DB_AD_ADC_I_OUT_I_MSK 0xfffffc00
+#define DB_AD_ADC_I_OUT_SFT 0
+#define DB_AD_ADC_I_OUT_HI 9
+#define DB_AD_ADC_I_OUT_SZ 10
+#define DB_AD_ADC_Q_OUT_MSK 0x000ffc00
+#define DB_AD_ADC_Q_OUT_I_MSK 0xfff003ff
+#define DB_AD_ADC_Q_OUT_SFT 10
+#define DB_AD_ADC_Q_OUT_HI 19
+#define DB_AD_ADC_Q_OUT_SZ 10
+#define DB_AD_RX_RSSIADC_MSK 0x00f00000
+#define DB_AD_RX_RSSIADC_I_MSK 0xff0fffff
+#define DB_AD_RX_RSSIADC_SFT 20
+#define DB_AD_RX_RSSIADC_HI 23
+#define DB_AD_RX_RSSIADC_SZ 4
+#define DB_DA_SARADC_BIT_MSK 0x3f000000
+#define DB_DA_SARADC_BIT_I_MSK 0xc0ffffff
+#define DB_DA_SARADC_BIT_SFT 24
+#define DB_DA_SARADC_BIT_HI 29
+#define DB_DA_SARADC_BIT_SZ 6
+#define SAR_ADC_FSM_RDY_MSK 0x40000000
+#define SAR_ADC_FSM_RDY_I_MSK 0xbfffffff
+#define SAR_ADC_FSM_RDY_SFT 30
+#define SAR_ADC_FSM_RDY_HI 30
+#define SAR_ADC_FSM_RDY_SZ 1
+#define DB_DA_SX_SUB_SEL_MSK 0x000000ff
+#define DB_DA_SX_SUB_SEL_I_MSK 0xffffff00
+#define DB_DA_SX_SUB_SEL_SFT 0
+#define DB_DA_SX_SUB_SEL_HI 7
+#define DB_DA_SX_SUB_SEL_SZ 8
+#define DB_DA_SX_VCO_ISEL_MSK 0x00000f00
+#define DB_DA_SX_VCO_ISEL_I_MSK 0xfffff0ff
+#define DB_DA_SX_VCO_ISEL_SFT 8
+#define DB_DA_SX_VCO_ISEL_HI 11
+#define DB_DA_SX_VCO_ISEL_SZ 4
+#define DB_VO_AAC_COMPOUT_MSK 0x00001000
+#define DB_VO_AAC_COMPOUT_I_MSK 0xffffefff
+#define DB_VO_AAC_COMPOUT_SFT 12
+#define DB_VO_AAC_COMPOUT_HI 12
+#define DB_VO_AAC_COMPOUT_SZ 1
+#define DB_SX_TTL_VT_DET_MSK 0x0000c000
+#define DB_SX_TTL_VT_DET_I_MSK 0xffff3fff
+#define DB_SX_TTL_VT_DET_SFT 14
+#define DB_SX_TTL_VT_DET_HI 15
+#define DB_SX_TTL_VT_DET_SZ 2
+#define DB_AD_DP_VT_MON_Q_MSK 0x00030000
+#define DB_AD_DP_VT_MON_Q_I_MSK 0xfffcffff
+#define DB_AD_DP_VT_MON_Q_SFT 16
+#define DB_AD_DP_VT_MON_Q_HI 17
+#define DB_AD_DP_VT_MON_Q_SZ 2
+#define DB_AD_IOT_ADC_OUT_MSK 0x3ff00000
+#define DB_AD_IOT_ADC_OUT_I_MSK 0xc00fffff
+#define DB_AD_IOT_ADC_OUT_SFT 20
+#define DB_AD_IOT_ADC_OUT_HI 29
+#define DB_AD_IOT_ADC_OUT_SZ 10
+#define DB_SX_SBCAL_NCOUNT_MSK 0x0000ffff
+#define DB_SX_SBCAL_NCOUNT_I_MSK 0xffff0000
+#define DB_SX_SBCAL_NCOUNT_SFT 0
+#define DB_SX_SBCAL_NCOUNT_HI 15
+#define DB_SX_SBCAL_NCOUNT_SZ 16
+#define DB_SX_SBCAL_NTARGET_MSK 0xffff0000
+#define DB_SX_SBCAL_NTARGET_I_MSK 0x0000ffff
+#define DB_SX_SBCAL_NTARGET_SFT 16
+#define DB_SX_SBCAL_NTARGET_HI 31
+#define DB_SX_SBCAL_NTARGET_SZ 16
+#define RG_5G_TX_TRSW_MANUAL_MSK 0x00000001
+#define RG_5G_TX_TRSW_MANUAL_I_MSK 0xfffffffe
+#define RG_5G_TX_TRSW_MANUAL_SFT 0
+#define RG_5G_TX_TRSW_MANUAL_HI 0
+#define RG_5G_TX_TRSW_MANUAL_SZ 1
+#define RG_5G_EN_TX_TRSW_MSK 0x00000002
+#define RG_5G_EN_TX_TRSW_I_MSK 0xfffffffd
+#define RG_5G_EN_TX_TRSW_SFT 1
+#define RG_5G_EN_TX_TRSW_HI 1
+#define RG_5G_EN_TX_TRSW_SZ 1
+#define RG_5G_RX_LNA_MANUAL_MSK 0x00000004
+#define RG_5G_RX_LNA_MANUAL_I_MSK 0xfffffffb
+#define RG_5G_RX_LNA_MANUAL_SFT 2
+#define RG_5G_RX_LNA_MANUAL_HI 2
+#define RG_5G_RX_LNA_MANUAL_SZ 1
+#define RG_5G_EN_RX_LNA_MSK 0x00000008
+#define RG_5G_EN_RX_LNA_I_MSK 0xfffffff7
+#define RG_5G_EN_RX_LNA_SFT 3
+#define RG_5G_EN_RX_LNA_HI 3
+#define RG_5G_EN_RX_LNA_SZ 1
+#define RG_5G_RX_MIXER_MANUAL_MSK 0x00000010
+#define RG_5G_RX_MIXER_MANUAL_I_MSK 0xffffffef
+#define RG_5G_RX_MIXER_MANUAL_SFT 4
+#define RG_5G_RX_MIXER_MANUAL_HI 4
+#define RG_5G_RX_MIXER_MANUAL_SZ 1
+#define RG_5G_EN_RX_MIXER_MSK 0x00000020
+#define RG_5G_EN_RX_MIXER_I_MSK 0xffffffdf
+#define RG_5G_EN_RX_MIXER_SFT 5
+#define RG_5G_EN_RX_MIXER_HI 5
+#define RG_5G_EN_RX_MIXER_SZ 1
+#define RG_5G_RX_DIV2_MANUAL_MSK 0x00000040
+#define RG_5G_RX_DIV2_MANUAL_I_MSK 0xffffffbf
+#define RG_5G_RX_DIV2_MANUAL_SFT 6
+#define RG_5G_RX_DIV2_MANUAL_HI 6
+#define RG_5G_RX_DIV2_MANUAL_SZ 1
+#define RG_5G_EN_RX_DIV2_MSK 0x00000080
+#define RG_5G_EN_RX_DIV2_I_MSK 0xffffff7f
+#define RG_5G_EN_RX_DIV2_SFT 7
+#define RG_5G_EN_RX_DIV2_HI 7
+#define RG_5G_EN_RX_DIV2_SZ 1
+#define RG_5G_RX_LOBUF_MANUAL_MSK 0x00000100
+#define RG_5G_RX_LOBUF_MANUAL_I_MSK 0xfffffeff
+#define RG_5G_RX_LOBUF_MANUAL_SFT 8
+#define RG_5G_RX_LOBUF_MANUAL_HI 8
+#define RG_5G_RX_LOBUF_MANUAL_SZ 1
+#define RG_5G_EN_RX_LOBUF_MSK 0x00000200
+#define RG_5G_EN_RX_LOBUF_I_MSK 0xfffffdff
+#define RG_5G_EN_RX_LOBUF_SFT 9
+#define RG_5G_EN_RX_LOBUF_HI 9
+#define RG_5G_EN_RX_LOBUF_SZ 1
+#define RG_5G_RX_TZ_MANUAL_MSK 0x00000400
+#define RG_5G_RX_TZ_MANUAL_I_MSK 0xfffffbff
+#define RG_5G_RX_TZ_MANUAL_SFT 10
+#define RG_5G_RX_TZ_MANUAL_HI 10
+#define RG_5G_RX_TZ_MANUAL_SZ 1
+#define RG_5G_EN_RX_TZ_MSK 0x00000800
+#define RG_5G_EN_RX_TZ_I_MSK 0xfffff7ff
+#define RG_5G_EN_RX_TZ_SFT 11
+#define RG_5G_EN_RX_TZ_HI 11
+#define RG_5G_EN_RX_TZ_SZ 1
+#define RG_5G_TX_PA_MANUAL_MSK 0x00001000
+#define RG_5G_TX_PA_MANUAL_I_MSK 0xffffefff
+#define RG_5G_TX_PA_MANUAL_SFT 12
+#define RG_5G_TX_PA_MANUAL_HI 12
+#define RG_5G_TX_PA_MANUAL_SZ 1
+#define RG_5G_EN_TX_PA_MSK 0x00002000
+#define RG_5G_EN_TX_PA_I_MSK 0xffffdfff
+#define RG_5G_EN_TX_PA_SFT 13
+#define RG_5G_EN_TX_PA_HI 13
+#define RG_5G_EN_TX_PA_SZ 1
+#define RG_5G_TX_MOD_MANUAL_MSK 0x00004000
+#define RG_5G_TX_MOD_MANUAL_I_MSK 0xffffbfff
+#define RG_5G_TX_MOD_MANUAL_SFT 14
+#define RG_5G_TX_MOD_MANUAL_HI 14
+#define RG_5G_TX_MOD_MANUAL_SZ 1
+#define RG_5G_EN_TX_MOD_MSK 0x00008000
+#define RG_5G_EN_TX_MOD_I_MSK 0xffff7fff
+#define RG_5G_EN_TX_MOD_SFT 15
+#define RG_5G_EN_TX_MOD_HI 15
+#define RG_5G_EN_TX_MOD_SZ 1
+#define RG_5G_TX_DIV2_MANUAL_MSK 0x00040000
+#define RG_5G_TX_DIV2_MANUAL_I_MSK 0xfffbffff
+#define RG_5G_TX_DIV2_MANUAL_SFT 18
+#define RG_5G_TX_DIV2_MANUAL_HI 18
+#define RG_5G_TX_DIV2_MANUAL_SZ 1
+#define RG_5G_EN_TX_DIV2_MSK 0x00080000
+#define RG_5G_EN_TX_DIV2_I_MSK 0xfff7ffff
+#define RG_5G_EN_TX_DIV2_SFT 19
+#define RG_5G_EN_TX_DIV2_HI 19
+#define RG_5G_EN_TX_DIV2_SZ 1
+#define RG_5G_TX_DIV2_BUF_MANUAL_MSK 0x00100000
+#define RG_5G_TX_DIV2_BUF_MANUAL_I_MSK 0xffefffff
+#define RG_5G_TX_DIV2_BUF_MANUAL_SFT 20
+#define RG_5G_TX_DIV2_BUF_MANUAL_HI 20
+#define RG_5G_TX_DIV2_BUF_MANUAL_SZ 1
+#define RG_5G_EN_TX_DIV2_BUF_MSK 0x00200000
+#define RG_5G_EN_TX_DIV2_BUF_I_MSK 0xffdfffff
+#define RG_5G_EN_TX_DIV2_BUF_SFT 21
+#define RG_5G_EN_TX_DIV2_BUF_HI 21
+#define RG_5G_EN_TX_DIV2_BUF_SZ 1
+#define RG_5G_RX_TZ_OUT_TRISTATE_MANUAL_MSK 0x00400000
+#define RG_5G_RX_TZ_OUT_TRISTATE_MANUAL_I_MSK 0xffbfffff
+#define RG_5G_RX_TZ_OUT_TRISTATE_MANUAL_SFT 22
+#define RG_5G_RX_TZ_OUT_TRISTATE_MANUAL_HI 22
+#define RG_5G_RX_TZ_OUT_TRISTATE_MANUAL_SZ 1
+#define RG_5G_RX_TZ_OUT_TRISTATE_MSK 0x00800000
+#define RG_5G_RX_TZ_OUT_TRISTATE_I_MSK 0xff7fffff
+#define RG_5G_RX_TZ_OUT_TRISTATE_SFT 23
+#define RG_5G_RX_TZ_OUT_TRISTATE_HI 23
+#define RG_5G_RX_TZ_OUT_TRISTATE_SZ 1
+#define RG_5G_TX_SELF_MIXER_MANUAL_MSK 0x01000000
+#define RG_5G_TX_SELF_MIXER_MANUAL_I_MSK 0xfeffffff
+#define RG_5G_TX_SELF_MIXER_MANUAL_SFT 24
+#define RG_5G_TX_SELF_MIXER_MANUAL_HI 24
+#define RG_5G_TX_SELF_MIXER_MANUAL_SZ 1
+#define RG_5G_EN_TX_SELF_MIXER_MSK 0x02000000
+#define RG_5G_EN_TX_SELF_MIXER_I_MSK 0xfdffffff
+#define RG_5G_EN_TX_SELF_MIXER_SFT 25
+#define RG_5G_EN_TX_SELF_MIXER_HI 25
+#define RG_5G_EN_TX_SELF_MIXER_SZ 1
+#define RG_5G_RX_IQCAL_MANUAL_MSK 0x04000000
+#define RG_5G_RX_IQCAL_MANUAL_I_MSK 0xfbffffff
+#define RG_5G_RX_IQCAL_MANUAL_SFT 26
+#define RG_5G_RX_IQCAL_MANUAL_HI 26
+#define RG_5G_RX_IQCAL_MANUAL_SZ 1
+#define RG_5G_EN_RX_IQCAL_MSK 0x08000000
+#define RG_5G_EN_RX_IQCAL_I_MSK 0xf7ffffff
+#define RG_5G_EN_RX_IQCAL_SFT 27
+#define RG_5G_EN_RX_IQCAL_HI 27
+#define RG_5G_EN_RX_IQCAL_SZ 1
+#define RG_5G_TX_DPD_MANUAL_MSK 0x10000000
+#define RG_5G_TX_DPD_MANUAL_I_MSK 0xefffffff
+#define RG_5G_TX_DPD_MANUAL_SFT 28
+#define RG_5G_TX_DPD_MANUAL_HI 28
+#define RG_5G_TX_DPD_MANUAL_SZ 1
+#define RG_5G_EN_TX_DPD_MSK 0x20000000
+#define RG_5G_EN_TX_DPD_I_MSK 0xdfffffff
+#define RG_5G_EN_TX_DPD_SFT 29
+#define RG_5G_EN_TX_DPD_HI 29
+#define RG_5G_EN_TX_DPD_SZ 1
+#define RG_5G_EN_TX_TSSI_MSK 0x40000000
+#define RG_5G_EN_TX_TSSI_I_MSK 0xbfffffff
+#define RG_5G_EN_TX_TSSI_SFT 30
+#define RG_5G_EN_TX_TSSI_HI 30
+#define RG_5G_EN_TX_TSSI_SZ 1
+#define RG_5G_LDO_LEVEL_RX_FE_MSK 0x00000007
+#define RG_5G_LDO_LEVEL_RX_FE_I_MSK 0xfffffff8
+#define RG_5G_LDO_LEVEL_RX_FE_SFT 0
+#define RG_5G_LDO_LEVEL_RX_FE_HI 2
+#define RG_5G_LDO_LEVEL_RX_FE_SZ 3
+#define RG_5G_EN_LDO_RX_FE_BYP_MSK 0x00000008
+#define RG_5G_EN_LDO_RX_FE_BYP_I_MSK 0xfffffff7
+#define RG_5G_EN_LDO_RX_FE_BYP_SFT 3
+#define RG_5G_EN_LDO_RX_FE_BYP_HI 3
+#define RG_5G_EN_LDO_RX_FE_BYP_SZ 1
+#define RG_SX5GB_LDO_CP_LEVEL_MSK 0x00000070
+#define RG_SX5GB_LDO_CP_LEVEL_I_MSK 0xffffff8f
+#define RG_SX5GB_LDO_CP_LEVEL_SFT 4
+#define RG_SX5GB_LDO_CP_LEVEL_HI 6
+#define RG_SX5GB_LDO_CP_LEVEL_SZ 3
+#define RG_EN_LDO_5G_CP_BYP_MSK 0x00000080
+#define RG_EN_LDO_5G_CP_BYP_I_MSK 0xffffff7f
+#define RG_EN_LDO_5G_CP_BYP_SFT 7
+#define RG_EN_LDO_5G_CP_BYP_HI 7
+#define RG_EN_LDO_5G_CP_BYP_SZ 1
+#define RG_SX5GB_LDO_LO_LEVEL_MSK 0x00000700
+#define RG_SX5GB_LDO_LO_LEVEL_I_MSK 0xfffff8ff
+#define RG_SX5GB_LDO_LO_LEVEL_SFT 8
+#define RG_SX5GB_LDO_LO_LEVEL_HI 10
+#define RG_SX5GB_LDO_LO_LEVEL_SZ 3
+#define RG_EN_LDO_5G_LO_BYP_MSK 0x00000800
+#define RG_EN_LDO_5G_LO_BYP_I_MSK 0xfffff7ff
+#define RG_EN_LDO_5G_LO_BYP_SFT 11
+#define RG_EN_LDO_5G_LO_BYP_HI 11
+#define RG_EN_LDO_5G_LO_BYP_SZ 1
+#define RG_SX5GB_LDO_VCO_LEVEL_MSK 0x00007000
+#define RG_SX5GB_LDO_VCO_LEVEL_I_MSK 0xffff8fff
+#define RG_SX5GB_LDO_VCO_LEVEL_SFT 12
+#define RG_SX5GB_LDO_VCO_LEVEL_HI 14
+#define RG_SX5GB_LDO_VCO_LEVEL_SZ 3
+#define RG_SX5GB_LDO_DIV_LEVEL_MSK 0x00070000
+#define RG_SX5GB_LDO_DIV_LEVEL_I_MSK 0xfff8ffff
+#define RG_SX5GB_LDO_DIV_LEVEL_SFT 16
+#define RG_SX5GB_LDO_DIV_LEVEL_HI 18
+#define RG_SX5GB_LDO_DIV_LEVEL_SZ 3
+#define RG_EN_LDO_5G_DIV_BYP_MSK 0x00080000
+#define RG_EN_LDO_5G_DIV_BYP_I_MSK 0xfff7ffff
+#define RG_EN_LDO_5G_DIV_BYP_SFT 19
+#define RG_EN_LDO_5G_DIV_BYP_HI 19
+#define RG_EN_LDO_5G_DIV_BYP_SZ 1
+#define RG_5G_EN_LDO_RX_FE_MSK 0x01000000
+#define RG_5G_EN_LDO_RX_FE_I_MSK 0xfeffffff
+#define RG_5G_EN_LDO_RX_FE_SFT 24
+#define RG_5G_EN_LDO_RX_FE_HI 24
+#define RG_5G_EN_LDO_RX_FE_SZ 1
+#define RG_5G_EN_IREF_RX_MSK 0x02000000
+#define RG_5G_EN_IREF_RX_I_MSK 0xfdffffff
+#define RG_5G_EN_IREF_RX_SFT 25
+#define RG_5G_EN_IREF_RX_HI 25
+#define RG_5G_EN_IREF_RX_SZ 1
+#define RG_5G_EN_LDO_RX_FE_FC_MSK 0x04000000
+#define RG_5G_EN_LDO_RX_FE_FC_I_MSK 0xfbffffff
+#define RG_5G_EN_LDO_RX_FE_FC_SFT 26
+#define RG_5G_EN_LDO_RX_FE_FC_HI 26
+#define RG_5G_EN_LDO_RX_FE_FC_SZ 1
+#define RG_5G_EN_LDO_RX_FE_IQUP_MSK 0x08000000
+#define RG_5G_EN_LDO_RX_FE_IQUP_I_MSK 0xf7ffffff
+#define RG_5G_EN_LDO_RX_FE_IQUP_SFT 27
+#define RG_5G_EN_LDO_RX_FE_IQUP_HI 27
+#define RG_5G_EN_LDO_RX_FE_IQUP_SZ 1
+#define RG_5G_RX_SCA_MANUAL_MSK 0x00000001
+#define RG_5G_RX_SCA_MANUAL_I_MSK 0xfffffffe
+#define RG_5G_RX_SCA_MANUAL_SFT 0
+#define RG_5G_RX_SCA_MANUAL_HI 0
+#define RG_5G_RX_SCA_MANUAL_SZ 1
+#define RG_5G_RX_SCA_MA_MSK 0x0000000e
+#define RG_5G_RX_SCA_MA_I_MSK 0xfffffff1
+#define RG_5G_RX_SCA_MA_SFT 1
+#define RG_5G_RX_SCA_MA_HI 3
+#define RG_5G_RX_SCA_MA_SZ 3
+#define RG_5G_RX_SCA_LOAD_MSK 0x00000070
+#define RG_5G_RX_SCA_LOAD_I_MSK 0xffffff8f
+#define RG_5G_RX_SCA_LOAD_SFT 4
+#define RG_5G_RX_SCA_LOAD_HI 6
+#define RG_5G_RX_SCA_LOAD_SZ 3
+#define RG_5G_RX_LNA_TRI_SEL_MSK 0x00000300
+#define RG_5G_RX_LNA_TRI_SEL_I_MSK 0xfffffcff
+#define RG_5G_RX_LNA_TRI_SEL_SFT 8
+#define RG_5G_RX_LNA_TRI_SEL_HI 9
+#define RG_5G_RX_LNA_TRI_SEL_SZ 2
+#define RG_5G_RX_LNA_SETTLE_MSK 0x00000c00
+#define RG_5G_RX_LNA_SETTLE_I_MSK 0xfffff3ff
+#define RG_5G_RX_LNA_SETTLE_SFT 10
+#define RG_5G_RX_LNA_SETTLE_HI 11
+#define RG_5G_RX_LNA_SETTLE_SZ 2
+#define RG_5G_GM_BIAS_MSK 0x00007000
+#define RG_5G_GM_BIAS_I_MSK 0xffff8fff
+#define RG_5G_GM_BIAS_SFT 12
+#define RG_5G_GM_BIAS_HI 14
+#define RG_5G_GM_BIAS_SZ 3
+#define RG_5G_RX_DIV2_BUF_MSK 0x00030000
+#define RG_5G_RX_DIV2_BUF_I_MSK 0xfffcffff
+#define RG_5G_RX_DIV2_BUF_SFT 16
+#define RG_5G_RX_DIV2_BUF_HI 17
+#define RG_5G_RX_DIV2_BUF_SZ 2
+#define RG_5G_RX_DIV2_CML_MSK 0x000c0000
+#define RG_5G_RX_DIV2_CML_I_MSK 0xfff3ffff
+#define RG_5G_RX_DIV2_CML_SFT 18
+#define RG_5G_RX_DIV2_CML_HI 19
+#define RG_5G_RX_DIV2_CML_SZ 2
+#define RG_5G_RX_DIV_CMLISEL_MSK 0x00300000
+#define RG_5G_RX_DIV_CMLISEL_I_MSK 0xffcfffff
+#define RG_5G_RX_DIV_CMLISEL_SFT 20
+#define RG_5G_RX_DIV_CMLISEL_HI 21
+#define RG_5G_RX_DIV_CMLISEL_SZ 2
+#define RG_5G_RX_DIV_PREBUFS2_MSK 0x00400000
+#define RG_5G_RX_DIV_PREBUFS2_I_MSK 0xffbfffff
+#define RG_5G_RX_DIV_PREBUFS2_SFT 22
+#define RG_5G_RX_DIV_PREBUFS2_HI 22
+#define RG_5G_RX_DIV_PREBUFS2_SZ 1
+#define RG_5G_RX_TZ_COURSE_MSK 0x03000000
+#define RG_5G_RX_TZ_COURSE_I_MSK 0xfcffffff
+#define RG_5G_RX_TZ_COURSE_SFT 24
+#define RG_5G_RX_TZ_COURSE_HI 25
+#define RG_5G_RX_TZ_COURSE_SZ 2
+#define RG_5G_TX_DPDGM_BIAS_MSK 0xf0000000
+#define RG_5G_TX_DPDGM_BIAS_I_MSK 0x0fffffff
+#define RG_5G_TX_DPDGM_BIAS_SFT 28
+#define RG_5G_TX_DPDGM_BIAS_HI 31
+#define RG_5G_TX_DPDGM_BIAS_SZ 4
+#define RG_5G_TX_DPD_DIV_MSK 0x0000000f
+#define RG_5G_TX_DPD_DIV_I_MSK 0xfffffff0
+#define RG_5G_TX_DPD_DIV_SFT 0
+#define RG_5G_TX_DPD_DIV_HI 3
+#define RG_5G_TX_DPD_DIV_SZ 4
+#define RG_5G_TX_TSSI_BIAS_MSK 0x00000070
+#define RG_5G_TX_TSSI_BIAS_I_MSK 0xffffff8f
+#define RG_5G_TX_TSSI_BIAS_SFT 4
+#define RG_5G_TX_TSSI_BIAS_HI 6
+#define RG_5G_TX_TSSI_BIAS_SZ 3
+#define RG_5G_TX_TSSI_DIV_MSK 0x00000700
+#define RG_5G_TX_TSSI_DIV_I_MSK 0xfffff8ff
+#define RG_5G_TX_TSSI_DIV_SFT 8
+#define RG_5G_TX_TSSI_DIV_HI 10
+#define RG_5G_TX_TSSI_DIV_SZ 3
+#define RG_5G_TX_TSSI_TEST_MSK 0x00003000
+#define RG_5G_TX_TSSI_TEST_I_MSK 0xffffcfff
+#define RG_5G_TX_TSSI_TEST_SFT 12
+#define RG_5G_TX_TSSI_TEST_HI 13
+#define RG_5G_TX_TSSI_TEST_SZ 2
+#define RG_5G_TX_TSSI_TESTMODE_MSK 0x00004000
+#define RG_5G_TX_TSSI_TESTMODE_I_MSK 0xffffbfff
+#define RG_5G_TX_TSSI_TESTMODE_SFT 14
+#define RG_5G_TX_TSSI_TESTMODE_HI 14
+#define RG_5G_TX_TSSI_TESTMODE_SZ 1
+#define RG_5G_RX_ADC_ICMP_MSK 0x00030000
+#define RG_5G_RX_ADC_ICMP_I_MSK 0xfffcffff
+#define RG_5G_RX_ADC_ICMP_SFT 16
+#define RG_5G_RX_ADC_ICMP_HI 17
+#define RG_5G_RX_ADC_ICMP_SZ 2
+#define RG_5G_RX_ADC_VCMI_MSK 0x000c0000
+#define RG_5G_RX_ADC_VCMI_I_MSK 0xfff3ffff
+#define RG_5G_RX_ADC_VCMI_SFT 18
+#define RG_5G_RX_ADC_VCMI_HI 19
+#define RG_5G_RX_ADC_VCMI_SZ 2
+#define RG_5G_RX_ADC_CLOAD_MSK 0x00300000
+#define RG_5G_RX_ADC_CLOAD_I_MSK 0xffcfffff
+#define RG_5G_RX_ADC_CLOAD_SFT 20
+#define RG_5G_RX_ADC_CLOAD_HI 21
+#define RG_5G_RX_ADC_CLOAD_SZ 2
+#define RG_5G_RX_ADC_PSW_MSK 0x00400000
+#define RG_5G_RX_ADC_PSW_I_MSK 0xffbfffff
+#define RG_5G_RX_ADC_PSW_SFT 22
+#define RG_5G_RX_ADC_PSW_HI 22
+#define RG_5G_RX_ADC_PSW_SZ 1
+#define RG_5G_RX_TZ_CMZ_C_MSK 0x01800000
+#define RG_5G_RX_TZ_CMZ_C_I_MSK 0xfe7fffff
+#define RG_5G_RX_TZ_CMZ_C_SFT 23
+#define RG_5G_RX_TZ_CMZ_C_HI 24
+#define RG_5G_RX_TZ_CMZ_C_SZ 2
+#define RG_5G_RX_TZ_CMZ_R_MSK 0x06000000
+#define RG_5G_RX_TZ_CMZ_R_I_MSK 0xf9ffffff
+#define RG_5G_RX_TZ_CMZ_R_SFT 25
+#define RG_5G_RX_TZ_CMZ_R_HI 26
+#define RG_5G_RX_TZ_CMZ_R_SZ 2
+#define RG_5G_TXPAPGA_MANUAL_MSK 0x00000001
+#define RG_5G_TXPAPGA_MANUAL_I_MSK 0xfffffffe
+#define RG_5G_TXPAPGA_MANUAL_SFT 0
+#define RG_5G_TXPAPGA_MANUAL_HI 0
+#define RG_5G_TXPAPGA_MANUAL_SZ 1
+#define RG_5G_TXPGA_CAPSW_MSK 0x0000000e
+#define RG_5G_TXPGA_CAPSW_I_MSK 0xfffffff1
+#define RG_5G_TXPGA_CAPSW_SFT 1
+#define RG_5G_TXPGA_CAPSW_HI 3
+#define RG_5G_TXPGA_CAPSW_SZ 3
+#define RG_5G_PACELL_EN_MSK 0x000000e0
+#define RG_5G_PACELL_EN_I_MSK 0xffffff1f
+#define RG_5G_PACELL_EN_SFT 5
+#define RG_5G_PACELL_EN_HI 7
+#define RG_5G_PACELL_EN_SZ 3
+#define RG_5G_PABIAS_CTRL_MSK 0x00000f00
+#define RG_5G_PABIAS_CTRL_I_MSK 0xfffff0ff
+#define RG_5G_PABIAS_CTRL_SFT 8
+#define RG_5G_PABIAS_CTRL_HI 11
+#define RG_5G_PABIAS_CTRL_SZ 4
+#define RG_5G_TX_PAFB_EN_MSK 0x00001000
+#define RG_5G_TX_PAFB_EN_I_MSK 0xffffefff
+#define RG_5G_TX_PAFB_EN_SFT 12
+#define RG_5G_TX_PAFB_EN_HI 12
+#define RG_5G_TX_PAFB_EN_SZ 1
+#define RG_5G_TX_PA1_VCAS_MSK 0x0000e000
+#define RG_5G_TX_PA1_VCAS_I_MSK 0xffff1fff
+#define RG_5G_TX_PA1_VCAS_SFT 13
+#define RG_5G_TX_PA1_VCAS_HI 15
+#define RG_5G_TX_PA1_VCAS_SZ 3
+#define RG_5G_TX_PA2_VCAS_MSK 0x00070000
+#define RG_5G_TX_PA2_VCAS_I_MSK 0xfff8ffff
+#define RG_5G_TX_PA2_VCAS_SFT 16
+#define RG_5G_TX_PA2_VCAS_HI 18
+#define RG_5G_TX_PA2_VCAS_SZ 3
+#define RG_5G_PABIAS_2X_MSK 0x00080000
+#define RG_5G_PABIAS_2X_I_MSK 0xfff7ffff
+#define RG_5G_PABIAS_2X_SFT 19
+#define RG_5G_PABIAS_2X_HI 19
+#define RG_5G_PABIAS_2X_SZ 1
+#define RG_5G_TX_PA3_VCAS_MSK 0x00700000
+#define RG_5G_TX_PA3_VCAS_I_MSK 0xff8fffff
+#define RG_5G_TX_PA3_VCAS_SFT 20
+#define RG_5G_TX_PA3_VCAS_HI 22
+#define RG_5G_TX_PA3_VCAS_SZ 3
+#define RG_5G_TX_DIV_PREBUFS2_MSK 0x00800000
+#define RG_5G_TX_DIV_PREBUFS2_I_MSK 0xff7fffff
+#define RG_5G_TX_DIV_PREBUFS2_SFT 23
+#define RG_5G_TX_DIV_PREBUFS2_HI 23
+#define RG_5G_TX_DIV_PREBUFS2_SZ 1
+#define RG_5G_TX_DIV_CMLISEL_MSK 0x03000000
+#define RG_5G_TX_DIV_CMLISEL_I_MSK 0xfcffffff
+#define RG_5G_TX_DIV_CMLISEL_SFT 24
+#define RG_5G_TX_DIV_CMLISEL_HI 25
+#define RG_5G_TX_DIV_CMLISEL_SZ 2
+#define RG_5G_TX_DIV_CMLVSEL_MSK 0x0c000000
+#define RG_5G_TX_DIV_CMLVSEL_I_MSK 0xf3ffffff
+#define RG_5G_TX_DIV_CMLVSEL_SFT 26
+#define RG_5G_TX_DIV_CMLVSEL_HI 27
+#define RG_5G_TX_DIV_CMLVSEL_SZ 2
+#define RG_5G_TX_DIV_VSET_MSK 0x30000000
+#define RG_5G_TX_DIV_VSET_I_MSK 0xcfffffff
+#define RG_5G_TX_DIV_VSET_SFT 28
+#define RG_5G_TX_DIV_VSET_HI 29
+#define RG_5G_TX_DIV_VSET_SZ 2
+#define RG_5G_TX_LOBUF_VSET_MSK 0xc0000000
+#define RG_5G_TX_LOBUF_VSET_I_MSK 0x3fffffff
+#define RG_5G_TX_LOBUF_VSET_SFT 30
+#define RG_5G_TX_LOBUF_VSET_HI 31
+#define RG_5G_TX_LOBUF_VSET_SZ 2
+#define RG_5G_TXPGA_MAIN_MSK 0x0000003f
+#define RG_5G_TXPGA_MAIN_I_MSK 0xffffffc0
+#define RG_5G_TXPGA_MAIN_SFT 0
+#define RG_5G_TXPGA_MAIN_HI 5
+#define RG_5G_TXPGA_MAIN_SZ 6
+#define RG_5G_TXPGA_STEER_MSK 0x00000fc0
+#define RG_5G_TXPGA_STEER_I_MSK 0xfffff03f
+#define RG_5G_TXPGA_STEER_SFT 6
+#define RG_5G_TXPGA_STEER_HI 11
+#define RG_5G_TXPGA_STEER_SZ 6
+#define RG_5G_TXMOD_GMCELL_MSK 0x00003000
+#define RG_5G_TXMOD_GMCELL_I_MSK 0xffffcfff
+#define RG_5G_TXMOD_GMCELL_SFT 12
+#define RG_5G_TXMOD_GMCELL_HI 13
+#define RG_5G_TXMOD_GMCELL_SZ 2
+#define RG_5G_TXLPF_GMCELL_MSK 0x0000c000
+#define RG_5G_TXLPF_GMCELL_I_MSK 0xffff3fff
+#define RG_5G_TXLPF_GMCELL_SFT 14
+#define RG_5G_TXLPF_GMCELL_HI 15
+#define RG_5G_TXLPF_GMCELL_SZ 2
+#define RG_5G_TX_GAIN_OFFSET_MSK 0x000f0000
+#define RG_5G_TX_GAIN_OFFSET_I_MSK 0xfff0ffff
+#define RG_5G_TX_GAIN_OFFSET_SFT 16
+#define RG_5G_TX_GAIN_OFFSET_HI 19
+#define RG_5G_TX_GAIN_OFFSET_SZ 4
+#define RG_5G_TX_GAIN_MSK 0x07f00000
+#define RG_5G_TX_GAIN_I_MSK 0xf80fffff
+#define RG_5G_TX_GAIN_SFT 20
+#define RG_5G_TX_GAIN_HI 26
+#define RG_5G_TX_GAIN_SZ 7
+#define RG_5G_TX_ADDGMCELL_MSK 0x08000000
+#define RG_5G_TX_ADDGMCELL_I_MSK 0xf7ffffff
+#define RG_5G_TX_ADDGMCELL_SFT 27
+#define RG_5G_TX_ADDGMCELL_HI 27
+#define RG_5G_TX_ADDGMCELL_SZ 1
+#define RG_5G_TXMOD_LOBIAS_MSK 0x30000000
+#define RG_5G_TXMOD_LOBIAS_I_MSK 0xcfffffff
+#define RG_5G_TXMOD_LOBIAS_SFT 28
+#define RG_5G_TXMOD_LOBIAS_HI 29
+#define RG_5G_TXMOD_LOBIAS_SZ 2
+#define RG_5G_TXMOD_PGABIAS_MSK 0xc0000000
+#define RG_5G_TXMOD_PGABIAS_I_MSK 0x3fffffff
+#define RG_5G_TXMOD_PGABIAS_SFT 30
+#define RG_5G_TXMOD_PGABIAS_HI 31
+#define RG_5G_TXMOD_PGABIAS_SZ 2
+#define RG_5G_RX_HG_LNA_GC_MSK 0x00000003
+#define RG_5G_RX_HG_LNA_GC_I_MSK 0xfffffffc
+#define RG_5G_RX_HG_LNA_GC_SFT 0
+#define RG_5G_RX_HG_LNA_GC_HI 1
+#define RG_5G_RX_HG_LNA_GC_SZ 2
+#define RG_5G_RX_HG_TZ_GC_MSK 0x0000000c
+#define RG_5G_RX_HG_TZ_GC_I_MSK 0xfffffff3
+#define RG_5G_RX_HG_TZ_GC_SFT 2
+#define RG_5G_RX_HG_TZ_GC_HI 3
+#define RG_5G_RX_HG_TZ_GC_SZ 2
+#define RG_5G_RX_HG_LNAHGN_BIAS_MSK 0x000000f0
+#define RG_5G_RX_HG_LNAHGN_BIAS_I_MSK 0xffffff0f
+#define RG_5G_RX_HG_LNAHGN_BIAS_SFT 4
+#define RG_5G_RX_HG_LNAHGN_BIAS_HI 7
+#define RG_5G_RX_HG_LNAHGN_BIAS_SZ 4
+#define RG_5G_RX_HG_LNAHGP_BIAS_MSK 0x00000f00
+#define RG_5G_RX_HG_LNAHGP_BIAS_I_MSK 0xfffff0ff
+#define RG_5G_RX_HG_LNAHGP_BIAS_SFT 8
+#define RG_5G_RX_HG_LNAHGP_BIAS_HI 11
+#define RG_5G_RX_HG_LNAHGP_BIAS_SZ 4
+#define RG_5G_RX_HG_LNALG_BIAS_MSK 0x0000f000
+#define RG_5G_RX_HG_LNALG_BIAS_I_MSK 0xffff0fff
+#define RG_5G_RX_HG_LNALG_BIAS_SFT 12
+#define RG_5G_RX_HG_LNALG_BIAS_HI 15
+#define RG_5G_RX_HG_LNALG_BIAS_SZ 4
+#define RG_5G_RX_HG_TZ_CAP_MSK 0x00070000
+#define RG_5G_RX_HG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_5G_RX_HG_TZ_CAP_SFT 16
+#define RG_5G_RX_HG_TZ_CAP_HI 18
+#define RG_5G_RX_HG_TZ_CAP_SZ 3
+#define RG_5G_RX_HG_SQDC_MSK 0x00380000
+#define RG_5G_RX_HG_SQDC_I_MSK 0xffc7ffff
+#define RG_5G_RX_HG_SQDC_SFT 19
+#define RG_5G_RX_HG_SQDC_HI 21
+#define RG_5G_RX_HG_SQDC_SZ 3
+#define RG_5G_RX_HG_DIV2_CORE_MSK 0x00c00000
+#define RG_5G_RX_HG_DIV2_CORE_I_MSK 0xff3fffff
+#define RG_5G_RX_HG_DIV2_CORE_SFT 22
+#define RG_5G_RX_HG_DIV2_CORE_HI 23
+#define RG_5G_RX_HG_DIV2_CORE_SZ 2
+#define RG_5G_RX_HG_TZ_GC_BOOST_MSK 0x03000000
+#define RG_5G_RX_HG_TZ_GC_BOOST_I_MSK 0xfcffffff
+#define RG_5G_RX_HG_TZ_GC_BOOST_SFT 24
+#define RG_5G_RX_HG_TZ_GC_BOOST_HI 25
+#define RG_5G_RX_HG_TZ_GC_BOOST_SZ 2
+#define RG_5G_RX_HG_TZI_MSK 0x1c000000
+#define RG_5G_RX_HG_TZI_I_MSK 0xe3ffffff
+#define RG_5G_RX_HG_TZI_SFT 26
+#define RG_5G_RX_HG_TZI_HI 28
+#define RG_5G_RX_HG_TZI_SZ 3
+#define RG_5G_RX_HG_TZ_VCM_MSK 0xe0000000
+#define RG_5G_RX_HG_TZ_VCM_I_MSK 0x1fffffff
+#define RG_5G_RX_HG_TZ_VCM_SFT 29
+#define RG_5G_RX_HG_TZ_VCM_HI 31
+#define RG_5G_RX_HG_TZ_VCM_SZ 3
+#define RG_5G_RX_MG_LNA_GC_MSK 0x00000003
+#define RG_5G_RX_MG_LNA_GC_I_MSK 0xfffffffc
+#define RG_5G_RX_MG_LNA_GC_SFT 0
+#define RG_5G_RX_MG_LNA_GC_HI 1
+#define RG_5G_RX_MG_LNA_GC_SZ 2
+#define RG_5G_RX_MG_TZ_GC_MSK 0x0000000c
+#define RG_5G_RX_MG_TZ_GC_I_MSK 0xfffffff3
+#define RG_5G_RX_MG_TZ_GC_SFT 2
+#define RG_5G_RX_MG_TZ_GC_HI 3
+#define RG_5G_RX_MG_TZ_GC_SZ 2
+#define RG_5G_RX_MG_LNAHGN_BIAS_MSK 0x000000f0
+#define RG_5G_RX_MG_LNAHGN_BIAS_I_MSK 0xffffff0f
+#define RG_5G_RX_MG_LNAHGN_BIAS_SFT 4
+#define RG_5G_RX_MG_LNAHGN_BIAS_HI 7
+#define RG_5G_RX_MG_LNAHGN_BIAS_SZ 4
+#define RG_5G_RX_MG_LNAHGP_BIAS_MSK 0x00000f00
+#define RG_5G_RX_MG_LNAHGP_BIAS_I_MSK 0xfffff0ff
+#define RG_5G_RX_MG_LNAHGP_BIAS_SFT 8
+#define RG_5G_RX_MG_LNAHGP_BIAS_HI 11
+#define RG_5G_RX_MG_LNAHGP_BIAS_SZ 4
+#define RG_5G_RX_MG_LNALG_BIAS_MSK 0x0000f000
+#define RG_5G_RX_MG_LNALG_BIAS_I_MSK 0xffff0fff
+#define RG_5G_RX_MG_LNALG_BIAS_SFT 12
+#define RG_5G_RX_MG_LNALG_BIAS_HI 15
+#define RG_5G_RX_MG_LNALG_BIAS_SZ 4
+#define RG_5G_RX_MG_TZ_CAP_MSK 0x00070000
+#define RG_5G_RX_MG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_5G_RX_MG_TZ_CAP_SFT 16
+#define RG_5G_RX_MG_TZ_CAP_HI 18
+#define RG_5G_RX_MG_TZ_CAP_SZ 3
+#define RG_5G_RX_MG_SQDC_MSK 0x00380000
+#define RG_5G_RX_MG_SQDC_I_MSK 0xffc7ffff
+#define RG_5G_RX_MG_SQDC_SFT 19
+#define RG_5G_RX_MG_SQDC_HI 21
+#define RG_5G_RX_MG_SQDC_SZ 3
+#define RG_5G_RX_MG_DIV2_CORE_MSK 0x00c00000
+#define RG_5G_RX_MG_DIV2_CORE_I_MSK 0xff3fffff
+#define RG_5G_RX_MG_DIV2_CORE_SFT 22
+#define RG_5G_RX_MG_DIV2_CORE_HI 23
+#define RG_5G_RX_MG_DIV2_CORE_SZ 2
+#define RG_5G_RX_MG_TZ_GC_BOOST_MSK 0x03000000
+#define RG_5G_RX_MG_TZ_GC_BOOST_I_MSK 0xfcffffff
+#define RG_5G_RX_MG_TZ_GC_BOOST_SFT 24
+#define RG_5G_RX_MG_TZ_GC_BOOST_HI 25
+#define RG_5G_RX_MG_TZ_GC_BOOST_SZ 2
+#define RG_5G_RX_MG_TZI_MSK 0x1c000000
+#define RG_5G_RX_MG_TZI_I_MSK 0xe3ffffff
+#define RG_5G_RX_MG_TZI_SFT 26
+#define RG_5G_RX_MG_TZI_HI 28
+#define RG_5G_RX_MG_TZI_SZ 3
+#define RG_5G_RX_MG_TZ_VCM_MSK 0xe0000000
+#define RG_5G_RX_MG_TZ_VCM_I_MSK 0x1fffffff
+#define RG_5G_RX_MG_TZ_VCM_SFT 29
+#define RG_5G_RX_MG_TZ_VCM_HI 31
+#define RG_5G_RX_MG_TZ_VCM_SZ 3
+#define RG_5G_RX_LG_LNA_GC_MSK 0x00000003
+#define RG_5G_RX_LG_LNA_GC_I_MSK 0xfffffffc
+#define RG_5G_RX_LG_LNA_GC_SFT 0
+#define RG_5G_RX_LG_LNA_GC_HI 1
+#define RG_5G_RX_LG_LNA_GC_SZ 2
+#define RG_5G_RX_LG_TZ_GC_MSK 0x0000000c
+#define RG_5G_RX_LG_TZ_GC_I_MSK 0xfffffff3
+#define RG_5G_RX_LG_TZ_GC_SFT 2
+#define RG_5G_RX_LG_TZ_GC_HI 3
+#define RG_5G_RX_LG_TZ_GC_SZ 2
+#define RG_5G_RX_LG_LNAHGN_BIAS_MSK 0x000000f0
+#define RG_5G_RX_LG_LNAHGN_BIAS_I_MSK 0xffffff0f
+#define RG_5G_RX_LG_LNAHGN_BIAS_SFT 4
+#define RG_5G_RX_LG_LNAHGN_BIAS_HI 7
+#define RG_5G_RX_LG_LNAHGN_BIAS_SZ 4
+#define RG_5G_RX_LG_LNAHGP_BIAS_MSK 0x00000f00
+#define RG_5G_RX_LG_LNAHGP_BIAS_I_MSK 0xfffff0ff
+#define RG_5G_RX_LG_LNAHGP_BIAS_SFT 8
+#define RG_5G_RX_LG_LNAHGP_BIAS_HI 11
+#define RG_5G_RX_LG_LNAHGP_BIAS_SZ 4
+#define RG_5G_RX_LG_LNALG_BIAS_MSK 0x0000f000
+#define RG_5G_RX_LG_LNALG_BIAS_I_MSK 0xffff0fff
+#define RG_5G_RX_LG_LNALG_BIAS_SFT 12
+#define RG_5G_RX_LG_LNALG_BIAS_HI 15
+#define RG_5G_RX_LG_LNALG_BIAS_SZ 4
+#define RG_5G_RX_LG_TZ_CAP_MSK 0x00070000
+#define RG_5G_RX_LG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_5G_RX_LG_TZ_CAP_SFT 16
+#define RG_5G_RX_LG_TZ_CAP_HI 18
+#define RG_5G_RX_LG_TZ_CAP_SZ 3
+#define RG_5G_RX_LG_SQDC_MSK 0x00380000
+#define RG_5G_RX_LG_SQDC_I_MSK 0xffc7ffff
+#define RG_5G_RX_LG_SQDC_SFT 19
+#define RG_5G_RX_LG_SQDC_HI 21
+#define RG_5G_RX_LG_SQDC_SZ 3
+#define RG_5G_RX_LG_DIV2_CORE_MSK 0x00c00000
+#define RG_5G_RX_LG_DIV2_CORE_I_MSK 0xff3fffff
+#define RG_5G_RX_LG_DIV2_CORE_SFT 22
+#define RG_5G_RX_LG_DIV2_CORE_HI 23
+#define RG_5G_RX_LG_DIV2_CORE_SZ 2
+#define RG_5G_RX_LG_TZ_GC_BOOST_MSK 0x03000000
+#define RG_5G_RX_LG_TZ_GC_BOOST_I_MSK 0xfcffffff
+#define RG_5G_RX_LG_TZ_GC_BOOST_SFT 24
+#define RG_5G_RX_LG_TZ_GC_BOOST_HI 25
+#define RG_5G_RX_LG_TZ_GC_BOOST_SZ 2
+#define RG_5G_RX_LG_TZI_MSK 0x1c000000
+#define RG_5G_RX_LG_TZI_I_MSK 0xe3ffffff
+#define RG_5G_RX_LG_TZI_SFT 26
+#define RG_5G_RX_LG_TZI_HI 28
+#define RG_5G_RX_LG_TZI_SZ 3
+#define RG_5G_RX_LG_TZ_VCM_MSK 0xe0000000
+#define RG_5G_RX_LG_TZ_VCM_I_MSK 0x1fffffff
+#define RG_5G_RX_LG_TZ_VCM_SFT 29
+#define RG_5G_RX_LG_TZ_VCM_HI 31
+#define RG_5G_RX_LG_TZ_VCM_SZ 3
+#define RG_5G_RX_ULG_LNA_GC_MSK 0x00000003
+#define RG_5G_RX_ULG_LNA_GC_I_MSK 0xfffffffc
+#define RG_5G_RX_ULG_LNA_GC_SFT 0
+#define RG_5G_RX_ULG_LNA_GC_HI 1
+#define RG_5G_RX_ULG_LNA_GC_SZ 2
+#define RG_5G_RX_ULG_TZ_GC_MSK 0x0000000c
+#define RG_5G_RX_ULG_TZ_GC_I_MSK 0xfffffff3
+#define RG_5G_RX_ULG_TZ_GC_SFT 2
+#define RG_5G_RX_ULG_TZ_GC_HI 3
+#define RG_5G_RX_ULG_TZ_GC_SZ 2
+#define RG_5G_RX_ULG_LNAHGN_BIAS_MSK 0x000000f0
+#define RG_5G_RX_ULG_LNAHGN_BIAS_I_MSK 0xffffff0f
+#define RG_5G_RX_ULG_LNAHGN_BIAS_SFT 4
+#define RG_5G_RX_ULG_LNAHGN_BIAS_HI 7
+#define RG_5G_RX_ULG_LNAHGN_BIAS_SZ 4
+#define RG_5G_RX_ULG_LNAHGP_BIAS_MSK 0x00000f00
+#define RG_5G_RX_ULG_LNAHGP_BIAS_I_MSK 0xfffff0ff
+#define RG_5G_RX_ULG_LNAHGP_BIAS_SFT 8
+#define RG_5G_RX_ULG_LNAHGP_BIAS_HI 11
+#define RG_5G_RX_ULG_LNAHGP_BIAS_SZ 4
+#define RG_5G_RX_ULG_LNALG_BIAS_MSK 0x0000f000
+#define RG_5G_RX_ULG_LNALG_BIAS_I_MSK 0xffff0fff
+#define RG_5G_RX_ULG_LNALG_BIAS_SFT 12
+#define RG_5G_RX_ULG_LNALG_BIAS_HI 15
+#define RG_5G_RX_ULG_LNALG_BIAS_SZ 4
+#define RG_5G_RX_ULG_TZ_CAP_MSK 0x00070000
+#define RG_5G_RX_ULG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_5G_RX_ULG_TZ_CAP_SFT 16
+#define RG_5G_RX_ULG_TZ_CAP_HI 18
+#define RG_5G_RX_ULG_TZ_CAP_SZ 3
+#define RG_5G_RX_ULG_SQDC_MSK 0x00380000
+#define RG_5G_RX_ULG_SQDC_I_MSK 0xffc7ffff
+#define RG_5G_RX_ULG_SQDC_SFT 19
+#define RG_5G_RX_ULG_SQDC_HI 21
+#define RG_5G_RX_ULG_SQDC_SZ 3
+#define RG_5G_RX_ULG_DIV2_CORE_MSK 0x00c00000
+#define RG_5G_RX_ULG_DIV2_CORE_I_MSK 0xff3fffff
+#define RG_5G_RX_ULG_DIV2_CORE_SFT 22
+#define RG_5G_RX_ULG_DIV2_CORE_HI 23
+#define RG_5G_RX_ULG_DIV2_CORE_SZ 2
+#define RG_5G_RX_ULG_TZ_GC_BOOST_MSK 0x03000000
+#define RG_5G_RX_ULG_TZ_GC_BOOST_I_MSK 0xfcffffff
+#define RG_5G_RX_ULG_TZ_GC_BOOST_SFT 24
+#define RG_5G_RX_ULG_TZ_GC_BOOST_HI 25
+#define RG_5G_RX_ULG_TZ_GC_BOOST_SZ 2
+#define RG_5G_RX_ULG_TZI_MSK 0x1c000000
+#define RG_5G_RX_ULG_TZI_I_MSK 0xe3ffffff
+#define RG_5G_RX_ULG_TZI_SFT 26
+#define RG_5G_RX_ULG_TZI_HI 28
+#define RG_5G_RX_ULG_TZI_SZ 3
+#define RG_5G_RX_ULG_TZ_VCM_MSK 0xe0000000
+#define RG_5G_RX_ULG_TZ_VCM_I_MSK 0x1fffffff
+#define RG_5G_RX_ULG_TZ_VCM_SFT 29
+#define RG_5G_RX_ULG_TZ_VCM_HI 31
+#define RG_5G_RX_ULG_TZ_VCM_SZ 3
+#define RG_5G_TX_DACI1ST_MSK 0x00000003
+#define RG_5G_TX_DACI1ST_I_MSK 0xfffffffc
+#define RG_5G_TX_DACI1ST_SFT 0
+#define RG_5G_TX_DACI1ST_HI 1
+#define RG_5G_TX_DACI1ST_SZ 2
+#define RG_5G_TX_DACLPF_ICOARSE_MSK 0x0000000c
+#define RG_5G_TX_DACLPF_ICOARSE_I_MSK 0xfffffff3
+#define RG_5G_TX_DACLPF_ICOARSE_SFT 2
+#define RG_5G_TX_DACLPF_ICOARSE_HI 3
+#define RG_5G_TX_DACLPF_ICOARSE_SZ 2
+#define RG_5G_TX_DACLPF_IFINE_MSK 0x00000030
+#define RG_5G_TX_DACLPF_IFINE_I_MSK 0xffffffcf
+#define RG_5G_TX_DACLPF_IFINE_SFT 4
+#define RG_5G_TX_DACLPF_IFINE_HI 5
+#define RG_5G_TX_DACLPF_IFINE_SZ 2
+#define RG_5G_TX_DACLPF_VCM_MSK 0x000000c0
+#define RG_5G_TX_DACLPF_VCM_I_MSK 0xffffff3f
+#define RG_5G_TX_DACLPF_VCM_SFT 6
+#define RG_5G_TX_DACLPF_VCM_HI 7
+#define RG_5G_TX_DACLPF_VCM_SZ 2
+#define RG_5G_TX_DAC_IBIAS_MSK 0x00000300
+#define RG_5G_TX_DAC_IBIAS_I_MSK 0xfffffcff
+#define RG_5G_TX_DAC_IBIAS_SFT 8
+#define RG_5G_TX_DAC_IBIAS_HI 9
+#define RG_5G_TX_DAC_IBIAS_SZ 2
+#define RG_5G_TX_DAC_IATTN_MSK 0x00000400
+#define RG_5G_TX_DAC_IATTN_I_MSK 0xfffffbff
+#define RG_5G_TX_DAC_IATTN_SFT 10
+#define RG_5G_TX_DAC_IATTN_HI 10
+#define RG_5G_TX_DAC_IATTN_SZ 1
+#define RG_5G_TXLPF_BOOSTI_MSK 0x00000800
+#define RG_5G_TXLPF_BOOSTI_I_MSK 0xfffff7ff
+#define RG_5G_TXLPF_BOOSTI_SFT 11
+#define RG_5G_TXLPF_BOOSTI_HI 11
+#define RG_5G_TXLPF_BOOSTI_SZ 1
+#define RG_5G_TX_DAC_RCAL_MSK 0x00003000
+#define RG_5G_TX_DAC_RCAL_I_MSK 0xffffcfff
+#define RG_5G_TX_DAC_RCAL_SFT 12
+#define RG_5G_TX_DAC_RCAL_HI 13
+#define RG_5G_TX_DAC_RCAL_SZ 2
+#define RG_5G_TX_DAC_CKEDGE_SEL_MSK 0x00004000
+#define RG_5G_TX_DAC_CKEDGE_SEL_I_MSK 0xffffbfff
+#define RG_5G_TX_DAC_CKEDGE_SEL_SFT 14
+#define RG_5G_TX_DAC_CKEDGE_SEL_HI 14
+#define RG_5G_TX_DAC_CKEDGE_SEL_SZ 1
+#define RG_5G_TX_DAC_OS_MSK 0x00070000
+#define RG_5G_TX_DAC_OS_I_MSK 0xfff8ffff
+#define RG_5G_TX_DAC_OS_SFT 16
+#define RG_5G_TX_DAC_OS_HI 18
+#define RG_5G_TX_DAC_OS_SZ 3
+#define RG_5G_TX_DAC_IOFFSET_MSK 0x00f00000
+#define RG_5G_TX_DAC_IOFFSET_I_MSK 0xff0fffff
+#define RG_5G_TX_DAC_IOFFSET_SFT 20
+#define RG_5G_TX_DAC_IOFFSET_HI 23
+#define RG_5G_TX_DAC_IOFFSET_SZ 4
+#define RG_5G_TX_DAC_QOFFSET_MSK 0x0f000000
+#define RG_5G_TX_DAC_QOFFSET_I_MSK 0xf0ffffff
+#define RG_5G_TX_DAC_QOFFSET_SFT 24
+#define RG_5G_TX_DAC_QOFFSET_HI 27
+#define RG_5G_TX_DAC_QOFFSET_SZ 4
+#define RG_SX5GB_RFCTRL_F_MSK 0x00ffffff
+#define RG_SX5GB_RFCTRL_F_I_MSK 0xff000000
+#define RG_SX5GB_RFCTRL_F_SFT 0
+#define RG_SX5GB_RFCTRL_F_HI 23
+#define RG_SX5GB_RFCTRL_F_SZ 24
+#define RG_SX5GB_RFCTRL_CH_7_0_MSK 0xff000000
+#define RG_SX5GB_RFCTRL_CH_7_0_I_MSK 0x00ffffff
+#define RG_SX5GB_RFCTRL_CH_7_0_SFT 24
+#define RG_SX5GB_RFCTRL_CH_7_0_HI 31
+#define RG_SX5GB_RFCTRL_CH_7_0_SZ 8
+#define RG_SX5GB_RFCTRL_CH_10_8_MSK 0x00000007
+#define RG_SX5GB_RFCTRL_CH_10_8_I_MSK 0xfffffff8
+#define RG_SX5GB_RFCTRL_CH_10_8_SFT 0
+#define RG_SX5GB_RFCTRL_CH_10_8_HI 2
+#define RG_SX5GB_RFCTRL_CH_10_8_SZ 3
+#define RG_SX5GB_RFCH_MAP_EN_MSK 0x00000010
+#define RG_SX5GB_RFCH_MAP_EN_I_MSK 0xffffffef
+#define RG_SX5GB_RFCH_MAP_EN_SFT 4
+#define RG_SX5GB_RFCH_MAP_EN_HI 4
+#define RG_SX5GB_RFCH_MAP_EN_SZ 1
+#define RG_SX5GB_LO_TIMES_MSK 0x00000020
+#define RG_SX5GB_LO_TIMES_I_MSK 0xffffffdf
+#define RG_SX5GB_LO_TIMES_SFT 5
+#define RG_SX5GB_LO_TIMES_HI 5
+#define RG_SX5GB_LO_TIMES_SZ 1
+#define RG_SX5GB_CHANNEL_MSK 0x0000ff00
+#define RG_SX5GB_CHANNEL_I_MSK 0xffff00ff
+#define RG_SX5GB_CHANNEL_SFT 8
+#define RG_SX5GB_CHANNEL_HI 15
+#define RG_SX5GB_CHANNEL_SZ 8
+#define RG_SX_5GB_EN_MAN_MSK 0x00000001
+#define RG_SX_5GB_EN_MAN_I_MSK 0xfffffffe
+#define RG_SX_5GB_EN_MAN_SFT 0
+#define RG_SX_5GB_EN_MAN_HI 0
+#define RG_SX_5GB_EN_MAN_SZ 1
+#define RG_SX_5GB_EN_MSK 0x00000002
+#define RG_SX_5GB_EN_I_MSK 0xfffffffd
+#define RG_SX_5GB_EN_SFT 1
+#define RG_SX_5GB_EN_HI 1
+#define RG_SX_5GB_EN_SZ 1
+#define RG_EN_SX5GB_CP_MAN_MSK 0x00000004
+#define RG_EN_SX5GB_CP_MAN_I_MSK 0xfffffffb
+#define RG_EN_SX5GB_CP_MAN_SFT 2
+#define RG_EN_SX5GB_CP_MAN_HI 2
+#define RG_EN_SX5GB_CP_MAN_SZ 1
+#define RG_EN_SX5GB_CP_MSK 0x00000008
+#define RG_EN_SX5GB_CP_I_MSK 0xfffffff7
+#define RG_EN_SX5GB_CP_SFT 3
+#define RG_EN_SX5GB_CP_HI 3
+#define RG_EN_SX5GB_CP_SZ 1
+#define RG_EN_SX5GB_DIV_MAN_MSK 0x00000010
+#define RG_EN_SX5GB_DIV_MAN_I_MSK 0xffffffef
+#define RG_EN_SX5GB_DIV_MAN_SFT 4
+#define RG_EN_SX5GB_DIV_MAN_HI 4
+#define RG_EN_SX5GB_DIV_MAN_SZ 1
+#define RG_EN_SX5GB_DIV_MSK 0x00000020
+#define RG_EN_SX5GB_DIV_I_MSK 0xffffffdf
+#define RG_EN_SX5GB_DIV_SFT 5
+#define RG_EN_SX5GB_DIV_HI 5
+#define RG_EN_SX5GB_DIV_SZ 1
+#define RG_EN_SX5GB_VCO_MAN_MSK 0x00000040
+#define RG_EN_SX5GB_VCO_MAN_I_MSK 0xffffffbf
+#define RG_EN_SX5GB_VCO_MAN_SFT 6
+#define RG_EN_SX5GB_VCO_MAN_HI 6
+#define RG_EN_SX5GB_VCO_MAN_SZ 1
+#define RG_EN_SX5GB_VCO_MSK 0x00000080
+#define RG_EN_SX5GB_VCO_I_MSK 0xffffff7f
+#define RG_EN_SX5GB_VCO_SFT 7
+#define RG_EN_SX5GB_VCO_HI 7
+#define RG_EN_SX5GB_VCO_SZ 1
+#define RG_SX5GB_PFD_RST_MAN_MSK 0x00000100
+#define RG_SX5GB_PFD_RST_MAN_I_MSK 0xfffffeff
+#define RG_SX5GB_PFD_RST_MAN_SFT 8
+#define RG_SX5GB_PFD_RST_MAN_HI 8
+#define RG_SX5GB_PFD_RST_MAN_SZ 1
+#define RG_SX5GB_PFD_RST_MSK 0x00000200
+#define RG_SX5GB_PFD_RST_I_MSK 0xfffffdff
+#define RG_SX5GB_PFD_RST_SFT 9
+#define RG_SX5GB_PFD_RST_HI 9
+#define RG_SX5GB_PFD_RST_SZ 1
+#define RG_SX5GB_UOP_MAN_MSK 0x00000400
+#define RG_SX5GB_UOP_MAN_I_MSK 0xfffffbff
+#define RG_SX5GB_UOP_MAN_SFT 10
+#define RG_SX5GB_UOP_MAN_HI 10
+#define RG_SX5GB_UOP_MAN_SZ 1
+#define RG_SX5GB_UOP_EN_MSK 0x00000800
+#define RG_SX5GB_UOP_EN_I_MSK 0xfffff7ff
+#define RG_SX5GB_UOP_EN_SFT 11
+#define RG_SX5GB_UOP_EN_HI 11
+#define RG_SX5GB_UOP_EN_SZ 1
+#define RG_EN_SX5GB_HSDIV_MAN_MSK 0x00001000
+#define RG_EN_SX5GB_HSDIV_MAN_I_MSK 0xffffefff
+#define RG_EN_SX5GB_HSDIV_MAN_SFT 12
+#define RG_EN_SX5GB_HSDIV_MAN_HI 12
+#define RG_EN_SX5GB_HSDIV_MAN_SZ 1
+#define RG_EN_SX5GB_HSDIV_MSK 0x00002000
+#define RG_EN_SX5GB_HSDIV_I_MSK 0xffffdfff
+#define RG_EN_SX5GB_HSDIV_SFT 13
+#define RG_EN_SX5GB_HSDIV_HI 13
+#define RG_EN_SX5GB_HSDIV_SZ 1
+#define RG_EN_HSDIV_OBF_SX_MAN_MSK 0x00004000
+#define RG_EN_HSDIV_OBF_SX_MAN_I_MSK 0xffffbfff
+#define RG_EN_HSDIV_OBF_SX_MAN_SFT 14
+#define RG_EN_HSDIV_OBF_SX_MAN_HI 14
+#define RG_EN_HSDIV_OBF_SX_MAN_SZ 1
+#define RG_EN_HSDIV_OBF_SX_MSK 0x00008000
+#define RG_EN_HSDIV_OBF_SX_I_MSK 0xffff7fff
+#define RG_EN_HSDIV_OBF_SX_SFT 15
+#define RG_EN_HSDIV_OBF_SX_HI 15
+#define RG_EN_HSDIV_OBF_SX_SZ 1
+#define RG_EN_HSDIV_OBF_MX_MAN_MSK 0x00010000
+#define RG_EN_HSDIV_OBF_MX_MAN_I_MSK 0xfffeffff
+#define RG_EN_HSDIV_OBF_MX_MAN_SFT 16
+#define RG_EN_HSDIV_OBF_MX_MAN_HI 16
+#define RG_EN_HSDIV_OBF_MX_MAN_SZ 1
+#define RG_EN_HSDIV_OBF_MX_MSK 0x00020000
+#define RG_EN_HSDIV_OBF_MX_I_MSK 0xfffdffff
+#define RG_EN_HSDIV_OBF_MX_SFT 17
+#define RG_EN_HSDIV_OBF_MX_HI 17
+#define RG_EN_HSDIV_OBF_MX_SZ 1
+#define RG_EN_SX_MIX_MAN_MSK 0x00040000
+#define RG_EN_SX_MIX_MAN_I_MSK 0xfffbffff
+#define RG_EN_SX_MIX_MAN_SFT 18
+#define RG_EN_SX_MIX_MAN_HI 18
+#define RG_EN_SX_MIX_MAN_SZ 1
+#define RG_EN_SX_MIX_MSK 0x00080000
+#define RG_EN_SX_MIX_I_MSK 0xfff7ffff
+#define RG_EN_SX_MIX_SFT 19
+#define RG_EN_SX_MIX_HI 19
+#define RG_EN_SX_MIX_SZ 1
+#define RG_EN_SX_REP_MAN_MSK 0x00100000
+#define RG_EN_SX_REP_MAN_I_MSK 0xffefffff
+#define RG_EN_SX_REP_MAN_SFT 20
+#define RG_EN_SX_REP_MAN_HI 20
+#define RG_EN_SX_REP_MAN_SZ 1
+#define RG_EN_SX_REP_MSK 0x00200000
+#define RG_EN_SX_REP_I_MSK 0xffdfffff
+#define RG_EN_SX_REP_SFT 21
+#define RG_EN_SX_REP_HI 21
+#define RG_EN_SX_REP_SZ 1
+#define RG_SX5GB_SBCAL_DIS_MSK 0x00400000
+#define RG_SX5GB_SBCAL_DIS_I_MSK 0xffbfffff
+#define RG_SX5GB_SBCAL_DIS_SFT 22
+#define RG_SX5GB_SBCAL_DIS_HI 22
+#define RG_SX5GB_SBCAL_DIS_SZ 1
+#define RG_SX5GB_SBCAL_2ND_DIS_MSK 0x00800000
+#define RG_SX5GB_SBCAL_2ND_DIS_I_MSK 0xff7fffff
+#define RG_SX5GB_SBCAL_2ND_DIS_SFT 23
+#define RG_SX5GB_SBCAL_2ND_DIS_HI 23
+#define RG_SX5GB_SBCAL_2ND_DIS_SZ 1
+#define RG_SX5GB_SBCAL_AW_MSK 0x01000000
+#define RG_SX5GB_SBCAL_AW_I_MSK 0xfeffffff
+#define RG_SX5GB_SBCAL_AW_SFT 24
+#define RG_SX5GB_SBCAL_AW_HI 24
+#define RG_SX5GB_SBCAL_AW_SZ 1
+#define RG_SX5GB_VOAAC_DIS_MSK 0x02000000
+#define RG_SX5GB_VOAAC_DIS_I_MSK 0xfdffffff
+#define RG_SX5GB_VOAAC_DIS_SFT 25
+#define RG_SX5GB_VOAAC_DIS_HI 25
+#define RG_SX5GB_VOAAC_DIS_SZ 1
+#define RG_SX5GB_MIXAAC_DIS_MSK 0x04000000
+#define RG_SX5GB_MIXAAC_DIS_I_MSK 0xfbffffff
+#define RG_SX5GB_MIXAAC_DIS_SFT 26
+#define RG_SX5GB_MIXAAC_DIS_HI 26
+#define RG_SX5GB_MIXAAC_DIS_SZ 1
+#define RG_SX5GB_REPAAC_DIS_MSK 0x08000000
+#define RG_SX5GB_REPAAC_DIS_I_MSK 0xf7ffffff
+#define RG_SX5GB_REPAAC_DIS_SFT 27
+#define RG_SX5GB_REPAAC_DIS_HI 27
+#define RG_SX5GB_REPAAC_DIS_SZ 1
+#define RG_SX5GB_TTL_DIS_MSK 0x10000000
+#define RG_SX5GB_TTL_DIS_I_MSK 0xefffffff
+#define RG_SX5GB_TTL_DIS_SFT 28
+#define RG_SX5GB_TTL_DIS_HI 28
+#define RG_SX5GB_TTL_DIS_SZ 1
+#define RG_SX5GB_CAL_INIT_MSK 0xe0000000
+#define RG_SX5GB_CAL_INIT_I_MSK 0x1fffffff
+#define RG_SX5GB_CAL_INIT_SFT 29
+#define RG_SX5GB_CAL_INIT_HI 31
+#define RG_SX5GB_CAL_INIT_SZ 3
+#define RG_EN_SX5GB_LDO_MAN_MSK 0x00000001
+#define RG_EN_SX5GB_LDO_MAN_I_MSK 0xfffffffe
+#define RG_EN_SX5GB_LDO_MAN_SFT 0
+#define RG_EN_SX5GB_LDO_MAN_HI 0
+#define RG_EN_SX5GB_LDO_MAN_SZ 1
+#define RG_EN_LDO_5G_CP_MSK 0x00000002
+#define RG_EN_LDO_5G_CP_I_MSK 0xfffffffd
+#define RG_EN_LDO_5G_CP_SFT 1
+#define RG_EN_LDO_5G_CP_HI 1
+#define RG_EN_LDO_5G_CP_SZ 1
+#define RG_EN_LDO_5G_DIV_MSK 0x00000004
+#define RG_EN_LDO_5G_DIV_I_MSK 0xfffffffb
+#define RG_EN_LDO_5G_DIV_SFT 2
+#define RG_EN_LDO_5G_DIV_HI 2
+#define RG_EN_LDO_5G_DIV_SZ 1
+#define RG_EN_LDO_5G_LO_MSK 0x00000008
+#define RG_EN_LDO_5G_LO_I_MSK 0xfffffff7
+#define RG_EN_LDO_5G_LO_SFT 3
+#define RG_EN_LDO_5G_LO_HI 3
+#define RG_EN_LDO_5G_LO_SZ 1
+#define RG_EN_LDO_5G_VCO_MSK 0x00000010
+#define RG_EN_LDO_5G_VCO_I_MSK 0xffffffef
+#define RG_EN_LDO_5G_VCO_SFT 4
+#define RG_EN_LDO_5G_VCO_HI 4
+#define RG_EN_LDO_5G_VCO_SZ 1
+#define RG_EN_SXMIX_INBF_MAN_MSK 0x00000040
+#define RG_EN_SXMIX_INBF_MAN_I_MSK 0xffffffbf
+#define RG_EN_SXMIX_INBF_MAN_SFT 6
+#define RG_EN_SXMIX_INBF_MAN_HI 6
+#define RG_EN_SXMIX_INBF_MAN_SZ 1
+#define RG_EN_SXMIX_INBF_MSK 0x00000080
+#define RG_EN_SXMIX_INBF_I_MSK 0xffffff7f
+#define RG_EN_SXMIX_INBF_SFT 7
+#define RG_EN_SXMIX_INBF_HI 7
+#define RG_EN_SXMIX_INBF_SZ 1
+#define RG_EN_LDO_5G_VCO_PSW_MSK 0x00000200
+#define RG_EN_LDO_5G_VCO_PSW_I_MSK 0xfffffdff
+#define RG_EN_LDO_5G_VCO_PSW_SFT 9
+#define RG_EN_LDO_5G_VCO_PSW_HI 9
+#define RG_EN_LDO_5G_VCO_PSW_SZ 1
+#define RG_EN_LDO_5G_VCO_VDD33_MSK 0x00000400
+#define RG_EN_LDO_5G_VCO_VDD33_I_MSK 0xfffffbff
+#define RG_EN_LDO_5G_VCO_VDD33_SFT 10
+#define RG_EN_LDO_5G_VCO_VDD33_HI 10
+#define RG_EN_LDO_5G_VCO_VDD33_SZ 1
+#define RG_EN_LDO_5G_CP_IQUP_MSK 0x00000800
+#define RG_EN_LDO_5G_CP_IQUP_I_MSK 0xfffff7ff
+#define RG_EN_LDO_5G_CP_IQUP_SFT 11
+#define RG_EN_LDO_5G_CP_IQUP_HI 11
+#define RG_EN_LDO_5G_CP_IQUP_SZ 1
+#define RG_EN_LDO_5G_DIV_IQUP_MSK 0x00001000
+#define RG_EN_LDO_5G_DIV_IQUP_I_MSK 0xffffefff
+#define RG_EN_LDO_5G_DIV_IQUP_SFT 12
+#define RG_EN_LDO_5G_DIV_IQUP_HI 12
+#define RG_EN_LDO_5G_DIV_IQUP_SZ 1
+#define RG_EN_LDO_5G_LO_IQUP_MSK 0x00002000
+#define RG_EN_LDO_5G_LO_IQUP_I_MSK 0xffffdfff
+#define RG_EN_LDO_5G_LO_IQUP_SFT 13
+#define RG_EN_LDO_5G_LO_IQUP_HI 13
+#define RG_EN_LDO_5G_LO_IQUP_SZ 1
+#define RG_EN_LDO_5G_VCO_IQUP_MSK 0x00004000
+#define RG_EN_LDO_5G_VCO_IQUP_I_MSK 0xffffbfff
+#define RG_EN_LDO_5G_VCO_IQUP_SFT 14
+#define RG_EN_LDO_5G_VCO_IQUP_HI 14
+#define RG_EN_LDO_5G_VCO_IQUP_SZ 1
+#define RG_SX5GB_LDO_FCOFFT_MSK 0x00380000
+#define RG_SX5GB_LDO_FCOFFT_I_MSK 0xffc7ffff
+#define RG_SX5GB_LDO_FCOFFT_SFT 19
+#define RG_SX5GB_LDO_FCOFFT_HI 21
+#define RG_SX5GB_LDO_FCOFFT_SZ 3
+#define RG_LDO_5G_CP_FC_MAN_MSK 0x00400000
+#define RG_LDO_5G_CP_FC_MAN_I_MSK 0xffbfffff
+#define RG_LDO_5G_CP_FC_MAN_SFT 22
+#define RG_LDO_5G_CP_FC_MAN_HI 22
+#define RG_LDO_5G_CP_FC_MAN_SZ 1
+#define RG_LDO_5G_CP_FC_MSK 0x00800000
+#define RG_LDO_5G_CP_FC_I_MSK 0xff7fffff
+#define RG_LDO_5G_CP_FC_SFT 23
+#define RG_LDO_5G_CP_FC_HI 23
+#define RG_LDO_5G_CP_FC_SZ 1
+#define RG_LDO_5G_DIV_FC_MAN_MSK 0x01000000
+#define RG_LDO_5G_DIV_FC_MAN_I_MSK 0xfeffffff
+#define RG_LDO_5G_DIV_FC_MAN_SFT 24
+#define RG_LDO_5G_DIV_FC_MAN_HI 24
+#define RG_LDO_5G_DIV_FC_MAN_SZ 1
+#define RG_LDO_5G_DIV_FC_MSK 0x02000000
+#define RG_LDO_5G_DIV_FC_I_MSK 0xfdffffff
+#define RG_LDO_5G_DIV_FC_SFT 25
+#define RG_LDO_5G_DIV_FC_HI 25
+#define RG_LDO_5G_DIV_FC_SZ 1
+#define RG_LDO_5G_LO_FC_MAN_MSK 0x04000000
+#define RG_LDO_5G_LO_FC_MAN_I_MSK 0xfbffffff
+#define RG_LDO_5G_LO_FC_MAN_SFT 26
+#define RG_LDO_5G_LO_FC_MAN_HI 26
+#define RG_LDO_5G_LO_FC_MAN_SZ 1
+#define RG_LDO_5G_LO_FC_MSK 0x08000000
+#define RG_LDO_5G_LO_FC_I_MSK 0xf7ffffff
+#define RG_LDO_5G_LO_FC_SFT 27
+#define RG_LDO_5G_LO_FC_HI 27
+#define RG_LDO_5G_LO_FC_SZ 1
+#define RG_LDO_5G_VCO_FC_MAN_MSK 0x10000000
+#define RG_LDO_5G_VCO_FC_MAN_I_MSK 0xefffffff
+#define RG_LDO_5G_VCO_FC_MAN_SFT 28
+#define RG_LDO_5G_VCO_FC_MAN_HI 28
+#define RG_LDO_5G_VCO_FC_MAN_SZ 1
+#define RG_LDO_5G_VCO_FC_MSK 0x20000000
+#define RG_LDO_5G_VCO_FC_I_MSK 0xdfffffff
+#define RG_LDO_5G_VCO_FC_SFT 29
+#define RG_LDO_5G_VCO_FC_HI 29
+#define RG_LDO_5G_VCO_FC_SZ 1
+#define RG_LDO_5G_VCO_RCF_MSK 0xc0000000
+#define RG_LDO_5G_VCO_RCF_I_MSK 0x3fffffff
+#define RG_LDO_5G_VCO_RCF_SFT 30
+#define RG_LDO_5G_VCO_RCF_HI 31
+#define RG_LDO_5G_VCO_RCF_SZ 2
+#define RG_SX5GB_CP_ISEL_MSK 0x0000000f
+#define RG_SX5GB_CP_ISEL_I_MSK 0xfffffff0
+#define RG_SX5GB_CP_ISEL_SFT 0
+#define RG_SX5GB_CP_ISEL_HI 3
+#define RG_SX5GB_CP_ISEL_SZ 4
+#define RG_SX5GB_CP_ISEL50U_MSK 0x00000010
+#define RG_SX5GB_CP_ISEL50U_I_MSK 0xffffffef
+#define RG_SX5GB_CP_ISEL50U_SFT 4
+#define RG_SX5GB_CP_ISEL50U_HI 4
+#define RG_SX5GB_CP_ISEL50U_SZ 1
+#define RG_SX5GB_CP_KP_DOUB_MSK 0x00000020
+#define RG_SX5GB_CP_KP_DOUB_I_MSK 0xffffffdf
+#define RG_SX5GB_CP_KP_DOUB_SFT 5
+#define RG_SX5GB_CP_KP_DOUB_HI 5
+#define RG_SX5GB_CP_KP_DOUB_SZ 1
+#define RG_SX5GB_CP_IOST_POL_MSK 0x00000080
+#define RG_SX5GB_CP_IOST_POL_I_MSK 0xffffff7f
+#define RG_SX5GB_CP_IOST_POL_SFT 7
+#define RG_SX5GB_CP_IOST_POL_HI 7
+#define RG_SX5GB_CP_IOST_POL_SZ 1
+#define RG_SX5GB_CP_IOST_MSK 0x00000700
+#define RG_SX5GB_CP_IOST_I_MSK 0xfffff8ff
+#define RG_SX5GB_CP_IOST_SFT 8
+#define RG_SX5GB_CP_IOST_HI 10
+#define RG_SX5GB_CP_IOST_SZ 3
+#define RG_SX5GB_PFD_SEL_MSK 0x00001000
+#define RG_SX5GB_PFD_SEL_I_MSK 0xffffefff
+#define RG_SX5GB_PFD_SEL_SFT 12
+#define RG_SX5GB_PFD_SEL_HI 12
+#define RG_SX5GB_PFD_SEL_SZ 1
+#define RG_SX5GB_PFD_SET_MSK 0x00002000
+#define RG_SX5GB_PFD_SET_I_MSK 0xffffdfff
+#define RG_SX5GB_PFD_SET_SFT 13
+#define RG_SX5GB_PFD_SET_HI 13
+#define RG_SX5GB_PFD_SET_SZ 1
+#define RG_SX5GB_PFD_SET1_MSK 0x00004000
+#define RG_SX5GB_PFD_SET1_I_MSK 0xffffbfff
+#define RG_SX5GB_PFD_SET1_SFT 14
+#define RG_SX5GB_PFD_SET1_HI 14
+#define RG_SX5GB_PFD_SET1_SZ 1
+#define RG_SX5GB_PFD_SET2_MSK 0x00008000
+#define RG_SX5GB_PFD_SET2_I_MSK 0xffff7fff
+#define RG_SX5GB_PFD_SET2_SFT 15
+#define RG_SX5GB_PFD_SET2_HI 15
+#define RG_SX5GB_PFD_SET2_SZ 1
+#define RG_SX5GB_PFD_TRUP_MSK 0x00010000
+#define RG_SX5GB_PFD_TRUP_I_MSK 0xfffeffff
+#define RG_SX5GB_PFD_TRUP_SFT 16
+#define RG_SX5GB_PFD_TRUP_HI 16
+#define RG_SX5GB_PFD_TRUP_SZ 1
+#define RG_SX5GB_PFD_TRDN_MSK 0x00020000
+#define RG_SX5GB_PFD_TRDN_I_MSK 0xfffdffff
+#define RG_SX5GB_PFD_TRDN_SFT 17
+#define RG_SX5GB_PFD_TRDN_HI 17
+#define RG_SX5GB_PFD_TRDN_SZ 1
+#define RG_SX5GB_PFD_TLSEL_MSK 0x00040000
+#define RG_SX5GB_PFD_TLSEL_I_MSK 0xfffbffff
+#define RG_SX5GB_PFD_TLSEL_SFT 18
+#define RG_SX5GB_PFD_TLSEL_HI 18
+#define RG_SX5GB_PFD_TLSEL_SZ 1
+#define RG_SX5GB_PFD_REF_EDGE_MSK 0x00080000
+#define RG_SX5GB_PFD_REF_EDGE_I_MSK 0xfff7ffff
+#define RG_SX5GB_PFD_REF_EDGE_SFT 19
+#define RG_SX5GB_PFD_REF_EDGE_HI 19
+#define RG_SX5GB_PFD_REF_EDGE_SZ 1
+#define RG_SX5GB_PFD_DIV_EDGE_MSK 0x00100000
+#define RG_SX5GB_PFD_DIV_EDGE_I_MSK 0xffefffff
+#define RG_SX5GB_PFD_DIV_EDGE_SFT 20
+#define RG_SX5GB_PFD_DIV_EDGE_HI 20
+#define RG_SX5GB_PFD_DIV_EDGE_SZ 1
+#define RG_SX5GB_LPF_C1_MSK 0x0000000f
+#define RG_SX5GB_LPF_C1_I_MSK 0xfffffff0
+#define RG_SX5GB_LPF_C1_SFT 0
+#define RG_SX5GB_LPF_C1_HI 3
+#define RG_SX5GB_LPF_C1_SZ 4
+#define RG_SX5GB_LPF_C2_MSK 0x000000f0
+#define RG_SX5GB_LPF_C2_I_MSK 0xffffff0f
+#define RG_SX5GB_LPF_C2_SFT 4
+#define RG_SX5GB_LPF_C2_HI 7
+#define RG_SX5GB_LPF_C2_SZ 4
+#define RG_SX5GB_LPF_C3_MSK 0x00000100
+#define RG_SX5GB_LPF_C3_I_MSK 0xfffffeff
+#define RG_SX5GB_LPF_C3_SFT 8
+#define RG_SX5GB_LPF_C3_HI 8
+#define RG_SX5GB_LPF_C3_SZ 1
+#define RG_SX5GB_LPF_R2_MSK 0x00001e00
+#define RG_SX5GB_LPF_R2_I_MSK 0xffffe1ff
+#define RG_SX5GB_LPF_R2_SFT 9
+#define RG_SX5GB_LPF_R2_HI 12
+#define RG_SX5GB_LPF_R2_SZ 4
+#define RG_SX5GB_LPF_R3_MSK 0x0000e000
+#define RG_SX5GB_LPF_R3_I_MSK 0xffff1fff
+#define RG_SX5GB_LPF_R3_SFT 13
+#define RG_SX5GB_LPF_R3_HI 15
+#define RG_SX5GB_LPF_R3_SZ 3
+#define RG_SX5GB_TTL_INIT_MSK 0x00030000
+#define RG_SX5GB_TTL_INIT_I_MSK 0xfffcffff
+#define RG_SX5GB_TTL_INIT_SFT 16
+#define RG_SX5GB_TTL_INIT_HI 17
+#define RG_SX5GB_TTL_INIT_SZ 2
+#define RG_SX5GB_TTL_FPT_MSK 0x000c0000
+#define RG_SX5GB_TTL_FPT_I_MSK 0xfff3ffff
+#define RG_SX5GB_TTL_FPT_SFT 18
+#define RG_SX5GB_TTL_FPT_HI 19
+#define RG_SX5GB_TTL_FPT_SZ 2
+#define RG_SX5GB_TTL_CPT_MSK 0x00300000
+#define RG_SX5GB_TTL_CPT_I_MSK 0xffcfffff
+#define RG_SX5GB_TTL_CPT_SFT 20
+#define RG_SX5GB_TTL_CPT_HI 21
+#define RG_SX5GB_TTL_CPT_SZ 2
+#define RG_SX5GB_TTL_ACCUM_MSK 0x00c00000
+#define RG_SX5GB_TTL_ACCUM_I_MSK 0xff3fffff
+#define RG_SX5GB_TTL_ACCUM_SFT 22
+#define RG_SX5GB_TTL_ACCUM_HI 23
+#define RG_SX5GB_TTL_ACCUM_SZ 2
+#define RG_SX5GB_TTL_SUB_MSK 0x03000000
+#define RG_SX5GB_TTL_SUB_I_MSK 0xfcffffff
+#define RG_SX5GB_TTL_SUB_SFT 24
+#define RG_SX5GB_TTL_SUB_HI 25
+#define RG_SX5GB_TTL_SUB_SZ 2
+#define RG_SX5GB_TTL_SUB_INV_MSK 0x04000000
+#define RG_SX5GB_TTL_SUB_INV_I_MSK 0xfbffffff
+#define RG_SX5GB_TTL_SUB_INV_SFT 26
+#define RG_SX5GB_TTL_SUB_INV_HI 26
+#define RG_SX5GB_TTL_SUB_INV_SZ 1
+#define RG_SX5GB_TTL_VH_MSK 0x18000000
+#define RG_SX5GB_TTL_VH_I_MSK 0xe7ffffff
+#define RG_SX5GB_TTL_VH_SFT 27
+#define RG_SX5GB_TTL_VH_HI 28
+#define RG_SX5GB_TTL_VH_SZ 2
+#define RG_SX5GB_TTL_VL_MSK 0x60000000
+#define RG_SX5GB_TTL_VL_I_MSK 0x9fffffff
+#define RG_SX5GB_TTL_VL_SFT 29
+#define RG_SX5GB_TTL_VL_HI 30
+#define RG_SX5GB_TTL_VL_SZ 2
+#define RG_SX5GB_LPF_VTUNE_TEST_MSK 0x80000000
+#define RG_SX5GB_LPF_VTUNE_TEST_I_MSK 0x7fffffff
+#define RG_SX5GB_LPF_VTUNE_TEST_SFT 31
+#define RG_SX5GB_LPF_VTUNE_TEST_HI 31
+#define RG_SX5GB_LPF_VTUNE_TEST_SZ 1
+#define RG_SX5GB_VCO_ISEL_MAN_MSK 0x00000001
+#define RG_SX5GB_VCO_ISEL_MAN_I_MSK 0xfffffffe
+#define RG_SX5GB_VCO_ISEL_MAN_SFT 0
+#define RG_SX5GB_VCO_ISEL_MAN_HI 0
+#define RG_SX5GB_VCO_ISEL_MAN_SZ 1
+#define RG_SX5GB_VCO_ISEL_MSK 0x0000001e
+#define RG_SX5GB_VCO_ISEL_I_MSK 0xffffffe1
+#define RG_SX5GB_VCO_ISEL_SFT 1
+#define RG_SX5GB_VCO_ISEL_HI 4
+#define RG_SX5GB_VCO_ISEL_SZ 4
+#define RG_SX5GB_VCO_VCCBSEL_MSK 0x000001c0
+#define RG_SX5GB_VCO_VCCBSEL_I_MSK 0xfffffe3f
+#define RG_SX5GB_VCO_VCCBSEL_SFT 6
+#define RG_SX5GB_VCO_VCCBSEL_HI 8
+#define RG_SX5GB_VCO_VCCBSEL_SZ 3
+#define RG_SX5GB_VCO_KVDOUB_MSK 0x00000200
+#define RG_SX5GB_VCO_KVDOUB_I_MSK 0xfffffdff
+#define RG_SX5GB_VCO_KVDOUB_SFT 9
+#define RG_SX5GB_VCO_KVDOUB_HI 9
+#define RG_SX5GB_VCO_KVDOUB_SZ 1
+#define RG_SX5GB_VCO_VARBSEL_MSK 0x00001800
+#define RG_SX5GB_VCO_VARBSEL_I_MSK 0xffffe7ff
+#define RG_SX5GB_VCO_VARBSEL_SFT 11
+#define RG_SX5GB_VCO_VARBSEL_HI 12
+#define RG_SX5GB_VCO_VARBSEL_SZ 2
+#define RG_SX5GB_VCO_RTAIL_SHIFT_MSK 0x00002000
+#define RG_SX5GB_VCO_RTAIL_SHIFT_I_MSK 0xffffdfff
+#define RG_SX5GB_VCO_RTAIL_SHIFT_SFT 13
+#define RG_SX5GB_VCO_RTAIL_SHIFT_HI 13
+#define RG_SX5GB_VCO_RTAIL_SHIFT_SZ 1
+#define RG_SX5GB_VCO_CS_AWH_MSK 0x00004000
+#define RG_SX5GB_VCO_CS_AWH_I_MSK 0xffffbfff
+#define RG_SX5GB_VCO_CS_AWH_SFT 14
+#define RG_SX5GB_VCO_CS_AWH_HI 14
+#define RG_SX5GB_VCO_CS_AWH_SZ 1
+#define RG_HSDIV_INBFSEL_MSK 0x00018000
+#define RG_HSDIV_INBFSEL_I_MSK 0xfffe7fff
+#define RG_HSDIV_INBFSEL_SFT 15
+#define RG_HSDIV_INBFSEL_HI 16
+#define RG_HSDIV_INBFSEL_SZ 2
+#define RG_HSDIV_OBFMX_SEL_MSK 0x00020000
+#define RG_HSDIV_OBFMX_SEL_I_MSK 0xfffdffff
+#define RG_HSDIV_OBFMX_SEL_SFT 17
+#define RG_HSDIV_OBFMX_SEL_HI 17
+#define RG_HSDIV_OBFMX_SEL_SZ 1
+#define RG_HSDIV_OBFSX_SEL_MSK 0x00040000
+#define RG_HSDIV_OBFSX_SEL_I_MSK 0xfffbffff
+#define RG_HSDIV_OBFSX_SEL_SFT 18
+#define RG_HSDIV_OBFSX_SEL_HI 18
+#define RG_HSDIV_OBFSX_SEL_SZ 1
+#define RG_HSDIV_VRSEL_MSK 0x00180000
+#define RG_HSDIV_VRSEL_I_MSK 0xffe7ffff
+#define RG_HSDIV_VRSEL_SFT 19
+#define RG_HSDIV_VRSEL_HI 20
+#define RG_HSDIV_VRSEL_SZ 2
+#define RG_SXMIX_IBIAS_SEL_MSK 0x00600000
+#define RG_SXMIX_IBIAS_SEL_I_MSK 0xff9fffff
+#define RG_SXMIX_IBIAS_SEL_SFT 21
+#define RG_SXMIX_IBIAS_SEL_HI 22
+#define RG_SXMIX_IBIAS_SEL_SZ 2
+#define RG_SXMIX_SWB_SEL_MSK 0x01800000
+#define RG_SXMIX_SWB_SEL_I_MSK 0xfe7fffff
+#define RG_SXMIX_SWB_SEL_SFT 23
+#define RG_SXMIX_SWB_SEL_HI 24
+#define RG_SXMIX_SWB_SEL_SZ 2
+#define RG_SXMIX_GMSEL_MSK 0x06000000
+#define RG_SXMIX_GMSEL_I_MSK 0xf9ffffff
+#define RG_SXMIX_GMSEL_SFT 25
+#define RG_SXMIX_GMSEL_HI 26
+#define RG_SXMIX_GMSEL_SZ 2
+#define RG_SXREP_SWB_SEL_MSK 0x18000000
+#define RG_SXREP_SWB_SEL_I_MSK 0xe7ffffff
+#define RG_SXREP_SWB_SEL_SFT 27
+#define RG_SXREP_SWB_SEL_HI 28
+#define RG_SXREP_SWB_SEL_SZ 2
+#define RG_SXREP_CSSEL_MSK 0x60000000
+#define RG_SXREP_CSSEL_I_MSK 0x9fffffff
+#define RG_SXREP_CSSEL_SFT 29
+#define RG_SXREP_CSSEL_HI 30
+#define RG_SXREP_CSSEL_SZ 2
+#define RG_EN_SX5GB_VCOMON_MSK 0x80000000
+#define RG_EN_SX5GB_VCOMON_I_MSK 0x7fffffff
+#define RG_EN_SX5GB_VCOMON_SFT 31
+#define RG_EN_SX5GB_VCOMON_HI 31
+#define RG_EN_SX5GB_VCOMON_SZ 1
+#define RG_SX5GB_DIV_PREVDD_MSK 0x0000000f
+#define RG_SX5GB_DIV_PREVDD_I_MSK 0xfffffff0
+#define RG_SX5GB_DIV_PREVDD_SFT 0
+#define RG_SX5GB_DIV_PREVDD_HI 3
+#define RG_SX5GB_DIV_PREVDD_SZ 4
+#define RG_SX5GB_DIV_PSCVDD_MSK 0x000000f0
+#define RG_SX5GB_DIV_PSCVDD_I_MSK 0xffffff0f
+#define RG_SX5GB_DIV_PSCVDD_SFT 4
+#define RG_SX5GB_DIV_PSCVDD_HI 7
+#define RG_SX5GB_DIV_PSCVDD_SZ 4
+#define RG_SX5GB_DIV_RST_H_MSK 0x00000200
+#define RG_SX5GB_DIV_RST_H_I_MSK 0xfffffdff
+#define RG_SX5GB_DIV_RST_H_SFT 9
+#define RG_SX5GB_DIV_RST_H_HI 9
+#define RG_SX5GB_DIV_RST_H_SZ 1
+#define RG_SX5GB_DIV_SDM_EDGE_MSK 0x00000400
+#define RG_SX5GB_DIV_SDM_EDGE_I_MSK 0xfffffbff
+#define RG_SX5GB_DIV_SDM_EDGE_SFT 10
+#define RG_SX5GB_DIV_SDM_EDGE_HI 10
+#define RG_SX5GB_DIV_SDM_EDGE_SZ 1
+#define RG_SX5GB_DIV_DMYBUF_EN_MSK 0x00000800
+#define RG_SX5GB_DIV_DMYBUF_EN_I_MSK 0xfffff7ff
+#define RG_SX5GB_DIV_DMYBUF_EN_SFT 11
+#define RG_SX5GB_DIV_DMYBUF_EN_HI 11
+#define RG_SX5GB_DIV_DMYBUF_EN_SZ 1
+#define RG_EN_SX5GB_MOD_MSK 0x00020000
+#define RG_EN_SX5GB_MOD_I_MSK 0xfffdffff
+#define RG_EN_SX5GB_MOD_SFT 17
+#define RG_EN_SX5GB_MOD_HI 17
+#define RG_EN_SX5GB_MOD_SZ 1
+#define RG_EN_SX5GB_DITHER_MSK 0x00040000
+#define RG_EN_SX5GB_DITHER_I_MSK 0xfffbffff
+#define RG_EN_SX5GB_DITHER_SFT 18
+#define RG_EN_SX5GB_DITHER_HI 18
+#define RG_EN_SX5GB_DITHER_SZ 1
+#define RG_SX5GB_MOD_ORDER_MSK 0x00180000
+#define RG_SX5GB_MOD_ORDER_I_MSK 0xffe7ffff
+#define RG_SX5GB_MOD_ORDER_SFT 19
+#define RG_SX5GB_MOD_ORDER_HI 20
+#define RG_SX5GB_MOD_ORDER_SZ 2
+#define RG_SX5GB_DITHER_WEIGHT_MSK 0x00600000
+#define RG_SX5GB_DITHER_WEIGHT_I_MSK 0xff9fffff
+#define RG_SX5GB_DITHER_WEIGHT_SFT 21
+#define RG_SX5GB_DITHER_WEIGHT_HI 22
+#define RG_SX5GB_DITHER_WEIGHT_SZ 2
+#define RG_SXMIX_INBF_SEL_MSK 0x03000000
+#define RG_SXMIX_INBF_SEL_I_MSK 0xfcffffff
+#define RG_SXMIX_INBF_SEL_SFT 24
+#define RG_SXMIX_INBF_SEL_HI 25
+#define RG_SXMIX_INBF_SEL_SZ 2
+#define RG_SXMIX_GMBIAS_OP1_MSK 0x04000000
+#define RG_SXMIX_GMBIAS_OP1_I_MSK 0xfbffffff
+#define RG_SXMIX_GMBIAS_OP1_SFT 26
+#define RG_SXMIX_GMBIAS_OP1_HI 26
+#define RG_SXMIX_GMBIAS_OP1_SZ 1
+#define RG_SXMIX_SWBIAS_OP1_MSK 0x08000000
+#define RG_SXMIX_SWBIAS_OP1_I_MSK 0xf7ffffff
+#define RG_SXMIX_SWBIAS_OP1_SFT 27
+#define RG_SXMIX_SWBIAS_OP1_HI 27
+#define RG_SXMIX_SWBIAS_OP1_SZ 1
+#define RG_SX5GB_SUB_SEL_MAN_MSK 0x00000001
+#define RG_SX5GB_SUB_SEL_MAN_I_MSK 0xfffffffe
+#define RG_SX5GB_SUB_SEL_MAN_SFT 0
+#define RG_SX5GB_SUB_SEL_MAN_HI 0
+#define RG_SX5GB_SUB_SEL_MAN_SZ 1
+#define RG_SX5GB_SUB_SEL_MSK 0x000001fe
+#define RG_SX5GB_SUB_SEL_I_MSK 0xfffffe01
+#define RG_SX5GB_SUB_SEL_SFT 1
+#define RG_SX5GB_SUB_SEL_HI 8
+#define RG_SX5GB_SUB_SEL_SZ 8
+#define RG_SX5GB_SUB_C0P5_DIS_MSK 0x00000200
+#define RG_SX5GB_SUB_C0P5_DIS_I_MSK 0xfffffdff
+#define RG_SX5GB_SUB_C0P5_DIS_SFT 9
+#define RG_SX5GB_SUB_C0P5_DIS_HI 9
+#define RG_SX5GB_SUB_C0P5_DIS_SZ 1
+#define RG_SX5GB_SBCAL_CT_MSK 0x00000c00
+#define RG_SX5GB_SBCAL_CT_I_MSK 0xfffff3ff
+#define RG_SX5GB_SBCAL_CT_SFT 10
+#define RG_SX5GB_SBCAL_CT_HI 11
+#define RG_SX5GB_SBCAL_CT_SZ 2
+#define RG_SX5GB_SBCAL_WT_MSK 0x00001000
+#define RG_SX5GB_SBCAL_WT_I_MSK 0xffffefff
+#define RG_SX5GB_SBCAL_WT_SFT 12
+#define RG_SX5GB_SBCAL_WT_HI 12
+#define RG_SX5GB_SBCAL_WT_SZ 1
+#define RG_SX5GB_SBCAL_DIFFMIN_MSK 0x00002000
+#define RG_SX5GB_SBCAL_DIFFMIN_I_MSK 0xffffdfff
+#define RG_SX5GB_SBCAL_DIFFMIN_SFT 13
+#define RG_SX5GB_SBCAL_DIFFMIN_HI 13
+#define RG_SX5GB_SBCAL_DIFFMIN_SZ 1
+#define RG_SX5GB_SBCAL_NTARG_MAN_MSK 0x00008000
+#define RG_SX5GB_SBCAL_NTARG_MAN_I_MSK 0xffff7fff
+#define RG_SX5GB_SBCAL_NTARG_MAN_SFT 15
+#define RG_SX5GB_SBCAL_NTARG_MAN_HI 15
+#define RG_SX5GB_SBCAL_NTARG_MAN_SZ 1
+#define RG_SX5GB_SBCAL_NTARG_MSK 0xffff0000
+#define RG_SX5GB_SBCAL_NTARG_I_MSK 0x0000ffff
+#define RG_SX5GB_SBCAL_NTARG_SFT 16
+#define RG_SX5GB_SBCAL_NTARG_HI 31
+#define RG_SX5GB_SBCAL_NTARG_SZ 16
+#define RG_SX5GB_VOAAC_TAR_MSK 0x0000000f
+#define RG_SX5GB_VOAAC_TAR_I_MSK 0xfffffff0
+#define RG_SX5GB_VOAAC_TAR_SFT 0
+#define RG_SX5GB_VOAAC_TAR_HI 3
+#define RG_SX5GB_VOAAC_TAR_SZ 4
+#define RG_VO5GB_AAC_IOST_MSK 0x00000030
+#define RG_VO5GB_AAC_IOST_I_MSK 0xffffffcf
+#define RG_VO5GB_AAC_IOST_SFT 4
+#define RG_VO5GB_AAC_IOST_HI 5
+#define RG_VO5GB_AAC_IOST_SZ 2
+#define RG_VO5GB_AAC_IMAX_MSK 0x000003c0
+#define RG_VO5GB_AAC_IMAX_I_MSK 0xfffffc3f
+#define RG_VO5GB_AAC_IMAX_SFT 6
+#define RG_VO5GB_AAC_IMAX_HI 9
+#define RG_VO5GB_AAC_IMAX_SZ 4
+#define RG_SX5GB_AAC_ACCUMH_MSK 0x00000c00
+#define RG_SX5GB_AAC_ACCUMH_I_MSK 0xfffff3ff
+#define RG_SX5GB_AAC_ACCUMH_SFT 10
+#define RG_SX5GB_AAC_ACCUMH_HI 11
+#define RG_SX5GB_AAC_ACCUMH_SZ 2
+#define RG_SX5GB_AAC_ACCUML_MSK 0x00003000
+#define RG_SX5GB_AAC_ACCUML_I_MSK 0xffffcfff
+#define RG_SX5GB_AAC_ACCUML_SFT 12
+#define RG_SX5GB_AAC_ACCUML_HI 13
+#define RG_SX5GB_AAC_ACCUML_SZ 2
+#define RG_SX5GB_AAC_INIT_MSK 0x0000c000
+#define RG_SX5GB_AAC_INIT_I_MSK 0xffff3fff
+#define RG_SX5GB_AAC_INIT_SFT 14
+#define RG_SX5GB_AAC_INIT_HI 15
+#define RG_SX5GB_AAC_INIT_SZ 2
+#define RG_SX5GB_AAC_EVA_TS_MSK 0x00030000
+#define RG_SX5GB_AAC_EVA_TS_I_MSK 0xfffcffff
+#define RG_SX5GB_AAC_EVA_TS_SFT 16
+#define RG_SX5GB_AAC_EVA_TS_HI 17
+#define RG_SX5GB_AAC_EVA_TS_SZ 2
+#define RG_SX5GB_AAC_EN_MAN_MSK 0x00040000
+#define RG_SX5GB_AAC_EN_MAN_I_MSK 0xfffbffff
+#define RG_SX5GB_AAC_EN_MAN_SFT 18
+#define RG_SX5GB_AAC_EN_MAN_HI 18
+#define RG_SX5GB_AAC_EN_MAN_SZ 1
+#define RG_SX5GB_AAC_EN_MSK 0x00080000
+#define RG_SX5GB_AAC_EN_I_MSK 0xfff7ffff
+#define RG_SX5GB_AAC_EN_SFT 19
+#define RG_SX5GB_AAC_EN_HI 19
+#define RG_SX5GB_AAC_EN_SZ 1
+#define RG_SX5GB_AAC_EVA_MAN_MSK 0x00100000
+#define RG_SX5GB_AAC_EVA_MAN_I_MSK 0xffefffff
+#define RG_SX5GB_AAC_EVA_MAN_SFT 20
+#define RG_SX5GB_AAC_EVA_MAN_HI 20
+#define RG_SX5GB_AAC_EVA_MAN_SZ 1
+#define RG_SX5GB_AAC_EVA_MSK 0x00200000
+#define RG_SX5GB_AAC_EVA_I_MSK 0xffdfffff
+#define RG_SX5GB_AAC_EVA_SFT 21
+#define RG_SX5GB_AAC_EVA_HI 21
+#define RG_SX5GB_AAC_EVA_SZ 1
+#define RG_AAC5GB_TAR_MAN_MSK 0x00400000
+#define RG_AAC5GB_TAR_MAN_I_MSK 0xffbfffff
+#define RG_AAC5GB_TAR_MAN_SFT 22
+#define RG_AAC5GB_TAR_MAN_HI 22
+#define RG_AAC5GB_TAR_MAN_SZ 1
+#define RG_AAC5GB_PDSW_EN_MAN_MSK 0x01000000
+#define RG_AAC5GB_PDSW_EN_MAN_I_MSK 0xfeffffff
+#define RG_AAC5GB_PDSW_EN_MAN_SFT 24
+#define RG_AAC5GB_PDSW_EN_MAN_HI 24
+#define RG_AAC5GB_PDSW_EN_MAN_SZ 1
+#define RG_EN_AAC5GB_VOPDSW_MSK 0x02000000
+#define RG_EN_AAC5GB_VOPDSW_I_MSK 0xfdffffff
+#define RG_EN_AAC5GB_VOPDSW_SFT 25
+#define RG_EN_AAC5GB_VOPDSW_HI 25
+#define RG_EN_AAC5GB_VOPDSW_SZ 1
+#define RG_EN_AAC5GB_MXPDSW_MSK 0x04000000
+#define RG_EN_AAC5GB_MXPDSW_I_MSK 0xfbffffff
+#define RG_EN_AAC5GB_MXPDSW_SFT 26
+#define RG_EN_AAC5GB_MXPDSW_HI 26
+#define RG_EN_AAC5GB_MXPDSW_SZ 1
+#define RG_EN_AAC5GB_RPPDSW_MSK 0x08000000
+#define RG_EN_AAC5GB_RPPDSW_I_MSK 0xf7ffffff
+#define RG_EN_AAC5GB_RPPDSW_SFT 27
+#define RG_EN_AAC5GB_RPPDSW_HI 27
+#define RG_EN_AAC5GB_RPPDSW_SZ 1
+#define RG_SX5GB_AAC_TEST_EN_MSK 0x40000000
+#define RG_SX5GB_AAC_TEST_EN_I_MSK 0xbfffffff
+#define RG_SX5GB_AAC_TEST_EN_SFT 30
+#define RG_SX5GB_AAC_TEST_EN_HI 30
+#define RG_SX5GB_AAC_TEST_EN_SZ 1
+#define RG_SX5GB_AAC_TEST_SEL_MSK 0x80000000
+#define RG_SX5GB_AAC_TEST_SEL_I_MSK 0x7fffffff
+#define RG_SX5GB_AAC_TEST_SEL_SFT 31
+#define RG_SX5GB_AAC_TEST_SEL_HI 31
+#define RG_SX5GB_AAC_TEST_SEL_SZ 1
+#define RG_SX5GB_MIXAAC_TAR_MSK 0x0000000f
+#define RG_SX5GB_MIXAAC_TAR_I_MSK 0xfffffff0
+#define RG_SX5GB_MIXAAC_TAR_SFT 0
+#define RG_SX5GB_MIXAAC_TAR_HI 3
+#define RG_SX5GB_MIXAAC_TAR_SZ 4
+#define RG_SXMIX_SCA_SEL_MAN_MSK 0x00000020
+#define RG_SXMIX_SCA_SEL_MAN_I_MSK 0xffffffdf
+#define RG_SXMIX_SCA_SEL_MAN_SFT 5
+#define RG_SXMIX_SCA_SEL_MAN_HI 5
+#define RG_SXMIX_SCA_SEL_MAN_SZ 1
+#define RG_SXMIX_SCA_SEL_MSK 0x00000fc0
+#define RG_SXMIX_SCA_SEL_I_MSK 0xfffff03f
+#define RG_SXMIX_SCA_SEL_SFT 6
+#define RG_SXMIX_SCA_SEL_HI 11
+#define RG_SXMIX_SCA_SEL_SZ 6
+#define RG_SX5GB_REPAAC_TAR_MSK 0x0001e000
+#define RG_SX5GB_REPAAC_TAR_I_MSK 0xfffe1fff
+#define RG_SX5GB_REPAAC_TAR_SFT 13
+#define RG_SX5GB_REPAAC_TAR_HI 16
+#define RG_SX5GB_REPAAC_TAR_SZ 4
+#define RG_SXREP_SCA_SEL_MAN_MSK 0x00040000
+#define RG_SXREP_SCA_SEL_MAN_I_MSK 0xfffbffff
+#define RG_SXREP_SCA_SEL_MAN_SFT 18
+#define RG_SXREP_SCA_SEL_MAN_HI 18
+#define RG_SXREP_SCA_SEL_MAN_SZ 1
+#define RG_SXREP_SCA_SEL_MSK 0x01f80000
+#define RG_SXREP_SCA_SEL_I_MSK 0xfe07ffff
+#define RG_SXREP_SCA_SEL_SFT 19
+#define RG_SXREP_SCA_SEL_HI 24
+#define RG_SXREP_SCA_SEL_SZ 6
+#define RG_5G_IDACAI_TZ0_PGAG15_MSK 0x0000003f
+#define RG_5G_IDACAI_TZ0_PGAG15_I_MSK 0xffffffc0
+#define RG_5G_IDACAI_TZ0_PGAG15_SFT 0
+#define RG_5G_IDACAI_TZ0_PGAG15_HI 5
+#define RG_5G_IDACAI_TZ0_PGAG15_SZ 6
+#define RG_5G_IDACAQ_TZ0_PGAG15_MSK 0x00003f00
+#define RG_5G_IDACAQ_TZ0_PGAG15_I_MSK 0xffffc0ff
+#define RG_5G_IDACAQ_TZ0_PGAG15_SFT 8
+#define RG_5G_IDACAQ_TZ0_PGAG15_HI 13
+#define RG_5G_IDACAQ_TZ0_PGAG15_SZ 6
+#define RG_5G_IDACAI_TZ0_PGAG14_MSK 0x003f0000
+#define RG_5G_IDACAI_TZ0_PGAG14_I_MSK 0xffc0ffff
+#define RG_5G_IDACAI_TZ0_PGAG14_SFT 16
+#define RG_5G_IDACAI_TZ0_PGAG14_HI 21
+#define RG_5G_IDACAI_TZ0_PGAG14_SZ 6
+#define RG_5G_IDACAQ_TZ0_PGAG14_MSK 0x3f000000
+#define RG_5G_IDACAQ_TZ0_PGAG14_I_MSK 0xc0ffffff
+#define RG_5G_IDACAQ_TZ0_PGAG14_SFT 24
+#define RG_5G_IDACAQ_TZ0_PGAG14_HI 29
+#define RG_5G_IDACAQ_TZ0_PGAG14_SZ 6
+#define RG_5G_IDACAI_TZ0_PGAG13_MSK 0x0000003f
+#define RG_5G_IDACAI_TZ0_PGAG13_I_MSK 0xffffffc0
+#define RG_5G_IDACAI_TZ0_PGAG13_SFT 0
+#define RG_5G_IDACAI_TZ0_PGAG13_HI 5
+#define RG_5G_IDACAI_TZ0_PGAG13_SZ 6
+#define RG_5G_IDACAQ_TZ0_PGAG13_MSK 0x00003f00
+#define RG_5G_IDACAQ_TZ0_PGAG13_I_MSK 0xffffc0ff
+#define RG_5G_IDACAQ_TZ0_PGAG13_SFT 8
+#define RG_5G_IDACAQ_TZ0_PGAG13_HI 13
+#define RG_5G_IDACAQ_TZ0_PGAG13_SZ 6
+#define RG_5G_IDACAI_TZ0_PGAG12_MSK 0x003f0000
+#define RG_5G_IDACAI_TZ0_PGAG12_I_MSK 0xffc0ffff
+#define RG_5G_IDACAI_TZ0_PGAG12_SFT 16
+#define RG_5G_IDACAI_TZ0_PGAG12_HI 21
+#define RG_5G_IDACAI_TZ0_PGAG12_SZ 6
+#define RG_5G_IDACAQ_TZ0_PGAG12_MSK 0x3f000000
+#define RG_5G_IDACAQ_TZ0_PGAG12_I_MSK 0xc0ffffff
+#define RG_5G_IDACAQ_TZ0_PGAG12_SFT 24
+#define RG_5G_IDACAQ_TZ0_PGAG12_HI 29
+#define RG_5G_IDACAQ_TZ0_PGAG12_SZ 6
+#define RG_5G_IDACAI_TZ0_PGAG11_MSK 0x0000003f
+#define RG_5G_IDACAI_TZ0_PGAG11_I_MSK 0xffffffc0
+#define RG_5G_IDACAI_TZ0_PGAG11_SFT 0
+#define RG_5G_IDACAI_TZ0_PGAG11_HI 5
+#define RG_5G_IDACAI_TZ0_PGAG11_SZ 6
+#define RG_5G_IDACAQ_TZ0_PGAG11_MSK 0x00003f00
+#define RG_5G_IDACAQ_TZ0_PGAG11_I_MSK 0xffffc0ff
+#define RG_5G_IDACAQ_TZ0_PGAG11_SFT 8
+#define RG_5G_IDACAQ_TZ0_PGAG11_HI 13
+#define RG_5G_IDACAQ_TZ0_PGAG11_SZ 6
+#define RG_5G_IDACAI_TZ0_PGAG10_MSK 0x003f0000
+#define RG_5G_IDACAI_TZ0_PGAG10_I_MSK 0xffc0ffff
+#define RG_5G_IDACAI_TZ0_PGAG10_SFT 16
+#define RG_5G_IDACAI_TZ0_PGAG10_HI 21
+#define RG_5G_IDACAI_TZ0_PGAG10_SZ 6
+#define RG_5G_IDACAQ_TZ0_PGAG10_MSK 0x3f000000
+#define RG_5G_IDACAQ_TZ0_PGAG10_I_MSK 0xc0ffffff
+#define RG_5G_IDACAQ_TZ0_PGAG10_SFT 24
+#define RG_5G_IDACAQ_TZ0_PGAG10_HI 29
+#define RG_5G_IDACAQ_TZ0_PGAG10_SZ 6
+#define RG_5G_IDACAI_TZ0_PGAG9_MSK 0x0000003f
+#define RG_5G_IDACAI_TZ0_PGAG9_I_MSK 0xffffffc0
+#define RG_5G_IDACAI_TZ0_PGAG9_SFT 0
+#define RG_5G_IDACAI_TZ0_PGAG9_HI 5
+#define RG_5G_IDACAI_TZ0_PGAG9_SZ 6
+#define RG_5G_IDACAQ_TZ0_PGAG9_MSK 0x00003f00
+#define RG_5G_IDACAQ_TZ0_PGAG9_I_MSK 0xffffc0ff
+#define RG_5G_IDACAQ_TZ0_PGAG9_SFT 8
+#define RG_5G_IDACAQ_TZ0_PGAG9_HI 13
+#define RG_5G_IDACAQ_TZ0_PGAG9_SZ 6
+#define RG_5G_IDACAI_TZ0_PGAG8_MSK 0x003f0000
+#define RG_5G_IDACAI_TZ0_PGAG8_I_MSK 0xffc0ffff
+#define RG_5G_IDACAI_TZ0_PGAG8_SFT 16
+#define RG_5G_IDACAI_TZ0_PGAG8_HI 21
+#define RG_5G_IDACAI_TZ0_PGAG8_SZ 6
+#define RG_5G_IDACAQ_TZ0_PGAG8_MSK 0x3f000000
+#define RG_5G_IDACAQ_TZ0_PGAG8_I_MSK 0xc0ffffff
+#define RG_5G_IDACAQ_TZ0_PGAG8_SFT 24
+#define RG_5G_IDACAQ_TZ0_PGAG8_HI 29
+#define RG_5G_IDACAQ_TZ0_PGAG8_SZ 6
+#define RG_5G_IDACAI_TZ0_PGAG7_MSK 0x0000003f
+#define RG_5G_IDACAI_TZ0_PGAG7_I_MSK 0xffffffc0
+#define RG_5G_IDACAI_TZ0_PGAG7_SFT 0
+#define RG_5G_IDACAI_TZ0_PGAG7_HI 5
+#define RG_5G_IDACAI_TZ0_PGAG7_SZ 6
+#define RG_5G_IDACAQ_TZ0_PGAG7_MSK 0x00003f00
+#define RG_5G_IDACAQ_TZ0_PGAG7_I_MSK 0xffffc0ff
+#define RG_5G_IDACAQ_TZ0_PGAG7_SFT 8
+#define RG_5G_IDACAQ_TZ0_PGAG7_HI 13
+#define RG_5G_IDACAQ_TZ0_PGAG7_SZ 6
+#define RG_5G_IDACAI_TZ0_PGAG6_MSK 0x003f0000
+#define RG_5G_IDACAI_TZ0_PGAG6_I_MSK 0xffc0ffff
+#define RG_5G_IDACAI_TZ0_PGAG6_SFT 16
+#define RG_5G_IDACAI_TZ0_PGAG6_HI 21
+#define RG_5G_IDACAI_TZ0_PGAG6_SZ 6
+#define RG_5G_IDACAQ_TZ0_PGAG6_MSK 0x3f000000
+#define RG_5G_IDACAQ_TZ0_PGAG6_I_MSK 0xc0ffffff
+#define RG_5G_IDACAQ_TZ0_PGAG6_SFT 24
+#define RG_5G_IDACAQ_TZ0_PGAG6_HI 29
+#define RG_5G_IDACAQ_TZ0_PGAG6_SZ 6
+#define RG_5G_IDACAI_TZ0_PGAG5_MSK 0x0000003f
+#define RG_5G_IDACAI_TZ0_PGAG5_I_MSK 0xffffffc0
+#define RG_5G_IDACAI_TZ0_PGAG5_SFT 0
+#define RG_5G_IDACAI_TZ0_PGAG5_HI 5
+#define RG_5G_IDACAI_TZ0_PGAG5_SZ 6
+#define RG_5G_IDACAQ_TZ0_PGAG5_MSK 0x00003f00
+#define RG_5G_IDACAQ_TZ0_PGAG5_I_MSK 0xffffc0ff
+#define RG_5G_IDACAQ_TZ0_PGAG5_SFT 8
+#define RG_5G_IDACAQ_TZ0_PGAG5_HI 13
+#define RG_5G_IDACAQ_TZ0_PGAG5_SZ 6
+#define RG_5G_IDACAI_TZ0_PGAG4_MSK 0x003f0000
+#define RG_5G_IDACAI_TZ0_PGAG4_I_MSK 0xffc0ffff
+#define RG_5G_IDACAI_TZ0_PGAG4_SFT 16
+#define RG_5G_IDACAI_TZ0_PGAG4_HI 21
+#define RG_5G_IDACAI_TZ0_PGAG4_SZ 6
+#define RG_5G_IDACAQ_TZ0_PGAG4_MSK 0x3f000000
+#define RG_5G_IDACAQ_TZ0_PGAG4_I_MSK 0xc0ffffff
+#define RG_5G_IDACAQ_TZ0_PGAG4_SFT 24
+#define RG_5G_IDACAQ_TZ0_PGAG4_HI 29
+#define RG_5G_IDACAQ_TZ0_PGAG4_SZ 6
+#define RG_5G_IDACAI_TZ0_PGAG3_MSK 0x0000003f
+#define RG_5G_IDACAI_TZ0_PGAG3_I_MSK 0xffffffc0
+#define RG_5G_IDACAI_TZ0_PGAG3_SFT 0
+#define RG_5G_IDACAI_TZ0_PGAG3_HI 5
+#define RG_5G_IDACAI_TZ0_PGAG3_SZ 6
+#define RG_5G_IDACAQ_TZ0_PGAG3_MSK 0x00003f00
+#define RG_5G_IDACAQ_TZ0_PGAG3_I_MSK 0xffffc0ff
+#define RG_5G_IDACAQ_TZ0_PGAG3_SFT 8
+#define RG_5G_IDACAQ_TZ0_PGAG3_HI 13
+#define RG_5G_IDACAQ_TZ0_PGAG3_SZ 6
+#define RG_5G_IDACAI_TZ0_PGAG2_MSK 0x003f0000
+#define RG_5G_IDACAI_TZ0_PGAG2_I_MSK 0xffc0ffff
+#define RG_5G_IDACAI_TZ0_PGAG2_SFT 16
+#define RG_5G_IDACAI_TZ0_PGAG2_HI 21
+#define RG_5G_IDACAI_TZ0_PGAG2_SZ 6
+#define RG_5G_IDACAQ_TZ0_PGAG2_MSK 0x3f000000
+#define RG_5G_IDACAQ_TZ0_PGAG2_I_MSK 0xc0ffffff
+#define RG_5G_IDACAQ_TZ0_PGAG2_SFT 24
+#define RG_5G_IDACAQ_TZ0_PGAG2_HI 29
+#define RG_5G_IDACAQ_TZ0_PGAG2_SZ 6
+#define RG_5G_IDACAI_TZ0_PGAG1_MSK 0x0000003f
+#define RG_5G_IDACAI_TZ0_PGAG1_I_MSK 0xffffffc0
+#define RG_5G_IDACAI_TZ0_PGAG1_SFT 0
+#define RG_5G_IDACAI_TZ0_PGAG1_HI 5
+#define RG_5G_IDACAI_TZ0_PGAG1_SZ 6
+#define RG_5G_IDACAQ_TZ0_PGAG1_MSK 0x00003f00
+#define RG_5G_IDACAQ_TZ0_PGAG1_I_MSK 0xffffc0ff
+#define RG_5G_IDACAQ_TZ0_PGAG1_SFT 8
+#define RG_5G_IDACAQ_TZ0_PGAG1_HI 13
+#define RG_5G_IDACAQ_TZ0_PGAG1_SZ 6
+#define RG_5G_IDACAI_TZ0_PGAG0_MSK 0x003f0000
+#define RG_5G_IDACAI_TZ0_PGAG0_I_MSK 0xffc0ffff
+#define RG_5G_IDACAI_TZ0_PGAG0_SFT 16
+#define RG_5G_IDACAI_TZ0_PGAG0_HI 21
+#define RG_5G_IDACAI_TZ0_PGAG0_SZ 6
+#define RG_5G_IDACAQ_TZ0_PGAG0_MSK 0x3f000000
+#define RG_5G_IDACAQ_TZ0_PGAG0_I_MSK 0xc0ffffff
+#define RG_5G_IDACAQ_TZ0_PGAG0_SFT 24
+#define RG_5G_IDACAQ_TZ0_PGAG0_HI 29
+#define RG_5G_IDACAQ_TZ0_PGAG0_SZ 6
+#define RG_5G_IDACAI_TZ1_PGAG15_MSK 0x0000003f
+#define RG_5G_IDACAI_TZ1_PGAG15_I_MSK 0xffffffc0
+#define RG_5G_IDACAI_TZ1_PGAG15_SFT 0
+#define RG_5G_IDACAI_TZ1_PGAG15_HI 5
+#define RG_5G_IDACAI_TZ1_PGAG15_SZ 6
+#define RG_5G_IDACAQ_TZ1_PGAG15_MSK 0x00003f00
+#define RG_5G_IDACAQ_TZ1_PGAG15_I_MSK 0xffffc0ff
+#define RG_5G_IDACAQ_TZ1_PGAG15_SFT 8
+#define RG_5G_IDACAQ_TZ1_PGAG15_HI 13
+#define RG_5G_IDACAQ_TZ1_PGAG15_SZ 6
+#define RG_5G_IDACAI_TZ1_PGAG14_MSK 0x003f0000
+#define RG_5G_IDACAI_TZ1_PGAG14_I_MSK 0xffc0ffff
+#define RG_5G_IDACAI_TZ1_PGAG14_SFT 16
+#define RG_5G_IDACAI_TZ1_PGAG14_HI 21
+#define RG_5G_IDACAI_TZ1_PGAG14_SZ 6
+#define RG_5G_IDACAQ_TZ1_PGAG14_MSK 0x3f000000
+#define RG_5G_IDACAQ_TZ1_PGAG14_I_MSK 0xc0ffffff
+#define RG_5G_IDACAQ_TZ1_PGAG14_SFT 24
+#define RG_5G_IDACAQ_TZ1_PGAG14_HI 29
+#define RG_5G_IDACAQ_TZ1_PGAG14_SZ 6
+#define RG_5G_IDACAI_TZ1_PGAG13_MSK 0x0000003f
+#define RG_5G_IDACAI_TZ1_PGAG13_I_MSK 0xffffffc0
+#define RG_5G_IDACAI_TZ1_PGAG13_SFT 0
+#define RG_5G_IDACAI_TZ1_PGAG13_HI 5
+#define RG_5G_IDACAI_TZ1_PGAG13_SZ 6
+#define RG_5G_IDACAQ_TZ1_PGAG13_MSK 0x00003f00
+#define RG_5G_IDACAQ_TZ1_PGAG13_I_MSK 0xffffc0ff
+#define RG_5G_IDACAQ_TZ1_PGAG13_SFT 8
+#define RG_5G_IDACAQ_TZ1_PGAG13_HI 13
+#define RG_5G_IDACAQ_TZ1_PGAG13_SZ 6
+#define RG_5G_IDACAI_TZ1_PGAG12_MSK 0x003f0000
+#define RG_5G_IDACAI_TZ1_PGAG12_I_MSK 0xffc0ffff
+#define RG_5G_IDACAI_TZ1_PGAG12_SFT 16
+#define RG_5G_IDACAI_TZ1_PGAG12_HI 21
+#define RG_5G_IDACAI_TZ1_PGAG12_SZ 6
+#define RG_5G_IDACAQ_TZ1_PGAG12_MSK 0x3f000000
+#define RG_5G_IDACAQ_TZ1_PGAG12_I_MSK 0xc0ffffff
+#define RG_5G_IDACAQ_TZ1_PGAG12_SFT 24
+#define RG_5G_IDACAQ_TZ1_PGAG12_HI 29
+#define RG_5G_IDACAQ_TZ1_PGAG12_SZ 6
+#define RG_5G_IDACAI_TZ1_PGAG11_MSK 0x0000003f
+#define RG_5G_IDACAI_TZ1_PGAG11_I_MSK 0xffffffc0
+#define RG_5G_IDACAI_TZ1_PGAG11_SFT 0
+#define RG_5G_IDACAI_TZ1_PGAG11_HI 5
+#define RG_5G_IDACAI_TZ1_PGAG11_SZ 6
+#define RG_5G_IDACAQ_TZ1_PGAG11_MSK 0x00003f00
+#define RG_5G_IDACAQ_TZ1_PGAG11_I_MSK 0xffffc0ff
+#define RG_5G_IDACAQ_TZ1_PGAG11_SFT 8
+#define RG_5G_IDACAQ_TZ1_PGAG11_HI 13
+#define RG_5G_IDACAQ_TZ1_PGAG11_SZ 6
+#define RG_5G_IDACAI_TZ1_PGAG10_MSK 0x003f0000
+#define RG_5G_IDACAI_TZ1_PGAG10_I_MSK 0xffc0ffff
+#define RG_5G_IDACAI_TZ1_PGAG10_SFT 16
+#define RG_5G_IDACAI_TZ1_PGAG10_HI 21
+#define RG_5G_IDACAI_TZ1_PGAG10_SZ 6
+#define RG_5G_IDACAQ_TZ1_PGAG10_MSK 0x3f000000
+#define RG_5G_IDACAQ_TZ1_PGAG10_I_MSK 0xc0ffffff
+#define RG_5G_IDACAQ_TZ1_PGAG10_SFT 24
+#define RG_5G_IDACAQ_TZ1_PGAG10_HI 29
+#define RG_5G_IDACAQ_TZ1_PGAG10_SZ 6
+#define RG_5G_IDACAI_TZ1_PGAG9_MSK 0x0000003f
+#define RG_5G_IDACAI_TZ1_PGAG9_I_MSK 0xffffffc0
+#define RG_5G_IDACAI_TZ1_PGAG9_SFT 0
+#define RG_5G_IDACAI_TZ1_PGAG9_HI 5
+#define RG_5G_IDACAI_TZ1_PGAG9_SZ 6
+#define RG_5G_IDACAQ_TZ1_PGAG9_MSK 0x00003f00
+#define RG_5G_IDACAQ_TZ1_PGAG9_I_MSK 0xffffc0ff
+#define RG_5G_IDACAQ_TZ1_PGAG9_SFT 8
+#define RG_5G_IDACAQ_TZ1_PGAG9_HI 13
+#define RG_5G_IDACAQ_TZ1_PGAG9_SZ 6
+#define RG_5G_IDACAI_TZ1_PGAG8_MSK 0x003f0000
+#define RG_5G_IDACAI_TZ1_PGAG8_I_MSK 0xffc0ffff
+#define RG_5G_IDACAI_TZ1_PGAG8_SFT 16
+#define RG_5G_IDACAI_TZ1_PGAG8_HI 21
+#define RG_5G_IDACAI_TZ1_PGAG8_SZ 6
+#define RG_5G_IDACAQ_TZ1_PGAG8_MSK 0x3f000000
+#define RG_5G_IDACAQ_TZ1_PGAG8_I_MSK 0xc0ffffff
+#define RG_5G_IDACAQ_TZ1_PGAG8_SFT 24
+#define RG_5G_IDACAQ_TZ1_PGAG8_HI 29
+#define RG_5G_IDACAQ_TZ1_PGAG8_SZ 6
+#define RG_5G_IDACAI_TZ1_PGAG7_MSK 0x0000003f
+#define RG_5G_IDACAI_TZ1_PGAG7_I_MSK 0xffffffc0
+#define RG_5G_IDACAI_TZ1_PGAG7_SFT 0
+#define RG_5G_IDACAI_TZ1_PGAG7_HI 5
+#define RG_5G_IDACAI_TZ1_PGAG7_SZ 6
+#define RG_5G_IDACAQ_TZ1_PGAG7_MSK 0x00003f00
+#define RG_5G_IDACAQ_TZ1_PGAG7_I_MSK 0xffffc0ff
+#define RG_5G_IDACAQ_TZ1_PGAG7_SFT 8
+#define RG_5G_IDACAQ_TZ1_PGAG7_HI 13
+#define RG_5G_IDACAQ_TZ1_PGAG7_SZ 6
+#define RG_5G_IDACAI_TZ1_PGAG6_MSK 0x003f0000
+#define RG_5G_IDACAI_TZ1_PGAG6_I_MSK 0xffc0ffff
+#define RG_5G_IDACAI_TZ1_PGAG6_SFT 16
+#define RG_5G_IDACAI_TZ1_PGAG6_HI 21
+#define RG_5G_IDACAI_TZ1_PGAG6_SZ 6
+#define RG_5G_IDACAQ_TZ1_PGAG6_MSK 0x3f000000
+#define RG_5G_IDACAQ_TZ1_PGAG6_I_MSK 0xc0ffffff
+#define RG_5G_IDACAQ_TZ1_PGAG6_SFT 24
+#define RG_5G_IDACAQ_TZ1_PGAG6_HI 29
+#define RG_5G_IDACAQ_TZ1_PGAG6_SZ 6
+#define RG_5G_IDACAI_TZ1_PGAG5_MSK 0x0000003f
+#define RG_5G_IDACAI_TZ1_PGAG5_I_MSK 0xffffffc0
+#define RG_5G_IDACAI_TZ1_PGAG5_SFT 0
+#define RG_5G_IDACAI_TZ1_PGAG5_HI 5
+#define RG_5G_IDACAI_TZ1_PGAG5_SZ 6
+#define RG_5G_IDACAQ_TZ1_PGAG5_MSK 0x00003f00
+#define RG_5G_IDACAQ_TZ1_PGAG5_I_MSK 0xffffc0ff
+#define RG_5G_IDACAQ_TZ1_PGAG5_SFT 8
+#define RG_5G_IDACAQ_TZ1_PGAG5_HI 13
+#define RG_5G_IDACAQ_TZ1_PGAG5_SZ 6
+#define RG_5G_IDACAI_TZ1_PGAG4_MSK 0x003f0000
+#define RG_5G_IDACAI_TZ1_PGAG4_I_MSK 0xffc0ffff
+#define RG_5G_IDACAI_TZ1_PGAG4_SFT 16
+#define RG_5G_IDACAI_TZ1_PGAG4_HI 21
+#define RG_5G_IDACAI_TZ1_PGAG4_SZ 6
+#define RG_5G_IDACAQ_TZ1_PGAG4_MSK 0x3f000000
+#define RG_5G_IDACAQ_TZ1_PGAG4_I_MSK 0xc0ffffff
+#define RG_5G_IDACAQ_TZ1_PGAG4_SFT 24
+#define RG_5G_IDACAQ_TZ1_PGAG4_HI 29
+#define RG_5G_IDACAQ_TZ1_PGAG4_SZ 6
+#define RG_5G_IDACAI_TZ1_PGAG3_MSK 0x0000003f
+#define RG_5G_IDACAI_TZ1_PGAG3_I_MSK 0xffffffc0
+#define RG_5G_IDACAI_TZ1_PGAG3_SFT 0
+#define RG_5G_IDACAI_TZ1_PGAG3_HI 5
+#define RG_5G_IDACAI_TZ1_PGAG3_SZ 6
+#define RG_5G_IDACAQ_TZ1_PGAG3_MSK 0x00003f00
+#define RG_5G_IDACAQ_TZ1_PGAG3_I_MSK 0xffffc0ff
+#define RG_5G_IDACAQ_TZ1_PGAG3_SFT 8
+#define RG_5G_IDACAQ_TZ1_PGAG3_HI 13
+#define RG_5G_IDACAQ_TZ1_PGAG3_SZ 6
+#define RG_5G_IDACAI_TZ1_PGAG2_MSK 0x003f0000
+#define RG_5G_IDACAI_TZ1_PGAG2_I_MSK 0xffc0ffff
+#define RG_5G_IDACAI_TZ1_PGAG2_SFT 16
+#define RG_5G_IDACAI_TZ1_PGAG2_HI 21
+#define RG_5G_IDACAI_TZ1_PGAG2_SZ 6
+#define RG_5G_IDACAQ_TZ1_PGAG2_MSK 0x3f000000
+#define RG_5G_IDACAQ_TZ1_PGAG2_I_MSK 0xc0ffffff
+#define RG_5G_IDACAQ_TZ1_PGAG2_SFT 24
+#define RG_5G_IDACAQ_TZ1_PGAG2_HI 29
+#define RG_5G_IDACAQ_TZ1_PGAG2_SZ 6
+#define RG_5G_IDACAI_TZ1_PGAG1_MSK 0x0000003f
+#define RG_5G_IDACAI_TZ1_PGAG1_I_MSK 0xffffffc0
+#define RG_5G_IDACAI_TZ1_PGAG1_SFT 0
+#define RG_5G_IDACAI_TZ1_PGAG1_HI 5
+#define RG_5G_IDACAI_TZ1_PGAG1_SZ 6
+#define RG_5G_IDACAQ_TZ1_PGAG1_MSK 0x00003f00
+#define RG_5G_IDACAQ_TZ1_PGAG1_I_MSK 0xffffc0ff
+#define RG_5G_IDACAQ_TZ1_PGAG1_SFT 8
+#define RG_5G_IDACAQ_TZ1_PGAG1_HI 13
+#define RG_5G_IDACAQ_TZ1_PGAG1_SZ 6
+#define RG_5G_IDACAI_TZ1_PGAG0_MSK 0x003f0000
+#define RG_5G_IDACAI_TZ1_PGAG0_I_MSK 0xffc0ffff
+#define RG_5G_IDACAI_TZ1_PGAG0_SFT 16
+#define RG_5G_IDACAI_TZ1_PGAG0_HI 21
+#define RG_5G_IDACAI_TZ1_PGAG0_SZ 6
+#define RG_5G_IDACAQ_TZ1_PGAG0_MSK 0x3f000000
+#define RG_5G_IDACAQ_TZ1_PGAG0_I_MSK 0xc0ffffff
+#define RG_5G_IDACAQ_TZ1_PGAG0_SFT 24
+#define RG_5G_IDACAQ_TZ1_PGAG0_HI 29
+#define RG_5G_IDACAQ_TZ1_PGAG0_SZ 6
+#define RG_5G_IDACAI_TZ0_COARSE4_MSK 0x0000003f
+#define RG_5G_IDACAI_TZ0_COARSE4_I_MSK 0xffffffc0
+#define RG_5G_IDACAI_TZ0_COARSE4_SFT 0
+#define RG_5G_IDACAI_TZ0_COARSE4_HI 5
+#define RG_5G_IDACAI_TZ0_COARSE4_SZ 6
+#define RG_5G_IDACAQ_TZ0_COARSE4_MSK 0x00003f00
+#define RG_5G_IDACAQ_TZ0_COARSE4_I_MSK 0xffffc0ff
+#define RG_5G_IDACAQ_TZ0_COARSE4_SFT 8
+#define RG_5G_IDACAQ_TZ0_COARSE4_HI 13
+#define RG_5G_IDACAQ_TZ0_COARSE4_SZ 6
+#define RG_5G_IDACAI_TZ0_COARSE3_MSK 0x003f0000
+#define RG_5G_IDACAI_TZ0_COARSE3_I_MSK 0xffc0ffff
+#define RG_5G_IDACAI_TZ0_COARSE3_SFT 16
+#define RG_5G_IDACAI_TZ0_COARSE3_HI 21
+#define RG_5G_IDACAI_TZ0_COARSE3_SZ 6
+#define RG_5G_IDACAQ_TZ0_COARSE3_MSK 0x3f000000
+#define RG_5G_IDACAQ_TZ0_COARSE3_I_MSK 0xc0ffffff
+#define RG_5G_IDACAQ_TZ0_COARSE3_SFT 24
+#define RG_5G_IDACAQ_TZ0_COARSE3_HI 29
+#define RG_5G_IDACAQ_TZ0_COARSE3_SZ 6
+#define RG_5G_IDACAI_TZ0_COARSE2_MSK 0x0000003f
+#define RG_5G_IDACAI_TZ0_COARSE2_I_MSK 0xffffffc0
+#define RG_5G_IDACAI_TZ0_COARSE2_SFT 0
+#define RG_5G_IDACAI_TZ0_COARSE2_HI 5
+#define RG_5G_IDACAI_TZ0_COARSE2_SZ 6
+#define RG_5G_IDACAQ_TZ0_COARSE2_MSK 0x00003f00
+#define RG_5G_IDACAQ_TZ0_COARSE2_I_MSK 0xffffc0ff
+#define RG_5G_IDACAQ_TZ0_COARSE2_SFT 8
+#define RG_5G_IDACAQ_TZ0_COARSE2_HI 13
+#define RG_5G_IDACAQ_TZ0_COARSE2_SZ 6
+#define RG_5G_IDACAI_TZ0_COARSE1_MSK 0x003f0000
+#define RG_5G_IDACAI_TZ0_COARSE1_I_MSK 0xffc0ffff
+#define RG_5G_IDACAI_TZ0_COARSE1_SFT 16
+#define RG_5G_IDACAI_TZ0_COARSE1_HI 21
+#define RG_5G_IDACAI_TZ0_COARSE1_SZ 6
+#define RG_5G_IDACAQ_TZ0_COARSE1_MSK 0x3f000000
+#define RG_5G_IDACAQ_TZ0_COARSE1_I_MSK 0xc0ffffff
+#define RG_5G_IDACAQ_TZ0_COARSE1_SFT 24
+#define RG_5G_IDACAQ_TZ0_COARSE1_HI 29
+#define RG_5G_IDACAQ_TZ0_COARSE1_SZ 6
+#define RG_5G_IDACAI_TZ0_COARSE0_MSK 0x0000003f
+#define RG_5G_IDACAI_TZ0_COARSE0_I_MSK 0xffffffc0
+#define RG_5G_IDACAI_TZ0_COARSE0_SFT 0
+#define RG_5G_IDACAI_TZ0_COARSE0_HI 5
+#define RG_5G_IDACAI_TZ0_COARSE0_SZ 6
+#define RG_5G_IDACAQ_TZ0_COARSE0_MSK 0x00003f00
+#define RG_5G_IDACAQ_TZ0_COARSE0_I_MSK 0xffffc0ff
+#define RG_5G_IDACAQ_TZ0_COARSE0_SFT 8
+#define RG_5G_IDACAQ_TZ0_COARSE0_HI 13
+#define RG_5G_IDACAQ_TZ0_COARSE0_SZ 6
+#define RG_5G_IDACAI_TZ1_COARSE4_MSK 0x003f0000
+#define RG_5G_IDACAI_TZ1_COARSE4_I_MSK 0xffc0ffff
+#define RG_5G_IDACAI_TZ1_COARSE4_SFT 16
+#define RG_5G_IDACAI_TZ1_COARSE4_HI 21
+#define RG_5G_IDACAI_TZ1_COARSE4_SZ 6
+#define RG_5G_IDACAQ_TZ1_COARSE4_MSK 0x3f000000
+#define RG_5G_IDACAQ_TZ1_COARSE4_I_MSK 0xc0ffffff
+#define RG_5G_IDACAQ_TZ1_COARSE4_SFT 24
+#define RG_5G_IDACAQ_TZ1_COARSE4_HI 29
+#define RG_5G_IDACAQ_TZ1_COARSE4_SZ 6
+#define RG_5G_IDACAI_TZ1_COARSE3_MSK 0x0000003f
+#define RG_5G_IDACAI_TZ1_COARSE3_I_MSK 0xffffffc0
+#define RG_5G_IDACAI_TZ1_COARSE3_SFT 0
+#define RG_5G_IDACAI_TZ1_COARSE3_HI 5
+#define RG_5G_IDACAI_TZ1_COARSE3_SZ 6
+#define RG_5G_IDACAQ_TZ1_COARSE3_MSK 0x00003f00
+#define RG_5G_IDACAQ_TZ1_COARSE3_I_MSK 0xffffc0ff
+#define RG_5G_IDACAQ_TZ1_COARSE3_SFT 8
+#define RG_5G_IDACAQ_TZ1_COARSE3_HI 13
+#define RG_5G_IDACAQ_TZ1_COARSE3_SZ 6
+#define RG_5G_IDACAI_TZ1_COARSE2_MSK 0x003f0000
+#define RG_5G_IDACAI_TZ1_COARSE2_I_MSK 0xffc0ffff
+#define RG_5G_IDACAI_TZ1_COARSE2_SFT 16
+#define RG_5G_IDACAI_TZ1_COARSE2_HI 21
+#define RG_5G_IDACAI_TZ1_COARSE2_SZ 6
+#define RG_5G_IDACAQ_TZ1_COARSE2_MSK 0x3f000000
+#define RG_5G_IDACAQ_TZ1_COARSE2_I_MSK 0xc0ffffff
+#define RG_5G_IDACAQ_TZ1_COARSE2_SFT 24
+#define RG_5G_IDACAQ_TZ1_COARSE2_HI 29
+#define RG_5G_IDACAQ_TZ1_COARSE2_SZ 6
+#define RG_5G_IDACAI_TZ1_COARSE1_MSK 0x0000003f
+#define RG_5G_IDACAI_TZ1_COARSE1_I_MSK 0xffffffc0
+#define RG_5G_IDACAI_TZ1_COARSE1_SFT 0
+#define RG_5G_IDACAI_TZ1_COARSE1_HI 5
+#define RG_5G_IDACAI_TZ1_COARSE1_SZ 6
+#define RG_5G_IDACAQ_TZ1_COARSE1_MSK 0x00003f00
+#define RG_5G_IDACAQ_TZ1_COARSE1_I_MSK 0xffffc0ff
+#define RG_5G_IDACAQ_TZ1_COARSE1_SFT 8
+#define RG_5G_IDACAQ_TZ1_COARSE1_HI 13
+#define RG_5G_IDACAQ_TZ1_COARSE1_SZ 6
+#define RG_5G_IDACAI_TZ1_COARSE0_MSK 0x003f0000
+#define RG_5G_IDACAI_TZ1_COARSE0_I_MSK 0xffc0ffff
+#define RG_5G_IDACAI_TZ1_COARSE0_SFT 16
+#define RG_5G_IDACAI_TZ1_COARSE0_HI 21
+#define RG_5G_IDACAI_TZ1_COARSE0_SZ 6
+#define RG_5G_IDACAQ_TZ1_COARSE0_MSK 0x3f000000
+#define RG_5G_IDACAQ_TZ1_COARSE0_I_MSK 0xc0ffffff
+#define RG_5G_IDACAQ_TZ1_COARSE0_SFT 24
+#define RG_5G_IDACAQ_TZ1_COARSE0_HI 29
+#define RG_5G_IDACAQ_TZ1_COARSE0_SZ 6
+#define RG_SX5GB_DELAY_MSK 0x0000000f
+#define RG_SX5GB_DELAY_I_MSK 0xfffffff0
+#define RG_SX5GB_DELAY_SFT 0
+#define RG_SX5GB_DELAY_HI 3
+#define RG_SX5GB_DELAY_SZ 4
+#define RG_5G_TXDAC_DELAY_MSK 0x000000f0
+#define RG_5G_TXDAC_DELAY_I_MSK 0xffffff0f
+#define RG_5G_TXDAC_DELAY_SFT 4
+#define RG_5G_TXDAC_DELAY_HI 7
+#define RG_5G_TXDAC_DELAY_SZ 4
+#define RG_5G_TXRF_DELAY_MSK 0x00000f00
+#define RG_5G_TXRF_DELAY_I_MSK 0xfffff0ff
+#define RG_5G_TXRF_DELAY_SFT 8
+#define RG_5G_TXRF_DELAY_HI 11
+#define RG_5G_TXRF_DELAY_SZ 4
+#define RG_5G_TXPA_DELAY_MSK 0x0000f000
+#define RG_5G_TXPA_DELAY_I_MSK 0xffff0fff
+#define RG_5G_TXPA_DELAY_SFT 12
+#define RG_5G_TXPA_DELAY_HI 15
+#define RG_5G_TXPA_DELAY_SZ 4
+#define RG_5G_RXRF_DELAY_MSK 0x000f0000
+#define RG_5G_RXRF_DELAY_I_MSK 0xfff0ffff
+#define RG_5G_RXRF_DELAY_SFT 16
+#define RG_5G_RXRF_DELAY_HI 19
+#define RG_5G_RXRF_DELAY_SZ 4
+#define RG_5G_TXDAC_T2R_DELAY_MSK 0x0000001f
+#define RG_5G_TXDAC_T2R_DELAY_I_MSK 0xffffffe0
+#define RG_5G_TXDAC_T2R_DELAY_SFT 0
+#define RG_5G_TXDAC_T2R_DELAY_HI 4
+#define RG_5G_TXDAC_T2R_DELAY_SZ 5
+#define RG_5G_TXRF_T2R_DELAY_MSK 0x00001f00
+#define RG_5G_TXRF_T2R_DELAY_I_MSK 0xffffe0ff
+#define RG_5G_TXRF_T2R_DELAY_SFT 8
+#define RG_5G_TXRF_T2R_DELAY_HI 12
+#define RG_5G_TXRF_T2R_DELAY_SZ 5
+#define RG_5G_TXPA_T2R_DELAY_MSK 0x001f0000
+#define RG_5G_TXPA_T2R_DELAY_I_MSK 0xffe0ffff
+#define RG_5G_TXPA_T2R_DELAY_SFT 16
+#define RG_5G_TXPA_T2R_DELAY_HI 20
+#define RG_5G_TXPA_T2R_DELAY_SZ 5
+#define RG_5G_RXRF_T2R_DELAY_MSK 0x1f000000
+#define RG_5G_RXRF_T2R_DELAY_I_MSK 0xe0ffffff
+#define RG_5G_RXRF_T2R_DELAY_SFT 24
+#define RG_5G_RXRF_T2R_DELAY_HI 28
+#define RG_5G_RXRF_T2R_DELAY_SZ 5
+#define RG_5G_TXDAC_R2T_DELAY_MSK 0x0000001f
+#define RG_5G_TXDAC_R2T_DELAY_I_MSK 0xffffffe0
+#define RG_5G_TXDAC_R2T_DELAY_SFT 0
+#define RG_5G_TXDAC_R2T_DELAY_HI 4
+#define RG_5G_TXDAC_R2T_DELAY_SZ 5
+#define RG_5G_TXRF_R2T_DELAY_MSK 0x00001f00
+#define RG_5G_TXRF_R2T_DELAY_I_MSK 0xffffe0ff
+#define RG_5G_TXRF_R2T_DELAY_SFT 8
+#define RG_5G_TXRF_R2T_DELAY_HI 12
+#define RG_5G_TXRF_R2T_DELAY_SZ 5
+#define RG_5G_TXPA_R2T_DELAY_MSK 0x001f0000
+#define RG_5G_TXPA_R2T_DELAY_I_MSK 0xffe0ffff
+#define RG_5G_TXPA_R2T_DELAY_SFT 16
+#define RG_5G_TXPA_R2T_DELAY_HI 20
+#define RG_5G_TXPA_R2T_DELAY_SZ 5
+#define RG_5G_RXRF_R2T_DELAY_MSK 0x1f000000
+#define RG_5G_RXRF_R2T_DELAY_I_MSK 0xe0ffffff
+#define RG_5G_RXRF_R2T_DELAY_SFT 24
+#define RG_5G_RXRF_R2T_DELAY_HI 28
+#define RG_5G_RXRF_R2T_DELAY_SZ 5
+#define RG_5G_RX_DCCAL_DELAY_MSK 0x00000007
+#define RG_5G_RX_DCCAL_DELAY_I_MSK 0xfffffff8
+#define RG_5G_RX_DCCAL_DELAY_SFT 0
+#define RG_5G_RX_DCCAL_DELAY_HI 2
+#define RG_5G_RX_DCCAL_DELAY_SZ 3
+#define RG_5G_TX_DCCAL_DELAY_MSK 0x00000700
+#define RG_5G_TX_DCCAL_DELAY_I_MSK 0xfffff8ff
+#define RG_5G_TX_DCCAL_DELAY_SFT 8
+#define RG_5G_TX_DCCAL_DELAY_HI 10
+#define RG_5G_TX_DCCAL_DELAY_SZ 3
+#define RG_5G_TX_IQCAL_DELAY_MSK 0x00007000
+#define RG_5G_TX_IQCAL_DELAY_I_MSK 0xffff8fff
+#define RG_5G_TX_IQCAL_DELAY_SFT 12
+#define RG_5G_TX_IQCAL_DELAY_HI 14
+#define RG_5G_TX_IQCAL_DELAY_SZ 3
+#define RG_5G_RX_IQCAL_DELAY_MSK 0x00070000
+#define RG_5G_RX_IQCAL_DELAY_I_MSK 0xfff8ffff
+#define RG_5G_RX_IQCAL_DELAY_SFT 16
+#define RG_5G_RX_IQCAL_DELAY_HI 18
+#define RG_5G_RX_IQCAL_DELAY_SZ 3
+#define RG_5G_PGAG_TXCAL_MSK 0x00f00000
+#define RG_5G_PGAG_TXCAL_I_MSK 0xff0fffff
+#define RG_5G_PGAG_TXCAL_SFT 20
+#define RG_5G_PGAG_TXCAL_HI 23
+#define RG_5G_PGAG_TXCAL_SZ 4
+#define RG_5G_TX_GAIN_TXCAL_MSK 0x7f000000
+#define RG_5G_TX_GAIN_TXCAL_I_MSK 0x80ffffff
+#define RG_5G_TX_GAIN_TXCAL_SFT 24
+#define RG_5G_TX_GAIN_TXCAL_HI 30
+#define RG_5G_TX_GAIN_TXCAL_SZ 7
+#define RG_5G_PGAG_RCCAL_MSK 0x0000000f
+#define RG_5G_PGAG_RCCAL_I_MSK 0xfffffff0
+#define RG_5G_PGAG_RCCAL_SFT 0
+#define RG_5G_PGAG_RCCAL_HI 3
+#define RG_5G_PGAG_RCCAL_SZ 4
+#define RG_5G_RFG_RXIQCAL_MSK 0x00000030
+#define RG_5G_RFG_RXIQCAL_I_MSK 0xffffffcf
+#define RG_5G_RFG_RXIQCAL_SFT 4
+#define RG_5G_RFG_RXIQCAL_HI 5
+#define RG_5G_RFG_RXIQCAL_SZ 2
+#define RG_5G_PGAG_RXIQCAL_MSK 0x000003c0
+#define RG_5G_PGAG_RXIQCAL_I_MSK 0xfffffc3f
+#define RG_5G_PGAG_RXIQCAL_SFT 6
+#define RG_5G_PGAG_RXIQCAL_HI 9
+#define RG_5G_PGAG_RXIQCAL_SZ 4
+#define RG_5G_TX_GAIN_RXIQCAL_MSK 0x0001fc00
+#define RG_5G_TX_GAIN_RXIQCAL_I_MSK 0xfffe03ff
+#define RG_5G_TX_GAIN_RXIQCAL_SFT 10
+#define RG_5G_TX_GAIN_RXIQCAL_HI 16
+#define RG_5G_TX_GAIN_RXIQCAL_SZ 7
+#define RG_5G_RFG_DPDCAL_MSK 0x00060000
+#define RG_5G_RFG_DPDCAL_I_MSK 0xfff9ffff
+#define RG_5G_RFG_DPDCAL_SFT 17
+#define RG_5G_RFG_DPDCAL_HI 18
+#define RG_5G_RFG_DPDCAL_SZ 2
+#define RG_5G_PGAG_DPDCAL_MSK 0x00780000
+#define RG_5G_PGAG_DPDCAL_I_MSK 0xff87ffff
+#define RG_5G_PGAG_DPDCAL_SFT 19
+#define RG_5G_PGAG_DPDCAL_HI 22
+#define RG_5G_PGAG_DPDCAL_SZ 4
+#define RG_5G_TX_GAIN_DPDCAL_MSK 0x3f800000
+#define RG_5G_TX_GAIN_DPDCAL_I_MSK 0xc07fffff
+#define RG_5G_TX_GAIN_DPDCAL_SFT 23
+#define RG_5G_TX_GAIN_DPDCAL_HI 29
+#define RG_5G_TX_GAIN_DPDCAL_SZ 7
+#define DB_DA_SX5GB_SUB_SEL_MSK 0x000000ff
+#define DB_DA_SX5GB_SUB_SEL_I_MSK 0xffffff00
+#define DB_DA_SX5GB_SUB_SEL_SFT 0
+#define DB_DA_SX5GB_SUB_SEL_HI 7
+#define DB_DA_SX5GB_SUB_SEL_SZ 8
+#define DB_DA_SX5GB_VCO_ISEL_MSK 0x00000f00
+#define DB_DA_SX5GB_VCO_ISEL_I_MSK 0xfffff0ff
+#define DB_DA_SX5GB_VCO_ISEL_SFT 8
+#define DB_DA_SX5GB_VCO_ISEL_HI 11
+#define DB_DA_SX5GB_VCO_ISEL_SZ 4
+#define DB_DA_SXMIX_SCA_SEL_MSK 0x0007e000
+#define DB_DA_SXMIX_SCA_SEL_I_MSK 0xfff81fff
+#define DB_DA_SXMIX_SCA_SEL_SFT 13
+#define DB_DA_SXMIX_SCA_SEL_HI 18
+#define DB_DA_SXMIX_SCA_SEL_SZ 6
+#define DB_DA_SXMIX_GMSEL_MSK 0x00180000
+#define DB_DA_SXMIX_GMSEL_I_MSK 0xffe7ffff
+#define DB_DA_SXMIX_GMSEL_SFT 19
+#define DB_DA_SXMIX_GMSEL_HI 20
+#define DB_DA_SXMIX_GMSEL_SZ 2
+#define DB_DA_SXREP_SCA_SEL_MSK 0x07e00000
+#define DB_DA_SXREP_SCA_SEL_I_MSK 0xf81fffff
+#define DB_DA_SXREP_SCA_SEL_SFT 21
+#define DB_DA_SXREP_SCA_SEL_HI 26
+#define DB_DA_SXREP_SCA_SEL_SZ 6
+#define DB_DA_SXREP_CSSEL_MSK 0x18000000
+#define DB_DA_SXREP_CSSEL_I_MSK 0xe7ffffff
+#define DB_DA_SXREP_CSSEL_SFT 27
+#define DB_DA_SXREP_CSSEL_HI 28
+#define DB_DA_SXREP_CSSEL_SZ 2
+#define DB_AD_SX5GB_AAC_COMPOUT_MSK 0x20000000
+#define DB_AD_SX5GB_AAC_COMPOUT_I_MSK 0xdfffffff
+#define DB_AD_SX5GB_AAC_COMPOUT_SFT 29
+#define DB_AD_SX5GB_AAC_COMPOUT_HI 29
+#define DB_AD_SX5GB_AAC_COMPOUT_SZ 1
+#define DB_SX5GB_TTL_VT_DET_MSK 0xc0000000
+#define DB_SX5GB_TTL_VT_DET_I_MSK 0x3fffffff
+#define DB_SX5GB_TTL_VT_DET_SFT 30
+#define DB_SX5GB_TTL_VT_DET_HI 31
+#define DB_SX5GB_TTL_VT_DET_SZ 2
+#define DB_SXMIX_SCA_SEL_A1_MSK 0x0000003f
+#define DB_SXMIX_SCA_SEL_A1_I_MSK 0xffffffc0
+#define DB_SXMIX_SCA_SEL_A1_SFT 0
+#define DB_SXMIX_SCA_SEL_A1_HI 5
+#define DB_SXMIX_SCA_SEL_A1_SZ 6
+#define DB_SXMIX_SCA_SEL_A2_MSK 0x00001f80
+#define DB_SXMIX_SCA_SEL_A2_I_MSK 0xffffe07f
+#define DB_SXMIX_SCA_SEL_A2_SFT 7
+#define DB_SXMIX_SCA_SEL_A2_HI 12
+#define DB_SXMIX_SCA_SEL_A2_SZ 6
+#define DB_SXREP_SCA_SEL_B1_MSK 0x000fc000
+#define DB_SXREP_SCA_SEL_B1_I_MSK 0xfff03fff
+#define DB_SXREP_SCA_SEL_B1_SFT 14
+#define DB_SXREP_SCA_SEL_B1_HI 19
+#define DB_SXREP_SCA_SEL_B1_SZ 6
+#define DB_SXREP_SCA_SEL_B2_MSK 0x07e00000
+#define DB_SXREP_SCA_SEL_B2_I_MSK 0xf81fffff
+#define DB_SXREP_SCA_SEL_B2_SFT 21
+#define DB_SXREP_SCA_SEL_B2_HI 26
+#define DB_SXREP_SCA_SEL_B2_SZ 6
+#define DB_SX5GB_SBCAL_NCOUNT_MSK 0x0000ffff
+#define DB_SX5GB_SBCAL_NCOUNT_I_MSK 0xffff0000
+#define DB_SX5GB_SBCAL_NCOUNT_SFT 0
+#define DB_SX5GB_SBCAL_NCOUNT_HI 15
+#define DB_SX5GB_SBCAL_NCOUNT_SZ 16
+#define DB_SX5GB_SBCAL_NTARGET_MSK 0xffff0000
+#define DB_SX5GB_SBCAL_NTARGET_I_MSK 0x0000ffff
+#define DB_SX5GB_SBCAL_NTARGET_SFT 16
+#define DB_SX5GB_SBCAL_NTARGET_HI 31
+#define DB_SX5GB_SBCAL_NTARGET_SZ 16
+#define RG_RX_SCAMA_STEP0_MSK 0x0000000f
+#define RG_RX_SCAMA_STEP0_I_MSK 0xfffffff0
+#define RG_RX_SCAMA_STEP0_SFT 0
+#define RG_RX_SCAMA_STEP0_HI 3
+#define RG_RX_SCAMA_STEP0_SZ 4
+#define RG_RX_SCAMA_STEP1_MSK 0x000000f0
+#define RG_RX_SCAMA_STEP1_I_MSK 0xffffff0f
+#define RG_RX_SCAMA_STEP1_SFT 4
+#define RG_RX_SCAMA_STEP1_HI 7
+#define RG_RX_SCAMA_STEP1_SZ 4
+#define RG_RX_SCAMA_STEP2_MSK 0x00000f00
+#define RG_RX_SCAMA_STEP2_I_MSK 0xfffff0ff
+#define RG_RX_SCAMA_STEP2_SFT 8
+#define RG_RX_SCAMA_STEP2_HI 11
+#define RG_RX_SCAMA_STEP2_SZ 4
+#define RG_RX_SCAMA_STEP3_MSK 0x0000f000
+#define RG_RX_SCAMA_STEP3_I_MSK 0xffff0fff
+#define RG_RX_SCAMA_STEP3_SFT 12
+#define RG_RX_SCAMA_STEP3_HI 15
+#define RG_RX_SCAMA_STEP3_SZ 4
+#define RG_RX_SCAMA_STEP4_MSK 0x000f0000
+#define RG_RX_SCAMA_STEP4_I_MSK 0xfff0ffff
+#define RG_RX_SCAMA_STEP4_SFT 16
+#define RG_RX_SCAMA_STEP4_HI 19
+#define RG_RX_SCAMA_STEP4_SZ 4
+#define RG_RX_SCAMA_STEP5_MSK 0x00f00000
+#define RG_RX_SCAMA_STEP5_I_MSK 0xff0fffff
+#define RG_RX_SCAMA_STEP5_SFT 20
+#define RG_RX_SCAMA_STEP5_HI 23
+#define RG_RX_SCAMA_STEP5_SZ 4
+#define RG_RX_SCAMA_STEP6_MSK 0x0f000000
+#define RG_RX_SCAMA_STEP6_I_MSK 0xf0ffffff
+#define RG_RX_SCAMA_STEP6_SFT 24
+#define RG_RX_SCAMA_STEP6_HI 27
+#define RG_RX_SCAMA_STEP6_SZ 4
+#define RG_RX_SCALOAD_STEP0_MSK 0x0000000f
+#define RG_RX_SCALOAD_STEP0_I_MSK 0xfffffff0
+#define RG_RX_SCALOAD_STEP0_SFT 0
+#define RG_RX_SCALOAD_STEP0_HI 3
+#define RG_RX_SCALOAD_STEP0_SZ 4
+#define RG_RX_SCALOAD_STEP1_MSK 0x000000f0
+#define RG_RX_SCALOAD_STEP1_I_MSK 0xffffff0f
+#define RG_RX_SCALOAD_STEP1_SFT 4
+#define RG_RX_SCALOAD_STEP1_HI 7
+#define RG_RX_SCALOAD_STEP1_SZ 4
+#define RG_RX_SCALOAD_STEP2_MSK 0x00000f00
+#define RG_RX_SCALOAD_STEP2_I_MSK 0xfffff0ff
+#define RG_RX_SCALOAD_STEP2_SFT 8
+#define RG_RX_SCALOAD_STEP2_HI 11
+#define RG_RX_SCALOAD_STEP2_SZ 4
+#define RG_RX_SCALOAD_STEP3_MSK 0x0000f000
+#define RG_RX_SCALOAD_STEP3_I_MSK 0xffff0fff
+#define RG_RX_SCALOAD_STEP3_SFT 12
+#define RG_RX_SCALOAD_STEP3_HI 15
+#define RG_RX_SCALOAD_STEP3_SZ 4
+#define RG_RX_SCALOAD_STEP4_MSK 0x000f0000
+#define RG_RX_SCALOAD_STEP4_I_MSK 0xfff0ffff
+#define RG_RX_SCALOAD_STEP4_SFT 16
+#define RG_RX_SCALOAD_STEP4_HI 19
+#define RG_RX_SCALOAD_STEP4_SZ 4
+#define RG_RX_SCALOAD_STEP5_MSK 0x00f00000
+#define RG_RX_SCALOAD_STEP5_I_MSK 0xff0fffff
+#define RG_RX_SCALOAD_STEP5_SFT 20
+#define RG_RX_SCALOAD_STEP5_HI 23
+#define RG_RX_SCALOAD_STEP5_SZ 4
+#define RG_RX_SCALOAD_STEP6_MSK 0x0f000000
+#define RG_RX_SCALOAD_STEP6_I_MSK 0xf0ffffff
+#define RG_RX_SCALOAD_STEP6_SFT 24
+#define RG_RX_SCALOAD_STEP6_HI 27
+#define RG_RX_SCALOAD_STEP6_SZ 4
+#define RG_5G_TXPGA_CAPSW_F0_MSK 0x00000007
+#define RG_5G_TXPGA_CAPSW_F0_I_MSK 0xfffffff8
+#define RG_5G_TXPGA_CAPSW_F0_SFT 0
+#define RG_5G_TXPGA_CAPSW_F0_HI 2
+#define RG_5G_TXPGA_CAPSW_F0_SZ 3
+#define RG_5G_PABIAS_CTRL_F0_MSK 0x00000078
+#define RG_5G_PABIAS_CTRL_F0_I_MSK 0xffffff87
+#define RG_5G_PABIAS_CTRL_F0_SFT 3
+#define RG_5G_PABIAS_CTRL_F0_HI 6
+#define RG_5G_PABIAS_CTRL_F0_SZ 4
+#define RG_5G_TX_PA1_VCAS_F0_MSK 0x00000380
+#define RG_5G_TX_PA1_VCAS_F0_I_MSK 0xfffffc7f
+#define RG_5G_TX_PA1_VCAS_F0_SFT 7
+#define RG_5G_TX_PA1_VCAS_F0_HI 9
+#define RG_5G_TX_PA1_VCAS_F0_SZ 3
+#define RG_5G_TX_PA2_VCAS_F0_MSK 0x00001c00
+#define RG_5G_TX_PA2_VCAS_F0_I_MSK 0xffffe3ff
+#define RG_5G_TX_PA2_VCAS_F0_SFT 10
+#define RG_5G_TX_PA2_VCAS_F0_HI 12
+#define RG_5G_TX_PA2_VCAS_F0_SZ 3
+#define RG_5G_TX_PA3_VCAS_F0_MSK 0x0000e000
+#define RG_5G_TX_PA3_VCAS_F0_I_MSK 0xffff1fff
+#define RG_5G_TX_PA3_VCAS_F0_SFT 13
+#define RG_5G_TX_PA3_VCAS_F0_HI 15
+#define RG_5G_TX_PA3_VCAS_F0_SZ 3
+#define RG_5G_TXPGA_CAPSW_F1_MSK 0x00070000
+#define RG_5G_TXPGA_CAPSW_F1_I_MSK 0xfff8ffff
+#define RG_5G_TXPGA_CAPSW_F1_SFT 16
+#define RG_5G_TXPGA_CAPSW_F1_HI 18
+#define RG_5G_TXPGA_CAPSW_F1_SZ 3
+#define RG_5G_PABIAS_CTRL_F1_MSK 0x00780000
+#define RG_5G_PABIAS_CTRL_F1_I_MSK 0xff87ffff
+#define RG_5G_PABIAS_CTRL_F1_SFT 19
+#define RG_5G_PABIAS_CTRL_F1_HI 22
+#define RG_5G_PABIAS_CTRL_F1_SZ 4
+#define RG_5G_TX_PA1_VCAS_F1_MSK 0x03800000
+#define RG_5G_TX_PA1_VCAS_F1_I_MSK 0xfc7fffff
+#define RG_5G_TX_PA1_VCAS_F1_SFT 23
+#define RG_5G_TX_PA1_VCAS_F1_HI 25
+#define RG_5G_TX_PA1_VCAS_F1_SZ 3
+#define RG_5G_TX_PA2_VCAS_F1_MSK 0x1c000000
+#define RG_5G_TX_PA2_VCAS_F1_I_MSK 0xe3ffffff
+#define RG_5G_TX_PA2_VCAS_F1_SFT 26
+#define RG_5G_TX_PA2_VCAS_F1_HI 28
+#define RG_5G_TX_PA2_VCAS_F1_SZ 3
+#define RG_5G_TX_PA3_VCAS_F1_MSK 0xe0000000
+#define RG_5G_TX_PA3_VCAS_F1_I_MSK 0x1fffffff
+#define RG_5G_TX_PA3_VCAS_F1_SFT 29
+#define RG_5G_TX_PA3_VCAS_F1_HI 31
+#define RG_5G_TX_PA3_VCAS_F1_SZ 3
+#define RG_5G_TXPGA_CAPSW_F2_MSK 0x00000007
+#define RG_5G_TXPGA_CAPSW_F2_I_MSK 0xfffffff8
+#define RG_5G_TXPGA_CAPSW_F2_SFT 0
+#define RG_5G_TXPGA_CAPSW_F2_HI 2
+#define RG_5G_TXPGA_CAPSW_F2_SZ 3
+#define RG_5G_PABIAS_CTRL_F2_MSK 0x00000078
+#define RG_5G_PABIAS_CTRL_F2_I_MSK 0xffffff87
+#define RG_5G_PABIAS_CTRL_F2_SFT 3
+#define RG_5G_PABIAS_CTRL_F2_HI 6
+#define RG_5G_PABIAS_CTRL_F2_SZ 4
+#define RG_5G_TX_PA1_VCAS_F2_MSK 0x00000380
+#define RG_5G_TX_PA1_VCAS_F2_I_MSK 0xfffffc7f
+#define RG_5G_TX_PA1_VCAS_F2_SFT 7
+#define RG_5G_TX_PA1_VCAS_F2_HI 9
+#define RG_5G_TX_PA1_VCAS_F2_SZ 3
+#define RG_5G_TX_PA2_VCAS_F2_MSK 0x00001c00
+#define RG_5G_TX_PA2_VCAS_F2_I_MSK 0xffffe3ff
+#define RG_5G_TX_PA2_VCAS_F2_SFT 10
+#define RG_5G_TX_PA2_VCAS_F2_HI 12
+#define RG_5G_TX_PA2_VCAS_F2_SZ 3
+#define RG_5G_TX_PA3_VCAS_F2_MSK 0x0000e000
+#define RG_5G_TX_PA3_VCAS_F2_I_MSK 0xffff1fff
+#define RG_5G_TX_PA3_VCAS_F2_SFT 13
+#define RG_5G_TX_PA3_VCAS_F2_HI 15
+#define RG_5G_TX_PA3_VCAS_F2_SZ 3
+#define RG_5G_TXPGA_CAPSW_F3_MSK 0x00070000
+#define RG_5G_TXPGA_CAPSW_F3_I_MSK 0xfff8ffff
+#define RG_5G_TXPGA_CAPSW_F3_SFT 16
+#define RG_5G_TXPGA_CAPSW_F3_HI 18
+#define RG_5G_TXPGA_CAPSW_F3_SZ 3
+#define RG_5G_PABIAS_CTRL_F3_MSK 0x00780000
+#define RG_5G_PABIAS_CTRL_F3_I_MSK 0xff87ffff
+#define RG_5G_PABIAS_CTRL_F3_SFT 19
+#define RG_5G_PABIAS_CTRL_F3_HI 22
+#define RG_5G_PABIAS_CTRL_F3_SZ 4
+#define RG_5G_TX_PA1_VCAS_F3_MSK 0x03800000
+#define RG_5G_TX_PA1_VCAS_F3_I_MSK 0xfc7fffff
+#define RG_5G_TX_PA1_VCAS_F3_SFT 23
+#define RG_5G_TX_PA1_VCAS_F3_HI 25
+#define RG_5G_TX_PA1_VCAS_F3_SZ 3
+#define RG_5G_TX_PA2_VCAS_F3_MSK 0x1c000000
+#define RG_5G_TX_PA2_VCAS_F3_I_MSK 0xe3ffffff
+#define RG_5G_TX_PA2_VCAS_F3_SFT 26
+#define RG_5G_TX_PA2_VCAS_F3_HI 28
+#define RG_5G_TX_PA2_VCAS_F3_SZ 3
+#define RG_5G_TX_PA3_VCAS_F3_MSK 0xe0000000
+#define RG_5G_TX_PA3_VCAS_F3_I_MSK 0x1fffffff
+#define RG_5G_TX_PA3_VCAS_F3_SFT 29
+#define RG_5G_TX_PA3_VCAS_F3_HI 31
+#define RG_5G_TX_PA3_VCAS_F3_SZ 3
+#define RG_5G_TX_PAFB_EN_F0_MSK 0x00000001
+#define RG_5G_TX_PAFB_EN_F0_I_MSK 0xfffffffe
+#define RG_5G_TX_PAFB_EN_F0_SFT 0
+#define RG_5G_TX_PAFB_EN_F0_HI 0
+#define RG_5G_TX_PAFB_EN_F0_SZ 1
+#define RG_5G_TX_PAFB_EN_F1_MSK 0x00000002
+#define RG_5G_TX_PAFB_EN_F1_I_MSK 0xfffffffd
+#define RG_5G_TX_PAFB_EN_F1_SFT 1
+#define RG_5G_TX_PAFB_EN_F1_HI 1
+#define RG_5G_TX_PAFB_EN_F1_SZ 1
+#define RG_5G_TX_PAFB_EN_F2_MSK 0x00000004
+#define RG_5G_TX_PAFB_EN_F2_I_MSK 0xfffffffb
+#define RG_5G_TX_PAFB_EN_F2_SFT 2
+#define RG_5G_TX_PAFB_EN_F2_HI 2
+#define RG_5G_TX_PAFB_EN_F2_SZ 1
+#define RG_5G_TX_PAFB_EN_F3_MSK 0x00000008
+#define RG_5G_TX_PAFB_EN_F3_I_MSK 0xfffffff7
+#define RG_5G_TX_PAFB_EN_F3_SFT 3
+#define RG_5G_TX_PAFB_EN_F3_HI 3
+#define RG_5G_TX_PAFB_EN_F3_SZ 1
+#define RG_5G_TX_GAIN_F0_MSK 0x000007f0
+#define RG_5G_TX_GAIN_F0_I_MSK 0xfffff80f
+#define RG_5G_TX_GAIN_F0_SFT 4
+#define RG_5G_TX_GAIN_F0_HI 10
+#define RG_5G_TX_GAIN_F0_SZ 7
+#define RG_5G_TX_GAIN_F1_MSK 0x0003f800
+#define RG_5G_TX_GAIN_F1_I_MSK 0xfffc07ff
+#define RG_5G_TX_GAIN_F1_SFT 11
+#define RG_5G_TX_GAIN_F1_HI 17
+#define RG_5G_TX_GAIN_F1_SZ 7
+#define RG_5G_TX_GAIN_F2_MSK 0x01fc0000
+#define RG_5G_TX_GAIN_F2_I_MSK 0xfe03ffff
+#define RG_5G_TX_GAIN_F2_SFT 18
+#define RG_5G_TX_GAIN_F2_HI 24
+#define RG_5G_TX_GAIN_F2_SZ 7
+#define RG_5G_TX_GAIN_F3_MSK 0xfe000000
+#define RG_5G_TX_GAIN_F3_I_MSK 0x01ffffff
+#define RG_5G_TX_GAIN_F3_SFT 25
+#define RG_5G_TX_GAIN_F3_HI 31
+#define RG_5G_TX_GAIN_F3_SZ 7
+#define RG_NFRAC_DELTA_MSK 0x00ffffff
+#define RG_NFRAC_DELTA_I_MSK 0xff000000
+#define RG_NFRAC_DELTA_SFT 0
+#define RG_NFRAC_DELTA_HI 23
+#define RG_NFRAC_DELTA_SZ 24
+#define RG_40M_MODE_MSK 0x01000000
+#define RG_40M_MODE_I_MSK 0xfeffffff
+#define RG_40M_MODE_SFT 24
+#define RG_40M_MODE_HI 24
+#define RG_40M_MODE_SZ 1
+#define RG_LO_UP_CH_MSK 0x10000000
+#define RG_LO_UP_CH_I_MSK 0xefffffff
+#define RG_LO_UP_CH_SFT 28
+#define RG_LO_UP_CH_HI 28
+#define RG_LO_UP_CH_SZ 1
+#define RG_BT_TRX_IF_MSK 0x07ff0000
+#define RG_BT_TRX_IF_I_MSK 0xf800ffff
+#define RG_BT_TRX_IF_SFT 16
+#define RG_BT_TRX_IF_HI 26
+#define RG_BT_TRX_IF_SZ 11
+#define RG_RX_IQ_ALPHA_MSK 0x0000001f
+#define RG_RX_IQ_ALPHA_I_MSK 0xffffffe0
+#define RG_RX_IQ_ALPHA_SFT 0
+#define RG_RX_IQ_ALPHA_HI 4
+#define RG_RX_IQ_ALPHA_SZ 5
+#define RG_RX_IQ_THETA_MSK 0x00001f00
+#define RG_RX_IQ_THETA_I_MSK 0xffffe0ff
+#define RG_RX_IQ_THETA_SFT 8
+#define RG_RX_IQ_THETA_HI 12
+#define RG_RX_IQ_THETA_SZ 5
+#define RG_RX_IQ_MANUAL_MSK 0x00010000
+#define RG_RX_IQ_MANUAL_I_MSK 0xfffeffff
+#define RG_RX_IQ_MANUAL_SFT 16
+#define RG_RX_IQ_MANUAL_HI 16
+#define RG_RX_IQ_MANUAL_SZ 1
+#define RG_RXIQ_NOSHRK_MSK 0x00020000
+#define RG_RXIQ_NOSHRK_I_MSK 0xfffdffff
+#define RG_RXIQ_NOSHRK_SFT 17
+#define RG_RXIQ_NOSHRK_HI 17
+#define RG_RXIQ_NOSHRK_SZ 1
+#define RG_RX_RSSIADC_TH_MSK 0x00f00000
+#define RG_RX_RSSIADC_TH_I_MSK 0xff0fffff
+#define RG_RX_RSSIADC_TH_SFT 20
+#define RG_RX_RSSIADC_TH_HI 23
+#define RG_RX_RSSIADC_TH_SZ 4
+#define RG_SUB_DC_MSK 0x01000000
+#define RG_SUB_DC_I_MSK 0xfeffffff
+#define RG_SUB_DC_SFT 24
+#define RG_SUB_DC_HI 24
+#define RG_SUB_DC_SZ 1
+#define RG_RSSI_EDGE_SEL_MSK 0x04000000
+#define RG_RSSI_EDGE_SEL_I_MSK 0xfbffffff
+#define RG_RSSI_EDGE_SEL_SFT 26
+#define RG_RSSI_EDGE_SEL_HI 26
+#define RG_RSSI_EDGE_SEL_SZ 1
+#define RG_ADC_EDGE_SEL_MSK 0x08000000
+#define RG_ADC_EDGE_SEL_I_MSK 0xf7ffffff
+#define RG_ADC_EDGE_SEL_SFT 27
+#define RG_ADC_EDGE_SEL_HI 27
+#define RG_ADC_EDGE_SEL_SZ 1
+#define RG_Q_INV_MSK 0x10000000
+#define RG_Q_INV_I_MSK 0xefffffff
+#define RG_Q_INV_SFT 28
+#define RG_Q_INV_HI 28
+#define RG_Q_INV_SZ 1
+#define RG_I_INV_MSK 0x20000000
+#define RG_I_INV_I_MSK 0xdfffffff
+#define RG_I_INV_SFT 29
+#define RG_I_INV_HI 29
+#define RG_I_INV_SZ 1
+#define RG_IQ_SWAP_MSK 0x40000000
+#define RG_IQ_SWAP_I_MSK 0xbfffffff
+#define RG_IQ_SWAP_SFT 30
+#define RG_IQ_SWAP_HI 30
+#define RG_IQ_SWAP_SZ 1
+#define RG_SIGN_SWAP_MSK 0x80000000
+#define RG_SIGN_SWAP_I_MSK 0x7fffffff
+#define RG_SIGN_SWAP_SFT 31
+#define RG_SIGN_SWAP_HI 31
+#define RG_SIGN_SWAP_SZ 1
+#define RG_TX_IQ_ALPHA_MSK 0x0000001f
+#define RG_TX_IQ_ALPHA_I_MSK 0xffffffe0
+#define RG_TX_IQ_ALPHA_SFT 0
+#define RG_TX_IQ_ALPHA_HI 4
+#define RG_TX_IQ_ALPHA_SZ 5
+#define RG_TX_IQ_THETA_MSK 0x00001f00
+#define RG_TX_IQ_THETA_I_MSK 0xffffe0ff
+#define RG_TX_IQ_THETA_SFT 8
+#define RG_TX_IQ_THETA_HI 12
+#define RG_TX_IQ_THETA_SZ 5
+#define RG_TX_IQ_MANUAL_MSK 0x00010000
+#define RG_TX_IQ_MANUAL_I_MSK 0xfffeffff
+#define RG_TX_IQ_MANUAL_SFT 16
+#define RG_TX_IQ_MANUAL_HI 16
+#define RG_TX_IQ_MANUAL_SZ 1
+#define RG_TXIQ_NOSHRK_MSK 0x00020000
+#define RG_TXIQ_NOSHRK_I_MSK 0xfffdffff
+#define RG_TXIQ_NOSHRK_SFT 17
+#define RG_TXIQ_NOSHRK_HI 17
+#define RG_TXIQ_NOSHRK_SZ 1
+#define RG_TX_IQCAL_TIME_MSK 0x00300000
+#define RG_TX_IQCAL_TIME_I_MSK 0xffcfffff
+#define RG_TX_IQCAL_TIME_SFT 20
+#define RG_TX_IQCAL_TIME_HI 21
+#define RG_TX_IQCAL_TIME_SZ 2
+#define RG_TX_FREQ_OFFSET_MSK 0x0000ffff
+#define RG_TX_FREQ_OFFSET_I_MSK 0xffff0000
+#define RG_TX_FREQ_OFFSET_SFT 0
+#define RG_TX_FREQ_OFFSET_HI 15
+#define RG_TX_FREQ_OFFSET_SZ 16
+#define RG_TONE_SCALE_MSK 0x01ff0000
+#define RG_TONE_SCALE_I_MSK 0xfe00ffff
+#define RG_TONE_SCALE_SFT 16
+#define RG_TONE_SCALE_HI 24
+#define RG_TONE_SCALE_SZ 9
+#define RG_BB_SIG_EN_MSK 0x02000000
+#define RG_BB_SIG_EN_I_MSK 0xfdffffff
+#define RG_BB_SIG_EN_SFT 25
+#define RG_BB_SIG_EN_HI 25
+#define RG_BB_SIG_EN_SZ 1
+#define RG_TONE_GEN_EN_MSK 0x04000000
+#define RG_TONE_GEN_EN_I_MSK 0xfbffffff
+#define RG_TONE_GEN_EN_SFT 26
+#define RG_TONE_GEN_EN_HI 26
+#define RG_TONE_GEN_EN_SZ 1
+#define RG_TX_UP8X_MAN_EN_MSK 0x08000000
+#define RG_TX_UP8X_MAN_EN_I_MSK 0xf7ffffff
+#define RG_TX_UP8X_MAN_EN_SFT 27
+#define RG_TX_UP8X_MAN_EN_HI 27
+#define RG_TX_UP8X_MAN_EN_SZ 1
+#define RG_DIS_DAC_OFFSET_MSK 0x10000000
+#define RG_DIS_DAC_OFFSET_I_MSK 0xefffffff
+#define RG_DIS_DAC_OFFSET_SFT 28
+#define RG_DIS_DAC_OFFSET_HI 28
+#define RG_DIS_DAC_OFFSET_SZ 1
+#define RG_CLK_320M_INV_MSK 0x20000000
+#define RG_CLK_320M_INV_I_MSK 0xdfffffff
+#define RG_CLK_320M_INV_SFT 29
+#define RG_CLK_320M_INV_HI 29
+#define RG_CLK_320M_INV_SZ 1
+#define RG_DPLL_CLK320BY2_MSK 0x40000000
+#define RG_DPLL_CLK320BY2_I_MSK 0xbfffffff
+#define RG_DPLL_CLK320BY2_SFT 30
+#define RG_DPLL_CLK320BY2_HI 30
+#define RG_DPLL_CLK320BY2_SZ 1
+#define RG_CBW_20_40_MSK 0x80000000
+#define RG_CBW_20_40_I_MSK 0x7fffffff
+#define RG_CBW_20_40_SFT 31
+#define RG_CBW_20_40_HI 31
+#define RG_CBW_20_40_SZ 1
+#define RG_DAC_DC_Q_MSK 0x000003ff
+#define RG_DAC_DC_Q_I_MSK 0xfffffc00
+#define RG_DAC_DC_Q_SFT 0
+#define RG_DAC_DC_Q_HI 9
+#define RG_DAC_DC_Q_SZ 10
+#define RG_DAC_DC_I_MSK 0x03ff0000
+#define RG_DAC_DC_I_I_MSK 0xfc00ffff
+#define RG_DAC_DC_I_SFT 16
+#define RG_DAC_DC_I_HI 25
+#define RG_DAC_DC_I_SZ 10
+#define RG_DAC_Q_SET_MSK 0x000003ff
+#define RG_DAC_Q_SET_I_MSK 0xfffffc00
+#define RG_DAC_Q_SET_SFT 0
+#define RG_DAC_Q_SET_HI 9
+#define RG_DAC_Q_SET_SZ 10
+#define RG_DAC_MAN_Q_EN_MSK 0x00001000
+#define RG_DAC_MAN_Q_EN_I_MSK 0xffffefff
+#define RG_DAC_MAN_Q_EN_SFT 12
+#define RG_DAC_MAN_Q_EN_HI 12
+#define RG_DAC_MAN_Q_EN_SZ 1
+#define RG_DAC_I_SET_MSK 0x03ff0000
+#define RG_DAC_I_SET_I_MSK 0xfc00ffff
+#define RG_DAC_I_SET_SFT 16
+#define RG_DAC_I_SET_HI 25
+#define RG_DAC_I_SET_SZ 10
+#define RG_DAC_MAN_I_EN_MSK 0x10000000
+#define RG_DAC_MAN_I_EN_I_MSK 0xefffffff
+#define RG_DAC_MAN_I_EN_SFT 28
+#define RG_DAC_MAN_I_EN_HI 28
+#define RG_DAC_MAN_I_EN_SZ 1
+#define RG_WF_RX_ABBCTUNE_TUNE_MSK 0x0000007f
+#define RG_WF_RX_ABBCTUNE_TUNE_I_MSK 0xffffff80
+#define RG_WF_RX_ABBCTUNE_TUNE_SFT 0
+#define RG_WF_RX_ABBCTUNE_TUNE_HI 6
+#define RG_WF_RX_ABBCTUNE_TUNE_SZ 7
+#define RG_WF_RX_ABBCTUNE_TUNE_EN_MSK 0x00000100
+#define RG_WF_RX_ABBCTUNE_TUNE_EN_I_MSK 0xfffffeff
+#define RG_WF_RX_ABBCTUNE_TUNE_EN_SFT 8
+#define RG_WF_RX_ABBCTUNE_TUNE_EN_HI 8
+#define RG_WF_RX_ABBCTUNE_TUNE_EN_SZ 1
+#define RG_WF_N_RX_ABBCTUNE_TUNE_MSK 0x007f0000
+#define RG_WF_N_RX_ABBCTUNE_TUNE_I_MSK 0xff80ffff
+#define RG_WF_N_RX_ABBCTUNE_TUNE_SFT 16
+#define RG_WF_N_RX_ABBCTUNE_TUNE_HI 22
+#define RG_WF_N_RX_ABBCTUNE_TUNE_SZ 7
+#define RG_WF_N_RX_ABBCTUNE_TUNE_EN_MSK 0x01000000
+#define RG_WF_N_RX_ABBCTUNE_TUNE_EN_I_MSK 0xfeffffff
+#define RG_WF_N_RX_ABBCTUNE_TUNE_EN_SFT 24
+#define RG_WF_N_RX_ABBCTUNE_TUNE_EN_HI 24
+#define RG_WF_N_RX_ABBCTUNE_TUNE_EN_SZ 1
+#define RG_RX_IQ_2500_ALPHA_MSK 0x0000001f
+#define RG_RX_IQ_2500_ALPHA_I_MSK 0xffffffe0
+#define RG_RX_IQ_2500_ALPHA_SFT 0
+#define RG_RX_IQ_2500_ALPHA_HI 4
+#define RG_RX_IQ_2500_ALPHA_SZ 5
+#define RG_RX_IQ_2500_THETA_MSK 0x00001f00
+#define RG_RX_IQ_2500_THETA_I_MSK 0xffffe0ff
+#define RG_RX_IQ_2500_THETA_SFT 8
+#define RG_RX_IQ_2500_THETA_HI 12
+#define RG_RX_IQ_2500_THETA_SZ 5
+#define RG_TX_IQ_2500_ALPHA_MSK 0x001f0000
+#define RG_TX_IQ_2500_ALPHA_I_MSK 0xffe0ffff
+#define RG_TX_IQ_2500_ALPHA_SFT 16
+#define RG_TX_IQ_2500_ALPHA_HI 20
+#define RG_TX_IQ_2500_ALPHA_SZ 5
+#define RG_TX_IQ_2500_THETA_MSK 0x1f000000
+#define RG_TX_IQ_2500_THETA_I_MSK 0xe0ffffff
+#define RG_TX_IQ_2500_THETA_SFT 24
+#define RG_TX_IQ_2500_THETA_HI 28
+#define RG_TX_IQ_2500_THETA_SZ 5
+#define RG_RX_IQ_5100_ALPHA_MSK 0x0000001f
+#define RG_RX_IQ_5100_ALPHA_I_MSK 0xffffffe0
+#define RG_RX_IQ_5100_ALPHA_SFT 0
+#define RG_RX_IQ_5100_ALPHA_HI 4
+#define RG_RX_IQ_5100_ALPHA_SZ 5
+#define RG_RX_IQ_5100_THETA_MSK 0x00001f00
+#define RG_RX_IQ_5100_THETA_I_MSK 0xffffe0ff
+#define RG_RX_IQ_5100_THETA_SFT 8
+#define RG_RX_IQ_5100_THETA_HI 12
+#define RG_RX_IQ_5100_THETA_SZ 5
+#define RG_TX_IQ_5100_ALPHA_MSK 0x001f0000
+#define RG_TX_IQ_5100_ALPHA_I_MSK 0xffe0ffff
+#define RG_TX_IQ_5100_ALPHA_SFT 16
+#define RG_TX_IQ_5100_ALPHA_HI 20
+#define RG_TX_IQ_5100_ALPHA_SZ 5
+#define RG_TX_IQ_5100_THETA_MSK 0x1f000000
+#define RG_TX_IQ_5100_THETA_I_MSK 0xe0ffffff
+#define RG_TX_IQ_5100_THETA_SFT 24
+#define RG_TX_IQ_5100_THETA_HI 28
+#define RG_TX_IQ_5100_THETA_SZ 5
+#define RG_RX_IQ_5500_ALPHA_MSK 0x0000001f
+#define RG_RX_IQ_5500_ALPHA_I_MSK 0xffffffe0
+#define RG_RX_IQ_5500_ALPHA_SFT 0
+#define RG_RX_IQ_5500_ALPHA_HI 4
+#define RG_RX_IQ_5500_ALPHA_SZ 5
+#define RG_RX_IQ_5500_THETA_MSK 0x00001f00
+#define RG_RX_IQ_5500_THETA_I_MSK 0xffffe0ff
+#define RG_RX_IQ_5500_THETA_SFT 8
+#define RG_RX_IQ_5500_THETA_HI 12
+#define RG_RX_IQ_5500_THETA_SZ 5
+#define RG_TX_IQ_5500_ALPHA_MSK 0x001f0000
+#define RG_TX_IQ_5500_ALPHA_I_MSK 0xffe0ffff
+#define RG_TX_IQ_5500_ALPHA_SFT 16
+#define RG_TX_IQ_5500_ALPHA_HI 20
+#define RG_TX_IQ_5500_ALPHA_SZ 5
+#define RG_TX_IQ_5500_THETA_MSK 0x1f000000
+#define RG_TX_IQ_5500_THETA_I_MSK 0xe0ffffff
+#define RG_TX_IQ_5500_THETA_SFT 24
+#define RG_TX_IQ_5500_THETA_HI 28
+#define RG_TX_IQ_5500_THETA_SZ 5
+#define RG_RX_IQ_5700_ALPHA_MSK 0x0000001f
+#define RG_RX_IQ_5700_ALPHA_I_MSK 0xffffffe0
+#define RG_RX_IQ_5700_ALPHA_SFT 0
+#define RG_RX_IQ_5700_ALPHA_HI 4
+#define RG_RX_IQ_5700_ALPHA_SZ 5
+#define RG_RX_IQ_5700_THETA_MSK 0x00001f00
+#define RG_RX_IQ_5700_THETA_I_MSK 0xffffe0ff
+#define RG_RX_IQ_5700_THETA_SFT 8
+#define RG_RX_IQ_5700_THETA_HI 12
+#define RG_RX_IQ_5700_THETA_SZ 5
+#define RG_TX_IQ_5700_ALPHA_MSK 0x001f0000
+#define RG_TX_IQ_5700_ALPHA_I_MSK 0xffe0ffff
+#define RG_TX_IQ_5700_ALPHA_SFT 16
+#define RG_TX_IQ_5700_ALPHA_HI 20
+#define RG_TX_IQ_5700_ALPHA_SZ 5
+#define RG_TX_IQ_5700_THETA_MSK 0x1f000000
+#define RG_TX_IQ_5700_THETA_I_MSK 0xe0ffffff
+#define RG_TX_IQ_5700_THETA_SFT 24
+#define RG_TX_IQ_5700_THETA_HI 28
+#define RG_TX_IQ_5700_THETA_SZ 5
+#define RG_RX_IQ_5900_ALPHA_MSK 0x0000001f
+#define RG_RX_IQ_5900_ALPHA_I_MSK 0xffffffe0
+#define RG_RX_IQ_5900_ALPHA_SFT 0
+#define RG_RX_IQ_5900_ALPHA_HI 4
+#define RG_RX_IQ_5900_ALPHA_SZ 5
+#define RG_RX_IQ_5900_THETA_MSK 0x00001f00
+#define RG_RX_IQ_5900_THETA_I_MSK 0xffffe0ff
+#define RG_RX_IQ_5900_THETA_SFT 8
+#define RG_RX_IQ_5900_THETA_HI 12
+#define RG_RX_IQ_5900_THETA_SZ 5
+#define RG_TX_IQ_5900_ALPHA_MSK 0x001f0000
+#define RG_TX_IQ_5900_ALPHA_I_MSK 0xffe0ffff
+#define RG_TX_IQ_5900_ALPHA_SFT 16
+#define RG_TX_IQ_5900_ALPHA_HI 20
+#define RG_TX_IQ_5900_ALPHA_SZ 5
+#define RG_TX_IQ_5900_THETA_MSK 0x1f000000
+#define RG_TX_IQ_5900_THETA_I_MSK 0xe0ffffff
+#define RG_TX_IQ_5900_THETA_SFT 24
+#define RG_TX_IQ_5900_THETA_HI 28
+#define RG_TX_IQ_5900_THETA_SZ 5
+#define RG_PHASE_STEP_VALUE_MSK 0x0000ffff
+#define RG_PHASE_STEP_VALUE_I_MSK 0xffff0000
+#define RG_PHASE_STEP_VALUE_SFT 0
+#define RG_PHASE_STEP_VALUE_HI 15
+#define RG_PHASE_STEP_VALUE_SZ 16
+#define RG_PHASE_MANUAL_MSK 0x00010000
+#define RG_PHASE_MANUAL_I_MSK 0xfffeffff
+#define RG_PHASE_MANUAL_SFT 16
+#define RG_PHASE_MANUAL_HI 16
+#define RG_PHASE_MANUAL_SZ 1
+#define RG_ALPHA_SEL_MSK 0x00300000
+#define RG_ALPHA_SEL_I_MSK 0xffcfffff
+#define RG_ALPHA_SEL_SFT 20
+#define RG_ALPHA_SEL_HI 21
+#define RG_ALPHA_SEL_SZ 2
+#define RG_SPECTRUM_BW_MSK 0x03000000
+#define RG_SPECTRUM_BW_I_MSK 0xfcffffff
+#define RG_SPECTRUM_BW_SFT 24
+#define RG_SPECTRUM_BW_HI 25
+#define RG_SPECTRUM_BW_SZ 2
+#define RG_SPECTRUM_EN_MSK 0x10000000
+#define RG_SPECTRUM_EN_I_MSK 0xefffffff
+#define RG_SPECTRUM_EN_SFT 28
+#define RG_SPECTRUM_EN_HI 28
+#define RG_SPECTRUM_EN_SZ 1
+#define RO_WF_DCCAL_DONE_MSK 0x00010000
+#define RO_WF_DCCAL_DONE_I_MSK 0xfffeffff
+#define RO_WF_DCCAL_DONE_SFT 16
+#define RO_WF_DCCAL_DONE_HI 16
+#define RO_WF_DCCAL_DONE_SZ 1
+#define RO_BT_DCCAL_DONE_MSK 0x00020000
+#define RO_BT_DCCAL_DONE_I_MSK 0xfffdffff
+#define RO_BT_DCCAL_DONE_SFT 17
+#define RO_BT_DCCAL_DONE_HI 17
+#define RO_BT_DCCAL_DONE_SZ 1
+#define RO_RCCAL_DONE_MSK 0x00040000
+#define RO_RCCAL_DONE_I_MSK 0xfffbffff
+#define RO_RCCAL_DONE_SFT 18
+#define RO_RCCAL_DONE_HI 18
+#define RO_RCCAL_DONE_SZ 1
+#define RO_TXDC_DONE_MSK 0x00080000
+#define RO_TXDC_DONE_I_MSK 0xfff7ffff
+#define RO_TXDC_DONE_SFT 19
+#define RO_TXDC_DONE_HI 19
+#define RO_TXDC_DONE_SZ 1
+#define RO_TXIQ_DONE_MSK 0x00100000
+#define RO_TXIQ_DONE_I_MSK 0xffefffff
+#define RO_TXIQ_DONE_SFT 20
+#define RO_TXIQ_DONE_HI 20
+#define RO_TXIQ_DONE_SZ 1
+#define RO_RXIQ_DONE_MSK 0x00200000
+#define RO_RXIQ_DONE_I_MSK 0xffdfffff
+#define RO_RXIQ_DONE_SFT 21
+#define RO_RXIQ_DONE_HI 21
+#define RO_RXIQ_DONE_SZ 1
+#define RO_5G_TXDC_DONE_MSK 0x00400000
+#define RO_5G_TXDC_DONE_I_MSK 0xffbfffff
+#define RO_5G_TXDC_DONE_SFT 22
+#define RO_5G_TXDC_DONE_HI 22
+#define RO_5G_TXDC_DONE_SZ 1
+#define RO_5G_TXIQ_DONE_MSK 0x00800000
+#define RO_5G_TXIQ_DONE_I_MSK 0xff7fffff
+#define RO_5G_TXIQ_DONE_SFT 23
+#define RO_5G_TXIQ_DONE_HI 23
+#define RO_5G_TXIQ_DONE_SZ 1
+#define RO_5G_RXIQ_DONE_MSK 0x01000000
+#define RO_5G_RXIQ_DONE_I_MSK 0xfeffffff
+#define RO_5G_RXIQ_DONE_SFT 24
+#define RO_5G_RXIQ_DONE_HI 24
+#define RO_5G_RXIQ_DONE_SZ 1
+#define RO_5G_DCCAL_DONE_MSK 0x02000000
+#define RO_5G_DCCAL_DONE_I_MSK 0xfdffffff
+#define RO_5G_DCCAL_DONE_SFT 25
+#define RO_5G_DCCAL_DONE_HI 25
+#define RO_5G_DCCAL_DONE_SZ 1
+#define RO_PRE_DC_DONE_MSK 0x04000000
+#define RO_PRE_DC_DONE_I_MSK 0xfbffffff
+#define RO_PRE_DC_DONE_SFT 26
+#define RO_PRE_DC_DONE_HI 26
+#define RO_PRE_DC_DONE_SZ 1
+#define RG_PHASE_17P5M_MSK 0x0000ffff
+#define RG_PHASE_17P5M_I_MSK 0xffff0000
+#define RG_PHASE_17P5M_SFT 0
+#define RG_PHASE_17P5M_HI 15
+#define RG_PHASE_17P5M_SZ 16
+#define RG_PHASE_2P5M_MSK 0xffff0000
+#define RG_PHASE_2P5M_I_MSK 0x0000ffff
+#define RG_PHASE_2P5M_SFT 16
+#define RG_PHASE_2P5M_HI 31
+#define RG_PHASE_2P5M_SZ 16
+#define RG_PHASE_RXIQ_1M_MSK 0x0000ffff
+#define RG_PHASE_RXIQ_1M_I_MSK 0xffff0000
+#define RG_PHASE_RXIQ_1M_SFT 0
+#define RG_PHASE_RXIQ_1M_HI 15
+#define RG_PHASE_RXIQ_1M_SZ 16
+#define RG_PHASE_1M_MSK 0xffff0000
+#define RG_PHASE_1M_I_MSK 0x0000ffff
+#define RG_PHASE_1M_SFT 16
+#define RG_PHASE_1M_HI 31
+#define RG_PHASE_1M_SZ 16
+#define RG_PHASE_35M_MSK 0xffff0000
+#define RG_PHASE_35M_I_MSK 0x0000ffff
+#define RG_PHASE_35M_SFT 16
+#define RG_PHASE_35M_HI 31
+#define RG_PHASE_35M_SZ 16
+#define RO_RX_IQ_THETA_MSK 0x0000001f
+#define RO_RX_IQ_THETA_I_MSK 0xffffffe0
+#define RO_RX_IQ_THETA_SFT 0
+#define RO_RX_IQ_THETA_HI 4
+#define RO_RX_IQ_THETA_SZ 5
+#define RO_RX_IQ_ALPHA_MSK 0x00001f00
+#define RO_RX_IQ_ALPHA_I_MSK 0xffffe0ff
+#define RO_RX_IQ_ALPHA_SFT 8
+#define RO_RX_IQ_ALPHA_HI 12
+#define RO_RX_IQ_ALPHA_SZ 5
+#define RO_TX_IQ_THETA_MSK 0x001f0000
+#define RO_TX_IQ_THETA_I_MSK 0xffe0ffff
+#define RO_TX_IQ_THETA_SFT 16
+#define RO_TX_IQ_THETA_HI 20
+#define RO_TX_IQ_THETA_SZ 5
+#define RO_TX_IQ_ALPHA_MSK 0x1f000000
+#define RO_TX_IQ_ALPHA_I_MSK 0xe0ffffff
+#define RO_TX_IQ_ALPHA_SFT 24
+#define RO_TX_IQ_ALPHA_HI 28
+#define RO_TX_IQ_ALPHA_SZ 5
+#define RG_RX_RCCAL_TARG_MSK 0x000003ff
+#define RG_RX_RCCAL_TARG_I_MSK 0xfffffc00
+#define RG_RX_RCCAL_TARG_SFT 0
+#define RG_RX_RCCAL_TARG_HI 9
+#define RG_RX_RCCAL_TARG_SZ 10
+#define RG_RX_DC_POLAR_INV_MSK 0x00001000
+#define RG_RX_DC_POLAR_INV_I_MSK 0xffffefff
+#define RG_RX_DC_POLAR_INV_SFT 12
+#define RG_RX_DC_POLAR_INV_HI 12
+#define RG_RX_DC_POLAR_INV_SZ 1
+#define RG_RCCAL_POLAR_INV_MSK 0x00002000
+#define RG_RCCAL_POLAR_INV_I_MSK 0xffffdfff
+#define RG_RCCAL_POLAR_INV_SFT 13
+#define RG_RCCAL_POLAR_INV_HI 13
+#define RG_RCCAL_POLAR_INV_SZ 1
+#define RG_RX_DC_RESOLUTION_MSK 0x00004000
+#define RG_RX_DC_RESOLUTION_I_MSK 0xffffbfff
+#define RG_RX_DC_RESOLUTION_SFT 14
+#define RG_RX_DC_RESOLUTION_HI 14
+#define RG_RX_DC_RESOLUTION_SZ 1
+#define RG_RX_RCCAL_40M_TARG_MSK 0x03ff0000
+#define RG_RX_RCCAL_40M_TARG_I_MSK 0xfc00ffff
+#define RG_RX_RCCAL_40M_TARG_SFT 16
+#define RG_RX_RCCAL_40M_TARG_HI 25
+#define RG_RX_RCCAL_40M_TARG_SZ 10
+#define RO_SPECTRUM_IQ_PWR_39_32_MSK 0x000000ff
+#define RO_SPECTRUM_IQ_PWR_39_32_I_MSK 0xffffff00
+#define RO_SPECTRUM_IQ_PWR_39_32_SFT 0
+#define RO_SPECTRUM_IQ_PWR_39_32_HI 7
+#define RO_SPECTRUM_IQ_PWR_39_32_SZ 8
+#define RG_SPECTRUM_LO_FIX_MSK 0x00010000
+#define RG_SPECTRUM_LO_FIX_I_MSK 0xfffeffff
+#define RG_SPECTRUM_LO_FIX_SFT 16
+#define RG_SPECTRUM_LO_FIX_HI 16
+#define RG_SPECTRUM_LO_FIX_SZ 1
+#define RG_SPECTRUM_PWR_UPDATE_MSK 0x00100000
+#define RG_SPECTRUM_PWR_UPDATE_I_MSK 0xffefffff
+#define RG_SPECTRUM_PWR_UPDATE_SFT 20
+#define RG_SPECTRUM_PWR_UPDATE_HI 20
+#define RG_SPECTRUM_PWR_UPDATE_SZ 1
+#define RO_SPECTRUM_IQ_PWR_31_0_MSK 0xffffffff
+#define RO_SPECTRUM_IQ_PWR_31_0_I_MSK 0x00000000
+#define RO_SPECTRUM_IQ_PWR_31_0_SFT 0
+#define RO_SPECTRUM_IQ_PWR_31_0_HI 31
+#define RO_SPECTRUM_IQ_PWR_31_0_SZ 32
+#define RG_PROC_DELAY_MSK 0x00000007
+#define RG_PROC_DELAY_I_MSK 0xfffffff8
+#define RG_PROC_DELAY_SFT 0
+#define RG_PROC_DELAY_HI 2
+#define RG_PROC_DELAY_SZ 3
+#define RG_PRE_DC_POLA_INV_MSK 0x00000010
+#define RG_PRE_DC_POLA_INV_I_MSK 0xffffffef
+#define RG_PRE_DC_POLA_INV_SFT 4
+#define RG_PRE_DC_POLA_INV_HI 4
+#define RG_PRE_DC_POLA_INV_SZ 1
+#define RG_RX_PRE_DC_RESOLUTION_MSK 0x00000020
+#define RG_RX_PRE_DC_RESOLUTION_I_MSK 0xffffffdf
+#define RG_RX_PRE_DC_RESOLUTION_SFT 5
+#define RG_RX_PRE_DC_RESOLUTION_HI 5
+#define RG_RX_PRE_DC_RESOLUTION_SZ 1
+#define RG_PRE_DC_AUTO_MSK 0x00000040
+#define RG_PRE_DC_AUTO_I_MSK 0xffffffbf
+#define RG_PRE_DC_AUTO_SFT 6
+#define RG_PRE_DC_AUTO_HI 6
+#define RG_PRE_DC_AUTO_SZ 1
+#define RG_FILTER_AVERAGE_EN_MSK 0x00000080
+#define RG_FILTER_AVERAGE_EN_I_MSK 0xffffff7f
+#define RG_FILTER_AVERAGE_EN_SFT 7
+#define RG_FILTER_AVERAGE_EN_HI 7
+#define RG_FILTER_AVERAGE_EN_SZ 1
+#define RG_PHASE_RND_EN_MSK 0x00000100
+#define RG_PHASE_RND_EN_I_MSK 0xfffffeff
+#define RG_PHASE_RND_EN_SFT 8
+#define RG_PHASE_RND_EN_HI 8
+#define RG_PHASE_RND_EN_SZ 1
+#define RG_RCCAL_DATA_SEL_MSK 0x00000200
+#define RG_RCCAL_DATA_SEL_I_MSK 0xfffffdff
+#define RG_RCCAL_DATA_SEL_SFT 9
+#define RG_RCCAL_DATA_SEL_HI 9
+#define RG_RCCAL_DATA_SEL_SZ 1
+#define RG_HS3W_TX_RF_GAIN_MSK 0x0000007f
+#define RG_HS3W_TX_RF_GAIN_I_MSK 0xffffff80
+#define RG_HS3W_TX_RF_GAIN_SFT 0
+#define RG_HS3W_TX_RF_GAIN_HI 6
+#define RG_HS3W_TX_RF_GAIN_SZ 7
+#define RG_HS3W_PGAGC_MSK 0x00000f00
+#define RG_HS3W_PGAGC_I_MSK 0xfffff0ff
+#define RG_HS3W_PGAGC_SFT 8
+#define RG_HS3W_PGAGC_HI 11
+#define RG_HS3W_PGAGC_SZ 4
+#define RG_HS3W_RFGC_MSK 0x00003000
+#define RG_HS3W_RFGC_I_MSK 0xffffcfff
+#define RG_HS3W_RFGC_SFT 12
+#define RG_HS3W_RFGC_HI 13
+#define RG_HS3W_RFGC_SZ 2
+#define RG_HS3W_RXAGC_MSK 0x00004000
+#define RG_HS3W_RXAGC_I_MSK 0xffffbfff
+#define RG_HS3W_RXAGC_SFT 14
+#define RG_HS3W_RXAGC_HI 14
+#define RG_HS3W_RXAGC_SZ 1
+#define RG_HS3W_RF_PHY_MODE_MSK 0x00070000
+#define RG_HS3W_RF_PHY_MODE_I_MSK 0xfff8ffff
+#define RG_HS3W_RF_PHY_MODE_SFT 16
+#define RG_HS3W_RF_PHY_MODE_HI 18
+#define RG_HS3W_RF_PHY_MODE_SZ 3
+#define RG_HS3W_MANUAL_MSK 0x00100000
+#define RG_HS3W_MANUAL_I_MSK 0xffefffff
+#define RG_HS3W_MANUAL_SFT 20
+#define RG_HS3W_MANUAL_HI 20
+#define RG_HS3W_MANUAL_SZ 1
+#define RG_HS3W_COMM_DATA_MSK 0x07000000
+#define RG_HS3W_COMM_DATA_I_MSK 0xf8ffffff
+#define RG_HS3W_COMM_DATA_SFT 24
+#define RG_HS3W_COMM_DATA_HI 26
+#define RG_HS3W_COMM_DATA_SZ 3
+#define RG_HS3W_START_SENT_MSK 0x10000000
+#define RG_HS3W_START_SENT_I_MSK 0xefffffff
+#define RG_HS3W_START_SENT_SFT 28
+#define RG_HS3W_START_SENT_HI 28
+#define RG_HS3W_START_SENT_SZ 1
+#define RG_HS3W_SX_RFCTRL_CH_INT_10_8_MSK 0x00000007
+#define RG_HS3W_SX_RFCTRL_CH_INT_10_8_I_MSK 0xfffffff8
+#define RG_HS3W_SX_RFCTRL_CH_INT_10_8_SFT 0
+#define RG_HS3W_SX_RFCTRL_CH_INT_10_8_HI 2
+#define RG_HS3W_SX_RFCTRL_CH_INT_10_8_SZ 3
+#define RG_HS3W_SX_RFCH_MAP_EN_INT_MSK 0x00000010
+#define RG_HS3W_SX_RFCH_MAP_EN_INT_I_MSK 0xffffffef
+#define RG_HS3W_SX_RFCH_MAP_EN_INT_SFT 4
+#define RG_HS3W_SX_RFCH_MAP_EN_INT_HI 4
+#define RG_HS3W_SX_RFCH_MAP_EN_INT_SZ 1
+#define RG_HS3W_SX_CHANNEL_INT_MSK 0x0007f800
+#define RG_HS3W_SX_CHANNEL_INT_I_MSK 0xfff807ff
+#define RG_HS3W_SX_CHANNEL_INT_SFT 11
+#define RG_HS3W_SX_CHANNEL_INT_HI 18
+#define RG_HS3W_SX_CHANNEL_INT_SZ 8
+#define RG_HS3W_SX_RFCTRL_F_INT_MSK 0x00ffffff
+#define RG_HS3W_SX_RFCTRL_F_INT_I_MSK 0xff000000
+#define RG_HS3W_SX_RFCTRL_F_INT_SFT 0
+#define RG_HS3W_SX_RFCTRL_F_INT_HI 23
+#define RG_HS3W_SX_RFCTRL_F_INT_SZ 24
+#define RG_HS3W_SX_RFCTRL_CH_INT_7_0_MSK 0xff000000
+#define RG_HS3W_SX_RFCTRL_CH_INT_7_0_I_MSK 0x00ffffff
+#define RG_HS3W_SX_RFCTRL_CH_INT_7_0_SFT 24
+#define RG_HS3W_SX_RFCTRL_CH_INT_7_0_HI 31
+#define RG_HS3W_SX_RFCTRL_CH_INT_7_0_SZ 8
+#define RG_MODE_BY_HS_3WIRE_MSK 0x00000001
+#define RG_MODE_BY_HS_3WIRE_I_MSK 0xfffffffe
+#define RG_MODE_BY_HS_3WIRE_SFT 0
+#define RG_MODE_BY_HS_3WIRE_HI 0
+#define RG_MODE_BY_HS_3WIRE_SZ 1
+#define RG_MODE_BY_PHY_MSK 0x00000010
+#define RG_MODE_BY_PHY_I_MSK 0xffffffef
+#define RG_MODE_BY_PHY_SFT 4
+#define RG_MODE_BY_PHY_HI 4
+#define RG_MODE_BY_PHY_SZ 1
+#define RG_MODE_BY_HWPIN_MSK 0x00000100
+#define RG_MODE_BY_HWPIN_I_MSK 0xfffffeff
+#define RG_MODE_BY_HWPIN_SFT 8
+#define RG_MODE_BY_HWPIN_HI 8
+#define RG_MODE_BY_HWPIN_SZ 1
+#define RO_RF_PHY_MODE_MSK 0x00070000
+#define RO_RF_PHY_MODE_I_MSK 0xfff8ffff
+#define RO_RF_PHY_MODE_SFT 16
+#define RO_RF_PHY_MODE_HI 18
+#define RO_RF_PHY_MODE_SZ 3
+#define RO_HS3W_SX_CHANNEL_MSK 0x000000ff
+#define RO_HS3W_SX_CHANNEL_I_MSK 0xffffff00
+#define RO_HS3W_SX_CHANNEL_SFT 0
+#define RO_HS3W_SX_CHANNEL_HI 7
+#define RO_HS3W_SX_CHANNEL_SZ 8
+#define RO_HS3W_SX_RFCH_MAP_EN_MSK 0x00000100
+#define RO_HS3W_SX_RFCH_MAP_EN_I_MSK 0xfffffeff
+#define RO_HS3W_SX_RFCH_MAP_EN_SFT 8
+#define RO_HS3W_SX_RFCH_MAP_EN_HI 8
+#define RO_HS3W_SX_RFCH_MAP_EN_SZ 1
+#define RO_GAIN_TX_MSK 0x007f0000
+#define RO_GAIN_TX_I_MSK 0xff80ffff
+#define RO_GAIN_TX_SFT 16
+#define RO_GAIN_TX_HI 22
+#define RO_GAIN_TX_SZ 7
+#define RO_ABBPGA_MSK 0x0f000000
+#define RO_ABBPGA_I_MSK 0xf0ffffff
+#define RO_ABBPGA_SFT 24
+#define RO_ABBPGA_HI 27
+#define RO_ABBPGA_SZ 4
+#define RO_RFPGA_MSK 0x30000000
+#define RO_RFPGA_I_MSK 0xcfffffff
+#define RO_RFPGA_SFT 28
+#define RO_RFPGA_HI 29
+#define RO_RFPGA_SZ 2
+#define RO_DA_RX_AGC_MSK 0x80000000
+#define RO_DA_RX_AGC_I_MSK 0x7fffffff
+#define RO_DA_RX_AGC_SFT 31
+#define RO_DA_RX_AGC_HI 31
+#define RO_DA_RX_AGC_SZ 1
+#define RO_HS3W_SX_RFCTRL_CH_MSK 0x000007ff
+#define RO_HS3W_SX_RFCTRL_CH_I_MSK 0xfffff800
+#define RO_HS3W_SX_RFCTRL_CH_SFT 0
+#define RO_HS3W_SX_RFCTRL_CH_HI 10
+#define RO_HS3W_SX_RFCTRL_CH_SZ 11
+#define RO_HS3W_SX_RFCTRL_F_MSK 0x00ffffff
+#define RO_HS3W_SX_RFCTRL_F_I_MSK 0xff000000
+#define RO_HS3W_SX_RFCTRL_F_SFT 0
+#define RO_HS3W_SX_RFCTRL_F_HI 23
+#define RO_HS3W_SX_RFCTRL_F_SZ 24
+#define RO_REFREG_KHZ_OUT_MSK 0x007fffff
+#define RO_REFREG_KHZ_OUT_I_MSK 0xff800000
+#define RO_REFREG_KHZ_OUT_SFT 0
+#define RO_REFREG_KHZ_OUT_HI 22
+#define RO_REFREG_KHZ_OUT_SZ 23
+#define RO_RF_CH_FREQ_MSK 0x00001fff
+#define RO_RF_CH_FREQ_I_MSK 0xffffe000
+#define RO_RF_CH_FREQ_SFT 0
+#define RO_RF_CH_FREQ_HI 12
+#define RO_RF_CH_FREQ_SZ 13
+#define RO_DC_CAL_Q_MSK 0x0000007f
+#define RO_DC_CAL_Q_I_MSK 0xffffff80
+#define RO_DC_CAL_Q_SFT 0
+#define RO_DC_CAL_Q_HI 6
+#define RO_DC_CAL_Q_SZ 7
+#define RO_DC_CAL_I_MSK 0x007f0000
+#define RO_DC_CAL_I_I_MSK 0xff80ffff
+#define RO_DC_CAL_I_SFT 16
+#define RO_DC_CAL_I_HI 22
+#define RO_DC_CAL_I_SZ 7
+#define RG_AUDIO_VOLUME_MSK 0x000003ff
+#define RG_AUDIO_VOLUME_I_MSK 0xfffffc00
+#define RG_AUDIO_VOLUME_SFT 0
+#define RG_AUDIO_VOLUME_HI 9
+#define RG_AUDIO_VOLUME_SZ 10
+#define RG_AUDIO_ALPHA_MSK 0x00003000
+#define RG_AUDIO_ALPHA_I_MSK 0xffffcfff
+#define RG_AUDIO_ALPHA_SFT 12
+#define RG_AUDIO_ALPHA_HI 13
+#define RG_AUDIO_ALPHA_SZ 2
+#define RG_AUDIO_FIL_EN_MSK 0x00010000
+#define RG_AUDIO_FIL_EN_I_MSK 0xfffeffff
+#define RG_AUDIO_FIL_EN_SFT 16
+#define RG_AUDIO_FIL_EN_HI 16
+#define RG_AUDIO_FIL_EN_SZ 1
+#define RG_IOT_ADC_SIGN_SWAP_MSK 0x01000000
+#define RG_IOT_ADC_SIGN_SWAP_I_MSK 0xfeffffff
+#define RG_IOT_ADC_SIGN_SWAP_SFT 24
+#define RG_IOT_ADC_SIGN_SWAP_HI 24
+#define RG_IOT_ADC_SIGN_SWAP_SZ 1
+#define RG_IOT_ADC_EDGE_SEL_MSK 0x02000000
+#define RG_IOT_ADC_EDGE_SEL_I_MSK 0xfdffffff
+#define RG_IOT_ADC_EDGE_SEL_SFT 25
+#define RG_IOT_ADC_EDGE_SEL_HI 25
+#define RG_IOT_ADC_EDGE_SEL_SZ 1
+#define RG_BYPASS_AUDIO_LWDF_MSK 0x10000000
+#define RG_BYPASS_AUDIO_LWDF_I_MSK 0xefffffff
+#define RG_BYPASS_AUDIO_LWDF_SFT 28
+#define RG_BYPASS_AUDIO_LWDF_HI 28
+#define RG_BYPASS_AUDIO_LWDF_SZ 1
+#define RG_PDM_EDGE_SEL_MSK 0x20000000
+#define RG_PDM_EDGE_SEL_I_MSK 0xdfffffff
+#define RG_PDM_EDGE_SEL_SFT 29
+#define RG_PDM_EDGE_SEL_HI 29
+#define RG_PDM_EDGE_SEL_SZ 1
+#define RG_AUDIO_TYPE_MSK 0x40000000
+#define RG_AUDIO_TYPE_I_MSK 0xbfffffff
+#define RG_AUDIO_TYPE_SFT 30
+#define RG_AUDIO_TYPE_HI 30
+#define RG_AUDIO_TYPE_SZ 1
+#define RG_PDM_LOW_LEVEL_MSK 0x00003fff
+#define RG_PDM_LOW_LEVEL_I_MSK 0xffffc000
+#define RG_PDM_LOW_LEVEL_SFT 0
+#define RG_PDM_LOW_LEVEL_HI 13
+#define RG_PDM_LOW_LEVEL_SZ 14
+#define RG_PDM_HIGH_LEVEL_MSK 0x3fff0000
+#define RG_PDM_HIGH_LEVEL_I_MSK 0xc000ffff
+#define RG_PDM_HIGH_LEVEL_SFT 16
+#define RG_PDM_HIGH_LEVEL_HI 29
+#define RG_PDM_HIGH_LEVEL_SZ 14
+#define RG_5G_TX_BAND_F1_MSK 0x00001fff
+#define RG_5G_TX_BAND_F1_I_MSK 0xffffe000
+#define RG_5G_TX_BAND_F1_SFT 0
+#define RG_5G_TX_BAND_F1_HI 12
+#define RG_5G_TX_BAND_F1_SZ 13
+#define RG_5G_TX_BAND_F0_MSK 0x1fff0000
+#define RG_5G_TX_BAND_F0_I_MSK 0xe000ffff
+#define RG_5G_TX_BAND_F0_SFT 16
+#define RG_5G_TX_BAND_F0_HI 28
+#define RG_5G_TX_BAND_F0_SZ 13
+#define RG_5G_TX_BAND_F2_MSK 0x00001fff
+#define RG_5G_TX_BAND_F2_I_MSK 0xffffe000
+#define RG_5G_TX_BAND_F2_SFT 0
+#define RG_5G_TX_BAND_F2_HI 12
+#define RG_5G_TX_BAND_F2_SZ 13
+#define RG_DPD_5100_020_GAIN_MSK 0x000003ff
+#define RG_DPD_5100_020_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5100_020_GAIN_SFT 0
+#define RG_DPD_5100_020_GAIN_HI 9
+#define RG_DPD_5100_020_GAIN_SZ 10
+#define RG_DPD_5100_040_GAIN_MSK 0x03ff0000
+#define RG_DPD_5100_040_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5100_040_GAIN_SFT 16
+#define RG_DPD_5100_040_GAIN_HI 25
+#define RG_DPD_5100_040_GAIN_SZ 10
+#define RG_DPD_5100_060_GAIN_MSK 0x000003ff
+#define RG_DPD_5100_060_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5100_060_GAIN_SFT 0
+#define RG_DPD_5100_060_GAIN_HI 9
+#define RG_DPD_5100_060_GAIN_SZ 10
+#define RG_DPD_5100_080_GAIN_MSK 0x03ff0000
+#define RG_DPD_5100_080_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5100_080_GAIN_SFT 16
+#define RG_DPD_5100_080_GAIN_HI 25
+#define RG_DPD_5100_080_GAIN_SZ 10
+#define RG_DPD_5100_0A0_GAIN_MSK 0x000003ff
+#define RG_DPD_5100_0A0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5100_0A0_GAIN_SFT 0
+#define RG_DPD_5100_0A0_GAIN_HI 9
+#define RG_DPD_5100_0A0_GAIN_SZ 10
+#define RG_DPD_5100_0C0_GAIN_MSK 0x03ff0000
+#define RG_DPD_5100_0C0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5100_0C0_GAIN_SFT 16
+#define RG_DPD_5100_0C0_GAIN_HI 25
+#define RG_DPD_5100_0C0_GAIN_SZ 10
+#define RG_DPD_5100_0D0_GAIN_MSK 0x000003ff
+#define RG_DPD_5100_0D0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5100_0D0_GAIN_SFT 0
+#define RG_DPD_5100_0D0_GAIN_HI 9
+#define RG_DPD_5100_0D0_GAIN_SZ 10
+#define RG_DPD_5100_0E0_GAIN_MSK 0x03ff0000
+#define RG_DPD_5100_0E0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5100_0E0_GAIN_SFT 16
+#define RG_DPD_5100_0E0_GAIN_HI 25
+#define RG_DPD_5100_0E0_GAIN_SZ 10
+#define RG_DPD_5100_0F0_GAIN_MSK 0x000003ff
+#define RG_DPD_5100_0F0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5100_0F0_GAIN_SFT 0
+#define RG_DPD_5100_0F0_GAIN_HI 9
+#define RG_DPD_5100_0F0_GAIN_SZ 10
+#define RG_DPD_5100_100_GAIN_MSK 0x03ff0000
+#define RG_DPD_5100_100_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5100_100_GAIN_SFT 16
+#define RG_DPD_5100_100_GAIN_HI 25
+#define RG_DPD_5100_100_GAIN_SZ 10
+#define RG_DPD_5100_110_GAIN_MSK 0x000003ff
+#define RG_DPD_5100_110_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5100_110_GAIN_SFT 0
+#define RG_DPD_5100_110_GAIN_HI 9
+#define RG_DPD_5100_110_GAIN_SZ 10
+#define RG_DPD_5100_120_GAIN_MSK 0x03ff0000
+#define RG_DPD_5100_120_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5100_120_GAIN_SFT 16
+#define RG_DPD_5100_120_GAIN_HI 25
+#define RG_DPD_5100_120_GAIN_SZ 10
+#define RG_DPD_5100_130_GAIN_MSK 0x000003ff
+#define RG_DPD_5100_130_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5100_130_GAIN_SFT 0
+#define RG_DPD_5100_130_GAIN_HI 9
+#define RG_DPD_5100_130_GAIN_SZ 10
+#define RG_DPD_5100_140_GAIN_MSK 0x03ff0000
+#define RG_DPD_5100_140_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5100_140_GAIN_SFT 16
+#define RG_DPD_5100_140_GAIN_HI 25
+#define RG_DPD_5100_140_GAIN_SZ 10
+#define RG_DPD_5100_150_GAIN_MSK 0x000003ff
+#define RG_DPD_5100_150_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5100_150_GAIN_SFT 0
+#define RG_DPD_5100_150_GAIN_HI 9
+#define RG_DPD_5100_150_GAIN_SZ 10
+#define RG_DPD_5100_160_GAIN_MSK 0x03ff0000
+#define RG_DPD_5100_160_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5100_160_GAIN_SFT 16
+#define RG_DPD_5100_160_GAIN_HI 25
+#define RG_DPD_5100_160_GAIN_SZ 10
+#define RG_DPD_5100_170_GAIN_MSK 0x000003ff
+#define RG_DPD_5100_170_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5100_170_GAIN_SFT 0
+#define RG_DPD_5100_170_GAIN_HI 9
+#define RG_DPD_5100_170_GAIN_SZ 10
+#define RG_DPD_5100_180_GAIN_MSK 0x03ff0000
+#define RG_DPD_5100_180_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5100_180_GAIN_SFT 16
+#define RG_DPD_5100_180_GAIN_HI 25
+#define RG_DPD_5100_180_GAIN_SZ 10
+#define RG_DPD_5100_190_GAIN_MSK 0x000003ff
+#define RG_DPD_5100_190_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5100_190_GAIN_SFT 0
+#define RG_DPD_5100_190_GAIN_HI 9
+#define RG_DPD_5100_190_GAIN_SZ 10
+#define RG_DPD_5100_1A0_GAIN_MSK 0x03ff0000
+#define RG_DPD_5100_1A0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5100_1A0_GAIN_SFT 16
+#define RG_DPD_5100_1A0_GAIN_HI 25
+#define RG_DPD_5100_1A0_GAIN_SZ 10
+#define RG_DPD_5100_1B0_GAIN_MSK 0x000003ff
+#define RG_DPD_5100_1B0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5100_1B0_GAIN_SFT 0
+#define RG_DPD_5100_1B0_GAIN_HI 9
+#define RG_DPD_5100_1B0_GAIN_SZ 10
+#define RG_DPD_5100_1C0_GAIN_MSK 0x03ff0000
+#define RG_DPD_5100_1C0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5100_1C0_GAIN_SFT 16
+#define RG_DPD_5100_1C0_GAIN_HI 25
+#define RG_DPD_5100_1C0_GAIN_SZ 10
+#define RG_DPD_5100_1D0_GAIN_MSK 0x000003ff
+#define RG_DPD_5100_1D0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5100_1D0_GAIN_SFT 0
+#define RG_DPD_5100_1D0_GAIN_HI 9
+#define RG_DPD_5100_1D0_GAIN_SZ 10
+#define RG_DPD_5100_1E0_GAIN_MSK 0x03ff0000
+#define RG_DPD_5100_1E0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5100_1E0_GAIN_SFT 16
+#define RG_DPD_5100_1E0_GAIN_HI 25
+#define RG_DPD_5100_1E0_GAIN_SZ 10
+#define RG_DPD_5100_1F0_GAIN_MSK 0x000003ff
+#define RG_DPD_5100_1F0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5100_1F0_GAIN_SFT 0
+#define RG_DPD_5100_1F0_GAIN_HI 9
+#define RG_DPD_5100_1F0_GAIN_SZ 10
+#define RG_DPD_5100_200_GAIN_MSK 0x03ff0000
+#define RG_DPD_5100_200_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5100_200_GAIN_SFT 16
+#define RG_DPD_5100_200_GAIN_HI 25
+#define RG_DPD_5100_200_GAIN_SZ 10
+#define RG_DPD_5100_020_PH_MSK 0x00001fff
+#define RG_DPD_5100_020_PH_I_MSK 0xffffe000
+#define RG_DPD_5100_020_PH_SFT 0
+#define RG_DPD_5100_020_PH_HI 12
+#define RG_DPD_5100_020_PH_SZ 13
+#define RG_DPD_5100_040_PH_MSK 0x1fff0000
+#define RG_DPD_5100_040_PH_I_MSK 0xe000ffff
+#define RG_DPD_5100_040_PH_SFT 16
+#define RG_DPD_5100_040_PH_HI 28
+#define RG_DPD_5100_040_PH_SZ 13
+#define RG_DPD_5100_060_PH_MSK 0x00001fff
+#define RG_DPD_5100_060_PH_I_MSK 0xffffe000
+#define RG_DPD_5100_060_PH_SFT 0
+#define RG_DPD_5100_060_PH_HI 12
+#define RG_DPD_5100_060_PH_SZ 13
+#define RG_DPD_5100_080_PH_MSK 0x1fff0000
+#define RG_DPD_5100_080_PH_I_MSK 0xe000ffff
+#define RG_DPD_5100_080_PH_SFT 16
+#define RG_DPD_5100_080_PH_HI 28
+#define RG_DPD_5100_080_PH_SZ 13
+#define RG_DPD_5100_0A0_PH_MSK 0x00001fff
+#define RG_DPD_5100_0A0_PH_I_MSK 0xffffe000
+#define RG_DPD_5100_0A0_PH_SFT 0
+#define RG_DPD_5100_0A0_PH_HI 12
+#define RG_DPD_5100_0A0_PH_SZ 13
+#define RG_DPD_5100_0C0_PH_MSK 0x1fff0000
+#define RG_DPD_5100_0C0_PH_I_MSK 0xe000ffff
+#define RG_DPD_5100_0C0_PH_SFT 16
+#define RG_DPD_5100_0C0_PH_HI 28
+#define RG_DPD_5100_0C0_PH_SZ 13
+#define RG_DPD_5100_0D0_PH_MSK 0x00001fff
+#define RG_DPD_5100_0D0_PH_I_MSK 0xffffe000
+#define RG_DPD_5100_0D0_PH_SFT 0
+#define RG_DPD_5100_0D0_PH_HI 12
+#define RG_DPD_5100_0D0_PH_SZ 13
+#define RG_DPD_5100_0E0_PH_MSK 0x1fff0000
+#define RG_DPD_5100_0E0_PH_I_MSK 0xe000ffff
+#define RG_DPD_5100_0E0_PH_SFT 16
+#define RG_DPD_5100_0E0_PH_HI 28
+#define RG_DPD_5100_0E0_PH_SZ 13
+#define RG_DPD_5100_0F0_PH_MSK 0x00001fff
+#define RG_DPD_5100_0F0_PH_I_MSK 0xffffe000
+#define RG_DPD_5100_0F0_PH_SFT 0
+#define RG_DPD_5100_0F0_PH_HI 12
+#define RG_DPD_5100_0F0_PH_SZ 13
+#define RG_DPD_5100_100_PH_MSK 0x1fff0000
+#define RG_DPD_5100_100_PH_I_MSK 0xe000ffff
+#define RG_DPD_5100_100_PH_SFT 16
+#define RG_DPD_5100_100_PH_HI 28
+#define RG_DPD_5100_100_PH_SZ 13
+#define RG_DPD_5100_110_PH_MSK 0x00001fff
+#define RG_DPD_5100_110_PH_I_MSK 0xffffe000
+#define RG_DPD_5100_110_PH_SFT 0
+#define RG_DPD_5100_110_PH_HI 12
+#define RG_DPD_5100_110_PH_SZ 13
+#define RG_DPD_5100_120_PH_MSK 0x1fff0000
+#define RG_DPD_5100_120_PH_I_MSK 0xe000ffff
+#define RG_DPD_5100_120_PH_SFT 16
+#define RG_DPD_5100_120_PH_HI 28
+#define RG_DPD_5100_120_PH_SZ 13
+#define RG_DPD_5100_130_PH_MSK 0x00001fff
+#define RG_DPD_5100_130_PH_I_MSK 0xffffe000
+#define RG_DPD_5100_130_PH_SFT 0
+#define RG_DPD_5100_130_PH_HI 12
+#define RG_DPD_5100_130_PH_SZ 13
+#define RG_DPD_5100_140_PH_MSK 0x1fff0000
+#define RG_DPD_5100_140_PH_I_MSK 0xe000ffff
+#define RG_DPD_5100_140_PH_SFT 16
+#define RG_DPD_5100_140_PH_HI 28
+#define RG_DPD_5100_140_PH_SZ 13
+#define RG_DPD_5100_150_PH_MSK 0x00001fff
+#define RG_DPD_5100_150_PH_I_MSK 0xffffe000
+#define RG_DPD_5100_150_PH_SFT 0
+#define RG_DPD_5100_150_PH_HI 12
+#define RG_DPD_5100_150_PH_SZ 13
+#define RG_DPD_5100_160_PH_MSK 0x1fff0000
+#define RG_DPD_5100_160_PH_I_MSK 0xe000ffff
+#define RG_DPD_5100_160_PH_SFT 16
+#define RG_DPD_5100_160_PH_HI 28
+#define RG_DPD_5100_160_PH_SZ 13
+#define RG_DPD_5100_170_PH_MSK 0x00001fff
+#define RG_DPD_5100_170_PH_I_MSK 0xffffe000
+#define RG_DPD_5100_170_PH_SFT 0
+#define RG_DPD_5100_170_PH_HI 12
+#define RG_DPD_5100_170_PH_SZ 13
+#define RG_DPD_5100_180_PH_MSK 0x1fff0000
+#define RG_DPD_5100_180_PH_I_MSK 0xe000ffff
+#define RG_DPD_5100_180_PH_SFT 16
+#define RG_DPD_5100_180_PH_HI 28
+#define RG_DPD_5100_180_PH_SZ 13
+#define RG_DPD_5100_190_PH_MSK 0x00001fff
+#define RG_DPD_5100_190_PH_I_MSK 0xffffe000
+#define RG_DPD_5100_190_PH_SFT 0
+#define RG_DPD_5100_190_PH_HI 12
+#define RG_DPD_5100_190_PH_SZ 13
+#define RG_DPD_5100_1A0_PH_MSK 0x1fff0000
+#define RG_DPD_5100_1A0_PH_I_MSK 0xe000ffff
+#define RG_DPD_5100_1A0_PH_SFT 16
+#define RG_DPD_5100_1A0_PH_HI 28
+#define RG_DPD_5100_1A0_PH_SZ 13
+#define RG_DPD_5100_1B0_PH_MSK 0x00001fff
+#define RG_DPD_5100_1B0_PH_I_MSK 0xffffe000
+#define RG_DPD_5100_1B0_PH_SFT 0
+#define RG_DPD_5100_1B0_PH_HI 12
+#define RG_DPD_5100_1B0_PH_SZ 13
+#define RG_DPD_5100_1C0_PH_MSK 0x1fff0000
+#define RG_DPD_5100_1C0_PH_I_MSK 0xe000ffff
+#define RG_DPD_5100_1C0_PH_SFT 16
+#define RG_DPD_5100_1C0_PH_HI 28
+#define RG_DPD_5100_1C0_PH_SZ 13
+#define RG_DPD_5100_1D0_PH_MSK 0x00001fff
+#define RG_DPD_5100_1D0_PH_I_MSK 0xffffe000
+#define RG_DPD_5100_1D0_PH_SFT 0
+#define RG_DPD_5100_1D0_PH_HI 12
+#define RG_DPD_5100_1D0_PH_SZ 13
+#define RG_DPD_5100_1E0_PH_MSK 0x1fff0000
+#define RG_DPD_5100_1E0_PH_I_MSK 0xe000ffff
+#define RG_DPD_5100_1E0_PH_SFT 16
+#define RG_DPD_5100_1E0_PH_HI 28
+#define RG_DPD_5100_1E0_PH_SZ 13
+#define RG_DPD_5100_1F0_PH_MSK 0x00001fff
+#define RG_DPD_5100_1F0_PH_I_MSK 0xffffe000
+#define RG_DPD_5100_1F0_PH_SFT 0
+#define RG_DPD_5100_1F0_PH_HI 12
+#define RG_DPD_5100_1F0_PH_SZ 13
+#define RG_DPD_5100_200_PH_MSK 0x1fff0000
+#define RG_DPD_5100_200_PH_I_MSK 0xe000ffff
+#define RG_DPD_5100_200_PH_SFT 16
+#define RG_DPD_5100_200_PH_HI 28
+#define RG_DPD_5100_200_PH_SZ 13
+#define RG_DPD_5500_020_GAIN_MSK 0x000003ff
+#define RG_DPD_5500_020_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5500_020_GAIN_SFT 0
+#define RG_DPD_5500_020_GAIN_HI 9
+#define RG_DPD_5500_020_GAIN_SZ 10
+#define RG_DPD_5500_040_GAIN_MSK 0x03ff0000
+#define RG_DPD_5500_040_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5500_040_GAIN_SFT 16
+#define RG_DPD_5500_040_GAIN_HI 25
+#define RG_DPD_5500_040_GAIN_SZ 10
+#define RG_DPD_5500_060_GAIN_MSK 0x000003ff
+#define RG_DPD_5500_060_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5500_060_GAIN_SFT 0
+#define RG_DPD_5500_060_GAIN_HI 9
+#define RG_DPD_5500_060_GAIN_SZ 10
+#define RG_DPD_5500_080_GAIN_MSK 0x03ff0000
+#define RG_DPD_5500_080_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5500_080_GAIN_SFT 16
+#define RG_DPD_5500_080_GAIN_HI 25
+#define RG_DPD_5500_080_GAIN_SZ 10
+#define RG_DPD_5500_0A0_GAIN_MSK 0x000003ff
+#define RG_DPD_5500_0A0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5500_0A0_GAIN_SFT 0
+#define RG_DPD_5500_0A0_GAIN_HI 9
+#define RG_DPD_5500_0A0_GAIN_SZ 10
+#define RG_DPD_5500_0C0_GAIN_MSK 0x03ff0000
+#define RG_DPD_5500_0C0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5500_0C0_GAIN_SFT 16
+#define RG_DPD_5500_0C0_GAIN_HI 25
+#define RG_DPD_5500_0C0_GAIN_SZ 10
+#define RG_DPD_5500_0D0_GAIN_MSK 0x000003ff
+#define RG_DPD_5500_0D0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5500_0D0_GAIN_SFT 0
+#define RG_DPD_5500_0D0_GAIN_HI 9
+#define RG_DPD_5500_0D0_GAIN_SZ 10
+#define RG_DPD_5500_0E0_GAIN_MSK 0x03ff0000
+#define RG_DPD_5500_0E0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5500_0E0_GAIN_SFT 16
+#define RG_DPD_5500_0E0_GAIN_HI 25
+#define RG_DPD_5500_0E0_GAIN_SZ 10
+#define RG_DPD_5500_0F0_GAIN_MSK 0x000003ff
+#define RG_DPD_5500_0F0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5500_0F0_GAIN_SFT 0
+#define RG_DPD_5500_0F0_GAIN_HI 9
+#define RG_DPD_5500_0F0_GAIN_SZ 10
+#define RG_DPD_5500_100_GAIN_MSK 0x03ff0000
+#define RG_DPD_5500_100_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5500_100_GAIN_SFT 16
+#define RG_DPD_5500_100_GAIN_HI 25
+#define RG_DPD_5500_100_GAIN_SZ 10
+#define RG_DPD_5500_110_GAIN_MSK 0x000003ff
+#define RG_DPD_5500_110_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5500_110_GAIN_SFT 0
+#define RG_DPD_5500_110_GAIN_HI 9
+#define RG_DPD_5500_110_GAIN_SZ 10
+#define RG_DPD_5500_120_GAIN_MSK 0x03ff0000
+#define RG_DPD_5500_120_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5500_120_GAIN_SFT 16
+#define RG_DPD_5500_120_GAIN_HI 25
+#define RG_DPD_5500_120_GAIN_SZ 10
+#define RG_DPD_5500_130_GAIN_MSK 0x000003ff
+#define RG_DPD_5500_130_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5500_130_GAIN_SFT 0
+#define RG_DPD_5500_130_GAIN_HI 9
+#define RG_DPD_5500_130_GAIN_SZ 10
+#define RG_DPD_5500_140_GAIN_MSK 0x03ff0000
+#define RG_DPD_5500_140_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5500_140_GAIN_SFT 16
+#define RG_DPD_5500_140_GAIN_HI 25
+#define RG_DPD_5500_140_GAIN_SZ 10
+#define RG_DPD_5500_150_GAIN_MSK 0x000003ff
+#define RG_DPD_5500_150_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5500_150_GAIN_SFT 0
+#define RG_DPD_5500_150_GAIN_HI 9
+#define RG_DPD_5500_150_GAIN_SZ 10
+#define RG_DPD_5500_160_GAIN_MSK 0x03ff0000
+#define RG_DPD_5500_160_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5500_160_GAIN_SFT 16
+#define RG_DPD_5500_160_GAIN_HI 25
+#define RG_DPD_5500_160_GAIN_SZ 10
+#define RG_DPD_5500_170_GAIN_MSK 0x000003ff
+#define RG_DPD_5500_170_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5500_170_GAIN_SFT 0
+#define RG_DPD_5500_170_GAIN_HI 9
+#define RG_DPD_5500_170_GAIN_SZ 10
+#define RG_DPD_5500_180_GAIN_MSK 0x03ff0000
+#define RG_DPD_5500_180_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5500_180_GAIN_SFT 16
+#define RG_DPD_5500_180_GAIN_HI 25
+#define RG_DPD_5500_180_GAIN_SZ 10
+#define RG_DPD_5500_190_GAIN_MSK 0x000003ff
+#define RG_DPD_5500_190_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5500_190_GAIN_SFT 0
+#define RG_DPD_5500_190_GAIN_HI 9
+#define RG_DPD_5500_190_GAIN_SZ 10
+#define RG_DPD_5500_1A0_GAIN_MSK 0x03ff0000
+#define RG_DPD_5500_1A0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5500_1A0_GAIN_SFT 16
+#define RG_DPD_5500_1A0_GAIN_HI 25
+#define RG_DPD_5500_1A0_GAIN_SZ 10
+#define RG_DPD_5500_1B0_GAIN_MSK 0x000003ff
+#define RG_DPD_5500_1B0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5500_1B0_GAIN_SFT 0
+#define RG_DPD_5500_1B0_GAIN_HI 9
+#define RG_DPD_5500_1B0_GAIN_SZ 10
+#define RG_DPD_5500_1C0_GAIN_MSK 0x03ff0000
+#define RG_DPD_5500_1C0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5500_1C0_GAIN_SFT 16
+#define RG_DPD_5500_1C0_GAIN_HI 25
+#define RG_DPD_5500_1C0_GAIN_SZ 10
+#define RG_DPD_5500_1D0_GAIN_MSK 0x000003ff
+#define RG_DPD_5500_1D0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5500_1D0_GAIN_SFT 0
+#define RG_DPD_5500_1D0_GAIN_HI 9
+#define RG_DPD_5500_1D0_GAIN_SZ 10
+#define RG_DPD_5500_1E0_GAIN_MSK 0x03ff0000
+#define RG_DPD_5500_1E0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5500_1E0_GAIN_SFT 16
+#define RG_DPD_5500_1E0_GAIN_HI 25
+#define RG_DPD_5500_1E0_GAIN_SZ 10
+#define RG_DPD_5500_1F0_GAIN_MSK 0x000003ff
+#define RG_DPD_5500_1F0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5500_1F0_GAIN_SFT 0
+#define RG_DPD_5500_1F0_GAIN_HI 9
+#define RG_DPD_5500_1F0_GAIN_SZ 10
+#define RG_DPD_5500_200_GAIN_MSK 0x03ff0000
+#define RG_DPD_5500_200_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5500_200_GAIN_SFT 16
+#define RG_DPD_5500_200_GAIN_HI 25
+#define RG_DPD_5500_200_GAIN_SZ 10
+#define RG_DPD_5500_020_PH_MSK 0x00001fff
+#define RG_DPD_5500_020_PH_I_MSK 0xffffe000
+#define RG_DPD_5500_020_PH_SFT 0
+#define RG_DPD_5500_020_PH_HI 12
+#define RG_DPD_5500_020_PH_SZ 13
+#define RG_DPD_5500_040_PH_MSK 0x1fff0000
+#define RG_DPD_5500_040_PH_I_MSK 0xe000ffff
+#define RG_DPD_5500_040_PH_SFT 16
+#define RG_DPD_5500_040_PH_HI 28
+#define RG_DPD_5500_040_PH_SZ 13
+#define RG_DPD_5500_060_PH_MSK 0x00001fff
+#define RG_DPD_5500_060_PH_I_MSK 0xffffe000
+#define RG_DPD_5500_060_PH_SFT 0
+#define RG_DPD_5500_060_PH_HI 12
+#define RG_DPD_5500_060_PH_SZ 13
+#define RG_DPD_5500_080_PH_MSK 0x1fff0000
+#define RG_DPD_5500_080_PH_I_MSK 0xe000ffff
+#define RG_DPD_5500_080_PH_SFT 16
+#define RG_DPD_5500_080_PH_HI 28
+#define RG_DPD_5500_080_PH_SZ 13
+#define RG_DPD_5500_0A0_PH_MSK 0x00001fff
+#define RG_DPD_5500_0A0_PH_I_MSK 0xffffe000
+#define RG_DPD_5500_0A0_PH_SFT 0
+#define RG_DPD_5500_0A0_PH_HI 12
+#define RG_DPD_5500_0A0_PH_SZ 13
+#define RG_DPD_5500_0C0_PH_MSK 0x1fff0000
+#define RG_DPD_5500_0C0_PH_I_MSK 0xe000ffff
+#define RG_DPD_5500_0C0_PH_SFT 16
+#define RG_DPD_5500_0C0_PH_HI 28
+#define RG_DPD_5500_0C0_PH_SZ 13
+#define RG_DPD_5500_0D0_PH_MSK 0x00001fff
+#define RG_DPD_5500_0D0_PH_I_MSK 0xffffe000
+#define RG_DPD_5500_0D0_PH_SFT 0
+#define RG_DPD_5500_0D0_PH_HI 12
+#define RG_DPD_5500_0D0_PH_SZ 13
+#define RG_DPD_5500_0E0_PH_MSK 0x1fff0000
+#define RG_DPD_5500_0E0_PH_I_MSK 0xe000ffff
+#define RG_DPD_5500_0E0_PH_SFT 16
+#define RG_DPD_5500_0E0_PH_HI 28
+#define RG_DPD_5500_0E0_PH_SZ 13
+#define RG_DPD_5500_0F0_PH_MSK 0x00001fff
+#define RG_DPD_5500_0F0_PH_I_MSK 0xffffe000
+#define RG_DPD_5500_0F0_PH_SFT 0
+#define RG_DPD_5500_0F0_PH_HI 12
+#define RG_DPD_5500_0F0_PH_SZ 13
+#define RG_DPD_5500_100_PH_MSK 0x1fff0000
+#define RG_DPD_5500_100_PH_I_MSK 0xe000ffff
+#define RG_DPD_5500_100_PH_SFT 16
+#define RG_DPD_5500_100_PH_HI 28
+#define RG_DPD_5500_100_PH_SZ 13
+#define RG_DPD_5500_110_PH_MSK 0x00001fff
+#define RG_DPD_5500_110_PH_I_MSK 0xffffe000
+#define RG_DPD_5500_110_PH_SFT 0
+#define RG_DPD_5500_110_PH_HI 12
+#define RG_DPD_5500_110_PH_SZ 13
+#define RG_DPD_5500_120_PH_MSK 0x1fff0000
+#define RG_DPD_5500_120_PH_I_MSK 0xe000ffff
+#define RG_DPD_5500_120_PH_SFT 16
+#define RG_DPD_5500_120_PH_HI 28
+#define RG_DPD_5500_120_PH_SZ 13
+#define RG_DPD_5500_130_PH_MSK 0x00001fff
+#define RG_DPD_5500_130_PH_I_MSK 0xffffe000
+#define RG_DPD_5500_130_PH_SFT 0
+#define RG_DPD_5500_130_PH_HI 12
+#define RG_DPD_5500_130_PH_SZ 13
+#define RG_DPD_5500_140_PH_MSK 0x1fff0000
+#define RG_DPD_5500_140_PH_I_MSK 0xe000ffff
+#define RG_DPD_5500_140_PH_SFT 16
+#define RG_DPD_5500_140_PH_HI 28
+#define RG_DPD_5500_140_PH_SZ 13
+#define RG_DPD_5500_150_PH_MSK 0x00001fff
+#define RG_DPD_5500_150_PH_I_MSK 0xffffe000
+#define RG_DPD_5500_150_PH_SFT 0
+#define RG_DPD_5500_150_PH_HI 12
+#define RG_DPD_5500_150_PH_SZ 13
+#define RG_DPD_5500_160_PH_MSK 0x1fff0000
+#define RG_DPD_5500_160_PH_I_MSK 0xe000ffff
+#define RG_DPD_5500_160_PH_SFT 16
+#define RG_DPD_5500_160_PH_HI 28
+#define RG_DPD_5500_160_PH_SZ 13
+#define RG_DPD_5500_170_PH_MSK 0x00001fff
+#define RG_DPD_5500_170_PH_I_MSK 0xffffe000
+#define RG_DPD_5500_170_PH_SFT 0
+#define RG_DPD_5500_170_PH_HI 12
+#define RG_DPD_5500_170_PH_SZ 13
+#define RG_DPD_5500_180_PH_MSK 0x1fff0000
+#define RG_DPD_5500_180_PH_I_MSK 0xe000ffff
+#define RG_DPD_5500_180_PH_SFT 16
+#define RG_DPD_5500_180_PH_HI 28
+#define RG_DPD_5500_180_PH_SZ 13
+#define RG_DPD_5500_190_PH_MSK 0x00001fff
+#define RG_DPD_5500_190_PH_I_MSK 0xffffe000
+#define RG_DPD_5500_190_PH_SFT 0
+#define RG_DPD_5500_190_PH_HI 12
+#define RG_DPD_5500_190_PH_SZ 13
+#define RG_DPD_5500_1A0_PH_MSK 0x1fff0000
+#define RG_DPD_5500_1A0_PH_I_MSK 0xe000ffff
+#define RG_DPD_5500_1A0_PH_SFT 16
+#define RG_DPD_5500_1A0_PH_HI 28
+#define RG_DPD_5500_1A0_PH_SZ 13
+#define RG_DPD_5500_1B0_PH_MSK 0x00001fff
+#define RG_DPD_5500_1B0_PH_I_MSK 0xffffe000
+#define RG_DPD_5500_1B0_PH_SFT 0
+#define RG_DPD_5500_1B0_PH_HI 12
+#define RG_DPD_5500_1B0_PH_SZ 13
+#define RG_DPD_5500_1C0_PH_MSK 0x1fff0000
+#define RG_DPD_5500_1C0_PH_I_MSK 0xe000ffff
+#define RG_DPD_5500_1C0_PH_SFT 16
+#define RG_DPD_5500_1C0_PH_HI 28
+#define RG_DPD_5500_1C0_PH_SZ 13
+#define RG_DPD_5500_1D0_PH_MSK 0x00001fff
+#define RG_DPD_5500_1D0_PH_I_MSK 0xffffe000
+#define RG_DPD_5500_1D0_PH_SFT 0
+#define RG_DPD_5500_1D0_PH_HI 12
+#define RG_DPD_5500_1D0_PH_SZ 13
+#define RG_DPD_5500_1E0_PH_MSK 0x1fff0000
+#define RG_DPD_5500_1E0_PH_I_MSK 0xe000ffff
+#define RG_DPD_5500_1E0_PH_SFT 16
+#define RG_DPD_5500_1E0_PH_HI 28
+#define RG_DPD_5500_1E0_PH_SZ 13
+#define RG_DPD_5500_1F0_PH_MSK 0x00001fff
+#define RG_DPD_5500_1F0_PH_I_MSK 0xffffe000
+#define RG_DPD_5500_1F0_PH_SFT 0
+#define RG_DPD_5500_1F0_PH_HI 12
+#define RG_DPD_5500_1F0_PH_SZ 13
+#define RG_DPD_5500_200_PH_MSK 0x1fff0000
+#define RG_DPD_5500_200_PH_I_MSK 0xe000ffff
+#define RG_DPD_5500_200_PH_SFT 16
+#define RG_DPD_5500_200_PH_HI 28
+#define RG_DPD_5500_200_PH_SZ 13
+#define RG_DPD_5700_020_GAIN_MSK 0x000003ff
+#define RG_DPD_5700_020_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5700_020_GAIN_SFT 0
+#define RG_DPD_5700_020_GAIN_HI 9
+#define RG_DPD_5700_020_GAIN_SZ 10
+#define RG_DPD_5700_040_GAIN_MSK 0x03ff0000
+#define RG_DPD_5700_040_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5700_040_GAIN_SFT 16
+#define RG_DPD_5700_040_GAIN_HI 25
+#define RG_DPD_5700_040_GAIN_SZ 10
+#define RG_DPD_5700_060_GAIN_MSK 0x000003ff
+#define RG_DPD_5700_060_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5700_060_GAIN_SFT 0
+#define RG_DPD_5700_060_GAIN_HI 9
+#define RG_DPD_5700_060_GAIN_SZ 10
+#define RG_DPD_5700_080_GAIN_MSK 0x03ff0000
+#define RG_DPD_5700_080_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5700_080_GAIN_SFT 16
+#define RG_DPD_5700_080_GAIN_HI 25
+#define RG_DPD_5700_080_GAIN_SZ 10
+#define RG_DPD_5700_0A0_GAIN_MSK 0x000003ff
+#define RG_DPD_5700_0A0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5700_0A0_GAIN_SFT 0
+#define RG_DPD_5700_0A0_GAIN_HI 9
+#define RG_DPD_5700_0A0_GAIN_SZ 10
+#define RG_DPD_5700_0C0_GAIN_MSK 0x03ff0000
+#define RG_DPD_5700_0C0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5700_0C0_GAIN_SFT 16
+#define RG_DPD_5700_0C0_GAIN_HI 25
+#define RG_DPD_5700_0C0_GAIN_SZ 10
+#define RG_DPD_5700_0D0_GAIN_MSK 0x000003ff
+#define RG_DPD_5700_0D0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5700_0D0_GAIN_SFT 0
+#define RG_DPD_5700_0D0_GAIN_HI 9
+#define RG_DPD_5700_0D0_GAIN_SZ 10
+#define RG_DPD_5700_0E0_GAIN_MSK 0x03ff0000
+#define RG_DPD_5700_0E0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5700_0E0_GAIN_SFT 16
+#define RG_DPD_5700_0E0_GAIN_HI 25
+#define RG_DPD_5700_0E0_GAIN_SZ 10
+#define RG_DPD_5700_0F0_GAIN_MSK 0x000003ff
+#define RG_DPD_5700_0F0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5700_0F0_GAIN_SFT 0
+#define RG_DPD_5700_0F0_GAIN_HI 9
+#define RG_DPD_5700_0F0_GAIN_SZ 10
+#define RG_DPD_5700_100_GAIN_MSK 0x03ff0000
+#define RG_DPD_5700_100_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5700_100_GAIN_SFT 16
+#define RG_DPD_5700_100_GAIN_HI 25
+#define RG_DPD_5700_100_GAIN_SZ 10
+#define RG_DPD_5700_110_GAIN_MSK 0x000003ff
+#define RG_DPD_5700_110_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5700_110_GAIN_SFT 0
+#define RG_DPD_5700_110_GAIN_HI 9
+#define RG_DPD_5700_110_GAIN_SZ 10
+#define RG_DPD_5700_120_GAIN_MSK 0x03ff0000
+#define RG_DPD_5700_120_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5700_120_GAIN_SFT 16
+#define RG_DPD_5700_120_GAIN_HI 25
+#define RG_DPD_5700_120_GAIN_SZ 10
+#define RG_DPD_5700_130_GAIN_MSK 0x000003ff
+#define RG_DPD_5700_130_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5700_130_GAIN_SFT 0
+#define RG_DPD_5700_130_GAIN_HI 9
+#define RG_DPD_5700_130_GAIN_SZ 10
+#define RG_DPD_5700_140_GAIN_MSK 0x03ff0000
+#define RG_DPD_5700_140_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5700_140_GAIN_SFT 16
+#define RG_DPD_5700_140_GAIN_HI 25
+#define RG_DPD_5700_140_GAIN_SZ 10
+#define RG_DPD_5700_150_GAIN_MSK 0x000003ff
+#define RG_DPD_5700_150_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5700_150_GAIN_SFT 0
+#define RG_DPD_5700_150_GAIN_HI 9
+#define RG_DPD_5700_150_GAIN_SZ 10
+#define RG_DPD_5700_160_GAIN_MSK 0x03ff0000
+#define RG_DPD_5700_160_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5700_160_GAIN_SFT 16
+#define RG_DPD_5700_160_GAIN_HI 25
+#define RG_DPD_5700_160_GAIN_SZ 10
+#define RG_DPD_5700_170_GAIN_MSK 0x000003ff
+#define RG_DPD_5700_170_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5700_170_GAIN_SFT 0
+#define RG_DPD_5700_170_GAIN_HI 9
+#define RG_DPD_5700_170_GAIN_SZ 10
+#define RG_DPD_5700_180_GAIN_MSK 0x03ff0000
+#define RG_DPD_5700_180_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5700_180_GAIN_SFT 16
+#define RG_DPD_5700_180_GAIN_HI 25
+#define RG_DPD_5700_180_GAIN_SZ 10
+#define RG_DPD_5700_190_GAIN_MSK 0x000003ff
+#define RG_DPD_5700_190_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5700_190_GAIN_SFT 0
+#define RG_DPD_5700_190_GAIN_HI 9
+#define RG_DPD_5700_190_GAIN_SZ 10
+#define RG_DPD_5700_1A0_GAIN_MSK 0x03ff0000
+#define RG_DPD_5700_1A0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5700_1A0_GAIN_SFT 16
+#define RG_DPD_5700_1A0_GAIN_HI 25
+#define RG_DPD_5700_1A0_GAIN_SZ 10
+#define RG_DPD_5700_1B0_GAIN_MSK 0x000003ff
+#define RG_DPD_5700_1B0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5700_1B0_GAIN_SFT 0
+#define RG_DPD_5700_1B0_GAIN_HI 9
+#define RG_DPD_5700_1B0_GAIN_SZ 10
+#define RG_DPD_5700_1C0_GAIN_MSK 0x03ff0000
+#define RG_DPD_5700_1C0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5700_1C0_GAIN_SFT 16
+#define RG_DPD_5700_1C0_GAIN_HI 25
+#define RG_DPD_5700_1C0_GAIN_SZ 10
+#define RG_DPD_5700_1D0_GAIN_MSK 0x000003ff
+#define RG_DPD_5700_1D0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5700_1D0_GAIN_SFT 0
+#define RG_DPD_5700_1D0_GAIN_HI 9
+#define RG_DPD_5700_1D0_GAIN_SZ 10
+#define RG_DPD_5700_1E0_GAIN_MSK 0x03ff0000
+#define RG_DPD_5700_1E0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5700_1E0_GAIN_SFT 16
+#define RG_DPD_5700_1E0_GAIN_HI 25
+#define RG_DPD_5700_1E0_GAIN_SZ 10
+#define RG_DPD_5700_1F0_GAIN_MSK 0x000003ff
+#define RG_DPD_5700_1F0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5700_1F0_GAIN_SFT 0
+#define RG_DPD_5700_1F0_GAIN_HI 9
+#define RG_DPD_5700_1F0_GAIN_SZ 10
+#define RG_DPD_5700_200_GAIN_MSK 0x03ff0000
+#define RG_DPD_5700_200_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5700_200_GAIN_SFT 16
+#define RG_DPD_5700_200_GAIN_HI 25
+#define RG_DPD_5700_200_GAIN_SZ 10
+#define RG_DPD_5700_020_PH_MSK 0x00001fff
+#define RG_DPD_5700_020_PH_I_MSK 0xffffe000
+#define RG_DPD_5700_020_PH_SFT 0
+#define RG_DPD_5700_020_PH_HI 12
+#define RG_DPD_5700_020_PH_SZ 13
+#define RG_DPD_5700_040_PH_MSK 0x1fff0000
+#define RG_DPD_5700_040_PH_I_MSK 0xe000ffff
+#define RG_DPD_5700_040_PH_SFT 16
+#define RG_DPD_5700_040_PH_HI 28
+#define RG_DPD_5700_040_PH_SZ 13
+#define RG_DPD_5700_060_PH_MSK 0x00001fff
+#define RG_DPD_5700_060_PH_I_MSK 0xffffe000
+#define RG_DPD_5700_060_PH_SFT 0
+#define RG_DPD_5700_060_PH_HI 12
+#define RG_DPD_5700_060_PH_SZ 13
+#define RG_DPD_5700_080_PH_MSK 0x1fff0000
+#define RG_DPD_5700_080_PH_I_MSK 0xe000ffff
+#define RG_DPD_5700_080_PH_SFT 16
+#define RG_DPD_5700_080_PH_HI 28
+#define RG_DPD_5700_080_PH_SZ 13
+#define RG_DPD_5700_0A0_PH_MSK 0x00001fff
+#define RG_DPD_5700_0A0_PH_I_MSK 0xffffe000
+#define RG_DPD_5700_0A0_PH_SFT 0
+#define RG_DPD_5700_0A0_PH_HI 12
+#define RG_DPD_5700_0A0_PH_SZ 13
+#define RG_DPD_5700_0C0_PH_MSK 0x1fff0000
+#define RG_DPD_5700_0C0_PH_I_MSK 0xe000ffff
+#define RG_DPD_5700_0C0_PH_SFT 16
+#define RG_DPD_5700_0C0_PH_HI 28
+#define RG_DPD_5700_0C0_PH_SZ 13
+#define RG_DPD_5700_0D0_PH_MSK 0x00001fff
+#define RG_DPD_5700_0D0_PH_I_MSK 0xffffe000
+#define RG_DPD_5700_0D0_PH_SFT 0
+#define RG_DPD_5700_0D0_PH_HI 12
+#define RG_DPD_5700_0D0_PH_SZ 13
+#define RG_DPD_5700_0E0_PH_MSK 0x1fff0000
+#define RG_DPD_5700_0E0_PH_I_MSK 0xe000ffff
+#define RG_DPD_5700_0E0_PH_SFT 16
+#define RG_DPD_5700_0E0_PH_HI 28
+#define RG_DPD_5700_0E0_PH_SZ 13
+#define RG_DPD_5700_0F0_PH_MSK 0x00001fff
+#define RG_DPD_5700_0F0_PH_I_MSK 0xffffe000
+#define RG_DPD_5700_0F0_PH_SFT 0
+#define RG_DPD_5700_0F0_PH_HI 12
+#define RG_DPD_5700_0F0_PH_SZ 13
+#define RG_DPD_5700_100_PH_MSK 0x1fff0000
+#define RG_DPD_5700_100_PH_I_MSK 0xe000ffff
+#define RG_DPD_5700_100_PH_SFT 16
+#define RG_DPD_5700_100_PH_HI 28
+#define RG_DPD_5700_100_PH_SZ 13
+#define RG_DPD_5700_110_PH_MSK 0x00001fff
+#define RG_DPD_5700_110_PH_I_MSK 0xffffe000
+#define RG_DPD_5700_110_PH_SFT 0
+#define RG_DPD_5700_110_PH_HI 12
+#define RG_DPD_5700_110_PH_SZ 13
+#define RG_DPD_5700_120_PH_MSK 0x1fff0000
+#define RG_DPD_5700_120_PH_I_MSK 0xe000ffff
+#define RG_DPD_5700_120_PH_SFT 16
+#define RG_DPD_5700_120_PH_HI 28
+#define RG_DPD_5700_120_PH_SZ 13
+#define RG_DPD_5700_130_PH_MSK 0x00001fff
+#define RG_DPD_5700_130_PH_I_MSK 0xffffe000
+#define RG_DPD_5700_130_PH_SFT 0
+#define RG_DPD_5700_130_PH_HI 12
+#define RG_DPD_5700_130_PH_SZ 13
+#define RG_DPD_5700_140_PH_MSK 0x1fff0000
+#define RG_DPD_5700_140_PH_I_MSK 0xe000ffff
+#define RG_DPD_5700_140_PH_SFT 16
+#define RG_DPD_5700_140_PH_HI 28
+#define RG_DPD_5700_140_PH_SZ 13
+#define RG_DPD_5700_150_PH_MSK 0x00001fff
+#define RG_DPD_5700_150_PH_I_MSK 0xffffe000
+#define RG_DPD_5700_150_PH_SFT 0
+#define RG_DPD_5700_150_PH_HI 12
+#define RG_DPD_5700_150_PH_SZ 13
+#define RG_DPD_5700_160_PH_MSK 0x1fff0000
+#define RG_DPD_5700_160_PH_I_MSK 0xe000ffff
+#define RG_DPD_5700_160_PH_SFT 16
+#define RG_DPD_5700_160_PH_HI 28
+#define RG_DPD_5700_160_PH_SZ 13
+#define RG_DPD_5700_170_PH_MSK 0x00001fff
+#define RG_DPD_5700_170_PH_I_MSK 0xffffe000
+#define RG_DPD_5700_170_PH_SFT 0
+#define RG_DPD_5700_170_PH_HI 12
+#define RG_DPD_5700_170_PH_SZ 13
+#define RG_DPD_5700_180_PH_MSK 0x1fff0000
+#define RG_DPD_5700_180_PH_I_MSK 0xe000ffff
+#define RG_DPD_5700_180_PH_SFT 16
+#define RG_DPD_5700_180_PH_HI 28
+#define RG_DPD_5700_180_PH_SZ 13
+#define RG_DPD_5700_190_PH_MSK 0x00001fff
+#define RG_DPD_5700_190_PH_I_MSK 0xffffe000
+#define RG_DPD_5700_190_PH_SFT 0
+#define RG_DPD_5700_190_PH_HI 12
+#define RG_DPD_5700_190_PH_SZ 13
+#define RG_DPD_5700_1A0_PH_MSK 0x1fff0000
+#define RG_DPD_5700_1A0_PH_I_MSK 0xe000ffff
+#define RG_DPD_5700_1A0_PH_SFT 16
+#define RG_DPD_5700_1A0_PH_HI 28
+#define RG_DPD_5700_1A0_PH_SZ 13
+#define RG_DPD_5700_1B0_PH_MSK 0x00001fff
+#define RG_DPD_5700_1B0_PH_I_MSK 0xffffe000
+#define RG_DPD_5700_1B0_PH_SFT 0
+#define RG_DPD_5700_1B0_PH_HI 12
+#define RG_DPD_5700_1B0_PH_SZ 13
+#define RG_DPD_5700_1C0_PH_MSK 0x1fff0000
+#define RG_DPD_5700_1C0_PH_I_MSK 0xe000ffff
+#define RG_DPD_5700_1C0_PH_SFT 16
+#define RG_DPD_5700_1C0_PH_HI 28
+#define RG_DPD_5700_1C0_PH_SZ 13
+#define RG_DPD_5700_1D0_PH_MSK 0x00001fff
+#define RG_DPD_5700_1D0_PH_I_MSK 0xffffe000
+#define RG_DPD_5700_1D0_PH_SFT 0
+#define RG_DPD_5700_1D0_PH_HI 12
+#define RG_DPD_5700_1D0_PH_SZ 13
+#define RG_DPD_5700_1E0_PH_MSK 0x1fff0000
+#define RG_DPD_5700_1E0_PH_I_MSK 0xe000ffff
+#define RG_DPD_5700_1E0_PH_SFT 16
+#define RG_DPD_5700_1E0_PH_HI 28
+#define RG_DPD_5700_1E0_PH_SZ 13
+#define RG_DPD_5700_1F0_PH_MSK 0x00001fff
+#define RG_DPD_5700_1F0_PH_I_MSK 0xffffe000
+#define RG_DPD_5700_1F0_PH_SFT 0
+#define RG_DPD_5700_1F0_PH_HI 12
+#define RG_DPD_5700_1F0_PH_SZ 13
+#define RG_DPD_5700_200_PH_MSK 0x1fff0000
+#define RG_DPD_5700_200_PH_I_MSK 0xe000ffff
+#define RG_DPD_5700_200_PH_SFT 16
+#define RG_DPD_5700_200_PH_HI 28
+#define RG_DPD_5700_200_PH_SZ 13
+#define RG_DPD_5900_020_GAIN_MSK 0x000003ff
+#define RG_DPD_5900_020_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5900_020_GAIN_SFT 0
+#define RG_DPD_5900_020_GAIN_HI 9
+#define RG_DPD_5900_020_GAIN_SZ 10
+#define RG_DPD_5900_040_GAIN_MSK 0x03ff0000
+#define RG_DPD_5900_040_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5900_040_GAIN_SFT 16
+#define RG_DPD_5900_040_GAIN_HI 25
+#define RG_DPD_5900_040_GAIN_SZ 10
+#define RG_DPD_5900_060_GAIN_MSK 0x000003ff
+#define RG_DPD_5900_060_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5900_060_GAIN_SFT 0
+#define RG_DPD_5900_060_GAIN_HI 9
+#define RG_DPD_5900_060_GAIN_SZ 10
+#define RG_DPD_5900_080_GAIN_MSK 0x03ff0000
+#define RG_DPD_5900_080_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5900_080_GAIN_SFT 16
+#define RG_DPD_5900_080_GAIN_HI 25
+#define RG_DPD_5900_080_GAIN_SZ 10
+#define RG_DPD_5900_0A0_GAIN_MSK 0x000003ff
+#define RG_DPD_5900_0A0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5900_0A0_GAIN_SFT 0
+#define RG_DPD_5900_0A0_GAIN_HI 9
+#define RG_DPD_5900_0A0_GAIN_SZ 10
+#define RG_DPD_5900_0C0_GAIN_MSK 0x03ff0000
+#define RG_DPD_5900_0C0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5900_0C0_GAIN_SFT 16
+#define RG_DPD_5900_0C0_GAIN_HI 25
+#define RG_DPD_5900_0C0_GAIN_SZ 10
+#define RG_DPD_5900_0D0_GAIN_MSK 0x000003ff
+#define RG_DPD_5900_0D0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5900_0D0_GAIN_SFT 0
+#define RG_DPD_5900_0D0_GAIN_HI 9
+#define RG_DPD_5900_0D0_GAIN_SZ 10
+#define RG_DPD_5900_0E0_GAIN_MSK 0x03ff0000
+#define RG_DPD_5900_0E0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5900_0E0_GAIN_SFT 16
+#define RG_DPD_5900_0E0_GAIN_HI 25
+#define RG_DPD_5900_0E0_GAIN_SZ 10
+#define RG_DPD_5900_0F0_GAIN_MSK 0x000003ff
+#define RG_DPD_5900_0F0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5900_0F0_GAIN_SFT 0
+#define RG_DPD_5900_0F0_GAIN_HI 9
+#define RG_DPD_5900_0F0_GAIN_SZ 10
+#define RG_DPD_5900_100_GAIN_MSK 0x03ff0000
+#define RG_DPD_5900_100_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5900_100_GAIN_SFT 16
+#define RG_DPD_5900_100_GAIN_HI 25
+#define RG_DPD_5900_100_GAIN_SZ 10
+#define RG_DPD_5900_110_GAIN_MSK 0x000003ff
+#define RG_DPD_5900_110_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5900_110_GAIN_SFT 0
+#define RG_DPD_5900_110_GAIN_HI 9
+#define RG_DPD_5900_110_GAIN_SZ 10
+#define RG_DPD_5900_120_GAIN_MSK 0x03ff0000
+#define RG_DPD_5900_120_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5900_120_GAIN_SFT 16
+#define RG_DPD_5900_120_GAIN_HI 25
+#define RG_DPD_5900_120_GAIN_SZ 10
+#define RG_DPD_5900_130_GAIN_MSK 0x000003ff
+#define RG_DPD_5900_130_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5900_130_GAIN_SFT 0
+#define RG_DPD_5900_130_GAIN_HI 9
+#define RG_DPD_5900_130_GAIN_SZ 10
+#define RG_DPD_5900_140_GAIN_MSK 0x03ff0000
+#define RG_DPD_5900_140_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5900_140_GAIN_SFT 16
+#define RG_DPD_5900_140_GAIN_HI 25
+#define RG_DPD_5900_140_GAIN_SZ 10
+#define RG_DPD_5900_150_GAIN_MSK 0x000003ff
+#define RG_DPD_5900_150_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5900_150_GAIN_SFT 0
+#define RG_DPD_5900_150_GAIN_HI 9
+#define RG_DPD_5900_150_GAIN_SZ 10
+#define RG_DPD_5900_160_GAIN_MSK 0x03ff0000
+#define RG_DPD_5900_160_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5900_160_GAIN_SFT 16
+#define RG_DPD_5900_160_GAIN_HI 25
+#define RG_DPD_5900_160_GAIN_SZ 10
+#define RG_DPD_5900_170_GAIN_MSK 0x000003ff
+#define RG_DPD_5900_170_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5900_170_GAIN_SFT 0
+#define RG_DPD_5900_170_GAIN_HI 9
+#define RG_DPD_5900_170_GAIN_SZ 10
+#define RG_DPD_5900_180_GAIN_MSK 0x03ff0000
+#define RG_DPD_5900_180_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5900_180_GAIN_SFT 16
+#define RG_DPD_5900_180_GAIN_HI 25
+#define RG_DPD_5900_180_GAIN_SZ 10
+#define RG_DPD_5900_190_GAIN_MSK 0x000003ff
+#define RG_DPD_5900_190_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5900_190_GAIN_SFT 0
+#define RG_DPD_5900_190_GAIN_HI 9
+#define RG_DPD_5900_190_GAIN_SZ 10
+#define RG_DPD_5900_1A0_GAIN_MSK 0x03ff0000
+#define RG_DPD_5900_1A0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5900_1A0_GAIN_SFT 16
+#define RG_DPD_5900_1A0_GAIN_HI 25
+#define RG_DPD_5900_1A0_GAIN_SZ 10
+#define RG_DPD_5900_1B0_GAIN_MSK 0x000003ff
+#define RG_DPD_5900_1B0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5900_1B0_GAIN_SFT 0
+#define RG_DPD_5900_1B0_GAIN_HI 9
+#define RG_DPD_5900_1B0_GAIN_SZ 10
+#define RG_DPD_5900_1C0_GAIN_MSK 0x03ff0000
+#define RG_DPD_5900_1C0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5900_1C0_GAIN_SFT 16
+#define RG_DPD_5900_1C0_GAIN_HI 25
+#define RG_DPD_5900_1C0_GAIN_SZ 10
+#define RG_DPD_5900_1D0_GAIN_MSK 0x000003ff
+#define RG_DPD_5900_1D0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5900_1D0_GAIN_SFT 0
+#define RG_DPD_5900_1D0_GAIN_HI 9
+#define RG_DPD_5900_1D0_GAIN_SZ 10
+#define RG_DPD_5900_1E0_GAIN_MSK 0x03ff0000
+#define RG_DPD_5900_1E0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5900_1E0_GAIN_SFT 16
+#define RG_DPD_5900_1E0_GAIN_HI 25
+#define RG_DPD_5900_1E0_GAIN_SZ 10
+#define RG_DPD_5900_1F0_GAIN_MSK 0x000003ff
+#define RG_DPD_5900_1F0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_5900_1F0_GAIN_SFT 0
+#define RG_DPD_5900_1F0_GAIN_HI 9
+#define RG_DPD_5900_1F0_GAIN_SZ 10
+#define RG_DPD_5900_200_GAIN_MSK 0x03ff0000
+#define RG_DPD_5900_200_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_5900_200_GAIN_SFT 16
+#define RG_DPD_5900_200_GAIN_HI 25
+#define RG_DPD_5900_200_GAIN_SZ 10
+#define RG_DPD_5900_020_PH_MSK 0x00001fff
+#define RG_DPD_5900_020_PH_I_MSK 0xffffe000
+#define RG_DPD_5900_020_PH_SFT 0
+#define RG_DPD_5900_020_PH_HI 12
+#define RG_DPD_5900_020_PH_SZ 13
+#define RG_DPD_5900_040_PH_MSK 0x1fff0000
+#define RG_DPD_5900_040_PH_I_MSK 0xe000ffff
+#define RG_DPD_5900_040_PH_SFT 16
+#define RG_DPD_5900_040_PH_HI 28
+#define RG_DPD_5900_040_PH_SZ 13
+#define RG_DPD_5900_060_PH_MSK 0x00001fff
+#define RG_DPD_5900_060_PH_I_MSK 0xffffe000
+#define RG_DPD_5900_060_PH_SFT 0
+#define RG_DPD_5900_060_PH_HI 12
+#define RG_DPD_5900_060_PH_SZ 13
+#define RG_DPD_5900_080_PH_MSK 0x1fff0000
+#define RG_DPD_5900_080_PH_I_MSK 0xe000ffff
+#define RG_DPD_5900_080_PH_SFT 16
+#define RG_DPD_5900_080_PH_HI 28
+#define RG_DPD_5900_080_PH_SZ 13
+#define RG_DPD_5900_0A0_PH_MSK 0x00001fff
+#define RG_DPD_5900_0A0_PH_I_MSK 0xffffe000
+#define RG_DPD_5900_0A0_PH_SFT 0
+#define RG_DPD_5900_0A0_PH_HI 12
+#define RG_DPD_5900_0A0_PH_SZ 13
+#define RG_DPD_5900_0C0_PH_MSK 0x1fff0000
+#define RG_DPD_5900_0C0_PH_I_MSK 0xe000ffff
+#define RG_DPD_5900_0C0_PH_SFT 16
+#define RG_DPD_5900_0C0_PH_HI 28
+#define RG_DPD_5900_0C0_PH_SZ 13
+#define RG_DPD_5900_0D0_PH_MSK 0x00001fff
+#define RG_DPD_5900_0D0_PH_I_MSK 0xffffe000
+#define RG_DPD_5900_0D0_PH_SFT 0
+#define RG_DPD_5900_0D0_PH_HI 12
+#define RG_DPD_5900_0D0_PH_SZ 13
+#define RG_DPD_5900_0E0_PH_MSK 0x1fff0000
+#define RG_DPD_5900_0E0_PH_I_MSK 0xe000ffff
+#define RG_DPD_5900_0E0_PH_SFT 16
+#define RG_DPD_5900_0E0_PH_HI 28
+#define RG_DPD_5900_0E0_PH_SZ 13
+#define RG_DPD_5900_0F0_PH_MSK 0x00001fff
+#define RG_DPD_5900_0F0_PH_I_MSK 0xffffe000
+#define RG_DPD_5900_0F0_PH_SFT 0
+#define RG_DPD_5900_0F0_PH_HI 12
+#define RG_DPD_5900_0F0_PH_SZ 13
+#define RG_DPD_5900_100_PH_MSK 0x1fff0000
+#define RG_DPD_5900_100_PH_I_MSK 0xe000ffff
+#define RG_DPD_5900_100_PH_SFT 16
+#define RG_DPD_5900_100_PH_HI 28
+#define RG_DPD_5900_100_PH_SZ 13
+#define RG_DPD_5900_110_PH_MSK 0x00001fff
+#define RG_DPD_5900_110_PH_I_MSK 0xffffe000
+#define RG_DPD_5900_110_PH_SFT 0
+#define RG_DPD_5900_110_PH_HI 12
+#define RG_DPD_5900_110_PH_SZ 13
+#define RG_DPD_5900_120_PH_MSK 0x1fff0000
+#define RG_DPD_5900_120_PH_I_MSK 0xe000ffff
+#define RG_DPD_5900_120_PH_SFT 16
+#define RG_DPD_5900_120_PH_HI 28
+#define RG_DPD_5900_120_PH_SZ 13
+#define RG_DPD_5900_130_PH_MSK 0x00001fff
+#define RG_DPD_5900_130_PH_I_MSK 0xffffe000
+#define RG_DPD_5900_130_PH_SFT 0
+#define RG_DPD_5900_130_PH_HI 12
+#define RG_DPD_5900_130_PH_SZ 13
+#define RG_DPD_5900_140_PH_MSK 0x1fff0000
+#define RG_DPD_5900_140_PH_I_MSK 0xe000ffff
+#define RG_DPD_5900_140_PH_SFT 16
+#define RG_DPD_5900_140_PH_HI 28
+#define RG_DPD_5900_140_PH_SZ 13
+#define RG_DPD_5900_150_PH_MSK 0x00001fff
+#define RG_DPD_5900_150_PH_I_MSK 0xffffe000
+#define RG_DPD_5900_150_PH_SFT 0
+#define RG_DPD_5900_150_PH_HI 12
+#define RG_DPD_5900_150_PH_SZ 13
+#define RG_DPD_5900_160_PH_MSK 0x1fff0000
+#define RG_DPD_5900_160_PH_I_MSK 0xe000ffff
+#define RG_DPD_5900_160_PH_SFT 16
+#define RG_DPD_5900_160_PH_HI 28
+#define RG_DPD_5900_160_PH_SZ 13
+#define RG_DPD_5900_170_PH_MSK 0x00001fff
+#define RG_DPD_5900_170_PH_I_MSK 0xffffe000
+#define RG_DPD_5900_170_PH_SFT 0
+#define RG_DPD_5900_170_PH_HI 12
+#define RG_DPD_5900_170_PH_SZ 13
+#define RG_DPD_5900_180_PH_MSK 0x1fff0000
+#define RG_DPD_5900_180_PH_I_MSK 0xe000ffff
+#define RG_DPD_5900_180_PH_SFT 16
+#define RG_DPD_5900_180_PH_HI 28
+#define RG_DPD_5900_180_PH_SZ 13
+#define RG_DPD_5900_190_PH_MSK 0x00001fff
+#define RG_DPD_5900_190_PH_I_MSK 0xffffe000
+#define RG_DPD_5900_190_PH_SFT 0
+#define RG_DPD_5900_190_PH_HI 12
+#define RG_DPD_5900_190_PH_SZ 13
+#define RG_DPD_5900_1A0_PH_MSK 0x1fff0000
+#define RG_DPD_5900_1A0_PH_I_MSK 0xe000ffff
+#define RG_DPD_5900_1A0_PH_SFT 16
+#define RG_DPD_5900_1A0_PH_HI 28
+#define RG_DPD_5900_1A0_PH_SZ 13
+#define RG_DPD_5900_1B0_PH_MSK 0x00001fff
+#define RG_DPD_5900_1B0_PH_I_MSK 0xffffe000
+#define RG_DPD_5900_1B0_PH_SFT 0
+#define RG_DPD_5900_1B0_PH_HI 12
+#define RG_DPD_5900_1B0_PH_SZ 13
+#define RG_DPD_5900_1C0_PH_MSK 0x1fff0000
+#define RG_DPD_5900_1C0_PH_I_MSK 0xe000ffff
+#define RG_DPD_5900_1C0_PH_SFT 16
+#define RG_DPD_5900_1C0_PH_HI 28
+#define RG_DPD_5900_1C0_PH_SZ 13
+#define RG_DPD_5900_1D0_PH_MSK 0x00001fff
+#define RG_DPD_5900_1D0_PH_I_MSK 0xffffe000
+#define RG_DPD_5900_1D0_PH_SFT 0
+#define RG_DPD_5900_1D0_PH_HI 12
+#define RG_DPD_5900_1D0_PH_SZ 13
+#define RG_DPD_5900_1E0_PH_MSK 0x1fff0000
+#define RG_DPD_5900_1E0_PH_I_MSK 0xe000ffff
+#define RG_DPD_5900_1E0_PH_SFT 16
+#define RG_DPD_5900_1E0_PH_HI 28
+#define RG_DPD_5900_1E0_PH_SZ 13
+#define RG_DPD_5900_1F0_PH_MSK 0x00001fff
+#define RG_DPD_5900_1F0_PH_I_MSK 0xffffe000
+#define RG_DPD_5900_1F0_PH_SFT 0
+#define RG_DPD_5900_1F0_PH_HI 12
+#define RG_DPD_5900_1F0_PH_SZ 13
+#define RG_DPD_5900_200_PH_MSK 0x1fff0000
+#define RG_DPD_5900_200_PH_I_MSK 0xe000ffff
+#define RG_DPD_5900_200_PH_SFT 16
+#define RG_DPD_5900_200_PH_HI 28
+#define RG_DPD_5900_200_PH_SZ 13
+#define RG_TONE_SEL_MSK 0x00000003
+#define RG_TONE_SEL_I_MSK 0xfffffffc
+#define RG_TONE_SEL_SFT 0
+#define RG_TONE_SEL_HI 1
+#define RG_TONE_SEL_SZ 2
+#define RG_TONE_1_RATE_MSK 0xffff0000
+#define RG_TONE_1_RATE_I_MSK 0x0000ffff
+#define RG_TONE_1_RATE_SFT 16
+#define RG_TONE_1_RATE_HI 31
+#define RG_TONE_1_RATE_SZ 16
+#define RG_RX_PADPD_EN_MSK 0x00000001
+#define RG_RX_PADPD_EN_I_MSK 0xfffffffe
+#define RG_RX_PADPD_EN_SFT 0
+#define RG_RX_PADPD_EN_HI 0
+#define RG_RX_PADPD_EN_SZ 1
+#define RG_RX_PADPD_LEAKY_FACTOR_MSK 0x00000070
+#define RG_RX_PADPD_LEAKY_FACTOR_I_MSK 0xffffff8f
+#define RG_RX_PADPD_LEAKY_FACTOR_SFT 4
+#define RG_RX_PADPD_LEAKY_FACTOR_HI 6
+#define RG_RX_PADPD_LEAKY_FACTOR_SZ 3
+#define RG_RX_PADPD_LATCH_MSK 0x00000100
+#define RG_RX_PADPD_LATCH_I_MSK 0xfffffeff
+#define RG_RX_PADPD_LATCH_SFT 8
+#define RG_RX_PADPD_LATCH_HI 8
+#define RG_RX_PADPD_LATCH_SZ 1
+#define RG_RX_PADPD_DATA_SEL_MSK 0x00001000
+#define RG_RX_PADPD_DATA_SEL_I_MSK 0xffffefff
+#define RG_RX_PADPD_DATA_SEL_SFT 12
+#define RG_RX_PADPD_DATA_SEL_HI 12
+#define RG_RX_PADPD_DATA_SEL_SZ 1
+#define RG_RX_PADPD_TONE_SEL_MSK 0x00002000
+#define RG_RX_PADPD_TONE_SEL_I_MSK 0xffffdfff
+#define RG_RX_PADPD_TONE_SEL_SFT 13
+#define RG_RX_PADPD_TONE_SEL_HI 13
+#define RG_RX_PADPD_TONE_SEL_SZ 1
+#define RG_RX_PADPD_RATE_MSK 0xffff0000
+#define RG_RX_PADPD_RATE_I_MSK 0x0000ffff
+#define RG_RX_PADPD_RATE_SFT 16
+#define RG_RX_PADPD_RATE_HI 31
+#define RG_RX_PADPD_RATE_SZ 16
+#define RO_RX_PHI_MSK 0x00001fff
+#define RO_RX_PHI_I_MSK 0xffffe000
+#define RO_RX_PHI_SFT 0
+#define RO_RX_PHI_HI 12
+#define RO_RX_PHI_SZ 13
+#define RO_RX_AMP_MSK 0x01ff0000
+#define RO_RX_AMP_I_MSK 0xfe00ffff
+#define RO_RX_AMP_SFT 16
+#define RO_RX_AMP_HI 24
+#define RO_RX_AMP_SZ 9
+#define RG_CFR_GAIN_MSK 0x000003ff
+#define RG_CFR_GAIN_I_MSK 0xfffffc00
+#define RG_CFR_GAIN_SFT 0
+#define RG_CFR_GAIN_HI 9
+#define RG_CFR_GAIN_SZ 10
+#define RG_CFR_PEAK_MSK 0x03ff0000
+#define RG_CFR_PEAK_I_MSK 0xfc00ffff
+#define RG_CFR_PEAK_SFT 16
+#define RG_CFR_PEAK_HI 25
+#define RG_CFR_PEAK_SZ 10
+#define RG_CFR_EN_MSK 0x80000000
+#define RG_CFR_EN_I_MSK 0x7fffffff
+#define RG_CFR_EN_SFT 31
+#define RG_CFR_EN_HI 31
+#define RG_CFR_EN_SZ 1
+#define RG_RX_PADPD_DC_RM_LEAKY_FACTOR_MSK 0x00000007
+#define RG_RX_PADPD_DC_RM_LEAKY_FACTOR_I_MSK 0xfffffff8
+#define RG_RX_PADPD_DC_RM_LEAKY_FACTOR_SFT 0
+#define RG_RX_PADPD_DC_RM_LEAKY_FACTOR_HI 2
+#define RG_RX_PADPD_DC_RM_LEAKY_FACTOR_SZ 3
+#define RG_RX_PADPD_DC_RM_BYP_MSK 0x00000010
+#define RG_RX_PADPD_DC_RM_BYP_I_MSK 0xffffffef
+#define RG_RX_PADPD_DC_RM_BYP_SFT 4
+#define RG_RX_PADPD_DC_RM_BYP_HI 4
+#define RG_RX_PADPD_DC_RM_BYP_SZ 1
+#define RG_TXIQ_CLP_THD_I_MSK 0x000003ff
+#define RG_TXIQ_CLP_THD_I_I_MSK 0xfffffc00
+#define RG_TXIQ_CLP_THD_I_SFT 0
+#define RG_TXIQ_CLP_THD_I_HI 9
+#define RG_TXIQ_CLP_THD_I_SZ 10
+#define RG_TXIQ_CLP_THD_Q_MSK 0x03ff0000
+#define RG_TXIQ_CLP_THD_Q_I_MSK 0xfc00ffff
+#define RG_TXIQ_CLP_THD_Q_SFT 16
+#define RG_TXIQ_CLP_THD_Q_HI 25
+#define RG_TXIQ_CLP_THD_Q_SZ 10
+#define RG_TX_SCALE_MSK 0x000000ff
+#define RG_TX_SCALE_I_MSK 0xffffff00
+#define RG_TX_SCALE_SFT 0
+#define RG_TX_SCALE_HI 7
+#define RG_TX_SCALE_SZ 8
+#define RG_TX_IQ_SWP_MSK 0x00010000
+#define RG_TX_IQ_SWP_I_MSK 0xfffeffff
+#define RG_TX_IQ_SWP_SFT 16
+#define RG_TX_IQ_SWP_HI 16
+#define RG_TX_IQ_SWP_SZ 1
+#define RG_TX_BB_SCALE_MANUAL_MSK 0x00100000
+#define RG_TX_BB_SCALE_MANUAL_I_MSK 0xffefffff
+#define RG_TX_BB_SCALE_MANUAL_SFT 20
+#define RG_TX_BB_SCALE_MANUAL_HI 20
+#define RG_TX_BB_SCALE_MANUAL_SZ 1
+#define RG_TX_IQ_SRC_MSK 0x03000000
+#define RG_TX_IQ_SRC_I_MSK 0xfcffffff
+#define RG_TX_IQ_SRC_SFT 24
+#define RG_TX_IQ_SRC_HI 25
+#define RG_TX_IQ_SRC_SZ 2
+#define RG_TX_I_DC_MSK 0x000003ff
+#define RG_TX_I_DC_I_MSK 0xfffffc00
+#define RG_TX_I_DC_SFT 0
+#define RG_TX_I_DC_HI 9
+#define RG_TX_I_DC_SZ 10
+#define RG_TX_Q_DC_MSK 0x03ff0000
+#define RG_TX_Q_DC_I_MSK 0xfc00ffff
+#define RG_TX_Q_DC_SFT 16
+#define RG_TX_Q_DC_HI 25
+#define RG_TX_Q_DC_SZ 10
+#define RG_TX_I_OFFSET_MSK 0x00ff0000
+#define RG_TX_I_OFFSET_I_MSK 0xff00ffff
+#define RG_TX_I_OFFSET_SFT 16
+#define RG_TX_I_OFFSET_HI 23
+#define RG_TX_I_OFFSET_SZ 8
+#define RG_TX_Q_OFFSET_MSK 0xff000000
+#define RG_TX_Q_OFFSET_I_MSK 0x00ffffff
+#define RG_TX_Q_OFFSET_SFT 24
+#define RG_TX_Q_OFFSET_HI 31
+#define RG_TX_Q_OFFSET_SZ 8
+#define RG_DPD_AM_EN_MSK 0x00000001
+#define RG_DPD_AM_EN_I_MSK 0xfffffffe
+#define RG_DPD_AM_EN_SFT 0
+#define RG_DPD_AM_EN_HI 0
+#define RG_DPD_AM_EN_SZ 1
+#define RG_DPD_PM_EN_MSK 0x00000002
+#define RG_DPD_PM_EN_I_MSK 0xfffffffd
+#define RG_DPD_PM_EN_SFT 1
+#define RG_DPD_PM_EN_HI 1
+#define RG_DPD_PM_EN_SZ 1
+#define RG_DPD_PM_AMSEL_MSK 0x00000004
+#define RG_DPD_PM_AMSEL_I_MSK 0xfffffffb
+#define RG_DPD_PM_AMSEL_SFT 2
+#define RG_DPD_PM_AMSEL_HI 2
+#define RG_DPD_PM_AMSEL_SZ 1
+#define RG_DPD_020_GAIN_MSK 0x000003ff
+#define RG_DPD_020_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_020_GAIN_SFT 0
+#define RG_DPD_020_GAIN_HI 9
+#define RG_DPD_020_GAIN_SZ 10
+#define RG_DPD_040_GAIN_MSK 0x03ff0000
+#define RG_DPD_040_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_040_GAIN_SFT 16
+#define RG_DPD_040_GAIN_HI 25
+#define RG_DPD_040_GAIN_SZ 10
+#define RG_DPD_060_GAIN_MSK 0x000003ff
+#define RG_DPD_060_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_060_GAIN_SFT 0
+#define RG_DPD_060_GAIN_HI 9
+#define RG_DPD_060_GAIN_SZ 10
+#define RG_DPD_080_GAIN_MSK 0x03ff0000
+#define RG_DPD_080_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_080_GAIN_SFT 16
+#define RG_DPD_080_GAIN_HI 25
+#define RG_DPD_080_GAIN_SZ 10
+#define RG_DPD_0A0_GAIN_MSK 0x000003ff
+#define RG_DPD_0A0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_0A0_GAIN_SFT 0
+#define RG_DPD_0A0_GAIN_HI 9
+#define RG_DPD_0A0_GAIN_SZ 10
+#define RG_DPD_0C0_GAIN_MSK 0x03ff0000
+#define RG_DPD_0C0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_0C0_GAIN_SFT 16
+#define RG_DPD_0C0_GAIN_HI 25
+#define RG_DPD_0C0_GAIN_SZ 10
+#define RG_DPD_0D0_GAIN_MSK 0x000003ff
+#define RG_DPD_0D0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_0D0_GAIN_SFT 0
+#define RG_DPD_0D0_GAIN_HI 9
+#define RG_DPD_0D0_GAIN_SZ 10
+#define RG_DPD_0E0_GAIN_MSK 0x03ff0000
+#define RG_DPD_0E0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_0E0_GAIN_SFT 16
+#define RG_DPD_0E0_GAIN_HI 25
+#define RG_DPD_0E0_GAIN_SZ 10
+#define RG_DPD_0F0_GAIN_MSK 0x000003ff
+#define RG_DPD_0F0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_0F0_GAIN_SFT 0
+#define RG_DPD_0F0_GAIN_HI 9
+#define RG_DPD_0F0_GAIN_SZ 10
+#define RG_DPD_100_GAIN_MSK 0x03ff0000
+#define RG_DPD_100_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_100_GAIN_SFT 16
+#define RG_DPD_100_GAIN_HI 25
+#define RG_DPD_100_GAIN_SZ 10
+#define RG_DPD_110_GAIN_MSK 0x000003ff
+#define RG_DPD_110_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_110_GAIN_SFT 0
+#define RG_DPD_110_GAIN_HI 9
+#define RG_DPD_110_GAIN_SZ 10
+#define RG_DPD_120_GAIN_MSK 0x03ff0000
+#define RG_DPD_120_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_120_GAIN_SFT 16
+#define RG_DPD_120_GAIN_HI 25
+#define RG_DPD_120_GAIN_SZ 10
+#define RG_DPD_130_GAIN_MSK 0x000003ff
+#define RG_DPD_130_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_130_GAIN_SFT 0
+#define RG_DPD_130_GAIN_HI 9
+#define RG_DPD_130_GAIN_SZ 10
+#define RG_DPD_140_GAIN_MSK 0x03ff0000
+#define RG_DPD_140_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_140_GAIN_SFT 16
+#define RG_DPD_140_GAIN_HI 25
+#define RG_DPD_140_GAIN_SZ 10
+#define RG_DPD_150_GAIN_MSK 0x000003ff
+#define RG_DPD_150_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_150_GAIN_SFT 0
+#define RG_DPD_150_GAIN_HI 9
+#define RG_DPD_150_GAIN_SZ 10
+#define RG_DPD_160_GAIN_MSK 0x03ff0000
+#define RG_DPD_160_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_160_GAIN_SFT 16
+#define RG_DPD_160_GAIN_HI 25
+#define RG_DPD_160_GAIN_SZ 10
+#define RG_DPD_170_GAIN_MSK 0x000003ff
+#define RG_DPD_170_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_170_GAIN_SFT 0
+#define RG_DPD_170_GAIN_HI 9
+#define RG_DPD_170_GAIN_SZ 10
+#define RG_DPD_180_GAIN_MSK 0x03ff0000
+#define RG_DPD_180_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_180_GAIN_SFT 16
+#define RG_DPD_180_GAIN_HI 25
+#define RG_DPD_180_GAIN_SZ 10
+#define RG_DPD_190_GAIN_MSK 0x000003ff
+#define RG_DPD_190_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_190_GAIN_SFT 0
+#define RG_DPD_190_GAIN_HI 9
+#define RG_DPD_190_GAIN_SZ 10
+#define RG_DPD_1A0_GAIN_MSK 0x03ff0000
+#define RG_DPD_1A0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_1A0_GAIN_SFT 16
+#define RG_DPD_1A0_GAIN_HI 25
+#define RG_DPD_1A0_GAIN_SZ 10
+#define RG_DPD_1B0_GAIN_MSK 0x000003ff
+#define RG_DPD_1B0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_1B0_GAIN_SFT 0
+#define RG_DPD_1B0_GAIN_HI 9
+#define RG_DPD_1B0_GAIN_SZ 10
+#define RG_DPD_1C0_GAIN_MSK 0x03ff0000
+#define RG_DPD_1C0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_1C0_GAIN_SFT 16
+#define RG_DPD_1C0_GAIN_HI 25
+#define RG_DPD_1C0_GAIN_SZ 10
+#define RG_DPD_1D0_GAIN_MSK 0x000003ff
+#define RG_DPD_1D0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_1D0_GAIN_SFT 0
+#define RG_DPD_1D0_GAIN_HI 9
+#define RG_DPD_1D0_GAIN_SZ 10
+#define RG_DPD_1E0_GAIN_MSK 0x03ff0000
+#define RG_DPD_1E0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_1E0_GAIN_SFT 16
+#define RG_DPD_1E0_GAIN_HI 25
+#define RG_DPD_1E0_GAIN_SZ 10
+#define RG_DPD_1F0_GAIN_MSK 0x000003ff
+#define RG_DPD_1F0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_1F0_GAIN_SFT 0
+#define RG_DPD_1F0_GAIN_HI 9
+#define RG_DPD_1F0_GAIN_SZ 10
+#define RG_DPD_200_GAIN_MSK 0x03ff0000
+#define RG_DPD_200_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_200_GAIN_SFT 16
+#define RG_DPD_200_GAIN_HI 25
+#define RG_DPD_200_GAIN_SZ 10
+#define RG_DPD_020_PH_MSK 0x00001fff
+#define RG_DPD_020_PH_I_MSK 0xffffe000
+#define RG_DPD_020_PH_SFT 0
+#define RG_DPD_020_PH_HI 12
+#define RG_DPD_020_PH_SZ 13
+#define RG_DPD_040_PH_MSK 0x1fff0000
+#define RG_DPD_040_PH_I_MSK 0xe000ffff
+#define RG_DPD_040_PH_SFT 16
+#define RG_DPD_040_PH_HI 28
+#define RG_DPD_040_PH_SZ 13
+#define RG_DPD_060_PH_MSK 0x00001fff
+#define RG_DPD_060_PH_I_MSK 0xffffe000
+#define RG_DPD_060_PH_SFT 0
+#define RG_DPD_060_PH_HI 12
+#define RG_DPD_060_PH_SZ 13
+#define RG_DPD_080_PH_MSK 0x1fff0000
+#define RG_DPD_080_PH_I_MSK 0xe000ffff
+#define RG_DPD_080_PH_SFT 16
+#define RG_DPD_080_PH_HI 28
+#define RG_DPD_080_PH_SZ 13
+#define RG_DPD_0A0_PH_MSK 0x00001fff
+#define RG_DPD_0A0_PH_I_MSK 0xffffe000
+#define RG_DPD_0A0_PH_SFT 0
+#define RG_DPD_0A0_PH_HI 12
+#define RG_DPD_0A0_PH_SZ 13
+#define RG_DPD_0C0_PH_MSK 0x1fff0000
+#define RG_DPD_0C0_PH_I_MSK 0xe000ffff
+#define RG_DPD_0C0_PH_SFT 16
+#define RG_DPD_0C0_PH_HI 28
+#define RG_DPD_0C0_PH_SZ 13
+#define RG_DPD_0D0_PH_MSK 0x00001fff
+#define RG_DPD_0D0_PH_I_MSK 0xffffe000
+#define RG_DPD_0D0_PH_SFT 0
+#define RG_DPD_0D0_PH_HI 12
+#define RG_DPD_0D0_PH_SZ 13
+#define RG_DPD_0E0_PH_MSK 0x1fff0000
+#define RG_DPD_0E0_PH_I_MSK 0xe000ffff
+#define RG_DPD_0E0_PH_SFT 16
+#define RG_DPD_0E0_PH_HI 28
+#define RG_DPD_0E0_PH_SZ 13
+#define RG_DPD_0F0_PH_MSK 0x00001fff
+#define RG_DPD_0F0_PH_I_MSK 0xffffe000
+#define RG_DPD_0F0_PH_SFT 0
+#define RG_DPD_0F0_PH_HI 12
+#define RG_DPD_0F0_PH_SZ 13
+#define RG_DPD_100_PH_MSK 0x1fff0000
+#define RG_DPD_100_PH_I_MSK 0xe000ffff
+#define RG_DPD_100_PH_SFT 16
+#define RG_DPD_100_PH_HI 28
+#define RG_DPD_100_PH_SZ 13
+#define RG_DPD_110_PH_MSK 0x00001fff
+#define RG_DPD_110_PH_I_MSK 0xffffe000
+#define RG_DPD_110_PH_SFT 0
+#define RG_DPD_110_PH_HI 12
+#define RG_DPD_110_PH_SZ 13
+#define RG_DPD_120_PH_MSK 0x1fff0000
+#define RG_DPD_120_PH_I_MSK 0xe000ffff
+#define RG_DPD_120_PH_SFT 16
+#define RG_DPD_120_PH_HI 28
+#define RG_DPD_120_PH_SZ 13
+#define RG_DPD_130_PH_MSK 0x00001fff
+#define RG_DPD_130_PH_I_MSK 0xffffe000
+#define RG_DPD_130_PH_SFT 0
+#define RG_DPD_130_PH_HI 12
+#define RG_DPD_130_PH_SZ 13
+#define RG_DPD_140_PH_MSK 0x1fff0000
+#define RG_DPD_140_PH_I_MSK 0xe000ffff
+#define RG_DPD_140_PH_SFT 16
+#define RG_DPD_140_PH_HI 28
+#define RG_DPD_140_PH_SZ 13
+#define RG_DPD_150_PH_MSK 0x00001fff
+#define RG_DPD_150_PH_I_MSK 0xffffe000
+#define RG_DPD_150_PH_SFT 0
+#define RG_DPD_150_PH_HI 12
+#define RG_DPD_150_PH_SZ 13
+#define RG_DPD_160_PH_MSK 0x1fff0000
+#define RG_DPD_160_PH_I_MSK 0xe000ffff
+#define RG_DPD_160_PH_SFT 16
+#define RG_DPD_160_PH_HI 28
+#define RG_DPD_160_PH_SZ 13
+#define RG_DPD_170_PH_MSK 0x00001fff
+#define RG_DPD_170_PH_I_MSK 0xffffe000
+#define RG_DPD_170_PH_SFT 0
+#define RG_DPD_170_PH_HI 12
+#define RG_DPD_170_PH_SZ 13
+#define RG_DPD_180_PH_MSK 0x1fff0000
+#define RG_DPD_180_PH_I_MSK 0xe000ffff
+#define RG_DPD_180_PH_SFT 16
+#define RG_DPD_180_PH_HI 28
+#define RG_DPD_180_PH_SZ 13
+#define RG_DPD_190_PH_MSK 0x00001fff
+#define RG_DPD_190_PH_I_MSK 0xffffe000
+#define RG_DPD_190_PH_SFT 0
+#define RG_DPD_190_PH_HI 12
+#define RG_DPD_190_PH_SZ 13
+#define RG_DPD_1A0_PH_MSK 0x1fff0000
+#define RG_DPD_1A0_PH_I_MSK 0xe000ffff
+#define RG_DPD_1A0_PH_SFT 16
+#define RG_DPD_1A0_PH_HI 28
+#define RG_DPD_1A0_PH_SZ 13
+#define RG_DPD_1B0_PH_MSK 0x00001fff
+#define RG_DPD_1B0_PH_I_MSK 0xffffe000
+#define RG_DPD_1B0_PH_SFT 0
+#define RG_DPD_1B0_PH_HI 12
+#define RG_DPD_1B0_PH_SZ 13
+#define RG_DPD_1C0_PH_MSK 0x1fff0000
+#define RG_DPD_1C0_PH_I_MSK 0xe000ffff
+#define RG_DPD_1C0_PH_SFT 16
+#define RG_DPD_1C0_PH_HI 28
+#define RG_DPD_1C0_PH_SZ 13
+#define RG_DPD_1D0_PH_MSK 0x00001fff
+#define RG_DPD_1D0_PH_I_MSK 0xffffe000
+#define RG_DPD_1D0_PH_SFT 0
+#define RG_DPD_1D0_PH_HI 12
+#define RG_DPD_1D0_PH_SZ 13
+#define RG_DPD_1E0_PH_MSK 0x1fff0000
+#define RG_DPD_1E0_PH_I_MSK 0xe000ffff
+#define RG_DPD_1E0_PH_SFT 16
+#define RG_DPD_1E0_PH_HI 28
+#define RG_DPD_1E0_PH_SZ 13
+#define RG_DPD_1F0_PH_MSK 0x00001fff
+#define RG_DPD_1F0_PH_I_MSK 0xffffe000
+#define RG_DPD_1F0_PH_SFT 0
+#define RG_DPD_1F0_PH_HI 12
+#define RG_DPD_1F0_PH_SZ 13
+#define RG_DPD_200_PH_MSK 0x1fff0000
+#define RG_DPD_200_PH_I_MSK 0xe000ffff
+#define RG_DPD_200_PH_SFT 16
+#define RG_DPD_200_PH_HI 28
+#define RG_DPD_200_PH_SZ 13
+#define RG_DPD_BB_SCALE_5900_MSK 0x000000ff
+#define RG_DPD_BB_SCALE_5900_I_MSK 0xffffff00
+#define RG_DPD_BB_SCALE_5900_SFT 0
+#define RG_DPD_BB_SCALE_5900_HI 7
+#define RG_DPD_BB_SCALE_5900_SZ 8
+#define RG_DPD_BB_SCALE_5700_MSK 0x0000ff00
+#define RG_DPD_BB_SCALE_5700_I_MSK 0xffff00ff
+#define RG_DPD_BB_SCALE_5700_SFT 8
+#define RG_DPD_BB_SCALE_5700_HI 15
+#define RG_DPD_BB_SCALE_5700_SZ 8
+#define RG_DPD_BB_SCALE_5500_MSK 0x00ff0000
+#define RG_DPD_BB_SCALE_5500_I_MSK 0xff00ffff
+#define RG_DPD_BB_SCALE_5500_SFT 16
+#define RG_DPD_BB_SCALE_5500_HI 23
+#define RG_DPD_BB_SCALE_5500_SZ 8
+#define RG_DPD_BB_SCALE_5100_MSK 0xff000000
+#define RG_DPD_BB_SCALE_5100_I_MSK 0x00ffffff
+#define RG_DPD_BB_SCALE_5100_SFT 24
+#define RG_DPD_BB_SCALE_5100_HI 31
+#define RG_DPD_BB_SCALE_5100_SZ 8
+#define RG_DPD_BB_SCALE_2500_MSK 0x000000ff
+#define RG_DPD_BB_SCALE_2500_I_MSK 0xffffff00
+#define RG_DPD_BB_SCALE_2500_SFT 0
+#define RG_DPD_BB_SCALE_2500_HI 7
+#define RG_DPD_BB_SCALE_2500_SZ 8
+#define RG_TX_SCALE_11B_MSK 0x000000ff
+#define RG_TX_SCALE_11B_I_MSK 0xffffff00
+#define RG_TX_SCALE_11B_SFT 0
+#define RG_TX_SCALE_11B_HI 7
+#define RG_TX_SCALE_11B_SZ 8
+#define RG_TX_SCALE_11B_P0D5_MSK 0x0000ff00
+#define RG_TX_SCALE_11B_P0D5_I_MSK 0xffff00ff
+#define RG_TX_SCALE_11B_P0D5_SFT 8
+#define RG_TX_SCALE_11B_P0D5_HI 15
+#define RG_TX_SCALE_11B_P0D5_SZ 8
+#define RG_TX_SCALE_11G_MSK 0x00ff0000
+#define RG_TX_SCALE_11G_I_MSK 0xff00ffff
+#define RG_TX_SCALE_11G_SFT 16
+#define RG_TX_SCALE_11G_HI 23
+#define RG_TX_SCALE_11G_SZ 8
+#define RG_TX_SCALE_11G_P0D5_MSK 0xff000000
+#define RG_TX_SCALE_11G_P0D5_I_MSK 0x00ffffff
+#define RG_TX_SCALE_11G_P0D5_SFT 24
+#define RG_TX_SCALE_11G_P0D5_HI 31
+#define RG_TX_SCALE_11G_P0D5_SZ 8
+#define RG_HS5W_M_MD_EN_MSK 0x00000001
+#define RG_HS5W_M_MD_EN_I_MSK 0xfffffffe
+#define RG_HS5W_M_MD_EN_SFT 0
+#define RG_HS5W_M_MD_EN_HI 0
+#define RG_HS5W_M_MD_EN_SZ 1
+#define RG_HS5W_M_MAN_MSK 0x00000001
+#define RG_HS5W_M_MAN_I_MSK 0xfffffffe
+#define RG_HS5W_M_MAN_SFT 0
+#define RG_HS5W_M_MAN_HI 0
+#define RG_HS5W_M_MAN_SZ 1
+#define RG_HS5W_M_CMD6_EN_MSK 0x02000000
+#define RG_HS5W_M_CMD6_EN_I_MSK 0xfdffffff
+#define RG_HS5W_M_CMD6_EN_SFT 25
+#define RG_HS5W_M_CMD6_EN_HI 25
+#define RG_HS5W_M_CMD6_EN_SZ 1
+#define RG_HS5W_M_CMD5_EN_MSK 0x04000000
+#define RG_HS5W_M_CMD5_EN_I_MSK 0xfbffffff
+#define RG_HS5W_M_CMD5_EN_SFT 26
+#define RG_HS5W_M_CMD5_EN_HI 26
+#define RG_HS5W_M_CMD5_EN_SZ 1
+#define RG_HS5W_M_CMD4_EN_MSK 0x08000000
+#define RG_HS5W_M_CMD4_EN_I_MSK 0xf7ffffff
+#define RG_HS5W_M_CMD4_EN_SFT 27
+#define RG_HS5W_M_CMD4_EN_HI 27
+#define RG_HS5W_M_CMD4_EN_SZ 1
+#define RG_HS5W_M_CMD3_EN_MSK 0x10000000
+#define RG_HS5W_M_CMD3_EN_I_MSK 0xefffffff
+#define RG_HS5W_M_CMD3_EN_SFT 28
+#define RG_HS5W_M_CMD3_EN_HI 28
+#define RG_HS5W_M_CMD3_EN_SZ 1
+#define RG_HS5W_M_CMD2_EN_MSK 0x20000000
+#define RG_HS5W_M_CMD2_EN_I_MSK 0xdfffffff
+#define RG_HS5W_M_CMD2_EN_SFT 29
+#define RG_HS5W_M_CMD2_EN_HI 29
+#define RG_HS5W_M_CMD2_EN_SZ 1
+#define RG_HS5W_M_CMD1_EN_MSK 0x40000000
+#define RG_HS5W_M_CMD1_EN_I_MSK 0xbfffffff
+#define RG_HS5W_M_CMD1_EN_SFT 30
+#define RG_HS5W_M_CMD1_EN_HI 30
+#define RG_HS5W_M_CMD1_EN_SZ 1
+#define RG_HS5W_M_CMD0_EN_MSK 0x80000000
+#define RG_HS5W_M_CMD0_EN_I_MSK 0x7fffffff
+#define RG_HS5W_M_CMD0_EN_SFT 31
+#define RG_HS5W_M_CMD0_EN_HI 31
+#define RG_HS5W_M_CMD0_EN_SZ 1
+#define RG_HS5W_M_RF_PHY_MODE_MSK 0x00000007
+#define RG_HS5W_M_RF_PHY_MODE_I_MSK 0xfffffff8
+#define RG_HS5W_M_RF_PHY_MODE_SFT 0
+#define RG_HS5W_M_RF_PHY_MODE_HI 2
+#define RG_HS5W_M_RF_PHY_MODE_SZ 3
+#define RG_HS5W_M_CAL_INDEX_MSK 0x0000001f
+#define RG_HS5W_M_CAL_INDEX_I_MSK 0xffffffe0
+#define RG_HS5W_M_CAL_INDEX_SFT 0
+#define RG_HS5W_M_CAL_INDEX_HI 4
+#define RG_HS5W_M_CAL_INDEX_SZ 5
+#define RG_HS5W_M_PGAGC_MSK 0x0000000f
+#define RG_HS5W_M_PGAGC_I_MSK 0xfffffff0
+#define RG_HS5W_M_PGAGC_SFT 0
+#define RG_HS5W_M_PGAGC_HI 3
+#define RG_HS5W_M_PGAGC_SZ 4
+#define RG_HS5W_M_RFGC_MSK 0x00000030
+#define RG_HS5W_M_RFGC_I_MSK 0xffffffcf
+#define RG_HS5W_M_RFGC_SFT 4
+#define RG_HS5W_M_RFGC_HI 5
+#define RG_HS5W_M_RFGC_SZ 2
+#define RG_HS5W_M_TXPWRLVL_MSK 0x0000003f
+#define RG_HS5W_M_TXPWRLVL_I_MSK 0xffffffc0
+#define RG_HS5W_M_TXPWRLVL_SFT 0
+#define RG_HS5W_M_TXPWRLVL_HI 5
+#define RG_HS5W_M_TXPWRLVL_SZ 6
+#define RG_HS5W_M_SX_RFCTRL_CH_MSK 0x000007ff
+#define RG_HS5W_M_SX_RFCTRL_CH_I_MSK 0xfffff800
+#define RG_HS5W_M_SX_RFCTRL_CH_SFT 0
+#define RG_HS5W_M_SX_RFCTRL_CH_HI 10
+#define RG_HS5W_M_SX_RFCTRL_CH_SZ 11
+#define RG_HS5W_M_SX5GB_RFCTRL_CH_MSK 0x000007ff
+#define RG_HS5W_M_SX5GB_RFCTRL_CH_I_MSK 0xfffff800
+#define RG_HS5W_M_SX5GB_RFCTRL_CH_SFT 0
+#define RG_HS5W_M_SX5GB_RFCTRL_CH_HI 10
+#define RG_HS5W_M_SX5GB_RFCTRL_CH_SZ 11
+#define RG_HS5W_M_SX_RFCTRL_F_MSK 0x00ffffff
+#define RG_HS5W_M_SX_RFCTRL_F_I_MSK 0xff000000
+#define RG_HS5W_M_SX_RFCTRL_F_SFT 0
+#define RG_HS5W_M_SX_RFCTRL_F_HI 23
+#define RG_HS5W_M_SX_RFCTRL_F_SZ 24
+#define RG_HS5W_M_SX_RFCH_MAP_EN_MSK 0x80000000
+#define RG_HS5W_M_SX_RFCH_MAP_EN_I_MSK 0x7fffffff
+#define RG_HS5W_M_SX_RFCH_MAP_EN_SFT 31
+#define RG_HS5W_M_SX_RFCH_MAP_EN_HI 31
+#define RG_HS5W_M_SX_RFCH_MAP_EN_SZ 1
+#define RG_HS5W_M_SX5GB_RFCTRL_F_MSK 0x00ffffff
+#define RG_HS5W_M_SX5GB_RFCTRL_F_I_MSK 0xff000000
+#define RG_HS5W_M_SX5GB_RFCTRL_F_SFT 0
+#define RG_HS5W_M_SX5GB_RFCTRL_F_HI 23
+#define RG_HS5W_M_SX5GB_RFCTRL_F_SZ 24
+#define RG_HS5W_M_SX5GB_RFCH_MAP_EN_MSK 0x80000000
+#define RG_HS5W_M_SX5GB_RFCH_MAP_EN_I_MSK 0x7fffffff
+#define RG_HS5W_M_SX5GB_RFCH_MAP_EN_SFT 31
+#define RG_HS5W_M_SX5GB_RFCH_MAP_EN_HI 31
+#define RG_HS5W_M_SX5GB_RFCH_MAP_EN_SZ 1
+#define RG_HS5W_M_SX_CHANNEL_MSK 0x000000ff
+#define RG_HS5W_M_SX_CHANNEL_I_MSK 0xffffff00
+#define RG_HS5W_M_SX_CHANNEL_SFT 0
+#define RG_HS5W_M_SX_CHANNEL_HI 7
+#define RG_HS5W_M_SX_CHANNEL_SZ 8
+#define RG_HS5W_M_SX5GB_CHANNEL_MSK 0x000000ff
+#define RG_HS5W_M_SX5GB_CHANNEL_I_MSK 0xffffff00
+#define RG_HS5W_M_SX5GB_CHANNEL_SFT 0
+#define RG_HS5W_M_SX5GB_CHANNEL_HI 7
+#define RG_HS5W_M_SX5GB_CHANNEL_SZ 8
+#define RG_HS5W_M_PHY_BW_MSK 0x00000003
+#define RG_HS5W_M_PHY_BW_I_MSK 0xfffffffc
+#define RG_HS5W_M_PHY_BW_SFT 0
+#define RG_HS5W_M_PHY_BW_HI 1
+#define RG_HS5W_M_PHY_BW_SZ 2
+#define RG_RESERVED_DPD_MSK 0xffffffff
+#define RG_RESERVED_DPD_I_MSK 0x00000000
+#define RG_RESERVED_DPD_SFT 0
+#define RG_RESERVED_DPD_HI 31
+#define RG_RESERVED_DPD_SZ 32
+#define RG_XO_LDO_LEVEL_MSK 0x00000007
+#define RG_XO_LDO_LEVEL_I_MSK 0xfffffff8
+#define RG_XO_LDO_LEVEL_SFT 0
+#define RG_XO_LDO_LEVEL_HI 2
+#define RG_XO_LDO_LEVEL_SZ 3
+#define RG_EN_LDO_XO_IQUP_MSK 0x00000010
+#define RG_EN_LDO_XO_IQUP_I_MSK 0xffffffef
+#define RG_EN_LDO_XO_IQUP_SFT 4
+#define RG_EN_LDO_XO_IQUP_HI 4
+#define RG_EN_LDO_XO_IQUP_SZ 1
+#define RG_EN_LDO_XO_BYP_MSK 0x00000020
+#define RG_EN_LDO_XO_BYP_I_MSK 0xffffffdf
+#define RG_EN_LDO_XO_BYP_SFT 5
+#define RG_EN_LDO_XO_BYP_HI 5
+#define RG_EN_LDO_XO_BYP_SZ 1
+#define RG_EN_DLDO_BYP_MSK 0x00000040
+#define RG_EN_DLDO_BYP_I_MSK 0xffffffbf
+#define RG_EN_DLDO_BYP_SFT 6
+#define RG_EN_DLDO_BYP_HI 6
+#define RG_EN_DLDO_BYP_SZ 1
+#define RG_EN_DLDO_HALF_IQ_MSK 0x00000080
+#define RG_EN_DLDO_HALF_IQ_I_MSK 0xffffff7f
+#define RG_EN_DLDO_HALF_IQ_SFT 7
+#define RG_EN_DLDO_HALF_IQ_HI 7
+#define RG_EN_DLDO_HALF_IQ_SZ 1
+#define RG_XO_CBANKI_MSK 0x0001ff00
+#define RG_XO_CBANKI_I_MSK 0xfffe00ff
+#define RG_XO_CBANKI_SFT 8
+#define RG_XO_CBANKI_HI 16
+#define RG_XO_CBANKI_SZ 9
+#define RG_XO_CBANKO_MSK 0x03fe0000
+#define RG_XO_CBANKO_I_MSK 0xfc01ffff
+#define RG_XO_CBANKO_SFT 17
+#define RG_XO_CBANKO_HI 25
+#define RG_XO_CBANKO_SZ 9
+#define RG_EN_FDB_MSK 0x04000000
+#define RG_EN_FDB_I_MSK 0xfbffffff
+#define RG_EN_FDB_SFT 26
+#define RG_EN_FDB_HI 26
+#define RG_EN_FDB_SZ 1
+#define RG_FDB_BYPASS_MSK 0x08000000
+#define RG_FDB_BYPASS_I_MSK 0xf7ffffff
+#define RG_FDB_BYPASS_SFT 27
+#define RG_FDB_BYPASS_HI 27
+#define RG_FDB_BYPASS_SZ 1
+#define RG_FDB_DUTY_LTH_MSK 0x30000000
+#define RG_FDB_DUTY_LTH_I_MSK 0xcfffffff
+#define RG_FDB_DUTY_LTH_SFT 28
+#define RG_FDB_DUTY_LTH_HI 29
+#define RG_FDB_DUTY_LTH_SZ 2
+#define RG_EN_XOTEST_MSK 0x40000000
+#define RG_EN_XOTEST_I_MSK 0xbfffffff
+#define RG_EN_XOTEST_SFT 30
+#define RG_EN_XOTEST_HI 30
+#define RG_EN_XOTEST_SZ 1
+#define RG_HW_WAKE_XOSC_MSK 0x80000000
+#define RG_HW_WAKE_XOSC_I_MSK 0x7fffffff
+#define RG_HW_WAKE_XOSC_SFT 31
+#define RG_HW_WAKE_XOSC_HI 31
+#define RG_HW_WAKE_XOSC_SZ 1
+#define RG_EN_FDB_DCC_MUAL_MSK 0x00000001
+#define RG_EN_FDB_DCC_MUAL_I_MSK 0xfffffffe
+#define RG_EN_FDB_DCC_MUAL_SFT 0
+#define RG_EN_FDB_DCC_MUAL_HI 0
+#define RG_EN_FDB_DCC_MUAL_SZ 1
+#define RG_EN_FDB_DELAYC_MUAL_MSK 0x00000002
+#define RG_EN_FDB_DELAYC_MUAL_I_MSK 0xfffffffd
+#define RG_EN_FDB_DELAYC_MUAL_SFT 1
+#define RG_EN_FDB_DELAYC_MUAL_HI 1
+#define RG_EN_FDB_DELAYC_MUAL_SZ 1
+#define RG_EN_FDB_DELAYF_MUAL_MSK 0x00000004
+#define RG_EN_FDB_DELAYF_MUAL_I_MSK 0xfffffffb
+#define RG_EN_FDB_DELAYF_MUAL_SFT 2
+#define RG_EN_FDB_DELAYF_MUAL_HI 2
+#define RG_EN_FDB_DELAYF_MUAL_SZ 1
+#define RG_EN_FDB_PHASESWAP_MUAL_MSK 0x00000008
+#define RG_EN_FDB_PHASESWAP_MUAL_I_MSK 0xfffffff7
+#define RG_EN_FDB_PHASESWAP_MUAL_SFT 3
+#define RG_EN_FDB_PHASESWAP_MUAL_HI 3
+#define RG_EN_FDB_PHASESWAP_MUAL_SZ 1
+#define RG_FDB_PHASESWAP_MUAL_MSK 0x00000010
+#define RG_FDB_PHASESWAP_MUAL_I_MSK 0xffffffef
+#define RG_FDB_PHASESWAP_MUAL_SFT 4
+#define RG_FDB_PHASESWAP_MUAL_HI 4
+#define RG_FDB_PHASESWAP_MUAL_SZ 1
+#define RG_CLOCK_BF_MUAL_MSK 0x00000020
+#define RG_CLOCK_BF_MUAL_I_MSK 0xffffffdf
+#define RG_CLOCK_BF_MUAL_SFT 5
+#define RG_CLOCK_BF_MUAL_HI 5
+#define RG_CLOCK_BF_MUAL_SZ 1
+#define RG_FDB_CDELAY_MUAL_MSK 0x00000f00
+#define RG_FDB_CDELAY_MUAL_I_MSK 0xfffff0ff
+#define RG_FDB_CDELAY_MUAL_SFT 8
+#define RG_FDB_CDELAY_MUAL_HI 11
+#define RG_FDB_CDELAY_MUAL_SZ 4
+#define RG_FDB_FDELAY_MUAL_MSK 0x0000f000
+#define RG_FDB_FDELAY_MUAL_I_MSK 0xffff0fff
+#define RG_FDB_FDELAY_MUAL_SFT 12
+#define RG_FDB_FDELAY_MUAL_HI 15
+#define RG_FDB_FDELAY_MUAL_SZ 4
+#define RG_XO_TIMMER_MSK 0x003f0000
+#define RG_XO_TIMMER_I_MSK 0xffc0ffff
+#define RG_XO_TIMMER_SFT 16
+#define RG_XO_TIMMER_HI 21
+#define RG_XO_TIMMER_SZ 6
+#define RG_DPL_SETTLING_TIMMER_MSK 0x00c00000
+#define RG_DPL_SETTLING_TIMMER_I_MSK 0xff3fffff
+#define RG_DPL_SETTLING_TIMMER_SFT 22
+#define RG_DPL_SETTLING_TIMMER_HI 23
+#define RG_DPL_SETTLING_TIMMER_SZ 2
+#define RG_FDB_RDELAYF_MSK 0x03000000
+#define RG_FDB_RDELAYF_I_MSK 0xfcffffff
+#define RG_FDB_RDELAYF_SFT 24
+#define RG_FDB_RDELAYF_HI 25
+#define RG_FDB_RDELAYF_SZ 2
+#define RG_FDB_RDELAYS_MSK 0x0c000000
+#define RG_FDB_RDELAYS_I_MSK 0xf3ffffff
+#define RG_FDB_RDELAYS_SFT 26
+#define RG_FDB_RDELAYS_HI 27
+#define RG_FDB_RDELAYS_SZ 2
+#define RG_FDB_RECAL_TIMMER_MSK 0x30000000
+#define RG_FDB_RECAL_TIMMER_I_MSK 0xcfffffff
+#define RG_FDB_RECAL_TIMMER_SFT 28
+#define RG_FDB_RECAL_TIMMER_HI 29
+#define RG_FDB_RECAL_TIMMER_SZ 2
+#define RG_EN_FDB_RECAL_MSK 0x40000000
+#define RG_EN_FDB_RECAL_I_MSK 0xbfffffff
+#define RG_EN_FDB_RECAL_SFT 30
+#define RG_EN_FDB_RECAL_HI 30
+#define RG_EN_FDB_RECAL_SZ 1
+#define RG_LOAD_RFTABLE_RDY_MSK 0x80000000
+#define RG_LOAD_RFTABLE_RDY_I_MSK 0x7fffffff
+#define RG_LOAD_RFTABLE_RDY_SFT 31
+#define RG_LOAD_RFTABLE_RDY_HI 31
+#define RG_LOAD_RFTABLE_RDY_SZ 1
+#define RG_DCDC_MODE_MSK 0x00000001
+#define RG_DCDC_MODE_I_MSK 0xfffffffe
+#define RG_DCDC_MODE_SFT 0
+#define RG_DCDC_MODE_HI 0
+#define RG_DCDC_MODE_SZ 1
+#define RG_DLDO_LEVEL_MSK 0x0000000e
+#define RG_DLDO_LEVEL_I_MSK 0xfffffff1
+#define RG_DLDO_LEVEL_SFT 1
+#define RG_DLDO_LEVEL_HI 3
+#define RG_DLDO_LEVEL_SZ 3
+#define RG_BUCK_LEVEL_MSK 0x000000f0
+#define RG_BUCK_LEVEL_I_MSK 0xffffff0f
+#define RG_BUCK_LEVEL_SFT 4
+#define RG_BUCK_LEVEL_HI 7
+#define RG_BUCK_LEVEL_SZ 4
+#define RG_DLDO_BOOST_IQ_MSK 0x00000100
+#define RG_DLDO_BOOST_IQ_I_MSK 0xfffffeff
+#define RG_DLDO_BOOST_IQ_SFT 8
+#define RG_DLDO_BOOST_IQ_HI 8
+#define RG_DLDO_BOOST_IQ_SZ 1
+#define RG_BUCK_EN_PSM_MSK 0x00000200
+#define RG_BUCK_EN_PSM_I_MSK 0xfffffdff
+#define RG_BUCK_EN_PSM_SFT 9
+#define RG_BUCK_EN_PSM_HI 9
+#define RG_BUCK_EN_PSM_SZ 1
+#define RG_BUCK_PSM_VTH_MSK 0x00000400
+#define RG_BUCK_PSM_VTH_I_MSK 0xfffffbff
+#define RG_BUCK_PSM_VTH_SFT 10
+#define RG_BUCK_PSM_VTH_HI 10
+#define RG_BUCK_PSM_VTH_SZ 1
+#define RG_BUCK_VREF_SEL_MSK 0x00000800
+#define RG_BUCK_VREF_SEL_I_MSK 0xfffff7ff
+#define RG_BUCK_VREF_SEL_SFT 11
+#define RG_BUCK_VREF_SEL_HI 11
+#define RG_BUCK_VREF_SEL_SZ 1
+#define RG_LDO_LEVEL_EFUSE_MSK 0x00007000
+#define RG_LDO_LEVEL_EFUSE_I_MSK 0xffff8fff
+#define RG_LDO_LEVEL_EFUSE_SFT 12
+#define RG_LDO_LEVEL_EFUSE_HI 14
+#define RG_LDO_LEVEL_EFUSE_SZ 3
+#define RG_EN_LDO_EFUSE_MSK 0x00010000
+#define RG_EN_LDO_EFUSE_I_MSK 0xfffeffff
+#define RG_EN_LDO_EFUSE_SFT 16
+#define RG_EN_LDO_EFUSE_HI 16
+#define RG_EN_LDO_EFUSE_SZ 1
+#define RG_DCDC_PULLLOW_CON_MSK 0x00040000
+#define RG_DCDC_PULLLOW_CON_I_MSK 0xfffbffff
+#define RG_DCDC_PULLLOW_CON_SFT 18
+#define RG_DCDC_PULLLOW_CON_HI 18
+#define RG_DCDC_PULLLOW_CON_SZ 1
+#define RG_DCDC_RES2_CON_MSK 0x00080000
+#define RG_DCDC_RES2_CON_I_MSK 0xfff7ffff
+#define RG_DCDC_RES2_CON_SFT 19
+#define RG_DCDC_RES2_CON_HI 19
+#define RG_DCDC_RES2_CON_SZ 1
+#define RG_DCDC_RES_CON_MSK 0x00100000
+#define RG_DCDC_RES_CON_I_MSK 0xffefffff
+#define RG_DCDC_RES_CON_SFT 20
+#define RG_DCDC_RES_CON_HI 20
+#define RG_DCDC_RES_CON_SZ 1
+#define RG_RTC_RS1_MSK 0x00200000
+#define RG_RTC_RS1_I_MSK 0xffdfffff
+#define RG_RTC_RS1_SFT 21
+#define RG_RTC_RS1_HI 21
+#define RG_RTC_RS1_SZ 1
+#define RG_RTC_RS2_MSK 0x00400000
+#define RG_RTC_RS2_I_MSK 0xffbfffff
+#define RG_RTC_RS2_SFT 22
+#define RG_RTC_RS2_HI 22
+#define RG_RTC_RS2_SZ 1
+#define RG_DCDC_CLK_MSK 0x0f000000
+#define RG_DCDC_CLK_I_MSK 0xf0ffffff
+#define RG_DCDC_CLK_SFT 24
+#define RG_DCDC_CLK_HI 27
+#define RG_DCDC_CLK_SZ 4
+#define RG_BUCK_RCZERO_MSK 0x10000000
+#define RG_BUCK_RCZERO_I_MSK 0xefffffff
+#define RG_BUCK_RCZERO_SFT 28
+#define RG_BUCK_RCZERO_HI 28
+#define RG_BUCK_RCZERO_SZ 1
+#define RG_BUCK_SLOP_MSK 0x60000000
+#define RG_BUCK_SLOP_I_MSK 0x9fffffff
+#define RG_BUCK_SLOP_SFT 29
+#define RG_BUCK_SLOP_HI 30
+#define RG_BUCK_SLOP_SZ 2
+#define RG_RTC_OFFSET_MSK 0x000000ff
+#define RG_RTC_OFFSET_I_MSK 0xffffff00
+#define RG_RTC_OFFSET_SFT 0
+#define RG_RTC_OFFSET_HI 7
+#define RG_RTC_OFFSET_SZ 8
+#define RG_RTC_CAL_TARGET_COUNT_MSK 0x000fff00
+#define RG_RTC_CAL_TARGET_COUNT_I_MSK 0xfff000ff
+#define RG_RTC_CAL_TARGET_COUNT_SFT 8
+#define RG_RTC_CAL_TARGET_COUNT_HI 19
+#define RG_RTC_CAL_TARGET_COUNT_SZ 12
+#define RG_RTC_OSC_RES_SW_MANUAL_MSK 0x3ff00000
+#define RG_RTC_OSC_RES_SW_MANUAL_I_MSK 0xc00fffff
+#define RG_RTC_OSC_RES_SW_MANUAL_SFT 20
+#define RG_RTC_OSC_RES_SW_MANUAL_HI 29
+#define RG_RTC_OSC_RES_SW_MANUAL_SZ 10
+#define RG_RTC_CAL_MODE_MSK 0x40000000
+#define RG_RTC_CAL_MODE_I_MSK 0xbfffffff
+#define RG_RTC_CAL_MODE_SFT 30
+#define RG_RTC_CAL_MODE_HI 30
+#define RG_RTC_CAL_MODE_SZ 1
+#define RG_SEL_DPLL_CLK_MSK 0x80000000
+#define RG_SEL_DPLL_CLK_I_MSK 0x7fffffff
+#define RG_SEL_DPLL_CLK_SFT 31
+#define RG_SEL_DPLL_CLK_HI 31
+#define RG_SEL_DPLL_CLK_SZ 1
+#define RG_RTC_OSC_RES_SW_MANUAL_EN_MSK 0x00000001
+#define RG_RTC_OSC_RES_SW_MANUAL_EN_I_MSK 0xfffffffe
+#define RG_RTC_OSC_RES_SW_MANUAL_EN_SFT 0
+#define RG_RTC_OSC_RES_SW_MANUAL_EN_HI 0
+#define RG_RTC_OSC_RES_SW_MANUAL_EN_SZ 1
+#define RG_EN_RTC_CAL_MSK 0x00000002
+#define RG_EN_RTC_CAL_I_MSK 0xfffffffd
+#define RG_EN_RTC_CAL_SFT 1
+#define RG_EN_RTC_CAL_HI 1
+#define RG_EN_RTC_CAL_SZ 1
+#define RO_FDB_CDELAY_MSK 0x0000000f
+#define RO_FDB_CDELAY_I_MSK 0xfffffff0
+#define RO_FDB_CDELAY_SFT 0
+#define RO_FDB_CDELAY_HI 3
+#define RO_FDB_CDELAY_SZ 4
+#define RO_FDB_FDELAY_MSK 0x000000f0
+#define RO_FDB_FDELAY_I_MSK 0xffffff0f
+#define RO_FDB_FDELAY_SFT 4
+#define RO_FDB_FDELAY_HI 7
+#define RO_FDB_FDELAY_SZ 4
+#define RO_FDB_PHASESWAP_MSK 0x00000100
+#define RO_FDB_PHASESWAP_I_MSK 0xfffffeff
+#define RO_FDB_PHASESWAP_SFT 8
+#define RO_FDB_PHASESWAP_HI 8
+#define RO_FDB_PHASESWAP_SZ 1
+#define RO_XO_RDY_MSK 0x00000200
+#define RO_XO_RDY_I_MSK 0xfffffdff
+#define RO_XO_RDY_SFT 9
+#define RO_XO_RDY_HI 9
+#define RO_XO_RDY_SZ 1
+#define RO_RTC_OSC_CAL_RES_RDY_MSK 0x00000400
+#define RO_RTC_OSC_CAL_RES_RDY_I_MSK 0xfffffbff
+#define RO_RTC_OSC_CAL_RES_RDY_SFT 10
+#define RO_RTC_OSC_CAL_RES_RDY_HI 10
+#define RO_RTC_OSC_CAL_RES_RDY_SZ 1
+#define RO_RTC_OSC_RES_SW_MSK 0x001ff800
+#define RO_RTC_OSC_RES_SW_I_MSK 0xffe007ff
+#define RO_RTC_OSC_RES_SW_SFT 11
+#define RO_RTC_OSC_RES_SW_HI 20
+#define RO_RTC_OSC_RES_SW_SZ 10
+#define RG_PMU_ENTER_SLEEP_MODE_MSK 0x00000001
+#define RG_PMU_ENTER_SLEEP_MODE_I_MSK 0xfffffffe
+#define RG_PMU_ENTER_SLEEP_MODE_SFT 0
+#define RG_PMU_ENTER_SLEEP_MODE_HI 0
+#define RG_PMU_ENTER_SLEEP_MODE_SZ 1
+#define RG_SLEEP_METHOD_MSK 0x00000002
+#define RG_SLEEP_METHOD_I_MSK 0xfffffffd
+#define RG_SLEEP_METHOD_SFT 1
+#define RG_SLEEP_METHOD_HI 1
+#define RG_SLEEP_METHOD_SZ 1
+#define RG_INT_PMU_MASK_MSK 0x00000004
+#define RG_INT_PMU_MASK_I_MSK 0xfffffffb
+#define RG_INT_PMU_MASK_SFT 2
+#define RG_INT_PMU_MASK_HI 2
+#define RG_INT_PMU_MASK_SZ 1
+#define RG_SLEEP_WAKE_CNT_MSK 0xffffffff
+#define RG_SLEEP_WAKE_CNT_I_MSK 0x00000000
+#define RG_SLEEP_WAKE_CNT_SFT 0
+#define RG_SLEEP_WAKE_CNT_HI 31
+#define RG_SLEEP_WAKE_CNT_SZ 32
+#define RG_SEC_CNT_VALUE_MSK 0x00007fff
+#define RG_SEC_CNT_VALUE_I_MSK 0xffff8000
+#define RG_SEC_CNT_VALUE_SFT 0
+#define RG_SEC_CNT_VALUE_HI 14
+#define RG_SEC_CNT_VALUE_SZ 15
+#define RG_RTC_EN_MSK 0x00008000
+#define RG_RTC_EN_I_MSK 0xffff7fff
+#define RG_RTC_EN_SFT 15
+#define RG_RTC_EN_HI 15
+#define RG_RTC_EN_SZ 1
+#define RO_RTC_TICK_CNT_MSK 0x7fff0000
+#define RO_RTC_TICK_CNT_I_MSK 0x8000ffff
+#define RO_RTC_TICK_CNT_SFT 16
+#define RO_RTC_TICK_CNT_HI 30
+#define RO_RTC_TICK_CNT_SZ 15
+#define RG_RTC_INT_SEC_MASK_MSK 0x00000001
+#define RG_RTC_INT_SEC_MASK_I_MSK 0xfffffffe
+#define RG_RTC_INT_SEC_MASK_SFT 0
+#define RG_RTC_INT_SEC_MASK_HI 0
+#define RG_RTC_INT_SEC_MASK_SZ 1
+#define RG_RTC_INT_ALARM_MASK_MSK 0x00000002
+#define RG_RTC_INT_ALARM_MASK_I_MSK 0xfffffffd
+#define RG_RTC_INT_ALARM_MASK_SFT 1
+#define RG_RTC_INT_ALARM_MASK_HI 1
+#define RG_RTC_INT_ALARM_MASK_SZ 1
+#define RO_PMU_WAKE_TRIG_EVENT_MSK 0x00007000
+#define RO_PMU_WAKE_TRIG_EVENT_I_MSK 0xffff8fff
+#define RO_PMU_WAKE_TRIG_EVENT_SFT 12
+#define RO_PMU_WAKE_TRIG_EVENT_HI 14
+#define RO_PMU_WAKE_TRIG_EVENT_SZ 3
+#define RO_RTC_INT_SEC_MSK 0x00010000
+#define RO_RTC_INT_SEC_I_MSK 0xfffeffff
+#define RO_RTC_INT_SEC_SFT 16
+#define RO_RTC_INT_SEC_HI 16
+#define RO_RTC_INT_SEC_SZ 1
+#define RO_RTC_INT_ALARM_MSK 0x00020000
+#define RO_RTC_INT_ALARM_I_MSK 0xfffdffff
+#define RO_RTC_INT_ALARM_SFT 17
+#define RO_RTC_INT_ALARM_HI 17
+#define RO_RTC_INT_ALARM_SZ 1
+#define RG_RTC_SEC_START_CNT_MSK 0xffffffff
+#define RG_RTC_SEC_START_CNT_I_MSK 0x00000000
+#define RG_RTC_SEC_START_CNT_SFT 0
+#define RG_RTC_SEC_START_CNT_HI 31
+#define RG_RTC_SEC_START_CNT_SZ 32
+#define RG_RTC_SEC_ALARM_VALUE_MSK 0xffffffff
+#define RG_RTC_SEC_ALARM_VALUE_I_MSK 0x00000000
+#define RG_RTC_SEC_ALARM_VALUE_SFT 0
+#define RG_RTC_SEC_ALARM_VALUE_HI 31
+#define RG_RTC_SEC_ALARM_VALUE_SZ 32
+#define RG_FPGA_CLK_REF_40M_EN_MSK 0x00000001
+#define RG_FPGA_CLK_REF_40M_EN_I_MSK 0xfffffffe
+#define RG_FPGA_CLK_REF_40M_EN_SFT 0
+#define RG_FPGA_CLK_REF_40M_EN_HI 0
+#define RG_FPGA_CLK_REF_40M_EN_SZ 1
+#define RG_CLK_RTC_SW_MSK 0x00000002
+#define RG_CLK_RTC_SW_I_MSK 0xfffffffd
+#define RG_CLK_RTC_SW_SFT 1
+#define RG_CLK_RTC_SW_HI 1
+#define RG_CLK_RTC_SW_SZ 1
+#define RG_PHY_RST_N_MSK 0x00000010
+#define RG_PHY_RST_N_I_MSK 0xffffffef
+#define RG_PHY_RST_N_SFT 4
+#define RG_PHY_RST_N_HI 4
+#define RG_PHY_RST_N_SZ 1
+#define RO_PMU_STATE_MSK 0x00000007
+#define RO_PMU_STATE_I_MSK 0xfffffff8
+#define RO_PMU_STATE_SFT 0
+#define RO_PMU_STATE_HI 2
+#define RO_PMU_STATE_SZ 3
+#define RO_AD_VBAT_OK_MSK 0x00000010
+#define RO_AD_VBAT_OK_I_MSK 0xffffffef
+#define RO_AD_VBAT_OK_SFT 4
+#define RO_AD_VBAT_OK_HI 4
+#define RO_AD_VBAT_OK_SZ 1
+#define RG_DP_LDO_LEVEL_MSK 0x00000007
+#define RG_DP_LDO_LEVEL_I_MSK 0xfffffff8
+#define RG_DP_LDO_LEVEL_SFT 0
+#define RG_DP_LDO_LEVEL_HI 2
+#define RG_DP_LDO_LEVEL_SZ 3
+#define RG_EN_LDO_DP_BYP_MSK 0x00000008
+#define RG_EN_LDO_DP_BYP_I_MSK 0xfffffff7
+#define RG_EN_LDO_DP_BYP_SFT 3
+#define RG_EN_LDO_DP_BYP_HI 3
+#define RG_EN_LDO_DP_BYP_SZ 1
+#define RG_DP_AUTOMAP_EN_MSK 0x00000020
+#define RG_DP_AUTOMAP_EN_I_MSK 0xffffffdf
+#define RG_DP_AUTOMAP_EN_SFT 5
+#define RG_DP_AUTOMAP_EN_HI 5
+#define RG_DP_AUTOMAP_EN_SZ 1
+#define RG_EN_ADC_320M_MSK 0x00000080
+#define RG_EN_ADC_320M_I_MSK 0xffffff7f
+#define RG_EN_ADC_320M_SFT 7
+#define RG_EN_ADC_320M_HI 7
+#define RG_EN_ADC_320M_SZ 1
+#define RG_EN_IOTADC_160M_MSK 0x00000100
+#define RG_EN_IOTADC_160M_I_MSK 0xfffffeff
+#define RG_EN_IOTADC_160M_SFT 8
+#define RG_EN_IOTADC_160M_HI 8
+#define RG_EN_IOTADC_160M_SZ 1
+#define RG_EN_MAC_80M_MSK 0x00000200
+#define RG_EN_MAC_80M_I_MSK 0xfffffdff
+#define RG_EN_MAC_80M_SFT 9
+#define RG_EN_MAC_80M_HI 9
+#define RG_EN_MAC_80M_SZ 1
+#define RG_EN_MAC_96M_MSK 0x00000400
+#define RG_EN_MAC_96M_I_MSK 0xfffffbff
+#define RG_EN_MAC_96M_SFT 10
+#define RG_EN_MAC_96M_HI 10
+#define RG_EN_MAC_96M_SZ 1
+#define RG_EN_MAC_120M_MSK 0x00000800
+#define RG_EN_MAC_120M_I_MSK 0xfffff7ff
+#define RG_EN_MAC_120M_SFT 11
+#define RG_EN_MAC_120M_HI 11
+#define RG_EN_MAC_120M_SZ 1
+#define RG_EN_PHY_80M_MSK 0x00001000
+#define RG_EN_PHY_80M_I_MSK 0xffffefff
+#define RG_EN_PHY_80M_SFT 12
+#define RG_EN_PHY_80M_HI 12
+#define RG_EN_PHY_80M_SZ 1
+#define RG_EN_PHY_160M_MSK 0x00002000
+#define RG_EN_PHY_160M_I_MSK 0xffffdfff
+#define RG_EN_PHY_160M_SFT 13
+#define RG_EN_PHY_160M_HI 13
+#define RG_EN_PHY_160M_SZ 1
+#define RG_EN_PHY_320M_MSK 0x00004000
+#define RG_EN_PHY_320M_I_MSK 0xffffbfff
+#define RG_EN_PHY_320M_SFT 14
+#define RG_EN_PHY_320M_HI 14
+#define RG_EN_PHY_320M_SZ 1
+#define RG_EN_MAC_160M_MSK 0x00008000
+#define RG_EN_MAC_160M_I_MSK 0xffff7fff
+#define RG_EN_MAC_160M_SFT 15
+#define RG_EN_MAC_160M_HI 15
+#define RG_EN_MAC_160M_SZ 1
+#define RG_DP_XTAL_FREQ_MSK 0x000f0000
+#define RG_DP_XTAL_FREQ_I_MSK 0xfff0ffff
+#define RG_DP_XTAL_FREQ_SFT 16
+#define RG_DP_XTAL_FREQ_HI 19
+#define RG_DP_XTAL_FREQ_SZ 4
+#define RG_DP_BBPLL_PD_MSK 0x00000001
+#define RG_DP_BBPLL_PD_I_MSK 0xfffffffe
+#define RG_DP_BBPLL_PD_SFT 0
+#define RG_DP_BBPLL_PD_HI 0
+#define RG_DP_BBPLL_PD_SZ 1
+#define RG_DP_BBPLL_BP_MSK 0x00000002
+#define RG_DP_BBPLL_BP_I_MSK 0xfffffffd
+#define RG_DP_BBPLL_BP_SFT 1
+#define RG_DP_BBPLL_BP_HI 1
+#define RG_DP_BBPLL_BP_SZ 1
+#define RG_EN_DP_MANUAL_MSK 0x00000004
+#define RG_EN_DP_MANUAL_I_MSK 0xfffffffb
+#define RG_EN_DP_MANUAL_SFT 2
+#define RG_EN_DP_MANUAL_HI 2
+#define RG_EN_DP_MANUAL_SZ 1
+#define RG_DP_FREF_DOUB_MSK 0x00000008
+#define RG_DP_FREF_DOUB_I_MSK 0xfffffff7
+#define RG_DP_FREF_DOUB_SFT 3
+#define RG_DP_FREF_DOUB_HI 3
+#define RG_DP_FREF_DOUB_SZ 1
+#define RG_DP_DAC320_DIVBY2_MSK 0x00000010
+#define RG_DP_DAC320_DIVBY2_I_MSK 0xffffffef
+#define RG_DP_DAC320_DIVBY2_SFT 4
+#define RG_DP_DAC320_DIVBY2_HI 4
+#define RG_DP_DAC320_DIVBY2_SZ 1
+#define RG_DP_ADC320_DIVBY2_BT_MSK 0x00000020
+#define RG_DP_ADC320_DIVBY2_BT_I_MSK 0xffffffdf
+#define RG_DP_ADC320_DIVBY2_BT_SFT 5
+#define RG_DP_ADC320_DIVBY2_BT_HI 5
+#define RG_DP_ADC320_DIVBY2_BT_SZ 1
+#define RG_DP_ADC320_DIVBY2_WF_MSK 0x00000040
+#define RG_DP_ADC320_DIVBY2_WF_I_MSK 0xffffffbf
+#define RG_DP_ADC320_DIVBY2_WF_SFT 6
+#define RG_DP_ADC320_DIVBY2_WF_HI 6
+#define RG_DP_ADC320_DIVBY2_WF_SZ 1
+#define RG_EN_DPL_MOD_MSK 0x00000100
+#define RG_EN_DPL_MOD_I_MSK 0xfffffeff
+#define RG_EN_DPL_MOD_SFT 8
+#define RG_EN_DPL_MOD_HI 8
+#define RG_EN_DPL_MOD_SZ 1
+#define RG_DPL_MOD_ORDER_MSK 0x00000600
+#define RG_DPL_MOD_ORDER_I_MSK 0xfffff9ff
+#define RG_DPL_MOD_ORDER_SFT 9
+#define RG_DPL_MOD_ORDER_HI 10
+#define RG_DPL_MOD_ORDER_SZ 2
+#define RG_DP_REFDIV_MSK 0x0003f800
+#define RG_DP_REFDIV_I_MSK 0xfffc07ff
+#define RG_DP_REFDIV_SFT 11
+#define RG_DP_REFDIV_HI 17
+#define RG_DP_REFDIV_SZ 7
+#define RG_DP_FODIV_MSK 0x01fc0000
+#define RG_DP_FODIV_I_MSK 0xfe03ffff
+#define RG_DP_FODIV_SFT 18
+#define RG_DP_FODIV_HI 24
+#define RG_DP_FODIV_SZ 7
+#define RG_EN_LDO_DP_IQUP_MSK 0x04000000
+#define RG_EN_LDO_DP_IQUP_I_MSK 0xfbffffff
+#define RG_EN_LDO_DP_IQUP_SFT 26
+#define RG_EN_LDO_DP_IQUP_HI 26
+#define RG_EN_LDO_DP_IQUP_SZ 1
+#define RG_DP_OD_TEST_MSK 0x08000000
+#define RG_DP_OD_TEST_I_MSK 0xf7ffffff
+#define RG_DP_OD_TEST_SFT 27
+#define RG_DP_OD_TEST_HI 27
+#define RG_DP_OD_TEST_SZ 1
+#define RG_DP_BBPLL_TESTSEL_MSK 0x70000000
+#define RG_DP_BBPLL_TESTSEL_I_MSK 0x8fffffff
+#define RG_DP_BBPLL_TESTSEL_SFT 28
+#define RG_DP_BBPLL_TESTSEL_HI 30
+#define RG_DP_BBPLL_TESTSEL_SZ 3
+#define RG_DP_BBPLL_ICP_MSK 0x00000003
+#define RG_DP_BBPLL_ICP_I_MSK 0xfffffffc
+#define RG_DP_BBPLL_ICP_SFT 0
+#define RG_DP_BBPLL_ICP_HI 1
+#define RG_DP_BBPLL_ICP_SZ 2
+#define RG_DP_BBPLL_IDUAL_MSK 0x0000000c
+#define RG_DP_BBPLL_IDUAL_I_MSK 0xfffffff3
+#define RG_DP_BBPLL_IDUAL_SFT 2
+#define RG_DP_BBPLL_IDUAL_HI 3
+#define RG_DP_BBPLL_IDUAL_SZ 2
+#define RG_DP_CP_IOSTPOL_MSK 0x00000010
+#define RG_DP_CP_IOSTPOL_I_MSK 0xffffffef
+#define RG_DP_CP_IOSTPOL_SFT 4
+#define RG_DP_CP_IOSTPOL_HI 4
+#define RG_DP_CP_IOSTPOL_SZ 1
+#define RG_DP_CP_IOST_MSK 0x00000060
+#define RG_DP_CP_IOST_I_MSK 0xffffff9f
+#define RG_DP_CP_IOST_SFT 5
+#define RG_DP_CP_IOST_HI 6
+#define RG_DP_CP_IOST_SZ 2
+#define RG_DP_PFD_PFDSEL_MSK 0x00000080
+#define RG_DP_PFD_PFDSEL_I_MSK 0xffffff7f
+#define RG_DP_PFD_PFDSEL_SFT 7
+#define RG_DP_PFD_PFDSEL_HI 7
+#define RG_DP_PFD_PFDSEL_SZ 1
+#define RG_DP_BBPLL_PFD_DLY_MSK 0x00000300
+#define RG_DP_BBPLL_PFD_DLY_I_MSK 0xfffffcff
+#define RG_DP_BBPLL_PFD_DLY_SFT 8
+#define RG_DP_BBPLL_PFD_DLY_HI 9
+#define RG_DP_BBPLL_PFD_DLY_SZ 2
+#define RG_DP_RP_MSK 0x00003800
+#define RG_DP_RP_I_MSK 0xffffc7ff
+#define RG_DP_RP_SFT 11
+#define RG_DP_RP_HI 13
+#define RG_DP_RP_SZ 3
+#define RG_DP_RHP_MSK 0x0000c000
+#define RG_DP_RHP_I_MSK 0xffff3fff
+#define RG_DP_RHP_SFT 14
+#define RG_DP_RHP_HI 15
+#define RG_DP_RHP_SZ 2
+#define RG_EN_DP_VT_MON_MSK 0x00020000
+#define RG_EN_DP_VT_MON_I_MSK 0xfffdffff
+#define RG_EN_DP_VT_MON_SFT 17
+#define RG_EN_DP_VT_MON_HI 17
+#define RG_EN_DP_VT_MON_SZ 1
+#define RG_DP_VT_TH_HI_MSK 0x000c0000
+#define RG_DP_VT_TH_HI_I_MSK 0xfff3ffff
+#define RG_DP_VT_TH_HI_SFT 18
+#define RG_DP_VT_TH_HI_HI 19
+#define RG_DP_VT_TH_HI_SZ 2
+#define RG_DP_VT_TH_LO_MSK 0x00300000
+#define RG_DP_VT_TH_LO_I_MSK 0xffcfffff
+#define RG_DP_VT_TH_LO_SFT 20
+#define RG_DP_VT_TH_LO_HI 21
+#define RG_DP_VT_TH_LO_SZ 2
+#define RG_DP_BBPLL_BS_MSK 0x1f800000
+#define RG_DP_BBPLL_BS_I_MSK 0xe07fffff
+#define RG_DP_BBPLL_BS_SFT 23
+#define RG_DP_BBPLL_BS_HI 28
+#define RG_DP_BBPLL_BS_SZ 6
+#define RG_DP_BBPLL_SDM_EDGE_MSK 0x80000000
+#define RG_DP_BBPLL_SDM_EDGE_I_MSK 0x7fffffff
+#define RG_DP_BBPLL_SDM_EDGE_SFT 31
+#define RG_DP_BBPLL_SDM_EDGE_HI 31
+#define RG_DP_BBPLL_SDM_EDGE_SZ 1
+#define RG_DPL_RFCTRL_F_MSK 0x00ffffff
+#define RG_DPL_RFCTRL_F_I_MSK 0xff000000
+#define RG_DPL_RFCTRL_F_SFT 0
+#define RG_DPL_RFCTRL_F_HI 23
+#define RG_DPL_RFCTRL_F_SZ 24
+#define RG_DPL_RFCTRL_CH_MSK 0xff000000
+#define RG_DPL_RFCTRL_CH_I_MSK 0x00ffffff
+#define RG_DPL_RFCTRL_CH_SFT 24
+#define RG_DPL_RFCTRL_CH_HI 31
+#define RG_DPL_RFCTRL_CH_SZ 8
+#define RG_DCDC_MODE_SLP_MSK 0x00000001
+#define RG_DCDC_MODE_SLP_I_MSK 0xfffffffe
+#define RG_DCDC_MODE_SLP_SFT 0
+#define RG_DCDC_MODE_SLP_HI 0
+#define RG_DCDC_MODE_SLP_SZ 1
+#define RG_DLDO_LEVEL_SLP_MSK 0x0000000e
+#define RG_DLDO_LEVEL_SLP_I_MSK 0xfffffff1
+#define RG_DLDO_LEVEL_SLP_SFT 1
+#define RG_DLDO_LEVEL_SLP_HI 3
+#define RG_DLDO_LEVEL_SLP_SZ 3
+#define RG_BUCK_LEVEL_SLP_MSK 0x000000f0
+#define RG_BUCK_LEVEL_SLP_I_MSK 0xffffff0f
+#define RG_BUCK_LEVEL_SLP_SFT 4
+#define RG_BUCK_LEVEL_SLP_HI 7
+#define RG_BUCK_LEVEL_SLP_SZ 4
+#define RG_XO_CBANKI_SLP_MSK 0x0001ff00
+#define RG_XO_CBANKI_SLP_I_MSK 0xfffe00ff
+#define RG_XO_CBANKI_SLP_SFT 8
+#define RG_XO_CBANKI_SLP_HI 16
+#define RG_XO_CBANKI_SLP_SZ 9
+#define RG_XO_CBANKO_SLP_MSK 0x03fe0000
+#define RG_XO_CBANKO_SLP_I_MSK 0xfc01ffff
+#define RG_XO_CBANKO_SLP_SFT 17
+#define RG_XO_CBANKO_SLP_HI 25
+#define RG_XO_CBANKO_SLP_SZ 9
+#define RG_EN_DLDO_HALF_IQ_SLP_MSK 0x04000000
+#define RG_EN_DLDO_HALF_IQ_SLP_I_MSK 0xfbffffff
+#define RG_EN_DLDO_HALF_IQ_SLP_SFT 26
+#define RG_EN_DLDO_HALF_IQ_SLP_HI 26
+#define RG_EN_DLDO_HALF_IQ_SLP_SZ 1
+#define RG_EN_DLDO_BYP_AUTO_MSK 0x08000000
+#define RG_EN_DLDO_BYP_AUTO_I_MSK 0xf7ffffff
+#define RG_EN_DLDO_BYP_AUTO_SFT 27
+#define RG_EN_DLDO_BYP_AUTO_HI 27
+#define RG_EN_DLDO_BYP_AUTO_SZ 1
+#define RG_HW_WAKE_XOSC_SLP_MSK 0x80000000
+#define RG_HW_WAKE_XOSC_SLP_I_MSK 0x7fffffff
+#define RG_HW_WAKE_XOSC_SLP_SFT 31
+#define RG_HW_WAKE_XOSC_SLP_HI 31
+#define RG_HW_WAKE_XOSC_SLP_SZ 1
+#define RG_RAM_00_MSK 0xffffffff
+#define RG_RAM_00_I_MSK 0x00000000
+#define RG_RAM_00_SFT 0
+#define RG_RAM_00_HI 31
+#define RG_RAM_00_SZ 32
+#define RG_RAM_01_MSK 0xffffffff
+#define RG_RAM_01_I_MSK 0x00000000
+#define RG_RAM_01_SFT 0
+#define RG_RAM_01_HI 31
+#define RG_RAM_01_SZ 32
+#define RG_RAM_02_MSK 0xffffffff
+#define RG_RAM_02_I_MSK 0x00000000
+#define RG_RAM_02_SFT 0
+#define RG_RAM_02_HI 31
+#define RG_RAM_02_SZ 32
+#define RG_RAM_03_MSK 0xffffffff
+#define RG_RAM_03_I_MSK 0x00000000
+#define RG_RAM_03_SFT 0
+#define RG_RAM_03_HI 31
+#define RG_RAM_03_SZ 32
+#define RG_RAM_04_MSK 0xffffffff
+#define RG_RAM_04_I_MSK 0x00000000
+#define RG_RAM_04_SFT 0
+#define RG_RAM_04_HI 31
+#define RG_RAM_04_SZ 32
+#define RG_RAM_05_MSK 0xffffffff
+#define RG_RAM_05_I_MSK 0x00000000
+#define RG_RAM_05_SFT 0
+#define RG_RAM_05_HI 31
+#define RG_RAM_05_SZ 32
+#define RG_RAM_06_MSK 0xffffffff
+#define RG_RAM_06_I_MSK 0x00000000
+#define RG_RAM_06_SFT 0
+#define RG_RAM_06_HI 31
+#define RG_RAM_06_SZ 32
+#define RG_RAM_07_MSK 0xffffffff
+#define RG_RAM_07_I_MSK 0x00000000
+#define RG_RAM_07_SFT 0
+#define RG_RAM_07_HI 31
+#define RG_RAM_07_SZ 32
+#define RG_RAM_08_MSK 0xffffffff
+#define RG_RAM_08_I_MSK 0x00000000
+#define RG_RAM_08_SFT 0
+#define RG_RAM_08_HI 31
+#define RG_RAM_08_SZ 32
+#define RG_RAM_09_MSK 0xffffffff
+#define RG_RAM_09_I_MSK 0x00000000
+#define RG_RAM_09_SFT 0
+#define RG_RAM_09_HI 31
+#define RG_RAM_09_SZ 32
+#define RG_RAM_10_MSK 0xffffffff
+#define RG_RAM_10_I_MSK 0x00000000
+#define RG_RAM_10_SFT 0
+#define RG_RAM_10_HI 31
+#define RG_RAM_10_SZ 32
+#define RG_RAM_11_MSK 0xffffffff
+#define RG_RAM_11_I_MSK 0x00000000
+#define RG_RAM_11_SFT 0
+#define RG_RAM_11_HI 31
+#define RG_RAM_11_SZ 32
+#define RG_RAM_12_MSK 0xffffffff
+#define RG_RAM_12_I_MSK 0x00000000
+#define RG_RAM_12_SFT 0
+#define RG_RAM_12_HI 31
+#define RG_RAM_12_SZ 32
+#define RG_RAM_13_MSK 0xffffffff
+#define RG_RAM_13_I_MSK 0x00000000
+#define RG_RAM_13_SFT 0
+#define RG_RAM_13_HI 31
+#define RG_RAM_13_SZ 32
+#define RG_RAM_14_MSK 0xffffffff
+#define RG_RAM_14_I_MSK 0x00000000
+#define RG_RAM_14_SFT 0
+#define RG_RAM_14_HI 31
+#define RG_RAM_14_SZ 32
+#define RG_RAM_15_MSK 0xffffffff
+#define RG_RAM_15_I_MSK 0x00000000
+#define RG_RAM_15_SFT 0
+#define RG_RAM_15_HI 31
+#define RG_RAM_15_SZ 32
+#define RG_PMDLBK_MSK 0x00000001
+#define RG_PMDLBK_I_MSK 0xfffffffe
+#define RG_PMDLBK_SFT 0
+#define RG_PMDLBK_HI 0
+#define RG_PMDLBK_SZ 1
+#define RG_DAC_LBK_EDGE_SEL_MSK 0x00000002
+#define RG_DAC_LBK_EDGE_SEL_I_MSK 0xfffffffd
+#define RG_DAC_LBK_EDGE_SEL_SFT 1
+#define RG_DAC_LBK_EDGE_SEL_HI 1
+#define RG_DAC_LBK_EDGE_SEL_SZ 1
+#define RG_RSSI_EDGE_SEL_BB_MSK 0x00000004
+#define RG_RSSI_EDGE_SEL_BB_I_MSK 0xfffffffb
+#define RG_RSSI_EDGE_SEL_BB_SFT 2
+#define RG_RSSI_EDGE_SEL_BB_HI 2
+#define RG_RSSI_EDGE_SEL_BB_SZ 1
+#define RG_SIGN_SWAP_BB_MSK 0x00000010
+#define RG_SIGN_SWAP_BB_I_MSK 0xffffffef
+#define RG_SIGN_SWAP_BB_SFT 4
+#define RG_SIGN_SWAP_BB_HI 4
+#define RG_SIGN_SWAP_BB_SZ 1
+#define RG_IQ_SWAP_BB_MSK 0x00000020
+#define RG_IQ_SWAP_BB_I_MSK 0xffffffdf
+#define RG_IQ_SWAP_BB_SFT 5
+#define RG_IQ_SWAP_BB_HI 5
+#define RG_IQ_SWAP_BB_SZ 1
+#define RG_Q_INV_BB_MSK 0x00000040
+#define RG_Q_INV_BB_I_MSK 0xffffffbf
+#define RG_Q_INV_BB_SFT 6
+#define RG_Q_INV_BB_HI 6
+#define RG_Q_INV_BB_SZ 1
+#define RG_I_INV_BB_MSK 0x00000080
+#define RG_I_INV_BB_I_MSK 0xffffff7f
+#define RG_I_INV_BB_SFT 7
+#define RG_I_INV_BB_HI 7
+#define RG_I_INV_BB_SZ 1
+#define RG_BYPASS_ACI_MSK 0x00000100
+#define RG_BYPASS_ACI_I_MSK 0xfffffeff
+#define RG_BYPASS_ACI_SFT 8
+#define RG_BYPASS_ACI_HI 8
+#define RG_BYPASS_ACI_SZ 1
+#define RG_LBK_ANA_PATH_MSK 0x00000200
+#define RG_LBK_ANA_PATH_I_MSK 0xfffffdff
+#define RG_LBK_ANA_PATH_SFT 9
+#define RG_LBK_ANA_PATH_HI 9
+#define RG_LBK_ANA_PATH_SZ 1
+#define RG_LBK_DIG_SEL_MSK 0x00000400
+#define RG_LBK_DIG_SEL_I_MSK 0xfffffbff
+#define RG_LBK_DIG_SEL_SFT 10
+#define RG_LBK_DIG_SEL_HI 10
+#define RG_LBK_DIG_SEL_SZ 1
+#define RG_RF_5G_BAND_MSK 0x00000800
+#define RG_RF_5G_BAND_I_MSK 0xfffff7ff
+#define RG_RF_5G_BAND_SFT 11
+#define RG_RF_5G_BAND_HI 11
+#define RG_RF_5G_BAND_SZ 1
+#define RG_PRIMARY_CH_SIDE_MSK 0x00004000
+#define RG_PRIMARY_CH_SIDE_I_MSK 0xffffbfff
+#define RG_PRIMARY_CH_SIDE_SFT 14
+#define RG_PRIMARY_CH_SIDE_HI 14
+#define RG_PRIMARY_CH_SIDE_SZ 1
+#define RG_SYSTEM_BW_MSK 0x00008000
+#define RG_SYSTEM_BW_I_MSK 0xffff7fff
+#define RG_SYSTEM_BW_SFT 15
+#define RG_SYSTEM_BW_HI 15
+#define RG_SYSTEM_BW_SZ 1
+#define RG_11B_ACI_SEL_MSK 0x00010000
+#define RG_11B_ACI_SEL_I_MSK 0xfffeffff
+#define RG_11B_ACI_SEL_SFT 16
+#define RG_11B_ACI_SEL_HI 16
+#define RG_11B_ACI_SEL_SZ 1
+#define RG_BB_CLK_SEL_MSK 0x80000000
+#define RG_BB_CLK_SEL_I_MSK 0x7fffffff
+#define RG_BB_CLK_SEL_SFT 31
+#define RG_BB_CLK_SEL_HI 31
+#define RG_BB_CLK_SEL_SZ 1
+#define RG_PHY_MD_EN_MSK 0x00000001
+#define RG_PHY_MD_EN_I_MSK 0xfffffffe
+#define RG_PHY_MD_EN_SFT 0
+#define RG_PHY_MD_EN_HI 0
+#define RG_PHY_MD_EN_SZ 1
+#define RG_PHYRX_MD_EN_MSK 0x00000002
+#define RG_PHYRX_MD_EN_I_MSK 0xfffffffd
+#define RG_PHYRX_MD_EN_SFT 1
+#define RG_PHYRX_MD_EN_HI 1
+#define RG_PHYRX_MD_EN_SZ 1
+#define RG_PHYTX_MD_EN_MSK 0x00000004
+#define RG_PHYTX_MD_EN_I_MSK 0xfffffffb
+#define RG_PHYTX_MD_EN_SFT 2
+#define RG_PHYTX_MD_EN_HI 2
+#define RG_PHYTX_MD_EN_SZ 1
+#define RG_PHY11GN_MD_EN_MSK 0x00000008
+#define RG_PHY11GN_MD_EN_I_MSK 0xfffffff7
+#define RG_PHY11GN_MD_EN_SFT 3
+#define RG_PHY11GN_MD_EN_HI 3
+#define RG_PHY11GN_MD_EN_SZ 1
+#define RG_PHY11B_MD_EN_MSK 0x00000010
+#define RG_PHY11B_MD_EN_I_MSK 0xffffffef
+#define RG_PHY11B_MD_EN_SFT 4
+#define RG_PHY11B_MD_EN_HI 4
+#define RG_PHY11B_MD_EN_SZ 1
+#define RG_PHYRXFIFO_MD_EN_MSK 0x00000020
+#define RG_PHYRXFIFO_MD_EN_I_MSK 0xffffffdf
+#define RG_PHYRXFIFO_MD_EN_SFT 5
+#define RG_PHYRXFIFO_MD_EN_HI 5
+#define RG_PHYRXFIFO_MD_EN_SZ 1
+#define RG_PHYTXFIFO_MD_EN_MSK 0x00000040
+#define RG_PHYTXFIFO_MD_EN_I_MSK 0xffffffbf
+#define RG_PHYTXFIFO_MD_EN_SFT 6
+#define RG_PHYTXFIFO_MD_EN_HI 6
+#define RG_PHYTXFIFO_MD_EN_SZ 1
+#define RG_PHY11BGN_MD_EN_MSK 0x00000100
+#define RG_PHY11BGN_MD_EN_I_MSK 0xfffffeff
+#define RG_PHY11BGN_MD_EN_SFT 8
+#define RG_PHY11BGN_MD_EN_HI 8
+#define RG_PHY11BGN_MD_EN_SZ 1
+#define RG_FORCE_11GN_EN_MSK 0x00001000
+#define RG_FORCE_11GN_EN_I_MSK 0xffffefff
+#define RG_FORCE_11GN_EN_SFT 12
+#define RG_FORCE_11GN_EN_HI 12
+#define RG_FORCE_11GN_EN_SZ 1
+#define RG_FORCE_11B_EN_MSK 0x00002000
+#define RG_FORCE_11B_EN_I_MSK 0xffffdfff
+#define RG_FORCE_11B_EN_SFT 13
+#define RG_FORCE_11B_EN_HI 13
+#define RG_FORCE_11B_EN_SZ 1
+#define RG_PHY_IQ_TRIG_SEL_MSK 0x000f0000
+#define RG_PHY_IQ_TRIG_SEL_I_MSK 0xfff0ffff
+#define RG_PHY_IQ_TRIG_SEL_SFT 16
+#define RG_PHY_IQ_TRIG_SEL_HI 19
+#define RG_PHY_IQ_TRIG_SEL_SZ 4
+#define SVN_VERSION_MSK 0xffffffff
+#define SVN_VERSION_I_MSK 0x00000000
+#define SVN_VERSION_SFT 0
+#define SVN_VERSION_HI 31
+#define SVN_VERSION_SZ 32
+#define RG_LENGTH_MSK 0x0000ffff
+#define RG_LENGTH_I_MSK 0xffff0000
+#define RG_LENGTH_SFT 0
+#define RG_LENGTH_HI 15
+#define RG_LENGTH_SZ 16
+#define RG_PKT_MODE_MSK 0x00070000
+#define RG_PKT_MODE_I_MSK 0xfff8ffff
+#define RG_PKT_MODE_SFT 16
+#define RG_PKT_MODE_HI 18
+#define RG_PKT_MODE_SZ 3
+#define RG_CH_BW_MSK 0x00380000
+#define RG_CH_BW_I_MSK 0xffc7ffff
+#define RG_CH_BW_SFT 19
+#define RG_CH_BW_HI 21
+#define RG_CH_BW_SZ 3
+#define RG_PRM_MSK 0x00400000
+#define RG_PRM_I_MSK 0xffbfffff
+#define RG_PRM_SFT 22
+#define RG_PRM_HI 22
+#define RG_PRM_SZ 1
+#define RG_SHORTGI_MSK 0x00800000
+#define RG_SHORTGI_I_MSK 0xff7fffff
+#define RG_SHORTGI_SFT 23
+#define RG_SHORTGI_HI 23
+#define RG_SHORTGI_SZ 1
+#define RG_RATE_MSK 0x7f000000
+#define RG_RATE_I_MSK 0x80ffffff
+#define RG_RATE_SFT 24
+#define RG_RATE_HI 30
+#define RG_RATE_SZ 7
+#define RG_L_LENGTH_MSK 0x00000fff
+#define RG_L_LENGTH_I_MSK 0xfffff000
+#define RG_L_LENGTH_SFT 0
+#define RG_L_LENGTH_HI 11
+#define RG_L_LENGTH_SZ 12
+#define RG_L_RATE_MSK 0x00007000
+#define RG_L_RATE_I_MSK 0xffff8fff
+#define RG_L_RATE_SFT 12
+#define RG_L_RATE_HI 14
+#define RG_L_RATE_SZ 3
+#define RG_SERVICE_MSK 0xffff0000
+#define RG_SERVICE_I_MSK 0x0000ffff
+#define RG_SERVICE_SFT 16
+#define RG_SERVICE_HI 31
+#define RG_SERVICE_SZ 16
+#define RG_SMOOTHING_MSK 0x00000001
+#define RG_SMOOTHING_I_MSK 0xfffffffe
+#define RG_SMOOTHING_SFT 0
+#define RG_SMOOTHING_HI 0
+#define RG_SMOOTHING_SZ 1
+#define RG_NO_SOUND_MSK 0x00000002
+#define RG_NO_SOUND_I_MSK 0xfffffffd
+#define RG_NO_SOUND_SFT 1
+#define RG_NO_SOUND_HI 1
+#define RG_NO_SOUND_SZ 1
+#define RG_AGGREGATE_MSK 0x00000004
+#define RG_AGGREGATE_I_MSK 0xfffffffb
+#define RG_AGGREGATE_SFT 2
+#define RG_AGGREGATE_HI 2
+#define RG_AGGREGATE_SZ 1
+#define RG_STBC_MSK 0x00000018
+#define RG_STBC_I_MSK 0xffffffe7
+#define RG_STBC_SFT 3
+#define RG_STBC_HI 4
+#define RG_STBC_SZ 2
+#define RG_FEC_MSK 0x00000020
+#define RG_FEC_I_MSK 0xffffffdf
+#define RG_FEC_SFT 5
+#define RG_FEC_HI 5
+#define RG_FEC_SZ 1
+#define RG_N_ESS_MSK 0x000000c0
+#define RG_N_ESS_I_MSK 0xffffff3f
+#define RG_N_ESS_SFT 6
+#define RG_N_ESS_HI 7
+#define RG_N_ESS_SZ 2
+#define RG_TXPWRLVL_MSK 0x00007f00
+#define RG_TXPWRLVL_I_MSK 0xffff80ff
+#define RG_TXPWRLVL_SFT 8
+#define RG_TXPWRLVL_HI 14
+#define RG_TXPWRLVL_SZ 7
+#define RG_BB_SCALE_MSK 0x00ff0000
+#define RG_BB_SCALE_I_MSK 0xff00ffff
+#define RG_BB_SCALE_SFT 16
+#define RG_BB_SCALE_HI 23
+#define RG_BB_SCALE_SZ 8
+#define RG_TX_START_MSK 0x00000001
+#define RG_TX_START_I_MSK 0xfffffffe
+#define RG_TX_START_SFT 0
+#define RG_TX_START_HI 0
+#define RG_TX_START_SZ 1
+#define RG_IFS_TIME_MSK 0x000000fc
+#define RG_IFS_TIME_I_MSK 0xffffff03
+#define RG_IFS_TIME_SFT 2
+#define RG_IFS_TIME_HI 7
+#define RG_IFS_TIME_SZ 6
+#define RG_CONTINUOUS_DATA_MSK 0x00000100
+#define RG_CONTINUOUS_DATA_I_MSK 0xfffffeff
+#define RG_CONTINUOUS_DATA_SFT 8
+#define RG_CONTINUOUS_DATA_HI 8
+#define RG_CONTINUOUS_DATA_SZ 1
+#define RG_DATA_SEL_MSK 0x00000600
+#define RG_DATA_SEL_I_MSK 0xfffff9ff
+#define RG_DATA_SEL_SFT 9
+#define RG_DATA_SEL_HI 10
+#define RG_DATA_SEL_SZ 2
+#define RG_TX_D_MSK 0x00ff0000
+#define RG_TX_D_I_MSK 0xff00ffff
+#define RG_TX_D_SFT 16
+#define RG_TX_D_HI 23
+#define RG_TX_D_SZ 8
+#define RG_IFS_TIME_EXT_MSK 0xff000000
+#define RG_IFS_TIME_EXT_I_MSK 0x00ffffff
+#define RG_IFS_TIME_EXT_SFT 24
+#define RG_IFS_TIME_EXT_HI 31
+#define RG_IFS_TIME_EXT_SZ 8
+#define RG_TX_CNT_TARGET_MSK 0xffffffff
+#define RG_TX_CNT_TARGET_I_MSK 0x00000000
+#define RG_TX_CNT_TARGET_SFT 0
+#define RG_TX_CNT_TARGET_HI 31
+#define RG_TX_CNT_TARGET_SZ 32
+#define RG_TXD_SEL_MSK 0x00000c00
+#define RG_TXD_SEL_I_MSK 0xfffff3ff
+#define RG_TXD_SEL_SFT 10
+#define RG_TXD_SEL_HI 11
+#define RG_TXD_SEL_SZ 2
+#define RG_TX_FREQ_OFFSET_DES_MSK 0x0000ffff
+#define RG_TX_FREQ_OFFSET_DES_I_MSK 0xffff0000
+#define RG_TX_FREQ_OFFSET_DES_SFT 0
+#define RG_TX_FREQ_OFFSET_DES_HI 15
+#define RG_TX_FREQ_OFFSET_DES_SZ 16
+#define RG_DES_RATE_MSK 0x000000ff
+#define RG_DES_RATE_I_MSK 0xffffff00
+#define RG_DES_RATE_SFT 0
+#define RG_DES_RATE_HI 7
+#define RG_DES_RATE_SZ 8
+#define RG_DES_MAN_EN_MSK 0x80000000
+#define RG_DES_MAN_EN_I_MSK 0x7fffffff
+#define RG_DES_MAN_EN_SFT 31
+#define RG_DES_MAN_EN_HI 31
+#define RG_DES_MAN_EN_SZ 1
+#define RG_PGA_REFDB_SAT_B_MSK 0x0000007f
+#define RG_PGA_REFDB_SAT_B_I_MSK 0xffffff80
+#define RG_PGA_REFDB_SAT_B_SFT 0
+#define RG_PGA_REFDB_SAT_B_HI 6
+#define RG_PGA_REFDB_SAT_B_SZ 7
+#define RG_PGA_REFDB_TOP_B_MSK 0x00007f00
+#define RG_PGA_REFDB_TOP_B_I_MSK 0xffff80ff
+#define RG_PGA_REFDB_TOP_B_SFT 8
+#define RG_PGA_REFDB_TOP_B_HI 14
+#define RG_PGA_REFDB_TOP_B_SZ 7
+#define RG_PGA_REF_UND_B_MSK 0x03ff0000
+#define RG_PGA_REF_UND_B_I_MSK 0xfc00ffff
+#define RG_PGA_REF_UND_B_SFT 16
+#define RG_PGA_REF_UND_B_HI 25
+#define RG_PGA_REF_UND_B_SZ 10
+#define RG_RF_REF_SAT_B_MSK 0xf0000000
+#define RG_RF_REF_SAT_B_I_MSK 0x0fffffff
+#define RG_RF_REF_SAT_B_SFT 28
+#define RG_RF_REF_SAT_B_HI 31
+#define RG_RF_REF_SAT_B_SZ 4
+#define RG_PGA_REFDB_SAT_GN_MSK 0x0000007f
+#define RG_PGA_REFDB_SAT_GN_I_MSK 0xffffff80
+#define RG_PGA_REFDB_SAT_GN_SFT 0
+#define RG_PGA_REFDB_SAT_GN_HI 6
+#define RG_PGA_REFDB_SAT_GN_SZ 7
+#define RG_PGA_REFDB_TOP_GN_MSK 0x00007f00
+#define RG_PGA_REFDB_TOP_GN_I_MSK 0xffff80ff
+#define RG_PGA_REFDB_TOP_GN_SFT 8
+#define RG_PGA_REFDB_TOP_GN_HI 14
+#define RG_PGA_REFDB_TOP_GN_SZ 7
+#define RG_PGA_REF_UND_GN_MSK 0x03ff0000
+#define RG_PGA_REF_UND_GN_I_MSK 0xfc00ffff
+#define RG_PGA_REF_UND_GN_SFT 16
+#define RG_PGA_REF_UND_GN_HI 25
+#define RG_PGA_REF_UND_GN_SZ 10
+#define RG_RF_REF_SAT_GN_MSK 0xf0000000
+#define RG_RF_REF_SAT_GN_I_MSK 0x0fffffff
+#define RG_RF_REF_SAT_GN_SFT 28
+#define RG_RF_REF_SAT_GN_HI 31
+#define RG_RF_REF_SAT_GN_SZ 4
+#define RG_PGAGC_SET_MSK 0x0000000f
+#define RG_PGAGC_SET_I_MSK 0xfffffff0
+#define RG_PGAGC_SET_SFT 0
+#define RG_PGAGC_SET_HI 3
+#define RG_PGAGC_SET_SZ 4
+#define RG_PGAGC_OW_MSK 0x00000010
+#define RG_PGAGC_OW_I_MSK 0xffffffef
+#define RG_PGAGC_OW_SFT 4
+#define RG_PGAGC_OW_HI 4
+#define RG_PGAGC_OW_SZ 1
+#define RG_RFGC_SET_MSK 0x00000060
+#define RG_RFGC_SET_I_MSK 0xffffff9f
+#define RG_RFGC_SET_SFT 5
+#define RG_RFGC_SET_HI 6
+#define RG_RFGC_SET_SZ 2
+#define RG_RFGC_OW_MSK 0x00000080
+#define RG_RFGC_OW_I_MSK 0xffffff7f
+#define RG_RFGC_OW_SFT 7
+#define RG_RFGC_OW_HI 7
+#define RG_RFGC_OW_SZ 1
+#define RG_WAIT_T_RXAGC_MSK 0x00003f00
+#define RG_WAIT_T_RXAGC_I_MSK 0xffffc0ff
+#define RG_WAIT_T_RXAGC_SFT 8
+#define RG_WAIT_T_RXAGC_HI 13
+#define RG_WAIT_T_RXAGC_SZ 6
+#define RG_RXAGC_SET_MSK 0x00004000
+#define RG_RXAGC_SET_I_MSK 0xffffbfff
+#define RG_RXAGC_SET_SFT 14
+#define RG_RXAGC_SET_HI 14
+#define RG_RXAGC_SET_SZ 1
+#define RG_RXAGC_OW_MSK 0x00008000
+#define RG_RXAGC_OW_I_MSK 0xffff7fff
+#define RG_RXAGC_OW_SFT 15
+#define RG_RXAGC_OW_HI 15
+#define RG_RXAGC_OW_SZ 1
+#define RG_WAIT_T_FINAL_MSK 0x003f0000
+#define RG_WAIT_T_FINAL_I_MSK 0xffc0ffff
+#define RG_WAIT_T_FINAL_SFT 16
+#define RG_WAIT_T_FINAL_HI 21
+#define RG_WAIT_T_FINAL_SZ 6
+#define RG_WAIT_T_MSK 0x3f000000
+#define RG_WAIT_T_I_MSK 0xc0ffffff
+#define RG_WAIT_T_SFT 24
+#define RG_WAIT_T_HI 29
+#define RG_WAIT_T_SZ 6
+#define RG_ULG_PGA_SAT_PGA_GAIN_MSK 0x0000000f
+#define RG_ULG_PGA_SAT_PGA_GAIN_I_MSK 0xfffffff0
+#define RG_ULG_PGA_SAT_PGA_GAIN_SFT 0
+#define RG_ULG_PGA_SAT_PGA_GAIN_HI 3
+#define RG_ULG_PGA_SAT_PGA_GAIN_SZ 4
+#define RG_LG_PGA_UND_PGA_GAIN_MSK 0x000000f0
+#define RG_LG_PGA_UND_PGA_GAIN_I_MSK 0xffffff0f
+#define RG_LG_PGA_UND_PGA_GAIN_SFT 4
+#define RG_LG_PGA_UND_PGA_GAIN_HI 7
+#define RG_LG_PGA_UND_PGA_GAIN_SZ 4
+#define RG_LG_PGA_SAT_PGA_GAIN_MSK 0x00000f00
+#define RG_LG_PGA_SAT_PGA_GAIN_I_MSK 0xfffff0ff
+#define RG_LG_PGA_SAT_PGA_GAIN_SFT 8
+#define RG_LG_PGA_SAT_PGA_GAIN_HI 11
+#define RG_LG_PGA_SAT_PGA_GAIN_SZ 4
+#define RG_LG_RF_SAT_PGA_GAIN_MSK 0x0000f000
+#define RG_LG_RF_SAT_PGA_GAIN_I_MSK 0xffff0fff
+#define RG_LG_RF_SAT_PGA_GAIN_SFT 12
+#define RG_LG_RF_SAT_PGA_GAIN_HI 15
+#define RG_LG_RF_SAT_PGA_GAIN_SZ 4
+#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_MSK 0x000f0000
+#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_I_MSK 0xfff0ffff
+#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_SFT 16
+#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_HI 19
+#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_SZ 4
+#define RG_HG_PGA_SAT2_PGA_GAIN_MSK 0x00f00000
+#define RG_HG_PGA_SAT2_PGA_GAIN_I_MSK 0xff0fffff
+#define RG_HG_PGA_SAT2_PGA_GAIN_SFT 20
+#define RG_HG_PGA_SAT2_PGA_GAIN_HI 23
+#define RG_HG_PGA_SAT2_PGA_GAIN_SZ 4
+#define RG_HG_PGA_SAT1_PGA_GAIN_MSK 0x0f000000
+#define RG_HG_PGA_SAT1_PGA_GAIN_I_MSK 0xf0ffffff
+#define RG_HG_PGA_SAT1_PGA_GAIN_SFT 24
+#define RG_HG_PGA_SAT1_PGA_GAIN_HI 27
+#define RG_HG_PGA_SAT1_PGA_GAIN_SZ 4
+#define RG_HG_RF_SAT_PGA_GAIN_MSK 0xf0000000
+#define RG_HG_RF_SAT_PGA_GAIN_I_MSK 0x0fffffff
+#define RG_HG_RF_SAT_PGA_GAIN_SFT 28
+#define RG_HG_RF_SAT_PGA_GAIN_HI 31
+#define RG_HG_RF_SAT_PGA_GAIN_SZ 4
+#define RG_MG_PGA_JB_TH_MSK 0x0000000f
+#define RG_MG_PGA_JB_TH_I_MSK 0xfffffff0
+#define RG_MG_PGA_JB_TH_SFT 0
+#define RG_MG_PGA_JB_TH_HI 3
+#define RG_MG_PGA_JB_TH_SZ 4
+#define RG_MA_PGA_LOW_TH_CNT_LMT_MSK 0x001f0000
+#define RG_MA_PGA_LOW_TH_CNT_LMT_I_MSK 0xffe0ffff
+#define RG_MA_PGA_LOW_TH_CNT_LMT_SFT 16
+#define RG_MA_PGA_LOW_TH_CNT_LMT_HI 20
+#define RG_MA_PGA_LOW_TH_CNT_LMT_SZ 5
+#define RG_MA_PGA_HIGH_TH_CNT_LMT_MSK 0x1f000000
+#define RG_MA_PGA_HIGH_TH_CNT_LMT_I_MSK 0xe0ffffff
+#define RG_MA_PGA_HIGH_TH_CNT_LMT_SFT 24
+#define RG_MA_PGA_HIGH_TH_CNT_LMT_HI 28
+#define RG_MA_PGA_HIGH_TH_CNT_LMT_SZ 5
+#define RG_AGC_THRESHOLD_MSK 0x00003fff
+#define RG_AGC_THRESHOLD_I_MSK 0xffffc000
+#define RG_AGC_THRESHOLD_SFT 0
+#define RG_AGC_THRESHOLD_HI 13
+#define RG_AGC_THRESHOLD_SZ 14
+#define RG_ACI_POINT_CNT_LMT_11B_MSK 0x007f0000
+#define RG_ACI_POINT_CNT_LMT_11B_I_MSK 0xff80ffff
+#define RG_ACI_POINT_CNT_LMT_11B_SFT 16
+#define RG_ACI_POINT_CNT_LMT_11B_HI 22
+#define RG_ACI_POINT_CNT_LMT_11B_SZ 7
+#define RG_ACI_DAGC_LEAKY_FACTOR_11B_MSK 0x03000000
+#define RG_ACI_DAGC_LEAKY_FACTOR_11B_I_MSK 0xfcffffff
+#define RG_ACI_DAGC_LEAKY_FACTOR_11B_SFT 24
+#define RG_ACI_DAGC_LEAKY_FACTOR_11B_HI 25
+#define RG_ACI_DAGC_LEAKY_FACTOR_11B_SZ 2
+#define RG_ACI_DAGC_PWR_SEL_11B_MSK 0x10000000
+#define RG_ACI_DAGC_PWR_SEL_11B_I_MSK 0xefffffff
+#define RG_ACI_DAGC_PWR_SEL_11B_SFT 28
+#define RG_ACI_DAGC_PWR_SEL_11B_HI 28
+#define RG_ACI_DAGC_PWR_SEL_11B_SZ 1
+#define RG_ACI_DAGC_TARGET_11B_MSK 0x0000007f
+#define RG_ACI_DAGC_TARGET_11B_I_MSK 0xffffff80
+#define RG_ACI_DAGC_TARGET_11B_SFT 0
+#define RG_ACI_DAGC_TARGET_11B_HI 6
+#define RG_ACI_DAGC_TARGET_11B_SZ 7
+#define RG_ACI_GAIN_INI_11B_MSK 0x0000ff00
+#define RG_ACI_GAIN_INI_11B_I_MSK 0xffff00ff
+#define RG_ACI_GAIN_INI_11B_SFT 8
+#define RG_ACI_GAIN_INI_11B_HI 15
+#define RG_ACI_GAIN_INI_11B_SZ 8
+#define RG_ACI_GAIN_SET_11B_MSK 0x00ff0000
+#define RG_ACI_GAIN_SET_11B_I_MSK 0xff00ffff
+#define RG_ACI_GAIN_SET_11B_SFT 16
+#define RG_ACI_GAIN_SET_11B_HI 23
+#define RG_ACI_GAIN_SET_11B_SZ 8
+#define RG_ACI_GAIN_OW_11B_MSK 0x80000000
+#define RG_ACI_GAIN_OW_11B_I_MSK 0x7fffffff
+#define RG_ACI_GAIN_OW_11B_SFT 31
+#define RG_ACI_GAIN_OW_11B_HI 31
+#define RG_ACI_GAIN_OW_11B_SZ 1
+#define RG_ACI_POINT_CNT_LMT_11GN_HT20_MSK 0x000000ff
+#define RG_ACI_POINT_CNT_LMT_11GN_HT20_I_MSK 0xffffff00
+#define RG_ACI_POINT_CNT_LMT_11GN_HT20_SFT 0
+#define RG_ACI_POINT_CNT_LMT_11GN_HT20_HI 7
+#define RG_ACI_POINT_CNT_LMT_11GN_HT20_SZ 8
+#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_HT20_MSK 0x00000300
+#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_HT20_I_MSK 0xfffffcff
+#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_HT20_SFT 8
+#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_HT20_HI 9
+#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_HT20_SZ 2
+#define RG_ACI_DAGC_PWR_SEL_11GN_HT20_MSK 0x00001000
+#define RG_ACI_DAGC_PWR_SEL_11GN_HT20_I_MSK 0xffffefff
+#define RG_ACI_DAGC_PWR_SEL_11GN_HT20_SFT 12
+#define RG_ACI_DAGC_PWR_SEL_11GN_HT20_HI 12
+#define RG_ACI_DAGC_PWR_SEL_11GN_HT20_SZ 1
+#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_MSK 0xff000000
+#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_I_MSK 0x00ffffff
+#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_SFT 24
+#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_HI 31
+#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_SZ 8
+#define RG_ACI_DAGC_TARGET_11GN_HT20_MSK 0x0000007f
+#define RG_ACI_DAGC_TARGET_11GN_HT20_I_MSK 0xffffff80
+#define RG_ACI_DAGC_TARGET_11GN_HT20_SFT 0
+#define RG_ACI_DAGC_TARGET_11GN_HT20_HI 6
+#define RG_ACI_DAGC_TARGET_11GN_HT20_SZ 7
+#define RG_ACI_GAIN_SET_11GN_HT20_MSK 0x01ff0000
+#define RG_ACI_GAIN_SET_11GN_HT20_I_MSK 0xfe00ffff
+#define RG_ACI_GAIN_SET_11GN_HT20_SFT 16
+#define RG_ACI_GAIN_SET_11GN_HT20_HI 24
+#define RG_ACI_GAIN_SET_11GN_HT20_SZ 9
+#define RG_ACI_GAIN_OW_11GN_HT20_MSK 0x80000000
+#define RG_ACI_GAIN_OW_11GN_HT20_I_MSK 0x7fffffff
+#define RG_ACI_GAIN_OW_11GN_HT20_SFT 31
+#define RG_ACI_GAIN_OW_11GN_HT20_HI 31
+#define RG_ACI_GAIN_OW_11GN_HT20_SZ 1
+#define RO_CCA_PWR_MA_11GN_HT40_MSK 0x0000007f
+#define RO_CCA_PWR_MA_11GN_HT40_I_MSK 0xffffff80
+#define RO_CCA_PWR_MA_11GN_HT40_SFT 0
+#define RO_CCA_PWR_MA_11GN_HT40_HI 6
+#define RO_CCA_PWR_MA_11GN_HT40_SZ 7
+#define RO_CCA_PWR_MA_11GN_HT20_MSK 0x00007f00
+#define RO_CCA_PWR_MA_11GN_HT20_I_MSK 0xffff80ff
+#define RO_CCA_PWR_MA_11GN_HT20_SFT 8
+#define RO_CCA_PWR_MA_11GN_HT20_HI 14
+#define RO_CCA_PWR_MA_11GN_HT20_SZ 7
+#define RO_CCA_PWR_MA_11B_MSK 0x007f0000
+#define RO_CCA_PWR_MA_11B_I_MSK 0xff80ffff
+#define RO_CCA_PWR_MA_11B_SFT 16
+#define RO_CCA_PWR_MA_11B_HI 22
+#define RO_CCA_PWR_MA_11B_SZ 7
+#define RO_ED_STATE_MSK 0x01000000
+#define RO_ED_STATE_I_MSK 0xfeffffff
+#define RO_ED_STATE_SFT 24
+#define RO_ED_STATE_HI 24
+#define RO_ED_STATE_SZ 1
+#define RO_2ND_ED_STATE_MSK 0x02000000
+#define RO_2ND_ED_STATE_I_MSK 0xfdffffff
+#define RO_2ND_ED_STATE_SFT 25
+#define RO_2ND_ED_STATE_HI 25
+#define RO_2ND_ED_STATE_SZ 1
+#define RO_PGA_PWR_FF1_MSK 0x00003fff
+#define RO_PGA_PWR_FF1_I_MSK 0xffffc000
+#define RO_PGA_PWR_FF1_SFT 0
+#define RO_PGA_PWR_FF1_HI 13
+#define RO_PGA_PWR_FF1_SZ 14
+#define RO_RF_PWR_FF1_MSK 0x000f0000
+#define RO_RF_PWR_FF1_I_MSK 0xfff0ffff
+#define RO_RF_PWR_FF1_SFT 16
+#define RO_RF_PWR_FF1_HI 19
+#define RO_RF_PWR_FF1_SZ 4
+#define RO_PGAGC_FF1_MSK 0x0f000000
+#define RO_PGAGC_FF1_I_MSK 0xf0ffffff
+#define RO_PGAGC_FF1_SFT 24
+#define RO_PGAGC_FF1_HI 27
+#define RO_PGAGC_FF1_SZ 4
+#define RO_RFGC_FF1_MSK 0x30000000
+#define RO_RFGC_FF1_I_MSK 0xcfffffff
+#define RO_RFGC_FF1_SFT 28
+#define RO_RFGC_FF1_HI 29
+#define RO_RFGC_FF1_SZ 2
+#define RO_PGA_PWR_FF2_MSK 0x00003fff
+#define RO_PGA_PWR_FF2_I_MSK 0xffffc000
+#define RO_PGA_PWR_FF2_SFT 0
+#define RO_PGA_PWR_FF2_HI 13
+#define RO_PGA_PWR_FF2_SZ 14
+#define RO_RF_PWR_FF2_MSK 0x000f0000
+#define RO_RF_PWR_FF2_I_MSK 0xfff0ffff
+#define RO_RF_PWR_FF2_SFT 16
+#define RO_RF_PWR_FF2_HI 19
+#define RO_RF_PWR_FF2_SZ 4
+#define RO_PGAGC_FF2_MSK 0x0f000000
+#define RO_PGAGC_FF2_I_MSK 0xf0ffffff
+#define RO_PGAGC_FF2_SFT 24
+#define RO_PGAGC_FF2_HI 27
+#define RO_PGAGC_FF2_SZ 4
+#define RO_RFGC_FF2_MSK 0x30000000
+#define RO_RFGC_FF2_I_MSK 0xcfffffff
+#define RO_RFGC_FF2_SFT 28
+#define RO_RFGC_FF2_HI 29
+#define RO_RFGC_FF2_SZ 2
+#define RO_PGA_PWR_FF3_MSK 0x00003fff
+#define RO_PGA_PWR_FF3_I_MSK 0xffffc000
+#define RO_PGA_PWR_FF3_SFT 0
+#define RO_PGA_PWR_FF3_HI 13
+#define RO_PGA_PWR_FF3_SZ 14
+#define RO_RF_PWR_FF3_MSK 0x000f0000
+#define RO_RF_PWR_FF3_I_MSK 0xfff0ffff
+#define RO_RF_PWR_FF3_SFT 16
+#define RO_RF_PWR_FF3_HI 19
+#define RO_RF_PWR_FF3_SZ 4
+#define RO_PGAGC_FF3_MSK 0x0f000000
+#define RO_PGAGC_FF3_I_MSK 0xf0ffffff
+#define RO_PGAGC_FF3_SFT 24
+#define RO_PGAGC_FF3_HI 27
+#define RO_PGAGC_FF3_SZ 4
+#define RO_RFGC_FF3_MSK 0x30000000
+#define RO_RFGC_FF3_I_MSK 0xcfffffff
+#define RO_RFGC_FF3_SFT 28
+#define RO_RFGC_FF3_HI 29
+#define RO_RFGC_FF3_SZ 2
+#define RG_5G_DC_RM_LEAKY_FACTOR_T3_MSK 0x00000070
+#define RG_5G_DC_RM_LEAKY_FACTOR_T3_I_MSK 0xffffff8f
+#define RG_5G_DC_RM_LEAKY_FACTOR_T3_SFT 4
+#define RG_5G_DC_RM_LEAKY_FACTOR_T3_HI 6
+#define RG_5G_DC_RM_LEAKY_FACTOR_T3_SZ 3
+#define RG_5G_DC_RM_LEAKY_FACTOR_T2_MSK 0x00000700
+#define RG_5G_DC_RM_LEAKY_FACTOR_T2_I_MSK 0xfffff8ff
+#define RG_5G_DC_RM_LEAKY_FACTOR_T2_SFT 8
+#define RG_5G_DC_RM_LEAKY_FACTOR_T2_HI 10
+#define RG_5G_DC_RM_LEAKY_FACTOR_T2_SZ 3
+#define RG_5G_DC_RM_LEAKY_FACTOR_T1_MSK 0x00007000
+#define RG_5G_DC_RM_LEAKY_FACTOR_T1_I_MSK 0xffff8fff
+#define RG_5G_DC_RM_LEAKY_FACTOR_T1_SFT 12
+#define RG_5G_DC_RM_LEAKY_FACTOR_T1_HI 14
+#define RG_5G_DC_RM_LEAKY_FACTOR_T1_SZ 3
+#define RG_DC_RM_BYP_MSK 0x00010000
+#define RG_DC_RM_BYP_I_MSK 0xfffeffff
+#define RG_DC_RM_BYP_SFT 16
+#define RG_DC_RM_BYP_HI 16
+#define RG_DC_RM_BYP_SZ 1
+#define RG_DC_RM_LEAKY_FACTOR_T3_MSK 0x00700000
+#define RG_DC_RM_LEAKY_FACTOR_T3_I_MSK 0xff8fffff
+#define RG_DC_RM_LEAKY_FACTOR_T3_SFT 20
+#define RG_DC_RM_LEAKY_FACTOR_T3_HI 22
+#define RG_DC_RM_LEAKY_FACTOR_T3_SZ 3
+#define RG_DC_RM_LEAKY_FACTOR_T2_MSK 0x07000000
+#define RG_DC_RM_LEAKY_FACTOR_T2_I_MSK 0xf8ffffff
+#define RG_DC_RM_LEAKY_FACTOR_T2_SFT 24
+#define RG_DC_RM_LEAKY_FACTOR_T2_HI 26
+#define RG_DC_RM_LEAKY_FACTOR_T2_SZ 3
+#define RG_DC_RM_LEAKY_FACTOR_T1_MSK 0x70000000
+#define RG_DC_RM_LEAKY_FACTOR_T1_I_MSK 0x8fffffff
+#define RG_DC_RM_LEAKY_FACTOR_T1_SFT 28
+#define RG_DC_RM_LEAKY_FACTOR_T1_HI 30
+#define RG_DC_RM_LEAKY_FACTOR_T1_SZ 3
+#define RO_Q_DC_OUT_MSK 0x000003ff
+#define RO_Q_DC_OUT_I_MSK 0xfffffc00
+#define RO_Q_DC_OUT_SFT 0
+#define RO_Q_DC_OUT_HI 9
+#define RO_Q_DC_OUT_SZ 10
+#define RO_I_DC_OUT_MSK 0x03ff0000
+#define RO_I_DC_OUT_I_MSK 0xfc00ffff
+#define RO_I_DC_OUT_SFT 16
+#define RO_I_DC_OUT_HI 25
+#define RO_I_DC_OUT_SZ 10
+#define RG_TBUS_SEL_MSK 0x0000000f
+#define RG_TBUS_SEL_I_MSK 0xfffffff0
+#define RG_TBUS_SEL_SFT 0
+#define RG_TBUS_SEL_HI 3
+#define RG_TBUS_SEL_SZ 4
+#define RG_RSSI_OFFSET_MSK 0x00ff0000
+#define RG_RSSI_OFFSET_I_MSK 0xff00ffff
+#define RG_RSSI_OFFSET_SFT 16
+#define RG_RSSI_OFFSET_HI 23
+#define RG_RSSI_OFFSET_SZ 8
+#define RG_RSSI_INV_MSK 0x01000000
+#define RG_RSSI_INV_I_MSK 0xfeffffff
+#define RG_RSSI_INV_SFT 24
+#define RG_RSSI_INV_HI 24
+#define RG_RSSI_INV_SZ 1
+#define RO_MRX_EN_CNT_MSK 0x0000ffff
+#define RO_MRX_EN_CNT_I_MSK 0xffff0000
+#define RO_MRX_EN_CNT_SFT 0
+#define RO_MRX_EN_CNT_HI 15
+#define RO_MRX_EN_CNT_SZ 16
+#define RG_MRX_EN_CNT_RST_N_MSK 0x80000000
+#define RG_MRX_EN_CNT_RST_N_I_MSK 0x7fffffff
+#define RG_MRX_EN_CNT_RST_N_SFT 31
+#define RG_MRX_EN_CNT_RST_N_HI 31
+#define RG_MRX_EN_CNT_RST_N_SZ 1
+#define RG_EDCCA_AVG_T_MSK 0x00000007
+#define RG_EDCCA_AVG_T_I_MSK 0xfffffff8
+#define RG_EDCCA_AVG_T_SFT 0
+#define RG_EDCCA_AVG_T_HI 2
+#define RG_EDCCA_AVG_T_SZ 3
+#define RG_EDCCA_STAT_EN_MSK 0x00000010
+#define RG_EDCCA_STAT_EN_I_MSK 0xffffffef
+#define RG_EDCCA_STAT_EN_SFT 4
+#define RG_EDCCA_STAT_EN_HI 4
+#define RG_EDCCA_STAT_EN_SZ 1
+#define RO_EDCCA_PRIMARY_PRD_MSK 0x0000ffff
+#define RO_EDCCA_PRIMARY_PRD_I_MSK 0xffff0000
+#define RO_EDCCA_PRIMARY_PRD_SFT 0
+#define RO_EDCCA_PRIMARY_PRD_HI 15
+#define RO_EDCCA_PRIMARY_PRD_SZ 16
+#define RO_PRIMARY_EDCCA_MSK 0xffff0000
+#define RO_PRIMARY_EDCCA_I_MSK 0x0000ffff
+#define RO_PRIMARY_EDCCA_SFT 16
+#define RO_PRIMARY_EDCCA_HI 31
+#define RO_PRIMARY_EDCCA_SZ 16
+#define RO_EDCCA_SECONDARY_PRD_MSK 0x0000ffff
+#define RO_EDCCA_SECONDARY_PRD_I_MSK 0xffff0000
+#define RO_EDCCA_SECONDARY_PRD_SFT 0
+#define RO_EDCCA_SECONDARY_PRD_HI 15
+#define RO_EDCCA_SECONDARY_PRD_SZ 16
+#define RO_SECONDARY_EDCCA_MSK 0xffff0000
+#define RO_SECONDARY_EDCCA_I_MSK 0x0000ffff
+#define RO_SECONDARY_EDCCA_SFT 16
+#define RO_SECONDARY_EDCCA_HI 31
+#define RO_SECONDARY_EDCCA_SZ 16
+#define RG_AGC_RELOCK_PWR_TH_MSK 0x00003fff
+#define RG_AGC_RELOCK_PWR_TH_I_MSK 0xffffc000
+#define RG_AGC_RELOCK_PWR_TH_SFT 0
+#define RG_AGC_RELOCK_PWR_TH_HI 13
+#define RG_AGC_RELOCK_PWR_TH_SZ 14
+#define RG_AGC_RELOCK_CNT_TH_MSK 0x003f0000
+#define RG_AGC_RELOCK_CNT_TH_I_MSK 0xffc0ffff
+#define RG_AGC_RELOCK_CNT_TH_SFT 16
+#define RG_AGC_RELOCK_CNT_TH_HI 21
+#define RG_AGC_RELOCK_CNT_TH_SZ 6
+#define RG_AGC_RELOCK_SEL_MSK 0x03000000
+#define RG_AGC_RELOCK_SEL_I_MSK 0xfcffffff
+#define RG_AGC_RELOCK_SEL_SFT 24
+#define RG_AGC_RELOCK_SEL_HI 25
+#define RG_AGC_RELOCK_SEL_SZ 2
+#define RG_AGC_RELOCK_EN_MSK 0x10000000
+#define RG_AGC_RELOCK_EN_I_MSK 0xefffffff
+#define RG_AGC_RELOCK_EN_SFT 28
+#define RG_AGC_RELOCK_EN_HI 28
+#define RG_AGC_RELOCK_EN_SZ 1
+#define RG_AGC_RELOCK_11GN_MSK 0x40000000
+#define RG_AGC_RELOCK_11GN_I_MSK 0xbfffffff
+#define RG_AGC_RELOCK_11GN_SFT 30
+#define RG_AGC_RELOCK_11GN_HI 30
+#define RG_AGC_RELOCK_11GN_SZ 1
+#define RG_AGC_RELOCK_11B_MSK 0x80000000
+#define RG_AGC_RELOCK_11B_I_MSK 0x7fffffff
+#define RG_AGC_RELOCK_11B_SFT 31
+#define RG_AGC_RELOCK_11B_HI 31
+#define RG_AGC_RELOCK_11B_SZ 1
+#define RG_AGC_RELOCK_PWR_DIFFDB_TH_MSK 0x0000007f
+#define RG_AGC_RELOCK_PWR_DIFFDB_TH_I_MSK 0xffffff80
+#define RG_AGC_RELOCK_PWR_DIFFDB_TH_SFT 0
+#define RG_AGC_RELOCK_PWR_DIFFDB_TH_HI 6
+#define RG_AGC_RELOCK_PWR_DIFFDB_TH_SZ 7
+#define RG_AGC_RELOCK_CNT_DIFFDB_TH_MSK 0x003f0000
+#define RG_AGC_RELOCK_CNT_DIFFDB_TH_I_MSK 0xffc0ffff
+#define RG_AGC_RELOCK_CNT_DIFFDB_TH_SFT 16
+#define RG_AGC_RELOCK_CNT_DIFFDB_TH_HI 21
+#define RG_AGC_RELOCK_CNT_DIFFDB_TH_SZ 6
+#define RG_MTX_LEN_LOWER_TH_0_MSK 0x0000ffff
+#define RG_MTX_LEN_LOWER_TH_0_I_MSK 0xffff0000
+#define RG_MTX_LEN_LOWER_TH_0_SFT 0
+#define RG_MTX_LEN_LOWER_TH_0_HI 15
+#define RG_MTX_LEN_LOWER_TH_0_SZ 16
+#define RG_MTX_LEN_UPPER_TH_0_MSK 0xffff0000
+#define RG_MTX_LEN_UPPER_TH_0_I_MSK 0x0000ffff
+#define RG_MTX_LEN_UPPER_TH_0_SFT 16
+#define RG_MTX_LEN_UPPER_TH_0_HI 31
+#define RG_MTX_LEN_UPPER_TH_0_SZ 16
+#define RG_MTX_LEN_LOWER_TH_1_MSK 0x0000ffff
+#define RG_MTX_LEN_LOWER_TH_1_I_MSK 0xffff0000
+#define RG_MTX_LEN_LOWER_TH_1_SFT 0
+#define RG_MTX_LEN_LOWER_TH_1_HI 15
+#define RG_MTX_LEN_LOWER_TH_1_SZ 16
+#define RG_MTX_LEN_UPPER_TH_1_MSK 0xffff0000
+#define RG_MTX_LEN_UPPER_TH_1_I_MSK 0x0000ffff
+#define RG_MTX_LEN_UPPER_TH_1_SFT 16
+#define RG_MTX_LEN_UPPER_TH_1_HI 31
+#define RG_MTX_LEN_UPPER_TH_1_SZ 16
+#define RG_MRX_LEN_LOWER_TH_0_MSK 0x0000ffff
+#define RG_MRX_LEN_LOWER_TH_0_I_MSK 0xffff0000
+#define RG_MRX_LEN_LOWER_TH_0_SFT 0
+#define RG_MRX_LEN_LOWER_TH_0_HI 15
+#define RG_MRX_LEN_LOWER_TH_0_SZ 16
+#define RG_MRX_LEN_UPPER_TH_0_MSK 0xffff0000
+#define RG_MRX_LEN_UPPER_TH_0_I_MSK 0x0000ffff
+#define RG_MRX_LEN_UPPER_TH_0_SFT 16
+#define RG_MRX_LEN_UPPER_TH_0_HI 31
+#define RG_MRX_LEN_UPPER_TH_0_SZ 16
+#define RG_MRX_LEN_LOWER_TH_1_MSK 0x0000ffff
+#define RG_MRX_LEN_LOWER_TH_1_I_MSK 0xffff0000
+#define RG_MRX_LEN_LOWER_TH_1_SFT 0
+#define RG_MRX_LEN_LOWER_TH_1_HI 15
+#define RG_MRX_LEN_LOWER_TH_1_SZ 16
+#define RG_MRX_LEN_UPPER_TH_1_MSK 0xffff0000
+#define RG_MRX_LEN_UPPER_TH_1_I_MSK 0x0000ffff
+#define RG_MRX_LEN_UPPER_TH_1_SFT 16
+#define RG_MRX_LEN_UPPER_TH_1_HI 31
+#define RG_MRX_LEN_UPPER_TH_1_SZ 16
+#define RO_MTX_LEN_CNT_1_MSK 0x0000ffff
+#define RO_MTX_LEN_CNT_1_I_MSK 0xffff0000
+#define RO_MTX_LEN_CNT_1_SFT 0
+#define RO_MTX_LEN_CNT_1_HI 15
+#define RO_MTX_LEN_CNT_1_SZ 16
+#define RO_MTX_LEN_CNT_0_MSK 0xffff0000
+#define RO_MTX_LEN_CNT_0_I_MSK 0x0000ffff
+#define RO_MTX_LEN_CNT_0_SFT 16
+#define RO_MTX_LEN_CNT_0_HI 31
+#define RO_MTX_LEN_CNT_0_SZ 16
+#define RO_MRX_LEN_CNT_1_MSK 0x0000ffff
+#define RO_MRX_LEN_CNT_1_I_MSK 0xffff0000
+#define RO_MRX_LEN_CNT_1_SFT 0
+#define RO_MRX_LEN_CNT_1_HI 15
+#define RO_MRX_LEN_CNT_1_SZ 16
+#define RO_MRX_LEN_CNT_0_MSK 0xffff0000
+#define RO_MRX_LEN_CNT_0_I_MSK 0x0000ffff
+#define RO_MRX_LEN_CNT_0_SFT 16
+#define RO_MRX_LEN_CNT_0_HI 31
+#define RO_MRX_LEN_CNT_0_SZ 16
+#define RG_MRX_TYPE_MSK 0x000000ff
+#define RG_MRX_TYPE_I_MSK 0xffffff00
+#define RG_MRX_TYPE_SFT 0
+#define RG_MRX_TYPE_HI 7
+#define RG_MRX_TYPE_SZ 8
+#define RG_MRX_TYPE_CNT_LMT_MSK 0x00001f00
+#define RG_MRX_TYPE_CNT_LMT_I_MSK 0xffffe0ff
+#define RG_MRX_TYPE_CNT_LMT_SFT 8
+#define RG_MRX_TYPE_CNT_LMT_HI 12
+#define RG_MRX_TYPE_CNT_LMT_SZ 5
+#define RG_MTX_TYPE_MSK 0x00ff0000
+#define RG_MTX_TYPE_I_MSK 0xff00ffff
+#define RG_MTX_TYPE_SFT 16
+#define RG_MTX_TYPE_HI 23
+#define RG_MTX_TYPE_SZ 8
+#define RG_MTX_TYPE_CNT_LMT_MSK 0x1f000000
+#define RG_MTX_TYPE_CNT_LMT_I_MSK 0xe0ffffff
+#define RG_MTX_TYPE_CNT_LMT_SFT 24
+#define RG_MTX_TYPE_CNT_LMT_HI 28
+#define RG_MTX_TYPE_CNT_LMT_SZ 5
+#define RO_MRX_TYPE_CNT_MSK 0x0000ffff
+#define RO_MRX_TYPE_CNT_I_MSK 0xffff0000
+#define RO_MRX_TYPE_CNT_SFT 0
+#define RO_MRX_TYPE_CNT_HI 15
+#define RO_MRX_TYPE_CNT_SZ 16
+#define RO_MTX_TYPE_CNT_MSK 0xffff0000
+#define RO_MTX_TYPE_CNT_I_MSK 0x0000ffff
+#define RO_MTX_TYPE_CNT_SFT 16
+#define RO_MTX_TYPE_CNT_HI 31
+#define RO_MTX_TYPE_CNT_SZ 16
+#define RG_ACI_POINT_CNT_LMT_11GN_HT40_MSK 0x000000ff
+#define RG_ACI_POINT_CNT_LMT_11GN_HT40_I_MSK 0xffffff00
+#define RG_ACI_POINT_CNT_LMT_11GN_HT40_SFT 0
+#define RG_ACI_POINT_CNT_LMT_11GN_HT40_HI 7
+#define RG_ACI_POINT_CNT_LMT_11GN_HT40_SZ 8
+#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_HT40_MSK 0x00000300
+#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_HT40_I_MSK 0xfffffcff
+#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_HT40_SFT 8
+#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_HT40_HI 9
+#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_HT40_SZ 2
+#define RG_ACI_DAGC_PWR_SEL_11GN_HT40_MSK 0x00001000
+#define RG_ACI_DAGC_PWR_SEL_11GN_HT40_I_MSK 0xffffefff
+#define RG_ACI_DAGC_PWR_SEL_11GN_HT40_SFT 12
+#define RG_ACI_DAGC_PWR_SEL_11GN_HT40_HI 12
+#define RG_ACI_DAGC_PWR_SEL_11GN_HT40_SZ 1
+#define RG_ACI_DAGC_TARGET_11GN_HT40_MSK 0x0000007f
+#define RG_ACI_DAGC_TARGET_11GN_HT40_I_MSK 0xffffff80
+#define RG_ACI_DAGC_TARGET_11GN_HT40_SFT 0
+#define RG_ACI_DAGC_TARGET_11GN_HT40_HI 6
+#define RG_ACI_DAGC_TARGET_11GN_HT40_SZ 7
+#define RG_ACI_GAIN_SET_11GN_HT40_MSK 0x01ff0000
+#define RG_ACI_GAIN_SET_11GN_HT40_I_MSK 0xfe00ffff
+#define RG_ACI_GAIN_SET_11GN_HT40_SFT 16
+#define RG_ACI_GAIN_SET_11GN_HT40_HI 24
+#define RG_ACI_GAIN_SET_11GN_HT40_SZ 9
+#define RG_ACI_GAIN_OW_11GN_HT40_MSK 0x80000000
+#define RG_ACI_GAIN_OW_11GN_HT40_I_MSK 0x7fffffff
+#define RG_ACI_GAIN_OW_11GN_HT40_SFT 31
+#define RG_ACI_GAIN_OW_11GN_HT40_HI 31
+#define RG_ACI_GAIN_OW_11GN_HT40_SZ 1
+#define RG_ACI_GAIN_INI_11GN_HT40_MSK 0x000001ff
+#define RG_ACI_GAIN_INI_11GN_HT40_I_MSK 0xfffffe00
+#define RG_ACI_GAIN_INI_11GN_HT40_SFT 0
+#define RG_ACI_GAIN_INI_11GN_HT40_HI 8
+#define RG_ACI_GAIN_INI_11GN_HT40_SZ 9
+#define RG_ACI_GAIN_INI_11GN_HT20_MSK 0x01ff0000
+#define RG_ACI_GAIN_INI_11GN_HT20_I_MSK 0xfe00ffff
+#define RG_ACI_GAIN_INI_11GN_HT20_SFT 16
+#define RG_ACI_GAIN_INI_11GN_HT20_HI 24
+#define RG_ACI_GAIN_INI_11GN_HT20_SZ 9
+#define RG_MAC_PKT_MODE_MSK 0x00000001
+#define RG_MAC_PKT_MODE_I_MSK 0xfffffffe
+#define RG_MAC_PKT_MODE_SFT 0
+#define RG_MAC_PKT_MODE_HI 0
+#define RG_MAC_PKT_MODE_SZ 1
+#define RG_MAC_PKT_AGGREGATE_MSK 0x00000002
+#define RG_MAC_PKT_AGGREGATE_I_MSK 0xfffffffd
+#define RG_MAC_PKT_AGGREGATE_SFT 1
+#define RG_MAC_PKT_AGGREGATE_HI 1
+#define RG_MAC_PKT_AGGREGATE_SZ 1
+#define RG_MAC_PKT_ADDR4_ON_MSK 0x00000010
+#define RG_MAC_PKT_ADDR4_ON_I_MSK 0xffffffef
+#define RG_MAC_PKT_ADDR4_ON_SFT 4
+#define RG_MAC_PKT_ADDR4_ON_HI 4
+#define RG_MAC_PKT_ADDR4_ON_SZ 1
+#define RG_MAC_PKT_SEQ_ON_MSK 0x00000020
+#define RG_MAC_PKT_SEQ_ON_I_MSK 0xffffffdf
+#define RG_MAC_PKT_SEQ_ON_SFT 5
+#define RG_MAC_PKT_SEQ_ON_HI 5
+#define RG_MAC_PKT_SEQ_ON_SZ 1
+#define RG_MAC_PKT_ADDR3_ON_MSK 0x00000040
+#define RG_MAC_PKT_ADDR3_ON_I_MSK 0xffffffbf
+#define RG_MAC_PKT_ADDR3_ON_SFT 6
+#define RG_MAC_PKT_ADDR3_ON_HI 6
+#define RG_MAC_PKT_ADDR3_ON_SZ 1
+#define RG_MAC_PKT_ADDR2_ON_MSK 0x00000080
+#define RG_MAC_PKT_ADDR2_ON_I_MSK 0xffffff7f
+#define RG_MAC_PKT_ADDR2_ON_SFT 7
+#define RG_MAC_PKT_ADDR2_ON_HI 7
+#define RG_MAC_PKT_ADDR2_ON_SZ 1
+#define RG_MAC_PKT_AGGREGATE_NUM_MSK 0x00000f00
+#define RG_MAC_PKT_AGGREGATE_NUM_I_MSK 0xfffff0ff
+#define RG_MAC_PKT_AGGREGATE_NUM_SFT 8
+#define RG_MAC_PKT_AGGREGATE_NUM_HI 11
+#define RG_MAC_PKT_AGGREGATE_NUM_SZ 4
+#define RG_MAC_PKT_PLD_LENGTH_MSK 0xffff0000
+#define RG_MAC_PKT_PLD_LENGTH_I_MSK 0x0000ffff
+#define RG_MAC_PKT_PLD_LENGTH_SFT 16
+#define RG_MAC_PKT_PLD_LENGTH_HI 31
+#define RG_MAC_PKT_PLD_LENGTH_SZ 16
+#define RG_MAC_PKT_DUR_MSK 0x0000ffff
+#define RG_MAC_PKT_DUR_I_MSK 0xffff0000
+#define RG_MAC_PKT_DUR_SFT 0
+#define RG_MAC_PKT_DUR_HI 15
+#define RG_MAC_PKT_DUR_SZ 16
+#define RG_MAC_PKT_FC_MSK 0xffff0000
+#define RG_MAC_PKT_FC_I_MSK 0x0000ffff
+#define RG_MAC_PKT_FC_SFT 16
+#define RG_MAC_PKT_FC_HI 31
+#define RG_MAC_PKT_FC_SZ 16
+#define RG_MAC_PKT_ADDR1_31_0_MSK 0xffffffff
+#define RG_MAC_PKT_ADDR1_31_0_I_MSK 0x00000000
+#define RG_MAC_PKT_ADDR1_31_0_SFT 0
+#define RG_MAC_PKT_ADDR1_31_0_HI 31
+#define RG_MAC_PKT_ADDR1_31_0_SZ 32
+#define RG_MAC_PKT_ADDR1_47_32_MSK 0x0000ffff
+#define RG_MAC_PKT_ADDR1_47_32_I_MSK 0xffff0000
+#define RG_MAC_PKT_ADDR1_47_32_SFT 0
+#define RG_MAC_PKT_ADDR1_47_32_HI 15
+#define RG_MAC_PKT_ADDR1_47_32_SZ 16
+#define RG_MAC_PKT_ADDR2_31_0_MSK 0xffffffff
+#define RG_MAC_PKT_ADDR2_31_0_I_MSK 0x00000000
+#define RG_MAC_PKT_ADDR2_31_0_SFT 0
+#define RG_MAC_PKT_ADDR2_31_0_HI 31
+#define RG_MAC_PKT_ADDR2_31_0_SZ 32
+#define RG_MAC_PKT_ADDR2_47_32_MSK 0x0000ffff
+#define RG_MAC_PKT_ADDR2_47_32_I_MSK 0xffff0000
+#define RG_MAC_PKT_ADDR2_47_32_SFT 0
+#define RG_MAC_PKT_ADDR2_47_32_HI 15
+#define RG_MAC_PKT_ADDR2_47_32_SZ 16
+#define RG_MAC_PKT_ADDR3_31_0_MSK 0xffffffff
+#define RG_MAC_PKT_ADDR3_31_0_I_MSK 0x00000000
+#define RG_MAC_PKT_ADDR3_31_0_SFT 0
+#define RG_MAC_PKT_ADDR3_31_0_HI 31
+#define RG_MAC_PKT_ADDR3_31_0_SZ 32
+#define RG_MAC_PKT_ADDR3_47_32_MSK 0x0000ffff
+#define RG_MAC_PKT_ADDR3_47_32_I_MSK 0xffff0000
+#define RG_MAC_PKT_ADDR3_47_32_SFT 0
+#define RG_MAC_PKT_ADDR3_47_32_HI 15
+#define RG_MAC_PKT_ADDR3_47_32_SZ 16
+#define RG_MAC_PKT_SEQ_MSK 0x0000ffff
+#define RG_MAC_PKT_SEQ_I_MSK 0xffff0000
+#define RG_MAC_PKT_SEQ_SFT 0
+#define RG_MAC_PKT_SEQ_HI 15
+#define RG_MAC_PKT_SEQ_SZ 16
+#define RG_MAC_PKT_ADDR4_31_0_MSK 0xffffffff
+#define RG_MAC_PKT_ADDR4_31_0_I_MSK 0x00000000
+#define RG_MAC_PKT_ADDR4_31_0_SFT 0
+#define RG_MAC_PKT_ADDR4_31_0_HI 31
+#define RG_MAC_PKT_ADDR4_31_0_SZ 32
+#define RG_MAC_PKT_ADDR4_47_32_MSK 0x0000ffff
+#define RG_MAC_PKT_ADDR4_47_32_I_MSK 0xffff0000
+#define RG_MAC_PKT_ADDR4_47_32_SFT 0
+#define RG_MAC_PKT_ADDR4_47_32_HI 15
+#define RG_MAC_PKT_ADDR4_47_32_SZ 16
+#define RG_BB_SCALE_BARKER_CCK_MSK 0x000000ff
+#define RG_BB_SCALE_BARKER_CCK_I_MSK 0xffffff00
+#define RG_BB_SCALE_BARKER_CCK_SFT 0
+#define RG_BB_SCALE_BARKER_CCK_HI 7
+#define RG_BB_SCALE_BARKER_CCK_SZ 8
+#define RG_BB_SCALE_MAN_EN_MSK 0x00010000
+#define RG_BB_SCALE_MAN_EN_I_MSK 0xfffeffff
+#define RG_BB_SCALE_MAN_EN_SFT 16
+#define RG_BB_SCALE_MAN_EN_HI 16
+#define RG_BB_SCALE_MAN_EN_SZ 1
+#define RG_BB_SCALE_LEGACY_64QAM_MSK 0x000000ff
+#define RG_BB_SCALE_LEGACY_64QAM_I_MSK 0xffffff00
+#define RG_BB_SCALE_LEGACY_64QAM_SFT 0
+#define RG_BB_SCALE_LEGACY_64QAM_HI 7
+#define RG_BB_SCALE_LEGACY_64QAM_SZ 8
+#define RG_BB_SCALE_LEGACY_16QAM_MSK 0x0000ff00
+#define RG_BB_SCALE_LEGACY_16QAM_I_MSK 0xffff00ff
+#define RG_BB_SCALE_LEGACY_16QAM_SFT 8
+#define RG_BB_SCALE_LEGACY_16QAM_HI 15
+#define RG_BB_SCALE_LEGACY_16QAM_SZ 8
+#define RG_BB_SCALE_LEGACY_QPSK_MSK 0x00ff0000
+#define RG_BB_SCALE_LEGACY_QPSK_I_MSK 0xff00ffff
+#define RG_BB_SCALE_LEGACY_QPSK_SFT 16
+#define RG_BB_SCALE_LEGACY_QPSK_HI 23
+#define RG_BB_SCALE_LEGACY_QPSK_SZ 8
+#define RG_BB_SCALE_LEGACY_BPSK_MSK 0xff000000
+#define RG_BB_SCALE_LEGACY_BPSK_I_MSK 0x00ffffff
+#define RG_BB_SCALE_LEGACY_BPSK_SFT 24
+#define RG_BB_SCALE_LEGACY_BPSK_HI 31
+#define RG_BB_SCALE_LEGACY_BPSK_SZ 8
+#define RG_BB_SCALE_HT20_64QAM_MSK 0x000000ff
+#define RG_BB_SCALE_HT20_64QAM_I_MSK 0xffffff00
+#define RG_BB_SCALE_HT20_64QAM_SFT 0
+#define RG_BB_SCALE_HT20_64QAM_HI 7
+#define RG_BB_SCALE_HT20_64QAM_SZ 8
+#define RG_BB_SCALE_HT20_16QAM_MSK 0x0000ff00
+#define RG_BB_SCALE_HT20_16QAM_I_MSK 0xffff00ff
+#define RG_BB_SCALE_HT20_16QAM_SFT 8
+#define RG_BB_SCALE_HT20_16QAM_HI 15
+#define RG_BB_SCALE_HT20_16QAM_SZ 8
+#define RG_BB_SCALE_HT20_QPSK_MSK 0x00ff0000
+#define RG_BB_SCALE_HT20_QPSK_I_MSK 0xff00ffff
+#define RG_BB_SCALE_HT20_QPSK_SFT 16
+#define RG_BB_SCALE_HT20_QPSK_HI 23
+#define RG_BB_SCALE_HT20_QPSK_SZ 8
+#define RG_BB_SCALE_HT20_BPSK_MSK 0xff000000
+#define RG_BB_SCALE_HT20_BPSK_I_MSK 0x00ffffff
+#define RG_BB_SCALE_HT20_BPSK_SFT 24
+#define RG_BB_SCALE_HT20_BPSK_HI 31
+#define RG_BB_SCALE_HT20_BPSK_SZ 8
+#define RG_BB_SCALE_HT40_64QAM_MSK 0x000000ff
+#define RG_BB_SCALE_HT40_64QAM_I_MSK 0xffffff00
+#define RG_BB_SCALE_HT40_64QAM_SFT 0
+#define RG_BB_SCALE_HT40_64QAM_HI 7
+#define RG_BB_SCALE_HT40_64QAM_SZ 8
+#define RG_BB_SCALE_HT40_16QAM_MSK 0x0000ff00
+#define RG_BB_SCALE_HT40_16QAM_I_MSK 0xffff00ff
+#define RG_BB_SCALE_HT40_16QAM_SFT 8
+#define RG_BB_SCALE_HT40_16QAM_HI 15
+#define RG_BB_SCALE_HT40_16QAM_SZ 8
+#define RG_BB_SCALE_HT40_QPSK_MSK 0x00ff0000
+#define RG_BB_SCALE_HT40_QPSK_I_MSK 0xff00ffff
+#define RG_BB_SCALE_HT40_QPSK_SFT 16
+#define RG_BB_SCALE_HT40_QPSK_HI 23
+#define RG_BB_SCALE_HT40_QPSK_SZ 8
+#define RG_BB_SCALE_HT40_BPSK_MSK 0xff000000
+#define RG_BB_SCALE_HT40_BPSK_I_MSK 0x00ffffff
+#define RG_BB_SCALE_HT40_BPSK_SFT 24
+#define RG_BB_SCALE_HT40_BPSK_HI 31
+#define RG_BB_SCALE_HT40_BPSK_SZ 8
+#define RG_RF_PWR_BARKER_CCK_MSK 0x0000007f
+#define RG_RF_PWR_BARKER_CCK_I_MSK 0xffffff80
+#define RG_RF_PWR_BARKER_CCK_SFT 0
+#define RG_RF_PWR_BARKER_CCK_HI 6
+#define RG_RF_PWR_BARKER_CCK_SZ 7
+#define RG_RF_PWR_MAN_EN_MSK 0x00010000
+#define RG_RF_PWR_MAN_EN_I_MSK 0xfffeffff
+#define RG_RF_PWR_MAN_EN_SFT 16
+#define RG_RF_PWR_MAN_EN_HI 16
+#define RG_RF_PWR_MAN_EN_SZ 1
+#define RG_RF_PWR_LEGACY_64QAM_MSK 0x0000007f
+#define RG_RF_PWR_LEGACY_64QAM_I_MSK 0xffffff80
+#define RG_RF_PWR_LEGACY_64QAM_SFT 0
+#define RG_RF_PWR_LEGACY_64QAM_HI 6
+#define RG_RF_PWR_LEGACY_64QAM_SZ 7
+#define RG_RF_PWR_LEGACY_16QAM_MSK 0x00007f00
+#define RG_RF_PWR_LEGACY_16QAM_I_MSK 0xffff80ff
+#define RG_RF_PWR_LEGACY_16QAM_SFT 8
+#define RG_RF_PWR_LEGACY_16QAM_HI 14
+#define RG_RF_PWR_LEGACY_16QAM_SZ 7
+#define RG_RF_PWR_LEGACY_QPSK_MSK 0x007f0000
+#define RG_RF_PWR_LEGACY_QPSK_I_MSK 0xff80ffff
+#define RG_RF_PWR_LEGACY_QPSK_SFT 16
+#define RG_RF_PWR_LEGACY_QPSK_HI 22
+#define RG_RF_PWR_LEGACY_QPSK_SZ 7
+#define RG_RF_PWR_LEGACY_BPSK_MSK 0x7f000000
+#define RG_RF_PWR_LEGACY_BPSK_I_MSK 0x80ffffff
+#define RG_RF_PWR_LEGACY_BPSK_SFT 24
+#define RG_RF_PWR_LEGACY_BPSK_HI 30
+#define RG_RF_PWR_LEGACY_BPSK_SZ 7
+#define RG_RF_PWR_HT20_64QAM_MSK 0x0000007f
+#define RG_RF_PWR_HT20_64QAM_I_MSK 0xffffff80
+#define RG_RF_PWR_HT20_64QAM_SFT 0
+#define RG_RF_PWR_HT20_64QAM_HI 6
+#define RG_RF_PWR_HT20_64QAM_SZ 7
+#define RG_RF_PWR_HT20_16QAM_MSK 0x00007f00
+#define RG_RF_PWR_HT20_16QAM_I_MSK 0xffff80ff
+#define RG_RF_PWR_HT20_16QAM_SFT 8
+#define RG_RF_PWR_HT20_16QAM_HI 14
+#define RG_RF_PWR_HT20_16QAM_SZ 7
+#define RG_RF_PWR_HT20_QPSK_MSK 0x007f0000
+#define RG_RF_PWR_HT20_QPSK_I_MSK 0xff80ffff
+#define RG_RF_PWR_HT20_QPSK_SFT 16
+#define RG_RF_PWR_HT20_QPSK_HI 22
+#define RG_RF_PWR_HT20_QPSK_SZ 7
+#define RG_RF_PWR_HT20_BPSK_MSK 0x7f000000
+#define RG_RF_PWR_HT20_BPSK_I_MSK 0x80ffffff
+#define RG_RF_PWR_HT20_BPSK_SFT 24
+#define RG_RF_PWR_HT20_BPSK_HI 30
+#define RG_RF_PWR_HT20_BPSK_SZ 7
+#define RG_RF_PWR_HT40_64QAM_MSK 0x0000007f
+#define RG_RF_PWR_HT40_64QAM_I_MSK 0xffffff80
+#define RG_RF_PWR_HT40_64QAM_SFT 0
+#define RG_RF_PWR_HT40_64QAM_HI 6
+#define RG_RF_PWR_HT40_64QAM_SZ 7
+#define RG_RF_PWR_HT40_16QAM_MSK 0x00007f00
+#define RG_RF_PWR_HT40_16QAM_I_MSK 0xffff80ff
+#define RG_RF_PWR_HT40_16QAM_SFT 8
+#define RG_RF_PWR_HT40_16QAM_HI 14
+#define RG_RF_PWR_HT40_16QAM_SZ 7
+#define RG_RF_PWR_HT40_QPSK_MSK 0x007f0000
+#define RG_RF_PWR_HT40_QPSK_I_MSK 0xff80ffff
+#define RG_RF_PWR_HT40_QPSK_SFT 16
+#define RG_RF_PWR_HT40_QPSK_HI 22
+#define RG_RF_PWR_HT40_QPSK_SZ 7
+#define RG_RF_PWR_HT40_BPSK_MSK 0x7f000000
+#define RG_RF_PWR_HT40_BPSK_I_MSK 0x80ffffff
+#define RG_RF_PWR_HT40_BPSK_SFT 24
+#define RG_RF_PWR_HT40_BPSK_HI 30
+#define RG_RF_PWR_HT40_BPSK_SZ 7
+#define RG_RX_MONITOR_ON_MSK 0x00000001
+#define RG_RX_MONITOR_ON_I_MSK 0xfffffffe
+#define RG_RX_MONITOR_ON_SFT 0
+#define RG_RX_MONITOR_ON_HI 0
+#define RG_RX_MONITOR_ON_SZ 1
+#define RG_RX_PKT_ADDR3_ON_MSK 0x00000002
+#define RG_RX_PKT_ADDR3_ON_I_MSK 0xfffffffd
+#define RG_RX_PKT_ADDR3_ON_SFT 1
+#define RG_RX_PKT_ADDR3_ON_HI 1
+#define RG_RX_PKT_ADDR3_ON_SZ 1
+#define RG_RX_PKT_ADDR2_ON_MSK 0x00000004
+#define RG_RX_PKT_ADDR2_ON_I_MSK 0xfffffffb
+#define RG_RX_PKT_ADDR2_ON_SFT 2
+#define RG_RX_PKT_ADDR2_ON_HI 2
+#define RG_RX_PKT_ADDR2_ON_SZ 1
+#define RG_RX_PKT_ADDR1_ON_MSK 0x00000008
+#define RG_RX_PKT_ADDR1_ON_I_MSK 0xfffffff7
+#define RG_RX_PKT_ADDR1_ON_SFT 3
+#define RG_RX_PKT_ADDR1_ON_HI 3
+#define RG_RX_PKT_ADDR1_ON_SZ 1
+#define RG_RX_BEACON_TU_MSK 0x00003ff0
+#define RG_RX_BEACON_TU_I_MSK 0xffffc00f
+#define RG_RX_BEACON_TU_SFT 4
+#define RG_RX_BEACON_TU_HI 13
+#define RG_RX_BEACON_TU_SZ 10
+#define RG_RX_PKT_TIMER_LMT_MSK 0xffff0000
+#define RG_RX_PKT_TIMER_LMT_I_MSK 0x0000ffff
+#define RG_RX_PKT_TIMER_LMT_SFT 16
+#define RG_RX_PKT_TIMER_LMT_HI 31
+#define RG_RX_PKT_TIMER_LMT_SZ 16
+#define RG_RX_BEACON_LOSS_CNT_LMT_MSK 0x000000ff
+#define RG_RX_BEACON_LOSS_CNT_LMT_I_MSK 0xffffff00
+#define RG_RX_BEACON_LOSS_CNT_LMT_SFT 0
+#define RG_RX_BEACON_LOSS_CNT_LMT_HI 7
+#define RG_RX_BEACON_LOSS_CNT_LMT_SZ 8
+#define RG_RX_BEACON_CRC_BYPASS_MSK 0x00000100
+#define RG_RX_BEACON_CRC_BYPASS_I_MSK 0xfffffeff
+#define RG_RX_BEACON_CRC_BYPASS_SFT 8
+#define RG_RX_BEACON_CRC_BYPASS_HI 8
+#define RG_RX_BEACON_CRC_BYPASS_SZ 1
+#define RG_RX_BEACON_INTERVAL_MSK 0xffff0000
+#define RG_RX_BEACON_INTERVAL_I_MSK 0x0000ffff
+#define RG_RX_BEACON_INTERVAL_SFT 16
+#define RG_RX_BEACON_INTERVAL_HI 31
+#define RG_RX_BEACON_INTERVAL_SZ 16
+#define RG_RX_PKT_FC_MSK 0xffff0000
+#define RG_RX_PKT_FC_I_MSK 0x0000ffff
+#define RG_RX_PKT_FC_SFT 16
+#define RG_RX_PKT_FC_HI 31
+#define RG_RX_PKT_FC_SZ 16
+#define RG_RX_PKT_ADDR1_31_0_MSK 0xffffffff
+#define RG_RX_PKT_ADDR1_31_0_I_MSK 0x00000000
+#define RG_RX_PKT_ADDR1_31_0_SFT 0
+#define RG_RX_PKT_ADDR1_31_0_HI 31
+#define RG_RX_PKT_ADDR1_31_0_SZ 32
+#define RG_RX_PKT_ADDR1_47_32_MSK 0x0000ffff
+#define RG_RX_PKT_ADDR1_47_32_I_MSK 0xffff0000
+#define RG_RX_PKT_ADDR1_47_32_SFT 0
+#define RG_RX_PKT_ADDR1_47_32_HI 15
+#define RG_RX_PKT_ADDR1_47_32_SZ 16
+#define RG_RX_PKT_ADDR2_31_0_MSK 0xffffffff
+#define RG_RX_PKT_ADDR2_31_0_I_MSK 0x00000000
+#define RG_RX_PKT_ADDR2_31_0_SFT 0
+#define RG_RX_PKT_ADDR2_31_0_HI 31
+#define RG_RX_PKT_ADDR2_31_0_SZ 32
+#define RG_RX_PKT_ADDR2_47_32_MSK 0x0000ffff
+#define RG_RX_PKT_ADDR2_47_32_I_MSK 0xffff0000
+#define RG_RX_PKT_ADDR2_47_32_SFT 0
+#define RG_RX_PKT_ADDR2_47_32_HI 15
+#define RG_RX_PKT_ADDR2_47_32_SZ 16
+#define RG_RX_PKT_ADDR3_31_0_MSK 0xffffffff
+#define RG_RX_PKT_ADDR3_31_0_I_MSK 0x00000000
+#define RG_RX_PKT_ADDR3_31_0_SFT 0
+#define RG_RX_PKT_ADDR3_31_0_HI 31
+#define RG_RX_PKT_ADDR3_31_0_SZ 32
+#define RG_RX_PKT_ADDR3_47_32_MSK 0x0000ffff
+#define RG_RX_PKT_ADDR3_47_32_I_MSK 0xffff0000
+#define RG_RX_PKT_ADDR3_47_32_SFT 0
+#define RG_RX_PKT_ADDR3_47_32_HI 15
+#define RG_RX_PKT_ADDR3_47_32_SZ 16
+#define RO_INTRP_RX_LOSS_MSK 0x00000001
+#define RO_INTRP_RX_LOSS_I_MSK 0xfffffffe
+#define RO_INTRP_RX_LOSS_SFT 0
+#define RO_INTRP_RX_LOSS_HI 0
+#define RO_INTRP_RX_LOSS_SZ 1
+#define RO_RX_PKT_TIMER_MSK 0xffff0000
+#define RO_RX_PKT_TIMER_I_MSK 0x0000ffff
+#define RO_RX_PKT_TIMER_SFT 16
+#define RO_RX_PKT_TIMER_HI 31
+#define RO_RX_PKT_TIMER_SZ 16
+#define RO_INTRP_RX_BEACON_LOSS_MSK 0x00000001
+#define RO_INTRP_RX_BEACON_LOSS_I_MSK 0xfffffffe
+#define RO_INTRP_RX_BEACON_LOSS_SFT 0
+#define RO_INTRP_RX_BEACON_LOSS_HI 0
+#define RO_INTRP_RX_BEACON_LOSS_SZ 1
+#define RO_RX_BEACON_LOSS_CNT_MSK 0x0000ff00
+#define RO_RX_BEACON_LOSS_CNT_I_MSK 0xffff00ff
+#define RO_RX_BEACON_LOSS_CNT_SFT 8
+#define RO_RX_BEACON_LOSS_CNT_HI 15
+#define RO_RX_BEACON_LOSS_CNT_SZ 8
+#define RO_RX_BEACON_CNT_MSK 0xffff0000
+#define RO_RX_BEACON_CNT_I_MSK 0x0000ffff
+#define RO_RX_BEACON_CNT_SFT 16
+#define RO_RX_BEACON_CNT_HI 31
+#define RO_RX_BEACON_CNT_SZ 16
+#define RG_RX_FIFO_FULL_CNT_EN_MSK 0x00000001
+#define RG_RX_FIFO_FULL_CNT_EN_I_MSK 0xfffffffe
+#define RG_RX_FIFO_FULL_CNT_EN_SFT 0
+#define RG_RX_FIFO_FULL_CNT_EN_HI 0
+#define RG_RX_FIFO_FULL_CNT_EN_SZ 1
+#define RG_TX_FIFO_EMPTY_CNT_EN_MSK 0x00000010
+#define RG_TX_FIFO_EMPTY_CNT_EN_I_MSK 0xffffffef
+#define RG_TX_FIFO_EMPTY_CNT_EN_SFT 4
+#define RG_TX_FIFO_EMPTY_CNT_EN_HI 4
+#define RG_TX_FIFO_EMPTY_CNT_EN_SZ 1
+#define RO_RX_FIFO_FULL_CNT_MSK 0x0000ffff
+#define RO_RX_FIFO_FULL_CNT_I_MSK 0xffff0000
+#define RO_RX_FIFO_FULL_CNT_SFT 0
+#define RO_RX_FIFO_FULL_CNT_HI 15
+#define RO_RX_FIFO_FULL_CNT_SZ 16
+#define RO_TX_FIFO_EMPTY_CNT_MSK 0xffff0000
+#define RO_TX_FIFO_EMPTY_CNT_I_MSK 0x0000ffff
+#define RO_TX_FIFO_EMPTY_CNT_SFT 16
+#define RO_TX_FIFO_EMPTY_CNT_HI 31
+#define RO_TX_FIFO_EMPTY_CNT_SZ 16
+#define RG_BIST_EN_RX_FFT_MSK 0x00000001
+#define RG_BIST_EN_RX_FFT_I_MSK 0xfffffffe
+#define RG_BIST_EN_RX_FFT_SFT 0
+#define RG_BIST_EN_RX_FFT_HI 0
+#define RG_BIST_EN_RX_FFT_SZ 1
+#define RG_BIST_MODE_RX_FFT_MSK 0x00000010
+#define RG_BIST_MODE_RX_FFT_I_MSK 0xffffffef
+#define RG_BIST_MODE_RX_FFT_SFT 4
+#define RG_BIST_MODE_RX_FFT_HI 4
+#define RG_BIST_MODE_RX_FFT_SZ 1
+#define RO_BIST_DONE_RX_FFT_1_MSK 0x00010000
+#define RO_BIST_DONE_RX_FFT_1_I_MSK 0xfffeffff
+#define RO_BIST_DONE_RX_FFT_1_SFT 16
+#define RO_BIST_DONE_RX_FFT_1_HI 16
+#define RO_BIST_DONE_RX_FFT_1_SZ 1
+#define RO_BIST_FAIL_RX_FFT_1_MSK 0x00020000
+#define RO_BIST_FAIL_RX_FFT_1_I_MSK 0xfffdffff
+#define RO_BIST_FAIL_RX_FFT_1_SFT 17
+#define RO_BIST_FAIL_RX_FFT_1_HI 17
+#define RO_BIST_FAIL_RX_FFT_1_SZ 1
+#define RO_BIST_DONE_RX_FFT_0_MSK 0x00100000
+#define RO_BIST_DONE_RX_FFT_0_I_MSK 0xffefffff
+#define RO_BIST_DONE_RX_FFT_0_SFT 20
+#define RO_BIST_DONE_RX_FFT_0_HI 20
+#define RO_BIST_DONE_RX_FFT_0_SZ 1
+#define RO_BIST_FAIL_RX_FFT_0_MSK 0x00200000
+#define RO_BIST_FAIL_RX_FFT_0_I_MSK 0xffdfffff
+#define RO_BIST_FAIL_RX_FFT_0_SFT 21
+#define RO_BIST_FAIL_RX_FFT_0_HI 21
+#define RO_BIST_FAIL_RX_FFT_0_SZ 1
+#define RG_AUDIO_CLK_EN_MSK 0x00000001
+#define RG_AUDIO_CLK_EN_I_MSK 0xfffffffe
+#define RG_AUDIO_CLK_EN_SFT 0
+#define RG_AUDIO_CLK_EN_HI 0
+#define RG_AUDIO_CLK_EN_SZ 1
+#define RG_AUDIO_CLK_SEL_MSK 0x00000002
+#define RG_AUDIO_CLK_SEL_I_MSK 0xfffffffd
+#define RG_AUDIO_CLK_SEL_SFT 1
+#define RG_AUDIO_CLK_SEL_HI 1
+#define RG_AUDIO_CLK_SEL_SZ 1
+#define RO_CSTATE_PKT_MSK 0x00000003
+#define RO_CSTATE_PKT_I_MSK 0xfffffffc
+#define RO_CSTATE_PKT_SFT 0
+#define RO_CSTATE_PKT_HI 1
+#define RO_CSTATE_PKT_SZ 2
+#define RO_MRX_RX_EN_MSK 0x00000010
+#define RO_MRX_RX_EN_I_MSK 0xffffffef
+#define RO_MRX_RX_EN_SFT 4
+#define RO_MRX_RX_EN_HI 4
+#define RO_MRX_RX_EN_SZ 1
+#define RO_CSTATE_AGC_MSK 0x00000300
+#define RO_CSTATE_AGC_I_MSK 0xfffffcff
+#define RO_CSTATE_AGC_SFT 8
+#define RO_CSTATE_AGC_HI 9
+#define RO_CSTATE_AGC_SZ 2
+#define RO_AGC_START_80M_MSK 0x00001000
+#define RO_AGC_START_80M_I_MSK 0xffffefff
+#define RO_AGC_START_80M_SFT 12
+#define RO_AGC_START_80M_HI 12
+#define RO_AGC_START_80M_SZ 1
+#define RO_CSTATE_RX_MSK 0x000f0000
+#define RO_CSTATE_RX_I_MSK 0xfff0ffff
+#define RO_CSTATE_RX_SFT 16
+#define RO_CSTATE_RX_HI 19
+#define RO_CSTATE_RX_SZ 4
+#define RO_TX_IP_MSK 0x00100000
+#define RO_TX_IP_I_MSK 0xffefffff
+#define RO_TX_IP_SFT 20
+#define RO_TX_IP_HI 20
+#define RO_TX_IP_SZ 1
+#define RO_CSTATE_TX_MSK 0x0f000000
+#define RO_CSTATE_TX_I_MSK 0xf0ffffff
+#define RO_CSTATE_TX_SFT 24
+#define RO_CSTATE_TX_HI 27
+#define RO_CSTATE_TX_SZ 4
+#define RO_MAC_PHY_TRX_EN_SYNC_MSK 0x10000000
+#define RO_MAC_PHY_TRX_EN_SYNC_I_MSK 0xefffffff
+#define RO_MAC_PHY_TRX_EN_SYNC_SFT 28
+#define RO_MAC_PHY_TRX_EN_SYNC_HI 28
+#define RO_MAC_PHY_TRX_EN_SYNC_SZ 1
+#define RG_RESERVED_CMM_MSK 0xffffffff
+#define RG_RESERVED_CMM_I_MSK 0x00000000
+#define RG_RESERVED_CMM_SFT 0
+#define RG_RESERVED_CMM_HI 31
+#define RG_RESERVED_CMM_SZ 32
+#define RG_BB_RISE_TIME_11B_TX_MSK 0x000000ff
+#define RG_BB_RISE_TIME_11B_TX_I_MSK 0xffffff00
+#define RG_BB_RISE_TIME_11B_TX_SFT 0
+#define RG_BB_RISE_TIME_11B_TX_HI 7
+#define RG_BB_RISE_TIME_11B_TX_SZ 8
+#define RG_BB_FALL_TIME_11B_TX_MSK 0x0000ff00
+#define RG_BB_FALL_TIME_11B_TX_I_MSK 0xffff00ff
+#define RG_BB_FALL_TIME_11B_TX_SFT 8
+#define RG_BB_FALL_TIME_11B_TX_HI 15
+#define RG_BB_FALL_TIME_11B_TX_SZ 8
+#define RG_BP_SMB_MSK 0x00010000
+#define RG_BP_SMB_I_MSK 0xfffeffff
+#define RG_BP_SMB_SFT 16
+#define RG_BP_SMB_HI 16
+#define RG_BP_SMB_SZ 1
+#define RO_TX_CNT_R_11B_TX_MSK 0xffffffff
+#define RO_TX_CNT_R_11B_TX_I_MSK 0x00000000
+#define RO_TX_CNT_R_11B_TX_SFT 0
+#define RO_TX_CNT_R_11B_TX_HI 31
+#define RO_TX_CNT_R_11B_TX_SZ 32
+#define RG_DEBUG_SEL_11B_TX_MSK 0x0000000f
+#define RG_DEBUG_SEL_11B_TX_I_MSK 0xfffffff0
+#define RG_DEBUG_SEL_11B_TX_SFT 0
+#define RG_DEBUG_SEL_11B_TX_HI 3
+#define RG_DEBUG_SEL_11B_TX_SZ 4
+#define RG_RESERVED_11B_TX_MSK 0xffffffff
+#define RG_RESERVED_11B_TX_I_MSK 0x00000000
+#define RG_RESERVED_11B_TX_SFT 0
+#define RG_RESERVED_11B_TX_HI 31
+#define RG_RESERVED_11B_TX_SZ 32
+#define RG_POS_DES_L_EXT_11B_RX_MSK 0x0000000f
+#define RG_POS_DES_L_EXT_11B_RX_I_MSK 0xfffffff0
+#define RG_POS_DES_L_EXT_11B_RX_SFT 0
+#define RG_POS_DES_L_EXT_11B_RX_HI 3
+#define RG_POS_DES_L_EXT_11B_RX_SZ 4
+#define RG_PRE_DES_DLY_11B_RX_MSK 0x000000f0
+#define RG_PRE_DES_DLY_11B_RX_I_MSK 0xffffff0f
+#define RG_PRE_DES_DLY_11B_RX_SFT 4
+#define RG_PRE_DES_DLY_11B_RX_HI 7
+#define RG_PRE_DES_DLY_11B_RX_SZ 4
+#define RG_CCA_RE_CHK_BIT_CNT_TH_MSK 0x00000f00
+#define RG_CCA_RE_CHK_BIT_CNT_TH_I_MSK 0xfffff0ff
+#define RG_CCA_RE_CHK_BIT_CNT_TH_SFT 8
+#define RG_CCA_RE_CHK_BIT_CNT_TH_HI 11
+#define RG_CCA_RE_CHK_BIT_CNT_TH_SZ 4
+#define RG_CNT_CCA_RE_CHK_LMT_MSK 0x000f0000
+#define RG_CNT_CCA_RE_CHK_LMT_I_MSK 0xfff0ffff
+#define RG_CNT_CCA_RE_CHK_LMT_SFT 16
+#define RG_CNT_CCA_RE_CHK_LMT_HI 19
+#define RG_CNT_CCA_RE_CHK_LMT_SZ 4
+#define RG_BYPASS_DESCRAMBLER_MSK 0x20000000
+#define RG_BYPASS_DESCRAMBLER_I_MSK 0xdfffffff
+#define RG_BYPASS_DESCRAMBLER_SFT 29
+#define RG_BYPASS_DESCRAMBLER_HI 29
+#define RG_BYPASS_DESCRAMBLER_SZ 1
+#define RG_CCA_BIT_CNT_TH_MSK 0x000000f0
+#define RG_CCA_BIT_CNT_TH_I_MSK 0xffffff0f
+#define RG_CCA_BIT_CNT_TH_SFT 4
+#define RG_CCA_BIT_CNT_TH_HI 7
+#define RG_CCA_BIT_CNT_TH_SZ 4
+#define RG_CCA_SCALE_BF_MSK 0x007f0000
+#define RG_CCA_SCALE_BF_I_MSK 0xff80ffff
+#define RG_CCA_SCALE_BF_SFT 16
+#define RG_CCA_SCALE_BF_HI 22
+#define RG_CCA_SCALE_BF_SZ 7
+#define RG_PEAK_IDX_CNT_SEL_MSK 0x30000000
+#define RG_PEAK_IDX_CNT_SEL_I_MSK 0xcfffffff
+#define RG_PEAK_IDX_CNT_SEL_SFT 28
+#define RG_PEAK_IDX_CNT_SEL_HI 29
+#define RG_PEAK_IDX_CNT_SEL_SZ 2
+#define RG_TR_KI_T2_MSK 0x00000007
+#define RG_TR_KI_T2_I_MSK 0xfffffff8
+#define RG_TR_KI_T2_SFT 0
+#define RG_TR_KI_T2_HI 2
+#define RG_TR_KI_T2_SZ 3
+#define RG_TR_KP_T2_MSK 0x00000070
+#define RG_TR_KP_T2_I_MSK 0xffffff8f
+#define RG_TR_KP_T2_SFT 4
+#define RG_TR_KP_T2_HI 6
+#define RG_TR_KP_T2_SZ 3
+#define RG_TR_KI_T1_MSK 0x00000700
+#define RG_TR_KI_T1_I_MSK 0xfffff8ff
+#define RG_TR_KI_T1_SFT 8
+#define RG_TR_KI_T1_HI 10
+#define RG_TR_KI_T1_SZ 3
+#define RG_TR_KP_T1_MSK 0x00007000
+#define RG_TR_KP_T1_I_MSK 0xffff8fff
+#define RG_TR_KP_T1_SFT 12
+#define RG_TR_KP_T1_HI 14
+#define RG_TR_KP_T1_SZ 3
+#define RG_CR_KI_T1_MSK 0x00070000
+#define RG_CR_KI_T1_I_MSK 0xfff8ffff
+#define RG_CR_KI_T1_SFT 16
+#define RG_CR_KI_T1_HI 18
+#define RG_CR_KI_T1_SZ 3
+#define RG_CR_KP_T1_MSK 0x00700000
+#define RG_CR_KP_T1_I_MSK 0xff8fffff
+#define RG_CR_KP_T1_SFT 20
+#define RG_CR_KP_T1_HI 22
+#define RG_CR_KP_T1_SZ 3
+#define RG_CHIP_CNT_SLICER_MSK 0x0000001f
+#define RG_CHIP_CNT_SLICER_I_MSK 0xffffffe0
+#define RG_CHIP_CNT_SLICER_SFT 0
+#define RG_CHIP_CNT_SLICER_HI 4
+#define RG_CHIP_CNT_SLICER_SZ 5
+#define RG_CE_T2_CNT_LMT_MSK 0xff000000
+#define RG_CE_T2_CNT_LMT_I_MSK 0x00ffffff
+#define RG_CE_T2_CNT_LMT_SFT 24
+#define RG_CE_T2_CNT_LMT_HI 31
+#define RG_CE_T2_CNT_LMT_SZ 8
+#define RG_CE_MU_T1_MSK 0x00000007
+#define RG_CE_MU_T1_I_MSK 0xfffffff8
+#define RG_CE_MU_T1_SFT 0
+#define RG_CE_MU_T1_HI 2
+#define RG_CE_MU_T1_SZ 3
+#define RG_CE_DLY_SEL_MSK 0x003f0000
+#define RG_CE_DLY_SEL_I_MSK 0xffc0ffff
+#define RG_CE_DLY_SEL_SFT 16
+#define RG_CE_DLY_SEL_HI 21
+#define RG_CE_DLY_SEL_SZ 6
+#define RG_CE_MU_T4_MSK 0x00000007
+#define RG_CE_MU_T4_I_MSK 0xfffffff8
+#define RG_CE_MU_T4_SFT 0
+#define RG_CE_MU_T4_HI 2
+#define RG_CE_MU_T4_SZ 3
+#define RG_CE_MU_T3_MSK 0x00070000
+#define RG_CE_MU_T3_I_MSK 0xfff8ffff
+#define RG_CE_MU_T3_SFT 16
+#define RG_CE_MU_T3_HI 18
+#define RG_CE_MU_T3_SZ 3
+#define RG_CE_MU_T2_MSK 0x07000000
+#define RG_CE_MU_T2_I_MSK 0xf8ffffff
+#define RG_CE_MU_T2_SFT 24
+#define RG_CE_MU_T2_HI 26
+#define RG_CE_MU_T2_SZ 3
+#define RG_EQ_MU_FB_T2_MSK 0x0000000f
+#define RG_EQ_MU_FB_T2_I_MSK 0xfffffff0
+#define RG_EQ_MU_FB_T2_SFT 0
+#define RG_EQ_MU_FB_T2_HI 3
+#define RG_EQ_MU_FB_T2_SZ 4
+#define RG_EQ_MU_FF_T2_MSK 0x000000f0
+#define RG_EQ_MU_FF_T2_I_MSK 0xffffff0f
+#define RG_EQ_MU_FF_T2_SFT 4
+#define RG_EQ_MU_FF_T2_HI 7
+#define RG_EQ_MU_FF_T2_SZ 4
+#define RG_EQ_MU_FB_T1_MSK 0x000f0000
+#define RG_EQ_MU_FB_T1_I_MSK 0xfff0ffff
+#define RG_EQ_MU_FB_T1_SFT 16
+#define RG_EQ_MU_FB_T1_HI 19
+#define RG_EQ_MU_FB_T1_SZ 4
+#define RG_EQ_MU_FF_T1_MSK 0x00f00000
+#define RG_EQ_MU_FF_T1_I_MSK 0xff0fffff
+#define RG_EQ_MU_FF_T1_SFT 20
+#define RG_EQ_MU_FF_T1_HI 23
+#define RG_EQ_MU_FF_T1_SZ 4
+#define RG_EQ_MU_FB_T4_MSK 0x0000000f
+#define RG_EQ_MU_FB_T4_I_MSK 0xfffffff0
+#define RG_EQ_MU_FB_T4_SFT 0
+#define RG_EQ_MU_FB_T4_HI 3
+#define RG_EQ_MU_FB_T4_SZ 4
+#define RG_EQ_MU_FF_T4_MSK 0x000000f0
+#define RG_EQ_MU_FF_T4_I_MSK 0xffffff0f
+#define RG_EQ_MU_FF_T4_SFT 4
+#define RG_EQ_MU_FF_T4_HI 7
+#define RG_EQ_MU_FF_T4_SZ 4
+#define RG_EQ_MU_FB_T3_MSK 0x000f0000
+#define RG_EQ_MU_FB_T3_I_MSK 0xfff0ffff
+#define RG_EQ_MU_FB_T3_SFT 16
+#define RG_EQ_MU_FB_T3_HI 19
+#define RG_EQ_MU_FB_T3_SZ 4
+#define RG_EQ_MU_FF_T3_MSK 0x00f00000
+#define RG_EQ_MU_FF_T3_I_MSK 0xff0fffff
+#define RG_EQ_MU_FF_T3_SFT 20
+#define RG_EQ_MU_FF_T3_HI 23
+#define RG_EQ_MU_FF_T3_SZ 4
+#define RG_EQ_KI_T2_MSK 0x00000700
+#define RG_EQ_KI_T2_I_MSK 0xfffff8ff
+#define RG_EQ_KI_T2_SFT 8
+#define RG_EQ_KI_T2_HI 10
+#define RG_EQ_KI_T2_SZ 3
+#define RG_EQ_KP_T2_MSK 0x00007000
+#define RG_EQ_KP_T2_I_MSK 0xffff8fff
+#define RG_EQ_KP_T2_SFT 12
+#define RG_EQ_KP_T2_HI 14
+#define RG_EQ_KP_T2_SZ 3
+#define RG_EQ_KI_T1_MSK 0x00070000
+#define RG_EQ_KI_T1_I_MSK 0xfff8ffff
+#define RG_EQ_KI_T1_SFT 16
+#define RG_EQ_KI_T1_HI 18
+#define RG_EQ_KI_T1_SZ 3
+#define RG_EQ_KP_T1_MSK 0x00700000
+#define RG_EQ_KP_T1_I_MSK 0xff8fffff
+#define RG_EQ_KP_T1_SFT 20
+#define RG_EQ_KP_T1_HI 22
+#define RG_EQ_KP_T1_SZ 3
+#define RG_TR_LPF_RATE_MSK 0x003fffff
+#define RG_TR_LPF_RATE_I_MSK 0xffc00000
+#define RG_TR_LPF_RATE_SFT 0
+#define RG_TR_LPF_RATE_HI 21
+#define RG_TR_LPF_RATE_SZ 22
+#define RG_CE_BIT_CNT_LMT_MSK 0x0000007f
+#define RG_CE_BIT_CNT_LMT_I_MSK 0xffffff80
+#define RG_CE_BIT_CNT_LMT_SFT 0
+#define RG_CE_BIT_CNT_LMT_HI 6
+#define RG_CE_BIT_CNT_LMT_SZ 7
+#define RG_CE_CH_MAIN_SET_MSK 0x00000080
+#define RG_CE_CH_MAIN_SET_I_MSK 0xffffff7f
+#define RG_CE_CH_MAIN_SET_SFT 7
+#define RG_CE_CH_MAIN_SET_HI 7
+#define RG_CE_CH_MAIN_SET_SZ 1
+#define RG_TC_BIT_CNT_LMT_MSK 0x00007f00
+#define RG_TC_BIT_CNT_LMT_I_MSK 0xffff80ff
+#define RG_TC_BIT_CNT_LMT_SFT 8
+#define RG_TC_BIT_CNT_LMT_HI 14
+#define RG_TC_BIT_CNT_LMT_SZ 7
+#define RG_CR_BIT_CNT_LMT_MSK 0x007f0000
+#define RG_CR_BIT_CNT_LMT_I_MSK 0xff80ffff
+#define RG_CR_BIT_CNT_LMT_SFT 16
+#define RG_CR_BIT_CNT_LMT_HI 22
+#define RG_CR_BIT_CNT_LMT_SZ 7
+#define RG_TR_BIT_CNT_LMT_MSK 0x7f000000
+#define RG_TR_BIT_CNT_LMT_I_MSK 0x80ffffff
+#define RG_TR_BIT_CNT_LMT_SFT 24
+#define RG_TR_BIT_CNT_LMT_HI 30
+#define RG_TR_BIT_CNT_LMT_SZ 7
+#define RG_EQ_MAIN_TAP_MAN_MSK 0x00000001
+#define RG_EQ_MAIN_TAP_MAN_I_MSK 0xfffffffe
+#define RG_EQ_MAIN_TAP_MAN_SFT 0
+#define RG_EQ_MAIN_TAP_MAN_HI 0
+#define RG_EQ_MAIN_TAP_MAN_SZ 1
+#define RG_EQ_MAIN_TAP_COEF_MSK 0x07ff0000
+#define RG_EQ_MAIN_TAP_COEF_I_MSK 0xf800ffff
+#define RG_EQ_MAIN_TAP_COEF_SFT 16
+#define RG_EQ_MAIN_TAP_COEF_HI 26
+#define RG_EQ_MAIN_TAP_COEF_SZ 11
+#define RG_CCK_TR_KI_T2_MSK 0x00000007
+#define RG_CCK_TR_KI_T2_I_MSK 0xfffffff8
+#define RG_CCK_TR_KI_T2_SFT 0
+#define RG_CCK_TR_KI_T2_HI 2
+#define RG_CCK_TR_KI_T2_SZ 3
+#define RG_CCK_TR_KP_T2_MSK 0x00000070
+#define RG_CCK_TR_KP_T2_I_MSK 0xffffff8f
+#define RG_CCK_TR_KP_T2_SFT 4
+#define RG_CCK_TR_KP_T2_HI 6
+#define RG_CCK_TR_KP_T2_SZ 3
+#define RG_PWRON_DLY_TH_11B_RX_MSK 0x000000ff
+#define RG_PWRON_DLY_TH_11B_RX_I_MSK 0xffffff00
+#define RG_PWRON_DLY_TH_11B_RX_SFT 0
+#define RG_PWRON_DLY_TH_11B_RX_HI 7
+#define RG_PWRON_DLY_TH_11B_RX_SZ 8
+#define RG_SFD_BIT_CNT_LMT_MSK 0x00ff0000
+#define RG_SFD_BIT_CNT_LMT_I_MSK 0xff00ffff
+#define RG_SFD_BIT_CNT_LMT_SFT 16
+#define RG_SFD_BIT_CNT_LMT_HI 23
+#define RG_SFD_BIT_CNT_LMT_SZ 8
+#define RG_PWR_TH_MSK 0x0000ffff
+#define RG_PWR_TH_I_MSK 0xffff0000
+#define RG_PWR_TH_SFT 0
+#define RG_PWR_TH_HI 15
+#define RG_PWR_TH_SZ 16
+#define RG_PWR_CNT_TH_MSK 0x001f0000
+#define RG_PWR_CNT_TH_I_MSK 0xffe0ffff
+#define RG_PWR_CNT_TH_SFT 16
+#define RG_PWR_CNT_TH_HI 20
+#define RG_PWR_CNT_TH_SZ 5
+#define RG_PWR_BIT_CNT_TH_MSK 0x0f000000
+#define RG_PWR_BIT_CNT_TH_I_MSK 0xf0ffffff
+#define RG_PWR_BIT_CNT_TH_SFT 24
+#define RG_PWR_BIT_CNT_TH_HI 27
+#define RG_PWR_BIT_CNT_TH_SZ 4
+#define RG_PSDU_TIME_OFFSET_11B_MSK 0x0000ffff
+#define RG_PSDU_TIME_OFFSET_11B_I_MSK 0xffff0000
+#define RG_PSDU_TIME_OFFSET_11B_SFT 0
+#define RG_PSDU_TIME_OFFSET_11B_HI 15
+#define RG_PSDU_TIME_OFFSET_11B_SZ 16
+#define RG_RESERVED_11B_RX_MSK 0xffffffff
+#define RG_RESERVED_11B_RX_I_MSK 0x00000000
+#define RG_RESERVED_11B_RX_SFT 0
+#define RG_RESERVED_11B_RX_HI 31
+#define RG_RESERVED_11B_RX_SZ 32
+#define RG_INTRUP_RX_11B_CLEAR_MSK 0x00000001
+#define RG_INTRUP_RX_11B_CLEAR_I_MSK 0xfffffffe
+#define RG_INTRUP_RX_11B_CLEAR_SFT 0
+#define RG_INTRUP_RX_11B_CLEAR_HI 0
+#define RG_INTRUP_RX_11B_CLEAR_SZ 1
+#define RG_INTRUP_RX_11B_MASK_MSK 0x00000010
+#define RG_INTRUP_RX_11B_MASK_I_MSK 0xffffffef
+#define RG_INTRUP_RX_11B_MASK_SFT 4
+#define RG_INTRUP_RX_11B_MASK_HI 4
+#define RG_INTRUP_RX_11B_MASK_SZ 1
+#define RG_INTRUP_RX_11B_TRIG_MSK 0x00000f00
+#define RG_INTRUP_RX_11B_TRIG_I_MSK 0xfffff0ff
+#define RG_INTRUP_RX_11B_TRIG_SFT 8
+#define RG_INTRUP_RX_11B_TRIG_HI 11
+#define RG_INTRUP_RX_11B_TRIG_SZ 4
+#define RO_INTRUP_RX_11B_MSK 0x00010000
+#define RO_INTRUP_RX_11B_I_MSK 0xfffeffff
+#define RO_INTRUP_RX_11B_SFT 16
+#define RO_INTRUP_RX_11B_HI 16
+#define RO_INTRUP_RX_11B_SZ 1
+#define RO_11B_FREQ_OS_MSK 0x000007ff
+#define RO_11B_FREQ_OS_I_MSK 0xfffff800
+#define RO_11B_FREQ_OS_SFT 0
+#define RO_11B_FREQ_OS_HI 10
+#define RO_11B_FREQ_OS_SZ 11
+#define RO_11B_SNR_MSK 0x0000007f
+#define RO_11B_SNR_I_MSK 0xffffff80
+#define RO_11B_SNR_SFT 0
+#define RO_11B_SNR_HI 6
+#define RO_11B_SNR_SZ 7
+#define RO_11B_RCPI_MSK 0x007f0000
+#define RO_11B_RCPI_I_MSK 0xff80ffff
+#define RO_11B_RCPI_SFT 16
+#define RO_11B_RCPI_HI 22
+#define RO_11B_RCPI_SZ 7
+#define RO_11B_CRC_CNT_MSK 0x0000ffff
+#define RO_11B_CRC_CNT_I_MSK 0xffff0000
+#define RO_11B_CRC_CNT_SFT 0
+#define RO_11B_CRC_CNT_HI 15
+#define RO_11B_CRC_CNT_SZ 16
+#define RO_11B_SFD_CNT_MSK 0xffff0000
+#define RO_11B_SFD_CNT_I_MSK 0x0000ffff
+#define RO_11B_SFD_CNT_SFT 16
+#define RO_11B_SFD_CNT_HI 31
+#define RO_11B_SFD_CNT_SZ 16
+#define RO_11B_PACKET_ERR_CNT_MSK 0x0000ffff
+#define RO_11B_PACKET_ERR_CNT_I_MSK 0xffff0000
+#define RO_11B_PACKET_ERR_CNT_SFT 0
+#define RO_11B_PACKET_ERR_CNT_HI 15
+#define RO_11B_PACKET_ERR_CNT_SZ 16
+#define RO_11B_PACKET_ERR_MSK 0x00010000
+#define RO_11B_PACKET_ERR_I_MSK 0xfffeffff
+#define RO_11B_PACKET_ERR_SFT 16
+#define RO_11B_PACKET_ERR_HI 16
+#define RO_11B_PACKET_ERR_SZ 1
+#define RO_11B_PACKET_CNT_MSK 0x0000ffff
+#define RO_11B_PACKET_CNT_I_MSK 0xffff0000
+#define RO_11B_PACKET_CNT_SFT 0
+#define RO_11B_PACKET_CNT_HI 15
+#define RO_11B_PACKET_CNT_SZ 16
+#define RO_11B_CCA_CNT_MSK 0xffff0000
+#define RO_11B_CCA_CNT_I_MSK 0x0000ffff
+#define RO_11B_CCA_CNT_SFT 16
+#define RO_11B_CCA_CNT_HI 31
+#define RO_11B_CCA_CNT_SZ 16
+#define RO_11B_LENGTH_FIELD_MSK 0x0000ffff
+#define RO_11B_LENGTH_FIELD_I_MSK 0xffff0000
+#define RO_11B_LENGTH_FIELD_SFT 0
+#define RO_11B_LENGTH_FIELD_HI 15
+#define RO_11B_LENGTH_FIELD_SZ 16
+#define RO_11B_SFD_FIELD_MSK 0xffff0000
+#define RO_11B_SFD_FIELD_I_MSK 0x0000ffff
+#define RO_11B_SFD_FIELD_SFT 16
+#define RO_11B_SFD_FIELD_HI 31
+#define RO_11B_SFD_FIELD_SZ 16
+#define RO_11B_SIGNAL_FIELD_MSK 0x000000ff
+#define RO_11B_SIGNAL_FIELD_I_MSK 0xffffff00
+#define RO_11B_SIGNAL_FIELD_SFT 0
+#define RO_11B_SIGNAL_FIELD_HI 7
+#define RO_11B_SIGNAL_FIELD_SZ 8
+#define RO_11B_SERVICE_FIELD_MSK 0x0000ff00
+#define RO_11B_SERVICE_FIELD_I_MSK 0xffff00ff
+#define RO_11B_SERVICE_FIELD_SFT 8
+#define RO_11B_SERVICE_FIELD_HI 15
+#define RO_11B_SERVICE_FIELD_SZ 8
+#define RO_11B_CRC_CORRECT_MSK 0x00010000
+#define RO_11B_CRC_CORRECT_I_MSK 0xfffeffff
+#define RO_11B_CRC_CORRECT_SFT 16
+#define RO_11B_CRC_CORRECT_HI 16
+#define RO_11B_CRC_CORRECT_SZ 1
+#define RG_RATE_STAT_MSK 0x00070000
+#define RG_RATE_STAT_I_MSK 0xfff8ffff
+#define RG_RATE_STAT_SFT 16
+#define RG_RATE_STAT_HI 18
+#define RG_RATE_STAT_SZ 3
+#define RG_PACKET_STAT_EN_11B_RX_MSK 0x00100000
+#define RG_PACKET_STAT_EN_11B_RX_I_MSK 0xffefffff
+#define RG_PACKET_STAT_EN_11B_RX_SFT 20
+#define RG_PACKET_STAT_EN_11B_RX_HI 20
+#define RG_PACKET_STAT_EN_11B_RX_SZ 1
+#define RG_BIT_REVERSE_MSK 0x00200000
+#define RG_BIT_REVERSE_I_MSK 0xffdfffff
+#define RG_BIT_REVERSE_SFT 21
+#define RG_BIT_REVERSE_HI 21
+#define RG_BIT_REVERSE_SZ 1
+#define RG_SOFT_RST_N_11B_RX_MSK 0x00000001
+#define RG_SOFT_RST_N_11B_RX_I_MSK 0xfffffffe
+#define RG_SOFT_RST_N_11B_RX_SFT 0
+#define RG_SOFT_RST_N_11B_RX_HI 0
+#define RG_SOFT_RST_N_11B_RX_SZ 1
+#define RG_CE_BYPASS_TAP_MSK 0x000000f0
+#define RG_CE_BYPASS_TAP_I_MSK 0xffffff0f
+#define RG_CE_BYPASS_TAP_SFT 4
+#define RG_CE_BYPASS_TAP_HI 7
+#define RG_CE_BYPASS_TAP_SZ 4
+#define RG_EQ_BYPASS_FBW_TAP_MSK 0x00000f00
+#define RG_EQ_BYPASS_FBW_TAP_I_MSK 0xfffff0ff
+#define RG_EQ_BYPASS_FBW_TAP_SFT 8
+#define RG_EQ_BYPASS_FBW_TAP_HI 11
+#define RG_EQ_BYPASS_FBW_TAP_SZ 4
+#define RG_DEBUG_SEL_11B_RX_MSK 0x000f0000
+#define RG_DEBUG_SEL_11B_RX_I_MSK 0xfff0ffff
+#define RG_DEBUG_SEL_11B_RX_SFT 16
+#define RG_DEBUG_SEL_11B_RX_HI 19
+#define RG_DEBUG_SEL_11B_RX_SZ 4
+#define RG_BIST_EN_TX_FFT_MSK 0x00000001
+#define RG_BIST_EN_TX_FFT_I_MSK 0xfffffffe
+#define RG_BIST_EN_TX_FFT_SFT 0
+#define RG_BIST_EN_TX_FFT_HI 0
+#define RG_BIST_EN_TX_FFT_SZ 1
+#define RG_BIST_MODE_TX_FFT_MSK 0x00000010
+#define RG_BIST_MODE_TX_FFT_I_MSK 0xffffffef
+#define RG_BIST_MODE_TX_FFT_SFT 4
+#define RG_BIST_MODE_TX_FFT_HI 4
+#define RG_BIST_MODE_TX_FFT_SZ 1
+#define RO_BIST_DONE_TX_FFT_1_MSK 0x00010000
+#define RO_BIST_DONE_TX_FFT_1_I_MSK 0xfffeffff
+#define RO_BIST_DONE_TX_FFT_1_SFT 16
+#define RO_BIST_DONE_TX_FFT_1_HI 16
+#define RO_BIST_DONE_TX_FFT_1_SZ 1
+#define RO_BIST_FAIL_TX_FFT_1_MSK 0x00020000
+#define RO_BIST_FAIL_TX_FFT_1_I_MSK 0xfffdffff
+#define RO_BIST_FAIL_TX_FFT_1_SFT 17
+#define RO_BIST_FAIL_TX_FFT_1_HI 17
+#define RO_BIST_FAIL_TX_FFT_1_SZ 1
+#define RO_BIST_DONE_TX_FFT_0_MSK 0x00100000
+#define RO_BIST_DONE_TX_FFT_0_I_MSK 0xffefffff
+#define RO_BIST_DONE_TX_FFT_0_SFT 20
+#define RO_BIST_DONE_TX_FFT_0_HI 20
+#define RO_BIST_DONE_TX_FFT_0_SZ 1
+#define RO_BIST_FAIL_TX_FFT_0_MSK 0x00200000
+#define RO_BIST_FAIL_TX_FFT_0_I_MSK 0xffdfffff
+#define RO_BIST_FAIL_TX_FFT_0_SFT 21
+#define RO_BIST_FAIL_TX_FFT_0_HI 21
+#define RO_BIST_FAIL_TX_FFT_0_SZ 1
+#define RG_BB_RISE_TIME_11GN_TX_MSK 0x000000ff
+#define RG_BB_RISE_TIME_11GN_TX_I_MSK 0xffffff00
+#define RG_BB_RISE_TIME_11GN_TX_SFT 0
+#define RG_BB_RISE_TIME_11GN_TX_HI 7
+#define RG_BB_RISE_TIME_11GN_TX_SZ 8
+#define RG_BB_FALL_TIME_11GN_TX_MSK 0x0000ff00
+#define RG_BB_FALL_TIME_11GN_TX_I_MSK 0xffff00ff
+#define RG_BB_FALL_TIME_11GN_TX_SFT 8
+#define RG_BB_FALL_TIME_11GN_TX_HI 15
+#define RG_BB_FALL_TIME_11GN_TX_SZ 8
+#define RG_TX_CLK_OUTER_EN_MSK 0x00000001
+#define RG_TX_CLK_OUTER_EN_I_MSK 0xfffffffe
+#define RG_TX_CLK_OUTER_EN_SFT 0
+#define RG_TX_CLK_OUTER_EN_HI 0
+#define RG_TX_CLK_OUTER_EN_SZ 1
+#define RG_SHORT_GI_EN_MSK 0x00000010
+#define RG_SHORT_GI_EN_I_MSK 0xffffffef
+#define RG_SHORT_GI_EN_SFT 4
+#define RG_SHORT_GI_EN_HI 4
+#define RG_SHORT_GI_EN_SZ 1
+#define RG_STF_SCALE_20_MSK 0x000003ff
+#define RG_STF_SCALE_20_I_MSK 0xfffffc00
+#define RG_STF_SCALE_20_SFT 0
+#define RG_STF_SCALE_20_HI 9
+#define RG_STF_SCALE_20_SZ 10
+#define RG_STF_SCALE_40_MSK 0x03ff0000
+#define RG_STF_SCALE_40_I_MSK 0xfc00ffff
+#define RG_STF_SCALE_40_SFT 16
+#define RG_STF_SCALE_40_HI 25
+#define RG_STF_SCALE_40_SZ 10
+#define RG_FFT_SCALE_104_MSK 0x000003ff
+#define RG_FFT_SCALE_104_I_MSK 0xfffffc00
+#define RG_FFT_SCALE_104_SFT 0
+#define RG_FFT_SCALE_104_HI 9
+#define RG_FFT_SCALE_104_SZ 10
+#define RG_FFT_SCALE_114_MSK 0x03ff0000
+#define RG_FFT_SCALE_114_I_MSK 0xfc00ffff
+#define RG_FFT_SCALE_114_SFT 16
+#define RG_FFT_SCALE_114_HI 25
+#define RG_FFT_SCALE_114_SZ 10
+#define RG_FFT_SCALE_52_MSK 0x000003ff
+#define RG_FFT_SCALE_52_I_MSK 0xfffffc00
+#define RG_FFT_SCALE_52_SFT 0
+#define RG_FFT_SCALE_52_HI 9
+#define RG_FFT_SCALE_52_SZ 10
+#define RG_FFT_SCALE_56_MSK 0x003ff000
+#define RG_FFT_SCALE_56_I_MSK 0xffc00fff
+#define RG_FFT_SCALE_56_SFT 12
+#define RG_FFT_SCALE_56_HI 21
+#define RG_FFT_SCALE_56_SZ 10
+#define RG_SCR_INIT_SEED_MSK 0x7f000000
+#define RG_SCR_INIT_SEED_I_MSK 0x80ffffff
+#define RG_SCR_INIT_SEED_SFT 24
+#define RG_SCR_INIT_SEED_HI 30
+#define RG_SCR_INIT_SEED_SZ 7
+#define RG_SCR_SEED_MANUANL_MSK 0x80000000
+#define RG_SCR_SEED_MANUANL_I_MSK 0x7fffffff
+#define RG_SCR_SEED_MANUANL_SFT 31
+#define RG_SCR_SEED_MANUANL_HI 31
+#define RG_SCR_SEED_MANUANL_SZ 1
+#define RO_TX_CNT_R_11GN_TX_MSK 0xffffffff
+#define RO_TX_CNT_R_11GN_TX_I_MSK 0x00000000
+#define RO_TX_CNT_R_11GN_TX_SFT 0
+#define RO_TX_CNT_R_11GN_TX_HI 31
+#define RO_TX_CNT_R_11GN_TX_SZ 32
+#define RG_DEBUG_SEL_11GN_TX_MSK 0x00000f00
+#define RG_DEBUG_SEL_11GN_TX_I_MSK 0xfffff0ff
+#define RG_DEBUG_SEL_11GN_TX_SFT 8
+#define RG_DEBUG_SEL_11GN_TX_HI 11
+#define RG_DEBUG_SEL_11GN_TX_SZ 4
+#define RG_RESERVED_11GN_TX_MSK 0xffffffff
+#define RG_RESERVED_11GN_TX_I_MSK 0x00000000
+#define RG_RESERVED_11GN_TX_SFT 0
+#define RG_RESERVED_11GN_TX_HI 31
+#define RG_RESERVED_11GN_TX_SZ 32
+#define RG_POS_DES_L_EXT_11GN_RX_MSK 0x0000000f
+#define RG_POS_DES_L_EXT_11GN_RX_I_MSK 0xfffffff0
+#define RG_POS_DES_L_EXT_11GN_RX_SFT 0
+#define RG_POS_DES_L_EXT_11GN_RX_HI 3
+#define RG_POS_DES_L_EXT_11GN_RX_SZ 4
+#define RG_PRE_DES_DLY_11GN_RX_MSK 0x000000f0
+#define RG_PRE_DES_DLY_11GN_RX_I_MSK 0xffffff0f
+#define RG_PRE_DES_DLY_11GN_RX_SFT 4
+#define RG_PRE_DES_DLY_11GN_RX_HI 7
+#define RG_PRE_DES_DLY_11GN_RX_SZ 4
+#define RG_RESERVED_11GN_RX_MSK 0xffffffff
+#define RG_RESERVED_11GN_RX_I_MSK 0x00000000
+#define RG_RESERVED_11GN_RX_SFT 0
+#define RG_RESERVED_11GN_RX_HI 31
+#define RG_RESERVED_11GN_RX_SZ 32
+#define RG_HT40_TR_LPF_KI_MSK 0x0000000f
+#define RG_HT40_TR_LPF_KI_I_MSK 0xfffffff0
+#define RG_HT40_TR_LPF_KI_SFT 0
+#define RG_HT40_TR_LPF_KI_HI 3
+#define RG_HT40_TR_LPF_KI_SZ 4
+#define RG_HT40_TR_LPF_KP_MSK 0x000000f0
+#define RG_HT40_TR_LPF_KP_I_MSK 0xffffff0f
+#define RG_HT40_TR_LPF_KP_SFT 4
+#define RG_HT40_TR_LPF_KP_HI 7
+#define RG_HT40_TR_LPF_KP_SZ 4
+#define RG_HT40_SYM_BOUND_CNT_MSK 0x00007f00
+#define RG_HT40_SYM_BOUND_CNT_I_MSK 0xffff80ff
+#define RG_HT40_SYM_BOUND_CNT_SFT 8
+#define RG_HT40_SYM_BOUND_CNT_HI 14
+#define RG_HT40_SYM_BOUND_CNT_SZ 7
+#define RG_HT20_TR_LPF_KI_MSK 0x0000000f
+#define RG_HT20_TR_LPF_KI_I_MSK 0xfffffff0
+#define RG_HT20_TR_LPF_KI_SFT 0
+#define RG_HT20_TR_LPF_KI_HI 3
+#define RG_HT20_TR_LPF_KI_SZ 4
+#define RG_HT20_TR_LPF_KP_MSK 0x000000f0
+#define RG_HT20_TR_LPF_KP_I_MSK 0xffffff0f
+#define RG_HT20_TR_LPF_KP_SFT 4
+#define RG_HT20_TR_LPF_KP_HI 7
+#define RG_HT20_TR_LPF_KP_SZ 4
+#define RG_TR_LPF_RATE_GN_MSK 0x3fffff00
+#define RG_TR_LPF_RATE_GN_I_MSK 0xc00000ff
+#define RG_TR_LPF_RATE_GN_SFT 8
+#define RG_TR_LPF_RATE_GN_HI 29
+#define RG_TR_LPF_RATE_GN_SZ 22
+#define RG_CR_LPF_KI_GN_MSK 0x00000007
+#define RG_CR_LPF_KI_GN_I_MSK 0xfffffff8
+#define RG_CR_LPF_KI_GN_SFT 0
+#define RG_CR_LPF_KI_GN_HI 2
+#define RG_CR_LPF_KI_GN_SZ 3
+#define RG_HT20_SYM_BOUND_CNT_MSK 0x00007f00
+#define RG_HT20_SYM_BOUND_CNT_I_MSK 0xffff80ff
+#define RG_HT20_SYM_BOUND_CNT_SFT 8
+#define RG_HT20_SYM_BOUND_CNT_HI 14
+#define RG_HT20_SYM_BOUND_CNT_SZ 7
+#define RG_XSCOR32_RATIO_MSK 0x007f0000
+#define RG_XSCOR32_RATIO_I_MSK 0xff80ffff
+#define RG_XSCOR32_RATIO_SFT 16
+#define RG_XSCOR32_RATIO_HI 22
+#define RG_XSCOR32_RATIO_SZ 7
+#define RG_ATCOR64_CNT_LMT_MSK 0x7f000000
+#define RG_ATCOR64_CNT_LMT_I_MSK 0x80ffffff
+#define RG_ATCOR64_CNT_LMT_SFT 24
+#define RG_ATCOR64_CNT_LMT_HI 30
+#define RG_ATCOR64_CNT_LMT_SZ 7
+#define RG_ATCOR16_CNT_LMT2_MSK 0x00007f00
+#define RG_ATCOR16_CNT_LMT2_I_MSK 0xffff80ff
+#define RG_ATCOR16_CNT_LMT2_SFT 8
+#define RG_ATCOR16_CNT_LMT2_HI 14
+#define RG_ATCOR16_CNT_LMT2_SZ 7
+#define RG_ATCOR16_CNT_LMT1_MSK 0x007f0000
+#define RG_ATCOR16_CNT_LMT1_I_MSK 0xff80ffff
+#define RG_ATCOR16_CNT_LMT1_SFT 16
+#define RG_ATCOR16_CNT_LMT1_HI 22
+#define RG_ATCOR16_CNT_LMT1_SZ 7
+#define RG_ATCOR16_RATIO_SB_MSK 0x7f000000
+#define RG_ATCOR16_RATIO_SB_I_MSK 0x80ffffff
+#define RG_ATCOR16_RATIO_SB_SFT 24
+#define RG_ATCOR16_RATIO_SB_HI 30
+#define RG_ATCOR16_RATIO_SB_SZ 7
+#define RG_XSCOR64_CNT_LMT2_MSK 0x007f0000
+#define RG_XSCOR64_CNT_LMT2_I_MSK 0xff80ffff
+#define RG_XSCOR64_CNT_LMT2_SFT 16
+#define RG_XSCOR64_CNT_LMT2_HI 22
+#define RG_XSCOR64_CNT_LMT2_SZ 7
+#define RG_XSCOR64_CNT_LMT1_MSK 0x7f000000
+#define RG_XSCOR64_CNT_LMT1_I_MSK 0x80ffffff
+#define RG_XSCOR64_CNT_LMT1_SFT 24
+#define RG_XSCOR64_CNT_LMT1_HI 30
+#define RG_XSCOR64_CNT_LMT1_SZ 7
+#define RG_HT20_RX_FFT_SCALE_MSK 0x000003ff
+#define RG_HT20_RX_FFT_SCALE_I_MSK 0xfffffc00
+#define RG_HT20_RX_FFT_SCALE_SFT 0
+#define RG_HT20_RX_FFT_SCALE_HI 9
+#define RG_HT20_RX_FFT_SCALE_SZ 10
+#define RG_VITERBI_AB_SWAP_MSK 0x00010000
+#define RG_VITERBI_AB_SWAP_I_MSK 0xfffeffff
+#define RG_VITERBI_AB_SWAP_SFT 16
+#define RG_VITERBI_AB_SWAP_HI 16
+#define RG_VITERBI_AB_SWAP_SZ 1
+#define RG_ATCOR16_CNT_TH_MSK 0x0f000000
+#define RG_ATCOR16_CNT_TH_I_MSK 0xf0ffffff
+#define RG_ATCOR16_CNT_TH_SFT 24
+#define RG_ATCOR16_CNT_TH_HI 27
+#define RG_ATCOR16_CNT_TH_SZ 4
+#define RG_NORMSQUARE_LOW_SNR_7_MSK 0x000000ff
+#define RG_NORMSQUARE_LOW_SNR_7_I_MSK 0xffffff00
+#define RG_NORMSQUARE_LOW_SNR_7_SFT 0
+#define RG_NORMSQUARE_LOW_SNR_7_HI 7
+#define RG_NORMSQUARE_LOW_SNR_7_SZ 8
+#define RG_NORMSQUARE_LOW_SNR_6_MSK 0x0000ff00
+#define RG_NORMSQUARE_LOW_SNR_6_I_MSK 0xffff00ff
+#define RG_NORMSQUARE_LOW_SNR_6_SFT 8
+#define RG_NORMSQUARE_LOW_SNR_6_HI 15
+#define RG_NORMSQUARE_LOW_SNR_6_SZ 8
+#define RG_NORMSQUARE_LOW_SNR_5_MSK 0x00ff0000
+#define RG_NORMSQUARE_LOW_SNR_5_I_MSK 0xff00ffff
+#define RG_NORMSQUARE_LOW_SNR_5_SFT 16
+#define RG_NORMSQUARE_LOW_SNR_5_HI 23
+#define RG_NORMSQUARE_LOW_SNR_5_SZ 8
+#define RG_NORMSQUARE_LOW_SNR_4_MSK 0xff000000
+#define RG_NORMSQUARE_LOW_SNR_4_I_MSK 0x00ffffff
+#define RG_NORMSQUARE_LOW_SNR_4_SFT 24
+#define RG_NORMSQUARE_LOW_SNR_4_HI 31
+#define RG_NORMSQUARE_LOW_SNR_4_SZ 8
+#define RG_NORMSQUARE_LOW_SNR_8_MSK 0xff000000
+#define RG_NORMSQUARE_LOW_SNR_8_I_MSK 0x00ffffff
+#define RG_NORMSQUARE_LOW_SNR_8_SFT 24
+#define RG_NORMSQUARE_LOW_SNR_8_HI 31
+#define RG_NORMSQUARE_LOW_SNR_8_SZ 8
+#define RG_NORMSQUARE_SNR_3_MSK 0x000000ff
+#define RG_NORMSQUARE_SNR_3_I_MSK 0xffffff00
+#define RG_NORMSQUARE_SNR_3_SFT 0
+#define RG_NORMSQUARE_SNR_3_HI 7
+#define RG_NORMSQUARE_SNR_3_SZ 8
+#define RG_NORMSQUARE_SNR_2_MSK 0x0000ff00
+#define RG_NORMSQUARE_SNR_2_I_MSK 0xffff00ff
+#define RG_NORMSQUARE_SNR_2_SFT 8
+#define RG_NORMSQUARE_SNR_2_HI 15
+#define RG_NORMSQUARE_SNR_2_SZ 8
+#define RG_NORMSQUARE_SNR_1_MSK 0x00ff0000
+#define RG_NORMSQUARE_SNR_1_I_MSK 0xff00ffff
+#define RG_NORMSQUARE_SNR_1_SFT 16
+#define RG_NORMSQUARE_SNR_1_HI 23
+#define RG_NORMSQUARE_SNR_1_SZ 8
+#define RG_NORMSQUARE_SNR_0_MSK 0xff000000
+#define RG_NORMSQUARE_SNR_0_I_MSK 0x00ffffff
+#define RG_NORMSQUARE_SNR_0_SFT 24
+#define RG_NORMSQUARE_SNR_0_HI 31
+#define RG_NORMSQUARE_SNR_0_SZ 8
+#define RG_NORMSQUARE_SNR_7_MSK 0x000000ff
+#define RG_NORMSQUARE_SNR_7_I_MSK 0xffffff00
+#define RG_NORMSQUARE_SNR_7_SFT 0
+#define RG_NORMSQUARE_SNR_7_HI 7
+#define RG_NORMSQUARE_SNR_7_SZ 8
+#define RG_NORMSQUARE_SNR_6_MSK 0x0000ff00
+#define RG_NORMSQUARE_SNR_6_I_MSK 0xffff00ff
+#define RG_NORMSQUARE_SNR_6_SFT 8
+#define RG_NORMSQUARE_SNR_6_HI 15
+#define RG_NORMSQUARE_SNR_6_SZ 8
+#define RG_NORMSQUARE_SNR_5_MSK 0x00ff0000
+#define RG_NORMSQUARE_SNR_5_I_MSK 0xff00ffff
+#define RG_NORMSQUARE_SNR_5_SFT 16
+#define RG_NORMSQUARE_SNR_5_HI 23
+#define RG_NORMSQUARE_SNR_5_SZ 8
+#define RG_NORMSQUARE_SNR_4_MSK 0xff000000
+#define RG_NORMSQUARE_SNR_4_I_MSK 0x00ffffff
+#define RG_NORMSQUARE_SNR_4_SFT 24
+#define RG_NORMSQUARE_SNR_4_HI 31
+#define RG_NORMSQUARE_SNR_4_SZ 8
+#define RG_NORMSQUARE_SNR_8_MSK 0xff000000
+#define RG_NORMSQUARE_SNR_8_I_MSK 0x00ffffff
+#define RG_NORMSQUARE_SNR_8_SFT 24
+#define RG_NORMSQUARE_SNR_8_HI 31
+#define RG_NORMSQUARE_SNR_8_SZ 8
+#define RG_SNR_TH_64QAM_MSK 0x0000007f
+#define RG_SNR_TH_64QAM_I_MSK 0xffffff80
+#define RG_SNR_TH_64QAM_SFT 0
+#define RG_SNR_TH_64QAM_HI 6
+#define RG_SNR_TH_64QAM_SZ 7
+#define RG_SNR_TH_16QAM_MSK 0x00007f00
+#define RG_SNR_TH_16QAM_I_MSK 0xffff80ff
+#define RG_SNR_TH_16QAM_SFT 8
+#define RG_SNR_TH_16QAM_HI 14
+#define RG_SNR_TH_16QAM_SZ 7
+#define RG_ATCOR16_CNT_PLUS_LMT2_MSK 0x0000007f
+#define RG_ATCOR16_CNT_PLUS_LMT2_I_MSK 0xffffff80
+#define RG_ATCOR16_CNT_PLUS_LMT2_SFT 0
+#define RG_ATCOR16_CNT_PLUS_LMT2_HI 6
+#define RG_ATCOR16_CNT_PLUS_LMT2_SZ 7
+#define RG_ATCOR16_CNT_PLUS_LMT1_MSK 0x00007f00
+#define RG_ATCOR16_CNT_PLUS_LMT1_I_MSK 0xffff80ff
+#define RG_ATCOR16_CNT_PLUS_LMT1_SFT 8
+#define RG_ATCOR16_CNT_PLUS_LMT1_HI 14
+#define RG_ATCOR16_CNT_PLUS_LMT1_SZ 7
+#define RG_SYM_BOUND_METHOD_MSK 0x00030000
+#define RG_SYM_BOUND_METHOD_I_MSK 0xfffcffff
+#define RG_SYM_BOUND_METHOD_SFT 16
+#define RG_SYM_BOUND_METHOD_HI 17
+#define RG_SYM_BOUND_METHOD_SZ 2
+#define RG_HT40_RX_FFT_SCALE_MSK 0x000003ff
+#define RG_HT40_RX_FFT_SCALE_I_MSK 0xfffffc00
+#define RG_HT40_RX_FFT_SCALE_SFT 0
+#define RG_HT40_RX_FFT_SCALE_HI 9
+#define RG_HT40_RX_FFT_SCALE_SZ 10
+#define RG_ERASE_SC_NUM3_MSK 0x0000007f
+#define RG_ERASE_SC_NUM3_I_MSK 0xffffff80
+#define RG_ERASE_SC_NUM3_SFT 0
+#define RG_ERASE_SC_NUM3_HI 6
+#define RG_ERASE_SC_NUM3_SZ 7
+#define RG_SC_CTRL3_MSK 0x00000080
+#define RG_SC_CTRL3_I_MSK 0xffffff7f
+#define RG_SC_CTRL3_SFT 7
+#define RG_SC_CTRL3_HI 7
+#define RG_SC_CTRL3_SZ 1
+#define RG_ERASE_SC_NUM2_MSK 0x00007f00
+#define RG_ERASE_SC_NUM2_I_MSK 0xffff80ff
+#define RG_ERASE_SC_NUM2_SFT 8
+#define RG_ERASE_SC_NUM2_HI 14
+#define RG_ERASE_SC_NUM2_SZ 7
+#define RG_SC_CTRL2_MSK 0x00008000
+#define RG_SC_CTRL2_I_MSK 0xffff7fff
+#define RG_SC_CTRL2_SFT 15
+#define RG_SC_CTRL2_HI 15
+#define RG_SC_CTRL2_SZ 1
+#define RG_ERASE_SC_NUM1_MSK 0x007f0000
+#define RG_ERASE_SC_NUM1_I_MSK 0xff80ffff
+#define RG_ERASE_SC_NUM1_SFT 16
+#define RG_ERASE_SC_NUM1_HI 22
+#define RG_ERASE_SC_NUM1_SZ 7
+#define RG_SC_CTRL1_MSK 0x00800000
+#define RG_SC_CTRL1_I_MSK 0xff7fffff
+#define RG_SC_CTRL1_SFT 23
+#define RG_SC_CTRL1_HI 23
+#define RG_SC_CTRL1_SZ 1
+#define RG_ERASE_SC_NUM0_MSK 0x7f000000
+#define RG_ERASE_SC_NUM0_I_MSK 0x80ffffff
+#define RG_ERASE_SC_NUM0_SFT 24
+#define RG_ERASE_SC_NUM0_HI 30
+#define RG_ERASE_SC_NUM0_SZ 7
+#define RG_SC_CTRL0_MSK 0x80000000
+#define RG_SC_CTRL0_I_MSK 0x7fffffff
+#define RG_SC_CTRL0_SFT 31
+#define RG_SC_CTRL0_HI 31
+#define RG_SC_CTRL0_SZ 1
+#define RG_ERASE_SC_NUM7_MSK 0x0000007f
+#define RG_ERASE_SC_NUM7_I_MSK 0xffffff80
+#define RG_ERASE_SC_NUM7_SFT 0
+#define RG_ERASE_SC_NUM7_HI 6
+#define RG_ERASE_SC_NUM7_SZ 7
+#define RG_SC_CTRL7_MSK 0x00000080
+#define RG_SC_CTRL7_I_MSK 0xffffff7f
+#define RG_SC_CTRL7_SFT 7
+#define RG_SC_CTRL7_HI 7
+#define RG_SC_CTRL7_SZ 1
+#define RG_ERASE_SC_NUM6_MSK 0x00007f00
+#define RG_ERASE_SC_NUM6_I_MSK 0xffff80ff
+#define RG_ERASE_SC_NUM6_SFT 8
+#define RG_ERASE_SC_NUM6_HI 14
+#define RG_ERASE_SC_NUM6_SZ 7
+#define RG_SC_CTRL6_MSK 0x00008000
+#define RG_SC_CTRL6_I_MSK 0xffff7fff
+#define RG_SC_CTRL6_SFT 15
+#define RG_SC_CTRL6_HI 15
+#define RG_SC_CTRL6_SZ 1
+#define RG_ERASE_SC_NUM5_MSK 0x007f0000
+#define RG_ERASE_SC_NUM5_I_MSK 0xff80ffff
+#define RG_ERASE_SC_NUM5_SFT 16
+#define RG_ERASE_SC_NUM5_HI 22
+#define RG_ERASE_SC_NUM5_SZ 7
+#define RG_SC_CTRL5_MSK 0x00800000
+#define RG_SC_CTRL5_I_MSK 0xff7fffff
+#define RG_SC_CTRL5_SFT 23
+#define RG_SC_CTRL5_HI 23
+#define RG_SC_CTRL5_SZ 1
+#define RG_ERASE_SC_NUM4_MSK 0x7f000000
+#define RG_ERASE_SC_NUM4_I_MSK 0x80ffffff
+#define RG_ERASE_SC_NUM4_SFT 24
+#define RG_ERASE_SC_NUM4_HI 30
+#define RG_ERASE_SC_NUM4_SZ 7
+#define RG_SC_CTRL4_MSK 0x80000000
+#define RG_SC_CTRL4_I_MSK 0x7fffffff
+#define RG_SC_CTRL4_SFT 31
+#define RG_SC_CTRL4_HI 31
+#define RG_SC_CTRL4_SZ 1
+#define RG_BIST_EN_CCFO_MSK 0x00000001
+#define RG_BIST_EN_CCFO_I_MSK 0xfffffffe
+#define RG_BIST_EN_CCFO_SFT 0
+#define RG_BIST_EN_CCFO_HI 0
+#define RG_BIST_EN_CCFO_SZ 1
+#define RG_BIST_MODE_CCFO_MSK 0x00000010
+#define RG_BIST_MODE_CCFO_I_MSK 0xffffffef
+#define RG_BIST_MODE_CCFO_SFT 4
+#define RG_BIST_MODE_CCFO_HI 4
+#define RG_BIST_MODE_CCFO_SZ 1
+#define RO_BIST_DONE_CCFO_1_MSK 0x00010000
+#define RO_BIST_DONE_CCFO_1_I_MSK 0xfffeffff
+#define RO_BIST_DONE_CCFO_1_SFT 16
+#define RO_BIST_DONE_CCFO_1_HI 16
+#define RO_BIST_DONE_CCFO_1_SZ 1
+#define RO_BIST_FAIL_CCFO_1_MSK 0x00020000
+#define RO_BIST_FAIL_CCFO_1_I_MSK 0xfffdffff
+#define RO_BIST_FAIL_CCFO_1_SFT 17
+#define RO_BIST_FAIL_CCFO_1_HI 17
+#define RO_BIST_FAIL_CCFO_1_SZ 1
+#define RO_BIST_DONE_CCFO_0_MSK 0x00100000
+#define RO_BIST_DONE_CCFO_0_I_MSK 0xffefffff
+#define RO_BIST_DONE_CCFO_0_SFT 20
+#define RO_BIST_DONE_CCFO_0_HI 20
+#define RO_BIST_DONE_CCFO_0_SZ 1
+#define RO_BIST_FAIL_CCFO_0_MSK 0x00200000
+#define RO_BIST_FAIL_CCFO_0_I_MSK 0xffdfffff
+#define RO_BIST_FAIL_CCFO_0_SFT 21
+#define RO_BIST_FAIL_CCFO_0_HI 21
+#define RO_BIST_FAIL_CCFO_0_SZ 1
+#define RG_BIST_EN_VTB_MSK 0x00000001
+#define RG_BIST_EN_VTB_I_MSK 0xfffffffe
+#define RG_BIST_EN_VTB_SFT 0
+#define RG_BIST_EN_VTB_HI 0
+#define RG_BIST_EN_VTB_SZ 1
+#define RG_BIST_MODE_VTB_MSK 0x00000010
+#define RG_BIST_MODE_VTB_I_MSK 0xffffffef
+#define RG_BIST_MODE_VTB_SFT 4
+#define RG_BIST_MODE_VTB_HI 4
+#define RG_BIST_MODE_VTB_SZ 1
+#define RO_BIST_DONE_VTB_3_MSK 0x00010000
+#define RO_BIST_DONE_VTB_3_I_MSK 0xfffeffff
+#define RO_BIST_DONE_VTB_3_SFT 16
+#define RO_BIST_DONE_VTB_3_HI 16
+#define RO_BIST_DONE_VTB_3_SZ 1
+#define RO_BIST_FAIL_VTB_3_MSK 0x00020000
+#define RO_BIST_FAIL_VTB_3_I_MSK 0xfffdffff
+#define RO_BIST_FAIL_VTB_3_SFT 17
+#define RO_BIST_FAIL_VTB_3_HI 17
+#define RO_BIST_FAIL_VTB_3_SZ 1
+#define RO_BIST_DONE_VTB_2_MSK 0x00100000
+#define RO_BIST_DONE_VTB_2_I_MSK 0xffefffff
+#define RO_BIST_DONE_VTB_2_SFT 20
+#define RO_BIST_DONE_VTB_2_HI 20
+#define RO_BIST_DONE_VTB_2_SZ 1
+#define RO_BIST_FAIL_VTB_2_MSK 0x00200000
+#define RO_BIST_FAIL_VTB_2_I_MSK 0xffdfffff
+#define RO_BIST_FAIL_VTB_2_SFT 21
+#define RO_BIST_FAIL_VTB_2_HI 21
+#define RO_BIST_FAIL_VTB_2_SZ 1
+#define RO_BIST_DONE_VTB_1_MSK 0x01000000
+#define RO_BIST_DONE_VTB_1_I_MSK 0xfeffffff
+#define RO_BIST_DONE_VTB_1_SFT 24
+#define RO_BIST_DONE_VTB_1_HI 24
+#define RO_BIST_DONE_VTB_1_SZ 1
+#define RO_BIST_FAIL_VTB_1_MSK 0x02000000
+#define RO_BIST_FAIL_VTB_1_I_MSK 0xfdffffff
+#define RO_BIST_FAIL_VTB_1_SFT 25
+#define RO_BIST_FAIL_VTB_1_HI 25
+#define RO_BIST_FAIL_VTB_1_SZ 1
+#define RO_BIST_DONE_VTB_0_MSK 0x10000000
+#define RO_BIST_DONE_VTB_0_I_MSK 0xefffffff
+#define RO_BIST_DONE_VTB_0_SFT 28
+#define RO_BIST_DONE_VTB_0_HI 28
+#define RO_BIST_DONE_VTB_0_SZ 1
+#define RO_BIST_FAIL_VTB_0_MSK 0x20000000
+#define RO_BIST_FAIL_VTB_0_I_MSK 0xdfffffff
+#define RO_BIST_FAIL_VTB_0_SFT 29
+#define RO_BIST_FAIL_VTB_0_HI 29
+#define RO_BIST_FAIL_VTB_0_SZ 1
+#define RG_PWRON_DLY_TH_11GN_RX_MSK 0x000000ff
+#define RG_PWRON_DLY_TH_11GN_RX_I_MSK 0xffffff00
+#define RG_PWRON_DLY_TH_11GN_RX_SFT 0
+#define RG_PWRON_DLY_TH_11GN_RX_HI 7
+#define RG_PWRON_DLY_TH_11GN_RX_SZ 8
+#define RG_SB_START_CNT_MSK 0x00007f00
+#define RG_SB_START_CNT_I_MSK 0xffff80ff
+#define RG_SB_START_CNT_SFT 8
+#define RG_SB_START_CNT_HI 14
+#define RG_SB_START_CNT_SZ 7
+#define RG_CCA_POW_CNT_TH_MSK 0x000000f0
+#define RG_CCA_POW_CNT_TH_I_MSK 0xffffff0f
+#define RG_CCA_POW_CNT_TH_SFT 4
+#define RG_CCA_POW_CNT_TH_HI 7
+#define RG_CCA_POW_CNT_TH_SZ 4
+#define RG_CCA_POW_SHORT_CNT_LMT_MSK 0x00000700
+#define RG_CCA_POW_SHORT_CNT_LMT_I_MSK 0xfffff8ff
+#define RG_CCA_POW_SHORT_CNT_LMT_SFT 8
+#define RG_CCA_POW_SHORT_CNT_LMT_HI 10
+#define RG_CCA_POW_SHORT_CNT_LMT_SZ 3
+#define RG_CCA_POW_TH_MSK 0xffff0000
+#define RG_CCA_POW_TH_I_MSK 0x0000ffff
+#define RG_CCA_POW_TH_SFT 16
+#define RG_CCA_POW_TH_HI 31
+#define RG_CCA_POW_TH_SZ 16
+#define RG_POW16_CNT_TH_MSK 0x000000f0
+#define RG_POW16_CNT_TH_I_MSK 0xffffff0f
+#define RG_POW16_CNT_TH_SFT 4
+#define RG_POW16_CNT_TH_HI 7
+#define RG_POW16_CNT_TH_SZ 4
+#define RG_POW16_SHORT_CNT_LMT_MSK 0x00000700
+#define RG_POW16_SHORT_CNT_LMT_I_MSK 0xfffff8ff
+#define RG_POW16_SHORT_CNT_LMT_SFT 8
+#define RG_POW16_SHORT_CNT_LMT_HI 10
+#define RG_POW16_SHORT_CNT_LMT_SZ 3
+#define RG_POW16_TH_L_MSK 0xff000000
+#define RG_POW16_TH_L_I_MSK 0x00ffffff
+#define RG_POW16_TH_L_SFT 24
+#define RG_POW16_TH_L_HI 31
+#define RG_POW16_TH_L_SZ 8
+#define RG_XSCOR16_SHORT_CNT_LMT_MSK 0x00000007
+#define RG_XSCOR16_SHORT_CNT_LMT_I_MSK 0xfffffff8
+#define RG_XSCOR16_SHORT_CNT_LMT_SFT 0
+#define RG_XSCOR16_SHORT_CNT_LMT_HI 2
+#define RG_XSCOR16_SHORT_CNT_LMT_SZ 3
+#define RG_XSCOR16_RATIO_MSK 0x00007f00
+#define RG_XSCOR16_RATIO_I_MSK 0xffff80ff
+#define RG_XSCOR16_RATIO_SFT 8
+#define RG_XSCOR16_RATIO_HI 14
+#define RG_XSCOR16_RATIO_SZ 7
+#define RG_ATCOR16_SHORT_CNT_LMT_MSK 0x00070000
+#define RG_ATCOR16_SHORT_CNT_LMT_I_MSK 0xfff8ffff
+#define RG_ATCOR16_SHORT_CNT_LMT_SFT 16
+#define RG_ATCOR16_SHORT_CNT_LMT_HI 18
+#define RG_ATCOR16_SHORT_CNT_LMT_SZ 3
+#define RG_ATCOR16_RATIO_CCD_MSK 0x7f000000
+#define RG_ATCOR16_RATIO_CCD_I_MSK 0x80ffffff
+#define RG_ATCOR16_RATIO_CCD_SFT 24
+#define RG_ATCOR16_RATIO_CCD_HI 30
+#define RG_ATCOR16_RATIO_CCD_SZ 7
+#define RG_ATCOR64_ACC_LMT_MSK 0x0000007f
+#define RG_ATCOR64_ACC_LMT_I_MSK 0xffffff80
+#define RG_ATCOR64_ACC_LMT_SFT 0
+#define RG_ATCOR64_ACC_LMT_HI 6
+#define RG_ATCOR64_ACC_LMT_SZ 7
+#define RG_ATCOR16_SHORT_CNT_LMT2_MSK 0x00070000
+#define RG_ATCOR16_SHORT_CNT_LMT2_I_MSK 0xfff8ffff
+#define RG_ATCOR16_SHORT_CNT_LMT2_SFT 16
+#define RG_ATCOR16_SHORT_CNT_LMT2_HI 18
+#define RG_ATCOR16_SHORT_CNT_LMT2_SZ 3
+#define RG_CCFO_CNT_LMT_MSK 0x0000007f
+#define RG_CCFO_CNT_LMT_I_MSK 0xffffff80
+#define RG_CCFO_CNT_LMT_SFT 0
+#define RG_CCFO_CNT_LMT_HI 6
+#define RG_CCFO_CNT_LMT_SZ 7
+#define RG_BYPASS_COARSE_FREQ_MSK 0x00000100
+#define RG_BYPASS_COARSE_FREQ_I_MSK 0xfffffeff
+#define RG_BYPASS_COARSE_FREQ_SFT 8
+#define RG_BYPASS_COARSE_FREQ_HI 8
+#define RG_BYPASS_COARSE_FREQ_SZ 1
+#define RG_CCFO_GAIN_BY2_MSK 0x00000200
+#define RG_CCFO_GAIN_BY2_I_MSK 0xfffffdff
+#define RG_CCFO_GAIN_BY2_SFT 9
+#define RG_CCFO_GAIN_BY2_HI 9
+#define RG_CCFO_GAIN_BY2_SZ 1
+#define RG_XSCOR64_RATIO_SB_MSK 0x007f0000
+#define RG_XSCOR64_RATIO_SB_I_MSK 0xff80ffff
+#define RG_XSCOR64_RATIO_SB_SFT 16
+#define RG_XSCOR64_RATIO_SB_HI 22
+#define RG_XSCOR64_RATIO_SB_SZ 7
+#define RG_5G_CCFO_CNT_LMT_MSK 0x0000007f
+#define RG_5G_CCFO_CNT_LMT_I_MSK 0xffffff80
+#define RG_5G_CCFO_CNT_LMT_SFT 0
+#define RG_5G_CCFO_CNT_LMT_HI 6
+#define RG_5G_CCFO_CNT_LMT_SZ 7
+#define RG_5G_BYPASS_COARSE_FREQ_MSK 0x00000100
+#define RG_5G_BYPASS_COARSE_FREQ_I_MSK 0xfffffeff
+#define RG_5G_BYPASS_COARSE_FREQ_SFT 8
+#define RG_5G_BYPASS_COARSE_FREQ_HI 8
+#define RG_5G_BYPASS_COARSE_FREQ_SZ 1
+#define RG_5G_CCFO_GAIN_BY2_MSK 0x00000200
+#define RG_5G_CCFO_GAIN_BY2_I_MSK 0xfffffdff
+#define RG_5G_CCFO_GAIN_BY2_SFT 9
+#define RG_5G_CCFO_GAIN_BY2_HI 9
+#define RG_5G_CCFO_GAIN_BY2_SZ 1
+#define RG_ACS_INI_PM_ALL0_MSK 0x00000001
+#define RG_ACS_INI_PM_ALL0_I_MSK 0xfffffffe
+#define RG_ACS_INI_PM_ALL0_SFT 0
+#define RG_ACS_INI_PM_ALL0_HI 0
+#define RG_ACS_INI_PM_ALL0_SZ 1
+#define RG_VITERBI_TB_BITS_MSK 0xff000000
+#define RG_VITERBI_TB_BITS_I_MSK 0x00ffffff
+#define RG_VITERBI_TB_BITS_SFT 24
+#define RG_VITERBI_TB_BITS_HI 31
+#define RG_VITERBI_TB_BITS_SZ 8
+#define RG_CR_CNT_UPDATE_SGI_MSK 0x000001ff
+#define RG_CR_CNT_UPDATE_SGI_I_MSK 0xfffffe00
+#define RG_CR_CNT_UPDATE_SGI_SFT 0
+#define RG_CR_CNT_UPDATE_SGI_HI 8
+#define RG_CR_CNT_UPDATE_SGI_SZ 9
+#define RG_TR_CNT_UPDATE_SGI_MSK 0x01ff0000
+#define RG_TR_CNT_UPDATE_SGI_I_MSK 0xfe00ffff
+#define RG_TR_CNT_UPDATE_SGI_SFT 16
+#define RG_TR_CNT_UPDATE_SGI_HI 24
+#define RG_TR_CNT_UPDATE_SGI_SZ 9
+#define RG_CR_CNT_UPDATE_MSK 0x000001ff
+#define RG_CR_CNT_UPDATE_I_MSK 0xfffffe00
+#define RG_CR_CNT_UPDATE_SFT 0
+#define RG_CR_CNT_UPDATE_HI 8
+#define RG_CR_CNT_UPDATE_SZ 9
+#define RG_TR_CNT_UPDATE_MSK 0x01ff0000
+#define RG_TR_CNT_UPDATE_I_MSK 0xfe00ffff
+#define RG_TR_CNT_UPDATE_SFT 16
+#define RG_TR_CNT_UPDATE_HI 24
+#define RG_TR_CNT_UPDATE_SZ 9
+#define RG_CPE_SEL_64QAM_MSK 0x00010000
+#define RG_CPE_SEL_64QAM_I_MSK 0xfffeffff
+#define RG_CPE_SEL_64QAM_SFT 16
+#define RG_CPE_SEL_64QAM_HI 16
+#define RG_CPE_SEL_64QAM_SZ 1
+#define RG_CPE_SEL_16QAM_MSK 0x00020000
+#define RG_CPE_SEL_16QAM_I_MSK 0xfffdffff
+#define RG_CPE_SEL_16QAM_SFT 17
+#define RG_CPE_SEL_16QAM_HI 17
+#define RG_CPE_SEL_16QAM_SZ 1
+#define RG_CPE_SEL_QPSK_MSK 0x00040000
+#define RG_CPE_SEL_QPSK_I_MSK 0xfffbffff
+#define RG_CPE_SEL_QPSK_SFT 18
+#define RG_CPE_SEL_QPSK_HI 18
+#define RG_CPE_SEL_QPSK_SZ 1
+#define RG_CPE_SEL_BPSK_MSK 0x00080000
+#define RG_CPE_SEL_BPSK_I_MSK 0xfff7ffff
+#define RG_CPE_SEL_BPSK_SFT 19
+#define RG_CPE_SEL_BPSK_HI 19
+#define RG_CPE_SEL_BPSK_SZ 1
+#define RG_BYPASS_CPE_MA_MSK 0x00000010
+#define RG_BYPASS_CPE_MA_I_MSK 0xffffffef
+#define RG_BYPASS_CPE_MA_SFT 4
+#define RG_BYPASS_CPE_MA_HI 4
+#define RG_BYPASS_CPE_MA_SZ 1
+#define RG_CHSMTH_COEF_MSK 0x00030000
+#define RG_CHSMTH_COEF_I_MSK 0xfffcffff
+#define RG_CHSMTH_COEF_SFT 16
+#define RG_CHSMTH_COEF_HI 17
+#define RG_CHSMTH_COEF_SZ 2
+#define RG_CHSMTH_EN_MSK 0x00040000
+#define RG_CHSMTH_EN_I_MSK 0xfffbffff
+#define RG_CHSMTH_EN_SFT 18
+#define RG_CHSMTH_EN_HI 18
+#define RG_CHSMTH_EN_SZ 1
+#define RG_CHEST_DD_FACTOR_MSK 0x07000000
+#define RG_CHEST_DD_FACTOR_I_MSK 0xf8ffffff
+#define RG_CHEST_DD_FACTOR_SFT 24
+#define RG_CHEST_DD_FACTOR_HI 26
+#define RG_CHEST_DD_FACTOR_SZ 3
+#define RG_CH_UPDATE_MSK 0x80000000
+#define RG_CH_UPDATE_I_MSK 0x7fffffff
+#define RG_CH_UPDATE_SFT 31
+#define RG_CH_UPDATE_HI 31
+#define RG_CH_UPDATE_SZ 1
+#define RG_FMT_DET_MM_TH_MSK 0x000000ff
+#define RG_FMT_DET_MM_TH_I_MSK 0xffffff00
+#define RG_FMT_DET_MM_TH_SFT 0
+#define RG_FMT_DET_MM_TH_HI 7
+#define RG_FMT_DET_MM_TH_SZ 8
+#define RG_FMT_DET_GF_TH_MSK 0x0000ff00
+#define RG_FMT_DET_GF_TH_I_MSK 0xffff00ff
+#define RG_FMT_DET_GF_TH_SFT 8
+#define RG_FMT_DET_GF_TH_HI 15
+#define RG_FMT_DET_GF_TH_SZ 8
+#define RG_DO_NOT_CHECK_L_RATE_MSK 0x02000000
+#define RG_DO_NOT_CHECK_L_RATE_I_MSK 0xfdffffff
+#define RG_DO_NOT_CHECK_L_RATE_SFT 25
+#define RG_DO_NOT_CHECK_L_RATE_HI 25
+#define RG_DO_NOT_CHECK_L_RATE_SZ 1
+#define RG_NEW_PILOT_AVG_MSK 0x00000001
+#define RG_NEW_PILOT_AVG_I_MSK 0xfffffffe
+#define RG_NEW_PILOT_AVG_SFT 0
+#define RG_NEW_PILOT_AVG_HI 0
+#define RG_NEW_PILOT_AVG_SZ 1
+#define RG_NEW_SB_MSK 0x00000010
+#define RG_NEW_SB_I_MSK 0xffffffef
+#define RG_NEW_SB_SFT 4
+#define RG_NEW_SB_HI 4
+#define RG_NEW_SB_SZ 1
+#define RG_ATCOR64_FREQ_START_MSK 0x00007f00
+#define RG_ATCOR64_FREQ_START_I_MSK 0xffff80ff
+#define RG_ATCOR64_FREQ_START_SFT 8
+#define RG_ATCOR64_FREQ_START_HI 14
+#define RG_ATCOR64_FREQ_START_SZ 7
+#define RG_L_LENGTH_MAX_MSK 0x0fff0000
+#define RG_L_LENGTH_MAX_I_MSK 0xf000ffff
+#define RG_L_LENGTH_MAX_SFT 16
+#define RG_L_LENGTH_MAX_HI 27
+#define RG_L_LENGTH_MAX_SZ 12
+#define RG_ATCOR16_CCA_GAIN_MSK 0x30000000
+#define RG_ATCOR16_CCA_GAIN_I_MSK 0xcfffffff
+#define RG_ATCOR16_CCA_GAIN_SFT 28
+#define RG_ATCOR16_CCA_GAIN_HI 29
+#define RG_ATCOR16_CCA_GAIN_SZ 2
+#define RG_PSDU_TIME_OFFSET_GF_MSK 0x0000ffff
+#define RG_PSDU_TIME_OFFSET_GF_I_MSK 0xffff0000
+#define RG_PSDU_TIME_OFFSET_GF_SFT 0
+#define RG_PSDU_TIME_OFFSET_GF_HI 15
+#define RG_PSDU_TIME_OFFSET_GF_SZ 16
+#define RG_PSDU_TIME_OFFSET_MF_MSK 0xffff0000
+#define RG_PSDU_TIME_OFFSET_MF_I_MSK 0x0000ffff
+#define RG_PSDU_TIME_OFFSET_MF_SFT 16
+#define RG_PSDU_TIME_OFFSET_MF_HI 31
+#define RG_PSDU_TIME_OFFSET_MF_SZ 16
+#define RG_PSDU_TIME_OFFSET_LEGACY_MSK 0x0000ffff
+#define RG_PSDU_TIME_OFFSET_LEGACY_I_MSK 0xffff0000
+#define RG_PSDU_TIME_OFFSET_LEGACY_SFT 0
+#define RG_PSDU_TIME_OFFSET_LEGACY_HI 15
+#define RG_PSDU_TIME_OFFSET_LEGACY_SZ 16
+#define RG_INTRUP_RX_11GN_CLEAR_MSK 0x00000001
+#define RG_INTRUP_RX_11GN_CLEAR_I_MSK 0xfffffffe
+#define RG_INTRUP_RX_11GN_CLEAR_SFT 0
+#define RG_INTRUP_RX_11GN_CLEAR_HI 0
+#define RG_INTRUP_RX_11GN_CLEAR_SZ 1
+#define RG_INTRUP_RX_11GN_MASK_MSK 0x00000010
+#define RG_INTRUP_RX_11GN_MASK_I_MSK 0xffffffef
+#define RG_INTRUP_RX_11GN_MASK_SFT 4
+#define RG_INTRUP_RX_11GN_MASK_HI 4
+#define RG_INTRUP_RX_11GN_MASK_SZ 1
+#define RG_INTRUP_RX_11GN_TRIG_MSK 0x00000f00
+#define RG_INTRUP_RX_11GN_TRIG_I_MSK 0xfffff0ff
+#define RG_INTRUP_RX_11GN_TRIG_SFT 8
+#define RG_INTRUP_RX_11GN_TRIG_HI 11
+#define RG_INTRUP_RX_11GN_TRIG_SZ 4
+#define RO_INTRUP_RX_11GN_MSK 0x00010000
+#define RO_INTRUP_RX_11GN_I_MSK 0xfffeffff
+#define RO_INTRUP_RX_11GN_SFT 16
+#define RO_INTRUP_RX_11GN_HI 16
+#define RO_INTRUP_RX_11GN_SZ 1
+#define RO_STBC_PACKET_CNT_MSK 0x0000ffff
+#define RO_STBC_PACKET_CNT_I_MSK 0xffff0000
+#define RO_STBC_PACKET_CNT_SFT 0
+#define RO_STBC_PACKET_CNT_HI 15
+#define RO_STBC_PACKET_CNT_SZ 16
+#define RO_STBC_PACKET_ERR_CNT_MSK 0xffff0000
+#define RO_STBC_PACKET_ERR_CNT_I_MSK 0x0000ffff
+#define RO_STBC_PACKET_ERR_CNT_SFT 16
+#define RO_STBC_PACKET_ERR_CNT_HI 31
+#define RO_STBC_PACKET_ERR_CNT_SZ 16
+#define RO_11GN_SNR_MSK 0x0000007f
+#define RO_11GN_SNR_I_MSK 0xffffff80
+#define RO_11GN_SNR_SFT 0
+#define RO_11GN_SNR_HI 6
+#define RO_11GN_SNR_SZ 7
+#define RO_11GN_NOISE_PWR_MSK 0x00007f00
+#define RO_11GN_NOISE_PWR_I_MSK 0xffff80ff
+#define RO_11GN_NOISE_PWR_SFT 8
+#define RO_11GN_NOISE_PWR_HI 14
+#define RO_11GN_NOISE_PWR_SZ 7
+#define RO_11GN_RCPI_MSK 0x007f0000
+#define RO_11GN_RCPI_I_MSK 0xff80ffff
+#define RO_11GN_RCPI_SFT 16
+#define RO_11GN_RCPI_HI 22
+#define RO_11GN_RCPI_SZ 7
+#define RO_11GN_SIGNAL_PWR_MSK 0x7f000000
+#define RO_11GN_SIGNAL_PWR_I_MSK 0x80ffffff
+#define RO_11GN_SIGNAL_PWR_SFT 24
+#define RO_11GN_SIGNAL_PWR_HI 30
+#define RO_11GN_SIGNAL_PWR_SZ 7
+#define RO_11GN_FREQ_OS_LTS_MSK 0x00007fff
+#define RO_11GN_FREQ_OS_LTS_I_MSK 0xffff8000
+#define RO_11GN_FREQ_OS_LTS_SFT 0
+#define RO_11GN_FREQ_OS_LTS_HI 14
+#define RO_11GN_FREQ_OS_LTS_SZ 15
+#define RO_11GN_HT_SIGNAL_FIELD_47_24_MSK 0x00ffffff
+#define RO_11GN_HT_SIGNAL_FIELD_47_24_I_MSK 0xff000000
+#define RO_11GN_HT_SIGNAL_FIELD_47_24_SFT 0
+#define RO_11GN_HT_SIGNAL_FIELD_47_24_HI 23
+#define RO_11GN_HT_SIGNAL_FIELD_47_24_SZ 24
+#define RO_11GN_HT_SIGNAL_FIELD_23_0_MSK 0x00ffffff
+#define RO_11GN_HT_SIGNAL_FIELD_23_0_I_MSK 0xff000000
+#define RO_11GN_HT_SIGNAL_FIELD_23_0_SFT 0
+#define RO_11GN_HT_SIGNAL_FIELD_23_0_HI 23
+#define RO_11GN_HT_SIGNAL_FIELD_23_0_SZ 24
+#define RO_11GN_PACKET_ERR_CNT_MSK 0x0000ffff
+#define RO_11GN_PACKET_ERR_CNT_I_MSK 0xffff0000
+#define RO_11GN_PACKET_ERR_CNT_SFT 0
+#define RO_11GN_PACKET_ERR_CNT_HI 15
+#define RO_11GN_PACKET_ERR_CNT_SZ 16
+#define RO_11GN_SERVICE_FIELD_MSK 0xffff0000
+#define RO_11GN_SERVICE_FIELD_I_MSK 0x0000ffff
+#define RO_11GN_SERVICE_FIELD_SFT 16
+#define RO_11GN_SERVICE_FIELD_HI 31
+#define RO_11GN_SERVICE_FIELD_SZ 16
+#define RO_11GN_PACKET_CNT_MSK 0x0000ffff
+#define RO_11GN_PACKET_CNT_I_MSK 0xffff0000
+#define RO_11GN_PACKET_CNT_SFT 0
+#define RO_11GN_PACKET_CNT_HI 15
+#define RO_11GN_PACKET_CNT_SZ 16
+#define RO_11GN_CCA_CNT_MSK 0xffff0000
+#define RO_11GN_CCA_CNT_I_MSK 0x0000ffff
+#define RO_11GN_CCA_CNT_SFT 16
+#define RO_11GN_CCA_CNT_HI 31
+#define RO_11GN_CCA_CNT_SZ 16
+#define RO_11GN_L_SIGNAL_FIELD_MSK 0x00ffffff
+#define RO_11GN_L_SIGNAL_FIELD_I_MSK 0xff000000
+#define RO_11GN_L_SIGNAL_FIELD_SFT 0
+#define RO_11GN_L_SIGNAL_FIELD_HI 23
+#define RO_11GN_L_SIGNAL_FIELD_SZ 24
+#define RO_AMPDU_PACKET_CNT_MSK 0x0000ffff
+#define RO_AMPDU_PACKET_CNT_I_MSK 0xffff0000
+#define RO_AMPDU_PACKET_CNT_SFT 0
+#define RO_AMPDU_PACKET_CNT_HI 15
+#define RO_AMPDU_PACKET_CNT_SZ 16
+#define RO_AMPDU_PACKET_ERR_CNT_MSK 0xffff0000
+#define RO_AMPDU_PACKET_ERR_CNT_I_MSK 0x0000ffff
+#define RO_AMPDU_PACKET_ERR_CNT_SFT 16
+#define RO_AMPDU_PACKET_ERR_CNT_HI 31
+#define RO_AMPDU_PACKET_ERR_CNT_SZ 16
+#define RG_DAGC_CNT_TH_MSK 0x00000003
+#define RG_DAGC_CNT_TH_I_MSK 0xfffffffc
+#define RG_DAGC_CNT_TH_SFT 0
+#define RG_DAGC_CNT_TH_HI 1
+#define RG_DAGC_CNT_TH_SZ 2
+#define RG_RATE_MCS_STAT_MSK 0x000f0000
+#define RG_RATE_MCS_STAT_I_MSK 0xfff0ffff
+#define RG_RATE_MCS_STAT_SFT 16
+#define RG_RATE_MCS_STAT_HI 19
+#define RG_RATE_MCS_STAT_SZ 4
+#define RG_PACKET_STAT_EN_11GN_RX_MSK 0x00100000
+#define RG_PACKET_STAT_EN_11GN_RX_I_MSK 0xffefffff
+#define RG_PACKET_STAT_EN_11GN_RX_SFT 20
+#define RG_PACKET_STAT_EN_11GN_RX_HI 20
+#define RG_PACKET_STAT_EN_11GN_RX_SZ 1
+#define RG_SOFT_RST_N_11GN_RX_MSK 0x00000001
+#define RG_SOFT_RST_N_11GN_RX_I_MSK 0xfffffffe
+#define RG_SOFT_RST_N_11GN_RX_SFT 0
+#define RG_SOFT_RST_N_11GN_RX_HI 0
+#define RG_SOFT_RST_N_11GN_RX_SZ 1
+#define RG_RIFS_EN_MSK 0x00000002
+#define RG_RIFS_EN_I_MSK 0xfffffffd
+#define RG_RIFS_EN_SFT 1
+#define RG_RIFS_EN_HI 1
+#define RG_RIFS_EN_SZ 1
+#define RG_STBC_EN_MSK 0x00000004
+#define RG_STBC_EN_I_MSK 0xfffffffb
+#define RG_STBC_EN_SFT 2
+#define RG_STBC_EN_HI 2
+#define RG_STBC_EN_SZ 1
+#define RG_COR_SEL_MSK 0x00000008
+#define RG_COR_SEL_I_MSK 0xfffffff7
+#define RG_COR_SEL_SFT 3
+#define RG_COR_SEL_HI 3
+#define RG_COR_SEL_SZ 1
+#define RG_INI_PHASE_MSK 0x00000030
+#define RG_INI_PHASE_I_MSK 0xffffffcf
+#define RG_INI_PHASE_SFT 4
+#define RG_INI_PHASE_HI 5
+#define RG_INI_PHASE_SZ 2
+#define RG_CCA_PWR_SEL_MSK 0x00000200
+#define RG_CCA_PWR_SEL_I_MSK 0xfffffdff
+#define RG_CCA_PWR_SEL_SFT 9
+#define RG_CCA_PWR_SEL_HI 9
+#define RG_CCA_PWR_SEL_SZ 1
+#define RG_CCA_XSCOR_PWR_SEL_MSK 0x00000400
+#define RG_CCA_XSCOR_PWR_SEL_I_MSK 0xfffffbff
+#define RG_CCA_XSCOR_PWR_SEL_SFT 10
+#define RG_CCA_XSCOR_PWR_SEL_HI 10
+#define RG_CCA_XSCOR_PWR_SEL_SZ 1
+#define RG_CCA_XSCOR_AVGPWR_SEL_MSK 0x00000800
+#define RG_CCA_XSCOR_AVGPWR_SEL_I_MSK 0xfffff7ff
+#define RG_CCA_XSCOR_AVGPWR_SEL_SFT 11
+#define RG_CCA_XSCOR_AVGPWR_SEL_HI 11
+#define RG_CCA_XSCOR_AVGPWR_SEL_SZ 1
+#define RG_DEBUG_SEL_11GN_RX_MSK 0x0000f000
+#define RG_DEBUG_SEL_11GN_RX_I_MSK 0xffff0fff
+#define RG_DEBUG_SEL_11GN_RX_SFT 12
+#define RG_DEBUG_SEL_11GN_RX_HI 15
+#define RG_DEBUG_SEL_11GN_RX_SZ 4
+#define RG_POST_CLK_EN_MSK 0x00010000
+#define RG_POST_CLK_EN_I_MSK 0xfffeffff
+#define RG_POST_CLK_EN_SFT 16
+#define RG_POST_CLK_EN_HI 16
+#define RG_POST_CLK_EN_SZ 1
+#define RG_THL_ED_MSK 0x0000003f
+#define RG_THL_ED_I_MSK 0xffffffc0
+#define RG_THL_ED_SFT 0
+#define RG_THL_ED_HI 5
+#define RG_THL_ED_SZ 6
+#define RG_THH_ED_MSK 0x00003f00
+#define RG_THH_ED_I_MSK 0xffffc0ff
+#define RG_THH_ED_SFT 8
+#define RG_THH_ED_HI 13
+#define RG_THH_ED_SZ 6
+#define RG_THL_RATIO_MSK 0x00ff0000
+#define RG_THL_RATIO_I_MSK 0xff00ffff
+#define RG_THL_RATIO_SFT 16
+#define RG_THL_RATIO_HI 23
+#define RG_THL_RATIO_SZ 8
+#define RG_THH_RATIO_MSK 0xff000000
+#define RG_THH_RATIO_I_MSK 0x00ffffff
+#define RG_THH_RATIO_SFT 24
+#define RG_THH_RATIO_HI 31
+#define RG_THH_RATIO_SZ 8
+#define RG_PW_MIN_MSK 0x00000fff
+#define RG_PW_MIN_I_MSK 0xfffff000
+#define RG_PW_MIN_SFT 0
+#define RG_PW_MIN_HI 11
+#define RG_PW_MIN_SZ 12
+#define RG_PW_MAX_MSK 0x0fff0000
+#define RG_PW_MAX_I_MSK 0xf000ffff
+#define RG_PW_MAX_SFT 16
+#define RG_PW_MAX_HI 27
+#define RG_PW_MAX_SZ 12
+#define RG_PERIOD_MIN_MSK 0x00000fff
+#define RG_PERIOD_MIN_I_MSK 0xfffff000
+#define RG_PERIOD_MIN_SFT 0
+#define RG_PERIOD_MIN_HI 11
+#define RG_PERIOD_MIN_SZ 12
+#define RG_PERIOD_MAX_MSK 0x0fff0000
+#define RG_PERIOD_MAX_I_MSK 0xf000ffff
+#define RG_PERIOD_MAX_SFT 16
+#define RG_PERIOD_MAX_HI 27
+#define RG_PERIOD_MAX_SZ 12
+#define RG_TIME_PERIOD_MSK 0x00000fff
+#define RG_TIME_PERIOD_I_MSK 0xfffff000
+#define RG_TIME_PERIOD_SFT 0
+#define RG_TIME_PERIOD_HI 11
+#define RG_TIME_PERIOD_SZ 12
+#define RG_PULSE_NUMBER_MSK 0x00700000
+#define RG_PULSE_NUMBER_I_MSK 0xff8fffff
+#define RG_PULSE_NUMBER_SFT 20
+#define RG_PULSE_NUMBER_HI 22
+#define RG_PULSE_NUMBER_SZ 3
+#define RG_ALPHA_FINE_MSK 0x07000000
+#define RG_ALPHA_FINE_I_MSK 0xf8ffffff
+#define RG_ALPHA_FINE_SFT 24
+#define RG_ALPHA_FINE_HI 26
+#define RG_ALPHA_FINE_SZ 3
+#define RG_ALPHA_COARSE_MSK 0x30000000
+#define RG_ALPHA_COARSE_I_MSK 0xcfffffff
+#define RG_ALPHA_COARSE_SFT 28
+#define RG_ALPHA_COARSE_HI 29
+#define RG_ALPHA_COARSE_SZ 2
+#define RG_RADAR_EN_MSK 0x00000001
+#define RG_RADAR_EN_I_MSK 0xfffffffe
+#define RG_RADAR_EN_SFT 0
+#define RG_RADAR_EN_HI 0
+#define RG_RADAR_EN_SZ 1
+#define RG_TOLERANCE_PERIOD_MSK 0x003f0000
+#define RG_TOLERANCE_PERIOD_I_MSK 0xffc0ffff
+#define RG_TOLERANCE_PERIOD_SFT 16
+#define RG_TOLERANCE_PERIOD_HI 21
+#define RG_TOLERANCE_PERIOD_SZ 6
+#define RG_TOLERANCE_PW_MSK 0x3f000000
+#define RG_TOLERANCE_PW_I_MSK 0xc0ffffff
+#define RG_TOLERANCE_PW_SFT 24
+#define RG_TOLERANCE_PW_HI 29
+#define RG_TOLERANCE_PW_SZ 6
+#define RO_RADAR_DET_NUM_MSK 0x00000007
+#define RO_RADAR_DET_NUM_I_MSK 0xfffffff8
+#define RO_RADAR_DET_NUM_SFT 0
+#define RO_RADAR_DET_NUM_HI 2
+#define RO_RADAR_DET_NUM_SZ 3
+#define RO_RADAR_DET_OUT_MSK 0x00000010
+#define RO_RADAR_DET_OUT_I_MSK 0xffffffef
+#define RO_RADAR_DET_OUT_SFT 4
+#define RO_RADAR_DET_OUT_HI 4
+#define RO_RADAR_DET_OUT_SZ 1
+#define RO_RADAR_VALID_MSK 0x00000100
+#define RO_RADAR_VALID_I_MSK 0xfffffeff
+#define RO_RADAR_VALID_SFT 8
+#define RO_RADAR_VALID_HI 8
+#define RO_RADAR_VALID_SZ 1
+#define RO_PW_MSK 0x0fff0000
+#define RO_PW_I_MSK 0xf000ffff
+#define RO_PW_SFT 16
+#define RO_PW_HI 27
+#define RO_PW_SZ 12
+#define RO_PW_ARRAY_0_MSK 0x00000fff
+#define RO_PW_ARRAY_0_I_MSK 0xfffff000
+#define RO_PW_ARRAY_0_SFT 0
+#define RO_PW_ARRAY_0_HI 11
+#define RO_PW_ARRAY_0_SZ 12
+#define RO_PW_ARRAY_1_MSK 0x0fff0000
+#define RO_PW_ARRAY_1_I_MSK 0xf000ffff
+#define RO_PW_ARRAY_1_SFT 16
+#define RO_PW_ARRAY_1_HI 27
+#define RO_PW_ARRAY_1_SZ 12
+#define RO_PW_ARRAY_2_MSK 0x00000fff
+#define RO_PW_ARRAY_2_I_MSK 0xfffff000
+#define RO_PW_ARRAY_2_SFT 0
+#define RO_PW_ARRAY_2_HI 11
+#define RO_PW_ARRAY_2_SZ 12
+#define RO_PW_ARRAY_3_MSK 0x0fff0000
+#define RO_PW_ARRAY_3_I_MSK 0xf000ffff
+#define RO_PW_ARRAY_3_SFT 16
+#define RO_PW_ARRAY_3_HI 27
+#define RO_PW_ARRAY_3_SZ 12
+#define RO_PW_ARRAY_4_MSK 0x00000fff
+#define RO_PW_ARRAY_4_I_MSK 0xfffff000
+#define RO_PW_ARRAY_4_SFT 0
+#define RO_PW_ARRAY_4_HI 11
+#define RO_PW_ARRAY_4_SZ 12
+#define RO_PW_ARRAY_5_MSK 0x0fff0000
+#define RO_PW_ARRAY_5_I_MSK 0xf000ffff
+#define RO_PW_ARRAY_5_SFT 16
+#define RO_PW_ARRAY_5_HI 27
+#define RO_PW_ARRAY_5_SZ 12
+#define RO_PERIOD_ARRAY_0_MSK 0x00000fff
+#define RO_PERIOD_ARRAY_0_I_MSK 0xfffff000
+#define RO_PERIOD_ARRAY_0_SFT 0
+#define RO_PERIOD_ARRAY_0_HI 11
+#define RO_PERIOD_ARRAY_0_SZ 12
+#define RO_PERIOD_ARRAY_1_MSK 0x0fff0000
+#define RO_PERIOD_ARRAY_1_I_MSK 0xf000ffff
+#define RO_PERIOD_ARRAY_1_SFT 16
+#define RO_PERIOD_ARRAY_1_HI 27
+#define RO_PERIOD_ARRAY_1_SZ 12
+#define RO_PERIOD_ARRAY_2_MSK 0x00000fff
+#define RO_PERIOD_ARRAY_2_I_MSK 0xfffff000
+#define RO_PERIOD_ARRAY_2_SFT 0
+#define RO_PERIOD_ARRAY_2_HI 11
+#define RO_PERIOD_ARRAY_2_SZ 12
+#define RO_PERIOD_ARRAY_3_MSK 0x0fff0000
+#define RO_PERIOD_ARRAY_3_I_MSK 0xf000ffff
+#define RO_PERIOD_ARRAY_3_SFT 16
+#define RO_PERIOD_ARRAY_3_HI 27
+#define RO_PERIOD_ARRAY_3_SZ 12
+#define RO_PERIOD_ARRAY_4_MSK 0x00000fff
+#define RO_PERIOD_ARRAY_4_I_MSK 0xfffff000
+#define RO_PERIOD_ARRAY_4_SFT 0
+#define RO_PERIOD_ARRAY_4_HI 11
+#define RO_PERIOD_ARRAY_4_SZ 12
+#define RO_PERIOD_ARRAY_5_MSK 0x0fff0000
+#define RO_PERIOD_ARRAY_5_I_MSK 0xf000ffff
+#define RO_PERIOD_ARRAY_5_SFT 16
+#define RO_PERIOD_ARRAY_5_HI 27
+#define RO_PERIOD_ARRAY_5_SZ 12
+#define RG_PW_CHIRP_MIN_MSK 0x00000fff
+#define RG_PW_CHIRP_MIN_I_MSK 0xfffff000
+#define RG_PW_CHIRP_MIN_SFT 0
+#define RG_PW_CHIRP_MIN_HI 11
+#define RG_PW_CHIRP_MIN_SZ 12
+#define RG_PW_CHIRP_MAX_MSK 0x0fff0000
+#define RG_PW_CHIRP_MAX_I_MSK 0xf000ffff
+#define RG_PW_CHIRP_MAX_SFT 16
+#define RG_PW_CHIRP_MAX_HI 27
+#define RG_PW_CHIRP_MAX_SZ 12
+#define CPU_QUE_POP_ALT_MSK 0x00000001
+#define CPU_QUE_POP_ALT_I_MSK 0xfffffffe
+#define CPU_QUE_POP_ALT_SFT 0
+#define CPU_QUE_POP_ALT_HI 0
+#define CPU_QUE_POP_ALT_SZ 1
+#define CPU_INT_ALT_MSK 0x00000004
+#define CPU_INT_ALT_I_MSK 0xfffffffb
+#define CPU_INT_ALT_SFT 2
+#define CPU_INT_ALT_HI 2
+#define CPU_INT_ALT_SZ 1
+#define CPU_QUE_POP_MSK 0x00000001
+#define CPU_QUE_POP_I_MSK 0xfffffffe
+#define CPU_QUE_POP_SFT 0
+#define CPU_QUE_POP_HI 0
+#define CPU_QUE_POP_SZ 1
+#define CPU_INT_MSK 0x00000004
+#define CPU_INT_I_MSK 0xfffffffb
+#define CPU_INT_SFT 2
+#define CPU_INT_HI 2
+#define CPU_INT_SZ 1
+#define CPU_ID_TB0_MSK 0xffffffff
+#define CPU_ID_TB0_I_MSK 0x00000000
+#define CPU_ID_TB0_SFT 0
+#define CPU_ID_TB0_HI 31
+#define CPU_ID_TB0_SZ 32
+#define CPU_ID_TB1_MSK 0xffffffff
+#define CPU_ID_TB1_I_MSK 0x00000000
+#define CPU_ID_TB1_SFT 0
+#define CPU_ID_TB1_HI 31
+#define CPU_ID_TB1_SZ 32
+#define HW_PKTID_MSK 0x000007ff
+#define HW_PKTID_I_MSK 0xfffff800
+#define HW_PKTID_SFT 0
+#define HW_PKTID_HI 10
+#define HW_PKTID_SZ 11
+#define PKTID_MSK 0x0000007f
+#define PKTID_I_MSK 0xffffff80
+#define PKTID_SFT 0
+#define PKTID_HI 6
+#define PKTID_SZ 7
+#define HWID_MSK 0x00000780
+#define HWID_I_MSK 0xfffff87f
+#define HWID_SFT 7
+#define HWID_HI 10
+#define HWID_SZ 4
+#define CH0_INT_ADDR_MSK 0xffffffff
+#define CH0_INT_ADDR_I_MSK 0x00000000
+#define CH0_INT_ADDR_SFT 0
+#define CH0_INT_ADDR_HI 31
+#define CH0_INT_ADDR_SZ 32
+#define PRI_HW_PKTID_MSK 0x000007ff
+#define PRI_HW_PKTID_I_MSK 0xfffff800
+#define PRI_HW_PKTID_SFT 0
+#define PRI_HW_PKTID_HI 10
+#define PRI_HW_PKTID_SZ 11
+#define PRIPKTID_MSK 0x0000007f
+#define PRIPKTID_I_MSK 0xffffff80
+#define PRIPKTID_SFT 0
+#define PRIPKTID_HI 6
+#define PRIPKTID_SZ 7
+#define PRIHWID_MSK 0x00000780
+#define PRIHWID_I_MSK 0xfffff87f
+#define PRIHWID_SFT 7
+#define PRIHWID_HI 10
+#define PRIHWID_SZ 4
+#define CH0_FULL_MSK 0x00000001
+#define CH0_FULL_I_MSK 0xfffffffe
+#define CH0_FULL_SFT 0
+#define CH0_FULL_HI 0
+#define CH0_FULL_SZ 1
+#define FF0_EMPTY_MSK 0x00000002
+#define FF0_EMPTY_I_MSK 0xfffffffd
+#define FF0_EMPTY_SFT 1
+#define FF0_EMPTY_HI 1
+#define FF0_EMPTY_SZ 1
+#define CH2_FULL_MSK 0x00000010
+#define CH2_FULL_I_MSK 0xffffffef
+#define CH2_FULL_SFT 4
+#define CH2_FULL_HI 4
+#define CH2_FULL_SZ 1
+#define FF2_EMPTY_MSK 0x00000020
+#define FF2_EMPTY_I_MSK 0xffffffdf
+#define FF2_EMPTY_SFT 5
+#define FF2_EMPTY_HI 5
+#define FF2_EMPTY_SZ 1
+#define RLS_BUSY_MSK 0x00000200
+#define RLS_BUSY_I_MSK 0xfffffdff
+#define RLS_BUSY_SFT 9
+#define RLS_BUSY_HI 9
+#define RLS_BUSY_SZ 1
+#define RLS_COUNT_CLR_MSK 0x00000400
+#define RLS_COUNT_CLR_I_MSK 0xfffffbff
+#define RLS_COUNT_CLR_SFT 10
+#define RLS_COUNT_CLR_HI 10
+#define RLS_COUNT_CLR_SZ 1
+#define RTN_COUNT_CLR_MSK 0x00000800
+#define RTN_COUNT_CLR_I_MSK 0xfffff7ff
+#define RTN_COUNT_CLR_SFT 11
+#define RTN_COUNT_CLR_HI 11
+#define RTN_COUNT_CLR_SZ 1
+#define RLS_COUNT_MSK 0x00ff0000
+#define RLS_COUNT_I_MSK 0xff00ffff
+#define RLS_COUNT_SFT 16
+#define RLS_COUNT_HI 23
+#define RLS_COUNT_SZ 8
+#define RTN_COUNT_MSK 0xff000000
+#define RTN_COUNT_I_MSK 0x00ffffff
+#define RTN_COUNT_SFT 24
+#define RTN_COUNT_HI 31
+#define RTN_COUNT_SZ 8
+#define FF0_CNT_MSK 0x0000001f
+#define FF0_CNT_I_MSK 0xffffffe0
+#define FF0_CNT_SFT 0
+#define FF0_CNT_HI 4
+#define FF0_CNT_SZ 5
+#define FF1_CNT_MSK 0x000001e0
+#define FF1_CNT_I_MSK 0xfffffe1f
+#define FF1_CNT_SFT 5
+#define FF1_CNT_HI 8
+#define FF1_CNT_SZ 4
+#define FF3_CNT_MSK 0x00003800
+#define FF3_CNT_I_MSK 0xffffc7ff
+#define FF3_CNT_SFT 11
+#define FF3_CNT_HI 13
+#define FF3_CNT_SZ 3
+#define FF5_CNT_MSK 0x000e0000
+#define FF5_CNT_I_MSK 0xfff1ffff
+#define FF5_CNT_SFT 17
+#define FF5_CNT_HI 19
+#define FF5_CNT_SZ 3
+#define FF6_CNT_MSK 0x00700000
+#define FF6_CNT_I_MSK 0xff8fffff
+#define FF6_CNT_SFT 20
+#define FF6_CNT_HI 22
+#define FF6_CNT_SZ 3
+#define FF7_CNT_MSK 0x03800000
+#define FF7_CNT_I_MSK 0xfc7fffff
+#define FF7_CNT_SFT 23
+#define FF7_CNT_HI 25
+#define FF7_CNT_SZ 3
+#define FF8_CNT_MSK 0x1c000000
+#define FF8_CNT_I_MSK 0xe3ffffff
+#define FF8_CNT_SFT 26
+#define FF8_CNT_HI 28
+#define FF8_CNT_SZ 3
+#define FF9_CNT_MSK 0xe0000000
+#define FF9_CNT_I_MSK 0x1fffffff
+#define FF9_CNT_SFT 29
+#define FF9_CNT_HI 31
+#define FF9_CNT_SZ 3
+#define FF10_CNT_MSK 0x00000007
+#define FF10_CNT_I_MSK 0xfffffff8
+#define FF10_CNT_SFT 0
+#define FF10_CNT_HI 2
+#define FF10_CNT_SZ 3
+#define FF11_CNT_MSK 0x00000038
+#define FF11_CNT_I_MSK 0xffffffc7
+#define FF11_CNT_SFT 3
+#define FF11_CNT_HI 5
+#define FF11_CNT_SZ 3
+#define FF12_CNT_MSK 0x000001c0
+#define FF12_CNT_I_MSK 0xfffffe3f
+#define FF12_CNT_SFT 6
+#define FF12_CNT_HI 8
+#define FF12_CNT_SZ 3
+#define FF13_CNT_MSK 0x00000e00
+#define FF13_CNT_I_MSK 0xfffff1ff
+#define FF13_CNT_SFT 9
+#define FF13_CNT_HI 11
+#define FF13_CNT_SZ 3
+#define FF14_CNT_MSK 0x00007000
+#define FF14_CNT_I_MSK 0xffff8fff
+#define FF14_CNT_SFT 12
+#define FF14_CNT_HI 14
+#define FF14_CNT_SZ 3
+#define FF15_CNT_MSK 0x00038000
+#define FF15_CNT_I_MSK 0xfffc7fff
+#define FF15_CNT_SFT 15
+#define FF15_CNT_HI 17
+#define FF15_CNT_SZ 3
+#define FF4_CNT_MSK 0x007c0000
+#define FF4_CNT_I_MSK 0xff83ffff
+#define FF4_CNT_SFT 18
+#define FF4_CNT_HI 22
+#define FF4_CNT_SZ 5
+#define FF2_CNT_MSK 0x03800000
+#define FF2_CNT_I_MSK 0xfc7fffff
+#define FF2_CNT_SFT 23
+#define FF2_CNT_HI 25
+#define FF2_CNT_SZ 3
+#define CH0_FULL_ALT_MSK 0x00000001
+#define CH0_FULL_ALT_I_MSK 0xfffffffe
+#define CH0_FULL_ALT_SFT 0
+#define CH0_FULL_ALT_HI 0
+#define CH0_FULL_ALT_SZ 1
+#define CH1_FULL_MSK 0x00000002
+#define CH1_FULL_I_MSK 0xfffffffd
+#define CH1_FULL_SFT 1
+#define CH1_FULL_HI 1
+#define CH1_FULL_SZ 1
+#define CH2_FULL_ALT_MSK 0x00000004
+#define CH2_FULL_ALT_I_MSK 0xfffffffb
+#define CH2_FULL_ALT_SFT 2
+#define CH2_FULL_ALT_HI 2
+#define CH2_FULL_ALT_SZ 1
+#define CH3_FULL_MSK 0x00000008
+#define CH3_FULL_I_MSK 0xfffffff7
+#define CH3_FULL_SFT 3
+#define CH3_FULL_HI 3
+#define CH3_FULL_SZ 1
+#define CH4_FULL_MSK 0x00000010
+#define CH4_FULL_I_MSK 0xffffffef
+#define CH4_FULL_SFT 4
+#define CH4_FULL_HI 4
+#define CH4_FULL_SZ 1
+#define CH5_FULL_MSK 0x00000020
+#define CH5_FULL_I_MSK 0xffffffdf
+#define CH5_FULL_SFT 5
+#define CH5_FULL_HI 5
+#define CH5_FULL_SZ 1
+#define CH6_FULL_MSK 0x00000040
+#define CH6_FULL_I_MSK 0xffffffbf
+#define CH6_FULL_SFT 6
+#define CH6_FULL_HI 6
+#define CH6_FULL_SZ 1
+#define CH7_FULL_MSK 0x00000080
+#define CH7_FULL_I_MSK 0xffffff7f
+#define CH7_FULL_SFT 7
+#define CH7_FULL_HI 7
+#define CH7_FULL_SZ 1
+#define CH8_FULL_MSK 0x00000100
+#define CH8_FULL_I_MSK 0xfffffeff
+#define CH8_FULL_SFT 8
+#define CH8_FULL_HI 8
+#define CH8_FULL_SZ 1
+#define CH9_FULL_MSK 0x00000200
+#define CH9_FULL_I_MSK 0xfffffdff
+#define CH9_FULL_SFT 9
+#define CH9_FULL_HI 9
+#define CH9_FULL_SZ 1
+#define CH10_FULL_MSK 0x00000400
+#define CH10_FULL_I_MSK 0xfffffbff
+#define CH10_FULL_SFT 10
+#define CH10_FULL_HI 10
+#define CH10_FULL_SZ 1
+#define CH11_FULL_MSK 0x00000800
+#define CH11_FULL_I_MSK 0xfffff7ff
+#define CH11_FULL_SFT 11
+#define CH11_FULL_HI 11
+#define CH11_FULL_SZ 1
+#define CH12_FULL_MSK 0x00001000
+#define CH12_FULL_I_MSK 0xffffefff
+#define CH12_FULL_SFT 12
+#define CH12_FULL_HI 12
+#define CH12_FULL_SZ 1
+#define CH13_FULL_MSK 0x00002000
+#define CH13_FULL_I_MSK 0xffffdfff
+#define CH13_FULL_SFT 13
+#define CH13_FULL_HI 13
+#define CH13_FULL_SZ 1
+#define CH14_FULL_MSK 0x00004000
+#define CH14_FULL_I_MSK 0xffffbfff
+#define CH14_FULL_SFT 14
+#define CH14_FULL_HI 14
+#define CH14_FULL_SZ 1
+#define CH15_FULL_MSK 0x00008000
+#define CH15_FULL_I_MSK 0xffff7fff
+#define CH15_FULL_SFT 15
+#define CH15_FULL_HI 15
+#define CH15_FULL_SZ 1
+#define HW_PKTID_ALT_MSK 0x000007ff
+#define HW_PKTID_ALT_I_MSK 0xfffff800
+#define HW_PKTID_ALT_SFT 0
+#define HW_PKTID_ALT_HI 10
+#define HW_PKTID_ALT_SZ 11
+#define PKTID_ALT_MSK 0x0000007f
+#define PKTID_ALT_I_MSK 0xffffff80
+#define PKTID_ALT_SFT 0
+#define PKTID_ALT_HI 6
+#define PKTID_ALT_SZ 7
+#define HWID_ALT_MSK 0x00000780
+#define HWID_ALT_I_MSK 0xfffff87f
+#define HWID_ALT_SFT 7
+#define HWID_ALT_HI 10
+#define HWID_ALT_SZ 4
+#define CH2_INT_ADDR_ALT_MSK 0xffffffff
+#define CH2_INT_ADDR_ALT_I_MSK 0x00000000
+#define CH2_INT_ADDR_ALT_SFT 0
+#define CH2_INT_ADDR_ALT_HI 31
+#define CH2_INT_ADDR_ALT_SZ 32
+#define HALT_CH1_MSK 0x00000002
+#define HALT_CH1_I_MSK 0xfffffffd
+#define HALT_CH1_SFT 1
+#define HALT_CH1_HI 1
+#define HALT_CH1_SZ 1
+#define HALT_CH3_MSK 0x00000008
+#define HALT_CH3_I_MSK 0xfffffff7
+#define HALT_CH3_SFT 3
+#define HALT_CH3_HI 3
+#define HALT_CH3_SZ 1
+#define HALT_CH4_MSK 0x00000010
+#define HALT_CH4_I_MSK 0xffffffef
+#define HALT_CH4_SFT 4
+#define HALT_CH4_HI 4
+#define HALT_CH4_SZ 1
+#define HALT_CH5_MSK 0x00000020
+#define HALT_CH5_I_MSK 0xffffffdf
+#define HALT_CH5_SFT 5
+#define HALT_CH5_HI 5
+#define HALT_CH5_SZ 1
+#define HALT_CH6_MSK 0x00000040
+#define HALT_CH6_I_MSK 0xffffffbf
+#define HALT_CH6_SFT 6
+#define HALT_CH6_HI 6
+#define HALT_CH6_SZ 1
+#define HALT_CH7_MSK 0x00000080
+#define HALT_CH7_I_MSK 0xffffff7f
+#define HALT_CH7_SFT 7
+#define HALT_CH7_HI 7
+#define HALT_CH7_SZ 1
+#define HALT_CH8_MSK 0x00000100
+#define HALT_CH8_I_MSK 0xfffffeff
+#define HALT_CH8_SFT 8
+#define HALT_CH8_HI 8
+#define HALT_CH8_SZ 1
+#define HALT_CH9_MSK 0x00000200
+#define HALT_CH9_I_MSK 0xfffffdff
+#define HALT_CH9_SFT 9
+#define HALT_CH9_HI 9
+#define HALT_CH9_SZ 1
+#define HALT_CH10_MSK 0x00000400
+#define HALT_CH10_I_MSK 0xfffffbff
+#define HALT_CH10_SFT 10
+#define HALT_CH10_HI 10
+#define HALT_CH10_SZ 1
+#define HALT_CH11_MSK 0x00000800
+#define HALT_CH11_I_MSK 0xfffff7ff
+#define HALT_CH11_SFT 11
+#define HALT_CH11_HI 11
+#define HALT_CH11_SZ 1
+#define HALT_CH12_MSK 0x00001000
+#define HALT_CH12_I_MSK 0xffffefff
+#define HALT_CH12_SFT 12
+#define HALT_CH12_HI 12
+#define HALT_CH12_SZ 1
+#define HALT_CH13_MSK 0x00002000
+#define HALT_CH13_I_MSK 0xffffdfff
+#define HALT_CH13_SFT 13
+#define HALT_CH13_HI 13
+#define HALT_CH13_SZ 1
+#define HALT_CH14_MSK 0x00004000
+#define HALT_CH14_I_MSK 0xffffbfff
+#define HALT_CH14_SFT 14
+#define HALT_CH14_HI 14
+#define HALT_CH14_SZ 1
+#define STOP_MBOX_OUT_MSK 0x00010000
+#define STOP_MBOX_OUT_I_MSK 0xfffeffff
+#define STOP_MBOX_OUT_SFT 16
+#define STOP_MBOX_OUT_HI 16
+#define STOP_MBOX_OUT_SZ 1
+#define STOP_MBOX_IN_MSK 0x00020000
+#define STOP_MBOX_IN_I_MSK 0xfffdffff
+#define STOP_MBOX_IN_SFT 17
+#define STOP_MBOX_IN_HI 17
+#define STOP_MBOX_IN_SZ 1
+#define MB_ERR_AUTO_HALT_EN_MSK 0x00100000
+#define MB_ERR_AUTO_HALT_EN_I_MSK 0xffefffff
+#define MB_ERR_AUTO_HALT_EN_SFT 20
+#define MB_ERR_AUTO_HALT_EN_HI 20
+#define MB_ERR_AUTO_HALT_EN_SZ 1
+#define MB_EXCEPT_CLR_MSK 0x00200000
+#define MB_EXCEPT_CLR_I_MSK 0xffdfffff
+#define MB_EXCEPT_CLR_SFT 21
+#define MB_EXCEPT_CLR_HI 21
+#define MB_EXCEPT_CLR_SZ 1
+#define CH1_HALT_STS_MSK 0x00000002
+#define CH1_HALT_STS_I_MSK 0xfffffffd
+#define CH1_HALT_STS_SFT 1
+#define CH1_HALT_STS_HI 1
+#define CH1_HALT_STS_SZ 1
+#define CH3_HALT_STS_MSK 0x00000008
+#define CH3_HALT_STS_I_MSK 0xfffffff7
+#define CH3_HALT_STS_SFT 3
+#define CH3_HALT_STS_HI 3
+#define CH3_HALT_STS_SZ 1
+#define CH4_HALT_STS_MSK 0x00000010
+#define CH4_HALT_STS_I_MSK 0xffffffef
+#define CH4_HALT_STS_SFT 4
+#define CH4_HALT_STS_HI 4
+#define CH4_HALT_STS_SZ 1
+#define CH5_HALT_STS_MSK 0x00000020
+#define CH5_HALT_STS_I_MSK 0xffffffdf
+#define CH5_HALT_STS_SFT 5
+#define CH5_HALT_STS_HI 5
+#define CH5_HALT_STS_SZ 1
+#define CH6_HALT_STS_MSK 0x00000040
+#define CH6_HALT_STS_I_MSK 0xffffffbf
+#define CH6_HALT_STS_SFT 6
+#define CH6_HALT_STS_HI 6
+#define CH6_HALT_STS_SZ 1
+#define CH7_HALT_STS_MSK 0x00000080
+#define CH7_HALT_STS_I_MSK 0xffffff7f
+#define CH7_HALT_STS_SFT 7
+#define CH7_HALT_STS_HI 7
+#define CH7_HALT_STS_SZ 1
+#define CH8_HALT_STS_MSK 0x00000100
+#define CH8_HALT_STS_I_MSK 0xfffffeff
+#define CH8_HALT_STS_SFT 8
+#define CH8_HALT_STS_HI 8
+#define CH8_HALT_STS_SZ 1
+#define CH9_HALT_STS_MSK 0x00000200
+#define CH9_HALT_STS_I_MSK 0xfffffdff
+#define CH9_HALT_STS_SFT 9
+#define CH9_HALT_STS_HI 9
+#define CH9_HALT_STS_SZ 1
+#define CH10_HALT_STS_MSK 0x00000400
+#define CH10_HALT_STS_I_MSK 0xfffffbff
+#define CH10_HALT_STS_SFT 10
+#define CH10_HALT_STS_HI 10
+#define CH10_HALT_STS_SZ 1
+#define CH11_HALT_STS_MSK 0x00000800
+#define CH11_HALT_STS_I_MSK 0xfffff7ff
+#define CH11_HALT_STS_SFT 11
+#define CH11_HALT_STS_HI 11
+#define CH11_HALT_STS_SZ 1
+#define CH12_HALT_STS_MSK 0x00001000
+#define CH12_HALT_STS_I_MSK 0xffffefff
+#define CH12_HALT_STS_SFT 12
+#define CH12_HALT_STS_HI 12
+#define CH12_HALT_STS_SZ 1
+#define CH13_HALT_STS_MSK 0x00002000
+#define CH13_HALT_STS_I_MSK 0xffffdfff
+#define CH13_HALT_STS_SFT 13
+#define CH13_HALT_STS_HI 13
+#define CH13_HALT_STS_SZ 1
+#define CH14_HALT_STS_MSK 0x00004000
+#define CH14_HALT_STS_I_MSK 0xffffbfff
+#define CH14_HALT_STS_SFT 14
+#define CH14_HALT_STS_HI 14
+#define CH14_HALT_STS_SZ 1
+#define STOP_MBOX_OUT_SUCCESS_MSK 0x00010000
+#define STOP_MBOX_OUT_SUCCESS_I_MSK 0xfffeffff
+#define STOP_MBOX_OUT_SUCCESS_SFT 16
+#define STOP_MBOX_OUT_SUCCESS_HI 16
+#define STOP_MBOX_OUT_SUCCESS_SZ 1
+#define MB_EXCEPT_CASE_MSK 0xff000000
+#define MB_EXCEPT_CASE_I_MSK 0x00ffffff
+#define MB_EXCEPT_CASE_SFT 24
+#define MB_EXCEPT_CASE_HI 31
+#define MB_EXCEPT_CASE_SZ 8
+#define MB_DBG_TIME_STEP_MSK 0x0000ffff
+#define MB_DBG_TIME_STEP_I_MSK 0xffff0000
+#define MB_DBG_TIME_STEP_SFT 0
+#define MB_DBG_TIME_STEP_HI 15
+#define MB_DBG_TIME_STEP_SZ 16
+#define DBG_TYPE_MSK 0x00030000
+#define DBG_TYPE_I_MSK 0xfffcffff
+#define DBG_TYPE_SFT 16
+#define DBG_TYPE_HI 17
+#define DBG_TYPE_SZ 2
+#define MB_DBG_CLR_MSK 0x00040000
+#define MB_DBG_CLR_I_MSK 0xfffbffff
+#define MB_DBG_CLR_SFT 18
+#define MB_DBG_CLR_HI 18
+#define MB_DBG_CLR_SZ 1
+#define DBG_ALC_LOG_EN_MSK 0x00080000
+#define DBG_ALC_LOG_EN_I_MSK 0xfff7ffff
+#define DBG_ALC_LOG_EN_SFT 19
+#define DBG_ALC_LOG_EN_HI 19
+#define DBG_ALC_LOG_EN_SZ 1
+#define MB_DBG_COUNTER_EN_MSK 0x01000000
+#define MB_DBG_COUNTER_EN_I_MSK 0xfeffffff
+#define MB_DBG_COUNTER_EN_SFT 24
+#define MB_DBG_COUNTER_EN_HI 24
+#define MB_DBG_COUNTER_EN_SZ 1
+#define MB_DBG_EN_MSK 0x80000000
+#define MB_DBG_EN_I_MSK 0x7fffffff
+#define MB_DBG_EN_SFT 31
+#define MB_DBG_EN_HI 31
+#define MB_DBG_EN_SZ 1
+#define MB_DBG_RECORD_CNT_MSK 0x0000ffff
+#define MB_DBG_RECORD_CNT_I_MSK 0xffff0000
+#define MB_DBG_RECORD_CNT_SFT 0
+#define MB_DBG_RECORD_CNT_HI 15
+#define MB_DBG_RECORD_CNT_SZ 16
+#define MB_DBG_LENGTH_MSK 0xffff0000
+#define MB_DBG_LENGTH_I_MSK 0x0000ffff
+#define MB_DBG_LENGTH_SFT 16
+#define MB_DBG_LENGTH_HI 31
+#define MB_DBG_LENGTH_SZ 16
+#define MB_DBG_CFG_ADDR_MSK 0xffffffff
+#define MB_DBG_CFG_ADDR_I_MSK 0x00000000
+#define MB_DBG_CFG_ADDR_SFT 0
+#define MB_DBG_CFG_ADDR_HI 31
+#define MB_DBG_CFG_ADDR_SZ 32
+#define DBG_HWID0_WR_EN_MSK 0x00000001
+#define DBG_HWID0_WR_EN_I_MSK 0xfffffffe
+#define DBG_HWID0_WR_EN_SFT 0
+#define DBG_HWID0_WR_EN_HI 0
+#define DBG_HWID0_WR_EN_SZ 1
+#define DBG_HWID1_WR_EN_MSK 0x00000002
+#define DBG_HWID1_WR_EN_I_MSK 0xfffffffd
+#define DBG_HWID1_WR_EN_SFT 1
+#define DBG_HWID1_WR_EN_HI 1
+#define DBG_HWID1_WR_EN_SZ 1
+#define DBG_HWID2_WR_EN_MSK 0x00000004
+#define DBG_HWID2_WR_EN_I_MSK 0xfffffffb
+#define DBG_HWID2_WR_EN_SFT 2
+#define DBG_HWID2_WR_EN_HI 2
+#define DBG_HWID2_WR_EN_SZ 1
+#define DBG_HWID3_WR_EN_MSK 0x00000008
+#define DBG_HWID3_WR_EN_I_MSK 0xfffffff7
+#define DBG_HWID3_WR_EN_SFT 3
+#define DBG_HWID3_WR_EN_HI 3
+#define DBG_HWID3_WR_EN_SZ 1
+#define DBG_HWID4_WR_EN_MSK 0x00000010
+#define DBG_HWID4_WR_EN_I_MSK 0xffffffef
+#define DBG_HWID4_WR_EN_SFT 4
+#define DBG_HWID4_WR_EN_HI 4
+#define DBG_HWID4_WR_EN_SZ 1
+#define DBG_HWID5_WR_EN_MSK 0x00000020
+#define DBG_HWID5_WR_EN_I_MSK 0xffffffdf
+#define DBG_HWID5_WR_EN_SFT 5
+#define DBG_HWID5_WR_EN_HI 5
+#define DBG_HWID5_WR_EN_SZ 1
+#define DBG_HWID6_WR_EN_MSK 0x00000040
+#define DBG_HWID6_WR_EN_I_MSK 0xffffffbf
+#define DBG_HWID6_WR_EN_SFT 6
+#define DBG_HWID6_WR_EN_HI 6
+#define DBG_HWID6_WR_EN_SZ 1
+#define DBG_HWID7_WR_EN_MSK 0x00000080
+#define DBG_HWID7_WR_EN_I_MSK 0xffffff7f
+#define DBG_HWID7_WR_EN_SFT 7
+#define DBG_HWID7_WR_EN_HI 7
+#define DBG_HWID7_WR_EN_SZ 1
+#define DBG_HWID8_WR_EN_MSK 0x00000100
+#define DBG_HWID8_WR_EN_I_MSK 0xfffffeff
+#define DBG_HWID8_WR_EN_SFT 8
+#define DBG_HWID8_WR_EN_HI 8
+#define DBG_HWID8_WR_EN_SZ 1
+#define DBG_HWID9_WR_EN_MSK 0x00000200
+#define DBG_HWID9_WR_EN_I_MSK 0xfffffdff
+#define DBG_HWID9_WR_EN_SFT 9
+#define DBG_HWID9_WR_EN_HI 9
+#define DBG_HWID9_WR_EN_SZ 1
+#define DBG_HWID10_WR_EN_MSK 0x00000400
+#define DBG_HWID10_WR_EN_I_MSK 0xfffffbff
+#define DBG_HWID10_WR_EN_SFT 10
+#define DBG_HWID10_WR_EN_HI 10
+#define DBG_HWID10_WR_EN_SZ 1
+#define DBG_HWID11_WR_EN_MSK 0x00000800
+#define DBG_HWID11_WR_EN_I_MSK 0xfffff7ff
+#define DBG_HWID11_WR_EN_SFT 11
+#define DBG_HWID11_WR_EN_HI 11
+#define DBG_HWID11_WR_EN_SZ 1
+#define DBG_HWID12_WR_EN_MSK 0x00001000
+#define DBG_HWID12_WR_EN_I_MSK 0xffffefff
+#define DBG_HWID12_WR_EN_SFT 12
+#define DBG_HWID12_WR_EN_HI 12
+#define DBG_HWID12_WR_EN_SZ 1
+#define DBG_HWID13_WR_EN_MSK 0x00002000
+#define DBG_HWID13_WR_EN_I_MSK 0xffffdfff
+#define DBG_HWID13_WR_EN_SFT 13
+#define DBG_HWID13_WR_EN_HI 13
+#define DBG_HWID13_WR_EN_SZ 1
+#define DBG_HWID14_WR_EN_MSK 0x00004000
+#define DBG_HWID14_WR_EN_I_MSK 0xffffbfff
+#define DBG_HWID14_WR_EN_SFT 14
+#define DBG_HWID14_WR_EN_HI 14
+#define DBG_HWID14_WR_EN_SZ 1
+#define DBG_HWID15_WR_EN_MSK 0x00008000
+#define DBG_HWID15_WR_EN_I_MSK 0xffff7fff
+#define DBG_HWID15_WR_EN_SFT 15
+#define DBG_HWID15_WR_EN_HI 15
+#define DBG_HWID15_WR_EN_SZ 1
+#define DBG_HWID0_RD_EN_MSK 0x00010000
+#define DBG_HWID0_RD_EN_I_MSK 0xfffeffff
+#define DBG_HWID0_RD_EN_SFT 16
+#define DBG_HWID0_RD_EN_HI 16
+#define DBG_HWID0_RD_EN_SZ 1
+#define DBG_HWID1_RD_EN_MSK 0x00020000
+#define DBG_HWID1_RD_EN_I_MSK 0xfffdffff
+#define DBG_HWID1_RD_EN_SFT 17
+#define DBG_HWID1_RD_EN_HI 17
+#define DBG_HWID1_RD_EN_SZ 1
+#define DBG_HWID2_RD_EN_MSK 0x00040000
+#define DBG_HWID2_RD_EN_I_MSK 0xfffbffff
+#define DBG_HWID2_RD_EN_SFT 18
+#define DBG_HWID2_RD_EN_HI 18
+#define DBG_HWID2_RD_EN_SZ 1
+#define DBG_HWID3_RD_EN_MSK 0x00080000
+#define DBG_HWID3_RD_EN_I_MSK 0xfff7ffff
+#define DBG_HWID3_RD_EN_SFT 19
+#define DBG_HWID3_RD_EN_HI 19
+#define DBG_HWID3_RD_EN_SZ 1
+#define DBG_HWID4_RD_EN_MSK 0x00100000
+#define DBG_HWID4_RD_EN_I_MSK 0xffefffff
+#define DBG_HWID4_RD_EN_SFT 20
+#define DBG_HWID4_RD_EN_HI 20
+#define DBG_HWID4_RD_EN_SZ 1
+#define DBG_HWID5_RD_EN_MSK 0x00200000
+#define DBG_HWID5_RD_EN_I_MSK 0xffdfffff
+#define DBG_HWID5_RD_EN_SFT 21
+#define DBG_HWID5_RD_EN_HI 21
+#define DBG_HWID5_RD_EN_SZ 1
+#define DBG_HWID6_RD_EN_MSK 0x00400000
+#define DBG_HWID6_RD_EN_I_MSK 0xffbfffff
+#define DBG_HWID6_RD_EN_SFT 22
+#define DBG_HWID6_RD_EN_HI 22
+#define DBG_HWID6_RD_EN_SZ 1
+#define DBG_HWID7_RD_EN_MSK 0x00800000
+#define DBG_HWID7_RD_EN_I_MSK 0xff7fffff
+#define DBG_HWID7_RD_EN_SFT 23
+#define DBG_HWID7_RD_EN_HI 23
+#define DBG_HWID7_RD_EN_SZ 1
+#define DBG_HWID8_RD_EN_MSK 0x01000000
+#define DBG_HWID8_RD_EN_I_MSK 0xfeffffff
+#define DBG_HWID8_RD_EN_SFT 24
+#define DBG_HWID8_RD_EN_HI 24
+#define DBG_HWID8_RD_EN_SZ 1
+#define DBG_HWID9_RD_EN_MSK 0x02000000
+#define DBG_HWID9_RD_EN_I_MSK 0xfdffffff
+#define DBG_HWID9_RD_EN_SFT 25
+#define DBG_HWID9_RD_EN_HI 25
+#define DBG_HWID9_RD_EN_SZ 1
+#define DBG_HWID10_RD_EN_MSK 0x04000000
+#define DBG_HWID10_RD_EN_I_MSK 0xfbffffff
+#define DBG_HWID10_RD_EN_SFT 26
+#define DBG_HWID10_RD_EN_HI 26
+#define DBG_HWID10_RD_EN_SZ 1
+#define DBG_HWID11_RD_EN_MSK 0x08000000
+#define DBG_HWID11_RD_EN_I_MSK 0xf7ffffff
+#define DBG_HWID11_RD_EN_SFT 27
+#define DBG_HWID11_RD_EN_HI 27
+#define DBG_HWID11_RD_EN_SZ 1
+#define DBG_HWID12_RD_EN_MSK 0x10000000
+#define DBG_HWID12_RD_EN_I_MSK 0xefffffff
+#define DBG_HWID12_RD_EN_SFT 28
+#define DBG_HWID12_RD_EN_HI 28
+#define DBG_HWID12_RD_EN_SZ 1
+#define DBG_HWID13_RD_EN_MSK 0x20000000
+#define DBG_HWID13_RD_EN_I_MSK 0xdfffffff
+#define DBG_HWID13_RD_EN_SFT 29
+#define DBG_HWID13_RD_EN_HI 29
+#define DBG_HWID13_RD_EN_SZ 1
+#define DBG_HWID14_RD_EN_MSK 0x40000000
+#define DBG_HWID14_RD_EN_I_MSK 0xbfffffff
+#define DBG_HWID14_RD_EN_SFT 30
+#define DBG_HWID14_RD_EN_HI 30
+#define DBG_HWID14_RD_EN_SZ 1
+#define DBG_HWID15_RD_EN_MSK 0x80000000
+#define DBG_HWID15_RD_EN_I_MSK 0x7fffffff
+#define DBG_HWID15_RD_EN_SFT 31
+#define DBG_HWID15_RD_EN_HI 31
+#define DBG_HWID15_RD_EN_SZ 1
+#define MB_OUT_QUEUE_EN_MSK 0x00000002
+#define MB_OUT_QUEUE_EN_I_MSK 0xfffffffd
+#define MB_OUT_QUEUE_EN_SFT 1
+#define MB_OUT_QUEUE_EN_HI 1
+#define MB_OUT_QUEUE_EN_SZ 1
+#define OUT_QUEUE_FLUSH_ID_MSK 0x0000007f
+#define OUT_QUEUE_FLUSH_ID_I_MSK 0xffffff80
+#define OUT_QUEUE_FLUSH_ID_SFT 0
+#define OUT_QUEUE_FLUSH_ID_HI 6
+#define OUT_QUEUE_FLUSH_ID_SZ 7
+#define OUT_QUEUE_FLUSH_MODE_MSK 0x00000003
+#define OUT_QUEUE_FLUSH_MODE_I_MSK 0xfffffffc
+#define OUT_QUEUE_FLUSH_MODE_SFT 0
+#define OUT_QUEUE_FLUSH_MODE_HI 1
+#define OUT_QUEUE_FLUSH_MODE_SZ 2
+#define OUT_QUEUE_FLUSH_SEL_MSK 0x00000f00
+#define OUT_QUEUE_FLUSH_SEL_I_MSK 0xfffff0ff
+#define OUT_QUEUE_FLUSH_SEL_SFT 8
+#define OUT_QUEUE_FLUSH_SEL_HI 11
+#define OUT_QUEUE_FLUSH_SEL_SZ 4
+#define FFO0_CNT_MSK 0x0000001f
+#define FFO0_CNT_I_MSK 0xffffffe0
+#define FFO0_CNT_SFT 0
+#define FFO0_CNT_HI 4
+#define FFO0_CNT_SZ 5
+#define FFO1_CNT_MSK 0x000003e0
+#define FFO1_CNT_I_MSK 0xfffffc1f
+#define FFO1_CNT_SFT 5
+#define FFO1_CNT_HI 9
+#define FFO1_CNT_SZ 5
+#define FFO2_CNT_MSK 0x00003c00
+#define FFO2_CNT_I_MSK 0xffffc3ff
+#define FFO2_CNT_SFT 10
+#define FFO2_CNT_HI 13
+#define FFO2_CNT_SZ 4
+#define FFO3_CNT_MSK 0x000f8000
+#define FFO3_CNT_I_MSK 0xfff07fff
+#define FFO3_CNT_SFT 15
+#define FFO3_CNT_HI 19
+#define FFO3_CNT_SZ 5
+#define FFO4_CNT_MSK 0x00300000
+#define FFO4_CNT_I_MSK 0xffcfffff
+#define FFO4_CNT_SFT 20
+#define FFO4_CNT_HI 21
+#define FFO4_CNT_SZ 2
+#define FFO5_CNT_MSK 0x0e000000
+#define FFO5_CNT_I_MSK 0xf1ffffff
+#define FFO5_CNT_SFT 25
+#define FFO5_CNT_HI 27
+#define FFO5_CNT_SZ 3
+#define FFO6_CNT_MSK 0x0000000f
+#define FFO6_CNT_I_MSK 0xfffffff0
+#define FFO6_CNT_SFT 0
+#define FFO6_CNT_HI 3
+#define FFO6_CNT_SZ 4
+#define FFO7_CNT_MSK 0x000003e0
+#define FFO7_CNT_I_MSK 0xfffffc1f
+#define FFO7_CNT_SFT 5
+#define FFO7_CNT_HI 9
+#define FFO7_CNT_SZ 5
+#define FFO8_CNT_MSK 0x00007c00
+#define FFO8_CNT_I_MSK 0xffff83ff
+#define FFO8_CNT_SFT 10
+#define FFO8_CNT_HI 14
+#define FFO8_CNT_SZ 5
+#define FFO9_CNT_MSK 0x000f8000
+#define FFO9_CNT_I_MSK 0xfff07fff
+#define FFO9_CNT_SFT 15
+#define FFO9_CNT_HI 19
+#define FFO9_CNT_SZ 5
+#define FFO10_CNT_MSK 0x00f00000
+#define FFO10_CNT_I_MSK 0xff0fffff
+#define FFO10_CNT_SFT 20
+#define FFO10_CNT_HI 23
+#define FFO10_CNT_SZ 4
+#define FFO11_CNT_MSK 0x3e000000
+#define FFO11_CNT_I_MSK 0xc1ffffff
+#define FFO11_CNT_SFT 25
+#define FFO11_CNT_HI 29
+#define FFO11_CNT_SZ 5
+#define FFO12_CNT_MSK 0x00000007
+#define FFO12_CNT_I_MSK 0xfffffff8
+#define FFO12_CNT_SFT 0
+#define FFO12_CNT_HI 2
+#define FFO12_CNT_SZ 3
+#define FFO13_CNT_MSK 0x00000060
+#define FFO13_CNT_I_MSK 0xffffff9f
+#define FFO13_CNT_SFT 5
+#define FFO13_CNT_HI 6
+#define FFO13_CNT_SZ 2
+#define FFO14_CNT_MSK 0x00007c00
+#define FFO14_CNT_I_MSK 0xffff83ff
+#define FFO14_CNT_SFT 10
+#define FFO14_CNT_HI 14
+#define FFO14_CNT_SZ 5
+#define FFO15_CNT_MSK 0x00078000
+#define FFO15_CNT_I_MSK 0xfff87fff
+#define FFO15_CNT_SFT 15
+#define FFO15_CNT_HI 18
+#define FFO15_CNT_SZ 4
+#define CH0_FFO_FULL_MSK 0x00000001
+#define CH0_FFO_FULL_I_MSK 0xfffffffe
+#define CH0_FFO_FULL_SFT 0
+#define CH0_FFO_FULL_HI 0
+#define CH0_FFO_FULL_SZ 1
+#define CH1_FFO_FULL_MSK 0x00000002
+#define CH1_FFO_FULL_I_MSK 0xfffffffd
+#define CH1_FFO_FULL_SFT 1
+#define CH1_FFO_FULL_HI 1
+#define CH1_FFO_FULL_SZ 1
+#define CH2_FFO_FULL_MSK 0x00000004
+#define CH2_FFO_FULL_I_MSK 0xfffffffb
+#define CH2_FFO_FULL_SFT 2
+#define CH2_FFO_FULL_HI 2
+#define CH2_FFO_FULL_SZ 1
+#define CH3_FFO_FULL_MSK 0x00000008
+#define CH3_FFO_FULL_I_MSK 0xfffffff7
+#define CH3_FFO_FULL_SFT 3
+#define CH3_FFO_FULL_HI 3
+#define CH3_FFO_FULL_SZ 1
+#define CH4_FFO_FULL_MSK 0x00000010
+#define CH4_FFO_FULL_I_MSK 0xffffffef
+#define CH4_FFO_FULL_SFT 4
+#define CH4_FFO_FULL_HI 4
+#define CH4_FFO_FULL_SZ 1
+#define CH5_FFO_FULL_MSK 0x00000020
+#define CH5_FFO_FULL_I_MSK 0xffffffdf
+#define CH5_FFO_FULL_SFT 5
+#define CH5_FFO_FULL_HI 5
+#define CH5_FFO_FULL_SZ 1
+#define CH6_FFO_FULL_MSK 0x00000040
+#define CH6_FFO_FULL_I_MSK 0xffffffbf
+#define CH6_FFO_FULL_SFT 6
+#define CH6_FFO_FULL_HI 6
+#define CH6_FFO_FULL_SZ 1
+#define CH7_FFO_FULL_MSK 0x00000080
+#define CH7_FFO_FULL_I_MSK 0xffffff7f
+#define CH7_FFO_FULL_SFT 7
+#define CH7_FFO_FULL_HI 7
+#define CH7_FFO_FULL_SZ 1
+#define CH8_FFO_FULL_MSK 0x00000100
+#define CH8_FFO_FULL_I_MSK 0xfffffeff
+#define CH8_FFO_FULL_SFT 8
+#define CH8_FFO_FULL_HI 8
+#define CH8_FFO_FULL_SZ 1
+#define CH9_FFO_FULL_MSK 0x00000200
+#define CH9_FFO_FULL_I_MSK 0xfffffdff
+#define CH9_FFO_FULL_SFT 9
+#define CH9_FFO_FULL_HI 9
+#define CH9_FFO_FULL_SZ 1
+#define CH10_FFO_FULL_MSK 0x00000400
+#define CH10_FFO_FULL_I_MSK 0xfffffbff
+#define CH10_FFO_FULL_SFT 10
+#define CH10_FFO_FULL_HI 10
+#define CH10_FFO_FULL_SZ 1
+#define CH11_FFO_FULL_MSK 0x00000800
+#define CH11_FFO_FULL_I_MSK 0xfffff7ff
+#define CH11_FFO_FULL_SFT 11
+#define CH11_FFO_FULL_HI 11
+#define CH11_FFO_FULL_SZ 1
+#define CH12_FFO_FULL_MSK 0x00001000
+#define CH12_FFO_FULL_I_MSK 0xffffefff
+#define CH12_FFO_FULL_SFT 12
+#define CH12_FFO_FULL_HI 12
+#define CH12_FFO_FULL_SZ 1
+#define CH13_FFO_FULL_MSK 0x00002000
+#define CH13_FFO_FULL_I_MSK 0xffffdfff
+#define CH13_FFO_FULL_SFT 13
+#define CH13_FFO_FULL_HI 13
+#define CH13_FFO_FULL_SZ 1
+#define CH14_FFO_FULL_MSK 0x00004000
+#define CH14_FFO_FULL_I_MSK 0xffffbfff
+#define CH14_FFO_FULL_SFT 14
+#define CH14_FFO_FULL_HI 14
+#define CH14_FFO_FULL_SZ 1
+#define CH15_FFO_FULL_MSK 0x00008000
+#define CH15_FFO_FULL_I_MSK 0xffff7fff
+#define CH15_FFO_FULL_SFT 15
+#define CH15_FFO_FULL_HI 15
+#define CH15_FFO_FULL_SZ 1
+#define CH0_LOWTHOLD_INT_MSK 0x00000001
+#define CH0_LOWTHOLD_INT_I_MSK 0xfffffffe
+#define CH0_LOWTHOLD_INT_SFT 0
+#define CH0_LOWTHOLD_INT_HI 0
+#define CH0_LOWTHOLD_INT_SZ 1
+#define CH1_LOWTHOLD_INT_MSK 0x00000002
+#define CH1_LOWTHOLD_INT_I_MSK 0xfffffffd
+#define CH1_LOWTHOLD_INT_SFT 1
+#define CH1_LOWTHOLD_INT_HI 1
+#define CH1_LOWTHOLD_INT_SZ 1
+#define CH2_LOWTHOLD_INT_MSK 0x00000004
+#define CH2_LOWTHOLD_INT_I_MSK 0xfffffffb
+#define CH2_LOWTHOLD_INT_SFT 2
+#define CH2_LOWTHOLD_INT_HI 2
+#define CH2_LOWTHOLD_INT_SZ 1
+#define CH3_LOWTHOLD_INT_MSK 0x00000008
+#define CH3_LOWTHOLD_INT_I_MSK 0xfffffff7
+#define CH3_LOWTHOLD_INT_SFT 3
+#define CH3_LOWTHOLD_INT_HI 3
+#define CH3_LOWTHOLD_INT_SZ 1
+#define CH4_LOWTHOLD_INT_MSK 0x00000010
+#define CH4_LOWTHOLD_INT_I_MSK 0xffffffef
+#define CH4_LOWTHOLD_INT_SFT 4
+#define CH4_LOWTHOLD_INT_HI 4
+#define CH4_LOWTHOLD_INT_SZ 1
+#define CH5_LOWTHOLD_INT_MSK 0x00000020
+#define CH5_LOWTHOLD_INT_I_MSK 0xffffffdf
+#define CH5_LOWTHOLD_INT_SFT 5
+#define CH5_LOWTHOLD_INT_HI 5
+#define CH5_LOWTHOLD_INT_SZ 1
+#define CH6_LOWTHOLD_INT_MSK 0x00000040
+#define CH6_LOWTHOLD_INT_I_MSK 0xffffffbf
+#define CH6_LOWTHOLD_INT_SFT 6
+#define CH6_LOWTHOLD_INT_HI 6
+#define CH6_LOWTHOLD_INT_SZ 1
+#define CH7_LOWTHOLD_INT_MSK 0x00000080
+#define CH7_LOWTHOLD_INT_I_MSK 0xffffff7f
+#define CH7_LOWTHOLD_INT_SFT 7
+#define CH7_LOWTHOLD_INT_HI 7
+#define CH7_LOWTHOLD_INT_SZ 1
+#define CH8_LOWTHOLD_INT_MSK 0x00000100
+#define CH8_LOWTHOLD_INT_I_MSK 0xfffffeff
+#define CH8_LOWTHOLD_INT_SFT 8
+#define CH8_LOWTHOLD_INT_HI 8
+#define CH8_LOWTHOLD_INT_SZ 1
+#define CH9_LOWTHOLD_INT_MSK 0x00000200
+#define CH9_LOWTHOLD_INT_I_MSK 0xfffffdff
+#define CH9_LOWTHOLD_INT_SFT 9
+#define CH9_LOWTHOLD_INT_HI 9
+#define CH9_LOWTHOLD_INT_SZ 1
+#define CH10_LOWTHOLD_INT_MSK 0x00000400
+#define CH10_LOWTHOLD_INT_I_MSK 0xfffffbff
+#define CH10_LOWTHOLD_INT_SFT 10
+#define CH10_LOWTHOLD_INT_HI 10
+#define CH10_LOWTHOLD_INT_SZ 1
+#define CH11_LOWTHOLD_INT_MSK 0x00000800
+#define CH11_LOWTHOLD_INT_I_MSK 0xfffff7ff
+#define CH11_LOWTHOLD_INT_SFT 11
+#define CH11_LOWTHOLD_INT_HI 11
+#define CH11_LOWTHOLD_INT_SZ 1
+#define CH12_LOWTHOLD_INT_MSK 0x00001000
+#define CH12_LOWTHOLD_INT_I_MSK 0xffffefff
+#define CH12_LOWTHOLD_INT_SFT 12
+#define CH12_LOWTHOLD_INT_HI 12
+#define CH12_LOWTHOLD_INT_SZ 1
+#define CH13_LOWTHOLD_INT_MSK 0x00002000
+#define CH13_LOWTHOLD_INT_I_MSK 0xffffdfff
+#define CH13_LOWTHOLD_INT_SFT 13
+#define CH13_LOWTHOLD_INT_HI 13
+#define CH13_LOWTHOLD_INT_SZ 1
+#define CH14_LOWTHOLD_INT_MSK 0x00004000
+#define CH14_LOWTHOLD_INT_I_MSK 0xffffbfff
+#define CH14_LOWTHOLD_INT_SFT 14
+#define CH14_LOWTHOLD_INT_HI 14
+#define CH14_LOWTHOLD_INT_SZ 1
+#define CH15_LOWTHOLD_INT_MSK 0x00008000
+#define CH15_LOWTHOLD_INT_I_MSK 0xffff7fff
+#define CH15_LOWTHOLD_INT_SFT 15
+#define CH15_LOWTHOLD_INT_HI 15
+#define CH15_LOWTHOLD_INT_SZ 1
+#define MB_LOW_THOLD_EN_MSK 0x80000000
+#define MB_LOW_THOLD_EN_I_MSK 0x7fffffff
+#define MB_LOW_THOLD_EN_SFT 31
+#define MB_LOW_THOLD_EN_HI 31
+#define MB_LOW_THOLD_EN_SZ 1
+#define CH0_LOWTHOLD_MSK 0x0000001f
+#define CH0_LOWTHOLD_I_MSK 0xffffffe0
+#define CH0_LOWTHOLD_SFT 0
+#define CH0_LOWTHOLD_HI 4
+#define CH0_LOWTHOLD_SZ 5
+#define CH1_LOWTHOLD_MSK 0x00001f00
+#define CH1_LOWTHOLD_I_MSK 0xffffe0ff
+#define CH1_LOWTHOLD_SFT 8
+#define CH1_LOWTHOLD_HI 12
+#define CH1_LOWTHOLD_SZ 5
+#define CH2_LOWTHOLD_MSK 0x001f0000
+#define CH2_LOWTHOLD_I_MSK 0xffe0ffff
+#define CH2_LOWTHOLD_SFT 16
+#define CH2_LOWTHOLD_HI 20
+#define CH2_LOWTHOLD_SZ 5
+#define CH3_LOWTHOLD_MSK 0x1f000000
+#define CH3_LOWTHOLD_I_MSK 0xe0ffffff
+#define CH3_LOWTHOLD_SFT 24
+#define CH3_LOWTHOLD_HI 28
+#define CH3_LOWTHOLD_SZ 5
+#define CH4_LOWTHOLD_MSK 0x0000001f
+#define CH4_LOWTHOLD_I_MSK 0xffffffe0
+#define CH4_LOWTHOLD_SFT 0
+#define CH4_LOWTHOLD_HI 4
+#define CH4_LOWTHOLD_SZ 5
+#define CH5_LOWTHOLD_MSK 0x00001f00
+#define CH5_LOWTHOLD_I_MSK 0xffffe0ff
+#define CH5_LOWTHOLD_SFT 8
+#define CH5_LOWTHOLD_HI 12
+#define CH5_LOWTHOLD_SZ 5
+#define CH6_LOWTHOLD_MSK 0x001f0000
+#define CH6_LOWTHOLD_I_MSK 0xffe0ffff
+#define CH6_LOWTHOLD_SFT 16
+#define CH6_LOWTHOLD_HI 20
+#define CH6_LOWTHOLD_SZ 5
+#define CH7_LOWTHOLD_MSK 0x1f000000
+#define CH7_LOWTHOLD_I_MSK 0xe0ffffff
+#define CH7_LOWTHOLD_SFT 24
+#define CH7_LOWTHOLD_HI 28
+#define CH7_LOWTHOLD_SZ 5
+#define CH8_LOWTHOLD_MSK 0x0000001f
+#define CH8_LOWTHOLD_I_MSK 0xffffffe0
+#define CH8_LOWTHOLD_SFT 0
+#define CH8_LOWTHOLD_HI 4
+#define CH8_LOWTHOLD_SZ 5
+#define CH9_LOWTHOLD_MSK 0x00001f00
+#define CH9_LOWTHOLD_I_MSK 0xffffe0ff
+#define CH9_LOWTHOLD_SFT 8
+#define CH9_LOWTHOLD_HI 12
+#define CH9_LOWTHOLD_SZ 5
+#define CH10_LOWTHOLD_MSK 0x001f0000
+#define CH10_LOWTHOLD_I_MSK 0xffe0ffff
+#define CH10_LOWTHOLD_SFT 16
+#define CH10_LOWTHOLD_HI 20
+#define CH10_LOWTHOLD_SZ 5
+#define CH11_LOWTHOLD_MSK 0x1f000000
+#define CH11_LOWTHOLD_I_MSK 0xe0ffffff
+#define CH11_LOWTHOLD_SFT 24
+#define CH11_LOWTHOLD_HI 28
+#define CH11_LOWTHOLD_SZ 5
+#define CH12_LOWTHOLD_MSK 0x0000001f
+#define CH12_LOWTHOLD_I_MSK 0xffffffe0
+#define CH12_LOWTHOLD_SFT 0
+#define CH12_LOWTHOLD_HI 4
+#define CH12_LOWTHOLD_SZ 5
+#define CH13_LOWTHOLD_MSK 0x00001f00
+#define CH13_LOWTHOLD_I_MSK 0xffffe0ff
+#define CH13_LOWTHOLD_SFT 8
+#define CH13_LOWTHOLD_HI 12
+#define CH13_LOWTHOLD_SZ 5
+#define CH14_LOWTHOLD_MSK 0x001f0000
+#define CH14_LOWTHOLD_I_MSK 0xffe0ffff
+#define CH14_LOWTHOLD_SFT 16
+#define CH14_LOWTHOLD_HI 20
+#define CH14_LOWTHOLD_SZ 5
+#define CH15_LOWTHOLD_MSK 0x1f000000
+#define CH15_LOWTHOLD_I_MSK 0xe0ffffff
+#define CH15_LOWTHOLD_SFT 24
+#define CH15_LOWTHOLD_HI 28
+#define CH15_LOWTHOLD_SZ 5
+#define TRASH_TIMEOUT_EN_MSK 0x00000001
+#define TRASH_TIMEOUT_EN_I_MSK 0xfffffffe
+#define TRASH_TIMEOUT_EN_SFT 0
+#define TRASH_TIMEOUT_EN_HI 0
+#define TRASH_TIMEOUT_EN_SZ 1
+#define TRASH_CAN_INT_MSK 0x00000002
+#define TRASH_CAN_INT_I_MSK 0xfffffffd
+#define TRASH_CAN_INT_SFT 1
+#define TRASH_CAN_INT_HI 1
+#define TRASH_CAN_INT_SZ 1
+#define TRASH_INT_ID_MSK 0x000007f0
+#define TRASH_INT_ID_I_MSK 0xfffff80f
+#define TRASH_INT_ID_SFT 4
+#define TRASH_INT_ID_HI 10
+#define TRASH_INT_ID_SZ 7
+#define TRASH_TIMEOUT_MSK 0x03ff0000
+#define TRASH_TIMEOUT_I_MSK 0xfc00ffff
+#define TRASH_TIMEOUT_SFT 16
+#define TRASH_TIMEOUT_HI 25
+#define TRASH_TIMEOUT_SZ 10
+#define IN_FIFO_FLUSH_ID_MSK 0x000007ff
+#define IN_FIFO_FLUSH_ID_I_MSK 0xfffff800
+#define IN_FIFO_FLUSH_ID_SFT 0
+#define IN_FIFO_FLUSH_ID_HI 10
+#define IN_FIFO_FLUSH_ID_SZ 11
+#define IN_FIFO_FLUSH_MODE_MSK 0x00000003
+#define IN_FIFO_FLUSH_MODE_I_MSK 0xfffffffc
+#define IN_FIFO_FLUSH_MODE_SFT 0
+#define IN_FIFO_FLUSH_MODE_HI 1
+#define IN_FIFO_FLUSH_MODE_SZ 2
+#define IN_FIFO_FLUSH_SEL_MSK 0x00000f00
+#define IN_FIFO_FLUSH_SEL_I_MSK 0xfffff0ff
+#define IN_FIFO_FLUSH_SEL_SFT 8
+#define IN_FIFO_FLUSH_SEL_HI 11
+#define IN_FIFO_FLUSH_SEL_SZ 4
+#define CPU_ID_TB2_MSK 0xffffffff
+#define CPU_ID_TB2_I_MSK 0x00000000
+#define CPU_ID_TB2_SFT 0
+#define CPU_ID_TB2_HI 31
+#define CPU_ID_TB2_SZ 32
+#define CPU_ID_TB3_MSK 0xffffffff
+#define CPU_ID_TB3_I_MSK 0x00000000
+#define CPU_ID_TB3_SFT 0
+#define CPU_ID_TB3_HI 31
+#define CPU_ID_TB3_SZ 32
+#define IQ_LOG_EN_MSK 0x00000001
+#define IQ_LOG_EN_I_MSK 0xfffffffe
+#define IQ_LOG_EN_SFT 0
+#define IQ_LOG_EN_HI 0
+#define IQ_LOG_EN_SZ 1
+#define IQ_LOG_STOP_MODE_MSK 0x00000001
+#define IQ_LOG_STOP_MODE_I_MSK 0xfffffffe
+#define IQ_LOG_STOP_MODE_SFT 0
+#define IQ_LOG_STOP_MODE_HI 0
+#define IQ_LOG_STOP_MODE_SZ 1
+#define IQ_LOG_TIMER_MSK 0xffff0000
+#define IQ_LOG_TIMER_I_MSK 0x0000ffff
+#define IQ_LOG_TIMER_SFT 16
+#define IQ_LOG_TIMER_HI 31
+#define IQ_LOG_TIMER_SZ 16
+#define IQ_LOG_LEN_MSK 0x0000ffff
+#define IQ_LOG_LEN_I_MSK 0xffff0000
+#define IQ_LOG_LEN_SFT 0
+#define IQ_LOG_LEN_HI 15
+#define IQ_LOG_LEN_SZ 16
+#define IQ_LOG_ST_ADR_MSK 0xffff0000
+#define IQ_LOG_ST_ADR_I_MSK 0x0000ffff
+#define IQ_LOG_ST_ADR_SFT 16
+#define IQ_LOG_ST_ADR_HI 31
+#define IQ_LOG_ST_ADR_SZ 16
+#define IQ_LOG_TAIL_ADR_MSK 0x0000ffff
+#define IQ_LOG_TAIL_ADR_I_MSK 0xffff0000
+#define IQ_LOG_TAIL_ADR_SFT 0
+#define IQ_LOG_TAIL_ADR_HI 15
+#define IQ_LOG_TAIL_ADR_SZ 16
+#define ALC_LENG_MSK 0x0003ffff
+#define ALC_LENG_I_MSK 0xfffc0000
+#define ALC_LENG_SFT 0
+#define ALC_LENG_HI 17
+#define ALC_LENG_SZ 18
+#define CH0_DYN_PRI_MSK 0x00300000
+#define CH0_DYN_PRI_I_MSK 0xffcfffff
+#define CH0_DYN_PRI_SFT 20
+#define CH0_DYN_PRI_HI 21
+#define CH0_DYN_PRI_SZ 2
+#define MCU_PKTID_MSK 0xffffffff
+#define MCU_PKTID_I_MSK 0x00000000
+#define MCU_PKTID_SFT 0
+#define MCU_PKTID_HI 31
+#define MCU_PKTID_SZ 32
+#define CH0_STA_PRI_MSK 0x00000003
+#define CH0_STA_PRI_I_MSK 0xfffffffc
+#define CH0_STA_PRI_SFT 0
+#define CH0_STA_PRI_HI 1
+#define CH0_STA_PRI_SZ 2
+#define CH1_STA_PRI_MSK 0x00000030
+#define CH1_STA_PRI_I_MSK 0xffffffcf
+#define CH1_STA_PRI_SFT 4
+#define CH1_STA_PRI_HI 5
+#define CH1_STA_PRI_SZ 2
+#define CH2_STA_PRI_MSK 0x00000300
+#define CH2_STA_PRI_I_MSK 0xfffffcff
+#define CH2_STA_PRI_SFT 8
+#define CH2_STA_PRI_HI 9
+#define CH2_STA_PRI_SZ 2
+#define CH3_STA_PRI_MSK 0x00003000
+#define CH3_STA_PRI_I_MSK 0xffffcfff
+#define CH3_STA_PRI_SFT 12
+#define CH3_STA_PRI_HI 13
+#define CH3_STA_PRI_SZ 2
+#define ID_TB0_MSK 0xffffffff
+#define ID_TB0_I_MSK 0x00000000
+#define ID_TB0_SFT 0
+#define ID_TB0_HI 31
+#define ID_TB0_SZ 32
+#define ID_TB1_MSK 0xffffffff
+#define ID_TB1_I_MSK 0x00000000
+#define ID_TB1_SFT 0
+#define ID_TB1_HI 31
+#define ID_TB1_SZ 32
+#define ID_MNG_HALT_MSK 0x00000010
+#define ID_MNG_HALT_I_MSK 0xffffffef
+#define ID_MNG_HALT_SFT 4
+#define ID_MNG_HALT_HI 4
+#define ID_MNG_HALT_SZ 1
+#define ID_MNG_ERR_HALT_EN_MSK 0x00000020
+#define ID_MNG_ERR_HALT_EN_I_MSK 0xffffffdf
+#define ID_MNG_ERR_HALT_EN_SFT 5
+#define ID_MNG_ERR_HALT_EN_HI 5
+#define ID_MNG_ERR_HALT_EN_SZ 1
+#define ID_EXCEPT_FLG_CLR_MSK 0x00000040
+#define ID_EXCEPT_FLG_CLR_I_MSK 0xffffffbf
+#define ID_EXCEPT_FLG_CLR_SFT 6
+#define ID_EXCEPT_FLG_CLR_HI 6
+#define ID_EXCEPT_FLG_CLR_SZ 1
+#define ID_EXCEPT_FLG_MSK 0x00000080
+#define ID_EXCEPT_FLG_I_MSK 0xffffff7f
+#define ID_EXCEPT_FLG_SFT 7
+#define ID_EXCEPT_FLG_HI 7
+#define ID_EXCEPT_FLG_SZ 1
+#define ID_FULL_MSK 0x00000001
+#define ID_FULL_I_MSK 0xfffffffe
+#define ID_FULL_SFT 0
+#define ID_FULL_HI 0
+#define ID_FULL_SZ 1
+#define ID_MNG_BUSY_MSK 0x00000002
+#define ID_MNG_BUSY_I_MSK 0xfffffffd
+#define ID_MNG_BUSY_SFT 1
+#define ID_MNG_BUSY_HI 1
+#define ID_MNG_BUSY_SZ 1
+#define REQ_LOCK_MSK 0x00000004
+#define REQ_LOCK_I_MSK 0xfffffffb
+#define REQ_LOCK_SFT 2
+#define REQ_LOCK_HI 2
+#define REQ_LOCK_SZ 1
+#define CH0_REQ_LOCK_MSK 0x00000010
+#define CH0_REQ_LOCK_I_MSK 0xffffffef
+#define CH0_REQ_LOCK_SFT 4
+#define CH0_REQ_LOCK_HI 4
+#define CH0_REQ_LOCK_SZ 1
+#define CH1_REQ_LOCK_MSK 0x00000020
+#define CH1_REQ_LOCK_I_MSK 0xffffffdf
+#define CH1_REQ_LOCK_SFT 5
+#define CH1_REQ_LOCK_HI 5
+#define CH1_REQ_LOCK_SZ 1
+#define CH2_REQ_LOCK_MSK 0x00000040
+#define CH2_REQ_LOCK_I_MSK 0xffffffbf
+#define CH2_REQ_LOCK_SFT 6
+#define CH2_REQ_LOCK_HI 6
+#define CH2_REQ_LOCK_SZ 1
+#define CH3_REQ_LOCK_MSK 0x00000080
+#define CH3_REQ_LOCK_I_MSK 0xffffff7f
+#define CH3_REQ_LOCK_SFT 7
+#define CH3_REQ_LOCK_HI 7
+#define CH3_REQ_LOCK_SZ 1
+#define REQ_LOCK_INT_EN_MSK 0x00000100
+#define REQ_LOCK_INT_EN_I_MSK 0xfffffeff
+#define REQ_LOCK_INT_EN_SFT 8
+#define REQ_LOCK_INT_EN_HI 8
+#define REQ_LOCK_INT_EN_SZ 1
+#define REQ_LOCK_INT_MSK 0x00000200
+#define REQ_LOCK_INT_I_MSK 0xfffffdff
+#define REQ_LOCK_INT_SFT 9
+#define REQ_LOCK_INT_HI 9
+#define REQ_LOCK_INT_SZ 1
+#define MCU_ALC_READY_MSK 0x00000001
+#define MCU_ALC_READY_I_MSK 0xfffffffe
+#define MCU_ALC_READY_SFT 0
+#define MCU_ALC_READY_HI 0
+#define MCU_ALC_READY_SZ 1
+#define ALC_FAIL_MSK 0x00000002
+#define ALC_FAIL_I_MSK 0xfffffffd
+#define ALC_FAIL_SFT 1
+#define ALC_FAIL_HI 1
+#define ALC_FAIL_SZ 1
+#define ALC_BUSY_MSK 0x00000004
+#define ALC_BUSY_I_MSK 0xfffffffb
+#define ALC_BUSY_SFT 2
+#define ALC_BUSY_HI 2
+#define ALC_BUSY_SZ 1
+#define CH0_NVLD_MSK 0x00000010
+#define CH0_NVLD_I_MSK 0xffffffef
+#define CH0_NVLD_SFT 4
+#define CH0_NVLD_HI 4
+#define CH0_NVLD_SZ 1
+#define CH1_NVLD_MSK 0x00000020
+#define CH1_NVLD_I_MSK 0xffffffdf
+#define CH1_NVLD_SFT 5
+#define CH1_NVLD_HI 5
+#define CH1_NVLD_SZ 1
+#define CH2_NVLD_MSK 0x00000040
+#define CH2_NVLD_I_MSK 0xffffffbf
+#define CH2_NVLD_SFT 6
+#define CH2_NVLD_HI 6
+#define CH2_NVLD_SZ 1
+#define CH3_NVLD_MSK 0x00000080
+#define CH3_NVLD_I_MSK 0xffffff7f
+#define CH3_NVLD_SFT 7
+#define CH3_NVLD_HI 7
+#define CH3_NVLD_SZ 1
+#define ALC_INT_ID_MSK 0x00007f00
+#define ALC_INT_ID_I_MSK 0xffff80ff
+#define ALC_INT_ID_SFT 8
+#define ALC_INT_ID_HI 14
+#define ALC_INT_ID_SZ 7
+#define ALC_TIMEOUT_MSK 0x03ff0000
+#define ALC_TIMEOUT_I_MSK 0xfc00ffff
+#define ALC_TIMEOUT_SFT 16
+#define ALC_TIMEOUT_HI 25
+#define ALC_TIMEOUT_SZ 10
+#define ALC_TIMEOUT_INT_EN_MSK 0x40000000
+#define ALC_TIMEOUT_INT_EN_I_MSK 0xbfffffff
+#define ALC_TIMEOUT_INT_EN_SFT 30
+#define ALC_TIMEOUT_INT_EN_HI 30
+#define ALC_TIMEOUT_INT_EN_SZ 1
+#define ALC_TIMEOUT_INT_MSK 0x80000000
+#define ALC_TIMEOUT_INT_I_MSK 0x7fffffff
+#define ALC_TIMEOUT_INT_SFT 31
+#define ALC_TIMEOUT_INT_HI 31
+#define ALC_TIMEOUT_INT_SZ 1
+#define TX_ID_COUNT_MSK 0x000000ff
+#define TX_ID_COUNT_I_MSK 0xffffff00
+#define TX_ID_COUNT_SFT 0
+#define TX_ID_COUNT_HI 7
+#define TX_ID_COUNT_SZ 8
+#define RX_ID_COUNT_MSK 0x0000ff00
+#define RX_ID_COUNT_I_MSK 0xffff00ff
+#define RX_ID_COUNT_SFT 8
+#define RX_ID_COUNT_HI 15
+#define RX_ID_COUNT_SZ 8
+#define TX_ID_THOLD_MSK 0x000000ff
+#define TX_ID_THOLD_I_MSK 0xffffff00
+#define TX_ID_THOLD_SFT 0
+#define TX_ID_THOLD_HI 7
+#define TX_ID_THOLD_SZ 8
+#define RX_ID_THOLD_MSK 0x0000ff00
+#define RX_ID_THOLD_I_MSK 0xffff00ff
+#define RX_ID_THOLD_SFT 8
+#define RX_ID_THOLD_HI 15
+#define RX_ID_THOLD_SZ 8
+#define ID_THOLD_RX_INT_MSK 0x00010000
+#define ID_THOLD_RX_INT_I_MSK 0xfffeffff
+#define ID_THOLD_RX_INT_SFT 16
+#define ID_THOLD_RX_INT_HI 16
+#define ID_THOLD_RX_INT_SZ 1
+#define RX_INT_CH_MSK 0x000e0000
+#define RX_INT_CH_I_MSK 0xfff1ffff
+#define RX_INT_CH_SFT 17
+#define RX_INT_CH_HI 19
+#define RX_INT_CH_SZ 3
+#define ID_THOLD_TX_INT_MSK 0x00100000
+#define ID_THOLD_TX_INT_I_MSK 0xffefffff
+#define ID_THOLD_TX_INT_SFT 20
+#define ID_THOLD_TX_INT_HI 20
+#define ID_THOLD_TX_INT_SZ 1
+#define TX_INT_CH_MSK 0x00e00000
+#define TX_INT_CH_I_MSK 0xff1fffff
+#define TX_INT_CH_SFT 21
+#define TX_INT_CH_HI 23
+#define TX_INT_CH_SZ 3
+#define ID_THOLD_INT_EN_MSK 0x01000000
+#define ID_THOLD_INT_EN_I_MSK 0xfeffffff
+#define ID_THOLD_INT_EN_SFT 24
+#define ID_THOLD_INT_EN_HI 24
+#define ID_THOLD_INT_EN_SZ 1
+#define TX_ID_TB0_MSK 0xffffffff
+#define TX_ID_TB0_I_MSK 0x00000000
+#define TX_ID_TB0_SFT 0
+#define TX_ID_TB0_HI 31
+#define TX_ID_TB0_SZ 32
+#define TX_ID_TB1_MSK 0xffffffff
+#define TX_ID_TB1_I_MSK 0x00000000
+#define TX_ID_TB1_SFT 0
+#define TX_ID_TB1_HI 31
+#define TX_ID_TB1_SZ 32
+#define RX_ID_TB0_MSK 0xffffffff
+#define RX_ID_TB0_I_MSK 0x00000000
+#define RX_ID_TB0_SFT 0
+#define RX_ID_TB0_HI 31
+#define RX_ID_TB0_SZ 32
+#define RX_ID_TB1_MSK 0xffffffff
+#define RX_ID_TB1_I_MSK 0x00000000
+#define RX_ID_TB1_SFT 0
+#define RX_ID_TB1_HI 31
+#define RX_ID_TB1_SZ 32
+#define DOUBLE_RLS_INT_EN_MSK 0x00000001
+#define DOUBLE_RLS_INT_EN_I_MSK 0xfffffffe
+#define DOUBLE_RLS_INT_EN_SFT 0
+#define DOUBLE_RLS_INT_EN_HI 0
+#define DOUBLE_RLS_INT_EN_SZ 1
+#define ID_DOUBLE_RLS_INT_MSK 0x00000002
+#define ID_DOUBLE_RLS_INT_I_MSK 0xfffffffd
+#define ID_DOUBLE_RLS_INT_SFT 1
+#define ID_DOUBLE_RLS_INT_HI 1
+#define ID_DOUBLE_RLS_INT_SZ 1
+#define DOUBLE_RLS_ID_MSK 0x00007f00
+#define DOUBLE_RLS_ID_I_MSK 0xffff80ff
+#define DOUBLE_RLS_ID_SFT 8
+#define DOUBLE_RLS_ID_HI 14
+#define DOUBLE_RLS_ID_SZ 7
+#define ID_LEN_THOLD_INT_EN_MSK 0x00000001
+#define ID_LEN_THOLD_INT_EN_I_MSK 0xfffffffe
+#define ID_LEN_THOLD_INT_EN_SFT 0
+#define ID_LEN_THOLD_INT_EN_HI 0
+#define ID_LEN_THOLD_INT_EN_SZ 1
+#define ALL_ID_LEN_THOLD_INT_MSK 0x00000002
+#define ALL_ID_LEN_THOLD_INT_I_MSK 0xfffffffd
+#define ALL_ID_LEN_THOLD_INT_SFT 1
+#define ALL_ID_LEN_THOLD_INT_HI 1
+#define ALL_ID_LEN_THOLD_INT_SZ 1
+#define TX_ID_LEN_THOLD_INT_MSK 0x00000004
+#define TX_ID_LEN_THOLD_INT_I_MSK 0xfffffffb
+#define TX_ID_LEN_THOLD_INT_SFT 2
+#define TX_ID_LEN_THOLD_INT_HI 2
+#define TX_ID_LEN_THOLD_INT_SZ 1
+#define RX_ID_LEN_THOLD_INT_MSK 0x00000008
+#define RX_ID_LEN_THOLD_INT_I_MSK 0xfffffff7
+#define RX_ID_LEN_THOLD_INT_SFT 3
+#define RX_ID_LEN_THOLD_INT_HI 3
+#define RX_ID_LEN_THOLD_INT_SZ 1
+#define ID_TX_LEN_THOLD_MSK 0x00001ff0
+#define ID_TX_LEN_THOLD_I_MSK 0xffffe00f
+#define ID_TX_LEN_THOLD_SFT 4
+#define ID_TX_LEN_THOLD_HI 12
+#define ID_TX_LEN_THOLD_SZ 9
+#define ID_RX_LEN_THOLD_MSK 0x003fe000
+#define ID_RX_LEN_THOLD_I_MSK 0xffc01fff
+#define ID_RX_LEN_THOLD_SFT 13
+#define ID_RX_LEN_THOLD_HI 21
+#define ID_RX_LEN_THOLD_SZ 9
+#define ID_LEN_THOLD_MSK 0x7fc00000
+#define ID_LEN_THOLD_I_MSK 0x803fffff
+#define ID_LEN_THOLD_SFT 22
+#define ID_LEN_THOLD_HI 30
+#define ID_LEN_THOLD_SZ 9
+#define ALL_ID_ALC_LEN_MSK 0x000001ff
+#define ALL_ID_ALC_LEN_I_MSK 0xfffffe00
+#define ALL_ID_ALC_LEN_SFT 0
+#define ALL_ID_ALC_LEN_HI 8
+#define ALL_ID_ALC_LEN_SZ 9
+#define TX_ID_ALC_LEN_MSK 0x0003fe00
+#define TX_ID_ALC_LEN_I_MSK 0xfffc01ff
+#define TX_ID_ALC_LEN_SFT 9
+#define TX_ID_ALC_LEN_HI 17
+#define TX_ID_ALC_LEN_SZ 9
+#define RX_ID_ALC_LEN_MSK 0x07fc0000
+#define RX_ID_ALC_LEN_I_MSK 0xf803ffff
+#define RX_ID_ALC_LEN_SFT 18
+#define RX_ID_ALC_LEN_HI 26
+#define RX_ID_ALC_LEN_SZ 9
+#define CH_ARB_EN_MSK 0x00000001
+#define CH_ARB_EN_I_MSK 0xfffffffe
+#define CH_ARB_EN_SFT 0
+#define CH_ARB_EN_HI 0
+#define CH_ARB_EN_SZ 1
+#define CH_PRI1_MSK 0x00000030
+#define CH_PRI1_I_MSK 0xffffffcf
+#define CH_PRI1_SFT 4
+#define CH_PRI1_HI 5
+#define CH_PRI1_SZ 2
+#define CH_PRI2_MSK 0x00000300
+#define CH_PRI2_I_MSK 0xfffffcff
+#define CH_PRI2_SFT 8
+#define CH_PRI2_HI 9
+#define CH_PRI2_SZ 2
+#define CH_PRI3_MSK 0x00003000
+#define CH_PRI3_I_MSK 0xffffcfff
+#define CH_PRI3_SFT 12
+#define CH_PRI3_HI 13
+#define CH_PRI3_SZ 2
+#define CH_PRI4_MSK 0x00030000
+#define CH_PRI4_I_MSK 0xfffcffff
+#define CH_PRI4_SFT 16
+#define CH_PRI4_HI 17
+#define CH_PRI4_SZ 2
+#define TX_ID_REMAIN_MSK 0x0000007f
+#define TX_ID_REMAIN_I_MSK 0xffffff80
+#define TX_ID_REMAIN_SFT 0
+#define TX_ID_REMAIN_HI 6
+#define TX_ID_REMAIN_SZ 7
+#define TX_PAGE_REMAIN_MSK 0x0001ff00
+#define TX_PAGE_REMAIN_I_MSK 0xfffe00ff
+#define TX_PAGE_REMAIN_SFT 8
+#define TX_PAGE_REMAIN_HI 16
+#define TX_PAGE_REMAIN_SZ 9
+#define ID_PAGE_MAX_SIZE_MSK 0x000001ff
+#define ID_PAGE_MAX_SIZE_I_MSK 0xfffffe00
+#define ID_PAGE_MAX_SIZE_SFT 0
+#define ID_PAGE_MAX_SIZE_HI 8
+#define ID_PAGE_MAX_SIZE_SZ 9
+#define TX_PAGE_LIMIT_MSK 0x000001ff
+#define TX_PAGE_LIMIT_I_MSK 0xfffffe00
+#define TX_PAGE_LIMIT_SFT 0
+#define TX_PAGE_LIMIT_HI 8
+#define TX_PAGE_LIMIT_SZ 9
+#define TX_COUNT_LIMIT_MSK 0x00ff0000
+#define TX_COUNT_LIMIT_I_MSK 0xff00ffff
+#define TX_COUNT_LIMIT_SFT 16
+#define TX_COUNT_LIMIT_HI 23
+#define TX_COUNT_LIMIT_SZ 8
+#define TX_LIMIT_INT_MSK 0x40000000
+#define TX_LIMIT_INT_I_MSK 0xbfffffff
+#define TX_LIMIT_INT_SFT 30
+#define TX_LIMIT_INT_HI 30
+#define TX_LIMIT_INT_SZ 1
+#define TX_LIMIT_INT_EN_MSK 0x80000000
+#define TX_LIMIT_INT_EN_I_MSK 0x7fffffff
+#define TX_LIMIT_INT_EN_SFT 31
+#define TX_LIMIT_INT_EN_HI 31
+#define TX_LIMIT_INT_EN_SZ 1
+#define TX_PAGE_USE_7_0_MSK 0x000000ff
+#define TX_PAGE_USE_7_0_I_MSK 0xffffff00
+#define TX_PAGE_USE_7_0_SFT 0
+#define TX_PAGE_USE_7_0_HI 7
+#define TX_PAGE_USE_7_0_SZ 8
+#define TX_ID_USE_5_0_MSK 0x00003f00
+#define TX_ID_USE_5_0_I_MSK 0xffffc0ff
+#define TX_ID_USE_5_0_SFT 8
+#define TX_ID_USE_5_0_HI 13
+#define TX_ID_USE_5_0_SZ 6
+#define EDCA0_FFO_CNT_MSK 0x0003c000
+#define EDCA0_FFO_CNT_I_MSK 0xfffc3fff
+#define EDCA0_FFO_CNT_SFT 14
+#define EDCA0_FFO_CNT_HI 17
+#define EDCA0_FFO_CNT_SZ 4
+#define EDCA1_FFO_CNT_3_0_MSK 0x003c0000
+#define EDCA1_FFO_CNT_3_0_I_MSK 0xffc3ffff
+#define EDCA1_FFO_CNT_3_0_SFT 18
+#define EDCA1_FFO_CNT_3_0_HI 21
+#define EDCA1_FFO_CNT_3_0_SZ 4
+#define EDCA2_FFO_CNT_MSK 0x07c00000
+#define EDCA2_FFO_CNT_I_MSK 0xf83fffff
+#define EDCA2_FFO_CNT_SFT 22
+#define EDCA2_FFO_CNT_HI 26
+#define EDCA2_FFO_CNT_SZ 5
+#define EDCA3_FFO_CNT_MSK 0xf8000000
+#define EDCA3_FFO_CNT_I_MSK 0x07ffffff
+#define EDCA3_FFO_CNT_SFT 27
+#define EDCA3_FFO_CNT_HI 31
+#define EDCA3_FFO_CNT_SZ 5
+#define ID_TB2_MSK 0xffffffff
+#define ID_TB2_I_MSK 0x00000000
+#define ID_TB2_SFT 0
+#define ID_TB2_HI 31
+#define ID_TB2_SZ 32
+#define ID_TB3_MSK 0xffffffff
+#define ID_TB3_I_MSK 0x00000000
+#define ID_TB3_SFT 0
+#define ID_TB3_HI 31
+#define ID_TB3_SZ 32
+#define TX_ID_TB2_MSK 0xffffffff
+#define TX_ID_TB2_I_MSK 0x00000000
+#define TX_ID_TB2_SFT 0
+#define TX_ID_TB2_HI 31
+#define TX_ID_TB2_SZ 32
+#define TX_ID_TB3_MSK 0xffffffff
+#define TX_ID_TB3_I_MSK 0x00000000
+#define TX_ID_TB3_SFT 0
+#define TX_ID_TB3_HI 31
+#define TX_ID_TB3_SZ 32
+#define RX_ID_TB2_MSK 0xffffffff
+#define RX_ID_TB2_I_MSK 0x00000000
+#define RX_ID_TB2_SFT 0
+#define RX_ID_TB2_HI 31
+#define RX_ID_TB2_SZ 32
+#define RX_ID_TB3_MSK 0xffffffff
+#define RX_ID_TB3_I_MSK 0x00000000
+#define RX_ID_TB3_SFT 0
+#define RX_ID_TB3_HI 31
+#define RX_ID_TB3_SZ 32
+#define TX_PAGE_USE2_MSK 0x000001ff
+#define TX_PAGE_USE2_I_MSK 0xfffffe00
+#define TX_PAGE_USE2_SFT 0
+#define TX_PAGE_USE2_HI 8
+#define TX_PAGE_USE2_SZ 9
+#define TX_ID_USE2_MSK 0x0001fe00
+#define TX_ID_USE2_I_MSK 0xfffe01ff
+#define TX_ID_USE2_SFT 9
+#define TX_ID_USE2_HI 16
+#define TX_ID_USE2_SZ 8
+#define EDCA4_FFO_CNT_MSK 0x001e0000
+#define EDCA4_FFO_CNT_I_MSK 0xffe1ffff
+#define EDCA4_FFO_CNT_SFT 17
+#define EDCA4_FFO_CNT_HI 20
+#define EDCA4_FFO_CNT_SZ 4
+#define EDCA5_FFO_CNT_MSK 0x03e00000
+#define EDCA5_FFO_CNT_I_MSK 0xfc1fffff
+#define EDCA5_FFO_CNT_SFT 21
+#define EDCA5_FFO_CNT_HI 25
+#define EDCA5_FFO_CNT_SZ 5
+#define TX_PAGE_USE3_MSK 0x000001ff
+#define TX_PAGE_USE3_I_MSK 0xfffffe00
+#define TX_PAGE_USE3_SFT 0
+#define TX_PAGE_USE3_HI 8
+#define TX_PAGE_USE3_SZ 9
+#define TX_ID_USE3_MSK 0x0001fe00
+#define TX_ID_USE3_I_MSK 0xfffe01ff
+#define TX_ID_USE3_SFT 9
+#define TX_ID_USE3_HI 16
+#define TX_ID_USE3_SZ 8
+#define EDCA1_FFO_CNT2_MSK 0x003e0000
+#define EDCA1_FFO_CNT2_I_MSK 0xffc1ffff
+#define EDCA1_FFO_CNT2_SFT 17
+#define EDCA1_FFO_CNT2_HI 21
+#define EDCA1_FFO_CNT2_SZ 5
+#define EDCA4_FFO_CNT2_MSK 0x07800000
+#define EDCA4_FFO_CNT2_I_MSK 0xf87fffff
+#define EDCA4_FFO_CNT2_SFT 23
+#define EDCA4_FFO_CNT2_HI 26
+#define EDCA4_FFO_CNT2_SZ 4
+#define EDCA5_FFO_CNT2_MSK 0xf8000000
+#define EDCA5_FFO_CNT2_I_MSK 0x07ffffff
+#define EDCA5_FFO_CNT2_SFT 27
+#define EDCA5_FFO_CNT2_HI 31
+#define EDCA5_FFO_CNT2_SZ 5
+#define TX_PAGE_USE4_MSK 0x000001ff
+#define TX_PAGE_USE4_I_MSK 0xfffffe00
+#define TX_PAGE_USE4_SFT 0
+#define TX_PAGE_USE4_HI 8
+#define TX_PAGE_USE4_SZ 9
+#define TX_ID_USE4_MSK 0x0001fe00
+#define TX_ID_USE4_I_MSK 0xfffe01ff
+#define TX_ID_USE4_SFT 9
+#define TX_ID_USE4_HI 16
+#define TX_ID_USE4_SZ 8
+#define EDCA2_FFO_CNT2_MSK 0x003e0000
+#define EDCA2_FFO_CNT2_I_MSK 0xffc1ffff
+#define EDCA2_FFO_CNT2_SFT 17
+#define EDCA2_FFO_CNT2_HI 21
+#define EDCA2_FFO_CNT2_SZ 5
+#define EDCA3_FFO_CNT2_MSK 0x07c00000
+#define EDCA3_FFO_CNT2_I_MSK 0xf83fffff
+#define EDCA3_FFO_CNT2_SFT 22
+#define EDCA3_FFO_CNT2_HI 26
+#define EDCA3_FFO_CNT2_SZ 5
+#define TX_ID_IFO_LEN_MSK 0x000001ff
+#define TX_ID_IFO_LEN_I_MSK 0xfffffe00
+#define TX_ID_IFO_LEN_SFT 0
+#define TX_ID_IFO_LEN_HI 8
+#define TX_ID_IFO_LEN_SZ 9
+#define RX_ID_IFO_LEN_MSK 0x01ff0000
+#define RX_ID_IFO_LEN_I_MSK 0xfe00ffff
+#define RX_ID_IFO_LEN_SFT 16
+#define RX_ID_IFO_LEN_HI 24
+#define RX_ID_IFO_LEN_SZ 9
+#define MAX_ALL_ALC_ID_CNT_MSK 0x000000ff
+#define MAX_ALL_ALC_ID_CNT_I_MSK 0xffffff00
+#define MAX_ALL_ALC_ID_CNT_SFT 0
+#define MAX_ALL_ALC_ID_CNT_HI 7
+#define MAX_ALL_ALC_ID_CNT_SZ 8
+#define MAX_TX_ALC_ID_CNT_MSK 0x0000ff00
+#define MAX_TX_ALC_ID_CNT_I_MSK 0xffff00ff
+#define MAX_TX_ALC_ID_CNT_SFT 8
+#define MAX_TX_ALC_ID_CNT_HI 15
+#define MAX_TX_ALC_ID_CNT_SZ 8
+#define MAX_RX_ALC_ID_CNT_MSK 0x00ff0000
+#define MAX_RX_ALC_ID_CNT_I_MSK 0xff00ffff
+#define MAX_RX_ALC_ID_CNT_SFT 16
+#define MAX_RX_ALC_ID_CNT_HI 23
+#define MAX_RX_ALC_ID_CNT_SZ 8
+#define MAX_ALL_ID_ALC_LEN_MSK 0x000001ff
+#define MAX_ALL_ID_ALC_LEN_I_MSK 0xfffffe00
+#define MAX_ALL_ID_ALC_LEN_SFT 0
+#define MAX_ALL_ID_ALC_LEN_HI 8
+#define MAX_ALL_ID_ALC_LEN_SZ 9
+#define MAX_TX_ID_ALC_LEN_MSK 0x0003fe00
+#define MAX_TX_ID_ALC_LEN_I_MSK 0xfffc01ff
+#define MAX_TX_ID_ALC_LEN_SFT 9
+#define MAX_TX_ID_ALC_LEN_HI 17
+#define MAX_TX_ID_ALC_LEN_SZ 9
+#define MAX_RX_ID_ALC_LEN_MSK 0x07fc0000
+#define MAX_RX_ID_ALC_LEN_I_MSK 0xf803ffff
+#define MAX_RX_ID_ALC_LEN_SFT 18
+#define MAX_RX_ID_ALC_LEN_HI 26
+#define MAX_RX_ID_ALC_LEN_SZ 9
+#define ALC_ABT_ID_MSK 0x0000007f
+#define ALC_ABT_ID_I_MSK 0xffffff80
+#define ALC_ABT_ID_SFT 0
+#define ALC_ABT_ID_HI 6
+#define ALC_ABT_ID_SZ 7
+#define ALC_ABT_STS_MSK 0x00000100
+#define ALC_ABT_STS_I_MSK 0xfffffeff
+#define ALC_ABT_STS_SFT 8
+#define ALC_ABT_STS_HI 8
+#define ALC_ABT_STS_SZ 1
+#define ALC_ABT_CLR_MSK 0x00000200
+#define ALC_ABT_CLR_I_MSK 0xfffffdff
+#define ALC_ABT_CLR_SFT 9
+#define ALC_ABT_CLR_HI 9
+#define ALC_ABT_CLR_SZ 1
+#define ALC_ERR_STS_MSK 0x00000001
+#define ALC_ERR_STS_I_MSK 0xfffffffe
+#define ALC_ERR_STS_SFT 0
+#define ALC_ERR_STS_HI 0
+#define ALC_ERR_STS_SZ 1
+#define RLS_ERR_STS_MSK 0x00000002
+#define RLS_ERR_STS_I_MSK 0xfffffffd
+#define RLS_ERR_STS_SFT 1
+#define RLS_ERR_STS_HI 1
+#define RLS_ERR_STS_SZ 1
+#define ALC_ERR_CLR_MSK 0x00000004
+#define ALC_ERR_CLR_I_MSK 0xfffffffb
+#define ALC_ERR_CLR_SFT 2
+#define ALC_ERR_CLR_HI 2
+#define ALC_ERR_CLR_SZ 1
+#define RLS_ERR_CLR_MSK 0x00000008
+#define RLS_ERR_CLR_I_MSK 0xfffffff7
+#define RLS_ERR_CLR_SFT 3
+#define RLS_ERR_CLR_HI 3
+#define RLS_ERR_CLR_SZ 1
+#define AL_STATE_MSK 0x00000700
+#define AL_STATE_I_MSK 0xfffff8ff
+#define AL_STATE_SFT 8
+#define AL_STATE_HI 10
+#define AL_STATE_SZ 3
+#define RL_STATE_MSK 0x00007000
+#define RL_STATE_I_MSK 0xffff8fff
+#define RL_STATE_SFT 12
+#define RL_STATE_HI 14
+#define RL_STATE_SZ 3
+#define ALC_ERR_ID_MSK 0x007f0000
+#define ALC_ERR_ID_I_MSK 0xff80ffff
+#define ALC_ERR_ID_SFT 16
+#define ALC_ERR_ID_HI 22
+#define ALC_ERR_ID_SZ 7
+#define RLS_ERR_ID_MSK 0x7f000000
+#define RLS_ERR_ID_I_MSK 0x80ffffff
+#define RLS_ERR_ID_SFT 24
+#define RLS_ERR_ID_HI 30
+#define RLS_ERR_ID_SZ 7
+#define DMN_NOHIT_STS_MSK 0x00000001
+#define DMN_NOHIT_STS_I_MSK 0xfffffffe
+#define DMN_NOHIT_STS_SFT 0
+#define DMN_NOHIT_STS_HI 0
+#define DMN_NOHIT_STS_SZ 1
+#define DMN_NOHIT_CLR_MSK 0x00000002
+#define DMN_NOHIT_CLR_I_MSK 0xfffffffd
+#define DMN_NOHIT_CLR_SFT 1
+#define DMN_NOHIT_CLR_HI 1
+#define DMN_NOHIT_CLR_SZ 1
+#define DMN_WR_MSK 0x00000004
+#define DMN_WR_I_MSK 0xfffffffb
+#define DMN_WR_SFT 2
+#define DMN_WR_HI 2
+#define DMN_WR_SZ 1
+#define DMN_PORT_MSK 0x000000f0
+#define DMN_PORT_I_MSK 0xffffff0f
+#define DMN_PORT_SFT 4
+#define DMN_PORT_HI 7
+#define DMN_PORT_SZ 4
+#define DMN_NHIT_ID_MSK 0x00007f00
+#define DMN_NHIT_ID_I_MSK 0xffff80ff
+#define DMN_NHIT_ID_SFT 8
+#define DMN_NHIT_ID_HI 14
+#define DMN_NHIT_ID_SZ 7
+#define DMN_NHIT_ADDR_MSK 0x00ff0000
+#define DMN_NHIT_ADDR_I_MSK 0xff00ffff
+#define DMN_NHIT_ADDR_SFT 16
+#define DMN_NHIT_ADDR_HI 23
+#define DMN_NHIT_ADDR_SZ 8
+#define AVA_TAG_MSK 0x000001ff
+#define AVA_TAG_I_MSK 0xfffffe00
+#define AVA_TAG_SFT 0
+#define AVA_TAG_HI 8
+#define AVA_TAG_SZ 9
+#define PKTBUF_FULL_MSK 0x00010000
+#define PKTBUF_FULL_I_MSK 0xfffeffff
+#define PKTBUF_FULL_SFT 16
+#define PKTBUF_FULL_HI 16
+#define PKTBUF_FULL_SZ 1
+#define PKT_REQ_STATUS_MSK 0x0000ffff
+#define PKT_REQ_STATUS_I_MSK 0xffff0000
+#define PKT_REQ_STATUS_SFT 0
+#define PKT_REQ_STATUS_HI 15
+#define PKT_REQ_STATUS_SZ 16
+#define PG_TAG_31_0_MSK 0xffffffff
+#define PG_TAG_31_0_I_MSK 0x00000000
+#define PG_TAG_31_0_SFT 0
+#define PG_TAG_31_0_HI 31
+#define PG_TAG_31_0_SZ 32
+#define PG_TAG_63_32_MSK 0xffffffff
+#define PG_TAG_63_32_I_MSK 0x00000000
+#define PG_TAG_63_32_SFT 0
+#define PG_TAG_63_32_HI 31
+#define PG_TAG_63_32_SZ 32
+#define PG_TAG_95_64_MSK 0xffffffff
+#define PG_TAG_95_64_I_MSK 0x00000000
+#define PG_TAG_95_64_SFT 0
+#define PG_TAG_95_64_HI 31
+#define PG_TAG_95_64_SZ 32
+#define PG_TAG_127_96_MSK 0xffffffff
+#define PG_TAG_127_96_I_MSK 0x00000000
+#define PG_TAG_127_96_SFT 0
+#define PG_TAG_127_96_HI 31
+#define PG_TAG_127_96_SZ 32
+#define PG_TAG_159_128_MSK 0xffffffff
+#define PG_TAG_159_128_I_MSK 0x00000000
+#define PG_TAG_159_128_SFT 0
+#define PG_TAG_159_128_HI 31
+#define PG_TAG_159_128_SZ 32
+#define PG_TAG_191_160_MSK 0xffffffff
+#define PG_TAG_191_160_I_MSK 0x00000000
+#define PG_TAG_191_160_SFT 0
+#define PG_TAG_191_160_HI 31
+#define PG_TAG_191_160_SZ 32
+#define PG_TAG_223_192_MSK 0xffffffff
+#define PG_TAG_223_192_I_MSK 0x00000000
+#define PG_TAG_223_192_SFT 0
+#define PG_TAG_223_192_HI 31
+#define PG_TAG_223_192_SZ 32
+#define PG_TAG_255_224_MSK 0xffffffff
+#define PG_TAG_255_224_I_MSK 0x00000000
+#define PG_TAG_255_224_SFT 0
+#define PG_TAG_255_224_HI 31
+#define PG_TAG_255_224_SZ 32
+#define FPGA_TO_GEMINIA_DAC_SIGN_SWAP_MSK 0x00000002
+#define FPGA_TO_GEMINIA_DAC_SIGN_SWAP_I_MSK 0xfffffffd
+#define FPGA_TO_GEMINIA_DAC_SIGN_SWAP_SFT 1
+#define FPGA_TO_GEMINIA_DAC_SIGN_SWAP_HI 1
+#define FPGA_TO_GEMINIA_DAC_SIGN_SWAP_SZ 1
+#define FPGA_TO_GEMINIA_DAC_EDGE_SEL_MSK 0x00000004
+#define FPGA_TO_GEMINIA_DAC_EDGE_SEL_I_MSK 0xfffffffb
+#define FPGA_TO_GEMINIA_DAC_EDGE_SEL_SFT 2
+#define FPGA_TO_GEMINIA_DAC_EDGE_SEL_HI 2
+#define FPGA_TO_GEMINIA_DAC_EDGE_SEL_SZ 1
+#define FPGA_TO_GEMINIA_ADC_EDGE_SEL_MSK 0x00000008
+#define FPGA_TO_GEMINIA_ADC_EDGE_SEL_I_MSK 0xfffffff7
+#define FPGA_TO_GEMINIA_ADC_EDGE_SEL_SFT 3
+#define FPGA_TO_GEMINIA_ADC_EDGE_SEL_HI 3
+#define FPGA_TO_GEMINIA_ADC_EDGE_SEL_SZ 1
diff --git a/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/ssv6006C_mac.c b/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/ssv6006C_mac.c
new file mode 100644
index 000000000..3c8bcf631
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/ssv6006C_mac.c
@@ -0,0 +1,2960 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifdef ECLIPSE
+#include <ssv_mod_conf.h>
+#endif
+#include <linux/version.h>
+#if ((defined SSV_SUPPORT_HAL) && (defined SSV_SUPPORT_SSV6006))
+#include <linux/etherdevice.h>
+#include <linux/string.h>
+#include <linux/random.h>
+#include <linux/platform_device.h>
+#include "ssv6006_cfg.h"
+#include "ssv6006_mac.h"
+#include "ssv6006C_reg.h"
+#include "ssv6006C_aux.h"
+#include <smac/dev.h>
+#include <smac/efuse.h>
+#include <hal.h>
+#include "ssv6006_priv.h"
+#include "ssv6006_priv_normal.h"
+#include <smac/ssv_skb.h>
+#include <ssvdevice/ssv_cmd.h>
+#include <hci/hctrl.h>
+#include <hwif/usb/usb.h>
+#include <linux_80211.h>
+static u32 ssv6006c_alloc_pbuf(struct ssv_softc *sc, int size, int type);
+static void ssv6006c_write_key_to_hw(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv,
+                                     void *key, int wsid, int key_idx, enum SSV6XXX_WSID_SEC key_type);
+static int ssv6006c_set_macaddr(struct ssv_hw *sh, int vif_idx);
+static int ssv6006c_set_bssid(struct ssv_hw *sh, u8 *bssid, int vif_idx);
+static void ssv6006c_write_hw_group_keyidx(struct ssv_hw *sh, struct ssv_vif_priv_data *vif_priv, int key_idx);
+static int ssv6006c_reset_cpu(struct ssv_hw *sh);
+static const u32 reg_wsid[] = {ADR_WSID0, ADR_WSID1, ADR_WSID2, ADR_WSID3,
+                               ADR_WSID4, ADR_WSID5, ADR_WSID6, ADR_WSID7
+                              };
+static const ssv_cabrio_reg ssv6006c_mac_ini_table[]= {
+    {ADR_CONTROL, 0x12000006},
+    {ADR_RX_TIME_STAMP_CFG, ((28 << MRX_STP_OFST_SFT) | 0x01)},
+    {
+        ADR_GLBLE_SET, (0 << OP_MODE_SFT) |
+        (0 << SNIFFER_MODE_SFT) |
+        (1 << DUP_FLT_SFT) |
+        (SSV6006_TX_PKT_RSVD_SETTING << TX_PKT_RSVD_SFT) |
+        ((u32)(RXPB_OFFSET) << PB_OFFSET_SFT)
+    },
+    {ADR_TX_ETHER_TYPE_0, 0x00000000},
+    {ADR_TX_ETHER_TYPE_1, 0x00000000},
+    {ADR_RX_ETHER_TYPE_0, 0x00000000},
+    {ADR_RX_ETHER_TYPE_1, 0x00000000},
+    {ADR_REASON_TRAP0, 0x7FBC7F87},
+    {ADR_REASON_TRAP1, 0x0000013F},
+    {ADR_TRAP_HW_ID, M_ENG_CPU},
+    {ADR_WSID0, 0x00000000},
+    {ADR_WSID1, 0x00000000},
+    {ADR_WSID2, 0x00000000},
+    {ADR_WSID3, 0x00000000},
+    {ADR_WSID4, 0x00000000},
+    {ADR_WSID5, 0x00000000},
+    {ADR_WSID6, 0x00000000},
+    {ADR_WSID7, 0x00000000},
+    {ADR_MASK_TYPHOST_INT_MAP, 0xffff7fff},
+    {ADR_MASK_TYPHOST_INT_MAP_15, 0xff0fffff},
+#ifdef CONFIG_SSV_SUPPORT_BTCX
+    {
+        ADR_BTCX0, COEXIST_EN_MSK |
+        (WIRE_MODE_SZ<<WIRE_MODE_SFT) |
+        WIFI_TX_SW_POL_MSK |
+        BT_SW_POL_MSK
+    },
+    {
+        ADR_BTCX1, SSV6006_BT_PRI_SMP_TIME |
+        (SSV6006_BT_STA_SMP_TIME << BT_STA_SMP_TIME_SFT) |
+        (SSV6006_WLAN_REMAIN_TIME << WLAN_REMAIN_TIME_SFT)
+    },
+    {ADR_SWITCH_CTL, BT_2WIRE_EN_MSK},
+    {ADR_PAD7, 1},
+    {ADR_PAD8, 0},
+    {ADR_PAD9, 1},
+    {ADR_PAD25, 1},
+    {ADR_PAD27, 8},
+    {ADR_PAD28, 8},
+#endif
+    {ADR_MTX_RESPFRM_RATE_TABLE_01, 0x0000},
+    {ADR_MTX_RESPFRM_RATE_TABLE_02, 0x0000},
+    {ADR_MTX_RESPFRM_RATE_TABLE_03, 0x0002},
+    {ADR_MTX_RESPFRM_RATE_TABLE_11, 0x0000},
+    {ADR_MTX_RESPFRM_RATE_TABLE_12, 0x0000},
+    {ADR_MTX_RESPFRM_RATE_TABLE_13, 0x0012},
+    {ADR_MTX_RESPFRM_RATE_TABLE_92_B2, 0x9090},
+    {ADR_MTX_RESPFRM_RATE_TABLE_94_B4, 0x9292},
+    {ADR_MTX_RESPFRM_RATE_TABLE_C1_E1, 0x9090},
+    {ADR_MTX_RESPFRM_RATE_TABLE_C3_E3, 0x9292},
+    {ADR_MTX_RESPFRM_RATE_TABLE_D1_F1, 0x9090},
+    {ADR_MTX_RESPFRM_RATE_TABLE_D3_F3, 0x9292},
+    {ADR_BA_CTRL, 0x9},
+};
+static void ssv6006c_sec_lut_setting(struct ssv_hw *sh)
+{
+    u8 lut_sel = 1;
+    sh->sc->ccmp_h_sel = 1;
+    if (sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_TX) {
+        dev_dbg(sh->sc->dev, "Support AMPDU TX mode, ccmp header source must from SW\n");
+        sh->sc->ccmp_h_sel = 1;
+    }
+    dev_dbg(sh->sc->dev, "CCMP header source from %s, Security LUT version V%d\n", (sh->sc->ccmp_h_sel == 1) ? "SW" : "LUT", lut_sel+1);
+    SMAC_REG_SET_BITS(sh, ADR_GLBLE_SET, (sh->sc->ccmp_h_sel << 22), 0x400000);
+    SMAC_REG_SET_BITS(sh, ADR_GLBLE_SET, (lut_sel << 23), 0x800000);
+}
+static void ssv6006c_set_page_id(struct ssv_hw *sh)
+{
+    u32 dev_type = HCI_DEVICE_TYPE(sh->hci.hci_ctrl);
+    u32 tx_page_threshold = 0;
+    SMAC_REG_SET_BITS(sh, ADR_TRX_ID_THRESHOLD,
+                      ((sh->tx_info.tx_id_threshold << TX_ID_THOLD_SFT)|
+                       (sh->rx_info.rx_id_threshold << RX_ID_THOLD_SFT)),
+                      (TX_ID_THOLD_MSK | RX_ID_THOLD_MSK));
+    if (dev_type == SSV_HWIF_INTERFACE_USB) {
+        tx_page_threshold = sh->tx_info.tx_page_threshold + SSV6006_USB_FIFO;
+    } else {
+        tx_page_threshold = sh->tx_info.tx_page_threshold;
+    }
+    SMAC_REG_SET_BITS(sh, ADR_ID_LEN_THREADSHOLD1,
+                      ((tx_page_threshold << ID_TX_LEN_THOLD_SFT)|
+                       (sh->rx_info.rx_page_threshold << ID_RX_LEN_THOLD_SFT)),
+                      (ID_TX_LEN_THOLD_MSK | ID_RX_LEN_THOLD_MSK));
+}
+static void ssv6006c_update_page_id(struct ssv_hw *sh)
+{
+    HAL_INIT_TX_CFG(sh);
+    HAL_INIT_RX_CFG(sh);
+    ssv6006c_set_page_id(sh);
+}
+static int ssv6006c_init_mac(struct ssv_hw *sh)
+{
+    struct ssv_softc *sc=sh->sc;
+    int ret = 0, i = 0;
+    u32 regval;
+    u8 null_address[6]= {0};
+    u32 dev_type = HCI_DEVICE_TYPE(sh->hci.hci_ctrl);
+    SMAC_REG_WRITE(sh, ADR_BRG_SW_RST, 1 << MAC_SW_RST_SFT);
+    do {
+        SMAC_REG_READ(sh, ADR_BRG_SW_RST, & regval);
+        i ++;
+        if (i >10000) {
+            dev_dbg(sc->dev, "MAC reset fail !!!!\n");
+            WARN_ON(1);
+            ret = 1;
+            goto exit;
+        }
+    } while (regval != 0);
+    regval = GET_CLK_DIGI_SEL;
+    switch (regval) {
+    case 8:
+        SET_MAC_CLK_80M(1);
+        SET_PHYTXSTART_NCYCLE(26);
+        SET_PRESCALER_US(80);
+        if (dev_type == SSV_HWIF_INTERFACE_USB) {
+            if ((sc->sh->cfg.usb_hw_resource & USB_HW_RESOURCE_CHK_FORCE_OFF) == 0) {
+                sc->sh->cfg.usb_hw_resource = ( USB_HW_RESOURCE_CHK_TXID
+                                                | USB_HW_RESOURCE_CHK_TXPAGE);
+                ssv6006c_update_page_id(sh);
+            } else {
+                sc->sh->cfg.usb_hw_resource &= ~( USB_HW_RESOURCE_CHK_TXID
+                                                  | USB_HW_RESOURCE_CHK_TXPAGE);
+            }
+        }
+        break;
+    case 4:
+        SET_MAC_CLK_80M(0);
+        SET_PHYTXSTART_NCYCLE(13);
+        SET_PRESCALER_US(40);
+        break;
+    default:
+        dev_dbg(sc->dev, "digi clk is invalid for mac!!!!\n");
+        goto exit;
+    }
+    ret = HAL_WRITE_MAC_INI(sh);
+    if (ret)
+        goto exit;
+    if (sh->cfg.hw_caps & SSV6200_HW_CAP_HCI_RX_AGGR) {
+        SMAC_REG_SET_BITS(sh, ADR_HCI_TRX_MODE, (0<<HCI_RX_EN_SFT), HCI_RX_EN_MSK);
+        do {
+            SMAC_REG_READ(sh, ADR_RX_PACKET_LENGTH_STATUS, &regval);
+            regval &= HCI_RX_LEN_I_MSK;
+            i++;
+            if (i > 10000) {
+                dev_dbg(sc->dev, "CANNOT ENABLE HCI RX AGGREGATION!!!\n");
+                WARN_ON(1);
+                ret = 1;
+                goto exit;
+            }
+        } while (regval != 0);
+        regval = 0;
+        SMAC_REG_SET_BITS(sh, ADR_HCI_TRX_MODE, (1<<HCI_RX_FORM_1_SFT), HCI_RX_FORM_1_MSK);
+        regval = (sh->cfg.hw_rx_agg_cnt << RX_AGG_CNT_SFT) |
+                 (sh->cfg.hw_rx_agg_method_3 << RX_AGG_METHOD_3_SFT) |
+                 (sh->cfg.hw_rx_agg_timer_reload << RX_AGG_TIMER_RELOAD_VALUE_SFT);
+        SMAC_REG_WRITE(sh, ADR_FORCE_RX_AGGREGATION_MODE, regval);
+        SMAC_REG_SET_BITS(sh, ADR_HCI_FORCE_PRE_BULK_IN, HCI_RX_AGGR_SIZE, HCI_BULK_IN_HOST_SIZE_MSK);
+        SMAC_REG_SET_BITS(sh, ADR_HCI_TRX_MODE, (1<<HCI_RX_EN_SFT), HCI_RX_EN_MSK);
+        sh->rx_mode = (sh->cfg.hw_rx_agg_method_3) ? RX_HW_AGG_MODE_METH3 : RX_HW_AGG_MODE;
+    }
+    SMAC_REG_SET_BITS(sh, ADR_MTX_BCN_EN_MISC,
+                      1 << MTX_TSF_TIMER_EN_SFT, MTX_TSF_TIMER_EN_MSK);
+    SMAC_REG_WRITE(sh, ADR_HCI_TX_RX_INFO_SIZE,
+                   ((u32)(TXPB_OFFSET) << TX_PBOFFSET_SFT) |
+                   ((u32)(sh->tx_desc_len) << TX_INFO_SIZE_SFT) |
+                   ((u32)(sh->rx_desc_len) << RX_INFO_SIZE_SFT) |
+                   ((u32)(sh->rx_pinfo_pad) << RX_LAST_PHY_SIZE_SFT )
+                  );
+    SMAC_REG_READ(sh,ADR_MRX_WATCH_DOG, &regval);
+    regval &= 0xfffffff0;
+    SMAC_REG_WRITE(sh,ADR_MRX_WATCH_DOG, regval);
+    ssv6006c_set_page_id(sh);
+#ifdef CONFIG_SSV_CABRIO_MB_DEBUG
+    SMAC_REG_READ(sh, ADR_MB_DBG_CFG3, &regval);
+    regval |= (debug_buffer<<0);
+    SMAC_REG_WRITE(sh, ADR_MB_DBG_CFG3, regval);
+    SMAC_REG_READ(sh, ADR_MB_DBG_CFG2, &regval);
+    regval |= (DEBUG_SIZE<<16);
+    SMAC_REG_WRITE(sh, ADR_MB_DBG_CFG2, regval);
+    SMAC_REG_SET_BITS(sh, ADR_MB_DBG_CFG1, (1<<MB_DBG_EN_SFT), MB_DBG_EN_MSK);
+    SMAC_REG_SET_BITS(sh, ADR_MBOX_HALT_CFG, (1<<MB_ERR_AUTO_HALT_EN_SFT),
+                      MB_ERR_AUTO_HALT_EN_MSK);
+#endif
+    SET_TX_PAGE_LIMIT(sh->tx_info.tx_lowthreshold_page_trigger);
+    SET_TX_COUNT_LIMIT(sh->tx_info.tx_lowthreshold_id_trigger);
+    SET_TX_LIMIT_INT_EN(1);
+    ret = HAL_INI_HW_SEC_PHY_TABLE(sc);
+    if (ret)
+        goto exit;
+    ssv6006c_set_macaddr(sh, 0);
+    for (i=0; i<SSV6006_NUM_HW_BSSID; i++)
+        ssv6006c_set_bssid(sh, null_address, i);
+#ifdef CONFIG_SSV_HW_ENCRYPT_SW_DECRYPT
+    HAL_SET_RX_FLOW(sh, RX_DATA_FLOW, RX_HCI);
+#else
+    HAL_SET_RX_FLOW(sh, RX_DATA_FLOW, RX_CIPHER_MIC_HCI);
+#endif
+#if defined(CONFIG_P2P_NOA) || defined(CONFIG_RX_MGMT_CHECK)
+    HAL_SET_RX_FLOW(sh, RX_MGMT_FLOW, RX_CPU_HCI);
+#else
+    HAL_SET_RX_FLOW(sh, RX_MGMT_FLOW, RX_HCI);
+#endif
+    HAL_SET_RX_FLOW(sh, RX_CTRL_FLOW, RX_HCI);
+    HAL_SET_REPLAY_IGNORE(sh, 1);
+    HAL_UPDATE_DECISION_TABLE(sc);
+    SMAC_REG_SET_BITS(sc->sh, ADR_GLBLE_SET, SSV6XXX_OPMODE_STA, OP_MODE_MSK);
+    ssv6006c_sec_lut_setting(sh);
+    SMAC_REG_SET_BITS(sc->sh, ADR_MTX_RATERPT, M_ENG_HWHCI, MTX_RATERPT_HWID_MSK);
+    SET_PEERPS_REJECT_ENABLE(1);
+    SMAC_REG_WRITE(sh, ADR_AMPDU_SCOREBOAD_SIZE, sh->cfg.max_rx_aggr_size);
+exit:
+    return ret;
+}
+static void ssv6006c_reset_sysplf(struct ssv_hw *sh)
+{
+    SMAC_SYSPLF_RESET(sh, ADR_BRG_SW_RST, (1 << PLF_SW_RST_SFT));
+}
+static int ssv6006c_init_hw_sec_phy_table(struct ssv_softc *sc)
+{
+    struct ssv_hw *sh = sc->sh;
+    int i, ret = 0;
+    u32 *hw_buf_ptr = sh->hw_buf_ptr;
+    u32 *hw_sec_key = sh->hw_sec_key;
+    *hw_buf_ptr = ssv6006c_alloc_pbuf(sc, SSV6006_HW_SEC_TABLE_SIZE
+                                      , RX_BUF);
+    if((*hw_buf_ptr >> 28) != 8) {
+        dev_dbg(sc->dev, "opps allocate pbuf error\n");
+        WARN_ON(1);
+        ret = 1;
+        goto exit;
+    }
+    *hw_sec_key = *hw_buf_ptr;
+    for(i = 0; i < SSV6006_HW_SEC_TABLE_SIZE; i+=4) {
+        SMAC_REG_WRITE(sh, *hw_sec_key + i, 0);
+    }
+    SMAC_REG_SET_BITS(sh, ADR_SCRT_SET, ((*hw_sec_key >> 16) << SCRT_PKT_ID_SFT),
+                      SCRT_PKT_ID_MSK);
+exit:
+    return ret;
+}
+static int ssv6006c_write_mac_ini(struct ssv_hw *sh)
+{
+    return SSV6XXX_SET_HW_TABLE(sh, ssv6006c_mac_ini_table);
+}
+static int ssv6006c_set_rx_flow(struct ssv_hw *sh, enum ssv_rx_flow type, u32 rxflow)
+{
+    switch (type) {
+    case RX_DATA_FLOW:
+        return SMAC_REG_WRITE(sh, ADR_RX_FLOW_DATA, rxflow);
+    case RX_MGMT_FLOW:
+        return SMAC_REG_WRITE(sh, ADR_RX_FLOW_MNG, rxflow);
+    case RX_CTRL_FLOW:
+        return SMAC_REG_WRITE(sh, ADR_RX_FLOW_CTRL, rxflow);
+    default:
+        return 1;
+    }
+}
+static int ssv6006c_set_rx_ctrl_flow(struct ssv_hw *sh)
+{
+    return ssv6006c_set_rx_flow(sh, ADR_RX_FLOW_CTRL, RX_HCI);
+}
+static int ssv6006c_set_macaddr(struct ssv_hw *sh, int vif_idx)
+{
+    int ret = 0;
+    switch (vif_idx) {
+    case 0:
+        ret = SMAC_REG_WRITE(sh, ADR_STA_MAC_0, *((u32 *)&sh->cfg.maddr[0][0]));
+        if (!ret)
+            ret = SMAC_REG_WRITE(sh, ADR_STA_MAC_1, *((u32 *)&sh->cfg.maddr[0][4]));
+        break;
+    case 1:
+        ret = SMAC_REG_WRITE(sh, ADR_STA_MAC1_0, *((u32 *)&sh->cfg.maddr[1][0]));
+        if (!ret)
+            ret = SMAC_REG_WRITE(sh, ADR_STA_MAC1_1, *((u32 *)&sh->cfg.maddr[1][4]));
+        break;
+    default:
+        dev_dbg(sh->sc->dev, "Does not support set MAC address to HW for VIF %d\n", vif_idx);
+        ret = -1;
+        break;
+    }
+    return ret;
+}
+static int ssv6006c_set_bssid(struct ssv_hw *sh, u8 *bssid, int vif_idx)
+{
+    int ret = 0;
+    struct ssv_softc *sc = sh->sc;
+    switch (vif_idx) {
+    case 0:
+        memcpy(sc->bssid[vif_idx], bssid, 6);
+        ret = SMAC_REG_WRITE(sh, ADR_BSSID_0, *((u32 *)&sc->bssid[0][0]));
+        if (!ret)
+            ret = SMAC_REG_WRITE(sh, ADR_BSSID_1, *((u32 *)&sc->bssid[0][4]));
+        break;
+    case 1:
+        memcpy(sc->bssid[vif_idx], bssid, 6);
+        ret = SMAC_REG_WRITE(sh, ADR_BSSID1_0, *((u32 *)&sc->bssid[1][0]));
+        if (!ret)
+            ret = SMAC_REG_WRITE(sh, ADR_BSSID1_1, *((u32 *)&sc->bssid[1][4]));
+        break;
+    default:
+        dev_dbg(sc->dev, "Does not support set BSSID to HW for VIF %d\n", vif_idx);
+        ret = -1;
+        break;
+    }
+    return ret;
+}
+static u64 ssv6006c_get_ic_time_tag(struct ssv_hw *sh)
+{
+    u32 regval;
+    SMAC_REG_READ(sh, ADR_CHIP_DATE_YYYYMMDD, &regval);
+    sh->chip_tag = ((u64)regval<<32);
+    SMAC_REG_READ(sh, ADR_CHIP_DATE_00HHMMSS, &regval);
+    sh->chip_tag |= (regval);
+    return sh->chip_tag;
+}
+static void ssv6006c_get_chip_id(struct ssv_hw *sh)
+{
+    char *chip_id = sh->chip_id;
+    u32 regval;
+    SMAC_REG_READ(sh, ADR_CHIP_ID_3, &regval);
+    *((u32 *)&chip_id[0]) = __be32_to_cpu(regval);
+    SMAC_REG_READ(sh, ADR_CHIP_ID_2, &regval);
+    *((u32 *)&chip_id[4]) = __be32_to_cpu(regval);
+    SMAC_REG_READ(sh, ADR_CHIP_ID_1, &regval);
+    *((u32 *)&chip_id[8]) = __be32_to_cpu(regval);
+    SMAC_REG_READ(sh, ADR_CHIP_ID_0, &regval);
+    *((u32 *)&chip_id[12]) = __be32_to_cpu(regval);
+    chip_id[12+sizeof(u32)] = 0;;
+}
+static void ssv6006c_set_mrx_mode(struct ssv_hw *sh, u32 val)
+{
+    struct sk_buff *skb;
+    struct cfg_host_cmd *host_cmd;
+    int retval = 0;
+    skb = ssv_skb_alloc(sh->sc, HOST_CMD_HDR_LEN);
+    if (!skb) {
+        dev_dbg(sh->sc->dev, "%s(): Fail to alloc cmd buffer.\n", __FUNCTION__);
+    }
+    skb_put(skb, HOST_CMD_HDR_LEN);
+    host_cmd = (struct cfg_host_cmd *)skb->data;
+    memset(host_cmd, 0x0, sizeof(struct cfg_host_cmd));
+    host_cmd->c_type = HOST_CMD;
+    host_cmd->RSVD0 = ((val == MRX_MODE_NORMAL) ? SSV6XXX_MRX_NORMAL : SSV6XXX_MRX_PROMISCUOUS);
+    host_cmd->h_cmd = (u8)SSV6XXX_HOST_CMD_MRX_MODE;
+    host_cmd->len = skb->len;
+    retval = HCI_SEND_CMD(sh, skb);
+    if (retval)
+        dev_dbg(sh->sc->dev, "%s(): Fail to send mrx mode\n", __FUNCTION__);
+    ssv_skb_free(sh->sc, skb);
+    SMAC_REG_WRITE(sh, ADR_MRX_FLT_TB13, val);
+}
+static void ssv6006c_get_mrx_mode(struct ssv_hw *sh, u32 *val)
+{
+    SMAC_REG_READ(sh, ADR_MRX_FLT_TB13, val);
+}
+static void ssv6006c_save_hw_status(struct ssv_softc *sc)
+{
+    struct ssv_hw *sh = sc->sh;
+    int i = 0;
+    int address = 0;
+    u32 word_data = 0;
+    u32 sec_key_tbl_base = sh->hw_sec_key[0];
+    u32 sec_key_tbl = sec_key_tbl_base;
+    for (i = 0; i < sizeof(struct ssv6006_hw_sec); i += 4) {
+        address = sec_key_tbl + i;
+        SMAC_REG_READ(sh, address, &word_data);
+        sh->write_hw_config_cb(sh->write_hw_config_args, address, word_data);
+    }
+}
+static void ssv6006c_set_hw_wsid(struct ssv_softc *sc, struct ieee80211_vif *vif,
+                                 struct ieee80211_sta *sta, int wsid)
+{
+    struct ssv_sta_priv_data *sta_priv_dat=(struct ssv_sta_priv_data *)sta->drv_priv;
+    struct ssv_sta_info *sta_info;
+    sta_info = &sc->sta_info[wsid];
+    if (sta_priv_dat->sta_idx < SSV6006_NUM_HW_STA) {
+        u32 reg_peer_mac0[] = {ADR_PEER_MAC0_0, ADR_PEER_MAC1_0, ADR_PEER_MAC2_0, ADR_PEER_MAC3_0,
+                               ADR_PEER_MAC4_0, ADR_PEER_MAC5_0, ADR_PEER_MAC6_0, ADR_PEER_MAC7_0
+                              };
+        u32 reg_peer_mac1[] = {ADR_PEER_MAC0_1, ADR_PEER_MAC1_1, ADR_PEER_MAC2_1, ADR_PEER_MAC3_1,
+                               ADR_PEER_MAC4_1, ADR_PEER_MAC5_1, ADR_PEER_MAC6_1, ADR_PEER_MAC7_1
+                              };
+        SMAC_REG_WRITE(sc->sh, reg_peer_mac0[wsid], *((u32 *)&sta->addr[0]));
+        SMAC_REG_WRITE(sc->sh, reg_peer_mac1[wsid], *((u32 *)&sta->addr[4]));
+        SMAC_REG_WRITE(sc->sh, reg_wsid[wsid], 1);
+        sta_info->hw_wsid = sta_priv_dat->sta_idx;
+    }
+}
+static void ssv6006c_del_hw_wsid(struct ssv_softc *sc, int hw_wsid)
+{
+    if ((hw_wsid != -1) && (hw_wsid < SSV6006_NUM_HW_STA)) {
+        SMAC_REG_WRITE(sc->sh, reg_wsid[hw_wsid], 0x00);
+    }
+}
+static void ssv6006c_set_aes_tkip_hw_crypto_group_key (struct ssv_softc *sc,
+        struct ssv_vif_info *vif_info,
+        struct ssv_sta_info *sta_info,
+        void *param)
+{
+    int wsid = sta_info->hw_wsid;
+    int key_idx = *(u8 *)param;
+    if (wsid == (-1))
+        return;
+    BUG_ON(key_idx == 0);
+    dev_dbg(sc->dev, "Set CCMP/TKIP group key index %d to WSID %d.\n", key_idx, wsid);
+    if (vif_info->vif_priv != NULL)
+        dev_info(sc->dev, "Write group key index %d to VIF %d \n",
+                 key_idx, vif_info->vif_priv->vif_idx);
+    else
+        dev_err(sc->dev, "NULL VIF.\n");
+    ssv6006c_write_hw_group_keyidx(sc->sh, vif_info->vif_priv, key_idx);
+    HAL_ENABLE_FW_WSID(sc, sta_info->sta, sta_info, SSV6XXX_WSID_SEC_GROUP);
+}
+static void ssv6006c_write_pairwise_keyidx_to_hw(struct ssv_hw *sh, int key_idx, int wsid)
+{
+    int address = 0;
+    u32 Word_data = 0;
+    u32 sec_key_tbl_base = sh->hw_sec_key[0];
+    u32 sec_key_tbl = sec_key_tbl_base;
+    address = sec_key_tbl + (SSV_NUM_VIF * sizeof(struct ssv6006_bss))
+              + wsid * sizeof(struct ssv6006_hw_sta_key);
+    SMAC_REG_READ(sh, address, &Word_data);
+    Word_data = ((Word_data & 0xffffff00) | (u32)key_idx);
+    SMAC_REG_WRITE(sh, address, Word_data);
+}
+static void ssv6006c_write_hw_group_keyidx(struct ssv_hw *sh, struct ssv_vif_priv_data *vif_priv, int key_idx)
+{
+    int address = 0;
+    u32 Word_data = 0;
+    u32 sec_key_tbl_base = sh->hw_sec_key[0];
+    u32 sec_key_tbl = sec_key_tbl_base;
+    address = sec_key_tbl + vif_priv->vif_idx * sizeof(struct ssv6006_bss);
+    SMAC_REG_READ(sh, address, &Word_data);
+    Word_data = ((Word_data & 0xffffff00) | key_idx);
+    SMAC_REG_WRITE(sh, address, Word_data);
+}
+static int ssv6006c_write_pairwise_key_to_hw (struct ssv_softc *sc,
+        int index, u8 algorithm, const u8 *key, int key_len,
+        struct ieee80211_key_conf *keyconf,
+        struct ssv_vif_priv_data *vif_priv,
+        struct ssv_sta_priv_data *sta_priv)
+{
+    int wsid = (-1);
+    if (sta_priv == NULL) {
+        dev_err(sc->dev, "Set pair-wise key with NULL STA.\n");
+        return -EOPNOTSUPP;
+    }
+    wsid = sta_priv->sta_info->hw_wsid;
+    if ((wsid < 0) || (wsid >= SSV_NUM_STA)) {
+        dev_err(sc->dev, "Set pair-wise key to invalid WSID %d.\n", wsid);
+        return -EOPNOTSUPP;
+    }
+    dev_dbg(sc->dev, "Set STA %d's pair-wise key of %d bytes.\n", wsid, key_len);
+    ssv6006c_write_key_to_hw(sc, vif_priv, keyconf->key, wsid, index, SSV6XXX_WSID_SEC_PAIRWISE);
+    return 0;
+}
+static int ssv6006c_write_group_key_to_hw (struct ssv_softc *sc,
+        int index, u8 algorithm, const u8 *key, int key_len,
+        struct ieee80211_key_conf *keyconf,
+        struct ssv_vif_priv_data *vif_priv,
+        struct ssv_sta_priv_data *sta_priv)
+{
+    u32 sec_key_tbl_base = sc->sh->hw_sec_key[0];
+    int address = 0;
+    int *pointer = NULL;
+    int i;
+    int wsid = sta_priv ? sta_priv->sta_info->hw_wsid : (-1);
+    int ret = 0;
+    if (vif_priv == NULL) {
+        dev_err(sc->dev, "Setting group key to NULL VIF\n");
+        return -EOPNOTSUPP;
+    }
+    dev_dbg(sc->dev, "Setting VIF %d group key %d of length %d to WSID %d.\n",
+             vif_priv->vif_idx, index, key_len, wsid);
+    vif_priv->group_key_idx = index;
+    if (sta_priv)
+        sta_priv->group_key_idx = index;
+    address = sec_key_tbl_base
+              + (vif_priv->vif_idx * sizeof(struct ssv6006_bss))
+              + SSV6006_GROUP_KEY_OFFSET
+              + index * sizeof(struct ssv6006_hw_key);
+    pointer = (int *)key;
+    for (i = 0; i < (sizeof(struct ssv6006_hw_key)/4); i++)
+        SMAC_REG_WRITE(sc->sh, address+(i*4), *(pointer++));
+    WARN_ON(sc->vif_info[vif_priv->vif_idx].vif_priv == NULL);
+    ssv6xxx_foreach_vif_sta(sc, &sc->vif_info[vif_priv->vif_idx],
+                            ssv6006c_set_aes_tkip_hw_crypto_group_key, &index);
+    ret = 0;
+    return ret;
+}
+static void ssv6006c_write_key_to_hw(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv,
+                                     void *key, int wsid, int key_idx, enum SSV6XXX_WSID_SEC key_type)
+{
+    int address = 0;
+    int *pointer = NULL;
+    u32 sec_key_tbl_base = sc->sh->hw_sec_key[0];
+    u32 sec_key_tbl = sec_key_tbl_base;
+    int i;
+    switch (key_type) {
+    case SSV6XXX_WSID_SEC_PAIRWISE:
+        if(key_idx >= 0)
+            ssv6006c_write_pairwise_keyidx_to_hw(sc->sh, key_idx, wsid);
+        address = sec_key_tbl + (SSV_NUM_VIF * sizeof(struct ssv6006_bss))
+                  + (wsid * sizeof(struct ssv6006_hw_sta_key))
+                  + SSV6006_PAIRWISE_KEY_OFFSET;
+        pointer = (int *)key;
+        for (i = 0; i < (sizeof(struct ssv6006_hw_key)/4); i++)
+            SMAC_REG_WRITE(sc->sh, address+(i*4), *(pointer++));
+        break;
+    case SSV6XXX_WSID_SEC_GROUP:
+        if(key_idx < 0) {
+            dev_dbg(sc->dev, "invalid group key index %d.\n",key_idx);
+            return;
+        }
+        ssv6006c_write_hw_group_keyidx(sc->sh, vif_priv, key_idx);
+        address = sec_key_tbl
+                  + (vif_priv->vif_idx * sizeof(struct ssv6006_bss))
+                  + SSV6006_GROUP_KEY_OFFSET
+                  + key_idx * SSV6006_HW_KEY_SIZE;
+        pointer = (int *)key;
+        for (i = 0; i < (sizeof(struct ssv6006_hw_key)/4); i++)
+            SMAC_REG_WRITE(sc->sh, address+(i*4), *(pointer++));
+        break;
+    default:
+        dev_dbg(sc->dev, "invalid key type %d.",key_type);
+        break;
+    }
+}
+static void ssv6006c_set_pairwise_cipher_type(struct ssv_hw *sh, u8 cipher, u8 wsid)
+{
+    int address = 0;
+    u32 temp = 0;
+    u32 sec_key_tbl_base = sh->hw_sec_key[0];
+    u32 sec_key_tbl = sec_key_tbl_base;
+    address = sec_key_tbl + (SSV_NUM_VIF * sizeof(struct ssv6006_bss))
+              + (wsid * sizeof(struct ssv6006_hw_sta_key));
+    SMAC_REG_READ(sh, address, &temp);
+    temp = (temp & 0xffff00ff);
+    temp |= (cipher << 8);
+    SMAC_REG_WRITE(sh, address, temp);
+    dev_dbg(sh->sc->dev, "Set parewise key type %d\n", cipher);
+}
+static void ssv6006c_set_group_cipher_type(struct ssv_hw *sh, struct ssv_vif_priv_data *vif_priv, u8 cipher)
+{
+    int address = 0;
+    u32 temp = 0;
+    u32 sec_key_tbl_base = sh->hw_sec_key[0];
+    u32 sec_key_tbl = sec_key_tbl_base;
+    address = sec_key_tbl + (vif_priv->vif_idx * sizeof(struct ssv6006_bss));
+    SMAC_REG_READ(sh, address, &temp);
+    temp = (temp & 0xffff00ff);
+    temp |= (cipher << 8);
+    SMAC_REG_WRITE(sh, address, temp);
+    dev_dbg(sh->sc->dev, "Set group key type %d\n", cipher);
+}
+#ifdef CONFIG_PM
+static void ssv6006c_save_clear_trap_reason(struct ssv_softc *sc)
+{
+    u32 trap0, trap1;
+    SMAC_REG_READ(sc->sh, ADR_REASON_TRAP0, &trap0);
+    SMAC_REG_READ(sc->sh, ADR_REASON_TRAP1, &trap1);
+    SMAC_REG_WRITE(sc->sh, ADR_REASON_TRAP0, 0x00000000);
+    SMAC_REG_WRITE(sc->sh, ADR_REASON_TRAP1, 0x00000000);
+    dev_dbg(sc->dev, "trap0 %08x, trap1 %08x\n", trap0, trap1);
+    sc->trap_data.reason_trap0 = trap0;
+    sc->trap_data.reason_trap1 = trap1;
+}
+static void ssv6006c_restore_trap_reason(struct ssv_softc *sc)
+{
+    SMAC_REG_WRITE(sc->sh, ADR_REASON_TRAP0, sc->trap_data.reason_trap0);
+    SMAC_REG_WRITE(sc->sh, ADR_REASON_TRAP1, sc->trap_data.reason_trap1);
+}
+static void ssv6006c_pmu_awake(struct ssv_softc *sc)
+{
+#if 0
+    u32 dev_type = 0;
+    dev_type = HCI_DEVICE_TYPE(sh->hci.hci_ctrl);
+    if (dev_type == SSV_HWIF_INTERFACE_SDIO) {
+        SMAC_REG_SET_BITS(sc->sh, ADR_FN1_INT_CTRL_RESET, (1<<24), 0x01000000);
+        MDELAY(5);
+        SMAC_REG_SET_BITS(sc->sh, ADR_FN1_INT_CTRL_RESET, (0<<24), 0x01000000);
+    } else if (dev_type == SSV_HWIF_INTERFACE_USB) {
+        dev_dbg(sc->dev, "ssv6006c_pmu_awake: USB TODO\n");
+    }
+#endif
+}
+#endif
+static void ssv6006c_set_wep_hw_crypto_setting (struct ssv_softc *sc,
+        struct ssv_vif_info *vif_info, struct ssv_sta_info *sta_info,
+        void *param)
+{
+    int wsid = sta_info->hw_wsid;
+    struct ssv_sta_priv_data *sta_priv = (struct ssv_sta_priv_data *)sta_info->sta->drv_priv;
+    struct ssv_vif_priv_data *vif_priv = (struct ssv_vif_priv_data *)vif_info->vif->drv_priv;
+    if (wsid == (-1))
+        return;
+    sta_priv->has_hw_encrypt = vif_priv->has_hw_encrypt;
+    sta_priv->has_hw_decrypt = vif_priv->has_hw_decrypt;
+    sta_priv->need_sw_encrypt = vif_priv->need_sw_encrypt;
+    sta_priv->need_sw_decrypt = vif_priv->need_sw_decrypt;
+}
+static void ssv6006c_store_wep_key(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv,
+                                   struct ssv_sta_priv_data *sta_priv, enum SSV_CIPHER_E cipher, struct ieee80211_key_conf *key)
+{
+    if ((vif_priv->has_hw_decrypt == true) && (vif_priv->has_hw_encrypt == true)) {
+        dev_dbg(sc->dev, "Store WEP key index %d to HW group_key[%d] of VIF %d\n", key->keyidx, key->keyidx,vif_priv->vif_idx);
+        ssv6006c_write_key_to_hw(sc, vif_priv, key->key, 0, key->keyidx, SSV6XXX_WSID_SEC_GROUP);
+        ssv6xxx_foreach_vif_sta(sc, &sc->vif_info[vif_priv->vif_idx], ssv6006c_set_wep_hw_crypto_setting, key);
+    } else
+        dev_dbg(sc->dev, "Not support HW security\n");
+}
+static void ssv6006c_set_replay_ignore(struct ssv_hw *sh,u8 ignore)
+{
+    u32 temp;
+    SMAC_REG_READ(sh,ADR_SCRT_SET,&temp);
+    temp = temp & SCRT_RPLY_IGNORE_I_MSK;
+    temp |= (ignore << SCRT_RPLY_IGNORE_SFT);
+    SMAC_REG_WRITE(sh,ADR_SCRT_SET, temp);
+}
+static void ssv6006c_update_decision_table_6(struct ssv_hw *sh, u32 value)
+{
+    SMAC_REG_WRITE(sh, ADR_MRX_FLT_TB6, value);
+}
+static int ssv6006c_update_decision_table(struct ssv_softc *sc)
+{
+    int i;
+#ifndef USE_CONCURRENT_DECI_TBL
+    for(i=0; i<MAC_DECITBL1_SIZE; i++) {
+        SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_TB0+i*4,
+                       sc->mac_deci_tbl[i]);
+        SMAC_REG_CONFIRM(sc->sh, ADR_MRX_FLT_TB0+i*4,
+                         sc->mac_deci_tbl[i]);
+    }
+    for(i=0; i<MAC_DECITBL2_SIZE; i++) {
+        SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_EN0+i*4,
+                       sc->mac_deci_tbl[i+MAC_DECITBL1_SIZE]);
+        SMAC_REG_CONFIRM(sc->sh, ADR_MRX_FLT_EN0+i*4,
+                         sc->mac_deci_tbl[i+MAC_DECITBL1_SIZE]);
+    }
+#else
+    extern u16 concurrent_deci_tbl[];
+    for(i=0; i<MAC_DECITBL1_SIZE; i++) {
+        SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_TB0+i*4,
+                       concurrent_deci_tbl[i]);
+        SMAC_REG_CONFIRM(sc->sh, ADR_MRX_FLT_TB0+i*4,
+                         concurrent_deci_tbl[i]);
+    }
+    for(i=0; i<MAC_DECITBL2_SIZE; i++) {
+        SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_EN0+i*4,
+                       concurrent_deci_tbl[i+MAC_DECITBL1_SIZE]);
+        SMAC_REG_CONFIRM(sc->sh, ADR_MRX_FLT_EN0+i*4,
+                         concurrent_deci_tbl[i+MAC_DECITBL1_SIZE]);
+    }
+    SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_EN9,
+                   concurrent_deci_tbl[8]);
+    SMAC_REG_CONFIRM(sc->sh, ADR_MRX_FLT_EN10,
+                     concurrent_deci_tbl[9]);
+    SMAC_REG_CONFIRM(sc->sh, ADR_DUAL_IDX_EXTEND, 1);
+#endif
+    return 0;
+}
+static void ssv6006c_get_fw_version(struct ssv_hw *sh, u32 *regval)
+{
+    SMAC_REG_READ(sh, ADR_TX_SEG, regval);
+}
+static void ssv6006c_set_op_mode(struct ssv_hw *sh, u32 op_mode, int vif_idx)
+{
+    switch (vif_idx) {
+    case 0:
+        SMAC_REG_SET_BITS(sh, ADR_GLBLE_SET, op_mode, OP_MODE_MSK);
+        break;
+    case 1:
+        SMAC_REG_SET_BITS(sh, ADR_OP_MODE1, op_mode, OP_MODE1_MSK);
+        break;
+    default:
+        dev_dbg(sh->sc->dev, "Does not support set OP mode to HW for VIF %d\n", vif_idx);
+        break;
+    }
+}
+static void ssv6006c_set_halt_mngq_util_dtim(struct ssv_hw *sh, bool val)
+{
+#if 0
+    if (val) {
+        SMAC_REG_SET_BITS(sh, ADR_MTX_BCN_EN_MISC,
+                          MTX_HALT_MNG_UNTIL_DTIM_MSK, MTX_HALT_MNG_UNTIL_DTIM_MSK);
+    } else {
+        SMAC_REG_SET_BITS(sh, ADR_MTX_BCN_EN_MISC,
+                          0, MTX_HALT_MNG_UNTIL_DTIM_MSK);
+    }
+#endif
+}
+static void ssv6006c_set_dur_burst_sifs_g(struct ssv_hw *sh, u32 val)
+{
+}
+static void ssv6006c_set_dur_slot(struct ssv_hw *sh, u32 val)
+{
+    SET_SLOTTIME(val);
+}
+static void ssv6006c_set_sifs(struct ssv_hw *sh, int band)
+{
+    if (band == INDEX_80211_BAND_2GHZ) {
+        SET_SIFS(10);
+        SET_SIGEXT(6);
+    } else {
+        SET_SIFS(16);
+        SET_SIGEXT(0);
+    }
+}
+static void ssv6006c_set_qos_enable(struct ssv_hw *sh, bool val)
+{
+    SMAC_REG_SET_BITS(sh, ADR_GLBLE_SET,
+                      (val<<QOS_EN_SFT), QOS_EN_MSK);
+}
+static void ssv6006c_set_wmm_param(struct ssv_softc *sc,
+                                   const struct ieee80211_tx_queue_params *params, u16 queue)
+{
+    u32 cw;
+    u8 hw_txqid = sc->tx.hw_txqid[queue];
+    struct ssv_hw *sh = sc->sh;
+    cw = params->aifs&0xf;
+    cw|= ((ilog2(params->cw_min+1))&0xf)<<TXQ1_MTX_Q_ECWMIN_SFT;
+    cw|= ((ilog2(params->cw_max+1))&0xf)<<TXQ1_MTX_Q_ECWMAX_SFT;
+    cw|= ((params->txop)&0xff)<<TXQ1_MTX_Q_TXOP_LIMIT_SFT;
+    SMAC_REG_WRITE(sc->sh, ADR_TXQ0_MTX_Q_AIFSN+0x100*hw_txqid, cw);
+    if (params->aifs == 10) {
+        u32 dev_type = 0;
+        dev_type = HCI_DEVICE_TYPE(sc->sh->hci.hci_ctrl);
+        if ((dev_type == SSV_HWIF_INTERFACE_USB) && (sc->sh->cfg.tx_id_threshold == 0)) {
+            sc->sh->cfg.tx_id_threshold = SSV6006_ID_TX_THRESHOLD;
+            HAL_UPDATE_PAGE_ID(sh);
+            sc->sh->cfg.usb_hw_resource |= (USB_HW_RESOURCE_CHK_TXID | USB_HW_RESOURCE_CHK_TXPAGE);
+        }
+    }
+}
+static u32 ssv6006c_alloc_pbuf(struct ssv_softc *sc, int size, int type)
+{
+    u32 regval, pad;
+    int cnt = MAX_RETRY_COUNT;
+    int page_cnt = (size + ((1 << HW_MMU_PAGE_SHIFT) - 1)) >> HW_MMU_PAGE_SHIFT;
+    regval = 0;
+    mutex_lock(&sc->mem_mutex);
+    pad = size%4;
+    size += pad;
+    do {
+        SMAC_REG_WRITE(sc->sh, ADR_WR_ALC, (size | (type << 16)));
+        SMAC_REG_READ(sc->sh, ADR_WR_ALC, &regval);
+        if (regval == 0) {
+            cnt--;
+            msleep(1);
+        } else
+            break;
+    } while (cnt);
+    if (type == TX_BUF) {
+        sc->sh->tx_page_available -= page_cnt;
+        sc->sh->page_count[PACKET_ADDR_2_ID(regval)] = page_cnt;
+    }
+    mutex_unlock(&sc->mem_mutex);
+    if (regval == 0)
+        dev_err(sc->dev, "Failed to allocate packet buffer of %d bytes in %d type.",
+                size, type);
+    else {
+        dev_info(sc->dev, "Allocated %d type packet buffer of size %d (%d) at address %x.\n",
+                 type, size, page_cnt, regval);
+    }
+    return regval;
+}
+static inline bool ssv6006c_mcu_input_full(struct ssv_softc *sc)
+{
+    u32 regval=0;
+    SMAC_REG_READ(sc->sh, ADR_MCU_STATUS, &regval);
+    return (CH0_FULL_MSK & regval);
+}
+static bool ssv6006c_free_pbuf(struct ssv_softc *sc, u32 pbuf_addr)
+{
+    u32 regval=0;
+    u16 failCount=0;
+    u8 *p_tx_page_cnt = &sc->sh->page_count[PACKET_ADDR_2_ID(pbuf_addr)];
+    while (ssv6006c_mcu_input_full(sc)) {
+        if (failCount++ < 1000) continue;
+        dev_dbg(sc->dev, "=============>ERROR!!MAILBOX Block[%d]\n", failCount);
+        return false;
+    }
+    mutex_lock(&sc->mem_mutex);
+    regval = ((M_ENG_TRASH_CAN << HW_ID_OFFSET) |(pbuf_addr >> ADDRESS_OFFSET));
+    dev_dbg(sc->dev, "[A] ssv6xxx_pbuf_free addr[%08x][%x]\n", pbuf_addr, regval);
+    SMAC_REG_WRITE(sc->sh, ADR_CH0_TRIG_1, regval);
+    if (*p_tx_page_cnt) {
+        sc->sh->tx_page_available += *p_tx_page_cnt;
+        *p_tx_page_cnt = 0;
+    }
+    mutex_unlock(&sc->mem_mutex);
+    return true;
+}
+static void ssv6006c_ampdu_auto_crc_en(struct ssv_hw *sh)
+{
+    SMAC_REG_SET_BITS(sh, ADR_MTX_MISC_EN, (0x1 << MTX_AMPDU_CRC8_AUTO_SFT),
+                      MTX_AMPDU_CRC8_AUTO_MSK);
+}
+static void ssv6006c_set_rx_ba(struct ssv_hw *sh, bool on, u8 *ta,
+                               u16 tid, u16 ssn, u8 buf_size)
+{
+#if 0
+    if (on) {
+        SMAC_REG_WRITE(sh, ADR_BA_CTRL,
+                       (1 << BA_AGRE_EN_SFT)| (0x01 << BA_CTRL_SFT));
+    } else {
+        if (sh->sc->rx_ba_session_count == 0)
+            SMAC_REG_WRITE(sh, ADR_BA_CTRL, 0x0);
+    }
+#endif
+    SET_BA_TID (0xf);
+}
+static u8 ssv6006c_read_efuse(struct ssv_hw *sh, u8 *pbuf)
+{
+    u32 val,i,j;
+    if (GET_EFS_RD_FLAG != 1) {
+        SET_EFS_RD_KICK(1);
+        i = 0;
+        while (!GET_EFS_PROGRESS_DONE) {
+            i++;
+            udelay(100);
+            if ( i > 10000) {
+                dev_dbg(sh->sc->dev, "EFUSE read error!!\n");
+                break;
+            }
+        }
+    }
+    sh->cfg.chip_identity = REG32(ADR_EFUSE_WDATA_0_0);
+    sh->cfg.chip_identity &= 0xff000000;
+    for (i = 0; i < (EFUSE_MAX_SECTION_MAP); i++) {
+        val = REG32(ADR_EFUSE_WDATA_0_1+i*4);
+        for ( j = 0; j < 4; j++)
+            *pbuf++ = ((val >> j*8) & 0xff);
+    }
+    return 1;
+}
+static void ssv6006c_write_efuse(struct ssv_hw *sh, u8 *data, u8 data_length)
+{
+    int i = 0x0;
+    u8 loop = 0x0;
+    u32 temp_value = 0x0;
+    u32 align_4_byte = 0x0;
+    u32 efuse_start_addr = 0x0;
+    efuse_start_addr = ADR_EFUSE_WDATA_0_1;
+    loop = data_length / 4;
+    align_4_byte = (data_length % 4)?(data_length % 4):0;
+    for(i = 0; i < 8; i++) {
+        REG32_W(efuse_start_addr + (i * 4), 0x0);
+    }
+    for(i = 0; i < loop; i++) {
+        temp_value = (data[(i * 4)+3] << 24) + (data[(i * 4)+2] << 16) + (data[(i * 4)+1] << 8) + (data[(i * 4)] << 0);
+        REG32_W(efuse_start_addr + (i * 4), temp_value);
+    }
+    temp_value = 0;
+    for (i = 0; i < align_4_byte; i++) {
+        temp_value += data[loop * 4 + i] << (i * 8);
+        REG32_W(efuse_start_addr + (loop * 4), temp_value);
+    }
+    SET_RG_EN_LDO_EFUSE(0x1);
+    SET_EFS_VDDQ_EN(0x1);
+    SET_EFS_WR_KICK(0x1);
+    do {
+        temp_value = GET_EFS_PROGRESS_DONE;
+    } while (0 == temp_value);
+    SET_RG_EN_LDO_EFUSE(0x0);
+    SET_EFS_VDDQ_EN(0x0);
+}
+#define CLK_SRC_SYNTH_40M 4
+#define CLK_80M_PHY 8
+static int ssv6006c_chg_clk_src(struct ssv_hw *sh)
+{
+#if 0
+    int ret = 0;
+    if (sh->cfg.clk_src_80m)
+        ret = SMAC_REG_WRITE(sh, ADR_CLOCK_SELECTION, CLK_80M_PHY);
+    else
+        ret = SMAC_REG_WRITE(sh, ADR_CLOCK_SELECTION, CLK_SRC_SYNTH_40M);
+    msleep(1);
+#endif
+    return 0;
+}
+static enum ssv6xxx_beacon_type ssv6006c_beacon_get_valid_cfg(struct ssv_hw *sh)
+{
+    u32 regval =0;
+    SMAC_REG_READ(sh, ADR_MTX_BCN_MISC, &regval);
+    regval &= MTX_BCN_CFG_VLD_MSK;
+    regval = regval >> MTX_BCN_CFG_VLD_SFT;
+    if(regval==0x2 || regval == 0x0)
+        return SSV6xxx_BEACON_0;
+    else if(regval==0x1)
+        return SSV6xxx_BEACON_1;
+    else
+        dev_dbg(sh->sc->dev, "=============>ERROR!!drv_bcn_reg_available\n");
+    return SSV6xxx_BEACON_0;
+}
+static void ssv6006c_set_beacon_reg_lock(struct ssv_hw *sh, bool val)
+{
+    struct ssv_softc *sc = sh->sc;
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_BEACON,
+             "ssv6xxx_beacon_reg_lock   val[0x:%08x]\n ", val);
+    SMAC_REG_SET_BITS(sh, ADR_MTX_BCN_MISC,
+                      val<<MTX_BCN_PKTID_CH_LOCK_SFT, MTX_BCN_PKTID_CH_LOCK_MSK);
+}
+static void ssv6006c_set_beacon_id_dtim(struct ssv_softc *sc,
+                                        enum ssv6xxx_beacon_type avl_bcn_type, int dtim_offset)
+{
+#define BEACON_HDR_LEN 24
+    struct ssv_hw *sh = sc->sh;
+    dtim_offset -= BEACON_HDR_LEN;
+    if (avl_bcn_type == SSV6xxx_BEACON_1) {
+        SET_MTX_BCN_PKT_ID1(PBUF_MapPkttoID(sc->beacon_info[avl_bcn_type].pubf_addr));
+        SET_MTX_DTIM_OFST1(dtim_offset);
+    } else {
+        SET_MTX_BCN_PKT_ID0(PBUF_MapPkttoID(sc->beacon_info[avl_bcn_type].pubf_addr));
+        SET_MTX_DTIM_OFST0(dtim_offset);
+    }
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_BEACON,
+             " update beacon %d, pktid %d, dtim offset %d \n", avl_bcn_type,
+             sc->beacon_info[avl_bcn_type].pubf_addr, dtim_offset);
+}
+static void ssv6006c_fill_beacon(struct ssv_softc *sc, u32 regaddr, struct sk_buff *skb)
+{
+    u8 *beacon = skb->data;
+    u32 i, j, val;
+    int size;
+    size = (skb->len)/4;
+    if (0 != (skb->len % 4))
+        size++;
+    for(i = 0; i < size; i++) {
+        val = 0;
+        for ( j = 0; j < 4; j ++) {
+            val += (*beacon++) << j*8;
+        }
+        dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_BEACON, "[%08x] ", val );
+        SMAC_REG_WRITE(sc->sh, regaddr+i*4, val);
+    }
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_BEACON, "\n");
+}
+static void ssv6006_send_soft_beacon_cmd(struct ssv_hw *sh, bool bEnable)
+{
+    struct sk_buff *skb;
+    struct cfg_host_cmd *host_cmd;
+    int retval = 0;
+    skb = ssv_skb_alloc(sh->sc, HOST_CMD_HDR_LEN);
+    if (!skb) {
+        dev_dbg(sh->sc->dev, "%s(): Fail to alloc cmd buffer.\n", __FUNCTION__);
+    }
+    skb_put(skb, HOST_CMD_HDR_LEN);
+    host_cmd = (struct cfg_host_cmd *)skb->data;
+    memset(host_cmd, 0x0, sizeof(struct cfg_host_cmd));
+    host_cmd->c_type = HOST_CMD;
+    host_cmd->RSVD0 = (bEnable ? SSV6XXX_SOFT_BEACON_START : SSV6XXX_SOFT_BEACON_STOP);
+    host_cmd->h_cmd = (u8)SSV6XXX_HOST_CMD_SOFT_BEACON;
+    host_cmd->len = skb->len;
+    retval = HCI_SEND_CMD(sh, skb);
+    if (retval)
+        dev_dbg(sh->sc->dev, "%s(): Fail to send soft beacon cmd\n", __FUNCTION__);
+    ssv_skb_free(sh->sc, skb);
+}
+static bool ssv6006c_beacon_enable(struct ssv_softc *sc, bool bEnable)
+{
+    u32 regval = 0;
+    bool ret = 0;
+    if (bEnable && !sc->beacon_usage) {
+        dev_dbg(sc->dev, "[A] Reject to set beacon!!!. ssv6xxx_beacon_enable bEnable[%d] sc->beacon_usage[%d]\n",
+               bEnable,sc->beacon_usage);
+        sc->enable_beacon = BEACON_WAITING_ENABLED;
+        return ret;
+    }
+    if((bEnable && (BEACON_ENABLED & sc->enable_beacon))||
+       (!bEnable && !sc->enable_beacon)) {
+        dev_dbg(sc->dev, "[A] ssv6xxx_beacon_enable bEnable[%d] and sc->enable_beacon[%d] are the same. no need to execute.\n",
+               bEnable,sc->enable_beacon);
+        if(bEnable) {
+            dev_dbg(sc->dev, "        Ignore enable beacon cmd!!!!\n");
+            return ret;
+        }
+    }
+    if (sc->sc_flags & SSV6200_HW_CAP_BEACON) {
+        SMAC_REG_READ(sc->sh, ADR_MTX_BCN_EN_MISC, &regval);
+        dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_BEACON,
+                 "[A] ssv6xxx_beacon_enable read misc reg val [%08x]\n", regval);
+        regval &= MTX_BCN_TIMER_EN_I_MSK;
+        dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_BEACON,
+                 "[A] ssv6xxx_beacon_enable read misc reg val [%08x]\n", regval);
+        regval |= (bEnable << MTX_BCN_TIMER_EN_SFT);
+        ret = SMAC_REG_WRITE(sc->sh, ADR_MTX_BCN_EN_MISC, regval);
+        dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_BEACON,
+                 "[A] ssv6xxx_beacon_enable read misc reg val [%08x]\n", regval);
+    } else {
+        ssv6006_send_soft_beacon_cmd(sc->sh, bEnable);
+    }
+    sc->enable_beacon = (bEnable==true)?BEACON_ENABLED:0;
+    return ret;
+}
+static void ssv6006c_set_beacon_info(struct ssv_hw *sh, u8 beacon_interval, u8 dtim_cnt)
+{
+    struct ssv_softc *sc = sh->sc;
+    if(beacon_interval==0)
+        beacon_interval = 100;
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_BEACON,
+             "[A] BSS_CHANGED_BEACON_INT beacon_int[%d] dtim_cnt[%d]\n", beacon_interval, (dtim_cnt));
+    SET_MTX_BCN_PERIOD(beacon_interval);
+    if (sh->cfg.hw_caps & SSV6200_HW_CAP_BEACON) {
+        SET_MTX_DTIM_NUM(dtim_cnt);
+        SET_MTX_DTIM_CNT_AUTO_FILL(1);
+    }
+    SET_MTX_BCN_AUTO_SEQ_NO(1);
+    SET_MTX_TIME_STAMP_AUTO_FILL(1);
+}
+static bool ssv6006c_get_bcn_ongoing(struct ssv_hw *sh)
+{
+    u32 regval;
+    SMAC_REG_READ(sh, ADR_MTX_BCN_MISC, &regval);
+    return ((MTX_AUTO_BCN_ONGOING_MSK & regval) >> MTX_AUTO_BCN_ONGOING_SFT);
+}
+static void ssv6006c_beacon_loss_enable(struct ssv_hw *sh)
+{
+    SET_RG_RX_MONITOR_ON(1);
+}
+static void ssv6006c_beacon_loss_disable(struct ssv_hw *sh)
+{
+    SET_RG_RX_MONITOR_ON(0);
+}
+static void ssv6006c_beacon_loss_config(struct ssv_hw *sh, u16 beacon_int, const u8 *bssid)
+{
+    struct ssv_softc *sc = sh->sc;
+    u32 mac_31_0;
+    u16 mac_47_32;
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_BEACON,
+             "%s(): beacon_int %x, bssid %02x:%02x:%02x:%02x:%02x:%02x\n",
+             __FUNCTION__, beacon_int, bssid[0], bssid[1], bssid[2], bssid[3], bssid[4], bssid[5]);
+    memcpy(&mac_31_0, bssid, 4);
+    memcpy(&mac_47_32, bssid+4, 2);
+    ssv6006c_beacon_loss_disable(sh);
+    SET_RG_RX_BEACON_INTERVAL(beacon_int);
+    SET_RG_RX_BEACON_LOSS_CNT_LMT(10);
+    SET_RG_RX_PKT_FC(0x0080);
+    SET_RG_RX_PKT_ADDR1_ON(0);
+    SET_RG_RX_PKT_ADDR2_ON(0);
+    SET_RG_RX_PKT_ADDR3_ON(1);
+    SET_RG_RX_PKT_ADDR3_31_0((u32)mac_31_0);
+    SET_RG_RX_PKT_ADDR3_47_32((u16)mac_47_32);
+    ssv6006c_beacon_loss_enable(sh);
+    return;
+}
+static void ssv6006c_update_txq_mask(struct ssv_hw *sh, u32 txq_mask)
+{
+    SMAC_REG_SET_BITS(sh, ADR_MTX_MISC_EN,
+                      (txq_mask << MTX_HALT_Q_MB_SFT), MTX_HALT_Q_MB_MSK);
+}
+static void ssv6006c_readrg_hci_inq_info(struct ssv_hw *sh, int *hci_used_id, int *tx_use_page)
+{
+    int ret = 0;
+    u32 regval = 0;
+    ret = SMAC_REG_READ(sh, ADR_RD_IN_FFCNT1, &regval);
+    if (ret == 0)
+        *hci_used_id = ((regval & FF1_CNT_MSK) >> FF1_CNT_SFT);
+    ret = SMAC_REG_READ(sh, ADR_TX_ID_ALL_INFO, &regval);
+    if (ret == 0)
+        *tx_use_page = ((regval & TX_PAGE_USE_7_0_MSK) >> TX_PAGE_USE_7_0_SFT);
+}
+#define MAX_HW_TXQ_INFO_LEN 2
+static bool ssv6006c_readrg_txq_info(struct ssv_hw *sh, u32 *txq_info, int *hci_used_id)
+{
+    int ret = 0;
+    u32 addr[MAX_HW_TXQ_INFO_LEN], value[MAX_HW_TXQ_INFO_LEN];
+    u32 dev_type = HCI_DEVICE_TYPE(sh->hci.hci_ctrl);
+    addr[0] = ADR_TX_ID_ALL_INFO;
+    addr[1] = ADR_RD_IN_FFCNT1;
+    if (dev_type == SSV_HWIF_INTERFACE_SDIO) {
+        ret = SMAC_BURST_REG_READ(sh, addr, value, MAX_HW_TXQ_INFO_LEN);
+        if (ret == 0) {
+            *txq_info = value[0];
+            *hci_used_id = ((value[1] & FF1_CNT_MSK) >> FF1_CNT_SFT);
+        }
+    } else {
+        ret = SMAC_REG_READ(sh, addr[0], &value[0]);
+        if (ret == 0) {
+            *txq_info = value[0];
+        }
+        ret = SMAC_REG_READ(sh, addr[1], &value[1]);
+        if (ret == 0) {
+            *hci_used_id = ((value[1] & FF1_CNT_MSK) >> FF1_CNT_SFT);
+        }
+    }
+    return ret;
+}
+static bool ssv6006c_readrg_txq_info2(struct ssv_hw *sh, u32 *txq_info2, int *hci_used_id)
+{
+    int ret = 0;
+    u32 addr[MAX_HW_TXQ_INFO_LEN], value[MAX_HW_TXQ_INFO_LEN];
+    u32 dev_type = HCI_DEVICE_TYPE(sh->hci.hci_ctrl);
+    addr[0] = ADR_TX_ID_ALL_INFO2;
+    addr[1] = ADR_RD_IN_FFCNT1;
+    if (dev_type == SSV_HWIF_INTERFACE_SDIO) {
+        ret = SMAC_BURST_REG_READ(sh, addr, value, MAX_HW_TXQ_INFO_LEN);
+        if (ret == 0) {
+            *txq_info2 = value[0];
+            *hci_used_id = ((value[1] & FF1_CNT_MSK) >> FF1_CNT_SFT);
+        }
+    } else {
+        ret = SMAC_REG_READ(sh, addr[0], &value[0]);
+        if (ret == 0) {
+            *txq_info2 = value[0];
+        }
+        ret = SMAC_REG_READ(sh, addr[1], &value[1]);
+        if (ret == 0) {
+            *hci_used_id = ((value[1] & FF1_CNT_MSK) >> FF1_CNT_SFT);
+        }
+    }
+    return ret;
+}
+static bool ssv6006c_dump_wsid(struct ssv_hw *sh)
+{
+    const u8 *op_mode_str[]= {"STA", "AP", "AD-HOC", "WDS"};
+    const u8 *ht_mode_str[]= {"Non-HT", "HT-MF", "HT-GF", "RSVD"};
+    u32 regval;
+    int s;
+    struct ssv_cmd_data *cmd_data = &sh->sc->cmd_data;
+    for (s = 0; s < SSV6006_NUM_HW_STA; s++) {
+        SMAC_REG_READ(sh, reg_wsid[s], &regval);
+        snprintf_res(cmd_data, "==>WSID[%d]\n\tvalid[%d] qos[%d] op_mode[%s] ht_mode[%s]\n",
+                     s, regval&0x1, (regval>>1)&0x1, op_mode_str[((regval>>2)&3)], ht_mode_str[((regval>>4)&3)]);
+        SMAC_REG_READ(sh, reg_wsid[s]+4, &regval);
+        snprintf_res(cmd_data, "\tMAC[%02x:%02x:%02x:%02x:",
+                     (regval&0xff), ((regval>>8)&0xff), ((regval>>16)&0xff), ((regval>>24)&0xff));
+        SMAC_REG_READ(sh, reg_wsid[s]+8, &regval);
+        snprintf_res(cmd_data, "%02x:%02x]\n",
+                     (regval&0xff), ((regval>>8)&0xff));
+    }
+    return 0;
+}
+static bool ssv6006c_dump_decision(struct ssv_hw *sh)
+{
+    u32 addr, regval;
+    int s;
+    struct ssv_cmd_data *cmd_data = &sh->sc->cmd_data;
+    snprintf_res(cmd_data, ">> Decision Table:\n");
+    for(s = 0, addr = ADR_MRX_FLT_TB0; s < 16; s++, addr+=4) {
+        SMAC_REG_READ(sh, addr, &regval);
+        snprintf_res(cmd_data, "   [%d]: ADDR[0x%08x] = 0x%08x\n",
+                     s, addr, regval);
+    }
+    snprintf_res(cmd_data, "\n\n>> Decision Mask:\n");
+    for (s = 0, addr = ADR_MRX_FLT_EN0; s < 9; s++, addr+=4) {
+        SMAC_REG_READ(sh, addr, &regval);
+        snprintf_res(cmd_data, "   [%d]: ADDR[0x%08x] = 0x%08x\n",
+                     s, addr, regval);
+    }
+    snprintf_res(cmd_data, "\n\n");
+    return 0;
+}
+static u32 ssv6006c_get_ffout_cnt(u32 value, int tag)
+{
+    switch (tag) {
+    case M_ENG_CPU:
+        return ((value & FFO0_CNT_MSK) >> FFO0_CNT_SFT);
+    case M_ENG_HWHCI:
+        return ((value & FFO1_CNT_MSK) >> FFO1_CNT_SFT);
+    case M_ENG_ENCRYPT:
+        return ((value & FFO3_CNT_MSK) >> FFO3_CNT_SFT);
+    case M_ENG_MACRX:
+        return ((value & FFO4_CNT_MSK) >> FFO4_CNT_SFT);
+    case M_ENG_MIC:
+        return ((value & FFO5_CNT_MSK) >> FFO5_CNT_SFT);
+    case M_ENG_TX_EDCA0:
+        return ((value & FFO6_CNT_MSK) >> FFO6_CNT_SFT);
+    case M_ENG_TX_EDCA1:
+        return ((value & FFO7_CNT_MSK) >> FFO7_CNT_SFT);
+    case M_ENG_TX_EDCA2:
+        return ((value & FFO8_CNT_MSK) >> FFO8_CNT_SFT);
+    case M_ENG_TX_EDCA3:
+        return ((value & FFO9_CNT_MSK) >> FFO9_CNT_SFT);
+    case M_ENG_TX_MNG:
+        return ((value & FFO10_CNT_MSK) >> FFO10_CNT_SFT);
+    case M_ENG_ENCRYPT_SEC:
+        return ((value & FFO11_CNT_MSK) >> FFO11_CNT_SFT);
+    case M_ENG_MIC_SEC:
+        return ((value & FFO12_CNT_MSK) >> FFO12_CNT_SFT);
+    case M_ENG_TRASH_CAN:
+        return ((value & FFO15_CNT_MSK) >> FFO15_CNT_SFT);
+    default:
+        return 0;
+    }
+}
+static u32 ssv6006c_get_in_ffcnt(u32 value, int tag)
+{
+    switch (tag) {
+    case M_ENG_CPU:
+        return ((value & FF0_CNT_MSK) >> FF0_CNT_SFT);
+    case M_ENG_HWHCI:
+        return ((value & FF1_CNT_MSK) >> FF1_CNT_SFT);
+    case M_ENG_ENCRYPT:
+        return ((value & FF3_CNT_MSK) >> FF3_CNT_SFT);
+    case M_ENG_MACRX:
+        return ((value & FF4_CNT_MSK) >> FF4_CNT_SFT);
+    case M_ENG_MIC:
+        return ((value & FF5_CNT_MSK) >> FF5_CNT_SFT);
+    case M_ENG_TX_EDCA0:
+        return ((value & FF6_CNT_MSK) >> FF6_CNT_SFT);
+    case M_ENG_TX_EDCA1:
+        return ((value & FF7_CNT_MSK) >> FF7_CNT_SFT);
+    case M_ENG_TX_EDCA2:
+        return ((value & FF8_CNT_MSK) >> FF8_CNT_SFT);
+    case M_ENG_TX_EDCA3:
+        return ((value & FF9_CNT_MSK) >> FF9_CNT_SFT);
+    case M_ENG_TX_MNG:
+        return ((value & FF10_CNT_MSK) >> FF10_CNT_SFT);
+    case M_ENG_ENCRYPT_SEC:
+        return ((value & FF11_CNT_MSK) >> FF11_CNT_SFT);
+    case M_ENG_MIC_SEC:
+        return ((value & FF12_CNT_MSK) >> FF12_CNT_SFT);
+    case M_ENG_TRASH_CAN:
+        return ((value & FF15_CNT_MSK) >> FF15_CNT_SFT);
+    default:
+        return 0;
+    }
+}
+static void ssv6006c_read_ffout_cnt(struct ssv_hw *sh,
+                                    u32 *value, u32 *value1, u32 *value2)
+{
+    SMAC_REG_READ(sh, ADR_RD_FFOUT_CNT1, value);
+    SMAC_REG_READ(sh, ADR_RD_FFOUT_CNT2, value1);
+    SMAC_REG_READ(sh, ADR_RD_FFOUT_CNT3, value2);
+}
+static void ssv6006c_read_in_ffcnt(struct ssv_hw *sh,
+                                   u32 *value, u32 *value1)
+{
+    SMAC_REG_READ(sh, ADR_RD_IN_FFCNT1, value);
+    SMAC_REG_READ(sh, ADR_RD_IN_FFCNT2, value1);
+}
+static void ssv6006c_read_id_len_threshold(struct ssv_hw *sh,
+        u32 *tx_len, u32 *rx_len)
+{
+    u32 regval = 0;
+    if(SMAC_REG_READ(sh, ADR_ID_LEN_THREADSHOLD2, &regval));
+    *tx_len = ((regval & TX_ID_ALC_LEN_MSK) >> TX_ID_ALC_LEN_SFT);
+    *rx_len = ((regval & RX_ID_ALC_LEN_MSK) >> RX_ID_ALC_LEN_SFT);
+}
+static void ssv6006c_read_tag_status(struct ssv_hw *sh,
+                                     u32 *ava_status)
+{
+    u32 regval = 0;
+    if(SMAC_REG_READ(sh, ADR_TAG_STATUS, &regval));
+    *ava_status = ((regval & AVA_TAG_MSK) >> AVA_TAG_SFT);
+}
+void ssv6006c_reset_mib_mac(struct ssv_hw *sh)
+{
+    SMAC_REG_WRITE(sh, ADR_MIB_EN, 0);
+    msleep(1);
+    SMAC_REG_WRITE(sh, ADR_MIB_EN, 0xffffffff);
+}
+static void ssv6006c_reset_mib(struct ssv_hw *sh)
+{
+    ssv6006c_reset_mib_mac(sh);
+    HAL_RESET_MIB_PHY(sh);
+}
+static void ssv6006c_list_mib(struct ssv_hw *sh)
+{
+    u32 addr, value;
+    int i;
+    struct ssv_cmd_data *cmd_data = &sh->sc->cmd_data;
+    addr = MIB_REG_BASE;
+    for (i = 0; i < 120; i++, addr+=4) {
+        SMAC_REG_READ(sh, addr, &value);
+        snprintf_res(cmd_data, "%08x ", value);
+        if (((i+1) & 0x07) == 0)
+            snprintf_res(cmd_data, "\n");
+    }
+    snprintf_res(cmd_data, "\n");
+}
+static void ssv6006c_dump_mib_rx(struct ssv_hw *sh)
+{
+    u32 value;
+    struct ssv_cmd_data *cmd_data = &sh->sc->cmd_data;
+    snprintf_res(cmd_data, "HWHCI status:\n");
+    snprintf_res(cmd_data, "%-12s\t%-12s\t%-12s\t%-12s\n",
+                 "HCI_RX_PKT_CNT", "HCI_RX_DROP_CNT", "HCI_RX_TRAP_CNT", "HCI_RX_FAIL_CNT");
+    snprintf_res(cmd_data, "[%08x]\t", GET_RX_PKT_COUNTER);
+    snprintf_res(cmd_data, "[%08x]\t", GET_RX_PKT_DROP_COUNTER);
+    snprintf_res(cmd_data, "[%08x]\t", GET_RX_PKT_TRAP_COUNTER);
+    snprintf_res(cmd_data, "[%08x]\n\n", GET_HOST_RX_FAIL_COUNTER);
+    snprintf_res(cmd_data, "MAC RX status:\n");
+    snprintf_res(cmd_data, "%-12s\t%-12s\t%-12s\t%-12s\n",
+                 "MRX_FCS_SUCC", "MRX_FCS_ERR", "MRX_ALC_FAIL", "MRX_MISS");
+    SMAC_REG_READ(sh, ADR_MRX_FCS_SUCC, &value);
+    snprintf_res(cmd_data, "[%08x]\t", value);
+    SMAC_REG_READ(sh, ADR_MRX_FCS_ERR, &value);
+    snprintf_res(cmd_data, "[%08x]\t", value);
+    SMAC_REG_READ(sh, ADR_MRX_ALC_FAIL, &value);
+    snprintf_res(cmd_data, "[%08x]\t", value);
+    SMAC_REG_READ(sh, ADR_MRX_MISS, &value);
+    snprintf_res(cmd_data, "[%08x]\n", value);
+    snprintf_res(cmd_data, "%-12s\t%-12s\t%-12s\t%-12s\n",
+                 "MRX_MB_MISS", "MRX_NIDLE_MISS", "LEN_ALC_FAIL", "LEN_CRC_FAIL");
+    SMAC_REG_READ(sh, ADR_MRX_MB_MISS, &value);
+    snprintf_res(cmd_data, "[%08x]\t", value);
+    SMAC_REG_READ(sh, ADR_MRX_NIDLE_MISS, &value);
+    snprintf_res(cmd_data, "[%08x]\t", value);
+    SMAC_REG_READ(sh, ADR_DBG_LEN_ALC_FAIL, &value);
+    snprintf_res(cmd_data, "[%08x]\t", value);
+    SMAC_REG_READ(sh, ADR_DBG_LEN_CRC_FAIL, &value);
+    snprintf_res(cmd_data, "[%08x]\n", value);
+    snprintf_res(cmd_data, "%-12s\t%-12s\t%-12s\t%-12s\n",
+                 "DBG_AMPDU_PASS", "DBG_AMPDU_FAIL", "ID_ALC_FAIL1", "ID_ALC_FAIL2");
+    SMAC_REG_READ(sh, ADR_DBG_AMPDU_PASS, &value);
+    snprintf_res(cmd_data, "[%08x]\t", value);
+    SMAC_REG_READ(sh, ADR_DBG_AMPDU_FAIL, &value);
+    snprintf_res(cmd_data, "[%08x]\t", value);
+    SMAC_REG_READ(sh, ADR_ID_ALC_FAIL1, &value);
+    snprintf_res(cmd_data, "[%08x]\t", value);
+    SMAC_REG_READ(sh, ADR_ID_ALC_FAIL2, &value);
+    snprintf_res(cmd_data, "[%08x]\n\n", value);
+    HAL_DUMP_MIB_RX_PHY(sh);
+}
+static void ssv6006c_dump_mib_tx(struct ssv_hw *sh)
+{
+    struct ssv_cmd_data *cmd_data = &sh->sc->cmd_data;
+    snprintf_res(cmd_data, "HWHCI status:\n");
+    snprintf_res(cmd_data, "  %-16s  :%08x\t%-16s  :%08x\n",
+                 "HCI_TX_ALLOC_CNT", GET_HCI_TX_ALLOC_CNT, "HCI_TX_PKT_CNT", GET_TX_PKT_COUNTER);
+    snprintf_res(cmd_data, "  %-16s  :%08x\t%-16s  :%08x\n",
+                 "HCI_TX_DROP_CNT", GET_TX_PKT_DROP_COUNTER, "HCI_TX_TRAP_CNT", GET_TX_PKT_TRAP_COUNTER);
+    snprintf_res(cmd_data, "  %-16s  :%08x\n\n", "HCI_TX_FAIL_CNT", GET_HOST_TX_FAIL_COUNTER);
+    snprintf_res(cmd_data, "MAC TX status:\n");
+    snprintf_res(cmd_data, "  %-16s  :%08d\t%-16s  :%08d\n", "Tx Group"
+                 , GET_MTX_GRP,"Tx Fail", GET_MTX_FAIL);
+    snprintf_res(cmd_data, "  %-16s  :%08d\t%-16s  :%08d\n", "Tx Retry"
+                 , GET_MTX_RETRY,"Tx Multi Retry", GET_MTX_MULTI_RETRY);
+    snprintf_res(cmd_data, "  %-16s  :%08d\t%-16s  :%08d\n", "Tx RTS success"
+                 , GET_MTX_RTS_SUCC,"Tx RTS Fail", GET_MTX_RTS_FAIL);
+    snprintf_res(cmd_data, "  %-16s  :%08d\t%-16s  :%08d\n", "Tx ACK Fail"
+                 , GET_MTX_ACK_FAIL,"Tx total count", GET_MTX_FRM);
+    snprintf_res(cmd_data, "  %-16s  :%08d\t%-16s  :%08d\n", "Tx ack count"
+                 , GET_MTX_ACK_TX,"Tx WSID0 success", GET_MTX_WSID0_SUCC);
+    snprintf_res(cmd_data, "  %-16s  :%08d\t%-16s  :%08d\n", "Tx WSID0 frame"
+                 , GET_MTX_WSID0_FRM,"Tx WSID0 retry", GET_MTX_WSID0_RETRY);
+    snprintf_res(cmd_data, "  %-16s  :%08d\t%-16s  :%08d\n", "Tx WSID0 Total "
+                 , GET_MTX_WSID0_TOTAL, "CTS_TX", GET_MTX_CTS_TX);
+}
+static void ssv6006c_cmd_mib(struct ssv_softc *sc, int argc, char *argv[])
+{
+    struct ssv_cmd_data *cmd_data = &sc->cmd_data;
+    int i, primary = 0, secondary = 0;
+    if ((argc == 2) && (!strcmp(argv[1], "reset"))) {
+        ssv6006c_reset_mib(sc->sh);
+        snprintf_res(cmd_data, " => MIB reseted\n");
+    } else if ((argc == 2) && (!strcmp(argv[1], "list"))) {
+        ssv6006c_list_mib(sc->sh);
+    } else if ((argc == 2) && (strcmp(argv[1], "rx") == 0)) {
+        ssv6006c_dump_mib_rx(sc->sh);
+    } else if ((argc == 2) && (strcmp(argv[1], "tx") == 0)) {
+        ssv6006c_dump_mib_tx(sc->sh);
+    } else if ((argc == 2) && (strcmp(argv[1], "edca") == 0)) {
+        for (i = 0; i < 5; i++) {
+            primary = GET_PRIMARY_EDCA(sc);
+            secondary = GET_SECONDARY_EDCA(sc);
+            snprintf_res(cmd_data, "Primary EDCCA   :channel use percentage %d\n", primary);
+            snprintf_res(cmd_data, "Secondary EDCCA :channel use percentage %d\n\n\n", secondary);
+            msleep(100);
+        }
+    } else {
+        snprintf_res(cmd_data, "mib [reset|list|rx|tx|edca]\n\n");
+    }
+}
+static void ssv6006c_cmd_power_saving(struct ssv_softc *sc, int argc, char *argv[])
+{
+    struct ssv_cmd_data *cmd_data = &sc->cmd_data;
+    char *endp;
+    if ((argc == 2) && (argv[1])) {
+        sc->ps_aid = simple_strtoul(argv[1], &endp, 10);
+    } else {
+        snprintf_res(cmd_data, "ps [aid_value]\n\n");
+    }
+#ifdef PM
+    ssv6xxx_trigger_pmu(sc);
+#endif
+}
+static void ssv6006c_cmd_mtx_lpbk_mac80211_hdr(struct ssv_hw *sh, struct sk_buff *skb, u8 seq)
+{
+    struct ieee80211_hdr_3addr *hdr = NULL;
+    int i, tx_desc_size = 0, hdrlen = 24;
+    u8 macaddr[ETH_ALEN];
+    u8 *payload;
+    tx_desc_size = SSV_GET_TX_DESC_SIZE(sh);
+    memcpy(macaddr, sh->cfg.maddr[0], ETH_ALEN);
+    hdr = (struct ieee80211_hdr_3addr *)(skb->data + tx_desc_size);
+    memset(hdr, 0, sizeof(struct ieee80211_hdr_3addr));
+    hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_DATA |
+                                     IEEE80211_STYPE_QOS_DATA |
+                                     IEEE80211_FCTL_TODS);
+    memcpy(hdr->addr1, macaddr, ETH_ALEN);
+    memcpy(hdr->addr2, macaddr, ETH_ALEN);
+    memcpy(hdr->addr3, macaddr, ETH_ALEN);
+    hdr->seq_ctrl = seq;
+    payload = (u8 *)hdr + hdrlen;
+    for (i = (tx_desc_size + hdrlen); i < skb->len; i++) {
+        *payload = (u8)seq;
+        payload++;
+    }
+}
+static void ssv6006c_cmd_loopback_start(struct ssv_hw *sh)
+{
+    struct ssv_softc *sc = sh->sc;
+    struct ssv_cmd_data *cmd_data = &sh->sc->cmd_data;
+    int tx_desc_size = SSV_GET_TX_DESC_SIZE(sh);
+    struct sk_buff *skb;
+    int lpbk_pkt_cnt, lpbk_sec_loop_cnt, lpbk_rate_loop_cnt;
+    int i, j, k, seq = 0, rate_idx_start = 0, rate_idx_end = 0;
+    unsigned int len, sec;
+    unsigned char rate = 0;
+    unsigned char rate_tbl[] = {
+        0x00,0x01,0x02,0x03,
+        0x11,0x12,0x13,
+        0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,
+        0xc0,0xc1,0xc2,0xc3,0xc4,0xc5,0xc6,0xc7,
+        0xd0,0xd1,0xd2,0xd3,0xd4,0xd5,0xd6,0xd7,
+        0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,
+        0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,
+    };
+#define SIZE_RATE_TBL (sizeof(rate_tbl) / sizeof((rate_tbl)[0]))
+    lpbk_pkt_cnt = (sh->cfg.lpbk_pkt_cnt == 0) ? 10 : sh->cfg.lpbk_pkt_cnt;
+    lpbk_sec_loop_cnt = (sh->cfg.lpbk_sec == SSV6006_CMD_LPBK_SEC_AUTO) ? 5 : 1;
+    if (sh->cfg.lpbk_mode) {
+        lpbk_rate_loop_cnt = 1;
+        rate_idx_end = 1;
+        rate_idx_start = 0;
+        rate = ((sh->cfg.rc_rate_idx_set & SSV6006RC_RATE_MSK) << SSV6006RC_RATE_SFT) |
+               (sh->cfg.rc_long_short << SSV6006RC_LONG_SHORT_SFT) |
+               (sh->cfg.rc_ht40 << SSV6006RC_20_40_SFT) |
+               (sh->cfg.rc_phy_mode << SSV6006RC_PHY_MODE_SFT);
+    } else {
+        if (sh->cfg.lpbk_type == SSV6006_CMD_LPBK_TYPE_2GRF) {
+            lpbk_rate_loop_cnt = SIZE_RATE_TBL - 16;
+            rate_idx_end = SIZE_RATE_TBL - 16;
+            rate_idx_start = 0;
+        } else if (sh->cfg.lpbk_type == SSV6006_CMD_LPBK_TYPE_5GRF) {
+            lpbk_rate_loop_cnt = SIZE_RATE_TBL - 16 - 7;
+            rate_idx_end = SIZE_RATE_TBL - 16;
+            rate_idx_start = 7;
+        } else {
+            lpbk_rate_loop_cnt = SIZE_RATE_TBL;
+            rate_idx_end = SIZE_RATE_TBL;
+            rate_idx_start = 0;
+        }
+    }
+    sc->lpbk_tx_pkt_cnt = lpbk_pkt_cnt * lpbk_sec_loop_cnt * lpbk_rate_loop_cnt;
+    sc->lpbk_rx_pkt_cnt = 0;
+    sc->lpbk_err_cnt = 0;
+    for (i = 0; i < lpbk_sec_loop_cnt; i++) {
+        for (j = rate_idx_start; j < rate_idx_end; j++) {
+            for (k = 0; k < lpbk_pkt_cnt; k++) {
+                sec = (sh->cfg.lpbk_sec == SSV6006_CMD_LPBK_SEC_AUTO) ? (i+1) : sh->cfg.lpbk_sec;
+                if (!sh->cfg.lpbk_mode)
+                    rate = rate_tbl[j % SIZE_RATE_TBL];
+                get_random_bytes(&len, sizeof(unsigned int));
+                len = sizeof(struct ieee80211_hdr_3addr) + (len % 2000);
+                skb = ssv_skb_alloc(sc, len + tx_desc_size);
+                if (!skb) {
+                    dev_dbg(sc->dev, "%s(): Fail to alloc lpbk buffer.\n", __FUNCTION__);
+                    goto out;
+                }
+                skb_put(skb, len + tx_desc_size);
+                SSV_FILL_LPBK_TX_DESC(sc, skb, sec, rate);
+                ssv6006c_cmd_mtx_lpbk_mac80211_hdr(sh, skb, (u8)(seq % 255));
+                HCI_SEND(sh, skb, 0);
+                seq++;
+            }
+        }
+    }
+    msleep(sc->lpbk_tx_pkt_cnt + 1000);
+out:
+    if ((sc->lpbk_tx_pkt_cnt == sc->lpbk_rx_pkt_cnt) && (sc->lpbk_err_cnt == 0)) {
+        snprintf_res(cmd_data, "\n mtx lpbk: pass, tx/rx pkt_cnt=%d/%d, err_cnt=%d\n",
+                     sc->lpbk_tx_pkt_cnt, sc->lpbk_rx_pkt_cnt, sc->lpbk_err_cnt);
+    } else {
+        snprintf_res(cmd_data, "\n mtx lpbk: fail, tx/rx pkt_cnt=%d/%d, err_cnt=%d\n",
+                     sc->lpbk_tx_pkt_cnt, sc->lpbk_rx_pkt_cnt, sc->lpbk_err_cnt);
+    }
+}
+static void ssv6006c_cmd_hwinfo_mac_peer_stat(struct ssv_hw *sh)
+{
+    struct ssv_cmd_data *cmd_data = &sh->sc->cmd_data;
+    u32 value, value1, peer_mode, mib;
+    SET_MTX_MIB_EN0(1);
+    SET_MTX_MIB_EN1(1);
+    SET_MTX_MIB_EN2(1);
+    SET_MTX_MIB_EN3(1);
+    SET_MTX_MIB_EN4(1);
+    SET_MTX_MIB_EN5(1);
+    SET_MTX_MIB_EN6(1);
+    SET_MTX_MIB_EN7(1);
+    MDELAY(500);
+    value1 = GET_BSSID_47_32;
+    value = GET_BSSID_31_0;
+    snprintf_res(cmd_data, "BSSID_0    : %02x:%02x:%02x:%02x:%02x:%02x\n",
+                 (((value >> 0) & 0xff)), ((value >> 8) & 0xff), ((value >> 16) & 0xff),
+                 ((value >> 24) & 0xff), ((value1 >> 0) & 0xff), ((value1 >> 8) & 0xff));
+    value1 = GET_STA_MAC_47_32;
+    value = GET_STA_MAC_31_0;
+    snprintf_res(cmd_data, "SELF_MAC_0 : %02x:%02x:%02x:%02x:%02x:%02x\n",
+                 (((value >> 0) & 0xff)), ((value >> 8) & 0xff), ((value >> 16) & 0xff),
+                 ((value >> 24) & 0xff), ((value1 >> 0) & 0xff), ((value1 >> 8) & 0xff));
+    value1 = GET_BSSID1_47_32;
+    value = GET_BSSID1_31_0;
+    snprintf_res(cmd_data, "BSSID_1    : %02x:%02x:%02x:%02x:%02x:%02x\n",
+                 (((value >> 0) & 0xff)), ((value >> 8) & 0xff), ((value >> 16) & 0xff),
+                 ((value >> 24) & 0xff), ((value1 >> 0) & 0xff), ((value1 >> 8) & 0xff));
+    value1 = GET_STA_MAC1_47_32;
+    value = GET_STA_MAC1_31_0;
+    snprintf_res(cmd_data, "SELF_MAC_1 : %02x:%02x:%02x:%02x:%02x:%02x\n\n",
+                 (((value >> 0) & 0xff)), ((value >> 8) & 0xff), ((value >> 16) & 0xff),
+                 ((value >> 24) & 0xff), ((value1 >> 0) & 0xff), ((value1 >> 8) & 0xff));
+    value1 = GET_PEER_MAC0_47_32;
+    value = GET_PEER_MAC0_31_0;
+    peer_mode = GET_PEER_OP_MODE0;
+    SMAC_REG_READ(sh, ADR_MTX_MIB_WSID0, &mib);
+    snprintf_res(cmd_data, "PEER_MAC_0 : %02x:%02x:%02x:%02x:%02x:%02x, mode 0x%x, succ %d, attempt %d, frame %d\n",
+                 (((value >> 0) & 0xff)), ((value >> 8) & 0xff), ((value >> 16) & 0xff),
+                 ((value >> 24) & 0xff), ((value1 >> 0) & 0xff), ((value1 >> 8) & 0xff), peer_mode,
+                 ((mib & MTX_MIB_CNT0_SUCC_MSK) >> MTX_MIB_CNT0_SUCC_SFT),
+                 ((mib & MTX_MIB_CNT0_ATTEMPT_MSK) >> MTX_MIB_CNT0_ATTEMPT_SFT),
+                 ((mib & MTX_MIB_CNT0_FRAME_MSK) >> MTX_MIB_CNT0_FRAME_SFT));
+    value1 = GET_PEER_MAC1_47_32;
+    value = GET_PEER_MAC1_31_0;
+    peer_mode = GET_PEER_OP_MODE1;
+    SMAC_REG_READ(sh, ADR_MTX_MIB_WSID1, &mib);
+    snprintf_res(cmd_data, "PEER_MAC_1 : %02x:%02x:%02x:%02x:%02x:%02x, mode 0x%x, succ %d, attempt %d, frame %d\n",
+                 (((value >> 0) & 0xff)), ((value >> 8) & 0xff), ((value >> 16) & 0xff),
+                 ((value >> 24) & 0xff), ((value1 >> 0) & 0xff), ((value1 >> 8) & 0xff), peer_mode,
+                 ((mib & MTX_MIB_CNT1_SUCC_MSK) >> MTX_MIB_CNT1_SUCC_SFT),
+                 ((mib & MTX_MIB_CNT1_ATTEMPT_MSK) >> MTX_MIB_CNT1_ATTEMPT_SFT),
+                 ((mib & MTX_MIB_CNT1_FRAME_MSK) >> MTX_MIB_CNT1_FRAME_SFT));
+    value1 = GET_PEER_MAC2_47_32;
+    value = GET_PEER_MAC2_31_0;
+    peer_mode = GET_PEER_OP_MODE2;
+    SMAC_REG_READ(sh, ADR_MTX_MIB_WSID2, &mib);
+    snprintf_res(cmd_data, "PEER_MAC_2 : %02x:%02x:%02x:%02x:%02x:%02x, mode 0x%x, succ %d, attempt %d, frame %d\n",
+                 (((value >> 0) & 0xff)), ((value >> 8) & 0xff), ((value >> 16) & 0xff),
+                 ((value >> 24) & 0xff), ((value1 >> 0) & 0xff), ((value1 >> 8) & 0xff), peer_mode,
+                 ((mib & MTX_MIB_CNT2_SUCC_MSK) >> MTX_MIB_CNT2_SUCC_SFT),
+                 ((mib & MTX_MIB_CNT2_ATTEMPT_MSK) >> MTX_MIB_CNT2_ATTEMPT_SFT),
+                 ((mib & MTX_MIB_CNT2_FRAME_MSK) >> MTX_MIB_CNT2_FRAME_SFT));
+    value1 = GET_PEER_MAC3_47_32;
+    value = GET_PEER_MAC3_31_0;
+    peer_mode = GET_PEER_OP_MODE3;
+    SMAC_REG_READ(sh, ADR_MTX_MIB_WSID3, &mib);
+    snprintf_res(cmd_data, "PEER_MAC_3 : %02x:%02x:%02x:%02x:%02x:%02x, mode 0x%x, succ %d, attempt %d, frame %d\n",
+                 (((value >> 0) & 0xff)), ((value >> 8) & 0xff), ((value >> 16) & 0xff),
+                 ((value >> 24) & 0xff), ((value1 >> 0) & 0xff), ((value1 >> 8) & 0xff), peer_mode,
+                 ((mib & MTX_MIB_CNT3_SUCC_MSK) >> MTX_MIB_CNT3_SUCC_SFT),
+                 ((mib & MTX_MIB_CNT3_ATTEMPT_MSK) >> MTX_MIB_CNT3_ATTEMPT_SFT),
+                 ((mib & MTX_MIB_CNT3_FRAME_MSK) >> MTX_MIB_CNT3_FRAME_SFT));
+    value1 = GET_PEER_MAC4_47_32;
+    value = GET_PEER_MAC4_31_0;
+    peer_mode = GET_PEER_OP_MODE4;
+    SMAC_REG_READ(sh, ADR_MTX_MIB_WSID4, &mib);
+    snprintf_res(cmd_data, "PEER_MAC_4 : %02x:%02x:%02x:%02x:%02x:%02x, mode 0x%x, succ %d, attempt %d, frame %d\n",
+                 (((value >> 0) & 0xff)), ((value >> 8) & 0xff), ((value >> 16) & 0xff),
+                 ((value >> 24) & 0xff), ((value1 >> 0) & 0xff), ((value1 >> 8) & 0xff), peer_mode,
+                 ((mib & MTX_MIB_CNT4_SUCC_MSK) >> MTX_MIB_CNT4_SUCC_SFT),
+                 ((mib & MTX_MIB_CNT4_ATTEMPT_MSK) >> MTX_MIB_CNT4_ATTEMPT_SFT),
+                 ((mib & MTX_MIB_CNT4_FRAME_MSK) >> MTX_MIB_CNT4_FRAME_SFT));
+    value1 = GET_PEER_MAC5_47_32;
+    value = GET_PEER_MAC5_31_0;
+    peer_mode = GET_PEER_OP_MODE5;
+    SMAC_REG_READ(sh, ADR_MTX_MIB_WSID5, &mib);
+    snprintf_res(cmd_data, "PEER_MAC_5 : %02x:%02x:%02x:%02x:%02x:%02x, mode 0x%x, succ %d, attempt %d, frame %d\n",
+                 (((value >> 0) & 0xff)), ((value >> 8) & 0xff), ((value >> 16) & 0xff),
+                 ((value >> 24) & 0xff), ((value1 >> 0) & 0xff), ((value1 >> 8) & 0xff), peer_mode,
+                 ((mib & MTX_MIB_CNT5_SUCC_MSK) >> MTX_MIB_CNT5_SUCC_SFT),
+                 ((mib & MTX_MIB_CNT5_ATTEMPT_MSK) >> MTX_MIB_CNT5_ATTEMPT_SFT),
+                 ((mib & MTX_MIB_CNT5_FRAME_MSK) >> MTX_MIB_CNT5_FRAME_SFT));
+    value1 = GET_PEER_MAC6_47_32;
+    value = GET_PEER_MAC6_31_0;
+    peer_mode = GET_PEER_OP_MODE6;
+    SMAC_REG_READ(sh, ADR_MTX_MIB_WSID6, &mib);
+    snprintf_res(cmd_data, "PEER_MAC_6 : %02x:%02x:%02x:%02x:%02x:%02x, mode 0x%x, succ %d, attempt %d, frame %d\n",
+                 (((value >> 0) & 0xff)), ((value >> 8) & 0xff), ((value >> 16) & 0xff),
+                 ((value >> 24) & 0xff), ((value1 >> 0) & 0xff), ((value1 >> 8) & 0xff), peer_mode,
+                 ((mib & MTX_MIB_CNT6_SUCC_MSK) >> MTX_MIB_CNT6_SUCC_SFT),
+                 ((mib & MTX_MIB_CNT6_ATTEMPT_MSK) >> MTX_MIB_CNT6_ATTEMPT_SFT),
+                 ((mib & MTX_MIB_CNT6_FRAME_MSK) >> MTX_MIB_CNT6_FRAME_SFT));
+    value1 = GET_PEER_MAC7_47_32;
+    value = GET_PEER_MAC7_31_0;
+    peer_mode = GET_PEER_OP_MODE7;
+    SMAC_REG_READ(sh, ADR_MTX_MIB_WSID7, &mib);
+    snprintf_res(cmd_data, "PEER_MAC_7 : %02x:%02x:%02x:%02x:%02x:%02x, mode 0x%x, succ %d, attempt %d, frame %d\n",
+                 (((value >> 0) & 0xff)), ((value >> 8) & 0xff), ((value >> 16) & 0xff),
+                 ((value >> 24) & 0xff), ((value1 >> 0) & 0xff), ((value1 >> 8) & 0xff), peer_mode,
+                 ((mib & MTX_MIB_CNT7_SUCC_MSK) >> MTX_MIB_CNT7_SUCC_SFT),
+                 ((mib & MTX_MIB_CNT7_ATTEMPT_MSK) >> MTX_MIB_CNT7_ATTEMPT_SFT),
+                 ((mib & MTX_MIB_CNT7_FRAME_MSK) >> MTX_MIB_CNT7_FRAME_SFT));
+}
+static void ssv6006c_cmd_hwinfo_mac_stat(struct ssv_hw *sh)
+{
+    struct ssv_cmd_data *cmd_data = &sh->sc->cmd_data;
+    snprintf_res(cmd_data, "RG_MAC_LPBK                     : 0x%x\n", GET_RG_MAC_LPBK);
+    snprintf_res(cmd_data, "RG_MAC_M2M          (obsolete)  : 0x%x\n", GET_RG_MAC_M2M);
+    snprintf_res(cmd_data, "RG_PHY_LPBK                     : 0x%x\n", GET_RG_PHY_LPBK);
+    snprintf_res(cmd_data, "RG_LPBK_RX_EN                   : 0x%x\n", GET_RG_LPBK_RX_EN);
+    snprintf_res(cmd_data, "EXT_MAC_MODE        (obsolete)  : 0x%x\n", GET_EXT_MAC_MODE);
+    snprintf_res(cmd_data, "EXT_PHY_MODE        (obsolete)  : 0x%x\n", GET_EXT_PHY_MODE);
+    snprintf_res(cmd_data, "SNIFFER_MODE        rx_sniffer  : 0x%x\n", GET_SNIFFER_MODE);
+    snprintf_res(cmd_data, "AMPDU_SNIFFER       rx_sniffer  : 0x%x\n", GET_AMPDU_SNIFFER);
+    snprintf_res(cmd_data, "MTX_MTX2PHY_SLOW    tx_for_lpbk : 0x%x\n", GET_MTX_MTX2PHY_SLOW);
+    snprintf_res(cmd_data, "MTX_M2M_SLOW_PRD    tx_for_lpbk : 0x%d\n", GET_MTX_M2M_SLOW_PRD);
+}
+static void ssv6006c_cmd_hwinfo_mac_scrt_stat(struct ssv_hw *sh)
+{
+    struct ssv_cmd_data *cmd_data = &sh->sc->cmd_data;
+    snprintf_res(cmd_data, "TX_PKT_RSVD        HCI          : %d\n", GET_TX_PKT_RSVD);
+    snprintf_res(cmd_data, "REASON_TRAP0       SECURITY/HCI : 0x%08x\n", GET_REASON_TRAP0);
+    snprintf_res(cmd_data, "REASON_TRAP1       SECURITY/HCI : 0x%08x\n", GET_REASON_TRAP1);
+    snprintf_res(cmd_data, "LUT_SEL_V2         SECURITY     : 0x%x\n", GET_CCMP_H_SEL);
+    snprintf_res(cmd_data, "CCMP_H_SEL         SECURITY     : 0x%x\n", GET_LUT_SEL_V2);
+    snprintf_res(cmd_data, "PAIR_SCRT          SECURITY     : 0x%x\n", GET_PAIR_SCRT);
+    snprintf_res(cmd_data, "GRP_SCRT           SECURITY     : 0x%x\n", GET_GRP_SCRT);
+    snprintf_res(cmd_data, "SCRT_PKT_ID        SECURITY     : 0x%d\n", GET_SCRT_PKT_ID);
+    snprintf_res(cmd_data, "SCRT_RPLY_IGNORE   SECURITY     : 0x%d\n", GET_SCRT_RPLY_IGNORE);
+}
+static void ssv6006c_cmd_hwinfo_mac_beacon(struct ssv_hw *sh)
+{
+    struct ssv_cmd_data *cmd_data = &sh->sc->cmd_data;
+    u32 value, value1;
+    snprintf_res(cmd_data, "HWBCN_PKTID\n");
+    snprintf_res(cmd_data, "\tMTX_BCN_CFG_VLD      : %d\n", GET_MTX_BCN_CFG_VLD);
+    snprintf_res(cmd_data, "\tMTX_AUTO_BCN_ONGOING : 0x%x\n", GET_MTX_AUTO_BCN_ONGOING);
+    snprintf_res(cmd_data, "\tMTX_BCN_PKT_ID0      : %d\n", GET_MTX_BCN_PKT_ID0);
+    snprintf_res(cmd_data, "\tMTX_BCN_PKT_ID1      : %d\n", GET_MTX_BCN_PKT_ID1);
+    snprintf_res(cmd_data, "\tMTX_BCN_PKTID_CH_LOCK (deprecated): 0x%x\n\n", GET_MTX_BCN_PKTID_CH_LOCK);
+    value = GET_MTX_BCN_TIMER;
+    value1 = GET_MTX_BCN_PERIOD;
+    snprintf_res(cmd_data, "HWBCN_TIMER\n");
+    snprintf_res(cmd_data, "\tMTX_BCN_TIMER_EN                         : 0x%x\n", GET_MTX_BCN_TIMER_EN);
+    snprintf_res(cmd_data, "\tMTX_BCN_TIMER(active interval count down): 0x%x=%d\n", value, value);
+    snprintf_res(cmd_data, "\tMTX_BCN_PERIOD(fixed period in TBTT)     : 0x%x=%d\n\n", value1, value1);
+    snprintf_res(cmd_data, "HWBCN_TSF\n");
+    snprintf_res(cmd_data, "\tMTX_TSF_TIMER_EN         : 0x%x\n", GET_MTX_TSF_TIMER_EN);
+    snprintf_res(cmd_data, "\tMTX_BCN_TSF              : 0x%x/0x%x(U/L)\n", GET_MTX_BCN_TSF_U, GET_MTX_BCN_TSF_L);
+    snprintf_res(cmd_data, "\tMTX_TIME_STAMP_AUTO_FILL : 0x%x\n\n", GET_MTX_TIME_STAMP_AUTO_FILL);
+    snprintf_res(cmd_data, "HWBCN_DTIM\n");
+    snprintf_res(cmd_data, "\tMTX_DTIM_CNT_AUTO_FILL  : 0x%x\n", GET_MTX_DTIM_CNT_AUTO_FILL);
+    snprintf_res(cmd_data, "\tMTX_DTIM_NUM            : %d\n", GET_MTX_DTIM_NUM);
+    snprintf_res(cmd_data, "\tMTX_DTIM_OFST0          : %d\n", GET_MTX_DTIM_OFST0);
+    snprintf_res(cmd_data, "\tMTX_DTIM_OFST1          : %d\n\n", GET_MTX_DTIM_OFST1);
+    snprintf_res(cmd_data, "HWBCN_MISC_OPTION\n");
+    snprintf_res(cmd_data, "\tMTX_BCN_AUTO_SEQ_NO        : 0x%x\n", GET_MTX_BCN_AUTO_SEQ_NO);
+    snprintf_res(cmd_data, "\tTXQ5_DTIM_BEACON_BURST_MNG : 0x%x\n\n", GET_TXQ5_DTIM_BEACON_BURST_MNG);
+    snprintf_res(cmd_data, "HWBCN_INT_DEPRECATED\n");
+    snprintf_res(cmd_data, "\tMTX_INT_DTIM_NUM (deprecated) : %d\n", GET_MTX_INT_DTIM_NUM);
+    snprintf_res(cmd_data, "\tMTX_INT_DTIM     (deprecated) : 0x%x\n", GET_MTX_INT_DTIM);
+    snprintf_res(cmd_data, "\tMTX_INT_BCN      (deprecated) : 0x%x\n", GET_MTX_INT_BCN);
+    snprintf_res(cmd_data, "\tMTX_EN_INT_BCN   (deprecated) : 0x%x\n", GET_MTX_EN_INT_BCN);
+    snprintf_res(cmd_data, "\tMTX_EN_INT_DTIM  (deprecated) : 0x%x\n\n", GET_MTX_EN_INT_DTIM);
+}
+static void ssv6006c_cmd_hwinfo_mac_txq(struct ssv_hw *sh)
+{
+    struct ssv_cmd_data *cmd_data = &sh->sc->cmd_data;
+    snprintf_res(cmd_data, "BLOCK_TXQ : 0x%x\n", GET_BLOCK_TXQ);
+    snprintf_res(cmd_data, "TXQ_NULLDATAFRAME_GEN_EN: txq0=%x, txq1=%x, txq2=%x, txq3=%x, txq4=%x, txq5=%x\n",
+                 GET_TXQ0_Q_NULLDATAFRAME_GEN_EN, GET_TXQ1_Q_NULLDATAFRAME_GEN_EN,
+                 GET_TXQ2_Q_NULLDATAFRAME_GEN_EN, GET_TXQ3_Q_NULLDATAFRAME_GEN_EN,
+                 GET_TXQ4_Q_NULLDATAFRAME_GEN_EN, GET_TXQ5_Q_NULLDATAFRAME_GEN_EN);
+    snprintf_res(cmd_data, "TXQ_MTX_Q_RND_MODE      : txq0=%d, txq1=%d, txq2=%d, txq3=%d, txq4=%d, txq5=%d\n",
+                 GET_TXQ0_MTX_Q_RND_MODE, GET_TXQ1_MTX_Q_RND_MODE,
+                 GET_TXQ2_MTX_Q_RND_MODE, GET_TXQ3_MTX_Q_RND_MODE,
+                 GET_TXQ4_MTX_Q_RND_MODE, GET_TXQ5_MTX_Q_RND_MODE);
+    snprintf_res(cmd_data, "TXQ_MTX_Q_MB_NO_RLS     : txq0=%x, txq1=%x, txq2=%x, txq3=%x, txq4=%x, txq5=%x\n",
+                 GET_TXQ0_MTX_Q_MB_NO_RLS, GET_TXQ1_MTX_Q_MB_NO_RLS,
+                 GET_TXQ2_MTX_Q_MB_NO_RLS, GET_TXQ3_MTX_Q_MB_NO_RLS,
+                 GET_TXQ4_MTX_Q_MB_NO_RLS, GET_TXQ5_MTX_Q_MB_NO_RLS);
+    snprintf_res(cmd_data, "TXQ_MTX_Q_BKF_CNT_FIX   : txq0=0x%x, txq1=0x%x, txq2=0x%x, txq3=0x%x, txq4=0x%x, txq5=0x%x\n",
+                 GET_TXQ0_MTX_Q_BKF_CNT_FIX, GET_TXQ1_MTX_Q_BKF_CNT_FIX,
+                 GET_TXQ2_MTX_Q_BKF_CNT_FIX, GET_TXQ3_MTX_Q_BKF_CNT_FIX,
+                 GET_TXQ4_MTX_Q_BKF_CNT_FIX, GET_TXQ5_MTX_Q_BKF_CNT_FIX);
+}
+static void ssv6006c_cmd_hwinfo_mac_edca(struct ssv_hw *sh)
+{
+    struct ssv_cmd_data *cmd_data = &sh->sc->cmd_data;
+    snprintf_res(cmd_data, "EDCA_Q0: TXOP[%d], ECWMIN[%d], ECWMAX[%d], AIFSN[%d]\n",
+                 GET_TXQ0_MTX_Q_TXOP_LIMIT, GET_TXQ0_MTX_Q_ECWMIN, GET_TXQ0_MTX_Q_ECWMAX, GET_TXQ0_MTX_Q_AIFSN);
+    snprintf_res(cmd_data, "EDCA_Q1: TXOP[%d], ECWMIN[%d], ECWMAX[%d], AIFSN[%d]\n",
+                 GET_TXQ1_MTX_Q_TXOP_LIMIT, GET_TXQ1_MTX_Q_ECWMIN, GET_TXQ1_MTX_Q_ECWMAX, GET_TXQ1_MTX_Q_AIFSN);
+    snprintf_res(cmd_data, "EDCA_Q2: TXOP[%d], ECWMIN[%d], ECWMAX[%d], AIFSN[%d]\n",
+                 GET_TXQ2_MTX_Q_TXOP_LIMIT, GET_TXQ2_MTX_Q_ECWMIN, GET_TXQ2_MTX_Q_ECWMAX, GET_TXQ2_MTX_Q_AIFSN);
+    snprintf_res(cmd_data, "EDCA_Q3: TXOP[%d], ECWMIN[%d], ECWMAX[%d], AIFSN[%d]\n",
+                 GET_TXQ3_MTX_Q_TXOP_LIMIT, GET_TXQ3_MTX_Q_ECWMIN, GET_TXQ3_MTX_Q_ECWMAX, GET_TXQ3_MTX_Q_AIFSN);
+    snprintf_res(cmd_data, "EDCA_Q4: TXOP[%d], ECWMIN[%d], ECWMAX[%d], AIFSN[%d]\n",
+                 GET_TXQ4_MTX_Q_TXOP_LIMIT, GET_TXQ4_MTX_Q_ECWMIN, GET_TXQ4_MTX_Q_ECWMAX, GET_TXQ4_MTX_Q_AIFSN);
+    snprintf_res(cmd_data, "EDCA_Q5: TXOP[%d], ECWMIN[%d], ECWMAX[%d], AIFSN[%d]\n",
+                 GET_TXQ5_MTX_Q_TXOP_LIMIT, GET_TXQ5_MTX_Q_ECWMIN, GET_TXQ5_MTX_Q_ECWMAX, GET_TXQ5_MTX_Q_AIFSN);
+}
+static void ssv6006c_cmd_hwinfo_mac_txstat(struct ssv_hw *sh)
+{
+    struct ssv_cmd_data *cmd_data = &sh->sc->cmd_data;
+    u32 regval;
+    snprintf_res(cmd_data, "MTX_STAT\n");
+    snprintf_res(cmd_data, "\tSTAT_ENABLE     : 0x%x\n", GET_STAT_ENABLE);
+    snprintf_res(cmd_data, "\tSTAT_FSM        : %d\n", GET_STAT_FSM);
+    snprintf_res(cmd_data, "\tSTAT_PKT_ID     : %d\n", GET_STAT_PKT_ID);
+    SMAC_REG_READ(sh, ADR_STAT_CONF0, &regval);
+    snprintf_res(cmd_data, "\tWD STAT_CONF0   : 0x%x\n", regval);
+    SMAC_REG_READ(sh, ADR_STAT_CONF1, &regval);
+    snprintf_res(cmd_data, "\tWD STAT_CONF1   : 0x%x\n\n", regval);
+    snprintf_res(cmd_data, "MTX_SETTING\n");
+    snprintf_res(cmd_data, "\tSIFS         : %d\n", GET_SIFS);
+    snprintf_res(cmd_data, "\tSLOTTIME     : %d\n", GET_SLOTTIME);
+    snprintf_res(cmd_data, "\tMAC_CLK_80M  : 0x%x\n", GET_MAC_CLK_80M);
+    snprintf_res(cmd_data, "\tSIGEXT       : %d\n", GET_SIGEXT);
+    snprintf_res(cmd_data, "\tTOUT_B       : %d\n", GET_TOUT_B);
+    snprintf_res(cmd_data, "\tTOUT_AGN     : %d\n", GET_TOUT_AGN);
+    snprintf_res(cmd_data, "\tEIFS_IN_SLOT : %d\n\n", GET_EIFS_IN_SLOT);
+    snprintf_res(cmd_data, "FINETUNE\n");
+    snprintf_res(cmd_data, "\tTXSIFS_SUB_MIN                    : %d\n", GET_TXSIFS_SUB_MIN);
+    snprintf_res(cmd_data, "\tTXSIFS_SUB_MAX                    : %d\n", GET_TXSIFS_SUB_MAX);
+    snprintf_res(cmd_data, "\tNAVCS_PHYCS_FALL_OFFSET_STEP      : %d\n", GET_NAVCS_PHYCS_FALL_OFFSET_STEP);
+    snprintf_res(cmd_data, "\tTX_IP_FALL_OFFSET_STEP            : %d\n", GET_TX_IP_FALL_OFFSET_STEP);
+    snprintf_res(cmd_data, "\tPHYTXSTART_NCYCLE                 : %d\n", GET_PHYTXSTART_NCYCLE);
+    snprintf_res(cmd_data, "\tMTX_DBG_PHYRX_IFS_DELTATIME       : %d\n", GET_MTX_DBG_PHYRX_IFS_DELTATIME);
+    snprintf_res(cmd_data, "\tMTX_NAV                           : %d\n\n", GET_MTX_NAV);
+    snprintf_res(cmd_data, "MTX_STATUS\n");
+    SMAC_REG_READ(sh, ADR_MTX_STATUS, &regval);
+    snprintf_res(cmd_data, "\tMTX_TX_EN                   : 0x%x\n",
+                 ((regval & RO_MTX_TX_EN_MSK) >> RO_MTX_TX_EN_SFT));
+    snprintf_res(cmd_data, "\tMAC_TX_FIFO_WINC            : 0x%x\n",
+                 ((regval & RO_MAC_TX_FIFO_WINC_MSK) >> RO_MAC_TX_FIFO_WINC_SFT));
+    snprintf_res(cmd_data, "\tMAC_TX_FIFO_WFULL_MX        : 0x%x\n",
+                 ((regval & RO_MAC_TX_FIFO_WFULL_MX_MSK)>>RO_MAC_TX_FIFO_WFULL_MX_SFT));
+    snprintf_res(cmd_data, "\tMAC_TX_FIFO_WEMPTY          : 0x%x\n",
+                 ((regval & RO_MAC_TX_FIFO_WEMPTY_MSK)>>RO_MAC_TX_FIFO_WEMPTY_SFT));
+    snprintf_res(cmd_data, "\tTOMAC_TX_IP                 : 0x%x\n",
+                 ((regval & TOMAC_TX_IP_MSK)>>TOMAC_TX_IP_SFT));
+    snprintf_res(cmd_data, "\tTOMAC_ED_CCA_PRIMARY_MX     : 0x%x\n",
+                 ((regval & TOMAC_ED_CCA_PRIMARY_MX_MSK) >> TOMAC_ED_CCA_PRIMARY_MX_SFT));
+    snprintf_res(cmd_data, "\tTOMAC_ED_CCA_SECONDARY_MX   : 0x%x\n",
+                 ((regval & TOMAC_ED_CCA_SECONDARY_MX_MSK)>>TOMAC_ED_CCA_SECONDARY_MX_SFT));
+    snprintf_res(cmd_data, "\tTOMAC_CS_CCA_MX             : 0x%x\n",
+                 ((regval & TOMAC_CS_CCA_MX_MSK)>>TOMAC_CS_CCA_MX_SFT));
+    snprintf_res(cmd_data, "\tBT_BUSY                     : 0x%x\n\n",
+                 ((regval & BT_BUSY_MSK)>>BT_BUSY_SFT));
+    snprintf_res(cmd_data, "MTX_PEER_PS\n");
+    snprintf_res(cmd_data, "\tMAC_TX_PEER_PS_LOCK_EN            : 0x%x\n", GET_MAC_TX_PEER_PS_LOCK_EN);
+    snprintf_res(cmd_data, "\tMAC_TX_PEER_PS_LOCK_AUTOLOCK_EN   : 0x%x\n", GET_MAC_TX_PEER_PS_LOCK_AUTOLOCK_EN);
+    snprintf_res(cmd_data, "\tMAC_TX_PS_LOCK_STATUS             : 0x%x\n\n", GET_MAC_TX_PS_LOCK_STATUS);
+}
+static void ssv6006c_cmd_hwinfo_mac_tx2phy(struct ssv_hw *sh)
+{
+    struct ssv_cmd_data *cmd_data = &sh->sc->cmd_data;
+    snprintf_res(cmd_data, "BLOCKTX_IGNORE_TOMAC_TX_IP            : 0x%x\n", GET_MTX_BLOCKTX_IGNORE_TOMAC_TX_IP);
+    snprintf_res(cmd_data, "BLOCKTX_IGNORE_TOMAC_RX_EN            : 0x%x\n", GET_MTX_BLOCKTX_IGNORE_TOMAC_RX_EN);
+    snprintf_res(cmd_data, "BLOCKTX_IGNORE_TOMAC_CCA_CS           : 0x%x\n", GET_MTX_BLOCKTX_IGNORE_TOMAC_CCA_CS);
+    snprintf_res(cmd_data, "BLOCKTX_IGNORE_TOMAC_CCA_ED_SECONDARY : 0x%x\n", GET_MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_SECONDARY);
+    snprintf_res(cmd_data, "BLOCKTX_IGNORE_TOMAC_CCA_ED_PRIMARY   : 0x%x\n", GET_MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_PRIMARY);
+    snprintf_res(cmd_data, "IGNORE_PHYRX_IFS_DELTATIME            : 0x%x\n", GET_MTX_IGNORE_PHYRX_IFS_DELTATIME);
+}
+static void ssv6006c_cmd_hwinfo_mac_tx2ptc(struct ssv_hw *sh)
+{
+    struct ssv_cmd_data *cmd_data = &sh->sc->cmd_data;
+    snprintf_res(cmd_data, "MTX_RATERPT_HWID                : %d\n", GET_MTX_RATERPT_HWID);
+    snprintf_res(cmd_data, "CTYPE_RATE_RPT                  : %d\n", GET_CTYPE_RATE_RPT);
+    snprintf_res(cmd_data, "NO_PKT_BUF_REDUCTION            : 0x%x\n", GET_NO_PKT_BUF_REDUCTION);
+    snprintf_res(cmd_data, "NO_REDUCE_TXALLFAIL_PKT         : 0x%x\n", GET_NO_REDUCE_TXALLFAIL_PKT);
+    snprintf_res(cmd_data, "NO_REDUCE_PKT_PEERPS_MPDU       : 0x%x\n", GET_NO_REDUCE_PKT_PEERPS_MPDU);
+    snprintf_res(cmd_data, "NO_REDUCE_PKT_PEERPS_AMPDUV1P2  : 0x%x\n", GET_NO_REDUCE_PKT_PEERPS_AMPDUV1P2);
+    snprintf_res(cmd_data, "NO_REDUCE_PKT_PEERPS_AMPDUV1P3  : 0x%x\n", GET_NO_REDUCE_PKT_PEERPS_AMPDUV1P3);
+}
+static void ssv6006c_cmd_hwinfo_mac_fixrate(struct ssv_hw *sh)
+{
+    struct ssv_cmd_data *cmd_data = &sh->sc->cmd_data;
+    snprintf_res(cmd_data, "MTX_DBGOPT_FORCE_TXMAJOR_RATE       : 0x%x\n", GET_MTX_DBGOPT_FORCE_TXMAJOR_RATE);
+    snprintf_res(cmd_data, "MTX_DBGOPT_FORCE_TXCTRL_RATE        : 0x%x\n", GET_MTX_DBGOPT_FORCE_TXCTRL_RATE);
+    snprintf_res(cmd_data, "MTX_DBGOPT_FORCE_DO_RTS_CTS_MODE    : 0x%x\n", GET_MTX_DBGOPT_FORCE_DO_RTS_CTS_MODE);
+    snprintf_res(cmd_data, "MTX_DBGOPT_FORCE_TXMAJOR_RATE_EN    : 0x%x\n", GET_MTX_DBGOPT_FORCE_TXMAJOR_RATE_EN);
+    snprintf_res(cmd_data, "MTX_DBGOPT_FORCE_TXCTRL_RATE_EN     : 0x%x\n", GET_MTX_DBGOPT_FORCE_TXCTRL_RATE_EN);
+    snprintf_res(cmd_data, "MTX_DBGOPT_FORCE_DO_RTS_CTS_MODE_EN : 0x%x\n", GET_MTX_DBGOPT_FORCE_DO_RTS_CTS_MODE_EN);
+}
+static void ssv6006c_cmd_hwinfo_lookup_fsm_mtxdma(u32 value, char *mtxstr)
+{
+    int len = 0;
+    len = sprintf(mtxstr, "ro_fsm_mtxdma[%d]        : ", value);
+    switch (value) {
+    case 0:
+        len = sprintf(mtxstr+len, "%s", "IDLE");
+        break;
+    case 1:
+        len = sprintf(mtxstr+len, "%s", "RD_DES");
+        break;
+    case 2:
+        len = sprintf(mtxstr+len, "%s", "RD_HDR");
+        break;
+    case 3:
+        len = sprintf(mtxstr+len, "%s", "GEN_PHYTXDESC");
+        break;
+    case 4:
+        len = sprintf(mtxstr+len, "%s", "TX_FRM");
+        break;
+    default:
+        len = sprintf(mtxstr+len, "%s", "INVALID");
+        break;
+    }
+}
+static void ssv6006c_cmd_hwinfo_lookup_mac_tx_wait_response_phase(u32 value, char *mtxstr)
+{
+    int len = 0;
+    len = sprintf(mtxstr, "ro_wait_response_phase[%d]   : ", value);
+    switch (value) {
+    case 0:
+        len = sprintf(mtxstr+len, "%s", "IDLE");
+        break;
+    case 1:
+        len = sprintf(mtxstr+len, "%s", "WAIT_RXCCA");
+        break;
+    case 2:
+        len = sprintf(mtxstr+len, "%s", "WAIT_YETTOUT");
+        break;
+    case 3:
+        len = sprintf(mtxstr+len, "%s", "WAIT_RXPROC");
+        break;
+    default:
+        len = sprintf(mtxstr+len, "%s", "INVALID");
+        break;
+    }
+}
+static void ssv6006c_cmd_hwinfo_lookup_mac_tx_mtxptc(u32 value, char *mtxstr)
+{
+    int len = 0;
+    len = sprintf(mtxstr, "ro_fsm_mtxptc[%d]        : ", value);
+    switch (value) {
+    case 0:
+        len = sprintf(mtxstr+len, "%s", "IDLE");
+        break;
+    case 1:
+        len = sprintf(mtxstr+len, "%s", "WRDES_RATERPT");
+        break;
+    case 2:
+        len = sprintf(mtxstr+len, "%s", "WRDES_CTYPE");
+        break;
+    case 3:
+        len = sprintf(mtxstr+len, "%s", "SIGNALRESULT");
+        break;
+    case 4:
+        len = sprintf(mtxstr+len, "%s", "WAIT_REDUCE");
+        break;
+    case 5:
+        len = sprintf(mtxstr+len, "%s", "LOCKQ");
+        break;
+    case 6:
+        len = sprintf(mtxstr+len, "%s", "EVTX");
+        break;
+    default:
+        len = sprintf(mtxstr+len, "%s", "INVALID");
+        break;
+    }
+}
+static void ssv6006c_cmd_hwinfo_lookup_mac_tx_ptc_schedule(u32 value, char *mtxstr)
+{
+    int len = 0;
+    len = sprintf(mtxstr, "ro_ptc_schedule[%d]      : ", value);
+    switch (value) {
+    case 0:
+        len = sprintf(mtxstr+len, "%s", "IDLE");
+        break;
+    case 1:
+        len = sprintf(mtxstr+len, "%s", "WAIT_RSP_ACK");
+        break;
+    case 2:
+        len = sprintf(mtxstr+len, "%s", "WAIT_RSP_BA");
+        break;
+    case 3:
+        len = sprintf(mtxstr+len, "%s", "WAIT_RSP_CTS");
+        break;
+    case 9:
+        len = sprintf(mtxstr+len, "%s", "WAIT_SIFS_TX_ACK");
+        break;
+    case 10:
+        len = sprintf(mtxstr+len, "%s", "WAIT_SIFS_TX_BA");
+        break;
+    case 11:
+        len = sprintf(mtxstr+len, "%s", "WAIT_SIFS_TX_CTS");
+        break;
+    case 12:
+        len = sprintf(mtxstr+len, "%s", "WAIT_SIFS_TX_MAJOR");
+        break;
+    case 13:
+        len = sprintf(mtxstr+len, "%s", "WAIT_SIFS_TX_TXOP");
+        break;
+    case 14:
+        len = sprintf(mtxstr+len, "%s", "WAIT_FRAMESEQ_TX");
+        break;
+    case 15:
+        len = sprintf(mtxstr+len, "%s", "WAIT_FRAMESEQ_TXOP");
+        break;
+    default:
+        len = sprintf(mtxstr+len, "%s", "INVALID");
+        break;
+    }
+}
+static void ssv6006c_cmd_hwinfo_lookup_mtxdma_cmd(u32 value, char *mtxstr)
+{
+    int len = 0;
+    len = sprintf(mtxstr, "ro_mtxdma_cmd        : ack_0x%x, ba_0x%x, cts_0x%x, nulldata_0x%x, postctrlqtx_0x%x, qtx_0x%x",
+                  ((value & 0x20) >> 5), ((value & 0x10) >> 4), ((value & 0x8) >> 3),
+                  ((value & 0x4) >> 2), ((value & 0x2) >> 1), ((value & 0x1) >> 0));
+}
+static void ssv6006c_cmd_hwinfo_mac_txfsm(struct ssv_hw *sh)
+{
+    struct ssv_cmd_data *cmd_data = &sh->sc->cmd_data;
+    char mtxstr[256];
+    u32 regval;
+    memset(mtxstr, 0, sizeof(mtxstr));
+    regval = GET_RO_PTC_SCHEDULE;
+    ssv6006c_cmd_hwinfo_lookup_mac_tx_ptc_schedule(regval, mtxstr);
+    snprintf_res(cmd_data, "%s\n", mtxstr);
+    memset(mtxstr, 0, sizeof(mtxstr));
+    regval = GET_RO_FSM_MTXPTC;
+    ssv6006c_cmd_hwinfo_lookup_mac_tx_mtxptc(regval, mtxstr);
+    snprintf_res(cmd_data, "%s\n", mtxstr);
+    snprintf_res(cmd_data, "RO_ACT_MASK              : 0x%x\n", GET_RO_ACT_MASK);
+    snprintf_res(cmd_data, "RO_CAND_MASK             : 0x%x\n", GET_RO_CAND_MASK);
+    memset(mtxstr, 0, sizeof(mtxstr));
+    regval = GET_RO_WAIT_RESPONSE_PHASE;
+    ssv6006c_cmd_hwinfo_lookup_mac_tx_wait_response_phase(regval, mtxstr);
+    snprintf_res(cmd_data, "%s\n", mtxstr);
+    snprintf_res(cmd_data, "RO_FSM_MTXHALT           : 0x%x\n", GET_RO_FSM_MTXHALT);
+    memset(mtxstr, 0, sizeof(mtxstr));
+    regval = GET_RO_FSM_MTXDMA;
+    ssv6006c_cmd_hwinfo_lookup_fsm_mtxdma(regval, mtxstr);
+    snprintf_res(cmd_data, "%s\n", mtxstr);
+    snprintf_res(cmd_data, "RO_FSM_MTXPHYTX          : 0x%x\n", GET_RO_FSM_MTXPHYTX);
+    memset(mtxstr, 0, sizeof(mtxstr));
+    regval = GET_RO_MTXDMA_CMD;
+    ssv6006c_cmd_hwinfo_lookup_mtxdma_cmd(regval, mtxstr);
+    snprintf_res(cmd_data, "%s\n", mtxstr);
+    snprintf_res(cmd_data, "RO_TXOP_INTERVAL         : %d\n", GET_RO_TXOP_INTERVAL);
+}
+static void ssv6006c_cmd_hwinfo_mac_txifs(struct ssv_hw *sh)
+{
+    struct ssv_cmd_data *cmd_data = &sh->sc->cmd_data;
+    u32 ifs_st0 = GET_RO_IFSST0;
+    u32 ifs_st1 = GET_RO_IFSST1;
+    u32 ifs_st2 = GET_RO_IFSST2;
+    u32 ifs_st3 = GET_RO_IFSST3;
+    snprintf_res(cmd_data, "r_nav_cnt                               : %d\n", ((ifs_st0 & 0x7fff0000) >> 16));
+    snprintf_res(cmd_data, "r_nav_cycle_count_us                    : %d\n", ((ifs_st0 & 0x00007f00) >> 8));
+    snprintf_res(cmd_data, "r_response_timeout_timer                : %d\n", ((ifs_st0 & 0x000000ff) >> 0));
+    snprintf_res(cmd_data, "r_ptc_cycle_count_us                    : %d\n", ((ifs_st1 & 0x7f000000) >> 24));
+    snprintf_res(cmd_data, "r_ptc_delta_us                          : %d\n", ((ifs_st1 & 0x001f0000) >> 16));
+    snprintf_res(cmd_data, "r_rx_ifs_calc                           : %d\n", ((ifs_st1 & 0x00004000) >> 14));
+    snprintf_res(cmd_data, "r_sigext_sifs_medium_must_idle          : %d\n", ((ifs_st1 & 0x00002000) >> 13));
+    snprintf_res(cmd_data, "r_sigext_sifs_period                    : %d\n", ((ifs_st1 & 0x00001000) >> 12));
+    snprintf_res(cmd_data, "f_navcs_phycs_deassert                  : %d\n", ((ifs_st1 & 0x00000800) >> 11));
+    snprintf_res(cmd_data, "r_ed_cs_phycs                           : %d\n", ((ifs_st1 & 0x00000400) >> 10));
+    snprintf_res(cmd_data, "r_navcs_phycs_proc                      : %d\n", ((ifs_st1 & 0x00000200) >> 9));
+    snprintf_res(cmd_data, "r_lastproc_need_sigext                  : %d\n", ((ifs_st1 & 0x00000100) >> 8));
+    snprintf_res(cmd_data, "r_trig_sifs_or_slot_past                : %d\n", ((ifs_st1 & 0x00000080) >> 7));
+    snprintf_res(cmd_data, "r_mac_rx_proc                           : %d\n", ((ifs_st1 & 0x00000040) >> 6));
+    snprintf_res(cmd_data, "r_rx_proc                               : %d\n", ((ifs_st1 & 0x00000020) >> 5));
+    snprintf_res(cmd_data, "r_tx_proc                               : %d\n", ((ifs_st1 & 0x00000010) >> 4));
+    snprintf_res(cmd_data, "c_navcs_phycs_deassert_alone_set_ifs    : %d\n", ((ifs_st1 & 0x00000008) >> 3));
+    snprintf_res(cmd_data, "g_sigext_proc_start                     : %d\n", ((ifs_st1 & 0x00000004) >> 2));
+    snprintf_res(cmd_data, "g_tx_us_tick_sel                        : %d\n", ((ifs_st1 & 0x00000002) >> 1));
+    snprintf_res(cmd_data, "g_rx_us_tick_sel                        : %d\n", ((ifs_st1 & 0x00000001) >> 0));
+    snprintf_res(cmd_data, "r_rx_ifs_deltatime                      : %d\n", ((ifs_st2 & 0x7fffff00) >> 8));
+    snprintf_res(cmd_data, "r_rx_ifs_delta_us                       : %d\n", ((ifs_st2 & 0x0000001f) >> 0));
+    snprintf_res(cmd_data, "r_eifs_cnt                              : %d\n", ((ifs_st3 & 0x0000003f) >> 0));
+}
+static void ssv6006c_cmd_hwinfo_mac_txbase(struct ssv_hw *sh)
+{
+    struct ssv_cmd_data *cmd_data = &sh->sc->cmd_data;
+    char mtxstr[256];
+    u32 regval;
+    u32 mtx_base1 = GET_RO_MTX_BASE1;
+    u32 mtx_base2 = GET_RO_MTX_BASE2;
+    u32 mtx_base3 = GET_RO_MTX_BASE3;
+    snprintf_res(cmd_data, "f_ptc_sifs                            : 0x%x\n", ((mtx_base1 & 0x04000000) >> 26));
+    snprintf_res(cmd_data, "f_ptc_txsifs                          : 0x%x\n", ((mtx_base1 & 0x20000000) >> 29));
+    snprintf_res(cmd_data, "f_ptc_txsifs_end                      : 0x%x\n", ((mtx_base1 & 0x10000000) >> 28));
+    snprintf_res(cmd_data, "f_ptc_slot                            : 0x%x\n", ((mtx_base1 & 0x01000000) >> 24));
+    snprintf_res(cmd_data, "f_ptc_txslot                          : 0x%x\n", ((mtx_base1 & 0x02000000) >> 25));
+    snprintf_res(cmd_data, "f_ptc_phytxstart                      : 0x%x\n", ((mtx_base1 & 0x08000000) >> 27));
+    snprintf_res(cmd_data, "mac_tx_fifo_wempty                    : 0x%x\n", ((mtx_base1 & 0x00080000) >> 19));
+    snprintf_res(cmd_data, "mac_tx_fifo_wfull_mx                  : 0x%x\n", ((mtx_base1 & 0x00040000) >> 18));
+    snprintf_res(cmd_data, "wait_rx_response                      : 0x%x\n", ((mtx_base1 & 0x00020000) >> 17));
+    snprintf_res(cmd_data, "wait_tx_response                      : 0x%x\n", ((mtx_base1 & 0x00010000) >> 16));
+    snprintf_res(cmd_data, "{cand_beacon_q_mask,cand_edca_q_mask} : 0x%x\n", ((mtx_base1 & 0x00007f00) >> 8));
+    snprintf_res(cmd_data, "{act_pkt_beacon_q_mask,act_q_mask}    : 0x%x\n", ((mtx_base1 & 0x0000007f) >> 0));
+    snprintf_res(cmd_data, "act_nulldatagen                       : 0x%x\n", ((mtx_base1 & 0x00000080) >> 7));
+    snprintf_res(cmd_data, "ro_txop_interval[15:0]: %d\n", ((mtx_base2 & 0xffff0000) >> 16));
+    memset(mtxstr, 0, sizeof(mtxstr));
+    regval = ((mtx_base2 & 0x00003f00) >> 8);
+    ssv6006c_cmd_hwinfo_lookup_mtxdma_cmd(regval, mtxstr);
+    snprintf_res(cmd_data, "%s\n", mtxstr);
+    memset(mtxstr, 0, sizeof(mtxstr));
+    regval = ((mtx_base2 & 0x00000030) >> 4);
+    ssv6006c_cmd_hwinfo_lookup_mac_tx_wait_response_phase(regval, mtxstr);
+    snprintf_res(cmd_data, "%s\n", mtxstr);
+    memset(mtxstr, 0, sizeof(mtxstr));
+    regval = ((mtx_base2 & 0x0000000f) >> 0);
+    ssv6006c_cmd_hwinfo_lookup_mac_tx_ptc_schedule(regval, mtxstr);
+    snprintf_res(cmd_data, "%s\n", mtxstr);
+    snprintf_res(cmd_data, "csr_prescaler_us : %d\n", ((mtx_base3 & 0x000000ff) >> 0));
+    snprintf_res(cmd_data, "act_retry_flag   : %d\n", ((mtx_base3 & 0x80000000) >> 31));
+    snprintf_res(cmd_data, "act_pktid        : %d\n", ((mtx_base3 & 0x7f000000) >> 24));
+    snprintf_res(cmd_data, "act_ratesetidx   : %d\n", ((mtx_base3 & 0x00c00000) >> 22));
+    snprintf_res(cmd_data, "act_trycnt       : %d\n", ((mtx_base3 & 0x000f0000) >> 16));
+}
+static void ssv6006c_cmd_hwinfo_mac_hci_stat(struct ssv_hw *sh)
+{
+    struct ssv_cmd_data *cmd_data = &sh->sc->cmd_data;
+    snprintf_res(cmd_data, "HCI_MONITOR_REG0 : 0x%08x\n", GET_HCI_MONITOR_REG0);
+    snprintf_res(cmd_data, "HCI_MONITOR_REG2 : 0x%08x\n", GET_HCI_MONITOR_REG2);
+    snprintf_res(cmd_data, "HCI_MONITOR_REG3 : 0x%08x\n", GET_HCI_MONITOR_REG3);
+    snprintf_res(cmd_data, "HCI_MONITOR_REG4 : 0x%08x\n", GET_HCI_MONITOR_REG4);
+    snprintf_res(cmd_data, "HCI_MONITOR_REG5 : 0x%08x\n", GET_HCI_MONITOR_REG5);
+}
+static void ssv6006c_cmd_hwinfo_page_id(struct ssv_hw *sh)
+{
+    struct ssv_cmd_data *cmd_data = &sh->sc->cmd_data;
+    snprintf_res(cmd_data, "PAGE ID info:\n");
+    snprintf_res(cmd_data, "TX_ID_COUNT : 0x%08x\n", GET_TX_ID_COUNT);
+    snprintf_res(cmd_data, "RX_ID_COUNT : 0x%08x\n", GET_RX_ID_COUNT);
+    snprintf_res(cmd_data, "TX_ID_THOLD : 0x%08x\n", GET_TX_ID_THOLD);
+    snprintf_res(cmd_data, "RX_ID_THOLD : 0x%08x\n", GET_RX_ID_THOLD);
+    snprintf_res(cmd_data, "TX_PAGE_USE : 0x%08x\n", GET_TX_PAGE_USE_7_0);
+    snprintf_res(cmd_data, "TX_PAGE_THOLD:0x%08x\n", GET_ID_TX_LEN_THOLD);
+    snprintf_res(cmd_data, "RX_PAGE_THOLD:0x%08x\n", GET_ID_RX_LEN_THOLD);
+}
+static void ssv6006c_cmd_hwinfo_phy_pmu(struct ssv_hw *sh)
+{
+    struct ssv_cmd_data *cmd_data = &sh->sc->cmd_data;
+    u32 regval;
+    regval = GET_RO_AD_VBAT_OK;
+    snprintf_res(cmd_data, "RO_AD_VBAT_OK[%d]       : %s\n", regval, ((1 == regval) ? "pass" : "fail"));
+    regval = GET_RO_PMU_STATE;
+    snprintf_res(cmd_data, "GET_RO_PMU_STATE[%d]    : %s\n", regval, ((3 == regval) ? "pass" : "fail"));
+    SMAC_REG_READ(sh, ADR_PMU_REG_3, &regval);
+    snprintf_res(cmd_data, "DCDC/LDO settings ADR_PMU_REG_3 is 0x%08x\n", regval);
+}
+static void ssv6006c_cmd_hwinfo_phy_xtal(struct ssv_hw *sh)
+{
+    struct ssv_cmd_data *cmd_data = &sh->sc->cmd_data;
+    int xtal_freq = 0;
+    char *clock_setting[] = {"16M", "24M", "26M", "40M", "12M", "20M",
+                             "25M", "32M", "19.2M", "38.4M", "52M", "Wrong settings"
+                            };
+    xtal_freq = GET_RG_DP_XTAL_FREQ;
+    xtal_freq = (xtal_freq < 11) ? xtal_freq : 11;
+    snprintf_res(cmd_data, "DPLL reference clock setting is   : %s\n", clock_setting[xtal_freq]);
+    xtal_freq = GET_RG_SX_XTAL_FREQ;
+    xtal_freq = (xtal_freq < 11) ? xtal_freq : 11;
+    snprintf_res(cmd_data, "SX reference clock setting is     : %s\n", clock_setting[xtal_freq]);
+}
+static void ssv6006c_cmd_hwinfo_phy_sx(struct ssv_hw *sh)
+{
+    struct ssv_cmd_data *cmd_data = &sh->sc->cmd_data;
+    snprintf_res(cmd_data, "RG_PHY_MD_EN is           : %d\n", GET_RG_PHY_MD_EN);
+    snprintf_res(cmd_data, "DB_DA_SX_SUB_SEL is       : %d\n", GET_DB_DA_SX_SUB_SEL);
+    snprintf_res(cmd_data, "DB_DA_SX5GB_SUB_SEL is    : %d\n", GET_DB_DA_SX5GB_SUB_SEL);
+    snprintf_res(cmd_data, "DB_SX_SBCAL_NTARGET is    : %d\n", GET_DB_SX_SBCAL_NTARGET);
+    snprintf_res(cmd_data, "DB_SX_SBCAL_NCOUNT is     : %d\n", GET_DB_SX_SBCAL_NCOUNT);
+    snprintf_res(cmd_data, "DB_SX5GB_SBCAL_NTARGET is : %d\n", GET_DB_SX5GB_SBCAL_NTARGET);
+    snprintf_res(cmd_data, "DB_SX5GB_SBCAL_NCOUNT is  : %d\n", GET_DB_SX5GB_SBCAL_NCOUNT);
+    snprintf_res(cmd_data, "RO_RF_CH_FREQ is          : %d MHz\n", GET_RO_RF_CH_FREQ);
+}
+static void ssv6006c_cmd_hwinfo_phy_cali(struct ssv_hw *sh)
+{
+    struct ssv_cmd_data *cmd_data = &sh->sc->cmd_data;
+    int i;
+    u32 regval, wifi_dc_addr, value;
+    snprintf_res(cmd_data, "\n+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\n");
+    snprintf_res(cmd_data, "2G Rx DC calibration results\n");
+    snprintf_res(cmd_data, "+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\n");
+    for (i = 0; i < 21; i++) {
+        wifi_dc_addr = ADR_WF_DCOC_IDAC_REGISTER1 + (i<<2);
+        SMAC_REG_READ(sh, wifi_dc_addr, &regval);
+        snprintf_res(cmd_data, "Turismo register 0x%08x : 0x%08x\n", wifi_dc_addr, regval);
+    }
+    snprintf_res(cmd_data, "\n+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\n");
+    snprintf_res(cmd_data, "5G Rx DC calibration results\n");
+    snprintf_res(cmd_data, "+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\n");
+    for (i = 0; i < 21; i++) {
+        wifi_dc_addr = ADR_5G_DCOC_IDAC_REGISTER1 + (i<<2);
+        SMAC_REG_READ(sh, wifi_dc_addr, &regval);
+        snprintf_res(cmd_data, "Turismo register 0x%08x : 0x%08x\n", wifi_dc_addr, regval);
+    }
+    snprintf_res(cmd_data, "\nBW20 RG_WF_RX_ABBCTUNE is     : %d\n", GET_RG_WF_RX_ABBCTUNE);
+    snprintf_res(cmd_data, "BW40 RG_WF_N_RX_ABBCTUNE is   : %d\n", GET_RG_WF_N_RX_ABBCTUNE);
+    snprintf_res(cmd_data, "\n+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\n");
+    snprintf_res(cmd_data, "Tx DC status\n");
+    snprintf_res(cmd_data, "+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\n");
+    snprintf_res(cmd_data, "RG_WF_TX_DAC_IOFFSET is : %d\n", GET_RG_WF_TX_DAC_IOFFSET);
+    snprintf_res(cmd_data, "RG_WF_TX_DAC_QOFFSET is : %d\n", GET_RG_WF_TX_DAC_QOFFSET);
+    snprintf_res(cmd_data, "RG_BT_TX_DAC_IOFFSET is : %d\n", GET_RG_BT_TX_DAC_IOFFSET);
+    snprintf_res(cmd_data, "RG_BT_TX_DAC_QOFFSET is : %d\n", GET_RG_BT_TX_DAC_QOFFSET);
+    snprintf_res(cmd_data, "RG_5G_TX_DAC_IOFFSET is : %d\n", GET_RG_5G_TX_DAC_IOFFSET);
+    snprintf_res(cmd_data, "RG_5G_TX_DAC_QOFFSET is : %d\n", GET_RG_5G_TX_DAC_QOFFSET);
+    snprintf_res(cmd_data, "\n+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\n");
+    snprintf_res(cmd_data, "Tx IQ status\n");
+    snprintf_res(cmd_data, "+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\n");
+    snprintf_res(cmd_data, "tx 2500 alpha is : %d, tx 2500 theta is : %d\n",
+                 GET_RG_TX_IQ_2500_ALPHA, GET_RG_TX_IQ_2500_THETA);
+    snprintf_res(cmd_data, "tx 5100 alpha is : %d, tx 5100 theta is : %d\n",
+                 GET_RG_TX_IQ_5100_ALPHA, GET_RG_TX_IQ_5100_THETA);
+    snprintf_res(cmd_data, "tx 5500 alpha is : %d, tx 5500 theta is : %d\n",
+                 GET_RG_TX_IQ_5500_ALPHA, GET_RG_TX_IQ_5500_THETA);
+    snprintf_res(cmd_data, "tx 5700 alpha is : %d, tx 5700 theta is : %d\n",
+                 GET_RG_TX_IQ_5700_ALPHA, GET_RG_TX_IQ_5700_THETA);
+    snprintf_res(cmd_data, "tx 5900 alpha is : %d, tx 5900 theta is : %d\n",
+                 GET_RG_TX_IQ_5900_ALPHA, GET_RG_TX_IQ_5900_THETA);
+    snprintf_res(cmd_data, "\n+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\n");
+    snprintf_res(cmd_data, "Rx IQ status\n");
+    snprintf_res(cmd_data, "+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\n");
+    snprintf_res(cmd_data, "rx 2500 alpha is : %d, rx 2500 theta is : %d\n",
+                 GET_RG_RX_IQ_2500_ALPHA, GET_RG_RX_IQ_2500_THETA);
+    snprintf_res(cmd_data, "rx 5100 alpha is : %d, rx 5100 theta is : %d\n",
+                 GET_RG_RX_IQ_5100_ALPHA, GET_RG_RX_IQ_5100_THETA);
+    snprintf_res(cmd_data, "rx 5500 alpha is : %d, rx 5500 theta is : %d\n",
+                 GET_RG_RX_IQ_5500_ALPHA, GET_RG_RX_IQ_5500_THETA);
+    snprintf_res(cmd_data, "rx 5700 alpha is : %d, rx 5700 theta is : %d\n",
+                 GET_RG_RX_IQ_5700_ALPHA, GET_RG_RX_IQ_5700_THETA);
+    snprintf_res(cmd_data, "rx 5900 alpha is : %d, rx 5900 theta is : %d\n",
+                 GET_RG_RX_IQ_5900_ALPHA, GET_RG_RX_IQ_5900_THETA);
+    snprintf_res(cmd_data, "\n+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\n");
+    snprintf_res(cmd_data, "PHY status\n");
+    snprintf_res(cmd_data, "+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\n");
+    SMAC_REG_READ(sh, ADR_WIFI_PHY_COMMON_SYS_REG, &regval);
+    value = ((regval & RG_BB_CLK_SEL_MSK) >> RG_BB_CLK_SEL_SFT);
+    snprintf_res(cmd_data, "RF/PHY reference clock is from %s\n", (value ? "DPLL(80MHz)" : "Xtal(26MHz)"));
+    snprintf_res(cmd_data, "SW channel bandwidth = %sM, channel type=%d\n",
+                 (((sh->sc->hw_chan_type == NL80211_CHAN_HT40MINUS)||(sh->sc->hw_chan_type == NL80211_CHAN_HT40PLUS)) ? "40" : "20"),
+                 sh->sc->hw_chan_type);
+    if (((regval & RG_SYSTEM_BW_MSK)>> RG_SYSTEM_BW_SFT)) {
+        snprintf_res(cmd_data, "PHY is set to 40MHz bandwidth\n");
+        if (((regval & RG_PRIMARY_CH_SIDE_MSK)>>RG_PRIMARY_CH_SIDE_SFT))
+            snprintf_res(cmd_data, "PHY primary channel is high at 40M\n");
+        else
+            snprintf_res(cmd_data, "PHY secondary channel is low at 40M\n");
+    } else
+        snprintf_res(cmd_data, "PHY is set to 20MHz bandwidth\n");
+    snprintf_res(cmd_data, "RO_MRX_EN_CNT 1st read is : %d\n", GET_RO_MRX_EN_CNT);
+    MDELAY(100);
+    snprintf_res(cmd_data, "RO_MRX_EN_CNT 2nd read is : %d\n", GET_RO_MRX_EN_CNT);
+    snprintf_res(cmd_data, "RO_TX_FIFO_EMPTY_CNT is   : %d\n", GET_RO_TX_FIFO_EMPTY_CNT);
+    snprintf_res(cmd_data, "RO_RX_FIFO_FULL_CNT is    : %d\n", GET_RO_RX_FIFO_FULL_CNT);
+    snprintf_res(cmd_data, "RO_MAC_PHY_TRX_EN_SYNC is : %d\n", GET_RO_MAC_PHY_TRX_EN_SYNC);
+    snprintf_res(cmd_data, "RO_CSTATE_TX is           : %d\n", GET_RO_CSTATE_TX);
+    snprintf_res(cmd_data, "RO_TX_IP is               : %d\n", GET_RO_TX_IP);
+    snprintf_res(cmd_data, "RO_CSTATE_RX is           : %d\n", GET_RO_CSTATE_RX);
+    snprintf_res(cmd_data, "RO_AGC_START_80M is       : %d\n", GET_RO_AGC_START_80M);
+    snprintf_res(cmd_data, "RO_CSTATE_AGC is          : %d\n", GET_RO_CSTATE_AGC);
+    snprintf_res(cmd_data, "RO_MRX_RX_EN is           : %d\n", GET_RO_MRX_RX_EN);
+    snprintf_res(cmd_data, "RO_CSTATE_PKT is          : %d\n", GET_RO_CSTATE_PKT);
+}
+static void ssv6006c_cmd_hwinfo_phy_txband(struct ssv_hw *sh)
+{
+    struct ssv_cmd_data *cmd_data = &sh->sc->cmd_data;
+    snprintf_res(cmd_data, "RG_5G_TX_BAND_F0 is   : %d\n", GET_RG_5G_TX_BAND_F0);
+    snprintf_res(cmd_data, "RG_5G_TX_BAND_F1 is   : %d\n", GET_RG_5G_TX_BAND_F1);
+    snprintf_res(cmd_data, "RG_5G_TX_BAND_F2 is   : %d\n", GET_RG_5G_TX_BAND_F2);
+}
+static void ssv6006c_cmd_hwinfo_phy_txgain(struct ssv_hw *sh)
+{
+    struct ssv_cmd_data *cmd_data = &sh->sc->cmd_data;
+    u32 regval;
+    regval = GET_RG_TXGAIN_PHYCTRL;
+    snprintf_res(cmd_data, "TX_GAIN is controlled by[%d]        : %s\n", regval, ((regval==1) ? "PHY" : "RF"));
+    snprintf_res(cmd_data, "2G RG_TX_GAIN is                    : 0x%08x\n\n", GET_RG_TX_GAIN);
+    SMAC_REG_READ(sh, ADR_5G_TX_GAIN_PAFB_CONTROL, &regval);
+    snprintf_res(cmd_data, "5G RG_5G_TX_GAIN_F0 (<5100)is       : 0x%x\n",
+                 ((regval & RG_5G_TX_GAIN_F0_MSK) >> RG_5G_TX_GAIN_F0_SFT));
+    snprintf_res(cmd_data, "5G RG_5G_TX_PAFB_EN_F0 is           : %d\n",
+                 ((regval & RG_5G_TX_PAFB_EN_F0_MSK) >> RG_5G_TX_PAFB_EN_F0_SFT));
+    snprintf_res(cmd_data, "5G RG_5G_TX_GAIN_F1 (5100~5495) is  : 0x%x\n",
+                 ((regval & RG_5G_TX_GAIN_F1_MSK) >> RG_5G_TX_GAIN_F1_SFT));
+    snprintf_res(cmd_data, "5G RG_5G_TX_PAFB_EN_F1 is           : %d\n",
+                 ((regval & RG_5G_TX_PAFB_EN_F1_MSK) >> RG_5G_TX_PAFB_EN_F1_SFT));
+    snprintf_res(cmd_data, "5G RG_5G_TX_GAIN_F2 (5500~5695) is  : 0x%x\n",
+                 ((regval & RG_5G_TX_GAIN_F2_MSK) >> RG_5G_TX_GAIN_F2_SFT));
+    snprintf_res(cmd_data, "5G RG_5G_TX_PAFB_EN_F2 is           : %d\n",
+                 ((regval & RG_5G_TX_PAFB_EN_F2_MSK) >> RG_5G_TX_PAFB_EN_F2_SFT));
+    snprintf_res(cmd_data, "5G RG_5G_TX_GAIN_F3 (>=5700) is     : 0x%x\n",
+                 ((regval & RG_5G_TX_GAIN_F3_MSK) >> RG_5G_TX_GAIN_F3_SFT));
+    snprintf_res(cmd_data, "5G RG_5G_TX_PAFB_EN_F3 is           : %d\n\n",
+                 ((regval & RG_5G_TX_PAFB_EN_F3_MSK) >> RG_5G_TX_PAFB_EN_F3_SFT));
+    SMAC_REG_READ(sh, ADR_5G_TX_PGA_CAPSW_CONTROL_I, &regval);
+    snprintf_res(cmd_data, "Tx PA bias ADR_5G_TX_PGA_CAPSW_CONTROL_I settings is  : 0x%x\n", regval);
+    SMAC_REG_READ(sh, ADR_5G_TX_PGA_CAPSW_CONTROL_II, &regval);
+    snprintf_res(cmd_data, "Tx PA bias ADR_5G_TX_PGA_CAPSW_Control_II settings is : 0x%x\n\n", regval);
+    SMAC_REG_READ(sh, ADR_WIFI_PHY_COMMON_BB_SCALE_REG_0, &regval);
+    snprintf_res(cmd_data, "RG_BB_SCALE_MAN_EN is           : %d\n",
+                 ((regval & RG_BB_SCALE_MAN_EN_MSK) >> RG_BB_SCALE_MAN_EN_SFT));
+    snprintf_res(cmd_data, "RG_BB_SCALE_BARKER_CCK is       : 0x%x\n",
+                 ((regval & RG_BB_SCALE_BARKER_CCK_MSK) >> RG_BB_SCALE_BARKER_CCK_SFT));
+    SMAC_REG_READ(sh, ADR_WIFI_PHY_COMMON_BB_SCALE_REG_1, &regval);
+    snprintf_res(cmd_data, "RG_BB_SCALE_LEGACY is           : 0x%x\n", regval);
+    SMAC_REG_READ(sh, ADR_WIFI_PHY_COMMON_BB_SCALE_REG_2, &regval);
+    snprintf_res(cmd_data, "RG_BB_SCALE_HT20 is             : 0x%x\n", regval);
+    SMAC_REG_READ(sh, ADR_WIFI_PHY_COMMON_BB_SCALE_REG_3, &regval);
+    snprintf_res(cmd_data, "RG_BB_SCALE_HT40 is             : 0x%x\n\n", regval);
+    SMAC_REG_READ(sh, ADR_WIFI_PHY_COMMON_RF_PWR_REG_0, &regval);
+    snprintf_res(cmd_data, "RG_RF_PWR_MAN_EN is             : %d\n",
+                 ((regval & RG_RF_PWR_MAN_EN_MSK) >> RG_RF_PWR_MAN_EN_SFT));
+    snprintf_res(cmd_data, "RG_RF_PWR_BARKER_CCK is         : 0x%x\n",
+                 ((regval & RG_RF_PWR_BARKER_CCK_MSK) >> RG_RF_PWR_BARKER_CCK_SFT));
+    SMAC_REG_READ(sh, ADR_WIFI_PHY_COMMON_RF_PWR_REG_1, &regval);
+    snprintf_res(cmd_data, "RG_RF_PWR_LEGACY is             : 0x%x\n", regval);
+    SMAC_REG_READ(sh, ADR_WIFI_PHY_COMMON_RF_PWR_REG_2, &regval);
+    snprintf_res(cmd_data, "RG_RF_PWR_HT20 is               : 0x%x\n", regval);
+    SMAC_REG_READ(sh, ADR_WIFI_PHY_COMMON_RF_PWR_REG_3, &regval);
+    snprintf_res(cmd_data, "RG_RF_PWR_HT40 is               : 0x%x\n\n", regval);
+    SMAC_REG_READ(sh, ADR_WIFI_PADPD_5G_BB_GAIN_REG, &regval);
+    snprintf_res(cmd_data, "RG_DPD_BB_SCALE_5100 is : 0x%x\n",
+                 ((regval & RG_DPD_BB_SCALE_5100_MSK) >> RG_DPD_BB_SCALE_5100_SFT));
+    snprintf_res(cmd_data, "RG_DPD_BB_SCALE_5500 is : 0x%x\n",
+                 ((regval & RG_DPD_BB_SCALE_5500_MSK) >> RG_DPD_BB_SCALE_5500_SFT));
+    snprintf_res(cmd_data, "RG_DPD_BB_SCALE_5700 is : 0x%x\n",
+                 ((regval & RG_DPD_BB_SCALE_5700_MSK) >> RG_DPD_BB_SCALE_5700_SFT));
+    snprintf_res(cmd_data, "RG_DPD_BB_SCALE_5900 is : 0x%x\n",
+                 ((regval & RG_DPD_BB_SCALE_5900_MSK) >> RG_DPD_BB_SCALE_5900_SFT));
+    SMAC_REG_READ(sh, ADR_WIFI_PADPD_2G_BB_GAIN_REG, &regval);
+    snprintf_res(cmd_data, "RG_DPD_BB_SCALE_2500 is : 0x%x\n\n",
+                 ((regval & RG_DPD_BB_SCALE_2500_MSK) >> RG_DPD_BB_SCALE_2500_SFT));
+    regval = GET_RG_DPD_AM_EN;
+    snprintf_res(cmd_data, "Tx PADPD AM is turned[%d] %s\n", regval, ((regval) ? "ON" : "OFF"));
+    regval = GET_RG_DPD_PM_EN;
+    snprintf_res(cmd_data, "Tx PADPD PM is turned[%d] %s\n", regval, ((regval) ? "ON" : "OFF"));
+    regval = GET_RG_DPD_PM_AMSEL;
+    snprintf_res(cmd_data, "Tx PADPD PM table is controlled by %s[%d] signal\n", ((regval) ? "DPD" : "orignal"), regval);
+}
+static void ssv6006c_cmd_hwinfo(struct ssv_hw *sh, int argc, char *argv[])
+{
+    struct ssv_cmd_data *cmd_data = &sh->sc->cmd_data;
+    if (argc < 2) {
+        snprintf_res(cmd_data, "hwmsg [mac|phy]\n\n");
+        return;
+    }
+    if (!strcmp(argv[1], "mac")) {
+        if ((argc == 3) && (!strcmp(argv[2], "peer"))) {
+            ssv6006c_cmd_hwinfo_mac_peer_stat(sh);
+        } else if ((argc == 3) && (!strcmp(argv[2], "stat"))) {
+            ssv6006c_cmd_hwinfo_mac_stat(sh);
+        } else if ((argc == 3) && (!strcmp(argv[2], "scrt"))) {
+            ssv6006c_cmd_hwinfo_mac_scrt_stat(sh);
+        } else if ((argc == 3) && (!strcmp(argv[2], "beacon"))) {
+            ssv6006c_cmd_hwinfo_mac_beacon(sh);
+        } else if ((argc == 3) && (!strcmp(argv[2], "txq"))) {
+            ssv6006c_cmd_hwinfo_mac_txq(sh);
+        } else if ((argc == 3) && (!strcmp(argv[2], "edca"))) {
+            ssv6006c_cmd_hwinfo_mac_edca(sh);
+        } else if ((argc == 3) && (!strcmp(argv[2], "tx"))) {
+            ssv6006c_cmd_hwinfo_mac_txstat(sh);
+        } else if ((argc == 3) && (!strcmp(argv[2], "tx2phy"))) {
+            ssv6006c_cmd_hwinfo_mac_tx2phy(sh);
+        } else if ((argc == 3) && (!strcmp(argv[2], "tx2ptc"))) {
+            ssv6006c_cmd_hwinfo_mac_tx2ptc(sh);
+        } else if ((argc == 3) && (!strcmp(argv[2], "fixrate"))) {
+            ssv6006c_cmd_hwinfo_mac_fixrate(sh);
+        } else if ((argc == 3) && (!strcmp(argv[2], "txfsm"))) {
+            ssv6006c_cmd_hwinfo_mac_txfsm(sh);
+        } else if ((argc == 3) && (!strcmp(argv[2], "txifs"))) {
+            ssv6006c_cmd_hwinfo_mac_txifs(sh);
+        } else if ((argc == 3) && (!strcmp(argv[2], "txbase"))) {
+            ssv6006c_cmd_hwinfo_mac_txbase(sh);
+        } else if ((argc == 3) && (!strcmp(argv[2], "hci"))) {
+            ssv6006c_cmd_hwinfo_mac_hci_stat(sh);
+        } else if ((argc == 3) && (!strcmp(argv[2], "pgid"))) {
+            ssv6006c_cmd_hwinfo_page_id(sh);
+        } else {
+            snprintf_res(cmd_data, "hwmsg mac [peer|stat|scrt|beacon|txq|edca|tx|tx2phy|tx2ptc|fixrate|txfsm|txifs|txbase|hci|pgid]\n\n");
+        }
+    } else if (!strcmp(argv[1], "phy")) {
+        if ((argc == 3) && (!strcmp(argv[2], "pmu"))) {
+            ssv6006c_cmd_hwinfo_phy_pmu(sh);
+        } else if ((argc == 3) && (!strcmp(argv[2], "xtal"))) {
+            ssv6006c_cmd_hwinfo_phy_xtal(sh);
+        } else if ((argc == 3) && (!strcmp(argv[2], "sx"))) {
+            ssv6006c_cmd_hwinfo_phy_sx(sh);
+        } else if ((argc == 3) && (!strcmp(argv[2], "cali"))) {
+            ssv6006c_cmd_hwinfo_phy_cali(sh);
+        } else if ((argc == 3) && (!strcmp(argv[2], "txband"))) {
+            ssv6006c_cmd_hwinfo_phy_txband(sh);
+        } else if ((argc == 3) && (!strcmp(argv[2], "txgain"))) {
+            ssv6006c_cmd_hwinfo_phy_txgain(sh);
+        } else {
+            snprintf_res(cmd_data, "hwmsg phy [pmu|xtal|sx|cali|txband|txgain]\n\n");
+        }
+    } else {
+        snprintf_res(cmd_data, "hwmsg [mac|phy]\n\n");
+    }
+    return;
+}
+static void ssv6006c_get_rd_id_adr(u32 *id_base_address)
+{
+    id_base_address[0] = ADR_RD_ID0;
+    id_base_address[1] = ADR_RD_ID1;
+    id_base_address[2] = ADR_RD_ID2;
+    id_base_address[3] = ADR_RD_ID3;
+}
+static int ssv6006c_burst_read_reg(struct ssv_hw *sh, u32 *addr, u32 *buf, u8 reg_amount)
+{
+    int ret = (-1), i;
+    u32 dev_type = HCI_DEVICE_TYPE(sh->hci.hci_ctrl);
+    if (dev_type == SSV_HWIF_INTERFACE_SDIO) {
+        ret = SMAC_BURST_REG_READ(sh, addr, buf, reg_amount);
+    } else {
+        for (i = 0 ; i < reg_amount ; i++) {
+            ret = SMAC_REG_READ(sh, addr[i], &buf[i]);
+            if (ret != 0) {
+                dev_dbg(sh->sc->dev, "%s(): read 0x%08x failed.\n", __func__, addr[i]);
+                break;
+            }
+        }
+    }
+    return ret;
+}
+static int ssv6006c_burst_write_reg(struct ssv_hw *sh, u32 *addr, u32 *buf, u8 reg_amount)
+{
+    int ret = (-1), i;
+    u32 dev_type = HCI_DEVICE_TYPE(sh->hci.hci_ctrl);
+    if (dev_type == SSV_HWIF_INTERFACE_SDIO) {
+        ret = SMAC_BURST_REG_WRITE(sh, addr, buf, reg_amount);
+    } else {
+        for (i = 0 ; i < reg_amount ; i++) {
+            ret = SMAC_REG_WRITE(sh, addr[i], buf[i]);
+            if (ret != 0) {
+                dev_dbg(sh->sc->dev, "%s(): write 0x%08x failed.\n", __func__, addr[i]);
+                break;
+            }
+        }
+    }
+    return ret;
+}
+static int ssv6006c_auto_gen_nullpkt(struct ssv_hw *sh, int hwq)
+{
+    switch (hwq) {
+    case 0:
+        SET_TXQ0_Q_NULLDATAFRAME_GEN_EN(1);
+        MDELAY(100);
+        SET_TXQ0_Q_NULLDATAFRAME_GEN_EN(0);
+        break;
+    case 1:
+        SET_TXQ1_Q_NULLDATAFRAME_GEN_EN(1);
+        MDELAY(100);
+        SET_TXQ1_Q_NULLDATAFRAME_GEN_EN(0);
+        break;
+    case 2:
+        SET_TXQ2_Q_NULLDATAFRAME_GEN_EN(1);
+        MDELAY(100);
+        SET_TXQ2_Q_NULLDATAFRAME_GEN_EN(0);
+        break;
+    case 3:
+        SET_TXQ3_Q_NULLDATAFRAME_GEN_EN(1);
+        MDELAY(100);
+        SET_TXQ3_Q_NULLDATAFRAME_GEN_EN(0);
+        break;
+    case 4:
+        SET_TXQ4_Q_NULLDATAFRAME_GEN_EN(1);
+        MDELAY(100);
+        SET_TXQ4_Q_NULLDATAFRAME_GEN_EN(0);
+        break;
+    case 5:
+        SET_TXQ5_Q_NULLDATAFRAME_GEN_EN(1);
+        MDELAY(100);
+        SET_TXQ5_Q_NULLDATAFRAME_GEN_EN(0);
+        break;
+    default:
+        return -EOPNOTSUPP;
+    }
+    return 0;
+}
+static void ssv6006c_load_fw_enable_mcu(struct ssv_hw *sh)
+{
+    SET_N10CFG_DEFAULT_IVB(0);
+    SET_CLK_EN_CPUN10(1);
+    SET_RESET_N_CPUN10(1);
+}
+static int ssv6006c_load_fw_disable_mcu(struct ssv_hw *sh)
+{
+    int ret = 0;
+    if (ssv6006c_reset_cpu(sh) != 0)
+        return -1;
+    SET_CLK_EN_CPUN10(0);
+    SET_MCU_ENABLE(0);
+    SET_RG_REBOOT(1);
+    return ret;
+}
+static int ssv6006c_load_fw_set_status(struct ssv_hw *sh, u32 status)
+{
+    return SMAC_REG_WRITE(sh, ADR_TX_SEG, status);
+}
+static int ssv6006c_load_fw_get_status(struct ssv_hw *sh, u32 *status)
+{
+    return SMAC_REG_READ(sh, ADR_TX_SEG, status);
+}
+static void ssv6006c_load_fw_pre_config_device(struct ssv_hw *sh)
+{
+    HCI_LOAD_FW_PRE_CONFIG_DEVICE(sh->hci.hci_ctrl);
+}
+static void ssv6006c_load_fw_post_config_device(struct ssv_hw *sh)
+{
+    HCI_LOAD_FW_POST_CONFIG_DEVICE(sh->hci.hci_ctrl);
+}
+static int ssv6006c_reset_cpu(struct ssv_hw *sh)
+{
+    u32 org_int_mask = GET_MASK_TYPMCU_INT_MAP;
+    u32 cnt = 0;
+    if (GET_RESET_N_CPUN10) {
+        SET_MASK_TYPMCU_INT_MAP(0xffffdfff);
+        SET_SYSCTRL_CMD(0x0000000e);
+        while(!GET_N10_STANDBY) {
+            cnt++;
+            if (cnt > 10) {
+                dev_dbg(sh->sc->dev, "Reset CPU failed! CPU can't enter standby\n");
+                return -1;
+            }
+        }
+    }
+    SET_RESET_N_CPUN10(0);
+    SET_MASK_TYPMCU_INT_MAP(org_int_mask);
+    return 0;
+}
+static void ssv6006c_set_sram_mode(struct ssv_hw *sh, enum SSV_SRAM_MODE mode)
+{
+    switch (mode) {
+    case SRAM_MODE_ILM_64K_DLM_128K:
+        SMAC_REG_SET_BITS(sh, 0xc0000128, (0<<1), 0x2);
+        break;
+    case SRAM_MODE_ILM_160K_DLM_32K:
+        SMAC_REG_SET_BITS(sh, 0xc0000128, (1<<1), 0x2);
+        break;
+    }
+}
+static void ssv6006c_enable_usb_acc(struct ssv_softc *sc, u8 epnum)
+{
+    switch (epnum) {
+    case SSV_EP_CMD:
+        dev_info(sc->dev, "Enable Command(ep%d) acc\n", SSV_EP_CMD);
+        SMAC_REG_SET_BITS(sc->sh, 0x700041AC, (1<<0), 0x1);
+        break;
+    case SSV_EP_RSP:
+        dev_info(sc->dev, "Enable Command Rsp(ep%d) acc\n", SSV_EP_RSP);
+        SMAC_REG_SET_BITS(sc->sh, 0x700041AC, (1<<1), 0x2);
+        break;
+    case SSV_EP_TX:
+        dev_info(sc->dev, "Enable TX(ep%d) acc\n", SSV_EP_TX);
+        SMAC_REG_SET_BITS(sc->sh, 0x700041AC, (1<<2), 0x4);
+        break;
+    case SSV_EP_RX:
+        dev_info(sc->dev, "Enable RX(ep%d) acc\n", SSV_EP_RX);
+        SMAC_REG_SET_BITS(sc->sh, 0x700041AC, (1<<3), 0x8);
+        break;
+    }
+}
+static void ssv6006c_disable_usb_acc(struct ssv_softc *sc, u8 epnum)
+{
+    switch (epnum) {
+    case SSV_EP_CMD:
+        dev_info(sc->dev, "Disable Command(ep%d) acc\n", SSV_EP_CMD);
+        SMAC_REG_SET_BITS(sc->sh, 0x700041AC, (0<<0), 0x1);
+        break;
+    case SSV_EP_RSP:
+        dev_info(sc->dev, "Disable Command Rsp(ep%d) acc\n", SSV_EP_RSP);
+        SMAC_REG_SET_BITS(sc->sh, 0x700041AC, (0<<1), 0x2);
+        break;
+    case SSV_EP_TX:
+        dev_info(sc->dev, "Disable TX(ep%d) acc\n", SSV_EP_TX);
+        SMAC_REG_SET_BITS(sc->sh, 0x700041AC, (0<<2), 0x4);
+        break;
+    case SSV_EP_RX:
+        dev_info(sc->dev, "Disable RX(ep%d) acc\n", SSV_EP_RX);
+        SMAC_REG_SET_BITS(sc->sh, 0x700041AC, (0<<3), 0x8);
+        break;
+    }
+}
+static void ssv6006c_set_usb_lpm(struct ssv_softc *sc, u8 enable)
+{
+    int dev_type = HCI_DEVICE_TYPE(sc->sh->hci.hci_ctrl);
+    int i = 0;
+    if (dev_type != SSV_HWIF_INTERFACE_USB) {
+        dev_dbg(sc->dev, "Not support set USB LPM for this model!!\n");
+        return;
+    }
+    for(i=0 ; i<SSV6200_MAX_VIF ; i++) {
+        if (sc->vif_info[i].vif == NULL)
+            continue;
+        if (sc->vif_info[i].vif->type == NL80211_IFTYPE_AP) {
+            dev_dbg(sc->dev, "Force to disable USB LPM function due to exist AP interface\n");
+            SMAC_REG_SET_BITS(sc->sh, 0x70004008, (0 << 11), 0x800);
+            return;
+        }
+    }
+    dev_dbg(sc->dev, "Set USB LPM support to %d\n", enable);
+    SMAC_REG_SET_BITS(sc->sh, 0x70004008, (enable << 11), 0x800);
+}
+static int ssv6006c_jump_to_rom(struct ssv_softc *sc)
+{
+    struct ssv_hw *sh = sc->sh;
+    int ret = 0;
+    dev_info(sc->dev, "Jump to ROM\n");
+    if (ssv6006c_reset_cpu(sh) != 0)
+        return -1;
+    SET_N10CFG_DEFAULT_IVB(0x4);
+    SET_RESET_N_CPUN10(1);
+    msleep(50);
+    return ret;
+}
+static void ssv6006c_init_gpio_cfg(struct ssv_hw *sh)
+{
+    SET_MANUAL_IO(0x8000);
+}
+static void ssv6006c_cmd_efuse(struct ssv_hw *sh, int argc, char *argv[])
+{
+    struct ssv_softc *sc = sh->sc;
+    struct ssv_cmd_data *cmd_data = &sc->cmd_data;
+    u8 efuse_mapping_table[EFUSE_HWSET_MAX_SIZE/8];
+    u8 mac[ETH_ALEN], oldmac[ETH_ALEN], newmac[ETH_ALEN];
+    int i = 0;
+    int j = 0;
+    char *endp;
+    u8 value8, value;
+    u32 value32 = 0, category_idx = 0;
+    int shift = 0;
+    u8 efuse_real_content_len = 0;
+    char *efuse_map_name[] = {"none", "cali", "sar", "oldmac", "freq", "txpower1", "txpower2",
+                              "chipid", "none1", "vid", "pid", "mac", "ratetbl1", "ratetbl2"
+                             };
+    struct efuse_map ssv_efuse_item_table[] = {
+        {4, 0, 0},
+        {4, 8, 0},
+        {4, 8, 0},
+        {4, 48, 0},
+        {4, 8, 0},
+        {4, 8, 0},
+        {4, 8, 0},
+        {4, 4, 0},
+        {4, 0, 0},
+        {4, 16, 0},
+        {4, 16, 0},
+        {4, 48, 0},
+        {4, 8, 0},
+        {4, 8, 0},
+    };
+    if ((argc == 4) && (strcmp(argv[1], "w") == 0)) {
+        memset(mac, 0x00, ETH_ALEN);
+        memset(oldmac, 0x00, ETH_ALEN);
+        memset(newmac, 0x00, ETH_ALEN);
+        memset(efuse_mapping_table, 0x00, EFUSE_HWSET_MAX_SIZE/8);
+        for (i = EFUSE_R_CALIBRATION_RESULT; i <= EFUSE_RATE_TABLE_2; i++) {
+            if (!strcmp(argv[2], efuse_map_name[i])) {
+                if ((i == NO_USE) || (i == EFUSE_MAC))
+                    break;
+                if (i == EFUSE_MAC_NEW) {
+                    memset(mac, 0x00, ETH_ALEN);
+                    if (6 == sscanf(argv[3], "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx",
+                                    &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5])) {
+                        if (!is_valid_ether_addr(mac)) {
+                            snprintf_res(cmd_data, "Invalid mac address\n");
+                            return;
+                        }
+                    } else {
+                        snprintf_res(cmd_data, "Invalid mac address\n");
+                        return;
+                    }
+                    break;
+                } else {
+                    value32 = simple_strtoul(argv[3], &endp, 16);
+                    if (ssv_efuse_item_table[i].byte_cnts == 4)
+                        value32 = (value32 & 0xf);
+                    else if (ssv_efuse_item_table[i].byte_cnts == 8)
+                        value32 = (value32 & 0xff);
+                    else if (ssv_efuse_item_table[i].byte_cnts == 16)
+                        value32 = (value32 & 0xffff);
+                    else {
+                        snprintf_res(cmd_data, "Invalid value\n");
+                        return;
+                    }
+                    break;
+                }
+            }
+        }
+        if ((i == EFUSE_R_CALIBRATION_RESULT) || (i == EFUSE_SAR_RESULT) ||
+            (i == EFUSE_MAC) || (i == EFUSE_CHIP_ID) ||
+            (i == NO_USE) || (i == EFUSE_VID) ||
+            (i == EFUSE_PID) || (i > EFUSE_RATE_TABLE_2)) {
+            snprintf_res(cmd_data, "efuse w [freq|txpower1|txpower2|mac|ratetbl1|ratetbl2] value\n");
+            return;
+        }
+        category_idx = i;
+        SSV_READ_EFUSE(sh, efuse_mapping_table);
+        efuse_real_content_len = parser_efuse(sh, efuse_mapping_table, oldmac, newmac, ssv_efuse_item_table);
+        ssv_efuse_item_table[category_idx].value = value32;
+        shift = efuse_real_content_len % 8;
+        if (shift) {
+            value8 = efuse_mapping_table[efuse_real_content_len>>3];
+            value8 &= 0x0f;
+            efuse_mapping_table[efuse_real_content_len>>3] = ((category_idx << 4) | value8);
+            efuse_real_content_len += ssv_efuse_item_table[category_idx].offset;
+        } else {
+            efuse_mapping_table[efuse_real_content_len>>3] = (category_idx & 0x0f);
+            efuse_real_content_len += ssv_efuse_item_table[category_idx].offset;
+        }
+        for (j = 0; j < ssv_efuse_item_table[category_idx].byte_cnts; j=j+4) {
+            if (category_idx == EFUSE_MAC_NEW) {
+                if (0 == (j % 8))
+                    value = mac[j>>3] & 0xff;
+                else
+                    value = (mac[j>>3] & 0xf0) >> 4;
+            } else
+                value = ((ssv_efuse_item_table[category_idx].value >> j) & 0xff);
+            shift = efuse_real_content_len % 8;
+            if (shift) {
+                value8 = efuse_mapping_table[efuse_real_content_len>>3];
+                value8 &= 0x0f;
+                efuse_mapping_table[efuse_real_content_len>>3] = ((value << 4) | value8);
+                efuse_real_content_len += 4;
+            } else {
+                efuse_mapping_table[efuse_real_content_len>>3] = (value & 0x0f);
+                efuse_real_content_len += 4;
+            }
+        }
+        if (efuse_real_content_len > EFUSE_HWSET_MAX_SIZE) {
+            snprintf_res(cmd_data, "No enough efuse space\n");
+            return;
+        }
+        SSV_WRITE_EFUSE(sh, efuse_mapping_table, efuse_real_content_len);
+        memset(oldmac, 0x00, ETH_ALEN);
+        memset(newmac, 0x00, ETH_ALEN);
+        memset(efuse_mapping_table, 0x00, EFUSE_HWSET_MAX_SIZE/8);
+        SSV_READ_EFUSE(sh, efuse_mapping_table);
+        parser_efuse(sh, efuse_mapping_table, oldmac, newmac, ssv_efuse_item_table);
+        if (category_idx == EFUSE_MAC_NEW) {
+            snprintf_res(cmd_data, "Efuse mac[%d] = %02x:%02x:%02x:%02x:%02x:%02x\n",
+                         EFUSE_MAC_NEW, newmac[0], newmac[1], newmac[2], newmac[3], newmac[4], newmac[5]);
+        } else {
+            snprintf_res(cmd_data, "Efuse %s[%d] = 0x%02x\n",
+                         efuse_map_name[category_idx], category_idx, ssv_efuse_item_table[category_idx].value);
+        }
+        return;
+    } else if ((argc == 3) && (strcmp(argv[1], "r") == 0)) {
+        memset(oldmac, 0x00, ETH_ALEN);
+        memset(newmac, 0x00, ETH_ALEN);
+        memset(efuse_mapping_table, 0x00, EFUSE_HWSET_MAX_SIZE/8);
+        SSV_READ_EFUSE(sh, efuse_mapping_table);
+        parser_efuse(sh, efuse_mapping_table, oldmac, newmac, ssv_efuse_item_table);
+        for (i = EFUSE_R_CALIBRATION_RESULT; i <= EFUSE_RATE_TABLE_2; i++) {
+            if (!strcmp(argv[2], efuse_map_name[i])) {
+                if ((i == NO_USE) || (i == EFUSE_MAC))
+                    break;
+                if (i == EFUSE_MAC_NEW) {
+                    if (!is_valid_ether_addr(newmac))
+                        snprintf_res(cmd_data, "Efuse cannot read %s value\n", argv[2]);
+                    else {
+                        snprintf_res(cmd_data, "Efuse mac[%d] = %02x:%02x:%02x:%02x:%02x:%02x\n",
+                                     EFUSE_MAC_NEW, newmac[0], newmac[1], newmac[2], newmac[3], newmac[4], newmac[5]);
+                    }
+                    break;
+                } else {
+                    if (!(sh->efuse_bitmap & BIT(i)))
+                        snprintf_res(cmd_data, "Efuse cannot read %s value\n", argv[2]);
+                    else {
+                        snprintf_res(cmd_data, "Efuse %s[%d] = 0x%02x\n",
+                                     argv[2], i, ssv_efuse_item_table[i].value);
+                    }
+                    break;
+                }
+            }
+        }
+        if ((i == EFUSE_R_CALIBRATION_RESULT) || (i == EFUSE_SAR_RESULT) ||
+            (i == EFUSE_MAC) || (i == EFUSE_CHIP_ID) ||
+            (i == NO_USE) || (i == EFUSE_VID) ||
+            (i == EFUSE_PID) || (i > EFUSE_RATE_TABLE_2)) {
+            snprintf_res(cmd_data, "efuse r [freq|txpower1|txpower2|mac|ratetbl1|ratetbl2] value\n");
+        }
+        return;
+    } else {
+        snprintf_res(cmd_data, "efuse [r|w] [category] [value]\n\n");
+    }
+}
+static void ssv6006c_update_product_hw_setting(struct ssv_hw *sh)
+{
+    return;
+}
+void ssv6006c_set_on3_enable(struct ssv_hw *sh, bool val)
+{
+    SMAC_REG_WRITE(sh, ADR_POWER_ON_OFF_CTRL, 0x7334);
+    if (val)
+        SMAC_REG_WRITE(sh, ADR_SYSCTRL_COMMAND, 0x80c);
+    else
+        SMAC_REG_WRITE(sh, ADR_SYSCTRL_COMMAND, 0x40c);
+}
+static void ssv6006c_wait_usb_rom_ready(struct ssv_hw *sh)
+{
+    int i = 0;
+    u32 dev_type = HCI_DEVICE_TYPE(sh->hci.hci_ctrl);
+    if (dev_type == SSV_HWIF_INTERFACE_USB) {
+        while (GET_USB20_HOST_SELRW == 0) {
+            i ++;
+            if (i > 100) break;
+            mdelay(1);
+        }
+        dev_dbg(sh->sc->dev, "wait %d ms for usb rom code ready\n", i);
+    }
+}
+static void ssv6006c_detach_usb_hci(struct ssv_hw *sh)
+{
+    SET_USB20_HOST_SELRW(0);
+}
+static void ssv6006c_pll_chk(struct ssv_hw *sh)
+{
+    u32 regval;
+    regval = GET_CLK_DIGI_SEL;
+    if (regval != 8) {
+        HAL_INIT_PLL(sh);
+        SET_MAC_CLK_80M(1);
+        SET_PHYTXSTART_NCYCLE(26);
+        SET_PRESCALER_US(80);
+    }
+}
+void ssv_attach_ssv6006c_mac(struct ssv_hal_ops *hal_ops)
+{
+    hal_ops->init_mac = ssv6006c_init_mac;
+    hal_ops->reset_sysplf = ssv6006c_reset_sysplf;
+    hal_ops->init_hw_sec_phy_table = ssv6006c_init_hw_sec_phy_table;
+    hal_ops->write_mac_ini = ssv6006c_write_mac_ini;
+    hal_ops->set_rx_flow = ssv6006c_set_rx_flow;
+    hal_ops->set_rx_ctrl_flow = ssv6006c_set_rx_ctrl_flow;
+    hal_ops->set_macaddr = ssv6006c_set_macaddr;
+    hal_ops->set_bssid = ssv6006c_set_bssid;
+    hal_ops->get_ic_time_tag = ssv6006c_get_ic_time_tag;
+    hal_ops->get_chip_id = ssv6006c_get_chip_id;
+    hal_ops->set_mrx_mode = ssv6006c_set_mrx_mode;
+    hal_ops->get_mrx_mode = ssv6006c_get_mrx_mode;
+    hal_ops->save_hw_status = ssv6006c_save_hw_status;
+    hal_ops->set_hw_wsid = ssv6006c_set_hw_wsid;
+    hal_ops->del_hw_wsid = ssv6006c_del_hw_wsid;
+    hal_ops->set_aes_tkip_hw_crypto_group_key = ssv6006c_set_aes_tkip_hw_crypto_group_key;
+    hal_ops->write_pairwise_keyidx_to_hw = ssv6006c_write_pairwise_keyidx_to_hw;
+    hal_ops->write_group_keyidx_to_hw = ssv6006c_write_hw_group_keyidx;
+    hal_ops->write_pairwise_key_to_hw = ssv6006c_write_pairwise_key_to_hw;
+    hal_ops->write_group_key_to_hw = ssv6006c_write_group_key_to_hw;
+    hal_ops->write_key_to_hw = ssv6006c_write_key_to_hw;
+    hal_ops->set_pairwise_cipher_type = ssv6006c_set_pairwise_cipher_type;
+    hal_ops->set_group_cipher_type = ssv6006c_set_group_cipher_type;
+#ifdef CONFIG_PM
+    hal_ops->save_clear_trap_reason = ssv6006c_save_clear_trap_reason;
+    hal_ops->restore_trap_reason = ssv6006c_restore_trap_reason;
+    hal_ops->pmu_awake = ssv6006c_pmu_awake;
+#endif
+    hal_ops->store_wep_key = ssv6006c_store_wep_key;
+    hal_ops->set_replay_ignore = ssv6006c_set_replay_ignore;
+    hal_ops->update_decision_table_6 = ssv6006c_update_decision_table_6;
+    hal_ops->update_decision_table = ssv6006c_update_decision_table;
+    hal_ops->get_fw_version = ssv6006c_get_fw_version;
+    hal_ops->set_op_mode = ssv6006c_set_op_mode;
+    hal_ops->set_halt_mngq_util_dtim = ssv6006c_set_halt_mngq_util_dtim;
+    hal_ops->set_dur_burst_sifs_g = ssv6006c_set_dur_burst_sifs_g;
+    hal_ops->set_dur_slot = ssv6006c_set_dur_slot;
+    hal_ops->set_sifs = ssv6006c_set_sifs;
+    hal_ops->set_qos_enable = ssv6006c_set_qos_enable;
+    hal_ops->set_wmm_param = ssv6006c_set_wmm_param;
+    hal_ops->update_page_id = ssv6006c_update_page_id;
+    hal_ops->alloc_pbuf = ssv6006c_alloc_pbuf;
+    hal_ops->free_pbuf = ssv6006c_free_pbuf;
+    hal_ops->ampdu_auto_crc_en = ssv6006c_ampdu_auto_crc_en;
+    hal_ops->set_rx_ba = ssv6006c_set_rx_ba;
+    hal_ops->read_efuse = ssv6006c_read_efuse;
+    hal_ops->write_efuse = ssv6006c_write_efuse;
+    hal_ops->chg_clk_src = ssv6006c_chg_clk_src;
+    hal_ops->beacon_get_valid_cfg = ssv6006c_beacon_get_valid_cfg;
+    hal_ops->set_beacon_reg_lock = ssv6006c_set_beacon_reg_lock;
+    hal_ops->set_beacon_id_dtim = ssv6006c_set_beacon_id_dtim;
+    hal_ops->fill_beacon = ssv6006c_fill_beacon;
+    hal_ops->beacon_enable = ssv6006c_beacon_enable;
+    hal_ops->set_beacon_info = ssv6006c_set_beacon_info;
+    hal_ops->get_bcn_ongoing = ssv6006c_get_bcn_ongoing;
+    hal_ops->beacon_loss_enable = ssv6006c_beacon_loss_enable;
+    hal_ops->beacon_loss_disable = ssv6006c_beacon_loss_disable;
+    hal_ops->beacon_loss_config = ssv6006c_beacon_loss_config;
+    hal_ops->update_txq_mask = ssv6006c_update_txq_mask;
+    hal_ops->readrg_hci_inq_info = ssv6006c_readrg_hci_inq_info;
+    hal_ops->readrg_txq_info = ssv6006c_readrg_txq_info;
+    hal_ops->readrg_txq_info2 = ssv6006c_readrg_txq_info2;
+    hal_ops->dump_wsid = ssv6006c_dump_wsid;
+    hal_ops->dump_decision = ssv6006c_dump_decision;
+    hal_ops->get_ffout_cnt = ssv6006c_get_ffout_cnt;
+    hal_ops->get_in_ffcnt = ssv6006c_get_in_ffcnt;
+    hal_ops->read_ffout_cnt = ssv6006c_read_ffout_cnt;
+    hal_ops->read_in_ffcnt = ssv6006c_read_in_ffcnt;
+    hal_ops->read_id_len_threshold = ssv6006c_read_id_len_threshold;
+    hal_ops->read_tag_status = ssv6006c_read_tag_status;
+    hal_ops->cmd_mib = ssv6006c_cmd_mib;
+    hal_ops->cmd_power_saving = ssv6006c_cmd_power_saving;
+    hal_ops->cmd_loopback_start = ssv6006c_cmd_loopback_start;
+    hal_ops->cmd_hwinfo = ssv6006c_cmd_hwinfo;
+    hal_ops->get_rd_id_adr = ssv6006c_get_rd_id_adr;
+    hal_ops->burst_read_reg = ssv6006c_burst_read_reg;
+    hal_ops->burst_write_reg = ssv6006c_burst_write_reg;
+    hal_ops->auto_gen_nullpkt = ssv6006c_auto_gen_nullpkt;
+    hal_ops->load_fw_enable_mcu = ssv6006c_load_fw_enable_mcu;
+    hal_ops->load_fw_disable_mcu = ssv6006c_load_fw_disable_mcu;
+    hal_ops->load_fw_set_status = ssv6006c_load_fw_set_status;
+    hal_ops->load_fw_get_status = ssv6006c_load_fw_get_status;
+    hal_ops->load_fw_pre_config_device = ssv6006c_load_fw_pre_config_device;
+    hal_ops->load_fw_post_config_device = ssv6006c_load_fw_post_config_device;
+    hal_ops->reset_cpu = ssv6006c_reset_cpu;
+    hal_ops->set_sram_mode = ssv6006c_set_sram_mode;
+    hal_ops->enable_usb_acc = ssv6006c_enable_usb_acc;
+    hal_ops->disable_usb_acc = ssv6006c_disable_usb_acc;
+    hal_ops->set_usb_lpm = ssv6006c_set_usb_lpm;
+    hal_ops->jump_to_rom = ssv6006c_jump_to_rom;
+    hal_ops->init_gpio_cfg = ssv6006c_init_gpio_cfg;
+    hal_ops->cmd_efuse = ssv6006c_cmd_efuse;
+    hal_ops->update_product_hw_setting = ssv6006c_update_product_hw_setting;
+    hal_ops->set_on3_enable = ssv6006c_set_on3_enable;
+    hal_ops->wait_usb_rom_ready = ssv6006c_wait_usb_rom_ready;
+    hal_ops->detach_usb_hci = ssv6006c_detach_usb_hci;
+    hal_ops->pll_chk = ssv6006c_pll_chk;
+}
+static int ssv_hwif_read_reg (struct ssv_softc *sc, u32 addr, u32 *val)
+{
+    struct ssv6xxx_platform_data *priv = sc->dev->platform_data;
+    return priv->ops->readreg(sc->dev, addr, val);
+}
+static u64 _ssv6006_get_ic_time_tag(struct ssv_softc *sc)
+{
+    u32 regval;
+    u64 ic_time_tag;
+    ssv_hwif_read_reg(sc, ADR_CHIP_DATE_YYYYMMDD, &regval);
+    ic_time_tag = ((u64)regval<<32);
+    ssv_hwif_read_reg(sc, ADR_CHIP_DATE_00HHMMSS, &regval);
+    ic_time_tag |= (regval);
+    return ic_time_tag;
+}
+void ssv_attach_ssv6006(struct ssv_softc *sc, struct ssv_hal_ops *hal_ops)
+{
+    u32 regval, chip_type;
+    char fpga_tag[5];
+    u64 ic_time_tag;
+    struct ssv6xxx_platform_data *priv = sc->dev->platform_data;
+    ssv_hwif_read_reg(sc, ADR_CHIP_INFO_FPGATAG, &regval);
+    *((u32 *)&fpga_tag[0])= __be32_to_cpu(regval);
+    fpga_tag[4] = 0x0;
+    ic_time_tag = _ssv6006_get_ic_time_tag(sc);
+    dev_dbg(sc->dev, "Load SSV6006 common code\n");
+    ssv_attach_ssv6006_common(hal_ops);
+    if (strstr(priv->chip_id, SSV6006C)
+        || strstr(priv->chip_id, SSV6006D)) {
+        ssv_attach_ssv6006c_mac(hal_ops);
+        dev_dbg(sc->dev, "Load SSV6006C/D HAL MAC function \n");
+    }
+#ifdef SSV_SUPPORT_SSV6006AB
+    else {
+        ssv_attach_ssv6006_mac(hal_ops);
+        dev_dbg(sc->dev, "Load SSV6006 HAL MAC function \n");
+    }
+#endif
+    ssv_hwif_read_reg(sc, ADR_CHIP_TYPE_VER, &regval);
+    chip_type = regval >>24;
+    dev_dbg(sc->dev, "Chip type %x\n", chip_type);
+    if (chip_type == CHIP_TYPE_CHIP) {
+        dev_dbg(sc->dev, "Load SSV6006 HAL common PHY function \n");
+        ssv_attach_ssv6006_phy(hal_ops);
+        if (strstr(priv->chip_id, SSV6006C)
+            || strstr(priv->chip_id, SSV6006D)) {
+            dev_dbg(sc->dev, "Load SSV6006C/D HAL BB-RF function \n");
+            ssv_attach_ssv6006_turismoC_BBRF(hal_ops);
+#ifdef SSV_SUPPORT_SSV6006AB
+        } else {
+            dev_dbg(sc->dev, "Load SSV6006 HAL shuttle BB-RF function \n");
+            ssv_attach_ssv6006_turismoB_BBRF(hal_ops);
+#endif
+        }
+    }
+#ifdef SSV_SUPPORT_SSV6006AB
+    else {
+        if (strstr(&fpga_tag[0], FPGA_PHY_5)) {
+            dev_dbg(sc->dev, "Load SSV6006 HAL common PHY function \n");
+            ssv_attach_ssv6006_phy(hal_ops);
+            ssv_hwif_read_reg(sc, ADR_GEMINA_TRX_VER, &regval);
+            if (regval == RF_GEMINA) {
+                dev_dbg(sc->dev, "Load SSV6006 HAL GeminiA BB-RF function \n");
+                ssv_attach_ssv6006_geminiA_BBRF(hal_ops);
+#ifdef SSV_SUPPORT_TURISMOA
+            } else {
+                ssv_hwif_read_reg(sc, ADR_GEMINA_TRX_VER, &regval);
+                if (regval == RF_TURISMOA) {
+                    dev_dbg(sc->dev, "Load SSV6006 HAL TurismoA BB-RF function \n");
+                    ssv_attach_ssv6006_turismoA_BBRF(hal_ops);
+                }
+#endif
+            }
+#ifdef SSV6006_SUPPORT_CABRIOA
+        } else if (ic_time_tag == FPGA_PHY_4) {
+            dev_dbg(sc->dev, "Load SSV6006 HAL common PHY function \n");
+            ssv_attach_ssv6006_phy(hal_ops);
+            dev_dbg(sc->dev, "Load SSV6006 HAL CabrioA BB-RF function \n");
+            ssv_attach_ssv6006_cabrioA_BBRF(hal_ops);
+#endif
+        }
+    }
+#endif
+}
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/ssv6006C_reg.h b/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/ssv6006C_reg.h
new file mode 100644
index 000000000..771ff379c
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/ssv6006C_reg.h
@@ -0,0 +1,17989 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define FBUS_DMAC_REG_BASE 0x40000000
+#define SBUS_DMAC_REG_BASE 0x50000000
+#define I2S_TRX_REG_BASE 0x60000000
+#define I2CMST_REG_BASE 0x60000400
+#define SPIMST_REG_BASE 0x60000800
+#define SYS_REG_BASE 0xc0000000
+#define CSR_ALLON_BASE 0xc0000100
+#define TU0_US_REG_BASE 0xc0000200
+#define TU1_US_REG_BASE 0xc0000210
+#define TU2_US_REG_BASE 0xc0000220
+#define TU3_US_REG_BASE 0xc0000230
+#define TM0_MS_REG_BASE 0xc0000240
+#define TM1_MS_REG_BASE 0xc0000250
+#define TM2_MS_REG_BASE 0xc0000260
+#define TM3_MS_REG_BASE 0xc0000270
+#define MCU_WDT_REG_BASE 0xc0000280
+#define SYS_WDT_REG_BASE 0xc0000284
+#define PWM_REG_BASE 0xc00002c0
+#define IO_REG_BASE 0xc0000500
+#define CSR_I2C_SLV_BASE 0xc0000600
+#define SD_REG_BASE 0xc0000800
+#define SPI_REG_BASE 0xc0000a00
+#define CSR_I2C_MST_BASE 0xc0000b00
+#define UART_REG_BASE 0xc0000c00
+#define DAT_UART_REG_BASE 0xc0000d00
+#define FLASH_SPI_REG_BASE 0xc0001000
+#define DMA_REG_BASE 0xc0001c00
+#define D2_DMA_REG_BASE 0xc0001e00
+#define INT_CTRL_REG_BASE 0xc0002000
+#define SYS_UTILS_BASE 0xc0003000
+#define RTC_MISC_REG_BASE 0xc0004000
+#define HCI_REG_BASE 0xc1000000
+#define CO_REG_BASE 0xc2000000
+#define EFS_REG_BASE 0xc2000100
+#define CSR_SPIMAS_BASE 0xc3000000
+#define SPIMAS_TX_BUF_BASE 0xc3000100
+#define SPIMAS_RX_BUF_BASE 0xc3000200
+#define MRX_REG_BASE 0xc6000000
+#define AMPDU_REG_BASE 0xc6001000
+#define MT_REG_CSR_BASE 0xc6002000
+#define TXQ0_MT_Q_REG_CSR_BASE 0xc6002100
+#define TXQ1_MT_Q_REG_CSR_BASE 0xc6002200
+#define TXQ2_MT_Q_REG_CSR_BASE 0xc6002300
+#define TXQ3_MT_Q_REG_CSR_BASE 0xc6002400
+#define TXQ4_MT_Q_REG_CSR_BASE 0xc6002500
+#define TXQ5_MT_Q_REG_CSR_BASE 0xc6002600
+#define MT_RESPFRM_REG_BASE 0xc6003000
+#define HIF_INFO_BASE 0xca000000
+#define PHY_RATE_INFO_BASE 0xca000200
+#define MAC_GLB_SET_BASE 0xca000300
+#define BTCX_REG_BASE 0xca000400
+#define MIB_REG_BASE 0xca000800
+#define WSID_EXT_BASE 0xca010000
+#define RF_REG_BASE 0xcb000000
+#define CSR_TU_RF_BASE 0xccb0a000
+#define CSR_TU_PMU_BASE 0xccb0b000
+#define CSR_TU_PHY_BASE 0xccb0e000
+#define MB_REG_BASE 0xcd000000
+#define ID_MNG_REG_BASE 0xcd010000
+#define MMU_REG_BASE 0xcf000000
+#define CSR_TEMP_REG_BASE 0xcfff0000
+#define FBUS_DMAC_REG_BANK_SIZE 0x000003a4
+#define SBUS_DMAC_REG_BANK_SIZE 0x000003a4
+#define I2S_TRX_REG_BANK_SIZE 0x000001cc
+#define I2CMST_REG_BANK_SIZE 0x00000070
+#define SPIMST_REG_BANK_SIZE 0x000000f4
+#define SYS_REG_BANK_SIZE 0x00000100
+#define CSR_ALLON_BANK_SIZE 0x00000044
+#define TU0_US_REG_BANK_SIZE 0x0000000c
+#define TU1_US_REG_BANK_SIZE 0x0000000c
+#define TU2_US_REG_BANK_SIZE 0x0000000c
+#define TU3_US_REG_BANK_SIZE 0x0000000c
+#define TM0_MS_REG_BANK_SIZE 0x0000000c
+#define TM1_MS_REG_BANK_SIZE 0x0000000c
+#define TM2_MS_REG_BANK_SIZE 0x0000000c
+#define TM3_MS_REG_BANK_SIZE 0x0000000c
+#define MCU_WDT_REG_BANK_SIZE 0x00000004
+#define SYS_WDT_REG_BANK_SIZE 0x00000004
+#define PWM_REG_BANK_SIZE 0x00000028
+#define IO_REG_BANK_SIZE 0x00000040
+#define CSR_I2C_SLV_BANK_SIZE 0x00000014
+#define SD_REG_BANK_SIZE 0x00000180
+#define SPI_REG_BANK_SIZE 0x00000020
+#define CSR_I2C_MST_BANK_SIZE 0x00000050
+#define UART_REG_BANK_SIZE 0x00000034
+#define DAT_UART_REG_BANK_SIZE 0x00000060
+#define FLASH_SPI_REG_BANK_SIZE 0x00000034
+#define DMA_REG_BANK_SIZE 0x00000014
+#define D2_DMA_REG_BANK_SIZE 0x00000014
+#define INT_CTRL_REG_BANK_SIZE 0x000000f8
+#define SYS_UTILS_BANK_SIZE 0x00000070
+#define RTC_MISC_REG_BANK_SIZE 0x00000008
+#define HCI_REG_BANK_SIZE 0x0000016c
+#define CO_REG_BANK_SIZE 0x000000ac
+#define EFS_REG_BANK_SIZE 0x00000040
+#define CSR_SPIMAS_BANK_SIZE 0x00000020
+#define SPIMAS_TX_BUF_BANK_SIZE 0x00000020
+#define SPIMAS_RX_BUF_BANK_SIZE 0x00000020
+#define MRX_REG_BANK_SIZE 0x000001b4
+#define AMPDU_REG_BANK_SIZE 0x00000014
+#define MT_REG_CSR_BANK_SIZE 0x00000100
+#define TXQ0_MT_Q_REG_CSR_BANK_SIZE 0x00000014
+#define TXQ1_MT_Q_REG_CSR_BANK_SIZE 0x00000014
+#define TXQ2_MT_Q_REG_CSR_BANK_SIZE 0x00000014
+#define TXQ3_MT_Q_REG_CSR_BANK_SIZE 0x00000014
+#define TXQ4_MT_Q_REG_CSR_BANK_SIZE 0x00000014
+#define TXQ5_MT_Q_REG_CSR_BANK_SIZE 0x00000014
+#define MT_RESPFRM_REG_BANK_SIZE 0x00000140
+#define HIF_INFO_BANK_SIZE 0x0000009c
+#define PHY_RATE_INFO_BANK_SIZE 0x00000004
+#define MAC_GLB_SET_BANK_SIZE 0x00000054
+#define BTCX_REG_BANK_SIZE 0x00000014
+#define MIB_REG_BANK_SIZE 0x00000480
+#define WSID_EXT_BANK_SIZE 0x000001dc
+#define RF_REG_BANK_SIZE 0x00c0b100
+#define CSR_TU_RF_BANK_SIZE 0x00001000
+#define CSR_TU_PMU_BANK_SIZE 0x00000100
+#define CSR_TU_PHY_BANK_SIZE 0x00001434
+#define MB_REG_BANK_SIZE 0x000000a0
+#define ID_MNG_REG_BANK_SIZE 0x00000084
+#define MMU_REG_BANK_SIZE 0x0000003c
+#define CSR_TEMP_REG_BANK_SIZE 0x00000034
+#define ADR_FBUS_SAR0 (FBUS_DMAC_REG_BASE+0x00000000)
+#define ADR_FBUS_DAR0 (FBUS_DMAC_REG_BASE+0x00000008)
+#define ADR_FBUS_CTL0_1 (FBUS_DMAC_REG_BASE+0x00000018)
+#define ADR_FBUS_CTL0_2 (FBUS_DMAC_REG_BASE+0x0000001c)
+#define ADR_FBUS_CFG0_1 (FBUS_DMAC_REG_BASE+0x00000040)
+#define ADR_FBUS_CFG0_2 (FBUS_DMAC_REG_BASE+0x00000044)
+#define ADR_FBUS_SAR1 (FBUS_DMAC_REG_BASE+0x00000058)
+#define ADR_FBUS_DAR1 (FBUS_DMAC_REG_BASE+0x00000060)
+#define ADR_FBUS_CTL1_1 (FBUS_DMAC_REG_BASE+0x00000070)
+#define ADR_FBUS_CTL1_2 (FBUS_DMAC_REG_BASE+0x00000074)
+#define ADR_FBUS_CFG1_1 (FBUS_DMAC_REG_BASE+0x00000098)
+#define ADR_FBUS_CFG1_2 (FBUS_DMAC_REG_BASE+0x0000009c)
+#define ADR_FBUS_RAWTR (FBUS_DMAC_REG_BASE+0x000002c0)
+#define ADR_FBUS_RAWERR (FBUS_DMAC_REG_BASE+0x000002e0)
+#define ADR_FBUS_STATUSTR (FBUS_DMAC_REG_BASE+0x000002e8)
+#define ADR_FBUS_STATUSERR (FBUS_DMAC_REG_BASE+0x00000308)
+#define ADR_FBUS_MASKTR (FBUS_DMAC_REG_BASE+0x00000310)
+#define ADR_FBUS_MASKERR (FBUS_DMAC_REG_BASE+0x00000330)
+#define ADR_FBUS_CLRTR (FBUS_DMAC_REG_BASE+0x00000338)
+#define ADR_FBUS_CLRERR (FBUS_DMAC_REG_BASE+0x00000358)
+#define ADR_FBUS_SHS_SRC_REQ_CFG (FBUS_DMAC_REG_BASE+0x00000368)
+#define ADR_FBUS_SHS_DST_REQ_CFG (FBUS_DMAC_REG_BASE+0x00000370)
+#define ADR_FBUS_SHS_SRC_SREQ_CFG (FBUS_DMAC_REG_BASE+0x00000378)
+#define ADR_FBUS_SHS_DST_SREQ_CFG (FBUS_DMAC_REG_BASE+0x00000380)
+#define ADR_FBUS_DMA_EN (FBUS_DMAC_REG_BASE+0x00000398)
+#define ADR_FBUS_CH_EN (FBUS_DMAC_REG_BASE+0x000003a0)
+#define ADR_SBUS_SAR0 (SBUS_DMAC_REG_BASE+0x00000000)
+#define ADR_SBUS_DAR0 (SBUS_DMAC_REG_BASE+0x00000008)
+#define ADR_SBUS_CTL0_1 (SBUS_DMAC_REG_BASE+0x00000018)
+#define ADR_SBUS_CTL0_2 (SBUS_DMAC_REG_BASE+0x0000001c)
+#define ADR_SBUS_CFG0_1 (SBUS_DMAC_REG_BASE+0x00000040)
+#define ADR_SBUS_CFG0_2 (SBUS_DMAC_REG_BASE+0x00000044)
+#define ADR_SBUS_SAR1 (SBUS_DMAC_REG_BASE+0x00000058)
+#define ADR_SBUS_DAR1 (SBUS_DMAC_REG_BASE+0x00000060)
+#define ADR_SBUS_CTL1_1 (SBUS_DMAC_REG_BASE+0x00000070)
+#define ADR_SBUS_CTL1_2 (SBUS_DMAC_REG_BASE+0x00000074)
+#define ADR_SBUS_CFG1_1 (SBUS_DMAC_REG_BASE+0x00000098)
+#define ADR_SBUS_CFG1_2 (SBUS_DMAC_REG_BASE+0x0000009c)
+#define ADR_SBUS_RAWTR (SBUS_DMAC_REG_BASE+0x000002c0)
+#define ADR_SBUS_RAWERR (SBUS_DMAC_REG_BASE+0x000002e0)
+#define ADR_SBUS_STATUSTR (SBUS_DMAC_REG_BASE+0x000002e8)
+#define ADR_SBUS_STATUSERR (SBUS_DMAC_REG_BASE+0x00000308)
+#define ADR_SBUS_MASKTR (SBUS_DMAC_REG_BASE+0x00000310)
+#define ADR_SBUS_MASKERR (SBUS_DMAC_REG_BASE+0x00000330)
+#define ADR_SBUS_CLRTR (SBUS_DMAC_REG_BASE+0x00000338)
+#define ADR_SBUS_CLRERR (SBUS_DMAC_REG_BASE+0x00000358)
+#define ADR_SBUS_SHS_SRC_REQ_CFG (SBUS_DMAC_REG_BASE+0x00000368)
+#define ADR_SBUS_SHS_DST_REQ_CFG (SBUS_DMAC_REG_BASE+0x00000370)
+#define ADR_SBUS_SHS_SRC_SREQ_CFG (SBUS_DMAC_REG_BASE+0x00000378)
+#define ADR_SBUS_SHS_DST_SREQ_CFG (SBUS_DMAC_REG_BASE+0x00000380)
+#define ADR_SBUS_DMA_EN (SBUS_DMAC_REG_BASE+0x00000398)
+#define ADR_SBUS_CH_EN (SBUS_DMAC_REG_BASE+0x000003a0)
+#define ADR_I2S_EN (I2S_TRX_REG_BASE+0x00000000)
+#define ADR_I2S_RX_EN (I2S_TRX_REG_BASE+0x00000004)
+#define ADR_I2S_TX_EN (I2S_TRX_REG_BASE+0x00000008)
+#define ADR_I2S_SCLK_SCR_EN (I2S_TRX_REG_BASE+0x0000000c)
+#define ADR_I2S_WS_DEF (I2S_TRX_REG_BASE+0x00000010)
+#define ADR_RESET_RX_FIFO (I2S_TRX_REG_BASE+0x00000014)
+#define ADR_RESET_TX_FIFO (I2S_TRX_REG_BASE+0x00000018)
+#define ADR_L_TRX_DATA (I2S_TRX_REG_BASE+0x00000020)
+#define ADR_R_TRX_DATA (I2S_TRX_REG_BASE+0x00000024)
+#define ADR_I2S_RX_CH_EN (I2S_TRX_REG_BASE+0x00000028)
+#define ADR_I2S_TX_CH_EN (I2S_TRX_REG_BASE+0x0000002c)
+#define ADR_I2S_RX_WORD_RES (I2S_TRX_REG_BASE+0x00000030)
+#define ADR_I2S_TX_WORD_RES (I2S_TRX_REG_BASE+0x00000034)
+#define ADR_I2S_INTR (I2S_TRX_REG_BASE+0x00000038)
+#define ADR_I2S_INTR_MASK (I2S_TRX_REG_BASE+0x0000003c)
+#define ADR_I2S_RXFO (I2S_TRX_REG_BASE+0x00000040)
+#define ADR_I2S_TXFO (I2S_TRX_REG_BASE+0x00000044)
+#define ADR_I2S_RX_FIFO_TH (I2S_TRX_REG_BASE+0x00000048)
+#define ADR_I2S_TX_FIFO_TH (I2S_TRX_REG_BASE+0x0000004c)
+#define ADR_I2S_RX_FIFO_FLUSH (I2S_TRX_REG_BASE+0x00000050)
+#define ADR_I2S_TX_FIFO_FLUSH (I2S_TRX_REG_BASE+0x00000054)
+#define ADR_I2S_RX_DMA (I2S_TRX_REG_BASE+0x000001c0)
+#define ADR_I2S_TX_DMA (I2S_TRX_REG_BASE+0x000001c8)
+#define ADR_I2CMST_CFG0 (I2CMST_REG_BASE+0x00000000)
+#define ADR_I2CMST_TAR (I2CMST_REG_BASE+0x00000004)
+#define ADR_I2CMST_TRX_CMD_DATA (I2CMST_REG_BASE+0x00000010)
+#define ADR_I2CMST_SCLK_H_WIDTH (I2CMST_REG_BASE+0x00000014)
+#define ADR_I2CMST_SCLK_L_WIDTH (I2CMST_REG_BASE+0x00000018)
+#define ADR_I2CMST_INT (I2CMST_REG_BASE+0x0000002c)
+#define ADR_I2CMST_INT_MASK (I2CMST_REG_BASE+0x00000030)
+#define ADR_I2CMST_INT_STA (I2CMST_REG_BASE+0x00000034)
+#define ADR_I2CMST_RX_FIFO_TH (I2CMST_REG_BASE+0x00000038)
+#define ADR_I2CMST_TX_FIFO_TH (I2CMST_REG_BASE+0x0000003c)
+#define ADR_I2CMST_ENABLE (I2CMST_REG_BASE+0x0000006c)
+#define ADR_SPIMST_CFG0 (SPIMST_REG_BASE+0x00000000)
+#define ADR_SPIMST_CFG1 (SPIMST_REG_BASE+0x00000004)
+#define ADR_SPIMST_EN (SPIMST_REG_BASE+0x00000008)
+#define ADR_SPIMST_CEN (SPIMST_REG_BASE+0x00000010)
+#define ADR_SPIMST_SCLK_RATE (SPIMST_REG_BASE+0x00000014)
+#define ADR_SPIMST_TXFIFO_TH (SPIMST_REG_BASE+0x00000018)
+#define ADR_SPIMST_RXFIFO_TH (SPIMST_REG_BASE+0x0000001c)
+#define ADR_SPIMST_STATUS (SPIMST_REG_BASE+0x00000028)
+#define ADR_SPIMST_INT_MASK (SPIMST_REG_BASE+0x0000002c)
+#define ADR_SPIMST_INT (SPIMST_REG_BASE+0x00000030)
+#define ADR_SPIMST_TRX_DATA (SPIMST_REG_BASE+0x00000060)
+#define ADR_SPIMST_RX_SAMPLE_DLY (SPIMST_REG_BASE+0x000000f0)
+#define ADR_BRG_SW_RST (SYS_REG_BASE+0x00000000)
+#define ADR_BOOT (SYS_REG_BASE+0x00000004)
+#define ADR_CHIP_ID_0 (SYS_REG_BASE+0x00000008)
+#define ADR_CHIP_ID_1 (SYS_REG_BASE+0x0000000c)
+#define ADR_CHIP_ID_2 (SYS_REG_BASE+0x00000010)
+#define ADR_CHIP_ID_3 (SYS_REG_BASE+0x00000014)
+#define ADR_CLOCK_SELECTION (SYS_REG_BASE+0x00000018)
+#define ADR_PLATFORM_CLOCK_ENABLE (SYS_REG_BASE+0x0000001c)
+#define ADR_SYS_CSR_CLOCK_ENABLE (SYS_REG_BASE+0x00000020)
+#define ADR_BOOTSTRAP_SAMPLE (SYS_REG_BASE+0x00000024)
+#define ADR_N10_DBG1 (SYS_REG_BASE+0x00000028)
+#define ADR_N10_DBG2 (SYS_REG_BASE+0x0000002c)
+#define ADR_ROPMUSTATE (SYS_REG_BASE+0x00000030)
+#define ADR_ROM_READ_PROT (SYS_REG_BASE+0x00000034)
+#define ADR_GPIO_IQ_LOG_STOP (SYS_REG_BASE+0x00000038)
+#define ADR_TB_ADR_SEL (SYS_REG_BASE+0x00000044)
+#define ADR_TB_RDATA (SYS_REG_BASE+0x00000048)
+#define ADR_UART_W2B (SYS_REG_BASE+0x0000004c)
+#define ADR_SYSCTRL_COMMAND (SYS_REG_BASE+0x00000054)
+#define ADR_FBUS_CLK_SEL (SYS_REG_BASE+0x00000058)
+#define ADR_SYSCTRL_STATUS (SYS_REG_BASE+0x0000005c)
+#define ADR_I2SMAS_CFG (SYS_REG_BASE+0x0000006c)
+#define ADR_HBUSREQ_LOCK (SYS_REG_BASE+0x00000090)
+#define ADR_HBURST_LOCK (SYS_REG_BASE+0x00000094)
+#define ADR_FENCE_CTRL (SYS_REG_BASE+0x00000098)
+#define ADR_FENCE_STATUS (SYS_REG_BASE+0x0000009c)
+#define ADR_POWER_SW_INFO (SYS_REG_BASE+0x000000a0)
+#define ADR_VIAROM_EMA (SYS_REG_BASE+0x000000a4)
+#define ADR_TEST_MODE (SYS_REG_BASE+0x000000b0)
+#define ADR_MANUAL_RESET_N (SYS_REG_BASE+0x000000b4)
+#define ADR_DEBUG_FIRMWARE_EVENT_FLAG (SYS_REG_BASE+0x000000b8)
+#define ADR_DEBUG_HOST_EVENT_FLAG (SYS_REG_BASE+0x000000bc)
+#define ADR_CHIP_INFO_ID_0 (SYS_REG_BASE+0x000000c0)
+#define ADR_CHIP_INFO_ID_1 (SYS_REG_BASE+0x000000c4)
+#define ADR_CHIP_TYPE_VER (SYS_REG_BASE+0x000000c8)
+#define ADR_CHIP_DATE_YYYYMMDD (SYS_REG_BASE+0x000000cc)
+#define ADR_CHIP_DATE_00HHMMSS (SYS_REG_BASE+0x000000d0)
+#define ADR_CHIP_GITSHA_0 (SYS_REG_BASE+0x000000d4)
+#define ADR_CHIP_GITSHA_1 (SYS_REG_BASE+0x000000d8)
+#define ADR_CHIP_GITSHA_2 (SYS_REG_BASE+0x000000dc)
+#define ADR_CHIP_GITSHA_3 (SYS_REG_BASE+0x000000e0)
+#define ADR_CHIP_GITSHA_4 (SYS_REG_BASE+0x000000e4)
+#define ADR_N10CFG_DEF_IVB (SYS_REG_BASE+0x000000e8)
+#define ADR_N10CFG_SETTING (SYS_REG_BASE+0x000000ec)
+#define ADR_USB20_HOST_SEL (SYS_REG_BASE+0x000000f0)
+#define ADR_CHIP_INFO_FPGATAG (SYS_REG_BASE+0x000000f4)
+#define ADR_PMU_MODE_TRAN_INT (SYS_REG_BASE+0x000000f8)
+#define ADR_DEBUG_SIM_FINISH (SYS_REG_BASE+0x000000fc)
+#define ADR_ALWAYS_ON_CFG00 (CSR_ALLON_BASE+0x00000000)
+#define ADR_SDIO_RESET_WAKE_CFG (CSR_ALLON_BASE+0x00000004)
+#define ADR_BOOT_INFO (CSR_ALLON_BASE+0x00000008)
+#define ADR_SPARE_UART_INFO (CSR_ALLON_BASE+0x0000000c)
+#define ADR_POWER_ON_OFF_CTRL (CSR_ALLON_BASE+0x00000010)
+#define ADR_HOST_WAKE_WIFI_CTRL (CSR_ALLON_BASE+0x00000014)
+#define ADR_PRESCALER_USTIMER (CSR_ALLON_BASE+0x00000018)
+#define ADR_DESIGN_FOR_TEST_ASSERTION (CSR_ALLON_BASE+0x0000001c)
+#define ADR_WAKE_PMU_ENABLE (CSR_ALLON_BASE+0x00000020)
+#define ADR_SRAMCFG_SETTING (CSR_ALLON_BASE+0x00000028)
+#define ADR_ROM_PATCH00_0 (CSR_ALLON_BASE+0x00000030)
+#define ADR_ROM_PATCH00_1 (CSR_ALLON_BASE+0x00000034)
+#define ADR_ROM_PATCH01_0 (CSR_ALLON_BASE+0x00000038)
+#define ADR_ROM_PATCH01_1 (CSR_ALLON_BASE+0x0000003c)
+#define ADR_DESIGN_FOR_TEST (CSR_ALLON_BASE+0x00000040)
+#define ADR_TU0_MICROSECOND_TIMER (TU0_US_REG_BASE+0x00000000)
+#define ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE (TU0_US_REG_BASE+0x00000004)
+#define ADR_TU0_MICROSECOND_TIMER_LOCAL_PRESCALE (TU0_US_REG_BASE+0x00000008)
+#define ADR_TU1_MICROSECOND_TIMER (TU1_US_REG_BASE+0x00000000)
+#define ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE (TU1_US_REG_BASE+0x00000004)
+#define ADR_TU1_MICROSECOND_TIMER_LOCAL_PRESCALE (TU1_US_REG_BASE+0x00000008)
+#define ADR_TU2_MICROSECOND_TIMER (TU2_US_REG_BASE+0x00000000)
+#define ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE (TU2_US_REG_BASE+0x00000004)
+#define ADR_TU2_MICROSECOND_TIMER_LOCAL_PRESCALE (TU2_US_REG_BASE+0x00000008)
+#define ADR_TU3_MICROSECOND_TIMER (TU3_US_REG_BASE+0x00000000)
+#define ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE (TU3_US_REG_BASE+0x00000004)
+#define ADR_TU3_MICROSECOND_TIMER_LOCAL_PRESCALE (TU3_US_REG_BASE+0x00000008)
+#define ADR_TM0_MILLISECOND_TIMER (TM0_MS_REG_BASE+0x00000000)
+#define ADR_TM0_CURRENT_MILLISECOND_TIME_VALUE (TM0_MS_REG_BASE+0x00000004)
+#define ADR_TM0_MILLISECOND_TIMER_PRESCALE (TM0_MS_REG_BASE+0x00000008)
+#define ADR_TM1_MILLISECOND_TIMER (TM1_MS_REG_BASE+0x00000000)
+#define ADR_TM1_CURRENT_MILLISECOND_TIME_VALUE (TM1_MS_REG_BASE+0x00000004)
+#define ADR_TM1_MILLISECOND_TIMER_PRESCALE (TM1_MS_REG_BASE+0x00000008)
+#define ADR_TM2_MILLISECOND_TIMER (TM2_MS_REG_BASE+0x00000000)
+#define ADR_TM2_CURRENT_MILLISECOND_TIME_VALUE (TM2_MS_REG_BASE+0x00000004)
+#define ADR_TM2_MILLISECOND_TIMER_PRESCALE (TM2_MS_REG_BASE+0x00000008)
+#define ADR_TM3_MILLISECOND_TIMER (TM3_MS_REG_BASE+0x00000000)
+#define ADR_TM3_CURRENT_MILLISECOND_TIME_VALUE (TM3_MS_REG_BASE+0x00000004)
+#define ADR_TM3_MILLISECOND_TIMER_PRESCALE (TM3_MS_REG_BASE+0x00000008)
+#define ADR_MCU_WDOG_REG (MCU_WDT_REG_BASE+0x00000000)
+#define ADR_SYS_WDOG_REG (SYS_WDT_REG_BASE+0x00000000)
+#define ADR_PWM_0_CTRL (PWM_REG_BASE+0x00000000)
+#define ADR_PWM_0_SET (PWM_REG_BASE+0x00000004)
+#define ADR_PWM_1_CTRL (PWM_REG_BASE+0x00000008)
+#define ADR_PWM_1_SET (PWM_REG_BASE+0x0000000c)
+#define ADR_PWM_2_CTRL (PWM_REG_BASE+0x00000010)
+#define ADR_PWM_2_SET (PWM_REG_BASE+0x00000014)
+#define ADR_PWM_3_CTRL (PWM_REG_BASE+0x00000018)
+#define ADR_PWM_3_SET (PWM_REG_BASE+0x0000001c)
+#define ADR_PWM_4_CTRL (PWM_REG_BASE+0x00000020)
+#define ADR_PWM_4_SET (PWM_REG_BASE+0x00000024)
+#define ADR_MANUAL_IO (IO_REG_BASE+0x00000000)
+#define ADR_MANUAL_PU (IO_REG_BASE+0x00000004)
+#define ADR_MANUAL_PD (IO_REG_BASE+0x00000008)
+#define ADR_MANUAL_DS (IO_REG_BASE+0x0000000c)
+#define ADR_IO_PO (IO_REG_BASE+0x00000010)
+#define ADR_IO_PI (IO_REG_BASE+0x00000014)
+#define ADR_IO_PIE (IO_REG_BASE+0x00000018)
+#define ADR_IO_POEN (IO_REG_BASE+0x0000001c)
+#define ADR_IO_PUE (IO_REG_BASE+0x00000020)
+#define ADR_IO_PDE (IO_REG_BASE+0x00000024)
+#define ADR_IO_DS (IO_REG_BASE+0x00000028)
+#define ADR_IO_FUNC_SEL (IO_REG_BASE+0x0000002c)
+#define ADR_INT_THRU_GPIO (IO_REG_BASE+0x00000030)
+#define ADR_BIST_CTRL (IO_REG_BASE+0x00000034)
+#define ADR_BIST_CTRL1 (IO_REG_BASE+0x00000038)
+#define ADR_BIST_CTRL2 (IO_REG_BASE+0x0000003c)
+#define ADR_I2CS_ID_ADDR (CSR_I2C_SLV_BASE+0x00000000)
+#define ADR_I2CS_STATUS (CSR_I2C_SLV_BASE+0x00000004)
+#define ADR_I2CS_TIME_CNT (CSR_I2C_SLV_BASE+0x00000008)
+#define ADR_I2CS_STATE (CSR_I2C_SLV_BASE+0x0000000c)
+#define ADR_I2CS_CTRL (CSR_I2C_SLV_BASE+0x00000010)
+#define ADR_IO_PORT_REG (SD_REG_BASE+0x00000000)
+#define ADR_INT_MASK_REG (SD_REG_BASE+0x00000004)
+#define ADR_INT_STATUS_REG (SD_REG_BASE+0x00000008)
+#define ADR_FN1_STATUS_REG (SD_REG_BASE+0x0000000c)
+#define ADR_CARD_RCA_REG (SD_REG_BASE+0x00000020)
+#define ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG (SD_REG_BASE+0x00000040)
+#define ADR_SDIO_CARD_STATUS_REG (SD_REG_BASE+0x00000050)
+#define ADR_R5_RESP_FLAG_OUT_TIMING (SD_REG_BASE+0x00000054)
+#define ADR_SDIO_DELAY_CHAIN_0 (SD_REG_BASE+0x00000058)
+#define ADR_SDIO_DELAY_CHAIN_1 (SD_REG_BASE+0x0000005c)
+#define ADR_FN1_DMA_START_ADDR_REG (SD_REG_BASE+0x00000060)
+#define ADR_FN1_INT_CTRL_RESET (SD_REG_BASE+0x00000064)
+#define ADR_MCU_NOTIFY_HOST_EVENT (SD_REG_BASE+0x00000068)
+#define ADR_FN1_DMA_RD_START_ADDR_REG (SD_REG_BASE+0x0000006c)
+#define ADR_CCCR_00H_REG (SD_REG_BASE+0x000000c0)
+#define ADR_CCCR_04H_REG (SD_REG_BASE+0x000000c4)
+#define ADR_CCCR_08H_REG (SD_REG_BASE+0x000000c8)
+#define ADR_CCCR_14H_REG (SD_REG_BASE+0x000000cc)
+#define ADR_CCCR_13H_REG (SD_REG_BASE+0x000000d0)
+#define ADR_FBR_100H_REG (SD_REG_BASE+0x000000e0)
+#define ADR_FBR_109H_REG (SD_REG_BASE+0x000000e8)
+#define ADR_F0_CIS_CONTENT_REG_0 (SD_REG_BASE+0x00000100)
+#define ADR_F0_CIS_CONTENT_REG_1 (SD_REG_BASE+0x00000104)
+#define ADR_F0_CIS_CONTENT_REG_2 (SD_REG_BASE+0x00000108)
+#define ADR_F0_CIS_CONTENT_REG_3 (SD_REG_BASE+0x0000010c)
+#define ADR_F0_CIS_CONTENT_REG_4 (SD_REG_BASE+0x00000110)
+#define ADR_F0_CIS_CONTENT_REG_5 (SD_REG_BASE+0x00000114)
+#define ADR_F0_CIS_CONTENT_REG_6 (SD_REG_BASE+0x00000118)
+#define ADR_F0_CIS_CONTENT_REG_7 (SD_REG_BASE+0x0000011c)
+#define ADR_F0_CIS_CONTENT_REG_8 (SD_REG_BASE+0x00000120)
+#define ADR_F0_CIS_CONTENT_REG_9 (SD_REG_BASE+0x00000124)
+#define ADR_F0_CIS_CONTENT_REG_10 (SD_REG_BASE+0x00000128)
+#define ADR_F0_CIS_CONTENT_REG_11 (SD_REG_BASE+0x0000012c)
+#define ADR_F0_CIS_CONTENT_REG_12 (SD_REG_BASE+0x00000130)
+#define ADR_F0_CIS_CONTENT_REG_13 (SD_REG_BASE+0x00000134)
+#define ADR_F0_CIS_CONTENT_REG_14 (SD_REG_BASE+0x00000138)
+#define ADR_F0_CIS_CONTENT_REG_15 (SD_REG_BASE+0x0000013c)
+#define ADR_F1_CIS_CONTENT_REG_0 (SD_REG_BASE+0x00000140)
+#define ADR_F1_CIS_CONTENT_REG_1 (SD_REG_BASE+0x00000144)
+#define ADR_F1_CIS_CONTENT_REG_2 (SD_REG_BASE+0x00000148)
+#define ADR_F1_CIS_CONTENT_REG_3 (SD_REG_BASE+0x0000014c)
+#define ADR_F1_CIS_CONTENT_REG_4 (SD_REG_BASE+0x00000150)
+#define ADR_F1_CIS_CONTENT_REG_5 (SD_REG_BASE+0x00000154)
+#define ADR_F1_CIS_CONTENT_REG_6 (SD_REG_BASE+0x00000158)
+#define ADR_F1_CIS_CONTENT_REG_7 (SD_REG_BASE+0x0000015c)
+#define ADR_F1_CIS_CONTENT_REG_8 (SD_REG_BASE+0x00000160)
+#define ADR_F1_CIS_CONTENT_REG_9 (SD_REG_BASE+0x00000164)
+#define ADR_F1_CIS_CONTENT_REG_10 (SD_REG_BASE+0x00000168)
+#define ADR_F1_CIS_CONTENT_REG_11 (SD_REG_BASE+0x0000016c)
+#define ADR_F1_CIS_CONTENT_REG_12 (SD_REG_BASE+0x00000170)
+#define ADR_F1_CIS_CONTENT_REG_13 (SD_REG_BASE+0x00000174)
+#define ADR_F1_CIS_CONTENT_REG_14 (SD_REG_BASE+0x00000178)
+#define ADR_F1_CIS_CONTENT_REG_15 (SD_REG_BASE+0x0000017c)
+#define ADR_SPI_MODE (SPI_REG_BASE+0x00000000)
+#define ADR_TX_SEG (SPI_REG_BASE+0x00000010)
+#define ADR_SPI_TO_PHY_PARAM1 (SPI_REG_BASE+0x00000018)
+#define ADR_SPI_TO_PHY_PARAM2 (SPI_REG_BASE+0x0000001c)
+#define ADR_TWIM_EN (CSR_I2C_MST_BASE+0x00000000)
+#define ADR_TWIM_STATUS_SETTING (CSR_I2C_MST_BASE+0x00000004)
+#define ADR_TWIM_INTERRUPT_EN (CSR_I2C_MST_BASE+0x00000008)
+#define ADR_TWIM_INTERRUPT (CSR_I2C_MST_BASE+0x0000000c)
+#define ADR_TWIM_INTERRUPT_STATUS (CSR_I2C_MST_BASE+0x00000010)
+#define ADR_TWIM_STATUS_RECORD_0 (CSR_I2C_MST_BASE+0x00000014)
+#define ADR_TWIM_STATUS_RECORD_1 (CSR_I2C_MST_BASE+0x00000018)
+#define ADR_TWIM_DEV_A (CSR_I2C_MST_BASE+0x0000001c)
+#define ADR_TWIM_TXD_DATA (CSR_I2C_MST_BASE+0x00000020)
+#define ADR_TWIM_RXD_DATA (CSR_I2C_MST_BASE+0x00000024)
+#define ADR_TWIM_PSCL (CSR_I2C_MST_BASE+0x00000028)
+#define ADR_TWIM_TRANS_PSDA (CSR_I2C_MST_BASE+0x0000002c)
+#define ADR_TWIM_DELAY_ACK (CSR_I2C_MST_BASE+0x00000030)
+#define ADR_I2CM_EN (CSR_I2C_MST_BASE+0x00000034)
+#define ADR_I2CM_DEV_A (CSR_I2C_MST_BASE+0x00000038)
+#define ADR_I2CM_LEN (CSR_I2C_MST_BASE+0x0000003c)
+#define ADR_I2CM_WDAT (CSR_I2C_MST_BASE+0x00000040)
+#define ADR_I2CM_RDAT (CSR_I2C_MST_BASE+0x00000044)
+#define ADR_I2CM_EN_2 (CSR_I2C_MST_BASE+0x00000048)
+#define ADR_I2CM_START_STOP_PERIOD (CSR_I2C_MST_BASE+0x0000004c)
+#define ADR_UART_DATA (UART_REG_BASE+0x00000000)
+#define ADR_UART_IER (UART_REG_BASE+0x00000004)
+#define ADR_UART_FCR (UART_REG_BASE+0x00000008)
+#define ADR_UART_LCR (UART_REG_BASE+0x0000000c)
+#define ADR_UART_MCR (UART_REG_BASE+0x00000010)
+#define ADR_UART_LSR (UART_REG_BASE+0x00000014)
+#define ADR_UART_MSR (UART_REG_BASE+0x00000018)
+#define ADR_UART_SPR (UART_REG_BASE+0x0000001c)
+#define ADR_UART_RTHR (UART_REG_BASE+0x00000020)
+#define ADR_UART_ISR (UART_REG_BASE+0x00000024)
+#define ADR_UART_TTHR (UART_REG_BASE+0x00000028)
+#define ADR_UART_INT_MAP (UART_REG_BASE+0x0000002c)
+#define ADR_UART_POINTER (UART_REG_BASE+0x00000030)
+#define ADR_HSUART_TRX_CHAR (DAT_UART_REG_BASE+0x00000000)
+#define ADR_HSUART_INTRRUPT_ENABLE (DAT_UART_REG_BASE+0x00000004)
+#define ADR_HSUART_FIFO_CTRL (DAT_UART_REG_BASE+0x00000008)
+#define ADR_HSUART_LINE_CTRL (DAT_UART_REG_BASE+0x0000000c)
+#define ADR_HSUART_MODEM_CTRL (DAT_UART_REG_BASE+0x00000010)
+#define ADR_HSUART_LINE_STATUS (DAT_UART_REG_BASE+0x00000014)
+#define ADR_HSUART_MODEM_STATUS (DAT_UART_REG_BASE+0x00000018)
+#define ADR_HSUART_SCRATCH_BOARD (DAT_UART_REG_BASE+0x0000001c)
+#define ADR_HSUART_FIFO_THRESHOLD (DAT_UART_REG_BASE+0x00000020)
+#define ADR_HSUART_INTERRUPT_STATUS (DAT_UART_REG_BASE+0x00000024)
+#define ADR_HSUART_DIV_FRAC (DAT_UART_REG_BASE+0x00000028)
+#define ADR_HSUART_EXPANSION_INTERRUPT_STATUS (DAT_UART_REG_BASE+0x0000002c)
+#define ADR_HSUART_DMA_RX_STR_ADDR (DAT_UART_REG_BASE+0x00000040)
+#define ADR_HSUART_DMA_RX_END_ADDR (DAT_UART_REG_BASE+0x00000044)
+#define ADR_HSUART_DMA_RX_WPT (DAT_UART_REG_BASE+0x00000048)
+#define ADR_HSUART_DMA_RX_RPT (DAT_UART_REG_BASE+0x0000004c)
+#define ADR_HSUART_DMA_TX_STR_ADDR (DAT_UART_REG_BASE+0x00000050)
+#define ADR_HSUART_DMA_TX_END_ADDR (DAT_UART_REG_BASE+0x00000054)
+#define ADR_HSUART_DMA_TX_WPT (DAT_UART_REG_BASE+0x00000058)
+#define ADR_HSUART_DMA_TX_RPT (DAT_UART_REG_BASE+0x0000005c)
+#define ADR_MANUAL_MODE_TX_ADDR (FLASH_SPI_REG_BASE+0x00000000)
+#define ADR_MANUAL_MODE_RX_ADDR (FLASH_SPI_REG_BASE+0x00000004)
+#define ADR_SPI_PARAM (FLASH_SPI_REG_BASE+0x00000008)
+#define ADR_SPI_PARAM2 (FLASH_SPI_REG_BASE+0x0000000c)
+#define ADR_SPI_TX_LEN (FLASH_SPI_REG_BASE+0x00000010)
+#define ADR_SPI_RX_LEN (FLASH_SPI_REG_BASE+0x00000014)
+#define ADR_CMD_SET (FLASH_SPI_REG_BASE+0x00000018)
+#define ADR_CMD_SET_1 (FLASH_SPI_REG_BASE+0x0000001c)
+#define ADR_FLASH_IO0_DLY (FLASH_SPI_REG_BASE+0x00000020)
+#define ADR_FLASH_IO1_DLY (FLASH_SPI_REG_BASE+0x00000024)
+#define ADR_INS_SPACE_START_ADDR (FLASH_SPI_REG_BASE+0x00000028)
+#define ADR_INS_SPACE_END_ADDR (FLASH_SPI_REG_BASE+0x0000002c)
+#define ADR_BUFFER_CLEAR_ERROR_FLAG_CLEAR (FLASH_SPI_REG_BASE+0x00000030)
+#define ADR_DMA_ADR_SRC (DMA_REG_BASE+0x00000000)
+#define ADR_DMA_ADR_DST (DMA_REG_BASE+0x00000004)
+#define ADR_DMA_CTRL (DMA_REG_BASE+0x00000008)
+#define ADR_DMA_INT (DMA_REG_BASE+0x0000000c)
+#define ADR_DMA_FILL_CONST (DMA_REG_BASE+0x00000010)
+#define ADR_D2_DMA_ADR_SRC (D2_DMA_REG_BASE+0x00000000)
+#define ADR_D2_DMA_ADR_DST (D2_DMA_REG_BASE+0x00000004)
+#define ADR_D2_DMA_CTRL (D2_DMA_REG_BASE+0x00000008)
+#define ADR_D2_DMA_INT (D2_DMA_REG_BASE+0x0000000c)
+#define ADR_D2_DMA_FILL_CONST (D2_DMA_REG_BASE+0x00000010)
+#define ADR_MASK_TYPHOST_INT_MAP_02 (INT_CTRL_REG_BASE+0x00000068)
+#define ADR_RAW_TYPHOST_INT_MAP_02 (INT_CTRL_REG_BASE+0x0000006c)
+#define ADR_POSTMASK_TYPHOST_INT_MAP_02 (INT_CTRL_REG_BASE+0x00000070)
+#define ADR_MASK_TYPHOST_INT_MAP_15 (INT_CTRL_REG_BASE+0x00000074)
+#define ADR_RAW_TYPHOST_INT_MAP_15 (INT_CTRL_REG_BASE+0x00000078)
+#define ADR_POSTMASK_TYPHOST_INT_MAP_15 (INT_CTRL_REG_BASE+0x0000007c)
+#define ADR_MASK_TYPHOST_INT_MAP_31 (INT_CTRL_REG_BASE+0x00000080)
+#define ADR_RAW_TYPHOST_INT_MAP_31 (INT_CTRL_REG_BASE+0x00000084)
+#define ADR_POSTMASK_TYPHOST_INT_MAP_31 (INT_CTRL_REG_BASE+0x00000088)
+#define ADR_MASK_TYPHOST_INT_MAP (INT_CTRL_REG_BASE+0x0000008c)
+#define ADR_RAW_TYPHOST_INT_MAP (INT_CTRL_REG_BASE+0x00000090)
+#define ADR_POSTMASK_TYPHOST_INT_MAP (INT_CTRL_REG_BASE+0x00000094)
+#define ADR_SUMMARY_TYPHOST_INT_MAP (INT_CTRL_REG_BASE+0x00000098)
+#define ADR_MASK_TYPMCU_INT_MAP_02 (INT_CTRL_REG_BASE+0x0000009c)
+#define ADR_RAW_TYPMCU_INT_MAP_02 (INT_CTRL_REG_BASE+0x000000a0)
+#define ADR_POSTMASK_TYPMCU_INT_MAP_02 (INT_CTRL_REG_BASE+0x000000a4)
+#define ADR_MASK_TYPMCU_INT_MAP_15 (INT_CTRL_REG_BASE+0x000000a8)
+#define ADR_RAW_TYPMCU_INT_MAP_15 (INT_CTRL_REG_BASE+0x000000ac)
+#define ADR_POSTMASK_TYPMCU_INT_MAP_15 (INT_CTRL_REG_BASE+0x000000b0)
+#define ADR_MASK_TYPMCU_INT_MAP_31 (INT_CTRL_REG_BASE+0x000000b4)
+#define ADR_RAW_TYPMCU_INT_MAP_31 (INT_CTRL_REG_BASE+0x000000b8)
+#define ADR_POSTMASK_TYPMCU_INT_MAP_31 (INT_CTRL_REG_BASE+0x000000bc)
+#define ADR_MASK_TYPMCU_INT_MAP (INT_CTRL_REG_BASE+0x000000c0)
+#define ADR_RAW_TYPMCU_INT_MAP (INT_CTRL_REG_BASE+0x000000c4)
+#define ADR_POSTMASK_TYPMCU_INT_MAP (INT_CTRL_REG_BASE+0x000000c8)
+#define ADR_SUMMARY_TYPMCU_INT_MAP (INT_CTRL_REG_BASE+0x000000cc)
+#define ADR_GPIO_INTERRUPT_BANK_00_TO_07 (INT_CTRL_REG_BASE+0x000000d0)
+#define ADR_GPIO_INTERRUPT_BANK_08_TO_15 (INT_CTRL_REG_BASE+0x000000d4)
+#define ADR_GPIO_INTERRUPT_BANK_16_TO_22 (INT_CTRL_REG_BASE+0x000000d8)
+#define ADR_GPIO_INTERRUPT_MODE_00_TO_07 (INT_CTRL_REG_BASE+0x000000dc)
+#define ADR_GPIO_INTERRUPT_MODE_08_TO_15 (INT_CTRL_REG_BASE+0x000000e0)
+#define ADR_GPIO_INTERRUPT_MODE_16_TO_22 (INT_CTRL_REG_BASE+0x000000e4)
+#define ADR_IPC_INTERRUPT (INT_CTRL_REG_BASE+0x000000e8)
+#define ADR_CLR_INT_STS2 (INT_CTRL_REG_BASE+0x000000ec)
+#define ADR_CLR_INT_STS1 (INT_CTRL_REG_BASE+0x000000f0)
+#define ADR_CLR_INT_STS0 (INT_CTRL_REG_BASE+0x000000f4)
+#define ADR_ROM_PATCH02_0 (SYS_UTILS_BASE+0x00000000)
+#define ADR_ROM_PATCH02_1 (SYS_UTILS_BASE+0x00000004)
+#define ADR_ROM_PATCH03_0 (SYS_UTILS_BASE+0x00000008)
+#define ADR_ROM_PATCH03_1 (SYS_UTILS_BASE+0x0000000c)
+#define ADR_ROM_PATCH04_0 (SYS_UTILS_BASE+0x00000010)
+#define ADR_ROM_PATCH04_1 (SYS_UTILS_BASE+0x00000014)
+#define ADR_ROM_PATCH05_0 (SYS_UTILS_BASE+0x00000018)
+#define ADR_ROM_PATCH05_1 (SYS_UTILS_BASE+0x0000001c)
+#define ADR_ROM_PATCH06_0 (SYS_UTILS_BASE+0x00000020)
+#define ADR_ROM_PATCH06_1 (SYS_UTILS_BASE+0x00000024)
+#define ADR_ROM_PATCH07_0 (SYS_UTILS_BASE+0x00000028)
+#define ADR_ROM_PATCH07_1 (SYS_UTILS_BASE+0x0000002c)
+#define ADR_ROM_PATCH08_0 (SYS_UTILS_BASE+0x00000030)
+#define ADR_ROM_PATCH08_1 (SYS_UTILS_BASE+0x00000034)
+#define ADR_ROM_PATCH09_0 (SYS_UTILS_BASE+0x00000038)
+#define ADR_ROM_PATCH09_1 (SYS_UTILS_BASE+0x0000003c)
+#define ADR_ROM_PATCH10_0 (SYS_UTILS_BASE+0x00000040)
+#define ADR_ROM_PATCH10_1 (SYS_UTILS_BASE+0x00000044)
+#define ADR_ROM_PATCH11_0 (SYS_UTILS_BASE+0x00000048)
+#define ADR_ROM_PATCH11_1 (SYS_UTILS_BASE+0x0000004c)
+#define ADR_ROM_PATCH12_0 (SYS_UTILS_BASE+0x00000050)
+#define ADR_ROM_PATCH12_1 (SYS_UTILS_BASE+0x00000054)
+#define ADR_ROM_PATCH13_0 (SYS_UTILS_BASE+0x00000058)
+#define ADR_ROM_PATCH13_1 (SYS_UTILS_BASE+0x0000005c)
+#define ADR_ROM_PATCH14_0 (SYS_UTILS_BASE+0x00000060)
+#define ADR_ROM_PATCH14_1 (SYS_UTILS_BASE+0x00000064)
+#define ADR_ROM_PATCH15_0 (SYS_UTILS_BASE+0x00000068)
+#define ADR_ROM_PATCH15_1 (SYS_UTILS_BASE+0x0000006c)
+#define ADR_BROWNOUT_INT (RTC_MISC_REG_BASE+0x00000000)
+#define ADR_BROWNOUT_SETUP (RTC_MISC_REG_BASE+0x00000004)
+#define ADR_CONTROL (HCI_REG_BASE+0x00000000)
+#define ADR_HCI_TRX_MODE (HCI_REG_BASE+0x00000004)
+#define ADR_TX_FLOW_0 (HCI_REG_BASE+0x00000008)
+#define ADR_TX_FLOW_1 (HCI_REG_BASE+0x0000000c)
+#define ADR_REMAINING_RX_PACKET_LENGTH (HCI_REG_BASE+0x00000010)
+#define ADR_RX_PACKET_LENGTH_STATUS (HCI_REG_BASE+0x00000014)
+#define ADR_THRESHOLD (HCI_REG_BASE+0x00000018)
+#define ADR_TX_ERROR_RECEOVERY (HCI_REG_BASE+0x0000001c)
+#define ADR_TXFID_INCREASE (HCI_REG_BASE+0x00000020)
+#define ADR_GLOBAL_SEQUENCE (HCI_REG_BASE+0x00000028)
+#define ADR_HCI_REG_0X2C (HCI_REG_BASE+0x0000002c)
+#define ADR_HCI_TX_RX_INFO_SIZE (HCI_REG_BASE+0x00000030)
+#define ADR_HCI_TX_INFO_CLEAR (HCI_REG_BASE+0x00000034)
+#define ADR_HCI_TO_PKTBUF_SETTING (HCI_REG_BASE+0x00000038)
+#define ADR_HCI_MANUAL_ALLOC (HCI_REG_BASE+0x00000040)
+#define ADR_HCI_MANUAL_ALLOC_ACTION (HCI_REG_BASE+0x00000044)
+#define ADR_HCI_MANUAL_ALLOC_STATUS (HCI_REG_BASE+0x00000048)
+#define ADR_TX_ETHER_TYPE_0 (HCI_REG_BASE+0x00000050)
+#define ADR_TX_ETHER_TYPE_1 (HCI_REG_BASE+0x00000054)
+#define ADR_RX_ETHER_TYPE_0 (HCI_REG_BASE+0x00000060)
+#define ADR_RX_ETHER_TYPE_1 (HCI_REG_BASE+0x00000064)
+#define ADR_TX_PACKET_LENGTH (HCI_REG_BASE+0x00000094)
+#define ADR_TX_PACKET_ID (HCI_REG_BASE+0x00000098)
+#define ADR_RX_RESCUE_HELPER (HCI_REG_BASE+0x0000009c)
+#define ADR_HCI_FORCE_PRE_BULK_IN (HCI_REG_BASE+0x000000a0)
+#define ADR_HCI_BULK_IN_TIME_OUT_VALUE (HCI_REG_BASE+0x000000a4)
+#define ADR_HCI_STATE_DEBUG_MODE_0 (HCI_REG_BASE+0x000000a8)
+#define ADR_HCI_STATE_DEBUG_MODE_2 (HCI_REG_BASE+0x000000b0)
+#define ADR_HCI_STATE_DEBUG_MODE_3 (HCI_REG_BASE+0x000000b4)
+#define ADR_HCI_STATE_DEBUG_MODE_4 (HCI_REG_BASE+0x000000b8)
+#define ADR_HCI_STATE_DEBUG_MODE_5 (HCI_REG_BASE+0x000000bc)
+#define ADR_HCI_STATE_DEBUG_MODE_6 (HCI_REG_BASE+0x000000c0)
+#define ADR_HCI_STATE_DEBUG_MODE_7 (HCI_REG_BASE+0x000000c8)
+#define ADR_HCI_TX_ON_DEMAND_LENGTH (HCI_REG_BASE+0x000000cc)
+#define ADR_HCI_TX_ALLOC_SUCCESS_COUNT (HCI_REG_BASE+0x000000d0)
+#define ADR_HCI_TX_ALLOC_SPENDING_TIME (HCI_REG_BASE+0x000000d8)
+#define ADR_RX_TRAP_COUNT (HCI_REG_BASE+0x00000100)
+#define ADR_TX_TRAP_COUNT (HCI_REG_BASE+0x00000108)
+#define ADR_RX_DROP_COUNT (HCI_REG_BASE+0x00000110)
+#define ADR_TX_DROP_COUNT (HCI_REG_BASE+0x00000118)
+#define ADR_RX_HOST_EVENT_COUNT (HCI_REG_BASE+0x00000120)
+#define ADR_TX_HOST_COMMAND_COUNT (HCI_REG_BASE+0x00000128)
+#define ADR_RX_PACKET_COUNTER (HCI_REG_BASE+0x00000130)
+#define ADR_TX_PACKET_COUNTER (HCI_REG_BASE+0x00000138)
+#define ADR_SDIO_RX_FAIL_COUNT (HCI_REG_BASE+0x00000140)
+#define ADR_SDIO_TX_FAIL_COUNT (HCI_REG_BASE+0x00000148)
+#define ADR_CORRECT_RATE_REPORT_LENGTH (HCI_REG_BASE+0x00000150)
+#define ADR_TX_PACKET_SEND_TO_RX_DIRECTLY (HCI_REG_BASE+0x00000154)
+#define ADR_POWER_SAVING_PEER_REJECT_FUNCTION (HCI_REG_BASE+0x00000158)
+#define ADR_TX_RX_TRAP_HW_ID_SELECTION_FUNCTION (HCI_REG_BASE+0x0000015c)
+#define ADR_RX_HCI_EXP_0_CTRL (HCI_REG_BASE+0x00000160)
+#define ADR_RX_HCI_EXP_0_LEN (HCI_REG_BASE+0x00000164)
+#define ADR_FORCE_RX_AGGREGATION_MODE (HCI_REG_BASE+0x00000168)
+#define ADR_CS_START_ADDR (CO_REG_BASE+0x00000000)
+#define ADR_CS_ADD_LEN (CO_REG_BASE+0x00000004)
+#define ADR_CS_CMD (CO_REG_BASE+0x00000008)
+#define ADR_CS_INI_BUF (CO_REG_BASE+0x0000000c)
+#define ADR_CS_PSEUDO_BUF (CO_REG_BASE+0x00000010)
+#define ADR_CS_CHECK_SUM (CO_REG_BASE+0x00000014)
+#define ADR_RAND_EN (CO_REG_BASE+0x00000018)
+#define ADR_RAND_NUM (CO_REG_BASE+0x0000001c)
+#define ADR_MUL_OP1 (CO_REG_BASE+0x00000060)
+#define ADR_MUL_OP2 (CO_REG_BASE+0x00000064)
+#define ADR_MUL_ANS0 (CO_REG_BASE+0x00000068)
+#define ADR_MUL_ANS1 (CO_REG_BASE+0x0000006c)
+#define ADR_DMA_RDATA (CO_REG_BASE+0x00000070)
+#define ADR_DMA_WDATA (CO_REG_BASE+0x00000074)
+#define ADR_DMA_LEN (CO_REG_BASE+0x00000078)
+#define ADR_DMA_CLR (CO_REG_BASE+0x0000007c)
+#define ADR_NAV_DATA (CO_REG_BASE+0x00000080)
+#define ADR_CO_NAV (CO_REG_BASE+0x00000084)
+#define ADR_SHA_DST_ADDR (CO_REG_BASE+0x000000a0)
+#define ADR_SHA_SRC_ADDR (CO_REG_BASE+0x000000a4)
+#define ADR_SHA_SETTING (CO_REG_BASE+0x000000a8)
+#define ADR_EFUSE_CLK_FREQ (EFS_REG_BASE+0x00000000)
+#define ADR_EFUSE_LDO_TIME (EFS_REG_BASE+0x00000004)
+#define ADR_EFUSE_STATUS (EFS_REG_BASE+0x00000008)
+#define ADR_EFUSE_STATUS2 (EFS_REG_BASE+0x0000000c)
+#define ADR_EFUSE_WR_KICK (EFS_REG_BASE+0x00000010)
+#define ADR_EFUSE_RD_KICK (EFS_REG_BASE+0x00000014)
+#define ADR_EFUSE_VDDQ_EN (EFS_REG_BASE+0x00000018)
+#define ADR_EFUSE_WDATA_0_0 (EFS_REG_BASE+0x00000020)
+#define ADR_EFUSE_WDATA_0_1 (EFS_REG_BASE+0x00000024)
+#define ADR_EFUSE_WDATA_0_2 (EFS_REG_BASE+0x00000028)
+#define ADR_EFUSE_WDATA_0_3 (EFS_REG_BASE+0x0000002c)
+#define ADR_EFUSE_WDATA_0_4 (EFS_REG_BASE+0x00000030)
+#define ADR_EFUSE_WDATA_0_5 (EFS_REG_BASE+0x00000034)
+#define ADR_EFUSE_WDATA_0_6 (EFS_REG_BASE+0x00000038)
+#define ADR_EFUSE_WDATA_0_7 (EFS_REG_BASE+0x0000003c)
+#define ADR_SPI_DELAY (CSR_SPIMAS_BASE+0x00000000)
+#define ADR_SPI_CLK_DIV (CSR_SPIMAS_BASE+0x00000004)
+#define ADR_SPI_BUSY (CSR_SPIMAS_BASE+0x00000008)
+#define ADR_SPI_CLR (CSR_SPIMAS_BASE+0x0000000c)
+#define ADR_SPI_MAS_MODE (CSR_SPIMAS_BASE+0x00000010)
+#define ADR_SPI_M_CFG (CSR_SPIMAS_BASE+0x00000014)
+#define ADR_SPI_CFG (CSR_SPIMAS_BASE+0x00000018)
+#define ADR_SPI_MAS_COMMAND_LEN (CSR_SPIMAS_BASE+0x0000001c)
+#define ADR_MRX_MCAST_TB0_0 (MRX_REG_BASE+0x00000000)
+#define ADR_MRX_MCAST_TB0_1 (MRX_REG_BASE+0x00000004)
+#define ADR_MRX_MCAST_MK0_0 (MRX_REG_BASE+0x00000008)
+#define ADR_MRX_MCAST_MK0_1 (MRX_REG_BASE+0x0000000c)
+#define ADR_MRX_MCAST_CTRL0 (MRX_REG_BASE+0x00000010)
+#define ADR_MRX_MCAST_TB1_0 (MRX_REG_BASE+0x00000014)
+#define ADR_MRX_MCAST_TB1_1 (MRX_REG_BASE+0x00000018)
+#define ADR_MRX_MCAST_MK1_0 (MRX_REG_BASE+0x0000001c)
+#define ADR_MRX_MCAST_MK1_1 (MRX_REG_BASE+0x00000020)
+#define ADR_MRX_MCAST_CTRL1 (MRX_REG_BASE+0x00000024)
+#define ADR_MRX_MCAST_TB2_0 (MRX_REG_BASE+0x00000028)
+#define ADR_MRX_MCAST_TB2_1 (MRX_REG_BASE+0x0000002c)
+#define ADR_MRX_MCAST_MK2_0 (MRX_REG_BASE+0x00000030)
+#define ADR_MRX_MCAST_MK2_1 (MRX_REG_BASE+0x00000034)
+#define ADR_MRX_MCAST_CTRL2 (MRX_REG_BASE+0x00000038)
+#define ADR_MRX_MCAST_TB3_0 (MRX_REG_BASE+0x0000003c)
+#define ADR_MRX_MCAST_TB3_1 (MRX_REG_BASE+0x00000040)
+#define ADR_MRX_MCAST_MK3_0 (MRX_REG_BASE+0x00000044)
+#define ADR_MRX_MCAST_MK3_1 (MRX_REG_BASE+0x00000048)
+#define ADR_MRX_MCAST_CTRL3 (MRX_REG_BASE+0x0000004c)
+#define ADR_MRX_PHY_INFO (MRX_REG_BASE+0x00000050)
+#define ADR_MRX_BA_DBG (MRX_REG_BASE+0x00000054)
+#define ADR_MRX_FLT_TB0 (MRX_REG_BASE+0x00000070)
+#define ADR_MRX_FLT_TB1 (MRX_REG_BASE+0x00000074)
+#define ADR_MRX_FLT_TB2 (MRX_REG_BASE+0x00000078)
+#define ADR_MRX_FLT_TB3 (MRX_REG_BASE+0x0000007c)
+#define ADR_MRX_FLT_TB4 (MRX_REG_BASE+0x00000080)
+#define ADR_MRX_FLT_TB5 (MRX_REG_BASE+0x00000084)
+#define ADR_MRX_FLT_TB6 (MRX_REG_BASE+0x00000088)
+#define ADR_MRX_FLT_TB7 (MRX_REG_BASE+0x0000008c)
+#define ADR_MRX_FLT_TB8 (MRX_REG_BASE+0x00000090)
+#define ADR_MRX_FLT_TB9 (MRX_REG_BASE+0x00000094)
+#define ADR_MRX_FLT_TB10 (MRX_REG_BASE+0x00000098)
+#define ADR_MRX_FLT_TB11 (MRX_REG_BASE+0x0000009c)
+#define ADR_MRX_FLT_TB12 (MRX_REG_BASE+0x000000a0)
+#define ADR_MRX_FLT_TB13 (MRX_REG_BASE+0x000000a4)
+#define ADR_MRX_FLT_TB14 (MRX_REG_BASE+0x000000a8)
+#define ADR_MRX_FLT_TB15 (MRX_REG_BASE+0x000000ac)
+#define ADR_MRX_FLT_EN0 (MRX_REG_BASE+0x000000b0)
+#define ADR_MRX_FLT_EN1 (MRX_REG_BASE+0x000000b4)
+#define ADR_MRX_FLT_EN2 (MRX_REG_BASE+0x000000b8)
+#define ADR_MRX_FLT_EN3 (MRX_REG_BASE+0x000000bc)
+#define ADR_MRX_FLT_EN4 (MRX_REG_BASE+0x000000c0)
+#define ADR_MRX_FLT_EN5 (MRX_REG_BASE+0x000000c4)
+#define ADR_MRX_FLT_EN6 (MRX_REG_BASE+0x000000c8)
+#define ADR_MRX_FLT_EN7 (MRX_REG_BASE+0x000000cc)
+#define ADR_MRX_FLT_EN8 (MRX_REG_BASE+0x000000d0)
+#define ADR_MRX_LEN_FLT (MRX_REG_BASE+0x000000d4)
+#define ADR_RX_FLOW_DATA (MRX_REG_BASE+0x000000e0)
+#define ADR_RX_FLOW_MNG (MRX_REG_BASE+0x000000e4)
+#define ADR_RX_FLOW_CTRL (MRX_REG_BASE+0x000000e8)
+#define ADR_RX_TIME_STAMP_CFG (MRX_REG_BASE+0x000000ec)
+#define ADR_DBG_FF_FULL (MRX_REG_BASE+0x000000f0)
+#define ADR_DBG_WFF_FULL (MRX_REG_BASE+0x000000f4)
+#define ADR_DBG_MB_FULL (MRX_REG_BASE+0x000000f8)
+#define ADR_BA_CTRL (MRX_REG_BASE+0x00000100)
+#define ADR_BA_TA_0 (MRX_REG_BASE+0x00000104)
+#define ADR_BA_TA_1 (MRX_REG_BASE+0x00000108)
+#define ADR_BA_TID (MRX_REG_BASE+0x0000010c)
+#define ADR_BA_ST_SEQ (MRX_REG_BASE+0x00000110)
+#define ADR_BA_SB0 (MRX_REG_BASE+0x00000114)
+#define ADR_BA_SB1 (MRX_REG_BASE+0x00000118)
+#define ADR_MRX_WATCH_DOG (MRX_REG_BASE+0x0000011c)
+#define ADR_ACK_GEN_EN (MRX_REG_BASE+0x00000120)
+#define ADR_ACK_GEN_PARA (MRX_REG_BASE+0x00000124)
+#define ADR_ACK_GEN_RA_0 (MRX_REG_BASE+0x00000128)
+#define ADR_ACK_GEN_RA_1 (MRX_REG_BASE+0x0000012c)
+#define ADR_MIB_LEN_FAIL (MRX_REG_BASE+0x00000130)
+#define ADR_TRAP_HW_ID (MRX_REG_BASE+0x00000134)
+#define ADR_ID_IN_USE (MRX_REG_BASE+0x00000138)
+#define ADR_MRX_ERR (MRX_REG_BASE+0x0000013c)
+#define ADR_GROUP_WSID (MRX_REG_BASE+0x00000190)
+#define ADR_HDR_ADDR_SEL (MRX_REG_BASE+0x00000194)
+#define ADR_FRAME_TYPE_CNTR_SET (MRX_REG_BASE+0x00000198)
+#define ADR_AMPDU_SCOREBOAD_SIZE (MRX_REG_BASE+0x0000019c)
+#define ADR_CHANNEL (MRX_REG_BASE+0x000001a0)
+#define ADR_HIGH_PRIORITY_FRM_HW_ID (MRX_REG_BASE+0x000001a4)
+#define ADR_DUAL_IDX_EXTEND (MRX_REG_BASE+0x000001a8)
+#define ADR_MRX_FLT_EN9 (MRX_REG_BASE+0x000001ac)
+#define ADR_MRX_FLT_EN10 (MRX_REG_BASE+0x000001b0)
+#define ADR_PHY_INFO (AMPDU_REG_BASE+0x00000000)
+#define ADR_AMPDU_SIG (AMPDU_REG_BASE+0x00000004)
+#define ADR_MIB_AMPDU (AMPDU_REG_BASE+0x00000008)
+#define ADR_LEN_FLT (AMPDU_REG_BASE+0x0000000c)
+#define ADR_MIB_DELIMITER (AMPDU_REG_BASE+0x00000010)
+#define ADR_MTX_INT_STS (MT_REG_CSR_BASE+0x00000000)
+#define ADR_MTX_INT_EN (MT_REG_CSR_BASE+0x00000004)
+#define ADR_MTX_MISC_EN (MT_REG_CSR_BASE+0x00000008)
+#define ADR_MTX_TX_REPORT_OPTION (MT_REG_CSR_BASE+0x0000000c)
+#define ADR_MTX_STATUS0 (MT_REG_CSR_BASE+0x00000010)
+#define ADR_MTX_STATUS4 (MT_REG_CSR_BASE+0x00000014)
+#define ADR_MTX_HALT_OPTION (MT_REG_CSR_BASE+0x00000018)
+#define ADR_MTX_PHYTX_DBG1 (MT_REG_CSR_BASE+0x0000001c)
+#define ADR_MTX_MIB_WSID0 (MT_REG_CSR_BASE+0x00000020)
+#define ADR_MTX_MIB_WSID1 (MT_REG_CSR_BASE+0x00000024)
+#define ADR_MTX_MIB_WSID2 (MT_REG_CSR_BASE+0x00000028)
+#define ADR_MTX_MIB_WSID3 (MT_REG_CSR_BASE+0x0000002c)
+#define ADR_MTX_MIB_WSID4 (MT_REG_CSR_BASE+0x00000030)
+#define ADR_MTX_MIB_WSID5 (MT_REG_CSR_BASE+0x00000034)
+#define ADR_MTX_MIB_WSID6 (MT_REG_CSR_BASE+0x00000038)
+#define ADR_MTX_MIB_WSID7 (MT_REG_CSR_BASE+0x0000003c)
+#define ADR_STAT_CONF0 (MT_REG_CSR_BASE+0x00000040)
+#define ADR_STAT_CONF1 (MT_REG_CSR_BASE+0x00000044)
+#define ADR_MTX_PEER_PS_LOCK (MT_REG_CSR_BASE+0x00000060)
+#define ADR_MTX_PEER_LOCK_STATUS (MT_REG_CSR_BASE+0x00000060)
+#define ADR_MTX_RATERPT (MT_REG_CSR_BASE+0x00000064)
+#define ADR_MTX_DBGOPT_FORCE_RATE (MT_REG_CSR_BASE+0x00000068)
+#define ADR_MTX_DBGOPT_FORCE_RATE_ENABLE (MT_REG_CSR_BASE+0x0000006c)
+#define ADR_MTX_DBG_PHYTXIPTIMEOUT (MT_REG_CSR_BASE+0x00000078)
+#define ADR_MTX_DBG_MORE (MT_REG_CSR_BASE+0x0000007c)
+#define ADR_MTX_DBG_ROIFSAIR1 (MT_REG_CSR_BASE+0x00000080)
+#define ADR_MTX_DBG_ROIFSAIR2 (MT_REG_CSR_BASE+0x00000084)
+#define ADR_MTX_BCN_PKT_SET0 (MT_REG_CSR_BASE+0x00000088)
+#define ADR_MTX_BCN_PKT_SET1 (MT_REG_CSR_BASE+0x0000008c)
+#define ADR_MTX_BCN_DTIM_SET0 (MT_REG_CSR_BASE+0x00000090)
+#define ADR_MTX_BCN_DTIM_SET1 (MT_REG_CSR_BASE+0x00000094)
+#define ADR_MTX_BCN_DTIM_CONFG (MT_REG_CSR_BASE+0x00000098)
+#define ADR_MTX_BCN_DTIM_INT_W1CLR (MT_REG_CSR_BASE+0x0000009c)
+#define ADR_MTX_BCN_INT_STS (MT_REG_CSR_BASE+0x000000a0)
+#define ADR_MTX_BCN_EN_INT (MT_REG_CSR_BASE+0x000000a4)
+#define ADR_MTX_BCN_EN_MISC (MT_REG_CSR_BASE+0x000000a8)
+#define ADR_MTX_BCN_MISC (MT_REG_CSR_BASE+0x000000ac)
+#define ADR_MTX_BCN_PRD (MT_REG_CSR_BASE+0x000000b0)
+#define ADR_MTX_BCN_TSF_L (MT_REG_CSR_BASE+0x000000b4)
+#define ADR_MTX_BCN_TSF_U (MT_REG_CSR_BASE+0x000000b8)
+#define ADR_MTX_TIME_TOUT (MT_REG_CSR_BASE+0x000000c0)
+#define ADR_MTX_TIME_IFS (MT_REG_CSR_BASE+0x000000c4)
+#define ADR_MTX_TIME_FINETUNE (MT_REG_CSR_BASE+0x000000c8)
+#define ADR_MTX_STATUS (MT_REG_CSR_BASE+0x000000cc)
+#define ADR_MTX_PHYRXIFS_DBG (MT_REG_CSR_BASE+0x000000d0)
+#define ADR_MTX_DBG_IFSAIRRO0 (MT_REG_CSR_BASE+0x000000e0)
+#define ADR_MTX_DBG_IFSAIRRO1 (MT_REG_CSR_BASE+0x000000e4)
+#define ADR_MTX_DBG_IFSAIRRO2 (MT_REG_CSR_BASE+0x000000e8)
+#define ADR_MTX_DBG_IFSAIRRO3 (MT_REG_CSR_BASE+0x000000ec)
+#define ADR_MTX_NAV (MT_REG_CSR_BASE+0x000000f0)
+#define ADR_MTX_DBG_RO_BASE1 (MT_REG_CSR_BASE+0x000000f4)
+#define ADR_MTX_DBG_RO_BASE2 (MT_REG_CSR_BASE+0x000000f8)
+#define ADR_MTX_DBG_RO_BASE3 (MT_REG_CSR_BASE+0x000000fc)
+#define ADR_TXQ0_MTX_Q_MISC_EN (TXQ0_MT_Q_REG_CSR_BASE+0x00000000)
+#define ADR_TXQ0_MTX_Q_AIFSN (TXQ0_MT_Q_REG_CSR_BASE+0x00000004)
+#define ADR_TXQ0_MTX_Q_BKF_CNT_DBG (TXQ0_MT_Q_REG_CSR_BASE+0x00000008)
+#define ADR_TXQ0_MTX_Q_HWDBG (TXQ0_MT_Q_REG_CSR_BASE+0x0000000c)
+#define ADR_TXQ0_MTX_Q_HWDBG2 (TXQ0_MT_Q_REG_CSR_BASE+0x00000010)
+#define ADR_TXQ1_MTX_Q_MISC_EN (TXQ1_MT_Q_REG_CSR_BASE+0x00000000)
+#define ADR_TXQ1_MTX_Q_AIFSN (TXQ1_MT_Q_REG_CSR_BASE+0x00000004)
+#define ADR_TXQ1_MTX_Q_BKF_CNT_DBG (TXQ1_MT_Q_REG_CSR_BASE+0x00000008)
+#define ADR_TXQ1_MTX_Q_HWDBG (TXQ1_MT_Q_REG_CSR_BASE+0x0000000c)
+#define ADR_TXQ1_MTX_Q_HWDBG2 (TXQ1_MT_Q_REG_CSR_BASE+0x00000010)
+#define ADR_TXQ2_MTX_Q_MISC_EN (TXQ2_MT_Q_REG_CSR_BASE+0x00000000)
+#define ADR_TXQ2_MTX_Q_AIFSN (TXQ2_MT_Q_REG_CSR_BASE+0x00000004)
+#define ADR_TXQ2_MTX_Q_BKF_CNT_DBG (TXQ2_MT_Q_REG_CSR_BASE+0x00000008)
+#define ADR_TXQ2_MTX_Q_HWDBG (TXQ2_MT_Q_REG_CSR_BASE+0x0000000c)
+#define ADR_TXQ2_MTX_Q_HWDBG2 (TXQ2_MT_Q_REG_CSR_BASE+0x00000010)
+#define ADR_TXQ3_MTX_Q_MISC_EN (TXQ3_MT_Q_REG_CSR_BASE+0x00000000)
+#define ADR_TXQ3_MTX_Q_AIFSN (TXQ3_MT_Q_REG_CSR_BASE+0x00000004)
+#define ADR_TXQ3_MTX_Q_BKF_CNT_DBG (TXQ3_MT_Q_REG_CSR_BASE+0x00000008)
+#define ADR_TXQ3_MTX_Q_HWDBG (TXQ3_MT_Q_REG_CSR_BASE+0x0000000c)
+#define ADR_TXQ3_MTX_Q_HWDBG2 (TXQ3_MT_Q_REG_CSR_BASE+0x00000010)
+#define ADR_TXQ4_MTX_Q_MISC_EN (TXQ4_MT_Q_REG_CSR_BASE+0x00000000)
+#define ADR_TXQ4_MTX_Q_AIFSN (TXQ4_MT_Q_REG_CSR_BASE+0x00000004)
+#define ADR_TXQ4_MTX_Q_BKF_CNT_DBG (TXQ4_MT_Q_REG_CSR_BASE+0x00000008)
+#define ADR_TXQ4_MTX_Q_HWDBG (TXQ4_MT_Q_REG_CSR_BASE+0x0000000c)
+#define ADR_TXQ4_MTX_Q_HWDBG2 (TXQ4_MT_Q_REG_CSR_BASE+0x00000010)
+#define ADR_TXQ5_MTX_Q_MISC_EN (TXQ5_MT_Q_REG_CSR_BASE+0x00000000)
+#define ADR_TXQ5_MTX_Q_AIFSN (TXQ5_MT_Q_REG_CSR_BASE+0x00000004)
+#define ADR_TXQ5_MTX_Q_BKF_CNT_DBG (TXQ5_MT_Q_REG_CSR_BASE+0x00000008)
+#define ADR_TXQ5_MTX_Q_HWDBG (TXQ5_MT_Q_REG_CSR_BASE+0x0000000c)
+#define ADR_TXQ5_MTX_Q_HWDBG2 (TXQ5_MT_Q_REG_CSR_BASE+0x00000010)
+#define ADR_MTX_RESPFRM_RATE_TABLE_EXCEPTION (MT_RESPFRM_REG_BASE+0x00000000)
+#define ADR_MTX_RESPFRM_RATE_TABLE_00 (MT_RESPFRM_REG_BASE+0x00000004)
+#define ADR_MTX_RESPFRM_RATE_TABLE_01 (MT_RESPFRM_REG_BASE+0x00000008)
+#define ADR_MTX_RESPFRM_RATE_TABLE_02 (MT_RESPFRM_REG_BASE+0x0000000c)
+#define ADR_MTX_RESPFRM_RATE_TABLE_03 (MT_RESPFRM_REG_BASE+0x00000010)
+#define ADR_MTX_RESPFRM_RATE_TABLE_11 (MT_RESPFRM_REG_BASE+0x00000014)
+#define ADR_MTX_RESPFRM_RATE_TABLE_12 (MT_RESPFRM_REG_BASE+0x00000018)
+#define ADR_MTX_RESPFRM_RATE_TABLE_13 (MT_RESPFRM_REG_BASE+0x0000001c)
+#define ADR_MTX_RESPFRM_RATE_TABLE_90_B0 (MT_RESPFRM_REG_BASE+0x00000020)
+#define ADR_MTX_RESPFRM_RATE_TABLE_91_B1 (MT_RESPFRM_REG_BASE+0x00000024)
+#define ADR_MTX_RESPFRM_RATE_TABLE_92_B2 (MT_RESPFRM_REG_BASE+0x00000028)
+#define ADR_MTX_RESPFRM_RATE_TABLE_93_B3 (MT_RESPFRM_REG_BASE+0x0000002c)
+#define ADR_MTX_RESPFRM_RATE_TABLE_94_B4 (MT_RESPFRM_REG_BASE+0x00000030)
+#define ADR_MTX_RESPFRM_RATE_TABLE_95_B5 (MT_RESPFRM_REG_BASE+0x00000034)
+#define ADR_MTX_RESPFRM_RATE_TABLE_96_B6 (MT_RESPFRM_REG_BASE+0x00000038)
+#define ADR_MTX_RESPFRM_RATE_TABLE_97_B7 (MT_RESPFRM_REG_BASE+0x0000003c)
+#define ADR_MTX_RESPFRM_RATE_TABLE_C0_E0 (MT_RESPFRM_REG_BASE+0x00000040)
+#define ADR_MTX_RESPFRM_RATE_TABLE_C1_E1 (MT_RESPFRM_REG_BASE+0x00000044)
+#define ADR_MTX_RESPFRM_RATE_TABLE_C2_E2 (MT_RESPFRM_REG_BASE+0x00000048)
+#define ADR_MTX_RESPFRM_RATE_TABLE_C3_E3 (MT_RESPFRM_REG_BASE+0x0000004c)
+#define ADR_MTX_RESPFRM_RATE_TABLE_C4_E4 (MT_RESPFRM_REG_BASE+0x00000050)
+#define ADR_MTX_RESPFRM_RATE_TABLE_C5_E5 (MT_RESPFRM_REG_BASE+0x00000054)
+#define ADR_MTX_RESPFRM_RATE_TABLE_C6_E6 (MT_RESPFRM_REG_BASE+0x00000058)
+#define ADR_MTX_RESPFRM_RATE_TABLE_C7_E7 (MT_RESPFRM_REG_BASE+0x0000005c)
+#define ADR_MTX_RESPFRM_RATE_TABLE_D0_F0 (MT_RESPFRM_REG_BASE+0x00000060)
+#define ADR_MTX_RESPFRM_RATE_TABLE_D1_F1 (MT_RESPFRM_REG_BASE+0x00000064)
+#define ADR_MTX_RESPFRM_RATE_TABLE_D2_F2 (MT_RESPFRM_REG_BASE+0x00000068)
+#define ADR_MTX_RESPFRM_RATE_TABLE_D3_F3 (MT_RESPFRM_REG_BASE+0x0000006c)
+#define ADR_MTX_RESPFRM_RATE_TABLE_D4_F4 (MT_RESPFRM_REG_BASE+0x00000070)
+#define ADR_MTX_RESPFRM_RATE_TABLE_D5_F5 (MT_RESPFRM_REG_BASE+0x00000074)
+#define ADR_MTX_RESPFRM_RATE_TABLE_D6_F6 (MT_RESPFRM_REG_BASE+0x00000078)
+#define ADR_MTX_RESPFRM_RATE_TABLE_D7_F7 (MT_RESPFRM_REG_BASE+0x0000007c)
+#define ADR_MTX_RESPFRM_RATE_TABLE_D8_F8 (MT_RESPFRM_REG_BASE+0x00000080)
+#define ADR_MTX_RESPFRM_RATE_TABLE_D9_F9 (MT_RESPFRM_REG_BASE+0x00000084)
+#define ADR_MTX_RESPFRM_RATE_TABLE_DA_FA (MT_RESPFRM_REG_BASE+0x00000088)
+#define ADR_MTX_RESPFRM_RATE_TABLE_DB_FB (MT_RESPFRM_REG_BASE+0x0000008c)
+#define ADR_MTX_RESPFRM_RATE_TABLE_DC_FC (MT_RESPFRM_REG_BASE+0x00000090)
+#define ADR_MTX_RESPFRM_RATE_TABLE_DD_FD (MT_RESPFRM_REG_BASE+0x00000094)
+#define ADR_MTX_RESPFRM_RATE_TABLE_DE_FE (MT_RESPFRM_REG_BASE+0x00000098)
+#define ADR_MTX_RESPFRM_RATE_TABLE_DF_FF (MT_RESPFRM_REG_BASE+0x0000009c)
+#define ADR_MTX_RESPFRM_INFO_TABLE_EXCEPTION (MT_RESPFRM_REG_BASE+0x000000a0)
+#define ADR_MTX_RESPFRM_INFO_00 (MT_RESPFRM_REG_BASE+0x000000a4)
+#define ADR_MTX_RESPFRM_INFO_01 (MT_RESPFRM_REG_BASE+0x000000a8)
+#define ADR_MTX_RESPFRM_INFO_02 (MT_RESPFRM_REG_BASE+0x000000ac)
+#define ADR_MTX_RESPFRM_INFO_03 (MT_RESPFRM_REG_BASE+0x000000b0)
+#define ADR_MTX_RESPFRM_INFO_11 (MT_RESPFRM_REG_BASE+0x000000b4)
+#define ADR_MTX_RESPFRM_INFO_12 (MT_RESPFRM_REG_BASE+0x000000b8)
+#define ADR_MTX_RESPFRM_INFO_13 (MT_RESPFRM_REG_BASE+0x000000bc)
+#define ADR_MTX_RESPFRM_INFO_90_B0 (MT_RESPFRM_REG_BASE+0x000000c0)
+#define ADR_MTX_RESPFRM_INFO_91_B1 (MT_RESPFRM_REG_BASE+0x000000c4)
+#define ADR_MTX_RESPFRM_INFO_92_B2 (MT_RESPFRM_REG_BASE+0x000000c8)
+#define ADR_MTX_RESPFRM_INFO_93_B3 (MT_RESPFRM_REG_BASE+0x000000cc)
+#define ADR_MTX_RESPFRM_INFO_94_B4 (MT_RESPFRM_REG_BASE+0x000000d0)
+#define ADR_MTX_RESPFRM_INFO_95_B5 (MT_RESPFRM_REG_BASE+0x000000d4)
+#define ADR_MTX_RESPFRM_INFO_96_B6 (MT_RESPFRM_REG_BASE+0x000000d8)
+#define ADR_MTX_RESPFRM_INFO_97_B7 (MT_RESPFRM_REG_BASE+0x000000dc)
+#define ADR_MTX_RESPFRM_INFO_C0 (MT_RESPFRM_REG_BASE+0x000000e0)
+#define ADR_MTX_RESPFRM_INFO_C1 (MT_RESPFRM_REG_BASE+0x000000e4)
+#define ADR_MTX_RESPFRM_INFO_C2 (MT_RESPFRM_REG_BASE+0x000000e8)
+#define ADR_MTX_RESPFRM_INFO_C3 (MT_RESPFRM_REG_BASE+0x000000ec)
+#define ADR_MTX_RESPFRM_INFO_C4 (MT_RESPFRM_REG_BASE+0x000000f0)
+#define ADR_MTX_RESPFRM_INFO_C5 (MT_RESPFRM_REG_BASE+0x000000f4)
+#define ADR_MTX_RESPFRM_INFO_C6 (MT_RESPFRM_REG_BASE+0x000000f8)
+#define ADR_MTX_RESPFRM_INFO_C7 (MT_RESPFRM_REG_BASE+0x000000fc)
+#define ADR_MTX_RESPFRM_INFO_D0 (MT_RESPFRM_REG_BASE+0x00000100)
+#define ADR_MTX_RESPFRM_INFO_D1 (MT_RESPFRM_REG_BASE+0x00000104)
+#define ADR_MTX_RESPFRM_INFO_D2 (MT_RESPFRM_REG_BASE+0x00000108)
+#define ADR_MTX_RESPFRM_INFO_D3 (MT_RESPFRM_REG_BASE+0x0000010c)
+#define ADR_MTX_RESPFRM_INFO_D4 (MT_RESPFRM_REG_BASE+0x00000110)
+#define ADR_MTX_RESPFRM_INFO_D5 (MT_RESPFRM_REG_BASE+0x00000114)
+#define ADR_MTX_RESPFRM_INFO_D6 (MT_RESPFRM_REG_BASE+0x00000118)
+#define ADR_MTX_RESPFRM_INFO_D7 (MT_RESPFRM_REG_BASE+0x0000011c)
+#define ADR_MTX_RESPFRM_INFO_D8 (MT_RESPFRM_REG_BASE+0x00000120)
+#define ADR_MTX_RESPFRM_INFO_D9 (MT_RESPFRM_REG_BASE+0x00000124)
+#define ADR_MTX_RESPFRM_INFO_DA (MT_RESPFRM_REG_BASE+0x00000128)
+#define ADR_MTX_RESPFRM_INFO_DB (MT_RESPFRM_REG_BASE+0x0000012c)
+#define ADR_MTX_RESPFRM_INFO_DC (MT_RESPFRM_REG_BASE+0x00000130)
+#define ADR_MTX_RESPFRM_INFO_DD (MT_RESPFRM_REG_BASE+0x00000134)
+#define ADR_MTX_RESPFRM_INFO_DE (MT_RESPFRM_REG_BASE+0x00000138)
+#define ADR_MTX_RESPFRM_INFO_DF (MT_RESPFRM_REG_BASE+0x0000013c)
+#define ADR_WSID0 (HIF_INFO_BASE+0x00000000)
+#define ADR_PEER_MAC0_0 (HIF_INFO_BASE+0x00000004)
+#define ADR_PEER_MAC0_1 (HIF_INFO_BASE+0x00000008)
+#define ADR_TX_ACK_POLICY_0_0 (HIF_INFO_BASE+0x0000000c)
+#define ADR_TX_SEQ_CTRL_0_0 (HIF_INFO_BASE+0x00000010)
+#define ADR_TX_ACK_POLICY_0_1 (HIF_INFO_BASE+0x00000014)
+#define ADR_TX_SEQ_CTRL_0_1 (HIF_INFO_BASE+0x00000018)
+#define ADR_TX_ACK_POLICY_0_2 (HIF_INFO_BASE+0x0000001c)
+#define ADR_TX_SEQ_CTRL_0_2 (HIF_INFO_BASE+0x00000020)
+#define ADR_TX_ACK_POLICY_0_3 (HIF_INFO_BASE+0x00000024)
+#define ADR_TX_SEQ_CTRL_0_3 (HIF_INFO_BASE+0x00000028)
+#define ADR_TX_ACK_POLICY_0_4 (HIF_INFO_BASE+0x0000002c)
+#define ADR_TX_SEQ_CTRL_0_4 (HIF_INFO_BASE+0x00000030)
+#define ADR_TX_ACK_POLICY_0_5 (HIF_INFO_BASE+0x00000034)
+#define ADR_TX_SEQ_CTRL_0_5 (HIF_INFO_BASE+0x00000038)
+#define ADR_TX_ACK_POLICY_0_6 (HIF_INFO_BASE+0x0000003c)
+#define ADR_TX_SEQ_CTRL_0_6 (HIF_INFO_BASE+0x00000040)
+#define ADR_TX_ACK_POLICY_0_7 (HIF_INFO_BASE+0x00000044)
+#define ADR_TX_SEQ_CTRL_0_7 (HIF_INFO_BASE+0x00000048)
+#define ADR_WSID1 (HIF_INFO_BASE+0x00000050)
+#define ADR_PEER_MAC1_0 (HIF_INFO_BASE+0x00000054)
+#define ADR_PEER_MAC1_1 (HIF_INFO_BASE+0x00000058)
+#define ADR_TX_ACK_POLICY_1_0 (HIF_INFO_BASE+0x0000005c)
+#define ADR_TX_SEQ_CTRL_1_0 (HIF_INFO_BASE+0x00000060)
+#define ADR_TX_ACK_POLICY_1_1 (HIF_INFO_BASE+0x00000064)
+#define ADR_TX_SEQ_CTRL_1_1 (HIF_INFO_BASE+0x00000068)
+#define ADR_TX_ACK_POLICY_1_2 (HIF_INFO_BASE+0x0000006c)
+#define ADR_TX_SEQ_CTRL_1_2 (HIF_INFO_BASE+0x00000070)
+#define ADR_TX_ACK_POLICY_1_3 (HIF_INFO_BASE+0x00000074)
+#define ADR_TX_SEQ_CTRL_1_3 (HIF_INFO_BASE+0x00000078)
+#define ADR_TX_ACK_POLICY_1_4 (HIF_INFO_BASE+0x0000007c)
+#define ADR_TX_SEQ_CTRL_1_4 (HIF_INFO_BASE+0x00000080)
+#define ADR_TX_ACK_POLICY_1_5 (HIF_INFO_BASE+0x00000084)
+#define ADR_TX_SEQ_CTRL_1_5 (HIF_INFO_BASE+0x00000088)
+#define ADR_TX_ACK_POLICY_1_6 (HIF_INFO_BASE+0x0000008c)
+#define ADR_TX_SEQ_CTRL_1_6 (HIF_INFO_BASE+0x00000090)
+#define ADR_TX_ACK_POLICY_1_7 (HIF_INFO_BASE+0x00000094)
+#define ADR_TX_SEQ_CTRL_1_7 (HIF_INFO_BASE+0x00000098)
+#define ADR_PACKET_ID_ALLOCATION_PRIORITY (PHY_RATE_INFO_BASE+0x00000000)
+#define ADR_MAC_MODE (MAC_GLB_SET_BASE+0x00000000)
+#define ADR_ALL_SOFTWARE_RESET (MAC_GLB_SET_BASE+0x00000004)
+#define ADR_ENG_SOFTWARE_RESET (MAC_GLB_SET_BASE+0x00000008)
+#define ADR_CSR_SOFTWARE_RESET (MAC_GLB_SET_BASE+0x0000000c)
+#define ADR_MAC_CLOCK_ENABLE (MAC_GLB_SET_BASE+0x00000010)
+#define ADR_MAC_ENGINE_CLOCK_ENABLE (MAC_GLB_SET_BASE+0x00000014)
+#define ADR_MAC_CSR_CLOCK_ENABLE (MAC_GLB_SET_BASE+0x00000018)
+#define ADR_GLBLE_SET (MAC_GLB_SET_BASE+0x0000001c)
+#define ADR_REASON_TRAP0 (MAC_GLB_SET_BASE+0x00000020)
+#define ADR_REASON_TRAP1 (MAC_GLB_SET_BASE+0x00000024)
+#define ADR_BSSID_0 (MAC_GLB_SET_BASE+0x00000028)
+#define ADR_BSSID_1 (MAC_GLB_SET_BASE+0x0000002c)
+#define ADR_STA_MAC_0 (MAC_GLB_SET_BASE+0x00000030)
+#define ADR_STA_MAC_1 (MAC_GLB_SET_BASE+0x00000034)
+#define ADR_SCRT_SET (MAC_GLB_SET_BASE+0x00000038)
+#define ADR_SCRT_STATE (MAC_GLB_SET_BASE+0x0000003c)
+#define ADR_BSSID1_0 (MAC_GLB_SET_BASE+0x00000040)
+#define ADR_BSSID1_1 (MAC_GLB_SET_BASE+0x00000044)
+#define ADR_STA_MAC1_0 (MAC_GLB_SET_BASE+0x00000048)
+#define ADR_STA_MAC1_1 (MAC_GLB_SET_BASE+0x0000004c)
+#define ADR_OP_MODE1 (MAC_GLB_SET_BASE+0x00000050)
+#define ADR_BTCX0 (BTCX_REG_BASE+0x00000000)
+#define ADR_BTCX1 (BTCX_REG_BASE+0x00000004)
+#define ADR_SWITCH_CTL (BTCX_REG_BASE+0x00000008)
+#define ADR_RANDOM_CTL (BTCX_REG_BASE+0x0000000c)
+#define ADR_BTCX_MISC_CTL (BTCX_REG_BASE+0x00000010)
+#define ADR_MIB_EN (MIB_REG_BASE+0x00000000)
+#define ADR_MTX_WSID0_SUCC (MIB_REG_BASE+0x00000118)
+#define ADR_MTX_WSID0_FRM (MIB_REG_BASE+0x00000128)
+#define ADR_MTX_WSID0_RETRY (MIB_REG_BASE+0x00000138)
+#define ADR_MTX_WSID0_TOTAL (MIB_REG_BASE+0x00000148)
+#define ADR_MTX_GROUP (MIB_REG_BASE+0x0000016c)
+#define ADR_MTX_FAIL (MIB_REG_BASE+0x00000170)
+#define ADR_MTX_RETRY (MIB_REG_BASE+0x00000174)
+#define ADR_MTX_MULTI_RETRY (MIB_REG_BASE+0x00000178)
+#define ADR_MTX_RTS_SUCCESS (MIB_REG_BASE+0x0000017c)
+#define ADR_MTX_RTS_FAIL (MIB_REG_BASE+0x00000180)
+#define ADR_MTX_ACK_FAIL (MIB_REG_BASE+0x00000184)
+#define ADR_MTX_FRM (MIB_REG_BASE+0x00000188)
+#define ADR_MTX_ACK_TX (MIB_REG_BASE+0x0000018c)
+#define ADR_MTX_CTS_TX (MIB_REG_BASE+0x00000190)
+#define ADR_MRX_DUP_FRM (MIB_REG_BASE+0x00000194)
+#define ADR_MRX_FRG_FRM (MIB_REG_BASE+0x00000198)
+#define ADR_MRX_GROUP_FRM (MIB_REG_BASE+0x0000019c)
+#define ADR_MRX_FCS_ERR (MIB_REG_BASE+0x000001a0)
+#define ADR_MRX_FCS_SUCC (MIB_REG_BASE+0x000001a4)
+#define ADR_MRX_MISS (MIB_REG_BASE+0x000001a8)
+#define ADR_MRX_ALC_FAIL (MIB_REG_BASE+0x000001ac)
+#define ADR_MRX_DAT_NTF (MIB_REG_BASE+0x000001b0)
+#define ADR_MRX_RTS_NTF (MIB_REG_BASE+0x000001b4)
+#define ADR_MRX_CTS_NTF (MIB_REG_BASE+0x000001b8)
+#define ADR_MRX_ACK_NTF (MIB_REG_BASE+0x000001bc)
+#define ADR_MRX_BA_NTF (MIB_REG_BASE+0x000001c0)
+#define ADR_MRX_DATA_NTF (MIB_REG_BASE+0x000001c4)
+#define ADR_MRX_MNG_NTF (MIB_REG_BASE+0x000001c8)
+#define ADR_MRX_DAT_CRC_NTF (MIB_REG_BASE+0x000001cc)
+#define ADR_MRX_BAR_NTF (MIB_REG_BASE+0x000001d0)
+#define ADR_MRX_MB_MISS (MIB_REG_BASE+0x000001d4)
+#define ADR_MRX_NIDLE_MISS (MIB_REG_BASE+0x000001d8)
+#define ADR_MRX_CSR_NTF (MIB_REG_BASE+0x000001dc)
+#define ADR_DBG_Q0_FRM_SUCCESS (MIB_REG_BASE+0x00000218)
+#define ADR_DBG_Q0_FRM_FAIL (MIB_REG_BASE+0x0000021c)
+#define ADR_DBG_Q0_ACK_SUCCESS (MIB_REG_BASE+0x00000220)
+#define ADR_DBG_Q0_ACK_FAIL (MIB_REG_BASE+0x00000224)
+#define ADR_DBG_Q1_FRM_SUCCESS (MIB_REG_BASE+0x00000268)
+#define ADR_DBG_Q1_FRM_FAIL (MIB_REG_BASE+0x0000026c)
+#define ADR_DBG_Q1_ACK_SUCCESS (MIB_REG_BASE+0x00000270)
+#define ADR_DBG_Q1_ACK_FAIL (MIB_REG_BASE+0x00000274)
+#define ADR_DBG_Q2_FRM_SUCCESS (MIB_REG_BASE+0x00000318)
+#define ADR_DBG_Q2_FRM_FAIL (MIB_REG_BASE+0x0000031c)
+#define ADR_DBG_Q2_ACK_SUCCESS (MIB_REG_BASE+0x00000320)
+#define ADR_DBG_Q2_ACK_FAIL (MIB_REG_BASE+0x00000324)
+#define ADR_DBG_Q3_FRM_SUCCESS (MIB_REG_BASE+0x00000368)
+#define ADR_DBG_Q3_FRM_FAIL (MIB_REG_BASE+0x0000036c)
+#define ADR_DBG_Q3_ACK_SUCCESS (MIB_REG_BASE+0x00000370)
+#define ADR_DBG_Q3_ACK_FAIL (MIB_REG_BASE+0x00000374)
+#define ADR_MIB_SCRT_TKIP0 (MIB_REG_BASE+0x00000418)
+#define ADR_MIB_SCRT_TKIP1 (MIB_REG_BASE+0x0000041c)
+#define ADR_MIB_SCRT_TKIP2 (MIB_REG_BASE+0x00000420)
+#define ADR_MIB_SCRT_CCMP0 (MIB_REG_BASE+0x00000424)
+#define ADR_MIB_SCRT_CCMP1 (MIB_REG_BASE+0x00000428)
+#define ADR_DBG_LEN_CRC_FAIL (MIB_REG_BASE+0x00000468)
+#define ADR_DBG_LEN_ALC_FAIL (MIB_REG_BASE+0x0000046c)
+#define ADR_DBG_AMPDU_PASS (MIB_REG_BASE+0x00000470)
+#define ADR_DBG_AMPDU_FAIL (MIB_REG_BASE+0x00000474)
+#define ADR_ID_ALC_FAIL1 (MIB_REG_BASE+0x00000478)
+#define ADR_ID_ALC_FAIL2 (MIB_REG_BASE+0x0000047c)
+#define ADR_WSID2 (WSID_EXT_BASE+0x00000000)
+#define ADR_PEER_MAC2_0 (WSID_EXT_BASE+0x00000004)
+#define ADR_PEER_MAC2_1 (WSID_EXT_BASE+0x00000008)
+#define ADR_TX_ACK_POLICY_2_0 (WSID_EXT_BASE+0x0000000c)
+#define ADR_TX_SEQ_CTRL_2_0 (WSID_EXT_BASE+0x00000010)
+#define ADR_TX_ACK_POLICY_2_1 (WSID_EXT_BASE+0x00000014)
+#define ADR_TX_SEQ_CTRL_2_1 (WSID_EXT_BASE+0x00000018)
+#define ADR_TX_ACK_POLICY_2_2 (WSID_EXT_BASE+0x0000001c)
+#define ADR_TX_SEQ_CTRL_2_2 (WSID_EXT_BASE+0x00000020)
+#define ADR_TX_ACK_POLICY_2_3 (WSID_EXT_BASE+0x00000024)
+#define ADR_TX_SEQ_CTRL_2_3 (WSID_EXT_BASE+0x00000028)
+#define ADR_TX_ACK_POLICY_2_4 (WSID_EXT_BASE+0x0000002c)
+#define ADR_TX_SEQ_CTRL_2_4 (WSID_EXT_BASE+0x00000030)
+#define ADR_TX_ACK_POLICY_2_5 (WSID_EXT_BASE+0x00000034)
+#define ADR_TX_SEQ_CTRL_2_5 (WSID_EXT_BASE+0x00000038)
+#define ADR_TX_ACK_POLICY_2_6 (WSID_EXT_BASE+0x0000003c)
+#define ADR_TX_SEQ_CTRL_2_6 (WSID_EXT_BASE+0x00000040)
+#define ADR_TX_ACK_POLICY_2_7 (WSID_EXT_BASE+0x00000044)
+#define ADR_TX_SEQ_CTRL_2_7 (WSID_EXT_BASE+0x00000048)
+#define ADR_WSID3 (WSID_EXT_BASE+0x00000050)
+#define ADR_PEER_MAC3_0 (WSID_EXT_BASE+0x00000054)
+#define ADR_PEER_MAC3_1 (WSID_EXT_BASE+0x00000058)
+#define ADR_TX_ACK_POLICY_3_0 (WSID_EXT_BASE+0x0000005c)
+#define ADR_TX_SEQ_CTRL_3_0 (WSID_EXT_BASE+0x00000060)
+#define ADR_TX_ACK_POLICY_3_1 (WSID_EXT_BASE+0x00000064)
+#define ADR_TX_SEQ_CTRL_3_1 (WSID_EXT_BASE+0x00000068)
+#define ADR_TX_ACK_POLICY_3_2 (WSID_EXT_BASE+0x0000006c)
+#define ADR_TX_SEQ_CTRL_3_2 (WSID_EXT_BASE+0x00000070)
+#define ADR_TX_ACK_POLICY_3_3 (WSID_EXT_BASE+0x00000074)
+#define ADR_TX_SEQ_CTRL_3_3 (WSID_EXT_BASE+0x00000078)
+#define ADR_TX_ACK_POLICY_3_4 (WSID_EXT_BASE+0x0000007c)
+#define ADR_TX_SEQ_CTRL_3_4 (WSID_EXT_BASE+0x00000080)
+#define ADR_TX_ACK_POLICY_3_5 (WSID_EXT_BASE+0x00000084)
+#define ADR_TX_SEQ_CTRL_3_5 (WSID_EXT_BASE+0x00000088)
+#define ADR_TX_ACK_POLICY_3_6 (WSID_EXT_BASE+0x0000008c)
+#define ADR_TX_SEQ_CTRL_3_6 (WSID_EXT_BASE+0x00000090)
+#define ADR_TX_ACK_POLICY_3_7 (WSID_EXT_BASE+0x00000094)
+#define ADR_TX_SEQ_CTRL_3_7 (WSID_EXT_BASE+0x00000098)
+#define ADR_WSID4 (WSID_EXT_BASE+0x000000a0)
+#define ADR_PEER_MAC4_0 (WSID_EXT_BASE+0x000000a4)
+#define ADR_PEER_MAC4_1 (WSID_EXT_BASE+0x000000a8)
+#define ADR_TX_ACK_POLICY_4_0 (WSID_EXT_BASE+0x000000ac)
+#define ADR_TX_SEQ_CTRL_4_0 (WSID_EXT_BASE+0x000000b0)
+#define ADR_TX_ACK_POLICY_4_1 (WSID_EXT_BASE+0x000000b4)
+#define ADR_TX_SEQ_CTRL_4_1 (WSID_EXT_BASE+0x000000b8)
+#define ADR_TX_ACK_POLICY_4_2 (WSID_EXT_BASE+0x000000bc)
+#define ADR_TX_SEQ_CTRL_4_2 (WSID_EXT_BASE+0x000000c0)
+#define ADR_TX_ACK_POLICY_4_3 (WSID_EXT_BASE+0x000000c4)
+#define ADR_TX_SEQ_CTRL_4_3 (WSID_EXT_BASE+0x000000c8)
+#define ADR_TX_ACK_POLICY_4_4 (WSID_EXT_BASE+0x000000cc)
+#define ADR_TX_SEQ_CTRL_4_4 (WSID_EXT_BASE+0x000000d0)
+#define ADR_TX_ACK_POLICY_4_5 (WSID_EXT_BASE+0x000000d4)
+#define ADR_TX_SEQ_CTRL_4_5 (WSID_EXT_BASE+0x000000d8)
+#define ADR_TX_ACK_POLICY_4_6 (WSID_EXT_BASE+0x000000dc)
+#define ADR_TX_SEQ_CTRL_4_6 (WSID_EXT_BASE+0x000000e0)
+#define ADR_TX_ACK_POLICY_4_7 (WSID_EXT_BASE+0x000000e4)
+#define ADR_TX_SEQ_CTRL_4_7 (WSID_EXT_BASE+0x000000e8)
+#define ADR_WSID5 (WSID_EXT_BASE+0x000000f0)
+#define ADR_PEER_MAC5_0 (WSID_EXT_BASE+0x000000f4)
+#define ADR_PEER_MAC5_1 (WSID_EXT_BASE+0x000000f8)
+#define ADR_TX_ACK_POLICY_5_0 (WSID_EXT_BASE+0x000000fc)
+#define ADR_TX_SEQ_CTRL_5_0 (WSID_EXT_BASE+0x00000100)
+#define ADR_TX_ACK_POLICY_5_1 (WSID_EXT_BASE+0x00000104)
+#define ADR_TX_SEQ_CTRL_5_1 (WSID_EXT_BASE+0x00000108)
+#define ADR_TX_ACK_POLICY_5_2 (WSID_EXT_BASE+0x0000010c)
+#define ADR_TX_SEQ_CTRL_5_2 (WSID_EXT_BASE+0x00000110)
+#define ADR_TX_ACK_POLICY_5_3 (WSID_EXT_BASE+0x00000114)
+#define ADR_TX_SEQ_CTRL_5_3 (WSID_EXT_BASE+0x00000118)
+#define ADR_TX_ACK_POLICY_5_4 (WSID_EXT_BASE+0x0000011c)
+#define ADR_TX_SEQ_CTRL_5_4 (WSID_EXT_BASE+0x00000120)
+#define ADR_TX_ACK_POLICY_5_5 (WSID_EXT_BASE+0x00000124)
+#define ADR_TX_SEQ_CTRL_5_5 (WSID_EXT_BASE+0x00000128)
+#define ADR_TX_ACK_POLICY_5_6 (WSID_EXT_BASE+0x0000012c)
+#define ADR_TX_SEQ_CTRL_5_6 (WSID_EXT_BASE+0x00000130)
+#define ADR_TX_ACK_POLICY_5_7 (WSID_EXT_BASE+0x00000134)
+#define ADR_TX_SEQ_CTRL_5_7 (WSID_EXT_BASE+0x00000138)
+#define ADR_WSID6 (WSID_EXT_BASE+0x00000140)
+#define ADR_PEER_MAC6_0 (WSID_EXT_BASE+0x00000144)
+#define ADR_PEER_MAC6_1 (WSID_EXT_BASE+0x00000148)
+#define ADR_TX_ACK_POLICY_6_0 (WSID_EXT_BASE+0x0000014c)
+#define ADR_TX_SEQ_CTRL_6_0 (WSID_EXT_BASE+0x00000150)
+#define ADR_TX_ACK_POLICY_6_1 (WSID_EXT_BASE+0x00000154)
+#define ADR_TX_SEQ_CTRL_6_1 (WSID_EXT_BASE+0x00000158)
+#define ADR_TX_ACK_POLICY_6_2 (WSID_EXT_BASE+0x0000015c)
+#define ADR_TX_SEQ_CTRL_6_2 (WSID_EXT_BASE+0x00000160)
+#define ADR_TX_ACK_POLICY_6_3 (WSID_EXT_BASE+0x00000164)
+#define ADR_TX_SEQ_CTRL_6_3 (WSID_EXT_BASE+0x00000168)
+#define ADR_TX_ACK_POLICY_6_4 (WSID_EXT_BASE+0x0000016c)
+#define ADR_TX_SEQ_CTRL_6_4 (WSID_EXT_BASE+0x00000170)
+#define ADR_TX_ACK_POLICY_6_5 (WSID_EXT_BASE+0x00000174)
+#define ADR_TX_SEQ_CTRL_6_5 (WSID_EXT_BASE+0x00000178)
+#define ADR_TX_ACK_POLICY_6_6 (WSID_EXT_BASE+0x0000017c)
+#define ADR_TX_SEQ_CTRL_6_6 (WSID_EXT_BASE+0x00000180)
+#define ADR_TX_ACK_POLICY_6_7 (WSID_EXT_BASE+0x00000184)
+#define ADR_TX_SEQ_CTRL_6_7 (WSID_EXT_BASE+0x00000188)
+#define ADR_WSID7 (WSID_EXT_BASE+0x00000190)
+#define ADR_PEER_MAC7_0 (WSID_EXT_BASE+0x00000194)
+#define ADR_PEER_MAC7_1 (WSID_EXT_BASE+0x00000198)
+#define ADR_TX_ACK_POLICY_7_0 (WSID_EXT_BASE+0x0000019c)
+#define ADR_TX_SEQ_CTRL_7_0 (WSID_EXT_BASE+0x000001a0)
+#define ADR_TX_ACK_POLICY_7_1 (WSID_EXT_BASE+0x000001a4)
+#define ADR_TX_SEQ_CTRL_7_1 (WSID_EXT_BASE+0x000001a8)
+#define ADR_TX_ACK_POLICY_7_2 (WSID_EXT_BASE+0x000001ac)
+#define ADR_TX_SEQ_CTRL_7_2 (WSID_EXT_BASE+0x000001b0)
+#define ADR_TX_ACK_POLICY_7_3 (WSID_EXT_BASE+0x000001b4)
+#define ADR_TX_SEQ_CTRL_7_3 (WSID_EXT_BASE+0x000001b8)
+#define ADR_TX_ACK_POLICY_7_4 (WSID_EXT_BASE+0x000001bc)
+#define ADR_TX_SEQ_CTRL_7_4 (WSID_EXT_BASE+0x000001c0)
+#define ADR_TX_ACK_POLICY_7_5 (WSID_EXT_BASE+0x000001c4)
+#define ADR_TX_SEQ_CTRL_7_5 (WSID_EXT_BASE+0x000001c8)
+#define ADR_TX_ACK_POLICY_7_6 (WSID_EXT_BASE+0x000001cc)
+#define ADR_TX_SEQ_CTRL_7_6 (WSID_EXT_BASE+0x000001d0)
+#define ADR_TX_ACK_POLICY_7_7 (WSID_EXT_BASE+0x000001d4)
+#define ADR_TX_SEQ_CTRL_7_7 (WSID_EXT_BASE+0x000001d8)
+#define ADR_GEMINIA_3_WIRE_REGISTER (RF_REG_BASE+0x00b0a000)
+#define ADR_GEMINIA_MANUAL_ENABLE_REGISTER (RF_REG_BASE+0x00b0a004)
+#define ADR_GEMINIA_CALIBRATION_TEST_REGISTER (RF_REG_BASE+0x00b0a008)
+#define ADR_GEMINIA_LDO_REGISTER (RF_REG_BASE+0x00b0a00c)
+#define ADR_GEMINIA_WIFI_RX_FILTER_REGISTER (RF_REG_BASE+0x00b0a010)
+#define ADR_GEMINIA_BT_RX_FILTER_REGISTER (RF_REG_BASE+0x00b0a014)
+#define ADR_GEMINIA_RX_REGISTER (RF_REG_BASE+0x00b0a018)
+#define ADR_GEMINIA_WBT_TX_FE_REGISTER (RF_REG_BASE+0x00b0a01c)
+#define ADR_GEMINIA_WBT_TX_PA_REGISTER (RF_REG_BASE+0x00b0a020)
+#define ADR_GEMINIA_TX_REGISTER (RF_REG_BASE+0x00b0a024)
+#define ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER (RF_REG_BASE+0x00b0a028)
+#define ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER (RF_REG_BASE+0x00b0a02c)
+#define ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER (RF_REG_BASE+0x00b0a030)
+#define ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER (RF_REG_BASE+0x00b0a034)
+#define ADR_GEMINIA_BT_RX_FE_HG_REGISTER (RF_REG_BASE+0x00b0a038)
+#define ADR_GEMINIA_BT_RX_FE_MG_REGISTER (RF_REG_BASE+0x00b0a03c)
+#define ADR_GEMINIA_BT_RX_FE_LG_REGISTER (RF_REG_BASE+0x00b0a040)
+#define ADR_GEMINIA_BT_RX_FE_ULG_REGISTER (RF_REG_BASE+0x00b0a044)
+#define ADR_GEMINIA_RX_ADC_REGISTER (RF_REG_BASE+0x00b0a048)
+#define ADR_GEMINIA_WIFI_TX_DAC_REGISTER (RF_REG_BASE+0x00b0a04c)
+#define ADR_GEMINIA_BT_TX_DAC_REGISTER (RF_REG_BASE+0x00b0a050)
+#define ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER (RF_REG_BASE+0x00b0a054)
+#define ADR_GEMINIA_SX_LDO_REGISTER (RF_REG_BASE+0x00b0a058)
+#define ADR_GEMINIA_SYN_FRACTIONAL_AND_INTEGER_8BITS (RF_REG_BASE+0x00b0a05c)
+#define ADR_GEMINIA_SYN_REGISTER_INT3BIT_CH_TABLE (RF_REG_BASE+0x00b0a060)
+#define ADR_GEMINIA_SYN_PFD_CHP_ (RF_REG_BASE+0x00b0a064)
+#define ADR_GEMINIA_SYN_LPF (RF_REG_BASE+0x00b0a068)
+#define ADR_GEMINIA_SYN_VCO (RF_REG_BASE+0x00b0a06c)
+#define ADR_GEMINIA_SYN_VCOBF (RF_REG_BASE+0x00b0a070)
+#define ADR_GEMINIA_SYN_DIV_SDM (RF_REG_BASE+0x00b0a074)
+#define ADR_GEMINIA_SYN_SBCAL (RF_REG_BASE+0x00b0a078)
+#define ADR_GEMINIA_SYN_AAC (RF_REG_BASE+0x00b0a07c)
+#define ADR_GEMINIA_SYN_TTL (RF_REG_BASE+0x00b0a080)
+#define ADR_GEMINIA_DPLL_TOP_REGISTER (RF_REG_BASE+0x00b0a084)
+#define ADR_GEMINIA_DPLL_CKT_REGISTER (RF_REG_BASE+0x00b0a088)
+#define ADR_GEMINIA_DPLL_FB_DIVISION_REGISTERS (RF_REG_BASE+0x00b0a08c)
+#define ADR_GEMINIA_WF_DCOC_IDAC_REGISTER1 (RF_REG_BASE+0x00b0a090)
+#define ADR_GEMINIA_WF_DCOC_IDAC_REGISTER2 (RF_REG_BASE+0x00b0a094)
+#define ADR_GEMINIA_WF_DCOC_IDAC_REGISTER3 (RF_REG_BASE+0x00b0a098)
+#define ADR_GEMINIA_WF_DCOC_IDAC_REGISTER4 (RF_REG_BASE+0x00b0a09c)
+#define ADR_GEMINIA_WF_DCOC_IDAC_REGISTER5 (RF_REG_BASE+0x00b0a0a0)
+#define ADR_GEMINIA_WF_DCOC_IDAC_REGISTER6 (RF_REG_BASE+0x00b0a0a4)
+#define ADR_GEMINIA_WF_DCOC_IDAC_REGISTER7 (RF_REG_BASE+0x00b0a0a8)
+#define ADR_GEMINIA_WF_DCOC_IDAC_REGISTER8 (RF_REG_BASE+0x00b0a0ac)
+#define ADR_GEMINIA_WF_DCOC_IDAC_REGISTER9 (RF_REG_BASE+0x00b0a0b0)
+#define ADR_GEMINIA_WF_DCOC_IDAC_REGISTER10 (RF_REG_BASE+0x00b0a0b4)
+#define ADR_GEMINIA_WF_DCOC_IDAC_REGISTER11 (RF_REG_BASE+0x00b0a0b8)
+#define ADR_GEMINIA_WF_DCOC_IDAC_REGISTER12 (RF_REG_BASE+0x00b0a0bc)
+#define ADR_GEMINIA_WF_DCOC_IDAC_REGISTER13 (RF_REG_BASE+0x00b0a0c0)
+#define ADR_GEMINIA_WF_DCOC_IDAC_REGISTER14 (RF_REG_BASE+0x00b0a0c4)
+#define ADR_GEMINIA_WF_DCOC_IDAC_REGISTER15 (RF_REG_BASE+0x00b0a0c8)
+#define ADR_GEMINIA_WF_DCOC_IDAC_REGISTER16 (RF_REG_BASE+0x00b0a0cc)
+#define ADR_GEMINIA_WF_DCOC_IDAC_REGISTER17 (RF_REG_BASE+0x00b0a0d0)
+#define ADR_GEMINIA_WF_DCOC_IDAC_REGISTER18 (RF_REG_BASE+0x00b0a0d4)
+#define ADR_GEMINIA_WF_DCOC_IDAC_REGISTER19 (RF_REG_BASE+0x00b0a0d8)
+#define ADR_GEMINIA_WF_DCOC_IDAC_REGISTER20 (RF_REG_BASE+0x00b0a0dc)
+#define ADR_GEMINIA_WF_DCOC_IDAC_REGISTER21 (RF_REG_BASE+0x00b0a0e0)
+#define ADR_GEMINIA_WF_DCOC_IDAC_REGISTER22 (RF_REG_BASE+0x00b0a0e4)
+#define ADR_GEMINIA_BT_DCOC_IDAC_REGISTER1 (RF_REG_BASE+0x00b0a0e8)
+#define ADR_GEMINIA_BT_DCOC_IDAC_REGISTER2 (RF_REG_BASE+0x00b0a0ec)
+#define ADR_GEMINIA_BT_DCOC_IDAC_REGISTER3 (RF_REG_BASE+0x00b0a0f0)
+#define ADR_GEMINIA_BT_DCOC_IDAC_REGISTER4 (RF_REG_BASE+0x00b0a0f4)
+#define ADR_GEMINIA_BT_DCOC_IDAC_REGISTER5 (RF_REG_BASE+0x00b0a0f8)
+#define ADR_GEMINIA_BT_DCOC_IDAC_REGISTER6 (RF_REG_BASE+0x00b0a0fc)
+#define ADR_GEMINIA_BT_DCOC_IDAC_REGISTER7 (RF_REG_BASE+0x00b0a100)
+#define ADR_GEMINIA_BT_DCOC_IDAC_REGISTER8 (RF_REG_BASE+0x00b0a104)
+#define ADR_GEMINIA_BT_DCOC_IDAC_REGISTER9 (RF_REG_BASE+0x00b0a108)
+#define ADR_GEMINIA_BT_DCOC_IDAC_REGISTER10 (RF_REG_BASE+0x00b0a10c)
+#define ADR_GEMINIA_BT_DCOC_IDAC_REGISTER11 (RF_REG_BASE+0x00b0a110)
+#define ADR_GEMINIA_BT_DCOC_IDAC_REGISTER12 (RF_REG_BASE+0x00b0a114)
+#define ADR_GEMINIA_BT_DCOC_IDAC_REGISTER13 (RF_REG_BASE+0x00b0a118)
+#define ADR_GEMINIA_BT_DCOC_IDAC_REGISTER14 (RF_REG_BASE+0x00b0a11c)
+#define ADR_GEMINIA_BT_DCOC_IDAC_REGISTER15 (RF_REG_BASE+0x00b0a120)
+#define ADR_GEMINIA_BT_DCOC_IDAC_REGISTER16 (RF_REG_BASE+0x00b0a124)
+#define ADR_GEMINIA_MODE_DECODER_TIMER_REGISTER1 (RF_REG_BASE+0x00b0a128)
+#define ADR_GEMINIA_WIFI_T2R_TIMER_REGISTER (RF_REG_BASE+0x00b0a12c)
+#define ADR_GEMINIA_WIFI_R2T_TIMER_REGISTER (RF_REG_BASE+0x00b0a130)
+#define ADR_GEMINIA_CALIBRATION_TIMER_REGISTER (RF_REG_BASE+0x00b0a134)
+#define ADR_GEMINIA_CALIBRATION_GAIN_REGISTER0 (RF_REG_BASE+0x00b0a138)
+#define ADR_GEMINIA_CALIBRATION_GAIN_REGISTER1 (RF_REG_BASE+0x00b0a13c)
+#define ADR_GEMINIA_TRX_DUMMY_REGISTER (RF_REG_BASE+0x00b0a140)
+#define ADR_GEMINIA_SX_DUMMY_REGISTER (RF_REG_BASE+0x00b0a144)
+#define ADR_GEMINIA_READ_ONLY_FLAGS_ADC (RF_REG_BASE+0x00b0a148)
+#define ADR_GEMINIA_READ_ONLY_FLAGS_SX1 (RF_REG_BASE+0x00b0a14c)
+#define ADR_GEMINIA_READ_ONLY_FLAGS_SX2 (RF_REG_BASE+0x00b0a150)
+#define ADR_GEMINIA_DIGITAL_ADD_ON_R0 (RF_REG_BASE+0x00b0a540)
+#define ADR_GEMINIA_DIGITAL_ADD_ON_R1 (RF_REG_BASE+0x00b0a544)
+#define ADR_GEMINIA_DIGITAL_ADD_ON_R2 (RF_REG_BASE+0x00b0a548)
+#define ADR_GEMINIA_DIGITAL_ADD_ON_R3 (RF_REG_BASE+0x00b0a54c)
+#define ADR_GEMINIA_DIGITAL_ADD_ON_R4 (RF_REG_BASE+0x00b0a550)
+#define ADR_GEMINIA_DIGITAL_ADD_ON_R5 (RF_REG_BASE+0x00b0a554)
+#define ADR_GEMINIA_DIGITAL_ADD_ON_R6 (RF_REG_BASE+0x00b0a558)
+#define ADR_GEMINIA_TX_UP8X_COEF_R0 (RF_REG_BASE+0x00b0a55c)
+#define ADR_GEMINIA_TX_UP8X_COEF_R1 (RF_REG_BASE+0x00b0a560)
+#define ADR_GEMINIA_TX_UP8X_COEF_R2 (RF_REG_BASE+0x00b0a564)
+#define ADR_GEMINIA_TX_UP8X_COEF_R3 (RF_REG_BASE+0x00b0a568)
+#define ADR_GEMINIA_TX_UP8X_COEF_R4 (RF_REG_BASE+0x00b0a56c)
+#define ADR_GEMINIA_TX_UP8X_COEF_R5 (RF_REG_BASE+0x00b0a570)
+#define ADR_GEMINIA_RF_D_CAL_TOP_R0 (RF_REG_BASE+0x00b0a574)
+#define ADR_GEMINIA_RF_D_CAL_TOP_R1 (RF_REG_BASE+0x00b0a578)
+#define ADR_GEMINIA_RF_D_CAL_TOP_R2 (RF_REG_BASE+0x00b0a57c)
+#define ADR_GEMINIA_RF_D_CAL_TOP_R3 (RF_REG_BASE+0x00b0a580)
+#define ADR_GEMINIA_PMU_REG_1 (RF_REG_BASE+0x00b0b000)
+#define ADR_GEMINIA_PMU_REG_2 (RF_REG_BASE+0x00b0b004)
+#define ADR_GEMINIA_PMU_REG_3 (RF_REG_BASE+0x00b0b008)
+#define ADR_GEMINIA_PMU_REG_4 (RF_REG_BASE+0x00b0b00c)
+#define ADR_GEMINIA_PMU_REG_5 (RF_REG_BASE+0x00b0b010)
+#define ADR_GEMINIA_PMU_REG_6 (RF_REG_BASE+0x00b0b014)
+#define ADR_GEMINIA_PMU_BT_CLK (RF_REG_BASE+0x00b0b018)
+#define ADR_GEMINIA_PMU_SLEEP_REG (RF_REG_BASE+0x00b0b01c)
+#define ADR_GEMINIA_PMU_RTC_REG_0 (RF_REG_BASE+0x00b0b020)
+#define ADR_GEMINIA_PMU_RTC_REG_1 (RF_REG_BASE+0x00b0b024)
+#define ADR_GEMINIA_PMU_RTC_REG_2 (RF_REG_BASE+0x00b0b028)
+#define ADR_GEMINIA_PMU_RTC_REG_3 (RF_REG_BASE+0x00b0b02c)
+#define ADR_GEMINIA_PMU_FDB_REG_0 (RF_REG_BASE+0x00b0b040)
+#define ADR_GEMINIA_IO_REG_0 (RF_REG_BASE+0x00b0b060)
+#define ADR_GEMINIA_IO_REG_1 (RF_REG_BASE+0x00b0b064)
+#define ADR_GEMINIA_IO_REG_2 (RF_REG_BASE+0x00b0b068)
+#define ADR_GEMINIA_MCU_REG_0 (RF_REG_BASE+0x00b0b06c)
+#define ADR_GEMINIA_PMU_RAM_00 (RF_REG_BASE+0x00b0b080)
+#define ADR_GEMINIA_PMU_RAM_01 (RF_REG_BASE+0x00b0b084)
+#define ADR_GEMINIA_PMU_RAM_02 (RF_REG_BASE+0x00b0b088)
+#define ADR_GEMINIA_PMU_RAM_03 (RF_REG_BASE+0x00b0b08c)
+#define ADR_GEMINIA_PMU_RAM_04 (RF_REG_BASE+0x00b0b090)
+#define ADR_GEMINIA_PMU_RAM_05 (RF_REG_BASE+0x00b0b094)
+#define ADR_GEMINIA_PMU_RAM_06 (RF_REG_BASE+0x00b0b098)
+#define ADR_GEMINIA_PMU_RAM_07 (RF_REG_BASE+0x00b0b09c)
+#define ADR_GEMINIA_PMU_RAM_08 (RF_REG_BASE+0x00b0b0a0)
+#define ADR_GEMINIA_PMU_RAM_09 (RF_REG_BASE+0x00b0b0a4)
+#define ADR_GEMINIA_PMU_RAM_10 (RF_REG_BASE+0x00b0b0a8)
+#define ADR_GEMINIA_PMU_RAM_11 (RF_REG_BASE+0x00b0b0ac)
+#define ADR_GEMINIA_PMU_RAM_12 (RF_REG_BASE+0x00b0b0b0)
+#define ADR_GEMINIA_PMU_RAM_13 (RF_REG_BASE+0x00b0b0b4)
+#define ADR_GEMINIA_PMU_RAM_14 (RF_REG_BASE+0x00b0b0b8)
+#define ADR_GEMINIA_PMU_RAM_15 (RF_REG_BASE+0x00b0b0bc)
+#define ADR_GEMINIA_PMU_RAM_16 (RF_REG_BASE+0x00b0b0c0)
+#define ADR_GEMINIA_PMU_RAM_17 (RF_REG_BASE+0x00b0b0c4)
+#define ADR_GEMINIA_PMU_RAM_18 (RF_REG_BASE+0x00b0b0c8)
+#define ADR_GEMINIA_PMU_RAM_19 (RF_REG_BASE+0x00b0b0cc)
+#define ADR_GEMINIA_PMU_RAM_20 (RF_REG_BASE+0x00b0b0d0)
+#define ADR_GEMINIA_PMU_RAM_21 (RF_REG_BASE+0x00b0b0d4)
+#define ADR_GEMINIA_PMU_RAM_22 (RF_REG_BASE+0x00b0b0d8)
+#define ADR_GEMINIA_PMU_RAM_23 (RF_REG_BASE+0x00b0b0dc)
+#define ADR_GEMINIA_PMU_RAM_24 (RF_REG_BASE+0x00b0b0e0)
+#define ADR_GEMINIA_PMU_RAM_25 (RF_REG_BASE+0x00b0b0e4)
+#define ADR_GEMINIA_PMU_RAM_26 (RF_REG_BASE+0x00b0b0e8)
+#define ADR_GEMINIA_PMU_RAM_27 (RF_REG_BASE+0x00b0b0ec)
+#define ADR_GEMINIA_PMU_RAM_28 (RF_REG_BASE+0x00b0b0f0)
+#define ADR_GEMINIA_PMU_RAM_29 (RF_REG_BASE+0x00b0b0f4)
+#define ADR_GEMINIA_PMU_RAM_30 (RF_REG_BASE+0x00b0b0f8)
+#define ADR_GEMINIA_PMU_RAM_31 (RF_REG_BASE+0x00b0b0fc)
+#define ADR_TURISMO_TRX_MODE_REGISTER (RF_REG_BASE+0x00c0a400)
+#define ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER (RF_REG_BASE+0x00c0a404)
+#define ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER (RF_REG_BASE+0x00c0a408)
+#define ADR_TURISMO_TRX_2_4G_LDO_REGISTER (RF_REG_BASE+0x00c0a40c)
+#define ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER (RF_REG_BASE+0x00c0a410)
+#define ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER (RF_REG_BASE+0x00c0a414)
+#define ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER (RF_REG_BASE+0x00c0a418)
+#define ADR_TURISMO_TRX_2_4G_RX_REGISTER (RF_REG_BASE+0x00c0a41c)
+#define ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER (RF_REG_BASE+0x00c0a420)
+#define ADR_TURISMO_TRX_2_4G_TX_PA_REGISTER (RF_REG_BASE+0x00c0a424)
+#define ADR_TURISMO_TRX_2_4G_TX_REGISTER (RF_REG_BASE+0x00c0a428)
+#define ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER (RF_REG_BASE+0x00c0a42c)
+#define ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER (RF_REG_BASE+0x00c0a430)
+#define ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER (RF_REG_BASE+0x00c0a434)
+#define ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER (RF_REG_BASE+0x00c0a438)
+#define ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER (RF_REG_BASE+0x00c0a43c)
+#define ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER (RF_REG_BASE+0x00c0a440)
+#define ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER (RF_REG_BASE+0x00c0a444)
+#define ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER (RF_REG_BASE+0x00c0a448)
+#define ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER (RF_REG_BASE+0x00c0a44c)
+#define ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER (RF_REG_BASE+0x00c0a450)
+#define ADR_TURISMO_TRX_BT_TX_DAC_REGISTER (RF_REG_BASE+0x00c0a454)
+#define ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER (RF_REG_BASE+0x00c0a458)
+#define ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER (RF_REG_BASE+0x00c0a45c)
+#define ADR_TURISMO_TRX_SX_2_4GB_FRACTIONAL_AND_INTEGER_8BITS (RF_REG_BASE+0x00c0a460)
+#define ADR_TURISMO_TRX_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE (RF_REG_BASE+0x00c0a464)
+#define ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_ (RF_REG_BASE+0x00c0a468)
+#define ADR_TURISMO_TRX_SX_2_4GB_LPF (RF_REG_BASE+0x00c0a46c)
+#define ADR_TURISMO_TRX_SX_2_4GB_VCO (RF_REG_BASE+0x00c0a470)
+#define ADR_TURISMO_TRX_SX_2_4GB_VCOBF (RF_REG_BASE+0x00c0a474)
+#define ADR_TURISMO_TRX_SX_2_4GB_DIV_SDM (RF_REG_BASE+0x00c0a478)
+#define ADR_TURISMO_TRX_SX_2_4GB_SBCAL (RF_REG_BASE+0x00c0a47c)
+#define ADR_TURISMO_TRX_SX_2_4GB_AAC (RF_REG_BASE+0x00c0a480)
+#define ADR_TURISMO_TRX_SX_2_4GB_TTL (RF_REG_BASE+0x00c0a484)
+#define ADR_TURISMO_TRX_DPLL_TOP_REGISTER (RF_REG_BASE+0x00c0a488)
+#define ADR_TURISMO_TRX_DPLL_CKT_REGISTER (RF_REG_BASE+0x00c0a48c)
+#define ADR_TURISMO_TRX_DPLL_FB_DIVISION__REGISTERS (RF_REG_BASE+0x00c0a490)
+#define ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER1 (RF_REG_BASE+0x00c0a494)
+#define ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER2 (RF_REG_BASE+0x00c0a498)
+#define ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER3 (RF_REG_BASE+0x00c0a49c)
+#define ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER4 (RF_REG_BASE+0x00c0a4a0)
+#define ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER5 (RF_REG_BASE+0x00c0a4a4)
+#define ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER6 (RF_REG_BASE+0x00c0a4a8)
+#define ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER7 (RF_REG_BASE+0x00c0a4ac)
+#define ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER8 (RF_REG_BASE+0x00c0a4b0)
+#define ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER9 (RF_REG_BASE+0x00c0a4b4)
+#define ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER10 (RF_REG_BASE+0x00c0a4b8)
+#define ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER11 (RF_REG_BASE+0x00c0a4bc)
+#define ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER12 (RF_REG_BASE+0x00c0a4c0)
+#define ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER13 (RF_REG_BASE+0x00c0a4c4)
+#define ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER14 (RF_REG_BASE+0x00c0a4c8)
+#define ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER15 (RF_REG_BASE+0x00c0a4cc)
+#define ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER16 (RF_REG_BASE+0x00c0a4d0)
+#define ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER17 (RF_REG_BASE+0x00c0a4d4)
+#define ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER18 (RF_REG_BASE+0x00c0a4d8)
+#define ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER19 (RF_REG_BASE+0x00c0a4dc)
+#define ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER20 (RF_REG_BASE+0x00c0a4e0)
+#define ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER21 (RF_REG_BASE+0x00c0a4e4)
+#define ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER1 (RF_REG_BASE+0x00c0a4e8)
+#define ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER2 (RF_REG_BASE+0x00c0a4ec)
+#define ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER3 (RF_REG_BASE+0x00c0a4f0)
+#define ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER4 (RF_REG_BASE+0x00c0a4f4)
+#define ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER5 (RF_REG_BASE+0x00c0a4f8)
+#define ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER6 (RF_REG_BASE+0x00c0a4fc)
+#define ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER7 (RF_REG_BASE+0x00c0a500)
+#define ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER8 (RF_REG_BASE+0x00c0a504)
+#define ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER9 (RF_REG_BASE+0x00c0a508)
+#define ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER10 (RF_REG_BASE+0x00c0a50c)
+#define ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER11 (RF_REG_BASE+0x00c0a510)
+#define ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER12 (RF_REG_BASE+0x00c0a514)
+#define ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER13 (RF_REG_BASE+0x00c0a518)
+#define ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER14 (RF_REG_BASE+0x00c0a51c)
+#define ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER15 (RF_REG_BASE+0x00c0a520)
+#define ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER16 (RF_REG_BASE+0x00c0a524)
+#define ADR_TURISMO_TRX_MODE_DECODER_TIMER_REGISTER1 (RF_REG_BASE+0x00c0a528)
+#define ADR_TURISMO_TRX_WIFI_T2R_TIMER_REGISTER (RF_REG_BASE+0x00c0a52c)
+#define ADR_TURISMO_TRX_WIFI_R2T_TIMER_REGISTER (RF_REG_BASE+0x00c0a530)
+#define ADR_TURISMO_TRX_CALIBRATION_TIMER_REGISTER (RF_REG_BASE+0x00c0a534)
+#define ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER0 (RF_REG_BASE+0x00c0a538)
+#define ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1 (RF_REG_BASE+0x00c0a53c)
+#define ADR_TURISMO_TRX_2_4G_TRX_DUMMY_REGISTER (RF_REG_BASE+0x00c0a540)
+#define ADR_TURISMO_TRX_READ_ONLY_FLAGS_ADC (RF_REG_BASE+0x00c0a544)
+#define ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_1 (RF_REG_BASE+0x00c0a548)
+#define ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_2 (RF_REG_BASE+0x00c0a54c)
+#define ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER (RF_REG_BASE+0x00c0a550)
+#define ADR_TURISMO_TRX_5G_LDO_REGISTER (RF_REG_BASE+0x00c0a554)
+#define ADR_TURISMO_TRX_5G_RX_REGISTER1 (RF_REG_BASE+0x00c0a558)
+#define ADR_TURISMO_TRX_5G_RX_REGISTER2 (RF_REG_BASE+0x00c0a55c)
+#define ADR_TURISMO_TRX_5G_TX_FE_REGISTER (RF_REG_BASE+0x00c0a560)
+#define ADR_TURISMO_TRX_5G_TX_REGISTER (RF_REG_BASE+0x00c0a564)
+#define ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER (RF_REG_BASE+0x00c0a568)
+#define ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER (RF_REG_BASE+0x00c0a56c)
+#define ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER (RF_REG_BASE+0x00c0a570)
+#define ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER (RF_REG_BASE+0x00c0a574)
+#define ADR_TURISMO_TRX_5G_TX_DAC_REGISTER (RF_REG_BASE+0x00c0a578)
+#define ADR_TURISMO_TRX_SX_5GB_FRACTIONAL_AND_INTEGER_8BITS (RF_REG_BASE+0x00c0a57c)
+#define ADR_TURISMO_TRX_SX_5GB_REGISTER_INT3BIT___CH_TABLE (RF_REG_BASE+0x00c0a580)
+#define ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER (RF_REG_BASE+0x00c0a584)
+#define ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER (RF_REG_BASE+0x00c0a588)
+#define ADR_TURISMO_TRX_SX_5GB_PFD_CHP_ (RF_REG_BASE+0x00c0a58c)
+#define ADR_TURISMO_TRX_SX_5GB_LPF_TTL (RF_REG_BASE+0x00c0a590)
+#define ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN (RF_REG_BASE+0x00c0a594)
+#define ADR_TURISMO_TRX_SX_5GB_DIV_SDM (RF_REG_BASE+0x00c0a598)
+#define ADR_TURISMO_TRX_SX_5GB_SBCAL (RF_REG_BASE+0x00c0a59c)
+#define ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION (RF_REG_BASE+0x00c0a5a0)
+#define ADR_TURISMO_TRX_SX_5GB_LOGEN_CALIBRATION (RF_REG_BASE+0x00c0a5a4)
+#define ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER1 (RF_REG_BASE+0x00c0a5a8)
+#define ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER2 (RF_REG_BASE+0x00c0a5ac)
+#define ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER3 (RF_REG_BASE+0x00c0a5b0)
+#define ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER4 (RF_REG_BASE+0x00c0a5b4)
+#define ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER5 (RF_REG_BASE+0x00c0a5b8)
+#define ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER6 (RF_REG_BASE+0x00c0a5bc)
+#define ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER7 (RF_REG_BASE+0x00c0a5c0)
+#define ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER8 (RF_REG_BASE+0x00c0a5c4)
+#define ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER9 (RF_REG_BASE+0x00c0a5c8)
+#define ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER10 (RF_REG_BASE+0x00c0a5cc)
+#define ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER11 (RF_REG_BASE+0x00c0a5d0)
+#define ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER12 (RF_REG_BASE+0x00c0a5d4)
+#define ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER13 (RF_REG_BASE+0x00c0a5d8)
+#define ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER14 (RF_REG_BASE+0x00c0a5dc)
+#define ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER15 (RF_REG_BASE+0x00c0a5e0)
+#define ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER16 (RF_REG_BASE+0x00c0a5e4)
+#define ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER17 (RF_REG_BASE+0x00c0a5e8)
+#define ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER18 (RF_REG_BASE+0x00c0a5ec)
+#define ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER19 (RF_REG_BASE+0x00c0a5f0)
+#define ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER20 (RF_REG_BASE+0x00c0a5f4)
+#define ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER21 (RF_REG_BASE+0x00c0a5f8)
+#define ADR_TURISMO_TRX_5G_MODE_DECODER_TIMER_REGISTER1 (RF_REG_BASE+0x00c0a5fc)
+#define ADR_TURISMO_TRX_5G_T2R_TIMER_REGISTER (RF_REG_BASE+0x00c0a600)
+#define ADR_TURISMO_TRX_5G_R2T_TIMER_REGISTER (RF_REG_BASE+0x00c0a604)
+#define ADR_TURISMO_TRX_5G_CALIBRATION_TIMER_GAIN_REGISTER (RF_REG_BASE+0x00c0a608)
+#define ADR_TURISMO_TRX_5G_CALIBRATION_GAIN_REGISTER1 (RF_REG_BASE+0x00c0a60c)
+#define ADR_TURISMO_TRX_5G_TRX_DUMMY_REGISTER (RF_REG_BASE+0x00c0a610)
+#define ADR_TURISMO_TRX_SX_5GB_DUMMY_REGISTER (RF_REG_BASE+0x00c0a614)
+#define ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_1 (RF_REG_BASE+0x00c0a618)
+#define ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_2 (RF_REG_BASE+0x00c0a61c)
+#define ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_3 (RF_REG_BASE+0x00c0a620)
+#define ADR_TURISMO_TRX_5G_RX_LNA_MATCHING_SCA_CONTROL (RF_REG_BASE+0x00c0a624)
+#define ADR_TURISMO_TRX_5G_RX_LNA_LOAD_SCA_CONTROL (RF_REG_BASE+0x00c0a628)
+#define ADR_TURISMO_TRX_5G_TX_PGA_CAPSW_CONTROL (RF_REG_BASE+0x00c0a62c)
+#define ADR_TURISMO_TRX_DIGITAL_ADD_ON_0 (RF_REG_BASE+0x00c0a800)
+#define ADR_TURISMO_TRX_DIGITAL_ADD_ON_1 (RF_REG_BASE+0x00c0a804)
+#define ADR_TURISMO_TRX_DIGITAL_ADD_ON_2 (RF_REG_BASE+0x00c0a808)
+#define ADR_TURISMO_TRX_DIGITAL_ADD_ON_3 (RF_REG_BASE+0x00c0a80c)
+#define ADR_TURISMO_TRX_DIGITAL_ADD_ON_4 (RF_REG_BASE+0x00c0a810)
+#define ADR_TURISMO_TRX_DIGITAL_ADD_ON_5 (RF_REG_BASE+0x00c0a814)
+#define ADR_TURISMO_TRX_DIGITAL_ADD_ON_6 (RF_REG_BASE+0x00c0a818)
+#define ADR_TURISMO_TRX_TX_BW20_FIR_COEF_00 (RF_REG_BASE+0x00c0a81c)
+#define ADR_TURISMO_TRX_TX_BW20_FIR_COEF_01 (RF_REG_BASE+0x00c0a820)
+#define ADR_TURISMO_TRX_TX_BW20_FIR_COEF_02 (RF_REG_BASE+0x00c0a824)
+#define ADR_TURISMO_TRX_TX_BW20_FIR_COEF_03 (RF_REG_BASE+0x00c0a828)
+#define ADR_TURISMO_TRX_TX_BW20_FIR_COEF_04 (RF_REG_BASE+0x00c0a82c)
+#define ADR_TURISMO_TRX_TX_BW20_FIR_COEF_05 (RF_REG_BASE+0x00c0a830)
+#define ADR_TURISMO_TRX_RF_D_CAL_TOP_0 (RF_REG_BASE+0x00c0a834)
+#define ADR_TURISMO_TRX_RF_D_CAL_TOP_1 (RF_REG_BASE+0x00c0a838)
+#define ADR_TURISMO_TRX_RF_D_CAL_TOP_2 (RF_REG_BASE+0x00c0a83c)
+#define ADR_TURISMO_TRX_RF_D_CAL_TOP_3 (RF_REG_BASE+0x00c0a840)
+#define ADR_TURISMO_TRX_RF_D_CAL_TOP_4 (RF_REG_BASE+0x00c0a844)
+#define ADR_TURISMO_TRX_RF_D_CAL_TOP_5 (RF_REG_BASE+0x00c0a848)
+#define ADR_TURISMO_TRX_RF_D_CAL_TOP_6 (RF_REG_BASE+0x00c0a84c)
+#define ADR_TURISMO_TRX_RF_D_CAL_TOP_7 (RF_REG_BASE+0x00c0a850)
+#define ADR_TURISMO_TRX_RF_D_CAL_TOP_8 (RF_REG_BASE+0x00c0a854)
+#define ADR_TURISMO_TRX_RF_D_CAL_TOP_9 (RF_REG_BASE+0x00c0a858)
+#define ADR_TURISMO_TRX_HS3W_CTRL1 (RF_REG_BASE+0x00c0a880)
+#define ADR_TURISMO_TRX_HS3W_CTRL2 (RF_REG_BASE+0x00c0a884)
+#define ADR_TURISMO_TRX_HS3W_CTRL3 (RF_REG_BASE+0x00c0a888)
+#define ADR_TURISMO_TRX_RF_D_MODE_CTRL (RF_REG_BASE+0x00c0a88c)
+#define ADR_TURISMO_TRX_RX_DC_CAL_RESULT (RF_REG_BASE+0x00c0a8c0)
+#define ADR_TURISMO_TRX_PMU_REG_1 (RF_REG_BASE+0x00c0b000)
+#define ADR_TURISMO_TRX_PMU_REG_2 (RF_REG_BASE+0x00c0b004)
+#define ADR_TURISMO_TRX_PMU_REG_3 (RF_REG_BASE+0x00c0b008)
+#define ADR_TURISMO_TRX_PMU_REG_4 (RF_REG_BASE+0x00c0b00c)
+#define ADR_TURISMO_TRX_PMU_REG_5 (RF_REG_BASE+0x00c0b010)
+#define ADR_TURISMO_TRX_PMU_REG_6 (RF_REG_BASE+0x00c0b014)
+#define ADR_TURISMO_TRX_PMU_SLEEP_REG_1 (RF_REG_BASE+0x00c0b018)
+#define ADR_TURISMO_TRX_PMU_SLEEP_REG_2 (RF_REG_BASE+0x00c0b01c)
+#define ADR_TURISMO_TRX_PMU_RTC_REG_0 (RF_REG_BASE+0x00c0b020)
+#define ADR_TURISMO_TRX_PMU_RTC_REG_1 (RF_REG_BASE+0x00c0b024)
+#define ADR_TURISMO_TRX_PMU_RTC_REG_2 (RF_REG_BASE+0x00c0b028)
+#define ADR_TURISMO_TRX_PMU_RTC_REG_3 (RF_REG_BASE+0x00c0b02c)
+#define ADR_TURISMO_TRX_PMU_CTRL_REG (RF_REG_BASE+0x00c0b03c)
+#define ADR_TURISMO_TRX_PMU_STATE_REG (RF_REG_BASE+0x00c0b044)
+#define ADR_TURISMO_TRX_PMU_BT_CLK (RF_REG_BASE+0x00c0b048)
+#define ADR_TURISMO_TRX_IO_REG_0 (RF_REG_BASE+0x00c0b060)
+#define ADR_TURISMO_TRX_IO_REG_1 (RF_REG_BASE+0x00c0b064)
+#define ADR_TURISMO_TRX_IO_REG_2 (RF_REG_BASE+0x00c0b068)
+#define ADR_TURISMO_TRX_MCU_REG_0 (RF_REG_BASE+0x00c0b06c)
+#define ADR_TURISMO_TRX_PMU_RAM_00 (RF_REG_BASE+0x00c0b080)
+#define ADR_TURISMO_TRX_PMU_RAM_01 (RF_REG_BASE+0x00c0b084)
+#define ADR_TURISMO_TRX_PMU_RAM_02 (RF_REG_BASE+0x00c0b088)
+#define ADR_TURISMO_TRX_PMU_RAM_03 (RF_REG_BASE+0x00c0b08c)
+#define ADR_TURISMO_TRX_PMU_RAM_04 (RF_REG_BASE+0x00c0b090)
+#define ADR_TURISMO_TRX_PMU_RAM_05 (RF_REG_BASE+0x00c0b094)
+#define ADR_TURISMO_TRX_PMU_RAM_06 (RF_REG_BASE+0x00c0b098)
+#define ADR_TURISMO_TRX_PMU_RAM_07 (RF_REG_BASE+0x00c0b09c)
+#define ADR_TURISMO_TRX_PMU_RAM_08 (RF_REG_BASE+0x00c0b0a0)
+#define ADR_TURISMO_TRX_PMU_RAM_09 (RF_REG_BASE+0x00c0b0a4)
+#define ADR_TURISMO_TRX_PMU_RAM_10 (RF_REG_BASE+0x00c0b0a8)
+#define ADR_TURISMO_TRX_PMU_RAM_11 (RF_REG_BASE+0x00c0b0ac)
+#define ADR_TURISMO_TRX_PMU_RAM_12 (RF_REG_BASE+0x00c0b0b0)
+#define ADR_TURISMO_TRX_PMU_RAM_13 (RF_REG_BASE+0x00c0b0b4)
+#define ADR_TURISMO_TRX_PMU_RAM_14 (RF_REG_BASE+0x00c0b0b8)
+#define ADR_TURISMO_TRX_PMU_RAM_15 (RF_REG_BASE+0x00c0b0bc)
+#define ADR_TURISMO_TRX_PMU_RAM_16 (RF_REG_BASE+0x00c0b0c0)
+#define ADR_TURISMO_TRX_PMU_RAM_17 (RF_REG_BASE+0x00c0b0c4)
+#define ADR_TURISMO_TRX_PMU_RAM_18 (RF_REG_BASE+0x00c0b0c8)
+#define ADR_TURISMO_TRX_PMU_RAM_19 (RF_REG_BASE+0x00c0b0cc)
+#define ADR_TURISMO_TRX_PMU_RAM_20 (RF_REG_BASE+0x00c0b0d0)
+#define ADR_TURISMO_TRX_PMU_RAM_21 (RF_REG_BASE+0x00c0b0d4)
+#define ADR_TURISMO_TRX_PMU_RAM_22 (RF_REG_BASE+0x00c0b0d8)
+#define ADR_TURISMO_TRX_PMU_RAM_23 (RF_REG_BASE+0x00c0b0dc)
+#define ADR_TURISMO_TRX_PMU_RAM_24 (RF_REG_BASE+0x00c0b0e0)
+#define ADR_TURISMO_TRX_PMU_RAM_25 (RF_REG_BASE+0x00c0b0e4)
+#define ADR_TURISMO_TRX_PMU_RAM_26 (RF_REG_BASE+0x00c0b0e8)
+#define ADR_TURISMO_TRX_PMU_RAM_27 (RF_REG_BASE+0x00c0b0ec)
+#define ADR_TURISMO_TRX_PMU_RAM_28 (RF_REG_BASE+0x00c0b0f0)
+#define ADR_TURISMO_TRX_PMU_RAM_29 (RF_REG_BASE+0x00c0b0f4)
+#define ADR_TURISMO_TRX_PMU_RAM_30 (RF_REG_BASE+0x00c0b0f8)
+#define ADR_TURISMO_TRX_PMU_RAM_31 (RF_REG_BASE+0x00c0b0fc)
+#define ADR_MODE_REGISTER (CSR_TU_RF_BASE+0x00000400)
+#define ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER (CSR_TU_RF_BASE+0x00000404)
+#define ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER (CSR_TU_RF_BASE+0x00000408)
+#define ADR_2_4G_LDO_REGISTER (CSR_TU_RF_BASE+0x0000040c)
+#define ADR_WIFI_HT20_RX_FILTER_REGISTER (CSR_TU_RF_BASE+0x00000410)
+#define ADR_WIFI_HT40_RX_FILTER_REGISTER (CSR_TU_RF_BASE+0x00000414)
+#define ADR_BT_RX_FILTER_REGISTER (CSR_TU_RF_BASE+0x00000418)
+#define ADR_2_4G_RX_REGISTER (CSR_TU_RF_BASE+0x0000041c)
+#define ADR_2_4G_TX_FE_REGISTER (CSR_TU_RF_BASE+0x00000420)
+#define ADR_2_4G_TX_PA_REGISTER (CSR_TU_RF_BASE+0x00000424)
+#define ADR_2_4G_TX_REGISTER (CSR_TU_RF_BASE+0x00000428)
+#define ADR_2_4G_RX_FE_HG_REGISTER (CSR_TU_RF_BASE+0x0000042c)
+#define ADR_2_4G_RX_FE_MG_REGISTER (CSR_TU_RF_BASE+0x00000430)
+#define ADR_2_4G_RX_FE_LG_REGISTER (CSR_TU_RF_BASE+0x00000434)
+#define ADR_2_4G_RX_FE_ULG_REGISTER (CSR_TU_RF_BASE+0x00000438)
+#define ADR_BT_RX_FE_HG_REGISTER (CSR_TU_RF_BASE+0x0000043c)
+#define ADR_BT_RX_FE_MG_REGISTER (CSR_TU_RF_BASE+0x00000440)
+#define ADR_BT_RX_FE_LG_REGISTER (CSR_TU_RF_BASE+0x00000444)
+#define ADR_BT_RX_FE_ULG_REGISTER (CSR_TU_RF_BASE+0x00000448)
+#define ADR_WBT_RX_ADC_REGISTER (CSR_TU_RF_BASE+0x0000044c)
+#define ADR_WIFI_TX_DAC_REGISTER (CSR_TU_RF_BASE+0x00000450)
+#define ADR_BT_TX_DAC_REGISTER (CSR_TU_RF_BASE+0x00000454)
+#define ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER (CSR_TU_RF_BASE+0x00000458)
+#define ADR_SX_2_4G_LDO_REGISTER (CSR_TU_RF_BASE+0x0000045c)
+#define ADR_SX_2_4GB_FRACTIONAL_AND_INTEGER_8BITS (CSR_TU_RF_BASE+0x00000460)
+#define ADR_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE (CSR_TU_RF_BASE+0x00000464)
+#define ADR_SX_2_4GB_PFD_CHP_ (CSR_TU_RF_BASE+0x00000468)
+#define ADR_SX_2_4GB_LPF (CSR_TU_RF_BASE+0x0000046c)
+#define ADR_SX_2_4GB_VCO (CSR_TU_RF_BASE+0x00000470)
+#define ADR_SX_2_4GB_VCOBF (CSR_TU_RF_BASE+0x00000474)
+#define ADR_SX_2_4GB_DIV_SDM (CSR_TU_RF_BASE+0x00000478)
+#define ADR_SX_2_4GB_SBCAL (CSR_TU_RF_BASE+0x0000047c)
+#define ADR_SX_2_4GB_AAC (CSR_TU_RF_BASE+0x00000480)
+#define ADR_SX_2_4GB_TTL (CSR_TU_RF_BASE+0x00000484)
+#define ADR_DPLL_TOP_REGISTER (CSR_TU_RF_BASE+0x00000488)
+#define ADR_DPLL_CKT_REGISTER (CSR_TU_RF_BASE+0x0000048c)
+#define ADR_DPLL_FB_DIVISION__REGISTERS (CSR_TU_RF_BASE+0x00000490)
+#define ADR_WF_DCOC_IDAC_REGISTER1 (CSR_TU_RF_BASE+0x00000494)
+#define ADR_WF_DCOC_IDAC_REGISTER2 (CSR_TU_RF_BASE+0x00000498)
+#define ADR_WF_DCOC_IDAC_REGISTER3 (CSR_TU_RF_BASE+0x0000049c)
+#define ADR_WF_DCOC_IDAC_REGISTER4 (CSR_TU_RF_BASE+0x000004a0)
+#define ADR_WF_DCOC_IDAC_REGISTER5 (CSR_TU_RF_BASE+0x000004a4)
+#define ADR_WF_DCOC_IDAC_REGISTER6 (CSR_TU_RF_BASE+0x000004a8)
+#define ADR_WF_DCOC_IDAC_REGISTER7 (CSR_TU_RF_BASE+0x000004ac)
+#define ADR_WF_DCOC_IDAC_REGISTER8 (CSR_TU_RF_BASE+0x000004b0)
+#define ADR_WF_DCOC_IDAC_REGISTER9 (CSR_TU_RF_BASE+0x000004b4)
+#define ADR_WF_DCOC_IDAC_REGISTER10 (CSR_TU_RF_BASE+0x000004b8)
+#define ADR_WF_DCOC_IDAC_REGISTER11 (CSR_TU_RF_BASE+0x000004bc)
+#define ADR_WF_DCOC_IDAC_REGISTER12 (CSR_TU_RF_BASE+0x000004c0)
+#define ADR_WF_DCOC_IDAC_REGISTER13 (CSR_TU_RF_BASE+0x000004c4)
+#define ADR_WF_DCOC_IDAC_REGISTER14 (CSR_TU_RF_BASE+0x000004c8)
+#define ADR_WF_DCOC_IDAC_REGISTER15 (CSR_TU_RF_BASE+0x000004cc)
+#define ADR_WF_DCOC_IDAC_REGISTER16 (CSR_TU_RF_BASE+0x000004d0)
+#define ADR_WF_DCOC_IDAC_REGISTER17 (CSR_TU_RF_BASE+0x000004d4)
+#define ADR_WF_DCOC_IDAC_REGISTER18 (CSR_TU_RF_BASE+0x000004d8)
+#define ADR_WF_DCOC_IDAC_REGISTER19 (CSR_TU_RF_BASE+0x000004dc)
+#define ADR_WF_DCOC_IDAC_REGISTER20 (CSR_TU_RF_BASE+0x000004e0)
+#define ADR_WF_DCOC_IDAC_REGISTER21 (CSR_TU_RF_BASE+0x000004e4)
+#define ADR_BT_DCOC_IDAC_REGISTER1 (CSR_TU_RF_BASE+0x000004e8)
+#define ADR_BT_DCOC_IDAC_REGISTER2 (CSR_TU_RF_BASE+0x000004ec)
+#define ADR_BT_DCOC_IDAC_REGISTER3 (CSR_TU_RF_BASE+0x000004f0)
+#define ADR_BT_DCOC_IDAC_REGISTER4 (CSR_TU_RF_BASE+0x000004f4)
+#define ADR_BT_DCOC_IDAC_REGISTER5 (CSR_TU_RF_BASE+0x000004f8)
+#define ADR_BT_DCOC_IDAC_REGISTER6 (CSR_TU_RF_BASE+0x000004fc)
+#define ADR_BT_DCOC_IDAC_REGISTER7 (CSR_TU_RF_BASE+0x00000500)
+#define ADR_BT_DCOC_IDAC_REGISTER8 (CSR_TU_RF_BASE+0x00000504)
+#define ADR_BT_DCOC_IDAC_REGISTER9 (CSR_TU_RF_BASE+0x00000508)
+#define ADR_BT_DCOC_IDAC_REGISTER10 (CSR_TU_RF_BASE+0x0000050c)
+#define ADR_BT_DCOC_IDAC_REGISTER11 (CSR_TU_RF_BASE+0x00000510)
+#define ADR_BT_DCOC_IDAC_REGISTER12 (CSR_TU_RF_BASE+0x00000514)
+#define ADR_BT_DCOC_IDAC_REGISTER13 (CSR_TU_RF_BASE+0x00000518)
+#define ADR_BT_DCOC_IDAC_REGISTER14 (CSR_TU_RF_BASE+0x0000051c)
+#define ADR_BT_DCOC_IDAC_REGISTER15 (CSR_TU_RF_BASE+0x00000520)
+#define ADR_BT_DCOC_IDAC_REGISTER16 (CSR_TU_RF_BASE+0x00000524)
+#define ADR_MODE_DECODER_TIMER_REGISTER1 (CSR_TU_RF_BASE+0x00000528)
+#define ADR_WIFI_T2R_TIMER_REGISTER (CSR_TU_RF_BASE+0x0000052c)
+#define ADR_WIFI_R2T_TIMER_REGISTER (CSR_TU_RF_BASE+0x00000530)
+#define ADR_CALIBRATION_TIMER_REGISTER (CSR_TU_RF_BASE+0x00000534)
+#define ADR_CALIBRATION_GAIN_REGISTER0 (CSR_TU_RF_BASE+0x00000538)
+#define ADR_CALIBRATION_GAIN_REGISTER1 (CSR_TU_RF_BASE+0x0000053c)
+#define ADR_2_4G_TRX_DUMMY_REGISTER (CSR_TU_RF_BASE+0x00000540)
+#define ADR_READ_ONLY_FLAGS_ADC (CSR_TU_RF_BASE+0x00000544)
+#define ADR_READ_ONLY_FLAGS_SX_2_4GB_1 (CSR_TU_RF_BASE+0x00000548)
+#define ADR_READ_ONLY_FLAGS_SX_2_4GB_2 (CSR_TU_RF_BASE+0x0000054c)
+#define ADR_5G_TRX_MANUAL_ENABLE_REGISTER (CSR_TU_RF_BASE+0x00000550)
+#define ADR_5G_LDO_REGISTER (CSR_TU_RF_BASE+0x00000554)
+#define ADR_5G_RX_REGISTER1 (CSR_TU_RF_BASE+0x00000558)
+#define ADR_5G_RX_REGISTER2 (CSR_TU_RF_BASE+0x0000055c)
+#define ADR_5G_TX_FE_REGISTER (CSR_TU_RF_BASE+0x00000560)
+#define ADR_5G_TX_REGISTER (CSR_TU_RF_BASE+0x00000564)
+#define ADR_5G_RX_FE_HG_REGISTER (CSR_TU_RF_BASE+0x00000568)
+#define ADR_5G_RX_FE_MG_REGISTER (CSR_TU_RF_BASE+0x0000056c)
+#define ADR_5G_RX_FE_LG_REGISTER (CSR_TU_RF_BASE+0x00000570)
+#define ADR_5G_RX_FE_ULG_REGISTER (CSR_TU_RF_BASE+0x00000574)
+#define ADR_5G_TX_DAC_REGISTER (CSR_TU_RF_BASE+0x00000578)
+#define ADR_SX_5GB_FRACTIONAL_AND_INTEGER_8BITS (CSR_TU_RF_BASE+0x0000057c)
+#define ADR_SX_5GB_REGISTER_INT3BIT___CH_TABLE (CSR_TU_RF_BASE+0x00000580)
+#define ADR_SX_5GB_ENABLE_TOP_CONTROLLER (CSR_TU_RF_BASE+0x00000584)
+#define ADR_SX_5GB_LDO_REGISTER (CSR_TU_RF_BASE+0x00000588)
+#define ADR_SX_5GB_PFD_CHP_ (CSR_TU_RF_BASE+0x0000058c)
+#define ADR_SX_5GB_LPF_TTL (CSR_TU_RF_BASE+0x00000590)
+#define ADR_SX_5GB_VCO_LOGEN (CSR_TU_RF_BASE+0x00000594)
+#define ADR_SX_5GB_DIV_SDM (CSR_TU_RF_BASE+0x00000598)
+#define ADR_SX_5GB_SBCAL (CSR_TU_RF_BASE+0x0000059c)
+#define ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION (CSR_TU_RF_BASE+0x000005a0)
+#define ADR_SX_5GB_LOGEN_CALIBRATION (CSR_TU_RF_BASE+0x000005a4)
+#define ADR_5G_DCOC_IDAC_REGISTER1 (CSR_TU_RF_BASE+0x000005a8)
+#define ADR_5G_DCOC_IDAC_REGISTER2 (CSR_TU_RF_BASE+0x000005ac)
+#define ADR_5G_DCOC_IDAC_REGISTER3 (CSR_TU_RF_BASE+0x000005b0)
+#define ADR_5G_DCOC_IDAC_REGISTER4 (CSR_TU_RF_BASE+0x000005b4)
+#define ADR_5G_DCOC_IDAC_REGISTER5 (CSR_TU_RF_BASE+0x000005b8)
+#define ADR_5G_DCOC_IDAC_REGISTER6 (CSR_TU_RF_BASE+0x000005bc)
+#define ADR_5G_DCOC_IDAC_REGISTER7 (CSR_TU_RF_BASE+0x000005c0)
+#define ADR_5G_DCOC_IDAC_REGISTER8 (CSR_TU_RF_BASE+0x000005c4)
+#define ADR_5G_DCOC_IDAC_REGISTER9 (CSR_TU_RF_BASE+0x000005c8)
+#define ADR_5G_DCOC_IDAC_REGISTER10 (CSR_TU_RF_BASE+0x000005cc)
+#define ADR_5G_DCOC_IDAC_REGISTER11 (CSR_TU_RF_BASE+0x000005d0)
+#define ADR_5G_DCOC_IDAC_REGISTER12 (CSR_TU_RF_BASE+0x000005d4)
+#define ADR_5G_DCOC_IDAC_REGISTER13 (CSR_TU_RF_BASE+0x000005d8)
+#define ADR_5G_DCOC_IDAC_REGISTER14 (CSR_TU_RF_BASE+0x000005dc)
+#define ADR_5G_DCOC_IDAC_REGISTER15 (CSR_TU_RF_BASE+0x000005e0)
+#define ADR_5G_DCOC_IDAC_REGISTER16 (CSR_TU_RF_BASE+0x000005e4)
+#define ADR_5G_DCOC_IDAC_REGISTER17 (CSR_TU_RF_BASE+0x000005e8)
+#define ADR_5G_DCOC_IDAC_REGISTER18 (CSR_TU_RF_BASE+0x000005ec)
+#define ADR_5G_DCOC_IDAC_REGISTER19 (CSR_TU_RF_BASE+0x000005f0)
+#define ADR_5G_DCOC_IDAC_REGISTER20 (CSR_TU_RF_BASE+0x000005f4)
+#define ADR_5G_DCOC_IDAC_REGISTER21 (CSR_TU_RF_BASE+0x000005f8)
+#define ADR_5G_MODE_DECODER_TIMER_REGISTER1 (CSR_TU_RF_BASE+0x000005fc)
+#define ADR_5G_T2R_TIMER_REGISTER (CSR_TU_RF_BASE+0x00000600)
+#define ADR_5G_R2T_TIMER_REGISTER (CSR_TU_RF_BASE+0x00000604)
+#define ADR_5G_CALIBRATION_TIMER_GAIN_REGISTER (CSR_TU_RF_BASE+0x00000608)
+#define ADR_5G_CALIBRATION_GAIN_REGISTER1 (CSR_TU_RF_BASE+0x0000060c)
+#define ADR_5G_TRX_DUMMY_REGISTER (CSR_TU_RF_BASE+0x00000610)
+#define ADR_SX_5GB_DUMMY_REGISTER (CSR_TU_RF_BASE+0x00000614)
+#define ADR_READ_ONLY_FLAGS_SX_5GB_1 (CSR_TU_RF_BASE+0x00000618)
+#define ADR_READ_ONLY_FLAGS_SX_5GB_2 (CSR_TU_RF_BASE+0x0000061c)
+#define ADR_READ_ONLY_FLAGS_SX_5GB_3 (CSR_TU_RF_BASE+0x00000620)
+#define ADR_5G_RX_LNA_MATCHING_SCA_CONTROL (CSR_TU_RF_BASE+0x00000624)
+#define ADR_5G_RX_LNA_LOAD_SCA_CONTROL (CSR_TU_RF_BASE+0x00000628)
+#define ADR_5G_TX_PGA_CAPSW_CONTROL_I (CSR_TU_RF_BASE+0x0000062c)
+#define ADR_5G_TX_PGA_CAPSW_CONTROL_II (CSR_TU_RF_BASE+0x00000630)
+#define ADR_5G_TX_GAIN_PAFB_CONTROL (CSR_TU_RF_BASE+0x00000634)
+#define ADR_DIGITAL_ADD_ON_0 (CSR_TU_RF_BASE+0x00000800)
+#define ADR_DIGITAL_ADD_ON_1 (CSR_TU_RF_BASE+0x00000804)
+#define ADR_DIGITAL_ADD_ON_2 (CSR_TU_RF_BASE+0x00000808)
+#define ADR_DIGITAL_ADD_ON_3 (CSR_TU_RF_BASE+0x0000080c)
+#define ADR_DIGITAL_ADD_ON_4 (CSR_TU_RF_BASE+0x00000810)
+#define ADR_DIGITAL_ADD_ON_5 (CSR_TU_RF_BASE+0x00000814)
+#define ADR_DIGITAL_ADD_ON_6 (CSR_TU_RF_BASE+0x00000818)
+#define ADR_RX_RC_VALUE_TUNE (CSR_TU_RF_BASE+0x0000081c)
+#define ADR_TRX_IQ_COMP_2G (CSR_TU_RF_BASE+0x00000820)
+#define ADR_TRX_IQ_COMP_5G_0 (CSR_TU_RF_BASE+0x00000824)
+#define ADR_TRX_IQ_COMP_5G_1 (CSR_TU_RF_BASE+0x00000828)
+#define ADR_TRX_IQ_COMP_5G_2 (CSR_TU_RF_BASE+0x0000082c)
+#define ADR_TRX_IQ_COMP_5G_3 (CSR_TU_RF_BASE+0x00000830)
+#define ADR_RF_D_CAL_TOP_0 (CSR_TU_RF_BASE+0x00000834)
+#define ADR_RF_D_CAL_TOP_1 (CSR_TU_RF_BASE+0x00000838)
+#define ADR_RF_D_CAL_TOP_2 (CSR_TU_RF_BASE+0x0000083c)
+#define ADR_RF_D_CAL_TOP_3 (CSR_TU_RF_BASE+0x00000840)
+#define ADR_RF_D_CAL_TOP_4 (CSR_TU_RF_BASE+0x00000844)
+#define ADR_RF_D_CAL_TOP_5 (CSR_TU_RF_BASE+0x00000848)
+#define ADR_RF_D_CAL_TOP_6 (CSR_TU_RF_BASE+0x0000084c)
+#define ADR_RF_D_CAL_TOP_7 (CSR_TU_RF_BASE+0x00000850)
+#define ADR_RF_D_CAL_TOP_8 (CSR_TU_RF_BASE+0x00000854)
+#define ADR_RF_D_CAL_TOP_9 (CSR_TU_RF_BASE+0x00000858)
+#define ADR_HS3W_CTRL1 (CSR_TU_RF_BASE+0x00000880)
+#define ADR_HS3W_CTRL2 (CSR_TU_RF_BASE+0x00000884)
+#define ADR_HS3W_CTRL3 (CSR_TU_RF_BASE+0x00000888)
+#define ADR_RF_D_MODE_CTRL (CSR_TU_RF_BASE+0x0000088c)
+#define ADR_HS3W_READ_OUT_1 (CSR_TU_RF_BASE+0x00000890)
+#define ADR_HS3W_READ_OUT_2_ (CSR_TU_RF_BASE+0x00000894)
+#define ADR_HS3W_READ_OUT_3 (CSR_TU_RF_BASE+0x00000898)
+#define ADR_SX_LOCK_FREQ_1 (CSR_TU_RF_BASE+0x0000089c)
+#define ADR_SX_LOCK_FREQ_2 (CSR_TU_RF_BASE+0x000008a0)
+#define ADR_RX_DC_CAL_RESULT (CSR_TU_RF_BASE+0x000008c0)
+#define ADR_AUDIO_CTRL_REG (CSR_TU_RF_BASE+0x000008c4)
+#define ADR_AUDIO_PDM_REG (CSR_TU_RF_BASE+0x000008c8)
+#define ADR_RF_5G_TX_PARTITION_BAND1 (CSR_TU_RF_BASE+0x000008cc)
+#define ADR_RF_5G_TX_PARTITION_BAND2 (CSR_TU_RF_BASE+0x000008d0)
+#define ADR_WIFI_PADPD_5100_GAIN_REG0 (CSR_TU_RF_BASE+0x00000900)
+#define ADR_WIFI_PADPD_5100_GAIN_REG1 (CSR_TU_RF_BASE+0x00000904)
+#define ADR_WIFI_PADPD_5100_GAIN_REG2 (CSR_TU_RF_BASE+0x00000908)
+#define ADR_WIFI_PADPD_5100_GAIN_REG3 (CSR_TU_RF_BASE+0x0000090c)
+#define ADR_WIFI_PADPD_5100_GAIN_REG4 (CSR_TU_RF_BASE+0x00000910)
+#define ADR_WIFI_PADPD_5100_GAIN_REG5 (CSR_TU_RF_BASE+0x00000914)
+#define ADR_WIFI_PADPD_5100_GAIN_REG6 (CSR_TU_RF_BASE+0x00000918)
+#define ADR_WIFI_PADPD_5100_GAIN_REG7 (CSR_TU_RF_BASE+0x0000091c)
+#define ADR_WIFI_PADPD_5100_GAIN_REG8 (CSR_TU_RF_BASE+0x00000920)
+#define ADR_WIFI_PADPD_5100_GAIN_REG9 (CSR_TU_RF_BASE+0x00000924)
+#define ADR_WIFI_PADPD_5100_GAIN_REGA (CSR_TU_RF_BASE+0x00000928)
+#define ADR_WIFI_PADPD_5100_GAIN_REGB (CSR_TU_RF_BASE+0x0000092c)
+#define ADR_WIFI_PADPD_5100_GAIN_REGC (CSR_TU_RF_BASE+0x00000930)
+#define ADR_WIFI_PADPD_5100_PHASE_REG0 (CSR_TU_RF_BASE+0x00000940)
+#define ADR_WIFI_PADPD_5100_PHASE_REG1 (CSR_TU_RF_BASE+0x00000944)
+#define ADR_WIFI_PADPD_5100_PHASE_REG2 (CSR_TU_RF_BASE+0x00000948)
+#define ADR_WIFI_PADPD_5100_PHASE_REG3 (CSR_TU_RF_BASE+0x0000094c)
+#define ADR_WIFI_PADPD_5100_PHASE_REG4 (CSR_TU_RF_BASE+0x00000950)
+#define ADR_WIFI_PADPD_5100_PHASE_REG5 (CSR_TU_RF_BASE+0x00000954)
+#define ADR_WIFI_PADPD_5100_PHASE_REG6 (CSR_TU_RF_BASE+0x00000958)
+#define ADR_WIFI_PADPD_5100_PHASE_REG7 (CSR_TU_RF_BASE+0x0000095c)
+#define ADR_WIFI_PADPD_5100_PHASE_REG8 (CSR_TU_RF_BASE+0x00000960)
+#define ADR_WIFI_PADPD_5100_PHASE_REG9 (CSR_TU_RF_BASE+0x00000964)
+#define ADR_WIFI_PADPD_5100_PHASE_REGA (CSR_TU_RF_BASE+0x00000968)
+#define ADR_WIFI_PADPD_5100_PHASE_REGB (CSR_TU_RF_BASE+0x0000096c)
+#define ADR_WIFI_PADPD_5100_PHASE_REGC (CSR_TU_RF_BASE+0x00000970)
+#define ADR_WIFI_PADPD_5500_GAIN_REG0 (CSR_TU_RF_BASE+0x00000980)
+#define ADR_WIFI_PADPD_5500_GAIN_REG1 (CSR_TU_RF_BASE+0x00000984)
+#define ADR_WIFI_PADPD_5500_GAIN_REG2 (CSR_TU_RF_BASE+0x00000988)
+#define ADR_WIFI_PADPD_5500_GAIN_REG3 (CSR_TU_RF_BASE+0x0000098c)
+#define ADR_WIFI_PADPD_5500_GAIN_REG4 (CSR_TU_RF_BASE+0x00000990)
+#define ADR_WIFI_PADPD_5500_GAIN_REG5 (CSR_TU_RF_BASE+0x00000994)
+#define ADR_WIFI_PADPD_5500_GAIN_REG6 (CSR_TU_RF_BASE+0x00000998)
+#define ADR_WIFI_PADPD_5500_GAIN_REG7 (CSR_TU_RF_BASE+0x0000099c)
+#define ADR_WIFI_PADPD_5500_GAIN_REG8 (CSR_TU_RF_BASE+0x000009a0)
+#define ADR_WIFI_PADPD_5500_GAIN_REG9 (CSR_TU_RF_BASE+0x000009a4)
+#define ADR_WIFI_PADPD_5500_GAIN_REGA (CSR_TU_RF_BASE+0x000009a8)
+#define ADR_WIFI_PADPD_5500_GAIN_REGB (CSR_TU_RF_BASE+0x000009ac)
+#define ADR_WIFI_PADPD_5500_GAIN_REGC (CSR_TU_RF_BASE+0x000009b0)
+#define ADR_WIFI_PADPD_5500_PHASE_REG0 (CSR_TU_RF_BASE+0x000009c0)
+#define ADR_WIFI_PADPD_5500_PHASE_REG1 (CSR_TU_RF_BASE+0x000009c4)
+#define ADR_WIFI_PADPD_5500_PHASE_REG2 (CSR_TU_RF_BASE+0x000009c8)
+#define ADR_WIFI_PADPD_5500_PHASE_REG3 (CSR_TU_RF_BASE+0x000009cc)
+#define ADR_WIFI_PADPD_5500_PHASE_REG4 (CSR_TU_RF_BASE+0x000009d0)
+#define ADR_WIFI_PADPD_5500_PHASE_REG5 (CSR_TU_RF_BASE+0x000009d4)
+#define ADR_WIFI_PADPD_5500_PHASE_REG6 (CSR_TU_RF_BASE+0x000009d8)
+#define ADR_WIFI_PADPD_5500_PHASE_REG7 (CSR_TU_RF_BASE+0x000009dc)
+#define ADR_WIFI_PADPD_5500_PHASE_REG8 (CSR_TU_RF_BASE+0x000009e0)
+#define ADR_WIFI_PADPD_5500_PHASE_REG9 (CSR_TU_RF_BASE+0x000009e4)
+#define ADR_WIFI_PADPD_5500_PHASE_REGA (CSR_TU_RF_BASE+0x000009e8)
+#define ADR_WIFI_PADPD_5500_PHASE_REGB (CSR_TU_RF_BASE+0x000009ec)
+#define ADR_WIFI_PADPD_5500_PHASE_REGC (CSR_TU_RF_BASE+0x000009f0)
+#define ADR_WIFI_PADPD_5700_GAIN_REG0 (CSR_TU_RF_BASE+0x00000a00)
+#define ADR_WIFI_PADPD_5700_GAIN_REG1 (CSR_TU_RF_BASE+0x00000a04)
+#define ADR_WIFI_PADPD_5700_GAIN_REG2 (CSR_TU_RF_BASE+0x00000a08)
+#define ADR_WIFI_PADPD_5700_GAIN_REG3 (CSR_TU_RF_BASE+0x00000a0c)
+#define ADR_WIFI_PADPD_5700_GAIN_REG4 (CSR_TU_RF_BASE+0x00000a10)
+#define ADR_WIFI_PADPD_5700_GAIN_REG5 (CSR_TU_RF_BASE+0x00000a14)
+#define ADR_WIFI_PADPD_5700_GAIN_REG6 (CSR_TU_RF_BASE+0x00000a18)
+#define ADR_WIFI_PADPD_5700_GAIN_REG7 (CSR_TU_RF_BASE+0x00000a1c)
+#define ADR_WIFI_PADPD_5700_GAIN_REG8 (CSR_TU_RF_BASE+0x00000a20)
+#define ADR_WIFI_PADPD_5700_GAIN_REG9 (CSR_TU_RF_BASE+0x00000a24)
+#define ADR_WIFI_PADPD_5700_GAIN_REGA (CSR_TU_RF_BASE+0x00000a28)
+#define ADR_WIFI_PADPD_5700_GAIN_REGB (CSR_TU_RF_BASE+0x00000a2c)
+#define ADR_WIFI_PADPD_5700_GAIN_REGC (CSR_TU_RF_BASE+0x00000a30)
+#define ADR_WIFI_PADPD_5700_PHASE_REG0 (CSR_TU_RF_BASE+0x00000a40)
+#define ADR_WIFI_PADPD_5700_PHASE_REG1 (CSR_TU_RF_BASE+0x00000a44)
+#define ADR_WIFI_PADPD_5700_PHASE_REG2 (CSR_TU_RF_BASE+0x00000a48)
+#define ADR_WIFI_PADPD_5700_PHASE_REG3 (CSR_TU_RF_BASE+0x00000a4c)
+#define ADR_WIFI_PADPD_5700_PHASE_REG4 (CSR_TU_RF_BASE+0x00000a50)
+#define ADR_WIFI_PADPD_5700_PHASE_REG5 (CSR_TU_RF_BASE+0x00000a54)
+#define ADR_WIFI_PADPD_5700_PHASE_REG6 (CSR_TU_RF_BASE+0x00000a58)
+#define ADR_WIFI_PADPD_5700_PHASE_REG7 (CSR_TU_RF_BASE+0x00000a5c)
+#define ADR_WIFI_PADPD_5700_PHASE_REG8 (CSR_TU_RF_BASE+0x00000a60)
+#define ADR_WIFI_PADPD_5700_PHASE_REG9 (CSR_TU_RF_BASE+0x00000a64)
+#define ADR_WIFI_PADPD_5700_PHASE_REGA (CSR_TU_RF_BASE+0x00000a68)
+#define ADR_WIFI_PADPD_5700_PHASE_REGB (CSR_TU_RF_BASE+0x00000a6c)
+#define ADR_WIFI_PADPD_5700_PHASE_REGC (CSR_TU_RF_BASE+0x00000a70)
+#define ADR_WIFI_PADPD_5900_GAIN_REG0 (CSR_TU_RF_BASE+0x00000a80)
+#define ADR_WIFI_PADPD_5900_GAIN_REG1 (CSR_TU_RF_BASE+0x00000a84)
+#define ADR_WIFI_PADPD_5900_GAIN_REG2 (CSR_TU_RF_BASE+0x00000a88)
+#define ADR_WIFI_PADPD_5900_GAIN_REG3 (CSR_TU_RF_BASE+0x00000a8c)
+#define ADR_WIFI_PADPD_5900_GAIN_REG4 (CSR_TU_RF_BASE+0x00000a90)
+#define ADR_WIFI_PADPD_5900_GAIN_REG5 (CSR_TU_RF_BASE+0x00000a94)
+#define ADR_WIFI_PADPD_5900_GAIN_REG6 (CSR_TU_RF_BASE+0x00000a98)
+#define ADR_WIFI_PADPD_5900_GAIN_REG7 (CSR_TU_RF_BASE+0x00000a9c)
+#define ADR_WIFI_PADPD_5900_GAIN_REG8 (CSR_TU_RF_BASE+0x00000aa0)
+#define ADR_WIFI_PADPD_5900_GAIN_REG9 (CSR_TU_RF_BASE+0x00000aa4)
+#define ADR_WIFI_PADPD_5900_GAIN_REGA (CSR_TU_RF_BASE+0x00000aa8)
+#define ADR_WIFI_PADPD_5900_GAIN_REGB (CSR_TU_RF_BASE+0x00000aac)
+#define ADR_WIFI_PADPD_5900_GAIN_REGC (CSR_TU_RF_BASE+0x00000ab0)
+#define ADR_WIFI_PADPD_5900_PHASE_REG0 (CSR_TU_RF_BASE+0x00000ac0)
+#define ADR_WIFI_PADPD_5900_PHASE_REG1 (CSR_TU_RF_BASE+0x00000ac4)
+#define ADR_WIFI_PADPD_5900_PHASE_REG2 (CSR_TU_RF_BASE+0x00000ac8)
+#define ADR_WIFI_PADPD_5900_PHASE_REG3 (CSR_TU_RF_BASE+0x00000acc)
+#define ADR_WIFI_PADPD_5900_PHASE_REG4 (CSR_TU_RF_BASE+0x00000ad0)
+#define ADR_WIFI_PADPD_5900_PHASE_REG5 (CSR_TU_RF_BASE+0x00000ad4)
+#define ADR_WIFI_PADPD_5900_PHASE_REG6 (CSR_TU_RF_BASE+0x00000ad8)
+#define ADR_WIFI_PADPD_5900_PHASE_REG7 (CSR_TU_RF_BASE+0x00000adc)
+#define ADR_WIFI_PADPD_5900_PHASE_REG8 (CSR_TU_RF_BASE+0x00000ae0)
+#define ADR_WIFI_PADPD_5900_PHASE_REG9 (CSR_TU_RF_BASE+0x00000ae4)
+#define ADR_WIFI_PADPD_5900_PHASE_REGA (CSR_TU_RF_BASE+0x00000ae8)
+#define ADR_WIFI_PADPD_5900_PHASE_REGB (CSR_TU_RF_BASE+0x00000aec)
+#define ADR_WIFI_PADPD_5900_PHASE_REGC (CSR_TU_RF_BASE+0x00000af0)
+#define ADR_WIFI_PADPD_CAL_TONEGEN_REG (CSR_TU_RF_BASE+0x00000c08)
+#define ADR_WIFI_PADPD_CAL_RX_PADPD_REG (CSR_TU_RF_BASE+0x00000c0c)
+#define ADR_WIFI_PADPD_CAL_RX_RO (CSR_TU_RF_BASE+0x00000c10)
+#define ADR_WIFI_PADPD_CFR (CSR_TU_RF_BASE+0x00000c14)
+#define ADR_WIFI_PADPD_DC_RM (CSR_TU_RF_BASE+0x00000c18)
+#define ADR_WIFI_PADPD_TXIQ_CLIP_REG (CSR_TU_RF_BASE+0x00000c40)
+#define ADR_WIFI_PADPD_TXIQ_CONTROL_REG (CSR_TU_RF_BASE+0x00000c44)
+#define ADR_WIFI_PADPD_TXIQ_DPD_DC_REG (CSR_TU_RF_BASE+0x00000c48)
+#define ADR_WIFI_PADPD_TXIQ_DC_OFFSET_REG (CSR_TU_RF_BASE+0x00000c4c)
+#define ADR_WIFI_PADPD_2G_CONTROL_REG (CSR_TU_RF_BASE+0x00000d1c)
+#define ADR_WIFI_PADPD_2G_GAIN_REG0 (CSR_TU_RF_BASE+0x00000d20)
+#define ADR_WIFI_PADPD_2G_GAIN_REG1 (CSR_TU_RF_BASE+0x00000d24)
+#define ADR_WIFI_PADPD_2G_GAIN_REG2 (CSR_TU_RF_BASE+0x00000d28)
+#define ADR_WIFI_PADPD_2G_GAIN_REG3 (CSR_TU_RF_BASE+0x00000d30)
+#define ADR_WIFI_PADPD_2G_GAIN_REG4 (CSR_TU_RF_BASE+0x00000d34)
+#define ADR_WIFI_PADPD_2G_GAIN_REG5 (CSR_TU_RF_BASE+0x00000d38)
+#define ADR_WIFI_PADPD_2G_GAIN_REG6 (CSR_TU_RF_BASE+0x00000d3c)
+#define ADR_WIFI_PADPD_2G_GAIN_REG7 (CSR_TU_RF_BASE+0x00000d40)
+#define ADR_WIFI_PADPD_2G_GAIN_REG8 (CSR_TU_RF_BASE+0x00000d44)
+#define ADR_WIFI_PADPD_2G_GAIN_REG9 (CSR_TU_RF_BASE+0x00000d48)
+#define ADR_WIFI_PADPD_2G_GAIN_REGA (CSR_TU_RF_BASE+0x00000d4c)
+#define ADR_WIFI_PADPD_2G_GAIN_REGB (CSR_TU_RF_BASE+0x00000d50)
+#define ADR_WIFI_PADPD_2G_GAIN_REGC (CSR_TU_RF_BASE+0x00000d54)
+#define ADR_WIFI_PADPD_2G_PHASE_REG0 (CSR_TU_RF_BASE+0x00000d70)
+#define ADR_WIFI_PADPD_2G_PHASE_REG1 (CSR_TU_RF_BASE+0x00000d74)
+#define ADR_WIFI_PADPD_2G_PHASE_REG2 (CSR_TU_RF_BASE+0x00000d78)
+#define ADR_WIFI_PADPD_2G_PHASE_REG3 (CSR_TU_RF_BASE+0x00000d80)
+#define ADR_WIFI_PADPD_2G_PHASE_REG4 (CSR_TU_RF_BASE+0x00000d84)
+#define ADR_WIFI_PADPD_2G_PHASE_REG5 (CSR_TU_RF_BASE+0x00000d88)
+#define ADR_WIFI_PADPD_2G_PHASE_REG6 (CSR_TU_RF_BASE+0x00000d8c)
+#define ADR_WIFI_PADPD_2G_PHASE_REG7 (CSR_TU_RF_BASE+0x00000d90)
+#define ADR_WIFI_PADPD_2G_PHASE_REG8 (CSR_TU_RF_BASE+0x00000d94)
+#define ADR_WIFI_PADPD_2G_PHASE_REG9 (CSR_TU_RF_BASE+0x00000d98)
+#define ADR_WIFI_PADPD_2G_PHASE_REGA (CSR_TU_RF_BASE+0x00000d9c)
+#define ADR_WIFI_PADPD_2G_PHASE_REGB (CSR_TU_RF_BASE+0x00000da0)
+#define ADR_WIFI_PADPD_2G_PHASE_REGC (CSR_TU_RF_BASE+0x00000da4)
+#define ADR_WIFI_PADPD_5G_BB_GAIN_REG (CSR_TU_RF_BASE+0x00000da8)
+#define ADR_WIFI_PADPD_2G_BB_GAIN_REG (CSR_TU_RF_BASE+0x00000dac)
+#define ADR_WIFI_PADPD_TX_GAIN_0P5DB_REG (CSR_TU_RF_BASE+0x00000dbc)
+#define ADR_HS5W_MD_EN (CSR_TU_RF_BASE+0x00000dc0)
+#define ADR_HS5W_MAN (CSR_TU_RF_BASE+0x00000dc4)
+#define ADR_HS5W_MAN_SET_ADD0 (CSR_TU_RF_BASE+0x00000dc8)
+#define ADR_HS5W_MAN_SET_ADD1 (CSR_TU_RF_BASE+0x00000dcc)
+#define ADR_HS5W_MAN_SET_ADD2 (CSR_TU_RF_BASE+0x00000dd0)
+#define ADR_HS5W_MAN_SET_ADD3 (CSR_TU_RF_BASE+0x00000dd4)
+#define ADR_HS5W_MAN_SET_ADD4_CH (CSR_TU_RF_BASE+0x00000dd8)
+#define ADR_HS5W_MAN_SET_ADD4_CH_5GB (CSR_TU_RF_BASE+0x00000ddc)
+#define ADR_HS5W_MAN_SET_ADD4_F (CSR_TU_RF_BASE+0x00000de0)
+#define ADR_HS5W_MAN_SET_ADD4_F_5GB (CSR_TU_RF_BASE+0x00000de4)
+#define ADR_HS5W_MAN_SET_ADD5 (CSR_TU_RF_BASE+0x00000de8)
+#define ADR_HS5W_MAN_SET_ADD5_5GB (CSR_TU_RF_BASE+0x00000dec)
+#define ADR_HS5W_MAN_SET_ADD6 (CSR_TU_RF_BASE+0x00000df0)
+#define ADR_WIFI_PADPD_RESERVED_REG (CSR_TU_RF_BASE+0x00000ffc)
+#define ADR_PMU_REG_1 (CSR_TU_PMU_BASE+0x00000000)
+#define ADR_PMU_REG_2 (CSR_TU_PMU_BASE+0x00000004)
+#define ADR_PMU_REG_3 (CSR_TU_PMU_BASE+0x00000008)
+#define ADR_PMU_REG_4 (CSR_TU_PMU_BASE+0x0000000c)
+#define ADR_PMU_REG_5 (CSR_TU_PMU_BASE+0x00000010)
+#define ADR_PMU_REG_6 (CSR_TU_PMU_BASE+0x00000014)
+#define ADR_PMU_SLEEP_REG_1 (CSR_TU_PMU_BASE+0x00000018)
+#define ADR_PMU_SLEEP_REG_2 (CSR_TU_PMU_BASE+0x0000001c)
+#define ADR_PMU_RTC_REG_0 (CSR_TU_PMU_BASE+0x00000020)
+#define ADR_PMU_RTC_REG_1 (CSR_TU_PMU_BASE+0x00000024)
+#define ADR_PMU_RTC_REG_2 (CSR_TU_PMU_BASE+0x00000028)
+#define ADR_PMU_RTC_REG_3 (CSR_TU_PMU_BASE+0x0000002c)
+#define ADR_PMU_CTRL_REG (CSR_TU_PMU_BASE+0x0000003c)
+#define ADR_PMU_STATE_REG (CSR_TU_PMU_BASE+0x00000044)
+#define ADR_PMU_DPLL_REG_0 (CSR_TU_PMU_BASE+0x00000080)
+#define ADR_PMU_DPLL_REG_1 (CSR_TU_PMU_BASE+0x00000084)
+#define ADR_PMU_DPLL_REG_2 (CSR_TU_PMU_BASE+0x00000088)
+#define ADR_PMU_DPLL_REG_3 (CSR_TU_PMU_BASE+0x0000008c)
+#define ADR_PMU_SLEEP_MODE_REG (CSR_TU_PMU_BASE+0x00000090)
+#define ADR_PMU_RAM_00 (CSR_TU_PMU_BASE+0x000000c0)
+#define ADR_PMU_RAM_01 (CSR_TU_PMU_BASE+0x000000c4)
+#define ADR_PMU_RAM_02 (CSR_TU_PMU_BASE+0x000000c8)
+#define ADR_PMU_RAM_03 (CSR_TU_PMU_BASE+0x000000cc)
+#define ADR_PMU_RAM_04 (CSR_TU_PMU_BASE+0x000000d0)
+#define ADR_PMU_RAM_05 (CSR_TU_PMU_BASE+0x000000d4)
+#define ADR_PMU_RAM_06 (CSR_TU_PMU_BASE+0x000000d8)
+#define ADR_PMU_RAM_07 (CSR_TU_PMU_BASE+0x000000dc)
+#define ADR_PMU_RAM_08 (CSR_TU_PMU_BASE+0x000000e0)
+#define ADR_PMU_RAM_09 (CSR_TU_PMU_BASE+0x000000e4)
+#define ADR_PMU_RAM_10 (CSR_TU_PMU_BASE+0x000000e8)
+#define ADR_PMU_RAM_11 (CSR_TU_PMU_BASE+0x000000ec)
+#define ADR_PMU_RAM_12 (CSR_TU_PMU_BASE+0x000000f0)
+#define ADR_PMU_RAM_13 (CSR_TU_PMU_BASE+0x000000f4)
+#define ADR_PMU_RAM_14 (CSR_TU_PMU_BASE+0x000000f8)
+#define ADR_PMU_RAM_15 (CSR_TU_PMU_BASE+0x000000fc)
+#define ADR_WIFI_PHY_COMMON_SYS_REG (CSR_TU_PHY_BASE+0x00000000)
+#define ADR_WIFI_PHY_COMMON_ENABLE_REG (CSR_TU_PHY_BASE+0x00000004)
+#define ADR_WIFI_PHY_COMMON_VERSION_REG (CSR_TU_PHY_BASE+0x00000008)
+#define ADR_WIFI_PHY_COMMON_DES_REG0 (CSR_TU_PHY_BASE+0x0000000c)
+#define ADR_WIFI_PHY_COMMON_DES_REG1 (CSR_TU_PHY_BASE+0x00000010)
+#define ADR_WIFI_PHY_COMMON_DES_REG2 (CSR_TU_PHY_BASE+0x00000014)
+#define ADR_WIFI_PHY_COMMON_DES_REG3 (CSR_TU_PHY_BASE+0x00000018)
+#define ADR_WIFI_PHY_COMMON_DES_REG4 (CSR_TU_PHY_BASE+0x0000001c)
+#define ADR_WIFI_PHY_COMMON_TX_CONTROL (CSR_TU_PHY_BASE+0x00000020)
+#define ADR_WIFI_PHY_COMMON_DES_REG5 (CSR_TU_PHY_BASE+0x00000024)
+#define ADR_WIFI_PHY_COMMON_DES_REG6 (CSR_TU_PHY_BASE+0x00000028)
+#define ADR_WIFI_PHY_COMMON_RFAGC_REG0 (CSR_TU_PHY_BASE+0x0000002c)
+#define ADR_WIFI_PHY_COMMON_RFAGC_REG1 (CSR_TU_PHY_BASE+0x00000030)
+#define ADR_WIFI_PHY_COMMON_RFAGC_REG2 (CSR_TU_PHY_BASE+0x00000034)
+#define ADR_WIFI_PHY_COMMON_RFAGC_REG3 (CSR_TU_PHY_BASE+0x00000038)
+#define ADR_WIFI_PHY_COMMON_RFAGC_REG4 (CSR_TU_PHY_BASE+0x0000003c)
+#define ADR_WIFI_PHY_COMMON_11B_DAGC_REG0 (CSR_TU_PHY_BASE+0x00000040)
+#define ADR_WIFI_PHY_COMMON_11B_DAGC_REG1 (CSR_TU_PHY_BASE+0x00000044)
+#define ADR_WIFI_PHY_COMMON_11GN20_DAGC_REG0 (CSR_TU_PHY_BASE+0x00000048)
+#define ADR_WIFI_PHY_COMMON_11GN20_DAGC_REG1 (CSR_TU_PHY_BASE+0x0000004c)
+#define ADR_WIFI_PHY_COMMON_11BGN_DIGPWR_REG (CSR_TU_PHY_BASE+0x00000050)
+#define ADR_WIFI_PHY_COMMON_RFAGC_RO00 (CSR_TU_PHY_BASE+0x00000054)
+#define ADR_WIFI_PHY_COMMON_RFAGC_RO01 (CSR_TU_PHY_BASE+0x00000058)
+#define ADR_WIFI_PHY_COMMON_RFAGC_RO02 (CSR_TU_PHY_BASE+0x0000005c)
+#define ADR_WIFI_PHY_COMMON_RXDC (CSR_TU_PHY_BASE+0x00000060)
+#define ADR_WIFI_PHY_COMMON_RXDC_RO (CSR_TU_PHY_BASE+0x00000064)
+#define ADR_WIFI_PHY_COMMON_RSSI_TBUS_REG (CSR_TU_PHY_BASE+0x00000080)
+#define ADR_WIFI_PHY_COMMON_RX_EN_CNT_REG (CSR_TU_PHY_BASE+0x00000088)
+#define ADR_WIFI_PHY_COMMON_EDCCA_0 (CSR_TU_PHY_BASE+0x0000008c)
+#define ADR_WIFI_PHY_COMMON_EDCCA_1 (CSR_TU_PHY_BASE+0x00000090)
+#define ADR_WIFI_PHY_COMMON_EDCCA_2 (CSR_TU_PHY_BASE+0x00000094)
+#define ADR_WIFI_PHY_AGC_RELOCK_1 (CSR_TU_PHY_BASE+0x00000098)
+#define ADR_WIFI_PHY_AGC_RELOCK_2 (CSR_TU_PHY_BASE+0x0000009c)
+#define ADR_WIFI_PHY_COMMON_TX_LENGTH_CNT_REG0 (CSR_TU_PHY_BASE+0x000000a0)
+#define ADR_WIFI_PHY_COMMON_TX_LENGTH_CNT_REG1 (CSR_TU_PHY_BASE+0x000000a4)
+#define ADR_WIFI_PHY_COMMON_RX_LENGTH_CNT_REG0 (CSR_TU_PHY_BASE+0x000000a8)
+#define ADR_WIFI_PHY_COMMON_RX_LENGTH_CNT_REG1 (CSR_TU_PHY_BASE+0x000000ac)
+#define ADR_WIFI_PHY_COMMON_TX_LENGTH_CNT_RO (CSR_TU_PHY_BASE+0x000000b0)
+#define ADR_WIFI_PHY_COMMON_RX_LENGTH_CNT_RO (CSR_TU_PHY_BASE+0x000000b4)
+#define ADR_WIFI_PHY_COMMON_TRX_TYPE_CNT_REG (CSR_TU_PHY_BASE+0x000000fc)
+#define ADR_WIFI_PHY_COMMON_TRX_TYPE_CNT_RO (CSR_TU_PHY_BASE+0x00000100)
+#define ADR_WIFI_PHY_COMMON_11GN40_DAGC_REG0 (CSR_TU_PHY_BASE+0x0000012c)
+#define ADR_WIFI_PHY_COMMON_11GN40_DAGC_REG1 (CSR_TU_PHY_BASE+0x00000130)
+#define ADR_WIFI_PHY_COMMON_11GN_DAGC_INI_REG (CSR_TU_PHY_BASE+0x00000134)
+#define ADR_WIFI_PHY_COMMON_MAC_PKT_REG_0 (CSR_TU_PHY_BASE+0x00000140)
+#define ADR_WIFI_PHY_COMMON_MAC_PKT_REG_1 (CSR_TU_PHY_BASE+0x00000144)
+#define ADR_WIFI_PHY_COMMON_MAC_PKT_REG_2 (CSR_TU_PHY_BASE+0x00000148)
+#define ADR_WIFI_PHY_COMMON_MAC_PKT_REG_3 (CSR_TU_PHY_BASE+0x0000014c)
+#define ADR_WIFI_PHY_COMMON_MAC_PKT_REG_4 (CSR_TU_PHY_BASE+0x00000150)
+#define ADR_WIFI_PHY_COMMON_MAC_PKT_REG_5 (CSR_TU_PHY_BASE+0x00000154)
+#define ADR_WIFI_PHY_COMMON_MAC_PKT_REG_6 (CSR_TU_PHY_BASE+0x00000158)
+#define ADR_WIFI_PHY_COMMON_MAC_PKT_REG_7 (CSR_TU_PHY_BASE+0x0000015c)
+#define ADR_WIFI_PHY_COMMON_MAC_PKT_REG_8 (CSR_TU_PHY_BASE+0x00000160)
+#define ADR_WIFI_PHY_COMMON_MAC_PKT_REG_9 (CSR_TU_PHY_BASE+0x00000164)
+#define ADR_WIFI_PHY_COMMON_MAC_PKT_REG_A (CSR_TU_PHY_BASE+0x00000168)
+#define ADR_WIFI_PHY_COMMON_BB_SCALE_REG_0 (CSR_TU_PHY_BASE+0x00000180)
+#define ADR_WIFI_PHY_COMMON_BB_SCALE_REG_1 (CSR_TU_PHY_BASE+0x00000184)
+#define ADR_WIFI_PHY_COMMON_BB_SCALE_REG_2 (CSR_TU_PHY_BASE+0x00000188)
+#define ADR_WIFI_PHY_COMMON_BB_SCALE_REG_3 (CSR_TU_PHY_BASE+0x0000018c)
+#define ADR_WIFI_PHY_COMMON_RF_PWR_REG_0 (CSR_TU_PHY_BASE+0x00000190)
+#define ADR_WIFI_PHY_COMMON_RF_PWR_REG_1 (CSR_TU_PHY_BASE+0x00000194)
+#define ADR_WIFI_PHY_COMMON_RF_PWR_REG_2 (CSR_TU_PHY_BASE+0x00000198)
+#define ADR_WIFI_PHY_COMMON_RF_PWR_REG_3 (CSR_TU_PHY_BASE+0x0000019c)
+#define ADR_WIFI_PHY_COMMON_RX_MON_0 (CSR_TU_PHY_BASE+0x000001c0)
+#define ADR_WIFI_PHY_COMMON_RX_MON_1 (CSR_TU_PHY_BASE+0x000001c4)
+#define ADR_WIFI_PHY_COMMON_RX_MON_2 (CSR_TU_PHY_BASE+0x000001c8)
+#define ADR_WIFI_PHY_COMMON_RX_MON_3 (CSR_TU_PHY_BASE+0x000001cc)
+#define ADR_WIFI_PHY_COMMON_RX_MON_4 (CSR_TU_PHY_BASE+0x000001d0)
+#define ADR_WIFI_PHY_COMMON_RX_MON_5 (CSR_TU_PHY_BASE+0x000001d4)
+#define ADR_WIFI_PHY_COMMON_RX_MON_6 (CSR_TU_PHY_BASE+0x000001d8)
+#define ADR_WIFI_PHY_COMMON_RX_MON_7 (CSR_TU_PHY_BASE+0x000001dc)
+#define ADR_WIFI_PHY_COMMON_RX_MON_8 (CSR_TU_PHY_BASE+0x000001e0)
+#define ADR_WIFI_PHY_COMMON_RX_TMR_MON_RO (CSR_TU_PHY_BASE+0x000001e4)
+#define ADR_WIFI_PHY_COMMON_RX_BKN_MON_RO (CSR_TU_PHY_BASE+0x000001e8)
+#define ADR_WIFI_PHY_COMMON_MAC_IF_CNT_CTRL (CSR_TU_PHY_BASE+0x00000200)
+#define ADR_WIFI_PHY_COMMON_MAC_IF_CNT_RO (CSR_TU_PHY_BASE+0x00000204)
+#define ADR_WIFI_PHY_COMMON_RX_FFT_MEM_BIST_REG (CSR_TU_PHY_BASE+0x00000220)
+#define ADR_WIFI_PHY_AUDIO_CLK_CTRL (CSR_TU_PHY_BASE+0x00000240)
+#define ADR_WIFI_PHY_COMMON_TOP_STATUS_RO (CSR_TU_PHY_BASE+0x000003c0)
+#define ADR_WIFI_PHY_COMMON_RESERVED_REG (CSR_TU_PHY_BASE+0x000003fc)
+#define ADR_WIFI_11B_TX_BB_RAMP_REG (CSR_TU_PHY_BASE+0x000004b4)
+#define ADR_WIFI_11B_TX_PKT_CNT_SENT_REG (CSR_TU_PHY_BASE+0x000007c0)
+#define ADR_WIFI_11B_TX_DEBUG_SEL_REG (CSR_TU_PHY_BASE+0x000007f8)
+#define ADR_WIFI_11B_TX_RESERVED_REG (CSR_TU_PHY_BASE+0x000007fc)
+#define ADR_WIFI_11B_RX_REG_000 (CSR_TU_PHY_BASE+0x00000800)
+#define ADR_WIFI_11B_RX_REG_001 (CSR_TU_PHY_BASE+0x00000804)
+#define ADR_WIFI_11B_RX_REG_002 (CSR_TU_PHY_BASE+0x00000808)
+#define ADR_WIFI_11B_RX_REG_003 (CSR_TU_PHY_BASE+0x0000080c)
+#define ADR_WIFI_11B_RX_REG_004 (CSR_TU_PHY_BASE+0x00000810)
+#define ADR_WIFI_11B_RX_REG_005 (CSR_TU_PHY_BASE+0x00000814)
+#define ADR_WIFI_11B_RX_REG_006 (CSR_TU_PHY_BASE+0x00000818)
+#define ADR_WIFI_11B_RX_REG_007 (CSR_TU_PHY_BASE+0x0000081c)
+#define ADR_WIFI_11B_RX_REG_008 (CSR_TU_PHY_BASE+0x00000820)
+#define ADR_WIFI_11B_RX_REG_009 (CSR_TU_PHY_BASE+0x00000824)
+#define ADR_WIFI_11B_RX_REG_010 (CSR_TU_PHY_BASE+0x00000828)
+#define ADR_WIFI_11B_RX_REG_011 (CSR_TU_PHY_BASE+0x0000082c)
+#define ADR_WIFI_11B_RX_REG_012 (CSR_TU_PHY_BASE+0x00000830)
+#define ADR_WIFI_11B_RX_REG_013 (CSR_TU_PHY_BASE+0x00000834)
+#define ADR_WIFI_11B_RX_REG_014 (CSR_TU_PHY_BASE+0x00000838)
+#define ADR_WIFI_11B_RX_REG_039 (CSR_TU_PHY_BASE+0x0000089c)
+#define ADR_WIFI_11B_RX_REG_040 (CSR_TU_PHY_BASE+0x000008a0)
+#define ADR_WIFI_11B_RX_REG_041 (CSR_TU_PHY_BASE+0x000008a4)
+#define ADR_WIFI_11B_RX_REG_240 (CSR_TU_PHY_BASE+0x00000bc0)
+#define ADR_WIFI_11B_RX_REG_241 (CSR_TU_PHY_BASE+0x00000bc4)
+#define ADR_WIFI_11B_RX_REG_244 (CSR_TU_PHY_BASE+0x00000bd0)
+#define ADR_WIFI_11B_RX_REG_245 (CSR_TU_PHY_BASE+0x00000bd4)
+#define ADR_WIFI_11B_RX_REG_246 (CSR_TU_PHY_BASE+0x00000bd8)
+#define ADR_WIFI_11B_RX_REG_249 (CSR_TU_PHY_BASE+0x00000be4)
+#define ADR_WIFI_11B_RX_REG_250 (CSR_TU_PHY_BASE+0x00000be8)
+#define ADR_WIFI_11B_RX_REG_251 (CSR_TU_PHY_BASE+0x00000bec)
+#define ADR_WIFI_11B_RX_REG_252 (CSR_TU_PHY_BASE+0x00000bf0)
+#define ADR_WIFI_11B_RX_REG_253 (CSR_TU_PHY_BASE+0x00000bf4)
+#define ADR_WIFI_11B_RX_REG_254 (CSR_TU_PHY_BASE+0x00000bf8)
+#define ADR_WIFI_11B_RX_REG_255 (CSR_TU_PHY_BASE+0x00000bfc)
+#define ADR_WIFI_11GN_TX_MEM_BIST_REG (CSR_TU_PHY_BASE+0x00000c80)
+#define ADR_WIFI_11GN_TX_BB_RAMP_REG (CSR_TU_PHY_BASE+0x00000ca4)
+#define ADR_WIFI_11GN_TX_CONTROL_REG (CSR_TU_PHY_BASE+0x00000ca8)
+#define ADR_WIFI_11GN_TX_STS_SCALE_REG (CSR_TU_PHY_BASE+0x00000cb0)
+#define ADR_WIFI_11GN_TX_FFT_SCALE_REG0 (CSR_TU_PHY_BASE+0x00000cb4)
+#define ADR_WIFI_11GN_TX_FFT_SCALE_REG1 (CSR_TU_PHY_BASE+0x00000cb8)
+#define ADR_WIFI_11GN_TX_PKT_CNT_SENT_REG (CSR_TU_PHY_BASE+0x00000fc0)
+#define ADR_WIFI_11GN_TX_DEBUG_SEL_REG (CSR_TU_PHY_BASE+0x00000ff8)
+#define ADR_WIFI_11GN_TX_RESERVED_REG (CSR_TU_PHY_BASE+0x00000ffc)
+#define ADR_WIFI_11GN_RX_REG_000 (CSR_TU_PHY_BASE+0x00001000)
+#define ADR_WIFI_11GN_RX_REG_001 (CSR_TU_PHY_BASE+0x00001004)
+#define ADR_WIFI_11GN_RX_REG_002 (CSR_TU_PHY_BASE+0x00001008)
+#define ADR_WIFI_11GN_RX_REG_003 (CSR_TU_PHY_BASE+0x0000100c)
+#define ADR_WIFI_11GN_RX_REG_004_ (CSR_TU_PHY_BASE+0x00001010)
+#define ADR_WIFI_11GN_RX_REG_005 (CSR_TU_PHY_BASE+0x00001014)
+#define ADR_WIFI_11GN_RX_REG_006_ (CSR_TU_PHY_BASE+0x00001018)
+#define ADR_WIFI_11GN_RX_REG_007_ (CSR_TU_PHY_BASE+0x0000101c)
+#define ADR_WIFI_11GN_RX_REG_008 (CSR_TU_PHY_BASE+0x00001020)
+#define ADR_WIFI_11GN_RX_REG_009 (CSR_TU_PHY_BASE+0x00001024)
+#define ADR_WIFI_11GN_RX_REG_010_ (CSR_TU_PHY_BASE+0x00001028)
+#define ADR_WIFI_11GN_RX_REG_011 (CSR_TU_PHY_BASE+0x0000102c)
+#define ADR_WIFI_11GN_RX_REG_012 (CSR_TU_PHY_BASE+0x00001030)
+#define ADR_WIFI_11GN_RX_REG_013 (CSR_TU_PHY_BASE+0x00001034)
+#define ADR_WIFI_11GN_RX_REG_014 (CSR_TU_PHY_BASE+0x00001038)
+#define ADR_WIFI_11GN_RX_REG_015 (CSR_TU_PHY_BASE+0x0000103c)
+#define ADR_WIFI_11GN_RX_REG_016 (CSR_TU_PHY_BASE+0x00001040)
+#define ADR_WIFI_11GN_RX_REG_017 (CSR_TU_PHY_BASE+0x00001044)
+#define ADR_WIFI_11GN_RX_REG_032 (CSR_TU_PHY_BASE+0x00001080)
+#define ADR_WIFI_11GN_RX_REG_033 (CSR_TU_PHY_BASE+0x00001084)
+#define ADR_WIFI_11GN_RX_REG_039 (CSR_TU_PHY_BASE+0x0000109c)
+#define ADR_WIFI_11GN_RX_REG_040 (CSR_TU_PHY_BASE+0x000010a0)
+#define ADR_WIFI_11GN_RX_REG_048 (CSR_TU_PHY_BASE+0x000010c0)
+#define ADR_WIFI_11GN_RX_REG_049 (CSR_TU_PHY_BASE+0x000010c4)
+#define ADR_WIFI_11GN_RX_REG_050 (CSR_TU_PHY_BASE+0x000010c8)
+#define ADR_WIFI_11GN_RX_REG_051 (CSR_TU_PHY_BASE+0x000010cc)
+#define ADR_WIFI_11GN_RX_REG_052 (CSR_TU_PHY_BASE+0x000010d0)
+#define ADR_WIFI_11GN_RX_REG_076 (CSR_TU_PHY_BASE+0x00001130)
+#define ADR_WIFI_11GN_RX_REG_087 (CSR_TU_PHY_BASE+0x0000115c)
+#define ADR_WIFI_11GN_RX_REG_088 (CSR_TU_PHY_BASE+0x00001160)
+#define ADR_WIFI_11GN_RX_REG_089 (CSR_TU_PHY_BASE+0x00001164)
+#define ADR_WIFI_11GN_RX_REG_096 (CSR_TU_PHY_BASE+0x00001180)
+#define ADR_WIFI_11GN_RX_REG_098 (CSR_TU_PHY_BASE+0x00001188)
+#define ADR_WIFI_11GN_RX_REG_100 (CSR_TU_PHY_BASE+0x00001190)
+#define ADR_WIFI_11GN_RX_REG_101 (CSR_TU_PHY_BASE+0x00001194)
+#define ADR_WIFI_11GN_RX_REG_102 (CSR_TU_PHY_BASE+0x00001198)
+#define ADR_WIFI_11GN_RX_REG_103 (CSR_TU_PHY_BASE+0x0000119c)
+#define ADR_WIFI_11GN_RX_REG_241 (CSR_TU_PHY_BASE+0x000013c4)
+#define ADR_WIFI_11GN_RX_REG_244 (CSR_TU_PHY_BASE+0x000013d0)
+#define ADR_WIFI_11GN_RX_REG_245 (CSR_TU_PHY_BASE+0x000013d4)
+#define ADR_WIFI_11GN_RX_REG_246 (CSR_TU_PHY_BASE+0x000013d8)
+#define ADR_WIFI_11GN_RX_REG_247 (CSR_TU_PHY_BASE+0x000013dc)
+#define ADR_WIFI_11GN_RX_REG_248 (CSR_TU_PHY_BASE+0x000013e0)
+#define ADR_WIFI_11GN_RX_REG_249 (CSR_TU_PHY_BASE+0x000013e4)
+#define ADR_WIFI_11GN_RX_REG_250 (CSR_TU_PHY_BASE+0x000013e8)
+#define ADR_WIFI_11GN_RX_REG_251 (CSR_TU_PHY_BASE+0x000013ec)
+#define ADR_WIFI_11GN_RX_REG_252 (CSR_TU_PHY_BASE+0x000013f0)
+#define ADR_WIFI_11GN_RX_REG_253 (CSR_TU_PHY_BASE+0x000013f4)
+#define ADR_WIFI_11GN_RX_REG_254 (CSR_TU_PHY_BASE+0x000013f8)
+#define ADR_WIFI_11GN_RX_REG_255 (CSR_TU_PHY_BASE+0x000013fc)
+#define ADR_WIFI_RADAR_REG_00 (CSR_TU_PHY_BASE+0x00001400)
+#define ADR_WIFI_RADAR_REG_01 (CSR_TU_PHY_BASE+0x00001404)
+#define ADR_WIFI_RADAR_REG_02 (CSR_TU_PHY_BASE+0x00001408)
+#define ADR_WIFI_RADAR_REG_03 (CSR_TU_PHY_BASE+0x0000140c)
+#define ADR_WIFI_RADAR_REG_04 (CSR_TU_PHY_BASE+0x00001410)
+#define ADR_WIFI_RADAR_REG_RO (CSR_TU_PHY_BASE+0x00001414)
+#define ADR_WIFI_RADAR_REG_DB_A0_RO (CSR_TU_PHY_BASE+0x00001418)
+#define ADR_WIFI_RADAR_REG_DB_A1_RO (CSR_TU_PHY_BASE+0x0000141c)
+#define ADR_WIFI_RADAR_REG_DB_A2_RO (CSR_TU_PHY_BASE+0x00001420)
+#define ADR_WIFI_RADAR_REG_DB_P0_RO (CSR_TU_PHY_BASE+0x00001424)
+#define ADR_WIFI_RADAR_REG_DB_P1_RO (CSR_TU_PHY_BASE+0x00001428)
+#define ADR_WIFI_RADAR_REG_DB_P2_RO (CSR_TU_PHY_BASE+0x0000142c)
+#define ADR_WIFI_RADAR_CHIRP_REG (CSR_TU_PHY_BASE+0x00001430)
+#define ADR_MB_CPU_INT_ALT (MB_REG_BASE+0x00000000)
+#define ADR_MB_CPU_INT (MB_REG_BASE+0x00000004)
+#define ADR_CPU_ID_TB0 (MB_REG_BASE+0x00000008)
+#define ADR_CPU_ID_TB1 (MB_REG_BASE+0x0000000c)
+#define ADR_CH0_TRIG_1 (MB_REG_BASE+0x00000010)
+#define ADR_CH0_TRIG_0 (MB_REG_BASE+0x00000010)
+#define ADR_CH0_PRI_TRIG (MB_REG_BASE+0x00000014)
+#define ADR_MCU_STATUS (MB_REG_BASE+0x00000018)
+#define ADR_RD_IN_FFCNT1 (MB_REG_BASE+0x0000001c)
+#define ADR_RD_IN_FFCNT2 (MB_REG_BASE+0x00000020)
+#define ADR_RD_FFIN_FULL (MB_REG_BASE+0x00000024)
+#define ADR_CH2_TRIG_ALT (MB_REG_BASE+0x00000028)
+#define ADR_CH2_INT_ADDR_ALT (MB_REG_BASE+0x00000028)
+#define ADR_MBOX_HALT_CFG (MB_REG_BASE+0x0000002c)
+#define ADR_MBOX_HALT_STS (MB_REG_BASE+0x0000002c)
+#define ADR_MB_DBG_CFG1 (MB_REG_BASE+0x00000030)
+#define ADR_MB_DBG_CFG2 (MB_REG_BASE+0x00000034)
+#define ADR_MB_DBG_CFG3 (MB_REG_BASE+0x00000038)
+#define ADR_MB_DBG_CFG4 (MB_REG_BASE+0x0000003c)
+#define ADR_MB_OUT_QUEUE_CFG (MB_REG_BASE+0x00000040)
+#define ADR_MB_OUT_QUEUE_FLUSH (MB_REG_BASE+0x00000044)
+#define ADR_MB_OUT_QUEUE_FLUSH (MB_REG_BASE+0x00000044)
+#define ADR_RD_FFOUT_CNT1 (MB_REG_BASE+0x00000048)
+#define ADR_RD_FFOUT_CNT2 (MB_REG_BASE+0x0000004c)
+#define ADR_RD_FFOUT_CNT3 (MB_REG_BASE+0x00000050)
+#define ADR_RD_FFOUT_FULL (MB_REG_BASE+0x00000054)
+#define ADR_MB_THRESHOLD6 (MB_REG_BASE+0x0000006c)
+#define ADR_MB_THRESHOLD7 (MB_REG_BASE+0x00000070)
+#define ADR_MB_THRESHOLD8 (MB_REG_BASE+0x00000074)
+#define ADR_MB_THRESHOLD9 (MB_REG_BASE+0x00000078)
+#define ADR_MB_THRESHOLD10 (MB_REG_BASE+0x0000007c)
+#define ADR_MB_TRASH_CFG (MB_REG_BASE+0x00000080)
+#define ADR_MB_IN_FF_FLUSH (MB_REG_BASE+0x00000084)
+#define ADR_MB_IN_FF_FLUSH (MB_REG_BASE+0x00000084)
+#define ADR_CPU_ID_TB2 (MB_REG_BASE+0x00000088)
+#define ADR_CPU_ID_TB3 (MB_REG_BASE+0x0000008c)
+#define ADR_PHY_IQ_LOG_CFG0 (MB_REG_BASE+0x00000090)
+#define ADR_PHY_IQ_LOG_CFG1 (MB_REG_BASE+0x00000094)
+#define ADR_PHY_IQ_LOG_LEN (MB_REG_BASE+0x00000098)
+#define ADR_PHY_IQ_LOG_PTR (MB_REG_BASE+0x0000009c)
+#define ADR_WR_ALC (ID_MNG_REG_BASE+0x00000000)
+#define ADR_GETID (ID_MNG_REG_BASE+0x00000000)
+#define ADR_CH_STA_PRI (ID_MNG_REG_BASE+0x00000004)
+#define ADR_RD_ID0 (ID_MNG_REG_BASE+0x00000008)
+#define ADR_RD_ID1 (ID_MNG_REG_BASE+0x0000000c)
+#define ADR_IMD_CFG (ID_MNG_REG_BASE+0x00000010)
+#define ADR_IMD_STA (ID_MNG_REG_BASE+0x00000014)
+#define ADR_ALC_STA (ID_MNG_REG_BASE+0x00000018)
+#define ADR_TRX_ID_COUNT (ID_MNG_REG_BASE+0x0000001c)
+#define ADR_TRX_ID_THRESHOLD (ID_MNG_REG_BASE+0x00000020)
+#define ADR_TX_ID0 (ID_MNG_REG_BASE+0x00000024)
+#define ADR_TX_ID1 (ID_MNG_REG_BASE+0x00000028)
+#define ADR_RX_ID0 (ID_MNG_REG_BASE+0x0000002c)
+#define ADR_RX_ID1 (ID_MNG_REG_BASE+0x00000030)
+#define ADR_RTN_STA (ID_MNG_REG_BASE+0x00000034)
+#define ADR_ID_LEN_THREADSHOLD1 (ID_MNG_REG_BASE+0x00000038)
+#define ADR_ID_LEN_THREADSHOLD2 (ID_MNG_REG_BASE+0x0000003c)
+#define ADR_CH_ARB_PRI (ID_MNG_REG_BASE+0x00000040)
+#define ADR_TX_ID_REMAIN_STATUS (ID_MNG_REG_BASE+0x00000044)
+#define ADR_ID_INFO_STA (ID_MNG_REG_BASE+0x00000048)
+#define ADR_TX_LIMIT_INTR (ID_MNG_REG_BASE+0x0000004c)
+#define ADR_TX_ID_ALL_INFO (ID_MNG_REG_BASE+0x00000050)
+#define ADR_RD_ID2 (ID_MNG_REG_BASE+0x00000054)
+#define ADR_RD_ID3 (ID_MNG_REG_BASE+0x00000058)
+#define ADR_TX_ID2 (ID_MNG_REG_BASE+0x0000005c)
+#define ADR_TX_ID3 (ID_MNG_REG_BASE+0x00000060)
+#define ADR_RX_ID2 (ID_MNG_REG_BASE+0x00000064)
+#define ADR_RX_ID3 (ID_MNG_REG_BASE+0x00000068)
+#define ADR_TX_ID_ALL_INFO2 (ID_MNG_REG_BASE+0x0000006c)
+#define ADR_TX_ID_ALL_INFO_A (ID_MNG_REG_BASE+0x00000070)
+#define ADR_TX_ID_ALL_INFO_B (ID_MNG_REG_BASE+0x00000074)
+#define ADR_TX_ID_REMAIN_STATUS2 (ID_MNG_REG_BASE+0x00000078)
+#define ADR_ALC_ID_INFO (ID_MNG_REG_BASE+0x0000007c)
+#define ADR_ALC_ID_INF1 (ID_MNG_REG_BASE+0x00000080)
+#define ADR_ALC_ABORT (MMU_REG_BASE+0x00000004)
+#define ADR_ALC_RLS_STATUS (MMU_REG_BASE+0x00000008)
+#define ADR_DMN_STATUS (MMU_REG_BASE+0x0000000c)
+#define ADR_TAG_STATUS (MMU_REG_BASE+0x00000010)
+#define ADR_REQ_STATUS (MMU_REG_BASE+0x00000014)
+#define ADR_PAGE_TAG_STATUS_0 (MMU_REG_BASE+0x00000018)
+#define ADR_PAGE_TAG_STATUS_1 (MMU_REG_BASE+0x0000001c)
+#define ADR_PAGE_TAG_STATUS_2 (MMU_REG_BASE+0x00000020)
+#define ADR_PAGE_TAG_STATUS_3 (MMU_REG_BASE+0x00000024)
+#define ADR_PAGE_TAG_STATUS_4 (MMU_REG_BASE+0x00000028)
+#define ADR_PAGE_TAG_STATUS_5 (MMU_REG_BASE+0x0000002c)
+#define ADR_PAGE_TAG_STATUS_6 (MMU_REG_BASE+0x00000030)
+#define ADR_PAGE_TAG_STATUS_7 (MMU_REG_BASE+0x00000034)
+#define ADR_FPGA_GEMINIARF_SWITCH (CSR_TEMP_REG_BASE+0x00000030)
+#define GET_FBUS_DMAC_SAR0 (((REG32(ADR_FBUS_SAR0)) & 0xffffffff ) >> 0)
+#define GET_FBUS_DMAC_DAR0 (((REG32(ADR_FBUS_DAR0)) & 0xffffffff ) >> 0)
+#define GET_FBUS_DMAC_INTR_EN0 (((REG32(ADR_FBUS_CTL0_1)) & 0x00000001 ) >> 0)
+#define GET_FBUS_DMAC_DST_TR_WIDTH0 (((REG32(ADR_FBUS_CTL0_1)) & 0x0000000e ) >> 1)
+#define GET_FBUS_DMAC_SRC_TR_WIDTH0 (((REG32(ADR_FBUS_CTL0_1)) & 0x00000070 ) >> 4)
+#define GET_FBUS_DMAC_DINC0 (((REG32(ADR_FBUS_CTL0_1)) & 0x00000180 ) >> 7)
+#define GET_FBUS_DMAC_SINC0 (((REG32(ADR_FBUS_CTL0_1)) & 0x00000600 ) >> 9)
+#define GET_FBUS_DMAC_DST_MSIZE0 (((REG32(ADR_FBUS_CTL0_1)) & 0x00003800 ) >> 11)
+#define GET_FBUS_DMAC_SRC_MSIZE0 (((REG32(ADR_FBUS_CTL0_1)) & 0x0001c000 ) >> 14)
+#define GET_FBUS_DMAC_FC_MODE0 (((REG32(ADR_FBUS_CTL0_1)) & 0x00700000 ) >> 20)
+#define GET_FBUS_DMAC_BLOCK0 (((REG32(ADR_FBUS_CTL0_2)) & 0x00000fff ) >> 0)
+#define GET_FBUS_DMAC_CH0_PRIOR (((REG32(ADR_FBUS_CFG0_1)) & 0x00000020 ) >> 5)
+#define GET_FBUS_DMAC_HS_SEL_DST0 (((REG32(ADR_FBUS_CFG0_1)) & 0x00000400 ) >> 10)
+#define GET_FBUS_DMAC_HS_SEL_SRC0 (((REG32(ADR_FBUS_CFG0_1)) & 0x00000800 ) >> 11)
+#define GET_FBUS_DMAC_MAX_BURST_LEN0 (((REG32(ADR_FBUS_CFG0_1)) & 0x3ff00000 ) >> 20)
+#define GET_FBUS_DMAC_SRC_HS_BUS_SEL0 (((REG32(ADR_FBUS_CFG0_2)) & 0x00000380 ) >> 7)
+#define GET_FBUS_DMAC_DST_HS_BUS_SEL0 (((REG32(ADR_FBUS_CFG0_2)) & 0x00003800 ) >> 11)
+#define GET_FBUS_DMAC_SAR1 (((REG32(ADR_FBUS_SAR1)) & 0xffffffff ) >> 0)
+#define GET_FBUS_DMAC_DAR1 (((REG32(ADR_FBUS_DAR1)) & 0xffffffff ) >> 0)
+#define GET_FBUS_DMAC_INTR_EN1 (((REG32(ADR_FBUS_CTL1_1)) & 0x00000001 ) >> 0)
+#define GET_FBUS_DMAC_DST_TR_WIDTH1 (((REG32(ADR_FBUS_CTL1_1)) & 0x0000000e ) >> 1)
+#define GET_FBUS_DMAC_SRC_TR_WIDTH1 (((REG32(ADR_FBUS_CTL1_1)) & 0x00000070 ) >> 4)
+#define GET_FBUS_DMAC_DINC1 (((REG32(ADR_FBUS_CTL1_1)) & 0x00000180 ) >> 7)
+#define GET_FBUS_DMAC_SINC1 (((REG32(ADR_FBUS_CTL1_1)) & 0x00000600 ) >> 9)
+#define GET_FBUS_DMAC_DST_MSIZE1 (((REG32(ADR_FBUS_CTL1_1)) & 0x00003800 ) >> 11)
+#define GET_FBUS_DMAC_SRC_MSIZE1 (((REG32(ADR_FBUS_CTL1_1)) & 0x0001c000 ) >> 14)
+#define GET_FBUS_DMAC_FC_MODE1 (((REG32(ADR_FBUS_CTL1_1)) & 0x00700000 ) >> 20)
+#define GET_FBUS_DMAC_BLOCK1 (((REG32(ADR_FBUS_CTL1_2)) & 0x00000fff ) >> 0)
+#define GET_FBUS_DMAC_CH1_PRIOR (((REG32(ADR_FBUS_CFG1_1)) & 0x00000020 ) >> 5)
+#define GET_FBUS_DMAC_HS_SEL_DST1 (((REG32(ADR_FBUS_CFG1_1)) & 0x00000400 ) >> 10)
+#define GET_FBUS_DMAC_HS_SEL_SRC1 (((REG32(ADR_FBUS_CFG1_1)) & 0x00000800 ) >> 11)
+#define GET_FBUS_DMAC_MAX_BURST_LEN1 (((REG32(ADR_FBUS_CFG1_1)) & 0x3ff00000 ) >> 20)
+#define GET_FBUS_DMAC_SRC_HS_BUS_SEL1 (((REG32(ADR_FBUS_CFG1_2)) & 0x00000380 ) >> 7)
+#define GET_FBUS_DMAC_DST_HS_BUS_SEL1 (((REG32(ADR_FBUS_CFG1_2)) & 0x00003800 ) >> 11)
+#define GET_FBUS_DMAC_CH_RAW_TR (((REG32(ADR_FBUS_RAWTR)) & 0xffffffff ) >> 0)
+#define GET_FBUS_DMAC_CH_ERR_TR (((REG32(ADR_FBUS_RAWERR)) & 0xffffffff ) >> 0)
+#define GET_FBUS_DMAC_CH_STATUSTR_TR (((REG32(ADR_FBUS_STATUSTR)) & 0xffffffff ) >> 0)
+#define GET_FBUS_DMAC_CH_STATUSERR_TR (((REG32(ADR_FBUS_STATUSERR)) & 0xffffffff ) >> 0)
+#define GET_FBUS_DMAC_CH_DEMASK_TR (((REG32(ADR_FBUS_MASKTR)) & 0xffffffff ) >> 0)
+#define GET_FBUS_DMAC_CH_DEMASK_ERR (((REG32(ADR_FBUS_MASKERR)) & 0xffffffff ) >> 0)
+#define GET_FBUS_DMAC_CH0_CLR_TR (((REG32(ADR_FBUS_CLRTR)) & 0x00000001 ) >> 0)
+#define GET_FBUS_DMAC_CH1_CLR_TR (((REG32(ADR_FBUS_CLRTR)) & 0x00000002 ) >> 1)
+#define GET_FBUS_DMAC_CH0_CLR_ERR (((REG32(ADR_FBUS_CLRERR)) & 0x00000001 ) >> 0)
+#define GET_FBUS_DMAC_CH1_CLR_ERR (((REG32(ADR_FBUS_CLRERR)) & 0x00000002 ) >> 1)
+#define GET_FBUS_DMAC_DISEN_SHS_SRC_REQ (((REG32(ADR_FBUS_SHS_SRC_REQ_CFG)) & 0x0000ffff ) >> 0)
+#define GET_FBUS_DMAC_DISEN_SHS_DST_REQ (((REG32(ADR_FBUS_SHS_DST_REQ_CFG)) & 0x0000ffff ) >> 0)
+#define GET_FBUS_DMAC_DISEN_SHS_SRC_SREQ (((REG32(ADR_FBUS_SHS_SRC_SREQ_CFG)) & 0x0000ffff ) >> 0)
+#define GET_FBUS_DMAC_DISEN_SHS_DST_SREQ (((REG32(ADR_FBUS_SHS_DST_SREQ_CFG)) & 0x0000ffff ) >> 0)
+#define GET_FBUS_DMAC_EN (((REG32(ADR_FBUS_DMA_EN)) & 0x00000001 ) >> 0)
+#define GET_FBUS_DMAC_CH_EN (((REG32(ADR_FBUS_CH_EN)) & 0x0000ffff ) >> 0)
+#define GET_SBUS_DMAC_SAR0 (((REG32(ADR_SBUS_SAR0)) & 0xffffffff ) >> 0)
+#define GET_SBUS_DMAC_DAR0 (((REG32(ADR_SBUS_DAR0)) & 0xffffffff ) >> 0)
+#define GET_SBUS_DMAC_INTR_EN0 (((REG32(ADR_SBUS_CTL0_1)) & 0x00000001 ) >> 0)
+#define GET_SBUS_DMAC_DST_TR_WIDTH0 (((REG32(ADR_SBUS_CTL0_1)) & 0x0000000e ) >> 1)
+#define GET_SBUS_DMAC_SRC_TR_WIDTH0 (((REG32(ADR_SBUS_CTL0_1)) & 0x00000070 ) >> 4)
+#define GET_SBUS_DMAC_DINC0 (((REG32(ADR_SBUS_CTL0_1)) & 0x00000180 ) >> 7)
+#define GET_SBUS_DMAC_SINC0 (((REG32(ADR_SBUS_CTL0_1)) & 0x00000600 ) >> 9)
+#define GET_SBUS_DMAC_DST_MSIZE0 (((REG32(ADR_SBUS_CTL0_1)) & 0x00003800 ) >> 11)
+#define GET_SBUS_DMAC_SRC_MSIZE0 (((REG32(ADR_SBUS_CTL0_1)) & 0x0001c000 ) >> 14)
+#define GET_SBUS_DMAC_FC_MODE0 (((REG32(ADR_SBUS_CTL0_1)) & 0x00700000 ) >> 20)
+#define GET_SBUS_DMAC_BLOCK0 (((REG32(ADR_SBUS_CTL0_2)) & 0x00000fff ) >> 0)
+#define GET_SBUS_DMAC_CH0_PRIOR (((REG32(ADR_SBUS_CFG0_1)) & 0x00000020 ) >> 5)
+#define GET_SBUS_DMAC_HS_SEL_DST0 (((REG32(ADR_SBUS_CFG0_1)) & 0x00000400 ) >> 10)
+#define GET_SBUS_DMAC_HS_SEL_SRC0 (((REG32(ADR_SBUS_CFG0_1)) & 0x00000800 ) >> 11)
+#define GET_SBUS_DMAC_MAX_BURST_LEN0 (((REG32(ADR_SBUS_CFG0_1)) & 0x3ff00000 ) >> 20)
+#define GET_SBUS_DMAC_SRC_HS_BUS_SEL0 (((REG32(ADR_SBUS_CFG0_2)) & 0x00000380 ) >> 7)
+#define GET_SBUS_DMAC_DST_HS_BUS_SEL0 (((REG32(ADR_SBUS_CFG0_2)) & 0x00003800 ) >> 11)
+#define GET_SBUS_DMAC_SAR1 (((REG32(ADR_SBUS_SAR1)) & 0xffffffff ) >> 0)
+#define GET_SBUS_DMAC_DAR1 (((REG32(ADR_SBUS_DAR1)) & 0xffffffff ) >> 0)
+#define GET_SBUS_DMAC_INTR_EN1 (((REG32(ADR_SBUS_CTL1_1)) & 0x00000001 ) >> 0)
+#define GET_SBUS_DMAC_DST_TR_WIDTH1 (((REG32(ADR_SBUS_CTL1_1)) & 0x0000000e ) >> 1)
+#define GET_SBUS_DMAC_SRC_TR_WIDTH1 (((REG32(ADR_SBUS_CTL1_1)) & 0x00000070 ) >> 4)
+#define GET_SBUS_DMAC_DINC1 (((REG32(ADR_SBUS_CTL1_1)) & 0x00000180 ) >> 7)
+#define GET_SBUS_DMAC_SINC1 (((REG32(ADR_SBUS_CTL1_1)) & 0x00000600 ) >> 9)
+#define GET_SBUS_DMAC_DST_MSIZE1 (((REG32(ADR_SBUS_CTL1_1)) & 0x00003800 ) >> 11)
+#define GET_SBUS_DMAC_SRC_MSIZE1 (((REG32(ADR_SBUS_CTL1_1)) & 0x0001c000 ) >> 14)
+#define GET_SBUS_DMAC_FC_MODE1 (((REG32(ADR_SBUS_CTL1_1)) & 0x00700000 ) >> 20)
+#define GET_SBUS_DMAC_BLOCK1 (((REG32(ADR_SBUS_CTL1_2)) & 0x00000fff ) >> 0)
+#define GET_SBUS_DMAC_CH1_PRIOR (((REG32(ADR_SBUS_CFG1_1)) & 0x00000020 ) >> 5)
+#define GET_SBUS_DMAC_HS_SEL_DST1 (((REG32(ADR_SBUS_CFG1_1)) & 0x00000400 ) >> 10)
+#define GET_SBUS_DMAC_HS_SEL_SRC1 (((REG32(ADR_SBUS_CFG1_1)) & 0x00000800 ) >> 11)
+#define GET_SBUS_DMAC_MAX_BURST_LEN1 (((REG32(ADR_SBUS_CFG1_1)) & 0x3ff00000 ) >> 20)
+#define GET_SBUS_DMAC_SRC_HS_BUS_SEL1 (((REG32(ADR_SBUS_CFG1_2)) & 0x00000380 ) >> 7)
+#define GET_SBUS_DMAC_DST_HS_BUS_SEL1 (((REG32(ADR_SBUS_CFG1_2)) & 0x00003800 ) >> 11)
+#define GET_SBUS_DMAC_CH_RAW_TR (((REG32(ADR_SBUS_RAWTR)) & 0xffffffff ) >> 0)
+#define GET_SBUS_DMAC_CH_ERR_TR (((REG32(ADR_SBUS_RAWERR)) & 0xffffffff ) >> 0)
+#define GET_SBUS_DMAC_CH_STATUSTR_TR (((REG32(ADR_SBUS_STATUSTR)) & 0xffffffff ) >> 0)
+#define GET_SBUS_DMAC_CH_STATUSERR_TR (((REG32(ADR_SBUS_STATUSERR)) & 0xffffffff ) >> 0)
+#define GET_SBUS_DMAC_CH_DEMASK_TR (((REG32(ADR_SBUS_MASKTR)) & 0xffffffff ) >> 0)
+#define GET_SBUS_DMAC_CH_DEMASK_ERR (((REG32(ADR_SBUS_MASKERR)) & 0xffffffff ) >> 0)
+#define GET_SBUS_DMAC_CH0_CLR_TR (((REG32(ADR_SBUS_CLRTR)) & 0x00000001 ) >> 0)
+#define GET_SBUS_DMAC_CH1_CLR_TR (((REG32(ADR_SBUS_CLRTR)) & 0x00000002 ) >> 1)
+#define GET_SBUS_DMAC_CH0_CLR_ERR (((REG32(ADR_SBUS_CLRERR)) & 0x00000001 ) >> 0)
+#define GET_SBUS_DMAC_CH1_CLR_ERR (((REG32(ADR_SBUS_CLRERR)) & 0x00000002 ) >> 1)
+#define GET_SBUS_DMAC_DISEN_SHS_SRC_REQ (((REG32(ADR_SBUS_SHS_SRC_REQ_CFG)) & 0x0000ffff ) >> 0)
+#define GET_SBUS_DMAC_DISEN_SHS_DST_REQ (((REG32(ADR_SBUS_SHS_DST_REQ_CFG)) & 0x0000ffff ) >> 0)
+#define GET_SBUS_DMAC_DISEN_SHS_SRC_SREQ (((REG32(ADR_SBUS_SHS_SRC_SREQ_CFG)) & 0x0000ffff ) >> 0)
+#define GET_SBUS_DMAC_DISEN_SHS_DST_SREQ (((REG32(ADR_SBUS_SHS_DST_SREQ_CFG)) & 0x0000ffff ) >> 0)
+#define GET_SBUS_DMAC_EN (((REG32(ADR_SBUS_DMA_EN)) & 0x00000001 ) >> 0)
+#define GET_SBUS_DMAC_CH_EN (((REG32(ADR_SBUS_CH_EN)) & 0x0000ffff ) >> 0)
+#define GET_I2S_ENABLE (((REG32(ADR_I2S_EN)) & 0x00000001 ) >> 0)
+#define GET_I2S_RX_ENABLE (((REG32(ADR_I2S_RX_EN)) & 0x00000001 ) >> 0)
+#define GET_I2S_TX_ENABLE (((REG32(ADR_I2S_TX_EN)) & 0x00000001 ) >> 0)
+#define GET_I2S_SCLK_SOURCE_ENABLE (((REG32(ADR_I2S_SCLK_SCR_EN)) & 0x00000001 ) >> 0)
+#define GET_I2S_SCLK_GATE (((REG32(ADR_I2S_WS_DEF)) & 0x00000007 ) >> 0)
+#define GET_I2S_WS_LENGTH (((REG32(ADR_I2S_WS_DEF)) & 0x00000018 ) >> 3)
+#define GET_I2S_RST_RXFIFO (((REG32(ADR_RESET_RX_FIFO)) & 0x00000001 ) >> 0)
+#define GET_I2S_RST_TXFIFO (((REG32(ADR_RESET_TX_FIFO)) & 0x00000001 ) >> 0)
+#define GET_I2S_L_TRX_DATA (((REG32(ADR_L_TRX_DATA)) & 0xffffffff ) >> 0)
+#define GET_I2S_R_TRX_DATA (((REG32(ADR_R_TRX_DATA)) & 0xffffffff ) >> 0)
+#define GET_I2S_RX_CH_ENABLE (((REG32(ADR_I2S_RX_CH_EN)) & 0x00000001 ) >> 0)
+#define GET_I2S_TX_CH_ENABLE (((REG32(ADR_I2S_TX_CH_EN)) & 0x00000001 ) >> 0)
+#define GET_I2S_RX_WD_RES (((REG32(ADR_I2S_RX_WORD_RES)) & 0x00000007 ) >> 0)
+#define GET_I2S_TX_WD_RES (((REG32(ADR_I2S_TX_WORD_RES)) & 0x00000007 ) >> 0)
+#define GET_I2S_INTR_RXDA (((REG32(ADR_I2S_INTR)) & 0x00000001 ) >> 0)
+#define GET_I2S_INTR_RXFO (((REG32(ADR_I2S_INTR)) & 0x00000002 ) >> 1)
+#define GET_I2S_INTR_RXFE (((REG32(ADR_I2S_INTR)) & 0x00000010 ) >> 4)
+#define GET_I2S_INTR_TXFO (((REG32(ADR_I2S_INTR)) & 0x00000020 ) >> 5)
+#define GET_I2S_INTR_RXFA_MASK (((REG32(ADR_I2S_INTR_MASK)) & 0x00000001 ) >> 0)
+#define GET_I2S_INTR_RXFO_MASK (((REG32(ADR_I2S_INTR_MASK)) & 0x00000002 ) >> 1)
+#define GET_I2S_INTR_TXFE_MASK (((REG32(ADR_I2S_INTR_MASK)) & 0x00000010 ) >> 4)
+#define GET_I2S_INTR_TXFO_MASK (((REG32(ADR_I2S_INTR_MASK)) & 0x00000020 ) >> 5)
+#define GET_I2S_RXFO (((REG32(ADR_I2S_RXFO)) & 0x00000001 ) >> 0)
+#define GET_I2S_TXFO (((REG32(ADR_I2S_TXFO)) & 0x00000001 ) >> 0)
+#define GET_I2S_RX_FIFO_TH (((REG32(ADR_I2S_RX_FIFO_TH)) & 0x00000007 ) >> 0)
+#define GET_I2S_TX_FIFO_TH (((REG32(ADR_I2S_TX_FIFO_TH)) & 0x00000007 ) >> 0)
+#define GET_I2S_RX_FIFO_FLUSH (((REG32(ADR_I2S_RX_FIFO_FLUSH)) & 0x00000001 ) >> 0)
+#define GET_I2S_TX_FIFO_FLUSH (((REG32(ADR_I2S_TX_FIFO_FLUSH)) & 0x00000001 ) >> 0)
+#define GET_I2S_RX_DMA (((REG32(ADR_I2S_RX_DMA)) & 0xffffffff ) >> 0)
+#define GET_I2S_TX_DMA (((REG32(ADR_I2S_TX_DMA)) & 0xffffffff ) >> 0)
+#define GET_I2CMST_ENABLE_MASTER (((REG32(ADR_I2CMST_CFG0)) & 0x00000001 ) >> 0)
+#define GET_I2CMST_SPEED (((REG32(ADR_I2CMST_CFG0)) & 0x00000006 ) >> 1)
+#define GET_I2CMST_RESTART_EN (((REG32(ADR_I2CMST_CFG0)) & 0x00000020 ) >> 5)
+#define GET_I2CMST_DISABLE_SLAVE (((REG32(ADR_I2CMST_CFG0)) & 0x00000040 ) >> 6)
+#define GET_I2CMST_TAR (((REG32(ADR_I2CMST_TAR)) & 0x000003ff ) >> 0)
+#define GET_I2CMST_TRX_DATA (((REG32(ADR_I2CMST_TRX_CMD_DATA)) & 0x000000ff ) >> 0)
+#define GET_I2CMST_TRX_CMDW (((REG32(ADR_I2CMST_TRX_CMD_DATA)) & 0x00000100 ) >> 8)
+#define GET_I2CMST_TRX_STOPW (((REG32(ADR_I2CMST_TRX_CMD_DATA)) & 0x00000200 ) >> 9)
+#define GET_I2CMST_TRX_RESTARTW (((REG32(ADR_I2CMST_TRX_CMD_DATA)) & 0x00000400 ) >> 10)
+#define GET_I2CMST_RX_1STBRDYR (((REG32(ADR_I2CMST_TRX_CMD_DATA)) & 0x00000800 ) >> 11)
+#define GET_I2CMST_SCLK_H_WIDTH (((REG32(ADR_I2CMST_SCLK_H_WIDTH)) & 0x0000ffff ) >> 0)
+#define GET_I2CMST_SCLK_L_WIDTH (((REG32(ADR_I2CMST_SCLK_L_WIDTH)) & 0x0000ffff ) >> 0)
+#define GET_I2CMST_RXU_INT (((REG32(ADR_I2CMST_INT)) & 0x00000001 ) >> 0)
+#define GET_I2CMST_RXO_INT (((REG32(ADR_I2CMST_INT)) & 0x00000002 ) >> 1)
+#define GET_I2CMST_RXF_INT (((REG32(ADR_I2CMST_INT)) & 0x00000004 ) >> 2)
+#define GET_I2CMST_TXO_INT (((REG32(ADR_I2CMST_INT)) & 0x00000008 ) >> 3)
+#define GET_I2CMST_TXE_INT (((REG32(ADR_I2CMST_INT)) & 0x00000010 ) >> 4)
+#define GET_I2CMST_RXDONE_INT (((REG32(ADR_I2CMST_INT)) & 0x00000080 ) >> 7)
+#define GET_I2CMST_RXU_INT_MASK (((REG32(ADR_I2CMST_INT_MASK)) & 0x00000001 ) >> 0)
+#define GET_I2CMST_RXO_INT_MASK (((REG32(ADR_I2CMST_INT_MASK)) & 0x00000002 ) >> 1)
+#define GET_I2CMST_RXF_INT_MASK (((REG32(ADR_I2CMST_INT_MASK)) & 0x00000004 ) >> 2)
+#define GET_I2CMST_TXO_INT_MASK (((REG32(ADR_I2CMST_INT_MASK)) & 0x00000008 ) >> 3)
+#define GET_I2CMST_TXE_INT_MASK (((REG32(ADR_I2CMST_INT_MASK)) & 0x00000010 ) >> 4)
+#define GET_I2CMST_RXDONE_INT_MASK (((REG32(ADR_I2CMST_INT_MASK)) & 0x00000080 ) >> 7)
+#define GET_I2CMST_RXU_INT_STAR (((REG32(ADR_I2CMST_INT_STA)) & 0x00000001 ) >> 0)
+#define GET_I2CMST_RXO_INT_STAR (((REG32(ADR_I2CMST_INT_STA)) & 0x00000002 ) >> 1)
+#define GET_I2CMST_RXF_INT_STAR (((REG32(ADR_I2CMST_INT_STA)) & 0x00000004 ) >> 2)
+#define GET_I2CMST_TXO_INT_STAR (((REG32(ADR_I2CMST_INT_STA)) & 0x00000008 ) >> 3)
+#define GET_I2CMST_TXE_INT_STAR (((REG32(ADR_I2CMST_INT_STA)) & 0x00000010 ) >> 4)
+#define GET_I2CMST_RXDONE_INT_STAR (((REG32(ADR_I2CMST_INT_STA)) & 0x00000080 ) >> 7)
+#define GET_I2CMST_RX_FIFO_TH (((REG32(ADR_I2CMST_RX_FIFO_TH)) & 0x0000ffff ) >> 0)
+#define GET_I2CMST_TX_FIFO_TH (((REG32(ADR_I2CMST_TX_FIFO_TH)) & 0x0000ffff ) >> 0)
+#define GET_I2CMST_EN (((REG32(ADR_I2CMST_ENABLE)) & 0x00000001 ) >> 0)
+#define GET_SPIMST_DATA_LEN (((REG32(ADR_SPIMST_CFG0)) & 0x0000000f ) >> 0)
+#define GET_SPIMST_CPHA (((REG32(ADR_SPIMST_CFG0)) & 0x00000040 ) >> 6)
+#define GET_SPIMST_CPOL (((REG32(ADR_SPIMST_CFG0)) & 0x00000080 ) >> 7)
+#define GET_TRX_MODE (((REG32(ADR_SPIMST_CFG0)) & 0x00000300 ) >> 8)
+#define GET_DATA_FRAMES (((REG32(ADR_SPIMST_CFG1)) & 0x0000ffff ) >> 0)
+#define GET_SPIMST_ENABLE (((REG32(ADR_SPIMST_EN)) & 0x00000001 ) >> 0)
+#define GET_SPIMST_CEN_ENABLE (((REG32(ADR_SPIMST_CEN)) & 0x00000001 ) >> 0)
+#define GET_SPIMST_SCLK_RATE (((REG32(ADR_SPIMST_SCLK_RATE)) & 0x0000ffff ) >> 0)
+#define GET_SPIMST_TXFIFO_TH (((REG32(ADR_SPIMST_TXFIFO_TH)) & 0x0000000f ) >> 0)
+#define GET_SPIMST_RXFIFO_TH (((REG32(ADR_SPIMST_RXFIFO_TH)) & 0x0000000f ) >> 0)
+#define GET_TRXBUSYFLAG (((REG32(ADR_SPIMST_STATUS)) & 0x00000001 ) >> 0)
+#define GET_TXNOTFULLFLAG (((REG32(ADR_SPIMST_STATUS)) & 0x00000002 ) >> 1)
+#define GET_TXEMPTYFLAG (((REG32(ADR_SPIMST_STATUS)) & 0x00000004 ) >> 2)
+#define GET_RXNOTEMPTYFLAG (((REG32(ADR_SPIMST_STATUS)) & 0x00000008 ) >> 3)
+#define GET_RXFULLFLAG (((REG32(ADR_SPIMST_STATUS)) & 0x00000010 ) >> 4)
+#define GET_TXERRORFLAG (((REG32(ADR_SPIMST_STATUS)) & 0x00000020 ) >> 5)
+#define GET_SPIMST_TXE_INT_UNMASK (((REG32(ADR_SPIMST_INT_MASK)) & 0x00000001 ) >> 0)
+#define GET_SPIMST_TXO_INT_UNMASK (((REG32(ADR_SPIMST_INT_MASK)) & 0x00000002 ) >> 1)
+#define GET_SPIMST_RXU_INT_UNMASK (((REG32(ADR_SPIMST_INT_MASK)) & 0x00000004 ) >> 2)
+#define GET_SPIMST_RXO_INT_UNMASK (((REG32(ADR_SPIMST_INT_MASK)) & 0x00000008 ) >> 3)
+#define GET_SPIMST_RXF_INT_UNMASK (((REG32(ADR_SPIMST_INT_MASK)) & 0x00000010 ) >> 4)
+#define GET_SPIMST_TXE_INT (((REG32(ADR_SPIMST_INT)) & 0x00000001 ) >> 0)
+#define GET_SPIMST_TXO_INT (((REG32(ADR_SPIMST_INT)) & 0x00000002 ) >> 1)
+#define GET_SPIMST_RXU_INT (((REG32(ADR_SPIMST_INT)) & 0x00000004 ) >> 2)
+#define GET_SPIMST_RXO_INT (((REG32(ADR_SPIMST_INT)) & 0x00000008 ) >> 3)
+#define GET_SPIMST_RXF_INT (((REG32(ADR_SPIMST_INT)) & 0x00000010 ) >> 4)
+#define GET_SPIMST_TRX_DATA (((REG32(ADR_SPIMST_TRX_DATA)) & 0xffffffff ) >> 0)
+#define GET_SPIMST_RX_SAMPLE_DLY (((REG32(ADR_SPIMST_RX_SAMPLE_DLY)) & 0x000000ff ) >> 0)
+#define GET_MCU_ENABLE (((REG32(ADR_BRG_SW_RST)) & 0x00000001 ) >> 0)
+#define GET_MAC_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000002 ) >> 1)
+#define GET_USB_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000004 ) >> 2)
+#define GET_SDIO_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000008 ) >> 3)
+#define GET_SPI_SLV_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000010 ) >> 4)
+#define GET_UART_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000020 ) >> 5)
+#define GET_DMA_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000040 ) >> 6)
+#define GET_WDT_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000080 ) >> 7)
+#define GET_I2C_SLV_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000100 ) >> 8)
+#define GET_INT_CTL_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000200 ) >> 9)
+#define GET_BTCX_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000400 ) >> 10)
+#define GET_US0TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00001000 ) >> 12)
+#define GET_US1TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00002000 ) >> 13)
+#define GET_US2TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00004000 ) >> 14)
+#define GET_US3TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00008000 ) >> 15)
+#define GET_MS0TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00010000 ) >> 16)
+#define GET_MS1TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00020000 ) >> 17)
+#define GET_MS2TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00040000 ) >> 18)
+#define GET_MS3TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00080000 ) >> 19)
+#define GET_PLF_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00100000 ) >> 20)
+#define GET_ALL_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00200000 ) >> 21)
+#define GET_DAT_UART_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00400000 ) >> 22)
+#define GET_I2C_MST_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00800000 ) >> 23)
+#define GET_RG_REBOOT (((REG32(ADR_BOOT)) & 0x00000001 ) >> 0)
+#define GET_TRAP_IMG_FLS (((REG32(ADR_BOOT)) & 0x00010000 ) >> 16)
+#define GET_TRAP_REBOOT (((REG32(ADR_BOOT)) & 0x00020000 ) >> 17)
+#define GET_TRAP_BOOT_FLS (((REG32(ADR_BOOT)) & 0x00040000 ) >> 18)
+#define GET_CHIP_ID_31_0 (((REG32(ADR_CHIP_ID_0)) & 0xffffffff ) >> 0)
+#define GET_CHIP_ID_63_32 (((REG32(ADR_CHIP_ID_1)) & 0xffffffff ) >> 0)
+#define GET_CHIP_ID_95_64 (((REG32(ADR_CHIP_ID_2)) & 0xffffffff ) >> 0)
+#define GET_CHIP_ID_127_96 (((REG32(ADR_CHIP_ID_3)) & 0xffffffff ) >> 0)
+#define GET_CLK_DIGI_SEL (((REG32(ADR_CLOCK_SELECTION)) & 0x0000000f ) >> 0)
+#define GET_CLK_USB_PHY30M_SEL (((REG32(ADR_CLOCK_SELECTION)) & 0x00000010 ) >> 4)
+#define GET_SYS_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000001 ) >> 0)
+#define GET_MAC_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000002 ) >> 1)
+#define GET_FLASH_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000004 ) >> 2)
+#define GET_SDIO_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000008 ) >> 3)
+#define GET_SPI_SLV_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000010 ) >> 4)
+#define GET_UART_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000020 ) >> 5)
+#define GET_DMA_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000040 ) >> 6)
+#define GET_WDT_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000080 ) >> 7)
+#define GET_I2C_SLV_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000100 ) >> 8)
+#define GET_INT_CTL_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000200 ) >> 9)
+#define GET_BTCX_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000400 ) >> 10)
+#define GET_EFS_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000800 ) >> 11)
+#define GET_US0TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00001000 ) >> 12)
+#define GET_US1TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00002000 ) >> 13)
+#define GET_US2TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00004000 ) >> 14)
+#define GET_US3TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00008000 ) >> 15)
+#define GET_MS0TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00010000 ) >> 16)
+#define GET_MS1TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00020000 ) >> 17)
+#define GET_MS2TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00040000 ) >> 18)
+#define GET_MS3TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00080000 ) >> 19)
+#define GET_SPI_MST2CBRA_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00100000 ) >> 20)
+#define GET_AHB2PKT_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00200000 ) >> 21)
+#define GET_PWM_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00400000 ) >> 22)
+#define GET_I2C_MST_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00800000 ) >> 23)
+#define GET_RESET_N_CPUN10 (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x01000000 ) >> 24)
+#define GET_USB_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x02000000 ) >> 25)
+#define GET_CLK_EN_USB_PHY30M (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x04000000 ) >> 26)
+#define GET_CLK_EN_USB_CTRLUTMI (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x08000000 ) >> 27)
+#define GET_PHY_IQ_LOG_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x10000000 ) >> 28)
+#define GET_SPIMAS_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x20000000 ) >> 29)
+#define GET_I2S_PCLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x40000000 ) >> 30)
+#define GET_CLK_EN_PHYRF40M (((REG32(ADR_SYS_CSR_CLOCK_ENABLE)) & 0x00000001 ) >> 0)
+#define GET_CLK_EN_PHYRF80M (((REG32(ADR_SYS_CSR_CLOCK_ENABLE)) & 0x00000002 ) >> 1)
+#define GET_CLK_EN_160M_PHY (((REG32(ADR_SYS_CSR_CLOCK_ENABLE)) & 0x00000004 ) >> 2)
+#define GET_BTCX_CSR_CLK_EN (((REG32(ADR_SYS_CSR_CLOCK_ENABLE)) & 0x00000400 ) >> 10)
+#define GET_CLK_EN_MBIST (((REG32(ADR_SYS_CSR_CLOCK_ENABLE)) & 0x00000800 ) >> 11)
+#define GET_R_BOOTSTRAP_SAMPLE (((REG32(ADR_BOOTSTRAP_SAMPLE)) & 0x0000000f ) >> 0)
+#define GET_N10_CORE_CURRENT_PC (((REG32(ADR_N10_DBG1)) & 0xffffffff ) >> 0)
+#define GET_N10_STANDBY_REQ (((REG32(ADR_N10_DBG2)) & 0x08000000 ) >> 27)
+#define GET_N10_CORE_STANDBY_MODE (((REG32(ADR_N10_DBG2)) & 0x10000000 ) >> 28)
+#define GET_N10_CORE_DEBUG_MODE (((REG32(ADR_N10_DBG2)) & 0x20000000 ) >> 29)
+#define GET_N10_STANDBY (((REG32(ADR_N10_DBG2)) & 0x40000000 ) >> 30)
+#define GET_N10_WAKEUP_OK (((REG32(ADR_N10_DBG2)) & 0x80000000 ) >> 31)
+#define GET_SYS_CLOCK_STATE (((REG32(ADR_ROPMUSTATE)) & 0x00000007 ) >> 0)
+#define GET_ROM_READ_PROT (((REG32(ADR_ROM_READ_PROT)) & 0x00000001 ) >> 0)
+#define GET_GPIO_STOP_SEL (((REG32(ADR_GPIO_IQ_LOG_STOP)) & 0x007fffff ) >> 0)
+#define GET_GPIO_STOP_POL (((REG32(ADR_GPIO_IQ_LOG_STOP)) & 0x40000000 ) >> 30)
+#define GET_GPIO_STOP_EN (((REG32(ADR_GPIO_IQ_LOG_STOP)) & 0x80000000 ) >> 31)
+#define GET_TB_ADR_SEL (((REG32(ADR_TB_ADR_SEL)) & 0x0000ffff ) >> 0)
+#define GET_TB_CS (((REG32(ADR_TB_ADR_SEL)) & 0x80000000 ) >> 31)
+#define GET_TB_RDATA (((REG32(ADR_TB_RDATA)) & 0xffffffff ) >> 0)
+#define GET_UART_W2B_EN (((REG32(ADR_UART_W2B)) & 0x00000001 ) >> 0)
+#define GET_SYSCTRL_CMD (((REG32(ADR_SYSCTRL_COMMAND)) & 0xffffffff ) >> 0)
+#define GET_CLK_FBUS_SEL (((REG32(ADR_FBUS_CLK_SEL)) & 0x0000000f ) >> 0)
+#define GET_SYS_XOSC_ON (((REG32(ADR_SYSCTRL_STATUS)) & 0x00000001 ) >> 0)
+#define GET_SYS_DPLL_ON (((REG32(ADR_SYSCTRL_STATUS)) & 0x00000002 ) >> 1)
+#define GET_FSM_SYSCTRL (((REG32(ADR_SYSCTRL_STATUS)) & 0x00001f00 ) >> 8)
+#define GET_I2SMAS_CLK_DIV (((REG32(ADR_I2SMAS_CFG)) & 0x00003fff ) >> 0)
+#define GET_I2S_MCLK_DIV (((REG32(ADR_I2SMAS_CFG)) & 0x00030000 ) >> 16)
+#define GET_I2S_MASTER (((REG32(ADR_I2SMAS_CFG)) & 0x80000000 ) >> 31)
+#define GET_HBUSREQ_LOCK (((REG32(ADR_HBUSREQ_LOCK)) & 0x00001fff ) >> 0)
+#define GET_HBURST_LOCK (((REG32(ADR_HBURST_LOCK)) & 0x00001fff ) >> 0)
+#define GET_FENCE_HIT_ADR (((REG32(ADR_FENCE_CTRL)) & 0x001fffff ) >> 0)
+#define GET_EDLM_SRAM_ERRCK_EN (((REG32(ADR_FENCE_CTRL)) & 0x08000000 ) >> 27)
+#define GET_EILM_ROM_ERRCK_EN (((REG32(ADR_FENCE_CTRL)) & 0x10000000 ) >> 28)
+#define GET_EILM_SRAM_ERRCK_EN (((REG32(ADR_FENCE_CTRL)) & 0x20000000 ) >> 29)
+#define GET_FBUS_SRAM_ERRCK_EN (((REG32(ADR_FENCE_CTRL)) & 0x40000000 ) >> 30)
+#define GET_FENCE_HIT_EN (((REG32(ADR_FENCE_CTRL)) & 0x80000000 ) >> 31)
+#define GET_EDLM_SRAM_ERR_INT (((REG32(ADR_FENCE_STATUS)) & 0x00000001 ) >> 0)
+#define GET_EILM_ROM_ERR_INT (((REG32(ADR_FENCE_STATUS)) & 0x00000002 ) >> 1)
+#define GET_EILM_SRAM_ERR_INT (((REG32(ADR_FENCE_STATUS)) & 0x00000004 ) >> 2)
+#define GET_FBUS_SRAM_ERR_INT (((REG32(ADR_FENCE_STATUS)) & 0x00000008 ) >> 3)
+#define GET_FENCE_HIT_INT (((REG32(ADR_FENCE_STATUS)) & 0x00000010 ) >> 4)
+#define GET_TOP_SW_PWR_ON1_OUTPUT_PWR_ON1_1_0_0 (((REG32(ADR_POWER_SW_INFO)) & 0x00000001 ) >> 0)
+#define GET_TOP_SW_PWR_ON2_OUTPUT_PWR_ON2_1_0_0 (((REG32(ADR_POWER_SW_INFO)) & 0x00000002 ) >> 1)
+#define GET_TOP_SW_PWR_ON3_OUTPUT_PWR_ON3_1_0_0 (((REG32(ADR_POWER_SW_INFO)) & 0x00000004 ) >> 2)
+#define GET_VIAROM_EMA (((REG32(ADR_VIAROM_EMA)) & 0x00000007 ) >> 0)
+#define GET_TEST_MODE0 (((REG32(ADR_TEST_MODE)) & 0x00000001 ) >> 0)
+#define GET_TEST_MODE1 (((REG32(ADR_TEST_MODE)) & 0x00000002 ) >> 1)
+#define GET_TEST_MODE2 (((REG32(ADR_TEST_MODE)) & 0x00000004 ) >> 2)
+#define GET_TEST_MODE3 (((REG32(ADR_TEST_MODE)) & 0x00000008 ) >> 3)
+#define GET_TEST_MODE4 (((REG32(ADR_TEST_MODE)) & 0x00000010 ) >> 4)
+#define GET_TEST_MODE_ALL (((REG32(ADR_TEST_MODE)) & 0x00000020 ) >> 5)
+#define GET_CLK_EN_CPUN10 (((REG32(ADR_MANUAL_RESET_N)) & 0x00000002 ) >> 1)
+#define GET_N10_WARM_RESET_N (((REG32(ADR_MANUAL_RESET_N)) & 0x00000004 ) >> 2)
+#define GET_FW_EVENT (((REG32(ADR_DEBUG_FIRMWARE_EVENT_FLAG)) & 0xffffffff ) >> 0)
+#define GET_HOST_EVENT (((REG32(ADR_DEBUG_HOST_EVENT_FLAG)) & 0xffffffff ) >> 0)
+#define GET_CHIP_INFO_ID_31_0 (((REG32(ADR_CHIP_INFO_ID_0)) & 0xffffffff ) >> 0)
+#define GET_CHIP_INFO_ID_63_32 (((REG32(ADR_CHIP_INFO_ID_1)) & 0xffffffff ) >> 0)
+#define GET_CHIP_VER (((REG32(ADR_CHIP_TYPE_VER)) & 0x00ffffff ) >> 0)
+#define GET_CHIP_TYPE (((REG32(ADR_CHIP_TYPE_VER)) & 0xff000000 ) >> 24)
+#define GET_CHIP_DATE_YYYYMMDD (((REG32(ADR_CHIP_DATE_YYYYMMDD)) & 0xffffffff ) >> 0)
+#define GET_CHIP_DATE_00HHMMSS (((REG32(ADR_CHIP_DATE_00HHMMSS)) & 0x00ffffff ) >> 0)
+#define GET_CHIP_GITSHA_31_0 (((REG32(ADR_CHIP_GITSHA_0)) & 0xffffffff ) >> 0)
+#define GET_CHIP_GITSHA_63_32 (((REG32(ADR_CHIP_GITSHA_1)) & 0xffffffff ) >> 0)
+#define GET_CHIP_GITSHA_95_64 (((REG32(ADR_CHIP_GITSHA_2)) & 0xffffffff ) >> 0)
+#define GET_CHIP_GITSHA_127_96 (((REG32(ADR_CHIP_GITSHA_3)) & 0xffffffff ) >> 0)
+#define GET_CHIP_GITSHA_159_128 (((REG32(ADR_CHIP_GITSHA_4)) & 0xffffffff ) >> 0)
+#define GET_N10CFG_DEFAULT_IVB (((REG32(ADR_N10CFG_DEF_IVB)) & 0x0000ffff ) >> 0)
+#define GET_SYS_N10_IVB_VAL (((REG32(ADR_N10CFG_SETTING)) & 0xffff0000 ) >> 16)
+#define GET_USB20_HOST_SELRW (((REG32(ADR_USB20_HOST_SEL)) & 0x00000001 ) >> 0)
+#define GET_CHIP_INFO_FPGA_TAG (((REG32(ADR_CHIP_INFO_FPGATAG)) & 0xffffffff ) >> 0)
+#define GET_SYS_PMU_MODE_TRAN_INT (((REG32(ADR_PMU_MODE_TRAN_INT)) & 0x00000001 ) >> 0)
+#define GET_DBG_WRITE_TO_FINISH_SIM (((REG32(ADR_DEBUG_SIM_FINISH)) & 0x00000001 ) >> 0)
+#define GET_DATA_SPI_WAKEUP (((REG32(ADR_ALWAYS_ON_CFG00)) & 0x00000001 ) >> 0)
+#define GET_WAKE_SOON_WITH_SCK (((REG32(ADR_SDIO_RESET_WAKE_CFG)) & 0x00000001 ) >> 0)
+#define GET_ALLOW_SD_SPI_RESET (((REG32(ADR_SDIO_RESET_WAKE_CFG)) & 0x00000002 ) >> 1)
+#define GET_WDT_MCU_RESET (((REG32(ADR_BOOT_INFO)) & 0x00000001 ) >> 0)
+#define GET_WDT_SYS_RESET (((REG32(ADR_BOOT_INFO)) & 0x00000002 ) >> 1)
+#define GET_SDIO_CMD52_06H_RESET (((REG32(ADR_BOOT_INFO)) & 0x00000004 ) >> 2)
+#define GET_DATA_SPI_RESET (((REG32(ADR_BOOT_INFO)) & 0x00000008 ) >> 3)
+#define GET_UART_NRTS (((REG32(ADR_SPARE_UART_INFO)) & 0x00000001 ) >> 0)
+#define GET_UART_NCTS (((REG32(ADR_SPARE_UART_INFO)) & 0x00000002 ) >> 1)
+#define GET_NORMAL_PWR_ON1 (((REG32(ADR_POWER_ON_OFF_CTRL)) & 0x00000001 ) >> 0)
+#define GET_NORMAL_PWR_ON2 (((REG32(ADR_POWER_ON_OFF_CTRL)) & 0x00000002 ) >> 1)
+#define GET_NORMAL_PWR_ON3 (((REG32(ADR_POWER_ON_OFF_CTRL)) & 0x00000004 ) >> 2)
+#define GET_SUSPEND_PWR_ON1 (((REG32(ADR_POWER_ON_OFF_CTRL)) & 0x00000010 ) >> 4)
+#define GET_SUSPEND_PWR_ON2 (((REG32(ADR_POWER_ON_OFF_CTRL)) & 0x00000020 ) >> 5)
+#define GET_SUSPEND_PWR_ON3 (((REG32(ADR_POWER_ON_OFF_CTRL)) & 0x00000040 ) >> 6)
+#define GET_NORMAL_ISO_ON1 (((REG32(ADR_POWER_ON_OFF_CTRL)) & 0x00000100 ) >> 8)
+#define GET_NORMAL_ISO_ON2 (((REG32(ADR_POWER_ON_OFF_CTRL)) & 0x00000200 ) >> 9)
+#define GET_NORMAL_ISO_ON3 (((REG32(ADR_POWER_ON_OFF_CTRL)) & 0x00000400 ) >> 10)
+#define GET_TOP_ON1_RST_N (((REG32(ADR_POWER_ON_OFF_CTRL)) & 0x00001000 ) >> 12)
+#define GET_TOP_ON2_RST_N (((REG32(ADR_POWER_ON_OFF_CTRL)) & 0x00002000 ) >> 13)
+#define GET_TOP_ON3_RST_N (((REG32(ADR_POWER_ON_OFF_CTRL)) & 0x00004000 ) >> 14)
+#define GET_HOST_WAKE_WIFI (((REG32(ADR_HOST_WAKE_WIFI_CTRL)) & 0x007fffff ) >> 0)
+#define GET_HOST_WAKE_WIFI_POL (((REG32(ADR_HOST_WAKE_WIFI_CTRL)) & 0x80000000 ) >> 31)
+#define GET_PRESCALER_US (((REG32(ADR_PRESCALER_USTIMER)) & 0x000001ff ) >> 0)
+#define GET_RTC_TIMER_WAKE_PMU_EN (((REG32(ADR_WAKE_PMU_ENABLE)) & 0x00000001 ) >> 0)
+#define GET_USB_WAKE_PMU_EN (((REG32(ADR_WAKE_PMU_ENABLE)) & 0x00000002 ) >> 1)
+#define GET_ILM160KB_EN (((REG32(ADR_SRAMCFG_SETTING)) & 0x00000002 ) >> 1)
+#define GET_PATCH00_EN (((REG32(ADR_ROM_PATCH00_0)) & 0x00000001 ) >> 0)
+#define GET_PATCH00_ADDR (((REG32(ADR_ROM_PATCH00_0)) & 0x0001fffc ) >> 2)
+#define GET_PATCH00_DATA (((REG32(ADR_ROM_PATCH00_1)) & 0xffffffff ) >> 0)
+#define GET_PATCH01_EN (((REG32(ADR_ROM_PATCH01_0)) & 0x00000001 ) >> 0)
+#define GET_PATCH01_ADDR (((REG32(ADR_ROM_PATCH01_0)) & 0x0001fffc ) >> 2)
+#define GET_PATCH01_DATA (((REG32(ADR_ROM_PATCH01_1)) & 0xffffffff ) >> 0)
+#define GET_TU0_TM_INIT_VALUE (((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TU0_TM_MODE (((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TU0_TM_INT_STS_DONE (((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TU0_TM_INT_MASK (((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TU0_TM_CUR_VALUE (((REG32(ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_TU0_PRESCALER_USTIMER_LOCAL (((REG32(ADR_TU0_MICROSECOND_TIMER_LOCAL_PRESCALE)) & 0x000001ff ) >> 0)
+#define GET_TU1_TM_INIT_VALUE (((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TU1_TM_MODE (((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TU1_TM_INT_STS_DONE (((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TU1_TM_INT_MASK (((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TU1_TM_CUR_VALUE (((REG32(ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_TU1_PRESCALER_USTIMER_LOCAL (((REG32(ADR_TU1_MICROSECOND_TIMER_LOCAL_PRESCALE)) & 0x000001ff ) >> 0)
+#define GET_TU2_TM_INIT_VALUE (((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TU2_TM_MODE (((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TU2_TM_INT_STS_DONE (((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TU2_TM_INT_MASK (((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TU2_TM_CUR_VALUE (((REG32(ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_TU2_PRESCALER_USTIMER_LOCAL (((REG32(ADR_TU2_MICROSECOND_TIMER_LOCAL_PRESCALE)) & 0x000001ff ) >> 0)
+#define GET_TU3_TM_INIT_VALUE (((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TU3_TM_MODE (((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TU3_TM_INT_STS_DONE (((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TU3_TM_INT_MASK (((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TU3_TM_CUR_VALUE (((REG32(ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_TU3_PRESCALER_USTIMER_LOCAL (((REG32(ADR_TU3_MICROSECOND_TIMER_LOCAL_PRESCALE)) & 0x000001ff ) >> 0)
+#define GET_TM0_TM_INIT_VALUE (((REG32(ADR_TM0_MILLISECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TM0_TM_MODE (((REG32(ADR_TM0_MILLISECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TM0_TM_INT_STS_DONE (((REG32(ADR_TM0_MILLISECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TM0_TM_INT_MASK (((REG32(ADR_TM0_MILLISECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TM0_TM_CUR_VALUE (((REG32(ADR_TM0_CURRENT_MILLISECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_TM0_PRESCALER_USTIMER_LOCAL (((REG32(ADR_TM0_MILLISECOND_TIMER_PRESCALE)) & 0x000001ff ) >> 0)
+#define GET_TM1_TM_INIT_VALUE (((REG32(ADR_TM1_MILLISECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TM1_TM_MODE (((REG32(ADR_TM1_MILLISECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TM1_TM_INT_STS_DONE (((REG32(ADR_TM1_MILLISECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TM1_TM_INT_MASK (((REG32(ADR_TM1_MILLISECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TM1_TM_CUR_VALUE (((REG32(ADR_TM1_CURRENT_MILLISECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_TM1_PRESCALER_USTIMER_LOCAL (((REG32(ADR_TM1_MILLISECOND_TIMER_PRESCALE)) & 0x000001ff ) >> 0)
+#define GET_TM2_TM_INIT_VALUE (((REG32(ADR_TM2_MILLISECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TM2_TM_MODE (((REG32(ADR_TM2_MILLISECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TM2_TM_INT_STS_DONE (((REG32(ADR_TM2_MILLISECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TM2_TM_INT_MASK (((REG32(ADR_TM2_MILLISECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TM2_TM_CUR_VALUE (((REG32(ADR_TM2_CURRENT_MILLISECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_TM2_PRESCALER_USTIMER_LOCAL (((REG32(ADR_TM2_MILLISECOND_TIMER_PRESCALE)) & 0x000001ff ) >> 0)
+#define GET_TM3_TM_INIT_VALUE (((REG32(ADR_TM3_MILLISECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TM3_TM_MODE (((REG32(ADR_TM3_MILLISECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TM3_TM_INT_STS_DONE (((REG32(ADR_TM3_MILLISECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TM3_TM_INT_MASK (((REG32(ADR_TM3_MILLISECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TM3_TM_CUR_VALUE (((REG32(ADR_TM3_CURRENT_MILLISECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_TM3_PRESCALER_USTIMER_LOCAL (((REG32(ADR_TM3_MILLISECOND_TIMER_PRESCALE)) & 0x000001ff ) >> 0)
+#define GET_MCU_WDT_TIME_CNT (((REG32(ADR_MCU_WDOG_REG)) & 0x0000ffff ) >> 0)
+#define GET_MCU_WDT_INT_CNT_OFS (((REG32(ADR_MCU_WDOG_REG)) & 0x00ff0000 ) >> 16)
+#define GET_MCU_WDT_STATUS (((REG32(ADR_MCU_WDOG_REG)) & 0x40000000 ) >> 30)
+#define GET_MCU_WDOG_ENA (((REG32(ADR_MCU_WDOG_REG)) & 0x80000000 ) >> 31)
+#define GET_SYS_WDT_TIME_CNT (((REG32(ADR_SYS_WDOG_REG)) & 0x0000ffff ) >> 0)
+#define GET_SYS_WDT_INT_CNT_OFS (((REG32(ADR_SYS_WDOG_REG)) & 0x00ff0000 ) >> 16)
+#define GET_SYS_WDT_STATUS (((REG32(ADR_SYS_WDOG_REG)) & 0x40000000 ) >> 30)
+#define GET_SYS_WDOG_ENA (((REG32(ADR_SYS_WDOG_REG)) & 0x80000000 ) >> 31)
+#define GET_PWM_POST_SCALER_0 (((REG32(ADR_PWM_0_CTRL)) & 0x000000ff ) >> 0)
+#define GET_PWM_SETTING_UPDATE_0 (((REG32(ADR_PWM_0_CTRL)) & 0x10000000 ) >> 28)
+#define GET_PWM_ALWAYSON_0 (((REG32(ADR_PWM_0_CTRL)) & 0x20000000 ) >> 29)
+#define GET_PWM_INVERT_0 (((REG32(ADR_PWM_0_CTRL)) & 0x40000000 ) >> 30)
+#define GET_PWM_ENABLE_0 (((REG32(ADR_PWM_0_CTRL)) & 0x80000000 ) >> 31)
+#define GET_PWM_INI_VALUE_PERIOD_0 (((REG32(ADR_PWM_0_SET)) & 0x0000ffff ) >> 0)
+#define GET_PWM_INI_VALUE_P_0 (((REG32(ADR_PWM_0_SET)) & 0xffff0000 ) >> 16)
+#define GET_PWM_POST_SCALER_1 (((REG32(ADR_PWM_1_CTRL)) & 0x000000ff ) >> 0)
+#define GET_PWM_SETTING_UPDATE_1 (((REG32(ADR_PWM_1_CTRL)) & 0x10000000 ) >> 28)
+#define GET_PWM_ALWAYSON_1 (((REG32(ADR_PWM_1_CTRL)) & 0x20000000 ) >> 29)
+#define GET_PWM_INVERT_1 (((REG32(ADR_PWM_1_CTRL)) & 0x40000000 ) >> 30)
+#define GET_PWM_ENABLE_1 (((REG32(ADR_PWM_1_CTRL)) & 0x80000000 ) >> 31)
+#define GET_PWM_INI_VALUE_PERIOD_1 (((REG32(ADR_PWM_1_SET)) & 0x0000ffff ) >> 0)
+#define GET_PWM_INI_VALUE_P_1 (((REG32(ADR_PWM_1_SET)) & 0xffff0000 ) >> 16)
+#define GET_PWM_POST_SCALER_2 (((REG32(ADR_PWM_2_CTRL)) & 0x000000ff ) >> 0)
+#define GET_PWM_SETTING_UPDATE_2 (((REG32(ADR_PWM_2_CTRL)) & 0x10000000 ) >> 28)
+#define GET_PWM_ALWAYSON_2 (((REG32(ADR_PWM_2_CTRL)) & 0x20000000 ) >> 29)
+#define GET_PWM_INVERT_2 (((REG32(ADR_PWM_2_CTRL)) & 0x40000000 ) >> 30)
+#define GET_PWM_ENABLE_2 (((REG32(ADR_PWM_2_CTRL)) & 0x80000000 ) >> 31)
+#define GET_PWM_INI_VALUE_PERIOD_2 (((REG32(ADR_PWM_2_SET)) & 0x0000ffff ) >> 0)
+#define GET_PWM_INI_VALUE_P_2 (((REG32(ADR_PWM_2_SET)) & 0xffff0000 ) >> 16)
+#define GET_PWM_POST_SCALER_3 (((REG32(ADR_PWM_3_CTRL)) & 0x000000ff ) >> 0)
+#define GET_PWM_SETTING_UPDATE_3 (((REG32(ADR_PWM_3_CTRL)) & 0x10000000 ) >> 28)
+#define GET_PWM_ALWAYSON_3 (((REG32(ADR_PWM_3_CTRL)) & 0x20000000 ) >> 29)
+#define GET_PWM_INVERT_3 (((REG32(ADR_PWM_3_CTRL)) & 0x40000000 ) >> 30)
+#define GET_PWM_ENABLE_3 (((REG32(ADR_PWM_3_CTRL)) & 0x80000000 ) >> 31)
+#define GET_PWM_INI_VALUE_PERIOD_3 (((REG32(ADR_PWM_3_SET)) & 0x0000ffff ) >> 0)
+#define GET_PWM_INI_VALUE_P_3 (((REG32(ADR_PWM_3_SET)) & 0xffff0000 ) >> 16)
+#define GET_PWM_POST_SCALER_4 (((REG32(ADR_PWM_4_CTRL)) & 0x000000ff ) >> 0)
+#define GET_PWM_SETTING_UPDATE_4 (((REG32(ADR_PWM_4_CTRL)) & 0x10000000 ) >> 28)
+#define GET_PWM_ALWAYSON_4 (((REG32(ADR_PWM_4_CTRL)) & 0x20000000 ) >> 29)
+#define GET_PWM_INVERT_4 (((REG32(ADR_PWM_4_CTRL)) & 0x40000000 ) >> 30)
+#define GET_PWM_ENABLE_4 (((REG32(ADR_PWM_4_CTRL)) & 0x80000000 ) >> 31)
+#define GET_PWM_INI_VALUE_PERIOD_4 (((REG32(ADR_PWM_4_SET)) & 0x0000ffff ) >> 0)
+#define GET_PWM_INI_VALUE_P_4 (((REG32(ADR_PWM_4_SET)) & 0xffff0000 ) >> 16)
+#define GET_MANUAL_IO (((REG32(ADR_MANUAL_IO)) & 0x007fffff ) >> 0)
+#define GET_MANUAL_PU (((REG32(ADR_MANUAL_PU)) & 0x007fffff ) >> 0)
+#define GET_MANUAL_PD (((REG32(ADR_MANUAL_PD)) & 0x007fffff ) >> 0)
+#define GET_MANUAL_DS (((REG32(ADR_MANUAL_DS)) & 0x007fffff ) >> 0)
+#define GET_IO_PO (((REG32(ADR_IO_PO)) & 0x007fffff ) >> 0)
+#define GET_IO_PI (((REG32(ADR_IO_PI)) & 0x007fffff ) >> 0)
+#define GET_IO_PIE (((REG32(ADR_IO_PIE)) & 0x007fffff ) >> 0)
+#define GET_IO_POEN (((REG32(ADR_IO_POEN)) & 0x007fffff ) >> 0)
+#define GET_IO_PUE (((REG32(ADR_IO_PUE)) & 0x007fffff ) >> 0)
+#define GET_IO_PDE (((REG32(ADR_IO_PDE)) & 0x007fffff ) >> 0)
+#define GET_IO_DS (((REG32(ADR_IO_DS)) & 0x007fffff ) >> 0)
+#define GET_SEL_I2STRX_II (((REG32(ADR_IO_FUNC_SEL)) & 0x00000001 ) >> 0)
+#define GET_SEL_I2STRX_I (((REG32(ADR_IO_FUNC_SEL)) & 0x00000002 ) >> 1)
+#define GET_SEL_SPI_SLV (((REG32(ADR_IO_FUNC_SEL)) & 0x00000004 ) >> 2)
+#define GET_SEL_SPI_MST (((REG32(ADR_IO_FUNC_SEL)) & 0x00000008 ) >> 3)
+#define GET_SEL_I2C_SLV (((REG32(ADR_IO_FUNC_SEL)) & 0x00000010 ) >> 4)
+#define GET_SEL_I2C_MST_II (((REG32(ADR_IO_FUNC_SEL)) & 0x00000020 ) >> 5)
+#define GET_SEL_I2C_MST_I (((REG32(ADR_IO_FUNC_SEL)) & 0x00000040 ) >> 6)
+#define GET_SEL_UART0_II (((REG32(ADR_IO_FUNC_SEL)) & 0x00000080 ) >> 7)
+#define GET_SEL_UART0_I (((REG32(ADR_IO_FUNC_SEL)) & 0x00000100 ) >> 8)
+#define GET_SEL_BTCX (((REG32(ADR_IO_FUNC_SEL)) & 0x00000200 ) >> 9)
+#define GET_SEL_FLASH (((REG32(ADR_IO_FUNC_SEL)) & 0x00000400 ) >> 10)
+#define GET_SEL_RF (((REG32(ADR_IO_FUNC_SEL)) & 0x00000800 ) >> 11)
+#define GET_SEL_PWM (((REG32(ADR_IO_FUNC_SEL)) & 0x0001f000 ) >> 12)
+#define GET_SEL_DEBUG_I (((REG32(ADR_IO_FUNC_SEL)) & 0x00020000 ) >> 17)
+#define GET_SEL_DEBUG_II (((REG32(ADR_IO_FUNC_SEL)) & 0x00040000 ) >> 18)
+#define GET_SEL_MEM_BIST (((REG32(ADR_IO_FUNC_SEL)) & 0x00080000 ) >> 19)
+#define GET_SEL_USB_BIST (((REG32(ADR_IO_FUNC_SEL)) & 0x00100000 ) >> 20)
+#define GET_SEL_USB_TEST (((REG32(ADR_IO_FUNC_SEL)) & 0x00200000 ) >> 21)
+#define GET_SEL_USB_IDDQ (((REG32(ADR_IO_FUNC_SEL)) & 0x00400000 ) >> 22)
+#define GET_I2S_RAW_DATA (((REG32(ADR_IO_FUNC_SEL)) & 0x40000000 ) >> 30)
+#define GET_SPI_RAW_DATA (((REG32(ADR_IO_FUNC_SEL)) & 0x80000000 ) >> 31)
+#define GET_SEL_GPO_INT (((REG32(ADR_INT_THRU_GPIO)) & 0x007fffff ) >> 0)
+#define GET_ROM_START_INDEX (((REG32(ADR_BIST_CTRL)) & 0x0000000f ) >> 0)
+#define GET_ROM_END_INDEX (((REG32(ADR_BIST_CTRL)) & 0x000000f0 ) >> 4)
+#define GET_ROMCRC32_GOLDEN (((REG32(ADR_BIST_CTRL1)) & 0xffffffff ) >> 0)
+#define GET_ROMCRC32_RESULT (((REG32(ADR_BIST_CTRL2)) & 0xffffffff ) >> 0)
+#define GET_I2CS_ADDR_DC (((REG32(ADR_I2CS_ID_ADDR)) & 0x00000001 ) >> 0)
+#define GET_I2CS_ADDR (((REG32(ADR_I2CS_ID_ADDR)) & 0x000000fe ) >> 1)
+#define GET_I2CS_INT (((REG32(ADR_I2CS_STATUS)) & 0x0000001f ) >> 0)
+#define GET_I2CS_IDLE (((REG32(ADR_I2CS_STATUS)) & 0x00000400 ) >> 10)
+#define GET_I2CS_TIME_OUT_CNT (((REG32(ADR_I2CS_TIME_CNT)) & 0x0000ffff ) >> 0)
+#define GET_I2CS_STATE (((REG32(ADR_I2CS_STATE)) & 0x000000ff ) >> 0)
+#define GET_I2CS_DATA_CONFIG (((REG32(ADR_I2CS_CTRL)) & 0x00000001 ) >> 0)
+#define GET_I2CS_HOLD_BUS_EN (((REG32(ADR_I2CS_CTRL)) & 0x00000002 ) >> 1)
+#define GET_IO_PORT_REG (((REG32(ADR_IO_PORT_REG)) & 0x0001ffff ) >> 0)
+#define GET_MASK_RX_INT (((REG32(ADR_INT_MASK_REG)) & 0x00000001 ) >> 0)
+#define GET_EDCA4_LOW_THR_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000002 ) >> 1)
+#define GET_MASK_SOC_SYSTEM_INT (((REG32(ADR_INT_MASK_REG)) & 0x00000004 ) >> 2)
+#define GET_EDCA0_LOW_THR_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000008 ) >> 3)
+#define GET_EDCA1_LOW_THR_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000010 ) >> 4)
+#define GET_EDCA2_LOW_THR_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000020 ) >> 5)
+#define GET_EDCA3_LOW_THR_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000040 ) >> 6)
+#define GET_TX_LIMIT_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000080 ) >> 7)
+#define GET_RX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000001 ) >> 0)
+#define GET_EDCA4_LOW_THR_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000002 ) >> 1)
+#define GET_SOC_SYSTEM_INT_STATUS (((REG32(ADR_INT_STATUS_REG)) & 0x00000004 ) >> 2)
+#define GET_EDCA0_LOW_THR_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000008 ) >> 3)
+#define GET_EDCA1_LOW_THR_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000010 ) >> 4)
+#define GET_EDCA2_LOW_THR_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000020 ) >> 5)
+#define GET_EDCA3_LOW_THR_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000040 ) >> 6)
+#define GET_TX_LIMIT_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000080 ) >> 7)
+#define GET_HOST_TRIGGERED_RX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000100 ) >> 8)
+#define GET_HOST_TRIGGERED_TX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000200 ) >> 9)
+#define GET_SOC_TRIGGER_RX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000400 ) >> 10)
+#define GET_SOC_TRIGGER_TX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000800 ) >> 11)
+#define GET_RDY_FOR_TX_RX (((REG32(ADR_FN1_STATUS_REG)) & 0x00000001 ) >> 0)
+#define GET_RDY_FOR_FW_DOWNLOAD (((REG32(ADR_FN1_STATUS_REG)) & 0x00000002 ) >> 1)
+#define GET_ILLEGAL_CMD_RESP_OPTION (((REG32(ADR_FN1_STATUS_REG)) & 0x00000004 ) >> 2)
+#define GET_SDIO_TRX_DATA_SEQUENCE (((REG32(ADR_FN1_STATUS_REG)) & 0x00000008 ) >> 3)
+#define GET_GPIO_INT_TRIGGER_OPTION (((REG32(ADR_FN1_STATUS_REG)) & 0x00000010 ) >> 4)
+#define GET_TRIGGER_FUNCTION_SETTING (((REG32(ADR_FN1_STATUS_REG)) & 0x00000060 ) >> 5)
+#define GET_CMD52_ABORT_RESPONSE (((REG32(ADR_FN1_STATUS_REG)) & 0x00000080 ) >> 7)
+#define GET_CARD_RCA_REG (((REG32(ADR_CARD_RCA_REG)) & 0x0000ffff ) >> 0)
+#define GET_SDIO_BYTE_MODE_BATCH_SIZE_REG (((REG32(ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG)) & 0x000000ff ) >> 0)
+#define GET_SDIO_CARD_STATUS_REG (((REG32(ADR_SDIO_CARD_STATUS_REG)) & 0xffffffff ) >> 0)
+#define GET_R5_RESPONSE_FLAG (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x000000ff ) >> 0)
+#define GET_MCU_TO_SDIO_INFO_MASK (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x00010000 ) >> 16)
+#define GET_INT_THROUGH_PIN (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x00020000 ) >> 17)
+#define GET_DIRECT_INT_MUX_MODE (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x00040000 ) >> 18)
+#define GET_SD_CMD_IN_DLY_SEL (((REG32(ADR_SDIO_DELAY_CHAIN_0)) & 0x00000007 ) >> 0)
+#define GET_SD_CMD_OUT_DLY_SEL (((REG32(ADR_SDIO_DELAY_CHAIN_0)) & 0x00000070 ) >> 4)
+#define GET_SD_DAT_3_IN_DLY_SEL (((REG32(ADR_SDIO_DELAY_CHAIN_0)) & 0x00000700 ) >> 8)
+#define GET_SD_DAT_3_OUT_DLY_SEL (((REG32(ADR_SDIO_DELAY_CHAIN_0)) & 0x00007000 ) >> 12)
+#define GET_SD_DAT_2_IN_DLY_SEL (((REG32(ADR_SDIO_DELAY_CHAIN_0)) & 0x00070000 ) >> 16)
+#define GET_SD_DAT_2_OUT_DLY_SEL (((REG32(ADR_SDIO_DELAY_CHAIN_0)) & 0x00700000 ) >> 20)
+#define GET_SD_DAT_1_IN_DLY_SEL (((REG32(ADR_SDIO_DELAY_CHAIN_0)) & 0x07000000 ) >> 24)
+#define GET_SD_DAT_1_OUT_DLY_SEL (((REG32(ADR_SDIO_DELAY_CHAIN_0)) & 0x70000000 ) >> 28)
+#define GET_SD_DAT_0_IN_DLY_SEL (((REG32(ADR_SDIO_DELAY_CHAIN_1)) & 0x00000007 ) >> 0)
+#define GET_SD_DAT_0_OUT_DLY_SEL (((REG32(ADR_SDIO_DELAY_CHAIN_1)) & 0x00000070 ) >> 4)
+#define GET_FN1_DMA_START_ADDR_REG (((REG32(ADR_FN1_DMA_START_ADDR_REG)) & 0xffffffff ) >> 0)
+#define GET_SDIO_TO_MCU_INFO (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x000000ff ) >> 0)
+#define GET_SDIO_PARTIAL_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00000100 ) >> 8)
+#define GET_SDIO_ALL_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00000200 ) >> 9)
+#define GET_PERI_MAC_ALL_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00000400 ) >> 10)
+#define GET_MAC_ALL_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00000800 ) >> 11)
+#define GET_AHB_BRIDGE_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00001000 ) >> 12)
+#define GET_MCU_TO_SDIO_INFO (((REG32(ADR_MCU_NOTIFY_HOST_EVENT)) & 0x000000ff ) >> 0)
+#define GET_FN1_DMA_RD_START_ADDR_REG (((REG32(ADR_FN1_DMA_RD_START_ADDR_REG)) & 0xffffffff ) >> 0)
+#define GET_CCCR_00H_REG (((REG32(ADR_CCCR_00H_REG)) & 0x000000ff ) >> 0)
+#define GET_CCCR_02H_REG (((REG32(ADR_CCCR_00H_REG)) & 0x00ff0000 ) >> 16)
+#define GET_CCCR_03H_REG (((REG32(ADR_CCCR_00H_REG)) & 0xff000000 ) >> 24)
+#define GET_CCCR_04H_REG (((REG32(ADR_CCCR_04H_REG)) & 0x000000ff ) >> 0)
+#define GET_CCCR_05H_REG (((REG32(ADR_CCCR_04H_REG)) & 0x0000ff00 ) >> 8)
+#define GET_CCCR_06H_REG (((REG32(ADR_CCCR_04H_REG)) & 0x000f0000 ) >> 16)
+#define GET_CCCR_07H_REG (((REG32(ADR_CCCR_04H_REG)) & 0xff000000 ) >> 24)
+#define GET_SUPPORT_DIRECT_COMMAND_SDIO (((REG32(ADR_CCCR_08H_REG)) & 0x00000001 ) >> 0)
+#define GET_SUPPORT_MULTIPLE_BLOCK_TRANSFER (((REG32(ADR_CCCR_08H_REG)) & 0x00000002 ) >> 1)
+#define GET_SUPPORT_READ_WAIT (((REG32(ADR_CCCR_08H_REG)) & 0x00000004 ) >> 2)
+#define GET_SUPPORT_BUS_CONTROL (((REG32(ADR_CCCR_08H_REG)) & 0x00000008 ) >> 3)
+#define GET_SUPPORT_BLOCK_GAP_INTERRUPT (((REG32(ADR_CCCR_08H_REG)) & 0x00000010 ) >> 4)
+#define GET_ENABLE_BLOCK_GAP_INTERRUPT (((REG32(ADR_CCCR_08H_REG)) & 0x00000020 ) >> 5)
+#define GET_LOW_SPEED_CARD (((REG32(ADR_CCCR_08H_REG)) & 0x00000040 ) >> 6)
+#define GET_LOW_SPEED_CARD_4BIT (((REG32(ADR_CCCR_08H_REG)) & 0x00000080 ) >> 7)
+#define GET_COMMON_CIS_PONTER (((REG32(ADR_CCCR_08H_REG)) & 0x01ffff00 ) >> 8)
+#define GET_SD_SSDR50 (((REG32(ADR_CCCR_14H_REG)) & 0x01000000 ) >> 24)
+#define GET_SD_SSDR104 (((REG32(ADR_CCCR_14H_REG)) & 0x02000000 ) >> 25)
+#define GET_SUPPORT_HIGH_SPEED (((REG32(ADR_CCCR_13H_REG)) & 0x01000000 ) >> 24)
+#define GET_BSS (((REG32(ADR_CCCR_13H_REG)) & 0x0e000000 ) >> 25)
+#define GET_FBR_100H_REG (((REG32(ADR_FBR_100H_REG)) & 0x0000000f ) >> 0)
+#define GET_CSASUPPORT (((REG32(ADR_FBR_100H_REG)) & 0x00000040 ) >> 6)
+#define GET_ENABLECSA (((REG32(ADR_FBR_100H_REG)) & 0x00000080 ) >> 7)
+#define GET_FBR_101H_REG (((REG32(ADR_FBR_100H_REG)) & 0x0000ff00 ) >> 8)
+#define GET_FBR_109H_REG (((REG32(ADR_FBR_109H_REG)) & 0x01ffff00 ) >> 8)
+#define GET_F0_CIS_CONTENT_REG_31_0 (((REG32(ADR_F0_CIS_CONTENT_REG_0)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_63_32 (((REG32(ADR_F0_CIS_CONTENT_REG_1)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_95_64 (((REG32(ADR_F0_CIS_CONTENT_REG_2)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_127_96 (((REG32(ADR_F0_CIS_CONTENT_REG_3)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_159_128 (((REG32(ADR_F0_CIS_CONTENT_REG_4)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_191_160 (((REG32(ADR_F0_CIS_CONTENT_REG_5)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_223_192 (((REG32(ADR_F0_CIS_CONTENT_REG_6)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_255_224 (((REG32(ADR_F0_CIS_CONTENT_REG_7)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_287_256 (((REG32(ADR_F0_CIS_CONTENT_REG_8)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_319_288 (((REG32(ADR_F0_CIS_CONTENT_REG_9)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_351_320 (((REG32(ADR_F0_CIS_CONTENT_REG_10)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_383_352 (((REG32(ADR_F0_CIS_CONTENT_REG_11)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_415_384 (((REG32(ADR_F0_CIS_CONTENT_REG_12)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_447_416 (((REG32(ADR_F0_CIS_CONTENT_REG_13)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_479_448 (((REG32(ADR_F0_CIS_CONTENT_REG_14)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_511_480 (((REG32(ADR_F0_CIS_CONTENT_REG_15)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_31_0 (((REG32(ADR_F1_CIS_CONTENT_REG_0)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_63_32 (((REG32(ADR_F1_CIS_CONTENT_REG_1)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_95_64 (((REG32(ADR_F1_CIS_CONTENT_REG_2)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_127_96 (((REG32(ADR_F1_CIS_CONTENT_REG_3)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_159_128 (((REG32(ADR_F1_CIS_CONTENT_REG_4)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_191_160 (((REG32(ADR_F1_CIS_CONTENT_REG_5)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_223_192 (((REG32(ADR_F1_CIS_CONTENT_REG_6)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_255_224 (((REG32(ADR_F1_CIS_CONTENT_REG_7)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_287_256 (((REG32(ADR_F1_CIS_CONTENT_REG_8)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_319_288 (((REG32(ADR_F1_CIS_CONTENT_REG_9)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_351_320 (((REG32(ADR_F1_CIS_CONTENT_REG_10)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_383_352 (((REG32(ADR_F1_CIS_CONTENT_REG_11)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_415_384 (((REG32(ADR_F1_CIS_CONTENT_REG_12)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_447_416 (((REG32(ADR_F1_CIS_CONTENT_REG_13)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_479_448 (((REG32(ADR_F1_CIS_CONTENT_REG_14)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_511_480 (((REG32(ADR_F1_CIS_CONTENT_REG_15)) & 0xffffffff ) >> 0)
+#define GET_SPARE_MEM (((REG32(ADR_SPI_MODE)) & 0x000000ff ) >> 0)
+#define GET_TX_SEG (((REG32(ADR_TX_SEG)) & 0xffffffff ) >> 0)
+#define GET_CLK_WIDTH (((REG32(ADR_SPI_TO_PHY_PARAM1)) & 0x0000ffff ) >> 0)
+#define GET_CSN_INTER (((REG32(ADR_SPI_TO_PHY_PARAM1)) & 0xffff0000 ) >> 16)
+#define GET_BACK_DLY (((REG32(ADR_SPI_TO_PHY_PARAM2)) & 0x0000ffff ) >> 0)
+#define GET_FRONT_DLY (((REG32(ADR_SPI_TO_PHY_PARAM2)) & 0xffff0000 ) >> 16)
+#define GET_TWI_START_TRIG (((REG32(ADR_TWIM_EN)) & 0x00000001 ) >> 0)
+#define GET_TWI_STOP_TRIG (((REG32(ADR_TWIM_EN)) & 0x00000002 ) >> 1)
+#define GET_TWI_TRANS_CONTINUE (((REG32(ADR_TWIM_EN)) & 0x00000004 ) >> 2)
+#define GET_TWI_DEV_A_10B (((REG32(ADR_TWIM_STATUS_SETTING)) & 0x00000001 ) >> 0)
+#define GET_TWI_MODE (((REG32(ADR_TWIM_STATUS_SETTING)) & 0x00000002 ) >> 1)
+#define GET_SCL (((REG32(ADR_TWIM_STATUS_SETTING)) & 0x00010000 ) >> 16)
+#define GET_SDA (((REG32(ADR_TWIM_STATUS_SETTING)) & 0x00020000 ) >> 17)
+#define GET_TWI_INT_TXD_STALL_EN (((REG32(ADR_TWIM_INTERRUPT_EN)) & 0x00000001 ) >> 0)
+#define GET_TWI_INT_RXD_STALL_EN (((REG32(ADR_TWIM_INTERRUPT_EN)) & 0x00000002 ) >> 1)
+#define GET_TWI_INT_TRANS_FINISH_EN (((REG32(ADR_TWIM_INTERRUPT_EN)) & 0x00000004 ) >> 2)
+#define GET_TWI_INT_MISMATCH_EN (((REG32(ADR_TWIM_INTERRUPT_EN)) & 0x00000008 ) >> 3)
+#define GET_TWI_INT_TRANS_FAIL_EN (((REG32(ADR_TWIM_INTERRUPT_EN)) & 0x00000010 ) >> 4)
+#define GET_TWI_INT_HOLD_BUS_EN (((REG32(ADR_TWIM_INTERRUPT_EN)) & 0x00000020 ) >> 5)
+#define GET_TWI_INT_TXD_STALL (((REG32(ADR_TWIM_INTERRUPT)) & 0x00000001 ) >> 0)
+#define GET_TWI_INT_RXD_STALL (((REG32(ADR_TWIM_INTERRUPT)) & 0x00000002 ) >> 1)
+#define GET_TWI_INT_TRANS_FINISH (((REG32(ADR_TWIM_INTERRUPT)) & 0x00000004 ) >> 2)
+#define GET_TWI_INT_MISMATCH (((REG32(ADR_TWIM_INTERRUPT)) & 0x00000008 ) >> 3)
+#define GET_TWI_INT_TRANS_FAIL (((REG32(ADR_TWIM_INTERRUPT)) & 0x00000010 ) >> 4)
+#define GET_TWI_INT_HOLD_BUS (((REG32(ADR_TWIM_INTERRUPT)) & 0x00000020 ) >> 5)
+#define GET_TWI_INT_TXD_STALL_ST (((REG32(ADR_TWIM_INTERRUPT_STATUS)) & 0x00000001 ) >> 0)
+#define GET_TWI_INT_RXD_STALL_ST (((REG32(ADR_TWIM_INTERRUPT_STATUS)) & 0x00000002 ) >> 1)
+#define GET_TWI_INT_TRANS_FINISH_ST (((REG32(ADR_TWIM_INTERRUPT_STATUS)) & 0x00000004 ) >> 2)
+#define GET_TWI_INT_MISMATCH_ST (((REG32(ADR_TWIM_INTERRUPT_STATUS)) & 0x00000008 ) >> 3)
+#define GET_TWI_INT_TRANS_FAIL_ST (((REG32(ADR_TWIM_INTERRUPT_STATUS)) & 0x00000010 ) >> 4)
+#define GET_TWI_INT_HOLD_BUS_ST (((REG32(ADR_TWIM_INTERRUPT_STATUS)) & 0x00000020 ) >> 5)
+#define GET_TWI_STATUS_RECORD_0 (((REG32(ADR_TWIM_STATUS_RECORD_0)) & 0xffffffff ) >> 0)
+#define GET_TWI_STATUS_RECORD_1 (((REG32(ADR_TWIM_STATUS_RECORD_1)) & 0xffffffff ) >> 0)
+#define GET_TWI_RX (((REG32(ADR_TWIM_DEV_A)) & 0x00000001 ) >> 0)
+#define GET_TWI_DEV_A10B (((REG32(ADR_TWIM_DEV_A)) & 0x000007fe ) >> 1)
+#define GET_TWI_TXD_DATA (((REG32(ADR_TWIM_TXD_DATA)) & 0x000000ff ) >> 0)
+#define GET_TWI_RXD_DATA (((REG32(ADR_TWIM_RXD_DATA)) & 0x000000ff ) >> 0)
+#define GET_TWI_PSCL (((REG32(ADR_TWIM_PSCL)) & 0x000003ff ) >> 0)
+#define GET_TWI_STA_STO_PSCL (((REG32(ADR_TWIM_PSCL)) & 0x03ff0000 ) >> 16)
+#define GET_TWI_TRANS_PSDA (((REG32(ADR_TWIM_TRANS_PSDA)) & 0x000003ff ) >> 0)
+#define GET_TWI_DELAY_ACK (((REG32(ADR_TWIM_DELAY_ACK)) & 0x000003ff ) >> 0)
+#define GET_I2CM_INT_WDONE (((REG32(ADR_I2CM_EN)) & 0x00000001 ) >> 0)
+#define GET_I2CM_INT_RDONE (((REG32(ADR_I2CM_EN)) & 0x00000002 ) >> 1)
+#define GET_I2CM_IDLE (((REG32(ADR_I2CM_EN)) & 0x00000004 ) >> 2)
+#define GET_I2CM_INT_MISMATCH (((REG32(ADR_I2CM_EN)) & 0x00000008 ) >> 3)
+#define GET_I2CM_PSCL (((REG32(ADR_I2CM_EN)) & 0x00003ff0 ) >> 4)
+#define GET_I2CM_MANUAL_MODE (((REG32(ADR_I2CM_EN)) & 0x00010000 ) >> 16)
+#define GET_I2CM_INT_WDATA_NEED (((REG32(ADR_I2CM_EN)) & 0x00020000 ) >> 17)
+#define GET_I2CM_INT_RDATA_NEED (((REG32(ADR_I2CM_EN)) & 0x00040000 ) >> 18)
+#define GET_I2CM_DEV_A (((REG32(ADR_I2CM_DEV_A)) & 0x000003ff ) >> 0)
+#define GET_I2CM_DEV_A10B (((REG32(ADR_I2CM_DEV_A)) & 0x00004000 ) >> 14)
+#define GET_I2CM_RX (((REG32(ADR_I2CM_DEV_A)) & 0x00008000 ) >> 15)
+#define GET_I2CM_LEN (((REG32(ADR_I2CM_LEN)) & 0x0000ffff ) >> 0)
+#define GET_I2CM_T_LEFT (((REG32(ADR_I2CM_LEN)) & 0x00070000 ) >> 16)
+#define GET_I2CM_R_GET (((REG32(ADR_I2CM_LEN)) & 0x07000000 ) >> 24)
+#define GET_I2CM_WDAT (((REG32(ADR_I2CM_WDAT)) & 0xffffffff ) >> 0)
+#define GET_I2CM_RDAT (((REG32(ADR_I2CM_RDAT)) & 0xffffffff ) >> 0)
+#define GET_I2CM_SR_LEN (((REG32(ADR_I2CM_EN_2)) & 0x0000ffff ) >> 0)
+#define GET_I2CM_SR_RX (((REG32(ADR_I2CM_EN_2)) & 0x00010000 ) >> 16)
+#define GET_I2CM_REPEAT_START (((REG32(ADR_I2CM_EN_2)) & 0x00020000 ) >> 17)
+#define GET_I2CM_STA_STO_PSCL (((REG32(ADR_I2CM_START_STOP_PERIOD)) & 0x000003ff ) >> 0)
+#define GET_UART_DATA (((REG32(ADR_UART_DATA)) & 0x000000ff ) >> 0)
+#define GET_DATA_RDY_IE (((REG32(ADR_UART_IER)) & 0x00000001 ) >> 0)
+#define GET_THR_EMPTY_IE (((REG32(ADR_UART_IER)) & 0x00000002 ) >> 1)
+#define GET_RX_LINESTS_IE (((REG32(ADR_UART_IER)) & 0x00000004 ) >> 2)
+#define GET_MDM_STS_IE (((REG32(ADR_UART_IER)) & 0x00000008 ) >> 3)
+#define GET_TX_THRH_IE (((REG32(ADR_UART_IER)) & 0x00000010 ) >> 4)
+#define GET_TX_THRL_IE (((REG32(ADR_UART_IER)) & 0x00000020 ) >> 5)
+#define GET_FIFO_EN (((REG32(ADR_UART_FCR)) & 0x00000001 ) >> 0)
+#define GET_RXFIFO_RST (((REG32(ADR_UART_FCR)) & 0x00000002 ) >> 1)
+#define GET_TXFIFO_RST (((REG32(ADR_UART_FCR)) & 0x00000004 ) >> 2)
+#define GET_DMA_MODE (((REG32(ADR_UART_FCR)) & 0x00000008 ) >> 3)
+#define GET_EN_AUTO_RTS (((REG32(ADR_UART_FCR)) & 0x00000010 ) >> 4)
+#define GET_EN_AUTO_CTS (((REG32(ADR_UART_FCR)) & 0x00000020 ) >> 5)
+#define GET_RXFIFO_TRGLVL (((REG32(ADR_UART_FCR)) & 0x000000c0 ) >> 6)
+#define GET_WORD_LEN (((REG32(ADR_UART_LCR)) & 0x00000003 ) >> 0)
+#define GET_STOP_BIT (((REG32(ADR_UART_LCR)) & 0x00000004 ) >> 2)
+#define GET_PARITY_EN (((REG32(ADR_UART_LCR)) & 0x00000008 ) >> 3)
+#define GET_EVEN_PARITY (((REG32(ADR_UART_LCR)) & 0x00000010 ) >> 4)
+#define GET_FORCE_PARITY (((REG32(ADR_UART_LCR)) & 0x00000020 ) >> 5)
+#define GET_SET_BREAK (((REG32(ADR_UART_LCR)) & 0x00000040 ) >> 6)
+#define GET_DLAB (((REG32(ADR_UART_LCR)) & 0x00000080 ) >> 7)
+#define GET_DTR (((REG32(ADR_UART_MCR)) & 0x00000001 ) >> 0)
+#define GET_RTS (((REG32(ADR_UART_MCR)) & 0x00000002 ) >> 1)
+#define GET_OUT_1 (((REG32(ADR_UART_MCR)) & 0x00000004 ) >> 2)
+#define GET_OUT_2 (((REG32(ADR_UART_MCR)) & 0x00000008 ) >> 3)
+#define GET_LOOP_BACK (((REG32(ADR_UART_MCR)) & 0x00000010 ) >> 4)
+#define GET_DE_RTS (((REG32(ADR_UART_MCR)) & 0x00000020 ) >> 5)
+#define GET_DATA_RDY (((REG32(ADR_UART_LSR)) & 0x00000001 ) >> 0)
+#define GET_OVERRUN_ERR (((REG32(ADR_UART_LSR)) & 0x00000002 ) >> 1)
+#define GET_PARITY_ERR (((REG32(ADR_UART_LSR)) & 0x00000004 ) >> 2)
+#define GET_FRAMING_ERR (((REG32(ADR_UART_LSR)) & 0x00000008 ) >> 3)
+#define GET_BREAK_INT (((REG32(ADR_UART_LSR)) & 0x00000010 ) >> 4)
+#define GET_THR_EMPTY (((REG32(ADR_UART_LSR)) & 0x00000020 ) >> 5)
+#define GET_TX_EMPTY (((REG32(ADR_UART_LSR)) & 0x00000040 ) >> 6)
+#define GET_FIFODATA_ERR (((REG32(ADR_UART_LSR)) & 0x00000080 ) >> 7)
+#define GET_DELTA_CTS (((REG32(ADR_UART_MSR)) & 0x00000001 ) >> 0)
+#define GET_DELTA_DSR (((REG32(ADR_UART_MSR)) & 0x00000002 ) >> 1)
+#define GET_TRAILEDGE_RI (((REG32(ADR_UART_MSR)) & 0x00000004 ) >> 2)
+#define GET_DELTA_CD (((REG32(ADR_UART_MSR)) & 0x00000008 ) >> 3)
+#define GET_CTS (((REG32(ADR_UART_MSR)) & 0x00000010 ) >> 4)
+#define GET_DSR (((REG32(ADR_UART_MSR)) & 0x00000020 ) >> 5)
+#define GET_RI (((REG32(ADR_UART_MSR)) & 0x00000040 ) >> 6)
+#define GET_CD (((REG32(ADR_UART_MSR)) & 0x00000080 ) >> 7)
+#define GET_BRDC_DIV (((REG32(ADR_UART_SPR)) & 0x0000ffff ) >> 0)
+#define GET_RTHR_L (((REG32(ADR_UART_RTHR)) & 0x0000000f ) >> 0)
+#define GET_RTHR_H (((REG32(ADR_UART_RTHR)) & 0x000000f0 ) >> 4)
+#define GET_INT_IDCODE (((REG32(ADR_UART_ISR)) & 0x0000000f ) >> 0)
+#define GET_RX_IDLE (((REG32(ADR_UART_ISR)) & 0x00000010 ) >> 4)
+#define GET_TX_IDLE (((REG32(ADR_UART_ISR)) & 0x00000020 ) >> 5)
+#define GET_FIFOS_ENABLED (((REG32(ADR_UART_ISR)) & 0x000000c0 ) >> 6)
+#define GET_TTHR_L (((REG32(ADR_UART_TTHR)) & 0x0000000f ) >> 0)
+#define GET_TTHR_H (((REG32(ADR_UART_TTHR)) & 0x000000f0 ) >> 4)
+#define GET_RX_RECIEVED (((REG32(ADR_UART_INT_MAP)) & 0x00000001 ) >> 0)
+#define GET_RX_FIFO_TO (((REG32(ADR_UART_INT_MAP)) & 0x00000002 ) >> 1)
+#define GET_TX_L (((REG32(ADR_UART_INT_MAP)) & 0x00000004 ) >> 2)
+#define GET_TX_H (((REG32(ADR_UART_INT_MAP)) & 0x00000008 ) >> 3)
+#define GET_TX_EMPTY2 (((REG32(ADR_UART_INT_MAP)) & 0x00000010 ) >> 4)
+#define GET_OVERRUN (((REG32(ADR_UART_INT_MAP)) & 0x00000020 ) >> 5)
+#define GET_FRAMING (((REG32(ADR_UART_INT_MAP)) & 0x00000040 ) >> 6)
+#define GET_BREAK (((REG32(ADR_UART_INT_MAP)) & 0x00000080 ) >> 7)
+#define GET_PARITY (((REG32(ADR_UART_INT_MAP)) & 0x00000100 ) >> 8)
+#define GET_MODEN_INT (((REG32(ADR_UART_INT_MAP)) & 0x00000200 ) >> 9)
+#define GET_ROP_A (((REG32(ADR_UART_POINTER)) & 0x0000000f ) >> 0)
+#define GET_RIP_A (((REG32(ADR_UART_POINTER)) & 0x000000f0 ) >> 4)
+#define GET_TOP_A (((REG32(ADR_UART_POINTER)) & 0x00000f00 ) >> 8)
+#define GET_TIP_A (((REG32(ADR_UART_POINTER)) & 0x0000f000 ) >> 12)
+#define GET_HSUART_RXD (((REG32(ADR_HSUART_TRX_CHAR)) & 0x000000ff ) >> 0)
+#define GET_HSUART_ENABRXBUFF (((REG32(ADR_HSUART_INTRRUPT_ENABLE)) & 0x00000001 ) >> 0)
+#define GET_HSUART_ENABTXBUFF (((REG32(ADR_HSUART_INTRRUPT_ENABLE)) & 0x00000002 ) >> 1)
+#define GET_HSUART_ENABLNSTAT (((REG32(ADR_HSUART_INTRRUPT_ENABLE)) & 0x00000004 ) >> 2)
+#define GET_HSUART_ENABMDSTAT (((REG32(ADR_HSUART_INTRRUPT_ENABLE)) & 0x00000008 ) >> 3)
+#define GET_HSUART_ENABCTXTHR (((REG32(ADR_HSUART_INTRRUPT_ENABLE)) & 0x00000010 ) >> 4)
+#define GET_HSUART_ENABDMARXEND (((REG32(ADR_HSUART_INTRRUPT_ENABLE)) & 0x00000040 ) >> 6)
+#define GET_HSUART_ENABDMATXEND (((REG32(ADR_HSUART_INTRRUPT_ENABLE)) & 0x00000080 ) >> 7)
+#define GET_HSUART_FIFOE (((REG32(ADR_HSUART_FIFO_CTRL)) & 0x00000001 ) >> 0)
+#define GET_HSUART_RX_FIFO_RST (((REG32(ADR_HSUART_FIFO_CTRL)) & 0x00000002 ) >> 1)
+#define GET_HSUART_TX_FIFO_RST (((REG32(ADR_HSUART_FIFO_CTRL)) & 0x00000004 ) >> 2)
+#define GET_HSUART_DMA (((REG32(ADR_HSUART_FIFO_CTRL)) & 0x00000008 ) >> 3)
+#define GET_HSUART_RX_TRIG_LV (((REG32(ADR_HSUART_FIFO_CTRL)) & 0x000000c0 ) >> 6)
+#define GET_HSUART_WLS (((REG32(ADR_HSUART_LINE_CTRL)) & 0x00000003 ) >> 0)
+#define GET_HSUART_STB (((REG32(ADR_HSUART_LINE_CTRL)) & 0x00000004 ) >> 2)
+#define GET_HSUART_PEN (((REG32(ADR_HSUART_LINE_CTRL)) & 0x00000008 ) >> 3)
+#define GET_HSUART_SP_EPS (((REG32(ADR_HSUART_LINE_CTRL)) & 0x00000030 ) >> 4)
+#define GET_HSUART_SB (((REG32(ADR_HSUART_LINE_CTRL)) & 0x00000040 ) >> 6)
+#define GET_HSUART_DLAB (((REG32(ADR_HSUART_LINE_CTRL)) & 0x00000080 ) >> 7)
+#define GET_HSUART_DTS (((REG32(ADR_HSUART_MODEM_CTRL)) & 0x00000001 ) >> 0)
+#define GET_HSUART_RTS (((REG32(ADR_HSUART_MODEM_CTRL)) & 0x00000002 ) >> 1)
+#define GET_HSUART_OUT1 (((REG32(ADR_HSUART_MODEM_CTRL)) & 0x00000004 ) >> 2)
+#define GET_HSUART_OUT2 (((REG32(ADR_HSUART_MODEM_CTRL)) & 0x00000008 ) >> 3)
+#define GET_HSUART_LOOP1 (((REG32(ADR_HSUART_MODEM_CTRL)) & 0x00000010 ) >> 4)
+#define GET_HSUART_ARTS (((REG32(ADR_HSUART_MODEM_CTRL)) & 0x00000040 ) >> 6)
+#define GET_HSUART_ACTS (((REG32(ADR_HSUART_MODEM_CTRL)) & 0x00000080 ) >> 7)
+#define GET_HSUART_DR (((REG32(ADR_HSUART_LINE_STATUS)) & 0x00000001 ) >> 0)
+#define GET_HSUART_OE (((REG32(ADR_HSUART_LINE_STATUS)) & 0x00000002 ) >> 1)
+#define GET_HSUART_PE (((REG32(ADR_HSUART_LINE_STATUS)) & 0x00000004 ) >> 2)
+#define GET_HSUART_FE (((REG32(ADR_HSUART_LINE_STATUS)) & 0x00000008 ) >> 3)
+#define GET_HSUART_BI (((REG32(ADR_HSUART_LINE_STATUS)) & 0x00000010 ) >> 4)
+#define GET_HSUART_THRE (((REG32(ADR_HSUART_LINE_STATUS)) & 0x00000020 ) >> 5)
+#define GET_HSUART_TSRE (((REG32(ADR_HSUART_LINE_STATUS)) & 0x00000040 ) >> 6)
+#define GET_HSUART_ERF (((REG32(ADR_HSUART_LINE_STATUS)) & 0x00000080 ) >> 7)
+#define GET_HSUART_DCTS (((REG32(ADR_HSUART_MODEM_STATUS)) & 0x00000001 ) >> 0)
+#define GET_HSUART_DDSR (((REG32(ADR_HSUART_MODEM_STATUS)) & 0x00000002 ) >> 1)
+#define GET_HSUART_TERI (((REG32(ADR_HSUART_MODEM_STATUS)) & 0x00000004 ) >> 2)
+#define GET_HSUART_DDCD (((REG32(ADR_HSUART_MODEM_STATUS)) & 0x00000008 ) >> 3)
+#define GET_HSUART_CTS (((REG32(ADR_HSUART_MODEM_STATUS)) & 0x00000010 ) >> 4)
+#define GET_HSUART_DSR (((REG32(ADR_HSUART_MODEM_STATUS)) & 0x00000020 ) >> 5)
+#define GET_HSUART_RI (((REG32(ADR_HSUART_MODEM_STATUS)) & 0x00000040 ) >> 6)
+#define GET_HSUART_DCR (((REG32(ADR_HSUART_MODEM_STATUS)) & 0x00000080 ) >> 7)
+#define GET_HSUART_SCR (((REG32(ADR_HSUART_SCRATCH_BOARD)) & 0x000000ff ) >> 0)
+#define GET_HSUART_RTS_AUTO_TH_L (((REG32(ADR_HSUART_FIFO_THRESHOLD)) & 0x0000001f ) >> 0)
+#define GET_HSUART_RTS_AUTO_TH_H (((REG32(ADR_HSUART_FIFO_THRESHOLD)) & 0x00001f00 ) >> 8)
+#define GET_HSUART_TX_THR_L (((REG32(ADR_HSUART_FIFO_THRESHOLD)) & 0x001f0000 ) >> 16)
+#define GET_HSUART_TX_THR_H (((REG32(ADR_HSUART_FIFO_THRESHOLD)) & 0x1f000000 ) >> 24)
+#define GET_HSUART_IIR (((REG32(ADR_HSUART_INTERRUPT_STATUS)) & 0x0000000f ) >> 0)
+#define GET_HSUART_TXDMA_DONE (((REG32(ADR_HSUART_INTERRUPT_STATUS)) & 0x00000020 ) >> 5)
+#define GET_HSUART_IFOFOE0 (((REG32(ADR_HSUART_INTERRUPT_STATUS)) & 0x00000040 ) >> 6)
+#define GET_HSUART_IFIFOE1 (((REG32(ADR_HSUART_INTERRUPT_STATUS)) & 0x00000080 ) >> 7)
+#define GET_HSUART_DIV (((REG32(ADR_HSUART_DIV_FRAC)) & 0x0000ffff ) >> 0)
+#define GET_HSUART_FRAC (((REG32(ADR_HSUART_DIV_FRAC)) & 0x00ff0000 ) >> 16)
+#define GET_HSUART_INT (((REG32(ADR_HSUART_EXPANSION_INTERRUPT_STATUS)) & 0x0000ffff ) >> 0)
+#define GET_HSUART_DMA_RX_STR_ADDR (((REG32(ADR_HSUART_DMA_RX_STR_ADDR)) & 0xffffffff ) >> 0)
+#define GET_HSUART_DMA_RX_END_ADDR (((REG32(ADR_HSUART_DMA_RX_END_ADDR)) & 0xffffffff ) >> 0)
+#define GET_HSUART_DMA_RX_WPT (((REG32(ADR_HSUART_DMA_RX_WPT)) & 0xffffffff ) >> 0)
+#define GET_HSUART_DMA_RX_RPT (((REG32(ADR_HSUART_DMA_RX_RPT)) & 0xffffffff ) >> 0)
+#define GET_HSUART_DMA_TX_STR_ADDR (((REG32(ADR_HSUART_DMA_TX_STR_ADDR)) & 0xffffffff ) >> 0)
+#define GET_HSUART_DMA_TX_END_ADDR (((REG32(ADR_HSUART_DMA_TX_END_ADDR)) & 0xffffffff ) >> 0)
+#define GET_HSUART_DMA_TX_WPT (((REG32(ADR_HSUART_DMA_TX_WPT)) & 0xffffffff ) >> 0)
+#define GET_HSUART_DMA_TX_RPT (((REG32(ADR_HSUART_DMA_TX_RPT)) & 0xffffffff ) >> 0)
+#define GET_MANUAL_T_ADDR (((REG32(ADR_MANUAL_MODE_TX_ADDR)) & 0xffffffff ) >> 0)
+#define GET_MANUAL_R_ADDR (((REG32(ADR_MANUAL_MODE_RX_ADDR)) & 0xffffffff ) >> 0)
+#define GET_FLASH_FRONT_DLY (((REG32(ADR_SPI_PARAM)) & 0x0000000f ) >> 0)
+#define GET_FLASH_BACK_DLY (((REG32(ADR_SPI_PARAM)) & 0x000000f0 ) >> 4)
+#define GET_CSN_DLY (((REG32(ADR_SPI_PARAM)) & 0x00000f00 ) >> 8)
+#define GET_INDICATOR (((REG32(ADR_SPI_PARAM)) & 0x000ff000 ) >> 12)
+#define GET_DUMY_DLY (((REG32(ADR_SPI_PARAM)) & 0x00f00000 ) >> 20)
+#define GET_MEM_SEL (((REG32(ADR_SPI_PARAM)) & 0x01000000 ) >> 24)
+#define GET_SPI_BUSY (((REG32(ADR_SPI_PARAM2)) & 0x00000001 ) >> 0)
+#define GET_SPI_FLASH_MODE (((REG32(ADR_SPI_PARAM2)) & 0x00000006 ) >> 1)
+#define GET_MANUAL_MODE_BUSY (((REG32(ADR_SPI_PARAM2)) & 0x00000008 ) >> 3)
+#define GET_PREFETCH_EN (((REG32(ADR_SPI_PARAM2)) & 0x00000010 ) >> 4)
+#define GET_WRAP_EN (((REG32(ADR_SPI_PARAM2)) & 0x00000020 ) >> 5)
+#define GET_CONTINUE_R_EN (((REG32(ADR_SPI_PARAM2)) & 0x00000040 ) >> 6)
+#define GET_MANUAL_T_LEN (((REG32(ADR_SPI_TX_LEN)) & 0x0000ffff ) >> 0)
+#define GET_MANUAL_R_LEN (((REG32(ADR_SPI_RX_LEN)) & 0x0000ffff ) >> 0)
+#define GET_BIT1_WR_CMD (((REG32(ADR_CMD_SET)) & 0x000000ff ) >> 0)
+#define GET_BIT1_RD_CMD (((REG32(ADR_CMD_SET)) & 0x0000ff00 ) >> 8)
+#define GET_BIT2_RD_CMD (((REG32(ADR_CMD_SET)) & 0x00ff0000 ) >> 16)
+#define GET_BIT4_RD_CMD (((REG32(ADR_CMD_SET)) & 0xff000000 ) >> 24)
+#define GET_BIT4_WR_CMD (((REG32(ADR_CMD_SET_1)) & 0x000000ff ) >> 0)
+#define GET_FLS_CLK_IN_DLY_SEL (((REG32(ADR_FLASH_IO0_DLY)) & 0x00000007 ) >> 0)
+#define GET_FLS_CLK_OUT_DLY_SEL (((REG32(ADR_FLASH_IO0_DLY)) & 0x00000070 ) >> 4)
+#define GET_FLS_MOSI_IN_DLY_SEL (((REG32(ADR_FLASH_IO0_DLY)) & 0x00000700 ) >> 8)
+#define GET_FLS_MOSI_OUT_DLY_SEL (((REG32(ADR_FLASH_IO0_DLY)) & 0x00007000 ) >> 12)
+#define GET_FLS_MISO_IN_DLY_SEL (((REG32(ADR_FLASH_IO0_DLY)) & 0x00070000 ) >> 16)
+#define GET_FLS_MISO_OUT_DLY_SEL (((REG32(ADR_FLASH_IO0_DLY)) & 0x00700000 ) >> 20)
+#define GET_FLS_WP_IN_DLY_SEL (((REG32(ADR_FLASH_IO0_DLY)) & 0x07000000 ) >> 24)
+#define GET_FLS_WP_OUT_DLY_SEL (((REG32(ADR_FLASH_IO0_DLY)) & 0x70000000 ) >> 28)
+#define GET_FLS_NC_IN_DLY_SEL (((REG32(ADR_FLASH_IO1_DLY)) & 0x00000007 ) >> 0)
+#define GET_FLS_NC_OUT_DLY_SEL (((REG32(ADR_FLASH_IO1_DLY)) & 0x00000070 ) >> 4)
+#define GET_SPI_F_MISO_CLK_SEL (((REG32(ADR_FLASH_IO1_DLY)) & 0x00000100 ) >> 8)
+#define GET_INS_START_ADDR (((REG32(ADR_INS_SPACE_START_ADDR)) & 0x00ffffff ) >> 0)
+#define GET_INS_END_ADDR (((REG32(ADR_INS_SPACE_END_ADDR)) & 0x00ffffff ) >> 0)
+#define GET_INS_BUF_CLR (((REG32(ADR_BUFFER_CLEAR_ERROR_FLAG_CLEAR)) & 0x00000001 ) >> 0)
+#define GET_RW_BUF_CLR (((REG32(ADR_BUFFER_CLEAR_ERROR_FLAG_CLEAR)) & 0x00000002 ) >> 1)
+#define GET_ERR_FLAG_CLR (((REG32(ADR_BUFFER_CLEAR_ERROR_FLAG_CLEAR)) & 0x00000004 ) >> 2)
+#define GET_DMA_ADR_SRC (((REG32(ADR_DMA_ADR_SRC)) & 0xffffffff ) >> 0)
+#define GET_DMA_ADR_DST (((REG32(ADR_DMA_ADR_DST)) & 0xffffffff ) >> 0)
+#define GET_DMA_SRC_SIZE (((REG32(ADR_DMA_CTRL)) & 0x00000007 ) >> 0)
+#define GET_DMA_SRC_INC (((REG32(ADR_DMA_CTRL)) & 0x00000008 ) >> 3)
+#define GET_DMA_DST_SIZE (((REG32(ADR_DMA_CTRL)) & 0x00000070 ) >> 4)
+#define GET_DMA_DST_INC (((REG32(ADR_DMA_CTRL)) & 0x00000080 ) >> 7)
+#define GET_DMA_FAST_FILL (((REG32(ADR_DMA_CTRL)) & 0x00000100 ) >> 8)
+#define GET_DMA_SDIO_KICK (((REG32(ADR_DMA_CTRL)) & 0x00001000 ) >> 12)
+#define GET_DMA_BADR_EN (((REG32(ADR_DMA_CTRL)) & 0x00002000 ) >> 13)
+#define GET_DMA_LEN (((REG32(ADR_DMA_CTRL)) & 0xffff0000 ) >> 16)
+#define GET_DMA_INT_MASK (((REG32(ADR_DMA_INT)) & 0x00000001 ) >> 0)
+#define GET_DMA_STS (((REG32(ADR_DMA_INT)) & 0x00000100 ) >> 8)
+#define GET_DMA_FINISH (((REG32(ADR_DMA_INT)) & 0x80000000 ) >> 31)
+#define GET_DMA_CONST (((REG32(ADR_DMA_FILL_CONST)) & 0xffffffff ) >> 0)
+#define GET_D2_DMA_ADR_SRC (((REG32(ADR_D2_DMA_ADR_SRC)) & 0xffffffff ) >> 0)
+#define GET_D2_DMA_ADR_DST (((REG32(ADR_D2_DMA_ADR_DST)) & 0xffffffff ) >> 0)
+#define GET_D2_DMA_SRC_SIZE (((REG32(ADR_D2_DMA_CTRL)) & 0x00000007 ) >> 0)
+#define GET_D2_DMA_SRC_INC (((REG32(ADR_D2_DMA_CTRL)) & 0x00000008 ) >> 3)
+#define GET_D2_DMA_DST_SIZE (((REG32(ADR_D2_DMA_CTRL)) & 0x00000070 ) >> 4)
+#define GET_D2_DMA_DST_INC (((REG32(ADR_D2_DMA_CTRL)) & 0x00000080 ) >> 7)
+#define GET_D2_DMA_FAST_FILL (((REG32(ADR_D2_DMA_CTRL)) & 0x00000100 ) >> 8)
+#define GET_D2_DMA_SDIO_KICK (((REG32(ADR_D2_DMA_CTRL)) & 0x00001000 ) >> 12)
+#define GET_D2_DMA_BADR_EN (((REG32(ADR_D2_DMA_CTRL)) & 0x00002000 ) >> 13)
+#define GET_D2_DMA_LEN (((REG32(ADR_D2_DMA_CTRL)) & 0xffff0000 ) >> 16)
+#define GET_D2_DMA_INT_MASK (((REG32(ADR_D2_DMA_INT)) & 0x00000001 ) >> 0)
+#define GET_D2_DMA_STS (((REG32(ADR_D2_DMA_INT)) & 0x00000100 ) >> 8)
+#define GET_D2_DMA_FINISH (((REG32(ADR_D2_DMA_INT)) & 0x80000000 ) >> 31)
+#define GET_D2_DMA_CONST (((REG32(ADR_D2_DMA_FILL_CONST)) & 0xffffffff ) >> 0)
+#define GET_MASK_TYPHOST_INT_MAP_02 (((REG32(ADR_MASK_TYPHOST_INT_MAP_02)) & 0xffffffff ) >> 0)
+#define GET_RAW_TYPHOST_INT_MAP_02 (((REG32(ADR_RAW_TYPHOST_INT_MAP_02)) & 0xffffffff ) >> 0)
+#define GET_POSTMASK_TYPHOST_INT_MAP_02 (((REG32(ADR_POSTMASK_TYPHOST_INT_MAP_02)) & 0xffffffff ) >> 0)
+#define GET_MASK_TYPHOST_INT_MAP_15 (((REG32(ADR_MASK_TYPHOST_INT_MAP_15)) & 0xffffffff ) >> 0)
+#define GET_RAW_TYPHOST_INT_MAP_15 (((REG32(ADR_RAW_TYPHOST_INT_MAP_15)) & 0xffffffff ) >> 0)
+#define GET_POSTMASK_TYPHOST_INT_MAP_15 (((REG32(ADR_POSTMASK_TYPHOST_INT_MAP_15)) & 0xffffffff ) >> 0)
+#define GET_MASK_TYPHOST_INT_MAP_31 (((REG32(ADR_MASK_TYPHOST_INT_MAP_31)) & 0xffffffff ) >> 0)
+#define GET_RAW_TYPHOST_INT_MAP_31 (((REG32(ADR_RAW_TYPHOST_INT_MAP_31)) & 0xffffffff ) >> 0)
+#define GET_POSTMASK_TYPHOST_INT_MAP_31 (((REG32(ADR_POSTMASK_TYPHOST_INT_MAP_31)) & 0xffffffff ) >> 0)
+#define GET_MASK_TYPHOST_INT_MAP (((REG32(ADR_MASK_TYPHOST_INT_MAP)) & 0xffffffff ) >> 0)
+#define GET_RAW_TYPHOST_INT_MAP (((REG32(ADR_RAW_TYPHOST_INT_MAP)) & 0xffffffff ) >> 0)
+#define GET_POSTMASK_TYPHOST_INT_MAP (((REG32(ADR_POSTMASK_TYPHOST_INT_MAP)) & 0xffffffff ) >> 0)
+#define GET_SUMMARY_TYPHOST_INT_MAP (((REG32(ADR_SUMMARY_TYPHOST_INT_MAP)) & 0x00000001 ) >> 0)
+#define GET_MASK_TYPMCU_INT_MAP_02 (((REG32(ADR_MASK_TYPMCU_INT_MAP_02)) & 0xffffffff ) >> 0)
+#define GET_RAW_TYPMCU_INT_MAP_02 (((REG32(ADR_RAW_TYPMCU_INT_MAP_02)) & 0xffffffff ) >> 0)
+#define GET_POSTMASK_TYPMCU_INT_MAP_02 (((REG32(ADR_POSTMASK_TYPMCU_INT_MAP_02)) & 0xffffffff ) >> 0)
+#define GET_MASK_TYPMCU_INT_MAP_15 (((REG32(ADR_MASK_TYPMCU_INT_MAP_15)) & 0xffffffff ) >> 0)
+#define GET_RAW_TYPMCU_INT_MAP_15 (((REG32(ADR_RAW_TYPMCU_INT_MAP_15)) & 0xffffffff ) >> 0)
+#define GET_POSTMASK_TYPMCU_INT_MAP_15 (((REG32(ADR_POSTMASK_TYPMCU_INT_MAP_15)) & 0xffffffff ) >> 0)
+#define GET_MASK_TYPMCU_INT_MAP_31 (((REG32(ADR_MASK_TYPMCU_INT_MAP_31)) & 0xffffffff ) >> 0)
+#define GET_RAW_TYPMCU_INT_MAP_31 (((REG32(ADR_RAW_TYPMCU_INT_MAP_31)) & 0xffffffff ) >> 0)
+#define GET_POSTMASK_TYPMCU_INT_MAP_31 (((REG32(ADR_POSTMASK_TYPMCU_INT_MAP_31)) & 0xffffffff ) >> 0)
+#define GET_MASK_TYPMCU_INT_MAP (((REG32(ADR_MASK_TYPMCU_INT_MAP)) & 0xffffffff ) >> 0)
+#define GET_RAW_TYPMCU_INT_MAP (((REG32(ADR_RAW_TYPMCU_INT_MAP)) & 0xffffffff ) >> 0)
+#define GET_POSTMASK_TYPMCU_INT_MAP (((REG32(ADR_POSTMASK_TYPMCU_INT_MAP)) & 0xffffffff ) >> 0)
+#define GET_SUMMARY_TYPMCU_INT_MAP (((REG32(ADR_SUMMARY_TYPMCU_INT_MAP)) & 0x00000001 ) >> 0)
+#define GET_INT_GPI_SUB_00 (((REG32(ADR_GPIO_INTERRUPT_BANK_00_TO_07)) & 0x0000000f ) >> 0)
+#define GET_INT_GPI_SUB_01 (((REG32(ADR_GPIO_INTERRUPT_BANK_00_TO_07)) & 0x000000f0 ) >> 4)
+#define GET_INT_GPI_SUB_02 (((REG32(ADR_GPIO_INTERRUPT_BANK_00_TO_07)) & 0x00000f00 ) >> 8)
+#define GET_INT_GPI_SUB_03 (((REG32(ADR_GPIO_INTERRUPT_BANK_00_TO_07)) & 0x0000f000 ) >> 12)
+#define GET_INT_GPI_SUB_04 (((REG32(ADR_GPIO_INTERRUPT_BANK_00_TO_07)) & 0x000f0000 ) >> 16)
+#define GET_INT_GPI_SUB_05 (((REG32(ADR_GPIO_INTERRUPT_BANK_00_TO_07)) & 0x00f00000 ) >> 20)
+#define GET_INT_GPI_SUB_06 (((REG32(ADR_GPIO_INTERRUPT_BANK_00_TO_07)) & 0x0f000000 ) >> 24)
+#define GET_INT_GPI_SUB_07 (((REG32(ADR_GPIO_INTERRUPT_BANK_00_TO_07)) & 0xf0000000 ) >> 28)
+#define GET_INT_GPI_SUB_08 (((REG32(ADR_GPIO_INTERRUPT_BANK_08_TO_15)) & 0x0000000f ) >> 0)
+#define GET_INT_GPI_SUB_09 (((REG32(ADR_GPIO_INTERRUPT_BANK_08_TO_15)) & 0x000000f0 ) >> 4)
+#define GET_INT_GPI_SUB_10 (((REG32(ADR_GPIO_INTERRUPT_BANK_08_TO_15)) & 0x00000f00 ) >> 8)
+#define GET_INT_GPI_SUB_11 (((REG32(ADR_GPIO_INTERRUPT_BANK_08_TO_15)) & 0x0000f000 ) >> 12)
+#define GET_INT_GPI_SUB_12 (((REG32(ADR_GPIO_INTERRUPT_BANK_08_TO_15)) & 0x000f0000 ) >> 16)
+#define GET_INT_GPI_SUB_13 (((REG32(ADR_GPIO_INTERRUPT_BANK_08_TO_15)) & 0x00f00000 ) >> 20)
+#define GET_INT_GPI_SUB_14 (((REG32(ADR_GPIO_INTERRUPT_BANK_08_TO_15)) & 0x0f000000 ) >> 24)
+#define GET_INT_GPI_SUB_15 (((REG32(ADR_GPIO_INTERRUPT_BANK_08_TO_15)) & 0xf0000000 ) >> 28)
+#define GET_INT_GPI_SUB_16 (((REG32(ADR_GPIO_INTERRUPT_BANK_16_TO_22)) & 0x0000000f ) >> 0)
+#define GET_INT_GPI_SUB_17 (((REG32(ADR_GPIO_INTERRUPT_BANK_16_TO_22)) & 0x000000f0 ) >> 4)
+#define GET_INT_GPI_SUB_18 (((REG32(ADR_GPIO_INTERRUPT_BANK_16_TO_22)) & 0x00000f00 ) >> 8)
+#define GET_INT_GPI_SUB_19 (((REG32(ADR_GPIO_INTERRUPT_BANK_16_TO_22)) & 0x0000f000 ) >> 12)
+#define GET_INT_GPI_SUB_20 (((REG32(ADR_GPIO_INTERRUPT_BANK_16_TO_22)) & 0x000f0000 ) >> 16)
+#define GET_INT_GPI_SUB_21 (((REG32(ADR_GPIO_INTERRUPT_BANK_16_TO_22)) & 0x00f00000 ) >> 20)
+#define GET_INT_GPI_SUB_22 (((REG32(ADR_GPIO_INTERRUPT_BANK_16_TO_22)) & 0x0f000000 ) >> 24)
+#define GET_INT_GPI_MODE_00 (((REG32(ADR_GPIO_INTERRUPT_MODE_00_TO_07)) & 0x00000007 ) >> 0)
+#define GET_INT_GPI_MODE_01 (((REG32(ADR_GPIO_INTERRUPT_MODE_00_TO_07)) & 0x00000070 ) >> 4)
+#define GET_INT_GPI_MODE_02 (((REG32(ADR_GPIO_INTERRUPT_MODE_00_TO_07)) & 0x00000700 ) >> 8)
+#define GET_INT_GPI_MODE_03 (((REG32(ADR_GPIO_INTERRUPT_MODE_00_TO_07)) & 0x00007000 ) >> 12)
+#define GET_INT_GPI_MODE_04 (((REG32(ADR_GPIO_INTERRUPT_MODE_00_TO_07)) & 0x00070000 ) >> 16)
+#define GET_INT_GPI_MODE_05 (((REG32(ADR_GPIO_INTERRUPT_MODE_00_TO_07)) & 0x00700000 ) >> 20)
+#define GET_INT_GPI_MODE_06 (((REG32(ADR_GPIO_INTERRUPT_MODE_00_TO_07)) & 0x07000000 ) >> 24)
+#define GET_INT_GPI_MODE_07 (((REG32(ADR_GPIO_INTERRUPT_MODE_00_TO_07)) & 0x70000000 ) >> 28)
+#define GET_INT_GPI_MODE_08 (((REG32(ADR_GPIO_INTERRUPT_MODE_08_TO_15)) & 0x00000007 ) >> 0)
+#define GET_INT_GPI_MODE_09 (((REG32(ADR_GPIO_INTERRUPT_MODE_08_TO_15)) & 0x00000070 ) >> 4)
+#define GET_INT_GPI_MODE_10 (((REG32(ADR_GPIO_INTERRUPT_MODE_08_TO_15)) & 0x00000700 ) >> 8)
+#define GET_INT_GPI_MODE_11 (((REG32(ADR_GPIO_INTERRUPT_MODE_08_TO_15)) & 0x00007000 ) >> 12)
+#define GET_INT_GPI_MODE_12 (((REG32(ADR_GPIO_INTERRUPT_MODE_08_TO_15)) & 0x00070000 ) >> 16)
+#define GET_INT_GPI_MODE_13 (((REG32(ADR_GPIO_INTERRUPT_MODE_08_TO_15)) & 0x00700000 ) >> 20)
+#define GET_INT_GPI_MODE_14 (((REG32(ADR_GPIO_INTERRUPT_MODE_08_TO_15)) & 0x07000000 ) >> 24)
+#define GET_INT_GPI_MODE_15 (((REG32(ADR_GPIO_INTERRUPT_MODE_08_TO_15)) & 0x70000000 ) >> 28)
+#define GET_INT_GPI_MODE_16 (((REG32(ADR_GPIO_INTERRUPT_MODE_16_TO_22)) & 0x00000007 ) >> 0)
+#define GET_INT_GPI_MODE_17 (((REG32(ADR_GPIO_INTERRUPT_MODE_16_TO_22)) & 0x00000070 ) >> 4)
+#define GET_INT_GPI_MODE_18 (((REG32(ADR_GPIO_INTERRUPT_MODE_16_TO_22)) & 0x00000700 ) >> 8)
+#define GET_INT_GPI_MODE_19 (((REG32(ADR_GPIO_INTERRUPT_MODE_16_TO_22)) & 0x00007000 ) >> 12)
+#define GET_INT_GPI_MODE_20 (((REG32(ADR_GPIO_INTERRUPT_MODE_16_TO_22)) & 0x00070000 ) >> 16)
+#define GET_INT_GPI_MODE_21 (((REG32(ADR_GPIO_INTERRUPT_MODE_16_TO_22)) & 0x00700000 ) >> 20)
+#define GET_INT_GPI_MODE_22 (((REG32(ADR_GPIO_INTERRUPT_MODE_16_TO_22)) & 0x07000000 ) >> 24)
+#define GET_GPO_INT_POL (((REG32(ADR_GPIO_INTERRUPT_MODE_16_TO_22)) & 0x80000000 ) >> 31)
+#define GET_INT_IPC_RAW (((REG32(ADR_IPC_INTERRUPT)) & 0xffffffff ) >> 0)
+#define GET_INT_WIFI_PHY (((REG32(ADR_CLR_INT_STS2)) & 0x00800000 ) >> 23)
+#define GET_INT_UART_DBG_RX_TOUT (((REG32(ADR_CLR_INT_STS2)) & 0x04000000 ) >> 26)
+#define GET_INT_UART_DATA_RX_TOUT (((REG32(ADR_CLR_INT_STS2)) & 0x40000000 ) >> 30)
+#define GET_INT_ALC_TIMEOUT (((REG32(ADR_CLR_INT_STS1)) & 0x00000100 ) >> 8)
+#define GET_INT_REQ_LOCK (((REG32(ADR_CLR_INT_STS1)) & 0x00000200 ) >> 9)
+#define GET_INT_TX_LIMIT (((REG32(ADR_CLR_INT_STS1)) & 0x00000400 ) >> 10)
+#define GET_INT_ID_THOLD_RX (((REG32(ADR_CLR_INT_STS1)) & 0x00000800 ) >> 11)
+#define GET_INT_ID_THOLD_TX (((REG32(ADR_CLR_INT_STS1)) & 0x00001000 ) >> 12)
+#define GET_INT_ID_DOUBLE_RLS (((REG32(ADR_CLR_INT_STS1)) & 0x00002000 ) >> 13)
+#define GET_INT_RX_ID_LEN_THOLD (((REG32(ADR_CLR_INT_STS1)) & 0x00004000 ) >> 14)
+#define GET_INT_TX_ID_LEN_THOLD (((REG32(ADR_CLR_INT_STS1)) & 0x00008000 ) >> 15)
+#define GET_INT_ALL_ID_LEN_THOLD (((REG32(ADR_CLR_INT_STS1)) & 0x00010000 ) >> 16)
+#define GET_INT_TRASH_CAN (((REG32(ADR_CLR_INT_STS1)) & 0x00020000 ) >> 17)
+#define GET_INT_MB_LOWTHOLD (((REG32(ADR_CLR_INT_STS1)) & 0x00040000 ) >> 18)
+#define GET_INT_EDCA0_LOWTHOLD (((REG32(ADR_CLR_INT_STS1)) & 0x00100000 ) >> 20)
+#define GET_INT_EDCA1_LOWTHOLD (((REG32(ADR_CLR_INT_STS1)) & 0x00200000 ) >> 21)
+#define GET_INT_EDCA2_LOWTHOLD (((REG32(ADR_CLR_INT_STS1)) & 0x00400000 ) >> 22)
+#define GET_INT_EDCA3_LOWTHOLD (((REG32(ADR_CLR_INT_STS1)) & 0x00800000 ) >> 23)
+#define GET_INT_SDIO_WAKE (((REG32(ADR_CLR_INT_STS0)) & 0x00000004 ) >> 2)
+#define GET_INT_SPI_M_DONE (((REG32(ADR_CLR_INT_STS0)) & 0x00000008 ) >> 3)
+#define GET_INT_FLASH_DMA_DONE (((REG32(ADR_CLR_INT_STS0)) & 0x00000040 ) >> 6)
+#define GET_INT_FBUSDMAC_INT_COMBINED (((REG32(ADR_CLR_INT_STS0)) & 0x00000200 ) >> 9)
+#define GET_INT_DMAC_INT_COMBINED (((REG32(ADR_CLR_INT_STS0)) & 0x00000400 ) >> 10)
+#define GET_INT_I2S (((REG32(ADR_CLR_INT_STS0)) & 0x00010000 ) >> 16)
+#define GET_INT_CPU_ALT (((REG32(ADR_CLR_INT_STS0)) & 0x00040000 ) >> 18)
+#define GET_INT_CPU (((REG32(ADR_CLR_INT_STS0)) & 0x00080000 ) >> 19)
+#define GET_INT_US_TIMER_0 (((REG32(ADR_CLR_INT_STS0)) & 0x00100000 ) >> 20)
+#define GET_INT_US_TIMER_1 (((REG32(ADR_CLR_INT_STS0)) & 0x00200000 ) >> 21)
+#define GET_INT_US_TIMER_2 (((REG32(ADR_CLR_INT_STS0)) & 0x00400000 ) >> 22)
+#define GET_INT_US_TIMER_3 (((REG32(ADR_CLR_INT_STS0)) & 0x00800000 ) >> 23)
+#define GET_INT_MS_TIMER_0 (((REG32(ADR_CLR_INT_STS0)) & 0x01000000 ) >> 24)
+#define GET_INT_MS_TIMER_1 (((REG32(ADR_CLR_INT_STS0)) & 0x02000000 ) >> 25)
+#define GET_INT_MS_TIMER_2 (((REG32(ADR_CLR_INT_STS0)) & 0x04000000 ) >> 26)
+#define GET_INT_MS_TIMER_3 (((REG32(ADR_CLR_INT_STS0)) & 0x08000000 ) >> 27)
+#define GET_INT_I2CMST (((REG32(ADR_CLR_INT_STS0)) & 0x10000000 ) >> 28)
+#define GET_INT_HCI (((REG32(ADR_CLR_INT_STS0)) & 0x20000000 ) >> 29)
+#define GET_INT_CO_DMA (((REG32(ADR_CLR_INT_STS0)) & 0x40000000 ) >> 30)
+#define GET_PATCH02_EN (((REG32(ADR_ROM_PATCH02_0)) & 0x00000001 ) >> 0)
+#define GET_PATCH02_ADDR (((REG32(ADR_ROM_PATCH02_0)) & 0x0001fffc ) >> 2)
+#define GET_PATCH02_DATA (((REG32(ADR_ROM_PATCH02_1)) & 0xffffffff ) >> 0)
+#define GET_PATCH03_EN (((REG32(ADR_ROM_PATCH03_0)) & 0x00000001 ) >> 0)
+#define GET_PATCH03_ADDR (((REG32(ADR_ROM_PATCH03_0)) & 0x0001fffc ) >> 2)
+#define GET_PATCH03_DATA (((REG32(ADR_ROM_PATCH03_1)) & 0xffffffff ) >> 0)
+#define GET_PATCH04_EN (((REG32(ADR_ROM_PATCH04_0)) & 0x00000001 ) >> 0)
+#define GET_PATCH04_ADDR (((REG32(ADR_ROM_PATCH04_0)) & 0x0001fffc ) >> 2)
+#define GET_PATCH04_DATA (((REG32(ADR_ROM_PATCH04_1)) & 0xffffffff ) >> 0)
+#define GET_PATCH05_EN (((REG32(ADR_ROM_PATCH05_0)) & 0x00000001 ) >> 0)
+#define GET_PATCH05_ADDR (((REG32(ADR_ROM_PATCH05_0)) & 0x0001fffc ) >> 2)
+#define GET_PATCH05_DATA (((REG32(ADR_ROM_PATCH05_1)) & 0xffffffff ) >> 0)
+#define GET_PATCH06_EN (((REG32(ADR_ROM_PATCH06_0)) & 0x00000001 ) >> 0)
+#define GET_PATCH06_ADDR (((REG32(ADR_ROM_PATCH06_0)) & 0x0001fffc ) >> 2)
+#define GET_PATCH06_DATA (((REG32(ADR_ROM_PATCH06_1)) & 0xffffffff ) >> 0)
+#define GET_PATCH07_EN (((REG32(ADR_ROM_PATCH07_0)) & 0x00000001 ) >> 0)
+#define GET_PATCH07_ADDR (((REG32(ADR_ROM_PATCH07_0)) & 0x0001fffc ) >> 2)
+#define GET_PATCH07_DATA (((REG32(ADR_ROM_PATCH07_1)) & 0xffffffff ) >> 0)
+#define GET_PATCH08_EN (((REG32(ADR_ROM_PATCH08_0)) & 0x00000001 ) >> 0)
+#define GET_PATCH08_ADDR (((REG32(ADR_ROM_PATCH08_0)) & 0x0001fffc ) >> 2)
+#define GET_PATCH08_DATA (((REG32(ADR_ROM_PATCH08_1)) & 0xffffffff ) >> 0)
+#define GET_PATCH09_EN (((REG32(ADR_ROM_PATCH09_0)) & 0x00000001 ) >> 0)
+#define GET_PATCH09_ADDR (((REG32(ADR_ROM_PATCH09_0)) & 0x0001fffc ) >> 2)
+#define GET_PATCH09_DATA (((REG32(ADR_ROM_PATCH09_1)) & 0xffffffff ) >> 0)
+#define GET_PATCH10_EN (((REG32(ADR_ROM_PATCH10_0)) & 0x00000001 ) >> 0)
+#define GET_PATCH10_ADDR (((REG32(ADR_ROM_PATCH10_0)) & 0x0001fffc ) >> 2)
+#define GET_PATCH10_DATA (((REG32(ADR_ROM_PATCH10_1)) & 0xffffffff ) >> 0)
+#define GET_PATCH11_EN (((REG32(ADR_ROM_PATCH11_0)) & 0x00000001 ) >> 0)
+#define GET_PATCH11_ADDR (((REG32(ADR_ROM_PATCH11_0)) & 0x0001fffc ) >> 2)
+#define GET_PATCH11_DATA (((REG32(ADR_ROM_PATCH11_1)) & 0xffffffff ) >> 0)
+#define GET_PATCH12_EN (((REG32(ADR_ROM_PATCH12_0)) & 0x00000001 ) >> 0)
+#define GET_PATCH12_ADDR (((REG32(ADR_ROM_PATCH12_0)) & 0x0001fffc ) >> 2)
+#define GET_PATCH12_DATA (((REG32(ADR_ROM_PATCH12_1)) & 0xffffffff ) >> 0)
+#define GET_PATCH13_EN (((REG32(ADR_ROM_PATCH13_0)) & 0x00000001 ) >> 0)
+#define GET_PATCH13_ADDR (((REG32(ADR_ROM_PATCH13_0)) & 0x0001fffc ) >> 2)
+#define GET_PATCH13_DATA (((REG32(ADR_ROM_PATCH13_1)) & 0xffffffff ) >> 0)
+#define GET_PATCH14_EN (((REG32(ADR_ROM_PATCH14_0)) & 0x00000001 ) >> 0)
+#define GET_PATCH14_ADDR (((REG32(ADR_ROM_PATCH14_0)) & 0x0001fffc ) >> 2)
+#define GET_PATCH14_DATA (((REG32(ADR_ROM_PATCH14_1)) & 0xffffffff ) >> 0)
+#define GET_PATCH15_EN (((REG32(ADR_ROM_PATCH15_0)) & 0x00000001 ) >> 0)
+#define GET_PATCH15_ADDR (((REG32(ADR_ROM_PATCH15_0)) & 0x0001fffc ) >> 2)
+#define GET_PATCH15_DATA (((REG32(ADR_ROM_PATCH15_1)) & 0xffffffff ) >> 0)
+#define GET_INT_BROWNOUT_LOWBATTERY (((REG32(ADR_BROWNOUT_INT)) & 0x00000001 ) >> 0)
+#define GET_LOWBATTERY_SAMPLE_MIN_COUNT (((REG32(ADR_BROWNOUT_SETUP)) & 0x0000000f ) >> 0)
+#define GET_TX_ON_DEMAND_ENA (((REG32(ADR_CONTROL)) & 0x00000002 ) >> 1)
+#define GET_RX_2_HOST (((REG32(ADR_CONTROL)) & 0x00000004 ) >> 2)
+#define GET_AUTO_SEQNO (((REG32(ADR_CONTROL)) & 0x00000008 ) >> 3)
+#define GET_BYPASS_TX_PARSER_ENCAP (((REG32(ADR_CONTROL)) & 0x00000010 ) >> 4)
+#define GET_HDR_STRIP (((REG32(ADR_CONTROL)) & 0x00000020 ) >> 5)
+#define GET_ERP_PROTECT (((REG32(ADR_CONTROL)) & 0x000000c0 ) >> 6)
+#define GET_PRO_VER (((REG32(ADR_CONTROL)) & 0x00000300 ) >> 8)
+#define GET_TXQ_ID0 (((REG32(ADR_CONTROL)) & 0x00007000 ) >> 12)
+#define GET_TXQ_ID1 (((REG32(ADR_CONTROL)) & 0x00070000 ) >> 16)
+#define GET_TX_ETHER_TRAP_EN (((REG32(ADR_CONTROL)) & 0x00100000 ) >> 20)
+#define GET_RX_ETHER_TRAP_EN (((REG32(ADR_CONTROL)) & 0x00200000 ) >> 21)
+#define GET_RX_NULL_TRAP_EN (((REG32(ADR_CONTROL)) & 0x00400000 ) >> 22)
+#define GET_TRX_DEBUG_CNT_ENA (((REG32(ADR_CONTROL)) & 0x10000000 ) >> 28)
+#define GET_HCI_TX_AGG_EN (((REG32(ADR_HCI_TRX_MODE)) & 0x00000001 ) >> 0)
+#define GET_HCI_RX_EN (((REG32(ADR_HCI_TRX_MODE)) & 0x00000002 ) >> 1)
+#define GET_HCI_RX_FORM_1 (((REG32(ADR_HCI_TRX_MODE)) & 0x40000000 ) >> 30)
+#define GET_HCI_RX_FORM_0 (((REG32(ADR_HCI_TRX_MODE)) & 0x80000000 ) >> 31)
+#define GET_TX_FLOW_CTRL (((REG32(ADR_TX_FLOW_0)) & 0x0000ffff ) >> 0)
+#define GET_TX_FLOW_MGMT (((REG32(ADR_TX_FLOW_0)) & 0xffff0000 ) >> 16)
+#define GET_TX_FLOW_DATA (((REG32(ADR_TX_FLOW_1)) & 0xffffffff ) >> 0)
+#define GET_SD_RX_LEN (((REG32(ADR_REMAINING_RX_PACKET_LENGTH)) & 0x0000ffff ) >> 0)
+#define GET_RX_ACCU_LEN (((REG32(ADR_RX_PACKET_LENGTH_STATUS)) & 0x0000ffff ) >> 0)
+#define GET_HCI_RX_LEN (((REG32(ADR_RX_PACKET_LENGTH_STATUS)) & 0xffff0000 ) >> 16)
+#define GET_DOT11RTSTHRESHOLD (((REG32(ADR_THRESHOLD)) & 0xffff0000 ) >> 16)
+#define GET_TX_ERR_RECOVER (((REG32(ADR_TX_ERROR_RECEOVERY)) & 0x00000001 ) >> 0)
+#define GET_TX_ERR_FIRST_4B_EN (((REG32(ADR_TX_ERROR_RECEOVERY)) & 0x00000002 ) >> 1)
+#define GET_RX_INT_TIMEOUT (((REG32(ADR_TX_ERROR_RECEOVERY)) & 0xffff0000 ) >> 16)
+#define GET_TXF_ID (((REG32(ADR_TXFID_INCREASE)) & 0x0000003f ) >> 0)
+#define GET_SEQ_CTRL (((REG32(ADR_GLOBAL_SEQUENCE)) & 0x0000ffff ) >> 0)
+#define GET_DBG_ADDR_EN (((REG32(ADR_HCI_REG_0X2C)) & 0x00000001 ) >> 0)
+#define GET_DBG_ADDR_FENCE (((REG32(ADR_HCI_REG_0X2C)) & 0x0000ff00 ) >> 8)
+#define GET_TX_PBOFFSET (((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0x000000ff ) >> 0)
+#define GET_TX_INFO_SIZE (((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0x0000ff00 ) >> 8)
+#define GET_RX_INFO_SIZE (((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0x00ff0000 ) >> 16)
+#define GET_RX_LAST_PHY_SIZE (((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0xff000000 ) >> 24)
+#define GET_TX_INFO_CLEAR_SIZE (((REG32(ADR_HCI_TX_INFO_CLEAR)) & 0x0000003f ) >> 0)
+#define GET_TX_INFO_CLEAR_ENABLE (((REG32(ADR_HCI_TX_INFO_CLEAR)) & 0x00000100 ) >> 8)
+#define GET_RX_PER_RD_LEN (((REG32(ADR_HCI_TO_PKTBUF_SETTING)) & 0x0000003f ) >> 0)
+#define GET_BACKUP_PG_CNT (((REG32(ADR_HCI_TO_PKTBUF_SETTING)) & 0x00000f00 ) >> 8)
+#define GET_MANUAL_HCI_ALLOC_EN (((REG32(ADR_HCI_MANUAL_ALLOC)) & 0x00000001 ) >> 0)
+#define GET_MANUAL_HCI_ALLOC_SIZE (((REG32(ADR_HCI_MANUAL_ALLOC_ACTION)) & 0x0000ffff ) >> 0)
+#define GET_MANUAL_ALLOC_ID (((REG32(ADR_HCI_MANUAL_ALLOC_STATUS)) & 0x0000007f ) >> 0)
+#define GET_HAS_MANUAL_BUF (((REG32(ADR_HCI_MANUAL_ALLOC_STATUS)) & 0x00000080 ) >> 7)
+#define GET_DOUBLE_ALLOC_ERR (((REG32(ADR_HCI_MANUAL_ALLOC_STATUS)) & 0x00000100 ) >> 8)
+#define GET_NO_ALLOC_ERR (((REG32(ADR_HCI_MANUAL_ALLOC_STATUS)) & 0x00000200 ) >> 9)
+#define GET_TXTRAP_ETHTYPE1 (((REG32(ADR_TX_ETHER_TYPE_1)) & 0x0000ffff ) >> 0)
+#define GET_TXTRAP_ETHTYPE0 (((REG32(ADR_TX_ETHER_TYPE_1)) & 0xffff0000 ) >> 16)
+#define GET_RXTRAP_ETHTYPE1 (((REG32(ADR_RX_ETHER_TYPE_1)) & 0x0000ffff ) >> 0)
+#define GET_RXTRAP_ETHTYPE0 (((REG32(ADR_RX_ETHER_TYPE_1)) & 0xffff0000 ) >> 16)
+#define GET_TX_PKT_SEND_LEN (((REG32(ADR_TX_PACKET_LENGTH)) & 0x0000ffff ) >> 0)
+#define GET_TX_SDIO_PKT_LEN (((REG32(ADR_TX_PACKET_LENGTH)) & 0xffff0000 ) >> 16)
+#define GET_TX_PKT_SEND_ID (((REG32(ADR_TX_PACKET_ID)) & 0x0000007f ) >> 0)
+#define GET_HCI_PENDING_RX_MPDU_CNT (((REG32(ADR_RX_RESCUE_HELPER)) & 0x0000001f ) >> 0)
+#define GET_HCI_RX_HALT (((REG32(ADR_RX_RESCUE_HELPER)) & 0x00000100 ) >> 8)
+#define GET_HIF_LOOP_BACK (((REG32(ADR_RX_RESCUE_HELPER)) & 0x00000200 ) >> 9)
+#define GET_USB_BULK_IN_LEN_INIT (((REG32(ADR_RX_RESCUE_HELPER)) & 0x40000000 ) >> 30)
+#define GET_HCI_RX_MPDU_DEQUE (((REG32(ADR_RX_RESCUE_HELPER)) & 0x80000000 ) >> 31)
+#define GET_HCI_BULK_IN_HOST_SIZE (((REG32(ADR_HCI_FORCE_PRE_BULK_IN)) & 0x0001ffff ) >> 0)
+#define GET_HCI_BULK_IN_TIME_OUT (((REG32(ADR_HCI_BULK_IN_TIME_OUT_VALUE)) & 0xffffffff ) >> 0)
+#define GET_HCI_MONITOR_REG0 (((REG32(ADR_HCI_STATE_DEBUG_MODE_0)) & 0xffffffff ) >> 0)
+#define GET_HCI_MONITOR_REG2 (((REG32(ADR_HCI_STATE_DEBUG_MODE_2)) & 0xffffffff ) >> 0)
+#define GET_HCI_MONITOR_REG3 (((REG32(ADR_HCI_STATE_DEBUG_MODE_3)) & 0xffffffff ) >> 0)
+#define GET_HCI_MONITOR_REG4 (((REG32(ADR_HCI_STATE_DEBUG_MODE_4)) & 0xffffffff ) >> 0)
+#define GET_HCI_MONITOR_REG5 (((REG32(ADR_HCI_STATE_DEBUG_MODE_5)) & 0xffffffff ) >> 0)
+#define GET_SDIO_TX_INVALID_CNT (((REG32(ADR_HCI_STATE_DEBUG_MODE_6)) & 0xffffffff ) >> 0)
+#define GET_HCI_MB_MAX_CNT (((REG32(ADR_HCI_STATE_DEBUG_MODE_7)) & 0x000000ff ) >> 0)
+#define GET_HCI_PROC_CNT (((REG32(ADR_HCI_STATE_DEBUG_MODE_7)) & 0x0000ff00 ) >> 8)
+#define GET_SDIO_TRANS_CNT (((REG32(ADR_HCI_STATE_DEBUG_MODE_7)) & 0x00ff0000 ) >> 16)
+#define GET_TX_ON_DEMAND_LENGTH (((REG32(ADR_HCI_TX_ON_DEMAND_LENGTH)) & 0xffffffff ) >> 0)
+#define GET_HCI_TX_ALLOC_CNT (((REG32(ADR_HCI_TX_ALLOC_SUCCESS_COUNT)) & 0xffffffff ) >> 0)
+#define GET_HCI_TX_ALLOC_TIME (((REG32(ADR_HCI_TX_ALLOC_SPENDING_TIME)) & 0xffffffff ) >> 0)
+#define GET_RX_PKT_TRAP_COUNTER (((REG32(ADR_RX_TRAP_COUNT)) & 0xffffffff ) >> 0)
+#define GET_TX_PKT_TRAP_COUNTER (((REG32(ADR_TX_TRAP_COUNT)) & 0xffffffff ) >> 0)
+#define GET_RX_PKT_DROP_COUNTER (((REG32(ADR_RX_DROP_COUNT)) & 0xffffffff ) >> 0)
+#define GET_TX_PKT_DROP_COUNTER (((REG32(ADR_TX_DROP_COUNT)) & 0xffffffff ) >> 0)
+#define GET_HOST_EVENT_COUNTER (((REG32(ADR_RX_HOST_EVENT_COUNT)) & 0xffffffff ) >> 0)
+#define GET_HOST_CMD_COUNTER (((REG32(ADR_TX_HOST_COMMAND_COUNT)) & 0xffffffff ) >> 0)
+#define GET_RX_PKT_COUNTER (((REG32(ADR_RX_PACKET_COUNTER)) & 0xffffffff ) >> 0)
+#define GET_TX_PKT_COUNTER (((REG32(ADR_TX_PACKET_COUNTER)) & 0xffffffff ) >> 0)
+#define GET_HOST_RX_FAIL_COUNTER (((REG32(ADR_SDIO_RX_FAIL_COUNT)) & 0xffffffff ) >> 0)
+#define GET_HOST_TX_FAIL_COUNTER (((REG32(ADR_SDIO_TX_FAIL_COUNT)) & 0xffffffff ) >> 0)
+#define GET_CORRECT_RATE_REP_LEN (((REG32(ADR_CORRECT_RATE_REPORT_LENGTH)) & 0x00000001 ) >> 0)
+#define GET_TX_PKT_SEND_TO_RX (((REG32(ADR_TX_PACKET_SEND_TO_RX_DIRECTLY)) & 0x00000001 ) >> 0)
+#define GET_PEERPS_REJECT_ENABLE (((REG32(ADR_POWER_SAVING_PEER_REJECT_FUNCTION)) & 0x00000001 ) >> 0)
+#define GET_TRANS_FULL_PKT_AMPDU1P2 (((REG32(ADR_POWER_SAVING_PEER_REJECT_FUNCTION)) & 0x00000010 ) >> 4)
+#define GET_TX_RX_TRAP_HW_ID_SELECT_ENABLE (((REG32(ADR_TX_RX_TRAP_HW_ID_SELECTION_FUNCTION)) & 0x00000001 ) >> 0)
+#define GET_TX_TRAP_HW_ID (((REG32(ADR_TX_RX_TRAP_HW_ID_SELECTION_FUNCTION)) & 0x000000f0 ) >> 4)
+#define GET_RX_TRAP_HW_ID (((REG32(ADR_TX_RX_TRAP_HW_ID_SELECTION_FUNCTION)) & 0x00000f00 ) >> 8)
+#define GET_RX_DEBUG_HCI_EXP_0 (((REG32(ADR_RX_HCI_EXP_0_CTRL)) & 0x00000001 ) >> 0)
+#define GET_RX_DEBUG_HCI_EXP_0_RND_MODE (((REG32(ADR_RX_HCI_EXP_0_CTRL)) & 0x00000030 ) >> 4)
+#define GET_RX_DEBUG_HCI_EXP_0_LENGHT_LIMIT_MIN (((REG32(ADR_RX_HCI_EXP_0_LEN)) & 0x0000ffff ) >> 0)
+#define GET_RX_DEBUG_HCI_EXP_0_LENGHT_LIMIT_MAX (((REG32(ADR_RX_HCI_EXP_0_LEN)) & 0xffff0000 ) >> 16)
+#define GET_RX_AGG_CNT (((REG32(ADR_FORCE_RX_AGGREGATION_MODE)) & 0x0000000f ) >> 0)
+#define GET_RX_AGG_METHOD_3 (((REG32(ADR_FORCE_RX_AGGREGATION_MODE)) & 0x00000080 ) >> 7)
+#define GET_RX_AGG_TIMER_RELOAD_VALUE (((REG32(ADR_FORCE_RX_AGGREGATION_MODE)) & 0xffff0000 ) >> 16)
+#define GET_CS_START_ADDR (((REG32(ADR_CS_START_ADDR)) & 0x0000ffff ) >> 0)
+#define GET_CS_PKT_ID (((REG32(ADR_CS_START_ADDR)) & 0x007f0000 ) >> 16)
+#define GET_ADD_LEN (((REG32(ADR_CS_ADD_LEN)) & 0x0000ffff ) >> 0)
+#define GET_CS_ADDER_EN (((REG32(ADR_CS_CMD)) & 0x00000001 ) >> 0)
+#define GET_PSEUDO (((REG32(ADR_CS_CMD)) & 0x00000002 ) >> 1)
+#define GET_CALCULATE (((REG32(ADR_CS_INI_BUF)) & 0xffffffff ) >> 0)
+#define GET_L4_LEN (((REG32(ADR_CS_PSEUDO_BUF)) & 0x0000ffff ) >> 0)
+#define GET_L4_PROTOL (((REG32(ADR_CS_PSEUDO_BUF)) & 0x00ff0000 ) >> 16)
+#define GET_CHECK_SUM (((REG32(ADR_CS_CHECK_SUM)) & 0x0000ffff ) >> 0)
+#define GET_RAND_EN (((REG32(ADR_RAND_EN)) & 0x00000001 ) >> 0)
+#define GET_RAND_NUM (((REG32(ADR_RAND_NUM)) & 0xffffffff ) >> 0)
+#define GET_MUL_OP1 (((REG32(ADR_MUL_OP1)) & 0xffffffff ) >> 0)
+#define GET_MUL_OP2 (((REG32(ADR_MUL_OP2)) & 0xffffffff ) >> 0)
+#define GET_MUL_ANS0 (((REG32(ADR_MUL_ANS0)) & 0xffffffff ) >> 0)
+#define GET_MUL_ANS1 (((REG32(ADR_MUL_ANS1)) & 0xffffffff ) >> 0)
+#define GET_RD_ADDR (((REG32(ADR_DMA_RDATA)) & 0x0000ffff ) >> 0)
+#define GET_RD_ID (((REG32(ADR_DMA_RDATA)) & 0x007f0000 ) >> 16)
+#define GET_WR_ADDR (((REG32(ADR_DMA_WDATA)) & 0x0000ffff ) >> 0)
+#define GET_WR_ID (((REG32(ADR_DMA_WDATA)) & 0x007f0000 ) >> 16)
+#define GET_LEN (((REG32(ADR_DMA_LEN)) & 0x0000ffff ) >> 0)
+#define GET_CLR (((REG32(ADR_DMA_CLR)) & 0x00000001 ) >> 0)
+#define GET_PHY_MODE (((REG32(ADR_NAV_DATA)) & 0x00000003 ) >> 0)
+#define GET_SHRT_PREAM (((REG32(ADR_NAV_DATA)) & 0x00000004 ) >> 2)
+#define GET_SHRT_GI (((REG32(ADR_NAV_DATA)) & 0x00000008 ) >> 3)
+#define GET_DATA_RATE (((REG32(ADR_NAV_DATA)) & 0x000007f0 ) >> 4)
+#define GET_MCS (((REG32(ADR_NAV_DATA)) & 0x00007000 ) >> 12)
+#define GET_FRAME_LEN (((REG32(ADR_NAV_DATA)) & 0xffff0000 ) >> 16)
+#define GET_DURATION (((REG32(ADR_CO_NAV)) & 0x0000ffff ) >> 0)
+#define GET_SHA_DST_ADDR (((REG32(ADR_SHA_DST_ADDR)) & 0xffffffff ) >> 0)
+#define GET_SHA_SRC_ADDR (((REG32(ADR_SHA_SRC_ADDR)) & 0xffffffff ) >> 0)
+#define GET_SHA_BUSY (((REG32(ADR_SHA_SETTING)) & 0x00000001 ) >> 0)
+#define GET_SHA_ENDIAN (((REG32(ADR_SHA_SETTING)) & 0x00000002 ) >> 1)
+#define GET_EFS_CLKFREQ (((REG32(ADR_EFUSE_CLK_FREQ)) & 0x00000fff ) >> 0)
+#define GET_EFS_VDDQ_EN_LOW_ACTIVE (((REG32(ADR_EFUSE_CLK_FREQ)) & 0x00010000 ) >> 16)
+#define GET_EFS_CLKFREQ_RD (((REG32(ADR_EFUSE_CLK_FREQ)) & 0x0ff00000 ) >> 20)
+#define GET_EFS_PRE_RD (((REG32(ADR_EFUSE_CLK_FREQ)) & 0xf0000000 ) >> 28)
+#define GET_EFS_LDO_ON (((REG32(ADR_EFUSE_LDO_TIME)) & 0x0000ffff ) >> 0)
+#define GET_EFS_LDO_OFF (((REG32(ADR_EFUSE_LDO_TIME)) & 0xffff0000 ) >> 16)
+#define GET_EFS_RD_FLAG (((REG32(ADR_EFUSE_STATUS)) & 0x00000001 ) >> 0)
+#define GET_EFS_PROGRESS_DONE (((REG32(ADR_EFUSE_STATUS2)) & 0x00000001 ) >> 0)
+#define GET_EFS_WR_KICK (((REG32(ADR_EFUSE_WR_KICK)) & 0x00000001 ) >> 0)
+#define GET_EFS_RD_KICK (((REG32(ADR_EFUSE_RD_KICK)) & 0x00000001 ) >> 0)
+#define GET_EFS_VDDQ_EN (((REG32(ADR_EFUSE_VDDQ_EN)) & 0x00000001 ) >> 0)
+#define GET_EFS_BYTE_0 (((REG32(ADR_EFUSE_WDATA_0_0)) & 0x000000ff ) >> 0)
+#define GET_EFS_BYTE_1 (((REG32(ADR_EFUSE_WDATA_0_0)) & 0x0000ff00 ) >> 8)
+#define GET_EFS_BYTE_2 (((REG32(ADR_EFUSE_WDATA_0_0)) & 0x00ff0000 ) >> 16)
+#define GET_EFS_BYTE_3 (((REG32(ADR_EFUSE_WDATA_0_0)) & 0xff000000 ) >> 24)
+#define GET_EFS_BYTE_4 (((REG32(ADR_EFUSE_WDATA_0_1)) & 0x000000ff ) >> 0)
+#define GET_EFS_BYTE_5 (((REG32(ADR_EFUSE_WDATA_0_1)) & 0x0000ff00 ) >> 8)
+#define GET_EFS_BYTE_6 (((REG32(ADR_EFUSE_WDATA_0_1)) & 0x00ff0000 ) >> 16)
+#define GET_EFS_BYTE_7 (((REG32(ADR_EFUSE_WDATA_0_1)) & 0xff000000 ) >> 24)
+#define GET_EFS_BYTE_8 (((REG32(ADR_EFUSE_WDATA_0_2)) & 0x000000ff ) >> 0)
+#define GET_EFS_BYTE_9 (((REG32(ADR_EFUSE_WDATA_0_2)) & 0x0000ff00 ) >> 8)
+#define GET_EFS_BYTE_10 (((REG32(ADR_EFUSE_WDATA_0_2)) & 0x00ff0000 ) >> 16)
+#define GET_EFS_BYTE_11 (((REG32(ADR_EFUSE_WDATA_0_2)) & 0xff000000 ) >> 24)
+#define GET_EFS_BYTE_12 (((REG32(ADR_EFUSE_WDATA_0_3)) & 0x000000ff ) >> 0)
+#define GET_EFS_BYTE_13 (((REG32(ADR_EFUSE_WDATA_0_3)) & 0x0000ff00 ) >> 8)
+#define GET_EFS_BYTE_14 (((REG32(ADR_EFUSE_WDATA_0_3)) & 0x00ff0000 ) >> 16)
+#define GET_EFS_BYTE_15 (((REG32(ADR_EFUSE_WDATA_0_3)) & 0xff000000 ) >> 24)
+#define GET_EFS_BYTE_16 (((REG32(ADR_EFUSE_WDATA_0_4)) & 0x000000ff ) >> 0)
+#define GET_EFS_BYTE_17 (((REG32(ADR_EFUSE_WDATA_0_4)) & 0x0000ff00 ) >> 8)
+#define GET_EFS_BYTE_18 (((REG32(ADR_EFUSE_WDATA_0_4)) & 0x00ff0000 ) >> 16)
+#define GET_EFS_BYTE_19 (((REG32(ADR_EFUSE_WDATA_0_4)) & 0xff000000 ) >> 24)
+#define GET_EFS_BYTE_20 (((REG32(ADR_EFUSE_WDATA_0_5)) & 0x000000ff ) >> 0)
+#define GET_EFS_BYTE_21 (((REG32(ADR_EFUSE_WDATA_0_5)) & 0x0000ff00 ) >> 8)
+#define GET_EFS_BYTE_22 (((REG32(ADR_EFUSE_WDATA_0_5)) & 0x00ff0000 ) >> 16)
+#define GET_EFS_BYTE_23 (((REG32(ADR_EFUSE_WDATA_0_5)) & 0xff000000 ) >> 24)
+#define GET_EFS_BYTE_24 (((REG32(ADR_EFUSE_WDATA_0_6)) & 0x000000ff ) >> 0)
+#define GET_EFS_BYTE_25 (((REG32(ADR_EFUSE_WDATA_0_6)) & 0x0000ff00 ) >> 8)
+#define GET_EFS_BYTE_26 (((REG32(ADR_EFUSE_WDATA_0_6)) & 0x00ff0000 ) >> 16)
+#define GET_EFS_BYTE_27 (((REG32(ADR_EFUSE_WDATA_0_6)) & 0xff000000 ) >> 24)
+#define GET_EFS_BYTE_28 (((REG32(ADR_EFUSE_WDATA_0_7)) & 0x000000ff ) >> 0)
+#define GET_EFS_BYTE_29 (((REG32(ADR_EFUSE_WDATA_0_7)) & 0x0000ff00 ) >> 8)
+#define GET_EFS_BYTE_30 (((REG32(ADR_EFUSE_WDATA_0_7)) & 0x00ff0000 ) >> 16)
+#define GET_EFS_BYTE_31 (((REG32(ADR_EFUSE_WDATA_0_7)) & 0xff000000 ) >> 24)
+#define GET_SPI_M_FRONT_DLY (((REG32(ADR_SPI_DELAY)) & 0x0000ffff ) >> 0)
+#define GET_SPI_M_BACK_DLY (((REG32(ADR_SPI_DELAY)) & 0xffff0000 ) >> 16)
+#define GET_SPI_CLK_DIV (((REG32(ADR_SPI_CLK_DIV)) & 0x0000ffff ) >> 0)
+#define GET_SPI_MASTER_BUSY (((REG32(ADR_SPI_BUSY)) & 0x00000001 ) >> 0)
+#define GET_SPI_CLR (((REG32(ADR_SPI_CLR)) & 0x00000001 ) >> 0)
+#define GET_CPOL (((REG32(ADR_SPI_MAS_MODE)) & 0x00000001 ) >> 0)
+#define GET_CPHA (((REG32(ADR_SPI_MAS_MODE)) & 0x00000002 ) >> 1)
+#define GET_CSPOL (((REG32(ADR_SPI_M_CFG)) & 0x00000001 ) >> 0)
+#define GET_INV_DATA (((REG32(ADR_SPI_M_CFG)) & 0x00000002 ) >> 1)
+#define GET_FAST_CLK (((REG32(ADR_SPI_M_CFG)) & 0x00000004 ) >> 2)
+#define GET_AUTO_CSN (((REG32(ADR_SPI_M_CFG)) & 0x00000008 ) >> 3)
+#define GET_THREE_WIRE (((REG32(ADR_SPI_M_CFG)) & 0x000003f0 ) >> 4)
+#define GET_ENDIAN (((REG32(ADR_SPI_M_CFG)) & 0x00000400 ) >> 10)
+#define GET_EARLY_SAMPLE (((REG32(ADR_SPI_M_CFG)) & 0x00000800 ) >> 11)
+#define GET_SPI_CSN (((REG32(ADR_SPI_CFG)) & 0x00000001 ) >> 0)
+#define GET_CMD_LEN_SPIMAS (((REG32(ADR_SPI_MAS_COMMAND_LEN)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_TB0_31_0 (((REG32(ADR_MRX_MCAST_TB0_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_TB0_47_32 (((REG32(ADR_MRX_MCAST_TB0_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_MASK0_31_0 (((REG32(ADR_MRX_MCAST_MK0_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_MASK0_47_32 (((REG32(ADR_MRX_MCAST_MK0_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_CTRL_0 (((REG32(ADR_MRX_MCAST_CTRL0)) & 0x00000003 ) >> 0)
+#define GET_MRX_MCAST_TB1_31_0 (((REG32(ADR_MRX_MCAST_TB1_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_TB1_47_32 (((REG32(ADR_MRX_MCAST_TB1_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_MASK1_31_0 (((REG32(ADR_MRX_MCAST_MK1_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_MASK1_47_32 (((REG32(ADR_MRX_MCAST_MK1_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_CTRL_1 (((REG32(ADR_MRX_MCAST_CTRL1)) & 0x00000003 ) >> 0)
+#define GET_MRX_MCAST_TB2_31_0 (((REG32(ADR_MRX_MCAST_TB2_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_TB2_47_32 (((REG32(ADR_MRX_MCAST_TB2_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_MASK2_31_0 (((REG32(ADR_MRX_MCAST_MK2_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_MASK2_47_32 (((REG32(ADR_MRX_MCAST_MK2_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_CTRL_2 (((REG32(ADR_MRX_MCAST_CTRL2)) & 0x00000003 ) >> 0)
+#define GET_MRX_MCAST_TB3_31_0 (((REG32(ADR_MRX_MCAST_TB3_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_TB3_47_32 (((REG32(ADR_MRX_MCAST_TB3_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_MASK3_31_0 (((REG32(ADR_MRX_MCAST_MK3_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_MASK3_47_32 (((REG32(ADR_MRX_MCAST_MK3_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_CTRL_3 (((REG32(ADR_MRX_MCAST_CTRL3)) & 0x00000003 ) >> 0)
+#define GET_MRX_PHY_INFO (((REG32(ADR_MRX_PHY_INFO)) & 0xffffffff ) >> 0)
+#define GET_DBG_BA_TYPE (((REG32(ADR_MRX_BA_DBG)) & 0x0000003f ) >> 0)
+#define GET_DBG_BA_SEQ (((REG32(ADR_MRX_BA_DBG)) & 0x000fff00 ) >> 8)
+#define GET_MRX_FLT_TB0 (((REG32(ADR_MRX_FLT_TB0)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB1 (((REG32(ADR_MRX_FLT_TB1)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB2 (((REG32(ADR_MRX_FLT_TB2)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB3 (((REG32(ADR_MRX_FLT_TB3)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB4 (((REG32(ADR_MRX_FLT_TB4)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB5 (((REG32(ADR_MRX_FLT_TB5)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB6 (((REG32(ADR_MRX_FLT_TB6)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB7 (((REG32(ADR_MRX_FLT_TB7)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB8 (((REG32(ADR_MRX_FLT_TB8)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB9 (((REG32(ADR_MRX_FLT_TB9)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB10 (((REG32(ADR_MRX_FLT_TB10)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB11 (((REG32(ADR_MRX_FLT_TB11)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB12 (((REG32(ADR_MRX_FLT_TB12)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB13 (((REG32(ADR_MRX_FLT_TB13)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB14 (((REG32(ADR_MRX_FLT_TB14)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB15 (((REG32(ADR_MRX_FLT_TB15)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_EN0 (((REG32(ADR_MRX_FLT_EN0)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN1 (((REG32(ADR_MRX_FLT_EN1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN2 (((REG32(ADR_MRX_FLT_EN2)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN3 (((REG32(ADR_MRX_FLT_EN3)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN4 (((REG32(ADR_MRX_FLT_EN4)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN5 (((REG32(ADR_MRX_FLT_EN5)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN6 (((REG32(ADR_MRX_FLT_EN6)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN7 (((REG32(ADR_MRX_FLT_EN7)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN8 (((REG32(ADR_MRX_FLT_EN8)) & 0x0000ffff ) >> 0)
+#define GET_MRX_LEN_FLT (((REG32(ADR_MRX_LEN_FLT)) & 0x0000ffff ) >> 0)
+#define GET_RX_FLOW_DATA (((REG32(ADR_RX_FLOW_DATA)) & 0xffffffff ) >> 0)
+#define GET_RX_FLOW_MNG (((REG32(ADR_RX_FLOW_MNG)) & 0x0000ffff ) >> 0)
+#define GET_RX_FLOW_CTRL (((REG32(ADR_RX_FLOW_CTRL)) & 0x0000ffff ) >> 0)
+#define GET_MRX_STP_EN (((REG32(ADR_RX_TIME_STAMP_CFG)) & 0x00000001 ) >> 0)
+#define GET_MRX_STP_OFST (((REG32(ADR_RX_TIME_STAMP_CFG)) & 0x0000ff00 ) >> 8)
+#define GET_DBG_FF_FULL (((REG32(ADR_DBG_FF_FULL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_FF_FULL_CLR (((REG32(ADR_DBG_FF_FULL)) & 0x80000000 ) >> 31)
+#define GET_DBG_WFF_FULL (((REG32(ADR_DBG_WFF_FULL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_WFF_FULL_CLR (((REG32(ADR_DBG_WFF_FULL)) & 0x80000000 ) >> 31)
+#define GET_DBG_MB_FULL (((REG32(ADR_DBG_MB_FULL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_MB_FULL_CLR (((REG32(ADR_DBG_MB_FULL)) & 0x80000000 ) >> 31)
+#define GET_BA_CTRL (((REG32(ADR_BA_CTRL)) & 0x00000003 ) >> 0)
+#define GET_BA_DBG_EN (((REG32(ADR_BA_CTRL)) & 0x00000004 ) >> 2)
+#define GET_BA_AGRE_EN (((REG32(ADR_BA_CTRL)) & 0x00000008 ) >> 3)
+#define GET_BA_TA_31_0 (((REG32(ADR_BA_TA_0)) & 0xffffffff ) >> 0)
+#define GET_BA_TA_47_32 (((REG32(ADR_BA_TA_1)) & 0x0000ffff ) >> 0)
+#define GET_BA_TID (((REG32(ADR_BA_TID)) & 0x0000000f ) >> 0)
+#define GET_BA_ST_SEQ (((REG32(ADR_BA_ST_SEQ)) & 0x00000fff ) >> 0)
+#define GET_BA_SB0 (((REG32(ADR_BA_SB0)) & 0xffffffff ) >> 0)
+#define GET_BA_SB1 (((REG32(ADR_BA_SB1)) & 0xffffffff ) >> 0)
+#define GET_MRX_WD (((REG32(ADR_MRX_WATCH_DOG)) & 0x0001ffff ) >> 0)
+#define GET_ACK_GEN_EN (((REG32(ADR_ACK_GEN_EN)) & 0x00000001 ) >> 0)
+#define GET_BA_GEN_EN (((REG32(ADR_ACK_GEN_EN)) & 0x00000002 ) >> 1)
+#define GET_ACK_GEN_DUR (((REG32(ADR_ACK_GEN_PARA)) & 0x0000ffff ) >> 0)
+#define GET_ACK_GEN_INFO (((REG32(ADR_ACK_GEN_PARA)) & 0x00ff0000 ) >> 16)
+#define GET_ACK_GEN_RA_31_0 (((REG32(ADR_ACK_GEN_RA_0)) & 0xffffffff ) >> 0)
+#define GET_ACK_GEN_RA_47_32 (((REG32(ADR_ACK_GEN_RA_1)) & 0x0000ffff ) >> 0)
+#define GET_MIB_LEN_FAIL (((REG32(ADR_MIB_LEN_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_TRAP_HW_ID (((REG32(ADR_TRAP_HW_ID)) & 0x0000000f ) >> 0)
+#define GET_ID_IN_USE (((REG32(ADR_ID_IN_USE)) & 0x000000ff ) >> 0)
+#define GET_MRX_ERR (((REG32(ADR_MRX_ERR)) & 0xffffffff ) >> 0)
+#define GET_GRP_WSID (((REG32(ADR_GROUP_WSID)) & 0x0000000f ) >> 0)
+#define GET_ADDR1A_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00000003 ) >> 0)
+#define GET_ADDR2A_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x0000000c ) >> 2)
+#define GET_ADDR3A_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00000030 ) >> 4)
+#define GET_ADDR1B_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x000000c0 ) >> 6)
+#define GET_ADDR2B_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00000300 ) >> 8)
+#define GET_ADDR3B_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00000c00 ) >> 10)
+#define GET_ADDR3C_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00003000 ) >> 12)
+#define GET_FRM_CTRL (((REG32(ADR_FRAME_TYPE_CNTR_SET)) & 0x0000003f ) >> 0)
+#define GET_SCOREBOAD_SIZE (((REG32(ADR_AMPDU_SCOREBOAD_SIZE)) & 0x0000007f ) >> 0)
+#define GET_MASK_ABNORMAL_CRC (((REG32(ADR_CHANNEL)) & 0x00000001 ) >> 0)
+#define GET_PS_EN (((REG32(ADR_CHANNEL)) & 0x00000002 ) >> 1)
+#define GET_MULTI_AMPDU_W_EN (((REG32(ADR_CHANNEL)) & 0x00000004 ) >> 2)
+#define GET_BA_H_QUEUE_EN (((REG32(ADR_HIGH_PRIORITY_FRM_HW_ID)) & 0x00000001 ) >> 0)
+#define GET_EOSP_H_QUEUE_EN (((REG32(ADR_HIGH_PRIORITY_FRM_HW_ID)) & 0x00000002 ) >> 1)
+#define GET_EOSP_HW_ID (((REG32(ADR_HIGH_PRIORITY_FRM_HW_ID)) & 0x0000003c ) >> 2)
+#define GET_BA_HW_ID (((REG32(ADR_HIGH_PRIORITY_FRM_HW_ID)) & 0x000003c0 ) >> 6)
+#define GET_IDX_EXTEND (((REG32(ADR_DUAL_IDX_EXTEND)) & 0x00000001 ) >> 0)
+#define GET_MRX_FLT_EN9 (((REG32(ADR_MRX_FLT_EN9)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN10 (((REG32(ADR_MRX_FLT_EN10)) & 0x0000ffff ) >> 0)
+#define GET_CSR_PHY_INFO (((REG32(ADR_PHY_INFO)) & 0x00007fff ) >> 0)
+#define GET_AMPDU_SIG (((REG32(ADR_AMPDU_SIG)) & 0x000000ff ) >> 0)
+#define GET_MIB_AMPDU (((REG32(ADR_MIB_AMPDU)) & 0xffffffff ) >> 0)
+#define GET_LEN_FLT (((REG32(ADR_LEN_FLT)) & 0x0000ffff ) >> 0)
+#define GET_MIB_DELIMITER (((REG32(ADR_MIB_DELIMITER)) & 0x0000ffff ) >> 0)
+#define GET_MTX_INT_Q0_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x00010000 ) >> 16)
+#define GET_MTX_INT_Q0_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x00020000 ) >> 17)
+#define GET_MTX_INT_Q1_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x00040000 ) >> 18)
+#define GET_MTX_INT_Q1_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x00080000 ) >> 19)
+#define GET_MTX_INT_Q2_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x00100000 ) >> 20)
+#define GET_MTX_INT_Q2_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x00200000 ) >> 21)
+#define GET_MTX_INT_Q3_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x00400000 ) >> 22)
+#define GET_MTX_INT_Q3_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x00800000 ) >> 23)
+#define GET_MTX_INT_Q4_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x01000000 ) >> 24)
+#define GET_MTX_INT_Q4_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x02000000 ) >> 25)
+#define GET_MTX_INT_Q5_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x04000000 ) >> 26)
+#define GET_MTX_INT_Q5_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x08000000 ) >> 27)
+#define GET_MTX_EN_INT_Q0_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x00010000 ) >> 16)
+#define GET_MTX_EN_INT_Q0_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x00020000 ) >> 17)
+#define GET_MTX_EN_INT_Q1_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x00040000 ) >> 18)
+#define GET_MTX_EN_INT_Q1_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x00080000 ) >> 19)
+#define GET_MTX_EN_INT_Q2_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x00100000 ) >> 20)
+#define GET_MTX_EN_INT_Q2_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x00200000 ) >> 21)
+#define GET_MTX_EN_INT_Q3_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x00400000 ) >> 22)
+#define GET_MTX_EN_INT_Q3_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x00800000 ) >> 23)
+#define GET_MTX_EN_INT_Q4_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x01000000 ) >> 24)
+#define GET_MTX_EN_INT_Q4_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x02000000 ) >> 25)
+#define GET_MTX_EN_INT_Q5_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x04000000 ) >> 26)
+#define GET_MTX_EN_INT_Q5_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x08000000 ) >> 27)
+#define GET_MTX_MTX2PHY_SLOW (((REG32(ADR_MTX_MISC_EN)) & 0x00000001 ) >> 0)
+#define GET_MTX_M2M_SLOW_PRD (((REG32(ADR_MTX_MISC_EN)) & 0x0000000e ) >> 1)
+#define GET_MTX_AMPDU_CRC8_AUTO (((REG32(ADR_MTX_MISC_EN)) & 0x00000020 ) >> 5)
+#define GET_MTX_BLOCKTX_IGNORE_BT_BUSY (((REG32(ADR_MTX_MISC_EN)) & 0x00000040 ) >> 6)
+#define GET_MTX_RAW_DATA_MODE (((REG32(ADR_MTX_MISC_EN)) & 0x00000080 ) >> 7)
+#define GET_MTX_BLOCKTX_IGNORE_TOMAC_TX_IP (((REG32(ADR_MTX_MISC_EN)) & 0x00000800 ) >> 11)
+#define GET_MTX_BLOCKTX_IGNORE_TOMAC_RX_EN (((REG32(ADR_MTX_MISC_EN)) & 0x00001000 ) >> 12)
+#define GET_MTX_BLOCKTX_IGNORE_TOMAC_CCA_CS (((REG32(ADR_MTX_MISC_EN)) & 0x00002000 ) >> 13)
+#define GET_MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_SECONDARY (((REG32(ADR_MTX_MISC_EN)) & 0x00004000 ) >> 14)
+#define GET_MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_PRIMARY (((REG32(ADR_MTX_MISC_EN)) & 0x00008000 ) >> 15)
+#define GET_MTX_HALT_Q_MB (((REG32(ADR_MTX_MISC_EN)) & 0x007f0000 ) >> 16)
+#define GET_MTX_IGNORE_PHYRX_IFS_DELTATIME (((REG32(ADR_MTX_MISC_EN)) & 0x01000000 ) >> 24)
+#define GET_MTX_SELFSTA_PS (((REG32(ADR_MTX_MISC_EN)) & 0x02000000 ) >> 25)
+#define GET_NO_PKT_BUF_REDUCTION (((REG32(ADR_MTX_TX_REPORT_OPTION)) & 0x00000001 ) >> 0)
+#define GET_NO_REDUCE_TXALLFAIL_PKT (((REG32(ADR_MTX_TX_REPORT_OPTION)) & 0x00000004 ) >> 2)
+#define GET_NO_REDUCE_PKT_PEERPS_MPDU (((REG32(ADR_MTX_TX_REPORT_OPTION)) & 0x00000010 ) >> 4)
+#define GET_NO_REDUCE_PKT_PEERPS_AMPDUV1P2 (((REG32(ADR_MTX_TX_REPORT_OPTION)) & 0x00000040 ) >> 6)
+#define GET_NO_REDUCE_PKT_PEERPS_AMPDUV1P3 (((REG32(ADR_MTX_TX_REPORT_OPTION)) & 0x00000080 ) >> 7)
+#define GET_RO_PTC_SCHEDULE (((REG32(ADR_MTX_STATUS0)) & 0x0000000f ) >> 0)
+#define GET_RO_FSM_MTXPTC (((REG32(ADR_MTX_STATUS0)) & 0x00000070 ) >> 4)
+#define GET_RO_ACT_MASK (((REG32(ADR_MTX_STATUS0)) & 0x00007f00 ) >> 8)
+#define GET_RO_CAND_MASK (((REG32(ADR_MTX_STATUS0)) & 0x007f0000 ) >> 16)
+#define GET_RO_WAIT_RESPONSE_PHASE (((REG32(ADR_MTX_STATUS0)) & 0x03000000 ) >> 24)
+#define GET_RO_FSM_MTXHALT (((REG32(ADR_MTX_STATUS0)) & 0x30000000 ) >> 28)
+#define GET_RO_FSM_MTXDMA (((REG32(ADR_MTX_STATUS4)) & 0x00000007 ) >> 0)
+#define GET_RO_FSM_MTXPHYTX (((REG32(ADR_MTX_STATUS4)) & 0x00000070 ) >> 4)
+#define GET_RO_MTXDMA_CMD (((REG32(ADR_MTX_STATUS4)) & 0x00003f00 ) >> 8)
+#define GET_RO_TXOP_INTERVAL (((REG32(ADR_MTX_STATUS4)) & 0xffff0000 ) >> 16)
+#define GET_MTX_HALT_MODE0 (((REG32(ADR_MTX_HALT_OPTION)) & 0x00000001 ) >> 0)
+#define GET_BLOCK_TXQ (((REG32(ADR_MTX_HALT_OPTION)) & 0x007f0000 ) >> 16)
+#define GET_MTX_HALT_IGNORE_TXREQ_EN (((REG32(ADR_MTX_HALT_OPTION)) & 0x01000000 ) >> 24)
+#define GET_MTX_HALT_IGNORE_RXREQ_EN (((REG32(ADR_MTX_HALT_OPTION)) & 0x02000000 ) >> 25)
+#define GET_DBG_PHYTX_PROCEED (((REG32(ADR_MTX_PHYTX_DBG1)) & 0x00000001 ) >> 0)
+#define GET_MTX_MIB_CNT0_FRAME (((REG32(ADR_MTX_MIB_WSID0)) & 0x000003ff ) >> 0)
+#define GET_MTX_MIB_CNT0_ATTEMPT (((REG32(ADR_MTX_MIB_WSID0)) & 0x000ffc00 ) >> 10)
+#define GET_MTX_MIB_CNT0_SUCC (((REG32(ADR_MTX_MIB_WSID0)) & 0x3ff00000 ) >> 20)
+#define GET_MTX_MIB_EN0 (((REG32(ADR_MTX_MIB_WSID0)) & 0x40000000 ) >> 30)
+#define GET_MTX_MIB_CNT1_FRAME (((REG32(ADR_MTX_MIB_WSID1)) & 0x000003ff ) >> 0)
+#define GET_MTX_MIB_CNT1_ATTEMPT (((REG32(ADR_MTX_MIB_WSID1)) & 0x000ffc00 ) >> 10)
+#define GET_MTX_MIB_CNT1_SUCC (((REG32(ADR_MTX_MIB_WSID1)) & 0x3ff00000 ) >> 20)
+#define GET_MTX_MIB_EN1 (((REG32(ADR_MTX_MIB_WSID1)) & 0x40000000 ) >> 30)
+#define GET_MTX_MIB_CNT2_FRAME (((REG32(ADR_MTX_MIB_WSID2)) & 0x000003ff ) >> 0)
+#define GET_MTX_MIB_CNT2_ATTEMPT (((REG32(ADR_MTX_MIB_WSID2)) & 0x000ffc00 ) >> 10)
+#define GET_MTX_MIB_CNT2_SUCC (((REG32(ADR_MTX_MIB_WSID2)) & 0x3ff00000 ) >> 20)
+#define GET_MTX_MIB_EN2 (((REG32(ADR_MTX_MIB_WSID2)) & 0x40000000 ) >> 30)
+#define GET_MTX_MIB_CNT3_FRAME (((REG32(ADR_MTX_MIB_WSID3)) & 0x000003ff ) >> 0)
+#define GET_MTX_MIB_CNT3_ATTEMPT (((REG32(ADR_MTX_MIB_WSID3)) & 0x000ffc00 ) >> 10)
+#define GET_MTX_MIB_CNT3_SUCC (((REG32(ADR_MTX_MIB_WSID3)) & 0x3ff00000 ) >> 20)
+#define GET_MTX_MIB_EN3 (((REG32(ADR_MTX_MIB_WSID3)) & 0x40000000 ) >> 30)
+#define GET_MTX_MIB_CNT4_FRAME (((REG32(ADR_MTX_MIB_WSID4)) & 0x000003ff ) >> 0)
+#define GET_MTX_MIB_CNT4_ATTEMPT (((REG32(ADR_MTX_MIB_WSID4)) & 0x000ffc00 ) >> 10)
+#define GET_MTX_MIB_CNT4_SUCC (((REG32(ADR_MTX_MIB_WSID4)) & 0x3ff00000 ) >> 20)
+#define GET_MTX_MIB_EN4 (((REG32(ADR_MTX_MIB_WSID4)) & 0x40000000 ) >> 30)
+#define GET_MTX_MIB_CNT5_FRAME (((REG32(ADR_MTX_MIB_WSID5)) & 0x000003ff ) >> 0)
+#define GET_MTX_MIB_CNT5_ATTEMPT (((REG32(ADR_MTX_MIB_WSID5)) & 0x000ffc00 ) >> 10)
+#define GET_MTX_MIB_CNT5_SUCC (((REG32(ADR_MTX_MIB_WSID5)) & 0x3ff00000 ) >> 20)
+#define GET_MTX_MIB_EN5 (((REG32(ADR_MTX_MIB_WSID5)) & 0x40000000 ) >> 30)
+#define GET_MTX_MIB_CNT6_FRAME (((REG32(ADR_MTX_MIB_WSID6)) & 0x000003ff ) >> 0)
+#define GET_MTX_MIB_CNT6_ATTEMPT (((REG32(ADR_MTX_MIB_WSID6)) & 0x000ffc00 ) >> 10)
+#define GET_MTX_MIB_CNT6_SUCC (((REG32(ADR_MTX_MIB_WSID6)) & 0x3ff00000 ) >> 20)
+#define GET_MTX_MIB_EN6 (((REG32(ADR_MTX_MIB_WSID6)) & 0x40000000 ) >> 30)
+#define GET_MTX_MIB_CNT7_FRAME (((REG32(ADR_MTX_MIB_WSID7)) & 0x000003ff ) >> 0)
+#define GET_MTX_MIB_CNT7_ATTEMPT (((REG32(ADR_MTX_MIB_WSID7)) & 0x000ffc00 ) >> 10)
+#define GET_MTX_MIB_CNT7_SUCC (((REG32(ADR_MTX_MIB_WSID7)) & 0x3ff00000 ) >> 20)
+#define GET_MTX_MIB_EN7 (((REG32(ADR_MTX_MIB_WSID7)) & 0x40000000 ) >> 30)
+#define GET_EN_UNEXPECT_WSID (((REG32(ADR_STAT_CONF0)) & 0x00000001 ) >> 0)
+#define GET_EN_STAT_FINISH_INT (((REG32(ADR_STAT_CONF0)) & 0x00000002 ) >> 1)
+#define GET_STAT_EN_MB (((REG32(ADR_STAT_CONF0)) & 0x00000040 ) >> 6)
+#define GET_STAT_MB_TARGET (((REG32(ADR_STAT_CONF0)) & 0x00000080 ) >> 7)
+#define GET_STAT_UNEXPECT_WSID (((REG32(ADR_STAT_CONF0)) & 0x00000100 ) >> 8)
+#define GET_STAT_FINISH (((REG32(ADR_STAT_CONF0)) & 0x00000200 ) >> 9)
+#define GET_STAT_PKT_ID (((REG32(ADR_STAT_CONF0)) & 0x007f0000 ) >> 16)
+#define GET_STAT_FSM (((REG32(ADR_STAT_CONF0)) & 0x1f000000 ) >> 24)
+#define GET_STAT_ENABLE (((REG32(ADR_STAT_CONF0)) & 0x20000000 ) >> 29)
+#define GET_STAT_WSID (((REG32(ADR_STAT_CONF1)) & 0x00000007 ) >> 0)
+#define GET_STAT_FREEZE (((REG32(ADR_STAT_CONF1)) & 0x00000100 ) >> 8)
+#define GET_STAT_CLR (((REG32(ADR_STAT_CONF1)) & 0x00000200 ) >> 9)
+#define GET_STAT_CLR_DONE (((REG32(ADR_STAT_CONF1)) & 0x00000400 ) >> 10)
+#define GET_MAC_TX_PS_UNLOCK (((REG32(ADR_MTX_PEER_PS_LOCK)) & 0x000000ff ) >> 0)
+#define GET_MAC_TX_PEER_PS_LOCK_EN (((REG32(ADR_MTX_PEER_PS_LOCK)) & 0x00000100 ) >> 8)
+#define GET_MAC_TX_PEER_PS_LOCK_AUTOLOCK_EN (((REG32(ADR_MTX_PEER_PS_LOCK)) & 0x00000200 ) >> 9)
+#define GET_MAC_TX_PS_LOCK (((REG32(ADR_MTX_PEER_PS_LOCK)) & 0xff000000 ) >> 24)
+#define GET_MAC_TX_PS_LOCK_STATUS (((REG32(ADR_MTX_PEER_LOCK_STATUS)) & 0x000000ff ) >> 0)
+#define GET_MTX_RATERPT_HWID (((REG32(ADR_MTX_RATERPT)) & 0x0000000f ) >> 0)
+#define GET_CTYPE_RATE_RPT (((REG32(ADR_MTX_RATERPT)) & 0x00000070 ) >> 4)
+#define GET_MTX_DBGOPT_FORCE_TXMAJOR_RATE (((REG32(ADR_MTX_DBGOPT_FORCE_RATE)) & 0x000000ff ) >> 0)
+#define GET_MTX_DBGOPT_FORCE_TXCTRL_RATE (((REG32(ADR_MTX_DBGOPT_FORCE_RATE)) & 0x0000ff00 ) >> 8)
+#define GET_MTX_DBGOPT_FORCE_DO_RTS_CTS_MODE (((REG32(ADR_MTX_DBGOPT_FORCE_RATE)) & 0x00030000 ) >> 16)
+#define GET_MTX_DBGOPT_FORCE_TXMAJOR_RATE_EN (((REG32(ADR_MTX_DBGOPT_FORCE_RATE_ENABLE)) & 0x00000001 ) >> 0)
+#define GET_MTX_DBGOPT_FORCE_TXCTRL_RATE_EN (((REG32(ADR_MTX_DBGOPT_FORCE_RATE_ENABLE)) & 0x00000004 ) >> 2)
+#define GET_MTX_DBGOPT_FORCE_DO_RTS_CTS_MODE_EN (((REG32(ADR_MTX_DBGOPT_FORCE_RATE_ENABLE)) & 0x00000010 ) >> 4)
+#define GET_RO_PHYTXIP_TIMEOUT_CNT (((REG32(ADR_MTX_DBG_PHYTXIPTIMEOUT)) & 0x0000000f ) >> 0)
+#define GET_DBG_PHYTXIP_TIMEOUT_RECOVERY (((REG32(ADR_MTX_DBG_PHYTXIPTIMEOUT)) & 0x00000100 ) >> 8)
+#define GET_DBG_MTX_IGNORE_NAV (((REG32(ADR_MTX_DBG_MORE)) & 0x00000001 ) >> 0)
+#define GET_RO_IFSAIR1 (((REG32(ADR_MTX_DBG_ROIFSAIR1)) & 0xffffffff ) >> 0)
+#define GET_RO_IFSAIR2 (((REG32(ADR_MTX_DBG_ROIFSAIR2)) & 0xffffffff ) >> 0)
+#define GET_MTX_BCN_PKT_ID0 (((REG32(ADR_MTX_BCN_PKT_SET0)) & 0x0000007f ) >> 0)
+#define GET_MTX_BCN_PKT_ID1 (((REG32(ADR_MTX_BCN_PKT_SET1)) & 0x0000007f ) >> 0)
+#define GET_MTX_DTIM_OFST0 (((REG32(ADR_MTX_BCN_DTIM_SET0)) & 0x000003ff ) >> 0)
+#define GET_MTX_DTIM_OFST1 (((REG32(ADR_MTX_BCN_DTIM_SET1)) & 0x000003ff ) >> 0)
+#define GET_MTX_DTIM_NUM (((REG32(ADR_MTX_BCN_DTIM_CONFG)) & 0x000000ff ) >> 0)
+#define GET_MTX_INT_DTIM_NUM (((REG32(ADR_MTX_BCN_DTIM_CONFG)) & 0x0000ff00 ) >> 8)
+#define GET_MTX_INT_DTIM (((REG32(ADR_MTX_BCN_DTIM_INT_W1CLR)) & 0x00000001 ) >> 0)
+#define GET_MTX_INT_BCN (((REG32(ADR_MTX_BCN_INT_STS)) & 0x00000001 ) >> 0)
+#define GET_MTX_EN_INT_BCN (((REG32(ADR_MTX_BCN_EN_INT)) & 0x00000002 ) >> 1)
+#define GET_MTX_EN_INT_DTIM (((REG32(ADR_MTX_BCN_EN_INT)) & 0x00000008 ) >> 3)
+#define GET_MTX_BCN_TIMER_EN (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00000001 ) >> 0)
+#define GET_MTX_TIME_STAMP_AUTO_FILL (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00000002 ) >> 1)
+#define GET_MTX_DTIM_CNT_AUTO_FILL (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00000008 ) >> 3)
+#define GET_MTX_TSF_TIMER_EN (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00000020 ) >> 5)
+#define GET_TXQ5_DTIM_BEACON_BURST_MNG (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00010000 ) >> 16)
+#define GET_MTX_BCN_AUTO_SEQ_NO (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00020000 ) >> 17)
+#define GET_MTX_BCN_PKTID_CH_LOCK (((REG32(ADR_MTX_BCN_MISC)) & 0x00000001 ) >> 0)
+#define GET_MTX_BCN_CFG_VLD (((REG32(ADR_MTX_BCN_MISC)) & 0x00000006 ) >> 1)
+#define GET_MTX_AUTO_BCN_ONGOING (((REG32(ADR_MTX_BCN_MISC)) & 0x00000008 ) >> 3)
+#define GET_MTX_BCN_TIMER (((REG32(ADR_MTX_BCN_MISC)) & 0xffff0000 ) >> 16)
+#define GET_MTX_BCN_PERIOD (((REG32(ADR_MTX_BCN_PRD)) & 0x0000ffff ) >> 0)
+#define GET_MTX_BCN_TSF_L (((REG32(ADR_MTX_BCN_TSF_L)) & 0xffffffff ) >> 0)
+#define GET_MTX_BCN_TSF_U (((REG32(ADR_MTX_BCN_TSF_U)) & 0xffffffff ) >> 0)
+#define GET_TOUT_B (((REG32(ADR_MTX_TIME_TOUT)) & 0x000000ff ) >> 0)
+#define GET_TOUT_AGN (((REG32(ADR_MTX_TIME_TOUT)) & 0x0000ff00 ) >> 8)
+#define GET_EIFS_IN_SLOT (((REG32(ADR_MTX_TIME_TOUT)) & 0x003f0000 ) >> 16)
+#define GET_TXSIFS_SUB_MIN (((REG32(ADR_MTX_TIME_IFS)) & 0x0000000f ) >> 0)
+#define GET_TXSIFS_SUB_MAX (((REG32(ADR_MTX_TIME_IFS)) & 0x000000f0 ) >> 4)
+#define GET_SLOTTIME (((REG32(ADR_MTX_TIME_IFS)) & 0x00001f00 ) >> 8)
+#define GET_SIFS (((REG32(ADR_MTX_TIME_IFS)) & 0x001f0000 ) >> 16)
+#define GET_NAVCS_PHYCS_FALL_OFFSET_STEP (((REG32(ADR_MTX_TIME_FINETUNE)) & 0x0000007f ) >> 0)
+#define GET_TX_IP_FALL_OFFSET_STEP (((REG32(ADR_MTX_TIME_FINETUNE)) & 0x00007f00 ) >> 8)
+#define GET_PHYTXSTART_NCYCLE (((REG32(ADR_MTX_TIME_FINETUNE)) & 0x007f0000 ) >> 16)
+#define GET_SIGEXT (((REG32(ADR_MTX_TIME_FINETUNE)) & 0x0f000000 ) >> 24)
+#define GET_MAC_CLK_80M (((REG32(ADR_MTX_TIME_FINETUNE)) & 0x10000000 ) >> 28)
+#define GET_RO_MTX_TX_EN (((REG32(ADR_MTX_STATUS)) & 0x00100000 ) >> 20)
+#define GET_RO_MAC_TX_FIFO_WINC (((REG32(ADR_MTX_STATUS)) & 0x00200000 ) >> 21)
+#define GET_RO_MAC_TX_FIFO_WFULL_MX (((REG32(ADR_MTX_STATUS)) & 0x00400000 ) >> 22)
+#define GET_RO_MAC_TX_FIFO_WEMPTY (((REG32(ADR_MTX_STATUS)) & 0x00800000 ) >> 23)
+#define GET_TOMAC_TX_IP (((REG32(ADR_MTX_STATUS)) & 0x01000000 ) >> 24)
+#define GET_TOMAC_ED_CCA_PRIMARY_MX (((REG32(ADR_MTX_STATUS)) & 0x10000000 ) >> 28)
+#define GET_TOMAC_ED_CCA_SECONDARY_MX (((REG32(ADR_MTX_STATUS)) & 0x20000000 ) >> 29)
+#define GET_TOMAC_CS_CCA_MX (((REG32(ADR_MTX_STATUS)) & 0x40000000 ) >> 30)
+#define GET_BT_BUSY (((REG32(ADR_MTX_STATUS)) & 0x80000000 ) >> 31)
+#define GET_MTX_DBG_PHYRX_IFS_DELTATIME (((REG32(ADR_MTX_PHYRXIFS_DBG)) & 0x000007ff ) >> 0)
+#define GET_RO_IFSST0 (((REG32(ADR_MTX_DBG_IFSAIRRO0)) & 0xffffffff ) >> 0)
+#define GET_RO_IFSST1 (((REG32(ADR_MTX_DBG_IFSAIRRO1)) & 0xffffffff ) >> 0)
+#define GET_RO_IFSST2 (((REG32(ADR_MTX_DBG_IFSAIRRO2)) & 0xffffffff ) >> 0)
+#define GET_RO_IFSST3 (((REG32(ADR_MTX_DBG_IFSAIRRO3)) & 0xffffffff ) >> 0)
+#define GET_MTX_NAV (((REG32(ADR_MTX_NAV)) & 0x0000ffff ) >> 0)
+#define GET_RO_MTX_BASE1 (((REG32(ADR_MTX_DBG_RO_BASE1)) & 0xffffffff ) >> 0)
+#define GET_RO_MTX_BASE2 (((REG32(ADR_MTX_DBG_RO_BASE2)) & 0xffffffff ) >> 0)
+#define GET_RO_MTX_BASE3 (((REG32(ADR_MTX_DBG_RO_BASE3)) & 0xffffffff ) >> 0)
+#define GET_TXQ0_MTX_Q_RND_MODE (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000007 ) >> 0)
+#define GET_TXQ0_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4)
+#define GET_TXQ0_Q_NULLDATAFRAME_GEN_EN (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x80000000 ) >> 31)
+#define GET_TXQ0_MTX_Q_AIFSN (((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0x0000000f ) >> 0)
+#define GET_TXQ0_MTX_Q_ECWMIN (((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8)
+#define GET_TXQ0_MTX_Q_ECWMAX (((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12)
+#define GET_TXQ0_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16)
+#define GET_TXQ0_MTX_Q_BKF_CNT_FIX (((REG32(ADR_TXQ0_MTX_Q_BKF_CNT_DBG)) & 0x0000ffff ) >> 0)
+#define GET_TXQ0_RO_FSM_TXQ (((REG32(ADR_TXQ0_MTX_Q_HWDBG)) & 0x00000003 ) >> 0)
+#define GET_TXQ0_RO_TRY_CNT (((REG32(ADR_TXQ0_MTX_Q_HWDBG)) & 0x000000f0 ) >> 4)
+#define GET_TXQ0_RO_RATESET_IDX (((REG32(ADR_TXQ0_MTX_Q_HWDBG)) & 0x00000300 ) >> 8)
+#define GET_TXQ0_RO_AIFS_CNT (((REG32(ADR_TXQ0_MTX_Q_HWDBG)) & 0x0000f000 ) >> 12)
+#define GET_TXQ0_RO_BKF_CNT (((REG32(ADR_TXQ0_MTX_Q_HWDBG)) & 0xffff0000 ) >> 16)
+#define GET_TXQ0_RO_PKTID (((REG32(ADR_TXQ0_MTX_Q_HWDBG2)) & 0x0000007f ) >> 0)
+#define GET_TXQ1_MTX_Q_RND_MODE (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000007 ) >> 0)
+#define GET_TXQ1_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4)
+#define GET_TXQ1_Q_NULLDATAFRAME_GEN_EN (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x80000000 ) >> 31)
+#define GET_TXQ1_MTX_Q_AIFSN (((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0x0000000f ) >> 0)
+#define GET_TXQ1_MTX_Q_ECWMIN (((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8)
+#define GET_TXQ1_MTX_Q_ECWMAX (((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12)
+#define GET_TXQ1_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16)
+#define GET_TXQ1_MTX_Q_BKF_CNT_FIX (((REG32(ADR_TXQ1_MTX_Q_BKF_CNT_DBG)) & 0x0000ffff ) >> 0)
+#define GET_TXQ1_RO_FSM_TXQ (((REG32(ADR_TXQ1_MTX_Q_HWDBG)) & 0x00000003 ) >> 0)
+#define GET_TXQ1_RO_TRY_CNT (((REG32(ADR_TXQ1_MTX_Q_HWDBG)) & 0x000000f0 ) >> 4)
+#define GET_TXQ1_RO_RATESET_IDX (((REG32(ADR_TXQ1_MTX_Q_HWDBG)) & 0x00000300 ) >> 8)
+#define GET_TXQ1_RO_AIFS_CNT (((REG32(ADR_TXQ1_MTX_Q_HWDBG)) & 0x0000f000 ) >> 12)
+#define GET_TXQ1_RO_BKF_CNT (((REG32(ADR_TXQ1_MTX_Q_HWDBG)) & 0xffff0000 ) >> 16)
+#define GET_TXQ1_RO_PKTID (((REG32(ADR_TXQ1_MTX_Q_HWDBG2)) & 0x0000007f ) >> 0)
+#define GET_TXQ2_MTX_Q_RND_MODE (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000007 ) >> 0)
+#define GET_TXQ2_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4)
+#define GET_TXQ2_Q_NULLDATAFRAME_GEN_EN (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x80000000 ) >> 31)
+#define GET_TXQ2_MTX_Q_AIFSN (((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0x0000000f ) >> 0)
+#define GET_TXQ2_MTX_Q_ECWMIN (((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8)
+#define GET_TXQ2_MTX_Q_ECWMAX (((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12)
+#define GET_TXQ2_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16)
+#define GET_TXQ2_MTX_Q_BKF_CNT_FIX (((REG32(ADR_TXQ2_MTX_Q_BKF_CNT_DBG)) & 0x0000ffff ) >> 0)
+#define GET_TXQ2_RO_FSM_TXQ (((REG32(ADR_TXQ2_MTX_Q_HWDBG)) & 0x00000003 ) >> 0)
+#define GET_TXQ2_RO_TRY_CNT (((REG32(ADR_TXQ2_MTX_Q_HWDBG)) & 0x000000f0 ) >> 4)
+#define GET_TXQ2_RO_RATESET_IDX (((REG32(ADR_TXQ2_MTX_Q_HWDBG)) & 0x00000300 ) >> 8)
+#define GET_TXQ2_RO_AIFS_CNT (((REG32(ADR_TXQ2_MTX_Q_HWDBG)) & 0x0000f000 ) >> 12)
+#define GET_TXQ2_RO_BKF_CNT (((REG32(ADR_TXQ2_MTX_Q_HWDBG)) & 0xffff0000 ) >> 16)
+#define GET_TXQ2_RO_PKTID (((REG32(ADR_TXQ2_MTX_Q_HWDBG2)) & 0x0000007f ) >> 0)
+#define GET_TXQ3_MTX_Q_RND_MODE (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000007 ) >> 0)
+#define GET_TXQ3_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4)
+#define GET_TXQ3_Q_NULLDATAFRAME_GEN_EN (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x80000000 ) >> 31)
+#define GET_TXQ3_MTX_Q_AIFSN (((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0x0000000f ) >> 0)
+#define GET_TXQ3_MTX_Q_ECWMIN (((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8)
+#define GET_TXQ3_MTX_Q_ECWMAX (((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12)
+#define GET_TXQ3_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16)
+#define GET_TXQ3_MTX_Q_BKF_CNT_FIX (((REG32(ADR_TXQ3_MTX_Q_BKF_CNT_DBG)) & 0x0000ffff ) >> 0)
+#define GET_TXQ3_RO_FSM_TXQ (((REG32(ADR_TXQ3_MTX_Q_HWDBG)) & 0x00000003 ) >> 0)
+#define GET_TXQ3_RO_TRY_CNT (((REG32(ADR_TXQ3_MTX_Q_HWDBG)) & 0x000000f0 ) >> 4)
+#define GET_TXQ3_RO_RATESET_IDX (((REG32(ADR_TXQ3_MTX_Q_HWDBG)) & 0x00000300 ) >> 8)
+#define GET_TXQ3_RO_AIFS_CNT (((REG32(ADR_TXQ3_MTX_Q_HWDBG)) & 0x0000f000 ) >> 12)
+#define GET_TXQ3_RO_BKF_CNT (((REG32(ADR_TXQ3_MTX_Q_HWDBG)) & 0xffff0000 ) >> 16)
+#define GET_TXQ3_RO_PKTID (((REG32(ADR_TXQ3_MTX_Q_HWDBG2)) & 0x0000007f ) >> 0)
+#define GET_TXQ4_MTX_Q_RND_MODE (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000007 ) >> 0)
+#define GET_TXQ4_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4)
+#define GET_TXQ4_Q_NULLDATAFRAME_GEN_EN (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x80000000 ) >> 31)
+#define GET_TXQ4_MTX_Q_AIFSN (((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0x0000000f ) >> 0)
+#define GET_TXQ4_MTX_Q_ECWMIN (((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8)
+#define GET_TXQ4_MTX_Q_ECWMAX (((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12)
+#define GET_TXQ4_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16)
+#define GET_TXQ4_MTX_Q_BKF_CNT_FIX (((REG32(ADR_TXQ4_MTX_Q_BKF_CNT_DBG)) & 0x0000ffff ) >> 0)
+#define GET_TXQ4_RO_FSM_TXQ (((REG32(ADR_TXQ4_MTX_Q_HWDBG)) & 0x00000003 ) >> 0)
+#define GET_TXQ4_RO_TRY_CNT (((REG32(ADR_TXQ4_MTX_Q_HWDBG)) & 0x000000f0 ) >> 4)
+#define GET_TXQ4_RO_RATESET_IDX (((REG32(ADR_TXQ4_MTX_Q_HWDBG)) & 0x00000300 ) >> 8)
+#define GET_TXQ4_RO_AIFS_CNT (((REG32(ADR_TXQ4_MTX_Q_HWDBG)) & 0x0000f000 ) >> 12)
+#define GET_TXQ4_RO_BKF_CNT (((REG32(ADR_TXQ4_MTX_Q_HWDBG)) & 0xffff0000 ) >> 16)
+#define GET_TXQ4_RO_PKTID (((REG32(ADR_TXQ4_MTX_Q_HWDBG2)) & 0x0000007f ) >> 0)
+#define GET_TXQ5_MTX_Q_RND_MODE (((REG32(ADR_TXQ5_MTX_Q_MISC_EN)) & 0x00000007 ) >> 0)
+#define GET_TXQ5_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ5_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4)
+#define GET_TXQ5_Q_NULLDATAFRAME_GEN_EN (((REG32(ADR_TXQ5_MTX_Q_MISC_EN)) & 0x80000000 ) >> 31)
+#define GET_TXQ5_MTX_Q_AIFSN (((REG32(ADR_TXQ5_MTX_Q_AIFSN)) & 0x0000000f ) >> 0)
+#define GET_TXQ5_MTX_Q_ECWMIN (((REG32(ADR_TXQ5_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8)
+#define GET_TXQ5_MTX_Q_ECWMAX (((REG32(ADR_TXQ5_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12)
+#define GET_TXQ5_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ5_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16)
+#define GET_TXQ5_MTX_Q_BKF_CNT_FIX (((REG32(ADR_TXQ5_MTX_Q_BKF_CNT_DBG)) & 0x0000ffff ) >> 0)
+#define GET_TXQ5_RO_FSM_TXQ (((REG32(ADR_TXQ5_MTX_Q_HWDBG)) & 0x00000003 ) >> 0)
+#define GET_TXQ5_RO_TRY_CNT (((REG32(ADR_TXQ5_MTX_Q_HWDBG)) & 0x000000f0 ) >> 4)
+#define GET_TXQ5_RO_RATESET_IDX (((REG32(ADR_TXQ5_MTX_Q_HWDBG)) & 0x00000300 ) >> 8)
+#define GET_TXQ5_RO_AIFS_CNT (((REG32(ADR_TXQ5_MTX_Q_HWDBG)) & 0x0000f000 ) >> 12)
+#define GET_TXQ5_RO_BKF_CNT (((REG32(ADR_TXQ5_MTX_Q_HWDBG)) & 0xffff0000 ) >> 16)
+#define GET_TXQ5_RO_PKTID (((REG32(ADR_TXQ5_MTX_Q_HWDBG2)) & 0x0000007f ) >> 0)
+#define GET_MTX_RESPFRM_RATE_EXCEPTION (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_EXCEPTION)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RESPFRM_RATE_00 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_00)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RESPFRM_RATE_01 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_01)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RESPFRM_RATE_02 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_02)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RESPFRM_RATE_03 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_03)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RESPFRM_RATE_11 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_11)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RESPFRM_RATE_12 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_12)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RESPFRM_RATE_13 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_13)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RESPFRM_RATE_90_B0 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_90_B0)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RESPFRM_RATE_91_B1 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_91_B1)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RESPFRM_RATE_92_B2 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_92_B2)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RESPFRM_RATE_93_B3 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_93_B3)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RESPFRM_RATE_94_B4 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_94_B4)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RESPFRM_RATE_95_B5 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_95_B5)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RESPFRM_RATE_96_B6 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_96_B6)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RESPFRM_RATE_97_B7 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_97_B7)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RESPFRM_RATE_C0_E0 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_C0_E0)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RESPFRM_RATE_C1_E1 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_C1_E1)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RESPFRM_RATE_C2_E2 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_C2_E2)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RESPFRM_RATE_C3_E3 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_C3_E3)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RESPFRM_RATE_C4_E4 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_C4_E4)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RESPFRM_RATE_C5_E5 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_C5_E5)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RESPFRM_RATE_C6_E6 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_C6_E6)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RESPFRM_RATE_C7_E7 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_C7_E7)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RESPFRM_RATE_D0_F0 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_D0_F0)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RESPFRM_RATE_D1_F1 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_D1_F1)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RESPFRM_RATE_D2_F2 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_D2_F2)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RESPFRM_RATE_D3_F3 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_D3_F3)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RESPFRM_RATE_D4_F4 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_D4_F4)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RESPFRM_RATE_D5_F5 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_D5_F5)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RESPFRM_RATE_D6_F6 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_D6_F6)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RESPFRM_RATE_D7_F7 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_D7_F7)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RESPFRM_RATE_D8_F8 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_D8_F8)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RESPFRM_RATE_D9_F9 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_D9_F9)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RESPFRM_RATE_DA_FA (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_DA_FA)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RESPFRM_RATE_DB_FB (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_DB_FB)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RESPFRM_RATE_DC_FC (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_DC_FC)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RESPFRM_RATE_DD_FD (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_DD_FD)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RESPFRM_RATE_DE_FE (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_DE_FE)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RESPFRM_RATE_DF_FF (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_DF_FF)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RESPFRM_INFO_EXCEPTION (((REG32(ADR_MTX_RESPFRM_INFO_TABLE_EXCEPTION)) & 0x001fffff ) >> 0)
+#define GET_MTX_RESPFRM_INFO_00 (((REG32(ADR_MTX_RESPFRM_INFO_00)) & 0x001fffff ) >> 0)
+#define GET_MTX_RESPFRM_INFO_01 (((REG32(ADR_MTX_RESPFRM_INFO_01)) & 0x001fffff ) >> 0)
+#define GET_MTX_RESPFRM_INFO_02 (((REG32(ADR_MTX_RESPFRM_INFO_02)) & 0x001fffff ) >> 0)
+#define GET_MTX_RESPFRM_INFO_03 (((REG32(ADR_MTX_RESPFRM_INFO_03)) & 0x001fffff ) >> 0)
+#define GET_MTX_RESPFRM_INFO_11 (((REG32(ADR_MTX_RESPFRM_INFO_11)) & 0x001fffff ) >> 0)
+#define GET_MTX_RESPFRM_INFO_12 (((REG32(ADR_MTX_RESPFRM_INFO_12)) & 0x001fffff ) >> 0)
+#define GET_MTX_RESPFRM_INFO_13 (((REG32(ADR_MTX_RESPFRM_INFO_13)) & 0x001fffff ) >> 0)
+#define GET_MTX_RESPFRM_INFO_90_B0 (((REG32(ADR_MTX_RESPFRM_INFO_90_B0)) & 0x001fffff ) >> 0)
+#define GET_MTX_RESPFRM_INFO_91_B1 (((REG32(ADR_MTX_RESPFRM_INFO_91_B1)) & 0x001fffff ) >> 0)
+#define GET_MTX_RESPFRM_INFO_92_B2 (((REG32(ADR_MTX_RESPFRM_INFO_92_B2)) & 0x001fffff ) >> 0)
+#define GET_MTX_RESPFRM_INFO_93_B3 (((REG32(ADR_MTX_RESPFRM_INFO_93_B3)) & 0x001fffff ) >> 0)
+#define GET_MTX_RESPFRM_INFO_94_B4 (((REG32(ADR_MTX_RESPFRM_INFO_94_B4)) & 0x001fffff ) >> 0)
+#define GET_MTX_RESPFRM_INFO_95_B5 (((REG32(ADR_MTX_RESPFRM_INFO_95_B5)) & 0x001fffff ) >> 0)
+#define GET_MTX_RESPFRM_INFO_96_B6 (((REG32(ADR_MTX_RESPFRM_INFO_96_B6)) & 0x001fffff ) >> 0)
+#define GET_MTX_RESPFRM_INFO_97_B7 (((REG32(ADR_MTX_RESPFRM_INFO_97_B7)) & 0x001fffff ) >> 0)
+#define GET_MTX_RESPFRM_INFO_C0 (((REG32(ADR_MTX_RESPFRM_INFO_C0)) & 0x001fffff ) >> 0)
+#define GET_MTX_RESPFRM_INFO_C1 (((REG32(ADR_MTX_RESPFRM_INFO_C1)) & 0x001fffff ) >> 0)
+#define GET_MTX_RESPFRM_INFO_C2 (((REG32(ADR_MTX_RESPFRM_INFO_C2)) & 0x001fffff ) >> 0)
+#define GET_MTX_RESPFRM_INFO_C3 (((REG32(ADR_MTX_RESPFRM_INFO_C3)) & 0x001fffff ) >> 0)
+#define GET_MTX_RESPFRM_INFO_C4 (((REG32(ADR_MTX_RESPFRM_INFO_C4)) & 0x001fffff ) >> 0)
+#define GET_MTX_RESPFRM_INFO_C5 (((REG32(ADR_MTX_RESPFRM_INFO_C5)) & 0x001fffff ) >> 0)
+#define GET_MTX_RESPFRM_INFO_C6 (((REG32(ADR_MTX_RESPFRM_INFO_C6)) & 0x001fffff ) >> 0)
+#define GET_MTX_RESPFRM_INFO_C7 (((REG32(ADR_MTX_RESPFRM_INFO_C7)) & 0x001fffff ) >> 0)
+#define GET_MTX_RESPFRM_INFO_D0 (((REG32(ADR_MTX_RESPFRM_INFO_D0)) & 0x001fffff ) >> 0)
+#define GET_MTX_RESPFRM_INFO_D1 (((REG32(ADR_MTX_RESPFRM_INFO_D1)) & 0x001fffff ) >> 0)
+#define GET_MTX_RESPFRM_INFO_D2 (((REG32(ADR_MTX_RESPFRM_INFO_D2)) & 0x001fffff ) >> 0)
+#define GET_MTX_RESPFRM_INFO_D3 (((REG32(ADR_MTX_RESPFRM_INFO_D3)) & 0x001fffff ) >> 0)
+#define GET_MTX_RESPFRM_INFO_D4 (((REG32(ADR_MTX_RESPFRM_INFO_D4)) & 0x001fffff ) >> 0)
+#define GET_MTX_RESPFRM_INFO_D5 (((REG32(ADR_MTX_RESPFRM_INFO_D5)) & 0x001fffff ) >> 0)
+#define GET_MTX_RESPFRM_INFO_D6 (((REG32(ADR_MTX_RESPFRM_INFO_D6)) & 0x001fffff ) >> 0)
+#define GET_MTX_RESPFRM_INFO_D7 (((REG32(ADR_MTX_RESPFRM_INFO_D7)) & 0x001fffff ) >> 0)
+#define GET_MTX_RESPFRM_INFO_D8 (((REG32(ADR_MTX_RESPFRM_INFO_D8)) & 0x001fffff ) >> 0)
+#define GET_MTX_RESPFRM_INFO_D9 (((REG32(ADR_MTX_RESPFRM_INFO_D9)) & 0x001fffff ) >> 0)
+#define GET_MTX_RESPFRM_INFO_DA (((REG32(ADR_MTX_RESPFRM_INFO_DA)) & 0x001fffff ) >> 0)
+#define GET_MTX_RESPFRM_INFO_DB (((REG32(ADR_MTX_RESPFRM_INFO_DB)) & 0x001fffff ) >> 0)
+#define GET_MTX_RESPFRM_INFO_DC (((REG32(ADR_MTX_RESPFRM_INFO_DC)) & 0x001fffff ) >> 0)
+#define GET_MTX_RESPFRM_INFO_DD (((REG32(ADR_MTX_RESPFRM_INFO_DD)) & 0x001fffff ) >> 0)
+#define GET_MTX_RESPFRM_INFO_DE (((REG32(ADR_MTX_RESPFRM_INFO_DE)) & 0x001fffff ) >> 0)
+#define GET_MTX_RESPFRM_INFO_DF (((REG32(ADR_MTX_RESPFRM_INFO_DF)) & 0x001fffff ) >> 0)
+#define GET_VALID0 (((REG32(ADR_WSID0)) & 0x00000001 ) >> 0)
+#define GET_PEER_QOS_EN0 (((REG32(ADR_WSID0)) & 0x00000002 ) >> 1)
+#define GET_PEER_OP_MODE0 (((REG32(ADR_WSID0)) & 0x0000000c ) >> 2)
+#define GET_PEER_HT_MODE0 (((REG32(ADR_WSID0)) & 0x00000030 ) >> 4)
+#define GET_PEER_MAC0_31_0 (((REG32(ADR_PEER_MAC0_0)) & 0xffffffff ) >> 0)
+#define GET_PEER_MAC0_47_32 (((REG32(ADR_PEER_MAC0_1)) & 0x0000ffff ) >> 0)
+#define GET_TX_ACK_POLICY_0_0 (((REG32(ADR_TX_ACK_POLICY_0_0)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_0 (((REG32(ADR_TX_SEQ_CTRL_0_0)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_0_1 (((REG32(ADR_TX_ACK_POLICY_0_1)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_1 (((REG32(ADR_TX_SEQ_CTRL_0_1)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_0_2 (((REG32(ADR_TX_ACK_POLICY_0_2)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_2 (((REG32(ADR_TX_SEQ_CTRL_0_2)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_0_3 (((REG32(ADR_TX_ACK_POLICY_0_3)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_3 (((REG32(ADR_TX_SEQ_CTRL_0_3)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_0_4 (((REG32(ADR_TX_ACK_POLICY_0_4)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_4 (((REG32(ADR_TX_SEQ_CTRL_0_4)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_0_5 (((REG32(ADR_TX_ACK_POLICY_0_5)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_5 (((REG32(ADR_TX_SEQ_CTRL_0_5)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_0_6 (((REG32(ADR_TX_ACK_POLICY_0_6)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_6 (((REG32(ADR_TX_SEQ_CTRL_0_6)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_0_7 (((REG32(ADR_TX_ACK_POLICY_0_7)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_7 (((REG32(ADR_TX_SEQ_CTRL_0_7)) & 0x00000fff ) >> 0)
+#define GET_VALID1 (((REG32(ADR_WSID1)) & 0x00000001 ) >> 0)
+#define GET_PEER_QOS_EN1 (((REG32(ADR_WSID1)) & 0x00000002 ) >> 1)
+#define GET_PEER_OP_MODE1 (((REG32(ADR_WSID1)) & 0x0000000c ) >> 2)
+#define GET_PEER_HT_MODE1 (((REG32(ADR_WSID1)) & 0x00000030 ) >> 4)
+#define GET_PEER_MAC1_31_0 (((REG32(ADR_PEER_MAC1_0)) & 0xffffffff ) >> 0)
+#define GET_PEER_MAC1_47_32 (((REG32(ADR_PEER_MAC1_1)) & 0x0000ffff ) >> 0)
+#define GET_TX_ACK_POLICY_1_0 (((REG32(ADR_TX_ACK_POLICY_1_0)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_0 (((REG32(ADR_TX_SEQ_CTRL_1_0)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_1_1 (((REG32(ADR_TX_ACK_POLICY_1_1)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_1 (((REG32(ADR_TX_SEQ_CTRL_1_1)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_1_2 (((REG32(ADR_TX_ACK_POLICY_1_2)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_2 (((REG32(ADR_TX_SEQ_CTRL_1_2)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_1_3 (((REG32(ADR_TX_ACK_POLICY_1_3)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_3 (((REG32(ADR_TX_SEQ_CTRL_1_3)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_1_4 (((REG32(ADR_TX_ACK_POLICY_1_4)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_4 (((REG32(ADR_TX_SEQ_CTRL_1_4)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_1_5 (((REG32(ADR_TX_ACK_POLICY_1_5)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_5 (((REG32(ADR_TX_SEQ_CTRL_1_5)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_1_6 (((REG32(ADR_TX_ACK_POLICY_1_6)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_6 (((REG32(ADR_TX_SEQ_CTRL_1_6)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_1_7 (((REG32(ADR_TX_ACK_POLICY_1_7)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_7 (((REG32(ADR_TX_SEQ_CTRL_1_7)) & 0x00000fff ) >> 0)
+#define GET_CH1_PRI (((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0x00000003 ) >> 0)
+#define GET_CH2_PRI (((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0x00000300 ) >> 8)
+#define GET_CH3_PRI (((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0x00030000 ) >> 16)
+#define GET_RG_MAC_LPBK (((REG32(ADR_MAC_MODE)) & 0x00000001 ) >> 0)
+#define GET_RG_MAC_M2M (((REG32(ADR_MAC_MODE)) & 0x00000002 ) >> 1)
+#define GET_RG_PHY_LPBK (((REG32(ADR_MAC_MODE)) & 0x00000004 ) >> 2)
+#define GET_RG_LPBK_RX_EN (((REG32(ADR_MAC_MODE)) & 0x00000008 ) >> 3)
+#define GET_EXT_MAC_MODE (((REG32(ADR_MAC_MODE)) & 0x00000010 ) >> 4)
+#define GET_EXT_PHY_MODE (((REG32(ADR_MAC_MODE)) & 0x00000020 ) >> 5)
+#define GET_HCI_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000001 ) >> 0)
+#define GET_CO_PROC_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000002 ) >> 1)
+#define GET_MTX_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000004 ) >> 2)
+#define GET_MTX_MISC_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000008 ) >> 3)
+#define GET_MTX_QUE_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000010 ) >> 4)
+#define GET_MTX_CHST_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000020 ) >> 5)
+#define GET_MTX_BCN_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000040 ) >> 6)
+#define GET_MRX_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000080 ) >> 7)
+#define GET_AMPDU_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000100 ) >> 8)
+#define GET_MMU_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000200 ) >> 9)
+#define GET_ID_MNG_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000800 ) >> 11)
+#define GET_MBOX_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00001000 ) >> 12)
+#define GET_SCRT_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00002000 ) >> 13)
+#define GET_MIC_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00004000 ) >> 14)
+#define GET_CO_PROC_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000002 ) >> 1)
+#define GET_MTX_MISC_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000008 ) >> 3)
+#define GET_MTX_QUE_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000010 ) >> 4)
+#define GET_MTX_CHST_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000020 ) >> 5)
+#define GET_MTX_BCN_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000040 ) >> 6)
+#define GET_MRX_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000080 ) >> 7)
+#define GET_AMPDU_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000100 ) >> 8)
+#define GET_ID_MNG_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00004000 ) >> 14)
+#define GET_MBOX_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00008000 ) >> 15)
+#define GET_SCRT_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00010000 ) >> 16)
+#define GET_MIC_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00020000 ) >> 17)
+#define GET_CO_PROC_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000002 ) >> 1)
+#define GET_MTX_MISC_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000008 ) >> 3)
+#define GET_MTX_QUE0_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000010 ) >> 4)
+#define GET_MTX_QUE1_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000020 ) >> 5)
+#define GET_MTX_QUE2_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000040 ) >> 6)
+#define GET_MTX_QUE3_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000080 ) >> 7)
+#define GET_MTX_QUE4_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000100 ) >> 8)
+#define GET_MTX_QUE5_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000200 ) >> 9)
+#define GET_MRX_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000400 ) >> 10)
+#define GET_AMPDU_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000800 ) >> 11)
+#define GET_SCRT_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00002000 ) >> 13)
+#define GET_ID_MNG_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00004000 ) >> 14)
+#define GET_MBOX_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00008000 ) >> 15)
+#define GET_HCI_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000001 ) >> 0)
+#define GET_CO_PROC_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000002 ) >> 1)
+#define GET_MTX_MISC_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000008 ) >> 3)
+#define GET_MTX_QUE_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000010 ) >> 4)
+#define GET_MRX_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000020 ) >> 5)
+#define GET_AMPDU_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000040 ) >> 6)
+#define GET_MMU_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000080 ) >> 7)
+#define GET_ID_MNG_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000200 ) >> 9)
+#define GET_MBOX_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000400 ) >> 10)
+#define GET_SCRT_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000800 ) >> 11)
+#define GET_MIC_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00001000 ) >> 12)
+#define GET_MIB_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00002000 ) >> 13)
+#define GET_HCI_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000001 ) >> 0)
+#define GET_CO_PROC_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000002 ) >> 1)
+#define GET_MTX_MISC_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000008 ) >> 3)
+#define GET_MTX_QUE_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000010 ) >> 4)
+#define GET_MRX_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000020 ) >> 5)
+#define GET_AMPDU_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000040 ) >> 6)
+#define GET_ID_MNG_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00001000 ) >> 12)
+#define GET_MBOX_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00002000 ) >> 13)
+#define GET_SCRT_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00004000 ) >> 14)
+#define GET_MIC_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00008000 ) >> 15)
+#define GET_CO_PROC_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00000002 ) >> 1)
+#define GET_MRX_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00000400 ) >> 10)
+#define GET_AMPDU_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00000800 ) >> 11)
+#define GET_SCRT_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00002000 ) >> 13)
+#define GET_ID_MNG_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00004000 ) >> 14)
+#define GET_MBOX_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00008000 ) >> 15)
+#define GET_OP_MODE (((REG32(ADR_GLBLE_SET)) & 0x00000003 ) >> 0)
+#define GET_HT_MODE (((REG32(ADR_GLBLE_SET)) & 0x0000000c ) >> 2)
+#define GET_QOS_EN (((REG32(ADR_GLBLE_SET)) & 0x00000010 ) >> 4)
+#define GET_PB_OFFSET (((REG32(ADR_GLBLE_SET)) & 0x0000ff00 ) >> 8)
+#define GET_SNIFFER_MODE (((REG32(ADR_GLBLE_SET)) & 0x00010000 ) >> 16)
+#define GET_DUP_FLT (((REG32(ADR_GLBLE_SET)) & 0x00020000 ) >> 17)
+#define GET_TX_PKT_RSVD (((REG32(ADR_GLBLE_SET)) & 0x001c0000 ) >> 18)
+#define GET_AMPDU_SNIFFER (((REG32(ADR_GLBLE_SET)) & 0x00200000 ) >> 21)
+#define GET_CCMP_H_SEL (((REG32(ADR_GLBLE_SET)) & 0x00400000 ) >> 22)
+#define GET_LUT_SEL_V2 (((REG32(ADR_GLBLE_SET)) & 0x00800000 ) >> 23)
+#define GET_REASON_TRAP0 (((REG32(ADR_REASON_TRAP0)) & 0xffffffff ) >> 0)
+#define GET_REASON_TRAP1 (((REG32(ADR_REASON_TRAP1)) & 0xffffffff ) >> 0)
+#define GET_BSSID_31_0 (((REG32(ADR_BSSID_0)) & 0xffffffff ) >> 0)
+#define GET_BSSID_47_32 (((REG32(ADR_BSSID_1)) & 0x0000ffff ) >> 0)
+#define GET_STA_MAC_31_0 (((REG32(ADR_STA_MAC_0)) & 0xffffffff ) >> 0)
+#define GET_STA_MAC_47_32 (((REG32(ADR_STA_MAC_1)) & 0x0000ffff ) >> 0)
+#define GET_PAIR_SCRT (((REG32(ADR_SCRT_SET)) & 0x00000007 ) >> 0)
+#define GET_GRP_SCRT (((REG32(ADR_SCRT_SET)) & 0x00000038 ) >> 3)
+#define GET_SCRT_PKT_ID (((REG32(ADR_SCRT_SET)) & 0x00001fc0 ) >> 6)
+#define GET_SCRT_RPLY_IGNORE (((REG32(ADR_SCRT_SET)) & 0x00010000 ) >> 16)
+#define GET_SCRT_STATE (((REG32(ADR_SCRT_STATE)) & 0x0000000f ) >> 0)
+#define GET_BSSID1_31_0 (((REG32(ADR_BSSID1_0)) & 0xffffffff ) >> 0)
+#define GET_BSSID1_47_32 (((REG32(ADR_BSSID1_1)) & 0x0000ffff ) >> 0)
+#define GET_STA_MAC1_31_0 (((REG32(ADR_STA_MAC1_0)) & 0xffffffff ) >> 0)
+#define GET_STA_MAC1_47_32 (((REG32(ADR_STA_MAC1_1)) & 0x0000ffff ) >> 0)
+#define GET_OP_MODE1 (((REG32(ADR_OP_MODE1)) & 0x00000003 ) >> 0)
+#define GET_COEXIST_EN (((REG32(ADR_BTCX0)) & 0x00000001 ) >> 0)
+#define GET_WIRE_MODE (((REG32(ADR_BTCX0)) & 0x0000000e ) >> 1)
+#define GET_WL_RX_PRI (((REG32(ADR_BTCX0)) & 0x00000010 ) >> 4)
+#define GET_WL_TX_PRI (((REG32(ADR_BTCX0)) & 0x00000020 ) >> 5)
+#define GET_GURAN_USE_EN (((REG32(ADR_BTCX0)) & 0x00000100 ) >> 8)
+#define GET_GURAN_USE_CTRL (((REG32(ADR_BTCX0)) & 0x00000200 ) >> 9)
+#define GET_BEACON_TIMEOUT_EN (((REG32(ADR_BTCX0)) & 0x00000400 ) >> 10)
+#define GET_WLAN_ACT_POL (((REG32(ADR_BTCX0)) & 0x00000800 ) >> 11)
+#define GET_DUAL_ANT_EN (((REG32(ADR_BTCX0)) & 0x00001000 ) >> 12)
+#define GET_TRSW_PHY_POL (((REG32(ADR_BTCX0)) & 0x00010000 ) >> 16)
+#define GET_WIFI_TX_SW_POL (((REG32(ADR_BTCX0)) & 0x00020000 ) >> 17)
+#define GET_WIFI_RX_SW_POL (((REG32(ADR_BTCX0)) & 0x00040000 ) >> 18)
+#define GET_BT_SW_POL (((REG32(ADR_BTCX0)) & 0x00080000 ) >> 19)
+#define GET_BT_PRI_SMP_TIME (((REG32(ADR_BTCX1)) & 0x000000ff ) >> 0)
+#define GET_BT_STA_SMP_TIME (((REG32(ADR_BTCX1)) & 0x0000ff00 ) >> 8)
+#define GET_BEACON_TIMEOUT (((REG32(ADR_BTCX1)) & 0x00ff0000 ) >> 16)
+#define GET_WLAN_REMAIN_TIME (((REG32(ADR_BTCX1)) & 0xff000000 ) >> 24)
+#define GET_SW_MANUAL_EN (((REG32(ADR_SWITCH_CTL)) & 0x00000001 ) >> 0)
+#define GET_SW_WL_TX (((REG32(ADR_SWITCH_CTL)) & 0x00000002 ) >> 1)
+#define GET_SW_WL_RX (((REG32(ADR_SWITCH_CTL)) & 0x00000004 ) >> 2)
+#define GET_SW_BT_TRX (((REG32(ADR_SWITCH_CTL)) & 0x00000008 ) >> 3)
+#define GET_BT_TXBAR_MANUAL_EN (((REG32(ADR_SWITCH_CTL)) & 0x00000010 ) >> 4)
+#define GET_BT_TXBAR_SET (((REG32(ADR_SWITCH_CTL)) & 0x00000020 ) >> 5)
+#define GET_BT_BUSY_MANUAL_EN (((REG32(ADR_SWITCH_CTL)) & 0x00000100 ) >> 8)
+#define GET_BT_BUSY_SET (((REG32(ADR_SWITCH_CTL)) & 0x00000200 ) >> 9)
+#define GET_SWITCH_2WIRE_EN (((REG32(ADR_SWITCH_CTL)) & 0x00000400 ) >> 10)
+#define GET_RANDOM_SEED3 (((REG32(ADR_RANDOM_CTL)) & 0x000000ff ) >> 0)
+#define GET_RANDOM_SEED2 (((REG32(ADR_RANDOM_CTL)) & 0x0000ff00 ) >> 8)
+#define GET_RANDOM_SEED1 (((REG32(ADR_RANDOM_CTL)) & 0x00ff0000 ) >> 16)
+#define GET_BT_TRX_SMP_TIME (((REG32(ADR_RANDOM_CTL)) & 0xff000000 ) >> 24)
+#define GET_BTCX_INT_MASK (((REG32(ADR_BTCX_MISC_CTL)) & 0x0000001f ) >> 0)
+#define GET_BTCX_INTR (((REG32(ADR_BTCX_MISC_CTL)) & 0x00000020 ) >> 5)
+#define GET_AUTO_REMAIN (((REG32(ADR_BTCX_MISC_CTL)) & 0x00000040 ) >> 6)
+#define GET_PREDE_BT_TX (((REG32(ADR_BTCX_MISC_CTL)) & 0x00000080 ) >> 7)
+#define GET_G0_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000004 ) >> 2)
+#define GET_G0_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000008 ) >> 3)
+#define GET_G1_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000010 ) >> 4)
+#define GET_G1_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000020 ) >> 5)
+#define GET_Q0_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000040 ) >> 6)
+#define GET_Q0_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000080 ) >> 7)
+#define GET_Q1_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000100 ) >> 8)
+#define GET_Q1_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000200 ) >> 9)
+#define GET_Q2_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000400 ) >> 10)
+#define GET_Q2_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000800 ) >> 11)
+#define GET_Q3_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00001000 ) >> 12)
+#define GET_Q3_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00002000 ) >> 13)
+#define GET_SCRT_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00004000 ) >> 14)
+#define GET_SCRT_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00008000 ) >> 15)
+#define GET_MISC_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00010000 ) >> 16)
+#define GET_MISC_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00020000 ) >> 17)
+#define GET_MTX_WSID0_SUCC (((REG32(ADR_MTX_WSID0_SUCC)) & 0x0000ffff ) >> 0)
+#define GET_MTX_WSID0_FRM (((REG32(ADR_MTX_WSID0_FRM)) & 0x0000ffff ) >> 0)
+#define GET_MTX_WSID0_RETRY (((REG32(ADR_MTX_WSID0_RETRY)) & 0x0000ffff ) >> 0)
+#define GET_MTX_WSID0_TOTAL (((REG32(ADR_MTX_WSID0_TOTAL)) & 0x0000ffff ) >> 0)
+#define GET_MTX_GRP (((REG32(ADR_MTX_GROUP)) & 0x000fffff ) >> 0)
+#define GET_MTX_FAIL (((REG32(ADR_MTX_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RETRY (((REG32(ADR_MTX_RETRY)) & 0x000fffff ) >> 0)
+#define GET_MTX_MULTI_RETRY (((REG32(ADR_MTX_MULTI_RETRY)) & 0x000fffff ) >> 0)
+#define GET_MTX_RTS_SUCC (((REG32(ADR_MTX_RTS_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RTS_FAIL (((REG32(ADR_MTX_RTS_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_MTX_ACK_FAIL (((REG32(ADR_MTX_ACK_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_MTX_FRM (((REG32(ADR_MTX_FRM)) & 0x000fffff ) >> 0)
+#define GET_MTX_ACK_TX (((REG32(ADR_MTX_ACK_TX)) & 0x0000ffff ) >> 0)
+#define GET_MTX_CTS_TX (((REG32(ADR_MTX_CTS_TX)) & 0x0000ffff ) >> 0)
+#define GET_MRX_DUP (((REG32(ADR_MRX_DUP_FRM)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FRG (((REG32(ADR_MRX_FRG_FRM)) & 0x000fffff ) >> 0)
+#define GET_MRX_GRP (((REG32(ADR_MRX_GROUP_FRM)) & 0x000fffff ) >> 0)
+#define GET_MRX_FCS_ERR (((REG32(ADR_MRX_FCS_ERR)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FCS_SUC (((REG32(ADR_MRX_FCS_SUCC)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MISS (((REG32(ADR_MRX_MISS)) & 0x0000ffff ) >> 0)
+#define GET_MRX_ALC_FAIL (((REG32(ADR_MRX_ALC_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_MRX_DAT_NTF (((REG32(ADR_MRX_DAT_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_RTS_NTF (((REG32(ADR_MRX_RTS_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_CTS_NTF (((REG32(ADR_MRX_CTS_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_ACK_NTF (((REG32(ADR_MRX_ACK_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_BA_NTF (((REG32(ADR_MRX_BA_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_DATA_NTF (((REG32(ADR_MRX_DATA_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MNG_NTF (((REG32(ADR_MRX_MNG_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_DAT_CRC_NTF (((REG32(ADR_MRX_DAT_CRC_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_BAR_NTF (((REG32(ADR_MRX_BAR_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MB_MISS (((REG32(ADR_MRX_MB_MISS)) & 0x0000ffff ) >> 0)
+#define GET_MRX_NIDLE_MISS (((REG32(ADR_MRX_NIDLE_MISS)) & 0x0000ffff ) >> 0)
+#define GET_MRX_CSR_NTF (((REG32(ADR_MRX_CSR_NTF)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q0_SUCC (((REG32(ADR_DBG_Q0_FRM_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q0_FAIL (((REG32(ADR_DBG_Q0_FRM_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q0_ACK_SUCC (((REG32(ADR_DBG_Q0_ACK_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q0_ACK_FAIL (((REG32(ADR_DBG_Q0_ACK_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q1_SUCC (((REG32(ADR_DBG_Q1_FRM_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q1_FAIL (((REG32(ADR_DBG_Q1_FRM_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q1_ACK_SUCC (((REG32(ADR_DBG_Q1_ACK_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q1_ACK_FAIL (((REG32(ADR_DBG_Q1_ACK_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q2_SUCC (((REG32(ADR_DBG_Q2_FRM_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q2_FAIL (((REG32(ADR_DBG_Q2_FRM_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q2_ACK_SUCC (((REG32(ADR_DBG_Q2_ACK_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q2_ACK_FAIL (((REG32(ADR_DBG_Q2_ACK_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q3_SUCC (((REG32(ADR_DBG_Q3_FRM_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q3_FAIL (((REG32(ADR_DBG_Q3_FRM_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q3_ACK_SUCC (((REG32(ADR_DBG_Q3_ACK_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q3_ACK_FAIL (((REG32(ADR_DBG_Q3_ACK_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_SCRT_TKIP_CERR (((REG32(ADR_MIB_SCRT_TKIP0)) & 0x000fffff ) >> 0)
+#define GET_SCRT_TKIP_MIC_ERR (((REG32(ADR_MIB_SCRT_TKIP1)) & 0x000fffff ) >> 0)
+#define GET_SCRT_TKIP_RPLY (((REG32(ADR_MIB_SCRT_TKIP2)) & 0x000fffff ) >> 0)
+#define GET_SCRT_CCMP_RPLY (((REG32(ADR_MIB_SCRT_CCMP0)) & 0x000fffff ) >> 0)
+#define GET_SCRT_CCMP_CERR (((REG32(ADR_MIB_SCRT_CCMP1)) & 0x000fffff ) >> 0)
+#define GET_DBG_LEN_CRC_FAIL (((REG32(ADR_DBG_LEN_CRC_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_LEN_ALC_FAIL (((REG32(ADR_DBG_LEN_ALC_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_AMPDU_PASS (((REG32(ADR_DBG_AMPDU_PASS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_AMPDU_FAIL (((REG32(ADR_DBG_AMPDU_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_RXID_ALC_CNT_FAIL (((REG32(ADR_ID_ALC_FAIL1)) & 0x0000ffff ) >> 0)
+#define GET_RXID_ALC_LEN_FAIL (((REG32(ADR_ID_ALC_FAIL2)) & 0x0000ffff ) >> 0)
+#define GET_VALID2 (((REG32(ADR_WSID2)) & 0x00000001 ) >> 0)
+#define GET_PEER_QOS_EN2 (((REG32(ADR_WSID2)) & 0x00000002 ) >> 1)
+#define GET_PEER_OP_MODE2 (((REG32(ADR_WSID2)) & 0x0000000c ) >> 2)
+#define GET_PEER_HT_MODE2 (((REG32(ADR_WSID2)) & 0x00000030 ) >> 4)
+#define GET_PEER_MAC2_31_0 (((REG32(ADR_PEER_MAC2_0)) & 0xffffffff ) >> 0)
+#define GET_PEER_MAC2_47_32 (((REG32(ADR_PEER_MAC2_1)) & 0x0000ffff ) >> 0)
+#define GET_TX_ACK_POLICY_2_0 (((REG32(ADR_TX_ACK_POLICY_2_0)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_2_0 (((REG32(ADR_TX_SEQ_CTRL_2_0)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_2_1 (((REG32(ADR_TX_ACK_POLICY_2_1)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_2_1 (((REG32(ADR_TX_SEQ_CTRL_2_1)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_2_2 (((REG32(ADR_TX_ACK_POLICY_2_2)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_2_2 (((REG32(ADR_TX_SEQ_CTRL_2_2)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_2_3 (((REG32(ADR_TX_ACK_POLICY_2_3)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_2_3 (((REG32(ADR_TX_SEQ_CTRL_2_3)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_2_4 (((REG32(ADR_TX_ACK_POLICY_2_4)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_2_4 (((REG32(ADR_TX_SEQ_CTRL_2_4)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_2_5 (((REG32(ADR_TX_ACK_POLICY_2_5)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_2_5 (((REG32(ADR_TX_SEQ_CTRL_2_5)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_2_6 (((REG32(ADR_TX_ACK_POLICY_2_6)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_2_6 (((REG32(ADR_TX_SEQ_CTRL_2_6)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_2_7 (((REG32(ADR_TX_ACK_POLICY_2_7)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_2_7 (((REG32(ADR_TX_SEQ_CTRL_2_7)) & 0x00000fff ) >> 0)
+#define GET_VALID3 (((REG32(ADR_WSID3)) & 0x00000001 ) >> 0)
+#define GET_PEER_QOS_EN3 (((REG32(ADR_WSID3)) & 0x00000002 ) >> 1)
+#define GET_PEER_OP_MODE3 (((REG32(ADR_WSID3)) & 0x0000000c ) >> 2)
+#define GET_PEER_HT_MODE3 (((REG32(ADR_WSID3)) & 0x00000030 ) >> 4)
+#define GET_PEER_MAC3_31_0 (((REG32(ADR_PEER_MAC3_0)) & 0xffffffff ) >> 0)
+#define GET_PEER_MAC3_47_32 (((REG32(ADR_PEER_MAC3_1)) & 0x0000ffff ) >> 0)
+#define GET_TX_ACK_POLICY_3_0 (((REG32(ADR_TX_ACK_POLICY_3_0)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_3_0 (((REG32(ADR_TX_SEQ_CTRL_3_0)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_3_1 (((REG32(ADR_TX_ACK_POLICY_3_1)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_3_1 (((REG32(ADR_TX_SEQ_CTRL_3_1)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_3_2 (((REG32(ADR_TX_ACK_POLICY_3_2)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_3_2 (((REG32(ADR_TX_SEQ_CTRL_3_2)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_3_3 (((REG32(ADR_TX_ACK_POLICY_3_3)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_3_3 (((REG32(ADR_TX_SEQ_CTRL_3_3)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_3_4 (((REG32(ADR_TX_ACK_POLICY_3_4)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_3_4 (((REG32(ADR_TX_SEQ_CTRL_3_4)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_3_5 (((REG32(ADR_TX_ACK_POLICY_3_5)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_3_5 (((REG32(ADR_TX_SEQ_CTRL_3_5)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_3_6 (((REG32(ADR_TX_ACK_POLICY_3_6)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_3_6 (((REG32(ADR_TX_SEQ_CTRL_3_6)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_3_7 (((REG32(ADR_TX_ACK_POLICY_3_7)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_3_7 (((REG32(ADR_TX_SEQ_CTRL_3_7)) & 0x00000fff ) >> 0)
+#define GET_VALID4 (((REG32(ADR_WSID4)) & 0x00000001 ) >> 0)
+#define GET_PEER_QOS_EN4 (((REG32(ADR_WSID4)) & 0x00000002 ) >> 1)
+#define GET_PEER_OP_MODE4 (((REG32(ADR_WSID4)) & 0x0000000c ) >> 2)
+#define GET_PEER_HT_MODE4 (((REG32(ADR_WSID4)) & 0x00000030 ) >> 4)
+#define GET_PEER_MAC4_31_0 (((REG32(ADR_PEER_MAC4_0)) & 0xffffffff ) >> 0)
+#define GET_PEER_MAC4_47_32 (((REG32(ADR_PEER_MAC4_1)) & 0x0000ffff ) >> 0)
+#define GET_TX_ACK_POLICY_4_0 (((REG32(ADR_TX_ACK_POLICY_4_0)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_4_0 (((REG32(ADR_TX_SEQ_CTRL_4_0)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_4_1 (((REG32(ADR_TX_ACK_POLICY_4_1)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_4_1 (((REG32(ADR_TX_SEQ_CTRL_4_1)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_4_2 (((REG32(ADR_TX_ACK_POLICY_4_2)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_4_2 (((REG32(ADR_TX_SEQ_CTRL_4_2)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_4_3 (((REG32(ADR_TX_ACK_POLICY_4_3)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_4_3 (((REG32(ADR_TX_SEQ_CTRL_4_3)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_4_4 (((REG32(ADR_TX_ACK_POLICY_4_4)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_4_4 (((REG32(ADR_TX_SEQ_CTRL_4_4)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_4_5 (((REG32(ADR_TX_ACK_POLICY_4_5)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_4_5 (((REG32(ADR_TX_SEQ_CTRL_4_5)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_4_6 (((REG32(ADR_TX_ACK_POLICY_4_6)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_4_6 (((REG32(ADR_TX_SEQ_CTRL_4_6)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_4_7 (((REG32(ADR_TX_ACK_POLICY_4_7)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_4_7 (((REG32(ADR_TX_SEQ_CTRL_4_7)) & 0x00000fff ) >> 0)
+#define GET_VALID5 (((REG32(ADR_WSID5)) & 0x00000001 ) >> 0)
+#define GET_PEER_QOS_EN5 (((REG32(ADR_WSID5)) & 0x00000002 ) >> 1)
+#define GET_PEER_OP_MODE5 (((REG32(ADR_WSID5)) & 0x0000000c ) >> 2)
+#define GET_PEER_HT_MODE5 (((REG32(ADR_WSID5)) & 0x00000030 ) >> 4)
+#define GET_PEER_MAC5_31_0 (((REG32(ADR_PEER_MAC5_0)) & 0xffffffff ) >> 0)
+#define GET_PEER_MAC5_47_32 (((REG32(ADR_PEER_MAC5_1)) & 0x0000ffff ) >> 0)
+#define GET_TX_ACK_POLICY_5_0 (((REG32(ADR_TX_ACK_POLICY_5_0)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_5_0 (((REG32(ADR_TX_SEQ_CTRL_5_0)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_5_1 (((REG32(ADR_TX_ACK_POLICY_5_1)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_5_1 (((REG32(ADR_TX_SEQ_CTRL_5_1)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_5_2 (((REG32(ADR_TX_ACK_POLICY_5_2)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_5_2 (((REG32(ADR_TX_SEQ_CTRL_5_2)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_5_3 (((REG32(ADR_TX_ACK_POLICY_5_3)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_5_3 (((REG32(ADR_TX_SEQ_CTRL_5_3)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_5_4 (((REG32(ADR_TX_ACK_POLICY_5_4)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_5_4 (((REG32(ADR_TX_SEQ_CTRL_5_4)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_5_5 (((REG32(ADR_TX_ACK_POLICY_5_5)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_5_5 (((REG32(ADR_TX_SEQ_CTRL_5_5)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_5_6 (((REG32(ADR_TX_ACK_POLICY_5_6)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_5_6 (((REG32(ADR_TX_SEQ_CTRL_5_6)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_5_7 (((REG32(ADR_TX_ACK_POLICY_5_7)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_5_7 (((REG32(ADR_TX_SEQ_CTRL_5_7)) & 0x00000fff ) >> 0)
+#define GET_VALID6 (((REG32(ADR_WSID6)) & 0x00000001 ) >> 0)
+#define GET_PEER_QOS_EN6 (((REG32(ADR_WSID6)) & 0x00000002 ) >> 1)
+#define GET_PEER_OP_MODE6 (((REG32(ADR_WSID6)) & 0x0000000c ) >> 2)
+#define GET_PEER_HT_MODE6 (((REG32(ADR_WSID6)) & 0x00000030 ) >> 4)
+#define GET_PEER_MAC6_31_0 (((REG32(ADR_PEER_MAC6_0)) & 0xffffffff ) >> 0)
+#define GET_PEER_MAC6_47_32 (((REG32(ADR_PEER_MAC6_1)) & 0x0000ffff ) >> 0)
+#define GET_TX_ACK_POLICY_6_0 (((REG32(ADR_TX_ACK_POLICY_6_0)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_6_0 (((REG32(ADR_TX_SEQ_CTRL_6_0)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_6_1 (((REG32(ADR_TX_ACK_POLICY_6_1)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_6_1 (((REG32(ADR_TX_SEQ_CTRL_6_1)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_6_2 (((REG32(ADR_TX_ACK_POLICY_6_2)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_6_2 (((REG32(ADR_TX_SEQ_CTRL_6_2)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_6_3 (((REG32(ADR_TX_ACK_POLICY_6_3)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_6_3 (((REG32(ADR_TX_SEQ_CTRL_6_3)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_6_4 (((REG32(ADR_TX_ACK_POLICY_6_4)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_6_4 (((REG32(ADR_TX_SEQ_CTRL_6_4)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_6_5 (((REG32(ADR_TX_ACK_POLICY_6_5)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_6_5 (((REG32(ADR_TX_SEQ_CTRL_6_5)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_6_6 (((REG32(ADR_TX_ACK_POLICY_6_6)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_6_6 (((REG32(ADR_TX_SEQ_CTRL_6_6)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_6_7 (((REG32(ADR_TX_ACK_POLICY_6_7)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_6_7 (((REG32(ADR_TX_SEQ_CTRL_6_7)) & 0x00000fff ) >> 0)
+#define GET_VALID7 (((REG32(ADR_WSID7)) & 0x00000001 ) >> 0)
+#define GET_PEER_QOS_EN7 (((REG32(ADR_WSID7)) & 0x00000002 ) >> 1)
+#define GET_PEER_OP_MODE7 (((REG32(ADR_WSID7)) & 0x0000000c ) >> 2)
+#define GET_PEER_HT_MODE7 (((REG32(ADR_WSID7)) & 0x00000030 ) >> 4)
+#define GET_PEER_MAC7_31_0 (((REG32(ADR_PEER_MAC7_0)) & 0xffffffff ) >> 0)
+#define GET_PEER_MAC7_47_32 (((REG32(ADR_PEER_MAC7_1)) & 0x0000ffff ) >> 0)
+#define GET_TX_ACK_POLICY_7_0 (((REG32(ADR_TX_ACK_POLICY_7_0)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_7_0 (((REG32(ADR_TX_SEQ_CTRL_7_0)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_7_1 (((REG32(ADR_TX_ACK_POLICY_7_1)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_7_1 (((REG32(ADR_TX_SEQ_CTRL_7_1)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_7_2 (((REG32(ADR_TX_ACK_POLICY_7_2)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_7_2 (((REG32(ADR_TX_SEQ_CTRL_7_2)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_7_3 (((REG32(ADR_TX_ACK_POLICY_7_3)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_7_3 (((REG32(ADR_TX_SEQ_CTRL_7_3)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_7_4 (((REG32(ADR_TX_ACK_POLICY_7_4)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_7_4 (((REG32(ADR_TX_SEQ_CTRL_7_4)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_7_5 (((REG32(ADR_TX_ACK_POLICY_7_5)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_7_5 (((REG32(ADR_TX_SEQ_CTRL_7_5)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_7_6 (((REG32(ADR_TX_ACK_POLICY_7_6)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_7_6 (((REG32(ADR_TX_SEQ_CTRL_7_6)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_7_7 (((REG32(ADR_TX_ACK_POLICY_7_7)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_7_7 (((REG32(ADR_TX_SEQ_CTRL_7_7)) & 0x00000fff ) >> 0)
+#define GET_RG_GEMINIA_HW_PINSEL (((REG32(ADR_GEMINIA_3_WIRE_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_GEMINIA_HS_3WIRE_MANUAL (((REG32(ADR_GEMINIA_3_WIRE_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_RG_GEMINIA_MODE_MANUAL (((REG32(ADR_GEMINIA_3_WIRE_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_RG_GEMINIA_RX_GAIN_MANUAL (((REG32(ADR_GEMINIA_3_WIRE_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_RG_GEMINIA_TX_GAIN_MANUAL (((REG32(ADR_GEMINIA_3_WIRE_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_RG_GEMINIA_TXGAIN_PHYCTRL (((REG32(ADR_GEMINIA_3_WIRE_REGISTER)) & 0x00000020 ) >> 5)
+#define GET_RG_GEMINIA_RX_AGC (((REG32(ADR_GEMINIA_3_WIRE_REGISTER)) & 0x00000040 ) >> 6)
+#define GET_RG_GEMINIA_MODE (((REG32(ADR_GEMINIA_3_WIRE_REGISTER)) & 0x00000700 ) >> 8)
+#define GET_RG_GEMINIA_CAL_INDEX (((REG32(ADR_GEMINIA_3_WIRE_REGISTER)) & 0x00007000 ) >> 12)
+#define GET_RG_GEMINIA_RFG (((REG32(ADR_GEMINIA_3_WIRE_REGISTER)) & 0x00030000 ) >> 16)
+#define GET_RG_GEMINIA_PGAG (((REG32(ADR_GEMINIA_3_WIRE_REGISTER)) & 0x003c0000 ) >> 18)
+#define GET_RG_GEMINIA_TX_GAIN (((REG32(ADR_GEMINIA_3_WIRE_REGISTER)) & 0x7f000000 ) >> 24)
+#define GET_RG_GEMINIA_TX_TRSW_MANUAL (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_GEMINIA_EN_TX_TRSW (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_RG_GEMINIA_RX_LNA_MANUAL (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_RG_GEMINIA_EN_RX_LNA (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_RG_GEMINIA_RX_MIXER_MANUAL (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_RG_GEMINIA_EN_RX_MIXER (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00000020 ) >> 5)
+#define GET_RG_GEMINIA_RX_DIV2_MANUAL (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00000040 ) >> 6)
+#define GET_RG_GEMINIA_EN_RX_DIV2 (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00000080 ) >> 7)
+#define GET_RG_GEMINIA_RX_LOBUF_MANUAL (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00000100 ) >> 8)
+#define GET_RG_GEMINIA_EN_RX_LOBUF (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00000200 ) >> 9)
+#define GET_RG_GEMINIA_RX_TZ_MANUAL (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00000400 ) >> 10)
+#define GET_RG_GEMINIA_EN_RX_TZ (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_RG_GEMINIA_RX_FILTER_MANUAL (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00001000 ) >> 12)
+#define GET_RG_GEMINIA_EN_RX_FILTER (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00002000 ) >> 13)
+#define GET_RG_GEMINIA_RX_ADC_MANUAL (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_RG_GEMINIA_EN_RX_ADC (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00008000 ) >> 15)
+#define GET_RG_GEMINIA_RX_RSSI_MANUAL (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00010000 ) >> 16)
+#define GET_RG_GEMINIA_EN_RX_RSSI (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00020000 ) >> 17)
+#define GET_RG_GEMINIA_TX_PA_MANUAL (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00040000 ) >> 18)
+#define GET_RG_GEMINIA_EN_TX_PA (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00080000 ) >> 19)
+#define GET_RG_GEMINIA_TX_MOD_MANUAL (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00100000 ) >> 20)
+#define GET_RG_GEMINIA_EN_TX_MOD (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00200000 ) >> 21)
+#define GET_RG_GEMINIA_TX_DAC_MANUAL (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00400000 ) >> 22)
+#define GET_RG_GEMINIA_EN_TX_DAC (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00800000 ) >> 23)
+#define GET_RG_GEMINIA_TX_DIV2_MANUAL (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x01000000 ) >> 24)
+#define GET_RG_GEMINIA_EN_TX_DIV2 (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x02000000 ) >> 25)
+#define GET_RG_GEMINIA_TX_DIV2_BUF_MANUAL (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x04000000 ) >> 26)
+#define GET_RG_GEMINIA_EN_TX_DIV2_BUF (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x08000000 ) >> 27)
+#define GET_RG_GEMINIA_TX_BT_PA_MANUAL (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x10000000 ) >> 28)
+#define GET_RG_GEMINIA_EN_TX_BT_PA (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x20000000 ) >> 29)
+#define GET_RG_GEMINIA_EN_LDO_RX_FE (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_GEMINIA_EN_LDO_ABB (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_RG_GEMINIA_EN_LDO_ADC (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_RG_GEMINIA_EN_LDO_DAC (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_RG_GEMINIA_EN_IREF_RX (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_RG_GEMINIA_TX_DAC_CAL_MANUAL (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x00000040 ) >> 6)
+#define GET_RG_GEMINIA_EN_TX_DAC_CAL (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x00000080 ) >> 7)
+#define GET_RG_GEMINIA_RX_TZ_OUT_TRISTATE_MANUAL (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x00000100 ) >> 8)
+#define GET_RG_GEMINIA_RX_TZ_OUT_TRISTATE (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x00000200 ) >> 9)
+#define GET_RG_GEMINIA_TX_SELF_MIXER_MANUAL (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x00000400 ) >> 10)
+#define GET_RG_GEMINIA_EN_TX_SELF_MIXER (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_RG_GEMINIA_RX_IQCAL_MANUAL (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x00001000 ) >> 12)
+#define GET_RG_GEMINIA_EN_RX_IQCAL (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x00002000 ) >> 13)
+#define GET_RG_GEMINIA_TX_DPD_MANUAL (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_RG_GEMINIA_EN_TX_DPD (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x00008000 ) >> 15)
+#define GET_RG_GEMINIA_RXRCCALQ_EN_BYP (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x00010000 ) >> 16)
+#define GET_RG_GEMINIA_EN_TX_TSSI (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x00020000 ) >> 17)
+#define GET_RG_GEMINIA_EN_SARADC (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x00040000 ) >> 18)
+#define GET_RG_GEMINIA_EN_TX_VTOI_2ND (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x00080000 ) >> 19)
+#define GET_RG_GEMINIA_TXLPF_BYPASS (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x00100000 ) >> 20)
+#define GET_RG_GEMINIA_TX_EN_VOLTAGE_IN (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x00200000 ) >> 21)
+#define GET_RG_GEMINIA_EN_TX_DAC_OUT (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x00400000 ) >> 22)
+#define GET_RG_GEMINIA_EN_TX_DAC_VOUT (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x00800000 ) >> 23)
+#define GET_RG_GEMINIA_RX_ABBOUT_TRI_STATE (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x01000000 ) >> 24)
+#define GET_RG_GEMINIA_EN_RX_TESTNODE (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x02000000 ) >> 25)
+#define GET_RG_GEMINIA_EN_RX_PADSW (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x04000000 ) >> 26)
+#define GET_RG_GEMINIA_LDO_RX_FE_EN_BYP (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x08000000 ) >> 27)
+#define GET_RG_GEMINIA_LDO_RX_ABB_EN_BYP (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x10000000 ) >> 28)
+#define GET_RG_GEMINIA_LDO_RX_ADC_EN_BYP (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x20000000 ) >> 29)
+#define GET_RG_GEMINIA_LDO_TX_DAC_EN_BYP (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x40000000 ) >> 30)
+#define GET_RG_GEMINIA_EN_LDO_RX_ADC_IQUP (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x80000000 ) >> 31)
+#define GET_RG_GEMINIA_LDO_LEVEL_RX_FE (((REG32(ADR_GEMINIA_LDO_REGISTER)) & 0x00000007 ) >> 0)
+#define GET_RG_GEMINIA_LDO_LEVEL_ABB (((REG32(ADR_GEMINIA_LDO_REGISTER)) & 0x00000038 ) >> 3)
+#define GET_RG_GEMINIA_LDO_LEVEL_ADC (((REG32(ADR_GEMINIA_LDO_REGISTER)) & 0x000001c0 ) >> 6)
+#define GET_RG_GEMINIA_LDO_LEVEL_DAC (((REG32(ADR_GEMINIA_LDO_REGISTER)) & 0x00000e00 ) >> 9)
+#define GET_RG_GEMINIA_SX_LDO_CP_LEVEL (((REG32(ADR_GEMINIA_LDO_REGISTER)) & 0x00007000 ) >> 12)
+#define GET_RG_GEMINIA_SX_LDO_LO_LEVEL (((REG32(ADR_GEMINIA_LDO_REGISTER)) & 0x00038000 ) >> 15)
+#define GET_RG_GEMINIA_DP_LDO_LEVEL (((REG32(ADR_GEMINIA_LDO_REGISTER)) & 0x00e00000 ) >> 21)
+#define GET_RG_GEMINIA_SX_LDO_VCO_LEVEL (((REG32(ADR_GEMINIA_LDO_REGISTER)) & 0x07000000 ) >> 24)
+#define GET_RG_GEMINIA_SX_LDO_DIV_LEVEL (((REG32(ADR_GEMINIA_LDO_REGISTER)) & 0x38000000 ) >> 27)
+#define GET_RG_GEMINIA_WF_RX_ABBCTUNEI (((REG32(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER)) & 0x0000003f ) >> 0)
+#define GET_RG_GEMINIA_WF_RX_ABBCTUNEQ (((REG32(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER)) & 0x00000fc0 ) >> 6)
+#define GET_RG_GEMINIA_WF_RX_FILTERI_COARSE (((REG32(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER)) & 0x00003000 ) >> 12)
+#define GET_RG_GEMINIA_WF_RX_FILTERI1ST (((REG32(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER)) & 0x0000c000 ) >> 14)
+#define GET_RG_GEMINIA_WF_RX_FILTERI2ND (((REG32(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER)) & 0x00030000 ) >> 16)
+#define GET_RG_GEMINIA_WF_RX_FILTERI3RD (((REG32(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER)) & 0x000c0000 ) >> 18)
+#define GET_RG_GEMINIA_WF_RX_ABBCFIX (((REG32(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER)) & 0x00100000 ) >> 20)
+#define GET_RG_GEMINIA_WF_RX_ABB_N_MODE (((REG32(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER)) & 0x00200000 ) >> 21)
+#define GET_RG_GEMINIA_WF_RX_ABB_BT_MODE (((REG32(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER)) & 0x00400000 ) >> 22)
+#define GET_RG_GEMINIA_WF_RX_ABB_IDIV3 (((REG32(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER)) & 0x00800000 ) >> 23)
+#define GET_RG_GEMINIA_WF_RX_EN_IDACA_COARSE (((REG32(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER)) & 0x01000000 ) >> 24)
+#define GET_RG_GEMINIA_WF_RX_EN_LOOPA (((REG32(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER)) & 0x02000000 ) >> 25)
+#define GET_RG_GEMINIA_WF_RX_FILTERVCM (((REG32(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER)) & 0x0c000000 ) >> 26)
+#define GET_RG_GEMINIA_WF_RX_OUTVCM (((REG32(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER)) & 0x30000000 ) >> 28)
+#define GET_RG_GEMINIA_BT_RX_ABBCTUNEI (((REG32(ADR_GEMINIA_BT_RX_FILTER_REGISTER)) & 0x0000003f ) >> 0)
+#define GET_RG_GEMINIA_BT_RX_ABBCTUNEQ (((REG32(ADR_GEMINIA_BT_RX_FILTER_REGISTER)) & 0x00000fc0 ) >> 6)
+#define GET_RG_GEMINIA_BT_RX_FILTERI_COARSE (((REG32(ADR_GEMINIA_BT_RX_FILTER_REGISTER)) & 0x00003000 ) >> 12)
+#define GET_RG_GEMINIA_BT_RX_FILTERI1ST (((REG32(ADR_GEMINIA_BT_RX_FILTER_REGISTER)) & 0x0000c000 ) >> 14)
+#define GET_RG_GEMINIA_BT_RX_FILTERI2ND (((REG32(ADR_GEMINIA_BT_RX_FILTER_REGISTER)) & 0x00030000 ) >> 16)
+#define GET_RG_GEMINIA_BT_RX_FILTERI3RD (((REG32(ADR_GEMINIA_BT_RX_FILTER_REGISTER)) & 0x000c0000 ) >> 18)
+#define GET_RG_GEMINIA_BT_RX_ABBCFIX (((REG32(ADR_GEMINIA_BT_RX_FILTER_REGISTER)) & 0x00100000 ) >> 20)
+#define GET_RG_GEMINIA_BT_RX_ABB_N_MODE (((REG32(ADR_GEMINIA_BT_RX_FILTER_REGISTER)) & 0x00200000 ) >> 21)
+#define GET_RG_GEMINIA_BT_RX_ABB_BT_MODE (((REG32(ADR_GEMINIA_BT_RX_FILTER_REGISTER)) & 0x00400000 ) >> 22)
+#define GET_RG_GEMINIA_BT_RX_ABB_IDIV3 (((REG32(ADR_GEMINIA_BT_RX_FILTER_REGISTER)) & 0x00800000 ) >> 23)
+#define GET_RG_GEMINIA_BT_RX_EN_IDACA_COARSE (((REG32(ADR_GEMINIA_BT_RX_FILTER_REGISTER)) & 0x01000000 ) >> 24)
+#define GET_RG_GEMINIA_BT_RX_EN_LOOPA (((REG32(ADR_GEMINIA_BT_RX_FILTER_REGISTER)) & 0x02000000 ) >> 25)
+#define GET_RG_GEMINIA_BT_RX_FILTERVCM (((REG32(ADR_GEMINIA_BT_RX_FILTER_REGISTER)) & 0x0c000000 ) >> 26)
+#define GET_RG_GEMINIA_BT_RX_OUTVCM (((REG32(ADR_GEMINIA_BT_RX_FILTER_REGISTER)) & 0x30000000 ) >> 28)
+#define GET_RG_GEMINIA_RX_ADCRSSI_VCM (((REG32(ADR_GEMINIA_RX_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_GEMINIA_RX_REC_LPFCORNER (((REG32(ADR_GEMINIA_RX_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_GEMINIA_RX_ADCRSSI_CLKSEL (((REG32(ADR_GEMINIA_RX_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_RG_GEMINIA_RSSI_CLOCK_GATING (((REG32(ADR_GEMINIA_RX_REGISTER)) & 0x00000020 ) >> 5)
+#define GET_RG_GEMINIA_TX_DPDGM_BIAS (((REG32(ADR_GEMINIA_RX_REGISTER)) & 0x00000f00 ) >> 8)
+#define GET_RG_GEMINIA_TX_DPD_DIV (((REG32(ADR_GEMINIA_RX_REGISTER)) & 0x0000f000 ) >> 12)
+#define GET_RG_GEMINIA_TX_TSSI_BIAS (((REG32(ADR_GEMINIA_RX_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_GEMINIA_TX_TSSI_DIV (((REG32(ADR_GEMINIA_RX_REGISTER)) & 0x00380000 ) >> 19)
+#define GET_RG_GEMINIA_TX_TSSI_TEST (((REG32(ADR_GEMINIA_RX_REGISTER)) & 0x00c00000 ) >> 22)
+#define GET_RG_GEMINIA_TX_TSSI_TESTMODE (((REG32(ADR_GEMINIA_RX_REGISTER)) & 0x01000000 ) >> 24)
+#define GET_RG_GEMINIA_EN_RX_RSSI_TESTNODE (((REG32(ADR_GEMINIA_RX_REGISTER)) & 0x0e000000 ) >> 25)
+#define GET_RG_GEMINIA_RX_LNA_TRI_SEL (((REG32(ADR_GEMINIA_RX_REGISTER)) & 0x30000000 ) >> 28)
+#define GET_RG_GEMINIA_RX_LNA_SETTLE (((REG32(ADR_GEMINIA_RX_REGISTER)) & 0xc0000000 ) >> 30)
+#define GET_RG_GEMINIA_WF_TXPGA_CAPSW (((REG32(ADR_GEMINIA_WBT_TX_FE_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_GEMINIA_WF_TX_DIV_VSET (((REG32(ADR_GEMINIA_WBT_TX_FE_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_GEMINIA_WF_TX_LOBUF_VSET (((REG32(ADR_GEMINIA_WBT_TX_FE_REGISTER)) & 0x00000030 ) >> 4)
+#define GET_RG_GEMINIA_WF_TX_VDDSW (((REG32(ADR_GEMINIA_WBT_TX_FE_REGISTER)) & 0x00000040 ) >> 6)
+#define GET_RG_GEMINIA_BT_TXPGA_CAPSW (((REG32(ADR_GEMINIA_WBT_TX_FE_REGISTER)) & 0x00000300 ) >> 8)
+#define GET_RG_GEMINIA_BT_TX_DIV_VSET (((REG32(ADR_GEMINIA_WBT_TX_FE_REGISTER)) & 0x00000c00 ) >> 10)
+#define GET_RG_GEMINIA_BT_TX_LOBUF_VSET (((REG32(ADR_GEMINIA_WBT_TX_FE_REGISTER)) & 0x00003000 ) >> 12)
+#define GET_RG_GEMINIA_BT_TX_VDDSW (((REG32(ADR_GEMINIA_WBT_TX_FE_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_RG_GEMINIA_WF_PACELL_EN (((REG32(ADR_GEMINIA_WBT_TX_PA_REGISTER)) & 0x00000007 ) >> 0)
+#define GET_RG_GEMINIA_WF_PABIAS_CTRL (((REG32(ADR_GEMINIA_WBT_TX_PA_REGISTER)) & 0x000000f0 ) >> 4)
+#define GET_RG_GEMINIA_WF_TX_PA1_VCAS (((REG32(ADR_GEMINIA_WBT_TX_PA_REGISTER)) & 0x00000700 ) >> 8)
+#define GET_RG_GEMINIA_WF_TX_PA2_VCAS (((REG32(ADR_GEMINIA_WBT_TX_PA_REGISTER)) & 0x00007000 ) >> 12)
+#define GET_RG_GEMINIA_WF_TX_PA3_VCAS (((REG32(ADR_GEMINIA_WBT_TX_PA_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_GEMINIA_BT_PA_CAPSEL (((REG32(ADR_GEMINIA_WBT_TX_PA_REGISTER)) & 0x00700000 ) >> 20)
+#define GET_RG_GEMINIA_BT_PABIAS_2X (((REG32(ADR_GEMINIA_WBT_TX_PA_REGISTER)) & 0x00800000 ) >> 23)
+#define GET_RG_GEMINIA_BT_PABIAS_CTRL (((REG32(ADR_GEMINIA_WBT_TX_PA_REGISTER)) & 0x0f000000 ) >> 24)
+#define GET_RG_GEMINIA_BT_TX_PA_VCAS (((REG32(ADR_GEMINIA_WBT_TX_PA_REGISTER)) & 0x70000000 ) >> 28)
+#define GET_RG_GEMINIA_TXPGA_MAIN (((REG32(ADR_GEMINIA_TX_REGISTER)) & 0x0000003f ) >> 0)
+#define GET_RG_GEMINIA_TXPGA_STEER (((REG32(ADR_GEMINIA_TX_REGISTER)) & 0x00000fc0 ) >> 6)
+#define GET_RG_GEMINIA_TXMOD_GMCELL (((REG32(ADR_GEMINIA_TX_REGISTER)) & 0x00003000 ) >> 12)
+#define GET_RG_GEMINIA_TXLPF_GMCELL (((REG32(ADR_GEMINIA_TX_REGISTER)) & 0x0000c000 ) >> 14)
+#define GET_RG_GEMINIA_WF_TX_GAIN_OFFSET (((REG32(ADR_GEMINIA_TX_REGISTER)) & 0x000f0000 ) >> 16)
+#define GET_RG_GEMINIA_BT_TX_GAIN_OFFSET (((REG32(ADR_GEMINIA_TX_REGISTER)) & 0x00f00000 ) >> 20)
+#define GET_RG_GEMINIA_TX_VTOI_CURRENT (((REG32(ADR_GEMINIA_TX_REGISTER)) & 0x03000000 ) >> 24)
+#define GET_RG_GEMINIA_TX_VTOI_GM (((REG32(ADR_GEMINIA_TX_REGISTER)) & 0x0c000000 ) >> 26)
+#define GET_RG_GEMINIA_TX_VTOI_OPTION (((REG32(ADR_GEMINIA_TX_REGISTER)) & 0x30000000 ) >> 28)
+#define GET_RG_GEMINIA_TX_VTOI_FS (((REG32(ADR_GEMINIA_TX_REGISTER)) & 0x40000000 ) >> 30)
+#define GET_RG_GEMINIA_WF_RX_HG_LNA_GC (((REG32(ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_GEMINIA_WF_RX_HG_TZ_GC (((REG32(ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_GEMINIA_WF_RX_HG_LNAHGN_BIAS (((REG32(ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER)) & 0x000000f0 ) >> 4)
+#define GET_RG_GEMINIA_WF_RX_HG_LNAHGP_BIAS (((REG32(ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER)) & 0x00000f00 ) >> 8)
+#define GET_RG_GEMINIA_WF_RX_HG_LNALG_BIAS (((REG32(ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER)) & 0x0000f000 ) >> 12)
+#define GET_RG_GEMINIA_WF_RX_HG_TZ_CAP (((REG32(ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_GEMINIA_WF_RX_HG_SQDC (((REG32(ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER)) & 0x00700000 ) >> 20)
+#define GET_RG_GEMINIA_WF_RX_HG_DIV2_CORE (((REG32(ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER)) & 0x01800000 ) >> 23)
+#define GET_RG_GEMINIA_WF_RX_HG_LOBUF (((REG32(ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER)) & 0x06000000 ) >> 25)
+#define GET_RG_GEMINIA_WF_RX_HG_TZI (((REG32(ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER)) & 0x38000000 ) >> 27)
+#define GET_RG_GEMINIA_WF_RX_HG_TZ_VCM (((REG32(ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER)) & 0xc0000000 ) >> 30)
+#define GET_RG_GEMINIA_WF_RX_MG_LNA_GC (((REG32(ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_GEMINIA_WF_RX_MG_TZ_GC (((REG32(ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_GEMINIA_WF_RX_MG_LNAHGN_BIAS (((REG32(ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER)) & 0x000000f0 ) >> 4)
+#define GET_RG_GEMINIA_WF_RX_MG_LNAHGP_BIAS (((REG32(ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER)) & 0x00000f00 ) >> 8)
+#define GET_RG_GEMINIA_WF_RX_MG_LNALG_BIAS (((REG32(ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER)) & 0x0000f000 ) >> 12)
+#define GET_RG_GEMINIA_WF_RX_MG_TZ_CAP (((REG32(ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_GEMINIA_WF_RX_MG_SQDC (((REG32(ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER)) & 0x00700000 ) >> 20)
+#define GET_RG_GEMINIA_WF_RX_MG_DIV2_CORE (((REG32(ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER)) & 0x01800000 ) >> 23)
+#define GET_RG_GEMINIA_WF_RX_MG_LOBUF (((REG32(ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER)) & 0x06000000 ) >> 25)
+#define GET_RG_GEMINIA_WF_RX_MG_TZI (((REG32(ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER)) & 0x38000000 ) >> 27)
+#define GET_RG_GEMINIA_WF_RX_MG_TZ_VCM (((REG32(ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER)) & 0xc0000000 ) >> 30)
+#define GET_RG_GEMINIA_WF_RX_LG_LNA_GC (((REG32(ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_GEMINIA_WF_RX_LG_TZ_GC (((REG32(ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_GEMINIA_WF_RX_LG_LNAHGN_BIAS (((REG32(ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER)) & 0x000000f0 ) >> 4)
+#define GET_RG_GEMINIA_WF_RX_LG_LNAHGP_BIAS (((REG32(ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER)) & 0x00000f00 ) >> 8)
+#define GET_RG_GEMINIA_WF_RX_LG_LNALG_BIAS (((REG32(ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER)) & 0x0000f000 ) >> 12)
+#define GET_RG_GEMINIA_WF_RX_LG_TZ_CAP (((REG32(ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_GEMINIA_WF_RX_LG_SQDC (((REG32(ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER)) & 0x00700000 ) >> 20)
+#define GET_RG_GEMINIA_WF_RX_LG_DIV2_CORE (((REG32(ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER)) & 0x01800000 ) >> 23)
+#define GET_RG_GEMINIA_WF_RX_LG_LOBUF (((REG32(ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER)) & 0x06000000 ) >> 25)
+#define GET_RG_GEMINIA_WF_RX_LG_TZI (((REG32(ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER)) & 0x38000000 ) >> 27)
+#define GET_RG_GEMINIA_WF_RX_LG_TZ_VCM (((REG32(ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER)) & 0xc0000000 ) >> 30)
+#define GET_RG_GEMINIA_WF_RX_ULG_LNA_GC (((REG32(ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_GEMINIA_WF_RX_ULG_TZ_GC (((REG32(ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_GEMINIA_WF_RX_ULG_LNAHGN_BIAS (((REG32(ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER)) & 0x000000f0 ) >> 4)
+#define GET_RG_GEMINIA_WF_RX_ULG_LNAHGP_BIAS (((REG32(ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER)) & 0x00000f00 ) >> 8)
+#define GET_RG_GEMINIA_WF_RX_ULG_LNALG_BIAS (((REG32(ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER)) & 0x0000f000 ) >> 12)
+#define GET_RG_GEMINIA_WF_RX_ULG_TZ_CAP (((REG32(ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_GEMINIA_WF_RX_ULG_SQDC (((REG32(ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER)) & 0x00700000 ) >> 20)
+#define GET_RG_GEMINIA_WF_RX_ULG_DIV2_CORE (((REG32(ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER)) & 0x01800000 ) >> 23)
+#define GET_RG_GEMINIA_WF_RX_ULG_LOBUF (((REG32(ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER)) & 0x06000000 ) >> 25)
+#define GET_RG_GEMINIA_WF_RX_ULG_TZI (((REG32(ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER)) & 0x38000000 ) >> 27)
+#define GET_RG_GEMINIA_WF_RX_ULG_TZ_VCM (((REG32(ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER)) & 0xc0000000 ) >> 30)
+#define GET_RG_GEMINIA_BT_RX_HG_LNA_GC (((REG32(ADR_GEMINIA_BT_RX_FE_HG_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_GEMINIA_BT_RX_HG_TZ_GC (((REG32(ADR_GEMINIA_BT_RX_FE_HG_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_GEMINIA_BT_RX_HG_LNAHGN_BIAS (((REG32(ADR_GEMINIA_BT_RX_FE_HG_REGISTER)) & 0x000000f0 ) >> 4)
+#define GET_RG_GEMINIA_BT_RX_HG_LNAHGP_BIAS (((REG32(ADR_GEMINIA_BT_RX_FE_HG_REGISTER)) & 0x00000f00 ) >> 8)
+#define GET_RG_GEMINIA_BT_RX_HG_LNALG_BIAS (((REG32(ADR_GEMINIA_BT_RX_FE_HG_REGISTER)) & 0x0000f000 ) >> 12)
+#define GET_RG_GEMINIA_BT_RX_HG_TZ_CAP (((REG32(ADR_GEMINIA_BT_RX_FE_HG_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_GEMINIA_BT_RX_HG_SQDC (((REG32(ADR_GEMINIA_BT_RX_FE_HG_REGISTER)) & 0x00700000 ) >> 20)
+#define GET_RG_GEMINIA_BT_RX_HG_DIV2_CORE (((REG32(ADR_GEMINIA_BT_RX_FE_HG_REGISTER)) & 0x01800000 ) >> 23)
+#define GET_RG_GEMINIA_BT_RX_HG_LOBUF (((REG32(ADR_GEMINIA_BT_RX_FE_HG_REGISTER)) & 0x06000000 ) >> 25)
+#define GET_RG_GEMINIA_BT_RX_HG_TZI (((REG32(ADR_GEMINIA_BT_RX_FE_HG_REGISTER)) & 0x38000000 ) >> 27)
+#define GET_RG_GEMINIA_BT_RX_HG_TZ_VCM (((REG32(ADR_GEMINIA_BT_RX_FE_HG_REGISTER)) & 0xc0000000 ) >> 30)
+#define GET_RG_GEMINIA_BT_RX_MG_LNA_GC (((REG32(ADR_GEMINIA_BT_RX_FE_MG_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_GEMINIA_BT_RX_MG_TZ_GC (((REG32(ADR_GEMINIA_BT_RX_FE_MG_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_GEMINIA_BT_RX_MG_LNAHGN_BIAS (((REG32(ADR_GEMINIA_BT_RX_FE_MG_REGISTER)) & 0x000000f0 ) >> 4)
+#define GET_RG_GEMINIA_BT_RX_MG_LNAHGP_BIAS (((REG32(ADR_GEMINIA_BT_RX_FE_MG_REGISTER)) & 0x00000f00 ) >> 8)
+#define GET_RG_GEMINIA_BT_RX_MG_LNALG_BIAS (((REG32(ADR_GEMINIA_BT_RX_FE_MG_REGISTER)) & 0x0000f000 ) >> 12)
+#define GET_RG_GEMINIA_BT_RX_MG_TZ_CAP (((REG32(ADR_GEMINIA_BT_RX_FE_MG_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_GEMINIA_BT_RX_MG_SQDC (((REG32(ADR_GEMINIA_BT_RX_FE_MG_REGISTER)) & 0x00700000 ) >> 20)
+#define GET_RG_GEMINIA_BT_RX_MG_DIV2_CORE (((REG32(ADR_GEMINIA_BT_RX_FE_MG_REGISTER)) & 0x01800000 ) >> 23)
+#define GET_RG_GEMINIA_BT_RX_MG_LOBUF (((REG32(ADR_GEMINIA_BT_RX_FE_MG_REGISTER)) & 0x06000000 ) >> 25)
+#define GET_RG_GEMINIA_BT_RX_MG_TZI (((REG32(ADR_GEMINIA_BT_RX_FE_MG_REGISTER)) & 0x38000000 ) >> 27)
+#define GET_RG_GEMINIA_BT_RX_MG_TZ_VCM (((REG32(ADR_GEMINIA_BT_RX_FE_MG_REGISTER)) & 0xc0000000 ) >> 30)
+#define GET_RG_GEMINIA_BT_RX_LG_LNA_GC (((REG32(ADR_GEMINIA_BT_RX_FE_LG_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_GEMINIA_BT_RX_LG_TZ_GC (((REG32(ADR_GEMINIA_BT_RX_FE_LG_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_GEMINIA_BT_RX_LG_LNAHGN_BIAS (((REG32(ADR_GEMINIA_BT_RX_FE_LG_REGISTER)) & 0x000000f0 ) >> 4)
+#define GET_RG_GEMINIA_BT_RX_LG_LNAHGP_BIAS (((REG32(ADR_GEMINIA_BT_RX_FE_LG_REGISTER)) & 0x00000f00 ) >> 8)
+#define GET_RG_GEMINIA_BT_RX_LG_LNALG_BIAS (((REG32(ADR_GEMINIA_BT_RX_FE_LG_REGISTER)) & 0x0000f000 ) >> 12)
+#define GET_RG_GEMINIA_BT_RX_LG_TZ_CAP (((REG32(ADR_GEMINIA_BT_RX_FE_LG_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_GEMINIA_BT_RX_LG_SQDC (((REG32(ADR_GEMINIA_BT_RX_FE_LG_REGISTER)) & 0x00700000 ) >> 20)
+#define GET_RG_GEMINIA_BT_RX_LG_DIV2_CORE (((REG32(ADR_GEMINIA_BT_RX_FE_LG_REGISTER)) & 0x01800000 ) >> 23)
+#define GET_RG_GEMINIA_BT_RX_LG_LOBUF (((REG32(ADR_GEMINIA_BT_RX_FE_LG_REGISTER)) & 0x06000000 ) >> 25)
+#define GET_RG_GEMINIA_BT_RX_LG_TZI (((REG32(ADR_GEMINIA_BT_RX_FE_LG_REGISTER)) & 0x38000000 ) >> 27)
+#define GET_RG_GEMINIA_BT_RX_LG_TZ_VCM (((REG32(ADR_GEMINIA_BT_RX_FE_LG_REGISTER)) & 0xc0000000 ) >> 30)
+#define GET_RG_GEMINIA_BT_RX_ULG_LNA_GC (((REG32(ADR_GEMINIA_BT_RX_FE_ULG_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_GEMINIA_BT_RX_ULG_TZ_GC (((REG32(ADR_GEMINIA_BT_RX_FE_ULG_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_GEMINIA_BT_RX_ULG_LNAHGN_BIAS (((REG32(ADR_GEMINIA_BT_RX_FE_ULG_REGISTER)) & 0x000000f0 ) >> 4)
+#define GET_RG_GEMINIA_BT_RX_ULG_LNAHGP_BIAS (((REG32(ADR_GEMINIA_BT_RX_FE_ULG_REGISTER)) & 0x00000f00 ) >> 8)
+#define GET_RG_GEMINIA_BT_RX_ULG_LNALG_BIAS (((REG32(ADR_GEMINIA_BT_RX_FE_ULG_REGISTER)) & 0x0000f000 ) >> 12)
+#define GET_RG_GEMINIA_BT_RX_ULG_TZ_CAP (((REG32(ADR_GEMINIA_BT_RX_FE_ULG_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_GEMINIA_BT_RX_ULG_SQDC (((REG32(ADR_GEMINIA_BT_RX_FE_ULG_REGISTER)) & 0x00700000 ) >> 20)
+#define GET_RG_GEMINIA_BT_RX_ULG_DIV2_CORE (((REG32(ADR_GEMINIA_BT_RX_FE_ULG_REGISTER)) & 0x01800000 ) >> 23)
+#define GET_RG_GEMINIA_BT_RX_ULG_LOBUF (((REG32(ADR_GEMINIA_BT_RX_FE_ULG_REGISTER)) & 0x06000000 ) >> 25)
+#define GET_RG_GEMINIA_BT_RX_ULG_TZI (((REG32(ADR_GEMINIA_BT_RX_FE_ULG_REGISTER)) & 0x38000000 ) >> 27)
+#define GET_RG_GEMINIA_BT_RX_ULG_TZ_VCM (((REG32(ADR_GEMINIA_BT_RX_FE_ULG_REGISTER)) & 0xc0000000 ) >> 30)
+#define GET_RG_GEMINIA_RX_ADC_CLKSEL (((REG32(ADR_GEMINIA_RX_ADC_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_GEMINIA_RX_ADC_DNLEN (((REG32(ADR_GEMINIA_RX_ADC_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_RG_GEMINIA_RX_ADC_METAEN (((REG32(ADR_GEMINIA_RX_ADC_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_RG_GEMINIA_RX_ADC_TFLAG (((REG32(ADR_GEMINIA_RX_ADC_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_RG_GEMINIA_RX_ADC_TSEL (((REG32(ADR_GEMINIA_RX_ADC_REGISTER)) & 0x000000f0 ) >> 4)
+#define GET_RG_GEMINIA_WF_RX_ADC_ICMP (((REG32(ADR_GEMINIA_RX_ADC_REGISTER)) & 0x00000300 ) >> 8)
+#define GET_RG_GEMINIA_WF_RX_ADC_VCMI (((REG32(ADR_GEMINIA_RX_ADC_REGISTER)) & 0x00000c00 ) >> 10)
+#define GET_RG_GEMINIA_WF_RX_ADC_CLOAD (((REG32(ADR_GEMINIA_RX_ADC_REGISTER)) & 0x00003000 ) >> 12)
+#define GET_RG_GEMINIA_BT_RX_ADC_ICMP (((REG32(ADR_GEMINIA_RX_ADC_REGISTER)) & 0x00030000 ) >> 16)
+#define GET_RG_GEMINIA_BT_RX_ADC_VCMI (((REG32(ADR_GEMINIA_RX_ADC_REGISTER)) & 0x000c0000 ) >> 18)
+#define GET_RG_GEMINIA_BT_RX_ADC_CLOAD (((REG32(ADR_GEMINIA_RX_ADC_REGISTER)) & 0x00300000 ) >> 20)
+#define GET_RG_GEMINIA_SARADC_VRSEL (((REG32(ADR_GEMINIA_RX_ADC_REGISTER)) & 0x03000000 ) >> 24)
+#define GET_RG_GEMINIA_EN_SAR_TEST (((REG32(ADR_GEMINIA_RX_ADC_REGISTER)) & 0x0c000000 ) >> 26)
+#define GET_RG_GEMINIA_SARADC_THERMAL (((REG32(ADR_GEMINIA_RX_ADC_REGISTER)) & 0x10000000 ) >> 28)
+#define GET_RG_GEMINIA_SARADC_TSSI (((REG32(ADR_GEMINIA_RX_ADC_REGISTER)) & 0x20000000 ) >> 29)
+#define GET_RG_GEMINIA_CLK_SAR_SEL (((REG32(ADR_GEMINIA_RX_ADC_REGISTER)) & 0xc0000000 ) >> 30)
+#define GET_RG_GEMINIA_WF_TX_DACI1ST (((REG32(ADR_GEMINIA_WIFI_TX_DAC_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_GEMINIA_WF_TX_DACLPF_ICOARSE (((REG32(ADR_GEMINIA_WIFI_TX_DAC_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_GEMINIA_WF_TX_DACLPF_IFINE (((REG32(ADR_GEMINIA_WIFI_TX_DAC_REGISTER)) & 0x00000030 ) >> 4)
+#define GET_RG_GEMINIA_WF_TX_DACLPF_VCM (((REG32(ADR_GEMINIA_WIFI_TX_DAC_REGISTER)) & 0x000000c0 ) >> 6)
+#define GET_RG_GEMINIA_WF_TX_DAC_IBIAS (((REG32(ADR_GEMINIA_WIFI_TX_DAC_REGISTER)) & 0x00000300 ) >> 8)
+#define GET_RG_GEMINIA_WF_TX_DAC_IATTN (((REG32(ADR_GEMINIA_WIFI_TX_DAC_REGISTER)) & 0x00000400 ) >> 10)
+#define GET_RG_GEMINIA_WF_TXLPF_BOOSTI (((REG32(ADR_GEMINIA_WIFI_TX_DAC_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_RG_GEMINIA_WF_TX_DAC_RCAL (((REG32(ADR_GEMINIA_WIFI_TX_DAC_REGISTER)) & 0x00003000 ) >> 12)
+#define GET_RG_GEMINIA_WF_TX_DAC_CKEDGE_SEL (((REG32(ADR_GEMINIA_WIFI_TX_DAC_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_RG_GEMINIA_WF_TX_DAC_OS (((REG32(ADR_GEMINIA_WIFI_TX_DAC_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_GEMINIA_WF_TX_DAC_IOFFSET (((REG32(ADR_GEMINIA_WIFI_TX_DAC_REGISTER)) & 0x00f00000 ) >> 20)
+#define GET_RG_GEMINIA_WF_TX_DAC_QOFFSET (((REG32(ADR_GEMINIA_WIFI_TX_DAC_REGISTER)) & 0x0f000000 ) >> 24)
+#define GET_RG_GEMINIA_TX_DAC_TSEL (((REG32(ADR_GEMINIA_WIFI_TX_DAC_REGISTER)) & 0xf0000000 ) >> 28)
+#define GET_RG_GEMINIA_BT_TX_DACI1ST (((REG32(ADR_GEMINIA_BT_TX_DAC_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_GEMINIA_BT_TX_DACLPF_ICOARSE (((REG32(ADR_GEMINIA_BT_TX_DAC_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_GEMINIA_BT_TX_DACLPF_IFINE (((REG32(ADR_GEMINIA_BT_TX_DAC_REGISTER)) & 0x00000030 ) >> 4)
+#define GET_RG_GEMINIA_BT_TX_DACLPF_VCM (((REG32(ADR_GEMINIA_BT_TX_DAC_REGISTER)) & 0x000000c0 ) >> 6)
+#define GET_RG_GEMINIA_BT_TX_DAC_IBIAS (((REG32(ADR_GEMINIA_BT_TX_DAC_REGISTER)) & 0x00000300 ) >> 8)
+#define GET_RG_GEMINIA_BT_TX_DAC_IATTN (((REG32(ADR_GEMINIA_BT_TX_DAC_REGISTER)) & 0x00000400 ) >> 10)
+#define GET_RG_GEMINIA_BT_TXLPF_BOOSTI (((REG32(ADR_GEMINIA_BT_TX_DAC_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_RG_GEMINIA_BT_TX_DAC_RCAL (((REG32(ADR_GEMINIA_BT_TX_DAC_REGISTER)) & 0x00003000 ) >> 12)
+#define GET_RG_GEMINIA_BT_TX_DAC_CKEDGE_SEL (((REG32(ADR_GEMINIA_BT_TX_DAC_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_RG_GEMINIA_BT_TX_DAC_OS (((REG32(ADR_GEMINIA_BT_TX_DAC_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_GEMINIA_BT_TX_DAC_IOFFSET (((REG32(ADR_GEMINIA_BT_TX_DAC_REGISTER)) & 0x00f00000 ) >> 20)
+#define GET_RG_GEMINIA_BT_TX_DAC_QOFFSET (((REG32(ADR_GEMINIA_BT_TX_DAC_REGISTER)) & 0x0f000000 ) >> 24)
+#define GET_RG_GEMINIA_SX_EN_MAN (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000001 ) >> 0)
+#define GET_RG_GEMINIA_SX_EN (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000002 ) >> 1)
+#define GET_RG_GEMINIA_EN_SX_CP_MAN (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000004 ) >> 2)
+#define GET_RG_GEMINIA_EN_SX_CP (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000008 ) >> 3)
+#define GET_RG_GEMINIA_EN_SX_DIV_MAN (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000010 ) >> 4)
+#define GET_RG_GEMINIA_EN_SX_DIV (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000020 ) >> 5)
+#define GET_RG_GEMINIA_EN_SX_VCO_MAN (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000040 ) >> 6)
+#define GET_RG_GEMINIA_EN_SX_VCO (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000080 ) >> 7)
+#define GET_RG_GEMINIA_SX_PFD_RST_MAN (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000100 ) >> 8)
+#define GET_RG_GEMINIA_SX_PFD_RST (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000200 ) >> 9)
+#define GET_RG_GEMINIA_SX_UOP_MAN (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000400 ) >> 10)
+#define GET_RG_GEMINIA_SX_UOP_EN (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000800 ) >> 11)
+#define GET_RG_GEMINIA_EN_VCOBF_TXMB_MAN (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00001000 ) >> 12)
+#define GET_RG_GEMINIA_EN_VCOBF_TXMB (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00002000 ) >> 13)
+#define GET_RG_GEMINIA_EN_VCOBF_TXOB_MAN (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00004000 ) >> 14)
+#define GET_RG_GEMINIA_EN_VCOBF_TXOB (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00008000 ) >> 15)
+#define GET_RG_GEMINIA_EN_VCOBF_RXMB_MAN (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00010000 ) >> 16)
+#define GET_RG_GEMINIA_EN_VCOBF_RXMB (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00020000 ) >> 17)
+#define GET_RG_GEMINIA_EN_VCOBF_RXOB_MAN (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00040000 ) >> 18)
+#define GET_RG_GEMINIA_EN_VCOBF_RXOB (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00080000 ) >> 19)
+#define GET_RG_GEMINIA_EN_VCOBF_DIVCK_MAN (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00100000 ) >> 20)
+#define GET_RG_GEMINIA_EN_VCOBF_DIVCK (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00200000 ) >> 21)
+#define GET_RG_GEMINIA_SX_SBCAL_DIS (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00800000 ) >> 23)
+#define GET_RG_GEMINIA_SX_SBCAL_AW (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x01000000 ) >> 24)
+#define GET_RG_GEMINIA_SX_AAC_DIS (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x04000000 ) >> 26)
+#define GET_RG_GEMINIA_SX_TTL_DIS (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x08000000 ) >> 27)
+#define GET_RG_GEMINIA_SX_CAL_INIT (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0xe0000000 ) >> 29)
+#define GET_RG_GEMINIA_EN_SX_LDO_MAN (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_GEMINIA_EN_LDO_CP (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_RG_GEMINIA_EN_LDO_DIV (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_RG_GEMINIA_EN_LDO_LO (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_RG_GEMINIA_EN_LDO_VCO (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_RG_GEMINIA_EN_LDO_CP_BYP (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0x00000040 ) >> 6)
+#define GET_RG_GEMINIA_EN_LDO_DIV_BYP (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0x00000080 ) >> 7)
+#define GET_RG_GEMINIA_EN_LDO_LO_BYP (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0x00000100 ) >> 8)
+#define GET_RG_GEMINIA_EN_LDO_VCO_PSW (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0x00000200 ) >> 9)
+#define GET_RG_GEMINIA_EN_LDO_VCO_VDD33 (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0x00000400 ) >> 10)
+#define GET_RG_GEMINIA_EN_LDO_CP_IQUP (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_RG_GEMINIA_EN_LDO_DIV_IQUP (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0x00001000 ) >> 12)
+#define GET_RG_GEMINIA_EN_LDO_LO_IQUP (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0x00002000 ) >> 13)
+#define GET_RG_GEMINIA_EN_LDO_VCO_IQUP (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_RG_GEMINIA_SX_LDO_FCOFFT (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0x00380000 ) >> 19)
+#define GET_RG_GEMINIA_LDO_CP_FC_MAN (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0x00400000 ) >> 22)
+#define GET_RG_GEMINIA_LDO_CP_FC (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0x00800000 ) >> 23)
+#define GET_RG_GEMINIA_LDO_DIV_FC_MAN (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0x01000000 ) >> 24)
+#define GET_RG_GEMINIA_LDO_DIV_FC (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0x02000000 ) >> 25)
+#define GET_RG_GEMINIA_LDO_LO_FC_MAN (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0x04000000 ) >> 26)
+#define GET_RG_GEMINIA_LDO_LO_FC (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0x08000000 ) >> 27)
+#define GET_RG_GEMINIA_LDO_VCO_FC_MAN (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0x10000000 ) >> 28)
+#define GET_RG_GEMINIA_LDO_VCO_FC (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0x20000000 ) >> 29)
+#define GET_RG_GEMINIA_LDO_VCO_RCF (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0xc0000000 ) >> 30)
+#define GET_RG_GEMINIA_SX_RFCTRL_F (((REG32(ADR_GEMINIA_SYN_FRACTIONAL_AND_INTEGER_8BITS)) & 0x00ffffff ) >> 0)
+#define GET_RG_GEMINIA_SX_RFCTRL_CH_7_0 (((REG32(ADR_GEMINIA_SYN_FRACTIONAL_AND_INTEGER_8BITS)) & 0xff000000 ) >> 24)
+#define GET_RG_GEMINIA_SX_RFCTRL_CH_10_8 (((REG32(ADR_GEMINIA_SYN_REGISTER_INT3BIT_CH_TABLE)) & 0x00000007 ) >> 0)
+#define GET_RG_GEMINIA_SX_RFCH_MAP_EN (((REG32(ADR_GEMINIA_SYN_REGISTER_INT3BIT_CH_TABLE)) & 0x00000010 ) >> 4)
+#define GET_RG_GEMINIA_SX_XTAL_FREQ (((REG32(ADR_GEMINIA_SYN_REGISTER_INT3BIT_CH_TABLE)) & 0x00000060 ) >> 5)
+#define GET_RG_GEMINIA_SX_FREF_DOUB (((REG32(ADR_GEMINIA_SYN_REGISTER_INT3BIT_CH_TABLE)) & 0x00000080 ) >> 7)
+#define GET_RG_GEMINIA_SX_BTRX_SIDE (((REG32(ADR_GEMINIA_SYN_REGISTER_INT3BIT_CH_TABLE)) & 0x00000100 ) >> 8)
+#define GET_RG_GEMINIA_SX_LO_TIMES (((REG32(ADR_GEMINIA_SYN_REGISTER_INT3BIT_CH_TABLE)) & 0x00000200 ) >> 9)
+#define GET_RG_GEMINIA_SX_CHANNEL (((REG32(ADR_GEMINIA_SYN_REGISTER_INT3BIT_CH_TABLE)) & 0x0007f800 ) >> 11)
+#define GET_RG_GEMINIA_SX_CP_ISEL_BT (((REG32(ADR_GEMINIA_SYN_PFD_CHP_)) & 0x0000000f ) >> 0)
+#define GET_RG_GEMINIA_SX_CP_ISEL50U_BT (((REG32(ADR_GEMINIA_SYN_PFD_CHP_)) & 0x00000010 ) >> 4)
+#define GET_RG_GEMINIA_SX_CP_KP_DOUB_BT (((REG32(ADR_GEMINIA_SYN_PFD_CHP_)) & 0x00000020 ) >> 5)
+#define GET_RG_GEMINIA_SX_CP_ISEL_WF (((REG32(ADR_GEMINIA_SYN_PFD_CHP_)) & 0x00000780 ) >> 7)
+#define GET_RG_GEMINIA_SX_CP_ISEL50U_WF (((REG32(ADR_GEMINIA_SYN_PFD_CHP_)) & 0x00000800 ) >> 11)
+#define GET_RG_GEMINIA_SX_CP_KP_DOUB_WF (((REG32(ADR_GEMINIA_SYN_PFD_CHP_)) & 0x00001000 ) >> 12)
+#define GET_RG_GEMINIA_SX_CP_IOST_POL (((REG32(ADR_GEMINIA_SYN_PFD_CHP_)) & 0x00008000 ) >> 15)
+#define GET_RG_GEMINIA_SX_CP_IOST (((REG32(ADR_GEMINIA_SYN_PFD_CHP_)) & 0x00070000 ) >> 16)
+#define GET_RG_GEMINIA_SX_PFD_SEL (((REG32(ADR_GEMINIA_SYN_PFD_CHP_)) & 0x00400000 ) >> 22)
+#define GET_RG_GEMINIA_SX_PFD_SET (((REG32(ADR_GEMINIA_SYN_PFD_CHP_)) & 0x00800000 ) >> 23)
+#define GET_RG_GEMINIA_SX_PFD_SET1 (((REG32(ADR_GEMINIA_SYN_PFD_CHP_)) & 0x01000000 ) >> 24)
+#define GET_RG_GEMINIA_SX_PFD_SET2 (((REG32(ADR_GEMINIA_SYN_PFD_CHP_)) & 0x02000000 ) >> 25)
+#define GET_RG_GEMINIA_SX_PFD_TRUP (((REG32(ADR_GEMINIA_SYN_PFD_CHP_)) & 0x10000000 ) >> 28)
+#define GET_RG_GEMINIA_SX_PFD_TRDN (((REG32(ADR_GEMINIA_SYN_PFD_CHP_)) & 0x20000000 ) >> 29)
+#define GET_RG_GEMINIA_SX_PFD_TLSEL (((REG32(ADR_GEMINIA_SYN_PFD_CHP_)) & 0x40000000 ) >> 30)
+#define GET_RG_GEMINIA_SX_LPF_C1_BT (((REG32(ADR_GEMINIA_SYN_LPF)) & 0x0000000f ) >> 0)
+#define GET_RG_GEMINIA_SX_LPF_C2_BT (((REG32(ADR_GEMINIA_SYN_LPF)) & 0x000000f0 ) >> 4)
+#define GET_RG_GEMINIA_SX_LPF_C3_BT (((REG32(ADR_GEMINIA_SYN_LPF)) & 0x00000100 ) >> 8)
+#define GET_RG_GEMINIA_SX_LPF_R2_BT (((REG32(ADR_GEMINIA_SYN_LPF)) & 0x00001e00 ) >> 9)
+#define GET_RG_GEMINIA_SX_LPF_R3_BT (((REG32(ADR_GEMINIA_SYN_LPF)) & 0x0000e000 ) >> 13)
+#define GET_RG_GEMINIA_SX_LPF_C1_WF (((REG32(ADR_GEMINIA_SYN_LPF)) & 0x000f0000 ) >> 16)
+#define GET_RG_GEMINIA_SX_LPF_C2_WF (((REG32(ADR_GEMINIA_SYN_LPF)) & 0x00f00000 ) >> 20)
+#define GET_RG_GEMINIA_SX_LPF_C3_WF (((REG32(ADR_GEMINIA_SYN_LPF)) & 0x01000000 ) >> 24)
+#define GET_RG_GEMINIA_SX_LPF_R2_WF (((REG32(ADR_GEMINIA_SYN_LPF)) & 0x1e000000 ) >> 25)
+#define GET_RG_GEMINIA_SX_LPF_R3_WF (((REG32(ADR_GEMINIA_SYN_LPF)) & 0xe0000000 ) >> 29)
+#define GET_RG_GEMINIA_SX_VCO_ISEL_MAN (((REG32(ADR_GEMINIA_SYN_VCO)) & 0x00000001 ) >> 0)
+#define GET_RG_GEMINIA_SX_VCO_ISEL_BT (((REG32(ADR_GEMINIA_SYN_VCO)) & 0x0000001e ) >> 1)
+#define GET_RG_GEMINIA_SX_VCO_LPM_BT (((REG32(ADR_GEMINIA_SYN_VCO)) & 0x00000020 ) >> 5)
+#define GET_RG_GEMINIA_SX_VCO_VCCBSEL_BT (((REG32(ADR_GEMINIA_SYN_VCO)) & 0x000001c0 ) >> 6)
+#define GET_RG_GEMINIA_SX_VCO_KVDOUB_BT (((REG32(ADR_GEMINIA_SYN_VCO)) & 0x00000200 ) >> 9)
+#define GET_RG_GEMINIA_SX_VCO_ISEL_WF (((REG32(ADR_GEMINIA_SYN_VCO)) & 0x00003c00 ) >> 10)
+#define GET_RG_GEMINIA_SX_VCO_LPM_WF (((REG32(ADR_GEMINIA_SYN_VCO)) & 0x00004000 ) >> 14)
+#define GET_RG_GEMINIA_SX_VCO_VCCBSEL_WF (((REG32(ADR_GEMINIA_SYN_VCO)) & 0x00038000 ) >> 15)
+#define GET_RG_GEMINIA_SX_VCO_KVDOUB_WF (((REG32(ADR_GEMINIA_SYN_VCO)) & 0x00040000 ) >> 18)
+#define GET_RG_GEMINIA_SX_VCO_VARBSEL (((REG32(ADR_GEMINIA_SYN_VCO)) & 0x00600000 ) >> 21)
+#define GET_RG_GEMINIA_SX_VCO_RTAIL_SHIFT (((REG32(ADR_GEMINIA_SYN_VCO)) & 0x00800000 ) >> 23)
+#define GET_RG_GEMINIA_SX_VCO_CS_AWH (((REG32(ADR_GEMINIA_SYN_VCO)) & 0x01000000 ) >> 24)
+#define GET_RG_GEMINIA_VOBF_TXMBSEL_BT (((REG32(ADR_GEMINIA_SYN_VCOBF)) & 0x00000003 ) >> 0)
+#define GET_RG_GEMINIA_VOBF_TXOBSEL_BT (((REG32(ADR_GEMINIA_SYN_VCOBF)) & 0x0000000c ) >> 2)
+#define GET_RG_GEMINIA_VOBF_RXMBSEL_BT (((REG32(ADR_GEMINIA_SYN_VCOBF)) & 0x00000030 ) >> 4)
+#define GET_RG_GEMINIA_VOBF_RXOBSEL_BT (((REG32(ADR_GEMINIA_SYN_VCOBF)) & 0x000000c0 ) >> 6)
+#define GET_RG_GEMINIA_VOBF_TXMBSEL_WF (((REG32(ADR_GEMINIA_SYN_VCOBF)) & 0x00000c00 ) >> 10)
+#define GET_RG_GEMINIA_VOBF_TXOBSEL_WF (((REG32(ADR_GEMINIA_SYN_VCOBF)) & 0x00003000 ) >> 12)
+#define GET_RG_GEMINIA_VOBF_RXMBSEL_WF (((REG32(ADR_GEMINIA_SYN_VCOBF)) & 0x0000c000 ) >> 14)
+#define GET_RG_GEMINIA_VOBF_RXOBSEL_WF (((REG32(ADR_GEMINIA_SYN_VCOBF)) & 0x00030000 ) >> 16)
+#define GET_RG_GEMINIA_VOBF_DIVBFSEL (((REG32(ADR_GEMINIA_SYN_VCOBF)) & 0x00080000 ) >> 19)
+#define GET_RG_GEMINIA_SX_VCO_TXOB_AW (((REG32(ADR_GEMINIA_SYN_VCOBF)) & 0x00100000 ) >> 20)
+#define GET_RG_GEMINIA_SX_VCO_RXOB_AW (((REG32(ADR_GEMINIA_SYN_VCOBF)) & 0x00200000 ) >> 21)
+#define GET_RG_GEMINIA_VOBF_CAPIMB_POL (((REG32(ADR_GEMINIA_SYN_VCOBF)) & 0x04000000 ) >> 26)
+#define GET_RG_GEMINIA_VOBF_CAPIMB (((REG32(ADR_GEMINIA_SYN_VCOBF)) & 0x38000000 ) >> 27)
+#define GET_RG_GEMINIA_EN_SX_VCOMON (((REG32(ADR_GEMINIA_SYN_VCOBF)) & 0x80000000 ) >> 31)
+#define GET_RG_GEMINIA_SX_DIV_PREVDD (((REG32(ADR_GEMINIA_SYN_DIV_SDM)) & 0x0000000f ) >> 0)
+#define GET_RG_GEMINIA_SX_DIV_PSCVDD (((REG32(ADR_GEMINIA_SYN_DIV_SDM)) & 0x000000f0 ) >> 4)
+#define GET_RG_GEMINIA_SX_DIV_RST_H (((REG32(ADR_GEMINIA_SYN_DIV_SDM)) & 0x00000200 ) >> 9)
+#define GET_RG_GEMINIA_SX_DIV_SDM_EDGE (((REG32(ADR_GEMINIA_SYN_DIV_SDM)) & 0x00000400 ) >> 10)
+#define GET_RG_GEMINIA_SX_DIV_DMYBUF_EN (((REG32(ADR_GEMINIA_SYN_DIV_SDM)) & 0x00000800 ) >> 11)
+#define GET_RG_GEMINIA_EN_SX_MOD (((REG32(ADR_GEMINIA_SYN_DIV_SDM)) & 0x00020000 ) >> 17)
+#define GET_RG_GEMINIA_EN_SX_DITHER (((REG32(ADR_GEMINIA_SYN_DIV_SDM)) & 0x00040000 ) >> 18)
+#define GET_RG_GEMINIA_SX_MOD_ORDER (((REG32(ADR_GEMINIA_SYN_DIV_SDM)) & 0x00180000 ) >> 19)
+#define GET_RG_GEMINIA_SX_DITHER_WEIGHT (((REG32(ADR_GEMINIA_SYN_DIV_SDM)) & 0x00600000 ) >> 21)
+#define GET_RG_GEMINIA_SX_SUB_SEL_MAN (((REG32(ADR_GEMINIA_SYN_SBCAL)) & 0x00000001 ) >> 0)
+#define GET_RG_GEMINIA_SX_SUB_SEL (((REG32(ADR_GEMINIA_SYN_SBCAL)) & 0x000001fe ) >> 1)
+#define GET_RG_GEMINIA_SX_SUB_C0P5_DIS (((REG32(ADR_GEMINIA_SYN_SBCAL)) & 0x00000200 ) >> 9)
+#define GET_RG_GEMINIA_SX_SBCAL_CT (((REG32(ADR_GEMINIA_SYN_SBCAL)) & 0x00000c00 ) >> 10)
+#define GET_RG_GEMINIA_SX_SBCAL_WT (((REG32(ADR_GEMINIA_SYN_SBCAL)) & 0x00001000 ) >> 12)
+#define GET_RG_GEMINIA_SX_SBCAL_DIFFMIN (((REG32(ADR_GEMINIA_SYN_SBCAL)) & 0x00002000 ) >> 13)
+#define GET_RG_GEMINIA_SX_SBCAL_NTARG_MAN (((REG32(ADR_GEMINIA_SYN_SBCAL)) & 0x00008000 ) >> 15)
+#define GET_RG_GEMINIA_SX_SBCAL_NTARG (((REG32(ADR_GEMINIA_SYN_SBCAL)) & 0xffff0000 ) >> 16)
+#define GET_RG_GEMINIA_VO_AAC_TAR_BT (((REG32(ADR_GEMINIA_SYN_AAC)) & 0x0000000f ) >> 0)
+#define GET_RG_GEMINIA_VO_AAC_IOST_BT (((REG32(ADR_GEMINIA_SYN_AAC)) & 0x00000030 ) >> 4)
+#define GET_RG_GEMINIA_VO_AAC_TAR_WF (((REG32(ADR_GEMINIA_SYN_AAC)) & 0x00000780 ) >> 7)
+#define GET_RG_GEMINIA_VO_AAC_IOST_WF (((REG32(ADR_GEMINIA_SYN_AAC)) & 0x00001800 ) >> 11)
+#define GET_RG_GEMINIA_VO_AAC_IMAX (((REG32(ADR_GEMINIA_SYN_AAC)) & 0x0003c000 ) >> 14)
+#define GET_RG_GEMINIA_VO_AAC_INIT (((REG32(ADR_GEMINIA_SYN_AAC)) & 0x000c0000 ) >> 18)
+#define GET_RG_GEMINIA_VO_AAC_EVA_TS (((REG32(ADR_GEMINIA_SYN_AAC)) & 0x00300000 ) >> 20)
+#define GET_RG_GEMINIA_VO_AAC_EN_MAN (((REG32(ADR_GEMINIA_SYN_AAC)) & 0x00800000 ) >> 23)
+#define GET_RG_GEMINIA_VO_AAC_EN (((REG32(ADR_GEMINIA_SYN_AAC)) & 0x01000000 ) >> 24)
+#define GET_RG_GEMINIA_VO_AAC_EVA_MAN (((REG32(ADR_GEMINIA_SYN_AAC)) & 0x02000000 ) >> 25)
+#define GET_RG_GEMINIA_VO_AAC_EVA (((REG32(ADR_GEMINIA_SYN_AAC)) & 0x04000000 ) >> 26)
+#define GET_RG_GEMINIA_VO_AAC_TEST_EN (((REG32(ADR_GEMINIA_SYN_AAC)) & 0x10000000 ) >> 28)
+#define GET_RG_GEMINIA_VO_AAC_TEST_SEL (((REG32(ADR_GEMINIA_SYN_AAC)) & 0x20000000 ) >> 29)
+#define GET_RG_GEMINIA_SX_TTL_INIT (((REG32(ADR_GEMINIA_SYN_TTL)) & 0x00000003 ) >> 0)
+#define GET_RG_GEMINIA_SX_TTL_FPT (((REG32(ADR_GEMINIA_SYN_TTL)) & 0x0000000c ) >> 2)
+#define GET_RG_GEMINIA_SX_TTL_CPT (((REG32(ADR_GEMINIA_SYN_TTL)) & 0x00000030 ) >> 4)
+#define GET_RG_GEMINIA_SX_TTL_ACCUM (((REG32(ADR_GEMINIA_SYN_TTL)) & 0x00000180 ) >> 7)
+#define GET_RG_GEMINIA_SX_TTL_SUB (((REG32(ADR_GEMINIA_SYN_TTL)) & 0x00000c00 ) >> 10)
+#define GET_RG_GEMINIA_SX_TTL_SUB_INV (((REG32(ADR_GEMINIA_SYN_TTL)) & 0x00001000 ) >> 12)
+#define GET_RG_GEMINIA_SX_TTL_VH (((REG32(ADR_GEMINIA_SYN_TTL)) & 0x0000c000 ) >> 14)
+#define GET_RG_GEMINIA_SX_TTL_VL (((REG32(ADR_GEMINIA_SYN_TTL)) & 0x00030000 ) >> 16)
+#define GET_RG_GEMINIA_SX_LPF_VTUNE_TEST (((REG32(ADR_GEMINIA_SYN_TTL)) & 0x00080000 ) >> 19)
+#define GET_RG_GEMINIA_DP_BBPLL_PD (((REG32(ADR_GEMINIA_DPLL_TOP_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_GEMINIA_DP_BBPLL_BP (((REG32(ADR_GEMINIA_DPLL_TOP_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_RG_GEMINIA_EN_DP_MANUAL (((REG32(ADR_GEMINIA_DPLL_TOP_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_RG_GEMINIA_DP_FREF_DOUB (((REG32(ADR_GEMINIA_DPLL_TOP_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_RG_GEMINIA_DP_DAC320_DIVBY2 (((REG32(ADR_GEMINIA_DPLL_TOP_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_RG_GEMINIA_DP_ADC320_DIVBY2_BT (((REG32(ADR_GEMINIA_DPLL_TOP_REGISTER)) & 0x00000020 ) >> 5)
+#define GET_RG_GEMINIA_DP_ADC320_DIVBY2_WF (((REG32(ADR_GEMINIA_DPLL_TOP_REGISTER)) & 0x00000040 ) >> 6)
+#define GET_RG_GEMINIA_EN_DPL_MOD (((REG32(ADR_GEMINIA_DPLL_TOP_REGISTER)) & 0x00000100 ) >> 8)
+#define GET_RG_GEMINIA_DPL_MOD_ORDER (((REG32(ADR_GEMINIA_DPLL_TOP_REGISTER)) & 0x00000600 ) >> 9)
+#define GET_RG_GEMINIA_DP_REFDIV (((REG32(ADR_GEMINIA_DPLL_TOP_REGISTER)) & 0x0003f800 ) >> 11)
+#define GET_RG_GEMINIA_DP_FODIV (((REG32(ADR_GEMINIA_DPLL_TOP_REGISTER)) & 0x01fc0000 ) >> 18)
+#define GET_RG_GEMINIA_EN_LDO_DP_BYP (((REG32(ADR_GEMINIA_DPLL_TOP_REGISTER)) & 0x02000000 ) >> 25)
+#define GET_RG_GEMINIA_EN_LDO_DP_IQUP (((REG32(ADR_GEMINIA_DPLL_TOP_REGISTER)) & 0x04000000 ) >> 26)
+#define GET_RG_GEMINIA_DP_OD_TEST (((REG32(ADR_GEMINIA_DPLL_TOP_REGISTER)) & 0x08000000 ) >> 27)
+#define GET_RG_GEMINIA_DP_BBPLL_TESTSEL (((REG32(ADR_GEMINIA_DPLL_TOP_REGISTER)) & 0x70000000 ) >> 28)
+#define GET_RG_GEMINIA_DP_BBPLL_ICP (((REG32(ADR_GEMINIA_DPLL_CKT_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_GEMINIA_DP_BBPLL_IDUAL (((REG32(ADR_GEMINIA_DPLL_CKT_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_GEMINIA_DP_CP_IOSTPOL (((REG32(ADR_GEMINIA_DPLL_CKT_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_RG_GEMINIA_DP_CP_IOST (((REG32(ADR_GEMINIA_DPLL_CKT_REGISTER)) & 0x00000060 ) >> 5)
+#define GET_RG_GEMINIA_DP_PFD_PFDSEL (((REG32(ADR_GEMINIA_DPLL_CKT_REGISTER)) & 0x00000080 ) >> 7)
+#define GET_RG_GEMINIA_DP_BBPLL_PFD_DLY (((REG32(ADR_GEMINIA_DPLL_CKT_REGISTER)) & 0x00000300 ) >> 8)
+#define GET_RG_GEMINIA_DP_RP (((REG32(ADR_GEMINIA_DPLL_CKT_REGISTER)) & 0x00003800 ) >> 11)
+#define GET_RG_GEMINIA_DP_RHP (((REG32(ADR_GEMINIA_DPLL_CKT_REGISTER)) & 0x0000c000 ) >> 14)
+#define GET_RG_GEMINIA_EN_DP_VT_MON (((REG32(ADR_GEMINIA_DPLL_CKT_REGISTER)) & 0x00020000 ) >> 17)
+#define GET_RG_GEMINIA_DP_VT_TH_HI (((REG32(ADR_GEMINIA_DPLL_CKT_REGISTER)) & 0x000c0000 ) >> 18)
+#define GET_RG_GEMINIA_DP_VT_TH_LO (((REG32(ADR_GEMINIA_DPLL_CKT_REGISTER)) & 0x00300000 ) >> 20)
+#define GET_RG_GEMINIA_DP_BBPLL_BS (((REG32(ADR_GEMINIA_DPLL_CKT_REGISTER)) & 0x1f800000 ) >> 23)
+#define GET_RG_GEMINIA_DP_BBPLL_SDM_EDGE (((REG32(ADR_GEMINIA_DPLL_CKT_REGISTER)) & 0x80000000 ) >> 31)
+#define GET_RG_GEMINIA_DPL_RFCTRL_F (((REG32(ADR_GEMINIA_DPLL_FB_DIVISION_REGISTERS)) & 0x00ffffff ) >> 0)
+#define GET_RG_GEMINIA_DPL_RFCTRL_CH (((REG32(ADR_GEMINIA_DPLL_FB_DIVISION_REGISTERS)) & 0xff000000 ) >> 24)
+#define GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG15 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER1)) & 0x0000003f ) >> 0)
+#define GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG15 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER1)) & 0x00003f00 ) >> 8)
+#define GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG14 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER1)) & 0x003f0000 ) >> 16)
+#define GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG14 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER1)) & 0x3f000000 ) >> 24)
+#define GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG13 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER2)) & 0x0000003f ) >> 0)
+#define GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG13 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER2)) & 0x00003f00 ) >> 8)
+#define GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG12 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER2)) & 0x003f0000 ) >> 16)
+#define GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG12 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER2)) & 0x3f000000 ) >> 24)
+#define GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG11 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER3)) & 0x0000003f ) >> 0)
+#define GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG11 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER3)) & 0x00003f00 ) >> 8)
+#define GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG10 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER3)) & 0x003f0000 ) >> 16)
+#define GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG10 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER3)) & 0x3f000000 ) >> 24)
+#define GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG9 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER4)) & 0x0000003f ) >> 0)
+#define GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG9 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER4)) & 0x00003f00 ) >> 8)
+#define GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG8 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER4)) & 0x003f0000 ) >> 16)
+#define GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG8 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER4)) & 0x3f000000 ) >> 24)
+#define GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG7 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER5)) & 0x0000003f ) >> 0)
+#define GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG7 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER5)) & 0x00003f00 ) >> 8)
+#define GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG6 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER5)) & 0x003f0000 ) >> 16)
+#define GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG6 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER5)) & 0x3f000000 ) >> 24)
+#define GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG5 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER6)) & 0x0000003f ) >> 0)
+#define GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG5 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER6)) & 0x00003f00 ) >> 8)
+#define GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG4 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER6)) & 0x003f0000 ) >> 16)
+#define GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG4 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER6)) & 0x3f000000 ) >> 24)
+#define GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG3 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER7)) & 0x0000003f ) >> 0)
+#define GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG3 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER7)) & 0x00003f00 ) >> 8)
+#define GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG2 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER7)) & 0x003f0000 ) >> 16)
+#define GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG2 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER7)) & 0x3f000000 ) >> 24)
+#define GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG1 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER8)) & 0x0000003f ) >> 0)
+#define GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG1 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER8)) & 0x00003f00 ) >> 8)
+#define GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG0 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER8)) & 0x003f0000 ) >> 16)
+#define GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG0 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER8)) & 0x3f000000 ) >> 24)
+#define GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG15 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER9)) & 0x0000003f ) >> 0)
+#define GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG15 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER9)) & 0x00003f00 ) >> 8)
+#define GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG14 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER9)) & 0x003f0000 ) >> 16)
+#define GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG14 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER9)) & 0x3f000000 ) >> 24)
+#define GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG13 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER10)) & 0x0000003f ) >> 0)
+#define GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG13 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER10)) & 0x00003f00 ) >> 8)
+#define GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG12 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER10)) & 0x003f0000 ) >> 16)
+#define GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG12 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER10)) & 0x3f000000 ) >> 24)
+#define GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG11 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER11)) & 0x0000003f ) >> 0)
+#define GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG11 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER11)) & 0x00003f00 ) >> 8)
+#define GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG10 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER11)) & 0x003f0000 ) >> 16)
+#define GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG10 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER11)) & 0x3f000000 ) >> 24)
+#define GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG9 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER12)) & 0x0000003f ) >> 0)
+#define GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG9 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER12)) & 0x00003f00 ) >> 8)
+#define GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG8 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER12)) & 0x003f0000 ) >> 16)
+#define GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG8 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER12)) & 0x3f000000 ) >> 24)
+#define GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG7 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER13)) & 0x0000003f ) >> 0)
+#define GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG7 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER13)) & 0x00003f00 ) >> 8)
+#define GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG6 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER13)) & 0x003f0000 ) >> 16)
+#define GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG6 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER13)) & 0x3f000000 ) >> 24)
+#define GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG5 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER14)) & 0x0000003f ) >> 0)
+#define GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG5 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER14)) & 0x00003f00 ) >> 8)
+#define GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG4 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER14)) & 0x003f0000 ) >> 16)
+#define GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG4 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER14)) & 0x3f000000 ) >> 24)
+#define GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG3 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER15)) & 0x0000003f ) >> 0)
+#define GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG3 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER15)) & 0x00003f00 ) >> 8)
+#define GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG2 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER15)) & 0x003f0000 ) >> 16)
+#define GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG2 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER15)) & 0x3f000000 ) >> 24)
+#define GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG1 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER16)) & 0x0000003f ) >> 0)
+#define GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG1 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER16)) & 0x00003f00 ) >> 8)
+#define GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG0 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER16)) & 0x003f0000 ) >> 16)
+#define GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG0 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER16)) & 0x3f000000 ) >> 24)
+#define GET_RG_GEMINIA_IDACAI_TZ0_COARSE4 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER17)) & 0x0000003f ) >> 0)
+#define GET_RG_GEMINIA_IDACAQ_TZ0_COARSE4 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER17)) & 0x00003f00 ) >> 8)
+#define GET_RG_GEMINIA_IDACAI_TZ0_COARSE3 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER17)) & 0x003f0000 ) >> 16)
+#define GET_RG_GEMINIA_IDACAQ_TZ0_COARSE3 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER17)) & 0x3f000000 ) >> 24)
+#define GET_RG_GEMINIA_IDACAI_TZ0_COARSE2 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER18)) & 0x0000003f ) >> 0)
+#define GET_RG_GEMINIA_IDACAQ_TZ0_COARSE2 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER18)) & 0x00003f00 ) >> 8)
+#define GET_RG_GEMINIA_IDACAI_TZ0_COARSE1 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER18)) & 0x003f0000 ) >> 16)
+#define GET_RG_GEMINIA_IDACAQ_TZ0_COARSE1 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER18)) & 0x3f000000 ) >> 24)
+#define GET_RG_GEMINIA_IDACAI_TZ0_COARSE0 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER19)) & 0x0000003f ) >> 0)
+#define GET_RG_GEMINIA_IDACAQ_TZ0_COARSE0 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER19)) & 0x00003f00 ) >> 8)
+#define GET_RG_GEMINIA_IDACAI_TZ1_COARSE4 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER20)) & 0x0000003f ) >> 0)
+#define GET_RG_GEMINIA_IDACAQ_TZ1_COARSE4 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER20)) & 0x00003f00 ) >> 8)
+#define GET_RG_GEMINIA_IDACAI_TZ1_COARSE3 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER20)) & 0x003f0000 ) >> 16)
+#define GET_RG_GEMINIA_IDACAQ_TZ1_COARSE3 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER20)) & 0x3f000000 ) >> 24)
+#define GET_RG_GEMINIA_IDACAI_TZ1_COARSE2 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER21)) & 0x0000003f ) >> 0)
+#define GET_RG_GEMINIA_IDACAQ_TZ1_COARSE2 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER21)) & 0x00003f00 ) >> 8)
+#define GET_RG_GEMINIA_IDACAI_TZ1_COARSE1 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER21)) & 0x003f0000 ) >> 16)
+#define GET_RG_GEMINIA_IDACAQ_TZ1_COARSE1 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER21)) & 0x3f000000 ) >> 24)
+#define GET_RG_GEMINIA_IDACAI_TZ1_COARSE0 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER22)) & 0x0000003f ) >> 0)
+#define GET_RG_GEMINIA_IDACAQ_TZ1_COARSE0 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER22)) & 0x00003f00 ) >> 8)
+#define GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG15 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER1)) & 0x0000003f ) >> 0)
+#define GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG15 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER1)) & 0x00003f00 ) >> 8)
+#define GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG14 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER1)) & 0x003f0000 ) >> 16)
+#define GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG14 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER1)) & 0x3f000000 ) >> 24)
+#define GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG13 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER2)) & 0x0000003f ) >> 0)
+#define GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG13 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER2)) & 0x00003f00 ) >> 8)
+#define GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG12 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER2)) & 0x003f0000 ) >> 16)
+#define GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG12 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER2)) & 0x3f000000 ) >> 24)
+#define GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG11 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER3)) & 0x0000003f ) >> 0)
+#define GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG11 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER3)) & 0x00003f00 ) >> 8)
+#define GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG10 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER3)) & 0x003f0000 ) >> 16)
+#define GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG10 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER3)) & 0x3f000000 ) >> 24)
+#define GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG9 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER4)) & 0x0000003f ) >> 0)
+#define GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG9 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER4)) & 0x00003f00 ) >> 8)
+#define GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG8 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER4)) & 0x003f0000 ) >> 16)
+#define GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG8 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER4)) & 0x3f000000 ) >> 24)
+#define GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG7 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER5)) & 0x0000003f ) >> 0)
+#define GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG7 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER5)) & 0x00003f00 ) >> 8)
+#define GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG6 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER5)) & 0x003f0000 ) >> 16)
+#define GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG6 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER5)) & 0x3f000000 ) >> 24)
+#define GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG5 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER6)) & 0x0000003f ) >> 0)
+#define GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG5 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER6)) & 0x00003f00 ) >> 8)
+#define GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG4 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER6)) & 0x003f0000 ) >> 16)
+#define GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG4 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER6)) & 0x3f000000 ) >> 24)
+#define GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG3 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER7)) & 0x0000003f ) >> 0)
+#define GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG3 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER7)) & 0x00003f00 ) >> 8)
+#define GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG2 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER7)) & 0x003f0000 ) >> 16)
+#define GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG2 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER7)) & 0x3f000000 ) >> 24)
+#define GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG1 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER8)) & 0x0000003f ) >> 0)
+#define GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG1 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER8)) & 0x00003f00 ) >> 8)
+#define GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG0 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER8)) & 0x003f0000 ) >> 16)
+#define GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG0 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER8)) & 0x3f000000 ) >> 24)
+#define GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG15 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER9)) & 0x0000003f ) >> 0)
+#define GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG15 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER9)) & 0x00003f00 ) >> 8)
+#define GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG14 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER9)) & 0x003f0000 ) >> 16)
+#define GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG14 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER9)) & 0x3f000000 ) >> 24)
+#define GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG13 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER10)) & 0x0000003f ) >> 0)
+#define GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG13 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER10)) & 0x00003f00 ) >> 8)
+#define GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG12 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER10)) & 0x003f0000 ) >> 16)
+#define GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG12 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER10)) & 0x3f000000 ) >> 24)
+#define GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG11 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER11)) & 0x0000003f ) >> 0)
+#define GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG11 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER11)) & 0x00003f00 ) >> 8)
+#define GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG10 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER11)) & 0x003f0000 ) >> 16)
+#define GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG10 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER11)) & 0x3f000000 ) >> 24)
+#define GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG9 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER12)) & 0x0000003f ) >> 0)
+#define GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG9 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER12)) & 0x00003f00 ) >> 8)
+#define GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG8 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER12)) & 0x003f0000 ) >> 16)
+#define GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG8 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER12)) & 0x3f000000 ) >> 24)
+#define GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG7 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER13)) & 0x0000003f ) >> 0)
+#define GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG7 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER13)) & 0x00003f00 ) >> 8)
+#define GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG6 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER13)) & 0x003f0000 ) >> 16)
+#define GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG6 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER13)) & 0x3f000000 ) >> 24)
+#define GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG5 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER14)) & 0x0000003f ) >> 0)
+#define GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG5 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER14)) & 0x00003f00 ) >> 8)
+#define GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG4 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER14)) & 0x003f0000 ) >> 16)
+#define GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG4 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER14)) & 0x3f000000 ) >> 24)
+#define GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG3 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER15)) & 0x0000003f ) >> 0)
+#define GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG3 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER15)) & 0x00003f00 ) >> 8)
+#define GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG2 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER15)) & 0x003f0000 ) >> 16)
+#define GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG2 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER15)) & 0x3f000000 ) >> 24)
+#define GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG1 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER16)) & 0x0000003f ) >> 0)
+#define GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG1 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER16)) & 0x00003f00 ) >> 8)
+#define GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG0 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER16)) & 0x003f0000 ) >> 16)
+#define GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG0 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER16)) & 0x3f000000 ) >> 24)
+#define GET_RG_GEMINIA_SX_DELAY (((REG32(ADR_GEMINIA_MODE_DECODER_TIMER_REGISTER1)) & 0x0000000f ) >> 0)
+#define GET_RG_GEMINIA_TXDAC_DELAY (((REG32(ADR_GEMINIA_MODE_DECODER_TIMER_REGISTER1)) & 0x000000f0 ) >> 4)
+#define GET_RG_GEMINIA_TXRF_DELAY (((REG32(ADR_GEMINIA_MODE_DECODER_TIMER_REGISTER1)) & 0x00000f00 ) >> 8)
+#define GET_RG_GEMINIA_TXPA_DELAY (((REG32(ADR_GEMINIA_MODE_DECODER_TIMER_REGISTER1)) & 0x0000f000 ) >> 12)
+#define GET_RG_GEMINIA_RXRF_DELAY (((REG32(ADR_GEMINIA_MODE_DECODER_TIMER_REGISTER1)) & 0x000f0000 ) >> 16)
+#define GET_RG_GEMINIA_TXBTPA_DELAY (((REG32(ADR_GEMINIA_MODE_DECODER_TIMER_REGISTER1)) & 0x00f00000 ) >> 20)
+#define GET_RG_GEMINIA_TXDAC_T2R_DELAY (((REG32(ADR_GEMINIA_WIFI_T2R_TIMER_REGISTER)) & 0x0000001f ) >> 0)
+#define GET_RG_GEMINIA_TXRF_T2R_DELAY (((REG32(ADR_GEMINIA_WIFI_T2R_TIMER_REGISTER)) & 0x00001f00 ) >> 8)
+#define GET_RG_GEMINIA_TXPA_T2R_DELAY (((REG32(ADR_GEMINIA_WIFI_T2R_TIMER_REGISTER)) & 0x001f0000 ) >> 16)
+#define GET_RG_GEMINIA_RXRF_T2R_DELAY (((REG32(ADR_GEMINIA_WIFI_T2R_TIMER_REGISTER)) & 0x1f000000 ) >> 24)
+#define GET_RG_GEMINIA_TXDAC_R2T_DELAY (((REG32(ADR_GEMINIA_WIFI_R2T_TIMER_REGISTER)) & 0x0000001f ) >> 0)
+#define GET_RG_GEMINIA_TXRF_R2T_DELAY (((REG32(ADR_GEMINIA_WIFI_R2T_TIMER_REGISTER)) & 0x00001f00 ) >> 8)
+#define GET_RG_GEMINIA_TXPA_R2T_DELAY (((REG32(ADR_GEMINIA_WIFI_R2T_TIMER_REGISTER)) & 0x001f0000 ) >> 16)
+#define GET_RG_GEMINIA_RXRF_R2T_DELAY (((REG32(ADR_GEMINIA_WIFI_R2T_TIMER_REGISTER)) & 0x1f000000 ) >> 24)
+#define GET_RG_GEMINIA_WF_RX_DCCAL_DELAY (((REG32(ADR_GEMINIA_CALIBRATION_TIMER_REGISTER)) & 0x00000007 ) >> 0)
+#define GET_RG_GEMINIA_BT_RX_DCCAL_DELAY (((REG32(ADR_GEMINIA_CALIBRATION_TIMER_REGISTER)) & 0x00000070 ) >> 4)
+#define GET_RG_GEMINIA_RX_RCCAL_DELAY (((REG32(ADR_GEMINIA_CALIBRATION_TIMER_REGISTER)) & 0x00000700 ) >> 8)
+#define GET_RG_GEMINIA_TX_LOCAL_DELAY (((REG32(ADR_GEMINIA_CALIBRATION_TIMER_REGISTER)) & 0x00007000 ) >> 12)
+#define GET_RG_GEMINIA_TX_IQCAL_DELAY (((REG32(ADR_GEMINIA_CALIBRATION_TIMER_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_GEMINIA_RX_IQCAL_DELAY (((REG32(ADR_GEMINIA_CALIBRATION_TIMER_REGISTER)) & 0x00700000 ) >> 20)
+#define GET_RG_GEMINIA_PGAG_RCCAL (((REG32(ADR_GEMINIA_CALIBRATION_GAIN_REGISTER0)) & 0x0000000f ) >> 0)
+#define GET_RG_GEMINIA_PGAG_TXCAL (((REG32(ADR_GEMINIA_CALIBRATION_GAIN_REGISTER0)) & 0x000000f0 ) >> 4)
+#define GET_RG_GEMINIA_TX_GAIN_TXCAL (((REG32(ADR_GEMINIA_CALIBRATION_GAIN_REGISTER0)) & 0x00007f00 ) >> 8)
+#define GET_RG_GEMINIA_RFG_RXIQCAL (((REG32(ADR_GEMINIA_CALIBRATION_GAIN_REGISTER0)) & 0x00030000 ) >> 16)
+#define GET_RG_GEMINIA_PGAG_RXIQCAL (((REG32(ADR_GEMINIA_CALIBRATION_GAIN_REGISTER0)) & 0x003c0000 ) >> 18)
+#define GET_RG_GEMINIA_TX_GAIN_RXIQCAL (((REG32(ADR_GEMINIA_CALIBRATION_GAIN_REGISTER0)) & 0x1fc00000 ) >> 22)
+#define GET_RG_GEMINIA_RFG_DPDCAL (((REG32(ADR_GEMINIA_CALIBRATION_GAIN_REGISTER1)) & 0x00000003 ) >> 0)
+#define GET_RG_GEMINIA_PGAG_DPDCAL (((REG32(ADR_GEMINIA_CALIBRATION_GAIN_REGISTER1)) & 0x0000003c ) >> 2)
+#define GET_RG_GEMINIA_TX_GAIN_DPDCAL (((REG32(ADR_GEMINIA_CALIBRATION_GAIN_REGISTER1)) & 0x00001fc0 ) >> 6)
+#define GET_DB_GEMINIA_AD_ADC_I_OUT (((REG32(ADR_GEMINIA_READ_ONLY_FLAGS_ADC)) & 0x000003ff ) >> 0)
+#define GET_DB_GEMINIA_AD_ADC_Q_OUT (((REG32(ADR_GEMINIA_READ_ONLY_FLAGS_ADC)) & 0x000ffc00 ) >> 10)
+#define GET_DB_GEMINIA_AD_RX_RSSIADC (((REG32(ADR_GEMINIA_READ_ONLY_FLAGS_ADC)) & 0x00f00000 ) >> 20)
+#define GET_DB_GEMINIA_DA_SARADC_BIT (((REG32(ADR_GEMINIA_READ_ONLY_FLAGS_ADC)) & 0x3f000000 ) >> 24)
+#define GET_GEMINIA_SAR_ADC_FSM_RDY (((REG32(ADR_GEMINIA_READ_ONLY_FLAGS_ADC)) & 0x40000000 ) >> 30)
+#define GET_DB_GEMINIA_DA_SX_SUB_SEL (((REG32(ADR_GEMINIA_READ_ONLY_FLAGS_SX1)) & 0x000000ff ) >> 0)
+#define GET_DB_GEMINIA_DA_SX_VCO_ISEL (((REG32(ADR_GEMINIA_READ_ONLY_FLAGS_SX1)) & 0x00001e00 ) >> 9)
+#define GET_DB_GEMINIA_VO_AAC_COMPOUT (((REG32(ADR_GEMINIA_READ_ONLY_FLAGS_SX1)) & 0x00002000 ) >> 13)
+#define GET_DB_GEMINIA_SX_TTL_VT_DET (((REG32(ADR_GEMINIA_READ_ONLY_FLAGS_SX1)) & 0x00018000 ) >> 15)
+#define GET_DB_GEMINIA_AD_DP_VT_MON_Q (((REG32(ADR_GEMINIA_READ_ONLY_FLAGS_SX1)) & 0x60000000 ) >> 29)
+#define GET_DB_GEMINIA_SX_SBCAL_NCOUNT (((REG32(ADR_GEMINIA_READ_ONLY_FLAGS_SX2)) & 0x0000ffff ) >> 0)
+#define GET_DB_GEMINIA_SX_SBCAL_NTARGET (((REG32(ADR_GEMINIA_READ_ONLY_FLAGS_SX2)) & 0xffff0000 ) >> 16)
+#define GET_RG_GEMINIA_NFRAC_DELTA (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R0)) & 0x00ffffff ) >> 0)
+#define GET_RG_GEMINIA_40M_MODE (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R0)) & 0x01000000 ) >> 24)
+#define GET_RG_GEMINIA_LO_UP_CH (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R0)) & 0x10000000 ) >> 28)
+#define GET_RG_GEMINIA_RX_IQ_ALPHA (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R2)) & 0x0000001f ) >> 0)
+#define GET_RG_GEMINIA_RX_IQ_THETA (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R2)) & 0x00001f00 ) >> 8)
+#define GET_RG_GEMINIA_RX_IQ_MANUAL (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R2)) & 0x00010000 ) >> 16)
+#define GET_RG_GEMINIA_RXIQ_NOSHRK (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R2)) & 0x00020000 ) >> 17)
+#define GET_RG_GEMINIA_RX_RSSIADC_TH (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R2)) & 0x00f00000 ) >> 20)
+#define GET_RG_GEMINIA_RSSI_EDGE_SEL (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R2)) & 0x04000000 ) >> 26)
+#define GET_RG_GEMINIA_ADC_EDGE_SEL (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R2)) & 0x08000000 ) >> 27)
+#define GET_RG_GEMINIA_Q_INV (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R2)) & 0x10000000 ) >> 28)
+#define GET_RG_GEMINIA_I_INV (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R2)) & 0x20000000 ) >> 29)
+#define GET_RG_GEMINIA_IQ_SWAP (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R2)) & 0x40000000 ) >> 30)
+#define GET_RG_GEMINIA_SIGN_SWAP (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R2)) & 0x80000000 ) >> 31)
+#define GET_RG_GEMINIA_TX_IQ_ALPHA (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R3)) & 0x0000001f ) >> 0)
+#define GET_RG_GEMINIA_TX_IQ_THETA (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R3)) & 0x00001f00 ) >> 8)
+#define GET_RG_GEMINIA_TX_IQ_MANUAL (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R3)) & 0x00010000 ) >> 16)
+#define GET_RG_GEMINIA_TXIQ_NOSHRK (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R3)) & 0x00020000 ) >> 17)
+#define GET_RG_GEMINIA_TX_FREQ_OFFSET (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R4)) & 0x0000ffff ) >> 0)
+#define GET_RG_GEMINIA_TONE_SCALE (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R4)) & 0x01ff0000 ) >> 16)
+#define GET_RG_GEMINIA_TX_UP8X_MAN_EN (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R4)) & 0x08000000 ) >> 27)
+#define GET_RG_GEMINIA_DIS_DAC_OFFSET (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R4)) & 0x10000000 ) >> 28)
+#define GET_RG_GEMINIA_EXT_DAC_EN (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R4)) & 0x20000000 ) >> 29)
+#define GET_RG_GEMINIA_DPLL_CLK320BY2 (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R4)) & 0x40000000 ) >> 30)
+#define GET_RG_GEMINIA_CBW_20_40 (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R4)) & 0x80000000 ) >> 31)
+#define GET_RG_GEMINIA_DAC_DC_Q (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R5)) & 0x000003ff ) >> 0)
+#define GET_RG_GEMINIA_DAC_DC_I (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R5)) & 0x03ff0000 ) >> 16)
+#define GET_RG_GEMINIA_DAC_Q_SET (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R6)) & 0x000003ff ) >> 0)
+#define GET_RG_GEMINIA_DAC_MAN_Q_EN (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R6)) & 0x00001000 ) >> 12)
+#define GET_RG_GEMINIA_DAC_I_SET (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R6)) & 0x03ff0000 ) >> 16)
+#define GET_RG_GEMINIA_DAC_MAN_I_EN (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R6)) & 0x10000000 ) >> 28)
+#define GET_RG_GEMINIA_BW20_HB_COEF_01 (((REG32(ADR_GEMINIA_TX_UP8X_COEF_R0)) & 0x00001fff ) >> 0)
+#define GET_RG_GEMINIA_BW20_HB_COEF_00 (((REG32(ADR_GEMINIA_TX_UP8X_COEF_R0)) & 0x1fff0000 ) >> 16)
+#define GET_RG_GEMINIA_BW20_HB_COEF_03 (((REG32(ADR_GEMINIA_TX_UP8X_COEF_R1)) & 0x00001fff ) >> 0)
+#define GET_RG_GEMINIA_BW20_HB_COEF_02 (((REG32(ADR_GEMINIA_TX_UP8X_COEF_R1)) & 0x1fff0000 ) >> 16)
+#define GET_RG_GEMINIA_BW20_HB_COEF_05 (((REG32(ADR_GEMINIA_TX_UP8X_COEF_R2)) & 0x00001fff ) >> 0)
+#define GET_RG_GEMINIA_BW20_HB_COEF_04 (((REG32(ADR_GEMINIA_TX_UP8X_COEF_R2)) & 0x1fff0000 ) >> 16)
+#define GET_RG_GEMINIA_BW20_HB_COEF_07 (((REG32(ADR_GEMINIA_TX_UP8X_COEF_R3)) & 0x00001fff ) >> 0)
+#define GET_RG_GEMINIA_BW20_HB_COEF_06 (((REG32(ADR_GEMINIA_TX_UP8X_COEF_R3)) & 0x1fff0000 ) >> 16)
+#define GET_RG_GEMINIA_BW20_HB_COEF_09 (((REG32(ADR_GEMINIA_TX_UP8X_COEF_R4)) & 0x00001fff ) >> 0)
+#define GET_RG_GEMINIA_BW20_HB_COEF_08 (((REG32(ADR_GEMINIA_TX_UP8X_COEF_R4)) & 0x1fff0000 ) >> 16)
+#define GET_RG_GEMINIA_BW20_HB_COEF_11 (((REG32(ADR_GEMINIA_TX_UP8X_COEF_R5)) & 0x00001fff ) >> 0)
+#define GET_RG_GEMINIA_BW20_HB_COEF_10 (((REG32(ADR_GEMINIA_TX_UP8X_COEF_R5)) & 0x1fff0000 ) >> 16)
+#define GET_RG_GEMINIA_PHASE_STEP_VALUE (((REG32(ADR_GEMINIA_RF_D_CAL_TOP_R0)) & 0x0000ffff ) >> 0)
+#define GET_RG_GEMINIA_PHASE_MANUAL (((REG32(ADR_GEMINIA_RF_D_CAL_TOP_R0)) & 0x00010000 ) >> 16)
+#define GET_RG_GEMINIA_ALPHA_SEL (((REG32(ADR_GEMINIA_RF_D_CAL_TOP_R0)) & 0x00300000 ) >> 20)
+#define GET_RG_GEMINIA_SPECTRUM_BW (((REG32(ADR_GEMINIA_RF_D_CAL_TOP_R0)) & 0x03000000 ) >> 24)
+#define GET_RG_GEMINIA_SPECTRUM_EN (((REG32(ADR_GEMINIA_RF_D_CAL_TOP_R0)) & 0x10000000 ) >> 28)
+#define GET_RG_GEMINIA_RX_RCCAL_TARG (((REG32(ADR_GEMINIA_RF_D_CAL_TOP_R1)) & 0x000003ff ) >> 0)
+#define GET_RG_GEMINIA_RX_DC_POLAR_INV (((REG32(ADR_GEMINIA_RF_D_CAL_TOP_R1)) & 0x00001000 ) >> 12)
+#define GET_RG_GEMINIA_RCCAL_POLAR_INV (((REG32(ADR_GEMINIA_RF_D_CAL_TOP_R1)) & 0x00002000 ) >> 13)
+#define GET_RO_GEMINIA_WF_DCCAL_DONE (((REG32(ADR_GEMINIA_RF_D_CAL_TOP_R1)) & 0x00010000 ) >> 16)
+#define GET_RO_GEMINIA_BT_DCCAL_DONE (((REG32(ADR_GEMINIA_RF_D_CAL_TOP_R1)) & 0x00020000 ) >> 17)
+#define GET_RO_GEMINIA_RCCAL_DONE (((REG32(ADR_GEMINIA_RF_D_CAL_TOP_R1)) & 0x00040000 ) >> 18)
+#define GET_RO_GEMINIA_TXDC_DONE (((REG32(ADR_GEMINIA_RF_D_CAL_TOP_R1)) & 0x00080000 ) >> 19)
+#define GET_RO_GEMINIA_TXIQ_DONE (((REG32(ADR_GEMINIA_RF_D_CAL_TOP_R1)) & 0x00100000 ) >> 20)
+#define GET_RO_GEMINIA_RXIQ_DONE (((REG32(ADR_GEMINIA_RF_D_CAL_TOP_R1)) & 0x00200000 ) >> 21)
+#define GET_RG_GEMINIA_PHASE_17P5M (((REG32(ADR_GEMINIA_RF_D_CAL_TOP_R2)) & 0x0000ffff ) >> 0)
+#define GET_RG_GEMINIA_PHASE_2P5M (((REG32(ADR_GEMINIA_RF_D_CAL_TOP_R2)) & 0xffff0000 ) >> 16)
+#define GET_RG_GEMINIA_PHASE_RXIQ_1M (((REG32(ADR_GEMINIA_RF_D_CAL_TOP_R3)) & 0x0000ffff ) >> 0)
+#define GET_RG_GEMINIA_PHASE_1M (((REG32(ADR_GEMINIA_RF_D_CAL_TOP_R3)) & 0xffff0000 ) >> 16)
+#define GET_RG_GEMINIA_EN_LDO_XO_BYP (((REG32(ADR_GEMINIA_PMU_REG_1)) & 0x00000001 ) >> 0)
+#define GET_RG_GEMINIA_EN_LDO_XO_IQUP (((REG32(ADR_GEMINIA_PMU_REG_1)) & 0x00000002 ) >> 1)
+#define GET_RG_GEMINIA_XO_LDO_LEVEL (((REG32(ADR_GEMINIA_PMU_REG_1)) & 0x0000001c ) >> 2)
+#define GET_RG_GEMINIA_XO_CBANKI (((REG32(ADR_GEMINIA_PMU_REG_1)) & 0x00001fe0 ) >> 5)
+#define GET_RG_GEMINIA_XO_CBANKO (((REG32(ADR_GEMINIA_PMU_REG_1)) & 0x001fe000 ) >> 13)
+#define GET_RG_GEMINIA_EN_FDB (((REG32(ADR_GEMINIA_PMU_REG_1)) & 0x00200000 ) >> 21)
+#define GET_RG_GEMINIA_FDB_BYPASS (((REG32(ADR_GEMINIA_PMU_REG_1)) & 0x00400000 ) >> 22)
+#define GET_RG_GEMINIA_FDB_DUTY_LTH (((REG32(ADR_GEMINIA_PMU_REG_1)) & 0x01800000 ) >> 23)
+#define GET_RG_GEMINIA_EN_XOTEST (((REG32(ADR_GEMINIA_PMU_REG_1)) & 0x02000000 ) >> 25)
+#define GET_RG_GEMINIA_EN_FDB_DCC_MUAL (((REG32(ADR_GEMINIA_PMU_REG_2)) & 0x00000001 ) >> 0)
+#define GET_RG_GEMINIA_EN_FDB_DELAYC_MUAL (((REG32(ADR_GEMINIA_PMU_REG_2)) & 0x00000002 ) >> 1)
+#define GET_RG_GEMINIA_EN_FDB_DELAYF_MUAL (((REG32(ADR_GEMINIA_PMU_REG_2)) & 0x00000004 ) >> 2)
+#define GET_RG_GEMINIA_EN_FDB_PHASESWAP_MUAL (((REG32(ADR_GEMINIA_PMU_REG_2)) & 0x00000008 ) >> 3)
+#define GET_RG_GEMINIA_FDB_PHASESWAP_MUAL (((REG32(ADR_GEMINIA_PMU_REG_2)) & 0x00000010 ) >> 4)
+#define GET_RG_GEMINIA_FDB_CDELAY_MUAL (((REG32(ADR_GEMINIA_PMU_REG_2)) & 0x00000f00 ) >> 8)
+#define GET_RG_GEMINIA_FDB_FDELAY_MUAL (((REG32(ADR_GEMINIA_PMU_REG_2)) & 0x0000f000 ) >> 12)
+#define GET_RG_GEMINIA_XO_TIMMER (((REG32(ADR_GEMINIA_PMU_REG_2)) & 0x003f0000 ) >> 16)
+#define GET_RG_GEMINIA_DPL_SETTLING_TIMMER (((REG32(ADR_GEMINIA_PMU_REG_2)) & 0x00c00000 ) >> 22)
+#define GET_RG_GEMINIA_FDB_RDELAYF (((REG32(ADR_GEMINIA_PMU_REG_2)) & 0x03000000 ) >> 24)
+#define GET_RG_GEMINIA_FDB_RDELAYS (((REG32(ADR_GEMINIA_PMU_REG_2)) & 0x0c000000 ) >> 26)
+#define GET_RG_GEMINIA_FDB_RECAL_TIMMER (((REG32(ADR_GEMINIA_PMU_REG_2)) & 0x30000000 ) >> 28)
+#define GET_RG_GEMINIA_EN_FDB_RECAL (((REG32(ADR_GEMINIA_PMU_REG_2)) & 0x40000000 ) >> 30)
+#define GET_RG_GEMINIA_LOAD_RFTABLE_RDY (((REG32(ADR_GEMINIA_PMU_REG_2)) & 0x80000000 ) >> 31)
+#define GET_RG_GEMINIA_DCDC_MODE (((REG32(ADR_GEMINIA_PMU_REG_3)) & 0x00000001 ) >> 0)
+#define GET_RG_GEMINIA_BUCK_LEVEL (((REG32(ADR_GEMINIA_PMU_REG_3)) & 0x0000000e ) >> 1)
+#define GET_RG_GEMINIA_DLDO_LEVEL (((REG32(ADR_GEMINIA_PMU_REG_3)) & 0x00000070 ) >> 4)
+#define GET_RG_GEMINIA_DLDO_BOOST_IQ (((REG32(ADR_GEMINIA_PMU_REG_3)) & 0x00000100 ) >> 8)
+#define GET_RG_GEMINIA_BUCK_EN_PSM (((REG32(ADR_GEMINIA_PMU_REG_3)) & 0x00000200 ) >> 9)
+#define GET_RG_GEMINIA_BUCK_PSM_VTH (((REG32(ADR_GEMINIA_PMU_REG_3)) & 0x00000400 ) >> 10)
+#define GET_RG_GEMINIA_BUCK_VREF_SEL (((REG32(ADR_GEMINIA_PMU_REG_3)) & 0x00000800 ) >> 11)
+#define GET_RG_GEMINIA_LDO_LEVEL_EFUSE (((REG32(ADR_GEMINIA_PMU_REG_3)) & 0x00007000 ) >> 12)
+#define GET_RG_GEMINIA_EN_LDO_EFUSE (((REG32(ADR_GEMINIA_PMU_REG_3)) & 0x00010000 ) >> 16)
+#define GET_RG_GEMINIA_DCDC_PULLLOW_CON (((REG32(ADR_GEMINIA_PMU_REG_3)) & 0x00040000 ) >> 18)
+#define GET_RG_GEMINIA_DCDC_RES2_CON (((REG32(ADR_GEMINIA_PMU_REG_3)) & 0x00080000 ) >> 19)
+#define GET_RG_GEMINIA_DCDC_RES_CON (((REG32(ADR_GEMINIA_PMU_REG_3)) & 0x00100000 ) >> 20)
+#define GET_RG_GEMINIA_RTC_RS1 (((REG32(ADR_GEMINIA_PMU_REG_3)) & 0x00200000 ) >> 21)
+#define GET_RG_GEMINIA_RTC_RS2 (((REG32(ADR_GEMINIA_PMU_REG_3)) & 0x00400000 ) >> 22)
+#define GET_RG_GEMINIA_DCDC_CLK (((REG32(ADR_GEMINIA_PMU_REG_3)) & 0x03000000 ) >> 24)
+#define GET_RG_GEMINIA_RTC_OFFSET (((REG32(ADR_GEMINIA_PMU_REG_4)) & 0x000000ff ) >> 0)
+#define GET_RG_GEMINIA_RTC_CAL_TARGET_COUNT (((REG32(ADR_GEMINIA_PMU_REG_4)) & 0x000fff00 ) >> 8)
+#define GET_RG_GEMINIA_RTC_OSC_RES_SW_MANUAL (((REG32(ADR_GEMINIA_PMU_REG_4)) & 0x3ff00000 ) >> 20)
+#define GET_RG_GEMINIA_RTC_CAL_MODE (((REG32(ADR_GEMINIA_PMU_REG_4)) & 0x40000000 ) >> 30)
+#define GET_RG_GEMINIA_SEL_DPLL_CLK (((REG32(ADR_GEMINIA_PMU_REG_4)) & 0x80000000 ) >> 31)
+#define GET_RG_GEMINIA_RTC_OSC_RES_SW_MANUAL_EN (((REG32(ADR_GEMINIA_PMU_REG_5)) & 0x00000001 ) >> 0)
+#define GET_RG_GEMINIA_EN_RTC_CAL (((REG32(ADR_GEMINIA_PMU_REG_5)) & 0x00000002 ) >> 1)
+#define GET_RO_GEMINIA_RTC_OSC_RES_SW (((REG32(ADR_GEMINIA_PMU_REG_6)) & 0x03ff0000 ) >> 16)
+#define GET_RO_GEMINIA_RTC_OSC_CAL_RES_RDY (((REG32(ADR_GEMINIA_PMU_REG_6)) & 0x80000000 ) >> 31)
+#define GET_RG_GEMINIA_BT_CLK_SW (((REG32(ADR_GEMINIA_PMU_BT_CLK)) & 0x00000001 ) >> 0)
+#define GET_RG_GEMINIA_BT_CLK32K_CAL_DONE (((REG32(ADR_GEMINIA_PMU_BT_CLK)) & 0x00000002 ) >> 1)
+#define GET_RG_GEMINIA_SLEEP_WAKE_CNT (((REG32(ADR_GEMINIA_PMU_SLEEP_REG)) & 0x00ffffff ) >> 0)
+#define GET_RG_GEMINIA_PMU_ENTER_SLEEP_MODE (((REG32(ADR_GEMINIA_PMU_SLEEP_REG)) & 0x01000000 ) >> 24)
+#define GET_RG_GEMINIA_RTC_EN (((REG32(ADR_GEMINIA_PMU_RTC_REG_0)) & 0x00000001 ) >> 0)
+#define GET_RG_GEMINIA_CLK_RTC_SW (((REG32(ADR_GEMINIA_PMU_RTC_REG_0)) & 0x00000002 ) >> 1)
+#define GET_RO_GEMINIA_PMU_WAKE_TRIG_EVENT (((REG32(ADR_GEMINIA_PMU_RTC_REG_0)) & 0x00003000 ) >> 12)
+#define GET_RO_GEMINIA_RTC_TICK_CNT (((REG32(ADR_GEMINIA_PMU_RTC_REG_0)) & 0x7fff0000 ) >> 16)
+#define GET_RG_GEMINIA_RTC_INT_SEC_MASK (((REG32(ADR_GEMINIA_PMU_RTC_REG_1)) & 0x00000001 ) >> 0)
+#define GET_RG_GEMINIA_RTC_INT_ALARM_MASK (((REG32(ADR_GEMINIA_PMU_RTC_REG_1)) & 0x00000002 ) >> 1)
+#define GET_RO_GEMINIA_RTC_INT_SEC (((REG32(ADR_GEMINIA_PMU_RTC_REG_1)) & 0x00010000 ) >> 16)
+#define GET_RO_GEMINIA_RTC_INT_ALARM (((REG32(ADR_GEMINIA_PMU_RTC_REG_1)) & 0x00020000 ) >> 17)
+#define GET_RG_GEMINIA_RTC_SEC_START_CNT (((REG32(ADR_GEMINIA_PMU_RTC_REG_2)) & 0xffffffff ) >> 0)
+#define GET_RG_GEMINIA_RTC_SEC_ALARM_VALUE (((REG32(ADR_GEMINIA_PMU_RTC_REG_3)) & 0xffffffff ) >> 0)
+#define GET_RO_GEMINIA_FDB_CDELAY (((REG32(ADR_GEMINIA_PMU_FDB_REG_0)) & 0x00f00000 ) >> 20)
+#define GET_RO_GEMINIA_FDB_FDELAY (((REG32(ADR_GEMINIA_PMU_FDB_REG_0)) & 0x0f000000 ) >> 24)
+#define GET_RO_GEMINIA_FDB_PHASESWAP (((REG32(ADR_GEMINIA_PMU_FDB_REG_0)) & 0x80000000 ) >> 31)
+#define GET_RG_GEMINIA_GPIO16_DS (((REG32(ADR_GEMINIA_IO_REG_0)) & 0x00000001 ) >> 0)
+#define GET_RG_GEMINIA_GPIO16_PD (((REG32(ADR_GEMINIA_IO_REG_0)) & 0x00000002 ) >> 1)
+#define GET_RG_GEMINIA_GPIO16_OE (((REG32(ADR_GEMINIA_IO_REG_0)) & 0x00000004 ) >> 2)
+#define GET_RG_GEMINIA_GPIO17_DS (((REG32(ADR_GEMINIA_IO_REG_0)) & 0x00000010 ) >> 4)
+#define GET_RG_GEMINIA_GPIO17_PD (((REG32(ADR_GEMINIA_IO_REG_0)) & 0x00000020 ) >> 5)
+#define GET_RG_GEMINIA_GPIO17_OE (((REG32(ADR_GEMINIA_IO_REG_0)) & 0x00000040 ) >> 6)
+#define GET_RG_GEMINIA_GPIO18_DS (((REG32(ADR_GEMINIA_IO_REG_0)) & 0x00000100 ) >> 8)
+#define GET_RG_GEMINIA_GPIO18_PD (((REG32(ADR_GEMINIA_IO_REG_0)) & 0x00000200 ) >> 9)
+#define GET_RG_GEMINIA_GPIO18_OE (((REG32(ADR_GEMINIA_IO_REG_0)) & 0x00000400 ) >> 10)
+#define GET_RG_GEMINIA_GPIO19_DS (((REG32(ADR_GEMINIA_IO_REG_0)) & 0x00001000 ) >> 12)
+#define GET_RG_GEMINIA_GPIO19_PD (((REG32(ADR_GEMINIA_IO_REG_0)) & 0x00002000 ) >> 13)
+#define GET_RG_GEMINIA_GPIO19_OE (((REG32(ADR_GEMINIA_IO_REG_0)) & 0x00004000 ) >> 14)
+#define GET_RG_GEMINIA_GPIO20_DS (((REG32(ADR_GEMINIA_IO_REG_0)) & 0x00010000 ) >> 16)
+#define GET_RG_GEMINIA_GPIO20_PD (((REG32(ADR_GEMINIA_IO_REG_0)) & 0x00020000 ) >> 17)
+#define GET_RG_GEMINIA_GPIO20_OE (((REG32(ADR_GEMINIA_IO_REG_0)) & 0x00040000 ) >> 18)
+#define GET_RG_GEMINIA_SPIS_MISO_DS (((REG32(ADR_GEMINIA_IO_REG_0)) & 0x01000000 ) >> 24)
+#define GET_RG_GEMINIA_FPGA_CLK_REF_40M_DS (((REG32(ADR_GEMINIA_IO_REG_0)) & 0x10000000 ) >> 28)
+#define GET_RG_GEMINIA_FPGA_CLK_REF_40M_PD (((REG32(ADR_GEMINIA_IO_REG_0)) & 0x20000000 ) >> 29)
+#define GET_RG_GEMINIA_FPGA_CLK_REF_40M_OE (((REG32(ADR_GEMINIA_IO_REG_0)) & 0x40000000 ) >> 30)
+#define GET_RG_GEMINIA_GPIO08_DS (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x00000001 ) >> 0)
+#define GET_RG_GEMINIA_GPIO08_PD (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x00000002 ) >> 1)
+#define GET_RG_GEMINIA_GPIO08_OE (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x00000004 ) >> 2)
+#define GET_RG_GEMINIA_GPIO09_DS (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x00000010 ) >> 4)
+#define GET_RG_GEMINIA_GPIO09_PD (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x00000020 ) >> 5)
+#define GET_RG_GEMINIA_GPIO09_OE (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x00000040 ) >> 6)
+#define GET_RG_GEMINIA_GPIO10_DS (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x00000100 ) >> 8)
+#define GET_RG_GEMINIA_GPIO10_PD (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x00000200 ) >> 9)
+#define GET_RG_GEMINIA_GPIO10_OE (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x00000400 ) >> 10)
+#define GET_RG_GEMINIA_GPIO11_DS (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x00001000 ) >> 12)
+#define GET_RG_GEMINIA_GPIO11_PD (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x00002000 ) >> 13)
+#define GET_RG_GEMINIA_GPIO11_OE (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x00004000 ) >> 14)
+#define GET_RG_GEMINIA_GPIO12_DS (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x00010000 ) >> 16)
+#define GET_RG_GEMINIA_GPIO12_PD (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x00020000 ) >> 17)
+#define GET_RG_GEMINIA_GPIO12_OE (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x00040000 ) >> 18)
+#define GET_RG_GEMINIA_GPIO13_DS (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x00100000 ) >> 20)
+#define GET_RG_GEMINIA_GPIO13_PD (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x00200000 ) >> 21)
+#define GET_RG_GEMINIA_GPIO13_OE (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x00400000 ) >> 22)
+#define GET_RG_GEMINIA_GPIO14_DS (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x01000000 ) >> 24)
+#define GET_RG_GEMINIA_GPIO14_PD (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x02000000 ) >> 25)
+#define GET_RG_GEMINIA_GPIO14_OE (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x04000000 ) >> 26)
+#define GET_RG_GEMINIA_GPIO15_DS (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x10000000 ) >> 28)
+#define GET_RG_GEMINIA_GPIO15_PD (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x20000000 ) >> 29)
+#define GET_RG_GEMINIA_GPIO15_OE (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x40000000 ) >> 30)
+#define GET_RG_GEMINIA_GPIO00_DS (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x00000001 ) >> 0)
+#define GET_RG_GEMINIA_GPIO00_PD (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x00000002 ) >> 1)
+#define GET_RG_GEMINIA_GPIO00_OE (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x00000004 ) >> 2)
+#define GET_RG_GEMINIA_GPIO01_DS (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x00000010 ) >> 4)
+#define GET_RG_GEMINIA_GPIO01_PD (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x00000020 ) >> 5)
+#define GET_RG_GEMINIA_GPIO01_OE (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x00000040 ) >> 6)
+#define GET_RG_GEMINIA_GPIO02_DS (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x00000100 ) >> 8)
+#define GET_RG_GEMINIA_GPIO02_PD (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x00000200 ) >> 9)
+#define GET_RG_GEMINIA_GPIO02_OE (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x00000400 ) >> 10)
+#define GET_RG_GEMINIA_GPIO03_DS (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x00001000 ) >> 12)
+#define GET_RG_GEMINIA_GPIO03_PD (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x00002000 ) >> 13)
+#define GET_RG_GEMINIA_GPIO03_OE (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x00004000 ) >> 14)
+#define GET_RG_GEMINIA_GPIO04_DS (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x00010000 ) >> 16)
+#define GET_RG_GEMINIA_GPIO04_PD (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x00020000 ) >> 17)
+#define GET_RG_GEMINIA_GPIO04_OE (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x00040000 ) >> 18)
+#define GET_RG_GEMINIA_GPIO05_DS (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x00100000 ) >> 20)
+#define GET_RG_GEMINIA_GPIO05_PD (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x00200000 ) >> 21)
+#define GET_RG_GEMINIA_GPIO05_OE (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x00400000 ) >> 22)
+#define GET_RG_GEMINIA_GPIO06_DS (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x01000000 ) >> 24)
+#define GET_RG_GEMINIA_GPIO06_PD (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x02000000 ) >> 25)
+#define GET_RG_GEMINIA_GPIO06_OE (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x04000000 ) >> 26)
+#define GET_RG_GEMINIA_GPIO07_DS (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x10000000 ) >> 28)
+#define GET_RG_GEMINIA_GPIO07_PD (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x20000000 ) >> 29)
+#define GET_RG_GEMINIA_GPIO07_OE (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x40000000 ) >> 30)
+#define GET_RG_GEMINIA_RF_PHY_MODE_SEL (((REG32(ADR_GEMINIA_MCU_REG_0)) & 0x00000003 ) >> 0)
+#define GET_RG_GEMINIA_RF_PHY_MODE_WIFI_MAC (((REG32(ADR_GEMINIA_MCU_REG_0)) & 0x00000070 ) >> 4)
+#define GET_RG_GEMINIA_PAD_MUX_SEL (((REG32(ADR_GEMINIA_MCU_REG_0)) & 0x00000f00 ) >> 8)
+#define GET_RG_GEMINIA_MODE_LATCH_LMT (((REG32(ADR_GEMINIA_MCU_REG_0)) & 0x00007000 ) >> 12)
+#define GET_RG_GEMINIA_EXT_MCU_PWRUP (((REG32(ADR_GEMINIA_MCU_REG_0)) & 0x80000000 ) >> 31)
+#define GET_RG_GEMINIA_RAM_00 (((REG32(ADR_GEMINIA_PMU_RAM_00)) & 0xffffffff ) >> 0)
+#define GET_RG_GEMINIA_RAM_01 (((REG32(ADR_GEMINIA_PMU_RAM_01)) & 0xffffffff ) >> 0)
+#define GET_RG_GEMINIA_RAM_02 (((REG32(ADR_GEMINIA_PMU_RAM_02)) & 0xffffffff ) >> 0)
+#define GET_RG_GEMINIA_RAM_03 (((REG32(ADR_GEMINIA_PMU_RAM_03)) & 0xffffffff ) >> 0)
+#define GET_RG_GEMINIA_RAM_04 (((REG32(ADR_GEMINIA_PMU_RAM_04)) & 0xffffffff ) >> 0)
+#define GET_RG_GEMINIA_RAM_05 (((REG32(ADR_GEMINIA_PMU_RAM_05)) & 0xffffffff ) >> 0)
+#define GET_RG_GEMINIA_RAM_06 (((REG32(ADR_GEMINIA_PMU_RAM_06)) & 0xffffffff ) >> 0)
+#define GET_RG_GEMINIA_RAM_07 (((REG32(ADR_GEMINIA_PMU_RAM_07)) & 0xffffffff ) >> 0)
+#define GET_RG_GEMINIA_RAM_08 (((REG32(ADR_GEMINIA_PMU_RAM_08)) & 0xffffffff ) >> 0)
+#define GET_RG_GEMINIA_RAM_09 (((REG32(ADR_GEMINIA_PMU_RAM_09)) & 0xffffffff ) >> 0)
+#define GET_RG_GEMINIA_RAM_10 (((REG32(ADR_GEMINIA_PMU_RAM_10)) & 0xffffffff ) >> 0)
+#define GET_RG_GEMINIA_RAM_11 (((REG32(ADR_GEMINIA_PMU_RAM_11)) & 0xffffffff ) >> 0)
+#define GET_RG_GEMINIA_RAM_12 (((REG32(ADR_GEMINIA_PMU_RAM_12)) & 0xffffffff ) >> 0)
+#define GET_RG_GEMINIA_RAM_13 (((REG32(ADR_GEMINIA_PMU_RAM_13)) & 0xffffffff ) >> 0)
+#define GET_RG_GEMINIA_RAM_14 (((REG32(ADR_GEMINIA_PMU_RAM_14)) & 0xffffffff ) >> 0)
+#define GET_RG_GEMINIA_RAM_15 (((REG32(ADR_GEMINIA_PMU_RAM_15)) & 0xffffffff ) >> 0)
+#define GET_RG_GEMINIA_RAM_16 (((REG32(ADR_GEMINIA_PMU_RAM_16)) & 0xffffffff ) >> 0)
+#define GET_RG_GEMINIA_RAM_17 (((REG32(ADR_GEMINIA_PMU_RAM_17)) & 0xffffffff ) >> 0)
+#define GET_RG_GEMINIA_RAM_18 (((REG32(ADR_GEMINIA_PMU_RAM_18)) & 0xffffffff ) >> 0)
+#define GET_RG_GEMINIA_RAM_19 (((REG32(ADR_GEMINIA_PMU_RAM_19)) & 0xffffffff ) >> 0)
+#define GET_RG_GEMINIA_RAM_20 (((REG32(ADR_GEMINIA_PMU_RAM_20)) & 0xffffffff ) >> 0)
+#define GET_RG_GEMINIA_RAM_21 (((REG32(ADR_GEMINIA_PMU_RAM_21)) & 0xffffffff ) >> 0)
+#define GET_RG_GEMINIA_RAM_22 (((REG32(ADR_GEMINIA_PMU_RAM_22)) & 0xffffffff ) >> 0)
+#define GET_RG_GEMINIA_RAM_23 (((REG32(ADR_GEMINIA_PMU_RAM_23)) & 0xffffffff ) >> 0)
+#define GET_RG_GEMINIA_RAM_24 (((REG32(ADR_GEMINIA_PMU_RAM_24)) & 0xffffffff ) >> 0)
+#define GET_RG_GEMINIA_RAM_25 (((REG32(ADR_GEMINIA_PMU_RAM_25)) & 0xffffffff ) >> 0)
+#define GET_RG_GEMINIA_RAM_26 (((REG32(ADR_GEMINIA_PMU_RAM_26)) & 0xffffffff ) >> 0)
+#define GET_RG_GEMINIA_RAM_27 (((REG32(ADR_GEMINIA_PMU_RAM_27)) & 0xffffffff ) >> 0)
+#define GET_RG_GEMINIA_RAM_28 (((REG32(ADR_GEMINIA_PMU_RAM_28)) & 0xffffffff ) >> 0)
+#define GET_RG_GEMINIA_RAM_29 (((REG32(ADR_GEMINIA_PMU_RAM_29)) & 0xffffffff ) >> 0)
+#define GET_RG_GEMINIA_RAM_30 (((REG32(ADR_GEMINIA_PMU_RAM_30)) & 0xffffffff ) >> 0)
+#define GET_RG_GEMINIA_RAM_31 (((REG32(ADR_GEMINIA_PMU_RAM_31)) & 0xffffffff ) >> 0)
+#define GET_RG_TURISMO_TRX_HW_PINSEL (((REG32(ADR_TURISMO_TRX_MODE_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_TURISMO_TRX_HS_3WIRE_MANUAL (((REG32(ADR_TURISMO_TRX_MODE_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_RG_TURISMO_TRX_MODE_MANUAL (((REG32(ADR_TURISMO_TRX_MODE_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_RG_TURISMO_TRX_RX_GAIN_MANUAL (((REG32(ADR_TURISMO_TRX_MODE_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_RG_TURISMO_TRX_TX_GAIN_MANUAL (((REG32(ADR_TURISMO_TRX_MODE_REGISTER)) & 0x00000020 ) >> 5)
+#define GET_RG_TURISMO_TRX_TXGAIN_PHYCTRL (((REG32(ADR_TURISMO_TRX_MODE_REGISTER)) & 0x00000040 ) >> 6)
+#define GET_RG_TURISMO_TRX_RX_AGC (((REG32(ADR_TURISMO_TRX_MODE_REGISTER)) & 0x00000080 ) >> 7)
+#define GET_RG_TURISMO_TRX_MODE (((REG32(ADR_TURISMO_TRX_MODE_REGISTER)) & 0x00000700 ) >> 8)
+#define GET_RG_TURISMO_TRX_CAL_INDEX (((REG32(ADR_TURISMO_TRX_MODE_REGISTER)) & 0x0000f000 ) >> 12)
+#define GET_RG_TURISMO_TRX_RFG (((REG32(ADR_TURISMO_TRX_MODE_REGISTER)) & 0x00030000 ) >> 16)
+#define GET_RG_TURISMO_TRX_PGAG (((REG32(ADR_TURISMO_TRX_MODE_REGISTER)) & 0x003c0000 ) >> 18)
+#define GET_RG_TURISMO_TRX_BW_HT40 (((REG32(ADR_TURISMO_TRX_MODE_REGISTER)) & 0x00400000 ) >> 22)
+#define GET_RG_TURISMO_TRX_BW_MANUAL (((REG32(ADR_TURISMO_TRX_MODE_REGISTER)) & 0x00800000 ) >> 23)
+#define GET_RG_TURISMO_TRX_TX_GAIN (((REG32(ADR_TURISMO_TRX_MODE_REGISTER)) & 0x7f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_TX_TRSW_MANUAL (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_TURISMO_TRX_EN_TX_TRSW (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_RG_TURISMO_TRX_RX_LNA_MANUAL (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_RG_TURISMO_TRX_EN_RX_LNA (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_RG_TURISMO_TRX_RX_MIXER_MANUAL (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_RG_TURISMO_TRX_EN_RX_MIXER (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000020 ) >> 5)
+#define GET_RG_TURISMO_TRX_RX_DIV2_MANUAL (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000040 ) >> 6)
+#define GET_RG_TURISMO_TRX_EN_RX_DIV2 (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000080 ) >> 7)
+#define GET_RG_TURISMO_TRX_RX_LOBUF_MANUAL (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000100 ) >> 8)
+#define GET_RG_TURISMO_TRX_EN_RX_LOBUF (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000200 ) >> 9)
+#define GET_RG_TURISMO_TRX_RX_TZ_MANUAL (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000400 ) >> 10)
+#define GET_RG_TURISMO_TRX_EN_RX_TZ (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_RG_TURISMO_TRX_RX_FILTER_MANUAL (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00001000 ) >> 12)
+#define GET_RG_TURISMO_TRX_EN_RX_FILTER (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00002000 ) >> 13)
+#define GET_RG_TURISMO_TRX_RX_ADC_MANUAL (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_RG_TURISMO_TRX_EN_RX_ADC (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00008000 ) >> 15)
+#define GET_RG_TURISMO_TRX_RX_RSSI_MANUAL (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00010000 ) >> 16)
+#define GET_RG_TURISMO_TRX_EN_RX_RSSI (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00020000 ) >> 17)
+#define GET_RG_TURISMO_TRX_TX_PA_MANUAL (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00040000 ) >> 18)
+#define GET_RG_TURISMO_TRX_EN_TX_PA (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00080000 ) >> 19)
+#define GET_RG_TURISMO_TRX_TX_MOD_MANUAL (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00100000 ) >> 20)
+#define GET_RG_TURISMO_TRX_EN_TX_MOD (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00200000 ) >> 21)
+#define GET_RG_TURISMO_TRX_TX_DAC_MANUAL (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00400000 ) >> 22)
+#define GET_RG_TURISMO_TRX_EN_TX_DAC (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00800000 ) >> 23)
+#define GET_RG_TURISMO_TRX_TX_DIV2_MANUAL (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x01000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_EN_TX_DIV2 (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x02000000 ) >> 25)
+#define GET_RG_TURISMO_TRX_TX_DIV2_BUF_MANUAL (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x04000000 ) >> 26)
+#define GET_RG_TURISMO_TRX_EN_TX_DIV2_BUF (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x08000000 ) >> 27)
+#define GET_RG_TURISMO_TRX_TX_BT_PA_MANUAL (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x10000000 ) >> 28)
+#define GET_RG_TURISMO_TRX_EN_TX_BT_PA (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x20000000 ) >> 29)
+#define GET_RG_TURISMO_TRX_EN_IOT_ADC_BUF (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x40000000 ) >> 30)
+#define GET_RG_TURISMO_TRX_EN_IOT_ADC (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x80000000 ) >> 31)
+#define GET_RG_TURISMO_TRX_EN_LDO_RX_FE (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_TURISMO_TRX_EN_LDO_AFE (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_RG_TURISMO_TRX_EN_IREF_RX (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_RG_TURISMO_TRX_TX_DAC_CAL_MANUAL (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_RG_TURISMO_TRX_EN_TX_DAC_CAL (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_RG_TURISMO_TRX_RX_TZ_OUT_TRISTATE_MANUAL (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000020 ) >> 5)
+#define GET_RG_TURISMO_TRX_RX_TZ_OUT_TRISTATE (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000040 ) >> 6)
+#define GET_RG_TURISMO_TRX_TX_SELF_MIXER_MANUAL (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000080 ) >> 7)
+#define GET_RG_TURISMO_TRX_EN_TX_SELF_MIXER (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000100 ) >> 8)
+#define GET_RG_TURISMO_TRX_RX_IQCAL_MANUAL (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000200 ) >> 9)
+#define GET_RG_TURISMO_TRX_EN_RX_IQCAL (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000400 ) >> 10)
+#define GET_RG_TURISMO_TRX_TX_DPD_MANUAL (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_RG_TURISMO_TRX_EN_TX_DPD (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00001000 ) >> 12)
+#define GET_RG_TURISMO_TRX_EN_TX_TSSI (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_RG_TURISMO_TRX_EN_SARADC (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00008000 ) >> 15)
+#define GET_RG_TURISMO_TRX_EN_TX_VTOI_2ND (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00010000 ) >> 16)
+#define GET_RG_TURISMO_TRX_TXLPF_BYPASS (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00020000 ) >> 17)
+#define GET_RG_TURISMO_TRX_TX_EN_VOLTAGE_IN (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00040000 ) >> 18)
+#define GET_RG_TURISMO_TRX_EN_TX_DAC_OUT (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00080000 ) >> 19)
+#define GET_RG_TURISMO_TRX_EN_TX_DAC_VOUT (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00100000 ) >> 20)
+#define GET_RG_TURISMO_TRX_RX_ABBOUT_TRI_STATE (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00200000 ) >> 21)
+#define GET_RG_TURISMO_TRX_EN_RX_TESTNODE (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00400000 ) >> 22)
+#define GET_RG_TURISMO_TRX_EN_RX_PADSW (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00800000 ) >> 23)
+#define GET_RG_TURISMO_TRX_EN_LDO_RX_FE_FC (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x02000000 ) >> 25)
+#define GET_RG_TURISMO_TRX_EN_LDO_RX_AFE_FC (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x04000000 ) >> 26)
+#define GET_RG_TURISMO_TRX_EN_LDO_RX_FE_IQUP (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x08000000 ) >> 27)
+#define GET_RG_TURISMO_TRX_EN_LDO_RX_AFE_IQUP (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x10000000 ) >> 28)
+#define GET_RG_TURISMO_TRX_RX_SQDC (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0xe0000000 ) >> 29)
+#define GET_RG_TURISMO_TRX_LDO_LEVEL_RX_FE (((REG32(ADR_TURISMO_TRX_2_4G_LDO_REGISTER)) & 0x00000007 ) >> 0)
+#define GET_RG_TURISMO_TRX_EN_LDO_RX_FE_BYP (((REG32(ADR_TURISMO_TRX_2_4G_LDO_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_RG_TURISMO_TRX_LDO_LEVEL_AFE (((REG32(ADR_TURISMO_TRX_2_4G_LDO_REGISTER)) & 0x00000070 ) >> 4)
+#define GET_RG_TURISMO_TRX_EN_LDO_RX_AFE_BYP (((REG32(ADR_TURISMO_TRX_2_4G_LDO_REGISTER)) & 0x00000080 ) >> 7)
+#define GET_RG_TURISMO_TRX_TX_PA_LDO_LEVEL (((REG32(ADR_TURISMO_TRX_2_4G_LDO_REGISTER)) & 0x00000700 ) >> 8)
+#define GET_RG_TURISMO_TRX_DP_LDO_LEVEL (((REG32(ADR_TURISMO_TRX_2_4G_LDO_REGISTER)) & 0x00007000 ) >> 12)
+#define GET_RG_TURISMO_TRX_EN_LDO_DP_BYP (((REG32(ADR_TURISMO_TRX_2_4G_LDO_REGISTER)) & 0x00008000 ) >> 15)
+#define GET_RG_TURISMO_TRX_SX_LDO_CP_LEVEL (((REG32(ADR_TURISMO_TRX_2_4G_LDO_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_TURISMO_TRX_EN_LDO_CP_BYP (((REG32(ADR_TURISMO_TRX_2_4G_LDO_REGISTER)) & 0x00080000 ) >> 19)
+#define GET_RG_TURISMO_TRX_SX_LDO_LO_LEVEL (((REG32(ADR_TURISMO_TRX_2_4G_LDO_REGISTER)) & 0x00700000 ) >> 20)
+#define GET_RG_TURISMO_TRX_EN_LDO_LO_BYP (((REG32(ADR_TURISMO_TRX_2_4G_LDO_REGISTER)) & 0x00800000 ) >> 23)
+#define GET_RG_TURISMO_TRX_SX_LDO_VCO_LEVEL (((REG32(ADR_TURISMO_TRX_2_4G_LDO_REGISTER)) & 0x07000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_SX_LDO_DIV_LEVEL (((REG32(ADR_TURISMO_TRX_2_4G_LDO_REGISTER)) & 0x70000000 ) >> 28)
+#define GET_RG_TURISMO_TRX_EN_LDO_DIV_BYP (((REG32(ADR_TURISMO_TRX_2_4G_LDO_REGISTER)) & 0x80000000 ) >> 31)
+#define GET_RG_TURISMO_TRX_WF_RX_ABBCTUNE (((REG32(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_WF_RX_FILTERI_COARSE (((REG32(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER)) & 0x00000300 ) >> 8)
+#define GET_RG_TURISMO_TRX_WF_RX_FILTERI1ST (((REG32(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER)) & 0x00000c00 ) >> 10)
+#define GET_RG_TURISMO_TRX_WF_RX_FILTERI2ND (((REG32(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER)) & 0x00003000 ) >> 12)
+#define GET_RG_TURISMO_TRX_WF_RX_FILTERI3RD (((REG32(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER)) & 0x0000c000 ) >> 14)
+#define GET_RG_TURISMO_TRX_WF_RX_ABBCFIX (((REG32(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER)) & 0x00010000 ) >> 16)
+#define GET_RG_TURISMO_TRX_WF_RX_ABB_N_MODE (((REG32(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER)) & 0x00020000 ) >> 17)
+#define GET_RG_TURISMO_TRX_WF_RX_ABB_BT_MODE (((REG32(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER)) & 0x00040000 ) >> 18)
+#define GET_RG_TURISMO_TRX_WF_RX_ABB_IDIV3 (((REG32(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER)) & 0x00080000 ) >> 19)
+#define GET_RG_TURISMO_TRX_WF_RX_EN_IDACA_COARSE (((REG32(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER)) & 0x00100000 ) >> 20)
+#define GET_RG_TURISMO_TRX_WF_RX_EN_LOOPA (((REG32(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER)) & 0x00200000 ) >> 21)
+#define GET_RG_TURISMO_TRX_WF_RX_FILTERVCM (((REG32(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER)) & 0x07000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_WF_RX_OUTVCM (((REG32(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER)) & 0x70000000 ) >> 28)
+#define GET_RG_TURISMO_TRX_WF_N_RX_ABBCTUNE (((REG32(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_WF_N_RX_FILTERI_COARSE (((REG32(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER)) & 0x00000300 ) >> 8)
+#define GET_RG_TURISMO_TRX_WF_N_RX_FILTERI1ST (((REG32(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER)) & 0x00000c00 ) >> 10)
+#define GET_RG_TURISMO_TRX_WF_N_RX_FILTERI2ND (((REG32(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER)) & 0x00003000 ) >> 12)
+#define GET_RG_TURISMO_TRX_WF_N_RX_FILTERI3RD (((REG32(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER)) & 0x0000c000 ) >> 14)
+#define GET_RG_TURISMO_TRX_WF_N_RX_ABBCFIX (((REG32(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER)) & 0x00010000 ) >> 16)
+#define GET_RG_TURISMO_TRX_WF_N_RX_ABB_N_MODE (((REG32(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER)) & 0x00020000 ) >> 17)
+#define GET_RG_TURISMO_TRX_WF_N_RX_ABB_BT_MODE (((REG32(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER)) & 0x00040000 ) >> 18)
+#define GET_RG_TURISMO_TRX_WF_N_RX_ABB_IDIV3 (((REG32(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER)) & 0x00080000 ) >> 19)
+#define GET_RG_TURISMO_TRX_WF_N_RX_EN_IDACA_COARSE (((REG32(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER)) & 0x00100000 ) >> 20)
+#define GET_RG_TURISMO_TRX_WF_N_RX_EN_LOOPA (((REG32(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER)) & 0x00200000 ) >> 21)
+#define GET_RG_TURISMO_TRX_WF_N_RX_FILTERVCM (((REG32(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER)) & 0x07000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_WF_N_RX_OUTVCM (((REG32(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER)) & 0x70000000 ) >> 28)
+#define GET_RG_TURISMO_TRX_BT_RX_ABBCTUNE (((REG32(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_BT_RX_FILTERI_COARSE (((REG32(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER)) & 0x00000300 ) >> 8)
+#define GET_RG_TURISMO_TRX_BT_RX_FILTERI1ST (((REG32(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER)) & 0x00000c00 ) >> 10)
+#define GET_RG_TURISMO_TRX_BT_RX_FILTERI2ND (((REG32(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER)) & 0x00003000 ) >> 12)
+#define GET_RG_TURISMO_TRX_BT_RX_FILTERI3RD (((REG32(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER)) & 0x0000c000 ) >> 14)
+#define GET_RG_TURISMO_TRX_BT_RX_ABBCFIX (((REG32(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER)) & 0x00010000 ) >> 16)
+#define GET_RG_TURISMO_TRX_BT_RX_ABB_N_MODE (((REG32(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER)) & 0x00020000 ) >> 17)
+#define GET_RG_TURISMO_TRX_BT_RX_ABB_BT_MODE (((REG32(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER)) & 0x00040000 ) >> 18)
+#define GET_RG_TURISMO_TRX_BT_RX_ABB_IDIV3 (((REG32(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER)) & 0x00080000 ) >> 19)
+#define GET_RG_TURISMO_TRX_BT_RX_EN_IDACA_COARSE (((REG32(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER)) & 0x00100000 ) >> 20)
+#define GET_RG_TURISMO_TRX_BT_RX_EN_LOOPA (((REG32(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER)) & 0x00200000 ) >> 21)
+#define GET_RG_TURISMO_TRX_BT_RX_FILTERVCM (((REG32(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER)) & 0x07000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_BT_RX_OUTVCM (((REG32(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER)) & 0x70000000 ) >> 28)
+#define GET_RG_TURISMO_TRX_RX_ADCRSSI_VCM (((REG32(ADR_TURISMO_TRX_2_4G_RX_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_TURISMO_TRX_RX_REC_LPFCORNER (((REG32(ADR_TURISMO_TRX_2_4G_RX_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_TURISMO_TRX_RX_ADCRSSI_CLKSEL (((REG32(ADR_TURISMO_TRX_2_4G_RX_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_RG_TURISMO_TRX_RSSI_CLOCK_GATING (((REG32(ADR_TURISMO_TRX_2_4G_RX_REGISTER)) & 0x00000020 ) >> 5)
+#define GET_RG_TURISMO_TRX_RX_IDACA_COARSE_PMOS_ON (((REG32(ADR_TURISMO_TRX_2_4G_RX_REGISTER)) & 0x00000040 ) >> 6)
+#define GET_RG_TURISMO_TRX_TX_DPDGM_BIAS (((REG32(ADR_TURISMO_TRX_2_4G_RX_REGISTER)) & 0x00000f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_TX_DPD_DIV (((REG32(ADR_TURISMO_TRX_2_4G_RX_REGISTER)) & 0x0000f000 ) >> 12)
+#define GET_RG_TURISMO_TRX_TX_TSSI_BIAS (((REG32(ADR_TURISMO_TRX_2_4G_RX_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_TURISMO_TRX_TX_TSSI_DIV (((REG32(ADR_TURISMO_TRX_2_4G_RX_REGISTER)) & 0x00380000 ) >> 19)
+#define GET_RG_TURISMO_TRX_TX_TSSI_TEST (((REG32(ADR_TURISMO_TRX_2_4G_RX_REGISTER)) & 0x00c00000 ) >> 22)
+#define GET_RG_TURISMO_TRX_TX_TSSI_TESTMODE (((REG32(ADR_TURISMO_TRX_2_4G_RX_REGISTER)) & 0x01000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_EN_RX_RSSI_TESTNODE (((REG32(ADR_TURISMO_TRX_2_4G_RX_REGISTER)) & 0x0e000000 ) >> 25)
+#define GET_RG_TURISMO_TRX_RX_LNA_TRI_SEL (((REG32(ADR_TURISMO_TRX_2_4G_RX_REGISTER)) & 0x30000000 ) >> 28)
+#define GET_RG_TURISMO_TRX_RX_LNA_SETTLE (((REG32(ADR_TURISMO_TRX_2_4G_RX_REGISTER)) & 0xc0000000 ) >> 30)
+#define GET_RG_TURISMO_TRX_WF_TXPGA_CAPSW (((REG32(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_TURISMO_TRX_WF_TX_DIV_VSET (((REG32(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_TURISMO_TRX_WF_TX_LOBUF_VSET (((REG32(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER)) & 0x00000030 ) >> 4)
+#define GET_RG_TURISMO_TRX_WF_TX_BTPASW (((REG32(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER)) & 0x00000040 ) >> 6)
+#define GET_RG_TURISMO_TRX_WF_EN_TX_PA_VIN33 (((REG32(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER)) & 0x00000080 ) >> 7)
+#define GET_RG_TURISMO_TRX_BT_TXPGA_CAPSW (((REG32(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER)) & 0x00003000 ) >> 12)
+#define GET_RG_TURISMO_TRX_BT_TX_DIV_VSET (((REG32(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER)) & 0x0000c000 ) >> 14)
+#define GET_RG_TURISMO_TRX_BT_TX_LOBUF_VSET (((REG32(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER)) & 0x00030000 ) >> 16)
+#define GET_RG_TURISMO_TRX_BT_TX_BTPASW (((REG32(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER)) & 0x00040000 ) >> 18)
+#define GET_RG_TURISMO_TRX_BT_EN_TX_PA_VIN33 (((REG32(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER)) & 0x00080000 ) >> 19)
+#define GET_RG_TURISMO_TRX_TX_PA_LDO_SEL_RES (((REG32(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER)) & 0x03000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_EN_LDO_TX_PA (((REG32(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER)) & 0x04000000 ) >> 26)
+#define GET_RG_TURISMO_TRX_EN_TX_PA_LDO_FC (((REG32(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER)) & 0x08000000 ) >> 27)
+#define GET_RG_TURISMO_TRX_EN_TX_PA_LDO_IQUP (((REG32(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER)) & 0x10000000 ) >> 28)
+#define GET_RG_TURISMO_TRX_EN_TX_PA_LDO_VTH (((REG32(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER)) & 0x20000000 ) >> 29)
+#define GET_RG_TURISMO_TRX_WF_PACELL_EN (((REG32(ADR_TURISMO_TRX_2_4G_TX_PA_REGISTER)) & 0x00000007 ) >> 0)
+#define GET_RG_TURISMO_TRX_WF_PABIAS_CTRL (((REG32(ADR_TURISMO_TRX_2_4G_TX_PA_REGISTER)) & 0x000000f0 ) >> 4)
+#define GET_RG_TURISMO_TRX_WF_TX_PA1_VCAS (((REG32(ADR_TURISMO_TRX_2_4G_TX_PA_REGISTER)) & 0x00000700 ) >> 8)
+#define GET_RG_TURISMO_TRX_WF_TX_PA2_VCAS (((REG32(ADR_TURISMO_TRX_2_4G_TX_PA_REGISTER)) & 0x00007000 ) >> 12)
+#define GET_RG_TURISMO_TRX_WF_TX_PA3_VCAS (((REG32(ADR_TURISMO_TRX_2_4G_TX_PA_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_TURISMO_TRX_BT_PABIAS_2X (((REG32(ADR_TURISMO_TRX_2_4G_TX_PA_REGISTER)) & 0x00800000 ) >> 23)
+#define GET_RG_TURISMO_TRX_BT_PABIAS_CTRL (((REG32(ADR_TURISMO_TRX_2_4G_TX_PA_REGISTER)) & 0x0f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_BT_TX_PA_VCAS (((REG32(ADR_TURISMO_TRX_2_4G_TX_PA_REGISTER)) & 0x30000000 ) >> 28)
+#define GET_RG_TURISMO_TRX_BT_TX_MOD_CS (((REG32(ADR_TURISMO_TRX_2_4G_TX_PA_REGISTER)) & 0xc0000000 ) >> 30)
+#define GET_RG_TURISMO_TRX_TXPGA_MAIN (((REG32(ADR_TURISMO_TRX_2_4G_TX_REGISTER)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_TXPGA_STEER (((REG32(ADR_TURISMO_TRX_2_4G_TX_REGISTER)) & 0x00000fc0 ) >> 6)
+#define GET_RG_TURISMO_TRX_TXMOD_GMCELL (((REG32(ADR_TURISMO_TRX_2_4G_TX_REGISTER)) & 0x00003000 ) >> 12)
+#define GET_RG_TURISMO_TRX_TXLPF_GMCELL (((REG32(ADR_TURISMO_TRX_2_4G_TX_REGISTER)) & 0x0000c000 ) >> 14)
+#define GET_RG_TURISMO_TRX_WF_TX_GAIN_OFFSET (((REG32(ADR_TURISMO_TRX_2_4G_TX_REGISTER)) & 0x000f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_BT_TX_GAIN_OFFSET (((REG32(ADR_TURISMO_TRX_2_4G_TX_REGISTER)) & 0x00f00000 ) >> 20)
+#define GET_RG_TURISMO_TRX_TX_VTOI_CURRENT (((REG32(ADR_TURISMO_TRX_2_4G_TX_REGISTER)) & 0x03000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_TX_VTOI_GM (((REG32(ADR_TURISMO_TRX_2_4G_TX_REGISTER)) & 0x0c000000 ) >> 26)
+#define GET_RG_TURISMO_TRX_TX_VTOI_OPTION (((REG32(ADR_TURISMO_TRX_2_4G_TX_REGISTER)) & 0x30000000 ) >> 28)
+#define GET_RG_TURISMO_TRX_TX_VTOI_FS (((REG32(ADR_TURISMO_TRX_2_4G_TX_REGISTER)) & 0x40000000 ) >> 30)
+#define GET_RG_TURISMO_TRX_WF_RX_HG_LNA_GC (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_TURISMO_TRX_WF_RX_HG_TZ_GC (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_TURISMO_TRX_WF_RX_HG_LNAHGN_BIAS (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER)) & 0x000000f0 ) >> 4)
+#define GET_RG_TURISMO_TRX_WF_RX_HG_LNAHGP_BIAS (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER)) & 0x00000f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_WF_RX_HG_LNALG_BIAS (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER)) & 0x0000f000 ) >> 12)
+#define GET_RG_TURISMO_TRX_WF_RX_HG_TZ_CAP (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_TURISMO_TRX_WF_RX_HG_TZ_GC_BOOST (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER)) & 0x00300000 ) >> 20)
+#define GET_RG_TURISMO_TRX_WF_RX_HG_DIV2_CORE (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER)) & 0x00c00000 ) >> 22)
+#define GET_RG_TURISMO_TRX_WF_RX_HG_LOBUF (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER)) & 0x03000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_WF_RX_HG_TZI (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER)) & 0x1c000000 ) >> 26)
+#define GET_RG_TURISMO_TRX_WF_RX_HG_TZ_VCM (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER)) & 0xe0000000 ) >> 29)
+#define GET_RG_TURISMO_TRX_WF_RX_MG_LNA_GC (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_TURISMO_TRX_WF_RX_MG_TZ_GC (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_TURISMO_TRX_WF_RX_MG_LNAHGN_BIAS (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER)) & 0x000000f0 ) >> 4)
+#define GET_RG_TURISMO_TRX_WF_RX_MG_LNAHGP_BIAS (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER)) & 0x00000f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_WF_RX_MG_LNALG_BIAS (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER)) & 0x0000f000 ) >> 12)
+#define GET_RG_TURISMO_TRX_WF_RX_MG_TZ_CAP (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_TURISMO_TRX_WF_RX_MG_TZ_GC_BOOST (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER)) & 0x00300000 ) >> 20)
+#define GET_RG_TURISMO_TRX_WF_RX_MG_DIV2_CORE (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER)) & 0x00c00000 ) >> 22)
+#define GET_RG_TURISMO_TRX_WF_RX_MG_LOBUF (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER)) & 0x03000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_WF_RX_MG_TZI (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER)) & 0x1c000000 ) >> 26)
+#define GET_RG_TURISMO_TRX_WF_RX_MG_TZ_VCM (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER)) & 0xe0000000 ) >> 29)
+#define GET_RG_TURISMO_TRX_WF_RX_LG_LNA_GC (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_TURISMO_TRX_WF_RX_LG_TZ_GC (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_TURISMO_TRX_WF_RX_LG_LNAHGN_BIAS (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER)) & 0x000000f0 ) >> 4)
+#define GET_RG_TURISMO_TRX_WF_RX_LG_LNAHGP_BIAS (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER)) & 0x00000f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_WF_RX_LG_LNALG_BIAS (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER)) & 0x0000f000 ) >> 12)
+#define GET_RG_TURISMO_TRX_WF_RX_LG_TZ_CAP (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_TURISMO_TRX_WF_RX_LG_TZ_GC_BOOST (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER)) & 0x00300000 ) >> 20)
+#define GET_RG_TURISMO_TRX_WF_RX_LG_DIV2_CORE (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER)) & 0x00c00000 ) >> 22)
+#define GET_RG_TURISMO_TRX_WF_RX_LG_LOBUF (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER)) & 0x03000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_WF_RX_LG_TZI (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER)) & 0x1c000000 ) >> 26)
+#define GET_RG_TURISMO_TRX_WF_RX_LG_TZ_VCM (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER)) & 0xe0000000 ) >> 29)
+#define GET_RG_TURISMO_TRX_WF_RX_ULG_LNA_GC (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_TURISMO_TRX_WF_RX_ULG_TZ_GC (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_TURISMO_TRX_WF_RX_ULG_LNAHGN_BIAS (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER)) & 0x000000f0 ) >> 4)
+#define GET_RG_TURISMO_TRX_WF_RX_ULG_LNAHGP_BIAS (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER)) & 0x00000f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_WF_RX_ULG_LNALG_BIAS (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER)) & 0x0000f000 ) >> 12)
+#define GET_RG_TURISMO_TRX_WF_RX_ULG_TZ_CAP (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_TURISMO_TRX_WF_RX_ULG_TZ_GC_BOOST (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER)) & 0x00300000 ) >> 20)
+#define GET_RG_TURISMO_TRX_WF_RX_ULG_DIV2_CORE (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER)) & 0x00c00000 ) >> 22)
+#define GET_RG_TURISMO_TRX_WF_RX_ULG_LOBUF (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER)) & 0x03000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_WF_RX_ULG_TZI (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER)) & 0x1c000000 ) >> 26)
+#define GET_RG_TURISMO_TRX_WF_RX_ULG_TZ_VCM (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER)) & 0xe0000000 ) >> 29)
+#define GET_RG_TURISMO_TRX_BT_RX_HG_LNA_GC (((REG32(ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_TURISMO_TRX_BT_RX_HG_TZ_GC (((REG32(ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_TURISMO_TRX_BT_RX_HG_LNAHGN_BIAS (((REG32(ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER)) & 0x000000f0 ) >> 4)
+#define GET_RG_TURISMO_TRX_BT_RX_HG_LNAHGP_BIAS (((REG32(ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER)) & 0x00000f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_BT_RX_HG_LNALG_BIAS (((REG32(ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER)) & 0x0000f000 ) >> 12)
+#define GET_RG_TURISMO_TRX_BT_RX_HG_TZ_CAP (((REG32(ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_TURISMO_TRX_BT_RX_HG_TZ_GC_BOOST (((REG32(ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER)) & 0x00300000 ) >> 20)
+#define GET_RG_TURISMO_TRX_BT_RX_HG_DIV2_CORE (((REG32(ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER)) & 0x00c00000 ) >> 22)
+#define GET_RG_TURISMO_TRX_BT_RX_HG_LOBUF (((REG32(ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER)) & 0x03000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_BT_RX_HG_TZI (((REG32(ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER)) & 0x1c000000 ) >> 26)
+#define GET_RG_TURISMO_TRX_BT_RX_HG_TZ_VCM (((REG32(ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER)) & 0xe0000000 ) >> 29)
+#define GET_RG_TURISMO_TRX_BT_RX_MG_LNA_GC (((REG32(ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_TURISMO_TRX_BT_RX_MG_TZ_GC (((REG32(ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_TURISMO_TRX_BT_RX_MG_LNAHGN_BIAS (((REG32(ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER)) & 0x000000f0 ) >> 4)
+#define GET_RG_TURISMO_TRX_BT_RX_MG_LNAHGP_BIAS (((REG32(ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER)) & 0x00000f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_BT_RX_MG_LNALG_BIAS (((REG32(ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER)) & 0x0000f000 ) >> 12)
+#define GET_RG_TURISMO_TRX_BT_RX_MG_TZ_CAP (((REG32(ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_TURISMO_TRX_BT_RX_MG_TZ_GC_BOOST (((REG32(ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER)) & 0x00300000 ) >> 20)
+#define GET_RG_TURISMO_TRX_BT_RX_MG_DIV2_CORE (((REG32(ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER)) & 0x00c00000 ) >> 22)
+#define GET_RG_TURISMO_TRX_BT_RX_MG_LOBUF (((REG32(ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER)) & 0x03000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_BT_RX_MG_TZI (((REG32(ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER)) & 0x1c000000 ) >> 26)
+#define GET_RG_TURISMO_TRX_BT_RX_MG_TZ_VCM (((REG32(ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER)) & 0xe0000000 ) >> 29)
+#define GET_RG_TURISMO_TRX_BT_RX_LG_LNA_GC (((REG32(ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_TURISMO_TRX_BT_RX_LG_TZ_GC (((REG32(ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_TURISMO_TRX_BT_RX_LG_LNAHGN_BIAS (((REG32(ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER)) & 0x000000f0 ) >> 4)
+#define GET_RG_TURISMO_TRX_BT_RX_LG_LNAHGP_BIAS (((REG32(ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER)) & 0x00000f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_BT_RX_LG_LNALG_BIAS (((REG32(ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER)) & 0x0000f000 ) >> 12)
+#define GET_RG_TURISMO_TRX_BT_RX_LG_TZ_CAP (((REG32(ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_TURISMO_TRX_BT_RX_LG_TZ_GC_BOOST (((REG32(ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER)) & 0x00300000 ) >> 20)
+#define GET_RG_TURISMO_TRX_BT_RX_LG_DIV2_CORE (((REG32(ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER)) & 0x00c00000 ) >> 22)
+#define GET_RG_TURISMO_TRX_BT_RX_LG_LOBUF (((REG32(ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER)) & 0x03000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_BT_RX_LG_TZI (((REG32(ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER)) & 0x1c000000 ) >> 26)
+#define GET_RG_TURISMO_TRX_BT_RX_LG_TZ_VCM (((REG32(ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER)) & 0xe0000000 ) >> 29)
+#define GET_RG_TURISMO_TRX_BT_RX_ULG_LNA_GC (((REG32(ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_TURISMO_TRX_BT_RX_ULG_TZ_GC (((REG32(ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_TURISMO_TRX_BT_RX_ULG_LNAHGN_BIAS (((REG32(ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER)) & 0x000000f0 ) >> 4)
+#define GET_RG_TURISMO_TRX_BT_RX_ULG_LNAHGP_BIAS (((REG32(ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER)) & 0x00000f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_BT_RX_ULG_LNALG_BIAS (((REG32(ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER)) & 0x0000f000 ) >> 12)
+#define GET_RG_TURISMO_TRX_BT_RX_ULG_TZ_CAP (((REG32(ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_TURISMO_TRX_BT_RX_ULG_TZ_GC_BOOST (((REG32(ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER)) & 0x00300000 ) >> 20)
+#define GET_RG_TURISMO_TRX_BT_RX_ULG_DIV2_CORE (((REG32(ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER)) & 0x00c00000 ) >> 22)
+#define GET_RG_TURISMO_TRX_BT_RX_ULG_LOBUF (((REG32(ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER)) & 0x03000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_BT_RX_ULG_TZI (((REG32(ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER)) & 0x1c000000 ) >> 26)
+#define GET_RG_TURISMO_TRX_BT_RX_ULG_TZ_VCM (((REG32(ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER)) & 0xe0000000 ) >> 29)
+#define GET_RG_TURISMO_TRX_RX_ADC_CLKSEL (((REG32(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_TURISMO_TRX_RX_ADC_DNLEN (((REG32(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_RG_TURISMO_TRX_RX_ADC_METAEN (((REG32(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_RG_TURISMO_TRX_RX_ADC_TFLAG (((REG32(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_RG_TURISMO_TRX_RX_ADC_TSEL (((REG32(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER)) & 0x000000f0 ) >> 4)
+#define GET_RG_TURISMO_TRX_WF_RX_ADC_ICMP (((REG32(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER)) & 0x00000300 ) >> 8)
+#define GET_RG_TURISMO_TRX_WF_RX_ADC_VCMI (((REG32(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER)) & 0x00000c00 ) >> 10)
+#define GET_RG_TURISMO_TRX_WF_RX_ADC_CLOAD (((REG32(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER)) & 0x00003000 ) >> 12)
+#define GET_RG_TURISMO_TRX_BT_RX_ADC_ICMP (((REG32(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER)) & 0x00030000 ) >> 16)
+#define GET_RG_TURISMO_TRX_BT_RX_ADC_VCMI (((REG32(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER)) & 0x000c0000 ) >> 18)
+#define GET_RG_TURISMO_TRX_BT_RX_ADC_CLOAD (((REG32(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER)) & 0x00300000 ) >> 20)
+#define GET_RG_TURISMO_TRX_SARADC_5G_TSSI (((REG32(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER)) & 0x00800000 ) >> 23)
+#define GET_RG_TURISMO_TRX_SARADC_VRSEL (((REG32(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER)) & 0x03000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_EN_SAR_TEST (((REG32(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER)) & 0x0c000000 ) >> 26)
+#define GET_RG_TURISMO_TRX_SARADC_THERMAL (((REG32(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER)) & 0x10000000 ) >> 28)
+#define GET_RG_TURISMO_TRX_SARADC_TSSI (((REG32(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER)) & 0x20000000 ) >> 29)
+#define GET_RG_TURISMO_TRX_CLK_SAR_SEL (((REG32(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER)) & 0xc0000000 ) >> 30)
+#define GET_RG_TURISMO_TRX_WF_TX_DACI1ST (((REG32(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_TURISMO_TRX_WF_TX_DACLPF_ICOARSE (((REG32(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_TURISMO_TRX_WF_TX_DACLPF_IFINE (((REG32(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER)) & 0x00000030 ) >> 4)
+#define GET_RG_TURISMO_TRX_WF_TX_DACLPF_VCM (((REG32(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER)) & 0x000000c0 ) >> 6)
+#define GET_RG_TURISMO_TRX_WF_TX_DAC_IBIAS (((REG32(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER)) & 0x00000300 ) >> 8)
+#define GET_RG_TURISMO_TRX_WF_TX_DAC_IATTN (((REG32(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER)) & 0x00000400 ) >> 10)
+#define GET_RG_TURISMO_TRX_WF_TXLPF_BOOSTI (((REG32(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_RG_TURISMO_TRX_WF_TX_DAC_RCAL (((REG32(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER)) & 0x00003000 ) >> 12)
+#define GET_RG_TURISMO_TRX_WF_TX_DAC_CKEDGE_SEL (((REG32(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_RG_TURISMO_TRX_WF_TX_DAC_OS (((REG32(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_TURISMO_TRX_WF_TX_DAC_IOFFSET (((REG32(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER)) & 0x00f00000 ) >> 20)
+#define GET_RG_TURISMO_TRX_WF_TX_DAC_QOFFSET (((REG32(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER)) & 0x0f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_TX_DAC_TSEL (((REG32(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER)) & 0xf0000000 ) >> 28)
+#define GET_RG_TURISMO_TRX_BT_TX_DACI1ST (((REG32(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_TURISMO_TRX_BT_TX_DACLPF_ICOARSE (((REG32(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_TURISMO_TRX_BT_TX_DACLPF_IFINE (((REG32(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER)) & 0x00000030 ) >> 4)
+#define GET_RG_TURISMO_TRX_BT_TX_DACLPF_VCM (((REG32(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER)) & 0x000000c0 ) >> 6)
+#define GET_RG_TURISMO_TRX_BT_TX_DAC_IBIAS (((REG32(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER)) & 0x00000300 ) >> 8)
+#define GET_RG_TURISMO_TRX_BT_TX_DAC_IATTN (((REG32(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER)) & 0x00000400 ) >> 10)
+#define GET_RG_TURISMO_TRX_BT_TXLPF_BOOSTI (((REG32(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_RG_TURISMO_TRX_BT_TX_DAC_RCAL (((REG32(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER)) & 0x00003000 ) >> 12)
+#define GET_RG_TURISMO_TRX_BT_TX_DAC_CKEDGE_SEL (((REG32(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_RG_TURISMO_TRX_BT_TX_DAC_OS (((REG32(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_TURISMO_TRX_BT_TX_DAC_IOFFSET (((REG32(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER)) & 0x00f00000 ) >> 20)
+#define GET_RG_TURISMO_TRX_BT_TX_DAC_QOFFSET (((REG32(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER)) & 0x0f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_SX_EN_MAN (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000001 ) >> 0)
+#define GET_RG_TURISMO_TRX_SX_EN (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000002 ) >> 1)
+#define GET_RG_TURISMO_TRX_EN_SX_CP_MAN (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000004 ) >> 2)
+#define GET_RG_TURISMO_TRX_EN_SX_CP (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000008 ) >> 3)
+#define GET_RG_TURISMO_TRX_EN_SX_DIV_MAN (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000010 ) >> 4)
+#define GET_RG_TURISMO_TRX_EN_SX_DIV (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000020 ) >> 5)
+#define GET_RG_TURISMO_TRX_EN_SX_VCO_MAN (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000040 ) >> 6)
+#define GET_RG_TURISMO_TRX_EN_SX_VCO (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000080 ) >> 7)
+#define GET_RG_TURISMO_TRX_SX_PFD_RST_MAN (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000100 ) >> 8)
+#define GET_RG_TURISMO_TRX_SX_PFD_RST (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000200 ) >> 9)
+#define GET_RG_TURISMO_TRX_SX_UOP_MAN (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000400 ) >> 10)
+#define GET_RG_TURISMO_TRX_SX_UOP_EN (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000800 ) >> 11)
+#define GET_RG_TURISMO_TRX_EN_VCOBF_TXMB_MAN (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00001000 ) >> 12)
+#define GET_RG_TURISMO_TRX_EN_VCOBF_TXMB (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00002000 ) >> 13)
+#define GET_RG_TURISMO_TRX_EN_VCOBF_TXOB_MAN (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00004000 ) >> 14)
+#define GET_RG_TURISMO_TRX_EN_VCOBF_TXOB (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00008000 ) >> 15)
+#define GET_RG_TURISMO_TRX_EN_VCOBF_RXMB_MAN (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00010000 ) >> 16)
+#define GET_RG_TURISMO_TRX_EN_VCOBF_RXMB (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00020000 ) >> 17)
+#define GET_RG_TURISMO_TRX_EN_VCOBF_RXOB_MAN (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00040000 ) >> 18)
+#define GET_RG_TURISMO_TRX_EN_VCOBF_RXOB (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00080000 ) >> 19)
+#define GET_RG_TURISMO_TRX_EN_VCOBF_DIVCK_MAN (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00100000 ) >> 20)
+#define GET_RG_TURISMO_TRX_EN_VCOBF_DIVCK (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00200000 ) >> 21)
+#define GET_RG_TURISMO_TRX_SX_SBCAL_DIS (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00800000 ) >> 23)
+#define GET_RG_TURISMO_TRX_SX_SBCAL_AW (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x01000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_SX_AAC_DIS (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x04000000 ) >> 26)
+#define GET_RG_TURISMO_TRX_SX_TTL_DIS (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x08000000 ) >> 27)
+#define GET_RG_TURISMO_TRX_SX_CAL_INIT (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0xe0000000 ) >> 29)
+#define GET_RG_TURISMO_TRX_EN_SX_LDO_MAN (((REG32(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_TURISMO_TRX_EN_LDO_CP (((REG32(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_RG_TURISMO_TRX_EN_LDO_DIV (((REG32(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_RG_TURISMO_TRX_EN_LDO_LO (((REG32(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_RG_TURISMO_TRX_EN_LDO_VCO (((REG32(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_RG_TURISMO_TRX_EN_LDO_VCO_PSW (((REG32(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER)) & 0x00000200 ) >> 9)
+#define GET_RG_TURISMO_TRX_EN_LDO_VCO_VDD33 (((REG32(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER)) & 0x00000400 ) >> 10)
+#define GET_RG_TURISMO_TRX_EN_LDO_CP_IQUP (((REG32(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_RG_TURISMO_TRX_EN_LDO_DIV_IQUP (((REG32(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER)) & 0x00001000 ) >> 12)
+#define GET_RG_TURISMO_TRX_EN_LDO_LO_IQUP (((REG32(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER)) & 0x00002000 ) >> 13)
+#define GET_RG_TURISMO_TRX_EN_LDO_VCO_IQUP (((REG32(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_RG_TURISMO_TRX_SX_LDO_FCOFFT (((REG32(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER)) & 0x00380000 ) >> 19)
+#define GET_RG_TURISMO_TRX_LDO_CP_FC_MAN (((REG32(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER)) & 0x00400000 ) >> 22)
+#define GET_RG_TURISMO_TRX_LDO_CP_FC (((REG32(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER)) & 0x00800000 ) >> 23)
+#define GET_RG_TURISMO_TRX_LDO_DIV_FC_MAN (((REG32(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER)) & 0x01000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_LDO_DIV_FC (((REG32(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER)) & 0x02000000 ) >> 25)
+#define GET_RG_TURISMO_TRX_LDO_LO_FC_MAN (((REG32(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER)) & 0x04000000 ) >> 26)
+#define GET_RG_TURISMO_TRX_LDO_LO_FC (((REG32(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER)) & 0x08000000 ) >> 27)
+#define GET_RG_TURISMO_TRX_LDO_VCO_FC_MAN (((REG32(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER)) & 0x10000000 ) >> 28)
+#define GET_RG_TURISMO_TRX_LDO_VCO_FC (((REG32(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER)) & 0x20000000 ) >> 29)
+#define GET_RG_TURISMO_TRX_LDO_VCO_RCF (((REG32(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER)) & 0xc0000000 ) >> 30)
+#define GET_RG_TURISMO_TRX_SX_RFCTRL_F (((REG32(ADR_TURISMO_TRX_SX_2_4GB_FRACTIONAL_AND_INTEGER_8BITS)) & 0x00ffffff ) >> 0)
+#define GET_RG_TURISMO_TRX_SX_RFCTRL_CH_7_0 (((REG32(ADR_TURISMO_TRX_SX_2_4GB_FRACTIONAL_AND_INTEGER_8BITS)) & 0xff000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_SX_RFCTRL_CH_10_8 (((REG32(ADR_TURISMO_TRX_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE)) & 0x00000007 ) >> 0)
+#define GET_RG_TURISMO_TRX_SX_RFCH_MAP_EN (((REG32(ADR_TURISMO_TRX_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE)) & 0x00000008 ) >> 3)
+#define GET_RG_TURISMO_TRX_SX_XTAL_FREQ (((REG32(ADR_TURISMO_TRX_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE)) & 0x00000060 ) >> 5)
+#define GET_RG_TURISMO_TRX_SX_FREF_DOUB (((REG32(ADR_TURISMO_TRX_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE)) & 0x00000080 ) >> 7)
+#define GET_RG_TURISMO_TRX_SX_BTRX_SIDE (((REG32(ADR_TURISMO_TRX_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE)) & 0x00000100 ) >> 8)
+#define GET_RG_TURISMO_TRX_SX_LO_TIMES (((REG32(ADR_TURISMO_TRX_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE)) & 0x00000200 ) >> 9)
+#define GET_RG_TURISMO_TRX_SX_CHANNEL (((REG32(ADR_TURISMO_TRX_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE)) & 0x0007f800 ) >> 11)
+#define GET_RG_TURISMO_TRX_SX_CP_ISEL_BT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_)) & 0x0000000f ) >> 0)
+#define GET_RG_TURISMO_TRX_SX_CP_ISEL50U_BT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_)) & 0x00000010 ) >> 4)
+#define GET_RG_TURISMO_TRX_SX_CP_KP_DOUB_BT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_)) & 0x00000020 ) >> 5)
+#define GET_RG_TURISMO_TRX_SX_CP_ISEL_WF (((REG32(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_)) & 0x00000780 ) >> 7)
+#define GET_RG_TURISMO_TRX_SX_CP_ISEL50U_WF (((REG32(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_)) & 0x00000800 ) >> 11)
+#define GET_RG_TURISMO_TRX_SX_CP_KP_DOUB_WF (((REG32(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_)) & 0x00001000 ) >> 12)
+#define GET_RG_TURISMO_TRX_SX_CP_IOST_POL (((REG32(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_)) & 0x00008000 ) >> 15)
+#define GET_RG_TURISMO_TRX_SX_CP_IOST (((REG32(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_)) & 0x00070000 ) >> 16)
+#define GET_RG_TURISMO_TRX_SX_PFD_SEL (((REG32(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_)) & 0x00400000 ) >> 22)
+#define GET_RG_TURISMO_TRX_SX_PFD_SET (((REG32(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_)) & 0x00800000 ) >> 23)
+#define GET_RG_TURISMO_TRX_SX_PFD_SET1 (((REG32(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_)) & 0x01000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_SX_PFD_SET2 (((REG32(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_)) & 0x02000000 ) >> 25)
+#define GET_RG_TURISMO_TRX_SX_PFD_REF_EDGE (((REG32(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_)) & 0x04000000 ) >> 26)
+#define GET_RG_TURISMO_TRX_SX_PFD_DIV_EDGE (((REG32(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_)) & 0x08000000 ) >> 27)
+#define GET_RG_TURISMO_TRX_SX_PFD_TRUP (((REG32(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_)) & 0x10000000 ) >> 28)
+#define GET_RG_TURISMO_TRX_SX_PFD_TRDN (((REG32(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_)) & 0x20000000 ) >> 29)
+#define GET_RG_TURISMO_TRX_SX_PFD_TLSEL (((REG32(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_)) & 0x40000000 ) >> 30)
+#define GET_RG_TURISMO_TRX_SX_LPF_C1_BT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_LPF)) & 0x0000000f ) >> 0)
+#define GET_RG_TURISMO_TRX_SX_LPF_C2_BT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_LPF)) & 0x000000f0 ) >> 4)
+#define GET_RG_TURISMO_TRX_SX_LPF_C3_BT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_LPF)) & 0x00000100 ) >> 8)
+#define GET_RG_TURISMO_TRX_SX_LPF_R2_BT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_LPF)) & 0x00001e00 ) >> 9)
+#define GET_RG_TURISMO_TRX_SX_LPF_R3_BT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_LPF)) & 0x0000e000 ) >> 13)
+#define GET_RG_TURISMO_TRX_SX_LPF_C1_WF (((REG32(ADR_TURISMO_TRX_SX_2_4GB_LPF)) & 0x000f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_SX_LPF_C2_WF (((REG32(ADR_TURISMO_TRX_SX_2_4GB_LPF)) & 0x00f00000 ) >> 20)
+#define GET_RG_TURISMO_TRX_SX_LPF_C3_WF (((REG32(ADR_TURISMO_TRX_SX_2_4GB_LPF)) & 0x01000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_SX_LPF_R2_WF (((REG32(ADR_TURISMO_TRX_SX_2_4GB_LPF)) & 0x1e000000 ) >> 25)
+#define GET_RG_TURISMO_TRX_SX_LPF_R3_WF (((REG32(ADR_TURISMO_TRX_SX_2_4GB_LPF)) & 0xe0000000 ) >> 29)
+#define GET_RG_TURISMO_TRX_SX_VCO_ISEL_MAN (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCO)) & 0x00000001 ) >> 0)
+#define GET_RG_TURISMO_TRX_SX_VCO_ISEL_BT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCO)) & 0x0000001e ) >> 1)
+#define GET_RG_TURISMO_TRX_SX_VCO_LPM_BT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCO)) & 0x00000020 ) >> 5)
+#define GET_RG_TURISMO_TRX_SX_VCO_VCCBSEL_BT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCO)) & 0x000001c0 ) >> 6)
+#define GET_RG_TURISMO_TRX_SX_VCO_KVDOUB_BT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCO)) & 0x00000200 ) >> 9)
+#define GET_RG_TURISMO_TRX_SX_VCO_ISEL_WF (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCO)) & 0x00003c00 ) >> 10)
+#define GET_RG_TURISMO_TRX_SX_VCO_LPM_WF (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCO)) & 0x00004000 ) >> 14)
+#define GET_RG_TURISMO_TRX_SX_VCO_VCCBSEL_WF (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCO)) & 0x00038000 ) >> 15)
+#define GET_RG_TURISMO_TRX_SX_VCO_KVDOUB_WF (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCO)) & 0x00040000 ) >> 18)
+#define GET_RG_TURISMO_TRX_SX_VCO_VARBSEL (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCO)) & 0x00600000 ) >> 21)
+#define GET_RG_TURISMO_TRX_SX_VCO_RTAIL_SHIFT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCO)) & 0x00800000 ) >> 23)
+#define GET_RG_TURISMO_TRX_SX_VCO_CS_AWH (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCO)) & 0x01000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_VOBF_TXMBSEL_BT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCOBF)) & 0x00000003 ) >> 0)
+#define GET_RG_TURISMO_TRX_VOBF_TXOBSEL_BT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCOBF)) & 0x0000000c ) >> 2)
+#define GET_RG_TURISMO_TRX_VOBF_RXMBSEL_BT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCOBF)) & 0x00000030 ) >> 4)
+#define GET_RG_TURISMO_TRX_VOBF_RXOBSEL_BT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCOBF)) & 0x000000c0 ) >> 6)
+#define GET_RG_TURISMO_TRX_VOBF_TXMBSEL_WF (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCOBF)) & 0x00000c00 ) >> 10)
+#define GET_RG_TURISMO_TRX_VOBF_TXOBSEL_WF (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCOBF)) & 0x00003000 ) >> 12)
+#define GET_RG_TURISMO_TRX_VOBF_RXMBSEL_WF (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCOBF)) & 0x0000c000 ) >> 14)
+#define GET_RG_TURISMO_TRX_VOBF_RXOBSEL_WF (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCOBF)) & 0x00030000 ) >> 16)
+#define GET_RG_TURISMO_TRX_VOBF_DIVBFSEL (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCOBF)) & 0x00080000 ) >> 19)
+#define GET_RG_TURISMO_TRX_SX_VCO_TXOB_AW (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCOBF)) & 0x00100000 ) >> 20)
+#define GET_RG_TURISMO_TRX_SX_VCO_RXOB_AW (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCOBF)) & 0x00200000 ) >> 21)
+#define GET_RG_TURISMO_TRX_VOBF_CAPIMB_POL (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCOBF)) & 0x04000000 ) >> 26)
+#define GET_RG_TURISMO_TRX_VOBF_CAPIMB (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCOBF)) & 0x38000000 ) >> 27)
+#define GET_RG_TURISMO_TRX_EN_SX_VCOMON (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCOBF)) & 0x80000000 ) >> 31)
+#define GET_RG_TURISMO_TRX_SX_DIV_PREVDD (((REG32(ADR_TURISMO_TRX_SX_2_4GB_DIV_SDM)) & 0x0000000f ) >> 0)
+#define GET_RG_TURISMO_TRX_SX_DIV_PSCVDD (((REG32(ADR_TURISMO_TRX_SX_2_4GB_DIV_SDM)) & 0x000000f0 ) >> 4)
+#define GET_RG_TURISMO_TRX_SX_DIV_RST_H (((REG32(ADR_TURISMO_TRX_SX_2_4GB_DIV_SDM)) & 0x00000200 ) >> 9)
+#define GET_RG_TURISMO_TRX_SX_DIV_SDM_EDGE (((REG32(ADR_TURISMO_TRX_SX_2_4GB_DIV_SDM)) & 0x00000400 ) >> 10)
+#define GET_RG_TURISMO_TRX_SX_DIV_DMYBUF_EN (((REG32(ADR_TURISMO_TRX_SX_2_4GB_DIV_SDM)) & 0x00000800 ) >> 11)
+#define GET_RG_TURISMO_TRX_EN_SX_MOD (((REG32(ADR_TURISMO_TRX_SX_2_4GB_DIV_SDM)) & 0x00020000 ) >> 17)
+#define GET_RG_TURISMO_TRX_EN_SX_DITHER (((REG32(ADR_TURISMO_TRX_SX_2_4GB_DIV_SDM)) & 0x00040000 ) >> 18)
+#define GET_RG_TURISMO_TRX_SX_MOD_ORDER (((REG32(ADR_TURISMO_TRX_SX_2_4GB_DIV_SDM)) & 0x00180000 ) >> 19)
+#define GET_RG_TURISMO_TRX_SX_DITHER_WEIGHT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_DIV_SDM)) & 0x00600000 ) >> 21)
+#define GET_RG_TURISMO_TRX_SX_SUB_SEL_MAN (((REG32(ADR_TURISMO_TRX_SX_2_4GB_SBCAL)) & 0x00000001 ) >> 0)
+#define GET_RG_TURISMO_TRX_SX_SUB_SEL (((REG32(ADR_TURISMO_TRX_SX_2_4GB_SBCAL)) & 0x000001fe ) >> 1)
+#define GET_RG_TURISMO_TRX_SX_SUB_C0P5_DIS (((REG32(ADR_TURISMO_TRX_SX_2_4GB_SBCAL)) & 0x00000200 ) >> 9)
+#define GET_RG_TURISMO_TRX_SX_SBCAL_CT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_SBCAL)) & 0x00000c00 ) >> 10)
+#define GET_RG_TURISMO_TRX_SX_SBCAL_WT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_SBCAL)) & 0x00001000 ) >> 12)
+#define GET_RG_TURISMO_TRX_SX_SBCAL_DIFFMIN (((REG32(ADR_TURISMO_TRX_SX_2_4GB_SBCAL)) & 0x00002000 ) >> 13)
+#define GET_RG_TURISMO_TRX_SX_SBCAL_NTARG_MAN (((REG32(ADR_TURISMO_TRX_SX_2_4GB_SBCAL)) & 0x00008000 ) >> 15)
+#define GET_RG_TURISMO_TRX_SX_SBCAL_NTARG (((REG32(ADR_TURISMO_TRX_SX_2_4GB_SBCAL)) & 0xffff0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_VO_AAC_TAR_BT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_AAC)) & 0x0000000f ) >> 0)
+#define GET_RG_TURISMO_TRX_VO_AAC_IOST_BT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_AAC)) & 0x00000030 ) >> 4)
+#define GET_RG_TURISMO_TRX_VO_AAC_TAR_WF (((REG32(ADR_TURISMO_TRX_SX_2_4GB_AAC)) & 0x00000780 ) >> 7)
+#define GET_RG_TURISMO_TRX_VO_AAC_IOST_WF (((REG32(ADR_TURISMO_TRX_SX_2_4GB_AAC)) & 0x00001800 ) >> 11)
+#define GET_RG_TURISMO_TRX_VO_AAC_IMAX (((REG32(ADR_TURISMO_TRX_SX_2_4GB_AAC)) & 0x0003c000 ) >> 14)
+#define GET_RG_TURISMO_TRX_VO_AAC_INIT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_AAC)) & 0x000c0000 ) >> 18)
+#define GET_RG_TURISMO_TRX_VO_AAC_EVA_TS (((REG32(ADR_TURISMO_TRX_SX_2_4GB_AAC)) & 0x00300000 ) >> 20)
+#define GET_RG_TURISMO_TRX_VO_AAC_EN_MAN (((REG32(ADR_TURISMO_TRX_SX_2_4GB_AAC)) & 0x00800000 ) >> 23)
+#define GET_RG_TURISMO_TRX_VO_AAC_EN (((REG32(ADR_TURISMO_TRX_SX_2_4GB_AAC)) & 0x01000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_VO_AAC_EVA_MAN (((REG32(ADR_TURISMO_TRX_SX_2_4GB_AAC)) & 0x02000000 ) >> 25)
+#define GET_RG_TURISMO_TRX_VO_AAC_EVA (((REG32(ADR_TURISMO_TRX_SX_2_4GB_AAC)) & 0x04000000 ) >> 26)
+#define GET_RG_TURISMO_TRX_VO_AAC_TEST_EN (((REG32(ADR_TURISMO_TRX_SX_2_4GB_AAC)) & 0x10000000 ) >> 28)
+#define GET_RG_TURISMO_TRX_VO_AAC_TEST_SEL (((REG32(ADR_TURISMO_TRX_SX_2_4GB_AAC)) & 0x20000000 ) >> 29)
+#define GET_RG_TURISMO_TRX_SX_TTL_INIT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_TTL)) & 0x00000003 ) >> 0)
+#define GET_RG_TURISMO_TRX_SX_TTL_FPT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_TTL)) & 0x0000000c ) >> 2)
+#define GET_RG_TURISMO_TRX_SX_TTL_CPT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_TTL)) & 0x00000030 ) >> 4)
+#define GET_RG_TURISMO_TRX_SX_TTL_ACCUM (((REG32(ADR_TURISMO_TRX_SX_2_4GB_TTL)) & 0x00000180 ) >> 7)
+#define GET_RG_TURISMO_TRX_SX_TTL_SUB (((REG32(ADR_TURISMO_TRX_SX_2_4GB_TTL)) & 0x00000c00 ) >> 10)
+#define GET_RG_TURISMO_TRX_SX_TTL_SUB_INV (((REG32(ADR_TURISMO_TRX_SX_2_4GB_TTL)) & 0x00001000 ) >> 12)
+#define GET_RG_TURISMO_TRX_SX_TTL_VH (((REG32(ADR_TURISMO_TRX_SX_2_4GB_TTL)) & 0x0000c000 ) >> 14)
+#define GET_RG_TURISMO_TRX_SX_TTL_VL (((REG32(ADR_TURISMO_TRX_SX_2_4GB_TTL)) & 0x00030000 ) >> 16)
+#define GET_RG_TURISMO_TRX_SX_LPF_VTUNE_TEST (((REG32(ADR_TURISMO_TRX_SX_2_4GB_TTL)) & 0x00080000 ) >> 19)
+#define GET_RG_TURISMO_TRX_DP_BBPLL_PD (((REG32(ADR_TURISMO_TRX_DPLL_TOP_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_TURISMO_TRX_DP_BBPLL_BP (((REG32(ADR_TURISMO_TRX_DPLL_TOP_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_RG_TURISMO_TRX_EN_DP_MANUAL (((REG32(ADR_TURISMO_TRX_DPLL_TOP_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_RG_TURISMO_TRX_DP_FREF_DOUB (((REG32(ADR_TURISMO_TRX_DPLL_TOP_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_RG_TURISMO_TRX_DP_DAC320_DIVBY2 (((REG32(ADR_TURISMO_TRX_DPLL_TOP_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_RG_TURISMO_TRX_DP_ADC320_DIVBY2_BT (((REG32(ADR_TURISMO_TRX_DPLL_TOP_REGISTER)) & 0x00000020 ) >> 5)
+#define GET_RG_TURISMO_TRX_DP_ADC320_DIVBY2_WF (((REG32(ADR_TURISMO_TRX_DPLL_TOP_REGISTER)) & 0x00000040 ) >> 6)
+#define GET_RG_TURISMO_TRX_EN_DPL_MOD (((REG32(ADR_TURISMO_TRX_DPLL_TOP_REGISTER)) & 0x00000100 ) >> 8)
+#define GET_RG_TURISMO_TRX_DPL_MOD_ORDER (((REG32(ADR_TURISMO_TRX_DPLL_TOP_REGISTER)) & 0x00000600 ) >> 9)
+#define GET_RG_TURISMO_TRX_DP_REFDIV (((REG32(ADR_TURISMO_TRX_DPLL_TOP_REGISTER)) & 0x0003f800 ) >> 11)
+#define GET_RG_TURISMO_TRX_DP_FODIV (((REG32(ADR_TURISMO_TRX_DPLL_TOP_REGISTER)) & 0x01fc0000 ) >> 18)
+#define GET_RG_TURISMO_TRX_EN_LDO_DP_IQUP (((REG32(ADR_TURISMO_TRX_DPLL_TOP_REGISTER)) & 0x04000000 ) >> 26)
+#define GET_RG_TURISMO_TRX_DP_OD_TEST (((REG32(ADR_TURISMO_TRX_DPLL_TOP_REGISTER)) & 0x08000000 ) >> 27)
+#define GET_RG_TURISMO_TRX_DP_BBPLL_TESTSEL (((REG32(ADR_TURISMO_TRX_DPLL_TOP_REGISTER)) & 0x70000000 ) >> 28)
+#define GET_RG_TURISMO_TRX_DP_BBPLL_ICP (((REG32(ADR_TURISMO_TRX_DPLL_CKT_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_TURISMO_TRX_DP_BBPLL_IDUAL (((REG32(ADR_TURISMO_TRX_DPLL_CKT_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_TURISMO_TRX_DP_CP_IOSTPOL (((REG32(ADR_TURISMO_TRX_DPLL_CKT_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_RG_TURISMO_TRX_DP_CP_IOST (((REG32(ADR_TURISMO_TRX_DPLL_CKT_REGISTER)) & 0x00000060 ) >> 5)
+#define GET_RG_TURISMO_TRX_DP_PFD_PFDSEL (((REG32(ADR_TURISMO_TRX_DPLL_CKT_REGISTER)) & 0x00000080 ) >> 7)
+#define GET_RG_TURISMO_TRX_DP_BBPLL_PFD_DLY (((REG32(ADR_TURISMO_TRX_DPLL_CKT_REGISTER)) & 0x00000300 ) >> 8)
+#define GET_RG_TURISMO_TRX_DP_RP (((REG32(ADR_TURISMO_TRX_DPLL_CKT_REGISTER)) & 0x00003800 ) >> 11)
+#define GET_RG_TURISMO_TRX_DP_RHP (((REG32(ADR_TURISMO_TRX_DPLL_CKT_REGISTER)) & 0x0000c000 ) >> 14)
+#define GET_RG_TURISMO_TRX_EN_DP_VT_MON (((REG32(ADR_TURISMO_TRX_DPLL_CKT_REGISTER)) & 0x00020000 ) >> 17)
+#define GET_RG_TURISMO_TRX_DP_VT_TH_HI (((REG32(ADR_TURISMO_TRX_DPLL_CKT_REGISTER)) & 0x000c0000 ) >> 18)
+#define GET_RG_TURISMO_TRX_DP_VT_TH_LO (((REG32(ADR_TURISMO_TRX_DPLL_CKT_REGISTER)) & 0x00300000 ) >> 20)
+#define GET_RG_TURISMO_TRX_DP_BBPLL_BS (((REG32(ADR_TURISMO_TRX_DPLL_CKT_REGISTER)) & 0x1f800000 ) >> 23)
+#define GET_RG_TURISMO_TRX_DP_BBPLL_SDM_EDGE (((REG32(ADR_TURISMO_TRX_DPLL_CKT_REGISTER)) & 0x80000000 ) >> 31)
+#define GET_RG_TURISMO_TRX_DPL_RFCTRL_F (((REG32(ADR_TURISMO_TRX_DPLL_FB_DIVISION__REGISTERS)) & 0x00ffffff ) >> 0)
+#define GET_RG_TURISMO_TRX_DPL_RFCTRL_CH (((REG32(ADR_TURISMO_TRX_DPLL_FB_DIVISION__REGISTERS)) & 0xff000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG15 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER1)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG15 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER1)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG14 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER1)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG14 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER1)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG13 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER2)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG13 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER2)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG12 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER2)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG12 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER2)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG11 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER3)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG11 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER3)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG10 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER3)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG10 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER3)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG9 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER4)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG9 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER4)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG8 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER4)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG8 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER4)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG7 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER5)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG7 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER5)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG6 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER5)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG6 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER5)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG5 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER6)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG5 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER6)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG4 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER6)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG4 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER6)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG3 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER7)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG3 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER7)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG2 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER7)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG2 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER7)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG1 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER8)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG1 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER8)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG0 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER8)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG0 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER8)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG15 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER9)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG15 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER9)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG14 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER9)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG14 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER9)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG13 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER10)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG13 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER10)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG12 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER10)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG12 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER10)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG11 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER11)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG11 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER11)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG10 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER11)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG10 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER11)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG9 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER12)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG9 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER12)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG8 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER12)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG8 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER12)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG7 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER13)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG7 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER13)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG6 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER13)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG6 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER13)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG5 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER14)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG5 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER14)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG4 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER14)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG4 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER14)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG3 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER15)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG3 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER15)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG2 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER15)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG2 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER15)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG1 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER16)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG1 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER16)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG0 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER16)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG0 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER16)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_IDACAI_TZ0_COARSE4 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER17)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_IDACAQ_TZ0_COARSE4 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER17)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_IDACAI_TZ0_COARSE3 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER17)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_IDACAQ_TZ0_COARSE3 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER17)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_IDACAI_TZ0_COARSE2 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER18)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_IDACAQ_TZ0_COARSE2 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER18)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_IDACAI_TZ0_COARSE1 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER18)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_IDACAQ_TZ0_COARSE1 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER18)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_IDACAI_TZ0_COARSE0 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER19)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_IDACAQ_TZ0_COARSE0 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER19)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_IDACAI_TZ1_COARSE4 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER19)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_IDACAQ_TZ1_COARSE4 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER19)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_IDACAI_TZ1_COARSE3 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER20)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_IDACAQ_TZ1_COARSE3 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER20)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_IDACAI_TZ1_COARSE2 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER20)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_IDACAQ_TZ1_COARSE2 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER20)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_IDACAI_TZ1_COARSE1 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER21)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_IDACAQ_TZ1_COARSE1 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER21)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_IDACAI_TZ1_COARSE0 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER21)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_IDACAQ_TZ1_COARSE0 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER21)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG15 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER1)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG15 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER1)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG14 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER1)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG14 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER1)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG13 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER2)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG13 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER2)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG12 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER2)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG12 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER2)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG11 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER3)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG11 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER3)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG10 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER3)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG10 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER3)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG9 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER4)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG9 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER4)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG8 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER4)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG8 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER4)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG7 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER5)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG7 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER5)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG6 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER5)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG6 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER5)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG5 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER6)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG5 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER6)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG4 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER6)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG4 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER6)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG3 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER7)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG3 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER7)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG2 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER7)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG2 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER7)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG1 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER8)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG1 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER8)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG0 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER8)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG0 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER8)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG15 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER9)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG15 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER9)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG14 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER9)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG14 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER9)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG13 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER10)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG13 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER10)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG12 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER10)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG12 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER10)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG11 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER11)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG11 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER11)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG10 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER11)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG10 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER11)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG9 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER12)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG9 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER12)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG8 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER12)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG8 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER12)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG7 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER13)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG7 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER13)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG6 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER13)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG6 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER13)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG5 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER14)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG5 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER14)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG4 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER14)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG4 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER14)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG3 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER15)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG3 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER15)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG2 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER15)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG2 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER15)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG1 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER16)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG1 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER16)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG0 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER16)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG0 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER16)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_SX_DELAY (((REG32(ADR_TURISMO_TRX_MODE_DECODER_TIMER_REGISTER1)) & 0x0000000f ) >> 0)
+#define GET_RG_TURISMO_TRX_TXDAC_DELAY (((REG32(ADR_TURISMO_TRX_MODE_DECODER_TIMER_REGISTER1)) & 0x000000f0 ) >> 4)
+#define GET_RG_TURISMO_TRX_TXRF_DELAY (((REG32(ADR_TURISMO_TRX_MODE_DECODER_TIMER_REGISTER1)) & 0x00000f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_TXPA_DELAY (((REG32(ADR_TURISMO_TRX_MODE_DECODER_TIMER_REGISTER1)) & 0x0000f000 ) >> 12)
+#define GET_RG_TURISMO_TRX_RXRF_DELAY (((REG32(ADR_TURISMO_TRX_MODE_DECODER_TIMER_REGISTER1)) & 0x000f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_TXBTPA_DELAY (((REG32(ADR_TURISMO_TRX_MODE_DECODER_TIMER_REGISTER1)) & 0x00f00000 ) >> 20)
+#define GET_RG_TURISMO_TRX_TXDAC_T2R_DELAY (((REG32(ADR_TURISMO_TRX_WIFI_T2R_TIMER_REGISTER)) & 0x0000001f ) >> 0)
+#define GET_RG_TURISMO_TRX_TXRF_T2R_DELAY (((REG32(ADR_TURISMO_TRX_WIFI_T2R_TIMER_REGISTER)) & 0x00001f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_TXPA_T2R_DELAY (((REG32(ADR_TURISMO_TRX_WIFI_T2R_TIMER_REGISTER)) & 0x001f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_RXRF_T2R_DELAY (((REG32(ADR_TURISMO_TRX_WIFI_T2R_TIMER_REGISTER)) & 0x1f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_TXDAC_R2T_DELAY (((REG32(ADR_TURISMO_TRX_WIFI_R2T_TIMER_REGISTER)) & 0x0000001f ) >> 0)
+#define GET_RG_TURISMO_TRX_TXRF_R2T_DELAY (((REG32(ADR_TURISMO_TRX_WIFI_R2T_TIMER_REGISTER)) & 0x00001f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_TXPA_R2T_DELAY (((REG32(ADR_TURISMO_TRX_WIFI_R2T_TIMER_REGISTER)) & 0x001f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_RXRF_R2T_DELAY (((REG32(ADR_TURISMO_TRX_WIFI_R2T_TIMER_REGISTER)) & 0x1f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_WF_RX_DCCAL_DELAY (((REG32(ADR_TURISMO_TRX_CALIBRATION_TIMER_REGISTER)) & 0x00000007 ) >> 0)
+#define GET_RG_TURISMO_TRX_BT_RX_DCCAL_DELAY (((REG32(ADR_TURISMO_TRX_CALIBRATION_TIMER_REGISTER)) & 0x00000070 ) >> 4)
+#define GET_RG_TURISMO_TRX_RX_RCCAL_DELAY (((REG32(ADR_TURISMO_TRX_CALIBRATION_TIMER_REGISTER)) & 0x00000700 ) >> 8)
+#define GET_RG_TURISMO_TRX_TX_DCCAL_DELAY (((REG32(ADR_TURISMO_TRX_CALIBRATION_TIMER_REGISTER)) & 0x00007000 ) >> 12)
+#define GET_RG_TURISMO_TRX_TX_IQCAL_DELAY (((REG32(ADR_TURISMO_TRX_CALIBRATION_TIMER_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_TURISMO_TRX_RX_IQCAL_DELAY (((REG32(ADR_TURISMO_TRX_CALIBRATION_TIMER_REGISTER)) & 0x00700000 ) >> 20)
+#define GET_RG_TURISMO_TRX_RX_N_RCCAL_DELAY (((REG32(ADR_TURISMO_TRX_CALIBRATION_TIMER_REGISTER)) & 0x07000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_PGAG_RCCAL (((REG32(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER0)) & 0x0000000f ) >> 0)
+#define GET_RG_TURISMO_TRX_PGAG_TXCAL (((REG32(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER0)) & 0x000000f0 ) >> 4)
+#define GET_RG_TURISMO_TRX_TX_GAIN_TXCAL (((REG32(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER0)) & 0x00007f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_RFG_RXIQCAL (((REG32(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER0)) & 0x00030000 ) >> 16)
+#define GET_RG_TURISMO_TRX_PGAG_RXIQCAL (((REG32(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER0)) & 0x003c0000 ) >> 18)
+#define GET_RG_TURISMO_TRX_TX_GAIN_RXIQCAL (((REG32(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER0)) & 0x1fc00000 ) >> 22)
+#define GET_RG_TURISMO_TRX_RFG_DPDCAL (((REG32(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1)) & 0x00000003 ) >> 0)
+#define GET_RG_TURISMO_TRX_PGAG_DPDCAL (((REG32(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1)) & 0x0000003c ) >> 2)
+#define GET_RG_TURISMO_TRX_TX_GAIN_DPDCAL (((REG32(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1)) & 0x00001fc0 ) >> 6)
+#define GET_RG_TURISMO_TRX_IOT_ADC_CLKSEL (((REG32(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1)) & 0x00010000 ) >> 16)
+#define GET_RG_TURISMO_TRX_IOT_ADC_DNLEN (((REG32(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1)) & 0x00020000 ) >> 17)
+#define GET_RG_TURISMO_TRX_IOT_ADC_METAEN (((REG32(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1)) & 0x00040000 ) >> 18)
+#define GET_RG_TURISMO_TRX_IOT_ADC_TFLAG (((REG32(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1)) & 0x00080000 ) >> 19)
+#define GET_RG_TURISMO_TRX_IOT_ADC_ICMP (((REG32(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1)) & 0x00300000 ) >> 20)
+#define GET_RG_TURISMO_TRX_IOT_ADC_VCMI (((REG32(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1)) & 0x00c00000 ) >> 22)
+#define GET_RG_TURISMO_TRX_IOT_ADC_CLOAD (((REG32(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1)) & 0x03000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_IOT_ADC_CLK_DIV (((REG32(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1)) & 0x0c000000 ) >> 26)
+#define GET_RG_TURISMO_TRX_IOT_ADC_CLK_SH_DUTY (((REG32(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1)) & 0x10000000 ) >> 28)
+#define GET_DB_TURISMO_TRX_AD_ADC_I_OUT (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_ADC)) & 0x000003ff ) >> 0)
+#define GET_DB_TURISMO_TRX_AD_ADC_Q_OUT (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_ADC)) & 0x000ffc00 ) >> 10)
+#define GET_DB_TURISMO_TRX_AD_RX_RSSIADC (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_ADC)) & 0x00f00000 ) >> 20)
+#define GET_DB_TURISMO_TRX_DA_SARADC_BIT (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_ADC)) & 0x3f000000 ) >> 24)
+#define GET_TURISMO_TRX_SAR_ADC_FSM_RDY (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_ADC)) & 0x40000000 ) >> 30)
+#define GET_DB_TURISMO_TRX_DA_SX_SUB_SEL (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_1)) & 0x000000ff ) >> 0)
+#define GET_DB_TURISMO_TRX_DA_SX_VCO_ISEL (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_1)) & 0x00000f00 ) >> 8)
+#define GET_DB_TURISMO_TRX_VO_AAC_COMPOUT (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_1)) & 0x00001000 ) >> 12)
+#define GET_DB_TURISMO_TRX_SX_TTL_VT_DET (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_1)) & 0x0000c000 ) >> 14)
+#define GET_DB_TURISMO_TRX_AD_DP_VT_MON_Q (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_1)) & 0x00030000 ) >> 16)
+#define GET_DB_TURISMO_TRX_AD_IOT_ADC_OUT (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_1)) & 0x3ff00000 ) >> 20)
+#define GET_DB_TURISMO_TRX_SX_SBCAL_NCOUNT (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_2)) & 0x0000ffff ) >> 0)
+#define GET_DB_TURISMO_TRX_SX_SBCAL_NTARGET (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_2)) & 0xffff0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_5G_TX_TRSW_MANUAL (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_TURISMO_TRX_5G_EN_TX_TRSW (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_RG_TURISMO_TRX_5G_RX_LNA_MANUAL (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_RG_TURISMO_TRX_5G_EN_RX_LNA (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_RG_TURISMO_TRX_5G_RX_MIXER_MANUAL (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_RG_TURISMO_TRX_5G_EN_RX_MIXER (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000020 ) >> 5)
+#define GET_RG_TURISMO_TRX_5G_RX_DIV2_MANUAL (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000040 ) >> 6)
+#define GET_RG_TURISMO_TRX_5G_EN_RX_DIV2 (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000080 ) >> 7)
+#define GET_RG_TURISMO_TRX_5G_RX_LOBUF_MANUAL (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000100 ) >> 8)
+#define GET_RG_TURISMO_TRX_5G_EN_RX_LOBUF (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000200 ) >> 9)
+#define GET_RG_TURISMO_TRX_5G_RX_TZ_MANUAL (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000400 ) >> 10)
+#define GET_RG_TURISMO_TRX_5G_EN_RX_TZ (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_RG_TURISMO_TRX_5G_TX_PA_MANUAL (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00001000 ) >> 12)
+#define GET_RG_TURISMO_TRX_5G_EN_TX_PA (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00002000 ) >> 13)
+#define GET_RG_TURISMO_TRX_5G_TX_MOD_MANUAL (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_RG_TURISMO_TRX_5G_EN_TX_MOD (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00008000 ) >> 15)
+#define GET_RG_TURISMO_TRX_5G_TX_DIV2_MANUAL (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00040000 ) >> 18)
+#define GET_RG_TURISMO_TRX_5G_EN_TX_DIV2 (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00080000 ) >> 19)
+#define GET_RG_TURISMO_TRX_5G_TX_DIV2_BUF_MANUAL (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00100000 ) >> 20)
+#define GET_RG_TURISMO_TRX_5G_EN_TX_DIV2_BUF (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00200000 ) >> 21)
+#define GET_RG_TURISMO_TRX_5G_RX_TZ_OUT_TRISTATE_MANUAL (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00400000 ) >> 22)
+#define GET_RG_TURISMO_TRX_5G_RX_TZ_OUT_TRISTATE (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00800000 ) >> 23)
+#define GET_RG_TURISMO_TRX_5G_TX_SELF_MIXER_MANUAL (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x01000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_5G_EN_TX_SELF_MIXER (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x02000000 ) >> 25)
+#define GET_RG_TURISMO_TRX_5G_RX_IQCAL_MANUAL (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x04000000 ) >> 26)
+#define GET_RG_TURISMO_TRX_5G_EN_RX_IQCAL (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x08000000 ) >> 27)
+#define GET_RG_TURISMO_TRX_5G_TX_DPD_MANUAL (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x10000000 ) >> 28)
+#define GET_RG_TURISMO_TRX_5G_EN_TX_DPD (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x20000000 ) >> 29)
+#define GET_RG_TURISMO_TRX_5G_EN_TX_TSSI (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x40000000 ) >> 30)
+#define GET_RG_TURISMO_TRX_5G_LDO_LEVEL_RX_FE (((REG32(ADR_TURISMO_TRX_5G_LDO_REGISTER)) & 0x00000007 ) >> 0)
+#define GET_RG_TURISMO_TRX_5G_EN_LDO_RX_FE_BYP (((REG32(ADR_TURISMO_TRX_5G_LDO_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_RG_TURISMO_TRX_SX5GB_LDO_CP_LEVEL (((REG32(ADR_TURISMO_TRX_5G_LDO_REGISTER)) & 0x00000070 ) >> 4)
+#define GET_RG_TURISMO_TRX_EN_LDO_5G_CP_BYP (((REG32(ADR_TURISMO_TRX_5G_LDO_REGISTER)) & 0x00000080 ) >> 7)
+#define GET_RG_TURISMO_TRX_SX5GB_LDO_LO_LEVEL (((REG32(ADR_TURISMO_TRX_5G_LDO_REGISTER)) & 0x00000700 ) >> 8)
+#define GET_RG_TURISMO_TRX_EN_LDO_5G_LO_BYP (((REG32(ADR_TURISMO_TRX_5G_LDO_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_RG_TURISMO_TRX_SX5GB_LDO_VCO_LEVEL (((REG32(ADR_TURISMO_TRX_5G_LDO_REGISTER)) & 0x00007000 ) >> 12)
+#define GET_RG_TURISMO_TRX_SX5GB_LDO_DIV_LEVEL (((REG32(ADR_TURISMO_TRX_5G_LDO_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_TURISMO_TRX_EN_LDO_5G_DIV_BYP (((REG32(ADR_TURISMO_TRX_5G_LDO_REGISTER)) & 0x00080000 ) >> 19)
+#define GET_RG_TURISMO_TRX_5G_EN_LDO_RX_FE (((REG32(ADR_TURISMO_TRX_5G_LDO_REGISTER)) & 0x01000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_5G_EN_IREF_RX (((REG32(ADR_TURISMO_TRX_5G_LDO_REGISTER)) & 0x02000000 ) >> 25)
+#define GET_RG_TURISMO_TRX_5G_EN_LDO_RX_FE_FC (((REG32(ADR_TURISMO_TRX_5G_LDO_REGISTER)) & 0x04000000 ) >> 26)
+#define GET_RG_TURISMO_TRX_5G_EN_LDO_RX_FE_IQUP (((REG32(ADR_TURISMO_TRX_5G_LDO_REGISTER)) & 0x08000000 ) >> 27)
+#define GET_RG_TURISMO_TRX_5G_RX_SCA_MANUAL (((REG32(ADR_TURISMO_TRX_5G_RX_REGISTER1)) & 0x00000001 ) >> 0)
+#define GET_RG_TURISMO_TRX_5G_RX_SCA_MA (((REG32(ADR_TURISMO_TRX_5G_RX_REGISTER1)) & 0x0000000e ) >> 1)
+#define GET_RG_TURISMO_TRX_5G_RX_SCA_LOAD (((REG32(ADR_TURISMO_TRX_5G_RX_REGISTER1)) & 0x00000070 ) >> 4)
+#define GET_RG_TURISMO_TRX_5G_RX_LNA_TRI_SEL (((REG32(ADR_TURISMO_TRX_5G_RX_REGISTER1)) & 0x00000300 ) >> 8)
+#define GET_RG_TURISMO_TRX_5G_RX_LNA_SETTLE (((REG32(ADR_TURISMO_TRX_5G_RX_REGISTER1)) & 0x00000c00 ) >> 10)
+#define GET_RG_TURISMO_TRX_5G_RX_GM_IDB (((REG32(ADR_TURISMO_TRX_5G_RX_REGISTER1)) & 0x00001000 ) >> 12)
+#define GET_RG_TURISMO_TRX_5G_GM_BIAS (((REG32(ADR_TURISMO_TRX_5G_RX_REGISTER1)) & 0x00006000 ) >> 13)
+#define GET_RG_TURISMO_TRX_5G_RX_DIV2_BUF (((REG32(ADR_TURISMO_TRX_5G_RX_REGISTER1)) & 0x00030000 ) >> 16)
+#define GET_RG_TURISMO_TRX_5G_RX_DIV2_CML (((REG32(ADR_TURISMO_TRX_5G_RX_REGISTER1)) & 0x000c0000 ) >> 18)
+#define GET_RG_TURISMO_TRX_5G_RX_DIV_CMLISEL (((REG32(ADR_TURISMO_TRX_5G_RX_REGISTER1)) & 0x00300000 ) >> 20)
+#define GET_RG_TURISMO_TRX_5G_RX_DIV_PREBUFS2 (((REG32(ADR_TURISMO_TRX_5G_RX_REGISTER1)) & 0x00400000 ) >> 22)
+#define GET_RG_TURISMO_TRX_5G_RX_TZ_COURSE (((REG32(ADR_TURISMO_TRX_5G_RX_REGISTER1)) & 0x03000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_5G_TX_DPDGM_BIAS (((REG32(ADR_TURISMO_TRX_5G_RX_REGISTER1)) & 0xf0000000 ) >> 28)
+#define GET_RG_TURISMO_TRX_5G_TX_DPD_DIV (((REG32(ADR_TURISMO_TRX_5G_RX_REGISTER2)) & 0x0000000f ) >> 0)
+#define GET_RG_TURISMO_TRX_5G_TX_TSSI_BIAS (((REG32(ADR_TURISMO_TRX_5G_RX_REGISTER2)) & 0x00000070 ) >> 4)
+#define GET_RG_TURISMO_TRX_5G_TX_TSSI_DIV (((REG32(ADR_TURISMO_TRX_5G_RX_REGISTER2)) & 0x00000700 ) >> 8)
+#define GET_RG_TURISMO_TRX_5G_TX_TSSI_TEST (((REG32(ADR_TURISMO_TRX_5G_RX_REGISTER2)) & 0x00003000 ) >> 12)
+#define GET_RG_TURISMO_TRX_5G_TX_TSSI_TESTMODE (((REG32(ADR_TURISMO_TRX_5G_RX_REGISTER2)) & 0x00004000 ) >> 14)
+#define GET_RG_TURISMO_TRX_5G_RX_ADC_ICMP (((REG32(ADR_TURISMO_TRX_5G_RX_REGISTER2)) & 0x00030000 ) >> 16)
+#define GET_RG_TURISMO_TRX_5G_RX_ADC_VCMI (((REG32(ADR_TURISMO_TRX_5G_RX_REGISTER2)) & 0x000c0000 ) >> 18)
+#define GET_RG_TURISMO_TRX_5G_RX_ADC_CLOAD (((REG32(ADR_TURISMO_TRX_5G_RX_REGISTER2)) & 0x00300000 ) >> 20)
+#define GET_RG_TURISMO_TRX_5G_TXPGA_CAPSW_MANUAL (((REG32(ADR_TURISMO_TRX_5G_TX_FE_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_TURISMO_TRX_5G_TXPGA_CAPSW (((REG32(ADR_TURISMO_TRX_5G_TX_FE_REGISTER)) & 0x0000000e ) >> 1)
+#define GET_RG_TURISMO_TRX_5G_TX_ADDGMCELL (((REG32(ADR_TURISMO_TRX_5G_TX_FE_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_RG_TURISMO_TRX_5G_PACELL_EN (((REG32(ADR_TURISMO_TRX_5G_TX_FE_REGISTER)) & 0x000000e0 ) >> 5)
+#define GET_RG_TURISMO_TRX_5G_PABIAS_CTRL (((REG32(ADR_TURISMO_TRX_5G_TX_FE_REGISTER)) & 0x00000f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_5G_TX_PAFB_EN (((REG32(ADR_TURISMO_TRX_5G_TX_FE_REGISTER)) & 0x00001000 ) >> 12)
+#define GET_RG_TURISMO_TRX_5G_TX_PA1_VCAS (((REG32(ADR_TURISMO_TRX_5G_TX_FE_REGISTER)) & 0x0000e000 ) >> 13)
+#define GET_RG_TURISMO_TRX_5G_TX_PA2_VCAS (((REG32(ADR_TURISMO_TRX_5G_TX_FE_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_TURISMO_TRX_5G_TX_PA3_VCAS (((REG32(ADR_TURISMO_TRX_5G_TX_FE_REGISTER)) & 0x00700000 ) >> 20)
+#define GET_RG_TURISMO_TRX_5G_TX_DIV_PREBUFS2 (((REG32(ADR_TURISMO_TRX_5G_TX_FE_REGISTER)) & 0x00800000 ) >> 23)
+#define GET_RG_TURISMO_TRX_5G_TX_DIV_CMLISEL (((REG32(ADR_TURISMO_TRX_5G_TX_FE_REGISTER)) & 0x03000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_5G_TX_DIV_CMLVSEL (((REG32(ADR_TURISMO_TRX_5G_TX_FE_REGISTER)) & 0x0c000000 ) >> 26)
+#define GET_RG_TURISMO_TRX_5G_TX_DIV_VSET (((REG32(ADR_TURISMO_TRX_5G_TX_FE_REGISTER)) & 0x30000000 ) >> 28)
+#define GET_RG_TURISMO_TRX_5G_TX_LOBUF_VSET (((REG32(ADR_TURISMO_TRX_5G_TX_FE_REGISTER)) & 0xc0000000 ) >> 30)
+#define GET_RG_TURISMO_TRX_5G_TXPGA_MAIN (((REG32(ADR_TURISMO_TRX_5G_TX_REGISTER)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_5G_TXPGA_STEER (((REG32(ADR_TURISMO_TRX_5G_TX_REGISTER)) & 0x00000fc0 ) >> 6)
+#define GET_RG_TURISMO_TRX_5G_TXMOD_GMCELL (((REG32(ADR_TURISMO_TRX_5G_TX_REGISTER)) & 0x00003000 ) >> 12)
+#define GET_RG_TURISMO_TRX_5G_TX_GAIN_OFFSET (((REG32(ADR_TURISMO_TRX_5G_TX_REGISTER)) & 0x000f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_5G_TX_GAIN (((REG32(ADR_TURISMO_TRX_5G_TX_REGISTER)) & 0x07f00000 ) >> 20)
+#define GET_RG_TURISMO_TRX_5G_RX_HG_LNA_GC (((REG32(ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_TURISMO_TRX_5G_RX_HG_TZ_GC (((REG32(ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_TURISMO_TRX_5G_RX_HG_LNAHGN_BIAS (((REG32(ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER)) & 0x000000f0 ) >> 4)
+#define GET_RG_TURISMO_TRX_5G_RX_HG_LNAHGP_BIAS (((REG32(ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER)) & 0x00000f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_5G_RX_HG_LNALG_BIAS (((REG32(ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER)) & 0x0000f000 ) >> 12)
+#define GET_RG_TURISMO_TRX_5G_RX_HG_TZ_CAP (((REG32(ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_TURISMO_TRX_5G_RX_HG_SQDC (((REG32(ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER)) & 0x00380000 ) >> 19)
+#define GET_RG_TURISMO_TRX_5G_RX_HG_DIV2_CORE (((REG32(ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER)) & 0x00c00000 ) >> 22)
+#define GET_RG_TURISMO_TRX_5G_RX_HG_TZ_GC_BOOST (((REG32(ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER)) & 0x03000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_5G_RX_HG_TZI (((REG32(ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER)) & 0x1c000000 ) >> 26)
+#define GET_RG_TURISMO_TRX_5G_RX_HG_TZ_VCM (((REG32(ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER)) & 0xe0000000 ) >> 29)
+#define GET_RG_TURISMO_TRX_5G_RX_MG_LNA_GC (((REG32(ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_TURISMO_TRX_5G_RX_MG_TZ_GC (((REG32(ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_TURISMO_TRX_5G_RX_MG_LNAHGN_BIAS (((REG32(ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER)) & 0x000000f0 ) >> 4)
+#define GET_RG_TURISMO_TRX_5G_RX_MG_LNAHGP_BIAS (((REG32(ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER)) & 0x00000f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_5G_RX_MG_LNALG_BIAS (((REG32(ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER)) & 0x0000f000 ) >> 12)
+#define GET_RG_TURISMO_TRX_5G_RX_MG_TZ_CAP (((REG32(ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_TURISMO_TRX_5G_RX_MG_SQDC (((REG32(ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER)) & 0x00380000 ) >> 19)
+#define GET_RG_TURISMO_TRX_5G_RX_MG_DIV2_CORE (((REG32(ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER)) & 0x00c00000 ) >> 22)
+#define GET_RG_TURISMO_TRX_5G_RX_MG_TZ_GC_BOOST (((REG32(ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER)) & 0x03000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_5G_RX_MG_TZI (((REG32(ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER)) & 0x1c000000 ) >> 26)
+#define GET_RG_TURISMO_TRX_5G_RX_MG_TZ_VCM (((REG32(ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER)) & 0xe0000000 ) >> 29)
+#define GET_RG_TURISMO_TRX_5G_RX_LG_LNA_GC (((REG32(ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_TURISMO_TRX_5G_RX_LG_TZ_GC (((REG32(ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_TURISMO_TRX_5G_RX_LG_LNAHGN_BIAS (((REG32(ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER)) & 0x000000f0 ) >> 4)
+#define GET_RG_TURISMO_TRX_5G_RX_LG_LNAHGP_BIAS (((REG32(ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER)) & 0x00000f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_5G_RX_LG_LNALG_BIAS (((REG32(ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER)) & 0x0000f000 ) >> 12)
+#define GET_RG_TURISMO_TRX_5G_RX_LG_TZ_CAP (((REG32(ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_TURISMO_TRX_5G_RX_LG_SQDC (((REG32(ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER)) & 0x00380000 ) >> 19)
+#define GET_RG_TURISMO_TRX_5G_RX_LG_DIV2_CORE (((REG32(ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER)) & 0x00c00000 ) >> 22)
+#define GET_RG_TURISMO_TRX_5G_RX_LG_TZ_GC_BOOST (((REG32(ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER)) & 0x03000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_5G_RX_LG_TZI (((REG32(ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER)) & 0x1c000000 ) >> 26)
+#define GET_RG_TURISMO_TRX_5G_RX_LG_TZ_VCM (((REG32(ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER)) & 0xe0000000 ) >> 29)
+#define GET_RG_TURISMO_TRX_5G_RX_ULG_LNA_GC (((REG32(ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_TURISMO_TRX_5G_RX_ULG_TZ_GC (((REG32(ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_TURISMO_TRX_5G_RX_ULG_LNAHGN_BIAS (((REG32(ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER)) & 0x000000f0 ) >> 4)
+#define GET_RG_TURISMO_TRX_5G_RX_ULG_LNAHGP_BIAS (((REG32(ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER)) & 0x00000f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_5G_RX_ULG_LNALG_BIAS (((REG32(ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER)) & 0x0000f000 ) >> 12)
+#define GET_RG_TURISMO_TRX_5G_RX_ULG_TZ_CAP (((REG32(ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_TURISMO_TRX_5G_RX_ULG_SQDC (((REG32(ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER)) & 0x00380000 ) >> 19)
+#define GET_RG_TURISMO_TRX_5G_RX_ULG_DIV2_CORE (((REG32(ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER)) & 0x00c00000 ) >> 22)
+#define GET_RG_TURISMO_TRX_5G_RX_ULG_TZ_GC_BOOST (((REG32(ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER)) & 0x03000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_5G_RX_ULG_TZI (((REG32(ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER)) & 0x1c000000 ) >> 26)
+#define GET_RG_TURISMO_TRX_5G_RX_ULG_TZ_VCM (((REG32(ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER)) & 0xe0000000 ) >> 29)
+#define GET_RG_TURISMO_TRX_5G_TX_DACI1ST (((REG32(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_TURISMO_TRX_5G_TX_DACLPF_ICOARSE (((REG32(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_TURISMO_TRX_5G_TX_DACLPF_IFINE (((REG32(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER)) & 0x00000030 ) >> 4)
+#define GET_RG_TURISMO_TRX_5G_TX_DACLPF_VCM (((REG32(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER)) & 0x000000c0 ) >> 6)
+#define GET_RG_TURISMO_TRX_5G_TX_DAC_IBIAS (((REG32(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER)) & 0x00000300 ) >> 8)
+#define GET_RG_TURISMO_TRX_5G_TX_DAC_IATTN (((REG32(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER)) & 0x00000400 ) >> 10)
+#define GET_RG_TURISMO_TRX_5G_TXLPF_BOOSTI (((REG32(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_RG_TURISMO_TRX_5G_TX_DAC_RCAL (((REG32(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER)) & 0x00003000 ) >> 12)
+#define GET_RG_TURISMO_TRX_5G_TX_DAC_CKEDGE_SEL (((REG32(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_RG_TURISMO_TRX_5G_TX_DAC_OS (((REG32(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_TURISMO_TRX_5G_TX_DAC_IOFFSET (((REG32(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER)) & 0x00f00000 ) >> 20)
+#define GET_RG_TURISMO_TRX_5G_TX_DAC_QOFFSET (((REG32(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER)) & 0x0f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_SX5GB_RFCTRL_F (((REG32(ADR_TURISMO_TRX_SX_5GB_FRACTIONAL_AND_INTEGER_8BITS)) & 0x00ffffff ) >> 0)
+#define GET_RG_TURISMO_TRX_SX5GB_RFCTRL_CH_7_0 (((REG32(ADR_TURISMO_TRX_SX_5GB_FRACTIONAL_AND_INTEGER_8BITS)) & 0xff000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_SX5GB_RFCTRL_CH_10_8 (((REG32(ADR_TURISMO_TRX_SX_5GB_REGISTER_INT3BIT___CH_TABLE)) & 0x00000007 ) >> 0)
+#define GET_RG_TURISMO_TRX_SX5GB_RFCH_MAP_EN (((REG32(ADR_TURISMO_TRX_SX_5GB_REGISTER_INT3BIT___CH_TABLE)) & 0x00000010 ) >> 4)
+#define GET_RG_TURISMO_TRX_SX5GB_LO_TIMES (((REG32(ADR_TURISMO_TRX_SX_5GB_REGISTER_INT3BIT___CH_TABLE)) & 0x00000020 ) >> 5)
+#define GET_RG_TURISMO_TRX_SX5GB_CHANNEL (((REG32(ADR_TURISMO_TRX_SX_5GB_REGISTER_INT3BIT___CH_TABLE)) & 0x0000ff00 ) >> 8)
+#define GET_RG_TURISMO_TRX_SX_5GB_EN_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000001 ) >> 0)
+#define GET_RG_TURISMO_TRX_SX_5GB_EN (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000002 ) >> 1)
+#define GET_RG_TURISMO_TRX_EN_SX5GB_CP_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000004 ) >> 2)
+#define GET_RG_TURISMO_TRX_EN_SX5GB_CP (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000008 ) >> 3)
+#define GET_RG_TURISMO_TRX_EN_SX5GB_DIV_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000010 ) >> 4)
+#define GET_RG_TURISMO_TRX_EN_SX5GB_DIV (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000020 ) >> 5)
+#define GET_RG_TURISMO_TRX_EN_SX5GB_VCO_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000040 ) >> 6)
+#define GET_RG_TURISMO_TRX_EN_SX5GB_VCO (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000080 ) >> 7)
+#define GET_RG_TURISMO_TRX_SX5GB_PFD_RST_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000100 ) >> 8)
+#define GET_RG_TURISMO_TRX_SX5GB_PFD_RST (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000200 ) >> 9)
+#define GET_RG_TURISMO_TRX_SX5GB_UOP_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000400 ) >> 10)
+#define GET_RG_TURISMO_TRX_SX5GB_UOP_EN (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000800 ) >> 11)
+#define GET_RG_TURISMO_TRX_EN_SX5GB_HSDIV_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00001000 ) >> 12)
+#define GET_RG_TURISMO_TRX_EN_SX5GB_HSDIV (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00002000 ) >> 13)
+#define GET_RG_TURISMO_TRX_EN_HSDIV_OBF_SX_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00004000 ) >> 14)
+#define GET_RG_TURISMO_TRX_EN_HSDIV_OBF_SX (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00008000 ) >> 15)
+#define GET_RG_TURISMO_TRX_EN_HSDIV_OBF_MX_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00010000 ) >> 16)
+#define GET_RG_TURISMO_TRX_EN_HSDIV_OBF_MX (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00020000 ) >> 17)
+#define GET_RG_TURISMO_TRX_EN_SX_MIX_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00040000 ) >> 18)
+#define GET_RG_TURISMO_TRX_EN_SX_MIX (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00080000 ) >> 19)
+#define GET_RG_TURISMO_TRX_EN_SX_REP_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00100000 ) >> 20)
+#define GET_RG_TURISMO_TRX_EN_SX_REP (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00200000 ) >> 21)
+#define GET_RG_TURISMO_TRX_SX5GB_SBCAL_DIS (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00400000 ) >> 22)
+#define GET_RG_TURISMO_TRX_SX5GB_SBCAL_2ND_DIS (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00800000 ) >> 23)
+#define GET_RG_TURISMO_TRX_SX5GB_SBCAL_AW (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x01000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_SX5GB_VOAAC_DIS (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x02000000 ) >> 25)
+#define GET_RG_TURISMO_TRX_SX5GB_MIXAAC_DIS (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x04000000 ) >> 26)
+#define GET_RG_TURISMO_TRX_SX5GB_REPAAC_DIS (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x08000000 ) >> 27)
+#define GET_RG_TURISMO_TRX_SX5GB_TTL_DIS (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x10000000 ) >> 28)
+#define GET_RG_TURISMO_TRX_SX5GB_CAL_INIT (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0xe0000000 ) >> 29)
+#define GET_RG_TURISMO_TRX_EN_SX5GB_LDO_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_TURISMO_TRX_EN_LDO_5G_CP (((REG32(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_RG_TURISMO_TRX_EN_LDO_5G_DIV (((REG32(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_RG_TURISMO_TRX_EN_LDO_5G_LO (((REG32(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_RG_TURISMO_TRX_EN_LDO_5G_VCO (((REG32(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_RG_TURISMO_TRX_EN_LDO_5G_VCO_PSW (((REG32(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER)) & 0x00000200 ) >> 9)
+#define GET_RG_TURISMO_TRX_EN_LDO_5G_VCO_VDD33 (((REG32(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER)) & 0x00000400 ) >> 10)
+#define GET_RG_TURISMO_TRX_EN_LDO_5G_CP_IQUP (((REG32(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_RG_TURISMO_TRX_EN_LDO_5G_DIV_IQUP (((REG32(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER)) & 0x00001000 ) >> 12)
+#define GET_RG_TURISMO_TRX_EN_LDO_5G_LO_IQUP (((REG32(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER)) & 0x00002000 ) >> 13)
+#define GET_RG_TURISMO_TRX_EN_LDO_5G_VCO_IQUP (((REG32(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_RG_TURISMO_TRX_SX5GB_LDO_FCOFFT (((REG32(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER)) & 0x00380000 ) >> 19)
+#define GET_RG_TURISMO_TRX_LDO_5G_CP_FC_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER)) & 0x00400000 ) >> 22)
+#define GET_RG_TURISMO_TRX_LDO_5G_CP_FC (((REG32(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER)) & 0x00800000 ) >> 23)
+#define GET_RG_TURISMO_TRX_LDO_5G_DIV_FC_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER)) & 0x01000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_LDO_5G_DIV_FC (((REG32(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER)) & 0x02000000 ) >> 25)
+#define GET_RG_TURISMO_TRX_LDO_5G_LO_FC_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER)) & 0x04000000 ) >> 26)
+#define GET_RG_TURISMO_TRX_LDO_5G_LO_FC (((REG32(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER)) & 0x08000000 ) >> 27)
+#define GET_RG_TURISMO_TRX_LDO_5G_VCO_FC_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER)) & 0x10000000 ) >> 28)
+#define GET_RG_TURISMO_TRX_LDO_5G_VCO_FC (((REG32(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER)) & 0x20000000 ) >> 29)
+#define GET_RG_TURISMO_TRX_LDO_5G_VCO_RCF (((REG32(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER)) & 0xc0000000 ) >> 30)
+#define GET_RG_TURISMO_TRX_SX5GB_CP_ISEL (((REG32(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_)) & 0x0000000f ) >> 0)
+#define GET_RG_TURISMO_TRX_SX5GB_CP_ISEL50U (((REG32(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_)) & 0x00000010 ) >> 4)
+#define GET_RG_TURISMO_TRX_SX5GB_CP_KP_DOUB (((REG32(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_)) & 0x00000020 ) >> 5)
+#define GET_RG_TURISMO_TRX_SX5GB_CP_IOST_POL (((REG32(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_)) & 0x00000080 ) >> 7)
+#define GET_RG_TURISMO_TRX_SX5GB_CP_IOST (((REG32(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_)) & 0x00000700 ) >> 8)
+#define GET_RG_TURISMO_TRX_SX5GB_PFD_SEL (((REG32(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_)) & 0x00001000 ) >> 12)
+#define GET_RG_TURISMO_TRX_SX5GB_PFD_SET (((REG32(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_)) & 0x00002000 ) >> 13)
+#define GET_RG_TURISMO_TRX_SX5GB_PFD_SET1 (((REG32(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_)) & 0x00004000 ) >> 14)
+#define GET_RG_TURISMO_TRX_SX5GB_PFD_SET2 (((REG32(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_)) & 0x00008000 ) >> 15)
+#define GET_RG_TURISMO_TRX_SX5GB_PFD_TRUP (((REG32(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_)) & 0x00010000 ) >> 16)
+#define GET_RG_TURISMO_TRX_SX5GB_PFD_TRDN (((REG32(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_)) & 0x00020000 ) >> 17)
+#define GET_RG_TURISMO_TRX_SX5GB_PFD_TLSEL (((REG32(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_)) & 0x00040000 ) >> 18)
+#define GET_RG_TURISMO_TRX_SX5GB_PFD_REF_EDGE (((REG32(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_)) & 0x00080000 ) >> 19)
+#define GET_RG_TURISMO_TRX_SX5GB_PFD_DIV_EDGE (((REG32(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_)) & 0x00100000 ) >> 20)
+#define GET_RG_TURISMO_TRX_SX5GB_LPF_C1 (((REG32(ADR_TURISMO_TRX_SX_5GB_LPF_TTL)) & 0x0000000f ) >> 0)
+#define GET_RG_TURISMO_TRX_SX5GB_LPF_C2 (((REG32(ADR_TURISMO_TRX_SX_5GB_LPF_TTL)) & 0x000000f0 ) >> 4)
+#define GET_RG_TURISMO_TRX_SX5GB_LPF_C3 (((REG32(ADR_TURISMO_TRX_SX_5GB_LPF_TTL)) & 0x00000100 ) >> 8)
+#define GET_RG_TURISMO_TRX_SX5GB_LPF_R2 (((REG32(ADR_TURISMO_TRX_SX_5GB_LPF_TTL)) & 0x00001e00 ) >> 9)
+#define GET_RG_TURISMO_TRX_SX5GB_LPF_R3 (((REG32(ADR_TURISMO_TRX_SX_5GB_LPF_TTL)) & 0x0000e000 ) >> 13)
+#define GET_RG_TURISMO_TRX_SX5GB_TTL_INIT (((REG32(ADR_TURISMO_TRX_SX_5GB_LPF_TTL)) & 0x00030000 ) >> 16)
+#define GET_RG_TURISMO_TRX_SX5GB_TTL_FPT (((REG32(ADR_TURISMO_TRX_SX_5GB_LPF_TTL)) & 0x000c0000 ) >> 18)
+#define GET_RG_TURISMO_TRX_SX5GB_TTL_CPT (((REG32(ADR_TURISMO_TRX_SX_5GB_LPF_TTL)) & 0x00300000 ) >> 20)
+#define GET_RG_TURISMO_TRX_SX5GB_TTL_ACCUM (((REG32(ADR_TURISMO_TRX_SX_5GB_LPF_TTL)) & 0x00c00000 ) >> 22)
+#define GET_RG_TURISMO_TRX_SX5GB_TTL_SUB (((REG32(ADR_TURISMO_TRX_SX_5GB_LPF_TTL)) & 0x03000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_SX5GB_TTL_SUB_INV (((REG32(ADR_TURISMO_TRX_SX_5GB_LPF_TTL)) & 0x04000000 ) >> 26)
+#define GET_RG_TURISMO_TRX_SX5GB_TTL_VH (((REG32(ADR_TURISMO_TRX_SX_5GB_LPF_TTL)) & 0x18000000 ) >> 27)
+#define GET_RG_TURISMO_TRX_SX5GB_TTL_VL (((REG32(ADR_TURISMO_TRX_SX_5GB_LPF_TTL)) & 0x60000000 ) >> 29)
+#define GET_RG_TURISMO_TRX_SX5GB_LPF_VTUNE_TEST (((REG32(ADR_TURISMO_TRX_SX_5GB_LPF_TTL)) & 0x80000000 ) >> 31)
+#define GET_RG_TURISMO_TRX_SX5GB_VCO_ISEL_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN)) & 0x00000001 ) >> 0)
+#define GET_RG_TURISMO_TRX_SX5GB_VCO_ISEL (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN)) & 0x0000001e ) >> 1)
+#define GET_RG_TURISMO_TRX_SX5GB_VCO_VCCBSEL (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN)) & 0x000001c0 ) >> 6)
+#define GET_RG_TURISMO_TRX_SX5GB_VCO_KVDOUB (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN)) & 0x00000200 ) >> 9)
+#define GET_RG_TURISMO_TRX_SX5GB_VCO_VARBSEL (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN)) & 0x00001800 ) >> 11)
+#define GET_RG_TURISMO_TRX_SX5GB_VCO_RTAIL_SHIFT (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN)) & 0x00002000 ) >> 13)
+#define GET_RG_TURISMO_TRX_SX5GB_VCO_CS_AWH (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN)) & 0x00004000 ) >> 14)
+#define GET_RG_TURISMO_TRX_HSDIV_INBFSEL (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN)) & 0x00018000 ) >> 15)
+#define GET_RG_TURISMO_TRX_HSDIV_OBFMX_SEL (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN)) & 0x00020000 ) >> 17)
+#define GET_RG_TURISMO_TRX_HSDIV_OBFSX_SEL (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN)) & 0x00040000 ) >> 18)
+#define GET_RG_TURISMO_TRX_HSDIV_VRSEL (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN)) & 0x00180000 ) >> 19)
+#define GET_RG_TURISMO_TRX_SXMIX_IBIAS_SEL (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN)) & 0x00600000 ) >> 21)
+#define GET_RG_TURISMO_TRX_SXMIX_SWB_SEL (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN)) & 0x01800000 ) >> 23)
+#define GET_RG_TURISMO_TRX_SXMIX_GMSEL (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN)) & 0x06000000 ) >> 25)
+#define GET_RG_TURISMO_TRX_SXREP_SWB_SEL (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN)) & 0x18000000 ) >> 27)
+#define GET_RG_TURISMO_TRX_SXREP_CSSEL (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN)) & 0x60000000 ) >> 29)
+#define GET_RG_TURISMO_TRX_EN_SX5GB_VCOMON (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN)) & 0x80000000 ) >> 31)
+#define GET_RG_TURISMO_TRX_SX5GB_DIV_PREVDD (((REG32(ADR_TURISMO_TRX_SX_5GB_DIV_SDM)) & 0x0000000f ) >> 0)
+#define GET_RG_TURISMO_TRX_SX5GB_DIV_PSCVDD (((REG32(ADR_TURISMO_TRX_SX_5GB_DIV_SDM)) & 0x000000f0 ) >> 4)
+#define GET_RG_TURISMO_TRX_SX5GB_DIV_RST_H (((REG32(ADR_TURISMO_TRX_SX_5GB_DIV_SDM)) & 0x00000200 ) >> 9)
+#define GET_RG_TURISMO_TRX_SX5GB_DIV_SDM_EDGE (((REG32(ADR_TURISMO_TRX_SX_5GB_DIV_SDM)) & 0x00000400 ) >> 10)
+#define GET_RG_TURISMO_TRX_SX5GB_DIV_DMYBUF_EN (((REG32(ADR_TURISMO_TRX_SX_5GB_DIV_SDM)) & 0x00000800 ) >> 11)
+#define GET_RG_TURISMO_TRX_EN_SX5GB_MOD (((REG32(ADR_TURISMO_TRX_SX_5GB_DIV_SDM)) & 0x00020000 ) >> 17)
+#define GET_RG_TURISMO_TRX_EN_SX5GB_DITHER (((REG32(ADR_TURISMO_TRX_SX_5GB_DIV_SDM)) & 0x00040000 ) >> 18)
+#define GET_RG_TURISMO_TRX_SX5GB_MOD_ORDER (((REG32(ADR_TURISMO_TRX_SX_5GB_DIV_SDM)) & 0x00180000 ) >> 19)
+#define GET_RG_TURISMO_TRX_SX5GB_DITHER_WEIGHT (((REG32(ADR_TURISMO_TRX_SX_5GB_DIV_SDM)) & 0x00600000 ) >> 21)
+#define GET_RG_TURISMO_TRX_SX5GB_SUB_SEL_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_SBCAL)) & 0x00000001 ) >> 0)
+#define GET_RG_TURISMO_TRX_SX5GB_SUB_SEL (((REG32(ADR_TURISMO_TRX_SX_5GB_SBCAL)) & 0x000001fe ) >> 1)
+#define GET_RG_TURISMO_TRX_SX5GB_SUB_C0P5_DIS (((REG32(ADR_TURISMO_TRX_SX_5GB_SBCAL)) & 0x00000200 ) >> 9)
+#define GET_RG_TURISMO_TRX_SX5GB_SBCAL_CT (((REG32(ADR_TURISMO_TRX_SX_5GB_SBCAL)) & 0x00000c00 ) >> 10)
+#define GET_RG_TURISMO_TRX_SX5GB_SBCAL_WT (((REG32(ADR_TURISMO_TRX_SX_5GB_SBCAL)) & 0x00001000 ) >> 12)
+#define GET_RG_TURISMO_TRX_SX5GB_SBCAL_DIFFMIN (((REG32(ADR_TURISMO_TRX_SX_5GB_SBCAL)) & 0x00002000 ) >> 13)
+#define GET_RG_TURISMO_TRX_SX5GB_SBCAL_NTARG_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_SBCAL)) & 0x00008000 ) >> 15)
+#define GET_RG_TURISMO_TRX_SX5GB_SBCAL_NTARG (((REG32(ADR_TURISMO_TRX_SX_5GB_SBCAL)) & 0xffff0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_SX5GB_VOAAC_TAR (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x0000000f ) >> 0)
+#define GET_RG_TURISMO_TRX_VO5GB_AAC_IOST (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x00000030 ) >> 4)
+#define GET_RG_TURISMO_TRX_VO5GB_AAC_IMAX (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x000003c0 ) >> 6)
+#define GET_RG_TURISMO_TRX_SX5GB_AAC_ACCUMH (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x00000c00 ) >> 10)
+#define GET_RG_TURISMO_TRX_SX5GB_AAC_ACCUML (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x00003000 ) >> 12)
+#define GET_RG_TURISMO_TRX_SX5GB_AAC_INIT (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x0000c000 ) >> 14)
+#define GET_RG_TURISMO_TRX_SX5GB_AAC_EVA_TS (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x00030000 ) >> 16)
+#define GET_RG_TURISMO_TRX_SX5GB_AAC_EN_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x00040000 ) >> 18)
+#define GET_RG_TURISMO_TRX_SX5GB_AAC_EN (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x00080000 ) >> 19)
+#define GET_RG_TURISMO_TRX_SX5GB_AAC_EVA_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x00100000 ) >> 20)
+#define GET_RG_TURISMO_TRX_SX5GB_AAC_EVA (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x00200000 ) >> 21)
+#define GET_RG_TURISMO_TRX_AAC5GB_TAR_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x00400000 ) >> 22)
+#define GET_RG_TURISMO_TRX_AAC5GB_PDSW_EN_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x01000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_EN_AAC5GB_VOPDSW (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x02000000 ) >> 25)
+#define GET_RG_TURISMO_TRX_EN_AAC5GB_MXPDSW (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x04000000 ) >> 26)
+#define GET_RG_TURISMO_TRX_EN_AAC5GB_RPPDSW (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x08000000 ) >> 27)
+#define GET_RG_TURISMO_TRX_SX5GB_AAC_TEST_EN (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x40000000 ) >> 30)
+#define GET_RG_TURISMO_TRX_SX5GB_AAC_TEST_SEL (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x80000000 ) >> 31)
+#define GET_RG_TURISMO_TRX_SX5GB_MIXAAC_TAR (((REG32(ADR_TURISMO_TRX_SX_5GB_LOGEN_CALIBRATION)) & 0x0000000f ) >> 0)
+#define GET_RG_TURISMO_TRX_SXMIX_SCA_SEL_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_LOGEN_CALIBRATION)) & 0x00000020 ) >> 5)
+#define GET_RG_TURISMO_TRX_SXMIX_SCA_SEL (((REG32(ADR_TURISMO_TRX_SX_5GB_LOGEN_CALIBRATION)) & 0x00000fc0 ) >> 6)
+#define GET_RG_TURISMO_TRX_SX5GB_REPAAC_TAR (((REG32(ADR_TURISMO_TRX_SX_5GB_LOGEN_CALIBRATION)) & 0x0001e000 ) >> 13)
+#define GET_RG_TURISMO_TRX_SXREP_SCA_SEL_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_LOGEN_CALIBRATION)) & 0x00040000 ) >> 18)
+#define GET_RG_TURISMO_TRX_SXREP_SCA_SEL (((REG32(ADR_TURISMO_TRX_SX_5GB_LOGEN_CALIBRATION)) & 0x01f80000 ) >> 19)
+#define GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG15 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER1)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG15 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER1)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG14 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER1)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG14 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER1)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG13 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER2)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG13 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER2)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG12 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER2)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG12 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER2)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG11 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER3)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG11 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER3)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG10 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER3)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG10 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER3)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG9 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER4)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG9 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER4)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG8 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER4)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG8 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER4)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG7 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER5)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG7 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER5)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG6 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER5)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG6 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER5)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG5 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER6)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG5 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER6)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG4 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER6)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG4 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER6)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG3 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER7)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG3 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER7)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG2 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER7)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG2 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER7)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG1 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER8)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG1 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER8)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG0 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER8)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG0 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER8)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG15 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER9)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG15 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER9)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG14 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER9)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG14 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER9)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG13 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER10)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG13 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER10)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG12 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER10)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG12 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER10)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG11 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER11)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG11 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER11)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG10 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER11)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG10 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER11)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG9 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER12)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG9 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER12)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG8 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER12)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG8 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER12)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG7 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER13)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG7 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER13)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG6 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER13)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG6 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER13)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG5 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER14)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG5 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER14)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG4 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER14)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG4 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER14)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG3 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER15)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG3 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER15)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG2 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER15)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG2 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER15)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG1 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER16)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG1 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER16)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG0 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER16)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG0 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER16)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE4 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER17)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE4 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER17)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE3 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER17)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE3 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER17)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE2 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER18)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE2 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER18)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE1 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER18)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE1 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER18)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE0 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER19)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE0 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER19)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE4 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER19)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE4 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER19)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE3 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER20)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE3 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER20)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE2 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER20)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE2 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER20)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE1 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER21)) & 0x0000003f ) >> 0)
+#define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE1 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER21)) & 0x00003f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE0 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER21)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE0 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER21)) & 0x3f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_SX5GB_DELAY (((REG32(ADR_TURISMO_TRX_5G_MODE_DECODER_TIMER_REGISTER1)) & 0x0000000f ) >> 0)
+#define GET_RG_TURISMO_TRX_5G_TXDAC_DELAY (((REG32(ADR_TURISMO_TRX_5G_MODE_DECODER_TIMER_REGISTER1)) & 0x000000f0 ) >> 4)
+#define GET_RG_TURISMO_TRX_5G_TXRF_DELAY (((REG32(ADR_TURISMO_TRX_5G_MODE_DECODER_TIMER_REGISTER1)) & 0x00000f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_5G_TXPA_DELAY (((REG32(ADR_TURISMO_TRX_5G_MODE_DECODER_TIMER_REGISTER1)) & 0x0000f000 ) >> 12)
+#define GET_RG_TURISMO_TRX_5G_RXRF_DELAY (((REG32(ADR_TURISMO_TRX_5G_MODE_DECODER_TIMER_REGISTER1)) & 0x000f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_5G_TXDAC_T2R_DELAY (((REG32(ADR_TURISMO_TRX_5G_T2R_TIMER_REGISTER)) & 0x0000001f ) >> 0)
+#define GET_RG_TURISMO_TRX_5G_TXRF_T2R_DELAY (((REG32(ADR_TURISMO_TRX_5G_T2R_TIMER_REGISTER)) & 0x00001f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_5G_TXPA_T2R_DELAY (((REG32(ADR_TURISMO_TRX_5G_T2R_TIMER_REGISTER)) & 0x001f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_5G_RXRF_T2R_DELAY (((REG32(ADR_TURISMO_TRX_5G_T2R_TIMER_REGISTER)) & 0x1f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_5G_TXDAC_R2T_DELAY (((REG32(ADR_TURISMO_TRX_5G_R2T_TIMER_REGISTER)) & 0x0000001f ) >> 0)
+#define GET_RG_TURISMO_TRX_5G_TXRF_R2T_DELAY (((REG32(ADR_TURISMO_TRX_5G_R2T_TIMER_REGISTER)) & 0x00001f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_5G_TXPA_R2T_DELAY (((REG32(ADR_TURISMO_TRX_5G_R2T_TIMER_REGISTER)) & 0x001f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_5G_RXRF_R2T_DELAY (((REG32(ADR_TURISMO_TRX_5G_R2T_TIMER_REGISTER)) & 0x1f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_5G_RX_DCCAL_DELAY (((REG32(ADR_TURISMO_TRX_5G_CALIBRATION_TIMER_GAIN_REGISTER)) & 0x00000007 ) >> 0)
+#define GET_RG_TURISMO_TRX_5G_TX_DCCAL_DELAY (((REG32(ADR_TURISMO_TRX_5G_CALIBRATION_TIMER_GAIN_REGISTER)) & 0x00000700 ) >> 8)
+#define GET_RG_TURISMO_TRX_5G_TX_IQCAL_DELAY (((REG32(ADR_TURISMO_TRX_5G_CALIBRATION_TIMER_GAIN_REGISTER)) & 0x00007000 ) >> 12)
+#define GET_RG_TURISMO_TRX_5G_RX_IQCAL_DELAY (((REG32(ADR_TURISMO_TRX_5G_CALIBRATION_TIMER_GAIN_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_TURISMO_TRX_5G_PGAG_TXCAL (((REG32(ADR_TURISMO_TRX_5G_CALIBRATION_TIMER_GAIN_REGISTER)) & 0x00f00000 ) >> 20)
+#define GET_RG_TURISMO_TRX_5G_TX_GAIN_TXCAL (((REG32(ADR_TURISMO_TRX_5G_CALIBRATION_TIMER_GAIN_REGISTER)) & 0x7f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_5G_PGAG_RCCAL (((REG32(ADR_TURISMO_TRX_5G_CALIBRATION_GAIN_REGISTER1)) & 0x0000000f ) >> 0)
+#define GET_RG_TURISMO_TRX_5G_RFG_RXIQCAL (((REG32(ADR_TURISMO_TRX_5G_CALIBRATION_GAIN_REGISTER1)) & 0x00000030 ) >> 4)
+#define GET_RG_TURISMO_TRX_5G_PGAG_RXIQCAL (((REG32(ADR_TURISMO_TRX_5G_CALIBRATION_GAIN_REGISTER1)) & 0x000003c0 ) >> 6)
+#define GET_RG_TURISMO_TRX_5G_TX_GAIN_RXIQCAL (((REG32(ADR_TURISMO_TRX_5G_CALIBRATION_GAIN_REGISTER1)) & 0x0001fc00 ) >> 10)
+#define GET_RG_TURISMO_TRX_5G_RFG_DPDCAL (((REG32(ADR_TURISMO_TRX_5G_CALIBRATION_GAIN_REGISTER1)) & 0x00060000 ) >> 17)
+#define GET_RG_TURISMO_TRX_5G_PGAG_DPDCAL (((REG32(ADR_TURISMO_TRX_5G_CALIBRATION_GAIN_REGISTER1)) & 0x00780000 ) >> 19)
+#define GET_RG_TURISMO_TRX_5G_TX_GAIN_DPDCAL (((REG32(ADR_TURISMO_TRX_5G_CALIBRATION_GAIN_REGISTER1)) & 0x3f800000 ) >> 23)
+#define GET_DB_TURISMO_TRX_DA_SX5GB_SUB_SEL (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_1)) & 0x000000ff ) >> 0)
+#define GET_DB_TURISMO_TRX_DA_SX5GB_VCO_ISEL (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_1)) & 0x00000f00 ) >> 8)
+#define GET_DB_TURISMO_TRX_DA_SXMIX_SCA_SEL (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_1)) & 0x0007e000 ) >> 13)
+#define GET_DB_TURISMO_TRX_DA_SXMIX_GMSEL (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_1)) & 0x00180000 ) >> 19)
+#define GET_DB_TURISMO_TRX_DA_SXREP_SCA_SEL (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_1)) & 0x07e00000 ) >> 21)
+#define GET_DB_TURISMO_TRX_DA_SXREP_CSSEL (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_1)) & 0x18000000 ) >> 27)
+#define GET_DB_TURISMO_TRX_AD_SX5GB_AAC_COMPOUT (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_1)) & 0x20000000 ) >> 29)
+#define GET_DB_TURISMO_TRX_SX5GB_TTL_VT_DET (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_1)) & 0xc0000000 ) >> 30)
+#define GET_DB_TURISMO_TRX_SXMIX_SCA_SEL_A1 (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_2)) & 0x0000003f ) >> 0)
+#define GET_DB_TURISMO_TRX_SXMIX_SCA_SEL_A2 (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_2)) & 0x00001f80 ) >> 7)
+#define GET_DB_TURISMO_TRX_SXREP_SCA_SEL_B1 (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_2)) & 0x000fc000 ) >> 14)
+#define GET_DB_TURISMO_TRX_SXREP_SCA_SEL_B2 (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_2)) & 0x07e00000 ) >> 21)
+#define GET_DB_TURISMO_TRX_SX5GB_SBCAL_NCOUNT (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_3)) & 0x0000ffff ) >> 0)
+#define GET_DB_TURISMO_TRX_SX5GB_SBCAL_NTARGET (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_3)) & 0xffff0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_RX_SCAMA_STEP0 (((REG32(ADR_TURISMO_TRX_5G_RX_LNA_MATCHING_SCA_CONTROL)) & 0x0000000f ) >> 0)
+#define GET_RG_TURISMO_TRX_RX_SCAMA_STEP1 (((REG32(ADR_TURISMO_TRX_5G_RX_LNA_MATCHING_SCA_CONTROL)) & 0x000000f0 ) >> 4)
+#define GET_RG_TURISMO_TRX_RX_SCAMA_STEP2 (((REG32(ADR_TURISMO_TRX_5G_RX_LNA_MATCHING_SCA_CONTROL)) & 0x00000f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_RX_SCAMA_STEP3 (((REG32(ADR_TURISMO_TRX_5G_RX_LNA_MATCHING_SCA_CONTROL)) & 0x0000f000 ) >> 12)
+#define GET_RG_TURISMO_TRX_RX_SCAMA_STEP4 (((REG32(ADR_TURISMO_TRX_5G_RX_LNA_MATCHING_SCA_CONTROL)) & 0x000f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_RX_SCAMA_STEP5 (((REG32(ADR_TURISMO_TRX_5G_RX_LNA_MATCHING_SCA_CONTROL)) & 0x00f00000 ) >> 20)
+#define GET_RG_TURISMO_TRX_RX_SCAMA_STEP6 (((REG32(ADR_TURISMO_TRX_5G_RX_LNA_MATCHING_SCA_CONTROL)) & 0x0f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_RX_SCALOAD_STEP0 (((REG32(ADR_TURISMO_TRX_5G_RX_LNA_LOAD_SCA_CONTROL)) & 0x0000000f ) >> 0)
+#define GET_RG_TURISMO_TRX_RX_SCALOAD_STEP1 (((REG32(ADR_TURISMO_TRX_5G_RX_LNA_LOAD_SCA_CONTROL)) & 0x000000f0 ) >> 4)
+#define GET_RG_TURISMO_TRX_RX_SCALOAD_STEP2 (((REG32(ADR_TURISMO_TRX_5G_RX_LNA_LOAD_SCA_CONTROL)) & 0x00000f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_RX_SCALOAD_STEP3 (((REG32(ADR_TURISMO_TRX_5G_RX_LNA_LOAD_SCA_CONTROL)) & 0x0000f000 ) >> 12)
+#define GET_RG_TURISMO_TRX_RX_SCALOAD_STEP4 (((REG32(ADR_TURISMO_TRX_5G_RX_LNA_LOAD_SCA_CONTROL)) & 0x000f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_RX_SCALOAD_STEP5 (((REG32(ADR_TURISMO_TRX_5G_RX_LNA_LOAD_SCA_CONTROL)) & 0x00f00000 ) >> 20)
+#define GET_RG_TURISMO_TRX_RX_SCALOAD_STEP6 (((REG32(ADR_TURISMO_TRX_5G_RX_LNA_LOAD_SCA_CONTROL)) & 0x0f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_TX_CAPSW_STEP0 (((REG32(ADR_TURISMO_TRX_5G_TX_PGA_CAPSW_CONTROL)) & 0x0000000f ) >> 0)
+#define GET_RG_TURISMO_TRX_TX_CAPSW_STEP1 (((REG32(ADR_TURISMO_TRX_5G_TX_PGA_CAPSW_CONTROL)) & 0x000000f0 ) >> 4)
+#define GET_RG_TURISMO_TRX_TX_CAPSW_STEP2 (((REG32(ADR_TURISMO_TRX_5G_TX_PGA_CAPSW_CONTROL)) & 0x00000f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_TX_CAPSW_STEP3 (((REG32(ADR_TURISMO_TRX_5G_TX_PGA_CAPSW_CONTROL)) & 0x0000f000 ) >> 12)
+#define GET_RG_TURISMO_TRX_TX_CAPSW_STEP4 (((REG32(ADR_TURISMO_TRX_5G_TX_PGA_CAPSW_CONTROL)) & 0x000f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_TX_CAPSW_STEP5 (((REG32(ADR_TURISMO_TRX_5G_TX_PGA_CAPSW_CONTROL)) & 0x00f00000 ) >> 20)
+#define GET_RG_TURISMO_TRX_TX_CAPSW_STEP6 (((REG32(ADR_TURISMO_TRX_5G_TX_PGA_CAPSW_CONTROL)) & 0x0f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_NFRAC_DELTA (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_0)) & 0x00ffffff ) >> 0)
+#define GET_RG_TURISMO_TRX_40M_MODE (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_0)) & 0x01000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_LO_UP_CH (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_0)) & 0x10000000 ) >> 28)
+#define GET_RG_TURISMO_TRX_BT_TRX_IF (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_1)) & 0x07ff0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_RX_IQ_ALPHA (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2)) & 0x0000001f ) >> 0)
+#define GET_RG_TURISMO_TRX_RX_IQ_THETA (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2)) & 0x00001f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_RX_IQ_MANUAL (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2)) & 0x00010000 ) >> 16)
+#define GET_RG_TURISMO_TRX_RXIQ_NOSHRK (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2)) & 0x00020000 ) >> 17)
+#define GET_RG_TURISMO_TRX_RX_RSSIADC_TH (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2)) & 0x00f00000 ) >> 20)
+#define GET_RG_TURISMO_TRX_SUB_DC (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2)) & 0x01000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_IOT_ADC_EDGE_SEL (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2)) & 0x02000000 ) >> 25)
+#define GET_RG_TURISMO_TRX_RSSI_EDGE_SEL (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2)) & 0x04000000 ) >> 26)
+#define GET_RG_TURISMO_TRX_ADC_EDGE_SEL (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2)) & 0x08000000 ) >> 27)
+#define GET_RG_TURISMO_TRX_Q_INV (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2)) & 0x10000000 ) >> 28)
+#define GET_RG_TURISMO_TRX_I_INV (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2)) & 0x20000000 ) >> 29)
+#define GET_RG_TURISMO_TRX_IQ_SWAP (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2)) & 0x40000000 ) >> 30)
+#define GET_RG_TURISMO_TRX_SIGN_SWAP (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2)) & 0x80000000 ) >> 31)
+#define GET_RG_TURISMO_TRX_TX_IQ_ALPHA (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_3)) & 0x0000001f ) >> 0)
+#define GET_RG_TURISMO_TRX_TX_IQ_THETA (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_3)) & 0x00001f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_TX_IQ_MANUAL (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_3)) & 0x00010000 ) >> 16)
+#define GET_RG_TURISMO_TRX_TXIQ_NOSHRK (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_3)) & 0x00020000 ) >> 17)
+#define GET_RG_TURISMO_TRX_TX_IQCAL_TIME (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_3)) & 0x00300000 ) >> 20)
+#define GET_RG_TURISMO_TRX_TX_FREQ_OFFSET (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_4)) & 0x0000ffff ) >> 0)
+#define GET_RG_TURISMO_TRX_TONE_SCALE (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_4)) & 0x01ff0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_BB_SIG_EN (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_4)) & 0x02000000 ) >> 25)
+#define GET_RG_TURISMO_TRX_TONE_GEN_EN (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_4)) & 0x04000000 ) >> 26)
+#define GET_RG_TURISMO_TRX_TX_UP8X_MAN_EN (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_4)) & 0x08000000 ) >> 27)
+#define GET_RG_TURISMO_TRX_DIS_DAC_OFFSET (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_4)) & 0x10000000 ) >> 28)
+#define GET_RG_TURISMO_TRX_CLK_320M_INV (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_4)) & 0x20000000 ) >> 29)
+#define GET_RG_TURISMO_TRX_DPLL_CLK320BY2 (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_4)) & 0x40000000 ) >> 30)
+#define GET_RG_TURISMO_TRX_CBW_20_40 (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_4)) & 0x80000000 ) >> 31)
+#define GET_RG_TURISMO_TRX_DAC_DC_Q (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_5)) & 0x000003ff ) >> 0)
+#define GET_RG_TURISMO_TRX_DAC_DC_I (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_5)) & 0x03ff0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_DAC_Q_SET (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_6)) & 0x000003ff ) >> 0)
+#define GET_RG_TURISMO_TRX_DAC_MAN_Q_EN (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_6)) & 0x00001000 ) >> 12)
+#define GET_RG_TURISMO_TRX_DAC_I_SET (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_6)) & 0x03ff0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_DAC_MAN_I_EN (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_6)) & 0x10000000 ) >> 28)
+#define GET_RG_TURISMO_TRX_BW20_HB_COEF_01 (((REG32(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_00)) & 0x00001fff ) >> 0)
+#define GET_RG_TURISMO_TRX_BW20_HB_COEF_00 (((REG32(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_00)) & 0x1fff0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_BW20_HB_COEF_03 (((REG32(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_01)) & 0x00001fff ) >> 0)
+#define GET_RG_TURISMO_TRX_BW20_HB_COEF_02 (((REG32(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_01)) & 0x1fff0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_BW20_HB_COEF_05 (((REG32(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_02)) & 0x00001fff ) >> 0)
+#define GET_RG_TURISMO_TRX_BW20_HB_COEF_04 (((REG32(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_02)) & 0x1fff0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_BW20_HB_COEF_07 (((REG32(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_03)) & 0x00001fff ) >> 0)
+#define GET_RG_TURISMO_TRX_BW20_HB_COEF_06 (((REG32(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_03)) & 0x1fff0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_BW20_HB_COEF_09 (((REG32(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_04)) & 0x00001fff ) >> 0)
+#define GET_RG_TURISMO_TRX_BW20_HB_COEF_08 (((REG32(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_04)) & 0x1fff0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_BW20_HB_COEF_11 (((REG32(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_05)) & 0x00001fff ) >> 0)
+#define GET_RG_TURISMO_TRX_BW20_HB_COEF_10 (((REG32(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_05)) & 0x1fff0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_PHASE_STEP_VALUE (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_0)) & 0x0000ffff ) >> 0)
+#define GET_RG_TURISMO_TRX_PHASE_MANUAL (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_0)) & 0x00010000 ) >> 16)
+#define GET_RG_TURISMO_TRX_ALPHA_SEL (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_0)) & 0x00300000 ) >> 20)
+#define GET_RG_TURISMO_TRX_SPECTRUM_BW (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_0)) & 0x03000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_SPECTRUM_EN (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_0)) & 0x10000000 ) >> 28)
+#define GET_RO_TURISMO_TRX_WF_DCCAL_DONE (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_1)) & 0x00010000 ) >> 16)
+#define GET_RO_TURISMO_TRX_BT_DCCAL_DONE (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_1)) & 0x00020000 ) >> 17)
+#define GET_RO_TURISMO_TRX_RCCAL_DONE (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_1)) & 0x00040000 ) >> 18)
+#define GET_RO_TURISMO_TRX_TXDC_DONE (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_1)) & 0x00080000 ) >> 19)
+#define GET_RO_TURISMO_TRX_TXIQ_DONE (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_1)) & 0x00100000 ) >> 20)
+#define GET_RO_TURISMO_TRX_RXIQ_DONE (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_1)) & 0x00200000 ) >> 21)
+#define GET_RO_TURISMO_TRX_5G_TXDC_DONE (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_1)) & 0x00400000 ) >> 22)
+#define GET_RO_TURISMO_TRX_5G_TXIQ_DONE (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_1)) & 0x00800000 ) >> 23)
+#define GET_RO_TURISMO_TRX_5G_RXIQ_DONE (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_1)) & 0x01000000 ) >> 24)
+#define GET_RO_TURISMO_TRX_5G_DCCAL_DONE (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_1)) & 0x02000000 ) >> 25)
+#define GET_RO_TURISMO_TRX_PRE_DC_DONE (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_1)) & 0x04000000 ) >> 26)
+#define GET_RG_TURISMO_TRX_PHASE_17P5M (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_2)) & 0x0000ffff ) >> 0)
+#define GET_RG_TURISMO_TRX_PHASE_2P5M (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_2)) & 0xffff0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_PHASE_RXIQ_1M (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_3)) & 0x0000ffff ) >> 0)
+#define GET_RG_TURISMO_TRX_PHASE_1M (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_3)) & 0xffff0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_PHASE_PADPD (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_4)) & 0x0000ffff ) >> 0)
+#define GET_RG_TURISMO_TRX_PHASE_35M (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_4)) & 0xffff0000 ) >> 16)
+#define GET_RO_TURISMO_TRX_RX_IQ_THETA (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_5)) & 0x0000001f ) >> 0)
+#define GET_RO_TURISMO_TRX_RX_IQ_ALPHA (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_5)) & 0x00001f00 ) >> 8)
+#define GET_RO_TURISMO_TRX_TX_IQ_THETA (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_5)) & 0x001f0000 ) >> 16)
+#define GET_RO_TURISMO_TRX_TX_IQ_ALPHA (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_5)) & 0x1f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_RX_RCCAL_TARG (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_6)) & 0x000003ff ) >> 0)
+#define GET_RG_TURISMO_TRX_RX_DC_POLAR_INV (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_6)) & 0x00001000 ) >> 12)
+#define GET_RG_TURISMO_TRX_RCCAL_POLAR_INV (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_6)) & 0x00002000 ) >> 13)
+#define GET_RG_TURISMO_TRX_RX_DC_RESOLUTION (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_6)) & 0x00004000 ) >> 14)
+#define GET_RG_TURISMO_TRX_RX_RCCAL_40M_TARG (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_6)) & 0x03ff0000 ) >> 16)
+#define GET_RO_TURISMO_TRX_SPECTRUM_IQ_PWR_39_32 (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_7)) & 0x000000ff ) >> 0)
+#define GET_RG_TURISMO_TRX_SPECTRUM_LO_FIX (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_7)) & 0x00010000 ) >> 16)
+#define GET_RG_TURISMO_TRX_SPECTRUM_PWR_UPDATE (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_7)) & 0x00100000 ) >> 20)
+#define GET_RO_TURISMO_TRX_SPECTRUM_IQ_PWR_31_0 (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_8)) & 0xffffffff ) >> 0)
+#define GET_RG_TURISMO_TRX_PROC_DELAY (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_9)) & 0x00000007 ) >> 0)
+#define GET_RG_TURISMO_TRX_PRE_DC_POLA_INV (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_9)) & 0x00000010 ) >> 4)
+#define GET_RG_TURISMO_TRX_RX_PRE_DC_RESOLUTION (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_9)) & 0x00000020 ) >> 5)
+#define GET_RG_TURISMO_TRX_PRE_DC_AUTO (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_9)) & 0x00000040 ) >> 6)
+#define GET_RG_TURISMO_TRX_HS3W_TX_RF_GAIN (((REG32(ADR_TURISMO_TRX_HS3W_CTRL1)) & 0x0000007f ) >> 0)
+#define GET_RG_TURISMO_TRX_HS3W_PGAGC (((REG32(ADR_TURISMO_TRX_HS3W_CTRL1)) & 0x00000f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_HS3W_RFGC (((REG32(ADR_TURISMO_TRX_HS3W_CTRL1)) & 0x00003000 ) >> 12)
+#define GET_RG_TURISMO_TRX_HS3W_RXAGC (((REG32(ADR_TURISMO_TRX_HS3W_CTRL1)) & 0x00004000 ) >> 14)
+#define GET_RG_TURISMO_TRX_HS3W_RF_PHY_MODE (((REG32(ADR_TURISMO_TRX_HS3W_CTRL1)) & 0x00070000 ) >> 16)
+#define GET_RG_TURISMO_TRX_HS3W_MANUAL (((REG32(ADR_TURISMO_TRX_HS3W_CTRL1)) & 0x00100000 ) >> 20)
+#define GET_RG_TURISMO_TRX_HS3W_COMM_DATA (((REG32(ADR_TURISMO_TRX_HS3W_CTRL1)) & 0x07000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_HS3W_START_SENT (((REG32(ADR_TURISMO_TRX_HS3W_CTRL1)) & 0x10000000 ) >> 28)
+#define GET_RG_TURISMO_TRX_HS3W_SX_RFCTRL_CH_INT_10_8 (((REG32(ADR_TURISMO_TRX_HS3W_CTRL2)) & 0x00000007 ) >> 0)
+#define GET_RG_TURISMO_TRX_HS3W_SX_RFCH_MAP_EN_INT (((REG32(ADR_TURISMO_TRX_HS3W_CTRL2)) & 0x00000010 ) >> 4)
+#define GET_RG_TURISMO_TRX_HS3W_SX_CHANNEL_INT (((REG32(ADR_TURISMO_TRX_HS3W_CTRL2)) & 0x0007f800 ) >> 11)
+#define GET_RG_TURISMO_TRX_HS3W_SX_RFCTRL_F_INT (((REG32(ADR_TURISMO_TRX_HS3W_CTRL3)) & 0x00ffffff ) >> 0)
+#define GET_RG_TURISMO_TRX_HS3W_SX_RFCTRL_CH_INT_7_0 (((REG32(ADR_TURISMO_TRX_HS3W_CTRL3)) & 0xff000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_MODE_BY_HS_3WIRE (((REG32(ADR_TURISMO_TRX_RF_D_MODE_CTRL)) & 0x00000001 ) >> 0)
+#define GET_RO_TURISMO_TRX_DC_CAL_Q (((REG32(ADR_TURISMO_TRX_RX_DC_CAL_RESULT)) & 0x0000007f ) >> 0)
+#define GET_RO_TURISMO_TRX_DC_CAL_I (((REG32(ADR_TURISMO_TRX_RX_DC_CAL_RESULT)) & 0x007f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_XO_LDO_LEVEL (((REG32(ADR_TURISMO_TRX_PMU_REG_1)) & 0x00000007 ) >> 0)
+#define GET_RG_TURISMO_TRX_EN_LDO_XO_IQUP (((REG32(ADR_TURISMO_TRX_PMU_REG_1)) & 0x00000010 ) >> 4)
+#define GET_RG_TURISMO_TRX_EN_LDO_XO_BYP (((REG32(ADR_TURISMO_TRX_PMU_REG_1)) & 0x00000020 ) >> 5)
+#define GET_RG_TURISMO_TRX_EN_DLDO_BYP (((REG32(ADR_TURISMO_TRX_PMU_REG_1)) & 0x00000040 ) >> 6)
+#define GET_RG_TURISMO_TRX_XO_CBANKI (((REG32(ADR_TURISMO_TRX_PMU_REG_1)) & 0x0001ff00 ) >> 8)
+#define GET_RG_TURISMO_TRX_XO_CBANKO (((REG32(ADR_TURISMO_TRX_PMU_REG_1)) & 0x03fe0000 ) >> 17)
+#define GET_RG_TURISMO_TRX_EN_FDB (((REG32(ADR_TURISMO_TRX_PMU_REG_1)) & 0x04000000 ) >> 26)
+#define GET_RG_TURISMO_TRX_FDB_BYPASS (((REG32(ADR_TURISMO_TRX_PMU_REG_1)) & 0x08000000 ) >> 27)
+#define GET_RG_TURISMO_TRX_FDB_DUTY_LTH (((REG32(ADR_TURISMO_TRX_PMU_REG_1)) & 0x30000000 ) >> 28)
+#define GET_RG_TURISMO_TRX_EN_XOTEST (((REG32(ADR_TURISMO_TRX_PMU_REG_1)) & 0x40000000 ) >> 30)
+#define GET_RG_TURISMO_TRX_EN_FDB_DCC_MUAL (((REG32(ADR_TURISMO_TRX_PMU_REG_2)) & 0x00000001 ) >> 0)
+#define GET_RG_TURISMO_TRX_EN_FDB_DELAYC_MUAL (((REG32(ADR_TURISMO_TRX_PMU_REG_2)) & 0x00000002 ) >> 1)
+#define GET_RG_TURISMO_TRX_EN_FDB_DELAYF_MUAL (((REG32(ADR_TURISMO_TRX_PMU_REG_2)) & 0x00000004 ) >> 2)
+#define GET_RG_TURISMO_TRX_EN_FDB_PHASESWAP_MUAL (((REG32(ADR_TURISMO_TRX_PMU_REG_2)) & 0x00000008 ) >> 3)
+#define GET_RG_TURISMO_TRX_FDB_PHASESWAP_MUAL (((REG32(ADR_TURISMO_TRX_PMU_REG_2)) & 0x00000010 ) >> 4)
+#define GET_RG_TURISMO_TRX_FDB_CDELAY_MUAL (((REG32(ADR_TURISMO_TRX_PMU_REG_2)) & 0x00000f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_FDB_FDELAY_MUAL (((REG32(ADR_TURISMO_TRX_PMU_REG_2)) & 0x0000f000 ) >> 12)
+#define GET_RG_TURISMO_TRX_XO_TIMMER (((REG32(ADR_TURISMO_TRX_PMU_REG_2)) & 0x003f0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_DPL_SETTLING_TIMMER (((REG32(ADR_TURISMO_TRX_PMU_REG_2)) & 0x00c00000 ) >> 22)
+#define GET_RG_TURISMO_TRX_FDB_RDELAYF (((REG32(ADR_TURISMO_TRX_PMU_REG_2)) & 0x03000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_FDB_RDELAYS (((REG32(ADR_TURISMO_TRX_PMU_REG_2)) & 0x0c000000 ) >> 26)
+#define GET_RG_TURISMO_TRX_FDB_RECAL_TIMMER (((REG32(ADR_TURISMO_TRX_PMU_REG_2)) & 0x30000000 ) >> 28)
+#define GET_RG_TURISMO_TRX_EN_FDB_RECAL (((REG32(ADR_TURISMO_TRX_PMU_REG_2)) & 0x40000000 ) >> 30)
+#define GET_RG_TURISMO_TRX_LOAD_RFTABLE_RDY (((REG32(ADR_TURISMO_TRX_PMU_REG_2)) & 0x80000000 ) >> 31)
+#define GET_RG_TURISMO_TRX_DCDC_MODE (((REG32(ADR_TURISMO_TRX_PMU_REG_3)) & 0x00000001 ) >> 0)
+#define GET_RG_TURISMO_TRX_DLDO_LEVEL (((REG32(ADR_TURISMO_TRX_PMU_REG_3)) & 0x0000000e ) >> 1)
+#define GET_RG_TURISMO_TRX_BUCK_LEVEL (((REG32(ADR_TURISMO_TRX_PMU_REG_3)) & 0x000000f0 ) >> 4)
+#define GET_RG_TURISMO_TRX_DLDO_BOOST_IQ (((REG32(ADR_TURISMO_TRX_PMU_REG_3)) & 0x00000100 ) >> 8)
+#define GET_RG_TURISMO_TRX_BUCK_EN_PSM (((REG32(ADR_TURISMO_TRX_PMU_REG_3)) & 0x00000200 ) >> 9)
+#define GET_RG_TURISMO_TRX_BUCK_PSM_VTH (((REG32(ADR_TURISMO_TRX_PMU_REG_3)) & 0x00000400 ) >> 10)
+#define GET_RG_TURISMO_TRX_BUCK_VREF_SEL (((REG32(ADR_TURISMO_TRX_PMU_REG_3)) & 0x00000800 ) >> 11)
+#define GET_RG_TURISMO_TRX_LDO_LEVEL_EFUSE (((REG32(ADR_TURISMO_TRX_PMU_REG_3)) & 0x00007000 ) >> 12)
+#define GET_RG_TURISMO_TRX_EN_LDO_EFUSE (((REG32(ADR_TURISMO_TRX_PMU_REG_3)) & 0x00010000 ) >> 16)
+#define GET_RG_TURISMO_TRX_DCDC_PULLLOW_CON (((REG32(ADR_TURISMO_TRX_PMU_REG_3)) & 0x00040000 ) >> 18)
+#define GET_RG_TURISMO_TRX_DCDC_RES2_CON (((REG32(ADR_TURISMO_TRX_PMU_REG_3)) & 0x00080000 ) >> 19)
+#define GET_RG_TURISMO_TRX_DCDC_RES_CON (((REG32(ADR_TURISMO_TRX_PMU_REG_3)) & 0x00100000 ) >> 20)
+#define GET_RG_TURISMO_TRX_RTC_RS1 (((REG32(ADR_TURISMO_TRX_PMU_REG_3)) & 0x00200000 ) >> 21)
+#define GET_RG_TURISMO_TRX_RTC_RS2 (((REG32(ADR_TURISMO_TRX_PMU_REG_3)) & 0x00400000 ) >> 22)
+#define GET_RG_TURISMO_TRX_DCDC_CLK (((REG32(ADR_TURISMO_TRX_PMU_REG_3)) & 0x0f000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_BUCK_RCZERO (((REG32(ADR_TURISMO_TRX_PMU_REG_3)) & 0x10000000 ) >> 28)
+#define GET_RG_TURISMO_TRX_BUCK_SLOP (((REG32(ADR_TURISMO_TRX_PMU_REG_3)) & 0x60000000 ) >> 29)
+#define GET_RG_TURISMO_TRX_RTC_OFFSET (((REG32(ADR_TURISMO_TRX_PMU_REG_4)) & 0x000000ff ) >> 0)
+#define GET_RG_TURISMO_TRX_RTC_CAL_TARGET_COUNT (((REG32(ADR_TURISMO_TRX_PMU_REG_4)) & 0x000fff00 ) >> 8)
+#define GET_RG_TURISMO_TRX_RTC_OSC_RES_SW_MANUAL (((REG32(ADR_TURISMO_TRX_PMU_REG_4)) & 0x3ff00000 ) >> 20)
+#define GET_RG_TURISMO_TRX_RTC_CAL_MODE (((REG32(ADR_TURISMO_TRX_PMU_REG_4)) & 0x40000000 ) >> 30)
+#define GET_RG_TURISMO_TRX_SEL_DPLL_CLK (((REG32(ADR_TURISMO_TRX_PMU_REG_4)) & 0x80000000 ) >> 31)
+#define GET_RG_TURISMO_TRX_RTC_OSC_RES_SW_MANUAL_EN (((REG32(ADR_TURISMO_TRX_PMU_REG_5)) & 0x00000001 ) >> 0)
+#define GET_RG_TURISMO_TRX_EN_RTC_CAL (((REG32(ADR_TURISMO_TRX_PMU_REG_5)) & 0x00000002 ) >> 1)
+#define GET_RO_TURISMO_TRX_FDB_CDELAY (((REG32(ADR_TURISMO_TRX_PMU_REG_6)) & 0x0000000f ) >> 0)
+#define GET_RO_TURISMO_TRX_FDB_FDELAY (((REG32(ADR_TURISMO_TRX_PMU_REG_6)) & 0x000000f0 ) >> 4)
+#define GET_RO_TURISMO_TRX_FDB_PHASESWAP (((REG32(ADR_TURISMO_TRX_PMU_REG_6)) & 0x00000100 ) >> 8)
+#define GET_RO_TURISMO_TRX_XO_RDY (((REG32(ADR_TURISMO_TRX_PMU_REG_6)) & 0x00000200 ) >> 9)
+#define GET_RO_TURISMO_TRX_RTC_OSC_CAL_RES_RDY (((REG32(ADR_TURISMO_TRX_PMU_REG_6)) & 0x00000400 ) >> 10)
+#define GET_RO_TURISMO_TRX_RTC_OSC_RES_SW (((REG32(ADR_TURISMO_TRX_PMU_REG_6)) & 0x001ff800 ) >> 11)
+#define GET_RG_TURISMO_TRX_PMU_ENTER_SLEEP_MODE (((REG32(ADR_TURISMO_TRX_PMU_SLEEP_REG_1)) & 0x00000001 ) >> 0)
+#define GET_RG_TURISMO_TRX_SLEEP_METHOD (((REG32(ADR_TURISMO_TRX_PMU_SLEEP_REG_1)) & 0x00000002 ) >> 1)
+#define GET_RG_TURISMO_TRX_INT_PMU_MASK (((REG32(ADR_TURISMO_TRX_PMU_SLEEP_REG_1)) & 0x00000004 ) >> 2)
+#define GET_RG_TURISMO_TRX_SLEEP_WAKE_CNT (((REG32(ADR_TURISMO_TRX_PMU_SLEEP_REG_2)) & 0xffffffff ) >> 0)
+#define GET_RG_TURISMO_TRX_SEC_CNT_VALUE (((REG32(ADR_TURISMO_TRX_PMU_RTC_REG_0)) & 0x00007fff ) >> 0)
+#define GET_RG_TURISMO_TRX_RTC_EN (((REG32(ADR_TURISMO_TRX_PMU_RTC_REG_0)) & 0x00008000 ) >> 15)
+#define GET_RO_TURISMO_TRX_RTC_TICK_CNT (((REG32(ADR_TURISMO_TRX_PMU_RTC_REG_0)) & 0x7fff0000 ) >> 16)
+#define GET_RG_TURISMO_TRX_RTC_INT_SEC_MASK (((REG32(ADR_TURISMO_TRX_PMU_RTC_REG_1)) & 0x00000001 ) >> 0)
+#define GET_RG_TURISMO_TRX_RTC_INT_ALARM_MASK (((REG32(ADR_TURISMO_TRX_PMU_RTC_REG_1)) & 0x00000002 ) >> 1)
+#define GET_RO_TURISMO_TRX_PMU_WAKE_TRIG_EVENT (((REG32(ADR_TURISMO_TRX_PMU_RTC_REG_1)) & 0x00007000 ) >> 12)
+#define GET_RO_TURISMO_TRX_RTC_INT_SEC (((REG32(ADR_TURISMO_TRX_PMU_RTC_REG_1)) & 0x00010000 ) >> 16)
+#define GET_RO_TURISMO_TRX_RTC_INT_ALARM (((REG32(ADR_TURISMO_TRX_PMU_RTC_REG_1)) & 0x00020000 ) >> 17)
+#define GET_RG_TURISMO_TRX_RTC_SEC_START_CNT (((REG32(ADR_TURISMO_TRX_PMU_RTC_REG_2)) & 0xffffffff ) >> 0)
+#define GET_RG_TURISMO_TRX_RTC_SEC_ALARM_VALUE (((REG32(ADR_TURISMO_TRX_PMU_RTC_REG_3)) & 0xffffffff ) >> 0)
+#define GET_RG_TURISMO_TRX_FPGA_CLK_REF_40M_EN (((REG32(ADR_TURISMO_TRX_PMU_CTRL_REG)) & 0x00000001 ) >> 0)
+#define GET_RG_TURISMO_TRX_CLK_RTC_SW (((REG32(ADR_TURISMO_TRX_PMU_CTRL_REG)) & 0x00000002 ) >> 1)
+#define GET_RG_TURISMO_TRX_PHY_RST_N (((REG32(ADR_TURISMO_TRX_PMU_CTRL_REG)) & 0x00000010 ) >> 4)
+#define GET_RO_TURISMO_TRX_PMU_STATE (((REG32(ADR_TURISMO_TRX_PMU_STATE_REG)) & 0x00000007 ) >> 0)
+#define GET_RO_TURISMO_TRX_AD_VBAT_OK (((REG32(ADR_TURISMO_TRX_PMU_STATE_REG)) & 0x00000010 ) >> 4)
+#define GET_RG_TURISMO_TRX_BT_CLK_SW (((REG32(ADR_TURISMO_TRX_PMU_BT_CLK)) & 0x00000001 ) >> 0)
+#define GET_RG_TURISMO_TRX_BT_CLK32K_CAL_DONE (((REG32(ADR_TURISMO_TRX_PMU_BT_CLK)) & 0x00000002 ) >> 1)
+#define GET_RG_TURISMO_TRX_GPIO16_DS (((REG32(ADR_TURISMO_TRX_IO_REG_0)) & 0x00000001 ) >> 0)
+#define GET_RG_TURISMO_TRX_GPIO16_PD (((REG32(ADR_TURISMO_TRX_IO_REG_0)) & 0x00000002 ) >> 1)
+#define GET_RG_TURISMO_TRX_GPIO16_OE (((REG32(ADR_TURISMO_TRX_IO_REG_0)) & 0x00000004 ) >> 2)
+#define GET_RG_TURISMO_TRX_GPIO17_DS (((REG32(ADR_TURISMO_TRX_IO_REG_0)) & 0x00000010 ) >> 4)
+#define GET_RG_TURISMO_TRX_GPIO17_PD (((REG32(ADR_TURISMO_TRX_IO_REG_0)) & 0x00000020 ) >> 5)
+#define GET_RG_TURISMO_TRX_GPIO17_OE (((REG32(ADR_TURISMO_TRX_IO_REG_0)) & 0x00000040 ) >> 6)
+#define GET_RG_TURISMO_TRX_GPIO18_DS (((REG32(ADR_TURISMO_TRX_IO_REG_0)) & 0x00000100 ) >> 8)
+#define GET_RG_TURISMO_TRX_GPIO18_PD (((REG32(ADR_TURISMO_TRX_IO_REG_0)) & 0x00000200 ) >> 9)
+#define GET_RG_TURISMO_TRX_GPIO18_OE (((REG32(ADR_TURISMO_TRX_IO_REG_0)) & 0x00000400 ) >> 10)
+#define GET_RG_TURISMO_TRX_GPIO19_DS (((REG32(ADR_TURISMO_TRX_IO_REG_0)) & 0x00001000 ) >> 12)
+#define GET_RG_TURISMO_TRX_GPIO19_PD (((REG32(ADR_TURISMO_TRX_IO_REG_0)) & 0x00002000 ) >> 13)
+#define GET_RG_TURISMO_TRX_GPIO19_OE (((REG32(ADR_TURISMO_TRX_IO_REG_0)) & 0x00004000 ) >> 14)
+#define GET_RG_TURISMO_TRX_GPIO20_DS (((REG32(ADR_TURISMO_TRX_IO_REG_0)) & 0x00010000 ) >> 16)
+#define GET_RG_TURISMO_TRX_GPIO20_PD (((REG32(ADR_TURISMO_TRX_IO_REG_0)) & 0x00020000 ) >> 17)
+#define GET_RG_TURISMO_TRX_GPIO20_OE (((REG32(ADR_TURISMO_TRX_IO_REG_0)) & 0x00040000 ) >> 18)
+#define GET_RG_TURISMO_TRX_SPIS_MISO_DS (((REG32(ADR_TURISMO_TRX_IO_REG_0)) & 0x01000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_FPGA_CLK_REF_40M_DS (((REG32(ADR_TURISMO_TRX_IO_REG_0)) & 0x10000000 ) >> 28)
+#define GET_RG_TURISMO_TRX_FPGA_CLK_REF_40M_PD (((REG32(ADR_TURISMO_TRX_IO_REG_0)) & 0x20000000 ) >> 29)
+#define GET_RG_TURISMO_TRX_FPGA_CLK_REF_40M_OE (((REG32(ADR_TURISMO_TRX_IO_REG_0)) & 0x40000000 ) >> 30)
+#define GET_RG_TURISMO_TRX_GPIO08_DS (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x00000001 ) >> 0)
+#define GET_RG_TURISMO_TRX_GPIO08_PD (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x00000002 ) >> 1)
+#define GET_RG_TURISMO_TRX_GPIO08_OE (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x00000004 ) >> 2)
+#define GET_RG_TURISMO_TRX_GPIO09_DS (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x00000010 ) >> 4)
+#define GET_RG_TURISMO_TRX_GPIO09_PD (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x00000020 ) >> 5)
+#define GET_RG_TURISMO_TRX_GPIO09_OE (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x00000040 ) >> 6)
+#define GET_RG_TURISMO_TRX_GPIO10_DS (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x00000100 ) >> 8)
+#define GET_RG_TURISMO_TRX_GPIO10_PD (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x00000200 ) >> 9)
+#define GET_RG_TURISMO_TRX_GPIO10_OE (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x00000400 ) >> 10)
+#define GET_RG_TURISMO_TRX_GPIO11_DS (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x00001000 ) >> 12)
+#define GET_RG_TURISMO_TRX_GPIO11_PD (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x00002000 ) >> 13)
+#define GET_RG_TURISMO_TRX_GPIO11_OE (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x00004000 ) >> 14)
+#define GET_RG_TURISMO_TRX_GPIO12_DS (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x00010000 ) >> 16)
+#define GET_RG_TURISMO_TRX_GPIO12_PD (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x00020000 ) >> 17)
+#define GET_RG_TURISMO_TRX_GPIO12_OE (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x00040000 ) >> 18)
+#define GET_RG_TURISMO_TRX_GPIO13_DS (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x00100000 ) >> 20)
+#define GET_RG_TURISMO_TRX_GPIO13_PD (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x00200000 ) >> 21)
+#define GET_RG_TURISMO_TRX_GPIO13_OE (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x00400000 ) >> 22)
+#define GET_RG_TURISMO_TRX_GPIO14_DS (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x01000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_GPIO14_PD (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x02000000 ) >> 25)
+#define GET_RG_TURISMO_TRX_GPIO14_OE (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x04000000 ) >> 26)
+#define GET_RG_TURISMO_TRX_GPIO15_DS (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x10000000 ) >> 28)
+#define GET_RG_TURISMO_TRX_GPIO15_PD (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x20000000 ) >> 29)
+#define GET_RG_TURISMO_TRX_GPIO15_OE (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x40000000 ) >> 30)
+#define GET_RG_TURISMO_TRX_GPIO00_DS (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x00000001 ) >> 0)
+#define GET_RG_TURISMO_TRX_GPIO00_PD (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x00000002 ) >> 1)
+#define GET_RG_TURISMO_TRX_GPIO00_OE (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x00000004 ) >> 2)
+#define GET_RG_TURISMO_TRX_GPIO01_DS (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x00000010 ) >> 4)
+#define GET_RG_TURISMO_TRX_GPIO01_PD (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x00000020 ) >> 5)
+#define GET_RG_TURISMO_TRX_GPIO01_OE (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x00000040 ) >> 6)
+#define GET_RG_TURISMO_TRX_GPIO02_DS (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x00000100 ) >> 8)
+#define GET_RG_TURISMO_TRX_GPIO02_PD (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x00000200 ) >> 9)
+#define GET_RG_TURISMO_TRX_GPIO02_OE (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x00000400 ) >> 10)
+#define GET_RG_TURISMO_TRX_GPIO03_DS (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x00001000 ) >> 12)
+#define GET_RG_TURISMO_TRX_GPIO03_PD (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x00002000 ) >> 13)
+#define GET_RG_TURISMO_TRX_GPIO03_OE (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x00004000 ) >> 14)
+#define GET_RG_TURISMO_TRX_GPIO04_DS (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x00010000 ) >> 16)
+#define GET_RG_TURISMO_TRX_GPIO04_PD (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x00020000 ) >> 17)
+#define GET_RG_TURISMO_TRX_GPIO04_OE (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x00040000 ) >> 18)
+#define GET_RG_TURISMO_TRX_GPIO05_DS (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x00100000 ) >> 20)
+#define GET_RG_TURISMO_TRX_GPIO05_PD (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x00200000 ) >> 21)
+#define GET_RG_TURISMO_TRX_GPIO05_OE (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x00400000 ) >> 22)
+#define GET_RG_TURISMO_TRX_GPIO06_DS (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x01000000 ) >> 24)
+#define GET_RG_TURISMO_TRX_GPIO06_PD (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x02000000 ) >> 25)
+#define GET_RG_TURISMO_TRX_GPIO06_OE (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x04000000 ) >> 26)
+#define GET_RG_TURISMO_TRX_GPIO07_DS (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x10000000 ) >> 28)
+#define GET_RG_TURISMO_TRX_GPIO07_PD (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x20000000 ) >> 29)
+#define GET_RG_TURISMO_TRX_GPIO07_OE (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x40000000 ) >> 30)
+#define GET_RG_TURISMO_TRX_RF_PHY_MODE_SEL (((REG32(ADR_TURISMO_TRX_MCU_REG_0)) & 0x00000003 ) >> 0)
+#define GET_RG_TURISMO_TRX_RF_PHY_MODE_WIFI_MAC (((REG32(ADR_TURISMO_TRX_MCU_REG_0)) & 0x00000070 ) >> 4)
+#define GET_RG_TURISMO_TRX_PAD_MUX_SEL (((REG32(ADR_TURISMO_TRX_MCU_REG_0)) & 0x00000f00 ) >> 8)
+#define GET_RG_TURISMO_TRX_MODE_LATCH_LMT (((REG32(ADR_TURISMO_TRX_MCU_REG_0)) & 0x00007000 ) >> 12)
+#define GET_RG_TURISMO_TRX_CLK_MON_SEL (((REG32(ADR_TURISMO_TRX_MCU_REG_0)) & 0x00070000 ) >> 16)
+#define GET_RG_TURISMO_TRX_EXT_MCU_PWRUP (((REG32(ADR_TURISMO_TRX_MCU_REG_0)) & 0x80000000 ) >> 31)
+#define GET_RG_TURISMO_TRX_RAM_00 (((REG32(ADR_TURISMO_TRX_PMU_RAM_00)) & 0xffffffff ) >> 0)
+#define GET_RG_TURISMO_TRX_RAM_01 (((REG32(ADR_TURISMO_TRX_PMU_RAM_01)) & 0xffffffff ) >> 0)
+#define GET_RG_TURISMO_TRX_RAM_02 (((REG32(ADR_TURISMO_TRX_PMU_RAM_02)) & 0xffffffff ) >> 0)
+#define GET_RG_TURISMO_TRX_RAM_03 (((REG32(ADR_TURISMO_TRX_PMU_RAM_03)) & 0xffffffff ) >> 0)
+#define GET_RG_TURISMO_TRX_RAM_04 (((REG32(ADR_TURISMO_TRX_PMU_RAM_04)) & 0xffffffff ) >> 0)
+#define GET_RG_TURISMO_TRX_RAM_05 (((REG32(ADR_TURISMO_TRX_PMU_RAM_05)) & 0xffffffff ) >> 0)
+#define GET_RG_TURISMO_TRX_RAM_06 (((REG32(ADR_TURISMO_TRX_PMU_RAM_06)) & 0xffffffff ) >> 0)
+#define GET_RG_TURISMO_TRX_RAM_07 (((REG32(ADR_TURISMO_TRX_PMU_RAM_07)) & 0xffffffff ) >> 0)
+#define GET_RG_TURISMO_TRX_RAM_08 (((REG32(ADR_TURISMO_TRX_PMU_RAM_08)) & 0xffffffff ) >> 0)
+#define GET_RG_TURISMO_TRX_RAM_09 (((REG32(ADR_TURISMO_TRX_PMU_RAM_09)) & 0xffffffff ) >> 0)
+#define GET_RG_TURISMO_TRX_RAM_10 (((REG32(ADR_TURISMO_TRX_PMU_RAM_10)) & 0xffffffff ) >> 0)
+#define GET_RG_TURISMO_TRX_RAM_11 (((REG32(ADR_TURISMO_TRX_PMU_RAM_11)) & 0xffffffff ) >> 0)
+#define GET_RG_TURISMO_TRX_RAM_12 (((REG32(ADR_TURISMO_TRX_PMU_RAM_12)) & 0xffffffff ) >> 0)
+#define GET_RG_TURISMO_TRX_RAM_13 (((REG32(ADR_TURISMO_TRX_PMU_RAM_13)) & 0xffffffff ) >> 0)
+#define GET_RG_TURISMO_TRX_RAM_14 (((REG32(ADR_TURISMO_TRX_PMU_RAM_14)) & 0xffffffff ) >> 0)
+#define GET_RG_TURISMO_TRX_RAM_15 (((REG32(ADR_TURISMO_TRX_PMU_RAM_15)) & 0xffffffff ) >> 0)
+#define GET_RG_TURISMO_TRX_RAM_16 (((REG32(ADR_TURISMO_TRX_PMU_RAM_16)) & 0xffffffff ) >> 0)
+#define GET_RG_TURISMO_TRX_RAM_17 (((REG32(ADR_TURISMO_TRX_PMU_RAM_17)) & 0xffffffff ) >> 0)
+#define GET_RG_TURISMO_TRX_RAM_18 (((REG32(ADR_TURISMO_TRX_PMU_RAM_18)) & 0xffffffff ) >> 0)
+#define GET_RG_TURISMO_TRX_RAM_19 (((REG32(ADR_TURISMO_TRX_PMU_RAM_19)) & 0xffffffff ) >> 0)
+#define GET_RG_TURISMO_TRX_RAM_20 (((REG32(ADR_TURISMO_TRX_PMU_RAM_20)) & 0xffffffff ) >> 0)
+#define GET_RG_TURISMO_TRX_RAM_21 (((REG32(ADR_TURISMO_TRX_PMU_RAM_21)) & 0xffffffff ) >> 0)
+#define GET_RG_TURISMO_TRX_RAM_22 (((REG32(ADR_TURISMO_TRX_PMU_RAM_22)) & 0xffffffff ) >> 0)
+#define GET_RG_TURISMO_TRX_RAM_23 (((REG32(ADR_TURISMO_TRX_PMU_RAM_23)) & 0xffffffff ) >> 0)
+#define GET_RG_TURISMO_TRX_RAM_24 (((REG32(ADR_TURISMO_TRX_PMU_RAM_24)) & 0xffffffff ) >> 0)
+#define GET_RG_TURISMO_TRX_RAM_25 (((REG32(ADR_TURISMO_TRX_PMU_RAM_25)) & 0xffffffff ) >> 0)
+#define GET_RG_TURISMO_TRX_RAM_26 (((REG32(ADR_TURISMO_TRX_PMU_RAM_26)) & 0xffffffff ) >> 0)
+#define GET_RG_TURISMO_TRX_RAM_27 (((REG32(ADR_TURISMO_TRX_PMU_RAM_27)) & 0xffffffff ) >> 0)
+#define GET_RG_TURISMO_TRX_RAM_28 (((REG32(ADR_TURISMO_TRX_PMU_RAM_28)) & 0xffffffff ) >> 0)
+#define GET_RG_TURISMO_TRX_RAM_29 (((REG32(ADR_TURISMO_TRX_PMU_RAM_29)) & 0xffffffff ) >> 0)
+#define GET_RG_TURISMO_TRX_RAM_30 (((REG32(ADR_TURISMO_TRX_PMU_RAM_30)) & 0xffffffff ) >> 0)
+#define GET_RG_TURISMO_TRX_RAM_31 (((REG32(ADR_TURISMO_TRX_PMU_RAM_31)) & 0xffffffff ) >> 0)
+#define GET_RG_HW_PINSEL (((REG32(ADR_MODE_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_HS_3WIRE_MANUAL (((REG32(ADR_MODE_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_RG_MODE_MANUAL (((REG32(ADR_MODE_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_RG_5G_TX_GAIN_MANUAL (((REG32(ADR_MODE_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_RG_RX_GAIN_MANUAL (((REG32(ADR_MODE_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_RG_TX_GAIN_MANUAL (((REG32(ADR_MODE_REGISTER)) & 0x00000020 ) >> 5)
+#define GET_RG_TXGAIN_PHYCTRL (((REG32(ADR_MODE_REGISTER)) & 0x00000040 ) >> 6)
+#define GET_RG_RX_AGC (((REG32(ADR_MODE_REGISTER)) & 0x00000080 ) >> 7)
+#define GET_RG_MODE (((REG32(ADR_MODE_REGISTER)) & 0x00000700 ) >> 8)
+#define GET_RG_CAL_INDEX (((REG32(ADR_MODE_REGISTER)) & 0x0000f000 ) >> 12)
+#define GET_RG_RFG (((REG32(ADR_MODE_REGISTER)) & 0x00030000 ) >> 16)
+#define GET_RG_PGAG (((REG32(ADR_MODE_REGISTER)) & 0x003c0000 ) >> 18)
+#define GET_RG_BW_HT40 (((REG32(ADR_MODE_REGISTER)) & 0x00400000 ) >> 22)
+#define GET_RG_BW_MANUAL (((REG32(ADR_MODE_REGISTER)) & 0x00800000 ) >> 23)
+#define GET_RG_TX_GAIN (((REG32(ADR_MODE_REGISTER)) & 0x7f000000 ) >> 24)
+#define GET_RG_TX_TRSW_MANUAL (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_EN_TX_TRSW (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_RG_RX_LNA_MANUAL (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_RG_EN_RX_LNA (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_RG_RX_MIXER_MANUAL (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_RG_EN_RX_MIXER (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000020 ) >> 5)
+#define GET_RG_RX_DIV2_MANUAL (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000040 ) >> 6)
+#define GET_RG_EN_RX_DIV2 (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000080 ) >> 7)
+#define GET_RG_RX_LOBUF_MANUAL (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000100 ) >> 8)
+#define GET_RG_EN_RX_LOBUF (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000200 ) >> 9)
+#define GET_RG_RX_TZ_MANUAL (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000400 ) >> 10)
+#define GET_RG_EN_RX_TZ (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_RG_RX_FILTER_MANUAL (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00001000 ) >> 12)
+#define GET_RG_EN_RX_FILTER (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00002000 ) >> 13)
+#define GET_RG_RX_ADC_MANUAL (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_RG_EN_RX_ADC (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00008000 ) >> 15)
+#define GET_RG_RX_RSSI_MANUAL (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00010000 ) >> 16)
+#define GET_RG_EN_RX_RSSI (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00020000 ) >> 17)
+#define GET_RG_TX_PA_MANUAL (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00040000 ) >> 18)
+#define GET_RG_EN_TX_PA (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00080000 ) >> 19)
+#define GET_RG_TX_MOD_MANUAL (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00100000 ) >> 20)
+#define GET_RG_EN_TX_MOD (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00200000 ) >> 21)
+#define GET_RG_TX_DAC_MANUAL (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00400000 ) >> 22)
+#define GET_RG_EN_TX_DAC (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00800000 ) >> 23)
+#define GET_RG_TX_DIV2_MANUAL (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x01000000 ) >> 24)
+#define GET_RG_EN_TX_DIV2 (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x02000000 ) >> 25)
+#define GET_RG_TX_DIV2_BUF_MANUAL (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x04000000 ) >> 26)
+#define GET_RG_EN_TX_DIV2_BUF (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x08000000 ) >> 27)
+#define GET_RG_TX_BT_PA_MANUAL (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x10000000 ) >> 28)
+#define GET_RG_EN_TX_BT_PA (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x20000000 ) >> 29)
+#define GET_RG_EN_IOT_ADC_BUF (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x40000000 ) >> 30)
+#define GET_RG_EN_IOT_ADC (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x80000000 ) >> 31)
+#define GET_RG_EN_LDO_RX_FE (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_EN_LDO_AFE (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_RG_EN_IREF_RX (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_RG_TX_DAC_CAL_MANUAL (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_RG_EN_TX_DAC_CAL (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_RG_RX_TZ_OUT_TRISTATE_MANUAL (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000020 ) >> 5)
+#define GET_RG_RX_TZ_OUT_TRISTATE (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000040 ) >> 6)
+#define GET_RG_TX_SELF_MIXER_MANUAL (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000080 ) >> 7)
+#define GET_RG_EN_TX_SELF_MIXER (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000100 ) >> 8)
+#define GET_RG_RX_IQCAL_MANUAL (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000200 ) >> 9)
+#define GET_RG_EN_RX_IQCAL (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000400 ) >> 10)
+#define GET_RG_TX_DPD_MANUAL (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_RG_EN_TX_DPD (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00001000 ) >> 12)
+#define GET_RG_EN_TX_TSSI (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_RG_EN_SARADC (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00008000 ) >> 15)
+#define GET_RG_EN_TX_VTOI_2ND (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00010000 ) >> 16)
+#define GET_RG_TXLPF_BYPASS (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00020000 ) >> 17)
+#define GET_RG_TX_EN_VOLTAGE_IN (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00040000 ) >> 18)
+#define GET_RG_EN_TX_DAC_OUT (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00080000 ) >> 19)
+#define GET_RG_EN_TX_DAC_VOUT (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00100000 ) >> 20)
+#define GET_RG_RX_ABBOUT_TRI_STATE (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00200000 ) >> 21)
+#define GET_RG_EN_RX_TESTNODE (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00400000 ) >> 22)
+#define GET_RG_EN_RX_PADSW (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00800000 ) >> 23)
+#define GET_RG_EN_LDO_RX_FE_FC (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x02000000 ) >> 25)
+#define GET_RG_EN_LDO_RX_AFE_FC (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x04000000 ) >> 26)
+#define GET_RG_EN_LDO_RX_FE_IQUP (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x08000000 ) >> 27)
+#define GET_RG_EN_LDO_RX_AFE_IQUP (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x10000000 ) >> 28)
+#define GET_RG_RX_SQDC (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0xe0000000 ) >> 29)
+#define GET_RG_LDO_LEVEL_RX_FE (((REG32(ADR_2_4G_LDO_REGISTER)) & 0x00000007 ) >> 0)
+#define GET_RG_EN_LDO_RX_FE_BYP (((REG32(ADR_2_4G_LDO_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_RG_LDO_LEVEL_AFE (((REG32(ADR_2_4G_LDO_REGISTER)) & 0x00000070 ) >> 4)
+#define GET_RG_EN_LDO_RX_AFE_BYP (((REG32(ADR_2_4G_LDO_REGISTER)) & 0x00000080 ) >> 7)
+#define GET_RG_SX_LDO_CP_LEVEL (((REG32(ADR_2_4G_LDO_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_EN_LDO_CP_BYP (((REG32(ADR_2_4G_LDO_REGISTER)) & 0x00080000 ) >> 19)
+#define GET_RG_SX_LDO_LO_LEVEL (((REG32(ADR_2_4G_LDO_REGISTER)) & 0x00700000 ) >> 20)
+#define GET_RG_EN_LDO_LO_BYP (((REG32(ADR_2_4G_LDO_REGISTER)) & 0x00800000 ) >> 23)
+#define GET_RG_SX_LDO_VCO_LEVEL (((REG32(ADR_2_4G_LDO_REGISTER)) & 0x07000000 ) >> 24)
+#define GET_RG_SX_LDO_DIV_LEVEL (((REG32(ADR_2_4G_LDO_REGISTER)) & 0x70000000 ) >> 28)
+#define GET_RG_EN_LDO_DIV_BYP (((REG32(ADR_2_4G_LDO_REGISTER)) & 0x80000000 ) >> 31)
+#define GET_RG_WF_RX_ABBCTUNE (((REG32(ADR_WIFI_HT20_RX_FILTER_REGISTER)) & 0x0000003f ) >> 0)
+#define GET_RG_WF_RX_TZ_CMZ_C (((REG32(ADR_WIFI_HT20_RX_FILTER_REGISTER)) & 0x000000c0 ) >> 6)
+#define GET_RG_WF_RX_FILTERI_COARSE (((REG32(ADR_WIFI_HT20_RX_FILTER_REGISTER)) & 0x00000300 ) >> 8)
+#define GET_RG_WF_RX_FILTERI1ST (((REG32(ADR_WIFI_HT20_RX_FILTER_REGISTER)) & 0x00000c00 ) >> 10)
+#define GET_RG_WF_RX_FILTERI2ND (((REG32(ADR_WIFI_HT20_RX_FILTER_REGISTER)) & 0x00003000 ) >> 12)
+#define GET_RG_WF_RX_FILTERI3RD (((REG32(ADR_WIFI_HT20_RX_FILTER_REGISTER)) & 0x0000c000 ) >> 14)
+#define GET_RG_WF_RX_ABBCFIX (((REG32(ADR_WIFI_HT20_RX_FILTER_REGISTER)) & 0x00010000 ) >> 16)
+#define GET_RG_WF_RX_ABB_N_MODE (((REG32(ADR_WIFI_HT20_RX_FILTER_REGISTER)) & 0x00020000 ) >> 17)
+#define GET_RG_WF_RX_ABB_BT_MODE (((REG32(ADR_WIFI_HT20_RX_FILTER_REGISTER)) & 0x00040000 ) >> 18)
+#define GET_RG_WF_RX_ABB_IDIV3 (((REG32(ADR_WIFI_HT20_RX_FILTER_REGISTER)) & 0x00080000 ) >> 19)
+#define GET_RG_WF_RX_EN_IDACA_COARSE (((REG32(ADR_WIFI_HT20_RX_FILTER_REGISTER)) & 0x00100000 ) >> 20)
+#define GET_RG_WF_RX_EN_LOOPA (((REG32(ADR_WIFI_HT20_RX_FILTER_REGISTER)) & 0x00200000 ) >> 21)
+#define GET_RG_WF_RX_TZ_CMZ_R (((REG32(ADR_WIFI_HT20_RX_FILTER_REGISTER)) & 0x00c00000 ) >> 22)
+#define GET_RG_WF_RX_FILTERVCM (((REG32(ADR_WIFI_HT20_RX_FILTER_REGISTER)) & 0x07000000 ) >> 24)
+#define GET_RG_WF_RX_OUTVCM (((REG32(ADR_WIFI_HT20_RX_FILTER_REGISTER)) & 0x70000000 ) >> 28)
+#define GET_RG_WF_N_RX_ABBCTUNE (((REG32(ADR_WIFI_HT40_RX_FILTER_REGISTER)) & 0x0000003f ) >> 0)
+#define GET_RG_WF_N_RX_TZ_CMZ_C (((REG32(ADR_WIFI_HT40_RX_FILTER_REGISTER)) & 0x000000c0 ) >> 6)
+#define GET_RG_WF_N_RX_FILTERI_COARSE (((REG32(ADR_WIFI_HT40_RX_FILTER_REGISTER)) & 0x00000300 ) >> 8)
+#define GET_RG_WF_N_RX_FILTERI1ST (((REG32(ADR_WIFI_HT40_RX_FILTER_REGISTER)) & 0x00000c00 ) >> 10)
+#define GET_RG_WF_N_RX_FILTERI2ND (((REG32(ADR_WIFI_HT40_RX_FILTER_REGISTER)) & 0x00003000 ) >> 12)
+#define GET_RG_WF_N_RX_FILTERI3RD (((REG32(ADR_WIFI_HT40_RX_FILTER_REGISTER)) & 0x0000c000 ) >> 14)
+#define GET_RG_WF_N_RX_ABBCFIX (((REG32(ADR_WIFI_HT40_RX_FILTER_REGISTER)) & 0x00010000 ) >> 16)
+#define GET_RG_WF_N_RX_ABB_N_MODE (((REG32(ADR_WIFI_HT40_RX_FILTER_REGISTER)) & 0x00020000 ) >> 17)
+#define GET_RG_WF_N_RX_ABB_BT_MODE (((REG32(ADR_WIFI_HT40_RX_FILTER_REGISTER)) & 0x00040000 ) >> 18)
+#define GET_RG_WF_N_RX_ABB_IDIV3 (((REG32(ADR_WIFI_HT40_RX_FILTER_REGISTER)) & 0x00080000 ) >> 19)
+#define GET_RG_WF_N_RX_EN_IDACA_COARSE (((REG32(ADR_WIFI_HT40_RX_FILTER_REGISTER)) & 0x00100000 ) >> 20)
+#define GET_RG_WF_N_RX_EN_LOOPA (((REG32(ADR_WIFI_HT40_RX_FILTER_REGISTER)) & 0x00200000 ) >> 21)
+#define GET_RG_WF_N_RX_TZ_CMZ_R (((REG32(ADR_WIFI_HT40_RX_FILTER_REGISTER)) & 0x00c00000 ) >> 22)
+#define GET_RG_WF_N_RX_FILTERVCM (((REG32(ADR_WIFI_HT40_RX_FILTER_REGISTER)) & 0x07000000 ) >> 24)
+#define GET_RG_WF_N_RX_OUTVCM (((REG32(ADR_WIFI_HT40_RX_FILTER_REGISTER)) & 0x70000000 ) >> 28)
+#define GET_RG_BT_RX_ABBCTUNE (((REG32(ADR_BT_RX_FILTER_REGISTER)) & 0x0000003f ) >> 0)
+#define GET_RG_BT_RX_TZ_CMZ_C (((REG32(ADR_BT_RX_FILTER_REGISTER)) & 0x000000c0 ) >> 6)
+#define GET_RG_BT_RX_FILTERI_COARSE (((REG32(ADR_BT_RX_FILTER_REGISTER)) & 0x00000300 ) >> 8)
+#define GET_RG_BT_RX_FILTERI1ST (((REG32(ADR_BT_RX_FILTER_REGISTER)) & 0x00000c00 ) >> 10)
+#define GET_RG_BT_RX_FILTERI2ND (((REG32(ADR_BT_RX_FILTER_REGISTER)) & 0x00003000 ) >> 12)
+#define GET_RG_BT_RX_FILTERI3RD (((REG32(ADR_BT_RX_FILTER_REGISTER)) & 0x0000c000 ) >> 14)
+#define GET_RG_BT_RX_ABBCFIX (((REG32(ADR_BT_RX_FILTER_REGISTER)) & 0x00010000 ) >> 16)
+#define GET_RG_BT_RX_ABB_N_MODE (((REG32(ADR_BT_RX_FILTER_REGISTER)) & 0x00020000 ) >> 17)
+#define GET_RG_BT_RX_ABB_BT_MODE (((REG32(ADR_BT_RX_FILTER_REGISTER)) & 0x00040000 ) >> 18)
+#define GET_RG_BT_RX_ABB_IDIV3 (((REG32(ADR_BT_RX_FILTER_REGISTER)) & 0x00080000 ) >> 19)
+#define GET_RG_BT_RX_EN_IDACA_COARSE (((REG32(ADR_BT_RX_FILTER_REGISTER)) & 0x00100000 ) >> 20)
+#define GET_RG_BT_RX_EN_LOOPA (((REG32(ADR_BT_RX_FILTER_REGISTER)) & 0x00200000 ) >> 21)
+#define GET_RG_BT_RX_TZ_CMZ_R (((REG32(ADR_BT_RX_FILTER_REGISTER)) & 0x00c00000 ) >> 22)
+#define GET_RG_BT_RX_FILTERVCM (((REG32(ADR_BT_RX_FILTER_REGISTER)) & 0x07000000 ) >> 24)
+#define GET_RG_BT_RX_OUTVCM (((REG32(ADR_BT_RX_FILTER_REGISTER)) & 0x70000000 ) >> 28)
+#define GET_RG_RX_ADCRSSI_VCM (((REG32(ADR_2_4G_RX_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_RX_REC_LPFCORNER (((REG32(ADR_2_4G_RX_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_RX_ADCRSSI_CLKSEL (((REG32(ADR_2_4G_RX_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_RG_RSSI_CLOCK_GATING (((REG32(ADR_2_4G_RX_REGISTER)) & 0x00000020 ) >> 5)
+#define GET_RG_RX_IDACA_COARSE_PMOS_ON (((REG32(ADR_2_4G_RX_REGISTER)) & 0x00000040 ) >> 6)
+#define GET_RG_TX_DPDGM_BIAS (((REG32(ADR_2_4G_RX_REGISTER)) & 0x00000f00 ) >> 8)
+#define GET_RG_TX_DPD_DIV (((REG32(ADR_2_4G_RX_REGISTER)) & 0x0000f000 ) >> 12)
+#define GET_RG_TX_TSSI_BIAS (((REG32(ADR_2_4G_RX_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_TX_TSSI_DIV (((REG32(ADR_2_4G_RX_REGISTER)) & 0x00380000 ) >> 19)
+#define GET_RG_TX_TSSI_TEST (((REG32(ADR_2_4G_RX_REGISTER)) & 0x00c00000 ) >> 22)
+#define GET_RG_TX_TSSI_TESTMODE (((REG32(ADR_2_4G_RX_REGISTER)) & 0x01000000 ) >> 24)
+#define GET_RG_EN_RX_RSSI_TESTNODE (((REG32(ADR_2_4G_RX_REGISTER)) & 0x0e000000 ) >> 25)
+#define GET_RG_RX_LNA_TRI_SEL (((REG32(ADR_2_4G_RX_REGISTER)) & 0x30000000 ) >> 28)
+#define GET_RG_RX_LNA_SETTLE (((REG32(ADR_2_4G_RX_REGISTER)) & 0xc0000000 ) >> 30)
+#define GET_RG_WF_TXPGA_CAPSW (((REG32(ADR_2_4G_TX_FE_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_WF_TX_DIV_VSET (((REG32(ADR_2_4G_TX_FE_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_WF_TX_LOBUF_VSET (((REG32(ADR_2_4G_TX_FE_REGISTER)) & 0x00000030 ) >> 4)
+#define GET_RG_WF_TXMOD_GMCELL_FINE (((REG32(ADR_2_4G_TX_FE_REGISTER)) & 0x00000700 ) >> 8)
+#define GET_RG_BT_TXPGA_CAPSW (((REG32(ADR_2_4G_TX_FE_REGISTER)) & 0x00003000 ) >> 12)
+#define GET_RG_BT_TX_DIV_VSET (((REG32(ADR_2_4G_TX_FE_REGISTER)) & 0x0000c000 ) >> 14)
+#define GET_RG_BT_TX_LOBUF_VSET (((REG32(ADR_2_4G_TX_FE_REGISTER)) & 0x00030000 ) >> 16)
+#define GET_RG_BT_TXMOD_GMCELL_FINE (((REG32(ADR_2_4G_TX_FE_REGISTER)) & 0x00700000 ) >> 20)
+#define GET_RG_WF_PACELL_EN (((REG32(ADR_2_4G_TX_PA_REGISTER)) & 0x00000007 ) >> 0)
+#define GET_RG_WF_PABIAS_CTRL (((REG32(ADR_2_4G_TX_PA_REGISTER)) & 0x000000f0 ) >> 4)
+#define GET_RG_WF_TX_PA1_VCAS (((REG32(ADR_2_4G_TX_PA_REGISTER)) & 0x00000700 ) >> 8)
+#define GET_RG_WF_TX_PA2_VCAS (((REG32(ADR_2_4G_TX_PA_REGISTER)) & 0x00007000 ) >> 12)
+#define GET_RG_WF_TX_PA3_VCAS (((REG32(ADR_2_4G_TX_PA_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_WF_BTPASW (((REG32(ADR_2_4G_TX_PA_REGISTER)) & 0x00100000 ) >> 20)
+#define GET_RG_BTRX_BTPASW (((REG32(ADR_2_4G_TX_PA_REGISTER)) & 0x00200000 ) >> 21)
+#define GET_RG_BTTX_BTPASW (((REG32(ADR_2_4G_TX_PA_REGISTER)) & 0x00400000 ) >> 22)
+#define GET_RG_BT_PABIAS_2X (((REG32(ADR_2_4G_TX_PA_REGISTER)) & 0x00800000 ) >> 23)
+#define GET_RG_BT_PABIAS_CTRL (((REG32(ADR_2_4G_TX_PA_REGISTER)) & 0x0f000000 ) >> 24)
+#define GET_RG_BT_TX_PA_VCAS (((REG32(ADR_2_4G_TX_PA_REGISTER)) & 0x70000000 ) >> 28)
+#define GET_RG_TXPGA_MAIN (((REG32(ADR_2_4G_TX_REGISTER)) & 0x0000003f ) >> 0)
+#define GET_RG_TXPGA_STEER (((REG32(ADR_2_4G_TX_REGISTER)) & 0x00000fc0 ) >> 6)
+#define GET_RG_TXMOD_GMCELL (((REG32(ADR_2_4G_TX_REGISTER)) & 0x00003000 ) >> 12)
+#define GET_RG_TXLPF_GMCELL (((REG32(ADR_2_4G_TX_REGISTER)) & 0x0000c000 ) >> 14)
+#define GET_RG_WF_TX_GAIN_OFFSET (((REG32(ADR_2_4G_TX_REGISTER)) & 0x000f0000 ) >> 16)
+#define GET_RG_BT_TX_GAIN_OFFSET (((REG32(ADR_2_4G_TX_REGISTER)) & 0x00f00000 ) >> 20)
+#define GET_RG_TX_VTOI_CURRENT (((REG32(ADR_2_4G_TX_REGISTER)) & 0x03000000 ) >> 24)
+#define GET_RG_TX_VTOI_GM (((REG32(ADR_2_4G_TX_REGISTER)) & 0x0c000000 ) >> 26)
+#define GET_RG_TX_VTOI_OPTION (((REG32(ADR_2_4G_TX_REGISTER)) & 0x30000000 ) >> 28)
+#define GET_RG_TX_VTOI_FS (((REG32(ADR_2_4G_TX_REGISTER)) & 0x40000000 ) >> 30)
+#define GET_RG_WF_RX_HG_LNA_GC (((REG32(ADR_2_4G_RX_FE_HG_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_WF_RX_HG_TZ_GC (((REG32(ADR_2_4G_RX_FE_HG_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_WF_RX_HG_LNAHGN_BIAS (((REG32(ADR_2_4G_RX_FE_HG_REGISTER)) & 0x000000f0 ) >> 4)
+#define GET_RG_WF_RX_HG_LNAHGP_BIAS (((REG32(ADR_2_4G_RX_FE_HG_REGISTER)) & 0x00000f00 ) >> 8)
+#define GET_RG_WF_RX_HG_LNALG_BIAS (((REG32(ADR_2_4G_RX_FE_HG_REGISTER)) & 0x0000f000 ) >> 12)
+#define GET_RG_WF_RX_HG_TZ_CAP (((REG32(ADR_2_4G_RX_FE_HG_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_WF_RX_HG_TZ_GC_BOOST (((REG32(ADR_2_4G_RX_FE_HG_REGISTER)) & 0x00300000 ) >> 20)
+#define GET_RG_WF_RX_HG_DIV2_CORE (((REG32(ADR_2_4G_RX_FE_HG_REGISTER)) & 0x00c00000 ) >> 22)
+#define GET_RG_WF_RX_HG_LOBUF (((REG32(ADR_2_4G_RX_FE_HG_REGISTER)) & 0x03000000 ) >> 24)
+#define GET_RG_WF_RX_HG_TZI (((REG32(ADR_2_4G_RX_FE_HG_REGISTER)) & 0x1c000000 ) >> 26)
+#define GET_RG_WF_RX_HG_TZ_VCM (((REG32(ADR_2_4G_RX_FE_HG_REGISTER)) & 0xe0000000 ) >> 29)
+#define GET_RG_WF_RX_MG_LNA_GC (((REG32(ADR_2_4G_RX_FE_MG_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_WF_RX_MG_TZ_GC (((REG32(ADR_2_4G_RX_FE_MG_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_WF_RX_MG_LNAHGN_BIAS (((REG32(ADR_2_4G_RX_FE_MG_REGISTER)) & 0x000000f0 ) >> 4)
+#define GET_RG_WF_RX_MG_LNAHGP_BIAS (((REG32(ADR_2_4G_RX_FE_MG_REGISTER)) & 0x00000f00 ) >> 8)
+#define GET_RG_WF_RX_MG_LNALG_BIAS (((REG32(ADR_2_4G_RX_FE_MG_REGISTER)) & 0x0000f000 ) >> 12)
+#define GET_RG_WF_RX_MG_TZ_CAP (((REG32(ADR_2_4G_RX_FE_MG_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_WF_RX_MG_TZ_GC_BOOST (((REG32(ADR_2_4G_RX_FE_MG_REGISTER)) & 0x00300000 ) >> 20)
+#define GET_RG_WF_RX_MG_DIV2_CORE (((REG32(ADR_2_4G_RX_FE_MG_REGISTER)) & 0x00c00000 ) >> 22)
+#define GET_RG_WF_RX_MG_LOBUF (((REG32(ADR_2_4G_RX_FE_MG_REGISTER)) & 0x03000000 ) >> 24)
+#define GET_RG_WF_RX_MG_TZI (((REG32(ADR_2_4G_RX_FE_MG_REGISTER)) & 0x1c000000 ) >> 26)
+#define GET_RG_WF_RX_MG_TZ_VCM (((REG32(ADR_2_4G_RX_FE_MG_REGISTER)) & 0xe0000000 ) >> 29)
+#define GET_RG_WF_RX_LG_LNA_GC (((REG32(ADR_2_4G_RX_FE_LG_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_WF_RX_LG_TZ_GC (((REG32(ADR_2_4G_RX_FE_LG_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_WF_RX_LG_LNAHGN_BIAS (((REG32(ADR_2_4G_RX_FE_LG_REGISTER)) & 0x000000f0 ) >> 4)
+#define GET_RG_WF_RX_LG_LNAHGP_BIAS (((REG32(ADR_2_4G_RX_FE_LG_REGISTER)) & 0x00000f00 ) >> 8)
+#define GET_RG_WF_RX_LG_LNALG_BIAS (((REG32(ADR_2_4G_RX_FE_LG_REGISTER)) & 0x0000f000 ) >> 12)
+#define GET_RG_WF_RX_LG_TZ_CAP (((REG32(ADR_2_4G_RX_FE_LG_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_WF_RX_LG_TZ_GC_BOOST (((REG32(ADR_2_4G_RX_FE_LG_REGISTER)) & 0x00300000 ) >> 20)
+#define GET_RG_WF_RX_LG_DIV2_CORE (((REG32(ADR_2_4G_RX_FE_LG_REGISTER)) & 0x00c00000 ) >> 22)
+#define GET_RG_WF_RX_LG_LOBUF (((REG32(ADR_2_4G_RX_FE_LG_REGISTER)) & 0x03000000 ) >> 24)
+#define GET_RG_WF_RX_LG_TZI (((REG32(ADR_2_4G_RX_FE_LG_REGISTER)) & 0x1c000000 ) >> 26)
+#define GET_RG_WF_RX_LG_TZ_VCM (((REG32(ADR_2_4G_RX_FE_LG_REGISTER)) & 0xe0000000 ) >> 29)
+#define GET_RG_WF_RX_ULG_LNA_GC (((REG32(ADR_2_4G_RX_FE_ULG_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_WF_RX_ULG_TZ_GC (((REG32(ADR_2_4G_RX_FE_ULG_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_WF_RX_ULG_LNAHGN_BIAS (((REG32(ADR_2_4G_RX_FE_ULG_REGISTER)) & 0x000000f0 ) >> 4)
+#define GET_RG_WF_RX_ULG_LNAHGP_BIAS (((REG32(ADR_2_4G_RX_FE_ULG_REGISTER)) & 0x00000f00 ) >> 8)
+#define GET_RG_WF_RX_ULG_LNALG_BIAS (((REG32(ADR_2_4G_RX_FE_ULG_REGISTER)) & 0x0000f000 ) >> 12)
+#define GET_RG_WF_RX_ULG_TZ_CAP (((REG32(ADR_2_4G_RX_FE_ULG_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_WF_RX_ULG_TZ_GC_BOOST (((REG32(ADR_2_4G_RX_FE_ULG_REGISTER)) & 0x00300000 ) >> 20)
+#define GET_RG_WF_RX_ULG_DIV2_CORE (((REG32(ADR_2_4G_RX_FE_ULG_REGISTER)) & 0x00c00000 ) >> 22)
+#define GET_RG_WF_RX_ULG_LOBUF (((REG32(ADR_2_4G_RX_FE_ULG_REGISTER)) & 0x03000000 ) >> 24)
+#define GET_RG_WF_RX_ULG_TZI (((REG32(ADR_2_4G_RX_FE_ULG_REGISTER)) & 0x1c000000 ) >> 26)
+#define GET_RG_WF_RX_ULG_TZ_VCM (((REG32(ADR_2_4G_RX_FE_ULG_REGISTER)) & 0xe0000000 ) >> 29)
+#define GET_RG_BT_RX_HG_LNA_GC (((REG32(ADR_BT_RX_FE_HG_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_BT_RX_HG_TZ_GC (((REG32(ADR_BT_RX_FE_HG_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_BT_RX_HG_LNAHGN_BIAS (((REG32(ADR_BT_RX_FE_HG_REGISTER)) & 0x000000f0 ) >> 4)
+#define GET_RG_BT_RX_HG_LNAHGP_BIAS (((REG32(ADR_BT_RX_FE_HG_REGISTER)) & 0x00000f00 ) >> 8)
+#define GET_RG_BT_RX_HG_LNALG_BIAS (((REG32(ADR_BT_RX_FE_HG_REGISTER)) & 0x0000f000 ) >> 12)
+#define GET_RG_BT_RX_HG_TZ_CAP (((REG32(ADR_BT_RX_FE_HG_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_BT_RX_HG_TZ_GC_BOOST (((REG32(ADR_BT_RX_FE_HG_REGISTER)) & 0x00300000 ) >> 20)
+#define GET_RG_BT_RX_HG_DIV2_CORE (((REG32(ADR_BT_RX_FE_HG_REGISTER)) & 0x00c00000 ) >> 22)
+#define GET_RG_BT_RX_HG_LOBUF (((REG32(ADR_BT_RX_FE_HG_REGISTER)) & 0x03000000 ) >> 24)
+#define GET_RG_BT_RX_HG_TZI (((REG32(ADR_BT_RX_FE_HG_REGISTER)) & 0x1c000000 ) >> 26)
+#define GET_RG_BT_RX_HG_TZ_VCM (((REG32(ADR_BT_RX_FE_HG_REGISTER)) & 0xe0000000 ) >> 29)
+#define GET_RG_BT_RX_MG_LNA_GC (((REG32(ADR_BT_RX_FE_MG_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_BT_RX_MG_TZ_GC (((REG32(ADR_BT_RX_FE_MG_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_BT_RX_MG_LNAHGN_BIAS (((REG32(ADR_BT_RX_FE_MG_REGISTER)) & 0x000000f0 ) >> 4)
+#define GET_RG_BT_RX_MG_LNAHGP_BIAS (((REG32(ADR_BT_RX_FE_MG_REGISTER)) & 0x00000f00 ) >> 8)
+#define GET_RG_BT_RX_MG_LNALG_BIAS (((REG32(ADR_BT_RX_FE_MG_REGISTER)) & 0x0000f000 ) >> 12)
+#define GET_RG_BT_RX_MG_TZ_CAP (((REG32(ADR_BT_RX_FE_MG_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_BT_RX_MG_TZ_GC_BOOST (((REG32(ADR_BT_RX_FE_MG_REGISTER)) & 0x00300000 ) >> 20)
+#define GET_RG_BT_RX_MG_DIV2_CORE (((REG32(ADR_BT_RX_FE_MG_REGISTER)) & 0x00c00000 ) >> 22)
+#define GET_RG_BT_RX_MG_LOBUF (((REG32(ADR_BT_RX_FE_MG_REGISTER)) & 0x03000000 ) >> 24)
+#define GET_RG_BT_RX_MG_TZI (((REG32(ADR_BT_RX_FE_MG_REGISTER)) & 0x1c000000 ) >> 26)
+#define GET_RG_BT_RX_MG_TZ_VCM (((REG32(ADR_BT_RX_FE_MG_REGISTER)) & 0xe0000000 ) >> 29)
+#define GET_RG_BT_RX_LG_LNA_GC (((REG32(ADR_BT_RX_FE_LG_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_BT_RX_LG_TZ_GC (((REG32(ADR_BT_RX_FE_LG_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_BT_RX_LG_LNAHGN_BIAS (((REG32(ADR_BT_RX_FE_LG_REGISTER)) & 0x000000f0 ) >> 4)
+#define GET_RG_BT_RX_LG_LNAHGP_BIAS (((REG32(ADR_BT_RX_FE_LG_REGISTER)) & 0x00000f00 ) >> 8)
+#define GET_RG_BT_RX_LG_LNALG_BIAS (((REG32(ADR_BT_RX_FE_LG_REGISTER)) & 0x0000f000 ) >> 12)
+#define GET_RG_BT_RX_LG_TZ_CAP (((REG32(ADR_BT_RX_FE_LG_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_BT_RX_LG_TZ_GC_BOOST (((REG32(ADR_BT_RX_FE_LG_REGISTER)) & 0x00300000 ) >> 20)
+#define GET_RG_BT_RX_LG_DIV2_CORE (((REG32(ADR_BT_RX_FE_LG_REGISTER)) & 0x00c00000 ) >> 22)
+#define GET_RG_BT_RX_LG_LOBUF (((REG32(ADR_BT_RX_FE_LG_REGISTER)) & 0x03000000 ) >> 24)
+#define GET_RG_BT_RX_LG_TZI (((REG32(ADR_BT_RX_FE_LG_REGISTER)) & 0x1c000000 ) >> 26)
+#define GET_RG_BT_RX_LG_TZ_VCM (((REG32(ADR_BT_RX_FE_LG_REGISTER)) & 0xe0000000 ) >> 29)
+#define GET_RG_BT_RX_ULG_LNA_GC (((REG32(ADR_BT_RX_FE_ULG_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_BT_RX_ULG_TZ_GC (((REG32(ADR_BT_RX_FE_ULG_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_BT_RX_ULG_LNAHGN_BIAS (((REG32(ADR_BT_RX_FE_ULG_REGISTER)) & 0x000000f0 ) >> 4)
+#define GET_RG_BT_RX_ULG_LNAHGP_BIAS (((REG32(ADR_BT_RX_FE_ULG_REGISTER)) & 0x00000f00 ) >> 8)
+#define GET_RG_BT_RX_ULG_LNALG_BIAS (((REG32(ADR_BT_RX_FE_ULG_REGISTER)) & 0x0000f000 ) >> 12)
+#define GET_RG_BT_RX_ULG_TZ_CAP (((REG32(ADR_BT_RX_FE_ULG_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_BT_RX_ULG_TZ_GC_BOOST (((REG32(ADR_BT_RX_FE_ULG_REGISTER)) & 0x00300000 ) >> 20)
+#define GET_RG_BT_RX_ULG_DIV2_CORE (((REG32(ADR_BT_RX_FE_ULG_REGISTER)) & 0x00c00000 ) >> 22)
+#define GET_RG_BT_RX_ULG_LOBUF (((REG32(ADR_BT_RX_FE_ULG_REGISTER)) & 0x03000000 ) >> 24)
+#define GET_RG_BT_RX_ULG_TZI (((REG32(ADR_BT_RX_FE_ULG_REGISTER)) & 0x1c000000 ) >> 26)
+#define GET_RG_BT_RX_ULG_TZ_VCM (((REG32(ADR_BT_RX_FE_ULG_REGISTER)) & 0xe0000000 ) >> 29)
+#define GET_RG_RX_ADC_CLKSEL (((REG32(ADR_WBT_RX_ADC_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_RX_ADC_DNLEN (((REG32(ADR_WBT_RX_ADC_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_RG_RX_ADC_METAEN (((REG32(ADR_WBT_RX_ADC_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_RG_RX_ADC_TFLAG (((REG32(ADR_WBT_RX_ADC_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_RG_RX_ADC_TSEL (((REG32(ADR_WBT_RX_ADC_REGISTER)) & 0x000000f0 ) >> 4)
+#define GET_RG_WF_RX_ADC_ICMP (((REG32(ADR_WBT_RX_ADC_REGISTER)) & 0x00000300 ) >> 8)
+#define GET_RG_WF_RX_ADC_VCMI (((REG32(ADR_WBT_RX_ADC_REGISTER)) & 0x00000c00 ) >> 10)
+#define GET_RG_WF_RX_ADC_CLOAD (((REG32(ADR_WBT_RX_ADC_REGISTER)) & 0x00003000 ) >> 12)
+#define GET_RG_WF_RX_ADC_PSW (((REG32(ADR_WBT_RX_ADC_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_RG_BT_RX_ADC_ICMP (((REG32(ADR_WBT_RX_ADC_REGISTER)) & 0x00030000 ) >> 16)
+#define GET_RG_BT_RX_ADC_VCMI (((REG32(ADR_WBT_RX_ADC_REGISTER)) & 0x000c0000 ) >> 18)
+#define GET_RG_BT_RX_ADC_CLOAD (((REG32(ADR_WBT_RX_ADC_REGISTER)) & 0x00300000 ) >> 20)
+#define GET_RG_BT_RX_ADC_PSW (((REG32(ADR_WBT_RX_ADC_REGISTER)) & 0x00400000 ) >> 22)
+#define GET_RG_SARADC_5G_TSSI (((REG32(ADR_WBT_RX_ADC_REGISTER)) & 0x00800000 ) >> 23)
+#define GET_RG_SARADC_VRSEL (((REG32(ADR_WBT_RX_ADC_REGISTER)) & 0x03000000 ) >> 24)
+#define GET_RG_EN_SAR_TEST (((REG32(ADR_WBT_RX_ADC_REGISTER)) & 0x0c000000 ) >> 26)
+#define GET_RG_SARADC_THERMAL (((REG32(ADR_WBT_RX_ADC_REGISTER)) & 0x10000000 ) >> 28)
+#define GET_RG_SARADC_TSSI (((REG32(ADR_WBT_RX_ADC_REGISTER)) & 0x20000000 ) >> 29)
+#define GET_RG_CLK_SAR_SEL (((REG32(ADR_WBT_RX_ADC_REGISTER)) & 0xc0000000 ) >> 30)
+#define GET_RG_WF_TX_DACI1ST (((REG32(ADR_WIFI_TX_DAC_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_WF_TX_DACLPF_ICOARSE (((REG32(ADR_WIFI_TX_DAC_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_WF_TX_DACLPF_IFINE (((REG32(ADR_WIFI_TX_DAC_REGISTER)) & 0x00000030 ) >> 4)
+#define GET_RG_WF_TX_DACLPF_VCM (((REG32(ADR_WIFI_TX_DAC_REGISTER)) & 0x000000c0 ) >> 6)
+#define GET_RG_WF_TX_DAC_IBIAS (((REG32(ADR_WIFI_TX_DAC_REGISTER)) & 0x00000300 ) >> 8)
+#define GET_RG_WF_TX_DAC_IATTN (((REG32(ADR_WIFI_TX_DAC_REGISTER)) & 0x00000400 ) >> 10)
+#define GET_RG_WF_TXLPF_BOOSTI (((REG32(ADR_WIFI_TX_DAC_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_RG_WF_TX_DAC_RCAL (((REG32(ADR_WIFI_TX_DAC_REGISTER)) & 0x00003000 ) >> 12)
+#define GET_RG_WF_TX_DAC_CKEDGE_SEL (((REG32(ADR_WIFI_TX_DAC_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_RG_WF_TX_DAC_OS (((REG32(ADR_WIFI_TX_DAC_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_WF_TX_DAC_IOFFSET (((REG32(ADR_WIFI_TX_DAC_REGISTER)) & 0x00f00000 ) >> 20)
+#define GET_RG_WF_TX_DAC_QOFFSET (((REG32(ADR_WIFI_TX_DAC_REGISTER)) & 0x0f000000 ) >> 24)
+#define GET_RG_TX_DAC_TSEL (((REG32(ADR_WIFI_TX_DAC_REGISTER)) & 0xf0000000 ) >> 28)
+#define GET_RG_BT_TX_DACI1ST (((REG32(ADR_BT_TX_DAC_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_BT_TX_DACLPF_ICOARSE (((REG32(ADR_BT_TX_DAC_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_BT_TX_DACLPF_IFINE (((REG32(ADR_BT_TX_DAC_REGISTER)) & 0x00000030 ) >> 4)
+#define GET_RG_BT_TX_DACLPF_VCM (((REG32(ADR_BT_TX_DAC_REGISTER)) & 0x000000c0 ) >> 6)
+#define GET_RG_BT_TX_DAC_IBIAS (((REG32(ADR_BT_TX_DAC_REGISTER)) & 0x00000300 ) >> 8)
+#define GET_RG_BT_TX_DAC_IATTN (((REG32(ADR_BT_TX_DAC_REGISTER)) & 0x00000400 ) >> 10)
+#define GET_RG_BT_TXLPF_BOOSTI (((REG32(ADR_BT_TX_DAC_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_RG_BT_TX_DAC_RCAL (((REG32(ADR_BT_TX_DAC_REGISTER)) & 0x00003000 ) >> 12)
+#define GET_RG_BT_TX_DAC_CKEDGE_SEL (((REG32(ADR_BT_TX_DAC_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_RG_BT_TX_DAC_OS (((REG32(ADR_BT_TX_DAC_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_BT_TX_DAC_IOFFSET (((REG32(ADR_BT_TX_DAC_REGISTER)) & 0x00f00000 ) >> 20)
+#define GET_RG_BT_TX_DAC_QOFFSET (((REG32(ADR_BT_TX_DAC_REGISTER)) & 0x0f000000 ) >> 24)
+#define GET_RG_SX_EN_MAN (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000001 ) >> 0)
+#define GET_RG_SX_EN (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000002 ) >> 1)
+#define GET_RG_EN_SX_CP_MAN (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000004 ) >> 2)
+#define GET_RG_EN_SX_CP (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000008 ) >> 3)
+#define GET_RG_EN_SX_DIV_MAN (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000010 ) >> 4)
+#define GET_RG_EN_SX_DIV (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000020 ) >> 5)
+#define GET_RG_EN_SX_VCO_MAN (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000040 ) >> 6)
+#define GET_RG_EN_SX_VCO (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000080 ) >> 7)
+#define GET_RG_SX_PFD_RST_MAN (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000100 ) >> 8)
+#define GET_RG_SX_PFD_RST (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000200 ) >> 9)
+#define GET_RG_SX_UOP_MAN (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000400 ) >> 10)
+#define GET_RG_SX_UOP_EN (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000800 ) >> 11)
+#define GET_RG_EN_VCOBF_TXMB_MAN (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00001000 ) >> 12)
+#define GET_RG_EN_VCOBF_TXMB (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00002000 ) >> 13)
+#define GET_RG_EN_VCOBF_TXOB_MAN (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00004000 ) >> 14)
+#define GET_RG_EN_VCOBF_TXOB (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00008000 ) >> 15)
+#define GET_RG_EN_VCOBF_RXMB_MAN (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00010000 ) >> 16)
+#define GET_RG_EN_VCOBF_RXMB (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00020000 ) >> 17)
+#define GET_RG_EN_VCOBF_RXOB_MAN (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00040000 ) >> 18)
+#define GET_RG_EN_VCOBF_RXOB (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00080000 ) >> 19)
+#define GET_RG_EN_VCOBF_DIVCK_MAN (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00100000 ) >> 20)
+#define GET_RG_EN_VCOBF_DIVCK (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00200000 ) >> 21)
+#define GET_RG_SX_SBCAL_DIS (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00800000 ) >> 23)
+#define GET_RG_SX_SBCAL_AW (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x01000000 ) >> 24)
+#define GET_RG_SX_AAC_DIS (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x04000000 ) >> 26)
+#define GET_RG_SX_TTL_DIS (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x08000000 ) >> 27)
+#define GET_RG_SX_CAL_INIT (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0xe0000000 ) >> 29)
+#define GET_RG_EN_SX_LDO_MAN (((REG32(ADR_SX_2_4G_LDO_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_EN_LDO_CP (((REG32(ADR_SX_2_4G_LDO_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_RG_EN_LDO_DIV (((REG32(ADR_SX_2_4G_LDO_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_RG_EN_LDO_LO (((REG32(ADR_SX_2_4G_LDO_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_RG_EN_LDO_VCO (((REG32(ADR_SX_2_4G_LDO_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_RG_EN_LDO_VCO_PSW (((REG32(ADR_SX_2_4G_LDO_REGISTER)) & 0x00000200 ) >> 9)
+#define GET_RG_EN_LDO_VCO_VDD33 (((REG32(ADR_SX_2_4G_LDO_REGISTER)) & 0x00000400 ) >> 10)
+#define GET_RG_EN_LDO_CP_IQUP (((REG32(ADR_SX_2_4G_LDO_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_RG_EN_LDO_DIV_IQUP (((REG32(ADR_SX_2_4G_LDO_REGISTER)) & 0x00001000 ) >> 12)
+#define GET_RG_EN_LDO_LO_IQUP (((REG32(ADR_SX_2_4G_LDO_REGISTER)) & 0x00002000 ) >> 13)
+#define GET_RG_EN_LDO_VCO_IQUP (((REG32(ADR_SX_2_4G_LDO_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_RG_SX_LDO_FCOFFT (((REG32(ADR_SX_2_4G_LDO_REGISTER)) & 0x00380000 ) >> 19)
+#define GET_RG_LDO_CP_FC_MAN (((REG32(ADR_SX_2_4G_LDO_REGISTER)) & 0x00400000 ) >> 22)
+#define GET_RG_LDO_CP_FC (((REG32(ADR_SX_2_4G_LDO_REGISTER)) & 0x00800000 ) >> 23)
+#define GET_RG_LDO_DIV_FC_MAN (((REG32(ADR_SX_2_4G_LDO_REGISTER)) & 0x01000000 ) >> 24)
+#define GET_RG_LDO_DIV_FC (((REG32(ADR_SX_2_4G_LDO_REGISTER)) & 0x02000000 ) >> 25)
+#define GET_RG_LDO_LO_FC_MAN (((REG32(ADR_SX_2_4G_LDO_REGISTER)) & 0x04000000 ) >> 26)
+#define GET_RG_LDO_LO_FC (((REG32(ADR_SX_2_4G_LDO_REGISTER)) & 0x08000000 ) >> 27)
+#define GET_RG_LDO_VCO_FC_MAN (((REG32(ADR_SX_2_4G_LDO_REGISTER)) & 0x10000000 ) >> 28)
+#define GET_RG_LDO_VCO_FC (((REG32(ADR_SX_2_4G_LDO_REGISTER)) & 0x20000000 ) >> 29)
+#define GET_RG_LDO_VCO_RCF (((REG32(ADR_SX_2_4G_LDO_REGISTER)) & 0xc0000000 ) >> 30)
+#define GET_RG_SX_RFCTRL_F (((REG32(ADR_SX_2_4GB_FRACTIONAL_AND_INTEGER_8BITS)) & 0x00ffffff ) >> 0)
+#define GET_RG_SX_RFCTRL_CH_7_0 (((REG32(ADR_SX_2_4GB_FRACTIONAL_AND_INTEGER_8BITS)) & 0xff000000 ) >> 24)
+#define GET_RG_SX_RFCTRL_CH_10_8 (((REG32(ADR_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE)) & 0x00000007 ) >> 0)
+#define GET_RG_SX_RFCH_MAP_EN (((REG32(ADR_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE)) & 0x00000008 ) >> 3)
+#define GET_RG_SX_FREF_DOUB_MAN (((REG32(ADR_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE)) & 0x00000040 ) >> 6)
+#define GET_RG_SX_FREF_DOUB (((REG32(ADR_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE)) & 0x00000080 ) >> 7)
+#define GET_RG_SX_BTRX_SIDE (((REG32(ADR_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE)) & 0x00000100 ) >> 8)
+#define GET_RG_SX_LO_TIMES (((REG32(ADR_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE)) & 0x00000200 ) >> 9)
+#define GET_RG_SX_CHANNEL (((REG32(ADR_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE)) & 0x0007f800 ) >> 11)
+#define GET_RG_SX_XTAL_FREQ (((REG32(ADR_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE)) & 0x00f00000 ) >> 20)
+#define GET_RG_SX_CP_ISEL_BT (((REG32(ADR_SX_2_4GB_PFD_CHP_)) & 0x0000000f ) >> 0)
+#define GET_RG_SX_CP_ISEL50U_BT (((REG32(ADR_SX_2_4GB_PFD_CHP_)) & 0x00000010 ) >> 4)
+#define GET_RG_SX_CP_KP_DOUB_BT (((REG32(ADR_SX_2_4GB_PFD_CHP_)) & 0x00000020 ) >> 5)
+#define GET_RG_SX_CP_ISEL_WF (((REG32(ADR_SX_2_4GB_PFD_CHP_)) & 0x00000780 ) >> 7)
+#define GET_RG_SX_CP_ISEL50U_WF (((REG32(ADR_SX_2_4GB_PFD_CHP_)) & 0x00000800 ) >> 11)
+#define GET_RG_SX_CP_KP_DOUB_WF (((REG32(ADR_SX_2_4GB_PFD_CHP_)) & 0x00001000 ) >> 12)
+#define GET_RG_SX_CP_IOST_POL (((REG32(ADR_SX_2_4GB_PFD_CHP_)) & 0x00008000 ) >> 15)
+#define GET_RG_SX_CP_IOST (((REG32(ADR_SX_2_4GB_PFD_CHP_)) & 0x00070000 ) >> 16)
+#define GET_RG_SX_PFD_SEL (((REG32(ADR_SX_2_4GB_PFD_CHP_)) & 0x00400000 ) >> 22)
+#define GET_RG_SX_PFD_SET (((REG32(ADR_SX_2_4GB_PFD_CHP_)) & 0x00800000 ) >> 23)
+#define GET_RG_SX_PFD_SET1 (((REG32(ADR_SX_2_4GB_PFD_CHP_)) & 0x01000000 ) >> 24)
+#define GET_RG_SX_PFD_SET2 (((REG32(ADR_SX_2_4GB_PFD_CHP_)) & 0x02000000 ) >> 25)
+#define GET_RG_SX_PFD_REF_EDGE (((REG32(ADR_SX_2_4GB_PFD_CHP_)) & 0x04000000 ) >> 26)
+#define GET_RG_SX_PFD_DIV_EDGE (((REG32(ADR_SX_2_4GB_PFD_CHP_)) & 0x08000000 ) >> 27)
+#define GET_RG_SX_PFD_TRUP (((REG32(ADR_SX_2_4GB_PFD_CHP_)) & 0x10000000 ) >> 28)
+#define GET_RG_SX_PFD_TRDN (((REG32(ADR_SX_2_4GB_PFD_CHP_)) & 0x20000000 ) >> 29)
+#define GET_RG_SX_PFD_TLSEL (((REG32(ADR_SX_2_4GB_PFD_CHP_)) & 0x40000000 ) >> 30)
+#define GET_RG_SX_LPF_C1_BT (((REG32(ADR_SX_2_4GB_LPF)) & 0x0000000f ) >> 0)
+#define GET_RG_SX_LPF_C2_BT (((REG32(ADR_SX_2_4GB_LPF)) & 0x000000f0 ) >> 4)
+#define GET_RG_SX_LPF_C3_BT (((REG32(ADR_SX_2_4GB_LPF)) & 0x00000100 ) >> 8)
+#define GET_RG_SX_LPF_R2_BT (((REG32(ADR_SX_2_4GB_LPF)) & 0x00001e00 ) >> 9)
+#define GET_RG_SX_LPF_R3_BT (((REG32(ADR_SX_2_4GB_LPF)) & 0x0000e000 ) >> 13)
+#define GET_RG_SX_LPF_C1_WF (((REG32(ADR_SX_2_4GB_LPF)) & 0x000f0000 ) >> 16)
+#define GET_RG_SX_LPF_C2_WF (((REG32(ADR_SX_2_4GB_LPF)) & 0x00f00000 ) >> 20)
+#define GET_RG_SX_LPF_C3_WF (((REG32(ADR_SX_2_4GB_LPF)) & 0x01000000 ) >> 24)
+#define GET_RG_SX_LPF_R2_WF (((REG32(ADR_SX_2_4GB_LPF)) & 0x1e000000 ) >> 25)
+#define GET_RG_SX_LPF_R3_WF (((REG32(ADR_SX_2_4GB_LPF)) & 0xe0000000 ) >> 29)
+#define GET_RG_SX_VCO_ISEL_MAN (((REG32(ADR_SX_2_4GB_VCO)) & 0x00000001 ) >> 0)
+#define GET_RG_SX_VCO_ISEL_BT (((REG32(ADR_SX_2_4GB_VCO)) & 0x0000001e ) >> 1)
+#define GET_RG_SX_VCO_LPM_BT (((REG32(ADR_SX_2_4GB_VCO)) & 0x00000020 ) >> 5)
+#define GET_RG_SX_VCO_VCCBSEL_BT (((REG32(ADR_SX_2_4GB_VCO)) & 0x000001c0 ) >> 6)
+#define GET_RG_SX_VCO_KVDOUB_BT (((REG32(ADR_SX_2_4GB_VCO)) & 0x00000200 ) >> 9)
+#define GET_RG_SX_VCO_ISEL_WF (((REG32(ADR_SX_2_4GB_VCO)) & 0x00003c00 ) >> 10)
+#define GET_RG_SX_VCO_LPM_WF (((REG32(ADR_SX_2_4GB_VCO)) & 0x00004000 ) >> 14)
+#define GET_RG_SX_VCO_VCCBSEL_WF (((REG32(ADR_SX_2_4GB_VCO)) & 0x00038000 ) >> 15)
+#define GET_RG_SX_VCO_KVDOUB_WF (((REG32(ADR_SX_2_4GB_VCO)) & 0x00040000 ) >> 18)
+#define GET_RG_SX_VCO_VARBSEL (((REG32(ADR_SX_2_4GB_VCO)) & 0x00600000 ) >> 21)
+#define GET_RG_SX_VCO_RTAIL_SHIFT (((REG32(ADR_SX_2_4GB_VCO)) & 0x00800000 ) >> 23)
+#define GET_RG_SX_VCO_CS_AWH (((REG32(ADR_SX_2_4GB_VCO)) & 0x01000000 ) >> 24)
+#define GET_RG_VOBF_TXMBSEL_BT (((REG32(ADR_SX_2_4GB_VCOBF)) & 0x00000003 ) >> 0)
+#define GET_RG_VOBF_TXOBSEL_BT (((REG32(ADR_SX_2_4GB_VCOBF)) & 0x0000000c ) >> 2)
+#define GET_RG_VOBF_RXMBSEL_BT (((REG32(ADR_SX_2_4GB_VCOBF)) & 0x00000030 ) >> 4)
+#define GET_RG_VOBF_RXOBSEL_BT (((REG32(ADR_SX_2_4GB_VCOBF)) & 0x000000c0 ) >> 6)
+#define GET_RG_VOBF_TXMBSEL_WF (((REG32(ADR_SX_2_4GB_VCOBF)) & 0x00000c00 ) >> 10)
+#define GET_RG_VOBF_TXOBSEL_WF (((REG32(ADR_SX_2_4GB_VCOBF)) & 0x00003000 ) >> 12)
+#define GET_RG_VOBF_RXMBSEL_WF (((REG32(ADR_SX_2_4GB_VCOBF)) & 0x0000c000 ) >> 14)
+#define GET_RG_VOBF_RXOBSEL_WF (((REG32(ADR_SX_2_4GB_VCOBF)) & 0x00030000 ) >> 16)
+#define GET_RG_VOBF_DIVBFSEL (((REG32(ADR_SX_2_4GB_VCOBF)) & 0x00080000 ) >> 19)
+#define GET_RG_SX_VCO_TXOB_AW (((REG32(ADR_SX_2_4GB_VCOBF)) & 0x00100000 ) >> 20)
+#define GET_RG_SX_VCO_RXOB_AW (((REG32(ADR_SX_2_4GB_VCOBF)) & 0x00200000 ) >> 21)
+#define GET_RG_VOBF_CAPIMB_POL (((REG32(ADR_SX_2_4GB_VCOBF)) & 0x04000000 ) >> 26)
+#define GET_RG_VOBF_CAPIMB (((REG32(ADR_SX_2_4GB_VCOBF)) & 0x38000000 ) >> 27)
+#define GET_RG_EN_SX_VCOMON (((REG32(ADR_SX_2_4GB_VCOBF)) & 0x80000000 ) >> 31)
+#define GET_RG_SX_DIV_PREVDD (((REG32(ADR_SX_2_4GB_DIV_SDM)) & 0x0000000f ) >> 0)
+#define GET_RG_SX_DIV_PSCVDD (((REG32(ADR_SX_2_4GB_DIV_SDM)) & 0x000000f0 ) >> 4)
+#define GET_RG_SX_DIV_RST_H (((REG32(ADR_SX_2_4GB_DIV_SDM)) & 0x00000200 ) >> 9)
+#define GET_RG_SX_DIV_SDM_EDGE (((REG32(ADR_SX_2_4GB_DIV_SDM)) & 0x00000400 ) >> 10)
+#define GET_RG_SX_DIV_DMYBUF_EN (((REG32(ADR_SX_2_4GB_DIV_SDM)) & 0x00000800 ) >> 11)
+#define GET_RG_EN_SX_MOD (((REG32(ADR_SX_2_4GB_DIV_SDM)) & 0x00020000 ) >> 17)
+#define GET_RG_EN_SX_DITHER (((REG32(ADR_SX_2_4GB_DIV_SDM)) & 0x00040000 ) >> 18)
+#define GET_RG_SX_MOD_ORDER (((REG32(ADR_SX_2_4GB_DIV_SDM)) & 0x00180000 ) >> 19)
+#define GET_RG_SX_DITHER_WEIGHT (((REG32(ADR_SX_2_4GB_DIV_SDM)) & 0x00600000 ) >> 21)
+#define GET_RG_SX_SUB_SEL_MAN (((REG32(ADR_SX_2_4GB_SBCAL)) & 0x00000001 ) >> 0)
+#define GET_RG_SX_SUB_SEL (((REG32(ADR_SX_2_4GB_SBCAL)) & 0x000001fe ) >> 1)
+#define GET_RG_SX_SUB_C0P5_DIS (((REG32(ADR_SX_2_4GB_SBCAL)) & 0x00000200 ) >> 9)
+#define GET_RG_SX_SBCAL_CT (((REG32(ADR_SX_2_4GB_SBCAL)) & 0x00000c00 ) >> 10)
+#define GET_RG_SX_SBCAL_WT (((REG32(ADR_SX_2_4GB_SBCAL)) & 0x00001000 ) >> 12)
+#define GET_RG_SX_SBCAL_DIFFMIN (((REG32(ADR_SX_2_4GB_SBCAL)) & 0x00002000 ) >> 13)
+#define GET_RG_SX_SBCAL_NTARG_MAN (((REG32(ADR_SX_2_4GB_SBCAL)) & 0x00008000 ) >> 15)
+#define GET_RG_SX_SBCAL_NTARG (((REG32(ADR_SX_2_4GB_SBCAL)) & 0xffff0000 ) >> 16)
+#define GET_RG_VO_AAC_TAR_BT (((REG32(ADR_SX_2_4GB_AAC)) & 0x0000000f ) >> 0)
+#define GET_RG_VO_AAC_IOST_BT (((REG32(ADR_SX_2_4GB_AAC)) & 0x00000030 ) >> 4)
+#define GET_RG_VO_AAC_TAR_WF (((REG32(ADR_SX_2_4GB_AAC)) & 0x00000780 ) >> 7)
+#define GET_RG_VO_AAC_IOST_WF (((REG32(ADR_SX_2_4GB_AAC)) & 0x00001800 ) >> 11)
+#define GET_RG_VO_AAC_IMAX (((REG32(ADR_SX_2_4GB_AAC)) & 0x0003c000 ) >> 14)
+#define GET_RG_VO_AAC_INIT (((REG32(ADR_SX_2_4GB_AAC)) & 0x000c0000 ) >> 18)
+#define GET_RG_VO_AAC_EVA_TS (((REG32(ADR_SX_2_4GB_AAC)) & 0x00300000 ) >> 20)
+#define GET_RG_VO_AAC_EN_MAN (((REG32(ADR_SX_2_4GB_AAC)) & 0x00800000 ) >> 23)
+#define GET_RG_VO_AAC_EN (((REG32(ADR_SX_2_4GB_AAC)) & 0x01000000 ) >> 24)
+#define GET_RG_VO_AAC_EVA_MAN (((REG32(ADR_SX_2_4GB_AAC)) & 0x02000000 ) >> 25)
+#define GET_RG_VO_AAC_EVA (((REG32(ADR_SX_2_4GB_AAC)) & 0x04000000 ) >> 26)
+#define GET_RG_VO_AAC_TEST_EN (((REG32(ADR_SX_2_4GB_AAC)) & 0x10000000 ) >> 28)
+#define GET_RG_VO_AAC_TEST_SEL (((REG32(ADR_SX_2_4GB_AAC)) & 0x20000000 ) >> 29)
+#define GET_RG_SX_TTL_INIT (((REG32(ADR_SX_2_4GB_TTL)) & 0x00000003 ) >> 0)
+#define GET_RG_SX_TTL_FPT (((REG32(ADR_SX_2_4GB_TTL)) & 0x0000000c ) >> 2)
+#define GET_RG_SX_TTL_CPT (((REG32(ADR_SX_2_4GB_TTL)) & 0x00000030 ) >> 4)
+#define GET_RG_SX_TTL_ACCUM (((REG32(ADR_SX_2_4GB_TTL)) & 0x00000180 ) >> 7)
+#define GET_RG_SX_TTL_SUB (((REG32(ADR_SX_2_4GB_TTL)) & 0x00000c00 ) >> 10)
+#define GET_RG_SX_TTL_SUB_INV (((REG32(ADR_SX_2_4GB_TTL)) & 0x00001000 ) >> 12)
+#define GET_RG_SX_TTL_VH (((REG32(ADR_SX_2_4GB_TTL)) & 0x0000c000 ) >> 14)
+#define GET_RG_SX_TTL_VL (((REG32(ADR_SX_2_4GB_TTL)) & 0x00030000 ) >> 16)
+#define GET_RG_SX_LPF_VTUNE_TEST (((REG32(ADR_SX_2_4GB_TTL)) & 0x00080000 ) >> 19)
+#define GET_DPLL_TOP_REGISTER (((REG32(ADR_DPLL_TOP_REGISTER)) & 0xffffffff ) >> 0)
+#define GET_DPLL_CKT_REGISTER (((REG32(ADR_DPLL_CKT_REGISTER)) & 0xffffffff ) >> 0)
+#define GET_DPLL_FB_DIVISION__REGISTERS (((REG32(ADR_DPLL_FB_DIVISION__REGISTERS)) & 0xffffffff ) >> 0)
+#define GET_RG_WF_IDACAI_TZ0_PGAG15 (((REG32(ADR_WF_DCOC_IDAC_REGISTER1)) & 0x0000003f ) >> 0)
+#define GET_RG_WF_IDACAQ_TZ0_PGAG15 (((REG32(ADR_WF_DCOC_IDAC_REGISTER1)) & 0x00003f00 ) >> 8)
+#define GET_RG_WF_IDACAI_TZ0_PGAG14 (((REG32(ADR_WF_DCOC_IDAC_REGISTER1)) & 0x003f0000 ) >> 16)
+#define GET_RG_WF_IDACAQ_TZ0_PGAG14 (((REG32(ADR_WF_DCOC_IDAC_REGISTER1)) & 0x3f000000 ) >> 24)
+#define GET_RG_WF_IDACAI_TZ0_PGAG13 (((REG32(ADR_WF_DCOC_IDAC_REGISTER2)) & 0x0000003f ) >> 0)
+#define GET_RG_WF_IDACAQ_TZ0_PGAG13 (((REG32(ADR_WF_DCOC_IDAC_REGISTER2)) & 0x00003f00 ) >> 8)
+#define GET_RG_WF_IDACAI_TZ0_PGAG12 (((REG32(ADR_WF_DCOC_IDAC_REGISTER2)) & 0x003f0000 ) >> 16)
+#define GET_RG_WF_IDACAQ_TZ0_PGAG12 (((REG32(ADR_WF_DCOC_IDAC_REGISTER2)) & 0x3f000000 ) >> 24)
+#define GET_RG_WF_IDACAI_TZ0_PGAG11 (((REG32(ADR_WF_DCOC_IDAC_REGISTER3)) & 0x0000003f ) >> 0)
+#define GET_RG_WF_IDACAQ_TZ0_PGAG11 (((REG32(ADR_WF_DCOC_IDAC_REGISTER3)) & 0x00003f00 ) >> 8)
+#define GET_RG_WF_IDACAI_TZ0_PGAG10 (((REG32(ADR_WF_DCOC_IDAC_REGISTER3)) & 0x003f0000 ) >> 16)
+#define GET_RG_WF_IDACAQ_TZ0_PGAG10 (((REG32(ADR_WF_DCOC_IDAC_REGISTER3)) & 0x3f000000 ) >> 24)
+#define GET_RG_WF_IDACAI_TZ0_PGAG9 (((REG32(ADR_WF_DCOC_IDAC_REGISTER4)) & 0x0000003f ) >> 0)
+#define GET_RG_WF_IDACAQ_TZ0_PGAG9 (((REG32(ADR_WF_DCOC_IDAC_REGISTER4)) & 0x00003f00 ) >> 8)
+#define GET_RG_WF_IDACAI_TZ0_PGAG8 (((REG32(ADR_WF_DCOC_IDAC_REGISTER4)) & 0x003f0000 ) >> 16)
+#define GET_RG_WF_IDACAQ_TZ0_PGAG8 (((REG32(ADR_WF_DCOC_IDAC_REGISTER4)) & 0x3f000000 ) >> 24)
+#define GET_RG_WF_IDACAI_TZ0_PGAG7 (((REG32(ADR_WF_DCOC_IDAC_REGISTER5)) & 0x0000003f ) >> 0)
+#define GET_RG_WF_IDACAQ_TZ0_PGAG7 (((REG32(ADR_WF_DCOC_IDAC_REGISTER5)) & 0x00003f00 ) >> 8)
+#define GET_RG_WF_IDACAI_TZ0_PGAG6 (((REG32(ADR_WF_DCOC_IDAC_REGISTER5)) & 0x003f0000 ) >> 16)
+#define GET_RG_WF_IDACAQ_TZ0_PGAG6 (((REG32(ADR_WF_DCOC_IDAC_REGISTER5)) & 0x3f000000 ) >> 24)
+#define GET_RG_WF_IDACAI_TZ0_PGAG5 (((REG32(ADR_WF_DCOC_IDAC_REGISTER6)) & 0x0000003f ) >> 0)
+#define GET_RG_WF_IDACAQ_TZ0_PGAG5 (((REG32(ADR_WF_DCOC_IDAC_REGISTER6)) & 0x00003f00 ) >> 8)
+#define GET_RG_WF_IDACAI_TZ0_PGAG4 (((REG32(ADR_WF_DCOC_IDAC_REGISTER6)) & 0x003f0000 ) >> 16)
+#define GET_RG_WF_IDACAQ_TZ0_PGAG4 (((REG32(ADR_WF_DCOC_IDAC_REGISTER6)) & 0x3f000000 ) >> 24)
+#define GET_RG_WF_IDACAI_TZ0_PGAG3 (((REG32(ADR_WF_DCOC_IDAC_REGISTER7)) & 0x0000003f ) >> 0)
+#define GET_RG_WF_IDACAQ_TZ0_PGAG3 (((REG32(ADR_WF_DCOC_IDAC_REGISTER7)) & 0x00003f00 ) >> 8)
+#define GET_RG_WF_IDACAI_TZ0_PGAG2 (((REG32(ADR_WF_DCOC_IDAC_REGISTER7)) & 0x003f0000 ) >> 16)
+#define GET_RG_WF_IDACAQ_TZ0_PGAG2 (((REG32(ADR_WF_DCOC_IDAC_REGISTER7)) & 0x3f000000 ) >> 24)
+#define GET_RG_WF_IDACAI_TZ0_PGAG1 (((REG32(ADR_WF_DCOC_IDAC_REGISTER8)) & 0x0000003f ) >> 0)
+#define GET_RG_WF_IDACAQ_TZ0_PGAG1 (((REG32(ADR_WF_DCOC_IDAC_REGISTER8)) & 0x00003f00 ) >> 8)
+#define GET_RG_WF_IDACAI_TZ0_PGAG0 (((REG32(ADR_WF_DCOC_IDAC_REGISTER8)) & 0x003f0000 ) >> 16)
+#define GET_RG_WF_IDACAQ_TZ0_PGAG0 (((REG32(ADR_WF_DCOC_IDAC_REGISTER8)) & 0x3f000000 ) >> 24)
+#define GET_RG_WF_IDACAI_TZ1_PGAG15 (((REG32(ADR_WF_DCOC_IDAC_REGISTER9)) & 0x0000003f ) >> 0)
+#define GET_RG_WF_IDACAQ_TZ1_PGAG15 (((REG32(ADR_WF_DCOC_IDAC_REGISTER9)) & 0x00003f00 ) >> 8)
+#define GET_RG_WF_IDACAI_TZ1_PGAG14 (((REG32(ADR_WF_DCOC_IDAC_REGISTER9)) & 0x003f0000 ) >> 16)
+#define GET_RG_WF_IDACAQ_TZ1_PGAG14 (((REG32(ADR_WF_DCOC_IDAC_REGISTER9)) & 0x3f000000 ) >> 24)
+#define GET_RG_WF_IDACAI_TZ1_PGAG13 (((REG32(ADR_WF_DCOC_IDAC_REGISTER10)) & 0x0000003f ) >> 0)
+#define GET_RG_WF_IDACAQ_TZ1_PGAG13 (((REG32(ADR_WF_DCOC_IDAC_REGISTER10)) & 0x00003f00 ) >> 8)
+#define GET_RG_WF_IDACAI_TZ1_PGAG12 (((REG32(ADR_WF_DCOC_IDAC_REGISTER10)) & 0x003f0000 ) >> 16)
+#define GET_RG_WF_IDACAQ_TZ1_PGAG12 (((REG32(ADR_WF_DCOC_IDAC_REGISTER10)) & 0x3f000000 ) >> 24)
+#define GET_RG_WF_IDACAI_TZ1_PGAG11 (((REG32(ADR_WF_DCOC_IDAC_REGISTER11)) & 0x0000003f ) >> 0)
+#define GET_RG_WF_IDACAQ_TZ1_PGAG11 (((REG32(ADR_WF_DCOC_IDAC_REGISTER11)) & 0x00003f00 ) >> 8)
+#define GET_RG_WF_IDACAI_TZ1_PGAG10 (((REG32(ADR_WF_DCOC_IDAC_REGISTER11)) & 0x003f0000 ) >> 16)
+#define GET_RG_WF_IDACAQ_TZ1_PGAG10 (((REG32(ADR_WF_DCOC_IDAC_REGISTER11)) & 0x3f000000 ) >> 24)
+#define GET_RG_WF_IDACAI_TZ1_PGAG9 (((REG32(ADR_WF_DCOC_IDAC_REGISTER12)) & 0x0000003f ) >> 0)
+#define GET_RG_WF_IDACAQ_TZ1_PGAG9 (((REG32(ADR_WF_DCOC_IDAC_REGISTER12)) & 0x00003f00 ) >> 8)
+#define GET_RG_WF_IDACAI_TZ1_PGAG8 (((REG32(ADR_WF_DCOC_IDAC_REGISTER12)) & 0x003f0000 ) >> 16)
+#define GET_RG_WF_IDACAQ_TZ1_PGAG8 (((REG32(ADR_WF_DCOC_IDAC_REGISTER12)) & 0x3f000000 ) >> 24)
+#define GET_RG_WF_IDACAI_TZ1_PGAG7 (((REG32(ADR_WF_DCOC_IDAC_REGISTER13)) & 0x0000003f ) >> 0)
+#define GET_RG_WF_IDACAQ_TZ1_PGAG7 (((REG32(ADR_WF_DCOC_IDAC_REGISTER13)) & 0x00003f00 ) >> 8)
+#define GET_RG_WF_IDACAI_TZ1_PGAG6 (((REG32(ADR_WF_DCOC_IDAC_REGISTER13)) & 0x003f0000 ) >> 16)
+#define GET_RG_WF_IDACAQ_TZ1_PGAG6 (((REG32(ADR_WF_DCOC_IDAC_REGISTER13)) & 0x3f000000 ) >> 24)
+#define GET_RG_WF_IDACAI_TZ1_PGAG5 (((REG32(ADR_WF_DCOC_IDAC_REGISTER14)) & 0x0000003f ) >> 0)
+#define GET_RG_WF_IDACAQ_TZ1_PGAG5 (((REG32(ADR_WF_DCOC_IDAC_REGISTER14)) & 0x00003f00 ) >> 8)
+#define GET_RG_WF_IDACAI_TZ1_PGAG4 (((REG32(ADR_WF_DCOC_IDAC_REGISTER14)) & 0x003f0000 ) >> 16)
+#define GET_RG_WF_IDACAQ_TZ1_PGAG4 (((REG32(ADR_WF_DCOC_IDAC_REGISTER14)) & 0x3f000000 ) >> 24)
+#define GET_RG_WF_IDACAI_TZ1_PGAG3 (((REG32(ADR_WF_DCOC_IDAC_REGISTER15)) & 0x0000003f ) >> 0)
+#define GET_RG_WF_IDACAQ_TZ1_PGAG3 (((REG32(ADR_WF_DCOC_IDAC_REGISTER15)) & 0x00003f00 ) >> 8)
+#define GET_RG_WF_IDACAI_TZ1_PGAG2 (((REG32(ADR_WF_DCOC_IDAC_REGISTER15)) & 0x003f0000 ) >> 16)
+#define GET_RG_WF_IDACAQ_TZ1_PGAG2 (((REG32(ADR_WF_DCOC_IDAC_REGISTER15)) & 0x3f000000 ) >> 24)
+#define GET_RG_WF_IDACAI_TZ1_PGAG1 (((REG32(ADR_WF_DCOC_IDAC_REGISTER16)) & 0x0000003f ) >> 0)
+#define GET_RG_WF_IDACAQ_TZ1_PGAG1 (((REG32(ADR_WF_DCOC_IDAC_REGISTER16)) & 0x00003f00 ) >> 8)
+#define GET_RG_WF_IDACAI_TZ1_PGAG0 (((REG32(ADR_WF_DCOC_IDAC_REGISTER16)) & 0x003f0000 ) >> 16)
+#define GET_RG_WF_IDACAQ_TZ1_PGAG0 (((REG32(ADR_WF_DCOC_IDAC_REGISTER16)) & 0x3f000000 ) >> 24)
+#define GET_RG_IDACAI_TZ0_COARSE4 (((REG32(ADR_WF_DCOC_IDAC_REGISTER17)) & 0x0000003f ) >> 0)
+#define GET_RG_IDACAQ_TZ0_COARSE4 (((REG32(ADR_WF_DCOC_IDAC_REGISTER17)) & 0x00003f00 ) >> 8)
+#define GET_RG_IDACAI_TZ0_COARSE3 (((REG32(ADR_WF_DCOC_IDAC_REGISTER17)) & 0x003f0000 ) >> 16)
+#define GET_RG_IDACAQ_TZ0_COARSE3 (((REG32(ADR_WF_DCOC_IDAC_REGISTER17)) & 0x3f000000 ) >> 24)
+#define GET_RG_IDACAI_TZ0_COARSE2 (((REG32(ADR_WF_DCOC_IDAC_REGISTER18)) & 0x0000003f ) >> 0)
+#define GET_RG_IDACAQ_TZ0_COARSE2 (((REG32(ADR_WF_DCOC_IDAC_REGISTER18)) & 0x00003f00 ) >> 8)
+#define GET_RG_IDACAI_TZ0_COARSE1 (((REG32(ADR_WF_DCOC_IDAC_REGISTER18)) & 0x003f0000 ) >> 16)
+#define GET_RG_IDACAQ_TZ0_COARSE1 (((REG32(ADR_WF_DCOC_IDAC_REGISTER18)) & 0x3f000000 ) >> 24)
+#define GET_RG_IDACAI_TZ0_COARSE0 (((REG32(ADR_WF_DCOC_IDAC_REGISTER19)) & 0x0000003f ) >> 0)
+#define GET_RG_IDACAQ_TZ0_COARSE0 (((REG32(ADR_WF_DCOC_IDAC_REGISTER19)) & 0x00003f00 ) >> 8)
+#define GET_RG_IDACAI_TZ1_COARSE4 (((REG32(ADR_WF_DCOC_IDAC_REGISTER19)) & 0x003f0000 ) >> 16)
+#define GET_RG_IDACAQ_TZ1_COARSE4 (((REG32(ADR_WF_DCOC_IDAC_REGISTER19)) & 0x3f000000 ) >> 24)
+#define GET_RG_IDACAI_TZ1_COARSE3 (((REG32(ADR_WF_DCOC_IDAC_REGISTER20)) & 0x0000003f ) >> 0)
+#define GET_RG_IDACAQ_TZ1_COARSE3 (((REG32(ADR_WF_DCOC_IDAC_REGISTER20)) & 0x00003f00 ) >> 8)
+#define GET_RG_IDACAI_TZ1_COARSE2 (((REG32(ADR_WF_DCOC_IDAC_REGISTER20)) & 0x003f0000 ) >> 16)
+#define GET_RG_IDACAQ_TZ1_COARSE2 (((REG32(ADR_WF_DCOC_IDAC_REGISTER20)) & 0x3f000000 ) >> 24)
+#define GET_RG_IDACAI_TZ1_COARSE1 (((REG32(ADR_WF_DCOC_IDAC_REGISTER21)) & 0x0000003f ) >> 0)
+#define GET_RG_IDACAQ_TZ1_COARSE1 (((REG32(ADR_WF_DCOC_IDAC_REGISTER21)) & 0x00003f00 ) >> 8)
+#define GET_RG_IDACAI_TZ1_COARSE0 (((REG32(ADR_WF_DCOC_IDAC_REGISTER21)) & 0x003f0000 ) >> 16)
+#define GET_RG_IDACAQ_TZ1_COARSE0 (((REG32(ADR_WF_DCOC_IDAC_REGISTER21)) & 0x3f000000 ) >> 24)
+#define GET_RG_BT_IDACAI_TZ0_PGAG15 (((REG32(ADR_BT_DCOC_IDAC_REGISTER1)) & 0x0000003f ) >> 0)
+#define GET_RG_BT_IDACAQ_TZ0_PGAG15 (((REG32(ADR_BT_DCOC_IDAC_REGISTER1)) & 0x00003f00 ) >> 8)
+#define GET_RG_BT_IDACAI_TZ0_PGAG14 (((REG32(ADR_BT_DCOC_IDAC_REGISTER1)) & 0x003f0000 ) >> 16)
+#define GET_RG_BT_IDACAQ_TZ0_PGAG14 (((REG32(ADR_BT_DCOC_IDAC_REGISTER1)) & 0x3f000000 ) >> 24)
+#define GET_RG_BT_IDACAI_TZ0_PGAG13 (((REG32(ADR_BT_DCOC_IDAC_REGISTER2)) & 0x0000003f ) >> 0)
+#define GET_RG_BT_IDACAQ_TZ0_PGAG13 (((REG32(ADR_BT_DCOC_IDAC_REGISTER2)) & 0x00003f00 ) >> 8)
+#define GET_RG_BT_IDACAI_TZ0_PGAG12 (((REG32(ADR_BT_DCOC_IDAC_REGISTER2)) & 0x003f0000 ) >> 16)
+#define GET_RG_BT_IDACAQ_TZ0_PGAG12 (((REG32(ADR_BT_DCOC_IDAC_REGISTER2)) & 0x3f000000 ) >> 24)
+#define GET_RG_BT_IDACAI_TZ0_PGAG11 (((REG32(ADR_BT_DCOC_IDAC_REGISTER3)) & 0x0000003f ) >> 0)
+#define GET_RG_BT_IDACAQ_TZ0_PGAG11 (((REG32(ADR_BT_DCOC_IDAC_REGISTER3)) & 0x00003f00 ) >> 8)
+#define GET_RG_BT_IDACAI_TZ0_PGAG10 (((REG32(ADR_BT_DCOC_IDAC_REGISTER3)) & 0x003f0000 ) >> 16)
+#define GET_RG_BT_IDACAQ_TZ0_PGAG10 (((REG32(ADR_BT_DCOC_IDAC_REGISTER3)) & 0x3f000000 ) >> 24)
+#define GET_RG_BT_IDACAI_TZ0_PGAG9 (((REG32(ADR_BT_DCOC_IDAC_REGISTER4)) & 0x0000003f ) >> 0)
+#define GET_RG_BT_IDACAQ_TZ0_PGAG9 (((REG32(ADR_BT_DCOC_IDAC_REGISTER4)) & 0x00003f00 ) >> 8)
+#define GET_RG_BT_IDACAI_TZ0_PGAG8 (((REG32(ADR_BT_DCOC_IDAC_REGISTER4)) & 0x003f0000 ) >> 16)
+#define GET_RG_BT_IDACAQ_TZ0_PGAG8 (((REG32(ADR_BT_DCOC_IDAC_REGISTER4)) & 0x3f000000 ) >> 24)
+#define GET_RG_BT_IDACAI_TZ0_PGAG7 (((REG32(ADR_BT_DCOC_IDAC_REGISTER5)) & 0x0000003f ) >> 0)
+#define GET_RG_BT_IDACAQ_TZ0_PGAG7 (((REG32(ADR_BT_DCOC_IDAC_REGISTER5)) & 0x00003f00 ) >> 8)
+#define GET_RG_BT_IDACAI_TZ0_PGAG6 (((REG32(ADR_BT_DCOC_IDAC_REGISTER5)) & 0x003f0000 ) >> 16)
+#define GET_RG_BT_IDACAQ_TZ0_PGAG6 (((REG32(ADR_BT_DCOC_IDAC_REGISTER5)) & 0x3f000000 ) >> 24)
+#define GET_RG_BT_IDACAI_TZ0_PGAG5 (((REG32(ADR_BT_DCOC_IDAC_REGISTER6)) & 0x0000003f ) >> 0)
+#define GET_RG_BT_IDACAQ_TZ0_PGAG5 (((REG32(ADR_BT_DCOC_IDAC_REGISTER6)) & 0x00003f00 ) >> 8)
+#define GET_RG_BT_IDACAI_TZ0_PGAG4 (((REG32(ADR_BT_DCOC_IDAC_REGISTER6)) & 0x003f0000 ) >> 16)
+#define GET_RG_BT_IDACAQ_TZ0_PGAG4 (((REG32(ADR_BT_DCOC_IDAC_REGISTER6)) & 0x3f000000 ) >> 24)
+#define GET_RG_BT_IDACAI_TZ0_PGAG3 (((REG32(ADR_BT_DCOC_IDAC_REGISTER7)) & 0x0000003f ) >> 0)
+#define GET_RG_BT_IDACAQ_TZ0_PGAG3 (((REG32(ADR_BT_DCOC_IDAC_REGISTER7)) & 0x00003f00 ) >> 8)
+#define GET_RG_BT_IDACAI_TZ0_PGAG2 (((REG32(ADR_BT_DCOC_IDAC_REGISTER7)) & 0x003f0000 ) >> 16)
+#define GET_RG_BT_IDACAQ_TZ0_PGAG2 (((REG32(ADR_BT_DCOC_IDAC_REGISTER7)) & 0x3f000000 ) >> 24)
+#define GET_RG_BT_IDACAI_TZ0_PGAG1 (((REG32(ADR_BT_DCOC_IDAC_REGISTER8)) & 0x0000003f ) >> 0)
+#define GET_RG_BT_IDACAQ_TZ0_PGAG1 (((REG32(ADR_BT_DCOC_IDAC_REGISTER8)) & 0x00003f00 ) >> 8)
+#define GET_RG_BT_IDACAI_TZ0_PGAG0 (((REG32(ADR_BT_DCOC_IDAC_REGISTER8)) & 0x003f0000 ) >> 16)
+#define GET_RG_BT_IDACAQ_TZ0_PGAG0 (((REG32(ADR_BT_DCOC_IDAC_REGISTER8)) & 0x3f000000 ) >> 24)
+#define GET_RG_BT_IDACAI_TZ1_PGAG15 (((REG32(ADR_BT_DCOC_IDAC_REGISTER9)) & 0x0000003f ) >> 0)
+#define GET_RG_BT_IDACAQ_TZ1_PGAG15 (((REG32(ADR_BT_DCOC_IDAC_REGISTER9)) & 0x00003f00 ) >> 8)
+#define GET_RG_BT_IDACAI_TZ1_PGAG14 (((REG32(ADR_BT_DCOC_IDAC_REGISTER9)) & 0x003f0000 ) >> 16)
+#define GET_RG_BT_IDACAQ_TZ1_PGAG14 (((REG32(ADR_BT_DCOC_IDAC_REGISTER9)) & 0x3f000000 ) >> 24)
+#define GET_RG_BT_IDACAI_TZ1_PGAG13 (((REG32(ADR_BT_DCOC_IDAC_REGISTER10)) & 0x0000003f ) >> 0)
+#define GET_RG_BT_IDACAQ_TZ1_PGAG13 (((REG32(ADR_BT_DCOC_IDAC_REGISTER10)) & 0x00003f00 ) >> 8)
+#define GET_RG_BT_IDACAI_TZ1_PGAG12 (((REG32(ADR_BT_DCOC_IDAC_REGISTER10)) & 0x003f0000 ) >> 16)
+#define GET_RG_BT_IDACAQ_TZ1_PGAG12 (((REG32(ADR_BT_DCOC_IDAC_REGISTER10)) & 0x3f000000 ) >> 24)
+#define GET_RG_BT_IDACAI_TZ1_PGAG11 (((REG32(ADR_BT_DCOC_IDAC_REGISTER11)) & 0x0000003f ) >> 0)
+#define GET_RG_BT_IDACAQ_TZ1_PGAG11 (((REG32(ADR_BT_DCOC_IDAC_REGISTER11)) & 0x00003f00 ) >> 8)
+#define GET_RG_BT_IDACAI_TZ1_PGAG10 (((REG32(ADR_BT_DCOC_IDAC_REGISTER11)) & 0x003f0000 ) >> 16)
+#define GET_RG_BT_IDACAQ_TZ1_PGAG10 (((REG32(ADR_BT_DCOC_IDAC_REGISTER11)) & 0x3f000000 ) >> 24)
+#define GET_RG_BT_IDACAI_TZ1_PGAG9 (((REG32(ADR_BT_DCOC_IDAC_REGISTER12)) & 0x0000003f ) >> 0)
+#define GET_RG_BT_IDACAQ_TZ1_PGAG9 (((REG32(ADR_BT_DCOC_IDAC_REGISTER12)) & 0x00003f00 ) >> 8)
+#define GET_RG_BT_IDACAI_TZ1_PGAG8 (((REG32(ADR_BT_DCOC_IDAC_REGISTER12)) & 0x003f0000 ) >> 16)
+#define GET_RG_BT_IDACAQ_TZ1_PGAG8 (((REG32(ADR_BT_DCOC_IDAC_REGISTER12)) & 0x3f000000 ) >> 24)
+#define GET_RG_BT_IDACAI_TZ1_PGAG7 (((REG32(ADR_BT_DCOC_IDAC_REGISTER13)) & 0x0000003f ) >> 0)
+#define GET_RG_BT_IDACAQ_TZ1_PGAG7 (((REG32(ADR_BT_DCOC_IDAC_REGISTER13)) & 0x00003f00 ) >> 8)
+#define GET_RG_BT_IDACAI_TZ1_PGAG6 (((REG32(ADR_BT_DCOC_IDAC_REGISTER13)) & 0x003f0000 ) >> 16)
+#define GET_RG_BT_IDACAQ_TZ1_PGAG6 (((REG32(ADR_BT_DCOC_IDAC_REGISTER13)) & 0x3f000000 ) >> 24)
+#define GET_RG_BT_IDACAI_TZ1_PGAG5 (((REG32(ADR_BT_DCOC_IDAC_REGISTER14)) & 0x0000003f ) >> 0)
+#define GET_RG_BT_IDACAQ_TZ1_PGAG5 (((REG32(ADR_BT_DCOC_IDAC_REGISTER14)) & 0x00003f00 ) >> 8)
+#define GET_RG_BT_IDACAI_TZ1_PGAG4 (((REG32(ADR_BT_DCOC_IDAC_REGISTER14)) & 0x003f0000 ) >> 16)
+#define GET_RG_BT_IDACAQ_TZ1_PGAG4 (((REG32(ADR_BT_DCOC_IDAC_REGISTER14)) & 0x3f000000 ) >> 24)
+#define GET_RG_BT_IDACAI_TZ1_PGAG3 (((REG32(ADR_BT_DCOC_IDAC_REGISTER15)) & 0x0000003f ) >> 0)
+#define GET_RG_BT_IDACAQ_TZ1_PGAG3 (((REG32(ADR_BT_DCOC_IDAC_REGISTER15)) & 0x00003f00 ) >> 8)
+#define GET_RG_BT_IDACAI_TZ1_PGAG2 (((REG32(ADR_BT_DCOC_IDAC_REGISTER15)) & 0x003f0000 ) >> 16)
+#define GET_RG_BT_IDACAQ_TZ1_PGAG2 (((REG32(ADR_BT_DCOC_IDAC_REGISTER15)) & 0x3f000000 ) >> 24)
+#define GET_RG_BT_IDACAI_TZ1_PGAG1 (((REG32(ADR_BT_DCOC_IDAC_REGISTER16)) & 0x0000003f ) >> 0)
+#define GET_RG_BT_IDACAQ_TZ1_PGAG1 (((REG32(ADR_BT_DCOC_IDAC_REGISTER16)) & 0x00003f00 ) >> 8)
+#define GET_RG_BT_IDACAI_TZ1_PGAG0 (((REG32(ADR_BT_DCOC_IDAC_REGISTER16)) & 0x003f0000 ) >> 16)
+#define GET_RG_BT_IDACAQ_TZ1_PGAG0 (((REG32(ADR_BT_DCOC_IDAC_REGISTER16)) & 0x3f000000 ) >> 24)
+#define GET_RG_SX_DELAY (((REG32(ADR_MODE_DECODER_TIMER_REGISTER1)) & 0x0000000f ) >> 0)
+#define GET_RG_TXDAC_DELAY (((REG32(ADR_MODE_DECODER_TIMER_REGISTER1)) & 0x000000f0 ) >> 4)
+#define GET_RG_TXRF_DELAY (((REG32(ADR_MODE_DECODER_TIMER_REGISTER1)) & 0x00000f00 ) >> 8)
+#define GET_RG_TXPA_DELAY (((REG32(ADR_MODE_DECODER_TIMER_REGISTER1)) & 0x0000f000 ) >> 12)
+#define GET_RG_RXRF_DELAY (((REG32(ADR_MODE_DECODER_TIMER_REGISTER1)) & 0x000f0000 ) >> 16)
+#define GET_RG_TXBTPA_DELAY (((REG32(ADR_MODE_DECODER_TIMER_REGISTER1)) & 0x00f00000 ) >> 20)
+#define GET_RG_TXDAC_T2R_DELAY (((REG32(ADR_WIFI_T2R_TIMER_REGISTER)) & 0x0000001f ) >> 0)
+#define GET_RG_TXRF_T2R_DELAY (((REG32(ADR_WIFI_T2R_TIMER_REGISTER)) & 0x00001f00 ) >> 8)
+#define GET_RG_TXPA_T2R_DELAY (((REG32(ADR_WIFI_T2R_TIMER_REGISTER)) & 0x001f0000 ) >> 16)
+#define GET_RG_RXRF_T2R_DELAY (((REG32(ADR_WIFI_T2R_TIMER_REGISTER)) & 0x1f000000 ) >> 24)
+#define GET_RG_TXDAC_R2T_DELAY (((REG32(ADR_WIFI_R2T_TIMER_REGISTER)) & 0x0000001f ) >> 0)
+#define GET_RG_TXRF_R2T_DELAY (((REG32(ADR_WIFI_R2T_TIMER_REGISTER)) & 0x00001f00 ) >> 8)
+#define GET_RG_TXPA_R2T_DELAY (((REG32(ADR_WIFI_R2T_TIMER_REGISTER)) & 0x001f0000 ) >> 16)
+#define GET_RG_RXRF_R2T_DELAY (((REG32(ADR_WIFI_R2T_TIMER_REGISTER)) & 0x1f000000 ) >> 24)
+#define GET_RG_WF_RX_DCCAL_DELAY (((REG32(ADR_CALIBRATION_TIMER_REGISTER)) & 0x00000007 ) >> 0)
+#define GET_RG_BT_RX_DCCAL_DELAY (((REG32(ADR_CALIBRATION_TIMER_REGISTER)) & 0x00000070 ) >> 4)
+#define GET_RG_RX_RCCAL_DELAY (((REG32(ADR_CALIBRATION_TIMER_REGISTER)) & 0x00000700 ) >> 8)
+#define GET_RG_TX_DCCAL_DELAY (((REG32(ADR_CALIBRATION_TIMER_REGISTER)) & 0x00007000 ) >> 12)
+#define GET_RG_TX_IQCAL_DELAY (((REG32(ADR_CALIBRATION_TIMER_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_RX_IQCAL_DELAY (((REG32(ADR_CALIBRATION_TIMER_REGISTER)) & 0x00700000 ) >> 20)
+#define GET_RG_RX_N_RCCAL_DELAY (((REG32(ADR_CALIBRATION_TIMER_REGISTER)) & 0x07000000 ) >> 24)
+#define GET_RG_PGAG_RCCAL (((REG32(ADR_CALIBRATION_GAIN_REGISTER0)) & 0x0000000f ) >> 0)
+#define GET_RG_PGAG_TXCAL (((REG32(ADR_CALIBRATION_GAIN_REGISTER0)) & 0x000000f0 ) >> 4)
+#define GET_RG_TX_GAIN_TXCAL (((REG32(ADR_CALIBRATION_GAIN_REGISTER0)) & 0x00007f00 ) >> 8)
+#define GET_RG_RFG_RXIQCAL (((REG32(ADR_CALIBRATION_GAIN_REGISTER0)) & 0x00030000 ) >> 16)
+#define GET_RG_PGAG_RXIQCAL (((REG32(ADR_CALIBRATION_GAIN_REGISTER0)) & 0x003c0000 ) >> 18)
+#define GET_RG_TX_GAIN_RXIQCAL (((REG32(ADR_CALIBRATION_GAIN_REGISTER0)) & 0x1fc00000 ) >> 22)
+#define GET_RG_RFG_DPDCAL (((REG32(ADR_CALIBRATION_GAIN_REGISTER1)) & 0x00000003 ) >> 0)
+#define GET_RG_PGAG_DPDCAL (((REG32(ADR_CALIBRATION_GAIN_REGISTER1)) & 0x0000003c ) >> 2)
+#define GET_RG_TX_GAIN_DPDCAL (((REG32(ADR_CALIBRATION_GAIN_REGISTER1)) & 0x00001fc0 ) >> 6)
+#define GET_RG_IOT_ADC_CLKSEL (((REG32(ADR_CALIBRATION_GAIN_REGISTER1)) & 0x00010000 ) >> 16)
+#define GET_RG_IOT_ADC_DNLEN (((REG32(ADR_CALIBRATION_GAIN_REGISTER1)) & 0x00020000 ) >> 17)
+#define GET_RG_IOT_ADC_METAEN (((REG32(ADR_CALIBRATION_GAIN_REGISTER1)) & 0x00040000 ) >> 18)
+#define GET_RG_IOT_ADC_TFLAG (((REG32(ADR_CALIBRATION_GAIN_REGISTER1)) & 0x00080000 ) >> 19)
+#define GET_RG_IOT_ADC_ICMP (((REG32(ADR_CALIBRATION_GAIN_REGISTER1)) & 0x00300000 ) >> 20)
+#define GET_RG_IOT_ADC_VCMI (((REG32(ADR_CALIBRATION_GAIN_REGISTER1)) & 0x00c00000 ) >> 22)
+#define GET_RG_IOT_ADC_CLOAD (((REG32(ADR_CALIBRATION_GAIN_REGISTER1)) & 0x03000000 ) >> 24)
+#define GET_RG_IOT_ADC_CLK_DIV (((REG32(ADR_CALIBRATION_GAIN_REGISTER1)) & 0x0c000000 ) >> 26)
+#define GET_RG_IOT_ADC_CLK_SH_DUTY (((REG32(ADR_CALIBRATION_GAIN_REGISTER1)) & 0x10000000 ) >> 28)
+#define GET_RG_IOT_ADC_VSEN_SEL (((REG32(ADR_CALIBRATION_GAIN_REGISTER1)) & 0x60000000 ) >> 29)
+#define GET_DB_AD_ADC_I_OUT (((REG32(ADR_READ_ONLY_FLAGS_ADC)) & 0x000003ff ) >> 0)
+#define GET_DB_AD_ADC_Q_OUT (((REG32(ADR_READ_ONLY_FLAGS_ADC)) & 0x000ffc00 ) >> 10)
+#define GET_DB_AD_RX_RSSIADC (((REG32(ADR_READ_ONLY_FLAGS_ADC)) & 0x00f00000 ) >> 20)
+#define GET_DB_DA_SARADC_BIT (((REG32(ADR_READ_ONLY_FLAGS_ADC)) & 0x3f000000 ) >> 24)
+#define GET_SAR_ADC_FSM_RDY (((REG32(ADR_READ_ONLY_FLAGS_ADC)) & 0x40000000 ) >> 30)
+#define GET_DB_DA_SX_SUB_SEL (((REG32(ADR_READ_ONLY_FLAGS_SX_2_4GB_1)) & 0x000000ff ) >> 0)
+#define GET_DB_DA_SX_VCO_ISEL (((REG32(ADR_READ_ONLY_FLAGS_SX_2_4GB_1)) & 0x00000f00 ) >> 8)
+#define GET_DB_VO_AAC_COMPOUT (((REG32(ADR_READ_ONLY_FLAGS_SX_2_4GB_1)) & 0x00001000 ) >> 12)
+#define GET_DB_SX_TTL_VT_DET (((REG32(ADR_READ_ONLY_FLAGS_SX_2_4GB_1)) & 0x0000c000 ) >> 14)
+#define GET_DB_AD_DP_VT_MON_Q (((REG32(ADR_READ_ONLY_FLAGS_SX_2_4GB_1)) & 0x00030000 ) >> 16)
+#define GET_DB_AD_IOT_ADC_OUT (((REG32(ADR_READ_ONLY_FLAGS_SX_2_4GB_1)) & 0x3ff00000 ) >> 20)
+#define GET_DB_SX_SBCAL_NCOUNT (((REG32(ADR_READ_ONLY_FLAGS_SX_2_4GB_2)) & 0x0000ffff ) >> 0)
+#define GET_DB_SX_SBCAL_NTARGET (((REG32(ADR_READ_ONLY_FLAGS_SX_2_4GB_2)) & 0xffff0000 ) >> 16)
+#define GET_RG_5G_TX_TRSW_MANUAL (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_5G_EN_TX_TRSW (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_RG_5G_RX_LNA_MANUAL (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_RG_5G_EN_RX_LNA (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_RG_5G_RX_MIXER_MANUAL (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_RG_5G_EN_RX_MIXER (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000020 ) >> 5)
+#define GET_RG_5G_RX_DIV2_MANUAL (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000040 ) >> 6)
+#define GET_RG_5G_EN_RX_DIV2 (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000080 ) >> 7)
+#define GET_RG_5G_RX_LOBUF_MANUAL (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000100 ) >> 8)
+#define GET_RG_5G_EN_RX_LOBUF (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000200 ) >> 9)
+#define GET_RG_5G_RX_TZ_MANUAL (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000400 ) >> 10)
+#define GET_RG_5G_EN_RX_TZ (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_RG_5G_TX_PA_MANUAL (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00001000 ) >> 12)
+#define GET_RG_5G_EN_TX_PA (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00002000 ) >> 13)
+#define GET_RG_5G_TX_MOD_MANUAL (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_RG_5G_EN_TX_MOD (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00008000 ) >> 15)
+#define GET_RG_5G_TX_DIV2_MANUAL (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00040000 ) >> 18)
+#define GET_RG_5G_EN_TX_DIV2 (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00080000 ) >> 19)
+#define GET_RG_5G_TX_DIV2_BUF_MANUAL (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00100000 ) >> 20)
+#define GET_RG_5G_EN_TX_DIV2_BUF (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00200000 ) >> 21)
+#define GET_RG_5G_RX_TZ_OUT_TRISTATE_MANUAL (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00400000 ) >> 22)
+#define GET_RG_5G_RX_TZ_OUT_TRISTATE (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00800000 ) >> 23)
+#define GET_RG_5G_TX_SELF_MIXER_MANUAL (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x01000000 ) >> 24)
+#define GET_RG_5G_EN_TX_SELF_MIXER (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x02000000 ) >> 25)
+#define GET_RG_5G_RX_IQCAL_MANUAL (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x04000000 ) >> 26)
+#define GET_RG_5G_EN_RX_IQCAL (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x08000000 ) >> 27)
+#define GET_RG_5G_TX_DPD_MANUAL (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x10000000 ) >> 28)
+#define GET_RG_5G_EN_TX_DPD (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x20000000 ) >> 29)
+#define GET_RG_5G_EN_TX_TSSI (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x40000000 ) >> 30)
+#define GET_RG_5G_LDO_LEVEL_RX_FE (((REG32(ADR_5G_LDO_REGISTER)) & 0x00000007 ) >> 0)
+#define GET_RG_5G_EN_LDO_RX_FE_BYP (((REG32(ADR_5G_LDO_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_RG_SX5GB_LDO_CP_LEVEL (((REG32(ADR_5G_LDO_REGISTER)) & 0x00000070 ) >> 4)
+#define GET_RG_EN_LDO_5G_CP_BYP (((REG32(ADR_5G_LDO_REGISTER)) & 0x00000080 ) >> 7)
+#define GET_RG_SX5GB_LDO_LO_LEVEL (((REG32(ADR_5G_LDO_REGISTER)) & 0x00000700 ) >> 8)
+#define GET_RG_EN_LDO_5G_LO_BYP (((REG32(ADR_5G_LDO_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_RG_SX5GB_LDO_VCO_LEVEL (((REG32(ADR_5G_LDO_REGISTER)) & 0x00007000 ) >> 12)
+#define GET_RG_SX5GB_LDO_DIV_LEVEL (((REG32(ADR_5G_LDO_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_EN_LDO_5G_DIV_BYP (((REG32(ADR_5G_LDO_REGISTER)) & 0x00080000 ) >> 19)
+#define GET_RG_5G_EN_LDO_RX_FE (((REG32(ADR_5G_LDO_REGISTER)) & 0x01000000 ) >> 24)
+#define GET_RG_5G_EN_IREF_RX (((REG32(ADR_5G_LDO_REGISTER)) & 0x02000000 ) >> 25)
+#define GET_RG_5G_EN_LDO_RX_FE_FC (((REG32(ADR_5G_LDO_REGISTER)) & 0x04000000 ) >> 26)
+#define GET_RG_5G_EN_LDO_RX_FE_IQUP (((REG32(ADR_5G_LDO_REGISTER)) & 0x08000000 ) >> 27)
+#define GET_RG_5G_RX_SCA_MANUAL (((REG32(ADR_5G_RX_REGISTER1)) & 0x00000001 ) >> 0)
+#define GET_RG_5G_RX_SCA_MA (((REG32(ADR_5G_RX_REGISTER1)) & 0x0000000e ) >> 1)
+#define GET_RG_5G_RX_SCA_LOAD (((REG32(ADR_5G_RX_REGISTER1)) & 0x00000070 ) >> 4)
+#define GET_RG_5G_RX_LNA_TRI_SEL (((REG32(ADR_5G_RX_REGISTER1)) & 0x00000300 ) >> 8)
+#define GET_RG_5G_RX_LNA_SETTLE (((REG32(ADR_5G_RX_REGISTER1)) & 0x00000c00 ) >> 10)
+#define GET_RG_5G_GM_BIAS (((REG32(ADR_5G_RX_REGISTER1)) & 0x00007000 ) >> 12)
+#define GET_RG_5G_RX_DIV2_BUF (((REG32(ADR_5G_RX_REGISTER1)) & 0x00030000 ) >> 16)
+#define GET_RG_5G_RX_DIV2_CML (((REG32(ADR_5G_RX_REGISTER1)) & 0x000c0000 ) >> 18)
+#define GET_RG_5G_RX_DIV_CMLISEL (((REG32(ADR_5G_RX_REGISTER1)) & 0x00300000 ) >> 20)
+#define GET_RG_5G_RX_DIV_PREBUFS2 (((REG32(ADR_5G_RX_REGISTER1)) & 0x00400000 ) >> 22)
+#define GET_RG_5G_RX_TZ_COURSE (((REG32(ADR_5G_RX_REGISTER1)) & 0x03000000 ) >> 24)
+#define GET_RG_5G_TX_DPDGM_BIAS (((REG32(ADR_5G_RX_REGISTER1)) & 0xf0000000 ) >> 28)
+#define GET_RG_5G_TX_DPD_DIV (((REG32(ADR_5G_RX_REGISTER2)) & 0x0000000f ) >> 0)
+#define GET_RG_5G_TX_TSSI_BIAS (((REG32(ADR_5G_RX_REGISTER2)) & 0x00000070 ) >> 4)
+#define GET_RG_5G_TX_TSSI_DIV (((REG32(ADR_5G_RX_REGISTER2)) & 0x00000700 ) >> 8)
+#define GET_RG_5G_TX_TSSI_TEST (((REG32(ADR_5G_RX_REGISTER2)) & 0x00003000 ) >> 12)
+#define GET_RG_5G_TX_TSSI_TESTMODE (((REG32(ADR_5G_RX_REGISTER2)) & 0x00004000 ) >> 14)
+#define GET_RG_5G_RX_ADC_ICMP (((REG32(ADR_5G_RX_REGISTER2)) & 0x00030000 ) >> 16)
+#define GET_RG_5G_RX_ADC_VCMI (((REG32(ADR_5G_RX_REGISTER2)) & 0x000c0000 ) >> 18)
+#define GET_RG_5G_RX_ADC_CLOAD (((REG32(ADR_5G_RX_REGISTER2)) & 0x00300000 ) >> 20)
+#define GET_RG_5G_RX_ADC_PSW (((REG32(ADR_5G_RX_REGISTER2)) & 0x00400000 ) >> 22)
+#define GET_RG_5G_RX_TZ_CMZ_C (((REG32(ADR_5G_RX_REGISTER2)) & 0x01800000 ) >> 23)
+#define GET_RG_5G_RX_TZ_CMZ_R (((REG32(ADR_5G_RX_REGISTER2)) & 0x06000000 ) >> 25)
+#define GET_RG_5G_TXPAPGA_MANUAL (((REG32(ADR_5G_TX_FE_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_5G_TXPGA_CAPSW (((REG32(ADR_5G_TX_FE_REGISTER)) & 0x0000000e ) >> 1)
+#define GET_RG_5G_PACELL_EN (((REG32(ADR_5G_TX_FE_REGISTER)) & 0x000000e0 ) >> 5)
+#define GET_RG_5G_PABIAS_CTRL (((REG32(ADR_5G_TX_FE_REGISTER)) & 0x00000f00 ) >> 8)
+#define GET_RG_5G_TX_PAFB_EN (((REG32(ADR_5G_TX_FE_REGISTER)) & 0x00001000 ) >> 12)
+#define GET_RG_5G_TX_PA1_VCAS (((REG32(ADR_5G_TX_FE_REGISTER)) & 0x0000e000 ) >> 13)
+#define GET_RG_5G_TX_PA2_VCAS (((REG32(ADR_5G_TX_FE_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_5G_PABIAS_2X (((REG32(ADR_5G_TX_FE_REGISTER)) & 0x00080000 ) >> 19)
+#define GET_RG_5G_TX_PA3_VCAS (((REG32(ADR_5G_TX_FE_REGISTER)) & 0x00700000 ) >> 20)
+#define GET_RG_5G_TX_DIV_PREBUFS2 (((REG32(ADR_5G_TX_FE_REGISTER)) & 0x00800000 ) >> 23)
+#define GET_RG_5G_TX_DIV_CMLISEL (((REG32(ADR_5G_TX_FE_REGISTER)) & 0x03000000 ) >> 24)
+#define GET_RG_5G_TX_DIV_CMLVSEL (((REG32(ADR_5G_TX_FE_REGISTER)) & 0x0c000000 ) >> 26)
+#define GET_RG_5G_TX_DIV_VSET (((REG32(ADR_5G_TX_FE_REGISTER)) & 0x30000000 ) >> 28)
+#define GET_RG_5G_TX_LOBUF_VSET (((REG32(ADR_5G_TX_FE_REGISTER)) & 0xc0000000 ) >> 30)
+#define GET_RG_5G_TXPGA_MAIN (((REG32(ADR_5G_TX_REGISTER)) & 0x0000003f ) >> 0)
+#define GET_RG_5G_TXPGA_STEER (((REG32(ADR_5G_TX_REGISTER)) & 0x00000fc0 ) >> 6)
+#define GET_RG_5G_TXMOD_GMCELL (((REG32(ADR_5G_TX_REGISTER)) & 0x00003000 ) >> 12)
+#define GET_RG_5G_TXLPF_GMCELL (((REG32(ADR_5G_TX_REGISTER)) & 0x0000c000 ) >> 14)
+#define GET_RG_5G_TX_GAIN_OFFSET (((REG32(ADR_5G_TX_REGISTER)) & 0x000f0000 ) >> 16)
+#define GET_RG_5G_TX_GAIN (((REG32(ADR_5G_TX_REGISTER)) & 0x07f00000 ) >> 20)
+#define GET_RG_5G_TX_ADDGMCELL (((REG32(ADR_5G_TX_REGISTER)) & 0x08000000 ) >> 27)
+#define GET_RG_5G_TXMOD_LOBIAS (((REG32(ADR_5G_TX_REGISTER)) & 0x30000000 ) >> 28)
+#define GET_RG_5G_TXMOD_PGABIAS (((REG32(ADR_5G_TX_REGISTER)) & 0xc0000000 ) >> 30)
+#define GET_RG_5G_RX_HG_LNA_GC (((REG32(ADR_5G_RX_FE_HG_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_5G_RX_HG_TZ_GC (((REG32(ADR_5G_RX_FE_HG_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_5G_RX_HG_LNAHGN_BIAS (((REG32(ADR_5G_RX_FE_HG_REGISTER)) & 0x000000f0 ) >> 4)
+#define GET_RG_5G_RX_HG_LNAHGP_BIAS (((REG32(ADR_5G_RX_FE_HG_REGISTER)) & 0x00000f00 ) >> 8)
+#define GET_RG_5G_RX_HG_LNALG_BIAS (((REG32(ADR_5G_RX_FE_HG_REGISTER)) & 0x0000f000 ) >> 12)
+#define GET_RG_5G_RX_HG_TZ_CAP (((REG32(ADR_5G_RX_FE_HG_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_5G_RX_HG_SQDC (((REG32(ADR_5G_RX_FE_HG_REGISTER)) & 0x00380000 ) >> 19)
+#define GET_RG_5G_RX_HG_DIV2_CORE (((REG32(ADR_5G_RX_FE_HG_REGISTER)) & 0x00c00000 ) >> 22)
+#define GET_RG_5G_RX_HG_TZ_GC_BOOST (((REG32(ADR_5G_RX_FE_HG_REGISTER)) & 0x03000000 ) >> 24)
+#define GET_RG_5G_RX_HG_TZI (((REG32(ADR_5G_RX_FE_HG_REGISTER)) & 0x1c000000 ) >> 26)
+#define GET_RG_5G_RX_HG_TZ_VCM (((REG32(ADR_5G_RX_FE_HG_REGISTER)) & 0xe0000000 ) >> 29)
+#define GET_RG_5G_RX_MG_LNA_GC (((REG32(ADR_5G_RX_FE_MG_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_5G_RX_MG_TZ_GC (((REG32(ADR_5G_RX_FE_MG_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_5G_RX_MG_LNAHGN_BIAS (((REG32(ADR_5G_RX_FE_MG_REGISTER)) & 0x000000f0 ) >> 4)
+#define GET_RG_5G_RX_MG_LNAHGP_BIAS (((REG32(ADR_5G_RX_FE_MG_REGISTER)) & 0x00000f00 ) >> 8)
+#define GET_RG_5G_RX_MG_LNALG_BIAS (((REG32(ADR_5G_RX_FE_MG_REGISTER)) & 0x0000f000 ) >> 12)
+#define GET_RG_5G_RX_MG_TZ_CAP (((REG32(ADR_5G_RX_FE_MG_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_5G_RX_MG_SQDC (((REG32(ADR_5G_RX_FE_MG_REGISTER)) & 0x00380000 ) >> 19)
+#define GET_RG_5G_RX_MG_DIV2_CORE (((REG32(ADR_5G_RX_FE_MG_REGISTER)) & 0x00c00000 ) >> 22)
+#define GET_RG_5G_RX_MG_TZ_GC_BOOST (((REG32(ADR_5G_RX_FE_MG_REGISTER)) & 0x03000000 ) >> 24)
+#define GET_RG_5G_RX_MG_TZI (((REG32(ADR_5G_RX_FE_MG_REGISTER)) & 0x1c000000 ) >> 26)
+#define GET_RG_5G_RX_MG_TZ_VCM (((REG32(ADR_5G_RX_FE_MG_REGISTER)) & 0xe0000000 ) >> 29)
+#define GET_RG_5G_RX_LG_LNA_GC (((REG32(ADR_5G_RX_FE_LG_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_5G_RX_LG_TZ_GC (((REG32(ADR_5G_RX_FE_LG_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_5G_RX_LG_LNAHGN_BIAS (((REG32(ADR_5G_RX_FE_LG_REGISTER)) & 0x000000f0 ) >> 4)
+#define GET_RG_5G_RX_LG_LNAHGP_BIAS (((REG32(ADR_5G_RX_FE_LG_REGISTER)) & 0x00000f00 ) >> 8)
+#define GET_RG_5G_RX_LG_LNALG_BIAS (((REG32(ADR_5G_RX_FE_LG_REGISTER)) & 0x0000f000 ) >> 12)
+#define GET_RG_5G_RX_LG_TZ_CAP (((REG32(ADR_5G_RX_FE_LG_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_5G_RX_LG_SQDC (((REG32(ADR_5G_RX_FE_LG_REGISTER)) & 0x00380000 ) >> 19)
+#define GET_RG_5G_RX_LG_DIV2_CORE (((REG32(ADR_5G_RX_FE_LG_REGISTER)) & 0x00c00000 ) >> 22)
+#define GET_RG_5G_RX_LG_TZ_GC_BOOST (((REG32(ADR_5G_RX_FE_LG_REGISTER)) & 0x03000000 ) >> 24)
+#define GET_RG_5G_RX_LG_TZI (((REG32(ADR_5G_RX_FE_LG_REGISTER)) & 0x1c000000 ) >> 26)
+#define GET_RG_5G_RX_LG_TZ_VCM (((REG32(ADR_5G_RX_FE_LG_REGISTER)) & 0xe0000000 ) >> 29)
+#define GET_RG_5G_RX_ULG_LNA_GC (((REG32(ADR_5G_RX_FE_ULG_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_5G_RX_ULG_TZ_GC (((REG32(ADR_5G_RX_FE_ULG_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_5G_RX_ULG_LNAHGN_BIAS (((REG32(ADR_5G_RX_FE_ULG_REGISTER)) & 0x000000f0 ) >> 4)
+#define GET_RG_5G_RX_ULG_LNAHGP_BIAS (((REG32(ADR_5G_RX_FE_ULG_REGISTER)) & 0x00000f00 ) >> 8)
+#define GET_RG_5G_RX_ULG_LNALG_BIAS (((REG32(ADR_5G_RX_FE_ULG_REGISTER)) & 0x0000f000 ) >> 12)
+#define GET_RG_5G_RX_ULG_TZ_CAP (((REG32(ADR_5G_RX_FE_ULG_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_5G_RX_ULG_SQDC (((REG32(ADR_5G_RX_FE_ULG_REGISTER)) & 0x00380000 ) >> 19)
+#define GET_RG_5G_RX_ULG_DIV2_CORE (((REG32(ADR_5G_RX_FE_ULG_REGISTER)) & 0x00c00000 ) >> 22)
+#define GET_RG_5G_RX_ULG_TZ_GC_BOOST (((REG32(ADR_5G_RX_FE_ULG_REGISTER)) & 0x03000000 ) >> 24)
+#define GET_RG_5G_RX_ULG_TZI (((REG32(ADR_5G_RX_FE_ULG_REGISTER)) & 0x1c000000 ) >> 26)
+#define GET_RG_5G_RX_ULG_TZ_VCM (((REG32(ADR_5G_RX_FE_ULG_REGISTER)) & 0xe0000000 ) >> 29)
+#define GET_RG_5G_TX_DACI1ST (((REG32(ADR_5G_TX_DAC_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_5G_TX_DACLPF_ICOARSE (((REG32(ADR_5G_TX_DAC_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_5G_TX_DACLPF_IFINE (((REG32(ADR_5G_TX_DAC_REGISTER)) & 0x00000030 ) >> 4)
+#define GET_RG_5G_TX_DACLPF_VCM (((REG32(ADR_5G_TX_DAC_REGISTER)) & 0x000000c0 ) >> 6)
+#define GET_RG_5G_TX_DAC_IBIAS (((REG32(ADR_5G_TX_DAC_REGISTER)) & 0x00000300 ) >> 8)
+#define GET_RG_5G_TX_DAC_IATTN (((REG32(ADR_5G_TX_DAC_REGISTER)) & 0x00000400 ) >> 10)
+#define GET_RG_5G_TXLPF_BOOSTI (((REG32(ADR_5G_TX_DAC_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_RG_5G_TX_DAC_RCAL (((REG32(ADR_5G_TX_DAC_REGISTER)) & 0x00003000 ) >> 12)
+#define GET_RG_5G_TX_DAC_CKEDGE_SEL (((REG32(ADR_5G_TX_DAC_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_RG_5G_TX_DAC_OS (((REG32(ADR_5G_TX_DAC_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_5G_TX_DAC_IOFFSET (((REG32(ADR_5G_TX_DAC_REGISTER)) & 0x00f00000 ) >> 20)
+#define GET_RG_5G_TX_DAC_QOFFSET (((REG32(ADR_5G_TX_DAC_REGISTER)) & 0x0f000000 ) >> 24)
+#define GET_RG_SX5GB_RFCTRL_F (((REG32(ADR_SX_5GB_FRACTIONAL_AND_INTEGER_8BITS)) & 0x00ffffff ) >> 0)
+#define GET_RG_SX5GB_RFCTRL_CH_7_0 (((REG32(ADR_SX_5GB_FRACTIONAL_AND_INTEGER_8BITS)) & 0xff000000 ) >> 24)
+#define GET_RG_SX5GB_RFCTRL_CH_10_8 (((REG32(ADR_SX_5GB_REGISTER_INT3BIT___CH_TABLE)) & 0x00000007 ) >> 0)
+#define GET_RG_SX5GB_RFCH_MAP_EN (((REG32(ADR_SX_5GB_REGISTER_INT3BIT___CH_TABLE)) & 0x00000010 ) >> 4)
+#define GET_RG_SX5GB_LO_TIMES (((REG32(ADR_SX_5GB_REGISTER_INT3BIT___CH_TABLE)) & 0x00000020 ) >> 5)
+#define GET_RG_SX5GB_CHANNEL (((REG32(ADR_SX_5GB_REGISTER_INT3BIT___CH_TABLE)) & 0x0000ff00 ) >> 8)
+#define GET_RG_SX_5GB_EN_MAN (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000001 ) >> 0)
+#define GET_RG_SX_5GB_EN (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000002 ) >> 1)
+#define GET_RG_EN_SX5GB_CP_MAN (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000004 ) >> 2)
+#define GET_RG_EN_SX5GB_CP (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000008 ) >> 3)
+#define GET_RG_EN_SX5GB_DIV_MAN (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000010 ) >> 4)
+#define GET_RG_EN_SX5GB_DIV (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000020 ) >> 5)
+#define GET_RG_EN_SX5GB_VCO_MAN (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000040 ) >> 6)
+#define GET_RG_EN_SX5GB_VCO (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000080 ) >> 7)
+#define GET_RG_SX5GB_PFD_RST_MAN (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000100 ) >> 8)
+#define GET_RG_SX5GB_PFD_RST (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000200 ) >> 9)
+#define GET_RG_SX5GB_UOP_MAN (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000400 ) >> 10)
+#define GET_RG_SX5GB_UOP_EN (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000800 ) >> 11)
+#define GET_RG_EN_SX5GB_HSDIV_MAN (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00001000 ) >> 12)
+#define GET_RG_EN_SX5GB_HSDIV (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00002000 ) >> 13)
+#define GET_RG_EN_HSDIV_OBF_SX_MAN (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00004000 ) >> 14)
+#define GET_RG_EN_HSDIV_OBF_SX (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00008000 ) >> 15)
+#define GET_RG_EN_HSDIV_OBF_MX_MAN (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00010000 ) >> 16)
+#define GET_RG_EN_HSDIV_OBF_MX (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00020000 ) >> 17)
+#define GET_RG_EN_SX_MIX_MAN (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00040000 ) >> 18)
+#define GET_RG_EN_SX_MIX (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00080000 ) >> 19)
+#define GET_RG_EN_SX_REP_MAN (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00100000 ) >> 20)
+#define GET_RG_EN_SX_REP (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00200000 ) >> 21)
+#define GET_RG_SX5GB_SBCAL_DIS (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00400000 ) >> 22)
+#define GET_RG_SX5GB_SBCAL_2ND_DIS (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00800000 ) >> 23)
+#define GET_RG_SX5GB_SBCAL_AW (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x01000000 ) >> 24)
+#define GET_RG_SX5GB_VOAAC_DIS (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x02000000 ) >> 25)
+#define GET_RG_SX5GB_MIXAAC_DIS (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x04000000 ) >> 26)
+#define GET_RG_SX5GB_REPAAC_DIS (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x08000000 ) >> 27)
+#define GET_RG_SX5GB_TTL_DIS (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x10000000 ) >> 28)
+#define GET_RG_SX5GB_CAL_INIT (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0xe0000000 ) >> 29)
+#define GET_RG_EN_SX5GB_LDO_MAN (((REG32(ADR_SX_5GB_LDO_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_EN_LDO_5G_CP (((REG32(ADR_SX_5GB_LDO_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_RG_EN_LDO_5G_DIV (((REG32(ADR_SX_5GB_LDO_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_RG_EN_LDO_5G_LO (((REG32(ADR_SX_5GB_LDO_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_RG_EN_LDO_5G_VCO (((REG32(ADR_SX_5GB_LDO_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_RG_EN_SXMIX_INBF_MAN (((REG32(ADR_SX_5GB_LDO_REGISTER)) & 0x00000040 ) >> 6)
+#define GET_RG_EN_SXMIX_INBF (((REG32(ADR_SX_5GB_LDO_REGISTER)) & 0x00000080 ) >> 7)
+#define GET_RG_EN_LDO_5G_VCO_PSW (((REG32(ADR_SX_5GB_LDO_REGISTER)) & 0x00000200 ) >> 9)
+#define GET_RG_EN_LDO_5G_VCO_VDD33 (((REG32(ADR_SX_5GB_LDO_REGISTER)) & 0x00000400 ) >> 10)
+#define GET_RG_EN_LDO_5G_CP_IQUP (((REG32(ADR_SX_5GB_LDO_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_RG_EN_LDO_5G_DIV_IQUP (((REG32(ADR_SX_5GB_LDO_REGISTER)) & 0x00001000 ) >> 12)
+#define GET_RG_EN_LDO_5G_LO_IQUP (((REG32(ADR_SX_5GB_LDO_REGISTER)) & 0x00002000 ) >> 13)
+#define GET_RG_EN_LDO_5G_VCO_IQUP (((REG32(ADR_SX_5GB_LDO_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_RG_SX5GB_LDO_FCOFFT (((REG32(ADR_SX_5GB_LDO_REGISTER)) & 0x00380000 ) >> 19)
+#define GET_RG_LDO_5G_CP_FC_MAN (((REG32(ADR_SX_5GB_LDO_REGISTER)) & 0x00400000 ) >> 22)
+#define GET_RG_LDO_5G_CP_FC (((REG32(ADR_SX_5GB_LDO_REGISTER)) & 0x00800000 ) >> 23)
+#define GET_RG_LDO_5G_DIV_FC_MAN (((REG32(ADR_SX_5GB_LDO_REGISTER)) & 0x01000000 ) >> 24)
+#define GET_RG_LDO_5G_DIV_FC (((REG32(ADR_SX_5GB_LDO_REGISTER)) & 0x02000000 ) >> 25)
+#define GET_RG_LDO_5G_LO_FC_MAN (((REG32(ADR_SX_5GB_LDO_REGISTER)) & 0x04000000 ) >> 26)
+#define GET_RG_LDO_5G_LO_FC (((REG32(ADR_SX_5GB_LDO_REGISTER)) & 0x08000000 ) >> 27)
+#define GET_RG_LDO_5G_VCO_FC_MAN (((REG32(ADR_SX_5GB_LDO_REGISTER)) & 0x10000000 ) >> 28)
+#define GET_RG_LDO_5G_VCO_FC (((REG32(ADR_SX_5GB_LDO_REGISTER)) & 0x20000000 ) >> 29)
+#define GET_RG_LDO_5G_VCO_RCF (((REG32(ADR_SX_5GB_LDO_REGISTER)) & 0xc0000000 ) >> 30)
+#define GET_RG_SX5GB_CP_ISEL (((REG32(ADR_SX_5GB_PFD_CHP_)) & 0x0000000f ) >> 0)
+#define GET_RG_SX5GB_CP_ISEL50U (((REG32(ADR_SX_5GB_PFD_CHP_)) & 0x00000010 ) >> 4)
+#define GET_RG_SX5GB_CP_KP_DOUB (((REG32(ADR_SX_5GB_PFD_CHP_)) & 0x00000020 ) >> 5)
+#define GET_RG_SX5GB_CP_IOST_POL (((REG32(ADR_SX_5GB_PFD_CHP_)) & 0x00000080 ) >> 7)
+#define GET_RG_SX5GB_CP_IOST (((REG32(ADR_SX_5GB_PFD_CHP_)) & 0x00000700 ) >> 8)
+#define GET_RG_SX5GB_PFD_SEL (((REG32(ADR_SX_5GB_PFD_CHP_)) & 0x00001000 ) >> 12)
+#define GET_RG_SX5GB_PFD_SET (((REG32(ADR_SX_5GB_PFD_CHP_)) & 0x00002000 ) >> 13)
+#define GET_RG_SX5GB_PFD_SET1 (((REG32(ADR_SX_5GB_PFD_CHP_)) & 0x00004000 ) >> 14)
+#define GET_RG_SX5GB_PFD_SET2 (((REG32(ADR_SX_5GB_PFD_CHP_)) & 0x00008000 ) >> 15)
+#define GET_RG_SX5GB_PFD_TRUP (((REG32(ADR_SX_5GB_PFD_CHP_)) & 0x00010000 ) >> 16)
+#define GET_RG_SX5GB_PFD_TRDN (((REG32(ADR_SX_5GB_PFD_CHP_)) & 0x00020000 ) >> 17)
+#define GET_RG_SX5GB_PFD_TLSEL (((REG32(ADR_SX_5GB_PFD_CHP_)) & 0x00040000 ) >> 18)
+#define GET_RG_SX5GB_PFD_REF_EDGE (((REG32(ADR_SX_5GB_PFD_CHP_)) & 0x00080000 ) >> 19)
+#define GET_RG_SX5GB_PFD_DIV_EDGE (((REG32(ADR_SX_5GB_PFD_CHP_)) & 0x00100000 ) >> 20)
+#define GET_RG_SX5GB_LPF_C1 (((REG32(ADR_SX_5GB_LPF_TTL)) & 0x0000000f ) >> 0)
+#define GET_RG_SX5GB_LPF_C2 (((REG32(ADR_SX_5GB_LPF_TTL)) & 0x000000f0 ) >> 4)
+#define GET_RG_SX5GB_LPF_C3 (((REG32(ADR_SX_5GB_LPF_TTL)) & 0x00000100 ) >> 8)
+#define GET_RG_SX5GB_LPF_R2 (((REG32(ADR_SX_5GB_LPF_TTL)) & 0x00001e00 ) >> 9)
+#define GET_RG_SX5GB_LPF_R3 (((REG32(ADR_SX_5GB_LPF_TTL)) & 0x0000e000 ) >> 13)
+#define GET_RG_SX5GB_TTL_INIT (((REG32(ADR_SX_5GB_LPF_TTL)) & 0x00030000 ) >> 16)
+#define GET_RG_SX5GB_TTL_FPT (((REG32(ADR_SX_5GB_LPF_TTL)) & 0x000c0000 ) >> 18)
+#define GET_RG_SX5GB_TTL_CPT (((REG32(ADR_SX_5GB_LPF_TTL)) & 0x00300000 ) >> 20)
+#define GET_RG_SX5GB_TTL_ACCUM (((REG32(ADR_SX_5GB_LPF_TTL)) & 0x00c00000 ) >> 22)
+#define GET_RG_SX5GB_TTL_SUB (((REG32(ADR_SX_5GB_LPF_TTL)) & 0x03000000 ) >> 24)
+#define GET_RG_SX5GB_TTL_SUB_INV (((REG32(ADR_SX_5GB_LPF_TTL)) & 0x04000000 ) >> 26)
+#define GET_RG_SX5GB_TTL_VH (((REG32(ADR_SX_5GB_LPF_TTL)) & 0x18000000 ) >> 27)
+#define GET_RG_SX5GB_TTL_VL (((REG32(ADR_SX_5GB_LPF_TTL)) & 0x60000000 ) >> 29)
+#define GET_RG_SX5GB_LPF_VTUNE_TEST (((REG32(ADR_SX_5GB_LPF_TTL)) & 0x80000000 ) >> 31)
+#define GET_RG_SX5GB_VCO_ISEL_MAN (((REG32(ADR_SX_5GB_VCO_LOGEN)) & 0x00000001 ) >> 0)
+#define GET_RG_SX5GB_VCO_ISEL (((REG32(ADR_SX_5GB_VCO_LOGEN)) & 0x0000001e ) >> 1)
+#define GET_RG_SX5GB_VCO_VCCBSEL (((REG32(ADR_SX_5GB_VCO_LOGEN)) & 0x000001c0 ) >> 6)
+#define GET_RG_SX5GB_VCO_KVDOUB (((REG32(ADR_SX_5GB_VCO_LOGEN)) & 0x00000200 ) >> 9)
+#define GET_RG_SX5GB_VCO_VARBSEL (((REG32(ADR_SX_5GB_VCO_LOGEN)) & 0x00001800 ) >> 11)
+#define GET_RG_SX5GB_VCO_RTAIL_SHIFT (((REG32(ADR_SX_5GB_VCO_LOGEN)) & 0x00002000 ) >> 13)
+#define GET_RG_SX5GB_VCO_CS_AWH (((REG32(ADR_SX_5GB_VCO_LOGEN)) & 0x00004000 ) >> 14)
+#define GET_RG_HSDIV_INBFSEL (((REG32(ADR_SX_5GB_VCO_LOGEN)) & 0x00018000 ) >> 15)
+#define GET_RG_HSDIV_OBFMX_SEL (((REG32(ADR_SX_5GB_VCO_LOGEN)) & 0x00020000 ) >> 17)
+#define GET_RG_HSDIV_OBFSX_SEL (((REG32(ADR_SX_5GB_VCO_LOGEN)) & 0x00040000 ) >> 18)
+#define GET_RG_HSDIV_VRSEL (((REG32(ADR_SX_5GB_VCO_LOGEN)) & 0x00180000 ) >> 19)
+#define GET_RG_SXMIX_IBIAS_SEL (((REG32(ADR_SX_5GB_VCO_LOGEN)) & 0x00600000 ) >> 21)
+#define GET_RG_SXMIX_SWB_SEL (((REG32(ADR_SX_5GB_VCO_LOGEN)) & 0x01800000 ) >> 23)
+#define GET_RG_SXMIX_GMSEL (((REG32(ADR_SX_5GB_VCO_LOGEN)) & 0x06000000 ) >> 25)
+#define GET_RG_SXREP_SWB_SEL (((REG32(ADR_SX_5GB_VCO_LOGEN)) & 0x18000000 ) >> 27)
+#define GET_RG_SXREP_CSSEL (((REG32(ADR_SX_5GB_VCO_LOGEN)) & 0x60000000 ) >> 29)
+#define GET_RG_EN_SX5GB_VCOMON (((REG32(ADR_SX_5GB_VCO_LOGEN)) & 0x80000000 ) >> 31)
+#define GET_RG_SX5GB_DIV_PREVDD (((REG32(ADR_SX_5GB_DIV_SDM)) & 0x0000000f ) >> 0)
+#define GET_RG_SX5GB_DIV_PSCVDD (((REG32(ADR_SX_5GB_DIV_SDM)) & 0x000000f0 ) >> 4)
+#define GET_RG_SX5GB_DIV_RST_H (((REG32(ADR_SX_5GB_DIV_SDM)) & 0x00000200 ) >> 9)
+#define GET_RG_SX5GB_DIV_SDM_EDGE (((REG32(ADR_SX_5GB_DIV_SDM)) & 0x00000400 ) >> 10)
+#define GET_RG_SX5GB_DIV_DMYBUF_EN (((REG32(ADR_SX_5GB_DIV_SDM)) & 0x00000800 ) >> 11)
+#define GET_RG_EN_SX5GB_MOD (((REG32(ADR_SX_5GB_DIV_SDM)) & 0x00020000 ) >> 17)
+#define GET_RG_EN_SX5GB_DITHER (((REG32(ADR_SX_5GB_DIV_SDM)) & 0x00040000 ) >> 18)
+#define GET_RG_SX5GB_MOD_ORDER (((REG32(ADR_SX_5GB_DIV_SDM)) & 0x00180000 ) >> 19)
+#define GET_RG_SX5GB_DITHER_WEIGHT (((REG32(ADR_SX_5GB_DIV_SDM)) & 0x00600000 ) >> 21)
+#define GET_RG_SXMIX_INBF_SEL (((REG32(ADR_SX_5GB_DIV_SDM)) & 0x03000000 ) >> 24)
+#define GET_RG_SXMIX_GMBIAS_OP1 (((REG32(ADR_SX_5GB_DIV_SDM)) & 0x04000000 ) >> 26)
+#define GET_RG_SXMIX_SWBIAS_OP1 (((REG32(ADR_SX_5GB_DIV_SDM)) & 0x08000000 ) >> 27)
+#define GET_RG_SX5GB_SUB_SEL_MAN (((REG32(ADR_SX_5GB_SBCAL)) & 0x00000001 ) >> 0)
+#define GET_RG_SX5GB_SUB_SEL (((REG32(ADR_SX_5GB_SBCAL)) & 0x000001fe ) >> 1)
+#define GET_RG_SX5GB_SUB_C0P5_DIS (((REG32(ADR_SX_5GB_SBCAL)) & 0x00000200 ) >> 9)
+#define GET_RG_SX5GB_SBCAL_CT (((REG32(ADR_SX_5GB_SBCAL)) & 0x00000c00 ) >> 10)
+#define GET_RG_SX5GB_SBCAL_WT (((REG32(ADR_SX_5GB_SBCAL)) & 0x00001000 ) >> 12)
+#define GET_RG_SX5GB_SBCAL_DIFFMIN (((REG32(ADR_SX_5GB_SBCAL)) & 0x00002000 ) >> 13)
+#define GET_RG_SX5GB_SBCAL_NTARG_MAN (((REG32(ADR_SX_5GB_SBCAL)) & 0x00008000 ) >> 15)
+#define GET_RG_SX5GB_SBCAL_NTARG (((REG32(ADR_SX_5GB_SBCAL)) & 0xffff0000 ) >> 16)
+#define GET_RG_SX5GB_VOAAC_TAR (((REG32(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x0000000f ) >> 0)
+#define GET_RG_VO5GB_AAC_IOST (((REG32(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x00000030 ) >> 4)
+#define GET_RG_VO5GB_AAC_IMAX (((REG32(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x000003c0 ) >> 6)
+#define GET_RG_SX5GB_AAC_ACCUMH (((REG32(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x00000c00 ) >> 10)
+#define GET_RG_SX5GB_AAC_ACCUML (((REG32(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x00003000 ) >> 12)
+#define GET_RG_SX5GB_AAC_INIT (((REG32(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x0000c000 ) >> 14)
+#define GET_RG_SX5GB_AAC_EVA_TS (((REG32(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x00030000 ) >> 16)
+#define GET_RG_SX5GB_AAC_EN_MAN (((REG32(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x00040000 ) >> 18)
+#define GET_RG_SX5GB_AAC_EN (((REG32(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x00080000 ) >> 19)
+#define GET_RG_SX5GB_AAC_EVA_MAN (((REG32(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x00100000 ) >> 20)
+#define GET_RG_SX5GB_AAC_EVA (((REG32(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x00200000 ) >> 21)
+#define GET_RG_AAC5GB_TAR_MAN (((REG32(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x00400000 ) >> 22)
+#define GET_RG_AAC5GB_PDSW_EN_MAN (((REG32(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x01000000 ) >> 24)
+#define GET_RG_EN_AAC5GB_VOPDSW (((REG32(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x02000000 ) >> 25)
+#define GET_RG_EN_AAC5GB_MXPDSW (((REG32(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x04000000 ) >> 26)
+#define GET_RG_EN_AAC5GB_RPPDSW (((REG32(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x08000000 ) >> 27)
+#define GET_RG_SX5GB_AAC_TEST_EN (((REG32(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x40000000 ) >> 30)
+#define GET_RG_SX5GB_AAC_TEST_SEL (((REG32(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x80000000 ) >> 31)
+#define GET_RG_SX5GB_MIXAAC_TAR (((REG32(ADR_SX_5GB_LOGEN_CALIBRATION)) & 0x0000000f ) >> 0)
+#define GET_RG_SXMIX_SCA_SEL_MAN (((REG32(ADR_SX_5GB_LOGEN_CALIBRATION)) & 0x00000020 ) >> 5)
+#define GET_RG_SXMIX_SCA_SEL (((REG32(ADR_SX_5GB_LOGEN_CALIBRATION)) & 0x00000fc0 ) >> 6)
+#define GET_RG_SX5GB_REPAAC_TAR (((REG32(ADR_SX_5GB_LOGEN_CALIBRATION)) & 0x0001e000 ) >> 13)
+#define GET_RG_SXREP_SCA_SEL_MAN (((REG32(ADR_SX_5GB_LOGEN_CALIBRATION)) & 0x00040000 ) >> 18)
+#define GET_RG_SXREP_SCA_SEL (((REG32(ADR_SX_5GB_LOGEN_CALIBRATION)) & 0x01f80000 ) >> 19)
+#define GET_RG_5G_IDACAI_TZ0_PGAG15 (((REG32(ADR_5G_DCOC_IDAC_REGISTER1)) & 0x0000003f ) >> 0)
+#define GET_RG_5G_IDACAQ_TZ0_PGAG15 (((REG32(ADR_5G_DCOC_IDAC_REGISTER1)) & 0x00003f00 ) >> 8)
+#define GET_RG_5G_IDACAI_TZ0_PGAG14 (((REG32(ADR_5G_DCOC_IDAC_REGISTER1)) & 0x003f0000 ) >> 16)
+#define GET_RG_5G_IDACAQ_TZ0_PGAG14 (((REG32(ADR_5G_DCOC_IDAC_REGISTER1)) & 0x3f000000 ) >> 24)
+#define GET_RG_5G_IDACAI_TZ0_PGAG13 (((REG32(ADR_5G_DCOC_IDAC_REGISTER2)) & 0x0000003f ) >> 0)
+#define GET_RG_5G_IDACAQ_TZ0_PGAG13 (((REG32(ADR_5G_DCOC_IDAC_REGISTER2)) & 0x00003f00 ) >> 8)
+#define GET_RG_5G_IDACAI_TZ0_PGAG12 (((REG32(ADR_5G_DCOC_IDAC_REGISTER2)) & 0x003f0000 ) >> 16)
+#define GET_RG_5G_IDACAQ_TZ0_PGAG12 (((REG32(ADR_5G_DCOC_IDAC_REGISTER2)) & 0x3f000000 ) >> 24)
+#define GET_RG_5G_IDACAI_TZ0_PGAG11 (((REG32(ADR_5G_DCOC_IDAC_REGISTER3)) & 0x0000003f ) >> 0)
+#define GET_RG_5G_IDACAQ_TZ0_PGAG11 (((REG32(ADR_5G_DCOC_IDAC_REGISTER3)) & 0x00003f00 ) >> 8)
+#define GET_RG_5G_IDACAI_TZ0_PGAG10 (((REG32(ADR_5G_DCOC_IDAC_REGISTER3)) & 0x003f0000 ) >> 16)
+#define GET_RG_5G_IDACAQ_TZ0_PGAG10 (((REG32(ADR_5G_DCOC_IDAC_REGISTER3)) & 0x3f000000 ) >> 24)
+#define GET_RG_5G_IDACAI_TZ0_PGAG9 (((REG32(ADR_5G_DCOC_IDAC_REGISTER4)) & 0x0000003f ) >> 0)
+#define GET_RG_5G_IDACAQ_TZ0_PGAG9 (((REG32(ADR_5G_DCOC_IDAC_REGISTER4)) & 0x00003f00 ) >> 8)
+#define GET_RG_5G_IDACAI_TZ0_PGAG8 (((REG32(ADR_5G_DCOC_IDAC_REGISTER4)) & 0x003f0000 ) >> 16)
+#define GET_RG_5G_IDACAQ_TZ0_PGAG8 (((REG32(ADR_5G_DCOC_IDAC_REGISTER4)) & 0x3f000000 ) >> 24)
+#define GET_RG_5G_IDACAI_TZ0_PGAG7 (((REG32(ADR_5G_DCOC_IDAC_REGISTER5)) & 0x0000003f ) >> 0)
+#define GET_RG_5G_IDACAQ_TZ0_PGAG7 (((REG32(ADR_5G_DCOC_IDAC_REGISTER5)) & 0x00003f00 ) >> 8)
+#define GET_RG_5G_IDACAI_TZ0_PGAG6 (((REG32(ADR_5G_DCOC_IDAC_REGISTER5)) & 0x003f0000 ) >> 16)
+#define GET_RG_5G_IDACAQ_TZ0_PGAG6 (((REG32(ADR_5G_DCOC_IDAC_REGISTER5)) & 0x3f000000 ) >> 24)
+#define GET_RG_5G_IDACAI_TZ0_PGAG5 (((REG32(ADR_5G_DCOC_IDAC_REGISTER6)) & 0x0000003f ) >> 0)
+#define GET_RG_5G_IDACAQ_TZ0_PGAG5 (((REG32(ADR_5G_DCOC_IDAC_REGISTER6)) & 0x00003f00 ) >> 8)
+#define GET_RG_5G_IDACAI_TZ0_PGAG4 (((REG32(ADR_5G_DCOC_IDAC_REGISTER6)) & 0x003f0000 ) >> 16)
+#define GET_RG_5G_IDACAQ_TZ0_PGAG4 (((REG32(ADR_5G_DCOC_IDAC_REGISTER6)) & 0x3f000000 ) >> 24)
+#define GET_RG_5G_IDACAI_TZ0_PGAG3 (((REG32(ADR_5G_DCOC_IDAC_REGISTER7)) & 0x0000003f ) >> 0)
+#define GET_RG_5G_IDACAQ_TZ0_PGAG3 (((REG32(ADR_5G_DCOC_IDAC_REGISTER7)) & 0x00003f00 ) >> 8)
+#define GET_RG_5G_IDACAI_TZ0_PGAG2 (((REG32(ADR_5G_DCOC_IDAC_REGISTER7)) & 0x003f0000 ) >> 16)
+#define GET_RG_5G_IDACAQ_TZ0_PGAG2 (((REG32(ADR_5G_DCOC_IDAC_REGISTER7)) & 0x3f000000 ) >> 24)
+#define GET_RG_5G_IDACAI_TZ0_PGAG1 (((REG32(ADR_5G_DCOC_IDAC_REGISTER8)) & 0x0000003f ) >> 0)
+#define GET_RG_5G_IDACAQ_TZ0_PGAG1 (((REG32(ADR_5G_DCOC_IDAC_REGISTER8)) & 0x00003f00 ) >> 8)
+#define GET_RG_5G_IDACAI_TZ0_PGAG0 (((REG32(ADR_5G_DCOC_IDAC_REGISTER8)) & 0x003f0000 ) >> 16)
+#define GET_RG_5G_IDACAQ_TZ0_PGAG0 (((REG32(ADR_5G_DCOC_IDAC_REGISTER8)) & 0x3f000000 ) >> 24)
+#define GET_RG_5G_IDACAI_TZ1_PGAG15 (((REG32(ADR_5G_DCOC_IDAC_REGISTER9)) & 0x0000003f ) >> 0)
+#define GET_RG_5G_IDACAQ_TZ1_PGAG15 (((REG32(ADR_5G_DCOC_IDAC_REGISTER9)) & 0x00003f00 ) >> 8)
+#define GET_RG_5G_IDACAI_TZ1_PGAG14 (((REG32(ADR_5G_DCOC_IDAC_REGISTER9)) & 0x003f0000 ) >> 16)
+#define GET_RG_5G_IDACAQ_TZ1_PGAG14 (((REG32(ADR_5G_DCOC_IDAC_REGISTER9)) & 0x3f000000 ) >> 24)
+#define GET_RG_5G_IDACAI_TZ1_PGAG13 (((REG32(ADR_5G_DCOC_IDAC_REGISTER10)) & 0x0000003f ) >> 0)
+#define GET_RG_5G_IDACAQ_TZ1_PGAG13 (((REG32(ADR_5G_DCOC_IDAC_REGISTER10)) & 0x00003f00 ) >> 8)
+#define GET_RG_5G_IDACAI_TZ1_PGAG12 (((REG32(ADR_5G_DCOC_IDAC_REGISTER10)) & 0x003f0000 ) >> 16)
+#define GET_RG_5G_IDACAQ_TZ1_PGAG12 (((REG32(ADR_5G_DCOC_IDAC_REGISTER10)) & 0x3f000000 ) >> 24)
+#define GET_RG_5G_IDACAI_TZ1_PGAG11 (((REG32(ADR_5G_DCOC_IDAC_REGISTER11)) & 0x0000003f ) >> 0)
+#define GET_RG_5G_IDACAQ_TZ1_PGAG11 (((REG32(ADR_5G_DCOC_IDAC_REGISTER11)) & 0x00003f00 ) >> 8)
+#define GET_RG_5G_IDACAI_TZ1_PGAG10 (((REG32(ADR_5G_DCOC_IDAC_REGISTER11)) & 0x003f0000 ) >> 16)
+#define GET_RG_5G_IDACAQ_TZ1_PGAG10 (((REG32(ADR_5G_DCOC_IDAC_REGISTER11)) & 0x3f000000 ) >> 24)
+#define GET_RG_5G_IDACAI_TZ1_PGAG9 (((REG32(ADR_5G_DCOC_IDAC_REGISTER12)) & 0x0000003f ) >> 0)
+#define GET_RG_5G_IDACAQ_TZ1_PGAG9 (((REG32(ADR_5G_DCOC_IDAC_REGISTER12)) & 0x00003f00 ) >> 8)
+#define GET_RG_5G_IDACAI_TZ1_PGAG8 (((REG32(ADR_5G_DCOC_IDAC_REGISTER12)) & 0x003f0000 ) >> 16)
+#define GET_RG_5G_IDACAQ_TZ1_PGAG8 (((REG32(ADR_5G_DCOC_IDAC_REGISTER12)) & 0x3f000000 ) >> 24)
+#define GET_RG_5G_IDACAI_TZ1_PGAG7 (((REG32(ADR_5G_DCOC_IDAC_REGISTER13)) & 0x0000003f ) >> 0)
+#define GET_RG_5G_IDACAQ_TZ1_PGAG7 (((REG32(ADR_5G_DCOC_IDAC_REGISTER13)) & 0x00003f00 ) >> 8)
+#define GET_RG_5G_IDACAI_TZ1_PGAG6 (((REG32(ADR_5G_DCOC_IDAC_REGISTER13)) & 0x003f0000 ) >> 16)
+#define GET_RG_5G_IDACAQ_TZ1_PGAG6 (((REG32(ADR_5G_DCOC_IDAC_REGISTER13)) & 0x3f000000 ) >> 24)
+#define GET_RG_5G_IDACAI_TZ1_PGAG5 (((REG32(ADR_5G_DCOC_IDAC_REGISTER14)) & 0x0000003f ) >> 0)
+#define GET_RG_5G_IDACAQ_TZ1_PGAG5 (((REG32(ADR_5G_DCOC_IDAC_REGISTER14)) & 0x00003f00 ) >> 8)
+#define GET_RG_5G_IDACAI_TZ1_PGAG4 (((REG32(ADR_5G_DCOC_IDAC_REGISTER14)) & 0x003f0000 ) >> 16)
+#define GET_RG_5G_IDACAQ_TZ1_PGAG4 (((REG32(ADR_5G_DCOC_IDAC_REGISTER14)) & 0x3f000000 ) >> 24)
+#define GET_RG_5G_IDACAI_TZ1_PGAG3 (((REG32(ADR_5G_DCOC_IDAC_REGISTER15)) & 0x0000003f ) >> 0)
+#define GET_RG_5G_IDACAQ_TZ1_PGAG3 (((REG32(ADR_5G_DCOC_IDAC_REGISTER15)) & 0x00003f00 ) >> 8)
+#define GET_RG_5G_IDACAI_TZ1_PGAG2 (((REG32(ADR_5G_DCOC_IDAC_REGISTER15)) & 0x003f0000 ) >> 16)
+#define GET_RG_5G_IDACAQ_TZ1_PGAG2 (((REG32(ADR_5G_DCOC_IDAC_REGISTER15)) & 0x3f000000 ) >> 24)
+#define GET_RG_5G_IDACAI_TZ1_PGAG1 (((REG32(ADR_5G_DCOC_IDAC_REGISTER16)) & 0x0000003f ) >> 0)
+#define GET_RG_5G_IDACAQ_TZ1_PGAG1 (((REG32(ADR_5G_DCOC_IDAC_REGISTER16)) & 0x00003f00 ) >> 8)
+#define GET_RG_5G_IDACAI_TZ1_PGAG0 (((REG32(ADR_5G_DCOC_IDAC_REGISTER16)) & 0x003f0000 ) >> 16)
+#define GET_RG_5G_IDACAQ_TZ1_PGAG0 (((REG32(ADR_5G_DCOC_IDAC_REGISTER16)) & 0x3f000000 ) >> 24)
+#define GET_RG_5G_IDACAI_TZ0_COARSE4 (((REG32(ADR_5G_DCOC_IDAC_REGISTER17)) & 0x0000003f ) >> 0)
+#define GET_RG_5G_IDACAQ_TZ0_COARSE4 (((REG32(ADR_5G_DCOC_IDAC_REGISTER17)) & 0x00003f00 ) >> 8)
+#define GET_RG_5G_IDACAI_TZ0_COARSE3 (((REG32(ADR_5G_DCOC_IDAC_REGISTER17)) & 0x003f0000 ) >> 16)
+#define GET_RG_5G_IDACAQ_TZ0_COARSE3 (((REG32(ADR_5G_DCOC_IDAC_REGISTER17)) & 0x3f000000 ) >> 24)
+#define GET_RG_5G_IDACAI_TZ0_COARSE2 (((REG32(ADR_5G_DCOC_IDAC_REGISTER18)) & 0x0000003f ) >> 0)
+#define GET_RG_5G_IDACAQ_TZ0_COARSE2 (((REG32(ADR_5G_DCOC_IDAC_REGISTER18)) & 0x00003f00 ) >> 8)
+#define GET_RG_5G_IDACAI_TZ0_COARSE1 (((REG32(ADR_5G_DCOC_IDAC_REGISTER18)) & 0x003f0000 ) >> 16)
+#define GET_RG_5G_IDACAQ_TZ0_COARSE1 (((REG32(ADR_5G_DCOC_IDAC_REGISTER18)) & 0x3f000000 ) >> 24)
+#define GET_RG_5G_IDACAI_TZ0_COARSE0 (((REG32(ADR_5G_DCOC_IDAC_REGISTER19)) & 0x0000003f ) >> 0)
+#define GET_RG_5G_IDACAQ_TZ0_COARSE0 (((REG32(ADR_5G_DCOC_IDAC_REGISTER19)) & 0x00003f00 ) >> 8)
+#define GET_RG_5G_IDACAI_TZ1_COARSE4 (((REG32(ADR_5G_DCOC_IDAC_REGISTER19)) & 0x003f0000 ) >> 16)
+#define GET_RG_5G_IDACAQ_TZ1_COARSE4 (((REG32(ADR_5G_DCOC_IDAC_REGISTER19)) & 0x3f000000 ) >> 24)
+#define GET_RG_5G_IDACAI_TZ1_COARSE3 (((REG32(ADR_5G_DCOC_IDAC_REGISTER20)) & 0x0000003f ) >> 0)
+#define GET_RG_5G_IDACAQ_TZ1_COARSE3 (((REG32(ADR_5G_DCOC_IDAC_REGISTER20)) & 0x00003f00 ) >> 8)
+#define GET_RG_5G_IDACAI_TZ1_COARSE2 (((REG32(ADR_5G_DCOC_IDAC_REGISTER20)) & 0x003f0000 ) >> 16)
+#define GET_RG_5G_IDACAQ_TZ1_COARSE2 (((REG32(ADR_5G_DCOC_IDAC_REGISTER20)) & 0x3f000000 ) >> 24)
+#define GET_RG_5G_IDACAI_TZ1_COARSE1 (((REG32(ADR_5G_DCOC_IDAC_REGISTER21)) & 0x0000003f ) >> 0)
+#define GET_RG_5G_IDACAQ_TZ1_COARSE1 (((REG32(ADR_5G_DCOC_IDAC_REGISTER21)) & 0x00003f00 ) >> 8)
+#define GET_RG_5G_IDACAI_TZ1_COARSE0 (((REG32(ADR_5G_DCOC_IDAC_REGISTER21)) & 0x003f0000 ) >> 16)
+#define GET_RG_5G_IDACAQ_TZ1_COARSE0 (((REG32(ADR_5G_DCOC_IDAC_REGISTER21)) & 0x3f000000 ) >> 24)
+#define GET_RG_SX5GB_DELAY (((REG32(ADR_5G_MODE_DECODER_TIMER_REGISTER1)) & 0x0000000f ) >> 0)
+#define GET_RG_5G_TXDAC_DELAY (((REG32(ADR_5G_MODE_DECODER_TIMER_REGISTER1)) & 0x000000f0 ) >> 4)
+#define GET_RG_5G_TXRF_DELAY (((REG32(ADR_5G_MODE_DECODER_TIMER_REGISTER1)) & 0x00000f00 ) >> 8)
+#define GET_RG_5G_TXPA_DELAY (((REG32(ADR_5G_MODE_DECODER_TIMER_REGISTER1)) & 0x0000f000 ) >> 12)
+#define GET_RG_5G_RXRF_DELAY (((REG32(ADR_5G_MODE_DECODER_TIMER_REGISTER1)) & 0x000f0000 ) >> 16)
+#define GET_RG_5G_TXDAC_T2R_DELAY (((REG32(ADR_5G_T2R_TIMER_REGISTER)) & 0x0000001f ) >> 0)
+#define GET_RG_5G_TXRF_T2R_DELAY (((REG32(ADR_5G_T2R_TIMER_REGISTER)) & 0x00001f00 ) >> 8)
+#define GET_RG_5G_TXPA_T2R_DELAY (((REG32(ADR_5G_T2R_TIMER_REGISTER)) & 0x001f0000 ) >> 16)
+#define GET_RG_5G_RXRF_T2R_DELAY (((REG32(ADR_5G_T2R_TIMER_REGISTER)) & 0x1f000000 ) >> 24)
+#define GET_RG_5G_TXDAC_R2T_DELAY (((REG32(ADR_5G_R2T_TIMER_REGISTER)) & 0x0000001f ) >> 0)
+#define GET_RG_5G_TXRF_R2T_DELAY (((REG32(ADR_5G_R2T_TIMER_REGISTER)) & 0x00001f00 ) >> 8)
+#define GET_RG_5G_TXPA_R2T_DELAY (((REG32(ADR_5G_R2T_TIMER_REGISTER)) & 0x001f0000 ) >> 16)
+#define GET_RG_5G_RXRF_R2T_DELAY (((REG32(ADR_5G_R2T_TIMER_REGISTER)) & 0x1f000000 ) >> 24)
+#define GET_RG_5G_RX_DCCAL_DELAY (((REG32(ADR_5G_CALIBRATION_TIMER_GAIN_REGISTER)) & 0x00000007 ) >> 0)
+#define GET_RG_5G_TX_DCCAL_DELAY (((REG32(ADR_5G_CALIBRATION_TIMER_GAIN_REGISTER)) & 0x00000700 ) >> 8)
+#define GET_RG_5G_TX_IQCAL_DELAY (((REG32(ADR_5G_CALIBRATION_TIMER_GAIN_REGISTER)) & 0x00007000 ) >> 12)
+#define GET_RG_5G_RX_IQCAL_DELAY (((REG32(ADR_5G_CALIBRATION_TIMER_GAIN_REGISTER)) & 0x00070000 ) >> 16)
+#define GET_RG_5G_PGAG_TXCAL (((REG32(ADR_5G_CALIBRATION_TIMER_GAIN_REGISTER)) & 0x00f00000 ) >> 20)
+#define GET_RG_5G_TX_GAIN_TXCAL (((REG32(ADR_5G_CALIBRATION_TIMER_GAIN_REGISTER)) & 0x7f000000 ) >> 24)
+#define GET_RG_5G_PGAG_RCCAL (((REG32(ADR_5G_CALIBRATION_GAIN_REGISTER1)) & 0x0000000f ) >> 0)
+#define GET_RG_5G_RFG_RXIQCAL (((REG32(ADR_5G_CALIBRATION_GAIN_REGISTER1)) & 0x00000030 ) >> 4)
+#define GET_RG_5G_PGAG_RXIQCAL (((REG32(ADR_5G_CALIBRATION_GAIN_REGISTER1)) & 0x000003c0 ) >> 6)
+#define GET_RG_5G_TX_GAIN_RXIQCAL (((REG32(ADR_5G_CALIBRATION_GAIN_REGISTER1)) & 0x0001fc00 ) >> 10)
+#define GET_RG_5G_RFG_DPDCAL (((REG32(ADR_5G_CALIBRATION_GAIN_REGISTER1)) & 0x00060000 ) >> 17)
+#define GET_RG_5G_PGAG_DPDCAL (((REG32(ADR_5G_CALIBRATION_GAIN_REGISTER1)) & 0x00780000 ) >> 19)
+#define GET_RG_5G_TX_GAIN_DPDCAL (((REG32(ADR_5G_CALIBRATION_GAIN_REGISTER1)) & 0x3f800000 ) >> 23)
+#define GET_DB_DA_SX5GB_SUB_SEL (((REG32(ADR_READ_ONLY_FLAGS_SX_5GB_1)) & 0x000000ff ) >> 0)
+#define GET_DB_DA_SX5GB_VCO_ISEL (((REG32(ADR_READ_ONLY_FLAGS_SX_5GB_1)) & 0x00000f00 ) >> 8)
+#define GET_DB_DA_SXMIX_SCA_SEL (((REG32(ADR_READ_ONLY_FLAGS_SX_5GB_1)) & 0x0007e000 ) >> 13)
+#define GET_DB_DA_SXMIX_GMSEL (((REG32(ADR_READ_ONLY_FLAGS_SX_5GB_1)) & 0x00180000 ) >> 19)
+#define GET_DB_DA_SXREP_SCA_SEL (((REG32(ADR_READ_ONLY_FLAGS_SX_5GB_1)) & 0x07e00000 ) >> 21)
+#define GET_DB_DA_SXREP_CSSEL (((REG32(ADR_READ_ONLY_FLAGS_SX_5GB_1)) & 0x18000000 ) >> 27)
+#define GET_DB_AD_SX5GB_AAC_COMPOUT (((REG32(ADR_READ_ONLY_FLAGS_SX_5GB_1)) & 0x20000000 ) >> 29)
+#define GET_DB_SX5GB_TTL_VT_DET (((REG32(ADR_READ_ONLY_FLAGS_SX_5GB_1)) & 0xc0000000 ) >> 30)
+#define GET_DB_SXMIX_SCA_SEL_A1 (((REG32(ADR_READ_ONLY_FLAGS_SX_5GB_2)) & 0x0000003f ) >> 0)
+#define GET_DB_SXMIX_SCA_SEL_A2 (((REG32(ADR_READ_ONLY_FLAGS_SX_5GB_2)) & 0x00001f80 ) >> 7)
+#define GET_DB_SXREP_SCA_SEL_B1 (((REG32(ADR_READ_ONLY_FLAGS_SX_5GB_2)) & 0x000fc000 ) >> 14)
+#define GET_DB_SXREP_SCA_SEL_B2 (((REG32(ADR_READ_ONLY_FLAGS_SX_5GB_2)) & 0x07e00000 ) >> 21)
+#define GET_DB_SX5GB_SBCAL_NCOUNT (((REG32(ADR_READ_ONLY_FLAGS_SX_5GB_3)) & 0x0000ffff ) >> 0)
+#define GET_DB_SX5GB_SBCAL_NTARGET (((REG32(ADR_READ_ONLY_FLAGS_SX_5GB_3)) & 0xffff0000 ) >> 16)
+#define GET_RG_RX_SCAMA_STEP0 (((REG32(ADR_5G_RX_LNA_MATCHING_SCA_CONTROL)) & 0x0000000f ) >> 0)
+#define GET_RG_RX_SCAMA_STEP1 (((REG32(ADR_5G_RX_LNA_MATCHING_SCA_CONTROL)) & 0x000000f0 ) >> 4)
+#define GET_RG_RX_SCAMA_STEP2 (((REG32(ADR_5G_RX_LNA_MATCHING_SCA_CONTROL)) & 0x00000f00 ) >> 8)
+#define GET_RG_RX_SCAMA_STEP3 (((REG32(ADR_5G_RX_LNA_MATCHING_SCA_CONTROL)) & 0x0000f000 ) >> 12)
+#define GET_RG_RX_SCAMA_STEP4 (((REG32(ADR_5G_RX_LNA_MATCHING_SCA_CONTROL)) & 0x000f0000 ) >> 16)
+#define GET_RG_RX_SCAMA_STEP5 (((REG32(ADR_5G_RX_LNA_MATCHING_SCA_CONTROL)) & 0x00f00000 ) >> 20)
+#define GET_RG_RX_SCAMA_STEP6 (((REG32(ADR_5G_RX_LNA_MATCHING_SCA_CONTROL)) & 0x0f000000 ) >> 24)
+#define GET_RG_RX_SCALOAD_STEP0 (((REG32(ADR_5G_RX_LNA_LOAD_SCA_CONTROL)) & 0x0000000f ) >> 0)
+#define GET_RG_RX_SCALOAD_STEP1 (((REG32(ADR_5G_RX_LNA_LOAD_SCA_CONTROL)) & 0x000000f0 ) >> 4)
+#define GET_RG_RX_SCALOAD_STEP2 (((REG32(ADR_5G_RX_LNA_LOAD_SCA_CONTROL)) & 0x00000f00 ) >> 8)
+#define GET_RG_RX_SCALOAD_STEP3 (((REG32(ADR_5G_RX_LNA_LOAD_SCA_CONTROL)) & 0x0000f000 ) >> 12)
+#define GET_RG_RX_SCALOAD_STEP4 (((REG32(ADR_5G_RX_LNA_LOAD_SCA_CONTROL)) & 0x000f0000 ) >> 16)
+#define GET_RG_RX_SCALOAD_STEP5 (((REG32(ADR_5G_RX_LNA_LOAD_SCA_CONTROL)) & 0x00f00000 ) >> 20)
+#define GET_RG_RX_SCALOAD_STEP6 (((REG32(ADR_5G_RX_LNA_LOAD_SCA_CONTROL)) & 0x0f000000 ) >> 24)
+#define GET_RG_5G_TXPGA_CAPSW_F0 (((REG32(ADR_5G_TX_PGA_CAPSW_CONTROL_I)) & 0x00000007 ) >> 0)
+#define GET_RG_5G_PABIAS_CTRL_F0 (((REG32(ADR_5G_TX_PGA_CAPSW_CONTROL_I)) & 0x00000078 ) >> 3)
+#define GET_RG_5G_TX_PA1_VCAS_F0 (((REG32(ADR_5G_TX_PGA_CAPSW_CONTROL_I)) & 0x00000380 ) >> 7)
+#define GET_RG_5G_TX_PA2_VCAS_F0 (((REG32(ADR_5G_TX_PGA_CAPSW_CONTROL_I)) & 0x00001c00 ) >> 10)
+#define GET_RG_5G_TX_PA3_VCAS_F0 (((REG32(ADR_5G_TX_PGA_CAPSW_CONTROL_I)) & 0x0000e000 ) >> 13)
+#define GET_RG_5G_TXPGA_CAPSW_F1 (((REG32(ADR_5G_TX_PGA_CAPSW_CONTROL_I)) & 0x00070000 ) >> 16)
+#define GET_RG_5G_PABIAS_CTRL_F1 (((REG32(ADR_5G_TX_PGA_CAPSW_CONTROL_I)) & 0x00780000 ) >> 19)
+#define GET_RG_5G_TX_PA1_VCAS_F1 (((REG32(ADR_5G_TX_PGA_CAPSW_CONTROL_I)) & 0x03800000 ) >> 23)
+#define GET_RG_5G_TX_PA2_VCAS_F1 (((REG32(ADR_5G_TX_PGA_CAPSW_CONTROL_I)) & 0x1c000000 ) >> 26)
+#define GET_RG_5G_TX_PA3_VCAS_F1 (((REG32(ADR_5G_TX_PGA_CAPSW_CONTROL_I)) & 0xe0000000 ) >> 29)
+#define GET_RG_5G_TXPGA_CAPSW_F2 (((REG32(ADR_5G_TX_PGA_CAPSW_CONTROL_II)) & 0x00000007 ) >> 0)
+#define GET_RG_5G_PABIAS_CTRL_F2 (((REG32(ADR_5G_TX_PGA_CAPSW_CONTROL_II)) & 0x00000078 ) >> 3)
+#define GET_RG_5G_TX_PA1_VCAS_F2 (((REG32(ADR_5G_TX_PGA_CAPSW_CONTROL_II)) & 0x00000380 ) >> 7)
+#define GET_RG_5G_TX_PA2_VCAS_F2 (((REG32(ADR_5G_TX_PGA_CAPSW_CONTROL_II)) & 0x00001c00 ) >> 10)
+#define GET_RG_5G_TX_PA3_VCAS_F2 (((REG32(ADR_5G_TX_PGA_CAPSW_CONTROL_II)) & 0x0000e000 ) >> 13)
+#define GET_RG_5G_TXPGA_CAPSW_F3 (((REG32(ADR_5G_TX_PGA_CAPSW_CONTROL_II)) & 0x00070000 ) >> 16)
+#define GET_RG_5G_PABIAS_CTRL_F3 (((REG32(ADR_5G_TX_PGA_CAPSW_CONTROL_II)) & 0x00780000 ) >> 19)
+#define GET_RG_5G_TX_PA1_VCAS_F3 (((REG32(ADR_5G_TX_PGA_CAPSW_CONTROL_II)) & 0x03800000 ) >> 23)
+#define GET_RG_5G_TX_PA2_VCAS_F3 (((REG32(ADR_5G_TX_PGA_CAPSW_CONTROL_II)) & 0x1c000000 ) >> 26)
+#define GET_RG_5G_TX_PA3_VCAS_F3 (((REG32(ADR_5G_TX_PGA_CAPSW_CONTROL_II)) & 0xe0000000 ) >> 29)
+#define GET_RG_5G_TX_PAFB_EN_F0 (((REG32(ADR_5G_TX_GAIN_PAFB_CONTROL)) & 0x00000001 ) >> 0)
+#define GET_RG_5G_TX_PAFB_EN_F1 (((REG32(ADR_5G_TX_GAIN_PAFB_CONTROL)) & 0x00000002 ) >> 1)
+#define GET_RG_5G_TX_PAFB_EN_F2 (((REG32(ADR_5G_TX_GAIN_PAFB_CONTROL)) & 0x00000004 ) >> 2)
+#define GET_RG_5G_TX_PAFB_EN_F3 (((REG32(ADR_5G_TX_GAIN_PAFB_CONTROL)) & 0x00000008 ) >> 3)
+#define GET_RG_5G_TX_GAIN_F0 (((REG32(ADR_5G_TX_GAIN_PAFB_CONTROL)) & 0x000007f0 ) >> 4)
+#define GET_RG_5G_TX_GAIN_F1 (((REG32(ADR_5G_TX_GAIN_PAFB_CONTROL)) & 0x0003f800 ) >> 11)
+#define GET_RG_5G_TX_GAIN_F2 (((REG32(ADR_5G_TX_GAIN_PAFB_CONTROL)) & 0x01fc0000 ) >> 18)
+#define GET_RG_5G_TX_GAIN_F3 (((REG32(ADR_5G_TX_GAIN_PAFB_CONTROL)) & 0xfe000000 ) >> 25)
+#define GET_RG_NFRAC_DELTA (((REG32(ADR_DIGITAL_ADD_ON_0)) & 0x00ffffff ) >> 0)
+#define GET_RG_40M_MODE (((REG32(ADR_DIGITAL_ADD_ON_0)) & 0x01000000 ) >> 24)
+#define GET_RG_LO_UP_CH (((REG32(ADR_DIGITAL_ADD_ON_0)) & 0x10000000 ) >> 28)
+#define GET_RG_BT_TRX_IF (((REG32(ADR_DIGITAL_ADD_ON_1)) & 0x07ff0000 ) >> 16)
+#define GET_RG_RX_IQ_ALPHA (((REG32(ADR_DIGITAL_ADD_ON_2)) & 0x0000001f ) >> 0)
+#define GET_RG_RX_IQ_THETA (((REG32(ADR_DIGITAL_ADD_ON_2)) & 0x00001f00 ) >> 8)
+#define GET_RG_RX_IQ_MANUAL (((REG32(ADR_DIGITAL_ADD_ON_2)) & 0x00010000 ) >> 16)
+#define GET_RG_RXIQ_NOSHRK (((REG32(ADR_DIGITAL_ADD_ON_2)) & 0x00020000 ) >> 17)
+#define GET_RG_RX_RSSIADC_TH (((REG32(ADR_DIGITAL_ADD_ON_2)) & 0x00f00000 ) >> 20)
+#define GET_RG_SUB_DC (((REG32(ADR_DIGITAL_ADD_ON_2)) & 0x01000000 ) >> 24)
+#define GET_RG_RSSI_EDGE_SEL (((REG32(ADR_DIGITAL_ADD_ON_2)) & 0x04000000 ) >> 26)
+#define GET_RG_ADC_EDGE_SEL (((REG32(ADR_DIGITAL_ADD_ON_2)) & 0x08000000 ) >> 27)
+#define GET_RG_Q_INV (((REG32(ADR_DIGITAL_ADD_ON_2)) & 0x10000000 ) >> 28)
+#define GET_RG_I_INV (((REG32(ADR_DIGITAL_ADD_ON_2)) & 0x20000000 ) >> 29)
+#define GET_RG_IQ_SWAP (((REG32(ADR_DIGITAL_ADD_ON_2)) & 0x40000000 ) >> 30)
+#define GET_RG_SIGN_SWAP (((REG32(ADR_DIGITAL_ADD_ON_2)) & 0x80000000 ) >> 31)
+#define GET_RG_TX_IQ_ALPHA (((REG32(ADR_DIGITAL_ADD_ON_3)) & 0x0000001f ) >> 0)
+#define GET_RG_TX_IQ_THETA (((REG32(ADR_DIGITAL_ADD_ON_3)) & 0x00001f00 ) >> 8)
+#define GET_RG_TX_IQ_MANUAL (((REG32(ADR_DIGITAL_ADD_ON_3)) & 0x00010000 ) >> 16)
+#define GET_RG_TXIQ_NOSHRK (((REG32(ADR_DIGITAL_ADD_ON_3)) & 0x00020000 ) >> 17)
+#define GET_RG_TX_IQCAL_TIME (((REG32(ADR_DIGITAL_ADD_ON_3)) & 0x00300000 ) >> 20)
+#define GET_RG_TX_FREQ_OFFSET (((REG32(ADR_DIGITAL_ADD_ON_4)) & 0x0000ffff ) >> 0)
+#define GET_RG_TONE_SCALE (((REG32(ADR_DIGITAL_ADD_ON_4)) & 0x01ff0000 ) >> 16)
+#define GET_RG_BB_SIG_EN (((REG32(ADR_DIGITAL_ADD_ON_4)) & 0x02000000 ) >> 25)
+#define GET_RG_TONE_GEN_EN (((REG32(ADR_DIGITAL_ADD_ON_4)) & 0x04000000 ) >> 26)
+#define GET_RG_TX_UP8X_MAN_EN (((REG32(ADR_DIGITAL_ADD_ON_4)) & 0x08000000 ) >> 27)
+#define GET_RG_DIS_DAC_OFFSET (((REG32(ADR_DIGITAL_ADD_ON_4)) & 0x10000000 ) >> 28)
+#define GET_RG_CLK_320M_INV (((REG32(ADR_DIGITAL_ADD_ON_4)) & 0x20000000 ) >> 29)
+#define GET_RG_DPLL_CLK320BY2 (((REG32(ADR_DIGITAL_ADD_ON_4)) & 0x40000000 ) >> 30)
+#define GET_RG_CBW_20_40 (((REG32(ADR_DIGITAL_ADD_ON_4)) & 0x80000000 ) >> 31)
+#define GET_RG_DAC_DC_Q (((REG32(ADR_DIGITAL_ADD_ON_5)) & 0x000003ff ) >> 0)
+#define GET_RG_DAC_DC_I (((REG32(ADR_DIGITAL_ADD_ON_5)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DAC_Q_SET (((REG32(ADR_DIGITAL_ADD_ON_6)) & 0x000003ff ) >> 0)
+#define GET_RG_DAC_MAN_Q_EN (((REG32(ADR_DIGITAL_ADD_ON_6)) & 0x00001000 ) >> 12)
+#define GET_RG_DAC_I_SET (((REG32(ADR_DIGITAL_ADD_ON_6)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DAC_MAN_I_EN (((REG32(ADR_DIGITAL_ADD_ON_6)) & 0x10000000 ) >> 28)
+#define GET_RG_WF_RX_ABBCTUNE_TUNE (((REG32(ADR_RX_RC_VALUE_TUNE)) & 0x0000007f ) >> 0)
+#define GET_RG_WF_RX_ABBCTUNE_TUNE_EN (((REG32(ADR_RX_RC_VALUE_TUNE)) & 0x00000100 ) >> 8)
+#define GET_RG_WF_N_RX_ABBCTUNE_TUNE (((REG32(ADR_RX_RC_VALUE_TUNE)) & 0x007f0000 ) >> 16)
+#define GET_RG_WF_N_RX_ABBCTUNE_TUNE_EN (((REG32(ADR_RX_RC_VALUE_TUNE)) & 0x01000000 ) >> 24)
+#define GET_RG_RX_IQ_2500_ALPHA (((REG32(ADR_TRX_IQ_COMP_2G)) & 0x0000001f ) >> 0)
+#define GET_RG_RX_IQ_2500_THETA (((REG32(ADR_TRX_IQ_COMP_2G)) & 0x00001f00 ) >> 8)
+#define GET_RG_TX_IQ_2500_ALPHA (((REG32(ADR_TRX_IQ_COMP_2G)) & 0x001f0000 ) >> 16)
+#define GET_RG_TX_IQ_2500_THETA (((REG32(ADR_TRX_IQ_COMP_2G)) & 0x1f000000 ) >> 24)
+#define GET_RG_RX_IQ_5100_ALPHA (((REG32(ADR_TRX_IQ_COMP_5G_0)) & 0x0000001f ) >> 0)
+#define GET_RG_RX_IQ_5100_THETA (((REG32(ADR_TRX_IQ_COMP_5G_0)) & 0x00001f00 ) >> 8)
+#define GET_RG_TX_IQ_5100_ALPHA (((REG32(ADR_TRX_IQ_COMP_5G_0)) & 0x001f0000 ) >> 16)
+#define GET_RG_TX_IQ_5100_THETA (((REG32(ADR_TRX_IQ_COMP_5G_0)) & 0x1f000000 ) >> 24)
+#define GET_RG_RX_IQ_5500_ALPHA (((REG32(ADR_TRX_IQ_COMP_5G_1)) & 0x0000001f ) >> 0)
+#define GET_RG_RX_IQ_5500_THETA (((REG32(ADR_TRX_IQ_COMP_5G_1)) & 0x00001f00 ) >> 8)
+#define GET_RG_TX_IQ_5500_ALPHA (((REG32(ADR_TRX_IQ_COMP_5G_1)) & 0x001f0000 ) >> 16)
+#define GET_RG_TX_IQ_5500_THETA (((REG32(ADR_TRX_IQ_COMP_5G_1)) & 0x1f000000 ) >> 24)
+#define GET_RG_RX_IQ_5700_ALPHA (((REG32(ADR_TRX_IQ_COMP_5G_2)) & 0x0000001f ) >> 0)
+#define GET_RG_RX_IQ_5700_THETA (((REG32(ADR_TRX_IQ_COMP_5G_2)) & 0x00001f00 ) >> 8)
+#define GET_RG_TX_IQ_5700_ALPHA (((REG32(ADR_TRX_IQ_COMP_5G_2)) & 0x001f0000 ) >> 16)
+#define GET_RG_TX_IQ_5700_THETA (((REG32(ADR_TRX_IQ_COMP_5G_2)) & 0x1f000000 ) >> 24)
+#define GET_RG_RX_IQ_5900_ALPHA (((REG32(ADR_TRX_IQ_COMP_5G_3)) & 0x0000001f ) >> 0)
+#define GET_RG_RX_IQ_5900_THETA (((REG32(ADR_TRX_IQ_COMP_5G_3)) & 0x00001f00 ) >> 8)
+#define GET_RG_TX_IQ_5900_ALPHA (((REG32(ADR_TRX_IQ_COMP_5G_3)) & 0x001f0000 ) >> 16)
+#define GET_RG_TX_IQ_5900_THETA (((REG32(ADR_TRX_IQ_COMP_5G_3)) & 0x1f000000 ) >> 24)
+#define GET_RG_PHASE_STEP_VALUE (((REG32(ADR_RF_D_CAL_TOP_0)) & 0x0000ffff ) >> 0)
+#define GET_RG_PHASE_MANUAL (((REG32(ADR_RF_D_CAL_TOP_0)) & 0x00010000 ) >> 16)
+#define GET_RG_ALPHA_SEL (((REG32(ADR_RF_D_CAL_TOP_0)) & 0x00300000 ) >> 20)
+#define GET_RG_SPECTRUM_BW (((REG32(ADR_RF_D_CAL_TOP_0)) & 0x03000000 ) >> 24)
+#define GET_RG_SPECTRUM_EN (((REG32(ADR_RF_D_CAL_TOP_0)) & 0x10000000 ) >> 28)
+#define GET_RO_WF_DCCAL_DONE (((REG32(ADR_RF_D_CAL_TOP_1)) & 0x00010000 ) >> 16)
+#define GET_RO_BT_DCCAL_DONE (((REG32(ADR_RF_D_CAL_TOP_1)) & 0x00020000 ) >> 17)
+#define GET_RO_RCCAL_DONE (((REG32(ADR_RF_D_CAL_TOP_1)) & 0x00040000 ) >> 18)
+#define GET_RO_TXDC_DONE (((REG32(ADR_RF_D_CAL_TOP_1)) & 0x00080000 ) >> 19)
+#define GET_RO_TXIQ_DONE (((REG32(ADR_RF_D_CAL_TOP_1)) & 0x00100000 ) >> 20)
+#define GET_RO_RXIQ_DONE (((REG32(ADR_RF_D_CAL_TOP_1)) & 0x00200000 ) >> 21)
+#define GET_RO_5G_TXDC_DONE (((REG32(ADR_RF_D_CAL_TOP_1)) & 0x00400000 ) >> 22)
+#define GET_RO_5G_TXIQ_DONE (((REG32(ADR_RF_D_CAL_TOP_1)) & 0x00800000 ) >> 23)
+#define GET_RO_5G_RXIQ_DONE (((REG32(ADR_RF_D_CAL_TOP_1)) & 0x01000000 ) >> 24)
+#define GET_RO_5G_DCCAL_DONE (((REG32(ADR_RF_D_CAL_TOP_1)) & 0x02000000 ) >> 25)
+#define GET_RO_PRE_DC_DONE (((REG32(ADR_RF_D_CAL_TOP_1)) & 0x04000000 ) >> 26)
+#define GET_RG_PHASE_17P5M (((REG32(ADR_RF_D_CAL_TOP_2)) & 0x0000ffff ) >> 0)
+#define GET_RG_PHASE_2P5M (((REG32(ADR_RF_D_CAL_TOP_2)) & 0xffff0000 ) >> 16)
+#define GET_RG_PHASE_RXIQ_1M (((REG32(ADR_RF_D_CAL_TOP_3)) & 0x0000ffff ) >> 0)
+#define GET_RG_PHASE_1M (((REG32(ADR_RF_D_CAL_TOP_3)) & 0xffff0000 ) >> 16)
+#define GET_RG_PHASE_35M (((REG32(ADR_RF_D_CAL_TOP_4)) & 0xffff0000 ) >> 16)
+#define GET_RO_RX_IQ_THETA (((REG32(ADR_RF_D_CAL_TOP_5)) & 0x0000001f ) >> 0)
+#define GET_RO_RX_IQ_ALPHA (((REG32(ADR_RF_D_CAL_TOP_5)) & 0x00001f00 ) >> 8)
+#define GET_RO_TX_IQ_THETA (((REG32(ADR_RF_D_CAL_TOP_5)) & 0x001f0000 ) >> 16)
+#define GET_RO_TX_IQ_ALPHA (((REG32(ADR_RF_D_CAL_TOP_5)) & 0x1f000000 ) >> 24)
+#define GET_RG_RX_RCCAL_TARG (((REG32(ADR_RF_D_CAL_TOP_6)) & 0x000003ff ) >> 0)
+#define GET_RG_RX_DC_POLAR_INV (((REG32(ADR_RF_D_CAL_TOP_6)) & 0x00001000 ) >> 12)
+#define GET_RG_RCCAL_POLAR_INV (((REG32(ADR_RF_D_CAL_TOP_6)) & 0x00002000 ) >> 13)
+#define GET_RG_RX_DC_RESOLUTION (((REG32(ADR_RF_D_CAL_TOP_6)) & 0x00004000 ) >> 14)
+#define GET_RG_RX_RCCAL_40M_TARG (((REG32(ADR_RF_D_CAL_TOP_6)) & 0x03ff0000 ) >> 16)
+#define GET_RO_SPECTRUM_IQ_PWR_39_32 (((REG32(ADR_RF_D_CAL_TOP_7)) & 0x000000ff ) >> 0)
+#define GET_RG_SPECTRUM_LO_FIX (((REG32(ADR_RF_D_CAL_TOP_7)) & 0x00010000 ) >> 16)
+#define GET_RG_SPECTRUM_PWR_UPDATE (((REG32(ADR_RF_D_CAL_TOP_7)) & 0x00100000 ) >> 20)
+#define GET_RO_SPECTRUM_IQ_PWR_31_0 (((REG32(ADR_RF_D_CAL_TOP_8)) & 0xffffffff ) >> 0)
+#define GET_RG_PROC_DELAY (((REG32(ADR_RF_D_CAL_TOP_9)) & 0x00000007 ) >> 0)
+#define GET_RG_PRE_DC_POLA_INV (((REG32(ADR_RF_D_CAL_TOP_9)) & 0x00000010 ) >> 4)
+#define GET_RG_RX_PRE_DC_RESOLUTION (((REG32(ADR_RF_D_CAL_TOP_9)) & 0x00000020 ) >> 5)
+#define GET_RG_PRE_DC_AUTO (((REG32(ADR_RF_D_CAL_TOP_9)) & 0x00000040 ) >> 6)
+#define GET_RG_FILTER_AVERAGE_EN (((REG32(ADR_RF_D_CAL_TOP_9)) & 0x00000080 ) >> 7)
+#define GET_RG_PHASE_RND_EN (((REG32(ADR_RF_D_CAL_TOP_9)) & 0x00000100 ) >> 8)
+#define GET_RG_RCCAL_DATA_SEL (((REG32(ADR_RF_D_CAL_TOP_9)) & 0x00000200 ) >> 9)
+#define GET_RG_HS3W_TX_RF_GAIN (((REG32(ADR_HS3W_CTRL1)) & 0x0000007f ) >> 0)
+#define GET_RG_HS3W_PGAGC (((REG32(ADR_HS3W_CTRL1)) & 0x00000f00 ) >> 8)
+#define GET_RG_HS3W_RFGC (((REG32(ADR_HS3W_CTRL1)) & 0x00003000 ) >> 12)
+#define GET_RG_HS3W_RXAGC (((REG32(ADR_HS3W_CTRL1)) & 0x00004000 ) >> 14)
+#define GET_RG_HS3W_RF_PHY_MODE (((REG32(ADR_HS3W_CTRL1)) & 0x00070000 ) >> 16)
+#define GET_RG_HS3W_MANUAL (((REG32(ADR_HS3W_CTRL1)) & 0x00100000 ) >> 20)
+#define GET_RG_HS3W_COMM_DATA (((REG32(ADR_HS3W_CTRL1)) & 0x07000000 ) >> 24)
+#define GET_RG_HS3W_START_SENT (((REG32(ADR_HS3W_CTRL1)) & 0x10000000 ) >> 28)
+#define GET_RG_HS3W_SX_RFCTRL_CH_INT_10_8 (((REG32(ADR_HS3W_CTRL2)) & 0x00000007 ) >> 0)
+#define GET_RG_HS3W_SX_RFCH_MAP_EN_INT (((REG32(ADR_HS3W_CTRL2)) & 0x00000010 ) >> 4)
+#define GET_RG_HS3W_SX_CHANNEL_INT (((REG32(ADR_HS3W_CTRL2)) & 0x0007f800 ) >> 11)
+#define GET_RG_HS3W_SX_RFCTRL_F_INT (((REG32(ADR_HS3W_CTRL3)) & 0x00ffffff ) >> 0)
+#define GET_RG_HS3W_SX_RFCTRL_CH_INT_7_0 (((REG32(ADR_HS3W_CTRL3)) & 0xff000000 ) >> 24)
+#define GET_RG_MODE_BY_HS_3WIRE (((REG32(ADR_RF_D_MODE_CTRL)) & 0x00000001 ) >> 0)
+#define GET_RG_MODE_BY_PHY (((REG32(ADR_RF_D_MODE_CTRL)) & 0x00000010 ) >> 4)
+#define GET_RG_MODE_BY_HWPIN (((REG32(ADR_RF_D_MODE_CTRL)) & 0x00000100 ) >> 8)
+#define GET_RO_RF_PHY_MODE (((REG32(ADR_RF_D_MODE_CTRL)) & 0x00070000 ) >> 16)
+#define GET_RO_HS3W_SX_CHANNEL (((REG32(ADR_HS3W_READ_OUT_1)) & 0x000000ff ) >> 0)
+#define GET_RO_HS3W_SX_RFCH_MAP_EN (((REG32(ADR_HS3W_READ_OUT_1)) & 0x00000100 ) >> 8)
+#define GET_RO_GAIN_TX (((REG32(ADR_HS3W_READ_OUT_1)) & 0x007f0000 ) >> 16)
+#define GET_RO_ABBPGA (((REG32(ADR_HS3W_READ_OUT_1)) & 0x0f000000 ) >> 24)
+#define GET_RO_RFPGA (((REG32(ADR_HS3W_READ_OUT_1)) & 0x30000000 ) >> 28)
+#define GET_RO_DA_RX_AGC (((REG32(ADR_HS3W_READ_OUT_1)) & 0x80000000 ) >> 31)
+#define GET_RO_HS3W_SX_RFCTRL_CH (((REG32(ADR_HS3W_READ_OUT_2_)) & 0x000007ff ) >> 0)
+#define GET_RO_HS3W_SX_RFCTRL_F (((REG32(ADR_HS3W_READ_OUT_3)) & 0x00ffffff ) >> 0)
+#define GET_RO_REFREG_KHZ_OUT (((REG32(ADR_SX_LOCK_FREQ_1)) & 0x007fffff ) >> 0)
+#define GET_RO_RF_CH_FREQ (((REG32(ADR_SX_LOCK_FREQ_2)) & 0x00001fff ) >> 0)
+#define GET_RO_DC_CAL_Q (((REG32(ADR_RX_DC_CAL_RESULT)) & 0x0000007f ) >> 0)
+#define GET_RO_DC_CAL_I (((REG32(ADR_RX_DC_CAL_RESULT)) & 0x007f0000 ) >> 16)
+#define GET_RG_AUDIO_VOLUME (((REG32(ADR_AUDIO_CTRL_REG)) & 0x000003ff ) >> 0)
+#define GET_RG_AUDIO_ALPHA (((REG32(ADR_AUDIO_CTRL_REG)) & 0x00003000 ) >> 12)
+#define GET_RG_AUDIO_FIL_EN (((REG32(ADR_AUDIO_CTRL_REG)) & 0x00010000 ) >> 16)
+#define GET_RG_IOT_ADC_SIGN_SWAP (((REG32(ADR_AUDIO_CTRL_REG)) & 0x01000000 ) >> 24)
+#define GET_RG_IOT_ADC_EDGE_SEL (((REG32(ADR_AUDIO_CTRL_REG)) & 0x02000000 ) >> 25)
+#define GET_RG_BYPASS_AUDIO_LWDF (((REG32(ADR_AUDIO_CTRL_REG)) & 0x10000000 ) >> 28)
+#define GET_RG_PDM_EDGE_SEL (((REG32(ADR_AUDIO_CTRL_REG)) & 0x20000000 ) >> 29)
+#define GET_RG_AUDIO_TYPE (((REG32(ADR_AUDIO_CTRL_REG)) & 0x40000000 ) >> 30)
+#define GET_RG_PDM_LOW_LEVEL (((REG32(ADR_AUDIO_PDM_REG)) & 0x00003fff ) >> 0)
+#define GET_RG_PDM_HIGH_LEVEL (((REG32(ADR_AUDIO_PDM_REG)) & 0x3fff0000 ) >> 16)
+#define GET_RG_5G_TX_BAND_F1 (((REG32(ADR_RF_5G_TX_PARTITION_BAND1)) & 0x00001fff ) >> 0)
+#define GET_RG_5G_TX_BAND_F0 (((REG32(ADR_RF_5G_TX_PARTITION_BAND1)) & 0x1fff0000 ) >> 16)
+#define GET_RG_5G_TX_BAND_F2 (((REG32(ADR_RF_5G_TX_PARTITION_BAND2)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5100_020_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REG0)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5100_040_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REG0)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5100_060_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REG1)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5100_080_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REG1)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5100_0A0_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REG2)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5100_0C0_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REG2)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5100_0D0_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REG3)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5100_0E0_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REG3)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5100_0F0_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REG4)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5100_100_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REG4)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5100_110_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REG5)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5100_120_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REG5)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5100_130_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REG6)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5100_140_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REG6)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5100_150_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REG7)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5100_160_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REG7)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5100_170_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REG8)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5100_180_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REG8)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5100_190_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REG9)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5100_1A0_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REG9)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5100_1B0_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REGA)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5100_1C0_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REGA)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5100_1D0_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REGB)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5100_1E0_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REGB)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5100_1F0_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REGC)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5100_200_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REGC)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5100_020_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REG0)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5100_040_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REG0)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5100_060_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REG1)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5100_080_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REG1)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5100_0A0_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REG2)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5100_0C0_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REG2)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5100_0D0_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REG3)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5100_0E0_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REG3)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5100_0F0_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REG4)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5100_100_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REG4)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5100_110_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REG5)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5100_120_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REG5)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5100_130_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REG6)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5100_140_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REG6)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5100_150_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REG7)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5100_160_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REG7)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5100_170_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REG8)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5100_180_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REG8)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5100_190_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REG9)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5100_1A0_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REG9)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5100_1B0_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REGA)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5100_1C0_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REGA)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5100_1D0_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REGB)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5100_1E0_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REGB)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5100_1F0_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REGC)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5100_200_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REGC)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5500_020_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REG0)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5500_040_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REG0)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5500_060_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REG1)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5500_080_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REG1)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5500_0A0_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REG2)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5500_0C0_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REG2)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5500_0D0_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REG3)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5500_0E0_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REG3)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5500_0F0_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REG4)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5500_100_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REG4)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5500_110_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REG5)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5500_120_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REG5)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5500_130_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REG6)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5500_140_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REG6)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5500_150_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REG7)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5500_160_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REG7)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5500_170_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REG8)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5500_180_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REG8)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5500_190_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REG9)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5500_1A0_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REG9)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5500_1B0_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REGA)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5500_1C0_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REGA)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5500_1D0_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REGB)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5500_1E0_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REGB)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5500_1F0_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REGC)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5500_200_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REGC)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5500_020_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REG0)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5500_040_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REG0)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5500_060_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REG1)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5500_080_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REG1)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5500_0A0_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REG2)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5500_0C0_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REG2)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5500_0D0_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REG3)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5500_0E0_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REG3)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5500_0F0_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REG4)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5500_100_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REG4)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5500_110_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REG5)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5500_120_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REG5)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5500_130_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REG6)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5500_140_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REG6)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5500_150_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REG7)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5500_160_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REG7)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5500_170_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REG8)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5500_180_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REG8)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5500_190_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REG9)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5500_1A0_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REG9)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5500_1B0_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REGA)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5500_1C0_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REGA)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5500_1D0_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REGB)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5500_1E0_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REGB)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5500_1F0_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REGC)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5500_200_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REGC)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5700_020_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REG0)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5700_040_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REG0)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5700_060_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REG1)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5700_080_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REG1)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5700_0A0_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REG2)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5700_0C0_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REG2)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5700_0D0_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REG3)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5700_0E0_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REG3)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5700_0F0_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REG4)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5700_100_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REG4)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5700_110_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REG5)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5700_120_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REG5)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5700_130_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REG6)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5700_140_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REG6)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5700_150_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REG7)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5700_160_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REG7)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5700_170_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REG8)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5700_180_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REG8)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5700_190_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REG9)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5700_1A0_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REG9)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5700_1B0_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REGA)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5700_1C0_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REGA)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5700_1D0_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REGB)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5700_1E0_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REGB)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5700_1F0_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REGC)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5700_200_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REGC)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5700_020_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REG0)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5700_040_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REG0)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5700_060_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REG1)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5700_080_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REG1)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5700_0A0_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REG2)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5700_0C0_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REG2)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5700_0D0_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REG3)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5700_0E0_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REG3)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5700_0F0_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REG4)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5700_100_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REG4)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5700_110_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REG5)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5700_120_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REG5)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5700_130_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REG6)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5700_140_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REG6)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5700_150_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REG7)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5700_160_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REG7)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5700_170_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REG8)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5700_180_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REG8)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5700_190_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REG9)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5700_1A0_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REG9)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5700_1B0_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REGA)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5700_1C0_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REGA)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5700_1D0_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REGB)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5700_1E0_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REGB)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5700_1F0_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REGC)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5700_200_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REGC)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5900_020_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REG0)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5900_040_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REG0)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5900_060_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REG1)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5900_080_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REG1)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5900_0A0_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REG2)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5900_0C0_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REG2)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5900_0D0_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REG3)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5900_0E0_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REG3)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5900_0F0_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REG4)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5900_100_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REG4)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5900_110_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REG5)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5900_120_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REG5)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5900_130_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REG6)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5900_140_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REG6)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5900_150_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REG7)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5900_160_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REG7)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5900_170_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REG8)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5900_180_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REG8)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5900_190_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REG9)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5900_1A0_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REG9)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5900_1B0_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REGA)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5900_1C0_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REGA)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5900_1D0_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REGB)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5900_1E0_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REGB)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5900_1F0_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REGC)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_5900_200_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REGC)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_5900_020_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REG0)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5900_040_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REG0)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5900_060_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REG1)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5900_080_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REG1)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5900_0A0_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REG2)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5900_0C0_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REG2)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5900_0D0_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REG3)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5900_0E0_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REG3)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5900_0F0_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REG4)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5900_100_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REG4)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5900_110_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REG5)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5900_120_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REG5)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5900_130_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REG6)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5900_140_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REG6)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5900_150_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REG7)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5900_160_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REG7)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5900_170_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REG8)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5900_180_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REG8)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5900_190_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REG9)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5900_1A0_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REG9)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5900_1B0_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REGA)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5900_1C0_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REGA)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5900_1D0_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REGB)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5900_1E0_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REGB)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_5900_1F0_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REGC)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_5900_200_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REGC)) & 0x1fff0000 ) >> 16)
+#define GET_RG_TONE_SEL (((REG32(ADR_WIFI_PADPD_CAL_TONEGEN_REG)) & 0x00000003 ) >> 0)
+#define GET_RG_TONE_1_RATE (((REG32(ADR_WIFI_PADPD_CAL_TONEGEN_REG)) & 0xffff0000 ) >> 16)
+#define GET_RG_RX_PADPD_EN (((REG32(ADR_WIFI_PADPD_CAL_RX_PADPD_REG)) & 0x00000001 ) >> 0)
+#define GET_RG_RX_PADPD_LEAKY_FACTOR (((REG32(ADR_WIFI_PADPD_CAL_RX_PADPD_REG)) & 0x00000070 ) >> 4)
+#define GET_RG_RX_PADPD_LATCH (((REG32(ADR_WIFI_PADPD_CAL_RX_PADPD_REG)) & 0x00000100 ) >> 8)
+#define GET_RG_RX_PADPD_DATA_SEL (((REG32(ADR_WIFI_PADPD_CAL_RX_PADPD_REG)) & 0x00001000 ) >> 12)
+#define GET_RG_RX_PADPD_TONE_SEL (((REG32(ADR_WIFI_PADPD_CAL_RX_PADPD_REG)) & 0x00002000 ) >> 13)
+#define GET_RG_RX_PADPD_RATE (((REG32(ADR_WIFI_PADPD_CAL_RX_PADPD_REG)) & 0xffff0000 ) >> 16)
+#define GET_RO_RX_PHI (((REG32(ADR_WIFI_PADPD_CAL_RX_RO)) & 0x00001fff ) >> 0)
+#define GET_RO_RX_AMP (((REG32(ADR_WIFI_PADPD_CAL_RX_RO)) & 0x01ff0000 ) >> 16)
+#define GET_RG_CFR_GAIN (((REG32(ADR_WIFI_PADPD_CFR)) & 0x000003ff ) >> 0)
+#define GET_RG_CFR_PEAK (((REG32(ADR_WIFI_PADPD_CFR)) & 0x03ff0000 ) >> 16)
+#define GET_RG_CFR_EN (((REG32(ADR_WIFI_PADPD_CFR)) & 0x80000000 ) >> 31)
+#define GET_RG_RX_PADPD_DC_RM_LEAKY_FACTOR (((REG32(ADR_WIFI_PADPD_DC_RM)) & 0x00000007 ) >> 0)
+#define GET_RG_RX_PADPD_DC_RM_BYP (((REG32(ADR_WIFI_PADPD_DC_RM)) & 0x00000010 ) >> 4)
+#define GET_RG_TXIQ_CLP_THD_I (((REG32(ADR_WIFI_PADPD_TXIQ_CLIP_REG)) & 0x000003ff ) >> 0)
+#define GET_RG_TXIQ_CLP_THD_Q (((REG32(ADR_WIFI_PADPD_TXIQ_CLIP_REG)) & 0x03ff0000 ) >> 16)
+#define GET_RG_TX_SCALE (((REG32(ADR_WIFI_PADPD_TXIQ_CONTROL_REG)) & 0x000000ff ) >> 0)
+#define GET_RG_TX_IQ_SWP (((REG32(ADR_WIFI_PADPD_TXIQ_CONTROL_REG)) & 0x00010000 ) >> 16)
+#define GET_RG_TX_BB_SCALE_MANUAL (((REG32(ADR_WIFI_PADPD_TXIQ_CONTROL_REG)) & 0x00100000 ) >> 20)
+#define GET_RG_TX_IQ_SRC (((REG32(ADR_WIFI_PADPD_TXIQ_CONTROL_REG)) & 0x03000000 ) >> 24)
+#define GET_RG_TX_I_DC (((REG32(ADR_WIFI_PADPD_TXIQ_DPD_DC_REG)) & 0x000003ff ) >> 0)
+#define GET_RG_TX_Q_DC (((REG32(ADR_WIFI_PADPD_TXIQ_DPD_DC_REG)) & 0x03ff0000 ) >> 16)
+#define GET_RG_TX_I_OFFSET (((REG32(ADR_WIFI_PADPD_TXIQ_DC_OFFSET_REG)) & 0x00ff0000 ) >> 16)
+#define GET_RG_TX_Q_OFFSET (((REG32(ADR_WIFI_PADPD_TXIQ_DC_OFFSET_REG)) & 0xff000000 ) >> 24)
+#define GET_RG_DPD_AM_EN (((REG32(ADR_WIFI_PADPD_2G_CONTROL_REG)) & 0x00000001 ) >> 0)
+#define GET_RG_DPD_PM_EN (((REG32(ADR_WIFI_PADPD_2G_CONTROL_REG)) & 0x00000002 ) >> 1)
+#define GET_RG_DPD_PM_AMSEL (((REG32(ADR_WIFI_PADPD_2G_CONTROL_REG)) & 0x00000004 ) >> 2)
+#define GET_RG_DPD_020_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REG0)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_040_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REG0)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_060_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REG1)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_080_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REG1)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_0A0_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REG2)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_0C0_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REG2)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_0D0_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REG3)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_0E0_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REG3)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_0F0_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REG4)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_100_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REG4)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_110_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REG5)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_120_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REG5)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_130_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REG6)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_140_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REG6)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_150_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REG7)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_160_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REG7)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_170_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REG8)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_180_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REG8)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_190_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REG9)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_1A0_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REG9)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_1B0_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REGA)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_1C0_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REGA)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_1D0_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REGB)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_1E0_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REGB)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_1F0_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REGC)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_200_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REGC)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_020_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REG0)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_040_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REG0)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_060_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REG1)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_080_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REG1)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_0A0_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REG2)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_0C0_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REG2)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_0D0_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REG3)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_0E0_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REG3)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_0F0_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REG4)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_100_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REG4)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_110_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REG5)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_120_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REG5)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_130_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REG6)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_140_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REG6)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_150_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REG7)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_160_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REG7)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_170_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REG8)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_180_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REG8)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_190_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REG9)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_1A0_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REG9)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_1B0_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REGA)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_1C0_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REGA)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_1D0_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REGB)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_1E0_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REGB)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_1F0_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REGC)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_200_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REGC)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_BB_SCALE_5900 (((REG32(ADR_WIFI_PADPD_5G_BB_GAIN_REG)) & 0x000000ff ) >> 0)
+#define GET_RG_DPD_BB_SCALE_5700 (((REG32(ADR_WIFI_PADPD_5G_BB_GAIN_REG)) & 0x0000ff00 ) >> 8)
+#define GET_RG_DPD_BB_SCALE_5500 (((REG32(ADR_WIFI_PADPD_5G_BB_GAIN_REG)) & 0x00ff0000 ) >> 16)
+#define GET_RG_DPD_BB_SCALE_5100 (((REG32(ADR_WIFI_PADPD_5G_BB_GAIN_REG)) & 0xff000000 ) >> 24)
+#define GET_RG_DPD_BB_SCALE_2500 (((REG32(ADR_WIFI_PADPD_2G_BB_GAIN_REG)) & 0x000000ff ) >> 0)
+#define GET_RG_TX_SCALE_11B (((REG32(ADR_WIFI_PADPD_TX_GAIN_0P5DB_REG)) & 0x000000ff ) >> 0)
+#define GET_RG_TX_SCALE_11B_P0D5 (((REG32(ADR_WIFI_PADPD_TX_GAIN_0P5DB_REG)) & 0x0000ff00 ) >> 8)
+#define GET_RG_TX_SCALE_11G (((REG32(ADR_WIFI_PADPD_TX_GAIN_0P5DB_REG)) & 0x00ff0000 ) >> 16)
+#define GET_RG_TX_SCALE_11G_P0D5 (((REG32(ADR_WIFI_PADPD_TX_GAIN_0P5DB_REG)) & 0xff000000 ) >> 24)
+#define GET_RG_HS5W_M_MD_EN (((REG32(ADR_HS5W_MD_EN)) & 0x00000001 ) >> 0)
+#define GET_RG_HS5W_M_MAN (((REG32(ADR_HS5W_MAN)) & 0x00000001 ) >> 0)
+#define GET_RG_HS5W_M_CMD6_EN (((REG32(ADR_HS5W_MAN)) & 0x02000000 ) >> 25)
+#define GET_RG_HS5W_M_CMD5_EN (((REG32(ADR_HS5W_MAN)) & 0x04000000 ) >> 26)
+#define GET_RG_HS5W_M_CMD4_EN (((REG32(ADR_HS5W_MAN)) & 0x08000000 ) >> 27)
+#define GET_RG_HS5W_M_CMD3_EN (((REG32(ADR_HS5W_MAN)) & 0x10000000 ) >> 28)
+#define GET_RG_HS5W_M_CMD2_EN (((REG32(ADR_HS5W_MAN)) & 0x20000000 ) >> 29)
+#define GET_RG_HS5W_M_CMD1_EN (((REG32(ADR_HS5W_MAN)) & 0x40000000 ) >> 30)
+#define GET_RG_HS5W_M_CMD0_EN (((REG32(ADR_HS5W_MAN)) & 0x80000000 ) >> 31)
+#define GET_RG_HS5W_M_RF_PHY_MODE (((REG32(ADR_HS5W_MAN_SET_ADD0)) & 0x00000007 ) >> 0)
+#define GET_RG_HS5W_M_CAL_INDEX (((REG32(ADR_HS5W_MAN_SET_ADD1)) & 0x0000001f ) >> 0)
+#define GET_RG_HS5W_M_PGAGC (((REG32(ADR_HS5W_MAN_SET_ADD2)) & 0x0000000f ) >> 0)
+#define GET_RG_HS5W_M_RFGC (((REG32(ADR_HS5W_MAN_SET_ADD2)) & 0x00000030 ) >> 4)
+#define GET_RG_HS5W_M_TXPWRLVL (((REG32(ADR_HS5W_MAN_SET_ADD3)) & 0x0000003f ) >> 0)
+#define GET_RG_HS5W_M_SX_RFCTRL_CH (((REG32(ADR_HS5W_MAN_SET_ADD4_CH)) & 0x000007ff ) >> 0)
+#define GET_RG_HS5W_M_SX5GB_RFCTRL_CH (((REG32(ADR_HS5W_MAN_SET_ADD4_CH_5GB)) & 0x000007ff ) >> 0)
+#define GET_RG_HS5W_M_SX_RFCTRL_F (((REG32(ADR_HS5W_MAN_SET_ADD4_F)) & 0x00ffffff ) >> 0)
+#define GET_RG_HS5W_M_SX_RFCH_MAP_EN (((REG32(ADR_HS5W_MAN_SET_ADD4_F)) & 0x80000000 ) >> 31)
+#define GET_RG_HS5W_M_SX5GB_RFCTRL_F (((REG32(ADR_HS5W_MAN_SET_ADD4_F_5GB)) & 0x00ffffff ) >> 0)
+#define GET_RG_HS5W_M_SX5GB_RFCH_MAP_EN (((REG32(ADR_HS5W_MAN_SET_ADD4_F_5GB)) & 0x80000000 ) >> 31)
+#define GET_RG_HS5W_M_SX_CHANNEL (((REG32(ADR_HS5W_MAN_SET_ADD5)) & 0x000000ff ) >> 0)
+#define GET_RG_HS5W_M_SX5GB_CHANNEL (((REG32(ADR_HS5W_MAN_SET_ADD5_5GB)) & 0x000000ff ) >> 0)
+#define GET_RG_HS5W_M_PHY_BW (((REG32(ADR_HS5W_MAN_SET_ADD6)) & 0x00000003 ) >> 0)
+#define GET_RG_RESERVED_DPD (((REG32(ADR_WIFI_PADPD_RESERVED_REG)) & 0xffffffff ) >> 0)
+#define GET_RG_XO_LDO_LEVEL (((REG32(ADR_PMU_REG_1)) & 0x00000007 ) >> 0)
+#define GET_RG_EN_LDO_XO_IQUP (((REG32(ADR_PMU_REG_1)) & 0x00000010 ) >> 4)
+#define GET_RG_EN_LDO_XO_BYP (((REG32(ADR_PMU_REG_1)) & 0x00000020 ) >> 5)
+#define GET_RG_EN_DLDO_BYP (((REG32(ADR_PMU_REG_1)) & 0x00000040 ) >> 6)
+#define GET_RG_EN_DLDO_HALF_IQ (((REG32(ADR_PMU_REG_1)) & 0x00000080 ) >> 7)
+#define GET_RG_XO_CBANKI (((REG32(ADR_PMU_REG_1)) & 0x0001ff00 ) >> 8)
+#define GET_RG_XO_CBANKO (((REG32(ADR_PMU_REG_1)) & 0x03fe0000 ) >> 17)
+#define GET_RG_EN_FDB (((REG32(ADR_PMU_REG_1)) & 0x04000000 ) >> 26)
+#define GET_RG_FDB_BYPASS (((REG32(ADR_PMU_REG_1)) & 0x08000000 ) >> 27)
+#define GET_RG_FDB_DUTY_LTH (((REG32(ADR_PMU_REG_1)) & 0x30000000 ) >> 28)
+#define GET_RG_EN_XOTEST (((REG32(ADR_PMU_REG_1)) & 0x40000000 ) >> 30)
+#define GET_RG_HW_WAKE_XOSC (((REG32(ADR_PMU_REG_1)) & 0x80000000 ) >> 31)
+#define GET_RG_EN_FDB_DCC_MUAL (((REG32(ADR_PMU_REG_2)) & 0x00000001 ) >> 0)
+#define GET_RG_EN_FDB_DELAYC_MUAL (((REG32(ADR_PMU_REG_2)) & 0x00000002 ) >> 1)
+#define GET_RG_EN_FDB_DELAYF_MUAL (((REG32(ADR_PMU_REG_2)) & 0x00000004 ) >> 2)
+#define GET_RG_EN_FDB_PHASESWAP_MUAL (((REG32(ADR_PMU_REG_2)) & 0x00000008 ) >> 3)
+#define GET_RG_FDB_PHASESWAP_MUAL (((REG32(ADR_PMU_REG_2)) & 0x00000010 ) >> 4)
+#define GET_RG_CLOCK_BF_MUAL (((REG32(ADR_PMU_REG_2)) & 0x00000020 ) >> 5)
+#define GET_RG_FDB_CDELAY_MUAL (((REG32(ADR_PMU_REG_2)) & 0x00000f00 ) >> 8)
+#define GET_RG_FDB_FDELAY_MUAL (((REG32(ADR_PMU_REG_2)) & 0x0000f000 ) >> 12)
+#define GET_RG_XO_TIMMER (((REG32(ADR_PMU_REG_2)) & 0x003f0000 ) >> 16)
+#define GET_RG_DPL_SETTLING_TIMMER (((REG32(ADR_PMU_REG_2)) & 0x00c00000 ) >> 22)
+#define GET_RG_FDB_RDELAYF (((REG32(ADR_PMU_REG_2)) & 0x03000000 ) >> 24)
+#define GET_RG_FDB_RDELAYS (((REG32(ADR_PMU_REG_2)) & 0x0c000000 ) >> 26)
+#define GET_RG_FDB_RECAL_TIMMER (((REG32(ADR_PMU_REG_2)) & 0x30000000 ) >> 28)
+#define GET_RG_EN_FDB_RECAL (((REG32(ADR_PMU_REG_2)) & 0x40000000 ) >> 30)
+#define GET_RG_LOAD_RFTABLE_RDY (((REG32(ADR_PMU_REG_2)) & 0x80000000 ) >> 31)
+#define GET_RG_DCDC_MODE (((REG32(ADR_PMU_REG_3)) & 0x00000001 ) >> 0)
+#define GET_RG_DLDO_LEVEL (((REG32(ADR_PMU_REG_3)) & 0x0000000e ) >> 1)
+#define GET_RG_BUCK_LEVEL (((REG32(ADR_PMU_REG_3)) & 0x000000f0 ) >> 4)
+#define GET_RG_DLDO_BOOST_IQ (((REG32(ADR_PMU_REG_3)) & 0x00000100 ) >> 8)
+#define GET_RG_BUCK_EN_PSM (((REG32(ADR_PMU_REG_3)) & 0x00000200 ) >> 9)
+#define GET_RG_BUCK_PSM_VTH (((REG32(ADR_PMU_REG_3)) & 0x00000400 ) >> 10)
+#define GET_RG_BUCK_VREF_SEL (((REG32(ADR_PMU_REG_3)) & 0x00000800 ) >> 11)
+#define GET_RG_LDO_LEVEL_EFUSE (((REG32(ADR_PMU_REG_3)) & 0x00007000 ) >> 12)
+#define GET_RG_EN_LDO_EFUSE (((REG32(ADR_PMU_REG_3)) & 0x00010000 ) >> 16)
+#define GET_RG_DCDC_PULLLOW_CON (((REG32(ADR_PMU_REG_3)) & 0x00040000 ) >> 18)
+#define GET_RG_DCDC_RES2_CON (((REG32(ADR_PMU_REG_3)) & 0x00080000 ) >> 19)
+#define GET_RG_DCDC_RES_CON (((REG32(ADR_PMU_REG_3)) & 0x00100000 ) >> 20)
+#define GET_RG_RTC_RS1 (((REG32(ADR_PMU_REG_3)) & 0x00200000 ) >> 21)
+#define GET_RG_RTC_RS2 (((REG32(ADR_PMU_REG_3)) & 0x00400000 ) >> 22)
+#define GET_RG_DCDC_CLK (((REG32(ADR_PMU_REG_3)) & 0x0f000000 ) >> 24)
+#define GET_RG_BUCK_RCZERO (((REG32(ADR_PMU_REG_3)) & 0x10000000 ) >> 28)
+#define GET_RG_BUCK_SLOP (((REG32(ADR_PMU_REG_3)) & 0x60000000 ) >> 29)
+#define GET_RG_RTC_OFFSET (((REG32(ADR_PMU_REG_4)) & 0x000000ff ) >> 0)
+#define GET_RG_RTC_CAL_TARGET_COUNT (((REG32(ADR_PMU_REG_4)) & 0x000fff00 ) >> 8)
+#define GET_RG_RTC_OSC_RES_SW_MANUAL (((REG32(ADR_PMU_REG_4)) & 0x3ff00000 ) >> 20)
+#define GET_RG_RTC_CAL_MODE (((REG32(ADR_PMU_REG_4)) & 0x40000000 ) >> 30)
+#define GET_RG_SEL_DPLL_CLK (((REG32(ADR_PMU_REG_4)) & 0x80000000 ) >> 31)
+#define GET_RG_RTC_OSC_RES_SW_MANUAL_EN (((REG32(ADR_PMU_REG_5)) & 0x00000001 ) >> 0)
+#define GET_RG_EN_RTC_CAL (((REG32(ADR_PMU_REG_5)) & 0x00000002 ) >> 1)
+#define GET_RO_FDB_CDELAY (((REG32(ADR_PMU_REG_6)) & 0x0000000f ) >> 0)
+#define GET_RO_FDB_FDELAY (((REG32(ADR_PMU_REG_6)) & 0x000000f0 ) >> 4)
+#define GET_RO_FDB_PHASESWAP (((REG32(ADR_PMU_REG_6)) & 0x00000100 ) >> 8)
+#define GET_RO_XO_RDY (((REG32(ADR_PMU_REG_6)) & 0x00000200 ) >> 9)
+#define GET_RO_RTC_OSC_CAL_RES_RDY (((REG32(ADR_PMU_REG_6)) & 0x00000400 ) >> 10)
+#define GET_RO_RTC_OSC_RES_SW (((REG32(ADR_PMU_REG_6)) & 0x001ff800 ) >> 11)
+#define GET_RG_PMU_ENTER_SLEEP_MODE (((REG32(ADR_PMU_SLEEP_REG_1)) & 0x00000001 ) >> 0)
+#define GET_RG_SLEEP_METHOD (((REG32(ADR_PMU_SLEEP_REG_1)) & 0x00000002 ) >> 1)
+#define GET_RG_INT_PMU_MASK (((REG32(ADR_PMU_SLEEP_REG_1)) & 0x00000004 ) >> 2)
+#define GET_RG_SLEEP_WAKE_CNT (((REG32(ADR_PMU_SLEEP_REG_2)) & 0xffffffff ) >> 0)
+#define GET_RG_SEC_CNT_VALUE (((REG32(ADR_PMU_RTC_REG_0)) & 0x00007fff ) >> 0)
+#define GET_RG_RTC_EN (((REG32(ADR_PMU_RTC_REG_0)) & 0x00008000 ) >> 15)
+#define GET_RO_RTC_TICK_CNT (((REG32(ADR_PMU_RTC_REG_0)) & 0x7fff0000 ) >> 16)
+#define GET_RG_RTC_INT_SEC_MASK (((REG32(ADR_PMU_RTC_REG_1)) & 0x00000001 ) >> 0)
+#define GET_RG_RTC_INT_ALARM_MASK (((REG32(ADR_PMU_RTC_REG_1)) & 0x00000002 ) >> 1)
+#define GET_RO_PMU_WAKE_TRIG_EVENT (((REG32(ADR_PMU_RTC_REG_1)) & 0x00007000 ) >> 12)
+#define GET_RO_RTC_INT_SEC (((REG32(ADR_PMU_RTC_REG_1)) & 0x00010000 ) >> 16)
+#define GET_RO_RTC_INT_ALARM (((REG32(ADR_PMU_RTC_REG_1)) & 0x00020000 ) >> 17)
+#define GET_RG_RTC_SEC_START_CNT (((REG32(ADR_PMU_RTC_REG_2)) & 0xffffffff ) >> 0)
+#define GET_RG_RTC_SEC_ALARM_VALUE (((REG32(ADR_PMU_RTC_REG_3)) & 0xffffffff ) >> 0)
+#define GET_RG_FPGA_CLK_REF_40M_EN (((REG32(ADR_PMU_CTRL_REG)) & 0x00000001 ) >> 0)
+#define GET_RG_CLK_RTC_SW (((REG32(ADR_PMU_CTRL_REG)) & 0x00000002 ) >> 1)
+#define GET_RG_PHY_RST_N (((REG32(ADR_PMU_CTRL_REG)) & 0x00000010 ) >> 4)
+#define GET_RO_PMU_STATE (((REG32(ADR_PMU_STATE_REG)) & 0x00000007 ) >> 0)
+#define GET_RO_AD_VBAT_OK (((REG32(ADR_PMU_STATE_REG)) & 0x00000010 ) >> 4)
+#define GET_RG_DP_LDO_LEVEL (((REG32(ADR_PMU_DPLL_REG_0)) & 0x00000007 ) >> 0)
+#define GET_RG_EN_LDO_DP_BYP (((REG32(ADR_PMU_DPLL_REG_0)) & 0x00000008 ) >> 3)
+#define GET_RG_DP_AUTOMAP_EN (((REG32(ADR_PMU_DPLL_REG_0)) & 0x00000020 ) >> 5)
+#define GET_RG_EN_ADC_320M (((REG32(ADR_PMU_DPLL_REG_0)) & 0x00000080 ) >> 7)
+#define GET_RG_EN_IOTADC_160M (((REG32(ADR_PMU_DPLL_REG_0)) & 0x00000100 ) >> 8)
+#define GET_RG_EN_MAC_80M (((REG32(ADR_PMU_DPLL_REG_0)) & 0x00000200 ) >> 9)
+#define GET_RG_EN_MAC_96M (((REG32(ADR_PMU_DPLL_REG_0)) & 0x00000400 ) >> 10)
+#define GET_RG_EN_MAC_120M (((REG32(ADR_PMU_DPLL_REG_0)) & 0x00000800 ) >> 11)
+#define GET_RG_EN_PHY_80M (((REG32(ADR_PMU_DPLL_REG_0)) & 0x00001000 ) >> 12)
+#define GET_RG_EN_PHY_160M (((REG32(ADR_PMU_DPLL_REG_0)) & 0x00002000 ) >> 13)
+#define GET_RG_EN_PHY_320M (((REG32(ADR_PMU_DPLL_REG_0)) & 0x00004000 ) >> 14)
+#define GET_RG_EN_MAC_160M (((REG32(ADR_PMU_DPLL_REG_0)) & 0x00008000 ) >> 15)
+#define GET_RG_DP_XTAL_FREQ (((REG32(ADR_PMU_DPLL_REG_0)) & 0x000f0000 ) >> 16)
+#define GET_RG_DP_BBPLL_PD (((REG32(ADR_PMU_DPLL_REG_1)) & 0x00000001 ) >> 0)
+#define GET_RG_DP_BBPLL_BP (((REG32(ADR_PMU_DPLL_REG_1)) & 0x00000002 ) >> 1)
+#define GET_RG_EN_DP_MANUAL (((REG32(ADR_PMU_DPLL_REG_1)) & 0x00000004 ) >> 2)
+#define GET_RG_DP_FREF_DOUB (((REG32(ADR_PMU_DPLL_REG_1)) & 0x00000008 ) >> 3)
+#define GET_RG_DP_DAC320_DIVBY2 (((REG32(ADR_PMU_DPLL_REG_1)) & 0x00000010 ) >> 4)
+#define GET_RG_DP_ADC320_DIVBY2_BT (((REG32(ADR_PMU_DPLL_REG_1)) & 0x00000020 ) >> 5)
+#define GET_RG_DP_ADC320_DIVBY2_WF (((REG32(ADR_PMU_DPLL_REG_1)) & 0x00000040 ) >> 6)
+#define GET_RG_EN_DPL_MOD (((REG32(ADR_PMU_DPLL_REG_1)) & 0x00000100 ) >> 8)
+#define GET_RG_DPL_MOD_ORDER (((REG32(ADR_PMU_DPLL_REG_1)) & 0x00000600 ) >> 9)
+#define GET_RG_DP_REFDIV (((REG32(ADR_PMU_DPLL_REG_1)) & 0x0003f800 ) >> 11)
+#define GET_RG_DP_FODIV (((REG32(ADR_PMU_DPLL_REG_1)) & 0x01fc0000 ) >> 18)
+#define GET_RG_EN_LDO_DP_IQUP (((REG32(ADR_PMU_DPLL_REG_1)) & 0x04000000 ) >> 26)
+#define GET_RG_DP_OD_TEST (((REG32(ADR_PMU_DPLL_REG_1)) & 0x08000000 ) >> 27)
+#define GET_RG_DP_BBPLL_TESTSEL (((REG32(ADR_PMU_DPLL_REG_1)) & 0x70000000 ) >> 28)
+#define GET_RG_DP_BBPLL_ICP (((REG32(ADR_PMU_DPLL_REG_2)) & 0x00000003 ) >> 0)
+#define GET_RG_DP_BBPLL_IDUAL (((REG32(ADR_PMU_DPLL_REG_2)) & 0x0000000c ) >> 2)
+#define GET_RG_DP_CP_IOSTPOL (((REG32(ADR_PMU_DPLL_REG_2)) & 0x00000010 ) >> 4)
+#define GET_RG_DP_CP_IOST (((REG32(ADR_PMU_DPLL_REG_2)) & 0x00000060 ) >> 5)
+#define GET_RG_DP_PFD_PFDSEL (((REG32(ADR_PMU_DPLL_REG_2)) & 0x00000080 ) >> 7)
+#define GET_RG_DP_BBPLL_PFD_DLY (((REG32(ADR_PMU_DPLL_REG_2)) & 0x00000300 ) >> 8)
+#define GET_RG_DP_RP (((REG32(ADR_PMU_DPLL_REG_2)) & 0x00003800 ) >> 11)
+#define GET_RG_DP_RHP (((REG32(ADR_PMU_DPLL_REG_2)) & 0x0000c000 ) >> 14)
+#define GET_RG_EN_DP_VT_MON (((REG32(ADR_PMU_DPLL_REG_2)) & 0x00020000 ) >> 17)
+#define GET_RG_DP_VT_TH_HI (((REG32(ADR_PMU_DPLL_REG_2)) & 0x000c0000 ) >> 18)
+#define GET_RG_DP_VT_TH_LO (((REG32(ADR_PMU_DPLL_REG_2)) & 0x00300000 ) >> 20)
+#define GET_RG_DP_BBPLL_BS (((REG32(ADR_PMU_DPLL_REG_2)) & 0x1f800000 ) >> 23)
+#define GET_RG_DP_BBPLL_SDM_EDGE (((REG32(ADR_PMU_DPLL_REG_2)) & 0x80000000 ) >> 31)
+#define GET_RG_DPL_RFCTRL_F (((REG32(ADR_PMU_DPLL_REG_3)) & 0x00ffffff ) >> 0)
+#define GET_RG_DPL_RFCTRL_CH (((REG32(ADR_PMU_DPLL_REG_3)) & 0xff000000 ) >> 24)
+#define GET_RG_DCDC_MODE_SLP (((REG32(ADR_PMU_SLEEP_MODE_REG)) & 0x00000001 ) >> 0)
+#define GET_RG_DLDO_LEVEL_SLP (((REG32(ADR_PMU_SLEEP_MODE_REG)) & 0x0000000e ) >> 1)
+#define GET_RG_BUCK_LEVEL_SLP (((REG32(ADR_PMU_SLEEP_MODE_REG)) & 0x000000f0 ) >> 4)
+#define GET_RG_XO_CBANKI_SLP (((REG32(ADR_PMU_SLEEP_MODE_REG)) & 0x0001ff00 ) >> 8)
+#define GET_RG_XO_CBANKO_SLP (((REG32(ADR_PMU_SLEEP_MODE_REG)) & 0x03fe0000 ) >> 17)
+#define GET_RG_EN_DLDO_HALF_IQ_SLP (((REG32(ADR_PMU_SLEEP_MODE_REG)) & 0x04000000 ) >> 26)
+#define GET_RG_EN_DLDO_BYP_AUTO (((REG32(ADR_PMU_SLEEP_MODE_REG)) & 0x08000000 ) >> 27)
+#define GET_RG_HW_WAKE_XOSC_SLP (((REG32(ADR_PMU_SLEEP_MODE_REG)) & 0x80000000 ) >> 31)
+#define GET_RG_RAM_00 (((REG32(ADR_PMU_RAM_00)) & 0xffffffff ) >> 0)
+#define GET_RG_RAM_01 (((REG32(ADR_PMU_RAM_01)) & 0xffffffff ) >> 0)
+#define GET_RG_RAM_02 (((REG32(ADR_PMU_RAM_02)) & 0xffffffff ) >> 0)
+#define GET_RG_RAM_03 (((REG32(ADR_PMU_RAM_03)) & 0xffffffff ) >> 0)
+#define GET_RG_RAM_04 (((REG32(ADR_PMU_RAM_04)) & 0xffffffff ) >> 0)
+#define GET_RG_RAM_05 (((REG32(ADR_PMU_RAM_05)) & 0xffffffff ) >> 0)
+#define GET_RG_RAM_06 (((REG32(ADR_PMU_RAM_06)) & 0xffffffff ) >> 0)
+#define GET_RG_RAM_07 (((REG32(ADR_PMU_RAM_07)) & 0xffffffff ) >> 0)
+#define GET_RG_RAM_08 (((REG32(ADR_PMU_RAM_08)) & 0xffffffff ) >> 0)
+#define GET_RG_RAM_09 (((REG32(ADR_PMU_RAM_09)) & 0xffffffff ) >> 0)
+#define GET_RG_RAM_10 (((REG32(ADR_PMU_RAM_10)) & 0xffffffff ) >> 0)
+#define GET_RG_RAM_11 (((REG32(ADR_PMU_RAM_11)) & 0xffffffff ) >> 0)
+#define GET_RG_RAM_12 (((REG32(ADR_PMU_RAM_12)) & 0xffffffff ) >> 0)
+#define GET_RG_RAM_13 (((REG32(ADR_PMU_RAM_13)) & 0xffffffff ) >> 0)
+#define GET_RG_RAM_14 (((REG32(ADR_PMU_RAM_14)) & 0xffffffff ) >> 0)
+#define GET_RG_RAM_15 (((REG32(ADR_PMU_RAM_15)) & 0xffffffff ) >> 0)
+#define GET_RG_PMDLBK (((REG32(ADR_WIFI_PHY_COMMON_SYS_REG)) & 0x00000001 ) >> 0)
+#define GET_RG_DAC_LBK_EDGE_SEL (((REG32(ADR_WIFI_PHY_COMMON_SYS_REG)) & 0x00000002 ) >> 1)
+#define GET_RG_RSSI_EDGE_SEL_BB (((REG32(ADR_WIFI_PHY_COMMON_SYS_REG)) & 0x00000004 ) >> 2)
+#define GET_RG_SIGN_SWAP_BB (((REG32(ADR_WIFI_PHY_COMMON_SYS_REG)) & 0x00000010 ) >> 4)
+#define GET_RG_IQ_SWAP_BB (((REG32(ADR_WIFI_PHY_COMMON_SYS_REG)) & 0x00000020 ) >> 5)
+#define GET_RG_Q_INV_BB (((REG32(ADR_WIFI_PHY_COMMON_SYS_REG)) & 0x00000040 ) >> 6)
+#define GET_RG_I_INV_BB (((REG32(ADR_WIFI_PHY_COMMON_SYS_REG)) & 0x00000080 ) >> 7)
+#define GET_RG_BYPASS_ACI (((REG32(ADR_WIFI_PHY_COMMON_SYS_REG)) & 0x00000100 ) >> 8)
+#define GET_RG_LBK_ANA_PATH (((REG32(ADR_WIFI_PHY_COMMON_SYS_REG)) & 0x00000200 ) >> 9)
+#define GET_RG_LBK_DIG_SEL (((REG32(ADR_WIFI_PHY_COMMON_SYS_REG)) & 0x00000400 ) >> 10)
+#define GET_RG_RF_5G_BAND (((REG32(ADR_WIFI_PHY_COMMON_SYS_REG)) & 0x00000800 ) >> 11)
+#define GET_RG_PRIMARY_CH_SIDE (((REG32(ADR_WIFI_PHY_COMMON_SYS_REG)) & 0x00004000 ) >> 14)
+#define GET_RG_SYSTEM_BW (((REG32(ADR_WIFI_PHY_COMMON_SYS_REG)) & 0x00008000 ) >> 15)
+#define GET_RG_11B_ACI_SEL (((REG32(ADR_WIFI_PHY_COMMON_SYS_REG)) & 0x00010000 ) >> 16)
+#define GET_RG_BB_CLK_SEL (((REG32(ADR_WIFI_PHY_COMMON_SYS_REG)) & 0x80000000 ) >> 31)
+#define GET_RG_PHY_MD_EN (((REG32(ADR_WIFI_PHY_COMMON_ENABLE_REG)) & 0x00000001 ) >> 0)
+#define GET_RG_PHYRX_MD_EN (((REG32(ADR_WIFI_PHY_COMMON_ENABLE_REG)) & 0x00000002 ) >> 1)
+#define GET_RG_PHYTX_MD_EN (((REG32(ADR_WIFI_PHY_COMMON_ENABLE_REG)) & 0x00000004 ) >> 2)
+#define GET_RG_PHY11GN_MD_EN (((REG32(ADR_WIFI_PHY_COMMON_ENABLE_REG)) & 0x00000008 ) >> 3)
+#define GET_RG_PHY11B_MD_EN (((REG32(ADR_WIFI_PHY_COMMON_ENABLE_REG)) & 0x00000010 ) >> 4)
+#define GET_RG_PHYRXFIFO_MD_EN (((REG32(ADR_WIFI_PHY_COMMON_ENABLE_REG)) & 0x00000020 ) >> 5)
+#define GET_RG_PHYTXFIFO_MD_EN (((REG32(ADR_WIFI_PHY_COMMON_ENABLE_REG)) & 0x00000040 ) >> 6)
+#define GET_RG_PHY11BGN_MD_EN (((REG32(ADR_WIFI_PHY_COMMON_ENABLE_REG)) & 0x00000100 ) >> 8)
+#define GET_RG_FORCE_11GN_EN (((REG32(ADR_WIFI_PHY_COMMON_ENABLE_REG)) & 0x00001000 ) >> 12)
+#define GET_RG_FORCE_11B_EN (((REG32(ADR_WIFI_PHY_COMMON_ENABLE_REG)) & 0x00002000 ) >> 13)
+#define GET_RG_PHY_IQ_TRIG_SEL (((REG32(ADR_WIFI_PHY_COMMON_ENABLE_REG)) & 0x000f0000 ) >> 16)
+#define GET_SVN_VERSION (((REG32(ADR_WIFI_PHY_COMMON_VERSION_REG)) & 0xffffffff ) >> 0)
+#define GET_RG_LENGTH (((REG32(ADR_WIFI_PHY_COMMON_DES_REG0)) & 0x0000ffff ) >> 0)
+#define GET_RG_PKT_MODE (((REG32(ADR_WIFI_PHY_COMMON_DES_REG0)) & 0x00070000 ) >> 16)
+#define GET_RG_CH_BW (((REG32(ADR_WIFI_PHY_COMMON_DES_REG0)) & 0x00380000 ) >> 19)
+#define GET_RG_PRM (((REG32(ADR_WIFI_PHY_COMMON_DES_REG0)) & 0x00400000 ) >> 22)
+#define GET_RG_SHORTGI (((REG32(ADR_WIFI_PHY_COMMON_DES_REG0)) & 0x00800000 ) >> 23)
+#define GET_RG_RATE (((REG32(ADR_WIFI_PHY_COMMON_DES_REG0)) & 0x7f000000 ) >> 24)
+#define GET_RG_L_LENGTH (((REG32(ADR_WIFI_PHY_COMMON_DES_REG1)) & 0x00000fff ) >> 0)
+#define GET_RG_L_RATE (((REG32(ADR_WIFI_PHY_COMMON_DES_REG1)) & 0x00007000 ) >> 12)
+#define GET_RG_SERVICE (((REG32(ADR_WIFI_PHY_COMMON_DES_REG1)) & 0xffff0000 ) >> 16)
+#define GET_RG_SMOOTHING (((REG32(ADR_WIFI_PHY_COMMON_DES_REG2)) & 0x00000001 ) >> 0)
+#define GET_RG_NO_SOUND (((REG32(ADR_WIFI_PHY_COMMON_DES_REG2)) & 0x00000002 ) >> 1)
+#define GET_RG_AGGREGATE (((REG32(ADR_WIFI_PHY_COMMON_DES_REG2)) & 0x00000004 ) >> 2)
+#define GET_RG_STBC (((REG32(ADR_WIFI_PHY_COMMON_DES_REG2)) & 0x00000018 ) >> 3)
+#define GET_RG_FEC (((REG32(ADR_WIFI_PHY_COMMON_DES_REG2)) & 0x00000020 ) >> 5)
+#define GET_RG_N_ESS (((REG32(ADR_WIFI_PHY_COMMON_DES_REG2)) & 0x000000c0 ) >> 6)
+#define GET_RG_TXPWRLVL (((REG32(ADR_WIFI_PHY_COMMON_DES_REG2)) & 0x00007f00 ) >> 8)
+#define GET_RG_BB_SCALE (((REG32(ADR_WIFI_PHY_COMMON_DES_REG2)) & 0x00ff0000 ) >> 16)
+#define GET_RG_TX_START (((REG32(ADR_WIFI_PHY_COMMON_DES_REG3)) & 0x00000001 ) >> 0)
+#define GET_RG_IFS_TIME (((REG32(ADR_WIFI_PHY_COMMON_DES_REG3)) & 0x000000fc ) >> 2)
+#define GET_RG_CONTINUOUS_DATA (((REG32(ADR_WIFI_PHY_COMMON_DES_REG3)) & 0x00000100 ) >> 8)
+#define GET_RG_DATA_SEL (((REG32(ADR_WIFI_PHY_COMMON_DES_REG3)) & 0x00000600 ) >> 9)
+#define GET_RG_TX_D (((REG32(ADR_WIFI_PHY_COMMON_DES_REG3)) & 0x00ff0000 ) >> 16)
+#define GET_RG_IFS_TIME_EXT (((REG32(ADR_WIFI_PHY_COMMON_DES_REG3)) & 0xff000000 ) >> 24)
+#define GET_RG_TX_CNT_TARGET (((REG32(ADR_WIFI_PHY_COMMON_DES_REG4)) & 0xffffffff ) >> 0)
+#define GET_RG_TXD_SEL (((REG32(ADR_WIFI_PHY_COMMON_TX_CONTROL)) & 0x00000c00 ) >> 10)
+#define GET_RG_TX_FREQ_OFFSET_DES (((REG32(ADR_WIFI_PHY_COMMON_DES_REG5)) & 0x0000ffff ) >> 0)
+#define GET_RG_DES_RATE (((REG32(ADR_WIFI_PHY_COMMON_DES_REG6)) & 0x000000ff ) >> 0)
+#define GET_RG_DES_MAN_EN (((REG32(ADR_WIFI_PHY_COMMON_DES_REG6)) & 0x80000000 ) >> 31)
+#define GET_RG_PGA_REFDB_SAT_B (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG0)) & 0x0000007f ) >> 0)
+#define GET_RG_PGA_REFDB_TOP_B (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG0)) & 0x00007f00 ) >> 8)
+#define GET_RG_PGA_REF_UND_B (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG0)) & 0x03ff0000 ) >> 16)
+#define GET_RG_RF_REF_SAT_B (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG0)) & 0xf0000000 ) >> 28)
+#define GET_RG_PGA_REFDB_SAT_GN (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG1)) & 0x0000007f ) >> 0)
+#define GET_RG_PGA_REFDB_TOP_GN (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG1)) & 0x00007f00 ) >> 8)
+#define GET_RG_PGA_REF_UND_GN (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG1)) & 0x03ff0000 ) >> 16)
+#define GET_RG_RF_REF_SAT_GN (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG1)) & 0xf0000000 ) >> 28)
+#define GET_RG_PGAGC_SET (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG2)) & 0x0000000f ) >> 0)
+#define GET_RG_PGAGC_OW (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG2)) & 0x00000010 ) >> 4)
+#define GET_RG_RFGC_SET (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG2)) & 0x00000060 ) >> 5)
+#define GET_RG_RFGC_OW (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG2)) & 0x00000080 ) >> 7)
+#define GET_RG_WAIT_T_RXAGC (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG2)) & 0x00003f00 ) >> 8)
+#define GET_RG_RXAGC_SET (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG2)) & 0x00004000 ) >> 14)
+#define GET_RG_RXAGC_OW (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG2)) & 0x00008000 ) >> 15)
+#define GET_RG_WAIT_T_FINAL (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG2)) & 0x003f0000 ) >> 16)
+#define GET_RG_WAIT_T (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG2)) & 0x3f000000 ) >> 24)
+#define GET_RG_ULG_PGA_SAT_PGA_GAIN (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG3)) & 0x0000000f ) >> 0)
+#define GET_RG_LG_PGA_UND_PGA_GAIN (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG3)) & 0x000000f0 ) >> 4)
+#define GET_RG_LG_PGA_SAT_PGA_GAIN (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG3)) & 0x00000f00 ) >> 8)
+#define GET_RG_LG_RF_SAT_PGA_GAIN (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG3)) & 0x0000f000 ) >> 12)
+#define GET_RG_MG_RF_SAT_PGANOREF_PGA_GAIN (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG3)) & 0x000f0000 ) >> 16)
+#define GET_RG_HG_PGA_SAT2_PGA_GAIN (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG3)) & 0x00f00000 ) >> 20)
+#define GET_RG_HG_PGA_SAT1_PGA_GAIN (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG3)) & 0x0f000000 ) >> 24)
+#define GET_RG_HG_RF_SAT_PGA_GAIN (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG3)) & 0xf0000000 ) >> 28)
+#define GET_RG_MG_PGA_JB_TH (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG4)) & 0x0000000f ) >> 0)
+#define GET_RG_MA_PGA_LOW_TH_CNT_LMT (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG4)) & 0x001f0000 ) >> 16)
+#define GET_RG_MA_PGA_HIGH_TH_CNT_LMT (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG4)) & 0x1f000000 ) >> 24)
+#define GET_RG_AGC_THRESHOLD (((REG32(ADR_WIFI_PHY_COMMON_11B_DAGC_REG0)) & 0x00003fff ) >> 0)
+#define GET_RG_ACI_POINT_CNT_LMT_11B (((REG32(ADR_WIFI_PHY_COMMON_11B_DAGC_REG0)) & 0x007f0000 ) >> 16)
+#define GET_RG_ACI_DAGC_LEAKY_FACTOR_11B (((REG32(ADR_WIFI_PHY_COMMON_11B_DAGC_REG0)) & 0x03000000 ) >> 24)
+#define GET_RG_ACI_DAGC_PWR_SEL_11B (((REG32(ADR_WIFI_PHY_COMMON_11B_DAGC_REG0)) & 0x10000000 ) >> 28)
+#define GET_RG_ACI_DAGC_TARGET_11B (((REG32(ADR_WIFI_PHY_COMMON_11B_DAGC_REG1)) & 0x0000007f ) >> 0)
+#define GET_RG_ACI_GAIN_INI_11B (((REG32(ADR_WIFI_PHY_COMMON_11B_DAGC_REG1)) & 0x0000ff00 ) >> 8)
+#define GET_RG_ACI_GAIN_SET_11B (((REG32(ADR_WIFI_PHY_COMMON_11B_DAGC_REG1)) & 0x00ff0000 ) >> 16)
+#define GET_RG_ACI_GAIN_OW_11B (((REG32(ADR_WIFI_PHY_COMMON_11B_DAGC_REG1)) & 0x80000000 ) >> 31)
+#define GET_RG_ACI_POINT_CNT_LMT_11GN_HT20 (((REG32(ADR_WIFI_PHY_COMMON_11GN20_DAGC_REG0)) & 0x000000ff ) >> 0)
+#define GET_RG_ACI_DAGC_LEAKY_FACTOR_11GN_HT20 (((REG32(ADR_WIFI_PHY_COMMON_11GN20_DAGC_REG0)) & 0x00000300 ) >> 8)
+#define GET_RG_ACI_DAGC_PWR_SEL_11GN_HT20 (((REG32(ADR_WIFI_PHY_COMMON_11GN20_DAGC_REG0)) & 0x00001000 ) >> 12)
+#define GET_RG_ACI_DAGC_DONE_CNT_LMT_11GN (((REG32(ADR_WIFI_PHY_COMMON_11GN20_DAGC_REG0)) & 0xff000000 ) >> 24)
+#define GET_RG_ACI_DAGC_TARGET_11GN_HT20 (((REG32(ADR_WIFI_PHY_COMMON_11GN20_DAGC_REG1)) & 0x0000007f ) >> 0)
+#define GET_RG_ACI_GAIN_SET_11GN_HT20 (((REG32(ADR_WIFI_PHY_COMMON_11GN20_DAGC_REG1)) & 0x01ff0000 ) >> 16)
+#define GET_RG_ACI_GAIN_OW_11GN_HT20 (((REG32(ADR_WIFI_PHY_COMMON_11GN20_DAGC_REG1)) & 0x80000000 ) >> 31)
+#define GET_RO_CCA_PWR_MA_11GN_HT40 (((REG32(ADR_WIFI_PHY_COMMON_11BGN_DIGPWR_REG)) & 0x0000007f ) >> 0)
+#define GET_RO_CCA_PWR_MA_11GN_HT20 (((REG32(ADR_WIFI_PHY_COMMON_11BGN_DIGPWR_REG)) & 0x00007f00 ) >> 8)
+#define GET_RO_CCA_PWR_MA_11B (((REG32(ADR_WIFI_PHY_COMMON_11BGN_DIGPWR_REG)) & 0x007f0000 ) >> 16)
+#define GET_RO_ED_STATE (((REG32(ADR_WIFI_PHY_COMMON_11BGN_DIGPWR_REG)) & 0x01000000 ) >> 24)
+#define GET_RO_2ND_ED_STATE (((REG32(ADR_WIFI_PHY_COMMON_11BGN_DIGPWR_REG)) & 0x02000000 ) >> 25)
+#define GET_RO_PGA_PWR_FF1 (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_RO00)) & 0x00003fff ) >> 0)
+#define GET_RO_RF_PWR_FF1 (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_RO00)) & 0x000f0000 ) >> 16)
+#define GET_RO_PGAGC_FF1 (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_RO00)) & 0x0f000000 ) >> 24)
+#define GET_RO_RFGC_FF1 (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_RO00)) & 0x30000000 ) >> 28)
+#define GET_RO_PGA_PWR_FF2 (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_RO01)) & 0x00003fff ) >> 0)
+#define GET_RO_RF_PWR_FF2 (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_RO01)) & 0x000f0000 ) >> 16)
+#define GET_RO_PGAGC_FF2 (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_RO01)) & 0x0f000000 ) >> 24)
+#define GET_RO_RFGC_FF2 (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_RO01)) & 0x30000000 ) >> 28)
+#define GET_RO_PGA_PWR_FF3 (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_RO02)) & 0x00003fff ) >> 0)
+#define GET_RO_RF_PWR_FF3 (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_RO02)) & 0x000f0000 ) >> 16)
+#define GET_RO_PGAGC_FF3 (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_RO02)) & 0x0f000000 ) >> 24)
+#define GET_RO_RFGC_FF3 (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_RO02)) & 0x30000000 ) >> 28)
+#define GET_RG_5G_DC_RM_LEAKY_FACTOR_T3 (((REG32(ADR_WIFI_PHY_COMMON_RXDC)) & 0x00000070 ) >> 4)
+#define GET_RG_5G_DC_RM_LEAKY_FACTOR_T2 (((REG32(ADR_WIFI_PHY_COMMON_RXDC)) & 0x00000700 ) >> 8)
+#define GET_RG_5G_DC_RM_LEAKY_FACTOR_T1 (((REG32(ADR_WIFI_PHY_COMMON_RXDC)) & 0x00007000 ) >> 12)
+#define GET_RG_DC_RM_BYP (((REG32(ADR_WIFI_PHY_COMMON_RXDC)) & 0x00010000 ) >> 16)
+#define GET_RG_DC_RM_LEAKY_FACTOR_T3 (((REG32(ADR_WIFI_PHY_COMMON_RXDC)) & 0x00700000 ) >> 20)
+#define GET_RG_DC_RM_LEAKY_FACTOR_T2 (((REG32(ADR_WIFI_PHY_COMMON_RXDC)) & 0x07000000 ) >> 24)
+#define GET_RG_DC_RM_LEAKY_FACTOR_T1 (((REG32(ADR_WIFI_PHY_COMMON_RXDC)) & 0x70000000 ) >> 28)
+#define GET_RO_Q_DC_OUT (((REG32(ADR_WIFI_PHY_COMMON_RXDC_RO)) & 0x000003ff ) >> 0)
+#define GET_RO_I_DC_OUT (((REG32(ADR_WIFI_PHY_COMMON_RXDC_RO)) & 0x03ff0000 ) >> 16)
+#define GET_RG_TBUS_SEL (((REG32(ADR_WIFI_PHY_COMMON_RSSI_TBUS_REG)) & 0x0000000f ) >> 0)
+#define GET_RG_RSSI_OFFSET (((REG32(ADR_WIFI_PHY_COMMON_RSSI_TBUS_REG)) & 0x00ff0000 ) >> 16)
+#define GET_RG_RSSI_INV (((REG32(ADR_WIFI_PHY_COMMON_RSSI_TBUS_REG)) & 0x01000000 ) >> 24)
+#define GET_RO_MRX_EN_CNT (((REG32(ADR_WIFI_PHY_COMMON_RX_EN_CNT_REG)) & 0x0000ffff ) >> 0)
+#define GET_RG_MRX_EN_CNT_RST_N (((REG32(ADR_WIFI_PHY_COMMON_RX_EN_CNT_REG)) & 0x80000000 ) >> 31)
+#define GET_RG_EDCCA_AVG_T (((REG32(ADR_WIFI_PHY_COMMON_EDCCA_0)) & 0x00000007 ) >> 0)
+#define GET_RG_EDCCA_STAT_EN (((REG32(ADR_WIFI_PHY_COMMON_EDCCA_0)) & 0x00000010 ) >> 4)
+#define GET_RO_EDCCA_PRIMARY_PRD (((REG32(ADR_WIFI_PHY_COMMON_EDCCA_1)) & 0x0000ffff ) >> 0)
+#define GET_RO_PRIMARY_EDCCA (((REG32(ADR_WIFI_PHY_COMMON_EDCCA_1)) & 0xffff0000 ) >> 16)
+#define GET_RO_EDCCA_SECONDARY_PRD (((REG32(ADR_WIFI_PHY_COMMON_EDCCA_2)) & 0x0000ffff ) >> 0)
+#define GET_RO_SECONDARY_EDCCA (((REG32(ADR_WIFI_PHY_COMMON_EDCCA_2)) & 0xffff0000 ) >> 16)
+#define GET_RG_AGC_RELOCK_PWR_TH (((REG32(ADR_WIFI_PHY_AGC_RELOCK_1)) & 0x00003fff ) >> 0)
+#define GET_RG_AGC_RELOCK_CNT_TH (((REG32(ADR_WIFI_PHY_AGC_RELOCK_1)) & 0x003f0000 ) >> 16)
+#define GET_RG_AGC_RELOCK_SEL (((REG32(ADR_WIFI_PHY_AGC_RELOCK_1)) & 0x03000000 ) >> 24)
+#define GET_RG_AGC_RELOCK_EN (((REG32(ADR_WIFI_PHY_AGC_RELOCK_1)) & 0x10000000 ) >> 28)
+#define GET_RG_AGC_RELOCK_11GN (((REG32(ADR_WIFI_PHY_AGC_RELOCK_1)) & 0x40000000 ) >> 30)
+#define GET_RG_AGC_RELOCK_11B (((REG32(ADR_WIFI_PHY_AGC_RELOCK_1)) & 0x80000000 ) >> 31)
+#define GET_RG_AGC_RELOCK_PWR_DIFFDB_TH (((REG32(ADR_WIFI_PHY_AGC_RELOCK_2)) & 0x0000007f ) >> 0)
+#define GET_RG_AGC_RELOCK_CNT_DIFFDB_TH (((REG32(ADR_WIFI_PHY_AGC_RELOCK_2)) & 0x003f0000 ) >> 16)
+#define GET_RG_MTX_LEN_LOWER_TH_0 (((REG32(ADR_WIFI_PHY_COMMON_TX_LENGTH_CNT_REG0)) & 0x0000ffff ) >> 0)
+#define GET_RG_MTX_LEN_UPPER_TH_0 (((REG32(ADR_WIFI_PHY_COMMON_TX_LENGTH_CNT_REG0)) & 0xffff0000 ) >> 16)
+#define GET_RG_MTX_LEN_LOWER_TH_1 (((REG32(ADR_WIFI_PHY_COMMON_TX_LENGTH_CNT_REG1)) & 0x0000ffff ) >> 0)
+#define GET_RG_MTX_LEN_UPPER_TH_1 (((REG32(ADR_WIFI_PHY_COMMON_TX_LENGTH_CNT_REG1)) & 0xffff0000 ) >> 16)
+#define GET_RG_MRX_LEN_LOWER_TH_0 (((REG32(ADR_WIFI_PHY_COMMON_RX_LENGTH_CNT_REG0)) & 0x0000ffff ) >> 0)
+#define GET_RG_MRX_LEN_UPPER_TH_0 (((REG32(ADR_WIFI_PHY_COMMON_RX_LENGTH_CNT_REG0)) & 0xffff0000 ) >> 16)
+#define GET_RG_MRX_LEN_LOWER_TH_1 (((REG32(ADR_WIFI_PHY_COMMON_RX_LENGTH_CNT_REG1)) & 0x0000ffff ) >> 0)
+#define GET_RG_MRX_LEN_UPPER_TH_1 (((REG32(ADR_WIFI_PHY_COMMON_RX_LENGTH_CNT_REG1)) & 0xffff0000 ) >> 16)
+#define GET_RO_MTX_LEN_CNT_1 (((REG32(ADR_WIFI_PHY_COMMON_TX_LENGTH_CNT_RO)) & 0x0000ffff ) >> 0)
+#define GET_RO_MTX_LEN_CNT_0 (((REG32(ADR_WIFI_PHY_COMMON_TX_LENGTH_CNT_RO)) & 0xffff0000 ) >> 16)
+#define GET_RO_MRX_LEN_CNT_1 (((REG32(ADR_WIFI_PHY_COMMON_RX_LENGTH_CNT_RO)) & 0x0000ffff ) >> 0)
+#define GET_RO_MRX_LEN_CNT_0 (((REG32(ADR_WIFI_PHY_COMMON_RX_LENGTH_CNT_RO)) & 0xffff0000 ) >> 16)
+#define GET_RG_MRX_TYPE (((REG32(ADR_WIFI_PHY_COMMON_TRX_TYPE_CNT_REG)) & 0x000000ff ) >> 0)
+#define GET_RG_MRX_TYPE_CNT_LMT (((REG32(ADR_WIFI_PHY_COMMON_TRX_TYPE_CNT_REG)) & 0x00001f00 ) >> 8)
+#define GET_RG_MTX_TYPE (((REG32(ADR_WIFI_PHY_COMMON_TRX_TYPE_CNT_REG)) & 0x00ff0000 ) >> 16)
+#define GET_RG_MTX_TYPE_CNT_LMT (((REG32(ADR_WIFI_PHY_COMMON_TRX_TYPE_CNT_REG)) & 0x1f000000 ) >> 24)
+#define GET_RO_MRX_TYPE_CNT (((REG32(ADR_WIFI_PHY_COMMON_TRX_TYPE_CNT_RO)) & 0x0000ffff ) >> 0)
+#define GET_RO_MTX_TYPE_CNT (((REG32(ADR_WIFI_PHY_COMMON_TRX_TYPE_CNT_RO)) & 0xffff0000 ) >> 16)
+#define GET_RG_ACI_POINT_CNT_LMT_11GN_HT40 (((REG32(ADR_WIFI_PHY_COMMON_11GN40_DAGC_REG0)) & 0x000000ff ) >> 0)
+#define GET_RG_ACI_DAGC_LEAKY_FACTOR_11GN_HT40 (((REG32(ADR_WIFI_PHY_COMMON_11GN40_DAGC_REG0)) & 0x00000300 ) >> 8)
+#define GET_RG_ACI_DAGC_PWR_SEL_11GN_HT40 (((REG32(ADR_WIFI_PHY_COMMON_11GN40_DAGC_REG0)) & 0x00001000 ) >> 12)
+#define GET_RG_ACI_DAGC_TARGET_11GN_HT40 (((REG32(ADR_WIFI_PHY_COMMON_11GN40_DAGC_REG1)) & 0x0000007f ) >> 0)
+#define GET_RG_ACI_GAIN_SET_11GN_HT40 (((REG32(ADR_WIFI_PHY_COMMON_11GN40_DAGC_REG1)) & 0x01ff0000 ) >> 16)
+#define GET_RG_ACI_GAIN_OW_11GN_HT40 (((REG32(ADR_WIFI_PHY_COMMON_11GN40_DAGC_REG1)) & 0x80000000 ) >> 31)
+#define GET_RG_ACI_GAIN_INI_11GN_HT40 (((REG32(ADR_WIFI_PHY_COMMON_11GN_DAGC_INI_REG)) & 0x000001ff ) >> 0)
+#define GET_RG_ACI_GAIN_INI_11GN_HT20 (((REG32(ADR_WIFI_PHY_COMMON_11GN_DAGC_INI_REG)) & 0x01ff0000 ) >> 16)
+#define GET_RG_MAC_PKT_MODE (((REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_0)) & 0x00000001 ) >> 0)
+#define GET_RG_MAC_PKT_AGGREGATE (((REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_0)) & 0x00000002 ) >> 1)
+#define GET_RG_MAC_PKT_ADDR4_ON (((REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_0)) & 0x00000010 ) >> 4)
+#define GET_RG_MAC_PKT_SEQ_ON (((REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_0)) & 0x00000020 ) >> 5)
+#define GET_RG_MAC_PKT_ADDR3_ON (((REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_0)) & 0x00000040 ) >> 6)
+#define GET_RG_MAC_PKT_ADDR2_ON (((REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_0)) & 0x00000080 ) >> 7)
+#define GET_RG_MAC_PKT_AGGREGATE_NUM (((REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_0)) & 0x00000f00 ) >> 8)
+#define GET_RG_MAC_PKT_PLD_LENGTH (((REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_0)) & 0xffff0000 ) >> 16)
+#define GET_RG_MAC_PKT_DUR (((REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_1)) & 0x0000ffff ) >> 0)
+#define GET_RG_MAC_PKT_FC (((REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_1)) & 0xffff0000 ) >> 16)
+#define GET_RG_MAC_PKT_ADDR1_31_0 (((REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_2)) & 0xffffffff ) >> 0)
+#define GET_RG_MAC_PKT_ADDR1_47_32 (((REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_3)) & 0x0000ffff ) >> 0)
+#define GET_RG_MAC_PKT_ADDR2_31_0 (((REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_4)) & 0xffffffff ) >> 0)
+#define GET_RG_MAC_PKT_ADDR2_47_32 (((REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_5)) & 0x0000ffff ) >> 0)
+#define GET_RG_MAC_PKT_ADDR3_31_0 (((REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_6)) & 0xffffffff ) >> 0)
+#define GET_RG_MAC_PKT_ADDR3_47_32 (((REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_7)) & 0x0000ffff ) >> 0)
+#define GET_RG_MAC_PKT_SEQ (((REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_8)) & 0x0000ffff ) >> 0)
+#define GET_RG_MAC_PKT_ADDR4_31_0 (((REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_9)) & 0xffffffff ) >> 0)
+#define GET_RG_MAC_PKT_ADDR4_47_32 (((REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_A)) & 0x0000ffff ) >> 0)
+#define GET_RG_BB_SCALE_BARKER_CCK (((REG32(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_0)) & 0x000000ff ) >> 0)
+#define GET_RG_BB_SCALE_MAN_EN (((REG32(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_0)) & 0x00010000 ) >> 16)
+#define GET_RG_BB_SCALE_LEGACY_64QAM (((REG32(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_1)) & 0x000000ff ) >> 0)
+#define GET_RG_BB_SCALE_LEGACY_16QAM (((REG32(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_1)) & 0x0000ff00 ) >> 8)
+#define GET_RG_BB_SCALE_LEGACY_QPSK (((REG32(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_1)) & 0x00ff0000 ) >> 16)
+#define GET_RG_BB_SCALE_LEGACY_BPSK (((REG32(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_1)) & 0xff000000 ) >> 24)
+#define GET_RG_BB_SCALE_HT20_64QAM (((REG32(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_2)) & 0x000000ff ) >> 0)
+#define GET_RG_BB_SCALE_HT20_16QAM (((REG32(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_2)) & 0x0000ff00 ) >> 8)
+#define GET_RG_BB_SCALE_HT20_QPSK (((REG32(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_2)) & 0x00ff0000 ) >> 16)
+#define GET_RG_BB_SCALE_HT20_BPSK (((REG32(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_2)) & 0xff000000 ) >> 24)
+#define GET_RG_BB_SCALE_HT40_64QAM (((REG32(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_3)) & 0x000000ff ) >> 0)
+#define GET_RG_BB_SCALE_HT40_16QAM (((REG32(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_3)) & 0x0000ff00 ) >> 8)
+#define GET_RG_BB_SCALE_HT40_QPSK (((REG32(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_3)) & 0x00ff0000 ) >> 16)
+#define GET_RG_BB_SCALE_HT40_BPSK (((REG32(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_3)) & 0xff000000 ) >> 24)
+#define GET_RG_RF_PWR_BARKER_CCK (((REG32(ADR_WIFI_PHY_COMMON_RF_PWR_REG_0)) & 0x0000007f ) >> 0)
+#define GET_RG_RF_PWR_MAN_EN (((REG32(ADR_WIFI_PHY_COMMON_RF_PWR_REG_0)) & 0x00010000 ) >> 16)
+#define GET_RG_RF_PWR_LEGACY_64QAM (((REG32(ADR_WIFI_PHY_COMMON_RF_PWR_REG_1)) & 0x0000007f ) >> 0)
+#define GET_RG_RF_PWR_LEGACY_16QAM (((REG32(ADR_WIFI_PHY_COMMON_RF_PWR_REG_1)) & 0x00007f00 ) >> 8)
+#define GET_RG_RF_PWR_LEGACY_QPSK (((REG32(ADR_WIFI_PHY_COMMON_RF_PWR_REG_1)) & 0x007f0000 ) >> 16)
+#define GET_RG_RF_PWR_LEGACY_BPSK (((REG32(ADR_WIFI_PHY_COMMON_RF_PWR_REG_1)) & 0x7f000000 ) >> 24)
+#define GET_RG_RF_PWR_HT20_64QAM (((REG32(ADR_WIFI_PHY_COMMON_RF_PWR_REG_2)) & 0x0000007f ) >> 0)
+#define GET_RG_RF_PWR_HT20_16QAM (((REG32(ADR_WIFI_PHY_COMMON_RF_PWR_REG_2)) & 0x00007f00 ) >> 8)
+#define GET_RG_RF_PWR_HT20_QPSK (((REG32(ADR_WIFI_PHY_COMMON_RF_PWR_REG_2)) & 0x007f0000 ) >> 16)
+#define GET_RG_RF_PWR_HT20_BPSK (((REG32(ADR_WIFI_PHY_COMMON_RF_PWR_REG_2)) & 0x7f000000 ) >> 24)
+#define GET_RG_RF_PWR_HT40_64QAM (((REG32(ADR_WIFI_PHY_COMMON_RF_PWR_REG_3)) & 0x0000007f ) >> 0)
+#define GET_RG_RF_PWR_HT40_16QAM (((REG32(ADR_WIFI_PHY_COMMON_RF_PWR_REG_3)) & 0x00007f00 ) >> 8)
+#define GET_RG_RF_PWR_HT40_QPSK (((REG32(ADR_WIFI_PHY_COMMON_RF_PWR_REG_3)) & 0x007f0000 ) >> 16)
+#define GET_RG_RF_PWR_HT40_BPSK (((REG32(ADR_WIFI_PHY_COMMON_RF_PWR_REG_3)) & 0x7f000000 ) >> 24)
+#define GET_RG_RX_MONITOR_ON (((REG32(ADR_WIFI_PHY_COMMON_RX_MON_0)) & 0x00000001 ) >> 0)
+#define GET_RG_RX_PKT_ADDR3_ON (((REG32(ADR_WIFI_PHY_COMMON_RX_MON_0)) & 0x00000002 ) >> 1)
+#define GET_RG_RX_PKT_ADDR2_ON (((REG32(ADR_WIFI_PHY_COMMON_RX_MON_0)) & 0x00000004 ) >> 2)
+#define GET_RG_RX_PKT_ADDR1_ON (((REG32(ADR_WIFI_PHY_COMMON_RX_MON_0)) & 0x00000008 ) >> 3)
+#define GET_RG_RX_BEACON_TU (((REG32(ADR_WIFI_PHY_COMMON_RX_MON_0)) & 0x00003ff0 ) >> 4)
+#define GET_RG_RX_PKT_TIMER_LMT (((REG32(ADR_WIFI_PHY_COMMON_RX_MON_0)) & 0xffff0000 ) >> 16)
+#define GET_RG_RX_BEACON_LOSS_CNT_LMT (((REG32(ADR_WIFI_PHY_COMMON_RX_MON_1)) & 0x000000ff ) >> 0)
+#define GET_RG_RX_BEACON_CRC_BYPASS (((REG32(ADR_WIFI_PHY_COMMON_RX_MON_1)) & 0x00000100 ) >> 8)
+#define GET_RG_RX_BEACON_INTERVAL (((REG32(ADR_WIFI_PHY_COMMON_RX_MON_1)) & 0xffff0000 ) >> 16)
+#define GET_RG_RX_PKT_FC (((REG32(ADR_WIFI_PHY_COMMON_RX_MON_2)) & 0xffff0000 ) >> 16)
+#define GET_RG_RX_PKT_ADDR1_31_0 (((REG32(ADR_WIFI_PHY_COMMON_RX_MON_3)) & 0xffffffff ) >> 0)
+#define GET_RG_RX_PKT_ADDR1_47_32 (((REG32(ADR_WIFI_PHY_COMMON_RX_MON_4)) & 0x0000ffff ) >> 0)
+#define GET_RG_RX_PKT_ADDR2_31_0 (((REG32(ADR_WIFI_PHY_COMMON_RX_MON_5)) & 0xffffffff ) >> 0)
+#define GET_RG_RX_PKT_ADDR2_47_32 (((REG32(ADR_WIFI_PHY_COMMON_RX_MON_6)) & 0x0000ffff ) >> 0)
+#define GET_RG_RX_PKT_ADDR3_31_0 (((REG32(ADR_WIFI_PHY_COMMON_RX_MON_7)) & 0xffffffff ) >> 0)
+#define GET_RG_RX_PKT_ADDR3_47_32 (((REG32(ADR_WIFI_PHY_COMMON_RX_MON_8)) & 0x0000ffff ) >> 0)
+#define GET_RO_INTRP_RX_LOSS (((REG32(ADR_WIFI_PHY_COMMON_RX_TMR_MON_RO)) & 0x00000001 ) >> 0)
+#define GET_RO_RX_PKT_TIMER (((REG32(ADR_WIFI_PHY_COMMON_RX_TMR_MON_RO)) & 0xffff0000 ) >> 16)
+#define GET_RO_INTRP_RX_BEACON_LOSS (((REG32(ADR_WIFI_PHY_COMMON_RX_BKN_MON_RO)) & 0x00000001 ) >> 0)
+#define GET_RO_RX_BEACON_LOSS_CNT (((REG32(ADR_WIFI_PHY_COMMON_RX_BKN_MON_RO)) & 0x0000ff00 ) >> 8)
+#define GET_RO_RX_BEACON_CNT (((REG32(ADR_WIFI_PHY_COMMON_RX_BKN_MON_RO)) & 0xffff0000 ) >> 16)
+#define GET_RG_RX_FIFO_FULL_CNT_EN (((REG32(ADR_WIFI_PHY_COMMON_MAC_IF_CNT_CTRL)) & 0x00000001 ) >> 0)
+#define GET_RG_TX_FIFO_EMPTY_CNT_EN (((REG32(ADR_WIFI_PHY_COMMON_MAC_IF_CNT_CTRL)) & 0x00000010 ) >> 4)
+#define GET_RO_RX_FIFO_FULL_CNT (((REG32(ADR_WIFI_PHY_COMMON_MAC_IF_CNT_RO)) & 0x0000ffff ) >> 0)
+#define GET_RO_TX_FIFO_EMPTY_CNT (((REG32(ADR_WIFI_PHY_COMMON_MAC_IF_CNT_RO)) & 0xffff0000 ) >> 16)
+#define GET_RG_BIST_EN_RX_FFT (((REG32(ADR_WIFI_PHY_COMMON_RX_FFT_MEM_BIST_REG)) & 0x00000001 ) >> 0)
+#define GET_RG_BIST_MODE_RX_FFT (((REG32(ADR_WIFI_PHY_COMMON_RX_FFT_MEM_BIST_REG)) & 0x00000010 ) >> 4)
+#define GET_RO_BIST_DONE_RX_FFT_1 (((REG32(ADR_WIFI_PHY_COMMON_RX_FFT_MEM_BIST_REG)) & 0x00010000 ) >> 16)
+#define GET_RO_BIST_FAIL_RX_FFT_1 (((REG32(ADR_WIFI_PHY_COMMON_RX_FFT_MEM_BIST_REG)) & 0x00020000 ) >> 17)
+#define GET_RO_BIST_DONE_RX_FFT_0 (((REG32(ADR_WIFI_PHY_COMMON_RX_FFT_MEM_BIST_REG)) & 0x00100000 ) >> 20)
+#define GET_RO_BIST_FAIL_RX_FFT_0 (((REG32(ADR_WIFI_PHY_COMMON_RX_FFT_MEM_BIST_REG)) & 0x00200000 ) >> 21)
+#define GET_RG_AUDIO_CLK_EN (((REG32(ADR_WIFI_PHY_AUDIO_CLK_CTRL)) & 0x00000001 ) >> 0)
+#define GET_RG_AUDIO_CLK_SEL (((REG32(ADR_WIFI_PHY_AUDIO_CLK_CTRL)) & 0x00000002 ) >> 1)
+#define GET_RO_CSTATE_PKT (((REG32(ADR_WIFI_PHY_COMMON_TOP_STATUS_RO)) & 0x00000003 ) >> 0)
+#define GET_RO_MRX_RX_EN (((REG32(ADR_WIFI_PHY_COMMON_TOP_STATUS_RO)) & 0x00000010 ) >> 4)
+#define GET_RO_CSTATE_AGC (((REG32(ADR_WIFI_PHY_COMMON_TOP_STATUS_RO)) & 0x00000300 ) >> 8)
+#define GET_RO_AGC_START_80M (((REG32(ADR_WIFI_PHY_COMMON_TOP_STATUS_RO)) & 0x00001000 ) >> 12)
+#define GET_RO_CSTATE_RX (((REG32(ADR_WIFI_PHY_COMMON_TOP_STATUS_RO)) & 0x000f0000 ) >> 16)
+#define GET_RO_TX_IP (((REG32(ADR_WIFI_PHY_COMMON_TOP_STATUS_RO)) & 0x00100000 ) >> 20)
+#define GET_RO_CSTATE_TX (((REG32(ADR_WIFI_PHY_COMMON_TOP_STATUS_RO)) & 0x0f000000 ) >> 24)
+#define GET_RO_MAC_PHY_TRX_EN_SYNC (((REG32(ADR_WIFI_PHY_COMMON_TOP_STATUS_RO)) & 0x10000000 ) >> 28)
+#define GET_RG_RESERVED_CMM (((REG32(ADR_WIFI_PHY_COMMON_RESERVED_REG)) & 0xffffffff ) >> 0)
+#define GET_RG_BB_RISE_TIME_11B_TX (((REG32(ADR_WIFI_11B_TX_BB_RAMP_REG)) & 0x000000ff ) >> 0)
+#define GET_RG_BB_FALL_TIME_11B_TX (((REG32(ADR_WIFI_11B_TX_BB_RAMP_REG)) & 0x0000ff00 ) >> 8)
+#define GET_RG_BP_SMB (((REG32(ADR_WIFI_11B_TX_BB_RAMP_REG)) & 0x00010000 ) >> 16)
+#define GET_RO_TX_CNT_R_11B_TX (((REG32(ADR_WIFI_11B_TX_PKT_CNT_SENT_REG)) & 0xffffffff ) >> 0)
+#define GET_RG_DEBUG_SEL_11B_TX (((REG32(ADR_WIFI_11B_TX_DEBUG_SEL_REG)) & 0x0000000f ) >> 0)
+#define GET_RG_RESERVED_11B_TX (((REG32(ADR_WIFI_11B_TX_RESERVED_REG)) & 0xffffffff ) >> 0)
+#define GET_RG_POS_DES_L_EXT_11B_RX (((REG32(ADR_WIFI_11B_RX_REG_000)) & 0x0000000f ) >> 0)
+#define GET_RG_PRE_DES_DLY_11B_RX (((REG32(ADR_WIFI_11B_RX_REG_000)) & 0x000000f0 ) >> 4)
+#define GET_RG_CCA_RE_CHK_BIT_CNT_TH (((REG32(ADR_WIFI_11B_RX_REG_000)) & 0x00000f00 ) >> 8)
+#define GET_RG_CNT_CCA_RE_CHK_LMT (((REG32(ADR_WIFI_11B_RX_REG_001)) & 0x000f0000 ) >> 16)
+#define GET_RG_BYPASS_DESCRAMBLER (((REG32(ADR_WIFI_11B_RX_REG_001)) & 0x20000000 ) >> 29)
+#define GET_RG_CCA_BIT_CNT_TH (((REG32(ADR_WIFI_11B_RX_REG_002)) & 0x000000f0 ) >> 4)
+#define GET_RG_CCA_SCALE_BF (((REG32(ADR_WIFI_11B_RX_REG_002)) & 0x007f0000 ) >> 16)
+#define GET_RG_PEAK_IDX_CNT_SEL (((REG32(ADR_WIFI_11B_RX_REG_002)) & 0x30000000 ) >> 28)
+#define GET_RG_TR_KI_T2 (((REG32(ADR_WIFI_11B_RX_REG_003)) & 0x00000007 ) >> 0)
+#define GET_RG_TR_KP_T2 (((REG32(ADR_WIFI_11B_RX_REG_003)) & 0x00000070 ) >> 4)
+#define GET_RG_TR_KI_T1 (((REG32(ADR_WIFI_11B_RX_REG_003)) & 0x00000700 ) >> 8)
+#define GET_RG_TR_KP_T1 (((REG32(ADR_WIFI_11B_RX_REG_003)) & 0x00007000 ) >> 12)
+#define GET_RG_CR_KI_T1 (((REG32(ADR_WIFI_11B_RX_REG_004)) & 0x00070000 ) >> 16)
+#define GET_RG_CR_KP_T1 (((REG32(ADR_WIFI_11B_RX_REG_004)) & 0x00700000 ) >> 20)
+#define GET_RG_CHIP_CNT_SLICER (((REG32(ADR_WIFI_11B_RX_REG_005)) & 0x0000001f ) >> 0)
+#define GET_RG_CE_T2_CNT_LMT (((REG32(ADR_WIFI_11B_RX_REG_005)) & 0xff000000 ) >> 24)
+#define GET_RG_CE_MU_T1 (((REG32(ADR_WIFI_11B_RX_REG_006)) & 0x00000007 ) >> 0)
+#define GET_RG_CE_DLY_SEL (((REG32(ADR_WIFI_11B_RX_REG_006)) & 0x003f0000 ) >> 16)
+#define GET_RG_CE_MU_T4 (((REG32(ADR_WIFI_11B_RX_REG_007)) & 0x00000007 ) >> 0)
+#define GET_RG_CE_MU_T3 (((REG32(ADR_WIFI_11B_RX_REG_007)) & 0x00070000 ) >> 16)
+#define GET_RG_CE_MU_T2 (((REG32(ADR_WIFI_11B_RX_REG_007)) & 0x07000000 ) >> 24)
+#define GET_RG_EQ_MU_FB_T2 (((REG32(ADR_WIFI_11B_RX_REG_008)) & 0x0000000f ) >> 0)
+#define GET_RG_EQ_MU_FF_T2 (((REG32(ADR_WIFI_11B_RX_REG_008)) & 0x000000f0 ) >> 4)
+#define GET_RG_EQ_MU_FB_T1 (((REG32(ADR_WIFI_11B_RX_REG_008)) & 0x000f0000 ) >> 16)
+#define GET_RG_EQ_MU_FF_T1 (((REG32(ADR_WIFI_11B_RX_REG_008)) & 0x00f00000 ) >> 20)
+#define GET_RG_EQ_MU_FB_T4 (((REG32(ADR_WIFI_11B_RX_REG_009)) & 0x0000000f ) >> 0)
+#define GET_RG_EQ_MU_FF_T4 (((REG32(ADR_WIFI_11B_RX_REG_009)) & 0x000000f0 ) >> 4)
+#define GET_RG_EQ_MU_FB_T3 (((REG32(ADR_WIFI_11B_RX_REG_009)) & 0x000f0000 ) >> 16)
+#define GET_RG_EQ_MU_FF_T3 (((REG32(ADR_WIFI_11B_RX_REG_009)) & 0x00f00000 ) >> 20)
+#define GET_RG_EQ_KI_T2 (((REG32(ADR_WIFI_11B_RX_REG_010)) & 0x00000700 ) >> 8)
+#define GET_RG_EQ_KP_T2 (((REG32(ADR_WIFI_11B_RX_REG_010)) & 0x00007000 ) >> 12)
+#define GET_RG_EQ_KI_T1 (((REG32(ADR_WIFI_11B_RX_REG_010)) & 0x00070000 ) >> 16)
+#define GET_RG_EQ_KP_T1 (((REG32(ADR_WIFI_11B_RX_REG_010)) & 0x00700000 ) >> 20)
+#define GET_RG_TR_LPF_RATE (((REG32(ADR_WIFI_11B_RX_REG_011)) & 0x003fffff ) >> 0)
+#define GET_RG_CE_BIT_CNT_LMT (((REG32(ADR_WIFI_11B_RX_REG_012)) & 0x0000007f ) >> 0)
+#define GET_RG_CE_CH_MAIN_SET (((REG32(ADR_WIFI_11B_RX_REG_012)) & 0x00000080 ) >> 7)
+#define GET_RG_TC_BIT_CNT_LMT (((REG32(ADR_WIFI_11B_RX_REG_012)) & 0x00007f00 ) >> 8)
+#define GET_RG_CR_BIT_CNT_LMT (((REG32(ADR_WIFI_11B_RX_REG_012)) & 0x007f0000 ) >> 16)
+#define GET_RG_TR_BIT_CNT_LMT (((REG32(ADR_WIFI_11B_RX_REG_012)) & 0x7f000000 ) >> 24)
+#define GET_RG_EQ_MAIN_TAP_MAN (((REG32(ADR_WIFI_11B_RX_REG_013)) & 0x00000001 ) >> 0)
+#define GET_RG_EQ_MAIN_TAP_COEF (((REG32(ADR_WIFI_11B_RX_REG_013)) & 0x07ff0000 ) >> 16)
+#define GET_RG_CCK_TR_KI_T2 (((REG32(ADR_WIFI_11B_RX_REG_014)) & 0x00000007 ) >> 0)
+#define GET_RG_CCK_TR_KP_T2 (((REG32(ADR_WIFI_11B_RX_REG_014)) & 0x00000070 ) >> 4)
+#define GET_RG_PWRON_DLY_TH_11B_RX (((REG32(ADR_WIFI_11B_RX_REG_039)) & 0x000000ff ) >> 0)
+#define GET_RG_SFD_BIT_CNT_LMT (((REG32(ADR_WIFI_11B_RX_REG_039)) & 0x00ff0000 ) >> 16)
+#define GET_RG_PWR_TH (((REG32(ADR_WIFI_11B_RX_REG_040)) & 0x0000ffff ) >> 0)
+#define GET_RG_PWR_CNT_TH (((REG32(ADR_WIFI_11B_RX_REG_040)) & 0x001f0000 ) >> 16)
+#define GET_RG_PWR_BIT_CNT_TH (((REG32(ADR_WIFI_11B_RX_REG_040)) & 0x0f000000 ) >> 24)
+#define GET_RG_PSDU_TIME_OFFSET_11B (((REG32(ADR_WIFI_11B_RX_REG_041)) & 0x0000ffff ) >> 0)
+#define GET_RG_RESERVED_11B_RX (((REG32(ADR_WIFI_11B_RX_REG_240)) & 0xffffffff ) >> 0)
+#define GET_RG_INTRUP_RX_11B_CLEAR (((REG32(ADR_WIFI_11B_RX_REG_241)) & 0x00000001 ) >> 0)
+#define GET_RG_INTRUP_RX_11B_MASK (((REG32(ADR_WIFI_11B_RX_REG_241)) & 0x00000010 ) >> 4)
+#define GET_RG_INTRUP_RX_11B_TRIG (((REG32(ADR_WIFI_11B_RX_REG_241)) & 0x00000f00 ) >> 8)
+#define GET_RO_INTRUP_RX_11B (((REG32(ADR_WIFI_11B_RX_REG_241)) & 0x00010000 ) >> 16)
+#define GET_RO_11B_FREQ_OS (((REG32(ADR_WIFI_11B_RX_REG_245)) & 0x000007ff ) >> 0)
+#define GET_RO_11B_SNR (((REG32(ADR_WIFI_11B_RX_REG_246)) & 0x0000007f ) >> 0)
+#define GET_RO_11B_RCPI (((REG32(ADR_WIFI_11B_RX_REG_246)) & 0x007f0000 ) >> 16)
+#define GET_RO_11B_CRC_CNT (((REG32(ADR_WIFI_11B_RX_REG_249)) & 0x0000ffff ) >> 0)
+#define GET_RO_11B_SFD_CNT (((REG32(ADR_WIFI_11B_RX_REG_249)) & 0xffff0000 ) >> 16)
+#define GET_RO_11B_PACKET_ERR_CNT (((REG32(ADR_WIFI_11B_RX_REG_250)) & 0x0000ffff ) >> 0)
+#define GET_RO_11B_PACKET_ERR (((REG32(ADR_WIFI_11B_RX_REG_250)) & 0x00010000 ) >> 16)
+#define GET_RO_11B_PACKET_CNT (((REG32(ADR_WIFI_11B_RX_REG_251)) & 0x0000ffff ) >> 0)
+#define GET_RO_11B_CCA_CNT (((REG32(ADR_WIFI_11B_RX_REG_251)) & 0xffff0000 ) >> 16)
+#define GET_RO_11B_LENGTH_FIELD (((REG32(ADR_WIFI_11B_RX_REG_252)) & 0x0000ffff ) >> 0)
+#define GET_RO_11B_SFD_FIELD (((REG32(ADR_WIFI_11B_RX_REG_252)) & 0xffff0000 ) >> 16)
+#define GET_RO_11B_SIGNAL_FIELD (((REG32(ADR_WIFI_11B_RX_REG_253)) & 0x000000ff ) >> 0)
+#define GET_RO_11B_SERVICE_FIELD (((REG32(ADR_WIFI_11B_RX_REG_253)) & 0x0000ff00 ) >> 8)
+#define GET_RO_11B_CRC_CORRECT (((REG32(ADR_WIFI_11B_RX_REG_253)) & 0x00010000 ) >> 16)
+#define GET_RG_RATE_STAT (((REG32(ADR_WIFI_11B_RX_REG_254)) & 0x00070000 ) >> 16)
+#define GET_RG_PACKET_STAT_EN_11B_RX (((REG32(ADR_WIFI_11B_RX_REG_254)) & 0x00100000 ) >> 20)
+#define GET_RG_BIT_REVERSE (((REG32(ADR_WIFI_11B_RX_REG_254)) & 0x00200000 ) >> 21)
+#define GET_RG_SOFT_RST_N_11B_RX (((REG32(ADR_WIFI_11B_RX_REG_255)) & 0x00000001 ) >> 0)
+#define GET_RG_CE_BYPASS_TAP (((REG32(ADR_WIFI_11B_RX_REG_255)) & 0x000000f0 ) >> 4)
+#define GET_RG_EQ_BYPASS_FBW_TAP (((REG32(ADR_WIFI_11B_RX_REG_255)) & 0x00000f00 ) >> 8)
+#define GET_RG_DEBUG_SEL_11B_RX (((REG32(ADR_WIFI_11B_RX_REG_255)) & 0x000f0000 ) >> 16)
+#define GET_RG_BIST_EN_TX_FFT (((REG32(ADR_WIFI_11GN_TX_MEM_BIST_REG)) & 0x00000001 ) >> 0)
+#define GET_RG_BIST_MODE_TX_FFT (((REG32(ADR_WIFI_11GN_TX_MEM_BIST_REG)) & 0x00000010 ) >> 4)
+#define GET_RO_BIST_DONE_TX_FFT_1 (((REG32(ADR_WIFI_11GN_TX_MEM_BIST_REG)) & 0x00010000 ) >> 16)
+#define GET_RO_BIST_FAIL_TX_FFT_1 (((REG32(ADR_WIFI_11GN_TX_MEM_BIST_REG)) & 0x00020000 ) >> 17)
+#define GET_RO_BIST_DONE_TX_FFT_0 (((REG32(ADR_WIFI_11GN_TX_MEM_BIST_REG)) & 0x00100000 ) >> 20)
+#define GET_RO_BIST_FAIL_TX_FFT_0 (((REG32(ADR_WIFI_11GN_TX_MEM_BIST_REG)) & 0x00200000 ) >> 21)
+#define GET_RG_BB_RISE_TIME_11GN_TX (((REG32(ADR_WIFI_11GN_TX_BB_RAMP_REG)) & 0x000000ff ) >> 0)
+#define GET_RG_BB_FALL_TIME_11GN_TX (((REG32(ADR_WIFI_11GN_TX_BB_RAMP_REG)) & 0x0000ff00 ) >> 8)
+#define GET_RG_TX_CLK_OUTER_EN (((REG32(ADR_WIFI_11GN_TX_CONTROL_REG)) & 0x00000001 ) >> 0)
+#define GET_RG_SHORT_GI_EN (((REG32(ADR_WIFI_11GN_TX_CONTROL_REG)) & 0x00000010 ) >> 4)
+#define GET_RG_STF_SCALE_20 (((REG32(ADR_WIFI_11GN_TX_STS_SCALE_REG)) & 0x000003ff ) >> 0)
+#define GET_RG_STF_SCALE_40 (((REG32(ADR_WIFI_11GN_TX_STS_SCALE_REG)) & 0x03ff0000 ) >> 16)
+#define GET_RG_FFT_SCALE_104 (((REG32(ADR_WIFI_11GN_TX_FFT_SCALE_REG0)) & 0x000003ff ) >> 0)
+#define GET_RG_FFT_SCALE_114 (((REG32(ADR_WIFI_11GN_TX_FFT_SCALE_REG0)) & 0x03ff0000 ) >> 16)
+#define GET_RG_FFT_SCALE_52 (((REG32(ADR_WIFI_11GN_TX_FFT_SCALE_REG1)) & 0x000003ff ) >> 0)
+#define GET_RG_FFT_SCALE_56 (((REG32(ADR_WIFI_11GN_TX_FFT_SCALE_REG1)) & 0x003ff000 ) >> 12)
+#define GET_RG_SCR_INIT_SEED (((REG32(ADR_WIFI_11GN_TX_FFT_SCALE_REG1)) & 0x7f000000 ) >> 24)
+#define GET_RG_SCR_SEED_MANUANL (((REG32(ADR_WIFI_11GN_TX_FFT_SCALE_REG1)) & 0x80000000 ) >> 31)
+#define GET_RO_TX_CNT_R_11GN_TX (((REG32(ADR_WIFI_11GN_TX_PKT_CNT_SENT_REG)) & 0xffffffff ) >> 0)
+#define GET_RG_DEBUG_SEL_11GN_TX (((REG32(ADR_WIFI_11GN_TX_DEBUG_SEL_REG)) & 0x00000f00 ) >> 8)
+#define GET_RG_RESERVED_11GN_TX (((REG32(ADR_WIFI_11GN_TX_RESERVED_REG)) & 0xffffffff ) >> 0)
+#define GET_RG_POS_DES_L_EXT_11GN_RX (((REG32(ADR_WIFI_11GN_RX_REG_000)) & 0x0000000f ) >> 0)
+#define GET_RG_PRE_DES_DLY_11GN_RX (((REG32(ADR_WIFI_11GN_RX_REG_000)) & 0x000000f0 ) >> 4)
+#define GET_RG_RESERVED_11GN_RX (((REG32(ADR_WIFI_11GN_RX_REG_001)) & 0xffffffff ) >> 0)
+#define GET_RG_HT40_TR_LPF_KI (((REG32(ADR_WIFI_11GN_RX_REG_002)) & 0x0000000f ) >> 0)
+#define GET_RG_HT40_TR_LPF_KP (((REG32(ADR_WIFI_11GN_RX_REG_002)) & 0x000000f0 ) >> 4)
+#define GET_RG_HT40_SYM_BOUND_CNT (((REG32(ADR_WIFI_11GN_RX_REG_002)) & 0x00007f00 ) >> 8)
+#define GET_RG_HT20_TR_LPF_KI (((REG32(ADR_WIFI_11GN_RX_REG_003)) & 0x0000000f ) >> 0)
+#define GET_RG_HT20_TR_LPF_KP (((REG32(ADR_WIFI_11GN_RX_REG_003)) & 0x000000f0 ) >> 4)
+#define GET_RG_TR_LPF_RATE_GN (((REG32(ADR_WIFI_11GN_RX_REG_003)) & 0x3fffff00 ) >> 8)
+#define GET_RG_CR_LPF_KI_GN (((REG32(ADR_WIFI_11GN_RX_REG_004_)) & 0x00000007 ) >> 0)
+#define GET_RG_HT20_SYM_BOUND_CNT (((REG32(ADR_WIFI_11GN_RX_REG_004_)) & 0x00007f00 ) >> 8)
+#define GET_RG_XSCOR32_RATIO (((REG32(ADR_WIFI_11GN_RX_REG_004_)) & 0x007f0000 ) >> 16)
+#define GET_RG_ATCOR64_CNT_LMT (((REG32(ADR_WIFI_11GN_RX_REG_004_)) & 0x7f000000 ) >> 24)
+#define GET_RG_ATCOR16_CNT_LMT2 (((REG32(ADR_WIFI_11GN_RX_REG_005)) & 0x00007f00 ) >> 8)
+#define GET_RG_ATCOR16_CNT_LMT1 (((REG32(ADR_WIFI_11GN_RX_REG_005)) & 0x007f0000 ) >> 16)
+#define GET_RG_ATCOR16_RATIO_SB (((REG32(ADR_WIFI_11GN_RX_REG_005)) & 0x7f000000 ) >> 24)
+#define GET_RG_XSCOR64_CNT_LMT2 (((REG32(ADR_WIFI_11GN_RX_REG_006_)) & 0x007f0000 ) >> 16)
+#define GET_RG_XSCOR64_CNT_LMT1 (((REG32(ADR_WIFI_11GN_RX_REG_006_)) & 0x7f000000 ) >> 24)
+#define GET_RG_HT20_RX_FFT_SCALE (((REG32(ADR_WIFI_11GN_RX_REG_007_)) & 0x000003ff ) >> 0)
+#define GET_RG_VITERBI_AB_SWAP (((REG32(ADR_WIFI_11GN_RX_REG_007_)) & 0x00010000 ) >> 16)
+#define GET_RG_ATCOR16_CNT_TH (((REG32(ADR_WIFI_11GN_RX_REG_007_)) & 0x0f000000 ) >> 24)
+#define GET_RG_NORMSQUARE_LOW_SNR_7 (((REG32(ADR_WIFI_11GN_RX_REG_008)) & 0x000000ff ) >> 0)
+#define GET_RG_NORMSQUARE_LOW_SNR_6 (((REG32(ADR_WIFI_11GN_RX_REG_008)) & 0x0000ff00 ) >> 8)
+#define GET_RG_NORMSQUARE_LOW_SNR_5 (((REG32(ADR_WIFI_11GN_RX_REG_008)) & 0x00ff0000 ) >> 16)
+#define GET_RG_NORMSQUARE_LOW_SNR_4 (((REG32(ADR_WIFI_11GN_RX_REG_008)) & 0xff000000 ) >> 24)
+#define GET_RG_NORMSQUARE_LOW_SNR_8 (((REG32(ADR_WIFI_11GN_RX_REG_009)) & 0xff000000 ) >> 24)
+#define GET_RG_NORMSQUARE_SNR_3 (((REG32(ADR_WIFI_11GN_RX_REG_010_)) & 0x000000ff ) >> 0)
+#define GET_RG_NORMSQUARE_SNR_2 (((REG32(ADR_WIFI_11GN_RX_REG_010_)) & 0x0000ff00 ) >> 8)
+#define GET_RG_NORMSQUARE_SNR_1 (((REG32(ADR_WIFI_11GN_RX_REG_010_)) & 0x00ff0000 ) >> 16)
+#define GET_RG_NORMSQUARE_SNR_0 (((REG32(ADR_WIFI_11GN_RX_REG_010_)) & 0xff000000 ) >> 24)
+#define GET_RG_NORMSQUARE_SNR_7 (((REG32(ADR_WIFI_11GN_RX_REG_011)) & 0x000000ff ) >> 0)
+#define GET_RG_NORMSQUARE_SNR_6 (((REG32(ADR_WIFI_11GN_RX_REG_011)) & 0x0000ff00 ) >> 8)
+#define GET_RG_NORMSQUARE_SNR_5 (((REG32(ADR_WIFI_11GN_RX_REG_011)) & 0x00ff0000 ) >> 16)
+#define GET_RG_NORMSQUARE_SNR_4 (((REG32(ADR_WIFI_11GN_RX_REG_011)) & 0xff000000 ) >> 24)
+#define GET_RG_NORMSQUARE_SNR_8 (((REG32(ADR_WIFI_11GN_RX_REG_012)) & 0xff000000 ) >> 24)
+#define GET_RG_SNR_TH_64QAM (((REG32(ADR_WIFI_11GN_RX_REG_013)) & 0x0000007f ) >> 0)
+#define GET_RG_SNR_TH_16QAM (((REG32(ADR_WIFI_11GN_RX_REG_013)) & 0x00007f00 ) >> 8)
+#define GET_RG_ATCOR16_CNT_PLUS_LMT2 (((REG32(ADR_WIFI_11GN_RX_REG_014)) & 0x0000007f ) >> 0)
+#define GET_RG_ATCOR16_CNT_PLUS_LMT1 (((REG32(ADR_WIFI_11GN_RX_REG_014)) & 0x00007f00 ) >> 8)
+#define GET_RG_SYM_BOUND_METHOD (((REG32(ADR_WIFI_11GN_RX_REG_014)) & 0x00030000 ) >> 16)
+#define GET_RG_HT40_RX_FFT_SCALE (((REG32(ADR_WIFI_11GN_RX_REG_015)) & 0x000003ff ) >> 0)
+#define GET_RG_ERASE_SC_NUM3 (((REG32(ADR_WIFI_11GN_RX_REG_016)) & 0x0000007f ) >> 0)
+#define GET_RG_SC_CTRL3 (((REG32(ADR_WIFI_11GN_RX_REG_016)) & 0x00000080 ) >> 7)
+#define GET_RG_ERASE_SC_NUM2 (((REG32(ADR_WIFI_11GN_RX_REG_016)) & 0x00007f00 ) >> 8)
+#define GET_RG_SC_CTRL2 (((REG32(ADR_WIFI_11GN_RX_REG_016)) & 0x00008000 ) >> 15)
+#define GET_RG_ERASE_SC_NUM1 (((REG32(ADR_WIFI_11GN_RX_REG_016)) & 0x007f0000 ) >> 16)
+#define GET_RG_SC_CTRL1 (((REG32(ADR_WIFI_11GN_RX_REG_016)) & 0x00800000 ) >> 23)
+#define GET_RG_ERASE_SC_NUM0 (((REG32(ADR_WIFI_11GN_RX_REG_016)) & 0x7f000000 ) >> 24)
+#define GET_RG_SC_CTRL0 (((REG32(ADR_WIFI_11GN_RX_REG_016)) & 0x80000000 ) >> 31)
+#define GET_RG_ERASE_SC_NUM7 (((REG32(ADR_WIFI_11GN_RX_REG_017)) & 0x0000007f ) >> 0)
+#define GET_RG_SC_CTRL7 (((REG32(ADR_WIFI_11GN_RX_REG_017)) & 0x00000080 ) >> 7)
+#define GET_RG_ERASE_SC_NUM6 (((REG32(ADR_WIFI_11GN_RX_REG_017)) & 0x00007f00 ) >> 8)
+#define GET_RG_SC_CTRL6 (((REG32(ADR_WIFI_11GN_RX_REG_017)) & 0x00008000 ) >> 15)
+#define GET_RG_ERASE_SC_NUM5 (((REG32(ADR_WIFI_11GN_RX_REG_017)) & 0x007f0000 ) >> 16)
+#define GET_RG_SC_CTRL5 (((REG32(ADR_WIFI_11GN_RX_REG_017)) & 0x00800000 ) >> 23)
+#define GET_RG_ERASE_SC_NUM4 (((REG32(ADR_WIFI_11GN_RX_REG_017)) & 0x7f000000 ) >> 24)
+#define GET_RG_SC_CTRL4 (((REG32(ADR_WIFI_11GN_RX_REG_017)) & 0x80000000 ) >> 31)
+#define GET_RG_BIST_EN_CCFO (((REG32(ADR_WIFI_11GN_RX_REG_032)) & 0x00000001 ) >> 0)
+#define GET_RG_BIST_MODE_CCFO (((REG32(ADR_WIFI_11GN_RX_REG_032)) & 0x00000010 ) >> 4)
+#define GET_RO_BIST_DONE_CCFO_1 (((REG32(ADR_WIFI_11GN_RX_REG_032)) & 0x00010000 ) >> 16)
+#define GET_RO_BIST_FAIL_CCFO_1 (((REG32(ADR_WIFI_11GN_RX_REG_032)) & 0x00020000 ) >> 17)
+#define GET_RO_BIST_DONE_CCFO_0 (((REG32(ADR_WIFI_11GN_RX_REG_032)) & 0x00100000 ) >> 20)
+#define GET_RO_BIST_FAIL_CCFO_0 (((REG32(ADR_WIFI_11GN_RX_REG_032)) & 0x00200000 ) >> 21)
+#define GET_RG_BIST_EN_VTB (((REG32(ADR_WIFI_11GN_RX_REG_033)) & 0x00000001 ) >> 0)
+#define GET_RG_BIST_MODE_VTB (((REG32(ADR_WIFI_11GN_RX_REG_033)) & 0x00000010 ) >> 4)
+#define GET_RO_BIST_DONE_VTB_3 (((REG32(ADR_WIFI_11GN_RX_REG_033)) & 0x00010000 ) >> 16)
+#define GET_RO_BIST_FAIL_VTB_3 (((REG32(ADR_WIFI_11GN_RX_REG_033)) & 0x00020000 ) >> 17)
+#define GET_RO_BIST_DONE_VTB_2 (((REG32(ADR_WIFI_11GN_RX_REG_033)) & 0x00100000 ) >> 20)
+#define GET_RO_BIST_FAIL_VTB_2 (((REG32(ADR_WIFI_11GN_RX_REG_033)) & 0x00200000 ) >> 21)
+#define GET_RO_BIST_DONE_VTB_1 (((REG32(ADR_WIFI_11GN_RX_REG_033)) & 0x01000000 ) >> 24)
+#define GET_RO_BIST_FAIL_VTB_1 (((REG32(ADR_WIFI_11GN_RX_REG_033)) & 0x02000000 ) >> 25)
+#define GET_RO_BIST_DONE_VTB_0 (((REG32(ADR_WIFI_11GN_RX_REG_033)) & 0x10000000 ) >> 28)
+#define GET_RO_BIST_FAIL_VTB_0 (((REG32(ADR_WIFI_11GN_RX_REG_033)) & 0x20000000 ) >> 29)
+#define GET_RG_PWRON_DLY_TH_11GN_RX (((REG32(ADR_WIFI_11GN_RX_REG_039)) & 0x000000ff ) >> 0)
+#define GET_RG_SB_START_CNT (((REG32(ADR_WIFI_11GN_RX_REG_039)) & 0x00007f00 ) >> 8)
+#define GET_RG_CCA_POW_CNT_TH (((REG32(ADR_WIFI_11GN_RX_REG_040)) & 0x000000f0 ) >> 4)
+#define GET_RG_CCA_POW_SHORT_CNT_LMT (((REG32(ADR_WIFI_11GN_RX_REG_040)) & 0x00000700 ) >> 8)
+#define GET_RG_CCA_POW_TH (((REG32(ADR_WIFI_11GN_RX_REG_040)) & 0xffff0000 ) >> 16)
+#define GET_RG_POW16_CNT_TH (((REG32(ADR_WIFI_11GN_RX_REG_048)) & 0x000000f0 ) >> 4)
+#define GET_RG_POW16_SHORT_CNT_LMT (((REG32(ADR_WIFI_11GN_RX_REG_048)) & 0x00000700 ) >> 8)
+#define GET_RG_POW16_TH_L (((REG32(ADR_WIFI_11GN_RX_REG_048)) & 0xff000000 ) >> 24)
+#define GET_RG_XSCOR16_SHORT_CNT_LMT (((REG32(ADR_WIFI_11GN_RX_REG_049)) & 0x00000007 ) >> 0)
+#define GET_RG_XSCOR16_RATIO (((REG32(ADR_WIFI_11GN_RX_REG_049)) & 0x00007f00 ) >> 8)
+#define GET_RG_ATCOR16_SHORT_CNT_LMT (((REG32(ADR_WIFI_11GN_RX_REG_049)) & 0x00070000 ) >> 16)
+#define GET_RG_ATCOR16_RATIO_CCD (((REG32(ADR_WIFI_11GN_RX_REG_049)) & 0x7f000000 ) >> 24)
+#define GET_RG_ATCOR64_ACC_LMT (((REG32(ADR_WIFI_11GN_RX_REG_050)) & 0x0000007f ) >> 0)
+#define GET_RG_ATCOR16_SHORT_CNT_LMT2 (((REG32(ADR_WIFI_11GN_RX_REG_050)) & 0x00070000 ) >> 16)
+#define GET_RG_CCFO_CNT_LMT (((REG32(ADR_WIFI_11GN_RX_REG_051)) & 0x0000007f ) >> 0)
+#define GET_RG_BYPASS_COARSE_FREQ (((REG32(ADR_WIFI_11GN_RX_REG_051)) & 0x00000100 ) >> 8)
+#define GET_RG_CCFO_GAIN_BY2 (((REG32(ADR_WIFI_11GN_RX_REG_051)) & 0x00000200 ) >> 9)
+#define GET_RG_XSCOR64_RATIO_SB (((REG32(ADR_WIFI_11GN_RX_REG_051)) & 0x007f0000 ) >> 16)
+#define GET_RG_5G_CCFO_CNT_LMT (((REG32(ADR_WIFI_11GN_RX_REG_052)) & 0x0000007f ) >> 0)
+#define GET_RG_5G_BYPASS_COARSE_FREQ (((REG32(ADR_WIFI_11GN_RX_REG_052)) & 0x00000100 ) >> 8)
+#define GET_RG_5G_CCFO_GAIN_BY2 (((REG32(ADR_WIFI_11GN_RX_REG_052)) & 0x00000200 ) >> 9)
+#define GET_RG_ACS_INI_PM_ALL0 (((REG32(ADR_WIFI_11GN_RX_REG_076)) & 0x00000001 ) >> 0)
+#define GET_RG_VITERBI_TB_BITS (((REG32(ADR_WIFI_11GN_RX_REG_076)) & 0xff000000 ) >> 24)
+#define GET_RG_CR_CNT_UPDATE_SGI (((REG32(ADR_WIFI_11GN_RX_REG_087)) & 0x000001ff ) >> 0)
+#define GET_RG_TR_CNT_UPDATE_SGI (((REG32(ADR_WIFI_11GN_RX_REG_087)) & 0x01ff0000 ) >> 16)
+#define GET_RG_CR_CNT_UPDATE (((REG32(ADR_WIFI_11GN_RX_REG_088)) & 0x000001ff ) >> 0)
+#define GET_RG_TR_CNT_UPDATE (((REG32(ADR_WIFI_11GN_RX_REG_088)) & 0x01ff0000 ) >> 16)
+#define GET_RG_CPE_SEL_64QAM (((REG32(ADR_WIFI_11GN_RX_REG_089)) & 0x00010000 ) >> 16)
+#define GET_RG_CPE_SEL_16QAM (((REG32(ADR_WIFI_11GN_RX_REG_089)) & 0x00020000 ) >> 17)
+#define GET_RG_CPE_SEL_QPSK (((REG32(ADR_WIFI_11GN_RX_REG_089)) & 0x00040000 ) >> 18)
+#define GET_RG_CPE_SEL_BPSK (((REG32(ADR_WIFI_11GN_RX_REG_089)) & 0x00080000 ) >> 19)
+#define GET_RG_BYPASS_CPE_MA (((REG32(ADR_WIFI_11GN_RX_REG_096)) & 0x00000010 ) >> 4)
+#define GET_RG_CHSMTH_COEF (((REG32(ADR_WIFI_11GN_RX_REG_098)) & 0x00030000 ) >> 16)
+#define GET_RG_CHSMTH_EN (((REG32(ADR_WIFI_11GN_RX_REG_098)) & 0x00040000 ) >> 18)
+#define GET_RG_CHEST_DD_FACTOR (((REG32(ADR_WIFI_11GN_RX_REG_098)) & 0x07000000 ) >> 24)
+#define GET_RG_CH_UPDATE (((REG32(ADR_WIFI_11GN_RX_REG_098)) & 0x80000000 ) >> 31)
+#define GET_RG_FMT_DET_MM_TH (((REG32(ADR_WIFI_11GN_RX_REG_100)) & 0x000000ff ) >> 0)
+#define GET_RG_FMT_DET_GF_TH (((REG32(ADR_WIFI_11GN_RX_REG_100)) & 0x0000ff00 ) >> 8)
+#define GET_RG_DO_NOT_CHECK_L_RATE (((REG32(ADR_WIFI_11GN_RX_REG_100)) & 0x02000000 ) >> 25)
+#define GET_RG_NEW_PILOT_AVG (((REG32(ADR_WIFI_11GN_RX_REG_101)) & 0x00000001 ) >> 0)
+#define GET_RG_NEW_SB (((REG32(ADR_WIFI_11GN_RX_REG_101)) & 0x00000010 ) >> 4)
+#define GET_RG_ATCOR64_FREQ_START (((REG32(ADR_WIFI_11GN_RX_REG_101)) & 0x00007f00 ) >> 8)
+#define GET_RG_L_LENGTH_MAX (((REG32(ADR_WIFI_11GN_RX_REG_101)) & 0x0fff0000 ) >> 16)
+#define GET_RG_ATCOR16_CCA_GAIN (((REG32(ADR_WIFI_11GN_RX_REG_101)) & 0x30000000 ) >> 28)
+#define GET_RG_PSDU_TIME_OFFSET_GF (((REG32(ADR_WIFI_11GN_RX_REG_102)) & 0x0000ffff ) >> 0)
+#define GET_RG_PSDU_TIME_OFFSET_MF (((REG32(ADR_WIFI_11GN_RX_REG_102)) & 0xffff0000 ) >> 16)
+#define GET_RG_PSDU_TIME_OFFSET_LEGACY (((REG32(ADR_WIFI_11GN_RX_REG_103)) & 0x0000ffff ) >> 0)
+#define GET_RG_INTRUP_RX_11GN_CLEAR (((REG32(ADR_WIFI_11GN_RX_REG_241)) & 0x00000001 ) >> 0)
+#define GET_RG_INTRUP_RX_11GN_MASK (((REG32(ADR_WIFI_11GN_RX_REG_241)) & 0x00000010 ) >> 4)
+#define GET_RG_INTRUP_RX_11GN_TRIG (((REG32(ADR_WIFI_11GN_RX_REG_241)) & 0x00000f00 ) >> 8)
+#define GET_RO_INTRUP_RX_11GN (((REG32(ADR_WIFI_11GN_RX_REG_241)) & 0x00010000 ) >> 16)
+#define GET_RO_STBC_PACKET_CNT (((REG32(ADR_WIFI_11GN_RX_REG_245)) & 0x0000ffff ) >> 0)
+#define GET_RO_STBC_PACKET_ERR_CNT (((REG32(ADR_WIFI_11GN_RX_REG_245)) & 0xffff0000 ) >> 16)
+#define GET_RO_11GN_SNR (((REG32(ADR_WIFI_11GN_RX_REG_246)) & 0x0000007f ) >> 0)
+#define GET_RO_11GN_NOISE_PWR (((REG32(ADR_WIFI_11GN_RX_REG_246)) & 0x00007f00 ) >> 8)
+#define GET_RO_11GN_RCPI (((REG32(ADR_WIFI_11GN_RX_REG_246)) & 0x007f0000 ) >> 16)
+#define GET_RO_11GN_SIGNAL_PWR (((REG32(ADR_WIFI_11GN_RX_REG_246)) & 0x7f000000 ) >> 24)
+#define GET_RO_11GN_FREQ_OS_LTS (((REG32(ADR_WIFI_11GN_RX_REG_247)) & 0x00007fff ) >> 0)
+#define GET_RO_11GN_HT_SIGNAL_FIELD_47_24 (((REG32(ADR_WIFI_11GN_RX_REG_248)) & 0x00ffffff ) >> 0)
+#define GET_RO_11GN_HT_SIGNAL_FIELD_23_0 (((REG32(ADR_WIFI_11GN_RX_REG_249)) & 0x00ffffff ) >> 0)
+#define GET_RO_11GN_PACKET_ERR_CNT (((REG32(ADR_WIFI_11GN_RX_REG_250)) & 0x0000ffff ) >> 0)
+#define GET_RO_11GN_SERVICE_FIELD (((REG32(ADR_WIFI_11GN_RX_REG_250)) & 0xffff0000 ) >> 16)
+#define GET_RO_11GN_PACKET_CNT (((REG32(ADR_WIFI_11GN_RX_REG_251)) & 0x0000ffff ) >> 0)
+#define GET_RO_11GN_CCA_CNT (((REG32(ADR_WIFI_11GN_RX_REG_251)) & 0xffff0000 ) >> 16)
+#define GET_RO_11GN_L_SIGNAL_FIELD (((REG32(ADR_WIFI_11GN_RX_REG_252)) & 0x00ffffff ) >> 0)
+#define GET_RO_AMPDU_PACKET_CNT (((REG32(ADR_WIFI_11GN_RX_REG_253)) & 0x0000ffff ) >> 0)
+#define GET_RO_AMPDU_PACKET_ERR_CNT (((REG32(ADR_WIFI_11GN_RX_REG_253)) & 0xffff0000 ) >> 16)
+#define GET_RG_DAGC_CNT_TH (((REG32(ADR_WIFI_11GN_RX_REG_254)) & 0x00000003 ) >> 0)
+#define GET_RG_RATE_MCS_STAT (((REG32(ADR_WIFI_11GN_RX_REG_254)) & 0x000f0000 ) >> 16)
+#define GET_RG_PACKET_STAT_EN_11GN_RX (((REG32(ADR_WIFI_11GN_RX_REG_254)) & 0x00100000 ) >> 20)
+#define GET_RG_SOFT_RST_N_11GN_RX (((REG32(ADR_WIFI_11GN_RX_REG_255)) & 0x00000001 ) >> 0)
+#define GET_RG_RIFS_EN (((REG32(ADR_WIFI_11GN_RX_REG_255)) & 0x00000002 ) >> 1)
+#define GET_RG_STBC_EN (((REG32(ADR_WIFI_11GN_RX_REG_255)) & 0x00000004 ) >> 2)
+#define GET_RG_COR_SEL (((REG32(ADR_WIFI_11GN_RX_REG_255)) & 0x00000008 ) >> 3)
+#define GET_RG_INI_PHASE (((REG32(ADR_WIFI_11GN_RX_REG_255)) & 0x00000030 ) >> 4)
+#define GET_RG_CCA_PWR_SEL (((REG32(ADR_WIFI_11GN_RX_REG_255)) & 0x00000200 ) >> 9)
+#define GET_RG_CCA_XSCOR_PWR_SEL (((REG32(ADR_WIFI_11GN_RX_REG_255)) & 0x00000400 ) >> 10)
+#define GET_RG_CCA_XSCOR_AVGPWR_SEL (((REG32(ADR_WIFI_11GN_RX_REG_255)) & 0x00000800 ) >> 11)
+#define GET_RG_DEBUG_SEL_11GN_RX (((REG32(ADR_WIFI_11GN_RX_REG_255)) & 0x0000f000 ) >> 12)
+#define GET_RG_POST_CLK_EN (((REG32(ADR_WIFI_11GN_RX_REG_255)) & 0x00010000 ) >> 16)
+#define GET_RG_THL_ED (((REG32(ADR_WIFI_RADAR_REG_00)) & 0x0000003f ) >> 0)
+#define GET_RG_THH_ED (((REG32(ADR_WIFI_RADAR_REG_00)) & 0x00003f00 ) >> 8)
+#define GET_RG_THL_RATIO (((REG32(ADR_WIFI_RADAR_REG_00)) & 0x00ff0000 ) >> 16)
+#define GET_RG_THH_RATIO (((REG32(ADR_WIFI_RADAR_REG_00)) & 0xff000000 ) >> 24)
+#define GET_RG_PW_MIN (((REG32(ADR_WIFI_RADAR_REG_01)) & 0x00000fff ) >> 0)
+#define GET_RG_PW_MAX (((REG32(ADR_WIFI_RADAR_REG_01)) & 0x0fff0000 ) >> 16)
+#define GET_RG_PERIOD_MIN (((REG32(ADR_WIFI_RADAR_REG_02)) & 0x00000fff ) >> 0)
+#define GET_RG_PERIOD_MAX (((REG32(ADR_WIFI_RADAR_REG_02)) & 0x0fff0000 ) >> 16)
+#define GET_RG_TIME_PERIOD (((REG32(ADR_WIFI_RADAR_REG_03)) & 0x00000fff ) >> 0)
+#define GET_RG_PULSE_NUMBER (((REG32(ADR_WIFI_RADAR_REG_03)) & 0x00700000 ) >> 20)
+#define GET_RG_ALPHA_FINE (((REG32(ADR_WIFI_RADAR_REG_03)) & 0x07000000 ) >> 24)
+#define GET_RG_ALPHA_COARSE (((REG32(ADR_WIFI_RADAR_REG_03)) & 0x30000000 ) >> 28)
+#define GET_RG_RADAR_EN (((REG32(ADR_WIFI_RADAR_REG_04)) & 0x00000001 ) >> 0)
+#define GET_RG_TOLERANCE_PERIOD (((REG32(ADR_WIFI_RADAR_REG_04)) & 0x003f0000 ) >> 16)
+#define GET_RG_TOLERANCE_PW (((REG32(ADR_WIFI_RADAR_REG_04)) & 0x3f000000 ) >> 24)
+#define GET_RO_RADAR_DET_NUM (((REG32(ADR_WIFI_RADAR_REG_RO)) & 0x00000007 ) >> 0)
+#define GET_RO_RADAR_DET_OUT (((REG32(ADR_WIFI_RADAR_REG_RO)) & 0x00000010 ) >> 4)
+#define GET_RO_RADAR_VALID (((REG32(ADR_WIFI_RADAR_REG_RO)) & 0x00000100 ) >> 8)
+#define GET_RO_PW (((REG32(ADR_WIFI_RADAR_REG_RO)) & 0x0fff0000 ) >> 16)
+#define GET_RO_PW_ARRAY_0 (((REG32(ADR_WIFI_RADAR_REG_DB_A0_RO)) & 0x00000fff ) >> 0)
+#define GET_RO_PW_ARRAY_1 (((REG32(ADR_WIFI_RADAR_REG_DB_A0_RO)) & 0x0fff0000 ) >> 16)
+#define GET_RO_PW_ARRAY_2 (((REG32(ADR_WIFI_RADAR_REG_DB_A1_RO)) & 0x00000fff ) >> 0)
+#define GET_RO_PW_ARRAY_3 (((REG32(ADR_WIFI_RADAR_REG_DB_A1_RO)) & 0x0fff0000 ) >> 16)
+#define GET_RO_PW_ARRAY_4 (((REG32(ADR_WIFI_RADAR_REG_DB_A2_RO)) & 0x00000fff ) >> 0)
+#define GET_RO_PW_ARRAY_5 (((REG32(ADR_WIFI_RADAR_REG_DB_A2_RO)) & 0x0fff0000 ) >> 16)
+#define GET_RO_PERIOD_ARRAY_0 (((REG32(ADR_WIFI_RADAR_REG_DB_P0_RO)) & 0x00000fff ) >> 0)
+#define GET_RO_PERIOD_ARRAY_1 (((REG32(ADR_WIFI_RADAR_REG_DB_P0_RO)) & 0x0fff0000 ) >> 16)
+#define GET_RO_PERIOD_ARRAY_2 (((REG32(ADR_WIFI_RADAR_REG_DB_P1_RO)) & 0x00000fff ) >> 0)
+#define GET_RO_PERIOD_ARRAY_3 (((REG32(ADR_WIFI_RADAR_REG_DB_P1_RO)) & 0x0fff0000 ) >> 16)
+#define GET_RO_PERIOD_ARRAY_4 (((REG32(ADR_WIFI_RADAR_REG_DB_P2_RO)) & 0x00000fff ) >> 0)
+#define GET_RO_PERIOD_ARRAY_5 (((REG32(ADR_WIFI_RADAR_REG_DB_P2_RO)) & 0x0fff0000 ) >> 16)
+#define GET_RG_PW_CHIRP_MIN (((REG32(ADR_WIFI_RADAR_CHIRP_REG)) & 0x00000fff ) >> 0)
+#define GET_RG_PW_CHIRP_MAX (((REG32(ADR_WIFI_RADAR_CHIRP_REG)) & 0x0fff0000 ) >> 16)
+#define GET_CPU_QUE_POP_ALT (((REG32(ADR_MB_CPU_INT_ALT)) & 0x00000001 ) >> 0)
+#define GET_CPU_INT_ALT (((REG32(ADR_MB_CPU_INT_ALT)) & 0x00000004 ) >> 2)
+#define GET_CPU_QUE_POP (((REG32(ADR_MB_CPU_INT)) & 0x00000001 ) >> 0)
+#define GET_CPU_INT (((REG32(ADR_MB_CPU_INT)) & 0x00000004 ) >> 2)
+#define GET_CPU_ID_TB0 (((REG32(ADR_CPU_ID_TB0)) & 0xffffffff ) >> 0)
+#define GET_CPU_ID_TB1 (((REG32(ADR_CPU_ID_TB1)) & 0xffffffff ) >> 0)
+#define GET_PKTID (((REG32(ADR_CH0_TRIG_1)) & 0x0000007f ) >> 0)
+#define GET_HWID (((REG32(ADR_CH0_TRIG_1)) & 0x00000780 ) >> 7)
+#define GET_CH0_INT_ADDR (((REG32(ADR_CH0_TRIG_0)) & 0xffffffff ) >> 0)
+#define GET_PRIPKTID (((REG32(ADR_CH0_PRI_TRIG)) & 0x0000007f ) >> 0)
+#define GET_PRIHWID (((REG32(ADR_CH0_PRI_TRIG)) & 0x00000780 ) >> 7)
+#define GET_CH0_FULL (((REG32(ADR_MCU_STATUS)) & 0x00000001 ) >> 0)
+#define GET_FF0_EMPTY (((REG32(ADR_MCU_STATUS)) & 0x00000002 ) >> 1)
+#define GET_CH2_FULL (((REG32(ADR_MCU_STATUS)) & 0x00000010 ) >> 4)
+#define GET_FF2_EMPTY (((REG32(ADR_MCU_STATUS)) & 0x00000020 ) >> 5)
+#define GET_RLS_BUSY (((REG32(ADR_MCU_STATUS)) & 0x00000200 ) >> 9)
+#define GET_RLS_COUNT_CLR (((REG32(ADR_MCU_STATUS)) & 0x00000400 ) >> 10)
+#define GET_RTN_COUNT_CLR (((REG32(ADR_MCU_STATUS)) & 0x00000800 ) >> 11)
+#define GET_RLS_COUNT (((REG32(ADR_MCU_STATUS)) & 0x00ff0000 ) >> 16)
+#define GET_RTN_COUNT (((REG32(ADR_MCU_STATUS)) & 0xff000000 ) >> 24)
+#define GET_FF0_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x0000001f ) >> 0)
+#define GET_FF1_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x000001e0 ) >> 5)
+#define GET_FF3_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x00003800 ) >> 11)
+#define GET_FF5_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x000e0000 ) >> 17)
+#define GET_FF6_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x00700000 ) >> 20)
+#define GET_FF7_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x03800000 ) >> 23)
+#define GET_FF8_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x1c000000 ) >> 26)
+#define GET_FF9_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0xe0000000 ) >> 29)
+#define GET_FF10_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00000007 ) >> 0)
+#define GET_FF11_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00000038 ) >> 3)
+#define GET_FF12_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x000001c0 ) >> 6)
+#define GET_FF13_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00000e00 ) >> 9)
+#define GET_FF14_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00007000 ) >> 12)
+#define GET_FF15_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00038000 ) >> 15)
+#define GET_FF4_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x007c0000 ) >> 18)
+#define GET_FF2_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x03800000 ) >> 23)
+#define GET_CH0_FULL_ALT (((REG32(ADR_RD_FFIN_FULL)) & 0x00000001 ) >> 0)
+#define GET_CH1_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000002 ) >> 1)
+#define GET_CH2_FULL_ALT (((REG32(ADR_RD_FFIN_FULL)) & 0x00000004 ) >> 2)
+#define GET_CH3_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000008 ) >> 3)
+#define GET_CH4_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000010 ) >> 4)
+#define GET_CH5_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000020 ) >> 5)
+#define GET_CH6_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000040 ) >> 6)
+#define GET_CH7_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000080 ) >> 7)
+#define GET_CH8_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000100 ) >> 8)
+#define GET_CH9_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000200 ) >> 9)
+#define GET_CH10_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000400 ) >> 10)
+#define GET_CH11_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000800 ) >> 11)
+#define GET_CH12_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00001000 ) >> 12)
+#define GET_CH13_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00002000 ) >> 13)
+#define GET_CH14_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00004000 ) >> 14)
+#define GET_CH15_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00008000 ) >> 15)
+#define GET_PKTID_ALT (((REG32(ADR_CH2_TRIG_ALT)) & 0x0000007f ) >> 0)
+#define GET_HWID_ALT (((REG32(ADR_CH2_TRIG_ALT)) & 0x00000780 ) >> 7)
+#define GET_CH2_INT_ADDR_ALT (((REG32(ADR_CH2_INT_ADDR_ALT)) & 0xffffffff ) >> 0)
+#define GET_HALT_CH1 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000002 ) >> 1)
+#define GET_HALT_CH3 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000008 ) >> 3)
+#define GET_HALT_CH4 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000010 ) >> 4)
+#define GET_HALT_CH5 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000020 ) >> 5)
+#define GET_HALT_CH6 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000040 ) >> 6)
+#define GET_HALT_CH7 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000080 ) >> 7)
+#define GET_HALT_CH8 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000100 ) >> 8)
+#define GET_HALT_CH9 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000200 ) >> 9)
+#define GET_HALT_CH10 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000400 ) >> 10)
+#define GET_HALT_CH11 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000800 ) >> 11)
+#define GET_HALT_CH12 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00001000 ) >> 12)
+#define GET_HALT_CH13 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00002000 ) >> 13)
+#define GET_HALT_CH14 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00004000 ) >> 14)
+#define GET_STOP_MBOX_OUT (((REG32(ADR_MBOX_HALT_CFG)) & 0x00010000 ) >> 16)
+#define GET_STOP_MBOX_IN (((REG32(ADR_MBOX_HALT_CFG)) & 0x00020000 ) >> 17)
+#define GET_MB_ERR_AUTO_HALT_EN (((REG32(ADR_MBOX_HALT_CFG)) & 0x00100000 ) >> 20)
+#define GET_MB_EXCEPT_CLR (((REG32(ADR_MBOX_HALT_CFG)) & 0x00200000 ) >> 21)
+#define GET_CH1_HALT_STS (((REG32(ADR_MBOX_HALT_STS)) & 0x00000002 ) >> 1)
+#define GET_CH3_HALT_STS (((REG32(ADR_MBOX_HALT_STS)) & 0x00000008 ) >> 3)
+#define GET_CH4_HALT_STS (((REG32(ADR_MBOX_HALT_STS)) & 0x00000010 ) >> 4)
+#define GET_CH5_HALT_STS (((REG32(ADR_MBOX_HALT_STS)) & 0x00000020 ) >> 5)
+#define GET_CH6_HALT_STS (((REG32(ADR_MBOX_HALT_STS)) & 0x00000040 ) >> 6)
+#define GET_CH7_HALT_STS (((REG32(ADR_MBOX_HALT_STS)) & 0x00000080 ) >> 7)
+#define GET_CH8_HALT_STS (((REG32(ADR_MBOX_HALT_STS)) & 0x00000100 ) >> 8)
+#define GET_CH9_HALT_STS (((REG32(ADR_MBOX_HALT_STS)) & 0x00000200 ) >> 9)
+#define GET_CH10_HALT_STS (((REG32(ADR_MBOX_HALT_STS)) & 0x00000400 ) >> 10)
+#define GET_CH11_HALT_STS (((REG32(ADR_MBOX_HALT_STS)) & 0x00000800 ) >> 11)
+#define GET_CH12_HALT_STS (((REG32(ADR_MBOX_HALT_STS)) & 0x00001000 ) >> 12)
+#define GET_CH13_HALT_STS (((REG32(ADR_MBOX_HALT_STS)) & 0x00002000 ) >> 13)
+#define GET_CH14_HALT_STS (((REG32(ADR_MBOX_HALT_STS)) & 0x00004000 ) >> 14)
+#define GET_STOP_MBOX_OUT_SUCCESS (((REG32(ADR_MBOX_HALT_STS)) & 0x00010000 ) >> 16)
+#define GET_MB_EXCEPT_CASE (((REG32(ADR_MBOX_HALT_STS)) & 0xff000000 ) >> 24)
+#define GET_MB_DBG_TIME_STEP (((REG32(ADR_MB_DBG_CFG1)) & 0x0000ffff ) >> 0)
+#define GET_DBG_TYPE (((REG32(ADR_MB_DBG_CFG1)) & 0x00030000 ) >> 16)
+#define GET_MB_DBG_CLR (((REG32(ADR_MB_DBG_CFG1)) & 0x00040000 ) >> 18)
+#define GET_DBG_ALC_LOG_EN (((REG32(ADR_MB_DBG_CFG1)) & 0x00080000 ) >> 19)
+#define GET_MB_DBG_COUNTER_EN (((REG32(ADR_MB_DBG_CFG1)) & 0x01000000 ) >> 24)
+#define GET_MB_DBG_EN (((REG32(ADR_MB_DBG_CFG1)) & 0x80000000 ) >> 31)
+#define GET_MB_DBG_RECORD_CNT (((REG32(ADR_MB_DBG_CFG2)) & 0x0000ffff ) >> 0)
+#define GET_MB_DBG_LENGTH (((REG32(ADR_MB_DBG_CFG2)) & 0xffff0000 ) >> 16)
+#define GET_MB_DBG_CFG_ADDR (((REG32(ADR_MB_DBG_CFG3)) & 0xffffffff ) >> 0)
+#define GET_DBG_HWID0_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000001 ) >> 0)
+#define GET_DBG_HWID1_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000002 ) >> 1)
+#define GET_DBG_HWID2_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000004 ) >> 2)
+#define GET_DBG_HWID3_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000008 ) >> 3)
+#define GET_DBG_HWID4_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000010 ) >> 4)
+#define GET_DBG_HWID5_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000020 ) >> 5)
+#define GET_DBG_HWID6_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000040 ) >> 6)
+#define GET_DBG_HWID7_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000080 ) >> 7)
+#define GET_DBG_HWID8_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000100 ) >> 8)
+#define GET_DBG_HWID9_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000200 ) >> 9)
+#define GET_DBG_HWID10_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000400 ) >> 10)
+#define GET_DBG_HWID11_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000800 ) >> 11)
+#define GET_DBG_HWID12_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00001000 ) >> 12)
+#define GET_DBG_HWID13_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00002000 ) >> 13)
+#define GET_DBG_HWID14_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00004000 ) >> 14)
+#define GET_DBG_HWID15_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00008000 ) >> 15)
+#define GET_DBG_HWID0_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00010000 ) >> 16)
+#define GET_DBG_HWID1_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00020000 ) >> 17)
+#define GET_DBG_HWID2_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00040000 ) >> 18)
+#define GET_DBG_HWID3_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00080000 ) >> 19)
+#define GET_DBG_HWID4_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00100000 ) >> 20)
+#define GET_DBG_HWID5_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00200000 ) >> 21)
+#define GET_DBG_HWID6_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00400000 ) >> 22)
+#define GET_DBG_HWID7_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00800000 ) >> 23)
+#define GET_DBG_HWID8_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x01000000 ) >> 24)
+#define GET_DBG_HWID9_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x02000000 ) >> 25)
+#define GET_DBG_HWID10_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x04000000 ) >> 26)
+#define GET_DBG_HWID11_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x08000000 ) >> 27)
+#define GET_DBG_HWID12_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x10000000 ) >> 28)
+#define GET_DBG_HWID13_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x20000000 ) >> 29)
+#define GET_DBG_HWID14_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x40000000 ) >> 30)
+#define GET_DBG_HWID15_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x80000000 ) >> 31)
+#define GET_MB_OUT_QUEUE_EN (((REG32(ADR_MB_OUT_QUEUE_CFG)) & 0x00000002 ) >> 1)
+#define GET_OUT_QUEUE_FLUSH_ID (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x0000007f ) >> 0)
+#define GET_OUT_QUEUE_FLUSH_MODE (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000003 ) >> 0)
+#define GET_OUT_QUEUE_FLUSH_SEL (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000f00 ) >> 8)
+#define GET_FFO0_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x0000001f ) >> 0)
+#define GET_FFO1_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x000003e0 ) >> 5)
+#define GET_FFO2_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x00003c00 ) >> 10)
+#define GET_FFO3_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x000f8000 ) >> 15)
+#define GET_FFO4_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x00300000 ) >> 20)
+#define GET_FFO5_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x0e000000 ) >> 25)
+#define GET_FFO6_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x0000000f ) >> 0)
+#define GET_FFO7_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x000003e0 ) >> 5)
+#define GET_FFO8_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x00007c00 ) >> 10)
+#define GET_FFO9_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x000f8000 ) >> 15)
+#define GET_FFO10_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x00f00000 ) >> 20)
+#define GET_FFO11_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x3e000000 ) >> 25)
+#define GET_FFO12_CNT (((REG32(ADR_RD_FFOUT_CNT3)) & 0x00000007 ) >> 0)
+#define GET_FFO13_CNT (((REG32(ADR_RD_FFOUT_CNT3)) & 0x00000060 ) >> 5)
+#define GET_FFO14_CNT (((REG32(ADR_RD_FFOUT_CNT3)) & 0x00007c00 ) >> 10)
+#define GET_FFO15_CNT (((REG32(ADR_RD_FFOUT_CNT3)) & 0x00078000 ) >> 15)
+#define GET_CH0_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000001 ) >> 0)
+#define GET_CH1_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000002 ) >> 1)
+#define GET_CH2_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000004 ) >> 2)
+#define GET_CH3_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000008 ) >> 3)
+#define GET_CH4_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000010 ) >> 4)
+#define GET_CH5_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000020 ) >> 5)
+#define GET_CH6_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000040 ) >> 6)
+#define GET_CH7_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000080 ) >> 7)
+#define GET_CH8_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000100 ) >> 8)
+#define GET_CH9_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000200 ) >> 9)
+#define GET_CH10_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000400 ) >> 10)
+#define GET_CH11_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000800 ) >> 11)
+#define GET_CH12_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00001000 ) >> 12)
+#define GET_CH13_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00002000 ) >> 13)
+#define GET_CH14_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00004000 ) >> 14)
+#define GET_CH15_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00008000 ) >> 15)
+#define GET_CH0_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000001 ) >> 0)
+#define GET_CH1_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000002 ) >> 1)
+#define GET_CH2_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000004 ) >> 2)
+#define GET_CH3_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000008 ) >> 3)
+#define GET_CH4_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000010 ) >> 4)
+#define GET_CH5_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000020 ) >> 5)
+#define GET_CH6_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000040 ) >> 6)
+#define GET_CH7_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000080 ) >> 7)
+#define GET_CH8_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000100 ) >> 8)
+#define GET_CH9_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000200 ) >> 9)
+#define GET_CH10_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000400 ) >> 10)
+#define GET_CH11_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000800 ) >> 11)
+#define GET_CH12_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00001000 ) >> 12)
+#define GET_CH13_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00002000 ) >> 13)
+#define GET_CH14_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00004000 ) >> 14)
+#define GET_CH15_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00008000 ) >> 15)
+#define GET_MB_LOW_THOLD_EN (((REG32(ADR_MB_THRESHOLD6)) & 0x80000000 ) >> 31)
+#define GET_CH0_LOWTHOLD (((REG32(ADR_MB_THRESHOLD7)) & 0x0000001f ) >> 0)
+#define GET_CH1_LOWTHOLD (((REG32(ADR_MB_THRESHOLD7)) & 0x00001f00 ) >> 8)
+#define GET_CH2_LOWTHOLD (((REG32(ADR_MB_THRESHOLD7)) & 0x001f0000 ) >> 16)
+#define GET_CH3_LOWTHOLD (((REG32(ADR_MB_THRESHOLD7)) & 0x1f000000 ) >> 24)
+#define GET_CH4_LOWTHOLD (((REG32(ADR_MB_THRESHOLD8)) & 0x0000001f ) >> 0)
+#define GET_CH5_LOWTHOLD (((REG32(ADR_MB_THRESHOLD8)) & 0x00001f00 ) >> 8)
+#define GET_CH6_LOWTHOLD (((REG32(ADR_MB_THRESHOLD8)) & 0x001f0000 ) >> 16)
+#define GET_CH7_LOWTHOLD (((REG32(ADR_MB_THRESHOLD8)) & 0x1f000000 ) >> 24)
+#define GET_CH8_LOWTHOLD (((REG32(ADR_MB_THRESHOLD9)) & 0x0000001f ) >> 0)
+#define GET_CH9_LOWTHOLD (((REG32(ADR_MB_THRESHOLD9)) & 0x00001f00 ) >> 8)
+#define GET_CH10_LOWTHOLD (((REG32(ADR_MB_THRESHOLD9)) & 0x001f0000 ) >> 16)
+#define GET_CH11_LOWTHOLD (((REG32(ADR_MB_THRESHOLD9)) & 0x1f000000 ) >> 24)
+#define GET_CH12_LOWTHOLD (((REG32(ADR_MB_THRESHOLD10)) & 0x0000001f ) >> 0)
+#define GET_CH13_LOWTHOLD (((REG32(ADR_MB_THRESHOLD10)) & 0x00001f00 ) >> 8)
+#define GET_CH14_LOWTHOLD (((REG32(ADR_MB_THRESHOLD10)) & 0x001f0000 ) >> 16)
+#define GET_CH15_LOWTHOLD (((REG32(ADR_MB_THRESHOLD10)) & 0x1f000000 ) >> 24)
+#define GET_TRASH_TIMEOUT_EN (((REG32(ADR_MB_TRASH_CFG)) & 0x00000001 ) >> 0)
+#define GET_TRASH_CAN_INT (((REG32(ADR_MB_TRASH_CFG)) & 0x00000002 ) >> 1)
+#define GET_TRASH_INT_ID (((REG32(ADR_MB_TRASH_CFG)) & 0x000007f0 ) >> 4)
+#define GET_TRASH_TIMEOUT (((REG32(ADR_MB_TRASH_CFG)) & 0x03ff0000 ) >> 16)
+#define GET_IN_FIFO_FLUSH_ID (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x000007ff ) >> 0)
+#define GET_IN_FIFO_FLUSH_MODE (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000003 ) >> 0)
+#define GET_IN_FIFO_FLUSH_SEL (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000f00 ) >> 8)
+#define GET_CPU_ID_TB2 (((REG32(ADR_CPU_ID_TB2)) & 0xffffffff ) >> 0)
+#define GET_CPU_ID_TB3 (((REG32(ADR_CPU_ID_TB3)) & 0xffffffff ) >> 0)
+#define GET_IQ_LOG_EN (((REG32(ADR_PHY_IQ_LOG_CFG0)) & 0x00000001 ) >> 0)
+#define GET_IQ_LOG_STOP_MODE (((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0x00000001 ) >> 0)
+#define GET_IQ_LOG_TIMER (((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0xffff0000 ) >> 16)
+#define GET_IQ_LOG_LEN (((REG32(ADR_PHY_IQ_LOG_LEN)) & 0x0000ffff ) >> 0)
+#define GET_IQ_LOG_ST_ADR (((REG32(ADR_PHY_IQ_LOG_LEN)) & 0xffff0000 ) >> 16)
+#define GET_IQ_LOG_TAIL_ADR (((REG32(ADR_PHY_IQ_LOG_PTR)) & 0x0000ffff ) >> 0)
+#define GET_ALC_LENG (((REG32(ADR_WR_ALC)) & 0x0003ffff ) >> 0)
+#define GET_CH0_DYN_PRI (((REG32(ADR_WR_ALC)) & 0x00300000 ) >> 20)
+#define GET_MCU_PKTID (((REG32(ADR_GETID)) & 0xffffffff ) >> 0)
+#define GET_CH0_STA_PRI (((REG32(ADR_CH_STA_PRI)) & 0x00000003 ) >> 0)
+#define GET_CH1_STA_PRI (((REG32(ADR_CH_STA_PRI)) & 0x00000030 ) >> 4)
+#define GET_CH2_STA_PRI (((REG32(ADR_CH_STA_PRI)) & 0x00000300 ) >> 8)
+#define GET_CH3_STA_PRI (((REG32(ADR_CH_STA_PRI)) & 0x00003000 ) >> 12)
+#define GET_ID_TB0 (((REG32(ADR_RD_ID0)) & 0xffffffff ) >> 0)
+#define GET_ID_TB1 (((REG32(ADR_RD_ID1)) & 0xffffffff ) >> 0)
+#define GET_ID_MNG_HALT (((REG32(ADR_IMD_CFG)) & 0x00000010 ) >> 4)
+#define GET_ID_MNG_ERR_HALT_EN (((REG32(ADR_IMD_CFG)) & 0x00000020 ) >> 5)
+#define GET_ID_EXCEPT_FLG_CLR (((REG32(ADR_IMD_CFG)) & 0x00000040 ) >> 6)
+#define GET_ID_EXCEPT_FLG (((REG32(ADR_IMD_CFG)) & 0x00000080 ) >> 7)
+#define GET_ID_FULL (((REG32(ADR_IMD_STA)) & 0x00000001 ) >> 0)
+#define GET_ID_MNG_BUSY (((REG32(ADR_IMD_STA)) & 0x00000002 ) >> 1)
+#define GET_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000004 ) >> 2)
+#define GET_CH0_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000010 ) >> 4)
+#define GET_CH1_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000020 ) >> 5)
+#define GET_CH2_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000040 ) >> 6)
+#define GET_CH3_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000080 ) >> 7)
+#define GET_REQ_LOCK_INT_EN (((REG32(ADR_IMD_STA)) & 0x00000100 ) >> 8)
+#define GET_REQ_LOCK_INT (((REG32(ADR_IMD_STA)) & 0x00000200 ) >> 9)
+#define GET_MCU_ALC_READY (((REG32(ADR_ALC_STA)) & 0x00000001 ) >> 0)
+#define GET_ALC_FAIL (((REG32(ADR_ALC_STA)) & 0x00000002 ) >> 1)
+#define GET_ALC_BUSY (((REG32(ADR_ALC_STA)) & 0x00000004 ) >> 2)
+#define GET_CH0_NVLD (((REG32(ADR_ALC_STA)) & 0x00000010 ) >> 4)
+#define GET_CH1_NVLD (((REG32(ADR_ALC_STA)) & 0x00000020 ) >> 5)
+#define GET_CH2_NVLD (((REG32(ADR_ALC_STA)) & 0x00000040 ) >> 6)
+#define GET_CH3_NVLD (((REG32(ADR_ALC_STA)) & 0x00000080 ) >> 7)
+#define GET_ALC_INT_ID (((REG32(ADR_ALC_STA)) & 0x00007f00 ) >> 8)
+#define GET_ALC_TIMEOUT (((REG32(ADR_ALC_STA)) & 0x03ff0000 ) >> 16)
+#define GET_ALC_TIMEOUT_INT_EN (((REG32(ADR_ALC_STA)) & 0x40000000 ) >> 30)
+#define GET_ALC_TIMEOUT_INT (((REG32(ADR_ALC_STA)) & 0x80000000 ) >> 31)
+#define GET_TX_ID_COUNT (((REG32(ADR_TRX_ID_COUNT)) & 0x000000ff ) >> 0)
+#define GET_RX_ID_COUNT (((REG32(ADR_TRX_ID_COUNT)) & 0x0000ff00 ) >> 8)
+#define GET_TX_ID_THOLD (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x000000ff ) >> 0)
+#define GET_RX_ID_THOLD (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x0000ff00 ) >> 8)
+#define GET_ID_THOLD_RX_INT (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x00010000 ) >> 16)
+#define GET_RX_INT_CH (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x000e0000 ) >> 17)
+#define GET_ID_THOLD_TX_INT (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x00100000 ) >> 20)
+#define GET_TX_INT_CH (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x00e00000 ) >> 21)
+#define GET_ID_THOLD_INT_EN (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x01000000 ) >> 24)
+#define GET_TX_ID_TB0 (((REG32(ADR_TX_ID0)) & 0xffffffff ) >> 0)
+#define GET_TX_ID_TB1 (((REG32(ADR_TX_ID1)) & 0xffffffff ) >> 0)
+#define GET_RX_ID_TB0 (((REG32(ADR_RX_ID0)) & 0xffffffff ) >> 0)
+#define GET_RX_ID_TB1 (((REG32(ADR_RX_ID1)) & 0xffffffff ) >> 0)
+#define GET_DOUBLE_RLS_INT_EN (((REG32(ADR_RTN_STA)) & 0x00000001 ) >> 0)
+#define GET_ID_DOUBLE_RLS_INT (((REG32(ADR_RTN_STA)) & 0x00000002 ) >> 1)
+#define GET_DOUBLE_RLS_ID (((REG32(ADR_RTN_STA)) & 0x00007f00 ) >> 8)
+#define GET_ID_LEN_THOLD_INT_EN (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00000001 ) >> 0)
+#define GET_ALL_ID_LEN_THOLD_INT (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00000002 ) >> 1)
+#define GET_TX_ID_LEN_THOLD_INT (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00000004 ) >> 2)
+#define GET_RX_ID_LEN_THOLD_INT (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00000008 ) >> 3)
+#define GET_ID_TX_LEN_THOLD (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00001ff0 ) >> 4)
+#define GET_ID_RX_LEN_THOLD (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x003fe000 ) >> 13)
+#define GET_ID_LEN_THOLD (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x7fc00000 ) >> 22)
+#define GET_ALL_ID_ALC_LEN (((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0x000001ff ) >> 0)
+#define GET_TX_ID_ALC_LEN (((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0x0003fe00 ) >> 9)
+#define GET_RX_ID_ALC_LEN (((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0x07fc0000 ) >> 18)
+#define GET_CH_ARB_EN (((REG32(ADR_CH_ARB_PRI)) & 0x00000001 ) >> 0)
+#define GET_CH_PRI1 (((REG32(ADR_CH_ARB_PRI)) & 0x00000030 ) >> 4)
+#define GET_CH_PRI2 (((REG32(ADR_CH_ARB_PRI)) & 0x00000300 ) >> 8)
+#define GET_CH_PRI3 (((REG32(ADR_CH_ARB_PRI)) & 0x00003000 ) >> 12)
+#define GET_CH_PRI4 (((REG32(ADR_CH_ARB_PRI)) & 0x00030000 ) >> 16)
+#define GET_TX_ID_REMAIN (((REG32(ADR_TX_ID_REMAIN_STATUS)) & 0x0000007f ) >> 0)
+#define GET_TX_PAGE_REMAIN (((REG32(ADR_TX_ID_REMAIN_STATUS)) & 0x0001ff00 ) >> 8)
+#define GET_ID_PAGE_MAX_SIZE (((REG32(ADR_ID_INFO_STA)) & 0x000001ff ) >> 0)
+#define GET_TX_PAGE_LIMIT (((REG32(ADR_TX_LIMIT_INTR)) & 0x000001ff ) >> 0)
+#define GET_TX_COUNT_LIMIT (((REG32(ADR_TX_LIMIT_INTR)) & 0x00ff0000 ) >> 16)
+#define GET_TX_LIMIT_INT (((REG32(ADR_TX_LIMIT_INTR)) & 0x40000000 ) >> 30)
+#define GET_TX_LIMIT_INT_EN (((REG32(ADR_TX_LIMIT_INTR)) & 0x80000000 ) >> 31)
+#define GET_TX_PAGE_USE_7_0 (((REG32(ADR_TX_ID_ALL_INFO)) & 0x000000ff ) >> 0)
+#define GET_TX_ID_USE_5_0 (((REG32(ADR_TX_ID_ALL_INFO)) & 0x00003f00 ) >> 8)
+#define GET_EDCA0_FFO_CNT (((REG32(ADR_TX_ID_ALL_INFO)) & 0x0003c000 ) >> 14)
+#define GET_EDCA1_FFO_CNT_3_0 (((REG32(ADR_TX_ID_ALL_INFO)) & 0x003c0000 ) >> 18)
+#define GET_EDCA2_FFO_CNT (((REG32(ADR_TX_ID_ALL_INFO)) & 0x07c00000 ) >> 22)
+#define GET_EDCA3_FFO_CNT (((REG32(ADR_TX_ID_ALL_INFO)) & 0xf8000000 ) >> 27)
+#define GET_ID_TB2 (((REG32(ADR_RD_ID2)) & 0xffffffff ) >> 0)
+#define GET_ID_TB3 (((REG32(ADR_RD_ID3)) & 0xffffffff ) >> 0)
+#define GET_TX_ID_TB2 (((REG32(ADR_TX_ID2)) & 0xffffffff ) >> 0)
+#define GET_TX_ID_TB3 (((REG32(ADR_TX_ID3)) & 0xffffffff ) >> 0)
+#define GET_RX_ID_TB2 (((REG32(ADR_RX_ID2)) & 0xffffffff ) >> 0)
+#define GET_RX_ID_TB3 (((REG32(ADR_RX_ID3)) & 0xffffffff ) >> 0)
+#define GET_TX_PAGE_USE2 (((REG32(ADR_TX_ID_ALL_INFO2)) & 0x000001ff ) >> 0)
+#define GET_TX_ID_USE2 (((REG32(ADR_TX_ID_ALL_INFO2)) & 0x0001fe00 ) >> 9)
+#define GET_EDCA4_FFO_CNT (((REG32(ADR_TX_ID_ALL_INFO2)) & 0x001e0000 ) >> 17)
+#define GET_EDCA5_FFO_CNT (((REG32(ADR_TX_ID_ALL_INFO2)) & 0x03e00000 ) >> 21)
+#define GET_TX_PAGE_USE3 (((REG32(ADR_TX_ID_ALL_INFO_A)) & 0x000001ff ) >> 0)
+#define GET_TX_ID_USE3 (((REG32(ADR_TX_ID_ALL_INFO_A)) & 0x0001fe00 ) >> 9)
+#define GET_EDCA1_FFO_CNT2 (((REG32(ADR_TX_ID_ALL_INFO_A)) & 0x003e0000 ) >> 17)
+#define GET_EDCA4_FFO_CNT2 (((REG32(ADR_TX_ID_ALL_INFO_A)) & 0x07800000 ) >> 23)
+#define GET_EDCA5_FFO_CNT2 (((REG32(ADR_TX_ID_ALL_INFO_A)) & 0xf8000000 ) >> 27)
+#define GET_TX_PAGE_USE4 (((REG32(ADR_TX_ID_ALL_INFO_B)) & 0x000001ff ) >> 0)
+#define GET_TX_ID_USE4 (((REG32(ADR_TX_ID_ALL_INFO_B)) & 0x0001fe00 ) >> 9)
+#define GET_EDCA2_FFO_CNT2 (((REG32(ADR_TX_ID_ALL_INFO_B)) & 0x003e0000 ) >> 17)
+#define GET_EDCA3_FFO_CNT2 (((REG32(ADR_TX_ID_ALL_INFO_B)) & 0x07c00000 ) >> 22)
+#define GET_TX_ID_IFO_LEN (((REG32(ADR_TX_ID_REMAIN_STATUS2)) & 0x000001ff ) >> 0)
+#define GET_RX_ID_IFO_LEN (((REG32(ADR_TX_ID_REMAIN_STATUS2)) & 0x01ff0000 ) >> 16)
+#define GET_MAX_ALL_ALC_ID_CNT (((REG32(ADR_ALC_ID_INFO)) & 0x000000ff ) >> 0)
+#define GET_MAX_TX_ALC_ID_CNT (((REG32(ADR_ALC_ID_INFO)) & 0x0000ff00 ) >> 8)
+#define GET_MAX_RX_ALC_ID_CNT (((REG32(ADR_ALC_ID_INFO)) & 0x00ff0000 ) >> 16)
+#define GET_MAX_ALL_ID_ALC_LEN (((REG32(ADR_ALC_ID_INF1)) & 0x000001ff ) >> 0)
+#define GET_MAX_TX_ID_ALC_LEN (((REG32(ADR_ALC_ID_INF1)) & 0x0003fe00 ) >> 9)
+#define GET_MAX_RX_ID_ALC_LEN (((REG32(ADR_ALC_ID_INF1)) & 0x07fc0000 ) >> 18)
+#define GET_ALC_ABT_ID (((REG32(ADR_ALC_ABORT)) & 0x0000007f ) >> 0)
+#define GET_ALC_ABT_STS (((REG32(ADR_ALC_ABORT)) & 0x00000100 ) >> 8)
+#define GET_ALC_ABT_CLR (((REG32(ADR_ALC_ABORT)) & 0x00000200 ) >> 9)
+#define GET_ALC_ERR_STS (((REG32(ADR_ALC_RLS_STATUS)) & 0x00000001 ) >> 0)
+#define GET_RLS_ERR_STS (((REG32(ADR_ALC_RLS_STATUS)) & 0x00000002 ) >> 1)
+#define GET_ALC_ERR_CLR (((REG32(ADR_ALC_RLS_STATUS)) & 0x00000004 ) >> 2)
+#define GET_RLS_ERR_CLR (((REG32(ADR_ALC_RLS_STATUS)) & 0x00000008 ) >> 3)
+#define GET_AL_STATE (((REG32(ADR_ALC_RLS_STATUS)) & 0x00000700 ) >> 8)
+#define GET_RL_STATE (((REG32(ADR_ALC_RLS_STATUS)) & 0x00007000 ) >> 12)
+#define GET_ALC_ERR_ID (((REG32(ADR_ALC_RLS_STATUS)) & 0x007f0000 ) >> 16)
+#define GET_RLS_ERR_ID (((REG32(ADR_ALC_RLS_STATUS)) & 0x7f000000 ) >> 24)
+#define GET_DMN_NOHIT_STS (((REG32(ADR_DMN_STATUS)) & 0x00000001 ) >> 0)
+#define GET_DMN_NOHIT_CLR (((REG32(ADR_DMN_STATUS)) & 0x00000002 ) >> 1)
+#define GET_DMN_WR (((REG32(ADR_DMN_STATUS)) & 0x00000004 ) >> 2)
+#define GET_DMN_PORT (((REG32(ADR_DMN_STATUS)) & 0x000000f0 ) >> 4)
+#define GET_DMN_NHIT_ID (((REG32(ADR_DMN_STATUS)) & 0x00007f00 ) >> 8)
+#define GET_DMN_NHIT_ADDR (((REG32(ADR_DMN_STATUS)) & 0x00ff0000 ) >> 16)
+#define GET_AVA_TAG (((REG32(ADR_TAG_STATUS)) & 0x000001ff ) >> 0)
+#define GET_PKTBUF_FULL (((REG32(ADR_TAG_STATUS)) & 0x00010000 ) >> 16)
+#define GET_PKT_REQ_STATUS (((REG32(ADR_REQ_STATUS)) & 0x0000ffff ) >> 0)
+#define GET_PG_TAG_31_0 (((REG32(ADR_PAGE_TAG_STATUS_0)) & 0xffffffff ) >> 0)
+#define GET_PG_TAG_63_32 (((REG32(ADR_PAGE_TAG_STATUS_1)) & 0xffffffff ) >> 0)
+#define GET_PG_TAG_95_64 (((REG32(ADR_PAGE_TAG_STATUS_2)) & 0xffffffff ) >> 0)
+#define GET_PG_TAG_127_96 (((REG32(ADR_PAGE_TAG_STATUS_3)) & 0xffffffff ) >> 0)
+#define GET_PG_TAG_159_128 (((REG32(ADR_PAGE_TAG_STATUS_4)) & 0xffffffff ) >> 0)
+#define GET_PG_TAG_191_160 (((REG32(ADR_PAGE_TAG_STATUS_5)) & 0xffffffff ) >> 0)
+#define GET_PG_TAG_223_192 (((REG32(ADR_PAGE_TAG_STATUS_6)) & 0xffffffff ) >> 0)
+#define GET_PG_TAG_255_224 (((REG32(ADR_PAGE_TAG_STATUS_7)) & 0xffffffff ) >> 0)
+#define GET_FPGA_TO_GEMINIA_DAC_SIGN_SWAP (((REG32(ADR_FPGA_GEMINIARF_SWITCH)) & 0x00000002 ) >> 1)
+#define GET_FPGA_TO_GEMINIA_DAC_EDGE_SEL (((REG32(ADR_FPGA_GEMINIARF_SWITCH)) & 0x00000004 ) >> 2)
+#define GET_FPGA_TO_GEMINIA_ADC_EDGE_SEL (((REG32(ADR_FPGA_GEMINIARF_SWITCH)) & 0x00000008 ) >> 3)
+#define SET_REG(_REG_,_VAL_,_SHIFT_,_MASK_) \
+         ({u32 reg = REG32_R(_REG_); reg =((((_VAL_) << _SHIFT_) & ~_MASK_) | (reg & _MASK_)); REG32_W(_REG_, reg); reg;})
+#define SET_FBUS_DMAC_SAR0(_VAL_) SET_REG(ADR_FBUS_SAR0,_VAL_,0,0x00000000)
+#define SET_FBUS_DMAC_DAR0(_VAL_) SET_REG(ADR_FBUS_DAR0,_VAL_,0,0x00000000)
+#define SET_FBUS_DMAC_INTR_EN0(_VAL_) SET_REG(ADR_FBUS_CTL0_1,_VAL_,0,0xfffffffe)
+#define SET_FBUS_DMAC_DST_TR_WIDTH0(_VAL_) SET_REG(ADR_FBUS_CTL0_1,_VAL_,1,0xfffffff1)
+#define SET_FBUS_DMAC_SRC_TR_WIDTH0(_VAL_) SET_REG(ADR_FBUS_CTL0_1,_VAL_,4,0xffffff8f)
+#define SET_FBUS_DMAC_DINC0(_VAL_) SET_REG(ADR_FBUS_CTL0_1,_VAL_,7,0xfffffe7f)
+#define SET_FBUS_DMAC_SINC0(_VAL_) SET_REG(ADR_FBUS_CTL0_1,_VAL_,9,0xfffff9ff)
+#define SET_FBUS_DMAC_DST_MSIZE0(_VAL_) SET_REG(ADR_FBUS_CTL0_1,_VAL_,11,0xffffc7ff)
+#define SET_FBUS_DMAC_SRC_MSIZE0(_VAL_) SET_REG(ADR_FBUS_CTL0_1,_VAL_,14,0xfffe3fff)
+#define SET_FBUS_DMAC_FC_MODE0(_VAL_) SET_REG(ADR_FBUS_CTL0_1,_VAL_,20,0xff8fffff)
+#define SET_FBUS_DMAC_BLOCK0(_VAL_) SET_REG(ADR_FBUS_CTL0_2,_VAL_,0,0xfffff000)
+#define SET_FBUS_DMAC_CH0_PRIOR(_VAL_) SET_REG(ADR_FBUS_CFG0_1,_VAL_,5,0xffffffdf)
+#define SET_FBUS_DMAC_HS_SEL_DST0(_VAL_) SET_REG(ADR_FBUS_CFG0_1,_VAL_,10,0xfffffbff)
+#define SET_FBUS_DMAC_HS_SEL_SRC0(_VAL_) SET_REG(ADR_FBUS_CFG0_1,_VAL_,11,0xfffff7ff)
+#define SET_FBUS_DMAC_MAX_BURST_LEN0(_VAL_) SET_REG(ADR_FBUS_CFG0_1,_VAL_,20,0xc00fffff)
+#define SET_FBUS_DMAC_SRC_HS_BUS_SEL0(_VAL_) SET_REG(ADR_FBUS_CFG0_2,_VAL_,7,0xfffffc7f)
+#define SET_FBUS_DMAC_DST_HS_BUS_SEL0(_VAL_) SET_REG(ADR_FBUS_CFG0_2,_VAL_,11,0xffffc7ff)
+#define SET_FBUS_DMAC_SAR1(_VAL_) SET_REG(ADR_FBUS_SAR1,_VAL_,0,0x00000000)
+#define SET_FBUS_DMAC_DAR1(_VAL_) SET_REG(ADR_FBUS_DAR1,_VAL_,0,0x00000000)
+#define SET_FBUS_DMAC_INTR_EN1(_VAL_) SET_REG(ADR_FBUS_CTL1_1,_VAL_,0,0xfffffffe)
+#define SET_FBUS_DMAC_DST_TR_WIDTH1(_VAL_) SET_REG(ADR_FBUS_CTL1_1,_VAL_,1,0xfffffff1)
+#define SET_FBUS_DMAC_SRC_TR_WIDTH1(_VAL_) SET_REG(ADR_FBUS_CTL1_1,_VAL_,4,0xffffff8f)
+#define SET_FBUS_DMAC_DINC1(_VAL_) SET_REG(ADR_FBUS_CTL1_1,_VAL_,7,0xfffffe7f)
+#define SET_FBUS_DMAC_SINC1(_VAL_) SET_REG(ADR_FBUS_CTL1_1,_VAL_,9,0xfffff9ff)
+#define SET_FBUS_DMAC_DST_MSIZE1(_VAL_) SET_REG(ADR_FBUS_CTL1_1,_VAL_,11,0xffffc7ff)
+#define SET_FBUS_DMAC_SRC_MSIZE1(_VAL_) SET_REG(ADR_FBUS_CTL1_1,_VAL_,14,0xfffe3fff)
+#define SET_FBUS_DMAC_FC_MODE1(_VAL_) SET_REG(ADR_FBUS_CTL1_1,_VAL_,20,0xff8fffff)
+#define SET_FBUS_DMAC_BLOCK1(_VAL_) SET_REG(ADR_FBUS_CTL1_2,_VAL_,0,0xfffff000)
+#define SET_FBUS_DMAC_CH1_PRIOR(_VAL_) SET_REG(ADR_FBUS_CFG1_1,_VAL_,5,0xffffffdf)
+#define SET_FBUS_DMAC_HS_SEL_DST1(_VAL_) SET_REG(ADR_FBUS_CFG1_1,_VAL_,10,0xfffffbff)
+#define SET_FBUS_DMAC_HS_SEL_SRC1(_VAL_) SET_REG(ADR_FBUS_CFG1_1,_VAL_,11,0xfffff7ff)
+#define SET_FBUS_DMAC_MAX_BURST_LEN1(_VAL_) SET_REG(ADR_FBUS_CFG1_1,_VAL_,20,0xc00fffff)
+#define SET_FBUS_DMAC_SRC_HS_BUS_SEL1(_VAL_) SET_REG(ADR_FBUS_CFG1_2,_VAL_,7,0xfffffc7f)
+#define SET_FBUS_DMAC_DST_HS_BUS_SEL1(_VAL_) SET_REG(ADR_FBUS_CFG1_2,_VAL_,11,0xffffc7ff)
+#define SET_FBUS_DMAC_CH_RAW_TR(_VAL_) SET_REG(ADR_FBUS_RAWTR,_VAL_,0,0x00000000)
+#define SET_FBUS_DMAC_CH_ERR_TR(_VAL_) SET_REG(ADR_FBUS_RAWERR,_VAL_,0,0x00000000)
+#define SET_FBUS_DMAC_CH_STATUSTR_TR(_VAL_) SET_REG(ADR_FBUS_STATUSTR,_VAL_,0,0x00000000)
+#define SET_FBUS_DMAC_CH_STATUSERR_TR(_VAL_) SET_REG(ADR_FBUS_STATUSERR,_VAL_,0,0x00000000)
+#define SET_FBUS_DMAC_CH_DEMASK_TR(_VAL_) SET_REG(ADR_FBUS_MASKTR,_VAL_,0,0x00000000)
+#define SET_FBUS_DMAC_CH_DEMASK_ERR(_VAL_) SET_REG(ADR_FBUS_MASKERR,_VAL_,0,0x00000000)
+#define SET_FBUS_DMAC_CH0_CLR_TR(_VAL_) SET_REG(ADR_FBUS_CLRTR,_VAL_,0,0xfffffffe)
+#define SET_FBUS_DMAC_CH1_CLR_TR(_VAL_) SET_REG(ADR_FBUS_CLRTR,_VAL_,1,0xfffffffd)
+#define SET_FBUS_DMAC_CH0_CLR_ERR(_VAL_) SET_REG(ADR_FBUS_CLRERR,_VAL_,0,0xfffffffe)
+#define SET_FBUS_DMAC_CH1_CLR_ERR(_VAL_) SET_REG(ADR_FBUS_CLRERR,_VAL_,1,0xfffffffd)
+#define SET_FBUS_DMAC_DISEN_SHS_SRC_REQ(_VAL_) SET_REG(ADR_FBUS_SHS_SRC_REQ_CFG,_VAL_,0,0xffff0000)
+#define SET_FBUS_DMAC_DISEN_SHS_DST_REQ(_VAL_) SET_REG(ADR_FBUS_SHS_DST_REQ_CFG,_VAL_,0,0xffff0000)
+#define SET_FBUS_DMAC_DISEN_SHS_SRC_SREQ(_VAL_) SET_REG(ADR_FBUS_SHS_SRC_SREQ_CFG,_VAL_,0,0xffff0000)
+#define SET_FBUS_DMAC_DISEN_SHS_DST_SREQ(_VAL_) SET_REG(ADR_FBUS_SHS_DST_SREQ_CFG,_VAL_,0,0xffff0000)
+#define SET_FBUS_DMAC_EN(_VAL_) SET_REG(ADR_FBUS_DMA_EN,_VAL_,0,0xfffffffe)
+#define SET_FBUS_DMAC_CH_EN(_VAL_) SET_REG(ADR_FBUS_CH_EN,_VAL_,0,0xffff0000)
+#define SET_SBUS_DMAC_SAR0(_VAL_) SET_REG(ADR_SBUS_SAR0,_VAL_,0,0x00000000)
+#define SET_SBUS_DMAC_DAR0(_VAL_) SET_REG(ADR_SBUS_DAR0,_VAL_,0,0x00000000)
+#define SET_SBUS_DMAC_INTR_EN0(_VAL_) SET_REG(ADR_SBUS_CTL0_1,_VAL_,0,0xfffffffe)
+#define SET_SBUS_DMAC_DST_TR_WIDTH0(_VAL_) SET_REG(ADR_SBUS_CTL0_1,_VAL_,1,0xfffffff1)
+#define SET_SBUS_DMAC_SRC_TR_WIDTH0(_VAL_) SET_REG(ADR_SBUS_CTL0_1,_VAL_,4,0xffffff8f)
+#define SET_SBUS_DMAC_DINC0(_VAL_) SET_REG(ADR_SBUS_CTL0_1,_VAL_,7,0xfffffe7f)
+#define SET_SBUS_DMAC_SINC0(_VAL_) SET_REG(ADR_SBUS_CTL0_1,_VAL_,9,0xfffff9ff)
+#define SET_SBUS_DMAC_DST_MSIZE0(_VAL_) SET_REG(ADR_SBUS_CTL0_1,_VAL_,11,0xffffc7ff)
+#define SET_SBUS_DMAC_SRC_MSIZE0(_VAL_) SET_REG(ADR_SBUS_CTL0_1,_VAL_,14,0xfffe3fff)
+#define SET_SBUS_DMAC_FC_MODE0(_VAL_) SET_REG(ADR_SBUS_CTL0_1,_VAL_,20,0xff8fffff)
+#define SET_SBUS_DMAC_BLOCK0(_VAL_) SET_REG(ADR_SBUS_CTL0_2,_VAL_,0,0xfffff000)
+#define SET_SBUS_DMAC_CH0_PRIOR(_VAL_) SET_REG(ADR_SBUS_CFG0_1,_VAL_,5,0xffffffdf)
+#define SET_SBUS_DMAC_HS_SEL_DST0(_VAL_) SET_REG(ADR_SBUS_CFG0_1,_VAL_,10,0xfffffbff)
+#define SET_SBUS_DMAC_HS_SEL_SRC0(_VAL_) SET_REG(ADR_SBUS_CFG0_1,_VAL_,11,0xfffff7ff)
+#define SET_SBUS_DMAC_MAX_BURST_LEN0(_VAL_) SET_REG(ADR_SBUS_CFG0_1,_VAL_,20,0xc00fffff)
+#define SET_SBUS_DMAC_SRC_HS_BUS_SEL0(_VAL_) SET_REG(ADR_SBUS_CFG0_2,_VAL_,7,0xfffffc7f)
+#define SET_SBUS_DMAC_DST_HS_BUS_SEL0(_VAL_) SET_REG(ADR_SBUS_CFG0_2,_VAL_,11,0xffffc7ff)
+#define SET_SBUS_DMAC_SAR1(_VAL_) SET_REG(ADR_SBUS_SAR1,_VAL_,0,0x00000000)
+#define SET_SBUS_DMAC_DAR1(_VAL_) SET_REG(ADR_SBUS_DAR1,_VAL_,0,0x00000000)
+#define SET_SBUS_DMAC_INTR_EN1(_VAL_) SET_REG(ADR_SBUS_CTL1_1,_VAL_,0,0xfffffffe)
+#define SET_SBUS_DMAC_DST_TR_WIDTH1(_VAL_) SET_REG(ADR_SBUS_CTL1_1,_VAL_,1,0xfffffff1)
+#define SET_SBUS_DMAC_SRC_TR_WIDTH1(_VAL_) SET_REG(ADR_SBUS_CTL1_1,_VAL_,4,0xffffff8f)
+#define SET_SBUS_DMAC_DINC1(_VAL_) SET_REG(ADR_SBUS_CTL1_1,_VAL_,7,0xfffffe7f)
+#define SET_SBUS_DMAC_SINC1(_VAL_) SET_REG(ADR_SBUS_CTL1_1,_VAL_,9,0xfffff9ff)
+#define SET_SBUS_DMAC_DST_MSIZE1(_VAL_) SET_REG(ADR_SBUS_CTL1_1,_VAL_,11,0xffffc7ff)
+#define SET_SBUS_DMAC_SRC_MSIZE1(_VAL_) SET_REG(ADR_SBUS_CTL1_1,_VAL_,14,0xfffe3fff)
+#define SET_SBUS_DMAC_FC_MODE1(_VAL_) SET_REG(ADR_SBUS_CTL1_1,_VAL_,20,0xff8fffff)
+#define SET_SBUS_DMAC_BLOCK1(_VAL_) SET_REG(ADR_SBUS_CTL1_2,_VAL_,0,0xfffff000)
+#define SET_SBUS_DMAC_CH1_PRIOR(_VAL_) SET_REG(ADR_SBUS_CFG1_1,_VAL_,5,0xffffffdf)
+#define SET_SBUS_DMAC_HS_SEL_DST1(_VAL_) SET_REG(ADR_SBUS_CFG1_1,_VAL_,10,0xfffffbff)
+#define SET_SBUS_DMAC_HS_SEL_SRC1(_VAL_) SET_REG(ADR_SBUS_CFG1_1,_VAL_,11,0xfffff7ff)
+#define SET_SBUS_DMAC_MAX_BURST_LEN1(_VAL_) SET_REG(ADR_SBUS_CFG1_1,_VAL_,20,0xc00fffff)
+#define SET_SBUS_DMAC_SRC_HS_BUS_SEL1(_VAL_) SET_REG(ADR_SBUS_CFG1_2,_VAL_,7,0xfffffc7f)
+#define SET_SBUS_DMAC_DST_HS_BUS_SEL1(_VAL_) SET_REG(ADR_SBUS_CFG1_2,_VAL_,11,0xffffc7ff)
+#define SET_SBUS_DMAC_CH_RAW_TR(_VAL_) SET_REG(ADR_SBUS_RAWTR,_VAL_,0,0x00000000)
+#define SET_SBUS_DMAC_CH_ERR_TR(_VAL_) SET_REG(ADR_SBUS_RAWERR,_VAL_,0,0x00000000)
+#define SET_SBUS_DMAC_CH_STATUSTR_TR(_VAL_) SET_REG(ADR_SBUS_STATUSTR,_VAL_,0,0x00000000)
+#define SET_SBUS_DMAC_CH_STATUSERR_TR(_VAL_) SET_REG(ADR_SBUS_STATUSERR,_VAL_,0,0x00000000)
+#define SET_SBUS_DMAC_CH_DEMASK_TR(_VAL_) SET_REG(ADR_SBUS_MASKTR,_VAL_,0,0x00000000)
+#define SET_SBUS_DMAC_CH_DEMASK_ERR(_VAL_) SET_REG(ADR_SBUS_MASKERR,_VAL_,0,0x00000000)
+#define SET_SBUS_DMAC_CH0_CLR_TR(_VAL_) SET_REG(ADR_SBUS_CLRTR,_VAL_,0,0xfffffffe)
+#define SET_SBUS_DMAC_CH1_CLR_TR(_VAL_) SET_REG(ADR_SBUS_CLRTR,_VAL_,1,0xfffffffd)
+#define SET_SBUS_DMAC_CH0_CLR_ERR(_VAL_) SET_REG(ADR_SBUS_CLRERR,_VAL_,0,0xfffffffe)
+#define SET_SBUS_DMAC_CH1_CLR_ERR(_VAL_) SET_REG(ADR_SBUS_CLRERR,_VAL_,1,0xfffffffd)
+#define SET_SBUS_DMAC_DISEN_SHS_SRC_REQ(_VAL_) SET_REG(ADR_SBUS_SHS_SRC_REQ_CFG,_VAL_,0,0xffff0000)
+#define SET_SBUS_DMAC_DISEN_SHS_DST_REQ(_VAL_) SET_REG(ADR_SBUS_SHS_DST_REQ_CFG,_VAL_,0,0xffff0000)
+#define SET_SBUS_DMAC_DISEN_SHS_SRC_SREQ(_VAL_) SET_REG(ADR_SBUS_SHS_SRC_SREQ_CFG,_VAL_,0,0xffff0000)
+#define SET_SBUS_DMAC_DISEN_SHS_DST_SREQ(_VAL_) SET_REG(ADR_SBUS_SHS_DST_SREQ_CFG,_VAL_,0,0xffff0000)
+#define SET_SBUS_DMAC_EN(_VAL_) SET_REG(ADR_SBUS_DMA_EN,_VAL_,0,0xfffffffe)
+#define SET_SBUS_DMAC_CH_EN(_VAL_) SET_REG(ADR_SBUS_CH_EN,_VAL_,0,0xffff0000)
+#define SET_I2S_ENABLE(_VAL_) SET_REG(ADR_I2S_EN,_VAL_,0,0xfffffffe)
+#define SET_I2S_RX_ENABLE(_VAL_) SET_REG(ADR_I2S_RX_EN,_VAL_,0,0xfffffffe)
+#define SET_I2S_TX_ENABLE(_VAL_) SET_REG(ADR_I2S_TX_EN,_VAL_,0,0xfffffffe)
+#define SET_I2S_SCLK_SOURCE_ENABLE(_VAL_) SET_REG(ADR_I2S_SCLK_SCR_EN,_VAL_,0,0xfffffffe)
+#define SET_I2S_SCLK_GATE(_VAL_) SET_REG(ADR_I2S_WS_DEF,_VAL_,0,0xfffffff8)
+#define SET_I2S_WS_LENGTH(_VAL_) SET_REG(ADR_I2S_WS_DEF,_VAL_,3,0xffffffe7)
+#define SET_I2S_RST_RXFIFO(_VAL_) SET_REG(ADR_RESET_RX_FIFO,_VAL_,0,0xfffffffe)
+#define SET_I2S_RST_TXFIFO(_VAL_) SET_REG(ADR_RESET_TX_FIFO,_VAL_,0,0xfffffffe)
+#define SET_I2S_L_TRX_DATA(_VAL_) SET_REG(ADR_L_TRX_DATA,_VAL_,0,0x00000000)
+#define SET_I2S_R_TRX_DATA(_VAL_) SET_REG(ADR_R_TRX_DATA,_VAL_,0,0x00000000)
+#define SET_I2S_RX_CH_ENABLE(_VAL_) SET_REG(ADR_I2S_RX_CH_EN,_VAL_,0,0xfffffffe)
+#define SET_I2S_TX_CH_ENABLE(_VAL_) SET_REG(ADR_I2S_TX_CH_EN,_VAL_,0,0xfffffffe)
+#define SET_I2S_RX_WD_RES(_VAL_) SET_REG(ADR_I2S_RX_WORD_RES,_VAL_,0,0xfffffff8)
+#define SET_I2S_TX_WD_RES(_VAL_) SET_REG(ADR_I2S_TX_WORD_RES,_VAL_,0,0xfffffff8)
+#define SET_I2S_INTR_RXDA(_VAL_) SET_REG(ADR_I2S_INTR,_VAL_,0,0xfffffffe)
+#define SET_I2S_INTR_RXFO(_VAL_) SET_REG(ADR_I2S_INTR,_VAL_,1,0xfffffffd)
+#define SET_I2S_INTR_RXFE(_VAL_) SET_REG(ADR_I2S_INTR,_VAL_,4,0xffffffef)
+#define SET_I2S_INTR_TXFO(_VAL_) SET_REG(ADR_I2S_INTR,_VAL_,5,0xffffffdf)
+#define SET_I2S_INTR_RXFA_MASK(_VAL_) SET_REG(ADR_I2S_INTR_MASK,_VAL_,0,0xfffffffe)
+#define SET_I2S_INTR_RXFO_MASK(_VAL_) SET_REG(ADR_I2S_INTR_MASK,_VAL_,1,0xfffffffd)
+#define SET_I2S_INTR_TXFE_MASK(_VAL_) SET_REG(ADR_I2S_INTR_MASK,_VAL_,4,0xffffffef)
+#define SET_I2S_INTR_TXFO_MASK(_VAL_) SET_REG(ADR_I2S_INTR_MASK,_VAL_,5,0xffffffdf)
+#define SET_I2S_RXFO(_VAL_) SET_REG(ADR_I2S_RXFO,_VAL_,0,0xfffffffe)
+#define SET_I2S_TXFO(_VAL_) SET_REG(ADR_I2S_TXFO,_VAL_,0,0xfffffffe)
+#define SET_I2S_RX_FIFO_TH(_VAL_) SET_REG(ADR_I2S_RX_FIFO_TH,_VAL_,0,0xfffffff8)
+#define SET_I2S_TX_FIFO_TH(_VAL_) SET_REG(ADR_I2S_TX_FIFO_TH,_VAL_,0,0xfffffff8)
+#define SET_I2S_RX_FIFO_FLUSH(_VAL_) SET_REG(ADR_I2S_RX_FIFO_FLUSH,_VAL_,0,0xfffffffe)
+#define SET_I2S_TX_FIFO_FLUSH(_VAL_) SET_REG(ADR_I2S_TX_FIFO_FLUSH,_VAL_,0,0xfffffffe)
+#define SET_I2S_RX_DMA(_VAL_) SET_REG(ADR_I2S_RX_DMA,_VAL_,0,0x00000000)
+#define SET_I2S_TX_DMA(_VAL_) SET_REG(ADR_I2S_TX_DMA,_VAL_,0,0x00000000)
+#define SET_I2CMST_ENABLE_MASTER(_VAL_) SET_REG(ADR_I2CMST_CFG0,_VAL_,0,0xfffffffe)
+#define SET_I2CMST_SPEED(_VAL_) SET_REG(ADR_I2CMST_CFG0,_VAL_,1,0xfffffff9)
+#define SET_I2CMST_RESTART_EN(_VAL_) SET_REG(ADR_I2CMST_CFG0,_VAL_,5,0xffffffdf)
+#define SET_I2CMST_DISABLE_SLAVE(_VAL_) SET_REG(ADR_I2CMST_CFG0,_VAL_,6,0xffffffbf)
+#define SET_I2CMST_TAR(_VAL_) SET_REG(ADR_I2CMST_TAR,_VAL_,0,0xfffffc00)
+#define SET_I2CMST_TRX_DATA(_VAL_) SET_REG(ADR_I2CMST_TRX_CMD_DATA,_VAL_,0,0xffffff00)
+#define SET_I2CMST_TRX_CMDW(_VAL_) SET_REG(ADR_I2CMST_TRX_CMD_DATA,_VAL_,8,0xfffffeff)
+#define SET_I2CMST_TRX_STOPW(_VAL_) SET_REG(ADR_I2CMST_TRX_CMD_DATA,_VAL_,9,0xfffffdff)
+#define SET_I2CMST_TRX_RESTARTW(_VAL_) SET_REG(ADR_I2CMST_TRX_CMD_DATA,_VAL_,10,0xfffffbff)
+#define SET_I2CMST_RX_1STBRDYR(_VAL_) SET_REG(ADR_I2CMST_TRX_CMD_DATA,_VAL_,11,0xfffff7ff)
+#define SET_I2CMST_SCLK_H_WIDTH(_VAL_) SET_REG(ADR_I2CMST_SCLK_H_WIDTH,_VAL_,0,0xffff0000)
+#define SET_I2CMST_SCLK_L_WIDTH(_VAL_) SET_REG(ADR_I2CMST_SCLK_L_WIDTH,_VAL_,0,0xffff0000)
+#define SET_I2CMST_RXU_INT(_VAL_) SET_REG(ADR_I2CMST_INT,_VAL_,0,0xfffffffe)
+#define SET_I2CMST_RXO_INT(_VAL_) SET_REG(ADR_I2CMST_INT,_VAL_,1,0xfffffffd)
+#define SET_I2CMST_RXF_INT(_VAL_) SET_REG(ADR_I2CMST_INT,_VAL_,2,0xfffffffb)
+#define SET_I2CMST_TXO_INT(_VAL_) SET_REG(ADR_I2CMST_INT,_VAL_,3,0xfffffff7)
+#define SET_I2CMST_TXE_INT(_VAL_) SET_REG(ADR_I2CMST_INT,_VAL_,4,0xffffffef)
+#define SET_I2CMST_RXDONE_INT(_VAL_) SET_REG(ADR_I2CMST_INT,_VAL_,7,0xffffff7f)
+#define SET_I2CMST_RXU_INT_MASK(_VAL_) SET_REG(ADR_I2CMST_INT_MASK,_VAL_,0,0xfffffffe)
+#define SET_I2CMST_RXO_INT_MASK(_VAL_) SET_REG(ADR_I2CMST_INT_MASK,_VAL_,1,0xfffffffd)
+#define SET_I2CMST_RXF_INT_MASK(_VAL_) SET_REG(ADR_I2CMST_INT_MASK,_VAL_,2,0xfffffffb)
+#define SET_I2CMST_TXO_INT_MASK(_VAL_) SET_REG(ADR_I2CMST_INT_MASK,_VAL_,3,0xfffffff7)
+#define SET_I2CMST_TXE_INT_MASK(_VAL_) SET_REG(ADR_I2CMST_INT_MASK,_VAL_,4,0xffffffef)
+#define SET_I2CMST_RXDONE_INT_MASK(_VAL_) SET_REG(ADR_I2CMST_INT_MASK,_VAL_,7,0xffffff7f)
+#define SET_I2CMST_RXU_INT_STAR(_VAL_) SET_REG(ADR_I2CMST_INT_STA,_VAL_,0,0xfffffffe)
+#define SET_I2CMST_RXO_INT_STAR(_VAL_) SET_REG(ADR_I2CMST_INT_STA,_VAL_,1,0xfffffffd)
+#define SET_I2CMST_RXF_INT_STAR(_VAL_) SET_REG(ADR_I2CMST_INT_STA,_VAL_,2,0xfffffffb)
+#define SET_I2CMST_TXO_INT_STAR(_VAL_) SET_REG(ADR_I2CMST_INT_STA,_VAL_,3,0xfffffff7)
+#define SET_I2CMST_TXE_INT_STAR(_VAL_) SET_REG(ADR_I2CMST_INT_STA,_VAL_,4,0xffffffef)
+#define SET_I2CMST_RXDONE_INT_STAR(_VAL_) SET_REG(ADR_I2CMST_INT_STA,_VAL_,7,0xffffff7f)
+#define SET_I2CMST_RX_FIFO_TH(_VAL_) SET_REG(ADR_I2CMST_RX_FIFO_TH,_VAL_,0,0xffff0000)
+#define SET_I2CMST_TX_FIFO_TH(_VAL_) SET_REG(ADR_I2CMST_TX_FIFO_TH,_VAL_,0,0xffff0000)
+#define SET_I2CMST_EN(_VAL_) SET_REG(ADR_I2CMST_ENABLE,_VAL_,0,0xfffffffe)
+#define SET_SPIMST_DATA_LEN(_VAL_) SET_REG(ADR_SPIMST_CFG0,_VAL_,0,0xfffffff0)
+#define SET_SPIMST_CPHA(_VAL_) SET_REG(ADR_SPIMST_CFG0,_VAL_,6,0xffffffbf)
+#define SET_SPIMST_CPOL(_VAL_) SET_REG(ADR_SPIMST_CFG0,_VAL_,7,0xffffff7f)
+#define SET_TRX_MODE(_VAL_) SET_REG(ADR_SPIMST_CFG0,_VAL_,8,0xfffffcff)
+#define SET_DATA_FRAMES(_VAL_) SET_REG(ADR_SPIMST_CFG1,_VAL_,0,0xffff0000)
+#define SET_SPIMST_ENABLE(_VAL_) SET_REG(ADR_SPIMST_EN,_VAL_,0,0xfffffffe)
+#define SET_SPIMST_CEN_ENABLE(_VAL_) SET_REG(ADR_SPIMST_CEN,_VAL_,0,0xfffffffe)
+#define SET_SPIMST_SCLK_RATE(_VAL_) SET_REG(ADR_SPIMST_SCLK_RATE,_VAL_,0,0xffff0000)
+#define SET_SPIMST_TXFIFO_TH(_VAL_) SET_REG(ADR_SPIMST_TXFIFO_TH,_VAL_,0,0xfffffff0)
+#define SET_SPIMST_RXFIFO_TH(_VAL_) SET_REG(ADR_SPIMST_RXFIFO_TH,_VAL_,0,0xfffffff0)
+#define SET_TRXBUSYFLAG(_VAL_) SET_REG(ADR_SPIMST_STATUS,_VAL_,0,0xfffffffe)
+#define SET_TXNOTFULLFLAG(_VAL_) SET_REG(ADR_SPIMST_STATUS,_VAL_,1,0xfffffffd)
+#define SET_TXEMPTYFLAG(_VAL_) SET_REG(ADR_SPIMST_STATUS,_VAL_,2,0xfffffffb)
+#define SET_RXNOTEMPTYFLAG(_VAL_) SET_REG(ADR_SPIMST_STATUS,_VAL_,3,0xfffffff7)
+#define SET_RXFULLFLAG(_VAL_) SET_REG(ADR_SPIMST_STATUS,_VAL_,4,0xffffffef)
+#define SET_TXERRORFLAG(_VAL_) SET_REG(ADR_SPIMST_STATUS,_VAL_,5,0xffffffdf)
+#define SET_SPIMST_TXE_INT_UNMASK(_VAL_) SET_REG(ADR_SPIMST_INT_MASK,_VAL_,0,0xfffffffe)
+#define SET_SPIMST_TXO_INT_UNMASK(_VAL_) SET_REG(ADR_SPIMST_INT_MASK,_VAL_,1,0xfffffffd)
+#define SET_SPIMST_RXU_INT_UNMASK(_VAL_) SET_REG(ADR_SPIMST_INT_MASK,_VAL_,2,0xfffffffb)
+#define SET_SPIMST_RXO_INT_UNMASK(_VAL_) SET_REG(ADR_SPIMST_INT_MASK,_VAL_,3,0xfffffff7)
+#define SET_SPIMST_RXF_INT_UNMASK(_VAL_) SET_REG(ADR_SPIMST_INT_MASK,_VAL_,4,0xffffffef)
+#define SET_SPIMST_TXE_INT(_VAL_) SET_REG(ADR_SPIMST_INT,_VAL_,0,0xfffffffe)
+#define SET_SPIMST_TXO_INT(_VAL_) SET_REG(ADR_SPIMST_INT,_VAL_,1,0xfffffffd)
+#define SET_SPIMST_RXU_INT(_VAL_) SET_REG(ADR_SPIMST_INT,_VAL_,2,0xfffffffb)
+#define SET_SPIMST_RXO_INT(_VAL_) SET_REG(ADR_SPIMST_INT,_VAL_,3,0xfffffff7)
+#define SET_SPIMST_RXF_INT(_VAL_) SET_REG(ADR_SPIMST_INT,_VAL_,4,0xffffffef)
+#define SET_SPIMST_TRX_DATA(_VAL_) SET_REG(ADR_SPIMST_TRX_DATA,_VAL_,0,0x00000000)
+#define SET_SPIMST_RX_SAMPLE_DLY(_VAL_) SET_REG(ADR_SPIMST_RX_SAMPLE_DLY,_VAL_,0,0xffffff00)
+#define SET_MCU_ENABLE(_VAL_) SET_REG(ADR_BRG_SW_RST,_VAL_,0,0xfffffffe)
+#define SET_MAC_SW_RST(_VAL_) SET_REG(ADR_BRG_SW_RST,_VAL_,1,0xfffffffd)
+#define SET_USB_SW_RST(_VAL_) SET_REG(ADR_BRG_SW_RST,_VAL_,2,0xfffffffb)
+#define SET_SDIO_SW_RST(_VAL_) SET_REG(ADR_BRG_SW_RST,_VAL_,3,0xfffffff7)
+#define SET_SPI_SLV_SW_RST(_VAL_) SET_REG(ADR_BRG_SW_RST,_VAL_,4,0xffffffef)
+#define SET_UART_SW_RST(_VAL_) SET_REG(ADR_BRG_SW_RST,_VAL_,5,0xffffffdf)
+#define SET_DMA_SW_RST(_VAL_) SET_REG(ADR_BRG_SW_RST,_VAL_,6,0xffffffbf)
+#define SET_WDT_SW_RST(_VAL_) SET_REG(ADR_BRG_SW_RST,_VAL_,7,0xffffff7f)
+#define SET_I2C_SLV_SW_RST(_VAL_) SET_REG(ADR_BRG_SW_RST,_VAL_,8,0xfffffeff)
+#define SET_INT_CTL_SW_RST(_VAL_) SET_REG(ADR_BRG_SW_RST,_VAL_,9,0xfffffdff)
+#define SET_BTCX_SW_RST(_VAL_) SET_REG(ADR_BRG_SW_RST,_VAL_,10,0xfffffbff)
+#define SET_US0TMR_SW_RST(_VAL_) SET_REG(ADR_BRG_SW_RST,_VAL_,12,0xffffefff)
+#define SET_US1TMR_SW_RST(_VAL_) SET_REG(ADR_BRG_SW_RST,_VAL_,13,0xffffdfff)
+#define SET_US2TMR_SW_RST(_VAL_) SET_REG(ADR_BRG_SW_RST,_VAL_,14,0xffffbfff)
+#define SET_US3TMR_SW_RST(_VAL_) SET_REG(ADR_BRG_SW_RST,_VAL_,15,0xffff7fff)
+#define SET_MS0TMR_SW_RST(_VAL_) SET_REG(ADR_BRG_SW_RST,_VAL_,16,0xfffeffff)
+#define SET_MS1TMR_SW_RST(_VAL_) SET_REG(ADR_BRG_SW_RST,_VAL_,17,0xfffdffff)
+#define SET_MS2TMR_SW_RST(_VAL_) SET_REG(ADR_BRG_SW_RST,_VAL_,18,0xfffbffff)
+#define SET_MS3TMR_SW_RST(_VAL_) SET_REG(ADR_BRG_SW_RST,_VAL_,19,0xfff7ffff)
+#define SET_PLF_SW_RST(_VAL_) SET_REG(ADR_BRG_SW_RST,_VAL_,20,0xffefffff)
+#define SET_ALL_SW_RST(_VAL_) SET_REG(ADR_BRG_SW_RST,_VAL_,21,0xffdfffff)
+#define SET_DAT_UART_SW_RST(_VAL_) SET_REG(ADR_BRG_SW_RST,_VAL_,22,0xffbfffff)
+#define SET_I2C_MST_SW_RST(_VAL_) SET_REG(ADR_BRG_SW_RST,_VAL_,23,0xff7fffff)
+#define SET_RG_REBOOT(_VAL_) SET_REG(ADR_BOOT,_VAL_,0,0xfffffffe)
+#define SET_TRAP_IMG_FLS(_VAL_) SET_REG(ADR_BOOT,_VAL_,16,0xfffeffff)
+#define SET_TRAP_REBOOT(_VAL_) SET_REG(ADR_BOOT,_VAL_,17,0xfffdffff)
+#define SET_TRAP_BOOT_FLS(_VAL_) SET_REG(ADR_BOOT,_VAL_,18,0xfffbffff)
+#define SET_CHIP_ID_31_0(_VAL_) SET_REG(ADR_CHIP_ID_0,_VAL_,0,0x00000000)
+#define SET_CHIP_ID_63_32(_VAL_) SET_REG(ADR_CHIP_ID_1,_VAL_,0,0x00000000)
+#define SET_CHIP_ID_95_64(_VAL_) SET_REG(ADR_CHIP_ID_2,_VAL_,0,0x00000000)
+#define SET_CHIP_ID_127_96(_VAL_) SET_REG(ADR_CHIP_ID_3,_VAL_,0,0x00000000)
+#define SET_CLK_DIGI_SEL(_VAL_) SET_REG(ADR_CLOCK_SELECTION,_VAL_,0,0xfffffff0)
+#define SET_CLK_USB_PHY30M_SEL(_VAL_) SET_REG(ADR_CLOCK_SELECTION,_VAL_,4,0xffffffef)
+#define SET_SYS_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,0,0xfffffffe)
+#define SET_MAC_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,1,0xfffffffd)
+#define SET_FLASH_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,2,0xfffffffb)
+#define SET_SDIO_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,3,0xfffffff7)
+#define SET_SPI_SLV_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,4,0xffffffef)
+#define SET_UART_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,5,0xffffffdf)
+#define SET_DMA_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,6,0xffffffbf)
+#define SET_WDT_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,7,0xffffff7f)
+#define SET_I2C_SLV_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,8,0xfffffeff)
+#define SET_INT_CTL_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,9,0xfffffdff)
+#define SET_BTCX_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,10,0xfffffbff)
+#define SET_EFS_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,11,0xfffff7ff)
+#define SET_US0TMR_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,12,0xffffefff)
+#define SET_US1TMR_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,13,0xffffdfff)
+#define SET_US2TMR_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,14,0xffffbfff)
+#define SET_US3TMR_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,15,0xffff7fff)
+#define SET_MS0TMR_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,16,0xfffeffff)
+#define SET_MS1TMR_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,17,0xfffdffff)
+#define SET_MS2TMR_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,18,0xfffbffff)
+#define SET_MS3TMR_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,19,0xfff7ffff)
+#define SET_SPI_MST2CBRA_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,20,0xffefffff)
+#define SET_AHB2PKT_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,21,0xffdfffff)
+#define SET_PWM_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,22,0xffbfffff)
+#define SET_I2C_MST_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,23,0xff7fffff)
+#define SET_RESET_N_CPUN10(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,24,0xfeffffff)
+#define SET_USB_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,25,0xfdffffff)
+#define SET_CLK_EN_USB_PHY30M(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,26,0xfbffffff)
+#define SET_CLK_EN_USB_CTRLUTMI(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,27,0xf7ffffff)
+#define SET_PHY_IQ_LOG_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,28,0xefffffff)
+#define SET_SPIMAS_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,29,0xdfffffff)
+#define SET_I2S_PCLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,30,0xbfffffff)
+#define SET_CLK_EN_PHYRF40M(_VAL_) SET_REG(ADR_SYS_CSR_CLOCK_ENABLE,_VAL_,0,0xfffffffe)
+#define SET_CLK_EN_PHYRF80M(_VAL_) SET_REG(ADR_SYS_CSR_CLOCK_ENABLE,_VAL_,1,0xfffffffd)
+#define SET_CLK_EN_160M_PHY(_VAL_) SET_REG(ADR_SYS_CSR_CLOCK_ENABLE,_VAL_,2,0xfffffffb)
+#define SET_BTCX_CSR_CLK_EN(_VAL_) SET_REG(ADR_SYS_CSR_CLOCK_ENABLE,_VAL_,10,0xfffffbff)
+#define SET_CLK_EN_MBIST(_VAL_) SET_REG(ADR_SYS_CSR_CLOCK_ENABLE,_VAL_,11,0xfffff7ff)
+#define SET_R_BOOTSTRAP_SAMPLE(_VAL_) SET_REG(ADR_BOOTSTRAP_SAMPLE,_VAL_,0,0xfffffff0)
+#define SET_N10_CORE_CURRENT_PC(_VAL_) SET_REG(ADR_N10_DBG1,_VAL_,0,0x00000000)
+#define SET_N10_STANDBY_REQ(_VAL_) SET_REG(ADR_N10_DBG2,_VAL_,27,0xf7ffffff)
+#define SET_N10_CORE_STANDBY_MODE(_VAL_) SET_REG(ADR_N10_DBG2,_VAL_,28,0xefffffff)
+#define SET_N10_CORE_DEBUG_MODE(_VAL_) SET_REG(ADR_N10_DBG2,_VAL_,29,0xdfffffff)
+#define SET_N10_STANDBY(_VAL_) SET_REG(ADR_N10_DBG2,_VAL_,30,0xbfffffff)
+#define SET_N10_WAKEUP_OK(_VAL_) SET_REG(ADR_N10_DBG2,_VAL_,31,0x7fffffff)
+#define SET_SYS_CLOCK_STATE(_VAL_) SET_REG(ADR_ROPMUSTATE,_VAL_,0,0xfffffff8)
+#define SET_ROM_READ_PROT(_VAL_) SET_REG(ADR_ROM_READ_PROT,_VAL_,0,0xfffffffe)
+#define SET_GPIO_STOP_SEL(_VAL_) SET_REG(ADR_GPIO_IQ_LOG_STOP,_VAL_,0,0xff800000)
+#define SET_GPIO_STOP_POL(_VAL_) SET_REG(ADR_GPIO_IQ_LOG_STOP,_VAL_,30,0xbfffffff)
+#define SET_GPIO_STOP_EN(_VAL_) SET_REG(ADR_GPIO_IQ_LOG_STOP,_VAL_,31,0x7fffffff)
+#define SET_TB_ADR_SEL(_VAL_) SET_REG(ADR_TB_ADR_SEL,_VAL_,0,0xffff0000)
+#define SET_TB_CS(_VAL_) SET_REG(ADR_TB_ADR_SEL,_VAL_,31,0x7fffffff)
+#define SET_TB_RDATA(_VAL_) SET_REG(ADR_TB_RDATA,_VAL_,0,0x00000000)
+#define SET_UART_W2B_EN(_VAL_) SET_REG(ADR_UART_W2B,_VAL_,0,0xfffffffe)
+#define SET_SYSCTRL_CMD(_VAL_) SET_REG(ADR_SYSCTRL_COMMAND,_VAL_,0,0x00000000)
+#define SET_CLK_FBUS_SEL(_VAL_) SET_REG(ADR_FBUS_CLK_SEL,_VAL_,0,0xfffffff0)
+#define SET_SYS_XOSC_ON(_VAL_) SET_REG(ADR_SYSCTRL_STATUS,_VAL_,0,0xfffffffe)
+#define SET_SYS_DPLL_ON(_VAL_) SET_REG(ADR_SYSCTRL_STATUS,_VAL_,1,0xfffffffd)
+#define SET_FSM_SYSCTRL(_VAL_) SET_REG(ADR_SYSCTRL_STATUS,_VAL_,8,0xffffe0ff)
+#define SET_I2SMAS_CLK_DIV(_VAL_) SET_REG(ADR_I2SMAS_CFG,_VAL_,0,0xffffc000)
+#define SET_I2S_MCLK_DIV(_VAL_) SET_REG(ADR_I2SMAS_CFG,_VAL_,16,0xfffcffff)
+#define SET_I2S_MASTER(_VAL_) SET_REG(ADR_I2SMAS_CFG,_VAL_,31,0x7fffffff)
+#define SET_HBUSREQ_LOCK(_VAL_) SET_REG(ADR_HBUSREQ_LOCK,_VAL_,0,0xffffe000)
+#define SET_HBURST_LOCK(_VAL_) SET_REG(ADR_HBURST_LOCK,_VAL_,0,0xffffe000)
+#define SET_FENCE_HIT_ADR(_VAL_) SET_REG(ADR_FENCE_CTRL,_VAL_,0,0xffe00000)
+#define SET_EDLM_SRAM_ERRCK_EN(_VAL_) SET_REG(ADR_FENCE_CTRL,_VAL_,27,0xf7ffffff)
+#define SET_EILM_ROM_ERRCK_EN(_VAL_) SET_REG(ADR_FENCE_CTRL,_VAL_,28,0xefffffff)
+#define SET_EILM_SRAM_ERRCK_EN(_VAL_) SET_REG(ADR_FENCE_CTRL,_VAL_,29,0xdfffffff)
+#define SET_FBUS_SRAM_ERRCK_EN(_VAL_) SET_REG(ADR_FENCE_CTRL,_VAL_,30,0xbfffffff)
+#define SET_FENCE_HIT_EN(_VAL_) SET_REG(ADR_FENCE_CTRL,_VAL_,31,0x7fffffff)
+#define SET_EDLM_SRAM_ERR_INT(_VAL_) SET_REG(ADR_FENCE_STATUS,_VAL_,0,0xfffffffe)
+#define SET_EILM_ROM_ERR_INT(_VAL_) SET_REG(ADR_FENCE_STATUS,_VAL_,1,0xfffffffd)
+#define SET_EILM_SRAM_ERR_INT(_VAL_) SET_REG(ADR_FENCE_STATUS,_VAL_,2,0xfffffffb)
+#define SET_FBUS_SRAM_ERR_INT(_VAL_) SET_REG(ADR_FENCE_STATUS,_VAL_,3,0xfffffff7)
+#define SET_FENCE_HIT_INT(_VAL_) SET_REG(ADR_FENCE_STATUS,_VAL_,4,0xffffffef)
+#define SET_TOP_SW_PWR_ON1_OUTPUT_PWR_ON1_1_0_0(_VAL_) SET_REG(ADR_POWER_SW_INFO,_VAL_,0,0xfffffffe)
+#define SET_TOP_SW_PWR_ON2_OUTPUT_PWR_ON2_1_0_0(_VAL_) SET_REG(ADR_POWER_SW_INFO,_VAL_,1,0xfffffffd)
+#define SET_TOP_SW_PWR_ON3_OUTPUT_PWR_ON3_1_0_0(_VAL_) SET_REG(ADR_POWER_SW_INFO,_VAL_,2,0xfffffffb)
+#define SET_VIAROM_EMA(_VAL_) SET_REG(ADR_VIAROM_EMA,_VAL_,0,0xfffffff8)
+#define SET_TEST_MODE0(_VAL_) SET_REG(ADR_TEST_MODE,_VAL_,0,0xfffffffe)
+#define SET_TEST_MODE1(_VAL_) SET_REG(ADR_TEST_MODE,_VAL_,1,0xfffffffd)
+#define SET_TEST_MODE2(_VAL_) SET_REG(ADR_TEST_MODE,_VAL_,2,0xfffffffb)
+#define SET_TEST_MODE3(_VAL_) SET_REG(ADR_TEST_MODE,_VAL_,3,0xfffffff7)
+#define SET_TEST_MODE4(_VAL_) SET_REG(ADR_TEST_MODE,_VAL_,4,0xffffffef)
+#define SET_TEST_MODE_ALL(_VAL_) SET_REG(ADR_TEST_MODE,_VAL_,5,0xffffffdf)
+#define SET_CLK_EN_CPUN10(_VAL_) SET_REG(ADR_MANUAL_RESET_N,_VAL_,1,0xfffffffd)
+#define SET_N10_WARM_RESET_N(_VAL_) SET_REG(ADR_MANUAL_RESET_N,_VAL_,2,0xfffffffb)
+#define SET_FW_EVENT(_VAL_) SET_REG(ADR_DEBUG_FIRMWARE_EVENT_FLAG,_VAL_,0,0x00000000)
+#define SET_HOST_EVENT(_VAL_) SET_REG(ADR_DEBUG_HOST_EVENT_FLAG,_VAL_,0,0x00000000)
+#define SET_CHIP_INFO_ID_31_0(_VAL_) SET_REG(ADR_CHIP_INFO_ID_0,_VAL_,0,0x00000000)
+#define SET_CHIP_INFO_ID_63_32(_VAL_) SET_REG(ADR_CHIP_INFO_ID_1,_VAL_,0,0x00000000)
+#define SET_CHIP_VER(_VAL_) SET_REG(ADR_CHIP_TYPE_VER,_VAL_,0,0xff000000)
+#define SET_CHIP_TYPE(_VAL_) SET_REG(ADR_CHIP_TYPE_VER,_VAL_,24,0x00ffffff)
+#define SET_CHIP_DATE_YYYYMMDD(_VAL_) SET_REG(ADR_CHIP_DATE_YYYYMMDD,_VAL_,0,0x00000000)
+#define SET_CHIP_DATE_00HHMMSS(_VAL_) SET_REG(ADR_CHIP_DATE_00HHMMSS,_VAL_,0,0xff000000)
+#define SET_CHIP_GITSHA_31_0(_VAL_) SET_REG(ADR_CHIP_GITSHA_0,_VAL_,0,0x00000000)
+#define SET_CHIP_GITSHA_63_32(_VAL_) SET_REG(ADR_CHIP_GITSHA_1,_VAL_,0,0x00000000)
+#define SET_CHIP_GITSHA_95_64(_VAL_) SET_REG(ADR_CHIP_GITSHA_2,_VAL_,0,0x00000000)
+#define SET_CHIP_GITSHA_127_96(_VAL_) SET_REG(ADR_CHIP_GITSHA_3,_VAL_,0,0x00000000)
+#define SET_CHIP_GITSHA_159_128(_VAL_) SET_REG(ADR_CHIP_GITSHA_4,_VAL_,0,0x00000000)
+#define SET_N10CFG_DEFAULT_IVB(_VAL_) SET_REG(ADR_N10CFG_DEF_IVB,_VAL_,0,0xffff0000)
+#define SET_SYS_N10_IVB_VAL(_VAL_) SET_REG(ADR_N10CFG_SETTING,_VAL_,16,0x0000ffff)
+#define SET_USB20_HOST_SELRW(_VAL_) SET_REG(ADR_USB20_HOST_SEL,_VAL_,0,0xfffffffe)
+#define SET_CHIP_INFO_FPGA_TAG(_VAL_) SET_REG(ADR_CHIP_INFO_FPGATAG,_VAL_,0,0x00000000)
+#define SET_SYS_PMU_MODE_TRAN_INT(_VAL_) SET_REG(ADR_PMU_MODE_TRAN_INT,_VAL_,0,0xfffffffe)
+#define SET_DBG_WRITE_TO_FINISH_SIM(_VAL_) SET_REG(ADR_DEBUG_SIM_FINISH,_VAL_,0,0xfffffffe)
+#define SET_DATA_SPI_WAKEUP(_VAL_) SET_REG(ADR_ALWAYS_ON_CFG00,_VAL_,0,0xfffffffe)
+#define SET_WAKE_SOON_WITH_SCK(_VAL_) SET_REG(ADR_SDIO_RESET_WAKE_CFG,_VAL_,0,0xfffffffe)
+#define SET_ALLOW_SD_SPI_RESET(_VAL_) SET_REG(ADR_SDIO_RESET_WAKE_CFG,_VAL_,1,0xfffffffd)
+#define SET_WDT_MCU_RESET(_VAL_) SET_REG(ADR_BOOT_INFO,_VAL_,0,0xfffffffe)
+#define SET_WDT_SYS_RESET(_VAL_) SET_REG(ADR_BOOT_INFO,_VAL_,1,0xfffffffd)
+#define SET_SDIO_CMD52_06H_RESET(_VAL_) SET_REG(ADR_BOOT_INFO,_VAL_,2,0xfffffffb)
+#define SET_DATA_SPI_RESET(_VAL_) SET_REG(ADR_BOOT_INFO,_VAL_,3,0xfffffff7)
+#define SET_UART_NRTS(_VAL_) SET_REG(ADR_SPARE_UART_INFO,_VAL_,0,0xfffffffe)
+#define SET_UART_NCTS(_VAL_) SET_REG(ADR_SPARE_UART_INFO,_VAL_,1,0xfffffffd)
+#define SET_NORMAL_PWR_ON1(_VAL_) SET_REG(ADR_POWER_ON_OFF_CTRL,_VAL_,0,0xfffffffe)
+#define SET_NORMAL_PWR_ON2(_VAL_) SET_REG(ADR_POWER_ON_OFF_CTRL,_VAL_,1,0xfffffffd)
+#define SET_NORMAL_PWR_ON3(_VAL_) SET_REG(ADR_POWER_ON_OFF_CTRL,_VAL_,2,0xfffffffb)
+#define SET_SUSPEND_PWR_ON1(_VAL_) SET_REG(ADR_POWER_ON_OFF_CTRL,_VAL_,4,0xffffffef)
+#define SET_SUSPEND_PWR_ON2(_VAL_) SET_REG(ADR_POWER_ON_OFF_CTRL,_VAL_,5,0xffffffdf)
+#define SET_SUSPEND_PWR_ON3(_VAL_) SET_REG(ADR_POWER_ON_OFF_CTRL,_VAL_,6,0xffffffbf)
+#define SET_NORMAL_ISO_ON1(_VAL_) SET_REG(ADR_POWER_ON_OFF_CTRL,_VAL_,8,0xfffffeff)
+#define SET_NORMAL_ISO_ON2(_VAL_) SET_REG(ADR_POWER_ON_OFF_CTRL,_VAL_,9,0xfffffdff)
+#define SET_NORMAL_ISO_ON3(_VAL_) SET_REG(ADR_POWER_ON_OFF_CTRL,_VAL_,10,0xfffffbff)
+#define SET_TOP_ON1_RST_N(_VAL_) SET_REG(ADR_POWER_ON_OFF_CTRL,_VAL_,12,0xffffefff)
+#define SET_TOP_ON2_RST_N(_VAL_) SET_REG(ADR_POWER_ON_OFF_CTRL,_VAL_,13,0xffffdfff)
+#define SET_TOP_ON3_RST_N(_VAL_) SET_REG(ADR_POWER_ON_OFF_CTRL,_VAL_,14,0xffffbfff)
+#define SET_HOST_WAKE_WIFI(_VAL_) SET_REG(ADR_HOST_WAKE_WIFI_CTRL,_VAL_,0,0xff800000)
+#define SET_HOST_WAKE_WIFI_POL(_VAL_) SET_REG(ADR_HOST_WAKE_WIFI_CTRL,_VAL_,31,0x7fffffff)
+#define SET_PRESCALER_US(_VAL_) SET_REG(ADR_PRESCALER_USTIMER,_VAL_,0,0xfffffe00)
+#define SET_RTC_TIMER_WAKE_PMU_EN(_VAL_) SET_REG(ADR_WAKE_PMU_ENABLE,_VAL_,0,0xfffffffe)
+#define SET_USB_WAKE_PMU_EN(_VAL_) SET_REG(ADR_WAKE_PMU_ENABLE,_VAL_,1,0xfffffffd)
+#define SET_ILM160KB_EN(_VAL_) SET_REG(ADR_SRAMCFG_SETTING,_VAL_,1,0xfffffffd)
+#define SET_PATCH00_EN(_VAL_) SET_REG(ADR_ROM_PATCH00_0,_VAL_,0,0xfffffffe)
+#define SET_PATCH00_ADDR(_VAL_) SET_REG(ADR_ROM_PATCH00_0,_VAL_,2,0xfffe0003)
+#define SET_PATCH00_DATA(_VAL_) SET_REG(ADR_ROM_PATCH00_1,_VAL_,0,0x00000000)
+#define SET_PATCH01_EN(_VAL_) SET_REG(ADR_ROM_PATCH01_0,_VAL_,0,0xfffffffe)
+#define SET_PATCH01_ADDR(_VAL_) SET_REG(ADR_ROM_PATCH01_0,_VAL_,2,0xfffe0003)
+#define SET_PATCH01_DATA(_VAL_) SET_REG(ADR_ROM_PATCH01_1,_VAL_,0,0x00000000)
+#define SET_TU0_TM_INIT_VALUE(_VAL_) SET_REG(ADR_TU0_MICROSECOND_TIMER,_VAL_,0,0xffff0000)
+#define SET_TU0_TM_MODE(_VAL_) SET_REG(ADR_TU0_MICROSECOND_TIMER,_VAL_,16,0xfffeffff)
+#define SET_TU0_TM_INT_STS_DONE(_VAL_) SET_REG(ADR_TU0_MICROSECOND_TIMER,_VAL_,17,0xfffdffff)
+#define SET_TU0_TM_INT_MASK(_VAL_) SET_REG(ADR_TU0_MICROSECOND_TIMER,_VAL_,18,0xfffbffff)
+#define SET_TU0_TM_CUR_VALUE(_VAL_) SET_REG(ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE,_VAL_,0,0xffff0000)
+#define SET_TU0_PRESCALER_USTIMER_LOCAL(_VAL_) SET_REG(ADR_TU0_MICROSECOND_TIMER_LOCAL_PRESCALE,_VAL_,0,0xfffffe00)
+#define SET_TU1_TM_INIT_VALUE(_VAL_) SET_REG(ADR_TU1_MICROSECOND_TIMER,_VAL_,0,0xffff0000)
+#define SET_TU1_TM_MODE(_VAL_) SET_REG(ADR_TU1_MICROSECOND_TIMER,_VAL_,16,0xfffeffff)
+#define SET_TU1_TM_INT_STS_DONE(_VAL_) SET_REG(ADR_TU1_MICROSECOND_TIMER,_VAL_,17,0xfffdffff)
+#define SET_TU1_TM_INT_MASK(_VAL_) SET_REG(ADR_TU1_MICROSECOND_TIMER,_VAL_,18,0xfffbffff)
+#define SET_TU1_TM_CUR_VALUE(_VAL_) SET_REG(ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE,_VAL_,0,0xffff0000)
+#define SET_TU1_PRESCALER_USTIMER_LOCAL(_VAL_) SET_REG(ADR_TU1_MICROSECOND_TIMER_LOCAL_PRESCALE,_VAL_,0,0xfffffe00)
+#define SET_TU2_TM_INIT_VALUE(_VAL_) SET_REG(ADR_TU2_MICROSECOND_TIMER,_VAL_,0,0xffff0000)
+#define SET_TU2_TM_MODE(_VAL_) SET_REG(ADR_TU2_MICROSECOND_TIMER,_VAL_,16,0xfffeffff)
+#define SET_TU2_TM_INT_STS_DONE(_VAL_) SET_REG(ADR_TU2_MICROSECOND_TIMER,_VAL_,17,0xfffdffff)
+#define SET_TU2_TM_INT_MASK(_VAL_) SET_REG(ADR_TU2_MICROSECOND_TIMER,_VAL_,18,0xfffbffff)
+#define SET_TU2_TM_CUR_VALUE(_VAL_) SET_REG(ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE,_VAL_,0,0xffff0000)
+#define SET_TU2_PRESCALER_USTIMER_LOCAL(_VAL_) SET_REG(ADR_TU2_MICROSECOND_TIMER_LOCAL_PRESCALE,_VAL_,0,0xfffffe00)
+#define SET_TU3_TM_INIT_VALUE(_VAL_) SET_REG(ADR_TU3_MICROSECOND_TIMER,_VAL_,0,0xffff0000)
+#define SET_TU3_TM_MODE(_VAL_) SET_REG(ADR_TU3_MICROSECOND_TIMER,_VAL_,16,0xfffeffff)
+#define SET_TU3_TM_INT_STS_DONE(_VAL_) SET_REG(ADR_TU3_MICROSECOND_TIMER,_VAL_,17,0xfffdffff)
+#define SET_TU3_TM_INT_MASK(_VAL_) SET_REG(ADR_TU3_MICROSECOND_TIMER,_VAL_,18,0xfffbffff)
+#define SET_TU3_TM_CUR_VALUE(_VAL_) SET_REG(ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE,_VAL_,0,0xffff0000)
+#define SET_TU3_PRESCALER_USTIMER_LOCAL(_VAL_) SET_REG(ADR_TU3_MICROSECOND_TIMER_LOCAL_PRESCALE,_VAL_,0,0xfffffe00)
+#define SET_TM0_TM_INIT_VALUE(_VAL_) SET_REG(ADR_TM0_MILLISECOND_TIMER,_VAL_,0,0xffff0000)
+#define SET_TM0_TM_MODE(_VAL_) SET_REG(ADR_TM0_MILLISECOND_TIMER,_VAL_,16,0xfffeffff)
+#define SET_TM0_TM_INT_STS_DONE(_VAL_) SET_REG(ADR_TM0_MILLISECOND_TIMER,_VAL_,17,0xfffdffff)
+#define SET_TM0_TM_INT_MASK(_VAL_) SET_REG(ADR_TM0_MILLISECOND_TIMER,_VAL_,18,0xfffbffff)
+#define SET_TM0_TM_CUR_VALUE(_VAL_) SET_REG(ADR_TM0_CURRENT_MILLISECOND_TIME_VALUE,_VAL_,0,0xffff0000)
+#define SET_TM0_PRESCALER_USTIMER_LOCAL(_VAL_) SET_REG(ADR_TM0_MILLISECOND_TIMER_PRESCALE,_VAL_,0,0xfffffe00)
+#define SET_TM1_TM_INIT_VALUE(_VAL_) SET_REG(ADR_TM1_MILLISECOND_TIMER,_VAL_,0,0xffff0000)
+#define SET_TM1_TM_MODE(_VAL_) SET_REG(ADR_TM1_MILLISECOND_TIMER,_VAL_,16,0xfffeffff)
+#define SET_TM1_TM_INT_STS_DONE(_VAL_) SET_REG(ADR_TM1_MILLISECOND_TIMER,_VAL_,17,0xfffdffff)
+#define SET_TM1_TM_INT_MASK(_VAL_) SET_REG(ADR_TM1_MILLISECOND_TIMER,_VAL_,18,0xfffbffff)
+#define SET_TM1_TM_CUR_VALUE(_VAL_) SET_REG(ADR_TM1_CURRENT_MILLISECOND_TIME_VALUE,_VAL_,0,0xffff0000)
+#define SET_TM1_PRESCALER_USTIMER_LOCAL(_VAL_) SET_REG(ADR_TM1_MILLISECOND_TIMER_PRESCALE,_VAL_,0,0xfffffe00)
+#define SET_TM2_TM_INIT_VALUE(_VAL_) SET_REG(ADR_TM2_MILLISECOND_TIMER,_VAL_,0,0xffff0000)
+#define SET_TM2_TM_MODE(_VAL_) SET_REG(ADR_TM2_MILLISECOND_TIMER,_VAL_,16,0xfffeffff)
+#define SET_TM2_TM_INT_STS_DONE(_VAL_) SET_REG(ADR_TM2_MILLISECOND_TIMER,_VAL_,17,0xfffdffff)
+#define SET_TM2_TM_INT_MASK(_VAL_) SET_REG(ADR_TM2_MILLISECOND_TIMER,_VAL_,18,0xfffbffff)
+#define SET_TM2_TM_CUR_VALUE(_VAL_) SET_REG(ADR_TM2_CURRENT_MILLISECOND_TIME_VALUE,_VAL_,0,0xffff0000)
+#define SET_TM2_PRESCALER_USTIMER_LOCAL(_VAL_) SET_REG(ADR_TM2_MILLISECOND_TIMER_PRESCALE,_VAL_,0,0xfffffe00)
+#define SET_TM3_TM_INIT_VALUE(_VAL_) SET_REG(ADR_TM3_MILLISECOND_TIMER,_VAL_,0,0xffff0000)
+#define SET_TM3_TM_MODE(_VAL_) SET_REG(ADR_TM3_MILLISECOND_TIMER,_VAL_,16,0xfffeffff)
+#define SET_TM3_TM_INT_STS_DONE(_VAL_) SET_REG(ADR_TM3_MILLISECOND_TIMER,_VAL_,17,0xfffdffff)
+#define SET_TM3_TM_INT_MASK(_VAL_) SET_REG(ADR_TM3_MILLISECOND_TIMER,_VAL_,18,0xfffbffff)
+#define SET_TM3_TM_CUR_VALUE(_VAL_) SET_REG(ADR_TM3_CURRENT_MILLISECOND_TIME_VALUE,_VAL_,0,0xffff0000)
+#define SET_TM3_PRESCALER_USTIMER_LOCAL(_VAL_) SET_REG(ADR_TM3_MILLISECOND_TIMER_PRESCALE,_VAL_,0,0xfffffe00)
+#define SET_MCU_WDT_TIME_CNT(_VAL_) SET_REG(ADR_MCU_WDOG_REG,_VAL_,0,0xffff0000)
+#define SET_MCU_WDT_INT_CNT_OFS(_VAL_) SET_REG(ADR_MCU_WDOG_REG,_VAL_,16,0xff00ffff)
+#define SET_MCU_WDT_STATUS(_VAL_) SET_REG(ADR_MCU_WDOG_REG,_VAL_,30,0xbfffffff)
+#define SET_MCU_WDOG_ENA(_VAL_) SET_REG(ADR_MCU_WDOG_REG,_VAL_,31,0x7fffffff)
+#define SET_SYS_WDT_TIME_CNT(_VAL_) SET_REG(ADR_SYS_WDOG_REG,_VAL_,0,0xffff0000)
+#define SET_SYS_WDT_INT_CNT_OFS(_VAL_) SET_REG(ADR_SYS_WDOG_REG,_VAL_,16,0xff00ffff)
+#define SET_SYS_WDT_STATUS(_VAL_) SET_REG(ADR_SYS_WDOG_REG,_VAL_,30,0xbfffffff)
+#define SET_SYS_WDOG_ENA(_VAL_) SET_REG(ADR_SYS_WDOG_REG,_VAL_,31,0x7fffffff)
+#define SET_PWM_POST_SCALER_0(_VAL_) SET_REG(ADR_PWM_0_CTRL,_VAL_,0,0xffffff00)
+#define SET_PWM_SETTING_UPDATE_0(_VAL_) SET_REG(ADR_PWM_0_CTRL,_VAL_,28,0xefffffff)
+#define SET_PWM_ALWAYSON_0(_VAL_) SET_REG(ADR_PWM_0_CTRL,_VAL_,29,0xdfffffff)
+#define SET_PWM_INVERT_0(_VAL_) SET_REG(ADR_PWM_0_CTRL,_VAL_,30,0xbfffffff)
+#define SET_PWM_ENABLE_0(_VAL_) SET_REG(ADR_PWM_0_CTRL,_VAL_,31,0x7fffffff)
+#define SET_PWM_INI_VALUE_PERIOD_0(_VAL_) SET_REG(ADR_PWM_0_SET,_VAL_,0,0xffff0000)
+#define SET_PWM_INI_VALUE_P_0(_VAL_) SET_REG(ADR_PWM_0_SET,_VAL_,16,0x0000ffff)
+#define SET_PWM_POST_SCALER_1(_VAL_) SET_REG(ADR_PWM_1_CTRL,_VAL_,0,0xffffff00)
+#define SET_PWM_SETTING_UPDATE_1(_VAL_) SET_REG(ADR_PWM_1_CTRL,_VAL_,28,0xefffffff)
+#define SET_PWM_ALWAYSON_1(_VAL_) SET_REG(ADR_PWM_1_CTRL,_VAL_,29,0xdfffffff)
+#define SET_PWM_INVERT_1(_VAL_) SET_REG(ADR_PWM_1_CTRL,_VAL_,30,0xbfffffff)
+#define SET_PWM_ENABLE_1(_VAL_) SET_REG(ADR_PWM_1_CTRL,_VAL_,31,0x7fffffff)
+#define SET_PWM_INI_VALUE_PERIOD_1(_VAL_) SET_REG(ADR_PWM_1_SET,_VAL_,0,0xffff0000)
+#define SET_PWM_INI_VALUE_P_1(_VAL_) SET_REG(ADR_PWM_1_SET,_VAL_,16,0x0000ffff)
+#define SET_PWM_POST_SCALER_2(_VAL_) SET_REG(ADR_PWM_2_CTRL,_VAL_,0,0xffffff00)
+#define SET_PWM_SETTING_UPDATE_2(_VAL_) SET_REG(ADR_PWM_2_CTRL,_VAL_,28,0xefffffff)
+#define SET_PWM_ALWAYSON_2(_VAL_) SET_REG(ADR_PWM_2_CTRL,_VAL_,29,0xdfffffff)
+#define SET_PWM_INVERT_2(_VAL_) SET_REG(ADR_PWM_2_CTRL,_VAL_,30,0xbfffffff)
+#define SET_PWM_ENABLE_2(_VAL_) SET_REG(ADR_PWM_2_CTRL,_VAL_,31,0x7fffffff)
+#define SET_PWM_INI_VALUE_PERIOD_2(_VAL_) SET_REG(ADR_PWM_2_SET,_VAL_,0,0xffff0000)
+#define SET_PWM_INI_VALUE_P_2(_VAL_) SET_REG(ADR_PWM_2_SET,_VAL_,16,0x0000ffff)
+#define SET_PWM_POST_SCALER_3(_VAL_) SET_REG(ADR_PWM_3_CTRL,_VAL_,0,0xffffff00)
+#define SET_PWM_SETTING_UPDATE_3(_VAL_) SET_REG(ADR_PWM_3_CTRL,_VAL_,28,0xefffffff)
+#define SET_PWM_ALWAYSON_3(_VAL_) SET_REG(ADR_PWM_3_CTRL,_VAL_,29,0xdfffffff)
+#define SET_PWM_INVERT_3(_VAL_) SET_REG(ADR_PWM_3_CTRL,_VAL_,30,0xbfffffff)
+#define SET_PWM_ENABLE_3(_VAL_) SET_REG(ADR_PWM_3_CTRL,_VAL_,31,0x7fffffff)
+#define SET_PWM_INI_VALUE_PERIOD_3(_VAL_) SET_REG(ADR_PWM_3_SET,_VAL_,0,0xffff0000)
+#define SET_PWM_INI_VALUE_P_3(_VAL_) SET_REG(ADR_PWM_3_SET,_VAL_,16,0x0000ffff)
+#define SET_PWM_POST_SCALER_4(_VAL_) SET_REG(ADR_PWM_4_CTRL,_VAL_,0,0xffffff00)
+#define SET_PWM_SETTING_UPDATE_4(_VAL_) SET_REG(ADR_PWM_4_CTRL,_VAL_,28,0xefffffff)
+#define SET_PWM_ALWAYSON_4(_VAL_) SET_REG(ADR_PWM_4_CTRL,_VAL_,29,0xdfffffff)
+#define SET_PWM_INVERT_4(_VAL_) SET_REG(ADR_PWM_4_CTRL,_VAL_,30,0xbfffffff)
+#define SET_PWM_ENABLE_4(_VAL_) SET_REG(ADR_PWM_4_CTRL,_VAL_,31,0x7fffffff)
+#define SET_PWM_INI_VALUE_PERIOD_4(_VAL_) SET_REG(ADR_PWM_4_SET,_VAL_,0,0xffff0000)
+#define SET_PWM_INI_VALUE_P_4(_VAL_) SET_REG(ADR_PWM_4_SET,_VAL_,16,0x0000ffff)
+#define SET_MANUAL_IO(_VAL_) SET_REG(ADR_MANUAL_IO,_VAL_,0,0xff800000)
+#define SET_MANUAL_PU(_VAL_) SET_REG(ADR_MANUAL_PU,_VAL_,0,0xff800000)
+#define SET_MANUAL_PD(_VAL_) SET_REG(ADR_MANUAL_PD,_VAL_,0,0xff800000)
+#define SET_MANUAL_DS(_VAL_) SET_REG(ADR_MANUAL_DS,_VAL_,0,0xff800000)
+#define SET_IO_PO(_VAL_) SET_REG(ADR_IO_PO,_VAL_,0,0xff800000)
+#define SET_IO_PI(_VAL_) SET_REG(ADR_IO_PI,_VAL_,0,0xff800000)
+#define SET_IO_PIE(_VAL_) SET_REG(ADR_IO_PIE,_VAL_,0,0xff800000)
+#define SET_IO_POEN(_VAL_) SET_REG(ADR_IO_POEN,_VAL_,0,0xff800000)
+#define SET_IO_PUE(_VAL_) SET_REG(ADR_IO_PUE,_VAL_,0,0xff800000)
+#define SET_IO_PDE(_VAL_) SET_REG(ADR_IO_PDE,_VAL_,0,0xff800000)
+#define SET_IO_DS(_VAL_) SET_REG(ADR_IO_DS,_VAL_,0,0xff800000)
+#define SET_SEL_I2STRX_II(_VAL_) SET_REG(ADR_IO_FUNC_SEL,_VAL_,0,0xfffffffe)
+#define SET_SEL_I2STRX_I(_VAL_) SET_REG(ADR_IO_FUNC_SEL,_VAL_,1,0xfffffffd)
+#define SET_SEL_SPI_SLV(_VAL_) SET_REG(ADR_IO_FUNC_SEL,_VAL_,2,0xfffffffb)
+#define SET_SEL_SPI_MST(_VAL_) SET_REG(ADR_IO_FUNC_SEL,_VAL_,3,0xfffffff7)
+#define SET_SEL_I2C_SLV(_VAL_) SET_REG(ADR_IO_FUNC_SEL,_VAL_,4,0xffffffef)
+#define SET_SEL_I2C_MST_II(_VAL_) SET_REG(ADR_IO_FUNC_SEL,_VAL_,5,0xffffffdf)
+#define SET_SEL_I2C_MST_I(_VAL_) SET_REG(ADR_IO_FUNC_SEL,_VAL_,6,0xffffffbf)
+#define SET_SEL_UART0_II(_VAL_) SET_REG(ADR_IO_FUNC_SEL,_VAL_,7,0xffffff7f)
+#define SET_SEL_UART0_I(_VAL_) SET_REG(ADR_IO_FUNC_SEL,_VAL_,8,0xfffffeff)
+#define SET_SEL_BTCX(_VAL_) SET_REG(ADR_IO_FUNC_SEL,_VAL_,9,0xfffffdff)
+#define SET_SEL_FLASH(_VAL_) SET_REG(ADR_IO_FUNC_SEL,_VAL_,10,0xfffffbff)
+#define SET_SEL_RF(_VAL_) SET_REG(ADR_IO_FUNC_SEL,_VAL_,11,0xfffff7ff)
+#define SET_SEL_PWM(_VAL_) SET_REG(ADR_IO_FUNC_SEL,_VAL_,12,0xfffe0fff)
+#define SET_SEL_DEBUG_I(_VAL_) SET_REG(ADR_IO_FUNC_SEL,_VAL_,17,0xfffdffff)
+#define SET_SEL_DEBUG_II(_VAL_) SET_REG(ADR_IO_FUNC_SEL,_VAL_,18,0xfffbffff)
+#define SET_SEL_MEM_BIST(_VAL_) SET_REG(ADR_IO_FUNC_SEL,_VAL_,19,0xfff7ffff)
+#define SET_SEL_USB_BIST(_VAL_) SET_REG(ADR_IO_FUNC_SEL,_VAL_,20,0xffefffff)
+#define SET_SEL_USB_TEST(_VAL_) SET_REG(ADR_IO_FUNC_SEL,_VAL_,21,0xffdfffff)
+#define SET_SEL_USB_IDDQ(_VAL_) SET_REG(ADR_IO_FUNC_SEL,_VAL_,22,0xffbfffff)
+#define SET_I2S_RAW_DATA(_VAL_) SET_REG(ADR_IO_FUNC_SEL,_VAL_,30,0xbfffffff)
+#define SET_SPI_RAW_DATA(_VAL_) SET_REG(ADR_IO_FUNC_SEL,_VAL_,31,0x7fffffff)
+#define SET_SEL_GPO_INT(_VAL_) SET_REG(ADR_INT_THRU_GPIO,_VAL_,0,0xff800000)
+#define SET_ROM_START_INDEX(_VAL_) SET_REG(ADR_BIST_CTRL,_VAL_,0,0xfffffff0)
+#define SET_ROM_END_INDEX(_VAL_) SET_REG(ADR_BIST_CTRL,_VAL_,4,0xffffff0f)
+#define SET_ROMCRC32_GOLDEN(_VAL_) SET_REG(ADR_BIST_CTRL1,_VAL_,0,0x00000000)
+#define SET_ROMCRC32_RESULT(_VAL_) SET_REG(ADR_BIST_CTRL2,_VAL_,0,0x00000000)
+#define SET_I2CS_ADDR_DC(_VAL_) SET_REG(ADR_I2CS_ID_ADDR,_VAL_,0,0xfffffffe)
+#define SET_I2CS_ADDR(_VAL_) SET_REG(ADR_I2CS_ID_ADDR,_VAL_,1,0xffffff01)
+#define SET_I2CS_INT(_VAL_) SET_REG(ADR_I2CS_STATUS,_VAL_,0,0xffffffe0)
+#define SET_I2CS_IDLE(_VAL_) SET_REG(ADR_I2CS_STATUS,_VAL_,10,0xfffffbff)
+#define SET_I2CS_TIME_OUT_CNT(_VAL_) SET_REG(ADR_I2CS_TIME_CNT,_VAL_,0,0xffff0000)
+#define SET_I2CS_STATE(_VAL_) SET_REG(ADR_I2CS_STATE,_VAL_,0,0xffffff00)
+#define SET_I2CS_DATA_CONFIG(_VAL_) SET_REG(ADR_I2CS_CTRL,_VAL_,0,0xfffffffe)
+#define SET_I2CS_HOLD_BUS_EN(_VAL_) SET_REG(ADR_I2CS_CTRL,_VAL_,1,0xfffffffd)
+#define SET_IO_PORT_REG(_VAL_) SET_REG(ADR_IO_PORT_REG,_VAL_,0,0xfffe0000)
+#define SET_MASK_RX_INT(_VAL_) SET_REG(ADR_INT_MASK_REG,_VAL_,0,0xfffffffe)
+#define SET_EDCA4_LOW_THR_INT_MASK(_VAL_) SET_REG(ADR_INT_MASK_REG,_VAL_,1,0xfffffffd)
+#define SET_MASK_SOC_SYSTEM_INT(_VAL_) SET_REG(ADR_INT_MASK_REG,_VAL_,2,0xfffffffb)
+#define SET_EDCA0_LOW_THR_INT_MASK(_VAL_) SET_REG(ADR_INT_MASK_REG,_VAL_,3,0xfffffff7)
+#define SET_EDCA1_LOW_THR_INT_MASK(_VAL_) SET_REG(ADR_INT_MASK_REG,_VAL_,4,0xffffffef)
+#define SET_EDCA2_LOW_THR_INT_MASK(_VAL_) SET_REG(ADR_INT_MASK_REG,_VAL_,5,0xffffffdf)
+#define SET_EDCA3_LOW_THR_INT_MASK(_VAL_) SET_REG(ADR_INT_MASK_REG,_VAL_,6,0xffffffbf)
+#define SET_TX_LIMIT_INT_MASK(_VAL_) SET_REG(ADR_INT_MASK_REG,_VAL_,7,0xffffff7f)
+#define SET_RX_INT(_VAL_) SET_REG(ADR_INT_STATUS_REG,_VAL_,0,0xfffffffe)
+#define SET_EDCA4_LOW_THR_INT_STS(_VAL_) SET_REG(ADR_INT_STATUS_REG,_VAL_,1,0xfffffffd)
+#define SET_SOC_SYSTEM_INT_STATUS(_VAL_) SET_REG(ADR_INT_STATUS_REG,_VAL_,2,0xfffffffb)
+#define SET_EDCA0_LOW_THR_INT_STS(_VAL_) SET_REG(ADR_INT_STATUS_REG,_VAL_,3,0xfffffff7)
+#define SET_EDCA1_LOW_THR_INT_STS(_VAL_) SET_REG(ADR_INT_STATUS_REG,_VAL_,4,0xffffffef)
+#define SET_EDCA2_LOW_THR_INT_STS(_VAL_) SET_REG(ADR_INT_STATUS_REG,_VAL_,5,0xffffffdf)
+#define SET_EDCA3_LOW_THR_INT_STS(_VAL_) SET_REG(ADR_INT_STATUS_REG,_VAL_,6,0xffffffbf)
+#define SET_TX_LIMIT_INT_STS(_VAL_) SET_REG(ADR_INT_STATUS_REG,_VAL_,7,0xffffff7f)
+#define SET_HOST_TRIGGERED_RX_INT(_VAL_) SET_REG(ADR_INT_STATUS_REG,_VAL_,8,0xfffffeff)
+#define SET_HOST_TRIGGERED_TX_INT(_VAL_) SET_REG(ADR_INT_STATUS_REG,_VAL_,9,0xfffffdff)
+#define SET_SOC_TRIGGER_RX_INT(_VAL_) SET_REG(ADR_INT_STATUS_REG,_VAL_,10,0xfffffbff)
+#define SET_SOC_TRIGGER_TX_INT(_VAL_) SET_REG(ADR_INT_STATUS_REG,_VAL_,11,0xfffff7ff)
+#define SET_RDY_FOR_TX_RX(_VAL_) SET_REG(ADR_FN1_STATUS_REG,_VAL_,0,0xfffffffe)
+#define SET_RDY_FOR_FW_DOWNLOAD(_VAL_) SET_REG(ADR_FN1_STATUS_REG,_VAL_,1,0xfffffffd)
+#define SET_ILLEGAL_CMD_RESP_OPTION(_VAL_) SET_REG(ADR_FN1_STATUS_REG,_VAL_,2,0xfffffffb)
+#define SET_SDIO_TRX_DATA_SEQUENCE(_VAL_) SET_REG(ADR_FN1_STATUS_REG,_VAL_,3,0xfffffff7)
+#define SET_GPIO_INT_TRIGGER_OPTION(_VAL_) SET_REG(ADR_FN1_STATUS_REG,_VAL_,4,0xffffffef)
+#define SET_TRIGGER_FUNCTION_SETTING(_VAL_) SET_REG(ADR_FN1_STATUS_REG,_VAL_,5,0xffffff9f)
+#define SET_CMD52_ABORT_RESPONSE(_VAL_) SET_REG(ADR_FN1_STATUS_REG,_VAL_,7,0xffffff7f)
+#define SET_CARD_RCA_REG(_VAL_) SET_REG(ADR_CARD_RCA_REG,_VAL_,0,0xffff0000)
+#define SET_SDIO_BYTE_MODE_BATCH_SIZE_REG(_VAL_) SET_REG(ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG,_VAL_,0,0xffffff00)
+#define SET_SDIO_CARD_STATUS_REG(_VAL_) SET_REG(ADR_SDIO_CARD_STATUS_REG,_VAL_,0,0x00000000)
+#define SET_R5_RESPONSE_FLAG(_VAL_) SET_REG(ADR_R5_RESP_FLAG_OUT_TIMING,_VAL_,0,0xffffff00)
+#define SET_MCU_TO_SDIO_INFO_MASK(_VAL_) SET_REG(ADR_R5_RESP_FLAG_OUT_TIMING,_VAL_,16,0xfffeffff)
+#define SET_INT_THROUGH_PIN(_VAL_) SET_REG(ADR_R5_RESP_FLAG_OUT_TIMING,_VAL_,17,0xfffdffff)
+#define SET_DIRECT_INT_MUX_MODE(_VAL_) SET_REG(ADR_R5_RESP_FLAG_OUT_TIMING,_VAL_,18,0xfffbffff)
+#define SET_SD_CMD_IN_DLY_SEL(_VAL_) SET_REG(ADR_SDIO_DELAY_CHAIN_0,_VAL_,0,0xfffffff8)
+#define SET_SD_CMD_OUT_DLY_SEL(_VAL_) SET_REG(ADR_SDIO_DELAY_CHAIN_0,_VAL_,4,0xffffff8f)
+#define SET_SD_DAT_3_IN_DLY_SEL(_VAL_) SET_REG(ADR_SDIO_DELAY_CHAIN_0,_VAL_,8,0xfffff8ff)
+#define SET_SD_DAT_3_OUT_DLY_SEL(_VAL_) SET_REG(ADR_SDIO_DELAY_CHAIN_0,_VAL_,12,0xffff8fff)
+#define SET_SD_DAT_2_IN_DLY_SEL(_VAL_) SET_REG(ADR_SDIO_DELAY_CHAIN_0,_VAL_,16,0xfff8ffff)
+#define SET_SD_DAT_2_OUT_DLY_SEL(_VAL_) SET_REG(ADR_SDIO_DELAY_CHAIN_0,_VAL_,20,0xff8fffff)
+#define SET_SD_DAT_1_IN_DLY_SEL(_VAL_) SET_REG(ADR_SDIO_DELAY_CHAIN_0,_VAL_,24,0xf8ffffff)
+#define SET_SD_DAT_1_OUT_DLY_SEL(_VAL_) SET_REG(ADR_SDIO_DELAY_CHAIN_0,_VAL_,28,0x8fffffff)
+#define SET_SD_DAT_0_IN_DLY_SEL(_VAL_) SET_REG(ADR_SDIO_DELAY_CHAIN_1,_VAL_,0,0xfffffff8)
+#define SET_SD_DAT_0_OUT_DLY_SEL(_VAL_) SET_REG(ADR_SDIO_DELAY_CHAIN_1,_VAL_,4,0xffffff8f)
+#define SET_FN1_DMA_START_ADDR_REG(_VAL_) SET_REG(ADR_FN1_DMA_START_ADDR_REG,_VAL_,0,0x00000000)
+#define SET_SDIO_TO_MCU_INFO(_VAL_) SET_REG(ADR_FN1_INT_CTRL_RESET,_VAL_,0,0xffffff00)
+#define SET_SDIO_PARTIAL_RESET(_VAL_) SET_REG(ADR_FN1_INT_CTRL_RESET,_VAL_,8,0xfffffeff)
+#define SET_SDIO_ALL_RESET(_VAL_) SET_REG(ADR_FN1_INT_CTRL_RESET,_VAL_,9,0xfffffdff)
+#define SET_PERI_MAC_ALL_RESET(_VAL_) SET_REG(ADR_FN1_INT_CTRL_RESET,_VAL_,10,0xfffffbff)
+#define SET_MAC_ALL_RESET(_VAL_) SET_REG(ADR_FN1_INT_CTRL_RESET,_VAL_,11,0xfffff7ff)
+#define SET_AHB_BRIDGE_RESET(_VAL_) SET_REG(ADR_FN1_INT_CTRL_RESET,_VAL_,12,0xffffefff)
+#define SET_MCU_TO_SDIO_INFO(_VAL_) SET_REG(ADR_MCU_NOTIFY_HOST_EVENT,_VAL_,0,0xffffff00)
+#define SET_FN1_DMA_RD_START_ADDR_REG(_VAL_) SET_REG(ADR_FN1_DMA_RD_START_ADDR_REG,_VAL_,0,0x00000000)
+#define SET_CCCR_00H_REG(_VAL_) SET_REG(ADR_CCCR_00H_REG,_VAL_,0,0xffffff00)
+#define SET_CCCR_02H_REG(_VAL_) SET_REG(ADR_CCCR_00H_REG,_VAL_,16,0xff00ffff)
+#define SET_CCCR_03H_REG(_VAL_) SET_REG(ADR_CCCR_00H_REG,_VAL_,24,0x00ffffff)
+#define SET_CCCR_04H_REG(_VAL_) SET_REG(ADR_CCCR_04H_REG,_VAL_,0,0xffffff00)
+#define SET_CCCR_05H_REG(_VAL_) SET_REG(ADR_CCCR_04H_REG,_VAL_,8,0xffff00ff)
+#define SET_CCCR_06H_REG(_VAL_) SET_REG(ADR_CCCR_04H_REG,_VAL_,16,0xfff0ffff)
+#define SET_CCCR_07H_REG(_VAL_) SET_REG(ADR_CCCR_04H_REG,_VAL_,24,0x00ffffff)
+#define SET_SUPPORT_DIRECT_COMMAND_SDIO(_VAL_) SET_REG(ADR_CCCR_08H_REG,_VAL_,0,0xfffffffe)
+#define SET_SUPPORT_MULTIPLE_BLOCK_TRANSFER(_VAL_) SET_REG(ADR_CCCR_08H_REG,_VAL_,1,0xfffffffd)
+#define SET_SUPPORT_READ_WAIT(_VAL_) SET_REG(ADR_CCCR_08H_REG,_VAL_,2,0xfffffffb)
+#define SET_SUPPORT_BUS_CONTROL(_VAL_) SET_REG(ADR_CCCR_08H_REG,_VAL_,3,0xfffffff7)
+#define SET_SUPPORT_BLOCK_GAP_INTERRUPT(_VAL_) SET_REG(ADR_CCCR_08H_REG,_VAL_,4,0xffffffef)
+#define SET_ENABLE_BLOCK_GAP_INTERRUPT(_VAL_) SET_REG(ADR_CCCR_08H_REG,_VAL_,5,0xffffffdf)
+#define SET_LOW_SPEED_CARD(_VAL_) SET_REG(ADR_CCCR_08H_REG,_VAL_,6,0xffffffbf)
+#define SET_LOW_SPEED_CARD_4BIT(_VAL_) SET_REG(ADR_CCCR_08H_REG,_VAL_,7,0xffffff7f)
+#define SET_COMMON_CIS_PONTER(_VAL_) SET_REG(ADR_CCCR_08H_REG,_VAL_,8,0xfe0000ff)
+#define SET_SD_SSDR50(_VAL_) SET_REG(ADR_CCCR_14H_REG,_VAL_,24,0xfeffffff)
+#define SET_SD_SSDR104(_VAL_) SET_REG(ADR_CCCR_14H_REG,_VAL_,25,0xfdffffff)
+#define SET_SUPPORT_HIGH_SPEED(_VAL_) SET_REG(ADR_CCCR_13H_REG,_VAL_,24,0xfeffffff)
+#define SET_BSS(_VAL_) SET_REG(ADR_CCCR_13H_REG,_VAL_,25,0xf1ffffff)
+#define SET_FBR_100H_REG(_VAL_) SET_REG(ADR_FBR_100H_REG,_VAL_,0,0xfffffff0)
+#define SET_CSASUPPORT(_VAL_) SET_REG(ADR_FBR_100H_REG,_VAL_,6,0xffffffbf)
+#define SET_ENABLECSA(_VAL_) SET_REG(ADR_FBR_100H_REG,_VAL_,7,0xffffff7f)
+#define SET_FBR_101H_REG(_VAL_) SET_REG(ADR_FBR_100H_REG,_VAL_,8,0xffff00ff)
+#define SET_FBR_109H_REG(_VAL_) SET_REG(ADR_FBR_109H_REG,_VAL_,8,0xfe0000ff)
+#define SET_F0_CIS_CONTENT_REG_31_0(_VAL_) SET_REG(ADR_F0_CIS_CONTENT_REG_0,_VAL_,0,0x00000000)
+#define SET_F0_CIS_CONTENT_REG_63_32(_VAL_) SET_REG(ADR_F0_CIS_CONTENT_REG_1,_VAL_,0,0x00000000)
+#define SET_F0_CIS_CONTENT_REG_95_64(_VAL_) SET_REG(ADR_F0_CIS_CONTENT_REG_2,_VAL_,0,0x00000000)
+#define SET_F0_CIS_CONTENT_REG_127_96(_VAL_) SET_REG(ADR_F0_CIS_CONTENT_REG_3,_VAL_,0,0x00000000)
+#define SET_F0_CIS_CONTENT_REG_159_128(_VAL_) SET_REG(ADR_F0_CIS_CONTENT_REG_4,_VAL_,0,0x00000000)
+#define SET_F0_CIS_CONTENT_REG_191_160(_VAL_) SET_REG(ADR_F0_CIS_CONTENT_REG_5,_VAL_,0,0x00000000)
+#define SET_F0_CIS_CONTENT_REG_223_192(_VAL_) SET_REG(ADR_F0_CIS_CONTENT_REG_6,_VAL_,0,0x00000000)
+#define SET_F0_CIS_CONTENT_REG_255_224(_VAL_) SET_REG(ADR_F0_CIS_CONTENT_REG_7,_VAL_,0,0x00000000)
+#define SET_F0_CIS_CONTENT_REG_287_256(_VAL_) SET_REG(ADR_F0_CIS_CONTENT_REG_8,_VAL_,0,0x00000000)
+#define SET_F0_CIS_CONTENT_REG_319_288(_VAL_) SET_REG(ADR_F0_CIS_CONTENT_REG_9,_VAL_,0,0x00000000)
+#define SET_F0_CIS_CONTENT_REG_351_320(_VAL_) SET_REG(ADR_F0_CIS_CONTENT_REG_10,_VAL_,0,0x00000000)
+#define SET_F0_CIS_CONTENT_REG_383_352(_VAL_) SET_REG(ADR_F0_CIS_CONTENT_REG_11,_VAL_,0,0x00000000)
+#define SET_F0_CIS_CONTENT_REG_415_384(_VAL_) SET_REG(ADR_F0_CIS_CONTENT_REG_12,_VAL_,0,0x00000000)
+#define SET_F0_CIS_CONTENT_REG_447_416(_VAL_) SET_REG(ADR_F0_CIS_CONTENT_REG_13,_VAL_,0,0x00000000)
+#define SET_F0_CIS_CONTENT_REG_479_448(_VAL_) SET_REG(ADR_F0_CIS_CONTENT_REG_14,_VAL_,0,0x00000000)
+#define SET_F0_CIS_CONTENT_REG_511_480(_VAL_) SET_REG(ADR_F0_CIS_CONTENT_REG_15,_VAL_,0,0x00000000)
+#define SET_F1_CIS_CONTENT_REG_31_0(_VAL_) SET_REG(ADR_F1_CIS_CONTENT_REG_0,_VAL_,0,0x00000000)
+#define SET_F1_CIS_CONTENT_REG_63_32(_VAL_) SET_REG(ADR_F1_CIS_CONTENT_REG_1,_VAL_,0,0x00000000)
+#define SET_F1_CIS_CONTENT_REG_95_64(_VAL_) SET_REG(ADR_F1_CIS_CONTENT_REG_2,_VAL_,0,0x00000000)
+#define SET_F1_CIS_CONTENT_REG_127_96(_VAL_) SET_REG(ADR_F1_CIS_CONTENT_REG_3,_VAL_,0,0x00000000)
+#define SET_F1_CIS_CONTENT_REG_159_128(_VAL_) SET_REG(ADR_F1_CIS_CONTENT_REG_4,_VAL_,0,0x00000000)
+#define SET_F1_CIS_CONTENT_REG_191_160(_VAL_) SET_REG(ADR_F1_CIS_CONTENT_REG_5,_VAL_,0,0x00000000)
+#define SET_F1_CIS_CONTENT_REG_223_192(_VAL_) SET_REG(ADR_F1_CIS_CONTENT_REG_6,_VAL_,0,0x00000000)
+#define SET_F1_CIS_CONTENT_REG_255_224(_VAL_) SET_REG(ADR_F1_CIS_CONTENT_REG_7,_VAL_,0,0x00000000)
+#define SET_F1_CIS_CONTENT_REG_287_256(_VAL_) SET_REG(ADR_F1_CIS_CONTENT_REG_8,_VAL_,0,0x00000000)
+#define SET_F1_CIS_CONTENT_REG_319_288(_VAL_) SET_REG(ADR_F1_CIS_CONTENT_REG_9,_VAL_,0,0x00000000)
+#define SET_F1_CIS_CONTENT_REG_351_320(_VAL_) SET_REG(ADR_F1_CIS_CONTENT_REG_10,_VAL_,0,0x00000000)
+#define SET_F1_CIS_CONTENT_REG_383_352(_VAL_) SET_REG(ADR_F1_CIS_CONTENT_REG_11,_VAL_,0,0x00000000)
+#define SET_F1_CIS_CONTENT_REG_415_384(_VAL_) SET_REG(ADR_F1_CIS_CONTENT_REG_12,_VAL_,0,0x00000000)
+#define SET_F1_CIS_CONTENT_REG_447_416(_VAL_) SET_REG(ADR_F1_CIS_CONTENT_REG_13,_VAL_,0,0x00000000)
+#define SET_F1_CIS_CONTENT_REG_479_448(_VAL_) SET_REG(ADR_F1_CIS_CONTENT_REG_14,_VAL_,0,0x00000000)
+#define SET_F1_CIS_CONTENT_REG_511_480(_VAL_) SET_REG(ADR_F1_CIS_CONTENT_REG_15,_VAL_,0,0x00000000)
+#define SET_SPARE_MEM(_VAL_) SET_REG(ADR_SPI_MODE,_VAL_,0,0xffffff00)
+#define SET_TX_SEG(_VAL_) SET_REG(ADR_TX_SEG,_VAL_,0,0x00000000)
+#define SET_CLK_WIDTH(_VAL_) SET_REG(ADR_SPI_TO_PHY_PARAM1,_VAL_,0,0xffff0000)
+#define SET_CSN_INTER(_VAL_) SET_REG(ADR_SPI_TO_PHY_PARAM1,_VAL_,16,0x0000ffff)
+#define SET_BACK_DLY(_VAL_) SET_REG(ADR_SPI_TO_PHY_PARAM2,_VAL_,0,0xffff0000)
+#define SET_FRONT_DLY(_VAL_) SET_REG(ADR_SPI_TO_PHY_PARAM2,_VAL_,16,0x0000ffff)
+#define SET_TWI_START_TRIG(_VAL_) SET_REG(ADR_TWIM_EN,_VAL_,0,0xfffffffe)
+#define SET_TWI_STOP_TRIG(_VAL_) SET_REG(ADR_TWIM_EN,_VAL_,1,0xfffffffd)
+#define SET_TWI_TRANS_CONTINUE(_VAL_) SET_REG(ADR_TWIM_EN,_VAL_,2,0xfffffffb)
+#define SET_TWI_DEV_A_10B(_VAL_) SET_REG(ADR_TWIM_STATUS_SETTING,_VAL_,0,0xfffffffe)
+#define SET_TWI_MODE(_VAL_) SET_REG(ADR_TWIM_STATUS_SETTING,_VAL_,1,0xfffffffd)
+#define SET_SCL(_VAL_) SET_REG(ADR_TWIM_STATUS_SETTING,_VAL_,16,0xfffeffff)
+#define SET_SDA(_VAL_) SET_REG(ADR_TWIM_STATUS_SETTING,_VAL_,17,0xfffdffff)
+#define SET_TWI_INT_TXD_STALL_EN(_VAL_) SET_REG(ADR_TWIM_INTERRUPT_EN,_VAL_,0,0xfffffffe)
+#define SET_TWI_INT_RXD_STALL_EN(_VAL_) SET_REG(ADR_TWIM_INTERRUPT_EN,_VAL_,1,0xfffffffd)
+#define SET_TWI_INT_TRANS_FINISH_EN(_VAL_) SET_REG(ADR_TWIM_INTERRUPT_EN,_VAL_,2,0xfffffffb)
+#define SET_TWI_INT_MISMATCH_EN(_VAL_) SET_REG(ADR_TWIM_INTERRUPT_EN,_VAL_,3,0xfffffff7)
+#define SET_TWI_INT_TRANS_FAIL_EN(_VAL_) SET_REG(ADR_TWIM_INTERRUPT_EN,_VAL_,4,0xffffffef)
+#define SET_TWI_INT_HOLD_BUS_EN(_VAL_) SET_REG(ADR_TWIM_INTERRUPT_EN,_VAL_,5,0xffffffdf)
+#define SET_TWI_INT_TXD_STALL(_VAL_) SET_REG(ADR_TWIM_INTERRUPT,_VAL_,0,0xfffffffe)
+#define SET_TWI_INT_RXD_STALL(_VAL_) SET_REG(ADR_TWIM_INTERRUPT,_VAL_,1,0xfffffffd)
+#define SET_TWI_INT_TRANS_FINISH(_VAL_) SET_REG(ADR_TWIM_INTERRUPT,_VAL_,2,0xfffffffb)
+#define SET_TWI_INT_MISMATCH(_VAL_) SET_REG(ADR_TWIM_INTERRUPT,_VAL_,3,0xfffffff7)
+#define SET_TWI_INT_TRANS_FAIL(_VAL_) SET_REG(ADR_TWIM_INTERRUPT,_VAL_,4,0xffffffef)
+#define SET_TWI_INT_HOLD_BUS(_VAL_) SET_REG(ADR_TWIM_INTERRUPT,_VAL_,5,0xffffffdf)
+#define SET_TWI_INT_TXD_STALL_ST(_VAL_) SET_REG(ADR_TWIM_INTERRUPT_STATUS,_VAL_,0,0xfffffffe)
+#define SET_TWI_INT_RXD_STALL_ST(_VAL_) SET_REG(ADR_TWIM_INTERRUPT_STATUS,_VAL_,1,0xfffffffd)
+#define SET_TWI_INT_TRANS_FINISH_ST(_VAL_) SET_REG(ADR_TWIM_INTERRUPT_STATUS,_VAL_,2,0xfffffffb)
+#define SET_TWI_INT_MISMATCH_ST(_VAL_) SET_REG(ADR_TWIM_INTERRUPT_STATUS,_VAL_,3,0xfffffff7)
+#define SET_TWI_INT_TRANS_FAIL_ST(_VAL_) SET_REG(ADR_TWIM_INTERRUPT_STATUS,_VAL_,4,0xffffffef)
+#define SET_TWI_INT_HOLD_BUS_ST(_VAL_) SET_REG(ADR_TWIM_INTERRUPT_STATUS,_VAL_,5,0xffffffdf)
+#define SET_TWI_STATUS_RECORD_0(_VAL_) SET_REG(ADR_TWIM_STATUS_RECORD_0,_VAL_,0,0x00000000)
+#define SET_TWI_STATUS_RECORD_1(_VAL_) SET_REG(ADR_TWIM_STATUS_RECORD_1,_VAL_,0,0x00000000)
+#define SET_TWI_RX(_VAL_) SET_REG(ADR_TWIM_DEV_A,_VAL_,0,0xfffffffe)
+#define SET_TWI_DEV_A10B(_VAL_) SET_REG(ADR_TWIM_DEV_A,_VAL_,1,0xfffff801)
+#define SET_TWI_TXD_DATA(_VAL_) SET_REG(ADR_TWIM_TXD_DATA,_VAL_,0,0xffffff00)
+#define SET_TWI_RXD_DATA(_VAL_) SET_REG(ADR_TWIM_RXD_DATA,_VAL_,0,0xffffff00)
+#define SET_TWI_PSCL(_VAL_) SET_REG(ADR_TWIM_PSCL,_VAL_,0,0xfffffc00)
+#define SET_TWI_STA_STO_PSCL(_VAL_) SET_REG(ADR_TWIM_PSCL,_VAL_,16,0xfc00ffff)
+#define SET_TWI_TRANS_PSDA(_VAL_) SET_REG(ADR_TWIM_TRANS_PSDA,_VAL_,0,0xfffffc00)
+#define SET_TWI_DELAY_ACK(_VAL_) SET_REG(ADR_TWIM_DELAY_ACK,_VAL_,0,0xfffffc00)
+#define SET_I2CM_INT_WDONE(_VAL_) SET_REG(ADR_I2CM_EN,_VAL_,0,0xfffffffe)
+#define SET_I2CM_INT_RDONE(_VAL_) SET_REG(ADR_I2CM_EN,_VAL_,1,0xfffffffd)
+#define SET_I2CM_IDLE(_VAL_) SET_REG(ADR_I2CM_EN,_VAL_,2,0xfffffffb)
+#define SET_I2CM_INT_MISMATCH(_VAL_) SET_REG(ADR_I2CM_EN,_VAL_,3,0xfffffff7)
+#define SET_I2CM_PSCL(_VAL_) SET_REG(ADR_I2CM_EN,_VAL_,4,0xffffc00f)
+#define SET_I2CM_MANUAL_MODE(_VAL_) SET_REG(ADR_I2CM_EN,_VAL_,16,0xfffeffff)
+#define SET_I2CM_INT_WDATA_NEED(_VAL_) SET_REG(ADR_I2CM_EN,_VAL_,17,0xfffdffff)
+#define SET_I2CM_INT_RDATA_NEED(_VAL_) SET_REG(ADR_I2CM_EN,_VAL_,18,0xfffbffff)
+#define SET_I2CM_DEV_A(_VAL_) SET_REG(ADR_I2CM_DEV_A,_VAL_,0,0xfffffc00)
+#define SET_I2CM_DEV_A10B(_VAL_) SET_REG(ADR_I2CM_DEV_A,_VAL_,14,0xffffbfff)
+#define SET_I2CM_RX(_VAL_) SET_REG(ADR_I2CM_DEV_A,_VAL_,15,0xffff7fff)
+#define SET_I2CM_LEN(_VAL_) SET_REG(ADR_I2CM_LEN,_VAL_,0,0xffff0000)
+#define SET_I2CM_T_LEFT(_VAL_) SET_REG(ADR_I2CM_LEN,_VAL_,16,0xfff8ffff)
+#define SET_I2CM_R_GET(_VAL_) SET_REG(ADR_I2CM_LEN,_VAL_,24,0xf8ffffff)
+#define SET_I2CM_WDAT(_VAL_) SET_REG(ADR_I2CM_WDAT,_VAL_,0,0x00000000)
+#define SET_I2CM_RDAT(_VAL_) SET_REG(ADR_I2CM_RDAT,_VAL_,0,0x00000000)
+#define SET_I2CM_SR_LEN(_VAL_) SET_REG(ADR_I2CM_EN_2,_VAL_,0,0xffff0000)
+#define SET_I2CM_SR_RX(_VAL_) SET_REG(ADR_I2CM_EN_2,_VAL_,16,0xfffeffff)
+#define SET_I2CM_REPEAT_START(_VAL_) SET_REG(ADR_I2CM_EN_2,_VAL_,17,0xfffdffff)
+#define SET_I2CM_STA_STO_PSCL(_VAL_) SET_REG(ADR_I2CM_START_STOP_PERIOD,_VAL_,0,0xfffffc00)
+#define SET_UART_DATA(_VAL_) SET_REG(ADR_UART_DATA,_VAL_,0,0xffffff00)
+#define SET_DATA_RDY_IE(_VAL_) SET_REG(ADR_UART_IER,_VAL_,0,0xfffffffe)
+#define SET_THR_EMPTY_IE(_VAL_) SET_REG(ADR_UART_IER,_VAL_,1,0xfffffffd)
+#define SET_RX_LINESTS_IE(_VAL_) SET_REG(ADR_UART_IER,_VAL_,2,0xfffffffb)
+#define SET_MDM_STS_IE(_VAL_) SET_REG(ADR_UART_IER,_VAL_,3,0xfffffff7)
+#define SET_TX_THRH_IE(_VAL_) SET_REG(ADR_UART_IER,_VAL_,4,0xffffffef)
+#define SET_TX_THRL_IE(_VAL_) SET_REG(ADR_UART_IER,_VAL_,5,0xffffffdf)
+#define SET_FIFO_EN(_VAL_) SET_REG(ADR_UART_FCR,_VAL_,0,0xfffffffe)
+#define SET_RXFIFO_RST(_VAL_) SET_REG(ADR_UART_FCR,_VAL_,1,0xfffffffd)
+#define SET_TXFIFO_RST(_VAL_) SET_REG(ADR_UART_FCR,_VAL_,2,0xfffffffb)
+#define SET_DMA_MODE(_VAL_) SET_REG(ADR_UART_FCR,_VAL_,3,0xfffffff7)
+#define SET_EN_AUTO_RTS(_VAL_) SET_REG(ADR_UART_FCR,_VAL_,4,0xffffffef)
+#define SET_EN_AUTO_CTS(_VAL_) SET_REG(ADR_UART_FCR,_VAL_,5,0xffffffdf)
+#define SET_RXFIFO_TRGLVL(_VAL_) SET_REG(ADR_UART_FCR,_VAL_,6,0xffffff3f)
+#define SET_WORD_LEN(_VAL_) SET_REG(ADR_UART_LCR,_VAL_,0,0xfffffffc)
+#define SET_STOP_BIT(_VAL_) SET_REG(ADR_UART_LCR,_VAL_,2,0xfffffffb)
+#define SET_PARITY_EN(_VAL_) SET_REG(ADR_UART_LCR,_VAL_,3,0xfffffff7)
+#define SET_EVEN_PARITY(_VAL_) SET_REG(ADR_UART_LCR,_VAL_,4,0xffffffef)
+#define SET_FORCE_PARITY(_VAL_) SET_REG(ADR_UART_LCR,_VAL_,5,0xffffffdf)
+#define SET_SET_BREAK(_VAL_) SET_REG(ADR_UART_LCR,_VAL_,6,0xffffffbf)
+#define SET_DLAB(_VAL_) SET_REG(ADR_UART_LCR,_VAL_,7,0xffffff7f)
+#define SET_DTR(_VAL_) SET_REG(ADR_UART_MCR,_VAL_,0,0xfffffffe)
+#define SET_RTS(_VAL_) SET_REG(ADR_UART_MCR,_VAL_,1,0xfffffffd)
+#define SET_OUT_1(_VAL_) SET_REG(ADR_UART_MCR,_VAL_,2,0xfffffffb)
+#define SET_OUT_2(_VAL_) SET_REG(ADR_UART_MCR,_VAL_,3,0xfffffff7)
+#define SET_LOOP_BACK(_VAL_) SET_REG(ADR_UART_MCR,_VAL_,4,0xffffffef)
+#define SET_DE_RTS(_VAL_) SET_REG(ADR_UART_MCR,_VAL_,5,0xffffffdf)
+#define SET_DATA_RDY(_VAL_) SET_REG(ADR_UART_LSR,_VAL_,0,0xfffffffe)
+#define SET_OVERRUN_ERR(_VAL_) SET_REG(ADR_UART_LSR,_VAL_,1,0xfffffffd)
+#define SET_PARITY_ERR(_VAL_) SET_REG(ADR_UART_LSR,_VAL_,2,0xfffffffb)
+#define SET_FRAMING_ERR(_VAL_) SET_REG(ADR_UART_LSR,_VAL_,3,0xfffffff7)
+#define SET_BREAK_INT(_VAL_) SET_REG(ADR_UART_LSR,_VAL_,4,0xffffffef)
+#define SET_THR_EMPTY(_VAL_) SET_REG(ADR_UART_LSR,_VAL_,5,0xffffffdf)
+#define SET_TX_EMPTY(_VAL_) SET_REG(ADR_UART_LSR,_VAL_,6,0xffffffbf)
+#define SET_FIFODATA_ERR(_VAL_) SET_REG(ADR_UART_LSR,_VAL_,7,0xffffff7f)
+#define SET_DELTA_CTS(_VAL_) SET_REG(ADR_UART_MSR,_VAL_,0,0xfffffffe)
+#define SET_DELTA_DSR(_VAL_) SET_REG(ADR_UART_MSR,_VAL_,1,0xfffffffd)
+#define SET_TRAILEDGE_RI(_VAL_) SET_REG(ADR_UART_MSR,_VAL_,2,0xfffffffb)
+#define SET_DELTA_CD(_VAL_) SET_REG(ADR_UART_MSR,_VAL_,3,0xfffffff7)
+#define SET_CTS(_VAL_) SET_REG(ADR_UART_MSR,_VAL_,4,0xffffffef)
+#define SET_DSR(_VAL_) SET_REG(ADR_UART_MSR,_VAL_,5,0xffffffdf)
+#define SET_RI(_VAL_) SET_REG(ADR_UART_MSR,_VAL_,6,0xffffffbf)
+#define SET_CD(_VAL_) SET_REG(ADR_UART_MSR,_VAL_,7,0xffffff7f)
+#define SET_BRDC_DIV(_VAL_) SET_REG(ADR_UART_SPR,_VAL_,0,0xffff0000)
+#define SET_RTHR_L(_VAL_) SET_REG(ADR_UART_RTHR,_VAL_,0,0xfffffff0)
+#define SET_RTHR_H(_VAL_) SET_REG(ADR_UART_RTHR,_VAL_,4,0xffffff0f)
+#define SET_INT_IDCODE(_VAL_) SET_REG(ADR_UART_ISR,_VAL_,0,0xfffffff0)
+#define SET_RX_IDLE(_VAL_) SET_REG(ADR_UART_ISR,_VAL_,4,0xffffffef)
+#define SET_TX_IDLE(_VAL_) SET_REG(ADR_UART_ISR,_VAL_,5,0xffffffdf)
+#define SET_FIFOS_ENABLED(_VAL_) SET_REG(ADR_UART_ISR,_VAL_,6,0xffffff3f)
+#define SET_TTHR_L(_VAL_) SET_REG(ADR_UART_TTHR,_VAL_,0,0xfffffff0)
+#define SET_TTHR_H(_VAL_) SET_REG(ADR_UART_TTHR,_VAL_,4,0xffffff0f)
+#define SET_RX_RECIEVED(_VAL_) SET_REG(ADR_UART_INT_MAP,_VAL_,0,0xfffffffe)
+#define SET_RX_FIFO_TO(_VAL_) SET_REG(ADR_UART_INT_MAP,_VAL_,1,0xfffffffd)
+#define SET_TX_L(_VAL_) SET_REG(ADR_UART_INT_MAP,_VAL_,2,0xfffffffb)
+#define SET_TX_H(_VAL_) SET_REG(ADR_UART_INT_MAP,_VAL_,3,0xfffffff7)
+#define SET_TX_EMPTY2(_VAL_) SET_REG(ADR_UART_INT_MAP,_VAL_,4,0xffffffef)
+#define SET_OVERRUN(_VAL_) SET_REG(ADR_UART_INT_MAP,_VAL_,5,0xffffffdf)
+#define SET_FRAMING(_VAL_) SET_REG(ADR_UART_INT_MAP,_VAL_,6,0xffffffbf)
+#define SET_BREAK(_VAL_) SET_REG(ADR_UART_INT_MAP,_VAL_,7,0xffffff7f)
+#define SET_PARITY(_VAL_) SET_REG(ADR_UART_INT_MAP,_VAL_,8,0xfffffeff)
+#define SET_MODEN_INT(_VAL_) SET_REG(ADR_UART_INT_MAP,_VAL_,9,0xfffffdff)
+#define SET_ROP_A(_VAL_) SET_REG(ADR_UART_POINTER,_VAL_,0,0xfffffff0)
+#define SET_RIP_A(_VAL_) SET_REG(ADR_UART_POINTER,_VAL_,4,0xffffff0f)
+#define SET_TOP_A(_VAL_) SET_REG(ADR_UART_POINTER,_VAL_,8,0xfffff0ff)
+#define SET_TIP_A(_VAL_) SET_REG(ADR_UART_POINTER,_VAL_,12,0xffff0fff)
+#define SET_HSUART_RXD(_VAL_) SET_REG(ADR_HSUART_TRX_CHAR,_VAL_,0,0xffffff00)
+#define SET_HSUART_ENABRXBUFF(_VAL_) SET_REG(ADR_HSUART_INTRRUPT_ENABLE,_VAL_,0,0xfffffffe)
+#define SET_HSUART_ENABTXBUFF(_VAL_) SET_REG(ADR_HSUART_INTRRUPT_ENABLE,_VAL_,1,0xfffffffd)
+#define SET_HSUART_ENABLNSTAT(_VAL_) SET_REG(ADR_HSUART_INTRRUPT_ENABLE,_VAL_,2,0xfffffffb)
+#define SET_HSUART_ENABMDSTAT(_VAL_) SET_REG(ADR_HSUART_INTRRUPT_ENABLE,_VAL_,3,0xfffffff7)
+#define SET_HSUART_ENABCTXTHR(_VAL_) SET_REG(ADR_HSUART_INTRRUPT_ENABLE,_VAL_,4,0xffffffef)
+#define SET_HSUART_ENABDMARXEND(_VAL_) SET_REG(ADR_HSUART_INTRRUPT_ENABLE,_VAL_,6,0xffffffbf)
+#define SET_HSUART_ENABDMATXEND(_VAL_) SET_REG(ADR_HSUART_INTRRUPT_ENABLE,_VAL_,7,0xffffff7f)
+#define SET_HSUART_FIFOE(_VAL_) SET_REG(ADR_HSUART_FIFO_CTRL,_VAL_,0,0xfffffffe)
+#define SET_HSUART_RX_FIFO_RST(_VAL_) SET_REG(ADR_HSUART_FIFO_CTRL,_VAL_,1,0xfffffffd)
+#define SET_HSUART_TX_FIFO_RST(_VAL_) SET_REG(ADR_HSUART_FIFO_CTRL,_VAL_,2,0xfffffffb)
+#define SET_HSUART_DMA(_VAL_) SET_REG(ADR_HSUART_FIFO_CTRL,_VAL_,3,0xfffffff7)
+#define SET_HSUART_RX_TRIG_LV(_VAL_) SET_REG(ADR_HSUART_FIFO_CTRL,_VAL_,6,0xffffff3f)
+#define SET_HSUART_WLS(_VAL_) SET_REG(ADR_HSUART_LINE_CTRL,_VAL_,0,0xfffffffc)
+#define SET_HSUART_STB(_VAL_) SET_REG(ADR_HSUART_LINE_CTRL,_VAL_,2,0xfffffffb)
+#define SET_HSUART_PEN(_VAL_) SET_REG(ADR_HSUART_LINE_CTRL,_VAL_,3,0xfffffff7)
+#define SET_HSUART_SP_EPS(_VAL_) SET_REG(ADR_HSUART_LINE_CTRL,_VAL_,4,0xffffffcf)
+#define SET_HSUART_SB(_VAL_) SET_REG(ADR_HSUART_LINE_CTRL,_VAL_,6,0xffffffbf)
+#define SET_HSUART_DLAB(_VAL_) SET_REG(ADR_HSUART_LINE_CTRL,_VAL_,7,0xffffff7f)
+#define SET_HSUART_DTS(_VAL_) SET_REG(ADR_HSUART_MODEM_CTRL,_VAL_,0,0xfffffffe)
+#define SET_HSUART_RTS(_VAL_) SET_REG(ADR_HSUART_MODEM_CTRL,_VAL_,1,0xfffffffd)
+#define SET_HSUART_OUT1(_VAL_) SET_REG(ADR_HSUART_MODEM_CTRL,_VAL_,2,0xfffffffb)
+#define SET_HSUART_OUT2(_VAL_) SET_REG(ADR_HSUART_MODEM_CTRL,_VAL_,3,0xfffffff7)
+#define SET_HSUART_LOOP1(_VAL_) SET_REG(ADR_HSUART_MODEM_CTRL,_VAL_,4,0xffffffef)
+#define SET_HSUART_ARTS(_VAL_) SET_REG(ADR_HSUART_MODEM_CTRL,_VAL_,6,0xffffffbf)
+#define SET_HSUART_ACTS(_VAL_) SET_REG(ADR_HSUART_MODEM_CTRL,_VAL_,7,0xffffff7f)
+#define SET_HSUART_DR(_VAL_) SET_REG(ADR_HSUART_LINE_STATUS,_VAL_,0,0xfffffffe)
+#define SET_HSUART_OE(_VAL_) SET_REG(ADR_HSUART_LINE_STATUS,_VAL_,1,0xfffffffd)
+#define SET_HSUART_PE(_VAL_) SET_REG(ADR_HSUART_LINE_STATUS,_VAL_,2,0xfffffffb)
+#define SET_HSUART_FE(_VAL_) SET_REG(ADR_HSUART_LINE_STATUS,_VAL_,3,0xfffffff7)
+#define SET_HSUART_BI(_VAL_) SET_REG(ADR_HSUART_LINE_STATUS,_VAL_,4,0xffffffef)
+#define SET_HSUART_THRE(_VAL_) SET_REG(ADR_HSUART_LINE_STATUS,_VAL_,5,0xffffffdf)
+#define SET_HSUART_TSRE(_VAL_) SET_REG(ADR_HSUART_LINE_STATUS,_VAL_,6,0xffffffbf)
+#define SET_HSUART_ERF(_VAL_) SET_REG(ADR_HSUART_LINE_STATUS,_VAL_,7,0xffffff7f)
+#define SET_HSUART_DCTS(_VAL_) SET_REG(ADR_HSUART_MODEM_STATUS,_VAL_,0,0xfffffffe)
+#define SET_HSUART_DDSR(_VAL_) SET_REG(ADR_HSUART_MODEM_STATUS,_VAL_,1,0xfffffffd)
+#define SET_HSUART_TERI(_VAL_) SET_REG(ADR_HSUART_MODEM_STATUS,_VAL_,2,0xfffffffb)
+#define SET_HSUART_DDCD(_VAL_) SET_REG(ADR_HSUART_MODEM_STATUS,_VAL_,3,0xfffffff7)
+#define SET_HSUART_CTS(_VAL_) SET_REG(ADR_HSUART_MODEM_STATUS,_VAL_,4,0xffffffef)
+#define SET_HSUART_DSR(_VAL_) SET_REG(ADR_HSUART_MODEM_STATUS,_VAL_,5,0xffffffdf)
+#define SET_HSUART_RI(_VAL_) SET_REG(ADR_HSUART_MODEM_STATUS,_VAL_,6,0xffffffbf)
+#define SET_HSUART_DCR(_VAL_) SET_REG(ADR_HSUART_MODEM_STATUS,_VAL_,7,0xffffff7f)
+#define SET_HSUART_SCR(_VAL_) SET_REG(ADR_HSUART_SCRATCH_BOARD,_VAL_,0,0xffffff00)
+#define SET_HSUART_RTS_AUTO_TH_L(_VAL_) SET_REG(ADR_HSUART_FIFO_THRESHOLD,_VAL_,0,0xffffffe0)
+#define SET_HSUART_RTS_AUTO_TH_H(_VAL_) SET_REG(ADR_HSUART_FIFO_THRESHOLD,_VAL_,8,0xffffe0ff)
+#define SET_HSUART_TX_THR_L(_VAL_) SET_REG(ADR_HSUART_FIFO_THRESHOLD,_VAL_,16,0xffe0ffff)
+#define SET_HSUART_TX_THR_H(_VAL_) SET_REG(ADR_HSUART_FIFO_THRESHOLD,_VAL_,24,0xe0ffffff)
+#define SET_HSUART_IIR(_VAL_) SET_REG(ADR_HSUART_INTERRUPT_STATUS,_VAL_,0,0xfffffff0)
+#define SET_HSUART_TXDMA_DONE(_VAL_) SET_REG(ADR_HSUART_INTERRUPT_STATUS,_VAL_,5,0xffffffdf)
+#define SET_HSUART_IFOFOE0(_VAL_) SET_REG(ADR_HSUART_INTERRUPT_STATUS,_VAL_,6,0xffffffbf)
+#define SET_HSUART_IFIFOE1(_VAL_) SET_REG(ADR_HSUART_INTERRUPT_STATUS,_VAL_,7,0xffffff7f)
+#define SET_HSUART_DIV(_VAL_) SET_REG(ADR_HSUART_DIV_FRAC,_VAL_,0,0xffff0000)
+#define SET_HSUART_FRAC(_VAL_) SET_REG(ADR_HSUART_DIV_FRAC,_VAL_,16,0xff00ffff)
+#define SET_HSUART_INT(_VAL_) SET_REG(ADR_HSUART_EXPANSION_INTERRUPT_STATUS,_VAL_,0,0xffff0000)
+#define SET_HSUART_DMA_RX_STR_ADDR(_VAL_) SET_REG(ADR_HSUART_DMA_RX_STR_ADDR,_VAL_,0,0x00000000)
+#define SET_HSUART_DMA_RX_END_ADDR(_VAL_) SET_REG(ADR_HSUART_DMA_RX_END_ADDR,_VAL_,0,0x00000000)
+#define SET_HSUART_DMA_RX_WPT(_VAL_) SET_REG(ADR_HSUART_DMA_RX_WPT,_VAL_,0,0x00000000)
+#define SET_HSUART_DMA_RX_RPT(_VAL_) SET_REG(ADR_HSUART_DMA_RX_RPT,_VAL_,0,0x00000000)
+#define SET_HSUART_DMA_TX_STR_ADDR(_VAL_) SET_REG(ADR_HSUART_DMA_TX_STR_ADDR,_VAL_,0,0x00000000)
+#define SET_HSUART_DMA_TX_END_ADDR(_VAL_) SET_REG(ADR_HSUART_DMA_TX_END_ADDR,_VAL_,0,0x00000000)
+#define SET_HSUART_DMA_TX_WPT(_VAL_) SET_REG(ADR_HSUART_DMA_TX_WPT,_VAL_,0,0x00000000)
+#define SET_HSUART_DMA_TX_RPT(_VAL_) SET_REG(ADR_HSUART_DMA_TX_RPT,_VAL_,0,0x00000000)
+#define SET_MANUAL_T_ADDR(_VAL_) SET_REG(ADR_MANUAL_MODE_TX_ADDR,_VAL_,0,0x00000000)
+#define SET_MANUAL_R_ADDR(_VAL_) SET_REG(ADR_MANUAL_MODE_RX_ADDR,_VAL_,0,0x00000000)
+#define SET_FLASH_FRONT_DLY(_VAL_) SET_REG(ADR_SPI_PARAM,_VAL_,0,0xfffffff0)
+#define SET_FLASH_BACK_DLY(_VAL_) SET_REG(ADR_SPI_PARAM,_VAL_,4,0xffffff0f)
+#define SET_CSN_DLY(_VAL_) SET_REG(ADR_SPI_PARAM,_VAL_,8,0xfffff0ff)
+#define SET_INDICATOR(_VAL_) SET_REG(ADR_SPI_PARAM,_VAL_,12,0xfff00fff)
+#define SET_DUMY_DLY(_VAL_) SET_REG(ADR_SPI_PARAM,_VAL_,20,0xff0fffff)
+#define SET_MEM_SEL(_VAL_) SET_REG(ADR_SPI_PARAM,_VAL_,24,0xfeffffff)
+#define SET_SPI_BUSY(_VAL_) SET_REG(ADR_SPI_PARAM2,_VAL_,0,0xfffffffe)
+#define SET_SPI_FLASH_MODE(_VAL_) SET_REG(ADR_SPI_PARAM2,_VAL_,1,0xfffffff9)
+#define SET_MANUAL_MODE_BUSY(_VAL_) SET_REG(ADR_SPI_PARAM2,_VAL_,3,0xfffffff7)
+#define SET_PREFETCH_EN(_VAL_) SET_REG(ADR_SPI_PARAM2,_VAL_,4,0xffffffef)
+#define SET_WRAP_EN(_VAL_) SET_REG(ADR_SPI_PARAM2,_VAL_,5,0xffffffdf)
+#define SET_CONTINUE_R_EN(_VAL_) SET_REG(ADR_SPI_PARAM2,_VAL_,6,0xffffffbf)
+#define SET_MANUAL_T_LEN(_VAL_) SET_REG(ADR_SPI_TX_LEN,_VAL_,0,0xffff0000)
+#define SET_MANUAL_R_LEN(_VAL_) SET_REG(ADR_SPI_RX_LEN,_VAL_,0,0xffff0000)
+#define SET_BIT1_WR_CMD(_VAL_) SET_REG(ADR_CMD_SET,_VAL_,0,0xffffff00)
+#define SET_BIT1_RD_CMD(_VAL_) SET_REG(ADR_CMD_SET,_VAL_,8,0xffff00ff)
+#define SET_BIT2_RD_CMD(_VAL_) SET_REG(ADR_CMD_SET,_VAL_,16,0xff00ffff)
+#define SET_BIT4_RD_CMD(_VAL_) SET_REG(ADR_CMD_SET,_VAL_,24,0x00ffffff)
+#define SET_BIT4_WR_CMD(_VAL_) SET_REG(ADR_CMD_SET_1,_VAL_,0,0xffffff00)
+#define SET_FLS_CLK_IN_DLY_SEL(_VAL_) SET_REG(ADR_FLASH_IO0_DLY,_VAL_,0,0xfffffff8)
+#define SET_FLS_CLK_OUT_DLY_SEL(_VAL_) SET_REG(ADR_FLASH_IO0_DLY,_VAL_,4,0xffffff8f)
+#define SET_FLS_MOSI_IN_DLY_SEL(_VAL_) SET_REG(ADR_FLASH_IO0_DLY,_VAL_,8,0xfffff8ff)
+#define SET_FLS_MOSI_OUT_DLY_SEL(_VAL_) SET_REG(ADR_FLASH_IO0_DLY,_VAL_,12,0xffff8fff)
+#define SET_FLS_MISO_IN_DLY_SEL(_VAL_) SET_REG(ADR_FLASH_IO0_DLY,_VAL_,16,0xfff8ffff)
+#define SET_FLS_MISO_OUT_DLY_SEL(_VAL_) SET_REG(ADR_FLASH_IO0_DLY,_VAL_,20,0xff8fffff)
+#define SET_FLS_WP_IN_DLY_SEL(_VAL_) SET_REG(ADR_FLASH_IO0_DLY,_VAL_,24,0xf8ffffff)
+#define SET_FLS_WP_OUT_DLY_SEL(_VAL_) SET_REG(ADR_FLASH_IO0_DLY,_VAL_,28,0x8fffffff)
+#define SET_FLS_NC_IN_DLY_SEL(_VAL_) SET_REG(ADR_FLASH_IO1_DLY,_VAL_,0,0xfffffff8)
+#define SET_FLS_NC_OUT_DLY_SEL(_VAL_) SET_REG(ADR_FLASH_IO1_DLY,_VAL_,4,0xffffff8f)
+#define SET_SPI_F_MISO_CLK_SEL(_VAL_) SET_REG(ADR_FLASH_IO1_DLY,_VAL_,8,0xfffffeff)
+#define SET_INS_START_ADDR(_VAL_) SET_REG(ADR_INS_SPACE_START_ADDR,_VAL_,0,0xff000000)
+#define SET_INS_END_ADDR(_VAL_) SET_REG(ADR_INS_SPACE_END_ADDR,_VAL_,0,0xff000000)
+#define SET_INS_BUF_CLR(_VAL_) SET_REG(ADR_BUFFER_CLEAR_ERROR_FLAG_CLEAR,_VAL_,0,0xfffffffe)
+#define SET_RW_BUF_CLR(_VAL_) SET_REG(ADR_BUFFER_CLEAR_ERROR_FLAG_CLEAR,_VAL_,1,0xfffffffd)
+#define SET_ERR_FLAG_CLR(_VAL_) SET_REG(ADR_BUFFER_CLEAR_ERROR_FLAG_CLEAR,_VAL_,2,0xfffffffb)
+#define SET_DMA_ADR_SRC(_VAL_) SET_REG(ADR_DMA_ADR_SRC,_VAL_,0,0x00000000)
+#define SET_DMA_ADR_DST(_VAL_) SET_REG(ADR_DMA_ADR_DST,_VAL_,0,0x00000000)
+#define SET_DMA_SRC_SIZE(_VAL_) SET_REG(ADR_DMA_CTRL,_VAL_,0,0xfffffff8)
+#define SET_DMA_SRC_INC(_VAL_) SET_REG(ADR_DMA_CTRL,_VAL_,3,0xfffffff7)
+#define SET_DMA_DST_SIZE(_VAL_) SET_REG(ADR_DMA_CTRL,_VAL_,4,0xffffff8f)
+#define SET_DMA_DST_INC(_VAL_) SET_REG(ADR_DMA_CTRL,_VAL_,7,0xffffff7f)
+#define SET_DMA_FAST_FILL(_VAL_) SET_REG(ADR_DMA_CTRL,_VAL_,8,0xfffffeff)
+#define SET_DMA_SDIO_KICK(_VAL_) SET_REG(ADR_DMA_CTRL,_VAL_,12,0xffffefff)
+#define SET_DMA_BADR_EN(_VAL_) SET_REG(ADR_DMA_CTRL,_VAL_,13,0xffffdfff)
+#define SET_DMA_LEN(_VAL_) SET_REG(ADR_DMA_CTRL,_VAL_,16,0x0000ffff)
+#define SET_DMA_INT_MASK(_VAL_) SET_REG(ADR_DMA_INT,_VAL_,0,0xfffffffe)
+#define SET_DMA_STS(_VAL_) SET_REG(ADR_DMA_INT,_VAL_,8,0xfffffeff)
+#define SET_DMA_FINISH(_VAL_) SET_REG(ADR_DMA_INT,_VAL_,31,0x7fffffff)
+#define SET_DMA_CONST(_VAL_) SET_REG(ADR_DMA_FILL_CONST,_VAL_,0,0x00000000)
+#define SET_D2_DMA_ADR_SRC(_VAL_) SET_REG(ADR_D2_DMA_ADR_SRC,_VAL_,0,0x00000000)
+#define SET_D2_DMA_ADR_DST(_VAL_) SET_REG(ADR_D2_DMA_ADR_DST,_VAL_,0,0x00000000)
+#define SET_D2_DMA_SRC_SIZE(_VAL_) SET_REG(ADR_D2_DMA_CTRL,_VAL_,0,0xfffffff8)
+#define SET_D2_DMA_SRC_INC(_VAL_) SET_REG(ADR_D2_DMA_CTRL,_VAL_,3,0xfffffff7)
+#define SET_D2_DMA_DST_SIZE(_VAL_) SET_REG(ADR_D2_DMA_CTRL,_VAL_,4,0xffffff8f)
+#define SET_D2_DMA_DST_INC(_VAL_) SET_REG(ADR_D2_DMA_CTRL,_VAL_,7,0xffffff7f)
+#define SET_D2_DMA_FAST_FILL(_VAL_) SET_REG(ADR_D2_DMA_CTRL,_VAL_,8,0xfffffeff)
+#define SET_D2_DMA_SDIO_KICK(_VAL_) SET_REG(ADR_D2_DMA_CTRL,_VAL_,12,0xffffefff)
+#define SET_D2_DMA_BADR_EN(_VAL_) SET_REG(ADR_D2_DMA_CTRL,_VAL_,13,0xffffdfff)
+#define SET_D2_DMA_LEN(_VAL_) SET_REG(ADR_D2_DMA_CTRL,_VAL_,16,0x0000ffff)
+#define SET_D2_DMA_INT_MASK(_VAL_) SET_REG(ADR_D2_DMA_INT,_VAL_,0,0xfffffffe)
+#define SET_D2_DMA_STS(_VAL_) SET_REG(ADR_D2_DMA_INT,_VAL_,8,0xfffffeff)
+#define SET_D2_DMA_FINISH(_VAL_) SET_REG(ADR_D2_DMA_INT,_VAL_,31,0x7fffffff)
+#define SET_D2_DMA_CONST(_VAL_) SET_REG(ADR_D2_DMA_FILL_CONST,_VAL_,0,0x00000000)
+#define SET_MASK_TYPHOST_INT_MAP_02(_VAL_) SET_REG(ADR_MASK_TYPHOST_INT_MAP_02,_VAL_,0,0x00000000)
+#define SET_RAW_TYPHOST_INT_MAP_02(_VAL_) SET_REG(ADR_RAW_TYPHOST_INT_MAP_02,_VAL_,0,0x00000000)
+#define SET_POSTMASK_TYPHOST_INT_MAP_02(_VAL_) SET_REG(ADR_POSTMASK_TYPHOST_INT_MAP_02,_VAL_,0,0x00000000)
+#define SET_MASK_TYPHOST_INT_MAP_15(_VAL_) SET_REG(ADR_MASK_TYPHOST_INT_MAP_15,_VAL_,0,0x00000000)
+#define SET_RAW_TYPHOST_INT_MAP_15(_VAL_) SET_REG(ADR_RAW_TYPHOST_INT_MAP_15,_VAL_,0,0x00000000)
+#define SET_POSTMASK_TYPHOST_INT_MAP_15(_VAL_) SET_REG(ADR_POSTMASK_TYPHOST_INT_MAP_15,_VAL_,0,0x00000000)
+#define SET_MASK_TYPHOST_INT_MAP_31(_VAL_) SET_REG(ADR_MASK_TYPHOST_INT_MAP_31,_VAL_,0,0x00000000)
+#define SET_RAW_TYPHOST_INT_MAP_31(_VAL_) SET_REG(ADR_RAW_TYPHOST_INT_MAP_31,_VAL_,0,0x00000000)
+#define SET_POSTMASK_TYPHOST_INT_MAP_31(_VAL_) SET_REG(ADR_POSTMASK_TYPHOST_INT_MAP_31,_VAL_,0,0x00000000)
+#define SET_MASK_TYPHOST_INT_MAP(_VAL_) SET_REG(ADR_MASK_TYPHOST_INT_MAP,_VAL_,0,0x00000000)
+#define SET_RAW_TYPHOST_INT_MAP(_VAL_) SET_REG(ADR_RAW_TYPHOST_INT_MAP,_VAL_,0,0x00000000)
+#define SET_POSTMASK_TYPHOST_INT_MAP(_VAL_) SET_REG(ADR_POSTMASK_TYPHOST_INT_MAP,_VAL_,0,0x00000000)
+#define SET_SUMMARY_TYPHOST_INT_MAP(_VAL_) SET_REG(ADR_SUMMARY_TYPHOST_INT_MAP,_VAL_,0,0xfffffffe)
+#define SET_MASK_TYPMCU_INT_MAP_02(_VAL_) SET_REG(ADR_MASK_TYPMCU_INT_MAP_02,_VAL_,0,0x00000000)
+#define SET_RAW_TYPMCU_INT_MAP_02(_VAL_) SET_REG(ADR_RAW_TYPMCU_INT_MAP_02,_VAL_,0,0x00000000)
+#define SET_POSTMASK_TYPMCU_INT_MAP_02(_VAL_) SET_REG(ADR_POSTMASK_TYPMCU_INT_MAP_02,_VAL_,0,0x00000000)
+#define SET_MASK_TYPMCU_INT_MAP_15(_VAL_) SET_REG(ADR_MASK_TYPMCU_INT_MAP_15,_VAL_,0,0x00000000)
+#define SET_RAW_TYPMCU_INT_MAP_15(_VAL_) SET_REG(ADR_RAW_TYPMCU_INT_MAP_15,_VAL_,0,0x00000000)
+#define SET_POSTMASK_TYPMCU_INT_MAP_15(_VAL_) SET_REG(ADR_POSTMASK_TYPMCU_INT_MAP_15,_VAL_,0,0x00000000)
+#define SET_MASK_TYPMCU_INT_MAP_31(_VAL_) SET_REG(ADR_MASK_TYPMCU_INT_MAP_31,_VAL_,0,0x00000000)
+#define SET_RAW_TYPMCU_INT_MAP_31(_VAL_) SET_REG(ADR_RAW_TYPMCU_INT_MAP_31,_VAL_,0,0x00000000)
+#define SET_POSTMASK_TYPMCU_INT_MAP_31(_VAL_) SET_REG(ADR_POSTMASK_TYPMCU_INT_MAP_31,_VAL_,0,0x00000000)
+#define SET_MASK_TYPMCU_INT_MAP(_VAL_) SET_REG(ADR_MASK_TYPMCU_INT_MAP,_VAL_,0,0x00000000)
+#define SET_RAW_TYPMCU_INT_MAP(_VAL_) SET_REG(ADR_RAW_TYPMCU_INT_MAP,_VAL_,0,0x00000000)
+#define SET_POSTMASK_TYPMCU_INT_MAP(_VAL_) SET_REG(ADR_POSTMASK_TYPMCU_INT_MAP,_VAL_,0,0x00000000)
+#define SET_SUMMARY_TYPMCU_INT_MAP(_VAL_) SET_REG(ADR_SUMMARY_TYPMCU_INT_MAP,_VAL_,0,0xfffffffe)
+#define SET_INT_GPI_SUB_00(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_BANK_00_TO_07,_VAL_,0,0xfffffff0)
+#define SET_INT_GPI_SUB_01(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_BANK_00_TO_07,_VAL_,4,0xffffff0f)
+#define SET_INT_GPI_SUB_02(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_BANK_00_TO_07,_VAL_,8,0xfffff0ff)
+#define SET_INT_GPI_SUB_03(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_BANK_00_TO_07,_VAL_,12,0xffff0fff)
+#define SET_INT_GPI_SUB_04(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_BANK_00_TO_07,_VAL_,16,0xfff0ffff)
+#define SET_INT_GPI_SUB_05(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_BANK_00_TO_07,_VAL_,20,0xff0fffff)
+#define SET_INT_GPI_SUB_06(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_BANK_00_TO_07,_VAL_,24,0xf0ffffff)
+#define SET_INT_GPI_SUB_07(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_BANK_00_TO_07,_VAL_,28,0x0fffffff)
+#define SET_INT_GPI_SUB_08(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_BANK_08_TO_15,_VAL_,0,0xfffffff0)
+#define SET_INT_GPI_SUB_09(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_BANK_08_TO_15,_VAL_,4,0xffffff0f)
+#define SET_INT_GPI_SUB_10(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_BANK_08_TO_15,_VAL_,8,0xfffff0ff)
+#define SET_INT_GPI_SUB_11(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_BANK_08_TO_15,_VAL_,12,0xffff0fff)
+#define SET_INT_GPI_SUB_12(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_BANK_08_TO_15,_VAL_,16,0xfff0ffff)
+#define SET_INT_GPI_SUB_13(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_BANK_08_TO_15,_VAL_,20,0xff0fffff)
+#define SET_INT_GPI_SUB_14(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_BANK_08_TO_15,_VAL_,24,0xf0ffffff)
+#define SET_INT_GPI_SUB_15(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_BANK_08_TO_15,_VAL_,28,0x0fffffff)
+#define SET_INT_GPI_SUB_16(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_BANK_16_TO_22,_VAL_,0,0xfffffff0)
+#define SET_INT_GPI_SUB_17(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_BANK_16_TO_22,_VAL_,4,0xffffff0f)
+#define SET_INT_GPI_SUB_18(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_BANK_16_TO_22,_VAL_,8,0xfffff0ff)
+#define SET_INT_GPI_SUB_19(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_BANK_16_TO_22,_VAL_,12,0xffff0fff)
+#define SET_INT_GPI_SUB_20(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_BANK_16_TO_22,_VAL_,16,0xfff0ffff)
+#define SET_INT_GPI_SUB_21(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_BANK_16_TO_22,_VAL_,20,0xff0fffff)
+#define SET_INT_GPI_SUB_22(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_BANK_16_TO_22,_VAL_,24,0xf0ffffff)
+#define SET_INT_GPI_MODE_00(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_00_TO_07,_VAL_,0,0xfffffff8)
+#define SET_INT_GPI_MODE_01(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_00_TO_07,_VAL_,4,0xffffff8f)
+#define SET_INT_GPI_MODE_02(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_00_TO_07,_VAL_,8,0xfffff8ff)
+#define SET_INT_GPI_MODE_03(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_00_TO_07,_VAL_,12,0xffff8fff)
+#define SET_INT_GPI_MODE_04(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_00_TO_07,_VAL_,16,0xfff8ffff)
+#define SET_INT_GPI_MODE_05(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_00_TO_07,_VAL_,20,0xff8fffff)
+#define SET_INT_GPI_MODE_06(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_00_TO_07,_VAL_,24,0xf8ffffff)
+#define SET_INT_GPI_MODE_07(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_00_TO_07,_VAL_,28,0x8fffffff)
+#define SET_INT_GPI_MODE_08(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_08_TO_15,_VAL_,0,0xfffffff8)
+#define SET_INT_GPI_MODE_09(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_08_TO_15,_VAL_,4,0xffffff8f)
+#define SET_INT_GPI_MODE_10(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_08_TO_15,_VAL_,8,0xfffff8ff)
+#define SET_INT_GPI_MODE_11(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_08_TO_15,_VAL_,12,0xffff8fff)
+#define SET_INT_GPI_MODE_12(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_08_TO_15,_VAL_,16,0xfff8ffff)
+#define SET_INT_GPI_MODE_13(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_08_TO_15,_VAL_,20,0xff8fffff)
+#define SET_INT_GPI_MODE_14(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_08_TO_15,_VAL_,24,0xf8ffffff)
+#define SET_INT_GPI_MODE_15(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_08_TO_15,_VAL_,28,0x8fffffff)
+#define SET_INT_GPI_MODE_16(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_16_TO_22,_VAL_,0,0xfffffff8)
+#define SET_INT_GPI_MODE_17(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_16_TO_22,_VAL_,4,0xffffff8f)
+#define SET_INT_GPI_MODE_18(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_16_TO_22,_VAL_,8,0xfffff8ff)
+#define SET_INT_GPI_MODE_19(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_16_TO_22,_VAL_,12,0xffff8fff)
+#define SET_INT_GPI_MODE_20(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_16_TO_22,_VAL_,16,0xfff8ffff)
+#define SET_INT_GPI_MODE_21(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_16_TO_22,_VAL_,20,0xff8fffff)
+#define SET_INT_GPI_MODE_22(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_16_TO_22,_VAL_,24,0xf8ffffff)
+#define SET_GPO_INT_POL(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_16_TO_22,_VAL_,31,0x7fffffff)
+#define SET_INT_IPC_RAW(_VAL_) SET_REG(ADR_IPC_INTERRUPT,_VAL_,0,0x00000000)
+#define SET_INT_WIFI_PHY(_VAL_) SET_REG(ADR_CLR_INT_STS2,_VAL_,23,0xff7fffff)
+#define SET_INT_UART_DBG_RX_TOUT(_VAL_) SET_REG(ADR_CLR_INT_STS2,_VAL_,26,0xfbffffff)
+#define SET_INT_UART_DATA_RX_TOUT(_VAL_) SET_REG(ADR_CLR_INT_STS2,_VAL_,30,0xbfffffff)
+#define SET_INT_ALC_TIMEOUT(_VAL_) SET_REG(ADR_CLR_INT_STS1,_VAL_,8,0xfffffeff)
+#define SET_INT_REQ_LOCK(_VAL_) SET_REG(ADR_CLR_INT_STS1,_VAL_,9,0xfffffdff)
+#define SET_INT_TX_LIMIT(_VAL_) SET_REG(ADR_CLR_INT_STS1,_VAL_,10,0xfffffbff)
+#define SET_INT_ID_THOLD_RX(_VAL_) SET_REG(ADR_CLR_INT_STS1,_VAL_,11,0xfffff7ff)
+#define SET_INT_ID_THOLD_TX(_VAL_) SET_REG(ADR_CLR_INT_STS1,_VAL_,12,0xffffefff)
+#define SET_INT_ID_DOUBLE_RLS(_VAL_) SET_REG(ADR_CLR_INT_STS1,_VAL_,13,0xffffdfff)
+#define SET_INT_RX_ID_LEN_THOLD(_VAL_) SET_REG(ADR_CLR_INT_STS1,_VAL_,14,0xffffbfff)
+#define SET_INT_TX_ID_LEN_THOLD(_VAL_) SET_REG(ADR_CLR_INT_STS1,_VAL_,15,0xffff7fff)
+#define SET_INT_ALL_ID_LEN_THOLD(_VAL_) SET_REG(ADR_CLR_INT_STS1,_VAL_,16,0xfffeffff)
+#define SET_INT_TRASH_CAN(_VAL_) SET_REG(ADR_CLR_INT_STS1,_VAL_,17,0xfffdffff)
+#define SET_INT_MB_LOWTHOLD(_VAL_) SET_REG(ADR_CLR_INT_STS1,_VAL_,18,0xfffbffff)
+#define SET_INT_EDCA0_LOWTHOLD(_VAL_) SET_REG(ADR_CLR_INT_STS1,_VAL_,20,0xffefffff)
+#define SET_INT_EDCA1_LOWTHOLD(_VAL_) SET_REG(ADR_CLR_INT_STS1,_VAL_,21,0xffdfffff)
+#define SET_INT_EDCA2_LOWTHOLD(_VAL_) SET_REG(ADR_CLR_INT_STS1,_VAL_,22,0xffbfffff)
+#define SET_INT_EDCA3_LOWTHOLD(_VAL_) SET_REG(ADR_CLR_INT_STS1,_VAL_,23,0xff7fffff)
+#define SET_INT_SDIO_WAKE(_VAL_) SET_REG(ADR_CLR_INT_STS0,_VAL_,2,0xfffffffb)
+#define SET_INT_SPI_M_DONE(_VAL_) SET_REG(ADR_CLR_INT_STS0,_VAL_,3,0xfffffff7)
+#define SET_INT_FLASH_DMA_DONE(_VAL_) SET_REG(ADR_CLR_INT_STS0,_VAL_,6,0xffffffbf)
+#define SET_INT_FBUSDMAC_INT_COMBINED(_VAL_) SET_REG(ADR_CLR_INT_STS0,_VAL_,9,0xfffffdff)
+#define SET_INT_DMAC_INT_COMBINED(_VAL_) SET_REG(ADR_CLR_INT_STS0,_VAL_,10,0xfffffbff)
+#define SET_INT_I2S(_VAL_) SET_REG(ADR_CLR_INT_STS0,_VAL_,16,0xfffeffff)
+#define SET_INT_CPU_ALT(_VAL_) SET_REG(ADR_CLR_INT_STS0,_VAL_,18,0xfffbffff)
+#define SET_INT_CPU(_VAL_) SET_REG(ADR_CLR_INT_STS0,_VAL_,19,0xfff7ffff)
+#define SET_INT_US_TIMER_0(_VAL_) SET_REG(ADR_CLR_INT_STS0,_VAL_,20,0xffefffff)
+#define SET_INT_US_TIMER_1(_VAL_) SET_REG(ADR_CLR_INT_STS0,_VAL_,21,0xffdfffff)
+#define SET_INT_US_TIMER_2(_VAL_) SET_REG(ADR_CLR_INT_STS0,_VAL_,22,0xffbfffff)
+#define SET_INT_US_TIMER_3(_VAL_) SET_REG(ADR_CLR_INT_STS0,_VAL_,23,0xff7fffff)
+#define SET_INT_MS_TIMER_0(_VAL_) SET_REG(ADR_CLR_INT_STS0,_VAL_,24,0xfeffffff)
+#define SET_INT_MS_TIMER_1(_VAL_) SET_REG(ADR_CLR_INT_STS0,_VAL_,25,0xfdffffff)
+#define SET_INT_MS_TIMER_2(_VAL_) SET_REG(ADR_CLR_INT_STS0,_VAL_,26,0xfbffffff)
+#define SET_INT_MS_TIMER_3(_VAL_) SET_REG(ADR_CLR_INT_STS0,_VAL_,27,0xf7ffffff)
+#define SET_INT_I2CMST(_VAL_) SET_REG(ADR_CLR_INT_STS0,_VAL_,28,0xefffffff)
+#define SET_INT_HCI(_VAL_) SET_REG(ADR_CLR_INT_STS0,_VAL_,29,0xdfffffff)
+#define SET_INT_CO_DMA(_VAL_) SET_REG(ADR_CLR_INT_STS0,_VAL_,30,0xbfffffff)
+#define SET_PATCH02_EN(_VAL_) SET_REG(ADR_ROM_PATCH02_0,_VAL_,0,0xfffffffe)
+#define SET_PATCH02_ADDR(_VAL_) SET_REG(ADR_ROM_PATCH02_0,_VAL_,2,0xfffe0003)
+#define SET_PATCH02_DATA(_VAL_) SET_REG(ADR_ROM_PATCH02_1,_VAL_,0,0x00000000)
+#define SET_PATCH03_EN(_VAL_) SET_REG(ADR_ROM_PATCH03_0,_VAL_,0,0xfffffffe)
+#define SET_PATCH03_ADDR(_VAL_) SET_REG(ADR_ROM_PATCH03_0,_VAL_,2,0xfffe0003)
+#define SET_PATCH03_DATA(_VAL_) SET_REG(ADR_ROM_PATCH03_1,_VAL_,0,0x00000000)
+#define SET_PATCH04_EN(_VAL_) SET_REG(ADR_ROM_PATCH04_0,_VAL_,0,0xfffffffe)
+#define SET_PATCH04_ADDR(_VAL_) SET_REG(ADR_ROM_PATCH04_0,_VAL_,2,0xfffe0003)
+#define SET_PATCH04_DATA(_VAL_) SET_REG(ADR_ROM_PATCH04_1,_VAL_,0,0x00000000)
+#define SET_PATCH05_EN(_VAL_) SET_REG(ADR_ROM_PATCH05_0,_VAL_,0,0xfffffffe)
+#define SET_PATCH05_ADDR(_VAL_) SET_REG(ADR_ROM_PATCH05_0,_VAL_,2,0xfffe0003)
+#define SET_PATCH05_DATA(_VAL_) SET_REG(ADR_ROM_PATCH05_1,_VAL_,0,0x00000000)
+#define SET_PATCH06_EN(_VAL_) SET_REG(ADR_ROM_PATCH06_0,_VAL_,0,0xfffffffe)
+#define SET_PATCH06_ADDR(_VAL_) SET_REG(ADR_ROM_PATCH06_0,_VAL_,2,0xfffe0003)
+#define SET_PATCH06_DATA(_VAL_) SET_REG(ADR_ROM_PATCH06_1,_VAL_,0,0x00000000)
+#define SET_PATCH07_EN(_VAL_) SET_REG(ADR_ROM_PATCH07_0,_VAL_,0,0xfffffffe)
+#define SET_PATCH07_ADDR(_VAL_) SET_REG(ADR_ROM_PATCH07_0,_VAL_,2,0xfffe0003)
+#define SET_PATCH07_DATA(_VAL_) SET_REG(ADR_ROM_PATCH07_1,_VAL_,0,0x00000000)
+#define SET_PATCH08_EN(_VAL_) SET_REG(ADR_ROM_PATCH08_0,_VAL_,0,0xfffffffe)
+#define SET_PATCH08_ADDR(_VAL_) SET_REG(ADR_ROM_PATCH08_0,_VAL_,2,0xfffe0003)
+#define SET_PATCH08_DATA(_VAL_) SET_REG(ADR_ROM_PATCH08_1,_VAL_,0,0x00000000)
+#define SET_PATCH09_EN(_VAL_) SET_REG(ADR_ROM_PATCH09_0,_VAL_,0,0xfffffffe)
+#define SET_PATCH09_ADDR(_VAL_) SET_REG(ADR_ROM_PATCH09_0,_VAL_,2,0xfffe0003)
+#define SET_PATCH09_DATA(_VAL_) SET_REG(ADR_ROM_PATCH09_1,_VAL_,0,0x00000000)
+#define SET_PATCH10_EN(_VAL_) SET_REG(ADR_ROM_PATCH10_0,_VAL_,0,0xfffffffe)
+#define SET_PATCH10_ADDR(_VAL_) SET_REG(ADR_ROM_PATCH10_0,_VAL_,2,0xfffe0003)
+#define SET_PATCH10_DATA(_VAL_) SET_REG(ADR_ROM_PATCH10_1,_VAL_,0,0x00000000)
+#define SET_PATCH11_EN(_VAL_) SET_REG(ADR_ROM_PATCH11_0,_VAL_,0,0xfffffffe)
+#define SET_PATCH11_ADDR(_VAL_) SET_REG(ADR_ROM_PATCH11_0,_VAL_,2,0xfffe0003)
+#define SET_PATCH11_DATA(_VAL_) SET_REG(ADR_ROM_PATCH11_1,_VAL_,0,0x00000000)
+#define SET_PATCH12_EN(_VAL_) SET_REG(ADR_ROM_PATCH12_0,_VAL_,0,0xfffffffe)
+#define SET_PATCH12_ADDR(_VAL_) SET_REG(ADR_ROM_PATCH12_0,_VAL_,2,0xfffe0003)
+#define SET_PATCH12_DATA(_VAL_) SET_REG(ADR_ROM_PATCH12_1,_VAL_,0,0x00000000)
+#define SET_PATCH13_EN(_VAL_) SET_REG(ADR_ROM_PATCH13_0,_VAL_,0,0xfffffffe)
+#define SET_PATCH13_ADDR(_VAL_) SET_REG(ADR_ROM_PATCH13_0,_VAL_,2,0xfffe0003)
+#define SET_PATCH13_DATA(_VAL_) SET_REG(ADR_ROM_PATCH13_1,_VAL_,0,0x00000000)
+#define SET_PATCH14_EN(_VAL_) SET_REG(ADR_ROM_PATCH14_0,_VAL_,0,0xfffffffe)
+#define SET_PATCH14_ADDR(_VAL_) SET_REG(ADR_ROM_PATCH14_0,_VAL_,2,0xfffe0003)
+#define SET_PATCH14_DATA(_VAL_) SET_REG(ADR_ROM_PATCH14_1,_VAL_,0,0x00000000)
+#define SET_PATCH15_EN(_VAL_) SET_REG(ADR_ROM_PATCH15_0,_VAL_,0,0xfffffffe)
+#define SET_PATCH15_ADDR(_VAL_) SET_REG(ADR_ROM_PATCH15_0,_VAL_,2,0xfffe0003)
+#define SET_PATCH15_DATA(_VAL_) SET_REG(ADR_ROM_PATCH15_1,_VAL_,0,0x00000000)
+#define SET_INT_BROWNOUT_LOWBATTERY(_VAL_) SET_REG(ADR_BROWNOUT_INT,_VAL_,0,0xfffffffe)
+#define SET_LOWBATTERY_SAMPLE_MIN_COUNT(_VAL_) SET_REG(ADR_BROWNOUT_SETUP,_VAL_,0,0xfffffff0)
+#define SET_TX_ON_DEMAND_ENA(_VAL_) SET_REG(ADR_CONTROL,_VAL_,1,0xfffffffd)
+#define SET_RX_2_HOST(_VAL_) SET_REG(ADR_CONTROL,_VAL_,2,0xfffffffb)
+#define SET_AUTO_SEQNO(_VAL_) SET_REG(ADR_CONTROL,_VAL_,3,0xfffffff7)
+#define SET_BYPASS_TX_PARSER_ENCAP(_VAL_) SET_REG(ADR_CONTROL,_VAL_,4,0xffffffef)
+#define SET_HDR_STRIP(_VAL_) SET_REG(ADR_CONTROL,_VAL_,5,0xffffffdf)
+#define SET_ERP_PROTECT(_VAL_) SET_REG(ADR_CONTROL,_VAL_,6,0xffffff3f)
+#define SET_PRO_VER(_VAL_) SET_REG(ADR_CONTROL,_VAL_,8,0xfffffcff)
+#define SET_TXQ_ID0(_VAL_) SET_REG(ADR_CONTROL,_VAL_,12,0xffff8fff)
+#define SET_TXQ_ID1(_VAL_) SET_REG(ADR_CONTROL,_VAL_,16,0xfff8ffff)
+#define SET_TX_ETHER_TRAP_EN(_VAL_) SET_REG(ADR_CONTROL,_VAL_,20,0xffefffff)
+#define SET_RX_ETHER_TRAP_EN(_VAL_) SET_REG(ADR_CONTROL,_VAL_,21,0xffdfffff)
+#define SET_RX_NULL_TRAP_EN(_VAL_) SET_REG(ADR_CONTROL,_VAL_,22,0xffbfffff)
+#define SET_TRX_DEBUG_CNT_ENA(_VAL_) SET_REG(ADR_CONTROL,_VAL_,28,0xefffffff)
+#define SET_HCI_TX_AGG_EN(_VAL_) SET_REG(ADR_HCI_TRX_MODE,_VAL_,0,0xfffffffe)
+#define SET_HCI_RX_EN(_VAL_) SET_REG(ADR_HCI_TRX_MODE,_VAL_,1,0xfffffffd)
+#define SET_HCI_RX_FORM_1(_VAL_) SET_REG(ADR_HCI_TRX_MODE,_VAL_,30,0xbfffffff)
+#define SET_HCI_RX_FORM_0(_VAL_) SET_REG(ADR_HCI_TRX_MODE,_VAL_,31,0x7fffffff)
+#define SET_TX_FLOW_CTRL(_VAL_) SET_REG(ADR_TX_FLOW_0,_VAL_,0,0xffff0000)
+#define SET_TX_FLOW_MGMT(_VAL_) SET_REG(ADR_TX_FLOW_0,_VAL_,16,0x0000ffff)
+#define SET_TX_FLOW_DATA(_VAL_) SET_REG(ADR_TX_FLOW_1,_VAL_,0,0x00000000)
+#define SET_SD_RX_LEN(_VAL_) SET_REG(ADR_REMAINING_RX_PACKET_LENGTH,_VAL_,0,0xffff0000)
+#define SET_RX_ACCU_LEN(_VAL_) SET_REG(ADR_RX_PACKET_LENGTH_STATUS,_VAL_,0,0xffff0000)
+#define SET_HCI_RX_LEN(_VAL_) SET_REG(ADR_RX_PACKET_LENGTH_STATUS,_VAL_,16,0x0000ffff)
+#define SET_DOT11RTSTHRESHOLD(_VAL_) SET_REG(ADR_THRESHOLD,_VAL_,16,0x0000ffff)
+#define SET_TX_ERR_RECOVER(_VAL_) SET_REG(ADR_TX_ERROR_RECEOVERY,_VAL_,0,0xfffffffe)
+#define SET_TX_ERR_FIRST_4B_EN(_VAL_) SET_REG(ADR_TX_ERROR_RECEOVERY,_VAL_,1,0xfffffffd)
+#define SET_RX_INT_TIMEOUT(_VAL_) SET_REG(ADR_TX_ERROR_RECEOVERY,_VAL_,16,0x0000ffff)
+#define SET_TXF_ID(_VAL_) SET_REG(ADR_TXFID_INCREASE,_VAL_,0,0xffffffc0)
+#define SET_SEQ_CTRL(_VAL_) SET_REG(ADR_GLOBAL_SEQUENCE,_VAL_,0,0xffff0000)
+#define SET_DBG_ADDR_EN(_VAL_) SET_REG(ADR_HCI_REG_0X2C,_VAL_,0,0xfffffffe)
+#define SET_DBG_ADDR_FENCE(_VAL_) SET_REG(ADR_HCI_REG_0X2C,_VAL_,8,0xffff00ff)
+#define SET_TX_PBOFFSET(_VAL_) SET_REG(ADR_HCI_TX_RX_INFO_SIZE,_VAL_,0,0xffffff00)
+#define SET_TX_INFO_SIZE(_VAL_) SET_REG(ADR_HCI_TX_RX_INFO_SIZE,_VAL_,8,0xffff00ff)
+#define SET_RX_INFO_SIZE(_VAL_) SET_REG(ADR_HCI_TX_RX_INFO_SIZE,_VAL_,16,0xff00ffff)
+#define SET_RX_LAST_PHY_SIZE(_VAL_) SET_REG(ADR_HCI_TX_RX_INFO_SIZE,_VAL_,24,0x00ffffff)
+#define SET_TX_INFO_CLEAR_SIZE(_VAL_) SET_REG(ADR_HCI_TX_INFO_CLEAR,_VAL_,0,0xffffffc0)
+#define SET_TX_INFO_CLEAR_ENABLE(_VAL_) SET_REG(ADR_HCI_TX_INFO_CLEAR,_VAL_,8,0xfffffeff)
+#define SET_RX_PER_RD_LEN(_VAL_) SET_REG(ADR_HCI_TO_PKTBUF_SETTING,_VAL_,0,0xffffffc0)
+#define SET_BACKUP_PG_CNT(_VAL_) SET_REG(ADR_HCI_TO_PKTBUF_SETTING,_VAL_,8,0xfffff0ff)
+#define SET_MANUAL_HCI_ALLOC_EN(_VAL_) SET_REG(ADR_HCI_MANUAL_ALLOC,_VAL_,0,0xfffffffe)
+#define SET_MANUAL_HCI_ALLOC_SIZE(_VAL_) SET_REG(ADR_HCI_MANUAL_ALLOC_ACTION,_VAL_,0,0xffff0000)
+#define SET_MANUAL_ALLOC_ID(_VAL_) SET_REG(ADR_HCI_MANUAL_ALLOC_STATUS,_VAL_,0,0xffffff80)
+#define SET_HAS_MANUAL_BUF(_VAL_) SET_REG(ADR_HCI_MANUAL_ALLOC_STATUS,_VAL_,7,0xffffff7f)
+#define SET_DOUBLE_ALLOC_ERR(_VAL_) SET_REG(ADR_HCI_MANUAL_ALLOC_STATUS,_VAL_,8,0xfffffeff)
+#define SET_NO_ALLOC_ERR(_VAL_) SET_REG(ADR_HCI_MANUAL_ALLOC_STATUS,_VAL_,9,0xfffffdff)
+#define SET_TXTRAP_ETHTYPE1(_VAL_) SET_REG(ADR_TX_ETHER_TYPE_1,_VAL_,0,0xffff0000)
+#define SET_TXTRAP_ETHTYPE0(_VAL_) SET_REG(ADR_TX_ETHER_TYPE_1,_VAL_,16,0x0000ffff)
+#define SET_RXTRAP_ETHTYPE1(_VAL_) SET_REG(ADR_RX_ETHER_TYPE_1,_VAL_,0,0xffff0000)
+#define SET_RXTRAP_ETHTYPE0(_VAL_) SET_REG(ADR_RX_ETHER_TYPE_1,_VAL_,16,0x0000ffff)
+#define SET_TX_PKT_SEND_LEN(_VAL_) SET_REG(ADR_TX_PACKET_LENGTH,_VAL_,0,0xffff0000)
+#define SET_TX_SDIO_PKT_LEN(_VAL_) SET_REG(ADR_TX_PACKET_LENGTH,_VAL_,16,0x0000ffff)
+#define SET_TX_PKT_SEND_ID(_VAL_) SET_REG(ADR_TX_PACKET_ID,_VAL_,0,0xffffff80)
+#define SET_HCI_PENDING_RX_MPDU_CNT(_VAL_) SET_REG(ADR_RX_RESCUE_HELPER,_VAL_,0,0xffffffe0)
+#define SET_HCI_RX_HALT(_VAL_) SET_REG(ADR_RX_RESCUE_HELPER,_VAL_,8,0xfffffeff)
+#define SET_HIF_LOOP_BACK(_VAL_) SET_REG(ADR_RX_RESCUE_HELPER,_VAL_,9,0xfffffdff)
+#define SET_USB_BULK_IN_LEN_INIT(_VAL_) SET_REG(ADR_RX_RESCUE_HELPER,_VAL_,30,0xbfffffff)
+#define SET_HCI_RX_MPDU_DEQUE(_VAL_) SET_REG(ADR_RX_RESCUE_HELPER,_VAL_,31,0x7fffffff)
+#define SET_HCI_BULK_IN_HOST_SIZE(_VAL_) SET_REG(ADR_HCI_FORCE_PRE_BULK_IN,_VAL_,0,0xfffe0000)
+#define SET_HCI_BULK_IN_TIME_OUT(_VAL_) SET_REG(ADR_HCI_BULK_IN_TIME_OUT_VALUE,_VAL_,0,0x00000000)
+#define SET_HCI_MONITOR_REG0(_VAL_) SET_REG(ADR_HCI_STATE_DEBUG_MODE_0,_VAL_,0,0x00000000)
+#define SET_HCI_MONITOR_REG2(_VAL_) SET_REG(ADR_HCI_STATE_DEBUG_MODE_2,_VAL_,0,0x00000000)
+#define SET_HCI_MONITOR_REG3(_VAL_) SET_REG(ADR_HCI_STATE_DEBUG_MODE_3,_VAL_,0,0x00000000)
+#define SET_HCI_MONITOR_REG4(_VAL_) SET_REG(ADR_HCI_STATE_DEBUG_MODE_4,_VAL_,0,0x00000000)
+#define SET_HCI_MONITOR_REG5(_VAL_) SET_REG(ADR_HCI_STATE_DEBUG_MODE_5,_VAL_,0,0x00000000)
+#define SET_SDIO_TX_INVALID_CNT(_VAL_) SET_REG(ADR_HCI_STATE_DEBUG_MODE_6,_VAL_,0,0x00000000)
+#define SET_HCI_MB_MAX_CNT(_VAL_) SET_REG(ADR_HCI_STATE_DEBUG_MODE_7,_VAL_,0,0xffffff00)
+#define SET_HCI_PROC_CNT(_VAL_) SET_REG(ADR_HCI_STATE_DEBUG_MODE_7,_VAL_,8,0xffff00ff)
+#define SET_SDIO_TRANS_CNT(_VAL_) SET_REG(ADR_HCI_STATE_DEBUG_MODE_7,_VAL_,16,0xff00ffff)
+#define SET_TX_ON_DEMAND_LENGTH(_VAL_) SET_REG(ADR_HCI_TX_ON_DEMAND_LENGTH,_VAL_,0,0x00000000)
+#define SET_HCI_TX_ALLOC_CNT(_VAL_) SET_REG(ADR_HCI_TX_ALLOC_SUCCESS_COUNT,_VAL_,0,0x00000000)
+#define SET_HCI_TX_ALLOC_TIME(_VAL_) SET_REG(ADR_HCI_TX_ALLOC_SPENDING_TIME,_VAL_,0,0x00000000)
+#define SET_RX_PKT_TRAP_COUNTER(_VAL_) SET_REG(ADR_RX_TRAP_COUNT,_VAL_,0,0x00000000)
+#define SET_TX_PKT_TRAP_COUNTER(_VAL_) SET_REG(ADR_TX_TRAP_COUNT,_VAL_,0,0x00000000)
+#define SET_RX_PKT_DROP_COUNTER(_VAL_) SET_REG(ADR_RX_DROP_COUNT,_VAL_,0,0x00000000)
+#define SET_TX_PKT_DROP_COUNTER(_VAL_) SET_REG(ADR_TX_DROP_COUNT,_VAL_,0,0x00000000)
+#define SET_HOST_EVENT_COUNTER(_VAL_) SET_REG(ADR_RX_HOST_EVENT_COUNT,_VAL_,0,0x00000000)
+#define SET_HOST_CMD_COUNTER(_VAL_) SET_REG(ADR_TX_HOST_COMMAND_COUNT,_VAL_,0,0x00000000)
+#define SET_RX_PKT_COUNTER(_VAL_) SET_REG(ADR_RX_PACKET_COUNTER,_VAL_,0,0x00000000)
+#define SET_TX_PKT_COUNTER(_VAL_) SET_REG(ADR_TX_PACKET_COUNTER,_VAL_,0,0x00000000)
+#define SET_HOST_RX_FAIL_COUNTER(_VAL_) SET_REG(ADR_SDIO_RX_FAIL_COUNT,_VAL_,0,0x00000000)
+#define SET_HOST_TX_FAIL_COUNTER(_VAL_) SET_REG(ADR_SDIO_TX_FAIL_COUNT,_VAL_,0,0x00000000)
+#define SET_CORRECT_RATE_REP_LEN(_VAL_) SET_REG(ADR_CORRECT_RATE_REPORT_LENGTH,_VAL_,0,0xfffffffe)
+#define SET_TX_PKT_SEND_TO_RX(_VAL_) SET_REG(ADR_TX_PACKET_SEND_TO_RX_DIRECTLY,_VAL_,0,0xfffffffe)
+#define SET_PEERPS_REJECT_ENABLE(_VAL_) SET_REG(ADR_POWER_SAVING_PEER_REJECT_FUNCTION,_VAL_,0,0xfffffffe)
+#define SET_TRANS_FULL_PKT_AMPDU1P2(_VAL_) SET_REG(ADR_POWER_SAVING_PEER_REJECT_FUNCTION,_VAL_,4,0xffffffef)
+#define SET_TX_RX_TRAP_HW_ID_SELECT_ENABLE(_VAL_) SET_REG(ADR_TX_RX_TRAP_HW_ID_SELECTION_FUNCTION,_VAL_,0,0xfffffffe)
+#define SET_TX_TRAP_HW_ID(_VAL_) SET_REG(ADR_TX_RX_TRAP_HW_ID_SELECTION_FUNCTION,_VAL_,4,0xffffff0f)
+#define SET_RX_TRAP_HW_ID(_VAL_) SET_REG(ADR_TX_RX_TRAP_HW_ID_SELECTION_FUNCTION,_VAL_,8,0xfffff0ff)
+#define SET_RX_DEBUG_HCI_EXP_0(_VAL_) SET_REG(ADR_RX_HCI_EXP_0_CTRL,_VAL_,0,0xfffffffe)
+#define SET_RX_DEBUG_HCI_EXP_0_RND_MODE(_VAL_) SET_REG(ADR_RX_HCI_EXP_0_CTRL,_VAL_,4,0xffffffcf)
+#define SET_RX_DEBUG_HCI_EXP_0_LENGHT_LIMIT_MIN(_VAL_) SET_REG(ADR_RX_HCI_EXP_0_LEN,_VAL_,0,0xffff0000)
+#define SET_RX_DEBUG_HCI_EXP_0_LENGHT_LIMIT_MAX(_VAL_) SET_REG(ADR_RX_HCI_EXP_0_LEN,_VAL_,16,0x0000ffff)
+#define SET_RX_AGG_CNT(_VAL_) SET_REG(ADR_FORCE_RX_AGGREGATION_MODE,_VAL_,0,0xfffffff0)
+#define SET_RX_AGG_METHOD_3(_VAL_) SET_REG(ADR_FORCE_RX_AGGREGATION_MODE,_VAL_,7,0xffffff7f)
+#define SET_RX_AGG_TIMER_RELOAD_VALUE(_VAL_) SET_REG(ADR_FORCE_RX_AGGREGATION_MODE,_VAL_,16,0x0000ffff)
+#define SET_CS_START_ADDR(_VAL_) SET_REG(ADR_CS_START_ADDR,_VAL_,0,0xffff0000)
+#define SET_CS_PKT_ID(_VAL_) SET_REG(ADR_CS_START_ADDR,_VAL_,16,0xff80ffff)
+#define SET_ADD_LEN(_VAL_) SET_REG(ADR_CS_ADD_LEN,_VAL_,0,0xffff0000)
+#define SET_CS_ADDER_EN(_VAL_) SET_REG(ADR_CS_CMD,_VAL_,0,0xfffffffe)
+#define SET_PSEUDO(_VAL_) SET_REG(ADR_CS_CMD,_VAL_,1,0xfffffffd)
+#define SET_CALCULATE(_VAL_) SET_REG(ADR_CS_INI_BUF,_VAL_,0,0x00000000)
+#define SET_L4_LEN(_VAL_) SET_REG(ADR_CS_PSEUDO_BUF,_VAL_,0,0xffff0000)
+#define SET_L4_PROTOL(_VAL_) SET_REG(ADR_CS_PSEUDO_BUF,_VAL_,16,0xff00ffff)
+#define SET_CHECK_SUM(_VAL_) SET_REG(ADR_CS_CHECK_SUM,_VAL_,0,0xffff0000)
+#define SET_RAND_EN(_VAL_) SET_REG(ADR_RAND_EN,_VAL_,0,0xfffffffe)
+#define SET_RAND_NUM(_VAL_) SET_REG(ADR_RAND_NUM,_VAL_,0,0x00000000)
+#define SET_MUL_OP1(_VAL_) SET_REG(ADR_MUL_OP1,_VAL_,0,0x00000000)
+#define SET_MUL_OP2(_VAL_) SET_REG(ADR_MUL_OP2,_VAL_,0,0x00000000)
+#define SET_MUL_ANS0(_VAL_) SET_REG(ADR_MUL_ANS0,_VAL_,0,0x00000000)
+#define SET_MUL_ANS1(_VAL_) SET_REG(ADR_MUL_ANS1,_VAL_,0,0x00000000)
+#define SET_RD_ADDR(_VAL_) SET_REG(ADR_DMA_RDATA,_VAL_,0,0xffff0000)
+#define SET_RD_ID(_VAL_) SET_REG(ADR_DMA_RDATA,_VAL_,16,0xff80ffff)
+#define SET_WR_ADDR(_VAL_) SET_REG(ADR_DMA_WDATA,_VAL_,0,0xffff0000)
+#define SET_WR_ID(_VAL_) SET_REG(ADR_DMA_WDATA,_VAL_,16,0xff80ffff)
+#define SET_LEN(_VAL_) SET_REG(ADR_DMA_LEN,_VAL_,0,0xffff0000)
+#define SET_CLR(_VAL_) SET_REG(ADR_DMA_CLR,_VAL_,0,0xfffffffe)
+#define SET_PHY_MODE(_VAL_) SET_REG(ADR_NAV_DATA,_VAL_,0,0xfffffffc)
+#define SET_SHRT_PREAM(_VAL_) SET_REG(ADR_NAV_DATA,_VAL_,2,0xfffffffb)
+#define SET_SHRT_GI(_VAL_) SET_REG(ADR_NAV_DATA,_VAL_,3,0xfffffff7)
+#define SET_DATA_RATE(_VAL_) SET_REG(ADR_NAV_DATA,_VAL_,4,0xfffff80f)
+#define SET_MCS(_VAL_) SET_REG(ADR_NAV_DATA,_VAL_,12,0xffff8fff)
+#define SET_FRAME_LEN(_VAL_) SET_REG(ADR_NAV_DATA,_VAL_,16,0x0000ffff)
+#define SET_DURATION(_VAL_) SET_REG(ADR_CO_NAV,_VAL_,0,0xffff0000)
+#define SET_SHA_DST_ADDR(_VAL_) SET_REG(ADR_SHA_DST_ADDR,_VAL_,0,0x00000000)
+#define SET_SHA_SRC_ADDR(_VAL_) SET_REG(ADR_SHA_SRC_ADDR,_VAL_,0,0x00000000)
+#define SET_SHA_BUSY(_VAL_) SET_REG(ADR_SHA_SETTING,_VAL_,0,0xfffffffe)
+#define SET_SHA_ENDIAN(_VAL_) SET_REG(ADR_SHA_SETTING,_VAL_,1,0xfffffffd)
+#define SET_EFS_CLKFREQ(_VAL_) SET_REG(ADR_EFUSE_CLK_FREQ,_VAL_,0,0xfffff000)
+#define SET_EFS_VDDQ_EN_LOW_ACTIVE(_VAL_) SET_REG(ADR_EFUSE_CLK_FREQ,_VAL_,16,0xfffeffff)
+#define SET_EFS_CLKFREQ_RD(_VAL_) SET_REG(ADR_EFUSE_CLK_FREQ,_VAL_,20,0xf00fffff)
+#define SET_EFS_PRE_RD(_VAL_) SET_REG(ADR_EFUSE_CLK_FREQ,_VAL_,28,0x0fffffff)
+#define SET_EFS_LDO_ON(_VAL_) SET_REG(ADR_EFUSE_LDO_TIME,_VAL_,0,0xffff0000)
+#define SET_EFS_LDO_OFF(_VAL_) SET_REG(ADR_EFUSE_LDO_TIME,_VAL_,16,0x0000ffff)
+#define SET_EFS_RD_FLAG(_VAL_) SET_REG(ADR_EFUSE_STATUS,_VAL_,0,0xfffffffe)
+#define SET_EFS_PROGRESS_DONE(_VAL_) SET_REG(ADR_EFUSE_STATUS2,_VAL_,0,0xfffffffe)
+#define SET_EFS_WR_KICK(_VAL_) SET_REG(ADR_EFUSE_WR_KICK,_VAL_,0,0xfffffffe)
+#define SET_EFS_RD_KICK(_VAL_) SET_REG(ADR_EFUSE_RD_KICK,_VAL_,0,0xfffffffe)
+#define SET_EFS_VDDQ_EN(_VAL_) SET_REG(ADR_EFUSE_VDDQ_EN,_VAL_,0,0xfffffffe)
+#define SET_EFS_BYTE_0(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_0,_VAL_,0,0xffffff00)
+#define SET_EFS_BYTE_1(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_0,_VAL_,8,0xffff00ff)
+#define SET_EFS_BYTE_2(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_0,_VAL_,16,0xff00ffff)
+#define SET_EFS_BYTE_3(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_0,_VAL_,24,0x00ffffff)
+#define SET_EFS_BYTE_4(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_1,_VAL_,0,0xffffff00)
+#define SET_EFS_BYTE_5(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_1,_VAL_,8,0xffff00ff)
+#define SET_EFS_BYTE_6(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_1,_VAL_,16,0xff00ffff)
+#define SET_EFS_BYTE_7(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_1,_VAL_,24,0x00ffffff)
+#define SET_EFS_BYTE_8(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_2,_VAL_,0,0xffffff00)
+#define SET_EFS_BYTE_9(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_2,_VAL_,8,0xffff00ff)
+#define SET_EFS_BYTE_10(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_2,_VAL_,16,0xff00ffff)
+#define SET_EFS_BYTE_11(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_2,_VAL_,24,0x00ffffff)
+#define SET_EFS_BYTE_12(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_3,_VAL_,0,0xffffff00)
+#define SET_EFS_BYTE_13(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_3,_VAL_,8,0xffff00ff)
+#define SET_EFS_BYTE_14(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_3,_VAL_,16,0xff00ffff)
+#define SET_EFS_BYTE_15(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_3,_VAL_,24,0x00ffffff)
+#define SET_EFS_BYTE_16(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_4,_VAL_,0,0xffffff00)
+#define SET_EFS_BYTE_17(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_4,_VAL_,8,0xffff00ff)
+#define SET_EFS_BYTE_18(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_4,_VAL_,16,0xff00ffff)
+#define SET_EFS_BYTE_19(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_4,_VAL_,24,0x00ffffff)
+#define SET_EFS_BYTE_20(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_5,_VAL_,0,0xffffff00)
+#define SET_EFS_BYTE_21(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_5,_VAL_,8,0xffff00ff)
+#define SET_EFS_BYTE_22(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_5,_VAL_,16,0xff00ffff)
+#define SET_EFS_BYTE_23(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_5,_VAL_,24,0x00ffffff)
+#define SET_EFS_BYTE_24(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_6,_VAL_,0,0xffffff00)
+#define SET_EFS_BYTE_25(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_6,_VAL_,8,0xffff00ff)
+#define SET_EFS_BYTE_26(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_6,_VAL_,16,0xff00ffff)
+#define SET_EFS_BYTE_27(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_6,_VAL_,24,0x00ffffff)
+#define SET_EFS_BYTE_28(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_7,_VAL_,0,0xffffff00)
+#define SET_EFS_BYTE_29(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_7,_VAL_,8,0xffff00ff)
+#define SET_EFS_BYTE_30(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_7,_VAL_,16,0xff00ffff)
+#define SET_EFS_BYTE_31(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_7,_VAL_,24,0x00ffffff)
+#define SET_SPI_M_FRONT_DLY(_VAL_) SET_REG(ADR_SPI_DELAY,_VAL_,0,0xffff0000)
+#define SET_SPI_M_BACK_DLY(_VAL_) SET_REG(ADR_SPI_DELAY,_VAL_,16,0x0000ffff)
+#define SET_SPI_CLK_DIV(_VAL_) SET_REG(ADR_SPI_CLK_DIV,_VAL_,0,0xffff0000)
+#define SET_SPI_MASTER_BUSY(_VAL_) SET_REG(ADR_SPI_BUSY,_VAL_,0,0xfffffffe)
+#define SET_SPI_CLR(_VAL_) SET_REG(ADR_SPI_CLR,_VAL_,0,0xfffffffe)
+#define SET_CPOL(_VAL_) SET_REG(ADR_SPI_MAS_MODE,_VAL_,0,0xfffffffe)
+#define SET_CPHA(_VAL_) SET_REG(ADR_SPI_MAS_MODE,_VAL_,1,0xfffffffd)
+#define SET_CSPOL(_VAL_) SET_REG(ADR_SPI_M_CFG,_VAL_,0,0xfffffffe)
+#define SET_INV_DATA(_VAL_) SET_REG(ADR_SPI_M_CFG,_VAL_,1,0xfffffffd)
+#define SET_FAST_CLK(_VAL_) SET_REG(ADR_SPI_M_CFG,_VAL_,2,0xfffffffb)
+#define SET_AUTO_CSN(_VAL_) SET_REG(ADR_SPI_M_CFG,_VAL_,3,0xfffffff7)
+#define SET_THREE_WIRE(_VAL_) SET_REG(ADR_SPI_M_CFG,_VAL_,4,0xfffffc0f)
+#define SET_ENDIAN(_VAL_) SET_REG(ADR_SPI_M_CFG,_VAL_,10,0xfffffbff)
+#define SET_EARLY_SAMPLE(_VAL_) SET_REG(ADR_SPI_M_CFG,_VAL_,11,0xfffff7ff)
+#define SET_SPI_CSN(_VAL_) SET_REG(ADR_SPI_CFG,_VAL_,0,0xfffffffe)
+#define SET_CMD_LEN_SPIMAS(_VAL_) SET_REG(ADR_SPI_MAS_COMMAND_LEN,_VAL_,0,0xffff0000)
+#define SET_MRX_MCAST_TB0_31_0(_VAL_) SET_REG(ADR_MRX_MCAST_TB0_0,_VAL_,0,0x00000000)
+#define SET_MRX_MCAST_TB0_47_32(_VAL_) SET_REG(ADR_MRX_MCAST_TB0_1,_VAL_,0,0xffff0000)
+#define SET_MRX_MCAST_MASK0_31_0(_VAL_) SET_REG(ADR_MRX_MCAST_MK0_0,_VAL_,0,0x00000000)
+#define SET_MRX_MCAST_MASK0_47_32(_VAL_) SET_REG(ADR_MRX_MCAST_MK0_1,_VAL_,0,0xffff0000)
+#define SET_MRX_MCAST_CTRL_0(_VAL_) SET_REG(ADR_MRX_MCAST_CTRL0,_VAL_,0,0xfffffffc)
+#define SET_MRX_MCAST_TB1_31_0(_VAL_) SET_REG(ADR_MRX_MCAST_TB1_0,_VAL_,0,0x00000000)
+#define SET_MRX_MCAST_TB1_47_32(_VAL_) SET_REG(ADR_MRX_MCAST_TB1_1,_VAL_,0,0xffff0000)
+#define SET_MRX_MCAST_MASK1_31_0(_VAL_) SET_REG(ADR_MRX_MCAST_MK1_0,_VAL_,0,0x00000000)
+#define SET_MRX_MCAST_MASK1_47_32(_VAL_) SET_REG(ADR_MRX_MCAST_MK1_1,_VAL_,0,0xffff0000)
+#define SET_MRX_MCAST_CTRL_1(_VAL_) SET_REG(ADR_MRX_MCAST_CTRL1,_VAL_,0,0xfffffffc)
+#define SET_MRX_MCAST_TB2_31_0(_VAL_) SET_REG(ADR_MRX_MCAST_TB2_0,_VAL_,0,0x00000000)
+#define SET_MRX_MCAST_TB2_47_32(_VAL_) SET_REG(ADR_MRX_MCAST_TB2_1,_VAL_,0,0xffff0000)
+#define SET_MRX_MCAST_MASK2_31_0(_VAL_) SET_REG(ADR_MRX_MCAST_MK2_0,_VAL_,0,0x00000000)
+#define SET_MRX_MCAST_MASK2_47_32(_VAL_) SET_REG(ADR_MRX_MCAST_MK2_1,_VAL_,0,0xffff0000)
+#define SET_MRX_MCAST_CTRL_2(_VAL_) SET_REG(ADR_MRX_MCAST_CTRL2,_VAL_,0,0xfffffffc)
+#define SET_MRX_MCAST_TB3_31_0(_VAL_) SET_REG(ADR_MRX_MCAST_TB3_0,_VAL_,0,0x00000000)
+#define SET_MRX_MCAST_TB3_47_32(_VAL_) SET_REG(ADR_MRX_MCAST_TB3_1,_VAL_,0,0xffff0000)
+#define SET_MRX_MCAST_MASK3_31_0(_VAL_) SET_REG(ADR_MRX_MCAST_MK3_0,_VAL_,0,0x00000000)
+#define SET_MRX_MCAST_MASK3_47_32(_VAL_) SET_REG(ADR_MRX_MCAST_MK3_1,_VAL_,0,0xffff0000)
+#define SET_MRX_MCAST_CTRL_3(_VAL_) SET_REG(ADR_MRX_MCAST_CTRL3,_VAL_,0,0xfffffffc)
+#define SET_MRX_PHY_INFO(_VAL_) SET_REG(ADR_MRX_PHY_INFO,_VAL_,0,0x00000000)
+#define SET_DBG_BA_TYPE(_VAL_) SET_REG(ADR_MRX_BA_DBG,_VAL_,0,0xffffffc0)
+#define SET_DBG_BA_SEQ(_VAL_) SET_REG(ADR_MRX_BA_DBG,_VAL_,8,0xfff000ff)
+#define SET_MRX_FLT_TB0(_VAL_) SET_REG(ADR_MRX_FLT_TB0,_VAL_,0,0xffff8000)
+#define SET_MRX_FLT_TB1(_VAL_) SET_REG(ADR_MRX_FLT_TB1,_VAL_,0,0xffff8000)
+#define SET_MRX_FLT_TB2(_VAL_) SET_REG(ADR_MRX_FLT_TB2,_VAL_,0,0xffff8000)
+#define SET_MRX_FLT_TB3(_VAL_) SET_REG(ADR_MRX_FLT_TB3,_VAL_,0,0xffff8000)
+#define SET_MRX_FLT_TB4(_VAL_) SET_REG(ADR_MRX_FLT_TB4,_VAL_,0,0xffff8000)
+#define SET_MRX_FLT_TB5(_VAL_) SET_REG(ADR_MRX_FLT_TB5,_VAL_,0,0xffff8000)
+#define SET_MRX_FLT_TB6(_VAL_) SET_REG(ADR_MRX_FLT_TB6,_VAL_,0,0xffff8000)
+#define SET_MRX_FLT_TB7(_VAL_) SET_REG(ADR_MRX_FLT_TB7,_VAL_,0,0xffff8000)
+#define SET_MRX_FLT_TB8(_VAL_) SET_REG(ADR_MRX_FLT_TB8,_VAL_,0,0xffff8000)
+#define SET_MRX_FLT_TB9(_VAL_) SET_REG(ADR_MRX_FLT_TB9,_VAL_,0,0xffff8000)
+#define SET_MRX_FLT_TB10(_VAL_) SET_REG(ADR_MRX_FLT_TB10,_VAL_,0,0xffff8000)
+#define SET_MRX_FLT_TB11(_VAL_) SET_REG(ADR_MRX_FLT_TB11,_VAL_,0,0xffff8000)
+#define SET_MRX_FLT_TB12(_VAL_) SET_REG(ADR_MRX_FLT_TB12,_VAL_,0,0xffff8000)
+#define SET_MRX_FLT_TB13(_VAL_) SET_REG(ADR_MRX_FLT_TB13,_VAL_,0,0xffff8000)
+#define SET_MRX_FLT_TB14(_VAL_) SET_REG(ADR_MRX_FLT_TB14,_VAL_,0,0xffff8000)
+#define SET_MRX_FLT_TB15(_VAL_) SET_REG(ADR_MRX_FLT_TB15,_VAL_,0,0xffff8000)
+#define SET_MRX_FLT_EN0(_VAL_) SET_REG(ADR_MRX_FLT_EN0,_VAL_,0,0xffff0000)
+#define SET_MRX_FLT_EN1(_VAL_) SET_REG(ADR_MRX_FLT_EN1,_VAL_,0,0xffff0000)
+#define SET_MRX_FLT_EN2(_VAL_) SET_REG(ADR_MRX_FLT_EN2,_VAL_,0,0xffff0000)
+#define SET_MRX_FLT_EN3(_VAL_) SET_REG(ADR_MRX_FLT_EN3,_VAL_,0,0xffff0000)
+#define SET_MRX_FLT_EN4(_VAL_) SET_REG(ADR_MRX_FLT_EN4,_VAL_,0,0xffff0000)
+#define SET_MRX_FLT_EN5(_VAL_) SET_REG(ADR_MRX_FLT_EN5,_VAL_,0,0xffff0000)
+#define SET_MRX_FLT_EN6(_VAL_) SET_REG(ADR_MRX_FLT_EN6,_VAL_,0,0xffff0000)
+#define SET_MRX_FLT_EN7(_VAL_) SET_REG(ADR_MRX_FLT_EN7,_VAL_,0,0xffff0000)
+#define SET_MRX_FLT_EN8(_VAL_) SET_REG(ADR_MRX_FLT_EN8,_VAL_,0,0xffff0000)
+#define SET_MRX_LEN_FLT(_VAL_) SET_REG(ADR_MRX_LEN_FLT,_VAL_,0,0xffff0000)
+#define SET_RX_FLOW_DATA(_VAL_) SET_REG(ADR_RX_FLOW_DATA,_VAL_,0,0x00000000)
+#define SET_RX_FLOW_MNG(_VAL_) SET_REG(ADR_RX_FLOW_MNG,_VAL_,0,0xffff0000)
+#define SET_RX_FLOW_CTRL(_VAL_) SET_REG(ADR_RX_FLOW_CTRL,_VAL_,0,0xffff0000)
+#define SET_MRX_STP_EN(_VAL_) SET_REG(ADR_RX_TIME_STAMP_CFG,_VAL_,0,0xfffffffe)
+#define SET_MRX_STP_OFST(_VAL_) SET_REG(ADR_RX_TIME_STAMP_CFG,_VAL_,8,0xffff00ff)
+#define SET_DBG_FF_FULL(_VAL_) SET_REG(ADR_DBG_FF_FULL,_VAL_,0,0xffff0000)
+#define SET_DBG_FF_FULL_CLR(_VAL_) SET_REG(ADR_DBG_FF_FULL,_VAL_,31,0x7fffffff)
+#define SET_DBG_WFF_FULL(_VAL_) SET_REG(ADR_DBG_WFF_FULL,_VAL_,0,0xffff0000)
+#define SET_DBG_WFF_FULL_CLR(_VAL_) SET_REG(ADR_DBG_WFF_FULL,_VAL_,31,0x7fffffff)
+#define SET_DBG_MB_FULL(_VAL_) SET_REG(ADR_DBG_MB_FULL,_VAL_,0,0xffff0000)
+#define SET_DBG_MB_FULL_CLR(_VAL_) SET_REG(ADR_DBG_MB_FULL,_VAL_,31,0x7fffffff)
+#define SET_BA_CTRL(_VAL_) SET_REG(ADR_BA_CTRL,_VAL_,0,0xfffffffc)
+#define SET_BA_DBG_EN(_VAL_) SET_REG(ADR_BA_CTRL,_VAL_,2,0xfffffffb)
+#define SET_BA_AGRE_EN(_VAL_) SET_REG(ADR_BA_CTRL,_VAL_,3,0xfffffff7)
+#define SET_BA_TA_31_0(_VAL_) SET_REG(ADR_BA_TA_0,_VAL_,0,0x00000000)
+#define SET_BA_TA_47_32(_VAL_) SET_REG(ADR_BA_TA_1,_VAL_,0,0xffff0000)
+#define SET_BA_TID(_VAL_) SET_REG(ADR_BA_TID,_VAL_,0,0xfffffff0)
+#define SET_BA_ST_SEQ(_VAL_) SET_REG(ADR_BA_ST_SEQ,_VAL_,0,0xfffff000)
+#define SET_BA_SB0(_VAL_) SET_REG(ADR_BA_SB0,_VAL_,0,0x00000000)
+#define SET_BA_SB1(_VAL_) SET_REG(ADR_BA_SB1,_VAL_,0,0x00000000)
+#define SET_MRX_WD(_VAL_) SET_REG(ADR_MRX_WATCH_DOG,_VAL_,0,0xfffe0000)
+#define SET_ACK_GEN_EN(_VAL_) SET_REG(ADR_ACK_GEN_EN,_VAL_,0,0xfffffffe)
+#define SET_BA_GEN_EN(_VAL_) SET_REG(ADR_ACK_GEN_EN,_VAL_,1,0xfffffffd)
+#define SET_ACK_GEN_DUR(_VAL_) SET_REG(ADR_ACK_GEN_PARA,_VAL_,0,0xffff0000)
+#define SET_ACK_GEN_INFO(_VAL_) SET_REG(ADR_ACK_GEN_PARA,_VAL_,16,0xff00ffff)
+#define SET_ACK_GEN_RA_31_0(_VAL_) SET_REG(ADR_ACK_GEN_RA_0,_VAL_,0,0x00000000)
+#define SET_ACK_GEN_RA_47_32(_VAL_) SET_REG(ADR_ACK_GEN_RA_1,_VAL_,0,0xffff0000)
+#define SET_MIB_LEN_FAIL(_VAL_) SET_REG(ADR_MIB_LEN_FAIL,_VAL_,0,0xffff0000)
+#define SET_TRAP_HW_ID(_VAL_) SET_REG(ADR_TRAP_HW_ID,_VAL_,0,0xfffffff0)
+#define SET_ID_IN_USE(_VAL_) SET_REG(ADR_ID_IN_USE,_VAL_,0,0xffffff00)
+#define SET_MRX_ERR(_VAL_) SET_REG(ADR_MRX_ERR,_VAL_,0,0x00000000)
+#define SET_GRP_WSID(_VAL_) SET_REG(ADR_GROUP_WSID,_VAL_,0,0xfffffff0)
+#define SET_ADDR1A_SEL(_VAL_) SET_REG(ADR_HDR_ADDR_SEL,_VAL_,0,0xfffffffc)
+#define SET_ADDR2A_SEL(_VAL_) SET_REG(ADR_HDR_ADDR_SEL,_VAL_,2,0xfffffff3)
+#define SET_ADDR3A_SEL(_VAL_) SET_REG(ADR_HDR_ADDR_SEL,_VAL_,4,0xffffffcf)
+#define SET_ADDR1B_SEL(_VAL_) SET_REG(ADR_HDR_ADDR_SEL,_VAL_,6,0xffffff3f)
+#define SET_ADDR2B_SEL(_VAL_) SET_REG(ADR_HDR_ADDR_SEL,_VAL_,8,0xfffffcff)
+#define SET_ADDR3B_SEL(_VAL_) SET_REG(ADR_HDR_ADDR_SEL,_VAL_,10,0xfffff3ff)
+#define SET_ADDR3C_SEL(_VAL_) SET_REG(ADR_HDR_ADDR_SEL,_VAL_,12,0xffffcfff)
+#define SET_FRM_CTRL(_VAL_) SET_REG(ADR_FRAME_TYPE_CNTR_SET,_VAL_,0,0xffffffc0)
+#define SET_SCOREBOAD_SIZE(_VAL_) SET_REG(ADR_AMPDU_SCOREBOAD_SIZE,_VAL_,0,0xffffff80)
+#define SET_MASK_ABNORMAL_CRC(_VAL_) SET_REG(ADR_CHANNEL,_VAL_,0,0xfffffffe)
+#define SET_PS_EN(_VAL_) SET_REG(ADR_CHANNEL,_VAL_,1,0xfffffffd)
+#define SET_MULTI_AMPDU_W_EN(_VAL_) SET_REG(ADR_CHANNEL,_VAL_,2,0xfffffffb)
+#define SET_BA_H_QUEUE_EN(_VAL_) SET_REG(ADR_HIGH_PRIORITY_FRM_HW_ID,_VAL_,0,0xfffffffe)
+#define SET_EOSP_H_QUEUE_EN(_VAL_) SET_REG(ADR_HIGH_PRIORITY_FRM_HW_ID,_VAL_,1,0xfffffffd)
+#define SET_EOSP_HW_ID(_VAL_) SET_REG(ADR_HIGH_PRIORITY_FRM_HW_ID,_VAL_,2,0xffffffc3)
+#define SET_BA_HW_ID(_VAL_) SET_REG(ADR_HIGH_PRIORITY_FRM_HW_ID,_VAL_,6,0xfffffc3f)
+#define SET_IDX_EXTEND(_VAL_) SET_REG(ADR_DUAL_IDX_EXTEND,_VAL_,0,0xfffffffe)
+#define SET_MRX_FLT_EN9(_VAL_) SET_REG(ADR_MRX_FLT_EN9,_VAL_,0,0xffff0000)
+#define SET_MRX_FLT_EN10(_VAL_) SET_REG(ADR_MRX_FLT_EN10,_VAL_,0,0xffff0000)
+#define SET_CSR_PHY_INFO(_VAL_) SET_REG(ADR_PHY_INFO,_VAL_,0,0xffff8000)
+#define SET_AMPDU_SIG(_VAL_) SET_REG(ADR_AMPDU_SIG,_VAL_,0,0xffffff00)
+#define SET_MIB_AMPDU(_VAL_) SET_REG(ADR_MIB_AMPDU,_VAL_,0,0x00000000)
+#define SET_LEN_FLT(_VAL_) SET_REG(ADR_LEN_FLT,_VAL_,0,0xffff0000)
+#define SET_MIB_DELIMITER(_VAL_) SET_REG(ADR_MIB_DELIMITER,_VAL_,0,0xffff0000)
+#define SET_MTX_INT_Q0_Q_EMPTY(_VAL_) SET_REG(ADR_MTX_INT_STS,_VAL_,16,0xfffeffff)
+#define SET_MTX_INT_Q0_TXOP_RUNOUT(_VAL_) SET_REG(ADR_MTX_INT_STS,_VAL_,17,0xfffdffff)
+#define SET_MTX_INT_Q1_Q_EMPTY(_VAL_) SET_REG(ADR_MTX_INT_STS,_VAL_,18,0xfffbffff)
+#define SET_MTX_INT_Q1_TXOP_RUNOUT(_VAL_) SET_REG(ADR_MTX_INT_STS,_VAL_,19,0xfff7ffff)
+#define SET_MTX_INT_Q2_Q_EMPTY(_VAL_) SET_REG(ADR_MTX_INT_STS,_VAL_,20,0xffefffff)
+#define SET_MTX_INT_Q2_TXOP_RUNOUT(_VAL_) SET_REG(ADR_MTX_INT_STS,_VAL_,21,0xffdfffff)
+#define SET_MTX_INT_Q3_Q_EMPTY(_VAL_) SET_REG(ADR_MTX_INT_STS,_VAL_,22,0xffbfffff)
+#define SET_MTX_INT_Q3_TXOP_RUNOUT(_VAL_) SET_REG(ADR_MTX_INT_STS,_VAL_,23,0xff7fffff)
+#define SET_MTX_INT_Q4_Q_EMPTY(_VAL_) SET_REG(ADR_MTX_INT_STS,_VAL_,24,0xfeffffff)
+#define SET_MTX_INT_Q4_TXOP_RUNOUT(_VAL_) SET_REG(ADR_MTX_INT_STS,_VAL_,25,0xfdffffff)
+#define SET_MTX_INT_Q5_Q_EMPTY(_VAL_) SET_REG(ADR_MTX_INT_STS,_VAL_,26,0xfbffffff)
+#define SET_MTX_INT_Q5_TXOP_RUNOUT(_VAL_) SET_REG(ADR_MTX_INT_STS,_VAL_,27,0xf7ffffff)
+#define SET_MTX_EN_INT_Q0_Q_EMPTY(_VAL_) SET_REG(ADR_MTX_INT_EN,_VAL_,16,0xfffeffff)
+#define SET_MTX_EN_INT_Q0_TXOP_RUNOUT(_VAL_) SET_REG(ADR_MTX_INT_EN,_VAL_,17,0xfffdffff)
+#define SET_MTX_EN_INT_Q1_Q_EMPTY(_VAL_) SET_REG(ADR_MTX_INT_EN,_VAL_,18,0xfffbffff)
+#define SET_MTX_EN_INT_Q1_TXOP_RUNOUT(_VAL_) SET_REG(ADR_MTX_INT_EN,_VAL_,19,0xfff7ffff)
+#define SET_MTX_EN_INT_Q2_Q_EMPTY(_VAL_) SET_REG(ADR_MTX_INT_EN,_VAL_,20,0xffefffff)
+#define SET_MTX_EN_INT_Q2_TXOP_RUNOUT(_VAL_) SET_REG(ADR_MTX_INT_EN,_VAL_,21,0xffdfffff)
+#define SET_MTX_EN_INT_Q3_Q_EMPTY(_VAL_) SET_REG(ADR_MTX_INT_EN,_VAL_,22,0xffbfffff)
+#define SET_MTX_EN_INT_Q3_TXOP_RUNOUT(_VAL_) SET_REG(ADR_MTX_INT_EN,_VAL_,23,0xff7fffff)
+#define SET_MTX_EN_INT_Q4_Q_EMPTY(_VAL_) SET_REG(ADR_MTX_INT_EN,_VAL_,24,0xfeffffff)
+#define SET_MTX_EN_INT_Q4_TXOP_RUNOUT(_VAL_) SET_REG(ADR_MTX_INT_EN,_VAL_,25,0xfdffffff)
+#define SET_MTX_EN_INT_Q5_Q_EMPTY(_VAL_) SET_REG(ADR_MTX_INT_EN,_VAL_,26,0xfbffffff)
+#define SET_MTX_EN_INT_Q5_TXOP_RUNOUT(_VAL_) SET_REG(ADR_MTX_INT_EN,_VAL_,27,0xf7ffffff)
+#define SET_MTX_MTX2PHY_SLOW(_VAL_) SET_REG(ADR_MTX_MISC_EN,_VAL_,0,0xfffffffe)
+#define SET_MTX_M2M_SLOW_PRD(_VAL_) SET_REG(ADR_MTX_MISC_EN,_VAL_,1,0xfffffff1)
+#define SET_MTX_AMPDU_CRC8_AUTO(_VAL_) SET_REG(ADR_MTX_MISC_EN,_VAL_,5,0xffffffdf)
+#define SET_MTX_BLOCKTX_IGNORE_BT_BUSY(_VAL_) SET_REG(ADR_MTX_MISC_EN,_VAL_,6,0xffffffbf)
+#define SET_MTX_RAW_DATA_MODE(_VAL_) SET_REG(ADR_MTX_MISC_EN,_VAL_,7,0xffffff7f)
+#define SET_MTX_BLOCKTX_IGNORE_TOMAC_TX_IP(_VAL_) SET_REG(ADR_MTX_MISC_EN,_VAL_,11,0xfffff7ff)
+#define SET_MTX_BLOCKTX_IGNORE_TOMAC_RX_EN(_VAL_) SET_REG(ADR_MTX_MISC_EN,_VAL_,12,0xffffefff)
+#define SET_MTX_BLOCKTX_IGNORE_TOMAC_CCA_CS(_VAL_) SET_REG(ADR_MTX_MISC_EN,_VAL_,13,0xffffdfff)
+#define SET_MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_SECONDARY(_VAL_) SET_REG(ADR_MTX_MISC_EN,_VAL_,14,0xffffbfff)
+#define SET_MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_PRIMARY(_VAL_) SET_REG(ADR_MTX_MISC_EN,_VAL_,15,0xffff7fff)
+#define SET_MTX_HALT_Q_MB(_VAL_) SET_REG(ADR_MTX_MISC_EN,_VAL_,16,0xff80ffff)
+#define SET_MTX_IGNORE_PHYRX_IFS_DELTATIME(_VAL_) SET_REG(ADR_MTX_MISC_EN,_VAL_,24,0xfeffffff)
+#define SET_MTX_SELFSTA_PS(_VAL_) SET_REG(ADR_MTX_MISC_EN,_VAL_,25,0xfdffffff)
+#define SET_NO_PKT_BUF_REDUCTION(_VAL_) SET_REG(ADR_MTX_TX_REPORT_OPTION,_VAL_,0,0xfffffffe)
+#define SET_NO_REDUCE_TXALLFAIL_PKT(_VAL_) SET_REG(ADR_MTX_TX_REPORT_OPTION,_VAL_,2,0xfffffffb)
+#define SET_NO_REDUCE_PKT_PEERPS_MPDU(_VAL_) SET_REG(ADR_MTX_TX_REPORT_OPTION,_VAL_,4,0xffffffef)
+#define SET_NO_REDUCE_PKT_PEERPS_AMPDUV1P2(_VAL_) SET_REG(ADR_MTX_TX_REPORT_OPTION,_VAL_,6,0xffffffbf)
+#define SET_NO_REDUCE_PKT_PEERPS_AMPDUV1P3(_VAL_) SET_REG(ADR_MTX_TX_REPORT_OPTION,_VAL_,7,0xffffff7f)
+#define SET_RO_PTC_SCHEDULE(_VAL_) SET_REG(ADR_MTX_STATUS0,_VAL_,0,0xfffffff0)
+#define SET_RO_FSM_MTXPTC(_VAL_) SET_REG(ADR_MTX_STATUS0,_VAL_,4,0xffffff8f)
+#define SET_RO_ACT_MASK(_VAL_) SET_REG(ADR_MTX_STATUS0,_VAL_,8,0xffff80ff)
+#define SET_RO_CAND_MASK(_VAL_) SET_REG(ADR_MTX_STATUS0,_VAL_,16,0xff80ffff)
+#define SET_RO_WAIT_RESPONSE_PHASE(_VAL_) SET_REG(ADR_MTX_STATUS0,_VAL_,24,0xfcffffff)
+#define SET_RO_FSM_MTXHALT(_VAL_) SET_REG(ADR_MTX_STATUS0,_VAL_,28,0xcfffffff)
+#define SET_RO_FSM_MTXDMA(_VAL_) SET_REG(ADR_MTX_STATUS4,_VAL_,0,0xfffffff8)
+#define SET_RO_FSM_MTXPHYTX(_VAL_) SET_REG(ADR_MTX_STATUS4,_VAL_,4,0xffffff8f)
+#define SET_RO_MTXDMA_CMD(_VAL_) SET_REG(ADR_MTX_STATUS4,_VAL_,8,0xffffc0ff)
+#define SET_RO_TXOP_INTERVAL(_VAL_) SET_REG(ADR_MTX_STATUS4,_VAL_,16,0x0000ffff)
+#define SET_MTX_HALT_MODE0(_VAL_) SET_REG(ADR_MTX_HALT_OPTION,_VAL_,0,0xfffffffe)
+#define SET_BLOCK_TXQ(_VAL_) SET_REG(ADR_MTX_HALT_OPTION,_VAL_,16,0xff80ffff)
+#define SET_MTX_HALT_IGNORE_TXREQ_EN(_VAL_) SET_REG(ADR_MTX_HALT_OPTION,_VAL_,24,0xfeffffff)
+#define SET_MTX_HALT_IGNORE_RXREQ_EN(_VAL_) SET_REG(ADR_MTX_HALT_OPTION,_VAL_,25,0xfdffffff)
+#define SET_DBG_PHYTX_PROCEED(_VAL_) SET_REG(ADR_MTX_PHYTX_DBG1,_VAL_,0,0xfffffffe)
+#define SET_MTX_MIB_CNT0(_VAL_) SET_REG(ADR_MTX_MIB_WSID0,_VAL_,0,0xc0000000)
+#define SET_MTX_MIB_EN0(_VAL_) SET_REG(ADR_MTX_MIB_WSID0,_VAL_,30,0xbfffffff)
+#define SET_MTX_MIB_CNT1(_VAL_) SET_REG(ADR_MTX_MIB_WSID1,_VAL_,0,0xc0000000)
+#define SET_MTX_MIB_EN1(_VAL_) SET_REG(ADR_MTX_MIB_WSID1,_VAL_,30,0xbfffffff)
+#define SET_MTX_MIB_CNT2(_VAL_) SET_REG(ADR_MTX_MIB_WSID2,_VAL_,0,0xc0000000)
+#define SET_MTX_MIB_EN2(_VAL_) SET_REG(ADR_MTX_MIB_WSID2,_VAL_,30,0xbfffffff)
+#define SET_MTX_MIB_CNT3(_VAL_) SET_REG(ADR_MTX_MIB_WSID3,_VAL_,0,0xc0000000)
+#define SET_MTX_MIB_EN3(_VAL_) SET_REG(ADR_MTX_MIB_WSID3,_VAL_,30,0xbfffffff)
+#define SET_MTX_MIB_CNT4(_VAL_) SET_REG(ADR_MTX_MIB_WSID4,_VAL_,0,0xc0000000)
+#define SET_MTX_MIB_EN4(_VAL_) SET_REG(ADR_MTX_MIB_WSID4,_VAL_,30,0xbfffffff)
+#define SET_MTX_MIB_CNT5(_VAL_) SET_REG(ADR_MTX_MIB_WSID5,_VAL_,0,0xc0000000)
+#define SET_MTX_MIB_EN5(_VAL_) SET_REG(ADR_MTX_MIB_WSID5,_VAL_,30,0xbfffffff)
+#define SET_MTX_MIB_CNT6(_VAL_) SET_REG(ADR_MTX_MIB_WSID6,_VAL_,0,0xc0000000)
+#define SET_MTX_MIB_EN6(_VAL_) SET_REG(ADR_MTX_MIB_WSID6,_VAL_,30,0xbfffffff)
+#define SET_MTX_MIB_CNT7(_VAL_) SET_REG(ADR_MTX_MIB_WSID7,_VAL_,0,0xc0000000)
+#define SET_MTX_MIB_EN7(_VAL_) SET_REG(ADR_MTX_MIB_WSID7,_VAL_,30,0xbfffffff)
+#define SET_EN_UNEXPECT_WSID(_VAL_) SET_REG(ADR_STAT_CONF0,_VAL_,0,0xfffffffe)
+#define SET_EN_STAT_FINISH_INT(_VAL_) SET_REG(ADR_STAT_CONF0,_VAL_,1,0xfffffffd)
+#define SET_STAT_EN_MB(_VAL_) SET_REG(ADR_STAT_CONF0,_VAL_,6,0xffffffbf)
+#define SET_STAT_MB_TARGET(_VAL_) SET_REG(ADR_STAT_CONF0,_VAL_,7,0xffffff7f)
+#define SET_STAT_UNEXPECT_WSID(_VAL_) SET_REG(ADR_STAT_CONF0,_VAL_,8,0xfffffeff)
+#define SET_STAT_FINISH(_VAL_) SET_REG(ADR_STAT_CONF0,_VAL_,9,0xfffffdff)
+#define SET_STAT_PKT_ID(_VAL_) SET_REG(ADR_STAT_CONF0,_VAL_,16,0xff80ffff)
+#define SET_STAT_FSM(_VAL_) SET_REG(ADR_STAT_CONF0,_VAL_,24,0xe0ffffff)
+#define SET_STAT_ENABLE(_VAL_) SET_REG(ADR_STAT_CONF0,_VAL_,29,0xdfffffff)
+#define SET_STAT_WSID(_VAL_) SET_REG(ADR_STAT_CONF1,_VAL_,0,0xfffffff8)
+#define SET_STAT_FREEZE(_VAL_) SET_REG(ADR_STAT_CONF1,_VAL_,8,0xfffffeff)
+#define SET_STAT_CLR(_VAL_) SET_REG(ADR_STAT_CONF1,_VAL_,9,0xfffffdff)
+#define SET_STAT_CLR_DONE(_VAL_) SET_REG(ADR_STAT_CONF1,_VAL_,10,0xfffffbff)
+#define SET_MAC_TX_PS_UNLOCK(_VAL_) SET_REG(ADR_MTX_PEER_PS_LOCK,_VAL_,0,0xffffff00)
+#define SET_MAC_TX_PEER_PS_LOCK_EN(_VAL_) SET_REG(ADR_MTX_PEER_PS_LOCK,_VAL_,8,0xfffffeff)
+#define SET_MAC_TX_PEER_PS_LOCK_AUTOLOCK_EN(_VAL_) SET_REG(ADR_MTX_PEER_PS_LOCK,_VAL_,9,0xfffffdff)
+#define SET_MAC_TX_PS_LOCK(_VAL_) SET_REG(ADR_MTX_PEER_PS_LOCK,_VAL_,24,0x00ffffff)
+#define SET_MAC_TX_PS_LOCK_STATUS(_VAL_) SET_REG(ADR_MTX_PEER_LOCK_STATUS,_VAL_,0,0xffffff00)
+#define SET_MTX_RATERPT_HWID(_VAL_) SET_REG(ADR_MTX_RATERPT,_VAL_,0,0xfffffff0)
+#define SET_CTYPE_RATE_RPT(_VAL_) SET_REG(ADR_MTX_RATERPT,_VAL_,4,0xffffff8f)
+#define SET_MTX_DBGOPT_FORCE_TXMAJOR_RATE(_VAL_) SET_REG(ADR_MTX_DBGOPT_FORCE_RATE,_VAL_,0,0xffffff00)
+#define SET_MTX_DBGOPT_FORCE_TXCTRL_RATE(_VAL_) SET_REG(ADR_MTX_DBGOPT_FORCE_RATE,_VAL_,8,0xffff00ff)
+#define SET_MTX_DBGOPT_FORCE_DO_RTS_CTS_MODE(_VAL_) SET_REG(ADR_MTX_DBGOPT_FORCE_RATE,_VAL_,16,0xfffcffff)
+#define SET_MTX_DBGOPT_FORCE_TXMAJOR_RATE_EN(_VAL_) SET_REG(ADR_MTX_DBGOPT_FORCE_RATE_ENABLE,_VAL_,0,0xfffffffe)
+#define SET_MTX_DBGOPT_FORCE_TXCTRL_RATE_EN(_VAL_) SET_REG(ADR_MTX_DBGOPT_FORCE_RATE_ENABLE,_VAL_,2,0xfffffffb)
+#define SET_MTX_DBGOPT_FORCE_DO_RTS_CTS_MODE_EN(_VAL_) SET_REG(ADR_MTX_DBGOPT_FORCE_RATE_ENABLE,_VAL_,4,0xffffffef)
+#define SET_RO_PHYTXIP_TIMEOUT_CNT(_VAL_) SET_REG(ADR_MTX_DBG_PHYTXIPTIMEOUT,_VAL_,0,0xfffffff0)
+#define SET_DBG_PHYTXIP_TIMEOUT_RECOVERY(_VAL_) SET_REG(ADR_MTX_DBG_PHYTXIPTIMEOUT,_VAL_,8,0xfffffeff)
+#define SET_DBG_MTX_IGNORE_NAV(_VAL_) SET_REG(ADR_MTX_DBG_MORE,_VAL_,0,0xfffffffe)
+#define SET_RO_IFSAIR1(_VAL_) SET_REG(ADR_MTX_DBG_ROIFSAIR1,_VAL_,0,0x00000000)
+#define SET_RO_IFSAIR2(_VAL_) SET_REG(ADR_MTX_DBG_ROIFSAIR2,_VAL_,0,0x00000000)
+#define SET_MTX_BCN_PKT_ID0(_VAL_) SET_REG(ADR_MTX_BCN_PKT_SET0,_VAL_,0,0xffffff80)
+#define SET_MTX_BCN_PKT_ID1(_VAL_) SET_REG(ADR_MTX_BCN_PKT_SET1,_VAL_,0,0xffffff80)
+#define SET_MTX_DTIM_OFST0(_VAL_) SET_REG(ADR_MTX_BCN_DTIM_SET0,_VAL_,0,0xfffffc00)
+#define SET_MTX_DTIM_OFST1(_VAL_) SET_REG(ADR_MTX_BCN_DTIM_SET1,_VAL_,0,0xfffffc00)
+#define SET_MTX_DTIM_NUM(_VAL_) SET_REG(ADR_MTX_BCN_DTIM_CONFG,_VAL_,0,0xffffff00)
+#define SET_MTX_INT_DTIM_NUM(_VAL_) SET_REG(ADR_MTX_BCN_DTIM_CONFG,_VAL_,8,0xffff00ff)
+#define SET_MTX_INT_DTIM(_VAL_) SET_REG(ADR_MTX_BCN_DTIM_INT_W1CLR,_VAL_,0,0xfffffffe)
+#define SET_MTX_INT_BCN(_VAL_) SET_REG(ADR_MTX_BCN_INT_STS,_VAL_,0,0xfffffffe)
+#define SET_MTX_EN_INT_BCN(_VAL_) SET_REG(ADR_MTX_BCN_EN_INT,_VAL_,1,0xfffffffd)
+#define SET_MTX_EN_INT_DTIM(_VAL_) SET_REG(ADR_MTX_BCN_EN_INT,_VAL_,3,0xfffffff7)
+#define SET_MTX_BCN_TIMER_EN(_VAL_) SET_REG(ADR_MTX_BCN_EN_MISC,_VAL_,0,0xfffffffe)
+#define SET_MTX_TIME_STAMP_AUTO_FILL(_VAL_) SET_REG(ADR_MTX_BCN_EN_MISC,_VAL_,1,0xfffffffd)
+#define SET_MTX_DTIM_CNT_AUTO_FILL(_VAL_) SET_REG(ADR_MTX_BCN_EN_MISC,_VAL_,3,0xfffffff7)
+#define SET_MTX_TSF_TIMER_EN(_VAL_) SET_REG(ADR_MTX_BCN_EN_MISC,_VAL_,5,0xffffffdf)
+#define SET_TXQ5_DTIM_BEACON_BURST_MNG(_VAL_) SET_REG(ADR_MTX_BCN_EN_MISC,_VAL_,16,0xfffeffff)
+#define SET_MTX_BCN_AUTO_SEQ_NO(_VAL_) SET_REG(ADR_MTX_BCN_EN_MISC,_VAL_,17,0xfffdffff)
+#define SET_MTX_BCN_PKTID_CH_LOCK(_VAL_) SET_REG(ADR_MTX_BCN_MISC,_VAL_,0,0xfffffffe)
+#define SET_MTX_BCN_CFG_VLD(_VAL_) SET_REG(ADR_MTX_BCN_MISC,_VAL_,1,0xfffffff9)
+#define SET_MTX_AUTO_BCN_ONGOING(_VAL_) SET_REG(ADR_MTX_BCN_MISC,_VAL_,3,0xfffffff7)
+#define SET_MTX_BCN_TIMER(_VAL_) SET_REG(ADR_MTX_BCN_MISC,_VAL_,16,0x0000ffff)
+#define SET_MTX_BCN_PERIOD(_VAL_) SET_REG(ADR_MTX_BCN_PRD,_VAL_,0,0xffff0000)
+#define SET_MTX_BCN_TSF_L(_VAL_) SET_REG(ADR_MTX_BCN_TSF_L,_VAL_,0,0x00000000)
+#define SET_MTX_BCN_TSF_U(_VAL_) SET_REG(ADR_MTX_BCN_TSF_U,_VAL_,0,0x00000000)
+#define SET_TOUT_B(_VAL_) SET_REG(ADR_MTX_TIME_TOUT,_VAL_,0,0xffffff00)
+#define SET_TOUT_AGN(_VAL_) SET_REG(ADR_MTX_TIME_TOUT,_VAL_,8,0xffff00ff)
+#define SET_EIFS_IN_SLOT(_VAL_) SET_REG(ADR_MTX_TIME_TOUT,_VAL_,16,0xffc0ffff)
+#define SET_TXSIFS_SUB_MIN(_VAL_) SET_REG(ADR_MTX_TIME_IFS,_VAL_,0,0xfffffff0)
+#define SET_TXSIFS_SUB_MAX(_VAL_) SET_REG(ADR_MTX_TIME_IFS,_VAL_,4,0xffffff0f)
+#define SET_SLOTTIME(_VAL_) SET_REG(ADR_MTX_TIME_IFS,_VAL_,8,0xffffe0ff)
+#define SET_SIFS(_VAL_) SET_REG(ADR_MTX_TIME_IFS,_VAL_,16,0xffe0ffff)
+#define SET_NAVCS_PHYCS_FALL_OFFSET_STEP(_VAL_) SET_REG(ADR_MTX_TIME_FINETUNE,_VAL_,0,0xffffff80)
+#define SET_TX_IP_FALL_OFFSET_STEP(_VAL_) SET_REG(ADR_MTX_TIME_FINETUNE,_VAL_,8,0xffff80ff)
+#define SET_PHYTXSTART_NCYCLE(_VAL_) SET_REG(ADR_MTX_TIME_FINETUNE,_VAL_,16,0xff80ffff)
+#define SET_SIGEXT(_VAL_) SET_REG(ADR_MTX_TIME_FINETUNE,_VAL_,24,0xf0ffffff)
+#define SET_MAC_CLK_80M(_VAL_) SET_REG(ADR_MTX_TIME_FINETUNE,_VAL_,28,0xefffffff)
+#define SET_RO_MTX_TX_EN(_VAL_) SET_REG(ADR_MTX_STATUS,_VAL_,20,0xffefffff)
+#define SET_RO_MAC_TX_FIFO_WINC(_VAL_) SET_REG(ADR_MTX_STATUS,_VAL_,21,0xffdfffff)
+#define SET_RO_MAC_TX_FIFO_WFULL_MX(_VAL_) SET_REG(ADR_MTX_STATUS,_VAL_,22,0xffbfffff)
+#define SET_RO_MAC_TX_FIFO_WEMPTY(_VAL_) SET_REG(ADR_MTX_STATUS,_VAL_,23,0xff7fffff)
+#define SET_TOMAC_TX_IP(_VAL_) SET_REG(ADR_MTX_STATUS,_VAL_,24,0xfeffffff)
+#define SET_TOMAC_ED_CCA_PRIMARY_MX(_VAL_) SET_REG(ADR_MTX_STATUS,_VAL_,28,0xefffffff)
+#define SET_TOMAC_ED_CCA_SECONDARY_MX(_VAL_) SET_REG(ADR_MTX_STATUS,_VAL_,29,0xdfffffff)
+#define SET_TOMAC_CS_CCA_MX(_VAL_) SET_REG(ADR_MTX_STATUS,_VAL_,30,0xbfffffff)
+#define SET_BT_BUSY(_VAL_) SET_REG(ADR_MTX_STATUS,_VAL_,31,0x7fffffff)
+#define SET_MTX_DBG_PHYRX_IFS_DELTATIME(_VAL_) SET_REG(ADR_MTX_PHYRXIFS_DBG,_VAL_,0,0xfffff800)
+#define SET_RO_IFSST0(_VAL_) SET_REG(ADR_MTX_DBG_IFSAIRRO0,_VAL_,0,0x00000000)
+#define SET_RO_IFSST1(_VAL_) SET_REG(ADR_MTX_DBG_IFSAIRRO1,_VAL_,0,0x00000000)
+#define SET_RO_IFSST2(_VAL_) SET_REG(ADR_MTX_DBG_IFSAIRRO2,_VAL_,0,0x00000000)
+#define SET_RO_IFSST3(_VAL_) SET_REG(ADR_MTX_DBG_IFSAIRRO3,_VAL_,0,0x00000000)
+#define SET_MTX_NAV(_VAL_) SET_REG(ADR_MTX_NAV,_VAL_,0,0xffff0000)
+#define SET_RO_MTX_BASE1(_VAL_) SET_REG(ADR_MTX_DBG_RO_BASE1,_VAL_,0,0x00000000)
+#define SET_RO_MTX_BASE2(_VAL_) SET_REG(ADR_MTX_DBG_RO_BASE2,_VAL_,0,0x00000000)
+#define SET_RO_MTX_BASE3(_VAL_) SET_REG(ADR_MTX_DBG_RO_BASE3,_VAL_,0,0x00000000)
+#define SET_TXQ0_MTX_Q_RND_MODE(_VAL_) SET_REG(ADR_TXQ0_MTX_Q_MISC_EN,_VAL_,0,0xfffffff8)
+#define SET_TXQ0_MTX_Q_MB_NO_RLS(_VAL_) SET_REG(ADR_TXQ0_MTX_Q_MISC_EN,_VAL_,4,0xffffffef)
+#define SET_TXQ0_Q_NULLDATAFRAME_GEN_EN(_VAL_) SET_REG(ADR_TXQ0_MTX_Q_MISC_EN,_VAL_,31,0x7fffffff)
+#define SET_TXQ0_MTX_Q_AIFSN(_VAL_) SET_REG(ADR_TXQ0_MTX_Q_AIFSN,_VAL_,0,0xfffffff0)
+#define SET_TXQ0_MTX_Q_ECWMIN(_VAL_) SET_REG(ADR_TXQ0_MTX_Q_AIFSN,_VAL_,8,0xfffff0ff)
+#define SET_TXQ0_MTX_Q_ECWMAX(_VAL_) SET_REG(ADR_TXQ0_MTX_Q_AIFSN,_VAL_,12,0xffff0fff)
+#define SET_TXQ0_MTX_Q_TXOP_LIMIT(_VAL_) SET_REG(ADR_TXQ0_MTX_Q_AIFSN,_VAL_,16,0x0000ffff)
+#define SET_TXQ0_MTX_Q_BKF_CNT_FIX(_VAL_) SET_REG(ADR_TXQ0_MTX_Q_BKF_CNT_DBG,_VAL_,0,0xffff0000)
+#define SET_TXQ0_RO_FSM_TXQ(_VAL_) SET_REG(ADR_TXQ0_MTX_Q_HWDBG,_VAL_,0,0xfffffffc)
+#define SET_TXQ0_RO_TRY_CNT(_VAL_) SET_REG(ADR_TXQ0_MTX_Q_HWDBG,_VAL_,4,0xffffff0f)
+#define SET_TXQ0_RO_RATESET_IDX(_VAL_) SET_REG(ADR_TXQ0_MTX_Q_HWDBG,_VAL_,8,0xfffffcff)
+#define SET_TXQ0_RO_AIFS_CNT(_VAL_) SET_REG(ADR_TXQ0_MTX_Q_HWDBG,_VAL_,12,0xffff0fff)
+#define SET_TXQ0_RO_BKF_CNT(_VAL_) SET_REG(ADR_TXQ0_MTX_Q_HWDBG,_VAL_,16,0x0000ffff)
+#define SET_TXQ0_RO_PKTID(_VAL_) SET_REG(ADR_TXQ0_MTX_Q_HWDBG2,_VAL_,0,0xffffff80)
+#define SET_TXQ1_MTX_Q_RND_MODE(_VAL_) SET_REG(ADR_TXQ1_MTX_Q_MISC_EN,_VAL_,0,0xfffffff8)
+#define SET_TXQ1_MTX_Q_MB_NO_RLS(_VAL_) SET_REG(ADR_TXQ1_MTX_Q_MISC_EN,_VAL_,4,0xffffffef)
+#define SET_TXQ1_Q_NULLDATAFRAME_GEN_EN(_VAL_) SET_REG(ADR_TXQ1_MTX_Q_MISC_EN,_VAL_,31,0x7fffffff)
+#define SET_TXQ1_MTX_Q_AIFSN(_VAL_) SET_REG(ADR_TXQ1_MTX_Q_AIFSN,_VAL_,0,0xfffffff0)
+#define SET_TXQ1_MTX_Q_ECWMIN(_VAL_) SET_REG(ADR_TXQ1_MTX_Q_AIFSN,_VAL_,8,0xfffff0ff)
+#define SET_TXQ1_MTX_Q_ECWMAX(_VAL_) SET_REG(ADR_TXQ1_MTX_Q_AIFSN,_VAL_,12,0xffff0fff)
+#define SET_TXQ1_MTX_Q_TXOP_LIMIT(_VAL_) SET_REG(ADR_TXQ1_MTX_Q_AIFSN,_VAL_,16,0x0000ffff)
+#define SET_TXQ1_MTX_Q_BKF_CNT_FIX(_VAL_) SET_REG(ADR_TXQ1_MTX_Q_BKF_CNT_DBG,_VAL_,0,0xffff0000)
+#define SET_TXQ1_RO_FSM_TXQ(_VAL_) SET_REG(ADR_TXQ1_MTX_Q_HWDBG,_VAL_,0,0xfffffffc)
+#define SET_TXQ1_RO_TRY_CNT(_VAL_) SET_REG(ADR_TXQ1_MTX_Q_HWDBG,_VAL_,4,0xffffff0f)
+#define SET_TXQ1_RO_RATESET_IDX(_VAL_) SET_REG(ADR_TXQ1_MTX_Q_HWDBG,_VAL_,8,0xfffffcff)
+#define SET_TXQ1_RO_AIFS_CNT(_VAL_) SET_REG(ADR_TXQ1_MTX_Q_HWDBG,_VAL_,12,0xffff0fff)
+#define SET_TXQ1_RO_BKF_CNT(_VAL_) SET_REG(ADR_TXQ1_MTX_Q_HWDBG,_VAL_,16,0x0000ffff)
+#define SET_TXQ1_RO_PKTID(_VAL_) SET_REG(ADR_TXQ1_MTX_Q_HWDBG2,_VAL_,0,0xffffff80)
+#define SET_TXQ2_MTX_Q_RND_MODE(_VAL_) SET_REG(ADR_TXQ2_MTX_Q_MISC_EN,_VAL_,0,0xfffffff8)
+#define SET_TXQ2_MTX_Q_MB_NO_RLS(_VAL_) SET_REG(ADR_TXQ2_MTX_Q_MISC_EN,_VAL_,4,0xffffffef)
+#define SET_TXQ2_Q_NULLDATAFRAME_GEN_EN(_VAL_) SET_REG(ADR_TXQ2_MTX_Q_MISC_EN,_VAL_,31,0x7fffffff)
+#define SET_TXQ2_MTX_Q_AIFSN(_VAL_) SET_REG(ADR_TXQ2_MTX_Q_AIFSN,_VAL_,0,0xfffffff0)
+#define SET_TXQ2_MTX_Q_ECWMIN(_VAL_) SET_REG(ADR_TXQ2_MTX_Q_AIFSN,_VAL_,8,0xfffff0ff)
+#define SET_TXQ2_MTX_Q_ECWMAX(_VAL_) SET_REG(ADR_TXQ2_MTX_Q_AIFSN,_VAL_,12,0xffff0fff)
+#define SET_TXQ2_MTX_Q_TXOP_LIMIT(_VAL_) SET_REG(ADR_TXQ2_MTX_Q_AIFSN,_VAL_,16,0x0000ffff)
+#define SET_TXQ2_MTX_Q_BKF_CNT_FIX(_VAL_) SET_REG(ADR_TXQ2_MTX_Q_BKF_CNT_DBG,_VAL_,0,0xffff0000)
+#define SET_TXQ2_RO_FSM_TXQ(_VAL_) SET_REG(ADR_TXQ2_MTX_Q_HWDBG,_VAL_,0,0xfffffffc)
+#define SET_TXQ2_RO_TRY_CNT(_VAL_) SET_REG(ADR_TXQ2_MTX_Q_HWDBG,_VAL_,4,0xffffff0f)
+#define SET_TXQ2_RO_RATESET_IDX(_VAL_) SET_REG(ADR_TXQ2_MTX_Q_HWDBG,_VAL_,8,0xfffffcff)
+#define SET_TXQ2_RO_AIFS_CNT(_VAL_) SET_REG(ADR_TXQ2_MTX_Q_HWDBG,_VAL_,12,0xffff0fff)
+#define SET_TXQ2_RO_BKF_CNT(_VAL_) SET_REG(ADR_TXQ2_MTX_Q_HWDBG,_VAL_,16,0x0000ffff)
+#define SET_TXQ2_RO_PKTID(_VAL_) SET_REG(ADR_TXQ2_MTX_Q_HWDBG2,_VAL_,0,0xffffff80)
+#define SET_TXQ3_MTX_Q_RND_MODE(_VAL_) SET_REG(ADR_TXQ3_MTX_Q_MISC_EN,_VAL_,0,0xfffffff8)
+#define SET_TXQ3_MTX_Q_MB_NO_RLS(_VAL_) SET_REG(ADR_TXQ3_MTX_Q_MISC_EN,_VAL_,4,0xffffffef)
+#define SET_TXQ3_Q_NULLDATAFRAME_GEN_EN(_VAL_) SET_REG(ADR_TXQ3_MTX_Q_MISC_EN,_VAL_,31,0x7fffffff)
+#define SET_TXQ3_MTX_Q_AIFSN(_VAL_) SET_REG(ADR_TXQ3_MTX_Q_AIFSN,_VAL_,0,0xfffffff0)
+#define SET_TXQ3_MTX_Q_ECWMIN(_VAL_) SET_REG(ADR_TXQ3_MTX_Q_AIFSN,_VAL_,8,0xfffff0ff)
+#define SET_TXQ3_MTX_Q_ECWMAX(_VAL_) SET_REG(ADR_TXQ3_MTX_Q_AIFSN,_VAL_,12,0xffff0fff)
+#define SET_TXQ3_MTX_Q_TXOP_LIMIT(_VAL_) SET_REG(ADR_TXQ3_MTX_Q_AIFSN,_VAL_,16,0x0000ffff)
+#define SET_TXQ3_MTX_Q_BKF_CNT_FIX(_VAL_) SET_REG(ADR_TXQ3_MTX_Q_BKF_CNT_DBG,_VAL_,0,0xffff0000)
+#define SET_TXQ3_RO_FSM_TXQ(_VAL_) SET_REG(ADR_TXQ3_MTX_Q_HWDBG,_VAL_,0,0xfffffffc)
+#define SET_TXQ3_RO_TRY_CNT(_VAL_) SET_REG(ADR_TXQ3_MTX_Q_HWDBG,_VAL_,4,0xffffff0f)
+#define SET_TXQ3_RO_RATESET_IDX(_VAL_) SET_REG(ADR_TXQ3_MTX_Q_HWDBG,_VAL_,8,0xfffffcff)
+#define SET_TXQ3_RO_AIFS_CNT(_VAL_) SET_REG(ADR_TXQ3_MTX_Q_HWDBG,_VAL_,12,0xffff0fff)
+#define SET_TXQ3_RO_BKF_CNT(_VAL_) SET_REG(ADR_TXQ3_MTX_Q_HWDBG,_VAL_,16,0x0000ffff)
+#define SET_TXQ3_RO_PKTID(_VAL_) SET_REG(ADR_TXQ3_MTX_Q_HWDBG2,_VAL_,0,0xffffff80)
+#define SET_TXQ4_MTX_Q_RND_MODE(_VAL_) SET_REG(ADR_TXQ4_MTX_Q_MISC_EN,_VAL_,0,0xfffffff8)
+#define SET_TXQ4_MTX_Q_MB_NO_RLS(_VAL_) SET_REG(ADR_TXQ4_MTX_Q_MISC_EN,_VAL_,4,0xffffffef)
+#define SET_TXQ4_Q_NULLDATAFRAME_GEN_EN(_VAL_) SET_REG(ADR_TXQ4_MTX_Q_MISC_EN,_VAL_,31,0x7fffffff)
+#define SET_TXQ4_MTX_Q_AIFSN(_VAL_) SET_REG(ADR_TXQ4_MTX_Q_AIFSN,_VAL_,0,0xfffffff0)
+#define SET_TXQ4_MTX_Q_ECWMIN(_VAL_) SET_REG(ADR_TXQ4_MTX_Q_AIFSN,_VAL_,8,0xfffff0ff)
+#define SET_TXQ4_MTX_Q_ECWMAX(_VAL_) SET_REG(ADR_TXQ4_MTX_Q_AIFSN,_VAL_,12,0xffff0fff)
+#define SET_TXQ4_MTX_Q_TXOP_LIMIT(_VAL_) SET_REG(ADR_TXQ4_MTX_Q_AIFSN,_VAL_,16,0x0000ffff)
+#define SET_TXQ4_MTX_Q_BKF_CNT_FIX(_VAL_) SET_REG(ADR_TXQ4_MTX_Q_BKF_CNT_DBG,_VAL_,0,0xffff0000)
+#define SET_TXQ4_RO_FSM_TXQ(_VAL_) SET_REG(ADR_TXQ4_MTX_Q_HWDBG,_VAL_,0,0xfffffffc)
+#define SET_TXQ4_RO_TRY_CNT(_VAL_) SET_REG(ADR_TXQ4_MTX_Q_HWDBG,_VAL_,4,0xffffff0f)
+#define SET_TXQ4_RO_RATESET_IDX(_VAL_) SET_REG(ADR_TXQ4_MTX_Q_HWDBG,_VAL_,8,0xfffffcff)
+#define SET_TXQ4_RO_AIFS_CNT(_VAL_) SET_REG(ADR_TXQ4_MTX_Q_HWDBG,_VAL_,12,0xffff0fff)
+#define SET_TXQ4_RO_BKF_CNT(_VAL_) SET_REG(ADR_TXQ4_MTX_Q_HWDBG,_VAL_,16,0x0000ffff)
+#define SET_TXQ4_RO_PKTID(_VAL_) SET_REG(ADR_TXQ4_MTX_Q_HWDBG2,_VAL_,0,0xffffff80)
+#define SET_TXQ5_MTX_Q_RND_MODE(_VAL_) SET_REG(ADR_TXQ5_MTX_Q_MISC_EN,_VAL_,0,0xfffffff8)
+#define SET_TXQ5_MTX_Q_MB_NO_RLS(_VAL_) SET_REG(ADR_TXQ5_MTX_Q_MISC_EN,_VAL_,4,0xffffffef)
+#define SET_TXQ5_Q_NULLDATAFRAME_GEN_EN(_VAL_) SET_REG(ADR_TXQ5_MTX_Q_MISC_EN,_VAL_,31,0x7fffffff)
+#define SET_TXQ5_MTX_Q_AIFSN(_VAL_) SET_REG(ADR_TXQ5_MTX_Q_AIFSN,_VAL_,0,0xfffffff0)
+#define SET_TXQ5_MTX_Q_ECWMIN(_VAL_) SET_REG(ADR_TXQ5_MTX_Q_AIFSN,_VAL_,8,0xfffff0ff)
+#define SET_TXQ5_MTX_Q_ECWMAX(_VAL_) SET_REG(ADR_TXQ5_MTX_Q_AIFSN,_VAL_,12,0xffff0fff)
+#define SET_TXQ5_MTX_Q_TXOP_LIMIT(_VAL_) SET_REG(ADR_TXQ5_MTX_Q_AIFSN,_VAL_,16,0x0000ffff)
+#define SET_TXQ5_MTX_Q_BKF_CNT_FIX(_VAL_) SET_REG(ADR_TXQ5_MTX_Q_BKF_CNT_DBG,_VAL_,0,0xffff0000)
+#define SET_TXQ5_RO_FSM_TXQ(_VAL_) SET_REG(ADR_TXQ5_MTX_Q_HWDBG,_VAL_,0,0xfffffffc)
+#define SET_TXQ5_RO_TRY_CNT(_VAL_) SET_REG(ADR_TXQ5_MTX_Q_HWDBG,_VAL_,4,0xffffff0f)
+#define SET_TXQ5_RO_RATESET_IDX(_VAL_) SET_REG(ADR_TXQ5_MTX_Q_HWDBG,_VAL_,8,0xfffffcff)
+#define SET_TXQ5_RO_AIFS_CNT(_VAL_) SET_REG(ADR_TXQ5_MTX_Q_HWDBG,_VAL_,12,0xffff0fff)
+#define SET_TXQ5_RO_BKF_CNT(_VAL_) SET_REG(ADR_TXQ5_MTX_Q_HWDBG,_VAL_,16,0x0000ffff)
+#define SET_TXQ5_RO_PKTID(_VAL_) SET_REG(ADR_TXQ5_MTX_Q_HWDBG2,_VAL_,0,0xffffff80)
+#define SET_MTX_RESPFRM_RATE_EXCEPTION(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_EXCEPTION,_VAL_,0,0xffff0000)
+#define SET_MTX_RESPFRM_RATE_00(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_00,_VAL_,0,0xffff0000)
+#define SET_MTX_RESPFRM_RATE_01(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_01,_VAL_,0,0xffff0000)
+#define SET_MTX_RESPFRM_RATE_02(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_02,_VAL_,0,0xffff0000)
+#define SET_MTX_RESPFRM_RATE_03(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_03,_VAL_,0,0xffff0000)
+#define SET_MTX_RESPFRM_RATE_11(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_11,_VAL_,0,0xffff0000)
+#define SET_MTX_RESPFRM_RATE_12(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_12,_VAL_,0,0xffff0000)
+#define SET_MTX_RESPFRM_RATE_13(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_13,_VAL_,0,0xffff0000)
+#define SET_MTX_RESPFRM_RATE_90_B0(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_90_B0,_VAL_,0,0xffff0000)
+#define SET_MTX_RESPFRM_RATE_91_B1(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_91_B1,_VAL_,0,0xffff0000)
+#define SET_MTX_RESPFRM_RATE_92_B2(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_92_B2,_VAL_,0,0xffff0000)
+#define SET_MTX_RESPFRM_RATE_93_B3(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_93_B3,_VAL_,0,0xffff0000)
+#define SET_MTX_RESPFRM_RATE_94_B4(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_94_B4,_VAL_,0,0xffff0000)
+#define SET_MTX_RESPFRM_RATE_95_B5(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_95_B5,_VAL_,0,0xffff0000)
+#define SET_MTX_RESPFRM_RATE_96_B6(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_96_B6,_VAL_,0,0xffff0000)
+#define SET_MTX_RESPFRM_RATE_97_B7(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_97_B7,_VAL_,0,0xffff0000)
+#define SET_MTX_RESPFRM_RATE_C0_E0(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_C0_E0,_VAL_,0,0xffff0000)
+#define SET_MTX_RESPFRM_RATE_C1_E1(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_C1_E1,_VAL_,0,0xffff0000)
+#define SET_MTX_RESPFRM_RATE_C2_E2(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_C2_E2,_VAL_,0,0xffff0000)
+#define SET_MTX_RESPFRM_RATE_C3_E3(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_C3_E3,_VAL_,0,0xffff0000)
+#define SET_MTX_RESPFRM_RATE_C4_E4(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_C4_E4,_VAL_,0,0xffff0000)
+#define SET_MTX_RESPFRM_RATE_C5_E5(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_C5_E5,_VAL_,0,0xffff0000)
+#define SET_MTX_RESPFRM_RATE_C6_E6(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_C6_E6,_VAL_,0,0xffff0000)
+#define SET_MTX_RESPFRM_RATE_C7_E7(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_C7_E7,_VAL_,0,0xffff0000)
+#define SET_MTX_RESPFRM_RATE_D0_F0(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_D0_F0,_VAL_,0,0xffff0000)
+#define SET_MTX_RESPFRM_RATE_D1_F1(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_D1_F1,_VAL_,0,0xffff0000)
+#define SET_MTX_RESPFRM_RATE_D2_F2(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_D2_F2,_VAL_,0,0xffff0000)
+#define SET_MTX_RESPFRM_RATE_D3_F3(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_D3_F3,_VAL_,0,0xffff0000)
+#define SET_MTX_RESPFRM_RATE_D4_F4(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_D4_F4,_VAL_,0,0xffff0000)
+#define SET_MTX_RESPFRM_RATE_D5_F5(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_D5_F5,_VAL_,0,0xffff0000)
+#define SET_MTX_RESPFRM_RATE_D6_F6(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_D6_F6,_VAL_,0,0xffff0000)
+#define SET_MTX_RESPFRM_RATE_D7_F7(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_D7_F7,_VAL_,0,0xffff0000)
+#define SET_MTX_RESPFRM_RATE_D8_F8(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_D8_F8,_VAL_,0,0xffff0000)
+#define SET_MTX_RESPFRM_RATE_D9_F9(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_D9_F9,_VAL_,0,0xffff0000)
+#define SET_MTX_RESPFRM_RATE_DA_FA(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_DA_FA,_VAL_,0,0xffff0000)
+#define SET_MTX_RESPFRM_RATE_DB_FB(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_DB_FB,_VAL_,0,0xffff0000)
+#define SET_MTX_RESPFRM_RATE_DC_FC(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_DC_FC,_VAL_,0,0xffff0000)
+#define SET_MTX_RESPFRM_RATE_DD_FD(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_DD_FD,_VAL_,0,0xffff0000)
+#define SET_MTX_RESPFRM_RATE_DE_FE(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_DE_FE,_VAL_,0,0xffff0000)
+#define SET_MTX_RESPFRM_RATE_DF_FF(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_DF_FF,_VAL_,0,0xffff0000)
+#define SET_MTX_RESPFRM_INFO_EXCEPTION(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_TABLE_EXCEPTION,_VAL_,0,0xffe00000)
+#define SET_MTX_RESPFRM_INFO_00(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_00,_VAL_,0,0xffe00000)
+#define SET_MTX_RESPFRM_INFO_01(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_01,_VAL_,0,0xffe00000)
+#define SET_MTX_RESPFRM_INFO_02(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_02,_VAL_,0,0xffe00000)
+#define SET_MTX_RESPFRM_INFO_03(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_03,_VAL_,0,0xffe00000)
+#define SET_MTX_RESPFRM_INFO_11(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_11,_VAL_,0,0xffe00000)
+#define SET_MTX_RESPFRM_INFO_12(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_12,_VAL_,0,0xffe00000)
+#define SET_MTX_RESPFRM_INFO_13(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_13,_VAL_,0,0xffe00000)
+#define SET_MTX_RESPFRM_INFO_90_B0(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_90_B0,_VAL_,0,0xffe00000)
+#define SET_MTX_RESPFRM_INFO_91_B1(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_91_B1,_VAL_,0,0xffe00000)
+#define SET_MTX_RESPFRM_INFO_92_B2(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_92_B2,_VAL_,0,0xffe00000)
+#define SET_MTX_RESPFRM_INFO_93_B3(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_93_B3,_VAL_,0,0xffe00000)
+#define SET_MTX_RESPFRM_INFO_94_B4(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_94_B4,_VAL_,0,0xffe00000)
+#define SET_MTX_RESPFRM_INFO_95_B5(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_95_B5,_VAL_,0,0xffe00000)
+#define SET_MTX_RESPFRM_INFO_96_B6(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_96_B6,_VAL_,0,0xffe00000)
+#define SET_MTX_RESPFRM_INFO_97_B7(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_97_B7,_VAL_,0,0xffe00000)
+#define SET_MTX_RESPFRM_INFO_C0(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_C0,_VAL_,0,0xffe00000)
+#define SET_MTX_RESPFRM_INFO_C1(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_C1,_VAL_,0,0xffe00000)
+#define SET_MTX_RESPFRM_INFO_C2(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_C2,_VAL_,0,0xffe00000)
+#define SET_MTX_RESPFRM_INFO_C3(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_C3,_VAL_,0,0xffe00000)
+#define SET_MTX_RESPFRM_INFO_C4(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_C4,_VAL_,0,0xffe00000)
+#define SET_MTX_RESPFRM_INFO_C5(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_C5,_VAL_,0,0xffe00000)
+#define SET_MTX_RESPFRM_INFO_C6(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_C6,_VAL_,0,0xffe00000)
+#define SET_MTX_RESPFRM_INFO_C7(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_C7,_VAL_,0,0xffe00000)
+#define SET_MTX_RESPFRM_INFO_D0(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_D0,_VAL_,0,0xffe00000)
+#define SET_MTX_RESPFRM_INFO_D1(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_D1,_VAL_,0,0xffe00000)
+#define SET_MTX_RESPFRM_INFO_D2(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_D2,_VAL_,0,0xffe00000)
+#define SET_MTX_RESPFRM_INFO_D3(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_D3,_VAL_,0,0xffe00000)
+#define SET_MTX_RESPFRM_INFO_D4(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_D4,_VAL_,0,0xffe00000)
+#define SET_MTX_RESPFRM_INFO_D5(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_D5,_VAL_,0,0xffe00000)
+#define SET_MTX_RESPFRM_INFO_D6(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_D6,_VAL_,0,0xffe00000)
+#define SET_MTX_RESPFRM_INFO_D7(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_D7,_VAL_,0,0xffe00000)
+#define SET_MTX_RESPFRM_INFO_D8(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_D8,_VAL_,0,0xffe00000)
+#define SET_MTX_RESPFRM_INFO_D9(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_D9,_VAL_,0,0xffe00000)
+#define SET_MTX_RESPFRM_INFO_DA(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_DA,_VAL_,0,0xffe00000)
+#define SET_MTX_RESPFRM_INFO_DB(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_DB,_VAL_,0,0xffe00000)
+#define SET_MTX_RESPFRM_INFO_DC(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_DC,_VAL_,0,0xffe00000)
+#define SET_MTX_RESPFRM_INFO_DD(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_DD,_VAL_,0,0xffe00000)
+#define SET_MTX_RESPFRM_INFO_DE(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_DE,_VAL_,0,0xffe00000)
+#define SET_MTX_RESPFRM_INFO_DF(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_DF,_VAL_,0,0xffe00000)
+#define SET_VALID0(_VAL_) SET_REG(ADR_WSID0,_VAL_,0,0xfffffffe)
+#define SET_PEER_QOS_EN0(_VAL_) SET_REG(ADR_WSID0,_VAL_,1,0xfffffffd)
+#define SET_PEER_OP_MODE0(_VAL_) SET_REG(ADR_WSID0,_VAL_,2,0xfffffff3)
+#define SET_PEER_HT_MODE0(_VAL_) SET_REG(ADR_WSID0,_VAL_,4,0xffffffcf)
+#define SET_PEER_MAC0_31_0(_VAL_) SET_REG(ADR_PEER_MAC0_0,_VAL_,0,0x00000000)
+#define SET_PEER_MAC0_47_32(_VAL_) SET_REG(ADR_PEER_MAC0_1,_VAL_,0,0xffff0000)
+#define SET_TX_ACK_POLICY_0_0(_VAL_) SET_REG(ADR_TX_ACK_POLICY_0_0,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_0_0(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_0_0,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_0_1(_VAL_) SET_REG(ADR_TX_ACK_POLICY_0_1,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_0_1(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_0_1,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_0_2(_VAL_) SET_REG(ADR_TX_ACK_POLICY_0_2,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_0_2(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_0_2,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_0_3(_VAL_) SET_REG(ADR_TX_ACK_POLICY_0_3,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_0_3(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_0_3,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_0_4(_VAL_) SET_REG(ADR_TX_ACK_POLICY_0_4,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_0_4(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_0_4,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_0_5(_VAL_) SET_REG(ADR_TX_ACK_POLICY_0_5,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_0_5(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_0_5,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_0_6(_VAL_) SET_REG(ADR_TX_ACK_POLICY_0_6,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_0_6(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_0_6,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_0_7(_VAL_) SET_REG(ADR_TX_ACK_POLICY_0_7,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_0_7(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_0_7,_VAL_,0,0xfffff000)
+#define SET_VALID1(_VAL_) SET_REG(ADR_WSID1,_VAL_,0,0xfffffffe)
+#define SET_PEER_QOS_EN1(_VAL_) SET_REG(ADR_WSID1,_VAL_,1,0xfffffffd)
+#define SET_PEER_OP_MODE1(_VAL_) SET_REG(ADR_WSID1,_VAL_,2,0xfffffff3)
+#define SET_PEER_HT_MODE1(_VAL_) SET_REG(ADR_WSID1,_VAL_,4,0xffffffcf)
+#define SET_PEER_MAC1_31_0(_VAL_) SET_REG(ADR_PEER_MAC1_0,_VAL_,0,0x00000000)
+#define SET_PEER_MAC1_47_32(_VAL_) SET_REG(ADR_PEER_MAC1_1,_VAL_,0,0xffff0000)
+#define SET_TX_ACK_POLICY_1_0(_VAL_) SET_REG(ADR_TX_ACK_POLICY_1_0,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_1_0(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_1_0,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_1_1(_VAL_) SET_REG(ADR_TX_ACK_POLICY_1_1,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_1_1(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_1_1,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_1_2(_VAL_) SET_REG(ADR_TX_ACK_POLICY_1_2,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_1_2(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_1_2,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_1_3(_VAL_) SET_REG(ADR_TX_ACK_POLICY_1_3,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_1_3(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_1_3,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_1_4(_VAL_) SET_REG(ADR_TX_ACK_POLICY_1_4,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_1_4(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_1_4,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_1_5(_VAL_) SET_REG(ADR_TX_ACK_POLICY_1_5,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_1_5(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_1_5,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_1_6(_VAL_) SET_REG(ADR_TX_ACK_POLICY_1_6,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_1_6(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_1_6,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_1_7(_VAL_) SET_REG(ADR_TX_ACK_POLICY_1_7,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_1_7(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_1_7,_VAL_,0,0xfffff000)
+#define SET_CH1_PRI(_VAL_) SET_REG(ADR_PACKET_ID_ALLOCATION_PRIORITY,_VAL_,0,0xfffffffc)
+#define SET_CH2_PRI(_VAL_) SET_REG(ADR_PACKET_ID_ALLOCATION_PRIORITY,_VAL_,8,0xfffffcff)
+#define SET_CH3_PRI(_VAL_) SET_REG(ADR_PACKET_ID_ALLOCATION_PRIORITY,_VAL_,16,0xfffcffff)
+#define SET_RG_MAC_LPBK(_VAL_) SET_REG(ADR_MAC_MODE,_VAL_,0,0xfffffffe)
+#define SET_RG_MAC_M2M(_VAL_) SET_REG(ADR_MAC_MODE,_VAL_,1,0xfffffffd)
+#define SET_RG_PHY_LPBK(_VAL_) SET_REG(ADR_MAC_MODE,_VAL_,2,0xfffffffb)
+#define SET_RG_LPBK_RX_EN(_VAL_) SET_REG(ADR_MAC_MODE,_VAL_,3,0xfffffff7)
+#define SET_EXT_MAC_MODE(_VAL_) SET_REG(ADR_MAC_MODE,_VAL_,4,0xffffffef)
+#define SET_EXT_PHY_MODE(_VAL_) SET_REG(ADR_MAC_MODE,_VAL_,5,0xffffffdf)
+#define SET_HCI_SW_RST(_VAL_) SET_REG(ADR_ALL_SOFTWARE_RESET,_VAL_,0,0xfffffffe)
+#define SET_CO_PROC_SW_RST(_VAL_) SET_REG(ADR_ALL_SOFTWARE_RESET,_VAL_,1,0xfffffffd)
+#define SET_MTX_SW_RST(_VAL_) SET_REG(ADR_ALL_SOFTWARE_RESET,_VAL_,2,0xfffffffb)
+#define SET_MTX_MISC_SW_RST(_VAL_) SET_REG(ADR_ALL_SOFTWARE_RESET,_VAL_,3,0xfffffff7)
+#define SET_MTX_QUE_SW_RST(_VAL_) SET_REG(ADR_ALL_SOFTWARE_RESET,_VAL_,4,0xffffffef)
+#define SET_MTX_CHST_SW_RST(_VAL_) SET_REG(ADR_ALL_SOFTWARE_RESET,_VAL_,5,0xffffffdf)
+#define SET_MTX_BCN_SW_RST(_VAL_) SET_REG(ADR_ALL_SOFTWARE_RESET,_VAL_,6,0xffffffbf)
+#define SET_MRX_SW_RST(_VAL_) SET_REG(ADR_ALL_SOFTWARE_RESET,_VAL_,7,0xffffff7f)
+#define SET_AMPDU_SW_RST(_VAL_) SET_REG(ADR_ALL_SOFTWARE_RESET,_VAL_,8,0xfffffeff)
+#define SET_MMU_SW_RST(_VAL_) SET_REG(ADR_ALL_SOFTWARE_RESET,_VAL_,9,0xfffffdff)
+#define SET_ID_MNG_SW_RST(_VAL_) SET_REG(ADR_ALL_SOFTWARE_RESET,_VAL_,11,0xfffff7ff)
+#define SET_MBOX_SW_RST(_VAL_) SET_REG(ADR_ALL_SOFTWARE_RESET,_VAL_,12,0xffffefff)
+#define SET_SCRT_SW_RST(_VAL_) SET_REG(ADR_ALL_SOFTWARE_RESET,_VAL_,13,0xffffdfff)
+#define SET_MIC_SW_RST(_VAL_) SET_REG(ADR_ALL_SOFTWARE_RESET,_VAL_,14,0xffffbfff)
+#define SET_CO_PROC_ENG_RST(_VAL_) SET_REG(ADR_ENG_SOFTWARE_RESET,_VAL_,1,0xfffffffd)
+#define SET_MTX_MISC_ENG_RST(_VAL_) SET_REG(ADR_ENG_SOFTWARE_RESET,_VAL_,3,0xfffffff7)
+#define SET_MTX_QUE_ENG_RST(_VAL_) SET_REG(ADR_ENG_SOFTWARE_RESET,_VAL_,4,0xffffffef)
+#define SET_MTX_CHST_ENG_RST(_VAL_) SET_REG(ADR_ENG_SOFTWARE_RESET,_VAL_,5,0xffffffdf)
+#define SET_MTX_BCN_ENG_RST(_VAL_) SET_REG(ADR_ENG_SOFTWARE_RESET,_VAL_,6,0xffffffbf)
+#define SET_MRX_ENG_RST(_VAL_) SET_REG(ADR_ENG_SOFTWARE_RESET,_VAL_,7,0xffffff7f)
+#define SET_AMPDU_ENG_RST(_VAL_) SET_REG(ADR_ENG_SOFTWARE_RESET,_VAL_,8,0xfffffeff)
+#define SET_ID_MNG_ENG_RST(_VAL_) SET_REG(ADR_ENG_SOFTWARE_RESET,_VAL_,14,0xffffbfff)
+#define SET_MBOX_ENG_RST(_VAL_) SET_REG(ADR_ENG_SOFTWARE_RESET,_VAL_,15,0xffff7fff)
+#define SET_SCRT_ENG_RST(_VAL_) SET_REG(ADR_ENG_SOFTWARE_RESET,_VAL_,16,0xfffeffff)
+#define SET_MIC_ENG_RST(_VAL_) SET_REG(ADR_ENG_SOFTWARE_RESET,_VAL_,17,0xfffdffff)
+#define SET_CO_PROC_CSR_RST(_VAL_) SET_REG(ADR_CSR_SOFTWARE_RESET,_VAL_,1,0xfffffffd)
+#define SET_MTX_MISC_CSR_RST(_VAL_) SET_REG(ADR_CSR_SOFTWARE_RESET,_VAL_,3,0xfffffff7)
+#define SET_MTX_QUE0_CSR_RST(_VAL_) SET_REG(ADR_CSR_SOFTWARE_RESET,_VAL_,4,0xffffffef)
+#define SET_MTX_QUE1_CSR_RST(_VAL_) SET_REG(ADR_CSR_SOFTWARE_RESET,_VAL_,5,0xffffffdf)
+#define SET_MTX_QUE2_CSR_RST(_VAL_) SET_REG(ADR_CSR_SOFTWARE_RESET,_VAL_,6,0xffffffbf)
+#define SET_MTX_QUE3_CSR_RST(_VAL_) SET_REG(ADR_CSR_SOFTWARE_RESET,_VAL_,7,0xffffff7f)
+#define SET_MTX_QUE4_CSR_RST(_VAL_) SET_REG(ADR_CSR_SOFTWARE_RESET,_VAL_,8,0xfffffeff)
+#define SET_MTX_QUE5_CSR_RST(_VAL_) SET_REG(ADR_CSR_SOFTWARE_RESET,_VAL_,9,0xfffffdff)
+#define SET_MRX_CSR_RST(_VAL_) SET_REG(ADR_CSR_SOFTWARE_RESET,_VAL_,10,0xfffffbff)
+#define SET_AMPDU_CSR_RST(_VAL_) SET_REG(ADR_CSR_SOFTWARE_RESET,_VAL_,11,0xfffff7ff)
+#define SET_SCRT_CSR_RST(_VAL_) SET_REG(ADR_CSR_SOFTWARE_RESET,_VAL_,13,0xffffdfff)
+#define SET_ID_MNG_CSR_RST(_VAL_) SET_REG(ADR_CSR_SOFTWARE_RESET,_VAL_,14,0xffffbfff)
+#define SET_MBOX_CSR_RST(_VAL_) SET_REG(ADR_CSR_SOFTWARE_RESET,_VAL_,15,0xffff7fff)
+#define SET_HCI_CLK_EN(_VAL_) SET_REG(ADR_MAC_CLOCK_ENABLE,_VAL_,0,0xfffffffe)
+#define SET_CO_PROC_CLK_EN(_VAL_) SET_REG(ADR_MAC_CLOCK_ENABLE,_VAL_,1,0xfffffffd)
+#define SET_MTX_MISC_CLK_EN(_VAL_) SET_REG(ADR_MAC_CLOCK_ENABLE,_VAL_,3,0xfffffff7)
+#define SET_MTX_QUE_CLK_EN(_VAL_) SET_REG(ADR_MAC_CLOCK_ENABLE,_VAL_,4,0xffffffef)
+#define SET_MRX_CLK_EN(_VAL_) SET_REG(ADR_MAC_CLOCK_ENABLE,_VAL_,5,0xffffffdf)
+#define SET_AMPDU_CLK_EN(_VAL_) SET_REG(ADR_MAC_CLOCK_ENABLE,_VAL_,6,0xffffffbf)
+#define SET_MMU_CLK_EN(_VAL_) SET_REG(ADR_MAC_CLOCK_ENABLE,_VAL_,7,0xffffff7f)
+#define SET_ID_MNG_CLK_EN(_VAL_) SET_REG(ADR_MAC_CLOCK_ENABLE,_VAL_,9,0xfffffdff)
+#define SET_MBOX_CLK_EN(_VAL_) SET_REG(ADR_MAC_CLOCK_ENABLE,_VAL_,10,0xfffffbff)
+#define SET_SCRT_CLK_EN(_VAL_) SET_REG(ADR_MAC_CLOCK_ENABLE,_VAL_,11,0xfffff7ff)
+#define SET_MIC_CLK_EN(_VAL_) SET_REG(ADR_MAC_CLOCK_ENABLE,_VAL_,12,0xffffefff)
+#define SET_MIB_CLK_EN(_VAL_) SET_REG(ADR_MAC_CLOCK_ENABLE,_VAL_,13,0xffffdfff)
+#define SET_HCI_ENG_CLK_EN(_VAL_) SET_REG(ADR_MAC_ENGINE_CLOCK_ENABLE,_VAL_,0,0xfffffffe)
+#define SET_CO_PROC_ENG_CLK_EN(_VAL_) SET_REG(ADR_MAC_ENGINE_CLOCK_ENABLE,_VAL_,1,0xfffffffd)
+#define SET_MTX_MISC_ENG_CLK_EN(_VAL_) SET_REG(ADR_MAC_ENGINE_CLOCK_ENABLE,_VAL_,3,0xfffffff7)
+#define SET_MTX_QUE_ENG_CLK_EN(_VAL_) SET_REG(ADR_MAC_ENGINE_CLOCK_ENABLE,_VAL_,4,0xffffffef)
+#define SET_MRX_ENG_CLK_EN(_VAL_) SET_REG(ADR_MAC_ENGINE_CLOCK_ENABLE,_VAL_,5,0xffffffdf)
+#define SET_AMPDU_ENG_CLK_EN(_VAL_) SET_REG(ADR_MAC_ENGINE_CLOCK_ENABLE,_VAL_,6,0xffffffbf)
+#define SET_ID_MNG_ENG_CLK_EN(_VAL_) SET_REG(ADR_MAC_ENGINE_CLOCK_ENABLE,_VAL_,12,0xffffefff)
+#define SET_MBOX_ENG_CLK_EN(_VAL_) SET_REG(ADR_MAC_ENGINE_CLOCK_ENABLE,_VAL_,13,0xffffdfff)
+#define SET_SCRT_ENG_CLK_EN(_VAL_) SET_REG(ADR_MAC_ENGINE_CLOCK_ENABLE,_VAL_,14,0xffffbfff)
+#define SET_MIC_ENG_CLK_EN(_VAL_) SET_REG(ADR_MAC_ENGINE_CLOCK_ENABLE,_VAL_,15,0xffff7fff)
+#define SET_CO_PROC_CSR_CLK_EN(_VAL_) SET_REG(ADR_MAC_CSR_CLOCK_ENABLE,_VAL_,1,0xfffffffd)
+#define SET_MRX_CSR_CLK_EN(_VAL_) SET_REG(ADR_MAC_CSR_CLOCK_ENABLE,_VAL_,10,0xfffffbff)
+#define SET_AMPDU_CSR_CLK_EN(_VAL_) SET_REG(ADR_MAC_CSR_CLOCK_ENABLE,_VAL_,11,0xfffff7ff)
+#define SET_SCRT_CSR_CLK_EN(_VAL_) SET_REG(ADR_MAC_CSR_CLOCK_ENABLE,_VAL_,13,0xffffdfff)
+#define SET_ID_MNG_CSR_CLK_EN(_VAL_) SET_REG(ADR_MAC_CSR_CLOCK_ENABLE,_VAL_,14,0xffffbfff)
+#define SET_MBOX_CSR_CLK_EN(_VAL_) SET_REG(ADR_MAC_CSR_CLOCK_ENABLE,_VAL_,15,0xffff7fff)
+#define SET_OP_MODE(_VAL_) SET_REG(ADR_GLBLE_SET,_VAL_,0,0xfffffffc)
+#define SET_HT_MODE(_VAL_) SET_REG(ADR_GLBLE_SET,_VAL_,2,0xfffffff3)
+#define SET_QOS_EN(_VAL_) SET_REG(ADR_GLBLE_SET,_VAL_,4,0xffffffef)
+#define SET_PB_OFFSET(_VAL_) SET_REG(ADR_GLBLE_SET,_VAL_,8,0xffff00ff)
+#define SET_SNIFFER_MODE(_VAL_) SET_REG(ADR_GLBLE_SET,_VAL_,16,0xfffeffff)
+#define SET_DUP_FLT(_VAL_) SET_REG(ADR_GLBLE_SET,_VAL_,17,0xfffdffff)
+#define SET_TX_PKT_RSVD(_VAL_) SET_REG(ADR_GLBLE_SET,_VAL_,18,0xffe3ffff)
+#define SET_AMPDU_SNIFFER(_VAL_) SET_REG(ADR_GLBLE_SET,_VAL_,21,0xffdfffff)
+#define SET_CCMP_H_SEL(_VAL_) SET_REG(ADR_GLBLE_SET,_VAL_,22,0xffbfffff)
+#define SET_LUT_SEL_V2(_VAL_) SET_REG(ADR_GLBLE_SET,_VAL_,23,0xff7fffff)
+#define SET_REASON_TRAP0(_VAL_) SET_REG(ADR_REASON_TRAP0,_VAL_,0,0x00000000)
+#define SET_REASON_TRAP1(_VAL_) SET_REG(ADR_REASON_TRAP1,_VAL_,0,0x00000000)
+#define SET_BSSID_31_0(_VAL_) SET_REG(ADR_BSSID_0,_VAL_,0,0x00000000)
+#define SET_BSSID_47_32(_VAL_) SET_REG(ADR_BSSID_1,_VAL_,0,0xffff0000)
+#define SET_STA_MAC_31_0(_VAL_) SET_REG(ADR_STA_MAC_0,_VAL_,0,0x00000000)
+#define SET_STA_MAC_47_32(_VAL_) SET_REG(ADR_STA_MAC_1,_VAL_,0,0xffff0000)
+#define SET_PAIR_SCRT(_VAL_) SET_REG(ADR_SCRT_SET,_VAL_,0,0xfffffff8)
+#define SET_GRP_SCRT(_VAL_) SET_REG(ADR_SCRT_SET,_VAL_,3,0xffffffc7)
+#define SET_SCRT_PKT_ID(_VAL_) SET_REG(ADR_SCRT_SET,_VAL_,6,0xffffe03f)
+#define SET_SCRT_RPLY_IGNORE(_VAL_) SET_REG(ADR_SCRT_SET,_VAL_,16,0xfffeffff)
+#define SET_SCRT_STATE(_VAL_) SET_REG(ADR_SCRT_STATE,_VAL_,0,0xfffffff0)
+#define SET_BSSID1_31_0(_VAL_) SET_REG(ADR_BSSID1_0,_VAL_,0,0x00000000)
+#define SET_BSSID1_47_32(_VAL_) SET_REG(ADR_BSSID1_1,_VAL_,0,0xffff0000)
+#define SET_STA_MAC1_31_0(_VAL_) SET_REG(ADR_STA_MAC1_0,_VAL_,0,0x00000000)
+#define SET_STA_MAC1_47_32(_VAL_) SET_REG(ADR_STA_MAC1_1,_VAL_,0,0xffff0000)
+#define SET_OP_MODE1(_VAL_) SET_REG(ADR_OP_MODE1,_VAL_,0,0xfffffffc)
+#define SET_COEXIST_EN(_VAL_) SET_REG(ADR_BTCX0,_VAL_,0,0xfffffffe)
+#define SET_WIRE_MODE(_VAL_) SET_REG(ADR_BTCX0,_VAL_,1,0xfffffff1)
+#define SET_WL_RX_PRI(_VAL_) SET_REG(ADR_BTCX0,_VAL_,4,0xffffffef)
+#define SET_WL_TX_PRI(_VAL_) SET_REG(ADR_BTCX0,_VAL_,5,0xffffffdf)
+#define SET_GURAN_USE_EN(_VAL_) SET_REG(ADR_BTCX0,_VAL_,8,0xfffffeff)
+#define SET_GURAN_USE_CTRL(_VAL_) SET_REG(ADR_BTCX0,_VAL_,9,0xfffffdff)
+#define SET_BEACON_TIMEOUT_EN(_VAL_) SET_REG(ADR_BTCX0,_VAL_,10,0xfffffbff)
+#define SET_WLAN_ACT_POL(_VAL_) SET_REG(ADR_BTCX0,_VAL_,11,0xfffff7ff)
+#define SET_DUAL_ANT_EN(_VAL_) SET_REG(ADR_BTCX0,_VAL_,12,0xffffefff)
+#define SET_TRSW_PHY_POL(_VAL_) SET_REG(ADR_BTCX0,_VAL_,16,0xfffeffff)
+#define SET_WIFI_TX_SW_POL(_VAL_) SET_REG(ADR_BTCX0,_VAL_,17,0xfffdffff)
+#define SET_WIFI_RX_SW_POL(_VAL_) SET_REG(ADR_BTCX0,_VAL_,18,0xfffbffff)
+#define SET_BT_SW_POL(_VAL_) SET_REG(ADR_BTCX0,_VAL_,19,0xfff7ffff)
+#define SET_BT_PRI_SMP_TIME(_VAL_) SET_REG(ADR_BTCX1,_VAL_,0,0xffffff00)
+#define SET_BT_STA_SMP_TIME(_VAL_) SET_REG(ADR_BTCX1,_VAL_,8,0xffff00ff)
+#define SET_BEACON_TIMEOUT(_VAL_) SET_REG(ADR_BTCX1,_VAL_,16,0xff00ffff)
+#define SET_WLAN_REMAIN_TIME(_VAL_) SET_REG(ADR_BTCX1,_VAL_,24,0x00ffffff)
+#define SET_SW_MANUAL_EN(_VAL_) SET_REG(ADR_SWITCH_CTL,_VAL_,0,0xfffffffe)
+#define SET_SW_WL_TX(_VAL_) SET_REG(ADR_SWITCH_CTL,_VAL_,1,0xfffffffd)
+#define SET_SW_WL_RX(_VAL_) SET_REG(ADR_SWITCH_CTL,_VAL_,2,0xfffffffb)
+#define SET_SW_BT_TRX(_VAL_) SET_REG(ADR_SWITCH_CTL,_VAL_,3,0xfffffff7)
+#define SET_BT_TXBAR_MANUAL_EN(_VAL_) SET_REG(ADR_SWITCH_CTL,_VAL_,4,0xffffffef)
+#define SET_BT_TXBAR_SET(_VAL_) SET_REG(ADR_SWITCH_CTL,_VAL_,5,0xffffffdf)
+#define SET_BT_BUSY_MANUAL_EN(_VAL_) SET_REG(ADR_SWITCH_CTL,_VAL_,8,0xfffffeff)
+#define SET_BT_BUSY_SET(_VAL_) SET_REG(ADR_SWITCH_CTL,_VAL_,9,0xfffffdff)
+#define SET_SWITCH_2WIRE_EN(_VAL_) SET_REG(ADR_SWITCH_CTL,_VAL_,10,0xfffffbff)
+#define SET_RANDOM_SEED3(_VAL_) SET_REG(ADR_RANDOM_CTL,_VAL_,0,0xffffff00)
+#define SET_RANDOM_SEED2(_VAL_) SET_REG(ADR_RANDOM_CTL,_VAL_,8,0xffff00ff)
+#define SET_RANDOM_SEED1(_VAL_) SET_REG(ADR_RANDOM_CTL,_VAL_,16,0xff00ffff)
+#define SET_BT_TRX_SMP_TIME(_VAL_) SET_REG(ADR_RANDOM_CTL,_VAL_,24,0x00ffffff)
+#define SET_BTCX_INT_MASK(_VAL_) SET_REG(ADR_BTCX_MISC_CTL,_VAL_,0,0xffffffe0)
+#define SET_BTCX_INTR(_VAL_) SET_REG(ADR_BTCX_MISC_CTL,_VAL_,5,0xffffffdf)
+#define SET_AUTO_REMAIN(_VAL_) SET_REG(ADR_BTCX_MISC_CTL,_VAL_,6,0xffffffbf)
+#define SET_PREDE_BT_TX(_VAL_) SET_REG(ADR_BTCX_MISC_CTL,_VAL_,7,0xffffff7f)
+#define SET_G0_PKT_CLS_MIB_EN(_VAL_) SET_REG(ADR_MIB_EN,_VAL_,2,0xfffffffb)
+#define SET_G0_PKT_CLS_ONGOING(_VAL_) SET_REG(ADR_MIB_EN,_VAL_,3,0xfffffff7)
+#define SET_G1_PKT_CLS_MIB_EN(_VAL_) SET_REG(ADR_MIB_EN,_VAL_,4,0xffffffef)
+#define SET_G1_PKT_CLS_ONGOING(_VAL_) SET_REG(ADR_MIB_EN,_VAL_,5,0xffffffdf)
+#define SET_Q0_PKT_CLS_MIB_EN(_VAL_) SET_REG(ADR_MIB_EN,_VAL_,6,0xffffffbf)
+#define SET_Q0_PKT_CLS_ONGOING(_VAL_) SET_REG(ADR_MIB_EN,_VAL_,7,0xffffff7f)
+#define SET_Q1_PKT_CLS_MIB_EN(_VAL_) SET_REG(ADR_MIB_EN,_VAL_,8,0xfffffeff)
+#define SET_Q1_PKT_CLS_ONGOING(_VAL_) SET_REG(ADR_MIB_EN,_VAL_,9,0xfffffdff)
+#define SET_Q2_PKT_CLS_MIB_EN(_VAL_) SET_REG(ADR_MIB_EN,_VAL_,10,0xfffffbff)
+#define SET_Q2_PKT_CLS_ONGOING(_VAL_) SET_REG(ADR_MIB_EN,_VAL_,11,0xfffff7ff)
+#define SET_Q3_PKT_CLS_MIB_EN(_VAL_) SET_REG(ADR_MIB_EN,_VAL_,12,0xffffefff)
+#define SET_Q3_PKT_CLS_ONGOING(_VAL_) SET_REG(ADR_MIB_EN,_VAL_,13,0xffffdfff)
+#define SET_SCRT_PKT_CLS_MIB_EN(_VAL_) SET_REG(ADR_MIB_EN,_VAL_,14,0xffffbfff)
+#define SET_SCRT_PKT_CLS_ONGOING(_VAL_) SET_REG(ADR_MIB_EN,_VAL_,15,0xffff7fff)
+#define SET_MISC_PKT_CLS_MIB_EN(_VAL_) SET_REG(ADR_MIB_EN,_VAL_,16,0xfffeffff)
+#define SET_MISC_PKT_CLS_ONGOING(_VAL_) SET_REG(ADR_MIB_EN,_VAL_,17,0xfffdffff)
+#define SET_MTX_WSID0_SUCC(_VAL_) SET_REG(ADR_MTX_WSID0_SUCC,_VAL_,0,0xffff0000)
+#define SET_MTX_WSID0_FRM(_VAL_) SET_REG(ADR_MTX_WSID0_FRM,_VAL_,0,0xffff0000)
+#define SET_MTX_WSID0_RETRY(_VAL_) SET_REG(ADR_MTX_WSID0_RETRY,_VAL_,0,0xffff0000)
+#define SET_MTX_WSID0_TOTAL(_VAL_) SET_REG(ADR_MTX_WSID0_TOTAL,_VAL_,0,0xffff0000)
+#define SET_MTX_GRP(_VAL_) SET_REG(ADR_MTX_GROUP,_VAL_,0,0xfff00000)
+#define SET_MTX_FAIL(_VAL_) SET_REG(ADR_MTX_FAIL,_VAL_,0,0xffff0000)
+#define SET_MTX_RETRY(_VAL_) SET_REG(ADR_MTX_RETRY,_VAL_,0,0xfff00000)
+#define SET_MTX_MULTI_RETRY(_VAL_) SET_REG(ADR_MTX_MULTI_RETRY,_VAL_,0,0xfff00000)
+#define SET_MTX_RTS_SUCC(_VAL_) SET_REG(ADR_MTX_RTS_SUCCESS,_VAL_,0,0xffff0000)
+#define SET_MTX_RTS_FAIL(_VAL_) SET_REG(ADR_MTX_RTS_FAIL,_VAL_,0,0xffff0000)
+#define SET_MTX_ACK_FAIL(_VAL_) SET_REG(ADR_MTX_ACK_FAIL,_VAL_,0,0xffff0000)
+#define SET_MTX_FRM(_VAL_) SET_REG(ADR_MTX_FRM,_VAL_,0,0xfff00000)
+#define SET_MTX_ACK_TX(_VAL_) SET_REG(ADR_MTX_ACK_TX,_VAL_,0,0xffff0000)
+#define SET_MTX_CTS_TX(_VAL_) SET_REG(ADR_MTX_CTS_TX,_VAL_,0,0xffff0000)
+#define SET_MRX_DUP(_VAL_) SET_REG(ADR_MRX_DUP_FRM,_VAL_,0,0xffff0000)
+#define SET_MRX_FRG(_VAL_) SET_REG(ADR_MRX_FRG_FRM,_VAL_,0,0xfff00000)
+#define SET_MRX_GRP(_VAL_) SET_REG(ADR_MRX_GROUP_FRM,_VAL_,0,0xfff00000)
+#define SET_MRX_FCS_ERR(_VAL_) SET_REG(ADR_MRX_FCS_ERR,_VAL_,0,0xffff0000)
+#define SET_MRX_FCS_SUC(_VAL_) SET_REG(ADR_MRX_FCS_SUCC,_VAL_,0,0xffff0000)
+#define SET_MRX_MISS(_VAL_) SET_REG(ADR_MRX_MISS,_VAL_,0,0xffff0000)
+#define SET_MRX_ALC_FAIL(_VAL_) SET_REG(ADR_MRX_ALC_FAIL,_VAL_,0,0xffff0000)
+#define SET_MRX_DAT_NTF(_VAL_) SET_REG(ADR_MRX_DAT_NTF,_VAL_,0,0xffff0000)
+#define SET_MRX_RTS_NTF(_VAL_) SET_REG(ADR_MRX_RTS_NTF,_VAL_,0,0xffff0000)
+#define SET_MRX_CTS_NTF(_VAL_) SET_REG(ADR_MRX_CTS_NTF,_VAL_,0,0xffff0000)
+#define SET_MRX_ACK_NTF(_VAL_) SET_REG(ADR_MRX_ACK_NTF,_VAL_,0,0xffff0000)
+#define SET_MRX_BA_NTF(_VAL_) SET_REG(ADR_MRX_BA_NTF,_VAL_,0,0xffff0000)
+#define SET_MRX_DATA_NTF(_VAL_) SET_REG(ADR_MRX_DATA_NTF,_VAL_,0,0xffff0000)
+#define SET_MRX_MNG_NTF(_VAL_) SET_REG(ADR_MRX_MNG_NTF,_VAL_,0,0xffff0000)
+#define SET_MRX_DAT_CRC_NTF(_VAL_) SET_REG(ADR_MRX_DAT_CRC_NTF,_VAL_,0,0xffff0000)
+#define SET_MRX_BAR_NTF(_VAL_) SET_REG(ADR_MRX_BAR_NTF,_VAL_,0,0xffff0000)
+#define SET_MRX_MB_MISS(_VAL_) SET_REG(ADR_MRX_MB_MISS,_VAL_,0,0xffff0000)
+#define SET_MRX_NIDLE_MISS(_VAL_) SET_REG(ADR_MRX_NIDLE_MISS,_VAL_,0,0xffff0000)
+#define SET_MRX_CSR_NTF(_VAL_) SET_REG(ADR_MRX_CSR_NTF,_VAL_,0,0xffff0000)
+#define SET_DBG_Q0_SUCC(_VAL_) SET_REG(ADR_DBG_Q0_FRM_SUCCESS,_VAL_,0,0xffff0000)
+#define SET_DBG_Q0_FAIL(_VAL_) SET_REG(ADR_DBG_Q0_FRM_FAIL,_VAL_,0,0xffff0000)
+#define SET_DBG_Q0_ACK_SUCC(_VAL_) SET_REG(ADR_DBG_Q0_ACK_SUCCESS,_VAL_,0,0xffff0000)
+#define SET_DBG_Q0_ACK_FAIL(_VAL_) SET_REG(ADR_DBG_Q0_ACK_FAIL,_VAL_,0,0xffff0000)
+#define SET_DBG_Q1_SUCC(_VAL_) SET_REG(ADR_DBG_Q1_FRM_SUCCESS,_VAL_,0,0xffff0000)
+#define SET_DBG_Q1_FAIL(_VAL_) SET_REG(ADR_DBG_Q1_FRM_FAIL,_VAL_,0,0xffff0000)
+#define SET_DBG_Q1_ACK_SUCC(_VAL_) SET_REG(ADR_DBG_Q1_ACK_SUCCESS,_VAL_,0,0xffff0000)
+#define SET_DBG_Q1_ACK_FAIL(_VAL_) SET_REG(ADR_DBG_Q1_ACK_FAIL,_VAL_,0,0xffff0000)
+#define SET_DBG_Q2_SUCC(_VAL_) SET_REG(ADR_DBG_Q2_FRM_SUCCESS,_VAL_,0,0xffff0000)
+#define SET_DBG_Q2_FAIL(_VAL_) SET_REG(ADR_DBG_Q2_FRM_FAIL,_VAL_,0,0xffff0000)
+#define SET_DBG_Q2_ACK_SUCC(_VAL_) SET_REG(ADR_DBG_Q2_ACK_SUCCESS,_VAL_,0,0xffff0000)
+#define SET_DBG_Q2_ACK_FAIL(_VAL_) SET_REG(ADR_DBG_Q2_ACK_FAIL,_VAL_,0,0xffff0000)
+#define SET_DBG_Q3_SUCC(_VAL_) SET_REG(ADR_DBG_Q3_FRM_SUCCESS,_VAL_,0,0xffff0000)
+#define SET_DBG_Q3_FAIL(_VAL_) SET_REG(ADR_DBG_Q3_FRM_FAIL,_VAL_,0,0xffff0000)
+#define SET_DBG_Q3_ACK_SUCC(_VAL_) SET_REG(ADR_DBG_Q3_ACK_SUCCESS,_VAL_,0,0xffff0000)
+#define SET_DBG_Q3_ACK_FAIL(_VAL_) SET_REG(ADR_DBG_Q3_ACK_FAIL,_VAL_,0,0xffff0000)
+#define SET_SCRT_TKIP_CERR(_VAL_) SET_REG(ADR_MIB_SCRT_TKIP0,_VAL_,0,0xfff00000)
+#define SET_SCRT_TKIP_MIC_ERR(_VAL_) SET_REG(ADR_MIB_SCRT_TKIP1,_VAL_,0,0xfff00000)
+#define SET_SCRT_TKIP_RPLY(_VAL_) SET_REG(ADR_MIB_SCRT_TKIP2,_VAL_,0,0xfff00000)
+#define SET_SCRT_CCMP_RPLY(_VAL_) SET_REG(ADR_MIB_SCRT_CCMP0,_VAL_,0,0xfff00000)
+#define SET_SCRT_CCMP_CERR(_VAL_) SET_REG(ADR_MIB_SCRT_CCMP1,_VAL_,0,0xfff00000)
+#define SET_DBG_LEN_CRC_FAIL(_VAL_) SET_REG(ADR_DBG_LEN_CRC_FAIL,_VAL_,0,0xffff0000)
+#define SET_DBG_LEN_ALC_FAIL(_VAL_) SET_REG(ADR_DBG_LEN_ALC_FAIL,_VAL_,0,0xffff0000)
+#define SET_DBG_AMPDU_PASS(_VAL_) SET_REG(ADR_DBG_AMPDU_PASS,_VAL_,0,0xffff0000)
+#define SET_DBG_AMPDU_FAIL(_VAL_) SET_REG(ADR_DBG_AMPDU_FAIL,_VAL_,0,0xffff0000)
+#define SET_RXID_ALC_CNT_FAIL(_VAL_) SET_REG(ADR_ID_ALC_FAIL1,_VAL_,0,0xffff0000)
+#define SET_RXID_ALC_LEN_FAIL(_VAL_) SET_REG(ADR_ID_ALC_FAIL2,_VAL_,0,0xffff0000)
+#define SET_VALID2(_VAL_) SET_REG(ADR_WSID2,_VAL_,0,0xfffffffe)
+#define SET_PEER_QOS_EN2(_VAL_) SET_REG(ADR_WSID2,_VAL_,1,0xfffffffd)
+#define SET_PEER_OP_MODE2(_VAL_) SET_REG(ADR_WSID2,_VAL_,2,0xfffffff3)
+#define SET_PEER_HT_MODE2(_VAL_) SET_REG(ADR_WSID2,_VAL_,4,0xffffffcf)
+#define SET_PEER_MAC2_31_0(_VAL_) SET_REG(ADR_PEER_MAC2_0,_VAL_,0,0x00000000)
+#define SET_PEER_MAC2_47_32(_VAL_) SET_REG(ADR_PEER_MAC2_1,_VAL_,0,0xffff0000)
+#define SET_TX_ACK_POLICY_2_0(_VAL_) SET_REG(ADR_TX_ACK_POLICY_2_0,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_2_0(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_2_0,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_2_1(_VAL_) SET_REG(ADR_TX_ACK_POLICY_2_1,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_2_1(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_2_1,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_2_2(_VAL_) SET_REG(ADR_TX_ACK_POLICY_2_2,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_2_2(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_2_2,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_2_3(_VAL_) SET_REG(ADR_TX_ACK_POLICY_2_3,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_2_3(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_2_3,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_2_4(_VAL_) SET_REG(ADR_TX_ACK_POLICY_2_4,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_2_4(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_2_4,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_2_5(_VAL_) SET_REG(ADR_TX_ACK_POLICY_2_5,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_2_5(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_2_5,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_2_6(_VAL_) SET_REG(ADR_TX_ACK_POLICY_2_6,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_2_6(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_2_6,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_2_7(_VAL_) SET_REG(ADR_TX_ACK_POLICY_2_7,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_2_7(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_2_7,_VAL_,0,0xfffff000)
+#define SET_VALID3(_VAL_) SET_REG(ADR_WSID3,_VAL_,0,0xfffffffe)
+#define SET_PEER_QOS_EN3(_VAL_) SET_REG(ADR_WSID3,_VAL_,1,0xfffffffd)
+#define SET_PEER_OP_MODE3(_VAL_) SET_REG(ADR_WSID3,_VAL_,2,0xfffffff3)
+#define SET_PEER_HT_MODE3(_VAL_) SET_REG(ADR_WSID3,_VAL_,4,0xffffffcf)
+#define SET_PEER_MAC3_31_0(_VAL_) SET_REG(ADR_PEER_MAC3_0,_VAL_,0,0x00000000)
+#define SET_PEER_MAC3_47_32(_VAL_) SET_REG(ADR_PEER_MAC3_1,_VAL_,0,0xffff0000)
+#define SET_TX_ACK_POLICY_3_0(_VAL_) SET_REG(ADR_TX_ACK_POLICY_3_0,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_3_0(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_3_0,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_3_1(_VAL_) SET_REG(ADR_TX_ACK_POLICY_3_1,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_3_1(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_3_1,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_3_2(_VAL_) SET_REG(ADR_TX_ACK_POLICY_3_2,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_3_2(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_3_2,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_3_3(_VAL_) SET_REG(ADR_TX_ACK_POLICY_3_3,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_3_3(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_3_3,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_3_4(_VAL_) SET_REG(ADR_TX_ACK_POLICY_3_4,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_3_4(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_3_4,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_3_5(_VAL_) SET_REG(ADR_TX_ACK_POLICY_3_5,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_3_5(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_3_5,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_3_6(_VAL_) SET_REG(ADR_TX_ACK_POLICY_3_6,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_3_6(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_3_6,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_3_7(_VAL_) SET_REG(ADR_TX_ACK_POLICY_3_7,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_3_7(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_3_7,_VAL_,0,0xfffff000)
+#define SET_VALID4(_VAL_) SET_REG(ADR_WSID4,_VAL_,0,0xfffffffe)
+#define SET_PEER_QOS_EN4(_VAL_) SET_REG(ADR_WSID4,_VAL_,1,0xfffffffd)
+#define SET_PEER_OP_MODE4(_VAL_) SET_REG(ADR_WSID4,_VAL_,2,0xfffffff3)
+#define SET_PEER_HT_MODE4(_VAL_) SET_REG(ADR_WSID4,_VAL_,4,0xffffffcf)
+#define SET_PEER_MAC4_31_0(_VAL_) SET_REG(ADR_PEER_MAC4_0,_VAL_,0,0x00000000)
+#define SET_PEER_MAC4_47_32(_VAL_) SET_REG(ADR_PEER_MAC4_1,_VAL_,0,0xffff0000)
+#define SET_TX_ACK_POLICY_4_0(_VAL_) SET_REG(ADR_TX_ACK_POLICY_4_0,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_4_0(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_4_0,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_4_1(_VAL_) SET_REG(ADR_TX_ACK_POLICY_4_1,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_4_1(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_4_1,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_4_2(_VAL_) SET_REG(ADR_TX_ACK_POLICY_4_2,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_4_2(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_4_2,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_4_3(_VAL_) SET_REG(ADR_TX_ACK_POLICY_4_3,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_4_3(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_4_3,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_4_4(_VAL_) SET_REG(ADR_TX_ACK_POLICY_4_4,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_4_4(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_4_4,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_4_5(_VAL_) SET_REG(ADR_TX_ACK_POLICY_4_5,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_4_5(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_4_5,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_4_6(_VAL_) SET_REG(ADR_TX_ACK_POLICY_4_6,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_4_6(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_4_6,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_4_7(_VAL_) SET_REG(ADR_TX_ACK_POLICY_4_7,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_4_7(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_4_7,_VAL_,0,0xfffff000)
+#define SET_VALID5(_VAL_) SET_REG(ADR_WSID5,_VAL_,0,0xfffffffe)
+#define SET_PEER_QOS_EN5(_VAL_) SET_REG(ADR_WSID5,_VAL_,1,0xfffffffd)
+#define SET_PEER_OP_MODE5(_VAL_) SET_REG(ADR_WSID5,_VAL_,2,0xfffffff3)
+#define SET_PEER_HT_MODE5(_VAL_) SET_REG(ADR_WSID5,_VAL_,4,0xffffffcf)
+#define SET_PEER_MAC5_31_0(_VAL_) SET_REG(ADR_PEER_MAC5_0,_VAL_,0,0x00000000)
+#define SET_PEER_MAC5_47_32(_VAL_) SET_REG(ADR_PEER_MAC5_1,_VAL_,0,0xffff0000)
+#define SET_TX_ACK_POLICY_5_0(_VAL_) SET_REG(ADR_TX_ACK_POLICY_5_0,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_5_0(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_5_0,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_5_1(_VAL_) SET_REG(ADR_TX_ACK_POLICY_5_1,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_5_1(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_5_1,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_5_2(_VAL_) SET_REG(ADR_TX_ACK_POLICY_5_2,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_5_2(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_5_2,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_5_3(_VAL_) SET_REG(ADR_TX_ACK_POLICY_5_3,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_5_3(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_5_3,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_5_4(_VAL_) SET_REG(ADR_TX_ACK_POLICY_5_4,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_5_4(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_5_4,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_5_5(_VAL_) SET_REG(ADR_TX_ACK_POLICY_5_5,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_5_5(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_5_5,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_5_6(_VAL_) SET_REG(ADR_TX_ACK_POLICY_5_6,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_5_6(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_5_6,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_5_7(_VAL_) SET_REG(ADR_TX_ACK_POLICY_5_7,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_5_7(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_5_7,_VAL_,0,0xfffff000)
+#define SET_VALID6(_VAL_) SET_REG(ADR_WSID6,_VAL_,0,0xfffffffe)
+#define SET_PEER_QOS_EN6(_VAL_) SET_REG(ADR_WSID6,_VAL_,1,0xfffffffd)
+#define SET_PEER_OP_MODE6(_VAL_) SET_REG(ADR_WSID6,_VAL_,2,0xfffffff3)
+#define SET_PEER_HT_MODE6(_VAL_) SET_REG(ADR_WSID6,_VAL_,4,0xffffffcf)
+#define SET_PEER_MAC6_31_0(_VAL_) SET_REG(ADR_PEER_MAC6_0,_VAL_,0,0x00000000)
+#define SET_PEER_MAC6_47_32(_VAL_) SET_REG(ADR_PEER_MAC6_1,_VAL_,0,0xffff0000)
+#define SET_TX_ACK_POLICY_6_0(_VAL_) SET_REG(ADR_TX_ACK_POLICY_6_0,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_6_0(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_6_0,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_6_1(_VAL_) SET_REG(ADR_TX_ACK_POLICY_6_1,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_6_1(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_6_1,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_6_2(_VAL_) SET_REG(ADR_TX_ACK_POLICY_6_2,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_6_2(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_6_2,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_6_3(_VAL_) SET_REG(ADR_TX_ACK_POLICY_6_3,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_6_3(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_6_3,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_6_4(_VAL_) SET_REG(ADR_TX_ACK_POLICY_6_4,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_6_4(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_6_4,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_6_5(_VAL_) SET_REG(ADR_TX_ACK_POLICY_6_5,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_6_5(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_6_5,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_6_6(_VAL_) SET_REG(ADR_TX_ACK_POLICY_6_6,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_6_6(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_6_6,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_6_7(_VAL_) SET_REG(ADR_TX_ACK_POLICY_6_7,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_6_7(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_6_7,_VAL_,0,0xfffff000)
+#define SET_VALID7(_VAL_) SET_REG(ADR_WSID7,_VAL_,0,0xfffffffe)
+#define SET_PEER_QOS_EN7(_VAL_) SET_REG(ADR_WSID7,_VAL_,1,0xfffffffd)
+#define SET_PEER_OP_MODE7(_VAL_) SET_REG(ADR_WSID7,_VAL_,2,0xfffffff3)
+#define SET_PEER_HT_MODE7(_VAL_) SET_REG(ADR_WSID7,_VAL_,4,0xffffffcf)
+#define SET_PEER_MAC7_31_0(_VAL_) SET_REG(ADR_PEER_MAC7_0,_VAL_,0,0x00000000)
+#define SET_PEER_MAC7_47_32(_VAL_) SET_REG(ADR_PEER_MAC7_1,_VAL_,0,0xffff0000)
+#define SET_TX_ACK_POLICY_7_0(_VAL_) SET_REG(ADR_TX_ACK_POLICY_7_0,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_7_0(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_7_0,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_7_1(_VAL_) SET_REG(ADR_TX_ACK_POLICY_7_1,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_7_1(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_7_1,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_7_2(_VAL_) SET_REG(ADR_TX_ACK_POLICY_7_2,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_7_2(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_7_2,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_7_3(_VAL_) SET_REG(ADR_TX_ACK_POLICY_7_3,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_7_3(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_7_3,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_7_4(_VAL_) SET_REG(ADR_TX_ACK_POLICY_7_4,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_7_4(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_7_4,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_7_5(_VAL_) SET_REG(ADR_TX_ACK_POLICY_7_5,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_7_5(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_7_5,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_7_6(_VAL_) SET_REG(ADR_TX_ACK_POLICY_7_6,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_7_6(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_7_6,_VAL_,0,0xfffff000)
+#define SET_TX_ACK_POLICY_7_7(_VAL_) SET_REG(ADR_TX_ACK_POLICY_7_7,_VAL_,0,0xfffffffc)
+#define SET_TX_SEQ_CTRL_7_7(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_7_7,_VAL_,0,0xfffff000)
+#define SET_RG_GEMINIA_HW_PINSEL(_VAL_) SET_REG(ADR_GEMINIA_3_WIRE_REGISTER,_VAL_,0,0xfffffffe)
+#define SET_RG_GEMINIA_HS_3WIRE_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_3_WIRE_REGISTER,_VAL_,1,0xfffffffd)
+#define SET_RG_GEMINIA_MODE_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_3_WIRE_REGISTER,_VAL_,2,0xfffffffb)
+#define SET_RG_GEMINIA_RX_GAIN_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_3_WIRE_REGISTER,_VAL_,3,0xfffffff7)
+#define SET_RG_GEMINIA_TX_GAIN_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_3_WIRE_REGISTER,_VAL_,4,0xffffffef)
+#define SET_RG_GEMINIA_TXGAIN_PHYCTRL(_VAL_) SET_REG(ADR_GEMINIA_3_WIRE_REGISTER,_VAL_,5,0xffffffdf)
+#define SET_RG_GEMINIA_RX_AGC(_VAL_) SET_REG(ADR_GEMINIA_3_WIRE_REGISTER,_VAL_,6,0xffffffbf)
+#define SET_RG_GEMINIA_MODE(_VAL_) SET_REG(ADR_GEMINIA_3_WIRE_REGISTER,_VAL_,8,0xfffff8ff)
+#define SET_RG_GEMINIA_CAL_INDEX(_VAL_) SET_REG(ADR_GEMINIA_3_WIRE_REGISTER,_VAL_,12,0xffff8fff)
+#define SET_RG_GEMINIA_RFG(_VAL_) SET_REG(ADR_GEMINIA_3_WIRE_REGISTER,_VAL_,16,0xfffcffff)
+#define SET_RG_GEMINIA_PGAG(_VAL_) SET_REG(ADR_GEMINIA_3_WIRE_REGISTER,_VAL_,18,0xffc3ffff)
+#define SET_RG_GEMINIA_TX_GAIN(_VAL_) SET_REG(ADR_GEMINIA_3_WIRE_REGISTER,_VAL_,24,0x80ffffff)
+#define SET_RG_GEMINIA_TX_TRSW_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,0,0xfffffffe)
+#define SET_RG_GEMINIA_EN_TX_TRSW(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,1,0xfffffffd)
+#define SET_RG_GEMINIA_RX_LNA_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,2,0xfffffffb)
+#define SET_RG_GEMINIA_EN_RX_LNA(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,3,0xfffffff7)
+#define SET_RG_GEMINIA_RX_MIXER_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,4,0xffffffef)
+#define SET_RG_GEMINIA_EN_RX_MIXER(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,5,0xffffffdf)
+#define SET_RG_GEMINIA_RX_DIV2_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,6,0xffffffbf)
+#define SET_RG_GEMINIA_EN_RX_DIV2(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,7,0xffffff7f)
+#define SET_RG_GEMINIA_RX_LOBUF_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,8,0xfffffeff)
+#define SET_RG_GEMINIA_EN_RX_LOBUF(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,9,0xfffffdff)
+#define SET_RG_GEMINIA_RX_TZ_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,10,0xfffffbff)
+#define SET_RG_GEMINIA_EN_RX_TZ(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,11,0xfffff7ff)
+#define SET_RG_GEMINIA_RX_FILTER_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,12,0xffffefff)
+#define SET_RG_GEMINIA_EN_RX_FILTER(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,13,0xffffdfff)
+#define SET_RG_GEMINIA_RX_ADC_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,14,0xffffbfff)
+#define SET_RG_GEMINIA_EN_RX_ADC(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,15,0xffff7fff)
+#define SET_RG_GEMINIA_RX_RSSI_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,16,0xfffeffff)
+#define SET_RG_GEMINIA_EN_RX_RSSI(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,17,0xfffdffff)
+#define SET_RG_GEMINIA_TX_PA_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,18,0xfffbffff)
+#define SET_RG_GEMINIA_EN_TX_PA(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,19,0xfff7ffff)
+#define SET_RG_GEMINIA_TX_MOD_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,20,0xffefffff)
+#define SET_RG_GEMINIA_EN_TX_MOD(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,21,0xffdfffff)
+#define SET_RG_GEMINIA_TX_DAC_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,22,0xffbfffff)
+#define SET_RG_GEMINIA_EN_TX_DAC(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,23,0xff7fffff)
+#define SET_RG_GEMINIA_TX_DIV2_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,24,0xfeffffff)
+#define SET_RG_GEMINIA_EN_TX_DIV2(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,25,0xfdffffff)
+#define SET_RG_GEMINIA_TX_DIV2_BUF_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,26,0xfbffffff)
+#define SET_RG_GEMINIA_EN_TX_DIV2_BUF(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,27,0xf7ffffff)
+#define SET_RG_GEMINIA_TX_BT_PA_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,28,0xefffffff)
+#define SET_RG_GEMINIA_EN_TX_BT_PA(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,29,0xdfffffff)
+#define SET_RG_GEMINIA_EN_LDO_RX_FE(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,0,0xfffffffe)
+#define SET_RG_GEMINIA_EN_LDO_ABB(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,1,0xfffffffd)
+#define SET_RG_GEMINIA_EN_LDO_ADC(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,2,0xfffffffb)
+#define SET_RG_GEMINIA_EN_LDO_DAC(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,3,0xfffffff7)
+#define SET_RG_GEMINIA_EN_IREF_RX(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,4,0xffffffef)
+#define SET_RG_GEMINIA_TX_DAC_CAL_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,6,0xffffffbf)
+#define SET_RG_GEMINIA_EN_TX_DAC_CAL(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,7,0xffffff7f)
+#define SET_RG_GEMINIA_RX_TZ_OUT_TRISTATE_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,8,0xfffffeff)
+#define SET_RG_GEMINIA_RX_TZ_OUT_TRISTATE(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,9,0xfffffdff)
+#define SET_RG_GEMINIA_TX_SELF_MIXER_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,10,0xfffffbff)
+#define SET_RG_GEMINIA_EN_TX_SELF_MIXER(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,11,0xfffff7ff)
+#define SET_RG_GEMINIA_RX_IQCAL_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,12,0xffffefff)
+#define SET_RG_GEMINIA_EN_RX_IQCAL(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,13,0xffffdfff)
+#define SET_RG_GEMINIA_TX_DPD_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,14,0xffffbfff)
+#define SET_RG_GEMINIA_EN_TX_DPD(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,15,0xffff7fff)
+#define SET_RG_GEMINIA_RXRCCALQ_EN_BYP(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,16,0xfffeffff)
+#define SET_RG_GEMINIA_EN_TX_TSSI(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,17,0xfffdffff)
+#define SET_RG_GEMINIA_EN_SARADC(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,18,0xfffbffff)
+#define SET_RG_GEMINIA_EN_TX_VTOI_2ND(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,19,0xfff7ffff)
+#define SET_RG_GEMINIA_TXLPF_BYPASS(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,20,0xffefffff)
+#define SET_RG_GEMINIA_TX_EN_VOLTAGE_IN(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,21,0xffdfffff)
+#define SET_RG_GEMINIA_EN_TX_DAC_OUT(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,22,0xffbfffff)
+#define SET_RG_GEMINIA_EN_TX_DAC_VOUT(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,23,0xff7fffff)
+#define SET_RG_GEMINIA_RX_ABBOUT_TRI_STATE(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,24,0xfeffffff)
+#define SET_RG_GEMINIA_EN_RX_TESTNODE(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,25,0xfdffffff)
+#define SET_RG_GEMINIA_EN_RX_PADSW(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,26,0xfbffffff)
+#define SET_RG_GEMINIA_LDO_RX_FE_EN_BYP(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,27,0xf7ffffff)
+#define SET_RG_GEMINIA_LDO_RX_ABB_EN_BYP(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,28,0xefffffff)
+#define SET_RG_GEMINIA_LDO_RX_ADC_EN_BYP(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,29,0xdfffffff)
+#define SET_RG_GEMINIA_LDO_TX_DAC_EN_BYP(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,30,0xbfffffff)
+#define SET_RG_GEMINIA_EN_LDO_RX_ADC_IQUP(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,31,0x7fffffff)
+#define SET_RG_GEMINIA_LDO_LEVEL_RX_FE(_VAL_) SET_REG(ADR_GEMINIA_LDO_REGISTER,_VAL_,0,0xfffffff8)
+#define SET_RG_GEMINIA_LDO_LEVEL_ABB(_VAL_) SET_REG(ADR_GEMINIA_LDO_REGISTER,_VAL_,3,0xffffffc7)
+#define SET_RG_GEMINIA_LDO_LEVEL_ADC(_VAL_) SET_REG(ADR_GEMINIA_LDO_REGISTER,_VAL_,6,0xfffffe3f)
+#define SET_RG_GEMINIA_LDO_LEVEL_DAC(_VAL_) SET_REG(ADR_GEMINIA_LDO_REGISTER,_VAL_,9,0xfffff1ff)
+#define SET_RG_GEMINIA_SX_LDO_CP_LEVEL(_VAL_) SET_REG(ADR_GEMINIA_LDO_REGISTER,_VAL_,12,0xffff8fff)
+#define SET_RG_GEMINIA_SX_LDO_LO_LEVEL(_VAL_) SET_REG(ADR_GEMINIA_LDO_REGISTER,_VAL_,15,0xfffc7fff)
+#define SET_RG_GEMINIA_DP_LDO_LEVEL(_VAL_) SET_REG(ADR_GEMINIA_LDO_REGISTER,_VAL_,21,0xff1fffff)
+#define SET_RG_GEMINIA_SX_LDO_VCO_LEVEL(_VAL_) SET_REG(ADR_GEMINIA_LDO_REGISTER,_VAL_,24,0xf8ffffff)
+#define SET_RG_GEMINIA_SX_LDO_DIV_LEVEL(_VAL_) SET_REG(ADR_GEMINIA_LDO_REGISTER,_VAL_,27,0xc7ffffff)
+#define SET_RG_GEMINIA_WF_RX_ABBCTUNEI(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER,_VAL_,0,0xffffffc0)
+#define SET_RG_GEMINIA_WF_RX_ABBCTUNEQ(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER,_VAL_,6,0xfffff03f)
+#define SET_RG_GEMINIA_WF_RX_FILTERI_COARSE(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER,_VAL_,12,0xffffcfff)
+#define SET_RG_GEMINIA_WF_RX_FILTERI1ST(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER,_VAL_,14,0xffff3fff)
+#define SET_RG_GEMINIA_WF_RX_FILTERI2ND(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER,_VAL_,16,0xfffcffff)
+#define SET_RG_GEMINIA_WF_RX_FILTERI3RD(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER,_VAL_,18,0xfff3ffff)
+#define SET_RG_GEMINIA_WF_RX_ABBCFIX(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER,_VAL_,20,0xffefffff)
+#define SET_RG_GEMINIA_WF_RX_ABB_N_MODE(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER,_VAL_,21,0xffdfffff)
+#define SET_RG_GEMINIA_WF_RX_ABB_BT_MODE(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER,_VAL_,22,0xffbfffff)
+#define SET_RG_GEMINIA_WF_RX_ABB_IDIV3(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER,_VAL_,23,0xff7fffff)
+#define SET_RG_GEMINIA_WF_RX_EN_IDACA_COARSE(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER,_VAL_,24,0xfeffffff)
+#define SET_RG_GEMINIA_WF_RX_EN_LOOPA(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER,_VAL_,25,0xfdffffff)
+#define SET_RG_GEMINIA_WF_RX_FILTERVCM(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER,_VAL_,26,0xf3ffffff)
+#define SET_RG_GEMINIA_WF_RX_OUTVCM(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER,_VAL_,28,0xcfffffff)
+#define SET_RG_GEMINIA_BT_RX_ABBCTUNEI(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FILTER_REGISTER,_VAL_,0,0xffffffc0)
+#define SET_RG_GEMINIA_BT_RX_ABBCTUNEQ(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FILTER_REGISTER,_VAL_,6,0xfffff03f)
+#define SET_RG_GEMINIA_BT_RX_FILTERI_COARSE(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FILTER_REGISTER,_VAL_,12,0xffffcfff)
+#define SET_RG_GEMINIA_BT_RX_FILTERI1ST(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FILTER_REGISTER,_VAL_,14,0xffff3fff)
+#define SET_RG_GEMINIA_BT_RX_FILTERI2ND(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FILTER_REGISTER,_VAL_,16,0xfffcffff)
+#define SET_RG_GEMINIA_BT_RX_FILTERI3RD(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FILTER_REGISTER,_VAL_,18,0xfff3ffff)
+#define SET_RG_GEMINIA_BT_RX_ABBCFIX(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FILTER_REGISTER,_VAL_,20,0xffefffff)
+#define SET_RG_GEMINIA_BT_RX_ABB_N_MODE(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FILTER_REGISTER,_VAL_,21,0xffdfffff)
+#define SET_RG_GEMINIA_BT_RX_ABB_BT_MODE(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FILTER_REGISTER,_VAL_,22,0xffbfffff)
+#define SET_RG_GEMINIA_BT_RX_ABB_IDIV3(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FILTER_REGISTER,_VAL_,23,0xff7fffff)
+#define SET_RG_GEMINIA_BT_RX_EN_IDACA_COARSE(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FILTER_REGISTER,_VAL_,24,0xfeffffff)
+#define SET_RG_GEMINIA_BT_RX_EN_LOOPA(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FILTER_REGISTER,_VAL_,25,0xfdffffff)
+#define SET_RG_GEMINIA_BT_RX_FILTERVCM(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FILTER_REGISTER,_VAL_,26,0xf3ffffff)
+#define SET_RG_GEMINIA_BT_RX_OUTVCM(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FILTER_REGISTER,_VAL_,28,0xcfffffff)
+#define SET_RG_GEMINIA_RX_ADCRSSI_VCM(_VAL_) SET_REG(ADR_GEMINIA_RX_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_GEMINIA_RX_REC_LPFCORNER(_VAL_) SET_REG(ADR_GEMINIA_RX_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_GEMINIA_RX_ADCRSSI_CLKSEL(_VAL_) SET_REG(ADR_GEMINIA_RX_REGISTER,_VAL_,4,0xffffffef)
+#define SET_RG_GEMINIA_RSSI_CLOCK_GATING(_VAL_) SET_REG(ADR_GEMINIA_RX_REGISTER,_VAL_,5,0xffffffdf)
+#define SET_RG_GEMINIA_TX_DPDGM_BIAS(_VAL_) SET_REG(ADR_GEMINIA_RX_REGISTER,_VAL_,8,0xfffff0ff)
+#define SET_RG_GEMINIA_TX_DPD_DIV(_VAL_) SET_REG(ADR_GEMINIA_RX_REGISTER,_VAL_,12,0xffff0fff)
+#define SET_RG_GEMINIA_TX_TSSI_BIAS(_VAL_) SET_REG(ADR_GEMINIA_RX_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_GEMINIA_TX_TSSI_DIV(_VAL_) SET_REG(ADR_GEMINIA_RX_REGISTER,_VAL_,19,0xffc7ffff)
+#define SET_RG_GEMINIA_TX_TSSI_TEST(_VAL_) SET_REG(ADR_GEMINIA_RX_REGISTER,_VAL_,22,0xff3fffff)
+#define SET_RG_GEMINIA_TX_TSSI_TESTMODE(_VAL_) SET_REG(ADR_GEMINIA_RX_REGISTER,_VAL_,24,0xfeffffff)
+#define SET_RG_GEMINIA_EN_RX_RSSI_TESTNODE(_VAL_) SET_REG(ADR_GEMINIA_RX_REGISTER,_VAL_,25,0xf1ffffff)
+#define SET_RG_GEMINIA_RX_LNA_TRI_SEL(_VAL_) SET_REG(ADR_GEMINIA_RX_REGISTER,_VAL_,28,0xcfffffff)
+#define SET_RG_GEMINIA_RX_LNA_SETTLE(_VAL_) SET_REG(ADR_GEMINIA_RX_REGISTER,_VAL_,30,0x3fffffff)
+#define SET_RG_GEMINIA_WF_TXPGA_CAPSW(_VAL_) SET_REG(ADR_GEMINIA_WBT_TX_FE_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_GEMINIA_WF_TX_DIV_VSET(_VAL_) SET_REG(ADR_GEMINIA_WBT_TX_FE_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_GEMINIA_WF_TX_LOBUF_VSET(_VAL_) SET_REG(ADR_GEMINIA_WBT_TX_FE_REGISTER,_VAL_,4,0xffffffcf)
+#define SET_RG_GEMINIA_WF_TX_VDDSW(_VAL_) SET_REG(ADR_GEMINIA_WBT_TX_FE_REGISTER,_VAL_,6,0xffffffbf)
+#define SET_RG_GEMINIA_BT_TXPGA_CAPSW(_VAL_) SET_REG(ADR_GEMINIA_WBT_TX_FE_REGISTER,_VAL_,8,0xfffffcff)
+#define SET_RG_GEMINIA_BT_TX_DIV_VSET(_VAL_) SET_REG(ADR_GEMINIA_WBT_TX_FE_REGISTER,_VAL_,10,0xfffff3ff)
+#define SET_RG_GEMINIA_BT_TX_LOBUF_VSET(_VAL_) SET_REG(ADR_GEMINIA_WBT_TX_FE_REGISTER,_VAL_,12,0xffffcfff)
+#define SET_RG_GEMINIA_BT_TX_VDDSW(_VAL_) SET_REG(ADR_GEMINIA_WBT_TX_FE_REGISTER,_VAL_,14,0xffffbfff)
+#define SET_RG_GEMINIA_WF_PACELL_EN(_VAL_) SET_REG(ADR_GEMINIA_WBT_TX_PA_REGISTER,_VAL_,0,0xfffffff8)
+#define SET_RG_GEMINIA_WF_PABIAS_CTRL(_VAL_) SET_REG(ADR_GEMINIA_WBT_TX_PA_REGISTER,_VAL_,4,0xffffff0f)
+#define SET_RG_GEMINIA_WF_TX_PA1_VCAS(_VAL_) SET_REG(ADR_GEMINIA_WBT_TX_PA_REGISTER,_VAL_,8,0xfffff8ff)
+#define SET_RG_GEMINIA_WF_TX_PA2_VCAS(_VAL_) SET_REG(ADR_GEMINIA_WBT_TX_PA_REGISTER,_VAL_,12,0xffff8fff)
+#define SET_RG_GEMINIA_WF_TX_PA3_VCAS(_VAL_) SET_REG(ADR_GEMINIA_WBT_TX_PA_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_GEMINIA_BT_PA_CAPSEL(_VAL_) SET_REG(ADR_GEMINIA_WBT_TX_PA_REGISTER,_VAL_,20,0xff8fffff)
+#define SET_RG_GEMINIA_BT_PABIAS_2X(_VAL_) SET_REG(ADR_GEMINIA_WBT_TX_PA_REGISTER,_VAL_,23,0xff7fffff)
+#define SET_RG_GEMINIA_BT_PABIAS_CTRL(_VAL_) SET_REG(ADR_GEMINIA_WBT_TX_PA_REGISTER,_VAL_,24,0xf0ffffff)
+#define SET_RG_GEMINIA_BT_TX_PA_VCAS(_VAL_) SET_REG(ADR_GEMINIA_WBT_TX_PA_REGISTER,_VAL_,28,0x8fffffff)
+#define SET_RG_GEMINIA_TXPGA_MAIN(_VAL_) SET_REG(ADR_GEMINIA_TX_REGISTER,_VAL_,0,0xffffffc0)
+#define SET_RG_GEMINIA_TXPGA_STEER(_VAL_) SET_REG(ADR_GEMINIA_TX_REGISTER,_VAL_,6,0xfffff03f)
+#define SET_RG_GEMINIA_TXMOD_GMCELL(_VAL_) SET_REG(ADR_GEMINIA_TX_REGISTER,_VAL_,12,0xffffcfff)
+#define SET_RG_GEMINIA_TXLPF_GMCELL(_VAL_) SET_REG(ADR_GEMINIA_TX_REGISTER,_VAL_,14,0xffff3fff)
+#define SET_RG_GEMINIA_WF_TX_GAIN_OFFSET(_VAL_) SET_REG(ADR_GEMINIA_TX_REGISTER,_VAL_,16,0xfff0ffff)
+#define SET_RG_GEMINIA_BT_TX_GAIN_OFFSET(_VAL_) SET_REG(ADR_GEMINIA_TX_REGISTER,_VAL_,20,0xff0fffff)
+#define SET_RG_GEMINIA_TX_VTOI_CURRENT(_VAL_) SET_REG(ADR_GEMINIA_TX_REGISTER,_VAL_,24,0xfcffffff)
+#define SET_RG_GEMINIA_TX_VTOI_GM(_VAL_) SET_REG(ADR_GEMINIA_TX_REGISTER,_VAL_,26,0xf3ffffff)
+#define SET_RG_GEMINIA_TX_VTOI_OPTION(_VAL_) SET_REG(ADR_GEMINIA_TX_REGISTER,_VAL_,28,0xcfffffff)
+#define SET_RG_GEMINIA_TX_VTOI_FS(_VAL_) SET_REG(ADR_GEMINIA_TX_REGISTER,_VAL_,30,0xbfffffff)
+#define SET_RG_GEMINIA_WF_RX_HG_LNA_GC(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_GEMINIA_WF_RX_HG_TZ_GC(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_GEMINIA_WF_RX_HG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER,_VAL_,4,0xffffff0f)
+#define SET_RG_GEMINIA_WF_RX_HG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER,_VAL_,8,0xfffff0ff)
+#define SET_RG_GEMINIA_WF_RX_HG_LNALG_BIAS(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER,_VAL_,12,0xffff0fff)
+#define SET_RG_GEMINIA_WF_RX_HG_TZ_CAP(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_GEMINIA_WF_RX_HG_SQDC(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER,_VAL_,20,0xff8fffff)
+#define SET_RG_GEMINIA_WF_RX_HG_DIV2_CORE(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER,_VAL_,23,0xfe7fffff)
+#define SET_RG_GEMINIA_WF_RX_HG_LOBUF(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER,_VAL_,25,0xf9ffffff)
+#define SET_RG_GEMINIA_WF_RX_HG_TZI(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER,_VAL_,27,0xc7ffffff)
+#define SET_RG_GEMINIA_WF_RX_HG_TZ_VCM(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER,_VAL_,30,0x3fffffff)
+#define SET_RG_GEMINIA_WF_RX_MG_LNA_GC(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_GEMINIA_WF_RX_MG_TZ_GC(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_GEMINIA_WF_RX_MG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER,_VAL_,4,0xffffff0f)
+#define SET_RG_GEMINIA_WF_RX_MG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER,_VAL_,8,0xfffff0ff)
+#define SET_RG_GEMINIA_WF_RX_MG_LNALG_BIAS(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER,_VAL_,12,0xffff0fff)
+#define SET_RG_GEMINIA_WF_RX_MG_TZ_CAP(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_GEMINIA_WF_RX_MG_SQDC(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER,_VAL_,20,0xff8fffff)
+#define SET_RG_GEMINIA_WF_RX_MG_DIV2_CORE(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER,_VAL_,23,0xfe7fffff)
+#define SET_RG_GEMINIA_WF_RX_MG_LOBUF(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER,_VAL_,25,0xf9ffffff)
+#define SET_RG_GEMINIA_WF_RX_MG_TZI(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER,_VAL_,27,0xc7ffffff)
+#define SET_RG_GEMINIA_WF_RX_MG_TZ_VCM(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER,_VAL_,30,0x3fffffff)
+#define SET_RG_GEMINIA_WF_RX_LG_LNA_GC(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_GEMINIA_WF_RX_LG_TZ_GC(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_GEMINIA_WF_RX_LG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER,_VAL_,4,0xffffff0f)
+#define SET_RG_GEMINIA_WF_RX_LG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER,_VAL_,8,0xfffff0ff)
+#define SET_RG_GEMINIA_WF_RX_LG_LNALG_BIAS(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER,_VAL_,12,0xffff0fff)
+#define SET_RG_GEMINIA_WF_RX_LG_TZ_CAP(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_GEMINIA_WF_RX_LG_SQDC(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER,_VAL_,20,0xff8fffff)
+#define SET_RG_GEMINIA_WF_RX_LG_DIV2_CORE(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER,_VAL_,23,0xfe7fffff)
+#define SET_RG_GEMINIA_WF_RX_LG_LOBUF(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER,_VAL_,25,0xf9ffffff)
+#define SET_RG_GEMINIA_WF_RX_LG_TZI(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER,_VAL_,27,0xc7ffffff)
+#define SET_RG_GEMINIA_WF_RX_LG_TZ_VCM(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER,_VAL_,30,0x3fffffff)
+#define SET_RG_GEMINIA_WF_RX_ULG_LNA_GC(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_GEMINIA_WF_RX_ULG_TZ_GC(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_GEMINIA_WF_RX_ULG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER,_VAL_,4,0xffffff0f)
+#define SET_RG_GEMINIA_WF_RX_ULG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER,_VAL_,8,0xfffff0ff)
+#define SET_RG_GEMINIA_WF_RX_ULG_LNALG_BIAS(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER,_VAL_,12,0xffff0fff)
+#define SET_RG_GEMINIA_WF_RX_ULG_TZ_CAP(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_GEMINIA_WF_RX_ULG_SQDC(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER,_VAL_,20,0xff8fffff)
+#define SET_RG_GEMINIA_WF_RX_ULG_DIV2_CORE(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER,_VAL_,23,0xfe7fffff)
+#define SET_RG_GEMINIA_WF_RX_ULG_LOBUF(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER,_VAL_,25,0xf9ffffff)
+#define SET_RG_GEMINIA_WF_RX_ULG_TZI(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER,_VAL_,27,0xc7ffffff)
+#define SET_RG_GEMINIA_WF_RX_ULG_TZ_VCM(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER,_VAL_,30,0x3fffffff)
+#define SET_RG_GEMINIA_BT_RX_HG_LNA_GC(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_HG_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_GEMINIA_BT_RX_HG_TZ_GC(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_HG_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_GEMINIA_BT_RX_HG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_HG_REGISTER,_VAL_,4,0xffffff0f)
+#define SET_RG_GEMINIA_BT_RX_HG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_HG_REGISTER,_VAL_,8,0xfffff0ff)
+#define SET_RG_GEMINIA_BT_RX_HG_LNALG_BIAS(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_HG_REGISTER,_VAL_,12,0xffff0fff)
+#define SET_RG_GEMINIA_BT_RX_HG_TZ_CAP(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_HG_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_GEMINIA_BT_RX_HG_SQDC(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_HG_REGISTER,_VAL_,20,0xff8fffff)
+#define SET_RG_GEMINIA_BT_RX_HG_DIV2_CORE(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_HG_REGISTER,_VAL_,23,0xfe7fffff)
+#define SET_RG_GEMINIA_BT_RX_HG_LOBUF(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_HG_REGISTER,_VAL_,25,0xf9ffffff)
+#define SET_RG_GEMINIA_BT_RX_HG_TZI(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_HG_REGISTER,_VAL_,27,0xc7ffffff)
+#define SET_RG_GEMINIA_BT_RX_HG_TZ_VCM(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_HG_REGISTER,_VAL_,30,0x3fffffff)
+#define SET_RG_GEMINIA_BT_RX_MG_LNA_GC(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_MG_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_GEMINIA_BT_RX_MG_TZ_GC(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_MG_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_GEMINIA_BT_RX_MG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_MG_REGISTER,_VAL_,4,0xffffff0f)
+#define SET_RG_GEMINIA_BT_RX_MG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_MG_REGISTER,_VAL_,8,0xfffff0ff)
+#define SET_RG_GEMINIA_BT_RX_MG_LNALG_BIAS(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_MG_REGISTER,_VAL_,12,0xffff0fff)
+#define SET_RG_GEMINIA_BT_RX_MG_TZ_CAP(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_MG_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_GEMINIA_BT_RX_MG_SQDC(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_MG_REGISTER,_VAL_,20,0xff8fffff)
+#define SET_RG_GEMINIA_BT_RX_MG_DIV2_CORE(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_MG_REGISTER,_VAL_,23,0xfe7fffff)
+#define SET_RG_GEMINIA_BT_RX_MG_LOBUF(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_MG_REGISTER,_VAL_,25,0xf9ffffff)
+#define SET_RG_GEMINIA_BT_RX_MG_TZI(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_MG_REGISTER,_VAL_,27,0xc7ffffff)
+#define SET_RG_GEMINIA_BT_RX_MG_TZ_VCM(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_MG_REGISTER,_VAL_,30,0x3fffffff)
+#define SET_RG_GEMINIA_BT_RX_LG_LNA_GC(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_LG_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_GEMINIA_BT_RX_LG_TZ_GC(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_LG_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_GEMINIA_BT_RX_LG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_LG_REGISTER,_VAL_,4,0xffffff0f)
+#define SET_RG_GEMINIA_BT_RX_LG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_LG_REGISTER,_VAL_,8,0xfffff0ff)
+#define SET_RG_GEMINIA_BT_RX_LG_LNALG_BIAS(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_LG_REGISTER,_VAL_,12,0xffff0fff)
+#define SET_RG_GEMINIA_BT_RX_LG_TZ_CAP(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_LG_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_GEMINIA_BT_RX_LG_SQDC(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_LG_REGISTER,_VAL_,20,0xff8fffff)
+#define SET_RG_GEMINIA_BT_RX_LG_DIV2_CORE(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_LG_REGISTER,_VAL_,23,0xfe7fffff)
+#define SET_RG_GEMINIA_BT_RX_LG_LOBUF(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_LG_REGISTER,_VAL_,25,0xf9ffffff)
+#define SET_RG_GEMINIA_BT_RX_LG_TZI(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_LG_REGISTER,_VAL_,27,0xc7ffffff)
+#define SET_RG_GEMINIA_BT_RX_LG_TZ_VCM(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_LG_REGISTER,_VAL_,30,0x3fffffff)
+#define SET_RG_GEMINIA_BT_RX_ULG_LNA_GC(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_ULG_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_GEMINIA_BT_RX_ULG_TZ_GC(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_ULG_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_GEMINIA_BT_RX_ULG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_ULG_REGISTER,_VAL_,4,0xffffff0f)
+#define SET_RG_GEMINIA_BT_RX_ULG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_ULG_REGISTER,_VAL_,8,0xfffff0ff)
+#define SET_RG_GEMINIA_BT_RX_ULG_LNALG_BIAS(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_ULG_REGISTER,_VAL_,12,0xffff0fff)
+#define SET_RG_GEMINIA_BT_RX_ULG_TZ_CAP(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_ULG_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_GEMINIA_BT_RX_ULG_SQDC(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_ULG_REGISTER,_VAL_,20,0xff8fffff)
+#define SET_RG_GEMINIA_BT_RX_ULG_DIV2_CORE(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_ULG_REGISTER,_VAL_,23,0xfe7fffff)
+#define SET_RG_GEMINIA_BT_RX_ULG_LOBUF(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_ULG_REGISTER,_VAL_,25,0xf9ffffff)
+#define SET_RG_GEMINIA_BT_RX_ULG_TZI(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_ULG_REGISTER,_VAL_,27,0xc7ffffff)
+#define SET_RG_GEMINIA_BT_RX_ULG_TZ_VCM(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_ULG_REGISTER,_VAL_,30,0x3fffffff)
+#define SET_RG_GEMINIA_RX_ADC_CLKSEL(_VAL_) SET_REG(ADR_GEMINIA_RX_ADC_REGISTER,_VAL_,0,0xfffffffe)
+#define SET_RG_GEMINIA_RX_ADC_DNLEN(_VAL_) SET_REG(ADR_GEMINIA_RX_ADC_REGISTER,_VAL_,1,0xfffffffd)
+#define SET_RG_GEMINIA_RX_ADC_METAEN(_VAL_) SET_REG(ADR_GEMINIA_RX_ADC_REGISTER,_VAL_,2,0xfffffffb)
+#define SET_RG_GEMINIA_RX_ADC_TFLAG(_VAL_) SET_REG(ADR_GEMINIA_RX_ADC_REGISTER,_VAL_,3,0xfffffff7)
+#define SET_RG_GEMINIA_RX_ADC_TSEL(_VAL_) SET_REG(ADR_GEMINIA_RX_ADC_REGISTER,_VAL_,4,0xffffff0f)
+#define SET_RG_GEMINIA_WF_RX_ADC_ICMP(_VAL_) SET_REG(ADR_GEMINIA_RX_ADC_REGISTER,_VAL_,8,0xfffffcff)
+#define SET_RG_GEMINIA_WF_RX_ADC_VCMI(_VAL_) SET_REG(ADR_GEMINIA_RX_ADC_REGISTER,_VAL_,10,0xfffff3ff)
+#define SET_RG_GEMINIA_WF_RX_ADC_CLOAD(_VAL_) SET_REG(ADR_GEMINIA_RX_ADC_REGISTER,_VAL_,12,0xffffcfff)
+#define SET_RG_GEMINIA_BT_RX_ADC_ICMP(_VAL_) SET_REG(ADR_GEMINIA_RX_ADC_REGISTER,_VAL_,16,0xfffcffff)
+#define SET_RG_GEMINIA_BT_RX_ADC_VCMI(_VAL_) SET_REG(ADR_GEMINIA_RX_ADC_REGISTER,_VAL_,18,0xfff3ffff)
+#define SET_RG_GEMINIA_BT_RX_ADC_CLOAD(_VAL_) SET_REG(ADR_GEMINIA_RX_ADC_REGISTER,_VAL_,20,0xffcfffff)
+#define SET_RG_GEMINIA_SARADC_VRSEL(_VAL_) SET_REG(ADR_GEMINIA_RX_ADC_REGISTER,_VAL_,24,0xfcffffff)
+#define SET_RG_GEMINIA_EN_SAR_TEST(_VAL_) SET_REG(ADR_GEMINIA_RX_ADC_REGISTER,_VAL_,26,0xf3ffffff)
+#define SET_RG_GEMINIA_SARADC_THERMAL(_VAL_) SET_REG(ADR_GEMINIA_RX_ADC_REGISTER,_VAL_,28,0xefffffff)
+#define SET_RG_GEMINIA_SARADC_TSSI(_VAL_) SET_REG(ADR_GEMINIA_RX_ADC_REGISTER,_VAL_,29,0xdfffffff)
+#define SET_RG_GEMINIA_CLK_SAR_SEL(_VAL_) SET_REG(ADR_GEMINIA_RX_ADC_REGISTER,_VAL_,30,0x3fffffff)
+#define SET_RG_GEMINIA_WF_TX_DACI1ST(_VAL_) SET_REG(ADR_GEMINIA_WIFI_TX_DAC_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_GEMINIA_WF_TX_DACLPF_ICOARSE(_VAL_) SET_REG(ADR_GEMINIA_WIFI_TX_DAC_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_GEMINIA_WF_TX_DACLPF_IFINE(_VAL_) SET_REG(ADR_GEMINIA_WIFI_TX_DAC_REGISTER,_VAL_,4,0xffffffcf)
+#define SET_RG_GEMINIA_WF_TX_DACLPF_VCM(_VAL_) SET_REG(ADR_GEMINIA_WIFI_TX_DAC_REGISTER,_VAL_,6,0xffffff3f)
+#define SET_RG_GEMINIA_WF_TX_DAC_IBIAS(_VAL_) SET_REG(ADR_GEMINIA_WIFI_TX_DAC_REGISTER,_VAL_,8,0xfffffcff)
+#define SET_RG_GEMINIA_WF_TX_DAC_IATTN(_VAL_) SET_REG(ADR_GEMINIA_WIFI_TX_DAC_REGISTER,_VAL_,10,0xfffffbff)
+#define SET_RG_GEMINIA_WF_TXLPF_BOOSTI(_VAL_) SET_REG(ADR_GEMINIA_WIFI_TX_DAC_REGISTER,_VAL_,11,0xfffff7ff)
+#define SET_RG_GEMINIA_WF_TX_DAC_RCAL(_VAL_) SET_REG(ADR_GEMINIA_WIFI_TX_DAC_REGISTER,_VAL_,12,0xffffcfff)
+#define SET_RG_GEMINIA_WF_TX_DAC_CKEDGE_SEL(_VAL_) SET_REG(ADR_GEMINIA_WIFI_TX_DAC_REGISTER,_VAL_,14,0xffffbfff)
+#define SET_RG_GEMINIA_WF_TX_DAC_OS(_VAL_) SET_REG(ADR_GEMINIA_WIFI_TX_DAC_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_GEMINIA_WF_TX_DAC_IOFFSET(_VAL_) SET_REG(ADR_GEMINIA_WIFI_TX_DAC_REGISTER,_VAL_,20,0xff0fffff)
+#define SET_RG_GEMINIA_WF_TX_DAC_QOFFSET(_VAL_) SET_REG(ADR_GEMINIA_WIFI_TX_DAC_REGISTER,_VAL_,24,0xf0ffffff)
+#define SET_RG_GEMINIA_TX_DAC_TSEL(_VAL_) SET_REG(ADR_GEMINIA_WIFI_TX_DAC_REGISTER,_VAL_,28,0x0fffffff)
+#define SET_RG_GEMINIA_BT_TX_DACI1ST(_VAL_) SET_REG(ADR_GEMINIA_BT_TX_DAC_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_GEMINIA_BT_TX_DACLPF_ICOARSE(_VAL_) SET_REG(ADR_GEMINIA_BT_TX_DAC_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_GEMINIA_BT_TX_DACLPF_IFINE(_VAL_) SET_REG(ADR_GEMINIA_BT_TX_DAC_REGISTER,_VAL_,4,0xffffffcf)
+#define SET_RG_GEMINIA_BT_TX_DACLPF_VCM(_VAL_) SET_REG(ADR_GEMINIA_BT_TX_DAC_REGISTER,_VAL_,6,0xffffff3f)
+#define SET_RG_GEMINIA_BT_TX_DAC_IBIAS(_VAL_) SET_REG(ADR_GEMINIA_BT_TX_DAC_REGISTER,_VAL_,8,0xfffffcff)
+#define SET_RG_GEMINIA_BT_TX_DAC_IATTN(_VAL_) SET_REG(ADR_GEMINIA_BT_TX_DAC_REGISTER,_VAL_,10,0xfffffbff)
+#define SET_RG_GEMINIA_BT_TXLPF_BOOSTI(_VAL_) SET_REG(ADR_GEMINIA_BT_TX_DAC_REGISTER,_VAL_,11,0xfffff7ff)
+#define SET_RG_GEMINIA_BT_TX_DAC_RCAL(_VAL_) SET_REG(ADR_GEMINIA_BT_TX_DAC_REGISTER,_VAL_,12,0xffffcfff)
+#define SET_RG_GEMINIA_BT_TX_DAC_CKEDGE_SEL(_VAL_) SET_REG(ADR_GEMINIA_BT_TX_DAC_REGISTER,_VAL_,14,0xffffbfff)
+#define SET_RG_GEMINIA_BT_TX_DAC_OS(_VAL_) SET_REG(ADR_GEMINIA_BT_TX_DAC_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_GEMINIA_BT_TX_DAC_IOFFSET(_VAL_) SET_REG(ADR_GEMINIA_BT_TX_DAC_REGISTER,_VAL_,20,0xff0fffff)
+#define SET_RG_GEMINIA_BT_TX_DAC_QOFFSET(_VAL_) SET_REG(ADR_GEMINIA_BT_TX_DAC_REGISTER,_VAL_,24,0xf0ffffff)
+#define SET_RG_GEMINIA_SX_EN_MAN(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,0,0xfffffffe)
+#define SET_RG_GEMINIA_SX_EN(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,1,0xfffffffd)
+#define SET_RG_GEMINIA_EN_SX_CP_MAN(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,2,0xfffffffb)
+#define SET_RG_GEMINIA_EN_SX_CP(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,3,0xfffffff7)
+#define SET_RG_GEMINIA_EN_SX_DIV_MAN(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,4,0xffffffef)
+#define SET_RG_GEMINIA_EN_SX_DIV(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,5,0xffffffdf)
+#define SET_RG_GEMINIA_EN_SX_VCO_MAN(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,6,0xffffffbf)
+#define SET_RG_GEMINIA_EN_SX_VCO(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,7,0xffffff7f)
+#define SET_RG_GEMINIA_SX_PFD_RST_MAN(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,8,0xfffffeff)
+#define SET_RG_GEMINIA_SX_PFD_RST(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,9,0xfffffdff)
+#define SET_RG_GEMINIA_SX_UOP_MAN(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,10,0xfffffbff)
+#define SET_RG_GEMINIA_SX_UOP_EN(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,11,0xfffff7ff)
+#define SET_RG_GEMINIA_EN_VCOBF_TXMB_MAN(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,12,0xffffefff)
+#define SET_RG_GEMINIA_EN_VCOBF_TXMB(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,13,0xffffdfff)
+#define SET_RG_GEMINIA_EN_VCOBF_TXOB_MAN(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,14,0xffffbfff)
+#define SET_RG_GEMINIA_EN_VCOBF_TXOB(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,15,0xffff7fff)
+#define SET_RG_GEMINIA_EN_VCOBF_RXMB_MAN(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,16,0xfffeffff)
+#define SET_RG_GEMINIA_EN_VCOBF_RXMB(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,17,0xfffdffff)
+#define SET_RG_GEMINIA_EN_VCOBF_RXOB_MAN(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,18,0xfffbffff)
+#define SET_RG_GEMINIA_EN_VCOBF_RXOB(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,19,0xfff7ffff)
+#define SET_RG_GEMINIA_EN_VCOBF_DIVCK_MAN(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,20,0xffefffff)
+#define SET_RG_GEMINIA_EN_VCOBF_DIVCK(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,21,0xffdfffff)
+#define SET_RG_GEMINIA_SX_SBCAL_DIS(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,23,0xff7fffff)
+#define SET_RG_GEMINIA_SX_SBCAL_AW(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,24,0xfeffffff)
+#define SET_RG_GEMINIA_SX_AAC_DIS(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,26,0xfbffffff)
+#define SET_RG_GEMINIA_SX_TTL_DIS(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,27,0xf7ffffff)
+#define SET_RG_GEMINIA_SX_CAL_INIT(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,29,0x1fffffff)
+#define SET_RG_GEMINIA_EN_SX_LDO_MAN(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,0,0xfffffffe)
+#define SET_RG_GEMINIA_EN_LDO_CP(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,1,0xfffffffd)
+#define SET_RG_GEMINIA_EN_LDO_DIV(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,2,0xfffffffb)
+#define SET_RG_GEMINIA_EN_LDO_LO(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,3,0xfffffff7)
+#define SET_RG_GEMINIA_EN_LDO_VCO(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,4,0xffffffef)
+#define SET_RG_GEMINIA_EN_LDO_CP_BYP(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,6,0xffffffbf)
+#define SET_RG_GEMINIA_EN_LDO_DIV_BYP(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,7,0xffffff7f)
+#define SET_RG_GEMINIA_EN_LDO_LO_BYP(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,8,0xfffffeff)
+#define SET_RG_GEMINIA_EN_LDO_VCO_PSW(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,9,0xfffffdff)
+#define SET_RG_GEMINIA_EN_LDO_VCO_VDD33(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,10,0xfffffbff)
+#define SET_RG_GEMINIA_EN_LDO_CP_IQUP(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,11,0xfffff7ff)
+#define SET_RG_GEMINIA_EN_LDO_DIV_IQUP(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,12,0xffffefff)
+#define SET_RG_GEMINIA_EN_LDO_LO_IQUP(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,13,0xffffdfff)
+#define SET_RG_GEMINIA_EN_LDO_VCO_IQUP(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,14,0xffffbfff)
+#define SET_RG_GEMINIA_SX_LDO_FCOFFT(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,19,0xffc7ffff)
+#define SET_RG_GEMINIA_LDO_CP_FC_MAN(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,22,0xffbfffff)
+#define SET_RG_GEMINIA_LDO_CP_FC(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,23,0xff7fffff)
+#define SET_RG_GEMINIA_LDO_DIV_FC_MAN(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,24,0xfeffffff)
+#define SET_RG_GEMINIA_LDO_DIV_FC(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,25,0xfdffffff)
+#define SET_RG_GEMINIA_LDO_LO_FC_MAN(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,26,0xfbffffff)
+#define SET_RG_GEMINIA_LDO_LO_FC(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,27,0xf7ffffff)
+#define SET_RG_GEMINIA_LDO_VCO_FC_MAN(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,28,0xefffffff)
+#define SET_RG_GEMINIA_LDO_VCO_FC(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,29,0xdfffffff)
+#define SET_RG_GEMINIA_LDO_VCO_RCF(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,30,0x3fffffff)
+#define SET_RG_GEMINIA_SX_RFCTRL_F(_VAL_) SET_REG(ADR_GEMINIA_SYN_FRACTIONAL_AND_INTEGER_8BITS,_VAL_,0,0xff000000)
+#define SET_RG_GEMINIA_SX_RFCTRL_CH_7_0(_VAL_) SET_REG(ADR_GEMINIA_SYN_FRACTIONAL_AND_INTEGER_8BITS,_VAL_,24,0x00ffffff)
+#define SET_RG_GEMINIA_SX_RFCTRL_CH_10_8(_VAL_) SET_REG(ADR_GEMINIA_SYN_REGISTER_INT3BIT_CH_TABLE,_VAL_,0,0xfffffff8)
+#define SET_RG_GEMINIA_SX_RFCH_MAP_EN(_VAL_) SET_REG(ADR_GEMINIA_SYN_REGISTER_INT3BIT_CH_TABLE,_VAL_,4,0xffffffef)
+#define SET_RG_GEMINIA_SX_XTAL_FREQ(_VAL_) SET_REG(ADR_GEMINIA_SYN_REGISTER_INT3BIT_CH_TABLE,_VAL_,5,0xffffff9f)
+#define SET_RG_GEMINIA_SX_FREF_DOUB(_VAL_) SET_REG(ADR_GEMINIA_SYN_REGISTER_INT3BIT_CH_TABLE,_VAL_,7,0xffffff7f)
+#define SET_RG_GEMINIA_SX_BTRX_SIDE(_VAL_) SET_REG(ADR_GEMINIA_SYN_REGISTER_INT3BIT_CH_TABLE,_VAL_,8,0xfffffeff)
+#define SET_RG_GEMINIA_SX_LO_TIMES(_VAL_) SET_REG(ADR_GEMINIA_SYN_REGISTER_INT3BIT_CH_TABLE,_VAL_,9,0xfffffdff)
+#define SET_RG_GEMINIA_SX_CHANNEL(_VAL_) SET_REG(ADR_GEMINIA_SYN_REGISTER_INT3BIT_CH_TABLE,_VAL_,11,0xfff807ff)
+#define SET_RG_GEMINIA_SX_CP_ISEL_BT(_VAL_) SET_REG(ADR_GEMINIA_SYN_PFD_CHP_,_VAL_,0,0xfffffff0)
+#define SET_RG_GEMINIA_SX_CP_ISEL50U_BT(_VAL_) SET_REG(ADR_GEMINIA_SYN_PFD_CHP_,_VAL_,4,0xffffffef)
+#define SET_RG_GEMINIA_SX_CP_KP_DOUB_BT(_VAL_) SET_REG(ADR_GEMINIA_SYN_PFD_CHP_,_VAL_,5,0xffffffdf)
+#define SET_RG_GEMINIA_SX_CP_ISEL_WF(_VAL_) SET_REG(ADR_GEMINIA_SYN_PFD_CHP_,_VAL_,7,0xfffff87f)
+#define SET_RG_GEMINIA_SX_CP_ISEL50U_WF(_VAL_) SET_REG(ADR_GEMINIA_SYN_PFD_CHP_,_VAL_,11,0xfffff7ff)
+#define SET_RG_GEMINIA_SX_CP_KP_DOUB_WF(_VAL_) SET_REG(ADR_GEMINIA_SYN_PFD_CHP_,_VAL_,12,0xffffefff)
+#define SET_RG_GEMINIA_SX_CP_IOST_POL(_VAL_) SET_REG(ADR_GEMINIA_SYN_PFD_CHP_,_VAL_,15,0xffff7fff)
+#define SET_RG_GEMINIA_SX_CP_IOST(_VAL_) SET_REG(ADR_GEMINIA_SYN_PFD_CHP_,_VAL_,16,0xfff8ffff)
+#define SET_RG_GEMINIA_SX_PFD_SEL(_VAL_) SET_REG(ADR_GEMINIA_SYN_PFD_CHP_,_VAL_,22,0xffbfffff)
+#define SET_RG_GEMINIA_SX_PFD_SET(_VAL_) SET_REG(ADR_GEMINIA_SYN_PFD_CHP_,_VAL_,23,0xff7fffff)
+#define SET_RG_GEMINIA_SX_PFD_SET1(_VAL_) SET_REG(ADR_GEMINIA_SYN_PFD_CHP_,_VAL_,24,0xfeffffff)
+#define SET_RG_GEMINIA_SX_PFD_SET2(_VAL_) SET_REG(ADR_GEMINIA_SYN_PFD_CHP_,_VAL_,25,0xfdffffff)
+#define SET_RG_GEMINIA_SX_PFD_TRUP(_VAL_) SET_REG(ADR_GEMINIA_SYN_PFD_CHP_,_VAL_,28,0xefffffff)
+#define SET_RG_GEMINIA_SX_PFD_TRDN(_VAL_) SET_REG(ADR_GEMINIA_SYN_PFD_CHP_,_VAL_,29,0xdfffffff)
+#define SET_RG_GEMINIA_SX_PFD_TLSEL(_VAL_) SET_REG(ADR_GEMINIA_SYN_PFD_CHP_,_VAL_,30,0xbfffffff)
+#define SET_RG_GEMINIA_SX_LPF_C1_BT(_VAL_) SET_REG(ADR_GEMINIA_SYN_LPF,_VAL_,0,0xfffffff0)
+#define SET_RG_GEMINIA_SX_LPF_C2_BT(_VAL_) SET_REG(ADR_GEMINIA_SYN_LPF,_VAL_,4,0xffffff0f)
+#define SET_RG_GEMINIA_SX_LPF_C3_BT(_VAL_) SET_REG(ADR_GEMINIA_SYN_LPF,_VAL_,8,0xfffffeff)
+#define SET_RG_GEMINIA_SX_LPF_R2_BT(_VAL_) SET_REG(ADR_GEMINIA_SYN_LPF,_VAL_,9,0xffffe1ff)
+#define SET_RG_GEMINIA_SX_LPF_R3_BT(_VAL_) SET_REG(ADR_GEMINIA_SYN_LPF,_VAL_,13,0xffff1fff)
+#define SET_RG_GEMINIA_SX_LPF_C1_WF(_VAL_) SET_REG(ADR_GEMINIA_SYN_LPF,_VAL_,16,0xfff0ffff)
+#define SET_RG_GEMINIA_SX_LPF_C2_WF(_VAL_) SET_REG(ADR_GEMINIA_SYN_LPF,_VAL_,20,0xff0fffff)
+#define SET_RG_GEMINIA_SX_LPF_C3_WF(_VAL_) SET_REG(ADR_GEMINIA_SYN_LPF,_VAL_,24,0xfeffffff)
+#define SET_RG_GEMINIA_SX_LPF_R2_WF(_VAL_) SET_REG(ADR_GEMINIA_SYN_LPF,_VAL_,25,0xe1ffffff)
+#define SET_RG_GEMINIA_SX_LPF_R3_WF(_VAL_) SET_REG(ADR_GEMINIA_SYN_LPF,_VAL_,29,0x1fffffff)
+#define SET_RG_GEMINIA_SX_VCO_ISEL_MAN(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCO,_VAL_,0,0xfffffffe)
+#define SET_RG_GEMINIA_SX_VCO_ISEL_BT(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCO,_VAL_,1,0xffffffe1)
+#define SET_RG_GEMINIA_SX_VCO_LPM_BT(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCO,_VAL_,5,0xffffffdf)
+#define SET_RG_GEMINIA_SX_VCO_VCCBSEL_BT(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCO,_VAL_,6,0xfffffe3f)
+#define SET_RG_GEMINIA_SX_VCO_KVDOUB_BT(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCO,_VAL_,9,0xfffffdff)
+#define SET_RG_GEMINIA_SX_VCO_ISEL_WF(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCO,_VAL_,10,0xffffc3ff)
+#define SET_RG_GEMINIA_SX_VCO_LPM_WF(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCO,_VAL_,14,0xffffbfff)
+#define SET_RG_GEMINIA_SX_VCO_VCCBSEL_WF(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCO,_VAL_,15,0xfffc7fff)
+#define SET_RG_GEMINIA_SX_VCO_KVDOUB_WF(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCO,_VAL_,18,0xfffbffff)
+#define SET_RG_GEMINIA_SX_VCO_VARBSEL(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCO,_VAL_,21,0xff9fffff)
+#define SET_RG_GEMINIA_SX_VCO_RTAIL_SHIFT(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCO,_VAL_,23,0xff7fffff)
+#define SET_RG_GEMINIA_SX_VCO_CS_AWH(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCO,_VAL_,24,0xfeffffff)
+#define SET_RG_GEMINIA_VOBF_TXMBSEL_BT(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCOBF,_VAL_,0,0xfffffffc)
+#define SET_RG_GEMINIA_VOBF_TXOBSEL_BT(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCOBF,_VAL_,2,0xfffffff3)
+#define SET_RG_GEMINIA_VOBF_RXMBSEL_BT(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCOBF,_VAL_,4,0xffffffcf)
+#define SET_RG_GEMINIA_VOBF_RXOBSEL_BT(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCOBF,_VAL_,6,0xffffff3f)
+#define SET_RG_GEMINIA_VOBF_TXMBSEL_WF(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCOBF,_VAL_,10,0xfffff3ff)
+#define SET_RG_GEMINIA_VOBF_TXOBSEL_WF(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCOBF,_VAL_,12,0xffffcfff)
+#define SET_RG_GEMINIA_VOBF_RXMBSEL_WF(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCOBF,_VAL_,14,0xffff3fff)
+#define SET_RG_GEMINIA_VOBF_RXOBSEL_WF(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCOBF,_VAL_,16,0xfffcffff)
+#define SET_RG_GEMINIA_VOBF_DIVBFSEL(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCOBF,_VAL_,19,0xfff7ffff)
+#define SET_RG_GEMINIA_SX_VCO_TXOB_AW(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCOBF,_VAL_,20,0xffefffff)
+#define SET_RG_GEMINIA_SX_VCO_RXOB_AW(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCOBF,_VAL_,21,0xffdfffff)
+#define SET_RG_GEMINIA_VOBF_CAPIMB_POL(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCOBF,_VAL_,26,0xfbffffff)
+#define SET_RG_GEMINIA_VOBF_CAPIMB(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCOBF,_VAL_,27,0xc7ffffff)
+#define SET_RG_GEMINIA_EN_SX_VCOMON(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCOBF,_VAL_,31,0x7fffffff)
+#define SET_RG_GEMINIA_SX_DIV_PREVDD(_VAL_) SET_REG(ADR_GEMINIA_SYN_DIV_SDM,_VAL_,0,0xfffffff0)
+#define SET_RG_GEMINIA_SX_DIV_PSCVDD(_VAL_) SET_REG(ADR_GEMINIA_SYN_DIV_SDM,_VAL_,4,0xffffff0f)
+#define SET_RG_GEMINIA_SX_DIV_RST_H(_VAL_) SET_REG(ADR_GEMINIA_SYN_DIV_SDM,_VAL_,9,0xfffffdff)
+#define SET_RG_GEMINIA_SX_DIV_SDM_EDGE(_VAL_) SET_REG(ADR_GEMINIA_SYN_DIV_SDM,_VAL_,10,0xfffffbff)
+#define SET_RG_GEMINIA_SX_DIV_DMYBUF_EN(_VAL_) SET_REG(ADR_GEMINIA_SYN_DIV_SDM,_VAL_,11,0xfffff7ff)
+#define SET_RG_GEMINIA_EN_SX_MOD(_VAL_) SET_REG(ADR_GEMINIA_SYN_DIV_SDM,_VAL_,17,0xfffdffff)
+#define SET_RG_GEMINIA_EN_SX_DITHER(_VAL_) SET_REG(ADR_GEMINIA_SYN_DIV_SDM,_VAL_,18,0xfffbffff)
+#define SET_RG_GEMINIA_SX_MOD_ORDER(_VAL_) SET_REG(ADR_GEMINIA_SYN_DIV_SDM,_VAL_,19,0xffe7ffff)
+#define SET_RG_GEMINIA_SX_DITHER_WEIGHT(_VAL_) SET_REG(ADR_GEMINIA_SYN_DIV_SDM,_VAL_,21,0xff9fffff)
+#define SET_RG_GEMINIA_SX_SUB_SEL_MAN(_VAL_) SET_REG(ADR_GEMINIA_SYN_SBCAL,_VAL_,0,0xfffffffe)
+#define SET_RG_GEMINIA_SX_SUB_SEL(_VAL_) SET_REG(ADR_GEMINIA_SYN_SBCAL,_VAL_,1,0xfffffe01)
+#define SET_RG_GEMINIA_SX_SUB_C0P5_DIS(_VAL_) SET_REG(ADR_GEMINIA_SYN_SBCAL,_VAL_,9,0xfffffdff)
+#define SET_RG_GEMINIA_SX_SBCAL_CT(_VAL_) SET_REG(ADR_GEMINIA_SYN_SBCAL,_VAL_,10,0xfffff3ff)
+#define SET_RG_GEMINIA_SX_SBCAL_WT(_VAL_) SET_REG(ADR_GEMINIA_SYN_SBCAL,_VAL_,12,0xffffefff)
+#define SET_RG_GEMINIA_SX_SBCAL_DIFFMIN(_VAL_) SET_REG(ADR_GEMINIA_SYN_SBCAL,_VAL_,13,0xffffdfff)
+#define SET_RG_GEMINIA_SX_SBCAL_NTARG_MAN(_VAL_) SET_REG(ADR_GEMINIA_SYN_SBCAL,_VAL_,15,0xffff7fff)
+#define SET_RG_GEMINIA_SX_SBCAL_NTARG(_VAL_) SET_REG(ADR_GEMINIA_SYN_SBCAL,_VAL_,16,0x0000ffff)
+#define SET_RG_GEMINIA_VO_AAC_TAR_BT(_VAL_) SET_REG(ADR_GEMINIA_SYN_AAC,_VAL_,0,0xfffffff0)
+#define SET_RG_GEMINIA_VO_AAC_IOST_BT(_VAL_) SET_REG(ADR_GEMINIA_SYN_AAC,_VAL_,4,0xffffffcf)
+#define SET_RG_GEMINIA_VO_AAC_TAR_WF(_VAL_) SET_REG(ADR_GEMINIA_SYN_AAC,_VAL_,7,0xfffff87f)
+#define SET_RG_GEMINIA_VO_AAC_IOST_WF(_VAL_) SET_REG(ADR_GEMINIA_SYN_AAC,_VAL_,11,0xffffe7ff)
+#define SET_RG_GEMINIA_VO_AAC_IMAX(_VAL_) SET_REG(ADR_GEMINIA_SYN_AAC,_VAL_,14,0xfffc3fff)
+#define SET_RG_GEMINIA_VO_AAC_INIT(_VAL_) SET_REG(ADR_GEMINIA_SYN_AAC,_VAL_,18,0xfff3ffff)
+#define SET_RG_GEMINIA_VO_AAC_EVA_TS(_VAL_) SET_REG(ADR_GEMINIA_SYN_AAC,_VAL_,20,0xffcfffff)
+#define SET_RG_GEMINIA_VO_AAC_EN_MAN(_VAL_) SET_REG(ADR_GEMINIA_SYN_AAC,_VAL_,23,0xff7fffff)
+#define SET_RG_GEMINIA_VO_AAC_EN(_VAL_) SET_REG(ADR_GEMINIA_SYN_AAC,_VAL_,24,0xfeffffff)
+#define SET_RG_GEMINIA_VO_AAC_EVA_MAN(_VAL_) SET_REG(ADR_GEMINIA_SYN_AAC,_VAL_,25,0xfdffffff)
+#define SET_RG_GEMINIA_VO_AAC_EVA(_VAL_) SET_REG(ADR_GEMINIA_SYN_AAC,_VAL_,26,0xfbffffff)
+#define SET_RG_GEMINIA_VO_AAC_TEST_EN(_VAL_) SET_REG(ADR_GEMINIA_SYN_AAC,_VAL_,28,0xefffffff)
+#define SET_RG_GEMINIA_VO_AAC_TEST_SEL(_VAL_) SET_REG(ADR_GEMINIA_SYN_AAC,_VAL_,29,0xdfffffff)
+#define SET_RG_GEMINIA_SX_TTL_INIT(_VAL_) SET_REG(ADR_GEMINIA_SYN_TTL,_VAL_,0,0xfffffffc)
+#define SET_RG_GEMINIA_SX_TTL_FPT(_VAL_) SET_REG(ADR_GEMINIA_SYN_TTL,_VAL_,2,0xfffffff3)
+#define SET_RG_GEMINIA_SX_TTL_CPT(_VAL_) SET_REG(ADR_GEMINIA_SYN_TTL,_VAL_,4,0xffffffcf)
+#define SET_RG_GEMINIA_SX_TTL_ACCUM(_VAL_) SET_REG(ADR_GEMINIA_SYN_TTL,_VAL_,7,0xfffffe7f)
+#define SET_RG_GEMINIA_SX_TTL_SUB(_VAL_) SET_REG(ADR_GEMINIA_SYN_TTL,_VAL_,10,0xfffff3ff)
+#define SET_RG_GEMINIA_SX_TTL_SUB_INV(_VAL_) SET_REG(ADR_GEMINIA_SYN_TTL,_VAL_,12,0xffffefff)
+#define SET_RG_GEMINIA_SX_TTL_VH(_VAL_) SET_REG(ADR_GEMINIA_SYN_TTL,_VAL_,14,0xffff3fff)
+#define SET_RG_GEMINIA_SX_TTL_VL(_VAL_) SET_REG(ADR_GEMINIA_SYN_TTL,_VAL_,16,0xfffcffff)
+#define SET_RG_GEMINIA_SX_LPF_VTUNE_TEST(_VAL_) SET_REG(ADR_GEMINIA_SYN_TTL,_VAL_,19,0xfff7ffff)
+#define SET_RG_GEMINIA_DP_BBPLL_PD(_VAL_) SET_REG(ADR_GEMINIA_DPLL_TOP_REGISTER,_VAL_,0,0xfffffffe)
+#define SET_RG_GEMINIA_DP_BBPLL_BP(_VAL_) SET_REG(ADR_GEMINIA_DPLL_TOP_REGISTER,_VAL_,1,0xfffffffd)
+#define SET_RG_GEMINIA_EN_DP_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_DPLL_TOP_REGISTER,_VAL_,2,0xfffffffb)
+#define SET_RG_GEMINIA_DP_FREF_DOUB(_VAL_) SET_REG(ADR_GEMINIA_DPLL_TOP_REGISTER,_VAL_,3,0xfffffff7)
+#define SET_RG_GEMINIA_DP_DAC320_DIVBY2(_VAL_) SET_REG(ADR_GEMINIA_DPLL_TOP_REGISTER,_VAL_,4,0xffffffef)
+#define SET_RG_GEMINIA_DP_ADC320_DIVBY2_BT(_VAL_) SET_REG(ADR_GEMINIA_DPLL_TOP_REGISTER,_VAL_,5,0xffffffdf)
+#define SET_RG_GEMINIA_DP_ADC320_DIVBY2_WF(_VAL_) SET_REG(ADR_GEMINIA_DPLL_TOP_REGISTER,_VAL_,6,0xffffffbf)
+#define SET_RG_GEMINIA_EN_DPL_MOD(_VAL_) SET_REG(ADR_GEMINIA_DPLL_TOP_REGISTER,_VAL_,8,0xfffffeff)
+#define SET_RG_GEMINIA_DPL_MOD_ORDER(_VAL_) SET_REG(ADR_GEMINIA_DPLL_TOP_REGISTER,_VAL_,9,0xfffff9ff)
+#define SET_RG_GEMINIA_DP_REFDIV(_VAL_) SET_REG(ADR_GEMINIA_DPLL_TOP_REGISTER,_VAL_,11,0xfffc07ff)
+#define SET_RG_GEMINIA_DP_FODIV(_VAL_) SET_REG(ADR_GEMINIA_DPLL_TOP_REGISTER,_VAL_,18,0xfe03ffff)
+#define SET_RG_GEMINIA_EN_LDO_DP_BYP(_VAL_) SET_REG(ADR_GEMINIA_DPLL_TOP_REGISTER,_VAL_,25,0xfdffffff)
+#define SET_RG_GEMINIA_EN_LDO_DP_IQUP(_VAL_) SET_REG(ADR_GEMINIA_DPLL_TOP_REGISTER,_VAL_,26,0xfbffffff)
+#define SET_RG_GEMINIA_DP_OD_TEST(_VAL_) SET_REG(ADR_GEMINIA_DPLL_TOP_REGISTER,_VAL_,27,0xf7ffffff)
+#define SET_RG_GEMINIA_DP_BBPLL_TESTSEL(_VAL_) SET_REG(ADR_GEMINIA_DPLL_TOP_REGISTER,_VAL_,28,0x8fffffff)
+#define SET_RG_GEMINIA_DP_BBPLL_ICP(_VAL_) SET_REG(ADR_GEMINIA_DPLL_CKT_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_GEMINIA_DP_BBPLL_IDUAL(_VAL_) SET_REG(ADR_GEMINIA_DPLL_CKT_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_GEMINIA_DP_CP_IOSTPOL(_VAL_) SET_REG(ADR_GEMINIA_DPLL_CKT_REGISTER,_VAL_,4,0xffffffef)
+#define SET_RG_GEMINIA_DP_CP_IOST(_VAL_) SET_REG(ADR_GEMINIA_DPLL_CKT_REGISTER,_VAL_,5,0xffffff9f)
+#define SET_RG_GEMINIA_DP_PFD_PFDSEL(_VAL_) SET_REG(ADR_GEMINIA_DPLL_CKT_REGISTER,_VAL_,7,0xffffff7f)
+#define SET_RG_GEMINIA_DP_BBPLL_PFD_DLY(_VAL_) SET_REG(ADR_GEMINIA_DPLL_CKT_REGISTER,_VAL_,8,0xfffffcff)
+#define SET_RG_GEMINIA_DP_RP(_VAL_) SET_REG(ADR_GEMINIA_DPLL_CKT_REGISTER,_VAL_,11,0xffffc7ff)
+#define SET_RG_GEMINIA_DP_RHP(_VAL_) SET_REG(ADR_GEMINIA_DPLL_CKT_REGISTER,_VAL_,14,0xffff3fff)
+#define SET_RG_GEMINIA_EN_DP_VT_MON(_VAL_) SET_REG(ADR_GEMINIA_DPLL_CKT_REGISTER,_VAL_,17,0xfffdffff)
+#define SET_RG_GEMINIA_DP_VT_TH_HI(_VAL_) SET_REG(ADR_GEMINIA_DPLL_CKT_REGISTER,_VAL_,18,0xfff3ffff)
+#define SET_RG_GEMINIA_DP_VT_TH_LO(_VAL_) SET_REG(ADR_GEMINIA_DPLL_CKT_REGISTER,_VAL_,20,0xffcfffff)
+#define SET_RG_GEMINIA_DP_BBPLL_BS(_VAL_) SET_REG(ADR_GEMINIA_DPLL_CKT_REGISTER,_VAL_,23,0xe07fffff)
+#define SET_RG_GEMINIA_DP_BBPLL_SDM_EDGE(_VAL_) SET_REG(ADR_GEMINIA_DPLL_CKT_REGISTER,_VAL_,31,0x7fffffff)
+#define SET_RG_GEMINIA_DPL_RFCTRL_F(_VAL_) SET_REG(ADR_GEMINIA_DPLL_FB_DIVISION_REGISTERS,_VAL_,0,0xff000000)
+#define SET_RG_GEMINIA_DPL_RFCTRL_CH(_VAL_) SET_REG(ADR_GEMINIA_DPLL_FB_DIVISION_REGISTERS,_VAL_,24,0x00ffffff)
+#define SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG15(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER1,_VAL_,0,0xffffffc0)
+#define SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG15(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER1,_VAL_,8,0xffffc0ff)
+#define SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG14(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER1,_VAL_,16,0xffc0ffff)
+#define SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG14(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER1,_VAL_,24,0xc0ffffff)
+#define SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG13(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER2,_VAL_,0,0xffffffc0)
+#define SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG13(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER2,_VAL_,8,0xffffc0ff)
+#define SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG12(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER2,_VAL_,16,0xffc0ffff)
+#define SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG12(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER2,_VAL_,24,0xc0ffffff)
+#define SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG11(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER3,_VAL_,0,0xffffffc0)
+#define SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG11(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER3,_VAL_,8,0xffffc0ff)
+#define SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG10(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER3,_VAL_,16,0xffc0ffff)
+#define SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG10(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER3,_VAL_,24,0xc0ffffff)
+#define SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG9(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER4,_VAL_,0,0xffffffc0)
+#define SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG9(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER4,_VAL_,8,0xffffc0ff)
+#define SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG8(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER4,_VAL_,16,0xffc0ffff)
+#define SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG8(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER4,_VAL_,24,0xc0ffffff)
+#define SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG7(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER5,_VAL_,0,0xffffffc0)
+#define SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG7(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER5,_VAL_,8,0xffffc0ff)
+#define SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG6(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER5,_VAL_,16,0xffc0ffff)
+#define SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG6(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER5,_VAL_,24,0xc0ffffff)
+#define SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG5(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER6,_VAL_,0,0xffffffc0)
+#define SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG5(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER6,_VAL_,8,0xffffc0ff)
+#define SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG4(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER6,_VAL_,16,0xffc0ffff)
+#define SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG4(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER6,_VAL_,24,0xc0ffffff)
+#define SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG3(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER7,_VAL_,0,0xffffffc0)
+#define SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG3(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER7,_VAL_,8,0xffffc0ff)
+#define SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG2(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER7,_VAL_,16,0xffc0ffff)
+#define SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG2(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER7,_VAL_,24,0xc0ffffff)
+#define SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG1(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER8,_VAL_,0,0xffffffc0)
+#define SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG1(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER8,_VAL_,8,0xffffc0ff)
+#define SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG0(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER8,_VAL_,16,0xffc0ffff)
+#define SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG0(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER8,_VAL_,24,0xc0ffffff)
+#define SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG15(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER9,_VAL_,0,0xffffffc0)
+#define SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG15(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER9,_VAL_,8,0xffffc0ff)
+#define SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG14(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER9,_VAL_,16,0xffc0ffff)
+#define SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG14(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER9,_VAL_,24,0xc0ffffff)
+#define SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG13(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER10,_VAL_,0,0xffffffc0)
+#define SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG13(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER10,_VAL_,8,0xffffc0ff)
+#define SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG12(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER10,_VAL_,16,0xffc0ffff)
+#define SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG12(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER10,_VAL_,24,0xc0ffffff)
+#define SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG11(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER11,_VAL_,0,0xffffffc0)
+#define SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG11(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER11,_VAL_,8,0xffffc0ff)
+#define SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG10(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER11,_VAL_,16,0xffc0ffff)
+#define SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG10(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER11,_VAL_,24,0xc0ffffff)
+#define SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG9(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER12,_VAL_,0,0xffffffc0)
+#define SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG9(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER12,_VAL_,8,0xffffc0ff)
+#define SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG8(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER12,_VAL_,16,0xffc0ffff)
+#define SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG8(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER12,_VAL_,24,0xc0ffffff)
+#define SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG7(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER13,_VAL_,0,0xffffffc0)
+#define SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG7(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER13,_VAL_,8,0xffffc0ff)
+#define SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG6(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER13,_VAL_,16,0xffc0ffff)
+#define SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG6(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER13,_VAL_,24,0xc0ffffff)
+#define SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG5(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER14,_VAL_,0,0xffffffc0)
+#define SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG5(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER14,_VAL_,8,0xffffc0ff)
+#define SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG4(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER14,_VAL_,16,0xffc0ffff)
+#define SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG4(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER14,_VAL_,24,0xc0ffffff)
+#define SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG3(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER15,_VAL_,0,0xffffffc0)
+#define SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG3(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER15,_VAL_,8,0xffffc0ff)
+#define SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG2(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER15,_VAL_,16,0xffc0ffff)
+#define SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG2(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER15,_VAL_,24,0xc0ffffff)
+#define SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG1(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER16,_VAL_,0,0xffffffc0)
+#define SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG1(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER16,_VAL_,8,0xffffc0ff)
+#define SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG0(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER16,_VAL_,16,0xffc0ffff)
+#define SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG0(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER16,_VAL_,24,0xc0ffffff)
+#define SET_RG_GEMINIA_IDACAI_TZ0_COARSE4(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER17,_VAL_,0,0xffffffc0)
+#define SET_RG_GEMINIA_IDACAQ_TZ0_COARSE4(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER17,_VAL_,8,0xffffc0ff)
+#define SET_RG_GEMINIA_IDACAI_TZ0_COARSE3(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER17,_VAL_,16,0xffc0ffff)
+#define SET_RG_GEMINIA_IDACAQ_TZ0_COARSE3(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER17,_VAL_,24,0xc0ffffff)
+#define SET_RG_GEMINIA_IDACAI_TZ0_COARSE2(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER18,_VAL_,0,0xffffffc0)
+#define SET_RG_GEMINIA_IDACAQ_TZ0_COARSE2(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER18,_VAL_,8,0xffffc0ff)
+#define SET_RG_GEMINIA_IDACAI_TZ0_COARSE1(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER18,_VAL_,16,0xffc0ffff)
+#define SET_RG_GEMINIA_IDACAQ_TZ0_COARSE1(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER18,_VAL_,24,0xc0ffffff)
+#define SET_RG_GEMINIA_IDACAI_TZ0_COARSE0(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER19,_VAL_,0,0xffffffc0)
+#define SET_RG_GEMINIA_IDACAQ_TZ0_COARSE0(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER19,_VAL_,8,0xffffc0ff)
+#define SET_RG_GEMINIA_IDACAI_TZ1_COARSE4(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER20,_VAL_,0,0xffffffc0)
+#define SET_RG_GEMINIA_IDACAQ_TZ1_COARSE4(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER20,_VAL_,8,0xffffc0ff)
+#define SET_RG_GEMINIA_IDACAI_TZ1_COARSE3(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER20,_VAL_,16,0xffc0ffff)
+#define SET_RG_GEMINIA_IDACAQ_TZ1_COARSE3(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER20,_VAL_,24,0xc0ffffff)
+#define SET_RG_GEMINIA_IDACAI_TZ1_COARSE2(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER21,_VAL_,0,0xffffffc0)
+#define SET_RG_GEMINIA_IDACAQ_TZ1_COARSE2(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER21,_VAL_,8,0xffffc0ff)
+#define SET_RG_GEMINIA_IDACAI_TZ1_COARSE1(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER21,_VAL_,16,0xffc0ffff)
+#define SET_RG_GEMINIA_IDACAQ_TZ1_COARSE1(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER21,_VAL_,24,0xc0ffffff)
+#define SET_RG_GEMINIA_IDACAI_TZ1_COARSE0(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER22,_VAL_,0,0xffffffc0)
+#define SET_RG_GEMINIA_IDACAQ_TZ1_COARSE0(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER22,_VAL_,8,0xffffc0ff)
+#define SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG15(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER1,_VAL_,0,0xffffffc0)
+#define SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG15(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER1,_VAL_,8,0xffffc0ff)
+#define SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG14(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER1,_VAL_,16,0xffc0ffff)
+#define SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG14(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER1,_VAL_,24,0xc0ffffff)
+#define SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG13(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER2,_VAL_,0,0xffffffc0)
+#define SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG13(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER2,_VAL_,8,0xffffc0ff)
+#define SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG12(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER2,_VAL_,16,0xffc0ffff)
+#define SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG12(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER2,_VAL_,24,0xc0ffffff)
+#define SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG11(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER3,_VAL_,0,0xffffffc0)
+#define SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG11(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER3,_VAL_,8,0xffffc0ff)
+#define SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG10(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER3,_VAL_,16,0xffc0ffff)
+#define SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG10(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER3,_VAL_,24,0xc0ffffff)
+#define SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG9(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER4,_VAL_,0,0xffffffc0)
+#define SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG9(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER4,_VAL_,8,0xffffc0ff)
+#define SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG8(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER4,_VAL_,16,0xffc0ffff)
+#define SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG8(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER4,_VAL_,24,0xc0ffffff)
+#define SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG7(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER5,_VAL_,0,0xffffffc0)
+#define SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG7(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER5,_VAL_,8,0xffffc0ff)
+#define SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG6(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER5,_VAL_,16,0xffc0ffff)
+#define SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG6(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER5,_VAL_,24,0xc0ffffff)
+#define SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG5(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER6,_VAL_,0,0xffffffc0)
+#define SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG5(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER6,_VAL_,8,0xffffc0ff)
+#define SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG4(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER6,_VAL_,16,0xffc0ffff)
+#define SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG4(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER6,_VAL_,24,0xc0ffffff)
+#define SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG3(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER7,_VAL_,0,0xffffffc0)
+#define SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG3(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER7,_VAL_,8,0xffffc0ff)
+#define SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG2(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER7,_VAL_,16,0xffc0ffff)
+#define SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG2(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER7,_VAL_,24,0xc0ffffff)
+#define SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG1(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER8,_VAL_,0,0xffffffc0)
+#define SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG1(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER8,_VAL_,8,0xffffc0ff)
+#define SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG0(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER8,_VAL_,16,0xffc0ffff)
+#define SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG0(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER8,_VAL_,24,0xc0ffffff)
+#define SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG15(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER9,_VAL_,0,0xffffffc0)
+#define SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG15(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER9,_VAL_,8,0xffffc0ff)
+#define SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG14(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER9,_VAL_,16,0xffc0ffff)
+#define SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG14(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER9,_VAL_,24,0xc0ffffff)
+#define SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG13(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER10,_VAL_,0,0xffffffc0)
+#define SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG13(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER10,_VAL_,8,0xffffc0ff)
+#define SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG12(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER10,_VAL_,16,0xffc0ffff)
+#define SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG12(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER10,_VAL_,24,0xc0ffffff)
+#define SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG11(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER11,_VAL_,0,0xffffffc0)
+#define SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG11(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER11,_VAL_,8,0xffffc0ff)
+#define SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG10(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER11,_VAL_,16,0xffc0ffff)
+#define SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG10(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER11,_VAL_,24,0xc0ffffff)
+#define SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG9(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER12,_VAL_,0,0xffffffc0)
+#define SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG9(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER12,_VAL_,8,0xffffc0ff)
+#define SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG8(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER12,_VAL_,16,0xffc0ffff)
+#define SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG8(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER12,_VAL_,24,0xc0ffffff)
+#define SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG7(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER13,_VAL_,0,0xffffffc0)
+#define SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG7(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER13,_VAL_,8,0xffffc0ff)
+#define SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG6(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER13,_VAL_,16,0xffc0ffff)
+#define SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG6(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER13,_VAL_,24,0xc0ffffff)
+#define SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG5(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER14,_VAL_,0,0xffffffc0)
+#define SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG5(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER14,_VAL_,8,0xffffc0ff)
+#define SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG4(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER14,_VAL_,16,0xffc0ffff)
+#define SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG4(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER14,_VAL_,24,0xc0ffffff)
+#define SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG3(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER15,_VAL_,0,0xffffffc0)
+#define SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG3(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER15,_VAL_,8,0xffffc0ff)
+#define SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG2(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER15,_VAL_,16,0xffc0ffff)
+#define SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG2(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER15,_VAL_,24,0xc0ffffff)
+#define SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG1(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER16,_VAL_,0,0xffffffc0)
+#define SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG1(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER16,_VAL_,8,0xffffc0ff)
+#define SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG0(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER16,_VAL_,16,0xffc0ffff)
+#define SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG0(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER16,_VAL_,24,0xc0ffffff)
+#define SET_RG_GEMINIA_SX_DELAY(_VAL_) SET_REG(ADR_GEMINIA_MODE_DECODER_TIMER_REGISTER1,_VAL_,0,0xfffffff0)
+#define SET_RG_GEMINIA_TXDAC_DELAY(_VAL_) SET_REG(ADR_GEMINIA_MODE_DECODER_TIMER_REGISTER1,_VAL_,4,0xffffff0f)
+#define SET_RG_GEMINIA_TXRF_DELAY(_VAL_) SET_REG(ADR_GEMINIA_MODE_DECODER_TIMER_REGISTER1,_VAL_,8,0xfffff0ff)
+#define SET_RG_GEMINIA_TXPA_DELAY(_VAL_) SET_REG(ADR_GEMINIA_MODE_DECODER_TIMER_REGISTER1,_VAL_,12,0xffff0fff)
+#define SET_RG_GEMINIA_RXRF_DELAY(_VAL_) SET_REG(ADR_GEMINIA_MODE_DECODER_TIMER_REGISTER1,_VAL_,16,0xfff0ffff)
+#define SET_RG_GEMINIA_TXBTPA_DELAY(_VAL_) SET_REG(ADR_GEMINIA_MODE_DECODER_TIMER_REGISTER1,_VAL_,20,0xff0fffff)
+#define SET_RG_GEMINIA_TXDAC_T2R_DELAY(_VAL_) SET_REG(ADR_GEMINIA_WIFI_T2R_TIMER_REGISTER,_VAL_,0,0xffffffe0)
+#define SET_RG_GEMINIA_TXRF_T2R_DELAY(_VAL_) SET_REG(ADR_GEMINIA_WIFI_T2R_TIMER_REGISTER,_VAL_,8,0xffffe0ff)
+#define SET_RG_GEMINIA_TXPA_T2R_DELAY(_VAL_) SET_REG(ADR_GEMINIA_WIFI_T2R_TIMER_REGISTER,_VAL_,16,0xffe0ffff)
+#define SET_RG_GEMINIA_RXRF_T2R_DELAY(_VAL_) SET_REG(ADR_GEMINIA_WIFI_T2R_TIMER_REGISTER,_VAL_,24,0xe0ffffff)
+#define SET_RG_GEMINIA_TXDAC_R2T_DELAY(_VAL_) SET_REG(ADR_GEMINIA_WIFI_R2T_TIMER_REGISTER,_VAL_,0,0xffffffe0)
+#define SET_RG_GEMINIA_TXRF_R2T_DELAY(_VAL_) SET_REG(ADR_GEMINIA_WIFI_R2T_TIMER_REGISTER,_VAL_,8,0xffffe0ff)
+#define SET_RG_GEMINIA_TXPA_R2T_DELAY(_VAL_) SET_REG(ADR_GEMINIA_WIFI_R2T_TIMER_REGISTER,_VAL_,16,0xffe0ffff)
+#define SET_RG_GEMINIA_RXRF_R2T_DELAY(_VAL_) SET_REG(ADR_GEMINIA_WIFI_R2T_TIMER_REGISTER,_VAL_,24,0xe0ffffff)
+#define SET_RG_GEMINIA_WF_RX_DCCAL_DELAY(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TIMER_REGISTER,_VAL_,0,0xfffffff8)
+#define SET_RG_GEMINIA_BT_RX_DCCAL_DELAY(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TIMER_REGISTER,_VAL_,4,0xffffff8f)
+#define SET_RG_GEMINIA_RX_RCCAL_DELAY(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TIMER_REGISTER,_VAL_,8,0xfffff8ff)
+#define SET_RG_GEMINIA_TX_LOCAL_DELAY(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TIMER_REGISTER,_VAL_,12,0xffff8fff)
+#define SET_RG_GEMINIA_TX_IQCAL_DELAY(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TIMER_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_GEMINIA_RX_IQCAL_DELAY(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TIMER_REGISTER,_VAL_,20,0xff8fffff)
+#define SET_RG_GEMINIA_PGAG_RCCAL(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_GAIN_REGISTER0,_VAL_,0,0xfffffff0)
+#define SET_RG_GEMINIA_PGAG_TXCAL(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_GAIN_REGISTER0,_VAL_,4,0xffffff0f)
+#define SET_RG_GEMINIA_TX_GAIN_TXCAL(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_GAIN_REGISTER0,_VAL_,8,0xffff80ff)
+#define SET_RG_GEMINIA_RFG_RXIQCAL(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_GAIN_REGISTER0,_VAL_,16,0xfffcffff)
+#define SET_RG_GEMINIA_PGAG_RXIQCAL(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_GAIN_REGISTER0,_VAL_,18,0xffc3ffff)
+#define SET_RG_GEMINIA_TX_GAIN_RXIQCAL(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_GAIN_REGISTER0,_VAL_,22,0xe03fffff)
+#define SET_RG_GEMINIA_RFG_DPDCAL(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_GAIN_REGISTER1,_VAL_,0,0xfffffffc)
+#define SET_RG_GEMINIA_PGAG_DPDCAL(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_GAIN_REGISTER1,_VAL_,2,0xffffffc3)
+#define SET_RG_GEMINIA_TX_GAIN_DPDCAL(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_GAIN_REGISTER1,_VAL_,6,0xffffe03f)
+#define SET_DB_GEMINIA_AD_ADC_I_OUT(_VAL_) SET_REG(ADR_GEMINIA_READ_ONLY_FLAGS_ADC,_VAL_,0,0xfffffc00)
+#define SET_DB_GEMINIA_AD_ADC_Q_OUT(_VAL_) SET_REG(ADR_GEMINIA_READ_ONLY_FLAGS_ADC,_VAL_,10,0xfff003ff)
+#define SET_DB_GEMINIA_AD_RX_RSSIADC(_VAL_) SET_REG(ADR_GEMINIA_READ_ONLY_FLAGS_ADC,_VAL_,20,0xff0fffff)
+#define SET_DB_GEMINIA_DA_SARADC_BIT(_VAL_) SET_REG(ADR_GEMINIA_READ_ONLY_FLAGS_ADC,_VAL_,24,0xc0ffffff)
+#define SET_GEMINIA_SAR_ADC_FSM_RDY(_VAL_) SET_REG(ADR_GEMINIA_READ_ONLY_FLAGS_ADC,_VAL_,30,0xbfffffff)
+#define SET_DB_GEMINIA_DA_SX_SUB_SEL(_VAL_) SET_REG(ADR_GEMINIA_READ_ONLY_FLAGS_SX1,_VAL_,0,0xffffff00)
+#define SET_DB_GEMINIA_DA_SX_VCO_ISEL(_VAL_) SET_REG(ADR_GEMINIA_READ_ONLY_FLAGS_SX1,_VAL_,9,0xffffe1ff)
+#define SET_DB_GEMINIA_VO_AAC_COMPOUT(_VAL_) SET_REG(ADR_GEMINIA_READ_ONLY_FLAGS_SX1,_VAL_,13,0xffffdfff)
+#define SET_DB_GEMINIA_SX_TTL_VT_DET(_VAL_) SET_REG(ADR_GEMINIA_READ_ONLY_FLAGS_SX1,_VAL_,15,0xfffe7fff)
+#define SET_DB_GEMINIA_AD_DP_VT_MON_Q(_VAL_) SET_REG(ADR_GEMINIA_READ_ONLY_FLAGS_SX1,_VAL_,29,0x9fffffff)
+#define SET_DB_GEMINIA_SX_SBCAL_NCOUNT(_VAL_) SET_REG(ADR_GEMINIA_READ_ONLY_FLAGS_SX2,_VAL_,0,0xffff0000)
+#define SET_DB_GEMINIA_SX_SBCAL_NTARGET(_VAL_) SET_REG(ADR_GEMINIA_READ_ONLY_FLAGS_SX2,_VAL_,16,0x0000ffff)
+#define SET_RG_GEMINIA_NFRAC_DELTA(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R0,_VAL_,0,0xff000000)
+#define SET_RG_GEMINIA_40M_MODE(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R0,_VAL_,24,0xfeffffff)
+#define SET_RG_GEMINIA_LO_UP_CH(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R0,_VAL_,28,0xefffffff)
+#define SET_RG_GEMINIA_RX_IQ_ALPHA(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R2,_VAL_,0,0xffffffe0)
+#define SET_RG_GEMINIA_RX_IQ_THETA(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R2,_VAL_,8,0xffffe0ff)
+#define SET_RG_GEMINIA_RX_IQ_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R2,_VAL_,16,0xfffeffff)
+#define SET_RG_GEMINIA_RXIQ_NOSHRK(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R2,_VAL_,17,0xfffdffff)
+#define SET_RG_GEMINIA_RX_RSSIADC_TH(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R2,_VAL_,20,0xff0fffff)
+#define SET_RG_GEMINIA_RSSI_EDGE_SEL(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R2,_VAL_,26,0xfbffffff)
+#define SET_RG_GEMINIA_ADC_EDGE_SEL(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R2,_VAL_,27,0xf7ffffff)
+#define SET_RG_GEMINIA_Q_INV(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R2,_VAL_,28,0xefffffff)
+#define SET_RG_GEMINIA_I_INV(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R2,_VAL_,29,0xdfffffff)
+#define SET_RG_GEMINIA_IQ_SWAP(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R2,_VAL_,30,0xbfffffff)
+#define SET_RG_GEMINIA_SIGN_SWAP(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R2,_VAL_,31,0x7fffffff)
+#define SET_RG_GEMINIA_TX_IQ_ALPHA(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R3,_VAL_,0,0xffffffe0)
+#define SET_RG_GEMINIA_TX_IQ_THETA(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R3,_VAL_,8,0xffffe0ff)
+#define SET_RG_GEMINIA_TX_IQ_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R3,_VAL_,16,0xfffeffff)
+#define SET_RG_GEMINIA_TXIQ_NOSHRK(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R3,_VAL_,17,0xfffdffff)
+#define SET_RG_GEMINIA_TX_FREQ_OFFSET(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R4,_VAL_,0,0xffff0000)
+#define SET_RG_GEMINIA_TONE_SCALE(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R4,_VAL_,16,0xfe00ffff)
+#define SET_RG_GEMINIA_TX_UP8X_MAN_EN(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R4,_VAL_,27,0xf7ffffff)
+#define SET_RG_GEMINIA_DIS_DAC_OFFSET(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R4,_VAL_,28,0xefffffff)
+#define SET_RG_GEMINIA_EXT_DAC_EN(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R4,_VAL_,29,0xdfffffff)
+#define SET_RG_GEMINIA_DPLL_CLK320BY2(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R4,_VAL_,30,0xbfffffff)
+#define SET_RG_GEMINIA_CBW_20_40(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R4,_VAL_,31,0x7fffffff)
+#define SET_RG_GEMINIA_DAC_DC_Q(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R5,_VAL_,0,0xfffffc00)
+#define SET_RG_GEMINIA_DAC_DC_I(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R5,_VAL_,16,0xfc00ffff)
+#define SET_RG_GEMINIA_DAC_Q_SET(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R6,_VAL_,0,0xfffffc00)
+#define SET_RG_GEMINIA_DAC_MAN_Q_EN(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R6,_VAL_,12,0xffffefff)
+#define SET_RG_GEMINIA_DAC_I_SET(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R6,_VAL_,16,0xfc00ffff)
+#define SET_RG_GEMINIA_DAC_MAN_I_EN(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R6,_VAL_,28,0xefffffff)
+#define SET_RG_GEMINIA_BW20_HB_COEF_01(_VAL_) SET_REG(ADR_GEMINIA_TX_UP8X_COEF_R0,_VAL_,0,0xffffe000)
+#define SET_RG_GEMINIA_BW20_HB_COEF_00(_VAL_) SET_REG(ADR_GEMINIA_TX_UP8X_COEF_R0,_VAL_,16,0xe000ffff)
+#define SET_RG_GEMINIA_BW20_HB_COEF_03(_VAL_) SET_REG(ADR_GEMINIA_TX_UP8X_COEF_R1,_VAL_,0,0xffffe000)
+#define SET_RG_GEMINIA_BW20_HB_COEF_02(_VAL_) SET_REG(ADR_GEMINIA_TX_UP8X_COEF_R1,_VAL_,16,0xe000ffff)
+#define SET_RG_GEMINIA_BW20_HB_COEF_05(_VAL_) SET_REG(ADR_GEMINIA_TX_UP8X_COEF_R2,_VAL_,0,0xffffe000)
+#define SET_RG_GEMINIA_BW20_HB_COEF_04(_VAL_) SET_REG(ADR_GEMINIA_TX_UP8X_COEF_R2,_VAL_,16,0xe000ffff)
+#define SET_RG_GEMINIA_BW20_HB_COEF_07(_VAL_) SET_REG(ADR_GEMINIA_TX_UP8X_COEF_R3,_VAL_,0,0xffffe000)
+#define SET_RG_GEMINIA_BW20_HB_COEF_06(_VAL_) SET_REG(ADR_GEMINIA_TX_UP8X_COEF_R3,_VAL_,16,0xe000ffff)
+#define SET_RG_GEMINIA_BW20_HB_COEF_09(_VAL_) SET_REG(ADR_GEMINIA_TX_UP8X_COEF_R4,_VAL_,0,0xffffe000)
+#define SET_RG_GEMINIA_BW20_HB_COEF_08(_VAL_) SET_REG(ADR_GEMINIA_TX_UP8X_COEF_R4,_VAL_,16,0xe000ffff)
+#define SET_RG_GEMINIA_BW20_HB_COEF_11(_VAL_) SET_REG(ADR_GEMINIA_TX_UP8X_COEF_R5,_VAL_,0,0xffffe000)
+#define SET_RG_GEMINIA_BW20_HB_COEF_10(_VAL_) SET_REG(ADR_GEMINIA_TX_UP8X_COEF_R5,_VAL_,16,0xe000ffff)
+#define SET_RG_GEMINIA_PHASE_STEP_VALUE(_VAL_) SET_REG(ADR_GEMINIA_RF_D_CAL_TOP_R0,_VAL_,0,0xffff0000)
+#define SET_RG_GEMINIA_PHASE_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_RF_D_CAL_TOP_R0,_VAL_,16,0xfffeffff)
+#define SET_RG_GEMINIA_ALPHA_SEL(_VAL_) SET_REG(ADR_GEMINIA_RF_D_CAL_TOP_R0,_VAL_,20,0xffcfffff)
+#define SET_RG_GEMINIA_SPECTRUM_BW(_VAL_) SET_REG(ADR_GEMINIA_RF_D_CAL_TOP_R0,_VAL_,24,0xfcffffff)
+#define SET_RG_GEMINIA_SPECTRUM_EN(_VAL_) SET_REG(ADR_GEMINIA_RF_D_CAL_TOP_R0,_VAL_,28,0xefffffff)
+#define SET_RG_GEMINIA_RX_RCCAL_TARG(_VAL_) SET_REG(ADR_GEMINIA_RF_D_CAL_TOP_R1,_VAL_,0,0xfffffc00)
+#define SET_RG_GEMINIA_RX_DC_POLAR_INV(_VAL_) SET_REG(ADR_GEMINIA_RF_D_CAL_TOP_R1,_VAL_,12,0xffffefff)
+#define SET_RG_GEMINIA_RCCAL_POLAR_INV(_VAL_) SET_REG(ADR_GEMINIA_RF_D_CAL_TOP_R1,_VAL_,13,0xffffdfff)
+#define SET_RO_GEMINIA_WF_DCCAL_DONE(_VAL_) SET_REG(ADR_GEMINIA_RF_D_CAL_TOP_R1,_VAL_,16,0xfffeffff)
+#define SET_RO_GEMINIA_BT_DCCAL_DONE(_VAL_) SET_REG(ADR_GEMINIA_RF_D_CAL_TOP_R1,_VAL_,17,0xfffdffff)
+#define SET_RO_GEMINIA_RCCAL_DONE(_VAL_) SET_REG(ADR_GEMINIA_RF_D_CAL_TOP_R1,_VAL_,18,0xfffbffff)
+#define SET_RO_GEMINIA_TXDC_DONE(_VAL_) SET_REG(ADR_GEMINIA_RF_D_CAL_TOP_R1,_VAL_,19,0xfff7ffff)
+#define SET_RO_GEMINIA_TXIQ_DONE(_VAL_) SET_REG(ADR_GEMINIA_RF_D_CAL_TOP_R1,_VAL_,20,0xffefffff)
+#define SET_RO_GEMINIA_RXIQ_DONE(_VAL_) SET_REG(ADR_GEMINIA_RF_D_CAL_TOP_R1,_VAL_,21,0xffdfffff)
+#define SET_RG_GEMINIA_PHASE_17P5M(_VAL_) SET_REG(ADR_GEMINIA_RF_D_CAL_TOP_R2,_VAL_,0,0xffff0000)
+#define SET_RG_GEMINIA_PHASE_2P5M(_VAL_) SET_REG(ADR_GEMINIA_RF_D_CAL_TOP_R2,_VAL_,16,0x0000ffff)
+#define SET_RG_GEMINIA_PHASE_RXIQ_1M(_VAL_) SET_REG(ADR_GEMINIA_RF_D_CAL_TOP_R3,_VAL_,0,0xffff0000)
+#define SET_RG_GEMINIA_PHASE_1M(_VAL_) SET_REG(ADR_GEMINIA_RF_D_CAL_TOP_R3,_VAL_,16,0x0000ffff)
+#define SET_RG_GEMINIA_EN_LDO_XO_BYP(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_1,_VAL_,0,0xfffffffe)
+#define SET_RG_GEMINIA_EN_LDO_XO_IQUP(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_1,_VAL_,1,0xfffffffd)
+#define SET_RG_GEMINIA_XO_LDO_LEVEL(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_1,_VAL_,2,0xffffffe3)
+#define SET_RG_GEMINIA_XO_CBANKI(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_1,_VAL_,5,0xffffe01f)
+#define SET_RG_GEMINIA_XO_CBANKO(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_1,_VAL_,13,0xffe01fff)
+#define SET_RG_GEMINIA_EN_FDB(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_1,_VAL_,21,0xffdfffff)
+#define SET_RG_GEMINIA_FDB_BYPASS(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_1,_VAL_,22,0xffbfffff)
+#define SET_RG_GEMINIA_FDB_DUTY_LTH(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_1,_VAL_,23,0xfe7fffff)
+#define SET_RG_GEMINIA_EN_XOTEST(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_1,_VAL_,25,0xfdffffff)
+#define SET_RG_GEMINIA_EN_FDB_DCC_MUAL(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_2,_VAL_,0,0xfffffffe)
+#define SET_RG_GEMINIA_EN_FDB_DELAYC_MUAL(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_2,_VAL_,1,0xfffffffd)
+#define SET_RG_GEMINIA_EN_FDB_DELAYF_MUAL(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_2,_VAL_,2,0xfffffffb)
+#define SET_RG_GEMINIA_EN_FDB_PHASESWAP_MUAL(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_2,_VAL_,3,0xfffffff7)
+#define SET_RG_GEMINIA_FDB_PHASESWAP_MUAL(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_2,_VAL_,4,0xffffffef)
+#define SET_RG_GEMINIA_FDB_CDELAY_MUAL(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_2,_VAL_,8,0xfffff0ff)
+#define SET_RG_GEMINIA_FDB_FDELAY_MUAL(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_2,_VAL_,12,0xffff0fff)
+#define SET_RG_GEMINIA_XO_TIMMER(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_2,_VAL_,16,0xffc0ffff)
+#define SET_RG_GEMINIA_DPL_SETTLING_TIMMER(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_2,_VAL_,22,0xff3fffff)
+#define SET_RG_GEMINIA_FDB_RDELAYF(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_2,_VAL_,24,0xfcffffff)
+#define SET_RG_GEMINIA_FDB_RDELAYS(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_2,_VAL_,26,0xf3ffffff)
+#define SET_RG_GEMINIA_FDB_RECAL_TIMMER(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_2,_VAL_,28,0xcfffffff)
+#define SET_RG_GEMINIA_EN_FDB_RECAL(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_2,_VAL_,30,0xbfffffff)
+#define SET_RG_GEMINIA_LOAD_RFTABLE_RDY(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_2,_VAL_,31,0x7fffffff)
+#define SET_RG_GEMINIA_DCDC_MODE(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_3,_VAL_,0,0xfffffffe)
+#define SET_RG_GEMINIA_BUCK_LEVEL(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_3,_VAL_,1,0xfffffff1)
+#define SET_RG_GEMINIA_DLDO_LEVEL(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_3,_VAL_,4,0xffffff8f)
+#define SET_RG_GEMINIA_DLDO_BOOST_IQ(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_3,_VAL_,8,0xfffffeff)
+#define SET_RG_GEMINIA_BUCK_EN_PSM(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_3,_VAL_,9,0xfffffdff)
+#define SET_RG_GEMINIA_BUCK_PSM_VTH(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_3,_VAL_,10,0xfffffbff)
+#define SET_RG_GEMINIA_BUCK_VREF_SEL(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_3,_VAL_,11,0xfffff7ff)
+#define SET_RG_GEMINIA_LDO_LEVEL_EFUSE(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_3,_VAL_,12,0xffff8fff)
+#define SET_RG_GEMINIA_EN_LDO_EFUSE(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_3,_VAL_,16,0xfffeffff)
+#define SET_RG_GEMINIA_DCDC_PULLLOW_CON(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_3,_VAL_,18,0xfffbffff)
+#define SET_RG_GEMINIA_DCDC_RES2_CON(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_3,_VAL_,19,0xfff7ffff)
+#define SET_RG_GEMINIA_DCDC_RES_CON(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_3,_VAL_,20,0xffefffff)
+#define SET_RG_GEMINIA_RTC_RS1(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_3,_VAL_,21,0xffdfffff)
+#define SET_RG_GEMINIA_RTC_RS2(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_3,_VAL_,22,0xffbfffff)
+#define SET_RG_GEMINIA_DCDC_CLK(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_3,_VAL_,24,0xfcffffff)
+#define SET_RG_GEMINIA_RTC_OFFSET(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_4,_VAL_,0,0xffffff00)
+#define SET_RG_GEMINIA_RTC_CAL_TARGET_COUNT(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_4,_VAL_,8,0xfff000ff)
+#define SET_RG_GEMINIA_RTC_OSC_RES_SW_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_4,_VAL_,20,0xc00fffff)
+#define SET_RG_GEMINIA_RTC_CAL_MODE(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_4,_VAL_,30,0xbfffffff)
+#define SET_RG_GEMINIA_SEL_DPLL_CLK(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_4,_VAL_,31,0x7fffffff)
+#define SET_RG_GEMINIA_RTC_OSC_RES_SW_MANUAL_EN(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_5,_VAL_,0,0xfffffffe)
+#define SET_RG_GEMINIA_EN_RTC_CAL(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_5,_VAL_,1,0xfffffffd)
+#define SET_RO_GEMINIA_RTC_OSC_RES_SW(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_6,_VAL_,16,0xfc00ffff)
+#define SET_RO_GEMINIA_RTC_OSC_CAL_RES_RDY(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_6,_VAL_,31,0x7fffffff)
+#define SET_RG_GEMINIA_BT_CLK_SW(_VAL_) SET_REG(ADR_GEMINIA_PMU_BT_CLK,_VAL_,0,0xfffffffe)
+#define SET_RG_GEMINIA_BT_CLK32K_CAL_DONE(_VAL_) SET_REG(ADR_GEMINIA_PMU_BT_CLK,_VAL_,1,0xfffffffd)
+#define SET_RG_GEMINIA_SLEEP_WAKE_CNT(_VAL_) SET_REG(ADR_GEMINIA_PMU_SLEEP_REG,_VAL_,0,0xff000000)
+#define SET_RG_GEMINIA_PMU_ENTER_SLEEP_MODE(_VAL_) SET_REG(ADR_GEMINIA_PMU_SLEEP_REG,_VAL_,24,0xfeffffff)
+#define SET_RG_GEMINIA_RTC_EN(_VAL_) SET_REG(ADR_GEMINIA_PMU_RTC_REG_0,_VAL_,0,0xfffffffe)
+#define SET_RG_GEMINIA_CLK_RTC_SW(_VAL_) SET_REG(ADR_GEMINIA_PMU_RTC_REG_0,_VAL_,1,0xfffffffd)
+#define SET_RO_GEMINIA_PMU_WAKE_TRIG_EVENT(_VAL_) SET_REG(ADR_GEMINIA_PMU_RTC_REG_0,_VAL_,12,0xffffcfff)
+#define SET_RO_GEMINIA_RTC_TICK_CNT(_VAL_) SET_REG(ADR_GEMINIA_PMU_RTC_REG_0,_VAL_,16,0x8000ffff)
+#define SET_RG_GEMINIA_RTC_INT_SEC_MASK(_VAL_) SET_REG(ADR_GEMINIA_PMU_RTC_REG_1,_VAL_,0,0xfffffffe)
+#define SET_RG_GEMINIA_RTC_INT_ALARM_MASK(_VAL_) SET_REG(ADR_GEMINIA_PMU_RTC_REG_1,_VAL_,1,0xfffffffd)
+#define SET_RO_GEMINIA_RTC_INT_SEC(_VAL_) SET_REG(ADR_GEMINIA_PMU_RTC_REG_1,_VAL_,16,0xfffeffff)
+#define SET_RO_GEMINIA_RTC_INT_ALARM(_VAL_) SET_REG(ADR_GEMINIA_PMU_RTC_REG_1,_VAL_,17,0xfffdffff)
+#define SET_RG_GEMINIA_RTC_SEC_START_CNT(_VAL_) SET_REG(ADR_GEMINIA_PMU_RTC_REG_2,_VAL_,0,0x00000000)
+#define SET_RG_GEMINIA_RTC_SEC_ALARM_VALUE(_VAL_) SET_REG(ADR_GEMINIA_PMU_RTC_REG_3,_VAL_,0,0x00000000)
+#define SET_RO_GEMINIA_FDB_CDELAY(_VAL_) SET_REG(ADR_GEMINIA_PMU_FDB_REG_0,_VAL_,20,0xff0fffff)
+#define SET_RO_GEMINIA_FDB_FDELAY(_VAL_) SET_REG(ADR_GEMINIA_PMU_FDB_REG_0,_VAL_,24,0xf0ffffff)
+#define SET_RO_GEMINIA_FDB_PHASESWAP(_VAL_) SET_REG(ADR_GEMINIA_PMU_FDB_REG_0,_VAL_,31,0x7fffffff)
+#define SET_RG_GEMINIA_GPIO16_DS(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_0,_VAL_,0,0xfffffffe)
+#define SET_RG_GEMINIA_GPIO16_PD(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_0,_VAL_,1,0xfffffffd)
+#define SET_RG_GEMINIA_GPIO16_OE(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_0,_VAL_,2,0xfffffffb)
+#define SET_RG_GEMINIA_GPIO17_DS(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_0,_VAL_,4,0xffffffef)
+#define SET_RG_GEMINIA_GPIO17_PD(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_0,_VAL_,5,0xffffffdf)
+#define SET_RG_GEMINIA_GPIO17_OE(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_0,_VAL_,6,0xffffffbf)
+#define SET_RG_GEMINIA_GPIO18_DS(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_0,_VAL_,8,0xfffffeff)
+#define SET_RG_GEMINIA_GPIO18_PD(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_0,_VAL_,9,0xfffffdff)
+#define SET_RG_GEMINIA_GPIO18_OE(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_0,_VAL_,10,0xfffffbff)
+#define SET_RG_GEMINIA_GPIO19_DS(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_0,_VAL_,12,0xffffefff)
+#define SET_RG_GEMINIA_GPIO19_PD(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_0,_VAL_,13,0xffffdfff)
+#define SET_RG_GEMINIA_GPIO19_OE(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_0,_VAL_,14,0xffffbfff)
+#define SET_RG_GEMINIA_GPIO20_DS(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_0,_VAL_,16,0xfffeffff)
+#define SET_RG_GEMINIA_GPIO20_PD(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_0,_VAL_,17,0xfffdffff)
+#define SET_RG_GEMINIA_GPIO20_OE(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_0,_VAL_,18,0xfffbffff)
+#define SET_RG_GEMINIA_SPIS_MISO_DS(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_0,_VAL_,24,0xfeffffff)
+#define SET_RG_GEMINIA_FPGA_CLK_REF_40M_DS(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_0,_VAL_,28,0xefffffff)
+#define SET_RG_GEMINIA_FPGA_CLK_REF_40M_PD(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_0,_VAL_,29,0xdfffffff)
+#define SET_RG_GEMINIA_FPGA_CLK_REF_40M_OE(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_0,_VAL_,30,0xbfffffff)
+#define SET_RG_GEMINIA_GPIO08_DS(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,0,0xfffffffe)
+#define SET_RG_GEMINIA_GPIO08_PD(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,1,0xfffffffd)
+#define SET_RG_GEMINIA_GPIO08_OE(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,2,0xfffffffb)
+#define SET_RG_GEMINIA_GPIO09_DS(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,4,0xffffffef)
+#define SET_RG_GEMINIA_GPIO09_PD(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,5,0xffffffdf)
+#define SET_RG_GEMINIA_GPIO09_OE(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,6,0xffffffbf)
+#define SET_RG_GEMINIA_GPIO10_DS(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,8,0xfffffeff)
+#define SET_RG_GEMINIA_GPIO10_PD(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,9,0xfffffdff)
+#define SET_RG_GEMINIA_GPIO10_OE(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,10,0xfffffbff)
+#define SET_RG_GEMINIA_GPIO11_DS(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,12,0xffffefff)
+#define SET_RG_GEMINIA_GPIO11_PD(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,13,0xffffdfff)
+#define SET_RG_GEMINIA_GPIO11_OE(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,14,0xffffbfff)
+#define SET_RG_GEMINIA_GPIO12_DS(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,16,0xfffeffff)
+#define SET_RG_GEMINIA_GPIO12_PD(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,17,0xfffdffff)
+#define SET_RG_GEMINIA_GPIO12_OE(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,18,0xfffbffff)
+#define SET_RG_GEMINIA_GPIO13_DS(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,20,0xffefffff)
+#define SET_RG_GEMINIA_GPIO13_PD(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,21,0xffdfffff)
+#define SET_RG_GEMINIA_GPIO13_OE(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,22,0xffbfffff)
+#define SET_RG_GEMINIA_GPIO14_DS(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,24,0xfeffffff)
+#define SET_RG_GEMINIA_GPIO14_PD(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,25,0xfdffffff)
+#define SET_RG_GEMINIA_GPIO14_OE(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,26,0xfbffffff)
+#define SET_RG_GEMINIA_GPIO15_DS(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,28,0xefffffff)
+#define SET_RG_GEMINIA_GPIO15_PD(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,29,0xdfffffff)
+#define SET_RG_GEMINIA_GPIO15_OE(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,30,0xbfffffff)
+#define SET_RG_GEMINIA_GPIO00_DS(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,0,0xfffffffe)
+#define SET_RG_GEMINIA_GPIO00_PD(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,1,0xfffffffd)
+#define SET_RG_GEMINIA_GPIO00_OE(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,2,0xfffffffb)
+#define SET_RG_GEMINIA_GPIO01_DS(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,4,0xffffffef)
+#define SET_RG_GEMINIA_GPIO01_PD(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,5,0xffffffdf)
+#define SET_RG_GEMINIA_GPIO01_OE(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,6,0xffffffbf)
+#define SET_RG_GEMINIA_GPIO02_DS(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,8,0xfffffeff)
+#define SET_RG_GEMINIA_GPIO02_PD(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,9,0xfffffdff)
+#define SET_RG_GEMINIA_GPIO02_OE(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,10,0xfffffbff)
+#define SET_RG_GEMINIA_GPIO03_DS(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,12,0xffffefff)
+#define SET_RG_GEMINIA_GPIO03_PD(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,13,0xffffdfff)
+#define SET_RG_GEMINIA_GPIO03_OE(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,14,0xffffbfff)
+#define SET_RG_GEMINIA_GPIO04_DS(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,16,0xfffeffff)
+#define SET_RG_GEMINIA_GPIO04_PD(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,17,0xfffdffff)
+#define SET_RG_GEMINIA_GPIO04_OE(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,18,0xfffbffff)
+#define SET_RG_GEMINIA_GPIO05_DS(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,20,0xffefffff)
+#define SET_RG_GEMINIA_GPIO05_PD(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,21,0xffdfffff)
+#define SET_RG_GEMINIA_GPIO05_OE(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,22,0xffbfffff)
+#define SET_RG_GEMINIA_GPIO06_DS(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,24,0xfeffffff)
+#define SET_RG_GEMINIA_GPIO06_PD(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,25,0xfdffffff)
+#define SET_RG_GEMINIA_GPIO06_OE(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,26,0xfbffffff)
+#define SET_RG_GEMINIA_GPIO07_DS(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,28,0xefffffff)
+#define SET_RG_GEMINIA_GPIO07_PD(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,29,0xdfffffff)
+#define SET_RG_GEMINIA_GPIO07_OE(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,30,0xbfffffff)
+#define SET_RG_GEMINIA_RF_PHY_MODE_SEL(_VAL_) SET_REG(ADR_GEMINIA_MCU_REG_0,_VAL_,0,0xfffffffc)
+#define SET_RG_GEMINIA_RF_PHY_MODE_WIFI_MAC(_VAL_) SET_REG(ADR_GEMINIA_MCU_REG_0,_VAL_,4,0xffffff8f)
+#define SET_RG_GEMINIA_PAD_MUX_SEL(_VAL_) SET_REG(ADR_GEMINIA_MCU_REG_0,_VAL_,8,0xfffff0ff)
+#define SET_RG_GEMINIA_MODE_LATCH_LMT(_VAL_) SET_REG(ADR_GEMINIA_MCU_REG_0,_VAL_,12,0xffff8fff)
+#define SET_RG_GEMINIA_EXT_MCU_PWRUP(_VAL_) SET_REG(ADR_GEMINIA_MCU_REG_0,_VAL_,31,0x7fffffff)
+#define SET_RG_GEMINIA_RAM_00(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_00,_VAL_,0,0x00000000)
+#define SET_RG_GEMINIA_RAM_01(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_01,_VAL_,0,0x00000000)
+#define SET_RG_GEMINIA_RAM_02(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_02,_VAL_,0,0x00000000)
+#define SET_RG_GEMINIA_RAM_03(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_03,_VAL_,0,0x00000000)
+#define SET_RG_GEMINIA_RAM_04(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_04,_VAL_,0,0x00000000)
+#define SET_RG_GEMINIA_RAM_05(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_05,_VAL_,0,0x00000000)
+#define SET_RG_GEMINIA_RAM_06(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_06,_VAL_,0,0x00000000)
+#define SET_RG_GEMINIA_RAM_07(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_07,_VAL_,0,0x00000000)
+#define SET_RG_GEMINIA_RAM_08(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_08,_VAL_,0,0x00000000)
+#define SET_RG_GEMINIA_RAM_09(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_09,_VAL_,0,0x00000000)
+#define SET_RG_GEMINIA_RAM_10(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_10,_VAL_,0,0x00000000)
+#define SET_RG_GEMINIA_RAM_11(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_11,_VAL_,0,0x00000000)
+#define SET_RG_GEMINIA_RAM_12(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_12,_VAL_,0,0x00000000)
+#define SET_RG_GEMINIA_RAM_13(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_13,_VAL_,0,0x00000000)
+#define SET_RG_GEMINIA_RAM_14(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_14,_VAL_,0,0x00000000)
+#define SET_RG_GEMINIA_RAM_15(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_15,_VAL_,0,0x00000000)
+#define SET_RG_GEMINIA_RAM_16(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_16,_VAL_,0,0x00000000)
+#define SET_RG_GEMINIA_RAM_17(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_17,_VAL_,0,0x00000000)
+#define SET_RG_GEMINIA_RAM_18(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_18,_VAL_,0,0x00000000)
+#define SET_RG_GEMINIA_RAM_19(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_19,_VAL_,0,0x00000000)
+#define SET_RG_GEMINIA_RAM_20(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_20,_VAL_,0,0x00000000)
+#define SET_RG_GEMINIA_RAM_21(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_21,_VAL_,0,0x00000000)
+#define SET_RG_GEMINIA_RAM_22(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_22,_VAL_,0,0x00000000)
+#define SET_RG_GEMINIA_RAM_23(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_23,_VAL_,0,0x00000000)
+#define SET_RG_GEMINIA_RAM_24(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_24,_VAL_,0,0x00000000)
+#define SET_RG_GEMINIA_RAM_25(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_25,_VAL_,0,0x00000000)
+#define SET_RG_GEMINIA_RAM_26(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_26,_VAL_,0,0x00000000)
+#define SET_RG_GEMINIA_RAM_27(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_27,_VAL_,0,0x00000000)
+#define SET_RG_GEMINIA_RAM_28(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_28,_VAL_,0,0x00000000)
+#define SET_RG_GEMINIA_RAM_29(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_29,_VAL_,0,0x00000000)
+#define SET_RG_GEMINIA_RAM_30(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_30,_VAL_,0,0x00000000)
+#define SET_RG_GEMINIA_RAM_31(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_31,_VAL_,0,0x00000000)
+#define SET_RG_TURISMO_TRX_HW_PINSEL(_VAL_) SET_REG(ADR_TURISMO_TRX_MODE_REGISTER,_VAL_,0,0xfffffffe)
+#define SET_RG_TURISMO_TRX_HS_3WIRE_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_MODE_REGISTER,_VAL_,1,0xfffffffd)
+#define SET_RG_TURISMO_TRX_MODE_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_MODE_REGISTER,_VAL_,2,0xfffffffb)
+#define SET_RG_TURISMO_TRX_RX_GAIN_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_MODE_REGISTER,_VAL_,4,0xffffffef)
+#define SET_RG_TURISMO_TRX_TX_GAIN_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_MODE_REGISTER,_VAL_,5,0xffffffdf)
+#define SET_RG_TURISMO_TRX_TXGAIN_PHYCTRL(_VAL_) SET_REG(ADR_TURISMO_TRX_MODE_REGISTER,_VAL_,6,0xffffffbf)
+#define SET_RG_TURISMO_TRX_RX_AGC(_VAL_) SET_REG(ADR_TURISMO_TRX_MODE_REGISTER,_VAL_,7,0xffffff7f)
+#define SET_RG_TURISMO_TRX_MODE(_VAL_) SET_REG(ADR_TURISMO_TRX_MODE_REGISTER,_VAL_,8,0xfffff8ff)
+#define SET_RG_TURISMO_TRX_CAL_INDEX(_VAL_) SET_REG(ADR_TURISMO_TRX_MODE_REGISTER,_VAL_,12,0xffff0fff)
+#define SET_RG_TURISMO_TRX_RFG(_VAL_) SET_REG(ADR_TURISMO_TRX_MODE_REGISTER,_VAL_,16,0xfffcffff)
+#define SET_RG_TURISMO_TRX_PGAG(_VAL_) SET_REG(ADR_TURISMO_TRX_MODE_REGISTER,_VAL_,18,0xffc3ffff)
+#define SET_RG_TURISMO_TRX_BW_HT40(_VAL_) SET_REG(ADR_TURISMO_TRX_MODE_REGISTER,_VAL_,22,0xffbfffff)
+#define SET_RG_TURISMO_TRX_BW_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_MODE_REGISTER,_VAL_,23,0xff7fffff)
+#define SET_RG_TURISMO_TRX_TX_GAIN(_VAL_) SET_REG(ADR_TURISMO_TRX_MODE_REGISTER,_VAL_,24,0x80ffffff)
+#define SET_RG_TURISMO_TRX_TX_TRSW_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,0,0xfffffffe)
+#define SET_RG_TURISMO_TRX_EN_TX_TRSW(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,1,0xfffffffd)
+#define SET_RG_TURISMO_TRX_RX_LNA_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,2,0xfffffffb)
+#define SET_RG_TURISMO_TRX_EN_RX_LNA(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,3,0xfffffff7)
+#define SET_RG_TURISMO_TRX_RX_MIXER_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,4,0xffffffef)
+#define SET_RG_TURISMO_TRX_EN_RX_MIXER(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,5,0xffffffdf)
+#define SET_RG_TURISMO_TRX_RX_DIV2_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,6,0xffffffbf)
+#define SET_RG_TURISMO_TRX_EN_RX_DIV2(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,7,0xffffff7f)
+#define SET_RG_TURISMO_TRX_RX_LOBUF_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,8,0xfffffeff)
+#define SET_RG_TURISMO_TRX_EN_RX_LOBUF(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,9,0xfffffdff)
+#define SET_RG_TURISMO_TRX_RX_TZ_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,10,0xfffffbff)
+#define SET_RG_TURISMO_TRX_EN_RX_TZ(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,11,0xfffff7ff)
+#define SET_RG_TURISMO_TRX_RX_FILTER_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,12,0xffffefff)
+#define SET_RG_TURISMO_TRX_EN_RX_FILTER(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,13,0xffffdfff)
+#define SET_RG_TURISMO_TRX_RX_ADC_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,14,0xffffbfff)
+#define SET_RG_TURISMO_TRX_EN_RX_ADC(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,15,0xffff7fff)
+#define SET_RG_TURISMO_TRX_RX_RSSI_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,16,0xfffeffff)
+#define SET_RG_TURISMO_TRX_EN_RX_RSSI(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,17,0xfffdffff)
+#define SET_RG_TURISMO_TRX_TX_PA_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,18,0xfffbffff)
+#define SET_RG_TURISMO_TRX_EN_TX_PA(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,19,0xfff7ffff)
+#define SET_RG_TURISMO_TRX_TX_MOD_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,20,0xffefffff)
+#define SET_RG_TURISMO_TRX_EN_TX_MOD(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,21,0xffdfffff)
+#define SET_RG_TURISMO_TRX_TX_DAC_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,22,0xffbfffff)
+#define SET_RG_TURISMO_TRX_EN_TX_DAC(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,23,0xff7fffff)
+#define SET_RG_TURISMO_TRX_TX_DIV2_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,24,0xfeffffff)
+#define SET_RG_TURISMO_TRX_EN_TX_DIV2(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,25,0xfdffffff)
+#define SET_RG_TURISMO_TRX_TX_DIV2_BUF_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,26,0xfbffffff)
+#define SET_RG_TURISMO_TRX_EN_TX_DIV2_BUF(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,27,0xf7ffffff)
+#define SET_RG_TURISMO_TRX_TX_BT_PA_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,28,0xefffffff)
+#define SET_RG_TURISMO_TRX_EN_TX_BT_PA(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,29,0xdfffffff)
+#define SET_RG_TURISMO_TRX_EN_IOT_ADC_BUF(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,30,0xbfffffff)
+#define SET_RG_TURISMO_TRX_EN_IOT_ADC(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,31,0x7fffffff)
+#define SET_RG_TURISMO_TRX_EN_LDO_RX_FE(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,0,0xfffffffe)
+#define SET_RG_TURISMO_TRX_EN_LDO_AFE(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,1,0xfffffffd)
+#define SET_RG_TURISMO_TRX_EN_IREF_RX(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,2,0xfffffffb)
+#define SET_RG_TURISMO_TRX_TX_DAC_CAL_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,3,0xfffffff7)
+#define SET_RG_TURISMO_TRX_EN_TX_DAC_CAL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,4,0xffffffef)
+#define SET_RG_TURISMO_TRX_RX_TZ_OUT_TRISTATE_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,5,0xffffffdf)
+#define SET_RG_TURISMO_TRX_RX_TZ_OUT_TRISTATE(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,6,0xffffffbf)
+#define SET_RG_TURISMO_TRX_TX_SELF_MIXER_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,7,0xffffff7f)
+#define SET_RG_TURISMO_TRX_EN_TX_SELF_MIXER(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,8,0xfffffeff)
+#define SET_RG_TURISMO_TRX_RX_IQCAL_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,9,0xfffffdff)
+#define SET_RG_TURISMO_TRX_EN_RX_IQCAL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,10,0xfffffbff)
+#define SET_RG_TURISMO_TRX_TX_DPD_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,11,0xfffff7ff)
+#define SET_RG_TURISMO_TRX_EN_TX_DPD(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,12,0xffffefff)
+#define SET_RG_TURISMO_TRX_EN_TX_TSSI(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,14,0xffffbfff)
+#define SET_RG_TURISMO_TRX_EN_SARADC(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,15,0xffff7fff)
+#define SET_RG_TURISMO_TRX_EN_TX_VTOI_2ND(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,16,0xfffeffff)
+#define SET_RG_TURISMO_TRX_TXLPF_BYPASS(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,17,0xfffdffff)
+#define SET_RG_TURISMO_TRX_TX_EN_VOLTAGE_IN(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,18,0xfffbffff)
+#define SET_RG_TURISMO_TRX_EN_TX_DAC_OUT(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,19,0xfff7ffff)
+#define SET_RG_TURISMO_TRX_EN_TX_DAC_VOUT(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,20,0xffefffff)
+#define SET_RG_TURISMO_TRX_RX_ABBOUT_TRI_STATE(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,21,0xffdfffff)
+#define SET_RG_TURISMO_TRX_EN_RX_TESTNODE(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,22,0xffbfffff)
+#define SET_RG_TURISMO_TRX_EN_RX_PADSW(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,23,0xff7fffff)
+#define SET_RG_TURISMO_TRX_EN_LDO_RX_FE_FC(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,25,0xfdffffff)
+#define SET_RG_TURISMO_TRX_EN_LDO_RX_AFE_FC(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,26,0xfbffffff)
+#define SET_RG_TURISMO_TRX_EN_LDO_RX_FE_IQUP(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,27,0xf7ffffff)
+#define SET_RG_TURISMO_TRX_EN_LDO_RX_AFE_IQUP(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,28,0xefffffff)
+#define SET_RG_TURISMO_TRX_RX_SQDC(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,29,0x1fffffff)
+#define SET_RG_TURISMO_TRX_LDO_LEVEL_RX_FE(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_LDO_REGISTER,_VAL_,0,0xfffffff8)
+#define SET_RG_TURISMO_TRX_EN_LDO_RX_FE_BYP(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_LDO_REGISTER,_VAL_,3,0xfffffff7)
+#define SET_RG_TURISMO_TRX_LDO_LEVEL_AFE(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_LDO_REGISTER,_VAL_,4,0xffffff8f)
+#define SET_RG_TURISMO_TRX_EN_LDO_RX_AFE_BYP(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_LDO_REGISTER,_VAL_,7,0xffffff7f)
+#define SET_RG_TURISMO_TRX_TX_PA_LDO_LEVEL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_LDO_REGISTER,_VAL_,8,0xfffff8ff)
+#define SET_RG_TURISMO_TRX_DP_LDO_LEVEL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_LDO_REGISTER,_VAL_,12,0xffff8fff)
+#define SET_RG_TURISMO_TRX_EN_LDO_DP_BYP(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_LDO_REGISTER,_VAL_,15,0xffff7fff)
+#define SET_RG_TURISMO_TRX_SX_LDO_CP_LEVEL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_LDO_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_TURISMO_TRX_EN_LDO_CP_BYP(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_LDO_REGISTER,_VAL_,19,0xfff7ffff)
+#define SET_RG_TURISMO_TRX_SX_LDO_LO_LEVEL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_LDO_REGISTER,_VAL_,20,0xff8fffff)
+#define SET_RG_TURISMO_TRX_EN_LDO_LO_BYP(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_LDO_REGISTER,_VAL_,23,0xff7fffff)
+#define SET_RG_TURISMO_TRX_SX_LDO_VCO_LEVEL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_LDO_REGISTER,_VAL_,24,0xf8ffffff)
+#define SET_RG_TURISMO_TRX_SX_LDO_DIV_LEVEL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_LDO_REGISTER,_VAL_,28,0x8fffffff)
+#define SET_RG_TURISMO_TRX_EN_LDO_DIV_BYP(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_LDO_REGISTER,_VAL_,31,0x7fffffff)
+#define SET_RG_TURISMO_TRX_WF_RX_ABBCTUNE(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_WF_RX_FILTERI_COARSE(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,8,0xfffffcff)
+#define SET_RG_TURISMO_TRX_WF_RX_FILTERI1ST(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,10,0xfffff3ff)
+#define SET_RG_TURISMO_TRX_WF_RX_FILTERI2ND(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,12,0xffffcfff)
+#define SET_RG_TURISMO_TRX_WF_RX_FILTERI3RD(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,14,0xffff3fff)
+#define SET_RG_TURISMO_TRX_WF_RX_ABBCFIX(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,16,0xfffeffff)
+#define SET_RG_TURISMO_TRX_WF_RX_ABB_N_MODE(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,17,0xfffdffff)
+#define SET_RG_TURISMO_TRX_WF_RX_ABB_BT_MODE(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,18,0xfffbffff)
+#define SET_RG_TURISMO_TRX_WF_RX_ABB_IDIV3(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,19,0xfff7ffff)
+#define SET_RG_TURISMO_TRX_WF_RX_EN_IDACA_COARSE(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,20,0xffefffff)
+#define SET_RG_TURISMO_TRX_WF_RX_EN_LOOPA(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,21,0xffdfffff)
+#define SET_RG_TURISMO_TRX_WF_RX_FILTERVCM(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,24,0xf8ffffff)
+#define SET_RG_TURISMO_TRX_WF_RX_OUTVCM(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,28,0x8fffffff)
+#define SET_RG_TURISMO_TRX_WF_N_RX_ABBCTUNE(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_WF_N_RX_FILTERI_COARSE(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,8,0xfffffcff)
+#define SET_RG_TURISMO_TRX_WF_N_RX_FILTERI1ST(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,10,0xfffff3ff)
+#define SET_RG_TURISMO_TRX_WF_N_RX_FILTERI2ND(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,12,0xffffcfff)
+#define SET_RG_TURISMO_TRX_WF_N_RX_FILTERI3RD(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,14,0xffff3fff)
+#define SET_RG_TURISMO_TRX_WF_N_RX_ABBCFIX(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,16,0xfffeffff)
+#define SET_RG_TURISMO_TRX_WF_N_RX_ABB_N_MODE(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,17,0xfffdffff)
+#define SET_RG_TURISMO_TRX_WF_N_RX_ABB_BT_MODE(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,18,0xfffbffff)
+#define SET_RG_TURISMO_TRX_WF_N_RX_ABB_IDIV3(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,19,0xfff7ffff)
+#define SET_RG_TURISMO_TRX_WF_N_RX_EN_IDACA_COARSE(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,20,0xffefffff)
+#define SET_RG_TURISMO_TRX_WF_N_RX_EN_LOOPA(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,21,0xffdfffff)
+#define SET_RG_TURISMO_TRX_WF_N_RX_FILTERVCM(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,24,0xf8ffffff)
+#define SET_RG_TURISMO_TRX_WF_N_RX_OUTVCM(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,28,0x8fffffff)
+#define SET_RG_TURISMO_TRX_BT_RX_ABBCTUNE(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_BT_RX_FILTERI_COARSE(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER,_VAL_,8,0xfffffcff)
+#define SET_RG_TURISMO_TRX_BT_RX_FILTERI1ST(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER,_VAL_,10,0xfffff3ff)
+#define SET_RG_TURISMO_TRX_BT_RX_FILTERI2ND(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER,_VAL_,12,0xffffcfff)
+#define SET_RG_TURISMO_TRX_BT_RX_FILTERI3RD(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER,_VAL_,14,0xffff3fff)
+#define SET_RG_TURISMO_TRX_BT_RX_ABBCFIX(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER,_VAL_,16,0xfffeffff)
+#define SET_RG_TURISMO_TRX_BT_RX_ABB_N_MODE(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER,_VAL_,17,0xfffdffff)
+#define SET_RG_TURISMO_TRX_BT_RX_ABB_BT_MODE(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER,_VAL_,18,0xfffbffff)
+#define SET_RG_TURISMO_TRX_BT_RX_ABB_IDIV3(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER,_VAL_,19,0xfff7ffff)
+#define SET_RG_TURISMO_TRX_BT_RX_EN_IDACA_COARSE(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER,_VAL_,20,0xffefffff)
+#define SET_RG_TURISMO_TRX_BT_RX_EN_LOOPA(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER,_VAL_,21,0xffdfffff)
+#define SET_RG_TURISMO_TRX_BT_RX_FILTERVCM(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER,_VAL_,24,0xf8ffffff)
+#define SET_RG_TURISMO_TRX_BT_RX_OUTVCM(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER,_VAL_,28,0x8fffffff)
+#define SET_RG_TURISMO_TRX_RX_ADCRSSI_VCM(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_TURISMO_TRX_RX_REC_LPFCORNER(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_TURISMO_TRX_RX_ADCRSSI_CLKSEL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_REGISTER,_VAL_,4,0xffffffef)
+#define SET_RG_TURISMO_TRX_RSSI_CLOCK_GATING(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_REGISTER,_VAL_,5,0xffffffdf)
+#define SET_RG_TURISMO_TRX_RX_IDACA_COARSE_PMOS_ON(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_REGISTER,_VAL_,6,0xffffffbf)
+#define SET_RG_TURISMO_TRX_TX_DPDGM_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_REGISTER,_VAL_,8,0xfffff0ff)
+#define SET_RG_TURISMO_TRX_TX_DPD_DIV(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_REGISTER,_VAL_,12,0xffff0fff)
+#define SET_RG_TURISMO_TRX_TX_TSSI_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_TURISMO_TRX_TX_TSSI_DIV(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_REGISTER,_VAL_,19,0xffc7ffff)
+#define SET_RG_TURISMO_TRX_TX_TSSI_TEST(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_REGISTER,_VAL_,22,0xff3fffff)
+#define SET_RG_TURISMO_TRX_TX_TSSI_TESTMODE(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_REGISTER,_VAL_,24,0xfeffffff)
+#define SET_RG_TURISMO_TRX_EN_RX_RSSI_TESTNODE(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_REGISTER,_VAL_,25,0xf1ffffff)
+#define SET_RG_TURISMO_TRX_RX_LNA_TRI_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_REGISTER,_VAL_,28,0xcfffffff)
+#define SET_RG_TURISMO_TRX_RX_LNA_SETTLE(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_REGISTER,_VAL_,30,0x3fffffff)
+#define SET_RG_TURISMO_TRX_WF_TXPGA_CAPSW(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_TURISMO_TRX_WF_TX_DIV_VSET(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_TURISMO_TRX_WF_TX_LOBUF_VSET(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER,_VAL_,4,0xffffffcf)
+#define SET_RG_TURISMO_TRX_WF_TX_BTPASW(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER,_VAL_,6,0xffffffbf)
+#define SET_RG_TURISMO_TRX_WF_EN_TX_PA_VIN33(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER,_VAL_,7,0xffffff7f)
+#define SET_RG_TURISMO_TRX_BT_TXPGA_CAPSW(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER,_VAL_,12,0xffffcfff)
+#define SET_RG_TURISMO_TRX_BT_TX_DIV_VSET(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER,_VAL_,14,0xffff3fff)
+#define SET_RG_TURISMO_TRX_BT_TX_LOBUF_VSET(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER,_VAL_,16,0xfffcffff)
+#define SET_RG_TURISMO_TRX_BT_TX_BTPASW(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER,_VAL_,18,0xfffbffff)
+#define SET_RG_TURISMO_TRX_BT_EN_TX_PA_VIN33(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER,_VAL_,19,0xfff7ffff)
+#define SET_RG_TURISMO_TRX_TX_PA_LDO_SEL_RES(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER,_VAL_,24,0xfcffffff)
+#define SET_RG_TURISMO_TRX_EN_LDO_TX_PA(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER,_VAL_,26,0xfbffffff)
+#define SET_RG_TURISMO_TRX_EN_TX_PA_LDO_FC(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER,_VAL_,27,0xf7ffffff)
+#define SET_RG_TURISMO_TRX_EN_TX_PA_LDO_IQUP(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER,_VAL_,28,0xefffffff)
+#define SET_RG_TURISMO_TRX_EN_TX_PA_LDO_VTH(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER,_VAL_,29,0xdfffffff)
+#define SET_RG_TURISMO_TRX_WF_PACELL_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_PA_REGISTER,_VAL_,0,0xfffffff8)
+#define SET_RG_TURISMO_TRX_WF_PABIAS_CTRL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_PA_REGISTER,_VAL_,4,0xffffff0f)
+#define SET_RG_TURISMO_TRX_WF_TX_PA1_VCAS(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_PA_REGISTER,_VAL_,8,0xfffff8ff)
+#define SET_RG_TURISMO_TRX_WF_TX_PA2_VCAS(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_PA_REGISTER,_VAL_,12,0xffff8fff)
+#define SET_RG_TURISMO_TRX_WF_TX_PA3_VCAS(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_PA_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_TURISMO_TRX_BT_PABIAS_2X(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_PA_REGISTER,_VAL_,23,0xff7fffff)
+#define SET_RG_TURISMO_TRX_BT_PABIAS_CTRL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_PA_REGISTER,_VAL_,24,0xf0ffffff)
+#define SET_RG_TURISMO_TRX_BT_TX_PA_VCAS(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_PA_REGISTER,_VAL_,28,0xcfffffff)
+#define SET_RG_TURISMO_TRX_BT_TX_MOD_CS(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_PA_REGISTER,_VAL_,30,0x3fffffff)
+#define SET_RG_TURISMO_TRX_TXPGA_MAIN(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_REGISTER,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_TXPGA_STEER(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_REGISTER,_VAL_,6,0xfffff03f)
+#define SET_RG_TURISMO_TRX_TXMOD_GMCELL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_REGISTER,_VAL_,12,0xffffcfff)
+#define SET_RG_TURISMO_TRX_TXLPF_GMCELL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_REGISTER,_VAL_,14,0xffff3fff)
+#define SET_RG_TURISMO_TRX_WF_TX_GAIN_OFFSET(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_REGISTER,_VAL_,16,0xfff0ffff)
+#define SET_RG_TURISMO_TRX_BT_TX_GAIN_OFFSET(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_REGISTER,_VAL_,20,0xff0fffff)
+#define SET_RG_TURISMO_TRX_TX_VTOI_CURRENT(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_REGISTER,_VAL_,24,0xfcffffff)
+#define SET_RG_TURISMO_TRX_TX_VTOI_GM(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_REGISTER,_VAL_,26,0xf3ffffff)
+#define SET_RG_TURISMO_TRX_TX_VTOI_OPTION(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_REGISTER,_VAL_,28,0xcfffffff)
+#define SET_RG_TURISMO_TRX_TX_VTOI_FS(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_REGISTER,_VAL_,30,0xbfffffff)
+#define SET_RG_TURISMO_TRX_WF_RX_HG_LNA_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_TURISMO_TRX_WF_RX_HG_TZ_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_TURISMO_TRX_WF_RX_HG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER,_VAL_,4,0xffffff0f)
+#define SET_RG_TURISMO_TRX_WF_RX_HG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER,_VAL_,8,0xfffff0ff)
+#define SET_RG_TURISMO_TRX_WF_RX_HG_LNALG_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER,_VAL_,12,0xffff0fff)
+#define SET_RG_TURISMO_TRX_WF_RX_HG_TZ_CAP(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_TURISMO_TRX_WF_RX_HG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER,_VAL_,20,0xffcfffff)
+#define SET_RG_TURISMO_TRX_WF_RX_HG_DIV2_CORE(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER,_VAL_,22,0xff3fffff)
+#define SET_RG_TURISMO_TRX_WF_RX_HG_LOBUF(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER,_VAL_,24,0xfcffffff)
+#define SET_RG_TURISMO_TRX_WF_RX_HG_TZI(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER,_VAL_,26,0xe3ffffff)
+#define SET_RG_TURISMO_TRX_WF_RX_HG_TZ_VCM(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER,_VAL_,29,0x1fffffff)
+#define SET_RG_TURISMO_TRX_WF_RX_MG_LNA_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_TURISMO_TRX_WF_RX_MG_TZ_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_TURISMO_TRX_WF_RX_MG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER,_VAL_,4,0xffffff0f)
+#define SET_RG_TURISMO_TRX_WF_RX_MG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER,_VAL_,8,0xfffff0ff)
+#define SET_RG_TURISMO_TRX_WF_RX_MG_LNALG_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER,_VAL_,12,0xffff0fff)
+#define SET_RG_TURISMO_TRX_WF_RX_MG_TZ_CAP(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_TURISMO_TRX_WF_RX_MG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER,_VAL_,20,0xffcfffff)
+#define SET_RG_TURISMO_TRX_WF_RX_MG_DIV2_CORE(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER,_VAL_,22,0xff3fffff)
+#define SET_RG_TURISMO_TRX_WF_RX_MG_LOBUF(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER,_VAL_,24,0xfcffffff)
+#define SET_RG_TURISMO_TRX_WF_RX_MG_TZI(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER,_VAL_,26,0xe3ffffff)
+#define SET_RG_TURISMO_TRX_WF_RX_MG_TZ_VCM(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER,_VAL_,29,0x1fffffff)
+#define SET_RG_TURISMO_TRX_WF_RX_LG_LNA_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_TURISMO_TRX_WF_RX_LG_TZ_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_TURISMO_TRX_WF_RX_LG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER,_VAL_,4,0xffffff0f)
+#define SET_RG_TURISMO_TRX_WF_RX_LG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER,_VAL_,8,0xfffff0ff)
+#define SET_RG_TURISMO_TRX_WF_RX_LG_LNALG_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER,_VAL_,12,0xffff0fff)
+#define SET_RG_TURISMO_TRX_WF_RX_LG_TZ_CAP(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_TURISMO_TRX_WF_RX_LG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER,_VAL_,20,0xffcfffff)
+#define SET_RG_TURISMO_TRX_WF_RX_LG_DIV2_CORE(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER,_VAL_,22,0xff3fffff)
+#define SET_RG_TURISMO_TRX_WF_RX_LG_LOBUF(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER,_VAL_,24,0xfcffffff)
+#define SET_RG_TURISMO_TRX_WF_RX_LG_TZI(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER,_VAL_,26,0xe3ffffff)
+#define SET_RG_TURISMO_TRX_WF_RX_LG_TZ_VCM(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER,_VAL_,29,0x1fffffff)
+#define SET_RG_TURISMO_TRX_WF_RX_ULG_LNA_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_TURISMO_TRX_WF_RX_ULG_TZ_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_TURISMO_TRX_WF_RX_ULG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER,_VAL_,4,0xffffff0f)
+#define SET_RG_TURISMO_TRX_WF_RX_ULG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER,_VAL_,8,0xfffff0ff)
+#define SET_RG_TURISMO_TRX_WF_RX_ULG_LNALG_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER,_VAL_,12,0xffff0fff)
+#define SET_RG_TURISMO_TRX_WF_RX_ULG_TZ_CAP(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_TURISMO_TRX_WF_RX_ULG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER,_VAL_,20,0xffcfffff)
+#define SET_RG_TURISMO_TRX_WF_RX_ULG_DIV2_CORE(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER,_VAL_,22,0xff3fffff)
+#define SET_RG_TURISMO_TRX_WF_RX_ULG_LOBUF(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER,_VAL_,24,0xfcffffff)
+#define SET_RG_TURISMO_TRX_WF_RX_ULG_TZI(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER,_VAL_,26,0xe3ffffff)
+#define SET_RG_TURISMO_TRX_WF_RX_ULG_TZ_VCM(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER,_VAL_,29,0x1fffffff)
+#define SET_RG_TURISMO_TRX_BT_RX_HG_LNA_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_TURISMO_TRX_BT_RX_HG_TZ_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_TURISMO_TRX_BT_RX_HG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER,_VAL_,4,0xffffff0f)
+#define SET_RG_TURISMO_TRX_BT_RX_HG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER,_VAL_,8,0xfffff0ff)
+#define SET_RG_TURISMO_TRX_BT_RX_HG_LNALG_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER,_VAL_,12,0xffff0fff)
+#define SET_RG_TURISMO_TRX_BT_RX_HG_TZ_CAP(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_TURISMO_TRX_BT_RX_HG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER,_VAL_,20,0xffcfffff)
+#define SET_RG_TURISMO_TRX_BT_RX_HG_DIV2_CORE(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER,_VAL_,22,0xff3fffff)
+#define SET_RG_TURISMO_TRX_BT_RX_HG_LOBUF(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER,_VAL_,24,0xfcffffff)
+#define SET_RG_TURISMO_TRX_BT_RX_HG_TZI(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER,_VAL_,26,0xe3ffffff)
+#define SET_RG_TURISMO_TRX_BT_RX_HG_TZ_VCM(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER,_VAL_,29,0x1fffffff)
+#define SET_RG_TURISMO_TRX_BT_RX_MG_LNA_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_TURISMO_TRX_BT_RX_MG_TZ_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_TURISMO_TRX_BT_RX_MG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER,_VAL_,4,0xffffff0f)
+#define SET_RG_TURISMO_TRX_BT_RX_MG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER,_VAL_,8,0xfffff0ff)
+#define SET_RG_TURISMO_TRX_BT_RX_MG_LNALG_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER,_VAL_,12,0xffff0fff)
+#define SET_RG_TURISMO_TRX_BT_RX_MG_TZ_CAP(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_TURISMO_TRX_BT_RX_MG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER,_VAL_,20,0xffcfffff)
+#define SET_RG_TURISMO_TRX_BT_RX_MG_DIV2_CORE(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER,_VAL_,22,0xff3fffff)
+#define SET_RG_TURISMO_TRX_BT_RX_MG_LOBUF(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER,_VAL_,24,0xfcffffff)
+#define SET_RG_TURISMO_TRX_BT_RX_MG_TZI(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER,_VAL_,26,0xe3ffffff)
+#define SET_RG_TURISMO_TRX_BT_RX_MG_TZ_VCM(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER,_VAL_,29,0x1fffffff)
+#define SET_RG_TURISMO_TRX_BT_RX_LG_LNA_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_TURISMO_TRX_BT_RX_LG_TZ_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_TURISMO_TRX_BT_RX_LG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER,_VAL_,4,0xffffff0f)
+#define SET_RG_TURISMO_TRX_BT_RX_LG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER,_VAL_,8,0xfffff0ff)
+#define SET_RG_TURISMO_TRX_BT_RX_LG_LNALG_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER,_VAL_,12,0xffff0fff)
+#define SET_RG_TURISMO_TRX_BT_RX_LG_TZ_CAP(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_TURISMO_TRX_BT_RX_LG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER,_VAL_,20,0xffcfffff)
+#define SET_RG_TURISMO_TRX_BT_RX_LG_DIV2_CORE(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER,_VAL_,22,0xff3fffff)
+#define SET_RG_TURISMO_TRX_BT_RX_LG_LOBUF(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER,_VAL_,24,0xfcffffff)
+#define SET_RG_TURISMO_TRX_BT_RX_LG_TZI(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER,_VAL_,26,0xe3ffffff)
+#define SET_RG_TURISMO_TRX_BT_RX_LG_TZ_VCM(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER,_VAL_,29,0x1fffffff)
+#define SET_RG_TURISMO_TRX_BT_RX_ULG_LNA_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_TURISMO_TRX_BT_RX_ULG_TZ_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_TURISMO_TRX_BT_RX_ULG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER,_VAL_,4,0xffffff0f)
+#define SET_RG_TURISMO_TRX_BT_RX_ULG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER,_VAL_,8,0xfffff0ff)
+#define SET_RG_TURISMO_TRX_BT_RX_ULG_LNALG_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER,_VAL_,12,0xffff0fff)
+#define SET_RG_TURISMO_TRX_BT_RX_ULG_TZ_CAP(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_TURISMO_TRX_BT_RX_ULG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER,_VAL_,20,0xffcfffff)
+#define SET_RG_TURISMO_TRX_BT_RX_ULG_DIV2_CORE(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER,_VAL_,22,0xff3fffff)
+#define SET_RG_TURISMO_TRX_BT_RX_ULG_LOBUF(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER,_VAL_,24,0xfcffffff)
+#define SET_RG_TURISMO_TRX_BT_RX_ULG_TZI(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER,_VAL_,26,0xe3ffffff)
+#define SET_RG_TURISMO_TRX_BT_RX_ULG_TZ_VCM(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER,_VAL_,29,0x1fffffff)
+#define SET_RG_TURISMO_TRX_RX_ADC_CLKSEL(_VAL_) SET_REG(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER,_VAL_,0,0xfffffffe)
+#define SET_RG_TURISMO_TRX_RX_ADC_DNLEN(_VAL_) SET_REG(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER,_VAL_,1,0xfffffffd)
+#define SET_RG_TURISMO_TRX_RX_ADC_METAEN(_VAL_) SET_REG(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER,_VAL_,2,0xfffffffb)
+#define SET_RG_TURISMO_TRX_RX_ADC_TFLAG(_VAL_) SET_REG(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER,_VAL_,3,0xfffffff7)
+#define SET_RG_TURISMO_TRX_RX_ADC_TSEL(_VAL_) SET_REG(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER,_VAL_,4,0xffffff0f)
+#define SET_RG_TURISMO_TRX_WF_RX_ADC_ICMP(_VAL_) SET_REG(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER,_VAL_,8,0xfffffcff)
+#define SET_RG_TURISMO_TRX_WF_RX_ADC_VCMI(_VAL_) SET_REG(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER,_VAL_,10,0xfffff3ff)
+#define SET_RG_TURISMO_TRX_WF_RX_ADC_CLOAD(_VAL_) SET_REG(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER,_VAL_,12,0xffffcfff)
+#define SET_RG_TURISMO_TRX_BT_RX_ADC_ICMP(_VAL_) SET_REG(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER,_VAL_,16,0xfffcffff)
+#define SET_RG_TURISMO_TRX_BT_RX_ADC_VCMI(_VAL_) SET_REG(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER,_VAL_,18,0xfff3ffff)
+#define SET_RG_TURISMO_TRX_BT_RX_ADC_CLOAD(_VAL_) SET_REG(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER,_VAL_,20,0xffcfffff)
+#define SET_RG_TURISMO_TRX_SARADC_5G_TSSI(_VAL_) SET_REG(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER,_VAL_,23,0xff7fffff)
+#define SET_RG_TURISMO_TRX_SARADC_VRSEL(_VAL_) SET_REG(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER,_VAL_,24,0xfcffffff)
+#define SET_RG_TURISMO_TRX_EN_SAR_TEST(_VAL_) SET_REG(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER,_VAL_,26,0xf3ffffff)
+#define SET_RG_TURISMO_TRX_SARADC_THERMAL(_VAL_) SET_REG(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER,_VAL_,28,0xefffffff)
+#define SET_RG_TURISMO_TRX_SARADC_TSSI(_VAL_) SET_REG(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER,_VAL_,29,0xdfffffff)
+#define SET_RG_TURISMO_TRX_CLK_SAR_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER,_VAL_,30,0x3fffffff)
+#define SET_RG_TURISMO_TRX_WF_TX_DACI1ST(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_TURISMO_TRX_WF_TX_DACLPF_ICOARSE(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_TURISMO_TRX_WF_TX_DACLPF_IFINE(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER,_VAL_,4,0xffffffcf)
+#define SET_RG_TURISMO_TRX_WF_TX_DACLPF_VCM(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER,_VAL_,6,0xffffff3f)
+#define SET_RG_TURISMO_TRX_WF_TX_DAC_IBIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER,_VAL_,8,0xfffffcff)
+#define SET_RG_TURISMO_TRX_WF_TX_DAC_IATTN(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER,_VAL_,10,0xfffffbff)
+#define SET_RG_TURISMO_TRX_WF_TXLPF_BOOSTI(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER,_VAL_,11,0xfffff7ff)
+#define SET_RG_TURISMO_TRX_WF_TX_DAC_RCAL(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER,_VAL_,12,0xffffcfff)
+#define SET_RG_TURISMO_TRX_WF_TX_DAC_CKEDGE_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER,_VAL_,14,0xffffbfff)
+#define SET_RG_TURISMO_TRX_WF_TX_DAC_OS(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_TURISMO_TRX_WF_TX_DAC_IOFFSET(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER,_VAL_,20,0xff0fffff)
+#define SET_RG_TURISMO_TRX_WF_TX_DAC_QOFFSET(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER,_VAL_,24,0xf0ffffff)
+#define SET_RG_TURISMO_TRX_TX_DAC_TSEL(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER,_VAL_,28,0x0fffffff)
+#define SET_RG_TURISMO_TRX_BT_TX_DACI1ST(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_TURISMO_TRX_BT_TX_DACLPF_ICOARSE(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_TURISMO_TRX_BT_TX_DACLPF_IFINE(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER,_VAL_,4,0xffffffcf)
+#define SET_RG_TURISMO_TRX_BT_TX_DACLPF_VCM(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER,_VAL_,6,0xffffff3f)
+#define SET_RG_TURISMO_TRX_BT_TX_DAC_IBIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER,_VAL_,8,0xfffffcff)
+#define SET_RG_TURISMO_TRX_BT_TX_DAC_IATTN(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER,_VAL_,10,0xfffffbff)
+#define SET_RG_TURISMO_TRX_BT_TXLPF_BOOSTI(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER,_VAL_,11,0xfffff7ff)
+#define SET_RG_TURISMO_TRX_BT_TX_DAC_RCAL(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER,_VAL_,12,0xffffcfff)
+#define SET_RG_TURISMO_TRX_BT_TX_DAC_CKEDGE_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER,_VAL_,14,0xffffbfff)
+#define SET_RG_TURISMO_TRX_BT_TX_DAC_OS(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_TURISMO_TRX_BT_TX_DAC_IOFFSET(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER,_VAL_,20,0xff0fffff)
+#define SET_RG_TURISMO_TRX_BT_TX_DAC_QOFFSET(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER,_VAL_,24,0xf0ffffff)
+#define SET_RG_TURISMO_TRX_SX_EN_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,0,0xfffffffe)
+#define SET_RG_TURISMO_TRX_SX_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,1,0xfffffffd)
+#define SET_RG_TURISMO_TRX_EN_SX_CP_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,2,0xfffffffb)
+#define SET_RG_TURISMO_TRX_EN_SX_CP(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,3,0xfffffff7)
+#define SET_RG_TURISMO_TRX_EN_SX_DIV_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,4,0xffffffef)
+#define SET_RG_TURISMO_TRX_EN_SX_DIV(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,5,0xffffffdf)
+#define SET_RG_TURISMO_TRX_EN_SX_VCO_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,6,0xffffffbf)
+#define SET_RG_TURISMO_TRX_EN_SX_VCO(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,7,0xffffff7f)
+#define SET_RG_TURISMO_TRX_SX_PFD_RST_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,8,0xfffffeff)
+#define SET_RG_TURISMO_TRX_SX_PFD_RST(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,9,0xfffffdff)
+#define SET_RG_TURISMO_TRX_SX_UOP_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,10,0xfffffbff)
+#define SET_RG_TURISMO_TRX_SX_UOP_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,11,0xfffff7ff)
+#define SET_RG_TURISMO_TRX_EN_VCOBF_TXMB_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,12,0xffffefff)
+#define SET_RG_TURISMO_TRX_EN_VCOBF_TXMB(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,13,0xffffdfff)
+#define SET_RG_TURISMO_TRX_EN_VCOBF_TXOB_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,14,0xffffbfff)
+#define SET_RG_TURISMO_TRX_EN_VCOBF_TXOB(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,15,0xffff7fff)
+#define SET_RG_TURISMO_TRX_EN_VCOBF_RXMB_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,16,0xfffeffff)
+#define SET_RG_TURISMO_TRX_EN_VCOBF_RXMB(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,17,0xfffdffff)
+#define SET_RG_TURISMO_TRX_EN_VCOBF_RXOB_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,18,0xfffbffff)
+#define SET_RG_TURISMO_TRX_EN_VCOBF_RXOB(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,19,0xfff7ffff)
+#define SET_RG_TURISMO_TRX_EN_VCOBF_DIVCK_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,20,0xffefffff)
+#define SET_RG_TURISMO_TRX_EN_VCOBF_DIVCK(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,21,0xffdfffff)
+#define SET_RG_TURISMO_TRX_SX_SBCAL_DIS(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,23,0xff7fffff)
+#define SET_RG_TURISMO_TRX_SX_SBCAL_AW(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,24,0xfeffffff)
+#define SET_RG_TURISMO_TRX_SX_AAC_DIS(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,26,0xfbffffff)
+#define SET_RG_TURISMO_TRX_SX_TTL_DIS(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,27,0xf7ffffff)
+#define SET_RG_TURISMO_TRX_SX_CAL_INIT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,29,0x1fffffff)
+#define SET_RG_TURISMO_TRX_EN_SX_LDO_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER,_VAL_,0,0xfffffffe)
+#define SET_RG_TURISMO_TRX_EN_LDO_CP(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER,_VAL_,1,0xfffffffd)
+#define SET_RG_TURISMO_TRX_EN_LDO_DIV(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER,_VAL_,2,0xfffffffb)
+#define SET_RG_TURISMO_TRX_EN_LDO_LO(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER,_VAL_,3,0xfffffff7)
+#define SET_RG_TURISMO_TRX_EN_LDO_VCO(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER,_VAL_,4,0xffffffef)
+#define SET_RG_TURISMO_TRX_EN_LDO_VCO_PSW(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER,_VAL_,9,0xfffffdff)
+#define SET_RG_TURISMO_TRX_EN_LDO_VCO_VDD33(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER,_VAL_,10,0xfffffbff)
+#define SET_RG_TURISMO_TRX_EN_LDO_CP_IQUP(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER,_VAL_,11,0xfffff7ff)
+#define SET_RG_TURISMO_TRX_EN_LDO_DIV_IQUP(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER,_VAL_,12,0xffffefff)
+#define SET_RG_TURISMO_TRX_EN_LDO_LO_IQUP(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER,_VAL_,13,0xffffdfff)
+#define SET_RG_TURISMO_TRX_EN_LDO_VCO_IQUP(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER,_VAL_,14,0xffffbfff)
+#define SET_RG_TURISMO_TRX_SX_LDO_FCOFFT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER,_VAL_,19,0xffc7ffff)
+#define SET_RG_TURISMO_TRX_LDO_CP_FC_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER,_VAL_,22,0xffbfffff)
+#define SET_RG_TURISMO_TRX_LDO_CP_FC(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER,_VAL_,23,0xff7fffff)
+#define SET_RG_TURISMO_TRX_LDO_DIV_FC_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER,_VAL_,24,0xfeffffff)
+#define SET_RG_TURISMO_TRX_LDO_DIV_FC(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER,_VAL_,25,0xfdffffff)
+#define SET_RG_TURISMO_TRX_LDO_LO_FC_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER,_VAL_,26,0xfbffffff)
+#define SET_RG_TURISMO_TRX_LDO_LO_FC(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER,_VAL_,27,0xf7ffffff)
+#define SET_RG_TURISMO_TRX_LDO_VCO_FC_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER,_VAL_,28,0xefffffff)
+#define SET_RG_TURISMO_TRX_LDO_VCO_FC(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER,_VAL_,29,0xdfffffff)
+#define SET_RG_TURISMO_TRX_LDO_VCO_RCF(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER,_VAL_,30,0x3fffffff)
+#define SET_RG_TURISMO_TRX_SX_RFCTRL_F(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_FRACTIONAL_AND_INTEGER_8BITS,_VAL_,0,0xff000000)
+#define SET_RG_TURISMO_TRX_SX_RFCTRL_CH_7_0(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_FRACTIONAL_AND_INTEGER_8BITS,_VAL_,24,0x00ffffff)
+#define SET_RG_TURISMO_TRX_SX_RFCTRL_CH_10_8(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE,_VAL_,0,0xfffffff8)
+#define SET_RG_TURISMO_TRX_SX_RFCH_MAP_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE,_VAL_,3,0xfffffff7)
+#define SET_RG_TURISMO_TRX_SX_XTAL_FREQ(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE,_VAL_,5,0xffffff9f)
+#define SET_RG_TURISMO_TRX_SX_FREF_DOUB(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE,_VAL_,7,0xffffff7f)
+#define SET_RG_TURISMO_TRX_SX_BTRX_SIDE(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE,_VAL_,8,0xfffffeff)
+#define SET_RG_TURISMO_TRX_SX_LO_TIMES(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE,_VAL_,9,0xfffffdff)
+#define SET_RG_TURISMO_TRX_SX_CHANNEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE,_VAL_,11,0xfff807ff)
+#define SET_RG_TURISMO_TRX_SX_CP_ISEL_BT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_,_VAL_,0,0xfffffff0)
+#define SET_RG_TURISMO_TRX_SX_CP_ISEL50U_BT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_,_VAL_,4,0xffffffef)
+#define SET_RG_TURISMO_TRX_SX_CP_KP_DOUB_BT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_,_VAL_,5,0xffffffdf)
+#define SET_RG_TURISMO_TRX_SX_CP_ISEL_WF(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_,_VAL_,7,0xfffff87f)
+#define SET_RG_TURISMO_TRX_SX_CP_ISEL50U_WF(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_,_VAL_,11,0xfffff7ff)
+#define SET_RG_TURISMO_TRX_SX_CP_KP_DOUB_WF(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_,_VAL_,12,0xffffefff)
+#define SET_RG_TURISMO_TRX_SX_CP_IOST_POL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_,_VAL_,15,0xffff7fff)
+#define SET_RG_TURISMO_TRX_SX_CP_IOST(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_,_VAL_,16,0xfff8ffff)
+#define SET_RG_TURISMO_TRX_SX_PFD_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_,_VAL_,22,0xffbfffff)
+#define SET_RG_TURISMO_TRX_SX_PFD_SET(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_,_VAL_,23,0xff7fffff)
+#define SET_RG_TURISMO_TRX_SX_PFD_SET1(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_,_VAL_,24,0xfeffffff)
+#define SET_RG_TURISMO_TRX_SX_PFD_SET2(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_,_VAL_,25,0xfdffffff)
+#define SET_RG_TURISMO_TRX_SX_PFD_REF_EDGE(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_,_VAL_,26,0xfbffffff)
+#define SET_RG_TURISMO_TRX_SX_PFD_DIV_EDGE(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_,_VAL_,27,0xf7ffffff)
+#define SET_RG_TURISMO_TRX_SX_PFD_TRUP(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_,_VAL_,28,0xefffffff)
+#define SET_RG_TURISMO_TRX_SX_PFD_TRDN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_,_VAL_,29,0xdfffffff)
+#define SET_RG_TURISMO_TRX_SX_PFD_TLSEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_,_VAL_,30,0xbfffffff)
+#define SET_RG_TURISMO_TRX_SX_LPF_C1_BT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_LPF,_VAL_,0,0xfffffff0)
+#define SET_RG_TURISMO_TRX_SX_LPF_C2_BT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_LPF,_VAL_,4,0xffffff0f)
+#define SET_RG_TURISMO_TRX_SX_LPF_C3_BT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_LPF,_VAL_,8,0xfffffeff)
+#define SET_RG_TURISMO_TRX_SX_LPF_R2_BT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_LPF,_VAL_,9,0xffffe1ff)
+#define SET_RG_TURISMO_TRX_SX_LPF_R3_BT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_LPF,_VAL_,13,0xffff1fff)
+#define SET_RG_TURISMO_TRX_SX_LPF_C1_WF(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_LPF,_VAL_,16,0xfff0ffff)
+#define SET_RG_TURISMO_TRX_SX_LPF_C2_WF(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_LPF,_VAL_,20,0xff0fffff)
+#define SET_RG_TURISMO_TRX_SX_LPF_C3_WF(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_LPF,_VAL_,24,0xfeffffff)
+#define SET_RG_TURISMO_TRX_SX_LPF_R2_WF(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_LPF,_VAL_,25,0xe1ffffff)
+#define SET_RG_TURISMO_TRX_SX_LPF_R3_WF(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_LPF,_VAL_,29,0x1fffffff)
+#define SET_RG_TURISMO_TRX_SX_VCO_ISEL_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCO,_VAL_,0,0xfffffffe)
+#define SET_RG_TURISMO_TRX_SX_VCO_ISEL_BT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCO,_VAL_,1,0xffffffe1)
+#define SET_RG_TURISMO_TRX_SX_VCO_LPM_BT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCO,_VAL_,5,0xffffffdf)
+#define SET_RG_TURISMO_TRX_SX_VCO_VCCBSEL_BT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCO,_VAL_,6,0xfffffe3f)
+#define SET_RG_TURISMO_TRX_SX_VCO_KVDOUB_BT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCO,_VAL_,9,0xfffffdff)
+#define SET_RG_TURISMO_TRX_SX_VCO_ISEL_WF(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCO,_VAL_,10,0xffffc3ff)
+#define SET_RG_TURISMO_TRX_SX_VCO_LPM_WF(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCO,_VAL_,14,0xffffbfff)
+#define SET_RG_TURISMO_TRX_SX_VCO_VCCBSEL_WF(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCO,_VAL_,15,0xfffc7fff)
+#define SET_RG_TURISMO_TRX_SX_VCO_KVDOUB_WF(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCO,_VAL_,18,0xfffbffff)
+#define SET_RG_TURISMO_TRX_SX_VCO_VARBSEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCO,_VAL_,21,0xff9fffff)
+#define SET_RG_TURISMO_TRX_SX_VCO_RTAIL_SHIFT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCO,_VAL_,23,0xff7fffff)
+#define SET_RG_TURISMO_TRX_SX_VCO_CS_AWH(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCO,_VAL_,24,0xfeffffff)
+#define SET_RG_TURISMO_TRX_VOBF_TXMBSEL_BT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCOBF,_VAL_,0,0xfffffffc)
+#define SET_RG_TURISMO_TRX_VOBF_TXOBSEL_BT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCOBF,_VAL_,2,0xfffffff3)
+#define SET_RG_TURISMO_TRX_VOBF_RXMBSEL_BT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCOBF,_VAL_,4,0xffffffcf)
+#define SET_RG_TURISMO_TRX_VOBF_RXOBSEL_BT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCOBF,_VAL_,6,0xffffff3f)
+#define SET_RG_TURISMO_TRX_VOBF_TXMBSEL_WF(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCOBF,_VAL_,10,0xfffff3ff)
+#define SET_RG_TURISMO_TRX_VOBF_TXOBSEL_WF(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCOBF,_VAL_,12,0xffffcfff)
+#define SET_RG_TURISMO_TRX_VOBF_RXMBSEL_WF(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCOBF,_VAL_,14,0xffff3fff)
+#define SET_RG_TURISMO_TRX_VOBF_RXOBSEL_WF(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCOBF,_VAL_,16,0xfffcffff)
+#define SET_RG_TURISMO_TRX_VOBF_DIVBFSEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCOBF,_VAL_,19,0xfff7ffff)
+#define SET_RG_TURISMO_TRX_SX_VCO_TXOB_AW(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCOBF,_VAL_,20,0xffefffff)
+#define SET_RG_TURISMO_TRX_SX_VCO_RXOB_AW(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCOBF,_VAL_,21,0xffdfffff)
+#define SET_RG_TURISMO_TRX_VOBF_CAPIMB_POL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCOBF,_VAL_,26,0xfbffffff)
+#define SET_RG_TURISMO_TRX_VOBF_CAPIMB(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCOBF,_VAL_,27,0xc7ffffff)
+#define SET_RG_TURISMO_TRX_EN_SX_VCOMON(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCOBF,_VAL_,31,0x7fffffff)
+#define SET_RG_TURISMO_TRX_SX_DIV_PREVDD(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_DIV_SDM,_VAL_,0,0xfffffff0)
+#define SET_RG_TURISMO_TRX_SX_DIV_PSCVDD(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_DIV_SDM,_VAL_,4,0xffffff0f)
+#define SET_RG_TURISMO_TRX_SX_DIV_RST_H(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_DIV_SDM,_VAL_,9,0xfffffdff)
+#define SET_RG_TURISMO_TRX_SX_DIV_SDM_EDGE(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_DIV_SDM,_VAL_,10,0xfffffbff)
+#define SET_RG_TURISMO_TRX_SX_DIV_DMYBUF_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_DIV_SDM,_VAL_,11,0xfffff7ff)
+#define SET_RG_TURISMO_TRX_EN_SX_MOD(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_DIV_SDM,_VAL_,17,0xfffdffff)
+#define SET_RG_TURISMO_TRX_EN_SX_DITHER(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_DIV_SDM,_VAL_,18,0xfffbffff)
+#define SET_RG_TURISMO_TRX_SX_MOD_ORDER(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_DIV_SDM,_VAL_,19,0xffe7ffff)
+#define SET_RG_TURISMO_TRX_SX_DITHER_WEIGHT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_DIV_SDM,_VAL_,21,0xff9fffff)
+#define SET_RG_TURISMO_TRX_SX_SUB_SEL_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_SBCAL,_VAL_,0,0xfffffffe)
+#define SET_RG_TURISMO_TRX_SX_SUB_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_SBCAL,_VAL_,1,0xfffffe01)
+#define SET_RG_TURISMO_TRX_SX_SUB_C0P5_DIS(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_SBCAL,_VAL_,9,0xfffffdff)
+#define SET_RG_TURISMO_TRX_SX_SBCAL_CT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_SBCAL,_VAL_,10,0xfffff3ff)
+#define SET_RG_TURISMO_TRX_SX_SBCAL_WT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_SBCAL,_VAL_,12,0xffffefff)
+#define SET_RG_TURISMO_TRX_SX_SBCAL_DIFFMIN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_SBCAL,_VAL_,13,0xffffdfff)
+#define SET_RG_TURISMO_TRX_SX_SBCAL_NTARG_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_SBCAL,_VAL_,15,0xffff7fff)
+#define SET_RG_TURISMO_TRX_SX_SBCAL_NTARG(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_SBCAL,_VAL_,16,0x0000ffff)
+#define SET_RG_TURISMO_TRX_VO_AAC_TAR_BT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_AAC,_VAL_,0,0xfffffff0)
+#define SET_RG_TURISMO_TRX_VO_AAC_IOST_BT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_AAC,_VAL_,4,0xffffffcf)
+#define SET_RG_TURISMO_TRX_VO_AAC_TAR_WF(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_AAC,_VAL_,7,0xfffff87f)
+#define SET_RG_TURISMO_TRX_VO_AAC_IOST_WF(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_AAC,_VAL_,11,0xffffe7ff)
+#define SET_RG_TURISMO_TRX_VO_AAC_IMAX(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_AAC,_VAL_,14,0xfffc3fff)
+#define SET_RG_TURISMO_TRX_VO_AAC_INIT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_AAC,_VAL_,18,0xfff3ffff)
+#define SET_RG_TURISMO_TRX_VO_AAC_EVA_TS(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_AAC,_VAL_,20,0xffcfffff)
+#define SET_RG_TURISMO_TRX_VO_AAC_EN_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_AAC,_VAL_,23,0xff7fffff)
+#define SET_RG_TURISMO_TRX_VO_AAC_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_AAC,_VAL_,24,0xfeffffff)
+#define SET_RG_TURISMO_TRX_VO_AAC_EVA_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_AAC,_VAL_,25,0xfdffffff)
+#define SET_RG_TURISMO_TRX_VO_AAC_EVA(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_AAC,_VAL_,26,0xfbffffff)
+#define SET_RG_TURISMO_TRX_VO_AAC_TEST_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_AAC,_VAL_,28,0xefffffff)
+#define SET_RG_TURISMO_TRX_VO_AAC_TEST_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_AAC,_VAL_,29,0xdfffffff)
+#define SET_RG_TURISMO_TRX_SX_TTL_INIT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_TTL,_VAL_,0,0xfffffffc)
+#define SET_RG_TURISMO_TRX_SX_TTL_FPT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_TTL,_VAL_,2,0xfffffff3)
+#define SET_RG_TURISMO_TRX_SX_TTL_CPT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_TTL,_VAL_,4,0xffffffcf)
+#define SET_RG_TURISMO_TRX_SX_TTL_ACCUM(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_TTL,_VAL_,7,0xfffffe7f)
+#define SET_RG_TURISMO_TRX_SX_TTL_SUB(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_TTL,_VAL_,10,0xfffff3ff)
+#define SET_RG_TURISMO_TRX_SX_TTL_SUB_INV(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_TTL,_VAL_,12,0xffffefff)
+#define SET_RG_TURISMO_TRX_SX_TTL_VH(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_TTL,_VAL_,14,0xffff3fff)
+#define SET_RG_TURISMO_TRX_SX_TTL_VL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_TTL,_VAL_,16,0xfffcffff)
+#define SET_RG_TURISMO_TRX_SX_LPF_VTUNE_TEST(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_TTL,_VAL_,19,0xfff7ffff)
+#define SET_RG_TURISMO_TRX_DP_BBPLL_PD(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_TOP_REGISTER,_VAL_,0,0xfffffffe)
+#define SET_RG_TURISMO_TRX_DP_BBPLL_BP(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_TOP_REGISTER,_VAL_,1,0xfffffffd)
+#define SET_RG_TURISMO_TRX_EN_DP_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_TOP_REGISTER,_VAL_,2,0xfffffffb)
+#define SET_RG_TURISMO_TRX_DP_FREF_DOUB(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_TOP_REGISTER,_VAL_,3,0xfffffff7)
+#define SET_RG_TURISMO_TRX_DP_DAC320_DIVBY2(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_TOP_REGISTER,_VAL_,4,0xffffffef)
+#define SET_RG_TURISMO_TRX_DP_ADC320_DIVBY2_BT(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_TOP_REGISTER,_VAL_,5,0xffffffdf)
+#define SET_RG_TURISMO_TRX_DP_ADC320_DIVBY2_WF(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_TOP_REGISTER,_VAL_,6,0xffffffbf)
+#define SET_RG_TURISMO_TRX_EN_DPL_MOD(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_TOP_REGISTER,_VAL_,8,0xfffffeff)
+#define SET_RG_TURISMO_TRX_DPL_MOD_ORDER(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_TOP_REGISTER,_VAL_,9,0xfffff9ff)
+#define SET_RG_TURISMO_TRX_DP_REFDIV(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_TOP_REGISTER,_VAL_,11,0xfffc07ff)
+#define SET_RG_TURISMO_TRX_DP_FODIV(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_TOP_REGISTER,_VAL_,18,0xfe03ffff)
+#define SET_RG_TURISMO_TRX_EN_LDO_DP_IQUP(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_TOP_REGISTER,_VAL_,26,0xfbffffff)
+#define SET_RG_TURISMO_TRX_DP_OD_TEST(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_TOP_REGISTER,_VAL_,27,0xf7ffffff)
+#define SET_RG_TURISMO_TRX_DP_BBPLL_TESTSEL(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_TOP_REGISTER,_VAL_,28,0x8fffffff)
+#define SET_RG_TURISMO_TRX_DP_BBPLL_ICP(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_CKT_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_TURISMO_TRX_DP_BBPLL_IDUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_CKT_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_TURISMO_TRX_DP_CP_IOSTPOL(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_CKT_REGISTER,_VAL_,4,0xffffffef)
+#define SET_RG_TURISMO_TRX_DP_CP_IOST(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_CKT_REGISTER,_VAL_,5,0xffffff9f)
+#define SET_RG_TURISMO_TRX_DP_PFD_PFDSEL(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_CKT_REGISTER,_VAL_,7,0xffffff7f)
+#define SET_RG_TURISMO_TRX_DP_BBPLL_PFD_DLY(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_CKT_REGISTER,_VAL_,8,0xfffffcff)
+#define SET_RG_TURISMO_TRX_DP_RP(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_CKT_REGISTER,_VAL_,11,0xffffc7ff)
+#define SET_RG_TURISMO_TRX_DP_RHP(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_CKT_REGISTER,_VAL_,14,0xffff3fff)
+#define SET_RG_TURISMO_TRX_EN_DP_VT_MON(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_CKT_REGISTER,_VAL_,17,0xfffdffff)
+#define SET_RG_TURISMO_TRX_DP_VT_TH_HI(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_CKT_REGISTER,_VAL_,18,0xfff3ffff)
+#define SET_RG_TURISMO_TRX_DP_VT_TH_LO(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_CKT_REGISTER,_VAL_,20,0xffcfffff)
+#define SET_RG_TURISMO_TRX_DP_BBPLL_BS(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_CKT_REGISTER,_VAL_,23,0xe07fffff)
+#define SET_RG_TURISMO_TRX_DP_BBPLL_SDM_EDGE(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_CKT_REGISTER,_VAL_,31,0x7fffffff)
+#define SET_RG_TURISMO_TRX_DPL_RFCTRL_F(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_FB_DIVISION__REGISTERS,_VAL_,0,0xff000000)
+#define SET_RG_TURISMO_TRX_DPL_RFCTRL_CH(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_FB_DIVISION__REGISTERS,_VAL_,24,0x00ffffff)
+#define SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG15(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER1,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG15(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER1,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG14(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER1,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG14(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER1,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG13(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER2,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG13(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER2,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG12(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER2,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG12(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER2,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG11(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER3,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG11(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER3,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG10(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER3,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG10(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER3,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG9(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER4,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG9(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER4,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG8(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER4,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG8(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER4,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG7(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER5,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG7(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER5,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG6(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER5,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG6(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER5,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG5(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER6,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG5(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER6,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG4(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER6,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG4(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER6,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG3(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER7,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG3(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER7,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG2(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER7,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG2(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER7,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG1(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER8,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG1(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER8,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG0(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER8,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG0(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER8,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG15(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER9,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG15(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER9,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG14(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER9,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG14(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER9,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG13(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER10,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG13(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER10,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG12(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER10,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG12(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER10,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG11(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER11,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG11(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER11,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG10(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER11,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG10(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER11,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG9(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER12,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG9(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER12,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG8(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER12,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG8(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER12,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG7(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER13,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG7(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER13,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG6(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER13,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG6(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER13,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG5(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER14,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG5(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER14,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG4(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER14,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG4(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER14,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG3(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER15,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG3(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER15,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG2(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER15,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG2(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER15,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG1(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER16,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG1(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER16,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG0(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER16,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG0(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER16,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_IDACAI_TZ0_COARSE4(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER17,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_IDACAQ_TZ0_COARSE4(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER17,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_IDACAI_TZ0_COARSE3(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER17,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_IDACAQ_TZ0_COARSE3(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER17,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_IDACAI_TZ0_COARSE2(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER18,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_IDACAQ_TZ0_COARSE2(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER18,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_IDACAI_TZ0_COARSE1(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER18,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_IDACAQ_TZ0_COARSE1(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER18,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_IDACAI_TZ0_COARSE0(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER19,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_IDACAQ_TZ0_COARSE0(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER19,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_IDACAI_TZ1_COARSE4(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER19,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_IDACAQ_TZ1_COARSE4(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER19,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_IDACAI_TZ1_COARSE3(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER20,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_IDACAQ_TZ1_COARSE3(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER20,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_IDACAI_TZ1_COARSE2(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER20,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_IDACAQ_TZ1_COARSE2(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER20,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_IDACAI_TZ1_COARSE1(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER21,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_IDACAQ_TZ1_COARSE1(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER21,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_IDACAI_TZ1_COARSE0(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER21,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_IDACAQ_TZ1_COARSE0(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER21,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG15(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER1,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG15(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER1,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG14(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER1,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG14(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER1,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG13(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER2,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG13(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER2,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG12(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER2,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG12(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER2,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG11(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER3,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG11(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER3,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG10(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER3,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG10(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER3,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG9(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER4,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG9(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER4,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG8(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER4,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG8(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER4,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG7(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER5,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG7(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER5,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG6(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER5,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG6(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER5,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG5(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER6,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG5(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER6,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG4(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER6,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG4(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER6,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG3(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER7,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG3(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER7,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG2(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER7,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG2(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER7,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG1(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER8,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG1(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER8,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG0(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER8,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG0(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER8,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG15(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER9,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG15(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER9,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG14(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER9,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG14(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER9,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG13(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER10,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG13(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER10,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG12(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER10,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG12(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER10,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG11(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER11,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG11(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER11,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG10(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER11,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG10(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER11,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG9(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER12,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG9(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER12,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG8(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER12,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG8(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER12,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG7(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER13,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG7(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER13,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG6(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER13,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG6(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER13,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG5(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER14,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG5(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER14,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG4(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER14,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG4(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER14,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG3(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER15,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG3(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER15,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG2(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER15,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG2(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER15,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG1(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER16,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG1(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER16,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG0(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER16,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG0(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER16,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_SX_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_MODE_DECODER_TIMER_REGISTER1,_VAL_,0,0xfffffff0)
+#define SET_RG_TURISMO_TRX_TXDAC_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_MODE_DECODER_TIMER_REGISTER1,_VAL_,4,0xffffff0f)
+#define SET_RG_TURISMO_TRX_TXRF_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_MODE_DECODER_TIMER_REGISTER1,_VAL_,8,0xfffff0ff)
+#define SET_RG_TURISMO_TRX_TXPA_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_MODE_DECODER_TIMER_REGISTER1,_VAL_,12,0xffff0fff)
+#define SET_RG_TURISMO_TRX_RXRF_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_MODE_DECODER_TIMER_REGISTER1,_VAL_,16,0xfff0ffff)
+#define SET_RG_TURISMO_TRX_TXBTPA_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_MODE_DECODER_TIMER_REGISTER1,_VAL_,20,0xff0fffff)
+#define SET_RG_TURISMO_TRX_TXDAC_T2R_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_T2R_TIMER_REGISTER,_VAL_,0,0xffffffe0)
+#define SET_RG_TURISMO_TRX_TXRF_T2R_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_T2R_TIMER_REGISTER,_VAL_,8,0xffffe0ff)
+#define SET_RG_TURISMO_TRX_TXPA_T2R_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_T2R_TIMER_REGISTER,_VAL_,16,0xffe0ffff)
+#define SET_RG_TURISMO_TRX_RXRF_T2R_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_T2R_TIMER_REGISTER,_VAL_,24,0xe0ffffff)
+#define SET_RG_TURISMO_TRX_TXDAC_R2T_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_R2T_TIMER_REGISTER,_VAL_,0,0xffffffe0)
+#define SET_RG_TURISMO_TRX_TXRF_R2T_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_R2T_TIMER_REGISTER,_VAL_,8,0xffffe0ff)
+#define SET_RG_TURISMO_TRX_TXPA_R2T_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_R2T_TIMER_REGISTER,_VAL_,16,0xffe0ffff)
+#define SET_RG_TURISMO_TRX_RXRF_R2T_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_R2T_TIMER_REGISTER,_VAL_,24,0xe0ffffff)
+#define SET_RG_TURISMO_TRX_WF_RX_DCCAL_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_TIMER_REGISTER,_VAL_,0,0xfffffff8)
+#define SET_RG_TURISMO_TRX_BT_RX_DCCAL_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_TIMER_REGISTER,_VAL_,4,0xffffff8f)
+#define SET_RG_TURISMO_TRX_RX_RCCAL_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_TIMER_REGISTER,_VAL_,8,0xfffff8ff)
+#define SET_RG_TURISMO_TRX_TX_DCCAL_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_TIMER_REGISTER,_VAL_,12,0xffff8fff)
+#define SET_RG_TURISMO_TRX_TX_IQCAL_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_TIMER_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_TURISMO_TRX_RX_IQCAL_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_TIMER_REGISTER,_VAL_,20,0xff8fffff)
+#define SET_RG_TURISMO_TRX_RX_N_RCCAL_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_TIMER_REGISTER,_VAL_,24,0xf8ffffff)
+#define SET_RG_TURISMO_TRX_PGAG_RCCAL(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER0,_VAL_,0,0xfffffff0)
+#define SET_RG_TURISMO_TRX_PGAG_TXCAL(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER0,_VAL_,4,0xffffff0f)
+#define SET_RG_TURISMO_TRX_TX_GAIN_TXCAL(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER0,_VAL_,8,0xffff80ff)
+#define SET_RG_TURISMO_TRX_RFG_RXIQCAL(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER0,_VAL_,16,0xfffcffff)
+#define SET_RG_TURISMO_TRX_PGAG_RXIQCAL(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER0,_VAL_,18,0xffc3ffff)
+#define SET_RG_TURISMO_TRX_TX_GAIN_RXIQCAL(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER0,_VAL_,22,0xe03fffff)
+#define SET_RG_TURISMO_TRX_RFG_DPDCAL(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1,_VAL_,0,0xfffffffc)
+#define SET_RG_TURISMO_TRX_PGAG_DPDCAL(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1,_VAL_,2,0xffffffc3)
+#define SET_RG_TURISMO_TRX_TX_GAIN_DPDCAL(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1,_VAL_,6,0xffffe03f)
+#define SET_RG_TURISMO_TRX_IOT_ADC_CLKSEL(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1,_VAL_,16,0xfffeffff)
+#define SET_RG_TURISMO_TRX_IOT_ADC_DNLEN(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1,_VAL_,17,0xfffdffff)
+#define SET_RG_TURISMO_TRX_IOT_ADC_METAEN(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1,_VAL_,18,0xfffbffff)
+#define SET_RG_TURISMO_TRX_IOT_ADC_TFLAG(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1,_VAL_,19,0xfff7ffff)
+#define SET_RG_TURISMO_TRX_IOT_ADC_ICMP(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1,_VAL_,20,0xffcfffff)
+#define SET_RG_TURISMO_TRX_IOT_ADC_VCMI(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1,_VAL_,22,0xff3fffff)
+#define SET_RG_TURISMO_TRX_IOT_ADC_CLOAD(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1,_VAL_,24,0xfcffffff)
+#define SET_RG_TURISMO_TRX_IOT_ADC_CLK_DIV(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1,_VAL_,26,0xf3ffffff)
+#define SET_RG_TURISMO_TRX_IOT_ADC_CLK_SH_DUTY(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1,_VAL_,28,0xefffffff)
+#define SET_DB_TURISMO_TRX_AD_ADC_I_OUT(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_ADC,_VAL_,0,0xfffffc00)
+#define SET_DB_TURISMO_TRX_AD_ADC_Q_OUT(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_ADC,_VAL_,10,0xfff003ff)
+#define SET_DB_TURISMO_TRX_AD_RX_RSSIADC(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_ADC,_VAL_,20,0xff0fffff)
+#define SET_DB_TURISMO_TRX_DA_SARADC_BIT(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_ADC,_VAL_,24,0xc0ffffff)
+#define SET_TURISMO_TRX_SAR_ADC_FSM_RDY(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_ADC,_VAL_,30,0xbfffffff)
+#define SET_DB_TURISMO_TRX_DA_SX_SUB_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_1,_VAL_,0,0xffffff00)
+#define SET_DB_TURISMO_TRX_DA_SX_VCO_ISEL(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_1,_VAL_,8,0xfffff0ff)
+#define SET_DB_TURISMO_TRX_VO_AAC_COMPOUT(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_1,_VAL_,12,0xffffefff)
+#define SET_DB_TURISMO_TRX_SX_TTL_VT_DET(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_1,_VAL_,14,0xffff3fff)
+#define SET_DB_TURISMO_TRX_AD_DP_VT_MON_Q(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_1,_VAL_,16,0xfffcffff)
+#define SET_DB_TURISMO_TRX_AD_IOT_ADC_OUT(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_1,_VAL_,20,0xc00fffff)
+#define SET_DB_TURISMO_TRX_SX_SBCAL_NCOUNT(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_2,_VAL_,0,0xffff0000)
+#define SET_DB_TURISMO_TRX_SX_SBCAL_NTARGET(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_2,_VAL_,16,0x0000ffff)
+#define SET_RG_TURISMO_TRX_5G_TX_TRSW_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,0,0xfffffffe)
+#define SET_RG_TURISMO_TRX_5G_EN_TX_TRSW(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,1,0xfffffffd)
+#define SET_RG_TURISMO_TRX_5G_RX_LNA_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,2,0xfffffffb)
+#define SET_RG_TURISMO_TRX_5G_EN_RX_LNA(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,3,0xfffffff7)
+#define SET_RG_TURISMO_TRX_5G_RX_MIXER_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,4,0xffffffef)
+#define SET_RG_TURISMO_TRX_5G_EN_RX_MIXER(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,5,0xffffffdf)
+#define SET_RG_TURISMO_TRX_5G_RX_DIV2_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,6,0xffffffbf)
+#define SET_RG_TURISMO_TRX_5G_EN_RX_DIV2(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,7,0xffffff7f)
+#define SET_RG_TURISMO_TRX_5G_RX_LOBUF_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,8,0xfffffeff)
+#define SET_RG_TURISMO_TRX_5G_EN_RX_LOBUF(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,9,0xfffffdff)
+#define SET_RG_TURISMO_TRX_5G_RX_TZ_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,10,0xfffffbff)
+#define SET_RG_TURISMO_TRX_5G_EN_RX_TZ(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,11,0xfffff7ff)
+#define SET_RG_TURISMO_TRX_5G_TX_PA_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,12,0xffffefff)
+#define SET_RG_TURISMO_TRX_5G_EN_TX_PA(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,13,0xffffdfff)
+#define SET_RG_TURISMO_TRX_5G_TX_MOD_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,14,0xffffbfff)
+#define SET_RG_TURISMO_TRX_5G_EN_TX_MOD(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,15,0xffff7fff)
+#define SET_RG_TURISMO_TRX_5G_TX_DIV2_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,18,0xfffbffff)
+#define SET_RG_TURISMO_TRX_5G_EN_TX_DIV2(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,19,0xfff7ffff)
+#define SET_RG_TURISMO_TRX_5G_TX_DIV2_BUF_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,20,0xffefffff)
+#define SET_RG_TURISMO_TRX_5G_EN_TX_DIV2_BUF(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,21,0xffdfffff)
+#define SET_RG_TURISMO_TRX_5G_RX_TZ_OUT_TRISTATE_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,22,0xffbfffff)
+#define SET_RG_TURISMO_TRX_5G_RX_TZ_OUT_TRISTATE(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,23,0xff7fffff)
+#define SET_RG_TURISMO_TRX_5G_TX_SELF_MIXER_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,24,0xfeffffff)
+#define SET_RG_TURISMO_TRX_5G_EN_TX_SELF_MIXER(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,25,0xfdffffff)
+#define SET_RG_TURISMO_TRX_5G_RX_IQCAL_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,26,0xfbffffff)
+#define SET_RG_TURISMO_TRX_5G_EN_RX_IQCAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,27,0xf7ffffff)
+#define SET_RG_TURISMO_TRX_5G_TX_DPD_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,28,0xefffffff)
+#define SET_RG_TURISMO_TRX_5G_EN_TX_DPD(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,29,0xdfffffff)
+#define SET_RG_TURISMO_TRX_5G_EN_TX_TSSI(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,30,0xbfffffff)
+#define SET_RG_TURISMO_TRX_5G_LDO_LEVEL_RX_FE(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_LDO_REGISTER,_VAL_,0,0xfffffff8)
+#define SET_RG_TURISMO_TRX_5G_EN_LDO_RX_FE_BYP(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_LDO_REGISTER,_VAL_,3,0xfffffff7)
+#define SET_RG_TURISMO_TRX_SX5GB_LDO_CP_LEVEL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_LDO_REGISTER,_VAL_,4,0xffffff8f)
+#define SET_RG_TURISMO_TRX_EN_LDO_5G_CP_BYP(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_LDO_REGISTER,_VAL_,7,0xffffff7f)
+#define SET_RG_TURISMO_TRX_SX5GB_LDO_LO_LEVEL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_LDO_REGISTER,_VAL_,8,0xfffff8ff)
+#define SET_RG_TURISMO_TRX_EN_LDO_5G_LO_BYP(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_LDO_REGISTER,_VAL_,11,0xfffff7ff)
+#define SET_RG_TURISMO_TRX_SX5GB_LDO_VCO_LEVEL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_LDO_REGISTER,_VAL_,12,0xffff8fff)
+#define SET_RG_TURISMO_TRX_SX5GB_LDO_DIV_LEVEL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_LDO_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_TURISMO_TRX_EN_LDO_5G_DIV_BYP(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_LDO_REGISTER,_VAL_,19,0xfff7ffff)
+#define SET_RG_TURISMO_TRX_5G_EN_LDO_RX_FE(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_LDO_REGISTER,_VAL_,24,0xfeffffff)
+#define SET_RG_TURISMO_TRX_5G_EN_IREF_RX(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_LDO_REGISTER,_VAL_,25,0xfdffffff)
+#define SET_RG_TURISMO_TRX_5G_EN_LDO_RX_FE_FC(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_LDO_REGISTER,_VAL_,26,0xfbffffff)
+#define SET_RG_TURISMO_TRX_5G_EN_LDO_RX_FE_IQUP(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_LDO_REGISTER,_VAL_,27,0xf7ffffff)
+#define SET_RG_TURISMO_TRX_5G_RX_SCA_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_REGISTER1,_VAL_,0,0xfffffffe)
+#define SET_RG_TURISMO_TRX_5G_RX_SCA_MA(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_REGISTER1,_VAL_,1,0xfffffff1)
+#define SET_RG_TURISMO_TRX_5G_RX_SCA_LOAD(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_REGISTER1,_VAL_,4,0xffffff8f)
+#define SET_RG_TURISMO_TRX_5G_RX_LNA_TRI_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_REGISTER1,_VAL_,8,0xfffffcff)
+#define SET_RG_TURISMO_TRX_5G_RX_LNA_SETTLE(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_REGISTER1,_VAL_,10,0xfffff3ff)
+#define SET_RG_TURISMO_TRX_5G_RX_GM_IDB(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_REGISTER1,_VAL_,12,0xffffefff)
+#define SET_RG_TURISMO_TRX_5G_GM_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_REGISTER1,_VAL_,13,0xffff9fff)
+#define SET_RG_TURISMO_TRX_5G_RX_DIV2_BUF(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_REGISTER1,_VAL_,16,0xfffcffff)
+#define SET_RG_TURISMO_TRX_5G_RX_DIV2_CML(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_REGISTER1,_VAL_,18,0xfff3ffff)
+#define SET_RG_TURISMO_TRX_5G_RX_DIV_CMLISEL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_REGISTER1,_VAL_,20,0xffcfffff)
+#define SET_RG_TURISMO_TRX_5G_RX_DIV_PREBUFS2(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_REGISTER1,_VAL_,22,0xffbfffff)
+#define SET_RG_TURISMO_TRX_5G_RX_TZ_COURSE(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_REGISTER1,_VAL_,24,0xfcffffff)
+#define SET_RG_TURISMO_TRX_5G_TX_DPDGM_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_REGISTER1,_VAL_,28,0x0fffffff)
+#define SET_RG_TURISMO_TRX_5G_TX_DPD_DIV(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_REGISTER2,_VAL_,0,0xfffffff0)
+#define SET_RG_TURISMO_TRX_5G_TX_TSSI_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_REGISTER2,_VAL_,4,0xffffff8f)
+#define SET_RG_TURISMO_TRX_5G_TX_TSSI_DIV(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_REGISTER2,_VAL_,8,0xfffff8ff)
+#define SET_RG_TURISMO_TRX_5G_TX_TSSI_TEST(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_REGISTER2,_VAL_,12,0xffffcfff)
+#define SET_RG_TURISMO_TRX_5G_TX_TSSI_TESTMODE(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_REGISTER2,_VAL_,14,0xffffbfff)
+#define SET_RG_TURISMO_TRX_5G_RX_ADC_ICMP(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_REGISTER2,_VAL_,16,0xfffcffff)
+#define SET_RG_TURISMO_TRX_5G_RX_ADC_VCMI(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_REGISTER2,_VAL_,18,0xfff3ffff)
+#define SET_RG_TURISMO_TRX_5G_RX_ADC_CLOAD(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_REGISTER2,_VAL_,20,0xffcfffff)
+#define SET_RG_TURISMO_TRX_5G_TXPGA_CAPSW_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_FE_REGISTER,_VAL_,0,0xfffffffe)
+#define SET_RG_TURISMO_TRX_5G_TXPGA_CAPSW(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_FE_REGISTER,_VAL_,1,0xfffffff1)
+#define SET_RG_TURISMO_TRX_5G_TX_ADDGMCELL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_FE_REGISTER,_VAL_,4,0xffffffef)
+#define SET_RG_TURISMO_TRX_5G_PACELL_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_FE_REGISTER,_VAL_,5,0xffffff1f)
+#define SET_RG_TURISMO_TRX_5G_PABIAS_CTRL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_FE_REGISTER,_VAL_,8,0xfffff0ff)
+#define SET_RG_TURISMO_TRX_5G_TX_PAFB_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_FE_REGISTER,_VAL_,12,0xffffefff)
+#define SET_RG_TURISMO_TRX_5G_TX_PA1_VCAS(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_FE_REGISTER,_VAL_,13,0xffff1fff)
+#define SET_RG_TURISMO_TRX_5G_TX_PA2_VCAS(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_FE_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_TURISMO_TRX_5G_TX_PA3_VCAS(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_FE_REGISTER,_VAL_,20,0xff8fffff)
+#define SET_RG_TURISMO_TRX_5G_TX_DIV_PREBUFS2(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_FE_REGISTER,_VAL_,23,0xff7fffff)
+#define SET_RG_TURISMO_TRX_5G_TX_DIV_CMLISEL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_FE_REGISTER,_VAL_,24,0xfcffffff)
+#define SET_RG_TURISMO_TRX_5G_TX_DIV_CMLVSEL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_FE_REGISTER,_VAL_,26,0xf3ffffff)
+#define SET_RG_TURISMO_TRX_5G_TX_DIV_VSET(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_FE_REGISTER,_VAL_,28,0xcfffffff)
+#define SET_RG_TURISMO_TRX_5G_TX_LOBUF_VSET(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_FE_REGISTER,_VAL_,30,0x3fffffff)
+#define SET_RG_TURISMO_TRX_5G_TXPGA_MAIN(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_REGISTER,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_5G_TXPGA_STEER(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_REGISTER,_VAL_,6,0xfffff03f)
+#define SET_RG_TURISMO_TRX_5G_TXMOD_GMCELL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_REGISTER,_VAL_,12,0xffffcfff)
+#define SET_RG_TURISMO_TRX_5G_TX_GAIN_OFFSET(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_REGISTER,_VAL_,16,0xfff0ffff)
+#define SET_RG_TURISMO_TRX_5G_TX_GAIN(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_REGISTER,_VAL_,20,0xf80fffff)
+#define SET_RG_TURISMO_TRX_5G_RX_HG_LNA_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_TURISMO_TRX_5G_RX_HG_TZ_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_TURISMO_TRX_5G_RX_HG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER,_VAL_,4,0xffffff0f)
+#define SET_RG_TURISMO_TRX_5G_RX_HG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER,_VAL_,8,0xfffff0ff)
+#define SET_RG_TURISMO_TRX_5G_RX_HG_LNALG_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER,_VAL_,12,0xffff0fff)
+#define SET_RG_TURISMO_TRX_5G_RX_HG_TZ_CAP(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_TURISMO_TRX_5G_RX_HG_SQDC(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER,_VAL_,19,0xffc7ffff)
+#define SET_RG_TURISMO_TRX_5G_RX_HG_DIV2_CORE(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER,_VAL_,22,0xff3fffff)
+#define SET_RG_TURISMO_TRX_5G_RX_HG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER,_VAL_,24,0xfcffffff)
+#define SET_RG_TURISMO_TRX_5G_RX_HG_TZI(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER,_VAL_,26,0xe3ffffff)
+#define SET_RG_TURISMO_TRX_5G_RX_HG_TZ_VCM(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER,_VAL_,29,0x1fffffff)
+#define SET_RG_TURISMO_TRX_5G_RX_MG_LNA_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_TURISMO_TRX_5G_RX_MG_TZ_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_TURISMO_TRX_5G_RX_MG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER,_VAL_,4,0xffffff0f)
+#define SET_RG_TURISMO_TRX_5G_RX_MG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER,_VAL_,8,0xfffff0ff)
+#define SET_RG_TURISMO_TRX_5G_RX_MG_LNALG_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER,_VAL_,12,0xffff0fff)
+#define SET_RG_TURISMO_TRX_5G_RX_MG_TZ_CAP(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_TURISMO_TRX_5G_RX_MG_SQDC(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER,_VAL_,19,0xffc7ffff)
+#define SET_RG_TURISMO_TRX_5G_RX_MG_DIV2_CORE(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER,_VAL_,22,0xff3fffff)
+#define SET_RG_TURISMO_TRX_5G_RX_MG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER,_VAL_,24,0xfcffffff)
+#define SET_RG_TURISMO_TRX_5G_RX_MG_TZI(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER,_VAL_,26,0xe3ffffff)
+#define SET_RG_TURISMO_TRX_5G_RX_MG_TZ_VCM(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER,_VAL_,29,0x1fffffff)
+#define SET_RG_TURISMO_TRX_5G_RX_LG_LNA_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_TURISMO_TRX_5G_RX_LG_TZ_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_TURISMO_TRX_5G_RX_LG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER,_VAL_,4,0xffffff0f)
+#define SET_RG_TURISMO_TRX_5G_RX_LG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER,_VAL_,8,0xfffff0ff)
+#define SET_RG_TURISMO_TRX_5G_RX_LG_LNALG_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER,_VAL_,12,0xffff0fff)
+#define SET_RG_TURISMO_TRX_5G_RX_LG_TZ_CAP(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_TURISMO_TRX_5G_RX_LG_SQDC(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER,_VAL_,19,0xffc7ffff)
+#define SET_RG_TURISMO_TRX_5G_RX_LG_DIV2_CORE(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER,_VAL_,22,0xff3fffff)
+#define SET_RG_TURISMO_TRX_5G_RX_LG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER,_VAL_,24,0xfcffffff)
+#define SET_RG_TURISMO_TRX_5G_RX_LG_TZI(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER,_VAL_,26,0xe3ffffff)
+#define SET_RG_TURISMO_TRX_5G_RX_LG_TZ_VCM(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER,_VAL_,29,0x1fffffff)
+#define SET_RG_TURISMO_TRX_5G_RX_ULG_LNA_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_TURISMO_TRX_5G_RX_ULG_TZ_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_TURISMO_TRX_5G_RX_ULG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER,_VAL_,4,0xffffff0f)
+#define SET_RG_TURISMO_TRX_5G_RX_ULG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER,_VAL_,8,0xfffff0ff)
+#define SET_RG_TURISMO_TRX_5G_RX_ULG_LNALG_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER,_VAL_,12,0xffff0fff)
+#define SET_RG_TURISMO_TRX_5G_RX_ULG_TZ_CAP(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_TURISMO_TRX_5G_RX_ULG_SQDC(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER,_VAL_,19,0xffc7ffff)
+#define SET_RG_TURISMO_TRX_5G_RX_ULG_DIV2_CORE(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER,_VAL_,22,0xff3fffff)
+#define SET_RG_TURISMO_TRX_5G_RX_ULG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER,_VAL_,24,0xfcffffff)
+#define SET_RG_TURISMO_TRX_5G_RX_ULG_TZI(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER,_VAL_,26,0xe3ffffff)
+#define SET_RG_TURISMO_TRX_5G_RX_ULG_TZ_VCM(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER,_VAL_,29,0x1fffffff)
+#define SET_RG_TURISMO_TRX_5G_TX_DACI1ST(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_TURISMO_TRX_5G_TX_DACLPF_ICOARSE(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_TURISMO_TRX_5G_TX_DACLPF_IFINE(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER,_VAL_,4,0xffffffcf)
+#define SET_RG_TURISMO_TRX_5G_TX_DACLPF_VCM(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER,_VAL_,6,0xffffff3f)
+#define SET_RG_TURISMO_TRX_5G_TX_DAC_IBIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER,_VAL_,8,0xfffffcff)
+#define SET_RG_TURISMO_TRX_5G_TX_DAC_IATTN(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER,_VAL_,10,0xfffffbff)
+#define SET_RG_TURISMO_TRX_5G_TXLPF_BOOSTI(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER,_VAL_,11,0xfffff7ff)
+#define SET_RG_TURISMO_TRX_5G_TX_DAC_RCAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER,_VAL_,12,0xffffcfff)
+#define SET_RG_TURISMO_TRX_5G_TX_DAC_CKEDGE_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER,_VAL_,14,0xffffbfff)
+#define SET_RG_TURISMO_TRX_5G_TX_DAC_OS(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_TURISMO_TRX_5G_TX_DAC_IOFFSET(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER,_VAL_,20,0xff0fffff)
+#define SET_RG_TURISMO_TRX_5G_TX_DAC_QOFFSET(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER,_VAL_,24,0xf0ffffff)
+#define SET_RG_TURISMO_TRX_SX5GB_RFCTRL_F(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_FRACTIONAL_AND_INTEGER_8BITS,_VAL_,0,0xff000000)
+#define SET_RG_TURISMO_TRX_SX5GB_RFCTRL_CH_7_0(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_FRACTIONAL_AND_INTEGER_8BITS,_VAL_,24,0x00ffffff)
+#define SET_RG_TURISMO_TRX_SX5GB_RFCTRL_CH_10_8(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_REGISTER_INT3BIT___CH_TABLE,_VAL_,0,0xfffffff8)
+#define SET_RG_TURISMO_TRX_SX5GB_RFCH_MAP_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_REGISTER_INT3BIT___CH_TABLE,_VAL_,4,0xffffffef)
+#define SET_RG_TURISMO_TRX_SX5GB_LO_TIMES(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_REGISTER_INT3BIT___CH_TABLE,_VAL_,5,0xffffffdf)
+#define SET_RG_TURISMO_TRX_SX5GB_CHANNEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_REGISTER_INT3BIT___CH_TABLE,_VAL_,8,0xffff00ff)
+#define SET_RG_TURISMO_TRX_SX_5GB_EN_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,0,0xfffffffe)
+#define SET_RG_TURISMO_TRX_SX_5GB_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,1,0xfffffffd)
+#define SET_RG_TURISMO_TRX_EN_SX5GB_CP_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,2,0xfffffffb)
+#define SET_RG_TURISMO_TRX_EN_SX5GB_CP(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,3,0xfffffff7)
+#define SET_RG_TURISMO_TRX_EN_SX5GB_DIV_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,4,0xffffffef)
+#define SET_RG_TURISMO_TRX_EN_SX5GB_DIV(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,5,0xffffffdf)
+#define SET_RG_TURISMO_TRX_EN_SX5GB_VCO_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,6,0xffffffbf)
+#define SET_RG_TURISMO_TRX_EN_SX5GB_VCO(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,7,0xffffff7f)
+#define SET_RG_TURISMO_TRX_SX5GB_PFD_RST_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,8,0xfffffeff)
+#define SET_RG_TURISMO_TRX_SX5GB_PFD_RST(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,9,0xfffffdff)
+#define SET_RG_TURISMO_TRX_SX5GB_UOP_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,10,0xfffffbff)
+#define SET_RG_TURISMO_TRX_SX5GB_UOP_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,11,0xfffff7ff)
+#define SET_RG_TURISMO_TRX_EN_SX5GB_HSDIV_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,12,0xffffefff)
+#define SET_RG_TURISMO_TRX_EN_SX5GB_HSDIV(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,13,0xffffdfff)
+#define SET_RG_TURISMO_TRX_EN_HSDIV_OBF_SX_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,14,0xffffbfff)
+#define SET_RG_TURISMO_TRX_EN_HSDIV_OBF_SX(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,15,0xffff7fff)
+#define SET_RG_TURISMO_TRX_EN_HSDIV_OBF_MX_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,16,0xfffeffff)
+#define SET_RG_TURISMO_TRX_EN_HSDIV_OBF_MX(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,17,0xfffdffff)
+#define SET_RG_TURISMO_TRX_EN_SX_MIX_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,18,0xfffbffff)
+#define SET_RG_TURISMO_TRX_EN_SX_MIX(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,19,0xfff7ffff)
+#define SET_RG_TURISMO_TRX_EN_SX_REP_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,20,0xffefffff)
+#define SET_RG_TURISMO_TRX_EN_SX_REP(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,21,0xffdfffff)
+#define SET_RG_TURISMO_TRX_SX5GB_SBCAL_DIS(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,22,0xffbfffff)
+#define SET_RG_TURISMO_TRX_SX5GB_SBCAL_2ND_DIS(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,23,0xff7fffff)
+#define SET_RG_TURISMO_TRX_SX5GB_SBCAL_AW(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,24,0xfeffffff)
+#define SET_RG_TURISMO_TRX_SX5GB_VOAAC_DIS(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,25,0xfdffffff)
+#define SET_RG_TURISMO_TRX_SX5GB_MIXAAC_DIS(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,26,0xfbffffff)
+#define SET_RG_TURISMO_TRX_SX5GB_REPAAC_DIS(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,27,0xf7ffffff)
+#define SET_RG_TURISMO_TRX_SX5GB_TTL_DIS(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,28,0xefffffff)
+#define SET_RG_TURISMO_TRX_SX5GB_CAL_INIT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,29,0x1fffffff)
+#define SET_RG_TURISMO_TRX_EN_SX5GB_LDO_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER,_VAL_,0,0xfffffffe)
+#define SET_RG_TURISMO_TRX_EN_LDO_5G_CP(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER,_VAL_,1,0xfffffffd)
+#define SET_RG_TURISMO_TRX_EN_LDO_5G_DIV(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER,_VAL_,2,0xfffffffb)
+#define SET_RG_TURISMO_TRX_EN_LDO_5G_LO(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER,_VAL_,3,0xfffffff7)
+#define SET_RG_TURISMO_TRX_EN_LDO_5G_VCO(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER,_VAL_,4,0xffffffef)
+#define SET_RG_TURISMO_TRX_EN_LDO_5G_VCO_PSW(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER,_VAL_,9,0xfffffdff)
+#define SET_RG_TURISMO_TRX_EN_LDO_5G_VCO_VDD33(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER,_VAL_,10,0xfffffbff)
+#define SET_RG_TURISMO_TRX_EN_LDO_5G_CP_IQUP(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER,_VAL_,11,0xfffff7ff)
+#define SET_RG_TURISMO_TRX_EN_LDO_5G_DIV_IQUP(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER,_VAL_,12,0xffffefff)
+#define SET_RG_TURISMO_TRX_EN_LDO_5G_LO_IQUP(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER,_VAL_,13,0xffffdfff)
+#define SET_RG_TURISMO_TRX_EN_LDO_5G_VCO_IQUP(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER,_VAL_,14,0xffffbfff)
+#define SET_RG_TURISMO_TRX_SX5GB_LDO_FCOFFT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER,_VAL_,19,0xffc7ffff)
+#define SET_RG_TURISMO_TRX_LDO_5G_CP_FC_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER,_VAL_,22,0xffbfffff)
+#define SET_RG_TURISMO_TRX_LDO_5G_CP_FC(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER,_VAL_,23,0xff7fffff)
+#define SET_RG_TURISMO_TRX_LDO_5G_DIV_FC_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER,_VAL_,24,0xfeffffff)
+#define SET_RG_TURISMO_TRX_LDO_5G_DIV_FC(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER,_VAL_,25,0xfdffffff)
+#define SET_RG_TURISMO_TRX_LDO_5G_LO_FC_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER,_VAL_,26,0xfbffffff)
+#define SET_RG_TURISMO_TRX_LDO_5G_LO_FC(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER,_VAL_,27,0xf7ffffff)
+#define SET_RG_TURISMO_TRX_LDO_5G_VCO_FC_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER,_VAL_,28,0xefffffff)
+#define SET_RG_TURISMO_TRX_LDO_5G_VCO_FC(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER,_VAL_,29,0xdfffffff)
+#define SET_RG_TURISMO_TRX_LDO_5G_VCO_RCF(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER,_VAL_,30,0x3fffffff)
+#define SET_RG_TURISMO_TRX_SX5GB_CP_ISEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_,_VAL_,0,0xfffffff0)
+#define SET_RG_TURISMO_TRX_SX5GB_CP_ISEL50U(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_,_VAL_,4,0xffffffef)
+#define SET_RG_TURISMO_TRX_SX5GB_CP_KP_DOUB(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_,_VAL_,5,0xffffffdf)
+#define SET_RG_TURISMO_TRX_SX5GB_CP_IOST_POL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_,_VAL_,7,0xffffff7f)
+#define SET_RG_TURISMO_TRX_SX5GB_CP_IOST(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_,_VAL_,8,0xfffff8ff)
+#define SET_RG_TURISMO_TRX_SX5GB_PFD_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_,_VAL_,12,0xffffefff)
+#define SET_RG_TURISMO_TRX_SX5GB_PFD_SET(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_,_VAL_,13,0xffffdfff)
+#define SET_RG_TURISMO_TRX_SX5GB_PFD_SET1(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_,_VAL_,14,0xffffbfff)
+#define SET_RG_TURISMO_TRX_SX5GB_PFD_SET2(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_,_VAL_,15,0xffff7fff)
+#define SET_RG_TURISMO_TRX_SX5GB_PFD_TRUP(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_,_VAL_,16,0xfffeffff)
+#define SET_RG_TURISMO_TRX_SX5GB_PFD_TRDN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_,_VAL_,17,0xfffdffff)
+#define SET_RG_TURISMO_TRX_SX5GB_PFD_TLSEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_,_VAL_,18,0xfffbffff)
+#define SET_RG_TURISMO_TRX_SX5GB_PFD_REF_EDGE(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_,_VAL_,19,0xfff7ffff)
+#define SET_RG_TURISMO_TRX_SX5GB_PFD_DIV_EDGE(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_,_VAL_,20,0xffefffff)
+#define SET_RG_TURISMO_TRX_SX5GB_LPF_C1(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LPF_TTL,_VAL_,0,0xfffffff0)
+#define SET_RG_TURISMO_TRX_SX5GB_LPF_C2(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LPF_TTL,_VAL_,4,0xffffff0f)
+#define SET_RG_TURISMO_TRX_SX5GB_LPF_C3(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LPF_TTL,_VAL_,8,0xfffffeff)
+#define SET_RG_TURISMO_TRX_SX5GB_LPF_R2(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LPF_TTL,_VAL_,9,0xffffe1ff)
+#define SET_RG_TURISMO_TRX_SX5GB_LPF_R3(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LPF_TTL,_VAL_,13,0xffff1fff)
+#define SET_RG_TURISMO_TRX_SX5GB_TTL_INIT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LPF_TTL,_VAL_,16,0xfffcffff)
+#define SET_RG_TURISMO_TRX_SX5GB_TTL_FPT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LPF_TTL,_VAL_,18,0xfff3ffff)
+#define SET_RG_TURISMO_TRX_SX5GB_TTL_CPT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LPF_TTL,_VAL_,20,0xffcfffff)
+#define SET_RG_TURISMO_TRX_SX5GB_TTL_ACCUM(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LPF_TTL,_VAL_,22,0xff3fffff)
+#define SET_RG_TURISMO_TRX_SX5GB_TTL_SUB(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LPF_TTL,_VAL_,24,0xfcffffff)
+#define SET_RG_TURISMO_TRX_SX5GB_TTL_SUB_INV(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LPF_TTL,_VAL_,26,0xfbffffff)
+#define SET_RG_TURISMO_TRX_SX5GB_TTL_VH(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LPF_TTL,_VAL_,27,0xe7ffffff)
+#define SET_RG_TURISMO_TRX_SX5GB_TTL_VL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LPF_TTL,_VAL_,29,0x9fffffff)
+#define SET_RG_TURISMO_TRX_SX5GB_LPF_VTUNE_TEST(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LPF_TTL,_VAL_,31,0x7fffffff)
+#define SET_RG_TURISMO_TRX_SX5GB_VCO_ISEL_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN,_VAL_,0,0xfffffffe)
+#define SET_RG_TURISMO_TRX_SX5GB_VCO_ISEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN,_VAL_,1,0xffffffe1)
+#define SET_RG_TURISMO_TRX_SX5GB_VCO_VCCBSEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN,_VAL_,6,0xfffffe3f)
+#define SET_RG_TURISMO_TRX_SX5GB_VCO_KVDOUB(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN,_VAL_,9,0xfffffdff)
+#define SET_RG_TURISMO_TRX_SX5GB_VCO_VARBSEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN,_VAL_,11,0xffffe7ff)
+#define SET_RG_TURISMO_TRX_SX5GB_VCO_RTAIL_SHIFT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN,_VAL_,13,0xffffdfff)
+#define SET_RG_TURISMO_TRX_SX5GB_VCO_CS_AWH(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN,_VAL_,14,0xffffbfff)
+#define SET_RG_TURISMO_TRX_HSDIV_INBFSEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN,_VAL_,15,0xfffe7fff)
+#define SET_RG_TURISMO_TRX_HSDIV_OBFMX_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN,_VAL_,17,0xfffdffff)
+#define SET_RG_TURISMO_TRX_HSDIV_OBFSX_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN,_VAL_,18,0xfffbffff)
+#define SET_RG_TURISMO_TRX_HSDIV_VRSEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN,_VAL_,19,0xffe7ffff)
+#define SET_RG_TURISMO_TRX_SXMIX_IBIAS_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN,_VAL_,21,0xff9fffff)
+#define SET_RG_TURISMO_TRX_SXMIX_SWB_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN,_VAL_,23,0xfe7fffff)
+#define SET_RG_TURISMO_TRX_SXMIX_GMSEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN,_VAL_,25,0xf9ffffff)
+#define SET_RG_TURISMO_TRX_SXREP_SWB_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN,_VAL_,27,0xe7ffffff)
+#define SET_RG_TURISMO_TRX_SXREP_CSSEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN,_VAL_,29,0x9fffffff)
+#define SET_RG_TURISMO_TRX_EN_SX5GB_VCOMON(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN,_VAL_,31,0x7fffffff)
+#define SET_RG_TURISMO_TRX_SX5GB_DIV_PREVDD(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_DIV_SDM,_VAL_,0,0xfffffff0)
+#define SET_RG_TURISMO_TRX_SX5GB_DIV_PSCVDD(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_DIV_SDM,_VAL_,4,0xffffff0f)
+#define SET_RG_TURISMO_TRX_SX5GB_DIV_RST_H(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_DIV_SDM,_VAL_,9,0xfffffdff)
+#define SET_RG_TURISMO_TRX_SX5GB_DIV_SDM_EDGE(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_DIV_SDM,_VAL_,10,0xfffffbff)
+#define SET_RG_TURISMO_TRX_SX5GB_DIV_DMYBUF_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_DIV_SDM,_VAL_,11,0xfffff7ff)
+#define SET_RG_TURISMO_TRX_EN_SX5GB_MOD(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_DIV_SDM,_VAL_,17,0xfffdffff)
+#define SET_RG_TURISMO_TRX_EN_SX5GB_DITHER(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_DIV_SDM,_VAL_,18,0xfffbffff)
+#define SET_RG_TURISMO_TRX_SX5GB_MOD_ORDER(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_DIV_SDM,_VAL_,19,0xffe7ffff)
+#define SET_RG_TURISMO_TRX_SX5GB_DITHER_WEIGHT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_DIV_SDM,_VAL_,21,0xff9fffff)
+#define SET_RG_TURISMO_TRX_SX5GB_SUB_SEL_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_SBCAL,_VAL_,0,0xfffffffe)
+#define SET_RG_TURISMO_TRX_SX5GB_SUB_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_SBCAL,_VAL_,1,0xfffffe01)
+#define SET_RG_TURISMO_TRX_SX5GB_SUB_C0P5_DIS(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_SBCAL,_VAL_,9,0xfffffdff)
+#define SET_RG_TURISMO_TRX_SX5GB_SBCAL_CT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_SBCAL,_VAL_,10,0xfffff3ff)
+#define SET_RG_TURISMO_TRX_SX5GB_SBCAL_WT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_SBCAL,_VAL_,12,0xffffefff)
+#define SET_RG_TURISMO_TRX_SX5GB_SBCAL_DIFFMIN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_SBCAL,_VAL_,13,0xffffdfff)
+#define SET_RG_TURISMO_TRX_SX5GB_SBCAL_NTARG_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_SBCAL,_VAL_,15,0xffff7fff)
+#define SET_RG_TURISMO_TRX_SX5GB_SBCAL_NTARG(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_SBCAL,_VAL_,16,0x0000ffff)
+#define SET_RG_TURISMO_TRX_SX5GB_VOAAC_TAR(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,0,0xfffffff0)
+#define SET_RG_TURISMO_TRX_VO5GB_AAC_IOST(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,4,0xffffffcf)
+#define SET_RG_TURISMO_TRX_VO5GB_AAC_IMAX(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,6,0xfffffc3f)
+#define SET_RG_TURISMO_TRX_SX5GB_AAC_ACCUMH(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,10,0xfffff3ff)
+#define SET_RG_TURISMO_TRX_SX5GB_AAC_ACCUML(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,12,0xffffcfff)
+#define SET_RG_TURISMO_TRX_SX5GB_AAC_INIT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,14,0xffff3fff)
+#define SET_RG_TURISMO_TRX_SX5GB_AAC_EVA_TS(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,16,0xfffcffff)
+#define SET_RG_TURISMO_TRX_SX5GB_AAC_EN_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,18,0xfffbffff)
+#define SET_RG_TURISMO_TRX_SX5GB_AAC_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,19,0xfff7ffff)
+#define SET_RG_TURISMO_TRX_SX5GB_AAC_EVA_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,20,0xffefffff)
+#define SET_RG_TURISMO_TRX_SX5GB_AAC_EVA(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,21,0xffdfffff)
+#define SET_RG_TURISMO_TRX_AAC5GB_TAR_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,22,0xffbfffff)
+#define SET_RG_TURISMO_TRX_AAC5GB_PDSW_EN_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,24,0xfeffffff)
+#define SET_RG_TURISMO_TRX_EN_AAC5GB_VOPDSW(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,25,0xfdffffff)
+#define SET_RG_TURISMO_TRX_EN_AAC5GB_MXPDSW(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,26,0xfbffffff)
+#define SET_RG_TURISMO_TRX_EN_AAC5GB_RPPDSW(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,27,0xf7ffffff)
+#define SET_RG_TURISMO_TRX_SX5GB_AAC_TEST_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,30,0xbfffffff)
+#define SET_RG_TURISMO_TRX_SX5GB_AAC_TEST_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,31,0x7fffffff)
+#define SET_RG_TURISMO_TRX_SX5GB_MIXAAC_TAR(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LOGEN_CALIBRATION,_VAL_,0,0xfffffff0)
+#define SET_RG_TURISMO_TRX_SXMIX_SCA_SEL_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LOGEN_CALIBRATION,_VAL_,5,0xffffffdf)
+#define SET_RG_TURISMO_TRX_SXMIX_SCA_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LOGEN_CALIBRATION,_VAL_,6,0xfffff03f)
+#define SET_RG_TURISMO_TRX_SX5GB_REPAAC_TAR(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LOGEN_CALIBRATION,_VAL_,13,0xfffe1fff)
+#define SET_RG_TURISMO_TRX_SXREP_SCA_SEL_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LOGEN_CALIBRATION,_VAL_,18,0xfffbffff)
+#define SET_RG_TURISMO_TRX_SXREP_SCA_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LOGEN_CALIBRATION,_VAL_,19,0xfe07ffff)
+#define SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG15(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER1,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG15(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER1,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG14(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER1,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG14(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER1,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG13(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER2,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG13(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER2,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG12(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER2,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG12(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER2,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG11(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER3,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG11(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER3,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG10(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER3,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG10(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER3,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG9(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER4,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG9(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER4,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG8(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER4,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG8(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER4,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG7(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER5,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG7(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER5,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG6(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER5,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG6(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER5,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG5(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER6,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG5(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER6,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG4(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER6,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG4(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER6,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG3(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER7,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG3(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER7,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG2(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER7,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG2(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER7,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG1(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER8,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG1(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER8,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG0(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER8,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG0(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER8,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG15(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER9,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG15(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER9,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG14(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER9,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG14(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER9,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG13(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER10,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG13(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER10,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG12(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER10,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG12(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER10,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG11(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER11,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG11(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER11,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG10(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER11,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG10(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER11,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG9(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER12,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG9(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER12,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG8(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER12,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG8(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER12,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG7(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER13,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG7(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER13,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG6(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER13,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG6(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER13,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG5(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER14,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG5(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER14,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG4(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER14,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG4(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER14,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG3(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER15,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG3(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER15,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG2(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER15,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG2(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER15,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG1(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER16,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG1(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER16,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG0(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER16,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG0(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER16,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE4(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER17,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE4(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER17,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE3(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER17,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE3(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER17,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE2(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER18,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE2(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER18,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE1(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER18,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE1(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER18,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE0(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER19,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE0(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER19,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE4(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER19,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE4(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER19,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE3(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER20,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE3(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER20,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE2(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER20,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE2(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER20,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE1(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER21,_VAL_,0,0xffffffc0)
+#define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE1(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER21,_VAL_,8,0xffffc0ff)
+#define SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE0(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER21,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE0(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER21,_VAL_,24,0xc0ffffff)
+#define SET_RG_TURISMO_TRX_SX5GB_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_MODE_DECODER_TIMER_REGISTER1,_VAL_,0,0xfffffff0)
+#define SET_RG_TURISMO_TRX_5G_TXDAC_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_MODE_DECODER_TIMER_REGISTER1,_VAL_,4,0xffffff0f)
+#define SET_RG_TURISMO_TRX_5G_TXRF_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_MODE_DECODER_TIMER_REGISTER1,_VAL_,8,0xfffff0ff)
+#define SET_RG_TURISMO_TRX_5G_TXPA_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_MODE_DECODER_TIMER_REGISTER1,_VAL_,12,0xffff0fff)
+#define SET_RG_TURISMO_TRX_5G_RXRF_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_MODE_DECODER_TIMER_REGISTER1,_VAL_,16,0xfff0ffff)
+#define SET_RG_TURISMO_TRX_5G_TXDAC_T2R_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_T2R_TIMER_REGISTER,_VAL_,0,0xffffffe0)
+#define SET_RG_TURISMO_TRX_5G_TXRF_T2R_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_T2R_TIMER_REGISTER,_VAL_,8,0xffffe0ff)
+#define SET_RG_TURISMO_TRX_5G_TXPA_T2R_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_T2R_TIMER_REGISTER,_VAL_,16,0xffe0ffff)
+#define SET_RG_TURISMO_TRX_5G_RXRF_T2R_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_T2R_TIMER_REGISTER,_VAL_,24,0xe0ffffff)
+#define SET_RG_TURISMO_TRX_5G_TXDAC_R2T_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_R2T_TIMER_REGISTER,_VAL_,0,0xffffffe0)
+#define SET_RG_TURISMO_TRX_5G_TXRF_R2T_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_R2T_TIMER_REGISTER,_VAL_,8,0xffffe0ff)
+#define SET_RG_TURISMO_TRX_5G_TXPA_R2T_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_R2T_TIMER_REGISTER,_VAL_,16,0xffe0ffff)
+#define SET_RG_TURISMO_TRX_5G_RXRF_R2T_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_R2T_TIMER_REGISTER,_VAL_,24,0xe0ffffff)
+#define SET_RG_TURISMO_TRX_5G_RX_DCCAL_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_CALIBRATION_TIMER_GAIN_REGISTER,_VAL_,0,0xfffffff8)
+#define SET_RG_TURISMO_TRX_5G_TX_DCCAL_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_CALIBRATION_TIMER_GAIN_REGISTER,_VAL_,8,0xfffff8ff)
+#define SET_RG_TURISMO_TRX_5G_TX_IQCAL_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_CALIBRATION_TIMER_GAIN_REGISTER,_VAL_,12,0xffff8fff)
+#define SET_RG_TURISMO_TRX_5G_RX_IQCAL_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_CALIBRATION_TIMER_GAIN_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_TURISMO_TRX_5G_PGAG_TXCAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_CALIBRATION_TIMER_GAIN_REGISTER,_VAL_,20,0xff0fffff)
+#define SET_RG_TURISMO_TRX_5G_TX_GAIN_TXCAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_CALIBRATION_TIMER_GAIN_REGISTER,_VAL_,24,0x80ffffff)
+#define SET_RG_TURISMO_TRX_5G_PGAG_RCCAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_CALIBRATION_GAIN_REGISTER1,_VAL_,0,0xfffffff0)
+#define SET_RG_TURISMO_TRX_5G_RFG_RXIQCAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_CALIBRATION_GAIN_REGISTER1,_VAL_,4,0xffffffcf)
+#define SET_RG_TURISMO_TRX_5G_PGAG_RXIQCAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_CALIBRATION_GAIN_REGISTER1,_VAL_,6,0xfffffc3f)
+#define SET_RG_TURISMO_TRX_5G_TX_GAIN_RXIQCAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_CALIBRATION_GAIN_REGISTER1,_VAL_,10,0xfffe03ff)
+#define SET_RG_TURISMO_TRX_5G_RFG_DPDCAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_CALIBRATION_GAIN_REGISTER1,_VAL_,17,0xfff9ffff)
+#define SET_RG_TURISMO_TRX_5G_PGAG_DPDCAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_CALIBRATION_GAIN_REGISTER1,_VAL_,19,0xff87ffff)
+#define SET_RG_TURISMO_TRX_5G_TX_GAIN_DPDCAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_CALIBRATION_GAIN_REGISTER1,_VAL_,23,0xc07fffff)
+#define SET_DB_TURISMO_TRX_DA_SX5GB_SUB_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_1,_VAL_,0,0xffffff00)
+#define SET_DB_TURISMO_TRX_DA_SX5GB_VCO_ISEL(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_1,_VAL_,8,0xfffff0ff)
+#define SET_DB_TURISMO_TRX_DA_SXMIX_SCA_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_1,_VAL_,13,0xfff81fff)
+#define SET_DB_TURISMO_TRX_DA_SXMIX_GMSEL(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_1,_VAL_,19,0xffe7ffff)
+#define SET_DB_TURISMO_TRX_DA_SXREP_SCA_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_1,_VAL_,21,0xf81fffff)
+#define SET_DB_TURISMO_TRX_DA_SXREP_CSSEL(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_1,_VAL_,27,0xe7ffffff)
+#define SET_DB_TURISMO_TRX_AD_SX5GB_AAC_COMPOUT(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_1,_VAL_,29,0xdfffffff)
+#define SET_DB_TURISMO_TRX_SX5GB_TTL_VT_DET(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_1,_VAL_,30,0x3fffffff)
+#define SET_DB_TURISMO_TRX_SXMIX_SCA_SEL_A1(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_2,_VAL_,0,0xffffffc0)
+#define SET_DB_TURISMO_TRX_SXMIX_SCA_SEL_A2(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_2,_VAL_,7,0xffffe07f)
+#define SET_DB_TURISMO_TRX_SXREP_SCA_SEL_B1(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_2,_VAL_,14,0xfff03fff)
+#define SET_DB_TURISMO_TRX_SXREP_SCA_SEL_B2(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_2,_VAL_,21,0xf81fffff)
+#define SET_DB_TURISMO_TRX_SX5GB_SBCAL_NCOUNT(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_3,_VAL_,0,0xffff0000)
+#define SET_DB_TURISMO_TRX_SX5GB_SBCAL_NTARGET(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_3,_VAL_,16,0x0000ffff)
+#define SET_RG_TURISMO_TRX_RX_SCAMA_STEP0(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_LNA_MATCHING_SCA_CONTROL,_VAL_,0,0xfffffff0)
+#define SET_RG_TURISMO_TRX_RX_SCAMA_STEP1(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_LNA_MATCHING_SCA_CONTROL,_VAL_,4,0xffffff0f)
+#define SET_RG_TURISMO_TRX_RX_SCAMA_STEP2(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_LNA_MATCHING_SCA_CONTROL,_VAL_,8,0xfffff0ff)
+#define SET_RG_TURISMO_TRX_RX_SCAMA_STEP3(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_LNA_MATCHING_SCA_CONTROL,_VAL_,12,0xffff0fff)
+#define SET_RG_TURISMO_TRX_RX_SCAMA_STEP4(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_LNA_MATCHING_SCA_CONTROL,_VAL_,16,0xfff0ffff)
+#define SET_RG_TURISMO_TRX_RX_SCAMA_STEP5(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_LNA_MATCHING_SCA_CONTROL,_VAL_,20,0xff0fffff)
+#define SET_RG_TURISMO_TRX_RX_SCAMA_STEP6(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_LNA_MATCHING_SCA_CONTROL,_VAL_,24,0xf0ffffff)
+#define SET_RG_TURISMO_TRX_RX_SCALOAD_STEP0(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_LNA_LOAD_SCA_CONTROL,_VAL_,0,0xfffffff0)
+#define SET_RG_TURISMO_TRX_RX_SCALOAD_STEP1(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_LNA_LOAD_SCA_CONTROL,_VAL_,4,0xffffff0f)
+#define SET_RG_TURISMO_TRX_RX_SCALOAD_STEP2(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_LNA_LOAD_SCA_CONTROL,_VAL_,8,0xfffff0ff)
+#define SET_RG_TURISMO_TRX_RX_SCALOAD_STEP3(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_LNA_LOAD_SCA_CONTROL,_VAL_,12,0xffff0fff)
+#define SET_RG_TURISMO_TRX_RX_SCALOAD_STEP4(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_LNA_LOAD_SCA_CONTROL,_VAL_,16,0xfff0ffff)
+#define SET_RG_TURISMO_TRX_RX_SCALOAD_STEP5(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_LNA_LOAD_SCA_CONTROL,_VAL_,20,0xff0fffff)
+#define SET_RG_TURISMO_TRX_RX_SCALOAD_STEP6(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_LNA_LOAD_SCA_CONTROL,_VAL_,24,0xf0ffffff)
+#define SET_RG_TURISMO_TRX_TX_CAPSW_STEP0(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_PGA_CAPSW_CONTROL,_VAL_,0,0xfffffff0)
+#define SET_RG_TURISMO_TRX_TX_CAPSW_STEP1(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_PGA_CAPSW_CONTROL,_VAL_,4,0xffffff0f)
+#define SET_RG_TURISMO_TRX_TX_CAPSW_STEP2(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_PGA_CAPSW_CONTROL,_VAL_,8,0xfffff0ff)
+#define SET_RG_TURISMO_TRX_TX_CAPSW_STEP3(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_PGA_CAPSW_CONTROL,_VAL_,12,0xffff0fff)
+#define SET_RG_TURISMO_TRX_TX_CAPSW_STEP4(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_PGA_CAPSW_CONTROL,_VAL_,16,0xfff0ffff)
+#define SET_RG_TURISMO_TRX_TX_CAPSW_STEP5(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_PGA_CAPSW_CONTROL,_VAL_,20,0xff0fffff)
+#define SET_RG_TURISMO_TRX_TX_CAPSW_STEP6(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_PGA_CAPSW_CONTROL,_VAL_,24,0xf0ffffff)
+#define SET_RG_TURISMO_TRX_NFRAC_DELTA(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_0,_VAL_,0,0xff000000)
+#define SET_RG_TURISMO_TRX_40M_MODE(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_0,_VAL_,24,0xfeffffff)
+#define SET_RG_TURISMO_TRX_LO_UP_CH(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_0,_VAL_,28,0xefffffff)
+#define SET_RG_TURISMO_TRX_BT_TRX_IF(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_1,_VAL_,16,0xf800ffff)
+#define SET_RG_TURISMO_TRX_RX_IQ_ALPHA(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2,_VAL_,0,0xffffffe0)
+#define SET_RG_TURISMO_TRX_RX_IQ_THETA(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2,_VAL_,8,0xffffe0ff)
+#define SET_RG_TURISMO_TRX_RX_IQ_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2,_VAL_,16,0xfffeffff)
+#define SET_RG_TURISMO_TRX_RXIQ_NOSHRK(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2,_VAL_,17,0xfffdffff)
+#define SET_RG_TURISMO_TRX_RX_RSSIADC_TH(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2,_VAL_,20,0xff0fffff)
+#define SET_RG_TURISMO_TRX_SUB_DC(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2,_VAL_,24,0xfeffffff)
+#define SET_RG_TURISMO_TRX_IOT_ADC_EDGE_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2,_VAL_,25,0xfdffffff)
+#define SET_RG_TURISMO_TRX_RSSI_EDGE_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2,_VAL_,26,0xfbffffff)
+#define SET_RG_TURISMO_TRX_ADC_EDGE_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2,_VAL_,27,0xf7ffffff)
+#define SET_RG_TURISMO_TRX_Q_INV(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2,_VAL_,28,0xefffffff)
+#define SET_RG_TURISMO_TRX_I_INV(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2,_VAL_,29,0xdfffffff)
+#define SET_RG_TURISMO_TRX_IQ_SWAP(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2,_VAL_,30,0xbfffffff)
+#define SET_RG_TURISMO_TRX_SIGN_SWAP(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2,_VAL_,31,0x7fffffff)
+#define SET_RG_TURISMO_TRX_TX_IQ_ALPHA(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_3,_VAL_,0,0xffffffe0)
+#define SET_RG_TURISMO_TRX_TX_IQ_THETA(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_3,_VAL_,8,0xffffe0ff)
+#define SET_RG_TURISMO_TRX_TX_IQ_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_3,_VAL_,16,0xfffeffff)
+#define SET_RG_TURISMO_TRX_TXIQ_NOSHRK(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_3,_VAL_,17,0xfffdffff)
+#define SET_RG_TURISMO_TRX_TX_IQCAL_TIME(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_3,_VAL_,20,0xffcfffff)
+#define SET_RG_TURISMO_TRX_TX_FREQ_OFFSET(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_4,_VAL_,0,0xffff0000)
+#define SET_RG_TURISMO_TRX_TONE_SCALE(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_4,_VAL_,16,0xfe00ffff)
+#define SET_RG_TURISMO_TRX_BB_SIG_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_4,_VAL_,25,0xfdffffff)
+#define SET_RG_TURISMO_TRX_TONE_GEN_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_4,_VAL_,26,0xfbffffff)
+#define SET_RG_TURISMO_TRX_TX_UP8X_MAN_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_4,_VAL_,27,0xf7ffffff)
+#define SET_RG_TURISMO_TRX_DIS_DAC_OFFSET(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_4,_VAL_,28,0xefffffff)
+#define SET_RG_TURISMO_TRX_CLK_320M_INV(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_4,_VAL_,29,0xdfffffff)
+#define SET_RG_TURISMO_TRX_DPLL_CLK320BY2(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_4,_VAL_,30,0xbfffffff)
+#define SET_RG_TURISMO_TRX_CBW_20_40(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_4,_VAL_,31,0x7fffffff)
+#define SET_RG_TURISMO_TRX_DAC_DC_Q(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_5,_VAL_,0,0xfffffc00)
+#define SET_RG_TURISMO_TRX_DAC_DC_I(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_5,_VAL_,16,0xfc00ffff)
+#define SET_RG_TURISMO_TRX_DAC_Q_SET(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_6,_VAL_,0,0xfffffc00)
+#define SET_RG_TURISMO_TRX_DAC_MAN_Q_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_6,_VAL_,12,0xffffefff)
+#define SET_RG_TURISMO_TRX_DAC_I_SET(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_6,_VAL_,16,0xfc00ffff)
+#define SET_RG_TURISMO_TRX_DAC_MAN_I_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_6,_VAL_,28,0xefffffff)
+#define SET_RG_TURISMO_TRX_BW20_HB_COEF_01(_VAL_) SET_REG(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_00,_VAL_,0,0xffffe000)
+#define SET_RG_TURISMO_TRX_BW20_HB_COEF_00(_VAL_) SET_REG(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_00,_VAL_,16,0xe000ffff)
+#define SET_RG_TURISMO_TRX_BW20_HB_COEF_03(_VAL_) SET_REG(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_01,_VAL_,0,0xffffe000)
+#define SET_RG_TURISMO_TRX_BW20_HB_COEF_02(_VAL_) SET_REG(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_01,_VAL_,16,0xe000ffff)
+#define SET_RG_TURISMO_TRX_BW20_HB_COEF_05(_VAL_) SET_REG(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_02,_VAL_,0,0xffffe000)
+#define SET_RG_TURISMO_TRX_BW20_HB_COEF_04(_VAL_) SET_REG(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_02,_VAL_,16,0xe000ffff)
+#define SET_RG_TURISMO_TRX_BW20_HB_COEF_07(_VAL_) SET_REG(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_03,_VAL_,0,0xffffe000)
+#define SET_RG_TURISMO_TRX_BW20_HB_COEF_06(_VAL_) SET_REG(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_03,_VAL_,16,0xe000ffff)
+#define SET_RG_TURISMO_TRX_BW20_HB_COEF_09(_VAL_) SET_REG(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_04,_VAL_,0,0xffffe000)
+#define SET_RG_TURISMO_TRX_BW20_HB_COEF_08(_VAL_) SET_REG(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_04,_VAL_,16,0xe000ffff)
+#define SET_RG_TURISMO_TRX_BW20_HB_COEF_11(_VAL_) SET_REG(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_05,_VAL_,0,0xffffe000)
+#define SET_RG_TURISMO_TRX_BW20_HB_COEF_10(_VAL_) SET_REG(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_05,_VAL_,16,0xe000ffff)
+#define SET_RG_TURISMO_TRX_PHASE_STEP_VALUE(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_0,_VAL_,0,0xffff0000)
+#define SET_RG_TURISMO_TRX_PHASE_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_0,_VAL_,16,0xfffeffff)
+#define SET_RG_TURISMO_TRX_ALPHA_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_0,_VAL_,20,0xffcfffff)
+#define SET_RG_TURISMO_TRX_SPECTRUM_BW(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_0,_VAL_,24,0xfcffffff)
+#define SET_RG_TURISMO_TRX_SPECTRUM_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_0,_VAL_,28,0xefffffff)
+#define SET_RO_TURISMO_TRX_WF_DCCAL_DONE(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_1,_VAL_,16,0xfffeffff)
+#define SET_RO_TURISMO_TRX_BT_DCCAL_DONE(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_1,_VAL_,17,0xfffdffff)
+#define SET_RO_TURISMO_TRX_RCCAL_DONE(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_1,_VAL_,18,0xfffbffff)
+#define SET_RO_TURISMO_TRX_TXDC_DONE(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_1,_VAL_,19,0xfff7ffff)
+#define SET_RO_TURISMO_TRX_TXIQ_DONE(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_1,_VAL_,20,0xffefffff)
+#define SET_RO_TURISMO_TRX_RXIQ_DONE(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_1,_VAL_,21,0xffdfffff)
+#define SET_RO_TURISMO_TRX_5G_TXDC_DONE(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_1,_VAL_,22,0xffbfffff)
+#define SET_RO_TURISMO_TRX_5G_TXIQ_DONE(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_1,_VAL_,23,0xff7fffff)
+#define SET_RO_TURISMO_TRX_5G_RXIQ_DONE(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_1,_VAL_,24,0xfeffffff)
+#define SET_RO_TURISMO_TRX_5G_DCCAL_DONE(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_1,_VAL_,25,0xfdffffff)
+#define SET_RO_TURISMO_TRX_PRE_DC_DONE(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_1,_VAL_,26,0xfbffffff)
+#define SET_RG_TURISMO_TRX_PHASE_17P5M(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_2,_VAL_,0,0xffff0000)
+#define SET_RG_TURISMO_TRX_PHASE_2P5M(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_2,_VAL_,16,0x0000ffff)
+#define SET_RG_TURISMO_TRX_PHASE_RXIQ_1M(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_3,_VAL_,0,0xffff0000)
+#define SET_RG_TURISMO_TRX_PHASE_1M(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_3,_VAL_,16,0x0000ffff)
+#define SET_RG_TURISMO_TRX_PHASE_PADPD(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_4,_VAL_,0,0xffff0000)
+#define SET_RG_TURISMO_TRX_PHASE_35M(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_4,_VAL_,16,0x0000ffff)
+#define SET_RO_TURISMO_TRX_RX_IQ_THETA(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_5,_VAL_,0,0xffffffe0)
+#define SET_RO_TURISMO_TRX_RX_IQ_ALPHA(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_5,_VAL_,8,0xffffe0ff)
+#define SET_RO_TURISMO_TRX_TX_IQ_THETA(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_5,_VAL_,16,0xffe0ffff)
+#define SET_RO_TURISMO_TRX_TX_IQ_ALPHA(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_5,_VAL_,24,0xe0ffffff)
+#define SET_RG_TURISMO_TRX_RX_RCCAL_TARG(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_6,_VAL_,0,0xfffffc00)
+#define SET_RG_TURISMO_TRX_RX_DC_POLAR_INV(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_6,_VAL_,12,0xffffefff)
+#define SET_RG_TURISMO_TRX_RCCAL_POLAR_INV(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_6,_VAL_,13,0xffffdfff)
+#define SET_RG_TURISMO_TRX_RX_DC_RESOLUTION(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_6,_VAL_,14,0xffffbfff)
+#define SET_RG_TURISMO_TRX_RX_RCCAL_40M_TARG(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_6,_VAL_,16,0xfc00ffff)
+#define SET_RO_TURISMO_TRX_SPECTRUM_IQ_PWR_39_32(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_7,_VAL_,0,0xffffff00)
+#define SET_RG_TURISMO_TRX_SPECTRUM_LO_FIX(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_7,_VAL_,16,0xfffeffff)
+#define SET_RG_TURISMO_TRX_SPECTRUM_PWR_UPDATE(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_7,_VAL_,20,0xffefffff)
+#define SET_RO_TURISMO_TRX_SPECTRUM_IQ_PWR_31_0(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_8,_VAL_,0,0x00000000)
+#define SET_RG_TURISMO_TRX_PROC_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_9,_VAL_,0,0xfffffff8)
+#define SET_RG_TURISMO_TRX_PRE_DC_POLA_INV(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_9,_VAL_,4,0xffffffef)
+#define SET_RG_TURISMO_TRX_RX_PRE_DC_RESOLUTION(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_9,_VAL_,5,0xffffffdf)
+#define SET_RG_TURISMO_TRX_PRE_DC_AUTO(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_9,_VAL_,6,0xffffffbf)
+#define SET_RG_TURISMO_TRX_HS3W_TX_RF_GAIN(_VAL_) SET_REG(ADR_TURISMO_TRX_HS3W_CTRL1,_VAL_,0,0xffffff80)
+#define SET_RG_TURISMO_TRX_HS3W_PGAGC(_VAL_) SET_REG(ADR_TURISMO_TRX_HS3W_CTRL1,_VAL_,8,0xfffff0ff)
+#define SET_RG_TURISMO_TRX_HS3W_RFGC(_VAL_) SET_REG(ADR_TURISMO_TRX_HS3W_CTRL1,_VAL_,12,0xffffcfff)
+#define SET_RG_TURISMO_TRX_HS3W_RXAGC(_VAL_) SET_REG(ADR_TURISMO_TRX_HS3W_CTRL1,_VAL_,14,0xffffbfff)
+#define SET_RG_TURISMO_TRX_HS3W_RF_PHY_MODE(_VAL_) SET_REG(ADR_TURISMO_TRX_HS3W_CTRL1,_VAL_,16,0xfff8ffff)
+#define SET_RG_TURISMO_TRX_HS3W_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_HS3W_CTRL1,_VAL_,20,0xffefffff)
+#define SET_RG_TURISMO_TRX_HS3W_COMM_DATA(_VAL_) SET_REG(ADR_TURISMO_TRX_HS3W_CTRL1,_VAL_,24,0xf8ffffff)
+#define SET_RG_TURISMO_TRX_HS3W_START_SENT(_VAL_) SET_REG(ADR_TURISMO_TRX_HS3W_CTRL1,_VAL_,28,0xefffffff)
+#define SET_RG_TURISMO_TRX_HS3W_SX_RFCTRL_CH_INT_10_8(_VAL_) SET_REG(ADR_TURISMO_TRX_HS3W_CTRL2,_VAL_,0,0xfffffff8)
+#define SET_RG_TURISMO_TRX_HS3W_SX_RFCH_MAP_EN_INT(_VAL_) SET_REG(ADR_TURISMO_TRX_HS3W_CTRL2,_VAL_,4,0xffffffef)
+#define SET_RG_TURISMO_TRX_HS3W_SX_CHANNEL_INT(_VAL_) SET_REG(ADR_TURISMO_TRX_HS3W_CTRL2,_VAL_,11,0xfff807ff)
+#define SET_RG_TURISMO_TRX_HS3W_SX_RFCTRL_F_INT(_VAL_) SET_REG(ADR_TURISMO_TRX_HS3W_CTRL3,_VAL_,0,0xff000000)
+#define SET_RG_TURISMO_TRX_HS3W_SX_RFCTRL_CH_INT_7_0(_VAL_) SET_REG(ADR_TURISMO_TRX_HS3W_CTRL3,_VAL_,24,0x00ffffff)
+#define SET_RG_TURISMO_TRX_MODE_BY_HS_3WIRE(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_MODE_CTRL,_VAL_,0,0xfffffffe)
+#define SET_RO_TURISMO_TRX_DC_CAL_Q(_VAL_) SET_REG(ADR_TURISMO_TRX_RX_DC_CAL_RESULT,_VAL_,0,0xffffff80)
+#define SET_RO_TURISMO_TRX_DC_CAL_I(_VAL_) SET_REG(ADR_TURISMO_TRX_RX_DC_CAL_RESULT,_VAL_,16,0xff80ffff)
+#define SET_RG_TURISMO_TRX_XO_LDO_LEVEL(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_1,_VAL_,0,0xfffffff8)
+#define SET_RG_TURISMO_TRX_EN_LDO_XO_IQUP(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_1,_VAL_,4,0xffffffef)
+#define SET_RG_TURISMO_TRX_EN_LDO_XO_BYP(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_1,_VAL_,5,0xffffffdf)
+#define SET_RG_TURISMO_TRX_EN_DLDO_BYP(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_1,_VAL_,6,0xffffffbf)
+#define SET_RG_TURISMO_TRX_XO_CBANKI(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_1,_VAL_,8,0xfffe00ff)
+#define SET_RG_TURISMO_TRX_XO_CBANKO(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_1,_VAL_,17,0xfc01ffff)
+#define SET_RG_TURISMO_TRX_EN_FDB(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_1,_VAL_,26,0xfbffffff)
+#define SET_RG_TURISMO_TRX_FDB_BYPASS(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_1,_VAL_,27,0xf7ffffff)
+#define SET_RG_TURISMO_TRX_FDB_DUTY_LTH(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_1,_VAL_,28,0xcfffffff)
+#define SET_RG_TURISMO_TRX_EN_XOTEST(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_1,_VAL_,30,0xbfffffff)
+#define SET_RG_TURISMO_TRX_EN_FDB_DCC_MUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_2,_VAL_,0,0xfffffffe)
+#define SET_RG_TURISMO_TRX_EN_FDB_DELAYC_MUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_2,_VAL_,1,0xfffffffd)
+#define SET_RG_TURISMO_TRX_EN_FDB_DELAYF_MUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_2,_VAL_,2,0xfffffffb)
+#define SET_RG_TURISMO_TRX_EN_FDB_PHASESWAP_MUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_2,_VAL_,3,0xfffffff7)
+#define SET_RG_TURISMO_TRX_FDB_PHASESWAP_MUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_2,_VAL_,4,0xffffffef)
+#define SET_RG_TURISMO_TRX_FDB_CDELAY_MUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_2,_VAL_,8,0xfffff0ff)
+#define SET_RG_TURISMO_TRX_FDB_FDELAY_MUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_2,_VAL_,12,0xffff0fff)
+#define SET_RG_TURISMO_TRX_XO_TIMMER(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_2,_VAL_,16,0xffc0ffff)
+#define SET_RG_TURISMO_TRX_DPL_SETTLING_TIMMER(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_2,_VAL_,22,0xff3fffff)
+#define SET_RG_TURISMO_TRX_FDB_RDELAYF(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_2,_VAL_,24,0xfcffffff)
+#define SET_RG_TURISMO_TRX_FDB_RDELAYS(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_2,_VAL_,26,0xf3ffffff)
+#define SET_RG_TURISMO_TRX_FDB_RECAL_TIMMER(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_2,_VAL_,28,0xcfffffff)
+#define SET_RG_TURISMO_TRX_EN_FDB_RECAL(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_2,_VAL_,30,0xbfffffff)
+#define SET_RG_TURISMO_TRX_LOAD_RFTABLE_RDY(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_2,_VAL_,31,0x7fffffff)
+#define SET_RG_TURISMO_TRX_DCDC_MODE(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_3,_VAL_,0,0xfffffffe)
+#define SET_RG_TURISMO_TRX_DLDO_LEVEL(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_3,_VAL_,1,0xfffffff1)
+#define SET_RG_TURISMO_TRX_BUCK_LEVEL(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_3,_VAL_,4,0xffffff0f)
+#define SET_RG_TURISMO_TRX_DLDO_BOOST_IQ(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_3,_VAL_,8,0xfffffeff)
+#define SET_RG_TURISMO_TRX_BUCK_EN_PSM(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_3,_VAL_,9,0xfffffdff)
+#define SET_RG_TURISMO_TRX_BUCK_PSM_VTH(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_3,_VAL_,10,0xfffffbff)
+#define SET_RG_TURISMO_TRX_BUCK_VREF_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_3,_VAL_,11,0xfffff7ff)
+#define SET_RG_TURISMO_TRX_LDO_LEVEL_EFUSE(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_3,_VAL_,12,0xffff8fff)
+#define SET_RG_TURISMO_TRX_EN_LDO_EFUSE(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_3,_VAL_,16,0xfffeffff)
+#define SET_RG_TURISMO_TRX_DCDC_PULLLOW_CON(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_3,_VAL_,18,0xfffbffff)
+#define SET_RG_TURISMO_TRX_DCDC_RES2_CON(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_3,_VAL_,19,0xfff7ffff)
+#define SET_RG_TURISMO_TRX_DCDC_RES_CON(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_3,_VAL_,20,0xffefffff)
+#define SET_RG_TURISMO_TRX_RTC_RS1(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_3,_VAL_,21,0xffdfffff)
+#define SET_RG_TURISMO_TRX_RTC_RS2(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_3,_VAL_,22,0xffbfffff)
+#define SET_RG_TURISMO_TRX_DCDC_CLK(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_3,_VAL_,24,0xf0ffffff)
+#define SET_RG_TURISMO_TRX_BUCK_RCZERO(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_3,_VAL_,28,0xefffffff)
+#define SET_RG_TURISMO_TRX_BUCK_SLOP(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_3,_VAL_,29,0x9fffffff)
+#define SET_RG_TURISMO_TRX_RTC_OFFSET(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_4,_VAL_,0,0xffffff00)
+#define SET_RG_TURISMO_TRX_RTC_CAL_TARGET_COUNT(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_4,_VAL_,8,0xfff000ff)
+#define SET_RG_TURISMO_TRX_RTC_OSC_RES_SW_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_4,_VAL_,20,0xc00fffff)
+#define SET_RG_TURISMO_TRX_RTC_CAL_MODE(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_4,_VAL_,30,0xbfffffff)
+#define SET_RG_TURISMO_TRX_SEL_DPLL_CLK(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_4,_VAL_,31,0x7fffffff)
+#define SET_RG_TURISMO_TRX_RTC_OSC_RES_SW_MANUAL_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_5,_VAL_,0,0xfffffffe)
+#define SET_RG_TURISMO_TRX_EN_RTC_CAL(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_5,_VAL_,1,0xfffffffd)
+#define SET_RO_TURISMO_TRX_FDB_CDELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_6,_VAL_,0,0xfffffff0)
+#define SET_RO_TURISMO_TRX_FDB_FDELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_6,_VAL_,4,0xffffff0f)
+#define SET_RO_TURISMO_TRX_FDB_PHASESWAP(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_6,_VAL_,8,0xfffffeff)
+#define SET_RO_TURISMO_TRX_XO_RDY(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_6,_VAL_,9,0xfffffdff)
+#define SET_RO_TURISMO_TRX_RTC_OSC_CAL_RES_RDY(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_6,_VAL_,10,0xfffffbff)
+#define SET_RO_TURISMO_TRX_RTC_OSC_RES_SW(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_6,_VAL_,11,0xffe007ff)
+#define SET_RG_TURISMO_TRX_PMU_ENTER_SLEEP_MODE(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_SLEEP_REG_1,_VAL_,0,0xfffffffe)
+#define SET_RG_TURISMO_TRX_SLEEP_METHOD(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_SLEEP_REG_1,_VAL_,1,0xfffffffd)
+#define SET_RG_TURISMO_TRX_INT_PMU_MASK(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_SLEEP_REG_1,_VAL_,2,0xfffffffb)
+#define SET_RG_TURISMO_TRX_SLEEP_WAKE_CNT(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_SLEEP_REG_2,_VAL_,0,0x00000000)
+#define SET_RG_TURISMO_TRX_SEC_CNT_VALUE(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RTC_REG_0,_VAL_,0,0xffff8000)
+#define SET_RG_TURISMO_TRX_RTC_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RTC_REG_0,_VAL_,15,0xffff7fff)
+#define SET_RO_TURISMO_TRX_RTC_TICK_CNT(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RTC_REG_0,_VAL_,16,0x8000ffff)
+#define SET_RG_TURISMO_TRX_RTC_INT_SEC_MASK(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RTC_REG_1,_VAL_,0,0xfffffffe)
+#define SET_RG_TURISMO_TRX_RTC_INT_ALARM_MASK(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RTC_REG_1,_VAL_,1,0xfffffffd)
+#define SET_RO_TURISMO_TRX_PMU_WAKE_TRIG_EVENT(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RTC_REG_1,_VAL_,12,0xffff8fff)
+#define SET_RO_TURISMO_TRX_RTC_INT_SEC(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RTC_REG_1,_VAL_,16,0xfffeffff)
+#define SET_RO_TURISMO_TRX_RTC_INT_ALARM(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RTC_REG_1,_VAL_,17,0xfffdffff)
+#define SET_RG_TURISMO_TRX_RTC_SEC_START_CNT(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RTC_REG_2,_VAL_,0,0x00000000)
+#define SET_RG_TURISMO_TRX_RTC_SEC_ALARM_VALUE(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RTC_REG_3,_VAL_,0,0x00000000)
+#define SET_RG_TURISMO_TRX_FPGA_CLK_REF_40M_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_CTRL_REG,_VAL_,0,0xfffffffe)
+#define SET_RG_TURISMO_TRX_CLK_RTC_SW(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_CTRL_REG,_VAL_,1,0xfffffffd)
+#define SET_RG_TURISMO_TRX_PHY_RST_N(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_CTRL_REG,_VAL_,4,0xffffffef)
+#define SET_RO_TURISMO_TRX_PMU_STATE(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_STATE_REG,_VAL_,0,0xfffffff8)
+#define SET_RO_TURISMO_TRX_AD_VBAT_OK(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_STATE_REG,_VAL_,4,0xffffffef)
+#define SET_RG_TURISMO_TRX_BT_CLK_SW(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_BT_CLK,_VAL_,0,0xfffffffe)
+#define SET_RG_TURISMO_TRX_BT_CLK32K_CAL_DONE(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_BT_CLK,_VAL_,1,0xfffffffd)
+#define SET_RG_TURISMO_TRX_GPIO16_DS(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_0,_VAL_,0,0xfffffffe)
+#define SET_RG_TURISMO_TRX_GPIO16_PD(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_0,_VAL_,1,0xfffffffd)
+#define SET_RG_TURISMO_TRX_GPIO16_OE(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_0,_VAL_,2,0xfffffffb)
+#define SET_RG_TURISMO_TRX_GPIO17_DS(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_0,_VAL_,4,0xffffffef)
+#define SET_RG_TURISMO_TRX_GPIO17_PD(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_0,_VAL_,5,0xffffffdf)
+#define SET_RG_TURISMO_TRX_GPIO17_OE(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_0,_VAL_,6,0xffffffbf)
+#define SET_RG_TURISMO_TRX_GPIO18_DS(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_0,_VAL_,8,0xfffffeff)
+#define SET_RG_TURISMO_TRX_GPIO18_PD(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_0,_VAL_,9,0xfffffdff)
+#define SET_RG_TURISMO_TRX_GPIO18_OE(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_0,_VAL_,10,0xfffffbff)
+#define SET_RG_TURISMO_TRX_GPIO19_DS(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_0,_VAL_,12,0xffffefff)
+#define SET_RG_TURISMO_TRX_GPIO19_PD(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_0,_VAL_,13,0xffffdfff)
+#define SET_RG_TURISMO_TRX_GPIO19_OE(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_0,_VAL_,14,0xffffbfff)
+#define SET_RG_TURISMO_TRX_GPIO20_DS(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_0,_VAL_,16,0xfffeffff)
+#define SET_RG_TURISMO_TRX_GPIO20_PD(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_0,_VAL_,17,0xfffdffff)
+#define SET_RG_TURISMO_TRX_GPIO20_OE(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_0,_VAL_,18,0xfffbffff)
+#define SET_RG_TURISMO_TRX_SPIS_MISO_DS(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_0,_VAL_,24,0xfeffffff)
+#define SET_RG_TURISMO_TRX_FPGA_CLK_REF_40M_DS(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_0,_VAL_,28,0xefffffff)
+#define SET_RG_TURISMO_TRX_FPGA_CLK_REF_40M_PD(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_0,_VAL_,29,0xdfffffff)
+#define SET_RG_TURISMO_TRX_FPGA_CLK_REF_40M_OE(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_0,_VAL_,30,0xbfffffff)
+#define SET_RG_TURISMO_TRX_GPIO08_DS(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,0,0xfffffffe)
+#define SET_RG_TURISMO_TRX_GPIO08_PD(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,1,0xfffffffd)
+#define SET_RG_TURISMO_TRX_GPIO08_OE(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,2,0xfffffffb)
+#define SET_RG_TURISMO_TRX_GPIO09_DS(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,4,0xffffffef)
+#define SET_RG_TURISMO_TRX_GPIO09_PD(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,5,0xffffffdf)
+#define SET_RG_TURISMO_TRX_GPIO09_OE(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,6,0xffffffbf)
+#define SET_RG_TURISMO_TRX_GPIO10_DS(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,8,0xfffffeff)
+#define SET_RG_TURISMO_TRX_GPIO10_PD(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,9,0xfffffdff)
+#define SET_RG_TURISMO_TRX_GPIO10_OE(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,10,0xfffffbff)
+#define SET_RG_TURISMO_TRX_GPIO11_DS(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,12,0xffffefff)
+#define SET_RG_TURISMO_TRX_GPIO11_PD(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,13,0xffffdfff)
+#define SET_RG_TURISMO_TRX_GPIO11_OE(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,14,0xffffbfff)
+#define SET_RG_TURISMO_TRX_GPIO12_DS(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,16,0xfffeffff)
+#define SET_RG_TURISMO_TRX_GPIO12_PD(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,17,0xfffdffff)
+#define SET_RG_TURISMO_TRX_GPIO12_OE(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,18,0xfffbffff)
+#define SET_RG_TURISMO_TRX_GPIO13_DS(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,20,0xffefffff)
+#define SET_RG_TURISMO_TRX_GPIO13_PD(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,21,0xffdfffff)
+#define SET_RG_TURISMO_TRX_GPIO13_OE(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,22,0xffbfffff)
+#define SET_RG_TURISMO_TRX_GPIO14_DS(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,24,0xfeffffff)
+#define SET_RG_TURISMO_TRX_GPIO14_PD(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,25,0xfdffffff)
+#define SET_RG_TURISMO_TRX_GPIO14_OE(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,26,0xfbffffff)
+#define SET_RG_TURISMO_TRX_GPIO15_DS(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,28,0xefffffff)
+#define SET_RG_TURISMO_TRX_GPIO15_PD(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,29,0xdfffffff)
+#define SET_RG_TURISMO_TRX_GPIO15_OE(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,30,0xbfffffff)
+#define SET_RG_TURISMO_TRX_GPIO00_DS(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,0,0xfffffffe)
+#define SET_RG_TURISMO_TRX_GPIO00_PD(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,1,0xfffffffd)
+#define SET_RG_TURISMO_TRX_GPIO00_OE(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,2,0xfffffffb)
+#define SET_RG_TURISMO_TRX_GPIO01_DS(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,4,0xffffffef)
+#define SET_RG_TURISMO_TRX_GPIO01_PD(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,5,0xffffffdf)
+#define SET_RG_TURISMO_TRX_GPIO01_OE(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,6,0xffffffbf)
+#define SET_RG_TURISMO_TRX_GPIO02_DS(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,8,0xfffffeff)
+#define SET_RG_TURISMO_TRX_GPIO02_PD(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,9,0xfffffdff)
+#define SET_RG_TURISMO_TRX_GPIO02_OE(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,10,0xfffffbff)
+#define SET_RG_TURISMO_TRX_GPIO03_DS(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,12,0xffffefff)
+#define SET_RG_TURISMO_TRX_GPIO03_PD(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,13,0xffffdfff)
+#define SET_RG_TURISMO_TRX_GPIO03_OE(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,14,0xffffbfff)
+#define SET_RG_TURISMO_TRX_GPIO04_DS(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,16,0xfffeffff)
+#define SET_RG_TURISMO_TRX_GPIO04_PD(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,17,0xfffdffff)
+#define SET_RG_TURISMO_TRX_GPIO04_OE(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,18,0xfffbffff)
+#define SET_RG_TURISMO_TRX_GPIO05_DS(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,20,0xffefffff)
+#define SET_RG_TURISMO_TRX_GPIO05_PD(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,21,0xffdfffff)
+#define SET_RG_TURISMO_TRX_GPIO05_OE(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,22,0xffbfffff)
+#define SET_RG_TURISMO_TRX_GPIO06_DS(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,24,0xfeffffff)
+#define SET_RG_TURISMO_TRX_GPIO06_PD(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,25,0xfdffffff)
+#define SET_RG_TURISMO_TRX_GPIO06_OE(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,26,0xfbffffff)
+#define SET_RG_TURISMO_TRX_GPIO07_DS(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,28,0xefffffff)
+#define SET_RG_TURISMO_TRX_GPIO07_PD(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,29,0xdfffffff)
+#define SET_RG_TURISMO_TRX_GPIO07_OE(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,30,0xbfffffff)
+#define SET_RG_TURISMO_TRX_RF_PHY_MODE_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_MCU_REG_0,_VAL_,0,0xfffffffc)
+#define SET_RG_TURISMO_TRX_RF_PHY_MODE_WIFI_MAC(_VAL_) SET_REG(ADR_TURISMO_TRX_MCU_REG_0,_VAL_,4,0xffffff8f)
+#define SET_RG_TURISMO_TRX_PAD_MUX_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_MCU_REG_0,_VAL_,8,0xfffff0ff)
+#define SET_RG_TURISMO_TRX_MODE_LATCH_LMT(_VAL_) SET_REG(ADR_TURISMO_TRX_MCU_REG_0,_VAL_,12,0xffff8fff)
+#define SET_RG_TURISMO_TRX_CLK_MON_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_MCU_REG_0,_VAL_,16,0xfff8ffff)
+#define SET_RG_TURISMO_TRX_EXT_MCU_PWRUP(_VAL_) SET_REG(ADR_TURISMO_TRX_MCU_REG_0,_VAL_,31,0x7fffffff)
+#define SET_RG_TURISMO_TRX_RAM_00(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_00,_VAL_,0,0x00000000)
+#define SET_RG_TURISMO_TRX_RAM_01(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_01,_VAL_,0,0x00000000)
+#define SET_RG_TURISMO_TRX_RAM_02(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_02,_VAL_,0,0x00000000)
+#define SET_RG_TURISMO_TRX_RAM_03(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_03,_VAL_,0,0x00000000)
+#define SET_RG_TURISMO_TRX_RAM_04(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_04,_VAL_,0,0x00000000)
+#define SET_RG_TURISMO_TRX_RAM_05(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_05,_VAL_,0,0x00000000)
+#define SET_RG_TURISMO_TRX_RAM_06(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_06,_VAL_,0,0x00000000)
+#define SET_RG_TURISMO_TRX_RAM_07(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_07,_VAL_,0,0x00000000)
+#define SET_RG_TURISMO_TRX_RAM_08(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_08,_VAL_,0,0x00000000)
+#define SET_RG_TURISMO_TRX_RAM_09(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_09,_VAL_,0,0x00000000)
+#define SET_RG_TURISMO_TRX_RAM_10(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_10,_VAL_,0,0x00000000)
+#define SET_RG_TURISMO_TRX_RAM_11(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_11,_VAL_,0,0x00000000)
+#define SET_RG_TURISMO_TRX_RAM_12(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_12,_VAL_,0,0x00000000)
+#define SET_RG_TURISMO_TRX_RAM_13(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_13,_VAL_,0,0x00000000)
+#define SET_RG_TURISMO_TRX_RAM_14(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_14,_VAL_,0,0x00000000)
+#define SET_RG_TURISMO_TRX_RAM_15(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_15,_VAL_,0,0x00000000)
+#define SET_RG_TURISMO_TRX_RAM_16(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_16,_VAL_,0,0x00000000)
+#define SET_RG_TURISMO_TRX_RAM_17(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_17,_VAL_,0,0x00000000)
+#define SET_RG_TURISMO_TRX_RAM_18(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_18,_VAL_,0,0x00000000)
+#define SET_RG_TURISMO_TRX_RAM_19(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_19,_VAL_,0,0x00000000)
+#define SET_RG_TURISMO_TRX_RAM_20(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_20,_VAL_,0,0x00000000)
+#define SET_RG_TURISMO_TRX_RAM_21(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_21,_VAL_,0,0x00000000)
+#define SET_RG_TURISMO_TRX_RAM_22(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_22,_VAL_,0,0x00000000)
+#define SET_RG_TURISMO_TRX_RAM_23(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_23,_VAL_,0,0x00000000)
+#define SET_RG_TURISMO_TRX_RAM_24(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_24,_VAL_,0,0x00000000)
+#define SET_RG_TURISMO_TRX_RAM_25(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_25,_VAL_,0,0x00000000)
+#define SET_RG_TURISMO_TRX_RAM_26(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_26,_VAL_,0,0x00000000)
+#define SET_RG_TURISMO_TRX_RAM_27(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_27,_VAL_,0,0x00000000)
+#define SET_RG_TURISMO_TRX_RAM_28(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_28,_VAL_,0,0x00000000)
+#define SET_RG_TURISMO_TRX_RAM_29(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_29,_VAL_,0,0x00000000)
+#define SET_RG_TURISMO_TRX_RAM_30(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_30,_VAL_,0,0x00000000)
+#define SET_RG_TURISMO_TRX_RAM_31(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_31,_VAL_,0,0x00000000)
+#define SET_RG_HW_PINSEL(_VAL_) SET_REG(ADR_MODE_REGISTER,_VAL_,0,0xfffffffe)
+#define SET_RG_HS_3WIRE_MANUAL(_VAL_) SET_REG(ADR_MODE_REGISTER,_VAL_,1,0xfffffffd)
+#define SET_RG_MODE_MANUAL(_VAL_) SET_REG(ADR_MODE_REGISTER,_VAL_,2,0xfffffffb)
+#define SET_RG_5G_TX_GAIN_MANUAL(_VAL_) SET_REG(ADR_MODE_REGISTER,_VAL_,3,0xfffffff7)
+#define SET_RG_RX_GAIN_MANUAL(_VAL_) SET_REG(ADR_MODE_REGISTER,_VAL_,4,0xffffffef)
+#define SET_RG_TX_GAIN_MANUAL(_VAL_) SET_REG(ADR_MODE_REGISTER,_VAL_,5,0xffffffdf)
+#define SET_RG_TXGAIN_PHYCTRL(_VAL_) SET_REG(ADR_MODE_REGISTER,_VAL_,6,0xffffffbf)
+#define SET_RG_RX_AGC(_VAL_) SET_REG(ADR_MODE_REGISTER,_VAL_,7,0xffffff7f)
+#define SET_RG_MODE(_VAL_) SET_REG(ADR_MODE_REGISTER,_VAL_,8,0xfffff8ff)
+#define SET_RG_CAL_INDEX(_VAL_) SET_REG(ADR_MODE_REGISTER,_VAL_,12,0xffff0fff)
+#define SET_RG_RFG(_VAL_) SET_REG(ADR_MODE_REGISTER,_VAL_,16,0xfffcffff)
+#define SET_RG_PGAG(_VAL_) SET_REG(ADR_MODE_REGISTER,_VAL_,18,0xffc3ffff)
+#define SET_RG_BW_HT40(_VAL_) SET_REG(ADR_MODE_REGISTER,_VAL_,22,0xffbfffff)
+#define SET_RG_BW_MANUAL(_VAL_) SET_REG(ADR_MODE_REGISTER,_VAL_,23,0xff7fffff)
+#define SET_RG_TX_GAIN(_VAL_) SET_REG(ADR_MODE_REGISTER,_VAL_,24,0x80ffffff)
+#define SET_RG_TX_TRSW_MANUAL(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,0,0xfffffffe)
+#define SET_RG_EN_TX_TRSW(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,1,0xfffffffd)
+#define SET_RG_RX_LNA_MANUAL(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,2,0xfffffffb)
+#define SET_RG_EN_RX_LNA(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,3,0xfffffff7)
+#define SET_RG_RX_MIXER_MANUAL(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,4,0xffffffef)
+#define SET_RG_EN_RX_MIXER(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,5,0xffffffdf)
+#define SET_RG_RX_DIV2_MANUAL(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,6,0xffffffbf)
+#define SET_RG_EN_RX_DIV2(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,7,0xffffff7f)
+#define SET_RG_RX_LOBUF_MANUAL(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,8,0xfffffeff)
+#define SET_RG_EN_RX_LOBUF(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,9,0xfffffdff)
+#define SET_RG_RX_TZ_MANUAL(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,10,0xfffffbff)
+#define SET_RG_EN_RX_TZ(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,11,0xfffff7ff)
+#define SET_RG_RX_FILTER_MANUAL(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,12,0xffffefff)
+#define SET_RG_EN_RX_FILTER(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,13,0xffffdfff)
+#define SET_RG_RX_ADC_MANUAL(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,14,0xffffbfff)
+#define SET_RG_EN_RX_ADC(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,15,0xffff7fff)
+#define SET_RG_RX_RSSI_MANUAL(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,16,0xfffeffff)
+#define SET_RG_EN_RX_RSSI(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,17,0xfffdffff)
+#define SET_RG_TX_PA_MANUAL(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,18,0xfffbffff)
+#define SET_RG_EN_TX_PA(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,19,0xfff7ffff)
+#define SET_RG_TX_MOD_MANUAL(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,20,0xffefffff)
+#define SET_RG_EN_TX_MOD(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,21,0xffdfffff)
+#define SET_RG_TX_DAC_MANUAL(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,22,0xffbfffff)
+#define SET_RG_EN_TX_DAC(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,23,0xff7fffff)
+#define SET_RG_TX_DIV2_MANUAL(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,24,0xfeffffff)
+#define SET_RG_EN_TX_DIV2(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,25,0xfdffffff)
+#define SET_RG_TX_DIV2_BUF_MANUAL(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,26,0xfbffffff)
+#define SET_RG_EN_TX_DIV2_BUF(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,27,0xf7ffffff)
+#define SET_RG_TX_BT_PA_MANUAL(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,28,0xefffffff)
+#define SET_RG_EN_TX_BT_PA(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,29,0xdfffffff)
+#define SET_RG_EN_IOT_ADC_BUF(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,30,0xbfffffff)
+#define SET_RG_EN_IOT_ADC(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,31,0x7fffffff)
+#define SET_RG_EN_LDO_RX_FE(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,0,0xfffffffe)
+#define SET_RG_EN_LDO_AFE(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,1,0xfffffffd)
+#define SET_RG_EN_IREF_RX(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,2,0xfffffffb)
+#define SET_RG_TX_DAC_CAL_MANUAL(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,3,0xfffffff7)
+#define SET_RG_EN_TX_DAC_CAL(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,4,0xffffffef)
+#define SET_RG_RX_TZ_OUT_TRISTATE_MANUAL(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,5,0xffffffdf)
+#define SET_RG_RX_TZ_OUT_TRISTATE(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,6,0xffffffbf)
+#define SET_RG_TX_SELF_MIXER_MANUAL(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,7,0xffffff7f)
+#define SET_RG_EN_TX_SELF_MIXER(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,8,0xfffffeff)
+#define SET_RG_RX_IQCAL_MANUAL(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,9,0xfffffdff)
+#define SET_RG_EN_RX_IQCAL(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,10,0xfffffbff)
+#define SET_RG_TX_DPD_MANUAL(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,11,0xfffff7ff)
+#define SET_RG_EN_TX_DPD(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,12,0xffffefff)
+#define SET_RG_EN_TX_TSSI(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,14,0xffffbfff)
+#define SET_RG_EN_SARADC(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,15,0xffff7fff)
+#define SET_RG_EN_TX_VTOI_2ND(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,16,0xfffeffff)
+#define SET_RG_TXLPF_BYPASS(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,17,0xfffdffff)
+#define SET_RG_TX_EN_VOLTAGE_IN(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,18,0xfffbffff)
+#define SET_RG_EN_TX_DAC_OUT(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,19,0xfff7ffff)
+#define SET_RG_EN_TX_DAC_VOUT(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,20,0xffefffff)
+#define SET_RG_RX_ABBOUT_TRI_STATE(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,21,0xffdfffff)
+#define SET_RG_EN_RX_TESTNODE(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,22,0xffbfffff)
+#define SET_RG_EN_RX_PADSW(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,23,0xff7fffff)
+#define SET_RG_EN_LDO_RX_FE_FC(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,25,0xfdffffff)
+#define SET_RG_EN_LDO_RX_AFE_FC(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,26,0xfbffffff)
+#define SET_RG_EN_LDO_RX_FE_IQUP(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,27,0xf7ffffff)
+#define SET_RG_EN_LDO_RX_AFE_IQUP(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,28,0xefffffff)
+#define SET_RG_RX_SQDC(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,29,0x1fffffff)
+#define SET_RG_LDO_LEVEL_RX_FE(_VAL_) SET_REG(ADR_2_4G_LDO_REGISTER,_VAL_,0,0xfffffff8)
+#define SET_RG_EN_LDO_RX_FE_BYP(_VAL_) SET_REG(ADR_2_4G_LDO_REGISTER,_VAL_,3,0xfffffff7)
+#define SET_RG_LDO_LEVEL_AFE(_VAL_) SET_REG(ADR_2_4G_LDO_REGISTER,_VAL_,4,0xffffff8f)
+#define SET_RG_EN_LDO_RX_AFE_BYP(_VAL_) SET_REG(ADR_2_4G_LDO_REGISTER,_VAL_,7,0xffffff7f)
+#define SET_RG_SX_LDO_CP_LEVEL(_VAL_) SET_REG(ADR_2_4G_LDO_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_EN_LDO_CP_BYP(_VAL_) SET_REG(ADR_2_4G_LDO_REGISTER,_VAL_,19,0xfff7ffff)
+#define SET_RG_SX_LDO_LO_LEVEL(_VAL_) SET_REG(ADR_2_4G_LDO_REGISTER,_VAL_,20,0xff8fffff)
+#define SET_RG_EN_LDO_LO_BYP(_VAL_) SET_REG(ADR_2_4G_LDO_REGISTER,_VAL_,23,0xff7fffff)
+#define SET_RG_SX_LDO_VCO_LEVEL(_VAL_) SET_REG(ADR_2_4G_LDO_REGISTER,_VAL_,24,0xf8ffffff)
+#define SET_RG_SX_LDO_DIV_LEVEL(_VAL_) SET_REG(ADR_2_4G_LDO_REGISTER,_VAL_,28,0x8fffffff)
+#define SET_RG_EN_LDO_DIV_BYP(_VAL_) SET_REG(ADR_2_4G_LDO_REGISTER,_VAL_,31,0x7fffffff)
+#define SET_RG_WF_RX_ABBCTUNE(_VAL_) SET_REG(ADR_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,0,0xffffffc0)
+#define SET_RG_WF_RX_TZ_CMZ_C(_VAL_) SET_REG(ADR_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,6,0xffffff3f)
+#define SET_RG_WF_RX_FILTERI_COARSE(_VAL_) SET_REG(ADR_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,8,0xfffffcff)
+#define SET_RG_WF_RX_FILTERI1ST(_VAL_) SET_REG(ADR_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,10,0xfffff3ff)
+#define SET_RG_WF_RX_FILTERI2ND(_VAL_) SET_REG(ADR_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,12,0xffffcfff)
+#define SET_RG_WF_RX_FILTERI3RD(_VAL_) SET_REG(ADR_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,14,0xffff3fff)
+#define SET_RG_WF_RX_ABBCFIX(_VAL_) SET_REG(ADR_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,16,0xfffeffff)
+#define SET_RG_WF_RX_ABB_N_MODE(_VAL_) SET_REG(ADR_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,17,0xfffdffff)
+#define SET_RG_WF_RX_ABB_BT_MODE(_VAL_) SET_REG(ADR_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,18,0xfffbffff)
+#define SET_RG_WF_RX_ABB_IDIV3(_VAL_) SET_REG(ADR_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,19,0xfff7ffff)
+#define SET_RG_WF_RX_EN_IDACA_COARSE(_VAL_) SET_REG(ADR_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,20,0xffefffff)
+#define SET_RG_WF_RX_EN_LOOPA(_VAL_) SET_REG(ADR_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,21,0xffdfffff)
+#define SET_RG_WF_RX_TZ_CMZ_R(_VAL_) SET_REG(ADR_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,22,0xff3fffff)
+#define SET_RG_WF_RX_FILTERVCM(_VAL_) SET_REG(ADR_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,24,0xf8ffffff)
+#define SET_RG_WF_RX_OUTVCM(_VAL_) SET_REG(ADR_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,28,0x8fffffff)
+#define SET_RG_WF_N_RX_ABBCTUNE(_VAL_) SET_REG(ADR_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,0,0xffffffc0)
+#define SET_RG_WF_N_RX_TZ_CMZ_C(_VAL_) SET_REG(ADR_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,6,0xffffff3f)
+#define SET_RG_WF_N_RX_FILTERI_COARSE(_VAL_) SET_REG(ADR_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,8,0xfffffcff)
+#define SET_RG_WF_N_RX_FILTERI1ST(_VAL_) SET_REG(ADR_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,10,0xfffff3ff)
+#define SET_RG_WF_N_RX_FILTERI2ND(_VAL_) SET_REG(ADR_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,12,0xffffcfff)
+#define SET_RG_WF_N_RX_FILTERI3RD(_VAL_) SET_REG(ADR_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,14,0xffff3fff)
+#define SET_RG_WF_N_RX_ABBCFIX(_VAL_) SET_REG(ADR_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,16,0xfffeffff)
+#define SET_RG_WF_N_RX_ABB_N_MODE(_VAL_) SET_REG(ADR_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,17,0xfffdffff)
+#define SET_RG_WF_N_RX_ABB_BT_MODE(_VAL_) SET_REG(ADR_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,18,0xfffbffff)
+#define SET_RG_WF_N_RX_ABB_IDIV3(_VAL_) SET_REG(ADR_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,19,0xfff7ffff)
+#define SET_RG_WF_N_RX_EN_IDACA_COARSE(_VAL_) SET_REG(ADR_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,20,0xffefffff)
+#define SET_RG_WF_N_RX_EN_LOOPA(_VAL_) SET_REG(ADR_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,21,0xffdfffff)
+#define SET_RG_WF_N_RX_TZ_CMZ_R(_VAL_) SET_REG(ADR_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,22,0xff3fffff)
+#define SET_RG_WF_N_RX_FILTERVCM(_VAL_) SET_REG(ADR_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,24,0xf8ffffff)
+#define SET_RG_WF_N_RX_OUTVCM(_VAL_) SET_REG(ADR_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,28,0x8fffffff)
+#define SET_RG_BT_RX_ABBCTUNE(_VAL_) SET_REG(ADR_BT_RX_FILTER_REGISTER,_VAL_,0,0xffffffc0)
+#define SET_RG_BT_RX_TZ_CMZ_C(_VAL_) SET_REG(ADR_BT_RX_FILTER_REGISTER,_VAL_,6,0xffffff3f)
+#define SET_RG_BT_RX_FILTERI_COARSE(_VAL_) SET_REG(ADR_BT_RX_FILTER_REGISTER,_VAL_,8,0xfffffcff)
+#define SET_RG_BT_RX_FILTERI1ST(_VAL_) SET_REG(ADR_BT_RX_FILTER_REGISTER,_VAL_,10,0xfffff3ff)
+#define SET_RG_BT_RX_FILTERI2ND(_VAL_) SET_REG(ADR_BT_RX_FILTER_REGISTER,_VAL_,12,0xffffcfff)
+#define SET_RG_BT_RX_FILTERI3RD(_VAL_) SET_REG(ADR_BT_RX_FILTER_REGISTER,_VAL_,14,0xffff3fff)
+#define SET_RG_BT_RX_ABBCFIX(_VAL_) SET_REG(ADR_BT_RX_FILTER_REGISTER,_VAL_,16,0xfffeffff)
+#define SET_RG_BT_RX_ABB_N_MODE(_VAL_) SET_REG(ADR_BT_RX_FILTER_REGISTER,_VAL_,17,0xfffdffff)
+#define SET_RG_BT_RX_ABB_BT_MODE(_VAL_) SET_REG(ADR_BT_RX_FILTER_REGISTER,_VAL_,18,0xfffbffff)
+#define SET_RG_BT_RX_ABB_IDIV3(_VAL_) SET_REG(ADR_BT_RX_FILTER_REGISTER,_VAL_,19,0xfff7ffff)
+#define SET_RG_BT_RX_EN_IDACA_COARSE(_VAL_) SET_REG(ADR_BT_RX_FILTER_REGISTER,_VAL_,20,0xffefffff)
+#define SET_RG_BT_RX_EN_LOOPA(_VAL_) SET_REG(ADR_BT_RX_FILTER_REGISTER,_VAL_,21,0xffdfffff)
+#define SET_RG_BT_RX_TZ_CMZ_R(_VAL_) SET_REG(ADR_BT_RX_FILTER_REGISTER,_VAL_,22,0xff3fffff)
+#define SET_RG_BT_RX_FILTERVCM(_VAL_) SET_REG(ADR_BT_RX_FILTER_REGISTER,_VAL_,24,0xf8ffffff)
+#define SET_RG_BT_RX_OUTVCM(_VAL_) SET_REG(ADR_BT_RX_FILTER_REGISTER,_VAL_,28,0x8fffffff)
+#define SET_RG_RX_ADCRSSI_VCM(_VAL_) SET_REG(ADR_2_4G_RX_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_RX_REC_LPFCORNER(_VAL_) SET_REG(ADR_2_4G_RX_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_RX_ADCRSSI_CLKSEL(_VAL_) SET_REG(ADR_2_4G_RX_REGISTER,_VAL_,4,0xffffffef)
+#define SET_RG_RSSI_CLOCK_GATING(_VAL_) SET_REG(ADR_2_4G_RX_REGISTER,_VAL_,5,0xffffffdf)
+#define SET_RG_RX_IDACA_COARSE_PMOS_ON(_VAL_) SET_REG(ADR_2_4G_RX_REGISTER,_VAL_,6,0xffffffbf)
+#define SET_RG_TX_DPDGM_BIAS(_VAL_) SET_REG(ADR_2_4G_RX_REGISTER,_VAL_,8,0xfffff0ff)
+#define SET_RG_TX_DPD_DIV(_VAL_) SET_REG(ADR_2_4G_RX_REGISTER,_VAL_,12,0xffff0fff)
+#define SET_RG_TX_TSSI_BIAS(_VAL_) SET_REG(ADR_2_4G_RX_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_TX_TSSI_DIV(_VAL_) SET_REG(ADR_2_4G_RX_REGISTER,_VAL_,19,0xffc7ffff)
+#define SET_RG_TX_TSSI_TEST(_VAL_) SET_REG(ADR_2_4G_RX_REGISTER,_VAL_,22,0xff3fffff)
+#define SET_RG_TX_TSSI_TESTMODE(_VAL_) SET_REG(ADR_2_4G_RX_REGISTER,_VAL_,24,0xfeffffff)
+#define SET_RG_EN_RX_RSSI_TESTNODE(_VAL_) SET_REG(ADR_2_4G_RX_REGISTER,_VAL_,25,0xf1ffffff)
+#define SET_RG_RX_LNA_TRI_SEL(_VAL_) SET_REG(ADR_2_4G_RX_REGISTER,_VAL_,28,0xcfffffff)
+#define SET_RG_RX_LNA_SETTLE(_VAL_) SET_REG(ADR_2_4G_RX_REGISTER,_VAL_,30,0x3fffffff)
+#define SET_RG_WF_TXPGA_CAPSW(_VAL_) SET_REG(ADR_2_4G_TX_FE_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_WF_TX_DIV_VSET(_VAL_) SET_REG(ADR_2_4G_TX_FE_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_WF_TX_LOBUF_VSET(_VAL_) SET_REG(ADR_2_4G_TX_FE_REGISTER,_VAL_,4,0xffffffcf)
+#define SET_RG_WF_TXMOD_GMCELL_FINE(_VAL_) SET_REG(ADR_2_4G_TX_FE_REGISTER,_VAL_,8,0xfffff8ff)
+#define SET_RG_BT_TXPGA_CAPSW(_VAL_) SET_REG(ADR_2_4G_TX_FE_REGISTER,_VAL_,12,0xffffcfff)
+#define SET_RG_BT_TX_DIV_VSET(_VAL_) SET_REG(ADR_2_4G_TX_FE_REGISTER,_VAL_,14,0xffff3fff)
+#define SET_RG_BT_TX_LOBUF_VSET(_VAL_) SET_REG(ADR_2_4G_TX_FE_REGISTER,_VAL_,16,0xfffcffff)
+#define SET_RG_BT_TXMOD_GMCELL_FINE(_VAL_) SET_REG(ADR_2_4G_TX_FE_REGISTER,_VAL_,20,0xff8fffff)
+#define SET_RG_WF_PACELL_EN(_VAL_) SET_REG(ADR_2_4G_TX_PA_REGISTER,_VAL_,0,0xfffffff8)
+#define SET_RG_WF_PABIAS_CTRL(_VAL_) SET_REG(ADR_2_4G_TX_PA_REGISTER,_VAL_,4,0xffffff0f)
+#define SET_RG_WF_TX_PA1_VCAS(_VAL_) SET_REG(ADR_2_4G_TX_PA_REGISTER,_VAL_,8,0xfffff8ff)
+#define SET_RG_WF_TX_PA2_VCAS(_VAL_) SET_REG(ADR_2_4G_TX_PA_REGISTER,_VAL_,12,0xffff8fff)
+#define SET_RG_WF_TX_PA3_VCAS(_VAL_) SET_REG(ADR_2_4G_TX_PA_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_WF_BTPASW(_VAL_) SET_REG(ADR_2_4G_TX_PA_REGISTER,_VAL_,20,0xffefffff)
+#define SET_RG_BTRX_BTPASW(_VAL_) SET_REG(ADR_2_4G_TX_PA_REGISTER,_VAL_,21,0xffdfffff)
+#define SET_RG_BTTX_BTPASW(_VAL_) SET_REG(ADR_2_4G_TX_PA_REGISTER,_VAL_,22,0xffbfffff)
+#define SET_RG_BT_PABIAS_2X(_VAL_) SET_REG(ADR_2_4G_TX_PA_REGISTER,_VAL_,23,0xff7fffff)
+#define SET_RG_BT_PABIAS_CTRL(_VAL_) SET_REG(ADR_2_4G_TX_PA_REGISTER,_VAL_,24,0xf0ffffff)
+#define SET_RG_BT_TX_PA_VCAS(_VAL_) SET_REG(ADR_2_4G_TX_PA_REGISTER,_VAL_,28,0x8fffffff)
+#define SET_RG_TXPGA_MAIN(_VAL_) SET_REG(ADR_2_4G_TX_REGISTER,_VAL_,0,0xffffffc0)
+#define SET_RG_TXPGA_STEER(_VAL_) SET_REG(ADR_2_4G_TX_REGISTER,_VAL_,6,0xfffff03f)
+#define SET_RG_TXMOD_GMCELL(_VAL_) SET_REG(ADR_2_4G_TX_REGISTER,_VAL_,12,0xffffcfff)
+#define SET_RG_TXLPF_GMCELL(_VAL_) SET_REG(ADR_2_4G_TX_REGISTER,_VAL_,14,0xffff3fff)
+#define SET_RG_WF_TX_GAIN_OFFSET(_VAL_) SET_REG(ADR_2_4G_TX_REGISTER,_VAL_,16,0xfff0ffff)
+#define SET_RG_BT_TX_GAIN_OFFSET(_VAL_) SET_REG(ADR_2_4G_TX_REGISTER,_VAL_,20,0xff0fffff)
+#define SET_RG_TX_VTOI_CURRENT(_VAL_) SET_REG(ADR_2_4G_TX_REGISTER,_VAL_,24,0xfcffffff)
+#define SET_RG_TX_VTOI_GM(_VAL_) SET_REG(ADR_2_4G_TX_REGISTER,_VAL_,26,0xf3ffffff)
+#define SET_RG_TX_VTOI_OPTION(_VAL_) SET_REG(ADR_2_4G_TX_REGISTER,_VAL_,28,0xcfffffff)
+#define SET_RG_TX_VTOI_FS(_VAL_) SET_REG(ADR_2_4G_TX_REGISTER,_VAL_,30,0xbfffffff)
+#define SET_RG_WF_RX_HG_LNA_GC(_VAL_) SET_REG(ADR_2_4G_RX_FE_HG_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_WF_RX_HG_TZ_GC(_VAL_) SET_REG(ADR_2_4G_RX_FE_HG_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_WF_RX_HG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_2_4G_RX_FE_HG_REGISTER,_VAL_,4,0xffffff0f)
+#define SET_RG_WF_RX_HG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_2_4G_RX_FE_HG_REGISTER,_VAL_,8,0xfffff0ff)
+#define SET_RG_WF_RX_HG_LNALG_BIAS(_VAL_) SET_REG(ADR_2_4G_RX_FE_HG_REGISTER,_VAL_,12,0xffff0fff)
+#define SET_RG_WF_RX_HG_TZ_CAP(_VAL_) SET_REG(ADR_2_4G_RX_FE_HG_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_WF_RX_HG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_2_4G_RX_FE_HG_REGISTER,_VAL_,20,0xffcfffff)
+#define SET_RG_WF_RX_HG_DIV2_CORE(_VAL_) SET_REG(ADR_2_4G_RX_FE_HG_REGISTER,_VAL_,22,0xff3fffff)
+#define SET_RG_WF_RX_HG_LOBUF(_VAL_) SET_REG(ADR_2_4G_RX_FE_HG_REGISTER,_VAL_,24,0xfcffffff)
+#define SET_RG_WF_RX_HG_TZI(_VAL_) SET_REG(ADR_2_4G_RX_FE_HG_REGISTER,_VAL_,26,0xe3ffffff)
+#define SET_RG_WF_RX_HG_TZ_VCM(_VAL_) SET_REG(ADR_2_4G_RX_FE_HG_REGISTER,_VAL_,29,0x1fffffff)
+#define SET_RG_WF_RX_MG_LNA_GC(_VAL_) SET_REG(ADR_2_4G_RX_FE_MG_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_WF_RX_MG_TZ_GC(_VAL_) SET_REG(ADR_2_4G_RX_FE_MG_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_WF_RX_MG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_2_4G_RX_FE_MG_REGISTER,_VAL_,4,0xffffff0f)
+#define SET_RG_WF_RX_MG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_2_4G_RX_FE_MG_REGISTER,_VAL_,8,0xfffff0ff)
+#define SET_RG_WF_RX_MG_LNALG_BIAS(_VAL_) SET_REG(ADR_2_4G_RX_FE_MG_REGISTER,_VAL_,12,0xffff0fff)
+#define SET_RG_WF_RX_MG_TZ_CAP(_VAL_) SET_REG(ADR_2_4G_RX_FE_MG_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_WF_RX_MG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_2_4G_RX_FE_MG_REGISTER,_VAL_,20,0xffcfffff)
+#define SET_RG_WF_RX_MG_DIV2_CORE(_VAL_) SET_REG(ADR_2_4G_RX_FE_MG_REGISTER,_VAL_,22,0xff3fffff)
+#define SET_RG_WF_RX_MG_LOBUF(_VAL_) SET_REG(ADR_2_4G_RX_FE_MG_REGISTER,_VAL_,24,0xfcffffff)
+#define SET_RG_WF_RX_MG_TZI(_VAL_) SET_REG(ADR_2_4G_RX_FE_MG_REGISTER,_VAL_,26,0xe3ffffff)
+#define SET_RG_WF_RX_MG_TZ_VCM(_VAL_) SET_REG(ADR_2_4G_RX_FE_MG_REGISTER,_VAL_,29,0x1fffffff)
+#define SET_RG_WF_RX_LG_LNA_GC(_VAL_) SET_REG(ADR_2_4G_RX_FE_LG_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_WF_RX_LG_TZ_GC(_VAL_) SET_REG(ADR_2_4G_RX_FE_LG_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_WF_RX_LG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_2_4G_RX_FE_LG_REGISTER,_VAL_,4,0xffffff0f)
+#define SET_RG_WF_RX_LG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_2_4G_RX_FE_LG_REGISTER,_VAL_,8,0xfffff0ff)
+#define SET_RG_WF_RX_LG_LNALG_BIAS(_VAL_) SET_REG(ADR_2_4G_RX_FE_LG_REGISTER,_VAL_,12,0xffff0fff)
+#define SET_RG_WF_RX_LG_TZ_CAP(_VAL_) SET_REG(ADR_2_4G_RX_FE_LG_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_WF_RX_LG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_2_4G_RX_FE_LG_REGISTER,_VAL_,20,0xffcfffff)
+#define SET_RG_WF_RX_LG_DIV2_CORE(_VAL_) SET_REG(ADR_2_4G_RX_FE_LG_REGISTER,_VAL_,22,0xff3fffff)
+#define SET_RG_WF_RX_LG_LOBUF(_VAL_) SET_REG(ADR_2_4G_RX_FE_LG_REGISTER,_VAL_,24,0xfcffffff)
+#define SET_RG_WF_RX_LG_TZI(_VAL_) SET_REG(ADR_2_4G_RX_FE_LG_REGISTER,_VAL_,26,0xe3ffffff)
+#define SET_RG_WF_RX_LG_TZ_VCM(_VAL_) SET_REG(ADR_2_4G_RX_FE_LG_REGISTER,_VAL_,29,0x1fffffff)
+#define SET_RG_WF_RX_ULG_LNA_GC(_VAL_) SET_REG(ADR_2_4G_RX_FE_ULG_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_WF_RX_ULG_TZ_GC(_VAL_) SET_REG(ADR_2_4G_RX_FE_ULG_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_WF_RX_ULG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_2_4G_RX_FE_ULG_REGISTER,_VAL_,4,0xffffff0f)
+#define SET_RG_WF_RX_ULG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_2_4G_RX_FE_ULG_REGISTER,_VAL_,8,0xfffff0ff)
+#define SET_RG_WF_RX_ULG_LNALG_BIAS(_VAL_) SET_REG(ADR_2_4G_RX_FE_ULG_REGISTER,_VAL_,12,0xffff0fff)
+#define SET_RG_WF_RX_ULG_TZ_CAP(_VAL_) SET_REG(ADR_2_4G_RX_FE_ULG_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_WF_RX_ULG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_2_4G_RX_FE_ULG_REGISTER,_VAL_,20,0xffcfffff)
+#define SET_RG_WF_RX_ULG_DIV2_CORE(_VAL_) SET_REG(ADR_2_4G_RX_FE_ULG_REGISTER,_VAL_,22,0xff3fffff)
+#define SET_RG_WF_RX_ULG_LOBUF(_VAL_) SET_REG(ADR_2_4G_RX_FE_ULG_REGISTER,_VAL_,24,0xfcffffff)
+#define SET_RG_WF_RX_ULG_TZI(_VAL_) SET_REG(ADR_2_4G_RX_FE_ULG_REGISTER,_VAL_,26,0xe3ffffff)
+#define SET_RG_WF_RX_ULG_TZ_VCM(_VAL_) SET_REG(ADR_2_4G_RX_FE_ULG_REGISTER,_VAL_,29,0x1fffffff)
+#define SET_RG_BT_RX_HG_LNA_GC(_VAL_) SET_REG(ADR_BT_RX_FE_HG_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_BT_RX_HG_TZ_GC(_VAL_) SET_REG(ADR_BT_RX_FE_HG_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_BT_RX_HG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_BT_RX_FE_HG_REGISTER,_VAL_,4,0xffffff0f)
+#define SET_RG_BT_RX_HG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_BT_RX_FE_HG_REGISTER,_VAL_,8,0xfffff0ff)
+#define SET_RG_BT_RX_HG_LNALG_BIAS(_VAL_) SET_REG(ADR_BT_RX_FE_HG_REGISTER,_VAL_,12,0xffff0fff)
+#define SET_RG_BT_RX_HG_TZ_CAP(_VAL_) SET_REG(ADR_BT_RX_FE_HG_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_BT_RX_HG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_BT_RX_FE_HG_REGISTER,_VAL_,20,0xffcfffff)
+#define SET_RG_BT_RX_HG_DIV2_CORE(_VAL_) SET_REG(ADR_BT_RX_FE_HG_REGISTER,_VAL_,22,0xff3fffff)
+#define SET_RG_BT_RX_HG_LOBUF(_VAL_) SET_REG(ADR_BT_RX_FE_HG_REGISTER,_VAL_,24,0xfcffffff)
+#define SET_RG_BT_RX_HG_TZI(_VAL_) SET_REG(ADR_BT_RX_FE_HG_REGISTER,_VAL_,26,0xe3ffffff)
+#define SET_RG_BT_RX_HG_TZ_VCM(_VAL_) SET_REG(ADR_BT_RX_FE_HG_REGISTER,_VAL_,29,0x1fffffff)
+#define SET_RG_BT_RX_MG_LNA_GC(_VAL_) SET_REG(ADR_BT_RX_FE_MG_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_BT_RX_MG_TZ_GC(_VAL_) SET_REG(ADR_BT_RX_FE_MG_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_BT_RX_MG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_BT_RX_FE_MG_REGISTER,_VAL_,4,0xffffff0f)
+#define SET_RG_BT_RX_MG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_BT_RX_FE_MG_REGISTER,_VAL_,8,0xfffff0ff)
+#define SET_RG_BT_RX_MG_LNALG_BIAS(_VAL_) SET_REG(ADR_BT_RX_FE_MG_REGISTER,_VAL_,12,0xffff0fff)
+#define SET_RG_BT_RX_MG_TZ_CAP(_VAL_) SET_REG(ADR_BT_RX_FE_MG_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_BT_RX_MG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_BT_RX_FE_MG_REGISTER,_VAL_,20,0xffcfffff)
+#define SET_RG_BT_RX_MG_DIV2_CORE(_VAL_) SET_REG(ADR_BT_RX_FE_MG_REGISTER,_VAL_,22,0xff3fffff)
+#define SET_RG_BT_RX_MG_LOBUF(_VAL_) SET_REG(ADR_BT_RX_FE_MG_REGISTER,_VAL_,24,0xfcffffff)
+#define SET_RG_BT_RX_MG_TZI(_VAL_) SET_REG(ADR_BT_RX_FE_MG_REGISTER,_VAL_,26,0xe3ffffff)
+#define SET_RG_BT_RX_MG_TZ_VCM(_VAL_) SET_REG(ADR_BT_RX_FE_MG_REGISTER,_VAL_,29,0x1fffffff)
+#define SET_RG_BT_RX_LG_LNA_GC(_VAL_) SET_REG(ADR_BT_RX_FE_LG_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_BT_RX_LG_TZ_GC(_VAL_) SET_REG(ADR_BT_RX_FE_LG_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_BT_RX_LG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_BT_RX_FE_LG_REGISTER,_VAL_,4,0xffffff0f)
+#define SET_RG_BT_RX_LG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_BT_RX_FE_LG_REGISTER,_VAL_,8,0xfffff0ff)
+#define SET_RG_BT_RX_LG_LNALG_BIAS(_VAL_) SET_REG(ADR_BT_RX_FE_LG_REGISTER,_VAL_,12,0xffff0fff)
+#define SET_RG_BT_RX_LG_TZ_CAP(_VAL_) SET_REG(ADR_BT_RX_FE_LG_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_BT_RX_LG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_BT_RX_FE_LG_REGISTER,_VAL_,20,0xffcfffff)
+#define SET_RG_BT_RX_LG_DIV2_CORE(_VAL_) SET_REG(ADR_BT_RX_FE_LG_REGISTER,_VAL_,22,0xff3fffff)
+#define SET_RG_BT_RX_LG_LOBUF(_VAL_) SET_REG(ADR_BT_RX_FE_LG_REGISTER,_VAL_,24,0xfcffffff)
+#define SET_RG_BT_RX_LG_TZI(_VAL_) SET_REG(ADR_BT_RX_FE_LG_REGISTER,_VAL_,26,0xe3ffffff)
+#define SET_RG_BT_RX_LG_TZ_VCM(_VAL_) SET_REG(ADR_BT_RX_FE_LG_REGISTER,_VAL_,29,0x1fffffff)
+#define SET_RG_BT_RX_ULG_LNA_GC(_VAL_) SET_REG(ADR_BT_RX_FE_ULG_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_BT_RX_ULG_TZ_GC(_VAL_) SET_REG(ADR_BT_RX_FE_ULG_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_BT_RX_ULG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_BT_RX_FE_ULG_REGISTER,_VAL_,4,0xffffff0f)
+#define SET_RG_BT_RX_ULG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_BT_RX_FE_ULG_REGISTER,_VAL_,8,0xfffff0ff)
+#define SET_RG_BT_RX_ULG_LNALG_BIAS(_VAL_) SET_REG(ADR_BT_RX_FE_ULG_REGISTER,_VAL_,12,0xffff0fff)
+#define SET_RG_BT_RX_ULG_TZ_CAP(_VAL_) SET_REG(ADR_BT_RX_FE_ULG_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_BT_RX_ULG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_BT_RX_FE_ULG_REGISTER,_VAL_,20,0xffcfffff)
+#define SET_RG_BT_RX_ULG_DIV2_CORE(_VAL_) SET_REG(ADR_BT_RX_FE_ULG_REGISTER,_VAL_,22,0xff3fffff)
+#define SET_RG_BT_RX_ULG_LOBUF(_VAL_) SET_REG(ADR_BT_RX_FE_ULG_REGISTER,_VAL_,24,0xfcffffff)
+#define SET_RG_BT_RX_ULG_TZI(_VAL_) SET_REG(ADR_BT_RX_FE_ULG_REGISTER,_VAL_,26,0xe3ffffff)
+#define SET_RG_BT_RX_ULG_TZ_VCM(_VAL_) SET_REG(ADR_BT_RX_FE_ULG_REGISTER,_VAL_,29,0x1fffffff)
+#define SET_RG_RX_ADC_CLKSEL(_VAL_) SET_REG(ADR_WBT_RX_ADC_REGISTER,_VAL_,0,0xfffffffe)
+#define SET_RG_RX_ADC_DNLEN(_VAL_) SET_REG(ADR_WBT_RX_ADC_REGISTER,_VAL_,1,0xfffffffd)
+#define SET_RG_RX_ADC_METAEN(_VAL_) SET_REG(ADR_WBT_RX_ADC_REGISTER,_VAL_,2,0xfffffffb)
+#define SET_RG_RX_ADC_TFLAG(_VAL_) SET_REG(ADR_WBT_RX_ADC_REGISTER,_VAL_,3,0xfffffff7)
+#define SET_RG_RX_ADC_TSEL(_VAL_) SET_REG(ADR_WBT_RX_ADC_REGISTER,_VAL_,4,0xffffff0f)
+#define SET_RG_WF_RX_ADC_ICMP(_VAL_) SET_REG(ADR_WBT_RX_ADC_REGISTER,_VAL_,8,0xfffffcff)
+#define SET_RG_WF_RX_ADC_VCMI(_VAL_) SET_REG(ADR_WBT_RX_ADC_REGISTER,_VAL_,10,0xfffff3ff)
+#define SET_RG_WF_RX_ADC_CLOAD(_VAL_) SET_REG(ADR_WBT_RX_ADC_REGISTER,_VAL_,12,0xffffcfff)
+#define SET_RG_WF_RX_ADC_PSW(_VAL_) SET_REG(ADR_WBT_RX_ADC_REGISTER,_VAL_,14,0xffffbfff)
+#define SET_RG_BT_RX_ADC_ICMP(_VAL_) SET_REG(ADR_WBT_RX_ADC_REGISTER,_VAL_,16,0xfffcffff)
+#define SET_RG_BT_RX_ADC_VCMI(_VAL_) SET_REG(ADR_WBT_RX_ADC_REGISTER,_VAL_,18,0xfff3ffff)
+#define SET_RG_BT_RX_ADC_CLOAD(_VAL_) SET_REG(ADR_WBT_RX_ADC_REGISTER,_VAL_,20,0xffcfffff)
+#define SET_RG_BT_RX_ADC_PSW(_VAL_) SET_REG(ADR_WBT_RX_ADC_REGISTER,_VAL_,22,0xffbfffff)
+#define SET_RG_SARADC_5G_TSSI(_VAL_) SET_REG(ADR_WBT_RX_ADC_REGISTER,_VAL_,23,0xff7fffff)
+#define SET_RG_SARADC_VRSEL(_VAL_) SET_REG(ADR_WBT_RX_ADC_REGISTER,_VAL_,24,0xfcffffff)
+#define SET_RG_EN_SAR_TEST(_VAL_) SET_REG(ADR_WBT_RX_ADC_REGISTER,_VAL_,26,0xf3ffffff)
+#define SET_RG_SARADC_THERMAL(_VAL_) SET_REG(ADR_WBT_RX_ADC_REGISTER,_VAL_,28,0xefffffff)
+#define SET_RG_SARADC_TSSI(_VAL_) SET_REG(ADR_WBT_RX_ADC_REGISTER,_VAL_,29,0xdfffffff)
+#define SET_RG_CLK_SAR_SEL(_VAL_) SET_REG(ADR_WBT_RX_ADC_REGISTER,_VAL_,30,0x3fffffff)
+#define SET_RG_WF_TX_DACI1ST(_VAL_) SET_REG(ADR_WIFI_TX_DAC_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_WF_TX_DACLPF_ICOARSE(_VAL_) SET_REG(ADR_WIFI_TX_DAC_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_WF_TX_DACLPF_IFINE(_VAL_) SET_REG(ADR_WIFI_TX_DAC_REGISTER,_VAL_,4,0xffffffcf)
+#define SET_RG_WF_TX_DACLPF_VCM(_VAL_) SET_REG(ADR_WIFI_TX_DAC_REGISTER,_VAL_,6,0xffffff3f)
+#define SET_RG_WF_TX_DAC_IBIAS(_VAL_) SET_REG(ADR_WIFI_TX_DAC_REGISTER,_VAL_,8,0xfffffcff)
+#define SET_RG_WF_TX_DAC_IATTN(_VAL_) SET_REG(ADR_WIFI_TX_DAC_REGISTER,_VAL_,10,0xfffffbff)
+#define SET_RG_WF_TXLPF_BOOSTI(_VAL_) SET_REG(ADR_WIFI_TX_DAC_REGISTER,_VAL_,11,0xfffff7ff)
+#define SET_RG_WF_TX_DAC_RCAL(_VAL_) SET_REG(ADR_WIFI_TX_DAC_REGISTER,_VAL_,12,0xffffcfff)
+#define SET_RG_WF_TX_DAC_CKEDGE_SEL(_VAL_) SET_REG(ADR_WIFI_TX_DAC_REGISTER,_VAL_,14,0xffffbfff)
+#define SET_RG_WF_TX_DAC_OS(_VAL_) SET_REG(ADR_WIFI_TX_DAC_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_WF_TX_DAC_IOFFSET(_VAL_) SET_REG(ADR_WIFI_TX_DAC_REGISTER,_VAL_,20,0xff0fffff)
+#define SET_RG_WF_TX_DAC_QOFFSET(_VAL_) SET_REG(ADR_WIFI_TX_DAC_REGISTER,_VAL_,24,0xf0ffffff)
+#define SET_RG_TX_DAC_TSEL(_VAL_) SET_REG(ADR_WIFI_TX_DAC_REGISTER,_VAL_,28,0x0fffffff)
+#define SET_RG_BT_TX_DACI1ST(_VAL_) SET_REG(ADR_BT_TX_DAC_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_BT_TX_DACLPF_ICOARSE(_VAL_) SET_REG(ADR_BT_TX_DAC_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_BT_TX_DACLPF_IFINE(_VAL_) SET_REG(ADR_BT_TX_DAC_REGISTER,_VAL_,4,0xffffffcf)
+#define SET_RG_BT_TX_DACLPF_VCM(_VAL_) SET_REG(ADR_BT_TX_DAC_REGISTER,_VAL_,6,0xffffff3f)
+#define SET_RG_BT_TX_DAC_IBIAS(_VAL_) SET_REG(ADR_BT_TX_DAC_REGISTER,_VAL_,8,0xfffffcff)
+#define SET_RG_BT_TX_DAC_IATTN(_VAL_) SET_REG(ADR_BT_TX_DAC_REGISTER,_VAL_,10,0xfffffbff)
+#define SET_RG_BT_TXLPF_BOOSTI(_VAL_) SET_REG(ADR_BT_TX_DAC_REGISTER,_VAL_,11,0xfffff7ff)
+#define SET_RG_BT_TX_DAC_RCAL(_VAL_) SET_REG(ADR_BT_TX_DAC_REGISTER,_VAL_,12,0xffffcfff)
+#define SET_RG_BT_TX_DAC_CKEDGE_SEL(_VAL_) SET_REG(ADR_BT_TX_DAC_REGISTER,_VAL_,14,0xffffbfff)
+#define SET_RG_BT_TX_DAC_OS(_VAL_) SET_REG(ADR_BT_TX_DAC_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_BT_TX_DAC_IOFFSET(_VAL_) SET_REG(ADR_BT_TX_DAC_REGISTER,_VAL_,20,0xff0fffff)
+#define SET_RG_BT_TX_DAC_QOFFSET(_VAL_) SET_REG(ADR_BT_TX_DAC_REGISTER,_VAL_,24,0xf0ffffff)
+#define SET_RG_SX_EN_MAN(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,0,0xfffffffe)
+#define SET_RG_SX_EN(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,1,0xfffffffd)
+#define SET_RG_EN_SX_CP_MAN(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,2,0xfffffffb)
+#define SET_RG_EN_SX_CP(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,3,0xfffffff7)
+#define SET_RG_EN_SX_DIV_MAN(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,4,0xffffffef)
+#define SET_RG_EN_SX_DIV(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,5,0xffffffdf)
+#define SET_RG_EN_SX_VCO_MAN(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,6,0xffffffbf)
+#define SET_RG_EN_SX_VCO(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,7,0xffffff7f)
+#define SET_RG_SX_PFD_RST_MAN(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,8,0xfffffeff)
+#define SET_RG_SX_PFD_RST(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,9,0xfffffdff)
+#define SET_RG_SX_UOP_MAN(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,10,0xfffffbff)
+#define SET_RG_SX_UOP_EN(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,11,0xfffff7ff)
+#define SET_RG_EN_VCOBF_TXMB_MAN(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,12,0xffffefff)
+#define SET_RG_EN_VCOBF_TXMB(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,13,0xffffdfff)
+#define SET_RG_EN_VCOBF_TXOB_MAN(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,14,0xffffbfff)
+#define SET_RG_EN_VCOBF_TXOB(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,15,0xffff7fff)
+#define SET_RG_EN_VCOBF_RXMB_MAN(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,16,0xfffeffff)
+#define SET_RG_EN_VCOBF_RXMB(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,17,0xfffdffff)
+#define SET_RG_EN_VCOBF_RXOB_MAN(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,18,0xfffbffff)
+#define SET_RG_EN_VCOBF_RXOB(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,19,0xfff7ffff)
+#define SET_RG_EN_VCOBF_DIVCK_MAN(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,20,0xffefffff)
+#define SET_RG_EN_VCOBF_DIVCK(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,21,0xffdfffff)
+#define SET_RG_SX_SBCAL_DIS(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,23,0xff7fffff)
+#define SET_RG_SX_SBCAL_AW(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,24,0xfeffffff)
+#define SET_RG_SX_AAC_DIS(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,26,0xfbffffff)
+#define SET_RG_SX_TTL_DIS(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,27,0xf7ffffff)
+#define SET_RG_SX_CAL_INIT(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,29,0x1fffffff)
+#define SET_RG_EN_SX_LDO_MAN(_VAL_) SET_REG(ADR_SX_2_4G_LDO_REGISTER,_VAL_,0,0xfffffffe)
+#define SET_RG_EN_LDO_CP(_VAL_) SET_REG(ADR_SX_2_4G_LDO_REGISTER,_VAL_,1,0xfffffffd)
+#define SET_RG_EN_LDO_DIV(_VAL_) SET_REG(ADR_SX_2_4G_LDO_REGISTER,_VAL_,2,0xfffffffb)
+#define SET_RG_EN_LDO_LO(_VAL_) SET_REG(ADR_SX_2_4G_LDO_REGISTER,_VAL_,3,0xfffffff7)
+#define SET_RG_EN_LDO_VCO(_VAL_) SET_REG(ADR_SX_2_4G_LDO_REGISTER,_VAL_,4,0xffffffef)
+#define SET_RG_EN_LDO_VCO_PSW(_VAL_) SET_REG(ADR_SX_2_4G_LDO_REGISTER,_VAL_,9,0xfffffdff)
+#define SET_RG_EN_LDO_VCO_VDD33(_VAL_) SET_REG(ADR_SX_2_4G_LDO_REGISTER,_VAL_,10,0xfffffbff)
+#define SET_RG_EN_LDO_CP_IQUP(_VAL_) SET_REG(ADR_SX_2_4G_LDO_REGISTER,_VAL_,11,0xfffff7ff)
+#define SET_RG_EN_LDO_DIV_IQUP(_VAL_) SET_REG(ADR_SX_2_4G_LDO_REGISTER,_VAL_,12,0xffffefff)
+#define SET_RG_EN_LDO_LO_IQUP(_VAL_) SET_REG(ADR_SX_2_4G_LDO_REGISTER,_VAL_,13,0xffffdfff)
+#define SET_RG_EN_LDO_VCO_IQUP(_VAL_) SET_REG(ADR_SX_2_4G_LDO_REGISTER,_VAL_,14,0xffffbfff)
+#define SET_RG_SX_LDO_FCOFFT(_VAL_) SET_REG(ADR_SX_2_4G_LDO_REGISTER,_VAL_,19,0xffc7ffff)
+#define SET_RG_LDO_CP_FC_MAN(_VAL_) SET_REG(ADR_SX_2_4G_LDO_REGISTER,_VAL_,22,0xffbfffff)
+#define SET_RG_LDO_CP_FC(_VAL_) SET_REG(ADR_SX_2_4G_LDO_REGISTER,_VAL_,23,0xff7fffff)
+#define SET_RG_LDO_DIV_FC_MAN(_VAL_) SET_REG(ADR_SX_2_4G_LDO_REGISTER,_VAL_,24,0xfeffffff)
+#define SET_RG_LDO_DIV_FC(_VAL_) SET_REG(ADR_SX_2_4G_LDO_REGISTER,_VAL_,25,0xfdffffff)
+#define SET_RG_LDO_LO_FC_MAN(_VAL_) SET_REG(ADR_SX_2_4G_LDO_REGISTER,_VAL_,26,0xfbffffff)
+#define SET_RG_LDO_LO_FC(_VAL_) SET_REG(ADR_SX_2_4G_LDO_REGISTER,_VAL_,27,0xf7ffffff)
+#define SET_RG_LDO_VCO_FC_MAN(_VAL_) SET_REG(ADR_SX_2_4G_LDO_REGISTER,_VAL_,28,0xefffffff)
+#define SET_RG_LDO_VCO_FC(_VAL_) SET_REG(ADR_SX_2_4G_LDO_REGISTER,_VAL_,29,0xdfffffff)
+#define SET_RG_LDO_VCO_RCF(_VAL_) SET_REG(ADR_SX_2_4G_LDO_REGISTER,_VAL_,30,0x3fffffff)
+#define SET_RG_SX_RFCTRL_F(_VAL_) SET_REG(ADR_SX_2_4GB_FRACTIONAL_AND_INTEGER_8BITS,_VAL_,0,0xff000000)
+#define SET_RG_SX_RFCTRL_CH_7_0(_VAL_) SET_REG(ADR_SX_2_4GB_FRACTIONAL_AND_INTEGER_8BITS,_VAL_,24,0x00ffffff)
+#define SET_RG_SX_RFCTRL_CH_10_8(_VAL_) SET_REG(ADR_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE,_VAL_,0,0xfffffff8)
+#define SET_RG_SX_RFCH_MAP_EN(_VAL_) SET_REG(ADR_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE,_VAL_,3,0xfffffff7)
+#define SET_RG_SX_FREF_DOUB_MAN(_VAL_) SET_REG(ADR_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE,_VAL_,6,0xffffffbf)
+#define SET_RG_SX_FREF_DOUB(_VAL_) SET_REG(ADR_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE,_VAL_,7,0xffffff7f)
+#define SET_RG_SX_BTRX_SIDE(_VAL_) SET_REG(ADR_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE,_VAL_,8,0xfffffeff)
+#define SET_RG_SX_LO_TIMES(_VAL_) SET_REG(ADR_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE,_VAL_,9,0xfffffdff)
+#define SET_RG_SX_CHANNEL(_VAL_) SET_REG(ADR_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE,_VAL_,11,0xfff807ff)
+#define SET_RG_SX_XTAL_FREQ(_VAL_) SET_REG(ADR_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE,_VAL_,20,0xff0fffff)
+#define SET_RG_SX_CP_ISEL_BT(_VAL_) SET_REG(ADR_SX_2_4GB_PFD_CHP_,_VAL_,0,0xfffffff0)
+#define SET_RG_SX_CP_ISEL50U_BT(_VAL_) SET_REG(ADR_SX_2_4GB_PFD_CHP_,_VAL_,4,0xffffffef)
+#define SET_RG_SX_CP_KP_DOUB_BT(_VAL_) SET_REG(ADR_SX_2_4GB_PFD_CHP_,_VAL_,5,0xffffffdf)
+#define SET_RG_SX_CP_ISEL_WF(_VAL_) SET_REG(ADR_SX_2_4GB_PFD_CHP_,_VAL_,7,0xfffff87f)
+#define SET_RG_SX_CP_ISEL50U_WF(_VAL_) SET_REG(ADR_SX_2_4GB_PFD_CHP_,_VAL_,11,0xfffff7ff)
+#define SET_RG_SX_CP_KP_DOUB_WF(_VAL_) SET_REG(ADR_SX_2_4GB_PFD_CHP_,_VAL_,12,0xffffefff)
+#define SET_RG_SX_CP_IOST_POL(_VAL_) SET_REG(ADR_SX_2_4GB_PFD_CHP_,_VAL_,15,0xffff7fff)
+#define SET_RG_SX_CP_IOST(_VAL_) SET_REG(ADR_SX_2_4GB_PFD_CHP_,_VAL_,16,0xfff8ffff)
+#define SET_RG_SX_PFD_SEL(_VAL_) SET_REG(ADR_SX_2_4GB_PFD_CHP_,_VAL_,22,0xffbfffff)
+#define SET_RG_SX_PFD_SET(_VAL_) SET_REG(ADR_SX_2_4GB_PFD_CHP_,_VAL_,23,0xff7fffff)
+#define SET_RG_SX_PFD_SET1(_VAL_) SET_REG(ADR_SX_2_4GB_PFD_CHP_,_VAL_,24,0xfeffffff)
+#define SET_RG_SX_PFD_SET2(_VAL_) SET_REG(ADR_SX_2_4GB_PFD_CHP_,_VAL_,25,0xfdffffff)
+#define SET_RG_SX_PFD_REF_EDGE(_VAL_) SET_REG(ADR_SX_2_4GB_PFD_CHP_,_VAL_,26,0xfbffffff)
+#define SET_RG_SX_PFD_DIV_EDGE(_VAL_) SET_REG(ADR_SX_2_4GB_PFD_CHP_,_VAL_,27,0xf7ffffff)
+#define SET_RG_SX_PFD_TRUP(_VAL_) SET_REG(ADR_SX_2_4GB_PFD_CHP_,_VAL_,28,0xefffffff)
+#define SET_RG_SX_PFD_TRDN(_VAL_) SET_REG(ADR_SX_2_4GB_PFD_CHP_,_VAL_,29,0xdfffffff)
+#define SET_RG_SX_PFD_TLSEL(_VAL_) SET_REG(ADR_SX_2_4GB_PFD_CHP_,_VAL_,30,0xbfffffff)
+#define SET_RG_SX_LPF_C1_BT(_VAL_) SET_REG(ADR_SX_2_4GB_LPF,_VAL_,0,0xfffffff0)
+#define SET_RG_SX_LPF_C2_BT(_VAL_) SET_REG(ADR_SX_2_4GB_LPF,_VAL_,4,0xffffff0f)
+#define SET_RG_SX_LPF_C3_BT(_VAL_) SET_REG(ADR_SX_2_4GB_LPF,_VAL_,8,0xfffffeff)
+#define SET_RG_SX_LPF_R2_BT(_VAL_) SET_REG(ADR_SX_2_4GB_LPF,_VAL_,9,0xffffe1ff)
+#define SET_RG_SX_LPF_R3_BT(_VAL_) SET_REG(ADR_SX_2_4GB_LPF,_VAL_,13,0xffff1fff)
+#define SET_RG_SX_LPF_C1_WF(_VAL_) SET_REG(ADR_SX_2_4GB_LPF,_VAL_,16,0xfff0ffff)
+#define SET_RG_SX_LPF_C2_WF(_VAL_) SET_REG(ADR_SX_2_4GB_LPF,_VAL_,20,0xff0fffff)
+#define SET_RG_SX_LPF_C3_WF(_VAL_) SET_REG(ADR_SX_2_4GB_LPF,_VAL_,24,0xfeffffff)
+#define SET_RG_SX_LPF_R2_WF(_VAL_) SET_REG(ADR_SX_2_4GB_LPF,_VAL_,25,0xe1ffffff)
+#define SET_RG_SX_LPF_R3_WF(_VAL_) SET_REG(ADR_SX_2_4GB_LPF,_VAL_,29,0x1fffffff)
+#define SET_RG_SX_VCO_ISEL_MAN(_VAL_) SET_REG(ADR_SX_2_4GB_VCO,_VAL_,0,0xfffffffe)
+#define SET_RG_SX_VCO_ISEL_BT(_VAL_) SET_REG(ADR_SX_2_4GB_VCO,_VAL_,1,0xffffffe1)
+#define SET_RG_SX_VCO_LPM_BT(_VAL_) SET_REG(ADR_SX_2_4GB_VCO,_VAL_,5,0xffffffdf)
+#define SET_RG_SX_VCO_VCCBSEL_BT(_VAL_) SET_REG(ADR_SX_2_4GB_VCO,_VAL_,6,0xfffffe3f)
+#define SET_RG_SX_VCO_KVDOUB_BT(_VAL_) SET_REG(ADR_SX_2_4GB_VCO,_VAL_,9,0xfffffdff)
+#define SET_RG_SX_VCO_ISEL_WF(_VAL_) SET_REG(ADR_SX_2_4GB_VCO,_VAL_,10,0xffffc3ff)
+#define SET_RG_SX_VCO_LPM_WF(_VAL_) SET_REG(ADR_SX_2_4GB_VCO,_VAL_,14,0xffffbfff)
+#define SET_RG_SX_VCO_VCCBSEL_WF(_VAL_) SET_REG(ADR_SX_2_4GB_VCO,_VAL_,15,0xfffc7fff)
+#define SET_RG_SX_VCO_KVDOUB_WF(_VAL_) SET_REG(ADR_SX_2_4GB_VCO,_VAL_,18,0xfffbffff)
+#define SET_RG_SX_VCO_VARBSEL(_VAL_) SET_REG(ADR_SX_2_4GB_VCO,_VAL_,21,0xff9fffff)
+#define SET_RG_SX_VCO_RTAIL_SHIFT(_VAL_) SET_REG(ADR_SX_2_4GB_VCO,_VAL_,23,0xff7fffff)
+#define SET_RG_SX_VCO_CS_AWH(_VAL_) SET_REG(ADR_SX_2_4GB_VCO,_VAL_,24,0xfeffffff)
+#define SET_RG_VOBF_TXMBSEL_BT(_VAL_) SET_REG(ADR_SX_2_4GB_VCOBF,_VAL_,0,0xfffffffc)
+#define SET_RG_VOBF_TXOBSEL_BT(_VAL_) SET_REG(ADR_SX_2_4GB_VCOBF,_VAL_,2,0xfffffff3)
+#define SET_RG_VOBF_RXMBSEL_BT(_VAL_) SET_REG(ADR_SX_2_4GB_VCOBF,_VAL_,4,0xffffffcf)
+#define SET_RG_VOBF_RXOBSEL_BT(_VAL_) SET_REG(ADR_SX_2_4GB_VCOBF,_VAL_,6,0xffffff3f)
+#define SET_RG_VOBF_TXMBSEL_WF(_VAL_) SET_REG(ADR_SX_2_4GB_VCOBF,_VAL_,10,0xfffff3ff)
+#define SET_RG_VOBF_TXOBSEL_WF(_VAL_) SET_REG(ADR_SX_2_4GB_VCOBF,_VAL_,12,0xffffcfff)
+#define SET_RG_VOBF_RXMBSEL_WF(_VAL_) SET_REG(ADR_SX_2_4GB_VCOBF,_VAL_,14,0xffff3fff)
+#define SET_RG_VOBF_RXOBSEL_WF(_VAL_) SET_REG(ADR_SX_2_4GB_VCOBF,_VAL_,16,0xfffcffff)
+#define SET_RG_VOBF_DIVBFSEL(_VAL_) SET_REG(ADR_SX_2_4GB_VCOBF,_VAL_,19,0xfff7ffff)
+#define SET_RG_SX_VCO_TXOB_AW(_VAL_) SET_REG(ADR_SX_2_4GB_VCOBF,_VAL_,20,0xffefffff)
+#define SET_RG_SX_VCO_RXOB_AW(_VAL_) SET_REG(ADR_SX_2_4GB_VCOBF,_VAL_,21,0xffdfffff)
+#define SET_RG_VOBF_CAPIMB_POL(_VAL_) SET_REG(ADR_SX_2_4GB_VCOBF,_VAL_,26,0xfbffffff)
+#define SET_RG_VOBF_CAPIMB(_VAL_) SET_REG(ADR_SX_2_4GB_VCOBF,_VAL_,27,0xc7ffffff)
+#define SET_RG_EN_SX_VCOMON(_VAL_) SET_REG(ADR_SX_2_4GB_VCOBF,_VAL_,31,0x7fffffff)
+#define SET_RG_SX_DIV_PREVDD(_VAL_) SET_REG(ADR_SX_2_4GB_DIV_SDM,_VAL_,0,0xfffffff0)
+#define SET_RG_SX_DIV_PSCVDD(_VAL_) SET_REG(ADR_SX_2_4GB_DIV_SDM,_VAL_,4,0xffffff0f)
+#define SET_RG_SX_DIV_RST_H(_VAL_) SET_REG(ADR_SX_2_4GB_DIV_SDM,_VAL_,9,0xfffffdff)
+#define SET_RG_SX_DIV_SDM_EDGE(_VAL_) SET_REG(ADR_SX_2_4GB_DIV_SDM,_VAL_,10,0xfffffbff)
+#define SET_RG_SX_DIV_DMYBUF_EN(_VAL_) SET_REG(ADR_SX_2_4GB_DIV_SDM,_VAL_,11,0xfffff7ff)
+#define SET_RG_EN_SX_MOD(_VAL_) SET_REG(ADR_SX_2_4GB_DIV_SDM,_VAL_,17,0xfffdffff)
+#define SET_RG_EN_SX_DITHER(_VAL_) SET_REG(ADR_SX_2_4GB_DIV_SDM,_VAL_,18,0xfffbffff)
+#define SET_RG_SX_MOD_ORDER(_VAL_) SET_REG(ADR_SX_2_4GB_DIV_SDM,_VAL_,19,0xffe7ffff)
+#define SET_RG_SX_DITHER_WEIGHT(_VAL_) SET_REG(ADR_SX_2_4GB_DIV_SDM,_VAL_,21,0xff9fffff)
+#define SET_RG_SX_SUB_SEL_MAN(_VAL_) SET_REG(ADR_SX_2_4GB_SBCAL,_VAL_,0,0xfffffffe)
+#define SET_RG_SX_SUB_SEL(_VAL_) SET_REG(ADR_SX_2_4GB_SBCAL,_VAL_,1,0xfffffe01)
+#define SET_RG_SX_SUB_C0P5_DIS(_VAL_) SET_REG(ADR_SX_2_4GB_SBCAL,_VAL_,9,0xfffffdff)
+#define SET_RG_SX_SBCAL_CT(_VAL_) SET_REG(ADR_SX_2_4GB_SBCAL,_VAL_,10,0xfffff3ff)
+#define SET_RG_SX_SBCAL_WT(_VAL_) SET_REG(ADR_SX_2_4GB_SBCAL,_VAL_,12,0xffffefff)
+#define SET_RG_SX_SBCAL_DIFFMIN(_VAL_) SET_REG(ADR_SX_2_4GB_SBCAL,_VAL_,13,0xffffdfff)
+#define SET_RG_SX_SBCAL_NTARG_MAN(_VAL_) SET_REG(ADR_SX_2_4GB_SBCAL,_VAL_,15,0xffff7fff)
+#define SET_RG_SX_SBCAL_NTARG(_VAL_) SET_REG(ADR_SX_2_4GB_SBCAL,_VAL_,16,0x0000ffff)
+#define SET_RG_VO_AAC_TAR_BT(_VAL_) SET_REG(ADR_SX_2_4GB_AAC,_VAL_,0,0xfffffff0)
+#define SET_RG_VO_AAC_IOST_BT(_VAL_) SET_REG(ADR_SX_2_4GB_AAC,_VAL_,4,0xffffffcf)
+#define SET_RG_VO_AAC_TAR_WF(_VAL_) SET_REG(ADR_SX_2_4GB_AAC,_VAL_,7,0xfffff87f)
+#define SET_RG_VO_AAC_IOST_WF(_VAL_) SET_REG(ADR_SX_2_4GB_AAC,_VAL_,11,0xffffe7ff)
+#define SET_RG_VO_AAC_IMAX(_VAL_) SET_REG(ADR_SX_2_4GB_AAC,_VAL_,14,0xfffc3fff)
+#define SET_RG_VO_AAC_INIT(_VAL_) SET_REG(ADR_SX_2_4GB_AAC,_VAL_,18,0xfff3ffff)
+#define SET_RG_VO_AAC_EVA_TS(_VAL_) SET_REG(ADR_SX_2_4GB_AAC,_VAL_,20,0xffcfffff)
+#define SET_RG_VO_AAC_EN_MAN(_VAL_) SET_REG(ADR_SX_2_4GB_AAC,_VAL_,23,0xff7fffff)
+#define SET_RG_VO_AAC_EN(_VAL_) SET_REG(ADR_SX_2_4GB_AAC,_VAL_,24,0xfeffffff)
+#define SET_RG_VO_AAC_EVA_MAN(_VAL_) SET_REG(ADR_SX_2_4GB_AAC,_VAL_,25,0xfdffffff)
+#define SET_RG_VO_AAC_EVA(_VAL_) SET_REG(ADR_SX_2_4GB_AAC,_VAL_,26,0xfbffffff)
+#define SET_RG_VO_AAC_TEST_EN(_VAL_) SET_REG(ADR_SX_2_4GB_AAC,_VAL_,28,0xefffffff)
+#define SET_RG_VO_AAC_TEST_SEL(_VAL_) SET_REG(ADR_SX_2_4GB_AAC,_VAL_,29,0xdfffffff)
+#define SET_RG_SX_TTL_INIT(_VAL_) SET_REG(ADR_SX_2_4GB_TTL,_VAL_,0,0xfffffffc)
+#define SET_RG_SX_TTL_FPT(_VAL_) SET_REG(ADR_SX_2_4GB_TTL,_VAL_,2,0xfffffff3)
+#define SET_RG_SX_TTL_CPT(_VAL_) SET_REG(ADR_SX_2_4GB_TTL,_VAL_,4,0xffffffcf)
+#define SET_RG_SX_TTL_ACCUM(_VAL_) SET_REG(ADR_SX_2_4GB_TTL,_VAL_,7,0xfffffe7f)
+#define SET_RG_SX_TTL_SUB(_VAL_) SET_REG(ADR_SX_2_4GB_TTL,_VAL_,10,0xfffff3ff)
+#define SET_RG_SX_TTL_SUB_INV(_VAL_) SET_REG(ADR_SX_2_4GB_TTL,_VAL_,12,0xffffefff)
+#define SET_RG_SX_TTL_VH(_VAL_) SET_REG(ADR_SX_2_4GB_TTL,_VAL_,14,0xffff3fff)
+#define SET_RG_SX_TTL_VL(_VAL_) SET_REG(ADR_SX_2_4GB_TTL,_VAL_,16,0xfffcffff)
+#define SET_RG_SX_LPF_VTUNE_TEST(_VAL_) SET_REG(ADR_SX_2_4GB_TTL,_VAL_,19,0xfff7ffff)
+#define SET_DPLL_TOP_REGISTER(_VAL_) SET_REG(ADR_DPLL_TOP_REGISTER,_VAL_,0,0x00000000)
+#define SET_DPLL_CKT_REGISTER(_VAL_) SET_REG(ADR_DPLL_CKT_REGISTER,_VAL_,0,0x00000000)
+#define SET_DPLL_FB_DIVISION__REGISTERS(_VAL_) SET_REG(ADR_DPLL_FB_DIVISION__REGISTERS,_VAL_,0,0x00000000)
+#define SET_RG_WF_IDACAI_TZ0_PGAG15(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER1,_VAL_,0,0xffffffc0)
+#define SET_RG_WF_IDACAQ_TZ0_PGAG15(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER1,_VAL_,8,0xffffc0ff)
+#define SET_RG_WF_IDACAI_TZ0_PGAG14(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER1,_VAL_,16,0xffc0ffff)
+#define SET_RG_WF_IDACAQ_TZ0_PGAG14(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER1,_VAL_,24,0xc0ffffff)
+#define SET_RG_WF_IDACAI_TZ0_PGAG13(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER2,_VAL_,0,0xffffffc0)
+#define SET_RG_WF_IDACAQ_TZ0_PGAG13(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER2,_VAL_,8,0xffffc0ff)
+#define SET_RG_WF_IDACAI_TZ0_PGAG12(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER2,_VAL_,16,0xffc0ffff)
+#define SET_RG_WF_IDACAQ_TZ0_PGAG12(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER2,_VAL_,24,0xc0ffffff)
+#define SET_RG_WF_IDACAI_TZ0_PGAG11(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER3,_VAL_,0,0xffffffc0)
+#define SET_RG_WF_IDACAQ_TZ0_PGAG11(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER3,_VAL_,8,0xffffc0ff)
+#define SET_RG_WF_IDACAI_TZ0_PGAG10(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER3,_VAL_,16,0xffc0ffff)
+#define SET_RG_WF_IDACAQ_TZ0_PGAG10(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER3,_VAL_,24,0xc0ffffff)
+#define SET_RG_WF_IDACAI_TZ0_PGAG9(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER4,_VAL_,0,0xffffffc0)
+#define SET_RG_WF_IDACAQ_TZ0_PGAG9(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER4,_VAL_,8,0xffffc0ff)
+#define SET_RG_WF_IDACAI_TZ0_PGAG8(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER4,_VAL_,16,0xffc0ffff)
+#define SET_RG_WF_IDACAQ_TZ0_PGAG8(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER4,_VAL_,24,0xc0ffffff)
+#define SET_RG_WF_IDACAI_TZ0_PGAG7(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER5,_VAL_,0,0xffffffc0)
+#define SET_RG_WF_IDACAQ_TZ0_PGAG7(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER5,_VAL_,8,0xffffc0ff)
+#define SET_RG_WF_IDACAI_TZ0_PGAG6(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER5,_VAL_,16,0xffc0ffff)
+#define SET_RG_WF_IDACAQ_TZ0_PGAG6(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER5,_VAL_,24,0xc0ffffff)
+#define SET_RG_WF_IDACAI_TZ0_PGAG5(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER6,_VAL_,0,0xffffffc0)
+#define SET_RG_WF_IDACAQ_TZ0_PGAG5(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER6,_VAL_,8,0xffffc0ff)
+#define SET_RG_WF_IDACAI_TZ0_PGAG4(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER6,_VAL_,16,0xffc0ffff)
+#define SET_RG_WF_IDACAQ_TZ0_PGAG4(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER6,_VAL_,24,0xc0ffffff)
+#define SET_RG_WF_IDACAI_TZ0_PGAG3(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER7,_VAL_,0,0xffffffc0)
+#define SET_RG_WF_IDACAQ_TZ0_PGAG3(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER7,_VAL_,8,0xffffc0ff)
+#define SET_RG_WF_IDACAI_TZ0_PGAG2(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER7,_VAL_,16,0xffc0ffff)
+#define SET_RG_WF_IDACAQ_TZ0_PGAG2(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER7,_VAL_,24,0xc0ffffff)
+#define SET_RG_WF_IDACAI_TZ0_PGAG1(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER8,_VAL_,0,0xffffffc0)
+#define SET_RG_WF_IDACAQ_TZ0_PGAG1(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER8,_VAL_,8,0xffffc0ff)
+#define SET_RG_WF_IDACAI_TZ0_PGAG0(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER8,_VAL_,16,0xffc0ffff)
+#define SET_RG_WF_IDACAQ_TZ0_PGAG0(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER8,_VAL_,24,0xc0ffffff)
+#define SET_RG_WF_IDACAI_TZ1_PGAG15(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER9,_VAL_,0,0xffffffc0)
+#define SET_RG_WF_IDACAQ_TZ1_PGAG15(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER9,_VAL_,8,0xffffc0ff)
+#define SET_RG_WF_IDACAI_TZ1_PGAG14(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER9,_VAL_,16,0xffc0ffff)
+#define SET_RG_WF_IDACAQ_TZ1_PGAG14(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER9,_VAL_,24,0xc0ffffff)
+#define SET_RG_WF_IDACAI_TZ1_PGAG13(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER10,_VAL_,0,0xffffffc0)
+#define SET_RG_WF_IDACAQ_TZ1_PGAG13(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER10,_VAL_,8,0xffffc0ff)
+#define SET_RG_WF_IDACAI_TZ1_PGAG12(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER10,_VAL_,16,0xffc0ffff)
+#define SET_RG_WF_IDACAQ_TZ1_PGAG12(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER10,_VAL_,24,0xc0ffffff)
+#define SET_RG_WF_IDACAI_TZ1_PGAG11(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER11,_VAL_,0,0xffffffc0)
+#define SET_RG_WF_IDACAQ_TZ1_PGAG11(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER11,_VAL_,8,0xffffc0ff)
+#define SET_RG_WF_IDACAI_TZ1_PGAG10(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER11,_VAL_,16,0xffc0ffff)
+#define SET_RG_WF_IDACAQ_TZ1_PGAG10(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER11,_VAL_,24,0xc0ffffff)
+#define SET_RG_WF_IDACAI_TZ1_PGAG9(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER12,_VAL_,0,0xffffffc0)
+#define SET_RG_WF_IDACAQ_TZ1_PGAG9(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER12,_VAL_,8,0xffffc0ff)
+#define SET_RG_WF_IDACAI_TZ1_PGAG8(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER12,_VAL_,16,0xffc0ffff)
+#define SET_RG_WF_IDACAQ_TZ1_PGAG8(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER12,_VAL_,24,0xc0ffffff)
+#define SET_RG_WF_IDACAI_TZ1_PGAG7(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER13,_VAL_,0,0xffffffc0)
+#define SET_RG_WF_IDACAQ_TZ1_PGAG7(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER13,_VAL_,8,0xffffc0ff)
+#define SET_RG_WF_IDACAI_TZ1_PGAG6(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER13,_VAL_,16,0xffc0ffff)
+#define SET_RG_WF_IDACAQ_TZ1_PGAG6(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER13,_VAL_,24,0xc0ffffff)
+#define SET_RG_WF_IDACAI_TZ1_PGAG5(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER14,_VAL_,0,0xffffffc0)
+#define SET_RG_WF_IDACAQ_TZ1_PGAG5(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER14,_VAL_,8,0xffffc0ff)
+#define SET_RG_WF_IDACAI_TZ1_PGAG4(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER14,_VAL_,16,0xffc0ffff)
+#define SET_RG_WF_IDACAQ_TZ1_PGAG4(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER14,_VAL_,24,0xc0ffffff)
+#define SET_RG_WF_IDACAI_TZ1_PGAG3(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER15,_VAL_,0,0xffffffc0)
+#define SET_RG_WF_IDACAQ_TZ1_PGAG3(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER15,_VAL_,8,0xffffc0ff)
+#define SET_RG_WF_IDACAI_TZ1_PGAG2(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER15,_VAL_,16,0xffc0ffff)
+#define SET_RG_WF_IDACAQ_TZ1_PGAG2(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER15,_VAL_,24,0xc0ffffff)
+#define SET_RG_WF_IDACAI_TZ1_PGAG1(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER16,_VAL_,0,0xffffffc0)
+#define SET_RG_WF_IDACAQ_TZ1_PGAG1(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER16,_VAL_,8,0xffffc0ff)
+#define SET_RG_WF_IDACAI_TZ1_PGAG0(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER16,_VAL_,16,0xffc0ffff)
+#define SET_RG_WF_IDACAQ_TZ1_PGAG0(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER16,_VAL_,24,0xc0ffffff)
+#define SET_RG_IDACAI_TZ0_COARSE4(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER17,_VAL_,0,0xffffffc0)
+#define SET_RG_IDACAQ_TZ0_COARSE4(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER17,_VAL_,8,0xffffc0ff)
+#define SET_RG_IDACAI_TZ0_COARSE3(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER17,_VAL_,16,0xffc0ffff)
+#define SET_RG_IDACAQ_TZ0_COARSE3(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER17,_VAL_,24,0xc0ffffff)
+#define SET_RG_IDACAI_TZ0_COARSE2(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER18,_VAL_,0,0xffffffc0)
+#define SET_RG_IDACAQ_TZ0_COARSE2(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER18,_VAL_,8,0xffffc0ff)
+#define SET_RG_IDACAI_TZ0_COARSE1(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER18,_VAL_,16,0xffc0ffff)
+#define SET_RG_IDACAQ_TZ0_COARSE1(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER18,_VAL_,24,0xc0ffffff)
+#define SET_RG_IDACAI_TZ0_COARSE0(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER19,_VAL_,0,0xffffffc0)
+#define SET_RG_IDACAQ_TZ0_COARSE0(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER19,_VAL_,8,0xffffc0ff)
+#define SET_RG_IDACAI_TZ1_COARSE4(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER19,_VAL_,16,0xffc0ffff)
+#define SET_RG_IDACAQ_TZ1_COARSE4(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER19,_VAL_,24,0xc0ffffff)
+#define SET_RG_IDACAI_TZ1_COARSE3(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER20,_VAL_,0,0xffffffc0)
+#define SET_RG_IDACAQ_TZ1_COARSE3(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER20,_VAL_,8,0xffffc0ff)
+#define SET_RG_IDACAI_TZ1_COARSE2(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER20,_VAL_,16,0xffc0ffff)
+#define SET_RG_IDACAQ_TZ1_COARSE2(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER20,_VAL_,24,0xc0ffffff)
+#define SET_RG_IDACAI_TZ1_COARSE1(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER21,_VAL_,0,0xffffffc0)
+#define SET_RG_IDACAQ_TZ1_COARSE1(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER21,_VAL_,8,0xffffc0ff)
+#define SET_RG_IDACAI_TZ1_COARSE0(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER21,_VAL_,16,0xffc0ffff)
+#define SET_RG_IDACAQ_TZ1_COARSE0(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER21,_VAL_,24,0xc0ffffff)
+#define SET_RG_BT_IDACAI_TZ0_PGAG15(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER1,_VAL_,0,0xffffffc0)
+#define SET_RG_BT_IDACAQ_TZ0_PGAG15(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER1,_VAL_,8,0xffffc0ff)
+#define SET_RG_BT_IDACAI_TZ0_PGAG14(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER1,_VAL_,16,0xffc0ffff)
+#define SET_RG_BT_IDACAQ_TZ0_PGAG14(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER1,_VAL_,24,0xc0ffffff)
+#define SET_RG_BT_IDACAI_TZ0_PGAG13(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER2,_VAL_,0,0xffffffc0)
+#define SET_RG_BT_IDACAQ_TZ0_PGAG13(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER2,_VAL_,8,0xffffc0ff)
+#define SET_RG_BT_IDACAI_TZ0_PGAG12(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER2,_VAL_,16,0xffc0ffff)
+#define SET_RG_BT_IDACAQ_TZ0_PGAG12(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER2,_VAL_,24,0xc0ffffff)
+#define SET_RG_BT_IDACAI_TZ0_PGAG11(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER3,_VAL_,0,0xffffffc0)
+#define SET_RG_BT_IDACAQ_TZ0_PGAG11(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER3,_VAL_,8,0xffffc0ff)
+#define SET_RG_BT_IDACAI_TZ0_PGAG10(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER3,_VAL_,16,0xffc0ffff)
+#define SET_RG_BT_IDACAQ_TZ0_PGAG10(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER3,_VAL_,24,0xc0ffffff)
+#define SET_RG_BT_IDACAI_TZ0_PGAG9(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER4,_VAL_,0,0xffffffc0)
+#define SET_RG_BT_IDACAQ_TZ0_PGAG9(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER4,_VAL_,8,0xffffc0ff)
+#define SET_RG_BT_IDACAI_TZ0_PGAG8(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER4,_VAL_,16,0xffc0ffff)
+#define SET_RG_BT_IDACAQ_TZ0_PGAG8(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER4,_VAL_,24,0xc0ffffff)
+#define SET_RG_BT_IDACAI_TZ0_PGAG7(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER5,_VAL_,0,0xffffffc0)
+#define SET_RG_BT_IDACAQ_TZ0_PGAG7(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER5,_VAL_,8,0xffffc0ff)
+#define SET_RG_BT_IDACAI_TZ0_PGAG6(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER5,_VAL_,16,0xffc0ffff)
+#define SET_RG_BT_IDACAQ_TZ0_PGAG6(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER5,_VAL_,24,0xc0ffffff)
+#define SET_RG_BT_IDACAI_TZ0_PGAG5(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER6,_VAL_,0,0xffffffc0)
+#define SET_RG_BT_IDACAQ_TZ0_PGAG5(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER6,_VAL_,8,0xffffc0ff)
+#define SET_RG_BT_IDACAI_TZ0_PGAG4(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER6,_VAL_,16,0xffc0ffff)
+#define SET_RG_BT_IDACAQ_TZ0_PGAG4(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER6,_VAL_,24,0xc0ffffff)
+#define SET_RG_BT_IDACAI_TZ0_PGAG3(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER7,_VAL_,0,0xffffffc0)
+#define SET_RG_BT_IDACAQ_TZ0_PGAG3(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER7,_VAL_,8,0xffffc0ff)
+#define SET_RG_BT_IDACAI_TZ0_PGAG2(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER7,_VAL_,16,0xffc0ffff)
+#define SET_RG_BT_IDACAQ_TZ0_PGAG2(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER7,_VAL_,24,0xc0ffffff)
+#define SET_RG_BT_IDACAI_TZ0_PGAG1(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER8,_VAL_,0,0xffffffc0)
+#define SET_RG_BT_IDACAQ_TZ0_PGAG1(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER8,_VAL_,8,0xffffc0ff)
+#define SET_RG_BT_IDACAI_TZ0_PGAG0(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER8,_VAL_,16,0xffc0ffff)
+#define SET_RG_BT_IDACAQ_TZ0_PGAG0(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER8,_VAL_,24,0xc0ffffff)
+#define SET_RG_BT_IDACAI_TZ1_PGAG15(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER9,_VAL_,0,0xffffffc0)
+#define SET_RG_BT_IDACAQ_TZ1_PGAG15(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER9,_VAL_,8,0xffffc0ff)
+#define SET_RG_BT_IDACAI_TZ1_PGAG14(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER9,_VAL_,16,0xffc0ffff)
+#define SET_RG_BT_IDACAQ_TZ1_PGAG14(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER9,_VAL_,24,0xc0ffffff)
+#define SET_RG_BT_IDACAI_TZ1_PGAG13(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER10,_VAL_,0,0xffffffc0)
+#define SET_RG_BT_IDACAQ_TZ1_PGAG13(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER10,_VAL_,8,0xffffc0ff)
+#define SET_RG_BT_IDACAI_TZ1_PGAG12(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER10,_VAL_,16,0xffc0ffff)
+#define SET_RG_BT_IDACAQ_TZ1_PGAG12(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER10,_VAL_,24,0xc0ffffff)
+#define SET_RG_BT_IDACAI_TZ1_PGAG11(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER11,_VAL_,0,0xffffffc0)
+#define SET_RG_BT_IDACAQ_TZ1_PGAG11(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER11,_VAL_,8,0xffffc0ff)
+#define SET_RG_BT_IDACAI_TZ1_PGAG10(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER11,_VAL_,16,0xffc0ffff)
+#define SET_RG_BT_IDACAQ_TZ1_PGAG10(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER11,_VAL_,24,0xc0ffffff)
+#define SET_RG_BT_IDACAI_TZ1_PGAG9(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER12,_VAL_,0,0xffffffc0)
+#define SET_RG_BT_IDACAQ_TZ1_PGAG9(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER12,_VAL_,8,0xffffc0ff)
+#define SET_RG_BT_IDACAI_TZ1_PGAG8(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER12,_VAL_,16,0xffc0ffff)
+#define SET_RG_BT_IDACAQ_TZ1_PGAG8(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER12,_VAL_,24,0xc0ffffff)
+#define SET_RG_BT_IDACAI_TZ1_PGAG7(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER13,_VAL_,0,0xffffffc0)
+#define SET_RG_BT_IDACAQ_TZ1_PGAG7(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER13,_VAL_,8,0xffffc0ff)
+#define SET_RG_BT_IDACAI_TZ1_PGAG6(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER13,_VAL_,16,0xffc0ffff)
+#define SET_RG_BT_IDACAQ_TZ1_PGAG6(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER13,_VAL_,24,0xc0ffffff)
+#define SET_RG_BT_IDACAI_TZ1_PGAG5(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER14,_VAL_,0,0xffffffc0)
+#define SET_RG_BT_IDACAQ_TZ1_PGAG5(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER14,_VAL_,8,0xffffc0ff)
+#define SET_RG_BT_IDACAI_TZ1_PGAG4(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER14,_VAL_,16,0xffc0ffff)
+#define SET_RG_BT_IDACAQ_TZ1_PGAG4(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER14,_VAL_,24,0xc0ffffff)
+#define SET_RG_BT_IDACAI_TZ1_PGAG3(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER15,_VAL_,0,0xffffffc0)
+#define SET_RG_BT_IDACAQ_TZ1_PGAG3(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER15,_VAL_,8,0xffffc0ff)
+#define SET_RG_BT_IDACAI_TZ1_PGAG2(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER15,_VAL_,16,0xffc0ffff)
+#define SET_RG_BT_IDACAQ_TZ1_PGAG2(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER15,_VAL_,24,0xc0ffffff)
+#define SET_RG_BT_IDACAI_TZ1_PGAG1(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER16,_VAL_,0,0xffffffc0)
+#define SET_RG_BT_IDACAQ_TZ1_PGAG1(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER16,_VAL_,8,0xffffc0ff)
+#define SET_RG_BT_IDACAI_TZ1_PGAG0(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER16,_VAL_,16,0xffc0ffff)
+#define SET_RG_BT_IDACAQ_TZ1_PGAG0(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER16,_VAL_,24,0xc0ffffff)
+#define SET_RG_SX_DELAY(_VAL_) SET_REG(ADR_MODE_DECODER_TIMER_REGISTER1,_VAL_,0,0xfffffff0)
+#define SET_RG_TXDAC_DELAY(_VAL_) SET_REG(ADR_MODE_DECODER_TIMER_REGISTER1,_VAL_,4,0xffffff0f)
+#define SET_RG_TXRF_DELAY(_VAL_) SET_REG(ADR_MODE_DECODER_TIMER_REGISTER1,_VAL_,8,0xfffff0ff)
+#define SET_RG_TXPA_DELAY(_VAL_) SET_REG(ADR_MODE_DECODER_TIMER_REGISTER1,_VAL_,12,0xffff0fff)
+#define SET_RG_RXRF_DELAY(_VAL_) SET_REG(ADR_MODE_DECODER_TIMER_REGISTER1,_VAL_,16,0xfff0ffff)
+#define SET_RG_TXBTPA_DELAY(_VAL_) SET_REG(ADR_MODE_DECODER_TIMER_REGISTER1,_VAL_,20,0xff0fffff)
+#define SET_RG_TXDAC_T2R_DELAY(_VAL_) SET_REG(ADR_WIFI_T2R_TIMER_REGISTER,_VAL_,0,0xffffffe0)
+#define SET_RG_TXRF_T2R_DELAY(_VAL_) SET_REG(ADR_WIFI_T2R_TIMER_REGISTER,_VAL_,8,0xffffe0ff)
+#define SET_RG_TXPA_T2R_DELAY(_VAL_) SET_REG(ADR_WIFI_T2R_TIMER_REGISTER,_VAL_,16,0xffe0ffff)
+#define SET_RG_RXRF_T2R_DELAY(_VAL_) SET_REG(ADR_WIFI_T2R_TIMER_REGISTER,_VAL_,24,0xe0ffffff)
+#define SET_RG_TXDAC_R2T_DELAY(_VAL_) SET_REG(ADR_WIFI_R2T_TIMER_REGISTER,_VAL_,0,0xffffffe0)
+#define SET_RG_TXRF_R2T_DELAY(_VAL_) SET_REG(ADR_WIFI_R2T_TIMER_REGISTER,_VAL_,8,0xffffe0ff)
+#define SET_RG_TXPA_R2T_DELAY(_VAL_) SET_REG(ADR_WIFI_R2T_TIMER_REGISTER,_VAL_,16,0xffe0ffff)
+#define SET_RG_RXRF_R2T_DELAY(_VAL_) SET_REG(ADR_WIFI_R2T_TIMER_REGISTER,_VAL_,24,0xe0ffffff)
+#define SET_RG_WF_RX_DCCAL_DELAY(_VAL_) SET_REG(ADR_CALIBRATION_TIMER_REGISTER,_VAL_,0,0xfffffff8)
+#define SET_RG_BT_RX_DCCAL_DELAY(_VAL_) SET_REG(ADR_CALIBRATION_TIMER_REGISTER,_VAL_,4,0xffffff8f)
+#define SET_RG_RX_RCCAL_DELAY(_VAL_) SET_REG(ADR_CALIBRATION_TIMER_REGISTER,_VAL_,8,0xfffff8ff)
+#define SET_RG_TX_DCCAL_DELAY(_VAL_) SET_REG(ADR_CALIBRATION_TIMER_REGISTER,_VAL_,12,0xffff8fff)
+#define SET_RG_TX_IQCAL_DELAY(_VAL_) SET_REG(ADR_CALIBRATION_TIMER_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_RX_IQCAL_DELAY(_VAL_) SET_REG(ADR_CALIBRATION_TIMER_REGISTER,_VAL_,20,0xff8fffff)
+#define SET_RG_RX_N_RCCAL_DELAY(_VAL_) SET_REG(ADR_CALIBRATION_TIMER_REGISTER,_VAL_,24,0xf8ffffff)
+#define SET_RG_PGAG_RCCAL(_VAL_) SET_REG(ADR_CALIBRATION_GAIN_REGISTER0,_VAL_,0,0xfffffff0)
+#define SET_RG_PGAG_TXCAL(_VAL_) SET_REG(ADR_CALIBRATION_GAIN_REGISTER0,_VAL_,4,0xffffff0f)
+#define SET_RG_TX_GAIN_TXCAL(_VAL_) SET_REG(ADR_CALIBRATION_GAIN_REGISTER0,_VAL_,8,0xffff80ff)
+#define SET_RG_RFG_RXIQCAL(_VAL_) SET_REG(ADR_CALIBRATION_GAIN_REGISTER0,_VAL_,16,0xfffcffff)
+#define SET_RG_PGAG_RXIQCAL(_VAL_) SET_REG(ADR_CALIBRATION_GAIN_REGISTER0,_VAL_,18,0xffc3ffff)
+#define SET_RG_TX_GAIN_RXIQCAL(_VAL_) SET_REG(ADR_CALIBRATION_GAIN_REGISTER0,_VAL_,22,0xe03fffff)
+#define SET_RG_RFG_DPDCAL(_VAL_) SET_REG(ADR_CALIBRATION_GAIN_REGISTER1,_VAL_,0,0xfffffffc)
+#define SET_RG_PGAG_DPDCAL(_VAL_) SET_REG(ADR_CALIBRATION_GAIN_REGISTER1,_VAL_,2,0xffffffc3)
+#define SET_RG_TX_GAIN_DPDCAL(_VAL_) SET_REG(ADR_CALIBRATION_GAIN_REGISTER1,_VAL_,6,0xffffe03f)
+#define SET_RG_IOT_ADC_CLKSEL(_VAL_) SET_REG(ADR_CALIBRATION_GAIN_REGISTER1,_VAL_,16,0xfffeffff)
+#define SET_RG_IOT_ADC_DNLEN(_VAL_) SET_REG(ADR_CALIBRATION_GAIN_REGISTER1,_VAL_,17,0xfffdffff)
+#define SET_RG_IOT_ADC_METAEN(_VAL_) SET_REG(ADR_CALIBRATION_GAIN_REGISTER1,_VAL_,18,0xfffbffff)
+#define SET_RG_IOT_ADC_TFLAG(_VAL_) SET_REG(ADR_CALIBRATION_GAIN_REGISTER1,_VAL_,19,0xfff7ffff)
+#define SET_RG_IOT_ADC_ICMP(_VAL_) SET_REG(ADR_CALIBRATION_GAIN_REGISTER1,_VAL_,20,0xffcfffff)
+#define SET_RG_IOT_ADC_VCMI(_VAL_) SET_REG(ADR_CALIBRATION_GAIN_REGISTER1,_VAL_,22,0xff3fffff)
+#define SET_RG_IOT_ADC_CLOAD(_VAL_) SET_REG(ADR_CALIBRATION_GAIN_REGISTER1,_VAL_,24,0xfcffffff)
+#define SET_RG_IOT_ADC_CLK_DIV(_VAL_) SET_REG(ADR_CALIBRATION_GAIN_REGISTER1,_VAL_,26,0xf3ffffff)
+#define SET_RG_IOT_ADC_CLK_SH_DUTY(_VAL_) SET_REG(ADR_CALIBRATION_GAIN_REGISTER1,_VAL_,28,0xefffffff)
+#define SET_RG_IOT_ADC_VSEN_SEL(_VAL_) SET_REG(ADR_CALIBRATION_GAIN_REGISTER1,_VAL_,29,0x9fffffff)
+#define SET_DB_AD_ADC_I_OUT(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_ADC,_VAL_,0,0xfffffc00)
+#define SET_DB_AD_ADC_Q_OUT(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_ADC,_VAL_,10,0xfff003ff)
+#define SET_DB_AD_RX_RSSIADC(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_ADC,_VAL_,20,0xff0fffff)
+#define SET_DB_DA_SARADC_BIT(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_ADC,_VAL_,24,0xc0ffffff)
+#define SET_SAR_ADC_FSM_RDY(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_ADC,_VAL_,30,0xbfffffff)
+#define SET_DB_DA_SX_SUB_SEL(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_SX_2_4GB_1,_VAL_,0,0xffffff00)
+#define SET_DB_DA_SX_VCO_ISEL(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_SX_2_4GB_1,_VAL_,8,0xfffff0ff)
+#define SET_DB_VO_AAC_COMPOUT(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_SX_2_4GB_1,_VAL_,12,0xffffefff)
+#define SET_DB_SX_TTL_VT_DET(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_SX_2_4GB_1,_VAL_,14,0xffff3fff)
+#define SET_DB_AD_DP_VT_MON_Q(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_SX_2_4GB_1,_VAL_,16,0xfffcffff)
+#define SET_DB_AD_IOT_ADC_OUT(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_SX_2_4GB_1,_VAL_,20,0xc00fffff)
+#define SET_DB_SX_SBCAL_NCOUNT(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_SX_2_4GB_2,_VAL_,0,0xffff0000)
+#define SET_DB_SX_SBCAL_NTARGET(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_SX_2_4GB_2,_VAL_,16,0x0000ffff)
+#define SET_RG_5G_TX_TRSW_MANUAL(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,0,0xfffffffe)
+#define SET_RG_5G_EN_TX_TRSW(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,1,0xfffffffd)
+#define SET_RG_5G_RX_LNA_MANUAL(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,2,0xfffffffb)
+#define SET_RG_5G_EN_RX_LNA(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,3,0xfffffff7)
+#define SET_RG_5G_RX_MIXER_MANUAL(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,4,0xffffffef)
+#define SET_RG_5G_EN_RX_MIXER(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,5,0xffffffdf)
+#define SET_RG_5G_RX_DIV2_MANUAL(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,6,0xffffffbf)
+#define SET_RG_5G_EN_RX_DIV2(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,7,0xffffff7f)
+#define SET_RG_5G_RX_LOBUF_MANUAL(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,8,0xfffffeff)
+#define SET_RG_5G_EN_RX_LOBUF(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,9,0xfffffdff)
+#define SET_RG_5G_RX_TZ_MANUAL(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,10,0xfffffbff)
+#define SET_RG_5G_EN_RX_TZ(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,11,0xfffff7ff)
+#define SET_RG_5G_TX_PA_MANUAL(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,12,0xffffefff)
+#define SET_RG_5G_EN_TX_PA(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,13,0xffffdfff)
+#define SET_RG_5G_TX_MOD_MANUAL(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,14,0xffffbfff)
+#define SET_RG_5G_EN_TX_MOD(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,15,0xffff7fff)
+#define SET_RG_5G_TX_DIV2_MANUAL(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,18,0xfffbffff)
+#define SET_RG_5G_EN_TX_DIV2(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,19,0xfff7ffff)
+#define SET_RG_5G_TX_DIV2_BUF_MANUAL(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,20,0xffefffff)
+#define SET_RG_5G_EN_TX_DIV2_BUF(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,21,0xffdfffff)
+#define SET_RG_5G_RX_TZ_OUT_TRISTATE_MANUAL(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,22,0xffbfffff)
+#define SET_RG_5G_RX_TZ_OUT_TRISTATE(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,23,0xff7fffff)
+#define SET_RG_5G_TX_SELF_MIXER_MANUAL(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,24,0xfeffffff)
+#define SET_RG_5G_EN_TX_SELF_MIXER(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,25,0xfdffffff)
+#define SET_RG_5G_RX_IQCAL_MANUAL(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,26,0xfbffffff)
+#define SET_RG_5G_EN_RX_IQCAL(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,27,0xf7ffffff)
+#define SET_RG_5G_TX_DPD_MANUAL(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,28,0xefffffff)
+#define SET_RG_5G_EN_TX_DPD(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,29,0xdfffffff)
+#define SET_RG_5G_EN_TX_TSSI(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,30,0xbfffffff)
+#define SET_RG_5G_LDO_LEVEL_RX_FE(_VAL_) SET_REG(ADR_5G_LDO_REGISTER,_VAL_,0,0xfffffff8)
+#define SET_RG_5G_EN_LDO_RX_FE_BYP(_VAL_) SET_REG(ADR_5G_LDO_REGISTER,_VAL_,3,0xfffffff7)
+#define SET_RG_SX5GB_LDO_CP_LEVEL(_VAL_) SET_REG(ADR_5G_LDO_REGISTER,_VAL_,4,0xffffff8f)
+#define SET_RG_EN_LDO_5G_CP_BYP(_VAL_) SET_REG(ADR_5G_LDO_REGISTER,_VAL_,7,0xffffff7f)
+#define SET_RG_SX5GB_LDO_LO_LEVEL(_VAL_) SET_REG(ADR_5G_LDO_REGISTER,_VAL_,8,0xfffff8ff)
+#define SET_RG_EN_LDO_5G_LO_BYP(_VAL_) SET_REG(ADR_5G_LDO_REGISTER,_VAL_,11,0xfffff7ff)
+#define SET_RG_SX5GB_LDO_VCO_LEVEL(_VAL_) SET_REG(ADR_5G_LDO_REGISTER,_VAL_,12,0xffff8fff)
+#define SET_RG_SX5GB_LDO_DIV_LEVEL(_VAL_) SET_REG(ADR_5G_LDO_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_EN_LDO_5G_DIV_BYP(_VAL_) SET_REG(ADR_5G_LDO_REGISTER,_VAL_,19,0xfff7ffff)
+#define SET_RG_5G_EN_LDO_RX_FE(_VAL_) SET_REG(ADR_5G_LDO_REGISTER,_VAL_,24,0xfeffffff)
+#define SET_RG_5G_EN_IREF_RX(_VAL_) SET_REG(ADR_5G_LDO_REGISTER,_VAL_,25,0xfdffffff)
+#define SET_RG_5G_EN_LDO_RX_FE_FC(_VAL_) SET_REG(ADR_5G_LDO_REGISTER,_VAL_,26,0xfbffffff)
+#define SET_RG_5G_EN_LDO_RX_FE_IQUP(_VAL_) SET_REG(ADR_5G_LDO_REGISTER,_VAL_,27,0xf7ffffff)
+#define SET_RG_5G_RX_SCA_MANUAL(_VAL_) SET_REG(ADR_5G_RX_REGISTER1,_VAL_,0,0xfffffffe)
+#define SET_RG_5G_RX_SCA_MA(_VAL_) SET_REG(ADR_5G_RX_REGISTER1,_VAL_,1,0xfffffff1)
+#define SET_RG_5G_RX_SCA_LOAD(_VAL_) SET_REG(ADR_5G_RX_REGISTER1,_VAL_,4,0xffffff8f)
+#define SET_RG_5G_RX_LNA_TRI_SEL(_VAL_) SET_REG(ADR_5G_RX_REGISTER1,_VAL_,8,0xfffffcff)
+#define SET_RG_5G_RX_LNA_SETTLE(_VAL_) SET_REG(ADR_5G_RX_REGISTER1,_VAL_,10,0xfffff3ff)
+#define SET_RG_5G_GM_BIAS(_VAL_) SET_REG(ADR_5G_RX_REGISTER1,_VAL_,12,0xffff8fff)
+#define SET_RG_5G_RX_DIV2_BUF(_VAL_) SET_REG(ADR_5G_RX_REGISTER1,_VAL_,16,0xfffcffff)
+#define SET_RG_5G_RX_DIV2_CML(_VAL_) SET_REG(ADR_5G_RX_REGISTER1,_VAL_,18,0xfff3ffff)
+#define SET_RG_5G_RX_DIV_CMLISEL(_VAL_) SET_REG(ADR_5G_RX_REGISTER1,_VAL_,20,0xffcfffff)
+#define SET_RG_5G_RX_DIV_PREBUFS2(_VAL_) SET_REG(ADR_5G_RX_REGISTER1,_VAL_,22,0xffbfffff)
+#define SET_RG_5G_RX_TZ_COURSE(_VAL_) SET_REG(ADR_5G_RX_REGISTER1,_VAL_,24,0xfcffffff)
+#define SET_RG_5G_TX_DPDGM_BIAS(_VAL_) SET_REG(ADR_5G_RX_REGISTER1,_VAL_,28,0x0fffffff)
+#define SET_RG_5G_TX_DPD_DIV(_VAL_) SET_REG(ADR_5G_RX_REGISTER2,_VAL_,0,0xfffffff0)
+#define SET_RG_5G_TX_TSSI_BIAS(_VAL_) SET_REG(ADR_5G_RX_REGISTER2,_VAL_,4,0xffffff8f)
+#define SET_RG_5G_TX_TSSI_DIV(_VAL_) SET_REG(ADR_5G_RX_REGISTER2,_VAL_,8,0xfffff8ff)
+#define SET_RG_5G_TX_TSSI_TEST(_VAL_) SET_REG(ADR_5G_RX_REGISTER2,_VAL_,12,0xffffcfff)
+#define SET_RG_5G_TX_TSSI_TESTMODE(_VAL_) SET_REG(ADR_5G_RX_REGISTER2,_VAL_,14,0xffffbfff)
+#define SET_RG_5G_RX_ADC_ICMP(_VAL_) SET_REG(ADR_5G_RX_REGISTER2,_VAL_,16,0xfffcffff)
+#define SET_RG_5G_RX_ADC_VCMI(_VAL_) SET_REG(ADR_5G_RX_REGISTER2,_VAL_,18,0xfff3ffff)
+#define SET_RG_5G_RX_ADC_CLOAD(_VAL_) SET_REG(ADR_5G_RX_REGISTER2,_VAL_,20,0xffcfffff)
+#define SET_RG_5G_RX_ADC_PSW(_VAL_) SET_REG(ADR_5G_RX_REGISTER2,_VAL_,22,0xffbfffff)
+#define SET_RG_5G_RX_TZ_CMZ_C(_VAL_) SET_REG(ADR_5G_RX_REGISTER2,_VAL_,23,0xfe7fffff)
+#define SET_RG_5G_RX_TZ_CMZ_R(_VAL_) SET_REG(ADR_5G_RX_REGISTER2,_VAL_,25,0xf9ffffff)
+#define SET_RG_5G_TXPAPGA_MANUAL(_VAL_) SET_REG(ADR_5G_TX_FE_REGISTER,_VAL_,0,0xfffffffe)
+#define SET_RG_5G_TXPGA_CAPSW(_VAL_) SET_REG(ADR_5G_TX_FE_REGISTER,_VAL_,1,0xfffffff1)
+#define SET_RG_5G_PACELL_EN(_VAL_) SET_REG(ADR_5G_TX_FE_REGISTER,_VAL_,5,0xffffff1f)
+#define SET_RG_5G_PABIAS_CTRL(_VAL_) SET_REG(ADR_5G_TX_FE_REGISTER,_VAL_,8,0xfffff0ff)
+#define SET_RG_5G_TX_PAFB_EN(_VAL_) SET_REG(ADR_5G_TX_FE_REGISTER,_VAL_,12,0xffffefff)
+#define SET_RG_5G_TX_PA1_VCAS(_VAL_) SET_REG(ADR_5G_TX_FE_REGISTER,_VAL_,13,0xffff1fff)
+#define SET_RG_5G_TX_PA2_VCAS(_VAL_) SET_REG(ADR_5G_TX_FE_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_5G_PABIAS_2X(_VAL_) SET_REG(ADR_5G_TX_FE_REGISTER,_VAL_,19,0xfff7ffff)
+#define SET_RG_5G_TX_PA3_VCAS(_VAL_) SET_REG(ADR_5G_TX_FE_REGISTER,_VAL_,20,0xff8fffff)
+#define SET_RG_5G_TX_DIV_PREBUFS2(_VAL_) SET_REG(ADR_5G_TX_FE_REGISTER,_VAL_,23,0xff7fffff)
+#define SET_RG_5G_TX_DIV_CMLISEL(_VAL_) SET_REG(ADR_5G_TX_FE_REGISTER,_VAL_,24,0xfcffffff)
+#define SET_RG_5G_TX_DIV_CMLVSEL(_VAL_) SET_REG(ADR_5G_TX_FE_REGISTER,_VAL_,26,0xf3ffffff)
+#define SET_RG_5G_TX_DIV_VSET(_VAL_) SET_REG(ADR_5G_TX_FE_REGISTER,_VAL_,28,0xcfffffff)
+#define SET_RG_5G_TX_LOBUF_VSET(_VAL_) SET_REG(ADR_5G_TX_FE_REGISTER,_VAL_,30,0x3fffffff)
+#define SET_RG_5G_TXPGA_MAIN(_VAL_) SET_REG(ADR_5G_TX_REGISTER,_VAL_,0,0xffffffc0)
+#define SET_RG_5G_TXPGA_STEER(_VAL_) SET_REG(ADR_5G_TX_REGISTER,_VAL_,6,0xfffff03f)
+#define SET_RG_5G_TXMOD_GMCELL(_VAL_) SET_REG(ADR_5G_TX_REGISTER,_VAL_,12,0xffffcfff)
+#define SET_RG_5G_TXLPF_GMCELL(_VAL_) SET_REG(ADR_5G_TX_REGISTER,_VAL_,14,0xffff3fff)
+#define SET_RG_5G_TX_GAIN_OFFSET(_VAL_) SET_REG(ADR_5G_TX_REGISTER,_VAL_,16,0xfff0ffff)
+#define SET_RG_5G_TX_GAIN(_VAL_) SET_REG(ADR_5G_TX_REGISTER,_VAL_,20,0xf80fffff)
+#define SET_RG_5G_TX_ADDGMCELL(_VAL_) SET_REG(ADR_5G_TX_REGISTER,_VAL_,27,0xf7ffffff)
+#define SET_RG_5G_TXMOD_LOBIAS(_VAL_) SET_REG(ADR_5G_TX_REGISTER,_VAL_,28,0xcfffffff)
+#define SET_RG_5G_TXMOD_PGABIAS(_VAL_) SET_REG(ADR_5G_TX_REGISTER,_VAL_,30,0x3fffffff)
+#define SET_RG_5G_RX_HG_LNA_GC(_VAL_) SET_REG(ADR_5G_RX_FE_HG_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_5G_RX_HG_TZ_GC(_VAL_) SET_REG(ADR_5G_RX_FE_HG_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_5G_RX_HG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_5G_RX_FE_HG_REGISTER,_VAL_,4,0xffffff0f)
+#define SET_RG_5G_RX_HG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_5G_RX_FE_HG_REGISTER,_VAL_,8,0xfffff0ff)
+#define SET_RG_5G_RX_HG_LNALG_BIAS(_VAL_) SET_REG(ADR_5G_RX_FE_HG_REGISTER,_VAL_,12,0xffff0fff)
+#define SET_RG_5G_RX_HG_TZ_CAP(_VAL_) SET_REG(ADR_5G_RX_FE_HG_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_5G_RX_HG_SQDC(_VAL_) SET_REG(ADR_5G_RX_FE_HG_REGISTER,_VAL_,19,0xffc7ffff)
+#define SET_RG_5G_RX_HG_DIV2_CORE(_VAL_) SET_REG(ADR_5G_RX_FE_HG_REGISTER,_VAL_,22,0xff3fffff)
+#define SET_RG_5G_RX_HG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_5G_RX_FE_HG_REGISTER,_VAL_,24,0xfcffffff)
+#define SET_RG_5G_RX_HG_TZI(_VAL_) SET_REG(ADR_5G_RX_FE_HG_REGISTER,_VAL_,26,0xe3ffffff)
+#define SET_RG_5G_RX_HG_TZ_VCM(_VAL_) SET_REG(ADR_5G_RX_FE_HG_REGISTER,_VAL_,29,0x1fffffff)
+#define SET_RG_5G_RX_MG_LNA_GC(_VAL_) SET_REG(ADR_5G_RX_FE_MG_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_5G_RX_MG_TZ_GC(_VAL_) SET_REG(ADR_5G_RX_FE_MG_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_5G_RX_MG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_5G_RX_FE_MG_REGISTER,_VAL_,4,0xffffff0f)
+#define SET_RG_5G_RX_MG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_5G_RX_FE_MG_REGISTER,_VAL_,8,0xfffff0ff)
+#define SET_RG_5G_RX_MG_LNALG_BIAS(_VAL_) SET_REG(ADR_5G_RX_FE_MG_REGISTER,_VAL_,12,0xffff0fff)
+#define SET_RG_5G_RX_MG_TZ_CAP(_VAL_) SET_REG(ADR_5G_RX_FE_MG_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_5G_RX_MG_SQDC(_VAL_) SET_REG(ADR_5G_RX_FE_MG_REGISTER,_VAL_,19,0xffc7ffff)
+#define SET_RG_5G_RX_MG_DIV2_CORE(_VAL_) SET_REG(ADR_5G_RX_FE_MG_REGISTER,_VAL_,22,0xff3fffff)
+#define SET_RG_5G_RX_MG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_5G_RX_FE_MG_REGISTER,_VAL_,24,0xfcffffff)
+#define SET_RG_5G_RX_MG_TZI(_VAL_) SET_REG(ADR_5G_RX_FE_MG_REGISTER,_VAL_,26,0xe3ffffff)
+#define SET_RG_5G_RX_MG_TZ_VCM(_VAL_) SET_REG(ADR_5G_RX_FE_MG_REGISTER,_VAL_,29,0x1fffffff)
+#define SET_RG_5G_RX_LG_LNA_GC(_VAL_) SET_REG(ADR_5G_RX_FE_LG_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_5G_RX_LG_TZ_GC(_VAL_) SET_REG(ADR_5G_RX_FE_LG_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_5G_RX_LG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_5G_RX_FE_LG_REGISTER,_VAL_,4,0xffffff0f)
+#define SET_RG_5G_RX_LG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_5G_RX_FE_LG_REGISTER,_VAL_,8,0xfffff0ff)
+#define SET_RG_5G_RX_LG_LNALG_BIAS(_VAL_) SET_REG(ADR_5G_RX_FE_LG_REGISTER,_VAL_,12,0xffff0fff)
+#define SET_RG_5G_RX_LG_TZ_CAP(_VAL_) SET_REG(ADR_5G_RX_FE_LG_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_5G_RX_LG_SQDC(_VAL_) SET_REG(ADR_5G_RX_FE_LG_REGISTER,_VAL_,19,0xffc7ffff)
+#define SET_RG_5G_RX_LG_DIV2_CORE(_VAL_) SET_REG(ADR_5G_RX_FE_LG_REGISTER,_VAL_,22,0xff3fffff)
+#define SET_RG_5G_RX_LG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_5G_RX_FE_LG_REGISTER,_VAL_,24,0xfcffffff)
+#define SET_RG_5G_RX_LG_TZI(_VAL_) SET_REG(ADR_5G_RX_FE_LG_REGISTER,_VAL_,26,0xe3ffffff)
+#define SET_RG_5G_RX_LG_TZ_VCM(_VAL_) SET_REG(ADR_5G_RX_FE_LG_REGISTER,_VAL_,29,0x1fffffff)
+#define SET_RG_5G_RX_ULG_LNA_GC(_VAL_) SET_REG(ADR_5G_RX_FE_ULG_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_5G_RX_ULG_TZ_GC(_VAL_) SET_REG(ADR_5G_RX_FE_ULG_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_5G_RX_ULG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_5G_RX_FE_ULG_REGISTER,_VAL_,4,0xffffff0f)
+#define SET_RG_5G_RX_ULG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_5G_RX_FE_ULG_REGISTER,_VAL_,8,0xfffff0ff)
+#define SET_RG_5G_RX_ULG_LNALG_BIAS(_VAL_) SET_REG(ADR_5G_RX_FE_ULG_REGISTER,_VAL_,12,0xffff0fff)
+#define SET_RG_5G_RX_ULG_TZ_CAP(_VAL_) SET_REG(ADR_5G_RX_FE_ULG_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_5G_RX_ULG_SQDC(_VAL_) SET_REG(ADR_5G_RX_FE_ULG_REGISTER,_VAL_,19,0xffc7ffff)
+#define SET_RG_5G_RX_ULG_DIV2_CORE(_VAL_) SET_REG(ADR_5G_RX_FE_ULG_REGISTER,_VAL_,22,0xff3fffff)
+#define SET_RG_5G_RX_ULG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_5G_RX_FE_ULG_REGISTER,_VAL_,24,0xfcffffff)
+#define SET_RG_5G_RX_ULG_TZI(_VAL_) SET_REG(ADR_5G_RX_FE_ULG_REGISTER,_VAL_,26,0xe3ffffff)
+#define SET_RG_5G_RX_ULG_TZ_VCM(_VAL_) SET_REG(ADR_5G_RX_FE_ULG_REGISTER,_VAL_,29,0x1fffffff)
+#define SET_RG_5G_TX_DACI1ST(_VAL_) SET_REG(ADR_5G_TX_DAC_REGISTER,_VAL_,0,0xfffffffc)
+#define SET_RG_5G_TX_DACLPF_ICOARSE(_VAL_) SET_REG(ADR_5G_TX_DAC_REGISTER,_VAL_,2,0xfffffff3)
+#define SET_RG_5G_TX_DACLPF_IFINE(_VAL_) SET_REG(ADR_5G_TX_DAC_REGISTER,_VAL_,4,0xffffffcf)
+#define SET_RG_5G_TX_DACLPF_VCM(_VAL_) SET_REG(ADR_5G_TX_DAC_REGISTER,_VAL_,6,0xffffff3f)
+#define SET_RG_5G_TX_DAC_IBIAS(_VAL_) SET_REG(ADR_5G_TX_DAC_REGISTER,_VAL_,8,0xfffffcff)
+#define SET_RG_5G_TX_DAC_IATTN(_VAL_) SET_REG(ADR_5G_TX_DAC_REGISTER,_VAL_,10,0xfffffbff)
+#define SET_RG_5G_TXLPF_BOOSTI(_VAL_) SET_REG(ADR_5G_TX_DAC_REGISTER,_VAL_,11,0xfffff7ff)
+#define SET_RG_5G_TX_DAC_RCAL(_VAL_) SET_REG(ADR_5G_TX_DAC_REGISTER,_VAL_,12,0xffffcfff)
+#define SET_RG_5G_TX_DAC_CKEDGE_SEL(_VAL_) SET_REG(ADR_5G_TX_DAC_REGISTER,_VAL_,14,0xffffbfff)
+#define SET_RG_5G_TX_DAC_OS(_VAL_) SET_REG(ADR_5G_TX_DAC_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_5G_TX_DAC_IOFFSET(_VAL_) SET_REG(ADR_5G_TX_DAC_REGISTER,_VAL_,20,0xff0fffff)
+#define SET_RG_5G_TX_DAC_QOFFSET(_VAL_) SET_REG(ADR_5G_TX_DAC_REGISTER,_VAL_,24,0xf0ffffff)
+#define SET_RG_SX5GB_RFCTRL_F(_VAL_) SET_REG(ADR_SX_5GB_FRACTIONAL_AND_INTEGER_8BITS,_VAL_,0,0xff000000)
+#define SET_RG_SX5GB_RFCTRL_CH_7_0(_VAL_) SET_REG(ADR_SX_5GB_FRACTIONAL_AND_INTEGER_8BITS,_VAL_,24,0x00ffffff)
+#define SET_RG_SX5GB_RFCTRL_CH_10_8(_VAL_) SET_REG(ADR_SX_5GB_REGISTER_INT3BIT___CH_TABLE,_VAL_,0,0xfffffff8)
+#define SET_RG_SX5GB_RFCH_MAP_EN(_VAL_) SET_REG(ADR_SX_5GB_REGISTER_INT3BIT___CH_TABLE,_VAL_,4,0xffffffef)
+#define SET_RG_SX5GB_LO_TIMES(_VAL_) SET_REG(ADR_SX_5GB_REGISTER_INT3BIT___CH_TABLE,_VAL_,5,0xffffffdf)
+#define SET_RG_SX5GB_CHANNEL(_VAL_) SET_REG(ADR_SX_5GB_REGISTER_INT3BIT___CH_TABLE,_VAL_,8,0xffff00ff)
+#define SET_RG_SX_5GB_EN_MAN(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,0,0xfffffffe)
+#define SET_RG_SX_5GB_EN(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,1,0xfffffffd)
+#define SET_RG_EN_SX5GB_CP_MAN(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,2,0xfffffffb)
+#define SET_RG_EN_SX5GB_CP(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,3,0xfffffff7)
+#define SET_RG_EN_SX5GB_DIV_MAN(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,4,0xffffffef)
+#define SET_RG_EN_SX5GB_DIV(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,5,0xffffffdf)
+#define SET_RG_EN_SX5GB_VCO_MAN(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,6,0xffffffbf)
+#define SET_RG_EN_SX5GB_VCO(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,7,0xffffff7f)
+#define SET_RG_SX5GB_PFD_RST_MAN(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,8,0xfffffeff)
+#define SET_RG_SX5GB_PFD_RST(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,9,0xfffffdff)
+#define SET_RG_SX5GB_UOP_MAN(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,10,0xfffffbff)
+#define SET_RG_SX5GB_UOP_EN(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,11,0xfffff7ff)
+#define SET_RG_EN_SX5GB_HSDIV_MAN(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,12,0xffffefff)
+#define SET_RG_EN_SX5GB_HSDIV(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,13,0xffffdfff)
+#define SET_RG_EN_HSDIV_OBF_SX_MAN(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,14,0xffffbfff)
+#define SET_RG_EN_HSDIV_OBF_SX(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,15,0xffff7fff)
+#define SET_RG_EN_HSDIV_OBF_MX_MAN(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,16,0xfffeffff)
+#define SET_RG_EN_HSDIV_OBF_MX(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,17,0xfffdffff)
+#define SET_RG_EN_SX_MIX_MAN(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,18,0xfffbffff)
+#define SET_RG_EN_SX_MIX(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,19,0xfff7ffff)
+#define SET_RG_EN_SX_REP_MAN(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,20,0xffefffff)
+#define SET_RG_EN_SX_REP(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,21,0xffdfffff)
+#define SET_RG_SX5GB_SBCAL_DIS(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,22,0xffbfffff)
+#define SET_RG_SX5GB_SBCAL_2ND_DIS(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,23,0xff7fffff)
+#define SET_RG_SX5GB_SBCAL_AW(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,24,0xfeffffff)
+#define SET_RG_SX5GB_VOAAC_DIS(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,25,0xfdffffff)
+#define SET_RG_SX5GB_MIXAAC_DIS(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,26,0xfbffffff)
+#define SET_RG_SX5GB_REPAAC_DIS(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,27,0xf7ffffff)
+#define SET_RG_SX5GB_TTL_DIS(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,28,0xefffffff)
+#define SET_RG_SX5GB_CAL_INIT(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,29,0x1fffffff)
+#define SET_RG_EN_SX5GB_LDO_MAN(_VAL_) SET_REG(ADR_SX_5GB_LDO_REGISTER,_VAL_,0,0xfffffffe)
+#define SET_RG_EN_LDO_5G_CP(_VAL_) SET_REG(ADR_SX_5GB_LDO_REGISTER,_VAL_,1,0xfffffffd)
+#define SET_RG_EN_LDO_5G_DIV(_VAL_) SET_REG(ADR_SX_5GB_LDO_REGISTER,_VAL_,2,0xfffffffb)
+#define SET_RG_EN_LDO_5G_LO(_VAL_) SET_REG(ADR_SX_5GB_LDO_REGISTER,_VAL_,3,0xfffffff7)
+#define SET_RG_EN_LDO_5G_VCO(_VAL_) SET_REG(ADR_SX_5GB_LDO_REGISTER,_VAL_,4,0xffffffef)
+#define SET_RG_EN_SXMIX_INBF_MAN(_VAL_) SET_REG(ADR_SX_5GB_LDO_REGISTER,_VAL_,6,0xffffffbf)
+#define SET_RG_EN_SXMIX_INBF(_VAL_) SET_REG(ADR_SX_5GB_LDO_REGISTER,_VAL_,7,0xffffff7f)
+#define SET_RG_EN_LDO_5G_VCO_PSW(_VAL_) SET_REG(ADR_SX_5GB_LDO_REGISTER,_VAL_,9,0xfffffdff)
+#define SET_RG_EN_LDO_5G_VCO_VDD33(_VAL_) SET_REG(ADR_SX_5GB_LDO_REGISTER,_VAL_,10,0xfffffbff)
+#define SET_RG_EN_LDO_5G_CP_IQUP(_VAL_) SET_REG(ADR_SX_5GB_LDO_REGISTER,_VAL_,11,0xfffff7ff)
+#define SET_RG_EN_LDO_5G_DIV_IQUP(_VAL_) SET_REG(ADR_SX_5GB_LDO_REGISTER,_VAL_,12,0xffffefff)
+#define SET_RG_EN_LDO_5G_LO_IQUP(_VAL_) SET_REG(ADR_SX_5GB_LDO_REGISTER,_VAL_,13,0xffffdfff)
+#define SET_RG_EN_LDO_5G_VCO_IQUP(_VAL_) SET_REG(ADR_SX_5GB_LDO_REGISTER,_VAL_,14,0xffffbfff)
+#define SET_RG_SX5GB_LDO_FCOFFT(_VAL_) SET_REG(ADR_SX_5GB_LDO_REGISTER,_VAL_,19,0xffc7ffff)
+#define SET_RG_LDO_5G_CP_FC_MAN(_VAL_) SET_REG(ADR_SX_5GB_LDO_REGISTER,_VAL_,22,0xffbfffff)
+#define SET_RG_LDO_5G_CP_FC(_VAL_) SET_REG(ADR_SX_5GB_LDO_REGISTER,_VAL_,23,0xff7fffff)
+#define SET_RG_LDO_5G_DIV_FC_MAN(_VAL_) SET_REG(ADR_SX_5GB_LDO_REGISTER,_VAL_,24,0xfeffffff)
+#define SET_RG_LDO_5G_DIV_FC(_VAL_) SET_REG(ADR_SX_5GB_LDO_REGISTER,_VAL_,25,0xfdffffff)
+#define SET_RG_LDO_5G_LO_FC_MAN(_VAL_) SET_REG(ADR_SX_5GB_LDO_REGISTER,_VAL_,26,0xfbffffff)
+#define SET_RG_LDO_5G_LO_FC(_VAL_) SET_REG(ADR_SX_5GB_LDO_REGISTER,_VAL_,27,0xf7ffffff)
+#define SET_RG_LDO_5G_VCO_FC_MAN(_VAL_) SET_REG(ADR_SX_5GB_LDO_REGISTER,_VAL_,28,0xefffffff)
+#define SET_RG_LDO_5G_VCO_FC(_VAL_) SET_REG(ADR_SX_5GB_LDO_REGISTER,_VAL_,29,0xdfffffff)
+#define SET_RG_LDO_5G_VCO_RCF(_VAL_) SET_REG(ADR_SX_5GB_LDO_REGISTER,_VAL_,30,0x3fffffff)
+#define SET_RG_SX5GB_CP_ISEL(_VAL_) SET_REG(ADR_SX_5GB_PFD_CHP_,_VAL_,0,0xfffffff0)
+#define SET_RG_SX5GB_CP_ISEL50U(_VAL_) SET_REG(ADR_SX_5GB_PFD_CHP_,_VAL_,4,0xffffffef)
+#define SET_RG_SX5GB_CP_KP_DOUB(_VAL_) SET_REG(ADR_SX_5GB_PFD_CHP_,_VAL_,5,0xffffffdf)
+#define SET_RG_SX5GB_CP_IOST_POL(_VAL_) SET_REG(ADR_SX_5GB_PFD_CHP_,_VAL_,7,0xffffff7f)
+#define SET_RG_SX5GB_CP_IOST(_VAL_) SET_REG(ADR_SX_5GB_PFD_CHP_,_VAL_,8,0xfffff8ff)
+#define SET_RG_SX5GB_PFD_SEL(_VAL_) SET_REG(ADR_SX_5GB_PFD_CHP_,_VAL_,12,0xffffefff)
+#define SET_RG_SX5GB_PFD_SET(_VAL_) SET_REG(ADR_SX_5GB_PFD_CHP_,_VAL_,13,0xffffdfff)
+#define SET_RG_SX5GB_PFD_SET1(_VAL_) SET_REG(ADR_SX_5GB_PFD_CHP_,_VAL_,14,0xffffbfff)
+#define SET_RG_SX5GB_PFD_SET2(_VAL_) SET_REG(ADR_SX_5GB_PFD_CHP_,_VAL_,15,0xffff7fff)
+#define SET_RG_SX5GB_PFD_TRUP(_VAL_) SET_REG(ADR_SX_5GB_PFD_CHP_,_VAL_,16,0xfffeffff)
+#define SET_RG_SX5GB_PFD_TRDN(_VAL_) SET_REG(ADR_SX_5GB_PFD_CHP_,_VAL_,17,0xfffdffff)
+#define SET_RG_SX5GB_PFD_TLSEL(_VAL_) SET_REG(ADR_SX_5GB_PFD_CHP_,_VAL_,18,0xfffbffff)
+#define SET_RG_SX5GB_PFD_REF_EDGE(_VAL_) SET_REG(ADR_SX_5GB_PFD_CHP_,_VAL_,19,0xfff7ffff)
+#define SET_RG_SX5GB_PFD_DIV_EDGE(_VAL_) SET_REG(ADR_SX_5GB_PFD_CHP_,_VAL_,20,0xffefffff)
+#define SET_RG_SX5GB_LPF_C1(_VAL_) SET_REG(ADR_SX_5GB_LPF_TTL,_VAL_,0,0xfffffff0)
+#define SET_RG_SX5GB_LPF_C2(_VAL_) SET_REG(ADR_SX_5GB_LPF_TTL,_VAL_,4,0xffffff0f)
+#define SET_RG_SX5GB_LPF_C3(_VAL_) SET_REG(ADR_SX_5GB_LPF_TTL,_VAL_,8,0xfffffeff)
+#define SET_RG_SX5GB_LPF_R2(_VAL_) SET_REG(ADR_SX_5GB_LPF_TTL,_VAL_,9,0xffffe1ff)
+#define SET_RG_SX5GB_LPF_R3(_VAL_) SET_REG(ADR_SX_5GB_LPF_TTL,_VAL_,13,0xffff1fff)
+#define SET_RG_SX5GB_TTL_INIT(_VAL_) SET_REG(ADR_SX_5GB_LPF_TTL,_VAL_,16,0xfffcffff)
+#define SET_RG_SX5GB_TTL_FPT(_VAL_) SET_REG(ADR_SX_5GB_LPF_TTL,_VAL_,18,0xfff3ffff)
+#define SET_RG_SX5GB_TTL_CPT(_VAL_) SET_REG(ADR_SX_5GB_LPF_TTL,_VAL_,20,0xffcfffff)
+#define SET_RG_SX5GB_TTL_ACCUM(_VAL_) SET_REG(ADR_SX_5GB_LPF_TTL,_VAL_,22,0xff3fffff)
+#define SET_RG_SX5GB_TTL_SUB(_VAL_) SET_REG(ADR_SX_5GB_LPF_TTL,_VAL_,24,0xfcffffff)
+#define SET_RG_SX5GB_TTL_SUB_INV(_VAL_) SET_REG(ADR_SX_5GB_LPF_TTL,_VAL_,26,0xfbffffff)
+#define SET_RG_SX5GB_TTL_VH(_VAL_) SET_REG(ADR_SX_5GB_LPF_TTL,_VAL_,27,0xe7ffffff)
+#define SET_RG_SX5GB_TTL_VL(_VAL_) SET_REG(ADR_SX_5GB_LPF_TTL,_VAL_,29,0x9fffffff)
+#define SET_RG_SX5GB_LPF_VTUNE_TEST(_VAL_) SET_REG(ADR_SX_5GB_LPF_TTL,_VAL_,31,0x7fffffff)
+#define SET_RG_SX5GB_VCO_ISEL_MAN(_VAL_) SET_REG(ADR_SX_5GB_VCO_LOGEN,_VAL_,0,0xfffffffe)
+#define SET_RG_SX5GB_VCO_ISEL(_VAL_) SET_REG(ADR_SX_5GB_VCO_LOGEN,_VAL_,1,0xffffffe1)
+#define SET_RG_SX5GB_VCO_VCCBSEL(_VAL_) SET_REG(ADR_SX_5GB_VCO_LOGEN,_VAL_,6,0xfffffe3f)
+#define SET_RG_SX5GB_VCO_KVDOUB(_VAL_) SET_REG(ADR_SX_5GB_VCO_LOGEN,_VAL_,9,0xfffffdff)
+#define SET_RG_SX5GB_VCO_VARBSEL(_VAL_) SET_REG(ADR_SX_5GB_VCO_LOGEN,_VAL_,11,0xffffe7ff)
+#define SET_RG_SX5GB_VCO_RTAIL_SHIFT(_VAL_) SET_REG(ADR_SX_5GB_VCO_LOGEN,_VAL_,13,0xffffdfff)
+#define SET_RG_SX5GB_VCO_CS_AWH(_VAL_) SET_REG(ADR_SX_5GB_VCO_LOGEN,_VAL_,14,0xffffbfff)
+#define SET_RG_HSDIV_INBFSEL(_VAL_) SET_REG(ADR_SX_5GB_VCO_LOGEN,_VAL_,15,0xfffe7fff)
+#define SET_RG_HSDIV_OBFMX_SEL(_VAL_) SET_REG(ADR_SX_5GB_VCO_LOGEN,_VAL_,17,0xfffdffff)
+#define SET_RG_HSDIV_OBFSX_SEL(_VAL_) SET_REG(ADR_SX_5GB_VCO_LOGEN,_VAL_,18,0xfffbffff)
+#define SET_RG_HSDIV_VRSEL(_VAL_) SET_REG(ADR_SX_5GB_VCO_LOGEN,_VAL_,19,0xffe7ffff)
+#define SET_RG_SXMIX_IBIAS_SEL(_VAL_) SET_REG(ADR_SX_5GB_VCO_LOGEN,_VAL_,21,0xff9fffff)
+#define SET_RG_SXMIX_SWB_SEL(_VAL_) SET_REG(ADR_SX_5GB_VCO_LOGEN,_VAL_,23,0xfe7fffff)
+#define SET_RG_SXMIX_GMSEL(_VAL_) SET_REG(ADR_SX_5GB_VCO_LOGEN,_VAL_,25,0xf9ffffff)
+#define SET_RG_SXREP_SWB_SEL(_VAL_) SET_REG(ADR_SX_5GB_VCO_LOGEN,_VAL_,27,0xe7ffffff)
+#define SET_RG_SXREP_CSSEL(_VAL_) SET_REG(ADR_SX_5GB_VCO_LOGEN,_VAL_,29,0x9fffffff)
+#define SET_RG_EN_SX5GB_VCOMON(_VAL_) SET_REG(ADR_SX_5GB_VCO_LOGEN,_VAL_,31,0x7fffffff)
+#define SET_RG_SX5GB_DIV_PREVDD(_VAL_) SET_REG(ADR_SX_5GB_DIV_SDM,_VAL_,0,0xfffffff0)
+#define SET_RG_SX5GB_DIV_PSCVDD(_VAL_) SET_REG(ADR_SX_5GB_DIV_SDM,_VAL_,4,0xffffff0f)
+#define SET_RG_SX5GB_DIV_RST_H(_VAL_) SET_REG(ADR_SX_5GB_DIV_SDM,_VAL_,9,0xfffffdff)
+#define SET_RG_SX5GB_DIV_SDM_EDGE(_VAL_) SET_REG(ADR_SX_5GB_DIV_SDM,_VAL_,10,0xfffffbff)
+#define SET_RG_SX5GB_DIV_DMYBUF_EN(_VAL_) SET_REG(ADR_SX_5GB_DIV_SDM,_VAL_,11,0xfffff7ff)
+#define SET_RG_EN_SX5GB_MOD(_VAL_) SET_REG(ADR_SX_5GB_DIV_SDM,_VAL_,17,0xfffdffff)
+#define SET_RG_EN_SX5GB_DITHER(_VAL_) SET_REG(ADR_SX_5GB_DIV_SDM,_VAL_,18,0xfffbffff)
+#define SET_RG_SX5GB_MOD_ORDER(_VAL_) SET_REG(ADR_SX_5GB_DIV_SDM,_VAL_,19,0xffe7ffff)
+#define SET_RG_SX5GB_DITHER_WEIGHT(_VAL_) SET_REG(ADR_SX_5GB_DIV_SDM,_VAL_,21,0xff9fffff)
+#define SET_RG_SXMIX_INBF_SEL(_VAL_) SET_REG(ADR_SX_5GB_DIV_SDM,_VAL_,24,0xfcffffff)
+#define SET_RG_SXMIX_GMBIAS_OP1(_VAL_) SET_REG(ADR_SX_5GB_DIV_SDM,_VAL_,26,0xfbffffff)
+#define SET_RG_SXMIX_SWBIAS_OP1(_VAL_) SET_REG(ADR_SX_5GB_DIV_SDM,_VAL_,27,0xf7ffffff)
+#define SET_RG_SX5GB_SUB_SEL_MAN(_VAL_) SET_REG(ADR_SX_5GB_SBCAL,_VAL_,0,0xfffffffe)
+#define SET_RG_SX5GB_SUB_SEL(_VAL_) SET_REG(ADR_SX_5GB_SBCAL,_VAL_,1,0xfffffe01)
+#define SET_RG_SX5GB_SUB_C0P5_DIS(_VAL_) SET_REG(ADR_SX_5GB_SBCAL,_VAL_,9,0xfffffdff)
+#define SET_RG_SX5GB_SBCAL_CT(_VAL_) SET_REG(ADR_SX_5GB_SBCAL,_VAL_,10,0xfffff3ff)
+#define SET_RG_SX5GB_SBCAL_WT(_VAL_) SET_REG(ADR_SX_5GB_SBCAL,_VAL_,12,0xffffefff)
+#define SET_RG_SX5GB_SBCAL_DIFFMIN(_VAL_) SET_REG(ADR_SX_5GB_SBCAL,_VAL_,13,0xffffdfff)
+#define SET_RG_SX5GB_SBCAL_NTARG_MAN(_VAL_) SET_REG(ADR_SX_5GB_SBCAL,_VAL_,15,0xffff7fff)
+#define SET_RG_SX5GB_SBCAL_NTARG(_VAL_) SET_REG(ADR_SX_5GB_SBCAL,_VAL_,16,0x0000ffff)
+#define SET_RG_SX5GB_VOAAC_TAR(_VAL_) SET_REG(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,0,0xfffffff0)
+#define SET_RG_VO5GB_AAC_IOST(_VAL_) SET_REG(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,4,0xffffffcf)
+#define SET_RG_VO5GB_AAC_IMAX(_VAL_) SET_REG(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,6,0xfffffc3f)
+#define SET_RG_SX5GB_AAC_ACCUMH(_VAL_) SET_REG(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,10,0xfffff3ff)
+#define SET_RG_SX5GB_AAC_ACCUML(_VAL_) SET_REG(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,12,0xffffcfff)
+#define SET_RG_SX5GB_AAC_INIT(_VAL_) SET_REG(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,14,0xffff3fff)
+#define SET_RG_SX5GB_AAC_EVA_TS(_VAL_) SET_REG(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,16,0xfffcffff)
+#define SET_RG_SX5GB_AAC_EN_MAN(_VAL_) SET_REG(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,18,0xfffbffff)
+#define SET_RG_SX5GB_AAC_EN(_VAL_) SET_REG(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,19,0xfff7ffff)
+#define SET_RG_SX5GB_AAC_EVA_MAN(_VAL_) SET_REG(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,20,0xffefffff)
+#define SET_RG_SX5GB_AAC_EVA(_VAL_) SET_REG(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,21,0xffdfffff)
+#define SET_RG_AAC5GB_TAR_MAN(_VAL_) SET_REG(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,22,0xffbfffff)
+#define SET_RG_AAC5GB_PDSW_EN_MAN(_VAL_) SET_REG(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,24,0xfeffffff)
+#define SET_RG_EN_AAC5GB_VOPDSW(_VAL_) SET_REG(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,25,0xfdffffff)
+#define SET_RG_EN_AAC5GB_MXPDSW(_VAL_) SET_REG(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,26,0xfbffffff)
+#define SET_RG_EN_AAC5GB_RPPDSW(_VAL_) SET_REG(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,27,0xf7ffffff)
+#define SET_RG_SX5GB_AAC_TEST_EN(_VAL_) SET_REG(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,30,0xbfffffff)
+#define SET_RG_SX5GB_AAC_TEST_SEL(_VAL_) SET_REG(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,31,0x7fffffff)
+#define SET_RG_SX5GB_MIXAAC_TAR(_VAL_) SET_REG(ADR_SX_5GB_LOGEN_CALIBRATION,_VAL_,0,0xfffffff0)
+#define SET_RG_SXMIX_SCA_SEL_MAN(_VAL_) SET_REG(ADR_SX_5GB_LOGEN_CALIBRATION,_VAL_,5,0xffffffdf)
+#define SET_RG_SXMIX_SCA_SEL(_VAL_) SET_REG(ADR_SX_5GB_LOGEN_CALIBRATION,_VAL_,6,0xfffff03f)
+#define SET_RG_SX5GB_REPAAC_TAR(_VAL_) SET_REG(ADR_SX_5GB_LOGEN_CALIBRATION,_VAL_,13,0xfffe1fff)
+#define SET_RG_SXREP_SCA_SEL_MAN(_VAL_) SET_REG(ADR_SX_5GB_LOGEN_CALIBRATION,_VAL_,18,0xfffbffff)
+#define SET_RG_SXREP_SCA_SEL(_VAL_) SET_REG(ADR_SX_5GB_LOGEN_CALIBRATION,_VAL_,19,0xfe07ffff)
+#define SET_RG_5G_IDACAI_TZ0_PGAG15(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER1,_VAL_,0,0xffffffc0)
+#define SET_RG_5G_IDACAQ_TZ0_PGAG15(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER1,_VAL_,8,0xffffc0ff)
+#define SET_RG_5G_IDACAI_TZ0_PGAG14(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER1,_VAL_,16,0xffc0ffff)
+#define SET_RG_5G_IDACAQ_TZ0_PGAG14(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER1,_VAL_,24,0xc0ffffff)
+#define SET_RG_5G_IDACAI_TZ0_PGAG13(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER2,_VAL_,0,0xffffffc0)
+#define SET_RG_5G_IDACAQ_TZ0_PGAG13(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER2,_VAL_,8,0xffffc0ff)
+#define SET_RG_5G_IDACAI_TZ0_PGAG12(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER2,_VAL_,16,0xffc0ffff)
+#define SET_RG_5G_IDACAQ_TZ0_PGAG12(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER2,_VAL_,24,0xc0ffffff)
+#define SET_RG_5G_IDACAI_TZ0_PGAG11(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER3,_VAL_,0,0xffffffc0)
+#define SET_RG_5G_IDACAQ_TZ0_PGAG11(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER3,_VAL_,8,0xffffc0ff)
+#define SET_RG_5G_IDACAI_TZ0_PGAG10(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER3,_VAL_,16,0xffc0ffff)
+#define SET_RG_5G_IDACAQ_TZ0_PGAG10(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER3,_VAL_,24,0xc0ffffff)
+#define SET_RG_5G_IDACAI_TZ0_PGAG9(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER4,_VAL_,0,0xffffffc0)
+#define SET_RG_5G_IDACAQ_TZ0_PGAG9(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER4,_VAL_,8,0xffffc0ff)
+#define SET_RG_5G_IDACAI_TZ0_PGAG8(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER4,_VAL_,16,0xffc0ffff)
+#define SET_RG_5G_IDACAQ_TZ0_PGAG8(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER4,_VAL_,24,0xc0ffffff)
+#define SET_RG_5G_IDACAI_TZ0_PGAG7(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER5,_VAL_,0,0xffffffc0)
+#define SET_RG_5G_IDACAQ_TZ0_PGAG7(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER5,_VAL_,8,0xffffc0ff)
+#define SET_RG_5G_IDACAI_TZ0_PGAG6(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER5,_VAL_,16,0xffc0ffff)
+#define SET_RG_5G_IDACAQ_TZ0_PGAG6(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER5,_VAL_,24,0xc0ffffff)
+#define SET_RG_5G_IDACAI_TZ0_PGAG5(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER6,_VAL_,0,0xffffffc0)
+#define SET_RG_5G_IDACAQ_TZ0_PGAG5(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER6,_VAL_,8,0xffffc0ff)
+#define SET_RG_5G_IDACAI_TZ0_PGAG4(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER6,_VAL_,16,0xffc0ffff)
+#define SET_RG_5G_IDACAQ_TZ0_PGAG4(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER6,_VAL_,24,0xc0ffffff)
+#define SET_RG_5G_IDACAI_TZ0_PGAG3(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER7,_VAL_,0,0xffffffc0)
+#define SET_RG_5G_IDACAQ_TZ0_PGAG3(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER7,_VAL_,8,0xffffc0ff)
+#define SET_RG_5G_IDACAI_TZ0_PGAG2(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER7,_VAL_,16,0xffc0ffff)
+#define SET_RG_5G_IDACAQ_TZ0_PGAG2(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER7,_VAL_,24,0xc0ffffff)
+#define SET_RG_5G_IDACAI_TZ0_PGAG1(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER8,_VAL_,0,0xffffffc0)
+#define SET_RG_5G_IDACAQ_TZ0_PGAG1(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER8,_VAL_,8,0xffffc0ff)
+#define SET_RG_5G_IDACAI_TZ0_PGAG0(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER8,_VAL_,16,0xffc0ffff)
+#define SET_RG_5G_IDACAQ_TZ0_PGAG0(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER8,_VAL_,24,0xc0ffffff)
+#define SET_RG_5G_IDACAI_TZ1_PGAG15(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER9,_VAL_,0,0xffffffc0)
+#define SET_RG_5G_IDACAQ_TZ1_PGAG15(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER9,_VAL_,8,0xffffc0ff)
+#define SET_RG_5G_IDACAI_TZ1_PGAG14(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER9,_VAL_,16,0xffc0ffff)
+#define SET_RG_5G_IDACAQ_TZ1_PGAG14(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER9,_VAL_,24,0xc0ffffff)
+#define SET_RG_5G_IDACAI_TZ1_PGAG13(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER10,_VAL_,0,0xffffffc0)
+#define SET_RG_5G_IDACAQ_TZ1_PGAG13(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER10,_VAL_,8,0xffffc0ff)
+#define SET_RG_5G_IDACAI_TZ1_PGAG12(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER10,_VAL_,16,0xffc0ffff)
+#define SET_RG_5G_IDACAQ_TZ1_PGAG12(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER10,_VAL_,24,0xc0ffffff)
+#define SET_RG_5G_IDACAI_TZ1_PGAG11(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER11,_VAL_,0,0xffffffc0)
+#define SET_RG_5G_IDACAQ_TZ1_PGAG11(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER11,_VAL_,8,0xffffc0ff)
+#define SET_RG_5G_IDACAI_TZ1_PGAG10(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER11,_VAL_,16,0xffc0ffff)
+#define SET_RG_5G_IDACAQ_TZ1_PGAG10(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER11,_VAL_,24,0xc0ffffff)
+#define SET_RG_5G_IDACAI_TZ1_PGAG9(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER12,_VAL_,0,0xffffffc0)
+#define SET_RG_5G_IDACAQ_TZ1_PGAG9(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER12,_VAL_,8,0xffffc0ff)
+#define SET_RG_5G_IDACAI_TZ1_PGAG8(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER12,_VAL_,16,0xffc0ffff)
+#define SET_RG_5G_IDACAQ_TZ1_PGAG8(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER12,_VAL_,24,0xc0ffffff)
+#define SET_RG_5G_IDACAI_TZ1_PGAG7(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER13,_VAL_,0,0xffffffc0)
+#define SET_RG_5G_IDACAQ_TZ1_PGAG7(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER13,_VAL_,8,0xffffc0ff)
+#define SET_RG_5G_IDACAI_TZ1_PGAG6(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER13,_VAL_,16,0xffc0ffff)
+#define SET_RG_5G_IDACAQ_TZ1_PGAG6(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER13,_VAL_,24,0xc0ffffff)
+#define SET_RG_5G_IDACAI_TZ1_PGAG5(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER14,_VAL_,0,0xffffffc0)
+#define SET_RG_5G_IDACAQ_TZ1_PGAG5(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER14,_VAL_,8,0xffffc0ff)
+#define SET_RG_5G_IDACAI_TZ1_PGAG4(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER14,_VAL_,16,0xffc0ffff)
+#define SET_RG_5G_IDACAQ_TZ1_PGAG4(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER14,_VAL_,24,0xc0ffffff)
+#define SET_RG_5G_IDACAI_TZ1_PGAG3(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER15,_VAL_,0,0xffffffc0)
+#define SET_RG_5G_IDACAQ_TZ1_PGAG3(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER15,_VAL_,8,0xffffc0ff)
+#define SET_RG_5G_IDACAI_TZ1_PGAG2(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER15,_VAL_,16,0xffc0ffff)
+#define SET_RG_5G_IDACAQ_TZ1_PGAG2(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER15,_VAL_,24,0xc0ffffff)
+#define SET_RG_5G_IDACAI_TZ1_PGAG1(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER16,_VAL_,0,0xffffffc0)
+#define SET_RG_5G_IDACAQ_TZ1_PGAG1(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER16,_VAL_,8,0xffffc0ff)
+#define SET_RG_5G_IDACAI_TZ1_PGAG0(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER16,_VAL_,16,0xffc0ffff)
+#define SET_RG_5G_IDACAQ_TZ1_PGAG0(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER16,_VAL_,24,0xc0ffffff)
+#define SET_RG_5G_IDACAI_TZ0_COARSE4(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER17,_VAL_,0,0xffffffc0)
+#define SET_RG_5G_IDACAQ_TZ0_COARSE4(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER17,_VAL_,8,0xffffc0ff)
+#define SET_RG_5G_IDACAI_TZ0_COARSE3(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER17,_VAL_,16,0xffc0ffff)
+#define SET_RG_5G_IDACAQ_TZ0_COARSE3(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER17,_VAL_,24,0xc0ffffff)
+#define SET_RG_5G_IDACAI_TZ0_COARSE2(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER18,_VAL_,0,0xffffffc0)
+#define SET_RG_5G_IDACAQ_TZ0_COARSE2(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER18,_VAL_,8,0xffffc0ff)
+#define SET_RG_5G_IDACAI_TZ0_COARSE1(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER18,_VAL_,16,0xffc0ffff)
+#define SET_RG_5G_IDACAQ_TZ0_COARSE1(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER18,_VAL_,24,0xc0ffffff)
+#define SET_RG_5G_IDACAI_TZ0_COARSE0(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER19,_VAL_,0,0xffffffc0)
+#define SET_RG_5G_IDACAQ_TZ0_COARSE0(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER19,_VAL_,8,0xffffc0ff)
+#define SET_RG_5G_IDACAI_TZ1_COARSE4(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER19,_VAL_,16,0xffc0ffff)
+#define SET_RG_5G_IDACAQ_TZ1_COARSE4(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER19,_VAL_,24,0xc0ffffff)
+#define SET_RG_5G_IDACAI_TZ1_COARSE3(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER20,_VAL_,0,0xffffffc0)
+#define SET_RG_5G_IDACAQ_TZ1_COARSE3(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER20,_VAL_,8,0xffffc0ff)
+#define SET_RG_5G_IDACAI_TZ1_COARSE2(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER20,_VAL_,16,0xffc0ffff)
+#define SET_RG_5G_IDACAQ_TZ1_COARSE2(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER20,_VAL_,24,0xc0ffffff)
+#define SET_RG_5G_IDACAI_TZ1_COARSE1(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER21,_VAL_,0,0xffffffc0)
+#define SET_RG_5G_IDACAQ_TZ1_COARSE1(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER21,_VAL_,8,0xffffc0ff)
+#define SET_RG_5G_IDACAI_TZ1_COARSE0(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER21,_VAL_,16,0xffc0ffff)
+#define SET_RG_5G_IDACAQ_TZ1_COARSE0(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER21,_VAL_,24,0xc0ffffff)
+#define SET_RG_SX5GB_DELAY(_VAL_) SET_REG(ADR_5G_MODE_DECODER_TIMER_REGISTER1,_VAL_,0,0xfffffff0)
+#define SET_RG_5G_TXDAC_DELAY(_VAL_) SET_REG(ADR_5G_MODE_DECODER_TIMER_REGISTER1,_VAL_,4,0xffffff0f)
+#define SET_RG_5G_TXRF_DELAY(_VAL_) SET_REG(ADR_5G_MODE_DECODER_TIMER_REGISTER1,_VAL_,8,0xfffff0ff)
+#define SET_RG_5G_TXPA_DELAY(_VAL_) SET_REG(ADR_5G_MODE_DECODER_TIMER_REGISTER1,_VAL_,12,0xffff0fff)
+#define SET_RG_5G_RXRF_DELAY(_VAL_) SET_REG(ADR_5G_MODE_DECODER_TIMER_REGISTER1,_VAL_,16,0xfff0ffff)
+#define SET_RG_5G_TXDAC_T2R_DELAY(_VAL_) SET_REG(ADR_5G_T2R_TIMER_REGISTER,_VAL_,0,0xffffffe0)
+#define SET_RG_5G_TXRF_T2R_DELAY(_VAL_) SET_REG(ADR_5G_T2R_TIMER_REGISTER,_VAL_,8,0xffffe0ff)
+#define SET_RG_5G_TXPA_T2R_DELAY(_VAL_) SET_REG(ADR_5G_T2R_TIMER_REGISTER,_VAL_,16,0xffe0ffff)
+#define SET_RG_5G_RXRF_T2R_DELAY(_VAL_) SET_REG(ADR_5G_T2R_TIMER_REGISTER,_VAL_,24,0xe0ffffff)
+#define SET_RG_5G_TXDAC_R2T_DELAY(_VAL_) SET_REG(ADR_5G_R2T_TIMER_REGISTER,_VAL_,0,0xffffffe0)
+#define SET_RG_5G_TXRF_R2T_DELAY(_VAL_) SET_REG(ADR_5G_R2T_TIMER_REGISTER,_VAL_,8,0xffffe0ff)
+#define SET_RG_5G_TXPA_R2T_DELAY(_VAL_) SET_REG(ADR_5G_R2T_TIMER_REGISTER,_VAL_,16,0xffe0ffff)
+#define SET_RG_5G_RXRF_R2T_DELAY(_VAL_) SET_REG(ADR_5G_R2T_TIMER_REGISTER,_VAL_,24,0xe0ffffff)
+#define SET_RG_5G_RX_DCCAL_DELAY(_VAL_) SET_REG(ADR_5G_CALIBRATION_TIMER_GAIN_REGISTER,_VAL_,0,0xfffffff8)
+#define SET_RG_5G_TX_DCCAL_DELAY(_VAL_) SET_REG(ADR_5G_CALIBRATION_TIMER_GAIN_REGISTER,_VAL_,8,0xfffff8ff)
+#define SET_RG_5G_TX_IQCAL_DELAY(_VAL_) SET_REG(ADR_5G_CALIBRATION_TIMER_GAIN_REGISTER,_VAL_,12,0xffff8fff)
+#define SET_RG_5G_RX_IQCAL_DELAY(_VAL_) SET_REG(ADR_5G_CALIBRATION_TIMER_GAIN_REGISTER,_VAL_,16,0xfff8ffff)
+#define SET_RG_5G_PGAG_TXCAL(_VAL_) SET_REG(ADR_5G_CALIBRATION_TIMER_GAIN_REGISTER,_VAL_,20,0xff0fffff)
+#define SET_RG_5G_TX_GAIN_TXCAL(_VAL_) SET_REG(ADR_5G_CALIBRATION_TIMER_GAIN_REGISTER,_VAL_,24,0x80ffffff)
+#define SET_RG_5G_PGAG_RCCAL(_VAL_) SET_REG(ADR_5G_CALIBRATION_GAIN_REGISTER1,_VAL_,0,0xfffffff0)
+#define SET_RG_5G_RFG_RXIQCAL(_VAL_) SET_REG(ADR_5G_CALIBRATION_GAIN_REGISTER1,_VAL_,4,0xffffffcf)
+#define SET_RG_5G_PGAG_RXIQCAL(_VAL_) SET_REG(ADR_5G_CALIBRATION_GAIN_REGISTER1,_VAL_,6,0xfffffc3f)
+#define SET_RG_5G_TX_GAIN_RXIQCAL(_VAL_) SET_REG(ADR_5G_CALIBRATION_GAIN_REGISTER1,_VAL_,10,0xfffe03ff)
+#define SET_RG_5G_RFG_DPDCAL(_VAL_) SET_REG(ADR_5G_CALIBRATION_GAIN_REGISTER1,_VAL_,17,0xfff9ffff)
+#define SET_RG_5G_PGAG_DPDCAL(_VAL_) SET_REG(ADR_5G_CALIBRATION_GAIN_REGISTER1,_VAL_,19,0xff87ffff)
+#define SET_RG_5G_TX_GAIN_DPDCAL(_VAL_) SET_REG(ADR_5G_CALIBRATION_GAIN_REGISTER1,_VAL_,23,0xc07fffff)
+#define SET_DB_DA_SX5GB_SUB_SEL(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_SX_5GB_1,_VAL_,0,0xffffff00)
+#define SET_DB_DA_SX5GB_VCO_ISEL(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_SX_5GB_1,_VAL_,8,0xfffff0ff)
+#define SET_DB_DA_SXMIX_SCA_SEL(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_SX_5GB_1,_VAL_,13,0xfff81fff)
+#define SET_DB_DA_SXMIX_GMSEL(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_SX_5GB_1,_VAL_,19,0xffe7ffff)
+#define SET_DB_DA_SXREP_SCA_SEL(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_SX_5GB_1,_VAL_,21,0xf81fffff)
+#define SET_DB_DA_SXREP_CSSEL(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_SX_5GB_1,_VAL_,27,0xe7ffffff)
+#define SET_DB_AD_SX5GB_AAC_COMPOUT(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_SX_5GB_1,_VAL_,29,0xdfffffff)
+#define SET_DB_SX5GB_TTL_VT_DET(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_SX_5GB_1,_VAL_,30,0x3fffffff)
+#define SET_DB_SXMIX_SCA_SEL_A1(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_SX_5GB_2,_VAL_,0,0xffffffc0)
+#define SET_DB_SXMIX_SCA_SEL_A2(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_SX_5GB_2,_VAL_,7,0xffffe07f)
+#define SET_DB_SXREP_SCA_SEL_B1(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_SX_5GB_2,_VAL_,14,0xfff03fff)
+#define SET_DB_SXREP_SCA_SEL_B2(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_SX_5GB_2,_VAL_,21,0xf81fffff)
+#define SET_DB_SX5GB_SBCAL_NCOUNT(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_SX_5GB_3,_VAL_,0,0xffff0000)
+#define SET_DB_SX5GB_SBCAL_NTARGET(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_SX_5GB_3,_VAL_,16,0x0000ffff)
+#define SET_RG_RX_SCAMA_STEP0(_VAL_) SET_REG(ADR_5G_RX_LNA_MATCHING_SCA_CONTROL,_VAL_,0,0xfffffff0)
+#define SET_RG_RX_SCAMA_STEP1(_VAL_) SET_REG(ADR_5G_RX_LNA_MATCHING_SCA_CONTROL,_VAL_,4,0xffffff0f)
+#define SET_RG_RX_SCAMA_STEP2(_VAL_) SET_REG(ADR_5G_RX_LNA_MATCHING_SCA_CONTROL,_VAL_,8,0xfffff0ff)
+#define SET_RG_RX_SCAMA_STEP3(_VAL_) SET_REG(ADR_5G_RX_LNA_MATCHING_SCA_CONTROL,_VAL_,12,0xffff0fff)
+#define SET_RG_RX_SCAMA_STEP4(_VAL_) SET_REG(ADR_5G_RX_LNA_MATCHING_SCA_CONTROL,_VAL_,16,0xfff0ffff)
+#define SET_RG_RX_SCAMA_STEP5(_VAL_) SET_REG(ADR_5G_RX_LNA_MATCHING_SCA_CONTROL,_VAL_,20,0xff0fffff)
+#define SET_RG_RX_SCAMA_STEP6(_VAL_) SET_REG(ADR_5G_RX_LNA_MATCHING_SCA_CONTROL,_VAL_,24,0xf0ffffff)
+#define SET_RG_RX_SCALOAD_STEP0(_VAL_) SET_REG(ADR_5G_RX_LNA_LOAD_SCA_CONTROL,_VAL_,0,0xfffffff0)
+#define SET_RG_RX_SCALOAD_STEP1(_VAL_) SET_REG(ADR_5G_RX_LNA_LOAD_SCA_CONTROL,_VAL_,4,0xffffff0f)
+#define SET_RG_RX_SCALOAD_STEP2(_VAL_) SET_REG(ADR_5G_RX_LNA_LOAD_SCA_CONTROL,_VAL_,8,0xfffff0ff)
+#define SET_RG_RX_SCALOAD_STEP3(_VAL_) SET_REG(ADR_5G_RX_LNA_LOAD_SCA_CONTROL,_VAL_,12,0xffff0fff)
+#define SET_RG_RX_SCALOAD_STEP4(_VAL_) SET_REG(ADR_5G_RX_LNA_LOAD_SCA_CONTROL,_VAL_,16,0xfff0ffff)
+#define SET_RG_RX_SCALOAD_STEP5(_VAL_) SET_REG(ADR_5G_RX_LNA_LOAD_SCA_CONTROL,_VAL_,20,0xff0fffff)
+#define SET_RG_RX_SCALOAD_STEP6(_VAL_) SET_REG(ADR_5G_RX_LNA_LOAD_SCA_CONTROL,_VAL_,24,0xf0ffffff)
+#define SET_RG_5G_TXPGA_CAPSW_F0(_VAL_) SET_REG(ADR_5G_TX_PGA_CAPSW_CONTROL_I,_VAL_,0,0xfffffff8)
+#define SET_RG_5G_PABIAS_CTRL_F0(_VAL_) SET_REG(ADR_5G_TX_PGA_CAPSW_CONTROL_I,_VAL_,3,0xffffff87)
+#define SET_RG_5G_TX_PA1_VCAS_F0(_VAL_) SET_REG(ADR_5G_TX_PGA_CAPSW_CONTROL_I,_VAL_,7,0xfffffc7f)
+#define SET_RG_5G_TX_PA2_VCAS_F0(_VAL_) SET_REG(ADR_5G_TX_PGA_CAPSW_CONTROL_I,_VAL_,10,0xffffe3ff)
+#define SET_RG_5G_TX_PA3_VCAS_F0(_VAL_) SET_REG(ADR_5G_TX_PGA_CAPSW_CONTROL_I,_VAL_,13,0xffff1fff)
+#define SET_RG_5G_TXPGA_CAPSW_F1(_VAL_) SET_REG(ADR_5G_TX_PGA_CAPSW_CONTROL_I,_VAL_,16,0xfff8ffff)
+#define SET_RG_5G_PABIAS_CTRL_F1(_VAL_) SET_REG(ADR_5G_TX_PGA_CAPSW_CONTROL_I,_VAL_,19,0xff87ffff)
+#define SET_RG_5G_TX_PA1_VCAS_F1(_VAL_) SET_REG(ADR_5G_TX_PGA_CAPSW_CONTROL_I,_VAL_,23,0xfc7fffff)
+#define SET_RG_5G_TX_PA2_VCAS_F1(_VAL_) SET_REG(ADR_5G_TX_PGA_CAPSW_CONTROL_I,_VAL_,26,0xe3ffffff)
+#define SET_RG_5G_TX_PA3_VCAS_F1(_VAL_) SET_REG(ADR_5G_TX_PGA_CAPSW_CONTROL_I,_VAL_,29,0x1fffffff)
+#define SET_RG_5G_TXPGA_CAPSW_F2(_VAL_) SET_REG(ADR_5G_TX_PGA_CAPSW_CONTROL_II,_VAL_,0,0xfffffff8)
+#define SET_RG_5G_PABIAS_CTRL_F2(_VAL_) SET_REG(ADR_5G_TX_PGA_CAPSW_CONTROL_II,_VAL_,3,0xffffff87)
+#define SET_RG_5G_TX_PA1_VCAS_F2(_VAL_) SET_REG(ADR_5G_TX_PGA_CAPSW_CONTROL_II,_VAL_,7,0xfffffc7f)
+#define SET_RG_5G_TX_PA2_VCAS_F2(_VAL_) SET_REG(ADR_5G_TX_PGA_CAPSW_CONTROL_II,_VAL_,10,0xffffe3ff)
+#define SET_RG_5G_TX_PA3_VCAS_F2(_VAL_) SET_REG(ADR_5G_TX_PGA_CAPSW_CONTROL_II,_VAL_,13,0xffff1fff)
+#define SET_RG_5G_TXPGA_CAPSW_F3(_VAL_) SET_REG(ADR_5G_TX_PGA_CAPSW_CONTROL_II,_VAL_,16,0xfff8ffff)
+#define SET_RG_5G_PABIAS_CTRL_F3(_VAL_) SET_REG(ADR_5G_TX_PGA_CAPSW_CONTROL_II,_VAL_,19,0xff87ffff)
+#define SET_RG_5G_TX_PA1_VCAS_F3(_VAL_) SET_REG(ADR_5G_TX_PGA_CAPSW_CONTROL_II,_VAL_,23,0xfc7fffff)
+#define SET_RG_5G_TX_PA2_VCAS_F3(_VAL_) SET_REG(ADR_5G_TX_PGA_CAPSW_CONTROL_II,_VAL_,26,0xe3ffffff)
+#define SET_RG_5G_TX_PA3_VCAS_F3(_VAL_) SET_REG(ADR_5G_TX_PGA_CAPSW_CONTROL_II,_VAL_,29,0x1fffffff)
+#define SET_RG_5G_TX_PAFB_EN_F0(_VAL_) SET_REG(ADR_5G_TX_GAIN_PAFB_CONTROL,_VAL_,0,0xfffffffe)
+#define SET_RG_5G_TX_PAFB_EN_F1(_VAL_) SET_REG(ADR_5G_TX_GAIN_PAFB_CONTROL,_VAL_,1,0xfffffffd)
+#define SET_RG_5G_TX_PAFB_EN_F2(_VAL_) SET_REG(ADR_5G_TX_GAIN_PAFB_CONTROL,_VAL_,2,0xfffffffb)
+#define SET_RG_5G_TX_PAFB_EN_F3(_VAL_) SET_REG(ADR_5G_TX_GAIN_PAFB_CONTROL,_VAL_,3,0xfffffff7)
+#define SET_RG_5G_TX_GAIN_F0(_VAL_) SET_REG(ADR_5G_TX_GAIN_PAFB_CONTROL,_VAL_,4,0xfffff80f)
+#define SET_RG_5G_TX_GAIN_F1(_VAL_) SET_REG(ADR_5G_TX_GAIN_PAFB_CONTROL,_VAL_,11,0xfffc07ff)
+#define SET_RG_5G_TX_GAIN_F2(_VAL_) SET_REG(ADR_5G_TX_GAIN_PAFB_CONTROL,_VAL_,18,0xfe03ffff)
+#define SET_RG_5G_TX_GAIN_F3(_VAL_) SET_REG(ADR_5G_TX_GAIN_PAFB_CONTROL,_VAL_,25,0x01ffffff)
+#define SET_RG_NFRAC_DELTA(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_0,_VAL_,0,0xff000000)
+#define SET_RG_40M_MODE(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_0,_VAL_,24,0xfeffffff)
+#define SET_RG_LO_UP_CH(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_0,_VAL_,28,0xefffffff)
+#define SET_RG_BT_TRX_IF(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_1,_VAL_,16,0xf800ffff)
+#define SET_RG_RX_IQ_ALPHA(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_2,_VAL_,0,0xffffffe0)
+#define SET_RG_RX_IQ_THETA(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_2,_VAL_,8,0xffffe0ff)
+#define SET_RG_RX_IQ_MANUAL(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_2,_VAL_,16,0xfffeffff)
+#define SET_RG_RXIQ_NOSHRK(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_2,_VAL_,17,0xfffdffff)
+#define SET_RG_RX_RSSIADC_TH(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_2,_VAL_,20,0xff0fffff)
+#define SET_RG_SUB_DC(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_2,_VAL_,24,0xfeffffff)
+#define SET_RG_RSSI_EDGE_SEL(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_2,_VAL_,26,0xfbffffff)
+#define SET_RG_ADC_EDGE_SEL(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_2,_VAL_,27,0xf7ffffff)
+#define SET_RG_Q_INV(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_2,_VAL_,28,0xefffffff)
+#define SET_RG_I_INV(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_2,_VAL_,29,0xdfffffff)
+#define SET_RG_IQ_SWAP(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_2,_VAL_,30,0xbfffffff)
+#define SET_RG_SIGN_SWAP(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_2,_VAL_,31,0x7fffffff)
+#define SET_RG_TX_IQ_ALPHA(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_3,_VAL_,0,0xffffffe0)
+#define SET_RG_TX_IQ_THETA(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_3,_VAL_,8,0xffffe0ff)
+#define SET_RG_TX_IQ_MANUAL(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_3,_VAL_,16,0xfffeffff)
+#define SET_RG_TXIQ_NOSHRK(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_3,_VAL_,17,0xfffdffff)
+#define SET_RG_TX_IQCAL_TIME(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_3,_VAL_,20,0xffcfffff)
+#define SET_RG_TX_FREQ_OFFSET(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_4,_VAL_,0,0xffff0000)
+#define SET_RG_TONE_SCALE(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_4,_VAL_,16,0xfe00ffff)
+#define SET_RG_BB_SIG_EN(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_4,_VAL_,25,0xfdffffff)
+#define SET_RG_TONE_GEN_EN(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_4,_VAL_,26,0xfbffffff)
+#define SET_RG_TX_UP8X_MAN_EN(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_4,_VAL_,27,0xf7ffffff)
+#define SET_RG_DIS_DAC_OFFSET(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_4,_VAL_,28,0xefffffff)
+#define SET_RG_CLK_320M_INV(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_4,_VAL_,29,0xdfffffff)
+#define SET_RG_DPLL_CLK320BY2(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_4,_VAL_,30,0xbfffffff)
+#define SET_RG_CBW_20_40(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_4,_VAL_,31,0x7fffffff)
+#define SET_RG_DAC_DC_Q(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_5,_VAL_,0,0xfffffc00)
+#define SET_RG_DAC_DC_I(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_5,_VAL_,16,0xfc00ffff)
+#define SET_RG_DAC_Q_SET(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_6,_VAL_,0,0xfffffc00)
+#define SET_RG_DAC_MAN_Q_EN(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_6,_VAL_,12,0xffffefff)
+#define SET_RG_DAC_I_SET(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_6,_VAL_,16,0xfc00ffff)
+#define SET_RG_DAC_MAN_I_EN(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_6,_VAL_,28,0xefffffff)
+#define SET_RG_WF_RX_ABBCTUNE_TUNE(_VAL_) SET_REG(ADR_RX_RC_VALUE_TUNE,_VAL_,0,0xffffff80)
+#define SET_RG_WF_RX_ABBCTUNE_TUNE_EN(_VAL_) SET_REG(ADR_RX_RC_VALUE_TUNE,_VAL_,8,0xfffffeff)
+#define SET_RG_WF_N_RX_ABBCTUNE_TUNE(_VAL_) SET_REG(ADR_RX_RC_VALUE_TUNE,_VAL_,16,0xff80ffff)
+#define SET_RG_WF_N_RX_ABBCTUNE_TUNE_EN(_VAL_) SET_REG(ADR_RX_RC_VALUE_TUNE,_VAL_,24,0xfeffffff)
+#define SET_RG_RX_IQ_2500_ALPHA(_VAL_) SET_REG(ADR_TRX_IQ_COMP_2G,_VAL_,0,0xffffffe0)
+#define SET_RG_RX_IQ_2500_THETA(_VAL_) SET_REG(ADR_TRX_IQ_COMP_2G,_VAL_,8,0xffffe0ff)
+#define SET_RG_TX_IQ_2500_ALPHA(_VAL_) SET_REG(ADR_TRX_IQ_COMP_2G,_VAL_,16,0xffe0ffff)
+#define SET_RG_TX_IQ_2500_THETA(_VAL_) SET_REG(ADR_TRX_IQ_COMP_2G,_VAL_,24,0xe0ffffff)
+#define SET_RG_RX_IQ_5100_ALPHA(_VAL_) SET_REG(ADR_TRX_IQ_COMP_5G_0,_VAL_,0,0xffffffe0)
+#define SET_RG_RX_IQ_5100_THETA(_VAL_) SET_REG(ADR_TRX_IQ_COMP_5G_0,_VAL_,8,0xffffe0ff)
+#define SET_RG_TX_IQ_5100_ALPHA(_VAL_) SET_REG(ADR_TRX_IQ_COMP_5G_0,_VAL_,16,0xffe0ffff)
+#define SET_RG_TX_IQ_5100_THETA(_VAL_) SET_REG(ADR_TRX_IQ_COMP_5G_0,_VAL_,24,0xe0ffffff)
+#define SET_RG_RX_IQ_5500_ALPHA(_VAL_) SET_REG(ADR_TRX_IQ_COMP_5G_1,_VAL_,0,0xffffffe0)
+#define SET_RG_RX_IQ_5500_THETA(_VAL_) SET_REG(ADR_TRX_IQ_COMP_5G_1,_VAL_,8,0xffffe0ff)
+#define SET_RG_TX_IQ_5500_ALPHA(_VAL_) SET_REG(ADR_TRX_IQ_COMP_5G_1,_VAL_,16,0xffe0ffff)
+#define SET_RG_TX_IQ_5500_THETA(_VAL_) SET_REG(ADR_TRX_IQ_COMP_5G_1,_VAL_,24,0xe0ffffff)
+#define SET_RG_RX_IQ_5700_ALPHA(_VAL_) SET_REG(ADR_TRX_IQ_COMP_5G_2,_VAL_,0,0xffffffe0)
+#define SET_RG_RX_IQ_5700_THETA(_VAL_) SET_REG(ADR_TRX_IQ_COMP_5G_2,_VAL_,8,0xffffe0ff)
+#define SET_RG_TX_IQ_5700_ALPHA(_VAL_) SET_REG(ADR_TRX_IQ_COMP_5G_2,_VAL_,16,0xffe0ffff)
+#define SET_RG_TX_IQ_5700_THETA(_VAL_) SET_REG(ADR_TRX_IQ_COMP_5G_2,_VAL_,24,0xe0ffffff)
+#define SET_RG_RX_IQ_5900_ALPHA(_VAL_) SET_REG(ADR_TRX_IQ_COMP_5G_3,_VAL_,0,0xffffffe0)
+#define SET_RG_RX_IQ_5900_THETA(_VAL_) SET_REG(ADR_TRX_IQ_COMP_5G_3,_VAL_,8,0xffffe0ff)
+#define SET_RG_TX_IQ_5900_ALPHA(_VAL_) SET_REG(ADR_TRX_IQ_COMP_5G_3,_VAL_,16,0xffe0ffff)
+#define SET_RG_TX_IQ_5900_THETA(_VAL_) SET_REG(ADR_TRX_IQ_COMP_5G_3,_VAL_,24,0xe0ffffff)
+#define SET_RG_PHASE_STEP_VALUE(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_0,_VAL_,0,0xffff0000)
+#define SET_RG_PHASE_MANUAL(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_0,_VAL_,16,0xfffeffff)
+#define SET_RG_ALPHA_SEL(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_0,_VAL_,20,0xffcfffff)
+#define SET_RG_SPECTRUM_BW(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_0,_VAL_,24,0xfcffffff)
+#define SET_RG_SPECTRUM_EN(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_0,_VAL_,28,0xefffffff)
+#define SET_RO_WF_DCCAL_DONE(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_1,_VAL_,16,0xfffeffff)
+#define SET_RO_BT_DCCAL_DONE(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_1,_VAL_,17,0xfffdffff)
+#define SET_RO_RCCAL_DONE(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_1,_VAL_,18,0xfffbffff)
+#define SET_RO_TXDC_DONE(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_1,_VAL_,19,0xfff7ffff)
+#define SET_RO_TXIQ_DONE(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_1,_VAL_,20,0xffefffff)
+#define SET_RO_RXIQ_DONE(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_1,_VAL_,21,0xffdfffff)
+#define SET_RO_5G_TXDC_DONE(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_1,_VAL_,22,0xffbfffff)
+#define SET_RO_5G_TXIQ_DONE(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_1,_VAL_,23,0xff7fffff)
+#define SET_RO_5G_RXIQ_DONE(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_1,_VAL_,24,0xfeffffff)
+#define SET_RO_5G_DCCAL_DONE(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_1,_VAL_,25,0xfdffffff)
+#define SET_RO_PRE_DC_DONE(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_1,_VAL_,26,0xfbffffff)
+#define SET_RG_PHASE_17P5M(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_2,_VAL_,0,0xffff0000)
+#define SET_RG_PHASE_2P5M(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_2,_VAL_,16,0x0000ffff)
+#define SET_RG_PHASE_RXIQ_1M(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_3,_VAL_,0,0xffff0000)
+#define SET_RG_PHASE_1M(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_3,_VAL_,16,0x0000ffff)
+#define SET_RG_PHASE_35M(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_4,_VAL_,16,0x0000ffff)
+#define SET_RO_RX_IQ_THETA(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_5,_VAL_,0,0xffffffe0)
+#define SET_RO_RX_IQ_ALPHA(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_5,_VAL_,8,0xffffe0ff)
+#define SET_RO_TX_IQ_THETA(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_5,_VAL_,16,0xffe0ffff)
+#define SET_RO_TX_IQ_ALPHA(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_5,_VAL_,24,0xe0ffffff)
+#define SET_RG_RX_RCCAL_TARG(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_6,_VAL_,0,0xfffffc00)
+#define SET_RG_RX_DC_POLAR_INV(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_6,_VAL_,12,0xffffefff)
+#define SET_RG_RCCAL_POLAR_INV(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_6,_VAL_,13,0xffffdfff)
+#define SET_RG_RX_DC_RESOLUTION(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_6,_VAL_,14,0xffffbfff)
+#define SET_RG_RX_RCCAL_40M_TARG(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_6,_VAL_,16,0xfc00ffff)
+#define SET_RO_SPECTRUM_IQ_PWR_39_32(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_7,_VAL_,0,0xffffff00)
+#define SET_RG_SPECTRUM_LO_FIX(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_7,_VAL_,16,0xfffeffff)
+#define SET_RG_SPECTRUM_PWR_UPDATE(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_7,_VAL_,20,0xffefffff)
+#define SET_RO_SPECTRUM_IQ_PWR_31_0(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_8,_VAL_,0,0x00000000)
+#define SET_RG_PROC_DELAY(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_9,_VAL_,0,0xfffffff8)
+#define SET_RG_PRE_DC_POLA_INV(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_9,_VAL_,4,0xffffffef)
+#define SET_RG_RX_PRE_DC_RESOLUTION(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_9,_VAL_,5,0xffffffdf)
+#define SET_RG_PRE_DC_AUTO(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_9,_VAL_,6,0xffffffbf)
+#define SET_RG_FILTER_AVERAGE_EN(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_9,_VAL_,7,0xffffff7f)
+#define SET_RG_PHASE_RND_EN(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_9,_VAL_,8,0xfffffeff)
+#define SET_RG_RCCAL_DATA_SEL(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_9,_VAL_,9,0xfffffdff)
+#define SET_RG_HS3W_TX_RF_GAIN(_VAL_) SET_REG(ADR_HS3W_CTRL1,_VAL_,0,0xffffff80)
+#define SET_RG_HS3W_PGAGC(_VAL_) SET_REG(ADR_HS3W_CTRL1,_VAL_,8,0xfffff0ff)
+#define SET_RG_HS3W_RFGC(_VAL_) SET_REG(ADR_HS3W_CTRL1,_VAL_,12,0xffffcfff)
+#define SET_RG_HS3W_RXAGC(_VAL_) SET_REG(ADR_HS3W_CTRL1,_VAL_,14,0xffffbfff)
+#define SET_RG_HS3W_RF_PHY_MODE(_VAL_) SET_REG(ADR_HS3W_CTRL1,_VAL_,16,0xfff8ffff)
+#define SET_RG_HS3W_MANUAL(_VAL_) SET_REG(ADR_HS3W_CTRL1,_VAL_,20,0xffefffff)
+#define SET_RG_HS3W_COMM_DATA(_VAL_) SET_REG(ADR_HS3W_CTRL1,_VAL_,24,0xf8ffffff)
+#define SET_RG_HS3W_START_SENT(_VAL_) SET_REG(ADR_HS3W_CTRL1,_VAL_,28,0xefffffff)
+#define SET_RG_HS3W_SX_RFCTRL_CH_INT_10_8(_VAL_) SET_REG(ADR_HS3W_CTRL2,_VAL_,0,0xfffffff8)
+#define SET_RG_HS3W_SX_RFCH_MAP_EN_INT(_VAL_) SET_REG(ADR_HS3W_CTRL2,_VAL_,4,0xffffffef)
+#define SET_RG_HS3W_SX_CHANNEL_INT(_VAL_) SET_REG(ADR_HS3W_CTRL2,_VAL_,11,0xfff807ff)
+#define SET_RG_HS3W_SX_RFCTRL_F_INT(_VAL_) SET_REG(ADR_HS3W_CTRL3,_VAL_,0,0xff000000)
+#define SET_RG_HS3W_SX_RFCTRL_CH_INT_7_0(_VAL_) SET_REG(ADR_HS3W_CTRL3,_VAL_,24,0x00ffffff)
+#define SET_RG_MODE_BY_HS_3WIRE(_VAL_) SET_REG(ADR_RF_D_MODE_CTRL,_VAL_,0,0xfffffffe)
+#define SET_RG_MODE_BY_PHY(_VAL_) SET_REG(ADR_RF_D_MODE_CTRL,_VAL_,4,0xffffffef)
+#define SET_RG_MODE_BY_HWPIN(_VAL_) SET_REG(ADR_RF_D_MODE_CTRL,_VAL_,8,0xfffffeff)
+#define SET_RO_RF_PHY_MODE(_VAL_) SET_REG(ADR_RF_D_MODE_CTRL,_VAL_,16,0xfff8ffff)
+#define SET_RO_HS3W_SX_CHANNEL(_VAL_) SET_REG(ADR_HS3W_READ_OUT_1,_VAL_,0,0xffffff00)
+#define SET_RO_HS3W_SX_RFCH_MAP_EN(_VAL_) SET_REG(ADR_HS3W_READ_OUT_1,_VAL_,8,0xfffffeff)
+#define SET_RO_GAIN_TX(_VAL_) SET_REG(ADR_HS3W_READ_OUT_1,_VAL_,16,0xff80ffff)
+#define SET_RO_ABBPGA(_VAL_) SET_REG(ADR_HS3W_READ_OUT_1,_VAL_,24,0xf0ffffff)
+#define SET_RO_RFPGA(_VAL_) SET_REG(ADR_HS3W_READ_OUT_1,_VAL_,28,0xcfffffff)
+#define SET_RO_DA_RX_AGC(_VAL_) SET_REG(ADR_HS3W_READ_OUT_1,_VAL_,31,0x7fffffff)
+#define SET_RO_HS3W_SX_RFCTRL_CH(_VAL_) SET_REG(ADR_HS3W_READ_OUT_2_,_VAL_,0,0xfffff800)
+#define SET_RO_HS3W_SX_RFCTRL_F(_VAL_) SET_REG(ADR_HS3W_READ_OUT_3,_VAL_,0,0xff000000)
+#define SET_RO_REFREG_KHZ_OUT(_VAL_) SET_REG(ADR_SX_LOCK_FREQ_1,_VAL_,0,0xff800000)
+#define SET_RO_RF_CH_FREQ(_VAL_) SET_REG(ADR_SX_LOCK_FREQ_2,_VAL_,0,0xffffe000)
+#define SET_RO_DC_CAL_Q(_VAL_) SET_REG(ADR_RX_DC_CAL_RESULT,_VAL_,0,0xffffff80)
+#define SET_RO_DC_CAL_I(_VAL_) SET_REG(ADR_RX_DC_CAL_RESULT,_VAL_,16,0xff80ffff)
+#define SET_RG_AUDIO_VOLUME(_VAL_) SET_REG(ADR_AUDIO_CTRL_REG,_VAL_,0,0xfffffc00)
+#define SET_RG_AUDIO_ALPHA(_VAL_) SET_REG(ADR_AUDIO_CTRL_REG,_VAL_,12,0xffffcfff)
+#define SET_RG_AUDIO_FIL_EN(_VAL_) SET_REG(ADR_AUDIO_CTRL_REG,_VAL_,16,0xfffeffff)
+#define SET_RG_IOT_ADC_SIGN_SWAP(_VAL_) SET_REG(ADR_AUDIO_CTRL_REG,_VAL_,24,0xfeffffff)
+#define SET_RG_IOT_ADC_EDGE_SEL(_VAL_) SET_REG(ADR_AUDIO_CTRL_REG,_VAL_,25,0xfdffffff)
+#define SET_RG_BYPASS_AUDIO_LWDF(_VAL_) SET_REG(ADR_AUDIO_CTRL_REG,_VAL_,28,0xefffffff)
+#define SET_RG_PDM_EDGE_SEL(_VAL_) SET_REG(ADR_AUDIO_CTRL_REG,_VAL_,29,0xdfffffff)
+#define SET_RG_AUDIO_TYPE(_VAL_) SET_REG(ADR_AUDIO_CTRL_REG,_VAL_,30,0xbfffffff)
+#define SET_RG_PDM_LOW_LEVEL(_VAL_) SET_REG(ADR_AUDIO_PDM_REG,_VAL_,0,0xffffc000)
+#define SET_RG_PDM_HIGH_LEVEL(_VAL_) SET_REG(ADR_AUDIO_PDM_REG,_VAL_,16,0xc000ffff)
+#define SET_RG_5G_TX_BAND_F1(_VAL_) SET_REG(ADR_RF_5G_TX_PARTITION_BAND1,_VAL_,0,0xffffe000)
+#define SET_RG_5G_TX_BAND_F0(_VAL_) SET_REG(ADR_RF_5G_TX_PARTITION_BAND1,_VAL_,16,0xe000ffff)
+#define SET_RG_5G_TX_BAND_F2(_VAL_) SET_REG(ADR_RF_5G_TX_PARTITION_BAND2,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5100_020_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REG0,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5100_040_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REG0,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5100_060_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REG1,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5100_080_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REG1,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5100_0A0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REG2,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5100_0C0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REG2,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5100_0D0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REG3,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5100_0E0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REG3,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5100_0F0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REG4,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5100_100_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REG4,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5100_110_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REG5,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5100_120_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REG5,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5100_130_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REG6,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5100_140_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REG6,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5100_150_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REG7,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5100_160_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REG7,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5100_170_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REG8,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5100_180_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REG8,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5100_190_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REG9,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5100_1A0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REG9,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5100_1B0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REGA,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5100_1C0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REGA,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5100_1D0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REGB,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5100_1E0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REGB,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5100_1F0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REGC,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5100_200_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REGC,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5100_020_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REG0,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5100_040_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REG0,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5100_060_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REG1,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5100_080_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REG1,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5100_0A0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REG2,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5100_0C0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REG2,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5100_0D0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REG3,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5100_0E0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REG3,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5100_0F0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REG4,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5100_100_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REG4,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5100_110_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REG5,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5100_120_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REG5,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5100_130_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REG6,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5100_140_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REG6,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5100_150_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REG7,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5100_160_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REG7,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5100_170_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REG8,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5100_180_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REG8,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5100_190_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REG9,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5100_1A0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REG9,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5100_1B0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REGA,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5100_1C0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REGA,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5100_1D0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REGB,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5100_1E0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REGB,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5100_1F0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REGC,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5100_200_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REGC,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5500_020_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REG0,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5500_040_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REG0,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5500_060_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REG1,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5500_080_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REG1,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5500_0A0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REG2,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5500_0C0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REG2,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5500_0D0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REG3,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5500_0E0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REG3,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5500_0F0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REG4,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5500_100_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REG4,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5500_110_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REG5,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5500_120_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REG5,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5500_130_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REG6,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5500_140_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REG6,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5500_150_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REG7,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5500_160_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REG7,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5500_170_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REG8,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5500_180_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REG8,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5500_190_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REG9,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5500_1A0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REG9,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5500_1B0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REGA,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5500_1C0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REGA,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5500_1D0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REGB,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5500_1E0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REGB,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5500_1F0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REGC,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5500_200_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REGC,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5500_020_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REG0,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5500_040_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REG0,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5500_060_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REG1,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5500_080_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REG1,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5500_0A0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REG2,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5500_0C0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REG2,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5500_0D0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REG3,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5500_0E0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REG3,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5500_0F0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REG4,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5500_100_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REG4,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5500_110_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REG5,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5500_120_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REG5,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5500_130_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REG6,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5500_140_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REG6,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5500_150_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REG7,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5500_160_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REG7,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5500_170_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REG8,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5500_180_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REG8,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5500_190_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REG9,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5500_1A0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REG9,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5500_1B0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REGA,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5500_1C0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REGA,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5500_1D0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REGB,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5500_1E0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REGB,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5500_1F0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REGC,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5500_200_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REGC,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5700_020_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REG0,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5700_040_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REG0,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5700_060_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REG1,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5700_080_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REG1,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5700_0A0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REG2,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5700_0C0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REG2,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5700_0D0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REG3,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5700_0E0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REG3,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5700_0F0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REG4,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5700_100_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REG4,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5700_110_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REG5,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5700_120_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REG5,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5700_130_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REG6,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5700_140_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REG6,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5700_150_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REG7,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5700_160_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REG7,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5700_170_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REG8,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5700_180_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REG8,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5700_190_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REG9,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5700_1A0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REG9,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5700_1B0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REGA,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5700_1C0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REGA,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5700_1D0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REGB,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5700_1E0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REGB,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5700_1F0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REGC,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5700_200_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REGC,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5700_020_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REG0,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5700_040_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REG0,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5700_060_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REG1,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5700_080_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REG1,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5700_0A0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REG2,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5700_0C0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REG2,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5700_0D0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REG3,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5700_0E0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REG3,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5700_0F0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REG4,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5700_100_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REG4,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5700_110_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REG5,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5700_120_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REG5,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5700_130_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REG6,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5700_140_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REG6,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5700_150_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REG7,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5700_160_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REG7,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5700_170_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REG8,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5700_180_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REG8,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5700_190_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REG9,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5700_1A0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REG9,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5700_1B0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REGA,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5700_1C0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REGA,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5700_1D0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REGB,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5700_1E0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REGB,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5700_1F0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REGC,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5700_200_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REGC,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5900_020_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REG0,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5900_040_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REG0,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5900_060_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REG1,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5900_080_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REG1,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5900_0A0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REG2,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5900_0C0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REG2,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5900_0D0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REG3,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5900_0E0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REG3,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5900_0F0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REG4,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5900_100_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REG4,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5900_110_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REG5,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5900_120_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REG5,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5900_130_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REG6,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5900_140_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REG6,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5900_150_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REG7,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5900_160_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REG7,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5900_170_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REG8,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5900_180_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REG8,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5900_190_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REG9,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5900_1A0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REG9,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5900_1B0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REGA,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5900_1C0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REGA,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5900_1D0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REGB,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5900_1E0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REGB,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5900_1F0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REGC,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_5900_200_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REGC,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_5900_020_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REG0,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5900_040_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REG0,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5900_060_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REG1,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5900_080_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REG1,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5900_0A0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REG2,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5900_0C0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REG2,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5900_0D0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REG3,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5900_0E0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REG3,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5900_0F0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REG4,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5900_100_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REG4,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5900_110_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REG5,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5900_120_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REG5,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5900_130_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REG6,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5900_140_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REG6,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5900_150_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REG7,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5900_160_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REG7,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5900_170_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REG8,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5900_180_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REG8,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5900_190_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REG9,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5900_1A0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REG9,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5900_1B0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REGA,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5900_1C0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REGA,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5900_1D0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REGB,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5900_1E0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REGB,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_5900_1F0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REGC,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_5900_200_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REGC,_VAL_,16,0xe000ffff)
+#define SET_RG_TONE_SEL(_VAL_) SET_REG(ADR_WIFI_PADPD_CAL_TONEGEN_REG,_VAL_,0,0xfffffffc)
+#define SET_RG_TONE_1_RATE(_VAL_) SET_REG(ADR_WIFI_PADPD_CAL_TONEGEN_REG,_VAL_,16,0x0000ffff)
+#define SET_RG_RX_PADPD_EN(_VAL_) SET_REG(ADR_WIFI_PADPD_CAL_RX_PADPD_REG,_VAL_,0,0xfffffffe)
+#define SET_RG_RX_PADPD_LEAKY_FACTOR(_VAL_) SET_REG(ADR_WIFI_PADPD_CAL_RX_PADPD_REG,_VAL_,4,0xffffff8f)
+#define SET_RG_RX_PADPD_LATCH(_VAL_) SET_REG(ADR_WIFI_PADPD_CAL_RX_PADPD_REG,_VAL_,8,0xfffffeff)
+#define SET_RG_RX_PADPD_DATA_SEL(_VAL_) SET_REG(ADR_WIFI_PADPD_CAL_RX_PADPD_REG,_VAL_,12,0xffffefff)
+#define SET_RG_RX_PADPD_TONE_SEL(_VAL_) SET_REG(ADR_WIFI_PADPD_CAL_RX_PADPD_REG,_VAL_,13,0xffffdfff)
+#define SET_RG_RX_PADPD_RATE(_VAL_) SET_REG(ADR_WIFI_PADPD_CAL_RX_PADPD_REG,_VAL_,16,0x0000ffff)
+#define SET_RO_RX_PHI(_VAL_) SET_REG(ADR_WIFI_PADPD_CAL_RX_RO,_VAL_,0,0xffffe000)
+#define SET_RO_RX_AMP(_VAL_) SET_REG(ADR_WIFI_PADPD_CAL_RX_RO,_VAL_,16,0xfe00ffff)
+#define SET_RG_CFR_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_CFR,_VAL_,0,0xfffffc00)
+#define SET_RG_CFR_PEAK(_VAL_) SET_REG(ADR_WIFI_PADPD_CFR,_VAL_,16,0xfc00ffff)
+#define SET_RG_CFR_EN(_VAL_) SET_REG(ADR_WIFI_PADPD_CFR,_VAL_,31,0x7fffffff)
+#define SET_RG_RX_PADPD_DC_RM_LEAKY_FACTOR(_VAL_) SET_REG(ADR_WIFI_PADPD_DC_RM,_VAL_,0,0xfffffff8)
+#define SET_RG_RX_PADPD_DC_RM_BYP(_VAL_) SET_REG(ADR_WIFI_PADPD_DC_RM,_VAL_,4,0xffffffef)
+#define SET_RG_TXIQ_CLP_THD_I(_VAL_) SET_REG(ADR_WIFI_PADPD_TXIQ_CLIP_REG,_VAL_,0,0xfffffc00)
+#define SET_RG_TXIQ_CLP_THD_Q(_VAL_) SET_REG(ADR_WIFI_PADPD_TXIQ_CLIP_REG,_VAL_,16,0xfc00ffff)
+#define SET_RG_TX_SCALE(_VAL_) SET_REG(ADR_WIFI_PADPD_TXIQ_CONTROL_REG,_VAL_,0,0xffffff00)
+#define SET_RG_TX_IQ_SWP(_VAL_) SET_REG(ADR_WIFI_PADPD_TXIQ_CONTROL_REG,_VAL_,16,0xfffeffff)
+#define SET_RG_TX_BB_SCALE_MANUAL(_VAL_) SET_REG(ADR_WIFI_PADPD_TXIQ_CONTROL_REG,_VAL_,20,0xffefffff)
+#define SET_RG_TX_IQ_SRC(_VAL_) SET_REG(ADR_WIFI_PADPD_TXIQ_CONTROL_REG,_VAL_,24,0xfcffffff)
+#define SET_RG_TX_I_DC(_VAL_) SET_REG(ADR_WIFI_PADPD_TXIQ_DPD_DC_REG,_VAL_,0,0xfffffc00)
+#define SET_RG_TX_Q_DC(_VAL_) SET_REG(ADR_WIFI_PADPD_TXIQ_DPD_DC_REG,_VAL_,16,0xfc00ffff)
+#define SET_RG_TX_I_OFFSET(_VAL_) SET_REG(ADR_WIFI_PADPD_TXIQ_DC_OFFSET_REG,_VAL_,16,0xff00ffff)
+#define SET_RG_TX_Q_OFFSET(_VAL_) SET_REG(ADR_WIFI_PADPD_TXIQ_DC_OFFSET_REG,_VAL_,24,0x00ffffff)
+#define SET_RG_DPD_AM_EN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_CONTROL_REG,_VAL_,0,0xfffffffe)
+#define SET_RG_DPD_PM_EN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_CONTROL_REG,_VAL_,1,0xfffffffd)
+#define SET_RG_DPD_PM_AMSEL(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_CONTROL_REG,_VAL_,2,0xfffffffb)
+#define SET_RG_DPD_020_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REG0,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_040_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REG0,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_060_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REG1,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_080_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REG1,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_0A0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REG2,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_0C0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REG2,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_0D0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REG3,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_0E0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REG3,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_0F0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REG4,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_100_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REG4,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_110_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REG5,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_120_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REG5,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_130_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REG6,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_140_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REG6,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_150_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REG7,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_160_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REG7,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_170_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REG8,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_180_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REG8,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_190_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REG9,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_1A0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REG9,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_1B0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REGA,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_1C0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REGA,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_1D0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REGB,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_1E0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REGB,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_1F0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REGC,_VAL_,0,0xfffffc00)
+#define SET_RG_DPD_200_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REGC,_VAL_,16,0xfc00ffff)
+#define SET_RG_DPD_020_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REG0,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_040_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REG0,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_060_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REG1,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_080_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REG1,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_0A0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REG2,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_0C0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REG2,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_0D0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REG3,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_0E0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REG3,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_0F0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REG4,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_100_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REG4,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_110_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REG5,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_120_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REG5,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_130_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REG6,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_140_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REG6,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_150_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REG7,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_160_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REG7,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_170_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REG8,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_180_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REG8,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_190_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REG9,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_1A0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REG9,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_1B0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REGA,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_1C0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REGA,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_1D0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REGB,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_1E0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REGB,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_1F0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REGC,_VAL_,0,0xffffe000)
+#define SET_RG_DPD_200_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REGC,_VAL_,16,0xe000ffff)
+#define SET_RG_DPD_BB_SCALE_5900(_VAL_) SET_REG(ADR_WIFI_PADPD_5G_BB_GAIN_REG,_VAL_,0,0xffffff00)
+#define SET_RG_DPD_BB_SCALE_5700(_VAL_) SET_REG(ADR_WIFI_PADPD_5G_BB_GAIN_REG,_VAL_,8,0xffff00ff)
+#define SET_RG_DPD_BB_SCALE_5500(_VAL_) SET_REG(ADR_WIFI_PADPD_5G_BB_GAIN_REG,_VAL_,16,0xff00ffff)
+#define SET_RG_DPD_BB_SCALE_5100(_VAL_) SET_REG(ADR_WIFI_PADPD_5G_BB_GAIN_REG,_VAL_,24,0x00ffffff)
+#define SET_RG_DPD_BB_SCALE_2500(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_BB_GAIN_REG,_VAL_,0,0xffffff00)
+#define SET_RG_TX_SCALE_11B(_VAL_) SET_REG(ADR_WIFI_PADPD_TX_GAIN_0P5DB_REG,_VAL_,0,0xffffff00)
+#define SET_RG_TX_SCALE_11B_P0D5(_VAL_) SET_REG(ADR_WIFI_PADPD_TX_GAIN_0P5DB_REG,_VAL_,8,0xffff00ff)
+#define SET_RG_TX_SCALE_11G(_VAL_) SET_REG(ADR_WIFI_PADPD_TX_GAIN_0P5DB_REG,_VAL_,16,0xff00ffff)
+#define SET_RG_TX_SCALE_11G_P0D5(_VAL_) SET_REG(ADR_WIFI_PADPD_TX_GAIN_0P5DB_REG,_VAL_,24,0x00ffffff)
+#define SET_RG_HS5W_M_MD_EN(_VAL_) SET_REG(ADR_HS5W_MD_EN,_VAL_,0,0xfffffffe)
+#define SET_RG_HS5W_M_MAN(_VAL_) SET_REG(ADR_HS5W_MAN,_VAL_,0,0xfffffffe)
+#define SET_RG_HS5W_M_CMD6_EN(_VAL_) SET_REG(ADR_HS5W_MAN,_VAL_,25,0xfdffffff)
+#define SET_RG_HS5W_M_CMD5_EN(_VAL_) SET_REG(ADR_HS5W_MAN,_VAL_,26,0xfbffffff)
+#define SET_RG_HS5W_M_CMD4_EN(_VAL_) SET_REG(ADR_HS5W_MAN,_VAL_,27,0xf7ffffff)
+#define SET_RG_HS5W_M_CMD3_EN(_VAL_) SET_REG(ADR_HS5W_MAN,_VAL_,28,0xefffffff)
+#define SET_RG_HS5W_M_CMD2_EN(_VAL_) SET_REG(ADR_HS5W_MAN,_VAL_,29,0xdfffffff)
+#define SET_RG_HS5W_M_CMD1_EN(_VAL_) SET_REG(ADR_HS5W_MAN,_VAL_,30,0xbfffffff)
+#define SET_RG_HS5W_M_CMD0_EN(_VAL_) SET_REG(ADR_HS5W_MAN,_VAL_,31,0x7fffffff)
+#define SET_RG_HS5W_M_RF_PHY_MODE(_VAL_) SET_REG(ADR_HS5W_MAN_SET_ADD0,_VAL_,0,0xfffffff8)
+#define SET_RG_HS5W_M_CAL_INDEX(_VAL_) SET_REG(ADR_HS5W_MAN_SET_ADD1,_VAL_,0,0xffffffe0)
+#define SET_RG_HS5W_M_PGAGC(_VAL_) SET_REG(ADR_HS5W_MAN_SET_ADD2,_VAL_,0,0xfffffff0)
+#define SET_RG_HS5W_M_RFGC(_VAL_) SET_REG(ADR_HS5W_MAN_SET_ADD2,_VAL_,4,0xffffffcf)
+#define SET_RG_HS5W_M_TXPWRLVL(_VAL_) SET_REG(ADR_HS5W_MAN_SET_ADD3,_VAL_,0,0xffffffc0)
+#define SET_RG_HS5W_M_SX_RFCTRL_CH(_VAL_) SET_REG(ADR_HS5W_MAN_SET_ADD4_CH,_VAL_,0,0xfffff800)
+#define SET_RG_HS5W_M_SX5GB_RFCTRL_CH(_VAL_) SET_REG(ADR_HS5W_MAN_SET_ADD4_CH_5GB,_VAL_,0,0xfffff800)
+#define SET_RG_HS5W_M_SX_RFCTRL_F(_VAL_) SET_REG(ADR_HS5W_MAN_SET_ADD4_F,_VAL_,0,0xff000000)
+#define SET_RG_HS5W_M_SX_RFCH_MAP_EN(_VAL_) SET_REG(ADR_HS5W_MAN_SET_ADD4_F,_VAL_,31,0x7fffffff)
+#define SET_RG_HS5W_M_SX5GB_RFCTRL_F(_VAL_) SET_REG(ADR_HS5W_MAN_SET_ADD4_F_5GB,_VAL_,0,0xff000000)
+#define SET_RG_HS5W_M_SX5GB_RFCH_MAP_EN(_VAL_) SET_REG(ADR_HS5W_MAN_SET_ADD4_F_5GB,_VAL_,31,0x7fffffff)
+#define SET_RG_HS5W_M_SX_CHANNEL(_VAL_) SET_REG(ADR_HS5W_MAN_SET_ADD5,_VAL_,0,0xffffff00)
+#define SET_RG_HS5W_M_SX5GB_CHANNEL(_VAL_) SET_REG(ADR_HS5W_MAN_SET_ADD5_5GB,_VAL_,0,0xffffff00)
+#define SET_RG_HS5W_M_PHY_BW(_VAL_) SET_REG(ADR_HS5W_MAN_SET_ADD6,_VAL_,0,0xfffffffc)
+#define SET_RG_RESERVED_DPD(_VAL_) SET_REG(ADR_WIFI_PADPD_RESERVED_REG,_VAL_,0,0x00000000)
+#define SET_RG_XO_LDO_LEVEL(_VAL_) SET_REG(ADR_PMU_REG_1,_VAL_,0,0xfffffff8)
+#define SET_RG_EN_LDO_XO_IQUP(_VAL_) SET_REG(ADR_PMU_REG_1,_VAL_,4,0xffffffef)
+#define SET_RG_EN_LDO_XO_BYP(_VAL_) SET_REG(ADR_PMU_REG_1,_VAL_,5,0xffffffdf)
+#define SET_RG_EN_DLDO_BYP(_VAL_) SET_REG(ADR_PMU_REG_1,_VAL_,6,0xffffffbf)
+#define SET_RG_EN_DLDO_HALF_IQ(_VAL_) SET_REG(ADR_PMU_REG_1,_VAL_,7,0xffffff7f)
+#define SET_RG_XO_CBANKI(_VAL_) SET_REG(ADR_PMU_REG_1,_VAL_,8,0xfffe00ff)
+#define SET_RG_XO_CBANKO(_VAL_) SET_REG(ADR_PMU_REG_1,_VAL_,17,0xfc01ffff)
+#define SET_RG_EN_FDB(_VAL_) SET_REG(ADR_PMU_REG_1,_VAL_,26,0xfbffffff)
+#define SET_RG_FDB_BYPASS(_VAL_) SET_REG(ADR_PMU_REG_1,_VAL_,27,0xf7ffffff)
+#define SET_RG_FDB_DUTY_LTH(_VAL_) SET_REG(ADR_PMU_REG_1,_VAL_,28,0xcfffffff)
+#define SET_RG_EN_XOTEST(_VAL_) SET_REG(ADR_PMU_REG_1,_VAL_,30,0xbfffffff)
+#define SET_RG_HW_WAKE_XOSC(_VAL_) SET_REG(ADR_PMU_REG_1,_VAL_,31,0x7fffffff)
+#define SET_RG_EN_FDB_DCC_MUAL(_VAL_) SET_REG(ADR_PMU_REG_2,_VAL_,0,0xfffffffe)
+#define SET_RG_EN_FDB_DELAYC_MUAL(_VAL_) SET_REG(ADR_PMU_REG_2,_VAL_,1,0xfffffffd)
+#define SET_RG_EN_FDB_DELAYF_MUAL(_VAL_) SET_REG(ADR_PMU_REG_2,_VAL_,2,0xfffffffb)
+#define SET_RG_EN_FDB_PHASESWAP_MUAL(_VAL_) SET_REG(ADR_PMU_REG_2,_VAL_,3,0xfffffff7)
+#define SET_RG_FDB_PHASESWAP_MUAL(_VAL_) SET_REG(ADR_PMU_REG_2,_VAL_,4,0xffffffef)
+#define SET_RG_CLOCK_BF_MUAL(_VAL_) SET_REG(ADR_PMU_REG_2,_VAL_,5,0xffffffdf)
+#define SET_RG_FDB_CDELAY_MUAL(_VAL_) SET_REG(ADR_PMU_REG_2,_VAL_,8,0xfffff0ff)
+#define SET_RG_FDB_FDELAY_MUAL(_VAL_) SET_REG(ADR_PMU_REG_2,_VAL_,12,0xffff0fff)
+#define SET_RG_XO_TIMMER(_VAL_) SET_REG(ADR_PMU_REG_2,_VAL_,16,0xffc0ffff)
+#define SET_RG_DPL_SETTLING_TIMMER(_VAL_) SET_REG(ADR_PMU_REG_2,_VAL_,22,0xff3fffff)
+#define SET_RG_FDB_RDELAYF(_VAL_) SET_REG(ADR_PMU_REG_2,_VAL_,24,0xfcffffff)
+#define SET_RG_FDB_RDELAYS(_VAL_) SET_REG(ADR_PMU_REG_2,_VAL_,26,0xf3ffffff)
+#define SET_RG_FDB_RECAL_TIMMER(_VAL_) SET_REG(ADR_PMU_REG_2,_VAL_,28,0xcfffffff)
+#define SET_RG_EN_FDB_RECAL(_VAL_) SET_REG(ADR_PMU_REG_2,_VAL_,30,0xbfffffff)
+#define SET_RG_LOAD_RFTABLE_RDY(_VAL_) SET_REG(ADR_PMU_REG_2,_VAL_,31,0x7fffffff)
+#define SET_RG_DCDC_MODE(_VAL_) SET_REG(ADR_PMU_REG_3,_VAL_,0,0xfffffffe)
+#define SET_RG_DLDO_LEVEL(_VAL_) SET_REG(ADR_PMU_REG_3,_VAL_,1,0xfffffff1)
+#define SET_RG_BUCK_LEVEL(_VAL_) SET_REG(ADR_PMU_REG_3,_VAL_,4,0xffffff0f)
+#define SET_RG_DLDO_BOOST_IQ(_VAL_) SET_REG(ADR_PMU_REG_3,_VAL_,8,0xfffffeff)
+#define SET_RG_BUCK_EN_PSM(_VAL_) SET_REG(ADR_PMU_REG_3,_VAL_,9,0xfffffdff)
+#define SET_RG_BUCK_PSM_VTH(_VAL_) SET_REG(ADR_PMU_REG_3,_VAL_,10,0xfffffbff)
+#define SET_RG_BUCK_VREF_SEL(_VAL_) SET_REG(ADR_PMU_REG_3,_VAL_,11,0xfffff7ff)
+#define SET_RG_LDO_LEVEL_EFUSE(_VAL_) SET_REG(ADR_PMU_REG_3,_VAL_,12,0xffff8fff)
+#define SET_RG_EN_LDO_EFUSE(_VAL_) SET_REG(ADR_PMU_REG_3,_VAL_,16,0xfffeffff)
+#define SET_RG_DCDC_PULLLOW_CON(_VAL_) SET_REG(ADR_PMU_REG_3,_VAL_,18,0xfffbffff)
+#define SET_RG_DCDC_RES2_CON(_VAL_) SET_REG(ADR_PMU_REG_3,_VAL_,19,0xfff7ffff)
+#define SET_RG_DCDC_RES_CON(_VAL_) SET_REG(ADR_PMU_REG_3,_VAL_,20,0xffefffff)
+#define SET_RG_RTC_RS1(_VAL_) SET_REG(ADR_PMU_REG_3,_VAL_,21,0xffdfffff)
+#define SET_RG_RTC_RS2(_VAL_) SET_REG(ADR_PMU_REG_3,_VAL_,22,0xffbfffff)
+#define SET_RG_DCDC_CLK(_VAL_) SET_REG(ADR_PMU_REG_3,_VAL_,24,0xf0ffffff)
+#define SET_RG_BUCK_RCZERO(_VAL_) SET_REG(ADR_PMU_REG_3,_VAL_,28,0xefffffff)
+#define SET_RG_BUCK_SLOP(_VAL_) SET_REG(ADR_PMU_REG_3,_VAL_,29,0x9fffffff)
+#define SET_RG_RTC_OFFSET(_VAL_) SET_REG(ADR_PMU_REG_4,_VAL_,0,0xffffff00)
+#define SET_RG_RTC_CAL_TARGET_COUNT(_VAL_) SET_REG(ADR_PMU_REG_4,_VAL_,8,0xfff000ff)
+#define SET_RG_RTC_OSC_RES_SW_MANUAL(_VAL_) SET_REG(ADR_PMU_REG_4,_VAL_,20,0xc00fffff)
+#define SET_RG_RTC_CAL_MODE(_VAL_) SET_REG(ADR_PMU_REG_4,_VAL_,30,0xbfffffff)
+#define SET_RG_SEL_DPLL_CLK(_VAL_) SET_REG(ADR_PMU_REG_4,_VAL_,31,0x7fffffff)
+#define SET_RG_RTC_OSC_RES_SW_MANUAL_EN(_VAL_) SET_REG(ADR_PMU_REG_5,_VAL_,0,0xfffffffe)
+#define SET_RG_EN_RTC_CAL(_VAL_) SET_REG(ADR_PMU_REG_5,_VAL_,1,0xfffffffd)
+#define SET_RO_FDB_CDELAY(_VAL_) SET_REG(ADR_PMU_REG_6,_VAL_,0,0xfffffff0)
+#define SET_RO_FDB_FDELAY(_VAL_) SET_REG(ADR_PMU_REG_6,_VAL_,4,0xffffff0f)
+#define SET_RO_FDB_PHASESWAP(_VAL_) SET_REG(ADR_PMU_REG_6,_VAL_,8,0xfffffeff)
+#define SET_RO_XO_RDY(_VAL_) SET_REG(ADR_PMU_REG_6,_VAL_,9,0xfffffdff)
+#define SET_RO_RTC_OSC_CAL_RES_RDY(_VAL_) SET_REG(ADR_PMU_REG_6,_VAL_,10,0xfffffbff)
+#define SET_RO_RTC_OSC_RES_SW(_VAL_) SET_REG(ADR_PMU_REG_6,_VAL_,11,0xffe007ff)
+#define SET_RG_PMU_ENTER_SLEEP_MODE(_VAL_) SET_REG(ADR_PMU_SLEEP_REG_1,_VAL_,0,0xfffffffe)
+#define SET_RG_SLEEP_METHOD(_VAL_) SET_REG(ADR_PMU_SLEEP_REG_1,_VAL_,1,0xfffffffd)
+#define SET_RG_INT_PMU_MASK(_VAL_) SET_REG(ADR_PMU_SLEEP_REG_1,_VAL_,2,0xfffffffb)
+#define SET_RG_SLEEP_WAKE_CNT(_VAL_) SET_REG(ADR_PMU_SLEEP_REG_2,_VAL_,0,0x00000000)
+#define SET_RG_SEC_CNT_VALUE(_VAL_) SET_REG(ADR_PMU_RTC_REG_0,_VAL_,0,0xffff8000)
+#define SET_RG_RTC_EN(_VAL_) SET_REG(ADR_PMU_RTC_REG_0,_VAL_,15,0xffff7fff)
+#define SET_RO_RTC_TICK_CNT(_VAL_) SET_REG(ADR_PMU_RTC_REG_0,_VAL_,16,0x8000ffff)
+#define SET_RG_RTC_INT_SEC_MASK(_VAL_) SET_REG(ADR_PMU_RTC_REG_1,_VAL_,0,0xfffffffe)
+#define SET_RG_RTC_INT_ALARM_MASK(_VAL_) SET_REG(ADR_PMU_RTC_REG_1,_VAL_,1,0xfffffffd)
+#define SET_RO_PMU_WAKE_TRIG_EVENT(_VAL_) SET_REG(ADR_PMU_RTC_REG_1,_VAL_,12,0xffff8fff)
+#define SET_RO_RTC_INT_SEC(_VAL_) SET_REG(ADR_PMU_RTC_REG_1,_VAL_,16,0xfffeffff)
+#define SET_RO_RTC_INT_ALARM(_VAL_) SET_REG(ADR_PMU_RTC_REG_1,_VAL_,17,0xfffdffff)
+#define SET_RG_RTC_SEC_START_CNT(_VAL_) SET_REG(ADR_PMU_RTC_REG_2,_VAL_,0,0x00000000)
+#define SET_RG_RTC_SEC_ALARM_VALUE(_VAL_) SET_REG(ADR_PMU_RTC_REG_3,_VAL_,0,0x00000000)
+#define SET_RG_FPGA_CLK_REF_40M_EN(_VAL_) SET_REG(ADR_PMU_CTRL_REG,_VAL_,0,0xfffffffe)
+#define SET_RG_CLK_RTC_SW(_VAL_) SET_REG(ADR_PMU_CTRL_REG,_VAL_,1,0xfffffffd)
+#define SET_RG_PHY_RST_N(_VAL_) SET_REG(ADR_PMU_CTRL_REG,_VAL_,4,0xffffffef)
+#define SET_RO_PMU_STATE(_VAL_) SET_REG(ADR_PMU_STATE_REG,_VAL_,0,0xfffffff8)
+#define SET_RO_AD_VBAT_OK(_VAL_) SET_REG(ADR_PMU_STATE_REG,_VAL_,4,0xffffffef)
+#define SET_RG_DP_LDO_LEVEL(_VAL_) SET_REG(ADR_PMU_DPLL_REG_0,_VAL_,0,0xfffffff8)
+#define SET_RG_EN_LDO_DP_BYP(_VAL_) SET_REG(ADR_PMU_DPLL_REG_0,_VAL_,3,0xfffffff7)
+#define SET_RG_DP_AUTOMAP_EN(_VAL_) SET_REG(ADR_PMU_DPLL_REG_0,_VAL_,5,0xffffffdf)
+#define SET_RG_EN_ADC_320M(_VAL_) SET_REG(ADR_PMU_DPLL_REG_0,_VAL_,7,0xffffff7f)
+#define SET_RG_EN_IOTADC_160M(_VAL_) SET_REG(ADR_PMU_DPLL_REG_0,_VAL_,8,0xfffffeff)
+#define SET_RG_EN_MAC_80M(_VAL_) SET_REG(ADR_PMU_DPLL_REG_0,_VAL_,9,0xfffffdff)
+#define SET_RG_EN_MAC_96M(_VAL_) SET_REG(ADR_PMU_DPLL_REG_0,_VAL_,10,0xfffffbff)
+#define SET_RG_EN_MAC_120M(_VAL_) SET_REG(ADR_PMU_DPLL_REG_0,_VAL_,11,0xfffff7ff)
+#define SET_RG_EN_PHY_80M(_VAL_) SET_REG(ADR_PMU_DPLL_REG_0,_VAL_,12,0xffffefff)
+#define SET_RG_EN_PHY_160M(_VAL_) SET_REG(ADR_PMU_DPLL_REG_0,_VAL_,13,0xffffdfff)
+#define SET_RG_EN_PHY_320M(_VAL_) SET_REG(ADR_PMU_DPLL_REG_0,_VAL_,14,0xffffbfff)
+#define SET_RG_EN_MAC_160M(_VAL_) SET_REG(ADR_PMU_DPLL_REG_0,_VAL_,15,0xffff7fff)
+#define SET_RG_DP_XTAL_FREQ(_VAL_) SET_REG(ADR_PMU_DPLL_REG_0,_VAL_,16,0xfff0ffff)
+#define SET_RG_DP_BBPLL_PD(_VAL_) SET_REG(ADR_PMU_DPLL_REG_1,_VAL_,0,0xfffffffe)
+#define SET_RG_DP_BBPLL_BP(_VAL_) SET_REG(ADR_PMU_DPLL_REG_1,_VAL_,1,0xfffffffd)
+#define SET_RG_EN_DP_MANUAL(_VAL_) SET_REG(ADR_PMU_DPLL_REG_1,_VAL_,2,0xfffffffb)
+#define SET_RG_DP_FREF_DOUB(_VAL_) SET_REG(ADR_PMU_DPLL_REG_1,_VAL_,3,0xfffffff7)
+#define SET_RG_DP_DAC320_DIVBY2(_VAL_) SET_REG(ADR_PMU_DPLL_REG_1,_VAL_,4,0xffffffef)
+#define SET_RG_DP_ADC320_DIVBY2_BT(_VAL_) SET_REG(ADR_PMU_DPLL_REG_1,_VAL_,5,0xffffffdf)
+#define SET_RG_DP_ADC320_DIVBY2_WF(_VAL_) SET_REG(ADR_PMU_DPLL_REG_1,_VAL_,6,0xffffffbf)
+#define SET_RG_EN_DPL_MOD(_VAL_) SET_REG(ADR_PMU_DPLL_REG_1,_VAL_,8,0xfffffeff)
+#define SET_RG_DPL_MOD_ORDER(_VAL_) SET_REG(ADR_PMU_DPLL_REG_1,_VAL_,9,0xfffff9ff)
+#define SET_RG_DP_REFDIV(_VAL_) SET_REG(ADR_PMU_DPLL_REG_1,_VAL_,11,0xfffc07ff)
+#define SET_RG_DP_FODIV(_VAL_) SET_REG(ADR_PMU_DPLL_REG_1,_VAL_,18,0xfe03ffff)
+#define SET_RG_EN_LDO_DP_IQUP(_VAL_) SET_REG(ADR_PMU_DPLL_REG_1,_VAL_,26,0xfbffffff)
+#define SET_RG_DP_OD_TEST(_VAL_) SET_REG(ADR_PMU_DPLL_REG_1,_VAL_,27,0xf7ffffff)
+#define SET_RG_DP_BBPLL_TESTSEL(_VAL_) SET_REG(ADR_PMU_DPLL_REG_1,_VAL_,28,0x8fffffff)
+#define SET_RG_DP_BBPLL_ICP(_VAL_) SET_REG(ADR_PMU_DPLL_REG_2,_VAL_,0,0xfffffffc)
+#define SET_RG_DP_BBPLL_IDUAL(_VAL_) SET_REG(ADR_PMU_DPLL_REG_2,_VAL_,2,0xfffffff3)
+#define SET_RG_DP_CP_IOSTPOL(_VAL_) SET_REG(ADR_PMU_DPLL_REG_2,_VAL_,4,0xffffffef)
+#define SET_RG_DP_CP_IOST(_VAL_) SET_REG(ADR_PMU_DPLL_REG_2,_VAL_,5,0xffffff9f)
+#define SET_RG_DP_PFD_PFDSEL(_VAL_) SET_REG(ADR_PMU_DPLL_REG_2,_VAL_,7,0xffffff7f)
+#define SET_RG_DP_BBPLL_PFD_DLY(_VAL_) SET_REG(ADR_PMU_DPLL_REG_2,_VAL_,8,0xfffffcff)
+#define SET_RG_DP_RP(_VAL_) SET_REG(ADR_PMU_DPLL_REG_2,_VAL_,11,0xffffc7ff)
+#define SET_RG_DP_RHP(_VAL_) SET_REG(ADR_PMU_DPLL_REG_2,_VAL_,14,0xffff3fff)
+#define SET_RG_EN_DP_VT_MON(_VAL_) SET_REG(ADR_PMU_DPLL_REG_2,_VAL_,17,0xfffdffff)
+#define SET_RG_DP_VT_TH_HI(_VAL_) SET_REG(ADR_PMU_DPLL_REG_2,_VAL_,18,0xfff3ffff)
+#define SET_RG_DP_VT_TH_LO(_VAL_) SET_REG(ADR_PMU_DPLL_REG_2,_VAL_,20,0xffcfffff)
+#define SET_RG_DP_BBPLL_BS(_VAL_) SET_REG(ADR_PMU_DPLL_REG_2,_VAL_,23,0xe07fffff)
+#define SET_RG_DP_BBPLL_SDM_EDGE(_VAL_) SET_REG(ADR_PMU_DPLL_REG_2,_VAL_,31,0x7fffffff)
+#define SET_RG_DPL_RFCTRL_F(_VAL_) SET_REG(ADR_PMU_DPLL_REG_3,_VAL_,0,0xff000000)
+#define SET_RG_DPL_RFCTRL_CH(_VAL_) SET_REG(ADR_PMU_DPLL_REG_3,_VAL_,24,0x00ffffff)
+#define SET_RG_DCDC_MODE_SLP(_VAL_) SET_REG(ADR_PMU_SLEEP_MODE_REG,_VAL_,0,0xfffffffe)
+#define SET_RG_DLDO_LEVEL_SLP(_VAL_) SET_REG(ADR_PMU_SLEEP_MODE_REG,_VAL_,1,0xfffffff1)
+#define SET_RG_BUCK_LEVEL_SLP(_VAL_) SET_REG(ADR_PMU_SLEEP_MODE_REG,_VAL_,4,0xffffff0f)
+#define SET_RG_XO_CBANKI_SLP(_VAL_) SET_REG(ADR_PMU_SLEEP_MODE_REG,_VAL_,8,0xfffe00ff)
+#define SET_RG_XO_CBANKO_SLP(_VAL_) SET_REG(ADR_PMU_SLEEP_MODE_REG,_VAL_,17,0xfc01ffff)
+#define SET_RG_EN_DLDO_HALF_IQ_SLP(_VAL_) SET_REG(ADR_PMU_SLEEP_MODE_REG,_VAL_,26,0xfbffffff)
+#define SET_RG_EN_DLDO_BYP_AUTO(_VAL_) SET_REG(ADR_PMU_SLEEP_MODE_REG,_VAL_,27,0xf7ffffff)
+#define SET_RG_HW_WAKE_XOSC_SLP(_VAL_) SET_REG(ADR_PMU_SLEEP_MODE_REG,_VAL_,31,0x7fffffff)
+#define SET_RG_RAM_00(_VAL_) SET_REG(ADR_PMU_RAM_00,_VAL_,0,0x00000000)
+#define SET_RG_RAM_01(_VAL_) SET_REG(ADR_PMU_RAM_01,_VAL_,0,0x00000000)
+#define SET_RG_RAM_02(_VAL_) SET_REG(ADR_PMU_RAM_02,_VAL_,0,0x00000000)
+#define SET_RG_RAM_03(_VAL_) SET_REG(ADR_PMU_RAM_03,_VAL_,0,0x00000000)
+#define SET_RG_RAM_04(_VAL_) SET_REG(ADR_PMU_RAM_04,_VAL_,0,0x00000000)
+#define SET_RG_RAM_05(_VAL_) SET_REG(ADR_PMU_RAM_05,_VAL_,0,0x00000000)
+#define SET_RG_RAM_06(_VAL_) SET_REG(ADR_PMU_RAM_06,_VAL_,0,0x00000000)
+#define SET_RG_RAM_07(_VAL_) SET_REG(ADR_PMU_RAM_07,_VAL_,0,0x00000000)
+#define SET_RG_RAM_08(_VAL_) SET_REG(ADR_PMU_RAM_08,_VAL_,0,0x00000000)
+#define SET_RG_RAM_09(_VAL_) SET_REG(ADR_PMU_RAM_09,_VAL_,0,0x00000000)
+#define SET_RG_RAM_10(_VAL_) SET_REG(ADR_PMU_RAM_10,_VAL_,0,0x00000000)
+#define SET_RG_RAM_11(_VAL_) SET_REG(ADR_PMU_RAM_11,_VAL_,0,0x00000000)
+#define SET_RG_RAM_12(_VAL_) SET_REG(ADR_PMU_RAM_12,_VAL_,0,0x00000000)
+#define SET_RG_RAM_13(_VAL_) SET_REG(ADR_PMU_RAM_13,_VAL_,0,0x00000000)
+#define SET_RG_RAM_14(_VAL_) SET_REG(ADR_PMU_RAM_14,_VAL_,0,0x00000000)
+#define SET_RG_RAM_15(_VAL_) SET_REG(ADR_PMU_RAM_15,_VAL_,0,0x00000000)
+#define SET_RG_PMDLBK(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_SYS_REG,_VAL_,0,0xfffffffe)
+#define SET_RG_DAC_LBK_EDGE_SEL(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_SYS_REG,_VAL_,1,0xfffffffd)
+#define SET_RG_RSSI_EDGE_SEL_BB(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_SYS_REG,_VAL_,2,0xfffffffb)
+#define SET_RG_SIGN_SWAP_BB(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_SYS_REG,_VAL_,4,0xffffffef)
+#define SET_RG_IQ_SWAP_BB(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_SYS_REG,_VAL_,5,0xffffffdf)
+#define SET_RG_Q_INV_BB(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_SYS_REG,_VAL_,6,0xffffffbf)
+#define SET_RG_I_INV_BB(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_SYS_REG,_VAL_,7,0xffffff7f)
+#define SET_RG_BYPASS_ACI(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_SYS_REG,_VAL_,8,0xfffffeff)
+#define SET_RG_LBK_ANA_PATH(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_SYS_REG,_VAL_,9,0xfffffdff)
+#define SET_RG_LBK_DIG_SEL(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_SYS_REG,_VAL_,10,0xfffffbff)
+#define SET_RG_RF_5G_BAND(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_SYS_REG,_VAL_,11,0xfffff7ff)
+#define SET_RG_PRIMARY_CH_SIDE(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_SYS_REG,_VAL_,14,0xffffbfff)
+#define SET_RG_SYSTEM_BW(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_SYS_REG,_VAL_,15,0xffff7fff)
+#define SET_RG_11B_ACI_SEL(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_SYS_REG,_VAL_,16,0xfffeffff)
+#define SET_RG_BB_CLK_SEL(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_SYS_REG,_VAL_,31,0x7fffffff)
+#define SET_RG_PHY_MD_EN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_ENABLE_REG,_VAL_,0,0xfffffffe)
+#define SET_RG_PHYRX_MD_EN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_ENABLE_REG,_VAL_,1,0xfffffffd)
+#define SET_RG_PHYTX_MD_EN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_ENABLE_REG,_VAL_,2,0xfffffffb)
+#define SET_RG_PHY11GN_MD_EN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_ENABLE_REG,_VAL_,3,0xfffffff7)
+#define SET_RG_PHY11B_MD_EN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_ENABLE_REG,_VAL_,4,0xffffffef)
+#define SET_RG_PHYRXFIFO_MD_EN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_ENABLE_REG,_VAL_,5,0xffffffdf)
+#define SET_RG_PHYTXFIFO_MD_EN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_ENABLE_REG,_VAL_,6,0xffffffbf)
+#define SET_RG_PHY11BGN_MD_EN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_ENABLE_REG,_VAL_,8,0xfffffeff)
+#define SET_RG_FORCE_11GN_EN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_ENABLE_REG,_VAL_,12,0xffffefff)
+#define SET_RG_FORCE_11B_EN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_ENABLE_REG,_VAL_,13,0xffffdfff)
+#define SET_RG_PHY_IQ_TRIG_SEL(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_ENABLE_REG,_VAL_,16,0xfff0ffff)
+#define SET_SVN_VERSION(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_VERSION_REG,_VAL_,0,0x00000000)
+#define SET_RG_LENGTH(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG0,_VAL_,0,0xffff0000)
+#define SET_RG_PKT_MODE(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG0,_VAL_,16,0xfff8ffff)
+#define SET_RG_CH_BW(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG0,_VAL_,19,0xffc7ffff)
+#define SET_RG_PRM(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG0,_VAL_,22,0xffbfffff)
+#define SET_RG_SHORTGI(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG0,_VAL_,23,0xff7fffff)
+#define SET_RG_RATE(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG0,_VAL_,24,0x80ffffff)
+#define SET_RG_L_LENGTH(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG1,_VAL_,0,0xfffff000)
+#define SET_RG_L_RATE(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG1,_VAL_,12,0xffff8fff)
+#define SET_RG_SERVICE(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG1,_VAL_,16,0x0000ffff)
+#define SET_RG_SMOOTHING(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG2,_VAL_,0,0xfffffffe)
+#define SET_RG_NO_SOUND(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG2,_VAL_,1,0xfffffffd)
+#define SET_RG_AGGREGATE(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG2,_VAL_,2,0xfffffffb)
+#define SET_RG_STBC(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG2,_VAL_,3,0xffffffe7)
+#define SET_RG_FEC(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG2,_VAL_,5,0xffffffdf)
+#define SET_RG_N_ESS(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG2,_VAL_,6,0xffffff3f)
+#define SET_RG_TXPWRLVL(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG2,_VAL_,8,0xffff80ff)
+#define SET_RG_BB_SCALE(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG2,_VAL_,16,0xff00ffff)
+#define SET_RG_TX_START(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG3,_VAL_,0,0xfffffffe)
+#define SET_RG_IFS_TIME(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG3,_VAL_,2,0xffffff03)
+#define SET_RG_CONTINUOUS_DATA(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG3,_VAL_,8,0xfffffeff)
+#define SET_RG_DATA_SEL(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG3,_VAL_,9,0xfffff9ff)
+#define SET_RG_TX_D(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG3,_VAL_,16,0xff00ffff)
+#define SET_RG_IFS_TIME_EXT(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG3,_VAL_,24,0x00ffffff)
+#define SET_RG_TX_CNT_TARGET(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG4,_VAL_,0,0x00000000)
+#define SET_RG_TXD_SEL(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_TX_CONTROL,_VAL_,10,0xfffff3ff)
+#define SET_RG_TX_FREQ_OFFSET_DES(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG5,_VAL_,0,0xffff0000)
+#define SET_RG_DES_RATE(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG6,_VAL_,0,0xffffff00)
+#define SET_RG_DES_MAN_EN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG6,_VAL_,31,0x7fffffff)
+#define SET_RG_PGA_REFDB_SAT_B(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG0,_VAL_,0,0xffffff80)
+#define SET_RG_PGA_REFDB_TOP_B(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG0,_VAL_,8,0xffff80ff)
+#define SET_RG_PGA_REF_UND_B(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG0,_VAL_,16,0xfc00ffff)
+#define SET_RG_RF_REF_SAT_B(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG0,_VAL_,28,0x0fffffff)
+#define SET_RG_PGA_REFDB_SAT_GN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG1,_VAL_,0,0xffffff80)
+#define SET_RG_PGA_REFDB_TOP_GN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG1,_VAL_,8,0xffff80ff)
+#define SET_RG_PGA_REF_UND_GN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG1,_VAL_,16,0xfc00ffff)
+#define SET_RG_RF_REF_SAT_GN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG1,_VAL_,28,0x0fffffff)
+#define SET_RG_PGAGC_SET(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG2,_VAL_,0,0xfffffff0)
+#define SET_RG_PGAGC_OW(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG2,_VAL_,4,0xffffffef)
+#define SET_RG_RFGC_SET(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG2,_VAL_,5,0xffffff9f)
+#define SET_RG_RFGC_OW(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG2,_VAL_,7,0xffffff7f)
+#define SET_RG_WAIT_T_RXAGC(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG2,_VAL_,8,0xffffc0ff)
+#define SET_RG_RXAGC_SET(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG2,_VAL_,14,0xffffbfff)
+#define SET_RG_RXAGC_OW(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG2,_VAL_,15,0xffff7fff)
+#define SET_RG_WAIT_T_FINAL(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG2,_VAL_,16,0xffc0ffff)
+#define SET_RG_WAIT_T(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG2,_VAL_,24,0xc0ffffff)
+#define SET_RG_ULG_PGA_SAT_PGA_GAIN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG3,_VAL_,0,0xfffffff0)
+#define SET_RG_LG_PGA_UND_PGA_GAIN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG3,_VAL_,4,0xffffff0f)
+#define SET_RG_LG_PGA_SAT_PGA_GAIN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG3,_VAL_,8,0xfffff0ff)
+#define SET_RG_LG_RF_SAT_PGA_GAIN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG3,_VAL_,12,0xffff0fff)
+#define SET_RG_MG_RF_SAT_PGANOREF_PGA_GAIN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG3,_VAL_,16,0xfff0ffff)
+#define SET_RG_HG_PGA_SAT2_PGA_GAIN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG3,_VAL_,20,0xff0fffff)
+#define SET_RG_HG_PGA_SAT1_PGA_GAIN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG3,_VAL_,24,0xf0ffffff)
+#define SET_RG_HG_RF_SAT_PGA_GAIN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG3,_VAL_,28,0x0fffffff)
+#define SET_RG_MG_PGA_JB_TH(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG4,_VAL_,0,0xfffffff0)
+#define SET_RG_MA_PGA_LOW_TH_CNT_LMT(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG4,_VAL_,16,0xffe0ffff)
+#define SET_RG_MA_PGA_HIGH_TH_CNT_LMT(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG4,_VAL_,24,0xe0ffffff)
+#define SET_RG_AGC_THRESHOLD(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11B_DAGC_REG0,_VAL_,0,0xffffc000)
+#define SET_RG_ACI_POINT_CNT_LMT_11B(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11B_DAGC_REG0,_VAL_,16,0xff80ffff)
+#define SET_RG_ACI_DAGC_LEAKY_FACTOR_11B(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11B_DAGC_REG0,_VAL_,24,0xfcffffff)
+#define SET_RG_ACI_DAGC_PWR_SEL_11B(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11B_DAGC_REG0,_VAL_,28,0xefffffff)
+#define SET_RG_ACI_DAGC_TARGET_11B(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11B_DAGC_REG1,_VAL_,0,0xffffff80)
+#define SET_RG_ACI_GAIN_INI_11B(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11B_DAGC_REG1,_VAL_,8,0xffff00ff)
+#define SET_RG_ACI_GAIN_SET_11B(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11B_DAGC_REG1,_VAL_,16,0xff00ffff)
+#define SET_RG_ACI_GAIN_OW_11B(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11B_DAGC_REG1,_VAL_,31,0x7fffffff)
+#define SET_RG_ACI_POINT_CNT_LMT_11GN_HT20(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11GN20_DAGC_REG0,_VAL_,0,0xffffff00)
+#define SET_RG_ACI_DAGC_LEAKY_FACTOR_11GN_HT20(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11GN20_DAGC_REG0,_VAL_,8,0xfffffcff)
+#define SET_RG_ACI_DAGC_PWR_SEL_11GN_HT20(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11GN20_DAGC_REG0,_VAL_,12,0xffffefff)
+#define SET_RG_ACI_DAGC_DONE_CNT_LMT_11GN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11GN20_DAGC_REG0,_VAL_,24,0x00ffffff)
+#define SET_RG_ACI_DAGC_TARGET_11GN_HT20(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11GN20_DAGC_REG1,_VAL_,0,0xffffff80)
+#define SET_RG_ACI_GAIN_SET_11GN_HT20(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11GN20_DAGC_REG1,_VAL_,16,0xfe00ffff)
+#define SET_RG_ACI_GAIN_OW_11GN_HT20(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11GN20_DAGC_REG1,_VAL_,31,0x7fffffff)
+#define SET_RO_CCA_PWR_MA_11GN_HT40(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11BGN_DIGPWR_REG,_VAL_,0,0xffffff80)
+#define SET_RO_CCA_PWR_MA_11GN_HT20(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11BGN_DIGPWR_REG,_VAL_,8,0xffff80ff)
+#define SET_RO_CCA_PWR_MA_11B(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11BGN_DIGPWR_REG,_VAL_,16,0xff80ffff)
+#define SET_RO_ED_STATE(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11BGN_DIGPWR_REG,_VAL_,24,0xfeffffff)
+#define SET_RO_2ND_ED_STATE(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11BGN_DIGPWR_REG,_VAL_,25,0xfdffffff)
+#define SET_RO_PGA_PWR_FF1(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_RO00,_VAL_,0,0xffffc000)
+#define SET_RO_RF_PWR_FF1(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_RO00,_VAL_,16,0xfff0ffff)
+#define SET_RO_PGAGC_FF1(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_RO00,_VAL_,24,0xf0ffffff)
+#define SET_RO_RFGC_FF1(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_RO00,_VAL_,28,0xcfffffff)
+#define SET_RO_PGA_PWR_FF2(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_RO01,_VAL_,0,0xffffc000)
+#define SET_RO_RF_PWR_FF2(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_RO01,_VAL_,16,0xfff0ffff)
+#define SET_RO_PGAGC_FF2(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_RO01,_VAL_,24,0xf0ffffff)
+#define SET_RO_RFGC_FF2(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_RO01,_VAL_,28,0xcfffffff)
+#define SET_RO_PGA_PWR_FF3(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_RO02,_VAL_,0,0xffffc000)
+#define SET_RO_RF_PWR_FF3(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_RO02,_VAL_,16,0xfff0ffff)
+#define SET_RO_PGAGC_FF3(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_RO02,_VAL_,24,0xf0ffffff)
+#define SET_RO_RFGC_FF3(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_RO02,_VAL_,28,0xcfffffff)
+#define SET_RG_5G_DC_RM_LEAKY_FACTOR_T3(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RXDC,_VAL_,4,0xffffff8f)
+#define SET_RG_5G_DC_RM_LEAKY_FACTOR_T2(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RXDC,_VAL_,8,0xfffff8ff)
+#define SET_RG_5G_DC_RM_LEAKY_FACTOR_T1(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RXDC,_VAL_,12,0xffff8fff)
+#define SET_RG_DC_RM_BYP(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RXDC,_VAL_,16,0xfffeffff)
+#define SET_RG_DC_RM_LEAKY_FACTOR_T3(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RXDC,_VAL_,20,0xff8fffff)
+#define SET_RG_DC_RM_LEAKY_FACTOR_T2(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RXDC,_VAL_,24,0xf8ffffff)
+#define SET_RG_DC_RM_LEAKY_FACTOR_T1(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RXDC,_VAL_,28,0x8fffffff)
+#define SET_RO_Q_DC_OUT(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RXDC_RO,_VAL_,0,0xfffffc00)
+#define SET_RO_I_DC_OUT(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RXDC_RO,_VAL_,16,0xfc00ffff)
+#define SET_RG_TBUS_SEL(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RSSI_TBUS_REG,_VAL_,0,0xfffffff0)
+#define SET_RG_RSSI_OFFSET(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RSSI_TBUS_REG,_VAL_,16,0xff00ffff)
+#define SET_RG_RSSI_INV(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RSSI_TBUS_REG,_VAL_,24,0xfeffffff)
+#define SET_RO_MRX_EN_CNT(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_EN_CNT_REG,_VAL_,0,0xffff0000)
+#define SET_RG_MRX_EN_CNT_RST_N(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_EN_CNT_REG,_VAL_,31,0x7fffffff)
+#define SET_RG_EDCCA_AVG_T(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_EDCCA_0,_VAL_,0,0xfffffff8)
+#define SET_RG_EDCCA_STAT_EN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_EDCCA_0,_VAL_,4,0xffffffef)
+#define SET_RO_EDCCA_PRIMARY_PRD(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_EDCCA_1,_VAL_,0,0xffff0000)
+#define SET_RO_PRIMARY_EDCCA(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_EDCCA_1,_VAL_,16,0x0000ffff)
+#define SET_RO_EDCCA_SECONDARY_PRD(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_EDCCA_2,_VAL_,0,0xffff0000)
+#define SET_RO_SECONDARY_EDCCA(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_EDCCA_2,_VAL_,16,0x0000ffff)
+#define SET_RG_AGC_RELOCK_PWR_TH(_VAL_) SET_REG(ADR_WIFI_PHY_AGC_RELOCK_1,_VAL_,0,0xffffc000)
+#define SET_RG_AGC_RELOCK_CNT_TH(_VAL_) SET_REG(ADR_WIFI_PHY_AGC_RELOCK_1,_VAL_,16,0xffc0ffff)
+#define SET_RG_AGC_RELOCK_SEL(_VAL_) SET_REG(ADR_WIFI_PHY_AGC_RELOCK_1,_VAL_,24,0xfcffffff)
+#define SET_RG_AGC_RELOCK_EN(_VAL_) SET_REG(ADR_WIFI_PHY_AGC_RELOCK_1,_VAL_,28,0xefffffff)
+#define SET_RG_AGC_RELOCK_11GN(_VAL_) SET_REG(ADR_WIFI_PHY_AGC_RELOCK_1,_VAL_,30,0xbfffffff)
+#define SET_RG_AGC_RELOCK_11B(_VAL_) SET_REG(ADR_WIFI_PHY_AGC_RELOCK_1,_VAL_,31,0x7fffffff)
+#define SET_RG_AGC_RELOCK_PWR_DIFFDB_TH(_VAL_) SET_REG(ADR_WIFI_PHY_AGC_RELOCK_2,_VAL_,0,0xffffff80)
+#define SET_RG_AGC_RELOCK_CNT_DIFFDB_TH(_VAL_) SET_REG(ADR_WIFI_PHY_AGC_RELOCK_2,_VAL_,16,0xffc0ffff)
+#define SET_RG_MTX_LEN_LOWER_TH_0(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_TX_LENGTH_CNT_REG0,_VAL_,0,0xffff0000)
+#define SET_RG_MTX_LEN_UPPER_TH_0(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_TX_LENGTH_CNT_REG0,_VAL_,16,0x0000ffff)
+#define SET_RG_MTX_LEN_LOWER_TH_1(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_TX_LENGTH_CNT_REG1,_VAL_,0,0xffff0000)
+#define SET_RG_MTX_LEN_UPPER_TH_1(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_TX_LENGTH_CNT_REG1,_VAL_,16,0x0000ffff)
+#define SET_RG_MRX_LEN_LOWER_TH_0(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_LENGTH_CNT_REG0,_VAL_,0,0xffff0000)
+#define SET_RG_MRX_LEN_UPPER_TH_0(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_LENGTH_CNT_REG0,_VAL_,16,0x0000ffff)
+#define SET_RG_MRX_LEN_LOWER_TH_1(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_LENGTH_CNT_REG1,_VAL_,0,0xffff0000)
+#define SET_RG_MRX_LEN_UPPER_TH_1(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_LENGTH_CNT_REG1,_VAL_,16,0x0000ffff)
+#define SET_RO_MTX_LEN_CNT_1(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_TX_LENGTH_CNT_RO,_VAL_,0,0xffff0000)
+#define SET_RO_MTX_LEN_CNT_0(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_TX_LENGTH_CNT_RO,_VAL_,16,0x0000ffff)
+#define SET_RO_MRX_LEN_CNT_1(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_LENGTH_CNT_RO,_VAL_,0,0xffff0000)
+#define SET_RO_MRX_LEN_CNT_0(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_LENGTH_CNT_RO,_VAL_,16,0x0000ffff)
+#define SET_RG_MRX_TYPE(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_TRX_TYPE_CNT_REG,_VAL_,0,0xffffff00)
+#define SET_RG_MRX_TYPE_CNT_LMT(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_TRX_TYPE_CNT_REG,_VAL_,8,0xffffe0ff)
+#define SET_RG_MTX_TYPE(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_TRX_TYPE_CNT_REG,_VAL_,16,0xff00ffff)
+#define SET_RG_MTX_TYPE_CNT_LMT(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_TRX_TYPE_CNT_REG,_VAL_,24,0xe0ffffff)
+#define SET_RO_MRX_TYPE_CNT(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_TRX_TYPE_CNT_RO,_VAL_,0,0xffff0000)
+#define SET_RO_MTX_TYPE_CNT(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_TRX_TYPE_CNT_RO,_VAL_,16,0x0000ffff)
+#define SET_RG_ACI_POINT_CNT_LMT_11GN_HT40(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11GN40_DAGC_REG0,_VAL_,0,0xffffff00)
+#define SET_RG_ACI_DAGC_LEAKY_FACTOR_11GN_HT40(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11GN40_DAGC_REG0,_VAL_,8,0xfffffcff)
+#define SET_RG_ACI_DAGC_PWR_SEL_11GN_HT40(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11GN40_DAGC_REG0,_VAL_,12,0xffffefff)
+#define SET_RG_ACI_DAGC_TARGET_11GN_HT40(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11GN40_DAGC_REG1,_VAL_,0,0xffffff80)
+#define SET_RG_ACI_GAIN_SET_11GN_HT40(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11GN40_DAGC_REG1,_VAL_,16,0xfe00ffff)
+#define SET_RG_ACI_GAIN_OW_11GN_HT40(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11GN40_DAGC_REG1,_VAL_,31,0x7fffffff)
+#define SET_RG_ACI_GAIN_INI_11GN_HT40(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11GN_DAGC_INI_REG,_VAL_,0,0xfffffe00)
+#define SET_RG_ACI_GAIN_INI_11GN_HT20(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11GN_DAGC_INI_REG,_VAL_,16,0xfe00ffff)
+#define SET_RG_MAC_PKT_MODE(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_0,_VAL_,0,0xfffffffe)
+#define SET_RG_MAC_PKT_AGGREGATE(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_0,_VAL_,1,0xfffffffd)
+#define SET_RG_MAC_PKT_ADDR4_ON(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_0,_VAL_,4,0xffffffef)
+#define SET_RG_MAC_PKT_SEQ_ON(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_0,_VAL_,5,0xffffffdf)
+#define SET_RG_MAC_PKT_ADDR3_ON(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_0,_VAL_,6,0xffffffbf)
+#define SET_RG_MAC_PKT_ADDR2_ON(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_0,_VAL_,7,0xffffff7f)
+#define SET_RG_MAC_PKT_AGGREGATE_NUM(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_0,_VAL_,8,0xfffff0ff)
+#define SET_RG_MAC_PKT_PLD_LENGTH(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_0,_VAL_,16,0x0000ffff)
+#define SET_RG_MAC_PKT_DUR(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_1,_VAL_,0,0xffff0000)
+#define SET_RG_MAC_PKT_FC(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_1,_VAL_,16,0x0000ffff)
+#define SET_RG_MAC_PKT_ADDR1_31_0(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_2,_VAL_,0,0x00000000)
+#define SET_RG_MAC_PKT_ADDR1_47_32(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_3,_VAL_,0,0xffff0000)
+#define SET_RG_MAC_PKT_ADDR2_31_0(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_4,_VAL_,0,0x00000000)
+#define SET_RG_MAC_PKT_ADDR2_47_32(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_5,_VAL_,0,0xffff0000)
+#define SET_RG_MAC_PKT_ADDR3_31_0(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_6,_VAL_,0,0x00000000)
+#define SET_RG_MAC_PKT_ADDR3_47_32(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_7,_VAL_,0,0xffff0000)
+#define SET_RG_MAC_PKT_SEQ(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_8,_VAL_,0,0xffff0000)
+#define SET_RG_MAC_PKT_ADDR4_31_0(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_9,_VAL_,0,0x00000000)
+#define SET_RG_MAC_PKT_ADDR4_47_32(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_A,_VAL_,0,0xffff0000)
+#define SET_RG_BB_SCALE_BARKER_CCK(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_0,_VAL_,0,0xffffff00)
+#define SET_RG_BB_SCALE_MAN_EN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_0,_VAL_,16,0xfffeffff)
+#define SET_RG_BB_SCALE_LEGACY_64QAM(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_1,_VAL_,0,0xffffff00)
+#define SET_RG_BB_SCALE_LEGACY_16QAM(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_1,_VAL_,8,0xffff00ff)
+#define SET_RG_BB_SCALE_LEGACY_QPSK(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_1,_VAL_,16,0xff00ffff)
+#define SET_RG_BB_SCALE_LEGACY_BPSK(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_1,_VAL_,24,0x00ffffff)
+#define SET_RG_BB_SCALE_HT20_64QAM(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_2,_VAL_,0,0xffffff00)
+#define SET_RG_BB_SCALE_HT20_16QAM(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_2,_VAL_,8,0xffff00ff)
+#define SET_RG_BB_SCALE_HT20_QPSK(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_2,_VAL_,16,0xff00ffff)
+#define SET_RG_BB_SCALE_HT20_BPSK(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_2,_VAL_,24,0x00ffffff)
+#define SET_RG_BB_SCALE_HT40_64QAM(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_3,_VAL_,0,0xffffff00)
+#define SET_RG_BB_SCALE_HT40_16QAM(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_3,_VAL_,8,0xffff00ff)
+#define SET_RG_BB_SCALE_HT40_QPSK(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_3,_VAL_,16,0xff00ffff)
+#define SET_RG_BB_SCALE_HT40_BPSK(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_3,_VAL_,24,0x00ffffff)
+#define SET_RG_RF_PWR_BARKER_CCK(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RF_PWR_REG_0,_VAL_,0,0xffffff80)
+#define SET_RG_RF_PWR_MAN_EN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RF_PWR_REG_0,_VAL_,16,0xfffeffff)
+#define SET_RG_RF_PWR_LEGACY_64QAM(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RF_PWR_REG_1,_VAL_,0,0xffffff80)
+#define SET_RG_RF_PWR_LEGACY_16QAM(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RF_PWR_REG_1,_VAL_,8,0xffff80ff)
+#define SET_RG_RF_PWR_LEGACY_QPSK(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RF_PWR_REG_1,_VAL_,16,0xff80ffff)
+#define SET_RG_RF_PWR_LEGACY_BPSK(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RF_PWR_REG_1,_VAL_,24,0x80ffffff)
+#define SET_RG_RF_PWR_HT20_64QAM(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RF_PWR_REG_2,_VAL_,0,0xffffff80)
+#define SET_RG_RF_PWR_HT20_16QAM(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RF_PWR_REG_2,_VAL_,8,0xffff80ff)
+#define SET_RG_RF_PWR_HT20_QPSK(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RF_PWR_REG_2,_VAL_,16,0xff80ffff)
+#define SET_RG_RF_PWR_HT20_BPSK(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RF_PWR_REG_2,_VAL_,24,0x80ffffff)
+#define SET_RG_RF_PWR_HT40_64QAM(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RF_PWR_REG_3,_VAL_,0,0xffffff80)
+#define SET_RG_RF_PWR_HT40_16QAM(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RF_PWR_REG_3,_VAL_,8,0xffff80ff)
+#define SET_RG_RF_PWR_HT40_QPSK(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RF_PWR_REG_3,_VAL_,16,0xff80ffff)
+#define SET_RG_RF_PWR_HT40_BPSK(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RF_PWR_REG_3,_VAL_,24,0x80ffffff)
+#define SET_RG_RX_MONITOR_ON(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_MON_0,_VAL_,0,0xfffffffe)
+#define SET_RG_RX_PKT_ADDR3_ON(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_MON_0,_VAL_,1,0xfffffffd)
+#define SET_RG_RX_PKT_ADDR2_ON(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_MON_0,_VAL_,2,0xfffffffb)
+#define SET_RG_RX_PKT_ADDR1_ON(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_MON_0,_VAL_,3,0xfffffff7)
+#define SET_RG_RX_BEACON_TU(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_MON_0,_VAL_,4,0xffffc00f)
+#define SET_RG_RX_PKT_TIMER_LMT(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_MON_0,_VAL_,16,0x0000ffff)
+#define SET_RG_RX_BEACON_LOSS_CNT_LMT(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_MON_1,_VAL_,0,0xffffff00)
+#define SET_RG_RX_BEACON_CRC_BYPASS(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_MON_1,_VAL_,8,0xfffffeff)
+#define SET_RG_RX_BEACON_INTERVAL(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_MON_1,_VAL_,16,0x0000ffff)
+#define SET_RG_RX_PKT_FC(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_MON_2,_VAL_,16,0x0000ffff)
+#define SET_RG_RX_PKT_ADDR1_31_0(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_MON_3,_VAL_,0,0x00000000)
+#define SET_RG_RX_PKT_ADDR1_47_32(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_MON_4,_VAL_,0,0xffff0000)
+#define SET_RG_RX_PKT_ADDR2_31_0(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_MON_5,_VAL_,0,0x00000000)
+#define SET_RG_RX_PKT_ADDR2_47_32(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_MON_6,_VAL_,0,0xffff0000)
+#define SET_RG_RX_PKT_ADDR3_31_0(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_MON_7,_VAL_,0,0x00000000)
+#define SET_RG_RX_PKT_ADDR3_47_32(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_MON_8,_VAL_,0,0xffff0000)
+#define SET_RO_INTRP_RX_LOSS(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_TMR_MON_RO,_VAL_,0,0xfffffffe)
+#define SET_RO_RX_PKT_TIMER(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_TMR_MON_RO,_VAL_,16,0x0000ffff)
+#define SET_RO_INTRP_RX_BEACON_LOSS(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_BKN_MON_RO,_VAL_,0,0xfffffffe)
+#define SET_RO_RX_BEACON_LOSS_CNT(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_BKN_MON_RO,_VAL_,8,0xffff00ff)
+#define SET_RO_RX_BEACON_CNT(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_BKN_MON_RO,_VAL_,16,0x0000ffff)
+#define SET_RG_RX_FIFO_FULL_CNT_EN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_MAC_IF_CNT_CTRL,_VAL_,0,0xfffffffe)
+#define SET_RG_TX_FIFO_EMPTY_CNT_EN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_MAC_IF_CNT_CTRL,_VAL_,4,0xffffffef)
+#define SET_RO_RX_FIFO_FULL_CNT(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_MAC_IF_CNT_RO,_VAL_,0,0xffff0000)
+#define SET_RO_TX_FIFO_EMPTY_CNT(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_MAC_IF_CNT_RO,_VAL_,16,0x0000ffff)
+#define SET_RG_BIST_EN_RX_FFT(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_FFT_MEM_BIST_REG,_VAL_,0,0xfffffffe)
+#define SET_RG_BIST_MODE_RX_FFT(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_FFT_MEM_BIST_REG,_VAL_,4,0xffffffef)
+#define SET_RO_BIST_DONE_RX_FFT_1(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_FFT_MEM_BIST_REG,_VAL_,16,0xfffeffff)
+#define SET_RO_BIST_FAIL_RX_FFT_1(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_FFT_MEM_BIST_REG,_VAL_,17,0xfffdffff)
+#define SET_RO_BIST_DONE_RX_FFT_0(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_FFT_MEM_BIST_REG,_VAL_,20,0xffefffff)
+#define SET_RO_BIST_FAIL_RX_FFT_0(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_FFT_MEM_BIST_REG,_VAL_,21,0xffdfffff)
+#define SET_RG_AUDIO_CLK_EN(_VAL_) SET_REG(ADR_WIFI_PHY_AUDIO_CLK_CTRL,_VAL_,0,0xfffffffe)
+#define SET_RG_AUDIO_CLK_SEL(_VAL_) SET_REG(ADR_WIFI_PHY_AUDIO_CLK_CTRL,_VAL_,1,0xfffffffd)
+#define SET_RO_CSTATE_PKT(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_TOP_STATUS_RO,_VAL_,0,0xfffffffc)
+#define SET_RO_MRX_RX_EN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_TOP_STATUS_RO,_VAL_,4,0xffffffef)
+#define SET_RO_CSTATE_AGC(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_TOP_STATUS_RO,_VAL_,8,0xfffffcff)
+#define SET_RO_AGC_START_80M(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_TOP_STATUS_RO,_VAL_,12,0xffffefff)
+#define SET_RO_CSTATE_RX(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_TOP_STATUS_RO,_VAL_,16,0xfff0ffff)
+#define SET_RO_TX_IP(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_TOP_STATUS_RO,_VAL_,20,0xffefffff)
+#define SET_RO_CSTATE_TX(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_TOP_STATUS_RO,_VAL_,24,0xf0ffffff)
+#define SET_RO_MAC_PHY_TRX_EN_SYNC(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_TOP_STATUS_RO,_VAL_,28,0xefffffff)
+#define SET_RG_RESERVED_CMM(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RESERVED_REG,_VAL_,0,0x00000000)
+#define SET_RG_BB_RISE_TIME_11B_TX(_VAL_) SET_REG(ADR_WIFI_11B_TX_BB_RAMP_REG,_VAL_,0,0xffffff00)
+#define SET_RG_BB_FALL_TIME_11B_TX(_VAL_) SET_REG(ADR_WIFI_11B_TX_BB_RAMP_REG,_VAL_,8,0xffff00ff)
+#define SET_RG_BP_SMB(_VAL_) SET_REG(ADR_WIFI_11B_TX_BB_RAMP_REG,_VAL_,16,0xfffeffff)
+#define SET_RO_TX_CNT_R_11B_TX(_VAL_) SET_REG(ADR_WIFI_11B_TX_PKT_CNT_SENT_REG,_VAL_,0,0x00000000)
+#define SET_RG_DEBUG_SEL_11B_TX(_VAL_) SET_REG(ADR_WIFI_11B_TX_DEBUG_SEL_REG,_VAL_,0,0xfffffff0)
+#define SET_RG_RESERVED_11B_TX(_VAL_) SET_REG(ADR_WIFI_11B_TX_RESERVED_REG,_VAL_,0,0x00000000)
+#define SET_RG_POS_DES_L_EXT_11B_RX(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_000,_VAL_,0,0xfffffff0)
+#define SET_RG_PRE_DES_DLY_11B_RX(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_000,_VAL_,4,0xffffff0f)
+#define SET_RG_CCA_RE_CHK_BIT_CNT_TH(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_000,_VAL_,8,0xfffff0ff)
+#define SET_RG_CNT_CCA_RE_CHK_LMT(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_001,_VAL_,16,0xfff0ffff)
+#define SET_RG_BYPASS_DESCRAMBLER(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_001,_VAL_,29,0xdfffffff)
+#define SET_RG_CCA_BIT_CNT_TH(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_002,_VAL_,4,0xffffff0f)
+#define SET_RG_CCA_SCALE_BF(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_002,_VAL_,16,0xff80ffff)
+#define SET_RG_PEAK_IDX_CNT_SEL(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_002,_VAL_,28,0xcfffffff)
+#define SET_RG_TR_KI_T2(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_003,_VAL_,0,0xfffffff8)
+#define SET_RG_TR_KP_T2(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_003,_VAL_,4,0xffffff8f)
+#define SET_RG_TR_KI_T1(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_003,_VAL_,8,0xfffff8ff)
+#define SET_RG_TR_KP_T1(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_003,_VAL_,12,0xffff8fff)
+#define SET_RG_CR_KI_T1(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_004,_VAL_,16,0xfff8ffff)
+#define SET_RG_CR_KP_T1(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_004,_VAL_,20,0xff8fffff)
+#define SET_RG_CHIP_CNT_SLICER(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_005,_VAL_,0,0xffffffe0)
+#define SET_RG_CE_T2_CNT_LMT(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_005,_VAL_,24,0x00ffffff)
+#define SET_RG_CE_MU_T1(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_006,_VAL_,0,0xfffffff8)
+#define SET_RG_CE_DLY_SEL(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_006,_VAL_,16,0xffc0ffff)
+#define SET_RG_CE_MU_T4(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_007,_VAL_,0,0xfffffff8)
+#define SET_RG_CE_MU_T3(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_007,_VAL_,16,0xfff8ffff)
+#define SET_RG_CE_MU_T2(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_007,_VAL_,24,0xf8ffffff)
+#define SET_RG_EQ_MU_FB_T2(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_008,_VAL_,0,0xfffffff0)
+#define SET_RG_EQ_MU_FF_T2(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_008,_VAL_,4,0xffffff0f)
+#define SET_RG_EQ_MU_FB_T1(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_008,_VAL_,16,0xfff0ffff)
+#define SET_RG_EQ_MU_FF_T1(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_008,_VAL_,20,0xff0fffff)
+#define SET_RG_EQ_MU_FB_T4(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_009,_VAL_,0,0xfffffff0)
+#define SET_RG_EQ_MU_FF_T4(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_009,_VAL_,4,0xffffff0f)
+#define SET_RG_EQ_MU_FB_T3(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_009,_VAL_,16,0xfff0ffff)
+#define SET_RG_EQ_MU_FF_T3(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_009,_VAL_,20,0xff0fffff)
+#define SET_RG_EQ_KI_T2(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_010,_VAL_,8,0xfffff8ff)
+#define SET_RG_EQ_KP_T2(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_010,_VAL_,12,0xffff8fff)
+#define SET_RG_EQ_KI_T1(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_010,_VAL_,16,0xfff8ffff)
+#define SET_RG_EQ_KP_T1(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_010,_VAL_,20,0xff8fffff)
+#define SET_RG_TR_LPF_RATE(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_011,_VAL_,0,0xffc00000)
+#define SET_RG_CE_BIT_CNT_LMT(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_012,_VAL_,0,0xffffff80)
+#define SET_RG_CE_CH_MAIN_SET(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_012,_VAL_,7,0xffffff7f)
+#define SET_RG_TC_BIT_CNT_LMT(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_012,_VAL_,8,0xffff80ff)
+#define SET_RG_CR_BIT_CNT_LMT(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_012,_VAL_,16,0xff80ffff)
+#define SET_RG_TR_BIT_CNT_LMT(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_012,_VAL_,24,0x80ffffff)
+#define SET_RG_EQ_MAIN_TAP_MAN(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_013,_VAL_,0,0xfffffffe)
+#define SET_RG_EQ_MAIN_TAP_COEF(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_013,_VAL_,16,0xf800ffff)
+#define SET_RG_CCK_TR_KI_T2(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_014,_VAL_,0,0xfffffff8)
+#define SET_RG_CCK_TR_KP_T2(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_014,_VAL_,4,0xffffff8f)
+#define SET_RG_PWRON_DLY_TH_11B_RX(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_039,_VAL_,0,0xffffff00)
+#define SET_RG_SFD_BIT_CNT_LMT(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_039,_VAL_,16,0xff00ffff)
+#define SET_RG_PWR_TH(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_040,_VAL_,0,0xffff0000)
+#define SET_RG_PWR_CNT_TH(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_040,_VAL_,16,0xffe0ffff)
+#define SET_RG_PWR_BIT_CNT_TH(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_040,_VAL_,24,0xf0ffffff)
+#define SET_RG_PSDU_TIME_OFFSET_11B(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_041,_VAL_,0,0xffff0000)
+#define SET_RG_RESERVED_11B_RX(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_240,_VAL_,0,0x00000000)
+#define SET_RG_INTRUP_RX_11B_CLEAR(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_241,_VAL_,0,0xfffffffe)
+#define SET_RG_INTRUP_RX_11B_MASK(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_241,_VAL_,4,0xffffffef)
+#define SET_RG_INTRUP_RX_11B_TRIG(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_241,_VAL_,8,0xfffff0ff)
+#define SET_RO_INTRUP_RX_11B(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_241,_VAL_,16,0xfffeffff)
+#define SET_RO_11B_FREQ_OS(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_245,_VAL_,0,0xfffff800)
+#define SET_RO_11B_SNR(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_246,_VAL_,0,0xffffff80)
+#define SET_RO_11B_RCPI(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_246,_VAL_,16,0xff80ffff)
+#define SET_RO_11B_CRC_CNT(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_249,_VAL_,0,0xffff0000)
+#define SET_RO_11B_SFD_CNT(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_249,_VAL_,16,0x0000ffff)
+#define SET_RO_11B_PACKET_ERR_CNT(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_250,_VAL_,0,0xffff0000)
+#define SET_RO_11B_PACKET_ERR(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_250,_VAL_,16,0xfffeffff)
+#define SET_RO_11B_PACKET_CNT(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_251,_VAL_,0,0xffff0000)
+#define SET_RO_11B_CCA_CNT(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_251,_VAL_,16,0x0000ffff)
+#define SET_RO_11B_LENGTH_FIELD(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_252,_VAL_,0,0xffff0000)
+#define SET_RO_11B_SFD_FIELD(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_252,_VAL_,16,0x0000ffff)
+#define SET_RO_11B_SIGNAL_FIELD(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_253,_VAL_,0,0xffffff00)
+#define SET_RO_11B_SERVICE_FIELD(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_253,_VAL_,8,0xffff00ff)
+#define SET_RO_11B_CRC_CORRECT(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_253,_VAL_,16,0xfffeffff)
+#define SET_RG_RATE_STAT(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_254,_VAL_,16,0xfff8ffff)
+#define SET_RG_PACKET_STAT_EN_11B_RX(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_254,_VAL_,20,0xffefffff)
+#define SET_RG_BIT_REVERSE(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_254,_VAL_,21,0xffdfffff)
+#define SET_RG_SOFT_RST_N_11B_RX(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_255,_VAL_,0,0xfffffffe)
+#define SET_RG_CE_BYPASS_TAP(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_255,_VAL_,4,0xffffff0f)
+#define SET_RG_EQ_BYPASS_FBW_TAP(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_255,_VAL_,8,0xfffff0ff)
+#define SET_RG_DEBUG_SEL_11B_RX(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_255,_VAL_,16,0xfff0ffff)
+#define SET_RG_BIST_EN_TX_FFT(_VAL_) SET_REG(ADR_WIFI_11GN_TX_MEM_BIST_REG,_VAL_,0,0xfffffffe)
+#define SET_RG_BIST_MODE_TX_FFT(_VAL_) SET_REG(ADR_WIFI_11GN_TX_MEM_BIST_REG,_VAL_,4,0xffffffef)
+#define SET_RO_BIST_DONE_TX_FFT_1(_VAL_) SET_REG(ADR_WIFI_11GN_TX_MEM_BIST_REG,_VAL_,16,0xfffeffff)
+#define SET_RO_BIST_FAIL_TX_FFT_1(_VAL_) SET_REG(ADR_WIFI_11GN_TX_MEM_BIST_REG,_VAL_,17,0xfffdffff)
+#define SET_RO_BIST_DONE_TX_FFT_0(_VAL_) SET_REG(ADR_WIFI_11GN_TX_MEM_BIST_REG,_VAL_,20,0xffefffff)
+#define SET_RO_BIST_FAIL_TX_FFT_0(_VAL_) SET_REG(ADR_WIFI_11GN_TX_MEM_BIST_REG,_VAL_,21,0xffdfffff)
+#define SET_RG_BB_RISE_TIME_11GN_TX(_VAL_) SET_REG(ADR_WIFI_11GN_TX_BB_RAMP_REG,_VAL_,0,0xffffff00)
+#define SET_RG_BB_FALL_TIME_11GN_TX(_VAL_) SET_REG(ADR_WIFI_11GN_TX_BB_RAMP_REG,_VAL_,8,0xffff00ff)
+#define SET_RG_TX_CLK_OUTER_EN(_VAL_) SET_REG(ADR_WIFI_11GN_TX_CONTROL_REG,_VAL_,0,0xfffffffe)
+#define SET_RG_SHORT_GI_EN(_VAL_) SET_REG(ADR_WIFI_11GN_TX_CONTROL_REG,_VAL_,4,0xffffffef)
+#define SET_RG_STF_SCALE_20(_VAL_) SET_REG(ADR_WIFI_11GN_TX_STS_SCALE_REG,_VAL_,0,0xfffffc00)
+#define SET_RG_STF_SCALE_40(_VAL_) SET_REG(ADR_WIFI_11GN_TX_STS_SCALE_REG,_VAL_,16,0xfc00ffff)
+#define SET_RG_FFT_SCALE_104(_VAL_) SET_REG(ADR_WIFI_11GN_TX_FFT_SCALE_REG0,_VAL_,0,0xfffffc00)
+#define SET_RG_FFT_SCALE_114(_VAL_) SET_REG(ADR_WIFI_11GN_TX_FFT_SCALE_REG0,_VAL_,16,0xfc00ffff)
+#define SET_RG_FFT_SCALE_52(_VAL_) SET_REG(ADR_WIFI_11GN_TX_FFT_SCALE_REG1,_VAL_,0,0xfffffc00)
+#define SET_RG_FFT_SCALE_56(_VAL_) SET_REG(ADR_WIFI_11GN_TX_FFT_SCALE_REG1,_VAL_,12,0xffc00fff)
+#define SET_RG_SCR_INIT_SEED(_VAL_) SET_REG(ADR_WIFI_11GN_TX_FFT_SCALE_REG1,_VAL_,24,0x80ffffff)
+#define SET_RG_SCR_SEED_MANUANL(_VAL_) SET_REG(ADR_WIFI_11GN_TX_FFT_SCALE_REG1,_VAL_,31,0x7fffffff)
+#define SET_RO_TX_CNT_R_11GN_TX(_VAL_) SET_REG(ADR_WIFI_11GN_TX_PKT_CNT_SENT_REG,_VAL_,0,0x00000000)
+#define SET_RG_DEBUG_SEL_11GN_TX(_VAL_) SET_REG(ADR_WIFI_11GN_TX_DEBUG_SEL_REG,_VAL_,8,0xfffff0ff)
+#define SET_RG_RESERVED_11GN_TX(_VAL_) SET_REG(ADR_WIFI_11GN_TX_RESERVED_REG,_VAL_,0,0x00000000)
+#define SET_RG_POS_DES_L_EXT_11GN_RX(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_000,_VAL_,0,0xfffffff0)
+#define SET_RG_PRE_DES_DLY_11GN_RX(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_000,_VAL_,4,0xffffff0f)
+#define SET_RG_RESERVED_11GN_RX(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_001,_VAL_,0,0x00000000)
+#define SET_RG_HT40_TR_LPF_KI(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_002,_VAL_,0,0xfffffff0)
+#define SET_RG_HT40_TR_LPF_KP(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_002,_VAL_,4,0xffffff0f)
+#define SET_RG_HT40_SYM_BOUND_CNT(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_002,_VAL_,8,0xffff80ff)
+#define SET_RG_HT20_TR_LPF_KI(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_003,_VAL_,0,0xfffffff0)
+#define SET_RG_HT20_TR_LPF_KP(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_003,_VAL_,4,0xffffff0f)
+#define SET_RG_TR_LPF_RATE_GN(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_003,_VAL_,8,0xc00000ff)
+#define SET_RG_CR_LPF_KI_GN(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_004_,_VAL_,0,0xfffffff8)
+#define SET_RG_HT20_SYM_BOUND_CNT(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_004_,_VAL_,8,0xffff80ff)
+#define SET_RG_XSCOR32_RATIO(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_004_,_VAL_,16,0xff80ffff)
+#define SET_RG_ATCOR64_CNT_LMT(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_004_,_VAL_,24,0x80ffffff)
+#define SET_RG_ATCOR16_CNT_LMT2(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_005,_VAL_,8,0xffff80ff)
+#define SET_RG_ATCOR16_CNT_LMT1(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_005,_VAL_,16,0xff80ffff)
+#define SET_RG_ATCOR16_RATIO_SB(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_005,_VAL_,24,0x80ffffff)
+#define SET_RG_XSCOR64_CNT_LMT2(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_006_,_VAL_,16,0xff80ffff)
+#define SET_RG_XSCOR64_CNT_LMT1(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_006_,_VAL_,24,0x80ffffff)
+#define SET_RG_HT20_RX_FFT_SCALE(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_007_,_VAL_,0,0xfffffc00)
+#define SET_RG_VITERBI_AB_SWAP(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_007_,_VAL_,16,0xfffeffff)
+#define SET_RG_ATCOR16_CNT_TH(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_007_,_VAL_,24,0xf0ffffff)
+#define SET_RG_NORMSQUARE_LOW_SNR_7(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_008,_VAL_,0,0xffffff00)
+#define SET_RG_NORMSQUARE_LOW_SNR_6(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_008,_VAL_,8,0xffff00ff)
+#define SET_RG_NORMSQUARE_LOW_SNR_5(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_008,_VAL_,16,0xff00ffff)
+#define SET_RG_NORMSQUARE_LOW_SNR_4(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_008,_VAL_,24,0x00ffffff)
+#define SET_RG_NORMSQUARE_LOW_SNR_8(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_009,_VAL_,24,0x00ffffff)
+#define SET_RG_NORMSQUARE_SNR_3(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_010_,_VAL_,0,0xffffff00)
+#define SET_RG_NORMSQUARE_SNR_2(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_010_,_VAL_,8,0xffff00ff)
+#define SET_RG_NORMSQUARE_SNR_1(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_010_,_VAL_,16,0xff00ffff)
+#define SET_RG_NORMSQUARE_SNR_0(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_010_,_VAL_,24,0x00ffffff)
+#define SET_RG_NORMSQUARE_SNR_7(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_011,_VAL_,0,0xffffff00)
+#define SET_RG_NORMSQUARE_SNR_6(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_011,_VAL_,8,0xffff00ff)
+#define SET_RG_NORMSQUARE_SNR_5(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_011,_VAL_,16,0xff00ffff)
+#define SET_RG_NORMSQUARE_SNR_4(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_011,_VAL_,24,0x00ffffff)
+#define SET_RG_NORMSQUARE_SNR_8(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_012,_VAL_,24,0x00ffffff)
+#define SET_RG_SNR_TH_64QAM(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_013,_VAL_,0,0xffffff80)
+#define SET_RG_SNR_TH_16QAM(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_013,_VAL_,8,0xffff80ff)
+#define SET_RG_ATCOR16_CNT_PLUS_LMT2(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_014,_VAL_,0,0xffffff80)
+#define SET_RG_ATCOR16_CNT_PLUS_LMT1(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_014,_VAL_,8,0xffff80ff)
+#define SET_RG_SYM_BOUND_METHOD(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_014,_VAL_,16,0xfffcffff)
+#define SET_RG_HT40_RX_FFT_SCALE(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_015,_VAL_,0,0xfffffc00)
+#define SET_RG_ERASE_SC_NUM3(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_016,_VAL_,0,0xffffff80)
+#define SET_RG_SC_CTRL3(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_016,_VAL_,7,0xffffff7f)
+#define SET_RG_ERASE_SC_NUM2(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_016,_VAL_,8,0xffff80ff)
+#define SET_RG_SC_CTRL2(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_016,_VAL_,15,0xffff7fff)
+#define SET_RG_ERASE_SC_NUM1(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_016,_VAL_,16,0xff80ffff)
+#define SET_RG_SC_CTRL1(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_016,_VAL_,23,0xff7fffff)
+#define SET_RG_ERASE_SC_NUM0(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_016,_VAL_,24,0x80ffffff)
+#define SET_RG_SC_CTRL0(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_016,_VAL_,31,0x7fffffff)
+#define SET_RG_ERASE_SC_NUM7(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_017,_VAL_,0,0xffffff80)
+#define SET_RG_SC_CTRL7(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_017,_VAL_,7,0xffffff7f)
+#define SET_RG_ERASE_SC_NUM6(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_017,_VAL_,8,0xffff80ff)
+#define SET_RG_SC_CTRL6(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_017,_VAL_,15,0xffff7fff)
+#define SET_RG_ERASE_SC_NUM5(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_017,_VAL_,16,0xff80ffff)
+#define SET_RG_SC_CTRL5(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_017,_VAL_,23,0xff7fffff)
+#define SET_RG_ERASE_SC_NUM4(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_017,_VAL_,24,0x80ffffff)
+#define SET_RG_SC_CTRL4(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_017,_VAL_,31,0x7fffffff)
+#define SET_RG_BIST_EN_CCFO(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_032,_VAL_,0,0xfffffffe)
+#define SET_RG_BIST_MODE_CCFO(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_032,_VAL_,4,0xffffffef)
+#define SET_RO_BIST_DONE_CCFO_1(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_032,_VAL_,16,0xfffeffff)
+#define SET_RO_BIST_FAIL_CCFO_1(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_032,_VAL_,17,0xfffdffff)
+#define SET_RO_BIST_DONE_CCFO_0(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_032,_VAL_,20,0xffefffff)
+#define SET_RO_BIST_FAIL_CCFO_0(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_032,_VAL_,21,0xffdfffff)
+#define SET_RG_BIST_EN_VTB(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_033,_VAL_,0,0xfffffffe)
+#define SET_RG_BIST_MODE_VTB(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_033,_VAL_,4,0xffffffef)
+#define SET_RO_BIST_DONE_VTB_3(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_033,_VAL_,16,0xfffeffff)
+#define SET_RO_BIST_FAIL_VTB_3(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_033,_VAL_,17,0xfffdffff)
+#define SET_RO_BIST_DONE_VTB_2(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_033,_VAL_,20,0xffefffff)
+#define SET_RO_BIST_FAIL_VTB_2(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_033,_VAL_,21,0xffdfffff)
+#define SET_RO_BIST_DONE_VTB_1(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_033,_VAL_,24,0xfeffffff)
+#define SET_RO_BIST_FAIL_VTB_1(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_033,_VAL_,25,0xfdffffff)
+#define SET_RO_BIST_DONE_VTB_0(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_033,_VAL_,28,0xefffffff)
+#define SET_RO_BIST_FAIL_VTB_0(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_033,_VAL_,29,0xdfffffff)
+#define SET_RG_PWRON_DLY_TH_11GN_RX(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_039,_VAL_,0,0xffffff00)
+#define SET_RG_SB_START_CNT(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_039,_VAL_,8,0xffff80ff)
+#define SET_RG_CCA_POW_CNT_TH(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_040,_VAL_,4,0xffffff0f)
+#define SET_RG_CCA_POW_SHORT_CNT_LMT(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_040,_VAL_,8,0xfffff8ff)
+#define SET_RG_CCA_POW_TH(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_040,_VAL_,16,0x0000ffff)
+#define SET_RG_POW16_CNT_TH(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_048,_VAL_,4,0xffffff0f)
+#define SET_RG_POW16_SHORT_CNT_LMT(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_048,_VAL_,8,0xfffff8ff)
+#define SET_RG_POW16_TH_L(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_048,_VAL_,24,0x00ffffff)
+#define SET_RG_XSCOR16_SHORT_CNT_LMT(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_049,_VAL_,0,0xfffffff8)
+#define SET_RG_XSCOR16_RATIO(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_049,_VAL_,8,0xffff80ff)
+#define SET_RG_ATCOR16_SHORT_CNT_LMT(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_049,_VAL_,16,0xfff8ffff)
+#define SET_RG_ATCOR16_RATIO_CCD(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_049,_VAL_,24,0x80ffffff)
+#define SET_RG_ATCOR64_ACC_LMT(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_050,_VAL_,0,0xffffff80)
+#define SET_RG_ATCOR16_SHORT_CNT_LMT2(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_050,_VAL_,16,0xfff8ffff)
+#define SET_RG_CCFO_CNT_LMT(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_051,_VAL_,0,0xffffff80)
+#define SET_RG_BYPASS_COARSE_FREQ(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_051,_VAL_,8,0xfffffeff)
+#define SET_RG_CCFO_GAIN_BY2(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_051,_VAL_,9,0xfffffdff)
+#define SET_RG_XSCOR64_RATIO_SB(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_051,_VAL_,16,0xff80ffff)
+#define SET_RG_5G_CCFO_CNT_LMT(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_052,_VAL_,0,0xffffff80)
+#define SET_RG_5G_BYPASS_COARSE_FREQ(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_052,_VAL_,8,0xfffffeff)
+#define SET_RG_5G_CCFO_GAIN_BY2(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_052,_VAL_,9,0xfffffdff)
+#define SET_RG_ACS_INI_PM_ALL0(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_076,_VAL_,0,0xfffffffe)
+#define SET_RG_VITERBI_TB_BITS(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_076,_VAL_,24,0x00ffffff)
+#define SET_RG_CR_CNT_UPDATE_SGI(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_087,_VAL_,0,0xfffffe00)
+#define SET_RG_TR_CNT_UPDATE_SGI(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_087,_VAL_,16,0xfe00ffff)
+#define SET_RG_CR_CNT_UPDATE(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_088,_VAL_,0,0xfffffe00)
+#define SET_RG_TR_CNT_UPDATE(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_088,_VAL_,16,0xfe00ffff)
+#define SET_RG_CPE_SEL_64QAM(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_089,_VAL_,16,0xfffeffff)
+#define SET_RG_CPE_SEL_16QAM(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_089,_VAL_,17,0xfffdffff)
+#define SET_RG_CPE_SEL_QPSK(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_089,_VAL_,18,0xfffbffff)
+#define SET_RG_CPE_SEL_BPSK(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_089,_VAL_,19,0xfff7ffff)
+#define SET_RG_BYPASS_CPE_MA(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_096,_VAL_,4,0xffffffef)
+#define SET_RG_CHSMTH_COEF(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_098,_VAL_,16,0xfffcffff)
+#define SET_RG_CHSMTH_EN(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_098,_VAL_,18,0xfffbffff)
+#define SET_RG_CHEST_DD_FACTOR(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_098,_VAL_,24,0xf8ffffff)
+#define SET_RG_CH_UPDATE(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_098,_VAL_,31,0x7fffffff)
+#define SET_RG_FMT_DET_MM_TH(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_100,_VAL_,0,0xffffff00)
+#define SET_RG_FMT_DET_GF_TH(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_100,_VAL_,8,0xffff00ff)
+#define SET_RG_DO_NOT_CHECK_L_RATE(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_100,_VAL_,25,0xfdffffff)
+#define SET_RG_NEW_PILOT_AVG(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_101,_VAL_,0,0xfffffffe)
+#define SET_RG_NEW_SB(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_101,_VAL_,4,0xffffffef)
+#define SET_RG_ATCOR64_FREQ_START(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_101,_VAL_,8,0xffff80ff)
+#define SET_RG_L_LENGTH_MAX(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_101,_VAL_,16,0xf000ffff)
+#define SET_RG_ATCOR16_CCA_GAIN(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_101,_VAL_,28,0xcfffffff)
+#define SET_RG_PSDU_TIME_OFFSET_GF(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_102,_VAL_,0,0xffff0000)
+#define SET_RG_PSDU_TIME_OFFSET_MF(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_102,_VAL_,16,0x0000ffff)
+#define SET_RG_PSDU_TIME_OFFSET_LEGACY(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_103,_VAL_,0,0xffff0000)
+#define SET_RG_INTRUP_RX_11GN_CLEAR(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_241,_VAL_,0,0xfffffffe)
+#define SET_RG_INTRUP_RX_11GN_MASK(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_241,_VAL_,4,0xffffffef)
+#define SET_RG_INTRUP_RX_11GN_TRIG(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_241,_VAL_,8,0xfffff0ff)
+#define SET_RO_INTRUP_RX_11GN(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_241,_VAL_,16,0xfffeffff)
+#define SET_RO_STBC_PACKET_CNT(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_245,_VAL_,0,0xffff0000)
+#define SET_RO_STBC_PACKET_ERR_CNT(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_245,_VAL_,16,0x0000ffff)
+#define SET_RO_11GN_SNR(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_246,_VAL_,0,0xffffff80)
+#define SET_RO_11GN_NOISE_PWR(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_246,_VAL_,8,0xffff80ff)
+#define SET_RO_11GN_RCPI(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_246,_VAL_,16,0xff80ffff)
+#define SET_RO_11GN_SIGNAL_PWR(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_246,_VAL_,24,0x80ffffff)
+#define SET_RO_11GN_FREQ_OS_LTS(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_247,_VAL_,0,0xffff8000)
+#define SET_RO_11GN_HT_SIGNAL_FIELD_47_24(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_248,_VAL_,0,0xff000000)
+#define SET_RO_11GN_HT_SIGNAL_FIELD_23_0(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_249,_VAL_,0,0xff000000)
+#define SET_RO_11GN_PACKET_ERR_CNT(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_250,_VAL_,0,0xffff0000)
+#define SET_RO_11GN_SERVICE_FIELD(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_250,_VAL_,16,0x0000ffff)
+#define SET_RO_11GN_PACKET_CNT(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_251,_VAL_,0,0xffff0000)
+#define SET_RO_11GN_CCA_CNT(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_251,_VAL_,16,0x0000ffff)
+#define SET_RO_11GN_L_SIGNAL_FIELD(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_252,_VAL_,0,0xff000000)
+#define SET_RO_AMPDU_PACKET_CNT(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_253,_VAL_,0,0xffff0000)
+#define SET_RO_AMPDU_PACKET_ERR_CNT(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_253,_VAL_,16,0x0000ffff)
+#define SET_RG_DAGC_CNT_TH(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_254,_VAL_,0,0xfffffffc)
+#define SET_RG_RATE_MCS_STAT(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_254,_VAL_,16,0xfff0ffff)
+#define SET_RG_PACKET_STAT_EN_11GN_RX(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_254,_VAL_,20,0xffefffff)
+#define SET_RG_SOFT_RST_N_11GN_RX(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_255,_VAL_,0,0xfffffffe)
+#define SET_RG_RIFS_EN(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_255,_VAL_,1,0xfffffffd)
+#define SET_RG_STBC_EN(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_255,_VAL_,2,0xfffffffb)
+#define SET_RG_COR_SEL(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_255,_VAL_,3,0xfffffff7)
+#define SET_RG_INI_PHASE(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_255,_VAL_,4,0xffffffcf)
+#define SET_RG_CCA_PWR_SEL(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_255,_VAL_,9,0xfffffdff)
+#define SET_RG_CCA_XSCOR_PWR_SEL(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_255,_VAL_,10,0xfffffbff)
+#define SET_RG_CCA_XSCOR_AVGPWR_SEL(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_255,_VAL_,11,0xfffff7ff)
+#define SET_RG_DEBUG_SEL_11GN_RX(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_255,_VAL_,12,0xffff0fff)
+#define SET_RG_POST_CLK_EN(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_255,_VAL_,16,0xfffeffff)
+#define SET_RG_THL_ED(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_00,_VAL_,0,0xffffffc0)
+#define SET_RG_THH_ED(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_00,_VAL_,8,0xffffc0ff)
+#define SET_RG_THL_RATIO(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_00,_VAL_,16,0xff00ffff)
+#define SET_RG_THH_RATIO(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_00,_VAL_,24,0x00ffffff)
+#define SET_RG_PW_MIN(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_01,_VAL_,0,0xfffff000)
+#define SET_RG_PW_MAX(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_01,_VAL_,16,0xf000ffff)
+#define SET_RG_PERIOD_MIN(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_02,_VAL_,0,0xfffff000)
+#define SET_RG_PERIOD_MAX(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_02,_VAL_,16,0xf000ffff)
+#define SET_RG_TIME_PERIOD(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_03,_VAL_,0,0xfffff000)
+#define SET_RG_PULSE_NUMBER(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_03,_VAL_,20,0xff8fffff)
+#define SET_RG_ALPHA_FINE(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_03,_VAL_,24,0xf8ffffff)
+#define SET_RG_ALPHA_COARSE(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_03,_VAL_,28,0xcfffffff)
+#define SET_RG_RADAR_EN(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_04,_VAL_,0,0xfffffffe)
+#define SET_RG_TOLERANCE_PERIOD(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_04,_VAL_,16,0xffc0ffff)
+#define SET_RG_TOLERANCE_PW(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_04,_VAL_,24,0xc0ffffff)
+#define SET_RO_RADAR_DET_NUM(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_RO,_VAL_,0,0xfffffff8)
+#define SET_RO_RADAR_DET_OUT(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_RO,_VAL_,4,0xffffffef)
+#define SET_RO_RADAR_VALID(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_RO,_VAL_,8,0xfffffeff)
+#define SET_RO_PW(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_RO,_VAL_,16,0xf000ffff)
+#define SET_RO_PW_ARRAY_0(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_DB_A0_RO,_VAL_,0,0xfffff000)
+#define SET_RO_PW_ARRAY_1(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_DB_A0_RO,_VAL_,16,0xf000ffff)
+#define SET_RO_PW_ARRAY_2(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_DB_A1_RO,_VAL_,0,0xfffff000)
+#define SET_RO_PW_ARRAY_3(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_DB_A1_RO,_VAL_,16,0xf000ffff)
+#define SET_RO_PW_ARRAY_4(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_DB_A2_RO,_VAL_,0,0xfffff000)
+#define SET_RO_PW_ARRAY_5(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_DB_A2_RO,_VAL_,16,0xf000ffff)
+#define SET_RO_PERIOD_ARRAY_0(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_DB_P0_RO,_VAL_,0,0xfffff000)
+#define SET_RO_PERIOD_ARRAY_1(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_DB_P0_RO,_VAL_,16,0xf000ffff)
+#define SET_RO_PERIOD_ARRAY_2(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_DB_P1_RO,_VAL_,0,0xfffff000)
+#define SET_RO_PERIOD_ARRAY_3(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_DB_P1_RO,_VAL_,16,0xf000ffff)
+#define SET_RO_PERIOD_ARRAY_4(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_DB_P2_RO,_VAL_,0,0xfffff000)
+#define SET_RO_PERIOD_ARRAY_5(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_DB_P2_RO,_VAL_,16,0xf000ffff)
+#define SET_RG_PW_CHIRP_MIN(_VAL_) SET_REG(ADR_WIFI_RADAR_CHIRP_REG,_VAL_,0,0xfffff000)
+#define SET_RG_PW_CHIRP_MAX(_VAL_) SET_REG(ADR_WIFI_RADAR_CHIRP_REG,_VAL_,16,0xf000ffff)
+#define SET_CPU_QUE_POP_ALT(_VAL_) SET_REG(ADR_MB_CPU_INT_ALT,_VAL_,0,0xfffffffe)
+#define SET_CPU_INT_ALT(_VAL_) SET_REG(ADR_MB_CPU_INT_ALT,_VAL_,2,0xfffffffb)
+#define SET_CPU_QUE_POP(_VAL_) SET_REG(ADR_MB_CPU_INT,_VAL_,0,0xfffffffe)
+#define SET_CPU_INT(_VAL_) SET_REG(ADR_MB_CPU_INT,_VAL_,2,0xfffffffb)
+#define SET_CPU_ID_TB0(_VAL_) SET_REG(ADR_CPU_ID_TB0,_VAL_,0,0x00000000)
+#define SET_CPU_ID_TB1(_VAL_) SET_REG(ADR_CPU_ID_TB1,_VAL_,0,0x00000000)
+#define SET_HW_PKTID(_VAL_) SET_REG(ADR_CH0_TRIG_1,_VAL_,0,0xfffff800)
+#define SET_CH0_INT_ADDR(_VAL_) SET_REG(ADR_CH0_TRIG_0,_VAL_,0,0x00000000)
+#define SET_PRI_HW_PKTID(_VAL_) SET_REG(ADR_CH0_PRI_TRIG,_VAL_,0,0xfffff800)
+#define SET_CH0_FULL(_VAL_) SET_REG(ADR_MCU_STATUS,_VAL_,0,0xfffffffe)
+#define SET_FF0_EMPTY(_VAL_) SET_REG(ADR_MCU_STATUS,_VAL_,1,0xfffffffd)
+#define SET_CH2_FULL(_VAL_) SET_REG(ADR_MCU_STATUS,_VAL_,4,0xffffffef)
+#define SET_FF2_EMPTY(_VAL_) SET_REG(ADR_MCU_STATUS,_VAL_,5,0xffffffdf)
+#define SET_RLS_BUSY(_VAL_) SET_REG(ADR_MCU_STATUS,_VAL_,9,0xfffffdff)
+#define SET_RLS_COUNT_CLR(_VAL_) SET_REG(ADR_MCU_STATUS,_VAL_,10,0xfffffbff)
+#define SET_RTN_COUNT_CLR(_VAL_) SET_REG(ADR_MCU_STATUS,_VAL_,11,0xfffff7ff)
+#define SET_RLS_COUNT(_VAL_) SET_REG(ADR_MCU_STATUS,_VAL_,16,0xff00ffff)
+#define SET_RTN_COUNT(_VAL_) SET_REG(ADR_MCU_STATUS,_VAL_,24,0x00ffffff)
+#define SET_FF0_CNT(_VAL_) SET_REG(ADR_RD_IN_FFCNT1,_VAL_,0,0xffffffe0)
+#define SET_FF1_CNT(_VAL_) SET_REG(ADR_RD_IN_FFCNT1,_VAL_,5,0xfffffe1f)
+#define SET_FF3_CNT(_VAL_) SET_REG(ADR_RD_IN_FFCNT1,_VAL_,11,0xffffc7ff)
+#define SET_FF5_CNT(_VAL_) SET_REG(ADR_RD_IN_FFCNT1,_VAL_,17,0xfff1ffff)
+#define SET_FF6_CNT(_VAL_) SET_REG(ADR_RD_IN_FFCNT1,_VAL_,20,0xff8fffff)
+#define SET_FF7_CNT(_VAL_) SET_REG(ADR_RD_IN_FFCNT1,_VAL_,23,0xfc7fffff)
+#define SET_FF8_CNT(_VAL_) SET_REG(ADR_RD_IN_FFCNT1,_VAL_,26,0xe3ffffff)
+#define SET_FF9_CNT(_VAL_) SET_REG(ADR_RD_IN_FFCNT1,_VAL_,29,0x1fffffff)
+#define SET_FF10_CNT(_VAL_) SET_REG(ADR_RD_IN_FFCNT2,_VAL_,0,0xfffffff8)
+#define SET_FF11_CNT(_VAL_) SET_REG(ADR_RD_IN_FFCNT2,_VAL_,3,0xffffffc7)
+#define SET_FF12_CNT(_VAL_) SET_REG(ADR_RD_IN_FFCNT2,_VAL_,6,0xfffffe3f)
+#define SET_FF13_CNT(_VAL_) SET_REG(ADR_RD_IN_FFCNT2,_VAL_,9,0xfffff1ff)
+#define SET_FF14_CNT(_VAL_) SET_REG(ADR_RD_IN_FFCNT2,_VAL_,12,0xffff8fff)
+#define SET_FF15_CNT(_VAL_) SET_REG(ADR_RD_IN_FFCNT2,_VAL_,15,0xfffc7fff)
+#define SET_FF4_CNT(_VAL_) SET_REG(ADR_RD_IN_FFCNT2,_VAL_,18,0xff83ffff)
+#define SET_FF2_CNT(_VAL_) SET_REG(ADR_RD_IN_FFCNT2,_VAL_,23,0xfc7fffff)
+#define SET_CH0_FULL_ALT(_VAL_) SET_REG(ADR_RD_FFIN_FULL,_VAL_,0,0xfffffffe)
+#define SET_CH1_FULL(_VAL_) SET_REG(ADR_RD_FFIN_FULL,_VAL_,1,0xfffffffd)
+#define SET_CH2_FULL_ALT(_VAL_) SET_REG(ADR_RD_FFIN_FULL,_VAL_,2,0xfffffffb)
+#define SET_CH3_FULL(_VAL_) SET_REG(ADR_RD_FFIN_FULL,_VAL_,3,0xfffffff7)
+#define SET_CH4_FULL(_VAL_) SET_REG(ADR_RD_FFIN_FULL,_VAL_,4,0xffffffef)
+#define SET_CH5_FULL(_VAL_) SET_REG(ADR_RD_FFIN_FULL,_VAL_,5,0xffffffdf)
+#define SET_CH6_FULL(_VAL_) SET_REG(ADR_RD_FFIN_FULL,_VAL_,6,0xffffffbf)
+#define SET_CH7_FULL(_VAL_) SET_REG(ADR_RD_FFIN_FULL,_VAL_,7,0xffffff7f)
+#define SET_CH8_FULL(_VAL_) SET_REG(ADR_RD_FFIN_FULL,_VAL_,8,0xfffffeff)
+#define SET_CH9_FULL(_VAL_) SET_REG(ADR_RD_FFIN_FULL,_VAL_,9,0xfffffdff)
+#define SET_CH10_FULL(_VAL_) SET_REG(ADR_RD_FFIN_FULL,_VAL_,10,0xfffffbff)
+#define SET_CH11_FULL(_VAL_) SET_REG(ADR_RD_FFIN_FULL,_VAL_,11,0xfffff7ff)
+#define SET_CH12_FULL(_VAL_) SET_REG(ADR_RD_FFIN_FULL,_VAL_,12,0xffffefff)
+#define SET_CH13_FULL(_VAL_) SET_REG(ADR_RD_FFIN_FULL,_VAL_,13,0xffffdfff)
+#define SET_CH14_FULL(_VAL_) SET_REG(ADR_RD_FFIN_FULL,_VAL_,14,0xffffbfff)
+#define SET_CH15_FULL(_VAL_) SET_REG(ADR_RD_FFIN_FULL,_VAL_,15,0xffff7fff)
+#define SET_HW_PKTID_ALT(_VAL_) SET_REG(ADR_CH2_TRIG_ALT,_VAL_,0,0xfffff800)
+#define SET_CH2_INT_ADDR_ALT(_VAL_) SET_REG(ADR_CH2_INT_ADDR_ALT,_VAL_,0,0x00000000)
+#define SET_HALT_CH1(_VAL_) SET_REG(ADR_MBOX_HALT_CFG,_VAL_,1,0xfffffffd)
+#define SET_HALT_CH3(_VAL_) SET_REG(ADR_MBOX_HALT_CFG,_VAL_,3,0xfffffff7)
+#define SET_HALT_CH4(_VAL_) SET_REG(ADR_MBOX_HALT_CFG,_VAL_,4,0xffffffef)
+#define SET_HALT_CH5(_VAL_) SET_REG(ADR_MBOX_HALT_CFG,_VAL_,5,0xffffffdf)
+#define SET_HALT_CH6(_VAL_) SET_REG(ADR_MBOX_HALT_CFG,_VAL_,6,0xffffffbf)
+#define SET_HALT_CH7(_VAL_) SET_REG(ADR_MBOX_HALT_CFG,_VAL_,7,0xffffff7f)
+#define SET_HALT_CH8(_VAL_) SET_REG(ADR_MBOX_HALT_CFG,_VAL_,8,0xfffffeff)
+#define SET_HALT_CH9(_VAL_) SET_REG(ADR_MBOX_HALT_CFG,_VAL_,9,0xfffffdff)
+#define SET_HALT_CH10(_VAL_) SET_REG(ADR_MBOX_HALT_CFG,_VAL_,10,0xfffffbff)
+#define SET_HALT_CH11(_VAL_) SET_REG(ADR_MBOX_HALT_CFG,_VAL_,11,0xfffff7ff)
+#define SET_HALT_CH12(_VAL_) SET_REG(ADR_MBOX_HALT_CFG,_VAL_,12,0xffffefff)
+#define SET_HALT_CH13(_VAL_) SET_REG(ADR_MBOX_HALT_CFG,_VAL_,13,0xffffdfff)
+#define SET_HALT_CH14(_VAL_) SET_REG(ADR_MBOX_HALT_CFG,_VAL_,14,0xffffbfff)
+#define SET_STOP_MBOX_OUT(_VAL_) SET_REG(ADR_MBOX_HALT_CFG,_VAL_,16,0xfffeffff)
+#define SET_STOP_MBOX_IN(_VAL_) SET_REG(ADR_MBOX_HALT_CFG,_VAL_,17,0xfffdffff)
+#define SET_MB_ERR_AUTO_HALT_EN(_VAL_) SET_REG(ADR_MBOX_HALT_CFG,_VAL_,20,0xffefffff)
+#define SET_MB_EXCEPT_CLR(_VAL_) SET_REG(ADR_MBOX_HALT_CFG,_VAL_,21,0xffdfffff)
+#define SET_CH1_HALT_STS(_VAL_) SET_REG(ADR_MBOX_HALT_STS,_VAL_,1,0xfffffffd)
+#define SET_CH3_HALT_STS(_VAL_) SET_REG(ADR_MBOX_HALT_STS,_VAL_,3,0xfffffff7)
+#define SET_CH4_HALT_STS(_VAL_) SET_REG(ADR_MBOX_HALT_STS,_VAL_,4,0xffffffef)
+#define SET_CH5_HALT_STS(_VAL_) SET_REG(ADR_MBOX_HALT_STS,_VAL_,5,0xffffffdf)
+#define SET_CH6_HALT_STS(_VAL_) SET_REG(ADR_MBOX_HALT_STS,_VAL_,6,0xffffffbf)
+#define SET_CH7_HALT_STS(_VAL_) SET_REG(ADR_MBOX_HALT_STS,_VAL_,7,0xffffff7f)
+#define SET_CH8_HALT_STS(_VAL_) SET_REG(ADR_MBOX_HALT_STS,_VAL_,8,0xfffffeff)
+#define SET_CH9_HALT_STS(_VAL_) SET_REG(ADR_MBOX_HALT_STS,_VAL_,9,0xfffffdff)
+#define SET_CH10_HALT_STS(_VAL_) SET_REG(ADR_MBOX_HALT_STS,_VAL_,10,0xfffffbff)
+#define SET_CH11_HALT_STS(_VAL_) SET_REG(ADR_MBOX_HALT_STS,_VAL_,11,0xfffff7ff)
+#define SET_CH12_HALT_STS(_VAL_) SET_REG(ADR_MBOX_HALT_STS,_VAL_,12,0xffffefff)
+#define SET_CH13_HALT_STS(_VAL_) SET_REG(ADR_MBOX_HALT_STS,_VAL_,13,0xffffdfff)
+#define SET_CH14_HALT_STS(_VAL_) SET_REG(ADR_MBOX_HALT_STS,_VAL_,14,0xffffbfff)
+#define SET_STOP_MBOX_OUT_SUCCESS(_VAL_) SET_REG(ADR_MBOX_HALT_STS,_VAL_,16,0xfffeffff)
+#define SET_MB_EXCEPT_CASE(_VAL_) SET_REG(ADR_MBOX_HALT_STS,_VAL_,24,0x00ffffff)
+#define SET_MB_DBG_TIME_STEP(_VAL_) SET_REG(ADR_MB_DBG_CFG1,_VAL_,0,0xffff0000)
+#define SET_DBG_TYPE(_VAL_) SET_REG(ADR_MB_DBG_CFG1,_VAL_,16,0xfffcffff)
+#define SET_MB_DBG_CLR(_VAL_) SET_REG(ADR_MB_DBG_CFG1,_VAL_,18,0xfffbffff)
+#define SET_DBG_ALC_LOG_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG1,_VAL_,19,0xfff7ffff)
+#define SET_MB_DBG_COUNTER_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG1,_VAL_,24,0xfeffffff)
+#define SET_MB_DBG_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG1,_VAL_,31,0x7fffffff)
+#define SET_MB_DBG_RECORD_CNT(_VAL_) SET_REG(ADR_MB_DBG_CFG2,_VAL_,0,0xffff0000)
+#define SET_MB_DBG_LENGTH(_VAL_) SET_REG(ADR_MB_DBG_CFG2,_VAL_,16,0x0000ffff)
+#define SET_MB_DBG_CFG_ADDR(_VAL_) SET_REG(ADR_MB_DBG_CFG3,_VAL_,0,0x00000000)
+#define SET_DBG_HWID0_WR_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,0,0xfffffffe)
+#define SET_DBG_HWID1_WR_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,1,0xfffffffd)
+#define SET_DBG_HWID2_WR_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,2,0xfffffffb)
+#define SET_DBG_HWID3_WR_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,3,0xfffffff7)
+#define SET_DBG_HWID4_WR_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,4,0xffffffef)
+#define SET_DBG_HWID5_WR_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,5,0xffffffdf)
+#define SET_DBG_HWID6_WR_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,6,0xffffffbf)
+#define SET_DBG_HWID7_WR_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,7,0xffffff7f)
+#define SET_DBG_HWID8_WR_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,8,0xfffffeff)
+#define SET_DBG_HWID9_WR_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,9,0xfffffdff)
+#define SET_DBG_HWID10_WR_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,10,0xfffffbff)
+#define SET_DBG_HWID11_WR_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,11,0xfffff7ff)
+#define SET_DBG_HWID12_WR_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,12,0xffffefff)
+#define SET_DBG_HWID13_WR_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,13,0xffffdfff)
+#define SET_DBG_HWID14_WR_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,14,0xffffbfff)
+#define SET_DBG_HWID15_WR_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,15,0xffff7fff)
+#define SET_DBG_HWID0_RD_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,16,0xfffeffff)
+#define SET_DBG_HWID1_RD_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,17,0xfffdffff)
+#define SET_DBG_HWID2_RD_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,18,0xfffbffff)
+#define SET_DBG_HWID3_RD_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,19,0xfff7ffff)
+#define SET_DBG_HWID4_RD_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,20,0xffefffff)
+#define SET_DBG_HWID5_RD_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,21,0xffdfffff)
+#define SET_DBG_HWID6_RD_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,22,0xffbfffff)
+#define SET_DBG_HWID7_RD_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,23,0xff7fffff)
+#define SET_DBG_HWID8_RD_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,24,0xfeffffff)
+#define SET_DBG_HWID9_RD_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,25,0xfdffffff)
+#define SET_DBG_HWID10_RD_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,26,0xfbffffff)
+#define SET_DBG_HWID11_RD_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,27,0xf7ffffff)
+#define SET_DBG_HWID12_RD_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,28,0xefffffff)
+#define SET_DBG_HWID13_RD_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,29,0xdfffffff)
+#define SET_DBG_HWID14_RD_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,30,0xbfffffff)
+#define SET_DBG_HWID15_RD_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,31,0x7fffffff)
+#define SET_MB_OUT_QUEUE_EN(_VAL_) SET_REG(ADR_MB_OUT_QUEUE_CFG,_VAL_,1,0xfffffffd)
+#define SET_OUT_QUEUE_FLUSH_ID(_VAL_) SET_REG(ADR_MB_OUT_QUEUE_FLUSH,_VAL_,0,0xffffff80)
+#define SET_OUT_QUEUE_FLUSH_MODE(_VAL_) SET_REG(ADR_MB_OUT_QUEUE_FLUSH,_VAL_,0,0xfffffffc)
+#define SET_OUT_QUEUE_FLUSH_SEL(_VAL_) SET_REG(ADR_MB_OUT_QUEUE_FLUSH,_VAL_,8,0xfffff0ff)
+#define SET_FFO0_CNT(_VAL_) SET_REG(ADR_RD_FFOUT_CNT1,_VAL_,0,0xffffffe0)
+#define SET_FFO1_CNT(_VAL_) SET_REG(ADR_RD_FFOUT_CNT1,_VAL_,5,0xfffffc1f)
+#define SET_FFO2_CNT(_VAL_) SET_REG(ADR_RD_FFOUT_CNT1,_VAL_,10,0xffffc3ff)
+#define SET_FFO3_CNT(_VAL_) SET_REG(ADR_RD_FFOUT_CNT1,_VAL_,15,0xfff07fff)
+#define SET_FFO4_CNT(_VAL_) SET_REG(ADR_RD_FFOUT_CNT1,_VAL_,20,0xffcfffff)
+#define SET_FFO5_CNT(_VAL_) SET_REG(ADR_RD_FFOUT_CNT1,_VAL_,25,0xf1ffffff)
+#define SET_FFO6_CNT(_VAL_) SET_REG(ADR_RD_FFOUT_CNT2,_VAL_,0,0xfffffff0)
+#define SET_FFO7_CNT(_VAL_) SET_REG(ADR_RD_FFOUT_CNT2,_VAL_,5,0xfffffc1f)
+#define SET_FFO8_CNT(_VAL_) SET_REG(ADR_RD_FFOUT_CNT2,_VAL_,10,0xffff83ff)
+#define SET_FFO9_CNT(_VAL_) SET_REG(ADR_RD_FFOUT_CNT2,_VAL_,15,0xfff07fff)
+#define SET_FFO10_CNT(_VAL_) SET_REG(ADR_RD_FFOUT_CNT2,_VAL_,20,0xff0fffff)
+#define SET_FFO11_CNT(_VAL_) SET_REG(ADR_RD_FFOUT_CNT2,_VAL_,25,0xc1ffffff)
+#define SET_FFO12_CNT(_VAL_) SET_REG(ADR_RD_FFOUT_CNT3,_VAL_,0,0xfffffff8)
+#define SET_FFO13_CNT(_VAL_) SET_REG(ADR_RD_FFOUT_CNT3,_VAL_,5,0xffffff9f)
+#define SET_FFO14_CNT(_VAL_) SET_REG(ADR_RD_FFOUT_CNT3,_VAL_,10,0xffff83ff)
+#define SET_FFO15_CNT(_VAL_) SET_REG(ADR_RD_FFOUT_CNT3,_VAL_,15,0xfff87fff)
+#define SET_CH0_FFO_FULL(_VAL_) SET_REG(ADR_RD_FFOUT_FULL,_VAL_,0,0xfffffffe)
+#define SET_CH1_FFO_FULL(_VAL_) SET_REG(ADR_RD_FFOUT_FULL,_VAL_,1,0xfffffffd)
+#define SET_CH2_FFO_FULL(_VAL_) SET_REG(ADR_RD_FFOUT_FULL,_VAL_,2,0xfffffffb)
+#define SET_CH3_FFO_FULL(_VAL_) SET_REG(ADR_RD_FFOUT_FULL,_VAL_,3,0xfffffff7)
+#define SET_CH4_FFO_FULL(_VAL_) SET_REG(ADR_RD_FFOUT_FULL,_VAL_,4,0xffffffef)
+#define SET_CH5_FFO_FULL(_VAL_) SET_REG(ADR_RD_FFOUT_FULL,_VAL_,5,0xffffffdf)
+#define SET_CH6_FFO_FULL(_VAL_) SET_REG(ADR_RD_FFOUT_FULL,_VAL_,6,0xffffffbf)
+#define SET_CH7_FFO_FULL(_VAL_) SET_REG(ADR_RD_FFOUT_FULL,_VAL_,7,0xffffff7f)
+#define SET_CH8_FFO_FULL(_VAL_) SET_REG(ADR_RD_FFOUT_FULL,_VAL_,8,0xfffffeff)
+#define SET_CH9_FFO_FULL(_VAL_) SET_REG(ADR_RD_FFOUT_FULL,_VAL_,9,0xfffffdff)
+#define SET_CH10_FFO_FULL(_VAL_) SET_REG(ADR_RD_FFOUT_FULL,_VAL_,10,0xfffffbff)
+#define SET_CH11_FFO_FULL(_VAL_) SET_REG(ADR_RD_FFOUT_FULL,_VAL_,11,0xfffff7ff)
+#define SET_CH12_FFO_FULL(_VAL_) SET_REG(ADR_RD_FFOUT_FULL,_VAL_,12,0xffffefff)
+#define SET_CH13_FFO_FULL(_VAL_) SET_REG(ADR_RD_FFOUT_FULL,_VAL_,13,0xffffdfff)
+#define SET_CH14_FFO_FULL(_VAL_) SET_REG(ADR_RD_FFOUT_FULL,_VAL_,14,0xffffbfff)
+#define SET_CH15_FFO_FULL(_VAL_) SET_REG(ADR_RD_FFOUT_FULL,_VAL_,15,0xffff7fff)
+#define SET_CH0_LOWTHOLD_INT(_VAL_) SET_REG(ADR_MB_THRESHOLD6,_VAL_,0,0xfffffffe)
+#define SET_CH1_LOWTHOLD_INT(_VAL_) SET_REG(ADR_MB_THRESHOLD6,_VAL_,1,0xfffffffd)
+#define SET_CH2_LOWTHOLD_INT(_VAL_) SET_REG(ADR_MB_THRESHOLD6,_VAL_,2,0xfffffffb)
+#define SET_CH3_LOWTHOLD_INT(_VAL_) SET_REG(ADR_MB_THRESHOLD6,_VAL_,3,0xfffffff7)
+#define SET_CH4_LOWTHOLD_INT(_VAL_) SET_REG(ADR_MB_THRESHOLD6,_VAL_,4,0xffffffef)
+#define SET_CH5_LOWTHOLD_INT(_VAL_) SET_REG(ADR_MB_THRESHOLD6,_VAL_,5,0xffffffdf)
+#define SET_CH6_LOWTHOLD_INT(_VAL_) SET_REG(ADR_MB_THRESHOLD6,_VAL_,6,0xffffffbf)
+#define SET_CH7_LOWTHOLD_INT(_VAL_) SET_REG(ADR_MB_THRESHOLD6,_VAL_,7,0xffffff7f)
+#define SET_CH8_LOWTHOLD_INT(_VAL_) SET_REG(ADR_MB_THRESHOLD6,_VAL_,8,0xfffffeff)
+#define SET_CH9_LOWTHOLD_INT(_VAL_) SET_REG(ADR_MB_THRESHOLD6,_VAL_,9,0xfffffdff)
+#define SET_CH10_LOWTHOLD_INT(_VAL_) SET_REG(ADR_MB_THRESHOLD6,_VAL_,10,0xfffffbff)
+#define SET_CH11_LOWTHOLD_INT(_VAL_) SET_REG(ADR_MB_THRESHOLD6,_VAL_,11,0xfffff7ff)
+#define SET_CH12_LOWTHOLD_INT(_VAL_) SET_REG(ADR_MB_THRESHOLD6,_VAL_,12,0xffffefff)
+#define SET_CH13_LOWTHOLD_INT(_VAL_) SET_REG(ADR_MB_THRESHOLD6,_VAL_,13,0xffffdfff)
+#define SET_CH14_LOWTHOLD_INT(_VAL_) SET_REG(ADR_MB_THRESHOLD6,_VAL_,14,0xffffbfff)
+#define SET_CH15_LOWTHOLD_INT(_VAL_) SET_REG(ADR_MB_THRESHOLD6,_VAL_,15,0xffff7fff)
+#define SET_MB_LOW_THOLD_EN(_VAL_) SET_REG(ADR_MB_THRESHOLD6,_VAL_,31,0x7fffffff)
+#define SET_CH0_LOWTHOLD(_VAL_) SET_REG(ADR_MB_THRESHOLD7,_VAL_,0,0xffffffe0)
+#define SET_CH1_LOWTHOLD(_VAL_) SET_REG(ADR_MB_THRESHOLD7,_VAL_,8,0xffffe0ff)
+#define SET_CH2_LOWTHOLD(_VAL_) SET_REG(ADR_MB_THRESHOLD7,_VAL_,16,0xffe0ffff)
+#define SET_CH3_LOWTHOLD(_VAL_) SET_REG(ADR_MB_THRESHOLD7,_VAL_,24,0xe0ffffff)
+#define SET_CH4_LOWTHOLD(_VAL_) SET_REG(ADR_MB_THRESHOLD8,_VAL_,0,0xffffffe0)
+#define SET_CH5_LOWTHOLD(_VAL_) SET_REG(ADR_MB_THRESHOLD8,_VAL_,8,0xffffe0ff)
+#define SET_CH6_LOWTHOLD(_VAL_) SET_REG(ADR_MB_THRESHOLD8,_VAL_,16,0xffe0ffff)
+#define SET_CH7_LOWTHOLD(_VAL_) SET_REG(ADR_MB_THRESHOLD8,_VAL_,24,0xe0ffffff)
+#define SET_CH8_LOWTHOLD(_VAL_) SET_REG(ADR_MB_THRESHOLD9,_VAL_,0,0xffffffe0)
+#define SET_CH9_LOWTHOLD(_VAL_) SET_REG(ADR_MB_THRESHOLD9,_VAL_,8,0xffffe0ff)
+#define SET_CH10_LOWTHOLD(_VAL_) SET_REG(ADR_MB_THRESHOLD9,_VAL_,16,0xffe0ffff)
+#define SET_CH11_LOWTHOLD(_VAL_) SET_REG(ADR_MB_THRESHOLD9,_VAL_,24,0xe0ffffff)
+#define SET_CH12_LOWTHOLD(_VAL_) SET_REG(ADR_MB_THRESHOLD10,_VAL_,0,0xffffffe0)
+#define SET_CH13_LOWTHOLD(_VAL_) SET_REG(ADR_MB_THRESHOLD10,_VAL_,8,0xffffe0ff)
+#define SET_CH14_LOWTHOLD(_VAL_) SET_REG(ADR_MB_THRESHOLD10,_VAL_,16,0xffe0ffff)
+#define SET_CH15_LOWTHOLD(_VAL_) SET_REG(ADR_MB_THRESHOLD10,_VAL_,24,0xe0ffffff)
+#define SET_TRASH_TIMEOUT_EN(_VAL_) SET_REG(ADR_MB_TRASH_CFG,_VAL_,0,0xfffffffe)
+#define SET_TRASH_CAN_INT(_VAL_) SET_REG(ADR_MB_TRASH_CFG,_VAL_,1,0xfffffffd)
+#define SET_TRASH_INT_ID(_VAL_) SET_REG(ADR_MB_TRASH_CFG,_VAL_,4,0xfffff80f)
+#define SET_TRASH_TIMEOUT(_VAL_) SET_REG(ADR_MB_TRASH_CFG,_VAL_,16,0xfc00ffff)
+#define SET_IN_FIFO_FLUSH_ID(_VAL_) SET_REG(ADR_MB_IN_FF_FLUSH,_VAL_,0,0xfffff800)
+#define SET_IN_FIFO_FLUSH_MODE(_VAL_) SET_REG(ADR_MB_IN_FF_FLUSH,_VAL_,0,0xfffffffc)
+#define SET_IN_FIFO_FLUSH_SEL(_VAL_) SET_REG(ADR_MB_IN_FF_FLUSH,_VAL_,8,0xfffff0ff)
+#define SET_CPU_ID_TB2(_VAL_) SET_REG(ADR_CPU_ID_TB2,_VAL_,0,0x00000000)
+#define SET_CPU_ID_TB3(_VAL_) SET_REG(ADR_CPU_ID_TB3,_VAL_,0,0x00000000)
+#define SET_IQ_LOG_EN(_VAL_) SET_REG(ADR_PHY_IQ_LOG_CFG0,_VAL_,0,0xfffffffe)
+#define SET_IQ_LOG_STOP_MODE(_VAL_) SET_REG(ADR_PHY_IQ_LOG_CFG1,_VAL_,0,0xfffffffe)
+#define SET_IQ_LOG_TIMER(_VAL_) SET_REG(ADR_PHY_IQ_LOG_CFG1,_VAL_,16,0x0000ffff)
+#define SET_IQ_LOG_LEN(_VAL_) SET_REG(ADR_PHY_IQ_LOG_LEN,_VAL_,0,0xffff0000)
+#define SET_IQ_LOG_ST_ADR(_VAL_) SET_REG(ADR_PHY_IQ_LOG_LEN,_VAL_,16,0x0000ffff)
+#define SET_IQ_LOG_TAIL_ADR(_VAL_) SET_REG(ADR_PHY_IQ_LOG_PTR,_VAL_,0,0xffff0000)
+#define SET_ALC_LENG(_VAL_) SET_REG(ADR_WR_ALC,_VAL_,0,0xfffc0000)
+#define SET_CH0_DYN_PRI(_VAL_) SET_REG(ADR_WR_ALC,_VAL_,20,0xffcfffff)
+#define SET_MCU_PKTID(_VAL_) SET_REG(ADR_GETID,_VAL_,0,0x00000000)
+#define SET_CH0_STA_PRI(_VAL_) SET_REG(ADR_CH_STA_PRI,_VAL_,0,0xfffffffc)
+#define SET_CH1_STA_PRI(_VAL_) SET_REG(ADR_CH_STA_PRI,_VAL_,4,0xffffffcf)
+#define SET_CH2_STA_PRI(_VAL_) SET_REG(ADR_CH_STA_PRI,_VAL_,8,0xfffffcff)
+#define SET_CH3_STA_PRI(_VAL_) SET_REG(ADR_CH_STA_PRI,_VAL_,12,0xffffcfff)
+#define SET_ID_TB0(_VAL_) SET_REG(ADR_RD_ID0,_VAL_,0,0x00000000)
+#define SET_ID_TB1(_VAL_) SET_REG(ADR_RD_ID1,_VAL_,0,0x00000000)
+#define SET_ID_MNG_HALT(_VAL_) SET_REG(ADR_IMD_CFG,_VAL_,4,0xffffffef)
+#define SET_ID_MNG_ERR_HALT_EN(_VAL_) SET_REG(ADR_IMD_CFG,_VAL_,5,0xffffffdf)
+#define SET_ID_EXCEPT_FLG_CLR(_VAL_) SET_REG(ADR_IMD_CFG,_VAL_,6,0xffffffbf)
+#define SET_ID_EXCEPT_FLG(_VAL_) SET_REG(ADR_IMD_CFG,_VAL_,7,0xffffff7f)
+#define SET_ID_FULL(_VAL_) SET_REG(ADR_IMD_STA,_VAL_,0,0xfffffffe)
+#define SET_ID_MNG_BUSY(_VAL_) SET_REG(ADR_IMD_STA,_VAL_,1,0xfffffffd)
+#define SET_REQ_LOCK(_VAL_) SET_REG(ADR_IMD_STA,_VAL_,2,0xfffffffb)
+#define SET_CH0_REQ_LOCK(_VAL_) SET_REG(ADR_IMD_STA,_VAL_,4,0xffffffef)
+#define SET_CH1_REQ_LOCK(_VAL_) SET_REG(ADR_IMD_STA,_VAL_,5,0xffffffdf)
+#define SET_CH2_REQ_LOCK(_VAL_) SET_REG(ADR_IMD_STA,_VAL_,6,0xffffffbf)
+#define SET_CH3_REQ_LOCK(_VAL_) SET_REG(ADR_IMD_STA,_VAL_,7,0xffffff7f)
+#define SET_REQ_LOCK_INT_EN(_VAL_) SET_REG(ADR_IMD_STA,_VAL_,8,0xfffffeff)
+#define SET_REQ_LOCK_INT(_VAL_) SET_REG(ADR_IMD_STA,_VAL_,9,0xfffffdff)
+#define SET_MCU_ALC_READY(_VAL_) SET_REG(ADR_ALC_STA,_VAL_,0,0xfffffffe)
+#define SET_ALC_FAIL(_VAL_) SET_REG(ADR_ALC_STA,_VAL_,1,0xfffffffd)
+#define SET_ALC_BUSY(_VAL_) SET_REG(ADR_ALC_STA,_VAL_,2,0xfffffffb)
+#define SET_CH0_NVLD(_VAL_) SET_REG(ADR_ALC_STA,_VAL_,4,0xffffffef)
+#define SET_CH1_NVLD(_VAL_) SET_REG(ADR_ALC_STA,_VAL_,5,0xffffffdf)
+#define SET_CH2_NVLD(_VAL_) SET_REG(ADR_ALC_STA,_VAL_,6,0xffffffbf)
+#define SET_CH3_NVLD(_VAL_) SET_REG(ADR_ALC_STA,_VAL_,7,0xffffff7f)
+#define SET_ALC_INT_ID(_VAL_) SET_REG(ADR_ALC_STA,_VAL_,8,0xffff80ff)
+#define SET_ALC_TIMEOUT(_VAL_) SET_REG(ADR_ALC_STA,_VAL_,16,0xfc00ffff)
+#define SET_ALC_TIMEOUT_INT_EN(_VAL_) SET_REG(ADR_ALC_STA,_VAL_,30,0xbfffffff)
+#define SET_ALC_TIMEOUT_INT(_VAL_) SET_REG(ADR_ALC_STA,_VAL_,31,0x7fffffff)
+#define SET_TX_ID_COUNT(_VAL_) SET_REG(ADR_TRX_ID_COUNT,_VAL_,0,0xffffff00)
+#define SET_RX_ID_COUNT(_VAL_) SET_REG(ADR_TRX_ID_COUNT,_VAL_,8,0xffff00ff)
+#define SET_TX_ID_THOLD(_VAL_) SET_REG(ADR_TRX_ID_THRESHOLD,_VAL_,0,0xffffff00)
+#define SET_RX_ID_THOLD(_VAL_) SET_REG(ADR_TRX_ID_THRESHOLD,_VAL_,8,0xffff00ff)
+#define SET_ID_THOLD_RX_INT(_VAL_) SET_REG(ADR_TRX_ID_THRESHOLD,_VAL_,16,0xfffeffff)
+#define SET_RX_INT_CH(_VAL_) SET_REG(ADR_TRX_ID_THRESHOLD,_VAL_,17,0xfff1ffff)
+#define SET_ID_THOLD_TX_INT(_VAL_) SET_REG(ADR_TRX_ID_THRESHOLD,_VAL_,20,0xffefffff)
+#define SET_TX_INT_CH(_VAL_) SET_REG(ADR_TRX_ID_THRESHOLD,_VAL_,21,0xff1fffff)
+#define SET_ID_THOLD_INT_EN(_VAL_) SET_REG(ADR_TRX_ID_THRESHOLD,_VAL_,24,0xfeffffff)
+#define SET_TX_ID_TB0(_VAL_) SET_REG(ADR_TX_ID0,_VAL_,0,0x00000000)
+#define SET_TX_ID_TB1(_VAL_) SET_REG(ADR_TX_ID1,_VAL_,0,0x00000000)
+#define SET_RX_ID_TB0(_VAL_) SET_REG(ADR_RX_ID0,_VAL_,0,0x00000000)
+#define SET_RX_ID_TB1(_VAL_) SET_REG(ADR_RX_ID1,_VAL_,0,0x00000000)
+#define SET_DOUBLE_RLS_INT_EN(_VAL_) SET_REG(ADR_RTN_STA,_VAL_,0,0xfffffffe)
+#define SET_ID_DOUBLE_RLS_INT(_VAL_) SET_REG(ADR_RTN_STA,_VAL_,1,0xfffffffd)
+#define SET_DOUBLE_RLS_ID(_VAL_) SET_REG(ADR_RTN_STA,_VAL_,8,0xffff80ff)
+#define SET_ID_LEN_THOLD_INT_EN(_VAL_) SET_REG(ADR_ID_LEN_THREADSHOLD1,_VAL_,0,0xfffffffe)
+#define SET_ALL_ID_LEN_THOLD_INT(_VAL_) SET_REG(ADR_ID_LEN_THREADSHOLD1,_VAL_,1,0xfffffffd)
+#define SET_TX_ID_LEN_THOLD_INT(_VAL_) SET_REG(ADR_ID_LEN_THREADSHOLD1,_VAL_,2,0xfffffffb)
+#define SET_RX_ID_LEN_THOLD_INT(_VAL_) SET_REG(ADR_ID_LEN_THREADSHOLD1,_VAL_,3,0xfffffff7)
+#define SET_ID_TX_LEN_THOLD(_VAL_) SET_REG(ADR_ID_LEN_THREADSHOLD1,_VAL_,4,0xffffe00f)
+#define SET_ID_RX_LEN_THOLD(_VAL_) SET_REG(ADR_ID_LEN_THREADSHOLD1,_VAL_,13,0xffc01fff)
+#define SET_ID_LEN_THOLD(_VAL_) SET_REG(ADR_ID_LEN_THREADSHOLD1,_VAL_,22,0x803fffff)
+#define SET_ALL_ID_ALC_LEN(_VAL_) SET_REG(ADR_ID_LEN_THREADSHOLD2,_VAL_,0,0xfffffe00)
+#define SET_TX_ID_ALC_LEN(_VAL_) SET_REG(ADR_ID_LEN_THREADSHOLD2,_VAL_,9,0xfffc01ff)
+#define SET_RX_ID_ALC_LEN(_VAL_) SET_REG(ADR_ID_LEN_THREADSHOLD2,_VAL_,18,0xf803ffff)
+#define SET_CH_ARB_EN(_VAL_) SET_REG(ADR_CH_ARB_PRI,_VAL_,0,0xfffffffe)
+#define SET_CH_PRI1(_VAL_) SET_REG(ADR_CH_ARB_PRI,_VAL_,4,0xffffffcf)
+#define SET_CH_PRI2(_VAL_) SET_REG(ADR_CH_ARB_PRI,_VAL_,8,0xfffffcff)
+#define SET_CH_PRI3(_VAL_) SET_REG(ADR_CH_ARB_PRI,_VAL_,12,0xffffcfff)
+#define SET_CH_PRI4(_VAL_) SET_REG(ADR_CH_ARB_PRI,_VAL_,16,0xfffcffff)
+#define SET_TX_ID_REMAIN(_VAL_) SET_REG(ADR_TX_ID_REMAIN_STATUS,_VAL_,0,0xffffff80)
+#define SET_TX_PAGE_REMAIN(_VAL_) SET_REG(ADR_TX_ID_REMAIN_STATUS,_VAL_,8,0xfffe00ff)
+#define SET_ID_PAGE_MAX_SIZE(_VAL_) SET_REG(ADR_ID_INFO_STA,_VAL_,0,0xfffffe00)
+#define SET_TX_PAGE_LIMIT(_VAL_) SET_REG(ADR_TX_LIMIT_INTR,_VAL_,0,0xfffffe00)
+#define SET_TX_COUNT_LIMIT(_VAL_) SET_REG(ADR_TX_LIMIT_INTR,_VAL_,16,0xff00ffff)
+#define SET_TX_LIMIT_INT(_VAL_) SET_REG(ADR_TX_LIMIT_INTR,_VAL_,30,0xbfffffff)
+#define SET_TX_LIMIT_INT_EN(_VAL_) SET_REG(ADR_TX_LIMIT_INTR,_VAL_,31,0x7fffffff)
+#define SET_TX_PAGE_USE_7_0(_VAL_) SET_REG(ADR_TX_ID_ALL_INFO,_VAL_,0,0xffffff00)
+#define SET_TX_ID_USE_5_0(_VAL_) SET_REG(ADR_TX_ID_ALL_INFO,_VAL_,8,0xffffc0ff)
+#define SET_EDCA0_FFO_CNT(_VAL_) SET_REG(ADR_TX_ID_ALL_INFO,_VAL_,14,0xfffc3fff)
+#define SET_EDCA1_FFO_CNT_3_0(_VAL_) SET_REG(ADR_TX_ID_ALL_INFO,_VAL_,18,0xffc3ffff)
+#define SET_EDCA2_FFO_CNT(_VAL_) SET_REG(ADR_TX_ID_ALL_INFO,_VAL_,22,0xf83fffff)
+#define SET_EDCA3_FFO_CNT(_VAL_) SET_REG(ADR_TX_ID_ALL_INFO,_VAL_,27,0x07ffffff)
+#define SET_ID_TB2(_VAL_) SET_REG(ADR_RD_ID2,_VAL_,0,0x00000000)
+#define SET_ID_TB3(_VAL_) SET_REG(ADR_RD_ID3,_VAL_,0,0x00000000)
+#define SET_TX_ID_TB2(_VAL_) SET_REG(ADR_TX_ID2,_VAL_,0,0x00000000)
+#define SET_TX_ID_TB3(_VAL_) SET_REG(ADR_TX_ID3,_VAL_,0,0x00000000)
+#define SET_RX_ID_TB2(_VAL_) SET_REG(ADR_RX_ID2,_VAL_,0,0x00000000)
+#define SET_RX_ID_TB3(_VAL_) SET_REG(ADR_RX_ID3,_VAL_,0,0x00000000)
+#define SET_TX_PAGE_USE2(_VAL_) SET_REG(ADR_TX_ID_ALL_INFO2,_VAL_,0,0xfffffe00)
+#define SET_TX_ID_USE2(_VAL_) SET_REG(ADR_TX_ID_ALL_INFO2,_VAL_,9,0xfffe01ff)
+#define SET_EDCA4_FFO_CNT(_VAL_) SET_REG(ADR_TX_ID_ALL_INFO2,_VAL_,17,0xffe1ffff)
+#define SET_EDCA5_FFO_CNT(_VAL_) SET_REG(ADR_TX_ID_ALL_INFO2,_VAL_,21,0xfc1fffff)
+#define SET_TX_PAGE_USE3(_VAL_) SET_REG(ADR_TX_ID_ALL_INFO_A,_VAL_,0,0xfffffe00)
+#define SET_TX_ID_USE3(_VAL_) SET_REG(ADR_TX_ID_ALL_INFO_A,_VAL_,9,0xfffe01ff)
+#define SET_EDCA1_FFO_CNT2(_VAL_) SET_REG(ADR_TX_ID_ALL_INFO_A,_VAL_,17,0xffc1ffff)
+#define SET_EDCA4_FFO_CNT2(_VAL_) SET_REG(ADR_TX_ID_ALL_INFO_A,_VAL_,23,0xf87fffff)
+#define SET_EDCA5_FFO_CNT2(_VAL_) SET_REG(ADR_TX_ID_ALL_INFO_A,_VAL_,27,0x07ffffff)
+#define SET_TX_PAGE_USE4(_VAL_) SET_REG(ADR_TX_ID_ALL_INFO_B,_VAL_,0,0xfffffe00)
+#define SET_TX_ID_USE4(_VAL_) SET_REG(ADR_TX_ID_ALL_INFO_B,_VAL_,9,0xfffe01ff)
+#define SET_EDCA2_FFO_CNT2(_VAL_) SET_REG(ADR_TX_ID_ALL_INFO_B,_VAL_,17,0xffc1ffff)
+#define SET_EDCA3_FFO_CNT2(_VAL_) SET_REG(ADR_TX_ID_ALL_INFO_B,_VAL_,22,0xf83fffff)
+#define SET_TX_ID_IFO_LEN(_VAL_) SET_REG(ADR_TX_ID_REMAIN_STATUS2,_VAL_,0,0xfffffe00)
+#define SET_RX_ID_IFO_LEN(_VAL_) SET_REG(ADR_TX_ID_REMAIN_STATUS2,_VAL_,16,0xfe00ffff)
+#define SET_MAX_ALL_ALC_ID_CNT(_VAL_) SET_REG(ADR_ALC_ID_INFO,_VAL_,0,0xffffff00)
+#define SET_MAX_TX_ALC_ID_CNT(_VAL_) SET_REG(ADR_ALC_ID_INFO,_VAL_,8,0xffff00ff)
+#define SET_MAX_RX_ALC_ID_CNT(_VAL_) SET_REG(ADR_ALC_ID_INFO,_VAL_,16,0xff00ffff)
+#define SET_MAX_ALL_ID_ALC_LEN(_VAL_) SET_REG(ADR_ALC_ID_INF1,_VAL_,0,0xfffffe00)
+#define SET_MAX_TX_ID_ALC_LEN(_VAL_) SET_REG(ADR_ALC_ID_INF1,_VAL_,9,0xfffc01ff)
+#define SET_MAX_RX_ID_ALC_LEN(_VAL_) SET_REG(ADR_ALC_ID_INF1,_VAL_,18,0xf803ffff)
+#define SET_ALC_ABT_ID(_VAL_) SET_REG(ADR_ALC_ABORT,_VAL_,0,0xffffff80)
+#define SET_ALC_ABT_STS(_VAL_) SET_REG(ADR_ALC_ABORT,_VAL_,8,0xfffffeff)
+#define SET_ALC_ABT_CLR(_VAL_) SET_REG(ADR_ALC_ABORT,_VAL_,9,0xfffffdff)
+#define SET_ALC_ERR_STS(_VAL_) SET_REG(ADR_ALC_RLS_STATUS,_VAL_,0,0xfffffffe)
+#define SET_RLS_ERR_STS(_VAL_) SET_REG(ADR_ALC_RLS_STATUS,_VAL_,1,0xfffffffd)
+#define SET_ALC_ERR_CLR(_VAL_) SET_REG(ADR_ALC_RLS_STATUS,_VAL_,2,0xfffffffb)
+#define SET_RLS_ERR_CLR(_VAL_) SET_REG(ADR_ALC_RLS_STATUS,_VAL_,3,0xfffffff7)
+#define SET_AL_STATE(_VAL_) SET_REG(ADR_ALC_RLS_STATUS,_VAL_,8,0xfffff8ff)
+#define SET_RL_STATE(_VAL_) SET_REG(ADR_ALC_RLS_STATUS,_VAL_,12,0xffff8fff)
+#define SET_ALC_ERR_ID(_VAL_) SET_REG(ADR_ALC_RLS_STATUS,_VAL_,16,0xff80ffff)
+#define SET_RLS_ERR_ID(_VAL_) SET_REG(ADR_ALC_RLS_STATUS,_VAL_,24,0x80ffffff)
+#define SET_DMN_NOHIT_STS(_VAL_) SET_REG(ADR_DMN_STATUS,_VAL_,0,0xfffffffe)
+#define SET_DMN_NOHIT_CLR(_VAL_) SET_REG(ADR_DMN_STATUS,_VAL_,1,0xfffffffd)
+#define SET_DMN_WR(_VAL_) SET_REG(ADR_DMN_STATUS,_VAL_,2,0xfffffffb)
+#define SET_DMN_PORT(_VAL_) SET_REG(ADR_DMN_STATUS,_VAL_,4,0xffffff0f)
+#define SET_DMN_NHIT_ID(_VAL_) SET_REG(ADR_DMN_STATUS,_VAL_,8,0xffff80ff)
+#define SET_DMN_NHIT_ADDR(_VAL_) SET_REG(ADR_DMN_STATUS,_VAL_,16,0xff00ffff)
+#define SET_AVA_TAG(_VAL_) SET_REG(ADR_TAG_STATUS,_VAL_,0,0xfffffe00)
+#define SET_PKTBUF_FULL(_VAL_) SET_REG(ADR_TAG_STATUS,_VAL_,16,0xfffeffff)
+#define SET_PKT_REQ_STATUS(_VAL_) SET_REG(ADR_REQ_STATUS,_VAL_,0,0xffff0000)
+#define SET_PG_TAG_31_0(_VAL_) SET_REG(ADR_PAGE_TAG_STATUS_0,_VAL_,0,0x00000000)
+#define SET_PG_TAG_63_32(_VAL_) SET_REG(ADR_PAGE_TAG_STATUS_1,_VAL_,0,0x00000000)
+#define SET_PG_TAG_95_64(_VAL_) SET_REG(ADR_PAGE_TAG_STATUS_2,_VAL_,0,0x00000000)
+#define SET_PG_TAG_127_96(_VAL_) SET_REG(ADR_PAGE_TAG_STATUS_3,_VAL_,0,0x00000000)
+#define SET_PG_TAG_159_128(_VAL_) SET_REG(ADR_PAGE_TAG_STATUS_4,_VAL_,0,0x00000000)
+#define SET_PG_TAG_191_160(_VAL_) SET_REG(ADR_PAGE_TAG_STATUS_5,_VAL_,0,0x00000000)
+#define SET_PG_TAG_223_192(_VAL_) SET_REG(ADR_PAGE_TAG_STATUS_6,_VAL_,0,0x00000000)
+#define SET_PG_TAG_255_224(_VAL_) SET_REG(ADR_PAGE_TAG_STATUS_7,_VAL_,0,0x00000000)
+#define SET_FPGA_TO_GEMINIA_DAC_SIGN_SWAP(_VAL_) SET_REG(ADR_FPGA_GEMINIARF_SWITCH,_VAL_,1,0xfffffffd)
+#define SET_FPGA_TO_GEMINIA_DAC_EDGE_SEL(_VAL_) SET_REG(ADR_FPGA_GEMINIARF_SWITCH,_VAL_,2,0xfffffffb)
+#define SET_FPGA_TO_GEMINIA_ADC_EDGE_SEL(_VAL_) SET_REG(ADR_FPGA_GEMINIARF_SWITCH,_VAL_,3,0xfffffff7)
+#define DEF_FBUS_SAR0() (REG32(ADR_FBUS_SAR0)) = (0x00000000)
+#define DEF_FBUS_DAR0() (REG32(ADR_FBUS_DAR0)) = (0x00000000)
+#define DEF_FBUS_CTL0_1() (REG32(ADR_FBUS_CTL0_1)) = (0x00000000)
+#define DEF_FBUS_CTL0_2() (REG32(ADR_FBUS_CTL0_2)) = (0x00000000)
+#define DEF_FBUS_CFG0_1() (REG32(ADR_FBUS_CFG0_1)) = (0x00000c00)
+#define DEF_FBUS_CFG0_2() (REG32(ADR_FBUS_CFG0_2)) = (0x00000000)
+#define DEF_FBUS_SAR1() (REG32(ADR_FBUS_SAR1)) = (0x00000000)
+#define DEF_FBUS_DAR1() (REG32(ADR_FBUS_DAR1)) = (0x00000000)
+#define DEF_FBUS_CTL1_1() (REG32(ADR_FBUS_CTL1_1)) = (0x00000000)
+#define DEF_FBUS_CTL1_2() (REG32(ADR_FBUS_CTL1_2)) = (0x00000000)
+#define DEF_FBUS_CFG1_1() (REG32(ADR_FBUS_CFG1_1)) = (0x00000c00)
+#define DEF_FBUS_CFG1_2() (REG32(ADR_FBUS_CFG1_2)) = (0x00000000)
+#define DEF_FBUS_RAWTR() (REG32(ADR_FBUS_RAWTR)) = (0x00000000)
+#define DEF_FBUS_RAWERR() (REG32(ADR_FBUS_RAWERR)) = (0x00000000)
+#define DEF_FBUS_STATUSTR() (REG32(ADR_FBUS_STATUSTR)) = (0x00000000)
+#define DEF_FBUS_STATUSERR() (REG32(ADR_FBUS_STATUSERR)) = (0x00000000)
+#define DEF_FBUS_MASKTR() (REG32(ADR_FBUS_MASKTR)) = (0x00000000)
+#define DEF_FBUS_MASKERR() (REG32(ADR_FBUS_MASKERR)) = (0x00000000)
+#define DEF_FBUS_CLRTR() (REG32(ADR_FBUS_CLRTR)) = (0x00000000)
+#define DEF_FBUS_CLRERR() (REG32(ADR_FBUS_CLRERR)) = (0x00000000)
+#define DEF_FBUS_SHS_SRC_REQ_CFG() (REG32(ADR_FBUS_SHS_SRC_REQ_CFG)) = (0x00000000)
+#define DEF_FBUS_SHS_DST_REQ_CFG() (REG32(ADR_FBUS_SHS_DST_REQ_CFG)) = (0x00000000)
+#define DEF_FBUS_SHS_SRC_SREQ_CFG() (REG32(ADR_FBUS_SHS_SRC_SREQ_CFG)) = (0x00000000)
+#define DEF_FBUS_SHS_DST_SREQ_CFG() (REG32(ADR_FBUS_SHS_DST_SREQ_CFG)) = (0x00000000)
+#define DEF_FBUS_DMA_EN() (REG32(ADR_FBUS_DMA_EN)) = (0x00000000)
+#define DEF_FBUS_CH_EN() (REG32(ADR_FBUS_CH_EN)) = (0x00000000)
+#define DEF_SBUS_SAR0() (REG32(ADR_SBUS_SAR0)) = (0x00000000)
+#define DEF_SBUS_DAR0() (REG32(ADR_SBUS_DAR0)) = (0x00000000)
+#define DEF_SBUS_CTL0_1() (REG32(ADR_SBUS_CTL0_1)) = (0x00000000)
+#define DEF_SBUS_CTL0_2() (REG32(ADR_SBUS_CTL0_2)) = (0x00000000)
+#define DEF_SBUS_CFG0_1() (REG32(ADR_SBUS_CFG0_1)) = (0x00000c00)
+#define DEF_SBUS_CFG0_2() (REG32(ADR_SBUS_CFG0_2)) = (0x00000000)
+#define DEF_SBUS_SAR1() (REG32(ADR_SBUS_SAR1)) = (0x00000000)
+#define DEF_SBUS_DAR1() (REG32(ADR_SBUS_DAR1)) = (0x00000000)
+#define DEF_SBUS_CTL1_1() (REG32(ADR_SBUS_CTL1_1)) = (0x00000000)
+#define DEF_SBUS_CTL1_2() (REG32(ADR_SBUS_CTL1_2)) = (0x00000000)
+#define DEF_SBUS_CFG1_1() (REG32(ADR_SBUS_CFG1_1)) = (0x00000c00)
+#define DEF_SBUS_CFG1_2() (REG32(ADR_SBUS_CFG1_2)) = (0x00000000)
+#define DEF_SBUS_RAWTR() (REG32(ADR_SBUS_RAWTR)) = (0x00000000)
+#define DEF_SBUS_RAWERR() (REG32(ADR_SBUS_RAWERR)) = (0x00000000)
+#define DEF_SBUS_STATUSTR() (REG32(ADR_SBUS_STATUSTR)) = (0x00000000)
+#define DEF_SBUS_STATUSERR() (REG32(ADR_SBUS_STATUSERR)) = (0x00000000)
+#define DEF_SBUS_MASKTR() (REG32(ADR_SBUS_MASKTR)) = (0x00000000)
+#define DEF_SBUS_MASKERR() (REG32(ADR_SBUS_MASKERR)) = (0x00000000)
+#define DEF_SBUS_CLRTR() (REG32(ADR_SBUS_CLRTR)) = (0x00000000)
+#define DEF_SBUS_CLRERR() (REG32(ADR_SBUS_CLRERR)) = (0x00000000)
+#define DEF_SBUS_SHS_SRC_REQ_CFG() (REG32(ADR_SBUS_SHS_SRC_REQ_CFG)) = (0x00000000)
+#define DEF_SBUS_SHS_DST_REQ_CFG() (REG32(ADR_SBUS_SHS_DST_REQ_CFG)) = (0x00000000)
+#define DEF_SBUS_SHS_SRC_SREQ_CFG() (REG32(ADR_SBUS_SHS_SRC_SREQ_CFG)) = (0x00000000)
+#define DEF_SBUS_SHS_DST_SREQ_CFG() (REG32(ADR_SBUS_SHS_DST_SREQ_CFG)) = (0x00000000)
+#define DEF_SBUS_DMA_EN() (REG32(ADR_SBUS_DMA_EN)) = (0x00000000)
+#define DEF_SBUS_CH_EN() (REG32(ADR_SBUS_CH_EN)) = (0x00000000)
+#define DEF_I2S_EN() (REG32(ADR_I2S_EN)) = (0x00000000)
+#define DEF_I2S_RX_EN() (REG32(ADR_I2S_RX_EN)) = (0x00000000)
+#define DEF_I2S_TX_EN() (REG32(ADR_I2S_TX_EN)) = (0x00000000)
+#define DEF_I2S_SCLK_SCR_EN() (REG32(ADR_I2S_SCLK_SCR_EN)) = (0x00000000)
+#define DEF_I2S_WS_DEF() (REG32(ADR_I2S_WS_DEF)) = (0x00000010)
+#define DEF_RESET_RX_FIFO() (REG32(ADR_RESET_RX_FIFO)) = (0x00000000)
+#define DEF_RESET_TX_FIFO() (REG32(ADR_RESET_TX_FIFO)) = (0x00000000)
+#define DEF_L_TRX_DATA() (REG32(ADR_L_TRX_DATA)) = (0x00000000)
+#define DEF_R_TRX_DATA() (REG32(ADR_R_TRX_DATA)) = (0x00000000)
+#define DEF_I2S_RX_CH_EN() (REG32(ADR_I2S_RX_CH_EN)) = (0x00000000)
+#define DEF_I2S_TX_CH_EN() (REG32(ADR_I2S_TX_CH_EN)) = (0x00000000)
+#define DEF_I2S_RX_WORD_RES() (REG32(ADR_I2S_RX_WORD_RES)) = (0x00000005)
+#define DEF_I2S_TX_WORD_RES() (REG32(ADR_I2S_TX_WORD_RES)) = (0x00000005)
+#define DEF_I2S_INTR() (REG32(ADR_I2S_INTR)) = (0x00000000)
+#define DEF_I2S_INTR_MASK() (REG32(ADR_I2S_INTR_MASK)) = (0x00000033)
+#define DEF_I2S_RXFO() (REG32(ADR_I2S_RXFO)) = (0x00000000)
+#define DEF_I2S_TXFO() (REG32(ADR_I2S_TXFO)) = (0x00000000)
+#define DEF_I2S_RX_FIFO_TH() (REG32(ADR_I2S_RX_FIFO_TH)) = (0x00000005)
+#define DEF_I2S_TX_FIFO_TH() (REG32(ADR_I2S_TX_FIFO_TH)) = (0x00000005)
+#define DEF_I2S_RX_FIFO_FLUSH() (REG32(ADR_I2S_RX_FIFO_FLUSH)) = (0x00000000)
+#define DEF_I2S_TX_FIFO_FLUSH() (REG32(ADR_I2S_TX_FIFO_FLUSH)) = (0x00000000)
+#define DEF_I2S_RX_DMA() (REG32(ADR_I2S_RX_DMA)) = (0x00000000)
+#define DEF_I2S_TX_DMA() (REG32(ADR_I2S_TX_DMA)) = (0x00000000)
+#define DEF_I2CMST_CFG0() (REG32(ADR_I2CMST_CFG0)) = (0x00000000)
+#define DEF_I2CMST_TAR() (REG32(ADR_I2CMST_TAR)) = (0x00000000)
+#define DEF_I2CMST_TRX_CMD_DATA() (REG32(ADR_I2CMST_TRX_CMD_DATA)) = (0x00000000)
+#define DEF_I2CMST_SCLK_H_WIDTH() (REG32(ADR_I2CMST_SCLK_H_WIDTH)) = (0x00000000)
+#define DEF_I2CMST_SCLK_L_WIDTH() (REG32(ADR_I2CMST_SCLK_L_WIDTH)) = (0x00000000)
+#define DEF_I2CMST_INT() (REG32(ADR_I2CMST_INT)) = (0x00000000)
+#define DEF_I2CMST_INT_MASK() (REG32(ADR_I2CMST_INT_MASK)) = (0x00000000)
+#define DEF_I2CMST_INT_STA() (REG32(ADR_I2CMST_INT_STA)) = (0x00000000)
+#define DEF_I2CMST_RX_FIFO_TH() (REG32(ADR_I2CMST_RX_FIFO_TH)) = (0x00000000)
+#define DEF_I2CMST_TX_FIFO_TH() (REG32(ADR_I2CMST_TX_FIFO_TH)) = (0x00000000)
+#define DEF_I2CMST_ENABLE() (REG32(ADR_I2CMST_ENABLE)) = (0x00000000)
+#define DEF_SPIMST_CFG0() (REG32(ADR_SPIMST_CFG0)) = (0x00000007)
+#define DEF_SPIMST_CFG1() (REG32(ADR_SPIMST_CFG1)) = (0x00000000)
+#define DEF_SPIMST_EN() (REG32(ADR_SPIMST_EN)) = (0x00000000)
+#define DEF_SPIMST_CEN() (REG32(ADR_SPIMST_CEN)) = (0x00000000)
+#define DEF_SPIMST_SCLK_RATE() (REG32(ADR_SPIMST_SCLK_RATE)) = (0x00000000)
+#define DEF_SPIMST_TXFIFO_TH() (REG32(ADR_SPIMST_TXFIFO_TH)) = (0x00000000)
+#define DEF_SPIMST_RXFIFO_TH() (REG32(ADR_SPIMST_RXFIFO_TH)) = (0x00000000)
+#define DEF_SPIMST_STATUS() (REG32(ADR_SPIMST_STATUS)) = (0x00000000)
+#define DEF_SPIMST_INT_MASK() (REG32(ADR_SPIMST_INT_MASK)) = (0x00000000)
+#define DEF_SPIMST_INT() (REG32(ADR_SPIMST_INT)) = (0x00000000)
+#define DEF_SPIMST_TRX_DATA() (REG32(ADR_SPIMST_TRX_DATA)) = (0x00000000)
+#define DEF_SPIMST_RX_SAMPLE_DLY() (REG32(ADR_SPIMST_RX_SAMPLE_DLY)) = (0x00000000)
+#define DEF_BRG_SW_RST() (REG32(ADR_BRG_SW_RST)) = (0x00000000)
+#define DEF_BOOT() (REG32(ADR_BOOT)) = (0x00040000)
+#define DEF_CHIP_ID_0() (REG32(ADR_CHIP_ID_0)) = (0x20202020)
+#define DEF_CHIP_ID_1() (REG32(ADR_CHIP_ID_1)) = (0x30202020)
+#define DEF_CHIP_ID_2() (REG32(ADR_CHIP_ID_2)) = (0x30303642)
+#define DEF_CHIP_ID_3() (REG32(ADR_CHIP_ID_3)) = (0x53535636)
+#define DEF_CLOCK_SELECTION() (REG32(ADR_CLOCK_SELECTION)) = (0x00000001)
+#define DEF_PLATFORM_CLOCK_ENABLE() (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (0x7effffff)
+#define DEF_SYS_CSR_CLOCK_ENABLE() (REG32(ADR_SYS_CSR_CLOCK_ENABLE)) = (0x00000407)
+#define DEF_BOOTSTRAP_SAMPLE() (REG32(ADR_BOOTSTRAP_SAMPLE)) = (0x00000000)
+#define DEF_N10_DBG1() (REG32(ADR_N10_DBG1)) = (0x00000000)
+#define DEF_N10_DBG2() (REG32(ADR_N10_DBG2)) = (0x00000000)
+#define DEF_ROPMUSTATE() (REG32(ADR_ROPMUSTATE)) = (0x00000000)
+#define DEF_ROM_READ_PROT() (REG32(ADR_ROM_READ_PROT)) = (0x00000001)
+#define DEF_GPIO_IQ_LOG_STOP() (REG32(ADR_GPIO_IQ_LOG_STOP)) = (0x00000000)
+#define DEF_TB_ADR_SEL() (REG32(ADR_TB_ADR_SEL)) = (0x00000000)
+#define DEF_TB_RDATA() (REG32(ADR_TB_RDATA)) = (0x00000000)
+#define DEF_UART_W2B() (REG32(ADR_UART_W2B)) = (0x00000000)
+#define DEF_SYSCTRL_COMMAND() (REG32(ADR_SYSCTRL_COMMAND)) = (0x00000000)
+#define DEF_FBUS_CLK_SEL() (REG32(ADR_FBUS_CLK_SEL)) = (0x00000001)
+#define DEF_SYSCTRL_STATUS() (REG32(ADR_SYSCTRL_STATUS)) = (0x00000000)
+#define DEF_I2SMAS_CFG() (REG32(ADR_I2SMAS_CFG)) = (0x80000000)
+#define DEF_HBUSREQ_LOCK() (REG32(ADR_HBUSREQ_LOCK)) = (0x00001ffd)
+#define DEF_HBURST_LOCK() (REG32(ADR_HBURST_LOCK)) = (0x00000000)
+#define DEF_FENCE_CTRL() (REG32(ADR_FENCE_CTRL)) = (0x00000000)
+#define DEF_FENCE_STATUS() (REG32(ADR_FENCE_STATUS)) = (0x00000000)
+#define DEF_POWER_SW_INFO() (REG32(ADR_POWER_SW_INFO)) = (0x00000000)
+#define DEF_VIAROM_EMA() (REG32(ADR_VIAROM_EMA)) = (0x00000002)
+#define DEF_TEST_MODE() (REG32(ADR_TEST_MODE)) = (0x00000000)
+#define DEF_MANUAL_RESET_N() (REG32(ADR_MANUAL_RESET_N)) = (0x00000002)
+#define DEF_DEBUG_FIRMWARE_EVENT_FLAG() (REG32(ADR_DEBUG_FIRMWARE_EVENT_FLAG)) = (0x00000000)
+#define DEF_DEBUG_HOST_EVENT_FLAG() (REG32(ADR_DEBUG_HOST_EVENT_FLAG)) = (0x00000000)
+#define DEF_CHIP_INFO_ID_0() (REG32(ADR_CHIP_INFO_ID_0)) = (0x534d4f5f)
+#define DEF_CHIP_INFO_ID_1() (REG32(ADR_CHIP_INFO_ID_1)) = (0x54555249)
+#define DEF_CHIP_TYPE_VER() (REG32(ADR_CHIP_TYPE_VER)) = (0x00303030)
+#define DEF_CHIP_DATE_YYYYMMDD() (REG32(ADR_CHIP_DATE_YYYYMMDD)) = (0x00000000)
+#define DEF_CHIP_DATE_00HHMMSS() (REG32(ADR_CHIP_DATE_00HHMMSS)) = (0x00000000)
+#define DEF_CHIP_GITSHA_0() (REG32(ADR_CHIP_GITSHA_0)) = (0x00000000)
+#define DEF_CHIP_GITSHA_1() (REG32(ADR_CHIP_GITSHA_1)) = (0x00000000)
+#define DEF_CHIP_GITSHA_2() (REG32(ADR_CHIP_GITSHA_2)) = (0x00000000)
+#define DEF_CHIP_GITSHA_3() (REG32(ADR_CHIP_GITSHA_3)) = (0x00000000)
+#define DEF_CHIP_GITSHA_4() (REG32(ADR_CHIP_GITSHA_4)) = (0x00000000)
+#define DEF_N10CFG_DEF_IVB() (REG32(ADR_N10CFG_DEF_IVB)) = (0x00000000)
+#define DEF_N10CFG_SETTING() (REG32(ADR_N10CFG_SETTING)) = (0x00000000)
+#define DEF_USB20_HOST_SEL() (REG32(ADR_USB20_HOST_SEL)) = (0x00000000)
+#define DEF_CHIP_INFO_FPGATAG() (REG32(ADR_CHIP_INFO_FPGATAG)) = (0x00000000)
+#define DEF_PMU_MODE_TRAN_INT() (REG32(ADR_PMU_MODE_TRAN_INT)) = (0x00000000)
+#define DEF_DEBUG_SIM_FINISH() (REG32(ADR_DEBUG_SIM_FINISH)) = (0x00000000)
+#define DEF_ALWAYS_ON_CFG00() (REG32(ADR_ALWAYS_ON_CFG00)) = (0x00000000)
+#define DEF_SDIO_RESET_WAKE_CFG() (REG32(ADR_SDIO_RESET_WAKE_CFG)) = (0x00000002)
+#define DEF_BOOT_INFO() (REG32(ADR_BOOT_INFO)) = (0x00000000)
+#define DEF_SPARE_UART_INFO() (REG32(ADR_SPARE_UART_INFO)) = (0x00000000)
+#define DEF_POWER_ON_OFF_CTRL() (REG32(ADR_POWER_ON_OFF_CTRL)) = (0x00007007)
+#define DEF_HOST_WAKE_WIFI_CTRL() (REG32(ADR_HOST_WAKE_WIFI_CTRL)) = (0x00000000)
+#define DEF_PRESCALER_USTIMER() (REG32(ADR_PRESCALER_USTIMER)) = (0x00000028)
+#define DEF_DESIGN_FOR_TEST_ASSERTION() (REG32(ADR_DESIGN_FOR_TEST_ASSERTION)) = (0x00000000)
+#define DEF_WAKE_PMU_ENABLE() (REG32(ADR_WAKE_PMU_ENABLE)) = (0x00000000)
+#define DEF_SRAMCFG_SETTING() (REG32(ADR_SRAMCFG_SETTING)) = (0x00000000)
+#define DEF_ROM_PATCH00_0() (REG32(ADR_ROM_PATCH00_0)) = (0x00000000)
+#define DEF_ROM_PATCH00_1() (REG32(ADR_ROM_PATCH00_1)) = (0x00000000)
+#define DEF_ROM_PATCH01_0() (REG32(ADR_ROM_PATCH01_0)) = (0x00000000)
+#define DEF_ROM_PATCH01_1() (REG32(ADR_ROM_PATCH01_1)) = (0x00000000)
+#define DEF_DESIGN_FOR_TEST() (REG32(ADR_DESIGN_FOR_TEST)) = (0x00000000)
+#define DEF_TU0_MICROSECOND_TIMER() (REG32(ADR_TU0_MICROSECOND_TIMER)) = (0x00000000)
+#define DEF_TU0_CURRENT_MICROSECOND_TIME_VALUE() (REG32(ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TU0_MICROSECOND_TIMER_LOCAL_PRESCALE() (REG32(ADR_TU0_MICROSECOND_TIMER_LOCAL_PRESCALE)) = (0x00000028)
+#define DEF_TU1_MICROSECOND_TIMER() (REG32(ADR_TU1_MICROSECOND_TIMER)) = (0x00000000)
+#define DEF_TU1_CURRENT_MICROSECOND_TIME_VALUE() (REG32(ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TU1_MICROSECOND_TIMER_LOCAL_PRESCALE() (REG32(ADR_TU1_MICROSECOND_TIMER_LOCAL_PRESCALE)) = (0x00000028)
+#define DEF_TU2_MICROSECOND_TIMER() (REG32(ADR_TU2_MICROSECOND_TIMER)) = (0x00000000)
+#define DEF_TU2_CURRENT_MICROSECOND_TIME_VALUE() (REG32(ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TU2_MICROSECOND_TIMER_LOCAL_PRESCALE() (REG32(ADR_TU2_MICROSECOND_TIMER_LOCAL_PRESCALE)) = (0x00000028)
+#define DEF_TU3_MICROSECOND_TIMER() (REG32(ADR_TU3_MICROSECOND_TIMER)) = (0x00000000)
+#define DEF_TU3_CURRENT_MICROSECOND_TIME_VALUE() (REG32(ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TU3_MICROSECOND_TIMER_LOCAL_PRESCALE() (REG32(ADR_TU3_MICROSECOND_TIMER_LOCAL_PRESCALE)) = (0x00000028)
+#define DEF_TM0_MILLISECOND_TIMER() (REG32(ADR_TM0_MILLISECOND_TIMER)) = (0x00000000)
+#define DEF_TM0_CURRENT_MILLISECOND_TIME_VALUE() (REG32(ADR_TM0_CURRENT_MILLISECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TM0_MILLISECOND_TIMER_PRESCALE() (REG32(ADR_TM0_MILLISECOND_TIMER_PRESCALE)) = (0x00000028)
+#define DEF_TM1_MILLISECOND_TIMER() (REG32(ADR_TM1_MILLISECOND_TIMER)) = (0x00000000)
+#define DEF_TM1_CURRENT_MILLISECOND_TIME_VALUE() (REG32(ADR_TM1_CURRENT_MILLISECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TM1_MILLISECOND_TIMER_PRESCALE() (REG32(ADR_TM1_MILLISECOND_TIMER_PRESCALE)) = (0x00000028)
+#define DEF_TM2_MILLISECOND_TIMER() (REG32(ADR_TM2_MILLISECOND_TIMER)) = (0x00000000)
+#define DEF_TM2_CURRENT_MILLISECOND_TIME_VALUE() (REG32(ADR_TM2_CURRENT_MILLISECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TM2_MILLISECOND_TIMER_PRESCALE() (REG32(ADR_TM2_MILLISECOND_TIMER_PRESCALE)) = (0x00000028)
+#define DEF_TM3_MILLISECOND_TIMER() (REG32(ADR_TM3_MILLISECOND_TIMER)) = (0x00000000)
+#define DEF_TM3_CURRENT_MILLISECOND_TIME_VALUE() (REG32(ADR_TM3_CURRENT_MILLISECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TM3_MILLISECOND_TIMER_PRESCALE() (REG32(ADR_TM3_MILLISECOND_TIMER_PRESCALE)) = (0x00000028)
+#define DEF_MCU_WDOG_REG() (REG32(ADR_MCU_WDOG_REG)) = (0x00010000)
+#define DEF_SYS_WDOG_REG() (REG32(ADR_SYS_WDOG_REG)) = (0x00010000)
+#define DEF_PWM_0_CTRL() (REG32(ADR_PWM_0_CTRL)) = (0x40000000)
+#define DEF_PWM_0_SET() (REG32(ADR_PWM_0_SET)) = (0x00000000)
+#define DEF_PWM_1_CTRL() (REG32(ADR_PWM_1_CTRL)) = (0x40000000)
+#define DEF_PWM_1_SET() (REG32(ADR_PWM_1_SET)) = (0x00000000)
+#define DEF_PWM_2_CTRL() (REG32(ADR_PWM_2_CTRL)) = (0x40000000)
+#define DEF_PWM_2_SET() (REG32(ADR_PWM_2_SET)) = (0x00000000)
+#define DEF_PWM_3_CTRL() (REG32(ADR_PWM_3_CTRL)) = (0x40000000)
+#define DEF_PWM_3_SET() (REG32(ADR_PWM_3_SET)) = (0x00000000)
+#define DEF_PWM_4_CTRL() (REG32(ADR_PWM_4_CTRL)) = (0x40000000)
+#define DEF_PWM_4_SET() (REG32(ADR_PWM_4_SET)) = (0x00000000)
+#define DEF_MANUAL_IO() (REG32(ADR_MANUAL_IO)) = (0x00000000)
+#define DEF_MANUAL_PU() (REG32(ADR_MANUAL_PU)) = (0x00000000)
+#define DEF_MANUAL_PD() (REG32(ADR_MANUAL_PD)) = (0x00000000)
+#define DEF_MANUAL_DS() (REG32(ADR_MANUAL_DS)) = (0x00000000)
+#define DEF_IO_PO() (REG32(ADR_IO_PO)) = (0x00000000)
+#define DEF_IO_PI() (REG32(ADR_IO_PI)) = (0x00000000)
+#define DEF_IO_PIE() (REG32(ADR_IO_PIE)) = (0x007fffff)
+#define DEF_IO_POEN() (REG32(ADR_IO_POEN)) = (0x007fffff)
+#define DEF_IO_PUE() (REG32(ADR_IO_PUE)) = (0x00000000)
+#define DEF_IO_PDE() (REG32(ADR_IO_PDE)) = (0x00000000)
+#define DEF_IO_DS() (REG32(ADR_IO_DS)) = (0x007fffff)
+#define DEF_IO_FUNC_SEL() (REG32(ADR_IO_FUNC_SEL)) = (0x00000000)
+#define DEF_INT_THRU_GPIO() (REG32(ADR_INT_THRU_GPIO)) = (0x00000000)
+#define DEF_BIST_CTRL() (REG32(ADR_BIST_CTRL)) = (0x00000050)
+#define DEF_BIST_CTRL1() (REG32(ADR_BIST_CTRL1)) = (0x00000000)
+#define DEF_BIST_CTRL2() (REG32(ADR_BIST_CTRL2)) = (0x00000000)
+#define DEF_I2CS_ID_ADDR() (REG32(ADR_I2CS_ID_ADDR)) = (0x000000a0)
+#define DEF_I2CS_STATUS() (REG32(ADR_I2CS_STATUS)) = (0x00000400)
+#define DEF_I2CS_TIME_CNT() (REG32(ADR_I2CS_TIME_CNT)) = (0x0000ffff)
+#define DEF_I2CS_STATE() (REG32(ADR_I2CS_STATE)) = (0x00000000)
+#define DEF_I2CS_CTRL() (REG32(ADR_I2CS_CTRL)) = (0x00000000)
+#define DEF_IO_PORT_REG() (REG32(ADR_IO_PORT_REG)) = (0x00010000)
+#define DEF_INT_MASK_REG() (REG32(ADR_INT_MASK_REG)) = (0x000000ff)
+#define DEF_INT_STATUS_REG() (REG32(ADR_INT_STATUS_REG)) = (0x00000000)
+#define DEF_FN1_STATUS_REG() (REG32(ADR_FN1_STATUS_REG)) = (0x00000000)
+#define DEF_CARD_RCA_REG() (REG32(ADR_CARD_RCA_REG)) = (0x00000000)
+#define DEF_SDIO_BYTE_MODE_BATCH_SIZE_REG() (REG32(ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG)) = (0x00000000)
+#define DEF_SDIO_CARD_STATUS_REG() (REG32(ADR_SDIO_CARD_STATUS_REG)) = (0x00000000)
+#define DEF_R5_RESP_FLAG_OUT_TIMING() (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (0x00040000)
+#define DEF_SDIO_DELAY_CHAIN_0() (REG32(ADR_SDIO_DELAY_CHAIN_0)) = (0x00000000)
+#define DEF_SDIO_DELAY_CHAIN_1() (REG32(ADR_SDIO_DELAY_CHAIN_1)) = (0x00000000)
+#define DEF_FN1_DMA_START_ADDR_REG() (REG32(ADR_FN1_DMA_START_ADDR_REG)) = (0x00000000)
+#define DEF_FN1_INT_CTRL_RESET() (REG32(ADR_FN1_INT_CTRL_RESET)) = (0x00000000)
+#define DEF_MCU_NOTIFY_HOST_EVENT() (REG32(ADR_MCU_NOTIFY_HOST_EVENT)) = (0x00000000)
+#define DEF_FN1_DMA_RD_START_ADDR_REG() (REG32(ADR_FN1_DMA_RD_START_ADDR_REG)) = (0x00000000)
+#define DEF_CCCR_00H_REG() (REG32(ADR_CCCR_00H_REG)) = (0x00000000)
+#define DEF_CCCR_04H_REG() (REG32(ADR_CCCR_04H_REG)) = (0x00000000)
+#define DEF_CCCR_08H_REG() (REG32(ADR_CCCR_08H_REG)) = (0x00000000)
+#define DEF_CCCR_14H_REG() (REG32(ADR_CCCR_14H_REG)) = (0x00000000)
+#define DEF_CCCR_13H_REG() (REG32(ADR_CCCR_13H_REG)) = (0x01000000)
+#define DEF_FBR_100H_REG() (REG32(ADR_FBR_100H_REG)) = (0x00000000)
+#define DEF_FBR_109H_REG() (REG32(ADR_FBR_109H_REG)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_0() (REG32(ADR_F0_CIS_CONTENT_REG_0)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_1() (REG32(ADR_F0_CIS_CONTENT_REG_1)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_2() (REG32(ADR_F0_CIS_CONTENT_REG_2)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_3() (REG32(ADR_F0_CIS_CONTENT_REG_3)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_4() (REG32(ADR_F0_CIS_CONTENT_REG_4)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_5() (REG32(ADR_F0_CIS_CONTENT_REG_5)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_6() (REG32(ADR_F0_CIS_CONTENT_REG_6)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_7() (REG32(ADR_F0_CIS_CONTENT_REG_7)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_8() (REG32(ADR_F0_CIS_CONTENT_REG_8)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_9() (REG32(ADR_F0_CIS_CONTENT_REG_9)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_10() (REG32(ADR_F0_CIS_CONTENT_REG_10)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_11() (REG32(ADR_F0_CIS_CONTENT_REG_11)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_12() (REG32(ADR_F0_CIS_CONTENT_REG_12)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_13() (REG32(ADR_F0_CIS_CONTENT_REG_13)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_14() (REG32(ADR_F0_CIS_CONTENT_REG_14)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_15() (REG32(ADR_F0_CIS_CONTENT_REG_15)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_0() (REG32(ADR_F1_CIS_CONTENT_REG_0)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_1() (REG32(ADR_F1_CIS_CONTENT_REG_1)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_2() (REG32(ADR_F1_CIS_CONTENT_REG_2)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_3() (REG32(ADR_F1_CIS_CONTENT_REG_3)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_4() (REG32(ADR_F1_CIS_CONTENT_REG_4)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_5() (REG32(ADR_F1_CIS_CONTENT_REG_5)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_6() (REG32(ADR_F1_CIS_CONTENT_REG_6)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_7() (REG32(ADR_F1_CIS_CONTENT_REG_7)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_8() (REG32(ADR_F1_CIS_CONTENT_REG_8)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_9() (REG32(ADR_F1_CIS_CONTENT_REG_9)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_10() (REG32(ADR_F1_CIS_CONTENT_REG_10)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_11() (REG32(ADR_F1_CIS_CONTENT_REG_11)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_12() (REG32(ADR_F1_CIS_CONTENT_REG_12)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_13() (REG32(ADR_F1_CIS_CONTENT_REG_13)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_14() (REG32(ADR_F1_CIS_CONTENT_REG_14)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_15() (REG32(ADR_F1_CIS_CONTENT_REG_15)) = (0x00000000)
+#define DEF_SPI_MODE() (REG32(ADR_SPI_MODE)) = (0x00000000)
+#define DEF_TX_SEG() (REG32(ADR_TX_SEG)) = (0x00000000)
+#define DEF_SPI_TO_PHY_PARAM1() (REG32(ADR_SPI_TO_PHY_PARAM1)) = (0x000e0006)
+#define DEF_SPI_TO_PHY_PARAM2() (REG32(ADR_SPI_TO_PHY_PARAM2)) = (0x000e000e)
+#define DEF_TWIM_EN() (REG32(ADR_TWIM_EN)) = (0x00000000)
+#define DEF_TWIM_STATUS_SETTING() (REG32(ADR_TWIM_STATUS_SETTING)) = (0x00030002)
+#define DEF_TWIM_INTERRUPT_EN() (REG32(ADR_TWIM_INTERRUPT_EN)) = (0x00000000)
+#define DEF_TWIM_INTERRUPT() (REG32(ADR_TWIM_INTERRUPT)) = (0x00000000)
+#define DEF_TWIM_INTERRUPT_STATUS() (REG32(ADR_TWIM_INTERRUPT_STATUS)) = (0x00000000)
+#define DEF_TWIM_STATUS_RECORD_0() (REG32(ADR_TWIM_STATUS_RECORD_0)) = (0x00000000)
+#define DEF_TWIM_STATUS_RECORD_1() (REG32(ADR_TWIM_STATUS_RECORD_1)) = (0x00000000)
+#define DEF_TWIM_DEV_A() (REG32(ADR_TWIM_DEV_A)) = (0x00000001)
+#define DEF_TWIM_TXD_DATA() (REG32(ADR_TWIM_TXD_DATA)) = (0x00000000)
+#define DEF_TWIM_RXD_DATA() (REG32(ADR_TWIM_RXD_DATA)) = (0x00000000)
+#define DEF_TWIM_PSCL() (REG32(ADR_TWIM_PSCL)) = (0x0014003f)
+#define DEF_TWIM_TRANS_PSDA() (REG32(ADR_TWIM_TRANS_PSDA)) = (0x00000005)
+#define DEF_TWIM_DELAY_ACK() (REG32(ADR_TWIM_DELAY_ACK)) = (0x00000000)
+#define DEF_I2CM_EN() (REG32(ADR_I2CM_EN)) = (0x000003f4)
+#define DEF_I2CM_DEV_A() (REG32(ADR_I2CM_DEV_A)) = (0x00008000)
+#define DEF_I2CM_LEN() (REG32(ADR_I2CM_LEN)) = (0x00000000)
+#define DEF_I2CM_WDAT() (REG32(ADR_I2CM_WDAT)) = (0x00000000)
+#define DEF_I2CM_RDAT() (REG32(ADR_I2CM_RDAT)) = (0x00000000)
+#define DEF_I2CM_EN_2() (REG32(ADR_I2CM_EN_2)) = (0x00010000)
+#define DEF_I2CM_START_STOP_PERIOD() (REG32(ADR_I2CM_START_STOP_PERIOD)) = (0x00000014)
+#define DEF_UART_DATA() (REG32(ADR_UART_DATA)) = (0x00000000)
+#define DEF_UART_IER() (REG32(ADR_UART_IER)) = (0x00000000)
+#define DEF_UART_FCR() (REG32(ADR_UART_FCR)) = (0x00000001)
+#define DEF_UART_LCR() (REG32(ADR_UART_LCR)) = (0x00000003)
+#define DEF_UART_MCR() (REG32(ADR_UART_MCR)) = (0x00000000)
+#define DEF_UART_LSR() (REG32(ADR_UART_LSR)) = (0x00000000)
+#define DEF_UART_MSR() (REG32(ADR_UART_MSR)) = (0x00000000)
+#define DEF_UART_SPR() (REG32(ADR_UART_SPR)) = (0x0000015b)
+#define DEF_UART_RTHR() (REG32(ADR_UART_RTHR)) = (0x000000c8)
+#define DEF_UART_ISR() (REG32(ADR_UART_ISR)) = (0x000000c1)
+#define DEF_UART_TTHR() (REG32(ADR_UART_TTHR)) = (0x000000c2)
+#define DEF_UART_INT_MAP() (REG32(ADR_UART_INT_MAP)) = (0x00000000)
+#define DEF_UART_POINTER() (REG32(ADR_UART_POINTER)) = (0x00000000)
+#define DEF_HSUART_TRX_CHAR() (REG32(ADR_HSUART_TRX_CHAR)) = (0x00000000)
+#define DEF_HSUART_INTRRUPT_ENABLE() (REG32(ADR_HSUART_INTRRUPT_ENABLE)) = (0x00000000)
+#define DEF_HSUART_FIFO_CTRL() (REG32(ADR_HSUART_FIFO_CTRL)) = (0x00000000)
+#define DEF_HSUART_LINE_CTRL() (REG32(ADR_HSUART_LINE_CTRL)) = (0x00000000)
+#define DEF_HSUART_MODEM_CTRL() (REG32(ADR_HSUART_MODEM_CTRL)) = (0x00000000)
+#define DEF_HSUART_LINE_STATUS() (REG32(ADR_HSUART_LINE_STATUS)) = (0x00000000)
+#define DEF_HSUART_MODEM_STATUS() (REG32(ADR_HSUART_MODEM_STATUS)) = (0x00000000)
+#define DEF_HSUART_SCRATCH_BOARD() (REG32(ADR_HSUART_SCRATCH_BOARD)) = (0x00000000)
+#define DEF_HSUART_FIFO_THRESHOLD() (REG32(ADR_HSUART_FIFO_THRESHOLD)) = (0x18041810)
+#define DEF_HSUART_INTERRUPT_STATUS() (REG32(ADR_HSUART_INTERRUPT_STATUS)) = (0x00000000)
+#define DEF_HSUART_DIV_FRAC() (REG32(ADR_HSUART_DIV_FRAC)) = (0x0067002b)
+#define DEF_HSUART_EXPANSION_INTERRUPT_STATUS() (REG32(ADR_HSUART_EXPANSION_INTERRUPT_STATUS)) = (0x00000000)
+#define DEF_HSUART_DMA_RX_STR_ADDR() (REG32(ADR_HSUART_DMA_RX_STR_ADDR)) = (0x00000000)
+#define DEF_HSUART_DMA_RX_END_ADDR() (REG32(ADR_HSUART_DMA_RX_END_ADDR)) = (0x00000000)
+#define DEF_HSUART_DMA_RX_WPT() (REG32(ADR_HSUART_DMA_RX_WPT)) = (0x00000000)
+#define DEF_HSUART_DMA_RX_RPT() (REG32(ADR_HSUART_DMA_RX_RPT)) = (0x00000000)
+#define DEF_HSUART_DMA_TX_STR_ADDR() (REG32(ADR_HSUART_DMA_TX_STR_ADDR)) = (0x00000000)
+#define DEF_HSUART_DMA_TX_END_ADDR() (REG32(ADR_HSUART_DMA_TX_END_ADDR)) = (0x00000000)
+#define DEF_HSUART_DMA_TX_WPT() (REG32(ADR_HSUART_DMA_TX_WPT)) = (0x00000000)
+#define DEF_HSUART_DMA_TX_RPT() (REG32(ADR_HSUART_DMA_TX_RPT)) = (0x00000000)
+#define DEF_MANUAL_MODE_TX_ADDR() (REG32(ADR_MANUAL_MODE_TX_ADDR)) = (0x00000000)
+#define DEF_MANUAL_MODE_RX_ADDR() (REG32(ADR_MANUAL_MODE_RX_ADDR)) = (0x00000000)
+#define DEF_SPI_PARAM() (REG32(ADR_SPI_PARAM)) = (0x00000444)
+#define DEF_SPI_PARAM2() (REG32(ADR_SPI_PARAM2)) = (0x00000000)
+#define DEF_SPI_TX_LEN() (REG32(ADR_SPI_TX_LEN)) = (0x00000000)
+#define DEF_SPI_RX_LEN() (REG32(ADR_SPI_RX_LEN)) = (0x00000000)
+#define DEF_CMD_SET() (REG32(ADR_CMD_SET)) = (0xebbb0b02)
+#define DEF_CMD_SET_1() (REG32(ADR_CMD_SET_1)) = (0x00000032)
+#define DEF_FLASH_IO0_DLY() (REG32(ADR_FLASH_IO0_DLY)) = (0x00000000)
+#define DEF_FLASH_IO1_DLY() (REG32(ADR_FLASH_IO1_DLY)) = (0x00000100)
+#define DEF_INS_SPACE_START_ADDR() (REG32(ADR_INS_SPACE_START_ADDR)) = (0x00000000)
+#define DEF_INS_SPACE_END_ADDR() (REG32(ADR_INS_SPACE_END_ADDR)) = (0x00000000)
+#define DEF_BUFFER_CLEAR_ERROR_FLAG_CLEAR() (REG32(ADR_BUFFER_CLEAR_ERROR_FLAG_CLEAR)) = (0x00000000)
+#define DEF_DMA_ADR_SRC() (REG32(ADR_DMA_ADR_SRC)) = (0x00000000)
+#define DEF_DMA_ADR_DST() (REG32(ADR_DMA_ADR_DST)) = (0x00000000)
+#define DEF_DMA_CTRL() (REG32(ADR_DMA_CTRL)) = (0x000000aa)
+#define DEF_DMA_INT() (REG32(ADR_DMA_INT)) = (0x00000001)
+#define DEF_DMA_FILL_CONST() (REG32(ADR_DMA_FILL_CONST)) = (0x00000000)
+#define DEF_D2_DMA_ADR_SRC() (REG32(ADR_D2_DMA_ADR_SRC)) = (0x00000000)
+#define DEF_D2_DMA_ADR_DST() (REG32(ADR_D2_DMA_ADR_DST)) = (0x00000000)
+#define DEF_D2_DMA_CTRL() (REG32(ADR_D2_DMA_CTRL)) = (0x000000aa)
+#define DEF_D2_DMA_INT() (REG32(ADR_D2_DMA_INT)) = (0x00000001)
+#define DEF_D2_DMA_FILL_CONST() (REG32(ADR_D2_DMA_FILL_CONST)) = (0x00000000)
+#define DEF_MASK_TYPHOST_INT_MAP_02() (REG32(ADR_MASK_TYPHOST_INT_MAP_02)) = (0xffffffff)
+#define DEF_RAW_TYPHOST_INT_MAP_02() (REG32(ADR_RAW_TYPHOST_INT_MAP_02)) = (0xffffffff)
+#define DEF_POSTMASK_TYPHOST_INT_MAP_02() (REG32(ADR_POSTMASK_TYPHOST_INT_MAP_02)) = (0xffffffff)
+#define DEF_MASK_TYPHOST_INT_MAP_15() (REG32(ADR_MASK_TYPHOST_INT_MAP_15)) = (0xffffffff)
+#define DEF_RAW_TYPHOST_INT_MAP_15() (REG32(ADR_RAW_TYPHOST_INT_MAP_15)) = (0xffffffff)
+#define DEF_POSTMASK_TYPHOST_INT_MAP_15() (REG32(ADR_POSTMASK_TYPHOST_INT_MAP_15)) = (0xffffffff)
+#define DEF_MASK_TYPHOST_INT_MAP_31() (REG32(ADR_MASK_TYPHOST_INT_MAP_31)) = (0xffffffff)
+#define DEF_RAW_TYPHOST_INT_MAP_31() (REG32(ADR_RAW_TYPHOST_INT_MAP_31)) = (0xffffffff)
+#define DEF_POSTMASK_TYPHOST_INT_MAP_31() (REG32(ADR_POSTMASK_TYPHOST_INT_MAP_31)) = (0xffffffff)
+#define DEF_MASK_TYPHOST_INT_MAP() (REG32(ADR_MASK_TYPHOST_INT_MAP)) = (0xffffffff)
+#define DEF_RAW_TYPHOST_INT_MAP() (REG32(ADR_RAW_TYPHOST_INT_MAP)) = (0xffffffff)
+#define DEF_POSTMASK_TYPHOST_INT_MAP() (REG32(ADR_POSTMASK_TYPHOST_INT_MAP)) = (0xffffffff)
+#define DEF_SUMMARY_TYPHOST_INT_MAP() (REG32(ADR_SUMMARY_TYPHOST_INT_MAP)) = (0x00000000)
+#define DEF_MASK_TYPMCU_INT_MAP_02() (REG32(ADR_MASK_TYPMCU_INT_MAP_02)) = (0xffffffff)
+#define DEF_RAW_TYPMCU_INT_MAP_02() (REG32(ADR_RAW_TYPMCU_INT_MAP_02)) = (0xffffffff)
+#define DEF_POSTMASK_TYPMCU_INT_MAP_02() (REG32(ADR_POSTMASK_TYPMCU_INT_MAP_02)) = (0xffffffff)
+#define DEF_MASK_TYPMCU_INT_MAP_15() (REG32(ADR_MASK_TYPMCU_INT_MAP_15)) = (0xffffffff)
+#define DEF_RAW_TYPMCU_INT_MAP_15() (REG32(ADR_RAW_TYPMCU_INT_MAP_15)) = (0xffffffff)
+#define DEF_POSTMASK_TYPMCU_INT_MAP_15() (REG32(ADR_POSTMASK_TYPMCU_INT_MAP_15)) = (0xffffffff)
+#define DEF_MASK_TYPMCU_INT_MAP_31() (REG32(ADR_MASK_TYPMCU_INT_MAP_31)) = (0xffffffff)
+#define DEF_RAW_TYPMCU_INT_MAP_31() (REG32(ADR_RAW_TYPMCU_INT_MAP_31)) = (0xffffffff)
+#define DEF_POSTMASK_TYPMCU_INT_MAP_31() (REG32(ADR_POSTMASK_TYPMCU_INT_MAP_31)) = (0xffffffff)
+#define DEF_MASK_TYPMCU_INT_MAP() (REG32(ADR_MASK_TYPMCU_INT_MAP)) = (0xffffffff)
+#define DEF_RAW_TYPMCU_INT_MAP() (REG32(ADR_RAW_TYPMCU_INT_MAP)) = (0xffffffff)
+#define DEF_POSTMASK_TYPMCU_INT_MAP() (REG32(ADR_POSTMASK_TYPMCU_INT_MAP)) = (0xffffffff)
+#define DEF_SUMMARY_TYPMCU_INT_MAP() (REG32(ADR_SUMMARY_TYPMCU_INT_MAP)) = (0x00000000)
+#define DEF_GPIO_INTERRUPT_BANK_00_TO_07() (REG32(ADR_GPIO_INTERRUPT_BANK_00_TO_07)) = (0x00000000)
+#define DEF_GPIO_INTERRUPT_BANK_08_TO_15() (REG32(ADR_GPIO_INTERRUPT_BANK_08_TO_15)) = (0x00000000)
+#define DEF_GPIO_INTERRUPT_BANK_16_TO_22() (REG32(ADR_GPIO_INTERRUPT_BANK_16_TO_22)) = (0x00000000)
+#define DEF_GPIO_INTERRUPT_MODE_00_TO_07() (REG32(ADR_GPIO_INTERRUPT_MODE_00_TO_07)) = (0x00000000)
+#define DEF_GPIO_INTERRUPT_MODE_08_TO_15() (REG32(ADR_GPIO_INTERRUPT_MODE_08_TO_15)) = (0x00000000)
+#define DEF_GPIO_INTERRUPT_MODE_16_TO_22() (REG32(ADR_GPIO_INTERRUPT_MODE_16_TO_22)) = (0x00000000)
+#define DEF_IPC_INTERRUPT() (REG32(ADR_IPC_INTERRUPT)) = (0x00000000)
+#define DEF_CLR_INT_STS2() (REG32(ADR_CLR_INT_STS2)) = (0x00000000)
+#define DEF_CLR_INT_STS1() (REG32(ADR_CLR_INT_STS1)) = (0x00000000)
+#define DEF_CLR_INT_STS0() (REG32(ADR_CLR_INT_STS0)) = (0x00000000)
+#define DEF_ROM_PATCH02_0() (REG32(ADR_ROM_PATCH02_0)) = (0x00000000)
+#define DEF_ROM_PATCH02_1() (REG32(ADR_ROM_PATCH02_1)) = (0x00000000)
+#define DEF_ROM_PATCH03_0() (REG32(ADR_ROM_PATCH03_0)) = (0x00000000)
+#define DEF_ROM_PATCH03_1() (REG32(ADR_ROM_PATCH03_1)) = (0x00000000)
+#define DEF_ROM_PATCH04_0() (REG32(ADR_ROM_PATCH04_0)) = (0x00000000)
+#define DEF_ROM_PATCH04_1() (REG32(ADR_ROM_PATCH04_1)) = (0x00000000)
+#define DEF_ROM_PATCH05_0() (REG32(ADR_ROM_PATCH05_0)) = (0x00000000)
+#define DEF_ROM_PATCH05_1() (REG32(ADR_ROM_PATCH05_1)) = (0x00000000)
+#define DEF_ROM_PATCH06_0() (REG32(ADR_ROM_PATCH06_0)) = (0x00000000)
+#define DEF_ROM_PATCH06_1() (REG32(ADR_ROM_PATCH06_1)) = (0x00000000)
+#define DEF_ROM_PATCH07_0() (REG32(ADR_ROM_PATCH07_0)) = (0x00000000)
+#define DEF_ROM_PATCH07_1() (REG32(ADR_ROM_PATCH07_1)) = (0x00000000)
+#define DEF_ROM_PATCH08_0() (REG32(ADR_ROM_PATCH08_0)) = (0x00000000)
+#define DEF_ROM_PATCH08_1() (REG32(ADR_ROM_PATCH08_1)) = (0x00000000)
+#define DEF_ROM_PATCH09_0() (REG32(ADR_ROM_PATCH09_0)) = (0x00000000)
+#define DEF_ROM_PATCH09_1() (REG32(ADR_ROM_PATCH09_1)) = (0x00000000)
+#define DEF_ROM_PATCH10_0() (REG32(ADR_ROM_PATCH10_0)) = (0x00000000)
+#define DEF_ROM_PATCH10_1() (REG32(ADR_ROM_PATCH10_1)) = (0x00000000)
+#define DEF_ROM_PATCH11_0() (REG32(ADR_ROM_PATCH11_0)) = (0x00000000)
+#define DEF_ROM_PATCH11_1() (REG32(ADR_ROM_PATCH11_1)) = (0x00000000)
+#define DEF_ROM_PATCH12_0() (REG32(ADR_ROM_PATCH12_0)) = (0x00000000)
+#define DEF_ROM_PATCH12_1() (REG32(ADR_ROM_PATCH12_1)) = (0x00000000)
+#define DEF_ROM_PATCH13_0() (REG32(ADR_ROM_PATCH13_0)) = (0x00000000)
+#define DEF_ROM_PATCH13_1() (REG32(ADR_ROM_PATCH13_1)) = (0x00000000)
+#define DEF_ROM_PATCH14_0() (REG32(ADR_ROM_PATCH14_0)) = (0x00000000)
+#define DEF_ROM_PATCH14_1() (REG32(ADR_ROM_PATCH14_1)) = (0x00000000)
+#define DEF_ROM_PATCH15_0() (REG32(ADR_ROM_PATCH15_0)) = (0x00000000)
+#define DEF_ROM_PATCH15_1() (REG32(ADR_ROM_PATCH15_1)) = (0x00000000)
+#define DEF_BROWNOUT_INT() (REG32(ADR_BROWNOUT_INT)) = (0x00000000)
+#define DEF_BROWNOUT_SETUP() (REG32(ADR_BROWNOUT_SETUP)) = (0x0000000f)
+#define DEF_CONTROL() (REG32(ADR_CONTROL)) = (0x00700008)
+#define DEF_HCI_TRX_MODE() (REG32(ADR_HCI_TRX_MODE)) = (0x00000002)
+#define DEF_TX_FLOW_0() (REG32(ADR_TX_FLOW_0)) = (0x00000000)
+#define DEF_TX_FLOW_1() (REG32(ADR_TX_FLOW_1)) = (0x00000000)
+#define DEF_REMAINING_RX_PACKET_LENGTH() (REG32(ADR_REMAINING_RX_PACKET_LENGTH)) = (0x00000000)
+#define DEF_RX_PACKET_LENGTH_STATUS() (REG32(ADR_RX_PACKET_LENGTH_STATUS)) = (0x00000000)
+#define DEF_THRESHOLD() (REG32(ADR_THRESHOLD)) = (0x09000000)
+#define DEF_TX_ERROR_RECEOVERY() (REG32(ADR_TX_ERROR_RECEOVERY)) = (0x00000002)
+#define DEF_TXFID_INCREASE() (REG32(ADR_TXFID_INCREASE)) = (0x00000000)
+#define DEF_GLOBAL_SEQUENCE() (REG32(ADR_GLOBAL_SEQUENCE)) = (0x00000000)
+#define DEF_HCI_REG_0X2C() (REG32(ADR_HCI_REG_0X2C)) = (0x00000300)
+#define DEF_HCI_TX_RX_INFO_SIZE() (REG32(ADR_HCI_TX_RX_INFO_SIZE)) = (0x00040450)
+#define DEF_HCI_TX_INFO_CLEAR() (REG32(ADR_HCI_TX_INFO_CLEAR)) = (0x00000008)
+#define DEF_HCI_TO_PKTBUF_SETTING() (REG32(ADR_HCI_TO_PKTBUF_SETTING)) = (0x00000410)
+#define DEF_HCI_MANUAL_ALLOC() (REG32(ADR_HCI_MANUAL_ALLOC)) = (0x00000000)
+#define DEF_HCI_MANUAL_ALLOC_ACTION() (REG32(ADR_HCI_MANUAL_ALLOC_ACTION)) = (0x00000000)
+#define DEF_HCI_MANUAL_ALLOC_STATUS() (REG32(ADR_HCI_MANUAL_ALLOC_STATUS)) = (0x00000000)
+#define DEF_TX_ETHER_TYPE_0() (REG32(ADR_TX_ETHER_TYPE_0)) = (0x00000000)
+#define DEF_TX_ETHER_TYPE_1() (REG32(ADR_TX_ETHER_TYPE_1)) = (0x00000000)
+#define DEF_RX_ETHER_TYPE_0() (REG32(ADR_RX_ETHER_TYPE_0)) = (0x00000000)
+#define DEF_RX_ETHER_TYPE_1() (REG32(ADR_RX_ETHER_TYPE_1)) = (0x00000000)
+#define DEF_TX_PACKET_LENGTH() (REG32(ADR_TX_PACKET_LENGTH)) = (0x00000000)
+#define DEF_TX_PACKET_ID() (REG32(ADR_TX_PACKET_ID)) = (0x00000000)
+#define DEF_RX_RESCUE_HELPER() (REG32(ADR_RX_RESCUE_HELPER)) = (0x00000000)
+#define DEF_HCI_FORCE_PRE_BULK_IN() (REG32(ADR_HCI_FORCE_PRE_BULK_IN)) = (0x00000000)
+#define DEF_HCI_BULK_IN_TIME_OUT_VALUE() (REG32(ADR_HCI_BULK_IN_TIME_OUT_VALUE)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_0() (REG32(ADR_HCI_STATE_DEBUG_MODE_0)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_2() (REG32(ADR_HCI_STATE_DEBUG_MODE_2)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_3() (REG32(ADR_HCI_STATE_DEBUG_MODE_3)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_4() (REG32(ADR_HCI_STATE_DEBUG_MODE_4)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_5() (REG32(ADR_HCI_STATE_DEBUG_MODE_5)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_6() (REG32(ADR_HCI_STATE_DEBUG_MODE_6)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_7() (REG32(ADR_HCI_STATE_DEBUG_MODE_7)) = (0x00000000)
+#define DEF_HCI_TX_ON_DEMAND_LENGTH() (REG32(ADR_HCI_TX_ON_DEMAND_LENGTH)) = (0x00000000)
+#define DEF_HCI_TX_ALLOC_SUCCESS_COUNT() (REG32(ADR_HCI_TX_ALLOC_SUCCESS_COUNT)) = (0x00000000)
+#define DEF_HCI_TX_ALLOC_SPENDING_TIME() (REG32(ADR_HCI_TX_ALLOC_SPENDING_TIME)) = (0x00000000)
+#define DEF_RX_TRAP_COUNT() (REG32(ADR_RX_TRAP_COUNT)) = (0x00000000)
+#define DEF_TX_TRAP_COUNT() (REG32(ADR_TX_TRAP_COUNT)) = (0x00000000)
+#define DEF_RX_DROP_COUNT() (REG32(ADR_RX_DROP_COUNT)) = (0x00000000)
+#define DEF_TX_DROP_COUNT() (REG32(ADR_TX_DROP_COUNT)) = (0x00000000)
+#define DEF_RX_HOST_EVENT_COUNT() (REG32(ADR_RX_HOST_EVENT_COUNT)) = (0x00000000)
+#define DEF_TX_HOST_COMMAND_COUNT() (REG32(ADR_TX_HOST_COMMAND_COUNT)) = (0x00000000)
+#define DEF_RX_PACKET_COUNTER() (REG32(ADR_RX_PACKET_COUNTER)) = (0x00000000)
+#define DEF_TX_PACKET_COUNTER() (REG32(ADR_TX_PACKET_COUNTER)) = (0x00000000)
+#define DEF_SDIO_RX_FAIL_COUNT() (REG32(ADR_SDIO_RX_FAIL_COUNT)) = (0x00000000)
+#define DEF_SDIO_TX_FAIL_COUNT() (REG32(ADR_SDIO_TX_FAIL_COUNT)) = (0x00000000)
+#define DEF_CORRECT_RATE_REPORT_LENGTH() (REG32(ADR_CORRECT_RATE_REPORT_LENGTH)) = (0x00000000)
+#define DEF_TX_PACKET_SEND_TO_RX_DIRECTLY() (REG32(ADR_TX_PACKET_SEND_TO_RX_DIRECTLY)) = (0x00000000)
+#define DEF_POWER_SAVING_PEER_REJECT_FUNCTION() (REG32(ADR_POWER_SAVING_PEER_REJECT_FUNCTION)) = (0x00000000)
+#define DEF_TX_RX_TRAP_HW_ID_SELECTION_FUNCTION() (REG32(ADR_TX_RX_TRAP_HW_ID_SELECTION_FUNCTION)) = (0x00000000)
+#define DEF_RX_HCI_EXP_0_CTRL() (REG32(ADR_RX_HCI_EXP_0_CTRL)) = (0x00000000)
+#define DEF_RX_HCI_EXP_0_LEN() (REG32(ADR_RX_HCI_EXP_0_LEN)) = (0x400000c8)
+#define DEF_FORCE_RX_AGGREGATION_MODE() (REG32(ADR_FORCE_RX_AGGREGATION_MODE)) = (0x03200002)
+#define DEF_CS_START_ADDR() (REG32(ADR_CS_START_ADDR)) = (0x00000000)
+#define DEF_CS_ADD_LEN() (REG32(ADR_CS_ADD_LEN)) = (0x00000000)
+#define DEF_CS_CMD() (REG32(ADR_CS_CMD)) = (0x00000000)
+#define DEF_CS_INI_BUF() (REG32(ADR_CS_INI_BUF)) = (0x00000000)
+#define DEF_CS_PSEUDO_BUF() (REG32(ADR_CS_PSEUDO_BUF)) = (0x00000000)
+#define DEF_CS_CHECK_SUM() (REG32(ADR_CS_CHECK_SUM)) = (0x00000000)
+#define DEF_RAND_EN() (REG32(ADR_RAND_EN)) = (0x00000000)
+#define DEF_RAND_NUM() (REG32(ADR_RAND_NUM)) = (0x00000000)
+#define DEF_MUL_OP1() (REG32(ADR_MUL_OP1)) = (0x00000000)
+#define DEF_MUL_OP2() (REG32(ADR_MUL_OP2)) = (0x00000000)
+#define DEF_MUL_ANS0() (REG32(ADR_MUL_ANS0)) = (0x00000000)
+#define DEF_MUL_ANS1() (REG32(ADR_MUL_ANS1)) = (0x00000000)
+#define DEF_DMA_RDATA() (REG32(ADR_DMA_RDATA)) = (0x00000000)
+#define DEF_DMA_WDATA() (REG32(ADR_DMA_WDATA)) = (0x00000000)
+#define DEF_DMA_LEN() (REG32(ADR_DMA_LEN)) = (0x00000000)
+#define DEF_DMA_CLR() (REG32(ADR_DMA_CLR)) = (0x00000000)
+#define DEF_NAV_DATA() (REG32(ADR_NAV_DATA)) = (0x00000000)
+#define DEF_CO_NAV() (REG32(ADR_CO_NAV)) = (0x00000000)
+#define DEF_SHA_DST_ADDR() (REG32(ADR_SHA_DST_ADDR)) = (0x00000000)
+#define DEF_SHA_SRC_ADDR() (REG32(ADR_SHA_SRC_ADDR)) = (0x00000000)
+#define DEF_SHA_SETTING() (REG32(ADR_SHA_SETTING)) = (0x00000002)
+#define DEF_EFUSE_CLK_FREQ() (REG32(ADR_EFUSE_CLK_FREQ)) = (0x610100d0)
+#define DEF_EFUSE_LDO_TIME() (REG32(ADR_EFUSE_LDO_TIME)) = (0x00020002)
+#define DEF_EFUSE_STATUS() (REG32(ADR_EFUSE_STATUS)) = (0x00000000)
+#define DEF_EFUSE_STATUS2() (REG32(ADR_EFUSE_STATUS2)) = (0x00000000)
+#define DEF_EFUSE_WR_KICK() (REG32(ADR_EFUSE_WR_KICK)) = (0x00000000)
+#define DEF_EFUSE_RD_KICK() (REG32(ADR_EFUSE_RD_KICK)) = (0x00000000)
+#define DEF_EFUSE_VDDQ_EN() (REG32(ADR_EFUSE_VDDQ_EN)) = (0x00000000)
+#define DEF_EFUSE_WDATA_0_0() (REG32(ADR_EFUSE_WDATA_0_0)) = (0x00000000)
+#define DEF_EFUSE_WDATA_0_1() (REG32(ADR_EFUSE_WDATA_0_1)) = (0x00000000)
+#define DEF_EFUSE_WDATA_0_2() (REG32(ADR_EFUSE_WDATA_0_2)) = (0x00000000)
+#define DEF_EFUSE_WDATA_0_3() (REG32(ADR_EFUSE_WDATA_0_3)) = (0x00000000)
+#define DEF_EFUSE_WDATA_0_4() (REG32(ADR_EFUSE_WDATA_0_4)) = (0x00000000)
+#define DEF_EFUSE_WDATA_0_5() (REG32(ADR_EFUSE_WDATA_0_5)) = (0x00000000)
+#define DEF_EFUSE_WDATA_0_6() (REG32(ADR_EFUSE_WDATA_0_6)) = (0x00000000)
+#define DEF_EFUSE_WDATA_0_7() (REG32(ADR_EFUSE_WDATA_0_7)) = (0x00000000)
+#define DEF_SPI_DELAY() (REG32(ADR_SPI_DELAY)) = (0x000f000f)
+#define DEF_SPI_CLK_DIV() (REG32(ADR_SPI_CLK_DIV)) = (0x00000001)
+#define DEF_SPI_BUSY() (REG32(ADR_SPI_BUSY)) = (0x00000000)
+#define DEF_SPI_CLR() (REG32(ADR_SPI_CLR)) = (0x00000000)
+#define DEF_SPI_MAS_MODE() (REG32(ADR_SPI_MAS_MODE)) = (0x00000000)
+#define DEF_SPI_M_CFG() (REG32(ADR_SPI_M_CFG)) = (0x00000008)
+#define DEF_SPI_CFG() (REG32(ADR_SPI_CFG)) = (0x00000001)
+#define DEF_SPI_MAS_COMMAND_LEN() (REG32(ADR_SPI_MAS_COMMAND_LEN)) = (0x00000000)
+#define DEF_MRX_MCAST_TB0_0() (REG32(ADR_MRX_MCAST_TB0_0)) = (0x00000000)
+#define DEF_MRX_MCAST_TB0_1() (REG32(ADR_MRX_MCAST_TB0_1)) = (0x00000000)
+#define DEF_MRX_MCAST_MK0_0() (REG32(ADR_MRX_MCAST_MK0_0)) = (0x00000000)
+#define DEF_MRX_MCAST_MK0_1() (REG32(ADR_MRX_MCAST_MK0_1)) = (0x00000000)
+#define DEF_MRX_MCAST_CTRL0() (REG32(ADR_MRX_MCAST_CTRL0)) = (0x00000000)
+#define DEF_MRX_MCAST_TB1_0() (REG32(ADR_MRX_MCAST_TB1_0)) = (0x00000000)
+#define DEF_MRX_MCAST_TB1_1() (REG32(ADR_MRX_MCAST_TB1_1)) = (0x00000000)
+#define DEF_MRX_MCAST_MK1_0() (REG32(ADR_MRX_MCAST_MK1_0)) = (0x00000000)
+#define DEF_MRX_MCAST_MK1_1() (REG32(ADR_MRX_MCAST_MK1_1)) = (0x00000000)
+#define DEF_MRX_MCAST_CTRL1() (REG32(ADR_MRX_MCAST_CTRL1)) = (0x00000000)
+#define DEF_MRX_MCAST_TB2_0() (REG32(ADR_MRX_MCAST_TB2_0)) = (0x00000000)
+#define DEF_MRX_MCAST_TB2_1() (REG32(ADR_MRX_MCAST_TB2_1)) = (0x00000000)
+#define DEF_MRX_MCAST_MK2_0() (REG32(ADR_MRX_MCAST_MK2_0)) = (0x00000000)
+#define DEF_MRX_MCAST_MK2_1() (REG32(ADR_MRX_MCAST_MK2_1)) = (0x00000000)
+#define DEF_MRX_MCAST_CTRL2() (REG32(ADR_MRX_MCAST_CTRL2)) = (0x00000000)
+#define DEF_MRX_MCAST_TB3_0() (REG32(ADR_MRX_MCAST_TB3_0)) = (0x00000000)
+#define DEF_MRX_MCAST_TB3_1() (REG32(ADR_MRX_MCAST_TB3_1)) = (0x00000000)
+#define DEF_MRX_MCAST_MK3_0() (REG32(ADR_MRX_MCAST_MK3_0)) = (0x00000000)
+#define DEF_MRX_MCAST_MK3_1() (REG32(ADR_MRX_MCAST_MK3_1)) = (0x00000000)
+#define DEF_MRX_MCAST_CTRL3() (REG32(ADR_MRX_MCAST_CTRL3)) = (0x00000000)
+#define DEF_MRX_PHY_INFO() (REG32(ADR_MRX_PHY_INFO)) = (0x00000000)
+#define DEF_MRX_BA_DBG() (REG32(ADR_MRX_BA_DBG)) = (0x00000000)
+#define DEF_MRX_FLT_TB0() (REG32(ADR_MRX_FLT_TB0)) = (0x00003df5)
+#define DEF_MRX_FLT_TB1() (REG32(ADR_MRX_FLT_TB1)) = (0x000031f6)
+#define DEF_MRX_FLT_TB2() (REG32(ADR_MRX_FLT_TB2)) = (0x000035f9)
+#define DEF_MRX_FLT_TB3() (REG32(ADR_MRX_FLT_TB3)) = (0x000021c1)
+#define DEF_MRX_FLT_TB4() (REG32(ADR_MRX_FLT_TB4)) = (0x00004bf9)
+#define DEF_MRX_FLT_TB5() (REG32(ADR_MRX_FLT_TB5)) = (0x00004db1)
+#define DEF_MRX_FLT_TB6() (REG32(ADR_MRX_FLT_TB6)) = (0x000011fe)
+#define DEF_MRX_FLT_TB7() (REG32(ADR_MRX_FLT_TB7)) = (0x00000bfe)
+#define DEF_MRX_FLT_TB8() (REG32(ADR_MRX_FLT_TB8)) = (0x00000000)
+#define DEF_MRX_FLT_TB9() (REG32(ADR_MRX_FLT_TB9)) = (0x00000000)
+#define DEF_MRX_FLT_TB10() (REG32(ADR_MRX_FLT_TB10)) = (0x00000000)
+#define DEF_MRX_FLT_TB11() (REG32(ADR_MRX_FLT_TB11)) = (0x00000006)
+#define DEF_MRX_FLT_TB12() (REG32(ADR_MRX_FLT_TB12)) = (0x00000001)
+#define DEF_MRX_FLT_TB13() (REG32(ADR_MRX_FLT_TB13)) = (0x00000003)
+#define DEF_MRX_FLT_TB14() (REG32(ADR_MRX_FLT_TB14)) = (0x00000005)
+#define DEF_MRX_FLT_TB15() (REG32(ADR_MRX_FLT_TB15)) = (0x00000007)
+#define DEF_MRX_FLT_EN0() (REG32(ADR_MRX_FLT_EN0)) = (0x00002008)
+#define DEF_MRX_FLT_EN1() (REG32(ADR_MRX_FLT_EN1)) = (0x00001001)
+#define DEF_MRX_FLT_EN2() (REG32(ADR_MRX_FLT_EN2)) = (0x00000808)
+#define DEF_MRX_FLT_EN3() (REG32(ADR_MRX_FLT_EN3)) = (0x00001000)
+#define DEF_MRX_FLT_EN4() (REG32(ADR_MRX_FLT_EN4)) = (0x00002008)
+#define DEF_MRX_FLT_EN5() (REG32(ADR_MRX_FLT_EN5)) = (0x0000800e)
+#define DEF_MRX_FLT_EN6() (REG32(ADR_MRX_FLT_EN6)) = (0x00000838)
+#define DEF_MRX_FLT_EN7() (REG32(ADR_MRX_FLT_EN7)) = (0x00002008)
+#define DEF_MRX_FLT_EN8() (REG32(ADR_MRX_FLT_EN8)) = (0x00002008)
+#define DEF_MRX_LEN_FLT() (REG32(ADR_MRX_LEN_FLT)) = (0x00000000)
+#define DEF_RX_FLOW_DATA() (REG32(ADR_RX_FLOW_DATA)) = (0x00105034)
+#define DEF_RX_FLOW_MNG() (REG32(ADR_RX_FLOW_MNG)) = (0x00000004)
+#define DEF_RX_FLOW_CTRL() (REG32(ADR_RX_FLOW_CTRL)) = (0x00000004)
+#define DEF_RX_TIME_STAMP_CFG() (REG32(ADR_RX_TIME_STAMP_CFG)) = (0x00001c00)
+#define DEF_DBG_FF_FULL() (REG32(ADR_DBG_FF_FULL)) = (0x00000000)
+#define DEF_DBG_WFF_FULL() (REG32(ADR_DBG_WFF_FULL)) = (0x00000000)
+#define DEF_DBG_MB_FULL() (REG32(ADR_DBG_MB_FULL)) = (0x00000000)
+#define DEF_BA_CTRL() (REG32(ADR_BA_CTRL)) = (0x00000008)
+#define DEF_BA_TA_0() (REG32(ADR_BA_TA_0)) = (0x00000000)
+#define DEF_BA_TA_1() (REG32(ADR_BA_TA_1)) = (0x00000000)
+#define DEF_BA_TID() (REG32(ADR_BA_TID)) = (0x00000000)
+#define DEF_BA_ST_SEQ() (REG32(ADR_BA_ST_SEQ)) = (0x00000000)
+#define DEF_BA_SB0() (REG32(ADR_BA_SB0)) = (0x00000000)
+#define DEF_BA_SB1() (REG32(ADR_BA_SB1)) = (0x00000000)
+#define DEF_MRX_WATCH_DOG() (REG32(ADR_MRX_WATCH_DOG)) = (0x0000ffff)
+#define DEF_ACK_GEN_EN() (REG32(ADR_ACK_GEN_EN)) = (0x00000000)
+#define DEF_ACK_GEN_PARA() (REG32(ADR_ACK_GEN_PARA)) = (0x00000000)
+#define DEF_ACK_GEN_RA_0() (REG32(ADR_ACK_GEN_RA_0)) = (0x00000000)
+#define DEF_ACK_GEN_RA_1() (REG32(ADR_ACK_GEN_RA_1)) = (0x00000000)
+#define DEF_MIB_LEN_FAIL() (REG32(ADR_MIB_LEN_FAIL)) = (0x00000000)
+#define DEF_TRAP_HW_ID() (REG32(ADR_TRAP_HW_ID)) = (0x00000000)
+#define DEF_ID_IN_USE() (REG32(ADR_ID_IN_USE)) = (0x00000000)
+#define DEF_MRX_ERR() (REG32(ADR_MRX_ERR)) = (0x00000000)
+#define DEF_GROUP_WSID() (REG32(ADR_GROUP_WSID)) = (0x0000000e)
+#define DEF_HDR_ADDR_SEL() (REG32(ADR_HDR_ADDR_SEL)) = (0x00003e79)
+#define DEF_FRAME_TYPE_CNTR_SET() (REG32(ADR_FRAME_TYPE_CNTR_SET)) = (0x00000000)
+#define DEF_AMPDU_SCOREBOAD_SIZE() (REG32(ADR_AMPDU_SCOREBOAD_SIZE)) = (0x00000040)
+#define DEF_CHANNEL() (REG32(ADR_CHANNEL)) = (0x00000006)
+#define DEF_HIGH_PRIORITY_FRM_HW_ID() (REG32(ADR_HIGH_PRIORITY_FRM_HW_ID)) = (0x00000000)
+#define DEF_DUAL_IDX_EXTEND() (REG32(ADR_DUAL_IDX_EXTEND)) = (0x00000000)
+#define DEF_MRX_FLT_EN9() (REG32(ADR_MRX_FLT_EN9)) = (0x00000808)
+#define DEF_MRX_FLT_EN10() (REG32(ADR_MRX_FLT_EN10)) = (0x00000838)
+#define DEF_PHY_INFO() (REG32(ADR_PHY_INFO)) = (0x00000000)
+#define DEF_AMPDU_SIG() (REG32(ADR_AMPDU_SIG)) = (0x0000004e)
+#define DEF_MIB_AMPDU() (REG32(ADR_MIB_AMPDU)) = (0x00000000)
+#define DEF_LEN_FLT() (REG32(ADR_LEN_FLT)) = (0x00000000)
+#define DEF_MIB_DELIMITER() (REG32(ADR_MIB_DELIMITER)) = (0x00000000)
+#define DEF_MTX_INT_STS() (REG32(ADR_MTX_INT_STS)) = (0x00000000)
+#define DEF_MTX_INT_EN() (REG32(ADR_MTX_INT_EN)) = (0x00000000)
+#define DEF_MTX_MISC_EN() (REG32(ADR_MTX_MISC_EN)) = (0x00004022)
+#define DEF_MTX_TX_REPORT_OPTION() (REG32(ADR_MTX_TX_REPORT_OPTION)) = (0x00000095)
+#define DEF_MTX_STATUS0() (REG32(ADR_MTX_STATUS0)) = (0x00000000)
+#define DEF_MTX_STATUS4() (REG32(ADR_MTX_STATUS4)) = (0x00000000)
+#define DEF_MTX_HALT_OPTION() (REG32(ADR_MTX_HALT_OPTION)) = (0x00000000)
+#define DEF_MTX_PHYTX_DBG1() (REG32(ADR_MTX_PHYTX_DBG1)) = (0x00000000)
+#define DEF_MTX_MIB_WSID0() (REG32(ADR_MTX_MIB_WSID0)) = (0x00000000)
+#define DEF_MTX_MIB_WSID1() (REG32(ADR_MTX_MIB_WSID1)) = (0x00000000)
+#define DEF_MTX_MIB_WSID2() (REG32(ADR_MTX_MIB_WSID2)) = (0x00000000)
+#define DEF_MTX_MIB_WSID3() (REG32(ADR_MTX_MIB_WSID3)) = (0x00000000)
+#define DEF_MTX_MIB_WSID4() (REG32(ADR_MTX_MIB_WSID4)) = (0x00000000)
+#define DEF_MTX_MIB_WSID5() (REG32(ADR_MTX_MIB_WSID5)) = (0x00000000)
+#define DEF_MTX_MIB_WSID6() (REG32(ADR_MTX_MIB_WSID6)) = (0x00000000)
+#define DEF_MTX_MIB_WSID7() (REG32(ADR_MTX_MIB_WSID7)) = (0x00000000)
+#define DEF_STAT_CONF0() (REG32(ADR_STAT_CONF0)) = (0x00000001)
+#define DEF_STAT_CONF1() (REG32(ADR_STAT_CONF1)) = (0x00000000)
+#define DEF_MTX_PEER_PS_LOCK() (REG32(ADR_MTX_PEER_PS_LOCK)) = (0x00000200)
+#define DEF_MTX_PEER_LOCK_STATUS() (REG32(ADR_MTX_PEER_LOCK_STATUS)) = (0x00000000)
+#define DEF_MTX_RATERPT() (REG32(ADR_MTX_RATERPT)) = (0x00000070)
+#define DEF_MTX_DBGOPT_FORCE_RATE() (REG32(ADR_MTX_DBGOPT_FORCE_RATE)) = (0x000194c0)
+#define DEF_MTX_DBGOPT_FORCE_RATE_ENABLE() (REG32(ADR_MTX_DBGOPT_FORCE_RATE_ENABLE)) = (0x00000000)
+#define DEF_MTX_DBG_PHYTXIPTIMEOUT() (REG32(ADR_MTX_DBG_PHYTXIPTIMEOUT)) = (0x00000000)
+#define DEF_MTX_DBG_MORE() (REG32(ADR_MTX_DBG_MORE)) = (0x00000000)
+#define DEF_MTX_DBG_ROIFSAIR1() (REG32(ADR_MTX_DBG_ROIFSAIR1)) = (0x00000000)
+#define DEF_MTX_DBG_ROIFSAIR2() (REG32(ADR_MTX_DBG_ROIFSAIR2)) = (0x00000000)
+#define DEF_MTX_BCN_PKT_SET0() (REG32(ADR_MTX_BCN_PKT_SET0)) = (0x00000064)
+#define DEF_MTX_BCN_PKT_SET1() (REG32(ADR_MTX_BCN_PKT_SET1)) = (0x00000064)
+#define DEF_MTX_BCN_DTIM_SET0() (REG32(ADR_MTX_BCN_DTIM_SET0)) = (0x00000016)
+#define DEF_MTX_BCN_DTIM_SET1() (REG32(ADR_MTX_BCN_DTIM_SET1)) = (0x00000016)
+#define DEF_MTX_BCN_DTIM_CONFG() (REG32(ADR_MTX_BCN_DTIM_CONFG)) = (0x00000000)
+#define DEF_MTX_BCN_DTIM_INT_W1CLR() (REG32(ADR_MTX_BCN_DTIM_INT_W1CLR)) = (0x00000000)
+#define DEF_MTX_BCN_INT_STS() (REG32(ADR_MTX_BCN_INT_STS)) = (0x00000000)
+#define DEF_MTX_BCN_EN_INT() (REG32(ADR_MTX_BCN_EN_INT)) = (0x00000000)
+#define DEF_MTX_BCN_EN_MISC() (REG32(ADR_MTX_BCN_EN_MISC)) = (0x0000000a)
+#define DEF_MTX_BCN_MISC() (REG32(ADR_MTX_BCN_MISC)) = (0x00000000)
+#define DEF_MTX_BCN_PRD() (REG32(ADR_MTX_BCN_PRD)) = (0x00000064)
+#define DEF_MTX_BCN_TSF_L() (REG32(ADR_MTX_BCN_TSF_L)) = (0x00000000)
+#define DEF_MTX_BCN_TSF_U() (REG32(ADR_MTX_BCN_TSF_U)) = (0x00000000)
+#define DEF_MTX_TIME_TOUT() (REG32(ADR_MTX_TIME_TOUT)) = (0x00052c2c)
+#define DEF_MTX_TIME_IFS() (REG32(ADR_MTX_TIME_IFS)) = (0x000a0962)
+#define DEF_MTX_TIME_FINETUNE() (REG32(ADR_MTX_TIME_FINETUNE)) = (0x060d0000)
+#define DEF_MTX_STATUS() (REG32(ADR_MTX_STATUS)) = (0x00000000)
+#define DEF_MTX_PHYRXIFS_DBG() (REG32(ADR_MTX_PHYRXIFS_DBG)) = (0x00000000)
+#define DEF_MTX_DBG_IFSAIRRO0() (REG32(ADR_MTX_DBG_IFSAIRRO0)) = (0x00000000)
+#define DEF_MTX_DBG_IFSAIRRO1() (REG32(ADR_MTX_DBG_IFSAIRRO1)) = (0x00000000)
+#define DEF_MTX_DBG_IFSAIRRO2() (REG32(ADR_MTX_DBG_IFSAIRRO2)) = (0x00000000)
+#define DEF_MTX_DBG_IFSAIRRO3() (REG32(ADR_MTX_DBG_IFSAIRRO3)) = (0x00000000)
+#define DEF_MTX_NAV() (REG32(ADR_MTX_NAV)) = (0x00000000)
+#define DEF_MTX_DBG_RO_BASE1() (REG32(ADR_MTX_DBG_RO_BASE1)) = (0x00000000)
+#define DEF_MTX_DBG_RO_BASE2() (REG32(ADR_MTX_DBG_RO_BASE2)) = (0x00000000)
+#define DEF_MTX_DBG_RO_BASE3() (REG32(ADR_MTX_DBG_RO_BASE3)) = (0x00000000)
+#define DEF_TXQ0_MTX_Q_MISC_EN() (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (0x00000000)
+#define DEF_TXQ0_MTX_Q_AIFSN() (REG32(ADR_TXQ0_MTX_Q_AIFSN)) = (0x00003202)
+#define DEF_TXQ0_MTX_Q_BKF_CNT_DBG() (REG32(ADR_TXQ0_MTX_Q_BKF_CNT_DBG)) = (0x00000000)
+#define DEF_TXQ0_MTX_Q_HWDBG() (REG32(ADR_TXQ0_MTX_Q_HWDBG)) = (0x00000000)
+#define DEF_TXQ0_MTX_Q_HWDBG2() (REG32(ADR_TXQ0_MTX_Q_HWDBG2)) = (0x00000000)
+#define DEF_TXQ1_MTX_Q_MISC_EN() (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (0x00000000)
+#define DEF_TXQ1_MTX_Q_AIFSN() (REG32(ADR_TXQ1_MTX_Q_AIFSN)) = (0x00003202)
+#define DEF_TXQ1_MTX_Q_BKF_CNT_DBG() (REG32(ADR_TXQ1_MTX_Q_BKF_CNT_DBG)) = (0x00000000)
+#define DEF_TXQ1_MTX_Q_HWDBG() (REG32(ADR_TXQ1_MTX_Q_HWDBG)) = (0x00000000)
+#define DEF_TXQ1_MTX_Q_HWDBG2() (REG32(ADR_TXQ1_MTX_Q_HWDBG2)) = (0x00000000)
+#define DEF_TXQ2_MTX_Q_MISC_EN() (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (0x00000000)
+#define DEF_TXQ2_MTX_Q_AIFSN() (REG32(ADR_TXQ2_MTX_Q_AIFSN)) = (0x00003202)
+#define DEF_TXQ2_MTX_Q_BKF_CNT_DBG() (REG32(ADR_TXQ2_MTX_Q_BKF_CNT_DBG)) = (0x00000000)
+#define DEF_TXQ2_MTX_Q_HWDBG() (REG32(ADR_TXQ2_MTX_Q_HWDBG)) = (0x00000000)
+#define DEF_TXQ2_MTX_Q_HWDBG2() (REG32(ADR_TXQ2_MTX_Q_HWDBG2)) = (0x00000000)
+#define DEF_TXQ3_MTX_Q_MISC_EN() (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (0x00000000)
+#define DEF_TXQ3_MTX_Q_AIFSN() (REG32(ADR_TXQ3_MTX_Q_AIFSN)) = (0x00003202)
+#define DEF_TXQ3_MTX_Q_BKF_CNT_DBG() (REG32(ADR_TXQ3_MTX_Q_BKF_CNT_DBG)) = (0x00000000)
+#define DEF_TXQ3_MTX_Q_HWDBG() (REG32(ADR_TXQ3_MTX_Q_HWDBG)) = (0x00000000)
+#define DEF_TXQ3_MTX_Q_HWDBG2() (REG32(ADR_TXQ3_MTX_Q_HWDBG2)) = (0x00000000)
+#define DEF_TXQ4_MTX_Q_MISC_EN() (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (0x00000000)
+#define DEF_TXQ4_MTX_Q_AIFSN() (REG32(ADR_TXQ4_MTX_Q_AIFSN)) = (0x00003202)
+#define DEF_TXQ4_MTX_Q_BKF_CNT_DBG() (REG32(ADR_TXQ4_MTX_Q_BKF_CNT_DBG)) = (0x00000000)
+#define DEF_TXQ4_MTX_Q_HWDBG() (REG32(ADR_TXQ4_MTX_Q_HWDBG)) = (0x00000000)
+#define DEF_TXQ4_MTX_Q_HWDBG2() (REG32(ADR_TXQ4_MTX_Q_HWDBG2)) = (0x00000000)
+#define DEF_TXQ5_MTX_Q_MISC_EN() (REG32(ADR_TXQ5_MTX_Q_MISC_EN)) = (0x00000000)
+#define DEF_TXQ5_MTX_Q_AIFSN() (REG32(ADR_TXQ5_MTX_Q_AIFSN)) = (0x00003202)
+#define DEF_TXQ5_MTX_Q_BKF_CNT_DBG() (REG32(ADR_TXQ5_MTX_Q_BKF_CNT_DBG)) = (0x00000000)
+#define DEF_TXQ5_MTX_Q_HWDBG() (REG32(ADR_TXQ5_MTX_Q_HWDBG)) = (0x00000000)
+#define DEF_TXQ5_MTX_Q_HWDBG2() (REG32(ADR_TXQ5_MTX_Q_HWDBG2)) = (0x00000000)
+#define DEF_MTX_RESPFRM_RATE_TABLE_EXCEPTION() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_EXCEPTION)) = (0x00000000)
+#define DEF_MTX_RESPFRM_RATE_TABLE_00() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_00)) = (0x00000000)
+#define DEF_MTX_RESPFRM_RATE_TABLE_01() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_01)) = (0x00000001)
+#define DEF_MTX_RESPFRM_RATE_TABLE_02() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_02)) = (0x00000001)
+#define DEF_MTX_RESPFRM_RATE_TABLE_03() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_03)) = (0x00000001)
+#define DEF_MTX_RESPFRM_RATE_TABLE_11() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_11)) = (0x00000011)
+#define DEF_MTX_RESPFRM_RATE_TABLE_12() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_12)) = (0x00000011)
+#define DEF_MTX_RESPFRM_RATE_TABLE_13() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_13)) = (0x00000011)
+#define DEF_MTX_RESPFRM_RATE_TABLE_90_B0() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_90_B0)) = (0x00009090)
+#define DEF_MTX_RESPFRM_RATE_TABLE_91_B1() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_91_B1)) = (0x00009090)
+#define DEF_MTX_RESPFRM_RATE_TABLE_92_B2() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_92_B2)) = (0x00009292)
+#define DEF_MTX_RESPFRM_RATE_TABLE_93_B3() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_93_B3)) = (0x00009292)
+#define DEF_MTX_RESPFRM_RATE_TABLE_94_B4() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_94_B4)) = (0x00009494)
+#define DEF_MTX_RESPFRM_RATE_TABLE_95_B5() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_95_B5)) = (0x00009494)
+#define DEF_MTX_RESPFRM_RATE_TABLE_96_B6() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_96_B6)) = (0x00009494)
+#define DEF_MTX_RESPFRM_RATE_TABLE_97_B7() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_97_B7)) = (0x00009494)
+#define DEF_MTX_RESPFRM_RATE_TABLE_C0_E0() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_C0_E0)) = (0x00009090)
+#define DEF_MTX_RESPFRM_RATE_TABLE_C1_E1() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_C1_E1)) = (0x00009292)
+#define DEF_MTX_RESPFRM_RATE_TABLE_C2_E2() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_C2_E2)) = (0x00009292)
+#define DEF_MTX_RESPFRM_RATE_TABLE_C3_E3() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_C3_E3)) = (0x00009494)
+#define DEF_MTX_RESPFRM_RATE_TABLE_C4_E4() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_C4_E4)) = (0x00009494)
+#define DEF_MTX_RESPFRM_RATE_TABLE_C5_E5() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_C5_E5)) = (0x00009494)
+#define DEF_MTX_RESPFRM_RATE_TABLE_C6_E6() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_C6_E6)) = (0x00009494)
+#define DEF_MTX_RESPFRM_RATE_TABLE_C7_E7() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_C7_E7)) = (0x00009494)
+#define DEF_MTX_RESPFRM_RATE_TABLE_D0_F0() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_D0_F0)) = (0x00009090)
+#define DEF_MTX_RESPFRM_RATE_TABLE_D1_F1() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_D1_F1)) = (0x00009292)
+#define DEF_MTX_RESPFRM_RATE_TABLE_D2_F2() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_D2_F2)) = (0x00009292)
+#define DEF_MTX_RESPFRM_RATE_TABLE_D3_F3() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_D3_F3)) = (0x00009494)
+#define DEF_MTX_RESPFRM_RATE_TABLE_D4_F4() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_D4_F4)) = (0x00009494)
+#define DEF_MTX_RESPFRM_RATE_TABLE_D5_F5() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_D5_F5)) = (0x00009494)
+#define DEF_MTX_RESPFRM_RATE_TABLE_D6_F6() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_D6_F6)) = (0x00009494)
+#define DEF_MTX_RESPFRM_RATE_TABLE_D7_F7() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_D7_F7)) = (0x00009494)
+#define DEF_MTX_RESPFRM_RATE_TABLE_D8_F8() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_D8_F8)) = (0x00009090)
+#define DEF_MTX_RESPFRM_RATE_TABLE_D9_F9() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_D9_F9)) = (0x00009292)
+#define DEF_MTX_RESPFRM_RATE_TABLE_DA_FA() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_DA_FA)) = (0x00009292)
+#define DEF_MTX_RESPFRM_RATE_TABLE_DB_FB() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_DB_FB)) = (0x00009494)
+#define DEF_MTX_RESPFRM_RATE_TABLE_DC_FC() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_DC_FC)) = (0x00009494)
+#define DEF_MTX_RESPFRM_RATE_TABLE_DD_FD() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_DD_FD)) = (0x00009494)
+#define DEF_MTX_RESPFRM_RATE_TABLE_DE_FE() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_DE_FE)) = (0x00009494)
+#define DEF_MTX_RESPFRM_RATE_TABLE_DF_FF() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_DF_FF)) = (0x00009494)
+#define DEF_MTX_RESPFRM_INFO_TABLE_EXCEPTION() (REG32(ADR_MTX_RESPFRM_INFO_TABLE_EXCEPTION)) = (0x0013a8f2)
+#define DEF_MTX_RESPFRM_INFO_00() (REG32(ADR_MTX_RESPFRM_INFO_00)) = (0x0013a8f2)
+#define DEF_MTX_RESPFRM_INFO_01() (REG32(ADR_MTX_RESPFRM_INFO_01)) = (0x001028f2)
+#define DEF_MTX_RESPFRM_INFO_02() (REG32(ADR_MTX_RESPFRM_INFO_02)) = (0x000df8f2)
+#define DEF_MTX_RESPFRM_INFO_03() (REG32(ADR_MTX_RESPFRM_INFO_03)) = (0x000d58f2)
+#define DEF_MTX_RESPFRM_INFO_11() (REG32(ADR_MTX_RESPFRM_INFO_11)) = (0x000a28f2)
+#define DEF_MTX_RESPFRM_INFO_12() (REG32(ADR_MTX_RESPFRM_INFO_12)) = (0x0007f8f2)
+#define DEF_MTX_RESPFRM_INFO_13() (REG32(ADR_MTX_RESPFRM_INFO_13)) = (0x000758f2)
+#define DEF_MTX_RESPFRM_INFO_90_B0() (REG32(ADR_MTX_RESPFRM_INFO_90_B0)) = (0x0003c8f2)
+#define DEF_MTX_RESPFRM_INFO_91_B1() (REG32(ADR_MTX_RESPFRM_INFO_91_B1)) = (0x000348f2)
+#define DEF_MTX_RESPFRM_INFO_92_B2() (REG32(ADR_MTX_RESPFRM_INFO_92_B2)) = (0x000308f2)
+#define DEF_MTX_RESPFRM_INFO_93_B3() (REG32(ADR_MTX_RESPFRM_INFO_93_B3)) = (0x0002c8f2)
+#define DEF_MTX_RESPFRM_INFO_94_B4() (REG32(ADR_MTX_RESPFRM_INFO_94_B4)) = (0x0002c8f2)
+#define DEF_MTX_RESPFRM_INFO_95_B5() (REG32(ADR_MTX_RESPFRM_INFO_95_B5)) = (0x000288f2)
+#define DEF_MTX_RESPFRM_INFO_96_B6() (REG32(ADR_MTX_RESPFRM_INFO_96_B6)) = (0x000288f2)
+#define DEF_MTX_RESPFRM_INFO_97_B7() (REG32(ADR_MTX_RESPFRM_INFO_97_B7)) = (0x000288f2)
+#define DEF_MTX_RESPFRM_INFO_C0() (REG32(ADR_MTX_RESPFRM_INFO_C0)) = (0x0004c8f2)
+#define DEF_MTX_RESPFRM_INFO_C1() (REG32(ADR_MTX_RESPFRM_INFO_C1)) = (0x000406a3)
+#define DEF_MTX_RESPFRM_INFO_C2() (REG32(ADR_MTX_RESPFRM_INFO_C2)) = (0x0003c5dd)
+#define DEF_MTX_RESPFRM_INFO_C3() (REG32(ADR_MTX_RESPFRM_INFO_C3)) = (0x0003c5da)
+#define DEF_MTX_RESPFRM_INFO_C4() (REG32(ADR_MTX_RESPFRM_INFO_C4)) = (0x00038517)
+#define DEF_MTX_RESPFRM_INFO_C5() (REG32(ADR_MTX_RESPFRM_INFO_C5)) = (0x00038517)
+#define DEF_MTX_RESPFRM_INFO_C6() (REG32(ADR_MTX_RESPFRM_INFO_C6)) = (0x00038517)
+#define DEF_MTX_RESPFRM_INFO_C7() (REG32(ADR_MTX_RESPFRM_INFO_C7)) = (0x00038517)
+#define DEF_MTX_RESPFRM_INFO_D0() (REG32(ADR_MTX_RESPFRM_INFO_D0)) = (0x0004c8ef)
+#define DEF_MTX_RESPFRM_INFO_D1() (REG32(ADR_MTX_RESPFRM_INFO_D1)) = (0x000406a3)
+#define DEF_MTX_RESPFRM_INFO_D2() (REG32(ADR_MTX_RESPFRM_INFO_D2)) = (0x0003c5dd)
+#define DEF_MTX_RESPFRM_INFO_D3() (REG32(ADR_MTX_RESPFRM_INFO_D3)) = (0x0003c5da)
+#define DEF_MTX_RESPFRM_INFO_D4() (REG32(ADR_MTX_RESPFRM_INFO_D4)) = (0x00038517)
+#define DEF_MTX_RESPFRM_INFO_D5() (REG32(ADR_MTX_RESPFRM_INFO_D5)) = (0x00038517)
+#define DEF_MTX_RESPFRM_INFO_D6() (REG32(ADR_MTX_RESPFRM_INFO_D6)) = (0x00038517)
+#define DEF_MTX_RESPFRM_INFO_D7() (REG32(ADR_MTX_RESPFRM_INFO_D7)) = (0x00038517)
+#define DEF_MTX_RESPFRM_INFO_D8() (REG32(ADR_MTX_RESPFRM_INFO_D8)) = (0x000408f2)
+#define DEF_MTX_RESPFRM_INFO_D9() (REG32(ADR_MTX_RESPFRM_INFO_D9)) = (0x000348f2)
+#define DEF_MTX_RESPFRM_INFO_DA() (REG32(ADR_MTX_RESPFRM_INFO_DA)) = (0x000308f2)
+#define DEF_MTX_RESPFRM_INFO_DB() (REG32(ADR_MTX_RESPFRM_INFO_DB)) = (0x000308f2)
+#define DEF_MTX_RESPFRM_INFO_DC() (REG32(ADR_MTX_RESPFRM_INFO_DC)) = (0x0002c8f2)
+#define DEF_MTX_RESPFRM_INFO_DD() (REG32(ADR_MTX_RESPFRM_INFO_DD)) = (0x0002c8f2)
+#define DEF_MTX_RESPFRM_INFO_DE() (REG32(ADR_MTX_RESPFRM_INFO_DE)) = (0x0002c8f2)
+#define DEF_MTX_RESPFRM_INFO_DF() (REG32(ADR_MTX_RESPFRM_INFO_DF)) = (0x0002c8f2)
+#define DEF_WSID0() (REG32(ADR_WSID0)) = (0x00000000)
+#define DEF_PEER_MAC0_0() (REG32(ADR_PEER_MAC0_0)) = (0x00000000)
+#define DEF_PEER_MAC0_1() (REG32(ADR_PEER_MAC0_1)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_0() (REG32(ADR_TX_ACK_POLICY_0_0)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_0() (REG32(ADR_TX_SEQ_CTRL_0_0)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_1() (REG32(ADR_TX_ACK_POLICY_0_1)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_1() (REG32(ADR_TX_SEQ_CTRL_0_1)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_2() (REG32(ADR_TX_ACK_POLICY_0_2)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_2() (REG32(ADR_TX_SEQ_CTRL_0_2)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_3() (REG32(ADR_TX_ACK_POLICY_0_3)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_3() (REG32(ADR_TX_SEQ_CTRL_0_3)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_4() (REG32(ADR_TX_ACK_POLICY_0_4)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_4() (REG32(ADR_TX_SEQ_CTRL_0_4)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_5() (REG32(ADR_TX_ACK_POLICY_0_5)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_5() (REG32(ADR_TX_SEQ_CTRL_0_5)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_6() (REG32(ADR_TX_ACK_POLICY_0_6)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_6() (REG32(ADR_TX_SEQ_CTRL_0_6)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_7() (REG32(ADR_TX_ACK_POLICY_0_7)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_7() (REG32(ADR_TX_SEQ_CTRL_0_7)) = (0x00000000)
+#define DEF_WSID1() (REG32(ADR_WSID1)) = (0x00000000)
+#define DEF_PEER_MAC1_0() (REG32(ADR_PEER_MAC1_0)) = (0x00000000)
+#define DEF_PEER_MAC1_1() (REG32(ADR_PEER_MAC1_1)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_0() (REG32(ADR_TX_ACK_POLICY_1_0)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_0() (REG32(ADR_TX_SEQ_CTRL_1_0)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_1() (REG32(ADR_TX_ACK_POLICY_1_1)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_1() (REG32(ADR_TX_SEQ_CTRL_1_1)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_2() (REG32(ADR_TX_ACK_POLICY_1_2)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_2() (REG32(ADR_TX_SEQ_CTRL_1_2)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_3() (REG32(ADR_TX_ACK_POLICY_1_3)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_3() (REG32(ADR_TX_SEQ_CTRL_1_3)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_4() (REG32(ADR_TX_ACK_POLICY_1_4)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_4() (REG32(ADR_TX_SEQ_CTRL_1_4)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_5() (REG32(ADR_TX_ACK_POLICY_1_5)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_5() (REG32(ADR_TX_SEQ_CTRL_1_5)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_6() (REG32(ADR_TX_ACK_POLICY_1_6)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_6() (REG32(ADR_TX_SEQ_CTRL_1_6)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_7() (REG32(ADR_TX_ACK_POLICY_1_7)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_7() (REG32(ADR_TX_SEQ_CTRL_1_7)) = (0x00000000)
+#define DEF_PACKET_ID_ALLOCATION_PRIORITY() (REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) = (0x00000000)
+#define DEF_MAC_MODE() (REG32(ADR_MAC_MODE)) = (0x00000000)
+#define DEF_ALL_SOFTWARE_RESET() (REG32(ADR_ALL_SOFTWARE_RESET)) = (0x00000000)
+#define DEF_ENG_SOFTWARE_RESET() (REG32(ADR_ENG_SOFTWARE_RESET)) = (0x00000000)
+#define DEF_CSR_SOFTWARE_RESET() (REG32(ADR_CSR_SOFTWARE_RESET)) = (0x00000000)
+#define DEF_MAC_CLOCK_ENABLE() (REG32(ADR_MAC_CLOCK_ENABLE)) = (0x00003efb)
+#define DEF_MAC_ENGINE_CLOCK_ENABLE() (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (0x0000f07b)
+#define DEF_MAC_CSR_CLOCK_ENABLE() (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (0x0000ec02)
+#define DEF_GLBLE_SET() (REG32(ADR_GLBLE_SET)) = (0x000e5000)
+#define DEF_REASON_TRAP0() (REG32(ADR_REASON_TRAP0)) = (0x00000000)
+#define DEF_REASON_TRAP1() (REG32(ADR_REASON_TRAP1)) = (0x00000000)
+#define DEF_BSSID_0() (REG32(ADR_BSSID_0)) = (0x00000000)
+#define DEF_BSSID_1() (REG32(ADR_BSSID_1)) = (0x00000000)
+#define DEF_STA_MAC_0() (REG32(ADR_STA_MAC_0)) = (0x00000000)
+#define DEF_STA_MAC_1() (REG32(ADR_STA_MAC_1)) = (0x00000000)
+#define DEF_SCRT_SET() (REG32(ADR_SCRT_SET)) = (0x00000000)
+#define DEF_SCRT_STATE() (REG32(ADR_SCRT_STATE)) = (0x00000000)
+#define DEF_BSSID1_0() (REG32(ADR_BSSID1_0)) = (0x00000000)
+#define DEF_BSSID1_1() (REG32(ADR_BSSID1_1)) = (0x00000000)
+#define DEF_STA_MAC1_0() (REG32(ADR_STA_MAC1_0)) = (0x00000000)
+#define DEF_STA_MAC1_1() (REG32(ADR_STA_MAC1_1)) = (0x00000000)
+#define DEF_OP_MODE1() (REG32(ADR_OP_MODE1)) = (0x00000000)
+#define DEF_BTCX0() (REG32(ADR_BTCX0)) = (0x00000006)
+#define DEF_BTCX1() (REG32(ADR_BTCX1)) = (0x00000000)
+#define DEF_SWITCH_CTL() (REG32(ADR_SWITCH_CTL)) = (0x00000000)
+#define DEF_RANDOM_CTL() (REG32(ADR_RANDOM_CTL)) = (0x00000000)
+#define DEF_BTCX_MISC_CTL() (REG32(ADR_BTCX_MISC_CTL)) = (0x0000005f)
+#define DEF_MIB_EN() (REG32(ADR_MIB_EN)) = (0x00000000)
+#define DEF_MTX_WSID0_SUCC() (REG32(ADR_MTX_WSID0_SUCC)) = (0x00000000)
+#define DEF_MTX_WSID0_FRM() (REG32(ADR_MTX_WSID0_FRM)) = (0x00000000)
+#define DEF_MTX_WSID0_RETRY() (REG32(ADR_MTX_WSID0_RETRY)) = (0x00000000)
+#define DEF_MTX_WSID0_TOTAL() (REG32(ADR_MTX_WSID0_TOTAL)) = (0x00000000)
+#define DEF_MTX_GROUP() (REG32(ADR_MTX_GROUP)) = (0x00000000)
+#define DEF_MTX_FAIL() (REG32(ADR_MTX_FAIL)) = (0x00000000)
+#define DEF_MTX_RETRY() (REG32(ADR_MTX_RETRY)) = (0x00000000)
+#define DEF_MTX_MULTI_RETRY() (REG32(ADR_MTX_MULTI_RETRY)) = (0x00000000)
+#define DEF_MTX_RTS_SUCCESS() (REG32(ADR_MTX_RTS_SUCCESS)) = (0x00000000)
+#define DEF_MTX_RTS_FAIL() (REG32(ADR_MTX_RTS_FAIL)) = (0x00000000)
+#define DEF_MTX_ACK_FAIL() (REG32(ADR_MTX_ACK_FAIL)) = (0x00000000)
+#define DEF_MTX_FRM() (REG32(ADR_MTX_FRM)) = (0x00000000)
+#define DEF_MTX_ACK_TX() (REG32(ADR_MTX_ACK_TX)) = (0x00000000)
+#define DEF_MTX_CTS_TX() (REG32(ADR_MTX_CTS_TX)) = (0x00000000)
+#define DEF_MRX_DUP_FRM() (REG32(ADR_MRX_DUP_FRM)) = (0x00000000)
+#define DEF_MRX_FRG_FRM() (REG32(ADR_MRX_FRG_FRM)) = (0x00000000)
+#define DEF_MRX_GROUP_FRM() (REG32(ADR_MRX_GROUP_FRM)) = (0x00000000)
+#define DEF_MRX_FCS_ERR() (REG32(ADR_MRX_FCS_ERR)) = (0x00000000)
+#define DEF_MRX_FCS_SUCC() (REG32(ADR_MRX_FCS_SUCC)) = (0x00000000)
+#define DEF_MRX_MISS() (REG32(ADR_MRX_MISS)) = (0x00000000)
+#define DEF_MRX_ALC_FAIL() (REG32(ADR_MRX_ALC_FAIL)) = (0x00000000)
+#define DEF_MRX_DAT_NTF() (REG32(ADR_MRX_DAT_NTF)) = (0x00000000)
+#define DEF_MRX_RTS_NTF() (REG32(ADR_MRX_RTS_NTF)) = (0x00000000)
+#define DEF_MRX_CTS_NTF() (REG32(ADR_MRX_CTS_NTF)) = (0x00000000)
+#define DEF_MRX_ACK_NTF() (REG32(ADR_MRX_ACK_NTF)) = (0x00000000)
+#define DEF_MRX_BA_NTF() (REG32(ADR_MRX_BA_NTF)) = (0x00000000)
+#define DEF_MRX_DATA_NTF() (REG32(ADR_MRX_DATA_NTF)) = (0x00000000)
+#define DEF_MRX_MNG_NTF() (REG32(ADR_MRX_MNG_NTF)) = (0x00000000)
+#define DEF_MRX_DAT_CRC_NTF() (REG32(ADR_MRX_DAT_CRC_NTF)) = (0x00000000)
+#define DEF_MRX_BAR_NTF() (REG32(ADR_MRX_BAR_NTF)) = (0x00000000)
+#define DEF_MRX_MB_MISS() (REG32(ADR_MRX_MB_MISS)) = (0x00000000)
+#define DEF_MRX_NIDLE_MISS() (REG32(ADR_MRX_NIDLE_MISS)) = (0x00000000)
+#define DEF_MRX_CSR_NTF() (REG32(ADR_MRX_CSR_NTF)) = (0x00000000)
+#define DEF_DBG_Q0_FRM_SUCCESS() (REG32(ADR_DBG_Q0_FRM_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q0_FRM_FAIL() (REG32(ADR_DBG_Q0_FRM_FAIL)) = (0x00000000)
+#define DEF_DBG_Q0_ACK_SUCCESS() (REG32(ADR_DBG_Q0_ACK_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q0_ACK_FAIL() (REG32(ADR_DBG_Q0_ACK_FAIL)) = (0x00000000)
+#define DEF_DBG_Q1_FRM_SUCCESS() (REG32(ADR_DBG_Q1_FRM_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q1_FRM_FAIL() (REG32(ADR_DBG_Q1_FRM_FAIL)) = (0x00000000)
+#define DEF_DBG_Q1_ACK_SUCCESS() (REG32(ADR_DBG_Q1_ACK_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q1_ACK_FAIL() (REG32(ADR_DBG_Q1_ACK_FAIL)) = (0x00000000)
+#define DEF_DBG_Q2_FRM_SUCCESS() (REG32(ADR_DBG_Q2_FRM_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q2_FRM_FAIL() (REG32(ADR_DBG_Q2_FRM_FAIL)) = (0x00000000)
+#define DEF_DBG_Q2_ACK_SUCCESS() (REG32(ADR_DBG_Q2_ACK_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q2_ACK_FAIL() (REG32(ADR_DBG_Q2_ACK_FAIL)) = (0x00000000)
+#define DEF_DBG_Q3_FRM_SUCCESS() (REG32(ADR_DBG_Q3_FRM_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q3_FRM_FAIL() (REG32(ADR_DBG_Q3_FRM_FAIL)) = (0x00000000)
+#define DEF_DBG_Q3_ACK_SUCCESS() (REG32(ADR_DBG_Q3_ACK_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q3_ACK_FAIL() (REG32(ADR_DBG_Q3_ACK_FAIL)) = (0x00000000)
+#define DEF_MIB_SCRT_TKIP0() (REG32(ADR_MIB_SCRT_TKIP0)) = (0x00000000)
+#define DEF_MIB_SCRT_TKIP1() (REG32(ADR_MIB_SCRT_TKIP1)) = (0x00000000)
+#define DEF_MIB_SCRT_TKIP2() (REG32(ADR_MIB_SCRT_TKIP2)) = (0x00000000)
+#define DEF_MIB_SCRT_CCMP0() (REG32(ADR_MIB_SCRT_CCMP0)) = (0x00000000)
+#define DEF_MIB_SCRT_CCMP1() (REG32(ADR_MIB_SCRT_CCMP1)) = (0x00000000)
+#define DEF_DBG_LEN_CRC_FAIL() (REG32(ADR_DBG_LEN_CRC_FAIL)) = (0x00000000)
+#define DEF_DBG_LEN_ALC_FAIL() (REG32(ADR_DBG_LEN_ALC_FAIL)) = (0x00000000)
+#define DEF_DBG_AMPDU_PASS() (REG32(ADR_DBG_AMPDU_PASS)) = (0x00000000)
+#define DEF_DBG_AMPDU_FAIL() (REG32(ADR_DBG_AMPDU_FAIL)) = (0x00000000)
+#define DEF_ID_ALC_FAIL1() (REG32(ADR_ID_ALC_FAIL1)) = (0x00000000)
+#define DEF_ID_ALC_FAIL2() (REG32(ADR_ID_ALC_FAIL2)) = (0x00000000)
+#define DEF_WSID2() (REG32(ADR_WSID2)) = (0x00000000)
+#define DEF_PEER_MAC2_0() (REG32(ADR_PEER_MAC2_0)) = (0x00000000)
+#define DEF_PEER_MAC2_1() (REG32(ADR_PEER_MAC2_1)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_2_0() (REG32(ADR_TX_ACK_POLICY_2_0)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_2_0() (REG32(ADR_TX_SEQ_CTRL_2_0)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_2_1() (REG32(ADR_TX_ACK_POLICY_2_1)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_2_1() (REG32(ADR_TX_SEQ_CTRL_2_1)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_2_2() (REG32(ADR_TX_ACK_POLICY_2_2)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_2_2() (REG32(ADR_TX_SEQ_CTRL_2_2)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_2_3() (REG32(ADR_TX_ACK_POLICY_2_3)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_2_3() (REG32(ADR_TX_SEQ_CTRL_2_3)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_2_4() (REG32(ADR_TX_ACK_POLICY_2_4)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_2_4() (REG32(ADR_TX_SEQ_CTRL_2_4)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_2_5() (REG32(ADR_TX_ACK_POLICY_2_5)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_2_5() (REG32(ADR_TX_SEQ_CTRL_2_5)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_2_6() (REG32(ADR_TX_ACK_POLICY_2_6)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_2_6() (REG32(ADR_TX_SEQ_CTRL_2_6)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_2_7() (REG32(ADR_TX_ACK_POLICY_2_7)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_2_7() (REG32(ADR_TX_SEQ_CTRL_2_7)) = (0x00000000)
+#define DEF_WSID3() (REG32(ADR_WSID3)) = (0x00000000)
+#define DEF_PEER_MAC3_0() (REG32(ADR_PEER_MAC3_0)) = (0x00000000)
+#define DEF_PEER_MAC3_1() (REG32(ADR_PEER_MAC3_1)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_3_0() (REG32(ADR_TX_ACK_POLICY_3_0)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_3_0() (REG32(ADR_TX_SEQ_CTRL_3_0)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_3_1() (REG32(ADR_TX_ACK_POLICY_3_1)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_3_1() (REG32(ADR_TX_SEQ_CTRL_3_1)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_3_2() (REG32(ADR_TX_ACK_POLICY_3_2)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_3_2() (REG32(ADR_TX_SEQ_CTRL_3_2)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_3_3() (REG32(ADR_TX_ACK_POLICY_3_3)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_3_3() (REG32(ADR_TX_SEQ_CTRL_3_3)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_3_4() (REG32(ADR_TX_ACK_POLICY_3_4)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_3_4() (REG32(ADR_TX_SEQ_CTRL_3_4)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_3_5() (REG32(ADR_TX_ACK_POLICY_3_5)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_3_5() (REG32(ADR_TX_SEQ_CTRL_3_5)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_3_6() (REG32(ADR_TX_ACK_POLICY_3_6)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_3_6() (REG32(ADR_TX_SEQ_CTRL_3_6)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_3_7() (REG32(ADR_TX_ACK_POLICY_3_7)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_3_7() (REG32(ADR_TX_SEQ_CTRL_3_7)) = (0x00000000)
+#define DEF_WSID4() (REG32(ADR_WSID4)) = (0x00000000)
+#define DEF_PEER_MAC4_0() (REG32(ADR_PEER_MAC4_0)) = (0x00000000)
+#define DEF_PEER_MAC4_1() (REG32(ADR_PEER_MAC4_1)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_4_0() (REG32(ADR_TX_ACK_POLICY_4_0)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_4_0() (REG32(ADR_TX_SEQ_CTRL_4_0)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_4_1() (REG32(ADR_TX_ACK_POLICY_4_1)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_4_1() (REG32(ADR_TX_SEQ_CTRL_4_1)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_4_2() (REG32(ADR_TX_ACK_POLICY_4_2)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_4_2() (REG32(ADR_TX_SEQ_CTRL_4_2)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_4_3() (REG32(ADR_TX_ACK_POLICY_4_3)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_4_3() (REG32(ADR_TX_SEQ_CTRL_4_3)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_4_4() (REG32(ADR_TX_ACK_POLICY_4_4)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_4_4() (REG32(ADR_TX_SEQ_CTRL_4_4)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_4_5() (REG32(ADR_TX_ACK_POLICY_4_5)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_4_5() (REG32(ADR_TX_SEQ_CTRL_4_5)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_4_6() (REG32(ADR_TX_ACK_POLICY_4_6)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_4_6() (REG32(ADR_TX_SEQ_CTRL_4_6)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_4_7() (REG32(ADR_TX_ACK_POLICY_4_7)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_4_7() (REG32(ADR_TX_SEQ_CTRL_4_7)) = (0x00000000)
+#define DEF_WSID5() (REG32(ADR_WSID5)) = (0x00000000)
+#define DEF_PEER_MAC5_0() (REG32(ADR_PEER_MAC5_0)) = (0x00000000)
+#define DEF_PEER_MAC5_1() (REG32(ADR_PEER_MAC5_1)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_5_0() (REG32(ADR_TX_ACK_POLICY_5_0)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_5_0() (REG32(ADR_TX_SEQ_CTRL_5_0)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_5_1() (REG32(ADR_TX_ACK_POLICY_5_1)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_5_1() (REG32(ADR_TX_SEQ_CTRL_5_1)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_5_2() (REG32(ADR_TX_ACK_POLICY_5_2)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_5_2() (REG32(ADR_TX_SEQ_CTRL_5_2)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_5_3() (REG32(ADR_TX_ACK_POLICY_5_3)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_5_3() (REG32(ADR_TX_SEQ_CTRL_5_3)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_5_4() (REG32(ADR_TX_ACK_POLICY_5_4)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_5_4() (REG32(ADR_TX_SEQ_CTRL_5_4)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_5_5() (REG32(ADR_TX_ACK_POLICY_5_5)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_5_5() (REG32(ADR_TX_SEQ_CTRL_5_5)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_5_6() (REG32(ADR_TX_ACK_POLICY_5_6)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_5_6() (REG32(ADR_TX_SEQ_CTRL_5_6)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_5_7() (REG32(ADR_TX_ACK_POLICY_5_7)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_5_7() (REG32(ADR_TX_SEQ_CTRL_5_7)) = (0x00000000)
+#define DEF_WSID6() (REG32(ADR_WSID6)) = (0x00000000)
+#define DEF_PEER_MAC6_0() (REG32(ADR_PEER_MAC6_0)) = (0x00000000)
+#define DEF_PEER_MAC6_1() (REG32(ADR_PEER_MAC6_1)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_6_0() (REG32(ADR_TX_ACK_POLICY_6_0)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_6_0() (REG32(ADR_TX_SEQ_CTRL_6_0)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_6_1() (REG32(ADR_TX_ACK_POLICY_6_1)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_6_1() (REG32(ADR_TX_SEQ_CTRL_6_1)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_6_2() (REG32(ADR_TX_ACK_POLICY_6_2)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_6_2() (REG32(ADR_TX_SEQ_CTRL_6_2)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_6_3() (REG32(ADR_TX_ACK_POLICY_6_3)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_6_3() (REG32(ADR_TX_SEQ_CTRL_6_3)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_6_4() (REG32(ADR_TX_ACK_POLICY_6_4)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_6_4() (REG32(ADR_TX_SEQ_CTRL_6_4)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_6_5() (REG32(ADR_TX_ACK_POLICY_6_5)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_6_5() (REG32(ADR_TX_SEQ_CTRL_6_5)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_6_6() (REG32(ADR_TX_ACK_POLICY_6_6)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_6_6() (REG32(ADR_TX_SEQ_CTRL_6_6)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_6_7() (REG32(ADR_TX_ACK_POLICY_6_7)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_6_7() (REG32(ADR_TX_SEQ_CTRL_6_7)) = (0x00000000)
+#define DEF_WSID7() (REG32(ADR_WSID7)) = (0x00000000)
+#define DEF_PEER_MAC7_0() (REG32(ADR_PEER_MAC7_0)) = (0x00000000)
+#define DEF_PEER_MAC7_1() (REG32(ADR_PEER_MAC7_1)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_7_0() (REG32(ADR_TX_ACK_POLICY_7_0)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_7_0() (REG32(ADR_TX_SEQ_CTRL_7_0)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_7_1() (REG32(ADR_TX_ACK_POLICY_7_1)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_7_1() (REG32(ADR_TX_SEQ_CTRL_7_1)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_7_2() (REG32(ADR_TX_ACK_POLICY_7_2)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_7_2() (REG32(ADR_TX_SEQ_CTRL_7_2)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_7_3() (REG32(ADR_TX_ACK_POLICY_7_3)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_7_3() (REG32(ADR_TX_SEQ_CTRL_7_3)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_7_4() (REG32(ADR_TX_ACK_POLICY_7_4)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_7_4() (REG32(ADR_TX_SEQ_CTRL_7_4)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_7_5() (REG32(ADR_TX_ACK_POLICY_7_5)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_7_5() (REG32(ADR_TX_SEQ_CTRL_7_5)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_7_6() (REG32(ADR_TX_ACK_POLICY_7_6)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_7_6() (REG32(ADR_TX_SEQ_CTRL_7_6)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_7_7() (REG32(ADR_TX_ACK_POLICY_7_7)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_7_7() (REG32(ADR_TX_SEQ_CTRL_7_7)) = (0x00000000)
+#define DEF_GEMINIA_3_WIRE_REGISTER() (REG32(ADR_GEMINIA_3_WIRE_REGISTER)) = (0x06000120)
+#define DEF_GEMINIA_MANUAL_ENABLE_REGISTER() (REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) = (0x2aaaaaaa)
+#define DEF_GEMINIA_CALIBRATION_TEST_REGISTER() (REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) = (0x0000aa9f)
+#define DEF_GEMINIA_LDO_REGISTER() (REG32(ADR_GEMINIA_LDO_REGISTER)) = (0x24824924)
+#define DEF_GEMINIA_WIFI_RX_FILTER_REGISTER() (REG32(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER)) = (0x271556db)
+#define DEF_GEMINIA_BT_RX_FILTER_REGISTER() (REG32(ADR_GEMINIA_BT_RX_FILTER_REGISTER)) = (0x26d556db)
+#define DEF_GEMINIA_RX_REGISTER() (REG32(ADR_GEMINIA_RX_REGISTER)) = (0x604aea08)
+#define DEF_GEMINIA_WBT_TX_FE_REGISTER() (REG32(ADR_GEMINIA_WBT_TX_FE_REGISTER)) = (0x00003e7e)
+#define DEF_GEMINIA_WBT_TX_PA_REGISTER() (REG32(ADR_GEMINIA_WBT_TX_PA_REGISTER)) = (0x37744497)
+#define DEF_GEMINIA_TX_REGISTER() (REG32(ADR_GEMINIA_TX_REGISTER)) = (0x2600a13f)
+#define DEF_GEMINIA_WIFI_RX_FE_HG_REGISTER() (REG32(ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER)) = (0xaf910e93)
+#define DEF_GEMINIA_WIFI_RX_FE_MG_REGISTER() (REG32(ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER)) = (0xaf910e92)
+#define DEF_GEMINIA_WIFI_RX_FE_LG_REGISTER() (REG32(ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER)) = (0xaf918001)
+#define DEF_GEMINIA_WIFI_RX_FE_ULG_REGISTER() (REG32(ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER)) = (0xaf938004)
+#define DEF_GEMINIA_BT_RX_FE_HG_REGISTER() (REG32(ADR_GEMINIA_BT_RX_FE_HG_REGISTER)) = (0x97910643)
+#define DEF_GEMINIA_BT_RX_FE_MG_REGISTER() (REG32(ADR_GEMINIA_BT_RX_FE_MG_REGISTER)) = (0x97910642)
+#define DEF_GEMINIA_BT_RX_FE_LG_REGISTER() (REG32(ADR_GEMINIA_BT_RX_FE_LG_REGISTER)) = (0x97918001)
+#define DEF_GEMINIA_BT_RX_FE_ULG_REGISTER() (REG32(ADR_GEMINIA_BT_RX_FE_ULG_REGISTER)) = (0x97938004)
+#define DEF_GEMINIA_RX_ADC_REGISTER() (REG32(ADR_GEMINIA_RX_ADC_REGISTER)) = (0x83050502)
+#define DEF_GEMINIA_WIFI_TX_DAC_REGISTER() (REG32(ADR_GEMINIA_WIFI_TX_DAC_REGISTER)) = (0x08804355)
+#define DEF_GEMINIA_BT_TX_DAC_REGISTER() (REG32(ADR_GEMINIA_BT_TX_DAC_REGISTER)) = (0x08800755)
+#define DEF_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER() (REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) = (0x802aa2aa)
+#define DEF_GEMINIA_SX_LDO_REGISTER() (REG32(ADR_GEMINIA_SX_LDO_REGISTER)) = (0x2aa0021e)
+#define DEF_GEMINIA_SYN_FRACTIONAL_AND_INTEGER_8BITS() (REG32(ADR_GEMINIA_SYN_FRACTIONAL_AND_INTEGER_8BITS)) = (0x5f800000)
+#define DEF_GEMINIA_SYN_REGISTER_INT3BIT_CH_TABLE() (REG32(ADR_GEMINIA_SYN_REGISTER_INT3BIT_CH_TABLE)) = (0x000043c0)
+#define DEF_GEMINIA_SYN_PFD_CHP_() (REG32(ADR_GEMINIA_SYN_PFD_CHP_)) = (0x01c00606)
+#define DEF_GEMINIA_SYN_LPF() (REG32(ADR_GEMINIA_SYN_LPF)) = (0x2c4293d6)
+#define DEF_GEMINIA_SYN_VCO() (REG32(ADR_GEMINIA_SYN_VCO)) = (0x002220a8)
+#define DEF_GEMINIA_SYN_VCOBF() (REG32(ADR_GEMINIA_SYN_VCOBF)) = (0x04015445)
+#define DEF_GEMINIA_SYN_DIV_SDM() (REG32(ADR_GEMINIA_SYN_DIV_SDM)) = (0x001e0077)
+#define DEF_GEMINIA_SYN_SBCAL() (REG32(ADR_GEMINIA_SYN_SBCAL)) = (0x30700400)
+#define DEF_GEMINIA_SYN_AAC() (REG32(ADR_GEMINIA_SYN_AAC)) = (0x0517cd06)
+#define DEF_GEMINIA_SYN_TTL() (REG32(ADR_GEMINIA_SYN_TTL)) = (0x00018495)
+#define DEF_GEMINIA_DPLL_TOP_REGISTER() (REG32(ADR_GEMINIA_DPLL_TOP_REGISTER)) = (0x00180f20)
+#define DEF_GEMINIA_DPLL_CKT_REGISTER() (REG32(ADR_GEMINIA_DPLL_CKT_REGISTER)) = (0x041c89ac)
+#define DEF_GEMINIA_DPLL_FB_DIVISION_REGISTERS() (REG32(ADR_GEMINIA_DPLL_FB_DIVISION_REGISTERS)) = (0x24ec2ec5)
+#define DEF_GEMINIA_WF_DCOC_IDAC_REGISTER1() (REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER1)) = (0x20202020)
+#define DEF_GEMINIA_WF_DCOC_IDAC_REGISTER2() (REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER2)) = (0x20202020)
+#define DEF_GEMINIA_WF_DCOC_IDAC_REGISTER3() (REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER3)) = (0x20202020)
+#define DEF_GEMINIA_WF_DCOC_IDAC_REGISTER4() (REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER4)) = (0x20202020)
+#define DEF_GEMINIA_WF_DCOC_IDAC_REGISTER5() (REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER5)) = (0x20202020)
+#define DEF_GEMINIA_WF_DCOC_IDAC_REGISTER6() (REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER6)) = (0x20202020)
+#define DEF_GEMINIA_WF_DCOC_IDAC_REGISTER7() (REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER7)) = (0x20202020)
+#define DEF_GEMINIA_WF_DCOC_IDAC_REGISTER8() (REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER8)) = (0x20202020)
+#define DEF_GEMINIA_WF_DCOC_IDAC_REGISTER9() (REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER9)) = (0x20202020)
+#define DEF_GEMINIA_WF_DCOC_IDAC_REGISTER10() (REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER10)) = (0x20202020)
+#define DEF_GEMINIA_WF_DCOC_IDAC_REGISTER11() (REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER11)) = (0x20202020)
+#define DEF_GEMINIA_WF_DCOC_IDAC_REGISTER12() (REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER12)) = (0x20202020)
+#define DEF_GEMINIA_WF_DCOC_IDAC_REGISTER13() (REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER13)) = (0x20202020)
+#define DEF_GEMINIA_WF_DCOC_IDAC_REGISTER14() (REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER14)) = (0x20202020)
+#define DEF_GEMINIA_WF_DCOC_IDAC_REGISTER15() (REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER15)) = (0x20202020)
+#define DEF_GEMINIA_WF_DCOC_IDAC_REGISTER16() (REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER16)) = (0x20202020)
+#define DEF_GEMINIA_WF_DCOC_IDAC_REGISTER17() (REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER17)) = (0x20202020)
+#define DEF_GEMINIA_WF_DCOC_IDAC_REGISTER18() (REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER18)) = (0x20202020)
+#define DEF_GEMINIA_WF_DCOC_IDAC_REGISTER19() (REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER19)) = (0x00002020)
+#define DEF_GEMINIA_WF_DCOC_IDAC_REGISTER20() (REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER20)) = (0x20202020)
+#define DEF_GEMINIA_WF_DCOC_IDAC_REGISTER21() (REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER21)) = (0x20202020)
+#define DEF_GEMINIA_WF_DCOC_IDAC_REGISTER22() (REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER22)) = (0x00002020)
+#define DEF_GEMINIA_BT_DCOC_IDAC_REGISTER1() (REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER1)) = (0x20202020)
+#define DEF_GEMINIA_BT_DCOC_IDAC_REGISTER2() (REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER2)) = (0x20202020)
+#define DEF_GEMINIA_BT_DCOC_IDAC_REGISTER3() (REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER3)) = (0x20202020)
+#define DEF_GEMINIA_BT_DCOC_IDAC_REGISTER4() (REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER4)) = (0x20202020)
+#define DEF_GEMINIA_BT_DCOC_IDAC_REGISTER5() (REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER5)) = (0x20202020)
+#define DEF_GEMINIA_BT_DCOC_IDAC_REGISTER6() (REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER6)) = (0x20202020)
+#define DEF_GEMINIA_BT_DCOC_IDAC_REGISTER7() (REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER7)) = (0x20202020)
+#define DEF_GEMINIA_BT_DCOC_IDAC_REGISTER8() (REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER8)) = (0x20202020)
+#define DEF_GEMINIA_BT_DCOC_IDAC_REGISTER9() (REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER9)) = (0x20202020)
+#define DEF_GEMINIA_BT_DCOC_IDAC_REGISTER10() (REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER10)) = (0x20202020)
+#define DEF_GEMINIA_BT_DCOC_IDAC_REGISTER11() (REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER11)) = (0x20202020)
+#define DEF_GEMINIA_BT_DCOC_IDAC_REGISTER12() (REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER12)) = (0x20202020)
+#define DEF_GEMINIA_BT_DCOC_IDAC_REGISTER13() (REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER13)) = (0x20202020)
+#define DEF_GEMINIA_BT_DCOC_IDAC_REGISTER14() (REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER14)) = (0x20202020)
+#define DEF_GEMINIA_BT_DCOC_IDAC_REGISTER15() (REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER15)) = (0x20202020)
+#define DEF_GEMINIA_BT_DCOC_IDAC_REGISTER16() (REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER16)) = (0x20202020)
+#define DEF_GEMINIA_MODE_DECODER_TIMER_REGISTER1() (REG32(ADR_GEMINIA_MODE_DECODER_TIMER_REGISTER1)) = (0x00000008)
+#define DEF_GEMINIA_WIFI_T2R_TIMER_REGISTER() (REG32(ADR_GEMINIA_WIFI_T2R_TIMER_REGISTER)) = (0x02000100)
+#define DEF_GEMINIA_WIFI_R2T_TIMER_REGISTER() (REG32(ADR_GEMINIA_WIFI_R2T_TIMER_REGISTER)) = (0x00010101)
+#define DEF_GEMINIA_CALIBRATION_TIMER_REGISTER() (REG32(ADR_GEMINIA_CALIBRATION_TIMER_REGISTER)) = (0x00222222)
+#define DEF_GEMINIA_CALIBRATION_GAIN_REGISTER0() (REG32(ADR_GEMINIA_CALIBRATION_GAIN_REGISTER0)) = (0x00000000)
+#define DEF_GEMINIA_CALIBRATION_GAIN_REGISTER1() (REG32(ADR_GEMINIA_CALIBRATION_GAIN_REGISTER1)) = (0x00000000)
+#define DEF_GEMINIA_TRX_DUMMY_REGISTER() (REG32(ADR_GEMINIA_TRX_DUMMY_REGISTER)) = (0xaaaaaaaa)
+#define DEF_GEMINIA_SX_DUMMY_REGISTER() (REG32(ADR_GEMINIA_SX_DUMMY_REGISTER)) = (0xaaaaaaaa)
+#define DEF_GEMINIA_READ_ONLY_FLAGS_ADC() (REG32(ADR_GEMINIA_READ_ONLY_FLAGS_ADC)) = (0x00000000)
+#define DEF_GEMINIA_READ_ONLY_FLAGS_SX1() (REG32(ADR_GEMINIA_READ_ONLY_FLAGS_SX1)) = (0x00000000)
+#define DEF_GEMINIA_READ_ONLY_FLAGS_SX2() (REG32(ADR_GEMINIA_READ_ONLY_FLAGS_SX2)) = (0x00000000)
+#define DEF_GEMINIA_DIGITAL_ADD_ON_R0() (REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R0)) = (0x00000000)
+#define DEF_GEMINIA_DIGITAL_ADD_ON_R1() (REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R1)) = (0x000000aa)
+#define DEF_GEMINIA_DIGITAL_ADD_ON_R2() (REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R2)) = (0x80000000)
+#define DEF_GEMINIA_DIGITAL_ADD_ON_R3() (REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R3)) = (0x00000000)
+#define DEF_GEMINIA_DIGITAL_ADD_ON_R4() (REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R4)) = (0x01000000)
+#define DEF_GEMINIA_DIGITAL_ADD_ON_R5() (REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R5)) = (0x00000000)
+#define DEF_GEMINIA_DIGITAL_ADD_ON_R6() (REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R6)) = (0x00000000)
+#define DEF_GEMINIA_TX_UP8X_COEF_R0() (REG32(ADR_GEMINIA_TX_UP8X_COEF_R0)) = (0x1ff00000)
+#define DEF_GEMINIA_TX_UP8X_COEF_R1() (REG32(ADR_GEMINIA_TX_UP8X_COEF_R1)) = (0x00290000)
+#define DEF_GEMINIA_TX_UP8X_COEF_R2() (REG32(ADR_GEMINIA_TX_UP8X_COEF_R2)) = (0x1fa60000)
+#define DEF_GEMINIA_TX_UP8X_COEF_R3() (REG32(ADR_GEMINIA_TX_UP8X_COEF_R3)) = (0x00b70000)
+#define DEF_GEMINIA_TX_UP8X_COEF_R4() (REG32(ADR_GEMINIA_TX_UP8X_COEF_R4)) = (0x1e800000)
+#define DEF_GEMINIA_TX_UP8X_COEF_R5() (REG32(ADR_GEMINIA_TX_UP8X_COEF_R5)) = (0x05060800)
+#define DEF_GEMINIA_RF_D_CAL_TOP_R0() (REG32(ADR_GEMINIA_RF_D_CAL_TOP_R0)) = (0x00000000)
+#define DEF_GEMINIA_RF_D_CAL_TOP_R1() (REG32(ADR_GEMINIA_RF_D_CAL_TOP_R1)) = (0x000000e5)
+#define DEF_GEMINIA_RF_D_CAL_TOP_R2() (REG32(ADR_GEMINIA_RF_D_CAL_TOP_R2)) = (0x08003800)
+#define DEF_GEMINIA_RF_D_CAL_TOP_R3() (REG32(ADR_GEMINIA_RF_D_CAL_TOP_R3)) = (0x03330333)
+#define DEF_GEMINIA_PMU_REG_1() (REG32(ADR_GEMINIA_PMU_REG_1)) = (0x01701012)
+#define DEF_GEMINIA_PMU_REG_2() (REG32(ADR_GEMINIA_PMU_REG_2)) = (0x251a8800)
+#define DEF_GEMINIA_PMU_REG_3() (REG32(ADR_GEMINIA_PMU_REG_3)) = (0x02604170)
+#define DEF_GEMINIA_PMU_REG_4() (REG32(ADR_GEMINIA_PMU_REG_4)) = (0x95d98900)
+#define DEF_GEMINIA_PMU_REG_5() (REG32(ADR_GEMINIA_PMU_REG_5)) = (0x0002aaa8)
+#define DEF_GEMINIA_PMU_REG_6() (REG32(ADR_GEMINIA_PMU_REG_6)) = (0x00000000)
+#define DEF_GEMINIA_PMU_BT_CLK() (REG32(ADR_GEMINIA_PMU_BT_CLK)) = (0x00000000)
+#define DEF_GEMINIA_PMU_SLEEP_REG() (REG32(ADR_GEMINIA_PMU_SLEEP_REG)) = (0x00000040)
+#define DEF_GEMINIA_PMU_RTC_REG_0() (REG32(ADR_GEMINIA_PMU_RTC_REG_0)) = (0x00000000)
+#define DEF_GEMINIA_PMU_RTC_REG_1() (REG32(ADR_GEMINIA_PMU_RTC_REG_1)) = (0x00000003)
+#define DEF_GEMINIA_PMU_RTC_REG_2() (REG32(ADR_GEMINIA_PMU_RTC_REG_2)) = (0x00000000)
+#define DEF_GEMINIA_PMU_RTC_REG_3() (REG32(ADR_GEMINIA_PMU_RTC_REG_3)) = (0x00000000)
+#define DEF_GEMINIA_PMU_FDB_REG_0() (REG32(ADR_GEMINIA_PMU_FDB_REG_0)) = (0x00000000)
+#define DEF_GEMINIA_IO_REG_0() (REG32(ADR_GEMINIA_IO_REG_0)) = (0x20022222)
+#define DEF_GEMINIA_IO_REG_1() (REG32(ADR_GEMINIA_IO_REG_1)) = (0x22222222)
+#define DEF_GEMINIA_IO_REG_2() (REG32(ADR_GEMINIA_IO_REG_2)) = (0x22222222)
+#define DEF_GEMINIA_MCU_REG_0() (REG32(ADR_GEMINIA_MCU_REG_0)) = (0x00003000)
+#define DEF_GEMINIA_PMU_RAM_00() (REG32(ADR_GEMINIA_PMU_RAM_00)) = (0x00000000)
+#define DEF_GEMINIA_PMU_RAM_01() (REG32(ADR_GEMINIA_PMU_RAM_01)) = (0x00000000)
+#define DEF_GEMINIA_PMU_RAM_02() (REG32(ADR_GEMINIA_PMU_RAM_02)) = (0x00000000)
+#define DEF_GEMINIA_PMU_RAM_03() (REG32(ADR_GEMINIA_PMU_RAM_03)) = (0x00000000)
+#define DEF_GEMINIA_PMU_RAM_04() (REG32(ADR_GEMINIA_PMU_RAM_04)) = (0x00000000)
+#define DEF_GEMINIA_PMU_RAM_05() (REG32(ADR_GEMINIA_PMU_RAM_05)) = (0x00000000)
+#define DEF_GEMINIA_PMU_RAM_06() (REG32(ADR_GEMINIA_PMU_RAM_06)) = (0x00000000)
+#define DEF_GEMINIA_PMU_RAM_07() (REG32(ADR_GEMINIA_PMU_RAM_07)) = (0x00000000)
+#define DEF_GEMINIA_PMU_RAM_08() (REG32(ADR_GEMINIA_PMU_RAM_08)) = (0x00000000)
+#define DEF_GEMINIA_PMU_RAM_09() (REG32(ADR_GEMINIA_PMU_RAM_09)) = (0x00000000)
+#define DEF_GEMINIA_PMU_RAM_10() (REG32(ADR_GEMINIA_PMU_RAM_10)) = (0x00000000)
+#define DEF_GEMINIA_PMU_RAM_11() (REG32(ADR_GEMINIA_PMU_RAM_11)) = (0x00000000)
+#define DEF_GEMINIA_PMU_RAM_12() (REG32(ADR_GEMINIA_PMU_RAM_12)) = (0x00000000)
+#define DEF_GEMINIA_PMU_RAM_13() (REG32(ADR_GEMINIA_PMU_RAM_13)) = (0x00000000)
+#define DEF_GEMINIA_PMU_RAM_14() (REG32(ADR_GEMINIA_PMU_RAM_14)) = (0x00000000)
+#define DEF_GEMINIA_PMU_RAM_15() (REG32(ADR_GEMINIA_PMU_RAM_15)) = (0x00000000)
+#define DEF_GEMINIA_PMU_RAM_16() (REG32(ADR_GEMINIA_PMU_RAM_16)) = (0x00000000)
+#define DEF_GEMINIA_PMU_RAM_17() (REG32(ADR_GEMINIA_PMU_RAM_17)) = (0x00000000)
+#define DEF_GEMINIA_PMU_RAM_18() (REG32(ADR_GEMINIA_PMU_RAM_18)) = (0x00000000)
+#define DEF_GEMINIA_PMU_RAM_19() (REG32(ADR_GEMINIA_PMU_RAM_19)) = (0x00000000)
+#define DEF_GEMINIA_PMU_RAM_20() (REG32(ADR_GEMINIA_PMU_RAM_20)) = (0x00000000)
+#define DEF_GEMINIA_PMU_RAM_21() (REG32(ADR_GEMINIA_PMU_RAM_21)) = (0x00000000)
+#define DEF_GEMINIA_PMU_RAM_22() (REG32(ADR_GEMINIA_PMU_RAM_22)) = (0x00000000)
+#define DEF_GEMINIA_PMU_RAM_23() (REG32(ADR_GEMINIA_PMU_RAM_23)) = (0x00000000)
+#define DEF_GEMINIA_PMU_RAM_24() (REG32(ADR_GEMINIA_PMU_RAM_24)) = (0x00000000)
+#define DEF_GEMINIA_PMU_RAM_25() (REG32(ADR_GEMINIA_PMU_RAM_25)) = (0x00000000)
+#define DEF_GEMINIA_PMU_RAM_26() (REG32(ADR_GEMINIA_PMU_RAM_26)) = (0x00000000)
+#define DEF_GEMINIA_PMU_RAM_27() (REG32(ADR_GEMINIA_PMU_RAM_27)) = (0x00000000)
+#define DEF_GEMINIA_PMU_RAM_28() (REG32(ADR_GEMINIA_PMU_RAM_28)) = (0x00000000)
+#define DEF_GEMINIA_PMU_RAM_29() (REG32(ADR_GEMINIA_PMU_RAM_29)) = (0x00000000)
+#define DEF_GEMINIA_PMU_RAM_30() (REG32(ADR_GEMINIA_PMU_RAM_30)) = (0x00000000)
+#define DEF_GEMINIA_PMU_RAM_31() (REG32(ADR_GEMINIA_PMU_RAM_31)) = (0x00000000)
+#define DEF_TURISMO_TRX_MODE_REGISTER() (REG32(ADR_TURISMO_TRX_MODE_REGISTER)) = (0x06000040)
+#define DEF_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER() (REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) = (0x2aaaaaaa)
+#define DEF_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER() (REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) = (0x20001557)
+#define DEF_TURISMO_TRX_2_4G_LDO_REGISTER() (REG32(ADR_TURISMO_TRX_2_4G_LDO_REGISTER)) = (0x44444444)
+#define DEF_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER() (REG32(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER)) = (0x4331551b)
+#define DEF_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER() (REG32(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER)) = (0x4332550d)
+#define DEF_TURISMO_TRX_BT_RX_FILTER_REGISTER() (REG32(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER)) = (0x431d551b)
+#define DEF_TURISMO_TRX_2_4G_RX_REGISTER() (REG32(ADR_TURISMO_TRX_2_4G_RX_REGISTER)) = (0x604aea48)
+#define DEF_TURISMO_TRX_2_4G_TX_FE_REGISTER() (REG32(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER)) = (0x0607e0be)
+#define DEF_TURISMO_TRX_2_4G_TX_PA_REGISTER() (REG32(ADR_TURISMO_TRX_2_4G_TX_PA_REGISTER)) = (0x97044497)
+#define DEF_TURISMO_TRX_2_4G_TX_REGISTER() (REG32(ADR_TURISMO_TRX_2_4G_TX_REGISTER)) = (0x2a00a13f)
+#define DEF_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER() (REG32(ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER)) = (0x97c10e93)
+#define DEF_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER() (REG32(ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER)) = (0x97c10e92)
+#define DEF_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER() (REG32(ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER)) = (0x97c18001)
+#define DEF_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER() (REG32(ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER)) = (0x97c38004)
+#define DEF_TURISMO_TRX_BT_RX_FE_HG_REGISTER() (REG32(ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER)) = (0x88210643)
+#define DEF_TURISMO_TRX_BT_RX_FE_MG_REGISTER() (REG32(ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER)) = (0x88210642)
+#define DEF_TURISMO_TRX_BT_RX_FE_LG_REGISTER() (REG32(ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER)) = (0x88212001)
+#define DEF_TURISMO_TRX_BT_RX_FE_ULG_REGISTER() (REG32(ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER)) = (0x88232004)
+#define DEF_TURISMO_TRX_WBT_RX_ADC_REGISTER() (REG32(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER)) = (0x83050502)
+#define DEF_TURISMO_TRX_WIFI_TX_DAC_REGISTER() (REG32(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER)) = (0x08804355)
+#define DEF_TURISMO_TRX_BT_TX_DAC_REGISTER() (REG32(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER)) = (0x08800755)
+#define DEF_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER() (REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) = (0x802aa2aa)
+#define DEF_TURISMO_TRX_SX_2_4G_LDO_REGISTER() (REG32(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER)) = (0x2aa0021e)
+#define DEF_TURISMO_TRX_SX_2_4GB_FRACTIONAL_AND_INTEGER_8BITS() (REG32(ADR_TURISMO_TRX_SX_2_4GB_FRACTIONAL_AND_INTEGER_8BITS)) = (0x5f800000)
+#define DEF_TURISMO_TRX_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE() (REG32(ADR_TURISMO_TRX_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE)) = (0x000043c0)
+#define DEF_TURISMO_TRX_SX_2_4GB_PFD_CHP_() (REG32(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_)) = (0x05c00606)
+#define DEF_TURISMO_TRX_SX_2_4GB_LPF() (REG32(ADR_TURISMO_TRX_SX_2_4GB_LPF)) = (0x2c4293d6)
+#define DEF_TURISMO_TRX_SX_2_4GB_VCO() (REG32(ADR_TURISMO_TRX_SX_2_4GB_VCO)) = (0x002220a8)
+#define DEF_TURISMO_TRX_SX_2_4GB_VCOBF() (REG32(ADR_TURISMO_TRX_SX_2_4GB_VCOBF)) = (0x04015445)
+#define DEF_TURISMO_TRX_SX_2_4GB_DIV_SDM() (REG32(ADR_TURISMO_TRX_SX_2_4GB_DIV_SDM)) = (0x001e0077)
+#define DEF_TURISMO_TRX_SX_2_4GB_SBCAL() (REG32(ADR_TURISMO_TRX_SX_2_4GB_SBCAL)) = (0x30700400)
+#define DEF_TURISMO_TRX_SX_2_4GB_AAC() (REG32(ADR_TURISMO_TRX_SX_2_4GB_AAC)) = (0x0517cd06)
+#define DEF_TURISMO_TRX_SX_2_4GB_TTL() (REG32(ADR_TURISMO_TRX_SX_2_4GB_TTL)) = (0x00018495)
+#define DEF_TURISMO_TRX_DPLL_TOP_REGISTER() (REG32(ADR_TURISMO_TRX_DPLL_TOP_REGISTER)) = (0x00180f20)
+#define DEF_TURISMO_TRX_DPLL_CKT_REGISTER() (REG32(ADR_TURISMO_TRX_DPLL_CKT_REGISTER)) = (0x021c89ac)
+#define DEF_TURISMO_TRX_DPLL_FB_DIVISION__REGISTERS() (REG32(ADR_TURISMO_TRX_DPLL_FB_DIVISION__REGISTERS)) = (0x24ec4ec5)
+#define DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER1() (REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER1)) = (0x20202020)
+#define DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER2() (REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER2)) = (0x20202020)
+#define DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER3() (REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER3)) = (0x20202020)
+#define DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER4() (REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER4)) = (0x20202020)
+#define DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER5() (REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER5)) = (0x20202020)
+#define DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER6() (REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER6)) = (0x20202020)
+#define DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER7() (REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER7)) = (0x20202020)
+#define DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER8() (REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER8)) = (0x20202020)
+#define DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER9() (REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER9)) = (0x20202020)
+#define DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER10() (REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER10)) = (0x20202020)
+#define DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER11() (REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER11)) = (0x20202020)
+#define DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER12() (REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER12)) = (0x20202020)
+#define DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER13() (REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER13)) = (0x20202020)
+#define DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER14() (REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER14)) = (0x20202020)
+#define DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER15() (REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER15)) = (0x20202020)
+#define DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER16() (REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER16)) = (0x20202020)
+#define DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER17() (REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER17)) = (0x20202020)
+#define DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER18() (REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER18)) = (0x20202020)
+#define DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER19() (REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER19)) = (0x20202020)
+#define DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER20() (REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER20)) = (0x20202020)
+#define DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER21() (REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER21)) = (0x20202020)
+#define DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER1() (REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER1)) = (0x20202020)
+#define DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER2() (REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER2)) = (0x20202020)
+#define DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER3() (REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER3)) = (0x20202020)
+#define DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER4() (REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER4)) = (0x20202020)
+#define DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER5() (REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER5)) = (0x20202020)
+#define DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER6() (REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER6)) = (0x20202020)
+#define DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER7() (REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER7)) = (0x20202020)
+#define DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER8() (REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER8)) = (0x20202020)
+#define DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER9() (REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER9)) = (0x20202020)
+#define DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER10() (REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER10)) = (0x20202020)
+#define DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER11() (REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER11)) = (0x20202020)
+#define DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER12() (REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER12)) = (0x20202020)
+#define DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER13() (REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER13)) = (0x20202020)
+#define DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER14() (REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER14)) = (0x20202020)
+#define DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER15() (REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER15)) = (0x20202020)
+#define DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER16() (REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER16)) = (0x20202020)
+#define DEF_TURISMO_TRX_MODE_DECODER_TIMER_REGISTER1() (REG32(ADR_TURISMO_TRX_MODE_DECODER_TIMER_REGISTER1)) = (0x00000008)
+#define DEF_TURISMO_TRX_WIFI_T2R_TIMER_REGISTER() (REG32(ADR_TURISMO_TRX_WIFI_T2R_TIMER_REGISTER)) = (0x02000100)
+#define DEF_TURISMO_TRX_WIFI_R2T_TIMER_REGISTER() (REG32(ADR_TURISMO_TRX_WIFI_R2T_TIMER_REGISTER)) = (0x00010101)
+#define DEF_TURISMO_TRX_CALIBRATION_TIMER_REGISTER() (REG32(ADR_TURISMO_TRX_CALIBRATION_TIMER_REGISTER)) = (0x02222222)
+#define DEF_TURISMO_TRX_CALIBRATION_GAIN_REGISTER0() (REG32(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER0)) = (0x00000000)
+#define DEF_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1() (REG32(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1)) = (0x08520000)
+#define DEF_TURISMO_TRX_2_4G_TRX_DUMMY_REGISTER() (REG32(ADR_TURISMO_TRX_2_4G_TRX_DUMMY_REGISTER)) = (0xaaaaaaaa)
+#define DEF_TURISMO_TRX_READ_ONLY_FLAGS_ADC() (REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_ADC)) = (0x00000000)
+#define DEF_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_1() (REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_1)) = (0x00000000)
+#define DEF_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_2() (REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_2)) = (0x00000000)
+#define DEF_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER() (REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) = (0x2aa8aaaa)
+#define DEF_TURISMO_TRX_5G_LDO_REGISTER() (REG32(ADR_TURISMO_TRX_5G_LDO_REGISTER)) = (0x03044444)
+#define DEF_TURISMO_TRX_5G_RX_REGISTER1() (REG32(ADR_TURISMO_TRX_5G_RX_REGISTER1)) = (0xa1154600)
+#define DEF_TURISMO_TRX_5G_RX_REGISTER2() (REG32(ADR_TURISMO_TRX_5G_RX_REGISTER2)) = (0x0005112e)
+#define DEF_TURISMO_TRX_5G_TX_FE_REGISTER() (REG32(ADR_TURISMO_TRX_5G_TX_FE_REGISTER)) = (0x554489f4)
+#define DEF_TURISMO_TRX_5G_TX_REGISTER() (REG32(ADR_TURISMO_TRX_5G_TX_REGISTER)) = (0x0060213f)
+#define DEF_TURISMO_TRX_5G_RX_FE_HG_REGISTER() (REG32(ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER)) = (0x94490ea3)
+#define DEF_TURISMO_TRX_5G_RX_FE_MG_REGISTER() (REG32(ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER)) = (0x94490ea2)
+#define DEF_TURISMO_TRX_5G_RX_FE_LG_REGISTER() (REG32(ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER)) = (0x94498001)
+#define DEF_TURISMO_TRX_5G_RX_FE_ULG_REGISTER() (REG32(ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER)) = (0x944b8004)
+#define DEF_TURISMO_TRX_5G_TX_DAC_REGISTER() (REG32(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER)) = (0x08804355)
+#define DEF_TURISMO_TRX_SX_5GB_FRACTIONAL_AND_INTEGER_8BITS() (REG32(ADR_TURISMO_TRX_SX_5GB_FRACTIONAL_AND_INTEGER_8BITS)) = (0x45800000)
+#define DEF_TURISMO_TRX_SX_5GB_REGISTER_INT3BIT___CH_TABLE() (REG32(ADR_TURISMO_TRX_SX_5GB_REGISTER_INT3BIT___CH_TABLE)) = (0x00005000)
+#define DEF_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER() (REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) = (0x802aa2aa)
+#define DEF_TURISMO_TRX_SX_5GB_LDO_REGISTER() (REG32(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER)) = (0x2aa0021e)
+#define DEF_TURISMO_TRX_SX_5GB_PFD_CHP_() (REG32(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_)) = (0x0008700c)
+#define DEF_TURISMO_TRX_SX_5GB_LPF_TTL() (REG32(ADR_TURISMO_TRX_SX_5GB_LPF_TTL)) = (0x31552c42)
+#define DEF_TURISMO_TRX_SX_5GB_VCO_LOGEN() (REG32(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN)) = (0x11120950)
+#define DEF_TURISMO_TRX_SX_5GB_DIV_SDM() (REG32(ADR_TURISMO_TRX_SX_5GB_DIV_SDM)) = (0x001e0077)
+#define DEF_TURISMO_TRX_SX_5GB_SBCAL() (REG32(ADR_TURISMO_TRX_SX_5GB_SBCAL)) = (0x23280400)
+#define DEF_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION() (REG32(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) = (0x002947ca)
+#define DEF_TURISMO_TRX_SX_5GB_LOGEN_CALIBRATION() (REG32(ADR_TURISMO_TRX_SX_5GB_LOGEN_CALIBRATION)) = (0x0100a805)
+#define DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER1() (REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER1)) = (0x20202020)
+#define DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER2() (REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER2)) = (0x20202020)
+#define DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER3() (REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER3)) = (0x20202020)
+#define DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER4() (REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER4)) = (0x20202020)
+#define DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER5() (REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER5)) = (0x20202020)
+#define DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER6() (REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER6)) = (0x20202020)
+#define DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER7() (REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER7)) = (0x20202020)
+#define DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER8() (REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER8)) = (0x20202020)
+#define DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER9() (REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER9)) = (0x20202020)
+#define DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER10() (REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER10)) = (0x20202020)
+#define DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER11() (REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER11)) = (0x20202020)
+#define DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER12() (REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER12)) = (0x20202020)
+#define DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER13() (REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER13)) = (0x20202020)
+#define DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER14() (REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER14)) = (0x20202020)
+#define DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER15() (REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER15)) = (0x20202020)
+#define DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER16() (REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER16)) = (0x20202020)
+#define DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER17() (REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER17)) = (0x20202020)
+#define DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER18() (REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER18)) = (0x20202020)
+#define DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER19() (REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER19)) = (0x20202020)
+#define DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER20() (REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER20)) = (0x20202020)
+#define DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER21() (REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER21)) = (0x20202020)
+#define DEF_TURISMO_TRX_5G_MODE_DECODER_TIMER_REGISTER1() (REG32(ADR_TURISMO_TRX_5G_MODE_DECODER_TIMER_REGISTER1)) = (0x0000000a)
+#define DEF_TURISMO_TRX_5G_T2R_TIMER_REGISTER() (REG32(ADR_TURISMO_TRX_5G_T2R_TIMER_REGISTER)) = (0x02000100)
+#define DEF_TURISMO_TRX_5G_R2T_TIMER_REGISTER() (REG32(ADR_TURISMO_TRX_5G_R2T_TIMER_REGISTER)) = (0x00010101)
+#define DEF_TURISMO_TRX_5G_CALIBRATION_TIMER_GAIN_REGISTER() (REG32(ADR_TURISMO_TRX_5G_CALIBRATION_TIMER_GAIN_REGISTER)) = (0x00022202)
+#define DEF_TURISMO_TRX_5G_CALIBRATION_GAIN_REGISTER1() (REG32(ADR_TURISMO_TRX_5G_CALIBRATION_GAIN_REGISTER1)) = (0x00000000)
+#define DEF_TURISMO_TRX_5G_TRX_DUMMY_REGISTER() (REG32(ADR_TURISMO_TRX_5G_TRX_DUMMY_REGISTER)) = (0xaaaaaaaa)
+#define DEF_TURISMO_TRX_SX_5GB_DUMMY_REGISTER() (REG32(ADR_TURISMO_TRX_SX_5GB_DUMMY_REGISTER)) = (0xaaaaaaaa)
+#define DEF_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_1() (REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_1)) = (0x00000000)
+#define DEF_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_2() (REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_2)) = (0x00000000)
+#define DEF_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_3() (REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_3)) = (0x00000000)
+#define DEF_TURISMO_TRX_5G_RX_LNA_MATCHING_SCA_CONTROL() (REG32(ADR_TURISMO_TRX_5G_RX_LNA_MATCHING_SCA_CONTROL)) = (0x03333220)
+#define DEF_TURISMO_TRX_5G_RX_LNA_LOAD_SCA_CONTROL() (REG32(ADR_TURISMO_TRX_5G_RX_LNA_LOAD_SCA_CONTROL)) = (0x03333220)
+#define DEF_TURISMO_TRX_5G_TX_PGA_CAPSW_CONTROL() (REG32(ADR_TURISMO_TRX_5G_TX_PGA_CAPSW_CONTROL)) = (0x02422220)
+#define DEF_TURISMO_TRX_DIGITAL_ADD_ON_0() (REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_0)) = (0x00000000)
+#define DEF_TURISMO_TRX_DIGITAL_ADD_ON_1() (REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_1)) = (0x036b55aa)
+#define DEF_TURISMO_TRX_DIGITAL_ADD_ON_2() (REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2)) = (0x80000000)
+#define DEF_TURISMO_TRX_DIGITAL_ADD_ON_3() (REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_3)) = (0x00100000)
+#define DEF_TURISMO_TRX_DIGITAL_ADD_ON_4() (REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_4)) = (0x01000000)
+#define DEF_TURISMO_TRX_DIGITAL_ADD_ON_5() (REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_5)) = (0x00000000)
+#define DEF_TURISMO_TRX_DIGITAL_ADD_ON_6() (REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_6)) = (0x00000000)
+#define DEF_TURISMO_TRX_TX_BW20_FIR_COEF_00() (REG32(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_00)) = (0x1ff00000)
+#define DEF_TURISMO_TRX_TX_BW20_FIR_COEF_01() (REG32(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_01)) = (0x00290000)
+#define DEF_TURISMO_TRX_TX_BW20_FIR_COEF_02() (REG32(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_02)) = (0x1fa60000)
+#define DEF_TURISMO_TRX_TX_BW20_FIR_COEF_03() (REG32(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_03)) = (0x00b70000)
+#define DEF_TURISMO_TRX_TX_BW20_FIR_COEF_04() (REG32(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_04)) = (0x1e800000)
+#define DEF_TURISMO_TRX_TX_BW20_FIR_COEF_05() (REG32(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_05)) = (0x05060800)
+#define DEF_TURISMO_TRX_RF_D_CAL_TOP_0() (REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_0)) = (0x00000000)
+#define DEF_TURISMO_TRX_RF_D_CAL_TOP_1() (REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_1)) = (0x00000000)
+#define DEF_TURISMO_TRX_RF_D_CAL_TOP_2() (REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_2)) = (0x08003800)
+#define DEF_TURISMO_TRX_RF_D_CAL_TOP_3() (REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_3)) = (0x03330333)
+#define DEF_TURISMO_TRX_RF_D_CAL_TOP_4() (REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_4)) = (0x70001000)
+#define DEF_TURISMO_TRX_RF_D_CAL_TOP_5() (REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_5)) = (0x00000000)
+#define DEF_TURISMO_TRX_RF_D_CAL_TOP_6() (REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_6)) = (0x00e500e5)
+#define DEF_TURISMO_TRX_RF_D_CAL_TOP_7() (REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_7)) = (0x00000000)
+#define DEF_TURISMO_TRX_RF_D_CAL_TOP_8() (REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_8)) = (0x00000000)
+#define DEF_TURISMO_TRX_RF_D_CAL_TOP_9() (REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_9)) = (0x00000044)
+#define DEF_TURISMO_TRX_HS3W_CTRL1() (REG32(ADR_TURISMO_TRX_HS3W_CTRL1)) = (0x00000000)
+#define DEF_TURISMO_TRX_HS3W_CTRL2() (REG32(ADR_TURISMO_TRX_HS3W_CTRL2)) = (0x00000000)
+#define DEF_TURISMO_TRX_HS3W_CTRL3() (REG32(ADR_TURISMO_TRX_HS3W_CTRL3)) = (0x60000000)
+#define DEF_TURISMO_TRX_RF_D_MODE_CTRL() (REG32(ADR_TURISMO_TRX_RF_D_MODE_CTRL)) = (0x00000000)
+#define DEF_TURISMO_TRX_RX_DC_CAL_RESULT() (REG32(ADR_TURISMO_TRX_RX_DC_CAL_RESULT)) = (0x00000000)
+#define DEF_TURISMO_TRX_PMU_REG_1() (REG32(ADR_TURISMO_TRX_PMU_REG_1)) = (0x2d008014)
+#define DEF_TURISMO_TRX_PMU_REG_2() (REG32(ADR_TURISMO_TRX_PMU_REG_2)) = (0x251a8800)
+#define DEF_TURISMO_TRX_PMU_REG_3() (REG32(ADR_TURISMO_TRX_PMU_REG_3)) = (0x486041ae)
+#define DEF_TURISMO_TRX_PMU_REG_4() (REG32(ADR_TURISMO_TRX_PMU_REG_4)) = (0x95d98900)
+#define DEF_TURISMO_TRX_PMU_REG_5() (REG32(ADR_TURISMO_TRX_PMU_REG_5)) = (0xaaaaaaa8)
+#define DEF_TURISMO_TRX_PMU_REG_6() (REG32(ADR_TURISMO_TRX_PMU_REG_6)) = (0x00000000)
+#define DEF_TURISMO_TRX_PMU_SLEEP_REG_1() (REG32(ADR_TURISMO_TRX_PMU_SLEEP_REG_1)) = (0x00000000)
+#define DEF_TURISMO_TRX_PMU_SLEEP_REG_2() (REG32(ADR_TURISMO_TRX_PMU_SLEEP_REG_2)) = (0x00000040)
+#define DEF_TURISMO_TRX_PMU_RTC_REG_0() (REG32(ADR_TURISMO_TRX_PMU_RTC_REG_0)) = (0x00007d00)
+#define DEF_TURISMO_TRX_PMU_RTC_REG_1() (REG32(ADR_TURISMO_TRX_PMU_RTC_REG_1)) = (0x00000003)
+#define DEF_TURISMO_TRX_PMU_RTC_REG_2() (REG32(ADR_TURISMO_TRX_PMU_RTC_REG_2)) = (0x00000000)
+#define DEF_TURISMO_TRX_PMU_RTC_REG_3() (REG32(ADR_TURISMO_TRX_PMU_RTC_REG_3)) = (0x00000000)
+#define DEF_TURISMO_TRX_PMU_CTRL_REG() (REG32(ADR_TURISMO_TRX_PMU_CTRL_REG)) = (0x00000010)
+#define DEF_TURISMO_TRX_PMU_STATE_REG() (REG32(ADR_TURISMO_TRX_PMU_STATE_REG)) = (0x00000000)
+#define DEF_TURISMO_TRX_PMU_BT_CLK() (REG32(ADR_TURISMO_TRX_PMU_BT_CLK)) = (0x00000000)
+#define DEF_TURISMO_TRX_IO_REG_0() (REG32(ADR_TURISMO_TRX_IO_REG_0)) = (0x20022222)
+#define DEF_TURISMO_TRX_IO_REG_1() (REG32(ADR_TURISMO_TRX_IO_REG_1)) = (0x22222222)
+#define DEF_TURISMO_TRX_IO_REG_2() (REG32(ADR_TURISMO_TRX_IO_REG_2)) = (0x22222222)
+#define DEF_TURISMO_TRX_MCU_REG_0() (REG32(ADR_TURISMO_TRX_MCU_REG_0)) = (0x00003000)
+#define DEF_TURISMO_TRX_PMU_RAM_00() (REG32(ADR_TURISMO_TRX_PMU_RAM_00)) = (0x00000000)
+#define DEF_TURISMO_TRX_PMU_RAM_01() (REG32(ADR_TURISMO_TRX_PMU_RAM_01)) = (0x00000000)
+#define DEF_TURISMO_TRX_PMU_RAM_02() (REG32(ADR_TURISMO_TRX_PMU_RAM_02)) = (0x00000000)
+#define DEF_TURISMO_TRX_PMU_RAM_03() (REG32(ADR_TURISMO_TRX_PMU_RAM_03)) = (0x00000000)
+#define DEF_TURISMO_TRX_PMU_RAM_04() (REG32(ADR_TURISMO_TRX_PMU_RAM_04)) = (0x00000000)
+#define DEF_TURISMO_TRX_PMU_RAM_05() (REG32(ADR_TURISMO_TRX_PMU_RAM_05)) = (0x00000000)
+#define DEF_TURISMO_TRX_PMU_RAM_06() (REG32(ADR_TURISMO_TRX_PMU_RAM_06)) = (0x00000000)
+#define DEF_TURISMO_TRX_PMU_RAM_07() (REG32(ADR_TURISMO_TRX_PMU_RAM_07)) = (0x00000000)
+#define DEF_TURISMO_TRX_PMU_RAM_08() (REG32(ADR_TURISMO_TRX_PMU_RAM_08)) = (0x00000000)
+#define DEF_TURISMO_TRX_PMU_RAM_09() (REG32(ADR_TURISMO_TRX_PMU_RAM_09)) = (0x00000000)
+#define DEF_TURISMO_TRX_PMU_RAM_10() (REG32(ADR_TURISMO_TRX_PMU_RAM_10)) = (0x00000000)
+#define DEF_TURISMO_TRX_PMU_RAM_11() (REG32(ADR_TURISMO_TRX_PMU_RAM_11)) = (0x00000000)
+#define DEF_TURISMO_TRX_PMU_RAM_12() (REG32(ADR_TURISMO_TRX_PMU_RAM_12)) = (0x00000000)
+#define DEF_TURISMO_TRX_PMU_RAM_13() (REG32(ADR_TURISMO_TRX_PMU_RAM_13)) = (0x00000000)
+#define DEF_TURISMO_TRX_PMU_RAM_14() (REG32(ADR_TURISMO_TRX_PMU_RAM_14)) = (0x00000000)
+#define DEF_TURISMO_TRX_PMU_RAM_15() (REG32(ADR_TURISMO_TRX_PMU_RAM_15)) = (0x00000000)
+#define DEF_TURISMO_TRX_PMU_RAM_16() (REG32(ADR_TURISMO_TRX_PMU_RAM_16)) = (0x00000000)
+#define DEF_TURISMO_TRX_PMU_RAM_17() (REG32(ADR_TURISMO_TRX_PMU_RAM_17)) = (0x00000000)
+#define DEF_TURISMO_TRX_PMU_RAM_18() (REG32(ADR_TURISMO_TRX_PMU_RAM_18)) = (0x00000000)
+#define DEF_TURISMO_TRX_PMU_RAM_19() (REG32(ADR_TURISMO_TRX_PMU_RAM_19)) = (0x00000000)
+#define DEF_TURISMO_TRX_PMU_RAM_20() (REG32(ADR_TURISMO_TRX_PMU_RAM_20)) = (0x00000000)
+#define DEF_TURISMO_TRX_PMU_RAM_21() (REG32(ADR_TURISMO_TRX_PMU_RAM_21)) = (0x00000000)
+#define DEF_TURISMO_TRX_PMU_RAM_22() (REG32(ADR_TURISMO_TRX_PMU_RAM_22)) = (0x00000000)
+#define DEF_TURISMO_TRX_PMU_RAM_23() (REG32(ADR_TURISMO_TRX_PMU_RAM_23)) = (0x00000000)
+#define DEF_TURISMO_TRX_PMU_RAM_24() (REG32(ADR_TURISMO_TRX_PMU_RAM_24)) = (0x00000000)
+#define DEF_TURISMO_TRX_PMU_RAM_25() (REG32(ADR_TURISMO_TRX_PMU_RAM_25)) = (0x00000000)
+#define DEF_TURISMO_TRX_PMU_RAM_26() (REG32(ADR_TURISMO_TRX_PMU_RAM_26)) = (0x00000000)
+#define DEF_TURISMO_TRX_PMU_RAM_27() (REG32(ADR_TURISMO_TRX_PMU_RAM_27)) = (0x00000000)
+#define DEF_TURISMO_TRX_PMU_RAM_28() (REG32(ADR_TURISMO_TRX_PMU_RAM_28)) = (0x00000000)
+#define DEF_TURISMO_TRX_PMU_RAM_29() (REG32(ADR_TURISMO_TRX_PMU_RAM_29)) = (0x00000000)
+#define DEF_TURISMO_TRX_PMU_RAM_30() (REG32(ADR_TURISMO_TRX_PMU_RAM_30)) = (0x00000000)
+#define DEF_TURISMO_TRX_PMU_RAM_31() (REG32(ADR_TURISMO_TRX_PMU_RAM_31)) = (0x00000000)
+#define DEF_MODE_REGISTER() (REG32(ADR_MODE_REGISTER)) = (0x06000044)
+#define DEF_2_4G_TRX_MANUAL_ENABLE_REGISTER() (REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) = (0x2aaaaaaa)
+#define DEF_2_4G_CALIBRATION__AMP__TEST_REGISTER() (REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) = (0x20001557)
+#define DEF_2_4G_LDO_REGISTER() (REG32(ADR_2_4G_LDO_REGISTER)) = (0x44440044)
+#define DEF_WIFI_HT20_RX_FILTER_REGISTER() (REG32(ADR_WIFI_HT20_RX_FILTER_REGISTER)) = (0x43b1559b)
+#define DEF_WIFI_HT40_RX_FILTER_REGISTER() (REG32(ADR_WIFI_HT40_RX_FILTER_REGISTER)) = (0x43b2558d)
+#define DEF_BT_RX_FILTER_REGISTER() (REG32(ADR_BT_RX_FILTER_REGISTER)) = (0x439d559b)
+#define DEF_2_4G_RX_REGISTER() (REG32(ADR_2_4G_RX_REGISTER)) = (0x604aea48)
+#define DEF_2_4G_TX_FE_REGISTER() (REG32(ADR_2_4G_TX_FE_REGISTER)) = (0x0033e73e)
+#define DEF_2_4G_TX_PA_REGISTER() (REG32(ADR_2_4G_TX_PA_REGISTER)) = (0x57444497)
+#define DEF_2_4G_TX_REGISTER() (REG32(ADR_2_4G_TX_REGISTER)) = (0x2a00a13f)
+#define DEF_2_4G_RX_FE_HG_REGISTER() (REG32(ADR_2_4G_RX_FE_HG_REGISTER)) = (0x97c10e93)
+#define DEF_2_4G_RX_FE_MG_REGISTER() (REG32(ADR_2_4G_RX_FE_MG_REGISTER)) = (0x97c10e92)
+#define DEF_2_4G_RX_FE_LG_REGISTER() (REG32(ADR_2_4G_RX_FE_LG_REGISTER)) = (0x97c18001)
+#define DEF_2_4G_RX_FE_ULG_REGISTER() (REG32(ADR_2_4G_RX_FE_ULG_REGISTER)) = (0x97c38004)
+#define DEF_BT_RX_FE_HG_REGISTER() (REG32(ADR_BT_RX_FE_HG_REGISTER)) = (0x88210863)
+#define DEF_BT_RX_FE_MG_REGISTER() (REG32(ADR_BT_RX_FE_MG_REGISTER)) = (0x88210862)
+#define DEF_BT_RX_FE_LG_REGISTER() (REG32(ADR_BT_RX_FE_LG_REGISTER)) = (0x88216001)
+#define DEF_BT_RX_FE_ULG_REGISTER() (REG32(ADR_BT_RX_FE_ULG_REGISTER)) = (0x88036000)
+#define DEF_WBT_RX_ADC_REGISTER() (REG32(ADR_WBT_RX_ADC_REGISTER)) = (0x83050502)
+#define DEF_WIFI_TX_DAC_REGISTER() (REG32(ADR_WIFI_TX_DAC_REGISTER)) = (0x08804355)
+#define DEF_BT_TX_DAC_REGISTER() (REG32(ADR_BT_TX_DAC_REGISTER)) = (0x08800755)
+#define DEF_SX_ENABLE_REGISTER_TOP_CONTROLLER() (REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) = (0x802aa2aa)
+#define DEF_SX_2_4G_LDO_REGISTER() (REG32(ADR_SX_2_4G_LDO_REGISTER)) = (0x2aa0021e)
+#define DEF_SX_2_4GB_FRACTIONAL_AND_INTEGER_8BITS() (REG32(ADR_SX_2_4GB_FRACTIONAL_AND_INTEGER_8BITS)) = (0x5f800000)
+#define DEF_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE() (REG32(ADR_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE)) = (0x00204280)
+#define DEF_SX_2_4GB_PFD_CHP_() (REG32(ADR_SX_2_4GB_PFD_CHP_)) = (0x05c30606)
+#define DEF_SX_2_4GB_LPF() (REG32(ADR_SX_2_4GB_LPF)) = (0x2c4293d6)
+#define DEF_SX_2_4GB_VCO() (REG32(ADR_SX_2_4GB_VCO)) = (0x002220a8)
+#define DEF_SX_2_4GB_VCOBF() (REG32(ADR_SX_2_4GB_VCOBF)) = (0x04015445)
+#define DEF_SX_2_4GB_DIV_SDM() (REG32(ADR_SX_2_4GB_DIV_SDM)) = (0x001e0077)
+#define DEF_SX_2_4GB_SBCAL() (REG32(ADR_SX_2_4GB_SBCAL)) = (0x30700400)
+#define DEF_SX_2_4GB_AAC() (REG32(ADR_SX_2_4GB_AAC)) = (0x0517cd06)
+#define DEF_SX_2_4GB_TTL() (REG32(ADR_SX_2_4GB_TTL)) = (0x00018495)
+#define DEF_WF_DCOC_IDAC_REGISTER1() (REG32(ADR_WF_DCOC_IDAC_REGISTER1)) = (0x20202020)
+#define DEF_WF_DCOC_IDAC_REGISTER2() (REG32(ADR_WF_DCOC_IDAC_REGISTER2)) = (0x20202020)
+#define DEF_WF_DCOC_IDAC_REGISTER3() (REG32(ADR_WF_DCOC_IDAC_REGISTER3)) = (0x20202020)
+#define DEF_WF_DCOC_IDAC_REGISTER4() (REG32(ADR_WF_DCOC_IDAC_REGISTER4)) = (0x20202020)
+#define DEF_WF_DCOC_IDAC_REGISTER5() (REG32(ADR_WF_DCOC_IDAC_REGISTER5)) = (0x20202020)
+#define DEF_WF_DCOC_IDAC_REGISTER6() (REG32(ADR_WF_DCOC_IDAC_REGISTER6)) = (0x20202020)
+#define DEF_WF_DCOC_IDAC_REGISTER7() (REG32(ADR_WF_DCOC_IDAC_REGISTER7)) = (0x20202020)
+#define DEF_WF_DCOC_IDAC_REGISTER8() (REG32(ADR_WF_DCOC_IDAC_REGISTER8)) = (0x20202020)
+#define DEF_WF_DCOC_IDAC_REGISTER9() (REG32(ADR_WF_DCOC_IDAC_REGISTER9)) = (0x20202020)
+#define DEF_WF_DCOC_IDAC_REGISTER10() (REG32(ADR_WF_DCOC_IDAC_REGISTER10)) = (0x20202020)
+#define DEF_WF_DCOC_IDAC_REGISTER11() (REG32(ADR_WF_DCOC_IDAC_REGISTER11)) = (0x20202020)
+#define DEF_WF_DCOC_IDAC_REGISTER12() (REG32(ADR_WF_DCOC_IDAC_REGISTER12)) = (0x20202020)
+#define DEF_WF_DCOC_IDAC_REGISTER13() (REG32(ADR_WF_DCOC_IDAC_REGISTER13)) = (0x20202020)
+#define DEF_WF_DCOC_IDAC_REGISTER14() (REG32(ADR_WF_DCOC_IDAC_REGISTER14)) = (0x20202020)
+#define DEF_WF_DCOC_IDAC_REGISTER15() (REG32(ADR_WF_DCOC_IDAC_REGISTER15)) = (0x20202020)
+#define DEF_WF_DCOC_IDAC_REGISTER16() (REG32(ADR_WF_DCOC_IDAC_REGISTER16)) = (0x20202020)
+#define DEF_WF_DCOC_IDAC_REGISTER17() (REG32(ADR_WF_DCOC_IDAC_REGISTER17)) = (0x20202020)
+#define DEF_WF_DCOC_IDAC_REGISTER18() (REG32(ADR_WF_DCOC_IDAC_REGISTER18)) = (0x20202020)
+#define DEF_WF_DCOC_IDAC_REGISTER19() (REG32(ADR_WF_DCOC_IDAC_REGISTER19)) = (0x20202020)
+#define DEF_WF_DCOC_IDAC_REGISTER20() (REG32(ADR_WF_DCOC_IDAC_REGISTER20)) = (0x20202020)
+#define DEF_WF_DCOC_IDAC_REGISTER21() (REG32(ADR_WF_DCOC_IDAC_REGISTER21)) = (0x20202020)
+#define DEF_BT_DCOC_IDAC_REGISTER1() (REG32(ADR_BT_DCOC_IDAC_REGISTER1)) = (0x20202020)
+#define DEF_BT_DCOC_IDAC_REGISTER2() (REG32(ADR_BT_DCOC_IDAC_REGISTER2)) = (0x20202020)
+#define DEF_BT_DCOC_IDAC_REGISTER3() (REG32(ADR_BT_DCOC_IDAC_REGISTER3)) = (0x20202020)
+#define DEF_BT_DCOC_IDAC_REGISTER4() (REG32(ADR_BT_DCOC_IDAC_REGISTER4)) = (0x20202020)
+#define DEF_BT_DCOC_IDAC_REGISTER5() (REG32(ADR_BT_DCOC_IDAC_REGISTER5)) = (0x20202020)
+#define DEF_BT_DCOC_IDAC_REGISTER6() (REG32(ADR_BT_DCOC_IDAC_REGISTER6)) = (0x20202020)
+#define DEF_BT_DCOC_IDAC_REGISTER7() (REG32(ADR_BT_DCOC_IDAC_REGISTER7)) = (0x20202020)
+#define DEF_BT_DCOC_IDAC_REGISTER8() (REG32(ADR_BT_DCOC_IDAC_REGISTER8)) = (0x20202020)
+#define DEF_BT_DCOC_IDAC_REGISTER9() (REG32(ADR_BT_DCOC_IDAC_REGISTER9)) = (0x20202020)
+#define DEF_BT_DCOC_IDAC_REGISTER10() (REG32(ADR_BT_DCOC_IDAC_REGISTER10)) = (0x20202020)
+#define DEF_BT_DCOC_IDAC_REGISTER11() (REG32(ADR_BT_DCOC_IDAC_REGISTER11)) = (0x20202020)
+#define DEF_BT_DCOC_IDAC_REGISTER12() (REG32(ADR_BT_DCOC_IDAC_REGISTER12)) = (0x20202020)
+#define DEF_BT_DCOC_IDAC_REGISTER13() (REG32(ADR_BT_DCOC_IDAC_REGISTER13)) = (0x20202020)
+#define DEF_BT_DCOC_IDAC_REGISTER14() (REG32(ADR_BT_DCOC_IDAC_REGISTER14)) = (0x20202020)
+#define DEF_BT_DCOC_IDAC_REGISTER15() (REG32(ADR_BT_DCOC_IDAC_REGISTER15)) = (0x20202020)
+#define DEF_BT_DCOC_IDAC_REGISTER16() (REG32(ADR_BT_DCOC_IDAC_REGISTER16)) = (0x20202020)
+#define DEF_MODE_DECODER_TIMER_REGISTER1() (REG32(ADR_MODE_DECODER_TIMER_REGISTER1)) = (0x00000008)
+#define DEF_WIFI_T2R_TIMER_REGISTER() (REG32(ADR_WIFI_T2R_TIMER_REGISTER)) = (0x02000100)
+#define DEF_WIFI_R2T_TIMER_REGISTER() (REG32(ADR_WIFI_R2T_TIMER_REGISTER)) = (0x00010101)
+#define DEF_CALIBRATION_TIMER_REGISTER() (REG32(ADR_CALIBRATION_TIMER_REGISTER)) = (0x02222222)
+#define DEF_CALIBRATION_GAIN_REGISTER0() (REG32(ADR_CALIBRATION_GAIN_REGISTER0)) = (0x00000000)
+#define DEF_CALIBRATION_GAIN_REGISTER1() (REG32(ADR_CALIBRATION_GAIN_REGISTER1)) = (0x04520000)
+#define DEF_2_4G_TRX_DUMMY_REGISTER() (REG32(ADR_2_4G_TRX_DUMMY_REGISTER)) = (0xaaaaaaaa)
+#define DEF_READ_ONLY_FLAGS_ADC() (REG32(ADR_READ_ONLY_FLAGS_ADC)) = (0x00000000)
+#define DEF_READ_ONLY_FLAGS_SX_2_4GB_1() (REG32(ADR_READ_ONLY_FLAGS_SX_2_4GB_1)) = (0x00000000)
+#define DEF_READ_ONLY_FLAGS_SX_2_4GB_2() (REG32(ADR_READ_ONLY_FLAGS_SX_2_4GB_2)) = (0x00000000)
+#define DEF_5G_TRX_MANUAL_ENABLE_REGISTER() (REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) = (0x2aa8aaaa)
+#define DEF_5G_LDO_REGISTER() (REG32(ADR_5G_LDO_REGISTER)) = (0x03044444)
+#define DEF_5G_RX_REGISTER1() (REG32(ADR_5G_RX_REGISTER1)) = (0xa1152600)
+#define DEF_5G_RX_REGISTER2() (REG32(ADR_5G_RX_REGISTER2)) = (0x0505112e)
+#define DEF_5G_TX_FE_REGISTER() (REG32(ADR_5G_TX_FE_REGISTER)) = (0x554489e4)
+#define DEF_5G_TX_REGISTER() (REG32(ADR_5G_TX_REGISTER)) = (0x9060a13f)
+#define DEF_5G_RX_FE_HG_REGISTER() (REG32(ADR_5G_RX_FE_HG_REGISTER)) = (0x94490ea3)
+#define DEF_5G_RX_FE_MG_REGISTER() (REG32(ADR_5G_RX_FE_MG_REGISTER)) = (0x94490ea2)
+#define DEF_5G_RX_FE_LG_REGISTER() (REG32(ADR_5G_RX_FE_LG_REGISTER)) = (0x94498001)
+#define DEF_5G_RX_FE_ULG_REGISTER() (REG32(ADR_5G_RX_FE_ULG_REGISTER)) = (0x944b8004)
+#define DEF_5G_TX_DAC_REGISTER() (REG32(ADR_5G_TX_DAC_REGISTER)) = (0x08804355)
+#define DEF_SX_5GB_FRACTIONAL_AND_INTEGER_8BITS() (REG32(ADR_SX_5GB_FRACTIONAL_AND_INTEGER_8BITS)) = (0x45800000)
+#define DEF_SX_5GB_REGISTER_INT3BIT___CH_TABLE() (REG32(ADR_SX_5GB_REGISTER_INT3BIT___CH_TABLE)) = (0x00005000)
+#define DEF_SX_5GB_ENABLE_TOP_CONTROLLER() (REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) = (0x802aa2aa)
+#define DEF_SX_5GB_LDO_REGISTER() (REG32(ADR_SX_5GB_LDO_REGISTER)) = (0x2aa0029e)
+#define DEF_SX_5GB_PFD_CHP_() (REG32(ADR_SX_5GB_PFD_CHP_)) = (0x0008730c)
+#define DEF_SX_5GB_LPF_TTL() (REG32(ADR_SX_5GB_LPF_TTL)) = (0x31552cc3)
+#define DEF_SX_5GB_VCO_LOGEN() (REG32(ADR_SX_5GB_VCO_LOGEN)) = (0x11120950)
+#define DEF_SX_5GB_DIV_SDM() (REG32(ADR_SX_5GB_DIV_SDM)) = (0x0f1e003f)
+#define DEF_SX_5GB_SBCAL() (REG32(ADR_SX_5GB_SBCAL)) = (0x23280400)
+#define DEF_SX_5GB_VCO_AAC_LOGEN_CALIBRATION() (REG32(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) = (0x002947ca)
+#define DEF_SX_5GB_LOGEN_CALIBRATION() (REG32(ADR_SX_5GB_LOGEN_CALIBRATION)) = (0x0100a805)
+#define DEF_5G_DCOC_IDAC_REGISTER1() (REG32(ADR_5G_DCOC_IDAC_REGISTER1)) = (0x20202020)
+#define DEF_5G_DCOC_IDAC_REGISTER2() (REG32(ADR_5G_DCOC_IDAC_REGISTER2)) = (0x20202020)
+#define DEF_5G_DCOC_IDAC_REGISTER3() (REG32(ADR_5G_DCOC_IDAC_REGISTER3)) = (0x20202020)
+#define DEF_5G_DCOC_IDAC_REGISTER4() (REG32(ADR_5G_DCOC_IDAC_REGISTER4)) = (0x20202020)
+#define DEF_5G_DCOC_IDAC_REGISTER5() (REG32(ADR_5G_DCOC_IDAC_REGISTER5)) = (0x20202020)
+#define DEF_5G_DCOC_IDAC_REGISTER6() (REG32(ADR_5G_DCOC_IDAC_REGISTER6)) = (0x20202020)
+#define DEF_5G_DCOC_IDAC_REGISTER7() (REG32(ADR_5G_DCOC_IDAC_REGISTER7)) = (0x20202020)
+#define DEF_5G_DCOC_IDAC_REGISTER8() (REG32(ADR_5G_DCOC_IDAC_REGISTER8)) = (0x20202020)
+#define DEF_5G_DCOC_IDAC_REGISTER9() (REG32(ADR_5G_DCOC_IDAC_REGISTER9)) = (0x20202020)
+#define DEF_5G_DCOC_IDAC_REGISTER10() (REG32(ADR_5G_DCOC_IDAC_REGISTER10)) = (0x20202020)
+#define DEF_5G_DCOC_IDAC_REGISTER11() (REG32(ADR_5G_DCOC_IDAC_REGISTER11)) = (0x20202020)
+#define DEF_5G_DCOC_IDAC_REGISTER12() (REG32(ADR_5G_DCOC_IDAC_REGISTER12)) = (0x20202020)
+#define DEF_5G_DCOC_IDAC_REGISTER13() (REG32(ADR_5G_DCOC_IDAC_REGISTER13)) = (0x20202020)
+#define DEF_5G_DCOC_IDAC_REGISTER14() (REG32(ADR_5G_DCOC_IDAC_REGISTER14)) = (0x20202020)
+#define DEF_5G_DCOC_IDAC_REGISTER15() (REG32(ADR_5G_DCOC_IDAC_REGISTER15)) = (0x20202020)
+#define DEF_5G_DCOC_IDAC_REGISTER16() (REG32(ADR_5G_DCOC_IDAC_REGISTER16)) = (0x20202020)
+#define DEF_5G_DCOC_IDAC_REGISTER17() (REG32(ADR_5G_DCOC_IDAC_REGISTER17)) = (0x20202020)
+#define DEF_5G_DCOC_IDAC_REGISTER18() (REG32(ADR_5G_DCOC_IDAC_REGISTER18)) = (0x20202020)
+#define DEF_5G_DCOC_IDAC_REGISTER19() (REG32(ADR_5G_DCOC_IDAC_REGISTER19)) = (0x20202020)
+#define DEF_5G_DCOC_IDAC_REGISTER20() (REG32(ADR_5G_DCOC_IDAC_REGISTER20)) = (0x20202020)
+#define DEF_5G_DCOC_IDAC_REGISTER21() (REG32(ADR_5G_DCOC_IDAC_REGISTER21)) = (0x20202020)
+#define DEF_5G_MODE_DECODER_TIMER_REGISTER1() (REG32(ADR_5G_MODE_DECODER_TIMER_REGISTER1)) = (0x0000000a)
+#define DEF_5G_T2R_TIMER_REGISTER() (REG32(ADR_5G_T2R_TIMER_REGISTER)) = (0x02000100)
+#define DEF_5G_R2T_TIMER_REGISTER() (REG32(ADR_5G_R2T_TIMER_REGISTER)) = (0x00010101)
+#define DEF_5G_CALIBRATION_TIMER_GAIN_REGISTER() (REG32(ADR_5G_CALIBRATION_TIMER_GAIN_REGISTER)) = (0x00022202)
+#define DEF_5G_CALIBRATION_GAIN_REGISTER1() (REG32(ADR_5G_CALIBRATION_GAIN_REGISTER1)) = (0x00000000)
+#define DEF_5G_TRX_DUMMY_REGISTER() (REG32(ADR_5G_TRX_DUMMY_REGISTER)) = (0xaaaaaaaa)
+#define DEF_SX_5GB_DUMMY_REGISTER() (REG32(ADR_SX_5GB_DUMMY_REGISTER)) = (0xaaaaaaaa)
+#define DEF_READ_ONLY_FLAGS_SX_5GB_1() (REG32(ADR_READ_ONLY_FLAGS_SX_5GB_1)) = (0x00000000)
+#define DEF_READ_ONLY_FLAGS_SX_5GB_2() (REG32(ADR_READ_ONLY_FLAGS_SX_5GB_2)) = (0x00000000)
+#define DEF_READ_ONLY_FLAGS_SX_5GB_3() (REG32(ADR_READ_ONLY_FLAGS_SX_5GB_3)) = (0x00000000)
+#define DEF_5G_RX_LNA_MATCHING_SCA_CONTROL() (REG32(ADR_5G_RX_LNA_MATCHING_SCA_CONTROL)) = (0x02000000)
+#define DEF_5G_RX_LNA_LOAD_SCA_CONTROL() (REG32(ADR_5G_RX_LNA_LOAD_SCA_CONTROL)) = (0x06665200)
+#define DEF_5G_TX_PGA_CAPSW_CONTROL_I() (REG32(ADR_5G_TX_PGA_CAPSW_CONTROL_I)) = (0x924a924a)
+#define DEF_5G_TX_PGA_CAPSW_CONTROL_II() (REG32(ADR_5G_TX_PGA_CAPSW_CONTROL_II)) = (0x924a924a)
+#define DEF_5G_TX_GAIN_PAFB_CONTROL() (REG32(ADR_5G_TX_GAIN_PAFB_CONTROL)) = (0x0000000f)
+#define DEF_DIGITAL_ADD_ON_0() (REG32(ADR_DIGITAL_ADD_ON_0)) = (0x00000000)
+#define DEF_DIGITAL_ADD_ON_1() (REG32(ADR_DIGITAL_ADD_ON_1)) = (0x036b55aa)
+#define DEF_DIGITAL_ADD_ON_2() (REG32(ADR_DIGITAL_ADD_ON_2)) = (0x80000000)
+#define DEF_DIGITAL_ADD_ON_3() (REG32(ADR_DIGITAL_ADD_ON_3)) = (0x00100000)
+#define DEF_DIGITAL_ADD_ON_4() (REG32(ADR_DIGITAL_ADD_ON_4)) = (0x01000000)
+#define DEF_DIGITAL_ADD_ON_5() (REG32(ADR_DIGITAL_ADD_ON_5)) = (0x00000000)
+#define DEF_DIGITAL_ADD_ON_6() (REG32(ADR_DIGITAL_ADD_ON_6)) = (0x00000000)
+#define DEF_RX_RC_VALUE_TUNE() (REG32(ADR_RX_RC_VALUE_TUNE)) = (0x00000000)
+#define DEF_TRX_IQ_COMP_2G() (REG32(ADR_TRX_IQ_COMP_2G)) = (0x00000000)
+#define DEF_TRX_IQ_COMP_5G_0() (REG32(ADR_TRX_IQ_COMP_5G_0)) = (0x00000000)
+#define DEF_TRX_IQ_COMP_5G_1() (REG32(ADR_TRX_IQ_COMP_5G_1)) = (0x00000000)
+#define DEF_TRX_IQ_COMP_5G_2() (REG32(ADR_TRX_IQ_COMP_5G_2)) = (0x00000000)
+#define DEF_TRX_IQ_COMP_5G_3() (REG32(ADR_TRX_IQ_COMP_5G_3)) = (0x00000000)
+#define DEF_RF_D_CAL_TOP_0() (REG32(ADR_RF_D_CAL_TOP_0)) = (0x00000000)
+#define DEF_RF_D_CAL_TOP_1() (REG32(ADR_RF_D_CAL_TOP_1)) = (0x00000000)
+#define DEF_RF_D_CAL_TOP_2() (REG32(ADR_RF_D_CAL_TOP_2)) = (0x08003800)
+#define DEF_RF_D_CAL_TOP_3() (REG32(ADR_RF_D_CAL_TOP_3)) = (0x03330333)
+#define DEF_RF_D_CAL_TOP_4() (REG32(ADR_RF_D_CAL_TOP_4)) = (0x70000000)
+#define DEF_RF_D_CAL_TOP_5() (REG32(ADR_RF_D_CAL_TOP_5)) = (0x00000000)
+#define DEF_RF_D_CAL_TOP_6() (REG32(ADR_RF_D_CAL_TOP_6)) = (0x00e500e5)
+#define DEF_RF_D_CAL_TOP_7() (REG32(ADR_RF_D_CAL_TOP_7)) = (0x00000000)
+#define DEF_RF_D_CAL_TOP_8() (REG32(ADR_RF_D_CAL_TOP_8)) = (0x00000000)
+#define DEF_RF_D_CAL_TOP_9() (REG32(ADR_RF_D_CAL_TOP_9)) = (0x00000044)
+#define DEF_HS3W_CTRL1() (REG32(ADR_HS3W_CTRL1)) = (0x00000000)
+#define DEF_HS3W_CTRL2() (REG32(ADR_HS3W_CTRL2)) = (0x00000000)
+#define DEF_HS3W_CTRL3() (REG32(ADR_HS3W_CTRL3)) = (0x60000000)
+#define DEF_RF_D_MODE_CTRL() (REG32(ADR_RF_D_MODE_CTRL)) = (0x00000000)
+#define DEF_HS3W_READ_OUT_1() (REG32(ADR_HS3W_READ_OUT_1)) = (0x00000000)
+#define DEF_HS3W_READ_OUT_2_() (REG32(ADR_HS3W_READ_OUT_2_)) = (0x00000000)
+#define DEF_HS3W_READ_OUT_3() (REG32(ADR_HS3W_READ_OUT_3)) = (0x00000000)
+#define DEF_SX_LOCK_FREQ_1() (REG32(ADR_SX_LOCK_FREQ_1)) = (0x00000000)
+#define DEF_SX_LOCK_FREQ_2() (REG32(ADR_SX_LOCK_FREQ_2)) = (0x00000000)
+#define DEF_RX_DC_CAL_RESULT() (REG32(ADR_RX_DC_CAL_RESULT)) = (0x00000000)
+#define DEF_AUDIO_CTRL_REG() (REG32(ADR_AUDIO_CTRL_REG)) = (0x00000000)
+#define DEF_AUDIO_PDM_REG() (REG32(ADR_AUDIO_PDM_REG)) = (0x08003800)
+#define DEF_RF_5G_TX_PARTITION_BAND1() (REG32(ADR_RF_5G_TX_PARTITION_BAND1)) = (0x13ec157c)
+#define DEF_RF_5G_TX_PARTITION_BAND2() (REG32(ADR_RF_5G_TX_PARTITION_BAND2)) = (0x00001644)
+#define DEF_WIFI_PADPD_5100_GAIN_REG0() (REG32(ADR_WIFI_PADPD_5100_GAIN_REG0)) = (0x02000200)
+#define DEF_WIFI_PADPD_5100_GAIN_REG1() (REG32(ADR_WIFI_PADPD_5100_GAIN_REG1)) = (0x02000200)
+#define DEF_WIFI_PADPD_5100_GAIN_REG2() (REG32(ADR_WIFI_PADPD_5100_GAIN_REG2)) = (0x02000200)
+#define DEF_WIFI_PADPD_5100_GAIN_REG3() (REG32(ADR_WIFI_PADPD_5100_GAIN_REG3)) = (0x02000200)
+#define DEF_WIFI_PADPD_5100_GAIN_REG4() (REG32(ADR_WIFI_PADPD_5100_GAIN_REG4)) = (0x02000200)
+#define DEF_WIFI_PADPD_5100_GAIN_REG5() (REG32(ADR_WIFI_PADPD_5100_GAIN_REG5)) = (0x02000200)
+#define DEF_WIFI_PADPD_5100_GAIN_REG6() (REG32(ADR_WIFI_PADPD_5100_GAIN_REG6)) = (0x02000200)
+#define DEF_WIFI_PADPD_5100_GAIN_REG7() (REG32(ADR_WIFI_PADPD_5100_GAIN_REG7)) = (0x02000200)
+#define DEF_WIFI_PADPD_5100_GAIN_REG8() (REG32(ADR_WIFI_PADPD_5100_GAIN_REG8)) = (0x02000200)
+#define DEF_WIFI_PADPD_5100_GAIN_REG9() (REG32(ADR_WIFI_PADPD_5100_GAIN_REG9)) = (0x02000200)
+#define DEF_WIFI_PADPD_5100_GAIN_REGA() (REG32(ADR_WIFI_PADPD_5100_GAIN_REGA)) = (0x02000200)
+#define DEF_WIFI_PADPD_5100_GAIN_REGB() (REG32(ADR_WIFI_PADPD_5100_GAIN_REGB)) = (0x02000200)
+#define DEF_WIFI_PADPD_5100_GAIN_REGC() (REG32(ADR_WIFI_PADPD_5100_GAIN_REGC)) = (0x02000200)
+#define DEF_WIFI_PADPD_5100_PHASE_REG0() (REG32(ADR_WIFI_PADPD_5100_PHASE_REG0)) = (0x00000000)
+#define DEF_WIFI_PADPD_5100_PHASE_REG1() (REG32(ADR_WIFI_PADPD_5100_PHASE_REG1)) = (0x00000000)
+#define DEF_WIFI_PADPD_5100_PHASE_REG2() (REG32(ADR_WIFI_PADPD_5100_PHASE_REG2)) = (0x00000000)
+#define DEF_WIFI_PADPD_5100_PHASE_REG3() (REG32(ADR_WIFI_PADPD_5100_PHASE_REG3)) = (0x00000000)
+#define DEF_WIFI_PADPD_5100_PHASE_REG4() (REG32(ADR_WIFI_PADPD_5100_PHASE_REG4)) = (0x00000000)
+#define DEF_WIFI_PADPD_5100_PHASE_REG5() (REG32(ADR_WIFI_PADPD_5100_PHASE_REG5)) = (0x00000000)
+#define DEF_WIFI_PADPD_5100_PHASE_REG6() (REG32(ADR_WIFI_PADPD_5100_PHASE_REG6)) = (0x00000000)
+#define DEF_WIFI_PADPD_5100_PHASE_REG7() (REG32(ADR_WIFI_PADPD_5100_PHASE_REG7)) = (0x00000000)
+#define DEF_WIFI_PADPD_5100_PHASE_REG8() (REG32(ADR_WIFI_PADPD_5100_PHASE_REG8)) = (0x00000000)
+#define DEF_WIFI_PADPD_5100_PHASE_REG9() (REG32(ADR_WIFI_PADPD_5100_PHASE_REG9)) = (0x00000000)
+#define DEF_WIFI_PADPD_5100_PHASE_REGA() (REG32(ADR_WIFI_PADPD_5100_PHASE_REGA)) = (0x00000000)
+#define DEF_WIFI_PADPD_5100_PHASE_REGB() (REG32(ADR_WIFI_PADPD_5100_PHASE_REGB)) = (0x00000000)
+#define DEF_WIFI_PADPD_5100_PHASE_REGC() (REG32(ADR_WIFI_PADPD_5100_PHASE_REGC)) = (0x00000000)
+#define DEF_WIFI_PADPD_5500_GAIN_REG0() (REG32(ADR_WIFI_PADPD_5500_GAIN_REG0)) = (0x02000200)
+#define DEF_WIFI_PADPD_5500_GAIN_REG1() (REG32(ADR_WIFI_PADPD_5500_GAIN_REG1)) = (0x02000200)
+#define DEF_WIFI_PADPD_5500_GAIN_REG2() (REG32(ADR_WIFI_PADPD_5500_GAIN_REG2)) = (0x02000200)
+#define DEF_WIFI_PADPD_5500_GAIN_REG3() (REG32(ADR_WIFI_PADPD_5500_GAIN_REG3)) = (0x02000200)
+#define DEF_WIFI_PADPD_5500_GAIN_REG4() (REG32(ADR_WIFI_PADPD_5500_GAIN_REG4)) = (0x02000200)
+#define DEF_WIFI_PADPD_5500_GAIN_REG5() (REG32(ADR_WIFI_PADPD_5500_GAIN_REG5)) = (0x02000200)
+#define DEF_WIFI_PADPD_5500_GAIN_REG6() (REG32(ADR_WIFI_PADPD_5500_GAIN_REG6)) = (0x02000200)
+#define DEF_WIFI_PADPD_5500_GAIN_REG7() (REG32(ADR_WIFI_PADPD_5500_GAIN_REG7)) = (0x02000200)
+#define DEF_WIFI_PADPD_5500_GAIN_REG8() (REG32(ADR_WIFI_PADPD_5500_GAIN_REG8)) = (0x02000200)
+#define DEF_WIFI_PADPD_5500_GAIN_REG9() (REG32(ADR_WIFI_PADPD_5500_GAIN_REG9)) = (0x02000200)
+#define DEF_WIFI_PADPD_5500_GAIN_REGA() (REG32(ADR_WIFI_PADPD_5500_GAIN_REGA)) = (0x02000200)
+#define DEF_WIFI_PADPD_5500_GAIN_REGB() (REG32(ADR_WIFI_PADPD_5500_GAIN_REGB)) = (0x02000200)
+#define DEF_WIFI_PADPD_5500_GAIN_REGC() (REG32(ADR_WIFI_PADPD_5500_GAIN_REGC)) = (0x02000200)
+#define DEF_WIFI_PADPD_5500_PHASE_REG0() (REG32(ADR_WIFI_PADPD_5500_PHASE_REG0)) = (0x00000000)
+#define DEF_WIFI_PADPD_5500_PHASE_REG1() (REG32(ADR_WIFI_PADPD_5500_PHASE_REG1)) = (0x00000000)
+#define DEF_WIFI_PADPD_5500_PHASE_REG2() (REG32(ADR_WIFI_PADPD_5500_PHASE_REG2)) = (0x00000000)
+#define DEF_WIFI_PADPD_5500_PHASE_REG3() (REG32(ADR_WIFI_PADPD_5500_PHASE_REG3)) = (0x00000000)
+#define DEF_WIFI_PADPD_5500_PHASE_REG4() (REG32(ADR_WIFI_PADPD_5500_PHASE_REG4)) = (0x00000000)
+#define DEF_WIFI_PADPD_5500_PHASE_REG5() (REG32(ADR_WIFI_PADPD_5500_PHASE_REG5)) = (0x00000000)
+#define DEF_WIFI_PADPD_5500_PHASE_REG6() (REG32(ADR_WIFI_PADPD_5500_PHASE_REG6)) = (0x00000000)
+#define DEF_WIFI_PADPD_5500_PHASE_REG7() (REG32(ADR_WIFI_PADPD_5500_PHASE_REG7)) = (0x00000000)
+#define DEF_WIFI_PADPD_5500_PHASE_REG8() (REG32(ADR_WIFI_PADPD_5500_PHASE_REG8)) = (0x00000000)
+#define DEF_WIFI_PADPD_5500_PHASE_REG9() (REG32(ADR_WIFI_PADPD_5500_PHASE_REG9)) = (0x00000000)
+#define DEF_WIFI_PADPD_5500_PHASE_REGA() (REG32(ADR_WIFI_PADPD_5500_PHASE_REGA)) = (0x00000000)
+#define DEF_WIFI_PADPD_5500_PHASE_REGB() (REG32(ADR_WIFI_PADPD_5500_PHASE_REGB)) = (0x00000000)
+#define DEF_WIFI_PADPD_5500_PHASE_REGC() (REG32(ADR_WIFI_PADPD_5500_PHASE_REGC)) = (0x00000000)
+#define DEF_WIFI_PADPD_5700_GAIN_REG0() (REG32(ADR_WIFI_PADPD_5700_GAIN_REG0)) = (0x02000200)
+#define DEF_WIFI_PADPD_5700_GAIN_REG1() (REG32(ADR_WIFI_PADPD_5700_GAIN_REG1)) = (0x02000200)
+#define DEF_WIFI_PADPD_5700_GAIN_REG2() (REG32(ADR_WIFI_PADPD_5700_GAIN_REG2)) = (0x02000200)
+#define DEF_WIFI_PADPD_5700_GAIN_REG3() (REG32(ADR_WIFI_PADPD_5700_GAIN_REG3)) = (0x02000200)
+#define DEF_WIFI_PADPD_5700_GAIN_REG4() (REG32(ADR_WIFI_PADPD_5700_GAIN_REG4)) = (0x02000200)
+#define DEF_WIFI_PADPD_5700_GAIN_REG5() (REG32(ADR_WIFI_PADPD_5700_GAIN_REG5)) = (0x02000200)
+#define DEF_WIFI_PADPD_5700_GAIN_REG6() (REG32(ADR_WIFI_PADPD_5700_GAIN_REG6)) = (0x02000200)
+#define DEF_WIFI_PADPD_5700_GAIN_REG7() (REG32(ADR_WIFI_PADPD_5700_GAIN_REG7)) = (0x02000200)
+#define DEF_WIFI_PADPD_5700_GAIN_REG8() (REG32(ADR_WIFI_PADPD_5700_GAIN_REG8)) = (0x02000200)
+#define DEF_WIFI_PADPD_5700_GAIN_REG9() (REG32(ADR_WIFI_PADPD_5700_GAIN_REG9)) = (0x02000200)
+#define DEF_WIFI_PADPD_5700_GAIN_REGA() (REG32(ADR_WIFI_PADPD_5700_GAIN_REGA)) = (0x02000200)
+#define DEF_WIFI_PADPD_5700_GAIN_REGB() (REG32(ADR_WIFI_PADPD_5700_GAIN_REGB)) = (0x02000200)
+#define DEF_WIFI_PADPD_5700_GAIN_REGC() (REG32(ADR_WIFI_PADPD_5700_GAIN_REGC)) = (0x02000200)
+#define DEF_WIFI_PADPD_5700_PHASE_REG0() (REG32(ADR_WIFI_PADPD_5700_PHASE_REG0)) = (0x00000000)
+#define DEF_WIFI_PADPD_5700_PHASE_REG1() (REG32(ADR_WIFI_PADPD_5700_PHASE_REG1)) = (0x00000000)
+#define DEF_WIFI_PADPD_5700_PHASE_REG2() (REG32(ADR_WIFI_PADPD_5700_PHASE_REG2)) = (0x00000000)
+#define DEF_WIFI_PADPD_5700_PHASE_REG3() (REG32(ADR_WIFI_PADPD_5700_PHASE_REG3)) = (0x00000000)
+#define DEF_WIFI_PADPD_5700_PHASE_REG4() (REG32(ADR_WIFI_PADPD_5700_PHASE_REG4)) = (0x00000000)
+#define DEF_WIFI_PADPD_5700_PHASE_REG5() (REG32(ADR_WIFI_PADPD_5700_PHASE_REG5)) = (0x00000000)
+#define DEF_WIFI_PADPD_5700_PHASE_REG6() (REG32(ADR_WIFI_PADPD_5700_PHASE_REG6)) = (0x00000000)
+#define DEF_WIFI_PADPD_5700_PHASE_REG7() (REG32(ADR_WIFI_PADPD_5700_PHASE_REG7)) = (0x00000000)
+#define DEF_WIFI_PADPD_5700_PHASE_REG8() (REG32(ADR_WIFI_PADPD_5700_PHASE_REG8)) = (0x00000000)
+#define DEF_WIFI_PADPD_5700_PHASE_REG9() (REG32(ADR_WIFI_PADPD_5700_PHASE_REG9)) = (0x00000000)
+#define DEF_WIFI_PADPD_5700_PHASE_REGA() (REG32(ADR_WIFI_PADPD_5700_PHASE_REGA)) = (0x00000000)
+#define DEF_WIFI_PADPD_5700_PHASE_REGB() (REG32(ADR_WIFI_PADPD_5700_PHASE_REGB)) = (0x00000000)
+#define DEF_WIFI_PADPD_5700_PHASE_REGC() (REG32(ADR_WIFI_PADPD_5700_PHASE_REGC)) = (0x00000000)
+#define DEF_WIFI_PADPD_5900_GAIN_REG0() (REG32(ADR_WIFI_PADPD_5900_GAIN_REG0)) = (0x02000200)
+#define DEF_WIFI_PADPD_5900_GAIN_REG1() (REG32(ADR_WIFI_PADPD_5900_GAIN_REG1)) = (0x02000200)
+#define DEF_WIFI_PADPD_5900_GAIN_REG2() (REG32(ADR_WIFI_PADPD_5900_GAIN_REG2)) = (0x02000200)
+#define DEF_WIFI_PADPD_5900_GAIN_REG3() (REG32(ADR_WIFI_PADPD_5900_GAIN_REG3)) = (0x02000200)
+#define DEF_WIFI_PADPD_5900_GAIN_REG4() (REG32(ADR_WIFI_PADPD_5900_GAIN_REG4)) = (0x02000200)
+#define DEF_WIFI_PADPD_5900_GAIN_REG5() (REG32(ADR_WIFI_PADPD_5900_GAIN_REG5)) = (0x02000200)
+#define DEF_WIFI_PADPD_5900_GAIN_REG6() (REG32(ADR_WIFI_PADPD_5900_GAIN_REG6)) = (0x02000200)
+#define DEF_WIFI_PADPD_5900_GAIN_REG7() (REG32(ADR_WIFI_PADPD_5900_GAIN_REG7)) = (0x02000200)
+#define DEF_WIFI_PADPD_5900_GAIN_REG8() (REG32(ADR_WIFI_PADPD_5900_GAIN_REG8)) = (0x02000200)
+#define DEF_WIFI_PADPD_5900_GAIN_REG9() (REG32(ADR_WIFI_PADPD_5900_GAIN_REG9)) = (0x02000200)
+#define DEF_WIFI_PADPD_5900_GAIN_REGA() (REG32(ADR_WIFI_PADPD_5900_GAIN_REGA)) = (0x02000200)
+#define DEF_WIFI_PADPD_5900_GAIN_REGB() (REG32(ADR_WIFI_PADPD_5900_GAIN_REGB)) = (0x02000200)
+#define DEF_WIFI_PADPD_5900_GAIN_REGC() (REG32(ADR_WIFI_PADPD_5900_GAIN_REGC)) = (0x02000200)
+#define DEF_WIFI_PADPD_5900_PHASE_REG0() (REG32(ADR_WIFI_PADPD_5900_PHASE_REG0)) = (0x00000000)
+#define DEF_WIFI_PADPD_5900_PHASE_REG1() (REG32(ADR_WIFI_PADPD_5900_PHASE_REG1)) = (0x00000000)
+#define DEF_WIFI_PADPD_5900_PHASE_REG2() (REG32(ADR_WIFI_PADPD_5900_PHASE_REG2)) = (0x00000000)
+#define DEF_WIFI_PADPD_5900_PHASE_REG3() (REG32(ADR_WIFI_PADPD_5900_PHASE_REG3)) = (0x00000000)
+#define DEF_WIFI_PADPD_5900_PHASE_REG4() (REG32(ADR_WIFI_PADPD_5900_PHASE_REG4)) = (0x00000000)
+#define DEF_WIFI_PADPD_5900_PHASE_REG5() (REG32(ADR_WIFI_PADPD_5900_PHASE_REG5)) = (0x00000000)
+#define DEF_WIFI_PADPD_5900_PHASE_REG6() (REG32(ADR_WIFI_PADPD_5900_PHASE_REG6)) = (0x00000000)
+#define DEF_WIFI_PADPD_5900_PHASE_REG7() (REG32(ADR_WIFI_PADPD_5900_PHASE_REG7)) = (0x00000000)
+#define DEF_WIFI_PADPD_5900_PHASE_REG8() (REG32(ADR_WIFI_PADPD_5900_PHASE_REG8)) = (0x00000000)
+#define DEF_WIFI_PADPD_5900_PHASE_REG9() (REG32(ADR_WIFI_PADPD_5900_PHASE_REG9)) = (0x00000000)
+#define DEF_WIFI_PADPD_5900_PHASE_REGA() (REG32(ADR_WIFI_PADPD_5900_PHASE_REGA)) = (0x00000000)
+#define DEF_WIFI_PADPD_5900_PHASE_REGB() (REG32(ADR_WIFI_PADPD_5900_PHASE_REGB)) = (0x00000000)
+#define DEF_WIFI_PADPD_5900_PHASE_REGC() (REG32(ADR_WIFI_PADPD_5900_PHASE_REGC)) = (0x00000000)
+#define DEF_WIFI_PADPD_CAL_TONEGEN_REG() (REG32(ADR_WIFI_PADPD_CAL_TONEGEN_REG)) = (0x00000000)
+#define DEF_WIFI_PADPD_CAL_RX_PADPD_REG() (REG32(ADR_WIFI_PADPD_CAL_RX_PADPD_REG)) = (0x00000000)
+#define DEF_WIFI_PADPD_CAL_RX_RO() (REG32(ADR_WIFI_PADPD_CAL_RX_RO)) = (0x00000000)
+#define DEF_WIFI_PADPD_CFR() (REG32(ADR_WIFI_PADPD_CFR)) = (0x02000200)
+#define DEF_WIFI_PADPD_DC_RM() (REG32(ADR_WIFI_PADPD_DC_RM)) = (0x00000000)
+#define DEF_WIFI_PADPD_TXIQ_CLIP_REG() (REG32(ADR_WIFI_PADPD_TXIQ_CLIP_REG)) = (0x02000200)
+#define DEF_WIFI_PADPD_TXIQ_CONTROL_REG() (REG32(ADR_WIFI_PADPD_TXIQ_CONTROL_REG)) = (0x00000080)
+#define DEF_WIFI_PADPD_TXIQ_DPD_DC_REG() (REG32(ADR_WIFI_PADPD_TXIQ_DPD_DC_REG)) = (0x00000000)
+#define DEF_WIFI_PADPD_TXIQ_DC_OFFSET_REG() (REG32(ADR_WIFI_PADPD_TXIQ_DC_OFFSET_REG)) = (0x00000000)
+#define DEF_WIFI_PADPD_2G_CONTROL_REG() (REG32(ADR_WIFI_PADPD_2G_CONTROL_REG)) = (0x00000000)
+#define DEF_WIFI_PADPD_2G_GAIN_REG0() (REG32(ADR_WIFI_PADPD_2G_GAIN_REG0)) = (0x02000200)
+#define DEF_WIFI_PADPD_2G_GAIN_REG1() (REG32(ADR_WIFI_PADPD_2G_GAIN_REG1)) = (0x02000200)
+#define DEF_WIFI_PADPD_2G_GAIN_REG2() (REG32(ADR_WIFI_PADPD_2G_GAIN_REG2)) = (0x02000200)
+#define DEF_WIFI_PADPD_2G_GAIN_REG3() (REG32(ADR_WIFI_PADPD_2G_GAIN_REG3)) = (0x02000200)
+#define DEF_WIFI_PADPD_2G_GAIN_REG4() (REG32(ADR_WIFI_PADPD_2G_GAIN_REG4)) = (0x02000200)
+#define DEF_WIFI_PADPD_2G_GAIN_REG5() (REG32(ADR_WIFI_PADPD_2G_GAIN_REG5)) = (0x02000200)
+#define DEF_WIFI_PADPD_2G_GAIN_REG6() (REG32(ADR_WIFI_PADPD_2G_GAIN_REG6)) = (0x02000200)
+#define DEF_WIFI_PADPD_2G_GAIN_REG7() (REG32(ADR_WIFI_PADPD_2G_GAIN_REG7)) = (0x02000200)
+#define DEF_WIFI_PADPD_2G_GAIN_REG8() (REG32(ADR_WIFI_PADPD_2G_GAIN_REG8)) = (0x02000200)
+#define DEF_WIFI_PADPD_2G_GAIN_REG9() (REG32(ADR_WIFI_PADPD_2G_GAIN_REG9)) = (0x02000200)
+#define DEF_WIFI_PADPD_2G_GAIN_REGA() (REG32(ADR_WIFI_PADPD_2G_GAIN_REGA)) = (0x02000200)
+#define DEF_WIFI_PADPD_2G_GAIN_REGB() (REG32(ADR_WIFI_PADPD_2G_GAIN_REGB)) = (0x02000200)
+#define DEF_WIFI_PADPD_2G_GAIN_REGC() (REG32(ADR_WIFI_PADPD_2G_GAIN_REGC)) = (0x02000200)
+#define DEF_WIFI_PADPD_2G_PHASE_REG0() (REG32(ADR_WIFI_PADPD_2G_PHASE_REG0)) = (0x00000000)
+#define DEF_WIFI_PADPD_2G_PHASE_REG1() (REG32(ADR_WIFI_PADPD_2G_PHASE_REG1)) = (0x00000000)
+#define DEF_WIFI_PADPD_2G_PHASE_REG2() (REG32(ADR_WIFI_PADPD_2G_PHASE_REG2)) = (0x00000000)
+#define DEF_WIFI_PADPD_2G_PHASE_REG3() (REG32(ADR_WIFI_PADPD_2G_PHASE_REG3)) = (0x00000000)
+#define DEF_WIFI_PADPD_2G_PHASE_REG4() (REG32(ADR_WIFI_PADPD_2G_PHASE_REG4)) = (0x00000000)
+#define DEF_WIFI_PADPD_2G_PHASE_REG5() (REG32(ADR_WIFI_PADPD_2G_PHASE_REG5)) = (0x00000000)
+#define DEF_WIFI_PADPD_2G_PHASE_REG6() (REG32(ADR_WIFI_PADPD_2G_PHASE_REG6)) = (0x00000000)
+#define DEF_WIFI_PADPD_2G_PHASE_REG7() (REG32(ADR_WIFI_PADPD_2G_PHASE_REG7)) = (0x00000000)
+#define DEF_WIFI_PADPD_2G_PHASE_REG8() (REG32(ADR_WIFI_PADPD_2G_PHASE_REG8)) = (0x00000000)
+#define DEF_WIFI_PADPD_2G_PHASE_REG9() (REG32(ADR_WIFI_PADPD_2G_PHASE_REG9)) = (0x00000000)
+#define DEF_WIFI_PADPD_2G_PHASE_REGA() (REG32(ADR_WIFI_PADPD_2G_PHASE_REGA)) = (0x00000000)
+#define DEF_WIFI_PADPD_2G_PHASE_REGB() (REG32(ADR_WIFI_PADPD_2G_PHASE_REGB)) = (0x00000000)
+#define DEF_WIFI_PADPD_2G_PHASE_REGC() (REG32(ADR_WIFI_PADPD_2G_PHASE_REGC)) = (0x00000000)
+#define DEF_WIFI_PADPD_5G_BB_GAIN_REG() (REG32(ADR_WIFI_PADPD_5G_BB_GAIN_REG)) = (0x80808080)
+#define DEF_WIFI_PADPD_2G_BB_GAIN_REG() (REG32(ADR_WIFI_PADPD_2G_BB_GAIN_REG)) = (0x00000080)
+#define DEF_WIFI_PADPD_TX_GAIN_0P5DB_REG() (REG32(ADR_WIFI_PADPD_TX_GAIN_0P5DB_REG)) = (0x79807980)
+#define DEF_HS5W_MD_EN() (REG32(ADR_HS5W_MD_EN)) = (0x00000001)
+#define DEF_HS5W_MAN() (REG32(ADR_HS5W_MAN)) = (0xfe000000)
+#define DEF_HS5W_MAN_SET_ADD0() (REG32(ADR_HS5W_MAN_SET_ADD0)) = (0x00000000)
+#define DEF_HS5W_MAN_SET_ADD1() (REG32(ADR_HS5W_MAN_SET_ADD1)) = (0x00000000)
+#define DEF_HS5W_MAN_SET_ADD2() (REG32(ADR_HS5W_MAN_SET_ADD2)) = (0x00000000)
+#define DEF_HS5W_MAN_SET_ADD3() (REG32(ADR_HS5W_MAN_SET_ADD3)) = (0x00000000)
+#define DEF_HS5W_MAN_SET_ADD4_CH() (REG32(ADR_HS5W_MAN_SET_ADD4_CH)) = (0x00000000)
+#define DEF_HS5W_MAN_SET_ADD4_CH_5GB() (REG32(ADR_HS5W_MAN_SET_ADD4_CH_5GB)) = (0x00000000)
+#define DEF_HS5W_MAN_SET_ADD4_F() (REG32(ADR_HS5W_MAN_SET_ADD4_F)) = (0x00000000)
+#define DEF_HS5W_MAN_SET_ADD4_F_5GB() (REG32(ADR_HS5W_MAN_SET_ADD4_F_5GB)) = (0x00000000)
+#define DEF_HS5W_MAN_SET_ADD5() (REG32(ADR_HS5W_MAN_SET_ADD5)) = (0x00000000)
+#define DEF_HS5W_MAN_SET_ADD5_5GB() (REG32(ADR_HS5W_MAN_SET_ADD5_5GB)) = (0x00000000)
+#define DEF_HS5W_MAN_SET_ADD6() (REG32(ADR_HS5W_MAN_SET_ADD6)) = (0x00000000)
+#define DEF_WIFI_PADPD_RESERVED_REG() (REG32(ADR_WIFI_PADPD_RESERVED_REG)) = (0x00000000)
+#define DEF_PMU_REG_1() (REG32(ADR_PMU_REG_1)) = (0x25008014)
+#define DEF_PMU_REG_2() (REG32(ADR_PMU_REG_2)) = (0x251a8820)
+#define DEF_PMU_REG_3() (REG32(ADR_PMU_REG_3)) = (0x486041be)
+#define DEF_PMU_REG_4() (REG32(ADR_PMU_REG_4)) = (0x95d98900)
+#define DEF_PMU_REG_5() (REG32(ADR_PMU_REG_5)) = (0xaaaaaaa8)
+#define DEF_PMU_REG_6() (REG32(ADR_PMU_REG_6)) = (0x00000000)
+#define DEF_PMU_SLEEP_REG_1() (REG32(ADR_PMU_SLEEP_REG_1)) = (0x00000000)
+#define DEF_PMU_SLEEP_REG_2() (REG32(ADR_PMU_SLEEP_REG_2)) = (0x00000040)
+#define DEF_PMU_RTC_REG_0() (REG32(ADR_PMU_RTC_REG_0)) = (0x00007d00)
+#define DEF_PMU_RTC_REG_1() (REG32(ADR_PMU_RTC_REG_1)) = (0x00000003)
+#define DEF_PMU_RTC_REG_2() (REG32(ADR_PMU_RTC_REG_2)) = (0x00000000)
+#define DEF_PMU_RTC_REG_3() (REG32(ADR_PMU_RTC_REG_3)) = (0x00000000)
+#define DEF_PMU_CTRL_REG() (REG32(ADR_PMU_CTRL_REG)) = (0x00000010)
+#define DEF_PMU_STATE_REG() (REG32(ADR_PMU_STATE_REG)) = (0x00000000)
+#define DEF_PMU_DPLL_REG_0() (REG32(ADR_PMU_DPLL_REG_0)) = (0x0002ffa4)
+#define DEF_PMU_DPLL_REG_1() (REG32(ADR_PMU_DPLL_REG_1)) = (0x00180f20)
+#define DEF_PMU_DPLL_REG_2() (REG32(ADR_PMU_DPLL_REG_2)) = (0x021c89ac)
+#define DEF_PMU_DPLL_REG_3() (REG32(ADR_PMU_DPLL_REG_3)) = (0x24ec4ec5)
+#define DEF_PMU_SLEEP_MODE_REG() (REG32(ADR_PMU_SLEEP_MODE_REG)) = (0x010080be)
+#define DEF_PMU_RAM_00() (REG32(ADR_PMU_RAM_00)) = (0x00000000)
+#define DEF_PMU_RAM_01() (REG32(ADR_PMU_RAM_01)) = (0x00000000)
+#define DEF_PMU_RAM_02() (REG32(ADR_PMU_RAM_02)) = (0x00000000)
+#define DEF_PMU_RAM_03() (REG32(ADR_PMU_RAM_03)) = (0x00000000)
+#define DEF_PMU_RAM_04() (REG32(ADR_PMU_RAM_04)) = (0x00000000)
+#define DEF_PMU_RAM_05() (REG32(ADR_PMU_RAM_05)) = (0x00000000)
+#define DEF_PMU_RAM_06() (REG32(ADR_PMU_RAM_06)) = (0x00000000)
+#define DEF_PMU_RAM_07() (REG32(ADR_PMU_RAM_07)) = (0x00000000)
+#define DEF_PMU_RAM_08() (REG32(ADR_PMU_RAM_08)) = (0x00000000)
+#define DEF_PMU_RAM_09() (REG32(ADR_PMU_RAM_09)) = (0x00000000)
+#define DEF_PMU_RAM_10() (REG32(ADR_PMU_RAM_10)) = (0x00000000)
+#define DEF_PMU_RAM_11() (REG32(ADR_PMU_RAM_11)) = (0x00000000)
+#define DEF_PMU_RAM_12() (REG32(ADR_PMU_RAM_12)) = (0x00000000)
+#define DEF_PMU_RAM_13() (REG32(ADR_PMU_RAM_13)) = (0x00000000)
+#define DEF_PMU_RAM_14() (REG32(ADR_PMU_RAM_14)) = (0x00000000)
+#define DEF_PMU_RAM_15() (REG32(ADR_PMU_RAM_15)) = (0x00000000)
+#define DEF_WIFI_PHY_COMMON_SYS_REG() (REG32(ADR_WIFI_PHY_COMMON_SYS_REG)) = (0x00000010)
+#define DEF_WIFI_PHY_COMMON_ENABLE_REG() (REG32(ADR_WIFI_PHY_COMMON_ENABLE_REG)) = (0x00000000)
+#define DEF_WIFI_PHY_COMMON_VERSION_REG() (REG32(ADR_WIFI_PHY_COMMON_VERSION_REG)) = (0x00000000)
+#define DEF_WIFI_PHY_COMMON_DES_REG0() (REG32(ADR_WIFI_PHY_COMMON_DES_REG0)) = (0x00000064)
+#define DEF_WIFI_PHY_COMMON_DES_REG1() (REG32(ADR_WIFI_PHY_COMMON_DES_REG1)) = (0x00000fff)
+#define DEF_WIFI_PHY_COMMON_DES_REG2() (REG32(ADR_WIFI_PHY_COMMON_DES_REG2)) = (0x00807f03)
+#define DEF_WIFI_PHY_COMMON_DES_REG3() (REG32(ADR_WIFI_PHY_COMMON_DES_REG3)) = (0x0069023c)
+#define DEF_WIFI_PHY_COMMON_DES_REG4() (REG32(ADR_WIFI_PHY_COMMON_DES_REG4)) = (0x00000001)
+#define DEF_WIFI_PHY_COMMON_TX_CONTROL() (REG32(ADR_WIFI_PHY_COMMON_TX_CONTROL)) = (0x00000000)
+#define DEF_WIFI_PHY_COMMON_DES_REG5() (REG32(ADR_WIFI_PHY_COMMON_DES_REG5)) = (0x00000000)
+#define DEF_WIFI_PHY_COMMON_DES_REG6() (REG32(ADR_WIFI_PHY_COMMON_DES_REG6)) = (0x00000000)
+#define DEF_WIFI_PHY_COMMON_RFAGC_REG0() (REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG0)) = (0x80046771)
+#define DEF_WIFI_PHY_COMMON_RFAGC_REG1() (REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG1)) = (0x80046771)
+#define DEF_WIFI_PHY_COMMON_RFAGC_REG2() (REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG2)) = (0x1f300f6f)
+#define DEF_WIFI_PHY_COMMON_RFAGC_REG3() (REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG3)) = (0x663f36d0)
+#define DEF_WIFI_PHY_COMMON_RFAGC_REG4() (REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG4)) = (0x100c0000)
+#define DEF_WIFI_PHY_COMMON_11B_DAGC_REG0() (REG32(ADR_WIFI_PHY_COMMON_11B_DAGC_REG0)) = (0x01603fff)
+#define DEF_WIFI_PHY_COMMON_11B_DAGC_REG1() (REG32(ADR_WIFI_PHY_COMMON_11B_DAGC_REG1)) = (0x00080860)
+#define DEF_WIFI_PHY_COMMON_11GN20_DAGC_REG0() (REG32(ADR_WIFI_PHY_COMMON_11GN20_DAGC_REG0)) = (0xff000160)
+#define DEF_WIFI_PHY_COMMON_11GN20_DAGC_REG1() (REG32(ADR_WIFI_PHY_COMMON_11GN20_DAGC_REG1)) = (0x00100040)
+#define DEF_WIFI_PHY_COMMON_11BGN_DIGPWR_REG() (REG32(ADR_WIFI_PHY_COMMON_11BGN_DIGPWR_REG)) = (0x00000000)
+#define DEF_WIFI_PHY_COMMON_RFAGC_RO00() (REG32(ADR_WIFI_PHY_COMMON_RFAGC_RO00)) = (0x00000000)
+#define DEF_WIFI_PHY_COMMON_RFAGC_RO01() (REG32(ADR_WIFI_PHY_COMMON_RFAGC_RO01)) = (0x00000000)
+#define DEF_WIFI_PHY_COMMON_RFAGC_RO02() (REG32(ADR_WIFI_PHY_COMMON_RFAGC_RO02)) = (0x00000000)
+#define DEF_WIFI_PHY_COMMON_RXDC() (REG32(ADR_WIFI_PHY_COMMON_RXDC)) = (0x12301230)
+#define DEF_WIFI_PHY_COMMON_RXDC_RO() (REG32(ADR_WIFI_PHY_COMMON_RXDC_RO)) = (0x00000000)
+#define DEF_WIFI_PHY_COMMON_RSSI_TBUS_REG() (REG32(ADR_WIFI_PHY_COMMON_RSSI_TBUS_REG)) = (0x00fc000f)
+#define DEF_WIFI_PHY_COMMON_RX_EN_CNT_REG() (REG32(ADR_WIFI_PHY_COMMON_RX_EN_CNT_REG)) = (0x00000000)
+#define DEF_WIFI_PHY_COMMON_EDCCA_0() (REG32(ADR_WIFI_PHY_COMMON_EDCCA_0)) = (0x00000004)
+#define DEF_WIFI_PHY_COMMON_EDCCA_1() (REG32(ADR_WIFI_PHY_COMMON_EDCCA_1)) = (0x00000000)
+#define DEF_WIFI_PHY_COMMON_EDCCA_2() (REG32(ADR_WIFI_PHY_COMMON_EDCCA_2)) = (0x00000000)
+#define DEF_WIFI_PHY_AGC_RELOCK_1() (REG32(ADR_WIFI_PHY_AGC_RELOCK_1)) = (0x00102000)
+#define DEF_WIFI_PHY_AGC_RELOCK_2() (REG32(ADR_WIFI_PHY_AGC_RELOCK_2)) = (0x00100018)
+#define DEF_WIFI_PHY_COMMON_TX_LENGTH_CNT_REG0() (REG32(ADR_WIFI_PHY_COMMON_TX_LENGTH_CNT_REG0)) = (0x00000000)
+#define DEF_WIFI_PHY_COMMON_TX_LENGTH_CNT_REG1() (REG32(ADR_WIFI_PHY_COMMON_TX_LENGTH_CNT_REG1)) = (0x00000000)
+#define DEF_WIFI_PHY_COMMON_RX_LENGTH_CNT_REG0() (REG32(ADR_WIFI_PHY_COMMON_RX_LENGTH_CNT_REG0)) = (0x00000000)
+#define DEF_WIFI_PHY_COMMON_RX_LENGTH_CNT_REG1() (REG32(ADR_WIFI_PHY_COMMON_RX_LENGTH_CNT_REG1)) = (0x00000000)
+#define DEF_WIFI_PHY_COMMON_TX_LENGTH_CNT_RO() (REG32(ADR_WIFI_PHY_COMMON_TX_LENGTH_CNT_RO)) = (0x00000000)
+#define DEF_WIFI_PHY_COMMON_RX_LENGTH_CNT_RO() (REG32(ADR_WIFI_PHY_COMMON_RX_LENGTH_CNT_RO)) = (0x00000000)
+#define DEF_WIFI_PHY_COMMON_TRX_TYPE_CNT_REG() (REG32(ADR_WIFI_PHY_COMMON_TRX_TYPE_CNT_REG)) = (0x0cff0cff)
+#define DEF_WIFI_PHY_COMMON_TRX_TYPE_CNT_RO() (REG32(ADR_WIFI_PHY_COMMON_TRX_TYPE_CNT_RO)) = (0x00000000)
+#define DEF_WIFI_PHY_COMMON_11GN40_DAGC_REG0() (REG32(ADR_WIFI_PHY_COMMON_11GN40_DAGC_REG0)) = (0x00000160)
+#define DEF_WIFI_PHY_COMMON_11GN40_DAGC_REG1() (REG32(ADR_WIFI_PHY_COMMON_11GN40_DAGC_REG1)) = (0x00100040)
+#define DEF_WIFI_PHY_COMMON_11GN_DAGC_INI_REG() (REG32(ADR_WIFI_PHY_COMMON_11GN_DAGC_INI_REG)) = (0x00100010)
+#define DEF_WIFI_PHY_COMMON_MAC_PKT_REG_0() (REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_0)) = (0x00000000)
+#define DEF_WIFI_PHY_COMMON_MAC_PKT_REG_1() (REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_1)) = (0x00000000)
+#define DEF_WIFI_PHY_COMMON_MAC_PKT_REG_2() (REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_2)) = (0x00000000)
+#define DEF_WIFI_PHY_COMMON_MAC_PKT_REG_3() (REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_3)) = (0x00000000)
+#define DEF_WIFI_PHY_COMMON_MAC_PKT_REG_4() (REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_4)) = (0x00000000)
+#define DEF_WIFI_PHY_COMMON_MAC_PKT_REG_5() (REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_5)) = (0x00000000)
+#define DEF_WIFI_PHY_COMMON_MAC_PKT_REG_6() (REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_6)) = (0x00000000)
+#define DEF_WIFI_PHY_COMMON_MAC_PKT_REG_7() (REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_7)) = (0x00000000)
+#define DEF_WIFI_PHY_COMMON_MAC_PKT_REG_8() (REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_8)) = (0x00000000)
+#define DEF_WIFI_PHY_COMMON_MAC_PKT_REG_9() (REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_9)) = (0x00000000)
+#define DEF_WIFI_PHY_COMMON_MAC_PKT_REG_A() (REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_A)) = (0x00000000)
+#define DEF_WIFI_PHY_COMMON_BB_SCALE_REG_0() (REG32(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_0)) = (0x00000080)
+#define DEF_WIFI_PHY_COMMON_BB_SCALE_REG_1() (REG32(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_1)) = (0x80808080)
+#define DEF_WIFI_PHY_COMMON_BB_SCALE_REG_2() (REG32(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_2)) = (0x80808080)
+#define DEF_WIFI_PHY_COMMON_BB_SCALE_REG_3() (REG32(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_3)) = (0x80808080)
+#define DEF_WIFI_PHY_COMMON_RF_PWR_REG_0() (REG32(ADR_WIFI_PHY_COMMON_RF_PWR_REG_0)) = (0x0000007f)
+#define DEF_WIFI_PHY_COMMON_RF_PWR_REG_1() (REG32(ADR_WIFI_PHY_COMMON_RF_PWR_REG_1)) = (0x7f7f7f7f)
+#define DEF_WIFI_PHY_COMMON_RF_PWR_REG_2() (REG32(ADR_WIFI_PHY_COMMON_RF_PWR_REG_2)) = (0x7f7f7f7f)
+#define DEF_WIFI_PHY_COMMON_RF_PWR_REG_3() (REG32(ADR_WIFI_PHY_COMMON_RF_PWR_REG_3)) = (0x7f7f7f7f)
+#define DEF_WIFI_PHY_COMMON_RX_MON_0() (REG32(ADR_WIFI_PHY_COMMON_RX_MON_0)) = (0x03e83ffe)
+#define DEF_WIFI_PHY_COMMON_RX_MON_1() (REG32(ADR_WIFI_PHY_COMMON_RX_MON_1)) = (0x00640005)
+#define DEF_WIFI_PHY_COMMON_RX_MON_2() (REG32(ADR_WIFI_PHY_COMMON_RX_MON_2)) = (0x00000000)
+#define DEF_WIFI_PHY_COMMON_RX_MON_3() (REG32(ADR_WIFI_PHY_COMMON_RX_MON_3)) = (0x00000000)
+#define DEF_WIFI_PHY_COMMON_RX_MON_4() (REG32(ADR_WIFI_PHY_COMMON_RX_MON_4)) = (0x00000000)
+#define DEF_WIFI_PHY_COMMON_RX_MON_5() (REG32(ADR_WIFI_PHY_COMMON_RX_MON_5)) = (0x00000000)
+#define DEF_WIFI_PHY_COMMON_RX_MON_6() (REG32(ADR_WIFI_PHY_COMMON_RX_MON_6)) = (0x00000000)
+#define DEF_WIFI_PHY_COMMON_RX_MON_7() (REG32(ADR_WIFI_PHY_COMMON_RX_MON_7)) = (0x00000000)
+#define DEF_WIFI_PHY_COMMON_RX_MON_8() (REG32(ADR_WIFI_PHY_COMMON_RX_MON_8)) = (0x00000000)
+#define DEF_WIFI_PHY_COMMON_RX_TMR_MON_RO() (REG32(ADR_WIFI_PHY_COMMON_RX_TMR_MON_RO)) = (0x00000000)
+#define DEF_WIFI_PHY_COMMON_RX_BKN_MON_RO() (REG32(ADR_WIFI_PHY_COMMON_RX_BKN_MON_RO)) = (0x00000000)
+#define DEF_WIFI_PHY_COMMON_MAC_IF_CNT_CTRL() (REG32(ADR_WIFI_PHY_COMMON_MAC_IF_CNT_CTRL)) = (0x00000000)
+#define DEF_WIFI_PHY_COMMON_MAC_IF_CNT_RO() (REG32(ADR_WIFI_PHY_COMMON_MAC_IF_CNT_RO)) = (0x00000000)
+#define DEF_WIFI_PHY_COMMON_RX_FFT_MEM_BIST_REG() (REG32(ADR_WIFI_PHY_COMMON_RX_FFT_MEM_BIST_REG)) = (0x00000000)
+#define DEF_WIFI_PHY_AUDIO_CLK_CTRL() (REG32(ADR_WIFI_PHY_AUDIO_CLK_CTRL)) = (0x00000000)
+#define DEF_WIFI_PHY_COMMON_TOP_STATUS_RO() (REG32(ADR_WIFI_PHY_COMMON_TOP_STATUS_RO)) = (0x00000000)
+#define DEF_WIFI_PHY_COMMON_RESERVED_REG() (REG32(ADR_WIFI_PHY_COMMON_RESERVED_REG)) = (0x00000000)
+#define DEF_WIFI_11B_TX_BB_RAMP_REG() (REG32(ADR_WIFI_11B_TX_BB_RAMP_REG)) = (0x00003c40)
+#define DEF_WIFI_11B_TX_PKT_CNT_SENT_REG() (REG32(ADR_WIFI_11B_TX_PKT_CNT_SENT_REG)) = (0x00000000)
+#define DEF_WIFI_11B_TX_DEBUG_SEL_REG() (REG32(ADR_WIFI_11B_TX_DEBUG_SEL_REG)) = (0x00000000)
+#define DEF_WIFI_11B_TX_RESERVED_REG() (REG32(ADR_WIFI_11B_TX_RESERVED_REG)) = (0x00000000)
+#define DEF_WIFI_11B_RX_REG_000() (REG32(ADR_WIFI_11B_RX_REG_000)) = (0x00000244)
+#define DEF_WIFI_11B_RX_REG_001() (REG32(ADR_WIFI_11B_RX_REG_001)) = (0x00040000)
+#define DEF_WIFI_11B_RX_REG_002() (REG32(ADR_WIFI_11B_RX_REG_002)) = (0x00400040)
+#define DEF_WIFI_11B_RX_REG_003() (REG32(ADR_WIFI_11B_RX_REG_003)) = (0x00003467)
+#define DEF_WIFI_11B_RX_REG_004() (REG32(ADR_WIFI_11B_RX_REG_004)) = (0x00550000)
+#define DEF_WIFI_11B_RX_REG_005() (REG32(ADR_WIFI_11B_RX_REG_005)) = (0x20000015)
+#define DEF_WIFI_11B_RX_REG_006() (REG32(ADR_WIFI_11B_RX_REG_006)) = (0x00390002)
+#define DEF_WIFI_11B_RX_REG_007() (REG32(ADR_WIFI_11B_RX_REG_007)) = (0x03030004)
+#define DEF_WIFI_11B_RX_REG_008() (REG32(ADR_WIFI_11B_RX_REG_008)) = (0x00350046)
+#define DEF_WIFI_11B_RX_REG_009() (REG32(ADR_WIFI_11B_RX_REG_009)) = (0x00350046)
+#define DEF_WIFI_11B_RX_REG_010() (REG32(ADR_WIFI_11B_RX_REG_010)) = (0x00236700)
+#define DEF_WIFI_11B_RX_REG_011() (REG32(ADR_WIFI_11B_RX_REG_011)) = (0x000d1746)
+#define DEF_WIFI_11B_RX_REG_012() (REG32(ADR_WIFI_11B_RX_REG_012)) = (0x04061787)
+#define DEF_WIFI_11B_RX_REG_013() (REG32(ADR_WIFI_11B_RX_REG_013)) = (0x07800000)
+#define DEF_WIFI_11B_RX_REG_014() (REG32(ADR_WIFI_11B_RX_REG_014)) = (0x00000067)
+#define DEF_WIFI_11B_RX_REG_039() (REG32(ADR_WIFI_11B_RX_REG_039)) = (0x00c0000a)
+#define DEF_WIFI_11B_RX_REG_040() (REG32(ADR_WIFI_11B_RX_REG_040)) = (0x00000000)
+#define DEF_WIFI_11B_RX_REG_041() (REG32(ADR_WIFI_11B_RX_REG_041)) = (0x00000006)
+#define DEF_WIFI_11B_RX_REG_240() (REG32(ADR_WIFI_11B_RX_REG_240)) = (0x00000000)
+#define DEF_WIFI_11B_RX_REG_241() (REG32(ADR_WIFI_11B_RX_REG_241)) = (0x00000f10)
+#define DEF_WIFI_11B_RX_REG_244() (REG32(ADR_WIFI_11B_RX_REG_244)) = (0x00000000)
+#define DEF_WIFI_11B_RX_REG_245() (REG32(ADR_WIFI_11B_RX_REG_245)) = (0x00000000)
+#define DEF_WIFI_11B_RX_REG_246() (REG32(ADR_WIFI_11B_RX_REG_246)) = (0x00000000)
+#define DEF_WIFI_11B_RX_REG_249() (REG32(ADR_WIFI_11B_RX_REG_249)) = (0x00000000)
+#define DEF_WIFI_11B_RX_REG_250() (REG32(ADR_WIFI_11B_RX_REG_250)) = (0x00000000)
+#define DEF_WIFI_11B_RX_REG_251() (REG32(ADR_WIFI_11B_RX_REG_251)) = (0x00000000)
+#define DEF_WIFI_11B_RX_REG_252() (REG32(ADR_WIFI_11B_RX_REG_252)) = (0x00000000)
+#define DEF_WIFI_11B_RX_REG_253() (REG32(ADR_WIFI_11B_RX_REG_253)) = (0x00000000)
+#define DEF_WIFI_11B_RX_REG_254() (REG32(ADR_WIFI_11B_RX_REG_254)) = (0x00100000)
+#define DEF_WIFI_11B_RX_REG_255() (REG32(ADR_WIFI_11B_RX_REG_255)) = (0x00000001)
+#define DEF_WIFI_11GN_TX_MEM_BIST_REG() (REG32(ADR_WIFI_11GN_TX_MEM_BIST_REG)) = (0x00000000)
+#define DEF_WIFI_11GN_TX_BB_RAMP_REG() (REG32(ADR_WIFI_11GN_TX_BB_RAMP_REG)) = (0x0000233c)
+#define DEF_WIFI_11GN_TX_CONTROL_REG() (REG32(ADR_WIFI_11GN_TX_CONTROL_REG)) = (0x00000011)
+#define DEF_WIFI_11GN_TX_STS_SCALE_REG() (REG32(ADR_WIFI_11GN_TX_STS_SCALE_REG)) = (0x01b001b0)
+#define DEF_WIFI_11GN_TX_FFT_SCALE_REG0() (REG32(ADR_WIFI_11GN_TX_FFT_SCALE_REG0)) = (0x0096009d)
+#define DEF_WIFI_11GN_TX_FFT_SCALE_REG1() (REG32(ADR_WIFI_11GN_TX_FFT_SCALE_REG1)) = (0x7f0c50cc)
+#define DEF_WIFI_11GN_TX_PKT_CNT_SENT_REG() (REG32(ADR_WIFI_11GN_TX_PKT_CNT_SENT_REG)) = (0x00000000)
+#define DEF_WIFI_11GN_TX_DEBUG_SEL_REG() (REG32(ADR_WIFI_11GN_TX_DEBUG_SEL_REG)) = (0x00000000)
+#define DEF_WIFI_11GN_TX_RESERVED_REG() (REG32(ADR_WIFI_11GN_TX_RESERVED_REG)) = (0x00000000)
+#define DEF_WIFI_11GN_RX_REG_000() (REG32(ADR_WIFI_11GN_RX_REG_000)) = (0x00000044)
+#define DEF_WIFI_11GN_RX_REG_001() (REG32(ADR_WIFI_11GN_RX_REG_001)) = (0x00000000)
+#define DEF_WIFI_11GN_RX_REG_002() (REG32(ADR_WIFI_11GN_RX_REG_002)) = (0x00004775)
+#define DEF_WIFI_11GN_RX_REG_003() (REG32(ADR_WIFI_11GN_RX_REG_003)) = (0x10000075)
+#define DEF_WIFI_11GN_RX_REG_004_() (REG32(ADR_WIFI_11GN_RX_REG_004_)) = (0x38324705)
+#define DEF_WIFI_11GN_RX_REG_005() (REG32(ADR_WIFI_11GN_RX_REG_005)) = (0x30182000)
+#define DEF_WIFI_11GN_RX_REG_006_() (REG32(ADR_WIFI_11GN_RX_REG_006_)) = (0x20600000)
+#define DEF_WIFI_11GN_RX_REG_007_() (REG32(ADR_WIFI_11GN_RX_REG_007_)) = (0x0a010080)
+#define DEF_WIFI_11GN_RX_REG_008() (REG32(ADR_WIFI_11GN_RX_REG_008)) = (0x50505050)
+#define DEF_WIFI_11GN_RX_REG_009() (REG32(ADR_WIFI_11GN_RX_REG_009)) = (0x50000000)
+#define DEF_WIFI_11GN_RX_REG_010_() (REG32(ADR_WIFI_11GN_RX_REG_010_)) = (0x50505050)
+#define DEF_WIFI_11GN_RX_REG_011() (REG32(ADR_WIFI_11GN_RX_REG_011)) = (0x50505050)
+#define DEF_WIFI_11GN_RX_REG_012() (REG32(ADR_WIFI_11GN_RX_REG_012)) = (0x50000000)
+#define DEF_WIFI_11GN_RX_REG_013() (REG32(ADR_WIFI_11GN_RX_REG_013)) = (0x00000000)
+#define DEF_WIFI_11GN_RX_REG_014() (REG32(ADR_WIFI_11GN_RX_REG_014)) = (0x00001420)
+#define DEF_WIFI_11GN_RX_REG_015() (REG32(ADR_WIFI_11GN_RX_REG_015)) = (0x00000040)
+#define DEF_WIFI_11GN_RX_REG_016() (REG32(ADR_WIFI_11GN_RX_REG_016)) = (0x7f7f7f7f)
+#define DEF_WIFI_11GN_RX_REG_017() (REG32(ADR_WIFI_11GN_RX_REG_017)) = (0x7f7f7f7f)
+#define DEF_WIFI_11GN_RX_REG_032() (REG32(ADR_WIFI_11GN_RX_REG_032)) = (0x00000000)
+#define DEF_WIFI_11GN_RX_REG_033() (REG32(ADR_WIFI_11GN_RX_REG_033)) = (0x00000000)
+#define DEF_WIFI_11GN_RX_REG_039() (REG32(ADR_WIFI_11GN_RX_REG_039)) = (0x0000200a)
+#define DEF_WIFI_11GN_RX_REG_040() (REG32(ADR_WIFI_11GN_RX_REG_040)) = (0x00000280)
+#define DEF_WIFI_11GN_RX_REG_048() (REG32(ADR_WIFI_11GN_RX_REG_048)) = (0x30000280)
+#define DEF_WIFI_11GN_RX_REG_049() (REG32(ADR_WIFI_11GN_RX_REG_049)) = (0x30023002)
+#define DEF_WIFI_11GN_RX_REG_050() (REG32(ADR_WIFI_11GN_RX_REG_050)) = (0x0000003a)
+#define DEF_WIFI_11GN_RX_REG_051() (REG32(ADR_WIFI_11GN_RX_REG_051)) = (0x00200120)
+#define DEF_WIFI_11GN_RX_REG_052() (REG32(ADR_WIFI_11GN_RX_REG_052)) = (0x00000120)
+#define DEF_WIFI_11GN_RX_REG_076() (REG32(ADR_WIFI_11GN_RX_REG_076)) = (0x40000000)
+#define DEF_WIFI_11GN_RX_REG_087() (REG32(ADR_WIFI_11GN_RX_REG_087)) = (0x01080110)
+#define DEF_WIFI_11GN_RX_REG_088() (REG32(ADR_WIFI_11GN_RX_REG_088)) = (0x00180120)
+#define DEF_WIFI_11GN_RX_REG_089() (REG32(ADR_WIFI_11GN_RX_REG_089)) = (0x00000000)
+#define DEF_WIFI_11GN_RX_REG_096() (REG32(ADR_WIFI_11GN_RX_REG_096)) = (0x00000000)
+#define DEF_WIFI_11GN_RX_REG_098() (REG32(ADR_WIFI_11GN_RX_REG_098)) = (0x02000000)
+#define DEF_WIFI_11GN_RX_REG_100() (REG32(ADR_WIFI_11GN_RX_REG_100)) = (0x02003030)
+#define DEF_WIFI_11GN_RX_REG_101() (REG32(ADR_WIFI_11GN_RX_REG_101)) = (0x09360000)
+#define DEF_WIFI_11GN_RX_REG_102() (REG32(ADR_WIFI_11GN_RX_REG_102)) = (0xff0cfc8c)
+#define DEF_WIFI_11GN_RX_REG_103() (REG32(ADR_WIFI_11GN_RX_REG_103)) = (0x0000fb88)
+#define DEF_WIFI_11GN_RX_REG_241() (REG32(ADR_WIFI_11GN_RX_REG_241)) = (0x00000f10)
+#define DEF_WIFI_11GN_RX_REG_244() (REG32(ADR_WIFI_11GN_RX_REG_244)) = (0x00000000)
+#define DEF_WIFI_11GN_RX_REG_245() (REG32(ADR_WIFI_11GN_RX_REG_245)) = (0x00000000)
+#define DEF_WIFI_11GN_RX_REG_246() (REG32(ADR_WIFI_11GN_RX_REG_246)) = (0x00000000)
+#define DEF_WIFI_11GN_RX_REG_247() (REG32(ADR_WIFI_11GN_RX_REG_247)) = (0x00000000)
+#define DEF_WIFI_11GN_RX_REG_248() (REG32(ADR_WIFI_11GN_RX_REG_248)) = (0x00000000)
+#define DEF_WIFI_11GN_RX_REG_249() (REG32(ADR_WIFI_11GN_RX_REG_249)) = (0x00000000)
+#define DEF_WIFI_11GN_RX_REG_250() (REG32(ADR_WIFI_11GN_RX_REG_250)) = (0x00000000)
+#define DEF_WIFI_11GN_RX_REG_251() (REG32(ADR_WIFI_11GN_RX_REG_251)) = (0x00000000)
+#define DEF_WIFI_11GN_RX_REG_252() (REG32(ADR_WIFI_11GN_RX_REG_252)) = (0x00000000)
+#define DEF_WIFI_11GN_RX_REG_253() (REG32(ADR_WIFI_11GN_RX_REG_253)) = (0x00000000)
+#define DEF_WIFI_11GN_RX_REG_254() (REG32(ADR_WIFI_11GN_RX_REG_254)) = (0x00100001)
+#define DEF_WIFI_11GN_RX_REG_255() (REG32(ADR_WIFI_11GN_RX_REG_255)) = (0x00000001)
+#define DEF_WIFI_RADAR_REG_00() (REG32(ADR_WIFI_RADAR_REG_00)) = (0x4d4d0d0a)
+#define DEF_WIFI_RADAR_REG_01() (REG32(ADR_WIFI_RADAR_REG_01)) = (0x07ee0007)
+#define DEF_WIFI_RADAR_REG_02() (REG32(ADR_WIFI_RADAR_REG_02)) = (0x0834002d)
+#define DEF_WIFI_RADAR_REG_03() (REG32(ADR_WIFI_RADAR_REG_03)) = (0x20600e74)
+#define DEF_WIFI_RADAR_REG_04() (REG32(ADR_WIFI_RADAR_REG_04)) = (0x04080000)
+#define DEF_WIFI_RADAR_REG_RO() (REG32(ADR_WIFI_RADAR_REG_RO)) = (0x00000000)
+#define DEF_WIFI_RADAR_REG_DB_A0_RO() (REG32(ADR_WIFI_RADAR_REG_DB_A0_RO)) = (0x00000000)
+#define DEF_WIFI_RADAR_REG_DB_A1_RO() (REG32(ADR_WIFI_RADAR_REG_DB_A1_RO)) = (0x00000000)
+#define DEF_WIFI_RADAR_REG_DB_A2_RO() (REG32(ADR_WIFI_RADAR_REG_DB_A2_RO)) = (0x00000000)
+#define DEF_WIFI_RADAR_REG_DB_P0_RO() (REG32(ADR_WIFI_RADAR_REG_DB_P0_RO)) = (0x00000000)
+#define DEF_WIFI_RADAR_REG_DB_P1_RO() (REG32(ADR_WIFI_RADAR_REG_DB_P1_RO)) = (0x00000000)
+#define DEF_WIFI_RADAR_REG_DB_P2_RO() (REG32(ADR_WIFI_RADAR_REG_DB_P2_RO)) = (0x00000000)
+#define DEF_WIFI_RADAR_CHIRP_REG() (REG32(ADR_WIFI_RADAR_CHIRP_REG)) = (0x07d003e8)
+#define DEF_MB_CPU_INT_ALT() (REG32(ADR_MB_CPU_INT_ALT)) = (0x00000000)
+#define DEF_MB_CPU_INT() (REG32(ADR_MB_CPU_INT)) = (0x00000000)
+#define DEF_CPU_ID_TB0() (REG32(ADR_CPU_ID_TB0)) = (0x00000000)
+#define DEF_CPU_ID_TB1() (REG32(ADR_CPU_ID_TB1)) = (0x00000000)
+#define DEF_CH0_TRIG_1() (REG32(ADR_CH0_TRIG_1)) = (0x00000000)
+#define DEF_CH0_TRIG_0() (REG32(ADR_CH0_TRIG_0)) = (0x00000000)
+#define DEF_CH0_PRI_TRIG() (REG32(ADR_CH0_PRI_TRIG)) = (0x00000000)
+#define DEF_MCU_STATUS() (REG32(ADR_MCU_STATUS)) = (0x00000000)
+#define DEF_RD_IN_FFCNT1() (REG32(ADR_RD_IN_FFCNT1)) = (0x00000000)
+#define DEF_RD_IN_FFCNT2() (REG32(ADR_RD_IN_FFCNT2)) = (0x00000000)
+#define DEF_RD_FFIN_FULL() (REG32(ADR_RD_FFIN_FULL)) = (0x00000000)
+#define DEF_CH2_TRIG_ALT() (REG32(ADR_CH2_TRIG_ALT)) = (0x00000000)
+#define DEF_CH2_INT_ADDR_ALT() (REG32(ADR_CH2_INT_ADDR_ALT)) = (0x00000000)
+#define DEF_MBOX_HALT_CFG() (REG32(ADR_MBOX_HALT_CFG)) = (0x00000000)
+#define DEF_MBOX_HALT_STS() (REG32(ADR_MBOX_HALT_STS)) = (0x00000000)
+#define DEF_MB_DBG_CFG1() (REG32(ADR_MB_DBG_CFG1)) = (0x00080000)
+#define DEF_MB_DBG_CFG2() (REG32(ADR_MB_DBG_CFG2)) = (0x00000000)
+#define DEF_MB_DBG_CFG3() (REG32(ADR_MB_DBG_CFG3)) = (0x00000000)
+#define DEF_MB_DBG_CFG4() (REG32(ADR_MB_DBG_CFG4)) = (0xffffffff)
+#define DEF_MB_OUT_QUEUE_CFG() (REG32(ADR_MB_OUT_QUEUE_CFG)) = (0x00000002)
+#define DEF_MB_OUT_QUEUE_FLUSH() (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (0x00000000)
+#define DEF_MB_OUT_QUEUE_FLUSH() (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (0x00000000)
+#define DEF_RD_FFOUT_CNT1() (REG32(ADR_RD_FFOUT_CNT1)) = (0x00000000)
+#define DEF_RD_FFOUT_CNT2() (REG32(ADR_RD_FFOUT_CNT2)) = (0x00000000)
+#define DEF_RD_FFOUT_CNT3() (REG32(ADR_RD_FFOUT_CNT3)) = (0x00000000)
+#define DEF_RD_FFOUT_FULL() (REG32(ADR_RD_FFOUT_FULL)) = (0x00000000)
+#define DEF_MB_THRESHOLD6() (REG32(ADR_MB_THRESHOLD6)) = (0x00000000)
+#define DEF_MB_THRESHOLD7() (REG32(ADR_MB_THRESHOLD7)) = (0x00000000)
+#define DEF_MB_THRESHOLD8() (REG32(ADR_MB_THRESHOLD8)) = (0x00000000)
+#define DEF_MB_THRESHOLD9() (REG32(ADR_MB_THRESHOLD9)) = (0x00000000)
+#define DEF_MB_THRESHOLD10() (REG32(ADR_MB_THRESHOLD10)) = (0x00000000)
+#define DEF_MB_TRASH_CFG() (REG32(ADR_MB_TRASH_CFG)) = (0x01000001)
+#define DEF_MB_IN_FF_FLUSH() (REG32(ADR_MB_IN_FF_FLUSH)) = (0x00000000)
+#define DEF_MB_IN_FF_FLUSH() (REG32(ADR_MB_IN_FF_FLUSH)) = (0x00000000)
+#define DEF_CPU_ID_TB2() (REG32(ADR_CPU_ID_TB2)) = (0x00000000)
+#define DEF_CPU_ID_TB3() (REG32(ADR_CPU_ID_TB3)) = (0x00000000)
+#define DEF_PHY_IQ_LOG_CFG0() (REG32(ADR_PHY_IQ_LOG_CFG0)) = (0x00000000)
+#define DEF_PHY_IQ_LOG_CFG1() (REG32(ADR_PHY_IQ_LOG_CFG1)) = (0x00000000)
+#define DEF_PHY_IQ_LOG_LEN() (REG32(ADR_PHY_IQ_LOG_LEN)) = (0x00001000)
+#define DEF_PHY_IQ_LOG_PTR() (REG32(ADR_PHY_IQ_LOG_PTR)) = (0x00000000)
+#define DEF_WR_ALC() (REG32(ADR_WR_ALC)) = (0x00000000)
+#define DEF_GETID() (REG32(ADR_GETID)) = (0x00000000)
+#define DEF_CH_STA_PRI() (REG32(ADR_CH_STA_PRI)) = (0x00000213)
+#define DEF_RD_ID0() (REG32(ADR_RD_ID0)) = (0x00000000)
+#define DEF_RD_ID1() (REG32(ADR_RD_ID1)) = (0x00000000)
+#define DEF_IMD_CFG() (REG32(ADR_IMD_CFG)) = (0x00000000)
+#define DEF_IMD_STA() (REG32(ADR_IMD_STA)) = (0x00000000)
+#define DEF_ALC_STA() (REG32(ADR_ALC_STA)) = (0x01000000)
+#define DEF_TRX_ID_COUNT() (REG32(ADR_TRX_ID_COUNT)) = (0x00000000)
+#define DEF_TRX_ID_THRESHOLD() (REG32(ADR_TRX_ID_THRESHOLD)) = (0x01ee3c3c)
+#define DEF_TX_ID0() (REG32(ADR_TX_ID0)) = (0x00000000)
+#define DEF_TX_ID1() (REG32(ADR_TX_ID1)) = (0x00000000)
+#define DEF_RX_ID0() (REG32(ADR_RX_ID0)) = (0x00000000)
+#define DEF_RX_ID1() (REG32(ADR_RX_ID1)) = (0x00000000)
+#define DEF_RTN_STA() (REG32(ADR_RTN_STA)) = (0x00000001)
+#define DEF_ID_LEN_THREADSHOLD1() (REG32(ADR_ID_LEN_THREADSHOLD1)) = (0x000f0641)
+#define DEF_ID_LEN_THREADSHOLD2() (REG32(ADR_ID_LEN_THREADSHOLD2)) = (0x00000000)
+#define DEF_CH_ARB_PRI() (REG32(ADR_CH_ARB_PRI)) = (0x00031201)
+#define DEF_TX_ID_REMAIN_STATUS() (REG32(ADR_TX_ID_REMAIN_STATUS)) = (0x00000000)
+#define DEF_ID_INFO_STA() (REG32(ADR_ID_INFO_STA)) = (0x00000100)
+#define DEF_TX_LIMIT_INTR() (REG32(ADR_TX_LIMIT_INTR)) = (0x00000000)
+#define DEF_TX_ID_ALL_INFO() (REG32(ADR_TX_ID_ALL_INFO)) = (0x00000000)
+#define DEF_RD_ID2() (REG32(ADR_RD_ID2)) = (0x00000000)
+#define DEF_RD_ID3() (REG32(ADR_RD_ID3)) = (0x00000000)
+#define DEF_TX_ID2() (REG32(ADR_TX_ID2)) = (0x00000000)
+#define DEF_TX_ID3() (REG32(ADR_TX_ID3)) = (0x00000000)
+#define DEF_RX_ID2() (REG32(ADR_RX_ID2)) = (0x00000000)
+#define DEF_RX_ID3() (REG32(ADR_RX_ID3)) = (0x00000000)
+#define DEF_TX_ID_ALL_INFO2() (REG32(ADR_TX_ID_ALL_INFO2)) = (0x00000000)
+#define DEF_TX_ID_ALL_INFO_A() (REG32(ADR_TX_ID_ALL_INFO_A)) = (0x00000000)
+#define DEF_TX_ID_ALL_INFO_B() (REG32(ADR_TX_ID_ALL_INFO_B)) = (0x00000000)
+#define DEF_TX_ID_REMAIN_STATUS2() (REG32(ADR_TX_ID_REMAIN_STATUS2)) = (0x01000100)
+#define DEF_ALC_ID_INFO() (REG32(ADR_ALC_ID_INFO)) = (0x00000000)
+#define DEF_ALC_ID_INF1() (REG32(ADR_ALC_ID_INF1)) = (0x00000000)
+#define DEF_ALC_ABORT() (REG32(ADR_ALC_ABORT)) = (0x00000000)
+#define DEF_ALC_RLS_STATUS() (REG32(ADR_ALC_RLS_STATUS)) = (0x00000000)
+#define DEF_DMN_STATUS() (REG32(ADR_DMN_STATUS)) = (0x00007ff0)
+#define DEF_TAG_STATUS() (REG32(ADR_TAG_STATUS)) = (0x00000000)
+#define DEF_REQ_STATUS() (REG32(ADR_REQ_STATUS)) = (0x00000000)
+#define DEF_PAGE_TAG_STATUS_0() (REG32(ADR_PAGE_TAG_STATUS_0)) = (0x00000000)
+#define DEF_PAGE_TAG_STATUS_1() (REG32(ADR_PAGE_TAG_STATUS_1)) = (0x00000000)
+#define DEF_PAGE_TAG_STATUS_2() (REG32(ADR_PAGE_TAG_STATUS_2)) = (0x00000000)
+#define DEF_PAGE_TAG_STATUS_3() (REG32(ADR_PAGE_TAG_STATUS_3)) = (0x00000000)
+#define DEF_PAGE_TAG_STATUS_4() (REG32(ADR_PAGE_TAG_STATUS_4)) = (0x00000000)
+#define DEF_PAGE_TAG_STATUS_5() (REG32(ADR_PAGE_TAG_STATUS_5)) = (0x00000000)
+#define DEF_PAGE_TAG_STATUS_6() (REG32(ADR_PAGE_TAG_STATUS_6)) = (0x00000000)
+#define DEF_PAGE_TAG_STATUS_7() (REG32(ADR_PAGE_TAG_STATUS_7)) = (0x00000000)
+#define DEF_FPGA_GEMINIARF_SWITCH() (REG32(ADR_FPGA_GEMINIARF_SWITCH)) = (0x00000000)
diff --git a/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/ssv6006C_reg_sim.h b/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/ssv6006C_reg_sim.h
new file mode 100644
index 000000000..dc01cca6f
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/ssv6006C_reg_sim.h
@@ -0,0 +1,209 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <regs/turismo_v0p5_reg.h>
+#define BANK_COUNT 61
+static const u32 BASE_BANK_SSV6200[] = {
+    FBUS_DMAC_REG_BASE,
+    SBUS_DMAC_REG_BASE,
+    I2S_TRX_REG_BASE,
+    I2CMST_REG_BASE,
+    SPIMST_REG_BASE,
+    SYS_REG_BASE,
+    CSR_ALLON_BASE,
+    TU0_US_REG_BASE,
+    TU1_US_REG_BASE,
+    TU2_US_REG_BASE,
+    TU3_US_REG_BASE,
+    TM0_MS_REG_BASE,
+    TM1_MS_REG_BASE,
+    TM2_MS_REG_BASE,
+    TM3_MS_REG_BASE,
+    MCU_WDT_REG_BASE,
+    SYS_WDT_REG_BASE,
+    PWM_REG_BASE,
+    IO_REG_BASE,
+    CSR_I2C_SLV_BASE,
+    SD_REG_BASE,
+    SPI_REG_BASE,
+    CSR_I2C_MST_BASE,
+    UART_REG_BASE,
+    DAT_UART_REG_BASE,
+    FLASH_SPI_REG_BASE,
+    DMA_REG_BASE,
+    D2_DMA_REG_BASE,
+    INT_CTRL_REG_BASE,
+    SYS_UTILS_BASE,
+    RTC_MISC_REG_BASE,
+    HCI_REG_BASE,
+    CO_REG_BASE,
+    EFS_REG_BASE,
+    CSR_SPIMAS_BASE,
+    SPIMAS_TX_BUF_BASE,
+    SPIMAS_RX_BUF_BASE,
+    MRX_REG_BASE,
+    AMPDU_REG_BASE,
+    MT_REG_CSR_BASE,
+    TXQ0_MT_Q_REG_CSR_BASE,
+    TXQ1_MT_Q_REG_CSR_BASE,
+    TXQ2_MT_Q_REG_CSR_BASE,
+    TXQ3_MT_Q_REG_CSR_BASE,
+    TXQ4_MT_Q_REG_CSR_BASE,
+    TXQ5_MT_Q_REG_CSR_BASE,
+    MT_RESPFRM_REG_BASE,
+    HIF_INFO_BASE,
+    PHY_RATE_INFO_BASE,
+    MAC_GLB_SET_BASE,
+    BTCX_REG_BASE,
+    MIB_REG_BASE,
+    WSID_EXT_BASE,
+    RF_REG_BASE,
+    CSR_TU_RF_BASE,
+    CSR_TU_PMU_BASE,
+    CSR_TU_PHY_BASE,
+    MB_REG_BASE,
+    ID_MNG_REG_BASE,
+    MMU_REG_BASE,
+    CSR_TEMP_REG_BASE,
+    0x00000000
+};
+static const char* STR_BANK_SSV6200[] = {
+    "FBUS_DMAC_REG",
+    "SBUS_DMAC_REG",
+    "I2S_TRX_REG",
+    "I2CMST_REG",
+    "SPIMST_REG",
+    "SYS_REG",
+    "CSR_ALLON",
+    "TU0_US_REG",
+    "TU1_US_REG",
+    "TU2_US_REG",
+    "TU3_US_REG",
+    "TM0_MS_REG",
+    "TM1_MS_REG",
+    "TM2_MS_REG",
+    "TM3_MS_REG",
+    "MCU_WDT_REG",
+    "SYS_WDT_REG",
+    "PWM_REG",
+    "IO_REG",
+    "CSR_I2C_SLV",
+    "SD_REG",
+    "SPI_REG",
+    "CSR_I2C_MST",
+    "UART_REG",
+    "DAT_UART_REG",
+    "FLASH_SPI_REG",
+    "DMA_REG",
+    "D2_DMA_REG",
+    "INT_CTRL_REG",
+    "SYS_UTILS",
+    "RTC_MISC_REG",
+    "HCI_REG",
+    "CO_REG",
+    "EFS_REG",
+    "CSR_SPIMAS",
+    "SPIMAS_TX_BUF",
+    "SPIMAS_RX_BUF",
+    "MRX_REG",
+    "AMPDU_REG",
+    "MT_REG_CSR",
+    "TXQ0_MT_Q_REG_CSR",
+    "TXQ1_MT_Q_REG_CSR",
+    "TXQ2_MT_Q_REG_CSR",
+    "TXQ3_MT_Q_REG_CSR",
+    "TXQ4_MT_Q_REG_CSR",
+    "TXQ5_MT_Q_REG_CSR",
+    "MT_RESPFRM_REG",
+    "HIF_INFO",
+    "PHY_RATE_INFO",
+    "MAC_GLB_SET",
+    "BTCX_REG",
+    "MIB_REG",
+    "WSID_EXT",
+    "RF_REG",
+    "CSR_TU_RF",
+    "CSR_TU_PMU",
+    "CSR_TU_PHY",
+    "MB_REG",
+    "ID_MNG_REG",
+    "MMU_REG",
+    "CSR_TEMP_REG",
+    ""
+};
+static const u32 SIZE_BANK_SSV6200[] = {
+    FBUS_DMAC_REG_BANK_SIZE,
+    SBUS_DMAC_REG_BANK_SIZE,
+    I2S_TRX_REG_BANK_SIZE,
+    I2CMST_REG_BANK_SIZE,
+    SPIMST_REG_BANK_SIZE,
+    SYS_REG_BANK_SIZE,
+    CSR_ALLON_BANK_SIZE,
+    TU0_US_REG_BANK_SIZE,
+    TU1_US_REG_BANK_SIZE,
+    TU2_US_REG_BANK_SIZE,
+    TU3_US_REG_BANK_SIZE,
+    TM0_MS_REG_BANK_SIZE,
+    TM1_MS_REG_BANK_SIZE,
+    TM2_MS_REG_BANK_SIZE,
+    TM3_MS_REG_BANK_SIZE,
+    MCU_WDT_REG_BANK_SIZE,
+    SYS_WDT_REG_BANK_SIZE,
+    PWM_REG_BANK_SIZE,
+    IO_REG_BANK_SIZE,
+    CSR_I2C_SLV_BANK_SIZE,
+    SD_REG_BANK_SIZE,
+    SPI_REG_BANK_SIZE,
+    CSR_I2C_MST_BANK_SIZE,
+    UART_REG_BANK_SIZE,
+    DAT_UART_REG_BANK_SIZE,
+    FLASH_SPI_REG_BANK_SIZE,
+    DMA_REG_BANK_SIZE,
+    D2_DMA_REG_BANK_SIZE,
+    INT_CTRL_REG_BANK_SIZE,
+    SYS_UTILS_BANK_SIZE,
+    RTC_MISC_REG_BANK_SIZE,
+    HCI_REG_BANK_SIZE,
+    CO_REG_BANK_SIZE,
+    EFS_REG_BANK_SIZE,
+    CSR_SPIMAS_BANK_SIZE,
+    SPIMAS_TX_BUF_BANK_SIZE,
+    SPIMAS_RX_BUF_BANK_SIZE,
+    MRX_REG_BANK_SIZE,
+    AMPDU_REG_BANK_SIZE,
+    MT_REG_CSR_BANK_SIZE,
+    TXQ0_MT_Q_REG_CSR_BANK_SIZE,
+    TXQ1_MT_Q_REG_CSR_BANK_SIZE,
+    TXQ2_MT_Q_REG_CSR_BANK_SIZE,
+    TXQ3_MT_Q_REG_CSR_BANK_SIZE,
+    TXQ4_MT_Q_REG_CSR_BANK_SIZE,
+    TXQ5_MT_Q_REG_CSR_BANK_SIZE,
+    MT_RESPFRM_REG_BANK_SIZE,
+    HIF_INFO_BANK_SIZE,
+    PHY_RATE_INFO_BANK_SIZE,
+    MAC_GLB_SET_BANK_SIZE,
+    BTCX_REG_BANK_SIZE,
+    MIB_REG_BANK_SIZE,
+    WSID_EXT_BANK_SIZE,
+    RF_REG_BANK_SIZE,
+    CSR_TU_RF_BANK_SIZE,
+    CSR_TU_PMU_BANK_SIZE,
+    CSR_TU_PHY_BANK_SIZE,
+    MB_REG_BANK_SIZE,
+    ID_MNG_REG_BANK_SIZE,
+    MMU_REG_BANK_SIZE,
+    CSR_TEMP_REG_BANK_SIZE,
+    0x00000000
+};
diff --git a/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/ssv6006_cfg.h b/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/ssv6006_cfg.h
new file mode 100644
index 000000000..e26a4a685
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/ssv6006_cfg.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __SSV6006_H___
+#define __SSV6006_H__
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#ifdef SSV_MAC80211
+#include "ssv_mac80211.h"
+#else
+#include <net/mac80211.h>
+#endif
+#ifdef ECLIPSE
+#include <ssv_mod_conf.h>
+#endif
+#include <hwif/hwif.h>
+#include <hci/ssv_hci.h>
+#include "ssv_cfg.h"
+#include "ssv6006_common.h"
+#define SSV6006_TOTAL_PAGE (256)
+#define SSV6006_TOTAL_ID (128)
+#ifndef HUW_DRV
+#define SSV6006_ID_SEC 1
+#define SSV6006_ID_TX_USB 1
+#define SSV6006_ID_TX_THRESHOLD (63 - SSV6006_ID_TX_USB)
+#define SSV6006_ID_RX_THRESHOLD (SSV6006_TOTAL_ID - (SSV6006_ID_TX_THRESHOLD + SSV6006_ID_TX_USB + SSV6006_ID_SEC))
+#define SSV6006_ID_USB_TX_THRESHOLD (17)
+#define SSV6006_ID_USB_RX_THRESHOLD (SSV6006_TOTAL_ID - (SSV6006_ID_USB_TX_THRESHOLD + SSV6006_ID_TX_USB + SSV6006_ID_SEC))
+#define SSV6006_USB_FIFO (8)
+#define SSV6006_RESERVED_SEC_PAGE (3)
+#define SSV6006_RESERVED_USB_PAGE (4)
+#define SSV6006_PAGE_TX_THRESHOLD (SSV6006_TOTAL_PAGE*3/4)
+#define SSV6006_PAGE_RX_THRESHOLD (SSV6006_TOTAL_PAGE*1/4)
+#define SSV6006_AMPDU_DIVIDER (2)
+#define SSV6006_TX_LOWTHRESHOLD_PAGE_TRIGGER (SSV6006_PAGE_TX_THRESHOLD - (SSV6006_PAGE_TX_THRESHOLD/SSV6006_AMPDU_DIVIDER))
+#define SSV6006_TX_LOWTHRESHOLD_ID_TRIGGER (SSV6006_ID_TX_THRESHOLD - 1)
+#else
+#undef SSV6006_ID_TX_THRESHOLD
+#undef SSV6006_ID_RX_THRESHOLD
+#undef SSV6006_PAGE_TX_THRESHOLD
+#undef SSV6006_PAGE_RX_THRESHOLD
+#undef SSV6006_TX_LOWTHRESHOLD_PAGE_TRIGGER
+#undef SSV6006_TX_LOWTHRESHOLD_ID_TRIGGER
+#define SSV6006_ID_TX_THRESHOLD 31
+#define SSV6006_ID_RX_THRESHOLD 31
+#define SSV6006_PAGE_TX_THRESHOLD 61
+#define SSV6006_PAGE_RX_THRESHOLD 61
+#define SSV6006_TX_LOWTHRESHOLD_PAGE_TRIGGER 45
+#define SSV6006_TX_LOWTHRESHOLD_ID_TRIGGER 2
+#endif
+#define SSV6006_ID_NUMBER (SSV6006_TOTAL_ID)
+#define PACKET_ADDR_2_ID(addr) ((addr >> 16) & 0x7F)
+#define SSV6006_ID_AC_RESERVED 1
+#define SSV6006_ID_AC_BK_OUT_QUEUE 8
+#define SSV6006_ID_AC_BE_OUT_QUEUE 15
+#define SSV6006_ID_AC_VI_OUT_QUEUE 16
+#define SSV6006_ID_AC_VO_OUT_QUEUE 16
+#define SSV6006_ID_MANAGER_QUEUE 8
+#define HW_MMU_PAGE_SHIFT 0x8
+#define HW_MMU_PAGE_MASK 0xff
+#define SSV6006_TX_PKT_RSVD_SETTING (0x3)
+#define SSV6006_TX_PKT_RSVD (SSV6006_TX_PKT_RSVD_SETTING * 16)
+#define SSV6006_ALLOC_RSVD (TXPB_OFFSET+SSV6006_TX_PKT_RSVD)
+#define SSV6006_BT_PRI_SMP_TIME 0
+#define SSV6006_BT_STA_SMP_TIME (SSV6006_BT_PRI_SMP_TIME+0)
+#define SSV6006_WLAN_REMAIN_TIME 0
+#define BT_2WIRE_EN_MSK 0x00000400
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/ssv6006_common.c b/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/ssv6006_common.c
new file mode 100644
index 000000000..1d4cfa206
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/ssv6006_common.c
@@ -0,0 +1,712 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifdef ECLIPSE
+#include <ssv_mod_conf.h>
+#endif
+#include <linux/version.h>
+#if ((defined SSV_SUPPORT_HAL) && (defined SSV_SUPPORT_SSV6006))
+#include <linux/etherdevice.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+#include "ssv6006_cfg.h"
+#include "ssv6006_mac.h"
+#include <smac/dev.h>
+#include <smac/ssv_rc_minstrel.h>
+#include <hal.h>
+#include "ssv6006_priv.h"
+#include <smac/ssv_skb.h>
+#include <hci/hctrl.h>
+#include <ssvdevice/ssv_cmd.h>
+static struct ssv_hw * ssv6006_alloc_hw (void)
+{
+    struct ssv_hw *sh;
+    sh = kzalloc(sizeof(struct ssv_hw), GFP_KERNEL);
+    if (sh == NULL)
+        goto out;
+    memset((void *)sh, 0, sizeof(struct ssv_hw));
+    sh->page_count = (u8 *)kzalloc(sizeof(u8) * SSV6006_ID_NUMBER, GFP_KERNEL);
+    if (sh->page_count == NULL)
+        goto out;
+    memset(sh->page_count, 0, sizeof(u8) * SSV6006_ID_NUMBER);
+    return sh;
+out:
+    if (sh->page_count)
+        kfree(sh->page_count);
+    if (sh)
+        kfree(sh);
+    return NULL;
+}
+static bool ssv6006_use_hw_encrypt(int cipher, struct ssv_softc *sc,
+                                   struct ssv_sta_priv_data *sta_priv, struct ssv_vif_priv_data *vif_priv )
+{
+    return true;
+}
+static bool ssv6006_if_chk_mac2(struct ssv_hw *sh)
+{
+    printk(" %s: is not need to check MAC addres 2 for this model \n",__func__);
+    return false;
+}
+static int ssv6006_get_wsid(struct ssv_softc *sc, struct ieee80211_vif *vif,
+                            struct ieee80211_sta *sta)
+{
+    struct ssv_vif_priv_data *vif_priv = (struct ssv_vif_priv_data *)vif->drv_priv;
+    int s;
+    struct ssv_sta_priv_data *sta_priv_dat=NULL;
+    struct ssv_sta_info *sta_info;
+    for (s = 0; s < SSV_NUM_STA; s++) {
+        sta_info = &sc->sta_info[s];
+        if ((sta_info->s_flags & STA_FLAG_VALID) == 0) {
+            sta_info->aid = sta->aid;
+            sta_info->sta = sta;
+            sta_info->vif = vif;
+            sta_info->s_flags = STA_FLAG_VALID;
+            sta_priv_dat =
+                (struct ssv_sta_priv_data *)sta->drv_priv;
+            sta_priv_dat->sta_idx = s;
+            sta_priv_dat->sta_info = sta_info;
+            sta_priv_dat->has_hw_encrypt = false;
+            sta_priv_dat->has_hw_decrypt = false;
+            sta_priv_dat->need_sw_decrypt = false;
+            sta_priv_dat->need_sw_encrypt = false;
+#ifdef USE_LOCAL_CRYPTO
+            if (HAL_NEED_SW_CIPHER(sc->sh)) {
+                sta_priv_dat->crypto_data.ops = NULL;
+                sta_priv_dat->crypto_data.priv = NULL;
+#ifdef HAS_CRYPTO_LOCK
+                rwlock_init(&sta_priv_dat->crypto_data.lock);
+#endif
+            }
+#endif
+            if ( (vif_priv->pair_cipher == SSV_CIPHER_WEP40)
+                 || (vif_priv->pair_cipher == SSV_CIPHER_WEP104)) {
+#ifdef USE_LOCAL_CRYPTO
+                if (vif_priv->crypto_data.ops != NULL) {
+                    sta_priv_dat->crypto_data.ops = vif_priv->crypto_data.ops;
+                    sta_priv_dat->crypto_data.priv = vif_priv->crypto_data.priv;
+                }
+#endif
+                sta_priv_dat->has_hw_encrypt = vif_priv->has_hw_encrypt;
+                sta_priv_dat->has_hw_decrypt = vif_priv->has_hw_decrypt;
+                sta_priv_dat->need_sw_encrypt = vif_priv->need_sw_encrypt;
+                sta_priv_dat->need_sw_decrypt = vif_priv->need_sw_decrypt;
+            }
+            list_add_tail(&sta_priv_dat->list, &vif_priv->sta_list);
+            break;
+        }
+    }
+    return s;
+}
+static void ssv6006_add_fw_wsid(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv,
+                                struct ieee80211_sta *sta, struct ssv_sta_info *sta_info)
+{
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_HAL,
+             " %s: is not need for this model \n",__func__);
+}
+static void ssv6006_del_fw_wsid(struct ssv_softc *sc, struct ieee80211_sta *sta,
+                                struct ssv_sta_info *sta_info)
+{
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_HAL,
+             " %s: is not need for this model \n",__func__);
+}
+static void ssv6006_enable_fw_wsid(struct ssv_softc *sc, struct ieee80211_sta *sta,
+                                   struct ssv_sta_info *sta_info, enum SSV6XXX_WSID_SEC key_type)
+{
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_HAL,
+             " %s: is not need for this model \n",__func__);
+}
+static void ssv6006_disable_fw_wsid(struct ssv_softc *sc, int key_idx,
+                                    struct ssv_sta_priv_data *sta_priv, struct ssv_vif_priv_data *vif_priv)
+{
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_HAL,
+             " %s: is not need for this model \n",__func__);
+}
+static void ssv6006_set_fw_hwwsid_sec_type(struct ssv_softc *sc, struct ieee80211_sta *sta,
+        struct ssv_sta_info *sta_info, struct ssv_vif_priv_data *vif_priv)
+{
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_HAL,
+             " %s: is not need for this model \n",__func__);
+}
+static bool ssv6006_wep_use_hw_cipher(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv)
+{
+    bool ret = false;
+    if (sc->sh->cfg.use_sw_cipher != 1) {
+        ret = true;
+    }
+    return ret;
+}
+static bool ssv6006_pairwise_wpa_use_hw_cipher(struct ssv_softc *sc,
+        struct ssv_vif_priv_data *vif_priv, enum SSV_CIPHER_E cipher,
+        struct ssv_sta_priv_data *sta_priv)
+{
+    bool ret = false;
+    if (sc->sh->cfg.use_sw_cipher != 1) {
+        ret = true;
+    }
+    return ret;
+}
+static bool ssv6006_group_wpa_use_hw_cipher(struct ssv_softc *sc,
+        struct ssv_vif_priv_data *vif_priv, enum SSV_CIPHER_E cipher)
+{
+    int ret =false;
+    if (sc->sh->cfg.use_sw_cipher != 1) {
+        ret = true;
+    }
+    return ret;
+}
+static bool ssv6006_chk_if_support_hw_bssid(struct ssv_softc *sc,
+        int vif_idx)
+{
+    if ((vif_idx >= 0) && (vif_idx < SSV6006_NUM_HW_BSSID))
+        return true;
+    printk(" %s: VIF %d doesn't support HW BSSID\n", __func__, vif_idx);
+    return false;
+}
+static void ssv6006_chk_dual_vif_chg_rx_flow(struct ssv_softc *sc,
+        struct ssv_vif_priv_data *vif_priv)
+{
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_HAL,
+             " %s: is not need for this model \n",__func__);
+}
+static void ssv6006_restore_rx_flow(struct ssv_softc *sc,
+                                    struct ssv_vif_priv_data *vif_priv, struct ieee80211_sta *sta)
+{
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_HAL,
+             " %s: is not need for this model \n",__func__);
+}
+static int ssv6006_hw_crypto_key_write_wep(struct ssv_softc *sc,
+        struct ieee80211_key_conf *keyconf, u8 algorithm,
+        struct ssv_vif_info *vif_info)
+{
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_HAL,
+             " %s: is not need for this model \n",__func__);
+    return 0;
+}
+static void ssv6006_set_wep_hw_crypto_key(struct ssv_softc *sc,
+        struct ssv_sta_info *sta_info, struct ssv_vif_priv_data *vif_priv)
+{
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_HAL,
+             " %s: is not need for this model \n",__func__);
+}
+static bool ssv6006_put_mic_space_for_hw_ccmp_encrypt(struct ssv_softc *sc, struct sk_buff *skb)
+{
+    struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
+    struct ieee80211_key_conf *hw_key = info->control.hw_key;
+    struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
+    struct SKB_info_st *skb_info = (struct SKB_info_st *)skb->head;
+    struct ieee80211_sta *sta = skb_info->sta;
+    struct ssv_vif_priv_data *vif_priv = (struct ssv_vif_priv_data *)info->control.vif->drv_priv;
+    struct ssv_sta_priv_data *ssv_sta_priv = sta ? (struct ssv_sta_priv_data *)sta->drv_priv : NULL;
+    if ( (!ieee80211_is_data_qos(hdr->frame_control)
+          && !ieee80211_is_data(hdr->frame_control))
+         || !ieee80211_has_protected(hdr->frame_control) )
+        return false;
+    if (hw_key) {
+        if(hw_key->cipher != WLAN_CIPHER_SUITE_CCMP)
+            return false;
+    }
+    if (!is_unicast_ether_addr(hdr->addr1)) {
+        if (vif_priv->is_security_valid
+            && vif_priv->has_hw_encrypt) {
+            pskb_expand_head(skb, 0, CCMP_MIC_LEN, GFP_ATOMIC);
+            skb_put(skb, CCMP_MIC_LEN);
+            return true;
+        }
+    } else if (ssv_sta_priv != NULL) {
+        if (ssv_sta_priv->has_hw_encrypt) {
+            pskb_expand_head(skb, 0, CCMP_MIC_LEN, GFP_ATOMIC);
+            skb_put(skb, CCMP_MIC_LEN);
+            return true;
+        }
+    }
+    return false;
+}
+static void ssv6006_init_tx_cfg(struct ssv_hw *sh)
+{
+    u32 dev_type = HCI_DEVICE_TYPE(sh->hci.hci_ctrl);
+    if ((sh->cfg.tx_id_threshold == 0) || (sh->cfg.tx_id_threshold > SSV6006_ID_TX_THRESHOLD)) {
+        if ((dev_type == SSV_HWIF_INTERFACE_USB) &&
+            ( (sh->cfg.usb_hw_resource & USB_HW_RESOURCE_CHK_TXID ) == 0)) {
+            sh->tx_info.tx_id_threshold = SSV6006_ID_USB_TX_THRESHOLD;
+        } else {
+            sh->tx_info.tx_id_threshold = SSV6006_ID_TX_THRESHOLD;
+        }
+        sh->tx_info.tx_lowthreshold_id_trigger = SSV6006_TX_LOWTHRESHOLD_ID_TRIGGER;
+    } else {
+        sh->tx_info.tx_id_threshold = sh->cfg.tx_id_threshold;
+        sh->tx_info.tx_lowthreshold_id_trigger = (sh->tx_info.tx_id_threshold - 1);
+    }
+    if ((sh->cfg.tx_page_threshold == 0) || (sh->cfg.tx_page_threshold > SSV6006_PAGE_TX_THRESHOLD)) {
+        sh->tx_info.tx_page_threshold = SSV6006_PAGE_TX_THRESHOLD;
+        sh->tx_info.tx_lowthreshold_page_trigger = SSV6006_TX_LOWTHRESHOLD_PAGE_TRIGGER;
+    } else {
+        sh->tx_info.tx_page_threshold = sh->cfg.tx_page_threshold;
+        sh->tx_info.tx_lowthreshold_page_trigger =
+            (sh->tx_info.tx_page_threshold - (sh->tx_info.tx_page_threshold/SSV6006_AMPDU_DIVIDER));
+    }
+    sh->tx_page_available = sh->tx_info.tx_page_threshold;
+    if (dev_type == SSV_HWIF_INTERFACE_USB) {
+        sh->tx_info.tx_page_threshold = SSV6006_PAGE_TX_THRESHOLD - SSV6006_USB_FIFO;
+        sh->tx_page_available = sh->tx_info.tx_page_threshold - SSV6006_RESERVED_USB_PAGE;
+    }
+    sh->tx_info.bk_txq_size = SSV6006_ID_AC_BK_OUT_QUEUE;
+    sh->tx_info.be_txq_size = SSV6006_ID_AC_BE_OUT_QUEUE;
+    sh->tx_info.vi_txq_size = SSV6006_ID_AC_VI_OUT_QUEUE;
+    sh->tx_info.vo_txq_size = SSV6006_ID_AC_VO_OUT_QUEUE;
+    sh->tx_info.manage_txq_size = SSV6006_ID_MANAGER_QUEUE;
+    sh->ampdu_divider = SSV6006_AMPDU_DIVIDER;
+    memcpy(&(sh->hci.hci_ctrl->tx_info), &(sh->tx_info), sizeof(struct ssv6xxx_tx_hw_info));
+}
+static void ssv6006_init_rx_cfg(struct ssv_hw *sh)
+{
+    sh->rx_info.rx_id_threshold = SSV6006_TOTAL_ID - (sh->tx_info.tx_id_threshold + SSV6006_ID_TX_USB + SSV6006_ID_SEC);
+    sh->rx_info.rx_page_threshold = SSV6006_PAGE_RX_THRESHOLD;
+    sh->rx_info.rx_ba_ma_sessions = SSV6006_RX_BA_MAX_SESSIONS;
+    memcpy(&(sh->hci.hci_ctrl->rx_info), &(sh->rx_info), sizeof(struct ssv6xxx_rx_hw_info));
+}
+static u32 ssv6006_ba_map_walker (struct AMPDU_TID_st *ampdu_tid, u32 start_ssn,
+                                  u32 sn_bit_map[2], u32 *p_acked_num, struct aggr_ssn *ampdu_ssn, struct ssv_softc *sc)
+{
+    int i = 0;
+    u32 ssn = ampdu_ssn->ssn[0];
+    u32 word_idx = (-1), bit_idx = (-1);
+    bool found = ssv6xxx_ssn_to_bit_idx(start_ssn, ssn, &word_idx, &bit_idx);
+    bool first_found = found;
+    u32 aggr_num = 0;
+    u32 acked_num = 0;
+    if (found && (word_idx >= 2 || bit_idx >= 32))
+        prn_aggr_err(sc, "idx error 1: %d %d %d %d\n",
+                     start_ssn, ssn, word_idx, bit_idx);
+    while ((i < MAX_AGGR_NUM) && (ssn < SSV_AMPDU_MAX_SSN)) {
+        u32 cur_ssn;
+        struct sk_buff *skb = INDEX_PKT_BY_SSN(ampdu_tid, ssn);
+        u32 skb_ssn = (skb == NULL) ? (-1) : ampdu_skb_ssn(skb);
+        struct SKB_info_st *skb_info;
+        aggr_num++;
+        if (skb_ssn != ssn) {
+            prn_aggr_err(sc, "Unmatched SSN packet: %d - %d - %d\n",
+                         ssn, skb_ssn, start_ssn);
+        } else {
+            skb_info = (struct SKB_info_st *) (skb->head);
+            if (found && (sn_bit_map[word_idx] & (1 << bit_idx))) {
+                if (skb_info->ampdu_tx_status == AMPDU_ST_SENT) {
+                    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_AMPDU_SSN,"%s: mark ssn %d done\n", __func__, ssn);
+                    skb_info->ampdu_tx_status = AMPDU_ST_DONE;
+                } else {
+                    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_AMPDU_SSN,"%s: Find a MPDU of status %d! ssn %d\n",
+                             __func__, skb_info->ampdu_tx_status, ssn);
+                }
+                acked_num++;
+            } else {
+                if (skb_info->ampdu_tx_status == AMPDU_ST_SENT) {
+                    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_AMPDU_SSN,"%s: mark ssn %d retry\n", __func__, ssn);
+                    ssv6xxx_mark_skb_retry(sc, skb_info, skb);
+                } else {
+                    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_AMPDU_SSN,"%s: Find a MPDU of status %d! ssn %d\n",
+                             __func__, skb_info->ampdu_tx_status, ssn);
+                }
+            }
+        }
+        cur_ssn = ssn;
+        if ((++i >= MAX_AGGR_NUM) || (i >= ampdu_ssn->mpdu_num))
+            break;
+        ssn = ampdu_ssn->ssn[i];
+        if (ssn >= SSV_AMPDU_MAX_SSN)
+            break;
+        if (first_found) {
+            u32 old_word_idx, old_bit_idx;
+            found = ssv6xxx_inc_bit_idx(sc, cur_ssn, ssn, &word_idx, &bit_idx);
+            old_word_idx = word_idx;
+            old_bit_idx = bit_idx;
+            if (found && (word_idx >= 2 || bit_idx >= 32)) {
+                prn_aggr_err(sc,
+                             "idx error 2: %d 0x%08X 0X%08X %d %d (%d %d) (%d %d)\n",
+                             start_ssn, sn_bit_map[1], sn_bit_map[0], cur_ssn, ssn, word_idx, bit_idx, old_word_idx, old_bit_idx);
+                found = false;
+            } else if (!found) {
+                int j;
+                prn_aggr_err(sc, "SN out-of-order: %d\n", start_ssn);
+                for (j = 0; j < ampdu_ssn->mpdu_num; j++)
+                    prn_aggr_err(sc, " %d", ampdu_ssn->ssn[j]);
+                prn_aggr_err(sc, "\n");
+            }
+        } else {
+            found = ssv6xxx_ssn_to_bit_idx(start_ssn, ssn, &word_idx, &bit_idx);
+            first_found = found;
+            if (found && (word_idx >= 2 || bit_idx >= 32))
+                prn_aggr_err(sc, "idx error 3: %d %d %d %d\n",
+                             cur_ssn, ssn, word_idx, bit_idx);
+        }
+    }
+    ssv6xxx_release_frames(ampdu_tid);
+    if (p_acked_num != NULL)
+        *p_acked_num = acked_num;
+    return aggr_num;
+}
+static void ssv6006_ampdu_ba_notify(struct ssv_softc *sc, struct ieee80211_sta *sta,
+                                    u32 pkt_no, int ampdu_len, int ampdu_ack_len)
+{
+    struct ssv_sta_priv_data *ssv_sta_priv;
+    struct ssv_minstrel_sta_priv *minstrel_sta_priv;
+    struct ssv_minstrel_ht_sta *mhs;
+    struct ssv_minstrel_ht_rpt ht_rpt[SSV6006RC_MAX_RATE_SERIES];
+    struct ssv_minstrel_ampdu_rate_rpt *ampdu_rpt;
+    int i, rpt_idx = -1;
+    ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+    if((minstrel_sta_priv = (struct ssv_minstrel_sta_priv *)ssv_sta_priv->rc_info) == NULL)
+        return;
+    if (!minstrel_sta_priv->is_ht)
+        return;
+    mhs = (struct ssv_minstrel_ht_sta *)&minstrel_sta_priv->ht;
+    if (!ssv6006_rc_get_previous_ampdu_rpt(mhs, pkt_no, &rpt_idx)) {
+        ssv6006_rc_add_ampdu_rpt_to_list(sc, mhs, NULL, pkt_no, ampdu_len, ampdu_ack_len);
+    } else {
+        ampdu_rpt = (struct ssv_minstrel_ampdu_rate_rpt *)&mhs->ampdu_rpt_list[rpt_idx];
+        for (i = 0; i < SSV6006RC_MAX_RATE_SERIES; i++) {
+            ht_rpt[i].dword = ampdu_rpt->rate_rpt[i].dword;
+            ht_rpt[i].count = ampdu_rpt->rate_rpt[i].count;
+            ht_rpt[i].success = ampdu_rpt->rate_rpt[i].success;
+            ht_rpt[i].last = ampdu_rpt->rate_rpt[i].last;
+        }
+        ssv_minstrel_ht_tx_status(sc, ssv_sta_priv->rc_info, ht_rpt, SSV6006RC_MAX_RATE_SERIES,
+                                  ampdu_len, ampdu_ack_len, ampdu_rpt->is_sample);
+        ampdu_rpt->used = false;
+    }
+}
+int ssv6006_ampdu_rx_start(struct ieee80211_hw *hw, struct ieee80211_vif *vif, struct ieee80211_sta *sta,
+                           u16 tid, u16 *ssn, u8 buf_size)
+{
+    struct ssv_softc *sc = hw->priv;
+    struct ssv_sta_info *sta_info;
+    int i = 0;
+    bool find_peer = false;
+    for (i = 0; i < SSV_NUM_STA; i++) {
+        sta_info = &sc->sta_info[i];
+        if ((sta_info->s_flags & STA_FLAG_VALID) && (sta == sta_info->sta)) {
+            find_peer = true;
+            break;
+        }
+    }
+    if ((find_peer == false) || (sc->rx_ba_session_count > sc->sh->rx_info.rx_ba_ma_sessions))
+        return -EBUSY;
+    if (sta_info->s_flags & STA_FLAG_AMPDU_RX)
+        return 0;
+    printk(KERN_ERR "IEEE80211_AMPDU_RX_START %02X:%02X:%02X:%02X:%02X:%02X %d.\n",
+           sta->addr[0], sta->addr[1], sta->addr[2], sta->addr[3],
+           sta->addr[4], sta->addr[5], tid);
+    sc->rx_ba_session_count++;
+    sta_info->s_flags |= STA_FLAG_AMPDU_RX;
+    return 0;
+}
+static void ssv6006_ampdu_ba_handler (struct ieee80211_hw *hw, struct sk_buff *skb,
+                                      u32 tx_pkt_run_no)
+{
+    struct ssv_softc *sc = hw->priv;
+    struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) (skb->data
+                                + sc->sh->rx_desc_len);
+    AMPDU_BLOCKACK *BA_frame = (AMPDU_BLOCKACK *) hdr;
+    struct ieee80211_sta *sta;
+    struct ssv_sta_priv_data *ssv_sta_priv;
+    int i;
+    u32 ssn, aggr_num = 0, acked_num = 0;
+    u8 tid_no;
+    u32 sn_bit_map[2];
+    sta = ssv6xxx_find_sta_by_rx_skb(sc, skb);
+    if (sta == NULL) {
+        dev_kfree_skb_any(skb);
+        return;
+    }
+    ssv_sta_priv = (struct ssv_sta_priv_data *) sta->drv_priv;
+    ssn = BA_frame->BA_ssn;
+    sn_bit_map[0] = BA_frame->BA_sn_bit_map[0];
+    sn_bit_map[1] = BA_frame->BA_sn_bit_map[1];
+    tid_no = BA_frame->tid_info;
+    ssv_sta_priv->ampdu_mib_total_BA_counter++;
+    if (ssv_sta_priv->ampdu_tid[tid_no].state == AMPDU_STATE_STOP) {
+        prn_aggr_err(sc, "%s: state == AMPDU_STATE_STOP.\n", __func__);
+        dev_kfree_skb_any(skb);
+        return;
+    }
+    if ( (tx_pkt_run_no < SSV6XXX_PKT_RUN_TYPE_AMPDU_START) ||(tx_pkt_run_no > SSV6XXX_PKT_RUN_TYPE_AMPDU_END)) {
+        dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_AMPDU_SSN,
+                 "%s:\n Invalid tx_pkt_run_no %d\n", __func__, tx_pkt_run_no);
+        dev_kfree_skb_any(skb);
+        return;
+    }
+    for (i = 0; i < MAX_CONCUR_AMPDU; i ++) {
+        if (ssv_sta_priv->ampdu_ssn[i].tx_pkt_run_no == tx_pkt_run_no) {
+            dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_AMPDU_SSN,
+                     "%s:\n BA tx_pkt_run_no %d: found at slot %d \n", __func__, tx_pkt_run_no, i);
+            break;
+        }
+    }
+    if (i == MAX_CONCUR_AMPDU) {
+        dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_AMPDU_SSN,"%s:tx_pkt_run_no %d not found on sent list.\n",
+                 __func__,tx_pkt_run_no );
+        dev_kfree_skb_any(skb);
+        return;
+    }
+    if (ssv_sta_priv->ampdu_ssn[i].mpdu_num == 0) {
+        dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_AMPDU_SSN,"%s: invalid sent list\n",__func__ );
+        dev_kfree_skb_any(skb);
+        return;
+    }
+    ssv_sta_priv->ampdu_tid[tid_no].mib.ampdu_mib_BA_counter++;
+    aggr_num = ssv6006_ba_map_walker(&(ssv_sta_priv->ampdu_tid[tid_no]), ssn,
+                                     sn_bit_map, &acked_num, &ssv_sta_priv->ampdu_ssn[i], sc);
+    memset((void*) &ssv_sta_priv->ampdu_ssn[i], 0, sizeof(struct aggr_ssn));
+    ssv6006_ampdu_ba_notify(sc, sta, tx_pkt_run_no, aggr_num, acked_num);
+    dev_kfree_skb_any(skb);
+}
+static void ssv6006_adj_config(struct ssv_hw *sh)
+{
+    int dev_type;
+    if (sh->cfg.force_chip_identity)
+        sh->cfg.chip_identity = sh->cfg.force_chip_identity;
+    switch (sh->cfg.chip_identity) {
+    case SV6255P:
+    case SV6256P:
+        sh->cfg.hw_caps |= SSV6200_HW_CAP_5GHZ;
+        break;
+    case SV6155P:
+    case SV6156P:
+    case SV6166P:
+    case SV6166F:
+    case SV6151P_SV6152P:
+        printk("not support 5G for this chip!! \n");
+        sh->cfg.hw_caps = sh->cfg.hw_caps & (~(SSV6200_HW_CAP_5GHZ));
+        break;
+    default:
+        printk("unknown chip\n");
+        break;
+    }
+    if (strstr(sh->priv->chip_id, SSV6006D)) {
+        printk("not support 5G for this chip!! \n");
+        sh->cfg.hw_caps = sh->cfg.hw_caps & (~(SSV6200_HW_CAP_5GHZ));
+    }
+    if (sh->cfg.use_wpa2_only) {
+        printk("%s: use_wpa2_only set to 1, force it to 0 \n", __func__);
+        sh->cfg.use_wpa2_only = 0;
+    }
+    if (sh->cfg.rx_burstread) {
+        printk("%s: rx_burstread set to 1, force it to 0 \n", __func__);
+        sh->cfg.rx_burstread = false;
+    }
+    dev_type = HCI_DEVICE_TYPE(sh->hci.hci_ctrl);
+    if (dev_type == SSV_HWIF_INTERFACE_USB) {
+        if (sh->cfg.hw_caps & SSV6200_HW_CAP_HCI_RX_AGGR) {
+            printk("%s: clear hci rx aggregation setting \n", __func__);
+            sh->cfg.hw_caps = sh->cfg.hw_caps & (~(SSV6200_HW_CAP_HCI_RX_AGGR));
+        }
+        if ((sh->cfg.crystal_type == SSV6XXX_IQK_CFG_XTAL_26M) || (sh->cfg.crystal_type == SSV6XXX_IQK_CFG_XTAL_24M)) {
+            sh->cfg.crystal_type = SSV6XXX_IQK_CFG_XTAL_40M;
+            printk("%s: for USB, change iqk config crystal_type to %d \n", __func__, sh->cfg.crystal_type);
+        }
+    }
+    if ((sh->cfg.tx_stuck_detect) && (dev_type == SSV_HWIF_INTERFACE_SDIO)) {
+        printk("%s: tx_stuck_detect set to 1, force it to 0 \n", __func__);
+        sh->cfg.tx_stuck_detect = false;
+    }
+    if (strstr(sh->priv->chip_id, SSV6006C)) {
+        printk("%s: clear hw beacon \n", __func__);
+        sh->cfg.hw_caps &= ~SSV6200_HW_CAP_BEACON;
+    }
+}
+static void ssv6006_get_fw_name(u8 *fw_name)
+{
+    strcpy(fw_name, "ssv6x5x-sw.bin");
+}
+static bool ssv6006_need_sw_cipher(struct ssv_hw *sh)
+{
+    if (sh->cfg.use_sw_cipher) {
+        return true;
+    } else {
+        return false;
+    }
+}
+static void ssv6006_send_tx_poll_cmd(struct ssv_hw *sh, u32 type)
+{
+    struct sk_buff *skb;
+    struct cfg_host_cmd *host_cmd;
+    int retval = 0;
+    if (!sh->cfg.tx_stuck_detect)
+        return;
+    skb = ssv_skb_alloc(sh->sc, HOST_CMD_HDR_LEN);
+    if (!skb) {
+        printk("%s(): Fail to alloc cmd buffer.\n", __FUNCTION__);
+    }
+    skb_put(skb, HOST_CMD_HDR_LEN);
+    host_cmd = (struct cfg_host_cmd *)skb->data;
+    memset(host_cmd, 0x0, sizeof(struct cfg_host_cmd));
+    host_cmd->c_type = HOST_CMD;
+    host_cmd->RSVD0 = type;
+    host_cmd->h_cmd = (u8)SSV6XXX_HOST_CMD_TX_POLL;
+    host_cmd->len = skb->len;
+    retval = HCI_SEND_CMD(sh, skb);
+    if (retval)
+        printk("%s(): Fail to send tx polling cmd\n", __FUNCTION__);
+    ssv_skb_free(sh->sc, skb);
+}
+static void ssv6006_cmd_set_hwq_limit(struct ssv_hw *sh, int argc, char *argv[])
+{
+    struct ssv_cmd_data *cmd_data = &sh->sc->cmd_data;
+    char *endp;
+    if ( argc != 3) return;
+    if (!strcmp(argv[1], "bk")) {
+        sh->cfg.bk_txq_size = simple_strtoul(argv[2], &endp, 0);
+    } else if (!strcmp(argv[1], "be")) {
+        sh->cfg.be_txq_size = simple_strtoul(argv[2], &endp, 0);
+    } else if (!strcmp(argv[1], "vi")) {
+        sh->cfg.vi_txq_size = simple_strtoul(argv[2], &endp, 0);
+    } else if (!strcmp(argv[1], "vo")) {
+        sh->cfg.vo_txq_size = simple_strtoul(argv[2], &endp, 0);
+    } else if (!strcmp(argv[1], "mng")) {
+        sh->cfg.manage_txq_size = simple_strtoul(argv[2], &endp, 0);
+    } else {
+        snprintf_res(cmd_data,"\t\t %s is unknown!\n", argv[1]);
+    }
+}
+static void ssv6006_flash_read_all_map(struct ssv_hw *sh)
+{
+    struct file *fp = (struct file *)NULL;
+    int rdlen = 0, i = 0;
+    struct ssv6006_flash_layout_table flash_table;
+    memset(&flash_table, 0, sizeof(struct ssv6006_flash_layout_table));
+    if (sh->cfg.flash_bin_path[0] != 0x00)
+        fp = filp_open(sh->cfg.flash_bin_path, O_RDONLY, 0);
+    else
+        fp = filp_open(DEFAULT_CFG_BIN_NAME, O_RDONLY, 0);
+    if (IS_ERR(fp) || fp == NULL)
+        fp = filp_open(SEC_CFG_BIN_NAME, O_RDONLY, 0);
+    if (IS_ERR(fp) || fp == NULL) {
+        printk("flash_file %s not found\n", DEFAULT_CFG_BIN_NAME);
+        return;
+    }
+    rdlen = kernel_read(fp, fp->f_pos, (u8 *)&flash_table, sizeof(struct ssv6006_flash_layout_table));
+    filp_close((struct file *)fp, NULL);
+    if (rdlen < 0)
+        return;
+#define SV6155P_IC 0x6155
+#define SV6156P_IC 0x6156
+#define SV6255P_IC 0x6255
+#define SV6256P_IC 0x6256
+    if (!((flash_table.ic == SV6155P_IC) ||
+          (flash_table.ic == SV6156P_IC) ||
+          (flash_table.ic == SV6255P_IC) ||
+          (flash_table.ic == SV6256P_IC))) {
+        printk("Invalid flash table [ic=0x%04x]\n", flash_table.ic);
+        BUG_ON(1);
+    }
+    sh->sc->thermal_monitor = true;
+    sh->flash_config.exist = true;
+    sh->flash_config.dcdc = flash_table.dcdc;
+    sh->cfg.volt_regulator = ((sh->flash_config.dcdc) ? SSV6XXX_VOLT_DCDC_CONVERT : SSV6XXX_VOLT_LDO_CONVERT);
+    sh->flash_config.padpd = flash_table.padpd;
+    sh->cfg.disable_dpd = ((sh->flash_config.padpd) ? 0x0 : 0x1f);
+    sh->flash_config.xtal_offset_tempe_state = SSV_TEMPERATURE_NORMAL;
+    sh->flash_config.xtal_offset_high_boundary = flash_table.xtal_offset_high_boundary;
+    sh->flash_config.xtal_offset_low_boundary = flash_table.xtal_offset_low_boundary;
+    sh->flash_config.band_gain_tempe_state = SSV_TEMPERATURE_NORMAL;
+    sh->flash_config.band_gain_high_boundary = flash_table.band_gain_high_boundary;
+    sh->flash_config.band_gain_low_boundary = flash_table.band_gain_low_boundary;
+    sh->flash_config.rt_config.xtal_offset = flash_table.xtal_offset_rt_config;
+    sh->flash_config.lt_config.xtal_offset = flash_table.xtal_offset_lt_config;
+    sh->flash_config.ht_config.xtal_offset = flash_table.xtal_offset_ht_config;
+    sh->flash_config.g_band_pa_bias0 = flash_table.g_band_pa_bias0;
+    sh->flash_config.g_band_pa_bias1 = flash_table.g_band_pa_bias1;
+    sh->flash_config.a_band_pa_bias0 = flash_table.a_band_pa_bias0;
+    sh->flash_config.a_band_pa_bias1 = flash_table.a_band_pa_bias1;
+#define SIZE_G_BAND_GAIN (sizeof(sh->flash_config.rt_config.g_band_gain) / sizeof((sh->flash_config.rt_config.g_band_gain)[0]))
+    for (i = 0; i < SIZE_G_BAND_GAIN; i++) {
+        sh->flash_config.rt_config.g_band_gain[i] = flash_table.g_band_gain_rt[i];
+        sh->flash_config.lt_config.g_band_gain[i] = flash_table.g_band_gain_lt[i];
+        sh->flash_config.ht_config.g_band_gain[i] = flash_table.g_band_gain_ht[i];
+    }
+#define SIZE_A_BAND_GAIN (sizeof(sh->flash_config.rt_config.a_band_gain) / sizeof((sh->flash_config.rt_config.a_band_gain)[0]))
+    for (i = 0; i < SIZE_A_BAND_GAIN; i++) {
+        sh->flash_config.rt_config.a_band_gain[i] = flash_table.a_band_gain_rt[i];
+        sh->flash_config.lt_config.a_band_gain[i] = flash_table.a_band_gain_lt[i];
+        sh->flash_config.ht_config.a_band_gain[i] = flash_table.a_band_gain_ht[i];
+    }
+#define SIZE_RATE_DELTA (sizeof(sh->flash_config.rate_delta) / sizeof((sh->flash_config.rate_delta)[0]))
+    for (i = 0; i < SIZE_RATE_DELTA; i++) {
+        sh->flash_config.rate_delta[i] = flash_table.rate_delta[i];
+    }
+    if (!(sh->sc->log_ctrl & LOG_FLASH_BIN))
+        return;
+    printk("flash.bin configuration\n");
+    printk("xtal_offset_boundary, high = %d, low = %d\n",
+           sh->flash_config.xtal_offset_high_boundary, sh->flash_config.xtal_offset_low_boundary);
+    printk("band_gain_boundary, high = %d, low = %d\n",
+           sh->flash_config.band_gain_high_boundary, sh->flash_config.band_gain_low_boundary);
+    printk("xtal_offset, rt = 0x%04x, lt = 0x%04x, ht = 0x%04x\n",
+           sh->flash_config.rt_config.xtal_offset,
+           sh->flash_config.lt_config.xtal_offset,
+           sh->flash_config.ht_config.xtal_offset);
+    printk("g_band_pa_bias0 = 0x%08x, g_band_pa_bias1 = 0x%08x\n",
+           sh->flash_config.g_band_pa_bias0, sh->flash_config.g_band_pa_bias1);
+    printk("a_band_pa_bias0 = 0x%08x, a_band_pa_bias1 = 0x%08x\n",
+           sh->flash_config.a_band_pa_bias0, sh->flash_config.a_band_pa_bias1);
+    printk("g band gain:\trt\tlt\tht\n");
+    for (i = 0; i < SIZE_G_BAND_GAIN; i++) {
+        printk("\t\t\t0x%x,\t0x%x,\t0x%x", sh->flash_config.rt_config.g_band_gain[i],
+               sh->flash_config.lt_config.g_band_gain[i],
+               sh->flash_config.ht_config.g_band_gain[i]);
+    }
+    printk("\n");
+    printk("a band gain:\trt\tlt\tht\n");
+    for (i = 0; i < SIZE_A_BAND_GAIN; i++) {
+        printk("\t\t\t0x%x,\t0x%x,\t0x%x", sh->flash_config.rt_config.a_band_gain[i],
+               sh->flash_config.lt_config.a_band_gain[i],
+               sh->flash_config.ht_config.a_band_gain[i]);
+    }
+    printk("\n");
+    printk("rate delta: ");
+    for (i = 0; i < SIZE_RATE_DELTA; i++)
+        printk("%x, ", sh->flash_config.rate_delta[i]);
+    return;
+}
+void ssv_attach_ssv6006_common(struct ssv_hal_ops *hal_ops)
+{
+    hal_ops->alloc_hw = ssv6006_alloc_hw;
+    hal_ops->use_hw_encrypt = ssv6006_use_hw_encrypt;
+    hal_ops->if_chk_mac2= ssv6006_if_chk_mac2;
+    hal_ops->get_wsid = ssv6006_get_wsid;
+    hal_ops->add_fw_wsid = ssv6006_add_fw_wsid;
+    hal_ops->del_fw_wsid = ssv6006_del_fw_wsid;
+    hal_ops->enable_fw_wsid = ssv6006_enable_fw_wsid;
+    hal_ops->disable_fw_wsid = ssv6006_disable_fw_wsid;
+    hal_ops->set_fw_hwwsid_sec_type = ssv6006_set_fw_hwwsid_sec_type;
+    hal_ops->wep_use_hw_cipher = ssv6006_wep_use_hw_cipher;
+    hal_ops->pairwise_wpa_use_hw_cipher = ssv6006_pairwise_wpa_use_hw_cipher;
+    hal_ops->group_wpa_use_hw_cipher = ssv6006_group_wpa_use_hw_cipher;
+    hal_ops->chk_if_support_hw_bssid = ssv6006_chk_if_support_hw_bssid;
+    hal_ops->chk_dual_vif_chg_rx_flow = ssv6006_chk_dual_vif_chg_rx_flow;
+    hal_ops->restore_rx_flow = ssv6006_restore_rx_flow;
+    hal_ops->hw_crypto_key_write_wep = ssv6006_hw_crypto_key_write_wep;
+    hal_ops->set_wep_hw_crypto_key = ssv6006_set_wep_hw_crypto_key;
+    hal_ops->put_mic_space_for_hw_ccmp_encrypt = ssv6006_put_mic_space_for_hw_ccmp_encrypt;
+    hal_ops->init_tx_cfg = ssv6006_init_tx_cfg;
+    hal_ops->init_rx_cfg = ssv6006_init_rx_cfg;
+    hal_ops->ampdu_rx_start = ssv6006_ampdu_rx_start;
+    hal_ops->ampdu_ba_handler = ssv6006_ampdu_ba_handler;
+    hal_ops->adj_config = ssv6006_adj_config;
+    hal_ops->get_fw_name = ssv6006_get_fw_name;
+    hal_ops->need_sw_cipher = ssv6006_need_sw_cipher;
+    hal_ops->send_tx_poll_cmd = ssv6006_send_tx_poll_cmd;
+    hal_ops->cmd_hwq_limit = ssv6006_cmd_set_hwq_limit;
+    hal_ops->flash_read_all_map = ssv6006_flash_read_all_map;
+}
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/ssv6006_common.h b/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/ssv6006_common.h
new file mode 100644
index 000000000..63fc23e10
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/ssv6006_common.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __SSV6006_COMMON_H__
+#define __SSV6006_COMMON_H__
+#include <ssv6xxx_common.h>
+#define FW_VERSION_REG ADR_TX_SEG
+#define M_ENG_CPU 0x00
+#define M_ENG_HWHCI 0x01
+#define M_ENG_EMPTY 0x02
+#define M_ENG_ENCRYPT 0x03
+#define M_ENG_MACRX 0x04
+#define M_ENG_MIC 0x05
+#define M_ENG_TX_EDCA0 0x06
+#define M_ENG_TX_EDCA1 0x07
+#define M_ENG_TX_EDCA2 0x08
+#define M_ENG_TX_EDCA3 0x09
+#define M_ENG_TX_MNG 0x0A
+#define M_ENG_ENCRYPT_SEC 0x0B
+#define M_ENG_MIC_SEC 0x0C
+#define M_ENG_RESERVED_1 0x0D
+#define M_ENG_RESERVED_2 0x0E
+#define M_ENG_TRASH_CAN 0x0F
+#define M_ENG_MAX (M_ENG_TRASH_CAN+1)
+#define M_CPU_HWENG 0x00
+#define M_CPU_TXL34CS 0x01
+#define M_CPU_RXL34CS 0x02
+#define M_CPU_DEFRAG 0x03
+#define M_CPU_EDCATX 0x04
+#define M_CPU_RXDATA 0x05
+#define M_CPU_RXMGMT 0x06
+#define M_CPU_RXCTRL 0x07
+#define M_CPU_FRAG 0x08
+#define M_CPU_TXTPUT 0x09
+#ifndef ID_TRAP_SW_TXTPUT
+#define ID_TRAP_SW_TXTPUT 50
+#endif
+#define M0_TXREQ 0
+#define M1_TXREQ 1
+#define M2_TXREQ 2
+#define M0_RXEVENT 3
+#define M2_RXEVENT 4
+#define HOST_CMD 5
+#define HOST_EVENT 6
+#define RATE_RPT 7
+#define SSV_NUM_HW_STA 8
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/ssv6006_mac.h b/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/ssv6006_mac.h
new file mode 100644
index 000000000..7996e6c3e
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/ssv6006_mac.h
@@ -0,0 +1,179 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV6006_MAC_H_
+#define _SSV6006_MAC_H_
+#define FPGA_PHY_5 "5."
+#define FPGA_PHY_4 ((u64)0x2015123100171848)
+#define RF_GEMINA 0x2B9
+#define RF_TURISMOA 0x06579597
+#define ADR_GEMINA_TRX_VER 0xCBB0E008
+#define ADR_TURISMO_TRX_VER 0xCBC0E008
+#define CHIP_TYPE_CHIP 0xA0
+#define CHIP_TYPE_FPGA 0x0F
+#define SSV6006_NUM_HW_STA 8
+#define SSV6006_NUM_HW_BSSID 2
+#define SSV6006_RX_BA_MAX_SESSIONS 255
+#define PBUF_BASE_ADDR 0x80000000
+#define PBUF_ADDR_SHIFT 16
+#define PBUF_MapPkttoID(_pkt) (((u32)_pkt&0x0FFF0000)>>PBUF_ADDR_SHIFT)
+#define PBUF_MapIDtoPkt(_id) (PBUF_BASE_ADDR|((_id)<<PBUF_ADDR_SHIFT))
+struct ssv6006_rc_idx {
+    u8 rate_idx:3;
+    u8 mf:1;
+    u8 long_short:1;
+    u8 ht40:1;
+    u8 phy_mode:2;
+};
+#define SSV6006RC_MAX_RATE_RETRY 10
+#define SSV6006RC_MAX_RATE_SERIES 4
+#define SSV6006RC_PHY_MODE_MSK 0xc0
+#define SSV6006RC_PHY_MODE_SFT 6
+#define SSV6006RC_B_MODE 0
+#define SSV6006RC_G_MODE 2
+#define SSV6006RC_N_MODE 3
+#define SSV6006RC_20_40_MSK 0x20
+#define SSV6006RC_20_40_SFT 5
+#define SSV6006RC_HT20 0
+#define SSV6006RC_HT40 1
+#define SSV6006RC_LONG_SHORT_MSK 0x10
+#define SSV6006RC_LONG_SHORT_SFT 4
+#define SSV6006RC_LONG 0
+#define SSV6006RC_SHORT 1
+#define SSV6006RC_MF_MSK 0x08
+#define SSV6006RC_MF_SFT 3
+#define SSV6006RC_MIX 0
+#define SSV6006RC_GREEN 1
+#define SSV6006RC_B_RATE_MSK 0x3
+#define SSV6006RC_RATE_MSK 0x7
+#define SSV6006RC_RATE_SFT 0
+#define SSV6006RC_B_1M 0
+#define SSV6006RC_B_2M 1
+#define SSV6006RC_B_5_5M 2
+#define SSV6006RC_B_11M 3
+#define SSV6006RC_B_MAX_RATE 4
+#define DOT11_G_RATE_IDX_OFFSET 4
+#define SSV6006RC_G_6M 0
+#define SSV6006RC_G_9M 1
+#define SSV6006RC_G_12M 2
+#define SSV6006RC_G_18M 3
+#define SSV6006RC_G_24M 4
+#define SSV6006RC_G_36M 5
+#define SSV6006RC_G_48M 6
+#define SSV6006RC_G_54M 7
+#define SSV6006RC_N_MCS0 0
+#define SSV6006RC_N_MCS1 1
+#define SSV6006RC_N_MCS2 2
+#define SSV6006RC_N_MCS3 3
+#define SSV6006RC_N_MCS4 4
+#define SSV6006RC_N_MCS5 5
+#define SSV6006RC_N_MCS6 6
+#define SSV6006RC_N_MCS7 7
+#define SSV6006RC_MAX_RATE 8
+#define SSV6006_EDCCA_AVG_T_6US 0x0
+#define SSV6006_EDCCA_AVG_T_12US 0x1
+#define SSV6006_EDCCA_AVG_T_25US 0x2
+#define SSV6006_EDCCA_AVG_T_51US 0x3
+#define SSV6006_EDCCA_AVG_T_102US 0x4
+#define SSV6006_EDCCA_AVG_T_204US 0x5
+#define SSV6006_EDCCA_AVG_T_409US 0x6
+#define SSV6006_EDCCA_AVG_T_819US 0x7
+enum ssv6006_lpbk_sec {
+    SSV6006_CMD_LPBK_SEC_AUTO = 0,
+    SSV6006_CMD_LPBK_SEC_WEP64,
+    SSV6006_CMD_LPBK_SEC_WEP128,
+    SSV6006_CMD_LPBK_SEC_TKIP,
+    SSV6006_CMD_LPBK_SEC_AES,
+    SSV6006_CMD_LPBK_SEC_OPEN,
+    MAX_SSV6006_CMD_LPBK_SEC
+};
+enum ssv6006_lpbk_type {
+    SSV6006_CMD_LPBK_TYPE_PHY = 0,
+    SSV6006_CMD_LPBK_TYPE_MAC,
+    SSV6006_CMD_LPBK_TYPE_HCI,
+    SSV6006_CMD_LPBK_TYPE_2GRF,
+    SSV6006_CMD_LPBK_TYPE_5GRF,
+    MAX_SSV6006_CMD_LPBK_TYPE
+};
+#define DEFAULT_CFG_BIN_NAME "/tmp/flash.bin"
+#define SEC_CFG_BIN_NAME "/system/etc/wifi/ssv6x5x/flash.bin"
+#define SSV6006_HW_SEC_TABLE_SIZE sizeof(struct ssv6006_hw_sec)
+#define SSV6006_HW_KEY_SIZE 32
+#define SSV6006_PAIRWISE_KEY_OFFSET 12
+#define SSV6006_GROUP_KEY_OFFSET 12
+#define SSV6006_SECURITY_KEY_LEN (32)
+struct ssv6006_hw_key {
+    u8 key[SSV6006_SECURITY_KEY_LEN];
+} __attribute__((packed));
+struct ssv6006_hw_sta_key {
+    u8 pair_key_idx;
+    u8 pair_cipher_type;
+    u8 valid;
+    u8 reserve[1];
+    u32 tx_pn_l;
+    u32 tx_pn_h;
+    struct ssv6006_hw_key pair;
+} __attribute__((packed));
+struct ssv6006_bss {
+    u8 group_key_idx;
+    u8 group_cipher_type;
+    u8 reserve[2];
+    u32 tx_pn_l;
+    u32 tx_pn_h;
+    struct ssv6006_hw_key group_key[4];
+} __attribute__((packed));
+struct ssv6006_hw_sec {
+    struct ssv6006_bss bss_group[2];
+    struct ssv6006_hw_sta_key sta_key[8];
+} __attribute__((packed));
+struct ssv6006_flash_layout_table {
+    u16 ic;
+    u16 sid;
+    u32 date;
+    u32 version:24;
+    u32 RSVD0:8;
+    u8 dcdc;
+    u8 padpd;
+    u16 RSVD1;
+    u16 xtal_offset_rt_config;
+    u16 xtal_offset_lt_config;
+    u16 xtal_offset_ht_config;
+    u16 RSVD2;
+    u8 xtal_offset_low_boundary;
+    u8 xtal_offset_high_boundary;
+    u8 band_gain_low_boundary;
+    u8 band_gain_high_boundary;
+    u32 RSVD3;
+    u8 g_band_gain_rt[7];
+    u8 RSVD4;
+    u32 g_band_pa_bias0;
+    u32 g_band_pa_bias1;
+    u8 g_band_gain_lt[7];
+    u8 RSVD5;
+    u8 g_band_gain_ht[7];
+    u8 RSVD6;
+    u8 rate_delta[13];
+    u8 RSVD7;
+    u16 RSVD8;
+    u8 a_band_gain_rt[4];
+    u32 RSVD9;
+    u32 a_band_pa_bias0;
+    u32 a_band_pa_bias1;
+    u8 a_band_gain_lt[4];
+    u8 a_band_gain_ht[4];
+    u32 RSVD10;
+    u32 RSVD11;
+} __attribute__((packed));
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/ssv6006_phy.c b/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/ssv6006_phy.c
new file mode 100644
index 000000000..0f2bfafbe
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/ssv6006_phy.c
@@ -0,0 +1,2373 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifdef ECLIPSE
+#include <ssv_mod_conf.h>
+#endif
+#include <linux/version.h>
+#if ((defined SSV_SUPPORT_HAL) && (defined SSV_SUPPORT_SSV6006))
+#include <linux/etherdevice.h>
+#include <ssv6200.h>
+#include "ssv6006_mac.h"
+#include "ssv6006C_reg.h"
+#include "ssv6006C_aux.h"
+#include <smac/dev.h>
+#include <smac/ssv_rc_minstrel.h>
+#include <smac/ssv_rc.h>
+#include <smac/ssv_skb.h>
+#include <hal.h>
+#include "ssv6006_priv.h"
+#include "ssv6006_priv_normal.h"
+#include <ssvdevice/ssv_cmd.h>
+#include <linux_80211.h>
+#include "turismo_common.h"
+#include "ssv6006_priv.h"
+#include <linux/etherdevice.h>
+
+#define DEBUG_MITIGATE_CCI
+const size_t ssv6006_tx_desc_length = sizeof(struct ssv6006_tx_desc);
+const size_t ssv6006_rx_desc_length = sizeof(struct ssv6006_rx_desc) + sizeof (struct ssv6006_rxphy_info);
+static const u32 rc_b_data_rate[4] = {1000, 2000, 5500, 11000};
+static const u32 rc_g_data_rate[8] = {6000, 9000, 12000, 18000, 24000, 36000, 48000, 54000};
+static const u32 rc_n_ht20_lgi_data_rate[8] = { 6500, 13000, 19500, 26000, 39000, 52000, 58500, 65000};
+static const u32 rc_n_ht20_sgi_data_rate[8] = { 7200, 14400, 21700, 28900, 43300, 57800, 65000, 72200};
+static const u32 rc_n_ht40_lgi_data_rate[8] = {13500, 27000, 40500, 54000, 81000, 108000, 121500, 135000};
+static const u32 rc_n_ht40_sgi_data_rate[8] = {15000, 30000, 45000, 60000, 90000, 120000, 135000, 150000};
+static u8 ssv6006_get_tx_desc_drate(struct ssv6006_tx_desc *tx_desc, int idx)
+{
+    switch (idx) {
+    case 0:
+        return tx_desc->drate_idx0;
+    case 1:
+        return tx_desc->drate_idx1;
+    case 2:
+        return tx_desc->drate_idx2;
+    case 3:
+        return tx_desc->drate_idx3;
+    default:
+        return 0;
+    }
+}
+static void ssv6006_set_tx_desc_drate(struct ssv6006_tx_desc *tx_desc, int idx, u8 drate)
+{
+    switch (idx) {
+    case 0:
+        tx_desc->drate_idx0 = drate;
+        break;
+    case 1:
+        tx_desc->drate_idx1 = drate;
+        break;
+    case 2:
+        tx_desc->drate_idx2 = drate;
+        break;
+    case 3:
+        tx_desc->drate_idx3 = drate;
+        break;
+    default:
+        printk("%s: invalid rate index[%d]\n", __FUNCTION__, idx);
+        break;
+    }
+}
+static void ssv6006_set_tx_desc_trycnt(struct ssv6006_tx_desc *tx_desc, int idx, u8 trycnt)
+{
+    switch (idx) {
+    case 0:
+        tx_desc->try_cnt0 = trycnt;
+        break;
+    case 1:
+        tx_desc->try_cnt1 = trycnt;
+        break;
+    case 2:
+        tx_desc->try_cnt2 = trycnt;
+        break;
+    case 3:
+        tx_desc->try_cnt3 = trycnt;
+        break;
+    default:
+        printk("%s: invalid rate index[%d]\n", __FUNCTION__, idx);
+        break;
+    }
+}
+static void ssv6006_set_tx_desc_crate(struct ssv6006_tx_desc *tx_desc, int idx, u8 crate)
+{
+    switch (idx) {
+    case 0:
+        tx_desc->crate_idx0 = crate;
+        break;
+    case 1:
+        tx_desc->crate_idx1 = crate;
+        break;
+    case 2:
+        tx_desc->crate_idx2 = crate;
+        break;
+    case 3:
+        tx_desc->crate_idx3 = crate;
+        break;
+    default:
+        printk("%s: invalid rate index[%d]\n", __FUNCTION__, idx);
+        break;
+    }
+}
+static bool ssv6006_get_tx_desc_last_rate(struct ssv6006_tx_desc *tx_desc, int idx)
+{
+    switch (idx) {
+    case 0:
+        return tx_desc->is_last_rate0;
+    case 1:
+        return tx_desc->is_last_rate1;
+    case 2:
+        return tx_desc->is_last_rate2;
+    case 3:
+        return tx_desc->is_last_rate3;
+    default:
+        return false;
+    }
+}
+static u32 ssv6006_get_data_rates(struct ssv6006_rc_idx *rc_word)
+{
+    union {
+        struct ssv6006_rc_idx rcword;
+        u8 val;
+    } u;
+    u.rcword = *rc_word;
+    switch (rc_word->phy_mode) {
+    case SSV6006RC_B_MODE:
+        return rc_b_data_rate[rc_word->rate_idx];
+    case SSV6006RC_G_MODE:
+        return rc_g_data_rate[rc_word->rate_idx];
+    case SSV6006RC_N_MODE:
+        if (rc_word->long_short == SSV6006RC_LONG) {
+            if (rc_word->ht40 == SSV6006RC_HT40) {
+                return rc_n_ht40_lgi_data_rate[rc_word->rate_idx];
+            } else {
+                return rc_n_ht20_lgi_data_rate[rc_word->rate_idx];
+            }
+        } else {
+            if (rc_word->ht40 == SSV6006RC_HT40) {
+                return rc_n_ht40_sgi_data_rate[rc_word->rate_idx];
+            } else {
+                return rc_n_ht20_sgi_data_rate[rc_word->rate_idx];
+            }
+        }
+    default:
+        printk(" %s: invalid rate control word %x\n", __func__, u.val);
+        memset(rc_word, 0, sizeof(struct ssv6006_rc_idx));
+        return 1000;
+    }
+}
+static void ssv6006_set_frame_duration(struct ssv_softc *sc, struct ieee80211_tx_info *info,
+                                       struct ssv6006_rc_idx *drate_idx, struct ssv6006_rc_idx *crate_idx,
+                                       u16 len, struct ssv6006_tx_desc *tx_desc, u32 *nav)
+{
+    u32 frame_time=0, ack_time = 0;
+    u32 drate_kbps=0, crate_kbps=0;
+    u32 rts_cts_nav[SSV6006RC_MAX_RATE_SERIES] = {0, 0, 0, 0};
+    u32 l_length[SSV6006RC_MAX_RATE_SERIES] = {0, 0, 0, 0};
+    bool ctrl_short_preamble=false, is_sgi, is_ht40;
+    bool is_ht, is_gf, do_rts_cts;
+    int d_phy,c_phy, i, mcsidx;
+    struct ssv6006_rc_idx *drate, *crate;
+    bool last_rate = false;
+    for (i = 0; i < SSV6006RC_MAX_RATE_SERIES ; i++) {
+        drate = &drate_idx[i];
+        mcsidx = drate->rate_idx;
+        is_sgi = drate->long_short;
+        ctrl_short_preamble = drate->long_short;
+        is_ht40 = drate->ht40;
+        is_ht = (drate->phy_mode == SSV6006RC_N_MODE);
+        is_gf = drate->mf;
+        drate_kbps = ssv6006_get_data_rates(drate);
+        crate = &crate_idx[i];
+        crate_kbps = ssv6006_get_data_rates(crate);
+        frame_time = 0 ;
+        ack_time = 0;
+        *nav = 0;
+        if (is_ht) {
+            frame_time = ssv6xxx_ht_txtime(mcsidx,
+                                           len, is_ht40, is_sgi, is_gf);
+            d_phy = WLAN_RC_PHY_OFDM;
+        } else {
+            if (drate->phy_mode == SSV6006RC_B_MODE)
+                d_phy = WLAN_RC_PHY_CCK;
+            else
+                d_phy = WLAN_RC_PHY_OFDM;
+            frame_time = ssv6xxx_non_ht_txtime(d_phy, drate_kbps,
+                                               len, ctrl_short_preamble);
+        }
+        if (crate->phy_mode == SSV6006RC_B_MODE)
+            c_phy = WLAN_RC_PHY_CCK;
+        else
+            c_phy = WLAN_RC_PHY_OFDM;
+        if (tx_desc->unicast) {
+            int threshold;
+            if (info->flags & IEEE80211_TX_CTL_AMPDU) {
+                ack_time = ssv6xxx_non_ht_txtime(c_phy,
+                                                 crate_kbps, BA_LEN, crate->long_short);
+            } else {
+                ack_time = ssv6xxx_non_ht_txtime(c_phy,
+                                                 crate_kbps, ACK_LEN, crate->long_short);
+            }
+            sc->ack_counter++;
+            if ((sc->sh->cfg.cci & CCI_P1) || (sc->sh->cfg.cci & CCI_P2)) {
+                if (sc->sh->cfg.cci & CCI_P2) {
+                    threshold = 1;
+                } else {
+                    threshold = 0;
+                }
+                if (sc->ack_counter > threshold) {
+                    ack_time += 100;
+                    sc->ack_counter = 0;
+                }
+            }
+        }
+        switch (i) {
+        case 0:
+            do_rts_cts = tx_desc->do_rts_cts0;
+            break;
+        case 1:
+            do_rts_cts = tx_desc->do_rts_cts1;
+            break;
+        case 2:
+            do_rts_cts = tx_desc->do_rts_cts2;
+            break;
+        case 3:
+            do_rts_cts = tx_desc->do_rts_cts3;
+            break;
+        default:
+            do_rts_cts = tx_desc->do_rts_cts0;
+            break;
+        }
+        if (do_rts_cts & IEEE80211_TX_RC_USE_RTS_CTS) {
+            rts_cts_nav[i] = frame_time;
+            rts_cts_nav[i] += ack_time;
+            rts_cts_nav[i] += ssv6xxx_non_ht_txtime(c_phy,
+                                                    crate_kbps, CTS_LEN, crate->long_short);
+        } else if (do_rts_cts & IEEE80211_TX_RC_USE_CTS_PROTECT) {
+            rts_cts_nav[i] = frame_time;
+            rts_cts_nav[i] += ack_time;
+        } else {
+            rts_cts_nav[i] = 0;
+        }
+        if (is_ht) {
+            l_length[i] = frame_time - HT_SIFS_TIME;
+            l_length[i] = ((l_length[i]-(HT_SIGNAL_EXT+20))+3)>>2;
+            l_length[i] += ((l_length[i]<<1) - 3);
+        } else {
+            l_length[i] = 0;
+        }
+        *nav++ = ack_time ;
+        last_rate = ssv6006_get_tx_desc_last_rate(tx_desc, i);
+        if (last_rate)
+            break;
+    }
+    tx_desc->rts_cts_nav0 = rts_cts_nav[0];
+    tx_desc->rts_cts_nav1 = rts_cts_nav[1];
+    tx_desc->rts_cts_nav2 = rts_cts_nav[2];
+    tx_desc->rts_cts_nav3 = rts_cts_nav[3];
+    tx_desc->dl_length0 = l_length[0];
+    tx_desc->dl_length1 = l_length[1];
+    tx_desc->dl_length2 = l_length[2];
+    tx_desc->dl_length3 = l_length[3];
+}
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,7,0)
+static u8 ssv6006_drword_to_crword(struct ssv6006_tx_desc *tx_desc, int idx, enum nl80211_band band)
+#else
+static u8 ssv6006_drword_to_crword(struct ssv6006_tx_desc *tx_desc, int idx, enum ieee80211_band band)
+#endif
+{
+    union {
+        struct ssv6006_rc_idx rc_word;
+        u8 val;
+    } d_rate, c_rate;
+    d_rate.val = ssv6006_get_tx_desc_drate(tx_desc, idx);
+    c_rate.val = 0;
+    switch (d_rate.rc_word.phy_mode) {
+    case SSV6006RC_B_MODE:
+        c_rate.rc_word.phy_mode = SSV6006RC_B_MODE;
+        c_rate.rc_word.rate_idx = SSV6006RC_B_1M;
+        break;
+    case SSV6006RC_G_MODE:
+        if ((d_rate.rc_word.rate_idx == SSV6006RC_G_6M) ||
+            (d_rate.rc_word.rate_idx == SSV6006RC_G_9M) ||
+            (d_rate.rc_word.rate_idx == SSV6006RC_G_12M)) {
+            c_rate.rc_word.phy_mode = SSV6006RC_G_MODE;
+            c_rate.rc_word.rate_idx = SSV6006RC_G_6M;
+        } else if ((d_rate.rc_word.rate_idx == SSV6006RC_G_18M) ||
+                   (d_rate.rc_word.rate_idx == SSV6006RC_G_24M)) {
+            c_rate.rc_word.phy_mode = SSV6006RC_G_MODE;
+            c_rate.rc_word.rate_idx = SSV6006RC_G_12M;
+        } else {
+            c_rate.rc_word.phy_mode = SSV6006RC_G_MODE;
+            c_rate.rc_word.rate_idx = SSV6006RC_G_24M;
+        }
+        break;
+    case SSV6006RC_N_MODE:
+        c_rate.rc_word.ht40 = d_rate.rc_word.ht40;
+        if ((d_rate.rc_word.rate_idx == SSV6006RC_N_MCS0) ||
+            (d_rate.rc_word.rate_idx == SSV6006RC_N_MCS1)) {
+            c_rate.rc_word.phy_mode = SSV6006RC_G_MODE;
+            c_rate.rc_word.rate_idx = SSV6006RC_G_6M;
+        } else if ((d_rate.rc_word.rate_idx == SSV6006RC_N_MCS2) ||
+                   (d_rate.rc_word.rate_idx == SSV6006RC_N_MCS3)) {
+            c_rate.rc_word.phy_mode = SSV6006RC_G_MODE;
+            c_rate.rc_word.rate_idx = SSV6006RC_G_12M;
+        } else {
+            c_rate.rc_word.phy_mode = SSV6006RC_G_MODE;
+            c_rate.rc_word.rate_idx = SSV6006RC_G_24M;
+        }
+        break;
+    default:
+        printk("%s:Don't support date rate[%02x]\n", __FUNCTION__, d_rate.val);
+        if (band == INDEX_80211_BAND_5GHZ)
+            c_rate.rc_word.phy_mode = SSV6006RC_G_MODE;
+        break;
+    }
+    ssv6006_set_tx_desc_crate(tx_desc, idx, c_rate.val);
+    return c_rate.val;
+}
+static void ssv6006_force_lowest_rate(struct ieee80211_tx_info *info,
+                                      struct ssv6006_tx_desc *tx_desc, struct ssv6006_rc_idx *drate_idx, struct ieee80211_hdr *hdr)
+{
+    u8 i, *drate_idx_tmp, trycnt;
+    drate_idx_tmp = (u8*) drate_idx;
+    for (i = 0; i < SSV6006RC_MAX_RATE_SERIES; i++) {
+        *drate_idx_tmp = 0;
+        if ((info->band == INDEX_80211_BAND_5GHZ) || (info->control.vif->p2p == true)||(info->flags & IEEE80211_TX_CTL_NO_CCK_RATE)) {
+            *drate_idx_tmp = (SSV6006RC_G_MODE << SSV6006RC_PHY_MODE_SFT) | (SSV6006RC_G_6M << SSV6006RC_RATE_SFT);
+        }
+        ssv6006_set_tx_desc_drate(tx_desc, i, *drate_idx_tmp);
+        trycnt = ((i == 0) ? (is_multicast_ether_addr(hdr->addr1) ? 1 : 15) : 0);
+        ssv6006_set_tx_desc_trycnt(tx_desc, i, trycnt);
+        drate_idx_tmp++;
+    }
+}
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,7,0)
+static void ssv6006_set_data_rcword(struct ssv_softc *sc, struct ssv_sta_priv_data *ssv_sta_priv,
+                                    struct ssv6006_tx_desc *tx_desc, struct ieee80211_tx_info *info,
+                                    struct ssv6006_rc_idx *drate_idx, bool is_mgmt, bool is_nullfunc, enum nl80211_band band,
+                                    struct ieee80211_hdr *hdr, bool no_update_rpt)
+#else
+static void ssv6006_set_data_rcword(struct ssv_softc *sc, struct ssv_sta_priv_data *ssv_sta_priv,
+                                    struct ssv6006_tx_desc *tx_desc, struct ieee80211_tx_info *info,
+                                    struct ssv6006_rc_idx *drate_idx, bool is_mgmt, bool is_nullfunc, enum ieee80211_band band,
+                                    struct ieee80211_hdr *hdr, bool no_update_rpt)
+#endif
+{
+    struct ieee80211_tx_rate *ar = info->control.rates;
+    struct ssv_minstrel_sta_priv *minstrel_sta_priv = NULL;
+    u8 i, *drate_idx_tmp;
+    union {
+        struct ssv6006_rc_idx rc_word;
+        u8 val;
+    } u;
+    if (!ssv_sta_priv) {
+        ssv6006_force_lowest_rate(info, tx_desc, drate_idx, hdr);
+        return;
+    }
+    minstrel_sta_priv = (struct ssv_minstrel_sta_priv *)ssv_sta_priv->rc_info;
+    if (!minstrel_sta_priv || no_update_rpt ||is_mgmt || is_nullfunc) {
+        ssv6006_force_lowest_rate(info, tx_desc, drate_idx, hdr);
+        return;
+    }
+    drate_idx_tmp = (u8*) drate_idx;
+    for (i = 0; i < SSV6006RC_MAX_RATE_SERIES; i++) {
+        *drate_idx_tmp = 0;
+        drate_idx_tmp++;
+    }
+    drate_idx_tmp = (u8*) drate_idx;
+    for (i = 0; i < SSV6006RC_MAX_RATE_SERIES; i++) {
+        u.val = 0;
+        if (ar[i].idx < 0)
+            break;
+        if (ar[i].flags & IEEE80211_TX_RC_MCS) {
+            u.rc_word.phy_mode = SSV6006RC_N_MODE;
+            u.rc_word.rate_idx = (ar[i].idx & SSV6006RC_RATE_MSK);
+            u.rc_word.ht40 = (ar[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? SSV6006RC_HT40 : SSV6006RC_HT20;
+            u.rc_word.long_short = (ar[i].flags & IEEE80211_TX_RC_SHORT_GI) ? SSV6006RC_SHORT : SSV6006RC_LONG;
+            u.rc_word.mf = (ar[i].flags & IEEE80211_TX_RC_GREEN_FIELD) ? SSV6006RC_GREEN :SSV6006RC_MIX;
+        } else {
+            if (band == INDEX_80211_BAND_5GHZ) {
+                u.rc_word.phy_mode = SSV6006RC_G_MODE;
+                u.rc_word.rate_idx = (ar[i].idx & SSV6006RC_RATE_MSK);
+            } else {
+                u.rc_word.phy_mode = (ar[i].idx < DOT11_G_RATE_IDX_OFFSET) ? SSV6006RC_B_MODE : SSV6006RC_G_MODE;
+                if (ar[i].idx < DOT11_G_RATE_IDX_OFFSET)
+                    u.rc_word.rate_idx = (ar[i].idx & 0x3);
+                else
+                    u.rc_word.rate_idx = ((ar[i].idx - DOT11_G_RATE_IDX_OFFSET) & SSV6006RC_RATE_MSK);
+                if (ar[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
+                    u.rc_word.long_short = SSV6006RC_SHORT;
+                if ((u.rc_word.phy_mode == SSV6006RC_B_MODE) && (sc->sh->cfg.auto_rate_enable == false)) {
+                    if (sc->sh->cfg.rc_long_short)
+                        u.rc_word.long_short = SSV6006RC_SHORT;
+                    else
+                        u.rc_word.long_short = SSV6006RC_LONG;
+                }
+            }
+        }
+        ssv6006_set_tx_desc_drate(tx_desc, i, u.val);
+        ssv6006_set_tx_desc_trycnt(tx_desc, i, ar[i].count);
+        *drate_idx_tmp = u.val;
+        drate_idx_tmp++;
+    }
+}
+static void ssv6006_update_txinfo (struct ssv_softc *sc, struct sk_buff *skb)
+{
+    struct ieee80211_hdr *hdr;
+    struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
+    struct ieee80211_sta *sta = NULL;
+    struct ssv_sta_info *sta_info = NULL;
+    struct ssv_sta_priv_data *ssv_sta_priv = NULL;
+    struct ssv_vif_priv_data *vif_priv = (struct ssv_vif_priv_data *)info->control.vif->drv_priv;
+    struct ssv6006_tx_desc *tx_desc = (struct ssv6006_tx_desc *)skb->data;
+    struct ieee80211_tx_rate *tx_drate;
+    int ac, hw_txqid;
+    u32 nav[SSV6006RC_MAX_RATE_SERIES] = {0, 0, 0, 0};
+    union {
+        struct ssv6006_rc_idx rate_idx[SSV6006RC_MAX_RATE_SERIES];
+        u8 val[SSV6006RC_MAX_RATE_SERIES];
+    } dr, cr, dr_to_cr;
+    struct ampdu_hdr_st *ampdu_hdr = (struct ampdu_hdr_st *)skb->head;
+    bool ampdu_retry_frame = false;
+    bool no_update_rpt = false;
+    if (info->flags & IEEE80211_TX_CTL_AMPDU) {
+        sta = ampdu_hdr->ampdu_tid->sta;
+        hdr = (struct ieee80211_hdr *)(skb->data + TXPB_OFFSET + AMPDU_DELIMITER_LEN);
+        ampdu_retry_frame = ieee80211_has_retry(hdr->frame_control);
+    } else {
+        struct SKB_info_st *skb_info = (struct SKB_info_st *)skb->head;
+        sta = skb_info->sta;
+        hdr = (struct ieee80211_hdr *)(skb->data + TXPB_OFFSET);
+        no_update_rpt = skb_info->no_update_rpt;
+    }
+    if (sta) {
+        ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+        sta_info = ssv_sta_priv->sta_info;
+        down_read(&sc->sta_info_sem);
+    }
+    if ((!sc->bq4_dtim) &&
+        (ieee80211_is_mgmt(hdr->frame_control) ||
+         ieee80211_is_nullfunc(hdr->frame_control) ||
+         ieee80211_is_qos_nullfunc(hdr->frame_control))) {
+        ac = 4;
+        hw_txqid = 4;
+    } else if((sc->bq4_dtim) &&
+              info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
+        hw_txqid = 4;
+        ac = 4;
+    } else {
+        ac = skb_get_queue_mapping(skb);
+        hw_txqid = sc->tx.hw_txqid[ac];
+    }
+    if (ampdu_retry_frame) {
+        int i;
+        if (sc->sh->cfg.auto_rate_enable) {
+            for (i = 0 ; i < SSV6006RC_MAX_RATE_SERIES ; i++) {
+                if (info->control.rates[i].idx > 0)
+                    info->control.rates[i].idx --;
+                else
+                    break;
+            }
+        }
+        hw_txqid = 4;
+        ac = 4;
+    }
+    memset(&dr, 0, sizeof(struct ssv6006_rc_idx) * SSV6006RC_MAX_RATE_SERIES);
+    memset(&cr, 0, sizeof(struct ssv6006_rc_idx) * SSV6006RC_MAX_RATE_SERIES);
+    tx_drate = &info->control.rates[0];
+    tx_desc->is_rate_stat_sample_pkt = (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ? 1 : 0;
+    ssv6006_set_data_rcword(sc, ssv_sta_priv, tx_desc, info,
+                            &dr.rate_idx[0], ieee80211_is_mgmt(hdr->frame_control), ieee80211_is_nullfunc(hdr->frame_control), info->band, hdr, no_update_rpt);
+    if (tx_desc->try_cnt1 == 0)
+        tx_desc->is_last_rate0 = 1;
+    else if (tx_desc->try_cnt2 == 0)
+        tx_desc->is_last_rate1 = 1;
+    else if (tx_desc->try_cnt3 == 0)
+        tx_desc->is_last_rate2 = 1;
+    else
+        tx_desc->is_last_rate3 = 1;
+    tx_desc->len = skb->len;
+    tx_desc->c_type = M2_TXREQ;
+    tx_desc->f80211 = 1;
+    tx_desc->qos = (ieee80211_is_data_qos(hdr->frame_control))? 1: 0;
+    if (sc->sh->cfg.auto_rate_enable) {
+        if (tx_drate->flags & IEEE80211_TX_RC_MCS) {
+            tx_desc->ht = 1;
+        }
+    } else {
+        if (sc->sh->cfg.rc_phy_mode == SSV6006RC_N_MODE) {
+            tx_desc->ht = 1;
+        }
+    }
+    tx_desc->use_4addr = (ieee80211_has_a4(hdr->frame_control))? 1: 0;
+    tx_desc->more_data = (ieee80211_has_morefrags(hdr->frame_control))? 1: 0;
+    tx_desc->stype_b5b4 = (cpu_to_le16(hdr->frame_control)>>4)&0x3;
+    tx_desc->frag = (tx_desc->more_data||(hdr->seq_ctrl&0xf))? 1: 0;
+    tx_desc->unicast = (is_multicast_ether_addr(hdr->addr1)) ? 0: 1;
+    tx_desc->bssidx = vif_priv->vif_idx;
+    tx_desc->wsid = (!sta_info || (sta_info->hw_wsid < 0)) ? 0x0F : sta_info->hw_wsid;
+    tx_desc->txq_idx = hw_txqid;
+    tx_desc->hdr_offset = TXPB_OFFSET;
+    tx_desc->hdr_len = ssv6xxx_frame_hdrlen(hdr, tx_desc->ht);
+    if (info->flags & IEEE80211_TX_CTL_AMPDU)
+        tx_desc->hdr_len += AMPDU_DELIMITER_LEN;
+    tx_desc->rate_rpt_mode = ((tx_desc->unicast && !no_update_rpt &&ieee80211_is_data(hdr->frame_control))
+                              && (!ieee80211_is_nullfunc(hdr->frame_control))) ? 1 : 2;
+    if (tx_desc->unicast && ieee80211_is_data(hdr->frame_control)) {
+        if (sc->hw->wiphy->rts_threshold != (u32) -1) {
+            if ((skb->len - sc->sh->tx_desc_len) > sc->hw->wiphy->rts_threshold) {
+                tx_desc->do_rts_cts0 = IEEE80211_TX_RC_USE_RTS_CTS;
+                tx_desc->do_rts_cts1 = IEEE80211_TX_RC_USE_RTS_CTS;
+            }
+        }
+        if (ieee80211_is_data(hdr->frame_control) &&
+            ((info->control.rates[0].idx <= 4) && (info->control.rates[0].flags & IEEE80211_TX_RC_MCS))) {
+            tx_desc->do_rts_cts0 = IEEE80211_TX_RC_USE_RTS_CTS;
+            tx_desc->do_rts_cts1 = IEEE80211_TX_RC_USE_RTS_CTS;
+        }
+        tx_desc->do_rts_cts2 = IEEE80211_TX_RC_USE_RTS_CTS;
+        tx_desc->do_rts_cts3 = IEEE80211_TX_RC_USE_RTS_CTS;
+        if (sc->sc_flags & SC_OP_CTS_PROT) {
+            tx_desc->do_rts_cts0 = IEEE80211_TX_RC_USE_CTS_PROTECT;
+            tx_desc->do_rts_cts1 = IEEE80211_TX_RC_USE_CTS_PROTECT;
+            tx_desc->do_rts_cts2 = IEEE80211_TX_RC_USE_CTS_PROTECT;
+            tx_desc->do_rts_cts3 = IEEE80211_TX_RC_USE_CTS_PROTECT;
+        }
+    }
+    dr_to_cr.val[0] = ssv6006_drword_to_crword(tx_desc, 0, info->band);
+    dr_to_cr.val[1] = ssv6006_drword_to_crword(tx_desc, 1, info->band);
+    dr_to_cr.val[2] = ssv6006_drword_to_crword(tx_desc, 2, info->band);
+    dr_to_cr.val[3] = ssv6006_drword_to_crword(tx_desc, 3, info->band);
+    if (0) {
+        tx_desc->crate_idx0 = 0;
+        tx_desc->crate_idx1 = 0;
+        tx_desc->crate_idx2 = 0;
+        tx_desc->crate_idx3 = 0;
+    } else {
+        cr.val[0] = dr_to_cr.val[0];
+        cr.val[1] = dr_to_cr.val[1];
+        cr.val[2] = dr_to_cr.val[2];
+        cr.val[3] = dr_to_cr.val[3];
+    }
+    if ((tx_desc->unicast == 0) || (ieee80211_is_ctl(hdr->frame_control))) {
+        tx_desc->ack_policy0 = 1;
+    } else if (tx_desc->qos == 1) {
+        tx_desc->ack_policy0 = (*ieee80211_get_qos_ctl(hdr)&0x60)>>5;
+    }
+    tx_desc->security = 0;
+    tx_desc->fCmdIdx = 0;
+    tx_desc->fCmd = (hw_txqid+M_ENG_TX_EDCA0);
+    if ((info->flags & IEEE80211_TX_CTL_AMPDU) && (tx_desc->aggr == 2)) {
+        tx_desc->ack_policy0 = 0;
+    }
+    tx_desc->ack_policy1 = tx_desc->ack_policy0;
+    tx_desc->ack_policy2 = tx_desc->ack_policy0;
+    tx_desc->ack_policy3 = tx_desc->ack_policy0;
+    if ( ieee80211_has_protected(hdr->frame_control)
+         && ( ieee80211_is_data_qos(hdr->frame_control)
+              || ieee80211_is_data(hdr->frame_control))) {
+        if ( (tx_desc->unicast && ssv_sta_priv && ssv_sta_priv->has_hw_encrypt)
+             || (!tx_desc->unicast && vif_priv && vif_priv->has_hw_encrypt)) {
+            if (!tx_desc->unicast && !list_empty(&vif_priv->sta_list)) {
+                struct ssv_sta_priv_data *one_sta_priv;
+                int hw_wsid;
+                one_sta_priv = list_first_entry(&vif_priv->sta_list, struct ssv_sta_priv_data, list);
+                hw_wsid = one_sta_priv->sta_info->hw_wsid;
+                if (hw_wsid != (-1)) {
+                    tx_desc->wsid = hw_wsid;
+                }
+#if 0
+                printk(KERN_ERR "HW ENC %d %02X:%02X:%02X:%02X:%02X:%02X\n",
+                       tx_desc->wsid,
+                       hdr->addr1[0], hdr->addr1[1], hdr->addr1[2],
+                       hdr->addr1[3], hdr->addr1[4], hdr->addr1[5]);
+                _ssv6xxx_hexdump("M ", (const u8 *)skb->data, (skb->len > 128) ? 128 : skb->len);
+                tx_desc->fCmd = (tx_desc->fCmd << 4) | M_ENG_CPU;
+#endif
+            }
+            tx_desc->fCmd = (tx_desc->fCmd << 4) | M_ENG_ENCRYPT;
+            if (tx_desc->unicast) {
+                if (vif_priv->pair_cipher == SSV_CIPHER_TKIP) {
+                    tx_desc->fCmd = (tx_desc->fCmd << 4) | M_ENG_MIC;
+                }
+            } else {
+                if (vif_priv->group_cipher == SSV_CIPHER_TKIP) {
+                    tx_desc->fCmd = (tx_desc->fCmd << 4) | M_ENG_MIC;
+                }
+            }
+        }
+    }
+    tx_desc->fCmd = (tx_desc->fCmd << 4) | M_ENG_HWHCI;
+#if 0
+    if ( ieee80211_is_data_qos(hdr->frame_control)
+         || ieee80211_is_data(hdr->frame_control))
+#endif
+#if 0
+        if (ieee80211_is_probe_resp(hdr->frame_control)) {
+            {
+                printk(KERN_ERR "Probe Resp %d %02X:%02X:%02X:%02X:%02X:%02X\n",
+                       tx_desc->wsid,
+                       hdr->addr1[0], hdr->addr1[1], hdr->addr1[2],
+                       hdr->addr1[3], hdr->addr1[4], hdr->addr1[5]);
+                _ssv6xxx_hexdump("M ", (const u8 *)skb->data, (skb->len > 128) ? 128 : skb->len);
+            }
+        }
+#endif
+    ssv6006_set_frame_duration(sc,info, &dr.rate_idx[0], &dr_to_cr.rate_idx[0], (skb->len+FCS_LEN), tx_desc, &nav[0]);
+    if (tx_desc->ack_policy0 != 0x01)
+        hdr->duration_id = nav[0];
+    if (tx_desc->ack_policy1 != 0x01)
+        tx_desc->rateidx1_data_duration = nav[1];
+    if (tx_desc->ack_policy2 != 0x01)
+        tx_desc->rateidx2_data_duration = nav[2];
+    if (tx_desc->ack_policy3 != 0x01)
+        tx_desc->rateidx3_data_duration = nav[3];
+    if (sta) {
+        up_read(&sc->sta_info_sem);
+    }
+}
+static void ssv6006_dump_ssv6006_txdesc(struct sk_buff *skb)
+{
+    struct ssv6006_tx_desc *tx_desc;
+    int s;
+    u8 *dat;
+    tx_desc = (struct ssv6006_tx_desc *)skb->data;
+    printk("\n>> TX desc:\n");
+    for(s = 0, dat= (u8 *)skb->data; s < sizeof(struct ssv6006_tx_desc) /4; s++) {
+        printk("%02x%02x%02x%02x ", dat[4*s+3], dat[4*s+2], dat[4*s+1], dat[4*s]);
+        if (((s+1)& 0x03) == 0)
+            printk("\n");
+    }
+}
+static void ssv6006_dump_ssv6006_txframe(struct sk_buff *skb)
+{
+    struct ssv6006_tx_desc *tx_desc;
+    int s;
+    u8 *dat;
+    tx_desc = (struct ssv6006_tx_desc *)skb->data;
+    printk(">> Tx Frame:\n");
+    for(s = 0, dat = skb->data; s < (tx_desc->len - TXPB_OFFSET); s++) {
+        printk("%02x ", dat[TXPB_OFFSET+s]);
+        if (((s+1)& 0x0F) == 0)
+            printk("\n");
+    }
+}
+static void ssv6006_dump_tx_desc(struct sk_buff *skb)
+{
+    struct ssv6006_tx_desc *tx_desc;
+    tx_desc = (struct ssv6006_tx_desc *)skb->data;
+    ssv6006_dump_ssv6006_txdesc(skb);
+    printk("\nlength: %d, c_type=%d, f80211=%d, qos=%d, ht=%d, use_4addr=%d, sec=%d\n",
+           tx_desc->len, tx_desc->c_type, tx_desc->f80211, tx_desc->qos, tx_desc->ht,
+           tx_desc->use_4addr, tx_desc->security);
+    printk("more_data=%d, sub_type=%x, extra_info=%d, aggr = %d\n", tx_desc->more_data,
+           tx_desc->stype_b5b4, tx_desc->extra_info, tx_desc->aggr);
+    printk("fcmd=0x%08x, hdr_offset=%d, frag=%d, unicast=%d, hdr_len=%d\n",
+           tx_desc->fCmd, tx_desc->hdr_offset, tx_desc->frag, tx_desc->unicast,
+           tx_desc->hdr_len);
+    printk("ack_policy0=%d, do_rts_cts0=%d, ack_policy1=%d, do_rts_cts1=%d, reason=%d\n",
+           tx_desc->ack_policy0, tx_desc->do_rts_cts0,tx_desc->ack_policy1, tx_desc->do_rts_cts1,
+           tx_desc->reason);
+    printk("ack_policy2=%d, do_rts_cts2=%d,ack_policy3=%d, do_rts_cts3=%d\n",
+           tx_desc->ack_policy2, tx_desc->do_rts_cts2,tx_desc->ack_policy3, tx_desc->do_rts_cts3);
+    printk("fcmdidx=%d, wsid=%d, txq_idx=%d\n",
+           tx_desc->fCmdIdx, tx_desc->wsid, tx_desc->txq_idx);
+    printk("0:RTS/CTS Nav=%d, crate_idx=%d, drate_idx=%d, dl_len=%d, retry=%d, last_rate %d \n",
+           tx_desc->rts_cts_nav0, tx_desc->crate_idx0, tx_desc->drate_idx0,
+           tx_desc->dl_length0, tx_desc->try_cnt0, tx_desc->is_last_rate0);
+    printk("1:RTS/CTS Nav=%d, crate_idx=%d, drate_idx=%d, dl_len=%d, retry=%d, last_rate %d  \n",
+           tx_desc->rts_cts_nav1, tx_desc->crate_idx1, tx_desc->drate_idx1,
+           tx_desc->dl_length1, tx_desc->try_cnt1, tx_desc->is_last_rate1);
+    printk("2:RTS/CTS Nav=%d, crate_idx=%d, drate_idx=%d, dl_len=%d, retry=%d, last_rate %d  \n",
+           tx_desc->rts_cts_nav2, tx_desc->crate_idx2, tx_desc->drate_idx2,
+           tx_desc->dl_length2, tx_desc->try_cnt2, tx_desc->is_last_rate2);
+    printk("3:RTS/CTS Nav=%d, crate_idx=%d, drate_idx=%d, dl_len=%d, retry=%d , last_rate %d \n",
+           tx_desc->rts_cts_nav3, tx_desc->crate_idx3, tx_desc->drate_idx3,
+           tx_desc->dl_length3, tx_desc->try_cnt3, tx_desc->is_last_rate3);
+}
+static void ssv6006_add_txinfo (struct ssv_softc *sc, struct sk_buff *skb)
+{
+    struct ssv6006_tx_desc *tx_desc;
+    skb_push(skb, TXPB_OFFSET);
+    tx_desc = (struct ssv6006_tx_desc *)skb->data;
+    memset((void *)tx_desc, 0, TXPB_OFFSET);
+    ssv6006_update_txinfo(sc, skb);
+    if (sc->log_ctrl & LOG_TX_FRAME) {
+        ssv6006_dump_ssv6006_txframe(skb);
+    }
+    if (sc->log_ctrl & LOG_TX_DESC) {
+        printk(" dump tx desciptor after tx add info:\n");
+        ssv6006_dump_tx_desc(skb);
+    }
+}
+static void ssv6006_update_ampdu_txinfo(struct ssv_softc *sc, struct sk_buff *ampdu_skb)
+{
+    struct ssv6006_tx_desc *tx_desc = (struct ssv6006_tx_desc *)ampdu_skb->data;
+    tx_desc->tx_pkt_run_no = sc->tx_pkt_run_no;
+}
+static void ssv6006_add_ampdu_txinfo(struct ssv_softc *sc, struct sk_buff *ampdu_skb)
+{
+    struct ssv6006_tx_desc *tx_desc;
+    skb_push(ampdu_skb, TXPB_OFFSET);
+    tx_desc = (struct ssv6006_tx_desc *)ampdu_skb->data;
+    memset((void *)tx_desc, 0, TXPB_OFFSET);
+    tx_desc->aggr = 2;
+    ssv6006_update_txinfo(sc, ampdu_skb);
+    if (sc->log_ctrl & LOG_TX_FRAME) {
+        ssv6006_dump_ssv6006_txframe(ampdu_skb);
+    }
+    if (sc->log_ctrl & LOG_TX_DESC) {
+        printk(" dump tx desciptor after tx ampdu add info:\n");
+        ssv6006_dump_tx_desc(ampdu_skb);
+    }
+}
+void ssv6006_fill_lpbk_tx_desc(struct sk_buff *skb, int security, unsigned char rate)
+{
+    struct ssv6006_tx_desc *tx_desc;
+    u32 frame_time = 0, l_length = 0;
+    u8 phy, mcsidx, ht40, sgi, gf;
+    phy = ((rate & SSV6006RC_PHY_MODE_MSK) >> SSV6006RC_PHY_MODE_SFT);
+    ht40 = ((rate & SSV6006RC_20_40_MSK) >> SSV6006RC_20_40_SFT);
+    sgi = ((rate & SSV6006RC_LONG_SHORT_MSK) >> SSV6006RC_LONG_SHORT_SFT);
+    gf = ((rate & SSV6006RC_MF_MSK) >> SSV6006RC_MF_SFT);
+    mcsidx = ((rate & SSV6006RC_RATE_MSK) >> SSV6006RC_RATE_SFT);
+    if (phy == SSV6006RC_N_MODE) {
+        frame_time = ssv6xxx_ht_txtime(mcsidx, skb->len - sizeof(struct ssv6006_tx_desc), ht40, sgi, gf);
+        l_length = frame_time - HT_SIFS_TIME;
+        l_length = ((l_length - (HT_SIGNAL_EXT + 20)) + 3 ) >> 2;
+        l_length += ((l_length << 1) - 3);
+    }
+    tx_desc = (struct ssv6006_tx_desc *)skb->data;
+    memset((void *)tx_desc, 0x0, sizeof(struct ssv6006_tx_desc));
+    tx_desc->len = skb->len;
+    tx_desc->c_type = M2_TXREQ;
+    tx_desc->f80211 = 1;
+    tx_desc->qos = 1;
+    tx_desc->ht = 1;
+    tx_desc->security = (security == SSV6006_CMD_LPBK_SEC_OPEN) ? 0 : 1;
+    tx_desc->fCmd = (M_ENG_TX_EDCA0 << 12)|(M_ENG_ENCRYPT << 8)|(M_ENG_MIC<<4)|M_ENG_HWHCI;
+    tx_desc->hdr_offset = 80;
+    tx_desc->unicast = 1;
+    tx_desc->hdr_len = sizeof(struct ieee80211_hdr_3addr);
+    tx_desc->tx_pkt_run_no = 88;
+    tx_desc->wsid = security;
+    tx_desc->dl_length0 = l_length;
+    tx_desc->drate_idx0 = rate;
+    tx_desc->try_cnt0 = 1;
+    tx_desc->is_last_rate0 = 1;
+    tx_desc->ack_policy0 = 1;
+    tx_desc->reason = ID_TRAP_SW_TXTPUT;
+    tx_desc->rate_rpt_mode = 2;
+}
+static int ssv6006_update_null_func_txinfo(struct ssv_softc *sc, struct ieee80211_sta *sta, struct sk_buff *skb)
+{
+    struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data + TXPB_OFFSET);
+    struct ssv_sta_priv_data *ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+    struct ssv_sta_info *sta_info = (struct ssv_sta_info *)ssv_sta_priv->sta_info;
+    struct ssv6006_tx_desc *tx_desc = (struct ssv6006_tx_desc *)skb->data;
+    int hw_txqid = 4;
+    memset(tx_desc, 0x0, sizeof(struct ssv6006_tx_desc));
+    tx_desc->len = skb->len;
+    tx_desc->c_type = M2_TXREQ;
+    tx_desc->f80211 = 1;
+    tx_desc->unicast = 1;
+    tx_desc->tx_pkt_run_no = SSV6XXX_PKT_RUN_TYPE_NULLFUN;
+    tx_desc->wsid = sta_info->hw_wsid;
+    tx_desc->txq_idx = hw_txqid;
+    tx_desc->hdr_offset = TXPB_OFFSET;
+    tx_desc->hdr_len = ssv6xxx_frame_hdrlen(hdr, false);
+    tx_desc->drate_idx0 = ((SSV6006RC_G_MODE << SSV6006RC_PHY_MODE_SFT) | (SSV6006RC_G_6M << SSV6006RC_RATE_SFT));
+    tx_desc->crate_idx0 = ((SSV6006RC_G_MODE << SSV6006RC_PHY_MODE_SFT) | (SSV6006RC_G_6M << SSV6006RC_RATE_SFT));
+    tx_desc->try_cnt0 = 0xf;
+    tx_desc->is_last_rate0 = 1;
+    tx_desc->rate_rpt_mode = 1;
+    tx_desc->fCmdIdx = 0;
+    tx_desc->fCmd = (hw_txqid+M_ENG_TX_EDCA0);
+    tx_desc->fCmd = (tx_desc->fCmd << 4) | M_ENG_HWHCI;
+    hdr->duration_id = ssv6xxx_non_ht_txtime(WLAN_RC_PHY_OFDM, 6000, ACK_LEN, false);
+    return 0;
+}
+static void ssv6006_dump_rx_desc(struct sk_buff *skb)
+{
+    struct ssv6006_rx_desc *rx_desc;
+    struct ssv6006_rxphy_info *rxphy;
+    int s;
+    u8 *dat;
+    rx_desc = (struct ssv6006_rx_desc *)skb->data;
+    printk(">> RX Descriptor:\n");
+    for(s = 0, dat= (u8 *)skb->data; s < sizeof(struct ssv6006_rx_desc) /4; s++) {
+        printk("%02x%02x%02x%02x ", dat[4*s+3], dat[4*s+2], dat[4*s+1], dat[4*s]);
+        if (((s+1)& 0x03) == 0)
+            printk("\n");
+    }
+    printk(">> RX Phy Info:\n");
+    for(s =0, dat= (u8 *)skb->data; s < sizeof(struct ssv6006_rxphy_info) /4; s++) {
+        printk("%02x%02x%02x%02x ", dat[4*s+3+ sizeof(*rx_desc)], dat[4*s+2+ sizeof(*rx_desc)],
+               dat[4*s+1+ sizeof(*rx_desc)], dat[4*s+ sizeof(*rx_desc)]);
+        if (((s+1)& 0x03) == 0)
+            printk("\n");
+    }
+    printk("\nlen=%d, c_type=%d, f80211=%d, qos=%d, ht=%d, use_4addr=%d\n",
+           rx_desc->len, rx_desc->c_type, rx_desc->f80211, rx_desc->qos, rx_desc->ht, rx_desc->use_4addr);
+    printk("psm=%d, stype_b5b4=%d, reason=%d, rx_result=%d, channel = %d\n",
+           rx_desc->psm, rx_desc->stype_b5b4, rx_desc->reason, rx_desc->RxResult, rx_desc->channel);
+    rxphy = (struct ssv6006_rxphy_info *)(skb->data + sizeof(*rx_desc));
+    printk("phy_rate=0x%x, aggregate=%d, l_length=%d, l_rate=%d, rssi = %d\n",
+           rxphy->phy_rate, rxphy->aggregate, rxphy->l_length, rxphy->l_rate, rxphy->rssi);
+    printk("snr=%d, rx_freq_offset=%d, timestamp 0x%x\n", rxphy->snr, rxphy->rx_freq_offset, rxphy->rx_time_stamp);
+}
+static int ssv6006_get_tx_desc_size(struct ssv_hw *sh)
+{
+    return sizeof(struct ssv6006_tx_desc);
+}
+static int ssv6006_get_tx_desc_ctype(struct sk_buff *skb)
+{
+    struct ssv6006_tx_desc *tx_desc = (struct ssv6006_tx_desc *) skb->data;
+    return tx_desc->c_type ;
+}
+static int ssv6006_get_tx_desc_reason(struct sk_buff *skb)
+{
+    struct ssv6006_tx_desc *tx_desc = (struct ssv6006_tx_desc *) skb->data;
+    return tx_desc->reason ;
+}
+static int ssv6006_get_tx_desc_txq_idx(struct sk_buff *skb)
+{
+    struct ssv6006_tx_desc *tx_desc = (struct ssv6006_tx_desc *) skb->data;
+    return tx_desc->txq_idx ;
+}
+static void ssv6006_tx_rate_update( struct ssv_softc *sc, struct sk_buff *skb)
+{
+    struct ieee80211_hdr *hdr;
+    struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
+    struct ssv6006_tx_desc *tx_desc = (struct ssv6006_tx_desc *)skb->data;
+    u32 nav[SSV6006RC_MAX_RATE_SERIES] = {0, 0, 0, 0};
+    union {
+        struct ssv6006_rc_idx rate_idx[SSV6006RC_MAX_RATE_SERIES];
+        u8 val[SSV6006RC_MAX_RATE_SERIES];
+    } dr, cr;
+    u8 bandwidth = 0;
+    if (info->flags & IEEE80211_TX_CTL_AMPDU)
+        hdr = (struct ieee80211_hdr *)(skb->data + TXPB_OFFSET + AMPDU_DELIMITER_LEN);
+    else
+        hdr = (struct ieee80211_hdr *)(skb->data + TXPB_OFFSET);
+    bandwidth = ((tx_desc->drate_idx0 & SSV6006RC_20_40_MSK) >> SSV6006RC_20_40_SFT);
+    if ((sc->hw_chan_type == NL80211_CHAN_HT20)||
+        (sc->hw_chan_type == NL80211_CHAN_NO_HT)) {
+        if (bandwidth == SSV6006RC_HT40) {
+            tx_desc->drate_idx0 &= ~(SSV6006RC_HT40 << SSV6006RC_20_40_SFT);
+            tx_desc->drate_idx1 &= ~(SSV6006RC_HT40 << SSV6006RC_20_40_SFT);
+            tx_desc->drate_idx2 &= ~(SSV6006RC_HT40 << SSV6006RC_20_40_SFT);
+            tx_desc->crate_idx0 &= ~(SSV6006RC_HT40 << SSV6006RC_20_40_SFT);
+            tx_desc->crate_idx1 &= ~(SSV6006RC_HT40 << SSV6006RC_20_40_SFT);
+            tx_desc->crate_idx2 &= ~(SSV6006RC_HT40 << SSV6006RC_20_40_SFT);
+            dr.val[0] = tx_desc->drate_idx0;
+            dr.val[1] = tx_desc->drate_idx1;
+            dr.val[2] = tx_desc->drate_idx2;
+            dr.val[3] = tx_desc->drate_idx3;
+            cr.val[0] = tx_desc->crate_idx0;
+            cr.val[1] = tx_desc->crate_idx1;
+            cr.val[2] = tx_desc->crate_idx2;
+            cr.val[3] = tx_desc->crate_idx3;
+            ssv6006_set_frame_duration(sc,info, &dr.rate_idx[0], &cr.rate_idx[0], (skb->len+FCS_LEN), tx_desc, &nav[0]);
+            if (tx_desc->ack_policy0 != 0x01)
+                hdr->duration_id = nav[0];
+            if (tx_desc->ack_policy1 != 0x01)
+                tx_desc->rateidx1_data_duration = nav[1];
+            if (tx_desc->ack_policy2 != 0x01)
+                tx_desc->rateidx2_data_duration = nav[2];
+            if (tx_desc->ack_policy3 != 0x01)
+                tx_desc->rateidx3_data_duration = nav[3];
+        }
+    }
+}
+static void ssv6006_txtput_set_desc(struct ssv_hw *sh, struct sk_buff *skb )
+{
+    struct ssv6006_tx_desc *tx_desc;
+    tx_desc = (struct ssv6006_tx_desc *)skb->data;
+    memset((void *)tx_desc, 0xff, sizeof(struct ssv6006_tx_desc));
+    tx_desc->len = skb->len;
+    tx_desc->c_type = M2_TXREQ;
+    tx_desc->fCmd = (M_ENG_CPU << 4) | M_ENG_HWHCI;
+    tx_desc->reason = ID_TRAP_SW_TXTPUT;
+}
+static void ssv6006_fill_beacon_tx_desc(struct ssv_softc *sc, struct sk_buff* beacon_skb)
+{
+    struct ssv6006_tx_desc *tx_desc;
+    skb_push(beacon_skb, TXPB_OFFSET);
+    tx_desc = (struct ssv6006_tx_desc *)beacon_skb->data;
+    memset(tx_desc,0, TXPB_OFFSET);
+    tx_desc->len = beacon_skb->len-TXPB_OFFSET;
+    tx_desc->c_type = M2_TXREQ;
+    tx_desc->f80211 = 1;
+    tx_desc->ack_policy0 = 1;
+    tx_desc->ack_policy1 = 1;
+    tx_desc->ack_policy2 = 1;
+    tx_desc->ack_policy3 = 1;
+    tx_desc->hdr_offset = TXPB_OFFSET;
+    tx_desc->hdr_len = 24;
+    tx_desc->wsid = 0xf;
+    if ((sc->cur_channel->band == INDEX_80211_BAND_5GHZ) || (sc->ap_vif->p2p == true)) {
+        tx_desc->drate_idx0 = ((SSV6006RC_G_MODE << SSV6006RC_PHY_MODE_SFT)
+                               | (SSV6006RC_G_6M << SSV6006RC_RATE_SFT));
+        tx_desc->crate_idx0 = ((SSV6006RC_G_MODE << SSV6006RC_PHY_MODE_SFT)
+                               | (SSV6006RC_G_6M << SSV6006RC_RATE_SFT));
+    } else {
+        tx_desc->drate_idx0 = ((SSV6006RC_B_MODE << SSV6006RC_PHY_MODE_SFT)
+                               | (SSV6006RC_B_1M << SSV6006RC_RATE_SFT));
+        tx_desc->crate_idx0 = ((SSV6006RC_B_MODE << SSV6006RC_PHY_MODE_SFT)
+                               | (SSV6006RC_B_1M << SSV6006RC_RATE_SFT));
+    }
+    tx_desc->try_cnt0 = 1;
+    tx_desc->is_last_rate0 = 1;
+}
+static int ssv6006_get_sec_decode_err(struct sk_buff *skb, bool *mic_err, bool *decode_err)
+{
+    struct ssv6006_rx_desc *rx_desc = (struct ssv6006_rx_desc *) skb->data;
+    if (rx_desc->sec_decode_err == 1)
+        *decode_err = true;
+    if (rx_desc->tkip_mmic_err == 1)
+        *mic_err = true;
+    return (((rx_desc->sec_decode_err == 1) || (rx_desc->tkip_mmic_err == 1)) ? 1 : 0);
+}
+static int ssv6006_get_rx_desc_size(struct ssv_hw *sh)
+{
+    return sizeof(struct ssv6006_rx_desc) + sizeof (struct ssv6006_rxphy_info);
+}
+static int ssv6006_get_rx_desc_length(struct ssv_hw *sh)
+{
+    return sizeof(struct ssv6006_rx_desc);
+}
+static u32 ssv6006_get_rx_desc_wsid(struct sk_buff *skb)
+{
+    struct ssv6006_rx_desc *rx_desc = (struct ssv6006_rx_desc *)skb->data;
+    return rx_desc->wsid;
+}
+static u32 ssv6006_get_rx_desc_rate_idx(struct sk_buff *skb)
+{
+    struct ssv6006_rxphy_info *rxphy;
+    struct ssv6006_rx_desc *rxdesc = (struct ssv6006_rx_desc *)skb->data;
+    rxphy = (struct ssv6006_rxphy_info *)(skb->data + sizeof(*rxdesc));
+    return rxphy->phy_rate;
+}
+static u32 ssv6006_get_rx_desc_mng_used(struct sk_buff *skb)
+{
+    struct ssv6006_rx_desc *rx_desc = (struct ssv6006_rx_desc *)skb->data;
+    return rx_desc->mng_used;
+}
+static bool ssv6006_is_rx_aggr(struct sk_buff *skb)
+{
+    struct ssv6006_rxphy_info *rxphy;
+    rxphy = (struct ssv6006_rxphy_info *)(skb->data + sizeof(struct ssv6006_rx_desc));
+    return rxphy->aggregate;
+}
+static void ssv6006_get_rx_desc_info(struct sk_buff *skb, u32 *packet_len, u32 *c_type,
+                                     u32 *tx_pkt_run_no)
+{
+    struct ssv6006_rx_desc *rxdesc = (struct ssv6006_rx_desc *)skb->data;
+    *packet_len = rxdesc->len;
+    *c_type = rxdesc->c_type;
+    *tx_pkt_run_no = rxdesc->rx_pkt_run_no;
+}
+static u32 ssv6006_get_rx_desc_ctype(struct sk_buff *skb)
+{
+    struct ssv6006_rx_desc *rxdesc = (struct ssv6006_rx_desc *)skb->data;
+    return rxdesc->c_type;
+}
+static int ssv6006_get_rx_desc_hdr_offset(struct sk_buff *skb)
+{
+    struct ssv6006_rx_desc *rxdesc = (struct ssv6006_rx_desc *)skb->data;
+    return rxdesc->hdr_offset;
+}
+static int ssv6006_chk_lpbk_rx_rate_desc(struct ssv_hw *sh, struct sk_buff *skb)
+{
+    struct ssv6006_rxphy_info *rxphy = (struct ssv6006_rxphy_info *)(skb->data + sizeof(struct ssv6006_rx_desc));
+    u8 rate = 0;
+    if (sh->cfg.lpbk_mode && (sh->cfg.lpbk_type == SSV6006_CMD_LPBK_TYPE_PHY)) {
+        rate = ((sh->cfg.rc_rate_idx_set & SSV6006RC_RATE_MSK) << SSV6006RC_RATE_SFT) |
+               (sh->cfg.rc_long_short << SSV6006RC_LONG_SHORT_SFT) |
+               (sh->cfg.rc_ht40 << SSV6006RC_20_40_SFT) |
+               (sh->cfg.rc_phy_mode << SSV6006RC_PHY_MODE_SFT);
+        return ((rate != rxphy->phy_rate) ? -1 : 0);
+    }
+    return 0;
+}
+static bool ssv6006_nullfun_frame_filter(struct sk_buff *skb)
+{
+    struct ssv6006_tx_desc *txdesc = (struct ssv6006_tx_desc *)skb->data;
+    if (txdesc->tx_pkt_run_no == SSV6XXX_PKT_RUN_TYPE_NULLFUN)
+        return true;
+    return false;
+}
+static void ssv6006_phy_enable(struct ssv_hw *sh, bool val)
+{
+    SMAC_REG_SET_BITS(sh, ADR_WIFI_PHY_COMMON_ENABLE_REG, (val << RG_PHY_MD_EN_SFT), RG_PHY_MD_EN_MSK);
+}
+static void ssv6006_set_phy_mode(struct ssv_hw *sh, bool val)
+{
+    if (val) {
+        SMAC_REG_WRITE(sh, ADR_WIFI_PHY_COMMON_ENABLE_REG,(RG_PHYRX_MD_EN_MSK | RG_PHYTX_MD_EN_MSK |
+                       RG_PHY11GN_MD_EN_MSK | RG_PHY11B_MD_EN_MSK | RG_PHYRXFIFO_MD_EN_MSK |
+                       RG_PHYTXFIFO_MD_EN_MSK | RG_PHY11BGN_MD_EN_MSK));
+    } else {
+        SMAC_REG_WRITE(sh, ADR_WIFI_PHY_COMMON_ENABLE_REG, 0x00000000);
+    }
+}
+static void ssv6006_edca_enable(struct ssv_hw *sh, bool val)
+{
+    if (val) {
+        SET_RG_EDCCA_AVG_T(SSV6006_EDCCA_AVG_T_25US);
+        SET_RG_EDCCA_STAT_EN(0);
+        udelay(100);
+        SET_RG_EDCCA_STAT_EN(1);
+    } else {
+        SET_RG_EDCCA_STAT_EN(0);
+    }
+}
+static u32 ssv6006_edca_ewma(int old, int new)
+{
+    return ((new + ((old << 3) - old)) >> 3);
+}
+static void ssv6006_edca_stat(struct ssv_hw *sh)
+{
+    struct ssv_softc *sc = sh->sc;
+    u32 regval;
+    int stat = 0, period = 0, percentage = 0;
+    SMAC_REG_READ(sh, ADR_WIFI_PHY_COMMON_EDCCA_1, &regval);
+    period = ((regval & RO_EDCCA_PRIMARY_PRD_MSK) >> RO_EDCCA_PRIMARY_PRD_SFT);
+    stat = ((regval & RO_PRIMARY_EDCCA_MSK) >> RO_PRIMARY_EDCCA_SFT);
+    if (period)
+        percentage = SSV_EDCA_FRAC(stat, period);
+    sc->primary_edca_mib = ssv6006_edca_ewma(sc->primary_edca_mib, percentage);
+    percentage = 0;
+    SMAC_REG_READ(sh, ADR_WIFI_PHY_COMMON_EDCCA_2, &regval);
+    period = ((regval & RO_EDCCA_SECONDARY_PRD_MSK) >> RO_EDCCA_SECONDARY_PRD_SFT);
+    stat = ((regval & RO_SECONDARY_EDCCA_MSK) >> RO_SECONDARY_EDCCA_SFT);
+    if (period)
+        percentage = SSV_EDCA_FRAC(stat, period);
+    sc->secondary_edca_mib = ssv6006_edca_ewma(sc->secondary_edca_mib, percentage);
+    SET_RG_EDCCA_STAT_EN(0);
+    MDELAY(1);
+    SET_RG_EDCCA_STAT_EN(1);
+}
+static void ssv6006_reset_mib_phy(struct ssv_hw *sh)
+{
+    SET_RG_MRX_EN_CNT_RST_N(0);
+    SET_RG_PACKET_STAT_EN_11B_RX(0);
+    SET_RG_PACKET_STAT_EN_11GN_RX(0);
+    msleep(1);
+    SET_RG_MRX_EN_CNT_RST_N(1);
+    SET_RG_PACKET_STAT_EN_11B_RX(1);
+    SET_RG_PACKET_STAT_EN_11GN_RX(1);
+}
+static void ssv6006_dump_mib_rx_phy(struct ssv_hw *sh)
+{
+    struct ssv_cmd_data *cmd_data = &sh->sc->cmd_data;
+    snprintf_res(cmd_data, "PHY total Rx\t:[%08x]\n", GET_RO_MRX_EN_CNT );
+    snprintf_res(cmd_data, "PHY B mode:\n");
+    snprintf_res(cmd_data, "%-10s\t%-10s\t%-10s\t%-10s\t%-10s\n", "SFD_CNT","CRC_CNT","PKT_ERR","CCA","PKT_CNT");
+    snprintf_res(cmd_data, "[%08x]\t", GET_RO_11B_SFD_CNT);
+    snprintf_res(cmd_data, "[%08x]\t", GET_RO_11B_CRC_CNT);
+    snprintf_res(cmd_data, "[%08x]\t", GET_RO_11B_PACKET_ERR_CNT);
+    snprintf_res(cmd_data, "[%08x]\t", GET_RO_11B_CCA_CNT);
+    snprintf_res(cmd_data, "[%08x]\t\n", GET_RO_11B_PACKET_CNT);
+    snprintf_res(cmd_data, "PHY G/N mode:\n");
+    snprintf_res(cmd_data, "%-10s\t%-10s\t%-10s\t%-10s\t%-10s\n","AMPDU ERR", "AMPDU PKT","PKT_ERR","CCA","PKT_CNT");
+    snprintf_res(cmd_data, "[%08x]\t", GET_RO_AMPDU_PACKET_ERR_CNT);
+    snprintf_res(cmd_data, "[%08x]\t", GET_RO_AMPDU_PACKET_CNT);
+    snprintf_res(cmd_data, "[%08x]\t", GET_RO_11GN_PACKET_ERR_CNT);
+    snprintf_res(cmd_data, "[%08x]\t", GET_RO_11GN_CCA_CNT);
+    snprintf_res(cmd_data, "[%08x]\t\n\n", GET_RO_11GN_PACKET_CNT);
+}
+void ssv6006_rc_mac80211_rate_idx(struct ssv_softc *sc,
+                                  int hw_rate_idx, struct ieee80211_rx_status *rxs)
+{
+    if (((hw_rate_idx & SSV6006RC_PHY_MODE_MSK) >>
+         SSV6006RC_PHY_MODE_SFT)== SSV6006RC_N_MODE) {
+        rxs->flag |= RX_FLAG_HT;
+        if (((hw_rate_idx & SSV6006RC_20_40_MSK) >>
+             SSV6006RC_20_40_SFT) == SSV6006RC_HT40) {
+            rxs->flag |= RX_FLAG_40MHZ;
+        }
+        if (((hw_rate_idx & SSV6006RC_LONG_SHORT_MSK) >>
+             SSV6006RC_LONG_SHORT_SFT) == SSV6006RC_SHORT) {
+            rxs->flag |= RX_FLAG_SHORT_GI;
+        }
+    } else {
+        if (((hw_rate_idx & SSV6006RC_LONG_SHORT_MSK) >>
+             SSV6006RC_LONG_SHORT_SFT) == SSV6006RC_SHORT) {
+            rxs->flag |= RX_FLAG_SHORTPRE;
+        }
+    }
+    rxs->rate_idx = (hw_rate_idx & SSV6006RC_RATE_MSK) >>
+                    SSV6006RC_RATE_SFT;
+    if ((((hw_rate_idx & SSV6006RC_PHY_MODE_MSK) >> SSV6006RC_PHY_MODE_SFT)== SSV6006RC_G_MODE) &&
+        (rxs->band == INDEX_80211_BAND_2GHZ)) {
+        rxs->rate_idx += DOT11_G_RATE_IDX_OFFSET;
+    }
+}
+void _update_green_tx(struct ssv_softc *sc, u16 rssi)
+{
+    int atteneuation_pwr = 0;
+    u8 gt_pwr_start;
+    if ((!(sc->gt_enabled)) || (sc->green_pwr == 0xff))
+        return;
+    gt_pwr_start = sc->sh->cfg.greentx & GT_PWR_START_MASK;
+    if ((rssi < gt_pwr_start) && (rssi >= 0)) {
+        atteneuation_pwr = (gt_pwr_start - rssi )*2 + sc->default_pwr;
+        sc->dpd.pwr_mode = GREEN_PWR;
+        if (sc->sh->cfg.greentx & GT_DBG) {
+            printk("[greentx]:current_power %d\n", sc->green_pwr);
+        }
+        if (atteneuation_pwr > (sc->green_pwr + (sc->sh->cfg.gt_stepsize*2))) {
+            sc->green_pwr += (sc->sh->cfg.gt_stepsize*2);
+            if (sc->green_pwr > ((sc->sh->cfg.gt_max_attenuation*2) + sc->default_pwr))
+                sc->green_pwr = (sc->sh->cfg.gt_max_attenuation*2 + sc->default_pwr);
+        } else if (atteneuation_pwr <(int) (sc->green_pwr - (sc->sh->cfg.gt_stepsize*2))) {
+            sc->green_pwr -= (sc->sh->cfg.gt_stepsize*2);
+            if (sc->green_pwr < sc->default_pwr)
+                sc->green_pwr = sc->default_pwr;
+        }
+        if (sc->sh->cfg.greentx & GT_DBG) {
+            printk("[greentx]:rssi: %d expected green tx pwr gain %d, set tx pwr gain %d\n",
+                   rssi, atteneuation_pwr, sc->green_pwr);
+        }
+    } else {
+        if ( sc->dpd.pwr_mode == GREEN_PWR) {
+            sc->dpd.pwr_mode = NORMAL_PWR;
+            sc->green_pwr = 0xff;
+            if (sc->sh->cfg.greentx & GT_DBG) {
+                printk("[greentx]:restore normal pwr\n");
+            }
+        }
+    }
+}
+#ifdef CONFIG_SSV_CCI_IMPROVEMENT
+static struct ssv6xxx_cca_control adjust_cci[] = {
+    {0, 43, 0x01162000, 0x20000180},
+    {40, 48, 0x01161000, 0x10000180},
+    {45, 53, 0x01160800, 0x08000180},
+    {50, 63, 0x01160400, 0x04000180},
+    {60, 68, 0x01160200, 0x02000180},
+    {65, 73, 0x01160100, 0x01000180},
+    {70, 128, 0x00000000, 0x00000000},
+};
+void ssv6006_update_scan_cci_setting(struct ssv_softc *sc)
+{
+    if (sc->cci_set) {
+        SMAC_REG_WRITE(sc->sh, ADR_WIFI_11B_RX_REG_040, 0);
+        SMAC_REG_WRITE(sc->sh, ADR_WIFI_11GN_RX_REG_040, 0);
+        sc->cci_set = false;
+#ifdef DEBUG_MITIGATE_CCI
+        if (sc->sh->cfg.cci & CCI_DBG) {
+            printk("clean cci settings\n");
+        }
+#endif
+    }
+    if (sc->cci_current_level == 0) {
+        sc->cci_current_level = MAX_CCI_LEVEL;
+        sc->cci_current_gate = (sizeof(adjust_cci)/sizeof(adjust_cci[0])) - 1;
+    }
+}
+void ssv6006_recover_scan_cci_setting(struct ssv_softc *sc)
+{
+    if (((sc->cci_set == false) || (sc->cci_modified)) && (sc->cci_current_level != MAX_CCI_LEVEL)) {
+        SMAC_REG_WRITE(sc->sh, ADR_WIFI_11B_RX_REG_040,
+                       adjust_cci[sc->cci_current_gate].adjust_cck_cca_control);
+        SMAC_REG_WRITE(sc->sh, ADR_WIFI_11GN_RX_REG_040,
+                       adjust_cci[sc->cci_current_gate].adjust_ofdm_cca_control);
+        sc->cci_set = true;
+        sc->cci_modified = false;
+#ifdef DEBUG_MITIGATE_CCI
+        if (sc->sh->cfg.cci & CCI_DBG) {
+            printk("update cci settings to %x %x\n",
+                   adjust_cci[sc->cci_current_gate].adjust_cck_cca_control,
+                   adjust_cci[sc->cci_current_gate].adjust_ofdm_cca_control);
+        }
+#endif
+    }
+}
+void ssv6006_update_data_cci_setting
+(struct ssv_softc *sc, struct ssv_sta_priv_data *sta_priv, u32 input_level)
+{
+    s32 i;
+    struct ssv_vif_priv_data *vif_priv = NULL;
+    struct ieee80211_vif *vif = NULL;
+    if (((sc->sh->cfg.cci & CCI_CTL) == 0) || (sc->bScanning == true)) {
+        return;
+    }
+    if (time_after(jiffies, sc->cci_last_jiffies + msecs_to_jiffies(500)) ||
+        (sc->cci_current_level == MAX_CCI_LEVEL)) {
+        if ((input_level > MAX_CCI_LEVEL) && (sc->sh->cfg.cci & CCI_DBG)) {
+            printk("mitigate_cci input error[%d]!!\n",input_level);
+            return;
+        }
+#ifndef IRQ_PROC_RX_DATA
+        down_read(&sc->sta_info_sem);
+#else
+        while(!down_read_trylock(&sc->sta_info_sem));
+#endif
+        if ((sta_priv->sta_info->s_flags & STA_FLAG_VALID) == 0) {
+            up_read(&sc->sta_info_sem);
+            printk("%s(): sta_info is gone.\n", __func__);
+            return;
+        }
+        sc->cci_last_jiffies = jiffies;
+        vif = sta_priv->sta_info->vif;
+        vif_priv = (struct ssv_vif_priv_data *)vif->drv_priv;
+        if ((vif_priv->vif_idx)&& (sc->sh->cfg.cci & CCI_DBG)) {
+            up_read(&sc->sta_info_sem);
+            printk("Interface skip CCI[%d]!!\n",vif_priv->vif_idx);
+            return;
+        }
+        if ((vif->p2p == true) && (sc->sh->cfg.cci & CCI_DBG)) {
+            up_read(&sc->sta_info_sem);
+            printk("Interface skip CCI by P2P!!\n");
+            return;
+        }
+        up_read(&sc->sta_info_sem);
+        if (sc->cci_current_level == 0)
+            sc->cci_current_level = MAX_CCI_LEVEL;
+        if (sc->cci_current_level == MAX_CCI_LEVEL) {
+            sc->cci_current_gate = (sizeof(adjust_cci)/sizeof(adjust_cci[0])) - 1;
+            sc->cci_set = true;
+        }
+        sc->cci_start = true;
+#ifdef DEBUG_MITIGATE_CCI
+        if (sc->sh->cfg.cci & CCI_DBG) {
+            printk("jiffies=%lu, input_level=%d\n", jiffies, input_level);
+        }
+#endif
+        if(( input_level >= adjust_cci[sc->cci_current_gate].down_level) && (input_level <= adjust_cci[sc->cci_current_gate].upper_level)) {
+            sc->cci_current_level = input_level;
+#ifdef DEBUG_MITIGATE_CCI
+            if (sc->sh->cfg.cci & CCI_DBG) {
+                printk("Keep the ADR_WIFI_11B_RX_REG_040[%x] ADR_WIFI_11GN_RX_REG_040[%x]!!\n",
+                       adjust_cci[sc->cci_current_gate].adjust_cck_cca_control,
+                       adjust_cci[sc->cci_current_gate].adjust_ofdm_cca_control);
+            }
+#endif
+        } else {
+            if(sc->cci_current_level < input_level) {
+                for (i = 0; i < sizeof(adjust_cci)/sizeof(adjust_cci[0]); i++) {
+                    if (input_level <= adjust_cci[i].upper_level) {
+#ifdef DEBUG_MITIGATE_CCI
+                        if (sc->sh->cfg.cci & CCI_DBG) {
+                            printk("gate=%d, input_level=%d, adjust_cci[%d].upper_level=%d, cck value=%08x, ofdm value= %08x\n",
+                                   sc->cci_current_gate, input_level, i, adjust_cci[i].upper_level
+                                   , adjust_cci[i].adjust_cck_cca_control, adjust_cci[i].adjust_ofdm_cca_control);
+                        }
+#endif
+                        sc->cci_current_level = input_level;
+                        sc->cci_current_gate = i;
+                        sc->cci_modified = true;
+#ifdef DEBUG_MITIGATE_CCI
+                        if (sc->sh->cfg.cci & CCI_DBG) {
+                            printk("Set to ADR_WIFI_11B_RX_REG_040[%x] ADR_WIFI_11GN_RX_REG_040[%x]!!\n",
+                                   adjust_cci[sc->cci_current_gate].adjust_cck_cca_control,
+                                   adjust_cci[sc->cci_current_gate].adjust_ofdm_cca_control);
+                        }
+#endif
+                        return;
+                    }
+                }
+            } else {
+                for (i = (sizeof(adjust_cci)/sizeof(adjust_cci[0]) -1); i >= 0; i--) {
+                    if (input_level >= adjust_cci[i].down_level) {
+#ifdef DEBUG_MITIGATE_CCI
+                        if (sc->sh->cfg.cci & CCI_DBG) {
+                            printk("gate=%d, input_level=%d, adjust_cci[%d].upper_level=%d, cck value=%08x, ofdm value= %08x\n",
+                                   sc->cci_current_gate, input_level, i, adjust_cci[i].upper_level
+                                   , adjust_cci[i].adjust_cck_cca_control, adjust_cci[i].adjust_ofdm_cca_control);
+                        }
+#endif
+                        sc->cci_current_level = input_level;
+                        sc->cci_current_gate = i;
+                        sc->cci_modified = true;
+#ifdef DEBUG_MITIGATE_CCI
+                        if (sc->sh->cfg.cci & CCI_DBG) {
+                            printk("Set to ADR_WIFI_11B_RX_REG_040[%x] ADR_WIFI_11GN_RX_REG_040[%x]!!\n",
+                                   adjust_cci[sc->cci_current_gate].adjust_cck_cca_control,
+                                   adjust_cci[sc->cci_current_gate].adjust_ofdm_cca_control);
+                        }
+#endif
+                        return;
+                    }
+                }
+            }
+        }
+    }
+    return;
+}
+#endif
+void ssv6006_update_rxstatus(struct ssv_softc *sc,
+                             struct sk_buff *rx_skb, struct ieee80211_rx_status *rxs)
+{
+    struct ssv6006_rxphy_info *rxphy;
+    struct ieee80211_sta *sta = NULL;
+    struct ssv_sta_priv_data *sta_priv = NULL;
+    struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(rx_skb->data + sc->sh->rx_desc_len);
+    rxphy = (struct ssv6006_rxphy_info *)(rx_skb->data + sizeof(struct ssv6006_rx_desc));
+    sta = ssv6xxx_find_sta_by_rx_skb(sc, rx_skb);
+    if(sta) {
+#ifdef CONFIG_SSV_CCI_IMPROVEMENT
+        sc-> cci_rx_unavailable_counter = 0;
+#endif
+        if (ieee80211_is_data(hdr->frame_control)) {
+            sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+            sc->rx_data_exist = true;
+            sta_priv->rxstats.phy_mode = ((rxphy-> phy_rate & SSV6006RC_PHY_MODE_MSK) >> SSV6006RC_PHY_MODE_SFT);
+            sta_priv->rxstats.ht40 = ((rxphy-> phy_rate & SSV6006RC_20_40_MSK) >> SSV6006RC_20_40_SFT);
+            if (sta_priv->rxstats.phy_mode == SSV6006RC_B_MODE) {
+                sta_priv->rxstats.cck_pkts[(rxphy-> phy_rate) & SSV6006RC_B_RATE_MSK] ++;
+            } else if (sta_priv->rxstats.phy_mode == SSV6006RC_N_MODE) {
+                sta_priv->rxstats.n_pkts[(rxphy-> phy_rate) & SSV6006RC_RATE_MSK] ++;
+            } else {
+                sta_priv->rxstats.g_pkts[(rxphy-> phy_rate) & SSV6006RC_RATE_MSK] ++;
+            }
+        }
+    }
+    if((ieee80211_is_beacon(hdr->frame_control))||(ieee80211_is_probe_resp(hdr->frame_control))) {
+        if (sta) {
+            sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+#ifdef SSV_RSSI_DEBUG
+            printk("beacon %02X:%02X:%02X:%02X:%02X:%02X rxphy->rssi=%d\n",
+                   hdr->addr2[0], hdr->addr2[1], hdr->addr2[2],
+                   hdr->addr2[3], hdr->addr2[4], hdr->addr2[5], rxphy->rssi);
+#endif
+            if(sta_priv->beacon_rssi) {
+                sta_priv->beacon_rssi = ((rxphy->rssi<< RSSI_DECIMAL_POINT_SHIFT)
+                                         + ((sta_priv->beacon_rssi<<RSSI_SMOOTHING_SHIFT) - sta_priv->beacon_rssi)) >> RSSI_SMOOTHING_SHIFT;
+                rxphy->rssi = (sta_priv->beacon_rssi >> RSSI_DECIMAL_POINT_SHIFT);
+            } else
+                sta_priv->beacon_rssi = (rxphy->rssi<< RSSI_DECIMAL_POINT_SHIFT);
+#ifdef SSV_RSSI_DEBUG
+            printk("Beacon smoothing RSSI %d %d\n",rxphy->rssi, sta_priv->beacon_rssi>> RSSI_DECIMAL_POINT_SHIFT);
+#endif
+#ifdef CONFIG_SSV_CCI_IMPROVEMENT
+            {
+                int assoc;
+                assoc = ssvxxx_get_sta_assco_cnt(sc);
+                if ((sc->ap_vif == NULL) && (assoc == 1)) {
+                    ssv6006_update_data_cci_setting(sc, sta_priv, rxphy->rssi);
+                    _update_green_tx(sc, rxphy->rssi);
+                }
+            }
+#endif
+        }
+        if ( sc->sh->cfg.beacon_rssi_minimal ) {
+            if ( rxphy->rssi > sc->sh->cfg.beacon_rssi_minimal )
+                rxphy->rssi = sc->sh->cfg.beacon_rssi_minimal;
+        }
+#if 0
+        printk("beacon %02X:%02X:%02X:%02X:%02X:%02X rxphypad-rpci=%d RxResult=%x wsid=%x\n",
+               hdr->addr2[0], hdr->addr2[1], hdr->addr2[2],
+               hdr->addr2[3], hdr->addr2[4], hdr->addr2[5], rxdesc->rssi, rxdesc->RxResult, wsid);
+#endif
+    }
+    if (sta) {
+        sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+        rxs->signal = - (sta_priv->beacon_rssi >> RSSI_DECIMAL_POINT_SHIFT);
+    } else {
+        rxs->signal = (-rxphy->rssi);
+    }
+}
+static void _cmd_rc_setting(struct ssv_hw *sh, int argc, char *argv[])
+{
+    char *endp;
+    int val;
+    struct ssv_cmd_data *cmd_data = &sh->sc->cmd_data;
+    struct rc_setting *rc_setting = &sh->cfg.rc_setting;
+    val = simple_strtoul(argv[4], &endp, 0);
+    snprintf_res(cmd_data, "\n set rc %s to %d\n", argv[3], val);
+    if (!strcmp(argv[3], "force_sample_pr")) {
+        rc_setting->force_sample_pr = val;
+    } else if (!strcmp(argv[3], "aging_period")) {
+        rc_setting->aging_period = val;
+    } else if (!strcmp(argv[3], "target_success_67")) {
+        rc_setting->target_success_67 = val;
+    } else if (!strcmp(argv[3], "target_success_5")) {
+        rc_setting->target_success_5 = val;
+    } else if (!strcmp(argv[3], "target_success_4")) {
+        rc_setting->target_success_4 = val;
+    } else if (!strcmp(argv[3], "target_success")) {
+        rc_setting->target_success = val;
+    } else if (!strcmp(argv[3], "up_pr")) {
+        rc_setting->up_pr = val;
+    } else if (!strcmp(argv[3], "up_pr3")) {
+        rc_setting->up_pr3 = val;
+    } else if (!strcmp(argv[3], "up_pr4")) {
+        rc_setting->up_pr4 = val;
+    } else if (!strcmp(argv[3], "up_pr5")) {
+        rc_setting->up_pr5 = val;
+    } else if (!strcmp(argv[3], "up_pr6")) {
+        rc_setting->up_pr6 = val;
+    } else if (!strcmp(argv[3], "forbid")) {
+        rc_setting->forbid = val;
+    } else if (!strcmp(argv[3], "forbid3")) {
+        rc_setting->forbid3 = val;
+    } else if (!strcmp(argv[3], "forbid4")) {
+        rc_setting->forbid4 = val;
+    } else if (!strcmp(argv[3], "forbid5")) {
+        rc_setting->forbid5 = val;
+    } else if (!strcmp(argv[3], "forbid6")) {
+        rc_setting->forbid6 = val;
+    } else if (!strcmp(argv[3], "sample_pr_4")) {
+        rc_setting->sample_pr_4 = val;
+    } else if (!strcmp(argv[3], "sample_pr_5")) {
+        rc_setting->sample_pr_5 = val;
+    } else {
+        snprintf_res(cmd_data, "\n rc set rc_setting [patch] [val]\n");
+        return;
+    }
+    snprintf_res(cmd_data, "current rc setting:\n");
+    snprintf_res(cmd_data, "\t aging_period %d\t force_sample_pr %d\t sample_pr_4 %d \t sample_pr_5 %d\n",
+                 rc_setting->aging_period, rc_setting->force_sample_pr,
+                 rc_setting->sample_pr_4, rc_setting->sample_pr_5);
+    snprintf_res(cmd_data, "\t target_success_67 %d \t target_success_5 %d\t target_success_4 %d\t target_success %d\n",
+                 rc_setting->target_success_67, rc_setting->target_success_5,
+                 rc_setting->target_success_4, rc_setting->target_success);
+    snprintf_res(cmd_data, "\t up_pr %d\t up_pr3 %d \t up_pr4 %d\t up_pr5 %d\t up_pr6 %d\n",
+                 rc_setting->up_pr, rc_setting->up_pr3, rc_setting->up_pr4,
+                 rc_setting->up_pr5, rc_setting->up_pr6);
+    snprintf_res(cmd_data, "\t forbid %d\t forbid3 %d \t forbid5 %d\t forbid5 %d\t forbid6 %d\n",
+                 rc_setting->forbid, rc_setting->forbid3, rc_setting->forbid4,
+                 rc_setting->forbid5, rc_setting->forbid6);
+}
+static void _sta_txstats(struct ssv_softc *sc, struct ssv_sta_priv_data *sta_priv)
+{
+    struct ssv_minstrel_sta_priv *minstrel_sta_priv = sta_priv->rc_info;
+    struct ssv_minstrel_sta_info *legacy;
+    struct ssv_minstrel_ht_sta *ht;
+    struct ssv_minstrel_ht_mcs_group_data *mg;
+    unsigned int i, j, tp, prob, eprob;
+    unsigned int max_mcs = MINSTREL_MAX_STREAMS * MINSTREL_STREAM_GROUPS;
+    int bitrates[4] = { 10, 20, 55, 110 };
+    int max_ht_groups = 0;
+    struct ssv_cmd_data *cmd_data = &sc->cmd_data;
+    struct ssv_hw *sh = sc->sh;
+    if (!minstrel_sta_priv->is_ht) {
+        legacy = (struct ssv_minstrel_sta_info *)&minstrel_sta_priv->legacy;
+        snprintf_res(cmd_data, "rate     throughput  ewma prob   this prob  "
+                     "this succ/attempt   success    attempts\n");
+        for (i = 0; i < legacy->n_rates; i++) {
+            struct ssv_minstrel_rate *mr = &minstrel_sta_priv->ratelist[i];
+            snprintf_res(cmd_data,"%c", (i == legacy->max_tp_rate) ? 'T' : ' ');
+            snprintf_res(cmd_data,"%c", (i == legacy->max_tp_rate2) ? 't' : ' ');
+            snprintf_res(cmd_data,"%c", (i == legacy->max_prob_rate) ? 'P' : ' ');
+            snprintf_res(cmd_data, "%3u%s", mr->bitrate / 10, (mr->bitrate & 1 ? ".5" : "  "));
+            tp = mr->cur_tp/(1024*1024);
+            prob = MINSTREL_TRUNC(mr->cur_prob * 1000);
+            eprob = MINSTREL_TRUNC(mr->probability * 1000);
+            snprintf_res(cmd_data, "  %6u.%1u   %6u.%1u   %6u.%1u        "
+                         "%3u(%3u)   %8llu    %8llu\n",
+                         tp / 10, tp % 10,
+                         eprob / 10, eprob % 10,
+                         prob / 10, prob % 10,
+                         mr->last_success,
+                         mr->last_attempts,
+                         (unsigned long long)mr->succ_hist,
+                         (unsigned long long)mr->att_hist);
+        }
+        snprintf_res(cmd_data, "\nTotal packet count::    total %llu      lookaround %llu\n\n",
+                     legacy->packet_count, legacy->sample_count);
+    } else {
+        ht = (struct ssv_minstrel_ht_sta *)&minstrel_sta_priv->ht;
+        snprintf_res(cmd_data, "%4s %8s %12s %12s %12s %20s %10s %10s\n",
+                     "type", "rate", "throughput", "ewma prob", "this prob", "this succ/attempt", "success", "attempts");
+        max_ht_groups = MINSTREL_MAX_STREAMS * MINSTREL_STREAM_GROUPS + 1;
+        for (i = 0; i < max_ht_groups; i++) {
+            mg = &ht->groups[i];
+            if (!mg->supported)
+                continue;
+            for (j = 0; j < MCS_GROUP_RATES; j++) {
+                struct ssv_minstrel_ht_rate_stats *mhr = &ht->groups[i].rates[j];
+                int idx = i * MCS_GROUP_RATES + j;
+                if (!(ht->groups[i].supported & BIT(j)))
+                    continue;
+                snprintf_res(cmd_data,"%c", (idx == ht->max_tp_rate) ? 'T' : ' ');
+                snprintf_res(cmd_data,"%c", (idx == ht->max_tp_rate2) ? 't' : ' ');
+                snprintf_res(cmd_data,"%c", (idx == ht->max_prob_rate) ? 'P' : ' ');
+                if (i == max_mcs) {
+                    int r = bitrates[j % 4];
+                    snprintf_res(cmd_data, "  %2u.%1uM/%c", r / 10, r % 10, (ht->cck_supported_short ? 'S' : 'L'));
+                } else
+                    snprintf_res(cmd_data, "    MCS%-2u", j);
+                tp = mhr->cur_tp / 10;
+                prob = MINSTREL_TRUNC(mhr->cur_prob * 1000);
+                eprob = MINSTREL_TRUNC(mhr->probability * 1000);
+                snprintf_res(cmd_data, "     %6u.%1u     %6u.%1u     %6u.%1u            %3u(%3u)    %8llu   %8llu\n",
+                             tp / 10, tp % 10,
+                             eprob / 10, eprob % 10,
+                             prob / 10, prob % 10,
+                             mhr->last_success,
+                             mhr->last_attempts,
+                             (unsigned long long)mhr->succ_hist,
+                             (unsigned long long)mhr->att_hist);
+            }
+        }
+        snprintf_res(cmd_data, "\nTotal packet count::    total %llu      lookaround %llu, short GI state = %d\n\n",
+                     ht->total_packets, ht->sample_packets, ht->sgi_state);
+        snprintf_res(cmd_data, "\nAMPDU Retry # statistics:: hw_retry_acc %d, hw_success_acc %d\n", ht->hw_retry_acc, ht->hw_success_acc);
+        for (i = 0; i < 16; i++) {
+            snprintf_res(cmd_data, " %2d:%8d", i+1, sta_priv->retry_samples[i]);
+            if (i%8 == 7) snprintf_res(cmd_data, "\n");
+        }
+    }
+    snprintf_res(cmd_data, "\nACK(BA) fail count %3d, BA NTF %3d,  ACK NTF %3d, MRX_FCS_ERR %3d, TX_RETRY %3d\n",
+                 GET_MTX_ACK_FAIL, GET_MRX_DUP, GET_MRX_ACK_NTF, GET_MRX_FCS_ERR, GET_MTX_MULTI_RETRY);
+    snprintf_res(cmd_data, "\nAMPDU ERR %3d, AMPDU PKT %3d, PKT_ERR %3d , CCA %3d, PKT_CNT %3d\n",
+                 GET_RO_AMPDU_PACKET_ERR_CNT, GET_RO_AMPDU_PACKET_CNT, GET_RO_11GN_PACKET_ERR_CNT,
+                 GET_RO_11GN_CCA_CNT, GET_RO_11GN_PACKET_CNT);
+    snprintf_res(cmd_data, "\nTx RTS success %3d, Tx RTS Fail %3d\n", GET_MTX_RTS_SUCC, GET_MTX_RTS_FAIL);
+    snprintf_res(cmd_data, "\nHW TX_PAGE_USE : %d, aggr_size %d\n", GET_TX_PAGE_USE_7_0, sta_priv->max_ampdu_size);
+    snprintf_res(cmd_data, "AMPDU tx_frame in q = %d\n", atomic_read(&sc->ampdu_tx_frame));
+    snprintf_res(cmd_data,"\n[TAG]  MCU - HCI - SEC -  RX - MIC - TX0 - TX1 - TX2 - TX3 - TX4 - SEC - MIC - TSH\n");
+    snprintf_res(cmd_data,"OUTPUT %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d\n",
+                 GET_FFO0_CNT, GET_FFO1_CNT, GET_FFO3_CNT, GET_FFO4_CNT, GET_FFO5_CNT, GET_FFO6_CNT,
+                 GET_FFO7_CNT, GET_FFO8_CNT, GET_FFO9_CNT, GET_FFO10_CNT, GET_FFO11_CNT, GET_FFO12_CNT, GET_FFO15_CNT);
+    snprintf_res(cmd_data,"INPUT  %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d\n",
+                 GET_FF0_CNT, GET_FF1_CNT, GET_FF3_CNT, GET_FF4_CNT, GET_FF5_CNT, GET_FF6_CNT,
+                 GET_FF7_CNT, GET_FF8_CNT, GET_FF9_CNT, GET_FF10_CNT, GET_FF11_CNT, GET_FF12_CNT, GET_FF15_CNT);
+    snprintf_res(cmd_data,"TX[%d]RX[%d]AVA[%d]\n",GET_TX_ID_ALC_LEN,GET_RX_ID_ALC_LEN,GET_AVA_TAG);
+    snprintf_res(cmd_data,"\nEDCA primary %d secondary %d\n", GET_PRIMARY_EDCA(sc), GET_SECONDARY_EDCA(sc));
+}
+static void _cmd_txstats(struct ssv_softc *sc)
+{
+    int j, sta_idx = 0;
+    struct ssv_cmd_data *cmd_data = &sc->cmd_data;
+    struct ssv_hw *sh = sc->sh;
+    for (j = 0; j < SSV6200_MAX_VIF; j++) {
+        struct ieee80211_vif *vif = sc->vif_info[j].vif;
+        struct ssv_vif_priv_data *priv_vif;
+        struct ssv_sta_priv_data *sta_priv_iter;
+        if (vif == NULL) {
+            snprintf_res(cmd_data, "    VIF: %d is not used.\n", j);
+            continue;
+        }
+        snprintf_res(cmd_data,
+                     "Tx statistics: VIF: %d - [%02X:%02X:%02X:%02X:%02X:%02X] type[%d] p2p[%d]\n", j,
+                     vif->addr[0], vif->addr[1], vif->addr[2],
+                     vif->addr[3], vif->addr[4], vif->addr[5], vif->type, vif->p2p);
+        priv_vif = (struct ssv_vif_priv_data *)(vif->drv_priv);
+        list_for_each_entry(sta_priv_iter, &priv_vif->sta_list, list) {
+            snprintf_res(cmd_data,"    sta_idx %d \n", sta_idx);
+            if ((sta_priv_iter->sta_info->s_flags & STA_FLAG_VALID) == 0) {
+                snprintf_res(cmd_data, "    STA: %d  is not valid.\n", sta_idx);
+                continue;
+            }
+            _sta_txstats(sc, sta_priv_iter);
+            sta_idx++;
+        }
+    }
+    ssv6006c_reset_mib_mac(sh);
+    ssv6006_reset_mib_phy(sh);
+}
+static void _sta_rxstats(struct ssv_softc *sc, struct ssv_sta_priv_data *sta_priv)
+{
+    struct ssv_cmd_data *cmd_data = &sc->cmd_data;
+    int i;
+    snprintf_res(cmd_data," \t last data packet mode %d, ht40 %d \n", sta_priv->rxstats.phy_mode,
+                 sta_priv->rxstats.ht40);
+    snprintf_res(cmd_data,"\t N packet statistics\n");
+    snprintf_res(cmd_data,"\t MCS0 \t MCS1 \t MCS2 \t MCS3 ");
+    snprintf_res(cmd_data,"\t MCS4 \t MCS5 \t MCS6 \t MCS7\n");
+    for (i = 0; i < SSV6006RC_MAX_RATE; i++) {
+        snprintf_res(cmd_data,"\t %llu", sta_priv->rxstats.n_pkts[i]);
+    }
+    snprintf_res(cmd_data,"\n\t G packet statistics\n");
+    snprintf_res(cmd_data,"\t 6M   \t 9M   \t 12M  \t 18M  ");
+    snprintf_res(cmd_data,"\t 24M  \t 36M  \t 48M  \t 54M\n");
+    for (i = 0; i < SSV6006RC_MAX_RATE; i++) {
+        snprintf_res(cmd_data,"\t %llu", sta_priv->rxstats.g_pkts[i]);
+    }
+    snprintf_res(cmd_data,"\n\t cck packet statistics\n");
+    snprintf_res(cmd_data,"\t 1M   \t 2M  \t 5.5M \t 11M\n");
+    for (i = 0; i < SSV6006RC_B_MAX_RATE; i++) {
+        snprintf_res(cmd_data,"\t %llu", sta_priv->rxstats.cck_pkts[i]);
+    }
+    snprintf_res(cmd_data,"\n");
+}
+static void _cmd_rxstats(struct ssv_softc *sc)
+{
+    int j, sta_idx = 0;
+    struct ssv_cmd_data *cmd_data = &sc->cmd_data;
+    for (j = 0; j < SSV6200_MAX_VIF; j++) {
+        struct ieee80211_vif *vif = sc->vif_info[j].vif;
+        struct ssv_vif_priv_data *priv_vif;
+        struct ssv_sta_priv_data *sta_priv_iter;
+        if (vif == NULL) {
+            snprintf_res(cmd_data, "    VIF: %d is not used.\n", j);
+            continue;
+        }
+        snprintf_res(cmd_data,
+                     "Rx statistics VIF: %d - [%02X:%02X:%02X:%02X:%02X:%02X] type[%d] p2p[%d]\n", j,
+                     vif->addr[0], vif->addr[1], vif->addr[2],
+                     vif->addr[3], vif->addr[4], vif->addr[5], vif->type, vif->p2p);
+        priv_vif = (struct ssv_vif_priv_data *)(vif->drv_priv);
+        list_for_each_entry(sta_priv_iter, &priv_vif->sta_list, list) {
+            snprintf_res(cmd_data,"    sta_idx %d \n", sta_idx);
+            if ((sta_priv_iter->sta_info->s_flags & STA_FLAG_VALID) == 0) {
+                snprintf_res(cmd_data, "    STA: %d  is not valid.\n", sta_idx);
+                continue;
+            }
+            _sta_rxstats(sc, sta_priv_iter);
+            sta_idx++;
+        }
+    }
+}
+static void _cmd_autosgi(struct ssv_hw *sh, int argc, char *argv[])
+{
+    struct ssv_cmd_data *cmd_data = &sh->sc->cmd_data;
+    if (!strcmp(argv[2], "enable")) {
+        sh->cfg.auto_sgi |= AUTOSGI_CTL;
+    } else if (!strcmp(argv[2], "disable")) {
+        sh->cfg.auto_sgi &= ~(AUTOSGI_CTL);
+    } else if (!strcmp(argv[2], "dbg")) {
+        if (!strcmp(argv[3], "enable")) {
+            sh->cfg.auto_sgi |= AUTOSGI_DBG;
+        } else if (!strcmp(argv[3], "disable")) {
+            sh->cfg.auto_sgi &= ~(AUTOSGI_DBG);
+        }
+    }
+    snprintf_res(cmd_data, "\n cfg.auto_sgi %d \n", sh->cfg.auto_sgi);
+}
+static void ssv6006_cmd_rc(struct ssv_hw *sh, int argc, char *argv[])
+{
+    char *endp;
+    int val;
+    struct ssv_cmd_data *cmd_data = &sh->sc->cmd_data;
+    if (argc < 2) {
+        snprintf_res(cmd_data, "\n rc show | set | txstats \n");
+        return;
+    }
+    if (!strcmp(argv[1], "show")) {
+        ;
+    } else if (!strcmp(argv[1], "set")) {
+        if (argc == 4) {
+            val = simple_strtoul(argv[3], &endp, 0);
+            snprintf_res(cmd_data, "\n set rc %s to %d\n", argv[2], val);
+            if (!strcmp(argv[2], "auto")) {
+                sh->cfg.auto_rate_enable = val;
+            } else if (!strcmp(argv[2], "auto")) {
+                sh->cfg.rc_rate_idx_set = val;
+            } else if (!strcmp(argv[2], "rate")) {
+                sh->cfg.rc_rate_idx_set = val;
+            } else if (!strcmp(argv[2], "retry")) {
+                sh->cfg.rc_retry_set = val;
+            } else if (!strcmp(argv[2], "green")) {
+                sh->cfg.rc_mf = val;
+            } else if (!strcmp(argv[2], "short")) {
+                sh->cfg.rc_long_short = val;
+            } else if (!strcmp(argv[2], "ht40")) {
+                sh->cfg.rc_ht40 = val;
+            } else if (!strcmp(argv[2], "phy")) {
+                sh->cfg.rc_phy_mode = val;
+            } else if (!strcmp(argv[2], "rc_log")) {
+                sh->cfg.rc_log = val;
+            } else {
+                snprintf_res(cmd_data, "\n rc set auto| rate | retry | green | short | ht40 | phy | rc_log [val]\n");
+                return;
+            }
+        } else if (argc ==5) {
+            if (!strcmp(argv[2], "rc_setting")) {
+                _cmd_rc_setting(sh, argc, argv);
+            } else {
+                snprintf_res(cmd_data, "\n rc set rc_setting [patch] [val]\n");
+            }
+            return;
+        } else {
+            snprintf_res(cmd_data, "\n rc set auto| rate | retry | green | short | ht40 | phy | rc_log |rc_setting [val]\n");
+            return;
+        }
+    } else if (!strcmp(argv[1], "txstats")) {
+        _cmd_txstats(sh->sc);
+        return;
+    } else if (!strcmp(argv[1], "rxstats")) {
+        _cmd_rxstats(sh->sc);
+        return;
+    } else if ((!strcmp(argv[1], "autosgi")) && (argc <= 4)) {
+        _cmd_autosgi(sh, argc, argv);
+        return;
+    } else {
+        snprintf_res(cmd_data, "\n rc show|set|txstats|rxstats|autosgi \n");
+        return;
+    }
+    snprintf_res(cmd_data, "\n fix rate control parameters for ssv6006\n");
+    snprintf_res(cmd_data, " auto rate enable         : %s\n", (sh->cfg.auto_rate_enable) ? "True": "False");
+    snprintf_res(cmd_data, " rc_rate_idx_set          : 0x%04x\n", sh->cfg.rc_rate_idx_set);
+    snprintf_res(cmd_data, " rc_retry_set             : 0x%04x\n", sh->cfg.rc_retry_set);
+    snprintf_res(cmd_data, " rc mix mode              : %s\n",(sh->cfg.rc_mf) ? "Green": "Mix");
+    snprintf_res(cmd_data, " rc long/short GI/Preambe : %s\n", (sh->cfg.rc_long_short ) ? "Short": "Long");
+    snprintf_res(cmd_data, " rc ht40/h20              : %s\n", sh->cfg.rc_ht40 ? "HT40":"HT20");
+    snprintf_res(cmd_data, " rc phy mode              :");
+    if (sh->cfg.rc_phy_mode == SSV6006RC_B_MODE) {
+        snprintf_res(cmd_data, " B mode\n");
+    } else if (sh->cfg.rc_phy_mode == SSV6006RC_G_MODE) {
+        snprintf_res(cmd_data, " G mode\n");
+    } else {
+        snprintf_res(cmd_data, " %s\n", (sh->cfg.rc_phy_mode == SSV6006RC_N_MODE) ? "N mode" : "Invalid");
+    }
+    snprintf_res(cmd_data, " rc log                   : %s\n", (sh->cfg.rc_log) ? "True": "False");
+    return;
+}
+bool ssv6006_is_legacy_rate(struct ssv_softc *sc, struct sk_buff *skb)
+{
+    bool ret = true;
+    struct ieee80211_tx_info *info;
+    info = IEEE80211_SKB_CB(skb);
+    if ((info->control.rates[0].flags & IEEE80211_TX_RC_MCS) &&
+        (info->control.rates[1].flags & IEEE80211_TX_RC_MCS) &&
+        (info->control.rates[2].flags & IEEE80211_TX_RC_MCS)) {
+        ret = false;
+    }
+    return ret;
+}
+static void ssv6006_rc_algorithm(struct ssv_softc *sc)
+{
+    struct ieee80211_hw *hw=sc->hw;
+    hw->rate_control_algorithm = "ssv_minstrel";
+}
+static void ssv6006_set_80211_hw_rate_config(struct ssv_softc *sc)
+{
+    struct ieee80211_hw *hw=sc->hw;
+    hw->max_rates = SSV6006RC_MAX_RATE_SERIES;
+    hw->max_rate_tries = SSV6006RC_MAX_RATE_RETRY;
+}
+static void ssv6006_rc_rx_data_handler(struct ssv_softc *sc, struct sk_buff *skb, u32 rate_index)
+{
+    if (sc->log_ctrl & LOG_RX_DESC) {
+        struct ieee80211_sta *sta;
+        struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data + sc->sh->rx_desc_len);
+        if (!(ieee80211_is_beacon(hdr->frame_control))) {
+            sta = ssv6xxx_find_sta_by_rx_skb(sc, skb);
+            if (sta != NULL)
+                ssv6006_dump_rx_desc(skb);
+        }
+    }
+}
+static void ssv6006_rate_report_nullfunc_handler(struct ssv_softc *sc, struct sk_buff *skb)
+{
+    struct ssv6006_tx_desc *tx_desc = (struct ssv6006_tx_desc *)skb->data;
+    struct sk_buff *beacon;
+    struct ieee80211_mgmt *hdr;
+    struct hci_rx_aggr_info *rx_aggr_info;
+    unsigned int time_diff;
+    unsigned char *pdata = NULL;
+    int rx_mode = sc->sh->rx_mode;
+    int alignment_size = 0;
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+    struct sk_buff_head rx_list;
+#endif
+    if (sc->beacon_container == NULL)
+        return;
+    if (tx_desc->rpt_result0 != 0) {
+        beacon = ssv_skb_alloc(sc, sc->beacon_container->len + sizeof(struct hci_rx_aggr_info) + 4);
+        if (!skb)
+            return;
+        if ((rx_mode == RX_HW_AGG_MODE) || (rx_mode == RX_HW_AGG_MODE_METH3)) {
+            pdata = skb_put(beacon, sizeof(struct hci_rx_aggr_info));
+            rx_aggr_info = (struct hci_rx_aggr_info *)pdata;
+            memset(rx_aggr_info, 0, sizeof(struct hci_rx_aggr_info));
+            rx_aggr_info->jmp_mpdu_len = ((sc->beacon_container->len + 3) / 4) * 4 + sizeof(struct hci_rx_aggr_info);
+            rx_aggr_info->accu_rx_len = ((sc->beacon_container->len + 3) / 4) * 4 + sizeof(struct hci_rx_aggr_info);
+        }
+        pdata = skb_put(beacon, sc->beacon_container->len);
+        memcpy(pdata, sc->beacon_container->data, sc->beacon_container->len);
+        hdr = (struct ieee80211_mgmt *)(pdata + sc->sh->rx_desc_len);
+        time_diff = jiffies_to_msecs(abs(jiffies - sc->beacon_container_update_time));
+        hdr->u.beacon.timestamp += time_diff;
+        if ((rx_mode == RX_HW_AGG_MODE) || (rx_mode == RX_HW_AGG_MODE_METH3)) {
+            alignment_size = rx_aggr_info->jmp_mpdu_len - beacon->len;
+            if (alignment_size != 0)
+                skb_put(beacon, alignment_size);
+        }
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+        skb_queue_head_init(&rx_list);
+        __skb_queue_tail(&rx_list, beacon);
+        ssv6200_rx(&rx_list, sc);
+#else
+        ssv6200_rx(beacon, sc);
+#endif
+    } else {
+        dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_BEACON, "nullfunc result is fail.\n");
+    }
+}
+static bool ssv6006_rate_report_filter(struct ssv_softc *sc, struct sk_buff *skb)
+{
+    struct ssv6006_tx_desc *tx_desc = (struct ssv6006_tx_desc *)skb->data;
+    if (tx_desc->tx_pkt_run_no == SSV6XXX_PKT_RUN_TYPE_NULLFUN) {
+        ssv6006_rate_report_nullfunc_handler(sc, skb);
+        return true;
+    }
+    return false;
+}
+static void ssv6006_rate_report_handler(struct ssv_softc *sc, struct sk_buff *skb, bool *no_ba_result)
+{
+    struct ssv6006_tx_desc *tx_desc = (struct ssv6006_tx_desc *)skb->data;
+    if (sc->log_ctrl & LOG_RATE_REPORT) {
+        printk(" Dump tx desc from rate report:\n");
+        ssv6006_dump_ssv6006_txdesc(skb);
+    }
+    if (ssv6006_rate_report_filter(sc, skb)) {
+        dev_kfree_skb_any(skb);
+        return;
+    }
+    if (tx_desc->aggr != 0) {
+        if ((tx_desc->rpt_result0 == 0) &&
+            (tx_desc->rpt_result1 == 0) &&
+            (tx_desc->rpt_result2 == 0) &&
+            (tx_desc->rpt_result3 == 0)) {
+            *no_ba_result = true;
+        }
+    }
+    skb_queue_tail(&sc->rc_report_queue, skb);
+    if (sc->rc_report_sechedule == 0)
+        queue_work(sc->rc_report_workqueue, &sc->rc_report_work);
+}
+static int ssv6006_get_tx_desc_rate_rpt(struct ssv_softc *sc, struct ssv6006_tx_desc *tx_desc,
+                                        int idx, u8 *drate, u8 *success, u8 *trycnt)
+{
+    switch (idx) {
+    case 0:
+        *drate = tx_desc->drate_idx0;
+        *success = tx_desc->rpt_result0;
+        *trycnt = tx_desc->rpt_trycnt0;
+        return tx_desc->is_last_rate0;
+    case 1:
+        *drate = tx_desc->drate_idx1;
+        *success = tx_desc->rpt_result1;
+        *trycnt = tx_desc->rpt_trycnt1;
+        return tx_desc->is_last_rate1;
+    case 2:
+        *drate = tx_desc->drate_idx2;
+        *success = tx_desc->rpt_result2;
+        *trycnt = tx_desc->rpt_trycnt2;
+        return tx_desc->is_last_rate2;
+    case 3:
+        *drate = tx_desc->drate_idx3;
+        *success = tx_desc->rpt_result3;
+        *trycnt = tx_desc->rpt_trycnt3;
+        return tx_desc->is_last_rate3;
+    default:
+        *drate = -1;
+        *success = 0;
+        *trycnt = 0;
+        return 0;
+    }
+}
+static void _update_ht_rpt(struct ssv_softc *sc, struct ssv6006_tx_desc *tx_desc,
+                           struct ssv_minstrel_ht_rpt *ht_rpt)
+{
+    u8 drate, success, rpt_trycnt, last;
+    int i;
+    for (i = 0; i < SSV6006RC_MAX_RATE_SERIES; i++) {
+        last = ssv6006_get_tx_desc_rate_rpt(sc, tx_desc, i, &drate, &success, &rpt_trycnt);
+        ht_rpt[i].dword = drate;
+        ht_rpt[i].count = rpt_trycnt;
+        ht_rpt[i].success = success;
+        ht_rpt[i].last = last;
+        if ((drate < 0) || success)
+            ht_rpt[i].last = 1;
+        if (ht_rpt[i].last)
+            break;
+    }
+}
+static void ssv6006_rc_no_ba_handler(struct ssv_softc *sc, struct sk_buff *report)
+{
+    struct ssv6006_tx_desc *tx_desc = (struct ssv6006_tx_desc *)report->data;
+    struct ssv_sta_info *ssv_sta;
+    struct ssv_sta_priv_data *ssv_sta_priv;
+    struct AMPDU_TID_st *ampdu_tid;
+    int i, cur_ampdu_idx;
+    struct ssv_minstrel_ht_rpt ht_rpt[SSV6006RC_MAX_RATE_SERIES];
+    int mpdu_num = 0;
+    u8 tid_no = 0;
+    if (tx_desc->wsid >= SSV_NUM_STA) {
+        dev_warn(sc->dev, "%s(): wsid[%d] is invaild!!\n", __FUNCTION__, tx_desc->wsid);
+        return;
+    }
+    down_read(&sc->sta_info_sem);
+    ssv_sta = &sc->sta_info[tx_desc->wsid];
+    if ((ssv_sta->s_flags & STA_FLAG_VALID) == 0) {
+        up_read(&sc->sta_info_sem);
+        dev_warn(sc->dev, "%s(): sta_info is gone. (%d)\n", __FUNCTION__, tx_desc->wsid);
+        return;
+    }
+    if (!ssv_sta->sta) {
+        up_read(&sc->sta_info_sem);
+        dev_warn(sc->dev, "%s(): Cannot find the station\n", __FUNCTION__);
+        return;
+    }
+    ssv_sta_priv = (struct ssv_sta_priv_data *)ssv_sta->sta->drv_priv;
+    for (i = 0; i < MAX_CONCUR_AMPDU; i ++) {
+        if (ssv_sta_priv->ampdu_ssn[i].tx_pkt_run_no == tx_desc->tx_pkt_run_no) {
+            cur_ampdu_idx = i;
+            mpdu_num = ssv_sta_priv->ampdu_ssn[i].mpdu_num;
+            break;
+        }
+    }
+    if (i == MAX_CONCUR_AMPDU) {
+        up_read(&sc->sta_info_sem);
+        dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_AMPDU_SSN,"%s:tx_pkt_run_no %d not found on sent list.\n",
+                 __FUNCTION__, tx_desc->tx_pkt_run_no );
+        return;
+    }
+    tid_no = ssv_sta_priv->ampdu_ssn[cur_ampdu_idx].tid_no;
+    ampdu_tid = &(ssv_sta_priv->ampdu_tid[tid_no]);
+    for (i = 0; i < ssv_sta_priv->ampdu_ssn[cur_ampdu_idx].mpdu_num; i++) {
+        u16 ssn = ssv_sta_priv->ampdu_ssn[cur_ampdu_idx].ssn[i];
+        struct sk_buff *skb;
+        u32 skb_ssn;
+        struct SKB_info_st *skb_info;
+        skb = INDEX_PKT_BY_SSN(ampdu_tid, ssn);
+        skb_ssn = (skb == NULL) ? (-1) : ampdu_skb_ssn(skb);
+        if (skb_ssn != ssn) {
+            dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_AMPDU_SSN, "%s(): Unmatched SSN packet: %d - %d\n",
+                     __FUNCTION__, ssn, skb_ssn);
+            continue;
+        }
+        skb_info = (struct SKB_info_st *) (skb->head);
+        if (skb_info->ampdu_tx_status == AMPDU_ST_SENT) {
+            if (skb_info->mpdu_retry_counter < SSV_AMPDU_retry_counter_max) {
+                if (skb_info->mpdu_retry_counter == 0) {
+                    struct ieee80211_hdr *skb_hdr = ampdu_skb_hdr(skb);
+                    skb_hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
+                }
+                skb_info->ampdu_tx_status = AMPDU_ST_RETRY;
+                ssv_sta_priv->retry_samples[skb_info->mpdu_retry_counter]++;
+                skb_info->mpdu_retry_counter++;
+            } else {
+                skb_info->ampdu_tx_status = AMPDU_ST_DROPPED;
+                dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_AMPDU_SSN, "%s(), drop skb ssn[%d]\n", __FUNCTION__, skb_ssn);
+            }
+        } else {
+            dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_AMPDU_SSN, "%s() skb ssn[%d] status[%d]\n",
+                     __FUNCTION__, skb_ssn, skb_info->ampdu_tx_status);
+        }
+    }
+    ssv6xxx_release_frames(ampdu_tid);
+    memset((void*)&ssv_sta_priv->ampdu_ssn[cur_ampdu_idx], 0, sizeof(struct aggr_ssn));
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_AMPDU_SSN, "%s(): ampdu slot=%d, tx_pkt_run_no=%d\n",
+             __FUNCTION__, ((cur_ampdu_idx <MAX_CONCUR_AMPDU) ? cur_ampdu_idx : (-1)), tx_desc->tx_pkt_run_no);
+    _update_ht_rpt(sc, tx_desc, ht_rpt);
+    if (sc->sh->cfg.auto_rate_enable == true) {
+        ssv_minstrel_ht_tx_status(sc, ssv_sta_priv->rc_info, ht_rpt, SSV6006RC_MAX_RATE_SERIES,
+                                  mpdu_num, 0, tx_desc->is_rate_stat_sample_pkt);
+    }
+    up_read(&sc->sta_info_sem);
+}
+bool ssv6006_rc_get_previous_ampdu_rpt(struct ssv_minstrel_ht_sta *mhs, int pkt_no, int *rpt_idx)
+{
+    bool ret = false;
+    int i;
+    for (i = 0; i < SSV_MINSTREL_AMPDU_RATE_RPTS; i++) {
+        if ((mhs->ampdu_rpt_list[i].used) && (pkt_no == mhs->ampdu_rpt_list[i].pkt_no)) {
+            *rpt_idx = i;
+            ret = true;
+            break;
+        }
+    }
+    return ret;
+}
+void ssv6006_rc_add_ampdu_rpt_to_list(struct ssv_softc *sc, struct ssv_minstrel_ht_sta *mhs, void *rate_rpt,
+                                      int pkt_no, int ampdu_len, int ampdu_ack_len)
+{
+    int i = 0, idx = -1;
+    struct ssv6006_tx_desc *tx_desc;
+    struct ssv_minstrel_ampdu_rate_rpt *ampdu_rpt;
+    u8 drate, success, rpt_trycnt;
+    int last = 0;
+    for (i = 0; i < SSV_MINSTREL_AMPDU_RATE_RPTS; i++) {
+        if (mhs->ampdu_rpt_list[i].used == false) {
+            idx = i;
+            break;
+        }
+    }
+    if (idx == -1) {
+        printk("AMPDU rpt list is full\n");
+        WARN_ON(1);
+        return;
+    }
+    ampdu_rpt = (struct ssv_minstrel_ampdu_rate_rpt *)&mhs->ampdu_rpt_list[idx];
+    if (!rate_rpt) {
+        ampdu_rpt->pkt_no = pkt_no;
+        ampdu_rpt->ampdu_len = ampdu_len;
+        ampdu_rpt->ampdu_ack_len = ampdu_ack_len;
+        ampdu_rpt->used = true;
+    } else {
+        tx_desc = (struct ssv6006_tx_desc *)rate_rpt;
+        ampdu_rpt->pkt_no = tx_desc->tx_pkt_run_no;
+        ampdu_rpt->is_sample = tx_desc->is_rate_stat_sample_pkt;
+        for (i = 0; i < SSV6006RC_MAX_RATE_SERIES; i++) {
+            last = ssv6006_get_tx_desc_rate_rpt(sc, tx_desc, i, &drate, &success, &rpt_trycnt);
+            ampdu_rpt->rate_rpt[i].dword = drate;
+            ampdu_rpt->rate_rpt[i].count = rpt_trycnt;
+            ampdu_rpt->rate_rpt[i].success = success;
+            ampdu_rpt->rate_rpt[i].last = last;
+            if ((drate < 0) || success)
+                ampdu_rpt->rate_rpt[i].last = 1;
+            if (ampdu_rpt->rate_rpt[i].last)
+                break;
+        }
+        ampdu_rpt->used = true;
+    }
+}
+static void ssv6006_rc_ba_handler(struct ssv_softc *sc, void *rate_rpt, u32 wsid)
+{
+    struct ssv6006_tx_desc *tx_desc;
+    struct ssv_sta_priv_data *ssv_sta_priv;
+    struct ssv_sta_info *ssv_sta;
+    struct ssv_minstrel_sta_priv *minstrel_sta_priv;
+    struct ssv_minstrel_ht_sta *mhs;
+    struct ssv_minstrel_ht_rpt ht_rpt[SSV6006RC_MAX_RATE_SERIES];
+    struct ssv_minstrel_ampdu_rate_rpt *ampdu_rpt;
+    int rpt_idx = -1;
+    if ((wsid < 0) || (wsid >= SSV_NUM_STA))
+        return;
+    down_read(&sc->sta_info_sem);
+    ssv_sta = &sc->sta_info[wsid];
+    if ((ssv_sta->s_flags & STA_FLAG_VALID) == 0) {
+        up_read(&sc->sta_info_sem);
+        dev_warn(sc->dev, "%s(): sta_info is gone. (%d)\n", __FUNCTION__, wsid);
+        return;
+    }
+    if (!ssv_sta->sta) {
+        up_read(&sc->sta_info_sem);
+        return;
+    }
+    ssv_sta_priv = (struct ssv_sta_priv_data *)ssv_sta->sta->drv_priv;
+    if((minstrel_sta_priv = (struct ssv_minstrel_sta_priv *)ssv_sta_priv->rc_info) == NULL) {
+        up_read(&sc->sta_info_sem);
+        return;
+    }
+    if (!minstrel_sta_priv->is_ht) {
+        up_read(&sc->sta_info_sem);
+        return;
+    }
+    mhs = (struct ssv_minstrel_ht_sta *)&minstrel_sta_priv->ht;
+    tx_desc = (struct ssv6006_tx_desc *)rate_rpt;
+    if (!ssv6006_rc_get_previous_ampdu_rpt(mhs, tx_desc->tx_pkt_run_no, &rpt_idx)) {
+        ssv6006_rc_add_ampdu_rpt_to_list(sc, mhs, tx_desc, 0, 0, 0);
+    } else {
+        ampdu_rpt = (struct ssv_minstrel_ampdu_rate_rpt *)&mhs->ampdu_rpt_list[rpt_idx];
+        _update_ht_rpt(sc, tx_desc, ht_rpt);
+        if (sc->sh->cfg.auto_rate_enable == true) {
+            ssv_minstrel_ht_tx_status(sc, ssv_sta_priv->rc_info, ht_rpt, SSV6006RC_MAX_RATE_SERIES,
+                                      ampdu_rpt->ampdu_len, ampdu_rpt->ampdu_ack_len,
+                                      tx_desc->is_rate_stat_sample_pkt);
+        }
+        ampdu_rpt->used = false;
+    }
+    up_read(&sc->sta_info_sem);
+}
+void ssv6006_rc_legacy_bitrate_to_rate_desc(int bitrate, u8 *drate)
+{
+    *drate = 0;
+    switch (bitrate) {
+    case 10:
+        *drate = ((SSV6006RC_B_MODE << SSV6006RC_PHY_MODE_SFT) | (SSV6006RC_B_1M << SSV6006RC_RATE_SFT));
+        return;
+    case 20:
+        *drate = ((SSV6006RC_B_MODE << SSV6006RC_PHY_MODE_SFT) | (SSV6006RC_B_2M << SSV6006RC_RATE_SFT));
+        return;
+    case 55:
+        *drate = ((SSV6006RC_B_MODE << SSV6006RC_PHY_MODE_SFT) | (SSV6006RC_B_5_5M << SSV6006RC_RATE_SFT));
+        return;
+    case 110:
+        *drate = ((SSV6006RC_B_MODE << SSV6006RC_PHY_MODE_SFT) | (SSV6006RC_B_11M << SSV6006RC_RATE_SFT));
+        return;
+    case 60:
+        *drate = ((SSV6006RC_G_MODE << SSV6006RC_PHY_MODE_SFT) | (SSV6006RC_G_6M << SSV6006RC_RATE_SFT));
+        return;
+    case 90:
+        *drate = ((SSV6006RC_G_MODE << SSV6006RC_PHY_MODE_SFT) | (SSV6006RC_G_9M << SSV6006RC_RATE_SFT));
+        return;
+    case 120:
+        *drate = ((SSV6006RC_G_MODE << SSV6006RC_PHY_MODE_SFT) | (SSV6006RC_G_12M << SSV6006RC_RATE_SFT));
+        return;
+    case 180:
+        *drate = ((SSV6006RC_G_MODE << SSV6006RC_PHY_MODE_SFT) | (SSV6006RC_G_18M << SSV6006RC_RATE_SFT));
+        return;
+    case 240:
+        *drate = ((SSV6006RC_G_MODE << SSV6006RC_PHY_MODE_SFT) | (SSV6006RC_G_24M << SSV6006RC_RATE_SFT));
+        return;
+    case 360:
+        *drate = ((SSV6006RC_G_MODE << SSV6006RC_PHY_MODE_SFT) | (SSV6006RC_G_36M << SSV6006RC_RATE_SFT));
+        return;
+    case 480:
+        *drate = ((SSV6006RC_G_MODE << SSV6006RC_PHY_MODE_SFT) | (SSV6006RC_G_48M << SSV6006RC_RATE_SFT));
+        return;
+    case 540:
+        *drate = ((SSV6006RC_G_MODE << SSV6006RC_PHY_MODE_SFT) | (SSV6006RC_G_54M << SSV6006RC_RATE_SFT));
+        return;
+    default:
+        printk("For B/G mode, it doesn't support the bitrate %d kbps\n", bitrate * 100);
+        WARN_ON(1);
+        return;
+    }
+}
+static int ssv6006_rc_legacy_drate_to_ndx(struct ssv_minstrel_sta_priv *minstrel_sta_priv, u8 drate)
+{
+    int i, ndx = -1;
+    int rix = drate & SSV6006RC_RATE_MSK;
+    int band = ((drate & SSV6006RC_PHY_MODE_MSK) >> SSV6006RC_PHY_MODE_SFT);
+    struct ssv_minstrel_sta_info *smi = (struct ssv_minstrel_sta_info *)&minstrel_sta_priv->legacy;
+    if (band & SSV6006RC_G_MODE)
+        ndx = rix + smi->g_rates_offset;
+    else
+        ndx = rix;
+    for (i = ndx; i >= 0; i--)
+        if ((minstrel_sta_priv->ratelist[i].hw_rate_desc & SSV6006RC_RATE_MSK) == rix)
+            break;
+    return i;
+}
+static void ssv6006_rc_process_rate_report(struct ssv_softc *sc, struct sk_buff *skb)
+{
+    struct ssv6006_tx_desc *tx_desc = (struct ssv6006_tx_desc *)skb->data;
+    struct ssv_minstrel_sta_priv *minstrel_sta_priv;
+    struct ssv_minstrel_sta_info *smi;
+    struct ssv_sta_priv_data *sta_priv;
+    struct ssv_sta_info *ssv_sta;
+    struct ssv_minstrel_ht_rpt ht_rpt[SSV6006RC_MAX_RATE_SERIES];
+    int i, ndx;
+    u8 drate, success, rpt_trycnt;
+    int last = 0;
+    if ((tx_desc->rpt_result0 == 3) ||
+        (tx_desc->rpt_result1 == 3) ||
+        (tx_desc->rpt_result2 == 3) ||
+        (tx_desc->rpt_result3 == 3)) {
+        printk("Enter power saving mode and drop the report\n");
+        return;
+    }
+    if (tx_desc->aggr != 0) {
+        if ((tx_desc->rpt_result0 == 0) &&
+            (tx_desc->rpt_result1 == 0) &&
+            (tx_desc->rpt_result2 == 0) &&
+            (tx_desc->rpt_result3 == 0)) {
+            ssv6006_rc_no_ba_handler(sc, skb);
+        } else {
+            ssv6006_rc_ba_handler(sc, tx_desc, tx_desc->wsid);
+        }
+        return;
+    }
+    if (sc->sh->cfg.auto_rate_enable == false)
+        return;
+    if ((tx_desc->wsid < 0) || (tx_desc->wsid >= SSV_NUM_STA)) {
+        dev_warn(sc->dev, "%s(): wsid[%d] is invaild!!\n", __FUNCTION__, tx_desc->wsid);
+        return;
+    }
+    down_read(&sc->sta_info_sem);
+    ssv_sta = &sc->sta_info[tx_desc->wsid];
+    if ((ssv_sta->s_flags & STA_FLAG_VALID) == 0) {
+        up_read(&sc->sta_info_sem);
+        dev_warn(sc->dev, "%s(): ssv_info is gone. (%d)\n", __FUNCTION__, tx_desc->wsid);
+        return;
+    }
+    if (!ssv_sta->sta) {
+        up_read(&sc->sta_info_sem);
+        dev_warn(sc->dev, "%s(): Cannot find the station\n", __FUNCTION__);
+        return;
+    }
+    sta_priv = (struct ssv_sta_priv_data *)ssv_sta->sta->drv_priv;
+    minstrel_sta_priv = (struct ssv_minstrel_sta_priv *)sta_priv->rc_info;
+    if (!minstrel_sta_priv) {
+        up_read(&sc->sta_info_sem);
+        dev_warn(sc->dev, "%s(): Cannot find the station's minstrel data\n", __FUNCTION__);
+        return;
+    }
+    if (!minstrel_sta_priv->is_ht) {
+        smi = (struct ssv_minstrel_sta_info *)&minstrel_sta_priv->legacy;
+        for (i = 0; i < SSV6006RC_MAX_RATE_SERIES; i++) {
+            last = ssv6006_get_tx_desc_rate_rpt(sc, tx_desc, i, &drate, &success, &rpt_trycnt);
+            if (drate < 0)
+                continue;
+            ndx = ssv6006_rc_legacy_drate_to_ndx(minstrel_sta_priv, drate);
+            if (ndx < 0)
+                continue;
+            minstrel_sta_priv->ratelist[ndx].attempts += rpt_trycnt;
+            minstrel_sta_priv->ratelist[ndx].success += success;
+            if (sc->sh->cfg.rc_log) {
+                printk("%s(), bitrate[%d], success=%d, attempts=%d\n", __FUNCTION__,
+                       minstrel_sta_priv->ratelist[ndx].bitrate,
+                       minstrel_sta_priv->ratelist[ndx].attempts,
+                       minstrel_sta_priv->ratelist[ndx].success);
+            }
+            if (last)
+                break;
+        }
+        if (tx_desc->is_rate_stat_sample_pkt)
+            smi->sample_count++;
+        if (smi->sample_deferred > 0)
+            smi->sample_deferred--;
+    } else {
+        for (i = 0; i < SSV6006RC_MAX_RATE_SERIES; i++) {
+            last = ssv6006_get_tx_desc_rate_rpt(sc, tx_desc, i, &drate, &success, &rpt_trycnt);
+            ht_rpt[i].dword = drate;
+            ht_rpt[i].count = rpt_trycnt;
+            ht_rpt[i].success = success;
+            ht_rpt[i].last = last;
+            if ((drate < 0) || success)
+                ht_rpt[i].last = 1;
+            if (ht_rpt[i].last)
+                break;
+        }
+        ssv_minstrel_ht_tx_status(sc, sta_priv->rc_info, ht_rpt, SSV6006RC_MAX_RATE_SERIES,
+                                  1, 1, tx_desc->is_rate_stat_sample_pkt);
+    }
+    up_read(&sc->sta_info_sem);
+}
+static void ssv6006_rc_update_basic_rate(struct ssv_softc *sc, u32 basic_rates)
+{
+    return;
+}
+s32 ssv6006_rc_ht_update_rate(struct sk_buff *skb, struct ssv_softc *sc, struct fw_rc_retry_params *ar)
+{
+    return ssv_minstrel_ht_update_rate(sc, skb);
+}
+bool ssv6006_rc_ht_sta_current_rate_is_cck(struct ieee80211_sta *sta)
+{
+    return ssv_minstrel_ht_sta_is_cck_rates(sta);
+}
+#define NUMBER_OF_MCS 8
+int ssv6006_ampdu_max_transmit_length(struct ssv_softc *sc, struct sk_buff *skb, int rate_idx)
+{
+    struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
+    struct ieee80211_tx_rate *ar;
+    int length = 4429;
+    u32 ampdu_max_transmit_length_lgi[NUMBER_OF_MCS] = {4429, 8860, 13291, 17723, 26586, 35448, 39880, 44311};
+    u32 ampdu_max_transmit_length_sgi[NUMBER_OF_MCS] = {4921, 9844, 14768, 19692, 29539, 39387, 44311, 49234};
+    ar = &info->control.rates[2];
+    if (ar->flags & IEEE80211_TX_RC_MCS) {
+        if (ar->flags & IEEE80211_TX_RC_SHORT_GI) {
+            length = ampdu_max_transmit_length_sgi[ar->idx];
+        } else {
+            length = ampdu_max_transmit_length_lgi[ar->idx];
+        }
+        if ((sc->cur_channel->band == INDEX_80211_BAND_5GHZ) && (ar->flags & IEEE80211_TX_RC_40_MHZ_WIDTH))
+            length = length * 2;
+    }
+    return length;
+}
+static void ssv6006_cmd_cci(struct ssv_hw *sh, int argc, char *argv[])
+{
+    struct ssv_cmd_data *cmd_data = &sh->sc->cmd_data;
+#ifdef CONFIG_SSV_CCI_IMPROVEMENT
+    if ((argc ==2) || (argc ==3)) {
+        if(!strcmp(argv[1], "enable")) {
+            sh->cfg.cci |= CCI_CTL;
+            snprintf_res(cmd_data,"\n\t turn on CCI detection\n");
+        } else if(!strcmp(argv[1], "disable")) {
+            sh->cfg.cci = 0;
+            SMAC_REG_WRITE(sh, ADR_WIFI_11B_RX_REG_040, 0);
+            SMAC_REG_WRITE(sh, ADR_WIFI_11GN_RX_REG_040, 0);
+            sh->sc->cci_current_level = 0;
+            snprintf_res(cmd_data,"\n\t turn off CCI detection\n");
+        } else if(!strcmp(argv[1], "dbg")) {
+            if(!strcmp(argv[2], "enable")) {
+                sh->cfg.cci |= CCI_DBG;
+                snprintf_res(cmd_data,"\n\t turn on CCI DBG\n");
+            } else if(!strcmp(argv[2], "disable")) {
+                sh->cfg.cci &= (~CCI_DBG);
+                snprintf_res(cmd_data,"\n\t turn off CCI DBG\n");
+            }
+        } else if(!strcmp(argv[1], "p1")) {
+            if(!strcmp(argv[2], "enable")) {
+                sh->cfg.cci |= CCI_P1;
+                snprintf_res(cmd_data,"\n\t turn on CCI P1\n");
+            } else if(!strcmp(argv[2], "disable")) {
+                sh->cfg.cci &= (~CCI_P1);
+                snprintf_res(cmd_data,"\n\t turn off CCI P1\n");
+            }
+        } else if(!strcmp(argv[1], "p2")) {
+            if(!strcmp(argv[2], "enable")) {
+                sh->cfg.cci |= CCI_P2;
+                snprintf_res(cmd_data,"\n\t turn on CCI P2\n");
+            } else if(!strcmp(argv[2], "disable")) {
+                sh->cfg.cci &= (~CCI_P2);
+                snprintf_res(cmd_data,"\n\t turn off CCI P2\n");
+            }
+        } else if(!strcmp(argv[1], "smart")) {
+            if(!strcmp(argv[2], "enable")) {
+                sh->cfg.cci |= CCI_SMART;
+                snprintf_res(cmd_data,"\n\t turn on CCI SMART\n");
+            } else if(!strcmp(argv[2], "disable")) {
+                sh->cfg.cci &= (~CCI_SMART);
+                snprintf_res(cmd_data,"\n\t turn off CCI SMART\n");
+            }
+        } else {
+            snprintf_res(cmd_data,"\n\t./cli cci [dbg|p1|p2|smart] enable|disable\n");
+        }
+    } else {
+        snprintf_res(cmd_data,"\n\t./cli cci [dbg|p1|p2|smart] enable|disable\n");
+    }
+    snprintf_res(cmd_data,"\n\t CCI setting 0x%x\n", sh->cfg.cci);
+#else
+    snprintf_res(cmd_data,"\n\t not support cci\n");
+#endif
+}
+void ssv_attach_ssv6006_phy(struct ssv_hal_ops *hal_ops)
+{
+    hal_ops->add_txinfo = ssv6006_add_txinfo;
+    hal_ops->update_txinfo = ssv6006_update_txinfo;
+    hal_ops->update_ampdu_txinfo = ssv6006_update_ampdu_txinfo;
+    hal_ops->add_ampdu_txinfo = ssv6006_add_ampdu_txinfo;
+    hal_ops->update_null_func_txinfo = ssv6006_update_null_func_txinfo;
+    hal_ops->get_tx_desc_size = ssv6006_get_tx_desc_size;
+    hal_ops->get_tx_desc_ctype = ssv6006_get_tx_desc_ctype;
+    hal_ops->get_tx_desc_reason = ssv6006_get_tx_desc_reason;
+    hal_ops->get_tx_desc_txq_idx = ssv6006_get_tx_desc_txq_idx;
+    hal_ops->tx_rate_update = ssv6006_tx_rate_update;
+    hal_ops->txtput_set_desc = ssv6006_txtput_set_desc;
+    hal_ops->fill_beacon_tx_desc = ssv6006_fill_beacon_tx_desc;
+    hal_ops->fill_lpbk_tx_desc = ssv6006_fill_lpbk_tx_desc;
+    hal_ops->chk_lpbk_rx_rate_desc = ssv6006_chk_lpbk_rx_rate_desc;
+    hal_ops->get_sec_decode_err = ssv6006_get_sec_decode_err;
+    hal_ops->get_rx_desc_size = ssv6006_get_rx_desc_size;
+    hal_ops->get_rx_desc_length = ssv6006_get_rx_desc_length;
+    hal_ops->get_rx_desc_wsid = ssv6006_get_rx_desc_wsid;
+    hal_ops->get_rx_desc_rate_idx = ssv6006_get_rx_desc_rate_idx;
+    hal_ops->get_rx_desc_mng_used = ssv6006_get_rx_desc_mng_used;
+    hal_ops->is_rx_aggr = ssv6006_is_rx_aggr;
+    hal_ops->get_rx_desc_ctype = ssv6006_get_rx_desc_ctype;
+    hal_ops->get_rx_desc_hdr_offset = ssv6006_get_rx_desc_hdr_offset;
+    hal_ops->get_rx_desc_info = ssv6006_get_rx_desc_info;
+    hal_ops->nullfun_frame_filter = ssv6006_nullfun_frame_filter;
+    hal_ops->phy_enable = ssv6006_phy_enable;
+    hal_ops->set_phy_mode = ssv6006_set_phy_mode;
+    hal_ops->edca_enable = ssv6006_edca_enable;
+    hal_ops->edca_stat = ssv6006_edca_stat;
+    hal_ops->reset_mib_phy = ssv6006_reset_mib_phy;
+    hal_ops->dump_mib_rx_phy = ssv6006_dump_mib_rx_phy;
+    hal_ops->rc_mac80211_rate_idx = ssv6006_rc_mac80211_rate_idx;
+    hal_ops->update_rxstatus = ssv6006_update_rxstatus;
+#ifdef CONFIG_SSV_CCI_IMPROVEMENT
+    hal_ops->update_scan_cci_setting = ssv6006_update_scan_cci_setting;
+    hal_ops->recover_scan_cci_setting = ssv6006_recover_scan_cci_setting;
+#endif
+    hal_ops->cmd_rc = ssv6006_cmd_rc;
+    hal_ops->is_legacy_rate = ssv6006_is_legacy_rate;
+    hal_ops->ampdu_max_transmit_length = ssv6006_ampdu_max_transmit_length;
+    hal_ops->rc_algorithm = ssv6006_rc_algorithm;
+    hal_ops->set_80211_hw_rate_config = ssv6006_set_80211_hw_rate_config;
+    hal_ops->rc_legacy_bitrate_to_rate_desc = ssv6006_rc_legacy_bitrate_to_rate_desc;
+    hal_ops->rc_rx_data_handler = ssv6006_rc_rx_data_handler;
+    hal_ops->rate_report_handler = ssv6006_rate_report_handler;
+    hal_ops->rc_process_rate_report = ssv6006_rc_process_rate_report;
+    hal_ops->rc_update_basic_rate = ssv6006_rc_update_basic_rate;
+    hal_ops->rc_ht_update_rate = ssv6006_rc_ht_update_rate;
+    hal_ops->rc_ht_sta_current_rate_is_cck = ssv6006_rc_ht_sta_current_rate_is_cck;
+    hal_ops->cmd_cci = ssv6006_cmd_cci;
+}
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/ssv6006_priv.h b/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/ssv6006_priv.h
new file mode 100644
index 000000000..10cbf0973
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/ssv6006_priv.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV6006_PRIV_H_
+#define _SSV6006_PRIV_H_
+#include <smac/ssv_rc_minstrel.h>
+#define COMMON_FOR_SMAC
+#define REG32(_addr) REG32_R(_addr)
+#define REG32_W(_addr,_value) do { SMAC_REG_WRITE(sh, _addr, _value); } while (0)
+static void inline print_null(const char *fmt, ...)
+{
+}
+#define MSLEEP(_val) msleep(_val)
+#define MDELAY(_val) mdelay(_val)
+#define UDELAY(_val) udelay(_val)
+#define PRINT printk
+#define PRINT_ERR printk
+#define PRINT_INFO printk
+void ssv_attach_ssv6006_common(struct ssv_hal_ops *hal_ops);
+void ssv_attach_ssv6051_phy(struct ssv_hal_ops *hal_ops);
+void ssv_attach_ssv6051_cabrioA_BBRF(struct ssv_hal_ops *hal_ops);
+void ssv_attach_ssv6006_phy(struct ssv_hal_ops *hal_ops);
+void ssv_attach_ssv6006c_phy(struct ssv_hal_ops *hal_ops);
+void ssv_attach_ssv6006c_mac(struct ssv_hal_ops *hal_ops);
+void ssv_attach_ssv6006_mac(struct ssv_hal_ops *hal_ops);
+void ssv_attach_ssv6006_cabrioA_BBRF(struct ssv_hal_ops *hal_ops);
+void ssv_attach_ssv6006_geminiA_BBRF(struct ssv_hal_ops *hal_ops);
+void ssv_attach_ssv6006_turismoA_BBRF(struct ssv_hal_ops *hal_ops);
+void ssv_attach_ssv6006_turismoB_BBRF(struct ssv_hal_ops *hal_ops);
+void ssv_attach_ssv6006_turismoC_BBRF(struct ssv_hal_ops *hal_ops);
+bool ssv6006_rc_get_previous_ampdu_rpt(struct ssv_minstrel_ht_sta *mhs, int pkt_no, int *rpt_idx);
+void ssv6006_rc_add_ampdu_rpt_to_list(struct ssv_softc *sc, struct ssv_minstrel_ht_sta *mhs, void *rate_rpt,
+                                      int pkt_no, int ampdu_len, int ampdu_ack_len);
+int ssv6006_get_pa_band(int ch);
+void ssv6006c_reset_mib_mac(struct ssv_hw *sh);
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/ssv6006_priv_normal.h b/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/ssv6006_priv_normal.h
new file mode 100644
index 000000000..1ca2f34a1
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/ssv6006_priv_normal.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV6006_PRIV_MAC_H_
+#define _SSV6006_PRIV_MAC_H_
+#define REG32_R(_addr) ({ u32 reg; SMAC_REG_READ(sh, _addr, &reg); reg;})
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/ssv6006_priv_safe.h b/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/ssv6006_priv_safe.h
new file mode 100644
index 000000000..08f66105d
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/ssv6006_priv_safe.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV6006_PRIV_RF_H_
+#define _SSV6006_PRIV_RF_H_
+#define REG32_R(_addr) ({ u32 reg; SMAC_REG_SAFE_READ(sh, _addr, &reg); reg;})
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/ssv6006_turismoC.c b/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/ssv6006_turismoC.c
new file mode 100644
index 000000000..39cd81170
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/ssv6006_turismoC.c
@@ -0,0 +1,2759 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/version.h>
+#if ((defined SSV_SUPPORT_HAL) && (defined SSV_SUPPORT_SSV6006))
+#include <linux/nl80211.h>
+#include <ssv6200.h>
+#include "ssv6006C_reg.h"
+#include "ssv6006C_aux.h"
+#include <smac/dev.h>
+#include <smac/efuse.h>
+#include <smac/ssv_skb.h>
+#include <hal.h>
+#include <ssvdevice/ssv_cmd.h>
+#include "ssv6006_mac.h"
+#include "ssv6006_priv.h"
+#include "ssv6006_priv_safe.h"
+#include "turismoC_rf_reg.c"
+#include "turismoC_wifi_phy_reg.c"
+#include "turismo_common.h"
+#include "turismo_common.c"
+#include <ssv6xxx_common.h>
+#include <linux_80211.h>
+static void ssv6006_turismoC_init_iqk (struct ssv_hw *sh, struct ssv6006_cal_result *cal);
+static void ssv6006_turismoC_init_cali (struct ssv_hw *sh, struct ssv6006_cal_result *cal);
+static bool ssv6006_turismoC_set_rf_enable(struct ssv_hw *sh, bool val);
+static void _set_tx_pwr(struct ssv_softc *sc, u32 pa_band, u32 txpwr);
+static const size_t ssv6006_turismoC_phy_tbl_size = sizeof(ssv6006_turismoC_phy_setting);
+static void ssv6006_turismoC_load_phy_table(ssv_cabrio_reg **phy_table)
+{
+    *phy_table = ssv6006_turismoC_phy_setting;
+}
+static u32 ssv6006_turismoC_get_phy_table_size(struct ssv_hw *sh)
+{
+    return(u32) ssv6006_turismoC_phy_tbl_size;
+}
+static const size_t ssv6006_turismoC_rf_tbl_size = sizeof(ssv6006_turismoC_rf_setting);
+static void ssv6006_turismoC_load_rf_table(ssv_cabrio_reg **rf_table)
+{
+    *rf_table = ssv6006_turismoC_rf_setting;
+}
+static u32 ssv6006_turismoC_get_rf_table_size(struct ssv_hw *sh)
+{
+    return (u32) ssv6006_turismoC_rf_tbl_size;
+}
+#define USE_COMMON_MACRO
+static void _restore_cal (struct ssv_hw *sh)
+{
+    int i, wifi_dc_addr;
+    dev_dbg(sh->sc->dev, "Restore calibration result");
+    for (i = 0; i < 21; i++) {
+        wifi_dc_addr = ADR_WF_DCOC_IDAC_REGISTER1+ (i << 2);
+        REG32_W(wifi_dc_addr, sh->cal.rxdc_2g[i]);
+        wifi_dc_addr = (ADR_5G_DCOC_IDAC_REGISTER1)+ (i << 2);
+        REG32_W(wifi_dc_addr, sh->cal.rxdc_5g[i]);
+    }
+    SET_RG_WF_RX_ABBCTUNE(sh->cal.rxrc_bw20);
+    SET_RG_WF_N_RX_ABBCTUNE(sh->cal.rxrc_bw40);
+    SET_RG_WF_TX_DAC_IOFFSET(sh->cal.txdc_i_2g);
+    SET_RG_WF_TX_DAC_QOFFSET(sh->cal.txdc_q_2g);
+    SET_RG_TX_IQ_2500_ALPHA(sh->cal.txiq_alpha[BAND_2G]);
+    SET_RG_TX_IQ_2500_THETA(sh->cal.txiq_theta[BAND_2G]);
+    SET_RG_RX_IQ_2500_ALPHA(sh->cal.rxiq_alpha[BAND_2G]);
+    SET_RG_RX_IQ_2500_THETA(sh->cal.rxiq_theta[BAND_2G]);
+    if (sh->cfg.hw_caps & SSV6200_HW_CAP_5GHZ) {
+        for (i = 0; i < 21; i++) {
+            wifi_dc_addr = (ADR_5G_DCOC_IDAC_REGISTER1)+ (i << 2);
+            REG32_W(wifi_dc_addr, sh->cal.rxdc_5g[i]);
+        }
+        SET_RG_5G_TX_DAC_IOFFSET(sh->cal.txdc_i_5g);
+        SET_RG_5G_TX_DAC_QOFFSET(sh->cal.txdc_q_5g);
+        SET_RG_TX_IQ_5100_ALPHA(sh->cal.txiq_alpha[BAND_5100]);
+        SET_RG_TX_IQ_5100_THETA(sh->cal.txiq_theta[BAND_5100]);
+        SET_RG_TX_IQ_5500_ALPHA(sh->cal.txiq_alpha[BAND_5500]);
+        SET_RG_TX_IQ_5500_THETA(sh->cal.txiq_theta[BAND_5500]);
+        SET_RG_TX_IQ_5700_ALPHA(sh->cal.txiq_alpha[BAND_5700]);
+        SET_RG_TX_IQ_5700_THETA(sh->cal.txiq_theta[BAND_5700]);
+        SET_RG_TX_IQ_5900_ALPHA(sh->cal.txiq_alpha[BAND_5900]);
+        SET_RG_TX_IQ_5900_THETA(sh->cal.txiq_theta[BAND_5900]);
+        SET_RG_RX_IQ_5100_ALPHA(sh->cal.rxiq_alpha[BAND_5100]);
+        SET_RG_RX_IQ_5100_THETA(sh->cal.rxiq_theta[BAND_5100]);
+        SET_RG_RX_IQ_5500_ALPHA(sh->cal.rxiq_alpha[BAND_5500]);
+        SET_RG_RX_IQ_5500_THETA(sh->cal.rxiq_theta[BAND_5500]);
+        SET_RG_RX_IQ_5700_ALPHA(sh->cal.rxiq_alpha[BAND_5700]);
+        SET_RG_RX_IQ_5700_THETA(sh->cal.rxiq_theta[BAND_5700]);
+        SET_RG_RX_IQ_5900_ALPHA(sh->cal.rxiq_alpha[BAND_5900]);
+        SET_RG_RX_IQ_5900_THETA(sh->cal.rxiq_theta[BAND_5900]);
+    }
+}
+static void ssv6006_turismoC_init_PLL(struct ssv_hw *sh)
+{
+#ifdef USE_COMMON_MACRO
+    TU_INIT_TURISMOC_PLL;
+#else
+    u32 regval, count = 0;
+    SET_RG_LOAD_RFTABLE_RDY(0x1);
+    do {
+        MSLEEP(1);
+        regval = REG32_R(ADR_PMU_STATE_REG);
+        count ++ ;
+        if (regval == 0x13)
+            break;
+        if (count > 100) {
+            dev_dbg(sh->sc->dev, " PLL initial fails ");
+            break;
+        }
+    } while (1);
+    MSLEEP(1);
+    REG32_W(ADR_WIFI_PHY_COMMON_SYS_REG, 0x80010000);
+    REG32_W(ADR_CLOCK_SELECTION, 0x00000008);
+    MSLEEP(1);
+#endif
+}
+#ifndef USE_COMMON_MACRO
+static void _set_ht20_g_resp_rate(struct ssv_hw *sh)
+{
+    SET_MTX_RESPFRM_RATE_90_B0(0x9090);
+    SET_MTX_RESPFRM_RATE_91_B1(0x9090);
+    SET_MTX_RESPFRM_RATE_92_B2(0x9090);
+    SET_MTX_RESPFRM_RATE_93_B3(0x9292);
+    SET_MTX_RESPFRM_RATE_94_B4(0x9292);
+    SET_MTX_RESPFRM_RATE_95_B5(0x9494);
+    SET_MTX_RESPFRM_RATE_96_B6(0x9494);
+    SET_MTX_RESPFRM_RATE_97_B7(0x9494);
+}
+static void _set_ht40_g_resp_rate(struct ssv_hw *sh)
+{
+    SET_MTX_RESPFRM_RATE_90_B0(0xB0B0);
+    SET_MTX_RESPFRM_RATE_91_B1(0xB0B0);
+    SET_MTX_RESPFRM_RATE_92_B2(0xB0B0);
+    SET_MTX_RESPFRM_RATE_93_B3(0xB2B2);
+    SET_MTX_RESPFRM_RATE_94_B4(0xB2B2);
+    SET_MTX_RESPFRM_RATE_95_B5(0xB4B4);
+    SET_MTX_RESPFRM_RATE_96_B6(0xB4B4);
+    SET_MTX_RESPFRM_RATE_97_B7(0xB4B4);
+}
+static void _set_turismoC_BW(struct ssv_hw *sh, enum nl80211_channel_type channel_type)
+{
+#ifdef USE_COMMON_MACRO
+    TU_SET_TURISMOC_BW(channel_type);
+#else
+    switch (channel_type) {
+    case NL80211_CHAN_HT20:
+    case NL80211_CHAN_NO_HT:
+        SET_MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_SECONDARY(1);
+        SET_REG(ADR_WIFI_PHY_COMMON_SYS_REG,
+                (0 << RG_PRIMARY_CH_SIDE_SFT) | (0 << RG_SYSTEM_BW_SFT), 0,
+                (RG_PRIMARY_CH_SIDE_I_MSK & RG_SYSTEM_BW_I_MSK));
+        SET_REG(ADR_DIGITAL_ADD_ON_0,
+                (0 << RG_40M_MODE_SFT) | (0 << RG_LO_UP_CH_SFT), 0,
+                (RG_40M_MODE_I_MSK & RG_LO_UP_CH_I_MSK));
+        _set_ht20_g_resp_rate(sh);
+        break;
+    case NL80211_CHAN_HT40MINUS:
+        SET_MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_SECONDARY(0);
+        SET_REG(ADR_WIFI_PHY_COMMON_SYS_REG,
+                (1 << RG_PRIMARY_CH_SIDE_SFT) | (1 << RG_SYSTEM_BW_SFT), 0,
+                (RG_PRIMARY_CH_SIDE_I_MSK & RG_SYSTEM_BW_I_MSK));
+        SET_REG(ADR_DIGITAL_ADD_ON_0,
+                (1 << RG_40M_MODE_SFT) | (0 << RG_LO_UP_CH_SFT), 0,
+                (RG_40M_MODE_I_MSK & RG_LO_UP_CH_I_MSK));
+        _set_ht40_g_resp_rate(sh);
+        break;
+    case NL80211_CHAN_HT40PLUS:
+        SET_MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_SECONDARY(0);
+        SET_REG(ADR_WIFI_PHY_COMMON_SYS_REG,
+                (0 << RG_PRIMARY_CH_SIDE_SFT) | (1 << RG_SYSTEM_BW_SFT), 0,
+                (RG_PRIMARY_CH_SIDE_I_MSK & RG_SYSTEM_BW_I_MSK));
+        SET_REG(ADR_DIGITAL_ADD_ON_0,
+                (1 << RG_40M_MODE_SFT) | (1 << RG_LO_UP_CH_SFT), 0,
+                (RG_40M_MODE_I_MSK & RG_LO_UP_CH_I_MSK));
+        _set_ht40_g_resp_rate(sh);
+        break;
+    default:
+        break;
+    }
+#endif
+}
+static void _set_2g_channel(struct ssv_hw *sh, int ch)
+{
+#ifdef USE_COMMON_MACRO
+    TURISMOC_SET_2G_CHANNEL(ch);
+#else
+    int regval;
+    SET_RG_RF_5G_BAND(0);
+    SET_RG_MODE_MANUAL(1);
+    SET_RG_SX_RFCH_MAP_EN(1);
+    regval = GET_RG_SX_CHANNEL;
+    if (regval == ch) {
+        if (ch != 1)
+            SET_RG_SX_CHANNEL(1);
+        else
+            SET_RG_SX_CHANNEL(11);
+    }
+    UDELAY(100);
+    SET_RG_SX_CHANNEL(ch);
+    SET_RG_MODE(0);
+    SET_RG_MODE(3);
+    SET_RG_MODE_MANUAL(0);
+    SET_RG_SOFT_RST_N_11GN_RX(1);
+    SET_RG_SOFT_RST_N_11B_RX(1);
+#endif
+}
+static void _set_5g_channel(struct ssv_hw *sh, int ch)
+{
+#ifdef USE_COMMON_MACRO
+    TURISMOC_SET_5G_CHANNEL(ch);
+#else
+    int regval;
+    SET_RG_RF_5G_BAND(1);
+    SET_RG_MODE_MANUAL(1);
+    SET_RG_SX5GB_RFCH_MAP_EN(1);
+    regval = GET_RG_SX5GB_CHANNEL;
+    if (regval == ch) {
+        if (ch != 36)
+            SET_RG_SX5GB_CHANNEL(36);
+        else
+            SET_RG_SX5GB_CHANNEL(40);
+    }
+    UDELAY(100);
+    SET_RG_SX5GB_CHANNEL(ch);
+    SET_RG_MODE(0);
+    SET_RG_MODE(7);
+    SET_RG_MODE_MANUAL(0);
+    SET_RG_SOFT_RST_N_11GN_RX(1);
+#endif
+}
+static void _turismoC_pre_cal(struct ssv_hw *sh)
+{
+    SET_RG_MODE(MODE_STANDBY);
+    SET_RG_MODE_MANUAL(1);
+    SET_RG_MODE(MODE_CALIBRATION);
+}
+static void _turismoC_post_cal(struct ssv_hw *sh)
+{
+    SET_RG_MODE(MODE_STANDBY);
+    SET_RG_MODE_MANUAL(0);
+}
+static void _turismoC_inter_cal(struct ssv_hw *sh)
+{
+    SET_RG_MODE(MODE_STANDBY);
+    UDELAY(100);
+    SET_RG_MODE(MODE_CALIBRATION);
+}
+static void _debug__2p4g_rxdc_cal(struct ssv_hw *sh)
+{
+    int i = 0, j ;
+    int rg_rfg, rg_pgag;
+    int adc_out_sum_i, adc_out_sumQ;
+    SET_RG_RX_GAIN_MANUAL(1);
+    for(i = 1; i >= 0; i--) {
+        for(j = 15; j >= 0; j--) {
+            rg_rfg = i;
+            rg_pgag = j;
+            SET_RG_RFG(rg_rfg);
+            SET_RG_PGAG(rg_pgag);
+            adc_out_sum_i = GET_RO_DC_CAL_I;
+            if (adc_out_sum_i>63) {
+                adc_out_sum_i -= 128;
+            }
+            adc_out_sumQ = GET_RO_DC_CAL_Q;
+            if(adc_out_sumQ>63) {
+                adc_out_sumQ -= 128;
+            }
+            dev_dbg(sh->sc->dev, "lna gain is %d, pga gain is %d, ADC_OUT_I is %d, ADC_OUT_Q is %d",
+                  rg_rfg, rg_pgag, adc_out_sum_i, adc_out_sumQ);
+        }
+        dev_dbg(sh->sc->dev, "------------------------------------------------------------");
+    }
+    SET_RG_RX_GAIN_MANUAL(0);
+}
+static void _turismoC_2p4g_rxdc_cal(struct ssv_hw *sh)
+{
+    int i = 0;
+    u32 wifi_dc_addr;
+    SET_REG(ADR_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE,
+            (0x6 << RG_SX_CHANNEL_SFT) | (0x1 << RG_SX_RFCH_MAP_EN_SFT), 0,
+            (RG_SX_CHANNEL_I_MSK & RG_SX_RFCH_MAP_EN_I_MSK));
+    SET_RG_CAL_INDEX(CAL_IDX_WIFI2P4G_RXDC);
+    UDELAY(100);
+    while (GET_RO_WF_DCCAL_DONE == 0) {
+        i ++;
+        if (i >10000) {
+            dev_err(sh->sc->dev, "%s: 5G RXDC cal failed",__func__);
+            break;
+        }
+        UDELAY(1);
+    }
+    dev_dbg(sh->sc->dev, "--------------------------------------------%d",i);
+    dev_dbg(sh->sc->dev, "--------- 2.4 G Rx DC Calibration result----------------");
+    for (i = 0; i < 21; i++) {
+        wifi_dc_addr = (ADR_WF_DCOC_IDAC_REGISTER1)+ (i << 2);
+        sh->cal.rxdc_2g[i] = REG32_R(wifi_dc_addr);
+        dev_dbg(sh->sc->dev, "addr %x : val %x, ", wifi_dc_addr, sh->cal.rxdc_2g[i]);
+    }
+    _debug__2p4g_rxdc_cal(sh);
+    SET_RG_CAL_INDEX(CAL_IDX_NONE);
+}
+static void _debug_5g_rxdc_cal(struct ssv_hw *sh)
+{
+    int i = 0, j;
+    int rg_rfg, rg_pgag;
+    int adc_out_sum_i, adc_out_sumQ;
+    SET_RG_RX_GAIN_MANUAL(1);
+    for(i = 1; i >= 0; i--) {
+        for(j = 15; j >= 0; j--) {
+            rg_rfg = i;
+            rg_pgag = j;
+            SET_RG_RFG(rg_rfg);
+            SET_RG_PGAG(rg_pgag);
+            adc_out_sum_i = GET_RO_DC_CAL_I;
+            if (adc_out_sum_i>63) {
+                adc_out_sum_i -= 128;
+            }
+            adc_out_sumQ = GET_RO_DC_CAL_Q;
+            if(adc_out_sumQ>63) {
+                adc_out_sumQ -= 128;
+            }
+            dev_dbg(sh->sc->dev, "lna gain is %d, pga gain is %d, ADC_OUT_I is %d, ADC_OUT_Q is %d",
+                  rg_rfg, rg_pgag, adc_out_sum_i, adc_out_sumQ);
+        }
+        dev_dbg(sh->sc->dev, "------------------------------------------------------------");
+    }
+    SET_RG_RX_GAIN_MANUAL(0);
+}
+static void _turismoC_5g_rxdc_cal(struct ssv_hw *sh)
+{
+    int i = 0;
+    u32 wifi_dc_addr;
+    SET_REG(ADR_SX_5GB_REGISTER_INT3BIT___CH_TABLE,
+            (100 << RG_SX5GB_CHANNEL_SFT) | (0x1 << RG_SX5GB_RFCH_MAP_EN_SFT), 0,
+            (RG_SX5GB_CHANNEL_I_MSK & RG_SX5GB_RFCH_MAP_EN_I_MSK));
+    SET_RG_CAL_INDEX(CAL_IDX_WIFI5G_RXDC);
+    UDELAY(100);
+    while (GET_RO_5G_DCCAL_DONE == 0) {
+        i ++;
+        if (i >100000) {
+            dev_err(sh->sc->dev, "%s: 5G RXDC cal failed",__func__);
+            break;
+        }
+        UDELAY(1);
+    }
+    dev_dbg(sh->sc->dev, "--------------------------------------------%d",i);
+    dev_dbg(sh->sc->dev, "--------- 5 G Rx DC Calibration result----------------");
+    for (i = 0; i < 21; i++) {
+        wifi_dc_addr = (ADR_5G_DCOC_IDAC_REGISTER1)+ (i << 2);
+        sh->cal.rxdc_5g[i] = REG32_R(wifi_dc_addr);
+        dev_dbg(sh->sc->dev, "addr %x : val %x, ", wifi_dc_addr,sh->cal.rxdc_5g[i]);
+    }
+    _debug_5g_rxdc_cal(sh);
+    SET_RG_CAL_INDEX(CAL_IDX_NONE);
+}
+static void _turismoC_bw20_rxrc_cal(struct ssv_hw *sh)
+{
+    int count = 0;
+    dev_dbg(sh->sc->dev, "--------------------------------------------");
+    dev_dbg(sh->sc->dev, "Before WiFi BW20 RG_WF_RX_ABBCTUNE: %d", GET_RG_WF_RX_ABBCTUNE);
+    SET_RG_RX_RCCAL_DELAY(2);
+    SET_RG_PHASE_17P5M(0x20d0);
+    SET_REG(ADR_RF_D_CAL_TOP_6,
+            (0x22c << RG_RX_RCCAL_TARG_SFT) | (0 << RG_RCCAL_POLAR_INV_SFT), 0,
+            (RG_RX_RCCAL_TARG_I_MSK & RG_RCCAL_POLAR_INV_I_MSK));
+    SET_RG_ALPHA_SEL(2);
+    SET_RG_PGAG_RCCAL(3);
+    SET_RG_TONE_SCALE(0x80);
+    SET_RG_CAL_INDEX(CAL_IDX_BW20_RXRC);
+    UDELAY(250);
+    while (GET_RO_RCCAL_DONE == 0) {
+        count ++;
+        if (count > 100000) {
+            dev_err(sh->sc->dev, "%s: bw20 RXRC cal failed",__func__);
+            break;
+        }
+        UDELAY(1);
+    }
+    dev_dbg(sh->sc->dev, "--------------------------------------------%d", count);
+    sh->cal.rxrc_bw20 = GET_RG_WF_RX_ABBCTUNE;
+    dev_dbg(sh->sc->dev, "WiFi BW20 RG_WF_RX_ABBCTUNE CAL RESULT: %d", sh->cal.rxrc_bw20);
+    SET_RG_CAL_INDEX(CAL_IDX_NONE);
+}
+static void _turismoC_bw40_rxrc_cal(struct ssv_hw *sh)
+{
+    int count = 0;
+    dev_dbg(sh->sc->dev, "--------------------------------------------");
+    dev_dbg(sh->sc->dev, "Before WiFi BW40 RG_WF_RX_N_ABBCTUNE: %d", GET_RG_WF_N_RX_ABBCTUNE);
+    SET_RG_RX_N_RCCAL_DELAY(2);
+    SET_RG_PHASE_35M(0x3fff);
+    SET_REG(ADR_RF_D_CAL_TOP_6,
+            (0x213 << RG_RX_RCCAL_40M_TARG_SFT) | (0 << RG_RCCAL_POLAR_INV_SFT), 0,
+            (RG_RX_RCCAL_40M_TARG_I_MSK & RG_RCCAL_POLAR_INV_I_MSK));
+    SET_RG_ALPHA_SEL(2);
+    SET_RG_PGAG_RCCAL(3);
+    SET_RG_TONE_SCALE(0x80);
+    SET_RG_CAL_INDEX(CAL_IDX_BW40_RXRC);
+    UDELAY(250);
+    while (GET_RO_RCCAL_DONE == 0) {
+        count ++;
+        if (count > 100000) {
+            dev_err(sh->sc->dev, "%s: BW40 RXRC cal failed",__func__);
+            break;
+        }
+        UDELAY(1);
+    }
+    dev_dbg(sh->sc->dev, "--------------------------------------------%d", count);
+    sh->cal.rxrc_bw40 = GET_RG_WF_N_RX_ABBCTUNE;
+    dev_dbg(sh->sc->dev, "WiFi BW40 RG_WF_N_RX_ABBCTUNE CAL RESULT: %d", sh->cal.rxrc_bw40);
+    SET_RG_CAL_INDEX(CAL_IDX_NONE);
+}
+static void _turismoC_txdc_cal(struct ssv_hw *sh)
+{
+    int count = 0;
+    SET_REG(ADR_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE,
+            (0x6 << RG_SX_CHANNEL_SFT) | (0x1 << RG_SX_RFCH_MAP_EN_SFT), 0,
+            (RG_SX_CHANNEL_I_MSK & RG_SX_RFCH_MAP_EN_I_MSK));
+    dev_dbg(sh->sc->dev, "--------------------------------------------");
+    dev_dbg(sh->sc->dev, "Before txdc calibration WiFi 2P4G Tx DAC IOFFSET: %d, QOFFSET %d",
+          GET_RG_WF_TX_DAC_IOFFSET, GET_RG_WF_TX_DAC_QOFFSET);
+    SET_RG_TXGAIN_PHYCTRL(1);
+    SET_REG(ADR_CALIBRATION_GAIN_REGISTER0,
+            (0x6 << RG_TX_GAIN_TXCAL_SFT) | (0x3 << RG_PGAG_TXCAL_SFT), 0,
+            (RG_TX_GAIN_TXCAL_I_MSK & RG_PGAG_TXCAL_I_MSK));
+    SET_RG_TONE_SCALE(0x80);
+    SET_RG_PRE_DC_AUTO(1);
+    SET_RG_TX_IQCAL_TIME(1);
+    SET_RG_PHASE_1M(0x0ccc);
+    SET_RG_PHASE_RXIQ_1M(0x0ccc);
+    SET_RG_ALPHA_SEL(2);
+    SET_RG_CAL_INDEX(CAL_IDX_WIFI2P4G_TXLO);
+    UDELAY(250);
+    while (GET_RO_TXDC_DONE == 0) {
+        count ++;
+        if (count > 100000) {
+            dev_err(sh->sc->dev, "%s: 2.4G TXDC cal failed",__func__);
+            break;
+        }
+        UDELAY(1);
+    }
+    dev_dbg(sh->sc->dev, "--------------------------------------------%d", count);
+    sh->cal.txdc_i_2g = GET_RG_WF_TX_DAC_IOFFSET;
+    sh->cal.txdc_q_2g = GET_RG_WF_TX_DAC_QOFFSET;
+    dev_dbg(sh->sc->dev, "After txdc calibration WiFi 2P4G Tx DAC IOFFSET: %d, QOFFSET %d",
+          sh->cal.txdc_i_2g, sh->cal.txdc_q_2g);
+    SET_RG_CAL_INDEX(CAL_IDX_NONE);
+}
+static void _turismoC_txiq_cal(struct ssv_hw *sh)
+{
+    int count = 0;
+    SET_REG(ADR_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE,
+            (0x6 << RG_SX_CHANNEL_SFT) | (0x1 << RG_SX_RFCH_MAP_EN_SFT), 0,
+            (RG_SX_CHANNEL_I_MSK & RG_SX_RFCH_MAP_EN_I_MSK));
+    dev_dbg(sh->sc->dev, "--------------------------------------------");
+    dev_dbg(sh->sc->dev, "before tx iq 2.4G calibration, tx alpha: %d, tx theta %d",
+          GET_RG_TX_IQ_2500_ALPHA, GET_RG_TX_IQ_2500_THETA);
+    SET_RG_TXGAIN_PHYCTRL(1);
+    SET_REG(ADR_CALIBRATION_GAIN_REGISTER0,
+            (0x6 << RG_TX_GAIN_TXCAL_SFT) | (0x3 << RG_PGAG_TXCAL_SFT), 0,
+            (RG_TX_GAIN_TXCAL_I_MSK & RG_PGAG_TXCAL_I_MSK));
+    SET_RG_TONE_SCALE(0x80);
+    SET_RG_PRE_DC_AUTO(1);
+    SET_RG_TX_IQCAL_TIME(1);
+    SET_RG_PHASE_1M(0xccc);
+    SET_RG_PHASE_RXIQ_1M(0xccc);
+    SET_RG_ALPHA_SEL(2);
+    SET_RG_CAL_INDEX(CAL_IDX_WIFI2P4G_TXIQ);
+    UDELAY(250);
+    while (GET_RO_TXIQ_DONE == 0) {
+        count ++;
+        if (count > 100000) {
+            dev_err(sh->sc->dev, "%s: 2.4G TXIQ cal failed",__func__);
+            break;
+        }
+        UDELAY(1);
+    }
+    dev_dbg(sh->sc->dev, "--------------------------------------------%d", count);
+    sh->cal.txiq_alpha[BAND_2G] = GET_RG_TX_IQ_2500_ALPHA;
+    sh->cal.txiq_theta[BAND_2G] = GET_RG_TX_IQ_2500_THETA;
+    dev_dbg(sh->sc->dev, "After tx iq calibration, tx alpha: %d, tx theta %d",
+          sh->cal.txiq_alpha[BAND_2G], sh->cal.txiq_theta[BAND_2G]);
+    SET_RG_CAL_INDEX(CAL_IDX_NONE);
+}
+static void _debug_rxiq_cal(struct ssv_hw *sh)
+{
+    u32 regval, regval1;
+    SET_RG_SPECTRUM_EN(1);
+    SET_REG(ADR_RF_D_CAL_TOP_7,
+            (0x1 << RG_SPECTRUM_PWR_UPDATE_SFT) | (0x1 << RG_SPECTRUM_LO_FIX_SFT), 0,
+            (RG_SPECTRUM_PWR_UPDATE_I_MSK & RG_SPECTRUM_LO_FIX_I_MSK));
+    MDELAY(10);
+    SET_REG(ADR_RF_D_CAL_TOP_7,
+            (0x0 << RG_SPECTRUM_PWR_UPDATE_SFT) | (0x1 << RG_SPECTRUM_LO_FIX_SFT), 0,
+            (RG_SPECTRUM_PWR_UPDATE_I_MSK & RG_SPECTRUM_LO_FIX_I_MSK));
+    regval1 = GET_RG_SPECTRUM_PWR_UPDATE;
+    regval = GET_RO_SPECTRUM_IQ_PWR_31_0;
+    dev_dbg(sh->sc->dev, "The spectrum power is 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x",
+          ((regval1 >> 4) & 0xf), (regval1 & 0xf), ((regval >> 28) & 0xf), ((regval >> 24) & 0xf),
+          ((regval >> 20) & 0xf), ((regval >> 16) & 0xf), ((regval >> 12) & 0xf), ((regval >> 8) & 0xf),
+          ((regval >> 4) & 0xf), (regval & 0xf));
+    SET_RG_PHASE_STEP_VALUE(0xF334);
+    SET_RG_SPECTRUM_EN(1);
+    SET_REG(ADR_RF_D_CAL_TOP_7,
+            (0x1 << RG_SPECTRUM_PWR_UPDATE_SFT) | (0x1 << RG_SPECTRUM_LO_FIX_SFT), 0,
+            (RG_SPECTRUM_PWR_UPDATE_I_MSK & RG_SPECTRUM_LO_FIX_I_MSK));
+    MDELAY(10);
+    SET_REG(ADR_RF_D_CAL_TOP_7,
+            (0x0 << RG_SPECTRUM_PWR_UPDATE_SFT) | (0x1 << RG_SPECTRUM_LO_FIX_SFT), 0,
+            (RG_SPECTRUM_PWR_UPDATE_I_MSK & RG_SPECTRUM_LO_FIX_I_MSK));
+    regval1 = GET_RG_SPECTRUM_PWR_UPDATE;
+    regval = GET_RO_SPECTRUM_IQ_PWR_31_0;
+    dev_dbg(sh->sc->dev, "The spectrum power is 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x",
+          ((regval1 >> 4) & 0xf), (regval1 & 0xf), ((regval >> 28) & 0xf), ((regval >> 24) & 0xf),
+          ((regval >> 20) & 0xf), ((regval >> 16) & 0xf), ((regval >> 12) & 0xf), ((regval >> 8) & 0xf),
+          ((regval >> 4) & 0xf), (regval & 0xf));
+    SET_RG_SPECTRUM_EN(0);
+}
+static void _turismoC_rxiq_cal(struct ssv_hw *sh)
+{
+    int count = 0;
+    SET_REG(ADR_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE,
+            (0x6 << RG_SX_CHANNEL_SFT) | (0x1 << RG_SX_RFCH_MAP_EN_SFT), 0,
+            (RG_SX_CHANNEL_I_MSK & RG_SX_RFCH_MAP_EN_I_MSK));
+    dev_dbg(sh->sc->dev, "--------------------------------------------");
+    dev_dbg(sh->sc->dev, "Before rx iq calibration, rx alpha: %d, rx theta %d",
+          GET_RG_RX_IQ_2500_ALPHA, GET_RG_RX_IQ_2500_THETA);
+    SET_RG_TXGAIN_PHYCTRL(1);
+    SET_RG_RFG_RXIQCAL(0x0);
+    SET_RG_PGAG_RXIQCAL(0x3);
+    SET_RG_TX_GAIN_RXIQCAL(0x6);
+    SET_RG_TONE_SCALE(0x80);
+    SET_RG_PRE_DC_AUTO(1);
+    SET_RG_TX_IQCAL_TIME(1);
+    SET_RG_PHASE_1M(0xccc);
+    SET_RG_PHASE_RXIQ_1M(0xccc);
+    SET_RG_ALPHA_SEL(2);
+    SET_RG_CAL_INDEX(CAL_IDX_WIFI2P4G_RXIQ);
+    UDELAY(250);
+    while (GET_RO_RXIQ_DONE == 0) {
+        count ++;
+        if (count > 100000) {
+            dev_err(sh->sc->dev, "%s: 2.4G RXIQ cal failed",__func__);
+            break;
+        }
+        UDELAY(1);
+    }
+    SET_RG_PHASE_STEP_VALUE(0xccc);
+    _debug_rxiq_cal(sh);
+    dev_dbg(sh->sc->dev, "--------------------------------------------%d", count);
+    sh->cal.rxiq_alpha[BAND_2G] = GET_RG_RX_IQ_2500_ALPHA;
+    sh->cal.rxiq_theta[BAND_2G] = GET_RG_RX_IQ_2500_THETA;
+    dev_dbg(sh->sc->dev, "After rx iq calibration, rx alpha: %d, rx theta %d",
+          sh->cal.rxiq_alpha[BAND_2G], sh->cal.rxiq_theta[BAND_2G]);
+    SET_RG_CAL_INDEX(CAL_IDX_NONE);
+}
+static void _turismoC_5g_txdc_cal(struct ssv_hw *sh)
+{
+    int count = 0;
+    SET_REG(ADR_SX_5GB_REGISTER_INT3BIT___CH_TABLE,
+            (100 << RG_SX5GB_CHANNEL_SFT) | (0x1 << RG_SX5GB_RFCH_MAP_EN_SFT), 0,
+            (RG_SX5GB_CHANNEL_I_MSK & RG_SX5GB_RFCH_MAP_EN_I_MSK));
+    dev_dbg(sh->sc->dev, "--------------------------------------------");
+    dev_dbg(sh->sc->dev, "Before 5G txdc calibration WiFi 5G Tx DAC IOFFSET: %d, QOFFSET %d",
+          GET_RG_5G_TX_DAC_IOFFSET, GET_RG_5G_TX_DAC_QOFFSET);
+    SET_RG_TXGAIN_PHYCTRL(1);
+    SET_RG_TONE_SCALE(0x80);
+    SET_REG(ADR_5G_CALIBRATION_TIMER_GAIN_REGISTER,
+            (0x2 << RG_5G_TX_GAIN_TXCAL_SFT) | (0x3 << RG_5G_PGAG_TXCAL_SFT), 0,
+            (RG_5G_TX_GAIN_TXCAL_I_MSK & RG_5G_PGAG_TXCAL_I_MSK));
+    SET_RG_PRE_DC_AUTO(1);
+    SET_RG_TX_IQCAL_TIME(1);
+    SET_RG_PHASE_1M(0xCCC);
+    SET_RG_PHASE_RXIQ_1M(0xCCC);
+    SET_RG_ALPHA_SEL(2);
+    SET_RG_CAL_INDEX(CAL_IDX_WIFI5G_TXLO);
+    UDELAY(250);
+    while (GET_RO_5G_TXDC_DONE == 0) {
+        count ++;
+        if (count >100000) {
+            dev_err(sh->sc->dev, "%s: 5G TXDC cal failed",__func__);
+            break;
+        }
+        UDELAY(1);
+    }
+    dev_dbg(sh->sc->dev, "--------------------------------------------%d", count);
+    sh->cal.txdc_i_5g = GET_RG_5G_TX_DAC_IOFFSET;
+    sh->cal.txdc_q_5g = GET_RG_5G_TX_DAC_QOFFSET;
+    dev_dbg(sh->sc->dev, "After 5G txdc calibration WiFi 5G Tx DAC IOFFSET: %d, QOFFSET %d",
+          sh->cal.txdc_i_5g, sh->cal.txdc_q_5g);
+    SET_RG_CAL_INDEX(CAL_IDX_NONE);
+}
+static void _turismoC_5g_txiq_cal(struct ssv_hw *sh)
+{
+    int count = 0;
+    int band;
+    SET_RG_SX5GB_RFCH_MAP_EN(1);
+    dev_dbg(sh->sc->dev, "--------------------------------------------");
+    dev_dbg(sh->sc->dev, "before 5G tx iq calibration, tx alpha: %d %d %d %d, tx theta %d %d %d %d",
+          GET_RG_TX_IQ_5100_ALPHA, GET_RG_TX_IQ_5500_ALPHA,
+          GET_RG_TX_IQ_5700_ALPHA, GET_RG_TX_IQ_5900_ALPHA,
+          GET_RG_TX_IQ_5100_THETA, GET_RG_TX_IQ_5500_THETA,
+          GET_RG_TX_IQ_5700_THETA, GET_RG_TX_IQ_5900_THETA);
+    SET_RG_TXGAIN_PHYCTRL(1);
+    SET_RG_TONE_SCALE(0x80);
+    SET_RG_5G_PGAG_TXCAL(0x3);
+    SET_RG_PRE_DC_AUTO(1);
+    SET_RG_TX_IQCAL_TIME(1);
+    SET_RG_PHASE_1M(0xccc);
+    SET_RG_PHASE_RXIQ_1M(0xccc);
+    SET_RG_ALPHA_SEL(2);
+    for (band = 0; band < 4; band ++) {
+        count = 0;
+        SET_RG_SX5GB_CHANNEL(cal_ch_5g[band]);
+        if( band == 2 ) {
+            SET_RG_5G_TX_GAIN_TXCAL(PAPDP_GAIN_SETTING_F2);
+        } else {
+            SET_RG_5G_TX_GAIN_TXCAL(PAPDP_GAIN_SETTING);
+        }
+        SET_RG_CAL_INDEX(CAL_IDX_WIFI5G_TXIQ);
+        UDELAY(250);
+        while (GET_RO_5G_TXIQ_DONE == 0) {
+            count ++;
+            if (count > 100000) {
+                dev_err(sh->sc->dev, "%s: 5G TXIQ band %d cal failed",__func__, band);
+                break;
+            }
+            UDELAY(1);
+        }
+        SET_RG_CAL_INDEX(CAL_IDX_NONE);
+    }
+    dev_dbg(sh->sc->dev, "--------------------------------------------%d", count);
+    sh->cal.txiq_alpha[BAND_5100] = GET_RG_TX_IQ_5100_ALPHA;
+    sh->cal.txiq_theta[BAND_5100] = GET_RG_TX_IQ_5100_THETA;
+    sh->cal.txiq_alpha[BAND_5500] = GET_RG_TX_IQ_5500_ALPHA;
+    sh->cal.txiq_theta[BAND_5500] = GET_RG_TX_IQ_5500_THETA;
+    sh->cal.txiq_alpha[BAND_5700] = GET_RG_TX_IQ_5700_ALPHA;
+    sh->cal.txiq_theta[BAND_5700] = GET_RG_TX_IQ_5700_THETA;
+    sh->cal.txiq_alpha[BAND_5900] = GET_RG_TX_IQ_5900_ALPHA;
+    sh->cal.txiq_theta[BAND_5900] = GET_RG_TX_IQ_5900_THETA;
+    dev_dbg(sh->sc->dev, "after 5G tx iq calibration, tx alpha: %d %d %d %d, tx theta %d %d %d %d",
+          sh->cal.txiq_alpha[BAND_5100], sh->cal.txiq_alpha[BAND_5500],
+          sh->cal.txiq_alpha[BAND_5700], sh->cal.txiq_alpha[BAND_5900],
+          sh->cal.txiq_theta[BAND_5100], sh->cal.txiq_theta[BAND_5500],
+          sh->cal.txiq_theta[BAND_5700], sh->cal.txiq_theta[BAND_5900]);
+}
+void _turismoC_5g_txiq_cal_band(struct ssv_hw *sh, int pa_band)
+{
+    int count = 0, alpha = 0, theta = 0;
+    SET_RG_SX5GB_RFCH_MAP_EN(1);
+    SET_RG_SX5GB_CHANNEL(cal_ch_5g[pa_band-1]);
+    if( pa_band == BAND_5700 ) {
+        SET_RG_5G_TX_GAIN_TXCAL(PAPDP_GAIN_SETTING_F2);
+    } else {
+        SET_RG_5G_TX_GAIN_TXCAL(PAPDP_GAIN_SETTING);
+    }
+    switch (pa_band) {
+    case BAND_5100:
+        alpha = GET_RG_TX_IQ_5100_ALPHA;
+        theta = GET_RG_TX_IQ_5100_THETA;
+        break;
+    case BAND_5500:
+        alpha = GET_RG_TX_IQ_5500_ALPHA;
+        theta = GET_RG_TX_IQ_5500_THETA;
+        break;
+    case BAND_5700:
+        alpha = GET_RG_TX_IQ_5700_ALPHA;
+        theta = GET_RG_TX_IQ_5700_THETA;
+        break;
+    case BAND_5900:
+        alpha = GET_RG_TX_IQ_5900_ALPHA;
+        theta = GET_RG_TX_IQ_5900_THETA;
+        break;
+    default:
+        break;
+    }
+    dev_dbg(sh->sc->dev, "--------------------------------------------");
+    dev_dbg(sh->sc->dev, "before 5G band %d tx iq calibration, tx alpha: %d, tx theta %d",
+          pa_band, alpha, theta);
+    SET_RG_TXGAIN_PHYCTRL(1);
+    SET_RG_TONE_SCALE(0x80);
+    SET_RG_5G_PGAG_TXCAL(0x3);
+    SET_RG_PRE_DC_AUTO(1);
+    SET_RG_TX_IQCAL_TIME(1);
+    SET_RG_PHASE_1M(0xccc);
+    SET_RG_PHASE_RXIQ_1M(0xccc);
+    SET_RG_ALPHA_SEL(2);
+    SET_RG_CAL_INDEX(CAL_IDX_WIFI5G_TXIQ);
+    UDELAY(250);
+    while (GET_RO_5G_TXIQ_DONE == 0) {
+        count ++;
+        if (count > 100000) {
+            dev_err(sh->sc->dev, "%s: 5G TXIQ band %d cal failed",__func__, pa_band);
+            break;
+        }
+        UDELAY(1);
+    }
+    SET_RG_CAL_INDEX(CAL_IDX_NONE);
+    switch (pa_band) {
+    case BAND_5100:
+        sh->cal.txiq_alpha[pa_band] = GET_RG_TX_IQ_5100_ALPHA;
+        sh->cal.txiq_theta[pa_band] = GET_RG_TX_IQ_5100_THETA;
+        break;
+    case BAND_5500:
+        sh->cal.txiq_alpha[pa_band] = GET_RG_TX_IQ_5500_ALPHA;
+        sh->cal.txiq_theta[pa_band] = GET_RG_TX_IQ_5500_THETA;
+        break;
+    case BAND_5700:
+        sh->cal.txiq_alpha[pa_band] = GET_RG_TX_IQ_5700_ALPHA;
+        sh->cal.txiq_theta[pa_band] = GET_RG_TX_IQ_5700_THETA;
+        break;
+    case BAND_5900:
+        sh->cal.txiq_alpha[pa_band] = GET_RG_TX_IQ_5900_ALPHA;
+        sh->cal.txiq_theta[pa_band] = GET_RG_TX_IQ_5900_THETA;
+        break;
+    default:
+        break;
+    }
+    dev_dbg(sh->sc->dev, "--------------------------------------------%d", count);
+    dev_dbg(sh->sc->dev, "after 5G band %d tx iq calibration, tx alpha: %d, tx theta %d",
+          pa_band, sh->cal.txiq_alpha[pa_band], sh->cal.txiq_theta[pa_band]);
+}
+static void _debug_5g_rxiq_cal(struct ssv_hw *sh)
+{
+    int regval, regval1;
+    SET_RG_SPECTRUM_EN(1);
+    SET_REG(ADR_RF_D_CAL_TOP_7,
+            (0x1 << RG_SPECTRUM_PWR_UPDATE_SFT) | (0x1 << RG_SPECTRUM_LO_FIX_SFT), 0,
+            (RG_SPECTRUM_PWR_UPDATE_I_MSK & RG_SPECTRUM_LO_FIX_I_MSK));
+    MDELAY(10);
+    SET_REG(ADR_RF_D_CAL_TOP_7,
+            (0x0 << RG_SPECTRUM_PWR_UPDATE_SFT) | (0x1 << RG_SPECTRUM_LO_FIX_SFT), 0,
+            (RG_SPECTRUM_PWR_UPDATE_I_MSK & RG_SPECTRUM_LO_FIX_I_MSK));
+    regval1 = GET_RG_SPECTRUM_PWR_UPDATE;
+    regval = GET_RO_SPECTRUM_IQ_PWR_31_0;
+    dev_dbg(sh->sc->dev, "The spectrum power is 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x",
+          ((regval1 >> 4) & 0xf), (regval1 & 0xf), ((regval >> 28) & 0xf), ((regval >> 24) & 0xf),
+          ((regval >> 20) & 0xf), ((regval >> 16) & 0xf), ((regval >> 12) & 0xf), ((regval >> 8) & 0xf),
+          ((regval >> 4) & 0xf), (regval & 0xf));
+    SET_RG_PHASE_STEP_VALUE(0xF334);
+    SET_RG_SPECTRUM_EN(1);
+    SET_REG(ADR_RF_D_CAL_TOP_7,
+            (0x1 << RG_SPECTRUM_PWR_UPDATE_SFT) | (0x1 << RG_SPECTRUM_LO_FIX_SFT), 0,
+            (RG_SPECTRUM_PWR_UPDATE_I_MSK & RG_SPECTRUM_LO_FIX_I_MSK));
+    MDELAY(10);
+    SET_REG(ADR_RF_D_CAL_TOP_7,
+            (0x0 << RG_SPECTRUM_PWR_UPDATE_SFT) | (0x1 << RG_SPECTRUM_LO_FIX_SFT), 0,
+            (RG_SPECTRUM_PWR_UPDATE_I_MSK & RG_SPECTRUM_LO_FIX_I_MSK));
+    regval1 = GET_RG_SPECTRUM_PWR_UPDATE;
+    regval = GET_RO_SPECTRUM_IQ_PWR_31_0;
+    dev_dbg(sh->sc->dev, "The spectrum power is 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x",
+          ((regval1 >> 4) & 0xf), (regval1 & 0xf), ((regval >> 28) & 0xf), ((regval >> 24) & 0xf),
+          ((regval >> 20) & 0xf), ((regval >> 16) & 0xf), ((regval >> 12) & 0xf), ((regval >> 8) & 0xf),
+          ((regval >> 4) & 0xf), (regval & 0xf));
+    SET_RG_SPECTRUM_EN(0);
+}
+static void _turismoC_5g_rxiq_cal(struct ssv_hw *sh)
+{
+    int count = 0;
+    int band;
+    SET_RG_SX5GB_RFCH_MAP_EN(1);
+    dev_dbg(sh->sc->dev, "--------------------------------------------");
+    dev_dbg(sh->sc->dev, "before 5G rx iq calibration, rx alpha: %d %d %d %d, rx theta %d %d %d %d",
+          GET_RG_RX_IQ_5100_ALPHA, GET_RG_RX_IQ_5500_ALPHA,
+          GET_RG_RX_IQ_5700_ALPHA, GET_RG_RX_IQ_5900_ALPHA,
+          GET_RG_RX_IQ_5100_THETA, GET_RG_RX_IQ_5500_THETA,
+          GET_RG_RX_IQ_5700_THETA, GET_RG_RX_IQ_5900_THETA);
+    SET_RG_TXGAIN_PHYCTRL(1);
+    SET_RG_5G_RFG_RXIQCAL(0x0);
+    SET_RG_5G_PGAG_RXIQCAL(0x3);
+    SET_RG_TONE_SCALE(0x80);
+    SET_RG_PRE_DC_AUTO(1);
+    SET_RG_TX_IQCAL_TIME(1);
+    SET_RG_PHASE_1M(0xccc);
+    SET_RG_PHASE_RXIQ_1M(0xccc);
+    SET_RG_ALPHA_SEL(2);
+    for (band = 0; band < 4; band ++) {
+        count = 0;
+        SET_RG_CAL_INDEX(CAL_IDX_WIFI5G_RXIQ);
+        UDELAY(250);
+        while (GET_RO_5G_RXIQ_DONE == 0) {
+            count ++;
+            if (count > 100000) {
+                dev_err(sh->sc->dev, "%s: 5G RXIQ band %d cal failed",__func__, band);
+                break;
+            }
+            UDELAY(1);
+        }
+        SET_RG_PHASE_STEP_VALUE(0xccc);
+        _debug_5g_rxiq_cal(sh);
+        SET_RG_CAL_INDEX(CAL_IDX_NONE);
+    }
+    dev_dbg(sh->sc->dev, "--------------------------------------------%d", count);
+    sh->cal.rxiq_alpha[BAND_5100] = GET_RG_RX_IQ_5100_ALPHA;
+    sh->cal.rxiq_theta[BAND_5100] = GET_RG_RX_IQ_5100_THETA;
+    sh->cal.rxiq_alpha[BAND_5500] = GET_RG_RX_IQ_5500_ALPHA;
+    sh->cal.rxiq_theta[BAND_5500] = GET_RG_RX_IQ_5500_THETA;
+    sh->cal.rxiq_alpha[BAND_5700] = GET_RG_RX_IQ_5700_ALPHA;
+    sh->cal.rxiq_theta[BAND_5700] = GET_RG_RX_IQ_5700_THETA;
+    sh->cal.rxiq_alpha[BAND_5900] = GET_RG_RX_IQ_5900_ALPHA;
+    sh->cal.rxiq_theta[BAND_5900] = GET_RG_RX_IQ_5900_THETA;
+    dev_dbg(sh->sc->dev, "After 5G rx iq calibration, rx alpha: %d %d %d %d, rx theta %d %d %d %d",
+          sh->cal.rxiq_alpha[BAND_5100], sh->cal.rxiq_alpha[BAND_5500],
+          sh->cal.rxiq_alpha[BAND_5700], sh->cal.rxiq_alpha[BAND_5900],
+          sh->cal.rxiq_theta[BAND_5100], sh->cal.rxiq_theta[BAND_5500],
+          sh->cal.rxiq_theta[BAND_5700], sh->cal.rxiq_theta[BAND_5900]);
+}
+void _turismoC_5g_rxiq_cal_band(struct ssv_hw *sh, int pa_band)
+{
+    int count = 0, alpha = 0, theta = 0;
+    SET_RG_SX5GB_RFCH_MAP_EN(1);
+    SET_RG_SX5GB_CHANNEL(cal_ch_5g[pa_band-1]);
+    if( pa_band == BAND_5700 ) {
+        SET_RG_5G_TX_GAIN_RXIQCAL(PAPDP_GAIN_SETTING_F2);
+    } else {
+        SET_RG_5G_TX_GAIN_RXIQCAL(PAPDP_GAIN_SETTING);
+    }
+    switch (pa_band) {
+    case BAND_5100:
+        alpha = GET_RG_RX_IQ_5100_ALPHA;
+        theta = GET_RG_RX_IQ_5100_THETA;
+        SET_RG_RX_IQ_5100_ALPHA(0);
+        SET_RG_RX_IQ_5100_THETA(0);
+        SET_RG_DPD_BB_SCALE_5100(0x80);
+        break;
+    case BAND_5500:
+        alpha = GET_RG_RX_IQ_5500_ALPHA;
+        theta = GET_RG_RX_IQ_5500_THETA;
+        SET_RG_RX_IQ_5500_ALPHA(0);
+        SET_RG_DPD_BB_SCALE_5500(0x80);
+        SET_RG_RX_IQ_5500_THETA(0);
+        break;
+    case BAND_5700:
+        alpha = GET_RG_RX_IQ_5700_ALPHA;
+        theta = GET_RG_RX_IQ_5700_THETA;
+        SET_RG_RX_IQ_5700_ALPHA(0);
+        SET_RG_RX_IQ_5700_THETA(0);
+        SET_RG_DPD_BB_SCALE_5700(0x80);
+        break;
+    case BAND_5900:
+        alpha = GET_RG_RX_IQ_5900_ALPHA;
+        theta = GET_RG_RX_IQ_5900_THETA;
+        SET_RG_RX_IQ_5900_ALPHA(0);
+        SET_RG_RX_IQ_5900_THETA(0);
+        SET_RG_DPD_BB_SCALE_5900(0x80);
+        break;
+    default:
+        break;
+    }
+    dev_dbg(sh->sc->dev, "--------------------------------------------");
+    dev_dbg(sh->sc->dev, "before 5G band%d rx iq calibration, rx alpha: %d, rx theta %d",
+          pa_band, alpha, theta);
+    SET_RG_TXGAIN_PHYCTRL(1);
+    SET_RG_5G_RFG_RXIQCAL(0x0);
+    SET_RG_5G_PGAG_RXIQCAL(0x3);
+    SET_RG_TONE_SCALE(0x80);
+    SET_RG_PRE_DC_AUTO(1);
+    SET_RG_TX_IQCAL_TIME(1);
+    SET_RG_PHASE_1M(0xccc);
+    SET_RG_PHASE_RXIQ_1M(0xccc);
+    SET_RG_ALPHA_SEL(2);
+    SET_RG_CAL_INDEX(CAL_IDX_WIFI5G_RXIQ);
+    UDELAY(250);
+    while (GET_RO_5G_RXIQ_DONE == 0) {
+        count ++;
+        if (count > 100000) {
+            dev_err(sh->sc->dev, "%s: 5G RXIQ band %d cal failed",__func__, pa_band);
+            break;
+        }
+        UDELAY(1);
+    }
+    SET_RG_PHASE_STEP_VALUE(0xccc);
+    _debug_5g_rxiq_cal(sh);
+    SET_RG_CAL_INDEX(CAL_IDX_NONE);
+    switch (pa_band) {
+    case BAND_5100:
+        sh->cal.rxiq_alpha[pa_band] = GET_RG_RX_IQ_5100_ALPHA;
+        sh->cal.rxiq_theta[pa_band] = GET_RG_RX_IQ_5100_THETA;
+        break;
+    case BAND_5500:
+        sh->cal.rxiq_alpha[pa_band] = GET_RG_RX_IQ_5500_ALPHA;
+        sh->cal.rxiq_theta[pa_band] = GET_RG_RX_IQ_5500_THETA;
+        break;
+    case BAND_5700:
+        sh->cal.rxiq_alpha[pa_band] = GET_RG_RX_IQ_5700_ALPHA;
+        sh->cal.rxiq_theta[pa_band] = GET_RG_RX_IQ_5700_THETA;
+        break;
+    case BAND_5900:
+        sh->cal.rxiq_alpha[pa_band] = GET_RG_RX_IQ_5900_ALPHA;
+        sh->cal.rxiq_theta[pa_band] = GET_RG_RX_IQ_5900_THETA;
+        break;
+    default:
+        break;
+    }
+    dev_dbg(sh->sc->dev, "--------------------------------------------%d", count);
+    dev_dbg(sh->sc->dev, "After 5G band%d rx iq calibration, rx alpha: %d, rx theta %d",
+          pa_band, sh->cal.rxiq_alpha[pa_band], sh->cal.rxiq_theta[pa_band]);
+}
+#define MULTIPLIER 1024
+static void _dpd_set_txscale_get_result(struct ssv_hw *sh, int rg_tx_scale, int *am, int *pm)
+{
+    int regval;
+    SET_RG_TX_SCALE(rg_tx_scale);
+    UDELAY(200);
+    SET_RG_RX_PADPD_LATCH(1);
+    UDELAY(10);
+    SET_RG_RX_PADPD_LATCH(0);
+    regval= REG32_R(ADR_WIFI_PADPD_CAL_RX_RO);
+    *am = (regval >>16) & 0x1ff;
+    *pm = regval & 0x1fff;
+}
+void _pre_padpd(struct ssv_hw *sh, int pa_band, int init_gain)
+{
+    SET_RG_DPD_AM_EN(0);
+    SET_RG_TXGAIN_PHYCTRL(1);
+    SET_RG_MODE_MANUAL(1);
+    SET_RG_MODE(MODE_STANDBY);
+    if (pa_band == 0) {
+        SET_REG(ADR_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE,
+                (0x6 << RG_SX_CHANNEL_SFT) | (0x1 << RG_SX_RFCH_MAP_EN_SFT), 0,
+                (RG_SX_CHANNEL_I_MSK & RG_SX_RFCH_MAP_EN_I_MSK));
+        SET_RG_TX_GAIN_DPDCAL(6);
+        SET_RG_PGAG_DPDCAL(init_gain);
+        SET_RG_RFG_DPDCAL(0);
+        SET_RG_TX_GAIN(PAPDP_GAIN_SETTING_2G);
+        SET_RG_DPD_BB_SCALE_2500(0x80);
+    } else {
+        SET_RG_SX5GB_RFCH_MAP_EN(1);
+        SET_RG_SX5GB_CHANNEL(cal_ch_5g[pa_band-1]);
+        SET_RG_5G_PGAG_DPDCAL(init_gain);
+        SET_RG_5G_RFG_DPDCAL(0);
+        switch (pa_band) {
+        case BAND_5100:
+            SET_RG_5G_TX_PAFB_EN_F0(0);
+            SET_RG_5G_TX_GAIN_F0(PAPDP_GAIN_SETTING);
+            SET_RG_5G_TX_GAIN_DPDCAL(PAPDP_GAIN_SETTING);
+            SET_RG_DPD_BB_SCALE_5100(0x80);
+            break;
+        case BAND_5500:
+            SET_RG_5G_TX_PAFB_EN_F1(0);
+            SET_RG_5G_TX_GAIN_F1(PAPDP_GAIN_SETTING);
+            SET_RG_5G_TX_GAIN_DPDCAL(PAPDP_GAIN_SETTING);
+            SET_RG_DPD_BB_SCALE_5500(0x80);
+            break;
+        case BAND_5700:
+            SET_RG_5G_TX_PAFB_EN_F2(0);
+            SET_RG_5G_TX_GAIN_F2(PAPDP_GAIN_SETTING_F2);
+            SET_RG_5G_TX_GAIN_DPDCAL(PAPDP_GAIN_SETTING_F2);
+            SET_RG_DPD_BB_SCALE_5700(0x80);
+            break;
+        case BAND_5900:
+            SET_RG_5G_TX_PAFB_EN_F3(0);
+            SET_RG_5G_TX_GAIN_F3(PAPDP_GAIN_SETTING);
+            SET_RG_5G_TX_GAIN_DPDCAL(PAPDP_GAIN_SETTING);
+            SET_RG_DPD_BB_SCALE_5900(0x80);
+            break;
+        default:
+            break;
+        }
+    }
+    SET_RG_BB_SIG_EN(1);
+    SET_RG_DC_RM_BYP(1);
+    SET_RG_TX_IQ_SRC(2);
+    SET_RG_TX_BB_SCALE_MANUAL(1);
+    SET_RG_TX_SCALE(0x0);
+    SET_RG_TONE_1_RATE(0xccc);
+    SET_RG_TONE_SEL(1);
+    SET_RG_RX_PADPD_TONE_SEL(0);
+    SET_RG_RX_PADPD_DATA_SEL(0);
+    SET_RG_RX_PADPD_LEAKY_FACTOR(7);
+    SET_RG_RX_PADPD_EN(1);
+    SET_RG_MODE(MODE_CALIBRATION);
+    if (pa_band == 0) {
+        SET_RG_CAL_INDEX(CAL_IDX_WIFI2P4G_PADPD);
+    } else {
+        SET_RG_CAL_INDEX(CAL_IDX_WIFI5G_PADPD);
+    }
+    UDELAY(100);
+}
+void _post_padpd(struct ssv_hw *sh)
+{
+    SET_RG_TX_SCALE(0x0);
+    UDELAY(200);
+    SET_RG_CAL_INDEX(CAL_IDX_NONE);
+    SET_RG_MODE(MODE_STANDBY);
+    SET_RG_MODE_MANUAL(0);
+    SET_RG_BB_SIG_EN(0);
+    SET_RG_DC_RM_BYP(0);
+    SET_RG_TX_IQ_SRC(0);
+    SET_RG_TX_BB_SCALE_MANUAL(0);
+    SET_RG_TONE_SEL(0);
+    SET_RG_RX_PADPD_EN(0);
+}
+void _check_padpd_gain(struct ssv_hw *sh, int pa_band, int init_gain, int *ret)
+{
+    int rg_tx_scale;
+    int am, pm;
+    dev_dbg(sh->sc->dev, "check PA DPD on band %d", pa_band);
+    _pre_padpd(sh, pa_band, init_gain);
+    rg_tx_scale = 48+(MAX_PADPD_TONE - 1-5)*4;
+    _dpd_set_txscale_get_result(sh, rg_tx_scale, &am, &pm);
+    if (am >=510) {
+        *ret = 1;
+        dev_dbg(sh->sc->dev, "gain probe fail, am %d", am);
+    }
+    _post_padpd(sh);
+}
+static void _start_padpd(struct ssv_hw *sh, struct ssv6006dpd *val, int pa_band, int init_gain, u8 dpd_bbscale, int *ret)
+{
+    int i, rg_tx_scale, regval;
+    int am, pm;
+    int slope_ini = 0, phase_ini = 0;
+    int padpd_am = 0, padpd_pm = 0;
+    u32 addr_am = 0, addr_pm = 0, mask_am = 0, mask_pm = 0;
+    dev_dbg(sh->sc->dev, "start PA DPD on band %d", pa_band);
+    _pre_padpd(sh, pa_band, init_gain);
+#if 0
+    rg_tx_scale = 8;
+    _dpd_set_txscale_get_result(sh, rg_tx_scale, &am, &pm);
+    slope_ini = (am * MULTIPLIER) / rg_tx_scale;
+    phase_ini = pm;
+    dev_dbg(sh->sc->dev, "slope is (%d/%d), initial phase is %d ", slope_ini, MULTIPLIER, pm);
+    rg_tx_scale = 48+(MAX_PADPD_TONE - 1-5)*4;
+    _dpd_set_txscale_get_result(sh, rg_tx_scale, &am, &pm);
+    if (am >=510) {
+        *ret = 1;
+        goto fail;
+    }
+    SET_RG_TX_SCALE(0);
+    UDELAY(1000);
+#endif
+    for(i = 0; i < MAX_PADPD_TONE; i++) {
+        if( i < 6 ) {
+            rg_tx_scale = (i+1)*8;
+        } else {
+            rg_tx_scale = 48+(i-5)*4;
+        }
+        _dpd_set_txscale_get_result(sh, rg_tx_scale, &am, &pm);
+        if (am >=510) {
+            *ret = 1;
+            break;
+        }
+        if ( i == 0) {
+            slope_ini = (am * MULTIPLIER) / rg_tx_scale;
+            phase_ini = pm;
+        }
+        if (am != 0)
+            padpd_am = (512 * rg_tx_scale * slope_ini ) / (am*MULTIPLIER);
+        if (padpd_am > 1023) {
+            padpd_am = 1023;
+        }
+        padpd_pm = (phase_ini >= pm) ? (phase_ini - pm) : (phase_ini - pm + 8192);
+        dev_dbg(sh->sc->dev, "index %d, padpd_am %d, padpd_pm 0x%04x, ", i, padpd_am, padpd_pm);
+        addr_am = padpd_am_addr_table[pa_band][(i >> 1)];
+        mask_am = am_mask[i%2];
+        addr_pm = padpd_pm_addr_table[pa_band][(i >> 1)];
+        mask_pm = pm_mask[i%2];
+        regval = REG32_R(addr_am);
+        REG32_W(addr_am, (regval & mask_am) | ((padpd_am) << ((i & 0x1)*16)) );
+        if (i & 0x1) {
+            val->am[ (i >> 1)] = (regval & mask_am) | ((padpd_am) << ((i & 0x1)*16));
+        }
+        regval = REG32_R(addr_pm);
+        REG32_W(addr_pm, (regval & mask_pm) | ((padpd_pm) << ((i & 0x1)*16)) );
+        if (i & 0x1) {
+            val->pm[ (i >> 1)] = (regval & mask_pm) | ((padpd_pm) << ((i & 0x1)*16));
+        }
+    }
+    _post_padpd(sh);
+    if (*ret != 1) {
+        switch (pa_band) {
+        case BAND_2G:
+            SET_RG_DPD_BB_SCALE_2500(dpd_bbscale);
+            break;
+        case BAND_5100:
+            SET_RG_DPD_BB_SCALE_5100(dpd_bbscale);
+            break;
+        case BAND_5500:
+            SET_RG_DPD_BB_SCALE_5500(dpd_bbscale);
+            break;
+        case BAND_5700:
+            SET_RG_DPD_BB_SCALE_5700(dpd_bbscale);
+            break;
+        case BAND_5900:
+            SET_RG_DPD_BB_SCALE_5900(dpd_bbscale);
+            break;
+        default:
+            break;
+        }
+        SET_RG_DPD_AM_EN(1);
+        SET_RG_TXGAIN_PHYCTRL(0);
+    }
+}
+static void _restore_dpd(struct ssv_hw *sh, struct ssv6006_padpd *dpd)
+{
+    int i;
+    u32 addr_am, addr_pm;
+    for (i = 0; i < (MAX_PADPD_TONE/2) ; i++) {
+        addr_am = padpd_am_addr_table[dpd->current_band][i];
+        addr_pm = padpd_pm_addr_table[dpd->current_band][i];
+        REG32_W(addr_am, dpd->val[dpd->current_band].am[i] );
+        REG32_W(addr_pm, dpd->val[dpd->current_band].pm[i] );
+    }
+    switch (dpd->current_band) {
+    case BAND_2G:
+        SET_RG_DPD_BB_SCALE_2500(dpd->bbscale[BAND_2G]);
+        break;
+    case BAND_5100:
+        SET_RG_DPD_BB_SCALE_5100(dpd->bbscale[BAND_5100]);
+        break;
+    case BAND_5500:
+        SET_RG_DPD_BB_SCALE_5500(dpd->bbscale[BAND_5500]);
+        break;
+    case BAND_5700:
+        SET_RG_DPD_BB_SCALE_5700(dpd->bbscale[BAND_5700]);
+        break;
+    case BAND_5900:
+        SET_RG_DPD_BB_SCALE_5900(dpd->bbscale[BAND_5900]);
+        break;
+    default:
+        break;
+    }
+}
+void _verify_dpd(struct ssv_hw *sh, struct ssv6006_padpd *dpd, int pa_band)
+{
+    u8 hw_dpd_bbscale;
+    switch (pa_band) {
+    case BAND_2G:
+        hw_dpd_bbscale = GET_RG_DPD_BB_SCALE_2500;
+        break;
+    case BAND_5100:
+        hw_dpd_bbscale = GET_RG_DPD_BB_SCALE_5100;
+        break;
+    case BAND_5500:
+        hw_dpd_bbscale = GET_RG_DPD_BB_SCALE_5500;
+        break;
+    case BAND_5700:
+        hw_dpd_bbscale = GET_RG_DPD_BB_SCALE_5700;
+        break;
+    case BAND_5900:
+        hw_dpd_bbscale = GET_RG_DPD_BB_SCALE_5900;
+        break;
+    default:
+        hw_dpd_bbscale = 0;
+        break;
+    }
+    if (hw_dpd_bbscale == 0x80) {
+        dev_dbg(sh->sc->dev, "HW DPD value changed, restore DPD");
+        _restore_dpd(sh, dpd);
+    }
+    if (dpd->current_band != pa_band) {
+        SET_RG_DPD_AM_EN(1);
+        SET_RG_TXGAIN_PHYCTRL(0);
+    }
+}
+static void _check_padpd(struct ssv_hw *sh, struct ssv6006_padpd *dpd, int pa_band)
+{
+    int ret = 0;
+    struct ssv6006dpd *val;
+    u8 dpd_bbscale = 0;
+    val = &dpd->val[pa_band];
+    dpd_bbscale = dpd->bbscale[pa_band];
+    if (dpd->dpd_disable[pa_band] == true) {
+        if (dpd->current_band != pa_band) {
+            SET_RG_DPD_AM_EN(0);
+            SET_RG_TXGAIN_PHYCTRL(0);
+        }
+        switch (dpd->current_band) {
+        case BAND_2G:
+            SET_RG_DPD_BB_SCALE_2500(dpd->bbscale[BAND_2G]);
+            dev_dbg(sh->sc->dev, "set dpd bbscale to %d", dpd->bbscale[BAND_2G]);
+            break;
+        case BAND_5100:
+            SET_RG_DPD_BB_SCALE_5100(dpd->bbscale[BAND_5100]);
+            break;
+        case BAND_5500:
+            SET_RG_DPD_BB_SCALE_5500(dpd->bbscale[BAND_5100]);
+            break;
+        case BAND_5700:
+            SET_RG_DPD_BB_SCALE_5700(dpd->bbscale[BAND_5700]);
+            break;
+        case BAND_5900:
+            SET_RG_DPD_BB_SCALE_5900(dpd->bbscale[BAND_5900]);
+            break;
+        default:
+            break;
+        }
+    } else {
+        if ( dpd->dpd_done[pa_band] == false) {
+            int init_gain = 4;
+            if (pa_band != 0) init_gain = 2;
+            while (1) {
+                ret = 0;
+                _check_padpd_gain(sh, pa_band, init_gain, &ret);
+                if (!ret) break;
+                dev_dbg(sh->sc->dev, "Check padpd init gain %d fail on band %d", init_gain, pa_band);
+                init_gain --;
+                if (init_gain == 0) break;
+            }
+            dev_dbg(sh->sc->dev, "Start PADPD on band %d ,init gain %d", pa_band, init_gain);
+            while (1) {
+                ret = 0;
+                _start_padpd(sh, val, pa_band, init_gain, dpd_bbscale, &ret);
+                if (!ret) {
+                    dev_dbg(sh->sc->dev, "PA DPD done!!");
+                    dpd->dpd_done[pa_band] = true;
+                    break;
+                }
+                init_gain--;
+                dev_dbg(sh->sc->dev, "Failed on band %d, Lower gain to %d", pa_band, init_gain);
+                if (init_gain < 0) {
+                    SET_RG_DPD_AM_EN(0);
+                    SET_RG_TXGAIN_PHYCTRL(0);
+                    dev_err(sh->sc->dev, "WARNING:PADPD FAIL");
+                    break;
+                }
+            }
+        } else {
+            _verify_dpd(sh, dpd, pa_band);
+        }
+    }
+    dpd->current_band = pa_band;
+}
+void _check_iqk(struct ssv_hw *sh, struct ssv6006_cal_result *cal, int pa_band)
+{
+    if (cal->cal_iq_done[pa_band] == false) {
+        printk("do iqk on band %d", pa_band);
+        SET_RG_DPD_AM_EN(0);
+        SET_RG_TXGAIN_PHYCTRL(1);
+        if (pa_band == BAND_2G) {
+            _turismoC_pre_cal(sh);
+            _turismoC_txiq_cal(sh);
+            _turismoC_inter_cal(sh);
+            _turismoC_rxiq_cal(sh);
+            _turismoC_post_cal(sh);
+        } else {
+            if (sh->cfg.hw_caps & SSV6200_HW_CAP_5GHZ) {
+                _turismoC_pre_cal(sh);
+                _turismoC_5g_txiq_cal_band(sh, pa_band);
+                _turismoC_inter_cal(sh);
+                _turismoC_5g_rxiq_cal_band(sh, pa_band);
+                _turismoC_post_cal(sh);
+            }
+        }
+        cal->cal_iq_done[pa_band] = true;
+    }
+}
+static void _check_padpd_iqk(struct ssv_hw *sh, struct ssv6006_padpd *dpd,
+                             struct ssv6006_cal_result *cal, int ch)
+{
+    int pa_band;
+    pa_band = ssv6006_get_pa_band(ch);
+    _check_iqk(sh, cal, pa_band);
+    _check_padpd(sh, dpd, pa_band);
+}
+void ssv6006_turismoC_init_fast_cali (struct ssv_hw *sh, struct ssv6006_cal_result *cal)
+{
+#ifdef USE_COMMON_MACRO
+    if (sh->cfg.hw_caps & SSV6200_HW_CAP_5GHZ) {
+        TU_INIT_TURISMOC_CALI(cal);
+    } else {
+        TU_INIT_TURISMOC_2G_CALI(cal);
+    }
+#else
+    SET_RG_DPD_AM_EN(0);
+    SET_RG_TXGAIN_PHYCTRL(1);
+    if (sh->cfg.hw_caps & SSV6200_HW_CAP_5GHZ)
+        REG32_W(ADR_WIFI_PADPD_5G_BB_GAIN_REG, 0x80808080);
+    _turismoC_pre_cal(sh);
+    _turismoC_2p4g_rxdc_cal(sh);
+    _turismoC_inter_cal(sh);
+    _turismoC_bw20_rxrc_cal(sh);
+    _turismoC_inter_cal(sh);
+    _turismoC_bw40_rxrc_cal(sh);
+    _turismoC_inter_cal(sh);
+    _turismoC_txdc_cal(sh);
+    if (sh->cfg.hw_caps & SSV6200_HW_CAP_5GHZ) {
+        _turismoC_inter_cal(sh);
+        _turismoC_5g_rxdc_cal(sh);
+        _turismoC_inter_cal(sh);
+        _turismoC_5g_txdc_cal(sh);
+    }
+    _turismoC_post_cal(sh);
+#endif
+    cal->cal_done = true;
+}
+static void _remove_spur_patch(struct ssv_hw *sh, struct ssv6006_padpd *dpd,
+                               struct ssv6006_cal_result *cal)
+{
+    if (dpd->spur_patched) {
+        SET_RG_EN_RX_PADSW(0);
+        SET_RG_WF_RX_ABBCTUNE(cal->rxrc_bw20);
+        SET_RG_SC_CTRL0(0);
+        SET_RG_ERASE_SC_NUM0(0x7f);
+        SET_RG_SC_CTRL1(0);
+        SET_RG_ERASE_SC_NUM1(0x7f);
+        SET_RG_ATCOR16_RATIO_CCD(0x30);
+        SET_RG_ATCOR16_CCA_GAIN(0x0);
+        dpd->spur_patched = false;
+    }
+}
+static void _check_spur(struct ssv_hw *sh, struct ssv6006_padpd *dpd,
+                        struct ssv6006_cal_result *cal, int ch, int channel_type)
+{
+    int pa_band = 0;
+    int xtal;
+    xtal = GET_RG_DP_XTAL_FREQ;
+    if (REG32_R(ADR_CHIP_ID_2) == DUAL_BAND_ID) {
+        if (xtal != XTAL40M)
+            return;
+    }
+    pa_band = ssv6006_get_pa_band(ch);
+    if (sh->cal.cal_iq_done[pa_band] == true) {
+        if ((ch >=13) || ((ch >= 9) && (channel_type == NL80211_CHAN_HT40PLUS))) {
+            SET_RG_EN_RX_PADSW(1);
+            dpd->spur_patched = true;
+        }
+        if ((ch == 13)
+            && ((channel_type == NL80211_CHAN_NO_HT) || (channel_type == NL80211_CHAN_HT20))) {
+            SET_RG_WF_RX_ABBCTUNE(0x3F);
+            SET_RG_SC_CTRL0(1);
+            SET_RG_ERASE_SC_NUM0(22);
+            SET_RG_SC_CTRL1(1);
+            SET_RG_ERASE_SC_NUM1(23);
+        } else {
+            SET_RG_WF_RX_ABBCTUNE(cal->rxrc_bw20);
+            if (((ch == 9) && (channel_type == NL80211_CHAN_HT40PLUS))
+                || ((ch == 13) && (channel_type == NL80211_CHAN_HT40MINUS))) {
+                SET_RG_SC_CTRL0(1);
+                SET_RG_ERASE_SC_NUM0(52);
+                SET_RG_SC_CTRL1(1);
+                SET_RG_ERASE_SC_NUM1(53);
+            }
+        }
+        if ((ch == 13) &&
+            ((channel_type == NL80211_CHAN_NO_HT) || (channel_type == NL80211_CHAN_HT20) ||
+             (channel_type == NL80211_CHAN_HT40MINUS))) {
+            SET_RG_ATCOR16_RATIO_CCD(0x40);
+            SET_RG_ATCOR16_CCA_GAIN(0x1);
+        }
+    }
+}
+#endif
+static void ssv6006_turismoC_update_channel_dpd_bbscale(struct ssv_softc *sc, int ch)
+{
+    struct ssv_hw *sh = sc->sh;
+    struct ssv_tempe_table *tempe_table;
+    u32 regval = 0;
+    if ((!sh->flash_config.exist) || (ch > 14))
+        return;
+    if (sh->flash_config.band_gain_tempe_state == SSV_TEMPERATURE_LOW) {
+        tempe_table = &sh->flash_config.lt_config;
+    } else if (sh->flash_config.band_gain_tempe_state == SSV_TEMPERATURE_HIGH) {
+        tempe_table = &sh->flash_config.ht_config;
+    } else {
+        tempe_table = &sh->flash_config.rt_config;
+    }
+    regval = tempe_table->g_band_gain[ch/2];
+    sc->dpd.bbscale[BAND_2G] = regval;
+    SET_RG_DPD_BB_SCALE_2500(regval);
+}
+static int ssv6006_turismoC_set_channel(struct ssv_softc *sc, struct ieee80211_channel *chan,
+                                        enum nl80211_channel_type channel_type)
+{
+    int ch = chan->hw_value;
+    struct ssv_hw *sh = sc->sh;
+    struct ssv6006_padpd *dpd = &sc->dpd;
+    struct ssv6006_cal_result *cal = &sc->sh->cal;
+#ifdef USE_COMMON_MACRO
+    TU_CHANGE_TURISMOC_CHANNEL(ch, channel_type, dpd, cal);
+#else
+    const char *chan_type[]= {"NL80211_CHAN_NO_HT",
+                              "NL80211_CHAN_HT20",
+                              "NL80211_CHAN_HT40MINUS",
+                              "NL80211_CHAN_HT40PLUS"
+                             };
+    dev_dbg(sh->sc->dev, "%s: ch %d, type %s", __func__, ch, chan_type[channel_type]);
+    SET_RG_SOFT_RST_N_11B_RX(0);
+    SET_RG_SOFT_RST_N_11GN_RX(0);
+    _remove_spur_patch(sh, dpd, cal);
+    if (REG32_R(ADR_WIFI_PHY_COMMON_ENABLE_REG) != 0) {
+        _check_padpd_iqk(sh, dpd, cal, ch);
+    }
+    _set_turismoC_BW(sh, channel_type);
+    if ((ch <=14) && (ch >=1)) {
+        SET_SIFS(10);
+        SET_SIGEXT(6);
+        _check_spur(sh, dpd, cal, ch, channel_type);
+        _set_2g_channel(sh, ch);
+    } else if (ch >=34) {
+        SET_SIFS(16);
+        SET_SIGEXT(0);
+        _set_5g_channel(sh, ch);
+    } else {
+        dev_dbg(sh->sc->dev, "invalid channel %d", ch);
+    }
+#endif
+    ssv6006_turismoC_update_channel_dpd_bbscale(sc, ch);
+    sc->dpd.pwr_mode = NORMAL_PWR;
+    HAL_UPDATE_RF_PWR(sc);
+    return 0;
+}
+static void ssv6006_turismoC_init_cali (struct ssv_hw *sh, struct ssv6006_cal_result *cal)
+{
+#ifdef USE_COMMON_MACRO
+    if (sh->cfg.hw_caps & SSV6200_HW_CAP_5GHZ) {
+        TU_INIT_TURISMOC_CALI(cal);
+    } else {
+        TU_INIT_TURISMOC_2G_CALI(cal);
+    }
+#else
+    SET_RG_DPD_AM_EN(0);
+    SET_RG_TXGAIN_PHYCTRL(1);
+    if (sh->cfg.hw_caps & SSV6200_HW_CAP_5GHZ)
+        REG32_W(ADR_WIFI_PADPD_5G_BB_GAIN_REG, 0x80808080);
+    _turismoC_pre_cal(sh);
+    _turismoC_2p4g_rxdc_cal(sh);
+    _turismoC_inter_cal(sh);
+    _turismoC_bw20_rxrc_cal(sh);
+    _turismoC_inter_cal(sh);
+    _turismoC_bw40_rxrc_cal(sh);
+    _turismoC_inter_cal(sh);
+    _turismoC_txdc_cal(sh);
+    _turismoC_inter_cal(sh);
+    _turismoC_txiq_cal(sh);
+    _turismoC_inter_cal(sh);
+    _turismoC_rxiq_cal(sh);
+    sh->cal.cal_iq_done[BAND_2G] = true;
+    if (sh->cfg.hw_caps & SSV6200_HW_CAP_5GHZ) {
+        int i;
+        _turismoC_inter_cal(sh);
+        _turismoC_5g_rxdc_cal(sh);
+        _turismoC_inter_cal(sh);
+        _turismoC_5g_txdc_cal(sh);
+        _turismoC_inter_cal(sh);
+        _turismoC_5g_txiq_cal(sh);
+        _turismoC_inter_cal(sh);
+        _turismoC_5g_rxiq_cal(sh);
+        for (i = BAND_5100; i < MAX_BAND; i++)
+            sh->cal.cal_iq_done[i] = true;
+    }
+    _turismoC_post_cal(sh);
+    cal->cal_done = true;
+#endif
+}
+static void ssv6006_turismoC_init_iqk (struct ssv_hw *sh, struct ssv6006_cal_result *cal)
+{
+#ifdef USE_COMMON_MACRO
+    if (sh->cfg.hw_caps & SSV6200_HW_CAP_5GHZ) {
+        TU_INIT_TURISMOC_CALI(cal);
+    } else {
+        TU_INIT_TURISMOC_2G_CALI(cal);
+    }
+#else
+    SET_RG_DPD_AM_EN(0);
+    SET_RG_TXGAIN_PHYCTRL(1);
+    if (sh->cfg.hw_caps & SSV6200_HW_CAP_5GHZ)
+        REG32_W(ADR_WIFI_PADPD_5G_BB_GAIN_REG, 0x80808080);
+    _turismoC_pre_cal(sh);
+    _turismoC_txiq_cal(sh);
+    _turismoC_inter_cal(sh);
+    _turismoC_rxiq_cal(sh);
+    sh->cal.cal_iq_done[BAND_2G] = true;
+    if (sh->cfg.hw_caps & SSV6200_HW_CAP_5GHZ) {
+        int i;
+        _turismoC_inter_cal(sh);
+        _turismoC_5g_txiq_cal(sh);
+        _turismoC_inter_cal(sh);
+        _turismoC_5g_rxiq_cal(sh);
+        for (i = BAND_5100; i < MAX_BAND; i++)
+            sh->cal.cal_iq_done[i] = true;
+    }
+    _turismoC_post_cal(sh);
+    cal->cal_done = true;
+#endif
+}
+#if 0
+void ssv6006_turismoC_write_rf_table(struct ssv_hw *sh )
+{
+}
+#endif
+#ifndef USE_COMMON_MACRO
+static void _update_rf_patch(struct ssv_hw *sh, int xtal)
+{
+    dev_dbg(sh->sc->dev, "Set XTAL to %sM", xtal_type[xtal]);
+    SET_RG_DP_XTAL_FREQ(xtal);
+    SET_RG_SX_XTAL_FREQ(xtal);
+}
+static void single_band_patch(struct ssv_hw *sh, int xtal)
+{
+    if (REG32_R(ADR_CHIP_ID_2) != DUAL_BAND_ID) {
+        SET_RG_SX_LPF_C2_WF(0xE);
+        SET_RG_XO_LDO_LEVEL(0x6);
+        SET_RG_SX_LDO_LO_LEVEL(0x3);
+        SET_RG_SX_VCO_RXOB_AW(0x1);
+        SET_RG_SX_VCO_TXOB_AW(0x1);
+        SET_RG_SX_CP_ISEL_WF(xtal_sx_cp_isel_wf[xtal]);
+        dev_dbg(sh->sc->dev, "set single band spur patch %x", REG32_R(ADR_CHIP_ID_2));
+    }
+}
+#endif
+static int ssv6006_turismoC_set_pll_phy_rf(struct ssv_hw *sh
+        , ssv_cabrio_reg *rf_tbl, ssv_cabrio_reg *phy_tbl)
+{
+    int ret = 0;
+    int xtal;
+    int i;
+    struct ssv6006_patch patch;
+    struct ssv6006_cal_result *cal = &sh->cal;
+    memset(&patch, 0x0, sizeof(struct ssv6006_patch));
+    switch (sh->cfg.crystal_type) {
+    case SSV6XXX_IQK_CFG_XTAL_16M:
+        xtal = XTAL16M;
+        break;
+    case SSV6XXX_IQK_CFG_XTAL_24M:
+        xtal = XTAL24M;
+        break;
+    case SSV6XXX_IQK_CFG_XTAL_26M:
+        xtal = XTAL26M;
+        break;
+    case SSV6XXX_IQK_CFG_XTAL_40M:
+        xtal = XTAL40M;
+        break;
+    case SSV6XXX_IQK_CFG_XTAL_12M:
+        xtal = XTAL12M;
+        break;
+    case SSV6XXX_IQK_CFG_XTAL_20M:
+        xtal = XTAL20M;
+        break;
+    case SSV6XXX_IQK_CFG_XTAL_25M:
+        xtal = XTAL25M;
+        break;
+    case SSV6XXX_IQK_CFG_XTAL_32M:
+        xtal = XTAL32M;
+        break;
+    default:
+        printk("Please redefine xtal_clock(wifi.cfg)!!");
+        WARN_ON(1);
+        return 1;
+        break;
+    }
+    patch.xtal = xtal;
+    if (sh->cfg.clk_src_80m)
+        patch.cpu_clk = CLK_80M;
+    else
+        patch.cpu_clk = CLK_40M;
+    if (sh->cfg.volt_regulator == SSV6XXX_VOLT_DCDC_CONVERT) {
+        patch.dcdc = true;
+    }
+#ifdef USE_COMMON_MACRO
+    dev_dbg(sh->sc->dev, "%s: use common macro",__func__);
+    if (sh->cfg.hw_caps & SSV6200_HW_CAP_5GHZ) {
+        INIT_TURISMOC_SYS(patch, AG_BAND_BOTH, cal);
+    } else {
+        INIT_TURISMOC_SYS(patch,G_BAND_ONLY, cal);
+    }
+#else
+    dev_dbg(sh->sc->dev, "%s: Not use common macro",__func__);
+    ret = SSV6XXX_SET_HW_TABLE(sh, ssv6006_turismoC_rf_setting);
+    if (patch.dcdc) {
+        SET_RG_DCDC_MODE(0x0);
+        SET_RG_BUCK_EN_PSM(0x1);
+        SET_RG_DCDC_MODE(0x1);
+        UDELAY(100);
+        SET_RG_BUCK_EN_PSM(0x0);
+    }
+    _update_rf_patch(sh, xtal);
+    SET_RG_EN_IOTADC_160M(0);
+    ssv6006_turismoC_init_PLL(sh);
+    REG32_W(ADR_WIFI_PHY_COMMON_ENABLE_REG, 0);
+    ret = SSV6XXX_SET_HW_TABLE(sh, ssv6006_turismoC_phy_setting);
+    single_band_patch(sh, patch.xtal);
+    SET_CLK_DIGI_SEL( patch.cpu_clk);
+    udelay(1);
+    if (cal->cal_done) {
+        _restore_cal(sh);
+    } else {
+        ssv6006_turismoC_init_fast_cali(sh, cal);
+    }
+#endif
+    if (cal->cal_done) {
+        sh->default_txgain[BAND_2G] = GET_RG_TX_GAIN;
+        sh->default_txgain[BAND_5100] = GET_RG_5G_TX_GAIN_F0;
+        sh->default_txgain[BAND_5500] = GET_RG_5G_TX_GAIN_F1;
+        sh->default_txgain[BAND_5700] = GET_RG_5G_TX_GAIN_F2;
+        sh->default_txgain[BAND_5900] = GET_RG_5G_TX_GAIN_F3;
+    }
+    for (i = 0; i < PADPDBAND; i++) {
+        if ((1 << i) & sh->cfg.disable_dpd) {
+            sh->sc->dpd.dpd_disable[i] = true;
+        }
+    }
+    return ret;
+}
+static bool ssv6006_turismoC_set_rf_enable(struct ssv_hw *sh, bool val)
+{
+    SMAC_REG_SET_BITS(sh, ADR_MODE_REGISTER, 1 << RG_MODE_MANUAL_SFT, RG_MODE_MANUAL_MSK);
+    msleep(1);
+    if (val) {
+        SMAC_REG_SET_BITS(sh, ADR_MODE_REGISTER, 3 << RG_MODE_SFT, RG_MODE_MSK);
+        msleep(1);
+        SMAC_REG_SET_BITS(sh, ADR_MODE_REGISTER, 0 << RG_MODE_MANUAL_SFT, RG_MODE_MANUAL_MSK);
+    } else {
+        SMAC_REG_SET_BITS(sh, ADR_MODE_REGISTER, 0 << RG_MODE_SFT, RG_MODE_MSK);
+    }
+    return true;
+}
+static bool ssv6006_turismoC_dump_phy_reg(struct ssv_hw *sh)
+{
+    u32 regval;
+    int s;
+    ssv_cabrio_reg *raw;
+    struct ssv_cmd_data *cmd_data = &sh->sc->cmd_data;
+    raw = ssv6006_turismoC_phy_setting;
+    snprintf_res(cmd_data, ">> PHY Register Table:");
+    for(s = 0; s < ssv6006_turismoC_phy_tbl_size/sizeof(ssv_cabrio_reg); s++, raw++) {
+        SMAC_REG_READ(sh, raw->address, &regval);
+        snprintf_res(cmd_data, "   ADDR[0x%08x] = 0x%08x",
+                     raw->address, regval);
+    }
+    snprintf_res(cmd_data, ">>PHY Table version: %s", SSV6006_TURISMOC_PHY_TABLE_VER);
+    snprintf_res(cmd_data, "");
+    return 0;
+}
+static bool ssv6006_turismoC_dump_rf_reg(struct ssv_hw *sh)
+{
+    u32 regval;
+    int s;
+    ssv_cabrio_reg *raw;
+    struct ssv_cmd_data *cmd_data = &sh->sc->cmd_data;
+    raw = ssv6006_turismoC_rf_setting;
+    snprintf_res(cmd_data, ">> RF Register Table:");
+    for(s = 0; s < ssv6006_turismoC_rf_tbl_size/sizeof(ssv_cabrio_reg); s++, raw++) {
+        SMAC_REG_READ(sh, raw->address, &regval);
+        snprintf_res(cmd_data, "   ADDR[0x%08x] = 0x%08x",
+                     raw->address, regval);
+    }
+    snprintf_res(cmd_data, ">>RF Table version: %s", SSV6006_TURISMOC_RF_TABLE_VER);
+    snprintf_res(cmd_data, "");
+    return 0;
+}
+static bool ssv6006_turismoC_support_iqk_cmd(struct ssv_hw *sh)
+{
+    return false;
+}
+static void ssv6006_cmd_turismoC_cali(struct ssv_hw *sh, int argc, char *argv[])
+{
+    struct ssv_cmd_data *cmd_data = &sh->sc->cmd_data;
+    struct ssv_softc *sc = sh->sc;
+    struct ieee80211_channel chan;
+    if(!strcmp(argv[1], "do")) {
+        chan.hw_value = sc->hw_chan;
+        sh->cal.cal_done = false;
+        ssv6006_turismoC_init_cali(sh, &sh->cal);
+        HAL_SET_CHANNEL(sc, &chan, sc->hw_chan_type);
+        snprintf_res(cmd_data,"   CALIRATION DONE");
+    } else if(!strcmp(argv[1], "show")) {
+        u32 i, regval = 0, wifi_dc_addr;
+        snprintf_res(cmd_data,"---------2.4G DC Calibration result-----------");
+        for (i = 0; i < 21; i++) {
+            if (i %2 == 0)
+                snprintf_res(cmd_data,"");
+            wifi_dc_addr = ADR_WF_DCOC_IDAC_REGISTER1+ (i << 2);
+            SMAC_REG_READ(sh, wifi_dc_addr, &regval);
+            snprintf_res(cmd_data,"addr %x : val %x, %x,", wifi_dc_addr, regval, sh->cal.rxdc_2g[i]);
+        }
+        snprintf_res(cmd_data,"--------------------------------------------");
+        snprintf_res(cmd_data,"WiFi BW20 RG_WF_RX_ABBCTUNE: %d, %d", GET_RG_WF_RX_ABBCTUNE, sh->cal.rxrc_bw20);
+        snprintf_res(cmd_data,"WiFi BW40 RG_WF_RX_N_ABBCTUNE: %d, %d", GET_RG_WF_N_RX_ABBCTUNE, sh->cal.rxrc_bw40);
+        snprintf_res(cmd_data,"TxDC calibration WiFi 2P4G Tx DAC IOFFSET: %d %d, QOFFSET %d %d",
+                     GET_RG_WF_TX_DAC_IOFFSET, sh->cal.txdc_i_2g, GET_RG_WF_TX_DAC_QOFFSET, sh->cal.txdc_q_2g);
+        snprintf_res(cmd_data,"Tx iq calibration, tx alpha: %d %d, tx theta %d %d",
+                     GET_RG_TX_IQ_2500_ALPHA, sh->cal.txiq_alpha[BAND_2G], GET_RG_TX_IQ_2500_THETA, sh->cal.txiq_theta[BAND_2G]);
+        snprintf_res(cmd_data,"Rx iq calibration, rx alpha: %d %d, rx theta %d %d",
+                     GET_RG_RX_IQ_2500_ALPHA, sh->cal.rxiq_alpha[BAND_2G], GET_RG_RX_IQ_2500_THETA, sh->cal.rxiq_theta[BAND_2G]);
+        if (sh->cfg.hw_caps & SSV6200_HW_CAP_5GHZ) {
+            snprintf_res(cmd_data,"--------------------------------------------");
+            snprintf_res(cmd_data,"--------- 5 G Rx DC Calibration result----------------");
+            for (i = 0; i < 21; i++) {
+                if (i %2 == 0)
+                    snprintf_res(cmd_data,"");
+                wifi_dc_addr = (ADR_5G_DCOC_IDAC_REGISTER1)+ (i << 2);
+                SMAC_REG_READ(sh, wifi_dc_addr, &regval);
+                snprintf_res(cmd_data,"addr %x : val %x, %x,", wifi_dc_addr, regval, sh->cal.rxdc_5g[i]);
+            }
+            snprintf_res(cmd_data,"");
+            snprintf_res(cmd_data,"5G txdc calibration WiFi 5G Tx DAC IOFFSET: %d %d, QOFFSET %d %d",
+                         GET_RG_5G_TX_DAC_IOFFSET, sh->cal.txdc_i_5g, GET_RG_5G_TX_DAC_QOFFSET, sh->cal.txdc_q_5g);
+            snprintf_res(cmd_data,"5G tx iq in memory, tx alpha: %d %d %d %d, tx theta %d %d %d %d",
+                         sh->cal.txiq_alpha[BAND_5100], sh->cal.txiq_alpha[BAND_5500],
+                         sh->cal.txiq_alpha[BAND_5700], sh->cal.txiq_alpha[BAND_5900],
+                         sh->cal.txiq_theta[BAND_5100], sh->cal.txiq_theta[BAND_5500],
+                         sh->cal.txiq_theta[BAND_5700], sh->cal.txiq_theta[BAND_5900]);
+            snprintf_res(cmd_data,"5G tx iq read back, tx alpha: %d %d %d %d, tx theta %d %d %d %d",
+                         GET_RG_TX_IQ_5100_ALPHA, GET_RG_TX_IQ_5500_ALPHA,
+                         GET_RG_TX_IQ_5700_ALPHA, GET_RG_TX_IQ_5900_ALPHA,
+                         GET_RG_TX_IQ_5100_THETA, GET_RG_TX_IQ_5500_THETA,
+                         GET_RG_TX_IQ_5700_THETA, GET_RG_TX_IQ_5900_THETA);
+            snprintf_res(cmd_data,"5G rx iq in memory, rx alpha: %d %d %d %d, rx theta %d %d %d %d",
+                         sh->cal.rxiq_alpha[BAND_5100], sh->cal.rxiq_alpha[BAND_5500],
+                         sh->cal.rxiq_alpha[BAND_5700], sh->cal.rxiq_alpha[BAND_5900],
+                         sh->cal.rxiq_theta[BAND_5100], sh->cal.rxiq_theta[BAND_5500],
+                         sh->cal.rxiq_theta[BAND_5700], sh->cal.rxiq_theta[BAND_5900]);
+            snprintf_res(cmd_data,"5G rx iq read back, rx alpha: %d %d %d %d, rx theta %d %d %d %d",
+                         GET_RG_RX_IQ_5100_ALPHA, GET_RG_RX_IQ_5500_ALPHA,
+                         GET_RG_RX_IQ_5700_ALPHA, GET_RG_RX_IQ_5900_ALPHA,
+                         GET_RG_RX_IQ_5100_THETA, GET_RG_RX_IQ_5500_THETA,
+                         GET_RG_RX_IQ_5700_THETA, GET_RG_RX_IQ_5900_THETA);
+        }
+    } else if(!strcmp(argv[1], "restore")) {
+        _restore_cal(sh);
+        snprintf_res(cmd_data, " Restore calibration result done!");
+    } else if(!strcmp(argv[1], "dpd")) {
+        if(!strcmp(argv[2], "show")) {
+            int pa_band;
+            snprintf_res(cmd_data, " DPD result: ");
+            for (pa_band = 0; pa_band < PADPDBAND; pa_band++) {
+                u32 regval;
+                switch (pa_band) {
+                case 0:
+                    snprintf_res(cmd_data,"\t 2G       channel <= 14 ");
+                    break;
+                case 1:
+                    snprintf_res(cmd_data,"\t 5G       channel <  36");
+                    break;
+                case 2:
+                    snprintf_res(cmd_data,"\t 5G 36 <= channel < 100");
+                    break;
+                case 3:
+                    snprintf_res(cmd_data,"\t 5G 100<= channel < 140");
+                    break;
+                case 4:
+                    snprintf_res(cmd_data,"\t 5G 140<= channel");
+                    break;
+                default:
+                    break;
+                }
+                if (pa_band == sc->dpd.current_band) {
+                    snprintf_res(cmd_data,":current band");
+                }
+                snprintf_res(cmd_data,"");
+                if (sc->dpd.dpd_done[pa_band]) {
+                    int i;
+                    snprintf_res(cmd_data,"\t\tam_am:");
+                    for (i = 0 ; i < MAX_PADPD_TONE/2; i ++) {
+                        if (i %4 == 0)
+                            snprintf_res(cmd_data,"\t\t");
+                        snprintf_res(cmd_data, "%03d %03d ", sc->dpd.val[pa_band].am[i] & 0xffff,
+                                     (sc->dpd.val[pa_band].am[i] >>16) & 0xffff);
+                    }
+                    snprintf_res(cmd_data,"\t\tread back bank%d am_am:", pa_band);
+                    for (i = 0 ; i < MAX_PADPD_TONE/2; i ++) {
+                        if (i %4 == 0)
+                            snprintf_res(cmd_data,"\t\t");
+                        regval = REG32_R(padpd_am_addr_table[pa_band][i]);
+                        snprintf_res(cmd_data, "%03d %03d ", regval & 0xffff,
+                                     (regval >>16) & 0xffff);
+                    }
+                    snprintf_res(cmd_data,"");
+                } else {
+                    snprintf_res(cmd_data,"\t\t DPD result not available");
+                }
+            }
+        } else if(!strcmp(argv[2], "enable")) {
+            sc->dpd.dpd_disable[sc->dpd.current_band] = false;
+            SET_RG_DPD_AM_EN(1);
+            SET_RG_TXGAIN_PHYCTRL(0);
+            snprintf_res(cmd_data,"enable DPD");
+        } else if(!strcmp(argv[2], "disable")) {
+            sc->dpd.dpd_disable[sc->dpd.current_band] = true;
+            SET_RG_DPD_AM_EN(0);
+            SET_RG_TXGAIN_PHYCTRL(0);
+            snprintf_res(cmd_data,"disable DPD");
+        } else if(!strcmp(argv[2], "do")) {
+            int pa_band = 0, ch = sc->hw_chan;
+            struct ssv6006_padpd *dpd = &sc->dpd;
+            int online_reset_bk;
+            online_reset_bk =sc->sh->cfg.online_reset;
+            sc->sh->cfg.online_reset &= (~ONLINE_RESET_ENABLE);
+            pa_band = ssv6006_get_pa_band(ch);
+            dpd->dpd_done[pa_band] = false;
+            sh->sc->dpd.dpd_disable[pa_band] = false;
+            chan.hw_value = sc->hw_chan;
+            HCI_PAUSE(sc->sh, (TXQ_EDCA_0|TXQ_EDCA_1|TXQ_EDCA_2|TXQ_EDCA_3| TXQ_MGMT));
+            SET_RG_SOFT_RST_N_11B_RX(0);
+            SET_RG_SOFT_RST_N_11GN_RX(0);
+#ifdef USE_COMMON_MACRO
+            CHECK_PADPD(dpd, ch);
+#else
+            pa_band = ssv6006_get_pa_band(ch);
+            _check_padpd(sh, dpd, pa_band);
+#endif
+            HAL_SET_CHANNEL(sc, &chan, sc->hw_chan_type);
+            sc->sh->cfg.online_reset = online_reset_bk;
+            SET_RG_SOFT_RST_N_11B_RX(1);
+            SET_RG_SOFT_RST_N_11GN_RX(1);
+            HCI_RESUME(sc->sh, (TXQ_EDCA_0|TXQ_EDCA_1|TXQ_EDCA_2|TXQ_EDCA_3| TXQ_MGMT));
+            snprintf_res(cmd_data,"DPD done");
+        } else if(!strcmp(argv[2], "restore")) {
+            int pa_band = 0, ch = sc->hw_chan;
+            struct ssv6006_padpd *dpd = &sc->dpd;
+            pa_band = ssv6006_get_pa_band(ch);
+            TU_RESTORE_DPD(dpd);
+            snprintf_res(cmd_data, " Restore current band dpd result done!");
+        } else {
+            snprintf_res(cmd_data," cali [do|show|restore|dpd(do|show|enable|disable|restore)] ");
+        }
+    } else if(!strcmp(argv[1], "iqk")) {
+        if(!strcmp(argv[2], "do")) {
+            chan.hw_value = sc->hw_chan;
+            ssv6006_turismoC_init_iqk(sh, &sh->cal);
+            HAL_SET_CHANNEL(sc, &chan, sc->hw_chan_type);
+            snprintf_res(cmd_data,"   CALIRATION DONE");
+        }
+    } else {
+        snprintf_res(cmd_data," cali [do|show|restore|dpd(show|enable|disable)] ");
+    }
+}
+static void ssv6006c_cmd_lpbk_setup_env_sec_talbe(struct ssv_hw *sh)
+{
+    int i, address = 0;
+    u32 temp;
+    u32 sec_key_tbl_base = sh->hw_sec_key[0];
+    u32 sec_key_tbl = sec_key_tbl_base;
+    u8 sec_tbl[] = {
+        0x01, 0x03, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+        0x58, 0xce, 0x11, 0x7c, 0x54, 0x74, 0x37, 0x41, 0xc7, 0x5d, 0xc4, 0x5f,
+        0x53, 0x90, 0xe8, 0x34, 0x87, 0xbb, 0xdd, 0x0a, 0x7f, 0x6c, 0x52, 0x03,
+        0x87, 0xbb, 0xdd, 0x0a, 0x7f, 0x6c, 0x52, 0x03, 0x59, 0xce, 0x11, 0x7c,
+        0x54, 0x74, 0x37, 0x41, 0xc7, 0x5d, 0xc4, 0x5f, 0x53, 0x90, 0xe8, 0x34,
+        0x88, 0xbb, 0xdd, 0x0a, 0x7f, 0x6c, 0x52, 0x03, 0x88, 0xbb, 0xdd, 0x0a,
+        0x7f, 0x6c, 0x52, 0x03, 0x5a, 0xce, 0x11, 0x7c, 0x54, 0x74, 0x37, 0x41,
+        0xc7, 0x5d, 0xc4, 0x5f, 0x53, 0x90, 0xe8, 0x34, 0x89, 0xbb, 0xdd, 0x0a,
+        0x7f, 0x6c, 0x52, 0x03, 0x89, 0xbb, 0xdd, 0x0a, 0x7f, 0x6c, 0x52, 0x03,
+        0x5a, 0xce, 0x11, 0x7c, 0x54, 0x74, 0x37, 0x41, 0xc7, 0x5d, 0xc4, 0x5f,
+        0x53, 0x90, 0xe8, 0x34, 0x89, 0xbb, 0xdd, 0x0a, 0x7f, 0x6c, 0x52, 0x03,
+        0x89, 0xbb, 0xdd, 0x0a, 0x7f, 0x6c, 0x52, 0x03,
+        0x01, 0x03, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+        0x58, 0xce, 0x11, 0x7c, 0x54, 0x74, 0x37, 0x41, 0xc7, 0x5d, 0xc4, 0x5f,
+        0x53, 0x90, 0xe8, 0x34, 0x87, 0xbb, 0xdd, 0x0a, 0x7f, 0x6c, 0x52, 0x03,
+        0x87, 0xbb, 0xdd, 0x0a, 0x7f, 0x6c, 0x52, 0x03, 0x59, 0xce, 0x11, 0x7c,
+        0x54, 0x74, 0x37, 0x41, 0xc7, 0x5d, 0xc4, 0x5f, 0x53, 0x90, 0xe8, 0x34,
+        0x88, 0xbb, 0xdd, 0x0a, 0x7f, 0x6c, 0x52, 0x03, 0x88, 0xbb, 0xdd, 0x0a,
+        0x7f, 0x6c, 0x52, 0x03, 0x5a, 0xce, 0x11, 0x7c, 0x54, 0x74, 0x37, 0x41,
+        0xc7, 0x5d, 0xc4, 0x5f, 0x53, 0x90, 0xe8, 0x34, 0x89, 0xbb, 0xdd, 0x0a,
+        0x7f, 0x6c, 0x52, 0x03, 0x89, 0xbb, 0xdd, 0x0a, 0x7f, 0x6c, 0x52, 0x03,
+        0x5a, 0xce, 0x11, 0x7c, 0x54, 0x74, 0x37, 0x41, 0xc7, 0x5d, 0xc4, 0x5f,
+        0x53, 0x90, 0xe8, 0x34, 0x89, 0xbb, 0xdd, 0x0a, 0x7f, 0x6c, 0x52, 0x03,
+        0x89, 0xbb, 0xdd, 0x0a, 0x7f, 0x6c, 0x52, 0x03,
+        0x00, 0x01, 0x00, 0x00, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11,
+        0x5e, 0xce, 0x11, 0x7c, 0x54, 0x74, 0x37, 0x41, 0xc7, 0x5d, 0xc4, 0x5f,
+        0x53, 0x90, 0xe8, 0x34, 0x8d, 0xbb, 0xdd, 0x0a, 0x7f, 0x6c, 0x52, 0x03,
+        0x8d, 0xbb, 0xdd, 0x0a, 0x7f, 0x6c, 0x52, 0x03,
+        0x00, 0x02, 0x00, 0x00, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11,
+        0x5e, 0xce, 0x11, 0x7c, 0x54, 0x74, 0x37, 0x41, 0xc7, 0x5d, 0xc4, 0x5f,
+        0x53, 0x90, 0xe8, 0x34, 0x8d, 0xbb, 0xdd, 0x0a, 0x7f, 0x6c, 0x52, 0x03,
+        0x8d, 0xbb, 0xdd, 0x0a, 0x7f, 0x6c, 0x52, 0x03,
+        0x00, 0x03, 0x00, 0x00, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11,
+        0x5e, 0xce, 0x11, 0x7c, 0x54, 0x74, 0x37, 0x41, 0xc7, 0x5d, 0xc4, 0x5f,
+        0x53, 0x90, 0xe8, 0x34, 0x8d, 0xbb, 0xdd, 0x0a, 0x7f, 0x6c, 0x52, 0x03,
+        0x8d, 0xbb, 0xdd, 0x0a, 0x7f, 0x6c, 0x52, 0x03,
+        0x00, 0x04, 0x00, 0x00, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11,
+        0x5e, 0xce, 0x11, 0x7c, 0x54, 0x74, 0x37, 0x41, 0xc7, 0x5d, 0xc4, 0x5f,
+        0x53, 0x90, 0xe8, 0x34, 0x8d, 0xbb, 0xdd, 0x0a, 0x7f, 0x6c, 0x52, 0x03,
+        0x8d, 0xbb, 0xdd, 0x0a, 0x7f, 0x6c, 0x52, 0x03,
+    };
+    address = sec_key_tbl;
+    for (i=0; i < sizeof(sec_tbl); i+=4) {
+        memcpy(&temp, &sec_tbl[i], sizeof(u32));
+        SMAC_REG_WRITE(sh, address, temp);
+        address += 4;
+    }
+}
+static void ssv6006c_cmd_loopback_setup_env(struct ssv_hw *sh)
+{
+    u32 mac0, mac1;
+    struct ieee80211_channel chan;
+    SSV_PHY_ENABLE(sh, 1);
+    SET_RX_2_HOST(1);
+    SET_TX_INFO_SIZE(80);
+    SET_RX_INFO_SIZE(80);
+    SET_LUT_SEL_V2(1);
+    ssv6006c_cmd_lpbk_setup_env_sec_talbe(sh);
+    mac0 = GET_STA_MAC_31_0;
+    mac1 = GET_STA_MAC_47_32;
+    SET_BSSID_31_0(mac0);
+    SET_BSSID_47_32(mac1);
+    SET_PEER_MAC0_31_0(mac0);
+    SET_PEER_MAC0_47_32(mac1);
+    SET_VALID0(1);
+    HAL_SET_RX_FLOW(sh, RX_DATA_FLOW, RX_CIPHER_MIC_HCI);
+    HAL_SET_RX_FLOW(sh, RX_MGMT_FLOW, RX_HCI);
+    HAL_SET_RX_FLOW(sh, RX_CTRL_FLOW, RX_HCI);
+    switch (sh->cfg.lpbk_type) {
+    case SSV6006_CMD_LPBK_TYPE_MAC:
+        SET_TX_PKT_SEND_TO_RX(0);
+        SET_RG_MAC_LPBK(1);
+        SET_MTX_MTX2PHY_SLOW(1);
+        SET_MTX_M2M_SLOW_PRD(3);
+        SET_RG_PMDLBK(0);
+        break;
+    case SSV6006_CMD_LPBK_TYPE_PHY:
+        SET_TX_PKT_SEND_TO_RX(0);
+        SET_RG_MAC_LPBK(0);
+        SET_MTX_MTX2PHY_SLOW(0);
+        SET_MTX_M2M_SLOW_PRD(0);
+        SET_RG_PMDLBK(1);
+        break;
+    case SSV6006_CMD_LPBK_TYPE_HCI:
+        SSV_PHY_ENABLE(sh, 0);
+        SET_TX_PKT_SEND_TO_RX(1);
+        SET_RG_MAC_LPBK(0);
+        SET_MTX_MTX2PHY_SLOW(0);
+        SET_MTX_M2M_SLOW_PRD(0);
+        SET_RG_PMDLBK(0);
+        break;
+    case SSV6006_CMD_LPBK_TYPE_2GRF:
+        memset(&chan, 0, sizeof( struct ieee80211_channel));
+        chan.hw_value = 6;
+        HAL_SET_CHANNEL(sh->sc, &chan, NL80211_CHAN_HT20);
+        SET_RG_TXGAIN_PHYCTRL(1);
+        SET_RG_BW_MANUAL(1);
+        SET_RG_BW_HT40(0);
+        SET_RG_TX_GAIN_DPDCAL(0x0c);
+        SET_RG_PGAG_DPDCAL(0x3);
+        SET_RG_RFG_DPDCAL(0);
+        SET_RG_BB_SIG_EN(0x1);
+        SET_RG_MODE_MANUAL(0x1);
+        SET_RG_MODE(1);
+        SET_RG_CAL_INDEX(7);
+        SSV_PHY_ENABLE(sh, 0);
+        SET_RG_LBK_DIG_SEL(0);
+        SET_RG_LBK_ANA_PATH(1);
+        SET_RG_PMDLBK(1);
+        SET_RG_SYSTEM_BW(0);
+        SET_RG_PRIMARY_CH_SIDE(1);
+        SSV_PHY_ENABLE(sh, 1);
+        break;
+    case SSV6006_CMD_LPBK_TYPE_5GRF:
+        memset(&chan, 0, sizeof( struct ieee80211_channel));
+        chan.hw_value = 100;
+        HAL_SET_CHANNEL(sh->sc, &chan, NL80211_CHAN_HT20);
+        SET_RG_TXGAIN_PHYCTRL(0x1);
+        SET_RG_BW_MANUAL(0x1);
+        SET_RG_BW_HT40(0);
+        SET_RG_5G_TX_GAIN_DPDCAL(0xc);
+        SET_RG_5G_PGAG_DPDCAL(0x3);
+        SET_RG_5G_RFG_DPDCAL(0);
+        SET_RG_BB_SIG_EN(0x1);
+        SET_RG_MODE_MANUAL(1);
+        SET_RG_MODE(1);
+        SET_RG_CAL_INDEX(15);
+        SSV_PHY_ENABLE(sh, 0);
+        SET_RG_LBK_DIG_SEL(0);
+        SET_RG_LBK_ANA_PATH(1);
+        SET_RG_PMDLBK(1);
+        SET_RG_SYSTEM_BW(0);
+        SET_RG_PRIMARY_CH_SIDE(1);
+        SSV_PHY_ENABLE(sh, 1);
+        break;
+    default:
+        printk("LPBK invalid setting!!!");
+        break;
+    }
+    msleep(10);
+    sh->sc->lpbk_enable = true;
+}
+static void ssv6006_cmd_turismoC_loopback(struct ssv_hw *sh, int argc, char *argv[])
+{
+    struct ssv_cmd_data *cmd_data = &sh->sc->cmd_data;
+    char *lpbk_types[] = {"phy", "mac", "hci", "2grf", "5grf"};
+    char *lpbk_secs[] = {"open/security", "wep64", "wep128", "tkip", "aes", "open"};
+    char *endp;
+    int val;
+    if (argc < 2) {
+        snprintf_res(cmd_data, " lpbk [show|set|start]");
+        return;
+    }
+    if (!strcmp(argv[1], "show")) {
+        snprintf_res(cmd_data, " lpbk parameters for ssv6006");
+        snprintf_res(cmd_data, " lpbk packet count    = %d", (!sh->cfg.lpbk_pkt_cnt) ? 10: sh->cfg.lpbk_pkt_cnt);
+        snprintf_res(cmd_data, " lpbk type            = %s", lpbk_types[sh->cfg.lpbk_type]);
+        snprintf_res(cmd_data, " lpbk security        = %s", lpbk_secs[sh->cfg.lpbk_sec]);
+        snprintf_res(cmd_data, " lpbk fixed rate      = %s", (!sh->cfg.lpbk_mode ? "all rates" : "sample rate"));
+    } else if (!strcmp(argv[1], "set")) {
+        if (argc == 4) {
+            val = simple_strtoul(argv[3], &endp, 0);
+            snprintf_res(cmd_data, " set lpbk %s to %d", argv[2], val);
+            if (!strcmp(argv[2], "pkt_cnt")) {
+                sh->cfg.lpbk_pkt_cnt = val;
+            } else if (!strcmp(argv[2], "type")) {
+                sh->cfg.lpbk_type = (val >= MAX_SSV6006_CMD_LPBK_TYPE) ? 0 : val;
+            } else if (!strcmp(argv[2], "security")) {
+                sh->cfg.lpbk_sec = (val >= MAX_SSV6006_CMD_LPBK_SEC) ? 0 : val;
+            } else if (!strcmp(argv[2], "fixed_rate")) {
+                sh->cfg.lpbk_mode = (val > 0) ? 1 : 0;
+            } else {
+                snprintf_res(cmd_data, " lpbk set [env_setup|pkt_cnt|type|security|fixed_rate]");
+            }
+        } else {
+            snprintf_res(cmd_data, " lpbk set [env_setup|pkt_cnt|type|security|fixed_rate]");
+        }
+    } else if (!strcmp(argv[1], "start")) {
+        HAL_CMD_LOOPBACK_SETUP_ENV(sh);
+        HAL_CMD_LOOPBACK_START(sh);
+    } else {
+        snprintf_res(cmd_data, " lpbk [show|set|start]");
+    }
+}
+static void ssv6006_cmd_turismoC_txgen(struct ssv_hw *sh)
+{
+    struct sk_buff *skb = NULL;
+    int len = (int) sizeof(pkt1614) ;
+    unsigned char *data = NULL;
+    struct ssv6006_tx_desc *tx_desc;
+    struct ssv_softc *sc = sh->sc;
+    skb = ssv_skb_alloc(sc, len);
+    if (!skb)
+        goto out;
+    data = skb_put(skb, len);
+    memcpy(data, pkt1614, len);
+    tx_desc = (struct ssv6006_tx_desc *)data;
+    tx_desc->drate_idx0 = sc->rf_rc;
+    SET_RG_TXD_SEL(0);
+    SET_RG_TX_START(0);
+    HCI_SEND_CMD(sc->sh, skb);
+out:
+    if (skb)
+        ssv_skb_free(sc, skb);
+}
+static void ssv6006_cmd_turismoC_rf(struct ssv_hw *sh, int argc, char *argv[])
+{
+    struct ssv_cmd_data *cmd_data = &sh->sc->cmd_data;
+    u32 regval = 0;
+    char *endp;
+    struct ssv_softc *sc = sh->sc;
+    int ch = sc->hw_chan;
+    int pa_band =0;
+    unsigned char rate_tbl[] = {
+        0x00,0x01,0x02,0x03,
+        0x00,0x12,0x13,
+        0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,
+        0xc0,0xc1,0xc2,0xc3,0xc4,0xc5,0xc6,0xc7,
+        0xd0,0xd1,0xd2,0xd3,0xd4,0xd5,0xd6,0xd7,
+        0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,
+        0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,
+    };
+#define SIZE_RATE_TBL (sizeof(rate_tbl) / sizeof((rate_tbl)[0]))
+    pa_band = ssv6006_get_pa_band(ch);
+    if ( argc < 2) goto out;
+    if(!strcmp(argv[1], "bbscale")) {
+        if (argc == 4) {
+            regval = simple_strtoul(argv[3], &endp, 0);
+            snprintf_res(cmd_data,"Set bbscale to 0x%x", regval);
+            if (!strcmp(argv[2], "ht40")) {
+                REG32_W(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_3, regval);
+            } else if(!strcmp(argv[2], "ht20")) {
+                REG32_W(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_2, regval);
+            } else if(!strcmp(argv[2], "g")) {
+                REG32_W(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_1, regval);
+            } else if(!strcmp(argv[2], "b")) {
+                SET_RG_BB_SCALE_BARKER_CCK(regval);
+            } else if(!strcmp(argv[2], "dpd")) {
+                switch (pa_band) {
+                case BAND_2G:
+                    SET_RG_DPD_BB_SCALE_2500(regval);
+                    break;
+                case BAND_5100:
+                    SET_RG_DPD_BB_SCALE_5100(regval);
+                    break;
+                case BAND_5500:
+                    SET_RG_DPD_BB_SCALE_5500(regval);
+                    break;
+                case BAND_5700:
+                    SET_RG_DPD_BB_SCALE_5700(regval);
+                    break;
+                case BAND_5900:
+                    SET_RG_DPD_BB_SCALE_5900(regval);
+                    break;
+                default:
+                    break;
+                }
+            }
+            return;
+        } else {
+            snprintf_res(cmd_data,"./cli rf bbscale ht40|ht20|g|b|dpd [value]");
+            return;
+        }
+    } else if(!strcmp(argv[1], "ack")) {
+        if (argc == 3) {
+            if (!strcmp(argv[2], "disable")) {
+                SET_RG_TXD_SEL(1);
+                snprintf_res(cmd_data," set %s %s", argv[1], argv[2]);
+            } else if (!strcmp(argv[2], "enable")) {
+                SET_RG_TXD_SEL(0);
+                snprintf_res(cmd_data," set %s %s", argv[1], argv[2]);
+            }
+        } else {
+            snprintf_res(cmd_data,"\t incorrect set ack format");
+        }
+        return;
+    } else if(!strcmp(argv[1], "ifs")) {
+        if (argc == 3) {
+            regval = simple_strtoul(argv[2], &endp, 0);
+            SET_RG_IFS_TIME((regval & 0x3f));
+            SET_RG_IFS_TIME_EXT((regval >> 6));
+        }
+        snprintf_res(cmd_data," set ifs to %d us", regval);
+        return;
+    } else if(!strcmp(argv[1], "rate")) {
+        if (argc == 3) {
+            regval = simple_strtoul(argv[2], &endp, 0);
+            sc->rf_rc = 0;
+            if ((regval != 4) && (regval < SIZE_RATE_TBL)) {
+                sc->rf_rc = rate_tbl[regval];
+                switch ((sc->rf_rc & SSV6006RC_PHY_MODE_MSK) >> SSV6006RC_PHY_MODE_SFT) {
+                case 0:
+                    SET_RG_PKT_MODE(0);
+                    break;
+                case 2:
+                    SET_RG_PKT_MODE(1);
+                    break;
+                case 3:
+                    SET_RG_PKT_MODE(2);
+                    break;
+                default:
+                    snprintf_res(cmd_data,"\t %s", "Invalid phy mode");
+                    break;
+                }
+                SET_RG_CH_BW(((sc->rf_rc & SSV6006RC_20_40_MSK) >> SSV6006RC_20_40_SFT)) ;
+                SET_RG_SHORTGI((sc->rf_rc & SSV6006RC_LONG_SHORT_MSK) >> SSV6006RC_LONG_SHORT_SFT);
+                SET_RG_RATE((sc->rf_rc & SSV6006RC_RATE_MSK) >> SSV6006RC_RATE_SFT);
+                snprintf_res(cmd_data,"Set rate to 0x%x", sc->rf_rc);
+                return;
+            } else {
+                snprintf_res(cmd_data,"Not support rf rate index %d", regval);
+                return;
+            }
+        } else {
+            snprintf_res(cmd_data,"\t Incorrect rf rate set format");
+            return;
+        }
+    } else if(!strcmp(argv[1], "freq")) {
+        if (argc == 3) {
+            regval = simple_strtoul(argv[2], &endp, 0);
+            snprintf_res(cmd_data,"Set cbanki/cbanko to 0x%x", regval);
+            SET_RG_XO_CBANKI(regval);
+            SET_RG_XO_CBANKO(regval);
+            return;
+        } else {
+            snprintf_res(cmd_data,"./cli rf freq [value]");
+            return;
+        }
+    } else if(!strcmp(argv[1], "rfreq")) {
+        if (argc == 2) {
+            snprintf_res(cmd_data,"Get freq 0x%x/0x%x", GET_RG_XO_CBANKI, GET_RG_XO_CBANKO);
+            return;
+        } else {
+            snprintf_res(cmd_data,"./cli rf rfreq");
+            return;
+        }
+    } else if(!strcmp(argv[1], "greentx")) {
+        if (argc == 3) {
+            if(!strcmp(argv[2], "enable")) {
+                sh->cfg.greentx |= GT_ENABLE;
+                sc->gt_channel = sc->hw_chan;
+                sc->gt_enabled = true;
+                sc->green_pwr = 0xff;
+                HAL_UPDATE_RF_PWR(sc);
+                snprintf_res(cmd_data,"\t Green Tx enabled, start attenuation from -%d dB"
+                             , sh->cfg.greentx & GT_PWR_START_MASK);
+            } else if(!strcmp(argv[2], "disable")) {
+                sh->cfg.greentx &= (~GT_ENABLE);
+                sc->dpd.pwr_mode = NORMAL_PWR;
+                sc->green_pwr = 0xff;
+                HAL_UPDATE_RF_PWR(sc);
+                sc->gt_enabled = false;
+                snprintf_res(cmd_data,"\t Green Tx disabled");
+            }
+        } else if ((argc == 4) && (!strcmp(argv[2], "dbg"))) {
+            if(!strcmp(argv[3], "enable")) {
+                sh->cfg.greentx |= GT_DBG;
+                snprintf_res(cmd_data,"\t Green Tx Debug enable");
+            } else if(!strcmp(argv[3], "disable")) {
+                sh->cfg.greentx &= (~GT_DBG);
+                snprintf_res(cmd_data,"\t Green Tx debug disabled");
+            }
+        } else if ((argc == 4) && (!strcmp(argv[2], "stepsize"))) {
+            regval = simple_strtoul(argv[3], &endp, 0);
+            sh->cfg.gt_stepsize = regval;
+            snprintf_res(cmd_data,"\t Green Tx set step size to %d", regval);
+        } else if ((argc == 4) && (!strcmp(argv[2], "max_atten"))) {
+            regval = simple_strtoul(argv[3], &endp, 0);
+            sh->cfg.gt_max_attenuation = regval;
+            snprintf_res(cmd_data,"\t Green Tx set gt_max_attenuation  to %d", regval);
+        } else {
+            snprintf_res(cmd_data,"\t Incorrect rf greentx format");
+        }
+        return;
+    } else if (!strcmp(argv[1], "rgreentx")) {
+        snprintf_res(cmd_data," cfg.greentx 0x%x, Tx Gain : %d %d %d %d %d",
+                     sh->cfg.greentx, GET_RG_TX_GAIN, GET_RG_5G_TX_GAIN_F0,
+                     GET_RG_5G_TX_GAIN_F1, GET_RG_5G_TX_GAIN_F2, GET_RG_5G_TX_GAIN_F3);
+        snprintf_res(cmd_data," step size %d, max attenuaton %d",
+                     sh->cfg.gt_stepsize, sh->cfg.gt_max_attenuation);
+        return;
+    } else if(!strcmp(argv[1], "rssi")) {
+        snprintf_res(cmd_data," ofdm RSSI -%d, B mode RSSI -%d",
+                     GET_RO_11GN_RCPI, GET_RO_11B_RCPI);
+        return;
+    } else if(!strcmp(argv[1], "sar")) {
+        SET_RG_SARADC_THERMAL(0);
+        SET_RG_EN_SARADC(0);
+        SET_RG_SARADC_THERMAL(1);
+        SET_RG_EN_SARADC(1);
+        do {
+            if (GET_SAR_ADC_FSM_RDY)
+                break;
+        } while(1);
+        SET_RG_SARADC_THERMAL(0);
+        SET_RG_EN_SARADC(0);
+        snprintf_res(cmd_data,"\tuSarCode[%d] ", GET_DB_DA_SARADC_BIT);
+        return;
+    } else if (!strcmp(argv[1], "phy_txgen")) {
+        if (argc == 3) {
+            SET_RG_TX_START(0);
+            regval = simple_strtoul(argv[2], &endp, 0);
+            SET_RG_LENGTH(1500);
+            SET_RG_TX_CNT_TARGET(regval);
+            SET_RG_TXD_SEL(1);
+            SET_RG_TX_START(1);
+        }
+        regval = (GET_RG_IFS_TIME)+ (GET_RG_IFS_TIME_EXT << 6);
+        snprintf_res(cmd_data,"\t phy_txgen triggered!! ifs %d us", regval);
+        return;
+    } else if(!strcmp(argv[1], "block")) {
+        sc->sc_flags |= SC_OP_BLOCK_CNTL;
+        sc->sc_flags |= SC_OP_CHAN_FIXED;
+        snprintf_res(cmd_data,"\t block control form system");
+        return;
+    } else if(!strcmp(argv[1], "unblock")) {
+        sc->sc_flags &= ~SC_OP_BLOCK_CNTL;
+        sc->sc_flags &= ~SC_OP_CHAN_FIXED;
+        SET_RG_TXD_SEL(0);
+        SET_RG_TX_START(0);
+        snprintf_res(cmd_data,"\t unblock control form system");
+        return;
+    } else if(!strcmp(argv[1], "count")) {
+        if (argc == 3) {
+            int count = 0, err = 0, integer= 0, point = 0;
+            bool valid =false;
+            if (!strcmp(argv[2], "0")) {
+                count = GET_RO_11B_PACKET_CNT;
+                err = GET_RO_11B_PACKET_ERR_CNT;
+                valid = true;
+            } else if(!strcmp(argv[2], "1")) {
+                count = GET_RO_11GN_PACKET_CNT;
+                err = GET_RO_11GN_PACKET_ERR_CNT;
+                valid = true;
+            }
+            if (count != 0) {
+                integer = (err * 100)/count;
+                point = ((err*10000)/count)%100;
+            }
+            if (valid) {
+                snprintf_res(cmd_data,"count = %d", count);
+                snprintf_res(cmd_data,"err = %d", err);
+                snprintf_res(cmd_data,"err_rate = %01d.%02d%", integer, point);
+                return;
+            }
+        }
+        snprintf_res(cmd_data,"\t./cli rf count 0|1");
+        return;
+    } else {
+        snprintf_res(cmd_data,
+                     "\t./cli rf phy_txgen|block|unblock|count|ack|freq|rfreq|sar|rssi|rgreentx|greentx|rate|bbscale|ifs");
+        return;
+    }
+out:
+    snprintf_res(cmd_data,"\t Current RF tool settings: ch %d, pa_band %d", ch, pa_band);
+    snprintf_res(cmd_data,"\t bbscale:");
+    if (sc->sc_flags && SC_OP_BLOCK_CNTL) {
+        snprintf_res(cmd_data,"\t system control is blocked");
+    } else {
+        snprintf_res(cmd_data,"\t WARNING system control is not blocked");
+    }
+    snprintf_res(cmd_data,"\t\t HT40 0x%08x, HT20 0x%08x, Legacy 0x%08x, B 0x%02x",
+                 REG32(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_3), REG32(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_2),
+                 REG32(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_1), GET_RG_BB_SCALE_BARKER_CCK);
+    switch (pa_band) {
+    case BAND_2G:
+        regval = GET_RG_DPD_BB_SCALE_2500;
+        break;
+    case BAND_5100:
+        regval = GET_RG_DPD_BB_SCALE_5100;
+        break;
+    case BAND_5500:
+        regval = GET_RG_DPD_BB_SCALE_5500;
+        break;
+    case BAND_5700:
+        regval = GET_RG_DPD_BB_SCALE_5700;
+        break;
+    case BAND_5900:
+        regval = GET_RG_DPD_BB_SCALE_5900;
+        break;
+    default:
+        break;
+    }
+    snprintf_res(cmd_data,"\t current band dpd bbscale: 0x%x", regval);
+    snprintf_res(cmd_data,"\t cbank:");
+    snprintf_res(cmd_data,"\t\t CBANKI %d, CBANKO %d", GET_RG_XO_CBANKI, GET_RG_XO_CBANKO);
+    snprintf_res(cmd_data,"\t tx gen rate: 0x%x", sc->rf_rc);
+    snprintf_res(cmd_data,"\t\t phy mode:");
+    switch ((sc->rf_rc & SSV6006RC_PHY_MODE_MSK) >> SSV6006RC_PHY_MODE_SFT) {
+    case 0:
+        snprintf_res(cmd_data,"\t %s", "B");
+        break;
+    case 2:
+        snprintf_res(cmd_data,"\t %s", "A/G");
+        break;
+    case 3:
+        snprintf_res(cmd_data,"\t %s", "N");
+        break;
+    default:
+        snprintf_res(cmd_data,"\t %s", "Invalid");
+        break;
+    }
+    snprintf_res(cmd_data,"\t\t HT40/HT20:\t %s",
+                 ((sc->rf_rc & SSV6006RC_20_40_MSK) >> SSV6006RC_20_40_SFT) ? "HT40":"HT20") ;
+    snprintf_res(cmd_data,"\t\t SHORT/LONG:\t %s",
+                 ((sc->rf_rc & SSV6006RC_LONG_SHORT_MSK) >> SSV6006RC_LONG_SHORT_SFT) ?"short":"long") ;
+    snprintf_res(cmd_data,"\t\t rate index:\t %d", (sc->rf_rc & SSV6006RC_RATE_MSK) >> SSV6006RC_RATE_SFT) ;
+}
+static void _set_tx_pwr(struct ssv_softc *sc, u32 pa_band, u32 txpwr)
+{
+    struct ssv_hw *sh = sc->sh;
+    switch (pa_band) {
+    case 0:
+        SET_RG_TX_GAIN(txpwr);
+        break;
+    case 1:
+        SET_RG_5G_TX_GAIN_F0(txpwr);
+        break;
+    case 2:
+        SET_RG_5G_TX_GAIN_F1(txpwr);
+        break;
+    case 3:
+        SET_RG_5G_TX_GAIN_F2(txpwr);
+        break;
+    case 4:
+        SET_RG_5G_TX_GAIN_F3(txpwr);
+        break;
+    default:
+        break;
+    }
+    if (sh->cfg.greentx & GT_DBG)
+        printk("update tx power %x  to pa_band %d", txpwr, pa_band);
+}
+void ssv6006_turismoC_update_rf_pwr(struct ssv_softc *sc)
+{
+    u32 pa_band, gt_pa_band;
+    u32 txpwr;
+    struct ssv_hw *sh = sc->sh;
+    if (!(sc->gt_enabled))
+        return;
+    pa_band = ssv6006_get_pa_band(sc->hw_chan);
+    gt_pa_band = ssv6006_get_pa_band(sc->gt_channel);
+    if (pa_band != gt_pa_band)
+        return;
+    txpwr = sh->default_txgain[pa_band];
+    if (sc->hw_chan == sc->gt_channel) {
+        if (sc->green_pwr == 0xff) {
+            sc->green_pwr = txpwr;
+            sc->default_pwr = txpwr;
+        }
+        if (sc->dpd.pwr_mode != NORMAL_PWR) {
+            if (txpwr < sc->green_pwr )
+                txpwr = sc->green_pwr;
+        }
+    }
+    if (txpwr != sc->current_pwr)
+        sc->current_pwr = txpwr;
+    else
+        return;
+    _set_tx_pwr(sc, pa_band, txpwr);
+}
+static void ssv6006_turismoC_set_xtal_freq_offset_compensation(struct ssv_hw *sh, int xi, int xo)
+{
+    SET_RG_XO_CBANKI(xi);
+    SET_RG_XO_CBANKO(xo);
+}
+static int ssv6006_turismoC_chg_xtal_freq_offset(struct ssv_hw *sh)
+{
+    if (sh->cfg.force_xtal_fo) {
+        SET_RG_XO_CBANKI(151);
+        SET_RG_XO_CBANKO(151);
+        return 0;
+    }
+    if (sh->flash_config.exist) {
+        ssv6006_turismoC_set_xtal_freq_offset_compensation(sh,
+                ((sh->flash_config.rt_config.xtal_offset & 0xff00) >> 8),
+                ((sh->flash_config.rt_config.xtal_offset & 0x00ff) >> 0));
+    } else if (sh->efuse_bitmap & BIT(EFUSE_CRYSTAL_FREQUENCY_OFFSET)) {
+        ssv6006_turismoC_set_xtal_freq_offset_compensation(sh,
+                sh->cfg.crystal_frequency_offset,
+                sh->cfg.crystal_frequency_offset);
+    }
+    return 0;
+}
+static void ssv6006_turismoC_chg_cck_bbscale(struct ssv_hw *sh, int cck)
+{
+    SET_RG_BB_SCALE_BARKER_CCK(cck);
+}
+static void ssv6006_turismoC_chg_legacy_bbscale(struct ssv_hw *sh, int bpsk, int qpsk, int qam16, int qam64)
+{
+    u32 regval = 0;
+    regval = ((qam64 << RG_BB_SCALE_LEGACY_64QAM_SFT) |
+              (qam16 << RG_BB_SCALE_LEGACY_16QAM_SFT) |
+              (qpsk << RG_BB_SCALE_LEGACY_QPSK_SFT) |
+              (bpsk << RG_BB_SCALE_LEGACY_BPSK_SFT));
+    REG32_W(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_1, regval);
+}
+static void ssv6006_turismoC_chg_ht20_bbscale(struct ssv_hw *sh, int bpsk, int qpsk, int qam16, int qam64)
+{
+    u32 regval = 0;
+    regval = ((qam64 << RG_BB_SCALE_HT20_64QAM_SFT) |
+              (qam16 << RG_BB_SCALE_HT20_16QAM_SFT) |
+              (qpsk << RG_BB_SCALE_HT20_QPSK_SFT) |
+              (bpsk << RG_BB_SCALE_HT20_BPSK_SFT));
+    REG32_W(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_2, regval);
+}
+static void ssv6006_turismoC_chg_ht40_bbscale(struct ssv_hw *sh, int bpsk, int qpsk, int qam16, int qam64)
+{
+    u32 regval = 0;
+    regval = ((qam64 << RG_BB_SCALE_HT40_64QAM_SFT) |
+              (qam16 << RG_BB_SCALE_HT40_16QAM_SFT) |
+              (qpsk << RG_BB_SCALE_HT40_QPSK_SFT) |
+              (bpsk << RG_BB_SCALE_HT40_BPSK_SFT));
+    REG32_W(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_3, regval);
+}
+static int ssv6006_turismoC_chg_bbscale(struct ssv_hw *sh)
+{
+    int value = 0;
+    int b_rate_gain_tbl[] = {0x98, 0x90, 0x88, 0x80, 0x79, 0x72, 0x6c, 0x66,
+                             0x60, 0x5b, 0x56, 0x51, 0x4c, 0x48, 0x44, 0x40
+                            };
+    int ofdm_rate_gain_tbl[] = {0xb5, 0xab, 0xa1, 0x98, 0x90, 0x88, 0x80, 0x79, 0x72, 0x6c,
+                                0x66, 0x60, 0x5b, 0x56, 0x51, 0x4c, 0x48, 0x44, 0x40
+                               };
+#define SIZE_B_RATE_GAIN_TBL (sizeof(b_rate_gain_tbl) / sizeof((b_rate_gain_tbl)[0]))
+#define MAX_OFDM_RATE_GAIN_INDEX (12)
+#define OFDM_RATE_GAIN_64QAM_OFFSET (6)
+#define OFDM_RATE_GAIN_16QAM_OFFSET (4)
+#define OFDM_RATE_GAIN_QPSK_OFFSET (2)
+#define OFDM_RATE_GAIN_BPSK_OFFSET (0)
+#define EFUSE_RATE_GAIN_MASK_CCK (0x01)
+#define EFUSE_RATE_GAIN_MASK_LEGACY (0x02)
+#define EFUSE_RATE_GAIN_MASK_HT20 (0x04)
+#define EFUSE_RATE_GAIN_MASK_HT40 (0x08)
+
+    if (sh->flash_config.exist) {
+        ssv6006_turismoC_chg_cck_bbscale(sh, sh->flash_config.rate_delta[0]);
+    } else {
+        if ((sh->efuse_bitmap & BIT(EFUSE_RATE_TABLE_1)) &&
+            (sh->cfg.efuse_rate_gain_mask & EFUSE_RATE_GAIN_MASK_CCK)) {
+            value = ((sh->cfg.rate_table_1 & 0xf0) >> 4);
+            if (value < SIZE_B_RATE_GAIN_TBL)
+                ssv6006_turismoC_chg_cck_bbscale(sh, b_rate_gain_tbl[value]);
+        }
+    }
+    if (sh->flash_config.exist) {
+        ssv6006_turismoC_chg_legacy_bbscale(sh,
+                                            sh->flash_config.rate_delta[1],
+                                            sh->flash_config.rate_delta[2],
+                                            sh->flash_config.rate_delta[3],
+                                            sh->flash_config.rate_delta[4]);
+    } else {
+        if ((sh->efuse_bitmap & BIT(EFUSE_RATE_TABLE_2)) &&
+            (sh->cfg.efuse_rate_gain_mask & EFUSE_RATE_GAIN_MASK_LEGACY)) {
+            value = ((sh->cfg.rate_table_2 & 0xf0) >> 4);
+            if (value <= MAX_OFDM_RATE_GAIN_INDEX) {
+                ssv6006_turismoC_chg_legacy_bbscale(sh,
+                                                    ofdm_rate_gain_tbl[value+OFDM_RATE_GAIN_BPSK_OFFSET],
+                                                    ofdm_rate_gain_tbl[value+OFDM_RATE_GAIN_QPSK_OFFSET],
+                                                    ofdm_rate_gain_tbl[value+OFDM_RATE_GAIN_16QAM_OFFSET],
+                                                    ofdm_rate_gain_tbl[value+OFDM_RATE_GAIN_64QAM_OFFSET]);
+            }
+        }
+    }
+    if (sh->flash_config.exist) {
+        ssv6006_turismoC_chg_ht20_bbscale(sh,
+                                          sh->flash_config.rate_delta[5],
+                                          sh->flash_config.rate_delta[6],
+                                          sh->flash_config.rate_delta[7],
+                                          sh->flash_config.rate_delta[8]);
+    } else {
+        if ((sh->efuse_bitmap & BIT(EFUSE_RATE_TABLE_2)) &&
+            (sh->cfg.efuse_rate_gain_mask & EFUSE_RATE_GAIN_MASK_HT20)) {
+            value = ((sh->cfg.rate_table_2 & 0x0f) >> 0);
+            if (value < MAX_OFDM_RATE_GAIN_INDEX) {
+                ssv6006_turismoC_chg_ht20_bbscale(sh,
+                                                  ofdm_rate_gain_tbl[value+OFDM_RATE_GAIN_BPSK_OFFSET],
+                                                  ofdm_rate_gain_tbl[value+OFDM_RATE_GAIN_QPSK_OFFSET],
+                                                  ofdm_rate_gain_tbl[value+OFDM_RATE_GAIN_16QAM_OFFSET],
+                                                  ofdm_rate_gain_tbl[value+OFDM_RATE_GAIN_64QAM_OFFSET]);
+            }
+        }
+    }
+    if (sh->flash_config.exist) {
+        ssv6006_turismoC_chg_ht40_bbscale(sh,
+                                          sh->flash_config.rate_delta[9],
+                                          sh->flash_config.rate_delta[10],
+                                          sh->flash_config.rate_delta[11],
+                                          sh->flash_config.rate_delta[12]);
+    } else {
+        if ((sh->efuse_bitmap & BIT(EFUSE_RATE_TABLE_1)) &&
+            (sh->cfg.efuse_rate_gain_mask & EFUSE_RATE_GAIN_MASK_HT40)) {
+            value = ((sh->cfg.rate_table_1 & 0x0f) >> 0);
+            if (value < MAX_OFDM_RATE_GAIN_INDEX) {
+                ssv6006_turismoC_chg_ht40_bbscale(sh,
+                                                  ofdm_rate_gain_tbl[value+OFDM_RATE_GAIN_BPSK_OFFSET],
+                                                  ofdm_rate_gain_tbl[value+OFDM_RATE_GAIN_QPSK_OFFSET],
+                                                  ofdm_rate_gain_tbl[value+OFDM_RATE_GAIN_16QAM_OFFSET],
+                                                  ofdm_rate_gain_tbl[value+OFDM_RATE_GAIN_64QAM_OFFSET]);
+            }
+        }
+    }
+    return 0;
+}
+static int ssv6006_turismoC_chg_dpd_bbscale(struct ssv_hw *sh)
+{
+    struct ssv_softc *sc = sh->sc;
+    int value = 0;
+    int band_gain_tbl[] = {0x48, 0x4c, 0x51, 0x56, 0x5b, 0x60, 0x66, 0x6c,
+                           0x72, 0x79, 0x80, 0x88, 0x90, 0x98, 0xa1, 0xab
+                          };
+#define SIZE_BAND_GAIN_TBL (sizeof(band_gain_tbl) / sizeof((band_gain_tbl)[0]))
+    if (sh->flash_config.exist) {
+        sc->dpd.bbscale[BAND_2G] = sh->flash_config.rt_config.g_band_gain[0];
+    } else if (sh->efuse_bitmap & BIT(EFUSE_TX_POWER_INDEX_1)) {
+        value = ((sh->cfg.tx_power_index_1 & 0x0f) >> 0);
+        sc->dpd.bbscale[BAND_2G] = band_gain_tbl[value];
+    } else {
+        sc->dpd.bbscale[BAND_2G] = DEFAULT_DPD_BBSCALE_2500;
+    }
+    if (sh->flash_config.exist) {
+        sc->dpd.bbscale[BAND_5100] = sh->flash_config.rt_config.a_band_gain[0];
+    } else {
+        sc->dpd.bbscale[BAND_5100] = DEFAULT_DPD_BBSCALE_5100;
+    }
+    if (sh->flash_config.exist) {
+        sc->dpd.bbscale[BAND_5500] = sh->flash_config.rt_config.a_band_gain[1];
+    } else if (sh->efuse_bitmap & BIT(EFUSE_TX_POWER_INDEX_1)) {
+        value = ((sh->cfg.tx_power_index_1 & 0xf0) >> 4);
+        sc->dpd.bbscale[BAND_5500] = band_gain_tbl[value];
+    } else {
+        sc->dpd.bbscale[BAND_5500] = DEFAULT_DPD_BBSCALE_5500;
+    }
+    if (sh->flash_config.exist) {
+        sc->dpd.bbscale[BAND_5700] = sh->flash_config.rt_config.a_band_gain[2];
+    } else if (sh->efuse_bitmap & BIT(EFUSE_TX_POWER_INDEX_2)) {
+        value = ((sh->cfg.tx_power_index_2 & 0x0f) >> 0);
+        sc->dpd.bbscale[BAND_5700] = band_gain_tbl[value];
+    } else {
+        sc->dpd.bbscale[BAND_5700] = DEFAULT_DPD_BBSCALE_5700;
+    }
+    if (sh->flash_config.exist) {
+        sc->dpd.bbscale[BAND_5900] = sh->flash_config.rt_config.a_band_gain[3];
+    } else if (sh->efuse_bitmap & BIT(EFUSE_TX_POWER_INDEX_2)) {
+        value = ((sh->cfg.tx_power_index_2 & 0xf0) >> 4);
+        sc->dpd.bbscale[BAND_5900] = band_gain_tbl[value];
+    } else {
+        sc->dpd.bbscale[BAND_5900] = DEFAULT_DPD_BBSCALE_5900;
+    }
+    return 0;
+}
+static void ssv6006_turismoC_apply_flash_setting_to_rf(struct ssv_hw *sh)
+{
+    if (sh->flash_config.exist) {
+        REG32_W(ADR_2_4G_TX_FE_REGISTER, sh->flash_config.g_band_pa_bias0);
+        REG32_W(ADR_2_4G_TX_PA_REGISTER, sh->flash_config.g_band_pa_bias1);
+        REG32_W(ADR_5G_TX_PGA_CAPSW_CONTROL_I, sh->flash_config.a_band_pa_bias0);
+        REG32_W(ADR_5G_TX_PGA_CAPSW_CONTROL_II, sh->flash_config.a_band_pa_bias1);
+    }
+}
+static int ssv6006_turismoC_update_efuse_setting(struct ssv_hw *sh)
+{
+    ssv6006_turismoC_chg_xtal_freq_offset(sh);
+    ssv6006_turismoC_chg_bbscale(sh);
+    ssv6006_turismoC_chg_dpd_bbscale(sh);
+    ssv6006_turismoC_apply_flash_setting_to_rf(sh);
+    return 0;
+}
+static int ssv6006_turismoC_get_current_temperature(struct ssv_hw *sh, int *pvalue)
+{
+    int ret = -1;
+    int i = 0;
+    SET_RG_SARADC_THERMAL(1);
+    SET_RG_EN_SARADC(1);
+    for (i = 0; i < 100; i++) {
+        if (GET_SAR_ADC_FSM_RDY) {
+            ret = 0;
+            break;
+        }
+    }
+    *pvalue = GET_DB_DA_SARADC_BIT;
+    SET_RG_SARADC_THERMAL(0);
+    SET_RG_EN_SARADC(0);
+    return ret;
+}
+static int ssv6006_turismoC_get_current_tempe_state(struct ssv_hw *sh, char low_boundary, char high_boundary)
+{
+    int tempe_state = 0;
+    int tempe = 0;
+    if (ssv6006_turismoC_get_current_temperature(sh, &tempe) < 0)
+        return -1;
+    if(tempe <= low_boundary)
+        tempe_state = SSV_TEMPERATURE_LOW;
+    else if(tempe >= high_boundary)
+        tempe_state = SSV_TEMPERATURE_HIGH;
+    else
+        tempe_state = SSV_TEMPERATURE_NORMAL;
+    return tempe_state;
+}
+static void ssv6006_turismoC_do_temperature_dpd_bbscale_compensation(struct ssv_hw *sh,
+        int chan, struct ssv_tempe_table *tempe_table)
+{
+    struct ssv_softc *sc = sh->sc;
+    u32 regval = 0;
+    regval = tempe_table->g_band_gain[chan/2];
+    sc->dpd.bbscale[BAND_2G] = regval;
+    SET_RG_DPD_BB_SCALE_2500(regval);
+    sc->dpd.bbscale[BAND_5100] = tempe_table->a_band_gain[0];
+    sc->dpd.bbscale[BAND_5500] = tempe_table->a_band_gain[1];
+    sc->dpd.bbscale[BAND_5700] = tempe_table->a_band_gain[2];
+    sc->dpd.bbscale[BAND_5900] = tempe_table->a_band_gain[3];
+    regval = 0;
+    regval = ((sc->dpd.bbscale[BAND_5900] << RG_DPD_BB_SCALE_5900_SFT) |
+              (sc->dpd.bbscale[BAND_5700] << RG_DPD_BB_SCALE_5700_SFT) |
+              (sc->dpd.bbscale[BAND_5500] << RG_DPD_BB_SCALE_5500_SFT) |
+              (sc->dpd.bbscale[BAND_5100] << RG_DPD_BB_SCALE_5100_SFT));
+    REG32_W(ADR_WIFI_PADPD_5G_BB_GAIN_REG, regval);
+}
+static void ssv6006_turismoC_do_temperature_compensation(struct ssv_hw *sh)
+{
+    int now_tempe_state = 0;
+    now_tempe_state = ssv6006_turismoC_get_current_tempe_state(sh, sh->flash_config.xtal_offset_low_boundary,
+                      sh->flash_config.xtal_offset_high_boundary);
+    if ((sh->flash_config.xtal_offset_tempe_state != now_tempe_state)) {
+        sh->flash_config.xtal_offset_tempe_state = now_tempe_state;
+        if (now_tempe_state == SSV_TEMPERATURE_LOW) {
+            ssv6006_turismoC_set_xtal_freq_offset_compensation(sh,
+                    ((sh->flash_config.lt_config.xtal_offset & 0xff00) >> 8),
+                    ((sh->flash_config.lt_config.xtal_offset & 0x00ff) >> 0));
+        } else if (now_tempe_state == SSV_TEMPERATURE_HIGH) {
+            ssv6006_turismoC_set_xtal_freq_offset_compensation(sh,
+                    ((sh->flash_config.ht_config.xtal_offset & 0xff00) >> 8),
+                    ((sh->flash_config.ht_config.xtal_offset & 0x00ff) >> 0));
+        } else if (now_tempe_state == SSV_TEMPERATURE_NORMAL) {
+            ssv6006_turismoC_set_xtal_freq_offset_compensation(sh,
+                    ((sh->flash_config.rt_config.xtal_offset & 0xff00) >> 8),
+                    ((sh->flash_config.rt_config.xtal_offset & 0x00ff) >> 0));
+        }
+    }
+    now_tempe_state = ssv6006_turismoC_get_current_tempe_state(sh, sh->flash_config.band_gain_low_boundary,
+                      sh->flash_config.band_gain_high_boundary);
+    if ((sh->flash_config.band_gain_tempe_state != now_tempe_state) || (sh->flash_config.chan != sh->sc->hw_chan)) {
+        sh->flash_config.band_gain_tempe_state = now_tempe_state;
+        sh->flash_config.chan = sh->sc->hw_chan;
+        if (now_tempe_state == SSV_TEMPERATURE_LOW) {
+            ssv6006_turismoC_do_temperature_dpd_bbscale_compensation(sh, sh->sc->hw_chan, &sh->flash_config.lt_config);
+        } else if (now_tempe_state == SSV_TEMPERATURE_HIGH) {
+            ssv6006_turismoC_do_temperature_dpd_bbscale_compensation(sh, sh->sc->hw_chan, &sh->flash_config.ht_config);
+        } else if (now_tempe_state == SSV_TEMPERATURE_NORMAL) {
+            ssv6006_turismoC_do_temperature_dpd_bbscale_compensation(sh, sh->sc->hw_chan, &sh->flash_config.rt_config);
+        }
+    }
+}
+static void ssv6006c_rx_spectrum(struct ssv_hw *sh)
+{
+    u32 single_tone_value = 0x0;
+    u32 single_tone_step = 0x40;
+    u64 regval1 = 0, regval2 = 0;
+    u64 value = 0;
+    int i = 0;
+    SET_RG_TXD_SEL(0x1);
+    SET_RG_RX_GAIN_MANUAL(0x1);
+    SET_RG_RFG(0x3);
+    SET_RG_PGAG(0xF);
+    SET_RG_SPECTRUM_EN(0x1);
+    SET_RG_ALPHA_SEL(0x2);
+    SET_RG_SPECTRUM_LO_FIX(0x1);
+    for (i = 0; i < (65536/single_tone_step); i++) {
+        SET_RG_SPECTRUM_PWR_UPDATE(0x1);
+        SET_RG_PHASE_STEP_VALUE(single_tone_value);
+        mdelay(10);
+        SET_RG_SPECTRUM_PWR_UPDATE(0x1);
+        regval1 = REG32_R(ADR_RF_D_CAL_TOP_8);
+        regval2 = REG32_R(ADR_RF_D_CAL_TOP_7);
+        value = (((regval2 & 0xff) << 32) | (regval1));
+        printk("The spectrum [single_tone=0x%04x] power is %llu", single_tone_value, value);
+        single_tone_value = single_tone_value + single_tone_step;
+    }
+    SET_RG_TXD_SEL(0x0);
+    SET_RG_RX_GAIN_MANUAL(0x0);
+    SET_RG_RFG(0x3);
+    SET_RG_PGAG(0xF);
+    SET_RG_SPECTRUM_EN(0x0);
+    SET_RG_ALPHA_SEL(0x2);
+    SET_RG_SPECTRUM_LO_FIX(0x0);
+}
+static void ssv6006c_cmd_spectrum(struct ssv_hw *sh)
+{
+    struct ssv_softc *sc = sh->sc;
+    struct ieee80211_channel chan;
+    sc->sc_flags |= SC_OP_BLOCK_CNTL;
+    sc->sc_flags |= SC_OP_CHAN_FIXED;
+    memset(&chan, 0, sizeof( struct ieee80211_channel));
+    chan.hw_value = 6;
+    HAL_SET_CHANNEL(sc, &chan, NL80211_CHAN_HT20);
+    sc->hw_chan = chan.hw_value;
+    sc->hw_chan_type = NL80211_CHAN_HT20;
+    mdelay(1);
+    ssv6006c_rx_spectrum(sh);
+    sc->sc_flags &= ~SC_OP_BLOCK_CNTL;
+    sc->sc_flags &= ~SC_OP_CHAN_FIXED;
+}
+void ssv_attach_ssv6006_turismoC_BBRF(struct ssv_hal_ops *hal_ops)
+{
+    hal_ops->load_phy_table = ssv6006_turismoC_load_phy_table;
+    hal_ops->get_phy_table_size = ssv6006_turismoC_get_phy_table_size;
+    hal_ops->get_rf_table_size = ssv6006_turismoC_get_rf_table_size;
+    hal_ops->load_rf_table = ssv6006_turismoC_load_rf_table;
+    hal_ops->init_pll = ssv6006_turismoC_init_PLL;
+    hal_ops->set_channel = ssv6006_turismoC_set_channel;
+    hal_ops->set_pll_phy_rf = ssv6006_turismoC_set_pll_phy_rf;
+    hal_ops->set_rf_enable = ssv6006_turismoC_set_rf_enable;
+    hal_ops->dump_phy_reg = ssv6006_turismoC_dump_phy_reg;
+    hal_ops->dump_rf_reg = ssv6006_turismoC_dump_rf_reg;
+    hal_ops->support_iqk_cmd = ssv6006_turismoC_support_iqk_cmd;
+    hal_ops->cmd_cali = ssv6006_cmd_turismoC_cali;
+    hal_ops->cmd_loopback_setup_env = ssv6006c_cmd_loopback_setup_env;
+    hal_ops->cmd_loopback = ssv6006_cmd_turismoC_loopback;
+    hal_ops->cmd_txgen = ssv6006_cmd_turismoC_txgen;
+    hal_ops->cmd_rf = ssv6006_cmd_turismoC_rf;
+    hal_ops->update_rf_pwr = ssv6006_turismoC_update_rf_pwr;
+    hal_ops->update_efuse_setting = ssv6006_turismoC_update_efuse_setting;
+    hal_ops->do_temperature_compensation = ssv6006_turismoC_do_temperature_compensation;
+    hal_ops->cmd_spectrum = ssv6006c_cmd_spectrum;
+}
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/turismoC_rf_reg.c b/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/turismoC_rf_reg.c
new file mode 100644
index 000000000..953de6358
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/turismoC_rf_reg.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define SSV6006_TURISMOC_RF_TABLE_VER "20.00"
+ssv_cabrio_reg ssv6006_turismoC_rf_setting[]= {
+    {0xCCB0A420,0x0033E73F},
+    {0xCCB0A554,0x03024444},
+    {0xCCB0A594,0x111E0950},
+    {0xCCB0A598,0x0F1E00FF},
+    {0xCCB0A530,0x001F1F01},
+    {0xCCB0A604,0x001F1F01},
+    {0xCCB0A62C,0x9264924A},
+    {0xCCB0A630,0x96DBB6CC},
+    {0xCCB0A634,0x00000000},
+    {0xCCB0A8CC,0x141E157C},
+    {0xCCB0A8D0,0x00001644},
+    {0xccb0a88c,0x00000010},
+    {0xccb0a808,0x88000000},
+    {0xCCB0B000,0x24844214},
+};
diff --git a/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/turismoC_wifi_phy_reg.c b/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/turismoC_wifi_phy_reg.c
new file mode 100644
index 000000000..c1180c6da
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/turismoC_wifi_phy_reg.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define SSV6006_TURISMOC_PHY_TABLE_VER "20.00"
+ssv_cabrio_reg ssv6006_turismoC_phy_setting[]= {
+    {0xccb0e010,0x00000FFF},
+    {0xccb0e014,0x00807f03},
+    {0xccb0e018,0x0055003C},
+    {0xccb0e01C,0x00000064},
+    {0xccb0e020,0x00000000},
+    {0xccb0e02C,0x7004606C},
+    {0xccb0e030,0x7004606C},
+    {0xccb0e034,0x1A040400},
+    {0xccb0e038,0x630F36D0},
+    {0xccb0e03C,0x100c0003},
+    {0xccb0e040,0x11600800},
+    {0xccb0e044,0x00080868},
+    {0xccb0e048,0xFF001160},
+    {0xccb0e04C,0x00100040},
+    {0xccb0e060,0x11501150},
+    {0xccb0e12C,0x00001160},
+    {0xccb0e130,0x00100040},
+    {0xccb0e134,0x00080010},
+    {0xccb0e180,0x00010060},
+    {0xccb0e184,0xB5A19080},
+    {0xccb0e188,0xB5A19080},
+    {0xccb0e18c,0xB5A19080},
+    {0xccb0e190,0x00010006},
+    {0xccb0e194,0x06060606},
+    {0xccb0e198,0x06060606},
+    {0xccb0e19c,0x06060606},
+    {0xccb0e080,0x0110000F},
+    {0xccb0e098,0x00102000},
+    {0xccb0e09C,0x00100018},
+    {0xccb0e4b4,0x00002001},
+    {0xccb0ecA4,0x00009001},
+    {0xccb0ecB8,0x000C50CC},
+    {0xccb0fc44,0x00028080},
+    {0xccb0f008,0x00004775},
+    {0xccb0f00c,0x10000075},
+    {0xccb0f010,0x3F304905},
+    {0xccb0f014,0x40182000},
+    {0xccb0f018,0x20600000},
+    {0xccb0f01C,0x0c010080},
+    {0xccb0f03C,0x0000005a},
+    {0xccb0f020,0x20202020},
+    {0xccb0f024,0x20000000},
+    {0xccb0f028,0x50505050},
+    {0xccb0f02c,0x20202020},
+    {0xccb0f030,0x20000000},
+    {0xccb0f034,0x00002424},
+    {0xccb0f09c,0x000030A0},
+    {0xccb0f0C0,0x0f0003c0},
+    {0xccb0f0C4,0x30023003},
+    {0xccb0f0CC,0x00000120},
+    {0xccb0f0D0,0x00000020},
+    {0xccb0f130,0x40000000},
+    {0xccb0f164,0x000e0090},
+    {0xccb0f188,0x82000000},
+    {0xccb0f190,0x00000020},
+    {0xccb0f194,0x09360001},
+    {0xccb0f3F8,0x00100001},
+    {0xccb0f3FC,0x00010425},
+    {0xccb0e804,0x00020000},
+    {0xccb0e808,0x20280060},
+    {0xccb0e80c,0x00003467},
+    {0xccb0e810,0x00430000},
+    {0xccb0e814,0x30000015},
+    {0xccb0e818,0x00390005},
+    {0xccb0e81C,0x05050005},
+    {0xccb0e820,0x00570057},
+    {0xccb0e824,0x00570057},
+    {0xccb0e828,0x00236700},
+    {0xccb0e82c,0x000d1746},
+    {0xccb0e830,0x05051787},
+    {0xccb0e834,0x07800000},
+    {0xccb0e89c,0x009000B0},
+    {0xccb0e8A0,0x00000000},
+    {0xccb0ebF8,0x00100000},
+    {0xccb0ebFC,0x00000001},
+};
+#define PAPDP_GAIN_SETTING 0x0
+#define PAPDP_GAIN_SETTING_F2 0x0
+#define PAPDP_GAIN_SETTING_2G 0x6
+#define DEFAULT_DPD_BBSCALE_2500 0x60
+#define DEFAULT_DPD_BBSCALE_5100 0x80
+#define DEFAULT_DPD_BBSCALE_5500 0x6C
+#define DEFAULT_DPD_BBSCALE_5700 0x6C
+#define DEFAULT_DPD_BBSCALE_5900 0x66
diff --git a/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/turismo_common.c b/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/turismo_common.c
new file mode 100644
index 000000000..ecd41fc84
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/turismo_common.c
@@ -0,0 +1,319 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifdef COMMON_FOR_REDBULL
+#include <stdio.h>
+#include <string.h>
+#include <ssv_regs.h>
+#include "turismo_common.h"
+#endif
+const int cal_ch_5g[4] = { 36, 40, 100, 140};
+const u32 am_mask[2] = {0xfffffc00,0xfc00ffff};
+const u32 padpd_am_addr_table[5][13]= {
+    {
+        ADR_WIFI_PADPD_2G_GAIN_REG0,
+        ADR_WIFI_PADPD_2G_GAIN_REG1,
+        ADR_WIFI_PADPD_2G_GAIN_REG2,
+        ADR_WIFI_PADPD_2G_GAIN_REG3,
+        ADR_WIFI_PADPD_2G_GAIN_REG4,
+        ADR_WIFI_PADPD_2G_GAIN_REG5,
+        ADR_WIFI_PADPD_2G_GAIN_REG6,
+        ADR_WIFI_PADPD_2G_GAIN_REG7,
+        ADR_WIFI_PADPD_2G_GAIN_REG8,
+        ADR_WIFI_PADPD_2G_GAIN_REG9,
+        ADR_WIFI_PADPD_2G_GAIN_REGA,
+        ADR_WIFI_PADPD_2G_GAIN_REGB,
+        ADR_WIFI_PADPD_2G_GAIN_REGC
+    },
+    {
+        ADR_WIFI_PADPD_5100_GAIN_REG0,
+        ADR_WIFI_PADPD_5100_GAIN_REG1,
+        ADR_WIFI_PADPD_5100_GAIN_REG2,
+        ADR_WIFI_PADPD_5100_GAIN_REG3,
+        ADR_WIFI_PADPD_5100_GAIN_REG4,
+        ADR_WIFI_PADPD_5100_GAIN_REG5,
+        ADR_WIFI_PADPD_5100_GAIN_REG6,
+        ADR_WIFI_PADPD_5100_GAIN_REG7,
+        ADR_WIFI_PADPD_5100_GAIN_REG8,
+        ADR_WIFI_PADPD_5100_GAIN_REG9,
+        ADR_WIFI_PADPD_5100_GAIN_REGA,
+        ADR_WIFI_PADPD_5100_GAIN_REGB,
+        ADR_WIFI_PADPD_5100_GAIN_REGC
+    },
+    {
+        ADR_WIFI_PADPD_5500_GAIN_REG0,
+        ADR_WIFI_PADPD_5500_GAIN_REG1,
+        ADR_WIFI_PADPD_5500_GAIN_REG2,
+        ADR_WIFI_PADPD_5500_GAIN_REG3,
+        ADR_WIFI_PADPD_5500_GAIN_REG4,
+        ADR_WIFI_PADPD_5500_GAIN_REG5,
+        ADR_WIFI_PADPD_5500_GAIN_REG6,
+        ADR_WIFI_PADPD_5500_GAIN_REG7,
+        ADR_WIFI_PADPD_5500_GAIN_REG8,
+        ADR_WIFI_PADPD_5500_GAIN_REG9,
+        ADR_WIFI_PADPD_5500_GAIN_REGA,
+        ADR_WIFI_PADPD_5500_GAIN_REGB,
+        ADR_WIFI_PADPD_5500_GAIN_REGC
+    },
+    {
+        ADR_WIFI_PADPD_5700_GAIN_REG0,
+        ADR_WIFI_PADPD_5700_GAIN_REG1,
+        ADR_WIFI_PADPD_5700_GAIN_REG2,
+        ADR_WIFI_PADPD_5700_GAIN_REG3,
+        ADR_WIFI_PADPD_5700_GAIN_REG4,
+        ADR_WIFI_PADPD_5700_GAIN_REG5,
+        ADR_WIFI_PADPD_5700_GAIN_REG6,
+        ADR_WIFI_PADPD_5700_GAIN_REG7,
+        ADR_WIFI_PADPD_5700_GAIN_REG8,
+        ADR_WIFI_PADPD_5700_GAIN_REG9,
+        ADR_WIFI_PADPD_5700_GAIN_REGA,
+        ADR_WIFI_PADPD_5700_GAIN_REGB,
+        ADR_WIFI_PADPD_5700_GAIN_REGC
+    },
+    {
+        ADR_WIFI_PADPD_5900_GAIN_REG0,
+        ADR_WIFI_PADPD_5900_GAIN_REG1,
+        ADR_WIFI_PADPD_5900_GAIN_REG2,
+        ADR_WIFI_PADPD_5900_GAIN_REG3,
+        ADR_WIFI_PADPD_5900_GAIN_REG4,
+        ADR_WIFI_PADPD_5900_GAIN_REG5,
+        ADR_WIFI_PADPD_5900_GAIN_REG6,
+        ADR_WIFI_PADPD_5900_GAIN_REG7,
+        ADR_WIFI_PADPD_5900_GAIN_REG8,
+        ADR_WIFI_PADPD_5900_GAIN_REG9,
+        ADR_WIFI_PADPD_5900_GAIN_REGA,
+        ADR_WIFI_PADPD_5900_GAIN_REGB,
+        ADR_WIFI_PADPD_5900_GAIN_REGC
+    }
+};
+const u32 pm_mask[2] = {0xffffe000,0xe000ffff};
+const u32 padpd_pm_addr_table[5][13]= {
+    {
+        ADR_WIFI_PADPD_2G_PHASE_REG0,
+        ADR_WIFI_PADPD_2G_PHASE_REG1,
+        ADR_WIFI_PADPD_2G_PHASE_REG2,
+        ADR_WIFI_PADPD_2G_PHASE_REG3,
+        ADR_WIFI_PADPD_2G_PHASE_REG4,
+        ADR_WIFI_PADPD_2G_PHASE_REG5,
+        ADR_WIFI_PADPD_2G_PHASE_REG6,
+        ADR_WIFI_PADPD_2G_PHASE_REG7,
+        ADR_WIFI_PADPD_2G_PHASE_REG8,
+        ADR_WIFI_PADPD_2G_PHASE_REG9,
+        ADR_WIFI_PADPD_2G_PHASE_REGA,
+        ADR_WIFI_PADPD_2G_PHASE_REGB,
+        ADR_WIFI_PADPD_2G_PHASE_REGC
+    },
+    {
+        ADR_WIFI_PADPD_5100_PHASE_REG0,
+        ADR_WIFI_PADPD_5100_PHASE_REG1,
+        ADR_WIFI_PADPD_5100_PHASE_REG2,
+        ADR_WIFI_PADPD_5100_PHASE_REG3,
+        ADR_WIFI_PADPD_5100_PHASE_REG4,
+        ADR_WIFI_PADPD_5100_PHASE_REG5,
+        ADR_WIFI_PADPD_5100_PHASE_REG6,
+        ADR_WIFI_PADPD_5100_PHASE_REG7,
+        ADR_WIFI_PADPD_5100_PHASE_REG8,
+        ADR_WIFI_PADPD_5100_PHASE_REG9,
+        ADR_WIFI_PADPD_5100_PHASE_REGA,
+        ADR_WIFI_PADPD_5100_PHASE_REGB,
+        ADR_WIFI_PADPD_5100_PHASE_REGC
+    },
+    {
+        ADR_WIFI_PADPD_5500_PHASE_REG0,
+        ADR_WIFI_PADPD_5500_PHASE_REG1,
+        ADR_WIFI_PADPD_5500_PHASE_REG2,
+        ADR_WIFI_PADPD_5500_PHASE_REG3,
+        ADR_WIFI_PADPD_5500_PHASE_REG4,
+        ADR_WIFI_PADPD_5500_PHASE_REG5,
+        ADR_WIFI_PADPD_5500_PHASE_REG6,
+        ADR_WIFI_PADPD_5500_PHASE_REG7,
+        ADR_WIFI_PADPD_5500_PHASE_REG8,
+        ADR_WIFI_PADPD_5500_PHASE_REG9,
+        ADR_WIFI_PADPD_5500_PHASE_REGA,
+        ADR_WIFI_PADPD_5500_PHASE_REGB,
+        ADR_WIFI_PADPD_5500_PHASE_REGC
+    },
+    {
+        ADR_WIFI_PADPD_5700_PHASE_REG0,
+        ADR_WIFI_PADPD_5700_PHASE_REG1,
+        ADR_WIFI_PADPD_5700_PHASE_REG2,
+        ADR_WIFI_PADPD_5700_PHASE_REG3,
+        ADR_WIFI_PADPD_5700_PHASE_REG4,
+        ADR_WIFI_PADPD_5700_PHASE_REG5,
+        ADR_WIFI_PADPD_5700_PHASE_REG6,
+        ADR_WIFI_PADPD_5700_PHASE_REG7,
+        ADR_WIFI_PADPD_5700_PHASE_REG8,
+        ADR_WIFI_PADPD_5700_PHASE_REG9,
+        ADR_WIFI_PADPD_5700_PHASE_REGA,
+        ADR_WIFI_PADPD_5700_PHASE_REGB,
+        ADR_WIFI_PADPD_5700_PHASE_REGC
+    },
+    {
+        ADR_WIFI_PADPD_5900_PHASE_REG0,
+        ADR_WIFI_PADPD_5900_PHASE_REG1,
+        ADR_WIFI_PADPD_5900_PHASE_REG2,
+        ADR_WIFI_PADPD_5900_PHASE_REG3,
+        ADR_WIFI_PADPD_5900_PHASE_REG4,
+        ADR_WIFI_PADPD_5900_PHASE_REG5,
+        ADR_WIFI_PADPD_5900_PHASE_REG6,
+        ADR_WIFI_PADPD_5900_PHASE_REG7,
+        ADR_WIFI_PADPD_5900_PHASE_REG8,
+        ADR_WIFI_PADPD_5900_PHASE_REG9,
+        ADR_WIFI_PADPD_5900_PHASE_REGA,
+        ADR_WIFI_PADPD_5900_PHASE_REGB,
+        ADR_WIFI_PADPD_5900_PHASE_REGC
+    }
+};
+#ifdef COMMON_FOR_SMAC
+const u8 pkt1614[] = {
+    0x4e, 0x06, 0x3a, 0x00, 0x71, 0x00, 0x00, 0x00, 0x50, 0x6a, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00,
+    0x2c, 0x00, 0x2c, 0x00, 0x00, 0x00, 0x40, 0x00, 0xf7, 0x84, 0x00, 0x00, 0x4e, 0x10, 0x11, 0x00,
+    0xf6, 0x84, 0x00, 0x00, 0x54, 0x20, 0x00, 0x00, 0xe5, 0x84, 0x08, 0x01, 0x66, 0x20, 0x14, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x88, 0x01, 0x2c, 0x00, 0xe4, 0xf4, 0xc6, 0x03, 0x5f, 0x49, 0x00, 0xaa, 0xb5, 0xc7, 0xd7, 0xf6,
+    0xf0, 0xde, 0xf1, 0x75, 0x05, 0x9d, 0xc0, 0x26, 0x00, 0x00, 0xaa, 0xaa, 0x03, 0x00, 0x00, 0x00,
+    0x08, 0x00, 0x45, 0x00, 0x05, 0xdc, 0x50, 0x02, 0x40, 0x00, 0x40, 0x06, 0x61, 0xa4, 0xc0, 0xa8,
+    0x01, 0x21, 0xc0, 0xa8, 0x01, 0x04, 0xc3, 0xa1, 0x13, 0x89, 0x1c, 0x24, 0xdb, 0x71, 0x80, 0x8c,
+    0xa5, 0x83, 0x80, 0x10, 0x00, 0xe5, 0x69, 0xdf, 0x00, 0x00, 0x01, 0x01, 0x08, 0x0a, 0x00, 0xd3,
+    0x02, 0xe2, 0x22, 0xc7, 0xbf, 0x14, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33,
+    0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39,
+    0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35,
+    0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31,
+    0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
+    0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33,
+    0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39,
+    0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35,
+    0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31,
+    0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
+    0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33,
+    0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39,
+    0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35,
+    0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31,
+    0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
+    0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33,
+    0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39,
+    0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35,
+    0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31,
+    0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
+    0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33,
+    0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39,
+    0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35,
+    0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31,
+    0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
+    0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33,
+    0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39,
+    0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35,
+    0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31,
+    0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
+    0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33,
+    0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39,
+    0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35,
+    0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31,
+    0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
+    0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33,
+    0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39,
+    0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35,
+    0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31,
+    0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
+    0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33,
+    0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39,
+    0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35,
+    0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31,
+    0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
+    0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33,
+    0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39,
+    0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35,
+    0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31,
+    0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
+    0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33,
+    0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39,
+    0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35,
+    0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31,
+    0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
+    0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33,
+    0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39,
+    0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35,
+    0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31,
+    0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
+    0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33,
+    0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39,
+    0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35,
+    0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31,
+    0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
+    0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33,
+    0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39,
+    0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35,
+    0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31,
+    0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
+    0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33,
+    0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39,
+    0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35,
+    0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31,
+    0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
+    0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33,
+    0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39,
+    0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35,
+    0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31,
+    0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
+    0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33,
+    0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39,
+    0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35,
+    0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31,
+    0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
+    0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33,
+    0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39,
+    0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35,
+    0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31,
+    0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
+    0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31,
+};
+#endif
+const u8 xtal_sx_cp_isel_wf[11] = { 0x8, 0x5, 0x5, 0x7, 0xb, 0x7, 0x5, 0x8, 0x7, 0x7, 0x5};
+const char* xtal_type[XTALMAX]= { "16", "24", "26", "40", "12", "20", "25", "32", "19.2", "38.4", "52"};
+int ssv6006_get_pa_band(int ch)
+{
+    int pa_band = 0;
+    if (ch <=14) {
+        pa_band =0;
+    } else if (ch < 36) {
+        pa_band = 1;
+    } else if ((ch >= 36) && (ch < 100)) {
+        pa_band = 2;
+    } else if ((ch >= 100) && (ch < 140)) {
+        pa_band = 3;
+    } else if (ch >= 140) {
+        pa_band = 4;
+    }
+    return pa_band;
+}
+void turismo_pre_cal(SSV_HW *sh)
+{
+    SET_RG_MODE(MODE_STANDBY);
+    SET_RG_CAL_INDEX(CAL_IDX_NONE);
+    SET_RG_MODE_MANUAL(1);
+    SET_RG_MODE(MODE_CALIBRATION);
+}
+void turismo_post_cal(SSV_HW *sh)
+{
+    SET_RG_MODE(MODE_STANDBY);
+    SET_RG_MODE_MANUAL(0);
+}
+void turismo_inter_cal(SSV_HW *sh)
+{
+    SET_RG_MODE(MODE_STANDBY);
+    UDELAY(100);
+    SET_RG_MODE(MODE_CALIBRATION);
+}
diff --git a/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/turismo_common.h b/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/turismo_common.h
new file mode 100644
index 000000000..fdcbf16b7
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/hal/ssv6006c/turismo_common.h
@@ -0,0 +1,3595 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef TU_COMMON_H
+#define TU_COMMON_H
+#define SSV6006_TURISMOC_COMMON_CODE_VER "1.15"
+#ifdef COMMON_FOR_SMAC
+struct ssv6006_tx_desc {
+    u32 len:16;
+    u32 c_type:3;
+    u32 f80211:1;
+    u32 qos:1;
+    u32 ht:1;
+    u32 use_4addr:1;
+    u32 rvdtx_0:3;
+    u32 bc_que:1;
+    u32 security:1;
+    u32 more_data:1;
+    u32 stype_b5b4:2;
+    u32 extra_info:1;
+    u32 fCmd;
+    u32 hdr_offset:8;
+    u32 frag:1;
+    u32 unicast:1;
+    u32 hdr_len:6;
+    u32 no_pkt_buf_reduction:1;
+    u32 tx_burst_obsolete:1;
+    u32 ack_policy_obsolete:2;
+    u32 aggr:2;
+    u32 rsvdtx_1:1;
+    u32 is_rate_stat_sample_pkt:1;
+    u32 bssidx:2;
+    u32 reason:6;
+    u32 payload_offset_obsolete:8;
+    u32 tx_pkt_run_no:8;
+    u32 fCmdIdx:3;
+    u32 wsid:4;
+    u32 txq_idx:3;
+    u32 TxF_ID:6;
+    u32 rateidx1_data_duration:16;
+    u32 rateidx2_data_duration:16;
+    u32 rateidx3_data_duration:16;
+    u32 rsvd_tx05 :2;
+    u32 rate_rpt_mode:2;
+    u32 ampdu_tx_ssn:12;
+    u32 drate_idx0:8;
+    u32 crate_idx0:8;
+    u32 rts_cts_nav0:16;
+    u32 dl_length0:12;
+    u32 try_cnt0:4;
+    u32 ack_policy0:2;
+    u32 do_rts_cts0:2;
+    u32 is_last_rate0:1;
+    u32 rsvdtx_07b:1;
+    u32 rpt_result0:2;
+    u32 rpt_trycnt0:4;
+    u32 rpt_noctstrycnt0:4;
+    u32 drate_idx1:8;
+    u32 crate_idx1:8;
+    u32 rts_cts_nav1:16;
+    u32 dl_length1:12;
+    u32 try_cnt1:4;
+    u32 ack_policy1:2;
+    u32 do_rts_cts1:2;
+    u32 is_last_rate1:1;
+    u32 rsvdtx_09b:1;
+    u32 rpt_result1:2;
+    u32 rpt_trycnt1:4;
+    u32 rpt_noctstrycnt1:4;
+    u32 drate_idx2:8;
+    u32 crate_idx2:8;
+    u32 rts_cts_nav2:16;
+    u32 dl_length2:12;
+    u32 try_cnt2:4;
+    u32 ack_policy2:2;
+    u32 do_rts_cts2:2;
+    u32 is_last_rate2:1;
+    u32 rsvdtx_11b:1;
+    u32 rpt_result2:2;
+    u32 rpt_trycnt2:4;
+    u32 rpt_noctstrycnt2:4;
+    u32 drate_idx3:8;
+    u32 crate_idx3:8;
+    u32 rts_cts_nav3:16;
+    u32 dl_length3:12;
+    u32 try_cnt3:4;
+    u32 ack_policy3:2;
+    u32 do_rts_cts3:2;
+    u32 is_last_rate3:1;
+    u32 rsvdtx_13b:1;
+    u32 rpt_result3:2;
+    u32 rpt_trycnt3:4;
+    u32 rpt_noctstrycnt3:4;
+    u32 ampdu_whole_length:16;
+    u32 ampdu_next_pkt:8;
+    u32 ampdu_last_pkt:1;
+    u32 rsvdtx_14a:3;
+    u32 ampdu_dmydelimiter_num:4;
+    u32 ampdu_tx_bitmap_lw;
+    u32 ampdu_tx_bitmap_hw;
+    u32 dummy0;
+    u32 dummy1;
+    u32 dummy2;
+};
+struct ssv6006_rx_desc {
+    u32 len:16;
+    u32 c_type:3;
+    u32 f80211:1;
+    u32 qos:1;
+    u32 ht:1;
+    u32 use_4addr:1;
+    u32 rsvdrx0_1:1;
+    u32 running_no:4;
+    u32 psm:1;
+    u32 stype_b5b4:2;
+    u32 sec_decode_err:1;
+    union {
+        u32 fCmd;
+        u32 edca0_used:4;
+        u32 edca1_used:5;
+        u32 edca2_used:5;
+        u32 edca3_used:5;
+        u32 mng_used:4;
+        u32 tx_page_used:9;
+    };
+    u32 hdr_offset:8;
+    u32 frag:1;
+    u32 unicast:1;
+    u32 hdr_len:6;
+    u32 RxResult:8;
+    u32 bssid:2;
+    u32 reason:6;
+    u32 channel:8;
+    u32 rx_pkt_run_no:8;
+    u32 fCmdIdx:3;
+    u32 wsid:4;
+    u32 tkip_mmic_err:1;
+    u32 rsvd_rx_3b:8;
+};
+struct ssv6006_rxphy_info {
+    u32 len:16;
+    u32 phy_rate:8;
+    u32 smoothing:1;
+    u32 no_sounding:1;
+    u32 aggregate:1;
+    u32 stbc:2;
+    u32 fec:1;
+    u32 n_ess:2;
+    u32 l_length:12;
+    u32 l_rate:3;
+    u32 mrx_seqn:1;
+    u32 rssi:8;
+    u32 snr:8;
+    u32 rx_freq_offset:16;
+    u32 service:16;
+    u32 rx_time_stamp;
+};
+#endif
+#ifndef COMMON_FOR_SMAC
+#define PADPDBAND 5
+#define MAX_PADPD_TONE 26
+struct ssv6006dpd {
+    u32 am[MAX_PADPD_TONE/2];
+    u32 pm[MAX_PADPD_TONE/2];
+};
+struct ssv6006_padpd {
+    bool dpd_done[PADPDBAND];
+    bool dpd_disable[PADPDBAND];
+    bool pwr_mode;
+    u8 current_band;
+    struct ssv6006dpd val[PADPDBAND];
+    u8 spur_patched;
+    u8 bbscale[PADPDBAND];
+};
+struct ssv6006_cal_result {
+    bool cal_done;
+    bool cal_iq_done[PADPDBAND];
+    u32 rxdc_2g[21];
+    u8 rxrc_bw20;
+    u8 rxrc_bw40;
+    u8 txdc_i_2g;
+    u8 txdc_q_2g;
+    u32 rxdc_5g[21];
+    u8 rxiq_alpha[PADPDBAND];
+    u8 rxiq_theta[PADPDBAND];
+    u8 txdc_i_5g;
+    u8 txdc_q_5g;
+    u8 txiq_alpha[PADPDBAND];
+    u8 txiq_theta[PADPDBAND];
+};
+typedef void SSV_HW;
+#else
+typedef struct ssv_hw SSV_HW;
+#endif
+struct ssv6006_patch {
+    bool dcdc;
+    u16 xtal;
+    u16 cpu_clk;
+};
+#ifdef COMMON_FOR_REDBULL
+#define PAPDP_GAIN_SETTING 0x0
+#define PAPDP_GAIN_SETTING_F2 0x0
+#define PAPDP_GAIN_SETTING_2G 0x6
+#define DEFAULT_DPD_BBSCALE_2500 0x72
+#define DEFAULT_DPD_BBSCALE_5100 0x80
+#define DEFAULT_DPD_BBSCALE_5500 0x6C
+#define DEFAULT_DPD_BBSCALE_5700 0x6C
+#define DEFAULT_DPD_BBSCALE_5900 0x66
+#endif
+#define CLK_32K 1
+#define CLK_XTAL 2
+#define CLK_40M 4
+#define CLK_80M 8
+enum {
+    XTAL16M = 0,
+    XTAL24M,
+    XTAL26M,
+    XTAL40M,
+    XTAL12M,
+    XTAL20M,
+    XTAL25M,
+    XTAL32M,
+    XTAL19P2M,
+    XTAL38P4M,
+    XTAL52M,
+    XTALMAX,
+};
+enum {
+    G_BAND_ONLY = 0,
+    AG_BAND_BOTH = 1,
+};
+enum {
+    CAL_IDX_NONE,
+    CAL_IDX_WIFI2P4G_RXDC,
+    CAL_IDX_BT_RXDC,
+    CAL_IDX_BW20_RXRC,
+    CAL_IDX_WIFI2P4G_TXLO,
+    CAL_IDX_WIFI2P4G_TXIQ,
+    CAL_IDX_WIFI2P4G_RXIQ,
+    CAL_IDX_WIFI2P4G_PADPD,
+    CAL_IDX_5G_NONE,
+    CAL_IDX_WIFI5G_RXDC,
+    CAL_IDX_5G_NONE2,
+    CAL_IDX_BW40_RXRC,
+    CAL_IDX_WIFI5G_TXLO,
+    CAL_IDX_WIFI5G_TXIQ,
+    CAL_IDX_WIFI5G_RXIQ,
+    CAL_IDX_WIFI5G_PADPD,
+};
+enum {
+    MODE_STANDBY,
+    MODE_CALIBRATION,
+    MODE_WIFI2P4G_TX,
+    MODE_WIFI2P4G_RX,
+    MODE_BT_TX,
+    MODE_BT_RX,
+    MODE_WIFI5G_TX,
+    MODE_WIFI5G_RX,
+};
+enum {
+    BAND_2G,
+    BAND_5100,
+    BAND_5500,
+    BAND_5700,
+    BAND_5900,
+    MAX_BAND,
+};
+#ifndef MAX_PADPD_TONE
+#define MAX_PADPD_TONE 26
+#endif
+struct padpd_table {
+    u32 addr;
+    u32 mask0;
+    u32 mask1;
+};
+extern const int cal_ch_5g[4];
+extern const struct padpd_table padpd_am_table[];
+extern const struct padpd_table padpd_pm_table[];
+extern const u8 xtal_sx_cp_isel_wf[];
+extern const char *xtal_type[];
+extern const u32 am_mask[];
+extern const u32 padpd_am_addr_table[][13];
+extern const u32 pm_mask[];
+extern const u32 padpd_pm_addr_table[][13];
+extern int ssv6006_get_pa_band(int ch);
+extern void turismo_pre_cal(SSV_HW *sh);
+extern void turismo_post_cal(SSV_HW *sh);
+extern void turismo_inter_cal(SSV_HW *sh);
+#ifndef COMMON_FOR_SMAC
+#ifndef COMMON_FOR_REDBULL
+extern int printf_null(const char *fmt, ...);
+#define MSLEEP(_val) drv_pmu_tu3(_val * 1000)
+#define MDELAY MSLEEP
+#define UDELAY(_val) drv_pmu_tu3(_val)
+#define PRINT printf_null
+#else
+extern void printf_null(const char *fmt, ...);
+#endif
+#define PRINT_ERR printf
+#define PRINT_INFO printf
+#else
+extern void printf_null(const char *fmt, ...);
+#endif
+#define TU_SET_CHANNEL(_ch) \
+do{ \
+                                                                                            \
+    SET_RG_MODE_MANUAL(1); \
+    MSLEEP(1); \
+                                                                                            \
+                                                                                            \
+    SET_RG_SX_RFCH_MAP_EN(1); \
+    MSLEEP(1); \
+                                                                                            \
+                                                                                            \
+    SET_RG_SX_CHANNEL(_ch); \
+    MSLEEP(1); \
+                                                                                            \
+                                                                                            \
+    SET_RG_MODE(0); \
+    MSLEEP(1); \
+                                                                                            \
+                                                                                            \
+    SET_RG_MODE(3); \
+    MSLEEP(1); \
+                                                                                            \
+                                                                                            \
+    SET_RG_MODE_MANUAL(0); \
+    MSLEEP(1); \
+                                                                                            \
+} while(0)
+#define TU_SET_GEMINIA_BW(_ch_type) \
+do{ \
+                                                                                            \
+    switch (_ch_type){ \
+      case NL80211_CHAN_HT20: \
+      case NL80211_CHAN_NO_HT: \
+                                                                                            \
+            SET_MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_SECONDARY(1); \
+                                                                                            \
+            REG32_W(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER, 0x271556db); \
+            MSLEEP(1); \
+                                                                                            \
+            SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R0, \
+                (0 << RG_GEMINIA_40M_MODE_SFT) | (0 << RG_GEMINIA_LO_UP_CH_SFT), 0, \
+                (RG_GEMINIA_LO_UP_CH_I_MSK & RG_GEMINIA_40M_MODE_I_MSK)); \
+            MSLEEP(1); \
+            SET_REG(ADR_WIFI_PHY_COMMON_SYS_REG, \
+                (0 << RG_SYSTEM_BW_SFT) | (0 << RG_PRIMARY_CH_SIDE_SFT), 0, \
+                (RG_SYSTEM_BW_I_MSK & RG_PRIMARY_CH_SIDE_I_MSK)); \
+                                                                                            \
+            break; \
+                                                                                            \
+   case NL80211_CHAN_HT40MINUS: \
+                                                                                            \
+            SET_MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_SECONDARY(0); \
+                                                                                            \
+            REG32_W(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER, 0x2725534d); \
+            UDELAY(50); \
+                                                                                            \
+            SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R0, \
+                (1 << RG_GEMINIA_40M_MODE_SFT) | (0 << RG_GEMINIA_LO_UP_CH_SFT), 0, \
+                (RG_GEMINIA_LO_UP_CH_I_MSK & RG_GEMINIA_40M_MODE_I_MSK)); \
+            UDELAY(50); \
+                                                                                            \
+            SET_REG(ADR_WIFI_PHY_COMMON_SYS_REG, \
+                (1 << RG_SYSTEM_BW_SFT) | (1 << RG_PRIMARY_CH_SIDE_SFT), 0, \
+                (RG_SYSTEM_BW_I_MSK & RG_PRIMARY_CH_SIDE_I_MSK)); \
+                                                                                            \
+         break; \
+                                                                                            \
+   case NL80211_CHAN_HT40PLUS: \
+                                                                                            \
+            SET_MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_SECONDARY(0); \
+                                                                                            \
+            REG32_W(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER, 0x2725534d); \
+            UDELAY(50); \
+                                                                                            \
+            SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R0, \
+                (1 << RG_GEMINIA_40M_MODE_SFT) | (1 << RG_GEMINIA_LO_UP_CH_SFT), 0, \
+                (RG_GEMINIA_LO_UP_CH_I_MSK & RG_GEMINIA_40M_MODE_I_MSK)); \
+            UDELAY(50); \
+                                                                                            \
+            SET_REG(ADR_WIFI_PHY_COMMON_SYS_REG, \
+                (1 << RG_SYSTEM_BW_SFT) | (0 << RG_PRIMARY_CH_SIDE_SFT), 0, \
+                (RG_SYSTEM_BW_I_MSK & RG_PRIMARY_CH_SIDE_I_MSK)); \
+                                                                                            \
+            break; \
+      default: \
+            break; \
+    } \
+    MSLEEP(1); \
+} while(0)
+#define TU_CHANGE_GEMINIA_CHANNEL(_ch,_ch_type) \
+do{ \
+    const char *chan_type[]={"NL80211_CHAN_NO_HT", \
+     "NL80211_CHAN_HT20", \
+     "NL80211_CHAN_HT40MINUS", \
+     "NL80211_CHAN_HT40PLUS"}; \
+                                                                                            \
+    dev_dbg(sh->sc->dev, "%s: ch %d, type %s", __func__, _ch, _chan_type[_ch_type]); \
+    TU_SET_GEMINIA_BW(_ch_type) \
+    TU_SET_CHANNEL(_ch); \
+} while(0)
+#define TU_INIT_PLL \
+do{ \
+    u32 regval , count = 0; \
+                                                                                            \
+    MSLEEP(1); \
+                                                                                            \
+    REG32_W(ADR_PMU_REG_2, 0xa51a8800); \
+    do \
+    { \
+        MSLEEP(1); \
+        regval = REG32_R(ADR_PMU_STATE_REG); \
+        count ++ ; \
+        if (regval == 3) \
+            break; \
+        if (count > 100){ \
+            dev_dbg(sh->sc->dev, " PLL initial fails "); \
+            break; \
+        } \
+    } while (1); \
+                                                                                            \
+    MSLEEP(1); \
+                                                                                            \
+    REG32_W(ADR_WIFI_PHY_COMMON_SYS_REG, 0x80000000); \
+                                                                                            \
+    REG32_W(ADR_CLOCK_SELECTION, 0x00000004); \
+    MSLEEP(1); \
+} while(0)
+#define TU_INIT_GEMINIA_CAL \
+do{ \
+    int i ; \
+    u32 wifi_dc_addr, reg_val; \
+                                                                                            \
+                                                                                            \
+    SET_RG_GEMINIA_HS_3WIRE_MANUAL(0); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_GEMINIA_HW_PINSEL(0); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER, \
+        ((1 << RG_GEMINIA_EN_RX_ADC_SFT) | (0 <<RG_GEMINIA_RX_ADC_MANUAL_SFT)), 0, \
+        (RG_GEMINIA_EN_RX_ADC_I_MSK & RG_GEMINIA_RX_ADC_MANUAL_I_MSK)); \
+    UDELAY(50); \
+                                                                                            \
+    dev_dbg(sh->sc->dev, "--------- reset Calibration result----------------"); \
+    for (i = 0; i < 22; i++) { \
+        wifi_dc_addr = (ADR_GEMINIA_WF_DCOC_IDAC_REGISTER1)+ (i << 2); \
+                                                                                            \
+        UDELAY(50); \
+        reg_val = REG32_R(wifi_dc_addr); \
+        dev_dbg(sh->sc->dev, "addr %x : val %x, ", wifi_dc_addr, reg_val); \
+    } \
+                                                                                            \
+    dev_dbg(sh->sc->dev, "Start WiFi Rx DC calibration..."); \
+                                                                                            \
+                                                                                            \
+    SET_RG_GEMINIA_MODE_MANUAL(1); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_GEMINIA_MODE(6); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_GEMINIA_CAL_INDEX(1); \
+                                                                                            \
+    MSLEEP(10); \
+                                                                                            \
+    dev_dbg(sh->sc->dev, "--------------------------------------------"); \
+    dev_dbg(sh->sc->dev, "--------- Calibration result----------------"); \
+    for (i = 0; i < 22; i++) { \
+       wifi_dc_addr = (ADR_GEMINIA_WF_DCOC_IDAC_REGISTER1)+ (i << 2); \
+       dev_dbg(sh->sc->dev, "addr %x : val %x, ", wifi_dc_addr, REG32_R(wifi_dc_addr)); \
+    } \
+                                                                                            \
+    SET_RG_GEMINIA_CAL_INDEX(0); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_GEMINIA_MODE(1); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_GEMINIA_MODE_MANUAL(0); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_GEMINIA_HS_3WIRE_MANUAL(1); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_GEMINIA_HW_PINSEL(1); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER, \
+        ((0 << RG_GEMINIA_EN_RX_ADC_SFT) | (1 <<RG_GEMINIA_RX_ADC_MANUAL_SFT)), 0, \
+        (RG_GEMINIA_EN_RX_ADC_I_MSK & RG_GEMINIA_RX_ADC_MANUAL_I_MSK)); \
+    UDELAY(50); \
+} while(0)
+#define TU_INIT_GEMINIA_TRX \
+do{ \
+   int val, mask; \
+                                                                                            \
+    SET_RG_GEMINIA_LOAD_RFTABLE_RDY(1); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_GEMINIA_HS_3WIRE_MANUAL(1); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_GEMINIA_HW_PINSEL(1); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_GEMINIA_TXGAIN_PHYCTRL(0); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_GEMINIA_TX_GAIN(3); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER, \
+        ((0 << RG_GEMINIA_EN_TX_DAC_SFT) | (1 <<RG_GEMINIA_TX_DAC_MANUAL_SFT)), 0, \
+        (RG_GEMINIA_EN_TX_DAC_I_MSK & RG_GEMINIA_TX_DAC_MANUAL_I_MSK)); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER, \
+        ((0 << RG_GEMINIA_EN_RX_ADC_SFT) | (1 <<RG_GEMINIA_RX_ADC_MANUAL_SFT)), 0, \
+        (RG_GEMINIA_EN_RX_ADC_I_MSK & RG_GEMINIA_RX_ADC_MANUAL_I_MSK)); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_GEMINIA_EN_TX_VTOI_2ND(1); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_GEMINIA_EN_RX_PADSW(1); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_GEMINIA_SX_FREF_DOUB(0); \
+                                                                                            \
+    MSLEEP(1); \
+                                                                                            \
+                                                                                            \
+    SET_RG_GEMINIA_PAD_MUX_SEL(1); \
+    UDELAY(50); \
+                                                                                            \
+    val = RG_GEMINIA_GPIO07_OE_MSK|RG_GEMINIA_GPIO06_OE_MSK|RG_GEMINIA_GPIO05_OE_MSK \
+         |RG_GEMINIA_GPIO04_OE_MSK|RG_GEMINIA_GPIO03_OE_MSK; \
+    mask = RG_GEMINIA_GPIO07_OE_I_MSK&RG_GEMINIA_GPIO06_OE_I_MSK&RG_GEMINIA_GPIO05_OE_I_MSK \
+         & RG_GEMINIA_GPIO04_OE_I_MSK & RG_GEMINIA_GPIO03_OE_I_MSK; \
+    SET_REG(ADR_GEMINIA_IO_REG_2, val, 0, mask); \
+    UDELAY(50); \
+    SET_RG_GEMINIA_FPGA_CLK_REF_40M_DS(1); \
+    UDELAY(50); \
+                                                                                            \
+    SET_RG_GEMINIA_FPGA_CLK_REF_40M_OE(1); \
+    MSLEEP(1); \
+} while(0)
+#define LOAD_TURISMOA_RF_TABLE \
+do{ \
+    u32 i = 0; \
+                                                                                            \
+    for( i = 0; i < sizeof(ssv6006_turismoA_rf_setting)/sizeof(ssv_cabrio_reg); i++) { \
+       REG32_W(ssv6006_turismoA_rf_setting[i].address, \
+           ssv6006_turismoA_rf_setting[i].data ); \
+       UDELAY(50); \
+    } \
+} while(0)
+#define LOAD_TURISMOA_PHY_TABLE \
+do{ \
+    u32 i = 0; \
+                                                                                            \
+    for( i = 0; i < sizeof(ssv6006_turismoA_phy_setting)/sizeof(ssv_cabrio_reg); i++) { \
+       REG32_W(ssv6006_turismoA_phy_setting[i].address, \
+           ssv6006_turismoA_phy_setting[i].data ); \
+    } \
+} while(0)
+#define TU_SET_TURISMOA_BW(_ch_type) \
+do{ \
+                                                                                            \
+    switch (_ch_type){ \
+      case NL80211_CHAN_HT20: \
+      case NL80211_CHAN_NO_HT: \
+                                                                                            \
+            SET_MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_SECONDARY(1); \
+                                                                                            \
+            SET_REG(ADR_TURISMO_TRX_MODE_REGISTER, \
+                (0 << RG_TURISMO_TRX_BW_HT40_SFT) | (1 << RG_TURISMO_TRX_BW_MANUAL_SFT), 0, \
+                (RG_TURISMO_TRX_BW_HT40_I_MSK & RG_TURISMO_TRX_BW_MANUAL_I_MSK)); \
+            UDELAY(50); \
+                                                                                            \
+            SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_0, \
+                (0 << RG_TURISMO_TRX_40M_MODE_SFT) | (0 << RG_TURISMO_TRX_LO_UP_CH_SFT), 0, \
+                (RG_TURISMO_TRX_LO_UP_CH_I_MSK & RG_TURISMO_TRX_40M_MODE_I_MSK)); \
+            UDELAY(50); \
+                                                                                            \
+            SET_REG(ADR_WIFI_PHY_COMMON_SYS_REG, \
+                (0 << RG_SYSTEM_BW_SFT) | (0 << RG_PRIMARY_CH_SIDE_SFT), 0, \
+                (RG_SYSTEM_BW_I_MSK & RG_PRIMARY_CH_SIDE_I_MSK)); \
+                                                                                            \
+            break; \
+                                                                                            \
+   case NL80211_CHAN_HT40MINUS: \
+                                                                                            \
+            SET_MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_SECONDARY(0); \
+                                                                                            \
+            SET_REG(ADR_TURISMO_TRX_MODE_REGISTER, \
+                (1 << RG_TURISMO_TRX_BW_HT40_SFT) | (1 << RG_TURISMO_TRX_BW_MANUAL_SFT), 0, \
+                (RG_TURISMO_TRX_BW_HT40_I_MSK & RG_TURISMO_TRX_BW_MANUAL_I_MSK)); \
+            UDELAY(50); \
+                                                                                            \
+            SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_0, \
+                (1 << RG_TURISMO_TRX_40M_MODE_SFT) | (0 << RG_TURISMO_TRX_LO_UP_CH_SFT), 0, \
+                (RG_TURISMO_TRX_LO_UP_CH_I_MSK & RG_TURISMO_TRX_40M_MODE_I_MSK)); \
+            UDELAY(50); \
+                                                                                            \
+            SET_REG(ADR_WIFI_PHY_COMMON_SYS_REG, \
+                (1 << RG_SYSTEM_BW_SFT) | (1<< RG_PRIMARY_CH_SIDE_SFT), 0, \
+                (RG_SYSTEM_BW_I_MSK & RG_PRIMARY_CH_SIDE_I_MSK)); \
+                                                                                            \
+            break; \
+   case NL80211_CHAN_HT40PLUS: \
+                                                                                            \
+            SET_MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_SECONDARY(0); \
+                                                                                            \
+            SET_REG(ADR_TURISMO_TRX_MODE_REGISTER, \
+                (1 << RG_TURISMO_TRX_BW_HT40_SFT) | (1 << RG_TURISMO_TRX_BW_MANUAL_SFT), 0, \
+                (RG_TURISMO_TRX_BW_HT40_I_MSK & RG_TURISMO_TRX_BW_MANUAL_I_MSK)); \
+            UDELAY(50); \
+                                                                                            \
+            SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_0, \
+                (1 << RG_TURISMO_TRX_40M_MODE_SFT) | (1 << RG_TURISMO_TRX_LO_UP_CH_SFT), 0, \
+                (RG_TURISMO_TRX_LO_UP_CH_I_MSK | RG_TURISMO_TRX_40M_MODE_I_MSK)); \
+            UDELAY(50); \
+                                                                                            \
+            SET_REG(ADR_WIFI_PHY_COMMON_SYS_REG, \
+                (1 << RG_SYSTEM_BW_SFT) | (0 << RG_PRIMARY_CH_SIDE_SFT), 0, \
+                (RG_SYSTEM_BW_I_MSK & RG_PRIMARY_CH_SIDE_I_MSK)); \
+            UDELAY(50); \
+                                                                                            \
+            break; \
+      default: \
+            break; \
+    } \
+    UDELAY(50); \
+} while(0)
+#define TURISMOA_SET_5G_TXPWR(_ch) \
+do{ \
+                                                                                            \
+                                                                                            \
+    u8 pwr_paras[3][7] = {{ 7, 8, 7, 7, 7}, \
+                           { 4, 8, 4, 4, 7}, \
+                           { 3, 8, 3, 3, 3}}; \
+    enum band { FRQ5400LO, FRQ5500LO, FRQ5500HI}; \
+    int idx; \
+                                                                                            \
+    if (_ch <=64) { \
+        idx = FRQ5400LO; \
+    } else if (_ch < 100) { \
+        idx = FRQ5500LO; \
+    } else { \
+        idx = FRQ5500HI; \
+    } \
+    SET_RG_TURISMO_TRX_TX_GAIN_MANUAL(1); \
+    UDELAY(50); \
+                                                                                            \
+    SET_REG(ADR_TURISMO_TRX_5G_TX_FE_REGISTER, \
+        ((1 << RG_TURISMO_TRX_5G_TXPGA_CAPSW_MANUAL_SFT) | \
+         (pwr_paras[idx][0] << RG_TURISMO_TRX_5G_TXPGA_CAPSW_SFT) | \
+         (pwr_paras[idx][1] << RG_TURISMO_TRX_5G_PABIAS_CTRL_SFT) | \
+         (pwr_paras[idx][2] << RG_TURISMO_TRX_5G_TX_PA1_VCAS_SFT) | \
+         (pwr_paras[idx][3] << RG_TURISMO_TRX_5G_TX_PA2_VCAS_SFT) | \
+         (pwr_paras[idx][4] << RG_TURISMO_TRX_5G_TX_PA3_VCAS_SFT)), 0, \
+        (RG_TURISMO_TRX_5G_TXPGA_CAPSW_MANUAL_I_MSK & RG_TURISMO_TRX_5G_TXPGA_CAPSW_I_MSK & \
+         RG_TURISMO_TRX_5G_PABIAS_CTRL_I_MSK & RG_TURISMO_TRX_5G_TX_PA1_VCAS_I_MSK & \
+         RG_TURISMO_TRX_5G_TX_PA2_VCAS_I_MSK & RG_TURISMO_TRX_5G_TX_PA3_VCAS_I_MSK)); \
+    UDELAY(50); \
+                                                                                            \
+    SET_REG(ADR_TURISMO_TRX_5G_TX_REGISTER, \
+        ((0x3f <<RG_TURISMO_TRX_5G_TXPGA_MAIN_SFT) | \
+         (0 << RG_TURISMO_TRX_5G_TXPGA_STEER_SFT) | \
+         (2 << RG_TURISMO_TRX_5G_TXMOD_GMCELL_SFT) | \
+         (3<< RG_TURISMO_TRX_5G_TX_GAIN_SFT)), 0, \
+        ( RG_TURISMO_TRX_5G_TXPGA_MAIN_I_MSK & RG_TURISMO_TRX_5G_TXPGA_STEER_I_MSK & \
+          RG_TURISMO_TRX_5G_TXMOD_GMCELL_I_MSK & RG_TURISMO_TRX_5G_TX_GAIN_I_MSK)); \
+    UDELAY(50); \
+                                                                                            \
+    SET_RG_TURISMO_TRX_5G_TX_GAIN(3); \
+    UDELAY(50); \
+                                                                                            \
+    SET_REG(ADR_TURISMO_TRX_2_4G_TX_REGISTER, \
+        ((0 << RG_TURISMO_TRX_TX_VTOI_CURRENT_SFT | 3 << RG_TURISMO_TRX_TX_VTOI_GM_SFT)), 0,\
+        (RG_TURISMO_TRX_TX_VTOI_CURRENT_I_MSK & RG_TURISMO_TRX_TX_VTOI_GM_I_MSK)); \
+    UDELAY(50); \
+                                                                                            \
+    SET_REG(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER, \
+        (( 0 << RG_TURISMO_TRX_5G_TX_DACLPF_ICOARSE_SFT \
+        | 0xc << RG_TURISMO_TRX_5G_TX_DAC_QOFFSET_SFT \
+        |0xc << RG_TURISMO_TRX_5G_TX_DAC_IOFFSET_SFT)), 0, \
+        ( RG_TURISMO_TRX_5G_TX_DACLPF_ICOARSE_I_MSK&RG_TURISMO_TRX_5G_TX_DAC_QOFFSET_I_MSK& \
+          RG_TURISMO_TRX_5G_TX_DAC_IOFFSET_I_MSK)); \
+    UDELAY(50); \
+                                                                                            \
+} while(0)
+#define TURISMOA_SET_5G_CHANNEL(_ch) \
+do{ \
+                                                                                            \
+    TURISMOA_SET_5G_TXPWR(_ch); \
+                                                                                            \
+    SET_RG_RF_5G_BAND(1); \
+                                                                                            \
+                                                                                            \
+    SET_RG_MODE_MANUAL(1); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_SX5GB_RFCH_MAP_EN(1); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_SX5GB_CHANNEL(_ch); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_MODE(0); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_MODE(7); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_MODE_MANUAL(0); \
+    UDELAY(50); \
+                                                                                            \
+} while(0)
+#define TURISMOA_SET_2G_TXPWR \
+do{ \
+    SET_RG_TURISMO_TRX_TX_GAIN_MANUAL(0); \
+    UDELAY(50); \
+                                                                                            \
+    SET_RG_TURISMO_TRX_TX_GAIN(3); \
+    UDELAY(50); \
+                                                                                            \
+    SET_REG(ADR_TURISMO_TRX_2_4G_TX_REGISTER, \
+        ((0 << RG_TURISMO_TRX_TX_VTOI_CURRENT_SFT|1 << RG_TURISMO_TRX_TX_VTOI_GM_SFT)), 0, \
+        (RG_TURISMO_TRX_TX_VTOI_CURRENT_I_MSK & RG_TURISMO_TRX_TX_VTOI_GM_I_MSK) ); \
+    UDELAY(50); \
+} while(0)
+#define TURISMOA_SET_2G_CHANNEL(_ch) \
+do{ \
+                                                                                            \
+    TURISMOA_SET_2G_TXPWR; \
+                                                                                            \
+    SET_RG_RF_5G_BAND(0); \
+                                                                                            \
+                                                                                            \
+    SET_RG_MODE_MANUAL(1); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_SX_RFCH_MAP_EN(1); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_SX_CHANNEL(_ch); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_MODE(0); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_MODE(3); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_MODE_MANUAL(0); \
+    UDELAY(50); \
+                                                                                            \
+} while(0)
+#define TU_CHANGE_TURISMOA_CHANNEL(_ch,_ch_type) \
+do{ \
+    const char *chan_type[]={"NL80211_CHAN_NO_HT", \
+     "NL80211_CHAN_HT20", \
+     "NL80211_CHAN_HT40MINUS", \
+     "NL80211_CHAN_HT40PLUS"}; \
+                                                                                            \
+    dev_dbg(sh->sc->dev, "%s: ch %d, type %s", __func__, _ch, chan_type[_ch_type]); \
+    TU_SET_TURISMOA_BW(_ch_type); \
+    if ( _ch <=14 && _ch >=1){ \
+        SET_MTX_DUR_RSP_SIFS_G(10); \
+     SET_MTX_DUR_RSP_SIFS_G(0); \
+     SET_TX2TX_SIFS(13); \
+        TURISMOA_SET_2G_CHANNEL( _ch); \
+    } else if (_ch >=34){ \
+     SET_MTX_DUR_RSP_SIFS_G(16); \
+     SET_MTX_DUR_RSP_SIFS_G(6); \
+     SET_TX2TX_SIFS(19); \
+                                                                                            \
+                                                                                            \
+        if ((_ch_type == NL80211_CHAN_HT40MINUS)||(_ch_type == NL80211_CHAN_HT40PLUS)){ \
+                                                                                            \
+            SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_0, \
+                (0 << RG_TURISMO_TRX_40M_MODE_SFT) | (0 << RG_TURISMO_TRX_LO_UP_CH_SFT), 0, \
+                (RG_TURISMO_TRX_LO_UP_CH_I_MSK & RG_TURISMO_TRX_40M_MODE_I_MSK)); \
+            UDELAY(50); \
+                                                                                            \
+            if (_ch_type == NL80211_CHAN_HT40MINUS) { \
+                _ch = _ch - 2; \
+            } else { \
+                _ch = _ch + 2; \
+            } \
+        } \
+        TURISMOA_SET_5G_CHANNEL(_ch); \
+    } else { \
+        dev_dbg(sh->sc->dev, "invalid channel %d", _ch); \
+    } \
+} while(0)
+#define TU_INIT_TURISMOA_CALI \
+do{ \
+    int i ; \
+    u32 wifi_dc_addr; \
+                                                                                            \
+                                                                                            \
+    SET_RG_TURISMO_TRX_HS_3WIRE_MANUAL(0); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_TURISMO_TRX_MODE_BY_HS_3WIRE(0); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_TURISMO_TRX_HW_PINSEL(0); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER, \
+        ((1 << RG_TURISMO_TRX_EN_RX_ADC_SFT) | (0 <<RG_TURISMO_TRX_RX_ADC_MANUAL_SFT)), 0, \
+        (RG_TURISMO_TRX_EN_RX_ADC_I_MSK & RG_TURISMO_TRX_RX_ADC_MANUAL_I_MSK)); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_TURISMO_TRX_MODE_MANUAL(1); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_TURISMO_TRX_MODE(1); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_TURISMO_TRX_CAL_INDEX(1); \
+                                                                                            \
+    MSLEEP(10); \
+                                                                                            \
+    dev_dbg(sh->sc->dev, "--------------------------------------------"); \
+    dev_dbg(sh->sc->dev, "--------- 2.4 G Calibration result----------------"); \
+    for (i = 0; i < 22; i++) { \
+       wifi_dc_addr = (ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER1)+ (i << 2); \
+       dev_dbg(sh->sc->dev, "addr %x : val %x, ", wifi_dc_addr, REG32_R(wifi_dc_addr)); \
+    } \
+    SET_RG_TURISMO_TRX_CAL_INDEX(0); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_TURISMO_TRX_MODE(0); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_TURISMO_TRX_MODE(1); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_TURISMO_TRX_CAL_INDEX(9); \
+                                                                                            \
+    MSLEEP(10); \
+                                                                                            \
+    dev_dbg(sh->sc->dev, "--------------------------------------------"); \
+    dev_dbg(sh->sc->dev, "--------- 5 G Calibration result----------------"); \
+    for (i = 0; i < 21; i++) { \
+       wifi_dc_addr = (ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER1)+ (i << 2); \
+       dev_dbg(sh->sc->dev, "addr %x : val %x, ", wifi_dc_addr, REG32_R(wifi_dc_addr)); \
+    } \
+    SET_RG_TURISMO_TRX_CAL_INDEX(0); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_TURISMO_TRX_MODE(0); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_TURISMO_TRX_MODE_MANUAL(0); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_TURISMO_TRX_HS_3WIRE_MANUAL(1); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_TURISMO_TRX_MODE_BY_HS_3WIRE(1); \
+    UDELAY(50); \
+                                                                                            \
+    SET_RG_TURISMO_TRX_HW_PINSEL(1); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER, \
+        ((0 << RG_TURISMO_TRX_EN_RX_ADC_SFT) | (1 <<RG_TURISMO_TRX_RX_ADC_MANUAL_SFT)), 0, \
+        (RG_TURISMO_TRX_EN_RX_ADC_I_MSK & RG_TURISMO_TRX_RX_ADC_MANUAL_I_MSK)); \
+    UDELAY(50); \
+} while(0)
+#define TU_INIT_TURISMOA_TRX \
+do{ \
+   int val, mask; \
+                                                                                            \
+    SET_RG_TURISMO_TRX_LOAD_RFTABLE_RDY(1); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_TURISMO_TRX_HS_3WIRE_MANUAL(1); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_TURISMO_TRX_MODE_BY_HS_3WIRE(1); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_TURISMO_TRX_HW_PINSEL(1); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_TURISMO_TRX_TXGAIN_PHYCTRL(0); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_TURISMO_TRX_TX_GAIN(3); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER, \
+        ((0 << RG_TURISMO_TRX_EN_TX_DAC_SFT) | (1 <<RG_TURISMO_TRX_TX_DAC_MANUAL_SFT)), 0, \
+        (RG_TURISMO_TRX_EN_TX_DAC_I_MSK & RG_TURISMO_TRX_TX_DAC_MANUAL_I_MSK)); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER, \
+        ((0 << RG_TURISMO_TRX_EN_RX_ADC_SFT) | (1 <<RG_TURISMO_TRX_RX_ADC_MANUAL_SFT)), 0, \
+        (RG_TURISMO_TRX_EN_RX_ADC_I_MSK & RG_TURISMO_TRX_RX_ADC_MANUAL_I_MSK)); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_TURISMO_TRX_EN_TX_VTOI_2ND(1); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_TURISMO_TRX_EN_RX_PADSW(1); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_TURISMO_TRX_PAD_MUX_SEL(1); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    val = RG_TURISMO_TRX_GPIO07_OE_MSK|RG_TURISMO_TRX_GPIO06_OE_MSK \
+         |RG_TURISMO_TRX_GPIO05_OE_MSK|RG_TURISMO_TRX_GPIO04_OE_MSK \
+         |RG_TURISMO_TRX_GPIO03_OE_MSK; \
+    mask = RG_TURISMO_TRX_GPIO07_OE_I_MSK&RG_TURISMO_TRX_GPIO06_OE_I_MSK \
+         &RG_TURISMO_TRX_GPIO05_OE_I_MSK&RG_TURISMO_TRX_GPIO04_OE_I_MSK \
+         &RG_TURISMO_TRX_GPIO03_OE_I_MSK; \
+    SET_REG(ADR_TURISMO_TRX_IO_REG_2, val, 0, mask); \
+    UDELAY(50); \
+                                                                                            \
+    SET_RG_TURISMO_TRX_FPGA_CLK_REF_40M_EN(1); \
+    UDELAY(50); \
+                                                                                            \
+    SET_RG_TURISMO_TRX_GPIO17_DS(1); \
+    UDELAY(50); \
+                                                                                            \
+    SET_RG_TURISMO_TRX_GPIO17_OE(1); \
+    MSLEEP(1); \
+} while(0)
+#define INIT_TURISMOA_SYS \
+do{ \
+    LOAD_TURISMOA_RF_TABLE; \
+    TU_INIT_TURISMOA_TRX; \
+    TU_INIT_PLL; \
+    REG32_W(ADR_WIFI_PHY_COMMON_ENABLE_REG, 0); \
+    LOAD_TURISMOA_PHY_TABLE; \
+    TU_INIT_TURISMOA_CALI; \
+} while(0)
+#define TU_INIT_TURISMOB_PLL \
+do{ \
+    u32 regval , count = 0; \
+                                                                                            \
+                                                                                            \
+    SET_RG_LOAD_RFTABLE_RDY(0x1); \
+    do \
+    { \
+        MSLEEP(1); \
+        regval = REG32_R(ADR_PMU_STATE_REG); \
+        count ++ ; \
+        if (regval == 0x13) \
+            break; \
+        if (count > 100){ \
+            dev_dbg(sh->sc->dev, " PLL initial fails "); \
+            break; \
+        } \
+    } while (1); \
+                                                                                            \
+    MSLEEP(1); \
+                                                                                            \
+    REG32_W(ADR_WIFI_PHY_COMMON_SYS_REG, 0x80010000); \
+                                                                                            \
+    REG32_W(ADR_CLOCK_SELECTION, 0x00000004); \
+    MSLEEP(1); \
+} while(0)
+#define TU_INIT_TURISMOB_CALI_ORG \
+do{ \
+    int i ; \
+    u32 wifi_dc_addr; \
+                                                                                            \
+                                                                                            \
+    SET_RG_MODE_MANUAL(1); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_MODE(1); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_CAL_INDEX(1); \
+                                                                                            \
+    MSLEEP(10); \
+                                                                                            \
+    dev_dbg(sh->sc->dev, "--------------------------------------------"); \
+    dev_dbg(sh->sc->dev, "--------- 2.4 G Rx DC Calibration result----------------"); \
+    for (i = 0; i < 22; i++) { \
+       wifi_dc_addr = (ADR_WF_DCOC_IDAC_REGISTER1)+ (i << 2); \
+       dev_dbg(sh->sc->dev, "addr %x : val %x, ", wifi_dc_addr, REG32_R(wifi_dc_addr)); \
+    } \
+    SET_RG_CAL_INDEX(0); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_MODE(0); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_MODE(1); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_CAL_INDEX(9); \
+                                                                                            \
+    MSLEEP(10); \
+                                                                                            \
+    dev_dbg(sh->sc->dev, "--------------------------------------------"); \
+    dev_dbg(sh->sc->dev, "--------- 5 G Rx DC Calibration result----------------"); \
+    for (i = 0; i < 21; i++) { \
+       wifi_dc_addr = (ADR_5G_DCOC_IDAC_REGISTER1)+ (i << 2); \
+       dev_dbg(sh->sc->dev, "addr %x : val %x, ", wifi_dc_addr, REG32_R(wifi_dc_addr)); \
+    } \
+    SET_RG_CAL_INDEX(0); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_MODE(0); \
+    UDELAY(50); \
+                                                                                            \
+    SET_RG_MODE_MANUAL(0); \
+    UDELAY(50); \
+} while(0)
+#define TU_INIT_TURISMOB_2G_CALI_ORG \
+do{ \
+    int i ; \
+    u32 wifi_dc_addr; \
+                                                                                            \
+                                                                                            \
+    SET_RG_MODE_MANUAL(1); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_MODE(1); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_CAL_INDEX(1); \
+                                                                                            \
+    MSLEEP(10); \
+                                                                                            \
+    dev_dbg(sh->sc->dev, "--------------------------------------------"); \
+    dev_dbg(sh->sc->dev, "--------- 2.4 G Rx DC Calibration result----------------"); \
+    for (i = 0; i < 22; i++) { \
+       wifi_dc_addr = (ADR_WF_DCOC_IDAC_REGISTER1)+ (i << 2); \
+       dev_dbg(sh->sc->dev, "addr %x : val %x, ", wifi_dc_addr, REG32_R(wifi_dc_addr)); \
+    } \
+                                                                                            \
+    SET_RG_CAL_INDEX(0); \
+    UDELAY(50); \
+                                                                                            \
+                                                                                            \
+    SET_RG_MODE(0); \
+    UDELAY(50); \
+                                                                                            \
+    SET_RG_MODE_MANUAL(0); \
+    UDELAY(50); \
+} while(0)
+#define TURISMOB_PRE_CAL \
+do { \
+                                                                                            \
+    SET_RG_MODE(MODE_STANDBY); \
+                                                                                            \
+    SET_RG_CAL_INDEX(CAL_IDX_NONE); \
+                                                                                            \
+    SET_RG_MODE_MANUAL(1); \
+                                                                                            \
+    SET_RG_MODE(MODE_CALIBRATION); \
+} while(0)
+#define TURISMOB_POST_CAL \
+do { \
+                                                                                            \
+    SET_RG_MODE(MODE_STANDBY); \
+                                                                                            \
+                                                                                            \
+    SET_RG_MODE_MANUAL(0); \
+} while(0)
+#define TURISMO_INTER_CAL \
+do { \
+                                                                                            \
+    SET_RG_MODE(MODE_STANDBY); \
+                                                                                            \
+                                                                                            \
+                                                                                            \
+    UDELAY(100); \
+                                                                                            \
+                                                                                            \
+                                                                                            \
+                                                                                            \
+    SET_RG_MODE(MODE_CALIBRATION); \
+                                                                                            \
+} while(0)
+#define TURISMOB_2P4G_RXDC_CAL \
+do { \
+    int i ; \
+    u32 wifi_dc_addr; \
+                                                                                            \
+                                                                                            \
+                                                                                            \
+                                                                                            \
+                                                                                            \
+    SET_RG_CAL_INDEX(CAL_IDX_WIFI2P4G_RXDC); \
+                                                                                            \
+    MSLEEP(10); \
+                                                                                            \
+    dev_dbg(sh->sc->dev, "--------------------------------------------"); \
+    dev_dbg(sh->sc->dev, "--------- 2.4 G Rx DC Calibration result----------------"); \
+    for (i = 0; i < 21; i++) { \
+       wifi_dc_addr = (ADR_WF_DCOC_IDAC_REGISTER1)+ (i << 2); \
+       dev_dbg(sh->sc->dev, "addr %x : val %x, ", wifi_dc_addr, REG32_R(wifi_dc_addr)); \
+    } \
+    SET_RG_CAL_INDEX(0); \
+                                                                                            \
+                                                                                            \
+                                                                                            \
+} while(0)
+#define TURISMOB_5G_RXDC_CAL \
+do{ \
+    int i ; \
+    u32 wifi_dc_addr; \
+                                                                                            \
+                                                                                            \
+                                                                                            \
+                                                                                            \
+                                                                                            \
+    SET_RG_CAL_INDEX(CAL_IDX_WIFI5G_RXDC); \
+                                                                                            \
+    MSLEEP(10); \
+                                                                                            \
+    dev_dbg(sh->sc->dev, "--------------------------------------------"); \
+    dev_dbg(sh->sc->dev, "--------- 5 G Rx DC Calibration result----------------"); \
+    for (i = 0; i < 21; i++) { \
+       wifi_dc_addr = (ADR_5G_DCOC_IDAC_REGISTER1)+ (i << 2); \
+       dev_dbg(sh->sc->dev, "addr %x : val %x, ", wifi_dc_addr, REG32_R(wifi_dc_addr)); \
+    } \
+                                                                                            \
+    SET_RG_CAL_INDEX(0); \
+                                                                                            \
+                                                                                            \
+                                                                                            \
+} while(0)
+#define TURISMOB_BW20_RXRC_CAL \
+do{ \
+    int count = 0; \
+                                                                                            \
+    dev_dbg(sh->sc->dev, "--------------------------------------------"); \
+    dev_dbg(sh->sc->dev, "Before WiFi BW20 RG_WF_RX_ABBCTUNE: %d", GET_RG_WF_RX_ABBCTUNE); \
+                                                                                            \
+    SET_RG_RX_RCCAL_DELAY(2); \
+                                                                                            \
+    SET_REG(ADR_RF_D_CAL_TOP_6, \
+        (0xe5 << RG_RX_RCCAL_TARG_SFT) | (0 << RG_RCCAL_POLAR_INV_SFT), 0, \
+        (RG_RX_RCCAL_TARG_I_MSK & RG_RCCAL_POLAR_INV_I_MSK)); \
+                                                                                            \
+    SET_RG_PGAG_RCCAL(3); \
+                                                                                            \
+    SET_RG_TONE_SCALE(0x80); \
+                                                                                            \
+                                                                                            \
+                                                                                            \
+                                                                                            \
+                                                                                            \
+    SET_RG_CAL_INDEX(CAL_IDX_BW20_RXRC); \
+                                                                                            \
+    while (GET_RO_RCCAL_DONE == 0){ \
+        count ++; \
+        if (count >100) { \
+            break; \
+        } \
+        MSLEEP(1); \
+    } \
+                                                                                            \
+    MSLEEP(10); \
+    dev_dbg(sh->sc->dev, "--------------------------------------------%d", count); \
+    dev_dbg(sh->sc->dev, "WiFi BW20 RG_WF_RX_ABBCTUNE CAL RESULT: %d", GET_RG_WF_RX_ABBCTUNE); \
+                                                                                            \
+                                                                                            \
+    SET_RG_CAL_INDEX(0); \
+                                                                                            \
+} while(0)
+#define TURISMOB_BW40_RXRC_CAL \
+do { \
+    int count = 0; \
+                                                                                            \
+                                                                                            \
+    dev_dbg(sh->sc->dev, "--------------------------------------------"); \
+    dev_dbg(sh->sc->dev, "Before WiFi BW40 RG_WF_RX_N_ABBCTUNE: %d", GET_RG_WF_N_RX_ABBCTUNE); \
+                                                                                            \
+    SET_RG_RX_N_RCCAL_DELAY(2); \
+                                                                                            \
+    SET_RG_PHASE_2P5M(0x800); \
+                                                                                            \
+    SET_REG(ADR_RF_D_CAL_TOP_6, \
+        (0x197 << RG_RX_RCCAL_40M_TARG_SFT) | (0 << RG_RCCAL_POLAR_INV_SFT), 0, \
+        (RG_RX_RCCAL_40M_TARG_I_MSK & RG_RCCAL_POLAR_INV_I_MSK)); \
+                                                                                            \
+    SET_RG_ALPHA_SEL(2); \
+                                                                                            \
+    SET_RG_PHASE_35M(0x5800); \
+                                                                                            \
+    SET_RG_PGAG_RCCAL(3); \
+                                                                                            \
+    SET_RG_TONE_SCALE(0x80); \
+                                                                                            \
+                                                                                            \
+                                                                                            \
+                                                                                            \
+                                                                                            \
+    SET_RG_CAL_INDEX(CAL_IDX_BW40_RXRC); \
+                                                                                            \
+    while (GET_RO_RCCAL_DONE == 0){ \
+        count ++; \
+        if (count >100) { \
+            break; \
+        } \
+        MSLEEP(1); \
+    } \
+                                                                                            \
+    MSLEEP(10); \
+    dev_dbg(sh->sc->dev, "--------------------------------------------%d", count); \
+    dev_dbg(sh->sc->dev, "WiFi BW40 RG_WF_N_RX_ABBCTUNE CAL RESULT: %d", GET_RG_WF_N_RX_ABBCTUNE); \
+                                                                                            \
+                                                                                            \
+    SET_RG_CAL_INDEX(0); \
+} while(0)
+#define TURISMOB_TXDC_CAL \
+do { \
+    int count = 0; \
+                                                                                            \
+                                                                                            \
+    dev_dbg(sh->sc->dev, "--------------------------------------------"); \
+    dev_dbg(sh->sc->dev, "Before txdc calibration WiFi 2P4G Tx DAC IOFFSET: %d, QOFFSET %d", \
+         GET_RG_WF_TX_DAC_IOFFSET, GET_RG_WF_TX_DAC_QOFFSET); \
+                                                                                            \
+    SET_RG_TONE_SCALE(0x80); \
+                                                                                            \
+    SET_REG(ADR_CALIBRATION_GAIN_REGISTER0, \
+        (0x6 << RG_TX_GAIN_TXCAL_SFT) | (0x0 << RG_PGAG_TXCAL_SFT), 0, \
+        (RG_TX_GAIN_TXCAL_I_MSK & RG_PGAG_TXCAL_I_MSK)); \
+                                                                                            \
+    SET_RG_PRE_DC_AUTO(1); \
+                                                                                            \
+    SET_RG_TX_IQCAL_TIME(1); \
+                                                                                            \
+    SET_RG_PHASE_1M(0x7FF); \
+    SET_RG_PHASE_RXIQ_1M(0x7FF); \
+                                                                                            \
+    SET_RG_ALPHA_SEL(2); \
+                                                                                            \
+                                                                                            \
+                                                                                            \
+                                                                                            \
+                                                                                            \
+    SET_RG_CAL_INDEX(CAL_IDX_WIFI2P4G_TXLO); \
+                                                                                            \
+    while (GET_RO_TXDC_DONE == 0){ \
+        count ++; \
+        if (count >100) { \
+            break; \
+        } \
+        MSLEEP(1); \
+    } \
+                                                                                            \
+    MSLEEP(10); \
+    dev_dbg(sh->sc->dev, "--------------------------------------------%d", count); \
+    dev_dbg(sh->sc->dev, "After txdc calibration WiFi 2P4G Tx DAC IOFFSET: %d, QOFFSET %d", \
+         GET_RG_WF_TX_DAC_IOFFSET, GET_RG_WF_TX_DAC_QOFFSET); \
+                                                                                            \
+                                                                                            \
+    SET_RG_CAL_INDEX(0); \
+} while(0)
+#define TURISMOB_TXIQ_CAL \
+do { \
+    int count = 0; \
+                                                                                            \
+                                                                                            \
+    dev_dbg(sh->sc->dev, "--------------------------------------------"); \
+    dev_dbg(sh->sc->dev, "before tx iq calibration, tx alpha: %d, tx theta %d", \
+         GET_RO_TX_IQ_ALPHA, GET_RO_TX_IQ_THETA); \
+                                                                                            \
+    SET_RG_TONE_SCALE(0x80); \
+                                                                                            \
+    SET_REG(ADR_CALIBRATION_GAIN_REGISTER0, \
+        (0x6 << RG_TX_GAIN_TXCAL_SFT) | (0x0 << RG_PGAG_TXCAL_SFT), 0, \
+        (RG_TX_GAIN_TXCAL_I_MSK & RG_PGAG_TXCAL_I_MSK)); \
+                                                                                            \
+    SET_RG_PRE_DC_AUTO(1); \
+                                                                                            \
+    SET_RG_TX_IQCAL_TIME(1); \
+                                                                                            \
+    SET_RG_PHASE_1M(0x7FF); \
+    SET_RG_PHASE_RXIQ_1M(0x7FF); \
+                                                                                            \
+    SET_RG_ALPHA_SEL(2); \
+                                                                                            \
+                                                                                            \
+                                                                                            \
+                                                                                            \
+                                                                                            \
+    SET_RG_CAL_INDEX(CAL_IDX_WIFI2P4G_TXIQ); \
+                                                                                            \
+    while (GET_RO_TXIQ_DONE == 0){ \
+        count ++; \
+        if (count >100) { \
+            break; \
+        } \
+        MSLEEP(1); \
+    } \
+                                                                                            \
+    MSLEEP(10); \
+    dev_dbg(sh->sc->dev, "--------------------------------------------%d", count); \
+    dev_dbg(sh->sc->dev, "After tx iq calibration, tx alpha: %d, tx theta %d", \
+         GET_RO_TX_IQ_ALPHA, GET_RO_TX_IQ_THETA); \
+                                                                                            \
+                                                                                            \
+    SET_RG_CAL_INDEX(0); \
+                                                                                            \
+} while(0)
+#define TURISMOB_RXIQ_CAL \
+do { \
+    int count = 0; \
+                                                                                            \
+                                                                                            \
+    dev_dbg(sh->sc->dev, "--------------------------------------------"); \
+    dev_dbg(sh->sc->dev, "Before rx iq calibration, rx alpha: %d, rx theta %d", \
+         GET_RO_RX_IQ_ALPHA, GET_RO_RX_IQ_THETA); \
+                                                                                            \
+    SET_RG_RFG_RXIQCAL(0x0); \
+                                                                                            \
+    SET_RG_PGAG_RXIQCAL(0x3); \
+                                                                                            \
+    SET_RG_TX_GAIN_RXIQCAL(0x6); \
+                                                                                            \
+    SET_RG_TONE_SCALE(0x80); \
+                                                                                            \
+    SET_RG_PRE_DC_AUTO(1); \
+                                                                                            \
+    SET_RG_TX_IQCAL_TIME(1); \
+                                                                                            \
+    SET_RG_PHASE_1M(0x7FF); \
+    SET_RG_PHASE_RXIQ_1M(0x7FF); \
+                                                                                            \
+    SET_RG_ALPHA_SEL(2); \
+                                                                                            \
+                                                                                            \
+                                                                                            \
+                                                                                            \
+                                                                                            \
+    SET_RG_CAL_INDEX(CAL_IDX_WIFI2P4G_RXIQ); \
+                                                                                            \
+    while (GET_RO_RXIQ_DONE == 0){ \
+        count ++; \
+        if (count >100) { \
+            break; \
+        } \
+        MSLEEP(1); \
+    } \
+                                                                                            \
+    MSLEEP(10); \
+    dev_dbg(sh->sc->dev, "--------------------------------------------%d", count); \
+    dev_dbg(sh->sc->dev, "After rx iq calibration, rx alpha: %d, rx theta %d", \
+         GET_RO_RX_IQ_ALPHA, GET_RO_RX_IQ_THETA); \
+                                                                                            \
+                                                                                            \
+    SET_RG_CAL_INDEX(0); \
+                                                                                            \
+} while(0)
+#define TURISMOB_5G_TXDC_CAL \
+do { \
+    int count = 0; \
+                                                                                            \
+    dev_dbg(sh->sc->dev, "--------------------------------------------"); \
+    dev_dbg(sh->sc->dev, "Before 5G txdc calibration WiFi 5G Tx DAC IOFFSET: %d, QOFFSET %d", \
+         GET_RG_5G_TX_DAC_IOFFSET, GET_RG_5G_TX_DAC_QOFFSET); \
+                                                                                            \
+    SET_RG_TONE_SCALE(0x80); \
+                                                                                            \
+    SET_REG(ADR_5G_CALIBRATION_TIMER_GAIN_REGISTER, \
+        (0xe << RG_5G_TX_GAIN_TXCAL_SFT) | (0x3 << RG_5G_PGAG_TXCAL_SFT), 0, \
+        (RG_5G_TX_GAIN_TXCAL_I_MSK & RG_5G_PGAG_TXCAL_I_MSK)); \
+                                                                                            \
+    SET_RG_PRE_DC_AUTO(1); \
+                                                                                            \
+    SET_RG_TX_IQCAL_TIME(1); \
+                                                                                            \
+    SET_RG_PHASE_1M(0x7FF); \
+    SET_RG_PHASE_RXIQ_1M(0x7FF); \
+                                                                                            \
+    SET_RG_ALPHA_SEL(2); \
+                                                                                            \
+                                                                                            \
+                                                                                            \
+                                                                                            \
+                                                                                            \
+    SET_RG_CAL_INDEX(CAL_IDX_WIFI5G_TXLO); \
+                                                                                            \
+    while (GET_RO_5G_TXDC_DONE == 0){ \
+        count ++; \
+        if (count >100) { \
+            break; \
+        } \
+        MSLEEP(1); \
+    } \
+                                                                                            \
+    MSLEEP(10); \
+    dev_dbg(sh->sc->dev, "--------------------------------------------%d", count); \
+    dev_dbg(sh->sc->dev, "After 5G txdc calibration WiFi 5G Tx DAC IOFFSET: %d, QOFFSET %d", \
+         GET_RG_5G_TX_DAC_IOFFSET, GET_RG_5G_TX_DAC_QOFFSET); \
+                                                                                            \
+                                                                                            \
+    SET_RG_CAL_INDEX(0); \
+                                                                                            \
+} while(0)
+#define TURISMOB_5G_TXIQ_CAL \
+{ \
+    int count = 0; \
+                                                                                            \
+                                                                                            \
+    dev_dbg(sh->sc->dev, "--------------------------------------------"); \
+    dev_dbg(sh->sc->dev, "before 5G tx iq calibration, tx alpha: %d, tx theta %d", \
+         GET_RO_TX_IQ_ALPHA, GET_RO_TX_IQ_THETA); \
+                                                                                            \
+    SET_RG_TONE_SCALE(0x80); \
+                                                                                            \
+    SET_REG(ADR_5G_CALIBRATION_TIMER_GAIN_REGISTER, \
+        (0xe << RG_5G_TX_GAIN_TXCAL_SFT) | (0x3 << RG_5G_PGAG_TXCAL_SFT), 0, \
+        (RG_5G_TX_GAIN_TXCAL_I_MSK & RG_5G_PGAG_TXCAL_I_MSK)); \
+                                                                                            \
+    SET_RG_PRE_DC_AUTO(1); \
+                                                                                            \
+    SET_RG_TX_IQCAL_TIME(1); \
+                                                                                            \
+    SET_RG_PHASE_1M(0x7FF); \
+    SET_RG_PHASE_RXIQ_1M(0x7FF); \
+                                                                                            \
+    SET_RG_ALPHA_SEL(2); \
+                                                                                            \
+                                                                                            \
+                                                                                            \
+                                                                                            \
+                                                                                            \
+    SET_RG_CAL_INDEX(CAL_IDX_WIFI5G_TXIQ); \
+                                                                                            \
+    while (GET_RO_5G_TXIQ_DONE == 0){ \
+        count ++; \
+        if (count >100) { \
+            break; \
+        } \
+        MSLEEP(1); \
+    } \
+                                                                                            \
+    MSLEEP(10); \
+    dev_dbg(sh->sc->dev, "--------------------------------------------%d", count); \
+    dev_dbg(sh->sc->dev, "After 5G tx iq calibration, tx alpha: %d, tx theta %d", \
+         GET_RO_TX_IQ_ALPHA, GET_RO_TX_IQ_THETA); \
+                                                                                            \
+                                                                                            \
+    SET_RG_CAL_INDEX(0); \
+                                                                                            \
+} while(0)
+#define TURISMOB_5G_RXIQ_CAL \
+do { \
+    int count = 0; \
+                                                                                            \
+                                                                                            \
+    dev_dbg(sh->sc->dev, "--------------------------------------------"); \
+    dev_dbg(sh->sc->dev, "Before 5G rx iq calibration, rx alpha: %d, rx theta %d", \
+         GET_RO_RX_IQ_ALPHA, GET_RO_RX_IQ_THETA); \
+                                                                                            \
+    SET_RG_5G_RFG_RXIQCAL(0x0); \
+                                                                                            \
+    SET_RG_5G_PGAG_RXIQCAL(0x3); \
+                                                                                            \
+    SET_RG_5G_TX_GAIN_RXIQCAL(0xe); \
+                                                                                            \
+    SET_RG_TONE_SCALE(0x80); \
+                                                                                            \
+    SET_RG_PRE_DC_AUTO(1); \
+                                                                                            \
+    SET_RG_TX_IQCAL_TIME(1); \
+                                                                                            \
+    SET_RG_PHASE_1M(0x7FF); \
+    SET_RG_PHASE_RXIQ_1M(0x7FF); \
+                                                                                            \
+                                                                                            \
+    SET_RG_ALPHA_SEL(2); \
+                                                                                            \
+                                                                                            \
+                                                                                            \
+                                                                                            \
+                                                                                            \
+    SET_RG_CAL_INDEX(CAL_IDX_WIFI5G_RXIQ); \
+                                                                                            \
+    while (GET_RO_5G_RXIQ_DONE == 0){ \
+        count ++; \
+        if (count >100) { \
+            break; \
+        } \
+        MSLEEP(1); \
+    } \
+                                                                                            \
+    MSLEEP(10); \
+    dev_dbg(sh->sc->dev, "--------------------------------------------%d", count); \
+    dev_dbg(sh->sc->dev, "After 5G rx iq calibration, rx alpha: %d, rx theta %d", \
+         GET_RO_RX_IQ_ALPHA, GET_RO_RX_IQ_THETA); \
+                                                                                            \
+                                                                                            \
+    SET_RG_CAL_INDEX(0); \
+                                                                                            \
+} while(0)
+#define TU_INIT_TURISMOB_CALI \
+do{ \
+    TURISMOB_PRE_CAL; \
+                                                                                            \
+    TURISMOB_2P4G_RXDC_CAL; \
+                                                                                            \
+    TURISMOB_BW20_RXRC_CAL; \
+                                                                                            \
+    TURISMOB_BW40_RXRC_CAL; \
+                                                                                            \
+    TURISMOB_TXDC_CAL; \
+                                                                                            \
+    TURISMOB_TXIQ_CAL; \
+                                                                                            \
+    TURISMOB_RXIQ_CAL; \
+                                                                                            \
+    TURISMOB_5G_RXDC_CAL; \
+                                                                                            \
+    TURISMOB_5G_TXDC_CAL; \
+                                                                                            \
+    TURISMOB_5G_TXIQ_CAL; \
+                                                                                            \
+    TURISMOB_5G_RXIQ_CAL; \
+                                                                                            \
+    TURISMOB_POST_CAL; \
+} while(0)
+#define TU_INIT_TURISMOB_2G_CALI \
+do{ \
+    TURISMOB_PRE_CAL; \
+                                                                                            \
+    TURISMOB_2P4G_RXDC_CAL; \
+                                                                                            \
+    TURISMOB_BW20_RXRC_CAL; \
+                                                                                            \
+    TURISMOB_BW40_RXRC_CAL; \
+                                                                                            \
+    TURISMOB_TXDC_CAL; \
+                                                                                            \
+    TURISMOB_TXIQ_CAL; \
+                                                                                            \
+    TURISMOB_RXIQ_CAL; \
+                                                                                            \
+    TURISMOB_POST_CAL; \
+} while(0)
+#define LOAD_TURISMOB_RF_TABLE \
+do{ \
+    u32 i = 0; \
+                                                                                            \
+    for( i = 0; i < sizeof(ssv6006_turismoB_rf_setting)/sizeof(ssv_cabrio_reg); i++) { \
+       REG32_W(ssv6006_turismoB_rf_setting[i].address, \
+           ssv6006_turismoB_rf_setting[i].data ); \
+       UDELAY(50); \
+    } \
+} while(0)
+#define LOAD_TURISMOB_PHY_TABLE \
+do{ \
+    u32 i = 0; \
+                                                                                            \
+    for( i = 0; i < sizeof(ssv6006_turismoB_phy_setting)/sizeof(ssv_cabrio_reg); i++) { \
+       REG32_W(ssv6006_turismoB_phy_setting[i].address, \
+           ssv6006_turismoB_phy_setting[i].data ); \
+    } \
+} while(0)
+#define INIT_TURISMOB_SYS(_xtal,_band) \
+do{ \
+    LOAD_TURISMOB_RF_TABLE; \
+    if (_xtal != XTAL26M){ \
+        SET_RG_DP_XTAL_FREQ(_xtal); \
+        SET_RG_SX_XTAL_FREQ(_xtal); \
+    } \
+    TU_INIT_TURISMOB_PLL; \
+    REG32_W(ADR_WIFI_PHY_COMMON_ENABLE_REG, 0); \
+    LOAD_TURISMOB_PHY_TABLE; \
+    if (_band == G_BAND_ONLY){ \
+        TU_INIT_TURISMOB_2G_CALI; \
+    } else { \
+        TU_INIT_TURISMOB_CALI; \
+    } \
+} while(0)
+#define TU_SET_TURISMOB_BW(_ch_type) \
+do{ \
+                                                                                            \
+    switch (_ch_type){ \
+      case NL80211_CHAN_HT20: \
+      case NL80211_CHAN_NO_HT: \
+                                                                                            \
+            SET_MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_SECONDARY(1); \
+                                                                                            \
+            SET_REG(ADR_WIFI_PHY_COMMON_SYS_REG, \
+                (0 << RG_PRIMARY_CH_SIDE_SFT) | (0 << RG_SYSTEM_BW_SFT), 0, \
+                (RG_PRIMARY_CH_SIDE_I_MSK & RG_SYSTEM_BW_I_MSK)); \
+            UDELAY(50); \
+                                                                                            \
+            SET_REG(ADR_DIGITAL_ADD_ON_0, \
+                (0 << RG_40M_MODE_SFT) | (0 << RG_LO_UP_CH_SFT), 0, \
+                (RG_40M_MODE_I_MSK & RG_LO_UP_CH_I_MSK)); \
+            UDELAY(50); \
+                                                                                            \
+            break; \
+                                                                                            \
+   case NL80211_CHAN_HT40MINUS: \
+                                                                                            \
+            SET_MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_SECONDARY(0); \
+                                                                                            \
+            SET_REG(ADR_WIFI_PHY_COMMON_SYS_REG, \
+                (1 << RG_PRIMARY_CH_SIDE_SFT) | (1 << RG_SYSTEM_BW_SFT), 0, \
+                (RG_PRIMARY_CH_SIDE_I_MSK & RG_SYSTEM_BW_I_MSK)); \
+            UDELAY(50); \
+                                                                                            \
+            SET_REG(ADR_DIGITAL_ADD_ON_0, \
+                (1 << RG_40M_MODE_SFT) | (0 << RG_LO_UP_CH_SFT), 0, \
+                (RG_40M_MODE_I_MSK & RG_LO_UP_CH_I_MSK)); \
+            UDELAY(50); \
+                                                                                            \
+            break; \
+   case NL80211_CHAN_HT40PLUS: \
+                                                                                            \
+            SET_MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_SECONDARY(0); \
+                                                                                            \
+            SET_REG(ADR_WIFI_PHY_COMMON_SYS_REG, \
+                (0 << RG_PRIMARY_CH_SIDE_SFT) | (1 << RG_SYSTEM_BW_SFT), 0, \
+                (RG_PRIMARY_CH_SIDE_I_MSK & RG_SYSTEM_BW_I_MSK)); \
+            UDELAY(50); \
+                                                                                            \
+            SET_REG(ADR_DIGITAL_ADD_ON_0, \
+                (1 << RG_40M_MODE_SFT) | (1 << RG_LO_UP_CH_SFT), 0, \
+                (RG_40M_MODE_I_MSK & RG_LO_UP_CH_I_MSK)); \
+            UDELAY(50); \
+                                                                                            \
+            break; \
+      default: \
+            break; \
+    } \
+} while(0)
+#define TURISMOB_SET_5G_CHANNEL(_ch) \
+do{ \
+                                                                                            \
+    SET_RG_RF_5G_BAND(1); \
+                                                                                            \
+                                                                                            \
+    SET_RG_MODE_MANUAL(1); \
+                                                                                            \
+                                                                                            \
+    SET_RG_SX5GB_RFCH_MAP_EN(1); \
+                                                                                            \
+                                                                                            \
+    SET_RG_SX5GB_CHANNEL(_ch); \
+                                                                                            \
+                                                                                            \
+    SET_RG_MODE(0); \
+                                                                                            \
+                                                                                            \
+    SET_RG_MODE(7); \
+                                                                                            \
+                                                                                            \
+    SET_RG_MODE_MANUAL(0); \
+                                                                                            \
+} while(0)
+#define TURISMOB_SET_2G_CHANNEL(_ch) \
+do{ \
+    SET_RG_RF_5G_BAND(0); \
+                                                                                            \
+                                                                                            \
+    SET_RG_MODE_MANUAL(1); \
+                                                                                            \
+                                                                                            \
+    SET_RG_SX_RFCH_MAP_EN(1); \
+                                                                                            \
+                                                                                            \
+    SET_RG_SX_CHANNEL(_ch); \
+                                                                                            \
+                                                                                            \
+    SET_RG_MODE(0); \
+                                                                                            \
+                                                                                            \
+    SET_RG_MODE(3); \
+                                                                                            \
+                                                                                            \
+    SET_RG_MODE_MANUAL(0); \
+                                                                                            \
+} while(0)
+#define TU_CHANGE_TURISMOB_CHANNEL(_ch,_ch_type) \
+do{ \
+    const char *chan_type[]={"NL80211_CHAN_NO_HT", \
+     "NL80211_CHAN_HT20", \
+     "NL80211_CHAN_HT40MINUS", \
+     "NL80211_CHAN_HT40PLUS"}; \
+                                                                                            \
+    dev_dbg(sh->sc->dev, "%s: ch %d, type %s", __func__, _ch, chan_type[_ch_type]); \
+    TU_SET_TURISMOB_BW(_ch_type); \
+    if ( _ch <=14 && _ch >=1){ \
+        SET_MTX_DUR_RSP_SIFS_G(10); \
+     SET_MTX_DUR_RSP_SIFS_G(0); \
+     SET_TX2TX_SIFS(13); \
+        TURISMOB_SET_2G_CHANNEL( _ch); \
+    } else if (_ch >=34){ \
+     SET_MTX_DUR_RSP_SIFS_G(16); \
+     SET_MTX_DUR_RSP_SIFS_G(6); \
+     SET_TX2TX_SIFS(19); \
+        TURISMOB_SET_5G_CHANNEL(_ch); \
+    } else { \
+        dev_dbg(sh->sc->dev, "invalid channel %d", _ch); \
+    } \
+} while(0)
+#define TU_INIT_TURISMOC_PLL \
+do{ \
+    u32 regval , count = 0; \
+                                                                                            \
+                                                                                            \
+    SET_RG_LOAD_RFTABLE_RDY(0x1); \
+    do \
+    { \
+        MSLEEP(1); \
+        regval = REG32_R(ADR_PMU_STATE_REG); \
+        count ++ ; \
+        if (regval == 0x13) \
+            break; \
+        if (count > 100){ \
+            dev_dbg(sh->sc->dev, " PLL initial fails "); \
+            break; \
+        } \
+    } while (1); \
+                                                                                            \
+    MSLEEP(1); \
+                                                                                            \
+    REG32_W(ADR_WIFI_PHY_COMMON_SYS_REG, 0x80010000); \
+                                                                                            \
+    REG32_W(ADR_CLOCK_SELECTION, 0x00000008); \
+    MSLEEP(1); \
+} while(0)
+#define LOAD_TURISMOC_RF_TABLE(_patch) \
+do{ \
+    u32 i = 0; \
+                                                                                            \
+    for( i = 0; i < sizeof(ssv6006_turismoC_rf_setting)/sizeof(ssv_cabrio_reg); i++) { \
+       REG32_W(ssv6006_turismoC_rf_setting[i].address, \
+           ssv6006_turismoC_rf_setting[i].data ); \
+       UDELAY(50); \
+    } \
+    if (_patch.dcdc){ \
+                                                                                            \
+        SET_RG_DCDC_MODE(0x0); \
+        SET_RG_BUCK_EN_PSM(0x1); \
+        SET_RG_DCDC_MODE(0x1); \
+        UDELAY(100); \
+        SET_RG_BUCK_EN_PSM(0x0); \
+   } \
+} while(0)
+#define LOAD_TURISMOC_PHY_TABLE \
+do{ \
+    u32 i = 0; \
+                                                                                            \
+    for( i = 0; i < sizeof(ssv6006_turismoC_phy_setting)/sizeof(ssv_cabrio_reg); i++) { \
+       REG32_W(ssv6006_turismoC_phy_setting[i].address, \
+           ssv6006_turismoC_phy_setting[i].data ); \
+    } \
+} while(0)
+#define DEBUG_2P4G_RXDC_CAL \
+do { \
+    int rg_rfg, rg_pgag, i, j; \
+    int adc_out_sum_i, adc_out_sumQ; \
+                                                                                            \
+    SET_RG_RX_GAIN_MANUAL(1); \
+                                                                                            \
+    for(i = 1;i >= 0; i--){ \
+        for(j = 15;j >= 0; j--){ \
+            rg_rfg = i; \
+            rg_pgag = j; \
+            SET_RG_RFG(rg_rfg); \
+            SET_RG_PGAG(rg_pgag); \
+            adc_out_sum_i = GET_RO_DC_CAL_I; \
+            if (adc_out_sum_i>63) { \
+                adc_out_sum_i -= 128; \
+            } \
+            adc_out_sumQ = GET_RO_DC_CAL_Q; \
+            if(adc_out_sumQ>63){ \
+                adc_out_sumQ -= 128; \
+            } \
+            dev_dbg(sh->sc->dev, "lna gain is %d, pga gain is %d, ADC_OUT_I is %d, ADC_OUT_Q is %d", \
+               rg_rfg, rg_pgag, adc_out_sum_i, adc_out_sumQ); \
+        } \
+        dev_dbg(sh->sc->dev, "------------------------------------------------------------"); \
+    } \
+                                                                                            \
+    SET_RG_RX_GAIN_MANUAL(0); \
+} while(0)
+#define TURISMOC_2P4G_RXDC_CAL(_cal) \
+do { \
+    int i = 0; \
+    u32 wifi_dc_addr; \
+                                                                                            \
+    SET_REG(ADR_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE, \
+        (0x6 << RG_SX_CHANNEL_SFT) | (0x1 << RG_SX_RFCH_MAP_EN_SFT), 0, \
+        (RG_SX_CHANNEL_I_MSK & RG_SX_RFCH_MAP_EN_I_MSK)); \
+                                                                                            \
+    SET_RG_CAL_INDEX(CAL_IDX_WIFI2P4G_RXDC); \
+    UDELAY(100); \
+    while (GET_RO_WF_DCCAL_DONE == 0){ \
+        i ++; \
+        if (i >10000) { \
+            dev_err(sh->sc->dev, "%s: 2.4 RXDC cal failed",__func__); \
+            break; \
+        } \
+        UDELAY(1); \
+    } \
+    dev_dbg(sh->sc->dev, "------------------------------------------------%d",i); \
+    dev_dbg(sh->sc->dev, "--------- 2.4 G Rx DC Calibration result----------------"); \
+    for (i = 0; i < 21; i++) { \
+       wifi_dc_addr = (ADR_WF_DCOC_IDAC_REGISTER1)+ (i << 2); \
+       _cal->rxdc_2g[i] = REG32_R(wifi_dc_addr); \
+       dev_dbg(sh->sc->dev, "addr %x : val %x, ", wifi_dc_addr, _cal->rxdc_2g[i]); \
+    } \
+                                                                                            \
+                                                                                            \
+                                                                                            \
+    SET_RG_CAL_INDEX(CAL_IDX_NONE); \
+                                                                                            \
+                                                                                            \
+                                                                                            \
+} while (0)
+#define DEBUG_5G_RXDC_CAL \
+do { \
+    int rg_rfg, rg_pgag, i, j; \
+    int adc_out_sum_i, adc_out_sumQ; \
+                                                                                            \
+    SET_RG_RX_GAIN_MANUAL(1); \
+                                                                                            \
+    for(i = 1;i >= 0; i--){ \
+        for(j = 15;j >= 0; j--){ \
+            rg_rfg = i; \
+            rg_pgag = j; \
+            SET_RG_RFG(rg_rfg); \
+            SET_RG_PGAG(rg_pgag); \
+            adc_out_sum_i = GET_RO_DC_CAL_I; \
+            if (adc_out_sum_i>63) { \
+                adc_out_sum_i -= 128; \
+            } \
+            adc_out_sumQ = GET_RO_DC_CAL_Q; \
+            if(adc_out_sumQ>63){ \
+                adc_out_sumQ -= 128; \
+            } \
+            dev_dbg(sh->sc->dev, "lna gain is %d, pga gain is %d, ADC_OUT_I is %d, ADC_OUT_Q is %d", \
+               rg_rfg, rg_pgag, adc_out_sum_i, adc_out_sumQ); \
+        } \
+        dev_dbg(sh->sc->dev, "------------------------------------------------------------"); \
+    } \
+                                                                                            \
+    SET_RG_RX_GAIN_MANUAL(0); \
+} while(0)
+#define TURISMOC_5G_RXDC_CAL(_cal) \
+do { \
+    int i = 0; \
+    u32 wifi_dc_addr; \
+                                                                                            \
+    SET_REG(ADR_SX_5GB_REGISTER_INT3BIT___CH_TABLE, \
+        (100 << RG_SX5GB_CHANNEL_SFT) | (0x1 << RG_SX5GB_RFCH_MAP_EN_SFT), 0, \
+        (RG_SX5GB_CHANNEL_I_MSK & RG_SX5GB_RFCH_MAP_EN_I_MSK)); \
+                                                                                            \
+                                                                                            \
+    SET_RG_CAL_INDEX(CAL_IDX_WIFI5G_RXDC); \
+    UDELAY(100); \
+    while (GET_RO_5G_DCCAL_DONE == 0){ \
+        i ++; \
+        if (i >10000) { \
+            dev_err(sh->sc->dev, "%s: 5G RXDC cal failed",__func__); \
+            break; \
+        } \
+        UDELAY(1); \
+    } \
+                                                                                            \
+    dev_dbg(sh->sc->dev, "------------------------------------------------%d",i); \
+    dev_dbg(sh->sc->dev, "--------- 5 G Rx DC Calibration result----------------"); \
+    for (i = 0; i < 21; i++) { \
+       wifi_dc_addr = (ADR_5G_DCOC_IDAC_REGISTER1)+ (i << 2); \
+       _cal->rxdc_5g[i] = REG32_R(wifi_dc_addr); \
+       dev_dbg(sh->sc->dev, "addr %x : val %x, ", wifi_dc_addr, _cal->rxdc_5g[i]); \
+    } \
+                                                                                            \
+                                                                                            \
+    SET_RG_CAL_INDEX(CAL_IDX_NONE); \
+                                                                                            \
+} while (0)
+#define TURISMOC_BW20_RXRC_CAL(_cal) \
+do { \
+    int count = 0; \
+                                                                                            \
+    dev_dbg(sh->sc->dev, "--------------------------------------------"); \
+    dev_dbg(sh->sc->dev, "Before WiFi BW20 RG_WF_RX_ABBCTUNE: %d", GET_RG_WF_RX_ABBCTUNE); \
+                                                                                            \
+    SET_RG_RX_RCCAL_DELAY(2); \
+                                                                                            \
+    SET_RG_PHASE_17P5M(0x20d0); \
+                                                                                            \
+    SET_REG(ADR_RF_D_CAL_TOP_6, \
+        (0x22c << RG_RX_RCCAL_TARG_SFT) | (0 << RG_RCCAL_POLAR_INV_SFT), 0, \
+        (RG_RX_RCCAL_TARG_I_MSK & RG_RCCAL_POLAR_INV_I_MSK)); \
+                                                                                            \
+    SET_RG_ALPHA_SEL(2); \
+                                                                                            \
+    SET_RG_PGAG_RCCAL(3); \
+                                                                                            \
+    SET_RG_TONE_SCALE(0x80); \
+                                                                                            \
+    SET_RG_CAL_INDEX(CAL_IDX_BW20_RXRC); \
+                                                                                            \
+    UDELAY(250); \
+                                                                                            \
+    while (GET_RO_RCCAL_DONE == 0){ \
+        count ++; \
+        if (count >100000) { \
+            dev_err(sh->sc->dev, "%s: bw20 RXRC cal failed",__func__); \
+            break; \
+        } \
+        UDELAY(1); \
+    } \
+                                                                                            \
+    dev_dbg(sh->sc->dev, "--------------------------------------------%d", count); \
+    _cal->rxrc_bw20 = GET_RG_WF_RX_ABBCTUNE; \
+    dev_dbg(sh->sc->dev, "WiFi BW20 RG_WF_RX_ABBCTUNE CAL RESULT: %d", _cal->rxrc_bw20); \
+                                                                                            \
+                                                                                            \
+    SET_RG_CAL_INDEX(CAL_IDX_NONE); \
+                                                                                            \
+} while (0)
+#define TURISMOC_BW40_RXRC_CAL(_cal) \
+do { \
+    int count = 0; \
+                                                                                            \
+    dev_dbg(sh->sc->dev, "--------------------------------------------"); \
+    dev_dbg(sh->sc->dev, "Before WiFi BW40 RG_WF_RX_N_ABBCTUNE: %d", GET_RG_WF_N_RX_ABBCTUNE); \
+                                                                                            \
+    SET_RG_RX_N_RCCAL_DELAY(2); \
+                                                                                            \
+    SET_RG_PHASE_35M(0x3fff); \
+                                                                                            \
+    SET_REG(ADR_RF_D_CAL_TOP_6, \
+        (0x213 << RG_RX_RCCAL_40M_TARG_SFT) | (0 << RG_RCCAL_POLAR_INV_SFT), 0, \
+        (RG_RX_RCCAL_40M_TARG_I_MSK & RG_RCCAL_POLAR_INV_I_MSK)); \
+                                                                                            \
+    SET_RG_ALPHA_SEL(2); \
+                                                                                            \
+    SET_RG_PGAG_RCCAL(3); \
+                                                                                            \
+    SET_RG_TONE_SCALE(0x80); \
+                                                                                            \
+                                                                                            \
+    SET_RG_CAL_INDEX(CAL_IDX_BW40_RXRC); \
+    UDELAY(250); \
+                                                                                            \
+    while (GET_RO_RCCAL_DONE == 0){ \
+        count ++; \
+        if (count >100000) { \
+            dev_err(sh->sc->dev, "%s: bw40 RXRC cal failed",__func__); \
+            break; \
+        } \
+        UDELAY(1); \
+    } \
+    dev_dbg(sh->sc->dev, "--------------------------------------------%d", count); \
+    _cal->rxrc_bw40 = GET_RG_WF_N_RX_ABBCTUNE; \
+    dev_dbg(sh->sc->dev, "WiFi BW40 RG_WF_N_RX_ABBCTUNE CAL RESULT: %d", _cal->rxrc_bw40); \
+                                                                                            \
+                                                                                            \
+    SET_RG_CAL_INDEX(CAL_IDX_NONE); \
+                                                                                            \
+} while (0)
+#define TURISMOC_TXDC_CAL(_cal) \
+do { \
+    int count = 0; \
+                                                                                        \
+    SET_REG(ADR_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE, \
+        (0x6 << RG_SX_CHANNEL_SFT) | (0x1 << RG_SX_RFCH_MAP_EN_SFT), 0, \
+        (RG_SX_CHANNEL_I_MSK & RG_SX_RFCH_MAP_EN_I_MSK)); \
+                                                                                        \
+    dev_dbg(sh->sc->dev, "--------------------------------------------"); \
+    dev_dbg(sh->sc->dev, "Before txdc calibration WiFi 2P4G Tx DAC IOFFSET: %d, QOFFSET %d", \
+         GET_RG_WF_TX_DAC_IOFFSET, GET_RG_WF_TX_DAC_QOFFSET); \
+                                                                                        \
+    SET_RG_TXGAIN_PHYCTRL(1); \
+                                                                                        \
+    SET_REG(ADR_CALIBRATION_GAIN_REGISTER0, \
+        (0x6 << RG_TX_GAIN_TXCAL_SFT) | (0x3 << RG_PGAG_TXCAL_SFT), 0, \
+        (RG_TX_GAIN_TXCAL_I_MSK & RG_PGAG_TXCAL_I_MSK)); \
+                                                                                        \
+    SET_RG_TONE_SCALE(0x80); \
+                                                                                        \
+    SET_RG_PRE_DC_AUTO(1); \
+                                                                                        \
+    SET_RG_TX_IQCAL_TIME(1); \
+                                                                                        \
+    SET_RG_PHASE_1M(0x0ccc); \
+                                                                                        \
+    SET_RG_PHASE_RXIQ_1M(0x0ccc); \
+                                                                                        \
+    SET_RG_ALPHA_SEL(2); \
+                                                                                        \
+                                                                                        \
+    SET_RG_CAL_INDEX(CAL_IDX_WIFI2P4G_TXLO); \
+    UDELAY(250); \
+    while (GET_RO_TXDC_DONE == 0){ \
+        count ++; \
+        if (count >100000) { \
+            dev_err(sh->sc->dev, "%s: 2.4G TXDC cal failed",__func__); \
+            break; \
+        } \
+        UDELAY(1); \
+    } \
+                                                                                        \
+    dev_dbg(sh->sc->dev, "--------------------------------------------%d", count); \
+    _cal->txdc_i_2g = GET_RG_WF_TX_DAC_IOFFSET; \
+    _cal->txdc_q_2g = GET_RG_WF_TX_DAC_QOFFSET; \
+    dev_dbg(sh->sc->dev, "After txdc calibration WiFi 2P4G Tx DAC IOFFSET: %d, QOFFSET %d", \
+         _cal->txdc_i_2g, _cal->txdc_q_2g); \
+                                                                                        \
+                                                                                        \
+    SET_RG_CAL_INDEX(CAL_IDX_NONE); \
+                                                                                        \
+} while(0)
+#define TURISMOC_TXIQ_CAL(_cal) \
+do { \
+    int count = 0; \
+                                                                                        \
+    SET_REG(ADR_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE, \
+        (0x6 << RG_SX_CHANNEL_SFT) | (0x1 << RG_SX_RFCH_MAP_EN_SFT), 0, \
+        (RG_SX_CHANNEL_I_MSK & RG_SX_RFCH_MAP_EN_I_MSK)); \
+                                                                                        \
+                                                                                        \
+    dev_dbg(sh->sc->dev, "--------------------------------------------"); \
+    dev_dbg(sh->sc->dev, "before tx iq 2.4G calibration, tx alpha: %d, tx theta %d", \
+         GET_RG_TX_IQ_2500_ALPHA, GET_RG_TX_IQ_2500_THETA); \
+                                                                                        \
+    SET_RG_TXGAIN_PHYCTRL(1); \
+                                                                                        \
+    SET_REG(ADR_CALIBRATION_GAIN_REGISTER0, \
+        (0x6 << RG_TX_GAIN_TXCAL_SFT) | (0x3 << RG_PGAG_TXCAL_SFT), 0, \
+        (RG_TX_GAIN_TXCAL_I_MSK & RG_PGAG_TXCAL_I_MSK)); \
+                                                                                        \
+    SET_RG_TONE_SCALE(0x80); \
+                                                                                        \
+    SET_RG_PRE_DC_AUTO(1); \
+                                                                                        \
+    SET_RG_TX_IQCAL_TIME(1); \
+                                                                                        \
+    SET_RG_PHASE_1M(0xccc); \
+    SET_RG_PHASE_RXIQ_1M(0xccc); \
+                                                                                        \
+    SET_RG_ALPHA_SEL(2); \
+                                                                                        \
+                                                                                        \
+    SET_RG_CAL_INDEX(CAL_IDX_WIFI2P4G_TXIQ); \
+    UDELAY(250); \
+    while (GET_RO_TXIQ_DONE == 0){ \
+        count ++; \
+        if (count >1000) { \
+            dev_err(sh->sc->dev, "%s: 2.4G txiq cal failed",__func__); \
+            break; \
+        } \
+        UDELAY(100); \
+    } \
+    dev_dbg(sh->sc->dev, "--------------------------------------------%d", count); \
+    _cal->txiq_alpha[BAND_2G] = GET_RG_TX_IQ_2500_ALPHA; \
+    _cal->txiq_theta[BAND_2G] = GET_RG_TX_IQ_2500_THETA; \
+    dev_dbg(sh->sc->dev, "After tx iq calibration, tx alpha: %d, tx theta %d", \
+         _cal->txiq_alpha[BAND_2G], _cal->txiq_theta[BAND_2G]); \
+                                                                                        \
+                                                                                        \
+    SET_RG_CAL_INDEX(CAL_IDX_NONE); \
+} while (0)
+#define DEBUG_RX_IQ_CAL \
+do { \
+    u32 regval, regval1; \
+    SET_RG_PHASE_STEP_VALUE(0xccc); \
+    SET_RG_SPECTRUM_EN(1); \
+                                                                                        \
+    SET_REG(ADR_RF_D_CAL_TOP_7, \
+        (0x1 << RG_SPECTRUM_PWR_UPDATE_SFT) | (0x1 << RG_SPECTRUM_LO_FIX_SFT), 0, \
+        (RG_SPECTRUM_PWR_UPDATE_I_MSK & RG_SPECTRUM_LO_FIX_I_MSK)); \
+                                                                                        \
+    MDELAY(10); \
+                                                                                        \
+    SET_REG(ADR_RF_D_CAL_TOP_7, \
+        (0x0 << RG_SPECTRUM_PWR_UPDATE_SFT) | (0x1 << RG_SPECTRUM_LO_FIX_SFT), 0, \
+        (RG_SPECTRUM_PWR_UPDATE_I_MSK & RG_SPECTRUM_LO_FIX_I_MSK)); \
+                                                                                        \
+    regval1 = GET_RG_SPECTRUM_PWR_UPDATE; \
+    regval = GET_RO_SPECTRUM_IQ_PWR_31_0; \
+    dev_dbg(sh->sc->dev, "The spectrum power is 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x", \
+        ((regval1 >> 4) & 0xf), (regval1 & 0xf), ((regval >> 28) & 0xf), ((regval >> 24) & 0xf), \
+        ((regval >> 20) & 0xf), ((regval >> 16) & 0xf), ((regval >> 12) & 0xf), ((regval >> 8) & 0xf), \
+        ((regval >> 4) & 0xf), (regval & 0xf)); \
+                                                                                                        \
+    SET_RG_PHASE_STEP_VALUE(0xF334); \
+    SET_RG_SPECTRUM_EN(1); \
+                                                                                                        \
+    SET_REG(ADR_RF_D_CAL_TOP_7, \
+        (0x1 << RG_SPECTRUM_PWR_UPDATE_SFT) | (0x1 << RG_SPECTRUM_LO_FIX_SFT), 0, \
+        (RG_SPECTRUM_PWR_UPDATE_I_MSK & RG_SPECTRUM_LO_FIX_I_MSK)); \
+                                                                                                        \
+    MDELAY(10); \
+                                                                                                        \
+    SET_REG(ADR_RF_D_CAL_TOP_7, \
+        (0x0 << RG_SPECTRUM_PWR_UPDATE_SFT) | (0x1 << RG_SPECTRUM_LO_FIX_SFT), 0, \
+        (RG_SPECTRUM_PWR_UPDATE_I_MSK & RG_SPECTRUM_LO_FIX_I_MSK)); \
+                                                                                                        \
+    regval1 = GET_RG_SPECTRUM_PWR_UPDATE; \
+    regval = GET_RO_SPECTRUM_IQ_PWR_31_0; \
+    dev_dbg(sh->sc->dev, "The spectrum power is 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x", \
+        ((regval1 >> 4) & 0xf), (regval1 & 0xf), ((regval >> 28) & 0xf), ((regval >> 24) & 0xf), \
+        ((regval >> 20) & 0xf), ((regval >> 16) & 0xf), ((regval >> 12) & 0xf), ((regval >> 8) & 0xf), \
+        ((regval >> 4) & 0xf), (regval & 0xf)); \
+                                                                                                        \
+    SET_RG_SPECTRUM_EN(0); \
+} while(0)
+#define TURISMOC_RXIQ_CAL(_cal) \
+do { \
+    int count = 0; \
+                                                                                        \
+    SET_REG(ADR_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE, \
+        (0x6 << RG_SX_CHANNEL_SFT) | (0x1 << RG_SX_RFCH_MAP_EN_SFT), 0, \
+        (RG_SX_CHANNEL_I_MSK & RG_SX_RFCH_MAP_EN_I_MSK)); \
+                                                                                        \
+                                                                                        \
+    dev_dbg(sh->sc->dev, "--------------------------------------------"); \
+    dev_dbg(sh->sc->dev, "Before rx iq calibration, rx alpha: %d, rx theta %d", \
+         GET_RG_RX_IQ_2500_ALPHA, GET_RG_RX_IQ_2500_THETA); \
+                                                                                        \
+    SET_RG_TXGAIN_PHYCTRL(1); \
+                                                                                        \
+    SET_RG_RFG_RXIQCAL(0x0); \
+                                                                                        \
+    SET_RG_PGAG_RXIQCAL(0x3); \
+                                                                                        \
+    SET_RG_TX_GAIN_RXIQCAL(0x6); \
+                                                                                        \
+    SET_RG_TONE_SCALE(0x80); \
+                                                                                        \
+    SET_RG_PRE_DC_AUTO(1); \
+                                                                                        \
+    SET_RG_TX_IQCAL_TIME(1); \
+                                                                                        \
+    SET_RG_PHASE_1M(0xccc); \
+    SET_RG_PHASE_RXIQ_1M(0xccc); \
+                                                                                        \
+    SET_RG_ALPHA_SEL(2); \
+                                                                                        \
+                                                                                        \
+    SET_RG_CAL_INDEX(CAL_IDX_WIFI2P4G_RXIQ); \
+    UDELAY(250); \
+    while (GET_RO_RXIQ_DONE == 0){ \
+        count ++; \
+        if (count >100000) { \
+            dev_err(sh->sc->dev, "%s: 2.4G RXIQ cal failed",__func__); \
+            break; \
+        } \
+        UDELAY(1); \
+    } \
+                                                                                        \
+                                                                                        \
+    dev_dbg(sh->sc->dev, "--------------------------------------------%d", count); \
+    _cal->rxiq_alpha[BAND_2G] = GET_RG_RX_IQ_2500_ALPHA; \
+    _cal->rxiq_theta[BAND_2G] = GET_RG_RX_IQ_2500_THETA; \
+    dev_dbg(sh->sc->dev, "After rx iq calibration, rx alpha: %d, rx theta %d", \
+         _cal->rxiq_alpha[BAND_2G], _cal->rxiq_theta[BAND_2G]); \
+                                                                                        \
+                                                                                        \
+    SET_RG_CAL_INDEX(CAL_IDX_NONE); \
+} while(0)
+#define TURISMOC_5G_TXDC_CAL(_cal) \
+do{ \
+    int count = 0; \
+                                                                                            \
+    SET_REG(ADR_SX_5GB_REGISTER_INT3BIT___CH_TABLE, \
+        (100 << RG_SX5GB_CHANNEL_SFT) | (0x1 << RG_SX5GB_RFCH_MAP_EN_SFT), 0, \
+        (RG_SX5GB_CHANNEL_I_MSK & RG_SX5GB_RFCH_MAP_EN_I_MSK)); \
+                                                                                            \
+    dev_dbg(sh->sc->dev, "--------------------------------------------"); \
+    dev_dbg(sh->sc->dev, "Before 5G txdc calibration WiFi 5G Tx DAC IOFFSET: %d, QOFFSET %d", \
+         GET_RG_5G_TX_DAC_IOFFSET, GET_RG_5G_TX_DAC_QOFFSET); \
+                                                                                            \
+    SET_RG_TXGAIN_PHYCTRL(1); \
+                                                                                            \
+    SET_RG_TONE_SCALE(0x80); \
+                                                                                            \
+    SET_REG(ADR_5G_CALIBRATION_TIMER_GAIN_REGISTER, \
+        (0x2 << RG_5G_TX_GAIN_TXCAL_SFT) | (0x3 << RG_5G_PGAG_TXCAL_SFT), 0, \
+        (RG_5G_TX_GAIN_TXCAL_I_MSK & RG_5G_PGAG_TXCAL_I_MSK)); \
+                                                                                            \
+    SET_RG_PRE_DC_AUTO(1); \
+                                                                                            \
+    SET_RG_TX_IQCAL_TIME(1); \
+                                                                                            \
+    SET_RG_PHASE_1M(0xCCC); \
+    SET_RG_PHASE_RXIQ_1M(0xCCC); \
+                                                                                            \
+    SET_RG_ALPHA_SEL(2); \
+                                                                                            \
+                                                                                            \
+    SET_RG_CAL_INDEX(CAL_IDX_WIFI5G_TXLO); \
+    UDELAY(250); \
+    while (GET_RO_5G_TXDC_DONE == 0){ \
+        count ++; \
+        if (count >100000) { \
+            dev_err(sh->sc->dev, "%s: 5G TXDC cal failed",__func__); \
+            break; \
+        } \
+        UDELAY(1); \
+    } \
+    dev_dbg(sh->sc->dev, "--------------------------------------------%d", count); \
+    _cal->txdc_i_5g = GET_RG_5G_TX_DAC_IOFFSET; \
+    _cal->txdc_q_5g = GET_RG_5G_TX_DAC_QOFFSET; \
+    dev_dbg(sh->sc->dev, "After 5G txdc calibration WiFi 5G Tx DAC IOFFSET: %d, QOFFSET %d", \
+         _cal->txdc_i_5g, _cal->txdc_q_5g); \
+                                                                                            \
+                                                                                            \
+    SET_RG_CAL_INDEX(CAL_IDX_NONE); \
+} while(0)
+#define TURISMOC_5G_TXIQ_CAL(_cal) \
+{ \
+    int count = 0; \
+    int band; \
+                                                                                            \
+                                                                                            \
+    SET_RG_SX5GB_RFCH_MAP_EN(1); \
+                                                                                            \
+    dev_dbg(sh->sc->dev, "--------------------------------------------"); \
+    dev_dbg(sh->sc->dev, "before 5G tx iq calibration, tx alpha: %d %d %d %d, tx theta %d %d %d %d", \
+         GET_RG_TX_IQ_5100_ALPHA, GET_RG_TX_IQ_5100_THETA, \
+         GET_RG_TX_IQ_5500_ALPHA, GET_RG_TX_IQ_5500_THETA, \
+         GET_RG_TX_IQ_5700_ALPHA, GET_RG_TX_IQ_5700_THETA, \
+         GET_RG_TX_IQ_5900_ALPHA, GET_RG_TX_IQ_5900_THETA); \
+                                                                                            \
+    SET_RG_TXGAIN_PHYCTRL(1); \
+                                                                                            \
+    SET_RG_TONE_SCALE(0x80); \
+                                                                                            \
+    SET_RG_5G_PGAG_TXCAL(0x3); \
+                                                                                            \
+    SET_RG_PRE_DC_AUTO(1); \
+                                                                                            \
+    SET_RG_TX_IQCAL_TIME(1); \
+                                                                                            \
+    SET_RG_PHASE_1M(0xccc); \
+    SET_RG_PHASE_RXIQ_1M(0xccc); \
+                                                                                            \
+    SET_RG_ALPHA_SEL(2); \
+                                                                                            \
+    for (band = 0; band < 4; band ++){ \
+        count=0; \
+        SET_RG_SX5GB_CHANNEL(cal_ch_5g[band]); \
+                                                                                            \
+        if( band == 2 ) { \
+            SET_RG_5G_TX_GAIN_TXCAL(0x2); \
+        } else { \
+            SET_RG_5G_TX_GAIN_TXCAL(0x0); \
+        } \
+        UDELAY(1); \
+                                                                                            \
+                                                                                            \
+        SET_RG_CAL_INDEX(CAL_IDX_WIFI5G_TXIQ); \
+        UDELAY(250); \
+        while (GET_RO_5G_TXIQ_DONE == 0){ \
+            count ++; \
+            if (count >100000) { \
+                dev_err(sh->sc->dev, "%s: 5G band %d TXIQ cal failed",__func__, band); \
+                break; \
+            } \
+            UDELAY(1); \
+        } \
+                                                                                            \
+        SET_RG_CAL_INDEX(CAL_IDX_NONE); \
+    } \
+                                                                                            \
+    dev_dbg(sh->sc->dev, "--------------------------------------------%d", count); \
+    _cal->txiq_alpha[BAND_5100] = GET_RG_TX_IQ_5100_ALPHA; \
+    _cal->txiq_theta[BAND_5100] = GET_RG_TX_IQ_5100_THETA; \
+    _cal->txiq_alpha[BAND_5500] = GET_RG_TX_IQ_5500_ALPHA; \
+    _cal->txiq_theta[BAND_5500] = GET_RG_TX_IQ_5500_THETA; \
+    _cal->txiq_alpha[BAND_5700] = GET_RG_TX_IQ_5700_ALPHA; \
+    _cal->txiq_theta[BAND_5700] = GET_RG_TX_IQ_5700_THETA; \
+    _cal->txiq_alpha[BAND_5900] = GET_RG_TX_IQ_5900_ALPHA; \
+    _cal->txiq_theta[BAND_5900] = GET_RG_TX_IQ_5900_THETA; \
+    dev_dbg(sh->sc->dev, "after 5G tx iq calibration, tx alpha: %d %d %d %d, tx theta %d %d %d %d", \
+        _cal->txiq_alpha[BAND_5100], _cal->txiq_alpha[BAND_5500], \
+        _cal->txiq_alpha[BAND_5700], _cal->txiq_alpha[BAND_5900], \
+        _cal->txiq_theta[BAND_5100], _cal->txiq_theta[BAND_5500], \
+        _cal->txiq_theta[BAND_5700], _cal->txiq_theta[BAND_5900]); \
+} while(0)
+#define TURISMOC_5G_TXIQ_CAL_BAND(_cal,_pa_band) \
+{ \
+    int count = 0, alpha = 0, theta = 0; \
+                                                                                            \
+    SET_RG_SX5GB_RFCH_MAP_EN(1); \
+                                                                                            \
+    SET_RG_SX5GB_CHANNEL(cal_ch_5g[pa_band-1]); \
+    if( pa_band == BAND_5700 ) { \
+        SET_RG_5G_TX_GAIN_TXCAL(0x2); \
+    } else { \
+        SET_RG_5G_TX_GAIN_TXCAL(0x0); \
+    } \
+                                                                                            \
+    switch (_pa_band){ \
+        case BAND_5100: \
+            alpha = GET_RG_TX_IQ_5100_ALPHA; \
+            theta = GET_RG_TX_IQ_5100_THETA; \
+            break; \
+        case BAND_5500: \
+            alpha = GET_RG_TX_IQ_5500_ALPHA; \
+            theta = GET_RG_TX_IQ_5500_THETA; \
+            break; \
+        case BAND_5700: \
+            alpha = GET_RG_TX_IQ_5700_ALPHA; \
+            theta = GET_RG_TX_IQ_5700_THETA; \
+            break; \
+        case BAND_5900: \
+            alpha = GET_RG_TX_IQ_5900_ALPHA; \
+            theta = GET_RG_TX_IQ_5900_THETA; \
+            break; \
+        default: \
+            break; \
+    } \
+    dev_dbg(sh->sc->dev, "--------------------------------------------"); \
+    dev_dbg(sh->sc->dev, "before 5G band %d tx iq calibration, tx alpha: %d, tx theta %d", \
+         _pa_band, alpha, theta); \
+                                                                                            \
+    SET_RG_TXGAIN_PHYCTRL(1); \
+                                                                                            \
+    SET_RG_TONE_SCALE(0x80); \
+                                                                                            \
+    SET_RG_5G_PGAG_TXCAL(0x3); \
+                                                                                            \
+    SET_RG_PRE_DC_AUTO(1); \
+                                                                                            \
+    SET_RG_TX_IQCAL_TIME(1); \
+                                                                                            \
+    SET_RG_PHASE_1M(0xccc); \
+    SET_RG_PHASE_RXIQ_1M(0xccc); \
+                                                                                            \
+    SET_RG_ALPHA_SEL(2); \
+                                                                                            \
+                                                                                            \
+    SET_RG_CAL_INDEX(CAL_IDX_WIFI5G_TXIQ); \
+    UDELAY(250); \
+    while (GET_RO_5G_TXIQ_DONE == 0){ \
+        count ++; \
+        if (count >100000){ \
+            dev_err(sh->sc->dev, "%s: 5G band %d TXIQ cal failed",__func__, _pa_band); \
+            break; \
+        } \
+        UDELAY(1); \
+    } \
+                                                                                            \
+    SET_RG_CAL_INDEX(CAL_IDX_NONE); \
+    switch (_pa_band){ \
+        case BAND_5100: \
+            _cal->txiq_alpha[_pa_band] = GET_RG_TX_IQ_5100_ALPHA; \
+            _cal->txiq_theta[_pa_band] = GET_RG_TX_IQ_5100_THETA; \
+            break; \
+        case BAND_5500: \
+            _cal->txiq_alpha[_pa_band] = GET_RG_TX_IQ_5500_ALPHA; \
+            _cal->txiq_theta[_pa_band] = GET_RG_TX_IQ_5500_THETA; \
+            break; \
+        case BAND_5700: \
+            _cal->txiq_alpha[_pa_band] = GET_RG_TX_IQ_5700_ALPHA; \
+            _cal->txiq_theta[_pa_band] = GET_RG_TX_IQ_5700_THETA; \
+            break; \
+        case BAND_5900: \
+            _cal->txiq_alpha[_pa_band] = GET_RG_TX_IQ_5900_ALPHA; \
+            _cal->txiq_theta[_pa_band] = GET_RG_TX_IQ_5900_THETA; \
+            break; \
+        default: \
+            break; \
+    } \
+    dev_dbg(sh->sc->dev, "--------------------------------------------%d", count); \
+    dev_dbg(sh->sc->dev, "after 5G band %d tx iq calibration, tx alpha: %d, tx theta %d", \
+        _pa_band, _cal->txiq_alpha[_pa_band], _cal->txiq_theta[_pa_band]); \
+} while(0)
+#define DEBUG_5G_RXIQ_CAL \
+do{ \
+    int regval, regval1; \
+                                                                                            \
+        SET_RG_PHASE_STEP_VALUE(0xccc); \
+        SET_RG_SPECTRUM_EN(1); \
+                                                                                            \
+        SET_REG(ADR_RF_D_CAL_TOP_7, \
+            (0x1 << RG_SPECTRUM_PWR_UPDATE_SFT) | (0x1 << RG_SPECTRUM_LO_FIX_SFT), 0, \
+            (RG_SPECTRUM_PWR_UPDATE_I_MSK & RG_SPECTRUM_LO_FIX_I_MSK)); \
+                                                                                            \
+        MDELAY(10); \
+                                                                                            \
+        SET_REG(ADR_RF_D_CAL_TOP_7, \
+            (0x0 << RG_SPECTRUM_PWR_UPDATE_SFT) | (0x1 << RG_SPECTRUM_LO_FIX_SFT), 0, \
+            (RG_SPECTRUM_PWR_UPDATE_I_MSK & RG_SPECTRUM_LO_FIX_I_MSK)); \
+                                                                                            \
+        regval1 = GET_RG_SPECTRUM_PWR_UPDATE; \
+        regval = GET_RO_SPECTRUM_IQ_PWR_31_0; \
+        dev_dbg(sh->sc->dev, "The spectrum power is 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x", \
+            ((regval1 >> 4) & 0xf), (regval1 & 0xf), ((regval >> 28) & 0xf), ((regval >> 24) & 0xf), \
+            ((regval >> 20) & 0xf), ((regval >> 16) & 0xf), ((regval >> 12) & 0xf), ((regval >> 8) & 0xf), \
+            ((regval >> 4) & 0xf), (regval & 0xf)); \
+                                                                                                            \
+        SET_RG_PHASE_STEP_VALUE(0xF334); \
+        SET_RG_SPECTRUM_EN(1); \
+                                                                                                            \
+        SET_REG(ADR_RF_D_CAL_TOP_7, \
+            (0x1 << RG_SPECTRUM_PWR_UPDATE_SFT) | (0x1 << RG_SPECTRUM_LO_FIX_SFT), 0, \
+            (RG_SPECTRUM_PWR_UPDATE_I_MSK & RG_SPECTRUM_LO_FIX_I_MSK)); \
+                                                                                                            \
+        MDELAY(10); \
+                                                                                                            \
+        SET_REG(ADR_RF_D_CAL_TOP_7, \
+            (0x0 << RG_SPECTRUM_PWR_UPDATE_SFT) | (0x1 << RG_SPECTRUM_LO_FIX_SFT), 0, \
+            (RG_SPECTRUM_PWR_UPDATE_I_MSK & RG_SPECTRUM_LO_FIX_I_MSK)); \
+                                                                                                            \
+        regval1 = GET_RG_SPECTRUM_PWR_UPDATE; \
+        regval = GET_RO_SPECTRUM_IQ_PWR_31_0; \
+        dev_dbg(sh->sc->dev, "The spectrum power is 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x", \
+            ((regval1 >> 4) & 0xf), (regval1 & 0xf), ((regval >> 28) & 0xf), ((regval >> 24) & 0xf), \
+            ((regval >> 20) & 0xf), ((regval >> 16) & 0xf), ((regval >> 12) & 0xf), ((regval >> 8) & 0xf), \
+            ((regval >> 4) & 0xf), (regval & 0xf)); \
+                                                                                                            \
+        SET_RG_SPECTRUM_EN(0); \
+} while(0)
+#define TURISMOC_5G_RXIQ_CAL(_cal) \
+do{ \
+    int count = 0; \
+    int band; \
+                                                                                            \
+    SET_RG_SX5GB_RFCH_MAP_EN(1); \
+    dev_dbg(sh->sc->dev, "--------------------------------------------"); \
+    dev_dbg(sh->sc->dev, "before 5G rx iq calibration, rx alpha: %d %d %d %d, rx theta %d %d %d %d", \
+         GET_RG_RX_IQ_5100_ALPHA, GET_RG_RX_IQ_5100_THETA, \
+         GET_RG_RX_IQ_5500_ALPHA, GET_RG_RX_IQ_5500_THETA, \
+         GET_RG_RX_IQ_5700_ALPHA, GET_RG_RX_IQ_5700_THETA, \
+         GET_RG_RX_IQ_5900_ALPHA, GET_RG_RX_IQ_5900_THETA); \
+                                                                                            \
+    SET_RG_TXGAIN_PHYCTRL(1); \
+                                                                                            \
+    SET_RG_5G_RFG_RXIQCAL(0x0); \
+                                                                                            \
+    SET_RG_5G_PGAG_RXIQCAL(0x3); \
+                                                                                            \
+    SET_RG_TONE_SCALE(0x80); \
+                                                                                            \
+    SET_RG_PRE_DC_AUTO(1); \
+                                                                                            \
+    SET_RG_TX_IQCAL_TIME(1); \
+                                                                                            \
+    SET_RG_PHASE_1M(0xccc); \
+    SET_RG_PHASE_RXIQ_1M(0xccc); \
+                                                                                            \
+    SET_RG_ALPHA_SEL(2); \
+                                                                                            \
+    for (band = 0; band < 4; band ++){ \
+        count=0; \
+        SET_RG_SX5GB_CHANNEL(cal_ch_5g[band]); \
+                                                                                            \
+        if( band == 2 ) { \
+            SET_RG_5G_TX_GAIN_RXIQCAL(0x2); \
+        } else { \
+            SET_RG_5G_TX_GAIN_RXIQCAL(0x0); \
+        } \
+        UDELAY(1); \
+                                                                                            \
+                                                                                            \
+        SET_RG_CAL_INDEX(CAL_IDX_WIFI5G_RXIQ); \
+        UDELAY(250); \
+        while (GET_RO_5G_RXIQ_DONE == 0){ \
+            count ++; \
+            if (count >100000) { \
+                dev_err(sh->sc->dev, "%s: 5G band %d RXDC cal failed",__func__, band); \
+                break; \
+            } \
+            UDELAY(1); \
+        } \
+                                                                                            \
+                                                                                            \
+                                                                                            \
+        SET_RG_CAL_INDEX(CAL_IDX_NONE); \
+    } \
+    dev_dbg(sh->sc->dev, "--------------------------------------------%d", count); \
+    _cal->rxiq_alpha[BAND_5100] = GET_RG_RX_IQ_5100_ALPHA; \
+    _cal->rxiq_theta[BAND_5100] = GET_RG_RX_IQ_5100_THETA; \
+    _cal->rxiq_alpha[BAND_5500] = GET_RG_RX_IQ_5500_ALPHA; \
+    _cal->rxiq_theta[BAND_5500] = GET_RG_RX_IQ_5500_THETA; \
+    _cal->rxiq_alpha[BAND_5700] = GET_RG_RX_IQ_5700_ALPHA; \
+    _cal->rxiq_theta[BAND_5700] = GET_RG_RX_IQ_5700_THETA; \
+    _cal->rxiq_alpha[BAND_5900] = GET_RG_RX_IQ_5900_ALPHA; \
+    _cal->rxiq_theta[BAND_5900] = GET_RG_RX_IQ_5900_THETA; \
+    dev_dbg(sh->sc->dev, "After 5G rx iq calibration, rx alpha: %d %d %d %d, rx theta %d %d %d %d", \
+        _cal->rxiq_alpha[BAND_5100], _cal->rxiq_alpha[BAND_5500], \
+        _cal->rxiq_alpha[BAND_5700], _cal->rxiq_alpha[BAND_5900], \
+        _cal->rxiq_theta[BAND_5100], _cal->rxiq_theta[BAND_5500], \
+        _cal->rxiq_theta[BAND_5700], _cal->rxiq_theta[BAND_5900]); \
+} while (0)
+#define TURISMOC_5G_RXIQ_CAL_BAND(_cal,_pa_band) \
+do{ \
+    int count = 0, alpha = 0, theta = 0; \
+                                                                                            \
+    SET_RG_SX5GB_RFCH_MAP_EN(1); \
+                                                                                            \
+    SET_RG_SX5GB_CHANNEL(cal_ch_5g[_pa_band-1]); \
+    if( _pa_band == BAND_5700 ) { \
+        SET_RG_5G_TX_GAIN_RXIQCAL(0x2); \
+    } else { \
+        SET_RG_5G_TX_GAIN_RXIQCAL(0x0); \
+    } \
+                                                                                            \
+    switch (_pa_band){ \
+        case BAND_5100: \
+            alpha = GET_RG_RX_IQ_5100_ALPHA; \
+            theta = GET_RG_RX_IQ_5100_THETA; \
+            break; \
+        case BAND_5500: \
+            alpha = GET_RG_RX_IQ_5500_ALPHA; \
+            theta = GET_RG_RX_IQ_5500_THETA; \
+            break; \
+        case BAND_5700: \
+            alpha = GET_RG_RX_IQ_5700_ALPHA; \
+            theta = GET_RG_RX_IQ_5700_THETA; \
+            break; \
+        case BAND_5900: \
+            alpha = GET_RG_RX_IQ_5900_ALPHA; \
+            theta = GET_RG_RX_IQ_5900_THETA; \
+            break; \
+        default: \
+            break; \
+    } \
+    dev_dbg(sh->sc->dev, "--------------------------------------------"); \
+    dev_dbg(sh->sc->dev, "before 5G band%d rx iq calibration, rx alpha: %d, rx theta %d", \
+         _pa_band, alpha, theta); \
+                                                                                            \
+    SET_RG_TXGAIN_PHYCTRL(1); \
+                                                                                            \
+    SET_RG_5G_RFG_RXIQCAL(0x0); \
+                                                                                            \
+    SET_RG_5G_PGAG_RXIQCAL(0x3); \
+                                                                                            \
+    SET_RG_TONE_SCALE(0x80); \
+                                                                                            \
+    SET_RG_PRE_DC_AUTO(1); \
+                                                                                            \
+    SET_RG_TX_IQCAL_TIME(1); \
+                                                                                            \
+    SET_RG_PHASE_1M(0xccc); \
+    SET_RG_PHASE_RXIQ_1M(0xccc); \
+                                                                                            \
+    SET_RG_ALPHA_SEL(2); \
+                                                                                            \
+                                                                                            \
+    SET_RG_CAL_INDEX(CAL_IDX_WIFI5G_RXIQ); \
+    UDELAY(250); \
+    while (GET_RO_5G_RXIQ_DONE == 0){ \
+        count ++; \
+        if (count >100000) { \
+            dev_err(sh->sc->dev, "%s: 5G band %d RXIQ cal failed",__func__, _pa_band); \
+            break; \
+        } \
+        UDELAY(1); \
+    } \
+                                                                                            \
+                                                                                            \
+                                                                                            \
+    SET_RG_CAL_INDEX(CAL_IDX_NONE); \
+                                                                                            \
+    switch (_pa_band){ \
+        case BAND_5100: \
+            _cal->rxiq_alpha[_pa_band] = GET_RG_RX_IQ_5100_ALPHA; \
+            _cal->rxiq_theta[_pa_band] = GET_RG_RX_IQ_5100_THETA; \
+            break; \
+        case BAND_5500: \
+            _cal->rxiq_alpha[_pa_band] = GET_RG_RX_IQ_5500_ALPHA; \
+            _cal->rxiq_theta[_pa_band] = GET_RG_RX_IQ_5500_THETA; \
+            break; \
+        case BAND_5700: \
+            _cal->rxiq_alpha[_pa_band] = GET_RG_RX_IQ_5700_ALPHA; \
+            _cal->rxiq_theta[_pa_band] = GET_RG_RX_IQ_5700_THETA; \
+            break; \
+        case BAND_5900: \
+            _cal->rxiq_alpha[_pa_band] = GET_RG_RX_IQ_5900_ALPHA; \
+            _cal->rxiq_theta[_pa_band] = GET_RG_RX_IQ_5900_THETA; \
+            break; \
+        default: \
+            break; \
+    } \
+                                                                                            \
+                                                                                            \
+    dev_dbg(sh->sc->dev, "--------------------------------------------%d", count); \
+                                                                                            \
+    dev_dbg(sh->sc->dev, "After 5G band%d rx iq calibration, rx alpha: %d, rx theta %d", \
+        _pa_band, _cal->rxiq_alpha[pa_band], _cal->rxiq_theta[pa_band]); \
+} while (0)
+#define TU_INIT_TURISMOC_CALI(_cal) \
+do{ int i; \
+    SET_RG_DPD_AM_EN(0); \
+    SET_RG_TXGAIN_PHYCTRL(1); \
+                                                                                            \
+    REG32_W(ADR_WIFI_PADPD_5G_BB_GAIN_REG, 0x80808080); \
+                                                                                            \
+    TURISMOB_PRE_CAL; \
+                                                                                            \
+    TURISMOC_2P4G_RXDC_CAL(_cal); \
+    TURISMO_INTER_CAL; \
+    TURISMOC_BW20_RXRC_CAL(_cal); \
+    TURISMO_INTER_CAL; \
+    TURISMOC_BW40_RXRC_CAL(_cal); \
+    TURISMO_INTER_CAL; \
+    TURISMOC_TXDC_CAL(_cal); \
+    TURISMO_INTER_CAL; \
+    TURISMOC_TXIQ_CAL(_cal); \
+    TURISMO_INTER_CAL; \
+    TURISMOC_RXIQ_CAL(_cal); \
+    _cal->cal_iq_done[BAND_2G] = true; \
+    TURISMO_INTER_CAL; \
+    TURISMOC_5G_RXDC_CAL(_cal); \
+    TURISMO_INTER_CAL; \
+    TURISMOC_5G_TXDC_CAL(_cal); \
+    TURISMO_INTER_CAL; \
+    TURISMOC_5G_TXIQ_CAL(_cal); \
+    TURISMO_INTER_CAL; \
+    TURISMOC_5G_RXIQ_CAL(_cal); \
+    for (i = BAND_5100; i < MAX_BAND; i++) \
+         _cal->cal_iq_done[i] = true; \
+                                                                                            \
+    TURISMOB_POST_CAL; \
+    _cal->cal_done = true; \
+} while(0)
+#define TU_INIT_TURISMOC_2G_CALI(_cal) \
+do{ \
+    SET_RG_DPD_AM_EN(0); \
+    SET_RG_TXGAIN_PHYCTRL(1); \
+                                                                                            \
+    TURISMOB_PRE_CAL; \
+                                                                                            \
+    TURISMOC_2P4G_RXDC_CAL(_cal); \
+    TURISMO_INTER_CAL; \
+    TURISMOC_BW20_RXRC_CAL(_cal); \
+    TURISMO_INTER_CAL; \
+    TURISMOC_BW40_RXRC_CAL(_cal); \
+    TURISMO_INTER_CAL; \
+    TURISMOC_TXDC_CAL(_cal); \
+    TURISMO_INTER_CAL; \
+    TURISMOC_TXIQ_CAL(_cal); \
+    TURISMO_INTER_CAL; \
+    TURISMOC_RXIQ_CAL(_cal); \
+    _cal->cal_iq_done[BAND_2G] = true; \
+                                                                                            \
+    TURISMOB_POST_CAL; \
+    _cal->cal_done = true; \
+} while(0)
+#define TU_INIT_TURISMOC_FAST_CALI(_cal) \
+do{ \
+    SET_RG_DPD_AM_EN(0); \
+    SET_RG_TXGAIN_PHYCTRL(1); \
+                                                                                            \
+    REG32_W(ADR_WIFI_PADPD_5G_BB_GAIN_REG, 0x80808080); \
+                                                                                            \
+    TURISMOB_PRE_CAL; \
+                                                                                            \
+    TURISMOC_2P4G_RXDC_CAL(_cal); \
+    TURISMO_INTER_CAL; \
+    TURISMOC_BW20_RXRC_CAL(_cal); \
+    TURISMO_INTER_CAL; \
+    TURISMOC_BW40_RXRC_CAL(_cal); \
+    TURISMO_INTER_CAL; \
+    TURISMOC_TXDC_CAL(_cal); \
+    TURISMO_INTER_CAL; \
+    TURISMOC_5G_RXDC_CAL(_cal); \
+    TURISMO_INTER_CAL; \
+    TURISMOC_5G_TXDC_CAL(_cal); \
+                                                                                            \
+    TURISMOB_POST_CAL; \
+    _cal->cal_done = true; \
+} while(0)
+#define TU_INIT_TURISMOC_2G_FAST_CALI(_cal) \
+do{ \
+    SET_RG_DPD_AM_EN(0); \
+    SET_RG_TXGAIN_PHYCTRL(1); \
+                                                                                            \
+    TURISMOB_PRE_CAL; \
+                                                                                            \
+    TURISMOC_2P4G_RXDC_CAL(_cal); \
+    TURISMO_INTER_CAL; \
+    TURISMOC_BW20_RXRC_CAL(_cal); \
+    TURISMO_INTER_CAL; \
+    TURISMOC_BW40_RXRC_CAL(_cal); \
+    TURISMO_INTER_CAL; \
+    TURISMOC_TXDC_CAL(_cal); \
+                                                                                            \
+    TURISMOB_POST_CAL; \
+    _cal->cal_done = true; \
+} while(0)
+#define DUAL_BAND_ID 0x30303643
+#define SINGLE_BAND_ID 0x30303644
+#define SINGLE_BAND_PATCH(_xtal) \
+do{ \
+    if (REG32_R(ADR_CHIP_ID_2) == SINGLE_BAND_ID){ \
+        SET_RG_SX_LPF_C2_WF(0xE); \
+        SET_RG_XO_LDO_LEVEL(0x6); \
+        SET_RG_SX_LDO_LO_LEVEL(0x3); \
+        SET_RG_SX_VCO_RXOB_AW(0x1); \
+        SET_RG_SX_VCO_TXOB_AW(0x1); \
+        SET_RG_SX_CP_ISEL_WF(xtal_sx_cp_isel_wf[_xtal]); \
+    } \
+} while (0)
+#define _RESTORE_CAL(_band,_cal) \
+do{ \
+     int i, wifi_dc_addr; \
+                                                                                            \
+    dev_dbg(sh->sc->dev, "Restore calibration result"); \
+                                                                                            \
+    for (i = 0; i < 21; i++) { \
+       wifi_dc_addr = ADR_WF_DCOC_IDAC_REGISTER1+ (i << 2); \
+       REG32_W(wifi_dc_addr,_cal->rxdc_2g[i]); \
+       wifi_dc_addr = (ADR_5G_DCOC_IDAC_REGISTER1)+ (i << 2); \
+       REG32_W(wifi_dc_addr,_cal->rxdc_5g[i]); \
+    } \
+                                                                                            \
+                                                                                            \
+    SET_RG_WF_RX_ABBCTUNE(_cal->rxrc_bw20); \
+    SET_RG_WF_N_RX_ABBCTUNE(_cal->rxrc_bw40); \
+                                                                                            \
+                                                                                            \
+    SET_RG_WF_TX_DAC_IOFFSET(_cal->txdc_i_2g); \
+    SET_RG_WF_TX_DAC_QOFFSET(_cal->txdc_q_2g); \
+                                                                                            \
+                                                                                            \
+    SET_RG_TX_IQ_2500_ALPHA(_cal->txiq_alpha[BAND_2G]); \
+    SET_RG_TX_IQ_2500_THETA(_cal->txiq_theta[BAND_2G]); \
+                                                                                            \
+                                                                                            \
+    SET_RG_RX_IQ_2500_ALPHA(_cal->rxiq_alpha[BAND_2G]); \
+    SET_RG_RX_IQ_2500_THETA(_cal->rxiq_theta[BAND_2G]); \
+                                                                                            \
+                                                                                            \
+    if ( _band == AG_BAND_BOTH) { \
+                                                                                            \
+                                                                                            \
+        for (i = 0; i < 21; i++) { \
+           wifi_dc_addr = (ADR_5G_DCOC_IDAC_REGISTER1)+ (i << 2); \
+           REG32_W(wifi_dc_addr,_cal->rxdc_5g[i]); \
+        } \
+                                                                                            \
+                                                                                            \
+        SET_RG_5G_TX_DAC_IOFFSET(_cal->txdc_i_5g); \
+        SET_RG_5G_TX_DAC_QOFFSET(_cal->txdc_q_5g); \
+                                                                                            \
+                                                                                            \
+        SET_RG_TX_IQ_5100_ALPHA(_cal->txiq_alpha[BAND_5100]); \
+        SET_RG_TX_IQ_5100_THETA(_cal->txiq_theta[BAND_5100]); \
+        SET_RG_TX_IQ_5500_ALPHA(_cal->txiq_alpha[BAND_5500]); \
+        SET_RG_TX_IQ_5500_THETA(_cal->txiq_theta[BAND_5500]); \
+        SET_RG_TX_IQ_5700_ALPHA(_cal->txiq_alpha[BAND_5700]); \
+        SET_RG_TX_IQ_5700_THETA(_cal->txiq_theta[BAND_5700]); \
+        SET_RG_TX_IQ_5900_ALPHA(_cal->txiq_alpha[BAND_5900]); \
+        SET_RG_TX_IQ_5900_THETA(_cal->txiq_theta[BAND_5900]); \
+                                                                                            \
+                                                                                            \
+        SET_RG_RX_IQ_5100_ALPHA(_cal->rxiq_alpha[BAND_5100]); \
+        SET_RG_RX_IQ_5100_THETA(_cal->rxiq_theta[BAND_5100]); \
+        SET_RG_RX_IQ_5500_ALPHA(_cal->rxiq_alpha[BAND_5500]); \
+        SET_RG_RX_IQ_5500_THETA(_cal->rxiq_theta[BAND_5500]); \
+        SET_RG_RX_IQ_5700_ALPHA(_cal->rxiq_alpha[BAND_5700]); \
+        SET_RG_RX_IQ_5700_THETA(_cal->rxiq_theta[BAND_5700]); \
+        SET_RG_RX_IQ_5900_ALPHA(_cal->rxiq_alpha[BAND_5900]); \
+        SET_RG_RX_IQ_5900_THETA(_cal->rxiq_theta[BAND_5900]); \
+    } \
+} while(0)
+#define _INIT_TURISMOC_SYS(_patch,_cal) \
+do{ \
+    PRINT_INFO("RF table ver %s PHY table ver %s, common code ver %s ", \
+        SSV6006_TURISMOC_RF_TABLE_VER, SSV6006_TURISMOC_PHY_TABLE_VER, \
+        SSV6006_TURISMOC_COMMON_CODE_VER); \
+    LOAD_TURISMOC_RF_TABLE(_patch); \
+    SET_RG_EN_IOTADC_160M(0); \
+    dev_dbg(sh->sc->dev, "Set XTAL to %sM", xtal_type[_patch.xtal]); \
+    SET_RG_DP_XTAL_FREQ(_patch.xtal); \
+    SET_RG_SX_XTAL_FREQ(_patch.xtal); \
+    TU_INIT_TURISMOC_PLL; \
+    REG32_W(ADR_WIFI_PHY_COMMON_ENABLE_REG, 0); \
+    LOAD_TURISMOC_PHY_TABLE; \
+    SINGLE_BAND_PATCH(_patch.xtal); \
+                                                                                            \
+    SET_CLK_DIGI_SEL(_patch.cpu_clk); \
+    UDELAY(1); \
+} while(0)
+#define INIT_TURISMOC_SYS(_patch,_band,_cal) \
+do{ \
+    _INIT_TURISMOC_SYS(_patch, _cal); \
+                                                                                            \
+    if (_cal->cal_done){ \
+        _RESTORE_CAL(_band, _cal); \
+    } else { \
+        if (_band == G_BAND_ONLY){ \
+            TU_INIT_TURISMOC_2G_FAST_CALI(_cal); \
+        } else { \
+            TU_INIT_TURISMOC_FAST_CALI(_cal); \
+        } \
+    } \
+} while(0)
+#define INIT_TURISMOC_SYS_IQK(_patch,_band,_cal) \
+do{ \
+    _INIT_TURISMOC_SYS(_patch, _cal); \
+                                                                                            \
+    if (_cal->cal_done){ \
+        _RESTORE_CAL(_band, _cal); \
+    } else { \
+        if (_band == G_BAND_ONLY){ \
+            TU_INIT_TURISMOC_2G_CALI(_cal); \
+        } else { \
+            TU_INIT_TURISMOC_CALI(_cal); \
+        } \
+    } \
+} while(0)
+#define SET_HT20_G_RESP_RATE \
+do{ \
+    SET_MTX_RESPFRM_RATE_90_B0(0x9090); \
+    SET_MTX_RESPFRM_RATE_91_B1(0x9090); \
+    SET_MTX_RESPFRM_RATE_92_B2(0x9090); \
+    SET_MTX_RESPFRM_RATE_93_B3(0x9292); \
+    SET_MTX_RESPFRM_RATE_94_B4(0x9292); \
+    SET_MTX_RESPFRM_RATE_95_B5(0x9494); \
+    SET_MTX_RESPFRM_RATE_96_B6(0x9494); \
+    SET_MTX_RESPFRM_RATE_97_B7(0x9494); \
+} while(0)
+#define SET_HT40_G_RESP_RATE \
+do { \
+    SET_MTX_RESPFRM_RATE_90_B0(0xB0B0); \
+    SET_MTX_RESPFRM_RATE_91_B1(0xB0B0); \
+    SET_MTX_RESPFRM_RATE_92_B2(0xB0B0); \
+    SET_MTX_RESPFRM_RATE_93_B3(0xB2B2); \
+    SET_MTX_RESPFRM_RATE_94_B4(0xB2B2); \
+    SET_MTX_RESPFRM_RATE_95_B5(0xB4B4); \
+    SET_MTX_RESPFRM_RATE_96_B6(0xB4B4); \
+    SET_MTX_RESPFRM_RATE_97_B7(0xB4B4); \
+} while (0)
+#define TU_SET_TURISMOC_BW(_ch_type) \
+do{ \
+                                                                                            \
+    switch (_ch_type){ \
+      case NL80211_CHAN_HT20: \
+      case NL80211_CHAN_NO_HT: \
+                                                                                            \
+            SET_MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_SECONDARY(1); \
+                                                                                            \
+            SET_REG(ADR_WIFI_PHY_COMMON_SYS_REG, \
+                (0 << RG_PRIMARY_CH_SIDE_SFT) | (0 << RG_SYSTEM_BW_SFT), 0, \
+                (RG_PRIMARY_CH_SIDE_I_MSK & RG_SYSTEM_BW_I_MSK)); \
+                                                                                            \
+            SET_REG(ADR_DIGITAL_ADD_ON_0, \
+                (0 << RG_40M_MODE_SFT) | (0 << RG_LO_UP_CH_SFT), 0, \
+                (RG_40M_MODE_I_MSK & RG_LO_UP_CH_I_MSK)); \
+                                                                                            \
+            SET_HT20_G_RESP_RATE; \
+            break; \
+                                                                                            \
+   case NL80211_CHAN_HT40MINUS: \
+                                                                                            \
+            SET_MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_SECONDARY(0); \
+                                                                                            \
+            SET_REG(ADR_WIFI_PHY_COMMON_SYS_REG, \
+                (1 << RG_PRIMARY_CH_SIDE_SFT) | (1 << RG_SYSTEM_BW_SFT), 0, \
+                (RG_PRIMARY_CH_SIDE_I_MSK & RG_SYSTEM_BW_I_MSK)); \
+                                                                                            \
+            SET_REG(ADR_DIGITAL_ADD_ON_0, \
+                (1 << RG_40M_MODE_SFT) | (0 << RG_LO_UP_CH_SFT), 0, \
+                (RG_40M_MODE_I_MSK & RG_LO_UP_CH_I_MSK)); \
+                                                                                            \
+            SET_HT40_G_RESP_RATE; \
+            break; \
+   case NL80211_CHAN_HT40PLUS: \
+                                                                                            \
+            SET_MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_SECONDARY(0); \
+                                                                                            \
+            SET_REG(ADR_WIFI_PHY_COMMON_SYS_REG, \
+                (0 << RG_PRIMARY_CH_SIDE_SFT) | (1 << RG_SYSTEM_BW_SFT), 0, \
+                (RG_PRIMARY_CH_SIDE_I_MSK & RG_SYSTEM_BW_I_MSK)); \
+                                                                                            \
+            SET_REG(ADR_DIGITAL_ADD_ON_0, \
+                (1 << RG_40M_MODE_SFT) | (1 << RG_LO_UP_CH_SFT), 0, \
+                (RG_40M_MODE_I_MSK & RG_LO_UP_CH_I_MSK)); \
+                                                                                            \
+            SET_HT40_G_RESP_RATE; \
+            break; \
+      default: \
+            break; \
+    } \
+} while(0)
+#define TURISMOC_SET_5G_CHANNEL(_ch) \
+do{ \
+    int regval; \
+                                                                                            \
+    SET_RG_RF_5G_BAND(1); \
+                                                                                            \
+                                                                                            \
+    SET_RG_MODE_MANUAL(1); \
+                                                                                            \
+                                                                                            \
+    SET_RG_SX5GB_RFCH_MAP_EN(1); \
+                                                                                            \
+    regval = GET_RG_SX5GB_CHANNEL; \
+                                                                                            \
+    if (regval == _ch){ \
+        if (_ch != 36) \
+           SET_RG_SX5GB_CHANNEL(36); \
+        else \
+           SET_RG_SX5GB_CHANNEL(40); \
+                                                                                            \
+    } \
+    UDELAY(100); \
+                                                                                            \
+                                                                                            \
+    SET_RG_SX5GB_CHANNEL(_ch); \
+                                                                                            \
+                                                                                            \
+    SET_RG_MODE(0); \
+                                                                                            \
+                                                                                            \
+    SET_RG_MODE(7); \
+                                                                                            \
+                                                                                            \
+    SET_RG_MODE_MANUAL(0); \
+                                                                                            \
+                                                                                            \
+    SET_RG_SOFT_RST_N_11GN_RX(1); \
+} while(0)
+#define TURISMOC_SET_2G_CHANNEL(_ch) \
+do{ \
+    int regval; \
+                                                                                            \
+    SET_RG_RF_5G_BAND(0); \
+                                                                                            \
+                                                                                            \
+    SET_RG_MODE_MANUAL(1); \
+                                                                                            \
+                                                                                            \
+    SET_RG_SX_RFCH_MAP_EN(1); \
+                                                                                            \
+    regval = GET_RG_SX_CHANNEL; \
+                                                                                            \
+    if (regval == _ch){ \
+        if (_ch != 1) \
+           SET_RG_SX_CHANNEL(1); \
+        else \
+           SET_RG_SX_CHANNEL(11); \
+                                                                                            \
+    } \
+    UDELAY(100); \
+                                                                                            \
+                                                                                            \
+    SET_RG_SX_CHANNEL(_ch); \
+                                                                                            \
+                                                                                            \
+    SET_RG_MODE(0); \
+                                                                                            \
+                                                                                            \
+    SET_RG_MODE(3); \
+                                                                                            \
+                                                                                            \
+    SET_RG_MODE_MANUAL(0); \
+                                                                                            \
+                                                                                            \
+    SET_RG_SOFT_RST_N_11B_RX(1); \
+    SET_RG_SOFT_RST_N_11GN_RX(1); \
+} while(0)
+#define MULTIPLIER 1024
+#define DPD_SET_TXSCALE_GET_RESULT(_rg_tx_scale,_am,_pm) \
+do { \
+    int regval; \
+                                                                                            \
+    SET_RG_TX_SCALE(_rg_tx_scale); \
+    UDELAY(200); \
+    SET_RG_RX_PADPD_LATCH(1); \
+    UDELAY(10); \
+    SET_RG_RX_PADPD_LATCH(0); \
+    regval= REG32_R(ADR_WIFI_PADPD_CAL_RX_RO); \
+    _am = (regval >>16) & 0x1ff; \
+    _pm = regval & 0x1fff; \
+} while(0)
+#define PRE_PADPD(_pa_band,_init_gain) \
+do { \
+    SET_RG_DPD_AM_EN(0); \
+    SET_RG_TXGAIN_PHYCTRL(1); \
+                                                                                            \
+    SET_RG_MODE_MANUAL(1); \
+    SET_RG_MODE(MODE_STANDBY); \
+                                                                                            \
+    if (_pa_band == 0){ \
+        SET_REG(ADR_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE, \
+            (0x6 << RG_SX_CHANNEL_SFT) | (0x1 << RG_SX_RFCH_MAP_EN_SFT), 0, \
+        (RG_SX_CHANNEL_I_MSK & RG_SX_RFCH_MAP_EN_I_MSK)); \
+        SET_RG_TX_GAIN_DPDCAL(6); \
+        SET_RG_PGAG_DPDCAL(_init_gain); \
+        SET_RG_RFG_DPDCAL(0); \
+        SET_RG_TX_GAIN(PAPDP_GAIN_SETTING_2G); \
+        SET_RG_DPD_BB_SCALE_2500(0x80); \
+    } else { \
+        SET_RG_SX5GB_RFCH_MAP_EN(1); \
+        SET_RG_SX5GB_CHANNEL(cal_ch_5g[_pa_band-1]); \
+                                                                                            \
+        SET_RG_5G_PGAG_DPDCAL(_init_gain); \
+        SET_RG_5G_RFG_DPDCAL(0); \
+                                                                                            \
+        switch (_pa_band){ \
+            case BAND_5100: \
+                SET_RG_5G_TX_PAFB_EN_F0(0); \
+                SET_RG_5G_TX_GAIN_F0(PAPDP_GAIN_SETTING); \
+                SET_RG_5G_TX_GAIN_DPDCAL(PAPDP_GAIN_SETTING); \
+                SET_RG_DPD_BB_SCALE_5100(0x80); \
+                break; \
+            case BAND_5500: \
+                SET_RG_5G_TX_PAFB_EN_F1(0); \
+                SET_RG_5G_TX_GAIN_F1(PAPDP_GAIN_SETTING); \
+                SET_RG_5G_TX_GAIN_DPDCAL(PAPDP_GAIN_SETTING); \
+                SET_RG_DPD_BB_SCALE_5500(0x80); \
+                break; \
+            case BAND_5700: \
+                SET_RG_5G_TX_PAFB_EN_F2(0); \
+                SET_RG_5G_TX_GAIN_F2(PAPDP_GAIN_SETTING_F2); \
+                SET_RG_5G_TX_GAIN_DPDCAL(PAPDP_GAIN_SETTING_F2); \
+                SET_RG_DPD_BB_SCALE_5700(0x80); \
+                break; \
+            case BAND_5900: \
+                SET_RG_5G_TX_PAFB_EN_F3(0); \
+                SET_RG_5G_TX_GAIN_F3(PAPDP_GAIN_SETTING); \
+                SET_RG_5G_TX_GAIN_DPDCAL(PAPDP_GAIN_SETTING); \
+                SET_RG_DPD_BB_SCALE_5900(0x80); \
+                break; \
+            default: \
+                break; \
+        } \
+    } \
+    SET_RG_BB_SIG_EN(1); \
+                                                                                            \
+    SET_RG_DC_RM_BYP(1); \
+                                                                                            \
+    SET_RG_TX_IQ_SRC(2); \
+    SET_RG_TX_BB_SCALE_MANUAL(1); \
+                                                                                            \
+    SET_RG_TX_SCALE(0x80); \
+    SET_RG_TONE_1_RATE(0xccc); \
+    SET_RG_TONE_SEL(1); \
+                                                                                            \
+    SET_RG_RX_PADPD_TONE_SEL(0); \
+    SET_RG_RX_PADPD_DATA_SEL(0); \
+    SET_RG_RX_PADPD_LEAKY_FACTOR(7); \
+    SET_RG_RX_PADPD_EN(1); \
+                                                                                            \
+                                                                                            \
+    SET_RG_MODE(MODE_CALIBRATION); \
+                                                                                            \
+    if (_pa_band == 0) { \
+       SET_RG_CAL_INDEX(CAL_IDX_WIFI2P4G_PADPD); \
+    } else { \
+       SET_RG_CAL_INDEX(CAL_IDX_WIFI5G_PADPD); \
+    } \
+                                                                                            \
+    UDELAY(100); \
+} while(0)
+#define POST_PADPD \
+do { \
+    SET_RG_CAL_INDEX(CAL_IDX_NONE); \
+    SET_RG_MODE(MODE_STANDBY); \
+    SET_RG_MODE_MANUAL(0); \
+                                                                                            \
+    SET_RG_BB_SIG_EN(0); \
+    SET_RG_DC_RM_BYP(0); \
+    SET_RG_TX_IQ_SRC(0); \
+    SET_RG_TX_BB_SCALE_MANUAL(0); \
+                                                                                            \
+    SET_RG_TX_SCALE(0x80); \
+                                                                                            \
+    SET_RG_TONE_SEL(0); \
+                                                                                            \
+    SET_RG_RX_PADPD_EN(0); \
+} while(0)
+#define CHECK_PADPD_GAIN(_pa_band,_init_gain,_ret) \
+do{ \
+    int rg_tx_scale; \
+    int am, pm; \
+                                                                                            \
+    dev_dbg(sh->sc->dev, "check PA DPD on band %d", pa_band); \
+                                                                                            \
+    PRE_PADPD(_pa_band, _init_gain); \
+                                                                                            \
+    rg_tx_scale = 48+(MAX_PADPD_TONE - 1-5)*4; \
+    DPD_SET_TXSCALE_GET_RESULT( rg_tx_scale, am, pm); \
+    if (am >=510) { \
+        *_ret = 1; \
+        dev_dbg(sh->sc->dev, "gain probe fail, am %d", am); \
+    } \
+                                                                                            \
+    POST_PADPD; \
+                                                                                            \
+} while(0)
+#define START_PADPD(_val,_pa_band,_init_gain,dpd_bbscale,_ret) \
+do { \
+    int i, rg_tx_scale, regval; \
+    int am, pm; \
+    int slope_ini = 0, phase_ini = 0; \
+    int padpd_am = 0, padpd_pm = 0; \
+    u32 addr_am = 0, addr_pm = 0 , mask_am = 0, mask_pm = 0; \
+                                                                                            \
+    dev_dbg(sh->sc->dev, "start PA DPD on band %d", _pa_band); \
+                                                                                            \
+    PRE_PADPD(_pa_band, _init_gain); \
+                                                                                            \
+    for (i = 0; i < MAX_PADPD_TONE; i++) { \
+                                                                                            \
+        if( i < 6 ){ \
+            rg_tx_scale = (i+1)*8; \
+        } else { \
+            rg_tx_scale = 48+(i-5)*4; \
+        } \
+        DPD_SET_TXSCALE_GET_RESULT( rg_tx_scale, am, pm); \
+        if (am >=510) { \
+            *_ret = 1; \
+            break; \
+        } \
+        if ( i == 0) { \
+            slope_ini = (am * MULTIPLIER) / rg_tx_scale; \
+            phase_ini = pm; \
+                                                                                                \
+        } \
+                                                                                                \
+        if (am != 0) \
+           padpd_am = (512 * rg_tx_scale * slope_ini ) / (am*MULTIPLIER); \
+                                                                                            \
+        if (padpd_am > 1023){ \
+            padpd_am = 1023; \
+        } \
+                                                                                            \
+        padpd_pm = (phase_ini >= pm) ? (phase_ini - pm) : (phase_ini - pm + 8192); \
+                                                                                            \
+        dev_dbg(sh->sc->dev, "index %d, padpd_am %d, padpd_pm 0x%04x, ", i, padpd_am, padpd_pm); \
+                                                                                            \
+        addr_am = padpd_am_addr_table[pa_band][(i >> 1)]; \
+        mask_am = am_mask[i%2]; \
+        addr_pm = padpd_pm_addr_table[pa_band][(i >> 1)]; \
+        mask_pm = pm_mask[i%2]; \
+                                                                                            \
+        regval = REG32_R(addr_am); \
+        REG32_W(addr_am, (regval & mask_am) | ((padpd_am) << ((i & 0x1)*16)) ); \
+        if (i & 0x1){ \
+            _val->am[ (i >> 1)] = (regval & mask_am) | ((padpd_am) << ((i & 0x1)*16)); \
+        } \
+                                                                                            \
+        regval = REG32_R(addr_pm); \
+        REG32_W(addr_pm, (regval & mask_pm) | ((padpd_pm) << ((i & 0x1)*16)) ); \
+                                                                                            \
+        if (i & 0x1){ \
+            _val->pm[ (i >> 1)] = (regval & mask_pm) | ((padpd_pm) << ((i & 0x1)*16)); \
+        } \
+    } \
+                                                                                            \
+    POST_PADPD; \
+                                                                                            \
+    if (*_ret != 1){ \
+        switch (_pa_band){ \
+            case BAND_2G: \
+                SET_RG_DPD_BB_SCALE_2500(dpd_bbscale); \
+                break; \
+            case BAND_5100: \
+                SET_RG_DPD_BB_SCALE_5100(dpd_bbscale); \
+                break; \
+            case BAND_5500: \
+                 SET_RG_DPD_BB_SCALE_5500(dpd_bbscale); \
+                                                                                            \
+                break; \
+            case BAND_5700: \
+                 SET_RG_DPD_BB_SCALE_5700(dpd_bbscale); \
+                                                                                            \
+                break; \
+            case BAND_5900: \
+                 SET_RG_DPD_BB_SCALE_5900(dpd_bbscale); \
+                                                                                            \
+                break; \
+            default: \
+                break; \
+        } \
+                                                                                            \
+        SET_RG_DPD_AM_EN(1); \
+        SET_RG_TXGAIN_PHYCTRL(0); \
+    } \
+} while(0)
+#define TU_RESTORE_DPD(_dpd) \
+do{ \
+    int i; \
+    u32 addr_am, addr_pm; \
+                                                                                            \
+    for (i = 0; i < (MAX_PADPD_TONE/2) ; i++) { \
+                                                                                            \
+        addr_am = padpd_am_addr_table[_dpd->current_band][i]; \
+        addr_pm = padpd_pm_addr_table[_dpd->current_band][i]; \
+                                                                                            \
+        REG32_W(addr_am, _dpd->val[_dpd->current_band].am[i] ); \
+        REG32_W(addr_pm, _dpd->val[_dpd->current_band].pm[i] ); \
+                                                                                            \
+    } \
+                                                                                            \
+    switch (_dpd->current_band){ \
+        case BAND_2G: \
+            SET_RG_DPD_BB_SCALE_2500(_dpd->bbscale[0]); \
+            break; \
+        case BAND_5100: \
+            SET_RG_DPD_BB_SCALE_5100(_dpd->bbscale[1]); \
+            break; \
+        case BAND_5500: \
+            SET_RG_DPD_BB_SCALE_5500(_dpd->bbscale[2]); \
+            break; \
+        case BAND_5700: \
+            SET_RG_DPD_BB_SCALE_5700(_dpd->bbscale[3]); \
+            break; \
+        case BAND_5900: \
+            SET_RG_DPD_BB_SCALE_5900(_dpd->bbscale[4]); \
+            break; \
+        default: \
+            break; \
+    } \
+    SET_RG_DPD_AM_EN(1); \
+    SET_RG_TXGAIN_PHYCTRL(0); \
+} while(0)
+#define VERIFY_DPD(_dpd,_pa_band) \
+do { \
+    u8 hw_dpd_bbscale; \
+                                                                                            \
+    switch (_pa_band){ \
+        case BAND_2G: \
+            hw_dpd_bbscale = GET_RG_DPD_BB_SCALE_2500; \
+            break; \
+        case BAND_5100: \
+            hw_dpd_bbscale = GET_RG_DPD_BB_SCALE_5100; \
+            break; \
+        case BAND_5500: \
+            hw_dpd_bbscale = GET_RG_DPD_BB_SCALE_5500; \
+            break; \
+        case BAND_5700: \
+            hw_dpd_bbscale = GET_RG_DPD_BB_SCALE_5700; \
+            break; \
+        case BAND_5900: \
+            hw_dpd_bbscale = GET_RG_DPD_BB_SCALE_5900; \
+            break; \
+        default: \
+            hw_dpd_bbscale = 0; \
+            break; \
+    } \
+                                                                                            \
+    if (hw_dpd_bbscale == 0x80){ \
+                                                                                            \
+        dev_dbg(sh->sc->dev, "HW DPD value changed, restore DPD"); \
+        TU_RESTORE_DPD(_dpd); \
+    } \
+} while(0)
+#ifdef COMMON_FOR_REDBULL
+#define _VERIFY_DPD(_dpd,_pa_band)
+#else
+#define _VERIFY_DPD(_dpd,_pa_band) VERIFY_DPD(_dpd, _pa_band)
+#endif
+#define TURN_OFF_PADPD(_dpd,_ch) \
+do { \
+    int pa_band; \
+                                                                                            \
+    pa_band = ssv6006_get_pa_band(_ch); \
+    _dpd->dpd_disable[pa_band] = true; \
+} while(0)
+#define TURN_ON_PADPD(_dpd,_ch) \
+do { \
+    int pa_band; \
+                                                                                            \
+    pa_band = ssv6006_get_pa_band(_ch); \
+    _dpd->dpd_disable[pa_band] = false; \
+} while(0)
+#define CHECK_PADPD(_dpd,_pa_band) \
+do { \
+    int ret = 0; \
+    struct ssv6006dpd *val; \
+    int *pret = &ret; \
+    u8 dpd_bbscale = 0; \
+                                                                                            \
+    val = &_dpd->val[_pa_band]; \
+    dpd_bbscale = _dpd->bbscale[_pa_band]; \
+                                                                                            \
+    if (_dpd->dpd_disable[_pa_band] == true) { \
+        if (_dpd->current_band != _pa_band){ \
+                                                                                            \
+            SET_RG_DPD_AM_EN(0); \
+            SET_RG_TXGAIN_PHYCTRL(0); \
+        } \
+    } else { \
+                                                                                            \
+        if ( _dpd->dpd_done[_pa_band] == false) { \
+            int init_gain = 4; \
+                                                                                            \
+            SET_RG_DPD_AM_EN(0); \
+            if (_pa_band != 0) init_gain = 2; \
+            dev_dbg(sh->sc->dev, "Start PADPD on band %d ,init gain %d", _pa_band, init_gain); \
+            while (1){ \
+                ret = 0; \
+                START_PADPD(val, _pa_band, init_gain, dpd_bbscale, pret); \
+                if (!ret){ \
+                    dev_dbg(sh->sc->dev, "PA DPD done!!"); \
+                    _dpd->dpd_done[_pa_band] = true; \
+                    break; \
+                } \
+                init_gain--; \
+                dev_dbg(sh->sc->dev, "Failed on band %d, Lower gain to %d", pa_band, init_gain); \
+                if (init_gain < 0) { \
+                    SET_RG_DPD_AM_EN(0); \
+                    dev_err(sh->sc->dev, "WARNING:PADPD FAIL on band %d", _pa_band); \
+                    break; \
+                } \
+            } \
+        } else { \
+            _VERIFY_DPD(_dpd, _pa_band); \
+        } \
+    } \
+    _dpd->current_band = _pa_band; \
+} while(0)
+#define START_IQK(_sh,_cal,_pa_band) \
+do { \
+                                                                                            \
+   SET_RG_DPD_AM_EN(0); \
+   SET_RG_TXGAIN_PHYCTRL(1); \
+   if (_pa_band == BAND_2G){ \
+       turismo_pre_cal(_sh); \
+       TURISMOC_TXIQ_CAL(_cal); \
+       turismo_inter_cal(_sh); \
+       TURISMOC_RXIQ_CAL(_cal); \
+       turismo_post_cal(_sh); \
+   } else { \
+       turismo_pre_cal(_sh); \
+       TURISMOC_5G_TXIQ_CAL_BAND(_cal, _pa_band); \
+       turismo_inter_cal(_sh); \
+       TURISMOC_5G_RXIQ_CAL_BAND(_cal, _pa_band); \
+       turismo_post_cal(_sh); \
+   } \
+} while(0)
+#ifdef COMMON_FOR_REDBULL
+#define CHECK_IQK(_cal,_pa_band)
+#else
+#ifdef COMMON_FOR_SMAC
+#define CHECK_IQK(_cal,_pa_band) \
+do { \
+    if (_cal->cal_iq_done[_pa_band] == false) { \
+        dev_dbg(sh->sc->dev, "do iqk on band %d", _pa_band); \
+                                                                                            \
+        START_IQK(sh, _cal, _pa_band); \
+        _cal->cal_iq_done[_pa_band] = true; \
+    } \
+} while(0)
+#else
+#define CHECK_IQK(_cal,_pa_band) \
+do { \
+    SSV_HW *sh = NULL; \
+    if (_cal->cal_iq_done[_pa_band] == false) { \
+        dev_dbg(sh->sc->dev, "do iqk on band %d", _pa_band); \
+                                                                                            \
+        START_IQK(sh, _cal, _pa_band); \
+        _cal->cal_iq_done[_pa_band] = true; \
+    } \
+} while (0)
+#endif
+#endif
+#define CHECK_PADPD_IQK(_dpd,_cal,_ch) \
+do { \
+    int pa_band = 0; \
+                                                                                            \
+    pa_band = ssv6006_get_pa_band(_ch); \
+                                                                                            \
+    CHECK_IQK(_cal, pa_band); \
+    CHECK_PADPD(_dpd, pa_band); \
+} while(0)
+#define REMOVE_SPUR_PATCH(_dpd,_cal) \
+do{ \
+    if (_dpd->spur_patched){ \
+        SET_RG_EN_RX_PADSW(0); \
+        SET_RG_SC_CTRL0(0); \
+        SET_RG_ERASE_SC_NUM0(0x7f); \
+        SET_RG_SC_CTRL1(0); \
+        SET_RG_ERASE_SC_NUM1(0x7f); \
+                                                                                            \
+        SET_RG_ATCOR16_RATIO_CCD(0x30); \
+        SET_RG_ATCOR16_CCA_GAIN(0x0); \
+        _dpd->spur_patched = false; \
+    } \
+} while (0)
+#define CHECK_SPUR(_dpd,_cal,_ch,_ch_type) \
+do { \
+    int pa_band = 0; \
+    int xtal, chip_id; \
+                                                                                            \
+    xtal = GET_RG_DP_XTAL_FREQ; \
+    chip_id = REG32_R(ADR_CHIP_ID_2); \
+                                                                                            \
+    if (chip_id == DUAL_BAND_ID){ \
+        if (xtal != XTAL40M) \
+            break; \
+    } \
+    pa_band = ssv6006_get_pa_band(_ch); \
+    if (_cal->cal_iq_done[pa_band] == true){ \
+                                                                                            \
+     if ((_ch >=13) || ((_ch >= 9) && (_ch_type == NL80211_CHAN_HT40PLUS))){ \
+                                                                                         \
+         SET_RG_EN_RX_PADSW(1); \
+         _dpd->spur_patched = true; \
+        } \
+                                                                                            \
+        if (chip_id == SINGLE_BAND_ID){ \
+            if ((_ch == 13) \
+                && ((_ch_type == NL80211_CHAN_NO_HT) || (_ch_type == NL80211_CHAN_HT20))){ \
+                SET_RG_SC_CTRL0(1); \
+                SET_RG_ERASE_SC_NUM0(22); \
+                SET_RG_SC_CTRL1(1); \
+                SET_RG_ERASE_SC_NUM1(23); \
+            } else if (((_ch == 9) && (_ch_type == NL80211_CHAN_HT40PLUS)) \
+                        || ((_ch == 13) && (_ch_type == NL80211_CHAN_HT40MINUS))) { \
+                SET_RG_SC_CTRL0(1); \
+                SET_RG_ERASE_SC_NUM0(52); \
+                SET_RG_SC_CTRL1(1); \
+                SET_RG_ERASE_SC_NUM1(53); \
+            } \
+        } \
+        if ((ch == 13) && \
+            ((_ch_type == NL80211_CHAN_NO_HT) || (_ch_type == NL80211_CHAN_HT20) || \
+                (_ch_type == NL80211_CHAN_HT40MINUS))){ \
+                                                                                            \
+         SET_RG_ATCOR16_RATIO_CCD(0x18); \
+            SET_RG_ATCOR16_CCA_GAIN(0x1); \
+        } \
+    } \
+} while (0)
+#define TU_CHANGE_TURISMOC_CHANNEL(_ch,_ch_type,_dpd,_cal) \
+do{ \
+    const char *chan_type[]={"NL80211_CHAN_NO_HT", \
+     "NL80211_CHAN_HT20", \
+     "NL80211_CHAN_HT40MINUS", \
+     "NL80211_CHAN_HT40PLUS"}; \
+                                                                                            \
+    dev_dbg(sh->sc->dev, "%s: ch %d, type %s", __func__, _ch, chan_type[_ch_type]); \
+    SET_RG_SOFT_RST_N_11B_RX(0); \
+    SET_RG_SOFT_RST_N_11GN_RX(0); \
+                                                                                            \
+    REMOVE_SPUR_PATCH(_dpd, _cal); \
+                                                                                            \
+    if (REG32_R(ADR_WIFI_PHY_COMMON_ENABLE_REG) != 0) { \
+                                                                                            \
+        CHECK_PADPD_IQK(_dpd, _cal, _ch); \
+    } \
+                                                                                            \
+    TU_SET_TURISMOC_BW(_ch_type); \
+    if ( _ch <=14 && _ch >=1){ \
+        SET_SIFS(10); \
+     SET_SIGEXT(6); \
+        CHECK_SPUR(_dpd, _cal, _ch, _ch_type); \
+        TURISMOC_SET_2G_CHANNEL( _ch); \
+    } else if (_ch >=34){ \
+     SET_SIFS(16); \
+     SET_SIGEXT(0); \
+        TURISMOC_SET_5G_CHANNEL(_ch); \
+    } else { \
+        dev_dbg(sh->sc->dev, "invalid channel %d", _ch); \
+    } \
+                                                                                            \
+} while(0)
+#define TU_DISABLE_TURISMOC_DPD(_dpd) \
+do { \
+    int pa_band; \
+                                                                                            \
+    for (pa_band = 0; pa_band <= 4; pa_band++){ \
+                                                                                            \
+        _dpd->dpd_done[pa_band] = true; \
+    } \
+    SET_RG_DPD_AM_EN(0); \
+    SET_RG_TXGAIN_PHYCTRL(0); \
+} while (0)
+#ifdef COMMON_FOR_REDBULL
+#define TU_ENABLE_TURISMOC_DPD(_ch,_dpd) \
+do { \
+    int pa_band; \
+                                                                                            \
+    for (pa_band = 0; pa_band <= 4; pa_band++){ \
+                                                                                            \
+        _dpd->dpd_done[pa_band] = false; \
+    } \
+} while (0)
+#else
+#define TU_ENABLE_TURISMOC_DPD(_ch,_dpd) \
+do { \
+    int pa_band; \
+                                                                                            \
+    for (pa_band = 0; pa_band <= 4; pa_band++){ \
+                                                                                            \
+        _dpd->dpd_done[pa_band] = false; \
+    } \
+    CHECK_PADPD(_dpd, _ch); \
+                                                                                            \
+} while (0)
+#endif
+#define TU_RESTART_RF_PHY(_band,_cal,_patch) \
+do { \
+    LOAD_TURISMOC_RF_TABLE(_patch); \
+    REG32_W(ADR_WIFI_PHY_COMMON_ENABLE_REG, 0); \
+    LOAD_TURISMOC_PHY_TABLE; \
+    SINGLE_BAND_SPUR_PATCH(_patch.xtal); \
+    if (_cal->cal_done){ \
+        _RESTORE_CAL(_band, _cal); \
+    } else { \
+        if (_band == G_BAND_ONLY){ \
+            TU_INIT_TURISMOC_2G_FAST_CALI(_cal); \
+        } else { \
+            TU_INIT_TURISMOC_FAST_CALI(_cal); \
+        } \
+    } \
+} while(0)
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smac/init.c b/drivers/net/wireless/ssv6x5x/smac/init.c
new file mode 100644
index 000000000..7c8c869ee
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/init.c
@@ -0,0 +1,2417 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/nl80211.h>
+#include <linux/kthread.h>
+#include <linux/etherdevice.h>
+#include <linux/version.h>
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,6,0)
+#include <crypto/hash.h>
+#else
+#include <linux/crypto.h>
+#endif
+#include <linux/rtnetlink.h>
+#include <ssv6200.h>
+#include <hci/hctrl.h>
+#include <ssv_version.h>
+#include <ssv_firmware_version.h>
+#include "ssv_skb.h"
+#include "dev_tbl.h"
+#include "dev.h"
+#include "lib.h"
+#include "ssv_rc.h"
+#include "ssv_rc_minstrel.h"
+#include "ap.h"
+#include "efuse.h"
+#include "init.h"
+#include "ssv_skb.h"
+#include "ssv_cli.h"
+#include <hal.h>
+#include <linux_80211.h>
+#ifdef CONFIG_SSV_SUPPORT_ANDROID
+#include "ssv_pm.h"
+#endif
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,0,0)
+#include "linux_2_6_35.h"
+#endif
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+#include "ssv6xxx_debugfs.h"
+#endif
+#ifdef MULTI_THREAD_ENCRYPT
+#include <linux/cpu.h>
+#include <linux/notifier.h>
+#endif
+MODULE_AUTHOR("iComm-semi, Ltd");
+MODULE_DESCRIPTION("Support for SSV6xxx wireless LAN cards.");
+MODULE_SUPPORTED_DEVICE("SSV6xxx 802.11n WLAN cards");
+MODULE_LICENSE("Dual BSD/GPL");
+static const struct ieee80211_iface_limit ssv6xxx_p2p_limits[] = {
+    {
+        .max = 2,
+        .types = BIT(NL80211_IFTYPE_STATION),
+    },
+    {
+        .max = 1,
+        .types = BIT(NL80211_IFTYPE_P2P_GO) |
+        BIT(NL80211_IFTYPE_P2P_CLIENT) |
+        BIT(NL80211_IFTYPE_AP),
+    },
+};
+static const struct ieee80211_iface_combination
+    ssv6xxx_iface_combinations_p2p[] = {
+    {
+        .num_different_channels = 1,
+        .max_interfaces = SSV6200_MAX_VIF,
+        .beacon_int_infra_match = true,
+        .limits = ssv6xxx_p2p_limits,
+        .n_limits = ARRAY_SIZE(ssv6xxx_p2p_limits),
+    },
+};
+#define CHAN2G(_freq,_idx) { \
+    .band = INDEX_80211_BAND_2GHZ, \
+    .center_freq = (_freq), \
+    .hw_value = (_idx), \
+    .max_power = 20, \
+}
+#define CHAN5G(_freq,_idx) { \
+    .band = INDEX_80211_BAND_5GHZ, \
+    .center_freq = (_freq), \
+    .hw_value = (_idx), \
+    .max_power = 20, \
+}
+#ifndef WLAN_CIPHER_SUITE_SMS4
+#define WLAN_CIPHER_SUITE_SMS4 0x00147201
+#endif
+#define SHPCHECK(__hw_rate,__flags) \
+    ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate +3 ) : 0)
+#define RATE(_bitrate,_hw_rate,_flags) { \
+    .bitrate = (_bitrate), \
+    .flags = (_flags), \
+    .hw_value = (_hw_rate), \
+    .hw_value_short = SHPCHECK(_hw_rate,_flags) \
+}
+extern struct ssv6xxx_cfg tu_ssv_cfg;
+static void ssv6xxx_stop_all_running_threads(struct ssv_softc *sc) ;
+static const struct ieee80211_channel ssv6200_2ghz_chantable[] = {
+    CHAN2G(2412, 1 ),
+    CHAN2G(2417, 2 ),
+    CHAN2G(2422, 3 ),
+    CHAN2G(2427, 4 ),
+    CHAN2G(2432, 5 ),
+    CHAN2G(2437, 6 ),
+    CHAN2G(2442, 7 ),
+    CHAN2G(2447, 8 ),
+    CHAN2G(2452, 9 ),
+    CHAN2G(2457, 10),
+    CHAN2G(2462, 11),
+    CHAN2G(2467, 12),
+    CHAN2G(2472, 13),
+    CHAN2G(2484, 14),
+};
+static struct ieee80211_channel ssv6200_5ghz_chantable[] = {
+    CHAN5G(5180, 36),
+    CHAN5G(5200, 40),
+    CHAN5G(5220, 44),
+    CHAN5G(5240, 48),
+    CHAN5G(5260, 52),
+    CHAN5G(5280, 56),
+    CHAN5G(5300, 60),
+    CHAN5G(5320, 64),
+    CHAN5G(5500, 100),
+    CHAN5G(5520, 104),
+    CHAN5G(5540, 108),
+    CHAN5G(5560, 112),
+    CHAN5G(5580, 116),
+    CHAN5G(5600, 120),
+    CHAN5G(5620, 124),
+    CHAN5G(5640, 128),
+    CHAN5G(5660, 132),
+    CHAN5G(5680, 136),
+    CHAN5G(5700, 140),
+    CHAN5G(5720, 144),
+    CHAN5G(5745, 149),
+    CHAN5G(5765, 153),
+    CHAN5G(5785, 157),
+    CHAN5G(5805, 161),
+    CHAN5G(5825, 165),
+};
+
+/*static struct ieee80211_channel ssv6200_5ghz_chantable_no_midband[] = {
+ CHAN5G(5180, 36),
+ CHAN5G(5200, 40),
+ CHAN5G(5220, 44),
+ CHAN5G(5240, 48),
+ CHAN5G(5260, 52),
+ CHAN5G(5280, 56),
+ CHAN5G(5300, 60),
+ CHAN5G(5320, 64),
+ CHAN5G(5745, 149),
+ CHAN5G(5765, 153),
+ CHAN5G(5785, 157),
+ CHAN5G(5805, 161),
+ CHAN5G(5825, 165),
+};*/
+
+
+static struct ieee80211_rate ssv6200_legacy_rates[] = {
+    RATE(10, 0x00, 0),
+    RATE(20, 0x01, 0),
+    RATE(55, 0x02, IEEE80211_RATE_SHORT_PREAMBLE),
+    RATE(110, 0x03, IEEE80211_RATE_SHORT_PREAMBLE),
+    RATE(60, 0x07, 0),
+    RATE(90, 0x08, 0),
+    RATE(120, 0x09, 0),
+    RATE(180, 0x0a, 0),
+    RATE(240, 0x0b, 0),
+    RATE(360, 0x0c, 0),
+    RATE(480, 0x0d, 0),
+    RATE(540, 0x0e, 0),
+};
+#if ((defined CONFIG_SSV_CABRIO_E) && !(defined SSV_SUPPORT_HAL))
+struct ssv6xxx_ch_cfg ch_cfg_z[] = {
+    {ADR_ABB_REGISTER_1, 0, 0x151559fc},
+    {ADR_LDO_REGISTER, 0, 0x00eb7c1c},
+    {ADR_RX_ADC_REGISTER, 0, 0x20d000d2}
+};
+struct ssv6xxx_ch_cfg ch_cfg_p[] = {
+    {ADR_ABB_REGISTER_1, 0, 0x151559fc},
+    {ADR_RX_ADC_REGISTER, 0, 0x20d000d2}
+};
+int ssv6xxx_do_iq_calib(struct ssv_hw *sh, struct ssv6xxx_iqk_cfg *p_cfg)
+{
+    struct sk_buff *skb;
+    struct cfg_host_cmd *host_cmd;
+    int ret = 0;
+    dev_dbg(sh->sc->dev, "# Do init_cali (iq)");
+    skb = ssv_skb_alloc(sh->sc, HOST_CMD_HDR_LEN + IQK_CFG_LEN + PHY_SETTING_SIZE + RF_SETTING_SIZE);
+    if (skb == NULL) {
+        dev_dbg(sh->sc->dev, "init ssv6xxx_do_iq_calib fail!!!");
+    }
+    if ((PHY_SETTING_SIZE > MAX_PHY_SETTING_TABLE_SIZE) ||
+        (RF_SETTING_SIZE > MAX_RF_SETTING_TABLE_SIZE)) {
+        dev_dbg(sh->sc->dev, "Please recheck RF or PHY table size!!!");
+        BUG_ON(1);
+    }
+    skb->data_len = HOST_CMD_HDR_LEN + IQK_CFG_LEN + PHY_SETTING_SIZE + RF_SETTING_SIZE;
+    skb->len = skb->data_len;
+    host_cmd = (struct cfg_host_cmd *)skb->data;
+    host_cmd->c_type = HOST_CMD;
+    host_cmd->h_cmd = (u8)SSV6XXX_HOST_CMD_INIT_CALI;
+    host_cmd->len = skb->data_len;
+    p_cfg->phy_tbl_size = PHY_SETTING_SIZE;
+    p_cfg->rf_tbl_size = RF_SETTING_SIZE;
+    memcpy(host_cmd->dat32, p_cfg, IQK_CFG_LEN);
+    memcpy(host_cmd->dat8+IQK_CFG_LEN, phy_setting, PHY_SETTING_SIZE);
+    memcpy(host_cmd->dat8+IQK_CFG_LEN+PHY_SETTING_SIZE, ssv6200_rf_tbl, RF_SETTING_SIZE);
+    HCI_SEND_CMD(sh, skb);
+    ssv_skb_free(sh->sc, skb);
+    {
+        u32 timeout;
+        sh->sc->iq_cali_done = IQ_CALI_RUNNING;
+        set_current_state(TASK_INTERRUPTIBLE);
+        timeout = wait_event_interruptible_timeout(sh->sc->fw_wait_q,
+                  sh->sc->iq_cali_done,
+                  msecs_to_jiffies(500));
+        set_current_state(TASK_RUNNING);
+        if (timeout == 0)
+            return -ETIME;
+        if (sh->sc->iq_cali_done != IQ_CALI_OK)
+            return (-1);
+    }
+    return ret;
+}
+#endif
+#define HT_CAP_RX_STBC_ONE_STREAM 0x1
+#ifdef CONFIG_SSV_WAPI
+static const u32 ssv6xxx_cipher_suites[] = {
+    WLAN_CIPHER_SUITE_WEP40,
+    WLAN_CIPHER_SUITE_WEP104,
+    WLAN_CIPHER_SUITE_TKIP,
+    WLAN_CIPHER_SUITE_CCMP,
+    WLAN_CIPHER_SUITE_SMS4,
+    WLAN_CIPHER_SUITE_AES_CMAC
+};
+#endif
+#if defined(CONFIG_PM) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
+static const struct wiphy_wowlan_support wowlan_support = {
+#ifdef SSV_WAKEUP_HOST
+    .flags = WIPHY_WOWLAN_ANY,
+#else
+    .flags = WIPHY_WOWLAN_DISCONNECT,
+#endif
+    .n_patterns = 0,
+    .pattern_max_len = 0,
+    .pattern_min_len = 0,
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0))
+    .max_pkt_offset = 0,
+#endif
+};
+#endif
+void ssv6xxx_rc_algorithm(struct ssv_softc *sc)
+{
+    struct ieee80211_hw *hw = sc->hw;
+    hw->rate_control_algorithm = "ssv6xxx_rate_control";
+}
+void ssv6xxx_set_80211_hw_rate_config(struct ssv_softc *sc)
+{
+    struct ieee80211_hw *hw = sc->hw;
+    hw->max_rates = 4;
+    hw->max_rate_tries = HW_MAX_RATE_TRIES;
+}
+static void ssv6xxx_set_80211_hw_capab(struct ssv_softc *sc)
+{
+    struct ieee80211_hw *hw=sc->hw;
+    struct ssv_hw *sh=sc->sh;
+    struct ieee80211_sta_ht_cap *ht_info;
+#ifdef CONFIG_SSV_WAPI
+    hw->wiphy->cipher_suites = ssv6xxx_cipher_suites;
+    hw->wiphy->n_cipher_suites = ARRAY_SIZE(ssv6xxx_cipher_suites);
+#endif
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,2,0)
+    hw->flags = IEEE80211_HW_SIGNAL_DBM;
+#else
+    ieee80211_hw_set(hw, SIGNAL_DBM);
+#endif
+#ifdef CONFIG_SSV_SUPPORT_ANDROID
+#endif
+    SSV_RC_ALGORITHM(sc);
+    ht_info = &sc->sbands[INDEX_80211_BAND_2GHZ].ht_cap;
+    ampdu_db_log("sh->cfg.hw_caps = 0x%x", sh->cfg.hw_caps);
+    if (sh->cfg.hw_caps & SSV6200_HW_CAP_HT) {
+        if (sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_RX) {
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,2,0)
+            hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
+            hw->flags |= IEEE80211_HW_SPECTRUM_MGMT;
+            ampdu_db_log("set IEEE80211_HW_AMPDU_AGGREGATION(0x%x)", ((hw->flags)&IEEE80211_HW_AMPDU_AGGREGATION));
+#else
+            ieee80211_hw_set(hw, AMPDU_AGGREGATION);
+            ieee80211_hw_set(hw, SPECTRUM_MGMT);
+            ampdu_db_log("set IEEE80211_HW_AMPDU_AGGREGATION(%d)", ieee80211_hw_check(hw, AMPDU_AGGREGATION));
+#endif
+        }
+        ht_info->cap |= IEEE80211_HT_CAP_SM_PS;
+        if (sh->cfg.hw_caps & SSV6200_HW_CAP_GF)
+            ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD;
+        if (sh->cfg.hw_caps & SSV6200_HW_CAP_STBC)
+            ht_info->cap |= HT_CAP_RX_STBC_ONE_STREAM << IEEE80211_HT_CAP_RX_STBC_SHIFT;
+        if (sh->cfg.hw_caps & SSV6200_HW_CAP_HT40)
+            ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
+        if (sh->cfg.hw_caps & SSV6200_HW_CAP_SGI) {
+            ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
+            if (sh->cfg.hw_caps & SSV6200_HW_CAP_HT40) {
+                ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
+            }
+        }
+        ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_32K;
+        ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
+        memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
+        ht_info->mcs.rx_mask[0] = 0xff;
+        ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
+        ht_info->mcs.rx_highest = cpu_to_le16(SSV6200_RX_HIGHEST_RATE);
+        ht_info->ht_supported = true;
+    }
+    hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0)
+    if (sh->cfg.hw_caps & SSV6200_HW_CAP_P2P) {
+        hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_P2P_CLIENT);
+        hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_P2P_GO);
+        hw->wiphy->iface_combinations = ssv6xxx_iface_combinations_p2p;
+        hw->wiphy->n_iface_combinations = ARRAY_SIZE(ssv6xxx_iface_combinations_p2p);
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0)
+        hw->wiphy->flags |= WIPHY_FLAG_ENFORCE_COMBINATIONS;
+#endif
+    }
+#endif
+#if LINUX_VERSION_CODE > KERNEL_VERSION(3,5,0)
+    hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;
+#endif
+    if (sh->cfg.hw_caps & SSV6200_HW_CAP_AP) {
+        hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_AP);
+#if LINUX_VERSION_CODE > KERNEL_VERSION(3,1,0)
+        hw->wiphy->flags |= WIPHY_FLAG_AP_UAPSD;
+#endif
+    }
+    if (sh->cfg.hw_caps & SSV6200_HW_CAP_TDLS) {
+        hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS;
+        hw->wiphy->flags |= WIPHY_FLAG_TDLS_EXTERNAL_SETUP;
+        dev_dbg(sh->sc->dev, "TDLS function enabled in sta.cfg");
+    }
+    hw->queues = 4;
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,14,0)
+    hw->channel_change_time = 5000;
+#endif
+    hw->max_listen_interval = 1;
+    SSV_SET_80211HW_RATE_CONFIG(sc);
+    hw->extra_tx_headroom = TXPB_OFFSET + AMPDU_DELIMITER_LEN;
+    if (sizeof(struct ampdu_hdr_st) > SSV_SKB_info_size)
+        hw->extra_tx_headroom += sizeof(struct ampdu_hdr_st);
+    else
+        hw->extra_tx_headroom += SSV_SKB_info_size;
+    if (sh->cfg.hw_caps & SSV6200_HW_CAP_2GHZ) {
+        hw->wiphy->bands[INDEX_80211_BAND_2GHZ] =
+            &sc->sbands[INDEX_80211_BAND_2GHZ];
+    }
+    if (sh->cfg.hw_caps & SSV6200_HW_CAP_5GHZ) {
+        memcpy(&sc->sbands[INDEX_80211_BAND_5GHZ].ht_cap, ht_info,
+               sizeof(struct ieee80211_sta_ht_cap));
+        hw->wiphy->bands[INDEX_80211_BAND_5GHZ] =
+            &sc->sbands[INDEX_80211_BAND_5GHZ];
+    }
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0)
+    hw->max_rx_aggregation_subframes = sh->cfg.max_rx_aggr_size;
+    hw->max_tx_aggregation_subframes = 64;
+#endif
+    hw->sta_data_size = sizeof(struct ssv_sta_priv_data);
+    hw->vif_data_size = sizeof(struct ssv_vif_priv_data);
+    memcpy(sh->maddr[0].addr, &sh->cfg.maddr[0][0], ETH_ALEN);
+    hw->wiphy->addresses = sh->maddr;
+    hw->wiphy->n_addresses = 1;
+    if (sh->cfg.hw_caps & SSV6200_HW_CAP_P2P) {
+        int i;
+        for (i = 1; i < SSV6200_MAX_HW_MAC_ADDR; i++) {
+            memcpy(sh->maddr[i].addr, sh->maddr[i-1].addr,
+                   ETH_ALEN);
+            sh->maddr[i].addr[5]++;
+            hw->wiphy->n_addresses++;
+        }
+    }
+    if (!is_zero_ether_addr(sh->cfg.maddr[1])) {
+        memcpy(sh->maddr[1].addr, sh->cfg.maddr[1], ETH_ALEN);
+        if (hw->wiphy->n_addresses < 2)
+            hw->wiphy->n_addresses = 2;
+    }
+#if defined(CONFIG_PM) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,11,0))
+    hw->wiphy->wowlan = wowlan_support;
+#else
+    hw->wiphy->wowlan = &wowlan_support;
+#endif
+#endif
+}
+#ifdef MULTI_THREAD_ENCRYPT
+int ssv6xxx_cpu_callback(struct notifier_block *nfb,
+                         unsigned long action,
+                         void *hcpu)
+{
+    struct ssv_softc *sc = container_of(nfb, struct ssv_softc, cpu_nfb);
+    int hotcpu = (unsigned long)hcpu;
+    struct ssv_encrypt_task_list *ta = NULL;
+    switch (action) {
+    case CPU_UP_PREPARE:
+    case CPU_UP_PREPARE_FROZEN:
+    case CPU_DOWN_FAILED: {
+        int cpu = 0;
+        list_for_each_entry(ta, &sc->encrypt_task_head, list) {
+            if(cpu == hotcpu)
+                break;
+            cpu++;
+        }
+        if(ta->encrypt_task->state & TASK_UNINTERRUPTIBLE) {
+            kthread_bind(ta->encrypt_task, hotcpu);
+        }
+        dev_dbg(sc->dev, "encrypt_task %p state is %ld", ta->encrypt_task, ta->encrypt_task->state);
+        break;
+    }
+    case CPU_ONLINE:
+    case CPU_ONLINE_FROZEN: {
+        int cpu = 0;
+        list_for_each_entry(ta, &sc->encrypt_task_head, list) {
+            if(cpu == hotcpu) {
+                ta->cpu_offline = 0;
+                if ( (ta->started == 0) && (cpu_online(cpu)) ) {
+                    wake_up_process(ta->encrypt_task);
+                    ta->started = 1;
+                    dev_dbg(sc->dev, "wake up encrypt_task %p state is %ld, cpu = %d", ta->encrypt_task, ta->encrypt_task->state, cpu);
+                }
+                break;
+            }
+            cpu++;
+        }
+        dev_dbg(sc->dev, "encrypt_task %p state is %ld", ta->encrypt_task, ta->encrypt_task->state);
+        break;
+    }
+#ifdef CONFIG_HOTPLUG_CPU
+    case CPU_UP_CANCELED:
+    case CPU_UP_CANCELED_FROZEN:
+    case CPU_DOWN_PREPARE: {
+        int cpu = 0;
+        list_for_each_entry(ta, &sc->encrypt_task_head, list) {
+            if(cpu == hotcpu) {
+                ta->cpu_offline = 1;
+                break;
+            }
+            cpu++;
+        }
+        dev_dbg(sc->dev, "p = %p",ta->encrypt_task);
+        break;
+    }
+    case CPU_DEAD:
+    case CPU_DEAD_FROZEN: {
+        break;
+    }
+#endif
+    }
+    return NOTIFY_OK;
+}
+#endif
+static void ssv6xxx_preload_sw_cipher(void)
+{
+#ifdef USE_LOCAL_CRYPTO
+    struct crypto_blkcipher *tmpblkcipher;
+    struct crypto_cipher *tmpcipher;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,6,0)
+    struct crypto_ahash *tmphash;
+#else
+    struct crypto_hash *tmphash;
+#endif
+    tmpblkcipher = crypto_alloc_blkcipher("ecb(arc4)", 0, CRYPTO_ALG_ASYNC);
+    if (IS_ERR(tmpblkcipher)) {
+        printk(KERN_ERR " ARC4 cipher allocate fail ");
+    } else {
+        crypto_free_blkcipher(tmpblkcipher);
+    }
+    tmpcipher = crypto_alloc_cipher("aes", 0, CRYPTO_ALG_ASYNC);
+    if (IS_ERR(tmpcipher)) {
+        printk(KERN_ERR " aes cipher allocate fail ");
+    } else {
+        crypto_free_cipher(tmpcipher);
+    }
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,6,0)
+    tmphash =crypto_alloc_ahash("michael_mic", 0, CRYPTO_ALG_ASYNC);
+#else
+    tmphash =crypto_alloc_hash("michael_mic", 0, CRYPTO_ALG_ASYNC);
+#endif
+    if (IS_ERR(tmphash)) {
+        printk(KERN_ERR " mic hash allocate fail ");
+    } else {
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,6,0)
+        crypto_free_ahash(tmphash);
+#else
+        crypto_free_hash(tmphash);
+#endif
+    }
+#endif
+}
+static int tu_ssv6xxx_init_softc(struct ssv_softc *sc)
+{
+    void *channels;
+    int ret=0;
+#ifdef MULTI_THREAD_ENCRYPT
+    unsigned int cpu;
+#endif
+    mutex_init(&sc->mutex);
+    mutex_init(&sc->mem_mutex);
+    sc->config_wq= create_singlethread_workqueue("ssv6xxx_cong_wq");
+    INIT_WORK(&sc->hw_restart_work, ssv6xxx_restart_hw);
+    INIT_WORK(&sc->set_tim_work, ssv6200_set_tim_work);
+    INIT_WORK(&sc->beacon_miss_work, ssv6xxx_beacon_miss_work);
+    INIT_WORK(&sc->bcast_start_work, ssv6200_bcast_start_work);
+    INIT_DELAYED_WORK(&sc->bcast_stop_work, ssv6200_bcast_stop_work);
+    INIT_DELAYED_WORK(&sc->bcast_tx_work, ssv6200_bcast_tx_work);
+    INIT_WORK(&sc->set_ampdu_rx_add_work, ssv6xxx_set_ampdu_rx_add_work);
+    INIT_WORK(&sc->set_ampdu_rx_del_work, ssv6xxx_set_ampdu_rx_del_work);
+#ifdef CONFIG_SSV_SUPPORT_ANDROID
+#ifdef CONFIG_HAS_EARLYSUSPEND
+    sc->early_suspend.level = EARLY_SUSPEND_LEVEL_BLANK_SCREEN + 20;
+    sc->early_suspend.suspend = ssv6xxx_early_suspend;
+    sc->early_suspend.resume = ssv6xxx_late_resume;
+    register_early_suspend(&sc->early_suspend);
+#endif
+    ssv_wakelock_init(sc);
+#endif
+    sc->mac_deci_tbl = sta_deci_tbl;
+    memset((void *)&sc->tx, 0, sizeof(struct ssv_tx));
+    sc->tx.hw_txqid[WMM_AC_VO] = 3;
+    sc->tx.ac_txqid[3] = WMM_AC_VO;
+    sc->tx.hw_txqid[WMM_AC_VI] = 2;
+    sc->tx.ac_txqid[2] = WMM_AC_VI;
+    sc->tx.hw_txqid[WMM_AC_BE] = 1;
+    sc->tx.ac_txqid[1] = WMM_AC_BE;
+    sc->tx.hw_txqid[WMM_AC_BK] = 0;
+    sc->tx.ac_txqid[0] = WMM_AC_BK;
+    INIT_LIST_HEAD(&sc->tx.ampdu_tx_que);
+    spin_lock_init(&sc->tx.ampdu_tx_que_lock);
+    memset((void *)&sc->rx, 0, sizeof(struct ssv_rx));
+    spin_lock_init(&sc->rx.rxq_lock);
+    skb_queue_head_init(&sc->rx.rxq_head);
+    sc->rx.rx_buf = ssv_skb_alloc(sc, MAX_FRAME_SIZE_DMG);
+    if (sc->rx.rx_buf == NULL)
+        return -ENOMEM;
+    memset(&sc->bcast_txq, 0, sizeof(struct ssv6xxx_bcast_txq));
+    spin_lock_init(&sc->bcast_txq.txq_lock);
+    skb_queue_head_init(&sc->bcast_txq.qhead);
+    spin_lock_init(&sc->ps_state_lock);
+    spin_lock_init(&sc->tx_pkt_run_no_lock);
+    init_rwsem(&sc->sta_info_sem);
+#ifdef CONFIG_P2P_NOA
+    spin_lock_init(&sc->p2p_noa.p2p_config_lock);
+#endif
+
+#ifdef CONFIG_SSV_CUSTOM_DOMAIN
+    if (sc->sh->cfg.hw_caps & SSV6200_HW_CAP_2GHZ) {
+        u32 domain_2ghz_channels_size = 0;
+        channels = kmalloc(sizeof(ssv6200_2ghz_chantable), GFP_KERNEL);
+        if (!channels) {
+            goto err_create_channel_list;
+        }
+        dev_dbg(sh->sc->dev, " sc->sh->cfg.domain = %d", sc->sh->cfg.domain);
+        switch (sc->sh->cfg.domain) {
+        case DOMAIN_FCC: // 2.412 ~ 2.462 GHz, 11 channels
+        case DOMAIN_North_America:
+        case DOMAIN_Taiwan:
+            domain_2ghz_channels_size = 11;
+            memcpy(channels, &(ssv6200_2ghz_chantable[0]), sizeof(struct ieee80211_channel) * domain_2ghz_channels_size);
+            break;
+
+        case DOMAIN_china: // 2.412 ~ 2.472 GHz, 13 channels
+        case DOMAIN_Singapore:
+        case DOMAIN_ETSI:
+            domain_2ghz_channels_size = 13;
+            memcpy(channels, &(ssv6200_2ghz_chantable[0]), sizeof(struct ieee80211_channel) * domain_2ghz_channels_size);
+            break;
+
+        case DOMAIN_Japan: // 2.412 ~ 2.484 GHz, 14 channels
+        case DOMAIN_Japan2:
+        case DOMAIN_Korea:
+            domain_2ghz_channels_size = 14;
+            memcpy(channels, &(ssv6200_2ghz_chantable[0]), sizeof(struct ieee80211_channel) * domain_2ghz_channels_size);
+            break;
+
+        case DOMAIN_Israel: // 2.432 ~ 2.472 GHz, 9 channels
+            domain_2ghz_channels_size = 9;
+            memcpy(channels, &(ssv6200_2ghz_chantable[4]), sizeof(struct ieee80211_channel) * domain_2ghz_channels_size);
+            break;
+
+        default: // 2.412 ~ 2.484 GHz, 14 channels
+            domain_2ghz_channels_size = 14;
+            memcpy(channels, &(ssv6200_2ghz_chantable[0]), sizeof(struct ieee80211_channel) * domain_2ghz_channels_size);
+            break;
+        }
+
+        sc->sbands[INDEX_80211_BAND_2GHZ].channels = channels;
+        sc->sbands[INDEX_80211_BAND_2GHZ].band = INDEX_80211_BAND_2GHZ;
+        sc->sbands[INDEX_80211_BAND_2GHZ].n_channels = domain_2ghz_channels_size;
+        sc->sbands[INDEX_80211_BAND_2GHZ].bitrates = ssv6200_legacy_rates;
+        sc->sbands[INDEX_80211_BAND_2GHZ].n_bitrates =
+            ARRAY_SIZE(ssv6200_legacy_rates);
+    }
+#else
+
+
+
+    if (sc->sh->cfg.hw_caps & SSV6200_HW_CAP_2GHZ) {
+        channels = kmemdup(ssv6200_2ghz_chantable,
+                           sizeof(ssv6200_2ghz_chantable), GFP_KERNEL);
+        if (!channels) {
+            goto err_create_channel_list;
+        }
+        sc->sbands[INDEX_80211_BAND_2GHZ].channels = channels;
+        sc->sbands[INDEX_80211_BAND_2GHZ].band = INDEX_80211_BAND_2GHZ;
+        sc->sbands[INDEX_80211_BAND_2GHZ].n_channels =
+            ARRAY_SIZE(ssv6200_2ghz_chantable);
+        sc->sbands[INDEX_80211_BAND_2GHZ].bitrates = ssv6200_legacy_rates;
+        sc->sbands[INDEX_80211_BAND_2GHZ].n_bitrates =
+            ARRAY_SIZE(ssv6200_legacy_rates);
+    }
+#endif
+
+#ifdef CONFIG_SSV_CUSTOM_DOMAIN
+    if (sc->sh->cfg.hw_caps & SSV6200_HW_CAP_5GHZ) {
+        u32 domain_5ghz_channels_size = 0;
+        channels = kmalloc(sizeof(ssv6200_5ghz_chantable), GFP_KERNEL);
+        if (!channels) {
+            goto err_create_channel_list;
+        }
+        switch (sc->sh->cfg.domain) {
+        case DOMAIN_FCC:
+        case DOMAIN_North_America:
+        case DOMAIN_Taiwan:
+            domain_5ghz_channels_size = 25;
+            memcpy(channels, &(ssv6200_5ghz_chantable[0]), sizeof(struct ieee80211_channel) * domain_5ghz_channels_size);
+            break;
+        case DOMAIN_Singapore:
+        case DOMAIN_china:
+        case DOMAIN_ETSI:
+            domain_5ghz_channels_size = 13;
+            memcpy(channels, &(ssv6200_5ghz_chantable_no_midband[0]), sizeof(struct ieee80211_channel) * domain_5ghz_channels_size);
+            break;
+        default:
+            domain_5ghz_channels_size = 25;
+            memcpy(channels, &(ssv6200_5ghz_chantable[0]), sizeof(struct ieee80211_channel) * domain_5ghz_channels_size);
+            break;
+        }
+
+        sc->sbands[INDEX_80211_BAND_5GHZ].channels = channels;
+        sc->sbands[INDEX_80211_BAND_5GHZ].band = INDEX_80211_BAND_2GHZ;
+        sc->sbands[INDEX_80211_BAND_5GHZ].n_channels =
+            domain_5ghz_channels_size;
+        sc->sbands[INDEX_80211_BAND_5GHZ].bitrates = ssv6200_legacy_rates + 4;
+        sc->sbands[INDEX_80211_BAND_5GHZ].n_bitrates =
+            ARRAY_SIZE(ssv6200_legacy_rates) - 4;
+    }
+#else
+
+
+    if (sc->sh->cfg.hw_caps & SSV6200_HW_CAP_5GHZ) {
+        channels = kmemdup(ssv6200_5ghz_chantable,
+                           sizeof(ssv6200_5ghz_chantable), GFP_KERNEL);
+        if (!channels) {
+            goto err_create_channel_list;
+        }
+        sc->sbands[INDEX_80211_BAND_5GHZ].channels = channels;
+        sc->sbands[INDEX_80211_BAND_5GHZ].band = INDEX_80211_BAND_5GHZ;
+        sc->sbands[INDEX_80211_BAND_5GHZ].n_channels =
+            ARRAY_SIZE(ssv6200_5ghz_chantable);
+        sc->sbands[INDEX_80211_BAND_5GHZ].bitrates = ssv6200_legacy_rates + 4;
+        sc->sbands[INDEX_80211_BAND_5GHZ].n_bitrates =
+            ARRAY_SIZE(ssv6200_legacy_rates) - 4 ;
+    }
+
+#endif
+    sc->cur_channel = NULL;
+    sc->hw_chan = (-1);
+    skb_queue_head_init(&sc->rc_report_queue);
+    INIT_WORK(&sc->rc_report_work, ssv6xxx_rc_report_work);
+    sc->rc_report_workqueue = create_workqueue("ssv6xxx_rc_report");
+    sc->rc_report_sechedule = 0;
+#ifdef MULTI_THREAD_ENCRYPT
+    if (SSV_NEED_SW_CIPHER(sc->sh)) {
+        skb_queue_head_init(&sc->preprocess_q);
+        skb_queue_head_init(&sc->crypted_q);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+        sc->max_preprocess_q_len = 0;
+        sc->max_crypted_q_len = 0;
+#endif
+        spin_lock_init(&sc->crypt_st_lock);
+        INIT_LIST_HEAD(&sc->encrypt_task_head);
+        for_each_cpu(cpu, cpu_present_mask) {
+            struct ssv_encrypt_task_list *ta = kzalloc(sizeof(*ta), GFP_KERNEL);
+            memset(ta, 0, sizeof(*ta));
+            ta->encrypt_task = kthread_create_on_node(ssv6xxx_encrypt_task, sc, cpu_to_node(cpu), "%d/ssv6xxx_encrypt_task", cpu);
+            init_waitqueue_head(&ta->encrypt_wait_q);
+            if (!IS_ERR(ta->encrypt_task)) {
+                dev_dbg(sc->dev, "[MT-ENCRYPT]: create kthread %p for CPU %d, ret = %d", ta->encrypt_task, cpu, ret);
+#ifdef KTHREAD_BIND
+                kthread_bind(ta->encrypt_task, cpu);
+#endif
+                list_add_tail(&ta->list, &sc->encrypt_task_head);
+                if (cpu_online(cpu)) {
+                    wake_up_process(ta->encrypt_task);
+                    ta->started = 1;
+                }
+                ta->cpu_no = cpu;
+            } else {
+                dev_dbg(sc->dev, "[MT-ENCRYPT]: Fail to create kthread");
+            }
+        }
+        sc->cpu_nfb.notifier_call = ssv6xxx_cpu_callback;
+#ifdef KTHREAD_BIND
+        register_cpu_notifier(&sc->cpu_nfb);
+#endif
+    }
+#endif
+    init_waitqueue_head(&sc->tx_wait_q);
+    sc->tx_wait_q_woken = 0;
+    skb_queue_head_init(&sc->tx_skb_q);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+    sc->max_tx_skb_q_len = 0;
+#endif
+    sc->tx_task = kthread_run(ssv6xxx_tx_task, sc, "ssv6xxx_tx_task");
+    sc->tx_q_empty = false;
+    skb_queue_head_init(&sc->tx_done_q);
+    init_waitqueue_head(&sc->rx_wait_q);
+    sc->rx_wait_q_woken = 0;
+    skb_queue_head_init(&sc->rx_skb_q);
+    sc->rx_task = kthread_run(ssv6xxx_rx_task, sc, "ssv6xxx_rx_task");
+    if (SSV_NEED_SW_CIPHER(sc->sh)) {
+        ssv6xxx_preload_sw_cipher();
+    }
+    init_waitqueue_head(&sc->fw_wait_q);
+    sc->log_ctrl = LOG_HWIF;
+    sc->sh->priv->dbg_control = true;
+    sc->cmd_data.log_to_ram = false;
+    sc->cmd_data.dbg_log.size = 0;
+    sc->cmd_data.dbg_log.totalsize = 0;
+    sc->cmd_data.dbg_log.data = NULL;
+    init_timer(&sc->house_keeping);
+    sc->house_keeping.expires = jiffies + msecs_to_jiffies(HOUSE_KEEPING_TIMEOUT);
+    sc->house_keeping.function = ssv6xxx_house_keeping;
+    sc->house_keeping.data = (unsigned long)sc;
+    sc->house_keeping_wq= create_singlethread_workqueue("ssv6xxx_house_keeping_wq");
+    INIT_WORK(&sc->rx_stuck_work, ssv6xxx_rx_stuck_process);
+    INIT_WORK(&sc->mib_edca_work, ssv6xxx_mib_edca_process);
+    INIT_WORK(&sc->tx_poll_work, ssv6xxx_tx_poll_process);
+#ifdef CONFIG_SSV_CCI_IMPROVEMENT
+    INIT_WORK(&sc->cci_clean_work, ssv6xxx_cci_clean_process);
+    INIT_WORK(&sc->cci_set_work, ssv6xxx_cci_set_process);
+#endif
+    INIT_WORK(&sc->set_txpwr_work, ssv6xxx_set_txpwr_process);
+    INIT_WORK(&sc->thermal_monitor_work, ssv6xxx_thermal_monitor_process);
+    sc->sc_flags |= SC_OP_DIRECTLY_ACK;
+    atomic_set(&sc->ampdu_tx_frame, 0);
+    sc->directly_ack_high_threshold = sc->sh->cfg.directly_ack_high_threshold;
+    sc->directly_ack_low_threshold = sc->sh->cfg.directly_ack_low_threshold;
+    sc->force_disable_directly_ack_tx = false;
+    return ret;
+err_create_channel_list:
+    kfree(sc->rx.rx_buf);
+    return -ENOMEM;
+}
+static int ssv6xxx_deinit_softc(struct ssv_softc *sc)
+{
+    void *channels;
+    struct sk_buff* skb;
+    u8 remain_size;
+    dev_dbg(sc->dev, "%s():", __FUNCTION__);
+    if (sc->sh->cfg.hw_caps & SSV6200_HW_CAP_2GHZ) {
+        channels = sc->sbands[INDEX_80211_BAND_2GHZ].channels;
+        kfree(channels);
+    }
+    if (sc->sh->cfg.hw_caps & SSV6200_HW_CAP_5GHZ) {
+        channels = sc->sbands[INDEX_80211_BAND_5GHZ].channels;
+        kfree(channels);
+    }
+#ifdef CONFIG_SSV_SUPPORT_ANDROID
+#ifdef CONFIG_HAS_EARLYSUSPEND
+    unregister_early_suspend(&sc->early_suspend);
+#endif
+    ssv_wakelock_destroy(sc);
+#endif
+    ssv_skb_free(sc, sc->rx.rx_buf);
+    sc->rx.rx_buf = NULL;
+    do {
+        skb = ssv6200_bcast_dequeue(&sc->bcast_txq, &remain_size);
+        if(skb)
+            ssv6xxx_txbuf_free_skb(skb, (void*)sc);
+        else
+            break;
+    } while(remain_size);
+#ifdef MULTI_THREAD_ENCRYPT
+    if (SSV_NEED_SW_CIPHER(sc->sh)) {
+        struct ssv_encrypt_task_list *qtask = NULL;
+        if (!list_empty(&sc->encrypt_task_head)) {
+            for (qtask = list_entry((&sc->encrypt_task_head)->next, typeof(*qtask), list);
+                 !list_empty(&sc->encrypt_task_head);
+                 qtask = list_entry((&sc->encrypt_task_head)->next, typeof(*qtask), list)) {
+                list_del(&qtask->list);
+                kfree(qtask);
+            }
+        }
+    }
+    while((skb = skb_dequeue(&sc->preprocess_q)) != NULL) {
+        SKB_info *skb_info = (SKB_info *)skb->head;
+        if(skb_info->crypt_st == PKT_CRYPT_ST_ENC_PRE)
+            ssv6xxx_txbuf_free_skb(skb, (void*)sc);
+        else
+            dev_kfree_skb_any(skb);
+    }
+    while((skb = skb_dequeue(&sc->crypted_q)) != NULL) {
+        SKB_info *skb_info = (SKB_info *)skb->head;
+        if(skb_info->crypt_st == PKT_CRYPT_ST_ENC_DONE)
+            ssv6xxx_txbuf_free_skb(skb, (void*)sc);
+        else
+            dev_kfree_skb_any(skb);
+    }
+    dev_dbg(sc->dev, "[MT-ENCRYPT]: end of de-init");
+#endif
+    dev_dbg(sc->dev, "%s(): Clean RX queues.", __func__);
+    while ((skb = skb_dequeue(&sc->rx_skb_q)) != NULL) {
+        dev_kfree_skb_any(skb);
+    }
+    if (sc->cmd_data.dbg_log.data)
+        kfree(sc->cmd_data.dbg_log.data);
+    flush_workqueue(sc->rc_report_workqueue);
+    destroy_workqueue(sc->rc_report_workqueue);
+    destroy_workqueue(sc->config_wq);
+    del_timer_sync(&sc->house_keeping);
+    destroy_workqueue(sc->house_keeping_wq);
+    return 0;
+}
+static void ssv6xxx_deinit_hwsh(struct ssv_softc *sc)
+{
+    struct ssv_hw *sh = sc->sh;
+    struct list_head *pos, *q;
+    struct ssv_hw_cfg *entry;
+    mutex_lock(&sh->hw_cfg_mutex);
+    list_for_each_safe(pos, q, &sh->hw_cfg) {
+        entry = list_entry(pos, struct ssv_hw_cfg, list);
+        list_del(pos);
+        kfree(entry);
+    }
+    mutex_unlock(&sh->hw_cfg_mutex);
+    if (sh->page_count)
+        kfree(sh->page_count);
+    kfree(sc->sh);
+}
+#ifndef SSV_SUPPORT_HAL
+void ssv6xxx_hw_set_replay_ignore(struct ssv_hw *sh,u8 ignore)
+{
+    u32 temp;
+    SMAC_REG_READ(sh,ADR_SCRT_SET,&temp);
+    temp = temp & SCRT_RPLY_IGNORE_I_MSK;
+    temp |= (ignore << SCRT_RPLY_IGNORE_SFT);
+    SMAC_REG_WRITE(sh,ADR_SCRT_SET, temp);
+}
+void ssv6xxx_flash_read_all_map(struct ssv_hw *sh)
+{
+    return;
+}
+#endif
+extern char *tu_cfgfirmwarepath ;
+int ssv6xxx_load_firmware(struct ssv_hw *sh)
+{
+    int ret=0;
+    u8 firmware_name[SSV_FIRMWARE_MAX] = "";
+    u8 temp_path[SSV_FIRMWARE_PATH_MAX] = "";
+    if (sh->cfg.external_firmware_name[0] != 0x00) {
+        dev_dbg(sh->sc->dev, KERN_INFO "Forced to use firmware \"%s\".",
+               sh->cfg.external_firmware_name);
+        strncpy(firmware_name, sh->cfg.external_firmware_name,
+                SSV_FIRMWARE_MAX-1);
+    } else {
+        SSV_GET_FW_NAME(sh, firmware_name);
+        dev_dbg(sh->sc->dev, KERN_INFO "Using firmware \"%s\".", firmware_name);
+    }
+    if (firmware_name[0] == 0x00) {
+        dev_dbg(sh->sc->dev, KERN_INFO "Not match correct CHIP identity");
+        return -1;
+    }
+    if (tu_cfgfirmwarepath != NULL) {
+        snprintf(temp_path, SSV_FIRMWARE_PATH_MAX, "%s%s", tu_cfgfirmwarepath,
+                 firmware_name);
+        ret = SMAC_LOAD_FW(sh,temp_path, 1);
+        dev_dbg(sh->sc->dev, KERN_INFO "Using firmware at %s", temp_path);
+    } else if (sh->cfg.firmware_path[0] != 0x00) {
+        snprintf(temp_path, SSV_FIRMWARE_PATH_MAX, "%s%s",
+                 sh->cfg.firmware_path, firmware_name);
+        ret = SMAC_LOAD_FW(sh,temp_path, 1);
+        dev_dbg(sh->sc->dev, KERN_INFO "Using firmware at %s", temp_path);
+    } else {
+        ret = SMAC_LOAD_FW(sh,firmware_name, 0);
+    }
+    return ret;
+}
+#ifdef SSV_SUPPORT_HAL
+int tu_ssv6xxx_init_mac(struct ssv_hw *sh)
+{
+    struct ssv_softc *sc=sh->sc;
+    int ret=0;
+    u32 regval;
+    dev_dbg(sh->sc->dev, KERN_INFO "SVN version %d", ssv_root_version);
+    dev_dbg(sh->sc->dev, KERN_INFO "SVN ROOT URL %s ", SSV_ROOT_URl);
+    dev_dbg(sh->sc->dev, KERN_INFO "COMPILER HOST %s ", COMPILERHOST);
+    dev_dbg(sh->sc->dev, KERN_INFO "COMPILER DATE %s ", COMPILERDATE);
+    dev_dbg(sh->sc->dev, KERN_INFO "COMPILER OS %s ", COMPILEROS);
+    dev_dbg(sh->sc->dev, KERN_INFO "COMPILER OS ARCH %s ", COMPILEROSARCH);
+    if(sc->ps_status == PWRSV_ENABLE) {
+#ifdef CONFIG_SSV_SUPPORT_ANDROID
+        dev_dbg(sh->sc->dev, KERN_INFO "%s: wifi Alive lock timeout after 3 secs!",__FUNCTION__);
+        {
+            ssv_wake_timeout(sc, 3);
+            dev_dbg(sh->sc->dev, KERN_INFO "wifi Alive lock!");
+        }
+#endif
+#ifdef CONFIG_SSV_HW_ENCRYPT_SW_DECRYPT
+        HAL_SET_RX_FLOW(sh, RX_DATA_FLOW, RX_HCI);
+#else
+        HAL_SET_RX_FLOW(sh, RX_DATA_FLOW, RX_CIPHER_HCI);
+#endif
+        HAL_SET_RX_FLOW(sh, RX_MGMT_FLOW, RX_HCI);
+        SSV_SET_RX_CTRL_FLOW(sh);
+        HAL_UPDATE_DECISION_TABLE_6(sc->sh, sc->mac_deci_tbl[6]);
+        return ret;
+    }
+    SSV_PHY_ENABLE(sh, false);
+    ret = HAL_INIT_MAC(sh);
+    if (ret)
+        goto exit;
+    ret = ssv6xxx_load_firmware(sh);
+    if (ret)
+        goto exit;
+    SSV_PLL_CHK(sh);
+    SSV_PHY_ENABLE(sh, true);
+    HAL_GET_FW_VERSION(sh, &regval);
+    if (regval == FIRWARE_NOT_MATCH_CODE) {
+        dev_dbg(sh->sc->dev, KERN_INFO "Firmware check CHIP ID fail[0x%08x]!!",regval);
+        ret = -1;
+        goto exit;
+    } else {
+        if (regval == ssv_firmware_version) {
+            dev_dbg(sh->sc->dev, KERN_INFO "Firmware version %d", regval);
+        } else {
+            if (sh->cfg.ignore_firmware_version == 0) {
+                dev_dbg(sh->sc->dev, KERN_INFO "Firmware version mapping not match[0x%08x]!!",regval);
+                dev_dbg(sh->sc->dev, KERN_INFO "It's should be [0x%08x]!!",ssv_firmware_version);
+                ret = -1;
+                goto exit;
+            } else
+                dev_dbg(sh->sc->dev, KERN_INFO "Force ignore_firmware_version");
+        }
+    }
+exit:
+    return ret;
+}
+#else
+#define SMAC_REG_READ_CHECK(SH,REG,VAL,FAIL_EXIT) \
+    do { \
+        ret = SMAC_REG_READ(SH, REG, VAL); \
+        if (ret != 0) {\
+            dev_dbg(sh->sc->dev, KERN_ERR "SMAC_REG_READ Failed @%d.", __LINE__); \
+            goto exit; \
+        } \
+    } while (0)
+#define SMAC_REG_WRITE_CHECK(SH,REG,VAL,FAIL_EXIT) \
+    do { \
+        ret = SMAC_REG_WRITE(SH, REG, VAL); \
+        if (ret != 0) {\
+            dev_dbg(sh->sc->dev, KERN_ERR "SMAC_REG_WRITE Failed @%d.", __LINE__); \
+            goto exit; \
+        } \
+    } while (0)
+#define SMAC_REG_SET_BITS_CHECK(SH,REG,BITS,MASK,FAIL_EXIT) \
+    do { \
+        ret = SMAC_REG_SET_BITS(SH, REG, BITS, MASK); \
+        if (ret != 0) {\
+            dev_dbg(sh->sc->dev, KERN_ERR "SMAC_REG_SET_BITS Failed @%d.", __LINE__); \
+            goto exit; \
+        } \
+    } while (0)
+#define SMAC_REG_CONFIRM_CHECK(SH,REG,VAL,FAIL_EXIT) \
+    do { \
+        ret = SMAC_REG_CONFIRM(SH, REG, VAL); \
+        if (ret != 0) {\
+            dev_dbg(sh->sc->dev, KERN_ERR "SMAC_REG_CONFIRM Failed @%d.", __LINE__); \
+            goto exit; \
+        } \
+    } while (0)
+int tu_ssv6xxx_init_mac(struct ssv_hw *sh)
+{
+    struct ssv_softc *sc=sh->sc;
+    int i = 0, ret = 0;
+#ifdef SSV6200_ECO
+    u32 *ptr, id_len, regval, temp[0x8];
+#else
+    u32 *ptr, id_len, regval;
+#endif
+    char *chip_id = sh->chip_id;
+    dev_dbg(sh->sc->dev, KERN_INFO "SVN version %d", ssv_root_version);
+    dev_dbg(sh->sc->dev, KERN_INFO "SVN ROOT URL %s ", SSV_ROOT_URl);
+    dev_dbg(sh->sc->dev, KERN_INFO "COMPILER HOST %s ", COMPILERHOST);
+    dev_dbg(sh->sc->dev, KERN_INFO "COMPILER DATE %s ", COMPILERDATE);
+    dev_dbg(sh->sc->dev, KERN_INFO "COMPILER OS %s ", COMPILEROS);
+    dev_dbg(sh->sc->dev, KERN_INFO "COMPILER OS ARCH %s ", COMPILEROSARCH);
+    SMAC_REG_READ_CHECK(sh, ADR_IC_TIME_TAG_1, &regval, exit);
+    sh->chip_tag = ((u64)regval<<32);
+    SMAC_REG_READ_CHECK(sh, ADR_IC_TIME_TAG_0, &regval, exit);
+    sh->chip_tag |= (regval);
+    dev_dbg(sh->sc->dev, KERN_INFO "CHIP TAG: %llx ", sh->chip_tag);
+    SMAC_REG_READ_CHECK(sh, ADR_CHIP_ID_3, &regval, exit);
+    *((u32 *)&chip_id[0]) = __be32_to_cpu(regval);
+    SMAC_REG_READ_CHECK(sh, ADR_CHIP_ID_2, &regval, exit);
+    *((u32 *)&chip_id[4]) = __be32_to_cpu(regval);
+    SMAC_REG_READ_CHECK(sh, ADR_CHIP_ID_1, &regval, exit);
+    *((u32 *)&chip_id[8]) = __be32_to_cpu(regval);
+    SMAC_REG_READ_CHECK(sh, ADR_CHIP_ID_0, &regval, exit);
+    *((u32 *)&chip_id[12]) = __be32_to_cpu(regval);
+    chip_id[12+sizeof(u32)] = 0;
+    dev_dbg(sh->sc->dev, KERN_INFO "CHIP ID: %s ",chip_id);
+    if(sc->ps_status == PWRSV_ENABLE) {
+#ifdef CONFIG_SSV_SUPPORT_ANDROID
+        dev_dbg(sh->sc->dev, KERN_INFO "%s: wifi Alive lock timeout after 3 secs!",__FUNCTION__);
+        {
+            ssv_wake_timeout(sc, 3);
+            dev_dbg(sh->sc->dev, KERN_INFO "wifi Alive lock!");
+        }
+#endif
+#ifdef CONFIG_SSV_HW_ENCRYPT_SW_DECRYPT
+        SMAC_REG_WRITE_CHECK(sh, ADR_RX_FLOW_DATA, M_ENG_MACRX|(M_ENG_HWHCI<<4), exit);
+#else
+        SMAC_REG_WRITE_CHECK(sh, ADR_RX_FLOW_DATA,
+                             M_ENG_MACRX|(M_ENG_ENCRYPT_SEC<<4)|(M_ENG_HWHCI<<8),
+                             exit);
+#endif
+        SMAC_REG_WRITE_CHECK(sc->sh, ADR_RX_FLOW_MNG, M_ENG_MACRX|(M_ENG_HWHCI<<4),
+                             exit);
+        SMAC_REG_WRITE_CHECK(sh, ADR_RX_FLOW_CTRL,
+                             M_ENG_MACRX|(M_ENG_CPU<<4)|(M_ENG_HWHCI<<8), exit);
+        SMAC_REG_WRITE_CHECK(sc->sh, ADR_MRX_FLT_TB0+6*4, (sc->mac_deci_tbl[6]), exit);
+        return ret;
+    }
+    SMAC_REG_SET_BITS_CHECK(sh, ADR_PHY_EN_1, (0 << RG_PHY_MD_EN_SFT),
+                            RG_PHY_MD_EN_MSK, exit);
+    SMAC_REG_WRITE_CHECK(sh, ADR_BRG_SW_RST, 1 << MAC_SW_RST_SFT, exit);
+    do {
+        SMAC_REG_READ_CHECK(sh, ADR_BRG_SW_RST, & regval, exit);
+        i ++;
+        if (i >10000) {
+            dev_dbg(sh->sc->dev, "MAC reset fail !!!!");
+            WARN_ON(1);
+            ret = 1;
+            goto exit;
+        }
+    } while (regval != 0);
+    if (sh->cfg.rx_burstread)
+        sh->rx_mode = RX_BURSTREAD_MODE;
+    SMAC_REG_WRITE_CHECK(sc->sh, ADR_TXQ4_MTX_Q_AIFSN, 0xffff2101, exit);
+    SMAC_REG_SET_BITS_CHECK(sc->sh, ADR_MTX_BCN_EN_MISC, 0,
+                            MTX_HALT_MNG_UNTIL_DTIM_MSK, exit);
+    SMAC_REG_WRITE_CHECK(sh, ADR_CONTROL, 0x12000006, exit);
+    SMAC_REG_WRITE_CHECK(sh, ADR_RX_TIME_STAMP_CFG, ((28<<MRX_STP_OFST_SFT)|0x01),
+                         exit);
+    SMAC_REG_WRITE_CHECK(sh, ADR_HCI_TX_RX_INFO_SIZE,
+                         ((u32)(TXPB_OFFSET) << TX_PBOFFSET_SFT) |
+                         ((u32)(sh->tx_desc_len) << TX_INFO_SIZE_SFT) |
+                         ((u32)(sh->rx_desc_len) << RX_INFO_SIZE_SFT) |
+                         ((u32)(sh->rx_pinfo_pad) << RX_LAST_PHY_SIZE_SFT ),
+                         exit
+                        );
+    SMAC_REG_READ_CHECK(sh,ADR_MMU_CTRL, &regval, exit);
+    regval |= (0xff<<MMU_SHARE_MCU_SFT);
+    SMAC_REG_WRITE_CHECK(sh,ADR_MMU_CTRL, regval, exit);
+    SMAC_REG_READ_CHECK(sh,ADR_MRX_WATCH_DOG, &regval, exit);
+    regval &= 0xfffffff0;
+    SMAC_REG_WRITE_CHECK(sh,ADR_MRX_WATCH_DOG, regval, exit);
+    SMAC_REG_READ_CHECK(sh, ADR_TRX_ID_THRESHOLD, &id_len, exit);
+    id_len = (id_len&0xffff0000 ) |
+             (sh->tx_info.tx_id_threshold<<TX_ID_THOLD_SFT)|
+             (sh->rx_info.rx_id_threshold<<RX_ID_THOLD_SFT);
+    SMAC_REG_WRITE_CHECK(sh, ADR_TRX_ID_THRESHOLD, id_len, exit);
+    SMAC_REG_READ_CHECK(sh, ADR_ID_LEN_THREADSHOLD1, &id_len, exit);
+    id_len = (id_len&0x0f )|
+             (sh->tx_info.tx_page_threshold<<ID_TX_LEN_THOLD_SFT)|
+             (sh->rx_info.rx_page_threshold<<ID_RX_LEN_THOLD_SFT);
+    SMAC_REG_WRITE_CHECK(sh, ADR_ID_LEN_THREADSHOLD1, id_len, exit);
+#ifdef CONFIG_SSV_CABRIO_MB_DEBUG
+    SMAC_REG_READ_CHECK(sh, ADR_MB_DBG_CFG3, &regval, exit);
+    regval |= (debug_buffer<<0);
+    SMAC_REG_WRITE_CHECK(sh, ADR_MB_DBG_CFG3, regval, exit);
+    SMAC_REG_READ_CHECK(sh, ADR_MB_DBG_CFG2, &regval, exit);
+    regval |= (DEBUG_SIZE<<16);
+    SMAC_REG_WRITE_CHECK(sh, ADR_MB_DBG_CFG2, regval, exit);
+    SMAC_REG_READ_CHECK(sh, ADR_MB_DBG_CFG1, &regval, exit);
+    regval |= (1<<MB_DBG_EN_SFT);
+    SMAC_REG_WRITE_CHECK(sh, ADR_MB_DBG_CFG1, regval, exit);
+    SMAC_REG_READ_CHECK(sh, ADR_MBOX_HALT_CFG, &regval, exit);
+    regval |= (1<<MB_ERR_AUTO_HALT_EN_SFT);
+    SMAC_REG_WRITE_CHECK(sh, ADR_MBOX_HALT_CFG, regval, exit);
+#endif
+    SMAC_REG_READ_CHECK(sc->sh, ADR_MTX_BCN_EN_MISC, &regval, exit);
+    regval|=(1<<MTX_TSF_TIMER_EN_SFT);
+    SMAC_REG_WRITE_CHECK(sc->sh, ADR_MTX_BCN_EN_MISC, regval, exit);
+#ifdef SSV6200_ECO
+    SMAC_REG_WRITE_CHECK(sh, 0xcd010004, 0x1213, exit);
+    for(i=0; i<SSV_RC_MAX_STA; i++) {
+        if(i==0) {
+            sh->hw_buf_ptr[i] = ssv6xxx_pbuf_alloc(sc, sizeof(phy_info_tbl)+
+                                                   sizeof(struct ssv6xxx_hw_sec), NOTYPE_BUF);
+            if((sh->hw_buf_ptr[i]>>28) != 8) {
+                dev_dbg(sh->sc->dev, "opps allocate pbuf error");
+                WARN_ON(1);
+                ret = 1;
+                goto exit;
+            }
+        } else {
+            sh->hw_buf_ptr[i] = ssv6xxx_pbuf_alloc(sc, sizeof(struct ssv6xxx_hw_sec), NOTYPE_BUF);
+            if((sh->hw_buf_ptr[i]>>28) != 8) {
+                dev_dbg(sh->sc->dev, "opps allocate pbuf error");
+                WARN_ON(1);
+                ret = 1;
+                goto exit;
+            }
+        }
+    }
+    for (i = 0; i < 0x8; i++) {
+        temp[i] = 0;
+        temp[i] = ssv6xxx_pbuf_alloc(sc, 256,NOTYPE_BUF);
+    }
+    for (i = 0; i < 0x8; i++) {
+        if(temp[i] == 0x800e0000)
+            dev_dbg(sh->sc->dev, "0x800e0000");
+        else
+            ssv6xxx_pbuf_free(sc,temp[i]);
+    }
+#else
+    sh->hw_buf_ptr = ssv6xxx_pbuf_alloc(sc, sizeof(phy_info_tbl)+
+                                        sizeof(struct ssv6xxx_hw_sec), NOTYPE_BUF);
+    if((sh->hw_buf_ptr>>28) != 8) {
+        dev_dbg(sh->sc->dev, "opps allocate pbuf error");
+        WARN_ON(1);
+        ret = 1;
+        goto exit;
+    }
+#endif
+#ifdef SSV6200_ECO
+    for(i=0; i<SSV_RC_MAX_STA; i++)
+        sh->hw_sec_key[i] = sh->hw_buf_ptr[i];
+    for(i=0; i<SSV_RC_MAX_STA; i++) {
+        int x;
+        for(x=0; x<sizeof(struct ssv6xxx_hw_sec); x+=4) {
+            SMAC_REG_WRITE_CHECK(sh, sh->hw_sec_key[i]+x, 0, exit);
+        }
+    }
+    SMAC_REG_READ_CHECK(sh, ADR_SCRT_SET, &regval, exit);
+    regval &= SCRT_PKT_ID_I_MSK;
+    regval |= ((sh->hw_sec_key[0] >> 16) << SCRT_PKT_ID_SFT);
+    SMAC_REG_WRITE_CHECK(sh, ADR_SCRT_SET, regval, exit);
+    sh->hw_pinfo = sh->hw_sec_key[0] + sizeof(struct ssv6xxx_hw_sec);
+    for(i=0, ptr=phy_info_tbl; i<PHY_INFO_TBL1_SIZE; i++, ptr++) {
+        SMAC_REG_WRITE_CHECK(sh, ADR_INFO0+i*4, *ptr, exit);
+        SMAC_REG_CONFIRM(sh, ADR_INFO0+i*4, *ptr);
+    }
+#else
+    sh->hw_sec_key = sh->hw_buf_ptr;
+    for(i=0; i<sizeof(struct ssv6xxx_hw_sec); i+=4) {
+        SMAC_REG_WRITE_CHECK(sh, sh->hw_sec_key+i, 0, exit);
+    }
+    SMAC_REG_READ_CHECK(sh, ADR_SCRT_SET, &regval, exit);
+    regval &= SCRT_PKT_ID_I_MSK;
+    regval |= ((sh->hw_sec_key >> 16) << SCRT_PKT_ID_SFT);
+    SMAC_REG_WRITE_CHECK(sh, ADR_SCRT_SET, regval, exit);
+    sh->hw_pinfo = sh->hw_sec_key + sizeof(struct ssv6xxx_hw_sec);
+    for(i=0, ptr=phy_info_tbl; i<PHY_INFO_TBL1_SIZE; i++, ptr++) {
+        SMAC_REG_WRITE_CHECK(sh, ADR_INFO0+i*4, *ptr, exit);
+        SMAC_REG_CONFIRM(sh, ADR_INFO0+i*4, *ptr);
+    }
+#endif
+    for(i=0; i<PHY_INFO_TBL2_SIZE; i++, ptr++) {
+        SMAC_REG_WRITE_CHECK(sh, sh->hw_pinfo+i*4, *ptr, exit);
+        SMAC_REG_CONFIRM(sh, sh->hw_pinfo+i*4, *ptr);
+    }
+    for(i=0; i<PHY_INFO_TBL3_SIZE; i++, ptr++) {
+        SMAC_REG_WRITE_CHECK(sh, sh->hw_pinfo+(PHY_INFO_TBL2_SIZE<<2)+i*4,
+                             *ptr, exit);
+        SMAC_REG_CONFIRM(sh, sh->hw_pinfo+(PHY_INFO_TBL2_SIZE<<2)+i*4, *ptr);
+    }
+    SMAC_REG_WRITE_CHECK(sh, ADR_INFO_RATE_OFFSET, 0x00040000, exit);
+    SMAC_REG_WRITE_CHECK(sh, ADR_INFO_IDX_ADDR, sh->hw_pinfo, exit);
+    SMAC_REG_WRITE_CHECK(sh, ADR_INFO_LEN_ADDR, sh->hw_pinfo+(PHY_INFO_TBL2_SIZE)*4,
+                         exit);
+    dev_dbg(sh->sc->dev, "ADR_INFO_IDX_ADDR[%08x] ADR_INFO_LEN_ADDR[%08x]", sh->hw_pinfo, sh->hw_pinfo+(PHY_INFO_TBL2_SIZE)*4);
+    SMAC_REG_WRITE_CHECK(sh, ADR_GLBLE_SET,
+                         (0 << OP_MODE_SFT) |
+                         (0 << SNIFFER_MODE_SFT) |
+                         (1 << DUP_FLT_SFT) |
+                         (SSV6200_TX_PKT_RSVD_SETTING << TX_PKT_RSVD_SFT) |
+                         ((u32)(RXPB_OFFSET) << PB_OFFSET_SFT),
+                         exit
+                        );
+    SMAC_REG_WRITE_CHECK(sh, ADR_STA_MAC_0, *((u32 *)&sh->cfg.maddr[0][0]), exit);
+    SMAC_REG_WRITE_CHECK(sh, ADR_STA_MAC_1, *((u32 *)&sh->cfg.maddr[0][4]), exit);
+    SMAC_REG_WRITE_CHECK(sh, ADR_BSSID_0, *((u32 *)&sc->bssid[0]), exit);
+    SMAC_REG_WRITE_CHECK(sh, ADR_BSSID_1, *((u32 *)&sc->bssid[4]), exit);
+    SMAC_REG_WRITE_CHECK(sh, ADR_TX_ETHER_TYPE_0, 0x00000000, exit);
+    SMAC_REG_WRITE_CHECK(sh, ADR_TX_ETHER_TYPE_1, 0x00000000, exit);
+    SMAC_REG_WRITE_CHECK(sh, ADR_RX_ETHER_TYPE_0, 0x00000000, exit);
+    SMAC_REG_WRITE_CHECK(sh, ADR_RX_ETHER_TYPE_1, 0x00000000, exit);
+    SMAC_REG_WRITE_CHECK(sh, ADR_REASON_TRAP0, 0x7FBC7F87, exit);
+    SMAC_REG_WRITE_CHECK(sh, ADR_REASON_TRAP1, 0x0000003F, exit);
+#ifndef FW_WSID_WATCH_LIST
+    SMAC_REG_WRITE_CHECK(sh, ADR_TRAP_HW_ID, M_ENG_HWHCI, exit);
+#else
+    SMAC_REG_WRITE_CHECK(sh, ADR_TRAP_HW_ID, M_ENG_CPU, exit);
+#endif
+    SMAC_REG_WRITE_CHECK(sh, ADR_WSID0, 0x00000000, exit);
+    SMAC_REG_WRITE_CHECK(sh, ADR_WSID1, 0x00000000, exit);
+#ifdef CONFIG_SSV_HW_ENCRYPT_SW_DECRYPT
+    SMAC_REG_WRITE_CHECK(sh, ADR_RX_FLOW_DATA, M_ENG_MACRX|(M_ENG_HWHCI<<4), exit);
+#else
+    SMAC_REG_WRITE_CHECK(sh, ADR_RX_FLOW_DATA,
+                         M_ENG_MACRX|(M_ENG_ENCRYPT_SEC<<4)|(M_ENG_HWHCI<<8), exit);
+#endif
+#if defined(CONFIG_P2P_NOA) || defined(CONFIG_RX_MGMT_CHECK)
+    SMAC_REG_WRITE_CHECK(sh, ADR_RX_FLOW_MNG,
+                         M_ENG_MACRX|(M_ENG_CPU<<4)|(M_ENG_HWHCI<<8), exit);
+#else
+    SMAC_REG_WRITE_CHECK(sh, ADR_RX_FLOW_MNG, M_ENG_MACRX|(M_ENG_HWHCI<<4), exit);
+#endif
+    SMAC_REG_WRITE_CHECK(sh, ADR_RX_FLOW_CTRL,
+                         M_ENG_MACRX|(M_ENG_CPU<<4)|(M_ENG_HWHCI<<8),
+                         exit);
+    ssv6xxx_hw_set_replay_ignore(sh, 1);
+    ssv6xxx_update_decision_table(sc);
+    SMAC_REG_SET_BITS_CHECK(sc->sh, ADR_GLBLE_SET, SSV6XXX_OPMODE_STA,
+                            OP_MODE_MSK, exit);
+    SMAC_REG_WRITE_CHECK(sh, ADR_SDIO_MASK, 0xfffe1fff, exit);
+#ifdef CONFIG_SSV_TX_LOWTHRESHOLD
+    SMAC_REG_WRITE_CHECK(sh, ADR_TX_LIMIT_INTR,
+                         ( 0x80000000
+                           | (sh->tx_info.tx_lowthreshold_id_trigger << 16)
+                           | sh->tx_info.tx_lowthreshold_page_trigger),
+                         exit);
+#else
+    SMAC_REG_WRITE_CHECK(sh, ADR_MB_THRESHOLD6, 0x80000000, exit);
+    SMAC_REG_WRITE_CHECK(sh, ADR_MB_THRESHOLD8, 0x04020000, exit);
+    SMAC_REG_WRITE_CHECK(sh, ADR_MB_THRESHOLD9, 0x00000404, exit);
+#endif
+#ifdef CONFIG_SSV_SUPPORT_BTCX
+    SMAC_REG_WRITE_CHECK(sh, ADR_BTCX0,COEXIST_EN_MSK|(WIRE_MODE_SZ<<WIRE_MODE_SFT)
+                         |WIFI_TX_SW_POL_MSK | BT_SW_POL_MSK, exit);
+    SMAC_REG_WRITE_CHECK(sh, ADR_BTCX1,
+                         ( SSV6200_BT_PRI_SMP_TIME
+                           | (SSV6200_BT_STA_SMP_TIME << BT_STA_SMP_TIME_SFT)
+                           | (SSV6200_WLAN_REMAIN_TIME << WLAN_REMAIN_TIME_SFT)),
+                         exit);
+    SMAC_REG_WRITE_CHECK(sh, ADR_SWITCH_CTL,BT_2WIRE_EN_MSK, exit);
+    SMAC_REG_WRITE_CHECK(sh, ADR_PAD7, 1, exit);
+    SMAC_REG_WRITE_CHECK(sh, ADR_PAD8, 0, exit);
+    SMAC_REG_WRITE_CHECK(sh, ADR_PAD9, 1, exit);
+    SMAC_REG_WRITE_CHECK(sh, ADR_PAD25, 1, exit);
+    SMAC_REG_WRITE_CHECK(sh, ADR_PAD27, 8, exit);
+    SMAC_REG_WRITE_CHECK(sh, ADR_PAD28, 8, exit);
+#endif
+    ret = ssv6xxx_load_firmware(sh);
+    if (ret)
+        goto exit;
+    SMAC_REG_SET_BITS_CHECK(sh, ADR_PHY_EN_1, (1 << RG_PHY_MD_EN_SFT),
+                            RG_PHY_MD_EN_MSK, exit);
+    SMAC_REG_READ_CHECK(sh, FW_VERSION_REG, &regval, exit);
+    if (regval == FIRWARE_NOT_MATCH_CODE) {
+        dev_dbg(sh->sc->dev, KERN_INFO "Firmware check CHIP ID fail[0x%08x]!!",regval);
+        SMAC_REG_WRITE_CHECK(sh, FW_VERSION_REG, 0x0, exit);
+        SMAC_REG_READ_CHECK(sh, FW_VERSION_REG, &regval, exit);
+        dev_dbg(sh->sc->dev, KERN_INFO "E-fuse data 0 is[0x%08x]!!",regval);
+        ret = -1;
+        goto exit;
+    } else {
+        if (regval == ssv_firmware_version) {
+            dev_dbg(sh->sc->dev, KERN_INFO "Firmware version %d", regval);
+        } else {
+            if (sh->cfg.ignore_firmware_version == 0) {
+                dev_dbg(sh->sc->dev, KERN_INFO "Firmware version mapping not match[0x%08x]!!",regval);
+                dev_dbg(sh->sc->dev, KERN_INFO "It's should be [0x%08x]!!",ssv_firmware_version);
+                ret = -1;
+                goto exit;
+            } else
+                dev_dbg(sh->sc->dev, KERN_INFO "Force ignore_firmware_version");
+        }
+    }
+exit:
+    return ret;
+}
+#endif
+void ssv6xxx_deinit_mac(struct ssv_softc *sc)
+{
+#ifdef SSV6200_ECO
+    int i;
+    for(i = 0; i < SSV_RC_MAX_STA; i++) {
+        if(sc->sh->hw_buf_ptr[i]) {
+            SSV_FREE_PBUF(sc, sc->sh->hw_buf_ptr[i]);
+        }
+    }
+#else
+    if(sc->sh->hw_buf_ptr) {
+        SSV_FREE_PBUF(sc, sc->sh->hw_buf_ptr[i]);
+    }
+#endif
+}
+void inline ssv6xxx_deinit_hw(struct ssv_softc *sc)
+{
+    dev_dbg(sc->dev, "%s(): ", __FUNCTION__);
+    ssv6xxx_deinit_mac(sc);
+    HAL_DETACH_USB_HCI(sc->sh);
+    SSV_SET_ON3_ENABLE(sc->sh, false);
+}
+#ifdef SSV_SUPPORT_HAL
+static int tu_ssv6xxx_init_hw(struct ssv_hw *sh)
+{
+    int ret = 0;
+    ssv_cabrio_reg *rf_tbl, *phy_tbl ;
+    SSV_SET_ON3_ENABLE(sh, true);
+    HAL_WAIT_USB_ROM_READY(sh);
+    sh->tx_desc_len = HAL_GET_TX_DESC_SIZE(sh);
+    sh->rx_desc_len = HAL_GET_RX_DESC_SIZE(sh);
+    sh->rx_pinfo_pad = 0x04;
+    sh->rx_mode = RX_NORMAL_MODE;
+    SSV_INIT_TX_CFG(sh);
+    SSV_INIT_RX_CFG(sh);
+    HAL_INIT_GPIO_CFG(sh);
+    SSV_INIT_IQK(sh);
+    HAL_CHG_IPD_PHYINFO(sh);
+    HAL_INIT_CH_CFG(sh);
+    HAL_LOAD_PHY_TABLE(sh, &phy_tbl);
+    HAL_LOAD_RF_TABLE(sh, &rf_tbl);
+    HAL_UPDATE_CFG_HW_PATCH(sh, rf_tbl, phy_tbl);
+    HAL_UPDATE_HW_CONFIG(sh, rf_tbl, phy_tbl);
+    if (ret == 0) ret = HAL_SET_PLL_PHY_RF(sh, rf_tbl, phy_tbl);
+    if (ret == 0) ret = HAL_CHG_PAD_SETTING(sh);
+    if (ret == 0) ret = HAL_CHG_CLK_SRC(sh);
+    if (ret == 0) ret = HAL_UPDATE_EFUSE_SETTING(sh);
+    HAL_UPDATE_PRODUCT_HW_SETTING(sh);
+    {
+        struct ieee80211_channel chan;
+        memset(&chan, 0, sizeof( struct ieee80211_channel));
+        chan.hw_value = sh->cfg.def_chan;
+        if ( ret == 0) {
+            ret=HAL_SET_CHANNEL(sh->sc, &chan, NL80211_CHAN_HT20);
+            sh->sc->hw_chan = chan.hw_value;
+            sh->sc->hw_chan_type = NL80211_CHAN_HT20;
+        }
+    }
+    HAL_SET_PHY_MODE(sh, true);
+    return ret;
+}
+#else
+static int tu_ssv6xxx_init_hw(struct ssv_hw *sh)
+{
+    int ret=0,i=0,x=0;
+#ifdef CONFIG_SSV_CABRIO_E
+    u32 regval;
+#endif
+    sh->tx_desc_len = SSV6XXX_TX_DESC_LEN;
+    sh->rx_desc_len = SSV6XXX_RX_DESC_LEN;
+    sh->rx_pinfo_pad = 0x04;
+    sh->rx_mode = RX_NORMAL_MODE;
+    sh->tx_info.tx_id_threshold = SSV6200_ID_TX_THRESHOLD;
+    sh->tx_info.tx_page_threshold = SSV6200_PAGE_TX_THRESHOLD;
+    sh->tx_info.tx_lowthreshold_id_trigger = SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER;
+    sh->tx_info.tx_lowthreshold_page_trigger = SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER;
+    sh->tx_info.bk_txq_size = SSV6200_ID_AC_BK_OUT_QUEUE;
+    sh->tx_info.be_txq_size = SSV6200_ID_AC_BE_OUT_QUEUE;
+    sh->tx_info.vi_txq_size = SSV6200_ID_AC_VI_OUT_QUEUE;
+    sh->tx_info.vo_txq_size = SSV6200_ID_AC_VO_OUT_QUEUE;
+    sh->tx_info.manage_txq_size = SSV6200_ID_MANAGER_QUEUE;
+    sh->tx_page_available = SSV6200_PAGE_TX_THRESHOLD;
+    sh->ampdu_divider = SSV6200_AMPDU_DIVIDER;
+    sh->rx_info.rx_id_threshold = SSV6200_ID_RX_THRESHOLD;
+    sh->rx_info.rx_page_threshold = SSV6200_PAGE_RX_THRESHOLD;
+    SSV_INIT_IQK(sh);
+    memcpy(&(sh->hci.hci_ctrl->tx_info), &(sh->tx_info), sizeof(struct ssv6xxx_tx_hw_info));
+    memcpy(&(sh->hci.hci_ctrl->rx_info), &(sh->rx_info), sizeof(struct ssv6xxx_rx_hw_info));
+#ifdef CONFIG_SSV_CABRIO_E
+    if (sh->cfg.force_chip_identity) {
+        dev_dbg(sh->sc->dev, "Force use external RF setting [%08x]",sh->cfg.force_chip_identity);
+        sh->cfg.chip_identity = sh->cfg.force_chip_identity;
+    }
+    if(sh->cfg.chip_identity == SSV6051Z) {
+        sh->p_ch_cfg = &ch_cfg_z[0];
+        sh->ch_cfg_size = sizeof(ch_cfg_z) / sizeof(struct ssv6xxx_ch_cfg);
+        memcpy(phy_info_tbl,phy_info_6051z,sizeof(phy_info_6051z));
+    } else if(sh->cfg.chip_identity == SSV6051P) {
+        sh->p_ch_cfg = &ch_cfg_p[0];
+        sh->ch_cfg_size = sizeof(ch_cfg_p) / sizeof(struct ssv6xxx_ch_cfg);
+    }
+    switch (sh->cfg.chip_identity) {
+    case SSV6051Q_P1:
+    case SSV6051Q_P2:
+    case SSV6051Q:
+        dev_dbg(sh->sc->dev, "SSV6051Q setting");
+        for (i=0; i<sizeof(ssv6200_rf_tbl)/sizeof(ssv_cabrio_reg); i++) {
+            if (ssv6200_rf_tbl[i].address == 0xCE010008)
+                ssv6200_rf_tbl[i].data = 0x008DF61B;
+            if (ssv6200_rf_tbl[i].address == 0xCE010014)
+                ssv6200_rf_tbl[i].data = 0x3D3E84FE;
+            if (ssv6200_rf_tbl[i].address == 0xCE010018)
+                ssv6200_rf_tbl[i].data = 0x01457D79;
+            if (ssv6200_rf_tbl[i].address == 0xCE01001C)
+                ssv6200_rf_tbl[i].data = 0x000103A7;
+            if (ssv6200_rf_tbl[i].address == 0xCE010020)
+                ssv6200_rf_tbl[i].data = 0x000103A6;
+            if (ssv6200_rf_tbl[i].address == 0xCE01002C)
+                ssv6200_rf_tbl[i].data = 0x00032CA8;
+            if (ssv6200_rf_tbl[i].address == 0xCE010048)
+                ssv6200_rf_tbl[i].data = 0xFCCCCF27;
+            if (ssv6200_rf_tbl[i].address == 0xCE010050)
+                ssv6200_rf_tbl[i].data = 0x0047C000;
+        }
+        break;
+    case SSV6051Z:
+        dev_dbg(sh->sc->dev, "SSV6051Z setting");
+        for (i=0; i<sizeof(ssv6200_rf_tbl)/sizeof(ssv_cabrio_reg); i++) {
+            if (ssv6200_rf_tbl[i].address == 0xCE010008)
+                ssv6200_rf_tbl[i].data = 0x004D561C;
+            if (ssv6200_rf_tbl[i].address == 0xCE010014)
+                ssv6200_rf_tbl[i].data = 0x3D9E84FE;
+            if (ssv6200_rf_tbl[i].address == 0xCE010018)
+                ssv6200_rf_tbl[i].data = 0x00457D79;
+            if (ssv6200_rf_tbl[i].address == 0xCE01001C)
+                ssv6200_rf_tbl[i].data = 0x000103EB;
+            if (ssv6200_rf_tbl[i].address == 0xCE010020)
+                ssv6200_rf_tbl[i].data = 0x000103EA;
+            if (ssv6200_rf_tbl[i].address == 0xCE01002C)
+                ssv6200_rf_tbl[i].data = 0x00062CA8;
+            if (ssv6200_rf_tbl[i].address == 0xCE010048)
+                ssv6200_rf_tbl[i].data = 0xFCCCCF27;
+            if (ssv6200_rf_tbl[i].address == 0xCE010050)
+                ssv6200_rf_tbl[i].data = 0x0047C000;
+        }
+        break;
+    case SSV6051P:
+        dev_dbg(sh->sc->dev, "SSV6051P setting");
+        for (i=0; i<sizeof(ssv6200_rf_tbl)/sizeof(ssv_cabrio_reg); i++) {
+            if (ssv6200_rf_tbl[i].address == 0xCE010008)
+                ssv6200_rf_tbl[i].data = 0x008B7C1C;
+            if (ssv6200_rf_tbl[i].address == 0xCE010014)
+                ssv6200_rf_tbl[i].data = 0x3D7E84FE;
+            if (ssv6200_rf_tbl[i].address == 0xCE010018)
+                ssv6200_rf_tbl[i].data = 0x01457D79;
+            if (ssv6200_rf_tbl[i].address == 0xCE01001C)
+                ssv6200_rf_tbl[i].data = 0x000103EB;
+            if (ssv6200_rf_tbl[i].address == 0xCE010020)
+                ssv6200_rf_tbl[i].data = 0x000103EA;
+            if (ssv6200_rf_tbl[i].address == 0xCE01002C)
+                ssv6200_rf_tbl[i].data = 0x00032CA8;
+            if (ssv6200_rf_tbl[i].address == 0xCE010048)
+                ssv6200_rf_tbl[i].data = 0xFCCCCC27;
+            if (ssv6200_rf_tbl[i].address == 0xCE010050)
+                ssv6200_rf_tbl[i].data = 0x0047C000;
+            if (ssv6200_rf_tbl[i].address == 0xC0001D00)
+                ssv6200_rf_tbl[i].data = 0x5F000040;
+        }
+        break;
+    default:
+        dev_dbg(sh->sc->dev, "No RF setting");
+        dev_dbg(sh->sc->dev, "**************");
+        dev_dbg(sh->sc->dev, "* Call Help! *");
+        dev_dbg(sh->sc->dev, "**************");
+        WARN_ON(1);
+        return -1;
+        break;
+    }
+    if(sh->cfg.crystal_type == SSV6XXX_IQK_CFG_XTAL_26M) {
+        sh->iqk_cfg.cfg_xtal = SSV6XXX_IQK_CFG_XTAL_26M;
+        dev_dbg(sh->sc->dev, "SSV6XXX_IQK_CFG_XTAL_26M");
+    } else if(sh->cfg.crystal_type == SSV6XXX_IQK_CFG_XTAL_40M) {
+        sh->iqk_cfg.cfg_xtal = SSV6XXX_IQK_CFG_XTAL_40M;
+        dev_dbg(sh->sc->dev, "SSV6XXX_IQK_CFG_XTAL_40M");
+    } else if(sh->cfg.crystal_type == SSV6XXX_IQK_CFG_XTAL_24M) {
+        dev_dbg(sh->sc->dev, "SSV6XXX_IQK_CFG_XTAL_24M");
+        sh->iqk_cfg.cfg_xtal = SSV6XXX_IQK_CFG_XTAL_24M;
+        for(i=0; i<sizeof(ssv6200_rf_tbl)/sizeof(ssv_cabrio_reg); i++) {
+            if(ssv6200_rf_tbl[i].address == ADR_SX_ENABLE_REGISTER)
+                ssv6200_rf_tbl[i].data = 0x0003E07C;
+            if(ssv6200_rf_tbl[i].address == ADR_DPLL_DIVIDER_REGISTER)
+                ssv6200_rf_tbl[i].data = 0x00406000;
+            if(ssv6200_rf_tbl[i].address == ADR_DPLL_FB_DIVIDER_REGISTERS_I)
+                ssv6200_rf_tbl[i].data = 0x00000028;
+            if(ssv6200_rf_tbl[i].address == ADR_DPLL_FB_DIVIDER_REGISTERS_II)
+                ssv6200_rf_tbl[i].data = 0x00000000;
+        }
+    } else {
+        dev_dbg(sh->sc->dev, "Illegal xtal setting !![No XX.cfg]");
+        dev_dbg(sh->sc->dev, "default value is SSV6XXX_IQK_CFG_XTAL_26M!!");
+    }
+    for(i=0; i<sizeof(ssv6200_rf_tbl)/sizeof(ssv_cabrio_reg); i++) {
+        if(ssv6200_rf_tbl[i].address == ADR_SYN_KVCO_XO_FINE_TUNE_CBANK) {
+            if(sh->cfg.crystal_frequency_offset) {
+                ssv6200_rf_tbl[i].data &= RG_XOSC_CBANK_XO_I_MSK;
+                ssv6200_rf_tbl[i].data |= (sh->cfg.crystal_frequency_offset << RG_XOSC_CBANK_XO_SFT);
+            }
+        }
+    }
+    for (i=0; i<sizeof(phy_setting)/sizeof(ssv_cabrio_reg); i++) {
+        if (phy_setting[i].address == ADR_TX_GAIN_FACTOR) {
+            switch (sh->cfg.chip_identity) {
+            case SSV6051Q_P1:
+            case SSV6051Q_P2:
+            case SSV6051Q:
+                dev_dbg(sh->sc->dev, "SSV6051Q setting [0x5B606C72]");
+                phy_setting[i].data = 0x5B606C72;
+                break;
+            case SSV6051Z:
+                dev_dbg(sh->sc->dev, "SSV6051Z setting [0x60606060]");
+                phy_setting[i].data = 0x60606060;
+                break;
+            case SSV6051P:
+                dev_dbg(sh->sc->dev, "SSV6051P setting [0x6C726C72]");
+                phy_setting[i].data = 0x6C726C72;
+                break;
+            default:
+                dev_dbg(sh->sc->dev, "Use default power setting");
+                break;
+            }
+            if (sh->cfg.wifi_tx_gain_level_b) {
+                phy_setting[i].data &= 0xffff0000;
+                phy_setting[i].data |= wifi_tx_gain[sh->cfg.wifi_tx_gain_level_b] & 0x0000ffff;
+            }
+            if (sh->cfg.wifi_tx_gain_level_gn) {
+                phy_setting[i].data &= 0x0000ffff;
+                phy_setting[i].data |= wifi_tx_gain[sh->cfg.wifi_tx_gain_level_gn] & 0xffff0000;
+            }
+            dev_dbg(sh->sc->dev, "TX power setting 0x%x",phy_setting[i].data);
+            sh->iqk_cfg.cfg_def_tx_scale_11b = (phy_setting[i].data>>0) & 0xff;
+            sh->iqk_cfg.cfg_def_tx_scale_11b_p0d5 = (phy_setting[i].data>>8) & 0xff;
+            sh->iqk_cfg.cfg_def_tx_scale_11g = (phy_setting[i].data>>16) & 0xff;
+            sh->iqk_cfg.cfg_def_tx_scale_11g_p0d5 = (phy_setting[i].data>>24) & 0xff;
+            break;
+        }
+    }
+    if(sh->cfg.volt_regulator == SSV6XXX_VOLT_LDO_CONVERT) {
+        dev_dbg(sh->sc->dev, "Volt regulator LDO");
+        for(i=0; i<sizeof(ssv6200_rf_tbl)/sizeof(ssv_cabrio_reg); i++) {
+            if(ssv6200_rf_tbl[i].address == ADR_PMU_2) {
+                ssv6200_rf_tbl[i].data &= 0xFFFFFFFE;
+                ssv6200_rf_tbl[i].data |= 0x00000000;
+            }
+        }
+    } else if(sh->cfg.volt_regulator == SSV6XXX_VOLT_DCDC_CONVERT) {
+        dev_dbg(sh->sc->dev, "Volt regulator DCDC");
+        for(i=0; i<sizeof(ssv6200_rf_tbl)/sizeof(ssv_cabrio_reg); i++) {
+            if(ssv6200_rf_tbl[i].address == ADR_PMU_2) {
+                ssv6200_rf_tbl[i].data &= 0xFFFFFFFE;
+                ssv6200_rf_tbl[i].data |= 0x00000001;
+            }
+        }
+    } else {
+        dev_dbg(sh->sc->dev, "Illegal volt regulator setting !![No XX.cfg]");
+        dev_dbg(sh->sc->dev, "default value is SSV6XXX_VOLT_DCDC_CONVERT!!");
+    }
+#endif
+    while(tu_ssv_cfg.configuration[x][0]) {
+        for(i=0; i<sizeof(ssv6200_rf_tbl)/sizeof(ssv_cabrio_reg); i++) {
+            if(ssv6200_rf_tbl[i].address == tu_ssv_cfg.configuration[x][0]) {
+                ssv6200_rf_tbl[i].data = tu_ssv_cfg.configuration[x][1];
+                break;
+            }
+        }
+        for(i=0; i<sizeof(phy_setting)/sizeof(ssv_cabrio_reg); i++) {
+            if(phy_setting[i].address == tu_ssv_cfg.configuration[x][0]) {
+                phy_setting[i].data = tu_ssv_cfg.configuration[x][1];
+                break;
+            }
+        }
+        x++;
+    };
+    if (ret == 0) ret = SSV6XXX_SET_HW_TABLE(sh, ssv6200_rf_tbl);
+    if (ret == 0) ret = SMAC_REG_WRITE(sh, ADR_PHY_EN_1, 0x00000000);
+#ifdef CONFIG_SSV_CABRIO_E
+    SMAC_REG_READ(sh, ADR_PHY_EN_0, &regval);
+    if (regval & (1<<RG_RF_BB_CLK_SEL_SFT)) {
+        dev_dbg(sh->sc->dev, "already do clock switch");
+    } else {
+        dev_dbg(sh->sc->dev, "reset PLL");
+        SMAC_REG_READ(sh, ADR_DPLL_CP_PFD_REGISTER, &regval);
+        regval |= ((1<<RG_DP_BBPLL_PD_SFT) | (1<<RG_DP_BBPLL_SDM_EDGE_SFT));
+        SMAC_REG_WRITE(sh, ADR_DPLL_CP_PFD_REGISTER, regval);
+        regval &= ~((1<<RG_DP_BBPLL_PD_SFT) | (1<<RG_DP_BBPLL_SDM_EDGE_SFT));
+        SMAC_REG_WRITE(sh, ADR_DPLL_CP_PFD_REGISTER, regval);
+        mdelay(10);
+    }
+#endif
+    if (ret == 0) ret = SSV6XXX_SET_HW_TABLE(sh, ssv6200_phy_tbl);
+#ifdef CONFIG_SSV_CABRIO_E
+    if (ret == 0) ret = SMAC_REG_WRITE(sh, ADR_TRX_DUMMY_REGISTER, 0xEAAAAAAA);
+    SMAC_REG_READ(sh,ADR_TRX_DUMMY_REGISTER,&regval);
+    if (regval != 0xEAAAAAAA) {
+        dev_dbg(sh->sc->dev, "@@@@@@@@@@@@");
+        dev_dbg(sh->sc->dev, " SDIO issue -- please check 0xCE01008C %08x!!",regval);
+        dev_dbg(sh->sc->dev, " It shouble be 0xEAAAAAAA!!");
+        dev_dbg(sh->sc->dev, "@@@@@@@@@@@@ ");
+    }
+#endif
+#ifdef CONFIG_SSV_CABRIO_E
+    if (ret == 0) ret = SMAC_REG_WRITE(sh, ADR_PAD53, 0x21);
+    if (ret == 0) ret = SMAC_REG_WRITE(sh, ADR_PAD54, 0x3000);
+    if (ret == 0) ret = SMAC_REG_WRITE(sh, ADR_PIN_SEL_0, 0x4000);
+    if (ret == 0) ret = SMAC_REG_WRITE(sh, 0xc0000304, 0x01);
+    if (ret == 0) ret = SMAC_REG_WRITE(sh, 0xc0000308, 0x01);
+#endif
+    if (ret == 0) ret = SMAC_REG_WRITE(sh, ADR_CLOCK_SELECTION, 0x3);
+#ifdef CONFIG_SSV_CABRIO_E
+    if (ret == 0) ret = SMAC_REG_WRITE(sh, ADR_TRX_DUMMY_REGISTER, 0xAAAAAAAA);
+#endif
+    {
+        struct ieee80211_channel chan;
+        memset(&chan, 0, sizeof( struct ieee80211_channel));
+        chan.hw_value = sh->cfg.def_chan;
+        if ((ret=ssv6xxx_set_channel(sh->sc, &chan, NL80211_CHAN_HT20)))
+            return ret;
+    }
+    if (ret == 0) ret = SMAC_REG_WRITE(sh, ADR_PHY_EN_1,
+                                           (RG_PHYRX_MD_EN_MSK | RG_PHYTX_MD_EN_MSK |
+                                            RG_PHY11GN_MD_EN_MSK | RG_PHY11B_MD_EN_MSK |
+                                            RG_PHYRXFIFO_MD_EN_MSK | RG_PHYTXFIFO_MD_EN_MSK |
+                                            RG_PHY11BGN_MD_EN_MSK));
+    return ret;
+}
+#endif
+static void ssv6xxx_save_hw_config(void *param, u32 addr, u32 value)
+{
+    struct ssv_softc *sc = (struct ssv_softc *)param;
+    struct ssv_hw *sh = sc->sh;
+    struct list_head *pos, *q;
+    struct ssv_hw_cfg *entry;
+    struct ssv_hw_cfg *new_cfg;
+    bool find = false;
+    if (!(sc->sh->cfg.online_reset & ONLINE_RESET_ENABLE) || (sc->sc_flags & SC_OP_HW_RESET))
+        return;
+    mutex_lock(&sh->hw_cfg_mutex);
+    list_for_each_safe(pos, q, &sh->hw_cfg) {
+        entry = list_entry(pos, struct ssv_hw_cfg, list);
+        if (entry->addr == addr) {
+            entry->value = value;
+            find = true;
+            break;
+        }
+    }
+    if (!find) {
+        new_cfg = (struct ssv_hw_cfg *)kmalloc(sizeof(struct ssv_hw_cfg), GFP_KERNEL);
+        memset(new_cfg, 0, sizeof(struct ssv_hw_cfg));
+        new_cfg->addr = addr;
+        new_cfg->value = value;
+        list_add_tail(&(new_cfg->list), &(sh->hw_cfg));
+    }
+    mutex_unlock(&sh->hw_cfg_mutex);
+}
+static void ssv6xxx_restore_hw_config(struct ssv_softc *sc)
+{
+    struct ssv_hw *sh = sc->sh;
+    struct list_head *pos, *q;
+    struct ssv_hw_cfg *entry;
+    mutex_lock(&sh->hw_cfg_mutex);
+    list_for_each_safe(pos, q, &sh->hw_cfg) {
+        entry = list_entry(pos, struct ssv_hw_cfg, list);
+        SMAC_REG_WRITE(sh, entry->addr, entry->value);
+    }
+    mutex_unlock(&sh->hw_cfg_mutex);
+}
+void ssv6xxx_restart_hw(struct work_struct *work)
+{
+    struct ssv_softc *sc = container_of(work, struct ssv_softc, hw_restart_work);
+    struct ieee80211_channel *chan;
+    enum nl80211_channel_type channel_type;
+    int i = 0, ret = 0;
+    dev_dbg(sc->dev, "**************************");
+    dev_dbg(sc->dev, "*** Software MAC reset ***");
+    dev_dbg(sc->dev, "**************************");
+    sc->sc_flags |= SC_OP_HW_RESET;
+    sc->restart_counter++;
+    sc->force_triger_reset = true;
+    while (sc->bScanning) {
+        mdelay(100);
+        if (++i > 10000)
+            return;
+    }
+    rtnl_lock();
+    mutex_lock(&sc->mutex);
+    dev_dbg(sc->dev, "%s() start", __FUNCTION__);
+    SSV_BEACON_LOSS_DISABLE(sc->sh);
+    HCI_STOP(sc->sh);
+    SSV_PHY_ENABLE(sc->sh, false);
+    sc->beacon_info[0].pubf_addr = 0x00;
+    sc->beacon_info[1].pubf_addr = 0x00;
+    SSV_SAVE_HW_STATUS(sc);
+    SSV_RESET_SYSPLF(sc->sh);
+    udelay(50);
+    tu_ssv6xxx_init_hw(sc->sh);
+    tu_ssv6xxx_init_mac(sc->sh);
+    ssv6xxx_restore_hw_config(sc);
+    HCI_START(sc->sh);
+    ret = SSV_DO_IQ_CALIB(sc->sh, &sc->sh->iqk_cfg);
+    if (ret != 0) {
+        dev_dbg(sc->dev, "IQ Calibration failed (%d)!!", ret);
+    }
+    SSV_EDCA_ENABLE(sc->sh, true);
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0)
+    chan = sc->hw->conf.channel;
+    channel_type = sc->hw->conf.channel_type;
+#else
+    chan = sc->hw->conf.chandef.chan;
+    channel_type = cfg80211_get_chandef_type(&sc->hw->conf.chandef);
+#endif
+    HAL_SET_CHANNEL(sc, chan, channel_type);
+    SSV_AMPDU_AUTO_CRC_EN(sc->sh);
+    SSV_SET_RF_ENABLE(sc->sh);
+    if (sc->isAssoc )
+        SSV_BEACON_LOSS_ENABLE(sc->sh);
+    mutex_unlock(&sc->mutex);
+    rtnl_unlock();
+    sc->sc_flags &= (~(SC_OP_HW_RESET));
+    sc->house_keeping.expires = jiffies + msecs_to_jiffies(HOUSE_KEEPING_TIMEOUT);
+    if (!timer_pending(&sc->house_keeping))
+        add_timer(&sc->house_keeping);
+}
+static void ssv6xxx_check_mac2(struct ssv_hw *sh)
+{
+    const u8 addr_mask[6]= {0xfd, 0xff, 0xff, 0xff, 0xff, 0xfc};
+    u8 i;
+    bool invalid = false;
+    for ( i=0; i<6; i++) {
+        if ((tu_ssv_cfg.maddr[0][i] & addr_mask[i]) !=
+            (tu_ssv_cfg.maddr[1][i] & addr_mask[i])) {
+            invalid = true;
+            printk (" i %d , mac1[i] %x, mac2[i] %x, mask %x ",i, tu_ssv_cfg.maddr[0][i],tu_ssv_cfg.maddr[1][i],addr_mask[i]);
+            break;
+        }
+    }
+    if (invalid) {
+        memcpy(&tu_ssv_cfg.maddr[1][0], &tu_ssv_cfg.maddr[0][0], 6);
+        tu_ssv_cfg.maddr[1][5] ^= 0x01;
+        if (tu_ssv_cfg.maddr[1][5] < tu_ssv_cfg.maddr[0][5]) {
+            u8 temp;
+            temp = tu_ssv_cfg.maddr[0][5];
+            tu_ssv_cfg.maddr[0][5] = tu_ssv_cfg.maddr[1][5];
+            tu_ssv_cfg.maddr[1][5] = temp;
+            sh->cfg.maddr[0][5] = tu_ssv_cfg.maddr[0][5];
+        }
+        dev_dbg(sh->sc->dev, "MAC 2 address invalid!!" );
+        dev_dbg(sh->sc->dev, "After modification, MAC1 %pM, MAC2 %pM",tu_ssv_cfg.maddr[0],
+               tu_ssv_cfg.maddr[1]);
+    }
+}
+static int ssv6xxx_read_configuration(struct ssv_hw *sh)
+{
+    memcpy(&sh->cfg, &tu_ssv_cfg, sizeof(struct ssv6xxx_cfg));
+    efuse_read_all_map(sh);
+    SSV_FLASH_READ_ALL_MAP(sh);
+    if (!(is_valid_ether_addr(&sh->cfg.maddr[0][0]))) {
+        dev_dbg(sh->sc->dev, "invalid mac addr 1 !!");
+        WARN_ON(1);
+        return 1;
+    }
+    if (SSV_IF_CHK_MAC2(sh)) {
+        ssv6xxx_check_mac2(sh);
+        memcpy(&sh->cfg.maddr[1][0], &tu_ssv_cfg.maddr[1][0], ETH_ALEN);
+    }
+#if 0
+    if(sh->cfg.crystal_type == 26)
+        sh->cfg.crystal_type = SSV6XXX_IQK_CFG_XTAL_26M;
+    else if(sh->cfg.crystal_type == 40)
+        sh->cfg.crystal_type = SSV6XXX_IQK_CFG_XTAL_40M;
+    else if(sh->cfg.crystal_type == 24)
+        sh->cfg.crystal_type = SSV6XXX_IQK_CFG_XTAL_24M;
+    else if(sh->cfg.crystal_type == 25)
+        sh->cfg.crystal_type = SSV6XXX_IQK_CFG_XTAL_25M;
+    else {
+        dev_dbg(sh->sc->dev, "Please redefine xtal_clock(wifi.cfg)!!");
+        WARN_ON(1);
+        return 1;
+    }
+#endif
+    switch (sh->cfg.crystal_type) {
+    case 16:
+        sh->cfg.crystal_type = SSV6XXX_IQK_CFG_XTAL_16M;
+        break;
+    case 24:
+        sh->cfg.crystal_type = SSV6XXX_IQK_CFG_XTAL_24M;
+        break;
+    case 26:
+        sh->cfg.crystal_type = SSV6XXX_IQK_CFG_XTAL_26M;
+        break;
+    case 40:
+        sh->cfg.crystal_type = SSV6XXX_IQK_CFG_XTAL_40M;
+        break;
+    case 12:
+        sh->cfg.crystal_type = SSV6XXX_IQK_CFG_XTAL_12M;
+        break;
+    case 20:
+        sh->cfg.crystal_type = SSV6XXX_IQK_CFG_XTAL_20M;
+        break;
+    case 25:
+        sh->cfg.crystal_type = SSV6XXX_IQK_CFG_XTAL_25M;
+        break;
+    case 32:
+        sh->cfg.crystal_type = SSV6XXX_IQK_CFG_XTAL_32M;
+        break;
+    default:
+        dev_dbg(sh->sc->dev, "Please redefine xtal_clock(wifi.cfg)!!");
+        WARN_ON(1);
+        return 1;
+        break;
+    }
+    if (!sh->flash_config.exist) {
+        if(sh->cfg.volt_regulator < 2)
+            sh->cfg.volt_regulator = tu_ssv_cfg.volt_regulator;
+        else {
+            dev_dbg(sh->sc->dev, "Please redefine volt_regulator(wifi.cfg)!!");
+            WARN_ON(1);
+            return 1;
+        }
+    }
+    SSV_ADJ_CONFIG(sh);
+    return 0;
+}
+static int ssv6xxx_hci_rx_mode(void *args)
+{
+    struct ssv_softc *sc = (struct ssv_softc *)args;
+    struct ssv_hw *sh = sc->sh;
+    return sh->rx_mode;
+}
+static int ssv6xxx_read_hw_info(struct ssv_softc *sc)
+{
+    struct ssv_hw *sh = sc->sh;
+    SSV_GET_IC_TIME_TAG(sh);
+    dev_dbg(sh->sc->dev, KERN_INFO "CHIP TAG: %llx ", sh->chip_tag);
+    if (ssv6xxx_read_configuration(sh))
+        return -ENOMEM;
+    sh->hci.hci_post_tx_cb= ssv6xxx_post_tx_cb;
+    sh->hci.hci_pre_tx_cb = ssv6xxx_pre_tx_cb;
+    sh->hci.hci_skb_update_cb = ssv6xxx_tx_rate_update;
+    sh->hci.hci_tx_flow_ctrl_cb = ssv6200_tx_flow_control;
+    sh->hci.hci_tx_q_empty_cb = ssv6xxx_tx_q_empty_cb;
+    sh->hci.hci_tx_buf_free_cb = ssv6xxx_txbuf_free_skb;
+    sh->hci.hci_rx_mode_cb = ssv6xxx_hci_rx_mode;
+    sh->hci.hci_peek_next_pkt_len_cb = ssv6xxx_peek_next_pkt_len;
+    sh->hci.skb_alloc = ssv_skb_alloc;
+    sh->hci.skb_free = ssv_skb_free;
+    sh->hci.dbgprint = ssv6xxx_hci_dbgprint;
+    sh->hci.write_hw_config_cb = ssv6xxx_save_hw_config;
+    sh->write_hw_config_cb = ssv6xxx_save_hw_config;
+    sh->write_hw_config_args = (void *)sc;
+    return 0;
+}
+#ifndef SSV_SUPPORT_HAL
+static int _alloc_sh (struct ssv_softc *sc)
+{
+    struct ssv_hw *sh;
+    sh = kzalloc(sizeof(struct ssv_hw), GFP_KERNEL);
+    if (sh == NULL)
+        return -ENOMEM;
+    memset((void *)sh, 0, sizeof(struct ssv_hw));
+    sh->page_count = (u8 *)kzalloc(sizeof(u8) * SSV6200_ID_NUMBER, GFP_KERNEL);
+    if (sh->page_count == NULL) {
+        kfree(sh);
+        return -ENOMEM;
+    }
+    memset(sh->page_count, 0, sizeof(u8) * SSV6200_ID_NUMBER);
+    sc->sh = sh;
+    sh->sc = sc;
+    INIT_LIST_HEAD(&sh->hw_cfg);
+    mutex_init(&sh->hw_cfg_mutex);
+    sh->priv = sc->dev->platform_data;
+    sh->hci.if_ops = sh->priv->ops;
+    sh->hci.dev = sc->dev;
+    sh->hci.skb_alloc = ssv_skb_alloc;
+    sh->hci.skb_free = ssv_skb_free;
+    sh->hci.hci_rx_cb = ssv6200_rx;
+    sh->hci.hci_is_rx_q_full = ssv6200_is_rx_q_full;
+    sh->priv->skb_alloc = ssv_skb_alloc_ex;
+    sh->priv->skb_free = ssv_skb_free;
+    sh->priv->skb_param = sc;
+#ifdef CONFIG_PM
+    sh->priv->suspend = ssv6xxx_power_sleep;
+    sh->priv->resume = ssv6xxx_power_awake;
+    sh->priv->pm_param = sc;
+#endif
+    sh->priv->enable_usb_acc = ssv6xxx_enable_usb_acc;
+    sh->priv->disable_usb_acc = ssv6xxx_disable_usb_acc;
+    sh->priv->jump_to_rom = ssv6xxx_jump_to_rom;
+    sh->priv->usb_param = sc;
+    sh->priv->rx_burstread_size = ssv6xxx_rx_burstread_size;
+    sh->priv->rx_burstread_param = sc;
+    sh->hci.sc = sc;
+    sh->hci.sh = sh;
+    return 0;
+}
+#endif
+static int tu_ssv6xxx_init_device(struct ssv_softc *sc, const char *name)
+{
+#ifndef CONFIG_SSV6XXX_HW_DEBUG
+    struct ieee80211_hw *hw = sc->hw;
+#endif
+    struct ssv_hw *sh;
+    int error = 0;
+    BUG_ON(!sc->dev->platform_data);
+#ifndef SSV_SUPPORT_HAL
+    if ((error = _alloc_sh(sc)) != 0) {
+#else
+    if ((error = tu_ssv6xxx_init_hal(sc)) != 0) {
+#endif
+        goto err;
+    }
+    sh = sc->sh;
+    if ((error = tu_ssv6xxx_hci_register(&sh->hci)) != 0)
+        goto err_sh;;
+    if ((error = ssv6xxx_read_hw_info(sc)) != 0) {
+        goto err_hci;
+    }
+    if (sh->cfg.hw_caps == 0) {
+        error = -1;
+        goto err_hci;
+    }
+    if ((error = tu_ssv6xxx_init_softc(sc)) != 0) {
+        goto err_softc;
+    }
+    ssv6xxx_set_80211_hw_capab(sc);
+    if ((error = tu_ssv6xxx_init_hw(sc->sh)) != 0) {
+        goto err_hw;
+    }
+#ifndef CONFIG_SSV6XXX_HW_DEBUG
+    if ((error = ieee80211_register_hw(hw)) != 0) {
+        dev_dbg(sh->sc->dev, KERN_ERR "Failed to register w. %d.", error);
+        goto err_hw;
+    }
+#endif
+#ifndef CONFIG_SSV6XXX_HW_DEBUG
+    ssv_init_cli(dev_name(&hw->wiphy->dev), &sc->cmd_data);
+#else
+    ssv_init_cli(dev_name(sc->dev), &sc->cmd_data);
+#endif
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+    tu_ssv6xxx_init_debugfs(sc, name);
+#endif
+#ifdef CONFIG_SSV_SMARTLINK
+    {
+        extern int ksmartlink_init(void);
+        (void)ksmartlink_init();
+    }
+#endif
+    sc->sc_flags |= SC_OP_DEV_READY;
+    return 0;
+err_hw:
+    ssv6xxx_deinit_hw(sc);
+err_softc:
+    ssv6xxx_deinit_softc(sc);
+err_hci:
+    tu_ssv6xxx_hci_deregister(&sh->hci);
+err_sh:
+    ssv6xxx_deinit_hwsh(sc);
+err:
+    return error;
+}
+int ssv6xxx_rate_control_register(void)
+{
+    int ret = 0;
+#if (!defined(SSV_SUPPORT_HAL)||defined(SSV_SUPPORT_SSV6051))
+    ret = ssv6xxx_pid_rate_control_register();
+    if (ret)
+        return ret;
+#endif
+    ret = ssv6xxx_minstrel_rate_control_register();
+    if (ret)
+        goto err_ssv_minstrel;
+    return 0;
+err_ssv_minstrel:
+#if (!defined(SSV_SUPPORT_HAL)||defined(SSV_SUPPORT_SSV6051))
+    ssv6xxx_pid_rate_control_unregister();
+#endif
+    return ret;
+}
+void ssv6xxx_rate_control_unregister(void)
+{
+#if (!defined(SSV_SUPPORT_HAL)||defined(SSV_SUPPORT_SSV6051))
+    ssv6xxx_pid_rate_control_unregister();
+#endif
+    ssv6xxx_minstrel_rate_control_unregister();
+}
+static void ssv6xxx_deinit_device(struct ssv_softc *sc)
+{
+    dev_dbg(sc->dev, "%s(): ", __FUNCTION__);
+    sc->sc_flags &= ~SC_OP_DEV_READY;
+#ifdef CONFIG_SSV_SMARTLINK
+    {
+        extern void ksmartlink_exit(void);
+        ksmartlink_exit();
+    }
+#endif
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+    ssv6xxx_deinit_debugfs(sc);
+#endif
+#ifndef CONFIG_SSV6XXX_HW_DEBUG
+    ssv_deinit_cli(dev_name(&sc->hw->wiphy->dev), &sc->cmd_data);
+#else
+    ssv_deinit_cli(dev_name(sc->dev), &sc->cmd_data);
+#endif
+    SSV_SET_RF_DISABLE(sc->sh);
+#ifndef CONFIG_SSV6XXX_HW_DEBUG
+    ieee80211_unregister_hw(sc->hw);
+#endif
+    ssv6xxx_deinit_hw(sc);
+    ssv6xxx_deinit_softc(sc);
+    tu_ssv6xxx_hci_deregister(&sc->sh->hci);
+    ssv6xxx_deinit_hwsh(sc);
+}
+extern struct ieee80211_ops ssv6200_ops;
+int tu_ssv6xxx_dev_probe(struct platform_device *pdev)
+{
+    struct ssv_softc *sc;
+    struct ieee80211_hw *hw;
+    int ret;
+    if (!pdev->dev.platform_data) {
+        dev_err(&pdev->dev, "no platform data specified!");
+        return -EINVAL;
+    }
+    dev_dbg(&pdev->dev, "%s(): SSV6X5X device \"%s\" found !", __FUNCTION__, pdev->name);
+#ifdef SSV_MAC80211
+    hw = ieee80211_alloc_hw_nm(sizeof(struct ssv_softc), &ssv6200_ops,"icomm");
+#else
+    hw = ieee80211_alloc_hw(sizeof(struct ssv_softc), &ssv6200_ops);
+#endif
+    if (hw == NULL) {
+        dev_err(&pdev->dev, "No memory for ieee80211_hw");
+        return -ENOMEM;
+    }
+    SET_IEEE80211_DEV(hw, &pdev->dev);
+    dev_set_drvdata(&pdev->dev, hw);
+    memset((void *)hw->priv, 0, sizeof(struct ssv_softc));
+    sc = hw->priv;
+    sc->hw = hw;
+    sc->dev = &pdev->dev;
+    sc->platform_dev = pdev;
+    ret = tu_ssv6xxx_init_device(sc, pdev->name);
+    if (ret) {
+        dev_err(&pdev->dev, "Failed to initialize device");
+        ieee80211_free_hw(hw);
+        return ret;
+    }
+    wiphy_info(hw->wiphy, "%s", "SSV6X5X of iComm-semi");
+    return 0;
+}
+EXPORT_SYMBOL(tu_ssv6xxx_dev_probe);
+static void ssv6xxx_stop_all_running_threads(struct ssv_softc *sc)
+{
+    if (sc->ssv_txtput.txtput_tsk) {
+        kthread_stop(sc->ssv_txtput.txtput_tsk);
+        sc->ssv_txtput.txtput_tsk = NULL;
+    }
+    cancel_work_sync(&sc->beacon_miss_work);
+    cancel_delayed_work_sync(&sc->bcast_tx_work);
+    sc->rc_report_sechedule = 0;
+    cancel_work_sync(&sc->rc_report_work);
+    cancel_work_sync(&sc->rx_stuck_work);
+    cancel_work_sync(&sc->mib_edca_work);
+    cancel_work_sync(&sc->tx_poll_work);
+#ifdef CONFIG_SSV_CCI_IMPROVEMENT
+    cancel_work_sync(&sc->cci_clean_work);
+    cancel_work_sync(&sc->cci_set_work);
+#endif
+    cancel_work_sync(&sc->set_txpwr_work);
+    cancel_work_sync(&sc->thermal_monitor_work);
+#ifdef MULTI_THREAD_ENCRYPT
+    if (SSV_NEED_SW_CIPHER(sc->sh)) {
+        unregister_cpu_notifier(&sc->cpu_nfb);
+        if (!list_empty(&sc->encrypt_task_head)) {
+            int counter = 0;
+            struct ssv_encrypt_task_list *qtask = NULL;
+            for (qtask = list_entry((&sc->encrypt_task_head)->next, typeof(*qtask), list);
+                 !list_empty(&sc->encrypt_task_head);
+                 qtask = list_entry((&sc->encrypt_task_head)->next, typeof(*qtask), list)) {
+                counter++;
+                dev_dbg(sc->dev, "Stopping encrypt task %d: ...", counter);
+                kthread_stop(qtask->encrypt_task);
+                dev_dbg(sc->dev, "encrypt task %d is stopped: ...", counter);
+            }
+        }
+    }
+#endif
+    if (sc->tx_task != NULL) {
+        dev_dbg(sc->dev, "Stopping TX task...");
+        kthread_stop(sc->tx_task);
+        sc->tx_task = NULL;
+        dev_dbg(sc->dev, "TX task is stopped.");
+    }
+    if (sc->rx_task != NULL) {
+        dev_dbg(sc->dev, "Stopping RX task...");
+        kthread_stop(sc->rx_task);
+        sc->rx_task = NULL;
+        dev_dbg(sc->dev, "RX task is stopped.");
+    }
+    if(sc->sh->hci.hci_ctrl->hci_tx_task != NULL) {
+        dev_dbg(sc->dev, "Stopping HCI TX task...");
+        kthread_stop(sc->sh->hci.hci_ctrl->hci_tx_task);
+        sc->sh->hci.hci_ctrl->hci_tx_task = NULL;
+        dev_dbg(sc->dev, "HCI TX task is stopped.");
+    }
+}
+int tu_ssv6xxx_dev_remove(struct platform_device *pdev)
+{
+    struct ieee80211_hw *hw=dev_get_drvdata(&pdev->dev);
+    struct ssv_softc *sc=hw->priv;
+    dev_dbg(sc->dev, "tu_ssv6xxx_dev_remove(): pdev=%p, hw=%p", pdev, hw);
+    ssv6xxx_stop_all_running_threads(sc);
+    ssv6xxx_deinit_device(sc);
+    dev_dbg(sc->dev, "ieee80211_free_hw(): ");
+    ieee80211_free_hw(hw);
+    dev_info(sc->dev, "ssv6200: Driver unloaded");
+    return 0;
+}
+EXPORT_SYMBOL(tu_ssv6xxx_dev_remove);
+static const struct platform_device_id ssv6xxx_id_table[] = {
+    {
+        .name = SSV6200A,
+        .driver_data = 0,
+    },
+    {
+        .name = RSV6200A,
+        .driver_data = 0,
+    },
+#ifdef SSV_SUPPORT_SSV6006
+    {
+        .name = SSV6006A,
+        .driver_data = 0,
+    },
+    {
+        .name = SSV6006C,
+        .driver_data = 0,
+    },
+    {
+        .name = SSV6006D,
+        .driver_data = 0,
+    },
+#endif
+    {},
+};
+MODULE_DEVICE_TABLE(platform, ssv6xxx_id_table);
+static struct platform_driver ssv6xxx_driver = {
+    .probe = tu_ssv6xxx_dev_probe,
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0)
+    .remove = __devexit_p(tu_ssv6xxx_dev_remove),
+#else
+    .remove = tu_ssv6xxx_dev_remove,
+#endif
+    .id_table = ssv6xxx_id_table,
+    .driver = {
+        .name = SSV_DRVER_NAME,
+        .owner = THIS_MODULE,
+    }
+};
+static int device_match_by_alias(struct device *dev, void *data)
+{
+    struct device_driver *driver = dev->driver;
+    struct _pattern {
+        char driver_name[32];
+        char device_name[32];
+    } *pattern;
+    pattern = (struct _pattern *)data;
+    if (!strcmp(driver->name, pattern->driver_name) && !strcmp(dev_name(dev), pattern->device_name))
+        return 1;
+    if (!strcmp(driver->name, pattern->driver_name) && !strcmp("", pattern->device_name))
+        return 1;
+    else {
+        dev_dbg(dev, "%s: driver[%s][%s], device[%s][%s]", __FUNCTION__, driver->name, pattern->driver_name,
+               dev_name(dev), pattern->device_name);
+        return 0;
+    }
+}
+struct ssv_softc *ssv6xxx_driver_attach(char *driver_name)
+{
+    struct device *dev;
+    struct ieee80211_hw *hw;
+    struct ssv_softc *sc;
+    struct _pattern {
+        char driver_name[32];
+        char device_name[32];
+    } pattern;
+    memset(&pattern, 0, sizeof(struct _pattern));
+    sprintf(pattern.driver_name, "%s", driver_name);
+    dev = driver_find_device(&ssv6xxx_driver.driver, NULL,
+                             (void *)&pattern, device_match_by_alias);
+    if (!dev) {
+        printk(KERN_ERR "Cannot find the driver[%s]", driver_name);
+        return NULL;
+    }
+    hw = dev_get_drvdata(dev);
+    sc = hw->priv;
+    return sc;
+}
+void ssv6xxx_umac_hci_start(char *driver_name, char *device_name)
+{
+    struct device *dev;
+    struct ieee80211_hw *hw;
+    struct ssv_softc *sc;
+    struct _pattern {
+        char driver_name[32];
+        char device_name[32];
+    } pattern;
+    sprintf(pattern.driver_name, "%s", driver_name);
+    sprintf(pattern.device_name, "%s", device_name);
+    dev = driver_find_device(&ssv6xxx_driver.driver, NULL,
+                             (void *)&pattern, device_match_by_alias);
+    if (!dev) {
+        printk(KERN_ERR "Cannot find the device[%s] driver[%s]", device_name, driver_name);
+        return;
+    }
+    hw = dev_get_drvdata(dev);
+    sc = hw->priv;
+    HCI_STOP(sc->sh);
+    HCI_START(sc->sh);
+}
+EXPORT_SYMBOL(ssv6xxx_umac_hci_start);
+void ssv6xxx_umac_test(char *driver_name, char *device_name, struct sk_buff *skb, int size)
+{
+    struct device *dev;
+    struct ieee80211_hw *hw;
+    struct ssv_softc *sc;
+    struct ssv_hw *sh;
+    struct ssv6xxx_platform_data *priv;
+    u32 ret;
+    struct _pattern {
+        char driver_name[32];
+        char device_name[32];
+    } pattern;
+    sprintf(pattern.driver_name, "%s", driver_name);
+    sprintf(pattern.device_name, "%s", device_name);
+    dev = driver_find_device(&ssv6xxx_driver.driver, NULL,
+                             (void *)&pattern, device_match_by_alias);
+    if (!dev) {
+        dev_dbg(sh->sc->dev, "Cannot find the device[%s] driver[%s]", device_name, driver_name);
+        return;
+    }
+    hw = dev_get_drvdata(dev);
+    sc = hw->priv;
+    sh = sc->sh;
+    priv = sh->priv;
+    ret = priv->ops->load_fw(dev,0x0,skb->data,size);
+}
+EXPORT_SYMBOL(ssv6xxx_umac_test);
+void ssv6xxx_umac_reg_read(char *driver_name, char *device_name, u32 addr, u32 *regval)
+{
+    int retval = 0;
+    struct device *dev;
+    struct ieee80211_hw *hw;
+    struct ssv_softc *sc;
+    struct _pattern {
+        char driver_name[32];
+        char device_name[32];
+    } pattern;
+    sprintf(pattern.driver_name, "%s", driver_name);
+    sprintf(pattern.device_name, "%s", device_name);
+    dev = driver_find_device(&ssv6xxx_driver.driver, NULL,
+                             (void *)&pattern, device_match_by_alias);
+    if (!dev) {
+        printk(KERN_ERR "Cannot find the device[%s] driver[%s]", device_name, driver_name);
+        return;
+    }
+    hw = dev_get_drvdata(dev);
+    sc = hw->priv;
+    retval = SMAC_REG_READ(sc->sh, addr, regval);
+    if (retval != 0)
+        dev_dbg(sc->dev, "Fail to read register");
+}
+EXPORT_SYMBOL(ssv6xxx_umac_reg_read);
+void ssv6xxx_umac_reg_write(char *driver_name, char *device_name, u32 addr, u32 value)
+{
+    int retval = 0;
+    struct device *dev;
+    struct ieee80211_hw *hw;
+    struct ssv_softc *sc;
+    struct _pattern {
+        char driver_name[32];
+        char device_name[32];
+    } pattern;
+    sprintf(pattern.driver_name, "%s", driver_name);
+    sprintf(pattern.device_name, "%s", device_name);
+    dev = driver_find_device(&ssv6xxx_driver.driver, NULL,
+                             (void *)&pattern, device_match_by_alias);
+    if (!dev) {
+        printk(KERN_ERR "Cannot find the device[%s] driver[%s]", device_name, driver_name);
+        return;
+    }
+    hw = dev_get_drvdata(dev);
+    sc = hw->priv;
+    retval = SMAC_REG_WRITE(sc->sh, addr, value);
+    if (retval != 0)
+        dev_dbg(sc->dev, "Fail to read register");
+}
+EXPORT_SYMBOL(ssv6xxx_umac_reg_write);
+void ssv6xxx_umac_tx_frame(char *driver_name, char *device_name, struct sk_buff *skb)
+{
+    struct device *dev;
+    struct ieee80211_hw *hw;
+    struct ssv_softc *sc;
+    struct _pattern {
+        char driver_name[32];
+        char device_name[32];
+    } pattern;
+    sprintf(pattern.driver_name, "%s", driver_name);
+    sprintf(pattern.device_name, "%s", device_name);
+    dev = driver_find_device(&ssv6xxx_driver.driver, NULL,
+                             (void *)&pattern, device_match_by_alias);
+    if (!dev) {
+        printk(KERN_ERR "Cannot find the device[%s] driver[%s]", device_name, driver_name);
+        return;
+    }
+    hw = dev_get_drvdata(dev);
+    sc = hw->priv;
+    HCI_SEND_CMD(sc->sh, skb);
+}
+EXPORT_SYMBOL(ssv6xxx_umac_tx_frame);
+int ssv6xxx_umac_attach(char *driver_name, char *device_name, struct ssv6xxx_umac_ops *umac_ops)
+{
+    struct device *dev;
+    struct ieee80211_hw *hw;
+    struct ssv_softc *sc;
+    struct _pattern {
+        char driver_name[32];
+        char device_name[32];
+    } pattern;
+    sprintf(pattern.driver_name, "%s", driver_name);
+    sprintf(pattern.device_name, "%s", device_name);
+    dev = driver_find_device(&ssv6xxx_driver.driver, NULL,
+                             (void *)&pattern, device_match_by_alias);
+    if (!dev) {
+        printk(KERN_ERR "Cannot find the device[%s] driver[%s]", device_name, driver_name);
+        return -1;
+    }
+    hw = dev_get_drvdata(dev);
+    sc = hw->priv;
+    sc->umac = umac_ops;
+    return 0;
+}
+EXPORT_SYMBOL(ssv6xxx_umac_attach);
+int ssv6xxx_umac_deattach(char *driver_name, char *device_name)
+{
+    struct device *dev;
+    struct ieee80211_hw *hw;
+    struct ssv_softc *sc;
+    struct _pattern {
+        char driver_name[32];
+        char device_name[32];
+    } pattern;
+    sprintf(pattern.driver_name, "%s", driver_name);
+    sprintf(pattern.device_name, "%s", device_name);
+    dev = driver_find_device(&ssv6xxx_driver.driver, NULL,
+                             (void *)&pattern, device_match_by_alias);
+    if (!dev) {
+        printk(KERN_ERR "Cannot find the device[%s] driver[%s]", device_name, driver_name);
+        return -1;
+    }
+    hw = dev_get_drvdata(dev);
+    sc = hw->priv;
+    sc->umac = NULL;
+    return 0;
+}
+EXPORT_SYMBOL(ssv6xxx_umac_deattach);
+#if (defined(CONFIG_SSV_SUPPORT_ANDROID)||defined(CONFIG_SSV_BUILD_AS_ONE_KO))
+int tu_ssv6xxx_init(void)
+#else
+static int __init tu_ssv6xxx_init(void)
+#endif
+{
+    int ret = 0;
+#ifndef SSV_SUPPORT_HAL
+    extern void *ssv_dbg_phy_table;
+    extern u32 ssv_dbg_phy_len;
+    extern void *ssv_dbg_rf_table;
+    extern u32 ssv_dbg_rf_len;
+    ssv_dbg_phy_table = (void *)ssv6200_phy_tbl;
+    ssv_dbg_phy_len = sizeof(ssv6200_phy_tbl)/sizeof(ssv_cabrio_reg);
+    ssv_dbg_rf_table = (void *)ssv6200_rf_tbl;
+    ssv_dbg_rf_len = sizeof(ssv6200_rf_tbl)/sizeof(ssv_cabrio_reg);
+#endif
+    ret = ssv6xxx_rate_control_register();
+    if (ret != 0) {
+        printk(KERN_ERR "%s(): Failed to register rc algorithm.", __FUNCTION__);
+        return ret;
+    }
+    return platform_driver_register(&ssv6xxx_driver);
+}
+#if (defined(CONFIG_SSV_SUPPORT_ANDROID)||defined(CONFIG_SSV_BUILD_AS_ONE_KO))
+void tu_ssv6xxx_exit(void)
+#else
+static void __exit tu_ssv6xxx_exit(void)
+#endif
+{
+    ssv6xxx_rate_control_unregister();
+    platform_driver_unregister(&ssv6xxx_driver);
+}
+#if (defined(CONFIG_SSV_SUPPORT_ANDROID)||defined(CONFIG_SSV_BUILD_AS_ONE_KO))
+EXPORT_SYMBOL(tu_ssv6xxx_init);
+EXPORT_SYMBOL(tu_ssv6xxx_exit);
+#else
+module_init(tu_ssv6xxx_init);
+module_exit(tu_ssv6xxx_exit);
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smac/init.h b/drivers/net/wireless/ssv6x5x/smac/init.h
new file mode 100644
index 000000000..673e164bc
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/init.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _INIT_H_
+#define _INIT_H_
+int tu_ssv6xxx_init_mac(struct ssv_hw *sh);
+void ssv6xxx_deinit_mac(struct ssv_softc *sc);
+void ssv6xxx_restart_hw(struct work_struct *work);
+void ssv6xxx_umac_hci_start(char *driver_name, char *device_name);
+void ssv6xxx_umac_test(char *driver_name, char *device_name, struct sk_buff *skb, int size);
+void ssv6xxx_umac_reg_read(char *driver_name, char *device_name, u32 addr, u32 *regval);
+void ssv6xxx_umac_reg_write(char *driver_name, char *device_name, u32 addr, u32 value);
+void ssv6xxx_umac_tx_frame(char *driver_name, char *device_name, struct sk_buff *skb);
+int ssv6xxx_umac_attach(char *driver_name, char *device_name, struct ssv6xxx_umac_ops *umac_ops);
+int ssv6xxx_umac_deattach(char *driver_name, char *device_name);
+#if defined(CONFIG_SMARTLINK) || defined(CONFIG_SSV_SUPPORT_ANDROID)
+struct ssv_softc *ssv6xxx_driver_attach(char *driver_name);
+#endif
+#ifdef SSV_SUPPORT_HAL
+#define SSV_NEED_SW_CIPHER(_sh) HAL_NEED_SW_CIPHER(_sh)
+#define SSV_DO_IQ_CALIB(_sh,_pcfg) HAL_DO_IQ_CAL(_sh,_pcfg)
+#define SSV_SET_RF_ENABLE(_sc) HAL_SET_RF_ENABLE(_sc, true)
+#define SSV_SET_RF_DISABLE(_sc) HAL_SET_RF_ENABLE(_sc, false)
+#define SSV_SET_ON3_ENABLE(_sh, _val) HAL_SET_ON3_ENABLE(_sh, _val)
+#define SSV_GET_FW_NAME(_sh, _name) HAL_GET_FW_NAME(_sh, _name)
+#define SSV_FLASH_READ_ALL_MAP(_sh) HAL_FLASH_READ_ALL_MAP(_sh)
+#else
+void ssv6xxx_flash_read_all_map(struct ssv_hw *sh);
+#define SSV_NEED_SW_CIPHER(_sh) true
+#ifdef CONFIG_SSV_CABRIO_E
+int ssv6xxx_do_iq_calib(struct ssv_hw *sh, struct ssv6xxx_iqk_cfg *p_cfg);
+#define SSV_DO_IQ_CALIB(_sh,_pcfg) ssv6xxx_do_iq_calib(_sh,_pcfg)
+#else
+#define SSV_DO_IQ_CALIB(_sh,_pcfg)
+#endif
+#define SSV_SET_RF_ENABLE(_sc) ssv6xxx_rf_enable(_sc)
+#define SSV_SET_RF_DISABLE(_sc) ssv6xxx_rf_disable(_sc)
+#define SSV_SET_ON3_ENABLE(_sh, _val) ssv6xxx_set_on3_enable(_sh, _val)
+#define SSV_GET_FW_NAME(_sc, _name) strcpy(_name, "ssv6051-sw.bin")
+#define SSV_FLASH_READ_ALL_MAP(_sh) ssv6xxx_flash_read_all_map(_sh)
+#endif
+#if (defined(CONFIG_SSV_SUPPORT_ANDROID)||defined(CONFIG_SSV_BUILD_AS_ONE_KO))
+int tu_ssv6xxx_init(void);
+void tu_ssv6xxx_exit(void);
+#endif
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smac/ksmartlink.c b/drivers/net/wireless/ssv6x5x/smac/ksmartlink.c
new file mode 100644
index 000000000..b9b1fd2c9
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/ksmartlink.c
@@ -0,0 +1,507 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <net/genetlink.h>
+#include <linux/init.h>
+#include <net/sock.h>
+#include <linux/socket.h>
+#include <linux/net.h>
+#include <asm/types.h>
+#include <linux/netlink.h>
+#include <linux/skbuff.h>
+#include <linux/version.h>
+#include <ssv6200.h>
+#include "../smac/lib.h"
+#include "../smac/dev.h"
+#include "kssvsmart.h"
+#include <hal.h>
+#include "dev.h"
+#include "init.h"
+#ifdef CONFIG_SMARTLINK
+#define GLOBAL_NL_ID 999
+enum {
+    KSMARTLINK_ATTR_UNSPEC,
+    KSMARTLINK_ATTR_ENABLE,
+    KSMARTLINK_ATTR_SUCCESS,
+    KSMARTLINK_ATTR_CHANNEL,
+    KSMARTLINK_ATTR_PROMISC,
+    KSMARTLINK_ATTR_RXFRAME,
+    KSMARTLINK_ATTR_SI_CMD,
+    KSMARTLINK_ATTR_SI_STATUS,
+    KSMARTLINK_ATTR_SI_SSID,
+    KSMARTLINK_ATTR_SI_PASS,
+    __KSMARTLINK_ATTR_MAX,
+};
+#define KSMARTLINK_ATTR_MAX (__KSMARTLINK_ATTR_MAX - 1)
+static struct nla_policy ksmartlink_genl_policy[KSMARTLINK_ATTR_MAX + 1] = {
+    [KSMARTLINK_ATTR_ENABLE] = { .type = NLA_U32 },
+    [KSMARTLINK_ATTR_SUCCESS] = { .type = NLA_U32 },
+    [KSMARTLINK_ATTR_CHANNEL] = { .type = NLA_U32 },
+    [KSMARTLINK_ATTR_PROMISC] = { .type = NLA_U32 },
+    [KSMARTLINK_ATTR_RXFRAME] = { .type = NLA_BINARY, .len = IEEE80211_MAX_DATA_LEN },
+    [KSMARTLINK_ATTR_SI_CMD] = { .type = NLA_U32 },
+    [KSMARTLINK_ATTR_SI_STATUS] = { .type = NLA_STRING },
+    [KSMARTLINK_ATTR_SI_SSID] = { .type = NLA_STRING },
+    [KSMARTLINK_ATTR_SI_PASS] = { .type = NLA_STRING },
+};
+static struct genl_family ksmartlink_gnl_family = {
+    .id = GLOBAL_NL_ID,
+    .hdrsize = 0,
+    .name = "KSMARTLINK",
+    .version = 1,
+    .maxattr = KSMARTLINK_ATTR_MAX,
+};
+enum {
+    KSMARTLINK_CMD_UNSPEC,
+    KSMARTLINK_CMD_SMARTLINK,
+    KSMARTLINK_CMD_SET_CHANNEL,
+    KSMARTLINK_CMD_GET_CHANNEL,
+    KSMARTLINK_CMD_SET_PROMISC,
+    KSMARTLINK_CMD_GET_PROMISC,
+    KSMARTLINK_CMD_RX_FRAME,
+    KSMARTLINK_CMD_SMARTICOMM,
+    KSMARTLINK_CMD_SET_SI_CMD,
+    KSMARTLINK_CMD_GET_SI_STATUS,
+    KSMARTLINK_CMD_GET_SI_SSID,
+    KSMARTLINK_CMD_GET_SI_PASS,
+    __KSMARTLINK_CMD_MAX,
+};
+#define KSMARTLINK_CMD_MAX (__KSMARTLINK_CMD_MAX - 1)
+int ksmartlink_cmd_smartlink(struct sk_buff *skb, struct genl_info *info)
+{
+    u32 enable;
+    struct ssv_softc *ssv_smartlink_sc = ssv6xxx_driver_attach(SSV_DRVER_NAME);
+    if (info == NULL)
+        return -EINVAL;
+    if (!info->attrs[KSMARTLINK_ATTR_ENABLE]) {
+        printk("the attrs is not enable\n");
+        return -EINVAL;
+    } else {
+        enable = nla_get_u32(info->attrs[KSMARTLINK_ATTR_ENABLE]);
+#ifdef SSV_SMARTLINK_DEBUG
+        printk("ksmartlink_cmd_smartlink enable=%d\n", enable);
+#endif
+    }
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,7,0)
+    ssv_smartlink_sc->ssv_usr_pid = info->snd_portid;
+#else
+    ssv_smartlink_sc->ssv_usr_pid = info->snd_pid;
+#endif
+    ssv_smartlink_sc->ssv_smartlink_status = enable;
+    return 0;
+}
+static int ksmartlink_set_channel(struct sk_buff *skb, struct genl_info *info)
+{
+    int retval;
+    u32 channel;
+    struct ssv_softc *ssv_smartlink_sc = ssv6xxx_driver_attach(SSV_DRVER_NAME);
+    struct ieee80211_channel chan;
+    if (info == NULL)
+        return -EINVAL;
+    if (!info->attrs[KSMARTLINK_ATTR_CHANNEL])
+        return -EINVAL;
+    else {
+        channel = nla_get_u32(info->attrs[KSMARTLINK_ATTR_CHANNEL]);
+#ifdef SSV_SMARTLINK_DEBUG
+        printk("ksmartlink_set_channel channel=%d\n", channel);
+#endif
+    }
+    memset(&chan, 0, sizeof( struct ieee80211_channel));
+    chan.hw_value = channel;
+    mutex_lock(&ssv_smartlink_sc->mutex);
+    retval = HAL_SET_CHANNEL(ssv_smartlink_sc, &chan, NL80211_CHAN_HT20);
+    ssv_smartlink_sc->hw_chan = chan.hw_value;
+    ssv_smartlink_sc->hw_chan_type = NL80211_CHAN_HT20;
+    mutex_unlock(&ssv_smartlink_sc->mutex);
+    return retval;
+}
+static int ksmartlink_get_channel(struct sk_buff *skb, struct genl_info *info)
+{
+    struct sk_buff *msg;
+    int retval;
+    void *hdr;
+    u32 channel = 0x00;
+    struct ssv_softc *ssv_smartlink_sc = ssv6xxx_driver_attach(SSV_DRVER_NAME);
+    if (info == NULL)
+        return -EINVAL;
+    mutex_lock(&ssv_smartlink_sc->mutex);
+    retval = ssv6xxx_get_channel(ssv_smartlink_sc, &channel);
+    mutex_unlock(&ssv_smartlink_sc->mutex);
+    msg = genlmsg_new(NLMSG_DEFAULT_SIZE, GFP_KERNEL);
+    if (!msg)
+        return -ENOMEM;
+#ifdef SSV_SMARTLINK_DEBUG
+    printk("ksmartlink_get_channel\n");
+#endif
+    hdr = genlmsg_put(msg, 0, info->snd_seq, &ksmartlink_gnl_family, 0, KSMARTLINK_CMD_GET_CHANNEL);
+    if (!hdr) {
+        retval = -ENOBUFS;
+        goto free_msg;
+    }
+    retval = nla_put_u32(msg, KSMARTLINK_ATTR_CHANNEL, channel);
+    if (retval) {
+        printk("Fail to add attribute in message\n");
+        goto free_msg;
+    }
+    genlmsg_end(msg, hdr);
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,7,0)
+    return genlmsg_unicast(genl_info_net(info), msg, info->snd_portid);
+#else
+    return genlmsg_unicast(genl_info_net(info), msg, info->snd_pid);
+#endif
+free_msg:
+    nlmsg_free(msg);
+    return retval;
+}
+static int ksmartlink_set_promisc(struct sk_buff *skb, struct genl_info *info)
+{
+    int retval;
+    u32 promisc;
+    struct ssv_softc *ssv_smartlink_sc = ssv6xxx_driver_attach(SSV_DRVER_NAME);
+    if (info == NULL)
+        return -EINVAL;
+    if (!info->attrs[KSMARTLINK_ATTR_PROMISC])
+        return -EINVAL;
+    else {
+        promisc = nla_get_u32(info->attrs[KSMARTLINK_ATTR_PROMISC]);
+#ifdef SSV_SMARTLINK_DEBUG
+        printk("ksmartlink_set_promisc promisc=%d\n", promisc);
+#endif
+    }
+    mutex_lock(&ssv_smartlink_sc->mutex);
+    retval = ssv6xxx_set_promisc(ssv_smartlink_sc, promisc);
+    mutex_unlock(&ssv_smartlink_sc->mutex);
+    return retval;
+}
+static int ksmartlink_get_promisc(struct sk_buff *skb, struct genl_info *info)
+{
+    struct sk_buff *msg;
+    int retval;
+    void *hdr;
+    u32 promisc = 0x00;
+    struct ssv_softc *ssv_smartlink_sc = ssv6xxx_driver_attach(SSV_DRVER_NAME);
+    if (info == NULL)
+        return -EINVAL;
+    mutex_lock(&ssv_smartlink_sc->mutex);
+    retval = ssv6xxx_get_promisc(ssv_smartlink_sc, &promisc);
+    mutex_unlock(&ssv_smartlink_sc->mutex);
+    msg = genlmsg_new(NLMSG_DEFAULT_SIZE, GFP_KERNEL);
+    if (!msg)
+        return -ENOMEM;
+#ifdef SSV_SMARTLINK_DEBUG
+    printk("ksmartlink_get_promisc\n");
+#endif
+    hdr = genlmsg_put(msg, 0, info->snd_seq, &ksmartlink_gnl_family, 0, KSMARTLINK_CMD_GET_PROMISC);
+    if (!hdr) {
+        retval = -ENOBUFS;
+        goto free_msg;
+    }
+    retval = nla_put_u32(msg, KSMARTLINK_ATTR_PROMISC, promisc);
+    if (retval) {
+        printk("Fail to add attribute in message\n");
+        goto free_msg;
+    }
+    genlmsg_end(msg, hdr);
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,7,0)
+    return genlmsg_unicast(genl_info_net(info), msg, info->snd_portid);
+#else
+    return genlmsg_unicast(genl_info_net(info), msg, info->snd_pid);
+#endif
+free_msg:
+    nlmsg_free(msg);
+    return retval;
+}
+#ifdef CONFIG_SSV_SMARTLINK
+static int ksmartlink_start_smarticomm(struct sk_buff *skb, struct genl_info *info)
+{
+    u32 enable;
+    struct ssv_softc *ssv_smartlink_sc = ssv6xxx_driver_attach(SSV_DRVER_NAME);
+    if (info == NULL)
+        return -EINVAL;
+    if (!info->attrs[KSMARTLINK_ATTR_ENABLE])
+        return -EINVAL;
+    else {
+        enable = nla_get_u32(info->attrs[KSMARTLINK_ATTR_ENABLE]);
+#ifdef SSV_SMARTLINK_DEBUG
+        printk("ksmartlink_start_smarticomm enable=%d\n", enable);
+#endif
+    }
+    ssv_smartlink_sc->ssv_smartlink_status = enable;
+    return 0;
+}
+static int ksmartlink_set_si_cmd(struct sk_buff *skb, struct genl_info *info)
+{
+    u32 si_cmd;
+    if (info == NULL)
+        return -EINVAL;
+    if (!info->attrs[KSMARTLINK_ATTR_SI_CMD])
+        return -EINVAL;
+    else {
+        si_cmd = nla_get_u32(info->attrs[KSMARTLINK_ATTR_SI_CMD]);
+#ifdef SSV_SMARTLINK_DEBUG
+        printk("ksmartlink_set_si_cmd si_cmd=%d\n", si_cmd);
+#endif
+    }
+    ssv6xxx_send_si_cmd(si_cmd);
+    return 0;
+}
+static int ksmartlink_get_si_status(struct sk_buff *skb, struct genl_info *info)
+{
+    struct sk_buff *msg;
+    int retval;
+    void *hdr;
+    char status[128] = "";
+    if (info == NULL)
+        return -EINVAL;
+    get_si_status((char *)status);
+    msg = genlmsg_new(NLMSG_DEFAULT_SIZE, GFP_KERNEL);
+    if (!msg)
+        return -ENOMEM;
+#ifdef SSV_SMARTLINK_DEBUG
+    printk("ksmartlink_get_si_status\n");
+#endif
+    hdr = genlmsg_put(msg, 0, info->snd_seq, &ksmartlink_gnl_family, 0, KSMARTLINK_CMD_GET_SI_STATUS);
+    if (!hdr) {
+        retval = -ENOBUFS;
+        goto free_msg;
+    }
+    retval = nla_put_string(msg, KSMARTLINK_ATTR_SI_STATUS, status);
+    if (retval) {
+        printk("Fail to add attribute in message\n");
+        goto free_msg;
+    }
+    genlmsg_end(msg, hdr);
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,7,0)
+    return genlmsg_unicast(genl_info_net(info), msg, info->snd_portid);
+#else
+    return genlmsg_unicast(genl_info_net(info), msg, info->snd_pid);
+#endif
+free_msg:
+    nlmsg_free(msg);
+    return retval;
+}
+static int ksmartlink_get_si_ssid(struct sk_buff *skb, struct genl_info *info)
+{
+    struct sk_buff *msg;
+    int retval;
+    void *hdr;
+    char ssid[128] = "";
+    if (info == NULL)
+        return -EINVAL;
+    get_si_ssid((char *)ssid);
+    msg = genlmsg_new(NLMSG_DEFAULT_SIZE, GFP_KERNEL);
+    if (!msg)
+        return -ENOMEM;
+#ifdef SSV_SMARTLINK_DEBUG
+    printk("ksmartlink_get_si_ssid\n");
+#endif
+    hdr = genlmsg_put(msg, 0, info->snd_seq, &ksmartlink_gnl_family, 0, KSMARTLINK_CMD_GET_SI_SSID);
+    if (!hdr) {
+        retval = -ENOBUFS;
+        goto free_msg;
+    }
+    retval = nla_put_string(msg, KSMARTLINK_ATTR_SI_SSID, ssid);
+    if (retval) {
+        printk("Fail to add attribute in message\n");
+        goto free_msg;
+    }
+    genlmsg_end(msg, hdr);
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,7,0)
+    return genlmsg_unicast(genl_info_net(info), msg, info->snd_portid);
+#else
+    return genlmsg_unicast(genl_info_net(info), msg, info->snd_pid);
+#endif
+free_msg:
+    nlmsg_free(msg);
+    return retval;
+}
+static int ksmartlink_get_si_pass(struct sk_buff *skb, struct genl_info *info)
+{
+    struct sk_buff *msg;
+    int retval;
+    void *hdr;
+    char pass[128] = "";
+    if (info == NULL)
+        return -EINVAL;
+    get_si_pass((char *)pass);
+    msg = genlmsg_new(NLMSG_DEFAULT_SIZE, GFP_KERNEL);
+    if (!msg)
+        return -ENOMEM;
+#ifdef SSV_SMARTLINK_DEBUG
+    printk("ksmartlink_get_si_pass\n");
+#endif
+    hdr = genlmsg_put(msg, 0, info->snd_seq, &ksmartlink_gnl_family, 0, KSMARTLINK_CMD_GET_SI_PASS);
+    if (!hdr) {
+        retval = -ENOBUFS;
+        goto free_msg;
+    }
+    retval = nla_put_string(msg, KSMARTLINK_ATTR_SI_PASS, pass);
+    if (retval) {
+        printk("Fail to add attribute in message\n");
+        goto free_msg;
+    }
+    genlmsg_end(msg, hdr);
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,7,0)
+    return genlmsg_unicast(genl_info_net(info), msg, info->snd_portid);
+#else
+    return genlmsg_unicast(genl_info_net(info), msg, info->snd_pid);
+#endif
+free_msg:
+    nlmsg_free(msg);
+    return retval;
+}
+#endif
+int smartlink_nl_send_msg(struct sk_buff *skb_in)
+{
+    struct sk_buff *skb;
+    int retval;
+    void *msg_head;
+    unsigned char *pOutBuf=skb_in->data;
+    int inBufLen=skb_in->len;
+    struct ssv_softc *ssv_smartlink_sc = ssv6xxx_driver_attach(SSV_DRVER_NAME);
+    skb = genlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL);
+    if (skb == NULL)
+        return -ENOMEM;
+    msg_head = genlmsg_put(skb, 0, 0, &ksmartlink_gnl_family, 0, KSMARTLINK_CMD_RX_FRAME);
+    if (msg_head == NULL) {
+        retval = -ENOMEM;
+        printk("Fail to create the netlink message header\n");
+        goto free_msg;
+    }
+    retval = nla_put(skb, KSMARTLINK_ATTR_RXFRAME, inBufLen, pOutBuf);
+    if (retval != 0) {
+        printk("Fail to add attribute in message\n");
+        goto free_msg;
+    }
+    genlmsg_end(skb, msg_head);
+    return genlmsg_unicast(&init_net, skb, ssv_smartlink_sc->ssv_usr_pid);
+free_msg:
+    nlmsg_free(skb);
+    return retval;
+}
+EXPORT_SYMBOL(smartlink_nl_send_msg);
+struct genl_ops ksmartlink_gnl_ops[] = {
+    {
+        .cmd = KSMARTLINK_CMD_SMARTLINK,
+        .flags = 0,
+        .policy = ksmartlink_genl_policy,
+        .doit = ksmartlink_cmd_smartlink,
+        .dumpit = NULL,
+    },
+    {
+        .cmd = KSMARTLINK_CMD_SET_CHANNEL,
+        .flags = 0,
+        .policy = ksmartlink_genl_policy,
+        .doit = ksmartlink_set_channel,
+        .dumpit = NULL,
+    },
+    {
+        .cmd = KSMARTLINK_CMD_GET_CHANNEL,
+        .flags = 0,
+        .policy = ksmartlink_genl_policy,
+        .doit = ksmartlink_get_channel,
+        .dumpit = NULL,
+    },
+    {
+        .cmd = KSMARTLINK_CMD_SET_PROMISC,
+        .flags = 0,
+        .policy = ksmartlink_genl_policy,
+        .doit = ksmartlink_set_promisc,
+        .dumpit = NULL,
+    },
+    {
+        .cmd = KSMARTLINK_CMD_GET_PROMISC,
+        .flags = 0,
+        .policy = ksmartlink_genl_policy,
+        .doit = ksmartlink_get_promisc,
+        .dumpit = NULL,
+    },
+#ifdef CONFIG_SSV_SMARTLINK
+    {
+        .cmd = KSMARTLINK_CMD_SMARTICOMM,
+        .flags = 0,
+        .policy = ksmartlink_genl_policy,
+        .doit = ksmartlink_start_smarticomm,
+        .dumpit = NULL,
+    },
+    {
+        .cmd = KSMARTLINK_CMD_SET_SI_CMD,
+        .flags = 0,
+        .policy = ksmartlink_genl_policy,
+        .doit = ksmartlink_set_si_cmd,
+        .dumpit = NULL,
+    },
+    {
+        .cmd = KSMARTLINK_CMD_GET_SI_STATUS,
+        .flags = 0,
+        .policy = ksmartlink_genl_policy,
+        .doit = ksmartlink_get_si_status,
+        .dumpit = NULL,
+    },
+    {
+        .cmd = KSMARTLINK_CMD_GET_SI_SSID,
+        .flags = 0,
+        .policy = ksmartlink_genl_policy,
+        .doit = ksmartlink_get_si_ssid,
+        .dumpit = NULL,
+    },
+    {
+        .cmd = KSMARTLINK_CMD_GET_SI_PASS,
+        .flags = 0,
+        .policy = ksmartlink_genl_policy,
+        .doit = ksmartlink_get_si_pass,
+        .dumpit = NULL,
+    },
+#endif
+};
+int ksmartlink_init(void)
+{
+    int rc;
+    printk("INIT SSV KSMARTLINK GENERIC NETLINK MODULE\n");
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,13,0)
+    rc = genl_register_family_with_ops(&ksmartlink_gnl_family,
+                                       ksmartlink_gnl_ops);
+#else
+    rc = genl_register_family_with_ops(&ksmartlink_gnl_family,
+                                       ksmartlink_gnl_ops, ARRAY_SIZE(ksmartlink_gnl_ops));
+#endif
+    if (rc != 0) {
+        printk("Fail to insert SSV KSMARTLINK NETLINK MODULE\n");
+        return -1;
+    }
+    if(ssv6xxx_driver_attach(SSV_DRVER_NAME) == NULL) {
+        printk("Fail to attach WIFI friver\n");
+        return -1;
+    }
+    return 0;
+}
+int ksmartlink_exit(void)
+{
+    int ret;
+    printk("EXIT SSV KSMARTLINK GENERIC NETLINK MODULE\n");
+    ret = genl_unregister_family(&ksmartlink_gnl_family);
+    if(ret !=0) {
+        printk("unregister family %i\n",ret);
+    }
+    printk("EXIT SSV KSMARTLINK GENERIC NETLINK MODULE ... end\n");
+    return ret;
+}
+#if (defined(CONFIG_SSV_SUPPORT_ANDROID)||defined(CONFIG_SSV_BUILD_AS_ONE_KO))
+EXPORT_SYMBOL(ksmartlink_init);
+EXPORT_SYMBOL(ksmartlink_exit);
+#endif
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smac/kssvsmart.c b/drivers/net/wireless/ssv6x5x/smac/kssvsmart.c
new file mode 100644
index 000000000..cd4c75295
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/kssvsmart.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <ssv6200.h>
+#ifdef SSV_MAC80211
+#include "ssv_mac80211.h"
+#else
+#include <net/mac80211.h>
+#endif
+#include <linux/module.h>
+#include <smac/dev.h>
+#include "kssvsmart.h"
+#include "lib.h"
+#include "ssv_skb.h"
+#include "init.h"
+#ifdef CONFIG_SSV_SMARTLINK
+#define VALID_SSID_LEN(x) ((x) <= 32)
+#define VALID_PASS_LEN(x) ((x) == 0 || ((x) >= 8 && (x) <= 64))
+#define INVALID "invalid"
+#define NONE "none"
+struct ssv6xxx_si_cfg si_cfg;
+int si_st;
+char si_status_st[][16] = {
+    "NG",
+    "OK",
+    "PROCESSING",
+    "MAX"
+};
+inline void set_si_status(u32 st)
+{
+    si_st = st;
+}
+int get_si_status(char *input)
+{
+    strcpy(input,si_status_st[si_st]);
+    return strlen(si_status_st[si_st]);
+}
+int get_si_ssid(char *input)
+{
+    strcpy(input,si_cfg.ssid);
+    return strlen(si_cfg.ssid);
+}
+int get_si_pass(char *input)
+{
+    strcpy(input,si_cfg.password);
+    return strlen(si_cfg.password);
+}
+void ssv6xxx_process_si_event(struct ssv_softc *sc, struct sk_buff *skb)
+{
+    struct cfg_host_event *host_event;
+    struct ssv6xxx_si_cfg *p_si_cfg;
+    printk("received SOC_EVT_SMART_ICOMM event\n");
+    host_event = (struct cfg_host_event *)skb->data;
+    p_si_cfg = (struct ssv6xxx_si_cfg *)&host_event->dat[0];
+    if (VALID_SSID_LEN(p_si_cfg->ssid_len) && VALID_PASS_LEN(p_si_cfg->password_len)) {
+        memcpy(&si_cfg.ssid, p_si_cfg->ssid, p_si_cfg->ssid_len);
+        if (p_si_cfg->password_len != 0)
+            memcpy(&si_cfg.password, p_si_cfg->password, p_si_cfg->password_len);
+        else
+            memcpy(&si_cfg.password, NONE, sizeof(NONE));
+        si_cfg.ssid_len = p_si_cfg->ssid_len;
+        si_cfg.password_len = p_si_cfg->password_len;
+        set_si_status(SI_ST_OK);
+        printk("SSID: %s, LEN: %d\n", si_cfg.ssid, si_cfg.ssid_len);
+        printk("PASS: %s, LEN: %d\n", si_cfg.password, si_cfg.password_len);
+    } else {
+        printk("!!! Oops, got invalid value of ssid_len:%d or password_len:%d !!!\n",
+               p_si_cfg->ssid_len, p_si_cfg->password_len);
+        set_si_status(SI_ST_NG);
+        memcpy(&si_cfg.ssid, INVALID, sizeof(INVALID));
+        memcpy(&si_cfg.password, INVALID, sizeof(INVALID));
+    }
+}
+EXPORT_SYMBOL(ssv6xxx_process_si_event);
+int ssv6xxx_send_si_cmd(u32 smart_icomm_cmd)
+{
+    struct sk_buff *skb;
+    struct cfg_host_cmd *host_cmd;
+    u32 total_ch_cfg_size, i;
+    struct ssv6xxx_ch_cfg ch;
+    int ret;
+    struct ssv_softc *ssv_dbg_sc;
+    struct ssv_hw *sh;
+    ssv_dbg_sc = ssv6xxx_driver_attach(SSV_DRVER_NAME);
+    if(ssv_dbg_sc == NULL) {
+        printk("Get ssv_dbg_sc fail!!!\n");
+        return -1;
+    }
+    sh = ssv_dbg_sc->sh;
+    if (smart_icomm_cmd == START_SMART_ICOMM || smart_icomm_cmd == RESET_SMART_ICOMM)
+        set_si_status(SI_ST_PROCESSING);
+    else
+        set_si_status(SI_ST_OK);
+    memset(&si_cfg, 0, sizeof(si_cfg));
+    total_ch_cfg_size = sh->ch_cfg_size * sizeof(struct ssv6xxx_ch_cfg);
+    skb = ssv_skb_alloc(sh->sc, HOST_CMD_HDR_LEN + sizeof(u32) + sizeof(u32) + total_ch_cfg_size);
+    if(skb == NULL) {
+        printk("ssv command ssvdevice_skb_alloc fail!!!\n");
+        set_si_status(SI_ST_NG);
+        return -1;
+    }
+    skb->data_len = HOST_CMD_HDR_LEN + sizeof(u32) + sizeof(u32) + total_ch_cfg_size;
+    skb->len = skb->data_len;
+    host_cmd = (struct cfg_host_cmd *)skb->data;
+    host_cmd->c_type = HOST_CMD;
+    host_cmd->h_cmd = (u8)SSV6XXX_HOST_CMD_SMART_ICOMM;
+    host_cmd->len = skb->data_len;
+    printk("smart icomm, cmd: %d, ch_cfg_size : %d\n", smart_icomm_cmd, sh->ch_cfg_size);
+    memcpy(host_cmd->dat8, &smart_icomm_cmd, sizeof(u32));
+    memcpy(host_cmd->dat8 + sizeof(u32), &sh->ch_cfg_size, sizeof(u32));
+    memcpy(host_cmd->dat8 + sizeof(s32) + sizeof(s32), sh->p_ch_cfg, total_ch_cfg_size);
+    for (i = 0; i < sh->ch_cfg_size; i++) {
+        memcpy(&ch, host_cmd->dat8+sizeof(u32) + sizeof(u32) + (i * sizeof(struct ssv6xxx_ch_cfg)), sizeof(struct ssv6xxx_ch_cfg));
+        printk("reg: 0x%08x, ch1: 0x%08x, ch13: 0x%08x\n", ch.reg_addr, ch.ch1_12_value, ch.ch13_14_value);
+    }
+    ret = HCI_SEND_CMD(sh, skb);
+    ssv_skb_free(sh->sc, skb);
+    return ret;
+}
+EXPORT_SYMBOL(ssv6xxx_send_si_cmd);
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smac/kssvsmart.h b/drivers/net/wireless/ssv6x5x/smac/kssvsmart.h
new file mode 100644
index 000000000..ecc860e90
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/kssvsmart.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSVSMART_CONFIG_H
+#define _SSVSMART_CONFIG_H
+#ifdef SSV_MAC80211
+#include "ssv_mac80211.h"
+#else
+#include <net/mac80211.h>
+#endif
+#include <ssv6200.h>
+#include <smac/dev.h>
+#ifdef CONFIG_SSV_SMARTLINK
+enum {
+    SI_ST_NG,
+    SI_ST_OK,
+    SI_ST_PROCESSING,
+    SI_ST_MAX
+};
+void ssv6xxx_process_si_event(struct ssv_softc *sc, struct sk_buff *skb);
+int ssv6xxx_send_si_cmd(u32 smart_icomm_cmd);
+inline void set_si_status(u32 st);
+int get_si_status(char *input);
+int get_si_ssid(char *input);
+int get_si_pass(char *input);
+#endif
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smac/lib.c b/drivers/net/wireless/ssv6x5x/smac/lib.c
new file mode 100644
index 000000000..1b783246e
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/lib.c
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/version.h>
+#include <ssv6200.h>
+#include "lib.h"
diff --git a/drivers/net/wireless/ssv6x5x/smac/lib.h b/drivers/net/wireless/ssv6x5x/smac/lib.h
new file mode 100644
index 000000000..d7f5d1cdc
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/lib.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _LIB_H_
+#define _LIB_H_
+#include <linux/skbuff.h>
+#include <linux/netdevice.h>
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smac/linux_2_6_35.h b/drivers/net/wireless/ssv6x5x/smac/linux_2_6_35.h
new file mode 100644
index 000000000..0b3713728
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/linux_2_6_35.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _LINUX_2_6_35_H_
+#define _LINUX_2_6_35_H_
+#ifdef SSV_MAC80211
+#include "ssv_mac80211.h"
+#else
+#include <net/mac80211.h>
+#endif
+enum ieee80211_ac_numbers {
+    IEEE80211_AC_VO = 0,
+    IEEE80211_AC_VI = 1,
+    IEEE80211_AC_BE = 2,
+    IEEE80211_AC_BK = 3,
+};
+#define IEEE80211_NUM_ACS 4
+#define wiphy_info(wiphy,format,args...) \
+ dev_info(&(wiphy)->dev, format, ##args)
+#define IEEE80211_CONF_OFFCHANNEL (1<<30)
+#define FIF_PROBE_REQ (1<<8)
+#define BSS_CHANGED_SSID (1<<15)
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smac/linux_3_0_0.h b/drivers/net/wireless/ssv6x5x/smac/linux_3_0_0.h
new file mode 100644
index 000000000..ce3073e6a
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/linux_3_0_0.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _LINUX_3_0_0_H_
+#define _LINUX_3_0_0_H_
+#define BSS_CHANGED_SSID (1<<15)
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smac/p2p.c b/drivers/net/wireless/ssv6x5x/smac/p2p.c
new file mode 100644
index 000000000..de2d4052a
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/p2p.c
@@ -0,0 +1,310 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/version.h>
+#include <ssv6200.h>
+#include <linux/types.h>
+#include <linux/nl80211.h>
+#ifdef SSV_MAC80211
+#include "ssv_mac80211.h"
+#else
+#include <net/mac80211.h>
+#endif
+#include <linux/nl80211.h>
+#include <linux/etherdevice.h>
+#include <linux/delay.h>
+#include <linux/version.h>
+#include <linux/time.h>
+#include <linux/kthread.h>
+#include <ssv6200.h>
+#include "p2p.h"
+#include "dev.h"
+#include "lib.h"
+#ifdef CONFIG_P2P_NOA
+#define P2P_IE_VENDOR_TYPE 0x506f9a09
+#define P2P_NOA_DETECT_INTERVAL (5 * HZ)
+#ifndef MAC2STR
+#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5]
+#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x"
+#define COMPACT_MACSTR "%02x%02x%02x%02x%02x%02x"
+#endif
+void ssv6xxx_send_noa_cmd(struct ssv_softc *sc, struct ssv6xxx_p2p_noa_param *p2p_noa_param);
+static inline u32 WPA_GET_BE32(const u8 *a)
+{
+    return (a[0] << 24) | (a[1] << 16) | (a[2] << 8) | a[3];
+}
+static inline u16 WPA_GET_LE16(const u8 *a)
+{
+    return (a[1] << 8) | a[0];
+}
+static inline u32 WPA_GET_LE32(const u8 *a)
+{
+    return (a[3] << 24) |(a[2] << 16) |(a[1] << 8) | a[0];
+}
+#define IEEE80211_HDRLEN 24
+enum p2p_attr_id {
+    P2P_ATTR_STATUS = 0,
+    P2P_ATTR_MINOR_REASON_CODE = 1,
+    P2P_ATTR_CAPABILITY = 2,
+    P2P_ATTR_DEVICE_ID = 3,
+    P2P_ATTR_GROUP_OWNER_INTENT = 4,
+    P2P_ATTR_CONFIGURATION_TIMEOUT = 5,
+    P2P_ATTR_LISTEN_CHANNEL = 6,
+    P2P_ATTR_GROUP_BSSID = 7,
+    P2P_ATTR_EXT_LISTEN_TIMING = 8,
+    P2P_ATTR_INTENDED_INTERFACE_ADDR = 9,
+    P2P_ATTR_MANAGEABILITY = 10,
+    P2P_ATTR_CHANNEL_LIST = 11,
+    P2P_ATTR_NOTICE_OF_ABSENCE = 12,
+    P2P_ATTR_DEVICE_INFO = 13,
+    P2P_ATTR_GROUP_INFO = 14,
+    P2P_ATTR_GROUP_ID = 15,
+    P2P_ATTR_INTERFACE = 16,
+    P2P_ATTR_OPERATING_CHANNEL = 17,
+    P2P_ATTR_INVITATION_FLAGS = 18,
+    P2P_ATTR_OOB_GO_NEG_CHANNEL = 19,
+    P2P_ATTR_VENDOR_SPECIFIC = 221
+};
+struct ssv6xxx_p2p_noa_attribute {
+    u8 index;
+    u16 ctwindows_oppps;
+    struct ssv6xxx_p2p_noa_param noa_param;
+};
+bool p2p_find_noa(const u8 *ies, struct ssv6xxx_p2p_noa_attribute *noa_attr)
+{
+    const u8 *end, *pos, *ie;
+    u32 len;
+    len = ie[1] - 4;
+    pos = ie + 6;
+    end = pos+len;
+    while (pos < end) {
+        u16 attr_len;
+        if (pos + 2 >= end) {
+            return false;
+        }
+        attr_len = WPA_GET_LE16(pos + 1);
+        if (pos + 3 + attr_len > end) {
+            return false;
+        }
+        if(pos[0] != P2P_ATTR_NOTICE_OF_ABSENCE) {
+            pos += 3 + attr_len;
+            continue;
+        }
+        if(attr_len<15) {
+            printk("*********************NOA descriptor does not exist len[%d]\n", attr_len);
+            break;
+        }
+        if(attr_len>15)
+            printk("More than one NOA descriptor\n");
+        noa_attr->index = pos[3];
+        noa_attr->ctwindows_oppps = pos[4];
+        noa_attr->noa_param.count = pos[5];
+        noa_attr->noa_param.duration = WPA_GET_LE32(&pos[6]);
+        noa_attr->noa_param.interval = WPA_GET_LE32(&pos[10]);
+        noa_attr->noa_param.start_time = WPA_GET_LE32(&pos[14]);
+        return true;
+    }
+    return false;
+}
+bool p2p_get_attribute_noa(const u8 *ies, u32 oui_type, struct ssv6xxx_p2p_noa_attribute *noa_attr)
+{
+    const u8 *end, *pos, *ie;
+    u32 len;
+    pos = ies;
+    end = ies + ies_len;
+    ie = NULL;
+    while (pos + 1 < end) {
+        if (pos + 2 + pos[1] > end)
+            return false;
+        if (pos[0] == WLAN_EID_VENDOR_SPECIFIC && pos[1] >= 4 &&
+            WPA_GET_BE32(&pos[2]) == oui_type) {
+            ie = pos;
+            if(p2p_find_noa(ie, 0, noa_attr) == true)
+                return true;
+        }
+        pos += 2 + pos[1];
+    }
+    return false;
+}
+void ssv6xxx_process_noa_event(struct ssv_softc *sc, struct sk_buff *skb)
+{
+    struct cfg_host_event *host_event;
+    struct ssv62xx_noa_evt *noa_evt;
+    host_event = (struct cfg_host_event *)skb->data;
+    noa_evt= (struct ssv62xx_noa_evt *)&host_event->dat[0];
+    switch(noa_evt->evt_id) {
+    case SSV6XXX_NOA_START:
+        sc->p2p_noa.active_noa_vif |= (1<<noa_evt->vif);
+        printk("SSV6XXX_NOA_START===>[%08x]\n", sc->p2p_noa.active_noa_vif);
+        break;
+    case SSV6XXX_NOA_STOP:
+        sc->p2p_noa.active_noa_vif &= ~(1<<noa_evt->vif);
+        printk("SSV6XXX_NOA_STOP===>[%08x]\n", sc->p2p_noa.active_noa_vif);
+        break;
+    default:
+        printk("--------->NOA wrong command<---------\n");
+        break;
+    }
+}
+void ssv6xxx_noa_reset(struct ssv_softc *sc)
+{
+    unsigned long flags;
+    printk("Reset NOA param...\n");
+    spin_lock_irqsave(&sc->p2p_noa.p2p_config_lock, flags);
+    memset(&sc->p2p_noa.noa_detect, 0, sizeof(struct ssv_p2p_noa_detect)*SSV_NUM_VIF);
+    sc->p2p_noa.active_noa_vif = 0;
+    sc->p2p_noa.monitor_noa_vif = 0;
+    spin_unlock_irqrestore(&sc->p2p_noa.p2p_config_lock, flags);
+}
+void ssv6xxx_noa_host_stop_noa(struct ssv_softc *sc, u8 vif_id)
+{
+    struct ssv6xxx_p2p_noa_attribute noa_attr;
+    if(sc->p2p_noa.noa_detect[vif_id].p2p_noa_index>=0) {
+        sc->p2p_noa.noa_detect[vif_id].p2p_noa_index = -1;
+        sc->p2p_noa.active_noa_vif &= ~(1<<vif_id);
+        memset(&sc->p2p_noa.noa_detect[vif_id].noa_param_cmd, 0, sizeof(struct ssv6xxx_p2p_noa_param));
+        printk("->remove NOA operating vif[%d]\n", vif_id);
+        noa_attr.noa_param.enable = 0;
+        noa_attr.noa_param.vif_id = vif_id;
+        ssv6xxx_send_noa_cmd(sc, &noa_attr.noa_param);
+    }
+}
+void ssv6xxx_noa_detect(struct ssv_softc *sc, struct ieee80211_hdr * hdr, u32 len)
+{
+    int i;
+    unsigned long flags;
+    struct ieee80211_mgmt * mgmt =(struct ieee80211_mgmt *)hdr;
+    struct ssv6xxx_p2p_noa_attribute noa_attr;
+    spin_lock_irqsave(&sc->p2p_noa.p2p_config_lock, flags);
+    if(sc->p2p_noa.monitor_noa_vif == 0)
+        goto out;
+    for(i=0; i<SSV_NUM_VIF; i++) {
+        if(sc->p2p_noa.noa_detect[i].noa_addr == NULL)
+            continue;
+        if(memcmp(mgmt->bssid, sc->p2p_noa.noa_detect[i].noa_addr, 6) != 0)
+            continue;
+        if(sc->p2p_noa.active_noa_vif &&
+           ((sc->p2p_noa.active_noa_vif & 1<<i) == 0))
+            continue;
+        sc->p2p_noa.noa_detect[i].last_rx = jiffies;
+        if(p2p_get_attribute_noa((const u8*)mgmt->u.beacon.variable,
+                                 len - (IEEE80211_HDRLEN + sizeof(mgmt->u.beacon)),
+                                 P2P_IE_VENDOR_TYPE,
+                                 &noa_attr)== false) {
+            continue;
+        }
+        if(sc->p2p_noa.noa_detect[i].p2p_noa_index == noa_attr.index) {
+            goto out;
+        }
+        printk(MACSTR"->set NOA element\n", MAC2STR(mgmt->bssid));
+        sc->p2p_noa.active_noa_vif |= (1<<i);
+        sc->p2p_noa.noa_detect[i].p2p_noa_index = noa_attr.index;
+        memcpy(&sc->p2p_noa.noa_detect[i].noa_param_cmd, &noa_attr.noa_param, sizeof(struct ssv6xxx_p2p_noa_param));
+        noa_attr.noa_param.enable = 1;
+        noa_attr.noa_param.vif_id = i;
+        memcpy(noa_attr.noa_param.addr, hdr->addr2, 6);
+        ssv6xxx_send_noa_cmd(sc, &noa_attr.noa_param);
+    }
+out:
+    spin_unlock_irqrestore(&sc->p2p_noa.p2p_config_lock, flags);
+}
+void ssv6xxx_noa_hdl_bss_change(struct ssv_softc *sc, enum ssv6xxx_noa_conf conf, u8 vif_idx){
+    unsigned long flags;
+    if(sc->vif_info[vif_idx].vif->type != NL80211_IFTYPE_STATION ||
+        sc->vif_info[vif_idx].vif->p2p != true)
+        return;
+    spin_lock_irqsave(&sc->p2p_noa.p2p_config_lock, flags);
+    printk("====>[NOA]ssv6xxx_noa_hdl_bss_change conf[%d] vif_idx[%d]\n", conf, vif_idx);
+    switch(conf)
+    {
+        case MONITOR_NOA_CONF_ADD:
+            memset(&sc->p2p_noa.noa_detect[vif_idx], 0, sizeof(struct ssv_p2p_noa_detect));
+            sc->p2p_noa.noa_detect[vif_idx].noa_addr = sc->vif_info[vif_idx].vif->bss_conf.bssid;
+            sc->p2p_noa.noa_detect[vif_idx].p2p_noa_index = -1;
+            sc->p2p_noa.noa_detect[vif_idx].last_rx = jiffies;
+            sc->p2p_noa.monitor_noa_vif |= 1<< vif_idx;
+            break;
+        case MONITOR_NOA_CONF_REMOVE:
+            sc->p2p_noa.monitor_noa_vif &= ~(1<< vif_idx);
+            sc->p2p_noa.noa_detect[vif_idx].noa_addr = NULL;
+            ssv6xxx_noa_host_stop_noa(sc, vif_idx);
+            break;
+        default:
+            break;
+    }
+    spin_unlock_irqrestore(&sc->p2p_noa.p2p_config_lock, flags);
+}
+void ssv6xxx_send_noa_cmd(struct ssv_softc *sc, struct ssv6xxx_p2p_noa_param *p2p_noa_param)
+{
+    struct sk_buff *skb;
+    struct cfg_host_cmd *host_cmd;
+    int retry_cnt = 5;
+    skb = ssv_skb_alloc(HOST_CMD_HDR_LEN + sizeof(struct ssv6xxx_p2p_noa_param));
+    skb->data_len = HOST_CMD_HDR_LEN + sizeof(struct ssv6xxx_p2p_noa_param);
+    skb->len = skb->data_len;
+    host_cmd = (struct cfg_host_cmd *)skb->data;
+    host_cmd->c_type = HOST_CMD;
+    host_cmd->h_cmd = (u8)SSV6XXX_HOST_CMD_SET_NOA;
+    host_cmd->len = skb->data_len;
+    memcpy(host_cmd->dat32, p2p_noa_param, sizeof(struct ssv6xxx_p2p_noa_param));
+    printk("Noa cmd NOA Parameter:\nEnable=%d\nInterval=%d\nDuration=%d\nStart_time=0x%08x\nCount=%d\nAddr=[%02x:%02x:%02x:%02x:%02x:%02x]vif[%d]\n\n",
+                        p2p_noa_param->enable,
+                        p2p_noa_param->interval,
+                        p2p_noa_param->duration,
+                        p2p_noa_param->start_time,
+                        p2p_noa_param->count,
+                        p2p_noa_param->addr[0],
+                        p2p_noa_param->addr[1],
+                        p2p_noa_param->addr[2],
+                        p2p_noa_param->addr[3],
+                        p2p_noa_param->addr[4],
+                        p2p_noa_param->addr[5],
+                        p2p_noa_param->vif_id);
+    while((HCI_SEND_CMD(sc->sh, skb)!=0)&&(retry_cnt)){
+        printk(KERN_INFO "NOA cmd retry=%d!!\n",retry_cnt);
+        retry_cnt--;
+    }
+    ssv_skb_free(skb);
+}
+#if 0
+void ssv6200_cmd_work(struct work_struct *work)
+{
+    struct ssv_softc *sc =
+            container_of(work, struct ssv_softc, cmd_work);
+    struct sk_buff *skb;
+    bool cmd_mode;
+    int retry_cnt = 5;
+    do{
+        if(sc->cmd_info.state == SSC_CMD_STATE_IDLE){
+            struct cfg_host_cmd *host_cmd;
+            skb = skb_peek(&sc->cmd_info.cmd_que);
+            if(skb == NULL)
+                break;
+            host_cmd = (struct cfg_host_cmd *)skb->data;
+            while((HCI_SEND_CMD(sc->sh, skb)!=0)&&(retry_cnt)){
+                    printk(KERN_INFO "cmd retry=%d!!\n",retry_cnt);
+                    retry_cnt--;
+            }
+            if(retry_cnt)
+                sc->cmd_info.state = SSC_CMD_STATE_WAIT_RSP;
+        }else{
+            skb = skb_dequeue(&sc->cmd_info.evt_que);
+            if(skb == NULL)
+                break;
+        }
+    }while(1);
+}
+#endif
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smac/p2p.h b/drivers/net/wireless/ssv6x5x/smac/p2p.h
new file mode 100644
index 000000000..98f4be84f
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/p2p.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _P2P_H_
+#define _P2P_H_
+#ifdef SSV_MAC80211
+#include "ssv_mac80211.h"
+#else
+#include <net/mac80211.h>
+#endif
+#include <ssv6xxx_common.h>
+#include "drv_comm.h"
+#ifdef CONFIG_P2P_NOA
+#define P2P_MAX_NOA_INTERFACE 1
+struct ssv_p2p_noa_detect {
+    const u8 *noa_addr;
+    s16 p2p_noa_index;
+    unsigned long last_rx;
+    struct ssv6xxx_p2p_noa_param noa_param_cmd;
+};
+struct ssv_p2p_noa {
+    spinlock_t p2p_config_lock;
+    struct ssv_p2p_noa_detect noa_detect[SSV_NUM_VIF];
+    u8 active_noa_vif;
+    u8 monitor_noa_vif;
+};
+enum ssv_cmd_state {
+    SSC_CMD_STATE_IDLE,
+    SSC_CMD_STATE_WAIT_RSP,
+};
+struct ssv_cmd_Info {
+    struct sk_buff_head cmd_que;
+    struct sk_buff_head evt_que;
+    enum ssv_cmd_state state;
+};
+enum ssv6xxx_noa_conf {
+    MONITOR_NOA_CONF_ADD,
+    MONITOR_NOA_CONF_REMOVE,
+};
+struct ssv_softc;
+void ssv6xxx_process_noa_event(struct ssv_softc *sc, struct sk_buff *skb);
+void ssv6xxx_noa_hdl_bss_change(struct ssv_softc *sc, enum ssv6xxx_noa_conf conf, u8 vif_idx);
+void ssv6xxx_process_noa_event(struct ssv_softc *sc, struct sk_buff *skb);
+void ssv6xxx_noa_detect(struct ssv_softc *sc, struct ieee80211_hdr * hdr, u32 len);
+void ssv6xxx_noa_reset(struct ssv_softc *sc);
+#endif
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smac/sec.h b/drivers/net/wireless/ssv6x5x/smac/sec.h
new file mode 100644
index 000000000..53cbf0e91
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/sec.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef SEC_H
+#define SEC_H
+#include <linux/types.h>
+#include <linux/ieee80211.h>
+#ifdef SSV_MAC80211
+#include "ssv_mac80211.h"
+#else
+#include <net/mac80211.h>
+#endif
+#define CCMP_TK_LEN 16
+#define TKIP_KEY_LEN 32
+#define WEP_KEY_LEN 13
+struct ssv_crypto_ops {
+    const char *name;
+    struct list_head list;
+    void *(*init) (int keyidx);
+    void (*deinit) (void *priv);
+    int (*encrypt_mpdu) (struct sk_buff * skb, int hdr_len, void *priv);
+    int (*decrypt_mpdu) (struct sk_buff * skb, int hdr_len, void *priv);
+    int (*encrypt_msdu) (struct sk_buff * skb, int hdr_len, void *priv);
+    int (*decrypt_msdu) (struct sk_buff * skb, int keyidx, int hdr_len,
+                         void *priv);
+    int (*set_tx_pn) (u8 * seq, void *priv);
+    int (*set_key) (void *key, int len, u8 * seq, void *priv);
+    int (*get_key) (void *key, int len, u8 * seq, void *priv);
+    char *(*print_stats) (char *p, void *priv);
+    unsigned long (*get_flags) (void *priv);
+    unsigned long (*set_flags) (unsigned long flags, void *priv);
+#ifdef MULTI_THREAD_ENCRYPT
+    int (*encrypt_prepare) (struct sk_buff * skb, int hdr_len, void *priv);
+    int (*decrypt_prepare) (struct sk_buff * skb, int hdr_len, void *priv);
+#endif
+    int extra_mpdu_prefix_len, extra_mpdu_postfix_len;
+    int extra_msdu_prefix_len, extra_msdu_postfix_len;
+};
+struct ssv_crypto_data {
+    struct ssv_crypto_ops *ops;
+    void *priv;
+#ifdef HAS_CRYPTO_LOCK
+    rwlock_t lock;
+#endif
+};
+struct ssv_crypto_ops *get_crypto_ccmp_ops(void);
+struct ssv_crypto_ops *get_crypto_tkip_ops(void);
+struct ssv_crypto_ops *get_crypto_wep_ops(void);
+#ifdef CONFIG_SSV_WAPI
+struct ssv_crypto_ops *get_crypto_wpi_ops(void);
+#endif
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smac/sec_ccmp.c b/drivers/net/wireless/ssv6x5x/smac/sec_ccmp.c
new file mode 100644
index 000000000..cfbfb0f24
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/sec_ccmp.c
@@ -0,0 +1,786 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/version.h>
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/random.h>
+#include <linux/skbuff.h>
+#include <linux/netdevice.h>
+#include <linux/if_ether.h>
+#include <linux/if_arp.h>
+#include <asm/string.h>
+#include <linux/wireless.h>
+#include <linux/ieee80211.h>
+#include <linux/crypto.h>
+#include <linux/module.h>
+#include "sec.h"
+#define PRINT_DEBUG 0
+#define AES_BLOCK_LEN 16
+#define CCMP_HDR_LEN 8
+#define CCMP_MIC_LEN 8
+#define CCMP_PN_LEN 6
+#ifdef MULTI_THREAD_ENCRYPT
+int prepare_mask = 0x0b0e0e0f;
+#endif
+struct lib80211_ccmp_data {
+    u8 key[CCMP_TK_LEN];
+    int key_set;
+    u8 tx_pn[CCMP_PN_LEN];
+    u8 rx_pn[CCMP_PN_LEN];
+#ifdef MULTI_THREAD_ENCRYPT
+    u8 pre_rx_pn[CCMP_PN_LEN];
+#endif
+    u32 dot11RSNAStatsCCMPFormatErrors;
+    u32 dot11RSNAStatsCCMPReplays;
+    u32 dot11RSNAStatsCCMPDecryptErrors;
+    int key_idx;
+    struct crypto_cipher *tfm;
+#ifndef MULTI_THREAD_ENCRYPT
+    u8 tx_b0[AES_BLOCK_LEN], tx_b[AES_BLOCK_LEN],
+    tx_e[AES_BLOCK_LEN], tx_s0[AES_BLOCK_LEN];
+    u8 rx_b0[AES_BLOCK_LEN], rx_b[AES_BLOCK_LEN], rx_a[AES_BLOCK_LEN];
+#else
+    u8 *tx_b0, *tx_b, *tx_e, *tx_s0;
+    u8 *rx_b0, *rx_b, *rx_a;
+#endif
+};
+static inline void lib80211_ccmp_aes_encrypt(struct crypto_cipher *tfm,
+        const u8 pt[16], u8 ct[16])
+{
+    crypto_cipher_encrypt_one(tfm, ct, pt);
+}
+static void *lib80211_ccmp_init(int key_idx)
+{
+    struct lib80211_ccmp_data *priv;
+    const char *cipher_name = "aes";
+#ifdef MULTI_THREAD_ENCRYPT
+    unsigned int buf_size = num_present_cpus()*AES_BLOCK_LEN*sizeof(u8);
+#endif
+    priv = kzalloc(sizeof(*priv), GFP_ATOMIC);
+    if (priv == NULL)
+        goto fail;
+    priv->key_idx = key_idx;
+    priv->tfm = crypto_alloc_cipher(cipher_name, 0, CRYPTO_ALG_ASYNC);
+    if (IS_ERR(priv->tfm)) {
+        printk(KERN_ERR "Failed to allocate cipher %s\n", cipher_name);
+        priv->tfm = NULL;
+        goto fail;
+    } else {
+        printk(KERN_ERR "Found %s in driver %s (M %s).\n",
+               priv->tfm->base.__crt_alg->cra_name,
+               priv->tfm->base.__crt_alg->cra_driver_name,
+               priv->tfm->base.__crt_alg->cra_module->name);
+    }
+#ifdef MULTI_THREAD_ENCRYPT
+    priv->tx_b0 = priv->tx_b = priv->tx_e = priv->tx_s0 = NULL;
+    priv->tx_b0 = (u8 *)kzalloc(buf_size, GFP_ATOMIC);
+    priv->tx_b = (u8 *)kzalloc(buf_size, GFP_ATOMIC);
+    priv->tx_e = (u8 *)kzalloc(buf_size, GFP_ATOMIC);
+    priv->tx_s0 = (u8 *)kzalloc(buf_size, GFP_ATOMIC);
+    priv->rx_b0 = (u8 *)kzalloc(buf_size, GFP_ATOMIC);
+    priv->rx_b = (u8 *)kzalloc(buf_size, GFP_ATOMIC);
+    priv->rx_a = (u8 *)kzalloc(buf_size, GFP_ATOMIC);
+    if( (priv->tx_b0 == NULL) || (priv->tx_b == NULL) || (priv->tx_e == NULL) ||
+        (priv->tx_s0 == NULL) ||(priv->rx_b0 == NULL) || (priv->rx_b == NULL) || (priv->rx_a == NULL) ) {
+        printk("#######fail to create memory for ccmp!!!\n");
+        goto fail;
+    }
+#endif
+    return priv;
+fail:
+    if (priv) {
+        if (priv->tfm)
+            crypto_free_cipher(priv->tfm);
+#ifdef MULTI_THREAD_ENCRYPT
+        if(priv->tx_b0 != NULL)
+            kfree(priv->tx_b0);
+        if(priv->tx_b != NULL)
+            kfree(priv->tx_b);
+        if(priv->tx_e != NULL)
+            kfree(priv->tx_e);
+        if(priv->tx_s0 != NULL)
+            kfree(priv->tx_s0);
+        if(priv->rx_b0 != NULL)
+            kfree(priv->rx_b0);
+        if(priv->rx_b != NULL)
+            kfree(priv->rx_b);
+        if(priv->rx_a != NULL)
+            kfree(priv->rx_a);
+#endif
+        kfree(priv);
+    }
+    return NULL;
+}
+static void lib80211_ccmp_deinit(void *priv)
+{
+    struct lib80211_ccmp_data *_priv = priv;
+    if (_priv && _priv->tfm)
+        crypto_free_cipher(_priv->tfm);
+#ifdef MULTI_THREAD_ENCRYPT
+    if(_priv->tx_b0 != NULL)
+        kfree(_priv->tx_b0);
+    if(_priv->tx_b != NULL)
+        kfree(_priv->tx_b);
+    if(_priv->tx_e != NULL)
+        kfree(_priv->tx_e);
+    if(_priv->tx_s0 != NULL)
+        kfree(_priv->tx_s0);
+    if(_priv->rx_b0 != NULL)
+        kfree(_priv->rx_b0);
+    if(_priv->rx_b != NULL)
+        kfree(_priv->rx_b);
+    if(_priv->rx_a != NULL)
+        kfree(_priv->rx_a);
+#endif
+    kfree(priv);
+}
+static inline void xor_block(u8 * b, u8 * a, size_t len)
+{
+    int i;
+    for (i = 0; i < len; i++)
+        b[i] ^= a[i];
+}
+static void ccmp_init_blocks(struct crypto_cipher *tfm,
+                             struct ieee80211_hdr *hdr,
+                             u8 * pn, size_t dlen, u8 * b0, u8 * auth, u8 * s0)
+{
+    u8 *pos, qc = 0;
+    size_t aad_len;
+    int a4_included, qc_included;
+    u8 aad[2 * AES_BLOCK_LEN];
+    a4_included = ieee80211_has_a4(hdr->frame_control);
+    qc_included = ieee80211_is_data_qos(hdr->frame_control);
+    aad_len = 22;
+    if (a4_included)
+        aad_len += 6;
+    if (qc_included) {
+        pos = (u8 *) & hdr->addr4;
+        if (a4_included)
+            pos += 6;
+        qc = *pos & 0x0f;
+        aad_len += 2;
+    }
+    b0[0] = 0x59;
+    b0[1] = qc;
+    memcpy(b0 + 2, hdr->addr2, ETH_ALEN);
+    memcpy(b0 + 8, pn, CCMP_PN_LEN);
+    b0[14] = (dlen >> 8) & 0xff;
+    b0[15] = dlen & 0xff;
+    pos = (u8 *) hdr;
+    aad[0] = 0;
+    aad[1] = aad_len & 0xff;
+    aad[2] = pos[0] & 0x8f;
+    aad[3] = pos[1] & 0xc7;
+    memcpy(aad + 4, hdr->addr1, 3 * ETH_ALEN);
+    pos = (u8 *) & hdr->seq_ctrl;
+    aad[22] = pos[0] & 0x0f;
+    aad[23] = 0;
+    memset(aad + 24, 0, 8);
+    if (a4_included)
+        memcpy(aad + 24, hdr->addr4, ETH_ALEN);
+    if (qc_included) {
+        aad[a4_included ? 30 : 24] = qc;
+    }
+    lib80211_ccmp_aes_encrypt(tfm, b0, auth);
+    xor_block(auth, aad, AES_BLOCK_LEN);
+    lib80211_ccmp_aes_encrypt(tfm, auth, auth);
+    xor_block(auth, &aad[AES_BLOCK_LEN], AES_BLOCK_LEN);
+    lib80211_ccmp_aes_encrypt(tfm, auth, auth);
+    b0[0] &= 0x07;
+    b0[14] = b0[15] = 0;
+    lib80211_ccmp_aes_encrypt(tfm, b0, s0);
+}
+static int lib80211_ccmp_hdr(struct sk_buff *skb, int hdr_len,
+                             u8 *aeskey, int keylen, void *priv)
+{
+    struct lib80211_ccmp_data *key = priv;
+    int i;
+    u8 *pos;
+    if (skb_headroom(skb) < CCMP_HDR_LEN || skb->len < hdr_len)
+        return -1;
+    if (aeskey != NULL && keylen >= CCMP_TK_LEN)
+        memcpy(aeskey, key->key, CCMP_TK_LEN);
+    pos = skb_push(skb, CCMP_HDR_LEN);
+    memmove(pos, pos + CCMP_HDR_LEN, hdr_len);
+    pos += hdr_len;
+    i = CCMP_PN_LEN - 1;
+    while (i >= 0) {
+        key->tx_pn[i]++;
+        if (key->tx_pn[i] != 0)
+            break;
+        i--;
+    }
+    *pos++ = key->tx_pn[5];
+    *pos++ = key->tx_pn[4];
+    *pos++ = 0;
+    *pos++ = (key->key_idx << 6) | (1 << 5) ;
+    *pos++ = key->tx_pn[3];
+    *pos++ = key->tx_pn[2];
+    *pos++ = key->tx_pn[1];
+    *pos++ = key->tx_pn[0];
+    return CCMP_HDR_LEN;
+}
+static int lib80211_ccmp_encrypt(struct sk_buff *skb, int hdr_len, void *priv)
+{
+    struct lib80211_ccmp_data *key = priv;
+    int data_len, i, blocks, last, len;
+    u8 *pos, *mic;
+    struct ieee80211_hdr *hdr;
+#ifndef MULTI_THREAD_ENCRYPT
+    u8 *b0 = key->tx_b0;
+    u8 *b = key->tx_b;
+    u8 *e = key->tx_e;
+    u8 *s0 = key->tx_s0;
+    int ret;
+#else
+    unsigned int offset = smp_processor_id()*AES_BLOCK_LEN*sizeof(u8);
+    u8 *b0 = (key->tx_b0 + offset);
+    u8 *b = (key->tx_b + offset);
+    u8 *e = (key->tx_e + offset);
+    u8 *s0 = (key->tx_s0 + offset);
+    u8 tmp_tx_pn[CCMP_PN_LEN], *ccmp_hdr_ptr = NULL;
+    void *mask_ptr = NULL;
+#endif
+#ifndef MULTI_THREAD_ENCRYPT
+    ret = skb_padto(skb, skb->len + CCMP_MIC_LEN);
+    if (ret) {
+        printk(KERN_ERR "Failed to extand skb for CCMP encryption.");
+        return -1;
+    }
+    if (skb->len < hdr_len)
+        return -1;
+#endif
+#ifndef MULTI_THREAD_ENCRYPT
+    data_len = skb->len - hdr_len;
+    len = lib80211_ccmp_hdr(skb, hdr_len, NULL, 0, priv);
+    if (len < 0)
+        return -1;
+#else
+    mask_ptr = (void *)((size_t)skb_end_pointer(skb) - sizeof(prepare_mask));
+    if(memcmp(mask_ptr, &prepare_mask, sizeof(prepare_mask)) != 0) {
+        printk("no prepared skb\n");
+        return -1;
+    }
+    data_len = skb->len - (hdr_len + CCMP_HDR_LEN);
+    ccmp_hdr_ptr = (u8 *)(skb->data + hdr_len);
+    tmp_tx_pn[5] = ccmp_hdr_ptr[0];
+    tmp_tx_pn[4] = ccmp_hdr_ptr[1];
+    tmp_tx_pn[3] = ccmp_hdr_ptr[4];
+    tmp_tx_pn[2] = ccmp_hdr_ptr[5];
+    tmp_tx_pn[1] = ccmp_hdr_ptr[6];
+    tmp_tx_pn[0] = ccmp_hdr_ptr[7];
+#endif
+    pos = skb->data + hdr_len + CCMP_HDR_LEN;
+    hdr = (struct ieee80211_hdr *)skb->data;
+#ifndef MULTI_THREAD_ENCRYPT
+    ccmp_init_blocks(key->tfm, hdr, key->tx_pn, data_len, b0, b, s0);
+#else
+    ccmp_init_blocks(key->tfm, hdr, tmp_tx_pn, data_len, b0, b, s0);
+#endif
+    blocks = DIV_ROUND_UP(data_len, AES_BLOCK_LEN);
+    last = data_len % AES_BLOCK_LEN;
+    for (i = 1; i <= blocks; i++) {
+        len = (i == blocks && last) ? last : AES_BLOCK_LEN;
+        xor_block(b, pos, len);
+        lib80211_ccmp_aes_encrypt(key->tfm, b, b);
+        b0[14] = (i >> 8) & 0xff;
+        b0[15] = i & 0xff;
+        lib80211_ccmp_aes_encrypt(key->tfm, b0, e);
+        xor_block(pos, e, len);
+        pos += len;
+    }
+    mic = skb_put(skb, CCMP_MIC_LEN);
+    for (i = 0; i < CCMP_MIC_LEN; i++)
+        mic[i] = b[i] ^ s0[i];
+    return 0;
+}
+static inline int ccmp_replay_check(u8 *pn_n, u8 *pn_o)
+{
+    u32 iv32_n, iv16_n;
+    u32 iv32_o, iv16_o;
+    iv32_n = (pn_n[0] << 24) | (pn_n[1] << 16) | (pn_n[2] << 8) | pn_n[3];
+    iv16_n = (pn_n[4] << 8) | pn_n[5];
+    iv32_o = (pn_o[0] << 24) | (pn_o[1] << 16) | (pn_o[2] << 8) | pn_o[3];
+    iv16_o = (pn_o[4] << 8) | pn_o[5];
+    if ((s32)iv32_n - (s32)iv32_o < 0 ||
+        (iv32_n == iv32_o && iv16_n <= iv16_o))
+        return 1;
+    return 0;
+}
+static int lib80211_ccmp_decrypt(struct sk_buff *skb, int hdr_len, void *priv)
+{
+    struct lib80211_ccmp_data *key = priv;
+    u8 keyidx, *pos;
+    struct ieee80211_hdr *hdr;
+#ifndef MULTI_THREAD_ENCRYPT
+    u8 *b0 = key->rx_b0;
+    u8 *b = key->rx_b;
+    u8 *a = key->rx_a;
+#else
+    unsigned int offset = smp_processor_id()*AES_BLOCK_LEN*sizeof(u8);
+    u8 *b0 = (key->rx_b0 + offset);
+    u8 *b = (key->rx_b + offset);
+    u8 *a = (key->rx_a + offset);
+#endif
+    u8 pn[6];
+    int i, blocks, last, len;
+    size_t data_len = skb->len - hdr_len - CCMP_HDR_LEN - CCMP_MIC_LEN;
+    u8 *mic = skb->data + skb->len - CCMP_MIC_LEN;
+#ifndef MULTI_THREAD_ENCRYPT
+    if (skb->len < hdr_len + CCMP_HDR_LEN + CCMP_MIC_LEN) {
+        key->dot11RSNAStatsCCMPFormatErrors++;
+        return -1;
+    }
+#endif
+    hdr = (struct ieee80211_hdr *)skb->data;
+    pos = skb->data + hdr_len;
+    keyidx = pos[3];
+#ifndef MULTI_THREAD_ENCRYPT
+    if (!(keyidx & (1 << 5))) {
+        if (net_ratelimit()) {
+            printk(KERN_DEBUG "CCMP: received packet without ExtIV"
+                   " flag from %pM (%02X)\n", hdr->addr2, keyidx);
+        }
+        key->dot11RSNAStatsCCMPFormatErrors++;
+        return -2;
+    }
+    keyidx >>= 6;
+    if (key->key_idx != keyidx) {
+        printk(KERN_DEBUG "CCMP: RX tkey->key_idx=%d frame "
+               "keyidx=%d priv=%p\n", key->key_idx, keyidx, priv);
+        return -6;
+    }
+    if (!key->key_set) {
+        if (net_ratelimit()) {
+            printk(KERN_DEBUG "CCMP: received packet from %pM"
+                   " with keyid=%d that does not have a configured"
+                   " key\n", hdr->addr2, keyidx);
+        }
+        return -3;
+    }
+#endif
+    pn[0] = pos[7];
+    pn[1] = pos[6];
+    pn[2] = pos[5];
+    pn[3] = pos[4];
+    pn[4] = pos[1];
+    pn[5] = pos[0];
+    pos += 8;
+#if 0
+    if (ccmp_replay_check(pn, key->rx_pn)) {
+#ifdef CONFIG_LIB80211_DEBUG
+        if (net_ratelimit()) {
+            printk(KERN_DEBUG "CCMP: replay detected: STA=%pM "
+                   "previous PN %02x%02x%02x%02x%02x%02x "
+                   "received PN %02x%02x%02x%02x%02x%02x\n",
+                   hdr->addr2,
+                   key->rx_pn[0], key->rx_pn[1], key->rx_pn[2],
+                   key->rx_pn[3], key->rx_pn[4], key->rx_pn[5],
+                   pn[0], pn[1], pn[2], pn[3], pn[4], pn[5]);
+        }
+#endif
+        key->dot11RSNAStatsCCMPReplays++;
+        return -4;
+    }
+#endif
+    ccmp_init_blocks(key->tfm, hdr, pn, data_len, b0, a, b);
+    xor_block(mic, b, CCMP_MIC_LEN);
+    blocks = DIV_ROUND_UP(data_len, AES_BLOCK_LEN);
+    last = data_len % AES_BLOCK_LEN;
+    for (i = 1; i <= blocks; i++) {
+        len = (i == blocks && last) ? last : AES_BLOCK_LEN;
+        b0[14] = (i >> 8) & 0xff;
+        b0[15] = i & 0xff;
+        lib80211_ccmp_aes_encrypt(key->tfm, b0, b);
+        xor_block(pos, b, len);
+        xor_block(a, pos, len);
+        lib80211_ccmp_aes_encrypt(key->tfm, a, a);
+        pos += len;
+    }
+    if (memcmp(mic, a, CCMP_MIC_LEN) != 0) {
+        if (net_ratelimit()) {
+            printk(KERN_DEBUG "CCMP: decrypt failed: STA="
+                   "%pM\n", hdr->addr2);
+        }
+        key->dot11RSNAStatsCCMPDecryptErrors++;
+        return -5;
+    }
+#ifndef MULTI_THREAD_ENCRYPT
+    memcpy(key->rx_pn, pn, CCMP_PN_LEN);
+#else
+    if (!ccmp_replay_check(pn, key->rx_pn))
+        memcpy(key->rx_pn, pn, CCMP_PN_LEN);
+#endif
+    memmove(skb->data + CCMP_HDR_LEN, skb->data, hdr_len);
+    skb_pull(skb, CCMP_HDR_LEN);
+    skb_trim(skb, skb->len - CCMP_MIC_LEN);
+    return keyidx;
+}
+static int lib80211_ccmp_set_key(void *key, int len, u8 * seq, void *priv)
+{
+    struct lib80211_ccmp_data *data = priv;
+    int keyidx;
+    struct crypto_cipher *tfm = data->tfm;
+#ifdef MULTI_THREAD_ENCRYPT
+    u8 *tx_b0 = data->tx_b0;
+    u8 *tx_b = data->tx_b;
+    u8 *tx_e = data->tx_e;
+    u8 *tx_s0 = data->tx_s0;
+    u8 *rx_b0 = data->rx_b0;
+    u8 *rx_b = data->rx_b;
+    u8 *rx_a = data->rx_a;
+#endif
+    keyidx = data->key_idx;
+    memset(data, 0, sizeof(*data));
+    data->key_idx = keyidx;
+    data->tfm = tfm;
+    if (len == CCMP_TK_LEN) {
+        memcpy(data->key, key, CCMP_TK_LEN);
+        data->key_set = 1;
+        if (seq) {
+            data->rx_pn[0] = seq[5];
+            data->rx_pn[1] = seq[4];
+            data->rx_pn[2] = seq[3];
+            data->rx_pn[3] = seq[2];
+            data->rx_pn[4] = seq[1];
+            data->rx_pn[5] = seq[0];
+#ifdef MULTI_THREAD_ENCRYPT
+            memcpy(data->pre_rx_pn, data->rx_pn, CCMP_PN_LEN);
+#endif
+        }
+        crypto_cipher_setkey(data->tfm, data->key, CCMP_TK_LEN);
+#ifdef MULTI_THREAD_ENCRYPT
+        data->tx_b0 = tx_b0;
+        data->tx_b = tx_b;
+        data->tx_e = tx_e;
+        data->tx_s0 = tx_s0;
+        data->rx_b0 = rx_b0;
+        data->rx_b = rx_b;
+        data->rx_a = rx_a;
+#endif
+    } else if (len == 0)
+        data->key_set = 0;
+    else
+        return -1;
+    return 0;
+}
+static int lib80211_ccmp_get_key(void *key, int len, u8 * seq, void *priv)
+{
+    struct lib80211_ccmp_data *data = priv;
+    if (len < CCMP_TK_LEN)
+        return -1;
+    if (!data->key_set)
+        return 0;
+    memcpy(key, data->key, CCMP_TK_LEN);
+    if (seq) {
+        seq[0] = data->tx_pn[5];
+        seq[1] = data->tx_pn[4];
+        seq[2] = data->tx_pn[3];
+        seq[3] = data->tx_pn[2];
+        seq[4] = data->tx_pn[1];
+        seq[5] = data->tx_pn[0];
+    }
+    return CCMP_TK_LEN;
+}
+static int lib80211_ccmp_set_tx_pn(u8 * seq, void *priv)
+{
+    struct lib80211_ccmp_data *data = priv;
+    if (seq) {
+        data->tx_pn[0] = seq[0];
+        data->tx_pn[1] = seq[1];
+        data->tx_pn[2] = seq[2];
+        data->tx_pn[3] = seq[3];
+        data->tx_pn[4] = seq[4];
+        data->tx_pn[5] = seq[5];
+    }
+    return 0;
+}
+static char *lib80211_ccmp_print_stats(char *p, void *priv)
+{
+    struct lib80211_ccmp_data *ccmp = priv;
+    p += sprintf(p, "key[%d] alg=CCMP key_set=%d "
+                 "tx_pn=%02x%02x%02x%02x%02x%02x "
+                 "rx_pn=%02x%02x%02x%02x%02x%02x "
+                 "format_errors=%d replays=%d decrypt_errors=%d\n",
+                 ccmp->key_idx, ccmp->key_set,
+                 ccmp->tx_pn[0], ccmp->tx_pn[1], ccmp->tx_pn[2],
+                 ccmp->tx_pn[3], ccmp->tx_pn[4], ccmp->tx_pn[5],
+                 ccmp->rx_pn[0], ccmp->rx_pn[1], ccmp->rx_pn[2],
+                 ccmp->rx_pn[3], ccmp->rx_pn[4], ccmp->rx_pn[5],
+                 ccmp->dot11RSNAStatsCCMPFormatErrors,
+                 ccmp->dot11RSNAStatsCCMPReplays,
+                 ccmp->dot11RSNAStatsCCMPDecryptErrors);
+    return p;
+}
+#ifdef MULTI_THREAD_ENCRYPT
+static int lib80211_ccmp_encrypt_prepare (struct sk_buff * skb, int hdr_len, void *priv)
+{
+    int data_len, len, ret;
+    void *ptr = NULL;
+    if (skb_tailroom(skb) < CCMP_MIC_LEN) {
+        ret = skb_padto(skb, skb->len + CCMP_MIC_LEN);
+        if (ret != 0) {
+            printk(KERN_ERR "Failed to extand skb for CCMP encryption, ret = %d.", ret);
+            return -1;
+        }
+    }
+    if (skb->len < hdr_len)
+        return -1;
+    data_len = skb->len - hdr_len;
+    len = lib80211_ccmp_hdr(skb, hdr_len, NULL, 0, priv);
+    if (len < 0)
+        return -1;
+    ptr = (void *)((size_t)skb_end_pointer(skb) - sizeof(prepare_mask));
+    memcpy(ptr, &prepare_mask, sizeof(prepare_mask));
+    return 0;
+}
+static int lib80211_ccmp_decrypt_prepare (struct sk_buff * skb, int hdr_len, void *priv)
+{
+    struct lib80211_ccmp_data *key = priv;
+    u8 keyidx, *pos;
+    struct ieee80211_hdr *hdr;
+    u8 pn[6];
+    if (skb->len < hdr_len + CCMP_HDR_LEN + CCMP_MIC_LEN) {
+        key->dot11RSNAStatsCCMPFormatErrors++;
+        return -1;
+    }
+    hdr = (struct ieee80211_hdr *)skb->data;
+    pos = skb->data + hdr_len;
+    keyidx = pos[3];
+    if (!(keyidx & (1 << 5))) {
+        {
+            printk(KERN_DEBUG "CCMP: received packet without ExtIV"
+                   " flag from %pM (%02X)\n", hdr->addr2, keyidx);
+        }
+        key->dot11RSNAStatsCCMPFormatErrors++;
+        return -2;
+    }
+    keyidx >>= 6;
+    if (key->key_idx != keyidx) {
+        printk(KERN_DEBUG "CCMP: RX tkey->key_idx=%d frame "
+               "keyidx=%d priv=%p\n", key->key_idx, keyidx, priv);
+        return -6;
+    }
+    if (!key->key_set) {
+        {
+            printk(KERN_DEBUG "CCMP: received packet from %pM"
+                   " with keyid=%d that does not have a configured"
+                   " key\n", hdr->addr2, keyidx);
+        }
+        return -3;
+    }
+    pn[0] = pos[7];
+    pn[1] = pos[6];
+    pn[2] = pos[5];
+    pn[3] = pos[4];
+    pn[4] = pos[1];
+    pn[5] = pos[0];
+#if 0
+    if (ccmp_replay_check(pn, key->pre_rx_pn)) {
+#if 1
+        {
+            printk(KERN_DEBUG "CCMP: replay detected: STA=%pM "
+                   "previous PN %02x%02x%02x%02x%02x%02x "
+                   "received PN %02x%02x%02x%02x%02x%02x\n",
+                   hdr->addr2,
+                   key->rx_pn[0], key->rx_pn[1], key->rx_pn[2],
+                   key->rx_pn[3], key->rx_pn[4], key->rx_pn[5],
+                   pn[0], pn[1], pn[2], pn[3], pn[4], pn[5]);
+        }
+#endif
+        key->dot11RSNAStatsCCMPReplays++;
+        return -4;
+    }
+#endif
+    memcpy(key->pre_rx_pn, pn, CCMP_PN_LEN);
+    return 0;
+}
+#endif
+static struct ssv_crypto_ops ssv_crypt_ccmp = {
+    .name = "CCMP",
+    .init = lib80211_ccmp_init,
+    .deinit = lib80211_ccmp_deinit,
+    .encrypt_mpdu = lib80211_ccmp_encrypt,
+    .decrypt_mpdu = lib80211_ccmp_decrypt,
+    .encrypt_msdu = NULL,
+    .decrypt_msdu = NULL,
+    .set_tx_pn = lib80211_ccmp_set_tx_pn,
+    .set_key = lib80211_ccmp_set_key,
+    .get_key = lib80211_ccmp_get_key,
+    .print_stats = lib80211_ccmp_print_stats,
+    .extra_mpdu_prefix_len = CCMP_HDR_LEN,
+    .extra_mpdu_postfix_len = CCMP_MIC_LEN,
+#ifdef MULTI_THREAD_ENCRYPT
+    .encrypt_prepare = lib80211_ccmp_encrypt_prepare,
+    .decrypt_prepare = lib80211_ccmp_decrypt_prepare,
+#endif
+};
+struct ssv_crypto_ops *get_crypto_ccmp_ops(void)
+{
+    return &ssv_crypt_ccmp;
+}
+#if 0
+static inline int ccmp_replay_check(u8 *pn_n, u8 *pn_o)
+{
+    u32 iv32_n, iv16_n;
+    u32 iv32_o, iv16_o;
+    iv32_n = (pn_n[5] << 24) | (pn_n[4] << 16) | (pn_n[3] << 8) | pn_n[2];
+    iv16_n = (pn_n[1] << 8) | pn_n[0];
+    iv32_o = (pn_o[5] << 24) | (pn_o[4] << 16) | (pn_o[3] << 8) | pn_o[2];
+    iv16_o = (pn_o[1] << 8) | pn_o[0];
+    if (((u32)iv32_n < (u32)iv32_o) ||
+        (iv32_n == iv32_o && iv16_n <= iv16_o))
+        return 1;
+    return 0;
+}
+static void ccmp_special_blocks(struct sk_buff *skb, u8 *pn, u8 *scratch, int encrypted)
+{
+    u16 mask_fc;
+    u8 a4_included=0, mgmt=0;
+    u8 qos_tid;
+    u8 *b_0, *aad;
+    u16 data_len, len_a;
+    unsigned int hdrlen;
+    struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
+    mask_fc = hdr->frame_control;
+    b_0 = scratch + 3 * AES_BLOCK_LEN;
+    aad = scratch + 4 * AES_BLOCK_LEN;
+    if((mask_fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT)
+        mgmt = 1;
+    else
+        mgmt = 0;
+    mask_fc &= ~IEEE80211_FCTL_RETRY;
+    mask_fc &= ~IEEE80211_FCTL_PM;
+    mask_fc &= ~IEEE80211_FCTL_MOREDATA;
+    if (!mgmt)
+        mask_fc &= ~0x0070;
+    hdrlen = ieee80211_hdrlen(hdr->frame_control);
+    len_a = hdrlen - 2;
+    if( (mask_fc & (IEEE80211_FCTL_FROMDS|IEEE80211_FCTL_TODS)) == (IEEE80211_FCTL_FROMDS|IEEE80211_FCTL_TODS))
+        a4_included = 1;
+    else
+        a4_included = 0;
+    if (ieee80211_is_data_qos(hdr->frame_control))
+        qos_tid = *ieee80211_get_qos_ctl(hdr) & IEEE80211_QOS_CTL_TID_MASK;
+    else
+        qos_tid = 0;
+#if 0
+    if ((mask_fc & (IEEE80211_FCTL_FTYPE | IEEE80211_STYPE_QOS_DATA)) == (IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_DATA)) {
+        if(a4_included)
+            qos_tid = (*((u8 *)ppkt + ppkt->hdr_offset+30)) & IEEE80211_QOS_CTL_TID_MASK;
+        else
+            qos_tid = (*((u8 *)ppkt + ppkt->hdr_offset+24)) & IEEE80211_QOS_CTL_TID_MASK;
+    } else
+        qos_tid = 0;
+#endif
+    data_len = skb->len - hdrlen;
+    if (encrypted) {
+        data_len -= CCMP_MIC_LEN;
+        data_len -= CCMP_HDR_LEN;
+    }
+    b_0[0] = 0x59;
+    b_0[1] = qos_tid | (mgmt << 4);
+    memcpy(&b_0[2], hdr->addr2, ETH_ALEN);
+    memcpy(&b_0[8], pn, CCMP_PN_LEN);
+    put_unaligned_be16(data_len, &b_0[14]);
+    put_unaligned_be16(len_a, &aad[0]);
+    put_unaligned(mask_fc, (__le16 *)&aad[2]);
+    memcpy(&aad[4], &hdr->addr1, 3 * ETH_ALEN);
+    aad[22] = *((u8 *) &hdr->seq_ctrl) & 0x0f;
+    aad[23] = 0;
+    if (a4_included) {
+        memcpy(&aad[24], hdr->addr4, ETH_ALEN);
+        aad[30] = qos_tid;
+        aad[31] = 0;
+    } else {
+        memset(&aad[24], 0, ETH_ALEN + IEEE80211_QOS_CTL_LEN);
+        aad[24] = qos_tid;
+    }
+}
+static void ccmp_pn2hdr(u8 *hdr, int key_id, u8 *pn)
+{
+#if 0
+    hdr[0] = pn[0];
+    hdr[1] = pn[1];
+    hdr[2] = 0;
+    hdr[3] = 0x20 | (key_id << 6);
+    hdr[4] = pn[2];
+    hdr[5] = pn[3];
+    hdr[6] = pn[4];
+    hdr[7] = pn[5];
+#endif
+    hdr[0] = pn[5];
+    hdr[1] = pn[4];
+    hdr[2] = 0;
+    hdr[3] = 0x20 | (key_id << 6);
+    hdr[4] = pn[3];
+    hdr[5] = pn[2];
+    hdr[6] = pn[1];
+    hdr[7] = pn[0];
+}
+#if 0
+static void ccmp_hdr2pn(u8 *hdr, u8 *pn)
+{
+    pn[0] = hdr[0];
+    pn[1] = hdr[1];
+    pn[2] = hdr[4];
+    pn[3] = hdr[5];
+    pn[4] = hdr[6];
+    pn[5] = hdr[7];
+}
+#endif
+int ieee80211_crypto_ccmp_encrypt(struct sk_buff *skb, u8 *key, u8 keyidx, u8 *tx_pn)
+{
+    u8 *data;
+    u32 data_len;
+    u8 crypto_buf[6 * AES_BLOCK_LEN];
+    struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
+    u32 hdrlen = ieee80211_hdrlen(hdr->frame_control);
+    u64 pn64;
+    u8 pn[6];
+    data_len = skb->len - hdrlen;
+    data = ((u8*)skb->data)+hdrlen;
+#ifdef SECURITY_DUMP
+    fpga_dump(ppkt,"case-",key,16,0);
+#endif
+#if PRINT_DEBUG
+    printk("CCMP encrypt: PN =             0x%02x%02x%02x%02x%02x%02x\n",tx_pn[5],tx_pn[4],tx_pn[3],tx_pn[2],tx_pn[1],tx_pn[0]);
+#endif
+    hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PROTECTED);
+#if 0
+    frame = (u16*)((u8 *)ppkt + ppkt->hdr_offset);
+    *frame |= IEEE80211_FCTL_PROTECTED;
+#endif
+    pn64 = (*(u64*)tx_pn)++;
+    pn[5] = pn64;
+    pn[4] = pn64 >> 8;
+    pn[3] = pn64 >> 16;
+    pn[2] = pn64 >> 24;
+    pn[1] = pn64 >> 32;
+    pn[0] = pn64 >> 40;
+    ccmp_special_blocks(skb, pn, crypto_buf, 0);
+    data = skb_push(skb, CCMP_HDR_LEN);
+    memmove(data, data + CCMP_HDR_LEN, hdrlen);
+    ccmp_pn2hdr(data+hdrlen, keyidx, pn);
+    ieee80211_aes_ccm_encrypt(crypto_buf,key, data+CCMP_HDR_LEN+hdrlen, data_len, skb_put(skb, CCMP_MIC_LEN));
+#ifdef SECURITY_DUMP
+    fpga_dump(ppkt,"case-",key,16,1);
+#endif
+    return true;
+}
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smac/sec_tkip.c b/drivers/net/wireless/ssv6x5x/smac/sec_tkip.c
new file mode 100644
index 000000000..bfd386248
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/sec_tkip.c
@@ -0,0 +1,785 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/err.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/random.h>
+#include <linux/scatterlist.h>
+#include <linux/skbuff.h>
+#include <linux/netdevice.h>
+#include <linux/mm.h>
+#include <linux/if_ether.h>
+#include <linux/if_arp.h>
+#include <asm/string.h>
+#include <linux/version.h>
+#include <linux/wireless.h>
+#include <linux/ieee80211.h>
+#include <net/iw_handler.h>
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,6,0)
+#include <crypto/hash.h>
+#include <crypto/skcipher.h>
+#else
+#include <linux/crypto.h>
+#endif
+#include <linux/crc32.h>
+#include <net/lib80211.h>
+#include "sec.h"
+#define TKIP_HDR_LEN 8
+struct lib80211_tkip_data {
+    u8 key[TKIP_KEY_LEN];
+    int key_set;
+    u32 tx_iv32;
+    u16 tx_iv16;
+    u16 tx_ttak[5];
+    int tx_phase1_done;
+    u32 rx_iv32;
+    u16 rx_iv16;
+    u16 rx_ttak[5];
+    int rx_phase1_done;
+    u32 rx_iv32_new;
+    u16 rx_iv16_new;
+    u32 dot11RSNAStatsTKIPReplays;
+    u32 dot11RSNAStatsTKIPICVErrors;
+    u32 dot11RSNAStatsTKIPLocalMICFailures;
+    int key_idx;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,6,0)
+    struct crypto_skcipher *rx_tfm_arc4;
+    struct crypto_ahash *rx_tfm_michael;
+    struct crypto_skcipher *tx_tfm_arc4;
+    struct crypto_ahash *tx_tfm_michael;
+#else
+    struct crypto_blkcipher *rx_tfm_arc4;
+    struct crypto_hash *rx_tfm_michael;
+    struct crypto_blkcipher *tx_tfm_arc4;
+    struct crypto_hash *tx_tfm_michael;
+#endif
+    u8 rx_hdr[16], tx_hdr[16];
+    unsigned long flags;
+};
+static unsigned long lib80211_tkip_set_flags(unsigned long flags, void *priv)
+{
+    struct lib80211_tkip_data *_priv = priv;
+    unsigned long old_flags = _priv->flags;
+    _priv->flags = flags;
+    return old_flags;
+}
+static unsigned long lib80211_tkip_get_flags(void *priv)
+{
+    struct lib80211_tkip_data *_priv = priv;
+    return _priv->flags;
+}
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,6,0)
+static void *lib80211_tkip_init(int key_idx)
+{
+    struct lib80211_tkip_data *priv;
+    priv = kzalloc(sizeof(*priv), GFP_ATOMIC);
+    if (priv == NULL)
+        goto fail;
+    priv->key_idx = key_idx;
+    priv->tx_tfm_arc4 = crypto_alloc_skcipher("ecb(arc4)", 0,
+                        CRYPTO_ALG_ASYNC);
+    if (IS_ERR(priv->tx_tfm_arc4)) {
+        priv->tx_tfm_arc4 = NULL;
+        goto fail;
+    }
+    priv->tx_tfm_michael = crypto_alloc_ahash("michael_mic", 0,
+                           CRYPTO_ALG_ASYNC);
+    if (IS_ERR(priv->tx_tfm_michael)) {
+        priv->tx_tfm_michael = NULL;
+        goto fail;
+    }
+    priv->rx_tfm_arc4 = crypto_alloc_skcipher("ecb(arc4)", 0,
+                        CRYPTO_ALG_ASYNC);
+    if (IS_ERR(priv->rx_tfm_arc4)) {
+        priv->rx_tfm_arc4 = NULL;
+        goto fail;
+    }
+    priv->rx_tfm_michael = crypto_alloc_ahash("michael_mic", 0,
+                           CRYPTO_ALG_ASYNC);
+    if (IS_ERR(priv->rx_tfm_michael)) {
+        priv->rx_tfm_michael = NULL;
+        goto fail;
+    }
+    return priv;
+fail:
+    if (priv) {
+        crypto_free_ahash(priv->tx_tfm_michael);
+        crypto_free_skcipher(priv->tx_tfm_arc4);
+        crypto_free_ahash(priv->rx_tfm_michael);
+        crypto_free_skcipher(priv->rx_tfm_arc4);
+        kfree(priv);
+    }
+    return NULL;
+}
+#else
+static void *lib80211_tkip_init(int key_idx)
+{
+    struct lib80211_tkip_data *priv;
+    priv = kzalloc(sizeof(*priv), GFP_ATOMIC);
+    if (priv == NULL)
+        goto fail;
+    priv->key_idx = key_idx;
+    priv->tx_tfm_arc4 = crypto_alloc_blkcipher("ecb(arc4)", 0,
+                        CRYPTO_ALG_ASYNC);
+    if (IS_ERR(priv->tx_tfm_arc4)) {
+        priv->tx_tfm_arc4 = NULL;
+        goto fail;
+    }
+    priv->tx_tfm_michael = crypto_alloc_hash("michael_mic", 0,
+                           CRYPTO_ALG_ASYNC);
+    if (IS_ERR(priv->tx_tfm_michael)) {
+        priv->tx_tfm_michael = NULL;
+        goto fail;
+    }
+    priv->rx_tfm_arc4 = crypto_alloc_blkcipher("ecb(arc4)", 0,
+                        CRYPTO_ALG_ASYNC);
+    if (IS_ERR(priv->rx_tfm_arc4)) {
+        priv->rx_tfm_arc4 = NULL;
+        goto fail;
+    }
+    priv->rx_tfm_michael = crypto_alloc_hash("michael_mic", 0,
+                           CRYPTO_ALG_ASYNC);
+    if (IS_ERR(priv->rx_tfm_michael)) {
+        priv->rx_tfm_michael = NULL;
+        goto fail;
+    }
+    return priv;
+fail:
+    if (priv) {
+        if (priv->tx_tfm_michael)
+            crypto_free_hash(priv->tx_tfm_michael);
+        if (priv->tx_tfm_arc4)
+            crypto_free_blkcipher(priv->tx_tfm_arc4);
+        if (priv->rx_tfm_michael)
+            crypto_free_hash(priv->rx_tfm_michael);
+        if (priv->rx_tfm_arc4)
+            crypto_free_blkcipher(priv->rx_tfm_arc4);
+        kfree(priv);
+    }
+    return NULL;
+}
+#endif
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,6,0)
+static void lib80211_tkip_deinit(void *priv)
+{
+    struct lib80211_tkip_data *_priv = priv;
+    if (_priv) {
+        crypto_free_ahash(_priv->tx_tfm_michael);
+        crypto_free_skcipher(_priv->tx_tfm_arc4);
+        crypto_free_ahash(_priv->rx_tfm_michael);
+        crypto_free_skcipher(_priv->rx_tfm_arc4);
+    }
+    kfree(priv);
+}
+#else
+static void lib80211_tkip_deinit(void *priv)
+{
+    struct lib80211_tkip_data *_priv = priv;
+    if (_priv) {
+        if (_priv->tx_tfm_michael)
+            crypto_free_hash(_priv->tx_tfm_michael);
+        if (_priv->tx_tfm_arc4)
+            crypto_free_blkcipher(_priv->tx_tfm_arc4);
+        if (_priv->rx_tfm_michael)
+            crypto_free_hash(_priv->rx_tfm_michael);
+        if (_priv->rx_tfm_arc4)
+            crypto_free_blkcipher(_priv->rx_tfm_arc4);
+    }
+    kfree(priv);
+}
+#endif
+static inline u16 RotR1(u16 val)
+{
+    return (val >> 1) | (val << 15);
+}
+static inline u8 Lo8(u16 val)
+{
+    return val & 0xff;
+}
+static inline u8 Hi8(u16 val)
+{
+    return val >> 8;
+}
+static inline u16 Lo16(u32 val)
+{
+    return val & 0xffff;
+}
+static inline u16 Hi16(u32 val)
+{
+    return val >> 16;
+}
+static inline u16 Mk16(u8 hi, u8 lo)
+{
+    return lo | (((u16) hi) << 8);
+}
+static inline u16 Mk16_le(__le16 * v)
+{
+    return le16_to_cpu(*v);
+}
+static const u16 Sbox[256] = {
+    0xC6A5, 0xF884, 0xEE99, 0xF68D, 0xFF0D, 0xD6BD, 0xDEB1, 0x9154,
+    0x6050, 0x0203, 0xCEA9, 0x567D, 0xE719, 0xB562, 0x4DE6, 0xEC9A,
+    0x8F45, 0x1F9D, 0x8940, 0xFA87, 0xEF15, 0xB2EB, 0x8EC9, 0xFB0B,
+    0x41EC, 0xB367, 0x5FFD, 0x45EA, 0x23BF, 0x53F7, 0xE496, 0x9B5B,
+    0x75C2, 0xE11C, 0x3DAE, 0x4C6A, 0x6C5A, 0x7E41, 0xF502, 0x834F,
+    0x685C, 0x51F4, 0xD134, 0xF908, 0xE293, 0xAB73, 0x6253, 0x2A3F,
+    0x080C, 0x9552, 0x4665, 0x9D5E, 0x3028, 0x37A1, 0x0A0F, 0x2FB5,
+    0x0E09, 0x2436, 0x1B9B, 0xDF3D, 0xCD26, 0x4E69, 0x7FCD, 0xEA9F,
+    0x121B, 0x1D9E, 0x5874, 0x342E, 0x362D, 0xDCB2, 0xB4EE, 0x5BFB,
+    0xA4F6, 0x764D, 0xB761, 0x7DCE, 0x527B, 0xDD3E, 0x5E71, 0x1397,
+    0xA6F5, 0xB968, 0x0000, 0xC12C, 0x4060, 0xE31F, 0x79C8, 0xB6ED,
+    0xD4BE, 0x8D46, 0x67D9, 0x724B, 0x94DE, 0x98D4, 0xB0E8, 0x854A,
+    0xBB6B, 0xC52A, 0x4FE5, 0xED16, 0x86C5, 0x9AD7, 0x6655, 0x1194,
+    0x8ACF, 0xE910, 0x0406, 0xFE81, 0xA0F0, 0x7844, 0x25BA, 0x4BE3,
+    0xA2F3, 0x5DFE, 0x80C0, 0x058A, 0x3FAD, 0x21BC, 0x7048, 0xF104,
+    0x63DF, 0x77C1, 0xAF75, 0x4263, 0x2030, 0xE51A, 0xFD0E, 0xBF6D,
+    0x814C, 0x1814, 0x2635, 0xC32F, 0xBEE1, 0x35A2, 0x88CC, 0x2E39,
+    0x9357, 0x55F2, 0xFC82, 0x7A47, 0xC8AC, 0xBAE7, 0x322B, 0xE695,
+    0xC0A0, 0x1998, 0x9ED1, 0xA37F, 0x4466, 0x547E, 0x3BAB, 0x0B83,
+    0x8CCA, 0xC729, 0x6BD3, 0x283C, 0xA779, 0xBCE2, 0x161D, 0xAD76,
+    0xDB3B, 0x6456, 0x744E, 0x141E, 0x92DB, 0x0C0A, 0x486C, 0xB8E4,
+    0x9F5D, 0xBD6E, 0x43EF, 0xC4A6, 0x39A8, 0x31A4, 0xD337, 0xF28B,
+    0xD532, 0x8B43, 0x6E59, 0xDAB7, 0x018C, 0xB164, 0x9CD2, 0x49E0,
+    0xD8B4, 0xACFA, 0xF307, 0xCF25, 0xCAAF, 0xF48E, 0x47E9, 0x1018,
+    0x6FD5, 0xF088, 0x4A6F, 0x5C72, 0x3824, 0x57F1, 0x73C7, 0x9751,
+    0xCB23, 0xA17C, 0xE89C, 0x3E21, 0x96DD, 0x61DC, 0x0D86, 0x0F85,
+    0xE090, 0x7C42, 0x71C4, 0xCCAA, 0x90D8, 0x0605, 0xF701, 0x1C12,
+    0xC2A3, 0x6A5F, 0xAEF9, 0x69D0, 0x1791, 0x9958, 0x3A27, 0x27B9,
+    0xD938, 0xEB13, 0x2BB3, 0x2233, 0xD2BB, 0xA970, 0x0789, 0x33A7,
+    0x2DB6, 0x3C22, 0x1592, 0xC920, 0x8749, 0xAAFF, 0x5078, 0xA57A,
+    0x038F, 0x59F8, 0x0980, 0x1A17, 0x65DA, 0xD731, 0x84C6, 0xD0B8,
+    0x82C3, 0x29B0, 0x5A77, 0x1E11, 0x7BCB, 0xA8FC, 0x6DD6, 0x2C3A,
+};
+static inline u16 _S_(u16 v)
+{
+    u16 t = Sbox[Hi8(v)];
+    return Sbox[Lo8(v)] ^ ((t << 8) | (t >> 8));
+}
+#define PHASE1_LOOP_COUNT 8
+static void tkip_mixing_phase1(u16 * TTAK, const u8 * TK, const u8 * TA,
+                               u32 IV32)
+{
+    int i, j;
+    TTAK[0] = Lo16(IV32);
+    TTAK[1] = Hi16(IV32);
+    TTAK[2] = Mk16(TA[1], TA[0]);
+    TTAK[3] = Mk16(TA[3], TA[2]);
+    TTAK[4] = Mk16(TA[5], TA[4]);
+    for (i = 0; i < PHASE1_LOOP_COUNT; i++) {
+        j = 2 * (i & 1);
+        TTAK[0] += _S_(TTAK[4] ^ Mk16(TK[1 + j], TK[0 + j]));
+        TTAK[1] += _S_(TTAK[0] ^ Mk16(TK[5 + j], TK[4 + j]));
+        TTAK[2] += _S_(TTAK[1] ^ Mk16(TK[9 + j], TK[8 + j]));
+        TTAK[3] += _S_(TTAK[2] ^ Mk16(TK[13 + j], TK[12 + j]));
+        TTAK[4] += _S_(TTAK[3] ^ Mk16(TK[1 + j], TK[0 + j])) + i;
+    }
+}
+static void tkip_mixing_phase2(u8 * WEPSeed, const u8 * TK, const u16 * TTAK,
+                               u16 IV16)
+{
+    u16 *PPK = (u16 *) & WEPSeed[4];
+    PPK[0] = TTAK[0];
+    PPK[1] = TTAK[1];
+    PPK[2] = TTAK[2];
+    PPK[3] = TTAK[3];
+    PPK[4] = TTAK[4];
+    PPK[5] = TTAK[4] + IV16;
+    PPK[0] += _S_(PPK[5] ^ Mk16_le((__le16 *) & TK[0]));
+    PPK[1] += _S_(PPK[0] ^ Mk16_le((__le16 *) & TK[2]));
+    PPK[2] += _S_(PPK[1] ^ Mk16_le((__le16 *) & TK[4]));
+    PPK[3] += _S_(PPK[2] ^ Mk16_le((__le16 *) & TK[6]));
+    PPK[4] += _S_(PPK[3] ^ Mk16_le((__le16 *) & TK[8]));
+    PPK[5] += _S_(PPK[4] ^ Mk16_le((__le16 *) & TK[10]));
+    PPK[0] += RotR1(PPK[5] ^ Mk16_le((__le16 *) & TK[12]));
+    PPK[1] += RotR1(PPK[0] ^ Mk16_le((__le16 *) & TK[14]));
+    PPK[2] += RotR1(PPK[1]);
+    PPK[3] += RotR1(PPK[2]);
+    PPK[4] += RotR1(PPK[3]);
+    PPK[5] += RotR1(PPK[4]);
+    WEPSeed[0] = Hi8(IV16);
+    WEPSeed[1] = (Hi8(IV16) | 0x20) & 0x7F;
+    WEPSeed[2] = Lo8(IV16);
+    WEPSeed[3] = Lo8((PPK[5] ^ Mk16_le((__le16 *) & TK[0])) >> 1);
+#ifdef __BIG_ENDIAN
+    {
+        int i;
+        for (i = 0; i < 6; i++)
+            PPK[i] = (PPK[i] << 8) | (PPK[i] >> 8);
+    }
+#endif
+}
+static int lib80211_tkip_hdr(struct sk_buff *skb, int hdr_len,
+                             u8 * rc4key, int keylen, void *priv)
+{
+    struct lib80211_tkip_data *tkey = priv;
+    u8 *pos;
+    struct ieee80211_hdr *hdr;
+    hdr = (struct ieee80211_hdr *)skb->data;
+    if (skb_headroom(skb) < TKIP_HDR_LEN || skb->len < hdr_len)
+        return -1;
+    if (rc4key == NULL || keylen < 16)
+        return -1;
+    if (!tkey->tx_phase1_done) {
+        tkip_mixing_phase1(tkey->tx_ttak, tkey->key, hdr->addr2,
+                           tkey->tx_iv32);
+        tkey->tx_phase1_done = 1;
+    }
+    tkip_mixing_phase2(rc4key, tkey->key, tkey->tx_ttak, tkey->tx_iv16);
+    pos = skb_push(skb, TKIP_HDR_LEN);
+    memmove(pos, pos + TKIP_HDR_LEN, hdr_len);
+    pos += hdr_len;
+    *pos++ = *rc4key;
+    *pos++ = *(rc4key + 1);
+    *pos++ = *(rc4key + 2);
+    *pos++ = (tkey->key_idx << 6) | (1 << 5) ;
+    *pos++ = tkey->tx_iv32 & 0xff;
+    *pos++ = (tkey->tx_iv32 >> 8) & 0xff;
+    *pos++ = (tkey->tx_iv32 >> 16) & 0xff;
+    *pos++ = (tkey->tx_iv32 >> 24) & 0xff;
+    tkey->tx_iv16++;
+    if (tkey->tx_iv16 == 0) {
+        tkey->tx_phase1_done = 0;
+        tkey->tx_iv32++;
+    }
+    return TKIP_HDR_LEN;
+}
+static int lib80211_tkip_encrypt(struct sk_buff *skb, int hdr_len, void *priv)
+{
+    struct lib80211_tkip_data *tkey = priv;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,6,0)
+    SKCIPHER_REQUEST_ON_STACK(req, tkey->tx_tfm_arc4);
+    int err;
+#else
+    struct blkcipher_desc desc = { .tfm = tkey->tx_tfm_arc4 };
+#endif
+    int len;
+    u8 rc4key[16], *pos, *icv;
+    u32 crc;
+    struct scatterlist sg;
+    if (tkey->flags & IEEE80211_CRYPTO_TKIP_COUNTERMEASURES) {
+        if (net_ratelimit()) {
+            struct ieee80211_hdr *hdr =
+                (struct ieee80211_hdr *)skb->data;
+            printk(KERN_DEBUG ": TKIP countermeasures: dropped "
+                   "TX packet to %pM\n", hdr->addr1);
+        }
+        return -1;
+    }
+    if (skb_tailroom(skb) < 4 || skb->len < hdr_len)
+        return -1;
+    len = skb->len - hdr_len;
+    pos = skb->data + hdr_len;
+    if ((lib80211_tkip_hdr(skb, hdr_len, rc4key, 16, priv)) < 0)
+        return -1;
+    crc = ~crc32_le(~0, pos, len);
+    icv = skb_put(skb, 4);
+    icv[0] = crc;
+    icv[1] = crc >> 8;
+    icv[2] = crc >> 16;
+    icv[3] = crc >> 24;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,6,0)
+    crypto_skcipher_setkey(tkey->tx_tfm_arc4, rc4key, 16);
+    sg_init_one(&sg, pos, len + 4);
+    skcipher_request_set_tfm(req, tkey->tx_tfm_arc4);
+    skcipher_request_set_callback(req, 0, NULL, NULL);
+    skcipher_request_set_crypt(req, &sg, &sg, len + 4, NULL);
+    err = crypto_skcipher_encrypt(req);
+    skcipher_request_zero(req);
+    return err;
+#else
+    crypto_blkcipher_setkey(tkey->tx_tfm_arc4, rc4key, 16);
+    sg_init_one(&sg, pos, len + 4);
+    return crypto_blkcipher_encrypt(&desc, &sg, &sg, len + 4);
+#endif
+}
+static inline int tkip_replay_check(u32 iv32_n, u16 iv16_n,
+                                    u32 iv32_o, u16 iv16_o)
+{
+    if ((s32)iv32_n - (s32)iv32_o < 0 ||
+        (iv32_n == iv32_o && iv16_n <= iv16_o))
+        return 1;
+    return 0;
+}
+static int lib80211_tkip_decrypt(struct sk_buff *skb, int hdr_len, void *priv)
+{
+    struct lib80211_tkip_data *tkey = priv;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,6,0)
+    SKCIPHER_REQUEST_ON_STACK(req, tkey->rx_tfm_arc4);
+    int err;
+#else
+    struct blkcipher_desc desc = { .tfm = tkey->rx_tfm_arc4 };
+#endif
+    u8 rc4key[16];
+    u8 keyidx, *pos;
+    u32 iv32;
+    u16 iv16;
+    struct ieee80211_hdr *hdr;
+    u8 icv[4];
+    u32 crc;
+    struct scatterlist sg;
+    int plen;
+    hdr = (struct ieee80211_hdr *)skb->data;
+    if (tkey->flags & IEEE80211_CRYPTO_TKIP_COUNTERMEASURES) {
+        if (net_ratelimit()) {
+            printk(KERN_DEBUG ": TKIP countermeasures: dropped "
+                   "received packet from %pM\n", hdr->addr2);
+        }
+        return -1;
+    }
+    if (skb->len < hdr_len + TKIP_HDR_LEN + 4)
+        return -1;
+    pos = skb->data + hdr_len;
+    keyidx = pos[3];
+    if (!(keyidx & (1 << 5))) {
+        if (net_ratelimit()) {
+            printk(KERN_DEBUG "TKIP: received packet without ExtIV"
+                   " flag from %pM\n", hdr->addr2);
+        }
+        return -2;
+    }
+    keyidx >>= 6;
+    if (tkey->key_idx != keyidx) {
+        printk(KERN_DEBUG "TKIP: RX tkey->key_idx=%d frame "
+               "keyidx=%d priv=%p\n", tkey->key_idx, keyidx, priv);
+        return -6;
+    }
+    if (!tkey->key_set) {
+        if (net_ratelimit()) {
+            printk(KERN_DEBUG "TKIP: received packet from %pM"
+                   " with keyid=%d that does not have a configured"
+                   " key\n", hdr->addr2, keyidx);
+        }
+        return -3;
+    }
+    iv16 = (pos[0] << 8) | pos[2];
+    iv32 = pos[4] | (pos[5] << 8) | (pos[6] << 16) | (pos[7] << 24);
+    pos += TKIP_HDR_LEN;
+    if (tkip_replay_check(iv32, iv16, tkey->rx_iv32, tkey->rx_iv16)) {
+#ifdef CONFIG_LIB80211_DEBUG
+        if (net_ratelimit()) {
+            printk(KERN_DEBUG "TKIP: replay detected: STA=%pM"
+                   " previous TSC %08x%04x received TSC "
+                   "%08x%04x\n", hdr->addr2,
+                   tkey->rx_iv32, tkey->rx_iv16, iv32, iv16);
+        }
+#endif
+        tkey->dot11RSNAStatsTKIPReplays++;
+        return -4;
+    }
+    if (iv32 != tkey->rx_iv32 || !tkey->rx_phase1_done) {
+        tkip_mixing_phase1(tkey->rx_ttak, tkey->key, hdr->addr2, iv32);
+        tkey->rx_phase1_done = 1;
+    }
+    tkip_mixing_phase2(rc4key, tkey->key, tkey->rx_ttak, iv16);
+    plen = skb->len - hdr_len - 12;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,6,0)
+    crypto_skcipher_setkey(tkey->rx_tfm_arc4, rc4key, 16);
+    sg_init_one(&sg, pos, plen + 4);
+    skcipher_request_set_tfm(req, tkey->rx_tfm_arc4);
+    skcipher_request_set_callback(req, 0, NULL, NULL);
+    skcipher_request_set_crypt(req, &sg, &sg, plen + 4, NULL);
+    err = crypto_skcipher_decrypt(req);
+    skcipher_request_zero(req);
+    if (err) {
+#else
+    crypto_blkcipher_setkey(tkey->rx_tfm_arc4, rc4key, 16);
+    sg_init_one(&sg, pos, plen + 4);
+    if (crypto_blkcipher_decrypt(&desc, &sg, &sg, plen + 4)) {
+#endif
+        if (net_ratelimit()) {
+            printk(KERN_DEBUG ": TKIP: failed to decrypt "
+                   "received packet from %pM\n",
+                   hdr->addr2);
+        }
+        return -7;
+    }
+    crc = ~crc32_le(~0, pos, plen);
+    icv[0] = crc;
+    icv[1] = crc >> 8;
+    icv[2] = crc >> 16;
+    icv[3] = crc >> 24;
+    if (memcmp(icv, pos + plen, 4) != 0) {
+        if (iv32 != tkey->rx_iv32) {
+            tkey->rx_phase1_done = 0;
+        }
+#ifdef CONFIG_LIB80211_DEBUG
+        if (net_ratelimit()) {
+            printk(KERN_DEBUG "TKIP: ICV error detected: STA="
+                   "%pM\n", hdr->addr2);
+        }
+#endif
+        tkey->dot11RSNAStatsTKIPICVErrors++;
+        return -5;
+    }
+    tkey->rx_iv32_new = iv32;
+    tkey->rx_iv16_new = iv16;
+    memmove(skb->data + TKIP_HDR_LEN, skb->data, hdr_len);
+    skb_pull(skb, TKIP_HDR_LEN);
+    skb_trim(skb, skb->len - 4);
+    return keyidx;
+}
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,6,0)
+static int michael_mic(struct crypto_ahash *tfm_michael, u8 * key, u8 * hdr,
+                       u8 * data, size_t data_len, u8 * mic)
+{
+    AHASH_REQUEST_ON_STACK(req, tfm_michael);
+    struct scatterlist sg[2];
+    int err;
+    if (tfm_michael == NULL) {
+        pr_warn("%s(): tfm_michael == NULL\n", __func__);
+        return -1;
+    }
+    sg_init_table(sg, 2);
+    sg_set_buf(&sg[0], hdr, 16);
+    sg_set_buf(&sg[1], data, data_len);
+    if (crypto_ahash_setkey(tfm_michael, key, 8))
+        return -1;
+    ahash_request_set_tfm(req, tfm_michael);
+    ahash_request_set_callback(req, 0, NULL, NULL);
+    ahash_request_set_crypt(req, sg, mic, data_len + 16);
+    err = crypto_ahash_digest(req);
+    ahash_request_zero(req);
+    return err;
+}
+#else
+static int michael_mic(struct crypto_hash *tfm_michael, u8 * key, u8 * hdr,
+                       u8 * data, size_t data_len, u8 * mic)
+{
+    struct hash_desc desc;
+    struct scatterlist sg[2];
+    if (tfm_michael == NULL) {
+        pr_warn("%s(): tfm_michael == NULL\n", __func__);
+        return -1;
+    }
+    sg_init_table(sg, 2);
+    sg_set_buf(&sg[0], hdr, 16);
+    sg_set_buf(&sg[1], data, data_len);
+    if (crypto_hash_setkey(tfm_michael, key, 8))
+        return -1;
+    desc.tfm = tfm_michael;
+    desc.flags = 0;
+    return crypto_hash_digest(&desc, sg, data_len + 16, mic);
+}
+#endif
+static void michael_mic_hdr(struct sk_buff *skb, u8 * hdr)
+{
+    struct ieee80211_hdr *hdr11;
+    hdr11 = (struct ieee80211_hdr *)skb->data;
+    switch (le16_to_cpu(hdr11->frame_control) &
+            (IEEE80211_FCTL_FROMDS | IEEE80211_FCTL_TODS)) {
+    case IEEE80211_FCTL_TODS:
+        memcpy(hdr, hdr11->addr3, ETH_ALEN);
+        memcpy(hdr + ETH_ALEN, hdr11->addr2, ETH_ALEN);
+        break;
+    case IEEE80211_FCTL_FROMDS:
+        memcpy(hdr, hdr11->addr1, ETH_ALEN);
+        memcpy(hdr + ETH_ALEN, hdr11->addr3, ETH_ALEN);
+        break;
+    case IEEE80211_FCTL_FROMDS | IEEE80211_FCTL_TODS:
+        memcpy(hdr, hdr11->addr3, ETH_ALEN);
+        memcpy(hdr + ETH_ALEN, hdr11->addr4, ETH_ALEN);
+        break;
+    case 0:
+        memcpy(hdr, hdr11->addr1, ETH_ALEN);
+        memcpy(hdr + ETH_ALEN, hdr11->addr2, ETH_ALEN);
+        break;
+    }
+    if (ieee80211_is_data_qos(hdr11->frame_control)) {
+        hdr[12] = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(hdr11)))
+                  & IEEE80211_QOS_CTL_TID_MASK;
+    } else
+        hdr[12] = 0;
+    hdr[13] = hdr[14] = hdr[15] = 0;
+}
+static int lib80211_michael_mic_add(struct sk_buff *skb, int hdr_len,
+                                    void *priv)
+{
+    struct lib80211_tkip_data *tkey = priv;
+    u8 *pos;
+    if (skb_tailroom(skb) < 8 || skb->len < hdr_len) {
+        printk(KERN_DEBUG "Invalid packet for Michael MIC add "
+               "(tailroom=%d hdr_len=%d skb->len=%d)\n",
+               skb_tailroom(skb), hdr_len, skb->len);
+        return -1;
+    }
+    michael_mic_hdr(skb, tkey->tx_hdr);
+    pos = skb_put(skb, 8);
+    if (michael_mic(tkey->tx_tfm_michael, &tkey->key[16], tkey->tx_hdr,
+                    skb->data + hdr_len, skb->len - 8 - hdr_len, pos))
+        return -1;
+    return 0;
+}
+#ifdef CONFIG_WEXT_CORE
+static void lib80211_michael_mic_failure(struct net_device *dev,
+        struct ieee80211_hdr *hdr,
+        int keyidx)
+{
+    union iwreq_data wrqu;
+    struct iw_michaelmicfailure ev;
+    memset(&ev, 0, sizeof(ev));
+    ev.flags = keyidx & IW_MICFAILURE_KEY_ID;
+    if (hdr->addr1[0] & 0x01)
+        ev.flags |= IW_MICFAILURE_GROUP;
+    else
+        ev.flags |= IW_MICFAILURE_PAIRWISE;
+    ev.src_addr.sa_family = ARPHRD_ETHER;
+    memcpy(ev.src_addr.sa_data, hdr->addr2, ETH_ALEN);
+    memset(&wrqu, 0, sizeof(wrqu));
+    wrqu.data.length = sizeof(ev);
+    wireless_send_event(dev, IWEVMICHAELMICFAILURE, &wrqu, (char *)&ev);
+}
+#endif
+static int lib80211_michael_mic_verify(struct sk_buff *skb, int keyidx,
+                                       int hdr_len, void *priv)
+{
+    struct lib80211_tkip_data *tkey = priv;
+    u8 mic[8];
+    if (!tkey->key_set)
+        return -1;
+    michael_mic_hdr(skb, tkey->rx_hdr);
+    if (michael_mic(tkey->rx_tfm_michael, &tkey->key[24], tkey->rx_hdr,
+                    skb->data + hdr_len, skb->len - 8 - hdr_len, mic))
+        return -1;
+    if (memcmp(mic, skb->data + skb->len - 8, 8) != 0) {
+        struct ieee80211_hdr *hdr;
+        hdr = (struct ieee80211_hdr *)skb->data;
+        printk(KERN_DEBUG "%s: Michael MIC verification failed for "
+               "MSDU from %pM keyidx=%d\n",
+               skb->dev ? skb->dev->name : "N/A", hdr->addr2,
+               keyidx);
+#ifdef CONFIG_WEXT_CORE
+        if (skb->dev)
+            lib80211_michael_mic_failure(skb->dev, hdr, keyidx);
+#endif
+        tkey->dot11RSNAStatsTKIPLocalMICFailures++;
+        return -1;
+    }
+    tkey->rx_iv32 = tkey->rx_iv32_new;
+    tkey->rx_iv16 = tkey->rx_iv16_new;
+    skb_trim(skb, skb->len - 8);
+    return 0;
+}
+static int lib80211_tkip_set_key(void *key, int len, u8 * seq, void *priv)
+{
+    struct lib80211_tkip_data *tkey = priv;
+    int keyidx;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,6,0)
+    struct crypto_ahash *tfm = tkey->tx_tfm_michael;
+    struct crypto_skcipher *tfm2 = tkey->tx_tfm_arc4;
+    struct crypto_ahash *tfm3 = tkey->rx_tfm_michael;
+    struct crypto_skcipher *tfm4 = tkey->rx_tfm_arc4;
+#else
+    struct crypto_hash *tfm = tkey->tx_tfm_michael;
+    struct crypto_blkcipher *tfm2 = tkey->tx_tfm_arc4;
+    struct crypto_hash *tfm3 = tkey->rx_tfm_michael;
+    struct crypto_blkcipher *tfm4 = tkey->rx_tfm_arc4;
+#endif
+    keyidx = tkey->key_idx;
+    memset(tkey, 0, sizeof(*tkey));
+    tkey->key_idx = keyidx;
+    tkey->tx_tfm_michael = tfm;
+    tkey->tx_tfm_arc4 = tfm2;
+    tkey->rx_tfm_michael = tfm3;
+    tkey->rx_tfm_arc4 = tfm4;
+    if (len == TKIP_KEY_LEN) {
+        memcpy(tkey->key, key, TKIP_KEY_LEN);
+        tkey->key_set = 1;
+        tkey->tx_iv16 = 1;
+        if (seq) {
+            tkey->rx_iv32 = (seq[5] << 24) | (seq[4] << 16) |
+                            (seq[3] << 8) | seq[2];
+            tkey->rx_iv16 = (seq[1] << 8) | seq[0];
+        }
+    } else if (len == 0)
+        tkey->key_set = 0;
+    else
+        return -1;
+    return 0;
+}
+static int lib80211_tkip_get_key(void *key, int len, u8 * seq, void *priv)
+{
+    struct lib80211_tkip_data *tkey = priv;
+    if (len < TKIP_KEY_LEN)
+        return -1;
+    if (!tkey->key_set)
+        return 0;
+    memcpy(key, tkey->key, TKIP_KEY_LEN);
+    if (seq) {
+        u16 iv16 = tkey->tx_iv16;
+        u32 iv32 = tkey->tx_iv32;
+        if (iv16 == 0)
+            iv32--;
+        iv16--;
+        seq[0] = tkey->tx_iv16;
+        seq[1] = tkey->tx_iv16 >> 8;
+        seq[2] = tkey->tx_iv32;
+        seq[3] = tkey->tx_iv32 >> 8;
+        seq[4] = tkey->tx_iv32 >> 16;
+        seq[5] = tkey->tx_iv32 >> 24;
+    }
+    return TKIP_KEY_LEN;
+}
+static char *lib80211_tkip_print_stats(char *p, void *priv)
+{
+    struct lib80211_tkip_data *tkip = priv;
+    p += sprintf(p, "key[%d] alg=TKIP key_set=%d "
+                 "tx_pn=%02x%02x%02x%02x%02x%02x "
+                 "rx_pn=%02x%02x%02x%02x%02x%02x "
+                 "replays=%d icv_errors=%d local_mic_failures=%d\n",
+                 tkip->key_idx, tkip->key_set,
+                 (tkip->tx_iv32 >> 24) & 0xff,
+                 (tkip->tx_iv32 >> 16) & 0xff,
+                 (tkip->tx_iv32 >> 8) & 0xff,
+                 tkip->tx_iv32 & 0xff,
+                 (tkip->tx_iv16 >> 8) & 0xff,
+                 tkip->tx_iv16 & 0xff,
+                 (tkip->rx_iv32 >> 24) & 0xff,
+                 (tkip->rx_iv32 >> 16) & 0xff,
+                 (tkip->rx_iv32 >> 8) & 0xff,
+                 tkip->rx_iv32 & 0xff,
+                 (tkip->rx_iv16 >> 8) & 0xff,
+                 tkip->rx_iv16 & 0xff,
+                 tkip->dot11RSNAStatsTKIPReplays,
+                 tkip->dot11RSNAStatsTKIPICVErrors,
+                 tkip->dot11RSNAStatsTKIPLocalMICFailures);
+    return p;
+}
+static struct ssv_crypto_ops ssv_crypt_tkip = {
+    .name = "TKIP",
+    .init = lib80211_tkip_init,
+    .deinit = lib80211_tkip_deinit,
+    .encrypt_mpdu = lib80211_tkip_encrypt,
+    .decrypt_mpdu = lib80211_tkip_decrypt,
+    .encrypt_msdu = lib80211_michael_mic_add,
+    .decrypt_msdu = lib80211_michael_mic_verify,
+    .set_key = lib80211_tkip_set_key,
+    .get_key = lib80211_tkip_get_key,
+    .print_stats = lib80211_tkip_print_stats,
+    .extra_mpdu_prefix_len = 4 + 4,
+    .extra_mpdu_postfix_len = 4,
+    .extra_msdu_postfix_len = 8,
+    .get_flags = lib80211_tkip_get_flags,
+    .set_flags = lib80211_tkip_set_flags,
+#ifdef MULTI_THREAD_ENCRYPT
+    .encrypt_prepare = NULL,
+    .decrypt_prepare = NULL,
+#endif
+};
+struct ssv_crypto_ops *get_crypto_tkip_ops(void)
+{
+    return &ssv_crypt_tkip;
+}
diff --git a/drivers/net/wireless/ssv6x5x/smac/sec_wep.c b/drivers/net/wireless/ssv6x5x/smac/sec_wep.c
new file mode 100644
index 000000000..3dd0c487b
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/sec_wep.c
@@ -0,0 +1,217 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/version.h>
+#include <linux/err.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/random.h>
+#include <linux/scatterlist.h>
+#include <linux/skbuff.h>
+#include <linux/mm.h>
+#include <asm/string.h>
+#include <net/lib80211.h>
+#include <linux/crypto.h>
+#include <linux/crc32.h>
+#include "sec.h"
+struct lib80211_wep_data {
+    u32 iv;
+    u8 key[WEP_KEY_LEN + 1];
+    u8 key_len;
+    u8 key_idx;
+    struct crypto_blkcipher *tx_tfm;
+    struct crypto_blkcipher *rx_tfm;
+};
+static void *lib80211_wep_init (int keyidx)
+{
+    struct lib80211_wep_data *priv;
+    priv = kzalloc (sizeof (*priv), GFP_ATOMIC);
+    if (priv == NULL)
+        goto fail;
+    priv->key_idx = keyidx;
+    priv->tx_tfm = crypto_alloc_blkcipher ("ecb(arc4)", 0, CRYPTO_ALG_ASYNC);
+    if (IS_ERR (priv->tx_tfm)) {
+        priv->tx_tfm = NULL;
+        goto fail;
+    }
+    priv->rx_tfm = crypto_alloc_blkcipher ("ecb(arc4)", 0, CRYPTO_ALG_ASYNC);
+    if (IS_ERR (priv->rx_tfm)) {
+        priv->rx_tfm = NULL;
+        goto fail;
+    }
+    get_random_bytes (&priv->iv, 4);
+    return priv;
+fail:
+    if (priv) {
+        if (priv->tx_tfm)
+            crypto_free_blkcipher (priv->tx_tfm);
+        if (priv->rx_tfm)
+            crypto_free_blkcipher (priv->rx_tfm);
+        kfree (priv);
+    }
+    return NULL;
+}
+static void lib80211_wep_deinit (void *priv)
+{
+    struct lib80211_wep_data *_priv = priv;
+    if (_priv) {
+        if (_priv->tx_tfm)
+            crypto_free_blkcipher (_priv->tx_tfm);
+        if (_priv->rx_tfm)
+            crypto_free_blkcipher (_priv->rx_tfm);
+    }
+    kfree (priv);
+}
+static int lib80211_wep_build_iv (struct sk_buff *skb, int hdr_len,
+                                  u8 *key, int keylen, void *priv)
+{
+    struct lib80211_wep_data *wep = priv;
+    u32 klen;
+    u8 *pos;
+    if (skb_headroom (skb) < 4 || skb->len < hdr_len)
+        return -1;
+    pos = skb_push (skb, 4);
+    memmove (pos, pos + 4, hdr_len);
+    pos += hdr_len;
+    klen = 3 + wep->key_len;
+    wep->iv++;
+    if ((wep->iv & 0xff00) == 0xff00) {
+        u8 B = (wep->iv >> 16) & 0xff;
+        if (B >= 3 && B < klen)
+            wep->iv += 0x0100;
+    }
+    *pos++ = (wep->iv >> 16) & 0xff;
+    *pos++ = (wep->iv >> 8) & 0xff;
+    *pos++ = wep->iv & 0xff;
+    *pos++ = wep->key_idx << 6;
+    return 0;
+}
+static int lib80211_wep_encrypt (struct sk_buff *skb, int hdr_len, void *priv)
+{
+    struct lib80211_wep_data *wep = priv;
+    struct blkcipher_desc desc = {.tfm = wep->tx_tfm};
+    u32 crc, klen, len;
+    u8 *pos, *icv;
+    struct scatterlist sg;
+    u8 key[WEP_KEY_LEN + 3];
+    if (skb_tailroom (skb) < 4) {
+        printk("####%s: too few tailroom\n", __FUNCTION__);
+        return -1;
+    }
+    if (lib80211_wep_build_iv (skb, hdr_len, NULL, 0, priv)) {
+        printk("####%s: build iv failure\n", __FUNCTION__);
+        return -1;
+    }
+    skb_copy_from_linear_data_offset (skb, hdr_len, key, 3);
+    memcpy (key + 3, wep->key, wep->key_len);
+    len = skb->len - hdr_len - 4;
+    pos = skb->data + hdr_len + 4;
+    klen = 3 + wep->key_len;
+    crc = ~crc32_le (~0, pos, len);
+    icv = skb_put (skb, 4);
+    icv[0] = crc;
+    icv[1] = crc >> 8;
+    icv[2] = crc >> 16;
+    icv[3] = crc >> 24;
+    crypto_blkcipher_setkey (wep->tx_tfm, key, klen);
+    sg_init_one (&sg, pos, len + 4);
+    return crypto_blkcipher_encrypt (&desc, &sg, &sg, len + 4);
+}
+static int lib80211_wep_decrypt (struct sk_buff *skb, int hdr_len, void *priv)
+{
+    struct lib80211_wep_data *wep = priv;
+    struct blkcipher_desc desc = {.tfm = wep->rx_tfm};
+    u32 crc, klen, plen;
+    u8 key[WEP_KEY_LEN + 3];
+    u8 keyidx, *pos, icv[4], *pos2;
+    struct scatterlist sg;
+    if (skb->len < hdr_len + 8) {
+        printk ("%s::skb->len = %d\n", __FUNCTION__, skb->len);
+        return -1;
+    }
+    pos = skb->data + hdr_len;
+    key[0] = *pos++;
+    key[1] = *pos++;
+    key[2] = *pos++;
+    keyidx = *pos++ >> 6;
+    if (keyidx != wep->key_idx)
+        return -1;
+    klen = 3 + wep->key_len;
+    memcpy (key + 3, wep->key, wep->key_len);
+    plen = skb->len - hdr_len - 8;
+    crypto_blkcipher_setkey (wep->rx_tfm, key, klen);
+    sg_init_one (&sg, pos, plen + 4);
+    if (crypto_blkcipher_decrypt (&desc, &sg, &sg, plen + 4))
+        return -7;
+    crc = ~crc32_le (~0, pos, plen);
+    icv[0] = crc;
+    icv[1] = crc >> 8;
+    icv[2] = crc >> 16;
+    icv[3] = crc >> 24;
+    pos2 = (pos + plen);
+    if (memcmp (icv, pos + plen, 4) != 0) {
+        return -2;
+    }
+    memmove (skb->data + 4, skb->data, hdr_len);
+    skb_pull (skb, 4);
+    skb_trim (skb, skb->len - 4);
+    return 0;
+}
+static int lib80211_wep_set_key (void *key, int len, u8 * seq, void *priv)
+{
+    struct lib80211_wep_data *wep = priv;
+    if (len < 0 || len > WEP_KEY_LEN)
+        return -1;
+    memcpy (wep->key, key, len);
+    wep->key_len = len;
+    return 0;
+}
+static int lib80211_wep_get_key (void *key, int len, u8 * seq, void *priv)
+{
+    struct lib80211_wep_data *wep = priv;
+    if (len < wep->key_len)
+        return -1;
+    memcpy (key, wep->key, wep->key_len);
+    return wep->key_len;
+}
+static char *lib80211_wep_print_stats (char *p, void *priv)
+{
+    struct lib80211_wep_data *wep = priv;
+    p += sprintf (p, "key[%d] alg=WEP len=%d\n", wep->key_idx, wep->key_len);
+    return p;
+}
+static struct ssv_crypto_ops ssv_crypt_wep = {
+    .name = "WEP",
+    .init = lib80211_wep_init,
+    .deinit = lib80211_wep_deinit,
+    .encrypt_mpdu = lib80211_wep_encrypt,
+    .decrypt_mpdu = lib80211_wep_decrypt,
+    .encrypt_msdu = NULL,
+    .decrypt_msdu = NULL,
+    .set_key = lib80211_wep_set_key,
+    .get_key = lib80211_wep_get_key,
+    .print_stats = lib80211_wep_print_stats,
+    .extra_mpdu_prefix_len = 4,
+    .extra_mpdu_postfix_len = 4,
+#ifdef MULTI_THREAD_ENCRYPT
+    .encrypt_prepare = NULL,
+    .decrypt_prepare = NULL,
+#endif
+};
+struct ssv_crypto_ops *get_crypto_wep_ops (void)
+{
+    return &ssv_crypt_wep;
+}
diff --git a/drivers/net/wireless/ssv6x5x/smac/sec_wpi.c b/drivers/net/wireless/ssv6x5x/smac/sec_wpi.c
new file mode 100644
index 000000000..fe0d3450b
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/sec_wpi.c
@@ -0,0 +1,465 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/version.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <net/cfg80211.h>
+#ifdef SSV_MAC80211
+#include "ssv_mac80211.h"
+#else
+#include <net/mac80211.h>
+#endif
+#include <linux/etherdevice.h>
+#include "wapi_sms4.h"
+#include "sec_wpi.h"
+#include "sec.h"
+#define IWAPIELEMENT 68
+#define WID_WAPI_KEY 0x3033
+u8 g_wapi_oui[3] = {0x00,0x14,0x72};
+const u16 frame_cntl_mask = 0x8FC7;
+const u16 seq_cntl_mask = 0x0F00;
+struct lib80211_wpi_data {
+    TRUTH_VALUE_T wapi_enable;
+    TRUTH_VALUE_T wapi_key_ok;
+    u8 wapi_version[2];
+    u8 ap_address[ETH_ALEN];
+    u8 key_index;
+    u8 pn_key[WAPI_PN_LEN];
+    u8 pmsk_key[3][WAPI_PN_LEN];
+    u8 mic_key[3][WAPI_PN_LEN];
+};
+TRUTH_VALUE_T mget_wapi_key_ok(void *priv)
+{
+    struct lib80211_wpi_data *data = priv;
+    return data->wapi_key_ok;
+}
+void mset_wapi_key_ok(TRUTH_VALUE_T val, void *priv)
+{
+    struct lib80211_wpi_data *data = priv;
+    data->wapi_key_ok = val;
+}
+TRUTH_VALUE_T mget_wapi_enable(void *priv)
+{
+    struct lib80211_wpi_data *data = priv;
+    return data->wapi_enable;
+}
+void mset_wapi_enable(TRUTH_VALUE_T val, void *priv)
+{
+    struct lib80211_wpi_data *data = priv;
+    data->wapi_enable = val;
+}
+u8* mget_wapi_version(void *priv)
+{
+    struct lib80211_wpi_data *data = priv;
+    return data->wapi_version;
+}
+void mset_wapi_version(u8* val, void *priv)
+{
+    struct lib80211_wpi_data *data = priv;
+    memcpy(data->wapi_version,val,2);
+}
+u8* mget_wapi_address(void *priv)
+{
+    struct lib80211_wpi_data *data = priv;
+    return data->ap_address;
+}
+void mset_wapi_address(u8* val, void *priv)
+{
+    struct lib80211_wpi_data *data = priv;
+    memcpy(data->ap_address,val, ETH_ALEN);
+}
+u8 mget_key_index(void *priv)
+{
+    struct lib80211_wpi_data *data = priv;
+    return data->key_index;
+}
+void mset_key_index(int index, void *priv)
+{
+    struct lib80211_wpi_data *data = priv;
+    if(index <= 3 ) {
+        data->key_index = index;
+    }
+}
+u8* mget_pn_key(void *priv)
+{
+    struct lib80211_wpi_data *data = priv;
+    return data->pn_key;
+}
+void mset_pn_key(u8* val, void *priv)
+{
+    struct lib80211_wpi_data *data = priv;
+    memcpy(data->pn_key,val,WAPI_PN_LEN);
+}
+u8 *inc_pn_key(void *priv)
+{
+    struct lib80211_wpi_data *data = priv;
+    int i;
+    data->pn_key[15] += 2;
+    if( data->pn_key[15] == 0x00 ) {
+        for(i = 14 ; i >= 0 ; i--) {
+            if( (data->pn_key[i] += 1) != 0x00 ) {
+                break;
+            }
+        }
+    }
+    return data->pn_key;
+}
+u8 *mget_pmsk_key(int index, void *priv)
+{
+    struct lib80211_wpi_data *data = priv;
+    return ( index >= 3 ) ? NULL : data->pmsk_key[index];
+}
+void mset_pmsk_key(int index,u8* val, void *priv)
+{
+    struct lib80211_wpi_data *data = priv;
+    if(index < 3 ) {
+        memcpy(data->pmsk_key[index],val, WAPI_MIC_LEN);
+    }
+}
+u8* mget_mic_key(int index, void *priv)
+{
+    struct lib80211_wpi_data *data = priv;
+    return ( index >= 3 ) ? NULL : data->mic_key[index];
+}
+void mset_mic_key(int index,u8* val, void *priv)
+{
+    struct lib80211_wpi_data *data = priv;
+    if(index < 3 ) {
+        memcpy(data->mic_key[index],val,WAPI_MIC_LEN);
+    }
+}
+u16 wlan_tx_wapi_encryption(u8 * header,
+                            u8 * data,u16 data_len,
+                            u8 * mic_pos, void *priv)
+{
+    int i = 0;
+    u16 offset = 0;
+    BOOL_T qos_in = BFALSE;
+    BOOL_T valid_addr4 = BTRUE;
+    u8 ptk_header[36] = {0};
+    u16 ptk_headr_len = 32;
+    u8 *p_ptk_header = ptk_header;
+    u8 *data_mic = mic_pos;
+    u8 *iv = NULL;
+    u8 keyid = 0;
+    keyid = mget_key_index(priv);
+#ifdef MULTI_THREAD_ENCRYPT
+    iv = kzalloc(WAPI_PN_LEN, GFP_KERNEL);
+    memcpy(iv, data + WAPI_KEYID_LEN + WAPI_RESERVD_LEN, WAPI_PN_LEN);
+    data_len -= WAPI_IV_LEN;
+#else
+    iv = inc_pn_key(priv);
+#endif
+    *data = keyid;
+    *(data + 1) = 0x00;
+    data += 2;
+    for( i = 15 ; i >= 0 ; i-- ) {
+        *data = iv[i];
+        data++;
+    }
+    *p_ptk_header = header[offset] & (frame_cntl_mask >> 8);
+    *(p_ptk_header + 1) = header[offset + 1] & (frame_cntl_mask & 0xFF);
+    if(*p_ptk_header & 0x80) {
+        qos_in = BTRUE;
+        ptk_headr_len += 2;
+    }
+    if((*(p_ptk_header + 1) & 0x03 ) != 0x03) {
+        valid_addr4 = BFALSE;
+    }
+    p_ptk_header += 2;
+    offset += 2;
+    offset += 2;
+    memcpy(p_ptk_header, &header[offset], ADDID_LEN);
+    p_ptk_header += ADDID_LEN;
+    offset += ADDID_LEN;
+    *p_ptk_header = header[offset + ETH_ALEN] & (seq_cntl_mask >> 8);
+    *(p_ptk_header + 1) = header[offset + ETH_ALEN + 1] & (seq_cntl_mask & 0xFF);
+    p_ptk_header += 2;
+    memcpy(p_ptk_header, &header[offset], ETH_ALEN);
+    p_ptk_header += ETH_ALEN;
+    offset += ETH_ALEN;
+    offset += 2;
+    if(valid_addr4) {
+        memcpy(p_ptk_header, &header[offset], ETH_ALEN);
+        p_ptk_header += ETH_ALEN;
+        offset += ETH_ALEN;
+    } else {
+        memset(p_ptk_header,0x00, ETH_ALEN);
+        p_ptk_header += ETH_ALEN;
+    }
+    if(qos_in) {
+        memcpy(p_ptk_header, &header[offset], 2);
+        p_ptk_header += 2;
+        offset += 2;
+    }
+    *p_ptk_header = keyid;
+    p_ptk_header++;
+    *p_ptk_header = 0x00;
+    p_ptk_header++;
+    *p_ptk_header = (data_len >> 8);
+    *(p_ptk_header+1) = data_len & 0xFF;
+    WapiCryptoSms4Mic(iv,
+                      mget_mic_key(keyid, priv),
+                      ptk_header, ptk_headr_len, data, data_len, data_mic);
+    data_len += WAPI_MIC_LEN;
+    WapiCryptoSms4(iv,
+                   mget_pmsk_key(keyid, priv),
+                   data, data_len,
+                   data);
+#ifdef MULTI_THREAD_ENCRYPT
+    kfree(iv);
+#endif
+    return data_len + WAPI_IV_LEN;
+}
+BOOL_T is_group(u8* addr)
+{
+    if((addr[0] & BIT(0)) != 0)
+        return BTRUE;
+    return BFALSE;
+}
+u16 wlan_rx_wapi_decryption(u8 * input_ptk,u16 header_len,u16 data_len,
+                            u8 * output_buf, void *priv)
+{
+    u16 offset = 0;
+    BOOL_T qos_in = BFALSE;
+    BOOL_T valid_addr4 = BTRUE;
+    BOOL_T is_group_ptk = BFALSE;
+    u8 ptk_header[36] = {0};
+    u16 ptk_headr_len = 32;
+    u8 * p_ptk_header = ptk_header;
+    u8 data_mic[WAPI_MIC_LEN] = {0};
+    u8 calc_data_mic[WAPI_MIC_LEN] = {0};
+    u8 iv[WAPI_PN_LEN] = {0};
+    u8 keyid = {0};
+    u16 ral_data_len = 0;
+    u16 encryp_data_len = 0;
+    int i = 0;
+    *p_ptk_header = input_ptk[offset] & (frame_cntl_mask >> 8);
+    *(p_ptk_header+1) = input_ptk[offset+1] & (frame_cntl_mask & 0xFF);
+    if(*p_ptk_header & 0x80) {
+        qos_in = BTRUE;
+        ptk_headr_len += 2;
+    }
+    if((*(p_ptk_header+1) & 0x03 ) != 0x03) {
+        valid_addr4 = BFALSE;
+    }
+    p_ptk_header += 2;
+    offset += 2;
+    offset += 2;
+    memcpy(p_ptk_header, &input_ptk[offset], ADDID_LEN);
+    is_group_ptk = is_group(p_ptk_header);
+    p_ptk_header += ADDID_LEN;
+    offset += ADDID_LEN;
+    *p_ptk_header = input_ptk[offset+6] & (seq_cntl_mask >> 8);
+    *(p_ptk_header+1) = input_ptk[offset+6+1] & (seq_cntl_mask & 0xFF);
+    p_ptk_header += 2;
+    memcpy(p_ptk_header, &input_ptk[offset], ETH_ALEN);
+    p_ptk_header += ETH_ALEN;
+    offset += ETH_ALEN;
+    offset += 2;
+    if(valid_addr4) {
+        memcpy(p_ptk_header, &input_ptk[offset], ETH_ALEN);
+        p_ptk_header += ETH_ALEN;
+        offset += ETH_ALEN;
+    } else {
+        memset(p_ptk_header, 0x00, ETH_ALEN);
+        p_ptk_header += ETH_ALEN;
+    }
+    if(qos_in) {
+        memcpy(p_ptk_header,&input_ptk[offset], 2);
+        p_ptk_header += 2;
+        offset += 2;
+    }
+    *p_ptk_header = input_ptk[offset];
+    keyid = input_ptk[offset];
+    p_ptk_header++;
+    offset++;
+    *p_ptk_header = input_ptk[offset];
+    p_ptk_header++;
+    offset++;
+    encryp_data_len = data_len - WAPI_IV_LEN;
+    ral_data_len = data_len - WAPI_IV_LEN - WAPI_MIC_LEN;
+    *p_ptk_header = (ral_data_len >> 8);
+    *(p_ptk_header+1) = ral_data_len & 0xFF;
+    for( i = 15 ; i >= 0 ; i-- ) {
+        iv[i] = input_ptk[offset];
+        offset++;
+    }
+    if(is_group_ptk) {
+        printk("%s, is_group_ptk\n", __func__);
+    } else {
+        if( (iv[15] & 0x01) != 0x01 ) {
+            printk(KERN_ALERT "decry pairwise error,iv[15]=%x\n", iv[15]);
+            return 0;
+        }
+    }
+    WapiCryptoSms4(iv,
+                   mget_pmsk_key(keyid, priv),
+                   (input_ptk + header_len + WAPI_IV_LEN), encryp_data_len,
+                   output_buf);
+    memcpy(data_mic, output_buf + ral_data_len, WAPI_MIC_LEN);
+    WapiCryptoSms4Mic(iv,
+                      mget_mic_key(keyid, priv),
+                      ptk_header, ptk_headr_len,
+                      (output_buf), ral_data_len,
+                      calc_data_mic);
+    if( memcmp(calc_data_mic, data_mic, WAPI_MIC_LEN) != 0 ) {
+        printk(KERN_ALERT "calc_data_mic != data_mic\n");
+        return 0;
+    } else {
+        return ral_data_len;
+    }
+}
+int lib80211_wpi_encrypt(struct sk_buff *mpdu, int hdr_len, void *priv)
+{
+    struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)mpdu->data;
+    u8 *pos, *mic_pos;
+    int hdrlen = 0, len = 0, out_len = 0;
+    u8 *pdata = NULL;
+#ifdef MULTI_THREAD_ENCRYPT
+    u32 wapi_iv_icv_offset = WAPI_IV_ICV_OFFSET - WAPI_IV_LEN;
+#else
+    u32 wapi_iv_icv_offset = WAPI_IV_ICV_OFFSET;
+#endif
+    hdrlen = ieee80211_hdrlen(hdr->frame_control);
+    pdata = (mpdu->data) + hdrlen;
+    if (mpdu->protocol != cpu_to_be16(0x88b4)) {
+        if (WARN_ON(skb_headroom(mpdu) < wapi_iv_icv_offset)) {
+            printk("[I] skb_headroom(skb) < %d\n", wapi_iv_icv_offset);
+            return 0;
+        }
+        len = mpdu->len - hdrlen;
+        pos = skb_push(mpdu, wapi_iv_icv_offset);
+#ifdef MULTI_THREAD_ENCRYPT
+        memmove(pos, pos + wapi_iv_icv_offset, mpdu->len - WAPI_MIC_LEN);
+#else
+        memmove(pos, pos + wapi_iv_icv_offset, hdrlen);
+        memmove(pos + hdrlen + WAPI_IV_LEN, pos + wapi_iv_icv_offset + hdrlen, len);
+#endif
+        hdr = (struct ieee80211_hdr *)pos;
+        pos += hdrlen;
+        mic_pos = mpdu->data + mpdu->len - WAPI_MIC_LEN;
+        out_len = wlan_tx_wapi_encryption((u8 *)hdr, pos, len, mic_pos, priv);
+    } else {
+        if (ieee80211_has_protected(hdr->frame_control))
+            hdr->frame_control &= ~(cpu_to_le16(IEEE80211_FCTL_PROTECTED));
+        printk("[I] send WAPI WAI data pkt\n");
+    }
+    return 1;
+}
+int lib80211_wpi_decrypt(struct sk_buff *rx_skb, int hdr_len, void *priv)
+{
+    struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(rx_skb->data);
+    int hdrlen, len, dcry_len;
+    char *pdata = NULL;
+    int ret = 0;
+    hdrlen = ieee80211_hdrlen(hdr->frame_control);
+    pdata = ((char*)(rx_skb->data)) + hdrlen;
+    len = rx_skb->len - hdrlen;
+    dcry_len = wlan_rx_wapi_decryption((u8 *)rx_skb->data, hdrlen, len, pdata, priv);
+    if (dcry_len) {
+        skb_trim(rx_skb, hdrlen + dcry_len);
+        hdr->frame_control &= ~(cpu_to_le16(IEEE80211_FCTL_PROTECTED));
+        ret = dcry_len;
+    }
+    return ret;
+}
+void *lib80211_wpi_init(int key_idx)
+{
+    struct lib80211_wpi_data *priv;
+    priv = kzalloc(sizeof(*priv), GFP_ATOMIC);
+    if (priv == NULL) {
+        printk("allocate lib80211_wpi_data failed\n");
+        return NULL;
+    }
+    priv->key_index = key_idx;
+    return priv;
+}
+void lib80211_wpi_deinit(void *priv)
+{
+    if (priv) {
+        printk("%s\n", __func__);
+        kfree(priv);
+        priv = NULL;
+    } else
+        printk("%s, passing NULL lib80211_wpi_data?\n", __func__);
+}
+#ifdef MULTI_THREAD_ENCRYPT
+int lib80211_wpi_encrypt_prepare(struct sk_buff *mpdu, int hdr_len, void *priv)
+{
+    struct lib80211_wpi_data *data = priv;
+    u8 *pos = NULL;
+    unsigned char *iv = NULL;
+    if (mpdu->protocol != cpu_to_be16(0x88b4) &&
+        (skb_headroom(mpdu) >= WAPI_IV_LEN)) {
+        pos = skb_push(mpdu, WAPI_IV_LEN);
+        memmove(pos, pos + WAPI_IV_LEN, hdr_len);
+        pos += hdr_len;
+        *pos = data->key_index;
+        pos++;
+        *pos = 0x00;
+        pos++;
+        iv = inc_pn_key(priv);
+        memcpy(pos, iv, WAPI_PN_LEN);
+        return 0;
+    }
+    printk("%s, pass through\n", __func__);
+    return 0;
+}
+#endif
+int lib80211_wpi_set_key(void *key, int len, u8 *seq, void *priv)
+{
+    struct lib80211_wpi_data *data = priv;
+    int keyidx = data->key_index;
+    u8 WapiASUEPNInitialValueSrc[16] = {
+        0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36,
+        0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36
+    };
+    printk("%s\n", __func__);
+    mset_key_index(keyidx, priv);
+    mset_pn_key(WapiASUEPNInitialValueSrc, priv);
+    mset_pmsk_key(keyidx, key, priv);
+    mset_mic_key(keyidx, key + WAPI_PN_LEN, priv);
+    if (seq) {
+        memcpy(data->ap_address, (u8 *)seq, ETH_ALEN);
+        printk("%s: set ap_address %pM\n", __func__, data->ap_address);
+    }
+    mset_wapi_key_ok(TV_TRUE, priv);
+    return 0;
+}
+static struct ssv_crypto_ops ssv_crypto_wpi = {
+    .name = "WPI",
+    .init = lib80211_wpi_init,
+    .deinit = lib80211_wpi_deinit,
+    .encrypt_mpdu = lib80211_wpi_encrypt,
+    .decrypt_mpdu = lib80211_wpi_decrypt,
+    .encrypt_msdu = NULL,
+    .decrypt_msdu = NULL,
+    .set_tx_pn = NULL,
+    .set_key = lib80211_wpi_set_key,
+    .get_key = NULL,
+    .print_stats = NULL,
+    .extra_mpdu_prefix_len = WAPI_IV_LEN,
+    .extra_mpdu_postfix_len = WAPI_MIC_LEN,
+#ifdef MULTI_THREAD_ENCRYPT
+    .encrypt_prepare = lib80211_wpi_encrypt_prepare,
+    .decrypt_prepare = NULL,
+#endif
+};
+struct ssv_crypto_ops *get_crypto_wpi_ops(void)
+{
+    return &ssv_crypto_wpi;
+}
diff --git a/drivers/net/wireless/ssv6x5x/smac/sec_wpi.h b/drivers/net/wireless/ssv6x5x/smac/sec_wpi.h
new file mode 100644
index 000000000..798b64be2
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/sec_wpi.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef WAPI_WPI_H
+#define WAPI_WPI_H
+#define WAPI_KEYID_LEN 1
+#define WAPI_RESERVD_LEN 1
+#define WAPI_PN_LEN 16
+#define WAPI_IV_LEN (WAPI_KEYID_LEN + WAPI_RESERVD_LEN + WAPI_PN_LEN)
+#define WAPI_MIC_LEN 16
+#define ADDID_LEN (ETH_ALEN + ETH_ALEN)
+#define WAPI_IV_ICV_OFFSET (WAPI_IV_LEN + WAPI_MIC_LEN)
+typedef enum {BFALSE = 0,
+              BTRUE = 1
+             } BOOL_T;
+typedef enum {TV_TRUE = 1,
+              TV_FALSE = 2
+             } TRUTH_VALUE_T;
+int lib80211_wpi_set_key(void *key, int len, u8 *seq, void *priv);
+int lib80211_wpi_encrypt(struct sk_buff *mpdu, int hdr_len, void *priv);
+int lib80211_wpi_decrypt(struct sk_buff *mpdu, int hdr_len, void *priv);
+void *lib80211_wpi_init(int key_idx);
+void lib80211_wpi_deinit(void *priv);
+#ifdef MULTI_THREAD_ENCRYPT
+int lib80211_wpi_encrypt_prepare(struct sk_buff *mpdu, int hdr_len, void *priv);
+#endif
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smac/ssv6xxx_debugfs.c b/drivers/net/wireless/ssv6x5x/smac/ssv6xxx_debugfs.c
new file mode 100644
index 000000000..c76385083
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/ssv6xxx_debugfs.c
@@ -0,0 +1,209 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/nl80211.h>
+#include <linux/etherdevice.h>
+#include <linux/delay.h>
+#include <linux/version.h>
+#include <linux/time.h>
+#ifdef SSV_MAC80211
+#include "ssv_mac80211.h"
+#else
+#include <net/mac80211.h>
+#endif
+#include <ssv6200.h>
+#include "dev.h"
+#include "ssv6xxx_debugfs.h"
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+#define QUEUE_STATUS_BUF_SIZE (4096)
+static ssize_t queue_status_read (struct file *file,
+                                  char __user *user_buf, size_t count,
+                                  loff_t *ppos)
+{
+    struct ssv_softc *sc = (struct ssv_softc *)file->private_data;
+    char *status_buf = kzalloc(QUEUE_STATUS_BUF_SIZE, GFP_KERNEL);
+    ssize_t status_size;
+    ssize_t ret;
+    if (!status_buf)
+        return -ENOMEM;
+    status_size = ssv6xxx_tx_queue_status_dump(sc, status_buf,
+                  QUEUE_STATUS_BUF_SIZE);
+    ret = simple_read_from_buffer(user_buf, count, ppos, status_buf,
+                                  status_size);
+    kfree(status_buf);
+    return ret;
+}
+static int queue_status_open (struct inode *inode, struct file *file)
+{
+    file->private_data = inode->i_private;
+    return 0;
+}
+static const struct file_operations queue_status_fops
+    = { .read = queue_status_read,
+    .open = queue_status_open
+};
+#endif
+int tu_ssv6xxx_init_debugfs (struct ssv_softc *sc, const char *name)
+{
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+    struct ieee80211_hw *hw = sc->hw;
+    struct dentry *phy_debugfs_dir = hw->wiphy->debugfsdir;
+    struct dentry *drv_debugfs_dir;
+    drv_debugfs_dir = debugfs_create_dir(name, phy_debugfs_dir);
+    if (!drv_debugfs_dir) {
+        dev_err(sc->dev, "Failed to create debugfs.\n");
+        return -ENOMEM;
+    }
+    sc->debugfs_dir = drv_debugfs_dir;
+    sc->sh->hci.hci_ops->hci_init_debugfs(sc->sh->hci.hci_ctrl, sc->debugfs_dir);
+    debugfs_create_file("queue_status", 00444, drv_debugfs_dir,
+                        sc, &queue_status_fops);
+#endif
+    return 0;
+}
+void ssv6xxx_deinit_debugfs (struct ssv_softc *sc)
+{
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+    if (!sc->debugfs_dir)
+        return;
+    sc->sh->hci.hci_ops->hci_deinit_debugfs(sc->sh->hci.hci_ctrl);
+    debugfs_remove_recursive(sc->debugfs_dir);
+    sc->debugfs_dir = NULL;
+#endif
+}
+int ssv6xxx_debugfs_add_interface(struct ssv_softc *sc, struct ieee80211_vif *vif)
+{
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+    struct dentry *drv_debugfs_dir = sc->debugfs_dir;
+    struct dentry *vif_debugfs_dir;
+    char vif_addr[18];
+    struct ssv_vif_priv_data *vif_priv = (struct ssv_vif_priv_data *)vif->drv_priv;
+    struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
+    snprintf(vif_addr, sizeof(vif_addr), "%02X-%02X-%02X-%02X-%02X-%02X",
+             vif->addr[0], vif->addr[1], vif->addr[2],
+             vif->addr[3], vif->addr[4], vif->addr[5]);
+    vif_debugfs_dir = debugfs_create_dir(vif_addr, drv_debugfs_dir);
+    if (!vif_debugfs_dir) {
+        dev_err(sc->dev, "Failed to create interface debugfs for %s.\n", vif_addr);
+        return -ENOMEM;
+    }
+    sc->debugfs_dir = drv_debugfs_dir;
+    vif_info->debugfs_dir = vif_debugfs_dir;
+#endif
+    return 0;
+}
+int ssv6xxx_debugfs_remove_interface(struct ssv_softc *sc, struct ieee80211_vif *vif)
+{
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+    struct ssv_vif_priv_data *vif_priv = (struct ssv_vif_priv_data *)vif->drv_priv;
+    struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
+    if ((vif_info->debugfs_dir == NULL) || (sc->debugfs_dir == NULL))
+        return 0;
+    debugfs_remove_recursive(vif_info->debugfs_dir);
+    vif_info->debugfs_dir = NULL;
+#endif
+    return 0;
+}
+int ssv6xxx_debugfs_remove_sta(struct ssv_softc *sc, struct ssv_sta_info *sta)
+{
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+    struct ssv_vif_priv_data *vif_priv = (struct ssv_vif_priv_data *)sta->vif->drv_priv;
+    struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
+    if ((sc->debugfs_dir == NULL) || (vif_info->debugfs_dir == NULL) || (sta->debugfs_dir == NULL))
+        return 0;
+    debugfs_remove_recursive(sta->debugfs_dir);
+    sta->debugfs_dir = NULL;
+#endif
+    return 0;
+}
+int ssv6xxx_debugfs_add_sta(struct ssv_softc *sc, struct ssv_sta_info *sta)
+{
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+    struct ssv_vif_priv_data *vif_priv = (struct ssv_vif_priv_data *)sta->vif->drv_priv;
+    struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
+    struct dentry *vif_debugfs_dir = vif_info->debugfs_dir;
+    struct dentry *sta_debugfs_dir;
+    char sta_addr[18];
+    if (vif_debugfs_dir == NULL)
+        return 0;
+    snprintf(sta_addr, sizeof(sta_addr), "%02X-%02X-%02X-%02X-%02X-%02X",
+             sta->sta->addr[0], sta->sta->addr[1], sta->sta->addr[2],
+             sta->sta->addr[3], sta->sta->addr[4], sta->sta->addr[5]);
+    sta_debugfs_dir = debugfs_create_dir(sta_addr, vif_debugfs_dir);
+    if (!sta_debugfs_dir) {
+        dev_err(sc->dev, "Failed to create interface debugfs for %s.\n", sta_addr);
+        return -ENOMEM;
+    }
+    sta->debugfs_dir = sta_debugfs_dir;
+#endif
+    return 0;
+}
+#define DEBUGFS_ADD_FILE(name,parent,mode) do { \
+    if (!debugfs_create_file(#name, mode, parent, priv, \
+                 &ssv_dbgfs_##name##_ops)) \
+        goto err; \
+} while (0)
+#define DEBUGFS_ADD_BOOL(name,parent,ptr) do { \
+    struct dentry *__tmp; \
+    __tmp = debugfs_create_bool(#name, S_IWUSR | S_IRUSR, \
+                    parent, ptr); \
+    if (IS_ERR(__tmp) || !__tmp) \
+        goto err; \
+} while (0)
+#define DEBUGFS_ADD_X32(name,parent,ptr) do { \
+    struct dentry *__tmp; \
+    __tmp = debugfs_create_x32(#name, S_IWUSR | S_IRUSR, \
+                   parent, ptr); \
+    if (IS_ERR(__tmp) || !__tmp) \
+        goto err; \
+} while (0)
+#define DEBUGFS_ADD_U32(name,parent,ptr,mode) do { \
+    struct dentry *__tmp; \
+    __tmp = debugfs_create_u32(#name, mode, \
+                   parent, ptr); \
+    if (IS_ERR(__tmp) || !__tmp) \
+        goto err; \
+} while (0)
+#define DEBUGFS_READ_FUNC(name) \
+static ssize_t ssv_dbgfs_##name##_read(struct file *file, \
+                    char __user *user_buf, \
+                    size_t count, loff_t *ppos);
+#define DEBUGFS_WRITE_FUNC(name) \
+static ssize_t ssv_dbgfs_##name##_write(struct file *file, \
+                    const char __user *user_buf, \
+                    size_t count, loff_t *ppos);
+#define DEBUGFS_READ_FILE_OPS(name) \
+    DEBUGFS_READ_FUNC(name); \
+static const struct file_operations ssv_dbgfs_##name##_ops = { \
+    .read = ssv_dbgfs_##name##_read, \
+    .open = ssv_dbgfs_open_file_generic, \
+    .llseek = generic_file_llseek, \
+};
+#define DEBUGFS_WRITE_FILE_OPS(name) \
+    DEBUGFS_WRITE_FUNC(name); \
+static const struct file_operations ssv_dbgfs_##name##_ops = { \
+    .write = ssv_dbgfs_##name##_write, \
+    .open = ssv_dbgfs_open_file_generic, \
+    .llseek = generic_file_llseek, \
+};
+#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
+    DEBUGFS_READ_FUNC(name); \
+    DEBUGFS_WRITE_FUNC(name); \
+static const struct file_operations ssv_dbgfs_##name##_ops = { \
+    .write = ssv_dbgfs_##name##_write, \
+    .read = ssv_dbgfs_##name##_read, \
+    .open = ssv_dbgfs_open_file_generic, \
+    .llseek = generic_file_llseek, \
+};
diff --git a/drivers/net/wireless/ssv6x5x/smac/ssv6xxx_debugfs.h b/drivers/net/wireless/ssv6x5x/smac/ssv6xxx_debugfs.h
new file mode 100644
index 000000000..1f0b284ec
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/ssv6xxx_debugfs.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __SSV6XXX_DBGFS_H__
+#define __SSV6XXX_DBGFS_H__
+int tu_ssv6xxx_init_debugfs (struct ssv_softc *sc, const char *name);
+void ssv6xxx_deinit_debugfs (struct ssv_softc *sc);
+int ssv6xxx_debugfs_remove_interface(struct ssv_softc *sc, struct ieee80211_vif *vif);
+int ssv6xxx_debugfs_add_interface(struct ssv_softc *sc, struct ieee80211_vif *vif);
+int ssv6xxx_debugfs_remove_sta(struct ssv_softc *sc, struct ssv_sta_info *sta);
+int ssv6xxx_debugfs_add_sta(struct ssv_softc *sc, struct ssv_sta_info *sta);
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smac/ssv_cli.h b/drivers/net/wireless/ssv6x5x/smac/ssv_cli.h
new file mode 100644
index 000000000..de8ef2164
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/ssv_cli.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __SSV_CLI_H__
+#define __SSV_CLI_H__
+struct ssv_cmd_data;
+int ssv_init_cli (const char *dev_name, struct ssv_cmd_data *cmd_data);
+int ssv_deinit_cli (const char *dev_name, struct ssv_cmd_data *cmd_data);
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smac/ssv_ht_rc.c b/drivers/net/wireless/ssv6x5x/smac/ssv_ht_rc.c
new file mode 100644
index 000000000..d7a9f97d2
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/ssv_ht_rc.c
@@ -0,0 +1,617 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/version.h>
+#include <ssv6200.h>
+#include "dev.h"
+#include "ssv_ht_rc.h"
+#include "ssv_rc.h"
+#include "ssv_skb.h"
+#define SAMPLE_COUNT 4
+#define HT_CW_MIN 15
+#define HT_SEGMENT_SIZE 6000
+#define AVG_PKT_SIZE 12000
+#define SAMPLE_COLUMNS 10
+#define EWMA_LEVEL 75
+#define MCS_NBITS (AVG_PKT_SIZE << 3)
+#define MCS_NSYMS(bps) ((MCS_NBITS + (bps) - 1) / (bps))
+#define MCS_SYMBOL_TIME(sgi,syms) \
+    (sgi ? \
+      ((syms) * 18 + 4) / 5 : \
+      (syms) << 2 \
+    )
+#define MCS_DURATION(streams,sgi,bps) MCS_SYMBOL_TIME(sgi, MCS_NSYMS((streams) * (bps)))
+#define MCS_GROUP(_streams,_sgi,_ht40) { \
+    .duration = { \
+        MCS_DURATION(_streams, _sgi, _ht40 ? 54 : 26), \
+        MCS_DURATION(_streams, _sgi, _ht40 ? 108 : 52), \
+        MCS_DURATION(_streams, _sgi, _ht40 ? 162 : 78), \
+        MCS_DURATION(_streams, _sgi, _ht40 ? 216 : 104), \
+        MCS_DURATION(_streams, _sgi, _ht40 ? 324 : 156), \
+        MCS_DURATION(_streams, _sgi, _ht40 ? 432 : 208), \
+        MCS_DURATION(_streams, _sgi, _ht40 ? 486 : 234), \
+        MCS_DURATION(_streams, _sgi, _ht40 ? 540 : 260) \
+    } \
+}
+const struct mcs_group minstrel_mcs_groups[] = {
+    MCS_GROUP(1, 0, 0),
+    MCS_GROUP(1, 1, 0),
+};
+static u8 sample_table[SAMPLE_COLUMNS][MCS_GROUP_RATES];
+static int minstrel_ewma(int old, int new, int weight)
+{
+    return (new * (100 - weight) + old * weight) / 100;
+}
+static inline struct minstrel_rate_stats *minstrel_get_ratestats(struct ssv62xx_ht *mi, int index)
+{
+    return &mi->groups.rates[index % MCS_GROUP_RATES];
+}
+static void minstrel_calc_rate_ewma(struct minstrel_rate_stats *mr)
+{
+    if (unlikely(mr->attempts > 0)) {
+        mr->sample_skipped = 0;
+        mr->cur_prob = MINSTREL_FRAC(mr->success, mr->attempts);
+        if (!mr->att_hist)
+            mr->probability = mr->cur_prob;
+        else
+            mr->probability = minstrel_ewma(mr->probability,
+                                            mr->cur_prob, EWMA_LEVEL);
+        mr->att_hist += mr->attempts;
+        mr->succ_hist += mr->success;
+    } else {
+        mr->sample_skipped++;
+    }
+    mr->last_success = mr->success;
+    mr->last_attempts = mr->attempts;
+    mr->success = 0;
+    mr->attempts = 0;
+}
+static void minstrel_ht_calc_tp(struct ssv62xx_ht *mi, struct ssv_sta_rc_info *rc_sta, int rate)
+{
+    struct minstrel_rate_stats *mr;
+    unsigned int usecs,group_id;
+    if(rc_sta->ht_rc_type == RC_TYPE_HT_LGI_20)
+        group_id = 0;
+    else
+        group_id = 1;
+    mr = &mi->groups.rates[rate];
+    if (mr->probability < MINSTREL_FRAC(1, 10)) {
+        mr->cur_tp = 0;
+        return;
+    }
+    usecs = mi->overhead / MINSTREL_TRUNC(mi->avg_ampdu_len);
+    usecs += minstrel_mcs_groups[group_id].duration[rate];
+    mr->cur_tp = MINSTREL_TRUNC((1000000 / usecs) * mr->probability);
+}
+static void rate_control_ht_sample(struct ssv62xx_ht *mi,struct ssv_sta_rc_info *rc_sta)
+{
+    struct minstrel_mcs_group_data *mg;
+    struct minstrel_rate_stats *mr;
+    int cur_prob, cur_prob_tp, cur_tp, cur_tp2;
+    int i, index;
+    if (mi->ampdu_packets > 0) {
+        mi->avg_ampdu_len = minstrel_ewma(mi->avg_ampdu_len,
+                                          MINSTREL_FRAC(mi->ampdu_len, mi->ampdu_packets), EWMA_LEVEL);
+        mi->ampdu_len = 0;
+        mi->ampdu_packets = 0;
+    } else
+        return;
+    mi->sample_slow = 0;
+    mi->sample_count = 0;
+    {
+        cur_prob = 0;
+        cur_prob_tp = 0;
+        cur_tp = 0;
+        cur_tp2 = 0;
+        mg = &mi->groups;
+        mg->max_tp_rate = 0;
+        mg->max_tp_rate2 = 0;
+        mg->max_prob_rate = 0;
+        for (i = 0; i < MCS_GROUP_RATES; i++) {
+            if (!(rc_sta->ht_supp_rates & BIT(i)))
+                continue;
+            mr = &mg->rates[i];
+            index = i;
+            minstrel_calc_rate_ewma(mr);
+            minstrel_ht_calc_tp(mi, rc_sta, i);
+#ifdef RATE_CONTROL_HT_PARAMETER_DEBUG
+            if(mr->cur_prob)
+                printk("rate[%d]probability[%08d]cur_prob[%08d]TP[%04d]\n",i,mr->probability,mr->cur_prob,mr->cur_tp);
+#endif
+#ifdef RATE_CONTROL_HT_STUPID_DEBUG
+            printk("HT sample result max_tp_rate[%d]max_tp_rate2[%d]max_prob_rate[%d]\n",mg->max_tp_rate,mg->max_tp_rate2,mg->max_prob_rate);
+            printk("rate[%d]probability[%08d]TP[%d]\n",i,mr->probability,mr->cur_tp);
+#endif
+            if (!mr->cur_tp)
+                continue;
+#ifdef RATE_CONTROL_HT_STUPID_DEBUG
+            printk("HT--1 mr->cur_tp[%d]cur_prob_tp[%d]\n",mr->cur_tp,cur_prob_tp);
+#endif
+            if ((mr->cur_tp > cur_prob_tp && mr->probability >
+                 MINSTREL_FRAC(3, 4)) || mr->probability > cur_prob) {
+                mg->max_prob_rate = index;
+                cur_prob = mr->probability;
+                cur_prob_tp = mr->cur_tp;
+            }
+#ifdef RATE_CONTROL_HT_STUPID_DEBUG
+            printk("HT--2 mr->cur_tp[%d]cur_tp[%d]\n",mr->cur_tp,cur_tp);
+#endif
+            if (mr->cur_tp > cur_tp) {
+                swap(index, mg->max_tp_rate);
+                cur_tp = mr->cur_tp;
+                mr = minstrel_get_ratestats(mi, index);
+            }
+#ifdef RATE_CONTROL_HT_STUPID_DEBUG
+            if(index != i)
+                printk("HT--3 index[%d]i[%d]mg->max_tp_rate[%d]\n",index,i,mg->max_tp_rate);
+#endif
+            if (index >= mg->max_tp_rate)
+                continue;
+#ifdef RATE_CONTROL_HT_STUPID_DEBUG
+            if(index != i)
+                printk("HT--4 mr->cur_tp[%d]cur_tp2[%d]\n",mr->cur_tp,cur_tp2);
+#endif
+            if (mr->cur_tp > cur_tp2) {
+                mg->max_tp_rate2 = index;
+                cur_tp2 = mr->cur_tp;
+            }
+        }
+    }
+    mi->sample_count = SAMPLE_COUNT;
+#if 0
+    cur_prob = 0;
+    cur_prob_tp = 0;
+    cur_tp = 0;
+    cur_tp2 = 0;
+    {
+        mg = &mi->groups;
+        mr = minstrel_get_ratestats(mi, mg->max_prob_rate);
+        if (cur_prob_tp < mr->cur_tp) {
+            mi->max_prob_rate = mg->max_prob_rate;
+            cur_prob = mr->cur_prob;
+            cur_prob_tp = mr->cur_tp;
+        }
+        mr = minstrel_get_ratestats(mi, mg->max_tp_rate);
+        if (cur_tp < mr->cur_tp) {
+            mi->max_tp_rate2 = mi->max_tp_rate;
+            cur_tp2 = cur_tp;
+            mi->max_tp_rate = mg->max_tp_rate;
+            cur_tp = mr->cur_tp;
+        }
+        mr = minstrel_get_ratestats(mi, mg->max_tp_rate2);
+        if (cur_tp2 < mr->cur_tp) {
+            mi->max_tp_rate2 = mg->max_tp_rate2;
+            cur_tp2 = mr->cur_tp;
+        }
+    }
+#else
+    mi->max_tp_rate = mg->max_tp_rate;
+    mi->max_tp_rate2 = mg->max_tp_rate2;
+    mi->max_prob_rate = mg->max_prob_rate;
+#endif
+#ifdef RATE_CONTROL_HT_STUPID_DEBUG
+    printk("HT sample result max_tp_rate[%d]max_tp_rate2[%d]max_prob_rate[%d]\n",mi->max_tp_rate,mi->max_tp_rate2,mi->max_prob_rate);
+#endif
+    mi->stats_update = jiffies;
+}
+#if 0
+static void minstrel_calc_retransmit(struct ssv62xx_ht *mi,int index, struct ssv_sta_rc_info *rc_sta)
+{
+    struct minstrel_rate_stats *mr;
+    const struct mcs_group *group;
+    unsigned int tx_time, tx_time_rtscts, tx_time_data;
+    unsigned int cw = HT_CW_MIN;
+    unsigned int cw_max = 1023;
+    unsigned int ctime = 0;
+    unsigned int t_slot = 9;
+    unsigned int ampdu_len = MINSTREL_TRUNC(mi->avg_ampdu_len);
+    unsigned int group_id;
+    if(rc_sta->ht_rc_type == RC_TYPE_HT_LGI_20)
+        group_id = 0;
+    else
+        group_id = 1;
+    mr = minstrel_get_ratestats(mi, index);
+    if (mr->probability < MINSTREL_FRAC(1, 10)) {
+        mr->retry_count = 1;
+        mr->retry_count_rtscts = 1;
+        return;
+    }
+    mr->retry_count = 2;
+    mr->retry_count_rtscts = 2;
+    mr->retry_updated = true;
+    group = &minstrel_mcs_groups[group_id];
+    tx_time_data = group->duration[index % MCS_GROUP_RATES] * ampdu_len;
+    ctime = (t_slot * cw) >> 1;
+    cw = min((cw << 1) | 1, cw_max);
+    ctime += (t_slot * cw) >> 1;
+    cw = min((cw << 1) | 1, cw_max);
+    tx_time = ctime + 2 * (mi->overhead + tx_time_data);
+    tx_time_rtscts = ctime + 2 * (mi->overhead_rtscts + tx_time_data);
+    do {
+        ctime = (t_slot * cw) >> 1;
+        cw = min((cw << 1) | 1, cw_max);
+        tx_time += ctime + mi->overhead + tx_time_data;
+        tx_time_rtscts += ctime + mi->overhead_rtscts + tx_time_data;
+        if (tx_time_rtscts < HT_SEGMENT_SIZE)
+            mr->retry_count_rtscts++;
+    } while ((tx_time < HT_SEGMENT_SIZE) &&
+             (++mr->retry_count < HW_MAX_RATE_TRIES));
+}
+#endif
+static void minstrel_ht_set_rate(struct ssv62xx_ht *mi,
+                                 struct fw_rc_retry_params *rate, int index,
+                                 bool sample, bool rtscts, struct ssv_sta_rc_info *rc_sta,
+                                 struct ssv_rate_ctrl *ssv_rc)
+{
+    struct minstrel_rate_stats *mr;
+    mr = minstrel_get_ratestats(mi, index);
+#if 0
+    if (!mr->retry_updated)
+        minstrel_calc_retransmit(mi, index, rc_sta);
+    if (sample)
+        rate->count = 1;
+    else if (mr->probability < MINSTREL_FRAC(20, 100))
+        rate->count = 2;
+    else if (rtscts)
+        rate->count = mr->retry_count_rtscts;
+    else
+        rate->count = mr->retry_count;
+#endif
+    rate->drate = ssv_rc->rc_table[mr->rc_index].hw_rate_idx;
+    rate->crate = ssv_rc->rc_table[mr->rc_index].ctrl_rate_idx;
+}
+static inline int minstrel_get_duration(int index, struct ssv_sta_rc_info *rc_sta)
+{
+    unsigned int group_id;
+    const struct mcs_group *group;
+    if(rc_sta->ht_rc_type == RC_TYPE_HT_LGI_20)
+        group_id = 0;
+    else
+        group_id = 1;
+    group = &minstrel_mcs_groups[group_id];
+    return group->duration[index % MCS_GROUP_RATES];
+}
+static void minstrel_next_sample_idx(struct ssv62xx_ht *mi)
+{
+    struct minstrel_mcs_group_data *mg;
+    for (;;) {
+        mg = &mi->groups;
+        if (++mg->index >= MCS_GROUP_RATES) {
+            mg->index = 0;
+            if (++mg->column >= ARRAY_SIZE(sample_table))
+                mg->column = 0;
+        }
+        break;
+    }
+}
+static int minstrel_get_sample_rate(struct ssv62xx_ht *mi, struct ssv_sta_rc_info *rc_sta)
+{
+    struct minstrel_rate_stats *mr;
+    struct minstrel_mcs_group_data *mg;
+    int sample_idx = 0;
+    if (mi->sample_wait > 0) {
+        mi->sample_wait--;
+        return -1;
+    }
+    if (!mi->sample_tries)
+        return -1;
+    mi->sample_tries--;
+    mg = &mi->groups;
+    sample_idx = sample_table[mg->column][mg->index];
+    mr = &mg->rates[sample_idx];
+    minstrel_next_sample_idx(mi);
+    if (minstrel_get_duration(sample_idx, rc_sta) >
+        minstrel_get_duration(mi->max_tp_rate, rc_sta)) {
+        if (mr->sample_skipped < 20) {
+            return -1;
+        }
+        if (mi->sample_slow++ > 2) {
+            return -1;
+        }
+    }
+    return sample_idx;
+}
+static void _fill_txinfo_rates (struct ssv_rate_ctrl *ssv_rc, struct sk_buff *skb, struct fw_rc_retry_params *ar)
+{
+    struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
+    info->control.rates[0].idx = ssv_rc->rc_table[ar[0].drate].dot11_rate_idx;
+    info->control.rates[0].count = 1;
+    info->control.rates[SSV_DRATE_IDX].count = ar[0].drate;
+    info->control.rates[SSV_CRATE_IDX].count = ar[0].crate;
+}
+extern const u16 ssv6xxx_rc_rate_set[RC_TYPE_MAX][13];
+s32 ssv62xx_ht_rate_update(struct sk_buff *skb, struct ssv_softc *sc, struct fw_rc_retry_params *ar)
+{
+    struct ssv_rate_ctrl *ssv_rc = sc->rc;
+    struct SKB_info_st *skb_info = (struct SKB_info_st *)skb->head;
+    struct ieee80211_sta *sta = skb_info->sta;
+    struct ssv62xx_ht *mi = NULL;
+    int sample_idx;
+    bool sample = false;
+    struct ssv_sta_rc_info *rc_sta;
+    struct ssv_sta_priv_data *sta_priv;
+    struct rc_pid_sta_info *spinfo;
+    int ret = 0;
+    if (sc->sc_flags & SC_OP_FIXED_RATE) {
+        ar[0].count = 3;
+        ar[0].drate = ssv_rc->rc_table[sc->max_rate_idx].hw_rate_idx;
+        ar[0].crate = ssv_rc->rc_table[sc->max_rate_idx].ctrl_rate_idx;
+        ar[1].count = 2;
+        ar[1].drate = ssv_rc->rc_table[sc->max_rate_idx].hw_rate_idx;
+        ar[1].crate = ssv_rc->rc_table[sc->max_rate_idx].ctrl_rate_idx;
+        ar[2].count = 2;
+        ar[2].drate = ssv_rc->rc_table[sc->max_rate_idx].hw_rate_idx;
+        ar[2].crate = ssv_rc->rc_table[sc->max_rate_idx].ctrl_rate_idx;
+        _fill_txinfo_rates(ssv_rc, skb, ar);
+        return ssv_rc->rc_table[sc->max_rate_idx].hw_rate_idx;
+    }
+    if(sta == NULL) {
+        printk("@Q@...station NULL\n");
+        BUG_ON(1);
+    }
+    sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+    rc_sta = &ssv_rc->sta_rc_info[sta_priv->rc_idx];
+    spinfo= &rc_sta->spinfo;
+#if 0
+    if ((rc_sta->rc_wsid >= SSV_RC_MAX_HARDWARE_SUPPORT) || (rc_sta->rc_wsid < 0)) {
+        struct ssv_sta_priv_data *ssv_sta_priv;
+        int rateidx=99;
+        ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+        {
+            if ((rc_sta->ht_rc_type >= RC_TYPE_HT_SGI_20) &&
+                (ssv_sta_priv->rx_data_rate < SSV62XX_RATE_MCS_INDEX)) {
+                if(ssv6xxx_rc_rate_set[rc_sta->ht_rc_type][0] == 12)
+                    rateidx = (int)rc_sta->pinfo.rinfo[4].rc_index;
+                else
+                    rateidx = (int)rc_sta->pinfo.rinfo[0].rc_index;
+#if 0
+                printk("RC %d rx %d tx %d\n", ssv_sta_priv->sta_idx,
+                       ssv_sta_priv->rx_data_rate, rateidx);
+#endif
+            } else {
+                rateidx = (int)ssv_sta_priv->rx_data_rate;
+                rateidx -= SSV62XX_RATE_MCS_INDEX;
+                rateidx %= 8;
+                if(rc_sta->ht_rc_type == RC_TYPE_HT_SGI_20)
+                    rateidx += SSV62XX_RATE_MCS_SGI_INDEX;
+                else if(rc_sta->ht_rc_type == RC_TYPE_HT_LGI_20)
+                    rateidx += SSV62XX_RATE_MCS_LGI_INDEX;
+                else
+                    rateidx += SSV62XX_RATE_MCS_GREENFIELD_INDEX;
+            }
+        }
+        ar[0].count = 3;
+        ar[2].drate = ar[1].drate = ar[0].drate = ssv_rc->rc_table[rateidx].hw_rate_idx;
+        ar[2].crate = ar[1].crate = ar[0].crate = ssv_rc->rc_table[rateidx].ctrl_rate_idx;
+        ar[1].count = 2;
+        ar[2].count = 2;
+        _fill_txinfo_rates(ssv_rc, skb, ar);
+        return rateidx;
+    }
+#endif
+    mi = &rc_sta->ht;
+    sample_idx = minstrel_get_sample_rate(mi, rc_sta);
+    if (sample_idx >= 0) {
+        sample = true;
+        minstrel_ht_set_rate(mi, &ar[0], sample_idx,
+                             true, false, rc_sta, ssv_rc);
+    } else {
+        minstrel_ht_set_rate(mi, &ar[0], mi->max_tp_rate,
+                             false, false, rc_sta, ssv_rc);
+    }
+    ar[0].count = mi->first_try_count;
+    ret = ar[0].drate;
+    {
+        if (sample_idx >= 0)
+            minstrel_ht_set_rate(mi, &ar[1], mi->max_tp_rate,
+                                 false, false, rc_sta, ssv_rc);
+        else
+            minstrel_ht_set_rate(mi, &ar[1], mi->max_tp_rate2,
+                                 false, true, rc_sta, ssv_rc);
+        ar[1].count = mi->second_try_count;
+        if(ret > ar[1].drate)
+            ret = ar[1].drate;
+        minstrel_ht_set_rate(mi, &ar[2], mi->max_prob_rate,
+                             false, !sample, rc_sta, ssv_rc);
+        ar[2].count = mi->other_try_count;
+        if(ret > ar[2].drate)
+            ret = ar[2].drate;
+    }
+    mi->total_packets++;
+    if (mi->total_packets == ~0) {
+        mi->total_packets = 0;
+        mi->sample_packets = 0;
+    }
+    if(spinfo->real_hw_index < SSV62XX_RATE_MCS_INDEX)
+        return spinfo->real_hw_index;
+    _fill_txinfo_rates(ssv_rc, skb, ar);
+    return ret;
+}
+static void init_sample_table(void)
+{
+    int col, i, new_idx;
+    u8 rnd[MCS_GROUP_RATES];
+    memset(sample_table, 0xff, sizeof(sample_table));
+    for (col = 0; col < SAMPLE_COLUMNS; col++) {
+        for (i = 0; i < MCS_GROUP_RATES; i++) {
+            get_random_bytes(rnd, sizeof(rnd));
+            new_idx = (i + rnd[i]) % MCS_GROUP_RATES;
+            while (sample_table[col][new_idx] != 0xff)
+                new_idx = (new_idx + 1) % MCS_GROUP_RATES;
+            sample_table[col][new_idx] = i;
+        }
+    }
+}
+void ssv62xx_ht_rc_caps(const u16 ssv6xxx_rc_rate_set[RC_TYPE_MAX][13],struct ssv_sta_rc_info *rc_sta)
+{
+    struct ssv62xx_ht *mi = &rc_sta->ht;
+    int ack_dur;
+    int i;
+#if 1
+    unsigned int group_id;
+    if(rc_sta->ht_rc_type == RC_TYPE_HT_LGI_20)
+        group_id = 0;
+    else
+        group_id = 1;
+    for (i = 0; i < MCS_GROUP_RATES; i++) {
+        printk("[RC]HT duration[%d][%d]\n",i,minstrel_mcs_groups[group_id].duration[i]);
+    }
+#endif
+    init_sample_table();
+    memset(mi, 0, sizeof(*mi));
+    mi->stats_update = jiffies;
+    ack_dur = pide_frame_duration( 10, 60, 0, 0);
+    mi->overhead = pide_frame_duration( 0, 60, 0, 0) + ack_dur;
+    mi->overhead_rtscts = mi->overhead + 2 * ack_dur;
+    mi->avg_ampdu_len = MINSTREL_FRAC(1, 1);
+    mi->sample_count = 16;
+    mi->sample_wait = 0;
+    mi->sample_tries = 4;
+#ifdef DISABLE_RATE_CONTROL_SAMPLE
+    mi->max_tp_rate = MCS_GROUP_RATES - 1;
+    mi->max_tp_rate2 = MCS_GROUP_RATES - 1;
+    mi->max_prob_rate = MCS_GROUP_RATES - 1;
+#endif
+#if (HW_MAX_RATE_TRIES == 7)
+    {
+        mi->first_try_count = 3;
+        mi->second_try_count = 2;
+        mi->other_try_count = 2;
+    }
+#else
+    {
+        mi->first_try_count = 2;
+        mi->second_try_count = 1;
+        mi->other_try_count = 1;
+    }
+#endif
+    for (i = 0; i < MCS_GROUP_RATES; i++) {
+        mi->groups.rates[i].rc_index = ssv6xxx_rc_rate_set[rc_sta->ht_rc_type][i+1];
+    }
+}
+static bool minstrel_ht_txstat_valid(struct ssv62xx_tx_rate *rate)
+{
+    if (!rate->count)
+        return false;
+    if (rate->data_rate < 0)
+        return false;
+    return true;
+}
+void ssv6xxx_ht_report_handler(struct ssv_softc *sc,struct sk_buff *skb,struct ssv_sta_rc_info *rc_sta)
+{
+    struct cfg_host_event *host_event;
+    struct firmware_rate_control_report_data *report_data;
+    struct ssv62xx_ht *mi;
+    struct minstrel_rate_stats *rate;
+    bool last = false;
+    int i = 0;
+    u16 report_ampdu_packets = 0;
+    unsigned long period;
+    host_event = (struct cfg_host_event *)skb->data;
+    report_data = (struct firmware_rate_control_report_data *)&host_event->dat[0];
+    if(host_event->h_event == SOC_EVT_RC_AMPDU_REPORT) {
+#if 0
+        printk("SC HT AMPDU wsid[%d]ampdu_len[%d]ampdu_ack_len[%d]\n",report_data->wsid,report_data->ampdu_len,report_data->ampdu_ack_len);
+        for (i = 0; i < SSV62XX_TX_MAX_RATES ; i++) {
+            if(report_data->rates[i].data_rate == -1)
+                break;
+            if(report_data->rates[i].count == 0) {
+                printk("*********************************\n");
+                printk("       Illegal HT report         \n");
+                printk("*********************************\n");
+            }
+            printk("        i=[%d] rate[%d] count[%d]\n",i,report_data->rates[i].data_rate,report_data->rates[i].count);
+        }
+#endif
+        report_ampdu_packets = 1;
+    } else if(host_event->h_event == SOC_EVT_RC_MPDU_REPORT) {
+        report_data->ampdu_len = 1;
+        report_ampdu_packets = report_data->ampdu_len;
+#if 0
+        printk("SC MPDU wsid[%d]ampdu_len[%d]ampdu_ack_len[%d]\n",report_data->wsid,report_data->ampdu_len,report_data->ampdu_ack_len);
+        for (i = 0; i < SSV62XX_TX_MAX_RATES ; i++) {
+            if(report_data->rates[i].data_rate == -1)
+                break;
+            if(report_data->rates[i].count == 0) {
+                printk("*********************************\n");
+                printk("       Illegal MPDU report       \n");
+                printk("*********************************\n");
+            }
+            printk("        i=[%d] rate[%d] count[%d]\n",i,report_data->rates[i].data_rate,report_data->rates[i].count);
+        }
+#endif
+    } else {
+        printk("RC work get garbage!!\n");
+        return;
+    }
+    mi = &rc_sta->ht;
+    mi->ampdu_packets += report_ampdu_packets;
+    mi->ampdu_len += report_data->ampdu_len;
+    if (!mi->sample_wait && !mi->sample_tries && mi->sample_count > 0) {
+        mi->sample_wait = 16 + 2 * MINSTREL_TRUNC(mi->avg_ampdu_len);
+        mi->sample_tries = 2;
+        mi->sample_count--;
+    }
+    for (i = 0; !last; i++) {
+        last = (i == SSV62XX_TX_MAX_RATES - 1) ||
+               !minstrel_ht_txstat_valid(&report_data->rates[i+1]);
+        if (!minstrel_ht_txstat_valid(&report_data->rates[i]))
+            break;
+#ifdef RATE_CONTROL_DEBUG
+        if((report_data->rates[i].data_rate < SSV62XX_RATE_MCS_INDEX) || (report_data->rates[i].data_rate >= SSV62XX_RATE_MCS_GREENFIELD_INDEX)) {
+            printk("[RC]ssv6xxx_ht_report_handler get error report rate[%d]\n",report_data->rates[i].data_rate);
+            break;
+        }
+#endif
+        rate = &mi->groups.rates[(report_data->rates[i].data_rate - SSV62XX_RATE_MCS_INDEX) % MCS_GROUP_RATES];
+        if (last)
+            rate->success += report_data->ampdu_ack_len;
+        rate->attempts += report_data->rates[i].count * report_data->ampdu_len;
+    }
+#if 0
+    rate = minstrel_get_ratestats(mi, mi->max_tp_rate);
+    if (rate->attempts > 30 &&
+        MINSTREL_FRAC(rate->success, rate->attempts) <
+        MINSTREL_FRAC(20, 100))
+        minstrel_downgrade_rate(mi, &mi->max_tp_rate, true);
+    rate2 = minstrel_get_ratestats(mi, mi->max_tp_rate2);
+    if (rate2->attempts > 30 &&
+        MINSTREL_FRAC(rate2->success, rate2->attempts) <
+        MINSTREL_FRAC(20, 100))
+        minstrel_downgrade_rate(mi, &mi->max_tp_rate2, false);
+#endif
+    period = msecs_to_jiffies(SSV_RC_HT_INTERVAL/2);
+    if (time_after(jiffies, mi->stats_update + period)) {
+        rate_control_ht_sample(mi,rc_sta);
+    }
+#if 0
+    period = msecs_to_jiffies(HT_RC_UPDATE_INTERVAL);
+    if (time_after(jiffies, mi->stats_update + period)) {
+        struct rc_pid_sta_info *spinfo;
+        spinfo = &rc_sta->spinfo;
+#if 1
+        printk("AMPDU rate update time!!\n");
+#endif
+        if(rc_sta->rc_num_rate == 12) {
+            if(spinfo->txrate_idx >= 4)
+                rc_sta->ht.max_tp_rate = spinfo->txrate_idx - 4;
+            else
+                rc_sta->ht.max_tp_rate = 0;
+        } else
+            rc_sta->ht.max_tp_rate = spinfo->txrate_idx;
+        mi->stats_update = jiffies;
+    }
+#endif
+}
diff --git a/drivers/net/wireless/ssv6x5x/smac/ssv_ht_rc.h b/drivers/net/wireless/ssv6x5x/smac/ssv_ht_rc.h
new file mode 100644
index 000000000..794a05564
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/ssv_ht_rc.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV_RC_HT_H_
+#define _SSV_RC_HT_H_
+#include "ssv_rc_common.h"
+#define MINSTREL_SCALE 16
+#define MINSTREL_FRAC(val,div) (((val) << MINSTREL_SCALE) / div)
+#define MINSTREL_TRUNC(val) ((val) >> MINSTREL_SCALE)
+#define SSV_RC_HT_INTERVAL 100
+s32 ssv62xx_ht_rate_update(struct sk_buff *skb, struct ssv_softc *sc, struct fw_rc_retry_params *ar);
+void ssv62xx_ht_rc_caps(const u16 ssv6xxx_rc_rate_set[RC_TYPE_MAX][13],struct ssv_sta_rc_info *rc_sta);
+void ssv6xxx_ht_report_handler(struct ssv_softc *sc,struct sk_buff *skb,struct ssv_sta_rc_info *rc_sta);
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smac/ssv_pm.c b/drivers/net/wireless/ssv6x5x/smac/ssv_pm.c
new file mode 100644
index 000000000..3c29068c7
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/ssv_pm.c
@@ -0,0 +1,180 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <ssv6200.h>
+#include "dev.h"
+#include "init.h"
+#ifdef CONFIG_SSV_SUPPORT_ANDROID
+#ifdef CONFIG_HAS_WAKELOCK
+#include <linux/wakelock.h>
+#endif
+#ifdef CONFIG_HAS_EARLYSUSPEND
+#include <linux/earlysuspend.h>
+#elif LINUX_VERSION_CODE > KERNEL_VERSION(3, 4, 0)
+#include <linux/notifier.h>
+#include <linux/fb.h>
+#endif
+#if defined(CONFIG_HAS_EARLYSUSPEND) || (LINUX_VERSION_CODE > KERNEL_VERSION(3, 4, 0))
+#ifdef CONFIG_HAS_EARLYSUSPEND
+void ssv6xxx_early_suspend(struct early_suspend *h)
+#else
+void ssv6xxx_early_suspend(void)
+#endif
+{
+#ifdef CONFIG_HAS_EARLYSUSPEND
+    struct ssv_softc *sc = container_of(h, struct ssv_softc, early_suspend);
+#else
+    struct ssv_softc *sc = ssv6xxx_driver_attach(SSV_DRVER_NAME);
+#endif
+    sc->ps_status = PWRSV_PREPARE;
+    printk(KERN_INFO "ssv6xxx_early_suspend\n");
+}
+#define DEAUTH_DISASSOC_LEN (24 + 2 )
+void ssv6xxx_send_deauth_toself(struct ssv_softc *sc,const u8 *bssid,const u8 *self_addr)
+{
+    struct sk_buff *deauth_skb ;
+    u8 frame_buf[DEAUTH_DISASSOC_LEN];
+    struct ieee80211_mgmt *mgmt = (void *)frame_buf;
+    mgmt->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT | IEEE80211_STYPE_DEAUTH);
+    mgmt->duration = 0;
+    mgmt->seq_ctrl = 0;
+    memcpy(mgmt->da, self_addr, ETH_ALEN);
+    memcpy(mgmt->sa, bssid, ETH_ALEN);
+    memcpy(mgmt->bssid, bssid, ETH_ALEN);
+    mgmt->u.deauth.reason_code = cpu_to_le16(2);
+    {
+        deauth_skb = dev_alloc_skb(DEAUTH_DISASSOC_LEN);
+        if (!deauth_skb)
+            return;
+        memcpy(skb_put(deauth_skb, DEAUTH_DISASSOC_LEN),
+               mgmt, DEAUTH_DISASSOC_LEN);
+#if defined(USE_THREAD_RX) && !defined(IRQ_PROC_RX_DATA)
+        local_bh_disable();
+        ieee80211_rx(sc->hw, deauth_skb);
+        local_bh_enable();
+#else
+        ieee80211_rx_irqsafe(sc->hw, deauth_skb);
+#endif
+        return;
+    }
+}
+#ifdef CONFIG_HAS_EARLYSUSPEND
+void ssv6xxx_late_resume(struct early_suspend *h)
+#else
+void ssv6xxx_late_resume(void)
+#endif
+{
+#ifdef CONFIG_HAS_EARLYSUSPEND
+    struct ssv_softc *sc = container_of(h, struct ssv_softc, early_suspend);
+#else
+    struct ssv_softc *sc = ssv6xxx_driver_attach(SSV_DRVER_NAME);
+#endif
+    if(sc->ps_status == PWRSV_ENABLE) {
+        if(sc->vif_info[0].vif) {
+            if(sc->vif_info[0].vif->bss_conf.assoc) {
+                printk("sc->vif_info[0].vif->bss_conf.assoc\n");
+                if ((sc->vif_info[0].vif->type == NL80211_IFTYPE_STATION) || (sc->vif_info[0].vif->p2p)) {
+                    printk("sc->vif_info[0].vif->bss_conf.assoc ssv6xxx_send_deauth_toself\n");
+                    ssv6xxx_send_deauth_toself(sc, sc->vif_info[0].vif->bss_conf.bssid, sc->vif_info[0].vif->addr);
+                }
+            }
+        }
+        if(sc->vif_info[1].vif) {
+            if(sc->vif_info[1].vif->bss_conf.assoc) {
+                printk("sc->vif_info[1].vif->bss_conf.assoc\n");
+                if ((sc->vif_info[1].vif->type == NL80211_IFTYPE_STATION) || (sc->vif_info[1].vif->p2p)) {
+                    printk("sc->vif_info[1].vif->bss_conf.assoc ssv6xxx_send_deauth_toself\n");
+                    ssv6xxx_send_deauth_toself(sc, sc->vif_info[1].vif->bss_conf.bssid, sc->vif_info[1].vif->addr);
+                }
+            }
+        }
+    }
+    if(sc)
+        ssv6xxx_disable_ps(sc);
+    else
+        printk(KERN_INFO "ssv6xxx_late_resume,sc=NULL\n");
+    printk(KERN_INFO "ssv6xxx_late_resume\n");
+}
+#ifndef CONFIG_HAS_EARLYSUSPEND
+static int ssv_wlan_fb_event_notify(struct notifier_block *self,
+                                    unsigned long action, void *data)
+{
+    struct fb_event *event = data;
+    int blank_mode = *((int *)event->data);
+    if (action == FB_EARLY_EVENT_BLANK) {
+        switch (blank_mode) {
+        case FB_BLANK_UNBLANK:
+            break;
+        default:
+            ssv6xxx_early_suspend();
+            break;
+        }
+    } else if (action == FB_EVENT_BLANK) {
+        switch (blank_mode) {
+        case FB_BLANK_UNBLANK:
+            ssv6xxx_late_resume();
+            break;
+        default:
+            break;
+        }
+    }
+    return NOTIFY_OK;
+}
+struct notifier_block ssv_wlan_fb_notifier = {
+    .notifier_call = ssv_wlan_fb_event_notify,
+};
+#endif
+#endif
+void ssv_wakelock_init(struct ssv_softc *sc)
+{
+#ifdef CONFIG_HAS_WAKELOCK
+    wake_lock_init(&sc->ssv_wake_lock_, WAKE_LOCK_SUSPEND, "ssv6051");
+#endif
+#ifndef CONFIG_HAS_EARLYSUSPEND
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)
+    fb_register_client(&ssv_wlan_fb_notifier);
+#endif
+#endif
+}
+void ssv_wakelock_destroy(struct ssv_softc *sc)
+{
+#ifdef CONFIG_HAS_WAKELOCK
+    wake_lock_destroy(&sc->ssv_wake_lock_);
+#endif
+#ifndef CONFIG_HAS_EARLYSUSPEND
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)
+    fb_unregister_client(&ssv_wlan_fb_notifier);
+#endif
+#endif
+}
+void ssv_wake_lock(struct ssv_softc *sc)
+{
+#ifdef CONFIG_HAS_WAKELOCK
+    wake_lock(&sc->ssv_wake_lock_);
+#endif
+}
+void ssv_wake_timeout(struct ssv_softc *sc, int secs)
+{
+#ifdef CONFIG_HAS_WAKELOCK
+    wake_lock_timeout(&sc->ssv_wake_lock_,secs*HZ);
+#endif
+}
+void ssv_wake_unlock(struct ssv_softc *sc)
+{
+#ifdef CONFIG_HAS_WAKELOCK
+    wake_unlock(&sc->ssv_wake_lock_);
+#endif
+}
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smac/ssv_pm.h b/drivers/net/wireless/ssv6x5x/smac/ssv_pm.h
new file mode 100644
index 000000000..664624f80
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/ssv_pm.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV_PM_H_
+#define _SSV_PM_H_
+#include <linux/version.h>
+#ifdef CONFIG_SSV_SUPPORT_ANDROID
+#ifdef CONFIG_HAS_EARLYSUSPEND
+void ssv6xxx_early_suspend(struct early_suspend *h);
+void ssv6xxx_late_resume(struct early_suspend *h);
+#elif LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)
+void ssv6xxx_early_suspend(void);
+void ssv6xxx_late_resume(void);
+#endif
+#ifdef CONFIG_HAS_WAKELOCK
+void ssv_wakelock_init(struct ssv_softc *sc);
+void ssv_wakelock_destroy(struct ssv_softc *sc);
+void ssv_wake_lock(struct ssv_softc *sc);
+void ssv_wake_timeout(struct ssv_softc *sc, int secs);
+void ssv_wake_unlock(struct ssv_softc *sc);
+#endif
+#endif
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smac/ssv_rc.c b/drivers/net/wireless/ssv6x5x/smac/ssv_rc.c
new file mode 100644
index 000000000..5a97ea2b5
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/ssv_rc.c
@@ -0,0 +1,1539 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/version.h>
+#include <ssv6200.h>
+#include "dev.h"
+#include "ssv_ht_rc.h"
+#include "ssv_rc.h"
+#include "ssv_rc_common.h"
+#include <hal.h>
+#include "ssv_skb.h"
+static struct ssv_rc_rate ssv_11bgn_rate_table[] = {
+    [0] = {
+        .rc_flags = RC_FLAG_LEGACY,
+        .phy_type = WLAN_RC_PHY_CCK,
+        .rate_kbps = 1000,
+        .dot11_rate_idx = 0,
+        .ctrl_rate_idx = 0,
+        .hw_rate_idx = 0,
+        .arith_shift = 8,
+        .target_pf = 26,
+    },
+    [1] = {
+        .rc_flags = RC_FLAG_LEGACY,
+        .phy_type = WLAN_RC_PHY_CCK,
+        .rate_kbps = 2000,
+        .dot11_rate_idx = 1,
+        .ctrl_rate_idx = 1,
+        .hw_rate_idx = 1,
+        .arith_shift = 8,
+        .target_pf = 26,
+    },
+    [2] = {
+        .rc_flags = RC_FLAG_LEGACY,
+        .phy_type = WLAN_RC_PHY_CCK,
+        .rate_kbps = 5500,
+        .dot11_rate_idx = 2,
+        .ctrl_rate_idx = 1,
+        .hw_rate_idx = 2,
+        .arith_shift = 8,
+        .target_pf = 26,
+    },
+    [3] = {
+        .rc_flags = RC_FLAG_LEGACY,
+        .phy_type = WLAN_RC_PHY_CCK,
+        .rate_kbps = 11000,
+        .dot11_rate_idx = 3,
+        .ctrl_rate_idx = 1,
+        .hw_rate_idx = 3,
+        .arith_shift = 8,
+        .target_pf = 26,
+    },
+    [4] = {
+        .rc_flags = RC_FLAG_LEGACY | RC_FLAG_SHORT_PREAMBLE,
+        .phy_type = WLAN_RC_PHY_CCK,
+        .rate_kbps = 2000,
+        .dot11_rate_idx = 1,
+        .ctrl_rate_idx = 4,
+        .hw_rate_idx = 4,
+        .arith_shift = 8,
+        .target_pf = 26,
+    },
+    [5] = {
+        .rc_flags = RC_FLAG_LEGACY | RC_FLAG_SHORT_PREAMBLE,
+        .phy_type = WLAN_RC_PHY_CCK,
+        .rate_kbps = 5500,
+        .dot11_rate_idx = 2,
+        .ctrl_rate_idx = 4,
+        .hw_rate_idx = 5,
+        .arith_shift = 8,
+        .target_pf = 26,
+    },
+    [6] = {
+        .rc_flags = RC_FLAG_LEGACY | RC_FLAG_SHORT_PREAMBLE,
+        .phy_type = WLAN_RC_PHY_CCK,
+        .rate_kbps = 11000,
+        .dot11_rate_idx = 3,
+        .ctrl_rate_idx = 4,
+        .hw_rate_idx = 6,
+        .arith_shift = 8,
+        .target_pf = 26,
+    },
+    [7] = {
+        .rc_flags = RC_FLAG_LEGACY,
+        .phy_type = WLAN_RC_PHY_OFDM,
+        .rate_kbps = 6000,
+        .dot11_rate_idx = 4,
+        .ctrl_rate_idx = 7,
+        .hw_rate_idx = 7,
+        .arith_shift = 8,
+        .target_pf = 26,
+    },
+    [8] = {
+        .rc_flags = RC_FLAG_LEGACY,
+        .phy_type = WLAN_RC_PHY_OFDM,
+        .rate_kbps = 9000,
+        .dot11_rate_idx = 5,
+        .ctrl_rate_idx = 7,
+        .hw_rate_idx = 8,
+        .arith_shift = 8,
+        .target_pf = 26,
+    },
+    [9] = {
+        .rc_flags = RC_FLAG_LEGACY,
+        .phy_type = WLAN_RC_PHY_OFDM,
+        .rate_kbps = 12000,
+        .dot11_rate_idx = 6,
+        .ctrl_rate_idx = 9,
+        .hw_rate_idx = 9,
+        .arith_shift = 8,
+        .target_pf = 26,
+    },
+    [10] = {
+        .rc_flags = RC_FLAG_LEGACY,
+        .phy_type = WLAN_RC_PHY_OFDM,
+        .rate_kbps = 18000,
+        .dot11_rate_idx = 7,
+        .ctrl_rate_idx = 9,
+        .hw_rate_idx = 10,
+        .arith_shift = 8,
+        .target_pf = 26,
+    },
+    [11] = {
+        .rc_flags = RC_FLAG_LEGACY,
+        .phy_type = WLAN_RC_PHY_OFDM,
+        .rate_kbps = 24000,
+        .dot11_rate_idx = 8,
+        .ctrl_rate_idx = 11,
+        .hw_rate_idx = 11,
+        .arith_shift = 8,
+        .target_pf = 26,
+    },
+    [12] = {
+        .rc_flags = RC_FLAG_LEGACY,
+        .phy_type = WLAN_RC_PHY_OFDM,
+        .rate_kbps = 36000,
+        .dot11_rate_idx = 9,
+        .ctrl_rate_idx = 11,
+        .hw_rate_idx = 12,
+        .arith_shift = 8,
+        .target_pf = 26,
+    },
+    [13] = {
+        .rc_flags = RC_FLAG_LEGACY,
+        .phy_type = WLAN_RC_PHY_OFDM,
+        .rate_kbps = 48000,
+        .dot11_rate_idx = 10,
+        .ctrl_rate_idx = 11,
+        .hw_rate_idx = 13,
+        .arith_shift = 8,
+        .target_pf = 26,
+    },
+    [14] = {
+        .rc_flags = RC_FLAG_LEGACY,
+        .phy_type = WLAN_RC_PHY_OFDM,
+        .rate_kbps = 54000,
+        .dot11_rate_idx = 11,
+        .ctrl_rate_idx = 11,
+        .hw_rate_idx = 14,
+        .arith_shift = 8,
+        .target_pf = 8
+    },
+    [15] = {
+        .rc_flags = RC_FLAG_HT,
+        .phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
+        .rate_kbps = 6500,
+        .dot11_rate_idx = 0,
+        .ctrl_rate_idx = 7,
+        .hw_rate_idx = 15,
+        .arith_shift = 8,
+        .target_pf = 26,
+    },
+    [16] = {
+        .rc_flags = RC_FLAG_HT,
+        .phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
+        .rate_kbps = 13000,
+        .dot11_rate_idx = 1,
+        .ctrl_rate_idx = 9,
+        .hw_rate_idx = 16,
+        .arith_shift = 8,
+        .target_pf = 26,
+    },
+    [17] = {
+        .rc_flags = RC_FLAG_HT,
+        .phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
+        .rate_kbps = 19500,
+        .dot11_rate_idx = 2,
+        .ctrl_rate_idx = 9,
+        .hw_rate_idx = 17,
+        .arith_shift = 8,
+        .target_pf = 26,
+    },
+    [18] = {
+        .rc_flags = RC_FLAG_HT,
+        .phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
+        .rate_kbps = 26000,
+        .dot11_rate_idx = 3,
+        .ctrl_rate_idx = 11,
+        .hw_rate_idx = 18,
+        .arith_shift = 8,
+        .target_pf = 26,
+    },
+    [19] = {
+        .rc_flags = RC_FLAG_HT,
+        .phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
+        .rate_kbps = 39000,
+        .dot11_rate_idx = 4,
+        .ctrl_rate_idx = 11,
+        .hw_rate_idx = 19,
+        .arith_shift = 8,
+        .target_pf = 26,
+    },
+    [20] = {
+        .rc_flags = RC_FLAG_HT,
+        .phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
+        .rate_kbps = 52000,
+        .dot11_rate_idx = 5,
+        .ctrl_rate_idx = 11,
+        .hw_rate_idx = 20,
+        .arith_shift = 8,
+        .target_pf = 26,
+    },
+    [21] = {
+        .rc_flags = RC_FLAG_HT,
+        .phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
+        .rate_kbps = 58500,
+        .dot11_rate_idx = 6,
+        .ctrl_rate_idx = 11,
+        .hw_rate_idx = 21,
+        .arith_shift = 8,
+        .target_pf = 26,
+    },
+    [22] = {
+        .rc_flags = RC_FLAG_HT,
+        .phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
+        .rate_kbps = 65000,
+        .dot11_rate_idx = 7,
+        .ctrl_rate_idx = 11,
+        .hw_rate_idx = 22,
+        .arith_shift = 8,
+        .target_pf = 8
+    },
+    [23] = {
+        .rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
+        .phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
+        .rate_kbps = 7200,
+        .dot11_rate_idx = 0,
+        .ctrl_rate_idx = 7,
+        .hw_rate_idx = 23,
+        .arith_shift = 8,
+        .target_pf = 26,
+    },
+    [24] = {
+        .rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
+        .phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
+        .rate_kbps = 14400,
+        .dot11_rate_idx = 1,
+        .ctrl_rate_idx = 9,
+        .hw_rate_idx = 24,
+        .arith_shift = 8,
+        .target_pf = 26,
+    },
+    [25] = {
+        .rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
+        .phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
+        .rate_kbps = 21700,
+        .dot11_rate_idx = 2,
+        .ctrl_rate_idx = 9,
+        .hw_rate_idx = 25,
+        .arith_shift = 8,
+        .target_pf = 26,
+    },
+    [26] = {
+        .rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
+        .phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
+        .rate_kbps = 28900,
+        .dot11_rate_idx = 3,
+        .ctrl_rate_idx = 11,
+        .hw_rate_idx = 26,
+        .arith_shift = 8,
+        .target_pf = 26,
+    },
+    [27] = {
+        .rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
+        .phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
+        .rate_kbps = 43300,
+        .dot11_rate_idx = 4,
+        .ctrl_rate_idx = 11,
+        .hw_rate_idx = 27,
+        .arith_shift = 8,
+        .target_pf = 26,
+    },
+    [28] = {
+        .rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
+        .phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
+        .rate_kbps = 57800,
+        .dot11_rate_idx = 5,
+        .ctrl_rate_idx = 11,
+        .hw_rate_idx = 28,
+        .arith_shift = 8,
+        .target_pf = 26,
+    },
+    [29] = {
+        .rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
+        .phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
+        .rate_kbps = 65000,
+        .dot11_rate_idx = 6,
+        .ctrl_rate_idx = 11,
+        .hw_rate_idx = 29,
+        .arith_shift = 8,
+        .target_pf = 26,
+    },
+    [30] = {
+        .rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
+        .phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
+        .rate_kbps = 72200,
+        .dot11_rate_idx = 7,
+        .ctrl_rate_idx = 11,
+        .hw_rate_idx = 30,
+        .arith_shift = 8,
+        .target_pf = 8
+    },
+    [31] = {
+        .rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
+        .phy_type = WLAN_RC_PHY_HT_20_SS_GF,
+        .rate_kbps = 6500,
+        .dot11_rate_idx = 0,
+        .ctrl_rate_idx = 7,
+        .hw_rate_idx = 31,
+        .arith_shift = 8,
+        .target_pf = 26,
+    },
+    [32] = {
+        .rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
+        .phy_type = WLAN_RC_PHY_HT_20_SS_GF,
+        .rate_kbps = 13000,
+        .dot11_rate_idx = 1,
+        .ctrl_rate_idx = 9,
+        .hw_rate_idx = 32,
+        .arith_shift = 8,
+        .target_pf = 26,
+    },
+    [33] = {
+        .rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
+        .phy_type = WLAN_RC_PHY_HT_20_SS_GF,
+        .rate_kbps = 19500,
+        .dot11_rate_idx = 2,
+        .ctrl_rate_idx = 9,
+        .hw_rate_idx = 33,
+        .arith_shift = 8,
+        .target_pf = 26,
+    },
+    [34] = {
+        .rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
+        .phy_type = WLAN_RC_PHY_HT_20_SS_GF,
+        .rate_kbps = 26000,
+        .dot11_rate_idx = 3,
+        .ctrl_rate_idx = 11,
+        .hw_rate_idx = 34,
+        .arith_shift = 8,
+        .target_pf = 26,
+    },
+    [35] = {
+        .rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
+        .phy_type = WLAN_RC_PHY_HT_20_SS_GF,
+        .rate_kbps = 39000,
+        .dot11_rate_idx = 4,
+        .ctrl_rate_idx = 11,
+        .hw_rate_idx = 35,
+        .arith_shift = 8,
+        .target_pf = 26,
+    },
+    [36] = {
+        .rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
+        .phy_type = WLAN_RC_PHY_HT_20_SS_GF,
+        .rate_kbps = 52000,
+        .dot11_rate_idx = 5,
+        .ctrl_rate_idx = 11,
+        .hw_rate_idx = 36,
+        .arith_shift = 8,
+        .target_pf = 26,
+    },
+    [37] = {
+        .rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
+        .phy_type = WLAN_RC_PHY_HT_20_SS_GF,
+        .rate_kbps = 58500,
+        .dot11_rate_idx = 6,
+        .ctrl_rate_idx = 11,
+        .hw_rate_idx = 37,
+        .arith_shift = 8,
+        .target_pf = 26,
+    },
+    [38] = {
+        .rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
+        .phy_type = WLAN_RC_PHY_HT_20_SS_GF,
+        .rate_kbps = 65000,
+        .dot11_rate_idx = 7,
+        .ctrl_rate_idx = 11,
+        .hw_rate_idx = 38,
+        .arith_shift = 8,
+        .target_pf = 8
+    },
+};
+const u16 ssv6xxx_rc_rate_set[RC_TYPE_MAX][13] = {
+    [RC_TYPE_B_ONLY] = { 4, 0, 1, 2, 3},
+    [RC_TYPE_LEGACY_GB] = { 12, 0, 1, 2, 7, 8, 3, 9, 10, 11, 12, 13, 14 },
+#if 0
+    [RC_TYPE_SGI_20] = { 12, 0, 1, 2, 3, 15, 16, 17, 18, 19, 20, 29, 30 },
+    [RC_TYPE_LGI_20] = { 12, 0, 1, 2, 3, 15, 16, 17, 18, 19, 20, 21, 22 },
+#else
+    [RC_TYPE_SGI_20] = { 8, 15, 16, 17, 18, 19, 20, 29, 30 },
+    [RC_TYPE_LGI_20] = { 8, 15, 16, 17, 18, 19, 20, 21, 22 },
+#endif
+    [RC_TYPE_HT_SGI_20] = { 8, 15, 16, 17, 18, 19, 20, 29, 30 },
+    [RC_TYPE_HT_LGI_20] = { 8, 15, 16, 17, 18, 19, 20, 21, 22 },
+    [RC_TYPE_HT_GF] = { 8, 31, 32, 33, 34, 35, 36, 37, 38 },
+};
+static u32 ssv6xxx_rate_supported(struct ssv_sta_rc_info *rc_sta, u32 index)
+{
+    return (rc_sta->rc_supp_rates & BIT(index));
+}
+#if 1
+static u8 ssv6xxx_rate_lowest_index(struct ssv_sta_rc_info *rc_sta)
+{
+    int i;
+    for (i = 0; i < rc_sta->rc_num_rate; i++)
+        if (ssv6xxx_rate_supported(rc_sta, i))
+            return i;
+    return 0;
+}
+#endif
+#ifdef DISABLE_RATE_CONTROL_SAMPLE
+static u8 ssv6xxx_rate_highest_index(struct ssv_sta_rc_info *rc_sta)
+{
+    int i;
+    for (i=rc_sta->rc_num_rate-1; i >= 0; i--)
+        if (ssv6xxx_rate_supported(rc_sta, i))
+            return i;
+    return 0;
+}
+#endif
+static void rate_control_pid_adjust_rate(struct ssv_sta_rc_info *rc_sta,
+        struct rc_pid_sta_info *spinfo, int adj,struct rc_pid_rateinfo *rinfo)
+{
+    int cur_sorted, new_sorted, probe, tmp, n_bitrates;
+    int cur = spinfo->txrate_idx;
+    n_bitrates = rc_sta->rc_num_rate;
+    cur_sorted = rinfo[cur].index;
+    new_sorted = cur_sorted + adj;
+    if (new_sorted < 0)
+        new_sorted = rinfo[0].index;
+    else if (new_sorted >= n_bitrates)
+        new_sorted = rinfo[n_bitrates - 1].index;
+    tmp = new_sorted;
+    if (adj < 0) {
+        for (probe = cur_sorted; probe >= new_sorted; probe--)
+            if (rinfo[probe].diff <= rinfo[cur_sorted].diff &&
+                ssv6xxx_rate_supported(rc_sta, rinfo[probe].index))
+                tmp = probe;
+    } else {
+        for (probe = new_sorted + 1; probe < n_bitrates; probe++)
+            if (rinfo[probe].diff <= rinfo[new_sorted].diff &&
+                ssv6xxx_rate_supported(rc_sta, rinfo[probe].index))
+                tmp = probe;
+    }
+    BUG_ON(tmp<0 || tmp>=n_bitrates);
+    do {
+        if (ssv6xxx_rate_supported(rc_sta, rinfo[tmp].index)) {
+            spinfo->tmp_rate_idx = rinfo[tmp].index;
+            break;
+        }
+        if (adj < 0)
+            tmp--;
+        else
+            tmp++;
+    } while (tmp < n_bitrates && tmp >= 0);
+    spinfo->oldrate = spinfo->txrate_idx;
+    if (spinfo->tmp_rate_idx != spinfo->txrate_idx) {
+        spinfo->monitoring = 1;
+#ifdef RATE_CONTROL_PARAMETER_DEBUG
+        printk("Trigger monitor tmp_rate_idx=[%d]\n",spinfo->tmp_rate_idx);
+#endif
+        spinfo->probe_cnt = MAXPROBES;
+    }
+}
+static void rate_control_pid_normalize(struct rc_pid_info *pinfo, int l)
+{
+    int i, norm_offset = RC_PID_NORM_OFFSET;
+    struct rc_pid_rateinfo *r = pinfo->rinfo;
+    if (r[0].diff > norm_offset)
+        r[0].diff -= norm_offset;
+    else if (r[0].diff < -norm_offset)
+        r[0].diff += norm_offset;
+    for (i = 0; i < l - 1; i++)
+        if (r[i + 1].diff > r[i].diff + norm_offset)
+            r[i + 1].diff -= norm_offset;
+        else if (r[i + 1].diff <= r[i].diff)
+            r[i + 1].diff += norm_offset;
+}
+#ifdef RATE_CONTROL_DEBUG
+unsigned int txrate_dlr=0;
+#endif
+static void rate_control_pid_sample(struct ssv_rate_ctrl* ssv_rc,struct rc_pid_info *pinfo,
+                                    struct ssv_sta_rc_info *rc_sta,
+                                    struct rc_pid_sta_info *spinfo)
+{
+    struct rc_pid_rateinfo *rinfo = pinfo->rinfo;
+    u8 pf;
+    s32 err_avg;
+    s32 err_prop;
+    s32 err_int;
+    s32 err_der;
+    int adj, i, j, tmp;
+    struct ssv_rc_rate *rc_table;
+    unsigned int dlr;
+    unsigned int perfect_time = 0;
+    unsigned int this_thp, ewma_thp;
+    struct rc_pid_rateinfo *rate;
+    if (!spinfo->monitoring) {
+#if 0
+        period = msecs_to_jiffies(pinfo->sampling_period);
+        if (jiffies - spinfo->last_sample > 2 * period)
+            spinfo->sharp_cnt = RC_PID_SHARPENING_DURATION;
+#endif
+        if (spinfo->tx_num_xmit == 0)
+            return;
+        spinfo->last_sample = jiffies;
+        pf = spinfo->tx_num_failed * 100 / spinfo->tx_num_xmit;
+        if (pinfo->rinfo[spinfo->txrate_idx].this_attempt > 0) {
+            rate = &pinfo->rinfo[spinfo->txrate_idx];
+            rc_table = &ssv_rc->rc_table[spinfo->txrate_idx];
+            dlr = 100 - rate->this_fail * 100 / rate->this_attempt;
+            perfect_time = rate->perfect_tx_time;
+            if (!perfect_time)
+                perfect_time = 1000000;
+            this_thp = dlr * (1000000 / perfect_time);
+            ewma_thp = rate->throughput;
+            if (ewma_thp == 0)
+                rate->throughput = this_thp;
+            else
+                rate->throughput = (ewma_thp + this_thp) >> 1;
+            rate->attempt += rate->this_attempt;
+            rate->success += rate->this_success;
+            rate->fail += rate->this_fail;
+            spinfo->tx_num_xmit = 0;
+            spinfo->tx_num_failed = 0;
+            rate->this_fail = 0;
+            rate->this_success = 0;
+            rate->this_attempt = 0;
+            if (pinfo->oldrate<0 || pinfo->oldrate>=rc_sta->rc_num_rate) {
+                WARN_ON(1);
+            }
+            if (spinfo->txrate_idx<0 || spinfo->txrate_idx>=rc_sta->rc_num_rate) {
+                WARN_ON(1);
+            }
+            if (pinfo->oldrate != spinfo->txrate_idx) {
+                i = rinfo[pinfo->oldrate].index;
+                j = rinfo[spinfo->txrate_idx].index;
+                tmp = (pf - spinfo->last_pf);
+                tmp = RC_PID_DO_ARITH_RIGHT_SHIFT(tmp, rc_table->arith_shift);
+                rinfo[j].diff = rinfo[i].diff + tmp;
+                pinfo->oldrate = spinfo->txrate_idx;
+            }
+            rate_control_pid_normalize(pinfo, rc_sta->rc_num_rate);
+            err_prop = (rc_table->target_pf - pf) << rc_table->arith_shift;
+            err_avg = spinfo->err_avg_sc >> RC_PID_SMOOTHING_SHIFT;
+            spinfo->err_avg_sc = spinfo->err_avg_sc - err_avg + err_prop;
+            err_int = spinfo->err_avg_sc >> RC_PID_SMOOTHING_SHIFT;
+            err_der = pf - spinfo->last_pf;
+            spinfo->last_pf = pf;
+            spinfo->last_dlr = dlr;
+            spinfo->oldrate = spinfo->txrate_idx;
+#if 0
+            if (spinfo->sharp_cnt)
+                spinfo->sharp_cnt--;
+#endif
+            adj = (err_prop * RC_PID_COEFF_P + err_int * RC_PID_COEFF_I + err_der * RC_PID_COEFF_D);
+            adj = RC_PID_DO_ARITH_RIGHT_SHIFT(adj, rc_table->arith_shift<<1);
+            if (adj) {
+#ifdef RATE_CONTROL_PARAMETER_DEBUG
+                if((spinfo->txrate_idx!=11) || ((spinfo->txrate_idx==11)&&(adj < 0)))
+                    printk("[RC]Probe adjust[%d] dlr[%d%%] this_thp[%d] ewma_thp[%d] index[%d]\n",adj,dlr,this_thp,ewma_thp,spinfo->txrate_idx);
+#endif
+                rate_control_pid_adjust_rate(rc_sta, spinfo, adj, rinfo);
+            }
+        }
+    } else {
+        if((spinfo->feedback_probes >= MAXPROBES) || (spinfo->feedback_probes && spinfo->probe_cnt)) {
+            rate = &pinfo->rinfo[spinfo->txrate_idx];
+#if 0
+            period = msecs_to_jiffies(pinfo->sampling_period);
+            if (jiffies - spinfo->last_sample > 2 * period)
+                spinfo->sharp_cnt = RC_PID_SHARPENING_DURATION;
+#endif
+            spinfo->last_sample = jiffies;
+            if (rate->this_attempt > 0) {
+                dlr = 100 - rate->this_fail * 100 / rate->this_attempt;
+#ifdef RATE_CONTROL_DEBUG
+#ifdef PROBE
+                txrate_dlr=dlr;
+#endif
+#endif
+                spinfo->last_dlr = dlr;
+                perfect_time = rate->perfect_tx_time;
+                if (!perfect_time)
+                    perfect_time = 1000000;
+                this_thp = dlr * (1000000 / perfect_time);
+                ewma_thp = rate->throughput;
+                if (ewma_thp == 0)
+                    rate->throughput = this_thp;
+                else
+                    rate->throughput = (ewma_thp + this_thp) >> 1;
+                rate->attempt += rate->this_attempt;
+                rate->success += rate->this_success;
+                rinfo[spinfo->txrate_idx].fail += rate->this_fail;
+                rate->this_fail = 0;
+                rate->this_success = 0;
+                rate->this_attempt = 0;
+            } else {
+#ifdef RATE_CONTROL_DEBUG
+#ifdef PROBE
+                txrate_dlr=0;
+#endif
+#endif
+            }
+            rate = &pinfo->rinfo[spinfo->tmp_rate_idx];
+            if (rate->this_attempt > 0) {
+                dlr = 100 - ((rate->this_fail * 100) / rate->this_attempt);
+                {
+                    perfect_time = rate->perfect_tx_time;
+                    if (!perfect_time)
+                        perfect_time = 1000000;
+                    if(dlr)
+                        this_thp = dlr * (1000000 / perfect_time);
+                    else
+                        this_thp = 0;
+                    ewma_thp = rate->throughput;
+                    if (ewma_thp == 0)
+                        rate->throughput = this_thp;
+                    else
+                        rate->throughput = (ewma_thp + this_thp) >> 1;
+                    if (rate->throughput > pinfo->rinfo[spinfo->txrate_idx].throughput) {
+#ifdef RATE_CONTROL_PARAMETER_DEBUG
+                        printk("[RC]UPDATE probe rate idx[%d] [%d][%d%%] Old idx[%d] [%d][%d%%] feedback[%d] \n",spinfo->tmp_rate_idx,rate->throughput,dlr,spinfo->txrate_idx,pinfo->rinfo[spinfo->txrate_idx].throughput,txrate_dlr,spinfo->feedback_probes);
+#endif
+                        spinfo->txrate_idx = spinfo->tmp_rate_idx;
+                    } else {
+#ifdef RATE_CONTROL_PARAMETER_DEBUG
+                        printk("[RC]Fail probe rate idx[%d] [%d][%d%%] Old idx[%d] [%d][%d%%] feedback[%d] \n",spinfo->tmp_rate_idx,rate->throughput,dlr,spinfo->txrate_idx,pinfo->rinfo[spinfo->txrate_idx].throughput,txrate_dlr,spinfo->feedback_probes);
+#endif
+                        ;
+                    }
+                    rate->attempt += rate->this_attempt;
+                    rate->success += rate->this_success;
+                    rate->fail += rate->this_fail;
+                    rate->this_fail = 0;
+                    rate->this_success = 0;
+                    rate->this_attempt = 0;
+                    spinfo->oldrate = spinfo->txrate_idx;
+                }
+            }
+#ifdef RATE_CONTROL_DEBUG
+            else
+                printk("SHIT-2!!!!\n");
+#endif
+            spinfo->feedback_probes = 0;
+            spinfo->tx_num_xmit = 0;
+            spinfo->tx_num_failed = 0;
+            spinfo->monitoring = 0;
+#ifdef RATE_CONTROL_PARAMETER_DEBUG
+            printk("Disable monitor\n");
+#endif
+            spinfo->probe_report_flag = 0;
+            spinfo->probe_wating_times = 0;
+        } else {
+            spinfo->probe_wating_times ++;
+#ifdef RATE_CONTROL_DEBUG
+            if(spinfo->probe_wating_times > 3) {
+                printk("[RC] sta[%d] @@@@@ PROBE LOSE @@@@@ feedback=[%d] need=[%d] probe_cnt=[%d] wating times[%d]\n",
+                       rc_sta->rc_wsid,spinfo->feedback_probes,MAXPROBES,spinfo->probe_cnt,spinfo->probe_wating_times);
+                spinfo->feedback_probes = 0;
+                spinfo->tx_num_xmit = 0;
+                spinfo->tx_num_failed = 0;
+                spinfo->monitoring = 0;
+                spinfo->probe_report_flag = 0;
+                spinfo->probe_wating_times = 0;
+            }
+#else
+            if(spinfo->probe_wating_times > 3) {
+                spinfo->feedback_probes = 0;
+                spinfo->tx_num_xmit = 0;
+                spinfo->tx_num_failed = 0;
+                spinfo->monitoring = 0;
+                spinfo->probe_report_flag = 0;
+                spinfo->probe_wating_times = 0;
+            }
+#endif
+        }
+    }
+}
+#ifdef RATE_CONTROL_PERCENTAGE_TRACE
+int percentage = 0;
+int percentageCounter = 0;
+#endif
+void ssv6xxx_legacy_report_handler(struct ssv_softc *sc,struct sk_buff *skb,struct ssv_sta_rc_info *rc_sta)
+{
+    struct ssv_rate_ctrl *ssv_rc=sc->rc;
+    struct cfg_host_event *host_event;
+    struct firmware_rate_control_report_data *report_data;
+    struct rc_pid_info *pinfo;
+    struct rc_pid_sta_info *spinfo;
+    struct rc_pid_rateinfo * pidrate;
+    struct rc_pid_rateinfo *rate;
+    s32 report_data_index = 0;
+    unsigned long period;
+    host_event = (struct cfg_host_event *)skb->data;
+    report_data = (struct firmware_rate_control_report_data *)&host_event->dat[0];
+    if ( (report_data->wsid != (-1))
+         && sc->sta_info[report_data->wsid].sta == NULL) {
+        dev_warn(sc->dev, "RC report has no valid STA.(%d)\n", report_data->wsid);
+        return;
+    }
+    pinfo = &rc_sta->pinfo;
+    spinfo = &rc_sta->spinfo;
+    pidrate = rc_sta->pinfo.rinfo;
+    if(host_event->h_event == SOC_EVT_RC_AMPDU_REPORT) {
+#if 1
+        period = msecs_to_jiffies(HT_RC_UPDATE_INTERVAL);
+        if (time_after(jiffies, spinfo->last_sample + period)) {
+            if(rc_sta->rc_num_rate == 12)
+                spinfo->txrate_idx = rc_sta->ht.max_tp_rate + 4;
+            else
+                spinfo->txrate_idx = rc_sta->ht.max_tp_rate;
+#ifdef RATE_CONTROL_DEBUG
+            printk("MPDU rate update time txrate_idx[%d]!!\n",spinfo->txrate_idx);
+#endif
+            spinfo->last_sample = jiffies;
+        }
+#endif
+        return;
+    } else if(host_event->h_event == SOC_EVT_RC_MPDU_REPORT) {
+#if 0
+        printk("SC report !MPDU! wsid[%d]rate[%d]M[%d]S[%d]R[%d]\n",report_data->wsid,report_data->rates[0].data_rate,
+               report_data->ampdu_len,report_data->ampdu_ack_len,report_data->rates[0].count);
+#endif
+        ;
+    } else {
+        printk("RC work get garbage!!\n");
+        return;
+    }
+    if(report_data->rates[0].data_rate < 7) {
+        if(report_data->rates[0].data_rate>3) {
+            report_data->rates[0].data_rate -= 3;
+        }
+    }
+    if(ssv_rc->rc_table[rc_sta->pinfo.rinfo[spinfo->txrate_idx].rc_index].hw_rate_idx == report_data->rates[0].data_rate) {
+        report_data_index = rc_sta->pinfo.rinfo[spinfo->txrate_idx].index;
+    } else if(ssv_rc->rc_table[rc_sta->pinfo.rinfo[spinfo->tmp_rate_idx].rc_index].hw_rate_idx == report_data->rates[0].data_rate) {
+        report_data_index = rc_sta->pinfo.rinfo[spinfo->tmp_rate_idx].index;
+    }
+    if((report_data_index != spinfo->tmp_rate_idx) && (report_data_index != spinfo->txrate_idx)) {
+#ifdef RATE_CONTROL_DEBUG
+        printk("Rate control report mismatch report_rate_idx[%d] tmp_rate_idx[%d]rate[%d] txrate_idx[%d]rate[%d]!!\n",
+               report_data->rates[0].data_rate,spinfo->tmp_rate_idx,
+               ssv_rc->rc_table[rc_sta->pinfo.rinfo[spinfo->tmp_rate_idx].rc_index].hw_rate_idx,
+               spinfo->txrate_idx,
+               ssv_rc->rc_table[rc_sta->pinfo.rinfo[spinfo->txrate_idx].rc_index].hw_rate_idx);
+#endif
+        return;
+    }
+    if(report_data_index == spinfo->txrate_idx) {
+        spinfo->tx_num_xmit += report_data->rates[0].count;
+        spinfo->tx_num_failed += (report_data->rates[0].count - report_data->ampdu_ack_len );
+        rate = &pidrate[spinfo->txrate_idx];
+        rate->this_fail += ( report_data->rates[0].count - report_data->ampdu_ack_len );
+        rate->this_attempt += report_data->rates[0].count;
+        rate->this_success += report_data->ampdu_ack_len;
+    }
+    if (report_data_index != spinfo->txrate_idx && report_data_index == spinfo->tmp_rate_idx) {
+        spinfo->feedback_probes += report_data->ampdu_len;
+        rate = &pidrate[spinfo->tmp_rate_idx];
+        rate->this_fail += ( report_data->rates[0].count - report_data->ampdu_ack_len );
+        rate->this_attempt += report_data->rates[0].count;
+        rate->this_success += report_data->ampdu_ack_len;
+    }
+    period = msecs_to_jiffies(RC_PID_INTERVAL);
+    if (time_after(jiffies, spinfo->last_sample + period)) {
+#ifdef RATE_CONTROL_PERCENTAGE_TRACE
+        rate = &pidrate[spinfo->txrate_idx];
+        if(rate->this_success > rate->this_attempt) {
+            printk("#############################\n");
+            printk("this_success[%ld] this_attempt[%ld]\n",rate->this_success,rate->this_attempt);
+            printk("#############################\n");
+        } else {
+            if(percentage == 0)
+                percentage = (int)((rate->this_success*100)/rate->this_attempt);
+            else
+                percentage = (percentage + (int)((rate->this_success*100)/rate->this_attempt))/2;
+            printk("Percentage[%d]\n",percentage);
+            if((percentageCounter % 16)==1)
+                percentage = 0;
+        }
+#endif
+#ifdef RATE_CONTROL_STUPID_DEBUG
+        if (spinfo->txrate_idx != spinfo->tmp_rate_idx) {
+            rate = &pidrate[spinfo->tmp_rate_idx];
+            if (spinfo->monitoring && ((rate->this_attempt == 0)||(rate->this_attempt!=MAXPROBES))) {
+                printk("Probe result a[%ld]s[%ld]f[%ld]",rate->this_attempt,rate->this_success,rate->this_fail);
+            }
+            rate = &pidrate[spinfo->txrate_idx];
+            printk("New a[%ld]s[%ld]f[%ld] \n",rate->this_attempt,rate->this_success,rate->this_fail);
+        } else {
+            rate = &pidrate[spinfo->txrate_idx];
+            printk("New a[%ld]s[%ld]f[%ld] \n",rate->this_attempt,rate->this_success,rate->this_fail);
+        }
+        printk("w[%d]x%03d-f%03d\n",rc_sta->rc_wsid,spinfo->tx_num_xmit,spinfo->tx_num_failed);
+#endif
+        rate_control_pid_sample(sc->rc, pinfo, rc_sta, spinfo);
+    }
+}
+static void ssv6xxx_tx_status(void *priv, struct ieee80211_supported_band *sband,
+                              struct ieee80211_sta *sta, void *priv_sta,
+                              struct sk_buff *skb)
+{
+    struct ssv_softc *sc;
+    struct ieee80211_hdr *hdr;
+    __le16 fc;
+    hdr = (struct ieee80211_hdr *)skb->data;
+    fc = hdr->frame_control;
+    if (!priv_sta || !ieee80211_is_data_qos(fc))
+        return;
+    sc = (struct ssv_softc *)priv;
+    if ( conf_is_ht(&sc->hw->conf)
+         && (!(skb->protocol == cpu_to_be16(ETH_P_PAE)))) {
+        if (skb_get_queue_mapping(skb) != IEEE80211_AC_VO)
+            ssv6200_ampdu_tx_update_state(priv, sta, skb);
+    }
+    return;
+}
+#if 1
+static void rateControlGetRate(u8 rateIndex, char * pointer)
+{
+    switch(rateIndex) {
+    case 0:
+        sprintf(pointer, "1Mbps");
+        return;
+    case 1:
+    case 4:
+        sprintf(pointer, "2Mbps");
+        return;
+    case 2:
+    case 5:
+        sprintf(pointer, "5.5Mbps");
+        return;
+    case 3:
+    case 6:
+        sprintf(pointer, "11Mbps");
+        return;
+    case 7:
+        sprintf(pointer, "6Mbps");
+        return;
+    case 8:
+        sprintf(pointer, "9Mbps");
+        return;
+    case 9:
+        sprintf(pointer, "12Mbps");
+        return;
+    case 10:
+        sprintf(pointer, "18Mbps");
+        return;
+    case 11:
+        sprintf(pointer, "24Mbps");
+        return;
+    case 12:
+        sprintf(pointer, "36Mbps");
+        return;
+    case 13:
+        sprintf(pointer, "48Mbps");
+        return;
+    case 14:
+        sprintf(pointer, "54Mbps");
+        return;
+    case 15:
+    case 31:
+        sprintf(pointer, "MCS0-l");
+        return;
+    case 16:
+    case 32:
+        sprintf(pointer, "MCS1-l");
+        return;
+    case 17:
+    case 33:
+        sprintf(pointer, "MCS2-l");
+        return;
+    case 18:
+    case 34:
+        sprintf(pointer, "MCS3-l");
+        return;
+    case 19:
+    case 35:
+        sprintf(pointer, "MCS4-l");
+        return;
+    case 20:
+    case 36:
+        sprintf(pointer, "MCS5-l");
+        return;
+    case 21:
+    case 37:
+        sprintf(pointer, "MCS6-l");
+        return;
+    case 22:
+    case 38:
+        sprintf(pointer, "MCS7-l");
+        return;
+    case 23:
+        sprintf(pointer, "MCS0-s");
+        return;
+    case 24:
+        sprintf(pointer, "MCS1-s");
+        return;
+    case 25:
+        sprintf(pointer, "MCS2-s");
+        return;
+    case 26:
+        sprintf(pointer, "MCS3-s");
+        return;
+    case 27:
+        sprintf(pointer, "MCS4-s");
+        return;
+    case 28:
+        sprintf(pointer, "MCS5-s");
+        return;
+    case 29:
+        sprintf(pointer, "MCS6-s");
+        return;
+    case 30:
+        sprintf(pointer, "MCS7-s");
+        return;
+    default:
+        sprintf(pointer, "Unknow");
+        return;
+    };
+}
+#endif
+static void ssv6xxx_get_rate(void *priv, struct ieee80211_sta *sta, void *priv_sta,
+                             struct ieee80211_tx_rate_control *txrc)
+{
+    struct ssv_softc *sc=priv;
+    struct ssv_rate_ctrl *ssv_rc=sc->rc;
+    struct ssv_sta_rc_info *rc_sta=priv_sta;
+    struct sk_buff *skb = txrc->skb;
+    struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
+    struct ieee80211_tx_rate *rates = tx_info->control.rates;
+    struct rc_pid_sta_info *spinfo=&rc_sta->spinfo;
+    struct ssv_rc_rate *rc_rate = NULL;
+    struct ssv_sta_priv_data *ssv_sta_priv;
+    int rateidx = 0;
+#if 0
+    if ( (tx_info->control.vif != NULL)
+         && (tx_info->control.vif->p2p)) {
+        tx_info->flags |= IEEE80211_TX_CTL_NO_CCK_RATE;
+    }
+#endif
+    if (rate_control_send_low(sta, priv_sta, txrc)) {
+        int i = 0;
+        int total_rates = (sizeof(ssv_11bgn_rate_table) / sizeof(ssv_11bgn_rate_table[0]));
+#if 1
+        if ((txrc->rate_idx_mask & (1 << rates[0].idx)) == 0) {
+            u32 rate_idx = rates[0].idx + 1;
+            u32 rate_idx_mask = txrc->rate_idx_mask >> rate_idx;
+            while (rate_idx_mask && (rate_idx_mask & 1) == 0) {
+                rate_idx_mask >>= 1;
+                rate_idx++;
+            }
+            if (rate_idx_mask)
+                rates[0].idx = rate_idx;
+            else {
+                WARN_ON(rate_idx_mask == 0);
+            }
+        }
+#endif
+        for (i = 0; i < total_rates; i++) {
+            if (rates[0].idx == ssv_11bgn_rate_table[i].dot11_rate_idx) {
+                break;
+            }
+        }
+        if (i < total_rates)
+            rc_rate = &ssv_rc->rc_table[i];
+        else {
+            WARN_ON("Failed to find matching low rate.");
+        }
+    }
+    if (rc_rate == NULL) {
+        if (conf_is_ht(&sc->hw->conf) &&
+            (sta->ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING))
+            tx_info->flags |= IEEE80211_TX_CTL_LDPC;
+        if (conf_is_ht(&sc->hw->conf) &&
+            (sta->ht_cap.cap & IEEE80211_HT_CAP_TX_STBC))
+            tx_info->flags |= (1 << IEEE80211_TX_CTL_STBC_SHIFT);
+        if (sc->sc_flags & SC_OP_FIXED_RATE) {
+            rateidx = sc->max_rate_idx;
+        } else {
+            if (rc_sta->rc_valid == false) {
+                rateidx = 0;
+            } else {
+                if ((rc_sta->rc_wsid >= SSV_RC_MAX_HARDWARE_SUPPORT) || (rc_sta->rc_wsid < 0)) {
+                    ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+                    {
+                        if ((rc_sta->ht_rc_type >= RC_TYPE_HT_SGI_20) &&
+                            (ssv_sta_priv->rx_data_rate < SSV62XX_RATE_MCS_INDEX)) {
+                            rateidx = rc_sta->pinfo.rinfo[spinfo->txrate_idx].rc_index;
+#if 0
+                            printk("RC %d rx %d tx %d\n", ssv_sta_priv->sta_idx,
+                                   ssv_sta_priv->rx_data_rate, rateidx);
+#endif
+                        } else {
+                            rateidx = ssv_sta_priv->rx_data_rate;
+                        }
+                    }
+                } else {
+                    if (rc_sta->is_ht) {
+#ifdef DISABLE_RATE_CONTROL_SAMPLE
+                        rateidx = rc_sta->ht.groups.rates[MCS_GROUP_RATES-1].rc_index;
+#else
+                        rateidx = rc_sta->pinfo.rinfo[spinfo->txrate_idx].rc_index;
+#endif
+                    } else {
+#if 0
+                        if (spinfo->monitoring && spinfo->probe_cnt > 0) {
+                            rateidx = rc_sta->pinfo.rinfo[spinfo->tmp_rate_idx].rc_index;
+                            spinfo->probe_cnt--;
+                        } else
+#endif
+                        {
+                            BUG_ON(spinfo->txrate_idx >= rc_sta->rc_num_rate);
+                            rateidx = rc_sta->pinfo.rinfo[spinfo->txrate_idx].rc_index;
+                        }
+                        if(rateidx<4) {
+                            if(rateidx) {
+                                if ((sc->sc_flags & SC_OP_SHORT_PREAMBLE)||(txrc->short_preamble)) {
+                                    rateidx += 3;
+                                }
+                            }
+                        }
+                    }
+                }
+            }
+        }
+        rc_rate = &ssv_rc->rc_table[rateidx];
+#if 1
+        if (spinfo->real_hw_index != rc_rate->hw_rate_idx) {
+            char string[24];
+            rateControlGetRate(rc_rate->hw_rate_idx,string);
+        }
+#endif
+        spinfo->real_hw_index = rc_rate->hw_rate_idx;
+        rates[0].count = 4;
+        rates[0].idx = rc_rate->dot11_rate_idx;
+        tx_info->control.rts_cts_rate_idx =
+            ssv_rc->rc_table[rc_rate->ctrl_rate_idx].dot11_rate_idx;
+        if (rc_rate->rc_flags & RC_FLAG_SHORT_PREAMBLE)
+            rates[0].flags |= IEEE80211_TX_RC_USE_SHORT_PREAMBLE;
+        if (rc_rate->rc_flags & RC_FLAG_HT) {
+            rates[0].flags |= IEEE80211_TX_RC_MCS;
+            if (rc_rate->rc_flags & RC_FLAG_HT_SGI)
+                rates[0].flags |= IEEE80211_TX_RC_SHORT_GI;
+            if (rc_rate->rc_flags & RC_FLAG_HT_GF)
+                rates[0].flags |= IEEE80211_TX_RC_GREEN_FIELD;
+        }
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0)
+        if (txrc->rts) {
+            rates[0].flags |= IEEE80211_TX_RC_USE_RTS_CTS;
+        }
+        if ((tx_info->control.vif &&
+             tx_info->control.vif->bss_conf.use_cts_prot) &&
+            (rc_rate->phy_type==WLAN_RC_PHY_OFDM ||
+             rc_rate->phy_type>WLAN_RC_PHY_OFDM)) {
+            rates[0].flags |= IEEE80211_TX_RC_USE_CTS_PROTECT;
+            tx_info->control.rts_cts_rate_idx = 1;
+        }
+#endif
+    }
+    rates[1].count = 0;
+    rates[1].idx = -1;
+    rates[SSV_DRATE_IDX].count = rc_rate->hw_rate_idx;
+    rc_rate = &ssv_rc->rc_table[rc_rate->ctrl_rate_idx];
+    rates[SSV_CRATE_IDX].count = rc_rate->hw_rate_idx;
+}
+int pide_frame_duration(size_t len,
+                        int rate, int short_preamble, int flags)
+{
+    int dur=0;
+    if (flags == WLAN_RC_PHY_CCK) {
+        dur = 10;
+        dur += short_preamble ? (72 + 24) : (144 + 48);
+        dur += DIV_ROUND_UP(8 * (len + 4) * 10, rate);
+    } else {
+        dur = 16;
+        dur += 16;
+        dur += 4;
+        dur += 4 * DIV_ROUND_UP((16 + 8 * (len + 4) + 6) * 10,
+                                4 * rate);
+    }
+    return dur;
+}
+static void ssv62xx_rc_caps(struct ssv_sta_rc_info *rc_sta)
+{
+    struct rc_pid_sta_info *spinfo;
+    struct rc_pid_info *pinfo;
+    struct rc_pid_rateinfo *rinfo;
+    int i;
+    spinfo = &rc_sta->spinfo;
+    pinfo = &rc_sta->pinfo;
+    memset(spinfo, 0, sizeof(struct rc_pid_sta_info));
+    memset(pinfo, 0, sizeof(struct rc_pid_info));
+    rinfo = rc_sta->pinfo.rinfo;
+    for(i=0; i<rc_sta->rc_num_rate; i++) {
+        rinfo[i].rc_index = ssv6xxx_rc_rate_set[rc_sta->rc_type][i+1];
+        rinfo[i].diff = i * RC_PID_NORM_OFFSET;
+        rinfo[i].index = (u16)i;
+        rinfo[i].perfect_tx_time = TDIFS + (TSLOT * 15 >> 1) + pide_frame_duration(1530,
+                                   ssv_11bgn_rate_table[rinfo[i].rc_index].rate_kbps/100, 1,ssv_11bgn_rate_table[rinfo[i].rc_index].phy_type) +
+                                   pide_frame_duration(10, ssv_11bgn_rate_table[rinfo[i].rc_index].rate_kbps/100, 1,ssv_11bgn_rate_table[rinfo[i].rc_index].phy_type);
+#if 1
+        printk("[RC]Init perfect_tx_time[%d][%d]\n",i,rinfo[i].perfect_tx_time);
+#endif
+        rinfo[i].throughput = 0;
+    }
+    if(rc_sta->is_ht) {
+        if(ssv6xxx_rc_rate_set[rc_sta->ht_rc_type][0] == 12)
+            spinfo->txrate_idx = 4;
+        else
+            spinfo->txrate_idx = 0;
+    } else {
+        spinfo->txrate_idx = ssv6xxx_rate_lowest_index(rc_sta);
+#ifdef DISABLE_RATE_CONTROL_SAMPLE
+        spinfo->txrate_idx = ssv6xxx_rate_highest_index(rc_sta);
+#endif
+    }
+    spinfo->real_hw_index = 0;
+    spinfo->probe_cnt = MAXPROBES;
+    spinfo->tmp_rate_idx = spinfo->txrate_idx;
+    spinfo->oldrate = spinfo->txrate_idx;
+    spinfo->last_sample = jiffies;
+    spinfo->last_report = jiffies;
+}
+static void ssv6xxx_rate_update_rc_type(void *priv, struct ieee80211_supported_band *sband,
+                                        struct ieee80211_sta *sta, void *priv_sta)
+{
+    struct ssv_softc *sc=priv;
+    struct ssv_hw *sh=sc->sh;
+    struct ssv_sta_rc_info *rc_sta=priv_sta;
+    int i;
+    u32 ht_supp_rates = 0;
+    BUG_ON(rc_sta->rc_valid == false);
+    printk("[I] %s(): \n", __FUNCTION__);
+    rc_sta->ht_supp_rates = 0;
+    rc_sta->rc_supp_rates = 0;
+    rc_sta->is_ht = 0;
+    if(sc->cur_channel->hw_value == 14) {
+        printk("[RC init ]Channel 14 support\n");
+        if((sta->supp_rates[sband->band] & (~0xfL)) == 0x0) {
+            printk("[RC init ]B only mode\n");
+            rc_sta->rc_type = RC_TYPE_B_ONLY;
+        } else {
+            printk("[RC init ]GB mode\n");
+            rc_sta->rc_type = RC_TYPE_LEGACY_GB;
+        }
+    } else if (sta->ht_cap.ht_supported == true) {
+        printk("[RC init ]HT support wsid\n");
+        for (i = 0; i < SSV_HT_RATE_MAX; i++) {
+            if (sta->ht_cap.mcs.rx_mask[i/MCS_GROUP_RATES] & (1<<(i%MCS_GROUP_RATES)))
+                ht_supp_rates |= BIT(i);
+        }
+        rc_sta->ht_supp_rates = ht_supp_rates;
+        if (sta->ht_cap.cap & IEEE80211_HT_CAP_GRN_FLD) {
+            rc_sta->rc_type = RC_TYPE_HT_GF;
+            rc_sta->ht_rc_type = RC_TYPE_HT_GF;
+        } else if (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) {
+            rc_sta->rc_type = RC_TYPE_SGI_20;
+            rc_sta->ht_rc_type = RC_TYPE_HT_SGI_20;
+        } else {
+            rc_sta->rc_type = RC_TYPE_LGI_20;
+            rc_sta->ht_rc_type = RC_TYPE_HT_LGI_20;
+        }
+    } else {
+        if((sta->supp_rates[sband->band] & (~0xfL)) == 0x0) {
+            rc_sta->rc_type = RC_TYPE_B_ONLY;
+            printk("[RC init ]B only mode\n");
+        } else {
+            rc_sta->rc_type = RC_TYPE_LEGACY_GB;
+            printk("[RC init ]legacy G mode\n");
+        }
+    }
+#ifdef CONFIG_SSV_DPD
+#ifdef SSV_SUPPORT_HAL
+    if (rc_sta->rc_type == RC_TYPE_B_ONLY) {
+        SHAL_DPD_ENABLE(sh, false);
+    } else {
+        SHAL_DPD_ENABLE(sh, true);
+    }
+#else
+#ifdef CONFIG_SSV_CABRIO_E
+    if(rc_sta->rc_type == RC_TYPE_B_ONLY) {
+        SMAC_REG_WRITE(sh, ADR_TX_FE_REGISTER, 0x3D3E84FE);
+        SMAC_REG_WRITE(sh, ADR_RX_FE_REGISTER_1, 0x1457D79);
+        SMAC_REG_WRITE(sh, ADR_DPD_CONTROL, 0x0);
+    } else {
+        SMAC_REG_WRITE(sh, ADR_TX_FE_REGISTER, 0x3CBE84FE);
+        SMAC_REG_WRITE(sh, ADR_RX_FE_REGISTER_1, 0x4507F9);
+        SMAC_REG_WRITE(sh, ADR_DPD_CONTROL, 0x3);
+    }
+#endif
+#endif
+#endif
+    if((rc_sta->rc_type != RC_TYPE_B_ONLY) && (rc_sta->rc_type != RC_TYPE_LEGACY_GB)) {
+        if ((sta->ht_cap.ht_supported) && (sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_TX)) {
+            rc_sta->is_ht = 1;
+            ssv62xx_ht_rc_caps(ssv6xxx_rc_rate_set, rc_sta);
+        }
+    }
+    {
+        rc_sta->rc_num_rate = (u8)ssv6xxx_rc_rate_set[rc_sta->rc_type][0];
+        if((rc_sta->rc_type == RC_TYPE_HT_GF) ||
+           (rc_sta->rc_type == RC_TYPE_LGI_20) || (rc_sta->rc_type == RC_TYPE_SGI_20)) {
+            if(rc_sta->rc_num_rate == 12) {
+                rc_sta->rc_supp_rates = sta->supp_rates[sband->band] & 0xfL;
+                rc_sta->rc_supp_rates |= (ht_supp_rates << 4);
+            } else
+                rc_sta->rc_supp_rates = ht_supp_rates;
+        } else if(rc_sta->rc_type == RC_TYPE_LEGACY_GB)
+            rc_sta->rc_supp_rates = sta->supp_rates[sband->band];
+        else if(rc_sta->rc_type == RC_TYPE_B_ONLY)
+            rc_sta->rc_supp_rates = sta->supp_rates[sband->band] & 0xfL;
+        ssv62xx_rc_caps(rc_sta);
+    }
+}
+#if LINUX_VERSION_CODE > 0x030500
+static void ssv6xxx_rate_update(void *priv, struct ieee80211_supported_band *sband,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,13,0)
+                                struct cfg80211_chan_def *chandef,
+#endif
+                                struct ieee80211_sta *sta, void *priv_sta,
+                                u32 changed)
+#else
+static void ssv6xxx_rate_update(void *priv, struct ieee80211_supported_band *sband,
+                                struct ieee80211_sta *sta, void *priv_sta,
+                                u32 changed, enum nl80211_channel_type oper_chan_type)
+#endif
+{
+    ssv6xxx_rate_update_rc_type(priv, sband, sta, priv_sta);
+}
+static void ssv6xxx_rate_init(void *priv, struct ieee80211_supported_band *sband,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,13,0)
+                              struct cfg80211_chan_def *chandef,
+#endif
+                              struct ieee80211_sta *sta, void *priv_sta)
+{
+    ssv6xxx_rate_update_rc_type(priv, sband, sta, priv_sta);
+}
+static void *ssv6xxx_rate_alloc_sta(void *priv, struct ieee80211_sta *sta, gfp_t gfp)
+{
+    struct ssv_sta_priv_data *sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+#ifndef RC_STA_DIRECT_MAP
+    struct ssv_softc *sc = priv;
+    struct ssv_rate_ctrl *ssv_rc = sc->rc;
+    int s;
+    sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+    for(s=0; s<SSV_RC_MAX_STA; s++) {
+        if (ssv_rc->sta_rc_info[s].rc_valid == false) {
+            printk("%s(): use index %d\n", __FUNCTION__, s);
+            memset(&ssv_rc->sta_rc_info[s], 0, sizeof(struct ssv_sta_rc_info));
+            ssv_rc->sta_rc_info[s].rc_valid = true;
+            ssv_rc->sta_rc_info[s].rc_wsid = -1;
+            sta_priv->rc_idx = s;
+            return &ssv_rc->sta_rc_info[s];
+        }
+    }
+    return NULL;
+#else
+    sta_priv->rc_idx = (-1);
+    return sta_priv;
+#endif
+}
+static void ssv6xxx_rate_free_sta(void *priv, struct ieee80211_sta *sta,
+                                  void *priv_sta)
+{
+    struct ssv_sta_rc_info *rc_sta=priv_sta;
+    rc_sta->rc_valid = false;
+}
+static void *ssv6xxx_rate_alloc(struct ieee80211_hw *hw, struct dentry *debugfsdir)
+{
+    struct ssv_softc *sc=hw->priv;
+    struct ssv_rate_ctrl *ssv_rc;
+    sc->rc = kzalloc(sizeof(struct ssv_rate_ctrl), GFP_KERNEL);
+    if (!sc->rc) {
+        printk("%s(): Unable to allocate RC structure !\n",
+               __FUNCTION__);
+        return NULL;
+    }
+    memset(sc->rc, 0, sizeof(struct ssv_rate_ctrl));
+    ssv_rc = (struct ssv_rate_ctrl *)sc->rc;
+    ssv_rc->rc_table = ssv_11bgn_rate_table;
+    return hw->priv;
+}
+static void ssv6xxx_rate_free(void *priv)
+{
+    struct ssv_softc *sc=priv;
+    if (sc->rc) {
+        kfree(sc->rc);
+        sc->rc = NULL;
+    }
+}
+static struct rate_control_ops ssv_rate_ops = {
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,15,0)
+    .module = NULL,
+#endif
+    .name = "ssv6xxx_rate_control",
+    .tx_status = ssv6xxx_tx_status,
+    .get_rate = ssv6xxx_get_rate,
+    .rate_init = ssv6xxx_rate_init,
+    .rate_update = ssv6xxx_rate_update,
+    .alloc = ssv6xxx_rate_alloc,
+    .free = ssv6xxx_rate_free,
+    .alloc_sta = ssv6xxx_rate_alloc_sta,
+    .free_sta = ssv6xxx_rate_free_sta,
+};
+#ifndef SSV_SUPPORT_HAL
+void ssv6xxx_rc_mac80211_rate_idx(struct ssv_softc *sc,
+                                  int hw_rate_idx, struct ieee80211_rx_status *rxs)
+{
+    struct ssv_rate_ctrl *ssv_rc=sc->rc;
+    struct ssv_rc_rate *rc_rate;
+    BUG_ON(hw_rate_idx>=RATE_TABLE_SIZE &&
+           hw_rate_idx < 0);
+    rc_rate = &ssv_rc->rc_table[hw_rate_idx];
+    if (rc_rate->rc_flags & RC_FLAG_HT) {
+        rxs->flag |= RX_FLAG_HT;
+        if (rc_rate->rc_flags & RC_FLAG_HT_SGI)
+            rxs->flag |= RX_FLAG_SHORT_GI;
+    } else {
+        if (rc_rate->rc_flags & RC_FLAG_SHORT_PREAMBLE)
+            rxs->flag |= RX_FLAG_SHORTPRE;
+    }
+    rxs->rate_idx = rc_rate->dot11_rate_idx;
+}
+#endif
+void ssv6xxx_rc_hw_rate_idx(struct ssv_softc *sc,
+                            struct ieee80211_tx_info *info, struct ssv_rate_info *sr)
+{
+    struct ieee80211_tx_rate *tx_rate;
+    struct ssv_rate_ctrl *ssv_rc=sc->rc;
+    tx_rate = &info->control.rates[0];
+    sr->d_flags = (ssv_rc->rc_table[tx_rate[SSV_DRATE_IDX].count].phy_type == WLAN_RC_PHY_OFDM) ? IEEE80211_RATE_ERP_G:0;
+    sr->d_flags |= (ssv_rc->rc_table[tx_rate[SSV_DRATE_IDX].count].rc_flags & RC_FLAG_SHORT_PREAMBLE)? IEEE80211_RATE_SHORT_PREAMBLE:0;
+    sr->c_flags = (ssv_rc->rc_table[tx_rate[SSV_CRATE_IDX].count].phy_type == WLAN_RC_PHY_OFDM) ? IEEE80211_RATE_ERP_G:0;
+    sr->c_flags |= (ssv_rc->rc_table[tx_rate[SSV_CRATE_IDX].count].rc_flags & RC_FLAG_SHORT_PREAMBLE)? IEEE80211_RATE_SHORT_PREAMBLE:0;
+    sr->drate_kbps = ssv_rc->rc_table[tx_rate[SSV_DRATE_IDX].count].rate_kbps;
+    sr->drate_hw_idx = tx_rate[SSV_DRATE_IDX].count;
+    sr->crate_kbps = ssv_rc->rc_table[tx_rate[SSV_CRATE_IDX].count].rate_kbps;
+    sr->crate_hw_idx = tx_rate[SSV_CRATE_IDX].count;
+}
+#ifdef RATE_CONTROL_REALTIME_UPDATE
+u8 ssv6xxx_rc_hw_rate_update_check(struct sk_buff *skb, struct ssv_softc *sc, u32 do_rts_cts)
+{
+    int ret = 0;
+    struct ssv_rate_ctrl *ssv_rc = sc->rc;
+    struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
+    struct SKB_info_st *skb_info = (struct SKB_info_st *)skb->head;
+    struct ieee80211_sta *sta = skb_info->sta;
+    struct ieee80211_tx_rate *rates = &tx_info->control.rates[0];
+    struct ssv_rc_rate *rc_rate = NULL;
+    u8 rateidx=0;
+    struct ssv_sta_rc_info *rc_sta = NULL;
+    struct rc_pid_sta_info *spinfo;
+    struct ssv_sta_priv_data *sta_priv = NULL;
+    unsigned long period=0;
+    if (sc->sc_flags & SC_OP_FIXED_RATE)
+        return ret;
+    if(sta == NULL)
+        return ret;
+    sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+    if(sta_priv == NULL) {
+#ifdef RATE_CONTROL_DEBUG
+        printk("%s sta_priv == NULL \n\r", __FUNCTION__);
+#endif
+        return ret;
+    }
+    if((sta_priv->rc_idx < 0)||(sta_priv->rc_idx >= SSV_RC_MAX_HARDWARE_SUPPORT)) {
+#ifdef RATE_CONTROL_DEBUG
+        printk("%s rc_idx %x illegal \n\r", __FUNCTION__, sta_priv->rc_idx);
+#endif
+        return ret;
+    }
+    rc_sta = &ssv_rc->sta_rc_info[sta_priv->rc_idx];
+    if(rc_sta->rc_valid == false) {
+#ifdef RATE_CONTROL_DEBUG
+        printk("%s rc_valid false \n\r", __FUNCTION__);
+#endif
+        return ret;
+    }
+    spinfo= &rc_sta->spinfo;
+    period = msecs_to_jiffies(RC_PID_REPORT_INTERVAL);
+    if (time_after(jiffies, spinfo->last_report + period)) {
+        ret |= RC_FIRMWARE_REPORT_FLAG;
+        spinfo->last_report = jiffies;
+    }
+    {
+        if (spinfo->monitoring) {
+            if(spinfo->probe_report_flag == 0) {
+                ret |= RC_FIRMWARE_REPORT_FLAG;
+                spinfo->last_report = jiffies;
+                spinfo->probe_report_flag = 1;
+                rateidx = spinfo->real_hw_index;
+            } else if (spinfo->probe_cnt > 0 && spinfo->probe_report_flag) {
+                rateidx = rc_sta->pinfo.rinfo[spinfo->tmp_rate_idx].rc_index;
+                spinfo->probe_cnt--;
+                if(spinfo->probe_cnt == 0) {
+                    ret |= RC_FIRMWARE_REPORT_FLAG;
+                    spinfo->last_report = jiffies;
+                }
+            } else
+                rateidx = spinfo->real_hw_index;
+        } else
+            rateidx = spinfo->real_hw_index;
+    }
+    rc_rate = &ssv_rc->rc_table[rateidx];
+#ifdef RATE_CONTROL_STUPID_DEBUG
+    if (spinfo->monitoring && (spinfo->probe_cnt)) {
+        char string[24];
+        rateControlGetRate(rc_rate->hw_rate_idx,string);
+        printk("[RC]Probe rate[%s]\n",string);
+    }
+#endif
+    if(rc_rate == NULL)
+        return ret;
+    if(rc_rate->hw_rate_idx != rates[SSV_DRATE_IDX].count) {
+        rates[0].flags = 0;
+        if (rc_rate->rc_flags & RC_FLAG_SHORT_PREAMBLE)
+            rates[0].flags |= IEEE80211_TX_RC_USE_SHORT_PREAMBLE;
+        if (rc_rate->rc_flags & RC_FLAG_HT) {
+            rates[0].flags |= IEEE80211_TX_RC_MCS;
+            if (rc_rate->rc_flags & RC_FLAG_HT_SGI)
+                rates[0].flags |= IEEE80211_TX_RC_SHORT_GI;
+            if (rc_rate->rc_flags & RC_FLAG_HT_GF)
+                rates[0].flags |= IEEE80211_TX_RC_GREEN_FIELD;
+        }
+        rates[SSV_DRATE_IDX].count = rc_rate->hw_rate_idx;
+        if (do_rts_cts & IEEE80211_TX_RC_USE_CTS_PROTECT) {
+            rates[SSV_CRATE_IDX].count = 0;
+        } else {
+            rc_rate = &ssv_rc->rc_table[rc_rate->ctrl_rate_idx];
+            rates[SSV_CRATE_IDX].count = rc_rate->hw_rate_idx;
+        }
+        ret |= 0x1;
+    }
+    return ret;
+}
+#endif
+#ifndef SSV_SUPPORT_HAL
+void ssv6xxx_rc_hw_reset(struct ssv_softc *sc, int rc_idx, int hwidx)
+{
+    struct ssv_rate_ctrl *ssv_rc=sc->rc;
+    struct ssv_sta_rc_info *rc_sta;
+    u32 rc_hw_reg[] = { ADR_MTX_MIB_WSID0, ADR_MTX_MIB_WSID1 };
+    BUG_ON(rc_idx >= SSV_RC_MAX_STA);
+    rc_sta = &ssv_rc->sta_rc_info[rc_idx];
+    if (hwidx >=0 && hwidx<SSV_NUM_HW_STA) {
+        rc_sta->rc_wsid = hwidx;
+        printk("rc_wsid[%d] rc_idx[%d]\n",rc_sta[rc_idx].rc_wsid,rc_idx);
+        SMAC_REG_WRITE(sc->sh, rc_hw_reg[hwidx], 0x40000000);
+    } else {
+        rc_sta->rc_wsid = -1;
+    }
+}
+#define UPDATE_PHY_INFO_ACK_RATE(_phy_info,_ack_rate_idx) ( _phy_info = (_phy_info&0xfffffc0f)|(_ack_rate_idx<<4))
+int ssv6xxx_rc_update_bmode_ctrl_rate(struct ssv_softc *sc, int rate_tbl_idx, int ctrl_rate_idx)
+{
+    u32 temp32;
+    struct ssv_hw *sh = sc->sh;
+    u32 addr;
+    addr = sh->hw_pinfo+rate_tbl_idx*4;
+    ssv_11bgn_rate_table[rate_tbl_idx].ctrl_rate_idx = ctrl_rate_idx;
+    SMAC_REG_READ(sh, addr, &temp32);
+    UPDATE_PHY_INFO_ACK_RATE(temp32, ctrl_rate_idx);
+    SMAC_REG_WRITE(sh, addr, temp32);
+    SMAC_REG_CONFIRM(sh, addr, temp32);
+    return 0;
+}
+void ssv6xxx_rc_update_basic_rate(struct ssv_softc *sc, u32 basic_rates)
+{
+    int i;
+    int rate_idx, pre_rate_idx = 0;
+    for(i=0; i<4; i++) {
+        if(((basic_rates>>i)&0x01)) {
+            rate_idx = i;
+            pre_rate_idx = i;
+        } else
+            rate_idx = pre_rate_idx;
+        ssv6xxx_rc_update_bmode_ctrl_rate(sc, i, rate_idx);
+        if(i)
+            ssv6xxx_rc_update_bmode_ctrl_rate(sc, i+3, rate_idx);
+    }
+}
+#endif
+int ssv6xxx_pid_rate_control_register(void)
+{
+    return ieee80211_rate_control_register(&ssv_rate_ops);
+}
+void ssv6xxx_pid_rate_control_unregister(void)
+{
+    ieee80211_rate_control_unregister(&ssv_rate_ops);
+}
+#ifndef SSV_SUPPORT_HAL
+void ssv6xxx_rc_rx_data_handler(struct ieee80211_hw *hw, struct sk_buff *skb, u32 rate_index)
+{
+    struct ssv_softc *sc = hw->priv;
+    struct ieee80211_sta *sta;
+    struct ssv_sta_priv_data *ssv_sta_priv;
+    sta = ssv6xxx_find_sta_by_rx_skb(sc, skb);
+    if(sta == NULL) {
+        return;
+    }
+    ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+    ssv_sta_priv->rx_data_rate = rate_index;
+}
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smac/ssv_rc.h b/drivers/net/wireless/ssv6x5x/smac/ssv_rc.h
new file mode 100644
index 000000000..58a40fbcf
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/ssv_rc.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV_RC_H_
+#define _SSV_RC_H_
+#include "ssv_rc_common.h"
+#define RC_PID_REPORT_INTERVAL 40
+#define RC_PID_INTERVAL 125
+#define RC_PID_DO_ARITH_RIGHT_SHIFT(x,y) \
+ ((x) < 0 ? -((-(x)) >> (y)) : (x) >> (y))
+#define RC_PID_NORM_OFFSET 3
+#define RC_PID_SMOOTHING_SHIFT 1
+#define RC_PID_SMOOTHING (1 << RC_PID_SMOOTHING_SHIFT)
+#define RC_PID_COEFF_P 15
+#define RC_PID_COEFF_I 15
+#define RC_PID_COEFF_D 5
+#define MAXPROBES 3
+#define SSV_DRATE_IDX (2)
+#define SSV_CRATE_IDX (3)
+struct ssv_softc;
+struct ssv_rc_rate *ssv6xxx_rc_get_rate(int rc_index);
+#ifdef RATE_CONTROL_REALTIME_UPDATE
+u8 ssv6xxx_rc_hw_rate_update_check(struct sk_buff *skb, struct ssv_softc *sc, u32 do_rts_cts);
+#endif
+#ifndef SSV_SUPPORT_HAL
+void ssv6xxx_rc_mac80211_rate_idx(struct ssv_softc *sc, int hw_rate_idx,
+                                  struct ieee80211_rx_status *rxs);
+void ssv6xxx_rc_hw_reset(struct ssv_softc *sc, int rc_idx, int hwidx);
+void ssv6xxx_rc_rx_data_handler(struct ieee80211_hw *hw, struct sk_buff *skb, u32 rate_index);
+void ssv6xxx_rc_update_basic_rate(struct ssv_softc *sc, u32 basic_rates);
+#endif
+void ssv6xxx_legacy_report_handler(struct ssv_softc *sc,struct sk_buff *skb,struct ssv_sta_rc_info *rc_sta);
+#if (!defined(SSV_SUPPORT_HAL)||defined(SSV_SUPPORT_SSV6051))
+int ssv6xxx_pid_rate_control_register(void);
+void ssv6xxx_pid_rate_control_unregister(void);
+void ssv6xxx_rc_hw_rate_idx(struct ssv_softc *sc,
+                            struct ieee80211_tx_info *info, struct ssv_rate_info *sr);
+#endif
+int pide_frame_duration(size_t len, int rate, int short_preamble, int flags);
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smac/ssv_rc_common.h b/drivers/net/wireless/ssv6x5x/smac/ssv_rc_common.h
new file mode 100644
index 000000000..df8b7973b
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/ssv_rc_common.h
@@ -0,0 +1,181 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV_RC_COM_H_
+#define _SSV_RC_COM_H_
+#define SSV_RC_MAX_STA 8
+#define MCS_GROUP_RATES 8
+#define SSV_HT_RATE_MAX 8
+#define TDIFS 34
+#define TSLOT 9
+#define RC_FLAG_INVALID 0x00000001
+#define RC_FLAG_LEGACY 0x00000002
+#define RC_FLAG_HT 0x00000004
+#define RC_FLAG_HT_SGI 0x00000008
+#define RC_FLAG_HT_GF 0x00000010
+#define RC_FLAG_SHORT_PREAMBLE 0x00000020
+enum ssv6xxx_rc_phy_type {
+    WLAN_RC_PHY_CCK,
+    WLAN_RC_PHY_OFDM,
+    WLAN_RC_PHY_HT_20_SS_LGI,
+    WLAN_RC_PHY_HT_20_SS_SGI,
+    WLAN_RC_PHY_HT_20_SS_GF,
+};
+#define RATE_TABLE_SIZE 39
+#define RC_STA_VALID 0x00000001
+#define RC_STA_CAP_HT 0x00000002
+#define RC_STA_CAP_GF 0x00000004
+#define RC_STA_CAP_SGI_20 0x00000008
+#define RC_STA_CAP_SHORT_PREAMBLE 0x00000010
+#define SSV62XX_G_RATE_INDEX 7
+#define SSV62XX_RATE_MCS_INDEX 15
+#define SSV62XX_RATE_MCS_LGI_INDEX 15
+#define SSV62XX_RATE_MCS_SGI_INDEX 23
+#define SSV62XX_RATE_MCS_GREENFIELD_INDEX 31
+enum ssv_rc_rate_type {
+    RC_TYPE_B_ONLY=0,
+    RC_TYPE_LEGACY_GB,
+    RC_TYPE_SGI_20,
+    RC_TYPE_LGI_20,
+    RC_TYPE_HT_SGI_20,
+    RC_TYPE_HT_LGI_20,
+    RC_TYPE_HT_GF,
+    RC_TYPE_MAX,
+};
+struct ssv_rate_info {
+    int crate_kbps;
+    int crate_hw_idx;
+    int drate_kbps;
+    int drate_hw_idx;
+    u32 d_flags;
+    u32 c_flags;
+};
+struct ssv_rc_rate {
+    u32 rc_flags;
+    u16 phy_type;
+    u32 rate_kbps;
+    u8 dot11_rate_idx;
+    u8 ctrl_rate_idx;
+    u8 hw_rate_idx;
+    u8 arith_shift;
+    u8 target_pf;
+};
+struct rc_pid_sta_info {
+    unsigned long last_sample;
+    unsigned long last_report;
+    u16 tx_num_failed;
+    u16 tx_num_xmit;
+    u8 probe_report_flag;
+    u8 probe_wating_times;
+    u8 real_hw_index;
+    int txrate_idx;
+    u8 last_pf;
+    s32 err_avg_sc;
+    int last_dlr;
+    u8 feedback_probes;
+    u8 monitoring;
+    u8 oldrate;
+    u8 tmp_rate_idx;
+    u8 probe_cnt;
+};
+struct rc_pid_rateinfo {
+    u16 rc_index;
+    u16 index;
+    s32 diff;
+    u16 perfect_tx_time;
+    u32 throughput;
+    unsigned long this_attempt;
+    unsigned long this_success;
+    unsigned long this_fail;
+    u64 attempt;
+    u64 success;
+    u64 fail;
+};
+struct rc_pid_info {
+    unsigned int target;
+#if 0
+    u8 coeff_p;
+    u8 coeff_i;
+    u8 coeff_d;
+    u8 smoothing_shift;
+    u8 sharpen_factor;
+    u8 sharpen_duration;
+    u8 norm_offset;
+#endif
+    int oldrate;
+    struct rc_pid_rateinfo rinfo[12];
+};
+struct mcs_group {
+    unsigned int duration[MCS_GROUP_RATES];
+};
+struct minstrel_rate_stats {
+    u16 rc_index;
+    unsigned int attempts, last_attempts;
+    unsigned int success, last_success;
+    u64 att_hist, succ_hist;
+    unsigned int cur_tp;
+    unsigned int cur_prob, probability;
+    unsigned int retry_count;
+    unsigned int retry_count_rtscts;
+    u8 sample_skipped;
+};
+struct minstrel_mcs_group_data {
+    u8 index;
+    u8 column;
+    unsigned int max_tp_rate;
+    unsigned int max_tp_rate2;
+    unsigned int max_prob_rate;
+    struct minstrel_rate_stats rates[MCS_GROUP_RATES];
+};
+struct ssv62xx_ht {
+    unsigned int ampdu_len;
+    unsigned int ampdu_packets;
+    unsigned int avg_ampdu_len;
+    unsigned int max_tp_rate;
+    unsigned int max_tp_rate2;
+    unsigned int max_prob_rate;
+    int first_try_count;
+    int second_try_count;
+    int other_try_count;
+    unsigned long stats_update;
+    unsigned int overhead;
+    unsigned int overhead_rtscts;
+    unsigned int total_packets;
+    unsigned int sample_packets;
+    u8 sample_wait;
+    u8 sample_tries;
+    u8 sample_count;
+    u8 sample_slow;
+    struct minstrel_mcs_group_data groups;
+};
+struct ssv_sta_rc_info {
+    u8 rc_valid;
+    u8 rc_type;
+    u8 rc_num_rate;
+    s8 rc_wsid;
+    u8 ht_rc_type;
+    u8 is_ht;
+    u32 rc_supp_rates;
+    u32 ht_supp_rates;
+    struct rc_pid_info pinfo;
+    struct rc_pid_sta_info spinfo;
+    struct ssv62xx_ht ht;
+};
+struct ssv_rate_ctrl {
+    struct ssv_rc_rate *rc_table;
+    struct ssv_sta_rc_info sta_rc_info[SSV_RC_MAX_STA];
+};
+#define HT_RC_UPDATE_INTERVAL 1000
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smac/ssv_rc_minstrel.c b/drivers/net/wireless/ssv6x5x/smac/ssv_rc_minstrel.c
new file mode 100644
index 000000000..4a6cf609e
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/ssv_rc_minstrel.c
@@ -0,0 +1,735 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/version.h>
+#include <linux/debugfs.h>
+#include <ssv6200.h>
+#include "dev.h"
+#include "ssv_rc_minstrel.h"
+#include <hal.h>
+#include <linux_80211.h>
+#define SSV_MINSTREL_ACK_LEN 39
+#define SAMPLE_COLUMNS 10
+#define SAMPLE_TBL(_sta_priv,_idx,_col) \
+  _sta_priv->sample_table[(_idx * SAMPLE_COLUMNS) + _col]
+int minstrel_ewma(int old, int new, int weight)
+{
+    return (new * (100 - weight) + old * weight) / 100;
+}
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,7,0)
+int ieee80211_frame_duration(enum nl80211_band band, size_t len,
+                             int rate, int erp, int short_preamble)
+#else
+int ieee80211_frame_duration(enum ieee80211_band band, size_t len,
+                             int rate, int erp, int short_preamble)
+#endif
+{
+    int dur;
+    if (band == INDEX_80211_BAND_5GHZ || erp) {
+        dur = 16;
+        dur += 16;
+        dur += 4;
+        dur += 4 * DIV_ROUND_UP((16 + 8 * (len + 4) + 6) * 10, 4 * rate);
+    } else {
+        dur = 10;
+        dur += short_preamble ? (72 + 24) : (144 + 48);
+        dur += DIV_ROUND_UP(8 * (len + 4) * 10, rate);
+    }
+    return dur;
+}
+static void ssv_minstrel_update_stats(struct ssv_softc *sc, struct ssv_minstrel_priv *smp,
+                                      struct ssv_minstrel_sta_priv *minstrel_sta_priv)
+{
+    struct ssv_minstrel_sta_info *smi = (struct ssv_minstrel_sta_info *)&minstrel_sta_priv->legacy;
+    u32 max_tp = 0, index_max_tp = 0, index_max_tp2 = 0;
+    u32 max_prob = 0, index_max_prob = 0;
+    u32 usecs;
+    int i;
+    bool no_update = false;
+    struct rc_setting *rc_setting = &sc->sh->cfg.rc_setting;
+    for (i = 0; i < smi->n_rates; i++) {
+        struct ssv_minstrel_rate *mr = &minstrel_sta_priv->ratelist[i];
+        if (mr->attempts)
+            break;
+    }
+    if (i == smi->n_rates) {
+        no_update = true;
+    }
+    smi->stats_update = jiffies;
+    if (no_update == false) {
+        for (i = 0; i < smi->n_rates; i++) {
+            struct ssv_minstrel_rate *mr = &minstrel_sta_priv->ratelist[i];
+            usecs = mr->perfect_tx_time;
+            if (!usecs)
+                usecs = 1000000;
+            if (mr->attempts) {
+                mr->succ_hist += mr->success;
+                mr->att_hist += mr->attempts;
+                mr->cur_prob = MINSTREL_FRAC(mr->success, mr->attempts);
+                if ((!mr->att_hist) || (mr->probability < MINSTREL_FRAC(10, 100)))
+                    mr->probability = mr->cur_prob;
+                else
+                    mr->probability = minstrel_ewma(mr->probability, mr->cur_prob, EWMA_LEVEL);
+                mr->cur_tp = mr->probability * (1000000 / usecs);
+                mr->last_jiffies = jiffies;
+            } else {
+                if (time_after(jiffies, mr->last_jiffies + msecs_to_jiffies(rc_setting->aging_period))) {
+                    if (sc->bScanning == false) {
+                        mr->probability = minstrel_ewma(mr->probability, 0, EWMA_LEVEL);
+                    }
+                    mr->last_jiffies = jiffies;
+                }
+            }
+            mr->last_success = mr->success;
+            mr->last_attempts = mr->attempts;
+            mr->success = 0;
+            mr->attempts = 0;
+            if ((mr->probability > MINSTREL_FRAC(95, 100)) || (mr->probability < MINSTREL_FRAC(10, 100))) {
+                mr->adjusted_retry_count = mr->retry_count >> 1;
+                if (mr->adjusted_retry_count > 2)
+                    mr->adjusted_retry_count = 2;
+                mr->sample_limit = 4;
+            } else {
+                mr->sample_limit = -1;
+                mr->adjusted_retry_count = mr->retry_count;
+            }
+            if (!mr->adjusted_retry_count)
+                mr->adjusted_retry_count = 2;
+        }
+    }
+    for (i = 0; i < smi->n_rates; i++) {
+        struct ssv_minstrel_rate *mr = &minstrel_sta_priv->ratelist[i];
+        if (mr->bitrate == 20)
+            continue;
+        if (max_tp < mr->cur_tp) {
+            index_max_tp = i;
+            max_tp = mr->cur_tp;
+        }
+        if (max_prob < mr->probability) {
+            index_max_prob = i;
+            max_prob = mr->probability;
+        }
+    }
+    max_tp = 0;
+    for (i = 0; i < smi->n_rates; i++) {
+        struct ssv_minstrel_rate *mr = &minstrel_sta_priv->ratelist[i];
+        if (mr->bitrate == 20)
+            continue;
+        if (i == index_max_tp)
+            continue;
+        if (max_tp < mr->cur_tp) {
+            index_max_tp2 = i;
+            max_tp = mr->cur_tp;
+        }
+    }
+    smi->max_tp_rate = index_max_tp;
+    if (smi->max_tp_rate > 1) {
+        smi->max_tp_rate2 = smi->max_tp_rate - 1;
+    } else {
+        smi->max_tp_rate2 = 0;
+    }
+    if (smi->max_tp_rate2 > index_max_prob) {
+        smi->max_prob_rate = index_max_prob;
+    } else {
+        if (smi->max_tp_rate2 > 1) {
+            smi->max_prob_rate = smi->max_tp_rate2 - 1;
+        } else {
+            smi->max_prob_rate = 0;
+        }
+    }
+    if (sc->sh->cfg.rc_log) {
+        printk("%s():\n", __FUNCTION__);
+        for (i = 0; i < smi->n_rates; i++) {
+            struct ssv_minstrel_rate *mr = &minstrel_sta_priv->ratelist[i];
+            printk("bitrate[%d], succ_hist=%llu, att_hist=%llu, cur_prob=%d, probability=%d, cur_tp=%d\n",
+                   mr->bitrate, mr->succ_hist, mr->att_hist, mr->cur_prob, mr->probability, mr->cur_tp);
+        }
+        printk("\n\n");
+        printk("max_tp_rate=%d, max_tp_rate2=%d, max_prob_rate=%d\n\n",
+               smi->max_tp_rate, smi->max_tp_rate2, smi->max_prob_rate);
+    }
+}
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,7,0)
+static void ssv_calc_rate_durations(enum nl80211_band band, struct ssv_minstrel_rate *d,
+                                    struct ieee80211_rate *rate, int use_short_preamble)
+#else
+static void ssv_calc_rate_durations(enum ieee80211_band band, struct ssv_minstrel_rate *d,
+                                    struct ieee80211_rate *rate, int use_short_preamble)
+#endif
+{
+    int erp = !!(rate->flags & IEEE80211_RATE_ERP_G);
+    int short_preamble = !!(rate->flags & IEEE80211_RATE_SHORT_PREAMBLE);
+    d->perfect_tx_time = ieee80211_frame_duration(band, 1200, rate->bitrate,
+                         erp, (use_short_preamble && short_preamble));
+    d->ack_time = ieee80211_frame_duration(band, SSV_MINSTREL_ACK_LEN, rate->bitrate,
+                                           erp, (use_short_preamble && short_preamble));
+}
+static inline unsigned int minstrel_get_retry_count(struct ssv_minstrel_rate *mr,
+        struct ieee80211_tx_info *info)
+{
+    unsigned int retry = mr->adjusted_retry_count;
+    if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS)
+        retry = max(2U, min(mr->retry_count_rtscts, retry));
+    else if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT)
+        retry = max(2U, min(mr->retry_count_cts, retry));
+    return retry;
+}
+static int minstrel_get_next_sample(struct ssv_minstrel_sta_priv *minstrel_sta_priv)
+{
+    struct ssv_minstrel_sta_info *smi = (struct ssv_minstrel_sta_info *)&minstrel_sta_priv->legacy;
+    unsigned int sample_ndx;
+    sample_ndx = SAMPLE_TBL(minstrel_sta_priv, smi->sample_idx, smi->sample_column);
+    smi->sample_idx++;
+    if ((int) smi->sample_idx > (smi->n_rates - 2)) {
+        smi->sample_idx = 0;
+        smi->sample_column++;
+        if (smi->sample_column >= SAMPLE_COLUMNS)
+            smi->sample_column = 0;
+    }
+    return sample_ndx;
+}
+static void ssv_init_sample_table(struct ssv_minstrel_sta_priv *minstrel_sta_priv)
+{
+    struct ssv_minstrel_sta_info *smi = (struct ssv_minstrel_sta_info *)&minstrel_sta_priv->legacy;
+    unsigned int i, col, new_idx;
+    unsigned int n_srates = smi->n_rates - 1;
+    u8 rnd[8];
+    smi->sample_column = 0;
+    smi->sample_idx = 0;
+    memset(minstrel_sta_priv->sample_table, 0, SAMPLE_COLUMNS * smi->n_rates);
+    for (col = 0; col < SAMPLE_COLUMNS; col++) {
+        for (i = 0; i < n_srates; i++) {
+            get_random_bytes(rnd, sizeof(rnd));
+            new_idx = (i + rnd[i & 7]) % n_srates;
+            while (SAMPLE_TBL(minstrel_sta_priv, new_idx, col) != 0)
+                new_idx = (new_idx + 1) % n_srates;
+            SAMPLE_TBL(minstrel_sta_priv, new_idx, col) = i + 1;
+        }
+    }
+}
+static void ssv_minstrel_tx_status(void *priv, struct ieee80211_supported_band *sband,
+                                   struct ieee80211_sta *sta, void *priv_sta,
+                                   struct sk_buff *skb)
+{
+    struct ssv_softc *sc;
+    struct ieee80211_hdr *hdr;
+    struct ssv_minstrel_sta_priv *minstrel_sta_priv;
+    struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
+    __le16 fc;
+    hdr = (struct ieee80211_hdr *)skb->data;
+    fc = hdr->frame_control;
+    if (!priv_sta || !ieee80211_is_data_qos(fc))
+        return;
+    minstrel_sta_priv = (struct ssv_minstrel_sta_priv *)priv_sta;
+    if ((!minstrel_sta_priv->is_ht) ||
+        (info->flags & IEEE80211_TX_CTL_AMPDU) ||
+        (!minstrel_sta_priv->update_aggr_check))
+        return;
+    sc = (struct ssv_softc *)priv;
+    if ( conf_is_ht(&sc->hw->conf)
+         && (!(skb->protocol == cpu_to_be16(ETH_P_PAE)))) {
+        if (skb_get_queue_mapping(skb) != IEEE80211_AC_VO)
+            ssv6200_ampdu_tx_update_state(priv, sta, skb);
+    }
+    minstrel_sta_priv->update_aggr_check = false;
+    return;
+}
+void ssv_minstrel_set_fix_data_rate(struct ssv_softc *sc,
+                                    struct ssv_minstrel_sta_priv *minstrel_sta_priv, struct ieee80211_tx_rate *ar)
+{
+    int i = 0;
+    struct ssv_hw *sh = sc->sh;
+    struct ieee80211_channel *curchan;
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0)
+    curchan = sc->hw->conf.channel;
+#else
+    curchan = sc->hw->conf.chandef.chan;
+#endif
+    for (i = 0; i < sc->hw->max_rates; i++) {
+        ar[i].count = (sh->cfg.rc_retry_set >> i*4) & 0xF;
+        switch (sh->cfg.rc_phy_mode) {
+        case 3:
+            minstrel_sta_priv->update_aggr_check = true;
+            ar[i].idx = (sh->cfg.rc_rate_idx_set >> i* 4) & 0x7;
+            ar[i].flags = IEEE80211_TX_RC_MCS;
+            if (sh->cfg.rc_long_short)
+                ar[i].flags |= IEEE80211_TX_RC_SHORT_GI;
+            if (sh->cfg.rc_ht40)
+                ar[i].flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
+            if (sh->cfg.rc_mf)
+                ar[i].flags |= IEEE80211_TX_RC_GREEN_FIELD;
+            break;
+        case 2:
+            if (curchan->band == INDEX_80211_BAND_2GHZ)
+                ar[i].idx = 4 + ((sh->cfg.rc_rate_idx_set >> i* 4) & 0x7);
+            else
+                ar[i].idx = ((sh->cfg.rc_rate_idx_set >> i* 4) & 0x7);
+            break;
+        case 0:
+            ar[i].idx = ((sh->cfg.rc_rate_idx_set >> i* 4) & 0x3);
+            break;
+        default:
+            ar[i].idx = 0;
+            break;
+        }
+    }
+}
+static void ssv_minstrel_get_rate(void *priv, struct ieee80211_sta *sta,
+                                  void *priv_sta, struct ieee80211_tx_rate_control *txrc)
+{
+    struct sk_buff *skb = txrc->skb;
+    struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
+    struct ssv_minstrel_sta_priv *minstrel_sta_priv = priv_sta;
+    struct ssv_minstrel_sta_info *smi;
+    struct ssv_softc *sc = priv;
+    struct ssv_minstrel_priv *smp = (struct ssv_minstrel_priv *)sc->rc;
+    struct ieee80211_tx_rate *ar = info->control.rates;
+    unsigned int ndx, sample_ndx = 0;
+    struct ssv_minstrel_rate *msr;
+    bool mrr;
+    bool sample_slower = false;
+    bool sample = false;
+    int i;
+    int mrr_ndx[3];
+    int sample_rate;
+    u64 delta;
+    struct rc_setting *rc_setting = &sc->sh->cfg.rc_setting;
+    int force_sample_pr;
+    if (rate_control_send_low(sta, priv_sta, txrc))
+        return;
+    if (sc->sh->cfg.auto_rate_enable == false) {
+        ssv_minstrel_set_fix_data_rate(sc, minstrel_sta_priv, ar);
+        return;
+    }
+    if (minstrel_sta_priv && minstrel_sta_priv->is_ht) {
+        ssv_minstrel_ht_get_rate(priv, sta, priv_sta, txrc);
+        return;
+    }
+    smi = (struct ssv_minstrel_sta_info *)&minstrel_sta_priv->legacy;
+    mrr = smp->has_mrr;
+    if (time_after(jiffies, smi->stats_update + (smp->update_interval * HZ) / 1000))
+        ssv_minstrel_update_stats(sc, smp, minstrel_sta_priv);
+    ndx = smi->max_tp_rate;
+    if (mrr)
+        sample_rate = smp->lookaround_rate_mrr;
+    else
+        sample_rate = smp->lookaround_rate;
+    smi->packet_count++;
+    delta = div_u64(smi->packet_count * sample_rate, 100) -
+            div_u64(smi->sample_count + smi->sample_deferred, 2);
+    if ((delta > 0) && (mrr || !smi->prev_sample)) {
+        if (smi->packet_count >= 10000) {
+            smi->sample_deferred = 0;
+            smi->sample_count = 0;
+            smi->packet_count = 0;
+        } else if (delta > smi->n_rates * 2) {
+            smi->sample_count += (delta - smi->n_rates * 2);
+        }
+        sample_ndx = minstrel_get_next_sample(minstrel_sta_priv);
+        msr = &minstrel_sta_priv->ratelist[sample_ndx];
+        sample = true;
+        sample_slower = mrr && (msr->perfect_tx_time > minstrel_sta_priv->ratelist[ndx].perfect_tx_time);
+        if (!sample_slower) {
+            if (msr->sample_limit != 0) {
+                ndx = sample_ndx;
+                smi->sample_count++;
+                if (msr->sample_limit > 0)
+                    msr->sample_limit--;
+            } else
+                sample = false;
+        } else {
+            info->flags |= IEEE80211_TX_CTL_RATE_CTRL_PROBE;
+            smi->sample_deferred++;
+        }
+    }
+    smi->prev_sample = sample;
+    if (sc->primary_edca_mib > 10)
+        force_sample_pr = rc_setting->force_sample_pr;
+    else
+        force_sample_pr = 10;
+    if ((sample) && ((sample_slower) ||
+                     ((minstrel_sta_priv->ratelist[sample_ndx].probability > MINSTREL_FRAC(force_sample_pr, 100)) &&
+                      (minstrel_sta_priv->ratelist[sample_ndx].probability < MINSTREL_FRAC(rc_setting->up_pr, 100)))) )
+        ndx = smi->max_tp_rate;
+    if ((sample)&&
+        ((time_before(jiffies,
+                      minstrel_sta_priv->ratelist[sample_ndx].last_jiffies + msecs_to_jiffies(500)) &&
+          minstrel_sta_priv->ratelist[sample_ndx].probability < MINSTREL_FRAC(force_sample_pr, 100))))
+        ndx = smi->max_tp_rate;
+    ar[0].idx = minstrel_sta_priv->ratelist[ndx].rix;
+    ar[0].count = minstrel_get_retry_count(&minstrel_sta_priv->ratelist[ndx], info);
+#if 0
+    if (sample) {
+        if (sample_slower)
+            mrr_ndx[0] = sample_ndx;
+        else
+            mrr_ndx[0] = smi->max_tp_rate;
+    } else {
+        mrr_ndx[0] = smi->max_tp_rate2;
+    }
+#endif
+    mrr_ndx[0] = smi->max_tp_rate2;
+    mrr_ndx[1] = smi->max_prob_rate;
+    mrr_ndx[2] = 0;
+    for (i = 1; i < 4; i++) {
+        ar[i].idx = minstrel_sta_priv->ratelist[mrr_ndx[i - 1]].rix;
+        ar[i].count = minstrel_sta_priv->ratelist[mrr_ndx[i - 1]].adjusted_retry_count;
+    }
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_RATE_CONTROL,
+             "%s():\nar[0].idx=%02x, ar[0].flags=%02x, ar[0].count=%d\n"
+             "ar[1].idx=%02x, ar[1].flags=%02x, ar[1].count=%d\n"
+             "ar[2].idx=%02x, ar[2].flags=%02x, ar[2].count=%d\n"
+             "ar[3].idx=%02x, ar[3].flags=%02x, ar[3].count=%d\n",
+             __FUNCTION__, ar[0].idx, ar[0].flags, ar[0].count, ar[1].idx, ar[1].flags, ar[1].count,
+             ar[2].idx, ar[2].flags, ar[2].count, ar[3].idx, ar[3].flags, ar[3].count);
+}
+static void ssv6xxx_rate_update_minstrel_type(void *priv, struct ieee80211_supported_band *sband,
+        struct ieee80211_sta *sta, void *priv_sta, enum nl80211_channel_type oper_chan_type)
+{
+    struct ssv_minstrel_sta_priv *minstrel_sta_priv = priv_sta;
+    struct ssv_minstrel_sta_info *smi;
+    struct ssv_softc *sc = priv;
+    struct ssv_minstrel_priv *smp = (struct ssv_minstrel_priv *)sc->rc;
+    struct ieee80211_rate *ctl_rate;
+    unsigned int i, t_slot, n = 0;
+    int use_short_preamble = 0;
+    u8 drate_desc = 0;
+    bool supportted_11m = false;
+    minstrel_sta_priv->sta = sta;
+    minstrel_sta_priv->is_ht = sta->ht_cap.ht_supported;
+    if (minstrel_sta_priv->is_ht) {
+        ssv_minstrel_ht_update_caps(priv, sband, sta, priv_sta, oper_chan_type);
+        return;
+    }
+    smi = (struct ssv_minstrel_sta_info *)&minstrel_sta_priv->legacy;
+    if (sc->sc_flags & SC_OP_SHORT_PREAMBLE)
+        use_short_preamble = 1;
+    smi->lowest_rix = rate_lowest_index(sband, sta);
+    ctl_rate = &sband->bitrates[smi->lowest_rix];
+    smi->sp_ack_dur = ieee80211_frame_duration(sband->band, SSV_MINSTREL_ACK_LEN, ctl_rate->bitrate,
+                      !!(ctl_rate->flags & IEEE80211_RATE_ERP_G),
+                      (use_short_preamble && (ctl_rate->flags & IEEE80211_RATE_SHORT_PREAMBLE)));
+    smi->g_rates_offset = 0;
+    for (i = 0; i < sband->n_bitrates; i++) {
+        struct ssv_minstrel_rate *mr = &minstrel_sta_priv->ratelist[n];
+        unsigned int tx_time = 0, tx_time_cts = 0, tx_time_rtscts = 0;
+        unsigned int tx_time_single;
+        unsigned int cw = smp->cw_min;
+        if (!rate_supported(sta, sband->band, i))
+            continue;
+        if (supportted_11m) {
+            if ((sband->bitrates[i].bitrate == 60) || (sband->bitrates[i].bitrate == 90))
+                continue;
+        }
+        n++;
+        memset(mr, 0, sizeof(*mr));
+        mr->rix = i;
+        mr->bitrate = sband->bitrates[i].bitrate;
+        mr->flags = sband->bitrates[i].flags;
+        SSV_RC_LEGACY_BITRATE_TO_RATE_DESC(sc, mr->bitrate, &drate_desc);
+        mr->hw_rate_desc = drate_desc;
+        if ((mr->bitrate == 10) || (mr->bitrate == 20) || (mr->bitrate == 55) || (mr->bitrate == 110))
+            smi->g_rates_offset++;
+        if (mr->bitrate == 110)
+            supportted_11m = true;
+        ssv_calc_rate_durations(sband->band, mr, &sband->bitrates[i], use_short_preamble);
+        if (use_short_preamble && (mr->flags & IEEE80211_RATE_SHORT_PREAMBLE))
+            t_slot = 9;
+        else
+            t_slot = 20;
+        mr->sample_limit = -1;
+        mr->retry_count = 1;
+        mr->retry_count_cts = 1;
+        mr->retry_count_rtscts = 1;
+        tx_time = mr->perfect_tx_time + smi->sp_ack_dur;
+        do {
+            tx_time_single = mr->ack_time + mr->perfect_tx_time;
+            tx_time_single += (t_slot * cw) >> 1;
+            cw = min((cw << 1) | 1, smp->cw_max);
+            tx_time += tx_time_single;
+            tx_time_cts += tx_time_single + smi->sp_ack_dur;
+            tx_time_rtscts += tx_time_single + 2 * smi->sp_ack_dur;
+            if ((tx_time_cts < smp->segment_size) && (mr->retry_count_cts < smp->max_retry))
+                mr->retry_count_cts++;
+            if ((tx_time_rtscts < smp->segment_size) && (mr->retry_count_rtscts < smp->max_retry))
+                mr->retry_count_rtscts++;
+        } while ((tx_time < smp->segment_size) && (++mr->retry_count < smp->max_retry));
+        mr->adjusted_retry_count = mr->retry_count;
+    }
+    for (i = n; i < sband->n_bitrates; i++) {
+        struct ssv_minstrel_rate *mr = &minstrel_sta_priv->ratelist[i];
+        mr->rix = -1;
+    }
+    smi->n_rates = n;
+    smi->stats_update = jiffies;
+    ssv_init_sample_table(minstrel_sta_priv);
+}
+#if LINUX_VERSION_CODE > 0x030500
+static void ssv_minstrel_rate_update(void *priv, struct ieee80211_supported_band *sband,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,13,0)
+                                     struct cfg80211_chan_def *chandef,
+#endif
+                                     struct ieee80211_sta *sta, void *priv_sta,
+                                     u32 changed)
+#else
+static void ssv_minstrel_rate_update(void *priv, struct ieee80211_supported_band *sband,
+                                     struct ieee80211_sta *sta, void *priv_sta,
+                                     u32 changed, enum nl80211_channel_type oper_chan_type)
+#endif
+{
+#if LINUX_VERSION_CODE > 0x030500
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,13,0)
+    ssv6xxx_rate_update_minstrel_type(priv, sband, sta, priv_sta, cfg80211_get_chandef_type(chandef));
+#else
+    struct ssv_softc *sc = priv;
+    struct ieee80211_hw *hw = sc->hw;
+    ssv6xxx_rate_update_minstrel_type(priv, sband, sta, priv_sta, cfg80211_get_chandef_type(&(hw->conf.chandef)));
+#endif
+#else
+    ssv6xxx_rate_update_minstrel_type(priv, sband, sta, priv_sta, oper_chan_type);
+#endif
+}
+static void ssv_minstrel_rate_init(void *priv, struct ieee80211_supported_band *sband,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,13,0)
+                                   struct cfg80211_chan_def *chandef,
+#endif
+                                   struct ieee80211_sta *sta, void *priv_sta)
+{
+#if LINUX_VERSION_CODE > 0x030500
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,13,0)
+    ssv6xxx_rate_update_minstrel_type(priv, sband, sta, priv_sta, cfg80211_get_chandef_type(chandef));
+#else
+    struct ssv_softc *sc = priv;
+    struct ieee80211_hw *hw = sc->hw;
+    ssv6xxx_rate_update_minstrel_type(priv, sband, sta, priv_sta, cfg80211_get_chandef_type(&(hw->conf.chandef)));
+#endif
+#else
+    struct ssv_softc *sc = priv;
+    struct ieee80211_hw *hw = sc->hw;
+    ssv6xxx_rate_update_minstrel_type(priv, sband, sta, priv_sta, hw->conf.channel_type);
+#endif
+}
+static void *ssv_minstrel_alloc_sta(void *priv, struct ieee80211_sta *sta, gfp_t gfp)
+{
+    struct ieee80211_supported_band *sband;
+    struct ssv_minstrel_sta_priv *minstrel_sta_priv;
+    struct ssv_sta_priv_data *sta_priv;
+    struct ssv_softc *sc = priv;
+    struct ieee80211_hw *hw = sc->hw;
+    int max_rates = 0;
+    int i;
+    minstrel_sta_priv = kzalloc(sizeof(struct ssv_minstrel_sta_priv), gfp);
+    if (!minstrel_sta_priv)
+        return NULL;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,7,0)
+    for (i = 0; i < NUM_NL80211_BANDS; i++) {
+#else
+    for (i = 0; i < IEEE80211_NUM_BANDS; i++) {
+#endif
+        sband = hw->wiphy->bands[i];
+        if (sband && sband->n_bitrates > max_rates)
+            max_rates = sband->n_bitrates;
+    }
+    minstrel_sta_priv->ratelist = kzalloc(sizeof(struct ssv_minstrel_rate) * max_rates, gfp);
+    if (!minstrel_sta_priv->ratelist)
+        goto error;
+    minstrel_sta_priv->sample_table = kmalloc(SAMPLE_COLUMNS * max_rates, gfp);
+    if (!minstrel_sta_priv->sample_table)
+        goto error1;
+    sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+    sta_priv->rc_info = minstrel_sta_priv;
+    return minstrel_sta_priv;
+error1:
+    kfree(minstrel_sta_priv);
+error:
+    return NULL;
+}
+static void ssv_minstrel_free_sta(void *priv, struct ieee80211_sta *sta, void *priv_sta)
+{
+    struct ssv_minstrel_sta_priv *minstrel_sta_priv = priv_sta;
+    kfree(minstrel_sta_priv->sample_table);
+    kfree(minstrel_sta_priv->ratelist);
+    kfree(minstrel_sta_priv);
+}
+static void *ssv_minstrel_alloc(struct ieee80211_hw *hw, struct dentry *debugfsdir)
+{
+    struct ssv_softc *sc = hw->priv;
+    struct ssv_minstrel_priv *smp;
+    sc->rc = kzalloc(sizeof(struct ssv_minstrel_priv), GFP_ATOMIC);
+    if (!sc->rc)
+        return NULL;
+    memset(sc->rc, 0, sizeof(struct ssv_minstrel_priv));
+    smp = (struct ssv_minstrel_priv *)sc->rc;
+    smp->cw_min = 15;
+    smp->cw_max = 1023;
+    smp->lookaround_rate = 5;
+    smp->lookaround_rate_mrr = 10;
+    smp->segment_size = 6000;
+    smp->max_retry = hw->max_rate_tries;
+    smp->max_rates = hw->max_rates;
+    smp->has_mrr = true;
+    smp->update_interval = 100;
+    return hw->priv;
+}
+static void ssv_minstrel_free(void *priv)
+{
+    struct ssv_softc *sc = priv;
+    if (sc->rc) {
+        kfree(sc->rc);
+        sc->rc = NULL;
+    }
+}
+#ifdef CONFIG_MAC80211_DEBUGFS
+static int ssv_minstrel_stats_open(struct inode *inode, struct file *file)
+{
+    struct ssv_minstrel_sta_priv *minstrel_sta_priv = inode->i_private;
+    struct ssv_minstrel_sta_info *legacy;
+    struct ssv_minstrel_ht_sta *ht;
+    struct ssv_minstrel_ht_mcs_group_data *mg;
+    struct ssv_minstrel_debugfs_info *ms;
+    unsigned int i, j, tp, prob, eprob;
+    char *p;
+    unsigned int max_mcs = MINSTREL_MAX_STREAMS * MINSTREL_STREAM_GROUPS;
+    int bitrates[4] = { 10, 20, 55, 110 };
+    int max_ht_groups = 0;
+    ms = kmalloc(sizeof(*ms) + 4096, GFP_KERNEL);
+    if (!ms)
+        return -ENOMEM;
+    file->private_data = ms;
+    p = ms->buf;
+    if (!minstrel_sta_priv->is_ht) {
+        legacy = (struct ssv_minstrel_sta_info *)&minstrel_sta_priv->legacy;
+        p += sprintf(p, "rate     throughput  ewma prob   this prob  "
+                     "this succ/attempt   success    attempts\n");
+        for (i = 0; i < legacy->n_rates; i++) {
+            struct ssv_minstrel_rate *mr = &minstrel_sta_priv->ratelist[i];
+            *(p++) = (i == legacy->max_tp_rate) ? 'T' : ' ';
+            *(p++) = (i == legacy->max_tp_rate2) ? 't' : ' ';
+            *(p++) = (i == legacy->max_prob_rate) ? 'P' : ' ';
+            p += sprintf(p, "%3u%s", mr->bitrate / 10, (mr->bitrate & 1 ? ".5" : "  "));
+            tp = mr->cur_tp/(1024*1024);
+            prob = MINSTREL_TRUNC(mr->cur_prob * 1000);
+            eprob = MINSTREL_TRUNC(mr->probability * 1000);
+            p += sprintf(p, "  %6u.%1u   %6u.%1u   %6u.%1u        "
+                         "%3u(%3u)   %8llu    %8llu\n",
+                         tp / 10, tp % 10,
+                         eprob / 10, eprob % 10,
+                         prob / 10, prob % 10,
+                         mr->last_success,
+                         mr->last_attempts,
+                         (unsigned long long)mr->succ_hist,
+                         (unsigned long long)mr->att_hist);
+        }
+        p += sprintf(p, "\nTotal packet count::    total %llu      lookaround %llu\n\n",
+                     legacy->packet_count, legacy->sample_count);
+    } else {
+        ht = (struct ssv_minstrel_ht_sta *)&minstrel_sta_priv->ht;
+        p += sprintf(p, "%4s %8s %12s %12s %12s %20s %10s %10s\n",
+                     "type", "rate", "throughput", "ewma prob", "this prob", "this succ/attempt", "success", "attempts");
+        max_ht_groups = MINSTREL_MAX_STREAMS * MINSTREL_STREAM_GROUPS + 1;
+        for (i = 0; i < max_ht_groups; i++) {
+            mg = &ht->groups[i];
+            if (!mg->supported)
+                continue;
+            for (j = 0; j < MCS_GROUP_RATES; j++) {
+                struct ssv_minstrel_ht_rate_stats *mhr = &ht->groups[i].rates[j];
+                int idx = i * MCS_GROUP_RATES + j;
+                if (!(ht->groups[i].supported & BIT(j)))
+                    continue;
+                *(p++) = ' ';
+                *(p++) = (idx == ht->max_tp_rate) ? 'T' : ' ';
+                *(p++) = (idx == ht->max_tp_rate2) ? 't' : ' ';
+                *(p++) = (idx == ht->max_prob_rate) ? 'P' : ' ';
+                if (i == max_mcs) {
+                    int r = bitrates[j % 4];
+                    p += sprintf(p, "  %2u.%1uM/%c", r / 10, r % 10, (ht->cck_supported_short ? 'S' : 'L'));
+                } else
+                    p += sprintf(p, "    MCS%-2u", j);
+                tp = mhr->cur_tp / 10;
+                prob = MINSTREL_TRUNC(mhr->cur_prob * 1000);
+                eprob = MINSTREL_TRUNC(mhr->probability * 1000);
+                p += sprintf(p, "     %6u.%1u     %6u.%1u     %6u.%1u            %3u(%3u)    %8llu   %8llu\n",
+                             tp / 10, tp % 10,
+                             eprob / 10, eprob % 10,
+                             prob / 10, prob % 10,
+                             mhr->last_success,
+                             mhr->last_attempts,
+                             (unsigned long long)mhr->succ_hist,
+                             (unsigned long long)mhr->att_hist);
+            }
+        }
+        p += sprintf(p, "\nTotal packet count::    total %llu      lookaround %llu, short GI state = %d\n",
+                     ht->total_packets, ht->sample_packets, ht->sgi_state);
+    }
+    ms->len = p - ms->buf;
+    return 0;
+}
+static ssize_t ssv_minstrel_stats_read(struct file *file, char __user *buf, size_t len, loff_t *ppos)
+{
+    struct ssv_minstrel_debugfs_info *ms;
+    ms = file->private_data;
+    return simple_read_from_buffer(buf, len, ppos, ms->buf, ms->len);
+}
+static int ssv_minstrel_stats_release(struct inode *inode, struct file *file)
+{
+    kfree(file->private_data);
+    return 0;
+}
+static const struct file_operations ssv_minstrel_stat_fops = {
+    .open = ssv_minstrel_stats_open,
+    .read = ssv_minstrel_stats_read,
+    .release = ssv_minstrel_stats_release,
+    .llseek = no_llseek,
+};
+static void ssv_minstrel_add_sta_debugfs(void *priv, void *priv_sta, struct dentry *dir)
+{
+    struct ssv_minstrel_sta_priv *minstrel_sta_priv = priv_sta;
+    minstrel_sta_priv->dbg_stats = debugfs_create_file("rc_stats", S_IRUGO, dir,
+                                   minstrel_sta_priv, &ssv_minstrel_stat_fops);
+}
+static void ssv_minstrel_remove_sta_debugfs(void *priv, void *priv_sta)
+{
+    struct ssv_minstrel_sta_priv *minstrel_sta_priv = priv_sta;
+    debugfs_remove(minstrel_sta_priv->dbg_stats);
+}
+#endif
+struct rate_control_ops ssv_minstrel = {
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,15,0)
+    .module = NULL,
+#endif
+    .name = "ssv_minstrel",
+    .tx_status = ssv_minstrel_tx_status,
+    .get_rate = ssv_minstrel_get_rate,
+    .rate_update = ssv_minstrel_rate_update,
+    .rate_init = ssv_minstrel_rate_init,
+    .alloc = ssv_minstrel_alloc,
+    .free = ssv_minstrel_free,
+    .alloc_sta = ssv_minstrel_alloc_sta,
+    .free_sta = ssv_minstrel_free_sta,
+#ifdef CONFIG_MAC80211_DEBUGFS
+    .add_sta_debugfs = ssv_minstrel_add_sta_debugfs,
+    .remove_sta_debugfs = ssv_minstrel_remove_sta_debugfs,
+#endif
+};
+int ssv6xxx_minstrel_rate_control_register(void)
+{
+    ssv_minstrel_ht_init_sample_table();
+    return ieee80211_rate_control_register(&ssv_minstrel);
+}
+void ssv6xxx_minstrel_rate_control_unregister(void)
+{
+    ieee80211_rate_control_unregister(&ssv_minstrel);
+}
diff --git a/drivers/net/wireless/ssv6x5x/smac/ssv_rc_minstrel.h b/drivers/net/wireless/ssv6x5x/smac/ssv_rc_minstrel.h
new file mode 100644
index 000000000..f54645062
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/ssv_rc_minstrel.h
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV_RC_MINSTREL_H_
+#define _SSV_RC_MINSTREL_H_
+#include "ssv_rc_minstrel_ht.h"
+struct ssv_minstrel_rate {
+    int bitrate;
+    int rix;
+    u32 flags;
+    u8 hw_rate_desc;
+    unsigned int perfect_tx_time;
+    unsigned int ack_time;
+    int sample_limit;
+    unsigned int retry_count;
+    unsigned int retry_count_cts;
+    unsigned int retry_count_rtscts;
+    unsigned int adjusted_retry_count;
+    u32 success;
+    u32 attempts;
+    u32 last_attempts;
+    u32 last_success;
+    u32 cur_prob;
+    u32 probability;
+    u32 cur_tp;
+    u64 succ_hist;
+    u64 att_hist;
+    unsigned long last_jiffies;
+};
+struct ssv_minstrel_sta_info {
+    unsigned long stats_update;
+    unsigned int sp_ack_dur;
+    unsigned int rate_avg;
+    unsigned int lowest_rix;
+    unsigned int max_tp_rate;
+    unsigned int max_tp_rate2;
+    unsigned int max_prob_rate;
+    u64 packet_count;
+    u64 sample_count;
+    int sample_deferred;
+    unsigned int sample_idx;
+    unsigned int sample_column;
+    int n_rates;
+    int g_rates_offset;
+    bool prev_sample;
+};
+struct ssv_minstrel_debugfs_info {
+    size_t len;
+    char buf[];
+};
+struct ssv_minstrel_sta_priv {
+    union {
+        struct ssv_minstrel_sta_info legacy;
+        struct ssv_minstrel_ht_sta ht;
+    };
+    struct ieee80211_sta *sta;
+    bool is_ht;
+    bool update_aggr_check;
+    struct ssv_minstrel_rate *ratelist;
+    u8 *sample_table;
+#ifdef CONFIG_MAC80211_DEBUGFS
+    struct dentry *dbg_stats;
+#endif
+};
+struct ssv_minstrel_priv {
+    bool has_mrr;
+    unsigned int cw_min;
+    unsigned int cw_max;
+    unsigned int max_rates;
+    unsigned int max_retry;
+    unsigned int segment_size;
+    unsigned int update_interval;
+    unsigned int lookaround_rate;
+    unsigned int lookaround_rate_mrr;
+    u8 cck_rates[4];
+};
+int minstrel_ewma(int old, int new, int weight);
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,7,0)
+int ieee80211_frame_duration(enum nl80211_band band, size_t len,
+                             int rate, int erp, int short_preamble);
+#else
+int ieee80211_frame_duration(enum ieee80211_band band, size_t len,
+                             int rate, int erp, int short_preamble);
+#endif
+void ssv_minstrel_set_fix_data_rate(struct ssv_softc *sc,
+                                    struct ssv_minstrel_sta_priv *minstrel_sta_priv, struct ieee80211_tx_rate *ar);
+int ssv6xxx_minstrel_rate_control_register(void);
+void ssv6xxx_minstrel_rate_control_unregister(void);
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smac/ssv_rc_minstrel_ht.c b/drivers/net/wireless/ssv6x5x/smac/ssv_rc_minstrel_ht.c
new file mode 100644
index 000000000..c44cc7889
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/ssv_rc_minstrel_ht.c
@@ -0,0 +1,940 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/random.h>
+#include <linux/math64.h>
+#include <ssv6200.h>
+#include "ssv_skb.h"
+#include "dev.h"
+#include <hal.h>
+#include "ssv_rc_minstrel.h"
+#include "ssv_rc_minstrel_ht.h"
+#include <linux_80211.h>
+#include "ampdu.h"
+#define AVG_PKT_SIZE 1200
+#define SAMPLE_COLUMNS 10
+#define MCS_NBITS (AVG_PKT_SIZE << 3)
+#define MCS_NSYMS(bps) ((MCS_NBITS + (bps) - 1) / (bps))
+#define MCS_SYMBOL_TIME(sgi,syms) \
+ (sgi ? \
+   ((syms) * 18000 + 4000) / 5 : \
+   ((syms) * 1000) << 2 \
+ )
+#define MCS_DURATION(streams,sgi,bps) MCS_SYMBOL_TIME(sgi, MCS_NSYMS((streams) * (bps)))
+#define GROUP_IDX(_streams,_sgi,_ht40) \
+ MINSTREL_MAX_STREAMS * 2 * _ht40 + \
+ MINSTREL_MAX_STREAMS * _sgi + \
+ _streams - 1
+#define MCS_GROUP(_streams,_sgi,_ht40) \
+ [GROUP_IDX(_streams, _sgi, _ht40)] = { \
+  .streams = _streams, \
+  .flags = \
+   (_sgi ? IEEE80211_TX_RC_SHORT_GI : 0) | \
+   (_ht40 ? IEEE80211_TX_RC_40_MHZ_WIDTH : 0), \
+  .duration = { \
+   MCS_DURATION(_streams, _sgi, _ht40 ? 54 : 26), \
+   MCS_DURATION(_streams, _sgi, _ht40 ? 108 : 52), \
+   MCS_DURATION(_streams, _sgi, _ht40 ? 162 : 78), \
+   MCS_DURATION(_streams, _sgi, _ht40 ? 216 : 104), \
+   MCS_DURATION(_streams, _sgi, _ht40 ? 324 : 156), \
+   MCS_DURATION(_streams, _sgi, _ht40 ? 432 : 208), \
+   MCS_DURATION(_streams, _sgi, _ht40 ? 486 : 234), \
+   MCS_DURATION(_streams, _sgi, _ht40 ? 540 : 260) \
+  } \
+    }
+#define CCK_DURATION(_bitrate,_short,_len) \
+    (1000 * (10 + \
+     (_short ? 72 + 24 : 144 + 48 ) + \
+     (8 * (_len + 4) * 10) / (_bitrate)))
+#define CCK_ACK_DURATION(_bitrate,_short) \
+    (CCK_DURATION((_bitrate > 10 ? 20 : 10), false, 60) + \
+     CCK_DURATION(_bitrate, _short, AVG_PKT_SIZE))
+#define CCK_DURATION_LIST(_short) \
+    CCK_ACK_DURATION(10, _short), \
+    CCK_ACK_DURATION(20, _short), \
+    CCK_ACK_DURATION(55, _short), \
+    CCK_ACK_DURATION(110, _short)
+#define CCK_GROUP \
+    [MINSTREL_MAX_STREAMS * MINSTREL_STREAM_GROUPS] = { \
+        .streams = 0, \
+        .duration = { \
+            CCK_DURATION_LIST(false), \
+            CCK_DURATION_LIST(true) \
+  } \
+    }
+const struct ssv_mcs_ht_group ssv_minstrel_mcs_groups[] = {
+    MCS_GROUP(1, 0, 0),
+    MCS_GROUP(1, 1, 0),
+    MCS_GROUP(1, 0, 1),
+    MCS_GROUP(1, 1, 1),
+    CCK_GROUP
+};
+#define SSV_MINSTREL_CCK_GROUP (ARRAY_SIZE(ssv_minstrel_mcs_groups) - 1)
+#define SSV_MINSTREL_STA_GROUP(_idx) (_idx/MCS_GROUP_RATES)
+static u8 ssv_minstrel_ht_sample_table[SAMPLE_COLUMNS][MCS_GROUP_RATES];
+static inline struct ssv_minstrel_ht_rate_stats *
+ssv_minstrel_ht_get_ratestats(struct ssv_minstrel_ht_sta *mhs, int index)
+{
+    return &mhs->groups[index / MCS_GROUP_RATES].rates[index % MCS_GROUP_RATES];
+}
+void ssv_minstrel_ht_init_sample_table(void)
+{
+    int col, i, new_idx;
+    u8 rnd[MCS_GROUP_RATES];
+    memset(ssv_minstrel_ht_sample_table, 0xff, sizeof(ssv_minstrel_ht_sample_table));
+    for (col = 0; col < SAMPLE_COLUMNS; col++) {
+        for (i = 0; i < MCS_GROUP_RATES; i++) {
+            get_random_bytes(rnd, sizeof(rnd));
+            new_idx = (i + rnd[i]) % MCS_GROUP_RATES;
+            while (ssv_minstrel_ht_sample_table[col][new_idx] != 0xff)
+                new_idx = (new_idx + 1) % MCS_GROUP_RATES;
+            ssv_minstrel_ht_sample_table[col][new_idx] = i;
+        }
+    }
+}
+static void ssv_minstrel_ht_calc_rate_ewma(struct ssv_softc *sc, struct ssv_minstrel_ht_rate_stats *mr)
+{
+    struct rc_setting *rc_setting = &sc->sh->cfg.rc_setting;
+    if (unlikely(mr->attempts > 0)) {
+        mr->sample_skipped = 0;
+        mr->cur_prob = MINSTREL_FRAC(mr->success, mr->attempts);
+        if ((!mr->att_hist) || (mr->probability < MINSTREL_FRAC(10, 100)))
+            mr->probability = mr->cur_prob;
+        else
+            mr->probability = minstrel_ewma(mr->probability, mr->cur_prob, EWMA_LEVEL);
+        mr->att_hist += mr->attempts;
+        mr->succ_hist += mr->success;
+        mr->last_jiffies = jiffies;
+    } else {
+        mr->sample_skipped++;
+        if (time_after(jiffies, mr->last_jiffies + msecs_to_jiffies(rc_setting->aging_period))) {
+            mr->probability = minstrel_ewma(mr->probability, 0, EWMA_LEVEL);
+            mr->last_jiffies = jiffies;
+        }
+    }
+    mr->last_success = mr->success;
+    mr->last_attempts = mr->attempts;
+    mr->success = 0;
+    mr->attempts = 0;
+}
+static void ssv_minstrel_ht_calc_tp(struct ssv_minstrel_ht_sta *mhs, int group, int rate)
+{
+    struct ssv_minstrel_ht_rate_stats *mr;
+    unsigned int nsecs = 0;
+    u64 s = 1000000;
+    mr = &mhs->groups[group].rates[rate];
+    if (mr->probability < MINSTREL_FRAC(1, 10)) {
+        mr->cur_tp = 0;
+        return;
+    }
+    if (group != SSV_MINSTREL_CCK_GROUP)
+        nsecs = (MINSTREL_TRUNC(mhs->avg_ampdu_len)!= 0) ? (1000 * mhs->overhead / MINSTREL_TRUNC(mhs->avg_ampdu_len)) : 0 ;
+    nsecs += ssv_minstrel_mcs_groups[group].duration[rate];
+    mr->cur_tp = (nsecs != 0 ) ? (u32)(MINSTREL_TRUNC(div_u64((s * mr->probability * 1000), nsecs))) : 0;
+}
+static void ssv_minstrel_ht_calc_retransmit(struct ssv_minstrel_priv *smp,
+        struct ssv_minstrel_ht_sta *mhs, int index)
+{
+    struct ssv_minstrel_ht_rate_stats *mr;
+    const struct ssv_mcs_ht_group *group;
+    unsigned int tx_time, tx_time_rtscts, tx_time_data;
+    unsigned int cw = smp->cw_min;
+    unsigned int ctime = 0;
+    unsigned int t_slot = 9;
+    unsigned int ampdu_len = MINSTREL_TRUNC(mhs->avg_ampdu_len);
+    mr = ssv_minstrel_ht_get_ratestats(mhs, index);
+    if (mr->probability < MINSTREL_FRAC(1, 10)) {
+        mr->retry_count = 1;
+        mr->retry_count_rtscts = 1;
+        return;
+    }
+    mr->retry_count = 2;
+    mr->retry_count_rtscts = 2;
+    mr->retry_updated = true;
+    group = &ssv_minstrel_mcs_groups[index / MCS_GROUP_RATES];
+    tx_time_data = group->duration[index % MCS_GROUP_RATES] * ampdu_len;
+    ctime = (t_slot * cw) >> 1;
+    cw = min((cw << 1) | 1, smp->cw_max);
+    ctime += (t_slot * cw) >> 1;
+    cw = min((cw << 1) | 1, smp->cw_max);
+    tx_time = ctime + 2 * (mhs->overhead + tx_time_data);
+    tx_time_rtscts = ctime + 2 * (mhs->overhead_rtscts + tx_time_data);
+    do {
+        ctime = (t_slot * cw) >> 1;
+        cw = min((cw << 1) | 1, smp->cw_max);
+        tx_time += ctime + mhs->overhead + tx_time_data;
+        tx_time_rtscts += ctime + mhs->overhead_rtscts + tx_time_data;
+        if (tx_time_rtscts < smp->segment_size)
+            mr->retry_count_rtscts++;
+    } while ((tx_time < smp->segment_size) && (++mr->retry_count < smp->max_retry));
+}
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,7,0)
+static void ssv_minstrel_ht_set_rate(struct ssv_softc *sc, struct ssv_minstrel_priv *smp, struct ssv_minstrel_ht_sta *mhs,
+                                     struct ieee80211_tx_rate *rate, int rate_series, int index, enum nl80211_band band, bool sample, bool rtscts)
+#else
+static void ssv_minstrel_ht_set_rate(struct ssv_softc *sc, struct ssv_minstrel_priv *smp, struct ssv_minstrel_ht_sta *mhs,
+                                     struct ieee80211_tx_rate *rate, int rate_series, int index, enum ieee80211_band band, bool sample, bool rtscts)
+#endif
+{
+    const struct ssv_mcs_ht_group *group = &ssv_minstrel_mcs_groups[index / MCS_GROUP_RATES];
+    struct ssv_minstrel_ht_rate_stats *mr;
+    mr = ssv_minstrel_ht_get_ratestats(mhs, index);
+    if (!mr->retry_updated)
+        ssv_minstrel_ht_calc_retransmit(smp, mhs, index);
+    if (sample)
+        rate->count = 2;
+    else if (mr->probability < MINSTREL_FRAC(20, 100))
+        rate->count = 2;
+    else if (rtscts)
+        rate->count = mr->retry_count_rtscts;
+    else
+        rate->count = 4;
+    rate->flags = 0;
+    if (rtscts)
+        rate->flags |= IEEE80211_TX_RC_USE_RTS_CTS;
+    if (SSV_MINSTREL_STA_GROUP(index) != SSV_MINSTREL_CCK_GROUP) {
+        rate->flags |= IEEE80211_TX_RC_MCS;
+        if (band == INDEX_80211_BAND_2GHZ) {
+            if (group->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) {
+                if (mhs->secondary_channel_clear)
+                    rate->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
+            }
+        } else {
+            if (group->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
+                rate->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
+        }
+        rate->idx = index % MCS_GROUP_RATES;
+        if (rate->idx == 0)
+            rate->flags &= ~IEEE80211_TX_RC_40_MHZ_WIDTH;
+        if (((rate->idx == 7) || (rate->idx == 6)) && (group->flags & IEEE80211_TX_RC_SHORT_GI) &&
+            ((mhs->sgi_state == SGI_ENABLE_SGI) || (mhs->sgi_state == SGI_DETECT_SGI)))
+            rate->flags |= IEEE80211_TX_RC_SHORT_GI;
+    } else {
+        rate->idx = index % ARRAY_SIZE(smp->cck_rates);
+        if (((rate->idx == 3) || (rate->idx == 2)) && mhs->cck_supported_short)
+            rate->flags |= IEEE80211_RATE_SHORT_PREAMBLE;
+    }
+}
+static inline int ssv_minstrel_ht_get_duration(int index)
+{
+    const struct ssv_mcs_ht_group *group = &ssv_minstrel_mcs_groups[index / MCS_GROUP_RATES];
+    return group->duration[index % MCS_GROUP_RATES];
+}
+static void ssv_minstrel_ht_next_sample_idx(struct ssv_minstrel_ht_sta *mhs)
+{
+    struct ssv_minstrel_ht_mcs_group_data *mg;
+    int group = SSV_MINSTREL_STA_GROUP(mhs->max_tp_rate);
+    int i;
+    for (i = 0 ; i < ARRAY_SIZE(ssv_minstrel_mcs_groups) ; ++i) {
+        mhs->sample_group++;
+        mhs->sample_group %= ARRAY_SIZE(ssv_minstrel_mcs_groups);
+        mg = &mhs->groups[mhs->sample_group];
+        if ((group != SSV_MINSTREL_CCK_GROUP) && (mhs->sample_group == SSV_MINSTREL_CCK_GROUP))
+            continue;
+        if (!mg->supported)
+            continue;
+        if (++mg->index >= MCS_GROUP_RATES) {
+            mg->index = 0;
+            if (++mg->column >= ARRAY_SIZE(ssv_minstrel_ht_sample_table))
+                mg->column = 0;
+        }
+        break;
+    }
+}
+static int ssv_minstrel_ht_get_sample_rate(struct ssv_softc *sc,
+        struct ssv_minstrel_priv *smp, struct ssv_minstrel_ht_sta *mhs)
+{
+    struct ssv_minstrel_ht_rate_stats *mr, *max_mr;
+    struct ssv_minstrel_ht_mcs_group_data *mg;
+    int sample_idx = 0, sample_rate_idx, current_rate_idx;
+    int cur_group = SSV_MINSTREL_STA_GROUP(mhs->max_tp_rate);
+    int cur_sample_group = mhs->sample_group;
+    struct rc_setting *rc_setting = &sc->sh->cfg.rc_setting;
+    if (mhs->sample_wait > 0) {
+        mhs->sample_wait--;
+        return -1;
+    }
+    if (!mhs->sample_tries)
+        return -1;
+    mg = &mhs->groups[cur_sample_group];
+    sample_idx = ssv_minstrel_ht_sample_table[mg->column][mg->index];
+    if (cur_group == SSV_MINSTREL_CCK_GROUP) {
+        if (cur_sample_group == SSV_MINSTREL_CCK_GROUP) {
+            sample_idx = sample_idx % ARRAY_SIZE(smp->cck_rates);
+            if ((mhs->cck_supported_short) && (sample_idx > 1))
+                sample_idx += ARRAY_SIZE(smp->cck_rates);
+        } else {
+            sample_idx = 1;
+        }
+    }
+    mr = &mg->rates[sample_idx];
+    ssv_minstrel_ht_next_sample_idx(mhs);
+    if (!(mg->supported & BIT(sample_idx)))
+        return -1;
+    if ((cur_group != SSV_MINSTREL_CCK_GROUP) && (cur_group != cur_sample_group))
+        return -1;
+    max_mr = ssv_minstrel_ht_get_ratestats(mhs, mhs->max_tp_rate);
+    mr = &mg->rates[sample_idx];
+    sample_rate_idx = sample_idx;
+    current_rate_idx = GET_RATE_INDEX(mhs->max_tp_rate);
+    sample_idx += cur_sample_group * MCS_GROUP_RATES;
+    if ((cur_group == SSV_MINSTREL_CCK_GROUP) && (cur_sample_group !=SSV_MINSTREL_CCK_GROUP)) {
+        if (max_mr->probability < MINSTREL_FRAC(80, 100))
+            return -1;
+    }
+    if (cur_group != SSV_MINSTREL_CCK_GROUP) {
+        if ((sample_rate_idx > current_rate_idx)) {
+            int sample_up_pr, forbid_time, force_sample_pr;
+            switch (current_rate_idx) {
+            case 4:
+                sample_up_pr = rc_setting->up_pr4;
+                forbid_time = rc_setting->forbid4;
+                break;
+            case 5:
+                sample_up_pr = rc_setting->up_pr5;;
+                forbid_time = rc_setting->forbid5;
+                break;
+            case 3:
+                sample_up_pr = rc_setting->up_pr3;
+                forbid_time = rc_setting->forbid3;
+            case 6:
+                sample_up_pr = rc_setting->up_pr6;
+                forbid_time = rc_setting->forbid6;
+                break;
+            default:
+                sample_up_pr = rc_setting->up_pr;
+                forbid_time = rc_setting->forbid;
+                break;
+            }
+            if (sc->primary_edca_mib > 10)
+                force_sample_pr = rc_setting->force_sample_pr;
+            else
+                force_sample_pr = 10;
+            if (!(mr->probability < MINSTREL_FRAC(force_sample_pr, 100))) {
+#if 1
+                if ((max_mr->probability < MINSTREL_FRAC(sample_up_pr, 100))
+                    || (!(time_after(jiffies, mr->last_jiffies + msecs_to_jiffies(forbid_time)))))
+                    return -1;
+                if (current_rate_idx == 4)
+                    if (sample_rate_idx == 5 ) {
+                        if (mr->probability < MINSTREL_FRAC(rc_setting->sample_pr_5, 100))
+                            return -1;
+                    }
+                if (current_rate_idx == 3)
+                    if (sample_rate_idx == 4 ) {
+                        if (mr->probability < MINSTREL_FRAC(rc_setting->sample_pr_4, 100))
+                            return -1;
+                    }
+#endif
+            } else {
+                mr->probability = 0;
+            }
+        } else {
+            return -1;
+        }
+    }
+    if (sc->sh->cfg.rc_log) {
+        printk("sample_rate_idx %x, current rate idx %x\n", sample_rate_idx, current_rate_idx);
+    }
+#if 0
+    if ((sample_idx == mhs->max_tp_rate) ||
+        (sample_idx == mhs->max_tp_rate2) ||
+        (sample_idx == mhs->max_prob_rate))
+        return -1;
+    if ((ssv_minstrel_ht_get_duration(sample_idx) > ssv_minstrel_ht_get_duration(mhs->max_tp_rate2)) &&
+        (ssv_minstrel_ht_get_duration(sample_idx) > ssv_minstrel_ht_get_duration(mhs->max_prob_rate))) {
+        if (mr->sample_skipped < 20)
+            return -1;
+        if (mhs->sample_slow++ > 2)
+            return -1;
+    }
+#endif
+    mhs->sample_tries--;
+    return sample_idx;
+}
+static void ssv_minstrel_ht_update_stats(struct ssv_softc *sc, struct ssv_minstrel_priv *smp,
+        struct ssv_minstrel_sta_priv *minstrel_sta_priv, struct ssv_minstrel_ht_sta *mhs)
+{
+    struct ssv_minstrel_ht_mcs_group_data *mg;
+    struct ssv_minstrel_ht_rate_stats *mr;
+    int cur_prob, cur_prob_tp, cur_tp, cur_tp2;
+    int group, i, index, rate_idx;
+    struct rc_setting *rc_setting = &sc->sh->cfg.rc_setting;
+    struct ssv_sta_priv_data *ssv_sta_priv = (struct ssv_sta_priv_data *)minstrel_sta_priv->sta->drv_priv;
+    int signal = -(ssv_sta_priv->beacon_rssi >> RSSI_DECIMAL_POINT_SHIFT);
+    if (mhs->ampdu_packets > 0) {
+        mhs->avg_ampdu_len = minstrel_ewma(mhs->avg_ampdu_len,
+                                           MINSTREL_FRAC(mhs->ampdu_len, mhs->ampdu_packets), EWMA_LEVEL);
+        mhs->ampdu_len = 0;
+        mhs->ampdu_packets = 0;
+    }
+    mhs->sample_slow = 0;
+    mhs->sample_count = 0;
+    mhs->max_tp_rate = mhs->group_idx * MCS_GROUP_RATES;
+    mhs->max_tp_rate2 = 0;
+    mhs->max_prob_rate = 0;
+    for (group = 0; group < ARRAY_SIZE(ssv_minstrel_mcs_groups); group++) {
+        cur_prob = 0;
+        cur_prob_tp = 0;
+        cur_tp = 0;
+        cur_tp2 = 0;
+        mg = &mhs->groups[group];
+        if (!mg->supported)
+            continue;
+        mg->max_tp_rate = 0;
+        mg->max_tp_rate2 = 0;
+        mg->max_prob_rate = 0;
+        mhs->sample_count++;
+        for (i = 0; i < MCS_GROUP_RATES; i++) {
+            if (!(mg->supported & BIT(i)))
+                continue;
+            mr = &mg->rates[i];
+            mr->retry_updated = false;
+            index = MCS_GROUP_RATES * group + i;
+            ssv_minstrel_ht_calc_rate_ewma(sc, mr);
+            ssv_minstrel_ht_calc_tp(mhs, group, i);
+            if (!mr->cur_tp)
+                continue;
+            if (!i && ssv_minstrel_mcs_groups[group].streams == 1)
+                continue;
+            if ((i == 1) && (group == SSV_MINSTREL_CCK_GROUP))
+                continue;
+            if ((mr->cur_tp > cur_prob_tp && mr->probability > MINSTREL_FRAC(3, 4)) || mr->probability > cur_prob) {
+                mg->max_prob_rate = index;
+                cur_prob = mr->probability;
+                cur_prob_tp = mr->cur_tp;
+            }
+            if (mr->cur_tp > cur_tp) {
+                swap(index, mg->max_tp_rate);
+                cur_tp = mr->cur_tp;
+                mr = ssv_minstrel_ht_get_ratestats(mhs, index);
+            }
+            if (index >= mg->max_tp_rate)
+                continue;
+            if (mr->cur_tp > cur_tp2) {
+                mg->max_tp_rate2 = index;
+                cur_tp2 = mr->cur_tp;
+            }
+        }
+    }
+    mhs->sample_count *= 4;
+    cur_prob = 0;
+    cur_prob_tp = 0;
+    cur_tp = 0;
+    cur_tp2 = 0;
+    for (group = 0; group < ARRAY_SIZE(ssv_minstrel_mcs_groups); group++) {
+        mg = &mhs->groups[group];
+        if (!mg->supported)
+            continue;
+        mr = ssv_minstrel_ht_get_ratestats(mhs, mg->max_prob_rate);
+        if (cur_prob_tp < mr->cur_tp && ssv_minstrel_mcs_groups[group].streams == 1) {
+            mhs->max_prob_rate = mg->max_prob_rate;
+            cur_prob = mr->cur_prob;
+            cur_prob_tp = mr->cur_tp;
+        }
+        mr = ssv_minstrel_ht_get_ratestats(mhs, mg->max_tp_rate);
+        if (cur_tp < mr->cur_tp) {
+            mhs->max_tp_rate2 = mhs->max_tp_rate;
+            cur_tp2 = cur_tp;
+            mhs->max_tp_rate = mg->max_tp_rate;
+            cur_tp = mr->cur_tp;
+        }
+        mr = ssv_minstrel_ht_get_ratestats(mhs, mg->max_tp_rate2);
+        if (cur_tp2 < mr->cur_tp) {
+            mhs->max_tp_rate2 = mg->max_tp_rate2;
+            cur_tp2 = mr->cur_tp;
+        }
+    }
+#define SSV_HT_RC_CHANGE_CCK_RSSI_THRESHOLD (-70)
+    group = SSV_MINSTREL_STA_GROUP(mhs->max_tp_rate);
+    if (mhs->cck_supported && (group != SSV_MINSTREL_CCK_GROUP) && (signal < SSV_HT_RC_CHANGE_CCK_RSSI_THRESHOLD)) {
+        if ((0 == (GET_RATE_INDEX(mhs->max_tp_rate))) || (1 == (GET_RATE_INDEX(mhs->max_tp_rate)))) {
+            mr = ssv_minstrel_ht_get_ratestats(mhs, mhs->max_tp_rate);
+            if ((mr->probability < MINSTREL_FRAC(1, 4) )||
+                (0 == (GET_RATE_INDEX(mhs->max_tp_rate)))) {
+                mhs->max_tp_rate = SSV_MINSTREL_CCK_GROUP * MCS_GROUP_RATES + 3;
+                if (mhs->cck_supported_short)
+                    mhs->max_tp_rate += 4;
+                cur_tp = 0;
+                mg = &mhs->groups[SSV_MINSTREL_CCK_GROUP];
+                for (i = MCS_GROUP_RATES - 1; i >= 0; i--) {
+                    if (!(mg->supported & BIT(i)))
+                        continue;
+                    mr = &mg->rates[i];
+                    if (cur_tp < mr->cur_tp) {
+                        mhs->max_tp_rate = SSV_MINSTREL_CCK_GROUP * MCS_GROUP_RATES + i;
+                        cur_tp = mr->cur_tp;
+                    }
+                }
+            }
+        }
+    }
+    mr = ssv_minstrel_ht_get_ratestats(mhs, mhs->max_tp_rate);
+    ssv_sta_priv->max_ampdu_size = SSV_AMPDU_SIZE_1_2(sc->sh);
+    if (mr->last_attempts > 0) {
+        if (MINSTREL_FRAC(mr->last_success, mr->last_attempts)
+            < MINSTREL_FRAC( sc->sh->cfg.aggr_size_sel_pr, 100))
+            ssv_sta_priv->max_ampdu_size = SSV_AMPDU_SIZE_3_7(sc->sh);
+    }
+    group = SSV_MINSTREL_STA_GROUP(mhs->max_tp_rate);
+    if (sc->sh->cfg.rc_log) {
+        printk(" max_tp_rate after selection %d\n", mhs->max_tp_rate);
+    }
+    if (group != SSV_MINSTREL_CCK_GROUP) {
+        u16 target_success;
+        rate_idx = GET_RATE_INDEX(mhs->max_tp_rate);
+        if (rate_idx >=2) {
+            if (rate_idx > 5)
+                target_success = rc_setting->target_success_67;
+            else if (rate_idx == 5)
+                target_success = rc_setting->target_success_5;
+            else if (rate_idx == 4)
+                target_success = rc_setting->target_success_4;
+            else
+                target_success = rc_setting->target_success;
+            if (mr->probability < MINSTREL_FRAC(target_success, 100)) {
+                mhs->max_tp_rate --;
+                rate_idx --;
+                if (mr->sample_skipped > 0 )
+                    mr->probability = minstrel_ewma(mr->probability, 0, 80);
+            }
+        }
+    } else {
+        rate_idx = GET_CCK_RATE_INDEX(mhs->max_tp_rate);
+        if (mr->probability < MINSTREL_FRAC(3, 10)) {
+            if (rate_idx!=0) {
+                mhs->max_tp_rate --;
+                rate_idx --;
+            }
+            if ((GET_RATE_INDEX(mhs->max_tp_rate) == 4) || (GET_RATE_INDEX(mhs->max_tp_rate) == 5)) {
+                mhs->max_tp_rate -= 4;
+                rate_idx -= 4;
+            }
+            if (mr->sample_skipped > 0 )
+                mr->probability = minstrel_ewma(mr->probability, 0, 80);
+        }
+    }
+    if (rate_idx >= 2) {
+        mhs->max_tp_rate2 = mhs->max_tp_rate - 1;
+        if (mhs->max_prob_rate >= mhs->max_tp_rate2)
+            mhs->max_prob_rate = mhs->max_tp_rate2 - 1;
+    } else {
+        mhs->max_tp_rate2 = group * MCS_GROUP_RATES;
+        if (mhs->max_prob_rate > mhs->max_tp_rate2)
+            mhs->max_prob_rate = mhs->max_tp_rate2;
+    }
+    if (group == SSV_MINSTREL_CCK_GROUP) {
+        if (rate_idx == 1)
+            mhs->max_tp_rate -=1;
+        if (GET_CCK_RATE_INDEX(mhs->max_tp_rate2) == 1)
+            mhs->max_tp_rate2 -=1;
+        if (GET_CCK_RATE_INDEX(mhs->max_prob_rate) == 1)
+            mhs->max_prob_rate -= 1;
+    }
+    if (group != SSV_MINSTREL_CCK_GROUP)
+        minstrel_sta_priv->update_aggr_check = true;
+    mg->max_tp_rate =mhs->max_tp_rate;
+    mg->max_tp_rate2 =mhs->max_tp_rate2;
+    mg->max_prob_rate = mhs->max_prob_rate;
+    mhs->stats_update = jiffies;
+    if (sc->sh->cfg.rc_log) {
+        printk("%s()\n", __FUNCTION__);
+        for (group = 0; group < ARRAY_SIZE(ssv_minstrel_mcs_groups); group++) {
+            mg = &mhs->groups[group];
+            if (!mg->supported)
+                continue;
+            printk("rate group[%d]\n", group);
+            for (i = 0; i < MCS_GROUP_RATES; i++) {
+                printk("rate[%d], succ_hist=%llu, att_hist=%llu, cur_prob=%d, probability=%d, cur_tp=%d\n",
+                       i, mg->rates[i].succ_hist, mg->rates[i].att_hist,
+                       mg->rates[i].cur_prob, mg->rates[i].probability, mg->rates[i].cur_tp);
+            }
+            printk("\n\n");
+            printk("max_tp_rate=%d, max_tp_rate2=%d, max_prob_rate=%d\n",
+                   mg->max_tp_rate, mg->max_tp_rate2, mg->max_prob_rate);
+        }
+    }
+}
+static void ssv_minstrel_ht_update_secondary_edcca_stats(struct ssv_softc *sc, struct ssv_minstrel_ht_sta *mhs)
+{
+    int primary = 0, secondary = 0;
+    primary = GET_PRIMARY_EDCA(sc);
+    secondary = GET_SECONDARY_EDCA(sc);
+    if ((sc->hw_chan_type == NL80211_CHAN_HT40MINUS) || (sc->hw_chan_type == NL80211_CHAN_HT40PLUS)) {
+        if (secondary < 50)
+            mhs->secondary_channel_clear = 1;
+        else
+            mhs->secondary_channel_clear = 0;
+    } else {
+        mhs->secondary_channel_clear = 0;
+    }
+}
+static void _check_sgi(struct ssv_softc *sc, struct ssv_minstrel_ht_sta *mhs, int ampdu_len, int ampdu_ack_len, int short_gi)
+{
+    if (mhs->sgi_state == SGI_DETECT_MCS67) {
+        if (mhs->sgi_state_count < 16) {
+            if (ampdu_len >= 4) {
+                mhs->sgi_state_count++ ;
+                mhs->sgi_state_total += ampdu_len;
+                mhs->sgi_state_success += ampdu_ack_len;
+            }
+            if (sc->sh->cfg.auto_sgi & AUTOSGI_DBG)
+                printk(" state: SGI_DETECT_MCS67 ampdu_size %d, ack_num %d total %d, success %d\n", ampdu_len,ampdu_ack_len
+                       , mhs->sgi_state_total, mhs->sgi_state_success);
+        } else {
+            if ((mhs->sgi_state_total-mhs->sgi_state_success) < (mhs->sgi_state_total >>2)) {
+                mhs->sgi_state = SGI_DETECT_SGI;
+                if (sc->sh->cfg.auto_sgi & AUTOSGI_DBG)
+                    printk("Change to state SGI_DETECT_SGI\n");
+            }
+            mhs->sgi_state_lgi_success = MINSTREL_FRAC(mhs->sgi_state_success, mhs->sgi_state_total);
+            mhs->sgi_state_count = 0;
+            mhs->sgi_state_total = 0;
+            mhs->sgi_state_success = 0;
+        }
+    } else if ((mhs->sgi_state == SGI_DETECT_SGI) && (short_gi!=0)) {
+        if (mhs->sgi_state_count < 32) {
+            if (ampdu_len >= 4) {
+                mhs->sgi_state_count++ ;
+                mhs->sgi_state_total += ampdu_len;
+                mhs->sgi_state_success += ampdu_ack_len;
+            }
+            if (sc->sh->cfg.auto_sgi & AUTOSGI_DBG)
+                printk(" state SGI_DETECT_SGI:ampdu_size %d, ack_num %d count %d ,total %d, success %d\n",
+                       ampdu_len,ampdu_ack_len,mhs->sgi_state_count, mhs->sgi_state_total, mhs->sgi_state_success);
+        } else {
+            if (MINSTREL_FRAC(mhs->sgi_state_success, mhs->sgi_state_total) > (mhs->sgi_state_lgi_success*9/10)) {
+                mhs->sgi_state = SGI_ENABLE_SGI;
+                if (sc->sh->cfg.auto_sgi & AUTOSGI_DBG)
+                    printk("change state: SGI_ENABLE_SGI %d, threshold %d\n",
+                           MINSTREL_FRAC(mhs->sgi_state_success, mhs->sgi_state_total), (mhs->sgi_state_lgi_success*9/10));
+            } else {
+                mhs->sgi_state = SGI_FORBID_SGI;
+                if (sc->sh->cfg.auto_sgi & AUTOSGI_DBG)
+                    printk("change state: SGI_FORBID_SGI sgi %d, threshold %d\n",
+                           MINSTREL_FRAC(mhs->sgi_state_success, mhs->sgi_state_total), (mhs->sgi_state_lgi_success*9/10));
+            }
+        }
+    }
+}
+void ssv_minstrel_ht_tx_status(struct ssv_softc *sc, void *rc_info,
+                               struct ssv_minstrel_ht_rpt ht_rpt[], int ht_rpt_num,
+                               int ampdu_len, int ampdu_ack_len, bool is_sample)
+{
+    struct ieee80211_hw *hw = sc->hw;
+    struct ssv_minstrel_sta_priv *minstrel_sta_priv = (struct ssv_minstrel_sta_priv *)rc_info;
+    struct ssv_minstrel_ht_sta *mhs;
+    struct ssv_minstrel_ht_rate_stats *rate;
+    struct ssv_minstrel_priv *smp = (struct ssv_minstrel_priv *)sc->rc;
+    u16 sta_cap = minstrel_sta_priv->sta->ht_cap.cap;
+    int group, r_idx, short_gi, ht40, phy;
+    enum nl80211_channel_type channel_type;
+    int i = 0;
+    if (!minstrel_sta_priv || !minstrel_sta_priv->is_ht)
+        return;
+    mhs = &minstrel_sta_priv->ht;
+    mhs->ampdu_packets++;
+    mhs->ampdu_len += ampdu_len;
+    if (!mhs->sample_wait && !mhs->sample_tries && mhs->sample_count > 0) {
+        mhs->sample_wait = 16 + 2 * MINSTREL_TRUNC(mhs->avg_ampdu_len);
+        mhs->sample_tries = 2;
+        mhs->sample_count--;
+    }
+    if (is_sample)
+        mhs->sample_packets += ampdu_len;
+    for (i = 0; i < ht_rpt_num; i++) {
+        r_idx = ht_rpt[i].dword & 0x07;
+        short_gi = ((ht_rpt[i].dword & 0x10) >> 4);
+        ht40 = ((ht_rpt[i].dword & 0x20) >> 5);
+        phy = ((ht_rpt[i].dword & 0xC0) >> 6);
+        if (r_idx < 0)
+            break;
+        if (phy == 0x3) {
+            group = mhs->group_idx;
+            rate = &mhs->groups[group].rates[r_idx % 8];
+            if ((sc->sh->cfg.auto_sgi & AUTOSGI_CTL) && (!is_sample)) {
+                if (ampdu_len >= 4) {
+                    if ((r_idx == 6) || (r_idx ==7)) {
+                        _check_sgi(sc, mhs, ampdu_len, ampdu_ack_len, short_gi);
+                    } else {
+                        mhs->sgi_state_count = 0;
+                        mhs->sgi_state_total = 0;
+                        mhs->sgi_state_success = 0;
+                    }
+                }
+            }
+        } else {
+            group = SSV_MINSTREL_CCK_GROUP;
+            if (short_gi)
+                rate = &mhs->groups[group].rates[(r_idx % 4) + 4];
+            else
+                rate = &mhs->groups[group].rates[r_idx % 4];
+        }
+        rate->success += ht_rpt[i].success * ampdu_ack_len;
+        if ( ht_rpt[i].success) {
+            rate->attempts += (ht_rpt[i].count-1) + ampdu_len;
+            mhs->hw_success_acc ++;
+            mhs->hw_retry_acc += (ht_rpt[i].count-1);
+        } else {
+            rate->attempts += ht_rpt[i].count;
+            mhs->hw_retry_acc += ht_rpt[i].count;
+        }
+        if (sc->sh->cfg.rc_log) {
+            printk("%s(), group[%d],rates[%d], success=%d, attempts=%d\n",
+                   __FUNCTION__, group, r_idx % 8, rate->success, rate->attempts);
+        }
+        if (ht_rpt[i].last)
+            break;
+    }
+    if (time_after(jiffies, mhs->stats_update + (smp->update_interval / 2 * HZ) / 1000)) {
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0)
+        channel_type = hw->conf.channel_type;
+#else
+        channel_type = cfg80211_get_chandef_type(&hw->conf.chandef);
+#endif
+        if ((sta_cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40) &&
+            ((channel_type == NL80211_CHAN_HT40MINUS) || (channel_type == NL80211_CHAN_HT40PLUS)))
+            ssv_minstrel_ht_update_secondary_edcca_stats(sc, mhs);
+        ssv_minstrel_ht_update_stats(sc, smp, minstrel_sta_priv, mhs);
+    }
+}
+void ssv_minstrel_ht_get_rate(void *priv, struct ieee80211_sta *sta, void *priv_sta,
+                              struct ieee80211_tx_rate_control *txrc)
+{
+    struct ieee80211_tx_info *info = IEEE80211_SKB_CB(txrc->skb);
+    struct ieee80211_tx_rate *ar = info->control.rates;
+    struct ssv_minstrel_sta_priv *sta_priv = priv_sta;
+    struct ssv_minstrel_ht_sta *mhs = &sta_priv->ht;
+    struct ssv_softc *sc = priv;
+    struct ssv_minstrel_priv *smp = (struct ssv_minstrel_priv *)sc->rc;
+    int sample_idx;
+    bool sample = false;
+    if (rate_control_send_low(sta, priv_sta, txrc))
+        return;
+    info->flags |= mhs->tx_flags;
+    if (smp->max_rates == 1 && txrc->skb->protocol == cpu_to_be16(ETH_P_PAE))
+        sample_idx = -1;
+    else
+        sample_idx = ssv_minstrel_ht_get_sample_rate(sc, smp, mhs);
+    if (sample_idx >= 0) {
+        sample = true;
+        ssv_minstrel_ht_set_rate(sc, smp, mhs, &ar[0], 0, sample_idx, sc->cur_channel->band, true, false);
+        info->flags |= IEEE80211_TX_CTL_RATE_CTRL_PROBE;
+    } else {
+        ssv_minstrel_ht_set_rate(sc, smp, mhs, &ar[0], 0, mhs->max_tp_rate, sc->cur_channel->band, false, false);
+    }
+    if (smp->max_rates >= 3) {
+        if (sample_idx >= 0)
+            ssv_minstrel_ht_set_rate(sc, smp, mhs, &ar[1], 1, mhs->max_tp_rate, sc->cur_channel->band, false, false);
+        else
+            ssv_minstrel_ht_set_rate(sc, smp, mhs, &ar[1], 1, mhs->max_tp_rate2, sc->cur_channel->band, false, false);
+        ssv_minstrel_ht_set_rate(sc, smp, mhs, &ar[2], 2, mhs->max_prob_rate, sc->cur_channel->band, false, true);
+        ar[3].count = 0;
+        ar[3].idx = -1;
+    } else if (smp->max_rates == 2) {
+        ssv_minstrel_ht_set_rate(sc, smp, mhs, &ar[1], 1, mhs->max_prob_rate, sc->cur_channel->band, false, true);
+        ar[2].count = 0;
+        ar[2].idx = -1;
+    } else {
+        ar[1].count = 0;
+        ar[1].idx = -1;
+    }
+    mhs->total_packets++;
+    if (mhs->total_packets == ~0) {
+        mhs->total_packets = 0;
+        mhs->sample_packets = 0;
+    }
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_RATE_CONTROL,
+             "%s():\nar[0].idx=%02x, ar[0].flags=%02x, ar[0].count=%d\n"
+             "ar[1].idx=%02x, ar[1].flags=%02x, ar[1].count=%d\n"
+             "ar[2].idx=%02x, ar[2].flags=%02x, ar[2].count=%d\n"
+             "ar[3].idx=%02x, ar[3].flags=%02x, ar[3].count=%d\n",
+             __FUNCTION__, ar[0].idx, ar[0].flags, ar[0].count, ar[1].idx, ar[1].flags, ar[1].count,
+             ar[2].idx, ar[2].flags, ar[2].count, ar[3].idx, ar[3].flags, ar[3].count);
+}
+static void ssv_minstrel_ht_update_cck(struct ssv_softc *sc, struct ssv_minstrel_priv *smp,
+                                       struct ssv_minstrel_ht_sta *mhs,
+                                       struct ieee80211_supported_band *sband,
+                                       struct ieee80211_sta *sta)
+{
+    int i;
+    if (!sc->sh->cfg.rc_ht_support_cck)
+        return;
+    if (sband->band != INDEX_80211_BAND_2GHZ)
+        return;
+    mhs->cck_supported = 0;
+    mhs->cck_supported_short = 0;
+    for (i = 0; i < 4; i++) {
+        if (!rate_supported(sta, sband->band, smp->cck_rates[i]))
+            continue;
+        mhs->cck_supported |= BIT(i);
+        if (sband->bitrates[i].flags & IEEE80211_RATE_SHORT_PREAMBLE)
+            mhs->cck_supported_short |= BIT(i);
+    }
+    if (mhs->cck_supported_short) {
+        mhs->groups[SSV_MINSTREL_CCK_GROUP].supported = 0xc3;
+        mhs->groups[SSV_MINSTREL_CCK_GROUP].max_tp_rate = SSV_MINSTREL_CCK_GROUP * MCS_GROUP_RATES + 4;
+    } else {
+        mhs->groups[SSV_MINSTREL_CCK_GROUP].supported = 0x0f;
+        mhs->groups[SSV_MINSTREL_CCK_GROUP].max_tp_rate = SSV_MINSTREL_CCK_GROUP * MCS_GROUP_RATES;
+    }
+}
+void ssv_minstrel_ht_update_caps(void *priv, struct ieee80211_supported_band *sband,
+                                 struct ieee80211_sta *sta, void *priv_sta, enum nl80211_channel_type oper_chan_type)
+{
+    struct ssv_softc *sc = priv;
+    struct ssv_minstrel_priv *smp = (struct ssv_minstrel_priv *)sc->rc;
+    struct ssv_minstrel_sta_priv *sta_priv = priv_sta;
+    struct ssv_minstrel_ht_sta *mhs = &sta_priv->ht;
+    struct ieee80211_mcs_info *mcs = &sta->ht_cap.mcs;
+    u16 sta_cap = sta->ht_cap.cap;
+    int ack_dur;
+    int stbc;
+    bool is_sgi = false;
+    sta_priv->is_ht = true;
+    memset(mhs, 0, sizeof(*mhs));
+    mhs->stats_update = jiffies;
+    ack_dur = ieee80211_frame_duration(sband->band, 10, 60, 1, 1);
+    mhs->overhead = ieee80211_frame_duration(sband->band, 0, 60, 1, 1) + ack_dur;
+    mhs->overhead_rtscts = mhs->overhead + 2 * ack_dur;
+    mhs->avg_ampdu_len = MINSTREL_FRAC(1, 1);
+    if (smp->has_mrr) {
+        mhs->sample_count = 16;
+        mhs->sample_wait = 0;
+    } else {
+        mhs->sample_count = 8;
+        mhs->sample_wait = 8;
+    }
+    mhs->sample_tries = 4;
+    stbc = (sta_cap & IEEE80211_HT_CAP_RX_STBC) >> IEEE80211_HT_CAP_RX_STBC_SHIFT;
+    mhs->tx_flags |= stbc << IEEE80211_TX_CTL_STBC_SHIFT;
+    if (sta_cap & IEEE80211_HT_CAP_LDPC_CODING)
+        mhs->tx_flags |= IEEE80211_TX_CTL_LDPC;
+    if (oper_chan_type != NL80211_CHAN_HT40MINUS && oper_chan_type != NL80211_CHAN_HT40PLUS)
+        sta_cap &= ~IEEE80211_HT_CAP_SUP_WIDTH_20_40;
+    if (sta_cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40) {
+        if (sta_cap & IEEE80211_HT_CAP_SGI_40) {
+            mhs->group_idx = GROUP_IDX(1, 1, 1);
+            is_sgi = true;
+        } else
+            mhs->group_idx = GROUP_IDX(1, 0, 1);
+    } else {
+        if (sta_cap & IEEE80211_HT_CAP_SGI_20) {
+            mhs->group_idx = GROUP_IDX(1, 1, 0);
+            is_sgi = true;
+        } else
+            mhs->group_idx = GROUP_IDX(1, 0, 0);
+    }
+    ssv_minstrel_ht_update_cck(sc, smp, mhs, sband, sta);
+    if (sc->sh->cfg.auto_sgi & AUTOSGI_CTL) {
+        if (is_sgi) {
+            mhs->sgi_state = SGI_DETECT_MCS67;
+        } else {
+            mhs->sgi_state = SGI_FORBID_SGI;
+        }
+    } else {
+        mhs->sgi_state = SGI_ENABLE_SGI;
+    }
+    mhs->groups[mhs->group_idx].supported = mcs->rx_mask[ssv_minstrel_mcs_groups[mhs->group_idx].streams - 1];
+    mhs->groups[mhs->group_idx].max_tp_rate = mhs->group_idx * MCS_GROUP_RATES;
+}
+int ssv_minstrel_ht_update_rate(struct ssv_softc *sc, struct sk_buff *skb)
+{
+    struct ssv_minstrel_priv *smp = (struct ssv_minstrel_priv *)sc->rc;
+    struct SKB_info_st *skb_info = (struct SKB_info_st *)skb->head;
+    struct ieee80211_sta *sta = skb_info->sta;
+    struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
+    struct ieee80211_tx_rate *ar = info->control.rates;
+    struct ssv_sta_priv_data *ssv_sta_priv;
+    struct ssv_minstrel_sta_priv *msp;
+    struct ssv_minstrel_ht_sta *mhs;
+    int lowest_rate = 0;
+    int sample_idx;
+    bool sample = false;
+    if (sta == NULL) {
+        WARN_ON(1);
+        return lowest_rate;
+    }
+    ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+    msp = (struct ssv_minstrel_sta_priv *)ssv_sta_priv->rc_info;
+    if ((!msp) || (msp->is_ht == false)) {
+        WARN_ON(1);
+        return lowest_rate;
+    }
+    if (sc->sh->cfg.auto_rate_enable == false) {
+        ssv_minstrel_set_fix_data_rate(sc, msp, ar);
+        return ar[2].idx;
+    }
+    mhs = &msp->ht;
+    info->flags |= mhs->tx_flags;
+    if (smp->max_rates == 1)
+        sample_idx = -1;
+    else
+        sample_idx = ssv_minstrel_ht_get_sample_rate(sc, smp, mhs);
+    if (sample_idx >= 0) {
+        sample = true;
+        ssv_minstrel_ht_set_rate(sc, smp, mhs, &ar[0], 0, sample_idx, sc->cur_channel->band, true, false);
+        info->flags |= IEEE80211_TX_CTL_RATE_CTRL_PROBE;
+    } else {
+        ssv_minstrel_ht_set_rate(sc, smp, mhs, &ar[0], 0, mhs->max_tp_rate, sc->cur_channel->band, false, false);
+    }
+    if (smp->max_rates >= 3) {
+        if (sample_idx >= 0)
+            ssv_minstrel_ht_set_rate(sc, smp, mhs, &ar[1], 1, mhs->max_tp_rate, sc->cur_channel->band, false, false);
+        else
+            ssv_minstrel_ht_set_rate(sc, smp, mhs, &ar[1], 1, mhs->max_tp_rate2, sc->cur_channel->band, false, false);
+        ssv_minstrel_ht_set_rate(sc, smp, mhs, &ar[2], 2, mhs->max_prob_rate, sc->cur_channel->band, false, true);
+        ar[3].count = 0;
+        ar[3].idx = -1;
+        lowest_rate = ar[2].idx;
+    } else if (smp->max_rates == 2) {
+        ssv_minstrel_ht_set_rate(sc, smp, mhs, &ar[1], 1, mhs->max_prob_rate, sc->cur_channel->band, false, true);
+        ar[2].count = 0;
+        ar[2].idx = -1;
+        lowest_rate = ar[1].idx;
+    } else {
+        ar[1].count = 0;
+        ar[1].idx = -1;
+        lowest_rate = ar[0].idx;
+    }
+    dbgprint(&sc->cmd_data, sc->log_ctrl, LOG_RATE_CONTROL,
+             "%s():\nar[0].idx=%02x, ar[0].flags=%02x, ar[0].count=%d\n"
+             "ar[1].idx=%02x, ar[1].flags=%02x, ar[1].count=%d\n"
+             "ar[2].idx=%02x, ar[2].flags=%02x, ar[2].count=%d\n"
+             "ar[3].idx=%02x, ar[3].flags=%02x, ar[3].count=%d\n",
+             __FUNCTION__, ar[0].idx, ar[0].flags, ar[0].count, ar[1].idx, ar[1].flags, ar[1].count,
+             ar[2].idx, ar[2].flags, ar[2].count, ar[3].idx, ar[3].flags, ar[3].count);
+    return lowest_rate;
+}
+bool ssv_minstrel_ht_sta_is_cck_rates(struct ieee80211_sta *sta)
+{
+    struct ssv_sta_priv_data *ssv_sta_priv;
+    struct ssv_minstrel_sta_priv *msp;
+    struct ssv_minstrel_ht_sta *mhs;
+    if (sta == NULL)
+        return false;
+    ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+    msp = (struct ssv_minstrel_sta_priv *)ssv_sta_priv->rc_info;
+    if ((!msp) || (msp->is_ht == false))
+        return false;
+    mhs = &msp->ht;
+    if (SSV_MINSTREL_CCK_GROUP == SSV_MINSTREL_STA_GROUP(mhs->max_tp_rate))
+        return true;
+    else
+        return false;
+}
diff --git a/drivers/net/wireless/ssv6x5x/smac/ssv_rc_minstrel_ht.h b/drivers/net/wireless/ssv6x5x/smac/ssv_rc_minstrel_ht.h
new file mode 100644
index 000000000..eb99afaba
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/ssv_rc_minstrel_ht.h
@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV_RC_MINSTREL_HT_H_
+#define _SSV_RC_MINSTREL_HT_H_
+#define EWMA_LEVEL 75
+#define MINSTREL_MAX_STREAMS 1
+#define MINSTREL_STREAM_GROUPS 4
+#define MINSTREL_SCALE 16
+#define MINSTREL_FRAC(val,div) (((val) << MINSTREL_SCALE) / div)
+#define MINSTREL_TRUNC(val) ((val) >> MINSTREL_SCALE)
+#define MCS_GROUP_RATES 8
+#define SSV_MINSTREL_AMPDU_RATE_RPTS 128
+#define GET_RATE_INDEX(_max_tp_rate) ( _max_tp_rate % MCS_GROUP_RATES)
+#define GET_CCK_RATE_INDEX(_max_tp_rate) ( _max_tp_rate % 4)
+struct ssv_minstrel_ht_rpt {
+    u8 dword;
+    u8 count;
+    int success;
+    int last;
+};
+struct ssv_minstrel_ampdu_rate_rpt {
+    bool used;
+    int pkt_no;
+    int ampdu_len;
+    int ampdu_ack_len;
+    bool is_sample;
+    struct ssv_minstrel_ht_rpt rate_rpt[4];
+};
+struct ssv_mcs_ht_group {
+    u32 flags;
+    unsigned int streams;
+    unsigned int duration[MCS_GROUP_RATES];
+};
+struct ssv_minstrel_ht_rate_stats {
+    unsigned int attempts, last_attempts;
+    unsigned int success, last_success;
+    u64 att_hist, succ_hist;
+    unsigned int cur_tp;
+    unsigned int cur_prob, probability;
+    unsigned int retry_count;
+    unsigned int retry_count_rtscts;
+    bool retry_updated;
+    u16 sample_skipped;
+    unsigned long last_jiffies;
+};
+struct ssv_minstrel_ht_mcs_group_data {
+    u8 index;
+    u8 column;
+    u8 supported;
+    unsigned int max_tp_rate;
+    unsigned int max_tp_rate2;
+    unsigned int max_prob_rate;
+    struct ssv_minstrel_ht_rate_stats rates[MCS_GROUP_RATES];
+};
+struct ssv_minstrel_ht_sta {
+    unsigned int ampdu_len;
+    unsigned int ampdu_packets;
+    unsigned int avg_ampdu_len;
+    unsigned int max_tp_rate;
+    unsigned int max_tp_rate2;
+    unsigned int max_prob_rate;
+    unsigned long stats_update;
+    unsigned int overhead;
+    unsigned int overhead_rtscts;
+    u64 total_packets;
+    u64 sample_packets;
+    u32 tx_flags;
+    u8 sample_wait;
+    u8 sample_tries;
+    u8 sample_count;
+    u8 sample_slow;
+    u8 sample_group;
+    u8 group_idx;
+    u32 secondary_channel_clear;
+    u8 cck_supported;
+    u8 cck_supported_short;
+    struct ssv_minstrel_ht_mcs_group_data groups[MINSTREL_MAX_STREAMS * MINSTREL_STREAM_GROUPS + 1];
+    struct ssv_minstrel_ampdu_rate_rpt ampdu_rpt_list[SSV_MINSTREL_AMPDU_RATE_RPTS];
+    u32 sgi_state_lgi_success;
+    u8 sgi_state_count;
+    u8 sgi_state;
+    u32 sgi_state_total;
+    u32 sgi_state_success;
+    u32 hw_retry_acc;
+    u32 hw_success_acc;
+};
+enum ssv6xxx_sgi_stat {
+    SGI_DETECT_MCS67,
+    SGI_DETECT_SGI,
+    SGI_FORBID_SGI,
+    SGI_ENABLE_SGI,
+};
+void ssv_minstrel_ht_init_sample_table(void);
+int ssv_minstrel_ht_update_rate(struct ssv_softc *sc, struct sk_buff *skb);
+bool ssv_minstrel_ht_sta_is_cck_rates(struct ieee80211_sta *sta);
+void ssv_minstrel_ht_tx_status(struct ssv_softc *sc, void *rc_info,
+                               struct ssv_minstrel_ht_rpt ht_rpt[], int ht_rpt_num,
+                               int ampdu_len, int ampdu_ack_len, bool is_sample);
+void ssv_minstrel_ht_get_rate(void *priv, struct ieee80211_sta *sta, void *priv_sta,
+                              struct ieee80211_tx_rate_control *txrc);
+void ssv_minstrel_ht_update_caps(void *priv, struct ieee80211_supported_band *sband,
+                                 struct ieee80211_sta *sta, void *priv_sta, enum nl80211_channel_type oper_chan_type);
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smac/ssv_reg_acc.h b/drivers/net/wireless/ssv6x5x/smac/ssv_reg_acc.h
new file mode 100644
index 000000000..41b4e79ba
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/ssv_reg_acc.h
@@ -0,0 +1,135 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV_REG_ACC_H_
+#define _SSV_REG_ACC_H_
+#define SMAC_REG_WRITE(_s,_r,_v) \
+        ({ \
+            typeof(_s) __s = _s; \
+            if ( _s->sc->log_ctrl & LOG_REGW) \
+                printk("w a:0x%x d:0x%x\n", _r ,_v); \
+            __s->hci.hci_ops->hci_write_word(__s->hci.hci_ctrl, _r,_v); \
+        })
+#define SMAC_REG_READ(_s,_r,_v) \
+        ({ \
+            typeof(_s) __s = _s; \
+            __s->hci.hci_ops->hci_read_word(__s->hci.hci_ctrl, _r, _v); \
+        })
+#define SMAC_REG_SAFE_WRITE(_s,_r,_v) \
+        ({ \
+            typeof(_s) __s = _s; \
+            __s->hci.hci_ops->hci_safe_write_word(__s->hci.hci_ctrl, _r,_v); \
+        })
+#define SMAC_REG_SAFE_READ(_s,_r,_v) \
+        ({ \
+            typeof(_s) __s = _s; \
+            __s->hci.hci_ops->hci_safe_read_word(__s->hci.hci_ctrl, _r, _v); \
+        })
+#ifndef __x86_64
+#define SMAC_RF_REG_READ(_s,_r,_v) SMAC_REG_READ(_s, _r, _v)
+#else
+#define SMAC_RF_REG_READ(_s,_r,_v) \
+        ({ \
+            typeof(_s) __s = _s; \
+            __s->hci.hci_ops->hci_read_word(__s->hci.hci_ctrl, _r, _v); \
+            __s->hci.hci_ops->hci_read_word(__s->hci.hci_ctrl, _r, _v); \
+        })
+#endif
+#define SMAC_BURST_REG_SAFE_READ(_s,_r,_v,_n) \
+        ({ \
+            typeof(_s) __s = _s; \
+            __s->hci.hci_ops->hci_burst_safe_read_word(__s->hci.hci_ctrl, _r, _v, _n); \
+        })
+#define SMAC_BURST_REG_SAFE_WRITE(_s,_r,_v,_n) \
+        ({ \
+            typeof(_s) __s = _s; \
+            __s->hci.hci_ops->hci_burst_safe_write_word(__s->hci.hci_ctrl, _r, _v, _n); \
+        })
+#define SMAC_BURST_REG_READ(_s,_r,_v,_n) \
+        ({ \
+            typeof(_s) __s = _s; \
+            __s->hci.hci_ops->hci_burst_read_word(__s->hci.hci_ctrl, _r, _v, _n); \
+        })
+#define SMAC_BURST_REG_WRITE(_s,_r,_v,_n) \
+        ({ \
+            typeof(_s) __s = _s; \
+            __s->hci.hci_ops->hci_burst_write_word(__s->hci.hci_ctrl, _r, _v, _n); \
+        })
+#define SMAC_LOAD_FW(_s,_r,_v) \
+        ({ \
+            typeof(_s) __s = _s; \
+            __s->hci.hci_ops->hci_load_fw(__s->hci.hci_ctrl, _r, _v); \
+        })
+#define SMAC_IFC_RESET(_s) \
+        ({ \
+            typeof(_s) __s = _s; \
+            __s->hci.hci_ops->hci_interface_reset(__s->hci.hci_ctrl); \
+        })
+#define SMAC_SYSPLF_RESET(_s,_r,_v) \
+        ({ \
+            typeof(_s) __s = _s; \
+            __s->hci.hci_ops->hci_sysplf_reset(__s->hci.hci_ctrl, _r, _v); \
+        })
+#define SMAC_REG_CONFIRM(_s,_r,_v) \
+{ \
+    u32 _regval; \
+    SMAC_REG_READ(_s, _r, &_regval); \
+    if (_regval != (_v)) { \
+        printk("ERROR!!Please check interface!\n"); \
+        printk("[0x%08x]: 0x%08x!=0x%08x\n", \
+        (_r), (_v), _regval); \
+        printk("SOS!SOS!\n"); \
+        return -1; \
+    } \
+}
+#define SMAC_REG_SET_BITS(_sh,_reg,_set,_clr) \
+({ \
+    int ret; \
+    u32 _regval; \
+    ret = SMAC_REG_READ(_sh, _reg, &_regval); \
+    _regval &= ~(_clr); \
+    _regval |= (_set); \
+    if (ret == 0) \
+        ret = SMAC_REG_WRITE(_sh, _reg, _regval); \
+    ret; \
+})
+#define SMAC_REG_SAFE_SET_BITS(_sh,_reg,_set,_clr) \
+({ \
+    int ret; \
+    u32 _regval; \
+    ret = SMAC_REG_SAFE_READ(_sh, _reg, &_regval); \
+    _regval &= ~(_clr); \
+    _regval |= (_set); \
+    if (ret == 0) \
+        ret = SMAC_REG_SAFE_WRITE(_sh, _reg, _regval); \
+    ret; \
+})
+#ifndef __x86_64
+#define SMAC_RF_REG_SET_BITS(_sh,_reg,_set,_clr) SMAC_REG_SET_BITS(_sh, _reg, _set, _clr)
+#else
+#define SMAC_RF_REG_SET_BITS(_sh,_reg,_set,_clr) \
+({ \
+    int ret; \
+    u32 _regval; \
+    ret = SMAC_REG_READ(_sh, _reg, &_regval); \
+    ret = SMAC_REG_READ(_sh, _reg, &_regval); \
+    _regval &= ~(_clr); \
+    _regval |= (_set); \
+    if (ret == 0) \
+        ret = SMAC_REG_WRITE(_sh, _reg, _regval); \
+    ret; \
+})
+#endif
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smac/ssv_skb.c b/drivers/net/wireless/ssv6x5x/smac/ssv_skb.c
new file mode 100644
index 000000000..4192913a8
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/ssv_skb.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/version.h>
+#include "ssv_skb.h"
+#include <ssv6200.h>
+struct sk_buff *ssv_skb_alloc(void *app_param, s32 len)
+{
+    struct sk_buff *skb;
+    skb = __dev_alloc_skb(len + SSV6200_ALLOC_RSVD, GFP_KERNEL);
+    if (skb != NULL) {
+        skb_reserve(skb, SSV_SKB_info_size);
+    }
+    return skb;
+}
+struct sk_buff *ssv_skb_alloc_ex(void *app_param, s32 len, gfp_t gfp_mask)
+{
+    struct sk_buff *skb;
+    skb = __dev_alloc_skb(len + SSV6200_ALLOC_RSVD, gfp_mask);
+    if (skb != NULL) {
+        skb_reserve(skb, SSV_SKB_info_size);
+    }
+    return skb;
+}
+void ssv_skb_free(void *app_param, struct sk_buff *skb)
+{
+    dev_kfree_skb_any(skb);
+}
diff --git a/drivers/net/wireless/ssv6x5x/smac/ssv_skb.h b/drivers/net/wireless/ssv6x5x/smac/ssv_skb.h
new file mode 100644
index 000000000..b898cf9d6
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/ssv_skb.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV_SKB_H_
+#define _SSV_SKB_H_
+#include <linux/skbuff.h>
+#include <ssv6xxx_common.h>
+struct SKB_info_st {
+    struct ieee80211_sta *sta;
+    u16 mpdu_retry_counter;
+    unsigned long aggr_timestamp;
+    u16 ampdu_tx_status;
+    u16 ampdu_tx_final_retry_count;
+    u16 lowest_rate;
+    struct fw_rc_retry_params rates[SSV62XX_TX_MAX_RATES];
+#ifdef CONFIG_DEBUG_SKB_TIMESTAMP
+    ktime_t timestamp;
+#endif
+#ifdef MULTI_THREAD_ENCRYPT
+    volatile u8 crypt_st;
+#endif
+    bool directly_ack;
+    bool no_update_rpt;
+};
+typedef struct SKB_info_st SKB_info;
+typedef struct SKB_info_st *p_SKB_info;
+struct ampdu_hdr_st {
+    u32 first_sn;
+    struct sk_buff_head mpdu_q;
+    u32 max_size;
+    u32 size;
+    struct AMPDU_TID_st *ampdu_tid;
+    struct ieee80211_sta *sta;
+    u16 mpdu_num;
+    u16 ssn[MAX_AGGR_NUM];
+    struct fw_rc_retry_params rates[SSV62XX_TX_MAX_RATES];
+};
+struct sk_buff *ssv_skb_alloc(void *app_param, s32 len);
+struct sk_buff *ssv_skb_alloc_ex(void *app_param, s32 len, gfp_t gfp_mask);
+void ssv_skb_free(void *app_param, struct sk_buff *skb);
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smac/wapi_sms4.c b/drivers/net/wireless/ssv6x5x/smac/wapi_sms4.c
new file mode 100644
index 000000000..8e5a156df
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/wapi_sms4.c
@@ -0,0 +1,236 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/string.h>
+#define SHA256_BLOCK_SIZE 64
+#define SHA256_DIGEST_SIZE 32
+typedef enum {
+    FALSE = 0,
+    TRUE = 1
+} CsrBool;
+#define BYTES_PER_WORD 4
+#define BYTE_LEN 8
+#define WORD_LEN (BYTE_LEN * BYTES_PER_WORD)
+#define TEXT_LEN 128
+#define MK_LEN (TEXT_LEN / WORD_LEN)
+#define RK_LEN 32
+#define TEXT_BYTES (TEXT_LEN / BYTE_LEN)
+#define CK_INCREMENT 7
+#define KEY_MULTIPLIER 0x80040100
+#define TEXT_MULTIPLIER 0xa0202080
+#define FK_PARAMETER_0 0xa3b1bac6
+#define FK_PARAMETER_1 0x56aa3350
+#define FK_PARAMETER_2 0x677d9197
+#define FK_PARAMETER_3 0xb27022dc
+static const u8 S_Box[] = {
+    0xd6, 0x90, 0xe9, 0xfe, 0xcc, 0xe1, 0x3d, 0xb7, 0x16, 0xb6, 0x14, 0xc2, 0x28, 0xfb, 0x2c, 0x05,
+    0x2b, 0x67, 0x9a, 0x76, 0x2a, 0xbe, 0x04, 0xc3, 0xaa, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99,
+    0x9c, 0x42, 0x50, 0xf4, 0x91, 0xef, 0x98, 0x7a, 0x33, 0x54, 0x0b, 0x43, 0xed, 0xcf, 0xac, 0x62,
+    0xe4, 0xb3, 0x1c, 0xa9, 0xc9, 0x08, 0xe8, 0x95, 0x80, 0xdf, 0x94, 0xfa, 0x75, 0x8f, 0x3f, 0xa6,
+    0x47, 0x07, 0xa7, 0xfc, 0xf3, 0x73, 0x17, 0xba, 0x83, 0x59, 0x3c, 0x19, 0xe6, 0x85, 0x4f, 0xa8,
+    0x68, 0x6b, 0x81, 0xb2, 0x71, 0x64, 0xda, 0x8b, 0xf8, 0xeb, 0x0f, 0x4b, 0x70, 0x56, 0x9d, 0x35,
+    0x1e, 0x24, 0x0e, 0x5e, 0x63, 0x58, 0xd1, 0xa2, 0x25, 0x22, 0x7c, 0x3b, 0x01, 0x21, 0x78, 0x87,
+    0xd4, 0x00, 0x46, 0x57, 0x9f, 0xd3, 0x27, 0x52, 0x4c, 0x36, 0x02, 0xe7, 0xa0, 0xc4, 0xc8, 0x9e,
+    0xea, 0xbf, 0x8a, 0xd2, 0x40, 0xc7, 0x38, 0xb5, 0xa3, 0xf7, 0xf2, 0xce, 0xf9, 0x61, 0x15, 0xa1,
+    0xe0, 0xae, 0x5d, 0xa4, 0x9b, 0x34, 0x1a, 0x55, 0xad, 0x93, 0x32, 0x30, 0xf5, 0x8c, 0xb1, 0xe3,
+    0x1d, 0xf6, 0xe2, 0x2e, 0x82, 0x66, 0xca, 0x60, 0xc0, 0x29, 0x23, 0xab, 0x0d, 0x53, 0x4e, 0x6f,
+    0xd5, 0xdb, 0x37, 0x45, 0xde, 0xfd, 0x8e, 0x2f, 0x03, 0xff, 0x6a, 0x72, 0x6d, 0x6c, 0x5b, 0x51,
+    0x8d, 0x1b, 0xaf, 0x92, 0xbb, 0xdd, 0xbc, 0x7f, 0x11, 0xd9, 0x5c, 0x41, 0x1f, 0x10, 0x5a, 0xd8,
+    0x0a, 0xc1, 0x31, 0x88, 0xa5, 0xcd, 0x7b, 0xbd, 0x2d, 0x74, 0xd0, 0x12, 0xb8, 0xe5, 0xb4, 0xb0,
+    0x89, 0x69, 0x97, 0x4a, 0x0c, 0x96, 0x77, 0x7e, 0x65, 0xb9, 0xf1, 0x09, 0xc5, 0x6e, 0xc6, 0x84,
+    0x18, 0xf0, 0x7d, 0xec, 0x3a, 0xdc, 0x4d, 0x20, 0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48
+};
+static const u32 FK_Parameter[] = { FK_PARAMETER_0, FK_PARAMETER_1, FK_PARAMETER_2, FK_PARAMETER_3 };
+static const u8 S_XState[] = {
+    0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
+    1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
+    1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
+    0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
+    1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
+    0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
+    0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
+    1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
+    1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
+    0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
+    0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
+    1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
+    0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
+    1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
+    1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
+    0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0
+};
+static const u32 g_NextInputTable[RK_LEN] = {
+    0x00070e15, 0x1c232a31, 0x383f464d, 0x545b6269,
+    0x70777e85, 0x8c939aa1, 0xa8afb6bd, 0xc4cbd2d9,
+    0xe0e7eef5, 0xfc030a11, 0x181f262d, 0x343b4249,
+    0x50575e65, 0x6c737a81, 0x888f969d, 0xa4abb2b9,
+    0xc0c7ced5, 0xdce3eaf1, 0xf8ff060d, 0x141b2229,
+    0x30373e45, 0x4c535a61, 0x686f767d, 0x848b9299,
+    0xa0a7aeb5, 0xbcc3cad1, 0xd8dfe6ed, 0xf4fb0209,
+    0x10171e25, 0x2c333a41, 0x484f565d, 0x646b7279
+};
+static const u32 CipherDataIdx[MK_LEN][MK_LEN] = {
+    {3, 2, 1, 0},
+    {0, 3, 2, 1},
+    {1, 0,3, 2},
+    {2, 1, 0, 3}
+};
+#define PARITY_MACRO(Value) (S_XState[(Value) >> 24] ^ S_XState[((Value) >> 16) & 0xFF] ^ S_XState[((Value) >> 8) & 0xFF] ^ S_XState[(Value) & 0xFF])
+#define XOR_MACRO(A,B) ((A) ^ (B))
+#define L_TRANSFORM_MACRO(Word,Key) MultiplyCircular(Word, Key ? KEY_MULTIPLIER : TEXT_MULTIPLIER )
+static u32 T_Transform(u32 Word)
+{
+    u32 j;
+    u32 New_Word;
+    int offset = 0;
+    New_Word = 0;
+    for (j = 0; j < MK_LEN; j++) {
+        New_Word = (New_Word << BYTE_LEN);
+        offset = ((u32)(Word >> (WORD_LEN - BYTE_LEN))) & ((u32)((1 << BYTE_LEN) - 1));
+        New_Word = New_Word | (u32)S_Box[offset];
+        Word = (Word << BYTE_LEN);
+    }
+    return (New_Word);
+}
+static u32 MultiplyCircular(u32 Word, u32 Basis)
+{
+    u32 New_Word;
+    u32 i;
+    New_Word = 0;
+    for (i = 0; i < WORD_LEN; i++) {
+        New_Word = (New_Word << 1) | PARITY_MACRO(Word & Basis);
+        Basis = (Basis >> 1) | ((Basis & 1) << (WORD_LEN - 1));
+    }
+    return (New_Word);
+}
+static u32 Iterate(CsrBool Key, u32 Next_Input, u32 *Cipher_Text, u32 curIdx)
+{
+    u32 New_State;
+    New_State = Next_Input;
+    New_State = XOR_MACRO(New_State, Cipher_Text[CipherDataIdx[curIdx][0]]);
+    New_State = XOR_MACRO(New_State, Cipher_Text[CipherDataIdx[curIdx][1]]);
+    New_State = XOR_MACRO(New_State, Cipher_Text[CipherDataIdx[curIdx][2]]);
+    New_State = L_TRANSFORM_MACRO(T_Transform(New_State), Key);
+    New_State = XOR_MACRO(New_State, Cipher_Text[CipherDataIdx[curIdx][3]]);
+    Cipher_Text[curIdx] = New_State;
+    return (New_State);
+}
+static void CalculateEnKey(u8 *Key, u32 *Key_Store)
+{
+    u32 Cipher_Text[MK_LEN];
+    u32 Next, i, j, Next_Input;
+    for (j = 0; j < MK_LEN; j++) {
+        Next = 0;
+        for (i = 0; i < BYTES_PER_WORD; i++) {
+            Next = (Next << BYTE_LEN);
+            Next = Next | Key[(j <<2) + i];
+        }
+        Cipher_Text[j] = XOR_MACRO(Next, FK_Parameter[j]);
+    }
+    for (i = 0; i < RK_LEN; i++) {
+        Next_Input = g_NextInputTable[i];
+        Key_Store[i] = Iterate(TRUE, Next_Input, Cipher_Text, i & (MK_LEN - 1));
+    }
+}
+static void SMS4_Run(u32 *Key_Store, u8 *PlainText, u8 *CipherText)
+{
+    u32 i, j;
+    u32 Next;
+    u32 Next_Input;
+    u32 Plain_Text[MK_LEN];
+    for (j = 0; j < MK_LEN; j++) {
+        Next = 0;
+        for (i = 0; i < BYTES_PER_WORD; i++) {
+            Next = (Next << BYTE_LEN);
+            Next = Next | PlainText[(j<<2) + i];
+        }
+        Plain_Text[j] = Next;
+    }
+    for (i = 0; i < RK_LEN; i++) {
+        Next_Input = Key_Store[i];
+        (void)Iterate(FALSE, Next_Input, Plain_Text, i & (MK_LEN - 1));
+    }
+    for (j = 0; j < MK_LEN; j++) {
+        Next = Plain_Text[(MK_LEN - 1) - j];
+        for (i = 0; i < BYTES_PER_WORD; i++) {
+            CipherText[(j << 2) + i] = (u8)((Next >> (WORD_LEN - BYTE_LEN)) & ((1 << BYTE_LEN) - 1));
+            Next = (Next << BYTE_LEN);
+        }
+    }
+}
+void WapiCryptoSms4(u8 *iv, u8 *key, u8 *input, u32 length, u8 *output)
+{
+    u32 i;
+    u8 sms4Output[TEXT_BYTES];
+    u8 tmp_data[TEXT_BYTES];
+    u32 Key_Store[RK_LEN];
+    u32 j = 0;
+    u8 * p[2];
+    p[0] = sms4Output;
+    p[1] = tmp_data;
+    memcpy(tmp_data, iv, TEXT_BYTES);
+    CalculateEnKey(key, Key_Store);
+    for (i = 0; i < length; i++) {
+        if ((i & (TEXT_BYTES - 1)) == 0) {
+            SMS4_Run(Key_Store, p[1-j], p[j]);
+            j = 1 - j;
+        }
+        output[i] = input[i] ^ p[1-j][i & (TEXT_BYTES - 1)];
+    }
+}
+void WapiCryptoSms4Mic(u8 *iv, u8 *key, u8 *header, u32 headerLength,
+                       const u8 *input, u32 dataLength, u8 *mic)
+{
+    u32 i, j = 0, totalLength;
+    u8 sms4Output[TEXT_BYTES], sms4Input[TEXT_BYTES];
+    u32 tmp_headerLength = 0;
+    u32 tmp_dataLength = 0;
+    u32 header_cnt = 0 ;
+    u32 header0_cnt = 0;
+    u32 data_cnt = 0;
+    u32 data0_cnt = 0;
+    u32 Key_Store[RK_LEN];
+    memcpy(sms4Input, iv, TEXT_BYTES);
+    totalLength = headerLength + dataLength;
+    tmp_headerLength = ((headerLength & (TEXT_BYTES-1)) == 0) ? 0 : (TEXT_BYTES - (headerLength & (TEXT_BYTES-1)));
+    tmp_dataLength = ((dataLength & (TEXT_BYTES-1)) == 0) ? 0 : (TEXT_BYTES - (dataLength & (TEXT_BYTES-1)));
+    totalLength += tmp_headerLength;
+    totalLength += tmp_dataLength;
+    CalculateEnKey(key, Key_Store);
+    for (i = 0; i < totalLength; i++) {
+        if ((i & (TEXT_BYTES-1)) == 0) {
+            SMS4_Run(Key_Store, sms4Input, sms4Output);
+        }
+        if ((dataLength == 0) && (headerLength == 0)) {
+            sms4Input[i & (TEXT_BYTES-1)] = 0 ^ sms4Output[i & (TEXT_BYTES-1)];
+            data0_cnt++;
+        } else if ( (headerLength == 0) && (tmp_headerLength == 0) ) {
+            sms4Input[i & (TEXT_BYTES-1)] = input[j] ^ sms4Output[i & (TEXT_BYTES-1)];
+            j++;
+            dataLength--;
+            data_cnt++;
+        } else if( headerLength == 0 ) {
+            sms4Input[i & (TEXT_BYTES-1)] = 0 ^ sms4Output[i & (TEXT_BYTES-1)];
+            tmp_headerLength--;
+            header0_cnt++;
+        } else {
+            sms4Input[i & (TEXT_BYTES-1)] = header[i] ^ sms4Output[i & (TEXT_BYTES-1)];
+            headerLength--;
+            header_cnt++;
+        }
+    }
+    SMS4_Run(Key_Store, sms4Input, mic);
+}
diff --git a/drivers/net/wireless/ssv6x5x/smac/wapi_sms4.h b/drivers/net/wireless/ssv6x5x/smac/wapi_sms4.h
new file mode 100644
index 000000000..efad25db2
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smac/wapi_sms4.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef WAPI_SMS4_H
+#define WAPI_SMS4_H
+void WapiCryptoSms4(u8 *iv, u8 *key, u8 *input, u16 length, u8 *output);
+void WapiCryptoSms4Mic(u8 *iv, u8 *Key, u8 *header, u16 headerLength,
+                       const u8 *input, u16 dataLength, u8 *output);
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smartlink/Makefile b/drivers/net/wireless/ssv6x5x/smartlink/Makefile
new file mode 100755
index 000000000..dbb25d932
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smartlink/Makefile
@@ -0,0 +1,12 @@
+all:
+	$(MAKE) -f Makefile.lib
+	$(MAKE) -f Makefile.airkiss
+	$(MAKE) -f Makefile.qqlink
+	$(MAKE) -f Makefile.smarticomm
+
+clean:
+	$(MAKE) -f Makefile.lib     clean
+	$(MAKE) -f Makefile.airkiss clean
+	$(MAKE) -f Makefile.qqlink  clean
+	$(MAKE) -f Makefile.smarticomm clean
+	
diff --git a/drivers/net/wireless/ssv6x5x/smartlink/Makefile.airkiss b/drivers/net/wireless/ssv6x5x/smartlink/Makefile.airkiss
new file mode 100755
index 000000000..8d44baffb
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smartlink/Makefile.airkiss
@@ -0,0 +1,8 @@
+all:
+#	/opt/mipsel-gcc472-glibc216-mips32/bin/mipsel-linux-gcc -o airkiss-mipsel airkiss.c libssv_airkiss.a airkiss-lib/mipsel/libairkiss.a
+#	/opt/mipsel-gcc472-glibc216-mips32/bin/mipsel-linux-gcc -o airkiss airkiss.c libssv_airkiss.a airkiss-lib/mipsel/libairkiss_log.a
+	/opt/mipsel-gcc472-glibc216-mips32/bin/mipsel-linux-gcc -o airkiss-mipsel airkiss.c libssv_smartlink-mipsel.a airkiss-lib/mipsel/libairkiss_aes.a
+#	/opt/mipsel-gcc472-glibc216-mips32/bin/mipsel-linux-gcc -o airkiss airkiss.c libssv_airkiss.a airkiss-lib/mipsel/libairkiss_aes_log.a
+
+	gcc -o airkiss-x64 airkiss.c libssv_smartlink-x64.a airkiss-lib/x64/libairkiss_aes.a
+clean:
diff --git a/drivers/net/wireless/ssv6x5x/smartlink/Makefile.lib b/drivers/net/wireless/ssv6x5x/smartlink/Makefile.lib
new file mode 100755
index 000000000..435ddbfb5
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smartlink/Makefile.lib
@@ -0,0 +1,8 @@
+all:
+	/opt/mipsel-gcc472-glibc216-mips32/bin/mipsel-linux-gcc -c -o ssv_smartlink-mipsel.o ssv_smartlink.c
+	/opt/mipsel-gcc472-glibc216-mips32/bin/mipsel-linux-ar rcs libssv_smartlink-mipsel.a ssv_smartlink-mipsel.o
+
+	gcc -c -o ssv_smartlink-x64.o ssv_smartlink.c
+	ar rcs libssv_smartlink-x64.a ssv_smartlink-x64.o
+clean:
+	rm -rf *.a *.o
diff --git a/drivers/net/wireless/ssv6x5x/smartlink/Makefile.qqlink b/drivers/net/wireless/ssv6x5x/smartlink/Makefile.qqlink
new file mode 100755
index 000000000..796013410
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smartlink/Makefile.qqlink
@@ -0,0 +1,4 @@
+all:
+	/opt/mipsel-gcc472-glibc216-mips32/bin/mipsel-linux-gcc -o qqlink-mipsel qqlink.c libssv_smartlink-mipsel.a qqlink-lib-mipsel/lib/libtxdevicesdk.a -lstdc++ -lm -lpthread -lrt
+	
+clean:
diff --git a/drivers/net/wireless/ssv6x5x/smartlink/Makefile.smarticomm b/drivers/net/wireless/ssv6x5x/smartlink/Makefile.smarticomm
new file mode 100755
index 000000000..24afdd006
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smartlink/Makefile.smarticomm
@@ -0,0 +1,5 @@
+all:
+	/opt/mipsel-gcc472-glibc216-mips32/bin/mipsel-linux-gcc -o smarticomm-mipsel smarticomm.c libssv_smartlink-mipsel.a
+	gcc -o smarticomm-x86 smarticomm.c libssv_smartlink-x64.a
+	
+clean:
diff --git a/drivers/net/wireless/ssv6x5x/smartlink/airkiss-lib/airkiss.h b/drivers/net/wireless/ssv6x5x/smartlink/airkiss-lib/airkiss.h
new file mode 100644
index 000000000..f71177645
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smartlink/airkiss-lib/airkiss.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef AIRKISS_H_
+#define AIRKISS_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+#ifndef AIRKISS_ENABLE_CRYPT
+#define AIRKISS_ENABLE_CRYPT 1
+#endif
+typedef void* (*airkiss_memset_fn) (void* ptr, int value, unsigned int num);
+typedef void* (*airkiss_memcpy_fn) (void* dst, const void* src, unsigned int num);
+typedef int (*airkiss_memcmp_fn) (const void* ptr1, const void* ptr2, unsigned int num);
+typedef int (*airkiss_printf_fn) (const char* format, ...);
+typedef struct {
+    airkiss_memset_fn memset;
+    airkiss_memcpy_fn memcpy;
+    airkiss_memcmp_fn memcmp;
+    airkiss_printf_fn printf;
+} airkiss_config_t;
+typedef struct {
+    int dummyap[26];
+    int dummy[32];
+} airkiss_context_t;
+typedef struct {
+    char* pwd;
+    char* ssid;
+    unsigned char pwd_length;
+    unsigned char ssid_length;
+    unsigned char random;
+    unsigned char reserved;
+} airkiss_result_t;
+typedef enum {
+    AIRKISS_STATUS_CONTINUE = 0,
+    AIRKISS_STATUS_CHANNEL_LOCKED = 1,
+    AIRKISS_STATUS_COMPLETE = 2
+} airkiss_status_t;
+#if AIRKISS_ENABLE_CRYPT
+int airkiss_set_key(airkiss_context_t* context, const unsigned char* key, unsigned int length);
+#endif
+const char* airkiss_version(void);
+int airkiss_init(airkiss_context_t* context, const airkiss_config_t* config);
+int airkiss_recv(airkiss_context_t* context, const void* frame, unsigned short length);
+int airkiss_get_result(airkiss_context_t* context, airkiss_result_t* result);
+int airkiss_change_channel(airkiss_context_t* context);
+typedef enum {
+    AIRKISS_LAN_ERR_OVERFLOW = -5,
+    AIRKISS_LAN_ERR_CMD = -4,
+    AIRKISS_LAN_ERR_PAKE = -3,
+    AIRKISS_LAN_ERR_PARA = -2,
+    AIRKISS_LAN_ERR_PKG = -1,
+    AIRKISS_LAN_CONTINUE = 0,
+    AIRKISS_LAN_SSDP_REQ = 1,
+    AIRKISS_LAN_PAKE_READY = 2
+} airkiss_lan_ret_t;
+typedef enum {
+    AIRKISS_LAN_SSDP_REQ_CMD = 0x1,
+    AIRKISS_LAN_SSDP_RESP_CMD = 0x1001,
+    AIRKISS_LAN_SSDP_NOTIFY_CMD = 0x1002
+} airkiss_lan_cmdid_t;
+int airkiss_lan_recv(const void* body, unsigned short length, const airkiss_config_t* config);
+int airkiss_lan_pack(airkiss_lan_cmdid_t ak_lan_cmdid, void* appid, void* deviceid, void* _datain, unsigned short inlength, void* _dataout, unsigned short* outlength, const airkiss_config_t* config);
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smartlink/airkiss-lib/mipsel/airkiss.h b/drivers/net/wireless/ssv6x5x/smartlink/airkiss-lib/mipsel/airkiss.h
new file mode 100644
index 000000000..f71177645
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smartlink/airkiss-lib/mipsel/airkiss.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef AIRKISS_H_
+#define AIRKISS_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+#ifndef AIRKISS_ENABLE_CRYPT
+#define AIRKISS_ENABLE_CRYPT 1
+#endif
+typedef void* (*airkiss_memset_fn) (void* ptr, int value, unsigned int num);
+typedef void* (*airkiss_memcpy_fn) (void* dst, const void* src, unsigned int num);
+typedef int (*airkiss_memcmp_fn) (const void* ptr1, const void* ptr2, unsigned int num);
+typedef int (*airkiss_printf_fn) (const char* format, ...);
+typedef struct {
+    airkiss_memset_fn memset;
+    airkiss_memcpy_fn memcpy;
+    airkiss_memcmp_fn memcmp;
+    airkiss_printf_fn printf;
+} airkiss_config_t;
+typedef struct {
+    int dummyap[26];
+    int dummy[32];
+} airkiss_context_t;
+typedef struct {
+    char* pwd;
+    char* ssid;
+    unsigned char pwd_length;
+    unsigned char ssid_length;
+    unsigned char random;
+    unsigned char reserved;
+} airkiss_result_t;
+typedef enum {
+    AIRKISS_STATUS_CONTINUE = 0,
+    AIRKISS_STATUS_CHANNEL_LOCKED = 1,
+    AIRKISS_STATUS_COMPLETE = 2
+} airkiss_status_t;
+#if AIRKISS_ENABLE_CRYPT
+int airkiss_set_key(airkiss_context_t* context, const unsigned char* key, unsigned int length);
+#endif
+const char* airkiss_version(void);
+int airkiss_init(airkiss_context_t* context, const airkiss_config_t* config);
+int airkiss_recv(airkiss_context_t* context, const void* frame, unsigned short length);
+int airkiss_get_result(airkiss_context_t* context, airkiss_result_t* result);
+int airkiss_change_channel(airkiss_context_t* context);
+typedef enum {
+    AIRKISS_LAN_ERR_OVERFLOW = -5,
+    AIRKISS_LAN_ERR_CMD = -4,
+    AIRKISS_LAN_ERR_PAKE = -3,
+    AIRKISS_LAN_ERR_PARA = -2,
+    AIRKISS_LAN_ERR_PKG = -1,
+    AIRKISS_LAN_CONTINUE = 0,
+    AIRKISS_LAN_SSDP_REQ = 1,
+    AIRKISS_LAN_PAKE_READY = 2
+} airkiss_lan_ret_t;
+typedef enum {
+    AIRKISS_LAN_SSDP_REQ_CMD = 0x1,
+    AIRKISS_LAN_SSDP_RESP_CMD = 0x1001,
+    AIRKISS_LAN_SSDP_NOTIFY_CMD = 0x1002
+} airkiss_lan_cmdid_t;
+int airkiss_lan_recv(const void* body, unsigned short length, const airkiss_config_t* config);
+int airkiss_lan_pack(airkiss_lan_cmdid_t ak_lan_cmdid, void* appid, void* deviceid, void* _datain, unsigned short inlength, void* _dataout, unsigned short* outlength, const airkiss_config_t* config);
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smartlink/airkiss-lib/x64/airkiss.h b/drivers/net/wireless/ssv6x5x/smartlink/airkiss-lib/x64/airkiss.h
new file mode 100644
index 000000000..f71177645
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smartlink/airkiss-lib/x64/airkiss.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef AIRKISS_H_
+#define AIRKISS_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+#ifndef AIRKISS_ENABLE_CRYPT
+#define AIRKISS_ENABLE_CRYPT 1
+#endif
+typedef void* (*airkiss_memset_fn) (void* ptr, int value, unsigned int num);
+typedef void* (*airkiss_memcpy_fn) (void* dst, const void* src, unsigned int num);
+typedef int (*airkiss_memcmp_fn) (const void* ptr1, const void* ptr2, unsigned int num);
+typedef int (*airkiss_printf_fn) (const char* format, ...);
+typedef struct {
+    airkiss_memset_fn memset;
+    airkiss_memcpy_fn memcpy;
+    airkiss_memcmp_fn memcmp;
+    airkiss_printf_fn printf;
+} airkiss_config_t;
+typedef struct {
+    int dummyap[26];
+    int dummy[32];
+} airkiss_context_t;
+typedef struct {
+    char* pwd;
+    char* ssid;
+    unsigned char pwd_length;
+    unsigned char ssid_length;
+    unsigned char random;
+    unsigned char reserved;
+} airkiss_result_t;
+typedef enum {
+    AIRKISS_STATUS_CONTINUE = 0,
+    AIRKISS_STATUS_CHANNEL_LOCKED = 1,
+    AIRKISS_STATUS_COMPLETE = 2
+} airkiss_status_t;
+#if AIRKISS_ENABLE_CRYPT
+int airkiss_set_key(airkiss_context_t* context, const unsigned char* key, unsigned int length);
+#endif
+const char* airkiss_version(void);
+int airkiss_init(airkiss_context_t* context, const airkiss_config_t* config);
+int airkiss_recv(airkiss_context_t* context, const void* frame, unsigned short length);
+int airkiss_get_result(airkiss_context_t* context, airkiss_result_t* result);
+int airkiss_change_channel(airkiss_context_t* context);
+typedef enum {
+    AIRKISS_LAN_ERR_OVERFLOW = -5,
+    AIRKISS_LAN_ERR_CMD = -4,
+    AIRKISS_LAN_ERR_PAKE = -3,
+    AIRKISS_LAN_ERR_PARA = -2,
+    AIRKISS_LAN_ERR_PKG = -1,
+    AIRKISS_LAN_CONTINUE = 0,
+    AIRKISS_LAN_SSDP_REQ = 1,
+    AIRKISS_LAN_PAKE_READY = 2
+} airkiss_lan_ret_t;
+typedef enum {
+    AIRKISS_LAN_SSDP_REQ_CMD = 0x1,
+    AIRKISS_LAN_SSDP_RESP_CMD = 0x1001,
+    AIRKISS_LAN_SSDP_NOTIFY_CMD = 0x1002
+} airkiss_lan_cmdid_t;
+int airkiss_lan_recv(const void* body, unsigned short length, const airkiss_config_t* config);
+int airkiss_lan_pack(airkiss_lan_cmdid_t ak_lan_cmdid, void* appid, void* deviceid, void* _datain, unsigned short inlength, void* _dataout, unsigned short* outlength, const airkiss_config_t* config);
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smartlink/airkiss-lib/x64/readme b/drivers/net/wireless/ssv6x5x/smartlink/airkiss-lib/x64/readme
new file mode 100755
index 000000000..02013b739
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smartlink/airkiss-lib/x64/readme
@@ -0,0 +1 @@
+airkiss_linux_x64_2.0.0.25360
diff --git a/drivers/net/wireless/ssv6x5x/smartlink/airkiss.c b/drivers/net/wireless/ssv6x5x/smartlink/airkiss.c
new file mode 100644
index 000000000..5415ecd83
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smartlink/airkiss.c
@@ -0,0 +1,219 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <stdint.h>
+#include <string.h>
+#include <sys/socket.h>
+#include <sys/errno.h>
+#include <sys/time.h>
+#include <signal.h>
+#include <linux/netlink.h>
+#include "ssv_smartlink.h"
+#include "airkiss-lib/airkiss.h"
+airkiss_context_t akcontex;
+const airkiss_config_t akconf = {
+    (airkiss_memset_fn)&memset,
+    (airkiss_memcpy_fn)&memcpy,
+    (airkiss_memcmp_fn)&memcmp,
+    (airkiss_printf_fn)&printf
+};
+static uint8_t gBuf[MAX_PAYLOAD]= {0};
+static uint32_t gBufLen=0;
+static airkiss_result_t ssv_airkiss_result;
+static char *ssv_wpa_conf_file = "%s/conf/wpa_supplicant.conf";
+static char *ssv_enter_airkiss_mode = "cd %s/scripts/ && ./startsmartlink.sh";
+static char *ssv_start_sta_mode = "cd %s/         && ./sta.sh";
+static uint32_t gChan=SSV_MIN_CHANNEL;
+static void _ssv_airkiss_finish(void)
+{
+    int ret=0;
+    ret = airkiss_get_result(&akcontex, &ssv_airkiss_result);
+    if (ret == 0) {
+        printf("airkiss_get_result() ok!\n");
+        printf("ssid = %s, pwd = %s, ssid_length = %d, pwd_length = %d, random = 0x%02x\n",
+               ssv_airkiss_result.ssid,
+               ssv_airkiss_result.pwd,
+               ssv_airkiss_result.ssid_length,
+               ssv_airkiss_result.pwd_length,
+               ssv_airkiss_result.random);
+    } else {
+        printf("airkiss_get_result() failed!\n");
+    }
+}
+static void _ssv_airkiss_setchannel_callback(int signum)
+{
+    (void)signum;
+    ssv_smartlink_set_channel(gChan);
+    gChan++;
+    if (gChan > SSV_MAX_CHANNEL) {
+        gChan = SSV_MIN_CHANNEL;
+    }
+}
+static int _ssv_airkiss_enable_setchannel_timer(void)
+{
+    struct itimerval t;
+    t.it_interval.tv_usec = 200000;
+    t.it_interval.tv_sec = 0;
+    t.it_value.tv_usec = 200000;
+    t.it_value.tv_sec = 0;
+    if (setitimer(ITIMER_REAL, &t, NULL) < 0) {
+        printf("%s\n", strerror(errno));
+        printf("setitimer error!\n");
+        return -1;
+    }
+    signal(SIGALRM, _ssv_airkiss_setchannel_callback);
+    return 0;
+}
+static int _ssv_airkiss_disable_setchannel_timer(void)
+{
+    struct itimerval t;
+    getitimer(ITIMER_REAL, &t );
+    t.it_interval.tv_usec = 0;
+    t.it_interval.tv_sec = 0;
+    t.it_value.tv_usec = 0;
+    t.it_value.tv_sec = 0;
+    if (setitimer(ITIMER_REAL, &t, NULL) < 0) {
+        printf("%s\n", strerror(errno));
+        printf("setitimer error!\n");
+        return -1;
+    }
+    return 0;
+}
+static void _ssv_sig_int(int signum)
+{
+    (void)ssv_smartlink_stop();
+    return;
+}
+static int _ssv_airkiss_write_wpa_config_file(char *pFileName, char *pSSID, char *pPWD)
+{
+    FILE *fptr=NULL;
+    if (!pFileName || !pSSID || !pPWD) {
+        printf("Parameter error!\n");
+        return -1;
+    }
+    fptr = fopen(pFileName, "w");
+    if (fptr == NULL) {
+        printf("Open %s failed: %s\n", pFileName, strerror(errno));
+        return -2;
+    }
+    fprintf(fptr, "ctrl_interface=/var/run/wpa_supplicant\n");
+    fprintf(fptr, "ap_scan=1\n");
+    fprintf(fptr, "\n");
+    fprintf(fptr, "network={\n");
+    fprintf(fptr, "\tssid=\"%s\"\n", pSSID);
+    fprintf(fptr, "\tpsk=\"%s\"\n", pPWD);
+    fprintf(fptr, "}\n");
+    fclose(fptr);
+    printf("Write %s success.\n", pFileName);
+    return 0;
+}
+int main(int argc, char *argv[])
+{
+    int ret=-1;
+    const char *key="Wechatiothardwav";
+    char cmdBuf[160]= {0};
+#if 0
+    file_path_getcwd = (char *)malloc(80);
+    getcwd(file_path_getcwd, 80);
+    printf("==Current Path: %s==\n", file_path_getcwd);
+    sprintf(cmdBuf, ssv_enter_airkiss_mode, file_path_getcwd);
+    ret = system(cmdBuf);
+    if (ret != 0) {
+        if (file_path_getcwd) {
+            free(file_path_getcwd);
+        }
+        return ret;
+    }
+#endif
+    ret = airkiss_init(&akcontex, &akconf);
+    if (ret < 0) {
+        printf("airkiss init failed\n");
+        goto out;
+    }
+    printf("%s\n", airkiss_version());
+#if AIRKISS_ENABLE_CRYPT
+    airkiss_set_key(&akcontex, key, strlen(key));
+#endif
+    printf("%s\n", ssv_smartlink_version());
+    ret = ssv_smartlink_start();
+    if (ret < 0) {
+        printf("ssv_smartlink_start error: %d\n", ret);
+        goto out;
+    }
+    ret = ssv_smartlink_set_promisc(1);
+    if (ret < 0) {
+        printf("ssv_smartlink_set_promisc error: %d\n", ret);
+        goto out;
+    }
+    ret = _ssv_airkiss_enable_setchannel_timer();
+    if (ret < 0) {
+        goto out;
+    }
+    signal(SIGINT, _ssv_sig_int);
+    while (1) {
+        gBufLen = 0;
+        memset(gBuf, 0, sizeof(gBuf));
+        ret = ssv_smartlink_recv_packet(gBuf, &gBufLen);
+        if (ret < 0) {
+            printf("ssv_smartlink_recv_packet error: %d\n", ret);
+            goto out;
+        }
+        ret = airkiss_recv(&akcontex, gBuf, gBufLen);
+        if (ret == AIRKISS_STATUS_CHANNEL_LOCKED) {
+            ret = _ssv_airkiss_disable_setchannel_timer();
+            if (ret < 0) {
+                goto out;
+            }
+            gChan = gChan - 1;
+            if (gChan < SSV_MIN_CHANNEL) {
+                gChan = SSV_MIN_CHANNEL;
+            }
+            printf("Channel locked to %d!\n", gChan);
+        } else if (ret == AIRKISS_STATUS_COMPLETE) {
+            _ssv_airkiss_finish();
+            ret = ssv_smartlink_set_promisc(0);
+            if (ret < 0) {
+                goto out;
+            }
+            break;
+        } else {
+        }
+    }
+    ret = 0;
+out:
+    (void)ssv_smartlink_stop();
+#if 0
+    if (ret == 0) {
+        sprintf(cmdBuf, ssv_wpa_conf_file, file_path_getcwd);
+        if (0 == _ssv_airkiss_write_wpa_config_file(cmdBuf, ssv_airkiss_result.ssid, ssv_airkiss_result.pwd)) {
+            char buf[64];
+            printf("Config file: %s\n", cmdBuf);
+            printf("----------------------------------------\n");
+            sprintf(buf, "cat %s", cmdBuf);
+            system(buf);
+            printf("----------------------------------------\n");
+            sprintf(cmdBuf, ssv_start_sta_mode, file_path_getcwd);
+            system(cmdBuf);
+        }
+    }
+    if (file_path_getcwd) {
+        free(file_path_getcwd);
+    }
+#endif
+    return ret;
+}
diff --git a/drivers/net/wireless/ssv6x5x/smartlink/package.sh b/drivers/net/wireless/ssv6x5x/smartlink/package.sh
new file mode 100755
index 000000000..2f1049d53
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smartlink/package.sh
@@ -0,0 +1,9 @@
+#!/bin/sh
+
+tarfile=ssv_smartlink.tar.gz
+
+tar czvf $tarfile airkiss airkiss.c qqlink qqlink.c ssv_smartlink.c ssv_smartlink.h libssv_smartlink-mipsel.a ssv_smartlink.h Makefile.airkiss Makefile.qqlink Makefile.smarticomm tencent/ Tencent_iot_SDK/ --exclude=".svn" 
+
+echo "======================================="
+ls -l $tarfile
+echo "======================================="
diff --git a/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/News.txt b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/News.txt
new file mode 100755
index 000000000..2e9c4c1e0
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/News.txt
@@ -0,0 +1,27 @@
+SDK 1.2
+==============================================
+新增 跨网注册绑定功能，对局域网注册方式的补充和完善，提高了注册绑定的成功率。
+新增 声波配网功能，和smartlink组合使用，提升配网成功率。
+新增 去掉openssl依赖，我们sdk自己裁剪了openssl的功能，对外不再依赖openssl动态库，体积只有小幅增加。极大缓解设备空间小的问题。
+新增 消息增加了生命期，优化了server消息缓存利用率。
+新增 大数据通道，最大支持25M的数据传送量。
+新增 datapoint接口优化，简化接口的复杂度，方便大家使用。
+
+
+
+
+SDK 1.1
+==============================================
+新增 设备群聊功能，设备和设备所有的共享者构成群，可以像群一下，消息所有人可见。
+新增 升级能力，手Q发送信令到设备，设备下载升级包后，升级固件或程序。
+
+
+
+SDK 1.0
+==============================================
+新增 音视频功能，手机QQ可以向设备发起1v1的音视频通话。
+新增 smartlink能力，手机QQ可以同步路由器的wifi和密码给设备，解决无输入设备联网的问题。
+新增 传文件功能，可以实现像 摄像头报警，视频/语音留言等功能。
+新增 通用可配置控制信令发送能力, 可以实现烟雾传感器报警，云台控制，温度计温度数据传送等功能。
+
+
diff --git a/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/ReadMe.txt b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/ReadMe.txt
new file mode 100755
index 000000000..519fe06e7
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/ReadMe.txt
@@ -0,0 +1,7 @@
+腾讯 QQ 物联设备SDK能够嵌入到arm-linux平台、mips-linux平台和RTOS平台，提供音视频能力，消息能力和控制信令能力。将设备注册到QQ平台后，QQ用户就能够用手机和设备进行音视频通话，发送消息和触发控制信令等。
+
+更多信息可以访问 QQ物联资料库 网址：
+http://iot.open.qq.com/wiki/index.html#!CASE/IP_Camera.md
+
+SDK 下载页面网址：
+http://iot.open.qq.com/wiki/index.html#!SDK/Linux.md
diff --git a/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/case/ipcamera/Makefile b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/case/ipcamera/Makefile
new file mode 100755
index 000000000..10bca9091
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/case/ipcamera/Makefile
@@ -0,0 +1,35 @@
+# replace with your target cross-compile toolchains.
+# default for host compiler.
+#
+
+# running:
+#     shell>export LD_LIBRARY_PATH=../../lib
+#	  shell>./ipcamera_demo
+
+# you will got this message "[error]get license from file failed..."
+# fix this:
+#      step 1: access http://iot.open.qq.com/wiki/index.html#CASE/IP_Camera.md 
+#      
+#      step 2: replace "pid" which is a product id number in main.c 
+#              copy sn file, licence file and server public key file (file name like "pid".pem) to ./
+#
+#	   step 3: > make
+
+CC:=gcc
+
+C_FLAGS:=-O0 -g3  -m32 -std=c99
+
+C_FILES:=\
+	alarm.c \
+	audiofile.c \
+	audiovideo.c \
+	ipcrotate.c \
+	main.c \
+	ota.c
+
+
+all: 
+	$(CC) $(C_FLAGS) $(C_FILES) -o ipcamera_demo -I../../include -L../../lib -ltxdevicesdk -lpthread -ldl
+
+clean:
+	rm ipcamra_demo
\ No newline at end of file
diff --git a/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/case/ipcamera/alarm.c b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/case/ipcamera/alarm.c
new file mode 100644
index 000000000..32d091469
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/case/ipcamera/alarm.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include "TXSDKCommonDef.h"
+#include "TXDeviceSDK.h"
+#include "TXMsg.h"
+void on_send_alarm_file_progress(const unsigned int cookie, unsigned long long transfer_progress, unsigned long long max_transfer_progress)
+{
+    printf("on_send_alarm_file_progress, cookie[%u]\n", cookie);
+}
+void on_send_alarm_msg_ret(const unsigned int cookie, int err_code)
+{
+    printf("on_send_alarm_msg_ret, cookie[%u] ret[%d]\n", cookie, err_code);
+}
+void test_send_pic_alarm()
+{
+    structuring_msg msg = {0};
+    msg.msg_id = 1;
+    msg.file_path = "./alarm.png";
+    msg.thumb_path = "./thumb.png";
+    msg.title = "发现异常";
+    msg.digest = "客厅发现异常";
+    msg.guide_words = "点击查看";
+    tx_send_msg_notify notify = {0};
+    notify.on_file_transfer_progress = on_send_alarm_file_progress;
+    notify.on_send_structuring_msg_ret = on_send_alarm_msg_ret;
+    tx_send_structuring_msg(&msg, &notify, 0);
+}
+void test_send_audio_alarm()
+{
+    structuring_msg msg = {0};
+    msg.msg_id = 2;
+    msg.file_path = "./test.mp3";
+    msg.title = "语音报警";
+    msg.digest = "收到语音报警";
+    msg.guide_words = "点击查看";
+    tx_send_msg_notify notify = {0};
+    notify.on_file_transfer_progress = on_send_alarm_file_progress;
+    notify.on_send_structuring_msg_ret = on_send_alarm_msg_ret;
+    tx_send_structuring_msg(&msg, &notify, 0);
+}
diff --git a/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/case/ipcamera/audiofile.c b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/case/ipcamera/audiofile.c
new file mode 100644
index 000000000..10eef5864
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/case/ipcamera/audiofile.c
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include "TXSDKCommonDef.h"
+#include "TXDeviceSDK.h"
+#include "TXFileTransfer.h"
+void cb_on_transfer_progress(unsigned long long transfer_cookie, unsigned long long transfer_progress, unsigned long long max_transfer_progress)
+{
+    printf("========> on file progress %f%%\n", transfer_progress * 100.0 / max_transfer_progress);
+}
+void cb_on_recv_file(unsigned long long transfer_cookie, const tx_ccmsg_inst_info * inst_info, const tx_file_transfer_info * tran_info)
+{
+}
+void cb_on_transfer_complete(unsigned long long transfer_cookie, int err_code, tx_file_transfer_info* tran_info)
+{
+    printf("================ontransfer complete=====transfer_cookie == %lld ====================\n", transfer_cookie);
+    printf("errcode %d, bussiness_name [%s], file path [%s]\n", err_code, tran_info->bussiness_name, tran_info->file_path);
+    printf("===============================================================================\n");
+    if(err_code == 0) {
+        if(strcmp(tran_info->bussiness_name, BUSINESS_NAME_AUDIO_MSG) == 0) {
+        } else {
+        }
+    }
+}
diff --git a/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/case/ipcamera/audiovideo.c b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/case/ipcamera/audiovideo.c
new file mode 100644
index 000000000..53841d808
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/case/ipcamera/audiovideo.c
@@ -0,0 +1,135 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include <pthread.h>
+#include <sys/time.h>
+#include "TXSDKCommonDef.h"
+#include "TXAudioVideo.h"
+static FILE *fstream = NULL;
+static char* s_cData = NULL;
+static bool s_bstart = false;
+static pthread_t thread_enc_id = 0;
+static unsigned long s_dwTotalFrameIndex = 0;
+unsigned long _GetTickCount()
+{
+    struct timeval current = {0};
+    gettimeofday(&current, NULL);
+    return (current.tv_sec*1000 + current.tv_usec/1000);
+}
+static void* EncoderThread(void* pThreadData)
+{
+    while(s_bstart) {
+        if(s_bstart) {
+            if(fstream &&!feof(fstream)) {
+                int iLen = 0;
+                int iType = -1;
+                fread(&iLen, 1, 4, fstream);
+                fread(&iType, 1, 4, fstream);
+                if (iLen > 0) {
+                    fread(s_cData, 1, iLen, fstream);
+                    static int s_nFrameIndex = 0;
+                    static int s_gopIndex = -1;
+                    unsigned char * pcEncData = (unsigned char *)s_cData;
+                    int nEncDataLen = iLen;
+                    int nFrameType = 1;
+                    if(iType == 0) {
+                        s_nFrameIndex = 0;
+                        s_gopIndex++;
+                        nFrameType = 0;
+                    } else {
+                        s_nFrameIndex++;
+                        nFrameType = 1;
+                    }
+                    if(s_gopIndex == -1) {
+                        printf("No I Frame s_gopIndex == -1\n");
+                    } else {
+                        if(nEncDataLen != 0) {
+                            tx_set_video_data(pcEncData, nEncDataLen, nFrameType, (int)_GetTickCount(), s_gopIndex, s_nFrameIndex, (int)s_dwTotalFrameIndex++, 40);
+                        }
+                    }
+                }
+            } else if(fstream && feof(fstream)) {
+                fclose(fstream);
+                fstream = fopen("test.264", "rb");
+            }
+        }
+        usleep(90000);
+    }
+    return 0;
+}
+bool test_start_camera()
+{
+    printf("###### test_start_camera ###################################### \n");
+    if (!fstream) {
+        fstream = fopen("test.264", "rb");
+    }
+    if (!s_cData) {
+        s_cData = (char*)malloc(1280*720);
+    }
+    if (!fstream || !s_cData) {
+        return false;
+    }
+    s_bstart = true;
+    int ret = pthread_create(&thread_enc_id, NULL, EncoderThread, NULL);
+    if (ret || !thread_enc_id) {
+        s_bstart = false;
+        return false;
+    }
+    return true;
+}
+bool test_stop_camera()
+{
+    printf("###### test_stop_camera ###################################### \n");
+    s_bstart = false;
+    if(fstream) {
+        fclose(fstream);
+        fstream = NULL;
+    }
+    if(s_cData) {
+        free(s_cData);
+        s_cData = NULL;
+    }
+    if(thread_enc_id !=0) {
+        pthread_join(thread_enc_id,NULL);
+        thread_enc_id = 0;
+    }
+    return true;
+}
+bool test_set_bitrate(int bit_rate)
+{
+    printf("###### test_set_bitrate  ##################################### %d \n", bit_rate);
+    return true;
+}
+bool test_restart_gop()
+{
+    printf("###### test_restart_gop ###################################### \n");
+    return true;
+}
+bool test_start_mic()
+{
+    printf("###### test_start_mic ###################################### \n");
+    return true;
+}
+bool test_stop_mic()
+{
+    printf("###### test_stop_mic ######################################\n");
+    return true;
+}
+void test_recv_audiodata(tx_audio_encode_param *param, unsigned char *pcEncData, int nEncDataLen)
+{
+    printf("##### test_recv_audiodata ######################################\n");
+}
diff --git a/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/case/ipcamera/build_darwin64.sh b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/case/ipcamera/build_darwin64.sh
new file mode 100755
index 000000000..ee8e45524
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/case/ipcamera/build_darwin64.sh
@@ -0,0 +1,14 @@
+test -e libtxdevicesdk.so && rm libtxdevicesdk.so
+test -e ipcdemo && rm ipcdemo
+
+test -e libcrypto.1.0.0.dylib && rm libcrypto.1.0.0.dylib
+test -e libcrypto.dylib && rm libcrypto.dylib
+test -e libssl.1.0.0.dylib && rm libssl.1.0.0.dylib
+test -e libssl.dylib && rm libssl.dylib
+
+
+make -C ../../txdevicesdk/build PLATFORM=darwin64
+
+gcc './alarm.c' './audiofile.c' './audiovideo.c' './ota.c' 'ipcrotate.c' './main.c' -o ipcdemo -I'../../txdevicesdk/sdkimpl/include' -L'../../txdevicesdk/build/darwin64/lib' -O0 -g3 -ltxdevicesdk -lpthread -ldl -m64 -std=c99
+
+cp ../../txdevicesdk/third_part/openssl-osx/lib/libcrypto.1.0.0.dylib ../../txdevicesdk/third_part/openssl-osx/lib/libcrypto.dylib ../../txdevicesdk/third_part/openssl-osx/lib/libssl.1.0.0.dylib ../../txdevicesdk/third_part/openssl-osx/lib/libssl.dylib ./
\ No newline at end of file
diff --git a/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/case/ipcamera/build_x86.sh b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/case/ipcamera/build_x86.sh
new file mode 100755
index 000000000..e58b74c40
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/case/ipcamera/build_x86.sh
@@ -0,0 +1,14 @@
+test -e libtxdevicesdk.so && rm libtxdevicesdk.so
+test -e ipcdemo && rm ipcdemo
+
+test -e libcrypto.so.1.0.0 && rm libcrypto.so.1.0.0
+test -e libcrypto.so && rm libcrypto.so
+test -e libssl.so.1.0.0 && rm libssl.so.1.0.0
+test -e libssl.so && rm libssl.so
+
+
+make -C ../../txdevicesdk/build PLATFORM=x86
+
+gcc './alarm.c' './audiofile.c' './audiovideo.c' './ota.c' 'ipcrotate.c' './main.c' -o ipcdemo -I'../../txdevicesdk/sdkimpl/include' -L'../../txdevicesdk/build/x86/lib' -O0 -g3 -ltxdevicesdk -lpthread -ldl -m32 -std=c99
+
+cp ../../txdevicesdk/third_part/openssl/lib/libcrypto.so.1.0.0 ../../txdevicesdk/third_part/openssl/lib/libcrypto.so ../../txdevicesdk/third_part/openssl/lib/libssl.so.1.0.0 ../../txdevicesdk/third_part/openssl/lib/libssl.so ./
diff --git a/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/case/ipcamera/ipcrotate.c b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/case/ipcamera/ipcrotate.c
new file mode 100644
index 000000000..aa13b7740
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/case/ipcamera/ipcrotate.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <stdio.h>
+#include <string.h>
+int cb_on_set_definition(int definition, char *cur_definition, int cur_definition_length)
+{
+    printf("==============cb_on_set_definition, definition:%d\n", definition);
+    return 0;
+}
+int cb_on_control_rotate(int rotate_direction, int rotate_degree)
+{
+    printf("===============cb_on_control_rotate, rotate_direction:%d, rotate_degree:%d\n", rotate_direction, rotate_degree);
+    return 0;
+}
diff --git a/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/case/ipcamera/main.c b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/case/ipcamera/main.c
new file mode 100644
index 000000000..8fd677a44
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/case/ipcamera/main.c
@@ -0,0 +1,187 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include "TXSDKCommonDef.h"
+#include "TXDeviceSDK.h"
+#include "TXOTA.h"
+#include "TXFileTransfer.h"
+#include "TXIPCAM.h"
+extern bool test_start_camera();
+extern bool test_stop_camera();
+extern bool test_set_bitrate(int bit_rate);
+extern void test_recv_audiodata(tx_audio_encode_param *param, unsigned char *pcEncData, int nEncDataLen);
+extern bool test_start_mic();
+extern bool test_stop_mic();
+extern void cb_on_transfer_progress(unsigned long long transfer_cookie, unsigned long long transfer_progress, unsigned long long max_transfer_progress);
+extern void cb_on_recv_file(unsigned long long transfer_cookie, const tx_ccmsg_inst_info * inst_info, const tx_file_transfer_info * tran_info);
+extern void cb_on_transfer_complete(unsigned long long transfer_cookie, int err_code, tx_file_transfer_info* tran_info);
+extern void test_send_pic_alarm();
+extern void test_send_audio_alarm();
+extern int cb_on_new_pkg_come(unsigned long long from, unsigned long long pkg_size, const char * title, const char * desc, unsigned int target_version);
+extern void cb_on_download_progress(unsigned long long download_size, unsigned long long total_size);
+extern void cb_on_download_complete(int ret_code);
+extern void cb_on_update_confirm();
+extern int cb_on_set_definition(int definition, char *cur_definition, int cur_definition_length);
+extern int cb_on_control_rotate(int rotate_direction, int rotate_degree);
+static bool g_start_av_service = false;
+void on_login_complete(int errcode)
+{
+    printf("on_login_complete | code[%d]\n", errcode);
+}
+void on_online_status(int old, int new)
+{
+    printf("online status: %s\n", 11 == new ? "true" : "false");
+    if(11 == new && !g_start_av_service) {
+        tx_av_callback avcallback = {0};
+        avcallback.on_start_camera = test_start_camera;
+        avcallback.on_stop_camera = test_stop_camera;
+        avcallback.on_set_bitrate = test_set_bitrate;
+        avcallback.on_recv_audiodata = test_recv_audiodata;
+        avcallback.on_start_mic = test_start_mic;
+        avcallback.on_stop_mic = test_stop_mic;
+        int ret = tx_start_av_service(&avcallback);
+        if (err_null == ret) {
+            printf(" >>> tx_start_av_service successed\n");
+        } else {
+            printf(" >>> tx_start_av_service failed [%d]\n", ret);
+        }
+        g_start_av_service = true;
+    }
+}
+void on_binder_list_change(int error_code, tx_binder_info * pBinderList, int nCount)
+{
+    if (err_null != error_code) {
+        printf("on_binder_list_change failed, errcode:%d\n", error_code);
+        return;
+    }
+    printf("on_binder_list_change, %d binder: \n", nCount);
+    int i = 0;
+    for (i = 0; i < nCount; ++i ) {
+        printf("binder uin[%llu], nick_name[%s]\n", pBinderList[i].uin, pBinderList[i].nick_name);
+    }
+}
+bool readBufferFromFile(char *pPath, unsigned char *pBuffer, int nInSize, int *pSizeUsed)
+{
+    if (!pPath || !pBuffer) {
+        return false;
+    }
+    int uLen = 0;
+    FILE * file = fopen(pPath, "rb");
+    if (!file) {
+        return false;
+    }
+    fseek(file, 0L, SEEK_END);
+    uLen = ftell(file);
+    fseek(file, 0L, SEEK_SET);
+    if (0 == uLen || nInSize < uLen) {
+        printf("invalide file or buffer size is too small...\n");
+        return false;
+    }
+    *pSizeUsed = fread(pBuffer, 1, uLen, file);
+    fclose(file);
+    return true;
+}
+void log_func(int level, const char* module, int line, const char* message)
+{
+    printf("%s\n", message);
+}
+bool initDevice()
+{
+    unsigned char license[256] = {0};
+    int nLicenseSize = 0;
+    if (!readBufferFromFile("./licence.sign.file.txt", license, sizeof(license), &nLicenseSize)) {
+        printf("[error]get license from file failed...\n");
+        return false;
+    }
+    unsigned char guid[32] = {0};
+    int nGUIDSize = 0;
+    if(!readBufferFromFile("./GUID_file.txt", guid, sizeof(guid), &nGUIDSize)) {
+        printf("[error]get guid from file failed...\n");
+        return false;
+    }
+    unsigned char svrPubkey[256] = {0};
+    int nPubkeySize = 0;
+    if (!readBufferFromFile("./1700001460.pem", svrPubkey, sizeof(svrPubkey), &nPubkeySize)) {
+        printf("[error]get svrPubkey from file failed...\n");
+        return NULL;
+    }
+    tx_device_info info = {0};
+    info.os_platform = "Linux";
+    info.device_name = "demo1";
+    info.device_serial_number = (char*)guid;
+    info.device_license = (char*)license;
+    info.product_version = 1;
+    info.network_type = network_type_wifi;
+    info.product_id = 1700001460;
+    info.server_pub_key = svrPubkey;
+    tx_device_notify notify = {0};
+    notify.on_login_complete = on_login_complete;
+    notify.on_online_status = on_online_status;
+    notify.on_binder_list_change = on_binder_list_change;
+    tx_init_path init_path = {0};
+    init_path.system_path = "./";
+    init_path.system_path_capicity = 100 * 1024;
+    init_path.app_path = "./";
+    init_path.app_path_capicity = 1024 * 1024;
+    init_path.temp_path = "./";
+    init_path.temp_path_capicity = 10 * 1024;
+    tx_set_log_func(log_func);
+    int ret = tx_init_device(&info, &notify, &init_path);
+    if (err_null != ret) {
+        printf(" >>> tx_init_device failed [%d]\n", ret);
+        return false;
+    }
+    printf(" >>> tx_init_device success\n");
+    tx_ipcamera_notify ipcamera_notify = {0};
+    ipcamera_notify.on_control_rotate = cb_on_control_rotate;
+    ipcamera_notify.on_set_definition = cb_on_set_definition;
+    tx_ipcamera_set_callback(&ipcamera_notify);
+    tx_file_transfer_notify fileTransferNotify = {0};
+    fileTransferNotify.on_transfer_complete = cb_on_transfer_complete;
+    fileTransferNotify.on_transfer_progress = cb_on_transfer_progress;
+    fileTransferNotify.on_file_in_come = cb_on_recv_file;
+    tx_init_file_transfer(fileTransferNotify, "/tmp/ramdisk/");
+    tx_ota_notify ota_notify = {0};
+    ota_notify.on_new_pkg_come = cb_on_new_pkg_come;
+    ota_notify.on_download_progress = cb_on_download_progress;
+    ota_notify.on_download_complete = cb_on_download_complete;
+    ota_notify.on_update_confirm = cb_on_update_confirm;
+    tx_init_ota(&ota_notify, 10*60, "/tmp/update_pkg.tar");
+    return true;
+}
+int main(int argc, char* argv[])
+{
+    if ( !initDevice() ) {
+        return -1;
+    }
+    char input[100];
+    while (scanf("%s", input)) {
+        if ( !strcmp(input, "quit") ) {
+            if (g_start_av_service) {
+                tx_stop_av_service();
+            }
+            tx_exit_device();
+            break;
+        } else if ( !strcmp(input, "sendpicalarm") ) {
+            test_send_pic_alarm();
+        } else if ( !strcmp(input, "sendaudioalarm") ) {
+            test_send_audio_alarm();
+        }
+        sleep(1);
+    }
+    return 0;
+}
diff --git a/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/case/ipcamera/ota.c b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/case/ipcamera/ota.c
new file mode 100644
index 000000000..fc0bab395
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/case/ipcamera/ota.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include "TXSDKCommonDef.h"
+#include "TXDeviceSDK.h"
+#include "TXFileTransfer.h"
+int cb_on_new_pkg_come(unsigned long long from, unsigned long long pkg_size, const char * title, const char * desc, unsigned int target_version)
+{
+    return 0;
+}
+void cb_on_download_progress(unsigned long long download_size, unsigned long long total_size)
+{
+}
+void cb_on_download_complete(int ret_code)
+{
+}
+void cb_on_update_confirm()
+{
+}
diff --git a/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/case/ipcamera/test.264 b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/case/ipcamera/test.264
new file mode 100755
index 000000000..e69de29bb
diff --git a/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/demo_bind.c b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/demo_bind.c
new file mode 100644
index 000000000..aab06c909
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/demo_bind.c
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include "TXSDKCommonDef.h"
+#include "TXDeviceSDK.h"
+void on_login_complete(int errcode)
+{
+    printf("on_login_complete | code[%d]\n", errcode);
+}
+void on_online_status(int old, int new)
+{
+    printf("online status: %s\n", 11 == new ? "true" : "false");
+}
+bool readBufferFromFile(char *pPath, unsigned char *pBuffer, int nInSize, int *pSizeUsed)
+{
+    if (!pPath || !pBuffer) {
+        return false;
+    }
+    int uLen = 0;
+    FILE * file = fopen(pPath, "rb");
+    if (!file) {
+        return false;
+    }
+    fseek(file, 0L, SEEK_END);
+    uLen = ftell(file);
+    fseek(file, 0L, SEEK_SET);
+    if (0 == uLen || nInSize < uLen) {
+        printf("invalide file or buffer size is too small...\n");
+        return false;
+    }
+    *pSizeUsed = fread(pBuffer, 1, uLen, file);
+    if (pBuffer[uLen-1] == 0x0a) {
+        *pSizeUsed = uLen - 1;
+        pBuffer[uLen-1] = '\0';
+    }
+    printf("len:%d, ulen:%d\n",uLen, *pSizeUsed);
+    fclose(file);
+    return true;
+}
+void log_func(int level, const char* module, int line, const char* message)
+{
+    printf("%s\n", message);
+}
+bool initDevice()
+{
+    unsigned char license[256] = {0};
+    int nLicenseSize = 0;
+    if (!readBufferFromFile("./licence.sign.file.txt", license, sizeof(license), &nLicenseSize)) {
+        printf("[error]get license from file failed...\n");
+        return false;
+    }
+    unsigned char guid[32] = {0};
+    int nGUIDSize = 0;
+    if(!readBufferFromFile("./GUID_file.txt", guid, sizeof(guid), &nGUIDSize)) {
+        printf("[error]get guid from file failed...\n");
+        return false;
+    }
+    char svrPubkey[256] = {0};
+    int nPubkeySize = 0;
+    if (!readBufferFromFile("./1000000004.pem", svrPubkey, sizeof(svrPubkey), &nPubkeySize)) {
+        printf("[error]get svrPubkey from file failed...\n");
+        return NULL;
+    }
+    tx_device_info info = {0};
+    info.os_platform = "Linux";
+    info.device_name = "demo1";
+    info.device_serial_number = guid;
+    info.device_license = license;
+    info.product_version = 1;
+    info.network_type = network_type_wifi;
+    info.product_id = 1000000004;
+    info.server_pub_key = svrPubkey;
+    tx_device_notify notify = {0};
+    notify.on_login_complete = on_login_complete;
+    notify.on_online_status = on_online_status;
+    notify.on_binder_list_change = NULL;
+    tx_init_path init_path = {0};
+    init_path.system_path = "./";
+    init_path.system_path_capicity = 100 * 1024;
+    init_path.app_path = "./";
+    init_path.app_path_capicity = 1024 * 1024;
+    init_path.temp_path = "./";
+    init_path.temp_path_capicity = 10 * 1024;
+    tx_set_log_func(log_func);
+    int ret = tx_init_device(&info, &notify, &init_path);
+    if (err_null == ret) {
+        printf(" >>> tx_init_device success\n");
+    } else {
+        printf(" >>> tx_init_device failed [%d]\n", ret);
+        return false;
+    }
+    return true;
+}
+int main(int argc, char* argv[])
+{
+    if ( !initDevice() ) {
+        return -1;
+    }
+    char input[100];
+    while (scanf("%s", input)) {
+        if ( !strcmp(input, "quit") ) {
+            tx_exit_device();
+            break;
+        }
+        sleep(1);
+    }
+    return 0;
+}
diff --git a/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/demo_filetransfer.c b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/demo_filetransfer.c
new file mode 100644
index 000000000..9da04f9db
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/demo_filetransfer.c
@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include "TXSDKCommonDef.h"
+#include "TXDeviceSDK.h"
+void on_login_complete(int errcode)
+{
+    printf("on_login_complete | code[%d]\n", errcode);
+}
+void on_online_status(int old, int new)
+{
+    printf("online status: %s\n", 11 == new ? "true" : "false");
+}
+void ontransfercomplete(unsigned long long transfer_cookie, int err_code, tx_file_transfer_info tran_info)
+{
+    printf("================ontransfer complete=====transfer_cookie == %lld ====================\n", transfer_cookie);
+    printf("errcode %d, bussiness_name [%s], file path [%s]\n", err_code, tran_info.bussiness_name, tran_info.file_path);
+    printf("===============================================================================\n");
+}
+bool readBufferFromFile(char *pPath, unsigned char *pBuffer, int nInSize, int *pSizeUsed)
+{
+    if (!pPath || !pBuffer) {
+        return false;
+    }
+    int uLen = 0;
+    FILE * file = fopen(pPath, "rb");
+    if (!file) {
+        return false;
+    }
+    fseek(file, 0L, SEEK_END);
+    uLen = ftell(file);
+    fseek(file, 0L, SEEK_SET);
+    if (0 == uLen || nInSize < uLen) {
+        printf("invalide file or buffer size is too small...\n");
+        return false;
+    }
+    *pSizeUsed = fread(pBuffer, 1, uLen, file);
+    if (pBuffer[uLen-1] == 0x0a) {
+        *pSizeUsed = uLen - 1;
+        pBuffer[uLen -1] = '\0';
+    }
+    printf("len:%d, ulen:%d\n",uLen, *pSizeUsed);
+    fclose(file);
+    return true;
+}
+void log_func(int level, const char* module, int line, const char* message)
+{
+    printf("%s\n", message);
+}
+bool initDevice()
+{
+    unsigned char license[256] = {0};
+    int nLicenseSize = 0;
+    if (!readBufferFromFile("./licence.sign.file.txt", license, sizeof(license), &nLicenseSize)) {
+        printf("[error]get license from file failed...\n");
+        return false;
+    }
+    unsigned char guid[32] = {0};
+    int nGUIDSize = 0;
+    if(!readBufferFromFile("./GUID_file.txt", guid, sizeof(guid), &nGUIDSize)) {
+        printf("[error]get guid from file failed...\n");
+        return false;
+    }
+    char svrPubkey[256] = {0};
+    int nPubkeySize = 0;
+    if (!readBufferFromFile("./1000000004.pem", svrPubkey, sizeof(svrPubkey), &nPubkeySize)) {
+        printf("[error]get svrPubkey from file failed...\n");
+        return NULL;
+    }
+    tx_device_info info = {0};
+    info.os_platform = "Linux";
+    info.device_name = "demo1";
+    info.device_serial_number = guid;
+    info.device_license = license;
+    info.product_version = 1;
+    info.network_type = network_type_wifi;
+    info.product_id = 1000000004;
+    info.server_pub_key = svrPubkey;
+    tx_device_notify notify = {0};
+    notify.on_login_complete = on_login_complete;
+    notify.on_online_status = on_online_status;
+    notify.on_binder_list_change = NULL;
+    tx_init_path init_path = {0};
+    init_path.system_path = "./";
+    init_path.system_path_capicity = 100 * 1024;
+    init_path.app_path = "./";
+    init_path.app_path_capicity = 1024 * 1024;
+    init_path.temp_path = "./";
+    init_path.temp_path_capicity = 10 * 1024;
+    tx_set_log_func(log_func);
+    int ret = tx_init_device(&info, &notify, &init_path);
+    if (err_null == ret) {
+        printf(" >>> tx_init_device success\n");
+    } else {
+        printf(" >>> tx_init_device failed [%d]\n", ret);
+        return false;
+    }
+    tx_file_transfer_notify fileTransferNotify = {0};
+    fileTransferNotify.on_transfer_complete = ontransfercomplete;
+    tx_init_file_transfer(fileTransferNotify, "./recv/");
+    return true;
+}
+int main(int argc, char* argv[])
+{
+    if ( !initDevice() ) {
+        return -1;
+    }
+    char input[100];
+    while (scanf("%s", input)) {
+        if ( !strcmp(input, "quit") ) {
+            tx_exit_device();
+            break;
+        }
+        sleep(1);
+    }
+    return 0;
+}
diff --git a/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/demo_video.c b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/demo_video.c
new file mode 100644
index 000000000..067792325
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/demo_video.c
@@ -0,0 +1,253 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include <pthread.h>
+#include <sys/time.h>
+#include "TXSDKCommonDef.h"
+#include "TXDeviceSDK.h"
+static FILE *fstream = NULL;
+static char* s_cData = NULL;
+static bool s_bstart = false;
+static pthread_t thread_enc_id = 0;
+static unsigned long s_dwTotalFrameIndex = 0;
+unsigned long _GetTickCount()
+{
+    struct timeval current = {0};
+    gettimeofday(&current, NULL);
+    return (current.tv_sec*1000 + current.tv_usec/1000);
+}
+static void* EncoderThread(void* pThreadData)
+{
+    while(s_bstart) {
+        if(s_bstart) {
+            if(fstream &&!feof(fstream)) {
+                int iLen = 0;
+                int iType = -1;
+                fread(&iLen, 1, 4, fstream);
+                fread(&iType, 1, 4, fstream);
+                if (iLen > 0) {
+                    fread(s_cData, 1, iLen, fstream);
+                    static int s_nFrameIndex = 0;
+                    static int s_gopIndex = -1;
+                    unsigned char * pcEncData = (unsigned char *)s_cData;
+                    int nEncDataLen = iLen;
+                    int nFrameType = 1;
+                    if(iType == 0) {
+                        s_nFrameIndex = 0;
+                        s_gopIndex++;
+                        nFrameType = 0;
+                    } else {
+                        s_nFrameIndex++;
+                        nFrameType = 1;
+                    }
+                    if(s_gopIndex == -1) {
+                        printf("No I Frame s_gopIndex == -1\n");
+                    } else {
+                        if(nEncDataLen != 0) {
+                            tx_set_video_data(pcEncData, nEncDataLen, nFrameType, _GetTickCount(), s_gopIndex, s_nFrameIndex, s_dwTotalFrameIndex++, 40);
+                        }
+                    }
+                }
+            } else if(fstream && feof(fstream)) {
+                fclose(fstream);
+                fstream = fopen("test.264", "rb");
+            }
+        }
+        usleep(90000);
+    }
+    return 0;
+}
+bool test_start_camera()
+{
+    printf("###### test_start_camera ###################################### \n");
+    if (!fstream) {
+        fstream = fopen("test.264", "rb");
+    }
+    if (!s_cData) {
+        s_cData = malloc(1280*720);
+    }
+    if (!fstream || !s_cData) {
+        return false;
+    }
+    s_bstart = true;
+    int ret = pthread_create(&thread_enc_id, NULL, EncoderThread, NULL);
+    if (ret || !thread_enc_id) {
+        s_bstart = false;
+        return false;
+    }
+    return true;
+}
+bool test_stop_camera()
+{
+    printf("###### test_stop_camera ###################################### \n");
+    s_bstart = false;
+    if(fstream) {
+        fclose(fstream);
+        fstream = NULL;
+    }
+    if(s_cData) {
+        free(s_cData);
+        s_cData = NULL;
+    }
+    if(thread_enc_id !=0) {
+        pthread_join(thread_enc_id,NULL);
+        thread_enc_id = 0;
+    }
+    return true;
+}
+bool test_set_bitrate(int bit_rate)
+{
+    printf("###### test_set_bitrate  ##################################### %d \n", bit_rate);
+    return true;
+}
+bool test_restart_gop()
+{
+    printf("###### test_restart_gop ###################################### \n");
+    return true;
+}
+bool test_start_mic()
+{
+    printf("###### test_start_mic ###################################### \n");
+    return true;
+}
+bool test_stop_mic()
+{
+    printf("###### test_stop_mic ######################################\n");
+    return true;
+}
+static bool g_start_av_service = false;
+void on_login_complete(int errcode)
+{
+    printf("on_login_complete | code[%d]\n", errcode);
+}
+void on_online_status(int old, int new)
+{
+    printf("online status: %s\n", 11 == new ? "true" : "false");
+    if(11 == new && !g_start_av_service) {
+        tx_av_callback avcallback = {0};
+        avcallback.on_start_camera = test_start_camera;
+        avcallback.on_stop_camera = test_stop_camera;
+        avcallback.on_set_bitrate = test_set_bitrate;
+        avcallback.on_start_mic = test_start_mic;
+        avcallback.on_stop_mic = test_stop_mic;
+        int ret = tx_start_av_service(&avcallback);
+        if (err_null == ret) {
+            printf(" >>> tx_start_av_service successed\n");
+        } else {
+            printf(" >>> tx_start_av_service failed [%d]\n", ret);
+        }
+        g_start_av_service = true;
+    }
+}
+bool readBufferFromFile(char *pPath, unsigned char *pBuffer, int nInSize, int *pSizeUsed)
+{
+    if (!pPath || !pBuffer) {
+        return false;
+    }
+    int uLen = 0;
+    FILE * file = fopen(pPath, "rb");
+    if (!file) {
+        return false;
+    }
+    fseek(file, 0L, SEEK_END);
+    uLen = ftell(file);
+    fseek(file, 0L, SEEK_SET);
+    if (0 == uLen || nInSize < uLen) {
+        printf("invalide file or buffer size is too small...\n");
+        return false;
+    }
+    *pSizeUsed = fread(pBuffer, 1, uLen, file);
+    if (pBuffer[uLen-1] == 0x0a) {
+        *pSizeUsed = uLen - 1;
+        pBuffer[uLen - 1] = '\0';
+    }
+    printf("len:%d, ulen:%d\n",uLen, *pSizeUsed);
+    fclose(file);
+    return true;
+}
+void log_func(int level, const char* module, int line, const char* message)
+{
+    printf("%s\n", message);
+}
+bool initDevice()
+{
+    unsigned char license[256] = {0};
+    int nLicenseSize = 0;
+    if (!readBufferFromFile("./licence.sign.file.txt", license, sizeof(license), &nLicenseSize)) {
+        printf("[error]get license from file failed...\n");
+        return false;
+    }
+    unsigned char guid[32] = {0};
+    int nGUIDSize = 0;
+    if(!readBufferFromFile("./GUID_file.txt", guid, sizeof(guid), &nGUIDSize)) {
+        printf("[error]get guid from file failed...\n");
+        return false;
+    }
+    char svrPubkey[256] = {0};
+    int nPubkeySize = 0;
+    if (!readBufferFromFile("./1000000004.pem", svrPubkey, sizeof(svrPubkey), &nPubkeySize)) {
+        printf("[error]get svrPubkey from file failed...\n");
+        return NULL;
+    }
+    tx_device_info info = {0};
+    info.os_platform = "Linux";
+    info.device_name = "demo1";
+    info.device_serial_number = guid;
+    info.device_license = license;
+    info.product_version = 1;
+    info.network_type = network_type_wifi;
+    info.product_id = 1000000004;
+    info.server_pub_key = svrPubkey;
+    tx_device_notify notify = {0};
+    notify.on_login_complete = on_login_complete;
+    notify.on_online_status = on_online_status;
+    notify.on_binder_list_change = NULL;
+    tx_init_path init_path = {0};
+    init_path.system_path = "./";
+    init_path.system_path_capicity = 100 * 1024;
+    init_path.app_path = "./";
+    init_path.app_path_capicity = 1024 * 1024;
+    init_path.temp_path = "./";
+    init_path.temp_path_capicity = 10 * 1024;
+    tx_set_log_func(log_func);
+    int ret = tx_init_device(&info, &notify, &init_path);
+    if (err_null == ret) {
+        printf(" >>> tx_init_device success\n");
+    } else {
+        printf(" >>> tx_init_device failed [%d]\n", ret);
+        return false;
+    }
+    return true;
+}
+int main(int argc, char* argv[])
+{
+    if ( !initDevice() ) {
+        return -1;
+    }
+    char input[100];
+    while (scanf("%s", input)) {
+        if ( !strcmp(input, "quit") ) {
+            if (g_start_av_service) {
+                tx_stop_av_service();
+            }
+            tx_exit_device();
+            break;
+        }
+        sleep(1);
+    }
+    return 0;
+}
diff --git a/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/include/TXAudioVideo.h b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/include/TXAudioVideo.h
new file mode 100644
index 000000000..d7850c79c
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/include/TXAudioVideo.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __TX_AUDIO_VIDEO_H__
+#define __TX_AUDIO_VIDEO_H__
+#include "TXSDKCommonDef.h"
+CXX_EXTERN_BEGIN
+typedef struct _tx_audio_encode_param {
+    unsigned char head_length;
+    unsigned char audio_format;
+    unsigned char encode_param;
+    unsigned char frame_per_pkg;
+    unsigned int sampling_info;
+    unsigned int reserved;
+} tx_audio_encode_param;
+#define GET_SIMPLING_INFO(channel,sampling,bit) ((channel << 24) | (sampling << 16) | (bit << 8) | 0x00)
+typedef struct _tx_av_callback {
+    bool (*on_start_camera)();
+    bool (*on_stop_camera)();
+    bool (*on_set_bitrate)(int bit_rate);
+    bool (*on_start_mic)();
+    bool (*on_stop_mic)();
+    void (*on_recv_audiodata)(tx_audio_encode_param *param, unsigned char *pcEncData, int nEncDataLen);
+} tx_av_callback;
+SDK_API int tx_start_av_service( tx_av_callback *callback);
+SDK_API int tx_stop_av_service();
+SDK_API void tx_set_video_data(unsigned char *pcEncData, int nEncDataLen,
+                               int nFrameType, int nTimeStamps, int nGopIndex, int nFrameIndex, int nTotalIndex, int nAvgQP);
+SDK_API void tx_set_audio_data(tx_audio_encode_param *param, unsigned char *pcEncData, int nEncDataLen);
+CXX_EXTERN_END
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/include/TXDataPoint.h b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/include/TXDataPoint.h
new file mode 100644
index 000000000..c5e8e5a5c
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/include/TXDataPoint.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __TX_DATA_POINT_H__
+#define __TX_DATA_POINT_H__
+#include "TXSDKCommonDef.h"
+#include "TXMsg.h"
+CXX_EXTERN_BEGIN
+typedef struct tag_tx_data_point {
+    unsigned int id;
+    char * value;
+    unsigned int seq;
+    unsigned int ret_code;
+} tx_data_point;
+typedef struct tag_tx_data_point_notify {
+    void (*on_receive_data_point)(unsigned long long from_client, tx_data_point * data_points, int data_points_count);
+} tx_data_point_notify;
+SDK_API int tx_init_data_point(const tx_data_point_notify *notify);
+typedef void (*on_report_data_point_ret)(unsigned int cookie, int err_code);
+SDK_API int tx_report_data_point(unsigned int id, char * value, unsigned int * cookie, on_report_data_point_ret ret_callback);
+SDK_API int tx_report_data_points(tx_data_point * data_points, int data_points_count, unsigned int * cookie, on_report_data_point_ret ret_callback);
+typedef void (*on_ack_data_point_ret)(unsigned int cookie, unsigned long long from_client, int err_code);
+SDK_API int tx_ack_data_point(unsigned long long from_client, unsigned int id, char * value, unsigned int seq, unsigned int ret_code, unsigned int * cookie, on_ack_data_point_ret ret_callback);
+SDK_API int tx_ack_data_points(unsigned long long from_client, tx_data_point * data_points, int data_points_count, unsigned int * cookie, on_ack_data_point_ret ret_callback);
+CXX_EXTERN_END
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h
new file mode 100644
index 000000000..70b829f57
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __TX_DEVICE_SDK_H__
+#define __TX_DEVICE_SDK_H__
+#include "TXAudioVideo.h"
+#include "TXMsg.h"
+#include "TXDataPoint.h"
+#include "TXFileTransfer.h"
+CXX_EXTERN_BEGIN
+enum tx_test_mode_enum {
+    test_mode_default = 0,
+    test_mode_test_env = 1,
+};
+enum tx_network_type {
+    network_type_none = 0,
+    network_type_wifi = 1,
+    network_type_mobile = 2,
+    network_type_unicom = 3,
+    network_type_telecom = 4,
+    network_type_hongkong = 5,
+};
+typedef struct _tx_device_info {
+    char * os_platform;
+    int network_type;
+    char * device_name;
+    char * device_serial_number;
+    char * device_license;
+    int product_version;
+    int product_id;
+    char * server_pub_key;
+    unsigned int test_mode;
+} tx_device_info;
+typedef struct tag_tx_binder_info {
+    int type;
+    unsigned long long tinyid;
+    unsigned long long uin;
+    char nick_name[128];
+    int gender;
+    char head_url[1024];
+} tx_binder_info;
+typedef struct _tx_device_notify {
+    void (*on_login_complete)(int error_code);
+    void (*on_online_status)(int old_status, int new_status);
+    void (*on_binder_list_change)(int error_code, tx_binder_info * pBinderList, int nCount);
+} tx_device_notify;
+typedef struct _tx_init_path {
+    char * system_path;
+    unsigned int system_path_capicity;
+    char * app_path;
+    unsigned int app_path_capicity;
+    char * temp_path;
+    unsigned int temp_path_capicity;
+} tx_init_path;
+enum tx_binder_type {
+    binder_type_unknown = 0,
+    binder_type_owner = 1,
+    binder_type_sharer = 2,
+};
+enum tx_binder_gender {
+    binder_gender_unknown = -1,
+    binder_gender_male = 0,
+    binder_gender_female = 1,
+};
+SDK_API int tx_init_device(tx_device_info *info, tx_device_notify *notify, tx_init_path* init_path);
+SDK_API int tx_ack_app(unsigned int ip, unsigned int port);
+SDK_API int tx_exit_device();
+SDK_API int tx_get_sdk_version(unsigned int *main_ver, unsigned int *sub_ver, unsigned int *build_no);
+typedef void (*tx_log_func)(int level, const char* module, int line, const char* message);
+SDK_API void tx_set_log_func(tx_log_func log_func);
+typedef void (*on_get_binder_list_result)(tx_binder_info * pBinderList, int nCount);
+SDK_API int tx_get_binder_list(tx_binder_info * pBinderList, int* nCount, on_get_binder_list_result callback);
+SDK_API unsigned long long tx_get_self_din();
+SDK_API int tx_device_relogin();
+typedef void (*on_erase_all_binders)(int error_code);
+SDK_API int tx_erase_all_binders(on_erase_all_binders callback);
+SDK_API int tx_get_server_time();
+CXX_EXTERN_END
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h
new file mode 100644
index 000000000..4be23662c
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __TX_FILE_TRANSFER_H__
+#define __TX_FILE_TRANSFER_H__
+#include "TXSDKCommonDef.h"
+#include "TXOldInf.h"
+CXX_EXTERN_BEGIN
+#define BUSINESS_NAME_IMAGE_MSG "ImgMsg"
+#define BUSINESS_NAME_AUDIO_MSG "AudioMsg"
+#define BUSINESS_NAME_VIDEO_MSG "VideoMsg"
+#define BUSINESS_NAME_NAS_DEVPUSHFILE "7000-NASDevPushFile"
+#define BUSINESS_NAME_NAS_DEVPUSHTHUMB "7001-NASDevPushThumb"
+enum tx_file_transfer_type {
+    transfet_type_none = 0,
+    transfer_type_upload = 1,
+    transfer_type_download = 2,
+    transfer_type_c2c_in = 3,
+    transfer_type_c2c_out = 4,
+};
+enum tx_file_transfer_filetype {
+    transfer_filetype_image = 1,
+    transfer_filetype_video = 2,
+    transfer_filetype_audio = 3,
+    transfer_filetype_other = 4,
+};
+enum tx_file_transfer_channeltype {
+    transfer_channeltype_FTN = 1,
+    transfer_channeltype_MINI = 2,
+};
+typedef struct tag_tx_file_transfer_info {
+    char file_path[1024];
+    char file_key[512];
+    int key_length;
+    char * buffer_raw;
+    unsigned long long buffer_raw_len;
+    char buffer_key[512];
+    int buffer_key_len;
+    char * buff_with_file;
+    int buff_length;
+    char bussiness_name[64];
+    unsigned long long file_size;
+    int channel_type;
+    int file_type;
+    int transfer_type;
+} tx_file_transfer_info;
+typedef struct tag_tx_file_transfer_notify {
+    void (*on_transfer_progress)(unsigned long long transfer_cookie, unsigned long long transfer_progress, unsigned long long max_transfer_progress);
+    void (*on_transfer_complete)(unsigned long long transfer_cookie, int err_code, tx_file_transfer_info* tran_info);
+    void (*on_file_in_come)(unsigned long long transfer_cookie, const tx_ccmsg_inst_info * inst_info, const tx_file_transfer_info * tran_info);
+} tx_file_transfer_notify;
+SDK_API int tx_init_file_transfer(tx_file_transfer_notify notify, char * path_recv_file);
+SDK_API int tx_upload_file(int channeltype, int filetype, char * file_path, unsigned long long * transfer_cookie);
+SDK_API int tx_download_file(int channeltype, int filetype, char * file_key, int key_length, unsigned long long * transfer_cookie);
+SDK_API int tx_send_file_to(unsigned long long target_id, char * file_path, unsigned long long * transfer_cookie, char * buff_with_file, int buff_length, char * bussiness_name);
+SDK_API int tx_cancel_transfer(unsigned long long transfer_cookie);
+SDK_API int tx_reg_file_transfer_filter(char * bussiness_name, tx_file_transfer_notify notify);
+SDK_API int tx_get_minidownload_url(char* fileId, int fileType, char* downloadUrl);
+CXX_EXTERN_END
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/include/TXIPCAM.h b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/include/TXIPCAM.h
new file mode 100644
index 000000000..09ecbd66f
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/include/TXIPCAM.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __IPCAMERA_H__
+#define __IPCAMERA_H__
+#include "TXSDKCommonDef.h"
+#include "TXDeviceSDK.h"
+CXX_EXTERN_BEGIN
+enum definition {
+    def_low = 1,
+    def_middle = 2,
+    def_high = 3,
+};
+enum rotate_direction {
+    rotate_direction_left = 1,
+    rotate_direction_right = 2,
+    rotate_direction_up = 3,
+    rotate_direction_down = 4,
+};
+enum rotate_degree {
+    rotate_degree_h_min = 0,
+    rotate_degree_h_max = 360,
+    rotate_degree_v_min = 0,
+    rotate_degree_v_max = 180,
+};
+typedef struct _tx_ipcamera_notify {
+    int (*on_set_definition)(int definition, char *cur_definition, int cur_definition_length);
+    int (*on_control_rotate)(int rotate_direction, int rotate_degree);
+} tx_ipcamera_notify;
+SDK_API int tx_ipcamera_set_callback(tx_ipcamera_notify *notify);
+typedef struct _tx_history_video_range {
+    unsigned int start_time;
+    unsigned int end_time;
+} tx_history_video_range;
+typedef struct _tx_history_video_notify {
+    void (*on_fetch_history_video)(unsigned int last_time, int max_count, int *count, tx_history_video_range * range_list);
+    void (*on_play_history_video)(unsigned int play_time);
+} tx_history_video_notify;
+SDK_API void tx_init_history_video_notify(tx_history_video_notify *notify);
+CXX_EXTERN_END
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/include/TXMsg.h b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/include/TXMsg.h
new file mode 100644
index 000000000..a9f5b89e7
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/include/TXMsg.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __TX_MSG_H__
+#define __TX_MSG_H__
+#include "TXSDKCommonDef.h"
+CXX_EXTERN_BEGIN
+typedef void (*on_send_text_msg_ret)(unsigned int cookie, int err_code);
+SDK_API void tx_send_text_msg(int msg_id, char *text, on_send_text_msg_ret ret_callback, unsigned int *cookie, unsigned long long* to_targetids, unsigned int to_targetids_count);
+typedef struct tag_structuring_msg {
+    int msg_id;
+    char* file_path;
+    char* thumb_path;
+    char* title;
+    char* digest;
+    char* guide_words;
+    unsigned int duration;
+    unsigned long long* to_targetids;
+    unsigned int to_targetids_count;
+} structuring_msg;
+typedef struct _tx_send_msg_notify {
+    void (*on_file_transfer_progress)(const unsigned int cookie, unsigned long long transfer_progress, unsigned long long max_transfer_progress);
+    void (*on_send_structuring_msg_ret)(const unsigned int cookie, int err_code);
+} tx_send_msg_notify;
+SDK_API void tx_send_structuring_msg(const structuring_msg *msg, tx_send_msg_notify *notify, unsigned int *cookie);
+typedef void (*on_send_notify_msg_ret)(unsigned int cookie, int err_code);
+SDK_API void tx_send_notify_msg(int msg_id, char* digest, on_send_notify_msg_ret ret_callback, unsigned int *cookie, unsigned long long* to_targetids, unsigned int to_targetids_count);
+CXX_EXTERN_END
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/include/TXOTA.h b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/include/TXOTA.h
new file mode 100644
index 000000000..375c2e754
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/include/TXOTA.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __OTA_H__
+#define __OTA_H__
+#include "TXSDKCommonDef.h"
+CXX_EXTERN_BEGIN
+typedef struct _tx_ota_notify {
+    int (*on_new_pkg_come)(unsigned long long from, unsigned long long pkg_size, const char * title, const char * desc, unsigned int target_version);
+    void (*on_download_progress)(unsigned long long download_size, unsigned long long total_size);
+    void (*on_download_complete)(int ret_code);
+    void (*on_update_confirm)();
+} tx_ota_notify;
+SDK_API int tx_init_ota(tx_ota_notify * notify, int replace_timeout, char* target_pathname);
+SDK_API void tx_ack_ota_result(int ret_code, char* err_msg);
+CXX_EXTERN_END
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/include/TXOldInf.h b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/include/TXOldInf.h
new file mode 100644
index 000000000..9e345844f
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/include/TXOldInf.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __TX_OLD_INTERFACE_H__
+#define __TX_OLD_INTERFACE_H__
+#include "TXSDKCommonDef.h"
+#include "TXDataPoint.h"
+CXX_EXTERN_BEGIN
+typedef struct tag_tx_ccmsg_inst_info {
+    unsigned long long target_id;
+    unsigned int appid;
+    unsigned int instid;
+    unsigned int platform;
+    unsigned int open_appid;
+    unsigned int productid;
+    unsigned int sso_bid;
+    char * guid;
+    int guid_len;
+} tx_ccmsg_inst_info;
+typedef void (*on_send_cc_data_point_ret)(unsigned int cookie, unsigned long long to_client, int err_code);
+SDK_API int tx_send_cc_data_point(unsigned long long to_client, unsigned int id, char * value, unsigned int * cookie, on_send_cc_data_point_ret ret_callback);
+SDK_API int tx_send_cc_data_points(unsigned long long to_client, tx_data_point * data_points, int data_points_count, unsigned int * cookie, on_send_cc_data_point_ret ret_callback);
+CXX_EXTERN_END
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h
new file mode 100644
index 000000000..44498762a
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __TX_SDK_COMMON_DEF_H__
+#define __TX_SDK_COMMON_DEF_H__
+#define SDK_API __attribute__((visibility("default")))
+#ifndef __cplusplus
+#define bool _Bool
+#define true 1
+#define false 0
+#define CXX_EXTERN_BEGIN
+#define CXX_EXTERN_END
+#define C_EXTERN extern
+#else
+#define _Bool bool
+#define CXX_EXTERN_BEGIN extern "C" {
+#define CXX_EXTERN_END }
+#define C_EXTERN
+#endif
+CXX_EXTERN_BEGIN
+enum error_code {
+    err_null = 0x00000000,
+    err_failed = 0x00000001,
+    err_unknown = 0x00000002,
+    err_invalid_param = 0x00000003,
+    err_buffer_notenough = 0x00000004,
+    err_mem_alloc = 0x00000005,
+    err_internal = 0x00000006,
+    err_device_inited = 0x00000007,
+    err_av_service_started = 0x00000008,
+    err_invalid_device_info = 0x00000009,
+    err_invalid_serial_number = 0x0000000A,
+    err_invalid_fs_handler = 0x0000000B,
+    err_invalid_device_notify = 0x0000000C,
+    err_invalid_av_callback = 0x0000000D,
+    err_invalid_system_path = 0x0000000E,
+    err_invalid_app_path = 0x0000000F,
+    err_invalid_temp_path = 0x00000010,
+    err_not_impl = 0x00000011,
+    err_fetching = 0x00000012,
+    err_fetching_buff_not_enough = 0x00000013,
+    err_off_line = 0x00000014,
+    err_invalid_device_name = 0x00000015,
+    err_invalid_os_platform = 0x00000016,
+    err_invalid_license = 0x00000017,
+    err_invalid_server_pub_key = 0x00000018,
+    err_invalid_product_version = 0x00000019,
+    err_invalid_product_id = 0x0000001A,
+    err_connect_failed = 0x0000001B,
+    err_call_too_frequently = 0x0000001C,
+    err_sys_path_access_permission = 0x0000001D,
+    err_invalid_network_type = 0x0000001E,
+    err_login_failed = 0x00010001,
+    err_login_invalid_deviceinfo = 0x00010002,
+    err_login_connect_failed = 0x00010003,
+    err_login_timeout = 0x00010004,
+    err_login_eraseinfo = 0x00010005,
+    err_login_servererror = 0x00010006,
+    err_msg_sendfailed = 0x00020001,
+    err_msg_sendtimeout = 0x00020002,
+    err_av_unlogin = 0x00030001,
+    err_ft_transfer_failed = 0x00040001,
+    err_ft_file_too_large = 0x00040002,
+};
+CXX_EXTERN_END
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h
new file mode 100644
index 000000000..4f5226177
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __TX_TV_BARRAGE_H__
+#define __TX_TV_BARRAGE_H__
+#include "TXDeviceSDK.h"
+CXX_EXTERN_BEGIN
+enum tx_barrage_msg_element_type {
+    element_none = 0,
+    element_text = 1,
+    element_face = 2,
+    element_image = 3,
+    element_audio = 4,
+};
+typedef struct tag_tx_text_msg_element {
+    char * msg_text;
+} tx_text_msg_element;
+typedef struct tag_tx_face_msg_element {
+    unsigned int face_index;
+} tx_face_msg_element;
+typedef struct tag_tx_image_msg_element {
+    char * image_guid;
+    int guid_length;
+    char * image_url;
+    char * image_thumb_url;
+} tx_image_msg_element;
+typedef struct tag_tx_audio_msg_element {
+    unsigned int voice_switch;
+    char * audio_msg_url;
+} tx_audio_msg_element;
+typedef struct tag_tx_barrage_msg_element {
+    int msg_ele_type;
+    void * msg_ele_point;
+} tx_barrage_msg_element;
+typedef struct tag_tx_barrage_msg {
+    unsigned long long group_id;
+    unsigned long long from_target_id;
+    unsigned int from_target_appid;
+    unsigned int from_target_instid;
+    char * group_name;
+    char * from_nick;
+    char * from_group_card;
+    char * from_head_url;
+    tx_barrage_msg_element * msg_ele_array;
+    int msg_ele_count;
+} tx_barrage_msg;
+typedef struct tag_tx_barrage_notify {
+    void (*on_receive_barrage_msg)(tx_barrage_msg * pMsg);
+} tx_barrage_notify;
+SDK_API void tx_set_barrage_notify(tx_barrage_notify * notify);
+CXX_EXTERN_END
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/include/TXTVSDK.h b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/include/TXTVSDK.h
new file mode 100644
index 000000000..ff4066156
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/include/TXTVSDK.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __TX_TV_SDK_H__
+#define __TX_TV_SDK_H__
+#include "TXSDKCommonDef.h"
+typedef struct tag_tx_tv_notify {
+    void (*on_bind_complete)(unsigned long long ddwID, int error);
+    void (*on_receive_video_push)(char * pBufReply, int nLenReply);
+} tx_tv_notify;
+SDK_API void tx_set_tv_notify(tx_tv_notify * notify);
+typedef void (*on_receive_video_reply)(char * pBufReply, int nLenReply);
+SDK_API void tx_send_video_request(int type, unsigned long long toDin, const char * pBuff, unsigned int uLen, on_receive_video_reply callback);
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+SDK_API unsigned long long tx_get_uin_by_tinyid(unsigned long long ddwID);
+SDK_API unsigned long long tx_get_tinyid_by_uin(unsigned long long ddwID);
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/include/TXVoiceLink.h b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/include/TXVoiceLink.h
new file mode 100644
index 000000000..158a44c69
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/include/TXVoiceLink.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __TX_DECODE_ENGINE__H__
+#define __TX_DECODE_ENGINE__H__
+#include "TXSDKCommonDef.h"
+CXX_EXTERN_BEGIN
+enum RESULT {
+    ERROR_NULL = 0,
+    ERROR_INITED = 1,
+    ERROR_NO_MEMORY = 2,
+    ERROR_CREATE_LOCK_FAIL = 3,
+    ERROR_CREATE_THREAD_FAIL = 4,
+};
+#define MAX_SSID_LEN 128
+#define MAX_PSWD_LEN 128
+#define MAX_IP_LEN 16
+typedef struct {
+    char sz_ssid[MAX_SSID_LEN];
+    char sz_password[MAX_PSWD_LEN];
+    char sz_ip[MAX_IP_LEN];
+    unsigned short sh_port;
+} tx_voicelink_param;
+typedef void (*VL_FUNC_NOTIFY)(tx_voicelink_param* pparam);
+SDK_API int tx_init_decoder(VL_FUNC_NOTIFY func, int samplerate);
+SDK_API void tx_uninit_decoder();
+SDK_API void tx_fill_audio(signed short* audio, int nlen);
+CXX_EXTERN_END
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/include/TXWifisync.h b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/include/TXWifisync.h
new file mode 100644
index 000000000..bf2681c05
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/include/TXWifisync.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __TX_WIFI_SYNC_H__
+#define __TX_WIFI_SYNC_H__
+#include "TXSDKCommonDef.h"
+CXX_EXTERN_BEGIN
+enum wifisyncerror {
+    QLERROR_INIT_SUCCESS = 0,
+    QLERROR_MEMORY_ALLOC = 1,
+    QLERROR_NOTIFY_NULL = 2,
+    QLERROR_PARAM_KEY = 3,
+    QLERROR_PARAM_KEY_LEN = 4,
+    QLERROR_OPENSSL_LOAD_FAILED = 5,
+    QLERROR_HOP_NULL = 6,
+    QLERROR_SZIFNAME_INVALID = 7,
+    QLERROR_WIFICHIP_NOTSUPPORT = 8,
+    QLERROR_INIT_OTHER = 9,
+};
+enum fill80211relust {
+    QLERROR_SUCCESS = 0,
+    QLERROR_HOP = 1,
+    QLERROR_LOCK = 2,
+    QLERROR_OTHER = 3,
+    QLERROR_DECRYPT_FAILED = 4,
+    QLERROR_NEED_INIT = 5,
+    QLERROR_VERSION = 6,
+    QLERROR_START_FRAME = 7,
+    QLERROR_BCAST_NOT_FRAME = 8,
+    QLERROR_BCAST_CALC_C = 9,
+    QLERROR_BCAST_ONE_DATA = 10,
+    QLERROR_MCAST_NOT_FRAME = 11,
+    QLERROR_MCAST_ONE_DATA = 12,
+};
+#define QLMAX_SSID_LEN 128
+#define QLMAX_PSWD_LEN 128
+#define QLMAX_IP_LEN 16
+typedef struct {
+    char sz_ssid[QLMAX_SSID_LEN];
+    char sz_password[QLMAX_PSWD_LEN];
+    char sz_ip[QLMAX_IP_LEN];
+    unsigned short sh_port;
+} tx_wifi_sync_param;
+typedef void (* FUNC_HOP)(int nchannel);
+typedef void (* FUNC_NOTIFY)(tx_wifi_sync_param *pwifi_sync_param, void *puserdata);
+SDK_API int init_wifi_sync(FUNC_NOTIFY fNotify, char *szSN, void *puserdata);
+SDK_API int fill_80211_frame(const unsigned char *buff, int nlen, int npackoffset, int* pChannel);
+SDK_API void wifi_sync_notify_hop(int channel);
+SDK_API void destory_wifi_sync();
+typedef enum {
+    WCT_REALTEK8188,
+    WCT_MTK7601,
+} WifiChipType;
+SDK_API int start_smartlink(
+    FUNC_HOP fHopping,
+    char* szifName,
+    FUNC_NOTIFY fNotify,
+    char* szSN,
+    WifiChipType chipType,
+    int hoppingTime,
+    int snifferTime,
+    void* pUserData
+);
+SDK_API void stop_smartlink();
+SDK_API int is_smartlink_running();
+CXX_EXTERN_END
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/lib/so_md5.txt b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/lib/so_md5.txt
new file mode 100755
index 000000000..1a975e633
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/lib/so_md5.txt
@@ -0,0 +1 @@
+6525df04d5db00629224f7efac043ec5
diff --git a/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/makefile b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/makefile
new file mode 100755
index 000000000..d28b1562d
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/makefile
@@ -0,0 +1,19 @@
+#if compile x86 demo on unbuntu 64.
+CC:=gcc -m32
+
+all:app1 app2 app3 
+	@echo build complete
+
+
+clean:
+	-rm SDKDemo_bind SDKDemo_video SDKDemo_filetransfer
+
+app1:demo_bind.c
+	$(CC) demo_bind.c -o SDKDemo_bind -O0 -g3 -I"./include" -L"./lib" -ltxdevicesdk -lpthread -ldl -lstdc++
+
+app2:demo_video.c
+	$(CC) demo_video.c -o SDKDemo_video -O0 -g3 -I"./include" -L"./lib" -ltxdevicesdk -lpthread -ldl -lstdc++
+
+app3:demo_filetransfer.c
+	$(CC) demo_filetransfer.c -o SDKDemo_filetransfer -O0 -g3 -I"./include" -L"./lib" -ltxdevicesdk -lpthread -ldl -lstdc++
+
diff --git a/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/test.264 b/drivers/net/wireless/ssv6x5x/smartlink/qqlink-lib-mipsel/test.264
new file mode 100755
index 000000000..e69de29bb
diff --git a/drivers/net/wireless/ssv6x5x/smartlink/qqlink.c b/drivers/net/wireless/ssv6x5x/smartlink/qqlink.c
new file mode 100644
index 000000000..8b1fef2a5
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smartlink/qqlink.c
@@ -0,0 +1,205 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <stdint.h>
+#include <string.h>
+#include <sys/socket.h>
+#include <sys/errno.h>
+#include <sys/time.h>
+#include <signal.h>
+#include <linux/netlink.h>
+#include "ssv_smartlink.h"
+#include "qqlink-lib-mipsel/include/TXWifisync.h"
+static uint8_t gBuf[MAX_PAYLOAD]= {0};
+static uint32_t gBufLen=0;
+static char _sz_ssid[QLMAX_SSID_LEN];
+static char _sz_password[QLMAX_PSWD_LEN];
+static char *ssv_wpa_conf_file = "%s/conf/wpa_supplicant.conf";
+static char *ssv_enter_qqlink_mode = "cd %s/scripts/ && ./startsmartlink.sh";
+static char *ssv_start_sta_mode = "cd %s/         && ./sta.sh";
+static uint32_t gChan=SSV_MIN_CHANNEL;
+void on_wifi_sync_notify(tx_wifi_sync_param *pwifi_sync_param, void *puserdata)
+{
+    printf("received said: %s\n", pwifi_sync_param->sz_ssid);
+    printf("received password: %s\n", pwifi_sync_param->sz_password);
+    strcpy(_sz_ssid, pwifi_sync_param->sz_ssid);
+    strcpy(_sz_password, pwifi_sync_param->sz_password);
+}
+static void _ssv_qqlink_setchannel_callback(int signum)
+{
+    (void)signum;
+    ssv_smartlink_set_channel(gChan);
+    wifi_sync_notify_hop(gChan);
+    gChan++;
+    if (gChan > SSV_MAX_CHANNEL) {
+        gChan = SSV_MIN_CHANNEL;
+    }
+}
+static int _ssv_qqlink_enable_setchannel_timer(void)
+{
+    struct itimerval t;
+    t.it_interval.tv_usec = 100000;
+    t.it_interval.tv_sec = 0;
+    t.it_value.tv_usec = 100000;
+    t.it_value.tv_sec = 0;
+    if (setitimer(ITIMER_REAL, &t, NULL) < 0) {
+        printf("%s\n", strerror(errno));
+        printf("setitimer error!\n");
+        return -1;
+    }
+    signal(SIGALRM, _ssv_qqlink_setchannel_callback);
+    return 0;
+}
+static int _ssv_qqlink_disable_setchannel_timer(void)
+{
+    struct itimerval t;
+    getitimer(ITIMER_REAL, &t );
+    t.it_interval.tv_usec = 0;
+    t.it_interval.tv_sec = 0;
+    t.it_value.tv_usec = 0;
+    t.it_value.tv_sec = 0;
+    if (setitimer(ITIMER_REAL, &t, NULL) < 0) {
+        printf("%s\n", strerror(errno));
+        printf("setitimer error!\n");
+        return -1;
+    }
+    return 0;
+}
+static void _ssv_sig_int(int signum)
+{
+    (void)ssv_smartlink_stop();
+    return;
+}
+static int _ssv_qqlink_write_wpa_config_file(char *pFileName, char *pSSID, char *pPWD)
+{
+    FILE *fptr=NULL;
+    if (!pFileName || !pSSID || !pPWD) {
+        printf("Parameter error!\n");
+        return -1;
+    }
+    fptr = fopen(pFileName, "w");
+    if (fptr == NULL) {
+        printf("Open %s failed: %s\n", pFileName, strerror(errno));
+        return -2;
+    }
+    fprintf(fptr, "ctrl_interface=/var/run/wpa_supplicant\n");
+    fprintf(fptr, "ap_scan=1\n");
+    fprintf(fptr, "\n");
+    fprintf(fptr, "network={\n");
+    fprintf(fptr, "\tssid=\"%s\"\n", pSSID);
+    fprintf(fptr, "\tpsk=\"%s\"\n", pPWD);
+    fprintf(fptr, "}\n");
+    fclose(fptr);
+    printf("Write %s success.\n", pFileName);
+    return 0;
+}
+int main(int argc, char *argv[])
+{
+    int ret=-1;
+    int channel=0;
+    static int locked=0;
+    char *file_path_getcwd=NULL;
+    const char *key="Wechatiothardwav";
+    char cmdBuf[160]= {0};
+    memset(_sz_ssid, 0, QLMAX_SSID_LEN);
+    memset(_sz_password, 0, QLMAX_PSWD_LEN);
+    file_path_getcwd = (char *)malloc(80);
+    getcwd(file_path_getcwd, 80);
+    printf("==Current Path: %s==\n", file_path_getcwd);
+    sprintf(cmdBuf, ssv_enter_qqlink_mode, file_path_getcwd);
+    ret = system(cmdBuf);
+    if (ret != 0) {
+        if (file_path_getcwd) {
+            free(file_path_getcwd);
+        }
+        return ret;
+    }
+    ret = init_wifi_sync(on_wifi_sync_notify, "SZSSV01234567890", "SSV1234567890");
+    if (ret != QLERROR_INIT_SUCCESS) {
+        printf("qqlink init failed\n");
+        goto out;
+    }
+    printf("%s\n", ssv_smartlink_version());
+    ret = ssv_smartlink_start();
+    if (ret < 0) {
+        printf("ssv_smartlink_start error: %d\n", ret);
+        goto out;
+    }
+    ret = ssv_smartlink_set_promisc(1);
+    if (ret < 0) {
+        printf("ssv_smartlink_set_promisc error: %d\n", ret);
+        goto out;
+    }
+    ret = _ssv_qqlink_enable_setchannel_timer();
+    if (ret < 0) {
+        goto out;
+    }
+    signal(SIGINT, _ssv_sig_int);
+    while (1) {
+        gBufLen = 0;
+        memset(gBuf, 0, sizeof(gBuf));
+        ret = ssv_smartlink_recv_packet(gBuf, &gBufLen);
+        if (ret < 0) {
+            printf("ssv_smartlink_recv_packet error: %d\n", ret);
+            goto out;
+        }
+        ret = fill_80211_frame(gBuf, gBufLen, 0, &channel);
+        if (ret == QLERROR_SUCCESS) {
+            ret = ssv_smartlink_set_promisc(0);
+            if (ret < 0) {
+                goto out;
+            }
+            break;
+        } else if (ret == QLERROR_LOCK) {
+            if (!locked) {
+                locked = 1;
+                ret = _ssv_qqlink_disable_setchannel_timer();
+                if (ret < 0) {
+                    goto out;
+                }
+                gChan = gChan - 1;
+                if (gChan < SSV_MIN_CHANNEL) {
+                    gChan = SSV_MIN_CHANNEL;
+                }
+                printf("Channel locked to %d!\n", gChan);
+            }
+        } else if (ret == QLERROR_HOP) {
+        } else {
+        }
+    }
+    ret = 0;
+out:
+    (void)ssv_smartlink_stop();
+    if (ret == 0) {
+        sprintf(cmdBuf, ssv_wpa_conf_file, file_path_getcwd);
+        if (0 == _ssv_qqlink_write_wpa_config_file(cmdBuf, _sz_ssid, _sz_password)) {
+            char buf[64];
+            printf("Config file: %s\n", cmdBuf);
+            printf("----------------------------------------\n");
+            sprintf(buf, "cat %s", cmdBuf);
+            system(buf);
+            printf("----------------------------------------\n");
+            sprintf(cmdBuf, ssv_start_sta_mode, file_path_getcwd);
+            system(cmdBuf);
+        }
+    }
+    if (file_path_getcwd) {
+        free(file_path_getcwd);
+    }
+    return ret;
+}
diff --git a/drivers/net/wireless/ssv6x5x/smartlink/smarticomm.c b/drivers/net/wireless/ssv6x5x/smartlink/smarticomm.c
new file mode 100644
index 000000000..2a3554177
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smartlink/smarticomm.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <stdint.h>
+#include <string.h>
+#include <sys/socket.h>
+#include <sys/errno.h>
+#include <sys/time.h>
+#include <signal.h>
+#include <linux/netlink.h>
+#include "ssv_smartlink.h"
+void main(void)
+{
+    int ret=-1;
+    int timeout=0;
+    int status = 0;
+    char status_str[128];
+    char ssid[128];
+    char pass[128];
+    printf("%s\n", ssv_smartlink_version());
+    ret = smaricomm_start();
+    if (ret < 0) {
+        printf("smaricomm_start fail\n");
+        return;
+    }
+    printf("smarticomm_set_si_cmd\n");
+    status = START_SMART_ICOMM;
+    smarticomm_set_si_cmd(status);
+    do {
+        sleep(2);
+        memset(status_str,0x00,128);
+        printf("smarticomm_get_si_status\n");
+        smarticomm_get_si_status(status_str);
+        printf("status string = %s\n",status_str);
+        timeout++;
+    } while(strcmp(status_str,"OK"));
+    smarticomm_get_si_ssid(ssid);
+    printf("ssid = %s\n",ssid);
+    smarticomm_get_si_pass(pass);
+    printf("pass = %s\n",pass);
+    smarticomm_stop();
+}
diff --git a/drivers/net/wireless/ssv6x5x/smartlink/ssv_smartlink.c b/drivers/net/wireless/ssv6x5x/smartlink/ssv_smartlink.c
new file mode 100644
index 000000000..5a89112db
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smartlink/ssv_smartlink.c
@@ -0,0 +1,662 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <string.h>
+#include <unistd.h>
+#include <sys/socket.h>
+#include <sys/errno.h>
+#include <linux/genetlink.h>
+#include "ssv_smartlink.h"
+#define SSV_SMARTLINK_VERSION "v1.0"
+#define GLOBAL_NL_ID 999
+enum {
+    KSMARTLINK_ATTR_UNSPEC,
+    KSMARTLINK_ATTR_ENABLE,
+    KSMARTLINK_ATTR_SUCCESS,
+    KSMARTLINK_ATTR_CHANNEL,
+    KSMARTLINK_ATTR_PROMISC,
+    KSMARTLINK_ATTR_RXFRAME,
+    KSMARTLINK_ATTR_SI_CMD,
+    KSMARTLINK_ATTR_SI_STATUS,
+    KSMARTLINK_ATTR_SI_SSID,
+    KSMARTLINK_ATTR_SI_PASS,
+    __KSMARTLINK_ATTR_MAX,
+};
+#define KSMARTLINK_ATTR_MAX (__KSMARTLINK_ATTR_MAX - 1)
+enum {
+    KSMARTLINK_CMD_UNSPEC,
+    KSMARTLINK_CMD_SMARTLINK,
+    KSMARTLINK_CMD_SET_CHANNEL,
+    KSMARTLINK_CMD_GET_CHANNEL,
+    KSMARTLINK_CMD_SET_PROMISC,
+    KSMARTLINK_CMD_GET_PROMISC,
+    KSMARTLINK_CMD_RX_FRAME,
+    KSMARTLINK_CMD_SMARTICOMM,
+    KSMARTLINK_CMD_SET_SI_CMD,
+    KSMARTLINK_CMD_GET_SI_STATUS,
+    KSMARTLINK_CMD_GET_SI_SSID,
+    KSMARTLINK_CMD_GET_SI_PASS,
+    __KSMARTLINK_CMD_MAX,
+};
+#define KSMARTLINK_CMD_MAX (__KSMARTLINK_CMD_MAX - 1)
+struct netlink_msg {
+    struct nlmsghdr n;
+    struct genlmsghdr g;
+    char buf[MAX_PAYLOAD];
+};
+static int gnl_fd=-1;
+static int gnl_id=GLOBAL_NL_ID;
+#define GENLMSG_DATA(glh) ((void *)(NLMSG_DATA(glh) + GENL_HDRLEN))
+#define GENLMSG_PAYLOAD(glh) (NLMSG_PAYLOAD(glh, 0) - GENL_HDRLEN)
+#define NLA_DATA(na) ((void *)((char*)(na) + NLA_HDRLEN))
+static int _ssv_trigger_smartlink(unsigned int enable)
+{
+    struct netlink_msg msg;
+    struct nlattr *na;
+    int mlength, retval;
+    struct sockaddr_nl nladdr;
+    msg.n.nlmsg_len = NLMSG_LENGTH(GENL_HDRLEN);
+    msg.n.nlmsg_type = gnl_id;;
+    msg.n.nlmsg_flags = NLM_F_REQUEST;
+    msg.n.nlmsg_seq = 0;
+    msg.n.nlmsg_pid = getpid();
+#ifdef SSV_SMARTLINK_DEBUG
+    printf("KSMARTLINK_CMD_SMARTLINK\n");
+#endif
+    msg.g.cmd = KSMARTLINK_CMD_SMARTLINK;
+    na = (struct nlattr *) GENLMSG_DATA(&msg);
+    na->nla_type = KSMARTLINK_ATTR_ENABLE;
+    mlength = sizeof(unsigned int);
+    na->nla_len = mlength+NLA_HDRLEN;
+    memcpy(NLA_DATA(na), &enable, mlength);
+    msg.n.nlmsg_len += NLMSG_ALIGN(na->nla_len);
+    memset(&nladdr, 0, sizeof(nladdr));
+    nladdr.nl_family = AF_NETLINK;
+    retval = sendto(gnl_fd, (char *)&msg, msg.n.nlmsg_len, 0,
+                    (struct sockaddr *) &nladdr, sizeof(nladdr));
+    if (retval < 0) {
+        printf("Fail to send message to kernel\n");
+        return retval;
+    }
+    return retval;
+}
+static int _ssv_set_channel(unsigned int ch)
+{
+    struct netlink_msg msg;
+    struct nlattr *na;
+    int mlength, retval;
+    struct sockaddr_nl nladdr;
+    msg.n.nlmsg_len = NLMSG_LENGTH(GENL_HDRLEN);
+    msg.n.nlmsg_type = gnl_id;;
+    msg.n.nlmsg_flags = NLM_F_REQUEST;
+    msg.n.nlmsg_seq = 0;
+    msg.n.nlmsg_pid = getpid();
+#ifdef SSV_SMARTLINK_DEBUG
+    printf("KSMARTLINK_CMD_SET_CHANNEL channel[%d]\n",ch);
+#endif
+    msg.g.cmd = KSMARTLINK_CMD_SET_CHANNEL;
+    na = (struct nlattr *) GENLMSG_DATA(&msg);
+    na->nla_type = KSMARTLINK_ATTR_CHANNEL;
+    mlength = sizeof(unsigned int);
+    na->nla_len = mlength+NLA_HDRLEN;
+    memcpy(NLA_DATA(na), &ch, mlength);
+    msg.n.nlmsg_len += NLMSG_ALIGN(na->nla_len);
+    memset(&nladdr, 0, sizeof(nladdr));
+    nladdr.nl_family = AF_NETLINK;
+    retval = sendto(gnl_fd, (char *)&msg, msg.n.nlmsg_len, 0,
+                    (struct sockaddr *) &nladdr, sizeof(nladdr));
+    if (retval < 0) {
+        printf("Fail to send message to kernel\n");
+        return retval;
+    }
+    return retval;
+}
+int ssv_smartlink_set_channel(unsigned int ch)
+{
+    if (gnl_fd < 0) {
+        return SSV_ERR_START_SMARTLINK;
+    } else {
+        return _ssv_set_channel(ch);
+    }
+}
+static int _ssv_get_channel(unsigned int *pch)
+{
+    struct netlink_msg msg;
+    struct nlattr *na;
+    int mlength, retval;
+    struct sockaddr_nl nladdr;
+    int len;
+    msg.n.nlmsg_len = NLMSG_LENGTH(GENL_HDRLEN);
+    msg.n.nlmsg_type = gnl_id;;
+    msg.n.nlmsg_flags = NLM_F_REQUEST;
+    msg.n.nlmsg_seq = 0;
+    msg.n.nlmsg_pid = getpid();
+#ifdef SSV_SMARTLINK_DEBUG
+    printf("KSMARTLINK_CMD_GET_CHANNEL\n");
+#endif
+    msg.g.cmd = KSMARTLINK_CMD_GET_CHANNEL;
+    na = (struct nlattr *) GENLMSG_DATA(&msg);
+    na->nla_type = KSMARTLINK_ATTR_UNSPEC;
+    mlength = 0;
+    na->nla_len = mlength+NLA_HDRLEN;
+    msg.n.nlmsg_len += NLMSG_ALIGN(na->nla_len);
+    memset(&nladdr, 0, sizeof(nladdr));
+    nladdr.nl_family = AF_NETLINK;
+    retval = sendto(gnl_fd, (char *)&msg, msg.n.nlmsg_len, 0,
+                    (struct sockaddr *) &nladdr, sizeof(nladdr));
+    if (retval < 0) {
+        printf("Fail to send message to kernel\n");
+        return retval;
+    }
+    len = recv(gnl_fd, &msg, sizeof(msg), 0);
+    if (len > 0) {
+        if (msg.n.nlmsg_type == NLMSG_ERROR) {
+            printf("Error, receive NACK\n");
+            return -1;
+        }
+        if (!NLMSG_OK((&msg.n), len)) {
+            printf("Invalid reply message received via Netlink\n");
+            return -1;
+        }
+#ifdef SSV_SMARTLINK_DEBUG
+        printf("Receive CMD GET CHANNEL\n");
+#endif
+        na = (struct nlattr *) GENLMSG_DATA(&msg);
+        if (na->nla_type != KSMARTLINK_ATTR_CHANNEL) {
+            printf("%s Receive nla_type ERROR\n",__FUNCTION__);
+            return -1;
+        }
+        *pch = *(unsigned int *)NLA_DATA(na);
+    }
+    return -1;
+}
+int ssv_smartlink_get_channel(unsigned int *pch)
+{
+    if (gnl_fd < 0) {
+        return SSV_ERR_START_SMARTLINK;
+    } else {
+        return _ssv_get_channel(pch);
+    }
+}
+static int _ssv_set_promisc(unsigned int promisc)
+{
+    struct netlink_msg msg;
+    struct nlattr *na;
+    int mlength, retval;
+    struct sockaddr_nl nladdr;
+    msg.n.nlmsg_len = NLMSG_LENGTH(GENL_HDRLEN);
+    msg.n.nlmsg_type = gnl_id;;
+    msg.n.nlmsg_flags = NLM_F_REQUEST;
+    msg.n.nlmsg_seq = 0;
+    msg.n.nlmsg_pid = getpid();
+#ifdef SSV_SMARTLINK_DEBUG
+    printf("KSMARTLINK_CMD_SET_PROMISC\n");
+#endif
+    msg.g.cmd = KSMARTLINK_CMD_SET_PROMISC;
+    na = (struct nlattr *) GENLMSG_DATA(&msg);
+    na->nla_type = KSMARTLINK_ATTR_PROMISC;
+    mlength = sizeof(unsigned int);
+    na->nla_len = mlength+NLA_HDRLEN;
+    memcpy(NLA_DATA(na), &promisc, mlength);
+    msg.n.nlmsg_len += NLMSG_ALIGN(na->nla_len);
+    memset(&nladdr, 0, sizeof(nladdr));
+    nladdr.nl_family = AF_NETLINK;
+    retval = sendto(gnl_fd, (char *)&msg, msg.n.nlmsg_len, 0,
+                    (struct sockaddr *) &nladdr, sizeof(nladdr));
+    if (retval < 0) {
+        printf("Fail to send message to kernel\n");
+        return retval;
+    }
+    return retval;
+}
+int ssv_smartlink_set_promisc(unsigned int promisc)
+{
+    if (gnl_fd < 0) {
+        return SSV_ERR_START_SMARTLINK;
+    } else {
+        return _ssv_set_promisc(promisc);
+    }
+}
+static int _ssv_get_promisc(int sock_fd, unsigned int *promisc)
+{
+    struct netlink_msg msg;
+    struct nlattr *na;
+    int mlength, retval;
+    struct sockaddr_nl nladdr;
+    int len;
+    msg.n.nlmsg_len = NLMSG_LENGTH(GENL_HDRLEN);
+    msg.n.nlmsg_type = gnl_id;;
+    msg.n.nlmsg_flags = NLM_F_REQUEST;
+    msg.n.nlmsg_seq = 0;
+    msg.n.nlmsg_pid = getpid();
+#ifdef SSV_SMARTLINK_DEBUG
+    printf("KSMARTLINK_CMD_GET_PROMISC\n");
+#endif
+    msg.g.cmd = KSMARTLINK_CMD_GET_PROMISC;
+    na = (struct nlattr *) GENLMSG_DATA(&msg);
+    na->nla_type = KSMARTLINK_ATTR_UNSPEC;
+    mlength = 0;
+    na->nla_len = mlength+NLA_HDRLEN;
+    msg.n.nlmsg_len += NLMSG_ALIGN(na->nla_len);
+    memset(&nladdr, 0, sizeof(nladdr));
+    nladdr.nl_family = AF_NETLINK;
+    retval = sendto(gnl_fd, (char *)&msg, msg.n.nlmsg_len, 0,
+                    (struct sockaddr *) &nladdr, sizeof(nladdr));
+    if (retval < 0) {
+        printf("Fail to send message to kernel\n");
+        return retval;
+    }
+    len = recv(gnl_fd, &msg, sizeof(msg), 0);
+    if (len > 0) {
+        if (msg.n.nlmsg_type == NLMSG_ERROR) {
+            printf("Error, receive NACK\n");
+            return -1;
+        }
+        if (!NLMSG_OK((&msg.n), len)) {
+            printf("Invalid reply message received via Netlink\n");
+            return -1;
+        }
+#ifdef SSV_SMARTLINK_DEBUG
+        printf("Receive CMD GET PROMISC\n");
+#endif
+        na = (struct nlattr *) GENLMSG_DATA(&msg);
+        if (na->nla_type != KSMARTLINK_ATTR_PROMISC) {
+            printf("%s Receive nla_type ERROR\n",__FUNCTION__);
+            return -1;
+        }
+        *promisc = *(unsigned int *)NLA_DATA(na);
+    }
+    return -1;
+}
+int ssv_smartlink_get_promisc(unsigned int *paccept)
+{
+    if (gnl_fd < 0) {
+        return SSV_ERR_START_SMARTLINK;
+    } else {
+        return _ssv_get_promisc(gnl_fd, paccept);
+    }
+}
+static int _ssv_set_si_cmd(int sock_fd, unsigned int command)
+{
+    struct netlink_msg msg;
+    struct nlattr *na;
+    int mlength, retval;
+    struct sockaddr_nl nladdr;
+    msg.n.nlmsg_len = NLMSG_LENGTH(GENL_HDRLEN);
+    msg.n.nlmsg_type = gnl_id;;
+    msg.n.nlmsg_flags = NLM_F_REQUEST;
+    msg.n.nlmsg_seq = 0;
+    msg.n.nlmsg_pid = getpid();
+#ifdef SSV_SMARTLINK_DEBUG
+    printf("KSMARTLINK_CMD_SET_SI_CMD\n");
+#endif
+    msg.g.cmd = KSMARTLINK_CMD_SET_SI_CMD;
+    na = (struct nlattr *) GENLMSG_DATA(&msg);
+    na->nla_type = KSMARTLINK_ATTR_SI_CMD;
+    mlength = sizeof(unsigned int);
+    na->nla_len = mlength+NLA_HDRLEN;
+    memcpy(NLA_DATA(na), &command, mlength);
+    msg.n.nlmsg_len += NLMSG_ALIGN(na->nla_len);
+    memset(&nladdr, 0, sizeof(nladdr));
+    nladdr.nl_family = AF_NETLINK;
+    retval = sendto(gnl_fd, (char *)&msg, msg.n.nlmsg_len, 0,
+                    (struct sockaddr *) &nladdr, sizeof(nladdr));
+    if (retval < 0) {
+        printf("Fail to send message to kernel\n");
+        return retval;
+    }
+    return retval;
+}
+int smarticomm_set_si_cmd(unsigned int command)
+{
+    if (gnl_fd < 0) {
+        return SSV_ERR_SET_SI_CMD;
+    } else {
+        return _ssv_set_si_cmd(gnl_fd, command);
+    }
+}
+static int _ssv_get_si_status(uint8_t *status)
+{
+    struct netlink_msg msg;
+    struct nlattr *na;
+    int mlength, retval;
+    struct sockaddr_nl nladdr;
+    int len;
+    msg.n.nlmsg_len = NLMSG_LENGTH(GENL_HDRLEN);
+    msg.n.nlmsg_type = gnl_id;;
+    msg.n.nlmsg_flags = NLM_F_REQUEST;
+    msg.n.nlmsg_seq = 0;
+    msg.n.nlmsg_pid = getpid();
+#ifdef SSV_SMARTLINK_DEBUG
+    printf("KSMARTLINK_CMD_GET_SI_STATUS\n");
+#endif
+    msg.g.cmd = KSMARTLINK_CMD_GET_SI_STATUS;
+    na = (struct nlattr *) GENLMSG_DATA(&msg);
+    na->nla_type = KSMARTLINK_ATTR_UNSPEC;
+    mlength = 0;
+    na->nla_len = mlength+NLA_HDRLEN;
+    msg.n.nlmsg_len += NLMSG_ALIGN(na->nla_len);
+    memset(&nladdr, 0, sizeof(nladdr));
+    nladdr.nl_family = AF_NETLINK;
+    retval = sendto(gnl_fd, (char *)&msg, msg.n.nlmsg_len, 0,
+                    (struct sockaddr *) &nladdr, sizeof(nladdr));
+    if (retval < 0) {
+        printf("Fail to send message to kernel\n");
+        return retval;
+    }
+    memset((void *)&msg,0x00,sizeof(struct netlink_msg));
+    len = recv(gnl_fd, &msg, sizeof(msg), 0);
+    if (len > 0) {
+        if (msg.n.nlmsg_type == NLMSG_ERROR) {
+            printf("Error, receive NACK\n");
+            return -1;
+        }
+        if (!NLMSG_OK((&msg.n), len)) {
+            printf("Invalid reply message received via Netlink\n");
+            return -1;
+        }
+#ifdef SSV_SMARTLINK_DEBUG
+        printf("Receive CMD SET SI_STATUS\n");
+#endif
+        na = (struct nlattr *) GENLMSG_DATA(&msg);
+        if (na->nla_type != KSMARTLINK_ATTR_SI_STATUS) {
+            printf("%s Receive nla_type ERROR\n",__FUNCTION__);
+            return -1;
+        }
+        strcpy(status,(char *)NLA_DATA(na));
+    }
+    return -1;
+}
+int smarticomm_get_si_status(uint8_t *status)
+{
+    if (gnl_fd < 0) {
+        return SSV_ERR_GET_SI_STATUS;
+    } else {
+        return _ssv_get_si_status(status);
+    }
+}
+static int _ssv_get_si_ssid(uint8_t *ssid)
+{
+    struct netlink_msg msg;
+    struct nlattr *na;
+    int mlength, retval;
+    struct sockaddr_nl nladdr;
+    int len;
+    msg.n.nlmsg_len = NLMSG_LENGTH(GENL_HDRLEN);
+    msg.n.nlmsg_type = gnl_id;;
+    msg.n.nlmsg_flags = NLM_F_REQUEST;
+    msg.n.nlmsg_seq = 0;
+    msg.n.nlmsg_pid = getpid();
+#ifdef SSV_SMARTLINK_DEBUG
+    printf("KSMARTLINK_CMD_GET_SI_SSID\n");
+#endif
+    msg.g.cmd = KSMARTLINK_CMD_GET_SI_SSID;
+    na = (struct nlattr *) GENLMSG_DATA(&msg);
+    na->nla_type = KSMARTLINK_ATTR_UNSPEC;
+    mlength = 0;
+    na->nla_len = mlength+NLA_HDRLEN;
+    msg.n.nlmsg_len += NLMSG_ALIGN(na->nla_len);
+    memset(&nladdr, 0, sizeof(nladdr));
+    nladdr.nl_family = AF_NETLINK;
+    retval = sendto(gnl_fd, (char *)&msg, msg.n.nlmsg_len, 0,
+                    (struct sockaddr *) &nladdr, sizeof(nladdr));
+    if (retval < 0) {
+        printf("Fail to send message to kernel\n");
+        return retval;
+    }
+    len = recv(gnl_fd, &msg, sizeof(msg), 0);
+    if (len > 0) {
+        if (msg.n.nlmsg_type == NLMSG_ERROR) {
+            printf("Error, receive NACK\n");
+            return -1;
+        }
+        if (!NLMSG_OK((&msg.n), len)) {
+            printf("Invalid reply message received via Netlink\n");
+            return -1;
+        }
+#ifdef SSV_SMARTLINK_DEBUG
+        printf("Receive CMD SET SI_SSID\n");
+#endif
+        na = (struct nlattr *) GENLMSG_DATA(&msg);
+        if (na->nla_type != KSMARTLINK_ATTR_SI_SSID) {
+            printf("%s Receive nla_type ERROR\n",__FUNCTION__);
+            return -1;
+        }
+        strcpy(ssid,(char *)NLA_DATA(na));
+    }
+    return -1;
+}
+int smarticomm_get_si_ssid(uint8_t *ssid)
+{
+    if (gnl_fd < 0) {
+        return SSV_ERR_GET_SI_SSID;
+    } else {
+        return _ssv_get_si_ssid(ssid);
+    }
+}
+static int _ssv_get_si_pass(uint8_t *pass)
+{
+    struct netlink_msg msg;
+    struct nlattr *na;
+    int mlength, retval;
+    struct sockaddr_nl nladdr;
+    int len;
+    msg.n.nlmsg_len = NLMSG_LENGTH(GENL_HDRLEN);
+    msg.n.nlmsg_type = gnl_id;;
+    msg.n.nlmsg_flags = NLM_F_REQUEST;
+    msg.n.nlmsg_seq = 0;
+    msg.n.nlmsg_pid = getpid();
+#ifdef SSV_SMARTLINK_DEBUG
+    printf("KSMARTLINK_CMD_SI_PASS\n");
+#endif
+    msg.g.cmd = KSMARTLINK_CMD_GET_SI_PASS;
+    na = (struct nlattr *) GENLMSG_DATA(&msg);
+    na->nla_type = KSMARTLINK_ATTR_UNSPEC;
+    mlength = 0;
+    na->nla_len = mlength+NLA_HDRLEN;
+    msg.n.nlmsg_len += NLMSG_ALIGN(na->nla_len);
+    memset(&nladdr, 0, sizeof(nladdr));
+    nladdr.nl_family = AF_NETLINK;
+    retval = sendto(gnl_fd, (char *)&msg, msg.n.nlmsg_len, 0,
+                    (struct sockaddr *) &nladdr, sizeof(nladdr));
+    if (retval < 0) {
+        printf("Fail to send message to kernel\n");
+        return retval;
+    }
+    len = recv(gnl_fd, &msg, sizeof(msg), 0);
+    if (len > 0) {
+        if (msg.n.nlmsg_type == NLMSG_ERROR) {
+            printf("Error, receive NACK\n");
+            return -1;
+        }
+        if (!NLMSG_OK((&msg.n), len)) {
+            printf("Invalid reply message received via Netlink\n");
+            return -1;
+        }
+#ifdef SSV_SMARTLINK_DEBUG
+        printf("Receive CMD SET SI_PASS\n");
+#endif
+        na = (struct nlattr *) GENLMSG_DATA(&msg);
+        if (na->nla_type != KSMARTLINK_ATTR_SI_PASS) {
+            printf("%s Receive nla_type ERROR\n",__FUNCTION__);
+            return -1;
+        }
+        strcpy(pass,(char *)NLA_DATA(na));
+    }
+    return -1;
+}
+int smarticomm_get_si_pass(uint8_t *pass)
+{
+    if (gnl_fd < 0) {
+        return SSV_ERR_GET_SI_PASS;
+    } else {
+        return _ssv_get_si_pass(pass);
+    }
+}
+static int _ssv_netlink_init(void)
+{
+    int fd;
+    struct sockaddr_nl local;
+    fd = socket(AF_NETLINK, SOCK_RAW, NETLINK_GENERIC);
+    if (fd < 0) {
+        printf("fail to create netlink socket\n");
+        return -1;
+    }
+    memset(&local, 0, sizeof(local));
+    local.nl_family = AF_NETLINK;
+    local.nl_groups = 0;
+    if (bind(fd, (struct sockaddr *) &local, sizeof(local)) < 0)
+        goto error;
+    return fd;
+error:
+    close(fd);
+    return -1;
+}
+static int _ssv_netlink_close(int *psock_fd)
+{
+    if (psock_fd) {
+        if (*psock_fd > 0) {
+            close(*psock_fd);
+        }
+        *psock_fd = -1;
+    }
+    return 0;
+}
+int ssv_smartlink_start(void)
+{
+    int ret=-1;
+    unsigned int ch=0;
+    unsigned int accept=0;
+    gnl_fd = _ssv_netlink_init();
+    if (gnl_fd < 0) {
+        ret = gnl_fd;
+        goto out;
+    }
+    ret = _ssv_trigger_smartlink(1);
+    if (ret < 0) {
+        goto out;
+    }
+    ret = 0;
+out:
+    return ret;
+}
+int ssv_smartlink_stop(void)
+{
+    (void)_ssv_trigger_smartlink(0);
+    (void)_ssv_netlink_close(&gnl_fd);
+    return 0;
+}
+void hexdump(unsigned char *buf, int len)
+{
+    int i;
+    printf("\n-----------------------------\n");
+    printf("hexdump(len=%d):\n", len);
+    for (i = 0; i < len; i++) {
+        printf(" %02x", buf[i]);
+        if ((i+1)%40 == 0)
+            printf("\n");
+    }
+    printf("\n-----------------------------\n");
+}
+int ssv_smartlink_recv_packet(uint8_t *pOutBuf, unsigned int *pOutBufLen)
+{
+    int len;
+    struct netlink_msg msg;
+    struct nlattr *na;
+    struct ssv_wireless_register *reg;
+    len = recv(gnl_fd, &msg, sizeof(msg), 0);
+    if (len > 0) {
+        if (msg.n.nlmsg_type == NLMSG_ERROR) {
+            printf("Error, receive NACK\n");
+            return -1;
+        }
+        if (!NLMSG_OK((&msg.n), len)) {
+            printf("Invalid reply message received via Netlink\n");
+            return -1;
+        }
+        na = (struct nlattr *) GENLMSG_DATA(&msg);
+        if (na->nla_type != KSMARTLINK_ATTR_RXFRAME) {
+            printf("%s Receive nla_type ERROR\n",__FUNCTION__);
+            return -1;
+        }
+        *pOutBufLen = na->nla_len - NLA_HDRLEN;
+        memcpy(pOutBuf,(unsigned char *)NLA_DATA(na),*pOutBufLen);
+#ifdef SSV_SMARTLINK_DEBUG
+        printf("Receive RX FRAME pOutBufLen[%d] nla_len[%d]\n",*pOutBufLen,na->nla_len);
+#endif
+        return 1;
+    }
+    return -1;
+}
+static int _ssv_trigger_smarticomm(unsigned int enable)
+{
+    struct netlink_msg msg;
+    struct nlattr *na;
+    int mlength, retval;
+    struct sockaddr_nl nladdr;
+    msg.n.nlmsg_len = NLMSG_LENGTH(GENL_HDRLEN);
+    msg.n.nlmsg_type = gnl_id;;
+    msg.n.nlmsg_flags = NLM_F_REQUEST;
+    msg.n.nlmsg_seq = 0;
+    msg.n.nlmsg_pid = getpid();
+#ifdef SSV_SMARTLINK_DEBUG
+    printf("KSMARTLINK_CMD_SMARTICOMM\n");
+#endif
+    msg.g.cmd = KSMARTLINK_CMD_SMARTICOMM;
+    na = (struct nlattr *) GENLMSG_DATA(&msg);
+    na->nla_type = KSMARTLINK_ATTR_ENABLE;
+    mlength = (sizeof(unsigned int));
+    na->nla_len = mlength+NLA_HDRLEN;
+    memcpy(NLA_DATA(na), &enable, mlength);
+    msg.n.nlmsg_len += NLMSG_ALIGN(na->nla_len);
+    memset(&nladdr, 0, sizeof(nladdr));
+    nladdr.nl_family = AF_NETLINK;
+    retval = sendto(gnl_fd, (char *)&msg, msg.n.nlmsg_len, 0,
+                    (struct sockaddr *) &nladdr, sizeof(nladdr));
+    if (retval < 0)
+        printf("Fail to send message to kernel\n");
+}
+int smaricomm_start(void)
+{
+    int ret=-1;
+    unsigned int ch=0;
+    unsigned int accept=0;
+    gnl_fd = _ssv_netlink_init();
+    if (gnl_fd < 0) {
+        ret = gnl_fd;
+        goto out;
+    }
+    ret = _ssv_trigger_smarticomm(START_SMART_ICOMM);
+    if (ret < 0) {
+        goto out;
+    }
+    ret = 0;
+out:
+    return ret;
+}
+int smarticomm_stop(void)
+{
+    (void)_ssv_trigger_smarticomm(STOP_SMART_ICOMM);
+    (void)_ssv_netlink_close(&gnl_fd);
+    return 0;
+}
+static char version[64]="SSV SmartLink Verison: " SSV_SMARTLINK_VERSION;
+char *ssv_smartlink_version(void)
+{
+    return version;
+}
diff --git a/drivers/net/wireless/ssv6x5x/smartlink/ssv_smartlink.h b/drivers/net/wireless/ssv6x5x/smartlink/ssv_smartlink.h
new file mode 100644
index 000000000..22b571a06
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/smartlink/ssv_smartlink.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV_SMARTLINK_H
+#define _SSV_SMARTLINK_H
+#define MAX_PAYLOAD (4096)
+enum {
+    SSV_ERR_BASE = -255,
+    SSV_ERR_PARAMETER,
+    SSV_ERR_NETLINK_SOCKET,
+    SSV_ERR_NETLINK_BIND,
+    SSV_ERR_NETLINK_SENDMSG,
+    SSV_ERR_NETLINK_RECVMSG,
+    SSV_ERR_NETLINK_CORRUPTED,
+    SSV_ERR_START_SMARTLINK = -248,
+    SSV_ERR_STOP_SMARTLINK,
+    SSV_ERR_SET_CHANNEL,
+    SSV_ERR_GET_CHANNEL,
+    SSV_ERR_SET_PROMISC,
+    SSV_ERR_GET_PROMISC,
+    SSV_ERR_SET_SI_CMD,
+    SSV_ERR_GET_SI_STATUS,
+    SSV_ERR_GET_SI_SSID,
+    SSV_ERR_GET_SI_PASS,
+};
+enum ssv_smart_icomm_cmd {
+    STOP_SMART_ICOMM,
+    START_SMART_ICOMM,
+    RESET_SMART_ICOMM,
+    MAX_SMART_ICOMM
+};
+#define SSV_MIN_CHANNEL (1)
+#define SSV_MAX_CHANNEL (14)
+#define SSV_PROMISC_DISABLED (0)
+#define SSV_PROMISC_ENABLED (1)
+int ssv_smartlink_start(void);
+int ssv_smartlink_set_channel(uint32_t ch);
+int ssv_smartlink_get_channel(uint32_t *pch);
+int ssv_smartlink_set_promisc(uint32_t promisc);
+int ssv_smartlink_get_promisc(uint32_t *promisc);
+int ssv_smartlink_recv_packet(uint8_t *pOutBuf, uint32_t *pOutBufLen);
+int ssv_smartlink_stop(void);
+char *ssv_smartlink_version(void);
+int smaricomm_start(void);
+int smarticomm_set_si_cmd(uint32_t command);
+int smarticomm_get_si_status(uint8_t *status);
+int smarticomm_get_si_ssid(uint8_t *ssid);
+int smarticomm_get_si_pass(uint8_t *pass);
+int smarticomm_stop(void);
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/ssv6x5x-generic-wlan.c b/drivers/net/wireless/ssv6x5x/ssv6x5x-generic-wlan.c
new file mode 100644
index 000000000..6d86793b1
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/ssv6x5x-generic-wlan.c
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/irq.h>
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/vmalloc.h>
+#include <linux/gpio.h>
+#include <linux/mmc/host.h>
+#include <linux/delay.h>
+#include <linux/regulator/consumer.h>
+#include <asm/io.h>
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
+#include <linux/printk.h>
+#include <linux/err.h>
+#else
+#include <config/printk.h>
+#endif
+extern int rockchip_wifi_power(int on);
+extern int rockchip_wifi_set_carddetect(int val);
+#ifdef ROCKCHIP_WIFI_AUTO_SUPPORT
+extern char wifi_chip_type_string[];
+#endif
+#define GPIO_REG_WRITEL(val,reg) \
+ do { \
+  __raw_writel(val, CTL_PIN_BASE + (reg)); \
+ } while (0)
+static int g_wifidev_registered = 0;
+extern int tu_ssvdevice_init(void);
+extern void tu_ssvdevice_exit(void);
+extern int ssv6xxx_get_dev_status(void);
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+extern int aes_init(void);
+extern void aes_fini(void);
+extern int sha1_mod_init(void);
+extern void sha1_mod_fini(void);
+#endif
+void ssv_wifi_power(void)
+{
+//rockchip_wifi_set_carddetect(0);
+//msleep(50);
+//rockchip_wifi_power(0);
+//msleep(50);
+//rockchip_wifi_power(1);
+//msleep(50);
+//rockchip_wifi_set_carddetect(1);
+    msleep(150);
+}
+int initWlan(void)
+{
+    int ret = 0;
+    int time = 5;
+    ssv_wifi_power();
+    msleep(120);
+    g_wifidev_registered = 1;
+    ret = tu_ssvdevice_init();
+    while(time-- > 0) {
+        msleep(1000);
+        // TODO: fix this!
+        //if(ssv6xxx_get_dev_status() == 1)
+        break;
+        printk("%s : Retry to carddetect\n",__func__);
+        ssv_wifi_power();
+    }
+#ifdef ROCKCHIP_WIFI_AUTO_SUPPORT
+    if (!ret) {
+        strcpy(wifi_chip_type_string, "ssv6051");
+        printk(KERN_INFO "wifi_chip_type_string : %s\n",wifi_chip_type_string);
+    }
+#endif
+    return ret;
+}
+void exitWlan(void)
+{
+    if (g_wifidev_registered) {
+        tu_ssvdevice_exit();
+        msleep(50);
+#ifndef ROCKCHIP_WIFI_AUTO_SUPPORT
+        rockchip_wifi_set_carddetect(0);
+#endif
+        rockchip_wifi_power(0);
+        g_wifidev_registered = 0;
+    }
+    return;
+}
+static __init int tu_generic_wifi_init_module(void)
+{
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+    sha1_mod_init();
+    aes_init();
+#endif
+    return initWlan();
+}
+static __exit void tu_generic_wifi_exit_module(void)
+{
+#ifdef CONFIG_SSV_SUPPORT_AES_ASM
+    aes_fini();
+    sha1_mod_fini();
+#endif
+    msleep(100);
+    exitWlan();
+}
+EXPORT_SYMBOL(tu_generic_wifi_init_module);
+EXPORT_SYMBOL(tu_generic_wifi_exit_module);
+module_init(tu_generic_wifi_init_module);
+module_exit(tu_generic_wifi_exit_module);
+
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/drivers/net/wireless/ssv6x5x/ssv6x5x-wifi.cfg b/drivers/net/wireless/ssv6x5x/ssv6x5x-wifi.cfg
new file mode 100755
index 000000000..bab2f9f61
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/ssv6x5x-wifi.cfg
@@ -0,0 +1,121 @@
+############################################################
+# ROCKCHIP RK3X28 & RK322X
+# WIFI-CONFIGURATION
+##################################################
+
+# hw_mac = 00:a5:b5:30:36:20
+# hw_mac_2 = 00:a5:b5:30:36:21
+##################################################
+# Firmware setting
+# Priority.1 insmod parameter "cfgfirmwarepath"
+# Priority.2 firmware_path
+# Priority.3 default firmware
+##################################################
+firmware_path = /lib/firmware/
+
+############################################################
+# MAC address
+#
+# Priority 1. From wifi.cfg [ hw_mac & hw_mac_2 ]
+#
+# Priority 2. From e-fuse[ON/OFF switch by wifi.cfg]
+#
+# Priority 3. From insert module parameter
+#
+# Priority 4. From external file path
+#   path only support some special charater "_" ":" "/" "." "-"
+#
+# Priority 5. Default[Software mode]
+#
+#   0. => 00:33:33:33:33:33
+#   1. => Always random
+#   2. => First random and write to file[Default path mac_output_path]
+#
+############################################################
+#ignore_efuse_mac = 1
+#mac_address_path = /xxxx/xxxx
+#mac_address_mode = 2
+#mac_output_path = /data/wifimac
+
+##################################################
+# Hardware setting
+#
+#volt regulator(DCDC-0 LDO-1)
+#
+##################################################
+xtal_clock = 24
+volt_regulator = 1
+
+##################################################
+# Default channel after wifi on
+# value range: [1 ~ 14]
+##################################################
+#def_chan = 6
+##################################################
+# Hardware Capability Settings:
+##################################################
+hw_cap_ampdu_rx = on
+hw_cap_ampdu_tx = on
+hw_cap_tdls = on
+hw_cap_5ghz = on
+
+use_wpa2_only = 1
+##################################################
+# TX power level setting [0-14]
+# The larger the number the smaller the TX power
+# 0 - The maximum power
+# 1 level = -0.5db
+#
+# 6051Z .. 4 or 4
+# 6051Q .. 2 or 5
+# 6051P .. 0 or 0
+#
+##################################################
+wifi_tx_gain_level_b = 2
+wifi_tx_gain_level_gn = 5
+
+##################################################
+# Import extenal configuration(UP to 64 groups)
+# example:
+#    register = CE010010:91919191
+#    register = 00CC0010:00091919
+##################################################
+
+##################################################
+# The AP RSSI signal is less than -88dbm complement signal to -88dbm
+##################################################
+#beacon_rssi_minimal = 88
+
+##################################################
+# Direct Ack Threshold Settings:
+##################################################
+directly_ack_low_threshold = 64
+directly_ack_high_threshold = 512
+
+##################################################
+# txrxboost Threshold Settings:
+##################################################
+#txrxboost_low_threshold = 999
+#txrxboost_high_threshold = 999
+
+# Disable the p2p0 interface. We don't really need it for general purpose
+# uses, but can be enabled back if required.
+hw_cap_p2p = off
+
+online_reset = 0x00f
+
+#################################################
+#	DOMAIN_FCC = 0,
+#	DOMAIN_china,
+#	DOMAIN_ETSI,
+#	DOMAIN_Japan,
+#	DOMAIN_Japan2,
+#	DOMAIN_Israel,
+#	DOMAIN_Korea,
+#	DOMAIN_North_America,
+#	DOMAIN_Singapore,
+# DOMAIN_Taiwan,
+# DOMAIN_other = 0xff,
+################################################
+
+#	domain = 1
diff --git a/drivers/net/wireless/ssv6x5x/ssv6x5x.cfg b/drivers/net/wireless/ssv6x5x/ssv6x5x.cfg
new file mode 100755
index 000000000..bfbbf6338
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/ssv6x5x.cfg
@@ -0,0 +1,35 @@
+############################################################
+# RK322x
+############################################################
+
+ccflags-y += -DCONFIG_SSV_SUPPORT_ANDROID
+#ccflags-y += -DCONFIG_SSV_SUPPORT_AES_ASM
+ccflags-y += -DCONFIG_FW_ALIGNMENT_CHECK
+ccflags-y += -DCONFIG_PLATFORM_SDIO_OUTPUT_TIMING=3
+ccflags-y += -DCONFIG_PLATFORM_SDIO_BLOCK_SIZE=128
+ccflags-y += -DMULTI_THREAD_ENCRYPT
+ccflags-y += -DKTHREAD_BIND
+#ccflags-y += -DROCKCHIP_WIFI_AUTO_SUPPORT
+ccflags-y += -DCONFIG_SSV_RSSI
+ccflags-y += -DCONFIG_SSV_VENDOR_EXT_SUPPORT
+
+#
+##ccflags-y += -DCONFIG_SSV_SUPPORT_ANDROID
+#ccflags-y += -DCONFIG_SSV_BUILD_AS_ONE_KO
+##ccflags-y += -DCONFIG_SSV_SUPPORT_AES_ASM
+#ccflags-y += -DCONFIG_FW_ALIGNMENT_CHECK
+#ccflags-y += -DCONFIG_PLATFORM_SDIO_OUTPUT_TIMING=3
+#ccflags-y += -DCONFIG_PLATFORM_SDIO_BLOCK_SIZE=128
+##ccflags-y += -DMULTI_THREAD_ENCRYPT
+##ccflags-y += -DKTHREAD_BIND
+##ccflags-y += -DROCKCHIP_WIFI_AUTO_SUPPORT
+#ccflags-y += -DCONFIG_SSV_RSSI
+
+############################################################
+# Compiler path
+############################################################
+SSV_CROSS = $(ANDROID_BUILD_TOP)/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi-
+SSV_KERNEL_PATH = $(ANDROID_BUILD_TOP)/kernel
+SSV_ARCH = arm
+KMODDESTDIR = $(MODDESTDIR)
+
diff --git a/drivers/net/wireless/ssv6x5x/ssvcfg.sh b/drivers/net/wireless/ssv6x5x/ssvcfg.sh
new file mode 100755
index 000000000..98900f438
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/ssvcfg.sh
@@ -0,0 +1,35 @@
+#/bin/bash
+
+KVERSION="`uname -r`"
+kern_mod=/lib/modules/$KVERSION/kernel/drivers/net/wireless/ssv6200/ssvdevicetype.ko
+type_str=`lsmod | grep "ssvdevicetype"`
+cfg_file=sta.cfg
+if [ $# -ge 1 ]; then 
+    cfg_file=$1; 
+    echo Using configuration file $1
+else
+    echo Using default configuration file $cfg_file \($?\)
+fi
+cfg_cmds=(`cat sta.cfg  | grep '^[a-zA-Z0-9]' | sed 's/ //g'`)
+#echo ${#cfg_cmds[*]}
+#echo ${!cfg_cmds[*]}
+#echo ${cfg_cmds[1]}
+
+if [ "$type_str" != "" ]; then
+    #rmmod ssv6200_sdio
+    #rmmod ssv6200s_core
+    #rmmod ssv6200_hci
+    rmmod ssvdevicetype
+fi
+
+
+if [ -f $kern_mod ]; then
+    insmod $kern_mod stacfgpath="$cfg_file"
+    #insmod $kern_mod
+    #./cli cfg reset
+    #for cmd in ${cfg_cmds[*]}
+    #do
+	#./cli cfg `echo $cmd | sed 's/=/ = /g'`
+    #done
+fi
+
diff --git a/drivers/net/wireless/ssv6x5x/ssvdevice/Makefile b/drivers/net/wireless/ssv6x5x/ssvdevice/Makefile
new file mode 100755
index 000000000..e11de471f
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/ssvdevice/Makefile
@@ -0,0 +1,18 @@
+ifeq ($(KBUILD_TOP),)
+    ifneq ($(KBUILD_EXTMOD),)
+    KBUILD_DIR := $(KBUILD_EXTMOD)
+    else
+    KBUILD_DIR := $(PWD)
+    endif
+KBUILD_TOP := $(KBUILD_DIR)/../
+endif
+
+include $(KBUILD_TOP)/config.mak
+
+
+KMODULE_NAME=ssvdevicetype
+KERN_SRCS := ssvdevice.c
+KERN_SRCS += ssv_cmd.c
+
+
+include $(KBUILD_TOP)/rules.mak
diff --git a/drivers/net/wireless/ssv6x5x/ssvdevice/backup b/drivers/net/wireless/ssv6x5x/ssvdevice/backup
new file mode 100755
index 000000000..bd0a4f7ca
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/ssvdevice/backup
@@ -0,0 +1,18 @@
+obj-m     += ssvdevicetype.o
+
+ssvdevicetype-objs += ssvdevice.o
+
+ifndef ($(KBUILD_EXTMOD),)
+KDIR=/lib/modules/`uname -r`/build
+
+_all:
+	$(MAKE) -C $(KDIR) M=$(PWD) modules 2>&1 | tee make.log
+	
+clean:
+	$(MAKE) -C $(KDIR) M=$(PWD) clean
+	rm make.log
+	
+install:
+	$(MAKE) INSTALL_MOD_DIR=kernel/drivers/net/wireless/ssv6200 -C $(KDIR) M=$(PWD) modules_install
+
+endif
diff --git a/drivers/net/wireless/ssv6x5x/ssvdevice/ssv_cmd.c b/drivers/net/wireless/ssv6x5x/ssvdevice/ssv_cmd.c
new file mode 100644
index 000000000..809e51b4a
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/ssvdevice/ssv_cmd.c
@@ -0,0 +1,2268 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/version.h>
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,0)
+#include <linux/export.h>
+#else
+#include <linux/module.h>
+#endif
+#include <linux/platform_device.h>
+#include <linux/string.h>
+#include <linux/sched.h>
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,15,0)
+#include <linux/sched/prio.h>
+#elif LINUX_VERSION_CODE >= KERNEL_VERSION(3,9,0)
+#include <linux/sched/rt.h>
+#endif
+#include <ssv_conf_parser.h>
+#ifndef SSV_SUPPORT_HAL
+#include <ssv6200_reg.h>
+#endif
+#include <ssv6200.h>
+#include <hci/hctrl.h>
+#include <smac/dev.h>
+#include <hal.h>
+#include "ssv_cmd.h"
+#include <ssv_version.h>
+#include <linux_80211.h>
+#ifndef CONFIG_SSV_CABRIO_A
+#include <ssv6200_configuration.h>
+#endif
+#define SSV_CMD_PRINTF()
+struct ssv6xxx_dev_table {
+    u32 address;
+    u32 val;
+};
+EXPORT_SYMBOL(snprintf_res);
+#ifndef SSV_SUPPORT_HAL
+static bool ssv6xxx_dump_wsid(struct ssv_hw *sh)
+{
+    const u32 reg_wsid[]= { ADR_WSID0, ADR_WSID1 };
+    const u32 reg_wsid_tid0[]= { ADR_WSID0_TID0_RX_SEQ, ADR_WSID1_TID0_RX_SEQ };
+    const u32 reg_wsid_tid7[]= { ADR_WSID0_TID7_RX_SEQ, ADR_WSID1_TID7_RX_SEQ };
+    const u8 *op_mode_str[]= {"STA", "AP", "AD-HOC", "WDS"};
+    const u8 *ht_mode_str[]= {"Non-HT", "HT-MF", "HT-GF", "RSVD"};
+    u32 addr, regval;
+    int s;
+    struct ssv_cmd_data *cmd_data = &sh->sc->cmd_data;
+    for (s = 0; s < SSV_NUM_HW_STA; s++) {
+        if(SMAC_REG_READ(sh, reg_wsid[s], &regval));
+        snprintf_res(cmd_data, "==>WSID[%d]\n\tvalid[%d] qos[%d] op_mode[%s] ht_mode[%s]\n",
+                     s, regval&0x1, (regval>>1)&0x1, op_mode_str[((regval>>2)&3)], ht_mode_str[((regval>>4)&3)]);
+        if(SMAC_REG_READ(sh, reg_wsid[s]+4, &regval));
+        snprintf_res(cmd_data, "\tMAC[%02x:%02x:%02x:%02x:",
+                     (regval&0xff), ((regval>>8)&0xff), ((regval>>16)&0xff), ((regval>>24)&0xff));
+        if(SMAC_REG_READ(sh, reg_wsid[s]+8, &regval));
+        snprintf_res(cmd_data, "%02x:%02x]\n",
+                     (regval&0xff), ((regval>>8)&0xff));
+        for(addr = reg_wsid_tid0[s]; addr <= reg_wsid_tid7[s]; addr+=4) {
+            if(SMAC_REG_READ(sh, addr, &regval));
+            snprintf_res(cmd_data, "\trx_seq%d[%d]\n", ((addr-reg_wsid_tid0[s])>>2), ((regval)&0xffff));
+        }
+    }
+    return 0;
+}
+static bool ssv6xxx_dump_decision(struct ssv_hw *sh)
+{
+    u32 addr, regval;
+    int s;
+    struct ssv_cmd_data *cmd_data = &sh->sc->cmd_data;
+    snprintf_res(cmd_data, ">> Decision Table:\n");
+    for(s = 0, addr = ADR_MRX_FLT_TB0; s < 16; s++, addr+=4) {
+        if(SMAC_REG_READ(sh, addr, &regval));
+        snprintf_res(cmd_data, "   [%d]: ADDR[0x%08x] = 0x%08x\n",
+                     s, addr, regval);
+    }
+    snprintf_res(cmd_data, "\n\n>> Decision Mask:\n");
+    for (s = 0, addr = ADR_MRX_FLT_EN0; s < 9; s++, addr+=4) {
+        if(SMAC_REG_READ(sh, addr, &regval));
+        snprintf_res(cmd_data, "   [%d]: ADDR[0x%08x] = 0x%08x\n",
+                     s, addr, regval);
+    }
+    snprintf_res(cmd_data, "\n\n");
+    return 0;
+}
+static u32 ssv6xxx_get_ffout_cnt(u32 value, int tag)
+{
+    switch (tag) {
+    case M_ENG_CPU:
+        return ((value & FFO0_CNT_MSK) >> FFO0_CNT_SFT);
+    case M_ENG_HWHCI:
+        return ((value & FFO1_CNT_MSK) >> FFO1_CNT_SFT);
+    case M_ENG_ENCRYPT:
+        return ((value & FFO3_CNT_MSK) >> FFO3_CNT_SFT);
+    case M_ENG_MACRX:
+        return ((value & FFO4_CNT_MSK) >> FFO4_CNT_SFT);
+    case M_ENG_MIC:
+        return ((value & FFO5_CNT_MSK) >> FFO5_CNT_SFT);
+    case M_ENG_TX_EDCA0:
+        return ((value & FFO6_CNT_MSK) >> FFO6_CNT_SFT);
+    case M_ENG_TX_EDCA1:
+        return ((value & FFO7_CNT_MSK) >> FFO7_CNT_SFT);
+    case M_ENG_TX_EDCA2:
+        return ((value & FFO8_CNT_MSK) >> FFO8_CNT_SFT);
+    case M_ENG_TX_EDCA3:
+        return ((value & FFO9_CNT_MSK) >> FFO9_CNT_SFT);
+    case M_ENG_TX_MNG:
+        return ((value & FFO10_CNT_MSK) >> FFO10_CNT_SFT);
+    case M_ENG_ENCRYPT_SEC:
+        return ((value & FFO11_CNT_MSK) >> FFO11_CNT_SFT);
+    case M_ENG_MIC_SEC:
+        return ((value & FFO12_CNT_MSK) >> FFO12_CNT_SFT);
+    case M_ENG_TRASH_CAN:
+        return ((value & FFO15_CNT_MSK) >> FFO15_CNT_SFT);
+    default:
+        return 0;
+    }
+}
+static u32 ssv6xxx_get_in_ffcnt(u32 value, int tag)
+{
+    switch (tag) {
+    case M_ENG_CPU:
+        return ((value & FF0_CNT_MSK) >> FF0_CNT_SFT);
+    case M_ENG_HWHCI:
+        return ((value & FF1_CNT_MSK) >> FF1_CNT_SFT);
+    case M_ENG_ENCRYPT:
+        return ((value & FF3_CNT_MSK) >> FF3_CNT_SFT);
+    case M_ENG_MACRX:
+        return ((value & FF4_CNT_MSK) >> FF4_CNT_SFT);
+    case M_ENG_MIC:
+        return ((value & FF5_CNT_MSK) >> FF5_CNT_SFT);
+    case M_ENG_TX_EDCA0:
+        return ((value & FF6_CNT_MSK) >> FF6_CNT_SFT);
+    case M_ENG_TX_EDCA1:
+        return ((value & FF7_CNT_MSK) >> FF7_CNT_SFT);
+    case M_ENG_TX_EDCA2:
+        return ((value & FF8_CNT_MSK) >> FF8_CNT_SFT);
+    case M_ENG_TX_EDCA3:
+        return ((value & FF9_CNT_MSK) >> FF9_CNT_SFT);
+    case M_ENG_TX_MNG:
+        return ((value & FF10_CNT_MSK) >> FF10_CNT_SFT);
+    case M_ENG_ENCRYPT_SEC:
+        return ((value & FF11_CNT_MSK) >> FF11_CNT_SFT);
+    case M_ENG_MIC_SEC:
+        return ((value & FF12_CNT_MSK) >> FF12_CNT_SFT);
+    case M_ENG_TRASH_CAN:
+        return ((value & FF15_CNT_MSK) >> FF15_CNT_SFT);
+    default:
+        return 0;
+    }
+}
+static void ssv6xxx_read_ffout_cnt(struct ssv_hw *sh,
+                                   u32 *value, u32 *value1, u32 *value2)
+{
+    if(SMAC_REG_READ(sh, ADR_RD_FFOUT_CNT1, value));
+    if(SMAC_REG_READ(sh, ADR_RD_FFOUT_CNT2, value1));
+    if(SMAC_REG_READ(sh, ADR_RD_FFOUT_CNT3, value2));
+}
+static void ssv6xxx_read_in_ffcnt(struct ssv_hw *sh,
+                                  u32 *value, u32 *value1)
+{
+    if(SMAC_REG_READ(sh, ADR_RD_IN_FFCNT1, value));
+    if(SMAC_REG_READ(sh, ADR_RD_IN_FFCNT2, value1));
+}
+static void ssv6xxx_read_id_len_threshold(struct ssv_hw *sh,
+        u32 *tx_len, u32 *rx_len)
+{
+    u32 regval = 0;
+    if(SMAC_REG_READ(sh, ADR_ID_LEN_THREADSHOLD2, &regval));
+    *tx_len = ((regval & TX_ID_ALC_LEN_MSK) >> TX_ID_ALC_LEN_SFT);
+    *rx_len = ((regval & RX_ID_ALC_LEN_MSK) >> RX_ID_ALC_LEN_SFT);
+}
+static void ssv6xxx_read_tag_status(struct ssv_hw *sh,
+                                    u32 *ava_status)
+{
+    u32 regval = 0;
+    if(SMAC_REG_READ(sh, ADR_TAG_STATUS, &regval));
+    *ava_status = ((regval & AVA_TAG_MSK) >> AVA_TAG_SFT);
+}
+static void ssv6xxx_dump_mib_rx_phy(struct ssv_hw *sh)
+{
+    u32 value;
+    struct ssv_cmd_data *cmd_data = &sh->sc->cmd_data;
+    snprintf_res(cmd_data, "PHY B mode:\n");
+    snprintf_res(cmd_data, "%-10s\t\t%-10s\t\t%-10s\n", "CRC error","CCA","counter");
+    if(SMAC_REG_READ(sh, ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT, &value));
+    snprintf_res(cmd_data, "[%08x]\t\t", value & B_PACKET_ERR_CNT_MSK);
+    if(SMAC_REG_READ(sh, ADR_RX_11B_PKT_CCA_AND_PKT_CNT, &value));
+    snprintf_res(cmd_data, "[%08x]\t\t", (value & B_CCA_CNT_MSK) >> B_CCA_CNT_SFT);
+    snprintf_res(cmd_data, "[%08x]\t\t\n\n", value & B_PACKET_CNT_MSK);
+    snprintf_res(cmd_data, "PHY G/N mode:\n");
+    snprintf_res(cmd_data, "%-10s\t\t%-10s\t\t%-10s\n", "CRC error","CCA","counter");
+    if(SMAC_REG_READ(sh, ADR_RX_11GN_PKT_ERR_CNT, &value));
+    snprintf_res(cmd_data, "[%08x]\t\t", value & GN_PACKET_ERR_CNT_MSK);
+    if(SMAC_REG_READ(sh, ADR_RX_11GN_PKT_CCA_AND_PKT_CNT, &value));
+    snprintf_res(cmd_data, "[%08x]\t\t", (value & GN_CCA_CNT_MSK) >> GN_CCA_CNT_SFT);
+    snprintf_res(cmd_data, "[%08x]\t\t\n\n", value & GN_PACKET_CNT_MSK);
+}
+static void ssv6xxx_reset_mib_phy(struct ssv_hw *sh)
+{
+    if(SMAC_REG_WRITE(sh, ADR_RX_11B_PKT_STAT_EN, 0));
+    msleep(1);
+    if(SMAC_REG_WRITE(sh, ADR_RX_11B_PKT_STAT_EN, RG_PACKET_STAT_EN_11B_MSK));
+    if(SMAC_REG_WRITE(sh, ADR_RX_11GN_STAT_EN, 0));
+    msleep(1);
+    if(SMAC_REG_WRITE(sh, ADR_RX_11GN_STAT_EN, RG_PACKET_STAT_EN_11GN_MSK));
+    if(SMAC_REG_WRITE(sh, ADR_PHY_REG_20_MRX_CNT, 0));
+    msleep(1);
+    if(SMAC_REG_WRITE(sh, ADR_PHY_REG_20_MRX_CNT, RG_MRX_EN_CNT_RST_N_MSK));
+}
+static void ssv6xxx_reset_mib(struct ssv_hw *sh)
+{
+    if(SMAC_REG_WRITE(sh, ADR_MIB_EN, 0));
+    msleep(1);
+    if(SMAC_REG_WRITE(sh, ADR_MIB_EN, 0xffffffff));
+    ssv6xxx_reset_mib_phy(sh);
+}
+static void ssv6xxx_list_mib(struct ssv_hw *sh)
+{
+    u32 addr, value;
+    int i;
+    struct ssv_cmd_data *cmd_data = &sh->sc->cmd_data;
+    addr = MIB_REG_BASE;
+    for (i = 0; i < 120; i++, addr+=4) {
+        if(SMAC_REG_READ(sh, addr, &value));
+        snprintf_res(cmd_data, "%08x ", value);
+        if (((i+1) & 0x07) == 0)
+            snprintf_res(cmd_data, "\n");
+    }
+    snprintf_res(cmd_data, "\n");
+}
+static void ssv6xxx_dump_mib_rx(struct ssv_hw *sh)
+{
+    u32 value;
+    struct ssv_cmd_data *cmd_data = &sh->sc->cmd_data;
+    snprintf_res(cmd_data, "%-10s\t\t%-10s\t\t%-10s\t\t%-10s\n",
+                 "MRX_FCS_SUCC", "MRX_FCS_ERR", "MRX_ALC_FAIL", "MRX_MISS");
+    if(SMAC_REG_READ(sh, ADR_MRX_FCS_SUCC, &value));
+    snprintf_res(cmd_data, "[%08x]\t\t", value);
+    if(SMAC_REG_READ(sh, ADR_MRX_FCS_ERR, &value));
+    snprintf_res(cmd_data, "[%08x]\t\t", value);
+    if(SMAC_REG_READ(sh, ADR_MRX_ALC_FAIL, &value));
+    snprintf_res(cmd_data, "[%08x]\t\t", value);
+    if(SMAC_REG_READ(sh, ADR_MRX_MISS, &value));
+    snprintf_res(cmd_data, "[%08x]\n", value);
+    snprintf_res(cmd_data, "%-10s\t\t%-10s\t\t%-10s\t%-10s\n",
+                 "MRX_MB_MISS", "MRX_NIDLE_MISS", "DBG_LEN_ALC_FAIL", "DBG_LEN_CRC_FAIL");
+    if(SMAC_REG_READ(sh, ADR_MRX_MB_MISS, &value));
+    snprintf_res(cmd_data, "[%08x]\t\t", value);
+    if(SMAC_REG_READ(sh, ADR_MRX_NIDLE_MISS, &value));
+    snprintf_res(cmd_data, "[%08x]\t\t", value);
+    if(SMAC_REG_READ(sh, ADR_DBG_LEN_ALC_FAIL, &value));
+    snprintf_res(cmd_data, "[%08x]\t\t", value);
+    if(SMAC_REG_READ(sh, ADR_DBG_LEN_CRC_FAIL, &value));
+    snprintf_res(cmd_data, "[%08x]\n\n", value);
+    snprintf_res(cmd_data, "%-10s\t\t%-10s\t\t%-10s\t%-10s\n",
+                 "DBG_AMPDU_PASS", "DBG_AMPDU_FAIL", "ID_ALC_FAIL1", "ID_ALC_FAIL2");
+    if(SMAC_REG_READ(sh, ADR_DBG_AMPDU_PASS, &value));
+    snprintf_res(cmd_data, "[%08x]\t\t", value);
+    if(SMAC_REG_READ(sh, ADR_DBG_AMPDU_FAIL, &value));
+    snprintf_res(cmd_data, "[%08x]\t\t", value);
+    if(SMAC_REG_READ(sh, ADR_ID_ALC_FAIL1, &value));
+    snprintf_res(cmd_data, "[%08x]\t\t", value);
+    if(SMAC_REG_READ(sh, ADR_ID_ALC_FAIL2, &value));
+    snprintf_res(cmd_data, "[%08x]\n\n", value);
+    ssv6xxx_dump_mib_rx_phy(sh);
+}
+static void ssv6xxx_cmd_mib(struct ssv_softc *sc, int argc, char *argv[])
+{
+    struct ssv_cmd_data *cmd_data = &sc->cmd_data;
+    if ((argc == 2) && (!strcmp(argv[1], "reset"))) {
+        ssv6xxx_reset_mib(sc->sh);
+        snprintf_res(cmd_data, " => MIB reseted\n");
+    } else if ((argc == 2) && (!strcmp(argv[1], "list"))) {
+        ssv6xxx_list_mib(sc->sh);
+    } else if ((argc == 2) && (strcmp(argv[1], "rx") == 0)) {
+        ssv6xxx_dump_mib_rx(sc->sh);
+    } else {
+        snprintf_res(cmd_data, "mib [reset|list|rx]\n\n");
+    }
+}
+static void ssv6xxx_cmd_power_saving(struct ssv_softc *sc, int argc, char *argv[])
+{
+    struct ssv_cmd_data *cmd_data = &sc->cmd_data;
+    char *endp;
+    if ((argc == 2) && (argv[1])) {
+        sc->ps_aid = simple_strtoul(argv[1], &endp, 10);
+    } else {
+        snprintf_res(cmd_data, "ps [aid_value]\n\n");
+    }
+    ssv6xxx_trigger_pmu(sc);
+}
+static void ssv6xxx_get_rd_id_adr(u32 *id_base_address)
+{
+    id_base_address[0] = ADR_RD_ID0;
+    id_base_address[1] = ADR_RD_ID1;
+    id_base_address[2] = ADR_RD_ID2;
+    id_base_address[3] = ADR_RD_ID3;
+}
+static void ssv6xxx_txtput_set_desc(struct ssv_hw *sh, struct sk_buff *skb )
+{
+    struct ssv6200_tx_desc *tx_desc;
+    tx_desc = (struct ssv6200_tx_desc *)skb->data;
+    memset((void *)tx_desc, 0xff, sizeof(struct ssv6200_tx_desc));
+    tx_desc->len = skb->len;
+    tx_desc->c_type = M2_TXREQ;
+    tx_desc->fCmd = (M_ENG_CPU << 4) | M_ENG_HWHCI;
+    tx_desc->reason = ID_TRAP_SW_TXTPUT;
+}
+static void ssv6xxx_get_fw_version(struct ssv_hw *sh, u32 *regval)
+{
+    if(SMAC_REG_READ(sh, ADR_TX_SEG, regval));
+}
+static int ssv6xxx_auto_gen_nullpkt(struct ssv_hw *sh, int hwq)
+{
+    return -EOPNOTSUPP;
+}
+#endif
+struct sk_buff *ssvdevice_skb_alloc(s32 len)
+{
+    struct sk_buff *skb;
+    skb = __dev_alloc_skb(len + SSV6200_ALLOC_RSVD, GFP_KERNEL);
+    if (skb != NULL) {
+        skb_put(skb,0x20);
+        skb_pull(skb,0x20);
+    }
+    return skb;
+}
+void ssvdevice_skb_free(struct sk_buff *skb)
+{
+    dev_kfree_skb_any(skb);
+}
+static int ssv_cmd_help(struct ssv_softc *sc, int argc, char *argv[])
+{
+    extern struct ssv_cmd_table cmd_table[];
+    struct ssv_cmd_table *sc_tbl;
+    int total_cmd = 0;
+    struct ssv_cmd_data *cmd_data = &sc->cmd_data;
+    snprintf_res(cmd_data, "Usage:\n");
+    for (sc_tbl = &cmd_table[3]; sc_tbl->cmd; sc_tbl++) {
+        snprintf_res(cmd_data, "%-20s\t\t%s\n", (char*)sc_tbl->cmd, sc_tbl->usage);
+        total_cmd++;
+    }
+    snprintf_res(cmd_data, "Total CMDs: %x\n\nType cli help [CMD] for more detail command.\n\n", total_cmd);
+    return 0;
+}
+static int ssv_cmd_reg(struct ssv_softc *sc, int argc, char *argv[])
+{
+    u32 addr, value, count;
+    char *endp;
+    int s;
+#ifdef SSV_SUPPORT_HAL
+    int ret = 0;
+#endif
+    struct ssv_cmd_data *cmd_data = &sc->cmd_data;
+    if ((argc == 4) && (strcmp(argv[1], "w") == 0)) {
+        addr = simple_strtoul(argv[2], &endp, 16);
+        value = simple_strtoul(argv[3], &endp, 16);
+        if (SMAC_REG_WRITE(sc->sh, addr, value)) ;
+        snprintf_res(cmd_data, " => write [0x%08x]: 0x%08x\n", addr, value);
+        return 0;
+    } else if (((argc == 4) || (argc == 3)) && (strcmp(argv[1], "r") == 0)) {
+        count = (argc ==3 )? 1: simple_strtoul(argv[3], &endp, 10);
+        addr = simple_strtoul(argv[2], &endp, 16);
+        snprintf_res(cmd_data, "ADDRESS: 0x%08x\n", addr);
+        for(s = 0; s < count; s++, addr += 4) {
+            if (SMAC_REG_READ(sc->sh, addr, &value));
+            snprintf_res(cmd_data, "%08x ", value);
+            if (((s+1) & 0x07) == 0) {
+                snprintf_res(cmd_data, "\n");
+            }
+        }
+        snprintf_res(cmd_data, "\n");
+        return 0;
+    }
+#ifdef SSV_SUPPORT_HAL
+    else if (argc == 5 && strcmp(argv[1], "bw")==0) {
+        u32 addr_list[8],value_list[8];
+        addr = simple_strtoul(argv[2], &endp, 16);
+        value = simple_strtoul(argv[3], &endp, 16);
+        count = simple_strtoul(argv[4], &endp, 16);
+        for (s=0; s<count; s++) {
+            addr_list[s] = addr+4*s;
+            value_list[s] = value;
+        }
+        ret = HAL_BURST_WRITE_REG(sc->sh, addr_list, value_list, count);
+        if (ret >= 0) {
+            snprintf_res(cmd_data, "  ==> write done.\n");
+            return 0;
+        } else if (ret == -EOPNOTSUPP) {
+            snprintf_res(cmd_data, "Does not support this command!\n");
+            return 0;
+        }
+    } else if (argc == 4 && strcmp(argv[1], "br")==0) {
+        u32 addr_list[8],value_list[8];
+        addr = simple_strtoul(argv[2], &endp, 16);
+        count = simple_strtoul(argv[3], &endp, 16);
+        for (s=0; s<count; s++)
+            addr_list[s] = addr+4*s;
+        ret = HAL_BURST_READ_REG(sc->sh, addr_list, value_list, count);
+        if (ret >= 0) {
+            snprintf_res(cmd_data, "ADDRESS:   0x%x\n", addr);
+            snprintf_res(cmd_data, "REG-COUNT: %d\n", count);
+            for (s=0; s<count; s++)
+                snprintf_res(cmd_data, "addr %x ==> %x\n", addr_list[s], value_list[s]);
+            return 0;
+        } else if (ret == -EOPNOTSUPP) {
+            snprintf_res(cmd_data, "Does not support this command!\n");
+            return 0;
+        }
+    }
+#endif
+    else {
+        snprintf_res(cmd_data, "reg [r|w] [address] [value|word-count]\n\n");
+#ifdef SSV_SUPPORT_HAL
+        snprintf_res(cmd_data, "reg [br] [address] [word-count]\n\n");
+        snprintf_res(cmd_data, "reg [bw] [address] [value] [word-count]\n\n");
+#endif
+        return 0;
+    }
+    return -1;
+}
+struct ssv6xxx_cfg tu_ssv_cfg;
+EXPORT_SYMBOL(tu_ssv_cfg);
+#if 0
+static int __string2s32(u8 *val_str, void *val)
+{
+    char *endp;
+    int base=10;
+    if (val_str[0]=='0' && ((val_str[1]=='x')||(val_str[1]=='X')))
+        base = 16;
+    *(int *)val = simple_strtoul(val_str, &endp, base);
+    return 0;
+}
+#endif
+static int __string2bool(u8 *u8str, void *val, u32 arg)
+{
+    char *endp;
+    *(u8 *)val = !!simple_strtoul(u8str, &endp, 10);
+    return 0;
+}
+static int __string2u32(u8 *u8str, void *val, u32 arg)
+{
+    char *endp;
+    int base=10;
+    if (u8str[0]=='0' && ((u8str[1]=='x')||(u8str[1]=='X')))
+        base = 16;
+    *(u32 *)val = simple_strtoul(u8str, &endp, base);
+    return 0;
+}
+static int __string2flag32(u8 *flag_str, void *flag, u32 arg)
+{
+    u32 *val=(u32 *)flag;
+    if (arg >= (sizeof(u32)<<3))
+        return -1;
+    if (strcmp(flag_str, "on")==0) {
+        *val |= (1<<arg);
+        return 0;
+    }
+    if (strcmp(flag_str, "off")==0) {
+        *val &= ~(1<<arg);
+        return 0;
+    }
+    return -1;
+}
+static int __string2mac(u8 *mac_str, void *val, u32 arg)
+{
+    int s, macaddr[6];
+    u8 *mac=(u8 *)val;
+    s = sscanf(mac_str, "%02x:%02x:%02x:%02x:%02x:%02x",
+               &macaddr[0], &macaddr[1], &macaddr[2],
+               &macaddr[3], &macaddr[4], &macaddr[5]);
+    if (s != 6)
+        return -1;
+    mac[0] = (u8)macaddr[0], mac[1] = (u8)macaddr[1];
+    mac[2] = (u8)macaddr[2], mac[3] = (u8)macaddr[3];
+    mac[4] = (u8)macaddr[4], mac[5] = (u8)macaddr[5];
+    return 0;
+}
+static int __string2str(u8 *path, void *val, u32 arg)
+{
+    u8 *temp=(u8 *)val;
+    sprintf(temp,"%s",path);
+    return 0;
+}
+static int __string2configuration(u8 *mac_str, void *val, u32 arg)
+{
+    unsigned int address,value;
+    int i;
+    i = sscanf(mac_str, "%08x:%08x", &address, &value);
+    if (i != 2)
+        return -1;
+    for(i=0; i<EXTERNEL_CONFIG_SUPPORT; i++) {
+        if(tu_ssv_cfg.configuration[i][0] == 0x0) {
+            tu_ssv_cfg.configuration[i][0] = address;
+            tu_ssv_cfg.configuration[i][1] = value;
+            return 0;
+        }
+    }
+    return 0;
+}
+struct ssv6xxx_cfg_cmd_table tu_cfg_cmds[] = {
+    { "hw_mac", (void *)&tu_ssv_cfg.maddr[0][0], 0, __string2mac, NULL},
+    { "hw_mac_2", (void *)&tu_ssv_cfg.maddr[1][0], 0, __string2mac, NULL},
+    { "def_chan", (void *)&tu_ssv_cfg.def_chan, 0, __string2u32, "6"},
+    { "hw_cap_ht", (void *)&tu_ssv_cfg.hw_caps, 0, __string2flag32, "on"},
+    { "hw_cap_gf", (void *)&tu_ssv_cfg.hw_caps, 1, __string2flag32, "off"},
+    { "hw_cap_2ghz", (void *)&tu_ssv_cfg.hw_caps, 2, __string2flag32, "on"},
+    { "hw_cap_5ghz", (void *)&tu_ssv_cfg.hw_caps, 3, __string2flag32, "off"},
+    { "hw_cap_security", (void *)&tu_ssv_cfg.hw_caps, 4, __string2flag32, "on"},
+    { "hw_cap_sgi", (void *)&tu_ssv_cfg.hw_caps, 5, __string2flag32, "on"},
+    { "hw_cap_ht40", (void *)&tu_ssv_cfg.hw_caps, 6, __string2flag32, "on"},
+    { "hw_cap_ap", (void *)&tu_ssv_cfg.hw_caps, 7, __string2flag32, "on"},
+    { "hw_cap_p2p", (void *)&tu_ssv_cfg.hw_caps, 8, __string2flag32, "on"},
+    { "hw_cap_ampdu_rx", (void *)&tu_ssv_cfg.hw_caps, 9, __string2flag32, "on"},
+    { "hw_cap_ampdu_tx", (void *)&tu_ssv_cfg.hw_caps, 10, __string2flag32, "on"},
+    { "hw_cap_tdls", (void *)&tu_ssv_cfg.hw_caps, 11, __string2flag32, "off"},
+    { "hw_cap_stbc", (void *)&tu_ssv_cfg.hw_caps, 12, __string2flag32, "on"},
+    { "hw_cap_hci_rx_aggr", (void *)&tu_ssv_cfg.hw_caps, 13, __string2flag32, "on"},
+    { "hw_beacon", (void *)&tu_ssv_cfg.hw_caps, 14, __string2flag32, "on"},
+    { "use_wpa2_only", (void *)&tu_ssv_cfg.use_wpa2_only, 0, __string2u32, NULL},
+    { "wifi_tx_gain_level_gn",(void *)&tu_ssv_cfg.wifi_tx_gain_level_gn, 0, __string2u32, NULL},
+    { "wifi_tx_gain_level_b", (void *)&tu_ssv_cfg.wifi_tx_gain_level_b, 0, __string2u32, NULL},
+    { "xtal_clock", (void *)&tu_ssv_cfg.crystal_type, 0, __string2u32, "24"},
+    { "volt_regulator", (void *)&tu_ssv_cfg.volt_regulator, 0, __string2u32, "0"},
+    { "firmware_path", (void *)&tu_ssv_cfg.firmware_path[0], 0, __string2str, NULL},
+    { "flash_bin_path", (void *)&tu_ssv_cfg.flash_bin_path[0], 0, __string2str, NULL},
+    { "mac_address_path", (void *)&tu_ssv_cfg.mac_address_path[0], 0, __string2str, NULL},
+    { "mac_output_path", (void *)&tu_ssv_cfg.mac_output_path[0], 0, __string2str, NULL},
+    { "ignore_efuse_mac", (void *)&tu_ssv_cfg.ignore_efuse_mac, 0, __string2u32, NULL},
+    { "efuse_rate_gain_mask", (void *)&tu_ssv_cfg.efuse_rate_gain_mask, 0, __string2u32, "0x1"},
+    { "mac_address_mode", (void *)&tu_ssv_cfg.mac_address_mode, 0, __string2u32, NULL},
+    { "register", NULL, 0, __string2configuration, NULL},
+    { "beacon_rssi_minimal", (void *)&tu_ssv_cfg.beacon_rssi_minimal, 0, __string2u32, NULL},
+    { "force_chip_identity", (void *)&tu_ssv_cfg.force_chip_identity, 0, __string2u32, NULL},
+    { "external_firmware_name", (void *)&tu_ssv_cfg.external_firmware_name[0], 0, __string2str, NULL},
+    { "ignore_firmware_version", (void *)&tu_ssv_cfg.ignore_firmware_version, 0, __string2u32, NULL},
+    { "use_sw_cipher", (void *)&tu_ssv_cfg.use_sw_cipher, 0, __string2u32, NULL},
+    { "rc_ht_support_cck", (void *)&tu_ssv_cfg.rc_ht_support_cck, 0, __string2u32, "1"},
+    { "auto_rate_enable", (void *)&tu_ssv_cfg.auto_rate_enable, 0, __string2u32, "1"},
+    { "rc_rate_idx_set", (void *)&tu_ssv_cfg.rc_rate_idx_set, 0, __string2u32, "0x7777"},
+    { "rc_retry_set", (void *)&tu_ssv_cfg.rc_retry_set, 0, __string2u32, "0x4444"},
+    { "rc_mf", (void *)&tu_ssv_cfg.rc_mf, 0, __string2u32, NULL},
+    { "rc_long_short", (void *)&tu_ssv_cfg.rc_long_short, 0, __string2u32, NULL},
+    { "rc_ht40", (void *)&tu_ssv_cfg.rc_ht40, 0, __string2u32, NULL},
+    { "rc_phy_mode", (void *)&tu_ssv_cfg.rc_phy_mode, 0, __string2u32, "3"},
+    { "tx_id_threshold", (void *)&tu_ssv_cfg.tx_id_threshold, 0, __string2u32, NULL},
+    { "tx_page_threshold", (void *)&tu_ssv_cfg.tx_page_threshold, 0, __string2u32, NULL},
+    { "max_rx_aggr_size", (void *)&tu_ssv_cfg.max_rx_aggr_size, 0, __string2u32, "64"},
+    { "online_reset", (void *)&tu_ssv_cfg.online_reset, 0, __string2u32, "0x00f"},
+    { "rx_burstread", (void *)&tu_ssv_cfg.rx_burstread, 0, __string2bool, "0"},
+    { "hw_rx_agg_cnt", (void *)&tu_ssv_cfg.hw_rx_agg_cnt, 0, __string2u32, "3"},
+    { "hw_rx_agg_method_3", (void *)&tu_ssv_cfg.hw_rx_agg_method_3, 0, __string2bool, "0"},
+    { "hw_rx_agg_timer_reload", (void *)&tu_ssv_cfg.hw_rx_agg_timer_reload, 0, __string2u32, "20"},
+    { "usb_hw_resource", (void *)&tu_ssv_cfg.usb_hw_resource, 0, __string2u32, "0"},
+    { "tx_stuck_detect", (void *)&tu_ssv_cfg.tx_stuck_detect, 0, __string2bool, "0"},
+    { "clk_src_80m", (void *)&tu_ssv_cfg.clk_src_80m, 0, __string2bool, "1"},
+    { "rts_thres_len", (void *)&tu_ssv_cfg.rts_thres_len, 0, __string2u32, "0"},
+    { "cci", (void *)&tu_ssv_cfg.cci, 0, __string2u32, "0x19"},
+    { "bk_txq_size", (void *)&tu_ssv_cfg.bk_txq_size, 0, __string2u32, "6"},
+    { "be_txq_size", (void *)&tu_ssv_cfg.be_txq_size, 0, __string2u32, "10"},
+    { "vi_txq_size", (void *)&tu_ssv_cfg.vi_txq_size, 0, __string2u32, "10"},
+    { "vo_txq_size", (void *)&tu_ssv_cfg.vo_txq_size, 0, __string2u32, "8"},
+    { "manage_txq_size", (void *)&tu_ssv_cfg.manage_txq_size, 0, __string2u32, "8"},
+    { "aggr_size_sel_pr", (void *)&tu_ssv_cfg.aggr_size_sel_pr, 0, __string2u32, "95"},
+    { "aging_period", (void *)&tu_ssv_cfg.rc_setting.aging_period,0, __string2u32, "2000"},
+    { "target_success_67", (void *)&tu_ssv_cfg.rc_setting.target_success_67, 0, __string2u32, "55"},
+    { "target_success_5", (void *)&tu_ssv_cfg.rc_setting.target_success_5, 0, __string2u32, "78"},
+    { "target_success_4", (void *)&tu_ssv_cfg.rc_setting.target_success_4, 0, __string2u32, "70"},
+    { "target_success", (void *)&tu_ssv_cfg.rc_setting.target_success, 0, __string2u32, "50"},
+    { "up_pr", (void *)&tu_ssv_cfg.rc_setting.up_pr, 0, __string2u32, "70"},
+    { "up_pr3", (void *)&tu_ssv_cfg.rc_setting.up_pr3, 0, __string2u32, "85"},
+    { "up_pr4", (void *)&tu_ssv_cfg.rc_setting.up_pr4, 0, __string2u32, "97"},
+    { "up_pr5", (void *)&tu_ssv_cfg.rc_setting.up_pr5, 0, __string2u32, "70"},
+    { "up_pr6", (void *)&tu_ssv_cfg.rc_setting.up_pr6, 0, __string2u32, "70"},
+    { "forbid", (void *)&tu_ssv_cfg.rc_setting.forbid, 0, __string2u32, "0"},
+    { "forbid3", (void *)&tu_ssv_cfg.rc_setting.forbid3, 0, __string2u32, "0"},
+    { "forbid4", (void *)&tu_ssv_cfg.rc_setting.forbid4, 0, __string2u32, "350"},
+    { "forbid5", (void *)&tu_ssv_cfg.rc_setting.forbid5, 0, __string2u32, "100"},
+    { "forbid6", (void *)&tu_ssv_cfg.rc_setting.forbid6, 0, __string2u32, "0"},
+    { "sample_pr_4", (void *)&tu_ssv_cfg.rc_setting.sample_pr_4, 0, __string2u32, "70"},
+    { "sample_pr_5", (void *)&tu_ssv_cfg.rc_setting.sample_pr_5, 0, __string2u32, "85"},
+    { "sample_pr_force", (void *)&tu_ssv_cfg.rc_setting.force_sample_pr, 0, __string2u32, "40"},
+    { "greentx", (void *)&tu_ssv_cfg.greentx, 0, __string2u32, "0x119"},
+    { "gt_stepsize", (void *)&tu_ssv_cfg.gt_stepsize, 0, __string2u32, "3"},
+    { "gt_max_attenuation", (void *)&tu_ssv_cfg.gt_max_attenuation, 0, __string2u32, "15"},
+    { "autosgi", (void *)&tu_ssv_cfg.auto_sgi, 0, __string2u32, "0x1"},
+    { "directly_ack_low_threshold",(void *)&tu_ssv_cfg.directly_ack_low_threshold, 0, __string2u32, "64"},
+    { "directly_ack_high_threshold",(void *)&tu_ssv_cfg.directly_ack_high_threshold, 0, __string2u32, "1024"},
+    { "txrxboost_prio", (void *)&tu_ssv_cfg.txrxboost_prio, 0, __string2u32, "20"},
+    { "txrxboost_low_threshold",(void *)&tu_ssv_cfg.txrxboost_low_threshold, 0, __string2u32, "64"},
+    { "txrxboost_high_threshold",(void *)&tu_ssv_cfg.txrxboost_high_threshold, 0, __string2u32, "256"},
+    { "rx_threshold", (void *)&tu_ssv_cfg.rx_threshold, 0, __string2u32, "64"},
+    { "force_xtal_fo", (void *)&tu_ssv_cfg.force_xtal_fo, 0, __string2u32, NULL},
+    { "disable_dpd", (void *)&tu_ssv_cfg.disable_dpd, 0, __string2u32, "0"},
+    { "mic_err_notify", (void *)&tu_ssv_cfg.mic_err_notify, 0, __string2u32, "0"},
+    { "domain", (void *)&tu_ssv_cfg.domain, 0xff, __string2u32, NULL},
+    { NULL, NULL, 0, NULL, NULL},
+};
+EXPORT_SYMBOL(tu_cfg_cmds);
+static int ssv_cmd_cfg(struct ssv_softc *sc, int argc, char *argv[])
+{
+    int s;
+    struct ssv_cmd_data *cmd_data = &sc->cmd_data;
+    if ((argc == 2) && (strcmp(argv[1], "reset") == 0)) {
+        memset(&tu_ssv_cfg, 0, sizeof(tu_ssv_cfg));
+        return 0;
+    } else if ((argc == 2) && (strcmp(argv[1], "show") == 0)) {
+        snprintf_res(cmd_data, ">> ssv6xxx config:\n");
+        snprintf_res(cmd_data, "    hw_caps = 0x%08x\n", tu_ssv_cfg.hw_caps);
+        snprintf_res(cmd_data, "    def_chan = %d\n", tu_ssv_cfg.def_chan);
+        snprintf_res(cmd_data, "    wifi_tx_gain_level_gn = %d\n", tu_ssv_cfg.wifi_tx_gain_level_gn);
+        snprintf_res(cmd_data, "    wifi_tx_gain_level_b = %d\n", tu_ssv_cfg.wifi_tx_gain_level_b);
+        snprintf_res(cmd_data, "    sta-mac = %02x:%02x:%02x:%02x:%02x:%02x",
+                     tu_ssv_cfg.maddr[0][0], tu_ssv_cfg.maddr[0][1], tu_ssv_cfg.maddr[0][2],
+                     tu_ssv_cfg.maddr[0][3], tu_ssv_cfg.maddr[0][4], tu_ssv_cfg.maddr[0][5]);
+        snprintf_res(cmd_data, "\n");
+        return 0;
+    }
+    if (argc != 4)
+        return -1;
+    for(s = 0; tu_cfg_cmds[s].cfg_cmd != NULL; s++) {
+        if (strcmp(tu_cfg_cmds[s].cfg_cmd, argv[1]) == 0) {
+            tu_cfg_cmds[s].translate_func(argv[3],
+                                          tu_cfg_cmds[s].var, tu_cfg_cmds[s].arg);
+            snprintf_res(cmd_data, "");
+            return 0;
+        }
+    }
+    return -1;
+}
+#ifndef SSV_SUPPORT_HAL
+void *ssv_dbg_phy_table = NULL;
+EXPORT_SYMBOL(ssv_dbg_phy_table);
+u32 ssv_dbg_phy_len = 0;
+EXPORT_SYMBOL(ssv_dbg_phy_len);
+void *ssv_dbg_rf_table = NULL;
+EXPORT_SYMBOL(ssv_dbg_rf_table);
+u32 ssv_dbg_rf_len = 0;
+EXPORT_SYMBOL(ssv_dbg_rf_len);
+#endif
+void snprintf_res(struct ssv_cmd_data *cmd_data, const char *fmt, ... )
+{
+    char *buf_head;
+    int buf_left;
+    va_list args;
+    char *ssv6xxx_result_buf = cmd_data->ssv6xxx_result_buf;
+    ssv6xxx_result_buf = cmd_data->ssv6xxx_result_buf;
+    if (cmd_data->rsbuf_len >= (cmd_data->rsbuf_size -1))
+        return;
+    buf_head = ssv6xxx_result_buf + cmd_data->rsbuf_len;
+    buf_left = cmd_data->rsbuf_size - cmd_data->rsbuf_len;
+    va_start(args, fmt);
+    cmd_data->rsbuf_len += vsnprintf(buf_head, buf_left, fmt, args);
+    va_end(args);
+}
+static void _dump_sta_info (struct ssv_softc *sc,
+                            struct ssv_vif_info *vif_info,
+                            struct ssv_sta_info *sta_info,
+                            int sta_idx)
+{
+    struct ssv_sta_priv_data *priv_sta = (struct ssv_sta_priv_data *)sta_info->sta->drv_priv;
+    struct ssv_cmd_data *cmd_data = &sc->cmd_data;
+    if ((sta_info->s_flags & STA_FLAG_VALID) == 0) {
+        snprintf_res(cmd_data,
+                     "        Station %d: %d is not valid\n",
+                     sta_idx, priv_sta->sta_idx);
+    } else {
+        snprintf_res(cmd_data,
+                     "        Station %d: %d\n"
+                     "             Address: %02X:%02X:%02X:%02X:%02X:%02X\n"
+                     "             WISD: %d\n"
+                     "             AID: %d\n",
+                     sta_idx, priv_sta->sta_idx,
+                     sta_info->sta->addr[0], sta_info->sta->addr[1], sta_info->sta->addr[2],
+                     sta_info->sta->addr[3], sta_info->sta->addr[4], sta_info->sta->addr[5],
+                     sta_info->hw_wsid, sta_info->aid);
+    }
+}
+void ssv6xxx_dump_sta_info (struct ssv_softc *sc)
+{
+    int j, sta_idx = 0;
+    struct ssv_cmd_data *cmd_data = &sc->cmd_data;
+    snprintf_res(cmd_data, "  >>>> bcast queue len[%d]\n", sc->bcast_txq.cur_qsize);
+    for (j = 0; j < SSV6200_MAX_VIF; j++) {
+        struct ieee80211_vif *vif = sc->vif_info[j].vif;
+        struct ssv_vif_priv_data *priv_vif;
+        struct ssv_sta_priv_data *sta_priv_iter;
+        if (vif == NULL) {
+            snprintf_res(cmd_data, "    VIF: %d is not used.\n", j);
+            continue;
+        }
+        snprintf_res(cmd_data,
+                     "    VIF: %d - [%02X:%02X:%02X:%02X:%02X:%02X] type[%d] p2p[%d] p2p_status[%d] channel[%d]\n", j,
+                     vif->addr[0], vif->addr[1], vif->addr[2],
+                     vif->addr[3], vif->addr[4], vif->addr[5], vif->type, vif->p2p, sc->p2p_status, sc->hw_chan);
+        priv_vif = (struct ssv_vif_priv_data *)(vif->drv_priv);
+        snprintf_res(cmd_data,
+                     "           - sta asleep mask[%08X]\n", priv_vif->sta_asleep_mask);
+        list_for_each_entry(sta_priv_iter, &priv_vif->sta_list, list) {
+            if ((sc->sta_info[sta_priv_iter->sta_idx].s_flags & STA_FLAG_VALID) == 0) {
+                snprintf_res(cmd_data, "    STA: %d  is not valid.\n", sta_idx);
+                continue;
+            }
+            _dump_sta_info(sc, &sc->vif_info[priv_vif->vif_idx],
+                           &sc->sta_info[sta_priv_iter->sta_idx], sta_idx);
+            sta_idx++;
+        }
+    }
+}
+static int ssv_cmd_sta(struct ssv_softc *sc, int argc, char *argv[])
+{
+    if ((argc >= 2) && (strcmp(argv[1], "show") == 0))
+        ssv6xxx_dump_sta_info(sc);
+    else
+        snprintf_res(&sc->cmd_data, "sta show\n\n");
+    return 0;
+}
+static void ssv_cmd_get_chip_id(struct ssv_softc *sc, char *chip_id)
+{
+#ifdef SSV_SUPPORT_HAL
+    HAL_GET_CHIP_ID(sc->sh);
+    strcpy(chip_id, sc->sh->chip_id);
+#else
+    u32 regval;
+    if (SMAC_REG_READ(sc->sh, ADR_CHIP_ID_3, &regval));
+    *((u32 *)&chip_id[0]) = __be32_to_cpu(regval);
+    if (SMAC_REG_READ(sc->sh, ADR_CHIP_ID_2, &regval));
+    *((u32 *)&chip_id[4]) = __be32_to_cpu(regval);
+    if (SMAC_REG_READ(sc->sh, ADR_CHIP_ID_1, &regval));
+    *((u32 *)&chip_id[8]) = __be32_to_cpu(regval);
+    if (SMAC_REG_READ(sc->sh, ADR_CHIP_ID_0, &regval));
+    *((u32 *)&chip_id[12]) = __be32_to_cpu(regval);
+    chip_id[12+sizeof(u32)] = 0;
+#endif
+}
+static bool ssv6xxx_dump_cfg(struct ssv_hw *sh)
+{
+    struct ssv_cmd_data *cmd_data = &sh->sc->cmd_data;
+    snprintf_res(cmd_data, "\n>> Current Configuration:\n\n");
+    snprintf_res(cmd_data, "  hw_mac:                   %pM\n", sh->cfg.maddr[0]);
+    snprintf_res(cmd_data, "  hw_mac2:                  %pM\n", sh->cfg.maddr[1]);
+    snprintf_res(cmd_data, "  def_chan:                 %d\n", sh->cfg.def_chan);
+    snprintf_res(cmd_data, "  hw_caps:                  0x%x\n", sh->cfg.hw_caps);
+    snprintf_res(cmd_data, "  use_wpa2_only:            %d\n", sh->cfg.use_wpa2_only);
+    snprintf_res(cmd_data, "  wifi_tx_gain_level_gn:    %d\n", sh->cfg.wifi_tx_gain_level_gn);
+    snprintf_res(cmd_data, "  wifi_tx_gain_level_b:     %d\n", sh->cfg.wifi_tx_gain_level_b);
+    snprintf_res(cmd_data, "  xtal_clock:               %d\n", sh->cfg.crystal_type);
+    snprintf_res(cmd_data, "  volt_regulator:           %d\n", sh->cfg.volt_regulator);
+    snprintf_res(cmd_data, "  firmware_path:            %s\n", sh->cfg.firmware_path);
+    snprintf_res(cmd_data, "  mac_address_path:         %s\n", sh->cfg.mac_address_path);
+    snprintf_res(cmd_data, "  mac_output_path:          %s\n", sh->cfg.mac_output_path);
+    snprintf_res(cmd_data, "  ignore_efuse_mac:         %d\n", sh->cfg.ignore_efuse_mac);
+    snprintf_res(cmd_data, "  mac_address_mode:         %d\n", sh->cfg.mac_address_mode);
+    snprintf_res(cmd_data, "  beacon_rssi_minimal:      %d\n", sh->cfg.beacon_rssi_minimal);
+    snprintf_res(cmd_data, "  force_chip_identity:      0x%x\n", sh->cfg.force_chip_identity);
+    snprintf_res(cmd_data, "  external_firmware_name:   %s\n", sh->cfg.external_firmware_name);
+    snprintf_res(cmd_data, "  ignore_firmware_version:  %d\n", sh->cfg.ignore_firmware_version);
+    snprintf_res(cmd_data, "  auto_rate_enable:         %d\n", sh->cfg.auto_rate_enable);
+    snprintf_res(cmd_data, "  rc_rate_idx_set:          0x%x\n", sh->cfg.rc_rate_idx_set);
+    snprintf_res(cmd_data, "  rc_retry_set:             0x%x\n", sh->cfg.rc_retry_set);
+    snprintf_res(cmd_data, "  rc_mf:                    %d\n", sh->cfg.rc_mf);
+    snprintf_res(cmd_data, "  rc_long_short:            %d\n", sh->cfg.rc_long_short);
+    snprintf_res(cmd_data, "  rc_ht40:                  %d\n", sh->cfg.rc_ht40);
+    snprintf_res(cmd_data, "  rc_phy_mode:              %d\n", sh->cfg.rc_phy_mode);
+    snprintf_res(cmd_data, "  cci:                      %d\n", sh->cfg.cci);
+#ifdef SSV_SUPPORT_HAL
+    snprintf_res(cmd_data, "  hwqlimit(BK queue):        %d\n", sh->cfg.bk_txq_size);
+    snprintf_res(cmd_data, "  hwqlimit(BE queue):        %d\n", sh->cfg.be_txq_size);
+    snprintf_res(cmd_data, "  hwqlimit(VI queue):        %d\n", sh->cfg.vi_txq_size);
+    snprintf_res(cmd_data, "  hwqlimit(VO queue):        %d\n", sh->cfg.vo_txq_size);
+    snprintf_res(cmd_data, "  hwqlimit(MNG queue):       %d\n", sh->cfg.manage_txq_size);
+#endif
+    snprintf_res(cmd_data, "\n\n");
+    return 0;
+}
+static int ssv_cmd_dump(struct ssv_softc *sc, int argc, char *argv[])
+{
+#ifndef SSV_SUPPORT_HAL
+    u32 regval;
+    int s;
+#endif
+    struct ssv_cmd_data *cmd_data = &sc->cmd_data;
+    if (argc != 2) {
+        snprintf_res(cmd_data, "dump [wsid|decision|phy-reg|rf-reg|cfg]\n");
+        return 0;
+    }
+    if (strcmp(argv[1], "wsid") == 0) {
+        return SSV_DUMP_WSID(sc->sh);
+    }
+    if (strcmp(argv[1], "decision") == 0 ) {
+        return SSV_DUMP_DECISION(sc->sh);
+    }
+    if (strcmp(argv[1], "phy-info") == 0) {
+        return 0;
+    }
+    if (strcmp(argv[1], "phy-reg") == 0) {
+#ifdef SSV_SUPPORT_HAL
+        return HAL_DUMP_PHY_REG(sc->sh);
+#else
+        int length;
+        struct ssv6xxx_dev_table *raw;
+        raw = (struct ssv6xxx_dev_table *) ssv_dbg_phy_table;
+        length = ssv_dbg_phy_len;
+        snprintf_res(cmd_data, ">> PHY Register Table:\n");
+        for(s = 0; s < length; s++, raw++) {
+            if(SMAC_REG_READ(sc->sh, raw->address, &regval));
+            snprintf_res(cmd_data, "   ADDR[0x%08x] = 0x%08x\n",
+                         raw->address, regval);
+        }
+        snprintf_res(cmd_data, "\n\n");
+        return 0;
+#endif
+    }
+    if (strcmp(argv[1], "rf-reg") == 0) {
+#ifdef SSV_SUPPORT_HAL
+        return HAL_DUMP_RF_REG(sc->sh);
+#else
+        int length;
+        struct ssv6xxx_dev_table *raw;
+        raw = (struct ssv6xxx_dev_table *)ssv_dbg_rf_table;
+        length = ssv_dbg_rf_len;
+        snprintf_res(cmd_data, ">> RF Register Table:\n");
+        for(s = 0; s < length ; s++, raw++) {
+            if (SMAC_REG_READ(sc->sh, raw->address, &regval));
+            snprintf_res(cmd_data, "   ADDR[0x%08x] = 0x%08x\n",
+                         raw->address, regval);
+        }
+        snprintf_res(cmd_data, "\n\n");
+        return 0;
+#endif
+    }
+    if (strcmp(argv[1], "cfg") == 0) {
+        return ssv6xxx_dump_cfg(sc->sh);
+    }
+    snprintf_res(cmd_data, "dump [wsid|decision|phy-reg|rf-reg|cfg]\n");
+    return 0;
+}
+static int ssv_cmd_irq(struct ssv_softc *sc, int argc, char *argv[])
+{
+    char *endp;
+    u32 irq_sts;
+    struct ssv6xxx_hci_info *hci = &sc->sh->hci;
+    struct ssv6xxx_hwif_ops *ifops = hci->if_ops;
+    struct ssv_cmd_data *cmd_data = &sc->cmd_data;
+    if ((argc >= 3) && (strcmp(argv[1], "set") == 0)) {
+        if ((strcmp(argv[2], "mask") == 0) && (argc == 4)) {
+            irq_sts = simple_strtoul(argv[3], &endp, 16);
+            if (!sc->sh->hci.if_ops->irq_setmask) {
+                snprintf_res(cmd_data, "The interface doesn't provide irq_setmask operation.\n");
+                return 0;
+            }
+            ifops->irq_setmask(hci->dev, irq_sts);
+            snprintf_res(cmd_data, "set sdio irq mask to 0x%08x\n", irq_sts);
+            return 0;
+        }
+        if (strcmp(argv[2], "enable") == 0) {
+            if (!ifops->irq_enable) {
+                snprintf_res(cmd_data, "The interface doesn't provide irq_enable operation.\n");
+                return 0;
+            }
+            ifops->irq_enable(hci->dev);
+            snprintf_res(cmd_data, "enable sdio irq.\n");
+            return 0;
+        }
+        if (strcmp(argv[2], "disable") == 0) {
+            if (!ifops->irq_disable) {
+                snprintf_res(cmd_data, "The interface doesn't provide irq_disable operation.\n");
+                return 0;
+            }
+            ifops->irq_disable(hci->dev, false);
+            snprintf_res(cmd_data, "disable sdio irq.\n");
+            return 0;
+        }
+        return -1;
+    } else if ( (argc == 3) && (strcmp(argv[1], "get") == 0)) {
+        if (strcmp(argv[2], "mask") == 0) {
+            if (!ifops->irq_getmask) {
+                snprintf_res(cmd_data, "The interface doesn't provide irq_getmask operation.\n");
+                return 0;
+            }
+            ifops->irq_getmask(hci->dev, &irq_sts);
+            snprintf_res(cmd_data, "sdio irq mask: 0x%08x, int_mask=0x%08x\n", irq_sts,
+                         hci->hci_ctrl->int_mask);
+            return 0;
+        }
+        if (strcmp(argv[2], "status") == 0) {
+            if (!ifops->irq_getstatus) {
+                snprintf_res(cmd_data, "The interface doesn't provide irq_getstatus operation.\n");
+                return 0;
+            }
+            ifops->irq_getstatus(hci->dev, &irq_sts);
+            snprintf_res(cmd_data, "sdio irq status: 0x%08x\n", irq_sts);
+            return 0;
+        }
+        return -1;
+    } else {
+        snprintf_res(cmd_data, "irq [set|get] [mask|enable|disable|status]\n");
+    }
+    return 0;
+}
+static int ssv_cmd_mac(struct ssv_softc *sc, int argc, char *argv[])
+{
+    char *endp;
+    int i;
+    struct ssv_cmd_data *cmd_data = &sc->cmd_data;
+#if 0
+    if ((argc == 3) && (!strcmp(argv[1], "wsid")) && (!strcmp(argv[2], "show"))) {
+        u32 s;
+    }
+    return 0;
+} else
+#endif
+    if ((argc == 3) && (!strcmp(argv[1], "rx")))
+    {
+        if (!strcmp(argv[2], "enable")) {
+            sc->dbg_rx_frame = 1;
+        } else {
+            sc->dbg_rx_frame = 0;
+        }
+        snprintf_res(cmd_data, "  dbg_rx_frame %d\n", sc->dbg_rx_frame);
+        return 0;
+    } else if ((argc == 3) && (!strcmp(argv[1], "tx")))
+    {
+        if(!strcmp(argv[2], "enable")) {
+            sc->dbg_tx_frame = 1;
+        } else {
+            sc->dbg_tx_frame = 0;
+        }
+        snprintf_res(cmd_data, "  dbg_tx_frame %d\n", sc->dbg_tx_frame);
+        return 0;
+    } else if ((argc == 3) && (!strcmp(argv[1], "rxq")) && (!strcmp(argv[2], "show")))
+    {
+        snprintf_res(cmd_data, ">> MAC RXQ: (%s)\n    cur_qsize=%d\n",
+                     ((sc->sc_flags & SC_OP_OFFCHAN)? "off channel": "on channel"),
+                     sc->rx.rxq_count);
+        return 0;
+    }
+#if 0
+if (argc==3 && !strcmp(argv[1], "tx") && !strcmp(argv[2], "status"))
+{
+    snprintf_res(cmd_data, ">> MAC TX Status:\n");
+    snprintf_res(cmd_data, "    txq flow control: 0x%x\n", sc->tx.flow_ctrl_status);
+    snprintf_res(cmd_data, "    rxq cur_qsize: %d\n", sc->rx.rxq_count);
+}
+#endif
+else if ((argc == 4) && (!strcmp(argv[1], "set")) && (!strcmp(argv[2], "rate")))
+{
+    if (strcmp(argv[3], "auto") == 0) {
+        sc->sc_flags &= ~SC_OP_FIXED_RATE;
+        return 0;
+    }
+    i = simple_strtoul(argv[3], &endp, 10);
+    if ( i < 0 || i > 38) {
+        snprintf_res(cmd_data, " Invalid rat index !!\n");
+        return -1;
+    }
+    sc->max_rate_idx = i;
+    sc->sc_flags |= SC_OP_FIXED_RATE;
+    snprintf_res(cmd_data, " Set rate to index %d\n", i);
+    return 0;
+} else if ((argc == 3) && (!strcmp(argv[1], "get")) && (!strcmp(argv[2], "rate")))
+{
+    if (sc->sc_flags & SC_OP_FIXED_RATE)
+        snprintf_res(cmd_data, " Current Rate Index: %d\n", sc->max_rate_idx);
+    else
+        snprintf_res(cmd_data, "  Current Rate Index: auto\n");
+    return 0;
+} else if ((argc == 2) && (!strcmp(argv[1], "setting")))
+{
+    snprintf_res(cmd_data, "tx_cfg threshold:\n");
+    snprintf_res(cmd_data, "\t tx_id_threshold %d tx_cfg tx_lowthreshold_id_trigger %d tx_page_threshold %d\n",
+                 sc->sh->tx_info.tx_id_threshold, sc->sh->tx_info.tx_lowthreshold_id_trigger,
+                 sc->sh->tx_info.tx_page_threshold);
+    snprintf_res(cmd_data, "rx_cfg threshold:\n");
+    snprintf_res(cmd_data, "\t rx_id_threshold %d  rx_page_threshold %d\n",
+                 sc->sh->rx_info.rx_id_threshold, sc->sh->rx_info.rx_page_threshold);
+    snprintf_res(cmd_data, "tx page available %d\n", sc->sh->tx_page_available);
+} else
+{
+    snprintf_res(cmd_data, "mac [rxq] [show]\n");
+    snprintf_res(cmd_data, "mac [set|get] [rate] [auto|idx]\n");
+    snprintf_res(cmd_data, "mac [rx|tx] [eable|disable]\n");
+    snprintf_res(cmd_data, "mac [setting]\n");
+}
+return 0;
+}
+#ifdef CONFIG_IRQ_DEBUG_COUNT
+void print_irq_count(struct ssv6xxx_hci_ctrl *hci_ctrl)
+{
+    struct ssv_cmd_data *cmd_data = &hci_ctrl->shi->sc->cmd_data;
+    snprintf_res(cmd_data, "irq debug (%s)\n", hci_ctrl->irq_enable?"enable":"disable");
+    snprintf_res(cmd_data, "total irq (%d)\n", hci_ctrl->irq_count);
+    snprintf_res(cmd_data, "invalid irq (%d)\n", hci_ctrl->invalid_irq_count);
+    snprintf_res(cmd_data, "rx irq (%d)\n", hci_ctrl->rx_irq_count);
+    snprintf_res(cmd_data, "tx irq (%d)\n", hci_ctrl->tx_irq_count);
+    snprintf_res(cmd_data, "real tx count irq (%d)\n", hci_ctrl->real_tx_irq_count);
+    snprintf_res(cmd_data, "tx  packet count (%d)\n", hci_ctrl->irq_tx_pkt_count);
+    snprintf_res(cmd_data, "rx packet (%d)\n", hci_ctrl->irq_rx_pkt_count);
+}
+#endif
+void print_isr_info(struct ssv_cmd_data *cmd_data, struct ssv6xxx_hci_ctrl *hci_ctrl)
+{
+    snprintf_res(cmd_data, ">>>> HCI Calculate ISR TIME(%s) unit:us\n",
+                 ((hci_ctrl->isr_summary_eable) ? "enable": "disable"));
+    snprintf_res(cmd_data, "isr_routine_time(%d)\n",
+                 jiffies_to_usecs(hci_ctrl->isr_routine_time));
+    snprintf_res(cmd_data, "isr_tx_time(%d)\n",
+                 jiffies_to_usecs(hci_ctrl->isr_tx_time));
+    snprintf_res(cmd_data, "isr_rx_time(%d)\n",
+                 jiffies_to_usecs(hci_ctrl->isr_rx_time));
+    snprintf_res(cmd_data, "isr_idle_time(%d)\n",
+                 jiffies_to_usecs(hci_ctrl->isr_idle_time));
+    snprintf_res(cmd_data, "isr_rx_idle_time(%d)\n",
+                 jiffies_to_usecs(hci_ctrl->isr_rx_idle_time));
+    snprintf_res(cmd_data, "isr_miss_cnt(%d)\n",
+                 hci_ctrl->isr_miss_cnt);
+    snprintf_res(cmd_data, "prev_isr_jiffes(%lu)\n",
+                 hci_ctrl->prev_isr_jiffes);
+    snprintf_res(cmd_data, "prev_rx_isr_jiffes(%lu)\n",
+                 hci_ctrl->prev_rx_isr_jiffes);
+}
+static int ssv_cmd_hci(struct ssv_softc *sc, int argc, char *argv[])
+{
+    struct ssv6xxx_hci_ctrl *hci_ctrl = sc->sh->hci.hci_ctrl;
+    struct ssv_hw_txq *txq;
+    struct ssv_cmd_data *cmd_data = &sc->cmd_data;
+    int s, ac = 0;
+    if ((argc == 3) && (!strcmp(argv[1], "txq")) && (!strcmp(argv[2], "show"))) {
+        for(s = 0; s < WMM_NUM_AC; s++) {
+            ac = sc->tx.ac_txqid[s];
+            txq = &hci_ctrl->hw_txq[s];
+            snprintf_res(cmd_data, ">> txq[%d]", txq->txq_no);
+            snprintf_res(cmd_data, "(%s): ",
+                         ( (sc->sc_flags & SC_OP_OFFCHAN)
+                           ? "off channel"
+                           : "on channel"));
+            snprintf_res(cmd_data, "cur_qsize=%d\n", skb_queue_len(&txq->qhead));
+            snprintf_res(cmd_data, "            max_qsize=%d, pause=%d, resume_thres=%d",
+                         txq->max_qsize, txq->paused, txq->resum_thres);
+            snprintf_res(cmd_data, " flow_control[%d]\n",
+                         (sc->tx.flow_ctrl_status & (1<<ac)));
+            snprintf_res(cmd_data, "            Total %d frame sent\n",
+                         txq->tx_pkt);
+        }
+        snprintf_res(cmd_data,
+                     ">> HCI Debug Counters:\n    read_rs0_info_fail=%d, read_rs1_info_fail=%d\n",
+                     hci_ctrl->read_rs0_info_fail, hci_ctrl->read_rs1_info_fail);
+        snprintf_res(cmd_data,
+                     "    rx_work_running=%d, isr_running=%d, xmit_running=%d\n",
+                     hci_ctrl->rx_work_running, hci_ctrl->isr_running,
+                     hci_ctrl->xmit_running);
+        snprintf_res(cmd_data, "    flow_ctrl_status=%08x\n", sc->tx.flow_ctrl_status);
+        return 0;
+    } else if ((argc == 3) && (!strcmp(argv[1], "rxq")) && (!strcmp(argv[2], "show"))) {
+        snprintf_res(cmd_data, ">> HCI RX Queue (%s): cur_qsize=%d\n",
+                     ((sc->sc_flags & SC_OP_OFFCHAN)? "off channel": "on channel"),
+                     hci_ctrl->rx_pkt);
+        return 0;
+    } else if ((argc == 3) && (!strcmp(argv[1], "isr_time")) && (!strcmp(argv[2], "start"))) {
+        hci_ctrl->isr_summary_eable = 1;
+        hci_ctrl->isr_routine_time = 0;
+        hci_ctrl->isr_tx_time = 0;
+        hci_ctrl->isr_rx_time = 0;
+        hci_ctrl->isr_idle_time = 0;
+        hci_ctrl->isr_rx_idle_time = 0;
+        hci_ctrl->isr_miss_cnt = 0;
+        hci_ctrl->prev_isr_jiffes = 0;
+        hci_ctrl->prev_rx_isr_jiffes = 0;
+        print_isr_info(cmd_data, hci_ctrl);
+        return 0;
+    } else if ((argc == 3) && (!strcmp(argv[1], "isr_time")) && (!strcmp(argv[2], "stop"))) {
+        hci_ctrl->isr_summary_eable = 0;
+        print_isr_info(cmd_data, hci_ctrl);
+        return 0;
+    } else if ((argc == 3) && (!strcmp(argv[1], "isr_time")) && (!strcmp(argv[2], "show"))) {
+        print_isr_info(cmd_data, hci_ctrl);
+        return 0;
+    }
+#ifdef CONFIG_IRQ_DEBUG_COUNT
+    else if ((argc == 3) && (!strcmp(argv[1], "isr_debug")) && (!strcmp(argv[2], "reset"))) {
+        hci_ctrl->irq_enable= 0;
+        hci_ctrl->irq_count = 0;
+        hci_ctrl->invalid_irq_count = 0;
+        hci_ctrl->tx_irq_count = 0;
+        hci_ctrl->real_tx_irq_count = 0;
+        hci_ctrl->rx_irq_count = 0;
+        hci_ctrl->isr_rx_idle_time = 0;
+        hci_ctrl->irq_rx_pkt_count = 0;
+        hci_ctrl->irq_tx_pkt_count = 0;
+        snprintf_res(cmd_data, "irq debug reset count\n");
+        return 0;
+    } else if ((argc == 3) && (!strcmp(argv[1], "isr_debug")) && (!strcmp(argv[2], "show"))) {
+        print_irq_count(hci_ctrl);
+        return 0;
+    } else if ((argc == 3) && (!strcmp(argv[1], "isr_debug")) && (!strcmp(argv[2], "stop"))) {
+        hci_ctrl->irq_enable= 0;
+        snprintf_res(cmd_data, "irq debug stop\n");
+        return 0;
+    } else if ((argc == 3) && (!strcmp(argv[1], "isr_debug")) && (!strcmp(argv[2], "start"))) {
+        hci_ctrl->irq_enable= 1;
+        snprintf_res(cmd_data, "irq debug start\n");
+        return 0;
+    }
+#endif
+    else {
+        snprintf_res(cmd_data,
+                     "hci [txq|rxq] [show]\nhci [isr_time] [start|stop|show]\n\n");
+        return 0;
+    }
+    return -1;
+}
+static int ssv_cmd_hwq(struct ssv_softc *sc, int argc, char *argv[])
+{
+    struct ssv_cmd_data *cmd_data = &sc->cmd_data;
+    u32 value, value1, value2;
+    u32 tx_len = 0, rx_len = 0, ava_status = 0;
+    SSV_READ_FFOUT_CNT(sc->sh, &value, &value1, &value2);
+    snprintf_res(cmd_data, "\n[TAG]  MCU - HCI - SEC -  RX - MIC - TX0 - TX1 - TX2 - TX3 - TX4 - SEC - MIC - TSH\n");
+    snprintf_res(cmd_data, "OUTPUT %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d\n",
+                 SSV_GET_FFOUT_CNT(sc->sh, value, M_ENG_CPU),
+                 SSV_GET_FFOUT_CNT(sc->sh, value, M_ENG_HWHCI),
+                 SSV_GET_FFOUT_CNT(sc->sh, value, M_ENG_ENCRYPT),
+                 SSV_GET_FFOUT_CNT(sc->sh, value, M_ENG_MACRX),
+                 SSV_GET_FFOUT_CNT(sc->sh, value, M_ENG_MIC),
+                 SSV_GET_FFOUT_CNT(sc->sh, value1, M_ENG_TX_EDCA0),
+                 SSV_GET_FFOUT_CNT(sc->sh, value1, M_ENG_TX_EDCA1),
+                 SSV_GET_FFOUT_CNT(sc->sh, value1, M_ENG_TX_EDCA2),
+                 SSV_GET_FFOUT_CNT(sc->sh, value1, M_ENG_TX_EDCA3),
+                 SSV_GET_FFOUT_CNT(sc->sh, value1, M_ENG_TX_MNG),
+                 SSV_GET_FFOUT_CNT(sc->sh, value1, M_ENG_ENCRYPT_SEC),
+                 SSV_GET_FFOUT_CNT(sc->sh, value2, M_ENG_MIC_SEC),
+                 SSV_GET_FFOUT_CNT(sc->sh, value2, M_ENG_TRASH_CAN));
+    SSV_READ_IN_FFCNT(sc->sh, &value, &value1);
+    snprintf_res(cmd_data, "INPUT  %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d\n",
+                 SSV_GET_IN_FFCNT(sc->sh, value, M_ENG_CPU),
+                 SSV_GET_IN_FFCNT(sc->sh, value, M_ENG_HWHCI),
+                 SSV_GET_IN_FFCNT(sc->sh, value, M_ENG_ENCRYPT),
+                 SSV_GET_IN_FFCNT(sc->sh, value1, M_ENG_MACRX),
+                 SSV_GET_IN_FFCNT(sc->sh, value, M_ENG_MIC),
+                 SSV_GET_IN_FFCNT(sc->sh, value, M_ENG_TX_EDCA0),
+                 SSV_GET_IN_FFCNT(sc->sh, value, M_ENG_TX_EDCA1),
+                 SSV_GET_IN_FFCNT(sc->sh, value, M_ENG_TX_EDCA2),
+                 SSV_GET_IN_FFCNT(sc->sh, value, M_ENG_TX_EDCA3),
+                 SSV_GET_IN_FFCNT(sc->sh, value1, M_ENG_TX_MNG),
+                 SSV_GET_IN_FFCNT(sc->sh, value1, M_ENG_ENCRYPT_SEC),
+                 SSV_GET_IN_FFCNT(sc->sh, value1, M_ENG_MIC_SEC),
+                 SSV_GET_IN_FFCNT(sc->sh, value1, M_ENG_TRASH_CAN));
+    SSV_READ_ID_LEN_THRESHOLD(sc->sh, &tx_len, &rx_len);
+    SSV_READ_TAG_STATUS(sc->sh, &ava_status);
+    snprintf_res(cmd_data, "TX[%d]RX[%d]AVA[%d]\n", tx_len, rx_len, ava_status);
+    return 0;
+}
+#ifdef CONFIG_P2P_NOA
+#if 0
+struct ssv6xxx_p2p_noa_param {
+    u32 duration;
+    u32 interval;
+    u32 start_time;
+    u32 enable:8;
+    u32 count:8;
+    u8 addr[6];
+};
+#endif
+static struct ssv6xxx_p2p_noa_param cmd_noa_param = {
+    50,
+    100,
+    0x12345678,
+    1,
+    255,
+    {0x4c, 0xe6, 0x76, 0xa2, 0x4e, 0x7c}
+};
+void noa_dump(struct ssv_cmd_data *cmd_data)
+{
+    snprintf_res(cmd_data, "NOA Parameter:\nEnable=%d\nInterval=%d\nDuration=%d\nStart_time=0x%08x\nCount=%d\nAddr=[%02x:%02x:%02x:%02x:%02x:%02x]\n",
+                 cmd_noa_param.enable,
+                 cmd_noa_param.interval,
+                 cmd_noa_param.duration,
+                 cmd_noa_param.start_time,
+                 cmd_noa_param.count,
+                 cmd_noa_param.addr[0],
+                 cmd_noa_param.addr[1],
+                 cmd_noa_param.addr[2],
+                 cmd_noa_param.addr[3],
+                 cmd_noa_param.addr[4],
+                 cmd_noa_param.addr[5]);
+}
+void ssv6xxx_send_noa_cmd(struct ssv_softc *sc, struct ssv6xxx_p2p_noa_param *p2p_noa_param)
+{
+    struct sk_buff *skb;
+    struct cfg_host_cmd *host_cmd;
+    int retry_cnt = 5;
+    skb = ssvdevice_skb_alloc(HOST_CMD_HDR_LEN + sizeof(struct ssv6xxx_p2p_noa_param));
+    skb->data_len = HOST_CMD_HDR_LEN + sizeof(struct ssv6xxx_p2p_noa_param);
+    skb->len = skb->data_len;
+    host_cmd = (struct cfg_host_cmd *)skb->data;
+    host_cmd->c_type = HOST_CMD;
+    host_cmd->h_cmd = (u8)SSV6XXX_HOST_CMD_SET_NOA;
+    host_cmd->len = skb->data_len;
+    memcpy(host_cmd->dat32, p2p_noa_param, sizeof(struct ssv6xxx_p2p_noa_param));
+    while((HCI_SEND_CMD(sc->sh, skb)!=0)&&(retry_cnt)) {
+        printk(KERN_INFO "NOA cmd retry=%d!!\n",retry_cnt);
+        retry_cnt--;
+    }
+    ssvdevice_skb_free(skb);
+}
+static int ssv_cmd_noa(struct ssv_softc *sc, int argc, char *argv[])
+{
+    char *endp = NULL;
+    if ( (argc == 2) && (!strcmp(argv[1], "show"))) {
+        ;
+    } else if ((argc == 3) && (!strcmp(argv[1], "duration"))) {
+        cmd_noa_param.duration= simple_strtoul(argv[2], &endp, 0);
+    } else if ((argc == 3) && (!strcmp(argv[1], "interval"))) {
+        cmd_noa_param.interval= simple_strtoul(argv[2], &endp, 0);
+    } else if ((argc == 3) && (!strcmp(argv[1], "start"))) {
+        cmd_noa_param.start_time= simple_strtoul(argv[2], &endp, 0);
+    } else if ((argc == 3) && (!strcmp(argv[1], "enable"))) {
+        cmd_noa_param.enable= simple_strtoul(argv[2], &endp, 0);
+    } else if ((argc == 3) && (!strcmp(argv[1], "count"))) {
+        cmd_noa_param.count= simple_strtoul(argv[2], &endp, 0);
+    } else if ((argc == 8) && (!strcmp(argv[1], "addr"))) {
+        cmd_noa_param.addr[0]= simple_strtoul(argv[2], &endp, 16);
+        cmd_noa_param.addr[1]= simple_strtoul(argv[3], &endp, 16);
+        cmd_noa_param.addr[2]= simple_strtoul(argv[4], &endp, 16);
+        cmd_noa_param.addr[3]= simple_strtoul(argv[5], &endp, 16);
+        cmd_noa_param.addr[4]= simple_strtoul(argv[6], &endp, 16);
+        cmd_noa_param.addr[5]= simple_strtoul(argv[7], &endp, 16);
+    } else if ((argc == 2) && (!strcmp(argv[1], "send"))) {
+        ssv6xxx_send_noa_cmd(sc, &cmd_noa_param);
+    } else {
+        snprintf_res(&sc->cmd_data, "## wrong command\n");
+        return 0;
+    }
+    noa_dump(&sc->cmd_data);
+    return 0;
+}
+#endif
+static int ssv_cmd_mib(struct ssv_softc *sc, int argc, char *argv[])
+{
+    SSV_CMD_MIB(sc, argc, argv);
+    return 0;
+}
+static int ssv_cmd_power_saving(struct ssv_softc *sc, int argc, char *argv[])
+{
+    SSV_CMD_POWER_SAVING(sc, argc, argv);
+    return 0;
+}
+static int ssv_cmd_sdio(struct ssv_softc *sc, int argc, char *argv[])
+{
+    u32 addr, value;
+    char *endp;
+    int ret=0;
+    struct ssv6xxx_hci_info *hci = &sc->sh->hci;
+    struct ssv6xxx_hwif_ops *ifops = hci->if_ops;
+    struct ssv_cmd_data *cmd_data = &sc->cmd_data;
+    if ((argc == 4) && (!strcmp(argv[1], "reg")) && (!strcmp(argv[2], "r"))) {
+        addr = simple_strtoul(argv[3], &endp, 16);
+        if (!ifops->cmd52_read) {
+            snprintf_res(cmd_data, "The interface doesn't provide cmd52 read\n");
+            return 0;
+        }
+        ret = ifops->cmd52_read(hci->dev, addr, &value);
+        if (ret >= 0) {
+            snprintf_res(cmd_data, "  ==> %x\n", value);
+            return 0;
+        }
+    } else if ((argc ==5) && (!strcmp(argv[1], "reg")) && (!strcmp(argv[2], "w"))) {
+        addr = simple_strtoul(argv[3], &endp, 16);
+        value = simple_strtoul(argv[4], &endp, 16);
+        if (!ifops->cmd52_write) {
+            snprintf_res(cmd_data, "The interface doesn't provide cmd52 write\n");
+            return 0;
+        }
+        ret = ifops->cmd52_write(hci->dev, addr, value);
+        if (ret >= 0) {
+            snprintf_res(cmd_data, "  ==> write done.\n");
+            return 0;
+        }
+    }
+    snprintf_res(cmd_data, "sdio cmd52 fail: %d\n", ret);
+    return 0;
+}
+#if (defined (SSV_SUPPORT_HAL) || defined ( CONFIG_SSV_CABRIO_E))
+static struct ssv6xxx_iqk_cfg cmd_iqk_cfg = {
+    SSV6XXX_IQK_CFG_XTAL_26M,
+    SSV6XXX_IQK_CFG_PA_DEF,
+    0,
+    0,
+    26,
+    3,
+    0x75,
+    0x75,
+    0x80,
+    0x80,
+    SSV6XXX_IQK_CMD_INIT_CALI,
+    {
+        SSV6XXX_IQK_TEMPERATURE
+        + SSV6XXX_IQK_RXDC
+        + SSV6XXX_IQK_RXRC
+        + SSV6XXX_IQK_TXDC
+        + SSV6XXX_IQK_TXIQ
+        + SSV6XXX_IQK_RXIQ
+    },
+};
+static int ssv_cmd_iqk (struct ssv_softc *sc, int argc, char *argv[])
+{
+    char *endp;
+    struct sk_buff *skb;
+    struct cfg_host_cmd *host_cmd;
+    u32 rxcnt_total, rxcnt_error;
+    struct ssv_cmd_data *cmd_data = &sc->cmd_data;
+#ifdef SSV_SUPPORT_HAL
+    if (HAL_SUPPORT_IQK_CMD(sc->sh) == false) {
+        snprintf_res(cmd_data, "iqk command is not supported for this chip\n");
+        return 0;
+    }
+#else
+    char chip_id[24]="";
+    ssv_cmd_get_chip_id(sc, chip_id);
+    if (!(strstr(chip_id, SSV6051_CHIP))) {
+        snprintf_res(cmd_data, "iqk command is not supported for this chip\n");
+        return 0;
+    }
+#endif
+    snprintf_res(cmd_data, "# got iqk command\n");
+    if ((argc == 3) && (strcmp(argv[1], "cfg-pa") == 0)) {
+        cmd_iqk_cfg.cfg_pa = simple_strtoul(argv[2], &endp, 0);
+        snprintf_res(cmd_data, "## set cfg_pa as %d\n", cmd_iqk_cfg.cfg_pa);
+        return 0;
+    } else if ((argc == 3) && (strcmp(argv[1], "cfg-tssi-trgt") == 0)) {
+        cmd_iqk_cfg.cfg_tssi_trgt = simple_strtoul(argv[2], &endp, 0);
+        snprintf_res(cmd_data, "## set cfg_tssi_trgt as %d\n", cmd_iqk_cfg.cfg_tssi_trgt);
+        return 0;
+    } else if ((argc == 3) && (strcmp(argv[1], "init-cali") == 0)) {
+        cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_INIT_CALI;
+        cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0);
+        snprintf_res(cmd_data, "## do init-cali\n");
+    } else if ((argc == 3) && (strcmp(argv[1], "rtbl-load") == 0)) {
+        cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_RTBL_LOAD;
+        cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0);
+        snprintf_res(cmd_data, "## do rtbl-load\n");
+    } else if ((argc == 3) && (strcmp(argv[1], "rtbl-load-def") == 0)) {
+        cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_RTBL_LOAD_DEF;
+        cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0);
+        snprintf_res(cmd_data, "## do rtbl-load\n");
+    } else if ((argc == 3) && (strcmp(argv[1], "rtbl-reset") == 0)) {
+        cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_RTBL_RESET;
+        cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0);
+        snprintf_res(cmd_data, "## do rtbl-reset\n");
+    } else if ((argc == 3) && (strcmp(argv[1], "rtbl-set") == 0)) {
+        cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_RTBL_SET;
+        cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0);
+        snprintf_res(cmd_data, "## do rtbl-set\n");
+    } else if ((argc == 3) && (strcmp(argv[1], "rtbl-export") == 0)) {
+        cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_RTBL_EXPORT;
+        cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0);
+        snprintf_res(cmd_data, "## do rtbl-export\n");
+    } else if ((argc == 3) && (strcmp(argv[1], "tk-evm") == 0)) {
+        cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_TK_EVM;
+        cmd_iqk_cfg.argv = simple_strtoul(argv[2], &endp, 0);
+        snprintf_res(cmd_data, "## do tk-evm\n");
+    } else if ((argc == 3) && (strcmp(argv[1], "tk-tone") == 0)) {
+        cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_TK_TONE;
+        cmd_iqk_cfg.argv = simple_strtoul(argv[2], &endp, 0);
+        snprintf_res(cmd_data, "## do tk-tone\n");
+    } else if ((argc == 3) && (strcmp(argv[1], "channel") == 0)) {
+        cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_TK_CHCH;
+        cmd_iqk_cfg.argv = simple_strtoul(argv[2], &endp, 0);
+        snprintf_res(cmd_data, "## do change channel\n");
+    } else if ((argc == 2) && (strcmp(argv[1], "tk-rxcnt-report") == 0)) {
+        if(SMAC_REG_READ(sc->sh, 0xCE0043E8, &rxcnt_error));
+        if(SMAC_REG_READ(sc->sh, 0xCE0043EC, &rxcnt_total));
+        snprintf_res(cmd_data, "## GN Rx error rate = (%06d/%06d)\n", rxcnt_error, rxcnt_total);
+        if(SMAC_REG_READ(sc->sh, 0xCE0023E8, &rxcnt_error));
+        if(SMAC_REG_READ(sc->sh, 0xCE0023EC, &rxcnt_total));
+        snprintf_res(cmd_data, "## B Rx error rate = (%06d/%06d)\n", rxcnt_error, rxcnt_total);
+        return 0;
+    } else {
+        snprintf_res(cmd_data, "## invalid iqk command\n");
+        snprintf_res(cmd_data, "## cmd: cfg-pa/cfg-tssi-trgt\n");
+        snprintf_res(cmd_data, "## cmd: init-cali/rtbl-load/rtbl-load-def/rtbl-reset/rtbl-set/rtbl-export/tk-evm/tk-tone/tk-channel\n");
+        snprintf_res(cmd_data, "## fx_sel: 0x0008: RXDC\n");
+        snprintf_res(cmd_data, "           0x0010: RXRC\n");
+        snprintf_res(cmd_data, "           0x0020: TXDC\n");
+        snprintf_res(cmd_data, "           0x0040: TXIQ\n");
+        snprintf_res(cmd_data, "           0x0080: RXIQ\n");
+        snprintf_res(cmd_data, "           0x0100: TSSI\n");
+        snprintf_res(cmd_data, "           0x0200: PAPD\n");
+        return 0;
+    }
+    {
+        int phy_setting_size, rf_setting_size;
+        ssv_cabrio_reg *phy_tbl, *rf_tbl ;
+#ifdef SSV_SUPPORT_HAL
+        phy_setting_size = HAL_GET_PHY_TABLE_SIZE(sc->sh);
+        rf_setting_size = HAL_GET_RF_TABLE_SIZE(sc->sh);
+        HAL_LOAD_PHY_TABLE(sc->sh, &phy_tbl);
+        HAL_LOAD_RF_TABLE(sc->sh, &rf_tbl);
+#else
+        phy_setting_size = PHY_SETTING_SIZE;
+        rf_setting_size = RF_SETTING_SIZE;
+        phy_tbl = phy_setting;
+        rf_tbl = asic_rf_setting;
+#endif
+        skb = ssvdevice_skb_alloc(HOST_CMD_HDR_LEN + IQK_CFG_LEN + phy_setting_size + rf_setting_size);
+        if(skb == NULL) {
+            printk("ssv command ssvdevice_skb_alloc fail!!!\n");
+            return 0;
+        }
+        if((phy_setting_size > MAX_PHY_SETTING_TABLE_SIZE) ||
+           (rf_setting_size > MAX_RF_SETTING_TABLE_SIZE)) {
+            printk("Please check RF or PHY table size!!!\n");
+            BUG_ON(1);
+            return 0;
+        }
+        skb->data_len = HOST_CMD_HDR_LEN + IQK_CFG_LEN + phy_setting_size + rf_setting_size;
+        skb->len = skb->data_len;
+        host_cmd = (struct cfg_host_cmd *)skb->data;
+        host_cmd->c_type = HOST_CMD;
+        host_cmd->h_cmd = (u8)SSV6XXX_HOST_CMD_INIT_CALI;
+        host_cmd->len = skb->data_len;
+        cmd_iqk_cfg.phy_tbl_size = phy_setting_size;
+        cmd_iqk_cfg.rf_tbl_size = rf_setting_size;
+        memcpy(host_cmd->dat32, &cmd_iqk_cfg, IQK_CFG_LEN);
+        memcpy(host_cmd->dat8+IQK_CFG_LEN, phy_tbl, phy_setting_size);
+        memcpy(host_cmd->dat8+IQK_CFG_LEN+phy_setting_size, rf_tbl, rf_setting_size);
+        if (sc->sh->hci.hci_ops->hci_send_cmd(sc->sh->hci.hci_ctrl, skb) == 0) {
+            snprintf_res(cmd_data, "## hci send cmd success\n");
+        } else {
+            snprintf_res(cmd_data, "## hci send cmd fail\n");
+        }
+        ssvdevice_skb_free(skb);
+        return 0;
+    }
+}
+#endif
+#define CLI_VERSION "0.08"
+static int ssv_cmd_version (struct ssv_softc *sc, int argc, char *argv[])
+{
+    u32 regval;
+    char chip_id[24] = "";
+    struct ssv_cmd_data *cmd_data = &sc->cmd_data;
+    snprintf_res(cmd_data, "CLI version: %s \n", CLI_VERSION);
+    snprintf_res(cmd_data, "CHIP TAG: %llx \n", sc->sh->chip_tag);
+    ssv_cmd_get_chip_id(sc, chip_id);
+    snprintf_res(cmd_data, "CHIP ID: %s \n", chip_id);
+    snprintf_res(cmd_data, "# current Software mac version: %d\n", ssv_root_version);
+    snprintf_res(cmd_data, "COMPILER DATE %s \n", COMPILERDATE);
+    SSV_GET_FW_VERSION(sc->sh, &regval);
+    snprintf_res(cmd_data, "Firmware image version: %d\n", regval);
+    return 0;
+}
+static int ssv_cmd_tool(struct ssv_softc *sc, int argc, char *argv[])
+{
+    u32 addr, value, count, len;
+    char *endp;
+    int s, retval;
+    struct ssv_cmd_data *cmd_data = &sc->cmd_data;
+    if ((argc == 4) && (strcmp(argv[1], "w") == 0)) {
+        addr = simple_strtoul(argv[2], &endp, 16);
+        value = simple_strtoul(argv[3], &endp, 16);
+        if (SMAC_REG_WRITE(sc->sh, addr, value)) ;
+        snprintf_res(cmd_data, "ok");
+        return 0;
+    }
+    if (( (argc == 4) || (argc == 3)) && (strcmp(argv[1], "r") == 0)) {
+        count = (argc==3)? 1: simple_strtoul(argv[3], &endp, 10);
+        addr = simple_strtoul(argv[2], &endp, 16);
+        for(s=0; s<count; s++, addr+=4) {
+            if (SMAC_REG_READ(sc->sh, addr, &value)) ;
+            snprintf_res(cmd_data, "%08x\n", value);
+        }
+        return 0;
+    }
+    if ((argc == 3) && (strcmp(argv[1], "auto_gen_nullpkt") == 0)) {
+        value = simple_strtoul(argv[2], &endp, 10);
+        retval = SSV_AUTO_GEN_NULLPKT(sc->sh, value);
+        if (!retval)
+            snprintf_res(cmd_data, "done to auto generate null frame\n");
+        else
+            snprintf_res(cmd_data, "Not suppout the tool\n");
+        return 0;
+    }
+    if ((argc == 3) && (strcmp(argv[1], "dump_pbuf") == 0)) {
+        value = simple_strtoul(argv[2], &endp, 10);
+        addr = 0x80000000 | (value << 16);
+        SMAC_REG_READ(sc->sh, addr, &len);
+        len &= 0xffff;
+        snprintf_res(cmd_data, "\n pbuf id=%d, len=%d\n\n", value, len);
+        if (len > 1024)
+            len = 1024;
+        for(s=0; s<len; s+=4, addr+=4) {
+            if (SMAC_REG_READ(sc->sh, addr, &value));
+            if((s+4)%32 == 0)
+                snprintf_res(cmd_data, " %08x\n", value);
+            else
+                snprintf_res(cmd_data, " %08x", value);
+        }
+        return 0;
+    }
+    return -1;
+}
+static int txtput_thread_m2(void *data)
+{
+#define Q_DELAY_MS 20
+    struct sk_buff *skb = NULL;
+    int qlen = 0, max_qlen, q_delay_urange[2];
+    struct ssv_softc *sc = data;
+    max_qlen = (200 * 1000 / 8 * Q_DELAY_MS) / sc->ssv_txtput.size_per_frame;
+    q_delay_urange[0] = Q_DELAY_MS * 1000;
+    q_delay_urange[1] = q_delay_urange[0] + 1000;
+    printk("max_qlen: %d\n", max_qlen);
+    while (!kthread_should_stop() && sc->ssv_txtput.loop_times > 0) {
+        sc->ssv_txtput.loop_times--;
+        skb = ssvdevice_skb_alloc(sc->ssv_txtput.size_per_frame);
+        if (skb == NULL) {
+            printk("ssv command txtput_generate_m2 "
+                   "ssvdevice_skb_alloc fail!!!\n");
+            goto end;
+        }
+        skb->data_len = sc->ssv_txtput.size_per_frame ;
+        skb->len = sc->ssv_txtput.size_per_frame ;
+        SSV_TXTPUT_SET_DESC(sc->sh, skb);
+        qlen = sc->sh->hci.hci_ops->hci_tx(sc->sh->hci.hci_ctrl, skb, 0, 0);
+        if (qlen >= max_qlen) {
+            usleep_range(q_delay_urange[0], q_delay_urange[1]);
+        }
+    }
+end:
+    sc->ssv_txtput.txtput_tsk = NULL;
+    return 0;
+}
+int txtput_generate_m2(struct ssv_softc *sc, u32 size_per_frame, u32 loop_times)
+{
+    sc->ssv_txtput.size_per_frame = size_per_frame;
+    sc->ssv_txtput.loop_times = loop_times;
+    sc->ssv_txtput.txtput_tsk = kthread_run(txtput_thread_m2, sc, "txtput_thread_m2");
+    return 0;
+}
+static int txtput_tsk_cleanup(struct ssv_softc *sc)
+{
+    int ret = 0;
+    if (sc->ssv_txtput.txtput_tsk) {
+        ret = kthread_stop(sc->ssv_txtput.txtput_tsk);
+        sc->ssv_txtput.txtput_tsk = NULL;
+    }
+    return ret;
+}
+static int ssv_cmd_txtput(struct ssv_softc *sc, int argc, char *argv[])
+{
+    char *endp;
+    u32 size_per_frame, loop_times;
+    struct ssv_cmd_data *cmd_data = &sc->cmd_data;
+    if ( (argc == 2) && (!strcmp(argv[1], "stop"))) {
+        txtput_tsk_cleanup(sc);
+        return 0;
+    }
+    if (argc != 3) {
+        snprintf_res(cmd_data, "* txtput stop\n");
+        snprintf_res(cmd_data, "* txtput [size] [frames]\n");
+        snprintf_res(cmd_data, " EX: txtput 14000 9999 \n");
+        return 0;
+    }
+    size_per_frame = simple_strtoul(argv[1], &endp, 10);
+    loop_times = simple_strtoul(argv[2], &endp, 10);
+    snprintf_res(cmd_data, "size & frames: %d & %d\n", size_per_frame, loop_times);
+    if (sc->ssv_txtput.txtput_tsk) {
+        snprintf_res(cmd_data, "txtput already in progress\n");
+        return 0;
+    }
+    txtput_generate_m2(sc, size_per_frame + TXPB_OFFSET, loop_times);
+    return 0;
+}
+#define MAX_FRM_SIZE 2304
+static int ssv_cmd_rxtput(struct ssv_softc *sc, int argc, char *argv[])
+{
+    struct sk_buff *skb;
+    struct cfg_host_cmd *host_cmd;
+    struct sdio_rxtput_cfg cmd_rxtput_cfg;
+    char *endp;
+    struct ssv_cmd_data *cmd_data = &sc->cmd_data;
+    if (argc != 3) {
+        snprintf_res(cmd_data, "rxtput [size] [frames]\n");
+        return 0;
+    }
+    cmd_rxtput_cfg.size_per_frame = simple_strtoul(argv[1], &endp, 10);
+    cmd_rxtput_cfg.total_frames = simple_strtoul(argv[2], &endp, 10);
+    if (cmd_rxtput_cfg.size_per_frame > MAX_FRM_SIZE) {
+        snprintf_res(cmd_data, "Frame size too large!!\n");
+        return 0 ;
+    }
+    snprintf_res(cmd_data, "size & frames: %d& %d\n",
+                 cmd_rxtput_cfg.size_per_frame, cmd_rxtput_cfg.total_frames);
+    skb = ssvdevice_skb_alloc(HOST_CMD_HDR_LEN + sizeof(struct sdio_rxtput_cfg));
+    if(skb == NULL) {
+        printk("ssv command ssvdevice_skb_alloc fail!!!\n");
+        return 0;
+    }
+    skb->data_len = HOST_CMD_HDR_LEN + sizeof(struct sdio_rxtput_cfg);
+    skb->len = skb->data_len;
+    host_cmd = (struct cfg_host_cmd *)skb->data;
+    host_cmd->c_type = HOST_CMD;
+    host_cmd->h_cmd = (u8)SSV6XXX_HOST_CMD_RX_TPUT;
+    host_cmd->len = skb->data_len;
+    memcpy(host_cmd->dat32, &cmd_rxtput_cfg, sizeof(struct sdio_rxtput_cfg));
+    if (sc->sh->hci.hci_ops->hci_send_cmd(sc->sh->hci.hci_ctrl, skb) == 0) {
+        snprintf_res(cmd_data, "## hci cmd was sent successfully\n");
+    } else {
+        snprintf_res(cmd_data, "## hci cmd was sent failed\n");
+    }
+    ssvdevice_skb_free(skb);
+    return 0;
+}
+static int ssv_cmd_check(struct ssv_softc *sc, int argc, char *argv[])
+{
+    u32 size,i,j,x,y,id,value,address,id_value;
+    char *endp;
+    struct ssv_cmd_data *cmd_data = &sc->cmd_data;
+    u32 id_base_address[4];
+#ifdef SSV_SUPPORT_HAL
+#endif
+    SSV_GET_RD_ID_ADR(sc->sh, &id_base_address[0]);
+    if (argc != 2) {
+        snprintf_res(cmd_data, "check [packet size]\n");
+        return 0;
+    }
+    snprintf_res(cmd_data, " id address %x %x %x %x \n", id_base_address[0],
+                 id_base_address[1], id_base_address[2], id_base_address[3]);
+    size = simple_strtoul(argv[1], &endp, 10);
+    size = size >> 2;
+    for (x = 0; x < 4; x++) {
+        if (SMAC_REG_READ(sc->sh, id_base_address[x], &id_value));
+        for (y = 0; y < 32 && id_value; y++, id_value>>=1) {
+            if (id_value & 0x1) {
+                id = 32*x + y;
+                address = 0x80000000 + (id << 16);
+                {
+                    printk("        ");
+                    for (i = 0; i < size; i += 8) {
+                        if(SMAC_REG_READ(sc->sh, address, &value));
+                        printk("\n%08X:%08X", address,value);
+                        address += 4;
+                        for (j = 1; j < 8; j++) {
+                            if(SMAC_REG_READ(sc->sh, address, &value));
+                            printk(" %08X", value);
+                            address += 4;
+                        }
+                    }
+                    printk("\n");
+                }
+            }
+        }
+    }
+    return 0;
+}
+static int ssv_cmd_rawpkt_context(char *buf, int len, void *file)
+{
+    struct file *fp = (struct file *)file;
+    int rdlen;
+    if (!file)
+        return 0;
+    rdlen = kernel_read(fp, fp->f_pos, buf, len);
+    if (rdlen > 0)
+        fp->f_pos += rdlen;
+    return rdlen;
+}
+static void ssv_cmd_rawpkt_send(struct ssv_hw *sh, char *filename)
+{
+#define LEN_RAW_PACKET 15000
+    struct sk_buff *skb = NULL;
+    struct file *fp = NULL;
+    u8 buffer[128];
+    int len = 0;
+    unsigned char *data = NULL;
+    skb = ssvdevice_skb_alloc(LEN_RAW_PACKET);
+    if (!skb)
+        goto out;
+    fp = filp_open(filename, O_RDONLY, 0);
+    if (IS_ERR(fp))
+        goto out;
+    memset(buffer, 0x0, sizeof(buffer));
+    while ((len = ssv_cmd_rawpkt_context((char*)buffer, sizeof(buffer), fp))) {
+        data = skb_put(skb, len);
+        memcpy(data, buffer, len);
+    }
+    HCI_SEND_CMD(sh, skb);
+out:
+    if (skb)
+        ssvdevice_skb_free(skb);
+    if (fp)
+        filp_close(fp, NULL);
+}
+static int ssv_cmd_rawpkt(struct ssv_softc *sc, int argc, char *argv[])
+{
+    struct ssv_cmd_data *cmd_data = &sc->cmd_data;
+    if (argc != 2) {
+        snprintf_res(cmd_data, "\n rawpkt [binary file path] \n");
+        return 0;
+    }
+    ssv_cmd_rawpkt_send(sc->sh, argv[1]);
+    return 0;
+}
+static int ssv_cmd_directack(struct ssv_softc *sc, int argc, char *argv[])
+{
+    struct ssv_cmd_data *cmd_data = &sc->cmd_data;
+    char *endp;
+    if ((argc == 2) && (!strcmp(argv[1], "show"))) {
+        snprintf_res(cmd_data, ">> act status = %s\n",
+                     ((sc->sc_flags & SC_OP_DIRECTLY_ACK) ? "direct complete" : "delay complete"));
+        snprintf_res(cmd_data, ">> ampdu_tx_frame = %d\n", atomic_read(&sc->ampdu_tx_frame));
+        snprintf_res(cmd_data, ">> directly_ack_low_threshold = %d\n", sc->directly_ack_low_threshold);
+        snprintf_res(cmd_data, ">> directly_ack_high_threshold = %d\n", sc->directly_ack_high_threshold);
+        return 0;
+    } else if ((argc == 3) && (!strcmp(argv[1], "low_threshold"))) {
+        sc->directly_ack_low_threshold = simple_strtoul(argv[2], &endp, 10);
+        snprintf_res(cmd_data, ">> Set directly_ack_low_threshold = %d\n", sc->directly_ack_low_threshold);
+        return 0;
+    } else if ((argc == 3) && (!strcmp(argv[1], "high_threshold"))) {
+        sc->directly_ack_high_threshold = simple_strtoul(argv[2], &endp, 10);
+        snprintf_res(cmd_data, ">> Set directly_ack_high_threshold = %d\n", sc->directly_ack_high_threshold);
+        return 0;
+    } else {
+        snprintf_res(cmd_data, "\n directack [show|low_threshold|high_threshold] [value] \n");
+        return 0;
+    }
+    return 0;
+}
+static int ssv_cmd_txrxboost(struct ssv_softc *sc, int argc, char *argv[])
+{
+    struct ssv_cmd_data *cmd_data = &sc->cmd_data;
+    char *endp;
+    if ((argc == 2) && (!strcmp(argv[1], "show"))) {
+        snprintf_res(cmd_data, ">> ampdu_tx_frame = %d\n", atomic_read(&sc->ampdu_tx_frame));
+        snprintf_res(cmd_data, ">> txrxboost_prio = %d\n", sc->sh->cfg.txrxboost_prio);
+        snprintf_res(cmd_data, ">> txrxboost_low_threshold = %d\n", sc->sh->cfg.txrxboost_low_threshold);
+        snprintf_res(cmd_data, ">> txrxboost_high_threshold = %d\n", sc->sh->cfg.txrxboost_high_threshold);
+        return 0;
+    } else if ((argc == 3) && (!strcmp(argv[1], "prio"))) {
+        u32 prio = simple_strtoul(argv[2], &endp, 10);
+        sc->sh->cfg.txrxboost_prio = (prio > (MAX_RT_PRIO-1))?(MAX_RT_PRIO-1):((prio < 0)?0:prio);
+        snprintf_res(cmd_data, ">> Set txrxboost_prio = %d\n", sc->sh->cfg.txrxboost_prio);
+        return 0;
+    } else if ((argc == 3) && (!strcmp(argv[1], "low_threshold"))) {
+        sc->sh->cfg.txrxboost_low_threshold = simple_strtoul(argv[2], &endp, 10);
+        snprintf_res(cmd_data, ">> Set txrxboost_low_threshold = %d\n", sc->sh->cfg.txrxboost_low_threshold);
+        return 0;
+    } else if ((argc == 3) && (!strcmp(argv[1], "high_threshold"))) {
+        sc->sh->cfg.txrxboost_high_threshold = simple_strtoul(argv[2], &endp, 10);
+        snprintf_res(cmd_data, ">> Set txrxboost_high_threshold = %d\n", sc->sh->cfg.txrxboost_high_threshold);
+        return 0;
+    } else {
+        snprintf_res(cmd_data, "\n txrxboost [show|prio|low_threshold|high_threshold] [value] \n");
+        return 0;
+    }
+    return 0;
+}
+static int ssv_cmd_txrx_skb_q(struct ssv_softc *sc, int argc, char *argv[])
+{
+    struct ssv_cmd_data *cmd_data = &sc->cmd_data;
+    struct ssv6xxx_hci_ctrl *hci_ctrl = sc->sh->hci.hci_ctrl;
+    int txqid;
+    char *endp;
+    if ((argc == 2) && (!strcmp(argv[1], "show"))) {
+        snprintf_res(cmd_data, ">> tx_skb_q = %u\n", skb_queue_len(&sc->tx_skb_q));
+        snprintf_res(cmd_data, ">> rx_skb_q = %u\n", skb_queue_len(&sc->rx_skb_q));
+        for(txqid=0; txqid<SSV_HW_TXQ_NUM; txqid++) {
+            snprintf_res(cmd_data, ">> hw_txq[%d] = %u\n", txqid, skb_queue_len(&hci_ctrl->hw_txq[txqid].qhead));
+        }
+        snprintf_res(cmd_data, ">> rx_threshold = %d\n", sc->sh->cfg.rx_threshold);
+        return 0;
+    } else if ((argc == 3) && (!strcmp(argv[1], "rx_threshold"))) {
+        sc->sh->cfg.rx_threshold = simple_strtoul(argv[2], &endp, 10);
+        snprintf_res(cmd_data, ">> Set rx_threshold = %d\n", sc->sh->cfg.rx_threshold);
+        return 0;
+    } else {
+        snprintf_res(cmd_data, "\n txrx_skb_q [show|rx_threshold] [value] \n");
+        return 0;
+    }
+    return 0;
+}
+#ifdef SSV_SUPPORT_HAL
+static int ssv_cmd_log(struct ssv_softc *sc, int argc, char *argv[])
+{
+    struct ssv_cmd_data *cmd_data = &sc->cmd_data;
+    u32 log_hex = 0;
+    int log_size = 0, total_log_size;
+    if ((argc == 3) && (!strcmp(argv[1], "tx_desc"))) {
+        if(!strcmp(argv[2], "enable")) {
+            sc->log_ctrl |= LOG_TX_DESC;
+        } else {
+            sc->log_ctrl &= ~(LOG_TX_DESC);
+        }
+        snprintf_res(cmd_data, "  log tx_desc %s\n", ((sc->log_ctrl & LOG_TX_DESC) ? "enable": "disable"));
+    } else if ((argc == 3) && (!strcmp(argv[1], "rx_desc"))) {
+        if(!strcmp(argv[2], "enable")) {
+            sc->log_ctrl |= LOG_RX_DESC;
+        } else {
+            sc->log_ctrl &= ~(LOG_RX_DESC);
+        }
+        snprintf_res(cmd_data, "  log rx_desc %s\n", ((sc->log_ctrl & LOG_RX_DESC) ? "enable": "disable"));
+    } else if ((argc == 3) && (!strcmp(argv[1], "tx_frame"))) {
+        if(!strcmp(argv[2], "enable")) {
+            sc->log_ctrl |= LOG_TX_FRAME;
+        } else {
+            sc->log_ctrl &= ~(LOG_TX_FRAME);
+        }
+        snprintf_res(cmd_data, "  log tx_frame %s\n", ((sc->log_ctrl & LOG_TX_FRAME) ? "enable": "disable"));
+    } else if((argc == 4) && (!strcmp(argv[1], "ampdu"))) {
+        if (!strcmp(argv[2], "ssn")) {
+            if(!strcmp(argv[3], "enable")) {
+                sc->log_ctrl |= LOG_AMPDU_SSN;
+            } else {
+                sc->log_ctrl &= ~(LOG_AMPDU_SSN);
+            }
+            snprintf_res(cmd_data, "  log ampdu ssn %s\n", ((sc->log_ctrl & LOG_AMPDU_SSN) ? "enable": "disable"));
+        } else if (!strcmp(argv[2], "dbg")) {
+            if(!strcmp(argv[3], "enable")) {
+                sc->log_ctrl |= LOG_AMPDU_DBG;
+            } else {
+                sc->log_ctrl &= ~(LOG_AMPDU_DBG);
+            }
+            snprintf_res(cmd_data, "  log ampdu dbg %s\n", ((sc->log_ctrl & LOG_AMPDU_DBG) ? "enable": "disable"));
+        } else if (!strcmp(argv[2], "err")) {
+            if(!strcmp(argv[3], "enable")) {
+                sc->log_ctrl |= LOG_AMPDU_ERR;
+            } else {
+                sc->log_ctrl &= ~(LOG_AMPDU_ERR);
+            }
+            snprintf_res(cmd_data, "  log ampdu err %s\n", ((sc->log_ctrl & LOG_AMPDU_ERR) ? "enable": "disable"));
+        } else {
+            snprintf_res(cmd_data, " Invalid command!!\n");
+            return 0;
+        }
+    } else if ((argc == 3) && (!strcmp(argv[1], "beacon"))) {
+        if (!strcmp(argv[2], "enable")) {
+            sc->log_ctrl |= LOG_BEACON;
+        } else {
+            sc->log_ctrl &= ~(LOG_BEACON);
+        }
+        snprintf_res(cmd_data, "  log beacon%s\n", ((sc->log_ctrl & LOG_BEACON) ? "enable": "disable"));
+    } else if ((argc == 3) && (!strcmp(argv[1], "rate_control"))) {
+        if (!strcmp(argv[2], "enable")) {
+            sc->log_ctrl |= LOG_RATE_CONTROL;
+        } else {
+            sc->log_ctrl &= ~(LOG_RATE_CONTROL);
+        }
+        snprintf_res(cmd_data, "  log rate control %s\n", ((sc->log_ctrl & LOG_RATE_CONTROL) ? "enable": "disable"));
+    } else if ((argc == 3) && (!strcmp(argv[1], "rate_report"))) {
+        if (!strcmp(argv[2], "enable")) {
+            sc->log_ctrl |= LOG_RATE_REPORT;
+        } else {
+            sc->log_ctrl &= ~(LOG_RATE_REPORT);
+        }
+        snprintf_res(cmd_data, "  log rate report %s\n", ((sc->log_ctrl & LOG_RATE_REPORT) ? "enable": "disable"));
+    } else if ((argc == 3) && (!strcmp(argv[1], "hci"))) {
+        if(!strcmp(argv[2], "enable")) {
+            sc->log_ctrl |= LOG_HCI;
+        } else {
+            sc->log_ctrl &= ~(LOG_HCI);
+        }
+        snprintf_res(cmd_data, "  log hci %s\n", ((sc->log_ctrl & LOG_HCI) ? "enable": "disable"));
+    } else if ((argc == 3) && (!strcmp(argv[1], "hwif"))) {
+        if(!strcmp(argv[2], "enable")) {
+            sc->log_ctrl |= LOG_HWIF;
+            sc->sh->priv->dbg_control = true;
+        } else {
+            sc->log_ctrl &= ~(LOG_HWIF);
+            sc->sh->priv->dbg_control = false;
+        }
+        snprintf_res(cmd_data, "  log hwif %s\n", ((sc->log_ctrl & LOG_HWIF) ? "enable": "disable"));
+    } else if ((argc == 3) && (!strcmp(argv[1], "flash_bin"))) {
+        if(!strcmp(argv[2], "enable")) {
+            sc->log_ctrl |= LOG_FLASH_BIN;
+        } else {
+            sc->log_ctrl &= ~(LOG_FLASH_BIN);
+        }
+        snprintf_res(cmd_data, "  log flash_bin %s\n", ((sc->log_ctrl & LOG_FLASH_BIN) ? "enable": "disable"));
+    } else if ((argc == 3) && (!strcmp(argv[1], "spectrum"))) {
+        if (!strcmp(argv[2], "enable")) {
+            snprintf_res(cmd_data, "  Spectrum log is in kernel log\n");
+            HAL_CMD_SPECTRUM(sc->sh);
+        }
+    } else if ((argc == 3) && (!strcmp(argv[1], "hex"))) {
+        if (1 != sscanf(argv[2], "%x", &log_hex)) {
+            snprintf_res(cmd_data, " log hex hexstring\n");
+        } else {
+            sc->log_ctrl = log_hex;
+        }
+        snprintf_res(cmd_data, "  log ctrl %d\n", sc->log_ctrl);
+    } else if ((argc == 3) && (!strcmp(argv[1], "log_to_ram"))) {
+        if (!strcmp(argv[2], "enable")) {
+            sc->cmd_data.log_to_ram = true;
+        } else {
+            sc->cmd_data.log_to_ram = false;
+        }
+        snprintf_res(cmd_data, " log_to_ram %s\n", (sc->cmd_data.log_to_ram ? "enable" : "disable"));
+        return 0;
+    } else if ((argc == 3) && (!strcmp(argv[1], "ram_size"))) {
+        if (1 == sscanf(argv[2], "%d", &log_size)) {
+            if (sc->cmd_data.dbg_log.data) {
+                kfree(sc->cmd_data.dbg_log.data);
+                memset(&sc->cmd_data.dbg_log, 0, sizeof(struct ssv_dbg_log));
+            }
+            if (log_size != 0) {
+                if (sc->cmd_data.dbg_log.data)
+                    kfree(sc->cmd_data.dbg_log.data);
+                total_log_size = log_size * 1024;
+                sc->cmd_data.dbg_log.data = (char *)kzalloc(total_log_size, GFP_KERNEL);
+                if (sc->cmd_data.dbg_log.data == NULL) {
+                    snprintf_res(cmd_data, " Fail to alloc dbg_log_size %d Kbytes\n", log_size);
+                    return 0;
+                }
+                sc->cmd_data.dbg_log.size = 0;
+                sc->cmd_data.dbg_log.totalsize = total_log_size;
+                sc->cmd_data.dbg_log.top = sc->cmd_data.dbg_log.data;
+                sc->cmd_data.dbg_log.tail = sc->cmd_data.dbg_log.data;
+                sc->cmd_data.dbg_log.end = &(sc->cmd_data.dbg_log.data[total_log_size]);
+            }
+            snprintf_res(cmd_data, " alloc dbg_log_size %d Kbytes\n", log_size);
+        } else {
+            snprintf_res(cmd_data, " log ram_size [size] Kbytes\n");
+        }
+        return 0;
+    } else if ((argc == 3) && (!strcmp(argv[1], "regw"))) {
+        if(!strcmp(argv[2], "enable")) {
+            sc->log_ctrl |= LOG_REGW;
+        } else {
+            sc->log_ctrl &= ~(LOG_REGW);
+        }
+        snprintf_res(cmd_data, "  log regw %s\n", ((sc->log_ctrl & LOG_REGW) ? "enable": "disable"));
+    } else {
+        snprintf_res(cmd_data, " log log_to_ram [enable | disable]\n");
+        snprintf_res(cmd_data, " log ram_size [size] kb\n");
+        snprintf_res(cmd_data, " log [category] [param] [enablel | disable]\n\n");
+        snprintf_res(cmd_data, " category: tx_desc, tx_frame, rx_desc, ampdu, beacon\n");
+        snprintf_res(cmd_data, "           rate_control, rate_report, hci, hwif, regw\n\n");
+        snprintf_res(cmd_data, " ampdu param: ssn, dbg, err\n");
+        return 0;
+    }
+    snprintf_res(cmd_data, "  log_ctrl 0x%x\n", sc->log_ctrl);
+    return 0;
+}
+static int ssv_cmd_chan(struct ssv_softc *sc, int argc, char *argv[])
+{
+    char *endp;
+    u32 ch;
+    struct ssv_cmd_data *cmd_data = &sc->cmd_data;
+    struct ieee80211_supported_band *sband;
+    struct ieee80211_channel *channel;
+    enum nl80211_channel_type type = NL80211_CHAN_HT20;
+    bool support_chan = false;
+    int i, band;
+    if ((argc == 2) || (argc == 3)) {
+        if (argc == 2) {
+            if (!strcmp(argv[1], "fixed") || !strcmp(argv[1], "auto")) {
+                if (!strcmp(argv[1], "fixed"))
+                    sc->sc_flags |= SC_OP_CHAN_FIXED;
+                if (!strcmp(argv[1], "auto"))
+                    sc->sc_flags &= ~SC_OP_CHAN_FIXED;
+                snprintf_res(cmd_data, "\n %s channel fixed\n", ((sc->sc_flags & SC_OP_CHAN_FIXED) ? "Force" : "Clear"));
+                return 0;
+            }
+        }
+        ch = simple_strtoul(argv[1], &endp, 0);
+        if (ch < 1) {
+            snprintf_res(cmd_data, "\n  Channel syntax error.\n");
+            return 0;
+        }
+        if (argc == 3) {
+            if (!strcmp(argv[2], "bw40")) {
+                if ((ch == 3) || (ch == 4) || (ch == 5) || (ch == 6) ||
+                    (ch == 7) || (ch == 8) || (ch == 9) || (ch == 10) ||
+                    (ch == 11) || (ch == 38) || (ch == 42) || (ch == 46) ||
+                    (ch == 50) || (ch == 54) || (ch == 58) || (ch == 62) ||
+                    (ch == 102) || (ch == 106) || (ch == 110) || (ch == 114) ||
+                    (ch == 118) || (ch == 122) || (ch == 126) || (ch == 130) ||
+                    (ch == 134) || (ch == 138) || (ch == 142) || (ch == 151) ||
+                    (ch == 155) || (ch == 159)) {
+                    type = NL80211_CHAN_HT40PLUS;
+                    ch = ch - 2;
+                } else {
+                    snprintf_res(cmd_data, "\n  Channel syntax error.\n");
+                    return 0;
+                }
+            } else if (!strcmp(argv[2], "+")) {
+                if ((ch >= 8) && (ch <= 13)) {
+                    snprintf_res(cmd_data, "\n  Channel syntax error.\n");
+                    return 0;
+                }
+                type = NL80211_CHAN_HT40PLUS;
+            } else if (!strcmp(argv[2], "-")) {
+                if ((ch >= 1) && (ch <= 4)) {
+                    snprintf_res(cmd_data, "\n  Channel syntax error.\n");
+                    return 0;
+                }
+                type = NL80211_CHAN_HT40MINUS;
+            } else {
+                snprintf_res(cmd_data, "\n  Channel syntax error.\n");
+                return 0;
+            }
+        }
+        if (argc == 2)
+            type = NL80211_CHAN_HT20;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,7,0)
+        for (band = 0; band < NUM_NL80211_BANDS; band++) {
+#else
+        for (band = 0; band < IEEE80211_NUM_BANDS; band++) {
+#endif
+            if ((band == INDEX_80211_BAND_5GHZ) && !(sc->sh->cfg.hw_caps & SSV6200_HW_CAP_5GHZ))
+                continue;
+            sband = &sc->sbands[band];
+            for (i = 0; i < sband->n_channels; i++) {
+                channel = &sband->channels[i];
+                if (ch == channel->hw_value)
+                    support_chan = true;
+            }
+        }
+        if (support_chan) {
+            struct ieee80211_channel chan;
+            memset(&chan, 0, sizeof( struct ieee80211_channel));
+            chan.hw_value = ch;
+            snprintf_res(cmd_data, "\n  switch to ch %d by command...\n", ch);
+            HAL_SET_CHANNEL(sc, &chan, type);
+            sc->hw_chan = chan.hw_value;
+            sc->hw_chan_type = type;
+            snprintf_res(cmd_data, "\n  DONE!!\n");
+        } else
+            snprintf_res(cmd_data, "\n  invalid ch %d\n", ch);
+    } else {
+        snprintf_res(cmd_data, "\n ch [chan_number] [chan_type]\n");
+    }
+    return 0;
+}
+static int ssv_cmd_cali(struct ssv_softc *sc, int argc, char *argv[])
+{
+    if((argc == 2) || (argc == 3)) {
+        HAL_CMD_CALI(sc->sh, argc, argv);
+    } else {
+        snprintf_res(&sc->cmd_data,"\n cali [do|show|dpd(show |enable|disable)] \n");
+    }
+    return 0;
+}
+static int ssv_cmd_init(struct ssv_softc *sc, int argc, char *argv[])
+{
+    if (!strcmp(argv[1], "mac")) {
+        SSV_PHY_ENABLE(sc->sh, false);
+        HAL_INIT_MAC(sc->sh);
+        SSV_PHY_ENABLE(sc->sh, true);
+        snprintf_res(&sc->cmd_data, "\n   reload mac DONE\n");
+    } else {
+        snprintf_res(&sc->cmd_data, "\n init [mac]\n");
+    }
+    return 0;
+}
+static int ssv_cmd_rc(struct ssv_softc *sc, int argc, char *argv[])
+{
+    HAL_CMD_RC(sc->sh, argc, argv);
+    return 0;
+}
+static int ssv_cmd_lpbk(struct ssv_softc *sc, int argc, char *argv[])
+{
+    HAL_CMD_LOOPBACK(sc->sh, argc, argv);
+    return 0;
+}
+static int ssv_cmd_hwinfo(struct ssv_softc *sc, int argc, char *argv[])
+{
+    HAL_CMD_HWINFO(sc->sh, argc, argv);
+    return 0;
+}
+static int ssv_cmd_cci(struct ssv_softc *sc, int argc, char *argv[])
+{
+    HAL_CMD_CCI(sc->sh, argc, argv);
+    return 0;
+}
+static int ssv_cmd_txgen(struct ssv_softc *sc, int argc, char *argv[])
+{
+    struct ssv_cmd_data *cmd_data = &sc->cmd_data;
+    u32 count = 0;
+    if (argc == 2) {
+        __string2u32(argv[1], &count, 0);
+    } else if (argc == 1) {
+        count = 1;
+    } else {
+        snprintf_res(cmd_data, "\n ./cli tx_gen [n] \n");
+        return 0;
+    }
+    if (count != 0) {
+        int i;
+        for (i = 0; i < count; i++) {
+            HAL_CMD_TXGEN(sc->sh);
+            mdelay(1);
+        }
+    }
+    snprintf_res(cmd_data, "\n tx_gen %d times done \n", count);
+    return 0;
+}
+static int ssv_cmd_rf(struct ssv_softc *sc, int argc, char *argv[])
+{
+    HAL_CMD_RF(sc->sh, argc, argv);
+    return 0;
+}
+static int ssv_cmd_hwq_limit(struct ssv_softc *sc, int argc, char *argv[])
+{
+    struct ssv_cmd_data *cmd_data = &sc->cmd_data;
+    if ((argc == 3)&&(!strcmp(argv[1], "bk")||!strcmp(argv[1], "be")||!strcmp(argv[1], "vi")||!strcmp(argv[1], "vo")||!strcmp(argv[1], "mng"))) {
+        HAL_CMD_HWQ_LIMIT(sc->sh, argc, argv);
+    } else {
+        snprintf_res(cmd_data, "%s [bk|be|vi|vo|mng] [queue limit]\n\n", argv[0]);
+    }
+    return 0;
+}
+static int ssv_cmd_efuse(struct ssv_softc *sc, int argc, char *argv[])
+{
+    HAL_CMD_EFUSE(sc->sh, argc, argv);
+    return 0;
+}
+#endif
+struct ssv_cmd_table cmd_table[] = {
+    { "help", ssv_cmd_help, "ssv6200 command usage.", 2048},
+    { "-h", ssv_cmd_help, "ssv6200 command usage.", 2048},
+    { "--help", ssv_cmd_help, "ssv6200 command usage.", 2048},
+    { "reg", ssv_cmd_reg, "ssv6200 register read/write.", 4096},
+    { "cfg", ssv_cmd_cfg, "ssv6200 configuration.", 256},
+    { "sta", ssv_cmd_sta, "svv6200 station info.", 4096},
+    { "dump", ssv_cmd_dump, "dump ssv6200 tables.", 8192},
+    { "hwq", ssv_cmd_hwq, "hardware queue staus", 512},
+#ifdef CONFIG_P2P_NOA
+    { "noa", ssv_cmd_noa, "config noa param", 512},
+#endif
+    { "irq", ssv_cmd_irq, "get sdio irq status.", 256},
+    { "mac", ssv_cmd_mac, "ieee80211 swmac.", 256},
+    { "hci", ssv_cmd_hci, "HCI command.", 1024},
+    { "sdio", ssv_cmd_sdio, "SDIO command.", 128},
+#if (defined (SSV_SUPPORT_HAL) || defined ( CONFIG_SSV_CABRIO_E))
+    { "iqk", ssv_cmd_iqk, "iqk command", 512},
+#endif
+    { "version",ssv_cmd_version,"version information", 512},
+    { "mib", ssv_cmd_mib, "mib counter related", 2048},
+    { "ps", ssv_cmd_power_saving, "power saving test", 256},
+    { "tool", ssv_cmd_tool, "ssv6200 tool register read/write.", 4096},
+    { "rxtput", ssv_cmd_rxtput, "test rx sdio throughput", 128},
+    { "txtput", ssv_cmd_txtput, "test tx sdio throughput", 256},
+    { "check", ssv_cmd_check, "dump all allocate packet buffer", 128},
+    { "rawpkt", ssv_cmd_rawpkt, "send raw packet", 512},
+    { "directack", ssv_cmd_directack, "directly ack control", 512},
+    { "txrxboost", ssv_cmd_txrxboost, "tx/rx kernel thread priority boost", 512},
+    { "txrx_skb_q", ssv_cmd_txrx_skb_q, "tx/rx skb queue control", 512},
+#ifdef SSV_SUPPORT_HAL
+    { "log", ssv_cmd_log, "enable debug log", 256},
+    { "ch", ssv_cmd_chan, "change channel by manual", 128},
+    { "cali", ssv_cmd_cali, "calibration for ssv6006", 4096},
+    { "init", ssv_cmd_init, "re-init ", 64},
+    { "rc", ssv_cmd_rc, "fix rate set for ssv6006", 4096},
+    { "lpbk", ssv_cmd_lpbk, "lpbk test for ssv6006", 4096},
+    { "hwmsg", ssv_cmd_hwinfo, "hw message for ssv6006", 4096},
+    { "cci", ssv_cmd_cci, "turn on/off cci", 128},
+    { "txgen", ssv_cmd_txgen, "auto gen tx ", 128},
+    { "rf", ssv_cmd_rf, "change parameters for rf tool", 512},
+    { "hwqlimit", ssv_cmd_hwq_limit, "Set software limit for hardware queue", 512},
+    { "efuse", ssv_cmd_efuse, "efuse read/write.", 2048},
+#endif
+    { NULL, NULL, NULL, 0},
+};
+int ssv_cmd_submit(struct ssv_cmd_data *cmd_data, char *cmd)
+{
+    struct ssv_cmd_table *sc_tbl;
+    char *pch, ch;
+    int ret, bf_size;
+    char *sg_cmd_buffer;
+    char *sg_argv[CLI_ARG_SIZE];
+    u32 sg_argc;
+    if (cmd_data->cmd_in_proc)
+        return -1;
+    sg_cmd_buffer = cmd;
+    for (sg_argc = 0, ch = 0, pch = sg_cmd_buffer;
+         (*pch!=0x00) && (sg_argc<CLI_ARG_SIZE); pch++ ) {
+        if ( (ch==0) && (*pch!=' ') ) {
+            ch = 1;
+            sg_argv[sg_argc] = pch;
+        }
+        if ( (ch==1) && (*pch==' ') ) {
+            *pch = 0x00;
+            ch = 0;
+            sg_argc ++;
+        }
+    }
+    if ( ch == 1) {
+        sg_argc ++;
+    } else if ( sg_argc > 0 ) {
+        *(pch-1) = ' ';
+    }
+    if ( sg_argc > 0 ) {
+        for( sc_tbl=cmd_table; sc_tbl->cmd; sc_tbl ++ ) {
+            if ( !strcmp(sg_argv[0], sc_tbl->cmd) ) {
+                struct ssv_softc *sc;
+                struct ssv6xxx_hci_info *hci;
+                sc = container_of(cmd_data, struct ssv_softc, cmd_data);
+                hci = &sc->sh->hci;
+                if ( (sc_tbl->cmd_func_ptr != ssv_cmd_cfg)
+                     && (!hci->dev || !hci->if_ops || !sc->platform_dev)) {
+                    cmd_data->ssv6xxx_result_buf = (char *)kzalloc(128, GFP_KERNEL);
+                    if (!cmd_data->ssv6xxx_result_buf)
+                        return -EFAULT;
+                    cmd_data->ssv6xxx_result_buf[0] = 0x00;
+                    snprintf_res(cmd_data, "Member of ssv6xxx_ifdebug_info is NULL !\n");
+                    return -1;
+                }
+                cmd_data->ssv6xxx_result_buf = (char *)kzalloc(sc_tbl->result_buffer_size, GFP_KERNEL);
+                if (!cmd_data->ssv6xxx_result_buf)
+                    return -EFAULT;
+                cmd_data->ssv6xxx_result_buf[0] = 0x00;
+                cmd_data->rsbuf_len = 0;
+                cmd_data->rsbuf_size = sc_tbl->result_buffer_size;
+                cmd_data->cmd_in_proc = true;
+                down_read(&sc->sta_info_sem);
+                ret = sc_tbl->cmd_func_ptr(sc, sg_argc, sg_argv);
+                up_read(&sc->sta_info_sem);
+                if (ret < 0) {
+                    strcpy(cmd_data->ssv6xxx_result_buf, "Invalid command !\n");
+                }
+                bf_size = strlen(cmd_data->ssv6xxx_result_buf);
+                if ((sc_tbl->result_buffer_size -1) <= bf_size) {
+                    cmd_data->rsbuf_len = 0;
+                    snprintf_res(cmd_data,
+                                 "\nALLOCATED BUFFER %d <= BUFFER USED +1 %d, OVERFLOW!!\n\n",
+                                 sc_tbl->result_buffer_size, bf_size+1);
+                } else {
+                    snprintf_res(cmd_data, "\nALLOCATED BUFFER %d , BUFFER USED %d\n\n",
+                                 sc_tbl->result_buffer_size, bf_size);
+                }
+                return 0;
+            }
+        }
+        cmd_data->ssv6xxx_result_buf = (char *)kzalloc(64, GFP_KERNEL);
+        if (!cmd_data->ssv6xxx_result_buf)
+            return -EFAULT;
+        cmd_data->ssv6xxx_result_buf[0] = 0x00;
+        cmd_data->rsbuf_len = 0;
+        cmd_data->rsbuf_size = 64;
+        cmd_data->cmd_in_proc = true;
+        snprintf_res(cmd_data, "Command not found !\n");
+        return -EFAULT;
+    } else {
+        cmd_data->ssv6xxx_result_buf = (char *)kzalloc(64, GFP_KERNEL);
+        if (!cmd_data->ssv6xxx_result_buf)
+            return -EFAULT;
+        cmd_data->ssv6xxx_result_buf[0] = 0x00;
+        cmd_data->rsbuf_len = 0;
+        cmd_data->rsbuf_size = 64;
+        cmd_data->cmd_in_proc = true;
+        snprintf_res(cmd_data, "./cli -h\n");
+    }
+    return 0;
+}
diff --git a/drivers/net/wireless/ssv6x5x/ssvdevice/ssv_cmd.h b/drivers/net/wireless/ssv6x5x/ssvdevice/ssv_cmd.h
new file mode 100644
index 000000000..2efe6f173
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/ssvdevice/ssv_cmd.h
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV_CMD_H_
+#define _SSV_CMD_H_
+#define CLI_ARG_SIZE 10
+#define PROC_DIR_ENTRY "tu_ssv"
+#define PROC_DEVICETYPE_ENTRY "ssv_devicetype"
+#define PROC_SSV_CMD_ENTRY "ssv_cmd"
+#define PROC_SSV_DBG_ENTRY "ssv_dbg_fs"
+#define PROC_SSV_FREQ_ENTRY "freq"
+#define PROC_SSV_P2P_ENTRY "p2p"
+#define MAX_CHARS_PER_LINE 256
+#ifdef CONFIG_SMART_ICOMM
+#define PROC_SI_ENTRY "smart_config"
+#define PROC_SI_SSID_ENTRY "si_ssid"
+#define PROC_SI_PASS_ENTRY "si_pass"
+#endif
+struct ssv_softc;
+struct ssv_cmd_table {
+    const char *cmd;
+    int (*cmd_func_ptr)(struct ssv_softc *sc, int, char **);
+    const char *usage;
+    const int result_buffer_size;
+};
+struct ssv6xxx_cfg_cmd_table {
+    u8 *cfg_cmd;
+    void *var;
+    u32 arg;
+    int (*translate_func)(u8 *, void *, u32);
+    u8 *def_val;
+};
+#define SSV_REG_READ1(ops,reg,val) \
+        (ops)->ifops->readreg((ops)->dev, reg, val)
+#define SSV_REG_WRITE1(ops,reg,val) \
+        (ops)->ifops->writereg((ops)->dev, reg, val)
+#define SSV_REG_SET_BITS1(ops,reg,set,clr) \
+    { \
+        u32 reg_val; \
+        SSV_REG_READ(ops, reg, &reg_val); \
+        reg_val &= ~(clr); \
+        reg_val |= (set); \
+        SSV_REG_WRITE(ops, reg, reg_val); \
+    }
+struct ssv_cmd_data;
+int ssv_cmd_submit(struct ssv_cmd_data *cmd_data, char *cmd);
+void snprintf_res(struct ssv_cmd_data *cmd_data, const char *fmt, ... );
+struct sk_buff *ssvdevice_skb_alloc(s32 len);
+void ssvdevice_skb_free(struct sk_buff *skb);
+#ifdef SSV_SUPPORT_HAL
+#define SSV_DUMP_WSID(_sh) HAL_DUMP_WSID(_sh)
+#define SSV_DUMP_DECISION(_sh) HAL_DUMP_DECISION(_sh)
+#define SSV_READ_FFOUT_CNT(_sh,_value,_value1,_value2) \
+                HAL_READ_FFOUT_CNT(_sh, _value, _value1, _value2)
+#define SSV_READ_IN_FFCNT(_sh,_value,_value1) HAL_READ_IN_FFCNT(_sh, _value, _value1)
+#define SSV_READ_ID_LEN_THRESHOLD(_sh,_tx_len,_rx_len) \
+    HAL_READ_ID_LEN_THRESHOLD(_sh, _tx_len, _rx_len)
+#define SSV_READ_TAG_STATUS(_sh,_ava_status) HAL_READ_TAG_STATUS(_sh, _ava_status)
+#define SSV_CMD_MIB(_sc,_argc,_argv) HAL_CMD_MIB(_sc, _argc, _argv)
+#define SSV_CMD_POWER_SAVING(_sc,_argc,_argv) HAL_CMD_POWER_SAVING(_sc, _argc, _argv)
+#define SSV_GET_FW_VERSION(_sh,_regval) HAL_GET_FW_VERSION(_sh, _regval)
+#define SSV_TXTPUT_SET_DESC(_sh,_skb) HAL_TXTPUT_SET_DESC(_sh, _skb)
+#define SSV_READRG_TXQ_INFO2(_ifops,_sh,_txq_info2) \
+                HAL_READRG_TXQ_INFO2(_sh , _txq_info2)
+#define SSV_GET_RD_ID_ADR(_sh,_id_base_addr) HAL_GET_RD_ID_ADR(_sh, _id_base_addr)
+#define SSV_GET_FFOUT_CNT(_sh,_value,_tag) HAL_GET_FFOUT_CNT(_sh, _value, _tag)
+#define SSV_GET_IN_FFCNT(_sh,_value,_tag) HAL_GET_IN_FFCNT(_sh, _value, _tag)
+#define SSV_AUTO_GEN_NULLPKT(_sh,_hwq) HAL_AUTO_GEN_NULLPKT(_sh, _hwq)
+#else
+#define SSV_DUMP_WSID(_sh) ssv6xxx_dump_wsid(_sh)
+#define SSV_DUMP_DECISION(_sh) ssv6xxx_dump_decision(_sh)
+#define SSV_READ_FFOUT_CNT(_sh,_value,_value1,_value2) \
+                ssv6xxx_read_ffout_cnt(_sh, _value, _value1, _value2)
+#define SSV_READ_IN_FFCNT(_sh,_value,_value1) ssv6xxx_read_in_ffcnt(_sh, _value, _value1)
+#define SSV_READ_ID_LEN_THRESHOLD(_sh,_tx_len,_rx_len) \
+    ssv6xxx_read_id_len_threshold(_sh, _tx_len, _rx_len)
+#define SSV_READ_TAG_STATUS(_sh,_ava_status) ssv6xxx_read_tag_status(_sh, _ava_status)
+#define SSV_CMD_MIB(_sh,_argc,argv) ssv6xxx_cmd_mib(_sh, _argc, argv)
+#define SSV_CMD_POWER_SAVING(_sh,_argc,argv) ssv6xxx_cmd_power_saving(_sh, _argc, argv)
+#define SSV_GET_FW_VERSION(_sh,_regval) ssv6xxx_get_fw_version(_sh, _regval)
+#define SSV_TXTPUT_SET_DESC(_sh,_skb) ssv6xxx_txtput_set_desc(_sh, _skb)
+#define SSV_READRG_TXQ_INFO2(_ifops,_sh,_txq_info2) \
+            SSV_REG_READ1(_ifops, ADR_TX_ID_ALL_INFO2, _txq_info2)
+#define SSV_GET_RD_ID_ADR(_sh,_id_base_addr) ssv6xxx_get_rd_id_adr(_id_base_addr)
+#define SSV_GET_FFOUT_CNT(_sh,_value,_tag) ssv6xxx_get_ffout_cnt(_value, _tag)
+#define SSV_GET_IN_FFCNT(_sh,_value,_tag) ssv6xxx_get_in_ffcnt(_value, _tag)
+#define SSV_AUTO_GEN_NULLPKT(_sh,_hwq) ssv6xxx_auto_gen_nullpkt(_sh, _hwq)
+#endif
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/ssvdevice/ssvdevice.c b/drivers/net/wireless/ssv6x5x/ssvdevice/ssvdevice.c
new file mode 100644
index 000000000..9c0b99d00
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/ssvdevice/ssvdevice.c
@@ -0,0 +1,510 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/slab.h>
+#include <linux/proc_fs.h>
+#include <asm/uaccess.h>
+#include <linux/errno.h>
+#ifdef CONFIG_DEBUG_FS
+#include <linux/debugfs.h>
+#endif
+#include "ssv_cmd.h"
+#include "ssv_cfg.h"
+#include <linux/fs.h>
+#include <asm/segment.h>
+#include <asm/uaccess.h>
+#include <linux/buffer_head.h>
+#include <linux/ctype.h>
+#include <ssv6200.h>
+#include <hci/hctrl.h>
+#include <smac/dev.h>
+#if (defined(CONFIG_SSV_SUPPORT_ANDROID)||defined(CONFIG_SSV_BUILD_AS_ONE_KO))
+#include <hci/ssv_hci.h>
+#include <smac/init.h>
+#include <hwif/sdio/sdio.h>
+#include <hwif/usb/usb.h>
+#endif
+MODULE_AUTHOR("iComm-semi, Ltd");
+MODULE_DESCRIPTION("Shared library for SSV wireless LAN cards.");
+MODULE_LICENSE("Dual BSD/GPL");
+static char *tu_stacfgpath = "/lib/firmware/ssv6x5x-wifi.cfg";
+EXPORT_SYMBOL(tu_stacfgpath);
+module_param(tu_stacfgpath, charp, 0000);
+MODULE_PARM_DESC(tu_stacfgpath, "Get path of sta cfg");
+char *tu_cfgfirmwarepath = NULL;
+EXPORT_SYMBOL(tu_cfgfirmwarepath);
+module_param(tu_cfgfirmwarepath, charp, 0000);
+MODULE_PARM_DESC(tu_cfgfirmwarepath, "Get firmware path");
+char* tu_ssv_initmac = NULL;
+EXPORT_SYMBOL(tu_ssv_initmac);
+module_param(tu_ssv_initmac, charp, 0644);
+MODULE_PARM_DESC(tu_ssv_initmac, "Wi-Fi MAC address");
+int ssv_rx_nr_recvbuff = 2;
+EXPORT_SYMBOL(ssv_rx_nr_recvbuff);
+module_param(ssv_rx_nr_recvbuff, int, 0644);
+MODULE_PARM_DESC(ssv_rx_nr_recvbuff, "USB RX buffer 1 ~ MAX_NR_RECVBUFF");
+int ssv_rx_use_wq = 0;
+EXPORT_SYMBOL(ssv_rx_use_wq);
+module_param(ssv_rx_use_wq, int, 0444);
+MODULE_PARM_DESC(ssv_rx_use_wq, "USB RX uses workqueue instead of tasklet");
+static struct proc_dir_entry *__ssv_procfs;
+extern struct ssv6xxx_cfg_cmd_table tu_cfg_cmds[];
+extern struct ssv6xxx_cfg tu_ssv_cfg;
+#define READ_CHUNK 32
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0)
+#define PDE_DATA(inode) ({ \
+    struct proc_dir_entry *dp = PDE(inode); \
+    data = dp->data; })
+#endif
+static char *p2pStatus = "0";
+static int ssv6xxx_p2p_open(struct inode *inode, struct file *filp)
+{
+    void *data = PDE_DATA(inode);
+    filp->private_data = data;
+    return 0;
+}
+static ssize_t ssv6xxx_p2p_read(struct file *filp, char __user *buffer,
+                                size_t count, loff_t *ppos)
+{
+    s32 ret, retlen, retval = 0;
+    retlen = strlen(p2pStatus)+1;
+    if (*ppos >= retlen)
+        goto out;
+    if (*ppos + count > retlen)
+        retlen = retlen - *ppos;
+    ret = copy_to_user(buffer, p2pStatus, retlen);
+    printk("%s: p2pStatus = %s \n", __func__,p2pStatus);
+    *ppos += retlen - ret;
+    retval = retlen - ret;
+out:
+    return retval;
+}
+static ssize_t ssv6xxx_p2p_write(struct file *filp, const char __user *buffer,
+                                 size_t count, loff_t *ppos)
+{
+    struct ssv_cmd_data *cmd_data = filp->private_data;
+    struct ssv_softc *sc = container_of(cmd_data, struct ssv_softc, cmd_data);
+    int enable = 0;
+    ssize_t retval= -ENOMEM;
+    if (*ppos != 0 || count > 255)
+        return 0;
+    if (copy_from_user(p2pStatus, buffer, count)) {
+        retval = -EFAULT;
+        goto out;
+    }
+    p2pStatus[count - 1] = 0;
+    enable = simple_strtol(p2pStatus, NULL, 10);
+    printk("%s: enable = %d\n", __func__, enable);
+    if(enable >= 0) {
+        sc->p2p_status = enable;
+        printk("p2p_status:%d\n",sc->p2p_status);
+    }
+    retval = count;
+out:
+    return retval;
+}
+static struct file_operations ssv6xxx_p2p_fops = {
+    .owner = THIS_MODULE,
+    .open = ssv6xxx_p2p_open,
+    .read = ssv6xxx_p2p_read,
+    .write = ssv6xxx_p2p_write,
+};
+static int ssv6xxx_freq_open(struct inode *inode, struct file *filp)
+{
+    void *data = PDE_DATA(inode);
+    filp->private_data = data;
+    return 0;
+}
+static ssize_t ssv6xxx_freq_read(struct file *filp, char __user *buffer,
+                                 size_t count, loff_t *ppos)
+{
+    struct ssv_cmd_data *cmd_data = filp->private_data;
+    struct ssv_softc *sc = container_of(cmd_data, struct ssv_softc, cmd_data);
+    char chan_freq[8]="0";
+    s32 ret, retlen, retval = 0;
+    u16 channel_freq = sc->channel_center_freq;
+    if(channel_freq > 0)
+        sprintf(chan_freq, "%u", channel_freq);
+    retlen = strlen(chan_freq)+1;
+    if (*ppos >= retlen)
+        goto out;
+    if (*ppos + count > retlen)
+        retlen = retlen - *ppos;
+    printk("freq=%s\n", chan_freq);
+    ret = copy_to_user(buffer, &chan_freq, retlen);
+    *ppos += retlen - ret;
+    retval = retlen - ret;
+out:
+    return retval;
+}
+static struct file_operations ssv6xxx_freq_fops = {
+    .owner = THIS_MODULE,
+    .open = ssv6xxx_freq_open,
+    .read = ssv6xxx_freq_read,
+};
+static int ssv6xxx_cmd_file_open(struct inode *inode, struct file *filp)
+{
+    void *data = PDE_DATA(inode);
+    filp->private_data = data;
+    return 0;
+}
+static ssize_t ssv6xxx_cmd_file_read(struct file *filp, char __user *buffer,
+                                     size_t count, loff_t *ppos)
+{
+    char *ssv6xxx_result_buf;
+    struct ssv_cmd_data *cmd_data = filp->private_data;
+    int len;
+    int ret = 0;
+    if (!(cmd_data->cmd_in_proc)) {
+        goto out;
+    }
+    ssv6xxx_result_buf = cmd_data->ssv6xxx_result_buf;
+    cmd_data->cmd_in_proc = false;
+    if (!ssv6xxx_result_buf) {
+        goto out;
+    }
+    cmd_data->ssv6xxx_result_buf = NULL;
+    if (*ppos != 0) {
+        goto free;
+    }
+    if (cmd_data->rsbuf_size < cmd_data->rsbuf_len)
+        cmd_data->rsbuf_len = cmd_data->rsbuf_size-1;
+    len = cmd_data->rsbuf_len + 1;
+    if (len == 1) {
+        goto free;
+    }
+    if (copy_to_user(buffer, ssv6xxx_result_buf, len)) {
+        ret = -EFAULT;
+        goto free;
+    }
+    ret = len;
+free:
+    kfree(ssv6xxx_result_buf);
+out:
+    if (atomic_read (&cmd_data->cli_count) > 0)
+        atomic_dec(&cmd_data->cli_count);
+    return ret;
+}
+static ssize_t ssv6xxx_cmd_file_write(struct file *filp, const char __user *buffer,
+                                      size_t count, loff_t *ppos)
+{
+    char *ssv6xxx_cmd_buf = NULL;
+    struct ssv_cmd_data *cmd_data = filp->private_data;
+    int i = 0;
+    if (*ppos != 0 || count > 255)
+        return 0;
+    ssv6xxx_cmd_buf = (char *)kzalloc(count, GFP_KERNEL);
+    if (!ssv6xxx_cmd_buf)
+        return 0;
+    ssv6xxx_cmd_buf[0] = 0x00;
+    if (copy_from_user(ssv6xxx_cmd_buf, buffer, count))
+        return -EFAULT;
+    while (atomic_read (&cmd_data->cli_count) != 0) {
+        msleep(1);
+        i++;
+        if (i > 1000) return -EFAULT;
+    }
+    atomic_add(2, &cmd_data->cli_count);
+    ssv6xxx_cmd_buf[count-1] = 0x00;
+    ssv_cmd_submit((struct ssv_cmd_data *)filp->private_data, ssv6xxx_cmd_buf);
+    kfree(ssv6xxx_cmd_buf);
+    return count;
+}
+size_t read_line(struct file *fp, char *buf, size_t size)
+{
+    size_t num_read = 0;
+    size_t total_read = 0;
+    char *buffer;
+    char ch;
+    size_t start_ignore = 0;
+    if (size <= 0 || buf == NULL) {
+        total_read = -EINVAL;
+        return -EINVAL;
+    }
+    buffer = buf;
+    for (;;) {
+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,4,37)
+        if (fp->f_op && fp->f_op->read)
+            num_read = fp->f_op->read(fp, &ch, 1, &fp->f_pos);
+#else
+        num_read = vfs_read(fp, &ch, 1, &fp->f_pos);
+#endif
+        if (num_read < 0) {
+            if (num_read == EINTR)
+                continue;
+            else
+                return -1;
+        } else if (num_read == 0) {
+            if (total_read == 0)
+                return 0;
+            else
+                break;
+        } else {
+            if (ch == '#')
+                start_ignore = 1;
+            if (total_read < size - 1) {
+                total_read++;
+                if (start_ignore)
+                    *buffer++ = '\0';
+                else
+                    *buffer++ = ch;
+            }
+            if (ch == '\n')
+                break;
+        }
+    }
+    *buffer = '\0';
+    return total_read;
+}
+int ischar(char *c)
+{
+    int is_char = 1;
+    while(*c) {
+        if (isalpha(*c) || isdigit(*c) || *c == '_' || *c == ':' || *c == '/' || *c == '.' || *c == '-')
+            c++;
+        else {
+            is_char = 0;
+            break;
+        }
+    }
+    return is_char;
+}
+static void _set_initial_cfg_default(void)
+{
+    size_t s;
+    for(s=0; tu_cfg_cmds[s].cfg_cmd != NULL; s++) {
+        if ((tu_cfg_cmds[s].def_val)!= NULL) {
+            tu_cfg_cmds[s].translate_func(tu_cfg_cmds[s].def_val,
+                                          tu_cfg_cmds[s].var, tu_cfg_cmds[s].arg);
+        }
+    }
+}
+static void _import_default_cfg (char *tu_stacfgpath)
+{
+    struct file *fp = (struct file *) NULL;
+    char buf[MAX_CHARS_PER_LINE], cfg_cmd[32], cfg_value[32];
+    mm_segment_t fs;
+    size_t s, read_len = 0, is_cmd_support = 0;
+    printk(KERN_INFO "ssv6x5x: importing configuration from %s", tu_stacfgpath);
+    if (tu_stacfgpath == NULL)
+        return;
+    memset(&tu_ssv_cfg, 0, sizeof(tu_ssv_cfg));
+    memset(buf, 0, sizeof(buf));
+    _set_initial_cfg_default();
+    fp = filp_open(tu_stacfgpath, O_RDONLY, 0);
+    if (IS_ERR(fp) || fp == NULL) {
+        printk(KERN_ERR "ERROR: filp_open\n");
+        WARN_ON(1);
+        return;
+    }
+    if (fp->f_path.dentry == NULL) {
+        printk(KERN_ERR "ERROR: dentry NULL\n");
+        WARN_ON(1);
+        return;
+    }
+    do {
+        memset(cfg_cmd, '\0', sizeof(cfg_cmd));
+        memset(cfg_value, '\0', sizeof(cfg_value));
+        fs = get_fs();
+        set_fs(get_ds());
+        read_len = read_line(fp, buf, MAX_CHARS_PER_LINE);
+        set_fs(fs);
+        sscanf(buf, "%s = %s", cfg_cmd, cfg_value);
+        if (!ischar(cfg_cmd) || !ischar(cfg_value)) {
+            printk("ERORR invalid parameter: %s\n", buf);
+            WARN_ON(1);
+            continue;
+        }
+        is_cmd_support = 0;
+        for(s=0; tu_cfg_cmds[s].cfg_cmd != NULL; s++) {
+            if (strcmp(tu_cfg_cmds[s].cfg_cmd, cfg_cmd)==0) {
+                tu_cfg_cmds[s].translate_func(cfg_value,
+                                              tu_cfg_cmds[s].var, tu_cfg_cmds[s].arg);
+                is_cmd_support = 1;
+                break;
+            }
+        }
+        if (!is_cmd_support && strlen(cfg_cmd) > 0) {
+            printk("ERROR Unsupported command: %s", cfg_cmd);
+            WARN_ON(1);
+        }
+    } while (read_len > 0);
+    filp_close(fp, NULL);
+}
+static struct file_operations ssv6xxx_cmd_fops = {
+    .owner = THIS_MODULE,
+    .open = ssv6xxx_cmd_file_open,
+    .read = ssv6xxx_cmd_file_read,
+    .write = ssv6xxx_cmd_file_write,
+};
+static void *ssv6xxx_dbg_seq_start(struct seq_file *s, loff_t *pos)
+{
+    struct ssv_cmd_data *cmd_data = s->private;
+    struct ssv_dbg_log *dbg_log = &cmd_data->dbg_log;
+    *pos = 0;
+    rcu_read_lock();
+    if (dbg_log->size <= 0)
+        return NULL;
+    return dbg_log;
+}
+static void *ssv6xxx_dbg_seq_next(struct seq_file *s, void *v, loff_t *pos)
+{
+    struct ssv_cmd_data *cmd_data = s->private;
+    struct ssv_dbg_log *dbg_log = &cmd_data->dbg_log;
+    ++*pos;
+    if (dbg_log->size <= 0)
+        return NULL;
+    return dbg_log;
+}
+static void ssv6xxx_dbg_seq_stop(struct seq_file *s, void *v)
+{
+    struct ssv_cmd_data *cmd_data = s->private;
+    struct ssv_dbg_log *dbg_log = &cmd_data->dbg_log;
+    if ((dbg_log == NULL) || (dbg_log->data == NULL) || (dbg_log->totalsize == 0)) {
+        rcu_read_lock();
+        return;
+    }
+    if (dbg_log->size == 0) {
+        dbg_log->top = dbg_log->data;
+        dbg_log->tail = dbg_log->data;
+        dbg_log->end = &(dbg_log->data[dbg_log->totalsize]);
+    }
+    seq_putc(s, '\n');
+    rcu_read_lock();
+    return;
+}
+static int ssv6xxx_dbg_seq_show(struct seq_file *s, void *v)
+{
+    struct ssv_dbg_log *dbg_log = (struct ssv_dbg_log *)v;
+    char *p = dbg_log->top;
+    seq_putc(s, *p++);
+    if (p == dbg_log->end)
+        p = dbg_log->data;
+    dbg_log->top = p;
+    dbg_log->size--;
+    return 0;
+}
+static struct seq_operations ssv6xxx_dbg_seq_fops = {
+    .start = ssv6xxx_dbg_seq_start,
+    .next = ssv6xxx_dbg_seq_next,
+    .stop = ssv6xxx_dbg_seq_stop,
+    .show = ssv6xxx_dbg_seq_show,
+};
+static int ssv6xxx_dbg_file_open(struct inode *inode, struct file *filp)
+{
+    int ret = 0;
+    struct seq_file *sf;
+    void *data = PDE_DATA(inode);
+    ret = seq_open(filp, &ssv6xxx_dbg_seq_fops);
+    if (!ret) {
+        sf = filp->private_data;
+        sf->private = data;
+    }
+    return ret;
+}
+static struct file_operations ssv6xxx_dbg_fops = {
+    .owner = THIS_MODULE,
+    .open = ssv6xxx_dbg_file_open,
+    .read = seq_read,
+    .llseek = seq_lseek,
+    .release = seq_release,
+};
+int ssv_init_cli (const char *dev_name, struct ssv_cmd_data *cmd_data)
+{
+    struct proc_dir_entry *proc_file_entry;
+    cmd_data->proc_dev_entry = proc_mkdir(dev_name, __ssv_procfs);
+    if (!cmd_data->proc_dev_entry)
+        printk("KERN_ERR" "Failed to create %s dev directory for CLI. \n", dev_name);
+    proc_file_entry = proc_create_data(PROC_SSV_CMD_ENTRY, S_IRUGO|S_IWUGO, cmd_data->proc_dev_entry, &ssv6xxx_cmd_fops, cmd_data);
+    if (proc_file_entry == NULL)
+        printk(KERN_ERR "Failed to create %s for CLI.\n", PROC_SSV_CMD_ENTRY);
+    proc_file_entry = proc_create_data(PROC_SSV_DBG_ENTRY, S_IRUGO|S_IWUGO, cmd_data->proc_dev_entry, &ssv6xxx_dbg_fops, cmd_data);
+    if (proc_file_entry == NULL)
+        printk(KERN_ERR "Failed to create %s for SSV DBG.\n", PROC_SSV_DBG_ENTRY);
+    proc_file_entry = proc_create_data(PROC_SSV_FREQ_ENTRY, S_IRUGO|S_IWUGO, cmd_data->proc_dev_entry, &ssv6xxx_freq_fops, cmd_data);
+    if (proc_file_entry == NULL)
+        printk(KERN_ERR "Failed to create %s for SSV FREQ.\n", PROC_SSV_FREQ_ENTRY);
+    proc_file_entry = proc_create_data(PROC_SSV_P2P_ENTRY, S_IRUGO|S_IWUGO, cmd_data->proc_dev_entry, &ssv6xxx_p2p_fops, cmd_data);
+    if (proc_file_entry == NULL)
+        printk(KERN_ERR "Failed to create %s for SSV P2P.\n", PROC_SSV_P2P_ENTRY);
+    atomic_set(&cmd_data->cli_count, 0);
+    return 0;
+}
+EXPORT_SYMBOL(ssv_init_cli);
+int ssv_deinit_cli (const char *dev_name, struct ssv_cmd_data *cmd_data)
+{
+    remove_proc_entry(PROC_SSV_DBG_ENTRY, cmd_data->proc_dev_entry);
+    remove_proc_entry(PROC_SSV_CMD_ENTRY, cmd_data->proc_dev_entry);
+    remove_proc_entry(PROC_SSV_FREQ_ENTRY, cmd_data->proc_dev_entry);
+    remove_proc_entry(PROC_SSV_P2P_ENTRY, cmd_data->proc_dev_entry);
+    remove_proc_entry(dev_name, __ssv_procfs);
+    return 0;
+}
+EXPORT_SYMBOL(ssv_deinit_cli);
+#if (defined(CONFIG_SSV_SUPPORT_ANDROID)||defined(CONFIG_SSV_BUILD_AS_ONE_KO))
+int tu_ssvdevice_init(void)
+#else
+static int __init tu_ssvdevice_init(void)
+#endif
+{
+    _import_default_cfg(tu_stacfgpath);
+    __ssv_procfs = proc_mkdir(PROC_DIR_ENTRY, NULL);
+    if (!__ssv_procfs)
+        return -ENOMEM;
+#if (defined(CONFIG_SSV_SUPPORT_ANDROID)||defined(CONFIG_SSV_BUILD_AS_ONE_KO))
+    {
+        int ret;
+        ret = tu_ssv6xxx_hci_init();
+        if(!ret) {
+            ret = tu_ssv6xxx_init();
+        }
+        if(!ret) {
+            ret = tu_ssv6xxx_sdio_init();
+#if (defined(SSV_SUPPORT_SSV6006))
+            ret = ssv6xxx_usb_init();
+#endif
+        }
+        return ret;
+    }
+#endif
+    return 0;
+}
+#if (defined(CONFIG_SSV_SUPPORT_ANDROID)||defined(CONFIG_SSV_BUILD_AS_ONE_KO))
+void tu_ssvdevice_exit(void)
+#else
+static void __exit tu_ssvdevice_exit(void)
+#endif
+{
+#if (defined(CONFIG_SSV_SUPPORT_ANDROID)||defined(CONFIG_SSV_BUILD_AS_ONE_KO))
+    tu_ssv6xxx_exit();
+    tu_ssv6xxx_hci_exit();
+    tu_ssv6xxx_sdio_exit();
+#if (defined(SSV_SUPPORT_SSV6006))
+    ssv6xxx_usb_exit();
+#endif
+#endif
+    remove_proc_entry(PROC_DIR_ENTRY, NULL);
+}
+#if (defined(CONFIG_SSV_SUPPORT_ANDROID)||defined(CONFIG_SSV_BUILD_AS_ONE_KO))
+EXPORT_SYMBOL(tu_ssvdevice_init);
+EXPORT_SYMBOL(tu_ssvdevice_exit);
+#else
+module_init(tu_ssvdevice_init);
+module_exit(tu_ssvdevice_exit);
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/sta.cfg b/drivers/net/wireless/ssv6x5x/sta.cfg
new file mode 100755
index 000000000..3d776b6f8
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/sta.cfg
@@ -0,0 +1,74 @@
+
+hw_mac = 00:a5:b5:ce:d7:f6
+hw_mac_2 = 00:a5:b5:ce:d7:f7
+
+############################################################
+# MAC address
+#
+# Priority 1. From wifi.cfg [ hw_mac & hw_mac_2 ]
+#
+# Priority 2. From e-fuse[ON/OFF switch by wifi.cfg]
+#
+# Priority 3. From insert module parameter
+#
+# Priority 4. From external file path
+#   path only support some special charater "_" ":" "/" "." "-"
+#
+# Priority 5. Default[Software mode]
+#
+#   0. => 00:33:33:33:33:33
+#   1. => Always random
+#   2. => First random and write to file[Default path mac_output_path]
+#
+############################################################
+#ignore_efuse_mac = 1
+#mac_address_path = /xxxx/xxxx
+#mac_address_mode = 0
+#mac_output_path = /data/wifimac
+
+##################################################
+# Firmware setting
+# Priority.1 insmod parameter "cfgfirmwarepath"
+# Priority.2 firmware_path
+# Priority.3 default firmware
+##################################################
+#firmware_path = /lib/firmware/
+
+##################################################
+# Hardware setting
+#
+#volt regulator(DCDC-0 LDO-1)
+#
+#Internal VOLT([MP4-4.2V]-42 [ON BOARD IC-3.3V]-33)
+#
+##################################################
+#xtal_clock = 26
+#volt_regulator = 1
+
+##################################################
+# Default channel after wifi on
+# value range: [1 ~ 14]
+##################################################
+#def_chan = 6
+
+##################################################
+# Hardware Capability Settings:
+##################################################
+
+use_wpa2_only = 1
+
+##################################################
+# TX power level setting [0-14]
+# The larger the number the smaller the TX power
+# 0 - The maximum power
+# 1 level = -0.5db
+##################################################
+wifi_tx_gain_level_b = 6
+wifi_tx_gain_level_gn = 4
+
+##################################################
+# Import extenal configuration(UP to 64 groups)
+# example:
+#    register = CE010010:91919191
+#    register = 00CC0010:00091919
+##################################################
diff --git a/drivers/net/wireless/ssv6x5x/tags b/drivers/net/wireless/ssv6x5x/tags
new file mode 100755
index 000000000..5f1d66a64
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/tags
@@ -0,0 +1,89917 @@
+!_TAG_FILE_FORMAT	2	/extended format; --format=1 will not append ;" to lines/
+!_TAG_FILE_SORTED	1	/0=unsorted, 1=sorted, 2=foldcase/
+!_TAG_PROGRAM_AUTHOR	Darren Hiebert	/dhiebert@users.sourceforge.net/
+!_TAG_PROGRAM_NAME	Exuberant Ctags	//
+!_TAG_PROGRAM_URL	http://ctags.sourceforge.net	/official site/
+!_TAG_PROGRAM_VERSION	5.9~svn20110310	//
+ABT_SW_RST_N_HI	include/ssv6200_aux.h	17719;"	d
+ABT_SW_RST_N_I_MSK	include/ssv6200_aux.h	17717;"	d
+ABT_SW_RST_N_MSK	include/ssv6200_aux.h	17716;"	d
+ABT_SW_RST_N_SFT	include/ssv6200_aux.h	17718;"	d
+ABT_SW_RST_N_SZ	include/ssv6200_aux.h	17720;"	d
+ACC_RD_LEN_HI	include/ssv6200_aux.h	17849;"	d
+ACC_RD_LEN_I_MSK	include/ssv6200_aux.h	17847;"	d
+ACC_RD_LEN_MSK	include/ssv6200_aux.h	17846;"	d
+ACC_RD_LEN_SFT	include/ssv6200_aux.h	17848;"	d
+ACC_RD_LEN_SZ	include/ssv6200_aux.h	17850;"	d
+ACC_WR_LEN_HI	include/ssv6200_aux.h	17844;"	d
+ACC_WR_LEN_I_MSK	include/ssv6200_aux.h	17842;"	d
+ACC_WR_LEN_MSK	include/ssv6200_aux.h	17841;"	d
+ACC_WR_LEN_SFT	include/ssv6200_aux.h	17843;"	d
+ACC_WR_LEN_SZ	include/ssv6200_aux.h	17845;"	d
+ACK_GEN_DUR_HI	include/ssv6200_aux.h	7219;"	d
+ACK_GEN_DUR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6394;"	d
+ACK_GEN_DUR_I_MSK	include/ssv6200_aux.h	7217;"	d
+ACK_GEN_DUR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6392;"	d
+ACK_GEN_DUR_MSK	include/ssv6200_aux.h	7216;"	d
+ACK_GEN_DUR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6391;"	d
+ACK_GEN_DUR_SFT	include/ssv6200_aux.h	7218;"	d
+ACK_GEN_DUR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6393;"	d
+ACK_GEN_DUR_SZ	include/ssv6200_aux.h	7220;"	d
+ACK_GEN_DUR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6395;"	d
+ACK_GEN_EN_HI	include/ssv6200_aux.h	7209;"	d
+ACK_GEN_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6384;"	d
+ACK_GEN_EN_I_MSK	include/ssv6200_aux.h	7207;"	d
+ACK_GEN_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6382;"	d
+ACK_GEN_EN_MSK	include/ssv6200_aux.h	7206;"	d
+ACK_GEN_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6381;"	d
+ACK_GEN_EN_SFT	include/ssv6200_aux.h	7208;"	d
+ACK_GEN_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6383;"	d
+ACK_GEN_EN_SZ	include/ssv6200_aux.h	7210;"	d
+ACK_GEN_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6385;"	d
+ACK_GEN_INFO_HI	include/ssv6200_aux.h	7224;"	d
+ACK_GEN_INFO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6399;"	d
+ACK_GEN_INFO_I_MSK	include/ssv6200_aux.h	7222;"	d
+ACK_GEN_INFO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6397;"	d
+ACK_GEN_INFO_MSK	include/ssv6200_aux.h	7221;"	d
+ACK_GEN_INFO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6396;"	d
+ACK_GEN_INFO_SFT	include/ssv6200_aux.h	7223;"	d
+ACK_GEN_INFO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6398;"	d
+ACK_GEN_INFO_SZ	include/ssv6200_aux.h	7225;"	d
+ACK_GEN_INFO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6400;"	d
+ACK_GEN_RA_31_0_HI	include/ssv6200_aux.h	7229;"	d
+ACK_GEN_RA_31_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6404;"	d
+ACK_GEN_RA_31_0_I_MSK	include/ssv6200_aux.h	7227;"	d
+ACK_GEN_RA_31_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6402;"	d
+ACK_GEN_RA_31_0_MSK	include/ssv6200_aux.h	7226;"	d
+ACK_GEN_RA_31_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6401;"	d
+ACK_GEN_RA_31_0_SFT	include/ssv6200_aux.h	7228;"	d
+ACK_GEN_RA_31_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6403;"	d
+ACK_GEN_RA_31_0_SZ	include/ssv6200_aux.h	7230;"	d
+ACK_GEN_RA_31_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6405;"	d
+ACK_GEN_RA_47_32_HI	include/ssv6200_aux.h	7234;"	d
+ACK_GEN_RA_47_32_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6409;"	d
+ACK_GEN_RA_47_32_I_MSK	include/ssv6200_aux.h	7232;"	d
+ACK_GEN_RA_47_32_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6407;"	d
+ACK_GEN_RA_47_32_MSK	include/ssv6200_aux.h	7231;"	d
+ACK_GEN_RA_47_32_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6406;"	d
+ACK_GEN_RA_47_32_SFT	include/ssv6200_aux.h	7233;"	d
+ACK_GEN_RA_47_32_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6408;"	d
+ACK_GEN_RA_47_32_SZ	include/ssv6200_aux.h	7235;"	d
+ACK_GEN_RA_47_32_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6410;"	d
+ACK_LEN	smac/dev.h	158;"	d
+ACTION_DO_NOTHING	smac/dev_tbl.h	30;"	d
+ACTION_RESET_NAV	smac/dev_tbl.h	32;"	d
+ACTION_SIGNAL_ACK	smac/dev_tbl.h	33;"	d
+ACTION_UPDATE_NAV	smac/dev_tbl.h	31;"	d
+ADDID_LEN	smac/sec_wpi.h	23;"	d
+ADDR1A_SEL_HI	include/ssv6200_aux.h	7339;"	d
+ADDR1A_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6439;"	d
+ADDR1A_SEL_I_MSK	include/ssv6200_aux.h	7337;"	d
+ADDR1A_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6437;"	d
+ADDR1A_SEL_MSK	include/ssv6200_aux.h	7336;"	d
+ADDR1A_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6436;"	d
+ADDR1A_SEL_SFT	include/ssv6200_aux.h	7338;"	d
+ADDR1A_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6438;"	d
+ADDR1A_SEL_SZ	include/ssv6200_aux.h	7340;"	d
+ADDR1A_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6440;"	d
+ADDR1B_SEL_HI	include/ssv6200_aux.h	7354;"	d
+ADDR1B_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6454;"	d
+ADDR1B_SEL_I_MSK	include/ssv6200_aux.h	7352;"	d
+ADDR1B_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6452;"	d
+ADDR1B_SEL_MSK	include/ssv6200_aux.h	7351;"	d
+ADDR1B_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6451;"	d
+ADDR1B_SEL_SFT	include/ssv6200_aux.h	7353;"	d
+ADDR1B_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6453;"	d
+ADDR1B_SEL_SZ	include/ssv6200_aux.h	7355;"	d
+ADDR1B_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6455;"	d
+ADDR2A_SEL_HI	include/ssv6200_aux.h	7344;"	d
+ADDR2A_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6444;"	d
+ADDR2A_SEL_I_MSK	include/ssv6200_aux.h	7342;"	d
+ADDR2A_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6442;"	d
+ADDR2A_SEL_MSK	include/ssv6200_aux.h	7341;"	d
+ADDR2A_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6441;"	d
+ADDR2A_SEL_SFT	include/ssv6200_aux.h	7343;"	d
+ADDR2A_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6443;"	d
+ADDR2A_SEL_SZ	include/ssv6200_aux.h	7345;"	d
+ADDR2A_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6445;"	d
+ADDR2B_SEL_HI	include/ssv6200_aux.h	7359;"	d
+ADDR2B_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6459;"	d
+ADDR2B_SEL_I_MSK	include/ssv6200_aux.h	7357;"	d
+ADDR2B_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6457;"	d
+ADDR2B_SEL_MSK	include/ssv6200_aux.h	7356;"	d
+ADDR2B_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6456;"	d
+ADDR2B_SEL_SFT	include/ssv6200_aux.h	7358;"	d
+ADDR2B_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6458;"	d
+ADDR2B_SEL_SZ	include/ssv6200_aux.h	7360;"	d
+ADDR2B_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6460;"	d
+ADDR3A_SEL_HI	include/ssv6200_aux.h	7349;"	d
+ADDR3A_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6449;"	d
+ADDR3A_SEL_I_MSK	include/ssv6200_aux.h	7347;"	d
+ADDR3A_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6447;"	d
+ADDR3A_SEL_MSK	include/ssv6200_aux.h	7346;"	d
+ADDR3A_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6446;"	d
+ADDR3A_SEL_SFT	include/ssv6200_aux.h	7348;"	d
+ADDR3A_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6448;"	d
+ADDR3A_SEL_SZ	include/ssv6200_aux.h	7350;"	d
+ADDR3A_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6450;"	d
+ADDR3B_SEL_HI	include/ssv6200_aux.h	7364;"	d
+ADDR3B_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6464;"	d
+ADDR3B_SEL_I_MSK	include/ssv6200_aux.h	7362;"	d
+ADDR3B_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6462;"	d
+ADDR3B_SEL_MSK	include/ssv6200_aux.h	7361;"	d
+ADDR3B_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6461;"	d
+ADDR3B_SEL_SFT	include/ssv6200_aux.h	7363;"	d
+ADDR3B_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6463;"	d
+ADDR3B_SEL_SZ	include/ssv6200_aux.h	7365;"	d
+ADDR3B_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6465;"	d
+ADDR3C_SEL_HI	include/ssv6200_aux.h	7369;"	d
+ADDR3C_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6469;"	d
+ADDR3C_SEL_I_MSK	include/ssv6200_aux.h	7367;"	d
+ADDR3C_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6467;"	d
+ADDR3C_SEL_MSK	include/ssv6200_aux.h	7366;"	d
+ADDR3C_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6466;"	d
+ADDR3C_SEL_SFT	include/ssv6200_aux.h	7368;"	d
+ADDR3C_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6468;"	d
+ADDR3C_SEL_SZ	include/ssv6200_aux.h	7370;"	d
+ADDR3C_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6470;"	d
+ADDRESS_OFFSET	include/hal.h	33;"	d
+ADDRESS_OFFSET	smac/dev.c	208;"	d	file:
+ADD_LEN_HI	include/ssv6200_aux.h	6344;"	d
+ADD_LEN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5589;"	d
+ADD_LEN_I_MSK	include/ssv6200_aux.h	6342;"	d
+ADD_LEN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5587;"	d
+ADD_LEN_MSK	include/ssv6200_aux.h	6341;"	d
+ADD_LEN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5586;"	d
+ADD_LEN_SFT	include/ssv6200_aux.h	6343;"	d
+ADD_LEN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5588;"	d
+ADD_LEN_SZ	include/ssv6200_aux.h	6345;"	d
+ADD_LEN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5590;"	d
+ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1512;"	d
+ADR_2_4G_LDO_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1513;"	d
+ADR_2_4G_RX_FE_HG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1521;"	d
+ADR_2_4G_RX_FE_LG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1523;"	d
+ADR_2_4G_RX_FE_MG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1522;"	d
+ADR_2_4G_RX_FE_ULG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1524;"	d
+ADR_2_4G_RX_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1517;"	d
+ADR_2_4G_TRX_DUMMY_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1590;"	d
+ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1511;"	d
+ADR_2_4G_TX_FE_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1518;"	d
+ADR_2_4G_TX_PA_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1519;"	d
+ADR_2_4G_TX_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1520;"	d
+ADR_5G_CALIBRATION_GAIN_REGISTER1	smac/hal/ssv6006c/ssv6006C_reg.h	1641;"	d
+ADR_5G_CALIBRATION_TIMER_GAIN_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1640;"	d
+ADR_5G_DCOC_IDAC_REGISTER1	smac/hal/ssv6006c/ssv6006C_reg.h	1616;"	d
+ADR_5G_DCOC_IDAC_REGISTER10	smac/hal/ssv6006c/ssv6006C_reg.h	1625;"	d
+ADR_5G_DCOC_IDAC_REGISTER11	smac/hal/ssv6006c/ssv6006C_reg.h	1626;"	d
+ADR_5G_DCOC_IDAC_REGISTER12	smac/hal/ssv6006c/ssv6006C_reg.h	1627;"	d
+ADR_5G_DCOC_IDAC_REGISTER13	smac/hal/ssv6006c/ssv6006C_reg.h	1628;"	d
+ADR_5G_DCOC_IDAC_REGISTER14	smac/hal/ssv6006c/ssv6006C_reg.h	1629;"	d
+ADR_5G_DCOC_IDAC_REGISTER15	smac/hal/ssv6006c/ssv6006C_reg.h	1630;"	d
+ADR_5G_DCOC_IDAC_REGISTER16	smac/hal/ssv6006c/ssv6006C_reg.h	1631;"	d
+ADR_5G_DCOC_IDAC_REGISTER17	smac/hal/ssv6006c/ssv6006C_reg.h	1632;"	d
+ADR_5G_DCOC_IDAC_REGISTER18	smac/hal/ssv6006c/ssv6006C_reg.h	1633;"	d
+ADR_5G_DCOC_IDAC_REGISTER19	smac/hal/ssv6006c/ssv6006C_reg.h	1634;"	d
+ADR_5G_DCOC_IDAC_REGISTER2	smac/hal/ssv6006c/ssv6006C_reg.h	1617;"	d
+ADR_5G_DCOC_IDAC_REGISTER20	smac/hal/ssv6006c/ssv6006C_reg.h	1635;"	d
+ADR_5G_DCOC_IDAC_REGISTER21	smac/hal/ssv6006c/ssv6006C_reg.h	1636;"	d
+ADR_5G_DCOC_IDAC_REGISTER3	smac/hal/ssv6006c/ssv6006C_reg.h	1618;"	d
+ADR_5G_DCOC_IDAC_REGISTER4	smac/hal/ssv6006c/ssv6006C_reg.h	1619;"	d
+ADR_5G_DCOC_IDAC_REGISTER5	smac/hal/ssv6006c/ssv6006C_reg.h	1620;"	d
+ADR_5G_DCOC_IDAC_REGISTER6	smac/hal/ssv6006c/ssv6006C_reg.h	1621;"	d
+ADR_5G_DCOC_IDAC_REGISTER7	smac/hal/ssv6006c/ssv6006C_reg.h	1622;"	d
+ADR_5G_DCOC_IDAC_REGISTER8	smac/hal/ssv6006c/ssv6006C_reg.h	1623;"	d
+ADR_5G_DCOC_IDAC_REGISTER9	smac/hal/ssv6006c/ssv6006C_reg.h	1624;"	d
+ADR_5G_LDO_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1595;"	d
+ADR_5G_MODE_DECODER_TIMER_REGISTER1	smac/hal/ssv6006c/ssv6006C_reg.h	1637;"	d
+ADR_5G_R2T_TIMER_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1639;"	d
+ADR_5G_RX_FE_HG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1600;"	d
+ADR_5G_RX_FE_LG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1602;"	d
+ADR_5G_RX_FE_MG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1601;"	d
+ADR_5G_RX_FE_ULG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1603;"	d
+ADR_5G_RX_LNA_LOAD_SCA_CONTROL	smac/hal/ssv6006c/ssv6006C_reg.h	1648;"	d
+ADR_5G_RX_LNA_MATCHING_SCA_CONTROL	smac/hal/ssv6006c/ssv6006C_reg.h	1647;"	d
+ADR_5G_RX_REGISTER1	smac/hal/ssv6006c/ssv6006C_reg.h	1596;"	d
+ADR_5G_RX_REGISTER2	smac/hal/ssv6006c/ssv6006C_reg.h	1597;"	d
+ADR_5G_T2R_TIMER_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1638;"	d
+ADR_5G_TRX_DUMMY_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1642;"	d
+ADR_5G_TRX_MANUAL_ENABLE_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1594;"	d
+ADR_5G_TX_DAC_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1604;"	d
+ADR_5G_TX_FE_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1598;"	d
+ADR_5G_TX_GAIN_PAFB_CONTROL	smac/hal/ssv6006c/ssv6006C_reg.h	1651;"	d
+ADR_5G_TX_PGA_CAPSW_CONTROL_I	smac/hal/ssv6006c/ssv6006C_reg.h	1649;"	d
+ADR_5G_TX_PGA_CAPSW_CONTROL_II	smac/hal/ssv6006c/ssv6006C_reg.h	1650;"	d
+ADR_5G_TX_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1599;"	d
+ADR_ABB_REGISTER_1	include/ssv6200_reg.h	1183;"	d
+ADR_ABB_REGISTER_2	include/ssv6200_reg.h	1184;"	d
+ADR_ACK_GEN_EN	include/ssv6200_reg.h	594;"	d
+ADR_ACK_GEN_EN	smac/hal/ssv6006c/ssv6006C_reg.h	715;"	d
+ADR_ACK_GEN_PARA	include/ssv6200_reg.h	595;"	d
+ADR_ACK_GEN_PARA	smac/hal/ssv6006c/ssv6006C_reg.h	716;"	d
+ADR_ACK_GEN_RA_0	include/ssv6200_reg.h	596;"	d
+ADR_ACK_GEN_RA_0	smac/hal/ssv6006c/ssv6006C_reg.h	717;"	d
+ADR_ACK_GEN_RA_1	include/ssv6200_reg.h	597;"	d
+ADR_ACK_GEN_RA_1	smac/hal/ssv6006c/ssv6006C_reg.h	718;"	d
+ADR_AHB_BRG_STATUS	include/ssv6200_reg.h	125;"	d
+ADR_AHB_FEN_ADDR	include/ssv6200_reg.h	135;"	d
+ADR_AHB_ILLFEN_STATUS	include/ssv6200_reg.h	136;"	d
+ADR_AHB_ILL_ADDR	include/ssv6200_reg.h	134;"	d
+ADR_ALC_ABORT	smac/hal/ssv6006c/ssv6006C_reg.h	2141;"	d
+ADR_ALC_ID_INF1	include/ssv6200_reg.h	962;"	d
+ADR_ALC_ID_INF1	smac/hal/ssv6006c/ssv6006C_reg.h	2140;"	d
+ADR_ALC_ID_INFO	include/ssv6200_reg.h	961;"	d
+ADR_ALC_ID_INFO	smac/hal/ssv6006c/ssv6006C_reg.h	2139;"	d
+ADR_ALC_NOCHG_ID_STATUS	include/ssv6200_reg.h	1257;"	d
+ADR_ALC_RLS_ABORT	include/ssv6200_reg.h	1230;"	d
+ADR_ALC_RLS_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	2142;"	d
+ADR_ALC_STA	include/ssv6200_reg.h	936;"	d
+ADR_ALC_STA	smac/hal/ssv6006c/ssv6006C_reg.h	2114;"	d
+ADR_ALL_SOFTWARE_RESET	include/ssv6200_reg.h	771;"	d
+ADR_ALL_SOFTWARE_RESET	smac/hal/ssv6006c/ssv6006C_reg.h	940;"	d
+ADR_ALWAYS_ON_CFG00	smac/hal/ssv6006c/ssv6006C_reg.h	284;"	d
+ADR_AMPDU_SCOREBOAD_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	726;"	d
+ADR_AMPDU_SIG	include/ssv6200_reg.h	621;"	d
+ADR_AMPDU_SIG	smac/hal/ssv6006c/ssv6006C_reg.h	733;"	d
+ADR_AUDIO_CTRL_REG	smac/hal/ssv6006c/ssv6006C_reg.h	1685;"	d
+ADR_AUDIO_PDM_REG	smac/hal/ssv6006c/ssv6006C_reg.h	1686;"	d
+ADR_BA_CTRL	include/ssv6200_reg.h	586;"	d
+ADR_BA_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	707;"	d
+ADR_BA_SB0	include/ssv6200_reg.h	591;"	d
+ADR_BA_SB0	smac/hal/ssv6006c/ssv6006C_reg.h	712;"	d
+ADR_BA_SB1	include/ssv6200_reg.h	592;"	d
+ADR_BA_SB1	smac/hal/ssv6006c/ssv6006C_reg.h	713;"	d
+ADR_BA_ST_SEQ	include/ssv6200_reg.h	590;"	d
+ADR_BA_ST_SEQ	smac/hal/ssv6006c/ssv6006C_reg.h	711;"	d
+ADR_BA_TA_0	include/ssv6200_reg.h	587;"	d
+ADR_BA_TA_0	smac/hal/ssv6006c/ssv6006C_reg.h	708;"	d
+ADR_BA_TA_1	include/ssv6200_reg.h	588;"	d
+ADR_BA_TA_1	smac/hal/ssv6006c/ssv6006C_reg.h	709;"	d
+ADR_BA_TID	include/ssv6200_reg.h	589;"	d
+ADR_BA_TID	smac/hal/ssv6006c/ssv6006C_reg.h	710;"	d
+ADR_BIST_BIST_CTRL	include/ssv6200_reg.h	126;"	d
+ADR_BIST_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	348;"	d
+ADR_BIST_CTRL1	smac/hal/ssv6006c/ssv6006C_reg.h	349;"	d
+ADR_BIST_CTRL2	smac/hal/ssv6006c/ssv6006C_reg.h	350;"	d
+ADR_BIST_MODE_REG_IN	include/ssv6200_reg.h	127;"	d
+ADR_BIST_MODE_REG_IN_MMU	include/ssv6200_reg.h	142;"	d
+ADR_BIST_MODE_REG_OUT	include/ssv6200_reg.h	128;"	d
+ADR_BIST_MODE_REG_OUT_MMU	include/ssv6200_reg.h	143;"	d
+ADR_BIST_MONITOR_BUS_LSB	include/ssv6200_reg.h	129;"	d
+ADR_BIST_MONITOR_BUS_MMU	include/ssv6200_reg.h	144;"	d
+ADR_BIST_MONITOR_BUS_MSB	include/ssv6200_reg.h	130;"	d
+ADR_BOOT	include/ssv6200_reg.h	115;"	d
+ADR_BOOT	smac/hal/ssv6006c/ssv6006C_reg.h	237;"	d
+ADR_BOOTSTRAP_SAMPLE	smac/hal/ssv6006c/ssv6006C_reg.h	245;"	d
+ADR_BOOT_ADDR	include/ssv6200_reg.h	384;"	d
+ADR_BOOT_INFO	include/ssv6200_reg.h	146;"	d
+ADR_BOOT_INFO	smac/hal/ssv6006c/ssv6006C_reg.h	286;"	d
+ADR_BRG_SW_RST	include/ssv6200_reg.h	114;"	d
+ADR_BRG_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	236;"	d
+ADR_BROWNOUT_INT	smac/hal/ssv6006c/ssv6006C_reg.h	553;"	d
+ADR_BROWNOUT_SETUP	smac/hal/ssv6006c/ssv6006C_reg.h	554;"	d
+ADR_BSSID1_0	smac/hal/ssv6006c/ssv6006C_reg.h	955;"	d
+ADR_BSSID1_1	smac/hal/ssv6006c/ssv6006C_reg.h	956;"	d
+ADR_BSSID_0	include/ssv6200_reg.h	780;"	d
+ADR_BSSID_0	smac/hal/ssv6006c/ssv6006C_reg.h	949;"	d
+ADR_BSSID_1	include/ssv6200_reg.h	781;"	d
+ADR_BSSID_1	smac/hal/ssv6006c/ssv6006C_reg.h	950;"	d
+ADR_BTCX0	include/ssv6200_reg.h	786;"	d
+ADR_BTCX0	smac/hal/ssv6006c/ssv6006C_reg.h	960;"	d
+ADR_BTCX1	include/ssv6200_reg.h	787;"	d
+ADR_BTCX1	smac/hal/ssv6006c/ssv6006C_reg.h	961;"	d
+ADR_BTCX_MISC_CTL	smac/hal/ssv6006c/ssv6006C_reg.h	964;"	d
+ADR_BT_DCOC_IDAC_REGISTER1	smac/hal/ssv6006c/ssv6006C_reg.h	1568;"	d
+ADR_BT_DCOC_IDAC_REGISTER10	smac/hal/ssv6006c/ssv6006C_reg.h	1577;"	d
+ADR_BT_DCOC_IDAC_REGISTER11	smac/hal/ssv6006c/ssv6006C_reg.h	1578;"	d
+ADR_BT_DCOC_IDAC_REGISTER12	smac/hal/ssv6006c/ssv6006C_reg.h	1579;"	d
+ADR_BT_DCOC_IDAC_REGISTER13	smac/hal/ssv6006c/ssv6006C_reg.h	1580;"	d
+ADR_BT_DCOC_IDAC_REGISTER14	smac/hal/ssv6006c/ssv6006C_reg.h	1581;"	d
+ADR_BT_DCOC_IDAC_REGISTER15	smac/hal/ssv6006c/ssv6006C_reg.h	1582;"	d
+ADR_BT_DCOC_IDAC_REGISTER16	smac/hal/ssv6006c/ssv6006C_reg.h	1583;"	d
+ADR_BT_DCOC_IDAC_REGISTER2	smac/hal/ssv6006c/ssv6006C_reg.h	1569;"	d
+ADR_BT_DCOC_IDAC_REGISTER3	smac/hal/ssv6006c/ssv6006C_reg.h	1570;"	d
+ADR_BT_DCOC_IDAC_REGISTER4	smac/hal/ssv6006c/ssv6006C_reg.h	1571;"	d
+ADR_BT_DCOC_IDAC_REGISTER5	smac/hal/ssv6006c/ssv6006C_reg.h	1572;"	d
+ADR_BT_DCOC_IDAC_REGISTER6	smac/hal/ssv6006c/ssv6006C_reg.h	1573;"	d
+ADR_BT_DCOC_IDAC_REGISTER7	smac/hal/ssv6006c/ssv6006C_reg.h	1574;"	d
+ADR_BT_DCOC_IDAC_REGISTER8	smac/hal/ssv6006c/ssv6006C_reg.h	1575;"	d
+ADR_BT_DCOC_IDAC_REGISTER9	smac/hal/ssv6006c/ssv6006C_reg.h	1576;"	d
+ADR_BT_RX_FE_HG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1525;"	d
+ADR_BT_RX_FE_LG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1527;"	d
+ADR_BT_RX_FE_MG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1526;"	d
+ADR_BT_RX_FE_ULG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1528;"	d
+ADR_BT_RX_FILTER_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1516;"	d
+ADR_BT_TX_DAC_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1531;"	d
+ADR_BUFFER_CLEAR_ERROR_FLAG_CLEAR	smac/hal/ssv6006c/ssv6006C_reg.h	478;"	d
+ADR_CALIBRATION_GAIN_REGISTER0	smac/hal/ssv6006c/ssv6006C_reg.h	1588;"	d
+ADR_CALIBRATION_GAIN_REGISTER1	smac/hal/ssv6006c/ssv6006C_reg.h	1589;"	d
+ADR_CALIBRATION_TIMER_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1587;"	d
+ADR_CARD_PKT_STATUS_TEST	include/ssv6200_reg.h	240;"	d
+ADR_CARD_RCA_REG	include/ssv6200_reg.h	242;"	d
+ADR_CARD_RCA_REG	smac/hal/ssv6006c/ssv6006C_reg.h	360;"	d
+ADR_CBR_ABB_REGISTER_1	include/ssv6200_reg.h	853;"	d
+ADR_CBR_ABB_REGISTER_2	include/ssv6200_reg.h	854;"	d
+ADR_CBR_DCOC_IDAC_REGISTER1	include/ssv6200_reg.h	875;"	d
+ADR_CBR_DCOC_IDAC_REGISTER2	include/ssv6200_reg.h	876;"	d
+ADR_CBR_DCOC_IDAC_REGISTER3	include/ssv6200_reg.h	877;"	d
+ADR_CBR_DCOC_IDAC_REGISTER4	include/ssv6200_reg.h	878;"	d
+ADR_CBR_DCOC_IDAC_REGISTER5	include/ssv6200_reg.h	879;"	d
+ADR_CBR_DCOC_IDAC_REGISTER6	include/ssv6200_reg.h	880;"	d
+ADR_CBR_DCOC_IDAC_REGISTER7	include/ssv6200_reg.h	881;"	d
+ADR_CBR_DCOC_IDAC_REGISTER8	include/ssv6200_reg.h	882;"	d
+ADR_CBR_DPLL_CP_PFD_REGISTER	include/ssv6200_reg.h	873;"	d
+ADR_CBR_DPLL_DIVIDER_REGISTER	include/ssv6200_reg.h	874;"	d
+ADR_CBR_DPLL_VCO_REGISTER	include/ssv6200_reg.h	872;"	d
+ADR_CBR_HARD_WIRE_PIN_REGISTER	include/ssv6200_reg.h	850;"	d
+ADR_CBR_LDO_REGISTER	include/ssv6200_reg.h	852;"	d
+ADR_CBR_MANUAL_ENABLE_REGISTER	include/ssv6200_reg.h	851;"	d
+ADR_CBR_MANUAL_REGISTER	include/ssv6200_reg.h	884;"	d
+ADR_CBR_PATTERN_GEN	include/ssv6200_reg.h	894;"	d
+ADR_CBR_RCAL_REGISTER	include/ssv6200_reg.h	883;"	d
+ADR_CBR_READ_ONLY_FLAGS_1	include/ssv6200_reg.h	887;"	d
+ADR_CBR_READ_ONLY_FLAGS_2	include/ssv6200_reg.h	888;"	d
+ADR_CBR_RG_INTEGRATION	include/ssv6200_reg.h	892;"	d
+ADR_CBR_RG_PKT_GEN_0	include/ssv6200_reg.h	889;"	d
+ADR_CBR_RG_PKT_GEN_1	include/ssv6200_reg.h	890;"	d
+ADR_CBR_RG_PKT_GEN_2	include/ssv6200_reg.h	891;"	d
+ADR_CBR_RG_PKT_GEN_TXCNT	include/ssv6200_reg.h	893;"	d
+ADR_CBR_RX_ADC_REGISTER	include/ssv6200_reg.h	862;"	d
+ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1	include/ssv6200_reg.h	857;"	d
+ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2	include/ssv6200_reg.h	858;"	d
+ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3	include/ssv6200_reg.h	859;"	d
+ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4	include/ssv6200_reg.h	860;"	d
+ADR_CBR_RX_FE_REGISTER_1	include/ssv6200_reg.h	856;"	d
+ADR_CBR_RX_FSM_REGISTER	include/ssv6200_reg.h	861;"	d
+ADR_CBR_SX_DUMMY_REGISTER	include/ssv6200_reg.h	886;"	d
+ADR_CBR_SX_ENABLE_RGISTER	include/ssv6200_reg.h	864;"	d
+ADR_CBR_SYN_DIV_SDM_XOSC	include/ssv6200_reg.h	869;"	d
+ADR_CBR_SYN_LCK1	include/ssv6200_reg.h	870;"	d
+ADR_CBR_SYN_LCK2	include/ssv6200_reg.h	871;"	d
+ADR_CBR_SYN_PFD_CHP	include/ssv6200_reg.h	867;"	d
+ADR_CBR_SYN_RGISTER_1	include/ssv6200_reg.h	865;"	d
+ADR_CBR_SYN_RGISTER_2	include/ssv6200_reg.h	866;"	d
+ADR_CBR_SYN_VCO_LOBF	include/ssv6200_reg.h	868;"	d
+ADR_CBR_TRX_DUMMY_REGISTER	include/ssv6200_reg.h	885;"	d
+ADR_CBR_TX_DAC_REGISTER	include/ssv6200_reg.h	863;"	d
+ADR_CBR_TX_FE_REGISTER	include/ssv6200_reg.h	855;"	d
+ADR_CCCR_00H_REG	include/ssv6200_reg.h	271;"	d
+ADR_CCCR_00H_REG	smac/hal/ssv6006c/ssv6006C_reg.h	370;"	d
+ADR_CCCR_04H_REG	include/ssv6200_reg.h	272;"	d
+ADR_CCCR_04H_REG	smac/hal/ssv6006c/ssv6006C_reg.h	371;"	d
+ADR_CCCR_08H_REG	include/ssv6200_reg.h	273;"	d
+ADR_CCCR_08H_REG	smac/hal/ssv6006c/ssv6006C_reg.h	372;"	d
+ADR_CCCR_13H_REG	include/ssv6200_reg.h	274;"	d
+ADR_CCCR_13H_REG	smac/hal/ssv6006c/ssv6006C_reg.h	374;"	d
+ADR_CCCR_14H_REG	smac/hal/ssv6006c/ssv6006C_reg.h	373;"	d
+ADR_CH0_PRI_TRIG	include/ssv6200_reg.h	900;"	d
+ADR_CH0_PRI_TRIG	smac/hal/ssv6006c/ssv6006C_reg.h	2073;"	d
+ADR_CH0_TRIG_0	include/ssv6200_reg.h	899;"	d
+ADR_CH0_TRIG_0	smac/hal/ssv6006c/ssv6006C_reg.h	2072;"	d
+ADR_CH0_TRIG_1	include/ssv6200_reg.h	898;"	d
+ADR_CH0_TRIG_1	smac/hal/ssv6006c/ssv6006C_reg.h	2071;"	d
+ADR_CH2_INT_ADDR_ALT	smac/hal/ssv6006c/ssv6006C_reg.h	2079;"	d
+ADR_CH2_TRIG_ALT	smac/hal/ssv6006c/ssv6006C_reg.h	2078;"	d
+ADR_CHANNEL	smac/hal/ssv6006c/ssv6006C_reg.h	727;"	d
+ADR_CHECK_SUM_IN_FILE	include/ssv6200_reg.h	392;"	d
+ADR_CHECK_SUM_RESULT	include/ssv6200_reg.h	391;"	d
+ADR_CHIP_DATE_00HHMMSS	smac/hal/ssv6006c/ssv6006C_reg.h	272;"	d
+ADR_CHIP_DATE_YYYYMMDD	smac/hal/ssv6006c/ssv6006C_reg.h	271;"	d
+ADR_CHIP_GITSHA_0	smac/hal/ssv6006c/ssv6006C_reg.h	273;"	d
+ADR_CHIP_GITSHA_1	smac/hal/ssv6006c/ssv6006C_reg.h	274;"	d
+ADR_CHIP_GITSHA_2	smac/hal/ssv6006c/ssv6006C_reg.h	275;"	d
+ADR_CHIP_GITSHA_3	smac/hal/ssv6006c/ssv6006C_reg.h	276;"	d
+ADR_CHIP_GITSHA_4	smac/hal/ssv6006c/ssv6006C_reg.h	277;"	d
+ADR_CHIP_ID_0	hwif/hwif.h	21;"	d
+ADR_CHIP_ID_0	include/ssv6200_reg.h	116;"	d
+ADR_CHIP_ID_0	smac/hal/ssv6006c/ssv6006C_reg.h	238;"	d
+ADR_CHIP_ID_1	hwif/hwif.h	22;"	d
+ADR_CHIP_ID_1	include/ssv6200_reg.h	117;"	d
+ADR_CHIP_ID_1	smac/hal/ssv6006c/ssv6006C_reg.h	239;"	d
+ADR_CHIP_ID_2	hwif/hwif.h	23;"	d
+ADR_CHIP_ID_2	include/ssv6200_reg.h	118;"	d
+ADR_CHIP_ID_2	smac/hal/ssv6006c/ssv6006C_reg.h	240;"	d
+ADR_CHIP_ID_3	hwif/hwif.h	24;"	d
+ADR_CHIP_ID_3	include/ssv6200_reg.h	119;"	d
+ADR_CHIP_ID_3	smac/hal/ssv6006c/ssv6006C_reg.h	241;"	d
+ADR_CHIP_INFO_FPGATAG	smac/hal/ssv6006c/ssv6006C_reg.h	281;"	d
+ADR_CHIP_INFO_ID_0	smac/hal/ssv6006c/ssv6006C_reg.h	268;"	d
+ADR_CHIP_INFO_ID_1	smac/hal/ssv6006c/ssv6006C_reg.h	269;"	d
+ADR_CHIP_TYPE_VER	smac/hal/ssv6006c/ssv6006C_reg.h	270;"	d
+ADR_CH_ARB_PRI	include/ssv6200_reg.h	946;"	d
+ADR_CH_ARB_PRI	smac/hal/ssv6006c/ssv6006C_reg.h	2124;"	d
+ADR_CH_STA_PRI	include/ssv6200_reg.h	931;"	d
+ADR_CH_STA_PRI	smac/hal/ssv6006c/ssv6006C_reg.h	2109;"	d
+ADR_CLOCK_SELECTION	include/ssv6200_reg.h	120;"	d
+ADR_CLOCK_SELECTION	smac/hal/ssv6006c/ssv6006C_reg.h	242;"	d
+ADR_CLR_INT_STS0	smac/hal/ssv6006c/ssv6006C_reg.h	524;"	d
+ADR_CLR_INT_STS1	smac/hal/ssv6006c/ssv6006C_reg.h	523;"	d
+ADR_CLR_INT_STS2	smac/hal/ssv6006c/ssv6006C_reg.h	522;"	d
+ADR_CMD52_DATA_FOR_LAST_TIME	include/ssv6200_reg.h	255;"	d
+ADR_CMD_SET	smac/hal/ssv6006c/ssv6006C_reg.h	472;"	d
+ADR_CMD_SET_1	smac/hal/ssv6006c/ssv6006C_reg.h	473;"	d
+ADR_COMMAND_ADDR	include/ssv6200_reg.h	394;"	d
+ADR_COMMAND_LEN	include/ssv6200_reg.h	393;"	d
+ADR_CONDITION_NUMBER	include/ssv6200_reg.h	311;"	d
+ADR_CONTROL	include/ssv6200_reg.h	415;"	d
+ADR_CONTROL	smac/hal/ssv6006c/ssv6006C_reg.h	555;"	d
+ADR_CORRECT_RATE_REPORT_LENGTH	smac/hal/ssv6006c/ssv6006C_reg.h	601;"	d
+ADR_CO_NAV	include/ssv6200_reg.h	466;"	d
+ADR_CO_NAV	smac/hal/ssv6006c/ssv6006C_reg.h	625;"	d
+ADR_CPU_ID_TB0	include/ssv6200_reg.h	896;"	d
+ADR_CPU_ID_TB0	smac/hal/ssv6006c/ssv6006C_reg.h	2069;"	d
+ADR_CPU_ID_TB1	include/ssv6200_reg.h	897;"	d
+ADR_CPU_ID_TB1	smac/hal/ssv6006c/ssv6006C_reg.h	2070;"	d
+ADR_CPU_ID_TB2	include/ssv6200_reg.h	923;"	d
+ADR_CPU_ID_TB2	smac/hal/ssv6006c/ssv6006C_reg.h	2101;"	d
+ADR_CPU_ID_TB3	include/ssv6200_reg.h	924;"	d
+ADR_CPU_ID_TB3	smac/hal/ssv6006c/ssv6006C_reg.h	2102;"	d
+ADR_CPU_POR0_7	include/ssv6200_reg.h	1226;"	d
+ADR_CPU_POR8_F	include/ssv6200_reg.h	1227;"	d
+ADR_CSR_SOFTWARE_RESET	include/ssv6200_reg.h	773;"	d
+ADR_CSR_SOFTWARE_RESET	smac/hal/ssv6006c/ssv6006C_reg.h	942;"	d
+ADR_CS_ADD_LEN	include/ssv6200_reg.h	450;"	d
+ADR_CS_ADD_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	609;"	d
+ADR_CS_CHECK_SUM	include/ssv6200_reg.h	454;"	d
+ADR_CS_CHECK_SUM	smac/hal/ssv6006c/ssv6006C_reg.h	613;"	d
+ADR_CS_CMD	include/ssv6200_reg.h	451;"	d
+ADR_CS_CMD	smac/hal/ssv6006c/ssv6006C_reg.h	610;"	d
+ADR_CS_INI_BUF	include/ssv6200_reg.h	452;"	d
+ADR_CS_INI_BUF	smac/hal/ssv6006c/ssv6006C_reg.h	611;"	d
+ADR_CS_PSEUDO_BUF	include/ssv6200_reg.h	453;"	d
+ADR_CS_PSEUDO_BUF	smac/hal/ssv6006c/ssv6006C_reg.h	612;"	d
+ADR_CS_START_ADDR	include/ssv6200_reg.h	449;"	d
+ADR_CS_START_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	608;"	d
+ADR_D2_DMA_ADR_DST	include/ssv6200_reg.h	411;"	d
+ADR_D2_DMA_ADR_DST	smac/hal/ssv6006c/ssv6006C_reg.h	485;"	d
+ADR_D2_DMA_ADR_SRC	include/ssv6200_reg.h	410;"	d
+ADR_D2_DMA_ADR_SRC	smac/hal/ssv6006c/ssv6006C_reg.h	484;"	d
+ADR_D2_DMA_CTRL	include/ssv6200_reg.h	412;"	d
+ADR_D2_DMA_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	486;"	d
+ADR_D2_DMA_FILL_CONST	include/ssv6200_reg.h	414;"	d
+ADR_D2_DMA_FILL_CONST	smac/hal/ssv6006c/ssv6006C_reg.h	488;"	d
+ADR_D2_DMA_INT	include/ssv6200_reg.h	413;"	d
+ADR_D2_DMA_INT	smac/hal/ssv6006c/ssv6006C_reg.h	487;"	d
+ADR_DAT_UART_DATA	include/ssv6200_reg.h	341;"	d
+ADR_DAT_UART_FCR	include/ssv6200_reg.h	343;"	d
+ADR_DAT_UART_IER	include/ssv6200_reg.h	342;"	d
+ADR_DAT_UART_ISR	include/ssv6200_reg.h	350;"	d
+ADR_DAT_UART_LCR	include/ssv6200_reg.h	344;"	d
+ADR_DAT_UART_LSR	include/ssv6200_reg.h	346;"	d
+ADR_DAT_UART_MCR	include/ssv6200_reg.h	345;"	d
+ADR_DAT_UART_MSR	include/ssv6200_reg.h	347;"	d
+ADR_DAT_UART_RTHR	include/ssv6200_reg.h	349;"	d
+ADR_DAT_UART_SPR	include/ssv6200_reg.h	348;"	d
+ADR_DBG_AMPDU_FAIL	include/ssv6200_reg.h	847;"	d
+ADR_DBG_AMPDU_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	1023;"	d
+ADR_DBG_AMPDU_PASS	include/ssv6200_reg.h	846;"	d
+ADR_DBG_AMPDU_PASS	smac/hal/ssv6006c/ssv6006C_reg.h	1022;"	d
+ADR_DBG_CNT	include/ssv6200_reg.h	320;"	d
+ADR_DBG_CNT2	include/ssv6200_reg.h	321;"	d
+ADR_DBG_CNT3	include/ssv6200_reg.h	322;"	d
+ADR_DBG_CNT4	include/ssv6200_reg.h	323;"	d
+ADR_DBG_CONDITION_NUMBER	include/ssv6200_reg.h	370;"	d
+ADR_DBG_DBG_CNT	include/ssv6200_reg.h	379;"	d
+ADR_DBG_DBG_CNT2	include/ssv6200_reg.h	380;"	d
+ADR_DBG_DBG_CNT3	include/ssv6200_reg.h	381;"	d
+ADR_DBG_DBG_CNT4	include/ssv6200_reg.h	382;"	d
+ADR_DBG_DEBUG_BURST_MODE	include/ssv6200_reg.h	373;"	d
+ADR_DBG_FF_FULL	include/ssv6200_reg.h	583;"	d
+ADR_DBG_FF_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	704;"	d
+ADR_DBG_HOST_PATH	include/ssv6200_reg.h	371;"	d
+ADR_DBG_INT_TAG	include/ssv6200_reg.h	383;"	d
+ADR_DBG_LEN_ALC_FAIL	include/ssv6200_reg.h	845;"	d
+ADR_DBG_LEN_ALC_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	1021;"	d
+ADR_DBG_LEN_CRC_FAIL	include/ssv6200_reg.h	844;"	d
+ADR_DBG_LEN_CRC_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	1020;"	d
+ADR_DBG_MB_FULL	include/ssv6200_reg.h	585;"	d
+ADR_DBG_MB_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	706;"	d
+ADR_DBG_Q0_ACK_FAIL	include/ssv6200_reg.h	826;"	d
+ADR_DBG_Q0_ACK_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	1002;"	d
+ADR_DBG_Q0_ACK_SUCCESS	include/ssv6200_reg.h	825;"	d
+ADR_DBG_Q0_ACK_SUCCESS	smac/hal/ssv6006c/ssv6006C_reg.h	1001;"	d
+ADR_DBG_Q0_FRM_FAIL	include/ssv6200_reg.h	824;"	d
+ADR_DBG_Q0_FRM_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	1000;"	d
+ADR_DBG_Q0_FRM_SUCCESS	include/ssv6200_reg.h	823;"	d
+ADR_DBG_Q0_FRM_SUCCESS	smac/hal/ssv6006c/ssv6006C_reg.h	999;"	d
+ADR_DBG_Q1_ACK_FAIL	include/ssv6200_reg.h	830;"	d
+ADR_DBG_Q1_ACK_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	1006;"	d
+ADR_DBG_Q1_ACK_SUCCESS	include/ssv6200_reg.h	829;"	d
+ADR_DBG_Q1_ACK_SUCCESS	smac/hal/ssv6006c/ssv6006C_reg.h	1005;"	d
+ADR_DBG_Q1_FRM_FAIL	include/ssv6200_reg.h	828;"	d
+ADR_DBG_Q1_FRM_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	1004;"	d
+ADR_DBG_Q1_FRM_SUCCESS	include/ssv6200_reg.h	827;"	d
+ADR_DBG_Q1_FRM_SUCCESS	smac/hal/ssv6006c/ssv6006C_reg.h	1003;"	d
+ADR_DBG_Q2_ACK_FAIL	include/ssv6200_reg.h	834;"	d
+ADR_DBG_Q2_ACK_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	1010;"	d
+ADR_DBG_Q2_ACK_SUCCESS	include/ssv6200_reg.h	833;"	d
+ADR_DBG_Q2_ACK_SUCCESS	smac/hal/ssv6006c/ssv6006C_reg.h	1009;"	d
+ADR_DBG_Q2_FRM_FAIL	include/ssv6200_reg.h	832;"	d
+ADR_DBG_Q2_FRM_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	1008;"	d
+ADR_DBG_Q2_FRM_SUCCESS	include/ssv6200_reg.h	831;"	d
+ADR_DBG_Q2_FRM_SUCCESS	smac/hal/ssv6006c/ssv6006C_reg.h	1007;"	d
+ADR_DBG_Q3_ACK_FAIL	include/ssv6200_reg.h	838;"	d
+ADR_DBG_Q3_ACK_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	1014;"	d
+ADR_DBG_Q3_ACK_SUCCESS	include/ssv6200_reg.h	837;"	d
+ADR_DBG_Q3_ACK_SUCCESS	smac/hal/ssv6006c/ssv6006C_reg.h	1013;"	d
+ADR_DBG_Q3_FRM_FAIL	include/ssv6200_reg.h	836;"	d
+ADR_DBG_Q3_FRM_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	1012;"	d
+ADR_DBG_Q3_FRM_SUCCESS	include/ssv6200_reg.h	835;"	d
+ADR_DBG_Q3_FRM_SUCCESS	smac/hal/ssv6006c/ssv6006C_reg.h	1011;"	d
+ADR_DBG_RX_QUOTA	include/ssv6200_reg.h	369;"	d
+ADR_DBG_SPI_MODE	include/ssv6200_reg.h	368;"	d
+ADR_DBG_SPI_STS	include/ssv6200_reg.h	376;"	d
+ADR_DBG_SPI_TO_PHY_PARAM1	include/ssv6200_reg.h	374;"	d
+ADR_DBG_SPI_TO_PHY_PARAM2	include/ssv6200_reg.h	375;"	d
+ADR_DBG_TX_ALLOC	include/ssv6200_reg.h	378;"	d
+ADR_DBG_TX_ALLOC_SET	include/ssv6200_reg.h	377;"	d
+ADR_DBG_TX_SEG	include/ssv6200_reg.h	372;"	d
+ADR_DBG_WFF_FULL	include/ssv6200_reg.h	584;"	d
+ADR_DBG_WFF_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	705;"	d
+ADR_DCOC_IDAC_REGISTER1	include/ssv6200_reg.h	1205;"	d
+ADR_DCOC_IDAC_REGISTER2	include/ssv6200_reg.h	1206;"	d
+ADR_DCOC_IDAC_REGISTER3	include/ssv6200_reg.h	1207;"	d
+ADR_DCOC_IDAC_REGISTER4	include/ssv6200_reg.h	1208;"	d
+ADR_DCOC_IDAC_REGISTER5	include/ssv6200_reg.h	1209;"	d
+ADR_DCOC_IDAC_REGISTER6	include/ssv6200_reg.h	1210;"	d
+ADR_DCOC_IDAC_REGISTER7	include/ssv6200_reg.h	1211;"	d
+ADR_DCOC_IDAC_REGISTER8	include/ssv6200_reg.h	1212;"	d
+ADR_DEBUG_BURST_MODE	include/ssv6200_reg.h	314;"	d
+ADR_DEBUG_CTL	include/ssv6200_reg.h	1231;"	d
+ADR_DEBUG_FIRMWARE_EVENT_FLAG	smac/hal/ssv6006c/ssv6006C_reg.h	266;"	d
+ADR_DEBUG_HOST_EVENT_FLAG	smac/hal/ssv6006c/ssv6006C_reg.h	267;"	d
+ADR_DEBUG_OUT	include/ssv6200_reg.h	1232;"	d
+ADR_DEBUG_SIM_FINISH	smac/hal/ssv6006c/ssv6006C_reg.h	283;"	d
+ADR_DESIGN_FOR_TEST	smac/hal/ssv6006c/ssv6006C_reg.h	298;"	d
+ADR_DESIGN_FOR_TEST_ASSERTION	smac/hal/ssv6006c/ssv6006C_reg.h	291;"	d
+ADR_DIGITAL_ADD_ON_0	smac/hal/ssv6006c/ssv6006C_reg.h	1652;"	d
+ADR_DIGITAL_ADD_ON_1	smac/hal/ssv6006c/ssv6006C_reg.h	1653;"	d
+ADR_DIGITAL_ADD_ON_2	smac/hal/ssv6006c/ssv6006C_reg.h	1654;"	d
+ADR_DIGITAL_ADD_ON_3	smac/hal/ssv6006c/ssv6006C_reg.h	1655;"	d
+ADR_DIGITAL_ADD_ON_4	smac/hal/ssv6006c/ssv6006C_reg.h	1656;"	d
+ADR_DIGITAL_ADD_ON_5	smac/hal/ssv6006c/ssv6006C_reg.h	1657;"	d
+ADR_DIGITAL_ADD_ON_6	smac/hal/ssv6006c/ssv6006C_reg.h	1658;"	d
+ADR_DMA_ADR_DST	include/ssv6200_reg.h	396;"	d
+ADR_DMA_ADR_DST	smac/hal/ssv6006c/ssv6006C_reg.h	480;"	d
+ADR_DMA_ADR_SRC	include/ssv6200_reg.h	395;"	d
+ADR_DMA_ADR_SRC	smac/hal/ssv6006c/ssv6006C_reg.h	479;"	d
+ADR_DMA_CLR	include/ssv6200_reg.h	464;"	d
+ADR_DMA_CLR	smac/hal/ssv6006c/ssv6006C_reg.h	623;"	d
+ADR_DMA_CTRL	include/ssv6200_reg.h	397;"	d
+ADR_DMA_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	481;"	d
+ADR_DMA_FILL_CONST	include/ssv6200_reg.h	399;"	d
+ADR_DMA_FILL_CONST	smac/hal/ssv6006c/ssv6006C_reg.h	483;"	d
+ADR_DMA_INT	include/ssv6200_reg.h	398;"	d
+ADR_DMA_INT	smac/hal/ssv6006c/ssv6006C_reg.h	482;"	d
+ADR_DMA_LEN	include/ssv6200_reg.h	463;"	d
+ADR_DMA_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	622;"	d
+ADR_DMA_RDATA	include/ssv6200_reg.h	461;"	d
+ADR_DMA_RDATA	smac/hal/ssv6006c/ssv6006C_reg.h	620;"	d
+ADR_DMA_WDATA	include/ssv6200_reg.h	462;"	d
+ADR_DMA_WDATA	smac/hal/ssv6006c/ssv6006C_reg.h	621;"	d
+ADR_DMN_IDTBL_0_STATUS	include/ssv6200_reg.h	1245;"	d
+ADR_DMN_IDTBL_1_STATUS	include/ssv6200_reg.h	1246;"	d
+ADR_DMN_IDTBL_2_STATUS	include/ssv6200_reg.h	1247;"	d
+ADR_DMN_IDTBL_3_STATUS	include/ssv6200_reg.h	1248;"	d
+ADR_DMN_MCU_STATUS	include/ssv6200_reg.h	1236;"	d
+ADR_DMN_READ_BYPASS	include/ssv6200_reg.h	1229;"	d
+ADR_DMN_STATUS	include/ssv6200_reg.h	1234;"	d
+ADR_DMN_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	2143;"	d
+ADR_DPD_CONTROL	include/ssv6200_reg.h	1149;"	d
+ADR_DPD_GAIN_ESTIMATION_0	include/ssv6200_reg.h	1176;"	d
+ADR_DPD_GAIN_ESTIMATION_1	include/ssv6200_reg.h	1177;"	d
+ADR_DPD_GAIN_ESTIMATION_2	include/ssv6200_reg.h	1178;"	d
+ADR_DPD_GAIN_TABLE_0	include/ssv6200_reg.h	1150;"	d
+ADR_DPD_GAIN_TABLE_1	include/ssv6200_reg.h	1151;"	d
+ADR_DPD_GAIN_TABLE_2	include/ssv6200_reg.h	1152;"	d
+ADR_DPD_GAIN_TABLE_3	include/ssv6200_reg.h	1153;"	d
+ADR_DPD_GAIN_TABLE_4	include/ssv6200_reg.h	1154;"	d
+ADR_DPD_GAIN_TABLE_5	include/ssv6200_reg.h	1155;"	d
+ADR_DPD_GAIN_TABLE_6	include/ssv6200_reg.h	1156;"	d
+ADR_DPD_GAIN_TABLE_7	include/ssv6200_reg.h	1157;"	d
+ADR_DPD_GAIN_TABLE_8	include/ssv6200_reg.h	1158;"	d
+ADR_DPD_GAIN_TABLE_9	include/ssv6200_reg.h	1159;"	d
+ADR_DPD_GAIN_TABLE_A	include/ssv6200_reg.h	1160;"	d
+ADR_DPD_GAIN_TABLE_B	include/ssv6200_reg.h	1161;"	d
+ADR_DPD_GAIN_TABLE_C	include/ssv6200_reg.h	1162;"	d
+ADR_DPD_PH_TABLE_0	include/ssv6200_reg.h	1163;"	d
+ADR_DPD_PH_TABLE_1	include/ssv6200_reg.h	1164;"	d
+ADR_DPD_PH_TABLE_2	include/ssv6200_reg.h	1165;"	d
+ADR_DPD_PH_TABLE_3	include/ssv6200_reg.h	1166;"	d
+ADR_DPD_PH_TABLE_4	include/ssv6200_reg.h	1167;"	d
+ADR_DPD_PH_TABLE_5	include/ssv6200_reg.h	1168;"	d
+ADR_DPD_PH_TABLE_6	include/ssv6200_reg.h	1169;"	d
+ADR_DPD_PH_TABLE_7	include/ssv6200_reg.h	1170;"	d
+ADR_DPD_PH_TABLE_8	include/ssv6200_reg.h	1171;"	d
+ADR_DPD_PH_TABLE_9	include/ssv6200_reg.h	1172;"	d
+ADR_DPD_PH_TABLE_A	include/ssv6200_reg.h	1173;"	d
+ADR_DPD_PH_TABLE_B	include/ssv6200_reg.h	1174;"	d
+ADR_DPD_PH_TABLE_C	include/ssv6200_reg.h	1175;"	d
+ADR_DPLL_CKT_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1545;"	d
+ADR_DPLL_CP_PFD_REGISTER	include/ssv6200_reg.h	1203;"	d
+ADR_DPLL_DIVIDER_REGISTER	include/ssv6200_reg.h	1204;"	d
+ADR_DPLL_FB_DIVIDER_REGISTERS_I	include/ssv6200_reg.h	1219;"	d
+ADR_DPLL_FB_DIVIDER_REGISTERS_II	include/ssv6200_reg.h	1220;"	d
+ADR_DPLL_FB_DIVISION__REGISTERS	smac/hal/ssv6006c/ssv6006C_reg.h	1546;"	d
+ADR_DPLL_TOP_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1544;"	d
+ADR_DPLL_VCO_REGISTER	include/ssv6200_reg.h	1202;"	d
+ADR_DUAL_IDX_EXTEND	smac/hal/ssv6006c/ssv6006C_reg.h	729;"	d
+ADR_EFUSE_AHB_RDATA_0	include/ssv6200_reg.h	472;"	d
+ADR_EFUSE_AHB_RDATA_1	include/ssv6200_reg.h	474;"	d
+ADR_EFUSE_AHB_RDATA_2	include/ssv6200_reg.h	476;"	d
+ADR_EFUSE_AHB_RDATA_3	include/ssv6200_reg.h	478;"	d
+ADR_EFUSE_AHB_RDATA_4	include/ssv6200_reg.h	480;"	d
+ADR_EFUSE_AHB_RDATA_5	include/ssv6200_reg.h	482;"	d
+ADR_EFUSE_AHB_RDATA_6	include/ssv6200_reg.h	484;"	d
+ADR_EFUSE_AHB_RDATA_7	include/ssv6200_reg.h	486;"	d
+ADR_EFUSE_CLK_FREQ	include/ssv6200_reg.h	470;"	d
+ADR_EFUSE_CLK_FREQ	smac/hal/ssv6006c/ssv6006C_reg.h	629;"	d
+ADR_EFUSE_LDO_TIME	include/ssv6200_reg.h	471;"	d
+ADR_EFUSE_LDO_TIME	smac/hal/ssv6006c/ssv6006C_reg.h	630;"	d
+ADR_EFUSE_RD_KICK	smac/hal/ssv6006c/ssv6006C_reg.h	634;"	d
+ADR_EFUSE_SPI_BUSY	include/ssv6200_reg.h	496;"	d
+ADR_EFUSE_SPI_RD0_EN	include/ssv6200_reg.h	488;"	d
+ADR_EFUSE_SPI_RD1_EN	include/ssv6200_reg.h	489;"	d
+ADR_EFUSE_SPI_RD2_EN	include/ssv6200_reg.h	490;"	d
+ADR_EFUSE_SPI_RD3_EN	include/ssv6200_reg.h	491;"	d
+ADR_EFUSE_SPI_RD4_EN	include/ssv6200_reg.h	492;"	d
+ADR_EFUSE_SPI_RD5_EN	include/ssv6200_reg.h	493;"	d
+ADR_EFUSE_SPI_RD6_EN	include/ssv6200_reg.h	494;"	d
+ADR_EFUSE_SPI_RD7_EN	include/ssv6200_reg.h	495;"	d
+ADR_EFUSE_SPI_RDATA_0	include/ssv6200_reg.h	497;"	d
+ADR_EFUSE_SPI_RDATA_1	include/ssv6200_reg.h	498;"	d
+ADR_EFUSE_SPI_RDATA_2	include/ssv6200_reg.h	499;"	d
+ADR_EFUSE_SPI_RDATA_3	include/ssv6200_reg.h	500;"	d
+ADR_EFUSE_SPI_RDATA_4	include/ssv6200_reg.h	501;"	d
+ADR_EFUSE_SPI_RDATA_5	include/ssv6200_reg.h	502;"	d
+ADR_EFUSE_SPI_RDATA_6	include/ssv6200_reg.h	503;"	d
+ADR_EFUSE_SPI_RDATA_7	include/ssv6200_reg.h	504;"	d
+ADR_EFUSE_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	631;"	d
+ADR_EFUSE_STATUS2	smac/hal/ssv6006c/ssv6006C_reg.h	632;"	d
+ADR_EFUSE_VDDQ_EN	smac/hal/ssv6006c/ssv6006C_reg.h	635;"	d
+ADR_EFUSE_WDATA_0	include/ssv6200_reg.h	473;"	d
+ADR_EFUSE_WDATA_0_0	smac/hal/ssv6006c/ssv6006C_reg.h	636;"	d
+ADR_EFUSE_WDATA_0_1	smac/hal/ssv6006c/ssv6006C_reg.h	637;"	d
+ADR_EFUSE_WDATA_0_2	smac/hal/ssv6006c/ssv6006C_reg.h	638;"	d
+ADR_EFUSE_WDATA_0_3	smac/hal/ssv6006c/ssv6006C_reg.h	639;"	d
+ADR_EFUSE_WDATA_0_4	smac/hal/ssv6006c/ssv6006C_reg.h	640;"	d
+ADR_EFUSE_WDATA_0_5	smac/hal/ssv6006c/ssv6006C_reg.h	641;"	d
+ADR_EFUSE_WDATA_0_6	smac/hal/ssv6006c/ssv6006C_reg.h	642;"	d
+ADR_EFUSE_WDATA_0_7	smac/hal/ssv6006c/ssv6006C_reg.h	643;"	d
+ADR_EFUSE_WDATA_1	include/ssv6200_reg.h	475;"	d
+ADR_EFUSE_WDATA_2	include/ssv6200_reg.h	477;"	d
+ADR_EFUSE_WDATA_3	include/ssv6200_reg.h	479;"	d
+ADR_EFUSE_WDATA_4	include/ssv6200_reg.h	481;"	d
+ADR_EFUSE_WDATA_5	include/ssv6200_reg.h	483;"	d
+ADR_EFUSE_WDATA_6	include/ssv6200_reg.h	485;"	d
+ADR_EFUSE_WDATA_7	include/ssv6200_reg.h	487;"	d
+ADR_EFUSE_WR_KICK	smac/hal/ssv6006c/ssv6006C_reg.h	633;"	d
+ADR_ENG_SOFTWARE_RESET	include/ssv6200_reg.h	772;"	d
+ADR_ENG_SOFTWARE_RESET	smac/hal/ssv6006c/ssv6006C_reg.h	941;"	d
+ADR_F0_CIS_CONTENT_REG_0	include/ssv6200_reg.h	277;"	d
+ADR_F0_CIS_CONTENT_REG_0	smac/hal/ssv6006c/ssv6006C_reg.h	377;"	d
+ADR_F0_CIS_CONTENT_REG_1	include/ssv6200_reg.h	278;"	d
+ADR_F0_CIS_CONTENT_REG_1	smac/hal/ssv6006c/ssv6006C_reg.h	378;"	d
+ADR_F0_CIS_CONTENT_REG_10	include/ssv6200_reg.h	287;"	d
+ADR_F0_CIS_CONTENT_REG_10	smac/hal/ssv6006c/ssv6006C_reg.h	387;"	d
+ADR_F0_CIS_CONTENT_REG_11	include/ssv6200_reg.h	288;"	d
+ADR_F0_CIS_CONTENT_REG_11	smac/hal/ssv6006c/ssv6006C_reg.h	388;"	d
+ADR_F0_CIS_CONTENT_REG_12	include/ssv6200_reg.h	289;"	d
+ADR_F0_CIS_CONTENT_REG_12	smac/hal/ssv6006c/ssv6006C_reg.h	389;"	d
+ADR_F0_CIS_CONTENT_REG_13	include/ssv6200_reg.h	290;"	d
+ADR_F0_CIS_CONTENT_REG_13	smac/hal/ssv6006c/ssv6006C_reg.h	390;"	d
+ADR_F0_CIS_CONTENT_REG_14	include/ssv6200_reg.h	291;"	d
+ADR_F0_CIS_CONTENT_REG_14	smac/hal/ssv6006c/ssv6006C_reg.h	391;"	d
+ADR_F0_CIS_CONTENT_REG_15	include/ssv6200_reg.h	292;"	d
+ADR_F0_CIS_CONTENT_REG_15	smac/hal/ssv6006c/ssv6006C_reg.h	392;"	d
+ADR_F0_CIS_CONTENT_REG_2	include/ssv6200_reg.h	279;"	d
+ADR_F0_CIS_CONTENT_REG_2	smac/hal/ssv6006c/ssv6006C_reg.h	379;"	d
+ADR_F0_CIS_CONTENT_REG_3	include/ssv6200_reg.h	280;"	d
+ADR_F0_CIS_CONTENT_REG_3	smac/hal/ssv6006c/ssv6006C_reg.h	380;"	d
+ADR_F0_CIS_CONTENT_REG_4	include/ssv6200_reg.h	281;"	d
+ADR_F0_CIS_CONTENT_REG_4	smac/hal/ssv6006c/ssv6006C_reg.h	381;"	d
+ADR_F0_CIS_CONTENT_REG_5	include/ssv6200_reg.h	282;"	d
+ADR_F0_CIS_CONTENT_REG_5	smac/hal/ssv6006c/ssv6006C_reg.h	382;"	d
+ADR_F0_CIS_CONTENT_REG_6	include/ssv6200_reg.h	283;"	d
+ADR_F0_CIS_CONTENT_REG_6	smac/hal/ssv6006c/ssv6006C_reg.h	383;"	d
+ADR_F0_CIS_CONTENT_REG_7	include/ssv6200_reg.h	284;"	d
+ADR_F0_CIS_CONTENT_REG_7	smac/hal/ssv6006c/ssv6006C_reg.h	384;"	d
+ADR_F0_CIS_CONTENT_REG_8	include/ssv6200_reg.h	285;"	d
+ADR_F0_CIS_CONTENT_REG_8	smac/hal/ssv6006c/ssv6006C_reg.h	385;"	d
+ADR_F0_CIS_CONTENT_REG_9	include/ssv6200_reg.h	286;"	d
+ADR_F0_CIS_CONTENT_REG_9	smac/hal/ssv6006c/ssv6006C_reg.h	386;"	d
+ADR_F1_BLOCK_SIZE_0_REG	include/ssv6200_reg.h	267;"	d
+ADR_F1_CIS_CONTENT_REG_0	include/ssv6200_reg.h	293;"	d
+ADR_F1_CIS_CONTENT_REG_0	smac/hal/ssv6006c/ssv6006C_reg.h	393;"	d
+ADR_F1_CIS_CONTENT_REG_1	include/ssv6200_reg.h	294;"	d
+ADR_F1_CIS_CONTENT_REG_1	smac/hal/ssv6006c/ssv6006C_reg.h	394;"	d
+ADR_F1_CIS_CONTENT_REG_10	include/ssv6200_reg.h	303;"	d
+ADR_F1_CIS_CONTENT_REG_10	smac/hal/ssv6006c/ssv6006C_reg.h	403;"	d
+ADR_F1_CIS_CONTENT_REG_11	include/ssv6200_reg.h	304;"	d
+ADR_F1_CIS_CONTENT_REG_11	smac/hal/ssv6006c/ssv6006C_reg.h	404;"	d
+ADR_F1_CIS_CONTENT_REG_12	include/ssv6200_reg.h	305;"	d
+ADR_F1_CIS_CONTENT_REG_12	smac/hal/ssv6006c/ssv6006C_reg.h	405;"	d
+ADR_F1_CIS_CONTENT_REG_13	include/ssv6200_reg.h	306;"	d
+ADR_F1_CIS_CONTENT_REG_13	smac/hal/ssv6006c/ssv6006C_reg.h	406;"	d
+ADR_F1_CIS_CONTENT_REG_14	include/ssv6200_reg.h	307;"	d
+ADR_F1_CIS_CONTENT_REG_14	smac/hal/ssv6006c/ssv6006C_reg.h	407;"	d
+ADR_F1_CIS_CONTENT_REG_15	include/ssv6200_reg.h	308;"	d
+ADR_F1_CIS_CONTENT_REG_15	smac/hal/ssv6006c/ssv6006C_reg.h	408;"	d
+ADR_F1_CIS_CONTENT_REG_2	include/ssv6200_reg.h	295;"	d
+ADR_F1_CIS_CONTENT_REG_2	smac/hal/ssv6006c/ssv6006C_reg.h	395;"	d
+ADR_F1_CIS_CONTENT_REG_3	include/ssv6200_reg.h	296;"	d
+ADR_F1_CIS_CONTENT_REG_3	smac/hal/ssv6006c/ssv6006C_reg.h	396;"	d
+ADR_F1_CIS_CONTENT_REG_4	include/ssv6200_reg.h	297;"	d
+ADR_F1_CIS_CONTENT_REG_4	smac/hal/ssv6006c/ssv6006C_reg.h	397;"	d
+ADR_F1_CIS_CONTENT_REG_5	include/ssv6200_reg.h	298;"	d
+ADR_F1_CIS_CONTENT_REG_5	smac/hal/ssv6006c/ssv6006C_reg.h	398;"	d
+ADR_F1_CIS_CONTENT_REG_6	include/ssv6200_reg.h	299;"	d
+ADR_F1_CIS_CONTENT_REG_6	smac/hal/ssv6006c/ssv6006C_reg.h	399;"	d
+ADR_F1_CIS_CONTENT_REG_7	include/ssv6200_reg.h	300;"	d
+ADR_F1_CIS_CONTENT_REG_7	smac/hal/ssv6006c/ssv6006C_reg.h	400;"	d
+ADR_F1_CIS_CONTENT_REG_8	include/ssv6200_reg.h	301;"	d
+ADR_F1_CIS_CONTENT_REG_8	smac/hal/ssv6006c/ssv6006C_reg.h	401;"	d
+ADR_F1_CIS_CONTENT_REG_9	include/ssv6200_reg.h	302;"	d
+ADR_F1_CIS_CONTENT_REG_9	smac/hal/ssv6006c/ssv6006C_reg.h	402;"	d
+ADR_FBR_100H_REG	include/ssv6200_reg.h	275;"	d
+ADR_FBR_100H_REG	smac/hal/ssv6006c/ssv6006C_reg.h	375;"	d
+ADR_FBR_109H_REG	include/ssv6200_reg.h	276;"	d
+ADR_FBR_109H_REG	smac/hal/ssv6006c/ssv6006C_reg.h	376;"	d
+ADR_FBUS_CFG0_1	smac/hal/ssv6006c/ssv6006C_reg.h	142;"	d
+ADR_FBUS_CFG0_2	smac/hal/ssv6006c/ssv6006C_reg.h	143;"	d
+ADR_FBUS_CFG1_1	smac/hal/ssv6006c/ssv6006C_reg.h	148;"	d
+ADR_FBUS_CFG1_2	smac/hal/ssv6006c/ssv6006C_reg.h	149;"	d
+ADR_FBUS_CH_EN	smac/hal/ssv6006c/ssv6006C_reg.h	163;"	d
+ADR_FBUS_CLK_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	255;"	d
+ADR_FBUS_CLRERR	smac/hal/ssv6006c/ssv6006C_reg.h	157;"	d
+ADR_FBUS_CLRTR	smac/hal/ssv6006c/ssv6006C_reg.h	156;"	d
+ADR_FBUS_CTL0_1	smac/hal/ssv6006c/ssv6006C_reg.h	140;"	d
+ADR_FBUS_CTL0_2	smac/hal/ssv6006c/ssv6006C_reg.h	141;"	d
+ADR_FBUS_CTL1_1	smac/hal/ssv6006c/ssv6006C_reg.h	146;"	d
+ADR_FBUS_CTL1_2	smac/hal/ssv6006c/ssv6006C_reg.h	147;"	d
+ADR_FBUS_DAR0	smac/hal/ssv6006c/ssv6006C_reg.h	139;"	d
+ADR_FBUS_DAR1	smac/hal/ssv6006c/ssv6006C_reg.h	145;"	d
+ADR_FBUS_DMA_EN	smac/hal/ssv6006c/ssv6006C_reg.h	162;"	d
+ADR_FBUS_MASKERR	smac/hal/ssv6006c/ssv6006C_reg.h	155;"	d
+ADR_FBUS_MASKTR	smac/hal/ssv6006c/ssv6006C_reg.h	154;"	d
+ADR_FBUS_RAWERR	smac/hal/ssv6006c/ssv6006C_reg.h	151;"	d
+ADR_FBUS_RAWTR	smac/hal/ssv6006c/ssv6006C_reg.h	150;"	d
+ADR_FBUS_SAR0	smac/hal/ssv6006c/ssv6006C_reg.h	138;"	d
+ADR_FBUS_SAR1	smac/hal/ssv6006c/ssv6006C_reg.h	144;"	d
+ADR_FBUS_SHS_DST_REQ_CFG	smac/hal/ssv6006c/ssv6006C_reg.h	159;"	d
+ADR_FBUS_SHS_DST_SREQ_CFG	smac/hal/ssv6006c/ssv6006C_reg.h	161;"	d
+ADR_FBUS_SHS_SRC_REQ_CFG	smac/hal/ssv6006c/ssv6006C_reg.h	158;"	d
+ADR_FBUS_SHS_SRC_SREQ_CFG	smac/hal/ssv6006c/ssv6006C_reg.h	160;"	d
+ADR_FBUS_STATUSERR	smac/hal/ssv6006c/ssv6006C_reg.h	153;"	d
+ADR_FBUS_STATUSTR	smac/hal/ssv6006c/ssv6006C_reg.h	152;"	d
+ADR_FENCE_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	260;"	d
+ADR_FENCE_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	261;"	d
+ADR_FIFO_PTR_READ_BLOCK_CNT	include/ssv6200_reg.h	263;"	d
+ADR_FLASH_ADDR	include/ssv6200_reg.h	386;"	d
+ADR_FLASH_IO0_DLY	smac/hal/ssv6006c/ssv6006C_reg.h	474;"	d
+ADR_FLASH_IO1_DLY	smac/hal/ssv6006c/ssv6006C_reg.h	475;"	d
+ADR_FN1_DMA_RD_START_ADDR_REG	smac/hal/ssv6006c/ssv6006C_reg.h	369;"	d
+ADR_FN1_DMA_START_ADDR_REG	include/ssv6200_reg.h	256;"	d
+ADR_FN1_DMA_START_ADDR_REG	smac/hal/ssv6006c/ssv6006C_reg.h	366;"	d
+ADR_FN1_INT_CTRL_RESET	include/ssv6200_reg.h	257;"	d
+ADR_FN1_INT_CTRL_RESET	smac/hal/ssv6006c/ssv6006C_reg.h	367;"	d
+ADR_FN1_STATUS_REG	include/ssv6200_reg.h	239;"	d
+ADR_FN1_STATUS_REG	smac/hal/ssv6006c/ssv6006C_reg.h	359;"	d
+ADR_FORCE_RX_AGGREGATION_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	607;"	d
+ADR_FPGA_GEMINIARF_SWITCH	smac/hal/ssv6006c/ssv6006C_reg.h	2154;"	d
+ADR_FRAME_TYPE_CNTR_SET	include/ssv6200_reg.h	619;"	d
+ADR_FRAME_TYPE_CNTR_SET	smac/hal/ssv6006c/ssv6006C_reg.h	725;"	d
+ADR_GEMINA_TRX_VER	smac/hal/ssv6006c/ssv6006_mac.h	22;"	d
+ADR_GEMINIA_3_WIRE_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1140;"	d
+ADR_GEMINIA_BT_DCOC_IDAC_REGISTER1	smac/hal/ssv6006c/ssv6006C_reg.h	1198;"	d
+ADR_GEMINIA_BT_DCOC_IDAC_REGISTER10	smac/hal/ssv6006c/ssv6006C_reg.h	1207;"	d
+ADR_GEMINIA_BT_DCOC_IDAC_REGISTER11	smac/hal/ssv6006c/ssv6006C_reg.h	1208;"	d
+ADR_GEMINIA_BT_DCOC_IDAC_REGISTER12	smac/hal/ssv6006c/ssv6006C_reg.h	1209;"	d
+ADR_GEMINIA_BT_DCOC_IDAC_REGISTER13	smac/hal/ssv6006c/ssv6006C_reg.h	1210;"	d
+ADR_GEMINIA_BT_DCOC_IDAC_REGISTER14	smac/hal/ssv6006c/ssv6006C_reg.h	1211;"	d
+ADR_GEMINIA_BT_DCOC_IDAC_REGISTER15	smac/hal/ssv6006c/ssv6006C_reg.h	1212;"	d
+ADR_GEMINIA_BT_DCOC_IDAC_REGISTER16	smac/hal/ssv6006c/ssv6006C_reg.h	1213;"	d
+ADR_GEMINIA_BT_DCOC_IDAC_REGISTER2	smac/hal/ssv6006c/ssv6006C_reg.h	1199;"	d
+ADR_GEMINIA_BT_DCOC_IDAC_REGISTER3	smac/hal/ssv6006c/ssv6006C_reg.h	1200;"	d
+ADR_GEMINIA_BT_DCOC_IDAC_REGISTER4	smac/hal/ssv6006c/ssv6006C_reg.h	1201;"	d
+ADR_GEMINIA_BT_DCOC_IDAC_REGISTER5	smac/hal/ssv6006c/ssv6006C_reg.h	1202;"	d
+ADR_GEMINIA_BT_DCOC_IDAC_REGISTER6	smac/hal/ssv6006c/ssv6006C_reg.h	1203;"	d
+ADR_GEMINIA_BT_DCOC_IDAC_REGISTER7	smac/hal/ssv6006c/ssv6006C_reg.h	1204;"	d
+ADR_GEMINIA_BT_DCOC_IDAC_REGISTER8	smac/hal/ssv6006c/ssv6006C_reg.h	1205;"	d
+ADR_GEMINIA_BT_DCOC_IDAC_REGISTER9	smac/hal/ssv6006c/ssv6006C_reg.h	1206;"	d
+ADR_GEMINIA_BT_RX_FE_HG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1154;"	d
+ADR_GEMINIA_BT_RX_FE_LG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1156;"	d
+ADR_GEMINIA_BT_RX_FE_MG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1155;"	d
+ADR_GEMINIA_BT_RX_FE_ULG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1157;"	d
+ADR_GEMINIA_BT_RX_FILTER_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1145;"	d
+ADR_GEMINIA_BT_TX_DAC_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1160;"	d
+ADR_GEMINIA_CALIBRATION_GAIN_REGISTER0	smac/hal/ssv6006c/ssv6006C_reg.h	1218;"	d
+ADR_GEMINIA_CALIBRATION_GAIN_REGISTER1	smac/hal/ssv6006c/ssv6006C_reg.h	1219;"	d
+ADR_GEMINIA_CALIBRATION_TEST_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1142;"	d
+ADR_GEMINIA_CALIBRATION_TIMER_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1217;"	d
+ADR_GEMINIA_DIGITAL_ADD_ON_R0	smac/hal/ssv6006c/ssv6006C_reg.h	1225;"	d
+ADR_GEMINIA_DIGITAL_ADD_ON_R1	smac/hal/ssv6006c/ssv6006C_reg.h	1226;"	d
+ADR_GEMINIA_DIGITAL_ADD_ON_R2	smac/hal/ssv6006c/ssv6006C_reg.h	1227;"	d
+ADR_GEMINIA_DIGITAL_ADD_ON_R3	smac/hal/ssv6006c/ssv6006C_reg.h	1228;"	d
+ADR_GEMINIA_DIGITAL_ADD_ON_R4	smac/hal/ssv6006c/ssv6006C_reg.h	1229;"	d
+ADR_GEMINIA_DIGITAL_ADD_ON_R5	smac/hal/ssv6006c/ssv6006C_reg.h	1230;"	d
+ADR_GEMINIA_DIGITAL_ADD_ON_R6	smac/hal/ssv6006c/ssv6006C_reg.h	1231;"	d
+ADR_GEMINIA_DPLL_CKT_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1174;"	d
+ADR_GEMINIA_DPLL_FB_DIVISION_REGISTERS	smac/hal/ssv6006c/ssv6006C_reg.h	1175;"	d
+ADR_GEMINIA_DPLL_TOP_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1173;"	d
+ADR_GEMINIA_IO_REG_0	smac/hal/ssv6006c/ssv6006C_reg.h	1255;"	d
+ADR_GEMINIA_IO_REG_1	smac/hal/ssv6006c/ssv6006C_reg.h	1256;"	d
+ADR_GEMINIA_IO_REG_2	smac/hal/ssv6006c/ssv6006C_reg.h	1257;"	d
+ADR_GEMINIA_LDO_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1143;"	d
+ADR_GEMINIA_MANUAL_ENABLE_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1141;"	d
+ADR_GEMINIA_MCU_REG_0	smac/hal/ssv6006c/ssv6006C_reg.h	1258;"	d
+ADR_GEMINIA_MODE_DECODER_TIMER_REGISTER1	smac/hal/ssv6006c/ssv6006C_reg.h	1214;"	d
+ADR_GEMINIA_PMU_BT_CLK	smac/hal/ssv6006c/ssv6006C_reg.h	1248;"	d
+ADR_GEMINIA_PMU_FDB_REG_0	smac/hal/ssv6006c/ssv6006C_reg.h	1254;"	d
+ADR_GEMINIA_PMU_RAM_00	smac/hal/ssv6006c/ssv6006C_reg.h	1259;"	d
+ADR_GEMINIA_PMU_RAM_01	smac/hal/ssv6006c/ssv6006C_reg.h	1260;"	d
+ADR_GEMINIA_PMU_RAM_02	smac/hal/ssv6006c/ssv6006C_reg.h	1261;"	d
+ADR_GEMINIA_PMU_RAM_03	smac/hal/ssv6006c/ssv6006C_reg.h	1262;"	d
+ADR_GEMINIA_PMU_RAM_04	smac/hal/ssv6006c/ssv6006C_reg.h	1263;"	d
+ADR_GEMINIA_PMU_RAM_05	smac/hal/ssv6006c/ssv6006C_reg.h	1264;"	d
+ADR_GEMINIA_PMU_RAM_06	smac/hal/ssv6006c/ssv6006C_reg.h	1265;"	d
+ADR_GEMINIA_PMU_RAM_07	smac/hal/ssv6006c/ssv6006C_reg.h	1266;"	d
+ADR_GEMINIA_PMU_RAM_08	smac/hal/ssv6006c/ssv6006C_reg.h	1267;"	d
+ADR_GEMINIA_PMU_RAM_09	smac/hal/ssv6006c/ssv6006C_reg.h	1268;"	d
+ADR_GEMINIA_PMU_RAM_10	smac/hal/ssv6006c/ssv6006C_reg.h	1269;"	d
+ADR_GEMINIA_PMU_RAM_11	smac/hal/ssv6006c/ssv6006C_reg.h	1270;"	d
+ADR_GEMINIA_PMU_RAM_12	smac/hal/ssv6006c/ssv6006C_reg.h	1271;"	d
+ADR_GEMINIA_PMU_RAM_13	smac/hal/ssv6006c/ssv6006C_reg.h	1272;"	d
+ADR_GEMINIA_PMU_RAM_14	smac/hal/ssv6006c/ssv6006C_reg.h	1273;"	d
+ADR_GEMINIA_PMU_RAM_15	smac/hal/ssv6006c/ssv6006C_reg.h	1274;"	d
+ADR_GEMINIA_PMU_RAM_16	smac/hal/ssv6006c/ssv6006C_reg.h	1275;"	d
+ADR_GEMINIA_PMU_RAM_17	smac/hal/ssv6006c/ssv6006C_reg.h	1276;"	d
+ADR_GEMINIA_PMU_RAM_18	smac/hal/ssv6006c/ssv6006C_reg.h	1277;"	d
+ADR_GEMINIA_PMU_RAM_19	smac/hal/ssv6006c/ssv6006C_reg.h	1278;"	d
+ADR_GEMINIA_PMU_RAM_20	smac/hal/ssv6006c/ssv6006C_reg.h	1279;"	d
+ADR_GEMINIA_PMU_RAM_21	smac/hal/ssv6006c/ssv6006C_reg.h	1280;"	d
+ADR_GEMINIA_PMU_RAM_22	smac/hal/ssv6006c/ssv6006C_reg.h	1281;"	d
+ADR_GEMINIA_PMU_RAM_23	smac/hal/ssv6006c/ssv6006C_reg.h	1282;"	d
+ADR_GEMINIA_PMU_RAM_24	smac/hal/ssv6006c/ssv6006C_reg.h	1283;"	d
+ADR_GEMINIA_PMU_RAM_25	smac/hal/ssv6006c/ssv6006C_reg.h	1284;"	d
+ADR_GEMINIA_PMU_RAM_26	smac/hal/ssv6006c/ssv6006C_reg.h	1285;"	d
+ADR_GEMINIA_PMU_RAM_27	smac/hal/ssv6006c/ssv6006C_reg.h	1286;"	d
+ADR_GEMINIA_PMU_RAM_28	smac/hal/ssv6006c/ssv6006C_reg.h	1287;"	d
+ADR_GEMINIA_PMU_RAM_29	smac/hal/ssv6006c/ssv6006C_reg.h	1288;"	d
+ADR_GEMINIA_PMU_RAM_30	smac/hal/ssv6006c/ssv6006C_reg.h	1289;"	d
+ADR_GEMINIA_PMU_RAM_31	smac/hal/ssv6006c/ssv6006C_reg.h	1290;"	d
+ADR_GEMINIA_PMU_REG_1	smac/hal/ssv6006c/ssv6006C_reg.h	1242;"	d
+ADR_GEMINIA_PMU_REG_2	smac/hal/ssv6006c/ssv6006C_reg.h	1243;"	d
+ADR_GEMINIA_PMU_REG_3	smac/hal/ssv6006c/ssv6006C_reg.h	1244;"	d
+ADR_GEMINIA_PMU_REG_4	smac/hal/ssv6006c/ssv6006C_reg.h	1245;"	d
+ADR_GEMINIA_PMU_REG_5	smac/hal/ssv6006c/ssv6006C_reg.h	1246;"	d
+ADR_GEMINIA_PMU_REG_6	smac/hal/ssv6006c/ssv6006C_reg.h	1247;"	d
+ADR_GEMINIA_PMU_RTC_REG_0	smac/hal/ssv6006c/ssv6006C_reg.h	1250;"	d
+ADR_GEMINIA_PMU_RTC_REG_1	smac/hal/ssv6006c/ssv6006C_reg.h	1251;"	d
+ADR_GEMINIA_PMU_RTC_REG_2	smac/hal/ssv6006c/ssv6006C_reg.h	1252;"	d
+ADR_GEMINIA_PMU_RTC_REG_3	smac/hal/ssv6006c/ssv6006C_reg.h	1253;"	d
+ADR_GEMINIA_PMU_SLEEP_REG	smac/hal/ssv6006c/ssv6006C_reg.h	1249;"	d
+ADR_GEMINIA_READ_ONLY_FLAGS_ADC	smac/hal/ssv6006c/ssv6006C_reg.h	1222;"	d
+ADR_GEMINIA_READ_ONLY_FLAGS_SX1	smac/hal/ssv6006c/ssv6006C_reg.h	1223;"	d
+ADR_GEMINIA_READ_ONLY_FLAGS_SX2	smac/hal/ssv6006c/ssv6006C_reg.h	1224;"	d
+ADR_GEMINIA_RF_D_CAL_TOP_R0	smac/hal/ssv6006c/ssv6006C_reg.h	1238;"	d
+ADR_GEMINIA_RF_D_CAL_TOP_R1	smac/hal/ssv6006c/ssv6006C_reg.h	1239;"	d
+ADR_GEMINIA_RF_D_CAL_TOP_R2	smac/hal/ssv6006c/ssv6006C_reg.h	1240;"	d
+ADR_GEMINIA_RF_D_CAL_TOP_R3	smac/hal/ssv6006c/ssv6006C_reg.h	1241;"	d
+ADR_GEMINIA_RX_ADC_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1158;"	d
+ADR_GEMINIA_RX_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1146;"	d
+ADR_GEMINIA_SX_DUMMY_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1221;"	d
+ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER	smac/hal/ssv6006c/ssv6006C_reg.h	1161;"	d
+ADR_GEMINIA_SX_LDO_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1162;"	d
+ADR_GEMINIA_SYN_AAC	smac/hal/ssv6006c/ssv6006C_reg.h	1171;"	d
+ADR_GEMINIA_SYN_DIV_SDM	smac/hal/ssv6006c/ssv6006C_reg.h	1169;"	d
+ADR_GEMINIA_SYN_FRACTIONAL_AND_INTEGER_8BITS	smac/hal/ssv6006c/ssv6006C_reg.h	1163;"	d
+ADR_GEMINIA_SYN_LPF	smac/hal/ssv6006c/ssv6006C_reg.h	1166;"	d
+ADR_GEMINIA_SYN_PFD_CHP_	smac/hal/ssv6006c/ssv6006C_reg.h	1165;"	d
+ADR_GEMINIA_SYN_REGISTER_INT3BIT_CH_TABLE	smac/hal/ssv6006c/ssv6006C_reg.h	1164;"	d
+ADR_GEMINIA_SYN_SBCAL	smac/hal/ssv6006c/ssv6006C_reg.h	1170;"	d
+ADR_GEMINIA_SYN_TTL	smac/hal/ssv6006c/ssv6006C_reg.h	1172;"	d
+ADR_GEMINIA_SYN_VCO	smac/hal/ssv6006c/ssv6006C_reg.h	1167;"	d
+ADR_GEMINIA_SYN_VCOBF	smac/hal/ssv6006c/ssv6006C_reg.h	1168;"	d
+ADR_GEMINIA_TRX_DUMMY_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1220;"	d
+ADR_GEMINIA_TX_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1149;"	d
+ADR_GEMINIA_TX_UP8X_COEF_R0	smac/hal/ssv6006c/ssv6006C_reg.h	1232;"	d
+ADR_GEMINIA_TX_UP8X_COEF_R1	smac/hal/ssv6006c/ssv6006C_reg.h	1233;"	d
+ADR_GEMINIA_TX_UP8X_COEF_R2	smac/hal/ssv6006c/ssv6006C_reg.h	1234;"	d
+ADR_GEMINIA_TX_UP8X_COEF_R3	smac/hal/ssv6006c/ssv6006C_reg.h	1235;"	d
+ADR_GEMINIA_TX_UP8X_COEF_R4	smac/hal/ssv6006c/ssv6006C_reg.h	1236;"	d
+ADR_GEMINIA_TX_UP8X_COEF_R5	smac/hal/ssv6006c/ssv6006C_reg.h	1237;"	d
+ADR_GEMINIA_WBT_TX_FE_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1147;"	d
+ADR_GEMINIA_WBT_TX_PA_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1148;"	d
+ADR_GEMINIA_WF_DCOC_IDAC_REGISTER1	smac/hal/ssv6006c/ssv6006C_reg.h	1176;"	d
+ADR_GEMINIA_WF_DCOC_IDAC_REGISTER10	smac/hal/ssv6006c/ssv6006C_reg.h	1185;"	d
+ADR_GEMINIA_WF_DCOC_IDAC_REGISTER11	smac/hal/ssv6006c/ssv6006C_reg.h	1186;"	d
+ADR_GEMINIA_WF_DCOC_IDAC_REGISTER12	smac/hal/ssv6006c/ssv6006C_reg.h	1187;"	d
+ADR_GEMINIA_WF_DCOC_IDAC_REGISTER13	smac/hal/ssv6006c/ssv6006C_reg.h	1188;"	d
+ADR_GEMINIA_WF_DCOC_IDAC_REGISTER14	smac/hal/ssv6006c/ssv6006C_reg.h	1189;"	d
+ADR_GEMINIA_WF_DCOC_IDAC_REGISTER15	smac/hal/ssv6006c/ssv6006C_reg.h	1190;"	d
+ADR_GEMINIA_WF_DCOC_IDAC_REGISTER16	smac/hal/ssv6006c/ssv6006C_reg.h	1191;"	d
+ADR_GEMINIA_WF_DCOC_IDAC_REGISTER17	smac/hal/ssv6006c/ssv6006C_reg.h	1192;"	d
+ADR_GEMINIA_WF_DCOC_IDAC_REGISTER18	smac/hal/ssv6006c/ssv6006C_reg.h	1193;"	d
+ADR_GEMINIA_WF_DCOC_IDAC_REGISTER19	smac/hal/ssv6006c/ssv6006C_reg.h	1194;"	d
+ADR_GEMINIA_WF_DCOC_IDAC_REGISTER2	smac/hal/ssv6006c/ssv6006C_reg.h	1177;"	d
+ADR_GEMINIA_WF_DCOC_IDAC_REGISTER20	smac/hal/ssv6006c/ssv6006C_reg.h	1195;"	d
+ADR_GEMINIA_WF_DCOC_IDAC_REGISTER21	smac/hal/ssv6006c/ssv6006C_reg.h	1196;"	d
+ADR_GEMINIA_WF_DCOC_IDAC_REGISTER22	smac/hal/ssv6006c/ssv6006C_reg.h	1197;"	d
+ADR_GEMINIA_WF_DCOC_IDAC_REGISTER3	smac/hal/ssv6006c/ssv6006C_reg.h	1178;"	d
+ADR_GEMINIA_WF_DCOC_IDAC_REGISTER4	smac/hal/ssv6006c/ssv6006C_reg.h	1179;"	d
+ADR_GEMINIA_WF_DCOC_IDAC_REGISTER5	smac/hal/ssv6006c/ssv6006C_reg.h	1180;"	d
+ADR_GEMINIA_WF_DCOC_IDAC_REGISTER6	smac/hal/ssv6006c/ssv6006C_reg.h	1181;"	d
+ADR_GEMINIA_WF_DCOC_IDAC_REGISTER7	smac/hal/ssv6006c/ssv6006C_reg.h	1182;"	d
+ADR_GEMINIA_WF_DCOC_IDAC_REGISTER8	smac/hal/ssv6006c/ssv6006C_reg.h	1183;"	d
+ADR_GEMINIA_WF_DCOC_IDAC_REGISTER9	smac/hal/ssv6006c/ssv6006C_reg.h	1184;"	d
+ADR_GEMINIA_WIFI_R2T_TIMER_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1216;"	d
+ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1150;"	d
+ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1152;"	d
+ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1151;"	d
+ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1153;"	d
+ADR_GEMINIA_WIFI_RX_FILTER_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1144;"	d
+ADR_GEMINIA_WIFI_T2R_TIMER_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1215;"	d
+ADR_GEMINIA_WIFI_TX_DAC_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1159;"	d
+ADR_GETID	include/ssv6200_reg.h	930;"	d
+ADR_GETID	smac/hal/ssv6006c/ssv6006C_reg.h	2108;"	d
+ADR_GLBLE_SET	include/ssv6200_reg.h	777;"	d
+ADR_GLBLE_SET	smac/hal/ssv6006c/ssv6006C_reg.h	946;"	d
+ADR_GLOBAL_SEQUENCE	include/ssv6200_reg.h	421;"	d
+ADR_GLOBAL_SEQUENCE	smac/hal/ssv6006c/ssv6006C_reg.h	564;"	d
+ADR_GPIO_INTERRUPT_BANK_00_TO_07	smac/hal/ssv6006c/ssv6006C_reg.h	515;"	d
+ADR_GPIO_INTERRUPT_BANK_08_TO_15	smac/hal/ssv6006c/ssv6006C_reg.h	516;"	d
+ADR_GPIO_INTERRUPT_BANK_16_TO_22	smac/hal/ssv6006c/ssv6006C_reg.h	517;"	d
+ADR_GPIO_INTERRUPT_MODE_00_TO_07	smac/hal/ssv6006c/ssv6006C_reg.h	518;"	d
+ADR_GPIO_INTERRUPT_MODE_08_TO_15	smac/hal/ssv6006c/ssv6006C_reg.h	519;"	d
+ADR_GPIO_INTERRUPT_MODE_16_TO_22	smac/hal/ssv6006c/ssv6006C_reg.h	520;"	d
+ADR_GPIO_IQ_LOG_STOP	smac/hal/ssv6006c/ssv6006C_reg.h	250;"	d
+ADR_GROUP_WSID	smac/hal/ssv6006c/ssv6006C_reg.h	723;"	d
+ADR_HARD_WIRE_PIN_REGISTER	include/ssv6200_reg.h	1180;"	d
+ADR_HBURST_LOCK	include/ssv6200_reg.h	140;"	d
+ADR_HBURST_LOCK	smac/hal/ssv6006c/ssv6006C_reg.h	259;"	d
+ADR_HBUSREQ_LOCK	include/ssv6200_reg.h	139;"	d
+ADR_HBUSREQ_LOCK	smac/hal/ssv6006c/ssv6006C_reg.h	258;"	d
+ADR_HCI_BULK_IN_TIME_OUT_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	580;"	d
+ADR_HCI_FORCE_PRE_BULK_IN	smac/hal/ssv6006c/ssv6006C_reg.h	579;"	d
+ADR_HCI_MANUAL_ALLOC	smac/hal/ssv6006c/ssv6006C_reg.h	569;"	d
+ADR_HCI_MANUAL_ALLOC_ACTION	smac/hal/ssv6006c/ssv6006C_reg.h	570;"	d
+ADR_HCI_MANUAL_ALLOC_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	571;"	d
+ADR_HCI_REG_0X2C	smac/hal/ssv6006c/ssv6006C_reg.h	565;"	d
+ADR_HCI_STATE_DEBUG_MODE_0	include/ssv6200_reg.h	438;"	d
+ADR_HCI_STATE_DEBUG_MODE_0	smac/hal/ssv6006c/ssv6006C_reg.h	581;"	d
+ADR_HCI_STATE_DEBUG_MODE_1	include/ssv6200_reg.h	439;"	d
+ADR_HCI_STATE_DEBUG_MODE_10	include/ssv6200_reg.h	448;"	d
+ADR_HCI_STATE_DEBUG_MODE_2	include/ssv6200_reg.h	440;"	d
+ADR_HCI_STATE_DEBUG_MODE_2	smac/hal/ssv6006c/ssv6006C_reg.h	582;"	d
+ADR_HCI_STATE_DEBUG_MODE_3	include/ssv6200_reg.h	441;"	d
+ADR_HCI_STATE_DEBUG_MODE_3	smac/hal/ssv6006c/ssv6006C_reg.h	583;"	d
+ADR_HCI_STATE_DEBUG_MODE_4	include/ssv6200_reg.h	442;"	d
+ADR_HCI_STATE_DEBUG_MODE_4	smac/hal/ssv6006c/ssv6006C_reg.h	584;"	d
+ADR_HCI_STATE_DEBUG_MODE_5	include/ssv6200_reg.h	443;"	d
+ADR_HCI_STATE_DEBUG_MODE_5	smac/hal/ssv6006c/ssv6006C_reg.h	585;"	d
+ADR_HCI_STATE_DEBUG_MODE_6	include/ssv6200_reg.h	444;"	d
+ADR_HCI_STATE_DEBUG_MODE_6	smac/hal/ssv6006c/ssv6006C_reg.h	586;"	d
+ADR_HCI_STATE_DEBUG_MODE_7	include/ssv6200_reg.h	445;"	d
+ADR_HCI_STATE_DEBUG_MODE_7	smac/hal/ssv6006c/ssv6006C_reg.h	587;"	d
+ADR_HCI_STATE_DEBUG_MODE_8	include/ssv6200_reg.h	446;"	d
+ADR_HCI_STATE_DEBUG_MODE_9	include/ssv6200_reg.h	447;"	d
+ADR_HCI_TO_PKTBUF_SETTING	smac/hal/ssv6006c/ssv6006C_reg.h	568;"	d
+ADR_HCI_TRX_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	556;"	d
+ADR_HCI_TX_ALLOC_SPENDING_TIME	smac/hal/ssv6006c/ssv6006C_reg.h	590;"	d
+ADR_HCI_TX_ALLOC_SUCCESS_COUNT	smac/hal/ssv6006c/ssv6006C_reg.h	589;"	d
+ADR_HCI_TX_INFO_CLEAR	include/ssv6200_reg.h	423;"	d
+ADR_HCI_TX_INFO_CLEAR	smac/hal/ssv6006c/ssv6006C_reg.h	567;"	d
+ADR_HCI_TX_ON_DEMAND_LENGTH	smac/hal/ssv6006c/ssv6006C_reg.h	588;"	d
+ADR_HCI_TX_RX_INFO_SIZE	include/ssv6200_reg.h	422;"	d
+ADR_HCI_TX_RX_INFO_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	566;"	d
+ADR_HDR_ADDR_SEL	include/ssv6200_reg.h	618;"	d
+ADR_HDR_ADDR_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	724;"	d
+ADR_HIGH_PRIORITY_FRM_HW_ID	smac/hal/ssv6006c/ssv6006C_reg.h	728;"	d
+ADR_HOST_PATH	include/ssv6200_reg.h	312;"	d
+ADR_HOST_WAKE_WIFI_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	289;"	d
+ADR_HS3W_CTRL1	smac/hal/ssv6006c/ssv6006C_reg.h	1675;"	d
+ADR_HS3W_CTRL2	smac/hal/ssv6006c/ssv6006C_reg.h	1676;"	d
+ADR_HS3W_CTRL3	smac/hal/ssv6006c/ssv6006C_reg.h	1677;"	d
+ADR_HS3W_READ_OUT_1	smac/hal/ssv6006c/ssv6006C_reg.h	1679;"	d
+ADR_HS3W_READ_OUT_2_	smac/hal/ssv6006c/ssv6006C_reg.h	1680;"	d
+ADR_HS3W_READ_OUT_3	smac/hal/ssv6006c/ssv6006C_reg.h	1681;"	d
+ADR_HS5W_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	1833;"	d
+ADR_HS5W_MAN_SET_ADD0	smac/hal/ssv6006c/ssv6006C_reg.h	1834;"	d
+ADR_HS5W_MAN_SET_ADD1	smac/hal/ssv6006c/ssv6006C_reg.h	1835;"	d
+ADR_HS5W_MAN_SET_ADD2	smac/hal/ssv6006c/ssv6006C_reg.h	1836;"	d
+ADR_HS5W_MAN_SET_ADD3	smac/hal/ssv6006c/ssv6006C_reg.h	1837;"	d
+ADR_HS5W_MAN_SET_ADD4_CH	smac/hal/ssv6006c/ssv6006C_reg.h	1838;"	d
+ADR_HS5W_MAN_SET_ADD4_CH_5GB	smac/hal/ssv6006c/ssv6006C_reg.h	1839;"	d
+ADR_HS5W_MAN_SET_ADD4_F	smac/hal/ssv6006c/ssv6006C_reg.h	1840;"	d
+ADR_HS5W_MAN_SET_ADD4_F_5GB	smac/hal/ssv6006c/ssv6006C_reg.h	1841;"	d
+ADR_HS5W_MAN_SET_ADD5	smac/hal/ssv6006c/ssv6006C_reg.h	1842;"	d
+ADR_HS5W_MAN_SET_ADD5_5GB	smac/hal/ssv6006c/ssv6006C_reg.h	1843;"	d
+ADR_HS5W_MAN_SET_ADD6	smac/hal/ssv6006c/ssv6006C_reg.h	1844;"	d
+ADR_HS5W_MD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	1832;"	d
+ADR_HSUART_DIV_FRAC	smac/hal/ssv6006c/ssv6006C_reg.h	456;"	d
+ADR_HSUART_DMA_RX_END_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	459;"	d
+ADR_HSUART_DMA_RX_RPT	smac/hal/ssv6006c/ssv6006C_reg.h	461;"	d
+ADR_HSUART_DMA_RX_STR_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	458;"	d
+ADR_HSUART_DMA_RX_WPT	smac/hal/ssv6006c/ssv6006C_reg.h	460;"	d
+ADR_HSUART_DMA_TX_END_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	463;"	d
+ADR_HSUART_DMA_TX_RPT	smac/hal/ssv6006c/ssv6006C_reg.h	465;"	d
+ADR_HSUART_DMA_TX_STR_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	462;"	d
+ADR_HSUART_DMA_TX_WPT	smac/hal/ssv6006c/ssv6006C_reg.h	464;"	d
+ADR_HSUART_EXPANSION_INTERRUPT_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	457;"	d
+ADR_HSUART_FIFO_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	448;"	d
+ADR_HSUART_FIFO_THRESHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	454;"	d
+ADR_HSUART_INTERRUPT_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	455;"	d
+ADR_HSUART_INTRRUPT_ENABLE	smac/hal/ssv6006c/ssv6006C_reg.h	447;"	d
+ADR_HSUART_LINE_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	449;"	d
+ADR_HSUART_LINE_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	451;"	d
+ADR_HSUART_MODEM_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	450;"	d
+ADR_HSUART_MODEM_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	452;"	d
+ADR_HSUART_SCRATCH_BOARD	smac/hal/ssv6006c/ssv6006C_reg.h	453;"	d
+ADR_HSUART_TRX_CHAR	smac/hal/ssv6006c/ssv6006C_reg.h	446;"	d
+ADR_HS_CTRL	include/ssv6200_reg.h	1225;"	d
+ADR_I2CMST_CFG0	smac/hal/ssv6006c/ssv6006C_reg.h	213;"	d
+ADR_I2CMST_ENABLE	smac/hal/ssv6006c/ssv6006C_reg.h	223;"	d
+ADR_I2CMST_INT	smac/hal/ssv6006c/ssv6006C_reg.h	218;"	d
+ADR_I2CMST_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	219;"	d
+ADR_I2CMST_INT_STA	smac/hal/ssv6006c/ssv6006C_reg.h	220;"	d
+ADR_I2CMST_RX_FIFO_TH	smac/hal/ssv6006c/ssv6006C_reg.h	221;"	d
+ADR_I2CMST_SCLK_H_WIDTH	smac/hal/ssv6006c/ssv6006C_reg.h	216;"	d
+ADR_I2CMST_SCLK_L_WIDTH	smac/hal/ssv6006c/ssv6006C_reg.h	217;"	d
+ADR_I2CMST_TAR	smac/hal/ssv6006c/ssv6006C_reg.h	214;"	d
+ADR_I2CMST_TRX_CMD_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	215;"	d
+ADR_I2CMST_TX_FIFO_TH	smac/hal/ssv6006c/ssv6006C_reg.h	222;"	d
+ADR_I2CM_DEV_A	include/ssv6200_reg.h	326;"	d
+ADR_I2CM_DEV_A	smac/hal/ssv6006c/ssv6006C_reg.h	427;"	d
+ADR_I2CM_EN	include/ssv6200_reg.h	325;"	d
+ADR_I2CM_EN	smac/hal/ssv6006c/ssv6006C_reg.h	426;"	d
+ADR_I2CM_EN_2	include/ssv6200_reg.h	330;"	d
+ADR_I2CM_EN_2	smac/hal/ssv6006c/ssv6006C_reg.h	431;"	d
+ADR_I2CM_LEN	include/ssv6200_reg.h	327;"	d
+ADR_I2CM_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	428;"	d
+ADR_I2CM_RDAT	include/ssv6200_reg.h	329;"	d
+ADR_I2CM_RDAT	smac/hal/ssv6006c/ssv6006C_reg.h	430;"	d
+ADR_I2CM_START_STOP_PERIOD	smac/hal/ssv6006c/ssv6006C_reg.h	432;"	d
+ADR_I2CM_WDAT	include/ssv6200_reg.h	328;"	d
+ADR_I2CM_WDAT	smac/hal/ssv6006c/ssv6006C_reg.h	429;"	d
+ADR_I2CS_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	355;"	d
+ADR_I2CS_ID_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	351;"	d
+ADR_I2CS_STATE	smac/hal/ssv6006c/ssv6006C_reg.h	354;"	d
+ADR_I2CS_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	352;"	d
+ADR_I2CS_TIME_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	353;"	d
+ADR_I2SMAS_CFG	smac/hal/ssv6006c/ssv6006C_reg.h	257;"	d
+ADR_I2S_EN	smac/hal/ssv6006c/ssv6006C_reg.h	190;"	d
+ADR_I2S_INTR	smac/hal/ssv6006c/ssv6006C_reg.h	203;"	d
+ADR_I2S_INTR_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	204;"	d
+ADR_I2S_RXFO	smac/hal/ssv6006c/ssv6006C_reg.h	205;"	d
+ADR_I2S_RX_CH_EN	smac/hal/ssv6006c/ssv6006C_reg.h	199;"	d
+ADR_I2S_RX_DMA	smac/hal/ssv6006c/ssv6006C_reg.h	211;"	d
+ADR_I2S_RX_EN	smac/hal/ssv6006c/ssv6006C_reg.h	191;"	d
+ADR_I2S_RX_FIFO_FLUSH	smac/hal/ssv6006c/ssv6006C_reg.h	209;"	d
+ADR_I2S_RX_FIFO_TH	smac/hal/ssv6006c/ssv6006C_reg.h	207;"	d
+ADR_I2S_RX_WORD_RES	smac/hal/ssv6006c/ssv6006C_reg.h	201;"	d
+ADR_I2S_SCLK_SCR_EN	smac/hal/ssv6006c/ssv6006C_reg.h	193;"	d
+ADR_I2S_TXFO	smac/hal/ssv6006c/ssv6006C_reg.h	206;"	d
+ADR_I2S_TX_CH_EN	smac/hal/ssv6006c/ssv6006C_reg.h	200;"	d
+ADR_I2S_TX_DMA	smac/hal/ssv6006c/ssv6006C_reg.h	212;"	d
+ADR_I2S_TX_EN	smac/hal/ssv6006c/ssv6006C_reg.h	192;"	d
+ADR_I2S_TX_FIFO_FLUSH	smac/hal/ssv6006c/ssv6006C_reg.h	210;"	d
+ADR_I2S_TX_FIFO_TH	smac/hal/ssv6006c/ssv6006C_reg.h	208;"	d
+ADR_I2S_TX_WORD_RES	smac/hal/ssv6006c/ssv6006C_reg.h	202;"	d
+ADR_I2S_WS_DEF	smac/hal/ssv6006c/ssv6006C_reg.h	194;"	d
+ADR_IC_TIME_TAG_0	include/ssv6200_reg.h	767;"	d
+ADR_IC_TIME_TAG_1	include/ssv6200_reg.h	768;"	d
+ADR_ID_ALC_FAIL1	include/ssv6200_reg.h	848;"	d
+ADR_ID_ALC_FAIL1	smac/hal/ssv6006c/ssv6006C_reg.h	1024;"	d
+ADR_ID_ALC_FAIL2	include/ssv6200_reg.h	849;"	d
+ADR_ID_ALC_FAIL2	smac/hal/ssv6006c/ssv6006C_reg.h	1025;"	d
+ADR_ID_INFO_STA	include/ssv6200_reg.h	948;"	d
+ADR_ID_INFO_STA	smac/hal/ssv6006c/ssv6006C_reg.h	2126;"	d
+ADR_ID_IN_USE	include/ssv6200_reg.h	600;"	d
+ADR_ID_IN_USE	smac/hal/ssv6006c/ssv6006C_reg.h	721;"	d
+ADR_ID_LEN_THREADSHOLD1	include/ssv6200_reg.h	944;"	d
+ADR_ID_LEN_THREADSHOLD1	smac/hal/ssv6006c/ssv6006C_reg.h	2122;"	d
+ADR_ID_LEN_THREADSHOLD2	include/ssv6200_reg.h	945;"	d
+ADR_ID_LEN_THREADSHOLD2	smac/hal/ssv6006c/ssv6006C_reg.h	2123;"	d
+ADR_IMD_CFG	include/ssv6200_reg.h	934;"	d
+ADR_IMD_CFG	smac/hal/ssv6006c/ssv6006C_reg.h	2112;"	d
+ADR_IMD_STA	include/ssv6200_reg.h	935;"	d
+ADR_IMD_STA	smac/hal/ssv6006c/ssv6006C_reg.h	2113;"	d
+ADR_INFO0	include/ssv6200_reg.h	724;"	d
+ADR_INFO1	include/ssv6200_reg.h	725;"	d
+ADR_INFO10	include/ssv6200_reg.h	734;"	d
+ADR_INFO11	include/ssv6200_reg.h	735;"	d
+ADR_INFO12	include/ssv6200_reg.h	736;"	d
+ADR_INFO13	include/ssv6200_reg.h	737;"	d
+ADR_INFO14	include/ssv6200_reg.h	738;"	d
+ADR_INFO15	include/ssv6200_reg.h	739;"	d
+ADR_INFO16	include/ssv6200_reg.h	740;"	d
+ADR_INFO17	include/ssv6200_reg.h	741;"	d
+ADR_INFO18	include/ssv6200_reg.h	742;"	d
+ADR_INFO19	include/ssv6200_reg.h	743;"	d
+ADR_INFO2	include/ssv6200_reg.h	726;"	d
+ADR_INFO20	include/ssv6200_reg.h	744;"	d
+ADR_INFO21	include/ssv6200_reg.h	745;"	d
+ADR_INFO22	include/ssv6200_reg.h	746;"	d
+ADR_INFO23	include/ssv6200_reg.h	747;"	d
+ADR_INFO24	include/ssv6200_reg.h	748;"	d
+ADR_INFO25	include/ssv6200_reg.h	749;"	d
+ADR_INFO26	include/ssv6200_reg.h	750;"	d
+ADR_INFO27	include/ssv6200_reg.h	751;"	d
+ADR_INFO28	include/ssv6200_reg.h	752;"	d
+ADR_INFO29	include/ssv6200_reg.h	753;"	d
+ADR_INFO3	include/ssv6200_reg.h	727;"	d
+ADR_INFO30	include/ssv6200_reg.h	754;"	d
+ADR_INFO31	include/ssv6200_reg.h	755;"	d
+ADR_INFO32	include/ssv6200_reg.h	756;"	d
+ADR_INFO33	include/ssv6200_reg.h	757;"	d
+ADR_INFO34	include/ssv6200_reg.h	758;"	d
+ADR_INFO35	include/ssv6200_reg.h	759;"	d
+ADR_INFO36	include/ssv6200_reg.h	760;"	d
+ADR_INFO37	include/ssv6200_reg.h	761;"	d
+ADR_INFO38	include/ssv6200_reg.h	762;"	d
+ADR_INFO4	include/ssv6200_reg.h	728;"	d
+ADR_INFO5	include/ssv6200_reg.h	729;"	d
+ADR_INFO6	include/ssv6200_reg.h	730;"	d
+ADR_INFO7	include/ssv6200_reg.h	731;"	d
+ADR_INFO8	include/ssv6200_reg.h	732;"	d
+ADR_INFO9	include/ssv6200_reg.h	733;"	d
+ADR_INFO_IDX_ADDR	include/ssv6200_reg.h	765;"	d
+ADR_INFO_LEN_ADDR	include/ssv6200_reg.h	766;"	d
+ADR_INFO_MASK	include/ssv6200_reg.h	763;"	d
+ADR_INFO_RATE_OFFSET	include/ssv6200_reg.h	764;"	d
+ADR_INS_SPACE_END_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	477;"	d
+ADR_INS_SPACE_START_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	476;"	d
+ADR_INT_FIQ_RAW	include/ssv6200_reg.h	356;"	d
+ADR_INT_FIQ_STS	include/ssv6200_reg.h	354;"	d
+ADR_INT_GPI_CFG	include/ssv6200_reg.h	360;"	d
+ADR_INT_IRQ_RAW	include/ssv6200_reg.h	355;"	d
+ADR_INT_IRQ_STS	include/ssv6200_reg.h	353;"	d
+ADR_INT_MASK	include/ssv6200_reg.h	351;"	d
+ADR_INT_MASK_REG	include/ssv6200_reg.h	237;"	d
+ADR_INT_MASK_REG	smac/hal/ssv6006c/ssv6006C_reg.h	357;"	d
+ADR_INT_MODE	include/ssv6200_reg.h	352;"	d
+ADR_INT_PERI_MASK	include/ssv6200_reg.h	357;"	d
+ADR_INT_PERI_RAW	include/ssv6200_reg.h	359;"	d
+ADR_INT_PERI_STS	include/ssv6200_reg.h	358;"	d
+ADR_INT_STATUS_REG	include/ssv6200_reg.h	238;"	d
+ADR_INT_STATUS_REG	smac/hal/ssv6006c/ssv6006C_reg.h	358;"	d
+ADR_INT_TAG	include/ssv6200_reg.h	324;"	d
+ADR_INT_THRU_GPIO	smac/hal/ssv6006c/ssv6006C_reg.h	347;"	d
+ADR_IO_DS	smac/hal/ssv6006c/ssv6006C_reg.h	345;"	d
+ADR_IO_FUNC_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	346;"	d
+ADR_IO_PDE	smac/hal/ssv6006c/ssv6006C_reg.h	344;"	d
+ADR_IO_PI	smac/hal/ssv6006c/ssv6006C_reg.h	340;"	d
+ADR_IO_PIE	smac/hal/ssv6006c/ssv6006C_reg.h	341;"	d
+ADR_IO_PO	smac/hal/ssv6006c/ssv6006C_reg.h	339;"	d
+ADR_IO_POEN	smac/hal/ssv6006c/ssv6006C_reg.h	342;"	d
+ADR_IO_PORT_REG	include/ssv6200_reg.h	236;"	d
+ADR_IO_PORT_REG	smac/hal/ssv6006c/ssv6006C_reg.h	356;"	d
+ADR_IO_PUE	smac/hal/ssv6006c/ssv6006C_reg.h	343;"	d
+ADR_IO_REG_PORT_REG	include/ssv6200_reg.h	258;"	d
+ADR_IPC_INTERRUPT	smac/hal/ssv6006c/ssv6006C_reg.h	521;"	d
+ADR_LDO_REGISTER	include/ssv6200_reg.h	1182;"	d
+ADR_LEN	include/ssv6200_reg.h	388;"	d
+ADR_LEN_FLT	include/ssv6200_reg.h	623;"	d
+ADR_LEN_FLT	smac/hal/ssv6006c/ssv6006C_reg.h	735;"	d
+ADR_L_TRX_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	197;"	d
+ADR_MAC_CLOCK_ENABLE	include/ssv6200_reg.h	774;"	d
+ADR_MAC_CLOCK_ENABLE	smac/hal/ssv6006c/ssv6006C_reg.h	943;"	d
+ADR_MAC_CSR_CLOCK_ENABLE	include/ssv6200_reg.h	776;"	d
+ADR_MAC_CSR_CLOCK_ENABLE	smac/hal/ssv6006c/ssv6006C_reg.h	945;"	d
+ADR_MAC_ENGINE_CLOCK_ENABLE	include/ssv6200_reg.h	775;"	d
+ADR_MAC_ENGINE_CLOCK_ENABLE	smac/hal/ssv6006c/ssv6006C_reg.h	944;"	d
+ADR_MAC_MODE	include/ssv6200_reg.h	770;"	d
+ADR_MAC_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	939;"	d
+ADR_MANUAL_DS	smac/hal/ssv6006c/ssv6006C_reg.h	338;"	d
+ADR_MANUAL_ENABLE_REGISTER	include/ssv6200_reg.h	1181;"	d
+ADR_MANUAL_IO	smac/hal/ssv6006c/ssv6006C_reg.h	335;"	d
+ADR_MANUAL_MODE_RX_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	467;"	d
+ADR_MANUAL_MODE_TX_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	466;"	d
+ADR_MANUAL_PD	smac/hal/ssv6006c/ssv6006C_reg.h	337;"	d
+ADR_MANUAL_PU	smac/hal/ssv6006c/ssv6006C_reg.h	336;"	d
+ADR_MANUAL_RESET_N	smac/hal/ssv6006c/ssv6006C_reg.h	265;"	d
+ADR_MASK_TYPHOST_INT_MAP	smac/hal/ssv6006c/ssv6006C_reg.h	498;"	d
+ADR_MASK_TYPHOST_INT_MAP_02	smac/hal/ssv6006c/ssv6006C_reg.h	489;"	d
+ADR_MASK_TYPHOST_INT_MAP_15	smac/hal/ssv6006c/ssv6006C_reg.h	492;"	d
+ADR_MASK_TYPHOST_INT_MAP_31	smac/hal/ssv6006c/ssv6006C_reg.h	495;"	d
+ADR_MASK_TYPMCU_INT_MAP	smac/hal/ssv6006c/ssv6006C_reg.h	511;"	d
+ADR_MASK_TYPMCU_INT_MAP_02	smac/hal/ssv6006c/ssv6006C_reg.h	502;"	d
+ADR_MASK_TYPMCU_INT_MAP_15	smac/hal/ssv6006c/ssv6006C_reg.h	505;"	d
+ADR_MASK_TYPMCU_INT_MAP_31	smac/hal/ssv6006c/ssv6006C_reg.h	508;"	d
+ADR_MBOX_HALT_CFG	include/ssv6200_reg.h	905;"	d
+ADR_MBOX_HALT_CFG	smac/hal/ssv6006c/ssv6006C_reg.h	2080;"	d
+ADR_MBOX_HALT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	2081;"	d
+ADR_MB_CPU_INT	include/ssv6200_reg.h	895;"	d
+ADR_MB_CPU_INT	smac/hal/ssv6006c/ssv6006C_reg.h	2068;"	d
+ADR_MB_CPU_INT_ALT	smac/hal/ssv6006c/ssv6006C_reg.h	2067;"	d
+ADR_MB_DBG_CFG1	include/ssv6200_reg.h	906;"	d
+ADR_MB_DBG_CFG1	smac/hal/ssv6006c/ssv6006C_reg.h	2082;"	d
+ADR_MB_DBG_CFG2	include/ssv6200_reg.h	907;"	d
+ADR_MB_DBG_CFG2	smac/hal/ssv6006c/ssv6006C_reg.h	2083;"	d
+ADR_MB_DBG_CFG3	include/ssv6200_reg.h	908;"	d
+ADR_MB_DBG_CFG3	smac/hal/ssv6006c/ssv6006C_reg.h	2084;"	d
+ADR_MB_DBG_CFG4	include/ssv6200_reg.h	909;"	d
+ADR_MB_DBG_CFG4	smac/hal/ssv6006c/ssv6006C_reg.h	2085;"	d
+ADR_MB_IDTBL_0_STATUS	include/ssv6200_reg.h	1237;"	d
+ADR_MB_IDTBL_1_STATUS	include/ssv6200_reg.h	1238;"	d
+ADR_MB_IDTBL_2_STATUS	include/ssv6200_reg.h	1239;"	d
+ADR_MB_IDTBL_3_STATUS	include/ssv6200_reg.h	1240;"	d
+ADR_MB_IN_FF_FLUSH	include/ssv6200_reg.h	922;"	d
+ADR_MB_IN_FF_FLUSH	smac/hal/ssv6006c/ssv6006C_reg.h	2099;"	d
+ADR_MB_IN_FF_FLUSH	smac/hal/ssv6006c/ssv6006C_reg.h	2100;"	d
+ADR_MB_NEQID_0_STATUS	include/ssv6200_reg.h	1249;"	d
+ADR_MB_NEQID_1_STATUS	include/ssv6200_reg.h	1250;"	d
+ADR_MB_NEQID_2_STATUS	include/ssv6200_reg.h	1251;"	d
+ADR_MB_NEQID_3_STATUS	include/ssv6200_reg.h	1252;"	d
+ADR_MB_OUT_QUEUE_CFG	include/ssv6200_reg.h	910;"	d
+ADR_MB_OUT_QUEUE_CFG	smac/hal/ssv6006c/ssv6006C_reg.h	2086;"	d
+ADR_MB_OUT_QUEUE_FLUSH	include/ssv6200_reg.h	911;"	d
+ADR_MB_OUT_QUEUE_FLUSH	smac/hal/ssv6006c/ssv6006C_reg.h	2087;"	d
+ADR_MB_OUT_QUEUE_FLUSH	smac/hal/ssv6006c/ssv6006C_reg.h	2088;"	d
+ADR_MB_THRESHOLD10	include/ssv6200_reg.h	920;"	d
+ADR_MB_THRESHOLD10	smac/hal/ssv6006c/ssv6006C_reg.h	2097;"	d
+ADR_MB_THRESHOLD6	include/ssv6200_reg.h	916;"	d
+ADR_MB_THRESHOLD6	smac/hal/ssv6006c/ssv6006C_reg.h	2093;"	d
+ADR_MB_THRESHOLD7	include/ssv6200_reg.h	917;"	d
+ADR_MB_THRESHOLD7	smac/hal/ssv6006c/ssv6006C_reg.h	2094;"	d
+ADR_MB_THRESHOLD8	include/ssv6200_reg.h	918;"	d
+ADR_MB_THRESHOLD8	smac/hal/ssv6006c/ssv6006C_reg.h	2095;"	d
+ADR_MB_THRESHOLD9	include/ssv6200_reg.h	919;"	d
+ADR_MB_THRESHOLD9	smac/hal/ssv6006c/ssv6006C_reg.h	2096;"	d
+ADR_MB_TRASH_CFG	include/ssv6200_reg.h	921;"	d
+ADR_MB_TRASH_CFG	smac/hal/ssv6006c/ssv6006C_reg.h	2098;"	d
+ADR_MCU_DBG_DATA	include/ssv6200_reg.h	124;"	d
+ADR_MCU_DBG_SEL	include/ssv6200_reg.h	123;"	d
+ADR_MCU_NOTIFY_HOST_EVENT	smac/hal/ssv6006c/ssv6006C_reg.h	368;"	d
+ADR_MCU_STATUS	include/ssv6200_reg.h	901;"	d
+ADR_MCU_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	2074;"	d
+ADR_MCU_WDOG_REG	include/ssv6200_reg.h	181;"	d
+ADR_MCU_WDOG_REG	smac/hal/ssv6006c/ssv6006C_reg.h	323;"	d
+ADR_MIB_AMPDU	include/ssv6200_reg.h	622;"	d
+ADR_MIB_AMPDU	smac/hal/ssv6006c/ssv6006C_reg.h	734;"	d
+ADR_MIB_DELIMITER	include/ssv6200_reg.h	624;"	d
+ADR_MIB_DELIMITER	smac/hal/ssv6006c/ssv6006C_reg.h	736;"	d
+ADR_MIB_EN	include/ssv6200_reg.h	789;"	d
+ADR_MIB_EN	smac/hal/ssv6006c/ssv6006C_reg.h	965;"	d
+ADR_MIB_LEN_FAIL	include/ssv6200_reg.h	598;"	d
+ADR_MIB_LEN_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	719;"	d
+ADR_MIB_SCRT_CCMP0	include/ssv6200_reg.h	842;"	d
+ADR_MIB_SCRT_CCMP0	smac/hal/ssv6006c/ssv6006C_reg.h	1018;"	d
+ADR_MIB_SCRT_CCMP1	include/ssv6200_reg.h	843;"	d
+ADR_MIB_SCRT_CCMP1	smac/hal/ssv6006c/ssv6006C_reg.h	1019;"	d
+ADR_MIB_SCRT_TKIP0	include/ssv6200_reg.h	839;"	d
+ADR_MIB_SCRT_TKIP0	smac/hal/ssv6006c/ssv6006C_reg.h	1015;"	d
+ADR_MIB_SCRT_TKIP1	include/ssv6200_reg.h	840;"	d
+ADR_MIB_SCRT_TKIP1	smac/hal/ssv6006c/ssv6006C_reg.h	1016;"	d
+ADR_MIB_SCRT_TKIP2	include/ssv6200_reg.h	841;"	d
+ADR_MIB_SCRT_TKIP2	smac/hal/ssv6006c/ssv6006C_reg.h	1017;"	d
+ADR_MMU_CTRL	include/ssv6200_reg.h	1224;"	d
+ADR_MMU_STATUS	include/ssv6200_reg.h	1233;"	d
+ADR_MODE_DECODER_TIMER_REGISTER1	smac/hal/ssv6006c/ssv6006C_reg.h	1584;"	d
+ADR_MODE_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1510;"	d
+ADR_MRX_ACK_NTF	include/ssv6200_reg.h	814;"	d
+ADR_MRX_ACK_NTF	smac/hal/ssv6006c/ssv6006C_reg.h	990;"	d
+ADR_MRX_ALC_FAIL	include/ssv6200_reg.h	810;"	d
+ADR_MRX_ALC_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	986;"	d
+ADR_MRX_BAR_NTF	include/ssv6200_reg.h	819;"	d
+ADR_MRX_BAR_NTF	smac/hal/ssv6006c/ssv6006C_reg.h	995;"	d
+ADR_MRX_BA_DBG	include/ssv6200_reg.h	552;"	d
+ADR_MRX_BA_DBG	smac/hal/ssv6006c/ssv6006C_reg.h	673;"	d
+ADR_MRX_BA_NTF	include/ssv6200_reg.h	815;"	d
+ADR_MRX_BA_NTF	smac/hal/ssv6006c/ssv6006C_reg.h	991;"	d
+ADR_MRX_CSR_NTF	include/ssv6200_reg.h	822;"	d
+ADR_MRX_CSR_NTF	smac/hal/ssv6006c/ssv6006C_reg.h	998;"	d
+ADR_MRX_CTS_NTF	include/ssv6200_reg.h	813;"	d
+ADR_MRX_CTS_NTF	smac/hal/ssv6006c/ssv6006C_reg.h	989;"	d
+ADR_MRX_DATA_NTF	include/ssv6200_reg.h	816;"	d
+ADR_MRX_DATA_NTF	smac/hal/ssv6006c/ssv6006C_reg.h	992;"	d
+ADR_MRX_DAT_CRC_NTF	include/ssv6200_reg.h	818;"	d
+ADR_MRX_DAT_CRC_NTF	smac/hal/ssv6006c/ssv6006C_reg.h	994;"	d
+ADR_MRX_DAT_NTF	include/ssv6200_reg.h	811;"	d
+ADR_MRX_DAT_NTF	smac/hal/ssv6006c/ssv6006C_reg.h	987;"	d
+ADR_MRX_DUP_FRM	include/ssv6200_reg.h	804;"	d
+ADR_MRX_DUP_FRM	smac/hal/ssv6006c/ssv6006C_reg.h	980;"	d
+ADR_MRX_ERR	include/ssv6200_reg.h	601;"	d
+ADR_MRX_ERR	smac/hal/ssv6006c/ssv6006C_reg.h	722;"	d
+ADR_MRX_FCS_ERR	include/ssv6200_reg.h	807;"	d
+ADR_MRX_FCS_ERR	smac/hal/ssv6006c/ssv6006C_reg.h	983;"	d
+ADR_MRX_FCS_SUCC	include/ssv6200_reg.h	808;"	d
+ADR_MRX_FCS_SUCC	smac/hal/ssv6006c/ssv6006C_reg.h	984;"	d
+ADR_MRX_FLT_EN0	include/ssv6200_reg.h	569;"	d
+ADR_MRX_FLT_EN0	smac/hal/ssv6006c/ssv6006C_reg.h	690;"	d
+ADR_MRX_FLT_EN1	include/ssv6200_reg.h	570;"	d
+ADR_MRX_FLT_EN1	smac/hal/ssv6006c/ssv6006C_reg.h	691;"	d
+ADR_MRX_FLT_EN10	smac/hal/ssv6006c/ssv6006C_reg.h	731;"	d
+ADR_MRX_FLT_EN2	include/ssv6200_reg.h	571;"	d
+ADR_MRX_FLT_EN2	smac/hal/ssv6006c/ssv6006C_reg.h	692;"	d
+ADR_MRX_FLT_EN3	include/ssv6200_reg.h	572;"	d
+ADR_MRX_FLT_EN3	smac/hal/ssv6006c/ssv6006C_reg.h	693;"	d
+ADR_MRX_FLT_EN4	include/ssv6200_reg.h	573;"	d
+ADR_MRX_FLT_EN4	smac/hal/ssv6006c/ssv6006C_reg.h	694;"	d
+ADR_MRX_FLT_EN5	include/ssv6200_reg.h	574;"	d
+ADR_MRX_FLT_EN5	smac/hal/ssv6006c/ssv6006C_reg.h	695;"	d
+ADR_MRX_FLT_EN6	include/ssv6200_reg.h	575;"	d
+ADR_MRX_FLT_EN6	smac/hal/ssv6006c/ssv6006C_reg.h	696;"	d
+ADR_MRX_FLT_EN7	include/ssv6200_reg.h	576;"	d
+ADR_MRX_FLT_EN7	smac/hal/ssv6006c/ssv6006C_reg.h	697;"	d
+ADR_MRX_FLT_EN8	include/ssv6200_reg.h	577;"	d
+ADR_MRX_FLT_EN8	smac/hal/ssv6006c/ssv6006C_reg.h	698;"	d
+ADR_MRX_FLT_EN9	smac/hal/ssv6006c/ssv6006C_reg.h	730;"	d
+ADR_MRX_FLT_TB0	include/ssv6200_reg.h	553;"	d
+ADR_MRX_FLT_TB0	smac/hal/ssv6006c/ssv6006C_reg.h	674;"	d
+ADR_MRX_FLT_TB1	include/ssv6200_reg.h	554;"	d
+ADR_MRX_FLT_TB1	smac/hal/ssv6006c/ssv6006C_reg.h	675;"	d
+ADR_MRX_FLT_TB10	include/ssv6200_reg.h	563;"	d
+ADR_MRX_FLT_TB10	smac/hal/ssv6006c/ssv6006C_reg.h	684;"	d
+ADR_MRX_FLT_TB11	include/ssv6200_reg.h	564;"	d
+ADR_MRX_FLT_TB11	smac/hal/ssv6006c/ssv6006C_reg.h	685;"	d
+ADR_MRX_FLT_TB12	include/ssv6200_reg.h	565;"	d
+ADR_MRX_FLT_TB12	smac/hal/ssv6006c/ssv6006C_reg.h	686;"	d
+ADR_MRX_FLT_TB13	include/ssv6200_reg.h	566;"	d
+ADR_MRX_FLT_TB13	smac/hal/ssv6006c/ssv6006C_reg.h	687;"	d
+ADR_MRX_FLT_TB14	include/ssv6200_reg.h	567;"	d
+ADR_MRX_FLT_TB14	smac/hal/ssv6006c/ssv6006C_reg.h	688;"	d
+ADR_MRX_FLT_TB15	include/ssv6200_reg.h	568;"	d
+ADR_MRX_FLT_TB15	smac/hal/ssv6006c/ssv6006C_reg.h	689;"	d
+ADR_MRX_FLT_TB2	include/ssv6200_reg.h	555;"	d
+ADR_MRX_FLT_TB2	smac/hal/ssv6006c/ssv6006C_reg.h	676;"	d
+ADR_MRX_FLT_TB3	include/ssv6200_reg.h	556;"	d
+ADR_MRX_FLT_TB3	smac/hal/ssv6006c/ssv6006C_reg.h	677;"	d
+ADR_MRX_FLT_TB4	include/ssv6200_reg.h	557;"	d
+ADR_MRX_FLT_TB4	smac/hal/ssv6006c/ssv6006C_reg.h	678;"	d
+ADR_MRX_FLT_TB5	include/ssv6200_reg.h	558;"	d
+ADR_MRX_FLT_TB5	smac/hal/ssv6006c/ssv6006C_reg.h	679;"	d
+ADR_MRX_FLT_TB6	include/ssv6200_reg.h	559;"	d
+ADR_MRX_FLT_TB6	smac/hal/ssv6006c/ssv6006C_reg.h	680;"	d
+ADR_MRX_FLT_TB7	include/ssv6200_reg.h	560;"	d
+ADR_MRX_FLT_TB7	smac/hal/ssv6006c/ssv6006C_reg.h	681;"	d
+ADR_MRX_FLT_TB8	include/ssv6200_reg.h	561;"	d
+ADR_MRX_FLT_TB8	smac/hal/ssv6006c/ssv6006C_reg.h	682;"	d
+ADR_MRX_FLT_TB9	include/ssv6200_reg.h	562;"	d
+ADR_MRX_FLT_TB9	smac/hal/ssv6006c/ssv6006C_reg.h	683;"	d
+ADR_MRX_FRG_FRM	include/ssv6200_reg.h	805;"	d
+ADR_MRX_FRG_FRM	smac/hal/ssv6006c/ssv6006C_reg.h	981;"	d
+ADR_MRX_GROUP_FRM	include/ssv6200_reg.h	806;"	d
+ADR_MRX_GROUP_FRM	smac/hal/ssv6006c/ssv6006C_reg.h	982;"	d
+ADR_MRX_LEN_FLT	include/ssv6200_reg.h	578;"	d
+ADR_MRX_LEN_FLT	smac/hal/ssv6006c/ssv6006C_reg.h	699;"	d
+ADR_MRX_MB_MISS	include/ssv6200_reg.h	820;"	d
+ADR_MRX_MB_MISS	smac/hal/ssv6006c/ssv6006C_reg.h	996;"	d
+ADR_MRX_MCAST_CTRL0	include/ssv6200_reg.h	535;"	d
+ADR_MRX_MCAST_CTRL0	smac/hal/ssv6006c/ssv6006C_reg.h	656;"	d
+ADR_MRX_MCAST_CTRL1	include/ssv6200_reg.h	540;"	d
+ADR_MRX_MCAST_CTRL1	smac/hal/ssv6006c/ssv6006C_reg.h	661;"	d
+ADR_MRX_MCAST_CTRL2	include/ssv6200_reg.h	545;"	d
+ADR_MRX_MCAST_CTRL2	smac/hal/ssv6006c/ssv6006C_reg.h	666;"	d
+ADR_MRX_MCAST_CTRL3	include/ssv6200_reg.h	550;"	d
+ADR_MRX_MCAST_CTRL3	smac/hal/ssv6006c/ssv6006C_reg.h	671;"	d
+ADR_MRX_MCAST_MK0_0	include/ssv6200_reg.h	533;"	d
+ADR_MRX_MCAST_MK0_0	smac/hal/ssv6006c/ssv6006C_reg.h	654;"	d
+ADR_MRX_MCAST_MK0_1	include/ssv6200_reg.h	534;"	d
+ADR_MRX_MCAST_MK0_1	smac/hal/ssv6006c/ssv6006C_reg.h	655;"	d
+ADR_MRX_MCAST_MK1_0	include/ssv6200_reg.h	538;"	d
+ADR_MRX_MCAST_MK1_0	smac/hal/ssv6006c/ssv6006C_reg.h	659;"	d
+ADR_MRX_MCAST_MK1_1	include/ssv6200_reg.h	539;"	d
+ADR_MRX_MCAST_MK1_1	smac/hal/ssv6006c/ssv6006C_reg.h	660;"	d
+ADR_MRX_MCAST_MK2_0	include/ssv6200_reg.h	543;"	d
+ADR_MRX_MCAST_MK2_0	smac/hal/ssv6006c/ssv6006C_reg.h	664;"	d
+ADR_MRX_MCAST_MK2_1	include/ssv6200_reg.h	544;"	d
+ADR_MRX_MCAST_MK2_1	smac/hal/ssv6006c/ssv6006C_reg.h	665;"	d
+ADR_MRX_MCAST_MK3_0	include/ssv6200_reg.h	548;"	d
+ADR_MRX_MCAST_MK3_0	smac/hal/ssv6006c/ssv6006C_reg.h	669;"	d
+ADR_MRX_MCAST_MK3_1	include/ssv6200_reg.h	549;"	d
+ADR_MRX_MCAST_MK3_1	smac/hal/ssv6006c/ssv6006C_reg.h	670;"	d
+ADR_MRX_MCAST_TB0_0	include/ssv6200_reg.h	531;"	d
+ADR_MRX_MCAST_TB0_0	smac/hal/ssv6006c/ssv6006C_reg.h	652;"	d
+ADR_MRX_MCAST_TB0_1	include/ssv6200_reg.h	532;"	d
+ADR_MRX_MCAST_TB0_1	smac/hal/ssv6006c/ssv6006C_reg.h	653;"	d
+ADR_MRX_MCAST_TB1_0	include/ssv6200_reg.h	536;"	d
+ADR_MRX_MCAST_TB1_0	smac/hal/ssv6006c/ssv6006C_reg.h	657;"	d
+ADR_MRX_MCAST_TB1_1	include/ssv6200_reg.h	537;"	d
+ADR_MRX_MCAST_TB1_1	smac/hal/ssv6006c/ssv6006C_reg.h	658;"	d
+ADR_MRX_MCAST_TB2_0	include/ssv6200_reg.h	541;"	d
+ADR_MRX_MCAST_TB2_0	smac/hal/ssv6006c/ssv6006C_reg.h	662;"	d
+ADR_MRX_MCAST_TB2_1	include/ssv6200_reg.h	542;"	d
+ADR_MRX_MCAST_TB2_1	smac/hal/ssv6006c/ssv6006C_reg.h	663;"	d
+ADR_MRX_MCAST_TB3_0	include/ssv6200_reg.h	546;"	d
+ADR_MRX_MCAST_TB3_0	smac/hal/ssv6006c/ssv6006C_reg.h	667;"	d
+ADR_MRX_MCAST_TB3_1	include/ssv6200_reg.h	547;"	d
+ADR_MRX_MCAST_TB3_1	smac/hal/ssv6006c/ssv6006C_reg.h	668;"	d
+ADR_MRX_MISS	include/ssv6200_reg.h	809;"	d
+ADR_MRX_MISS	smac/hal/ssv6006c/ssv6006C_reg.h	985;"	d
+ADR_MRX_MNG_NTF	include/ssv6200_reg.h	817;"	d
+ADR_MRX_MNG_NTF	smac/hal/ssv6006c/ssv6006C_reg.h	993;"	d
+ADR_MRX_NIDLE_MISS	include/ssv6200_reg.h	821;"	d
+ADR_MRX_NIDLE_MISS	smac/hal/ssv6006c/ssv6006C_reg.h	997;"	d
+ADR_MRX_PHY_INFO	include/ssv6200_reg.h	551;"	d
+ADR_MRX_PHY_INFO	smac/hal/ssv6006c/ssv6006C_reg.h	672;"	d
+ADR_MRX_RTS_NTF	include/ssv6200_reg.h	812;"	d
+ADR_MRX_RTS_NTF	smac/hal/ssv6006c/ssv6006C_reg.h	988;"	d
+ADR_MRX_WATCH_DOG	include/ssv6200_reg.h	593;"	d
+ADR_MRX_WATCH_DOG	smac/hal/ssv6006c/ssv6006C_reg.h	714;"	d
+ADR_MTX_ACK_FAIL	include/ssv6200_reg.h	800;"	d
+ADR_MTX_ACK_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	976;"	d
+ADR_MTX_ACK_TX	include/ssv6200_reg.h	802;"	d
+ADR_MTX_ACK_TX	smac/hal/ssv6006c/ssv6006C_reg.h	978;"	d
+ADR_MTX_BCN_CFG0	include/ssv6200_reg.h	636;"	d
+ADR_MTX_BCN_CFG1	include/ssv6200_reg.h	637;"	d
+ADR_MTX_BCN_DTIM_CONFG	smac/hal/ssv6006c/ssv6006C_reg.h	768;"	d
+ADR_MTX_BCN_DTIM_INT_W1CLR	smac/hal/ssv6006c/ssv6006C_reg.h	769;"	d
+ADR_MTX_BCN_DTIM_SET0	smac/hal/ssv6006c/ssv6006C_reg.h	766;"	d
+ADR_MTX_BCN_DTIM_SET1	smac/hal/ssv6006c/ssv6006C_reg.h	767;"	d
+ADR_MTX_BCN_EN_INT	include/ssv6200_reg.h	630;"	d
+ADR_MTX_BCN_EN_INT	smac/hal/ssv6006c/ssv6006C_reg.h	771;"	d
+ADR_MTX_BCN_EN_MISC	include/ssv6200_reg.h	631;"	d
+ADR_MTX_BCN_EN_MISC	smac/hal/ssv6006c/ssv6006C_reg.h	772;"	d
+ADR_MTX_BCN_INT_STS	include/ssv6200_reg.h	629;"	d
+ADR_MTX_BCN_INT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	770;"	d
+ADR_MTX_BCN_MISC	include/ssv6200_reg.h	632;"	d
+ADR_MTX_BCN_MISC	smac/hal/ssv6006c/ssv6006C_reg.h	773;"	d
+ADR_MTX_BCN_PKT_SET0	smac/hal/ssv6006c/ssv6006C_reg.h	764;"	d
+ADR_MTX_BCN_PKT_SET1	smac/hal/ssv6006c/ssv6006C_reg.h	765;"	d
+ADR_MTX_BCN_PRD	include/ssv6200_reg.h	633;"	d
+ADR_MTX_BCN_PRD	smac/hal/ssv6006c/ssv6006C_reg.h	774;"	d
+ADR_MTX_BCN_TSF_L	include/ssv6200_reg.h	634;"	d
+ADR_MTX_BCN_TSF_L	smac/hal/ssv6006c/ssv6006C_reg.h	775;"	d
+ADR_MTX_BCN_TSF_U	include/ssv6200_reg.h	635;"	d
+ADR_MTX_BCN_TSF_U	smac/hal/ssv6006c/ssv6006C_reg.h	776;"	d
+ADR_MTX_CTS_TX	include/ssv6200_reg.h	803;"	d
+ADR_MTX_CTS_TX	smac/hal/ssv6006c/ssv6006C_reg.h	979;"	d
+ADR_MTX_DBGOPT_FORCE_RATE	smac/hal/ssv6006c/ssv6006C_reg.h	758;"	d
+ADR_MTX_DBGOPT_FORCE_RATE_ENABLE	smac/hal/ssv6006c/ssv6006C_reg.h	759;"	d
+ADR_MTX_DBG_CTRL	include/ssv6200_reg.h	639;"	d
+ADR_MTX_DBG_DAT0	include/ssv6200_reg.h	640;"	d
+ADR_MTX_DBG_DAT1	include/ssv6200_reg.h	641;"	d
+ADR_MTX_DBG_DAT2	include/ssv6200_reg.h	642;"	d
+ADR_MTX_DBG_DAT3	include/ssv6200_reg.h	646;"	d
+ADR_MTX_DBG_DAT4	include/ssv6200_reg.h	650;"	d
+ADR_MTX_DBG_IFSAIRRO0	smac/hal/ssv6006c/ssv6006C_reg.h	782;"	d
+ADR_MTX_DBG_IFSAIRRO1	smac/hal/ssv6006c/ssv6006C_reg.h	783;"	d
+ADR_MTX_DBG_IFSAIRRO2	smac/hal/ssv6006c/ssv6006C_reg.h	784;"	d
+ADR_MTX_DBG_IFSAIRRO3	smac/hal/ssv6006c/ssv6006C_reg.h	785;"	d
+ADR_MTX_DBG_MORE	smac/hal/ssv6006c/ssv6006C_reg.h	761;"	d
+ADR_MTX_DBG_PHYTXIPTIMEOUT	smac/hal/ssv6006c/ssv6006C_reg.h	760;"	d
+ADR_MTX_DBG_ROIFSAIR1	smac/hal/ssv6006c/ssv6006C_reg.h	762;"	d
+ADR_MTX_DBG_ROIFSAIR2	smac/hal/ssv6006c/ssv6006C_reg.h	763;"	d
+ADR_MTX_DBG_RO_BASE1	smac/hal/ssv6006c/ssv6006C_reg.h	787;"	d
+ADR_MTX_DBG_RO_BASE2	smac/hal/ssv6006c/ssv6006C_reg.h	788;"	d
+ADR_MTX_DBG_RO_BASE3	smac/hal/ssv6006c/ssv6006C_reg.h	789;"	d
+ADR_MTX_DUR_IFS	include/ssv6200_reg.h	644;"	d
+ADR_MTX_DUR_SIFS_G	include/ssv6200_reg.h	645;"	d
+ADR_MTX_DUR_TOUT	include/ssv6200_reg.h	643;"	d
+ADR_MTX_EDCCA_TOUT	include/ssv6200_reg.h	628;"	d
+ADR_MTX_FAIL	include/ssv6200_reg.h	795;"	d
+ADR_MTX_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	971;"	d
+ADR_MTX_FRM	include/ssv6200_reg.h	801;"	d
+ADR_MTX_FRM	smac/hal/ssv6006c/ssv6006C_reg.h	977;"	d
+ADR_MTX_GROUP	include/ssv6200_reg.h	794;"	d
+ADR_MTX_GROUP	smac/hal/ssv6006c/ssv6006C_reg.h	970;"	d
+ADR_MTX_HALT_OPTION	smac/hal/ssv6006c/ssv6006C_reg.h	743;"	d
+ADR_MTX_INT_EN	include/ssv6200_reg.h	626;"	d
+ADR_MTX_INT_EN	smac/hal/ssv6006c/ssv6006C_reg.h	738;"	d
+ADR_MTX_INT_STS	include/ssv6200_reg.h	625;"	d
+ADR_MTX_INT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	737;"	d
+ADR_MTX_MIB_WSID0	include/ssv6200_reg.h	648;"	d
+ADR_MTX_MIB_WSID0	smac/hal/ssv6006c/ssv6006C_reg.h	745;"	d
+ADR_MTX_MIB_WSID1	include/ssv6200_reg.h	649;"	d
+ADR_MTX_MIB_WSID1	smac/hal/ssv6006c/ssv6006C_reg.h	746;"	d
+ADR_MTX_MIB_WSID2	smac/hal/ssv6006c/ssv6006C_reg.h	747;"	d
+ADR_MTX_MIB_WSID3	smac/hal/ssv6006c/ssv6006C_reg.h	748;"	d
+ADR_MTX_MIB_WSID4	smac/hal/ssv6006c/ssv6006C_reg.h	749;"	d
+ADR_MTX_MIB_WSID5	smac/hal/ssv6006c/ssv6006C_reg.h	750;"	d
+ADR_MTX_MIB_WSID6	smac/hal/ssv6006c/ssv6006C_reg.h	751;"	d
+ADR_MTX_MIB_WSID7	smac/hal/ssv6006c/ssv6006C_reg.h	752;"	d
+ADR_MTX_MISC_EN	include/ssv6200_reg.h	627;"	d
+ADR_MTX_MISC_EN	smac/hal/ssv6006c/ssv6006C_reg.h	739;"	d
+ADR_MTX_MULTI_RETRY	include/ssv6200_reg.h	797;"	d
+ADR_MTX_MULTI_RETRY	smac/hal/ssv6006c/ssv6006C_reg.h	973;"	d
+ADR_MTX_NAV	include/ssv6200_reg.h	647;"	d
+ADR_MTX_NAV	smac/hal/ssv6006c/ssv6006C_reg.h	786;"	d
+ADR_MTX_PEER_LOCK_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	756;"	d
+ADR_MTX_PEER_PS_LOCK	smac/hal/ssv6006c/ssv6006C_reg.h	755;"	d
+ADR_MTX_PHYRXIFS_DBG	smac/hal/ssv6006c/ssv6006C_reg.h	781;"	d
+ADR_MTX_PHYTX_DBG1	smac/hal/ssv6006c/ssv6006C_reg.h	744;"	d
+ADR_MTX_RATERPT	smac/hal/ssv6006c/ssv6006C_reg.h	757;"	d
+ADR_MTX_RESPFRM_INFO_00	smac/hal/ssv6006c/ssv6006C_reg.h	861;"	d
+ADR_MTX_RESPFRM_INFO_01	smac/hal/ssv6006c/ssv6006C_reg.h	862;"	d
+ADR_MTX_RESPFRM_INFO_02	smac/hal/ssv6006c/ssv6006C_reg.h	863;"	d
+ADR_MTX_RESPFRM_INFO_03	smac/hal/ssv6006c/ssv6006C_reg.h	864;"	d
+ADR_MTX_RESPFRM_INFO_11	smac/hal/ssv6006c/ssv6006C_reg.h	865;"	d
+ADR_MTX_RESPFRM_INFO_12	smac/hal/ssv6006c/ssv6006C_reg.h	866;"	d
+ADR_MTX_RESPFRM_INFO_13	smac/hal/ssv6006c/ssv6006C_reg.h	867;"	d
+ADR_MTX_RESPFRM_INFO_90_B0	smac/hal/ssv6006c/ssv6006C_reg.h	868;"	d
+ADR_MTX_RESPFRM_INFO_91_B1	smac/hal/ssv6006c/ssv6006C_reg.h	869;"	d
+ADR_MTX_RESPFRM_INFO_92_B2	smac/hal/ssv6006c/ssv6006C_reg.h	870;"	d
+ADR_MTX_RESPFRM_INFO_93_B3	smac/hal/ssv6006c/ssv6006C_reg.h	871;"	d
+ADR_MTX_RESPFRM_INFO_94_B4	smac/hal/ssv6006c/ssv6006C_reg.h	872;"	d
+ADR_MTX_RESPFRM_INFO_95_B5	smac/hal/ssv6006c/ssv6006C_reg.h	873;"	d
+ADR_MTX_RESPFRM_INFO_96_B6	smac/hal/ssv6006c/ssv6006C_reg.h	874;"	d
+ADR_MTX_RESPFRM_INFO_97_B7	smac/hal/ssv6006c/ssv6006C_reg.h	875;"	d
+ADR_MTX_RESPFRM_INFO_C0	smac/hal/ssv6006c/ssv6006C_reg.h	876;"	d
+ADR_MTX_RESPFRM_INFO_C1	smac/hal/ssv6006c/ssv6006C_reg.h	877;"	d
+ADR_MTX_RESPFRM_INFO_C2	smac/hal/ssv6006c/ssv6006C_reg.h	878;"	d
+ADR_MTX_RESPFRM_INFO_C3	smac/hal/ssv6006c/ssv6006C_reg.h	879;"	d
+ADR_MTX_RESPFRM_INFO_C4	smac/hal/ssv6006c/ssv6006C_reg.h	880;"	d
+ADR_MTX_RESPFRM_INFO_C5	smac/hal/ssv6006c/ssv6006C_reg.h	881;"	d
+ADR_MTX_RESPFRM_INFO_C6	smac/hal/ssv6006c/ssv6006C_reg.h	882;"	d
+ADR_MTX_RESPFRM_INFO_C7	smac/hal/ssv6006c/ssv6006C_reg.h	883;"	d
+ADR_MTX_RESPFRM_INFO_D0	smac/hal/ssv6006c/ssv6006C_reg.h	884;"	d
+ADR_MTX_RESPFRM_INFO_D1	smac/hal/ssv6006c/ssv6006C_reg.h	885;"	d
+ADR_MTX_RESPFRM_INFO_D2	smac/hal/ssv6006c/ssv6006C_reg.h	886;"	d
+ADR_MTX_RESPFRM_INFO_D3	smac/hal/ssv6006c/ssv6006C_reg.h	887;"	d
+ADR_MTX_RESPFRM_INFO_D4	smac/hal/ssv6006c/ssv6006C_reg.h	888;"	d
+ADR_MTX_RESPFRM_INFO_D5	smac/hal/ssv6006c/ssv6006C_reg.h	889;"	d
+ADR_MTX_RESPFRM_INFO_D6	smac/hal/ssv6006c/ssv6006C_reg.h	890;"	d
+ADR_MTX_RESPFRM_INFO_D7	smac/hal/ssv6006c/ssv6006C_reg.h	891;"	d
+ADR_MTX_RESPFRM_INFO_D8	smac/hal/ssv6006c/ssv6006C_reg.h	892;"	d
+ADR_MTX_RESPFRM_INFO_D9	smac/hal/ssv6006c/ssv6006C_reg.h	893;"	d
+ADR_MTX_RESPFRM_INFO_DA	smac/hal/ssv6006c/ssv6006C_reg.h	894;"	d
+ADR_MTX_RESPFRM_INFO_DB	smac/hal/ssv6006c/ssv6006C_reg.h	895;"	d
+ADR_MTX_RESPFRM_INFO_DC	smac/hal/ssv6006c/ssv6006C_reg.h	896;"	d
+ADR_MTX_RESPFRM_INFO_DD	smac/hal/ssv6006c/ssv6006C_reg.h	897;"	d
+ADR_MTX_RESPFRM_INFO_DE	smac/hal/ssv6006c/ssv6006C_reg.h	898;"	d
+ADR_MTX_RESPFRM_INFO_DF	smac/hal/ssv6006c/ssv6006C_reg.h	899;"	d
+ADR_MTX_RESPFRM_INFO_TABLE_EXCEPTION	smac/hal/ssv6006c/ssv6006C_reg.h	860;"	d
+ADR_MTX_RESPFRM_RATE_TABLE_00	smac/hal/ssv6006c/ssv6006C_reg.h	821;"	d
+ADR_MTX_RESPFRM_RATE_TABLE_01	smac/hal/ssv6006c/ssv6006C_reg.h	822;"	d
+ADR_MTX_RESPFRM_RATE_TABLE_02	smac/hal/ssv6006c/ssv6006C_reg.h	823;"	d
+ADR_MTX_RESPFRM_RATE_TABLE_03	smac/hal/ssv6006c/ssv6006C_reg.h	824;"	d
+ADR_MTX_RESPFRM_RATE_TABLE_11	smac/hal/ssv6006c/ssv6006C_reg.h	825;"	d
+ADR_MTX_RESPFRM_RATE_TABLE_12	smac/hal/ssv6006c/ssv6006C_reg.h	826;"	d
+ADR_MTX_RESPFRM_RATE_TABLE_13	smac/hal/ssv6006c/ssv6006C_reg.h	827;"	d
+ADR_MTX_RESPFRM_RATE_TABLE_90_B0	smac/hal/ssv6006c/ssv6006C_reg.h	828;"	d
+ADR_MTX_RESPFRM_RATE_TABLE_91_B1	smac/hal/ssv6006c/ssv6006C_reg.h	829;"	d
+ADR_MTX_RESPFRM_RATE_TABLE_92_B2	smac/hal/ssv6006c/ssv6006C_reg.h	830;"	d
+ADR_MTX_RESPFRM_RATE_TABLE_93_B3	smac/hal/ssv6006c/ssv6006C_reg.h	831;"	d
+ADR_MTX_RESPFRM_RATE_TABLE_94_B4	smac/hal/ssv6006c/ssv6006C_reg.h	832;"	d
+ADR_MTX_RESPFRM_RATE_TABLE_95_B5	smac/hal/ssv6006c/ssv6006C_reg.h	833;"	d
+ADR_MTX_RESPFRM_RATE_TABLE_96_B6	smac/hal/ssv6006c/ssv6006C_reg.h	834;"	d
+ADR_MTX_RESPFRM_RATE_TABLE_97_B7	smac/hal/ssv6006c/ssv6006C_reg.h	835;"	d
+ADR_MTX_RESPFRM_RATE_TABLE_C0_E0	smac/hal/ssv6006c/ssv6006C_reg.h	836;"	d
+ADR_MTX_RESPFRM_RATE_TABLE_C1_E1	smac/hal/ssv6006c/ssv6006C_reg.h	837;"	d
+ADR_MTX_RESPFRM_RATE_TABLE_C2_E2	smac/hal/ssv6006c/ssv6006C_reg.h	838;"	d
+ADR_MTX_RESPFRM_RATE_TABLE_C3_E3	smac/hal/ssv6006c/ssv6006C_reg.h	839;"	d
+ADR_MTX_RESPFRM_RATE_TABLE_C4_E4	smac/hal/ssv6006c/ssv6006C_reg.h	840;"	d
+ADR_MTX_RESPFRM_RATE_TABLE_C5_E5	smac/hal/ssv6006c/ssv6006C_reg.h	841;"	d
+ADR_MTX_RESPFRM_RATE_TABLE_C6_E6	smac/hal/ssv6006c/ssv6006C_reg.h	842;"	d
+ADR_MTX_RESPFRM_RATE_TABLE_C7_E7	smac/hal/ssv6006c/ssv6006C_reg.h	843;"	d
+ADR_MTX_RESPFRM_RATE_TABLE_D0_F0	smac/hal/ssv6006c/ssv6006C_reg.h	844;"	d
+ADR_MTX_RESPFRM_RATE_TABLE_D1_F1	smac/hal/ssv6006c/ssv6006C_reg.h	845;"	d
+ADR_MTX_RESPFRM_RATE_TABLE_D2_F2	smac/hal/ssv6006c/ssv6006C_reg.h	846;"	d
+ADR_MTX_RESPFRM_RATE_TABLE_D3_F3	smac/hal/ssv6006c/ssv6006C_reg.h	847;"	d
+ADR_MTX_RESPFRM_RATE_TABLE_D4_F4	smac/hal/ssv6006c/ssv6006C_reg.h	848;"	d
+ADR_MTX_RESPFRM_RATE_TABLE_D5_F5	smac/hal/ssv6006c/ssv6006C_reg.h	849;"	d
+ADR_MTX_RESPFRM_RATE_TABLE_D6_F6	smac/hal/ssv6006c/ssv6006C_reg.h	850;"	d
+ADR_MTX_RESPFRM_RATE_TABLE_D7_F7	smac/hal/ssv6006c/ssv6006C_reg.h	851;"	d
+ADR_MTX_RESPFRM_RATE_TABLE_D8_F8	smac/hal/ssv6006c/ssv6006C_reg.h	852;"	d
+ADR_MTX_RESPFRM_RATE_TABLE_D9_F9	smac/hal/ssv6006c/ssv6006C_reg.h	853;"	d
+ADR_MTX_RESPFRM_RATE_TABLE_DA_FA	smac/hal/ssv6006c/ssv6006C_reg.h	854;"	d
+ADR_MTX_RESPFRM_RATE_TABLE_DB_FB	smac/hal/ssv6006c/ssv6006C_reg.h	855;"	d
+ADR_MTX_RESPFRM_RATE_TABLE_DC_FC	smac/hal/ssv6006c/ssv6006C_reg.h	856;"	d
+ADR_MTX_RESPFRM_RATE_TABLE_DD_FD	smac/hal/ssv6006c/ssv6006C_reg.h	857;"	d
+ADR_MTX_RESPFRM_RATE_TABLE_DE_FE	smac/hal/ssv6006c/ssv6006C_reg.h	858;"	d
+ADR_MTX_RESPFRM_RATE_TABLE_DF_FF	smac/hal/ssv6006c/ssv6006C_reg.h	859;"	d
+ADR_MTX_RESPFRM_RATE_TABLE_EXCEPTION	smac/hal/ssv6006c/ssv6006C_reg.h	820;"	d
+ADR_MTX_RETRY	include/ssv6200_reg.h	796;"	d
+ADR_MTX_RETRY	smac/hal/ssv6006c/ssv6006C_reg.h	972;"	d
+ADR_MTX_RTS_FAIL	include/ssv6200_reg.h	799;"	d
+ADR_MTX_RTS_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	975;"	d
+ADR_MTX_RTS_SUCCESS	include/ssv6200_reg.h	798;"	d
+ADR_MTX_RTS_SUCCESS	smac/hal/ssv6006c/ssv6006C_reg.h	974;"	d
+ADR_MTX_STATUS	include/ssv6200_reg.h	638;"	d
+ADR_MTX_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	780;"	d
+ADR_MTX_STATUS0	smac/hal/ssv6006c/ssv6006C_reg.h	741;"	d
+ADR_MTX_STATUS4	smac/hal/ssv6006c/ssv6006C_reg.h	742;"	d
+ADR_MTX_TIME_FINETUNE	smac/hal/ssv6006c/ssv6006C_reg.h	779;"	d
+ADR_MTX_TIME_IFS	smac/hal/ssv6006c/ssv6006C_reg.h	778;"	d
+ADR_MTX_TIME_TOUT	smac/hal/ssv6006c/ssv6006C_reg.h	777;"	d
+ADR_MTX_TX_REPORT_OPTION	smac/hal/ssv6006c/ssv6006C_reg.h	740;"	d
+ADR_MTX_WSID0_FRM	include/ssv6200_reg.h	791;"	d
+ADR_MTX_WSID0_FRM	smac/hal/ssv6006c/ssv6006C_reg.h	967;"	d
+ADR_MTX_WSID0_RETRY	include/ssv6200_reg.h	792;"	d
+ADR_MTX_WSID0_RETRY	smac/hal/ssv6006c/ssv6006C_reg.h	968;"	d
+ADR_MTX_WSID0_SUCC	include/ssv6200_reg.h	790;"	d
+ADR_MTX_WSID0_SUCC	smac/hal/ssv6006c/ssv6006C_reg.h	966;"	d
+ADR_MTX_WSID0_TOTAL	include/ssv6200_reg.h	793;"	d
+ADR_MTX_WSID0_TOTAL	smac/hal/ssv6006c/ssv6006C_reg.h	969;"	d
+ADR_MUL_ANS0	include/ssv6200_reg.h	459;"	d
+ADR_MUL_ANS0	smac/hal/ssv6006c/ssv6006C_reg.h	618;"	d
+ADR_MUL_ANS1	include/ssv6200_reg.h	460;"	d
+ADR_MUL_ANS1	smac/hal/ssv6006c/ssv6006C_reg.h	619;"	d
+ADR_MUL_OP1	include/ssv6200_reg.h	457;"	d
+ADR_MUL_OP1	smac/hal/ssv6006c/ssv6006C_reg.h	616;"	d
+ADR_MUL_OP2	include/ssv6200_reg.h	458;"	d
+ADR_MUL_OP2	smac/hal/ssv6006c/ssv6006C_reg.h	617;"	d
+ADR_N10CFG_DEF_IVB	smac/hal/ssv6006c/ssv6006C_reg.h	278;"	d
+ADR_N10CFG_SETTING	smac/hal/ssv6006c/ssv6006C_reg.h	279;"	d
+ADR_N10_DBG1	smac/hal/ssv6006c/ssv6006C_reg.h	246;"	d
+ADR_N10_DBG2	smac/hal/ssv6006c/ssv6006C_reg.h	247;"	d
+ADR_NAV_DATA	include/ssv6200_reg.h	465;"	d
+ADR_NAV_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	624;"	d
+ADR_OP_MODE1	smac/hal/ssv6006c/ssv6006C_reg.h	959;"	d
+ADR_PACKET_COUNTER_INFO_0	include/ssv6200_reg.h	428;"	d
+ADR_PACKET_COUNTER_INFO_1	include/ssv6200_reg.h	429;"	d
+ADR_PACKET_COUNTER_INFO_2	include/ssv6200_reg.h	430;"	d
+ADR_PACKET_COUNTER_INFO_3	include/ssv6200_reg.h	431;"	d
+ADR_PACKET_COUNTER_INFO_4	include/ssv6200_reg.h	432;"	d
+ADR_PACKET_COUNTER_INFO_5	include/ssv6200_reg.h	433;"	d
+ADR_PACKET_COUNTER_INFO_6	include/ssv6200_reg.h	434;"	d
+ADR_PACKET_COUNTER_INFO_7	include/ssv6200_reg.h	435;"	d
+ADR_PACKET_ID_ALLOCATION_PRIORITY	include/ssv6200_reg.h	769;"	d
+ADR_PACKET_ID_ALLOCATION_PRIORITY	smac/hal/ssv6006c/ssv6006C_reg.h	938;"	d
+ADR_PAD11	include/ssv6200_reg.h	187;"	d
+ADR_PAD15	include/ssv6200_reg.h	188;"	d
+ADR_PAD16	include/ssv6200_reg.h	189;"	d
+ADR_PAD17	include/ssv6200_reg.h	190;"	d
+ADR_PAD18	include/ssv6200_reg.h	191;"	d
+ADR_PAD19	include/ssv6200_reg.h	192;"	d
+ADR_PAD20	include/ssv6200_reg.h	193;"	d
+ADR_PAD21	include/ssv6200_reg.h	194;"	d
+ADR_PAD22	include/ssv6200_reg.h	195;"	d
+ADR_PAD231	include/ssv6200_reg.h	233;"	d
+ADR_PAD24	include/ssv6200_reg.h	196;"	d
+ADR_PAD25	include/ssv6200_reg.h	197;"	d
+ADR_PAD27	include/ssv6200_reg.h	198;"	d
+ADR_PAD28	include/ssv6200_reg.h	199;"	d
+ADR_PAD29	include/ssv6200_reg.h	200;"	d
+ADR_PAD30	include/ssv6200_reg.h	201;"	d
+ADR_PAD31	include/ssv6200_reg.h	202;"	d
+ADR_PAD32	include/ssv6200_reg.h	203;"	d
+ADR_PAD33	include/ssv6200_reg.h	204;"	d
+ADR_PAD34	include/ssv6200_reg.h	205;"	d
+ADR_PAD42	include/ssv6200_reg.h	206;"	d
+ADR_PAD43	include/ssv6200_reg.h	207;"	d
+ADR_PAD44	include/ssv6200_reg.h	208;"	d
+ADR_PAD45	include/ssv6200_reg.h	209;"	d
+ADR_PAD46	include/ssv6200_reg.h	210;"	d
+ADR_PAD47	include/ssv6200_reg.h	211;"	d
+ADR_PAD48	include/ssv6200_reg.h	212;"	d
+ADR_PAD49	include/ssv6200_reg.h	213;"	d
+ADR_PAD50	include/ssv6200_reg.h	214;"	d
+ADR_PAD51	include/ssv6200_reg.h	215;"	d
+ADR_PAD52	include/ssv6200_reg.h	216;"	d
+ADR_PAD53	include/ssv6200_reg.h	217;"	d
+ADR_PAD54	include/ssv6200_reg.h	218;"	d
+ADR_PAD56	include/ssv6200_reg.h	219;"	d
+ADR_PAD57	include/ssv6200_reg.h	220;"	d
+ADR_PAD58	include/ssv6200_reg.h	221;"	d
+ADR_PAD59	include/ssv6200_reg.h	222;"	d
+ADR_PAD6	include/ssv6200_reg.h	183;"	d
+ADR_PAD60	include/ssv6200_reg.h	223;"	d
+ADR_PAD61	include/ssv6200_reg.h	224;"	d
+ADR_PAD62	include/ssv6200_reg.h	225;"	d
+ADR_PAD64	include/ssv6200_reg.h	226;"	d
+ADR_PAD65	include/ssv6200_reg.h	227;"	d
+ADR_PAD66	include/ssv6200_reg.h	228;"	d
+ADR_PAD67	include/ssv6200_reg.h	230;"	d
+ADR_PAD68	include/ssv6200_reg.h	229;"	d
+ADR_PAD69	include/ssv6200_reg.h	231;"	d
+ADR_PAD7	include/ssv6200_reg.h	184;"	d
+ADR_PAD70	include/ssv6200_reg.h	232;"	d
+ADR_PAD8	include/ssv6200_reg.h	185;"	d
+ADR_PAD9	include/ssv6200_reg.h	186;"	d
+ADR_PAGE_TAG_STATUS_0	smac/hal/ssv6006c/ssv6006C_reg.h	2146;"	d
+ADR_PAGE_TAG_STATUS_1	smac/hal/ssv6006c/ssv6006C_reg.h	2147;"	d
+ADR_PAGE_TAG_STATUS_2	smac/hal/ssv6006c/ssv6006C_reg.h	2148;"	d
+ADR_PAGE_TAG_STATUS_3	smac/hal/ssv6006c/ssv6006C_reg.h	2149;"	d
+ADR_PAGE_TAG_STATUS_4	smac/hal/ssv6006c/ssv6006C_reg.h	2150;"	d
+ADR_PAGE_TAG_STATUS_5	smac/hal/ssv6006c/ssv6006C_reg.h	2151;"	d
+ADR_PAGE_TAG_STATUS_6	smac/hal/ssv6006c/ssv6006C_reg.h	2152;"	d
+ADR_PAGE_TAG_STATUS_7	smac/hal/ssv6006c/ssv6006C_reg.h	2153;"	d
+ADR_PEER_MAC0_0	include/ssv6200_reg.h	687;"	d
+ADR_PEER_MAC0_0	smac/hal/ssv6006c/ssv6006C_reg.h	901;"	d
+ADR_PEER_MAC0_1	include/ssv6200_reg.h	688;"	d
+ADR_PEER_MAC0_1	smac/hal/ssv6006c/ssv6006C_reg.h	902;"	d
+ADR_PEER_MAC1_0	include/ssv6200_reg.h	706;"	d
+ADR_PEER_MAC1_0	smac/hal/ssv6006c/ssv6006C_reg.h	920;"	d
+ADR_PEER_MAC1_1	include/ssv6200_reg.h	707;"	d
+ADR_PEER_MAC1_1	smac/hal/ssv6006c/ssv6006C_reg.h	921;"	d
+ADR_PEER_MAC2_0	smac/hal/ssv6006c/ssv6006C_reg.h	1027;"	d
+ADR_PEER_MAC2_1	smac/hal/ssv6006c/ssv6006C_reg.h	1028;"	d
+ADR_PEER_MAC3_0	smac/hal/ssv6006c/ssv6006C_reg.h	1046;"	d
+ADR_PEER_MAC3_1	smac/hal/ssv6006c/ssv6006C_reg.h	1047;"	d
+ADR_PEER_MAC4_0	smac/hal/ssv6006c/ssv6006C_reg.h	1065;"	d
+ADR_PEER_MAC4_1	smac/hal/ssv6006c/ssv6006C_reg.h	1066;"	d
+ADR_PEER_MAC5_0	smac/hal/ssv6006c/ssv6006C_reg.h	1084;"	d
+ADR_PEER_MAC5_1	smac/hal/ssv6006c/ssv6006C_reg.h	1085;"	d
+ADR_PEER_MAC6_0	smac/hal/ssv6006c/ssv6006C_reg.h	1103;"	d
+ADR_PEER_MAC6_1	smac/hal/ssv6006c/ssv6006C_reg.h	1104;"	d
+ADR_PEER_MAC7_0	smac/hal/ssv6006c/ssv6006C_reg.h	1122;"	d
+ADR_PEER_MAC7_1	smac/hal/ssv6006c/ssv6006C_reg.h	1123;"	d
+ADR_PHY_EN_0	include/ssv6200_reg.h	963;"	d
+ADR_PHY_EN_1	include/ssv6200_reg.h	964;"	d
+ADR_PHY_INFO	include/ssv6200_reg.h	620;"	d
+ADR_PHY_INFO	smac/hal/ssv6006c/ssv6006C_reg.h	732;"	d
+ADR_PHY_IQ_LOG_CFG0	include/ssv6200_reg.h	925;"	d
+ADR_PHY_IQ_LOG_CFG0	smac/hal/ssv6006c/ssv6006C_reg.h	2103;"	d
+ADR_PHY_IQ_LOG_CFG1	include/ssv6200_reg.h	926;"	d
+ADR_PHY_IQ_LOG_CFG1	smac/hal/ssv6006c/ssv6006C_reg.h	2104;"	d
+ADR_PHY_IQ_LOG_LEN	include/ssv6200_reg.h	927;"	d
+ADR_PHY_IQ_LOG_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	2105;"	d
+ADR_PHY_IQ_LOG_PTR	include/ssv6200_reg.h	928;"	d
+ADR_PHY_IQ_LOG_PTR	smac/hal/ssv6006c/ssv6006C_reg.h	2106;"	d
+ADR_PHY_PKT_GEN_0	include/ssv6200_reg.h	966;"	d
+ADR_PHY_PKT_GEN_1	include/ssv6200_reg.h	967;"	d
+ADR_PHY_PKT_GEN_2	include/ssv6200_reg.h	968;"	d
+ADR_PHY_PKT_GEN_3	include/ssv6200_reg.h	969;"	d
+ADR_PHY_PKT_GEN_4	include/ssv6200_reg.h	970;"	d
+ADR_PHY_READ_REG_00_DIG_PWR	include/ssv6200_reg.h	981;"	d
+ADR_PHY_READ_REG_01_RF_GAIN_PWR	include/ssv6200_reg.h	982;"	d
+ADR_PHY_READ_REG_02_RF_GAIN_PWR	include/ssv6200_reg.h	983;"	d
+ADR_PHY_READ_REG_03_RF_GAIN_PWR	include/ssv6200_reg.h	984;"	d
+ADR_PHY_READ_REG_04	include/ssv6200_reg.h	1003;"	d
+ADR_PHY_READ_REG_05	include/ssv6200_reg.h	1004;"	d
+ADR_PHY_READ_REG_06_BIST	include/ssv6200_reg.h	1006;"	d
+ADR_PHY_READ_REG_07_BIST	include/ssv6200_reg.h	1007;"	d
+ADR_PHY_READ_REG_08_MTRX_MAC	include/ssv6200_reg.h	1009;"	d
+ADR_PHY_READ_REG_09_MTRX_MAC	include/ssv6200_reg.h	1010;"	d
+ADR_PHY_READ_TBUS	include/ssv6200_reg.h	1014;"	d
+ADR_PHY_REG_00	include/ssv6200_reg.h	971;"	d
+ADR_PHY_REG_01	include/ssv6200_reg.h	972;"	d
+ADR_PHY_REG_02_AGC	include/ssv6200_reg.h	973;"	d
+ADR_PHY_REG_03_AGC	include/ssv6200_reg.h	974;"	d
+ADR_PHY_REG_04_AGC	include/ssv6200_reg.h	975;"	d
+ADR_PHY_REG_05_AGC	include/ssv6200_reg.h	976;"	d
+ADR_PHY_REG_06_11B_DAGC	include/ssv6200_reg.h	977;"	d
+ADR_PHY_REG_07_11B_DAGC	include/ssv6200_reg.h	978;"	d
+ADR_PHY_REG_08_11GN_DAGC	include/ssv6200_reg.h	979;"	d
+ADR_PHY_REG_09_11GN_DAGC	include/ssv6200_reg.h	980;"	d
+ADR_PHY_REG_10_TX_DES	include/ssv6200_reg.h	985;"	d
+ADR_PHY_REG_11_TX_DES	include/ssv6200_reg.h	986;"	d
+ADR_PHY_REG_12_TX_DES	include/ssv6200_reg.h	987;"	d
+ADR_PHY_REG_13_RX_DES	include/ssv6200_reg.h	988;"	d
+ADR_PHY_REG_14_RX_DES	include/ssv6200_reg.h	989;"	d
+ADR_PHY_REG_15_RX_DES	include/ssv6200_reg.h	990;"	d
+ADR_PHY_REG_16_TX_DES_EXCP	include/ssv6200_reg.h	991;"	d
+ADR_PHY_REG_17_TX_DES_EXCP	include/ssv6200_reg.h	992;"	d
+ADR_PHY_REG_18_RSSI_SNR	include/ssv6200_reg.h	993;"	d
+ADR_PHY_REG_19_DAC_MANUAL	include/ssv6200_reg.h	994;"	d
+ADR_PHY_REG_20_MRX_CNT	include/ssv6200_reg.h	995;"	d
+ADR_PHY_REG_21_TRX_RAMP	include/ssv6200_reg.h	996;"	d
+ADR_PHY_REG_22_TRX_RAMP	include/ssv6200_reg.h	997;"	d
+ADR_PHY_REG_23_ANT	include/ssv6200_reg.h	998;"	d
+ADR_PHY_REG_24_MTX_LEN_CNT	include/ssv6200_reg.h	999;"	d
+ADR_PHY_REG_25_MTX_LEN_CNT	include/ssv6200_reg.h	1000;"	d
+ADR_PHY_REG_26_MRX_LEN_CNT	include/ssv6200_reg.h	1001;"	d
+ADR_PHY_REG_27_MRX_LEN_CNT	include/ssv6200_reg.h	1002;"	d
+ADR_PHY_REG_28_BIST	include/ssv6200_reg.h	1005;"	d
+ADR_PHY_REG_29_MTRX_MAC	include/ssv6200_reg.h	1008;"	d
+ADR_PHY_REG_30_TX_UP_FIL	include/ssv6200_reg.h	1011;"	d
+ADR_PHY_REG_31_TX_UP_FIL	include/ssv6200_reg.h	1012;"	d
+ADR_PHY_REG_32_TX_UP_FIL	include/ssv6200_reg.h	1013;"	d
+ADR_PIN_SEL_0	include/ssv6200_reg.h	234;"	d
+ADR_PIN_SEL_1	include/ssv6200_reg.h	235;"	d
+ADR_PKT_IDTBL_0_STATUS	include/ssv6200_reg.h	1241;"	d
+ADR_PKT_IDTBL_1_STATUS	include/ssv6200_reg.h	1242;"	d
+ADR_PKT_IDTBL_2_STATUS	include/ssv6200_reg.h	1243;"	d
+ADR_PKT_IDTBL_3_STATUS	include/ssv6200_reg.h	1244;"	d
+ADR_PKT_NEQID_0_STATUS	include/ssv6200_reg.h	1253;"	d
+ADR_PKT_NEQID_1_STATUS	include/ssv6200_reg.h	1254;"	d
+ADR_PKT_NEQID_2_STATUS	include/ssv6200_reg.h	1255;"	d
+ADR_PKT_NEQID_3_STATUS	include/ssv6200_reg.h	1256;"	d
+ADR_PLATFORM_CLOCK_ENABLE	include/ssv6200_reg.h	121;"	d
+ADR_PLATFORM_CLOCK_ENABLE	smac/hal/ssv6006c/ssv6006C_reg.h	243;"	d
+ADR_PMU_0	include/ssv6200_reg.h	400;"	d
+ADR_PMU_1	include/ssv6200_reg.h	401;"	d
+ADR_PMU_2	include/ssv6200_reg.h	402;"	d
+ADR_PMU_3	include/ssv6200_reg.h	403;"	d
+ADR_PMU_CTRL_REG	smac/hal/ssv6006c/ssv6006C_reg.h	1858;"	d
+ADR_PMU_DPLL_REG_0	smac/hal/ssv6006c/ssv6006C_reg.h	1860;"	d
+ADR_PMU_DPLL_REG_1	smac/hal/ssv6006c/ssv6006C_reg.h	1861;"	d
+ADR_PMU_DPLL_REG_2	smac/hal/ssv6006c/ssv6006C_reg.h	1862;"	d
+ADR_PMU_DPLL_REG_3	smac/hal/ssv6006c/ssv6006C_reg.h	1863;"	d
+ADR_PMU_MODE_TRAN_INT	smac/hal/ssv6006c/ssv6006C_reg.h	282;"	d
+ADR_PMU_RAM_00	smac/hal/ssv6006c/ssv6006C_reg.h	1865;"	d
+ADR_PMU_RAM_01	smac/hal/ssv6006c/ssv6006C_reg.h	1866;"	d
+ADR_PMU_RAM_02	smac/hal/ssv6006c/ssv6006C_reg.h	1867;"	d
+ADR_PMU_RAM_03	smac/hal/ssv6006c/ssv6006C_reg.h	1868;"	d
+ADR_PMU_RAM_04	smac/hal/ssv6006c/ssv6006C_reg.h	1869;"	d
+ADR_PMU_RAM_05	smac/hal/ssv6006c/ssv6006C_reg.h	1870;"	d
+ADR_PMU_RAM_06	smac/hal/ssv6006c/ssv6006C_reg.h	1871;"	d
+ADR_PMU_RAM_07	smac/hal/ssv6006c/ssv6006C_reg.h	1872;"	d
+ADR_PMU_RAM_08	smac/hal/ssv6006c/ssv6006C_reg.h	1873;"	d
+ADR_PMU_RAM_09	smac/hal/ssv6006c/ssv6006C_reg.h	1874;"	d
+ADR_PMU_RAM_10	smac/hal/ssv6006c/ssv6006C_reg.h	1875;"	d
+ADR_PMU_RAM_11	smac/hal/ssv6006c/ssv6006C_reg.h	1876;"	d
+ADR_PMU_RAM_12	smac/hal/ssv6006c/ssv6006C_reg.h	1877;"	d
+ADR_PMU_RAM_13	smac/hal/ssv6006c/ssv6006C_reg.h	1878;"	d
+ADR_PMU_RAM_14	smac/hal/ssv6006c/ssv6006C_reg.h	1879;"	d
+ADR_PMU_RAM_15	smac/hal/ssv6006c/ssv6006C_reg.h	1880;"	d
+ADR_PMU_REG_1	smac/hal/ssv6006c/ssv6006C_reg.h	1846;"	d
+ADR_PMU_REG_2	smac/hal/ssv6006c/ssv6006C_reg.h	1847;"	d
+ADR_PMU_REG_3	smac/hal/ssv6006c/ssv6006C_reg.h	1848;"	d
+ADR_PMU_REG_4	smac/hal/ssv6006c/ssv6006C_reg.h	1849;"	d
+ADR_PMU_REG_5	smac/hal/ssv6006c/ssv6006C_reg.h	1850;"	d
+ADR_PMU_REG_6	smac/hal/ssv6006c/ssv6006C_reg.h	1851;"	d
+ADR_PMU_RTC_REG_0	smac/hal/ssv6006c/ssv6006C_reg.h	1854;"	d
+ADR_PMU_RTC_REG_1	smac/hal/ssv6006c/ssv6006C_reg.h	1855;"	d
+ADR_PMU_RTC_REG_2	smac/hal/ssv6006c/ssv6006C_reg.h	1856;"	d
+ADR_PMU_RTC_REG_3	smac/hal/ssv6006c/ssv6006C_reg.h	1857;"	d
+ADR_PMU_SLEEP_MODE_REG	smac/hal/ssv6006c/ssv6006C_reg.h	1864;"	d
+ADR_PMU_SLEEP_REG_1	smac/hal/ssv6006c/ssv6006C_reg.h	1852;"	d
+ADR_PMU_SLEEP_REG_2	smac/hal/ssv6006c/ssv6006C_reg.h	1853;"	d
+ADR_PMU_STATE_REG	smac/hal/ssv6006c/ssv6006C_reg.h	1859;"	d
+ADR_POSTMASK_TYPHOST_INT_MAP	smac/hal/ssv6006c/ssv6006C_reg.h	500;"	d
+ADR_POSTMASK_TYPHOST_INT_MAP_02	smac/hal/ssv6006c/ssv6006C_reg.h	491;"	d
+ADR_POSTMASK_TYPHOST_INT_MAP_15	smac/hal/ssv6006c/ssv6006C_reg.h	494;"	d
+ADR_POSTMASK_TYPHOST_INT_MAP_31	smac/hal/ssv6006c/ssv6006C_reg.h	497;"	d
+ADR_POSTMASK_TYPMCU_INT_MAP	smac/hal/ssv6006c/ssv6006C_reg.h	513;"	d
+ADR_POSTMASK_TYPMCU_INT_MAP_02	smac/hal/ssv6006c/ssv6006C_reg.h	504;"	d
+ADR_POSTMASK_TYPMCU_INT_MAP_15	smac/hal/ssv6006c/ssv6006C_reg.h	507;"	d
+ADR_POSTMASK_TYPMCU_INT_MAP_31	smac/hal/ssv6006c/ssv6006C_reg.h	510;"	d
+ADR_POWER_ON_OFF_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	288;"	d
+ADR_POWER_SAVING_PEER_REJECT_FUNCTION	smac/hal/ssv6006c/ssv6006C_reg.h	603;"	d
+ADR_POWER_SW_INFO	smac/hal/ssv6006c/ssv6006C_reg.h	262;"	d
+ADR_PRESCALER_USTIMER	include/ssv6200_reg.h	141;"	d
+ADR_PRESCALER_USTIMER	smac/hal/ssv6006c/ssv6006C_reg.h	290;"	d
+ADR_PWM_0_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	325;"	d
+ADR_PWM_0_SET	smac/hal/ssv6006c/ssv6006C_reg.h	326;"	d
+ADR_PWM_1_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	327;"	d
+ADR_PWM_1_SET	smac/hal/ssv6006c/ssv6006C_reg.h	328;"	d
+ADR_PWM_2_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	329;"	d
+ADR_PWM_2_SET	smac/hal/ssv6006c/ssv6006C_reg.h	330;"	d
+ADR_PWM_3_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	331;"	d
+ADR_PWM_3_SET	smac/hal/ssv6006c/ssv6006C_reg.h	332;"	d
+ADR_PWM_4_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	333;"	d
+ADR_PWM_4_SET	smac/hal/ssv6006c/ssv6006C_reg.h	334;"	d
+ADR_PWM_A	include/ssv6200_reg.h	137;"	d
+ADR_PWM_B	include/ssv6200_reg.h	138;"	d
+ADR_R5_RESP_FLAG_OUT_TIMING	include/ssv6200_reg.h	254;"	d
+ADR_R5_RESP_FLAG_OUT_TIMING	smac/hal/ssv6006c/ssv6006C_reg.h	363;"	d
+ADR_RANDOM_CTL	smac/hal/ssv6006c/ssv6006C_reg.h	963;"	d
+ADR_RAND_EN	include/ssv6200_reg.h	455;"	d
+ADR_RAND_EN	smac/hal/ssv6006c/ssv6006C_reg.h	614;"	d
+ADR_RAND_NUM	include/ssv6200_reg.h	456;"	d
+ADR_RAND_NUM	smac/hal/ssv6006c/ssv6006C_reg.h	615;"	d
+ADR_RAW_TYPHOST_INT_MAP	smac/hal/ssv6006c/ssv6006C_reg.h	499;"	d
+ADR_RAW_TYPHOST_INT_MAP_02	smac/hal/ssv6006c/ssv6006C_reg.h	490;"	d
+ADR_RAW_TYPHOST_INT_MAP_15	smac/hal/ssv6006c/ssv6006C_reg.h	493;"	d
+ADR_RAW_TYPHOST_INT_MAP_31	smac/hal/ssv6006c/ssv6006C_reg.h	496;"	d
+ADR_RAW_TYPMCU_INT_MAP	smac/hal/ssv6006c/ssv6006C_reg.h	512;"	d
+ADR_RAW_TYPMCU_INT_MAP_02	smac/hal/ssv6006c/ssv6006C_reg.h	503;"	d
+ADR_RAW_TYPMCU_INT_MAP_15	smac/hal/ssv6006c/ssv6006C_reg.h	506;"	d
+ADR_RAW_TYPMCU_INT_MAP_31	smac/hal/ssv6006c/ssv6006C_reg.h	509;"	d
+ADR_RCAL_REGISTER	include/ssv6200_reg.h	1213;"	d
+ADR_RC_OSC_32K_CAL_REGISTERS	include/ssv6200_reg.h	1222;"	d
+ADR_RD_FFIN_FULL	include/ssv6200_reg.h	904;"	d
+ADR_RD_FFIN_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	2077;"	d
+ADR_RD_FFOUT_CNT1	include/ssv6200_reg.h	912;"	d
+ADR_RD_FFOUT_CNT1	smac/hal/ssv6006c/ssv6006C_reg.h	2089;"	d
+ADR_RD_FFOUT_CNT2	include/ssv6200_reg.h	913;"	d
+ADR_RD_FFOUT_CNT2	smac/hal/ssv6006c/ssv6006C_reg.h	2090;"	d
+ADR_RD_FFOUT_CNT3	include/ssv6200_reg.h	914;"	d
+ADR_RD_FFOUT_CNT3	smac/hal/ssv6006c/ssv6006C_reg.h	2091;"	d
+ADR_RD_FFOUT_FULL	include/ssv6200_reg.h	915;"	d
+ADR_RD_FFOUT_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	2092;"	d
+ADR_RD_ID0	include/ssv6200_reg.h	932;"	d
+ADR_RD_ID0	smac/hal/ssv6006c/ssv6006C_reg.h	2110;"	d
+ADR_RD_ID1	include/ssv6200_reg.h	933;"	d
+ADR_RD_ID1	smac/hal/ssv6006c/ssv6006C_reg.h	2111;"	d
+ADR_RD_ID2	include/ssv6200_reg.h	951;"	d
+ADR_RD_ID2	smac/hal/ssv6006c/ssv6006C_reg.h	2129;"	d
+ADR_RD_ID3	include/ssv6200_reg.h	952;"	d
+ADR_RD_ID3	smac/hal/ssv6006c/ssv6006C_reg.h	2130;"	d
+ADR_RD_IN_FFCNT1	include/ssv6200_reg.h	902;"	d
+ADR_RD_IN_FFCNT1	smac/hal/ssv6006c/ssv6006C_reg.h	2075;"	d
+ADR_RD_IN_FFCNT2	include/ssv6200_reg.h	903;"	d
+ADR_RD_IN_FFCNT2	smac/hal/ssv6006c/ssv6006C_reg.h	2076;"	d
+ADR_READ_ONLY_FLAGS_1	include/ssv6200_reg.h	1217;"	d
+ADR_READ_ONLY_FLAGS_2	include/ssv6200_reg.h	1218;"	d
+ADR_READ_ONLY_FLAGS_ADC	smac/hal/ssv6006c/ssv6006C_reg.h	1591;"	d
+ADR_READ_ONLY_FLAGS_SX_2_4GB_1	smac/hal/ssv6006c/ssv6006C_reg.h	1592;"	d
+ADR_READ_ONLY_FLAGS_SX_2_4GB_2	smac/hal/ssv6006c/ssv6006C_reg.h	1593;"	d
+ADR_READ_ONLY_FLAGS_SX_5GB_1	smac/hal/ssv6006c/ssv6006C_reg.h	1644;"	d
+ADR_READ_ONLY_FLAGS_SX_5GB_2	smac/hal/ssv6006c/ssv6006C_reg.h	1645;"	d
+ADR_READ_ONLY_FLAGS_SX_5GB_3	smac/hal/ssv6006c/ssv6006C_reg.h	1646;"	d
+ADR_REASON_TRAP0	include/ssv6200_reg.h	778;"	d
+ADR_REASON_TRAP0	smac/hal/ssv6006c/ssv6006C_reg.h	947;"	d
+ADR_REASON_TRAP1	include/ssv6200_reg.h	779;"	d
+ADR_REASON_TRAP1	smac/hal/ssv6006c/ssv6006C_reg.h	948;"	d
+ADR_REG_LEN_CTRL	include/ssv6200_reg.h	1228;"	d
+ADR_REMAINING_RX_PACKET_LENGTH	smac/hal/ssv6006c/ssv6006C_reg.h	559;"	d
+ADR_REQ_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	2145;"	d
+ADR_RESET_RX_FIFO	smac/hal/ssv6006c/ssv6006C_reg.h	195;"	d
+ADR_RESET_TX_FIFO	smac/hal/ssv6006c/ssv6006C_reg.h	196;"	d
+ADR_RF_5G_TX_PARTITION_BAND1	smac/hal/ssv6006c/ssv6006C_reg.h	1687;"	d
+ADR_RF_5G_TX_PARTITION_BAND2	smac/hal/ssv6006c/ssv6006C_reg.h	1688;"	d
+ADR_RF_CONTROL_0	include/ssv6200_reg.h	1134;"	d
+ADR_RF_CONTROL_1	include/ssv6200_reg.h	1135;"	d
+ADR_RF_D_CAL_TOP_0	smac/hal/ssv6006c/ssv6006C_reg.h	1665;"	d
+ADR_RF_D_CAL_TOP_1	smac/hal/ssv6006c/ssv6006C_reg.h	1666;"	d
+ADR_RF_D_CAL_TOP_2	smac/hal/ssv6006c/ssv6006C_reg.h	1667;"	d
+ADR_RF_D_CAL_TOP_3	smac/hal/ssv6006c/ssv6006C_reg.h	1668;"	d
+ADR_RF_D_CAL_TOP_4	smac/hal/ssv6006c/ssv6006C_reg.h	1669;"	d
+ADR_RF_D_CAL_TOP_5	smac/hal/ssv6006c/ssv6006C_reg.h	1670;"	d
+ADR_RF_D_CAL_TOP_6	smac/hal/ssv6006c/ssv6006C_reg.h	1671;"	d
+ADR_RF_D_CAL_TOP_7	smac/hal/ssv6006c/ssv6006C_reg.h	1672;"	d
+ADR_RF_D_CAL_TOP_8	smac/hal/ssv6006c/ssv6006C_reg.h	1673;"	d
+ADR_RF_D_CAL_TOP_9	smac/hal/ssv6006c/ssv6006C_reg.h	1674;"	d
+ADR_RF_D_DIGITAL_DEBUG_PORT_REGISTER	include/ssv6200_reg.h	1223;"	d
+ADR_RF_D_MODE_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	1678;"	d
+ADR_RF_IQ_CONTROL_0	include/ssv6200_reg.h	1145;"	d
+ADR_RF_IQ_CONTROL_1	include/ssv6200_reg.h	1146;"	d
+ADR_RF_IQ_CONTROL_2	include/ssv6200_reg.h	1147;"	d
+ADR_RF_IQ_CONTROL_3	include/ssv6200_reg.h	1148;"	d
+ADR_ROM_PATCH00_0	smac/hal/ssv6006c/ssv6006C_reg.h	294;"	d
+ADR_ROM_PATCH00_1	smac/hal/ssv6006c/ssv6006C_reg.h	295;"	d
+ADR_ROM_PATCH01_0	smac/hal/ssv6006c/ssv6006C_reg.h	296;"	d
+ADR_ROM_PATCH01_1	smac/hal/ssv6006c/ssv6006C_reg.h	297;"	d
+ADR_ROM_PATCH02_0	smac/hal/ssv6006c/ssv6006C_reg.h	525;"	d
+ADR_ROM_PATCH02_1	smac/hal/ssv6006c/ssv6006C_reg.h	526;"	d
+ADR_ROM_PATCH03_0	smac/hal/ssv6006c/ssv6006C_reg.h	527;"	d
+ADR_ROM_PATCH03_1	smac/hal/ssv6006c/ssv6006C_reg.h	528;"	d
+ADR_ROM_PATCH04_0	smac/hal/ssv6006c/ssv6006C_reg.h	529;"	d
+ADR_ROM_PATCH04_1	smac/hal/ssv6006c/ssv6006C_reg.h	530;"	d
+ADR_ROM_PATCH05_0	smac/hal/ssv6006c/ssv6006C_reg.h	531;"	d
+ADR_ROM_PATCH05_1	smac/hal/ssv6006c/ssv6006C_reg.h	532;"	d
+ADR_ROM_PATCH06_0	smac/hal/ssv6006c/ssv6006C_reg.h	533;"	d
+ADR_ROM_PATCH06_1	smac/hal/ssv6006c/ssv6006C_reg.h	534;"	d
+ADR_ROM_PATCH07_0	smac/hal/ssv6006c/ssv6006C_reg.h	535;"	d
+ADR_ROM_PATCH07_1	smac/hal/ssv6006c/ssv6006C_reg.h	536;"	d
+ADR_ROM_PATCH08_0	smac/hal/ssv6006c/ssv6006C_reg.h	537;"	d
+ADR_ROM_PATCH08_1	smac/hal/ssv6006c/ssv6006C_reg.h	538;"	d
+ADR_ROM_PATCH09_0	smac/hal/ssv6006c/ssv6006C_reg.h	539;"	d
+ADR_ROM_PATCH09_1	smac/hal/ssv6006c/ssv6006C_reg.h	540;"	d
+ADR_ROM_PATCH10_0	smac/hal/ssv6006c/ssv6006C_reg.h	541;"	d
+ADR_ROM_PATCH10_1	smac/hal/ssv6006c/ssv6006C_reg.h	542;"	d
+ADR_ROM_PATCH11_0	smac/hal/ssv6006c/ssv6006C_reg.h	543;"	d
+ADR_ROM_PATCH11_1	smac/hal/ssv6006c/ssv6006C_reg.h	544;"	d
+ADR_ROM_PATCH12_0	smac/hal/ssv6006c/ssv6006C_reg.h	545;"	d
+ADR_ROM_PATCH12_1	smac/hal/ssv6006c/ssv6006C_reg.h	546;"	d
+ADR_ROM_PATCH13_0	smac/hal/ssv6006c/ssv6006C_reg.h	547;"	d
+ADR_ROM_PATCH13_1	smac/hal/ssv6006c/ssv6006C_reg.h	548;"	d
+ADR_ROM_PATCH14_0	smac/hal/ssv6006c/ssv6006C_reg.h	549;"	d
+ADR_ROM_PATCH14_1	smac/hal/ssv6006c/ssv6006C_reg.h	550;"	d
+ADR_ROM_PATCH15_0	smac/hal/ssv6006c/ssv6006C_reg.h	551;"	d
+ADR_ROM_PATCH15_1	smac/hal/ssv6006c/ssv6006C_reg.h	552;"	d
+ADR_ROM_READ_PROT	smac/hal/ssv6006c/ssv6006C_reg.h	249;"	d
+ADR_ROPMUSTATE	smac/hal/ssv6006c/ssv6006C_reg.h	248;"	d
+ADR_RTC_1	include/ssv6200_reg.h	404;"	d
+ADR_RTC_2	include/ssv6200_reg.h	405;"	d
+ADR_RTC_3R	include/ssv6200_reg.h	407;"	d
+ADR_RTC_3W	include/ssv6200_reg.h	406;"	d
+ADR_RTC_4	include/ssv6200_reg.h	408;"	d
+ADR_RTC_RAM	include/ssv6200_reg.h	409;"	d
+ADR_RTN_STA	include/ssv6200_reg.h	943;"	d
+ADR_RTN_STA	smac/hal/ssv6006c/ssv6006C_reg.h	2121;"	d
+ADR_RX_11B_CCA_0	include/ssv6200_reg.h	1062;"	d
+ADR_RX_11B_CCA_1	include/ssv6200_reg.h	1063;"	d
+ADR_RX_11B_CCA_CONTROL	include/ssv6200_reg.h	1076;"	d
+ADR_RX_11B_CE_CNT_THRESHOLD	include/ssv6200_reg.h	1066;"	d
+ADR_RX_11B_CE_MU_0	include/ssv6200_reg.h	1067;"	d
+ADR_RX_11B_CE_MU_1	include/ssv6200_reg.h	1068;"	d
+ADR_RX_11B_CIT_CNT_THRESHOLD	include/ssv6200_reg.h	1073;"	d
+ADR_RX_11B_DES_DLY	include/ssv6200_reg.h	1061;"	d
+ADR_RX_11B_EQ_CH_MAIN_TAP	include/ssv6200_reg.h	1074;"	d
+ADR_RX_11B_EQ_CR_KP_KI	include/ssv6200_reg.h	1071;"	d
+ADR_RX_11B_EQ_MU_0	include/ssv6200_reg.h	1069;"	d
+ADR_RX_11B_EQ_MU_1	include/ssv6200_reg.h	1070;"	d
+ADR_RX_11B_FREQUENCY_OFFSET	include/ssv6200_reg.h	1077;"	d
+ADR_RX_11B_LPF_RATE	include/ssv6200_reg.h	1072;"	d
+ADR_RX_11B_PKT_CCA_AND_PKT_CNT	include/ssv6200_reg.h	1081;"	d
+ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT	include/ssv6200_reg.h	1080;"	d
+ADR_RX_11B_PKT_STAT_EN	include/ssv6200_reg.h	1084;"	d
+ADR_RX_11B_SEARCH_CNT_TH	include/ssv6200_reg.h	1075;"	d
+ADR_RX_11B_SFD_CRC_CNT	include/ssv6200_reg.h	1079;"	d
+ADR_RX_11B_SFD_FIELD_1	include/ssv6200_reg.h	1083;"	d
+ADR_RX_11B_SFD_FILED_0	include/ssv6200_reg.h	1082;"	d
+ADR_RX_11B_SNR_RSSI	include/ssv6200_reg.h	1078;"	d
+ADR_RX_11B_SOFT_RST	include/ssv6200_reg.h	1085;"	d
+ADR_RX_11B_TR_KP_KI_0	include/ssv6200_reg.h	1064;"	d
+ADR_RX_11B_TR_KP_KI_1	include/ssv6200_reg.h	1065;"	d
+ADR_RX_11GN_BIST_0	include/ssv6200_reg.h	1117;"	d
+ADR_RX_11GN_BIST_1	include/ssv6200_reg.h	1118;"	d
+ADR_RX_11GN_BIST_2	include/ssv6200_reg.h	1119;"	d
+ADR_RX_11GN_BIST_3	include/ssv6200_reg.h	1120;"	d
+ADR_RX_11GN_BIST_4	include/ssv6200_reg.h	1121;"	d
+ADR_RX_11GN_BIST_5	include/ssv6200_reg.h	1122;"	d
+ADR_RX_11GN_CCA_0	include/ssv6200_reg.h	1094;"	d
+ADR_RX_11GN_CCA_1	include/ssv6200_reg.h	1095;"	d
+ADR_RX_11GN_CCA_2	include/ssv6200_reg.h	1096;"	d
+ADR_RX_11GN_CCA_ATCOR_RE_CHECK	include/ssv6200_reg.h	1108;"	d
+ADR_RX_11GN_CCA_CNT	include/ssv6200_reg.h	1107;"	d
+ADR_RX_11GN_CCA_FFT_SCALE	include/ssv6200_reg.h	1097;"	d
+ADR_RX_11GN_CCA_PWR	include/ssv6200_reg.h	1106;"	d
+ADR_RX_11GN_CHANNEL_UPDATE	include/ssv6200_reg.h	1112;"	d
+ADR_RX_11GN_DES_DLY	include/ssv6200_reg.h	1090;"	d
+ADR_RX_11GN_ERR_UPDATE	include/ssv6200_reg.h	1110;"	d
+ADR_RX_11GN_FREQ_OFFSET	include/ssv6200_reg.h	1125;"	d
+ADR_RX_11GN_PKT_CCA_AND_PKT_CNT	include/ssv6200_reg.h	1129;"	d
+ADR_RX_11GN_PKT_ERR_CNT	include/ssv6200_reg.h	1128;"	d
+ADR_RX_11GN_PKT_FORMAT_0	include/ssv6200_reg.h	1113;"	d
+ADR_RX_11GN_PKT_FORMAT_1	include/ssv6200_reg.h	1114;"	d
+ADR_RX_11GN_RATE	include/ssv6200_reg.h	1131;"	d
+ADR_RX_11GN_READ_0	include/ssv6200_reg.h	1124;"	d
+ADR_RX_11GN_SERVICE_LENGTH_FIELD	include/ssv6200_reg.h	1130;"	d
+ADR_RX_11GN_SHORT_GI	include/ssv6200_reg.h	1111;"	d
+ADR_RX_11GN_SIGNAL_FIELD_0	include/ssv6200_reg.h	1126;"	d
+ADR_RX_11GN_SIGNAL_FIELD_1	include/ssv6200_reg.h	1127;"	d
+ADR_RX_11GN_SOFT_DEMAP_0	include/ssv6200_reg.h	1098;"	d
+ADR_RX_11GN_SOFT_DEMAP_1	include/ssv6200_reg.h	1099;"	d
+ADR_RX_11GN_SOFT_DEMAP_2	include/ssv6200_reg.h	1100;"	d
+ADR_RX_11GN_SOFT_DEMAP_3	include/ssv6200_reg.h	1101;"	d
+ADR_RX_11GN_SOFT_DEMAP_4	include/ssv6200_reg.h	1102;"	d
+ADR_RX_11GN_SOFT_DEMAP_5	include/ssv6200_reg.h	1103;"	d
+ADR_RX_11GN_SOFT_RST	include/ssv6200_reg.h	1133;"	d
+ADR_RX_11GN_SPECTRUM_ANALYZER	include/ssv6200_reg.h	1123;"	d
+ADR_RX_11GN_STAT_EN	include/ssv6200_reg.h	1132;"	d
+ADR_RX_11GN_STBC_TR_KP_KI	include/ssv6200_reg.h	1116;"	d
+ADR_RX_11GN_SYM_BOUND_0	include/ssv6200_reg.h	1104;"	d
+ADR_RX_11GN_SYM_BOUND_1	include/ssv6200_reg.h	1105;"	d
+ADR_RX_11GN_TR_0	include/ssv6200_reg.h	1091;"	d
+ADR_RX_11GN_TR_1	include/ssv6200_reg.h	1092;"	d
+ADR_RX_11GN_TR_2	include/ssv6200_reg.h	1093;"	d
+ADR_RX_11GN_TX_TIME	include/ssv6200_reg.h	1115;"	d
+ADR_RX_11GN_VTB_TB	include/ssv6200_reg.h	1109;"	d
+ADR_RX_ADC_REGISTER	include/ssv6200_reg.h	1192;"	d
+ADR_RX_COMPENSATION_CONTROL	include/ssv6200_reg.h	1140;"	d
+ADR_RX_DATA_CMD52_ABORT_COUNT	include/ssv6200_reg.h	262;"	d
+ADR_RX_DC_CAL_RESULT	smac/hal/ssv6006c/ssv6006C_reg.h	1684;"	d
+ADR_RX_DROP_COUNT	smac/hal/ssv6006c/ssv6006C_reg.h	593;"	d
+ADR_RX_ETHER_TYPE_0	include/ssv6200_reg.h	426;"	d
+ADR_RX_ETHER_TYPE_0	smac/hal/ssv6006c/ssv6006C_reg.h	574;"	d
+ADR_RX_ETHER_TYPE_1	include/ssv6200_reg.h	427;"	d
+ADR_RX_ETHER_TYPE_1	smac/hal/ssv6006c/ssv6006C_reg.h	575;"	d
+ADR_RX_FE_GAIN_DECODER_REGISTER_1	include/ssv6200_reg.h	1187;"	d
+ADR_RX_FE_GAIN_DECODER_REGISTER_2	include/ssv6200_reg.h	1188;"	d
+ADR_RX_FE_GAIN_DECODER_REGISTER_3	include/ssv6200_reg.h	1189;"	d
+ADR_RX_FE_GAIN_DECODER_REGISTER_4	include/ssv6200_reg.h	1190;"	d
+ADR_RX_FE_REGISTER_1	include/ssv6200_reg.h	1186;"	d
+ADR_RX_FLOW_CTRL	include/ssv6200_reg.h	581;"	d
+ADR_RX_FLOW_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	702;"	d
+ADR_RX_FLOW_DATA	include/ssv6200_reg.h	579;"	d
+ADR_RX_FLOW_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	700;"	d
+ADR_RX_FLOW_MNG	include/ssv6200_reg.h	580;"	d
+ADR_RX_FLOW_MNG	smac/hal/ssv6006c/ssv6006C_reg.h	701;"	d
+ADR_RX_HCI_EXP_0_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	605;"	d
+ADR_RX_HCI_EXP_0_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	606;"	d
+ADR_RX_HOST_EVENT_COUNT	smac/hal/ssv6006c/ssv6006C_reg.h	595;"	d
+ADR_RX_ID0	include/ssv6200_reg.h	941;"	d
+ADR_RX_ID0	smac/hal/ssv6006c/ssv6006C_reg.h	2119;"	d
+ADR_RX_ID1	include/ssv6200_reg.h	942;"	d
+ADR_RX_ID1	smac/hal/ssv6006c/ssv6006C_reg.h	2120;"	d
+ADR_RX_ID2	include/ssv6200_reg.h	955;"	d
+ADR_RX_ID2	smac/hal/ssv6006c/ssv6006C_reg.h	2133;"	d
+ADR_RX_ID3	include/ssv6200_reg.h	956;"	d
+ADR_RX_ID3	smac/hal/ssv6006c/ssv6006C_reg.h	2134;"	d
+ADR_RX_OBSERVATION_CIRCUIT_0	include/ssv6200_reg.h	1141;"	d
+ADR_RX_OBSERVATION_CIRCUIT_1	include/ssv6200_reg.h	1142;"	d
+ADR_RX_OBSERVATION_CIRCUIT_2	include/ssv6200_reg.h	1143;"	d
+ADR_RX_OBSERVATION_CIRCUIT_3	include/ssv6200_reg.h	1144;"	d
+ADR_RX_PACKET_COUNTER	smac/hal/ssv6006c/ssv6006C_reg.h	597;"	d
+ADR_RX_PACKET_LENGTH_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	560;"	d
+ADR_RX_QUOTA	include/ssv6200_reg.h	310;"	d
+ADR_RX_RC_VALUE_TUNE	smac/hal/ssv6006c/ssv6006C_reg.h	1659;"	d
+ADR_RX_RESCUE_HELPER	smac/hal/ssv6006c/ssv6006C_reg.h	578;"	d
+ADR_RX_TIME_STAMP_CFG	include/ssv6200_reg.h	582;"	d
+ADR_RX_TIME_STAMP_CFG	smac/hal/ssv6006c/ssv6006C_reg.h	703;"	d
+ADR_RX_TRAP_COUNT	smac/hal/ssv6006c/ssv6006C_reg.h	591;"	d
+ADR_RX_TX_FSM_REGISTER	include/ssv6200_reg.h	1191;"	d
+ADR_R_TRX_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	198;"	d
+ADR_SBUS_CFG0_1	smac/hal/ssv6006c/ssv6006C_reg.h	168;"	d
+ADR_SBUS_CFG0_2	smac/hal/ssv6006c/ssv6006C_reg.h	169;"	d
+ADR_SBUS_CFG1_1	smac/hal/ssv6006c/ssv6006C_reg.h	174;"	d
+ADR_SBUS_CFG1_2	smac/hal/ssv6006c/ssv6006C_reg.h	175;"	d
+ADR_SBUS_CH_EN	smac/hal/ssv6006c/ssv6006C_reg.h	189;"	d
+ADR_SBUS_CLRERR	smac/hal/ssv6006c/ssv6006C_reg.h	183;"	d
+ADR_SBUS_CLRTR	smac/hal/ssv6006c/ssv6006C_reg.h	182;"	d
+ADR_SBUS_CTL0_1	smac/hal/ssv6006c/ssv6006C_reg.h	166;"	d
+ADR_SBUS_CTL0_2	smac/hal/ssv6006c/ssv6006C_reg.h	167;"	d
+ADR_SBUS_CTL1_1	smac/hal/ssv6006c/ssv6006C_reg.h	172;"	d
+ADR_SBUS_CTL1_2	smac/hal/ssv6006c/ssv6006C_reg.h	173;"	d
+ADR_SBUS_DAR0	smac/hal/ssv6006c/ssv6006C_reg.h	165;"	d
+ADR_SBUS_DAR1	smac/hal/ssv6006c/ssv6006C_reg.h	171;"	d
+ADR_SBUS_DMA_EN	smac/hal/ssv6006c/ssv6006C_reg.h	188;"	d
+ADR_SBUS_MASKERR	smac/hal/ssv6006c/ssv6006C_reg.h	181;"	d
+ADR_SBUS_MASKTR	smac/hal/ssv6006c/ssv6006C_reg.h	180;"	d
+ADR_SBUS_RAWERR	smac/hal/ssv6006c/ssv6006C_reg.h	177;"	d
+ADR_SBUS_RAWTR	smac/hal/ssv6006c/ssv6006C_reg.h	176;"	d
+ADR_SBUS_SAR0	smac/hal/ssv6006c/ssv6006C_reg.h	164;"	d
+ADR_SBUS_SAR1	smac/hal/ssv6006c/ssv6006C_reg.h	170;"	d
+ADR_SBUS_SHS_DST_REQ_CFG	smac/hal/ssv6006c/ssv6006C_reg.h	185;"	d
+ADR_SBUS_SHS_DST_SREQ_CFG	smac/hal/ssv6006c/ssv6006C_reg.h	187;"	d
+ADR_SBUS_SHS_SRC_REQ_CFG	smac/hal/ssv6006c/ssv6006C_reg.h	184;"	d
+ADR_SBUS_SHS_SRC_SREQ_CFG	smac/hal/ssv6006c/ssv6006C_reg.h	186;"	d
+ADR_SBUS_STATUSERR	smac/hal/ssv6006c/ssv6006C_reg.h	179;"	d
+ADR_SBUS_STATUSTR	smac/hal/ssv6006c/ssv6006C_reg.h	178;"	d
+ADR_SCRT_SET	include/ssv6200_reg.h	785;"	d
+ADR_SCRT_SET	smac/hal/ssv6006c/ssv6006C_reg.h	953;"	d
+ADR_SCRT_STATE	include/ssv6200_reg.h	782;"	d
+ADR_SCRT_STATE	smac/hal/ssv6006c/ssv6006C_reg.h	954;"	d
+ADR_SDIO_BLOCK_CNT_INFO	include/ssv6200_reg.h	261;"	d
+ADR_SDIO_BUS_STATE_DEBUG_MONITOR	include/ssv6200_reg.h	252;"	d
+ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG	include/ssv6200_reg.h	249;"	d
+ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG	smac/hal/ssv6006c/ssv6006C_reg.h	361;"	d
+ADR_SDIO_CARD_STATUS_REG	include/ssv6200_reg.h	253;"	d
+ADR_SDIO_CARD_STATUS_REG	smac/hal/ssv6006c/ssv6006C_reg.h	362;"	d
+ADR_SDIO_COMMAND_LOG_DATA_31_0	include/ssv6200_reg.h	268;"	d
+ADR_SDIO_COMMAND_LOG_DATA_63_32	include/ssv6200_reg.h	269;"	d
+ADR_SDIO_CRC7_CRC16_ERROR_REG	include/ssv6200_reg.h	260;"	d
+ADR_SDIO_DELAY_CHAIN_0	smac/hal/ssv6006c/ssv6006C_reg.h	364;"	d
+ADR_SDIO_DELAY_CHAIN_1	smac/hal/ssv6006c/ssv6006C_reg.h	365;"	d
+ADR_SDIO_FIFO_ERROR_CNT	include/ssv6200_reg.h	259;"	d
+ADR_SDIO_FIFO_WR_LIMIT_REG	include/ssv6200_reg.h	244;"	d
+ADR_SDIO_FIFO_WR_THLD_REG	include/ssv6200_reg.h	243;"	d
+ADR_SDIO_IPC	include/ssv6200_reg.h	363;"	d
+ADR_SDIO_IRQ_STS	include/ssv6200_reg.h	365;"	d
+ADR_SDIO_LAST_CMD_ARG_REG	include/ssv6200_reg.h	251;"	d
+ADR_SDIO_LAST_CMD_INDEX_CRC_REG	include/ssv6200_reg.h	250;"	d
+ADR_SDIO_LOG_START_END_DATA_REG	include/ssv6200_reg.h	248;"	d
+ADR_SDIO_MASK	include/ssv6200_reg.h	364;"	d
+ADR_SDIO_RESET_WAKE_CFG	smac/hal/ssv6006c/ssv6006C_reg.h	285;"	d
+ADR_SDIO_RX_DATA_BATCH_SIZE_REG	include/ssv6200_reg.h	247;"	d
+ADR_SDIO_RX_FAIL_COUNT	smac/hal/ssv6006c/ssv6006C_reg.h	599;"	d
+ADR_SDIO_THLD_FOR_CMD53RD_REG	include/ssv6200_reg.h	246;"	d
+ADR_SDIO_TX_ALLOC_REG	include/ssv6200_reg.h	265;"	d
+ADR_SDIO_TX_DATA_BATCH_SIZE_REG	include/ssv6200_reg.h	245;"	d
+ADR_SDIO_TX_FAIL_COUNT	smac/hal/ssv6006c/ssv6006C_reg.h	600;"	d
+ADR_SDIO_TX_INFORM	include/ssv6200_reg.h	266;"	d
+ADR_SDIO_TX_RX_FAIL_COUNTER_0	include/ssv6200_reg.h	436;"	d
+ADR_SDIO_TX_RX_FAIL_COUNTER_1	include/ssv6200_reg.h	437;"	d
+ADR_SDIO_WAKE_MODE	include/ssv6200_reg.h	416;"	d
+ADR_SD_INIT_CFG	include/ssv6200_reg.h	147;"	d
+ADR_SD_PERI_MASK	include/ssv6200_reg.h	366;"	d
+ADR_SD_PERI_STS	include/ssv6200_reg.h	367;"	d
+ADR_SHA_DST_ADDR	include/ssv6200_reg.h	467;"	d
+ADR_SHA_DST_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	626;"	d
+ADR_SHA_SETTING	include/ssv6200_reg.h	469;"	d
+ADR_SHA_SETTING	smac/hal/ssv6006c/ssv6006C_reg.h	628;"	d
+ADR_SHA_SRC_ADDR	include/ssv6200_reg.h	468;"	d
+ADR_SHA_SRC_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	627;"	d
+ADR_SMS4_CFG1	include/ssv6200_reg.h	505;"	d
+ADR_SMS4_CFG2	include/ssv6200_reg.h	506;"	d
+ADR_SMS4_DATA_IN0	include/ssv6200_reg.h	511;"	d
+ADR_SMS4_DATA_IN1	include/ssv6200_reg.h	512;"	d
+ADR_SMS4_DATA_IN2	include/ssv6200_reg.h	513;"	d
+ADR_SMS4_DATA_IN3	include/ssv6200_reg.h	514;"	d
+ADR_SMS4_DATA_OUT0	include/ssv6200_reg.h	515;"	d
+ADR_SMS4_DATA_OUT1	include/ssv6200_reg.h	516;"	d
+ADR_SMS4_DATA_OUT2	include/ssv6200_reg.h	517;"	d
+ADR_SMS4_DATA_OUT3	include/ssv6200_reg.h	518;"	d
+ADR_SMS4_KEY_0	include/ssv6200_reg.h	519;"	d
+ADR_SMS4_KEY_1	include/ssv6200_reg.h	520;"	d
+ADR_SMS4_KEY_2	include/ssv6200_reg.h	521;"	d
+ADR_SMS4_KEY_3	include/ssv6200_reg.h	522;"	d
+ADR_SMS4_MODE1	include/ssv6200_reg.h	507;"	d
+ADR_SMS4_MODE_IV0	include/ssv6200_reg.h	523;"	d
+ADR_SMS4_MODE_IV1	include/ssv6200_reg.h	524;"	d
+ADR_SMS4_MODE_IV2	include/ssv6200_reg.h	525;"	d
+ADR_SMS4_MODE_IV3	include/ssv6200_reg.h	526;"	d
+ADR_SMS4_OFB_ENC0	include/ssv6200_reg.h	527;"	d
+ADR_SMS4_OFB_ENC1	include/ssv6200_reg.h	528;"	d
+ADR_SMS4_OFB_ENC2	include/ssv6200_reg.h	529;"	d
+ADR_SMS4_OFB_ENC3	include/ssv6200_reg.h	530;"	d
+ADR_SMS4_STATUS1	include/ssv6200_reg.h	509;"	d
+ADR_SMS4_STATUS2	include/ssv6200_reg.h	510;"	d
+ADR_SMS4_TRIG	include/ssv6200_reg.h	508;"	d
+ADR_SPARE_UART_INFO	include/ssv6200_reg.h	148;"	d
+ADR_SPARE_UART_INFO	smac/hal/ssv6006c/ssv6006C_reg.h	287;"	d
+ADR_SPIMST_CEN	smac/hal/ssv6006c/ssv6006C_reg.h	227;"	d
+ADR_SPIMST_CFG0	smac/hal/ssv6006c/ssv6006C_reg.h	224;"	d
+ADR_SPIMST_CFG1	smac/hal/ssv6006c/ssv6006C_reg.h	225;"	d
+ADR_SPIMST_EN	smac/hal/ssv6006c/ssv6006C_reg.h	226;"	d
+ADR_SPIMST_INT	smac/hal/ssv6006c/ssv6006C_reg.h	233;"	d
+ADR_SPIMST_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	232;"	d
+ADR_SPIMST_RXFIFO_TH	smac/hal/ssv6006c/ssv6006C_reg.h	230;"	d
+ADR_SPIMST_RX_SAMPLE_DLY	smac/hal/ssv6006c/ssv6006C_reg.h	235;"	d
+ADR_SPIMST_SCLK_RATE	smac/hal/ssv6006c/ssv6006C_reg.h	228;"	d
+ADR_SPIMST_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	231;"	d
+ADR_SPIMST_TRX_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	234;"	d
+ADR_SPIMST_TXFIFO_TH	smac/hal/ssv6006c/ssv6006C_reg.h	229;"	d
+ADR_SPI_BUSY	smac/hal/ssv6006c/ssv6006C_reg.h	646;"	d
+ADR_SPI_CFG	smac/hal/ssv6006c/ssv6006C_reg.h	650;"	d
+ADR_SPI_CLK_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	645;"	d
+ADR_SPI_CLR	smac/hal/ssv6006c/ssv6006C_reg.h	647;"	d
+ADR_SPI_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	644;"	d
+ADR_SPI_IPC	include/ssv6200_reg.h	362;"	d
+ADR_SPI_MAS_COMMAND_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	651;"	d
+ADR_SPI_MAS_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	648;"	d
+ADR_SPI_MODE	include/ssv6200_reg.h	309;"	d
+ADR_SPI_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	409;"	d
+ADR_SPI_M_CFG	smac/hal/ssv6006c/ssv6006C_reg.h	649;"	d
+ADR_SPI_PARAM	include/ssv6200_reg.h	389;"	d
+ADR_SPI_PARAM	smac/hal/ssv6006c/ssv6006C_reg.h	468;"	d
+ADR_SPI_PARAM2	include/ssv6200_reg.h	390;"	d
+ADR_SPI_PARAM2	smac/hal/ssv6006c/ssv6006C_reg.h	469;"	d
+ADR_SPI_RX_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	471;"	d
+ADR_SPI_STS	include/ssv6200_reg.h	317;"	d
+ADR_SPI_TO_PHY_PARAM1	include/ssv6200_reg.h	315;"	d
+ADR_SPI_TO_PHY_PARAM1	smac/hal/ssv6006c/ssv6006C_reg.h	411;"	d
+ADR_SPI_TO_PHY_PARAM2	include/ssv6200_reg.h	316;"	d
+ADR_SPI_TO_PHY_PARAM2	smac/hal/ssv6006c/ssv6006C_reg.h	412;"	d
+ADR_SPI_TX_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	470;"	d
+ADR_SRAMCFG_SETTING	smac/hal/ssv6006c/ssv6006C_reg.h	293;"	d
+ADR_SRAM_ADDR	include/ssv6200_reg.h	387;"	d
+ADR_STAT_CONF0	smac/hal/ssv6006c/ssv6006C_reg.h	753;"	d
+ADR_STAT_CONF1	smac/hal/ssv6006c/ssv6006C_reg.h	754;"	d
+ADR_STA_MAC1_0	smac/hal/ssv6006c/ssv6006C_reg.h	957;"	d
+ADR_STA_MAC1_1	smac/hal/ssv6006c/ssv6006C_reg.h	958;"	d
+ADR_STA_MAC_0	include/ssv6200_reg.h	783;"	d
+ADR_STA_MAC_0	smac/hal/ssv6006c/ssv6006C_reg.h	951;"	d
+ADR_STA_MAC_1	include/ssv6200_reg.h	784;"	d
+ADR_STA_MAC_1	smac/hal/ssv6006c/ssv6006C_reg.h	952;"	d
+ADR_SUMMARY_TYPHOST_INT_MAP	smac/hal/ssv6006c/ssv6006C_reg.h	501;"	d
+ADR_SUMMARY_TYPMCU_INT_MAP	smac/hal/ssv6006c/ssv6006C_reg.h	514;"	d
+ADR_SVN_VERSION_REG	include/ssv6200_reg.h	965;"	d
+ADR_SWITCH_CTL	include/ssv6200_reg.h	788;"	d
+ADR_SWITCH_CTL	smac/hal/ssv6006c/ssv6006C_reg.h	962;"	d
+ADR_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE	smac/hal/ssv6006c/ssv6006C_reg.h	1535;"	d
+ADR_SX_2_4GB_AAC	smac/hal/ssv6006c/ssv6006C_reg.h	1542;"	d
+ADR_SX_2_4GB_DIV_SDM	smac/hal/ssv6006c/ssv6006C_reg.h	1540;"	d
+ADR_SX_2_4GB_FRACTIONAL_AND_INTEGER_8BITS	smac/hal/ssv6006c/ssv6006C_reg.h	1534;"	d
+ADR_SX_2_4GB_LPF	smac/hal/ssv6006c/ssv6006C_reg.h	1537;"	d
+ADR_SX_2_4GB_PFD_CHP_	smac/hal/ssv6006c/ssv6006C_reg.h	1536;"	d
+ADR_SX_2_4GB_SBCAL	smac/hal/ssv6006c/ssv6006C_reg.h	1541;"	d
+ADR_SX_2_4GB_TTL	smac/hal/ssv6006c/ssv6006C_reg.h	1543;"	d
+ADR_SX_2_4GB_VCO	smac/hal/ssv6006c/ssv6006C_reg.h	1538;"	d
+ADR_SX_2_4GB_VCOBF	smac/hal/ssv6006c/ssv6006C_reg.h	1539;"	d
+ADR_SX_2_4G_LDO_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1533;"	d
+ADR_SX_5GB_DIV_SDM	smac/hal/ssv6006c/ssv6006C_reg.h	1612;"	d
+ADR_SX_5GB_DUMMY_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1643;"	d
+ADR_SX_5GB_ENABLE_TOP_CONTROLLER	smac/hal/ssv6006c/ssv6006C_reg.h	1607;"	d
+ADR_SX_5GB_FRACTIONAL_AND_INTEGER_8BITS	smac/hal/ssv6006c/ssv6006C_reg.h	1605;"	d
+ADR_SX_5GB_LDO_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1608;"	d
+ADR_SX_5GB_LOGEN_CALIBRATION	smac/hal/ssv6006c/ssv6006C_reg.h	1615;"	d
+ADR_SX_5GB_LPF_TTL	smac/hal/ssv6006c/ssv6006C_reg.h	1610;"	d
+ADR_SX_5GB_PFD_CHP_	smac/hal/ssv6006c/ssv6006C_reg.h	1609;"	d
+ADR_SX_5GB_REGISTER_INT3BIT___CH_TABLE	smac/hal/ssv6006c/ssv6006C_reg.h	1606;"	d
+ADR_SX_5GB_SBCAL	smac/hal/ssv6006c/ssv6006C_reg.h	1613;"	d
+ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION	smac/hal/ssv6006c/ssv6006C_reg.h	1614;"	d
+ADR_SX_5GB_VCO_LOGEN	smac/hal/ssv6006c/ssv6006C_reg.h	1611;"	d
+ADR_SX_DUMMY_REGISTER	include/ssv6200_reg.h	1216;"	d
+ADR_SX_ENABLE_REGISTER	include/ssv6200_reg.h	1194;"	d
+ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER	smac/hal/ssv6006c/ssv6006C_reg.h	1532;"	d
+ADR_SX_LCK_BIN_REGISTERS_I	include/ssv6200_reg.h	1214;"	d
+ADR_SX_LCK_BIN_REGISTERS_II	include/ssv6200_reg.h	1221;"	d
+ADR_SX_LOCK_FREQ_1	smac/hal/ssv6006c/ssv6006C_reg.h	1682;"	d
+ADR_SX_LOCK_FREQ_2	smac/hal/ssv6006c/ssv6006C_reg.h	1683;"	d
+ADR_SYN_DIV_SDM_XOSC	include/ssv6200_reg.h	1199;"	d
+ADR_SYN_KVCO_XO_FINE_TUNE_CBANK	include/ssv6200_reg.h	1200;"	d
+ADR_SYN_LCK_VT	include/ssv6200_reg.h	1201;"	d
+ADR_SYN_PFD_CHP	include/ssv6200_reg.h	1197;"	d
+ADR_SYN_REGISTER_1	include/ssv6200_reg.h	1195;"	d
+ADR_SYN_REGISTER_2	include/ssv6200_reg.h	1196;"	d
+ADR_SYN_VCO_LOBF	include/ssv6200_reg.h	1198;"	d
+ADR_SYSCTRL_COMMAND	smac/hal/ssv6006c/ssv6006C_reg.h	254;"	d
+ADR_SYSCTRL_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	256;"	d
+ADR_SYSTEM_INFORMATION_REG	include/ssv6200_reg.h	241;"	d
+ADR_SYSTEM_INFORMATION_REGISTER	include/ssv6200_reg.h	270;"	d
+ADR_SYS_CSR_CLOCK_ENABLE	include/ssv6200_reg.h	122;"	d
+ADR_SYS_CSR_CLOCK_ENABLE	smac/hal/ssv6006c/ssv6006C_reg.h	244;"	d
+ADR_SYS_INT_FOR_HOST	include/ssv6200_reg.h	361;"	d
+ADR_SYS_WDOG_REG	include/ssv6200_reg.h	182;"	d
+ADR_SYS_WDOG_REG	smac/hal/ssv6006c/ssv6006C_reg.h	324;"	d
+ADR_TAG_SRAM0_F_STATUS_0	include/ssv6200_reg.h	1258;"	d
+ADR_TAG_SRAM0_F_STATUS_1	include/ssv6200_reg.h	1259;"	d
+ADR_TAG_SRAM0_F_STATUS_2	include/ssv6200_reg.h	1260;"	d
+ADR_TAG_SRAM0_F_STATUS_3	include/ssv6200_reg.h	1261;"	d
+ADR_TAG_SRAM0_F_STATUS_4	include/ssv6200_reg.h	1262;"	d
+ADR_TAG_SRAM0_F_STATUS_5	include/ssv6200_reg.h	1263;"	d
+ADR_TAG_SRAM0_F_STATUS_6	include/ssv6200_reg.h	1264;"	d
+ADR_TAG_SRAM0_F_STATUS_7	include/ssv6200_reg.h	1265;"	d
+ADR_TAG_STATUS	include/ssv6200_reg.h	1235;"	d
+ADR_TAG_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	2144;"	d
+ADR_TB_ADR_SEL	include/ssv6200_reg.h	131;"	d
+ADR_TB_ADR_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	251;"	d
+ADR_TB_RDATA	include/ssv6200_reg.h	132;"	d
+ADR_TB_RDATA	smac/hal/ssv6006c/ssv6006C_reg.h	252;"	d
+ADR_TEST_MODE	include/ssv6200_reg.h	145;"	d
+ADR_TEST_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	264;"	d
+ADR_THREASHOLD	include/ssv6200_reg.h	419;"	d
+ADR_THRESHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	561;"	d
+ADR_TM0_CURRENT_MILISECOND_TIME_VALUE	include/ssv6200_reg.h	166;"	d
+ADR_TM0_CURRENT_MILLISECOND_TIME_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	312;"	d
+ADR_TM0_DUMMY_BIT_0	include/ssv6200_reg.h	167;"	d
+ADR_TM0_DUMMY_BIT_1	include/ssv6200_reg.h	168;"	d
+ADR_TM0_MILISECOND_TIMER	include/ssv6200_reg.h	165;"	d
+ADR_TM0_MILLISECOND_TIMER	smac/hal/ssv6006c/ssv6006C_reg.h	311;"	d
+ADR_TM0_MILLISECOND_TIMER_PRESCALE	smac/hal/ssv6006c/ssv6006C_reg.h	313;"	d
+ADR_TM1_CURRENT_MILISECOND_TIME_VALUE	include/ssv6200_reg.h	170;"	d
+ADR_TM1_CURRENT_MILLISECOND_TIME_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	315;"	d
+ADR_TM1_DUMMY_BIT_0	include/ssv6200_reg.h	171;"	d
+ADR_TM1_DUMMY_BIT_1	include/ssv6200_reg.h	172;"	d
+ADR_TM1_MILISECOND_TIMER	include/ssv6200_reg.h	169;"	d
+ADR_TM1_MILLISECOND_TIMER	smac/hal/ssv6006c/ssv6006C_reg.h	314;"	d
+ADR_TM1_MILLISECOND_TIMER_PRESCALE	smac/hal/ssv6006c/ssv6006C_reg.h	316;"	d
+ADR_TM2_CURRENT_MILISECOND_TIME_VALUE	include/ssv6200_reg.h	174;"	d
+ADR_TM2_CURRENT_MILLISECOND_TIME_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	318;"	d
+ADR_TM2_DUMMY_BIT_0	include/ssv6200_reg.h	175;"	d
+ADR_TM2_DUMMY_BIT_1	include/ssv6200_reg.h	176;"	d
+ADR_TM2_MILISECOND_TIMER	include/ssv6200_reg.h	173;"	d
+ADR_TM2_MILLISECOND_TIMER	smac/hal/ssv6006c/ssv6006C_reg.h	317;"	d
+ADR_TM2_MILLISECOND_TIMER_PRESCALE	smac/hal/ssv6006c/ssv6006C_reg.h	319;"	d
+ADR_TM3_CURRENT_MILISECOND_TIME_VALUE	include/ssv6200_reg.h	178;"	d
+ADR_TM3_CURRENT_MILLISECOND_TIME_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	321;"	d
+ADR_TM3_DUMMY_BIT_0	include/ssv6200_reg.h	179;"	d
+ADR_TM3_DUMMY_BIT_1	include/ssv6200_reg.h	180;"	d
+ADR_TM3_MILISECOND_TIMER	include/ssv6200_reg.h	177;"	d
+ADR_TM3_MILLISECOND_TIMER	smac/hal/ssv6006c/ssv6006C_reg.h	320;"	d
+ADR_TM3_MILLISECOND_TIMER_PRESCALE	smac/hal/ssv6006c/ssv6006C_reg.h	322;"	d
+ADR_TRAP_HW_ID	include/ssv6200_reg.h	599;"	d
+ADR_TRAP_HW_ID	smac/hal/ssv6006c/ssv6006C_reg.h	720;"	d
+ADR_TRX_DUMMY_REGISTER	include/ssv6200_reg.h	1215;"	d
+ADR_TRX_ID_COUNT	include/ssv6200_reg.h	937;"	d
+ADR_TRX_ID_COUNT	smac/hal/ssv6006c/ssv6006C_reg.h	2115;"	d
+ADR_TRX_ID_THRESHOLD	include/ssv6200_reg.h	938;"	d
+ADR_TRX_ID_THRESHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	2116;"	d
+ADR_TRX_IQ_COMP_2G	smac/hal/ssv6006c/ssv6006C_reg.h	1660;"	d
+ADR_TRX_IQ_COMP_5G_0	smac/hal/ssv6006c/ssv6006C_reg.h	1661;"	d
+ADR_TRX_IQ_COMP_5G_1	smac/hal/ssv6006c/ssv6006C_reg.h	1662;"	d
+ADR_TRX_IQ_COMP_5G_2	smac/hal/ssv6006c/ssv6006C_reg.h	1663;"	d
+ADR_TRX_IQ_COMP_5G_3	smac/hal/ssv6006c/ssv6006C_reg.h	1664;"	d
+ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE	include/ssv6200_reg.h	150;"	d
+ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	300;"	d
+ADR_TU0_DUMMY_BIT_0	include/ssv6200_reg.h	151;"	d
+ADR_TU0_DUMMY_BIT_1	include/ssv6200_reg.h	152;"	d
+ADR_TU0_MICROSECOND_TIMER	include/ssv6200_reg.h	149;"	d
+ADR_TU0_MICROSECOND_TIMER	smac/hal/ssv6006c/ssv6006C_reg.h	299;"	d
+ADR_TU0_MICROSECOND_TIMER_LOCAL_PRESCALE	smac/hal/ssv6006c/ssv6006C_reg.h	301;"	d
+ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE	include/ssv6200_reg.h	154;"	d
+ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	303;"	d
+ADR_TU1_DUMMY_BIT_0	include/ssv6200_reg.h	155;"	d
+ADR_TU1_DUMMY_BIT_1	include/ssv6200_reg.h	156;"	d
+ADR_TU1_MICROSECOND_TIMER	include/ssv6200_reg.h	153;"	d
+ADR_TU1_MICROSECOND_TIMER	smac/hal/ssv6006c/ssv6006C_reg.h	302;"	d
+ADR_TU1_MICROSECOND_TIMER_LOCAL_PRESCALE	smac/hal/ssv6006c/ssv6006C_reg.h	304;"	d
+ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE	include/ssv6200_reg.h	158;"	d
+ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	306;"	d
+ADR_TU2_DUMMY_BIT_0	include/ssv6200_reg.h	159;"	d
+ADR_TU2_DUMMY_BIT_1	include/ssv6200_reg.h	160;"	d
+ADR_TU2_MICROSECOND_TIMER	include/ssv6200_reg.h	157;"	d
+ADR_TU2_MICROSECOND_TIMER	smac/hal/ssv6006c/ssv6006C_reg.h	305;"	d
+ADR_TU2_MICROSECOND_TIMER_LOCAL_PRESCALE	smac/hal/ssv6006c/ssv6006C_reg.h	307;"	d
+ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE	include/ssv6200_reg.h	162;"	d
+ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	309;"	d
+ADR_TU3_DUMMY_BIT_0	include/ssv6200_reg.h	163;"	d
+ADR_TU3_DUMMY_BIT_1	include/ssv6200_reg.h	164;"	d
+ADR_TU3_MICROSECOND_TIMER	include/ssv6200_reg.h	161;"	d
+ADR_TU3_MICROSECOND_TIMER	smac/hal/ssv6006c/ssv6006C_reg.h	308;"	d
+ADR_TU3_MICROSECOND_TIMER_LOCAL_PRESCALE	smac/hal/ssv6006c/ssv6006C_reg.h	310;"	d
+ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1293;"	d
+ADR_TURISMO_TRX_2_4G_LDO_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1294;"	d
+ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1302;"	d
+ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1304;"	d
+ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1303;"	d
+ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1305;"	d
+ADR_TURISMO_TRX_2_4G_RX_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1298;"	d
+ADR_TURISMO_TRX_2_4G_TRX_DUMMY_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1371;"	d
+ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1292;"	d
+ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1299;"	d
+ADR_TURISMO_TRX_2_4G_TX_PA_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1300;"	d
+ADR_TURISMO_TRX_2_4G_TX_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1301;"	d
+ADR_TURISMO_TRX_5G_CALIBRATION_GAIN_REGISTER1	smac/hal/ssv6006c/ssv6006C_reg.h	1422;"	d
+ADR_TURISMO_TRX_5G_CALIBRATION_TIMER_GAIN_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1421;"	d
+ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER1	smac/hal/ssv6006c/ssv6006C_reg.h	1397;"	d
+ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER10	smac/hal/ssv6006c/ssv6006C_reg.h	1406;"	d
+ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER11	smac/hal/ssv6006c/ssv6006C_reg.h	1407;"	d
+ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER12	smac/hal/ssv6006c/ssv6006C_reg.h	1408;"	d
+ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER13	smac/hal/ssv6006c/ssv6006C_reg.h	1409;"	d
+ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER14	smac/hal/ssv6006c/ssv6006C_reg.h	1410;"	d
+ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER15	smac/hal/ssv6006c/ssv6006C_reg.h	1411;"	d
+ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER16	smac/hal/ssv6006c/ssv6006C_reg.h	1412;"	d
+ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER17	smac/hal/ssv6006c/ssv6006C_reg.h	1413;"	d
+ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER18	smac/hal/ssv6006c/ssv6006C_reg.h	1414;"	d
+ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER19	smac/hal/ssv6006c/ssv6006C_reg.h	1415;"	d
+ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER2	smac/hal/ssv6006c/ssv6006C_reg.h	1398;"	d
+ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER20	smac/hal/ssv6006c/ssv6006C_reg.h	1416;"	d
+ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER21	smac/hal/ssv6006c/ssv6006C_reg.h	1417;"	d
+ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER3	smac/hal/ssv6006c/ssv6006C_reg.h	1399;"	d
+ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER4	smac/hal/ssv6006c/ssv6006C_reg.h	1400;"	d
+ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER5	smac/hal/ssv6006c/ssv6006C_reg.h	1401;"	d
+ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER6	smac/hal/ssv6006c/ssv6006C_reg.h	1402;"	d
+ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER7	smac/hal/ssv6006c/ssv6006C_reg.h	1403;"	d
+ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER8	smac/hal/ssv6006c/ssv6006C_reg.h	1404;"	d
+ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER9	smac/hal/ssv6006c/ssv6006C_reg.h	1405;"	d
+ADR_TURISMO_TRX_5G_LDO_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1376;"	d
+ADR_TURISMO_TRX_5G_MODE_DECODER_TIMER_REGISTER1	smac/hal/ssv6006c/ssv6006C_reg.h	1418;"	d
+ADR_TURISMO_TRX_5G_R2T_TIMER_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1420;"	d
+ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1381;"	d
+ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1383;"	d
+ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1382;"	d
+ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1384;"	d
+ADR_TURISMO_TRX_5G_RX_LNA_LOAD_SCA_CONTROL	smac/hal/ssv6006c/ssv6006C_reg.h	1429;"	d
+ADR_TURISMO_TRX_5G_RX_LNA_MATCHING_SCA_CONTROL	smac/hal/ssv6006c/ssv6006C_reg.h	1428;"	d
+ADR_TURISMO_TRX_5G_RX_REGISTER1	smac/hal/ssv6006c/ssv6006C_reg.h	1377;"	d
+ADR_TURISMO_TRX_5G_RX_REGISTER2	smac/hal/ssv6006c/ssv6006C_reg.h	1378;"	d
+ADR_TURISMO_TRX_5G_T2R_TIMER_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1419;"	d
+ADR_TURISMO_TRX_5G_TRX_DUMMY_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1423;"	d
+ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1375;"	d
+ADR_TURISMO_TRX_5G_TX_DAC_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1385;"	d
+ADR_TURISMO_TRX_5G_TX_FE_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1379;"	d
+ADR_TURISMO_TRX_5G_TX_PGA_CAPSW_CONTROL	smac/hal/ssv6006c/ssv6006C_reg.h	1430;"	d
+ADR_TURISMO_TRX_5G_TX_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1380;"	d
+ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER1	smac/hal/ssv6006c/ssv6006C_reg.h	1349;"	d
+ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER10	smac/hal/ssv6006c/ssv6006C_reg.h	1358;"	d
+ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER11	smac/hal/ssv6006c/ssv6006C_reg.h	1359;"	d
+ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER12	smac/hal/ssv6006c/ssv6006C_reg.h	1360;"	d
+ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER13	smac/hal/ssv6006c/ssv6006C_reg.h	1361;"	d
+ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER14	smac/hal/ssv6006c/ssv6006C_reg.h	1362;"	d
+ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER15	smac/hal/ssv6006c/ssv6006C_reg.h	1363;"	d
+ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER16	smac/hal/ssv6006c/ssv6006C_reg.h	1364;"	d
+ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER2	smac/hal/ssv6006c/ssv6006C_reg.h	1350;"	d
+ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER3	smac/hal/ssv6006c/ssv6006C_reg.h	1351;"	d
+ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER4	smac/hal/ssv6006c/ssv6006C_reg.h	1352;"	d
+ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER5	smac/hal/ssv6006c/ssv6006C_reg.h	1353;"	d
+ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER6	smac/hal/ssv6006c/ssv6006C_reg.h	1354;"	d
+ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER7	smac/hal/ssv6006c/ssv6006C_reg.h	1355;"	d
+ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER8	smac/hal/ssv6006c/ssv6006C_reg.h	1356;"	d
+ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER9	smac/hal/ssv6006c/ssv6006C_reg.h	1357;"	d
+ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1306;"	d
+ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1308;"	d
+ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1307;"	d
+ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1309;"	d
+ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1297;"	d
+ADR_TURISMO_TRX_BT_TX_DAC_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1312;"	d
+ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER0	smac/hal/ssv6006c/ssv6006C_reg.h	1369;"	d
+ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1	smac/hal/ssv6006c/ssv6006C_reg.h	1370;"	d
+ADR_TURISMO_TRX_CALIBRATION_TIMER_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1368;"	d
+ADR_TURISMO_TRX_DIGITAL_ADD_ON_0	smac/hal/ssv6006c/ssv6006C_reg.h	1431;"	d
+ADR_TURISMO_TRX_DIGITAL_ADD_ON_1	smac/hal/ssv6006c/ssv6006C_reg.h	1432;"	d
+ADR_TURISMO_TRX_DIGITAL_ADD_ON_2	smac/hal/ssv6006c/ssv6006C_reg.h	1433;"	d
+ADR_TURISMO_TRX_DIGITAL_ADD_ON_3	smac/hal/ssv6006c/ssv6006C_reg.h	1434;"	d
+ADR_TURISMO_TRX_DIGITAL_ADD_ON_4	smac/hal/ssv6006c/ssv6006C_reg.h	1435;"	d
+ADR_TURISMO_TRX_DIGITAL_ADD_ON_5	smac/hal/ssv6006c/ssv6006C_reg.h	1436;"	d
+ADR_TURISMO_TRX_DIGITAL_ADD_ON_6	smac/hal/ssv6006c/ssv6006C_reg.h	1437;"	d
+ADR_TURISMO_TRX_DPLL_CKT_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1326;"	d
+ADR_TURISMO_TRX_DPLL_FB_DIVISION__REGISTERS	smac/hal/ssv6006c/ssv6006C_reg.h	1327;"	d
+ADR_TURISMO_TRX_DPLL_TOP_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1325;"	d
+ADR_TURISMO_TRX_HS3W_CTRL1	smac/hal/ssv6006c/ssv6006C_reg.h	1454;"	d
+ADR_TURISMO_TRX_HS3W_CTRL2	smac/hal/ssv6006c/ssv6006C_reg.h	1455;"	d
+ADR_TURISMO_TRX_HS3W_CTRL3	smac/hal/ssv6006c/ssv6006C_reg.h	1456;"	d
+ADR_TURISMO_TRX_IO_REG_0	smac/hal/ssv6006c/ssv6006C_reg.h	1474;"	d
+ADR_TURISMO_TRX_IO_REG_1	smac/hal/ssv6006c/ssv6006C_reg.h	1475;"	d
+ADR_TURISMO_TRX_IO_REG_2	smac/hal/ssv6006c/ssv6006C_reg.h	1476;"	d
+ADR_TURISMO_TRX_MCU_REG_0	smac/hal/ssv6006c/ssv6006C_reg.h	1477;"	d
+ADR_TURISMO_TRX_MODE_DECODER_TIMER_REGISTER1	smac/hal/ssv6006c/ssv6006C_reg.h	1365;"	d
+ADR_TURISMO_TRX_MODE_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1291;"	d
+ADR_TURISMO_TRX_PMU_BT_CLK	smac/hal/ssv6006c/ssv6006C_reg.h	1473;"	d
+ADR_TURISMO_TRX_PMU_CTRL_REG	smac/hal/ssv6006c/ssv6006C_reg.h	1471;"	d
+ADR_TURISMO_TRX_PMU_RAM_00	smac/hal/ssv6006c/ssv6006C_reg.h	1478;"	d
+ADR_TURISMO_TRX_PMU_RAM_01	smac/hal/ssv6006c/ssv6006C_reg.h	1479;"	d
+ADR_TURISMO_TRX_PMU_RAM_02	smac/hal/ssv6006c/ssv6006C_reg.h	1480;"	d
+ADR_TURISMO_TRX_PMU_RAM_03	smac/hal/ssv6006c/ssv6006C_reg.h	1481;"	d
+ADR_TURISMO_TRX_PMU_RAM_04	smac/hal/ssv6006c/ssv6006C_reg.h	1482;"	d
+ADR_TURISMO_TRX_PMU_RAM_05	smac/hal/ssv6006c/ssv6006C_reg.h	1483;"	d
+ADR_TURISMO_TRX_PMU_RAM_06	smac/hal/ssv6006c/ssv6006C_reg.h	1484;"	d
+ADR_TURISMO_TRX_PMU_RAM_07	smac/hal/ssv6006c/ssv6006C_reg.h	1485;"	d
+ADR_TURISMO_TRX_PMU_RAM_08	smac/hal/ssv6006c/ssv6006C_reg.h	1486;"	d
+ADR_TURISMO_TRX_PMU_RAM_09	smac/hal/ssv6006c/ssv6006C_reg.h	1487;"	d
+ADR_TURISMO_TRX_PMU_RAM_10	smac/hal/ssv6006c/ssv6006C_reg.h	1488;"	d
+ADR_TURISMO_TRX_PMU_RAM_11	smac/hal/ssv6006c/ssv6006C_reg.h	1489;"	d
+ADR_TURISMO_TRX_PMU_RAM_12	smac/hal/ssv6006c/ssv6006C_reg.h	1490;"	d
+ADR_TURISMO_TRX_PMU_RAM_13	smac/hal/ssv6006c/ssv6006C_reg.h	1491;"	d
+ADR_TURISMO_TRX_PMU_RAM_14	smac/hal/ssv6006c/ssv6006C_reg.h	1492;"	d
+ADR_TURISMO_TRX_PMU_RAM_15	smac/hal/ssv6006c/ssv6006C_reg.h	1493;"	d
+ADR_TURISMO_TRX_PMU_RAM_16	smac/hal/ssv6006c/ssv6006C_reg.h	1494;"	d
+ADR_TURISMO_TRX_PMU_RAM_17	smac/hal/ssv6006c/ssv6006C_reg.h	1495;"	d
+ADR_TURISMO_TRX_PMU_RAM_18	smac/hal/ssv6006c/ssv6006C_reg.h	1496;"	d
+ADR_TURISMO_TRX_PMU_RAM_19	smac/hal/ssv6006c/ssv6006C_reg.h	1497;"	d
+ADR_TURISMO_TRX_PMU_RAM_20	smac/hal/ssv6006c/ssv6006C_reg.h	1498;"	d
+ADR_TURISMO_TRX_PMU_RAM_21	smac/hal/ssv6006c/ssv6006C_reg.h	1499;"	d
+ADR_TURISMO_TRX_PMU_RAM_22	smac/hal/ssv6006c/ssv6006C_reg.h	1500;"	d
+ADR_TURISMO_TRX_PMU_RAM_23	smac/hal/ssv6006c/ssv6006C_reg.h	1501;"	d
+ADR_TURISMO_TRX_PMU_RAM_24	smac/hal/ssv6006c/ssv6006C_reg.h	1502;"	d
+ADR_TURISMO_TRX_PMU_RAM_25	smac/hal/ssv6006c/ssv6006C_reg.h	1503;"	d
+ADR_TURISMO_TRX_PMU_RAM_26	smac/hal/ssv6006c/ssv6006C_reg.h	1504;"	d
+ADR_TURISMO_TRX_PMU_RAM_27	smac/hal/ssv6006c/ssv6006C_reg.h	1505;"	d
+ADR_TURISMO_TRX_PMU_RAM_28	smac/hal/ssv6006c/ssv6006C_reg.h	1506;"	d
+ADR_TURISMO_TRX_PMU_RAM_29	smac/hal/ssv6006c/ssv6006C_reg.h	1507;"	d
+ADR_TURISMO_TRX_PMU_RAM_30	smac/hal/ssv6006c/ssv6006C_reg.h	1508;"	d
+ADR_TURISMO_TRX_PMU_RAM_31	smac/hal/ssv6006c/ssv6006C_reg.h	1509;"	d
+ADR_TURISMO_TRX_PMU_REG_1	smac/hal/ssv6006c/ssv6006C_reg.h	1459;"	d
+ADR_TURISMO_TRX_PMU_REG_2	smac/hal/ssv6006c/ssv6006C_reg.h	1460;"	d
+ADR_TURISMO_TRX_PMU_REG_3	smac/hal/ssv6006c/ssv6006C_reg.h	1461;"	d
+ADR_TURISMO_TRX_PMU_REG_4	smac/hal/ssv6006c/ssv6006C_reg.h	1462;"	d
+ADR_TURISMO_TRX_PMU_REG_5	smac/hal/ssv6006c/ssv6006C_reg.h	1463;"	d
+ADR_TURISMO_TRX_PMU_REG_6	smac/hal/ssv6006c/ssv6006C_reg.h	1464;"	d
+ADR_TURISMO_TRX_PMU_RTC_REG_0	smac/hal/ssv6006c/ssv6006C_reg.h	1467;"	d
+ADR_TURISMO_TRX_PMU_RTC_REG_1	smac/hal/ssv6006c/ssv6006C_reg.h	1468;"	d
+ADR_TURISMO_TRX_PMU_RTC_REG_2	smac/hal/ssv6006c/ssv6006C_reg.h	1469;"	d
+ADR_TURISMO_TRX_PMU_RTC_REG_3	smac/hal/ssv6006c/ssv6006C_reg.h	1470;"	d
+ADR_TURISMO_TRX_PMU_SLEEP_REG_1	smac/hal/ssv6006c/ssv6006C_reg.h	1465;"	d
+ADR_TURISMO_TRX_PMU_SLEEP_REG_2	smac/hal/ssv6006c/ssv6006C_reg.h	1466;"	d
+ADR_TURISMO_TRX_PMU_STATE_REG	smac/hal/ssv6006c/ssv6006C_reg.h	1472;"	d
+ADR_TURISMO_TRX_READ_ONLY_FLAGS_ADC	smac/hal/ssv6006c/ssv6006C_reg.h	1372;"	d
+ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_1	smac/hal/ssv6006c/ssv6006C_reg.h	1373;"	d
+ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_2	smac/hal/ssv6006c/ssv6006C_reg.h	1374;"	d
+ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_1	smac/hal/ssv6006c/ssv6006C_reg.h	1425;"	d
+ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_2	smac/hal/ssv6006c/ssv6006C_reg.h	1426;"	d
+ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_3	smac/hal/ssv6006c/ssv6006C_reg.h	1427;"	d
+ADR_TURISMO_TRX_RF_D_CAL_TOP_0	smac/hal/ssv6006c/ssv6006C_reg.h	1444;"	d
+ADR_TURISMO_TRX_RF_D_CAL_TOP_1	smac/hal/ssv6006c/ssv6006C_reg.h	1445;"	d
+ADR_TURISMO_TRX_RF_D_CAL_TOP_2	smac/hal/ssv6006c/ssv6006C_reg.h	1446;"	d
+ADR_TURISMO_TRX_RF_D_CAL_TOP_3	smac/hal/ssv6006c/ssv6006C_reg.h	1447;"	d
+ADR_TURISMO_TRX_RF_D_CAL_TOP_4	smac/hal/ssv6006c/ssv6006C_reg.h	1448;"	d
+ADR_TURISMO_TRX_RF_D_CAL_TOP_5	smac/hal/ssv6006c/ssv6006C_reg.h	1449;"	d
+ADR_TURISMO_TRX_RF_D_CAL_TOP_6	smac/hal/ssv6006c/ssv6006C_reg.h	1450;"	d
+ADR_TURISMO_TRX_RF_D_CAL_TOP_7	smac/hal/ssv6006c/ssv6006C_reg.h	1451;"	d
+ADR_TURISMO_TRX_RF_D_CAL_TOP_8	smac/hal/ssv6006c/ssv6006C_reg.h	1452;"	d
+ADR_TURISMO_TRX_RF_D_CAL_TOP_9	smac/hal/ssv6006c/ssv6006C_reg.h	1453;"	d
+ADR_TURISMO_TRX_RF_D_MODE_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	1457;"	d
+ADR_TURISMO_TRX_RX_DC_CAL_RESULT	smac/hal/ssv6006c/ssv6006C_reg.h	1458;"	d
+ADR_TURISMO_TRX_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE	smac/hal/ssv6006c/ssv6006C_reg.h	1316;"	d
+ADR_TURISMO_TRX_SX_2_4GB_AAC	smac/hal/ssv6006c/ssv6006C_reg.h	1323;"	d
+ADR_TURISMO_TRX_SX_2_4GB_DIV_SDM	smac/hal/ssv6006c/ssv6006C_reg.h	1321;"	d
+ADR_TURISMO_TRX_SX_2_4GB_FRACTIONAL_AND_INTEGER_8BITS	smac/hal/ssv6006c/ssv6006C_reg.h	1315;"	d
+ADR_TURISMO_TRX_SX_2_4GB_LPF	smac/hal/ssv6006c/ssv6006C_reg.h	1318;"	d
+ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_	smac/hal/ssv6006c/ssv6006C_reg.h	1317;"	d
+ADR_TURISMO_TRX_SX_2_4GB_SBCAL	smac/hal/ssv6006c/ssv6006C_reg.h	1322;"	d
+ADR_TURISMO_TRX_SX_2_4GB_TTL	smac/hal/ssv6006c/ssv6006C_reg.h	1324;"	d
+ADR_TURISMO_TRX_SX_2_4GB_VCO	smac/hal/ssv6006c/ssv6006C_reg.h	1319;"	d
+ADR_TURISMO_TRX_SX_2_4GB_VCOBF	smac/hal/ssv6006c/ssv6006C_reg.h	1320;"	d
+ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1314;"	d
+ADR_TURISMO_TRX_SX_5GB_DIV_SDM	smac/hal/ssv6006c/ssv6006C_reg.h	1393;"	d
+ADR_TURISMO_TRX_SX_5GB_DUMMY_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1424;"	d
+ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER	smac/hal/ssv6006c/ssv6006C_reg.h	1388;"	d
+ADR_TURISMO_TRX_SX_5GB_FRACTIONAL_AND_INTEGER_8BITS	smac/hal/ssv6006c/ssv6006C_reg.h	1386;"	d
+ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1389;"	d
+ADR_TURISMO_TRX_SX_5GB_LOGEN_CALIBRATION	smac/hal/ssv6006c/ssv6006C_reg.h	1396;"	d
+ADR_TURISMO_TRX_SX_5GB_LPF_TTL	smac/hal/ssv6006c/ssv6006C_reg.h	1391;"	d
+ADR_TURISMO_TRX_SX_5GB_PFD_CHP_	smac/hal/ssv6006c/ssv6006C_reg.h	1390;"	d
+ADR_TURISMO_TRX_SX_5GB_REGISTER_INT3BIT___CH_TABLE	smac/hal/ssv6006c/ssv6006C_reg.h	1387;"	d
+ADR_TURISMO_TRX_SX_5GB_SBCAL	smac/hal/ssv6006c/ssv6006C_reg.h	1394;"	d
+ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION	smac/hal/ssv6006c/ssv6006C_reg.h	1395;"	d
+ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN	smac/hal/ssv6006c/ssv6006C_reg.h	1392;"	d
+ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER	smac/hal/ssv6006c/ssv6006C_reg.h	1313;"	d
+ADR_TURISMO_TRX_TX_BW20_FIR_COEF_00	smac/hal/ssv6006c/ssv6006C_reg.h	1438;"	d
+ADR_TURISMO_TRX_TX_BW20_FIR_COEF_01	smac/hal/ssv6006c/ssv6006C_reg.h	1439;"	d
+ADR_TURISMO_TRX_TX_BW20_FIR_COEF_02	smac/hal/ssv6006c/ssv6006C_reg.h	1440;"	d
+ADR_TURISMO_TRX_TX_BW20_FIR_COEF_03	smac/hal/ssv6006c/ssv6006C_reg.h	1441;"	d
+ADR_TURISMO_TRX_TX_BW20_FIR_COEF_04	smac/hal/ssv6006c/ssv6006C_reg.h	1442;"	d
+ADR_TURISMO_TRX_TX_BW20_FIR_COEF_05	smac/hal/ssv6006c/ssv6006C_reg.h	1443;"	d
+ADR_TURISMO_TRX_VER	smac/hal/ssv6006c/ssv6006_mac.h	23;"	d
+ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1310;"	d
+ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER1	smac/hal/ssv6006c/ssv6006C_reg.h	1328;"	d
+ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER10	smac/hal/ssv6006c/ssv6006C_reg.h	1337;"	d
+ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER11	smac/hal/ssv6006c/ssv6006C_reg.h	1338;"	d
+ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER12	smac/hal/ssv6006c/ssv6006C_reg.h	1339;"	d
+ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER13	smac/hal/ssv6006c/ssv6006C_reg.h	1340;"	d
+ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER14	smac/hal/ssv6006c/ssv6006C_reg.h	1341;"	d
+ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER15	smac/hal/ssv6006c/ssv6006C_reg.h	1342;"	d
+ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER16	smac/hal/ssv6006c/ssv6006C_reg.h	1343;"	d
+ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER17	smac/hal/ssv6006c/ssv6006C_reg.h	1344;"	d
+ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER18	smac/hal/ssv6006c/ssv6006C_reg.h	1345;"	d
+ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER19	smac/hal/ssv6006c/ssv6006C_reg.h	1346;"	d
+ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER2	smac/hal/ssv6006c/ssv6006C_reg.h	1329;"	d
+ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER20	smac/hal/ssv6006c/ssv6006C_reg.h	1347;"	d
+ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER21	smac/hal/ssv6006c/ssv6006C_reg.h	1348;"	d
+ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER3	smac/hal/ssv6006c/ssv6006C_reg.h	1330;"	d
+ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER4	smac/hal/ssv6006c/ssv6006C_reg.h	1331;"	d
+ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER5	smac/hal/ssv6006c/ssv6006C_reg.h	1332;"	d
+ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER6	smac/hal/ssv6006c/ssv6006C_reg.h	1333;"	d
+ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER7	smac/hal/ssv6006c/ssv6006C_reg.h	1334;"	d
+ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER8	smac/hal/ssv6006c/ssv6006C_reg.h	1335;"	d
+ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER9	smac/hal/ssv6006c/ssv6006C_reg.h	1336;"	d
+ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1295;"	d
+ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1296;"	d
+ADR_TURISMO_TRX_WIFI_R2T_TIMER_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1367;"	d
+ADR_TURISMO_TRX_WIFI_T2R_TIMER_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1366;"	d
+ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1311;"	d
+ADR_TWIM_DELAY_ACK	smac/hal/ssv6006c/ssv6006C_reg.h	425;"	d
+ADR_TWIM_DEV_A	smac/hal/ssv6006c/ssv6006C_reg.h	420;"	d
+ADR_TWIM_EN	smac/hal/ssv6006c/ssv6006C_reg.h	413;"	d
+ADR_TWIM_INTERRUPT	smac/hal/ssv6006c/ssv6006C_reg.h	416;"	d
+ADR_TWIM_INTERRUPT_EN	smac/hal/ssv6006c/ssv6006C_reg.h	415;"	d
+ADR_TWIM_INTERRUPT_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	417;"	d
+ADR_TWIM_PSCL	smac/hal/ssv6006c/ssv6006C_reg.h	423;"	d
+ADR_TWIM_RXD_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	422;"	d
+ADR_TWIM_STATUS_RECORD_0	smac/hal/ssv6006c/ssv6006C_reg.h	418;"	d
+ADR_TWIM_STATUS_RECORD_1	smac/hal/ssv6006c/ssv6006C_reg.h	419;"	d
+ADR_TWIM_STATUS_SETTING	smac/hal/ssv6006c/ssv6006C_reg.h	414;"	d
+ADR_TWIM_TRANS_PSDA	smac/hal/ssv6006c/ssv6006C_reg.h	424;"	d
+ADR_TWIM_TXD_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	421;"	d
+ADR_TXFID_INCREASE	include/ssv6200_reg.h	420;"	d
+ADR_TXFID_INCREASE	smac/hal/ssv6006c/ssv6006C_reg.h	563;"	d
+ADR_TXQ0_MTX_Q_AIFSN	include/ssv6200_reg.h	652;"	d
+ADR_TXQ0_MTX_Q_AIFSN	smac/hal/ssv6006c/ssv6006C_reg.h	791;"	d
+ADR_TXQ0_MTX_Q_BKF_CNT	include/ssv6200_reg.h	653;"	d
+ADR_TXQ0_MTX_Q_BKF_CNT_DBG	smac/hal/ssv6006c/ssv6006C_reg.h	792;"	d
+ADR_TXQ0_MTX_Q_HWDBG	smac/hal/ssv6006c/ssv6006C_reg.h	793;"	d
+ADR_TXQ0_MTX_Q_HWDBG2	smac/hal/ssv6006c/ssv6006C_reg.h	794;"	d
+ADR_TXQ0_MTX_Q_ID_MAP_L	include/ssv6200_reg.h	655;"	d
+ADR_TXQ0_MTX_Q_MISC_EN	include/ssv6200_reg.h	651;"	d
+ADR_TXQ0_MTX_Q_MISC_EN	smac/hal/ssv6006c/ssv6006C_reg.h	790;"	d
+ADR_TXQ0_MTX_Q_RC_LIMIT	include/ssv6200_reg.h	654;"	d
+ADR_TXQ0_MTX_Q_TXOP_CH_THD	include/ssv6200_reg.h	656;"	d
+ADR_TXQ0_MTX_Q_TXOP_OV_THD	include/ssv6200_reg.h	657;"	d
+ADR_TXQ1_MTX_Q_AIFSN	include/ssv6200_reg.h	659;"	d
+ADR_TXQ1_MTX_Q_AIFSN	smac/hal/ssv6006c/ssv6006C_reg.h	796;"	d
+ADR_TXQ1_MTX_Q_BKF_CNT	include/ssv6200_reg.h	660;"	d
+ADR_TXQ1_MTX_Q_BKF_CNT_DBG	smac/hal/ssv6006c/ssv6006C_reg.h	797;"	d
+ADR_TXQ1_MTX_Q_HWDBG	smac/hal/ssv6006c/ssv6006C_reg.h	798;"	d
+ADR_TXQ1_MTX_Q_HWDBG2	smac/hal/ssv6006c/ssv6006C_reg.h	799;"	d
+ADR_TXQ1_MTX_Q_ID_MAP_L	include/ssv6200_reg.h	662;"	d
+ADR_TXQ1_MTX_Q_MISC_EN	include/ssv6200_reg.h	658;"	d
+ADR_TXQ1_MTX_Q_MISC_EN	smac/hal/ssv6006c/ssv6006C_reg.h	795;"	d
+ADR_TXQ1_MTX_Q_RC_LIMIT	include/ssv6200_reg.h	661;"	d
+ADR_TXQ1_MTX_Q_TXOP_CH_THD	include/ssv6200_reg.h	663;"	d
+ADR_TXQ1_MTX_Q_TXOP_OV_THD	include/ssv6200_reg.h	664;"	d
+ADR_TXQ2_MTX_Q_AIFSN	include/ssv6200_reg.h	666;"	d
+ADR_TXQ2_MTX_Q_AIFSN	smac/hal/ssv6006c/ssv6006C_reg.h	801;"	d
+ADR_TXQ2_MTX_Q_BKF_CNT	include/ssv6200_reg.h	667;"	d
+ADR_TXQ2_MTX_Q_BKF_CNT_DBG	smac/hal/ssv6006c/ssv6006C_reg.h	802;"	d
+ADR_TXQ2_MTX_Q_HWDBG	smac/hal/ssv6006c/ssv6006C_reg.h	803;"	d
+ADR_TXQ2_MTX_Q_HWDBG2	smac/hal/ssv6006c/ssv6006C_reg.h	804;"	d
+ADR_TXQ2_MTX_Q_ID_MAP_L	include/ssv6200_reg.h	669;"	d
+ADR_TXQ2_MTX_Q_MISC_EN	include/ssv6200_reg.h	665;"	d
+ADR_TXQ2_MTX_Q_MISC_EN	smac/hal/ssv6006c/ssv6006C_reg.h	800;"	d
+ADR_TXQ2_MTX_Q_RC_LIMIT	include/ssv6200_reg.h	668;"	d
+ADR_TXQ2_MTX_Q_TXOP_CH_THD	include/ssv6200_reg.h	670;"	d
+ADR_TXQ2_MTX_Q_TXOP_OV_THD	include/ssv6200_reg.h	671;"	d
+ADR_TXQ3_MTX_Q_AIFSN	include/ssv6200_reg.h	673;"	d
+ADR_TXQ3_MTX_Q_AIFSN	smac/hal/ssv6006c/ssv6006C_reg.h	806;"	d
+ADR_TXQ3_MTX_Q_BKF_CNT	include/ssv6200_reg.h	674;"	d
+ADR_TXQ3_MTX_Q_BKF_CNT_DBG	smac/hal/ssv6006c/ssv6006C_reg.h	807;"	d
+ADR_TXQ3_MTX_Q_HWDBG	smac/hal/ssv6006c/ssv6006C_reg.h	808;"	d
+ADR_TXQ3_MTX_Q_HWDBG2	smac/hal/ssv6006c/ssv6006C_reg.h	809;"	d
+ADR_TXQ3_MTX_Q_ID_MAP_L	include/ssv6200_reg.h	676;"	d
+ADR_TXQ3_MTX_Q_MISC_EN	include/ssv6200_reg.h	672;"	d
+ADR_TXQ3_MTX_Q_MISC_EN	smac/hal/ssv6006c/ssv6006C_reg.h	805;"	d
+ADR_TXQ3_MTX_Q_RC_LIMIT	include/ssv6200_reg.h	675;"	d
+ADR_TXQ3_MTX_Q_TXOP_CH_THD	include/ssv6200_reg.h	677;"	d
+ADR_TXQ3_MTX_Q_TXOP_OV_THD	include/ssv6200_reg.h	678;"	d
+ADR_TXQ4_MTX_Q_AIFSN	include/ssv6200_reg.h	680;"	d
+ADR_TXQ4_MTX_Q_AIFSN	smac/hal/ssv6006c/ssv6006C_reg.h	811;"	d
+ADR_TXQ4_MTX_Q_BKF_CNT	include/ssv6200_reg.h	681;"	d
+ADR_TXQ4_MTX_Q_BKF_CNT_DBG	smac/hal/ssv6006c/ssv6006C_reg.h	812;"	d
+ADR_TXQ4_MTX_Q_HWDBG	smac/hal/ssv6006c/ssv6006C_reg.h	813;"	d
+ADR_TXQ4_MTX_Q_HWDBG2	smac/hal/ssv6006c/ssv6006C_reg.h	814;"	d
+ADR_TXQ4_MTX_Q_ID_MAP_L	include/ssv6200_reg.h	683;"	d
+ADR_TXQ4_MTX_Q_MISC_EN	include/ssv6200_reg.h	679;"	d
+ADR_TXQ4_MTX_Q_MISC_EN	smac/hal/ssv6006c/ssv6006C_reg.h	810;"	d
+ADR_TXQ4_MTX_Q_RC_LIMIT	include/ssv6200_reg.h	682;"	d
+ADR_TXQ4_MTX_Q_TXOP_CH_THD	include/ssv6200_reg.h	684;"	d
+ADR_TXQ4_MTX_Q_TXOP_OV_THD	include/ssv6200_reg.h	685;"	d
+ADR_TXQ5_MTX_Q_AIFSN	smac/hal/ssv6006c/ssv6006C_reg.h	816;"	d
+ADR_TXQ5_MTX_Q_BKF_CNT_DBG	smac/hal/ssv6006c/ssv6006C_reg.h	817;"	d
+ADR_TXQ5_MTX_Q_HWDBG	smac/hal/ssv6006c/ssv6006C_reg.h	818;"	d
+ADR_TXQ5_MTX_Q_HWDBG2	smac/hal/ssv6006c/ssv6006C_reg.h	819;"	d
+ADR_TXQ5_MTX_Q_MISC_EN	smac/hal/ssv6006c/ssv6006C_reg.h	815;"	d
+ADR_TX_11B_EN_CNT	include/ssv6200_reg.h	1059;"	d
+ADR_TX_11B_EN_CNT_RST_N	include/ssv6200_reg.h	1058;"	d
+ADR_TX_11B_FIL_COEF_00	include/ssv6200_reg.h	1015;"	d
+ADR_TX_11B_FIL_COEF_01	include/ssv6200_reg.h	1016;"	d
+ADR_TX_11B_FIL_COEF_02	include/ssv6200_reg.h	1017;"	d
+ADR_TX_11B_FIL_COEF_03	include/ssv6200_reg.h	1018;"	d
+ADR_TX_11B_FIL_COEF_04	include/ssv6200_reg.h	1019;"	d
+ADR_TX_11B_FIL_COEF_05	include/ssv6200_reg.h	1020;"	d
+ADR_TX_11B_FIL_COEF_06	include/ssv6200_reg.h	1021;"	d
+ADR_TX_11B_FIL_COEF_07	include/ssv6200_reg.h	1022;"	d
+ADR_TX_11B_FIL_COEF_08	include/ssv6200_reg.h	1023;"	d
+ADR_TX_11B_FIL_COEF_09	include/ssv6200_reg.h	1024;"	d
+ADR_TX_11B_FIL_COEF_10	include/ssv6200_reg.h	1025;"	d
+ADR_TX_11B_FIL_COEF_11	include/ssv6200_reg.h	1026;"	d
+ADR_TX_11B_FIL_COEF_12	include/ssv6200_reg.h	1027;"	d
+ADR_TX_11B_FIL_COEF_13	include/ssv6200_reg.h	1028;"	d
+ADR_TX_11B_FIL_COEF_14	include/ssv6200_reg.h	1029;"	d
+ADR_TX_11B_FIL_COEF_15	include/ssv6200_reg.h	1030;"	d
+ADR_TX_11B_FIL_COEF_16	include/ssv6200_reg.h	1031;"	d
+ADR_TX_11B_FIL_COEF_17	include/ssv6200_reg.h	1032;"	d
+ADR_TX_11B_FIL_COEF_18	include/ssv6200_reg.h	1033;"	d
+ADR_TX_11B_FIL_COEF_19	include/ssv6200_reg.h	1034;"	d
+ADR_TX_11B_FIL_COEF_20	include/ssv6200_reg.h	1035;"	d
+ADR_TX_11B_FIL_COEF_21	include/ssv6200_reg.h	1036;"	d
+ADR_TX_11B_FIL_COEF_22	include/ssv6200_reg.h	1037;"	d
+ADR_TX_11B_FIL_COEF_23	include/ssv6200_reg.h	1038;"	d
+ADR_TX_11B_FIL_COEF_24	include/ssv6200_reg.h	1039;"	d
+ADR_TX_11B_FIL_COEF_25	include/ssv6200_reg.h	1040;"	d
+ADR_TX_11B_FIL_COEF_26	include/ssv6200_reg.h	1041;"	d
+ADR_TX_11B_FIL_COEF_27	include/ssv6200_reg.h	1042;"	d
+ADR_TX_11B_FIL_COEF_28	include/ssv6200_reg.h	1043;"	d
+ADR_TX_11B_FIL_COEF_29	include/ssv6200_reg.h	1044;"	d
+ADR_TX_11B_FIL_COEF_30	include/ssv6200_reg.h	1045;"	d
+ADR_TX_11B_FIL_COEF_31	include/ssv6200_reg.h	1046;"	d
+ADR_TX_11B_FIL_COEF_32	include/ssv6200_reg.h	1047;"	d
+ADR_TX_11B_FIL_COEF_33	include/ssv6200_reg.h	1048;"	d
+ADR_TX_11B_FIL_COEF_34	include/ssv6200_reg.h	1049;"	d
+ADR_TX_11B_FIL_COEF_35	include/ssv6200_reg.h	1050;"	d
+ADR_TX_11B_FIL_COEF_36	include/ssv6200_reg.h	1051;"	d
+ADR_TX_11B_FIL_COEF_37	include/ssv6200_reg.h	1052;"	d
+ADR_TX_11B_FIL_COEF_38	include/ssv6200_reg.h	1053;"	d
+ADR_TX_11B_FIL_COEF_39	include/ssv6200_reg.h	1054;"	d
+ADR_TX_11B_FIL_COEF_40	include/ssv6200_reg.h	1055;"	d
+ADR_TX_11B_PKT_GEN_CNT	include/ssv6200_reg.h	1060;"	d
+ADR_TX_11B_PLCP	include/ssv6200_reg.h	1056;"	d
+ADR_TX_11B_RAMP	include/ssv6200_reg.h	1057;"	d
+ADR_TX_11GN_PKT_GEN_CNT	include/ssv6200_reg.h	1088;"	d
+ADR_TX_11GN_PLCP	include/ssv6200_reg.h	1087;"	d
+ADR_TX_11GN_PLCP_CRC_ERR_CNT	include/ssv6200_reg.h	1089;"	d
+ADR_TX_11GN_RAMP	include/ssv6200_reg.h	1086;"	d
+ADR_TX_ACK_POLICY_0_0	include/ssv6200_reg.h	689;"	d
+ADR_TX_ACK_POLICY_0_0	smac/hal/ssv6006c/ssv6006C_reg.h	903;"	d
+ADR_TX_ACK_POLICY_0_1	include/ssv6200_reg.h	691;"	d
+ADR_TX_ACK_POLICY_0_1	smac/hal/ssv6006c/ssv6006C_reg.h	905;"	d
+ADR_TX_ACK_POLICY_0_2	include/ssv6200_reg.h	693;"	d
+ADR_TX_ACK_POLICY_0_2	smac/hal/ssv6006c/ssv6006C_reg.h	907;"	d
+ADR_TX_ACK_POLICY_0_3	include/ssv6200_reg.h	695;"	d
+ADR_TX_ACK_POLICY_0_3	smac/hal/ssv6006c/ssv6006C_reg.h	909;"	d
+ADR_TX_ACK_POLICY_0_4	include/ssv6200_reg.h	697;"	d
+ADR_TX_ACK_POLICY_0_4	smac/hal/ssv6006c/ssv6006C_reg.h	911;"	d
+ADR_TX_ACK_POLICY_0_5	include/ssv6200_reg.h	699;"	d
+ADR_TX_ACK_POLICY_0_5	smac/hal/ssv6006c/ssv6006C_reg.h	913;"	d
+ADR_TX_ACK_POLICY_0_6	include/ssv6200_reg.h	701;"	d
+ADR_TX_ACK_POLICY_0_6	smac/hal/ssv6006c/ssv6006C_reg.h	915;"	d
+ADR_TX_ACK_POLICY_0_7	include/ssv6200_reg.h	703;"	d
+ADR_TX_ACK_POLICY_0_7	smac/hal/ssv6006c/ssv6006C_reg.h	917;"	d
+ADR_TX_ACK_POLICY_1_0	include/ssv6200_reg.h	708;"	d
+ADR_TX_ACK_POLICY_1_0	smac/hal/ssv6006c/ssv6006C_reg.h	922;"	d
+ADR_TX_ACK_POLICY_1_1	include/ssv6200_reg.h	710;"	d
+ADR_TX_ACK_POLICY_1_1	smac/hal/ssv6006c/ssv6006C_reg.h	924;"	d
+ADR_TX_ACK_POLICY_1_2	include/ssv6200_reg.h	712;"	d
+ADR_TX_ACK_POLICY_1_2	smac/hal/ssv6006c/ssv6006C_reg.h	926;"	d
+ADR_TX_ACK_POLICY_1_3	include/ssv6200_reg.h	714;"	d
+ADR_TX_ACK_POLICY_1_3	smac/hal/ssv6006c/ssv6006C_reg.h	928;"	d
+ADR_TX_ACK_POLICY_1_4	include/ssv6200_reg.h	716;"	d
+ADR_TX_ACK_POLICY_1_4	smac/hal/ssv6006c/ssv6006C_reg.h	930;"	d
+ADR_TX_ACK_POLICY_1_5	include/ssv6200_reg.h	718;"	d
+ADR_TX_ACK_POLICY_1_5	smac/hal/ssv6006c/ssv6006C_reg.h	932;"	d
+ADR_TX_ACK_POLICY_1_6	include/ssv6200_reg.h	720;"	d
+ADR_TX_ACK_POLICY_1_6	smac/hal/ssv6006c/ssv6006C_reg.h	934;"	d
+ADR_TX_ACK_POLICY_1_7	include/ssv6200_reg.h	722;"	d
+ADR_TX_ACK_POLICY_1_7	smac/hal/ssv6006c/ssv6006C_reg.h	936;"	d
+ADR_TX_ACK_POLICY_2_0	smac/hal/ssv6006c/ssv6006C_reg.h	1029;"	d
+ADR_TX_ACK_POLICY_2_1	smac/hal/ssv6006c/ssv6006C_reg.h	1031;"	d
+ADR_TX_ACK_POLICY_2_2	smac/hal/ssv6006c/ssv6006C_reg.h	1033;"	d
+ADR_TX_ACK_POLICY_2_3	smac/hal/ssv6006c/ssv6006C_reg.h	1035;"	d
+ADR_TX_ACK_POLICY_2_4	smac/hal/ssv6006c/ssv6006C_reg.h	1037;"	d
+ADR_TX_ACK_POLICY_2_5	smac/hal/ssv6006c/ssv6006C_reg.h	1039;"	d
+ADR_TX_ACK_POLICY_2_6	smac/hal/ssv6006c/ssv6006C_reg.h	1041;"	d
+ADR_TX_ACK_POLICY_2_7	smac/hal/ssv6006c/ssv6006C_reg.h	1043;"	d
+ADR_TX_ACK_POLICY_3_0	smac/hal/ssv6006c/ssv6006C_reg.h	1048;"	d
+ADR_TX_ACK_POLICY_3_1	smac/hal/ssv6006c/ssv6006C_reg.h	1050;"	d
+ADR_TX_ACK_POLICY_3_2	smac/hal/ssv6006c/ssv6006C_reg.h	1052;"	d
+ADR_TX_ACK_POLICY_3_3	smac/hal/ssv6006c/ssv6006C_reg.h	1054;"	d
+ADR_TX_ACK_POLICY_3_4	smac/hal/ssv6006c/ssv6006C_reg.h	1056;"	d
+ADR_TX_ACK_POLICY_3_5	smac/hal/ssv6006c/ssv6006C_reg.h	1058;"	d
+ADR_TX_ACK_POLICY_3_6	smac/hal/ssv6006c/ssv6006C_reg.h	1060;"	d
+ADR_TX_ACK_POLICY_3_7	smac/hal/ssv6006c/ssv6006C_reg.h	1062;"	d
+ADR_TX_ACK_POLICY_4_0	smac/hal/ssv6006c/ssv6006C_reg.h	1067;"	d
+ADR_TX_ACK_POLICY_4_1	smac/hal/ssv6006c/ssv6006C_reg.h	1069;"	d
+ADR_TX_ACK_POLICY_4_2	smac/hal/ssv6006c/ssv6006C_reg.h	1071;"	d
+ADR_TX_ACK_POLICY_4_3	smac/hal/ssv6006c/ssv6006C_reg.h	1073;"	d
+ADR_TX_ACK_POLICY_4_4	smac/hal/ssv6006c/ssv6006C_reg.h	1075;"	d
+ADR_TX_ACK_POLICY_4_5	smac/hal/ssv6006c/ssv6006C_reg.h	1077;"	d
+ADR_TX_ACK_POLICY_4_6	smac/hal/ssv6006c/ssv6006C_reg.h	1079;"	d
+ADR_TX_ACK_POLICY_4_7	smac/hal/ssv6006c/ssv6006C_reg.h	1081;"	d
+ADR_TX_ACK_POLICY_5_0	smac/hal/ssv6006c/ssv6006C_reg.h	1086;"	d
+ADR_TX_ACK_POLICY_5_1	smac/hal/ssv6006c/ssv6006C_reg.h	1088;"	d
+ADR_TX_ACK_POLICY_5_2	smac/hal/ssv6006c/ssv6006C_reg.h	1090;"	d
+ADR_TX_ACK_POLICY_5_3	smac/hal/ssv6006c/ssv6006C_reg.h	1092;"	d
+ADR_TX_ACK_POLICY_5_4	smac/hal/ssv6006c/ssv6006C_reg.h	1094;"	d
+ADR_TX_ACK_POLICY_5_5	smac/hal/ssv6006c/ssv6006C_reg.h	1096;"	d
+ADR_TX_ACK_POLICY_5_6	smac/hal/ssv6006c/ssv6006C_reg.h	1098;"	d
+ADR_TX_ACK_POLICY_5_7	smac/hal/ssv6006c/ssv6006C_reg.h	1100;"	d
+ADR_TX_ACK_POLICY_6_0	smac/hal/ssv6006c/ssv6006C_reg.h	1105;"	d
+ADR_TX_ACK_POLICY_6_1	smac/hal/ssv6006c/ssv6006C_reg.h	1107;"	d
+ADR_TX_ACK_POLICY_6_2	smac/hal/ssv6006c/ssv6006C_reg.h	1109;"	d
+ADR_TX_ACK_POLICY_6_3	smac/hal/ssv6006c/ssv6006C_reg.h	1111;"	d
+ADR_TX_ACK_POLICY_6_4	smac/hal/ssv6006c/ssv6006C_reg.h	1113;"	d
+ADR_TX_ACK_POLICY_6_5	smac/hal/ssv6006c/ssv6006C_reg.h	1115;"	d
+ADR_TX_ACK_POLICY_6_6	smac/hal/ssv6006c/ssv6006C_reg.h	1117;"	d
+ADR_TX_ACK_POLICY_6_7	smac/hal/ssv6006c/ssv6006C_reg.h	1119;"	d
+ADR_TX_ACK_POLICY_7_0	smac/hal/ssv6006c/ssv6006C_reg.h	1124;"	d
+ADR_TX_ACK_POLICY_7_1	smac/hal/ssv6006c/ssv6006C_reg.h	1126;"	d
+ADR_TX_ACK_POLICY_7_2	smac/hal/ssv6006c/ssv6006C_reg.h	1128;"	d
+ADR_TX_ACK_POLICY_7_3	smac/hal/ssv6006c/ssv6006C_reg.h	1130;"	d
+ADR_TX_ACK_POLICY_7_4	smac/hal/ssv6006c/ssv6006C_reg.h	1132;"	d
+ADR_TX_ACK_POLICY_7_5	smac/hal/ssv6006c/ssv6006C_reg.h	1134;"	d
+ADR_TX_ACK_POLICY_7_6	smac/hal/ssv6006c/ssv6006C_reg.h	1136;"	d
+ADR_TX_ACK_POLICY_7_7	smac/hal/ssv6006c/ssv6006C_reg.h	1138;"	d
+ADR_TX_ALLOC	include/ssv6200_reg.h	319;"	d
+ADR_TX_ALLOC_SET	include/ssv6200_reg.h	318;"	d
+ADR_TX_COMPENSATION_CONTROL	include/ssv6200_reg.h	1139;"	d
+ADR_TX_DAC_REGISTER	include/ssv6200_reg.h	1193;"	d
+ADR_TX_DROP_COUNT	smac/hal/ssv6006c/ssv6006C_reg.h	594;"	d
+ADR_TX_ERROR_RECEOVERY	smac/hal/ssv6006c/ssv6006C_reg.h	562;"	d
+ADR_TX_ETHER_TYPE_0	include/ssv6200_reg.h	424;"	d
+ADR_TX_ETHER_TYPE_0	smac/hal/ssv6006c/ssv6006C_reg.h	572;"	d
+ADR_TX_ETHER_TYPE_1	include/ssv6200_reg.h	425;"	d
+ADR_TX_ETHER_TYPE_1	smac/hal/ssv6006c/ssv6006C_reg.h	573;"	d
+ADR_TX_FE_REGISTER	include/ssv6200_reg.h	1185;"	d
+ADR_TX_FLOW_0	include/ssv6200_reg.h	417;"	d
+ADR_TX_FLOW_0	smac/hal/ssv6006c/ssv6006C_reg.h	557;"	d
+ADR_TX_FLOW_1	include/ssv6200_reg.h	418;"	d
+ADR_TX_FLOW_1	smac/hal/ssv6006c/ssv6006C_reg.h	558;"	d
+ADR_TX_GAIN_FACTOR	include/ssv6200_reg.h	1179;"	d
+ADR_TX_HOST_COMMAND_COUNT	smac/hal/ssv6006c/ssv6006C_reg.h	596;"	d
+ADR_TX_ID0	include/ssv6200_reg.h	939;"	d
+ADR_TX_ID0	smac/hal/ssv6006c/ssv6006C_reg.h	2117;"	d
+ADR_TX_ID1	include/ssv6200_reg.h	940;"	d
+ADR_TX_ID1	smac/hal/ssv6006c/ssv6006C_reg.h	2118;"	d
+ADR_TX_ID2	include/ssv6200_reg.h	953;"	d
+ADR_TX_ID2	smac/hal/ssv6006c/ssv6006C_reg.h	2131;"	d
+ADR_TX_ID3	include/ssv6200_reg.h	954;"	d
+ADR_TX_ID3	smac/hal/ssv6006c/ssv6006C_reg.h	2132;"	d
+ADR_TX_ID_ALL_INFO	include/ssv6200_reg.h	950;"	d
+ADR_TX_ID_ALL_INFO	smac/hal/ssv6006c/ssv6006C_reg.h	2128;"	d
+ADR_TX_ID_ALL_INFO2	include/ssv6200_reg.h	957;"	d
+ADR_TX_ID_ALL_INFO2	smac/hal/ssv6006c/ssv6006C_reg.h	2135;"	d
+ADR_TX_ID_ALL_INFO_A	include/ssv6200_reg.h	958;"	d
+ADR_TX_ID_ALL_INFO_A	smac/hal/ssv6006c/ssv6006C_reg.h	2136;"	d
+ADR_TX_ID_ALL_INFO_B	include/ssv6200_reg.h	959;"	d
+ADR_TX_ID_ALL_INFO_B	smac/hal/ssv6006c/ssv6006C_reg.h	2137;"	d
+ADR_TX_ID_REMAIN_STATUS	include/ssv6200_reg.h	947;"	d
+ADR_TX_ID_REMAIN_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	2125;"	d
+ADR_TX_ID_REMAIN_STATUS2	include/ssv6200_reg.h	960;"	d
+ADR_TX_ID_REMAIN_STATUS2	smac/hal/ssv6006c/ssv6006C_reg.h	2138;"	d
+ADR_TX_IQ_CONTROL_0	include/ssv6200_reg.h	1136;"	d
+ADR_TX_IQ_CONTROL_1	include/ssv6200_reg.h	1137;"	d
+ADR_TX_IQ_CONTROL_2	include/ssv6200_reg.h	1138;"	d
+ADR_TX_LIMIT_INTR	include/ssv6200_reg.h	949;"	d
+ADR_TX_LIMIT_INTR	smac/hal/ssv6006c/ssv6006C_reg.h	2127;"	d
+ADR_TX_PACKET_COUNTER	smac/hal/ssv6006c/ssv6006C_reg.h	598;"	d
+ADR_TX_PACKET_ID	smac/hal/ssv6006c/ssv6006C_reg.h	577;"	d
+ADR_TX_PACKET_LENGTH	smac/hal/ssv6006c/ssv6006C_reg.h	576;"	d
+ADR_TX_PACKET_SEND_TO_RX_DIRECTLY	smac/hal/ssv6006c/ssv6006C_reg.h	602;"	d
+ADR_TX_RX_TRAP_HW_ID_SELECTION_FUNCTION	smac/hal/ssv6006c/ssv6006C_reg.h	604;"	d
+ADR_TX_SEG	include/ssv6200_reg.h	313;"	d
+ADR_TX_SEG	smac/hal/ssv6006c/ssv6006C_reg.h	410;"	d
+ADR_TX_SEQ_CTRL_0_0	include/ssv6200_reg.h	690;"	d
+ADR_TX_SEQ_CTRL_0_0	smac/hal/ssv6006c/ssv6006C_reg.h	904;"	d
+ADR_TX_SEQ_CTRL_0_1	include/ssv6200_reg.h	692;"	d
+ADR_TX_SEQ_CTRL_0_1	smac/hal/ssv6006c/ssv6006C_reg.h	906;"	d
+ADR_TX_SEQ_CTRL_0_2	include/ssv6200_reg.h	694;"	d
+ADR_TX_SEQ_CTRL_0_2	smac/hal/ssv6006c/ssv6006C_reg.h	908;"	d
+ADR_TX_SEQ_CTRL_0_3	include/ssv6200_reg.h	696;"	d
+ADR_TX_SEQ_CTRL_0_3	smac/hal/ssv6006c/ssv6006C_reg.h	910;"	d
+ADR_TX_SEQ_CTRL_0_4	include/ssv6200_reg.h	698;"	d
+ADR_TX_SEQ_CTRL_0_4	smac/hal/ssv6006c/ssv6006C_reg.h	912;"	d
+ADR_TX_SEQ_CTRL_0_5	include/ssv6200_reg.h	700;"	d
+ADR_TX_SEQ_CTRL_0_5	smac/hal/ssv6006c/ssv6006C_reg.h	914;"	d
+ADR_TX_SEQ_CTRL_0_6	include/ssv6200_reg.h	702;"	d
+ADR_TX_SEQ_CTRL_0_6	smac/hal/ssv6006c/ssv6006C_reg.h	916;"	d
+ADR_TX_SEQ_CTRL_0_7	include/ssv6200_reg.h	704;"	d
+ADR_TX_SEQ_CTRL_0_7	smac/hal/ssv6006c/ssv6006C_reg.h	918;"	d
+ADR_TX_SEQ_CTRL_1_0	include/ssv6200_reg.h	709;"	d
+ADR_TX_SEQ_CTRL_1_0	smac/hal/ssv6006c/ssv6006C_reg.h	923;"	d
+ADR_TX_SEQ_CTRL_1_1	include/ssv6200_reg.h	711;"	d
+ADR_TX_SEQ_CTRL_1_1	smac/hal/ssv6006c/ssv6006C_reg.h	925;"	d
+ADR_TX_SEQ_CTRL_1_2	include/ssv6200_reg.h	713;"	d
+ADR_TX_SEQ_CTRL_1_2	smac/hal/ssv6006c/ssv6006C_reg.h	927;"	d
+ADR_TX_SEQ_CTRL_1_3	include/ssv6200_reg.h	715;"	d
+ADR_TX_SEQ_CTRL_1_3	smac/hal/ssv6006c/ssv6006C_reg.h	929;"	d
+ADR_TX_SEQ_CTRL_1_4	include/ssv6200_reg.h	717;"	d
+ADR_TX_SEQ_CTRL_1_4	smac/hal/ssv6006c/ssv6006C_reg.h	931;"	d
+ADR_TX_SEQ_CTRL_1_5	include/ssv6200_reg.h	719;"	d
+ADR_TX_SEQ_CTRL_1_5	smac/hal/ssv6006c/ssv6006C_reg.h	933;"	d
+ADR_TX_SEQ_CTRL_1_6	include/ssv6200_reg.h	721;"	d
+ADR_TX_SEQ_CTRL_1_6	smac/hal/ssv6006c/ssv6006C_reg.h	935;"	d
+ADR_TX_SEQ_CTRL_1_7	include/ssv6200_reg.h	723;"	d
+ADR_TX_SEQ_CTRL_1_7	smac/hal/ssv6006c/ssv6006C_reg.h	937;"	d
+ADR_TX_SEQ_CTRL_2_0	smac/hal/ssv6006c/ssv6006C_reg.h	1030;"	d
+ADR_TX_SEQ_CTRL_2_1	smac/hal/ssv6006c/ssv6006C_reg.h	1032;"	d
+ADR_TX_SEQ_CTRL_2_2	smac/hal/ssv6006c/ssv6006C_reg.h	1034;"	d
+ADR_TX_SEQ_CTRL_2_3	smac/hal/ssv6006c/ssv6006C_reg.h	1036;"	d
+ADR_TX_SEQ_CTRL_2_4	smac/hal/ssv6006c/ssv6006C_reg.h	1038;"	d
+ADR_TX_SEQ_CTRL_2_5	smac/hal/ssv6006c/ssv6006C_reg.h	1040;"	d
+ADR_TX_SEQ_CTRL_2_6	smac/hal/ssv6006c/ssv6006C_reg.h	1042;"	d
+ADR_TX_SEQ_CTRL_2_7	smac/hal/ssv6006c/ssv6006C_reg.h	1044;"	d
+ADR_TX_SEQ_CTRL_3_0	smac/hal/ssv6006c/ssv6006C_reg.h	1049;"	d
+ADR_TX_SEQ_CTRL_3_1	smac/hal/ssv6006c/ssv6006C_reg.h	1051;"	d
+ADR_TX_SEQ_CTRL_3_2	smac/hal/ssv6006c/ssv6006C_reg.h	1053;"	d
+ADR_TX_SEQ_CTRL_3_3	smac/hal/ssv6006c/ssv6006C_reg.h	1055;"	d
+ADR_TX_SEQ_CTRL_3_4	smac/hal/ssv6006c/ssv6006C_reg.h	1057;"	d
+ADR_TX_SEQ_CTRL_3_5	smac/hal/ssv6006c/ssv6006C_reg.h	1059;"	d
+ADR_TX_SEQ_CTRL_3_6	smac/hal/ssv6006c/ssv6006C_reg.h	1061;"	d
+ADR_TX_SEQ_CTRL_3_7	smac/hal/ssv6006c/ssv6006C_reg.h	1063;"	d
+ADR_TX_SEQ_CTRL_4_0	smac/hal/ssv6006c/ssv6006C_reg.h	1068;"	d
+ADR_TX_SEQ_CTRL_4_1	smac/hal/ssv6006c/ssv6006C_reg.h	1070;"	d
+ADR_TX_SEQ_CTRL_4_2	smac/hal/ssv6006c/ssv6006C_reg.h	1072;"	d
+ADR_TX_SEQ_CTRL_4_3	smac/hal/ssv6006c/ssv6006C_reg.h	1074;"	d
+ADR_TX_SEQ_CTRL_4_4	smac/hal/ssv6006c/ssv6006C_reg.h	1076;"	d
+ADR_TX_SEQ_CTRL_4_5	smac/hal/ssv6006c/ssv6006C_reg.h	1078;"	d
+ADR_TX_SEQ_CTRL_4_6	smac/hal/ssv6006c/ssv6006C_reg.h	1080;"	d
+ADR_TX_SEQ_CTRL_4_7	smac/hal/ssv6006c/ssv6006C_reg.h	1082;"	d
+ADR_TX_SEQ_CTRL_5_0	smac/hal/ssv6006c/ssv6006C_reg.h	1087;"	d
+ADR_TX_SEQ_CTRL_5_1	smac/hal/ssv6006c/ssv6006C_reg.h	1089;"	d
+ADR_TX_SEQ_CTRL_5_2	smac/hal/ssv6006c/ssv6006C_reg.h	1091;"	d
+ADR_TX_SEQ_CTRL_5_3	smac/hal/ssv6006c/ssv6006C_reg.h	1093;"	d
+ADR_TX_SEQ_CTRL_5_4	smac/hal/ssv6006c/ssv6006C_reg.h	1095;"	d
+ADR_TX_SEQ_CTRL_5_5	smac/hal/ssv6006c/ssv6006C_reg.h	1097;"	d
+ADR_TX_SEQ_CTRL_5_6	smac/hal/ssv6006c/ssv6006C_reg.h	1099;"	d
+ADR_TX_SEQ_CTRL_5_7	smac/hal/ssv6006c/ssv6006C_reg.h	1101;"	d
+ADR_TX_SEQ_CTRL_6_0	smac/hal/ssv6006c/ssv6006C_reg.h	1106;"	d
+ADR_TX_SEQ_CTRL_6_1	smac/hal/ssv6006c/ssv6006C_reg.h	1108;"	d
+ADR_TX_SEQ_CTRL_6_2	smac/hal/ssv6006c/ssv6006C_reg.h	1110;"	d
+ADR_TX_SEQ_CTRL_6_3	smac/hal/ssv6006c/ssv6006C_reg.h	1112;"	d
+ADR_TX_SEQ_CTRL_6_4	smac/hal/ssv6006c/ssv6006C_reg.h	1114;"	d
+ADR_TX_SEQ_CTRL_6_5	smac/hal/ssv6006c/ssv6006C_reg.h	1116;"	d
+ADR_TX_SEQ_CTRL_6_6	smac/hal/ssv6006c/ssv6006C_reg.h	1118;"	d
+ADR_TX_SEQ_CTRL_6_7	smac/hal/ssv6006c/ssv6006C_reg.h	1120;"	d
+ADR_TX_SEQ_CTRL_7_0	smac/hal/ssv6006c/ssv6006C_reg.h	1125;"	d
+ADR_TX_SEQ_CTRL_7_1	smac/hal/ssv6006c/ssv6006C_reg.h	1127;"	d
+ADR_TX_SEQ_CTRL_7_2	smac/hal/ssv6006c/ssv6006C_reg.h	1129;"	d
+ADR_TX_SEQ_CTRL_7_3	smac/hal/ssv6006c/ssv6006C_reg.h	1131;"	d
+ADR_TX_SEQ_CTRL_7_4	smac/hal/ssv6006c/ssv6006C_reg.h	1133;"	d
+ADR_TX_SEQ_CTRL_7_5	smac/hal/ssv6006c/ssv6006C_reg.h	1135;"	d
+ADR_TX_SEQ_CTRL_7_6	smac/hal/ssv6006c/ssv6006C_reg.h	1137;"	d
+ADR_TX_SEQ_CTRL_7_7	smac/hal/ssv6006c/ssv6006C_reg.h	1139;"	d
+ADR_TX_TIME_OUT_READ_CTRL	include/ssv6200_reg.h	264;"	d
+ADR_TX_TRAP_COUNT	smac/hal/ssv6006c/ssv6006C_reg.h	592;"	d
+ADR_UART_DATA	include/ssv6200_reg.h	331;"	d
+ADR_UART_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	433;"	d
+ADR_UART_FCR	include/ssv6200_reg.h	333;"	d
+ADR_UART_FCR	smac/hal/ssv6006c/ssv6006C_reg.h	435;"	d
+ADR_UART_IER	include/ssv6200_reg.h	332;"	d
+ADR_UART_IER	smac/hal/ssv6006c/ssv6006C_reg.h	434;"	d
+ADR_UART_INT_MAP	smac/hal/ssv6006c/ssv6006C_reg.h	444;"	d
+ADR_UART_ISR	include/ssv6200_reg.h	340;"	d
+ADR_UART_ISR	smac/hal/ssv6006c/ssv6006C_reg.h	442;"	d
+ADR_UART_LCR	include/ssv6200_reg.h	334;"	d
+ADR_UART_LCR	smac/hal/ssv6006c/ssv6006C_reg.h	436;"	d
+ADR_UART_LSR	include/ssv6200_reg.h	336;"	d
+ADR_UART_LSR	smac/hal/ssv6006c/ssv6006C_reg.h	438;"	d
+ADR_UART_MCR	include/ssv6200_reg.h	335;"	d
+ADR_UART_MCR	smac/hal/ssv6006c/ssv6006C_reg.h	437;"	d
+ADR_UART_MSR	include/ssv6200_reg.h	337;"	d
+ADR_UART_MSR	smac/hal/ssv6006c/ssv6006C_reg.h	439;"	d
+ADR_UART_POINTER	smac/hal/ssv6006c/ssv6006C_reg.h	445;"	d
+ADR_UART_RTHR	include/ssv6200_reg.h	339;"	d
+ADR_UART_RTHR	smac/hal/ssv6006c/ssv6006C_reg.h	441;"	d
+ADR_UART_SPR	include/ssv6200_reg.h	338;"	d
+ADR_UART_SPR	smac/hal/ssv6006c/ssv6006C_reg.h	440;"	d
+ADR_UART_TTHR	smac/hal/ssv6006c/ssv6006C_reg.h	443;"	d
+ADR_UART_W2B	include/ssv6200_reg.h	133;"	d
+ADR_UART_W2B	smac/hal/ssv6006c/ssv6006C_reg.h	253;"	d
+ADR_USB20_HOST_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	280;"	d
+ADR_VERIFY_DATA	include/ssv6200_reg.h	385;"	d
+ADR_VIAROM_EMA	smac/hal/ssv6006c/ssv6006C_reg.h	263;"	d
+ADR_WAKE_PMU_ENABLE	smac/hal/ssv6006c/ssv6006C_reg.h	292;"	d
+ADR_WBT_RX_ADC_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1529;"	d
+ADR_WF_DCOC_IDAC_REGISTER1	smac/hal/ssv6006c/ssv6006C_reg.h	1547;"	d
+ADR_WF_DCOC_IDAC_REGISTER10	smac/hal/ssv6006c/ssv6006C_reg.h	1556;"	d
+ADR_WF_DCOC_IDAC_REGISTER11	smac/hal/ssv6006c/ssv6006C_reg.h	1557;"	d
+ADR_WF_DCOC_IDAC_REGISTER12	smac/hal/ssv6006c/ssv6006C_reg.h	1558;"	d
+ADR_WF_DCOC_IDAC_REGISTER13	smac/hal/ssv6006c/ssv6006C_reg.h	1559;"	d
+ADR_WF_DCOC_IDAC_REGISTER14	smac/hal/ssv6006c/ssv6006C_reg.h	1560;"	d
+ADR_WF_DCOC_IDAC_REGISTER15	smac/hal/ssv6006c/ssv6006C_reg.h	1561;"	d
+ADR_WF_DCOC_IDAC_REGISTER16	smac/hal/ssv6006c/ssv6006C_reg.h	1562;"	d
+ADR_WF_DCOC_IDAC_REGISTER17	smac/hal/ssv6006c/ssv6006C_reg.h	1563;"	d
+ADR_WF_DCOC_IDAC_REGISTER18	smac/hal/ssv6006c/ssv6006C_reg.h	1564;"	d
+ADR_WF_DCOC_IDAC_REGISTER19	smac/hal/ssv6006c/ssv6006C_reg.h	1565;"	d
+ADR_WF_DCOC_IDAC_REGISTER2	smac/hal/ssv6006c/ssv6006C_reg.h	1548;"	d
+ADR_WF_DCOC_IDAC_REGISTER20	smac/hal/ssv6006c/ssv6006C_reg.h	1566;"	d
+ADR_WF_DCOC_IDAC_REGISTER21	smac/hal/ssv6006c/ssv6006C_reg.h	1567;"	d
+ADR_WF_DCOC_IDAC_REGISTER3	smac/hal/ssv6006c/ssv6006C_reg.h	1549;"	d
+ADR_WF_DCOC_IDAC_REGISTER4	smac/hal/ssv6006c/ssv6006C_reg.h	1550;"	d
+ADR_WF_DCOC_IDAC_REGISTER5	smac/hal/ssv6006c/ssv6006C_reg.h	1551;"	d
+ADR_WF_DCOC_IDAC_REGISTER6	smac/hal/ssv6006c/ssv6006C_reg.h	1552;"	d
+ADR_WF_DCOC_IDAC_REGISTER7	smac/hal/ssv6006c/ssv6006C_reg.h	1553;"	d
+ADR_WF_DCOC_IDAC_REGISTER8	smac/hal/ssv6006c/ssv6006C_reg.h	1554;"	d
+ADR_WF_DCOC_IDAC_REGISTER9	smac/hal/ssv6006c/ssv6006C_reg.h	1555;"	d
+ADR_WIFI_11B_RX_REG_000	smac/hal/ssv6006c/ssv6006C_reg.h	1965;"	d
+ADR_WIFI_11B_RX_REG_001	smac/hal/ssv6006c/ssv6006C_reg.h	1966;"	d
+ADR_WIFI_11B_RX_REG_002	smac/hal/ssv6006c/ssv6006C_reg.h	1967;"	d
+ADR_WIFI_11B_RX_REG_003	smac/hal/ssv6006c/ssv6006C_reg.h	1968;"	d
+ADR_WIFI_11B_RX_REG_004	smac/hal/ssv6006c/ssv6006C_reg.h	1969;"	d
+ADR_WIFI_11B_RX_REG_005	smac/hal/ssv6006c/ssv6006C_reg.h	1970;"	d
+ADR_WIFI_11B_RX_REG_006	smac/hal/ssv6006c/ssv6006C_reg.h	1971;"	d
+ADR_WIFI_11B_RX_REG_007	smac/hal/ssv6006c/ssv6006C_reg.h	1972;"	d
+ADR_WIFI_11B_RX_REG_008	smac/hal/ssv6006c/ssv6006C_reg.h	1973;"	d
+ADR_WIFI_11B_RX_REG_009	smac/hal/ssv6006c/ssv6006C_reg.h	1974;"	d
+ADR_WIFI_11B_RX_REG_010	smac/hal/ssv6006c/ssv6006C_reg.h	1975;"	d
+ADR_WIFI_11B_RX_REG_011	smac/hal/ssv6006c/ssv6006C_reg.h	1976;"	d
+ADR_WIFI_11B_RX_REG_012	smac/hal/ssv6006c/ssv6006C_reg.h	1977;"	d
+ADR_WIFI_11B_RX_REG_013	smac/hal/ssv6006c/ssv6006C_reg.h	1978;"	d
+ADR_WIFI_11B_RX_REG_014	smac/hal/ssv6006c/ssv6006C_reg.h	1979;"	d
+ADR_WIFI_11B_RX_REG_039	smac/hal/ssv6006c/ssv6006C_reg.h	1980;"	d
+ADR_WIFI_11B_RX_REG_040	smac/hal/ssv6006c/ssv6006C_reg.h	1981;"	d
+ADR_WIFI_11B_RX_REG_041	smac/hal/ssv6006c/ssv6006C_reg.h	1982;"	d
+ADR_WIFI_11B_RX_REG_240	smac/hal/ssv6006c/ssv6006C_reg.h	1983;"	d
+ADR_WIFI_11B_RX_REG_241	smac/hal/ssv6006c/ssv6006C_reg.h	1984;"	d
+ADR_WIFI_11B_RX_REG_244	smac/hal/ssv6006c/ssv6006C_reg.h	1985;"	d
+ADR_WIFI_11B_RX_REG_245	smac/hal/ssv6006c/ssv6006C_reg.h	1986;"	d
+ADR_WIFI_11B_RX_REG_246	smac/hal/ssv6006c/ssv6006C_reg.h	1987;"	d
+ADR_WIFI_11B_RX_REG_249	smac/hal/ssv6006c/ssv6006C_reg.h	1988;"	d
+ADR_WIFI_11B_RX_REG_250	smac/hal/ssv6006c/ssv6006C_reg.h	1989;"	d
+ADR_WIFI_11B_RX_REG_251	smac/hal/ssv6006c/ssv6006C_reg.h	1990;"	d
+ADR_WIFI_11B_RX_REG_252	smac/hal/ssv6006c/ssv6006C_reg.h	1991;"	d
+ADR_WIFI_11B_RX_REG_253	smac/hal/ssv6006c/ssv6006C_reg.h	1992;"	d
+ADR_WIFI_11B_RX_REG_254	smac/hal/ssv6006c/ssv6006C_reg.h	1993;"	d
+ADR_WIFI_11B_RX_REG_255	smac/hal/ssv6006c/ssv6006C_reg.h	1994;"	d
+ADR_WIFI_11B_TX_BB_RAMP_REG	smac/hal/ssv6006c/ssv6006C_reg.h	1961;"	d
+ADR_WIFI_11B_TX_DEBUG_SEL_REG	smac/hal/ssv6006c/ssv6006C_reg.h	1963;"	d
+ADR_WIFI_11B_TX_PKT_CNT_SENT_REG	smac/hal/ssv6006c/ssv6006C_reg.h	1962;"	d
+ADR_WIFI_11B_TX_RESERVED_REG	smac/hal/ssv6006c/ssv6006C_reg.h	1964;"	d
+ADR_WIFI_11GN_RX_REG_000	smac/hal/ssv6006c/ssv6006C_reg.h	2004;"	d
+ADR_WIFI_11GN_RX_REG_001	smac/hal/ssv6006c/ssv6006C_reg.h	2005;"	d
+ADR_WIFI_11GN_RX_REG_002	smac/hal/ssv6006c/ssv6006C_reg.h	2006;"	d
+ADR_WIFI_11GN_RX_REG_003	smac/hal/ssv6006c/ssv6006C_reg.h	2007;"	d
+ADR_WIFI_11GN_RX_REG_004_	smac/hal/ssv6006c/ssv6006C_reg.h	2008;"	d
+ADR_WIFI_11GN_RX_REG_005	smac/hal/ssv6006c/ssv6006C_reg.h	2009;"	d
+ADR_WIFI_11GN_RX_REG_006_	smac/hal/ssv6006c/ssv6006C_reg.h	2010;"	d
+ADR_WIFI_11GN_RX_REG_007_	smac/hal/ssv6006c/ssv6006C_reg.h	2011;"	d
+ADR_WIFI_11GN_RX_REG_008	smac/hal/ssv6006c/ssv6006C_reg.h	2012;"	d
+ADR_WIFI_11GN_RX_REG_009	smac/hal/ssv6006c/ssv6006C_reg.h	2013;"	d
+ADR_WIFI_11GN_RX_REG_010_	smac/hal/ssv6006c/ssv6006C_reg.h	2014;"	d
+ADR_WIFI_11GN_RX_REG_011	smac/hal/ssv6006c/ssv6006C_reg.h	2015;"	d
+ADR_WIFI_11GN_RX_REG_012	smac/hal/ssv6006c/ssv6006C_reg.h	2016;"	d
+ADR_WIFI_11GN_RX_REG_013	smac/hal/ssv6006c/ssv6006C_reg.h	2017;"	d
+ADR_WIFI_11GN_RX_REG_014	smac/hal/ssv6006c/ssv6006C_reg.h	2018;"	d
+ADR_WIFI_11GN_RX_REG_015	smac/hal/ssv6006c/ssv6006C_reg.h	2019;"	d
+ADR_WIFI_11GN_RX_REG_016	smac/hal/ssv6006c/ssv6006C_reg.h	2020;"	d
+ADR_WIFI_11GN_RX_REG_017	smac/hal/ssv6006c/ssv6006C_reg.h	2021;"	d
+ADR_WIFI_11GN_RX_REG_032	smac/hal/ssv6006c/ssv6006C_reg.h	2022;"	d
+ADR_WIFI_11GN_RX_REG_033	smac/hal/ssv6006c/ssv6006C_reg.h	2023;"	d
+ADR_WIFI_11GN_RX_REG_039	smac/hal/ssv6006c/ssv6006C_reg.h	2024;"	d
+ADR_WIFI_11GN_RX_REG_040	smac/hal/ssv6006c/ssv6006C_reg.h	2025;"	d
+ADR_WIFI_11GN_RX_REG_048	smac/hal/ssv6006c/ssv6006C_reg.h	2026;"	d
+ADR_WIFI_11GN_RX_REG_049	smac/hal/ssv6006c/ssv6006C_reg.h	2027;"	d
+ADR_WIFI_11GN_RX_REG_050	smac/hal/ssv6006c/ssv6006C_reg.h	2028;"	d
+ADR_WIFI_11GN_RX_REG_051	smac/hal/ssv6006c/ssv6006C_reg.h	2029;"	d
+ADR_WIFI_11GN_RX_REG_052	smac/hal/ssv6006c/ssv6006C_reg.h	2030;"	d
+ADR_WIFI_11GN_RX_REG_076	smac/hal/ssv6006c/ssv6006C_reg.h	2031;"	d
+ADR_WIFI_11GN_RX_REG_087	smac/hal/ssv6006c/ssv6006C_reg.h	2032;"	d
+ADR_WIFI_11GN_RX_REG_088	smac/hal/ssv6006c/ssv6006C_reg.h	2033;"	d
+ADR_WIFI_11GN_RX_REG_089	smac/hal/ssv6006c/ssv6006C_reg.h	2034;"	d
+ADR_WIFI_11GN_RX_REG_096	smac/hal/ssv6006c/ssv6006C_reg.h	2035;"	d
+ADR_WIFI_11GN_RX_REG_098	smac/hal/ssv6006c/ssv6006C_reg.h	2036;"	d
+ADR_WIFI_11GN_RX_REG_100	smac/hal/ssv6006c/ssv6006C_reg.h	2037;"	d
+ADR_WIFI_11GN_RX_REG_101	smac/hal/ssv6006c/ssv6006C_reg.h	2038;"	d
+ADR_WIFI_11GN_RX_REG_102	smac/hal/ssv6006c/ssv6006C_reg.h	2039;"	d
+ADR_WIFI_11GN_RX_REG_103	smac/hal/ssv6006c/ssv6006C_reg.h	2040;"	d
+ADR_WIFI_11GN_RX_REG_241	smac/hal/ssv6006c/ssv6006C_reg.h	2041;"	d
+ADR_WIFI_11GN_RX_REG_244	smac/hal/ssv6006c/ssv6006C_reg.h	2042;"	d
+ADR_WIFI_11GN_RX_REG_245	smac/hal/ssv6006c/ssv6006C_reg.h	2043;"	d
+ADR_WIFI_11GN_RX_REG_246	smac/hal/ssv6006c/ssv6006C_reg.h	2044;"	d
+ADR_WIFI_11GN_RX_REG_247	smac/hal/ssv6006c/ssv6006C_reg.h	2045;"	d
+ADR_WIFI_11GN_RX_REG_248	smac/hal/ssv6006c/ssv6006C_reg.h	2046;"	d
+ADR_WIFI_11GN_RX_REG_249	smac/hal/ssv6006c/ssv6006C_reg.h	2047;"	d
+ADR_WIFI_11GN_RX_REG_250	smac/hal/ssv6006c/ssv6006C_reg.h	2048;"	d
+ADR_WIFI_11GN_RX_REG_251	smac/hal/ssv6006c/ssv6006C_reg.h	2049;"	d
+ADR_WIFI_11GN_RX_REG_252	smac/hal/ssv6006c/ssv6006C_reg.h	2050;"	d
+ADR_WIFI_11GN_RX_REG_253	smac/hal/ssv6006c/ssv6006C_reg.h	2051;"	d
+ADR_WIFI_11GN_RX_REG_254	smac/hal/ssv6006c/ssv6006C_reg.h	2052;"	d
+ADR_WIFI_11GN_RX_REG_255	smac/hal/ssv6006c/ssv6006C_reg.h	2053;"	d
+ADR_WIFI_11GN_TX_BB_RAMP_REG	smac/hal/ssv6006c/ssv6006C_reg.h	1996;"	d
+ADR_WIFI_11GN_TX_CONTROL_REG	smac/hal/ssv6006c/ssv6006C_reg.h	1997;"	d
+ADR_WIFI_11GN_TX_DEBUG_SEL_REG	smac/hal/ssv6006c/ssv6006C_reg.h	2002;"	d
+ADR_WIFI_11GN_TX_FFT_SCALE_REG0	smac/hal/ssv6006c/ssv6006C_reg.h	1999;"	d
+ADR_WIFI_11GN_TX_FFT_SCALE_REG1	smac/hal/ssv6006c/ssv6006C_reg.h	2000;"	d
+ADR_WIFI_11GN_TX_MEM_BIST_REG	smac/hal/ssv6006c/ssv6006C_reg.h	1995;"	d
+ADR_WIFI_11GN_TX_PKT_CNT_SENT_REG	smac/hal/ssv6006c/ssv6006C_reg.h	2001;"	d
+ADR_WIFI_11GN_TX_RESERVED_REG	smac/hal/ssv6006c/ssv6006C_reg.h	2003;"	d
+ADR_WIFI_11GN_TX_STS_SCALE_REG	smac/hal/ssv6006c/ssv6006C_reg.h	1998;"	d
+ADR_WIFI_HT20_RX_FILTER_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1514;"	d
+ADR_WIFI_HT40_RX_FILTER_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1515;"	d
+ADR_WIFI_PADPD_2G_BB_GAIN_REG	smac/hal/ssv6006c/ssv6006C_reg.h	1830;"	d
+ADR_WIFI_PADPD_2G_CONTROL_REG	smac/hal/ssv6006c/ssv6006C_reg.h	1802;"	d
+ADR_WIFI_PADPD_2G_GAIN_REG0	smac/hal/ssv6006c/ssv6006C_reg.h	1803;"	d
+ADR_WIFI_PADPD_2G_GAIN_REG1	smac/hal/ssv6006c/ssv6006C_reg.h	1804;"	d
+ADR_WIFI_PADPD_2G_GAIN_REG2	smac/hal/ssv6006c/ssv6006C_reg.h	1805;"	d
+ADR_WIFI_PADPD_2G_GAIN_REG3	smac/hal/ssv6006c/ssv6006C_reg.h	1806;"	d
+ADR_WIFI_PADPD_2G_GAIN_REG4	smac/hal/ssv6006c/ssv6006C_reg.h	1807;"	d
+ADR_WIFI_PADPD_2G_GAIN_REG5	smac/hal/ssv6006c/ssv6006C_reg.h	1808;"	d
+ADR_WIFI_PADPD_2G_GAIN_REG6	smac/hal/ssv6006c/ssv6006C_reg.h	1809;"	d
+ADR_WIFI_PADPD_2G_GAIN_REG7	smac/hal/ssv6006c/ssv6006C_reg.h	1810;"	d
+ADR_WIFI_PADPD_2G_GAIN_REG8	smac/hal/ssv6006c/ssv6006C_reg.h	1811;"	d
+ADR_WIFI_PADPD_2G_GAIN_REG9	smac/hal/ssv6006c/ssv6006C_reg.h	1812;"	d
+ADR_WIFI_PADPD_2G_GAIN_REGA	smac/hal/ssv6006c/ssv6006C_reg.h	1813;"	d
+ADR_WIFI_PADPD_2G_GAIN_REGB	smac/hal/ssv6006c/ssv6006C_reg.h	1814;"	d
+ADR_WIFI_PADPD_2G_GAIN_REGC	smac/hal/ssv6006c/ssv6006C_reg.h	1815;"	d
+ADR_WIFI_PADPD_2G_PHASE_REG0	smac/hal/ssv6006c/ssv6006C_reg.h	1816;"	d
+ADR_WIFI_PADPD_2G_PHASE_REG1	smac/hal/ssv6006c/ssv6006C_reg.h	1817;"	d
+ADR_WIFI_PADPD_2G_PHASE_REG2	smac/hal/ssv6006c/ssv6006C_reg.h	1818;"	d
+ADR_WIFI_PADPD_2G_PHASE_REG3	smac/hal/ssv6006c/ssv6006C_reg.h	1819;"	d
+ADR_WIFI_PADPD_2G_PHASE_REG4	smac/hal/ssv6006c/ssv6006C_reg.h	1820;"	d
+ADR_WIFI_PADPD_2G_PHASE_REG5	smac/hal/ssv6006c/ssv6006C_reg.h	1821;"	d
+ADR_WIFI_PADPD_2G_PHASE_REG6	smac/hal/ssv6006c/ssv6006C_reg.h	1822;"	d
+ADR_WIFI_PADPD_2G_PHASE_REG7	smac/hal/ssv6006c/ssv6006C_reg.h	1823;"	d
+ADR_WIFI_PADPD_2G_PHASE_REG8	smac/hal/ssv6006c/ssv6006C_reg.h	1824;"	d
+ADR_WIFI_PADPD_2G_PHASE_REG9	smac/hal/ssv6006c/ssv6006C_reg.h	1825;"	d
+ADR_WIFI_PADPD_2G_PHASE_REGA	smac/hal/ssv6006c/ssv6006C_reg.h	1826;"	d
+ADR_WIFI_PADPD_2G_PHASE_REGB	smac/hal/ssv6006c/ssv6006C_reg.h	1827;"	d
+ADR_WIFI_PADPD_2G_PHASE_REGC	smac/hal/ssv6006c/ssv6006C_reg.h	1828;"	d
+ADR_WIFI_PADPD_5100_GAIN_REG0	smac/hal/ssv6006c/ssv6006C_reg.h	1689;"	d
+ADR_WIFI_PADPD_5100_GAIN_REG1	smac/hal/ssv6006c/ssv6006C_reg.h	1690;"	d
+ADR_WIFI_PADPD_5100_GAIN_REG2	smac/hal/ssv6006c/ssv6006C_reg.h	1691;"	d
+ADR_WIFI_PADPD_5100_GAIN_REG3	smac/hal/ssv6006c/ssv6006C_reg.h	1692;"	d
+ADR_WIFI_PADPD_5100_GAIN_REG4	smac/hal/ssv6006c/ssv6006C_reg.h	1693;"	d
+ADR_WIFI_PADPD_5100_GAIN_REG5	smac/hal/ssv6006c/ssv6006C_reg.h	1694;"	d
+ADR_WIFI_PADPD_5100_GAIN_REG6	smac/hal/ssv6006c/ssv6006C_reg.h	1695;"	d
+ADR_WIFI_PADPD_5100_GAIN_REG7	smac/hal/ssv6006c/ssv6006C_reg.h	1696;"	d
+ADR_WIFI_PADPD_5100_GAIN_REG8	smac/hal/ssv6006c/ssv6006C_reg.h	1697;"	d
+ADR_WIFI_PADPD_5100_GAIN_REG9	smac/hal/ssv6006c/ssv6006C_reg.h	1698;"	d
+ADR_WIFI_PADPD_5100_GAIN_REGA	smac/hal/ssv6006c/ssv6006C_reg.h	1699;"	d
+ADR_WIFI_PADPD_5100_GAIN_REGB	smac/hal/ssv6006c/ssv6006C_reg.h	1700;"	d
+ADR_WIFI_PADPD_5100_GAIN_REGC	smac/hal/ssv6006c/ssv6006C_reg.h	1701;"	d
+ADR_WIFI_PADPD_5100_PHASE_REG0	smac/hal/ssv6006c/ssv6006C_reg.h	1702;"	d
+ADR_WIFI_PADPD_5100_PHASE_REG1	smac/hal/ssv6006c/ssv6006C_reg.h	1703;"	d
+ADR_WIFI_PADPD_5100_PHASE_REG2	smac/hal/ssv6006c/ssv6006C_reg.h	1704;"	d
+ADR_WIFI_PADPD_5100_PHASE_REG3	smac/hal/ssv6006c/ssv6006C_reg.h	1705;"	d
+ADR_WIFI_PADPD_5100_PHASE_REG4	smac/hal/ssv6006c/ssv6006C_reg.h	1706;"	d
+ADR_WIFI_PADPD_5100_PHASE_REG5	smac/hal/ssv6006c/ssv6006C_reg.h	1707;"	d
+ADR_WIFI_PADPD_5100_PHASE_REG6	smac/hal/ssv6006c/ssv6006C_reg.h	1708;"	d
+ADR_WIFI_PADPD_5100_PHASE_REG7	smac/hal/ssv6006c/ssv6006C_reg.h	1709;"	d
+ADR_WIFI_PADPD_5100_PHASE_REG8	smac/hal/ssv6006c/ssv6006C_reg.h	1710;"	d
+ADR_WIFI_PADPD_5100_PHASE_REG9	smac/hal/ssv6006c/ssv6006C_reg.h	1711;"	d
+ADR_WIFI_PADPD_5100_PHASE_REGA	smac/hal/ssv6006c/ssv6006C_reg.h	1712;"	d
+ADR_WIFI_PADPD_5100_PHASE_REGB	smac/hal/ssv6006c/ssv6006C_reg.h	1713;"	d
+ADR_WIFI_PADPD_5100_PHASE_REGC	smac/hal/ssv6006c/ssv6006C_reg.h	1714;"	d
+ADR_WIFI_PADPD_5500_GAIN_REG0	smac/hal/ssv6006c/ssv6006C_reg.h	1715;"	d
+ADR_WIFI_PADPD_5500_GAIN_REG1	smac/hal/ssv6006c/ssv6006C_reg.h	1716;"	d
+ADR_WIFI_PADPD_5500_GAIN_REG2	smac/hal/ssv6006c/ssv6006C_reg.h	1717;"	d
+ADR_WIFI_PADPD_5500_GAIN_REG3	smac/hal/ssv6006c/ssv6006C_reg.h	1718;"	d
+ADR_WIFI_PADPD_5500_GAIN_REG4	smac/hal/ssv6006c/ssv6006C_reg.h	1719;"	d
+ADR_WIFI_PADPD_5500_GAIN_REG5	smac/hal/ssv6006c/ssv6006C_reg.h	1720;"	d
+ADR_WIFI_PADPD_5500_GAIN_REG6	smac/hal/ssv6006c/ssv6006C_reg.h	1721;"	d
+ADR_WIFI_PADPD_5500_GAIN_REG7	smac/hal/ssv6006c/ssv6006C_reg.h	1722;"	d
+ADR_WIFI_PADPD_5500_GAIN_REG8	smac/hal/ssv6006c/ssv6006C_reg.h	1723;"	d
+ADR_WIFI_PADPD_5500_GAIN_REG9	smac/hal/ssv6006c/ssv6006C_reg.h	1724;"	d
+ADR_WIFI_PADPD_5500_GAIN_REGA	smac/hal/ssv6006c/ssv6006C_reg.h	1725;"	d
+ADR_WIFI_PADPD_5500_GAIN_REGB	smac/hal/ssv6006c/ssv6006C_reg.h	1726;"	d
+ADR_WIFI_PADPD_5500_GAIN_REGC	smac/hal/ssv6006c/ssv6006C_reg.h	1727;"	d
+ADR_WIFI_PADPD_5500_PHASE_REG0	smac/hal/ssv6006c/ssv6006C_reg.h	1728;"	d
+ADR_WIFI_PADPD_5500_PHASE_REG1	smac/hal/ssv6006c/ssv6006C_reg.h	1729;"	d
+ADR_WIFI_PADPD_5500_PHASE_REG2	smac/hal/ssv6006c/ssv6006C_reg.h	1730;"	d
+ADR_WIFI_PADPD_5500_PHASE_REG3	smac/hal/ssv6006c/ssv6006C_reg.h	1731;"	d
+ADR_WIFI_PADPD_5500_PHASE_REG4	smac/hal/ssv6006c/ssv6006C_reg.h	1732;"	d
+ADR_WIFI_PADPD_5500_PHASE_REG5	smac/hal/ssv6006c/ssv6006C_reg.h	1733;"	d
+ADR_WIFI_PADPD_5500_PHASE_REG6	smac/hal/ssv6006c/ssv6006C_reg.h	1734;"	d
+ADR_WIFI_PADPD_5500_PHASE_REG7	smac/hal/ssv6006c/ssv6006C_reg.h	1735;"	d
+ADR_WIFI_PADPD_5500_PHASE_REG8	smac/hal/ssv6006c/ssv6006C_reg.h	1736;"	d
+ADR_WIFI_PADPD_5500_PHASE_REG9	smac/hal/ssv6006c/ssv6006C_reg.h	1737;"	d
+ADR_WIFI_PADPD_5500_PHASE_REGA	smac/hal/ssv6006c/ssv6006C_reg.h	1738;"	d
+ADR_WIFI_PADPD_5500_PHASE_REGB	smac/hal/ssv6006c/ssv6006C_reg.h	1739;"	d
+ADR_WIFI_PADPD_5500_PHASE_REGC	smac/hal/ssv6006c/ssv6006C_reg.h	1740;"	d
+ADR_WIFI_PADPD_5700_GAIN_REG0	smac/hal/ssv6006c/ssv6006C_reg.h	1741;"	d
+ADR_WIFI_PADPD_5700_GAIN_REG1	smac/hal/ssv6006c/ssv6006C_reg.h	1742;"	d
+ADR_WIFI_PADPD_5700_GAIN_REG2	smac/hal/ssv6006c/ssv6006C_reg.h	1743;"	d
+ADR_WIFI_PADPD_5700_GAIN_REG3	smac/hal/ssv6006c/ssv6006C_reg.h	1744;"	d
+ADR_WIFI_PADPD_5700_GAIN_REG4	smac/hal/ssv6006c/ssv6006C_reg.h	1745;"	d
+ADR_WIFI_PADPD_5700_GAIN_REG5	smac/hal/ssv6006c/ssv6006C_reg.h	1746;"	d
+ADR_WIFI_PADPD_5700_GAIN_REG6	smac/hal/ssv6006c/ssv6006C_reg.h	1747;"	d
+ADR_WIFI_PADPD_5700_GAIN_REG7	smac/hal/ssv6006c/ssv6006C_reg.h	1748;"	d
+ADR_WIFI_PADPD_5700_GAIN_REG8	smac/hal/ssv6006c/ssv6006C_reg.h	1749;"	d
+ADR_WIFI_PADPD_5700_GAIN_REG9	smac/hal/ssv6006c/ssv6006C_reg.h	1750;"	d
+ADR_WIFI_PADPD_5700_GAIN_REGA	smac/hal/ssv6006c/ssv6006C_reg.h	1751;"	d
+ADR_WIFI_PADPD_5700_GAIN_REGB	smac/hal/ssv6006c/ssv6006C_reg.h	1752;"	d
+ADR_WIFI_PADPD_5700_GAIN_REGC	smac/hal/ssv6006c/ssv6006C_reg.h	1753;"	d
+ADR_WIFI_PADPD_5700_PHASE_REG0	smac/hal/ssv6006c/ssv6006C_reg.h	1754;"	d
+ADR_WIFI_PADPD_5700_PHASE_REG1	smac/hal/ssv6006c/ssv6006C_reg.h	1755;"	d
+ADR_WIFI_PADPD_5700_PHASE_REG2	smac/hal/ssv6006c/ssv6006C_reg.h	1756;"	d
+ADR_WIFI_PADPD_5700_PHASE_REG3	smac/hal/ssv6006c/ssv6006C_reg.h	1757;"	d
+ADR_WIFI_PADPD_5700_PHASE_REG4	smac/hal/ssv6006c/ssv6006C_reg.h	1758;"	d
+ADR_WIFI_PADPD_5700_PHASE_REG5	smac/hal/ssv6006c/ssv6006C_reg.h	1759;"	d
+ADR_WIFI_PADPD_5700_PHASE_REG6	smac/hal/ssv6006c/ssv6006C_reg.h	1760;"	d
+ADR_WIFI_PADPD_5700_PHASE_REG7	smac/hal/ssv6006c/ssv6006C_reg.h	1761;"	d
+ADR_WIFI_PADPD_5700_PHASE_REG8	smac/hal/ssv6006c/ssv6006C_reg.h	1762;"	d
+ADR_WIFI_PADPD_5700_PHASE_REG9	smac/hal/ssv6006c/ssv6006C_reg.h	1763;"	d
+ADR_WIFI_PADPD_5700_PHASE_REGA	smac/hal/ssv6006c/ssv6006C_reg.h	1764;"	d
+ADR_WIFI_PADPD_5700_PHASE_REGB	smac/hal/ssv6006c/ssv6006C_reg.h	1765;"	d
+ADR_WIFI_PADPD_5700_PHASE_REGC	smac/hal/ssv6006c/ssv6006C_reg.h	1766;"	d
+ADR_WIFI_PADPD_5900_GAIN_REG0	smac/hal/ssv6006c/ssv6006C_reg.h	1767;"	d
+ADR_WIFI_PADPD_5900_GAIN_REG1	smac/hal/ssv6006c/ssv6006C_reg.h	1768;"	d
+ADR_WIFI_PADPD_5900_GAIN_REG2	smac/hal/ssv6006c/ssv6006C_reg.h	1769;"	d
+ADR_WIFI_PADPD_5900_GAIN_REG3	smac/hal/ssv6006c/ssv6006C_reg.h	1770;"	d
+ADR_WIFI_PADPD_5900_GAIN_REG4	smac/hal/ssv6006c/ssv6006C_reg.h	1771;"	d
+ADR_WIFI_PADPD_5900_GAIN_REG5	smac/hal/ssv6006c/ssv6006C_reg.h	1772;"	d
+ADR_WIFI_PADPD_5900_GAIN_REG6	smac/hal/ssv6006c/ssv6006C_reg.h	1773;"	d
+ADR_WIFI_PADPD_5900_GAIN_REG7	smac/hal/ssv6006c/ssv6006C_reg.h	1774;"	d
+ADR_WIFI_PADPD_5900_GAIN_REG8	smac/hal/ssv6006c/ssv6006C_reg.h	1775;"	d
+ADR_WIFI_PADPD_5900_GAIN_REG9	smac/hal/ssv6006c/ssv6006C_reg.h	1776;"	d
+ADR_WIFI_PADPD_5900_GAIN_REGA	smac/hal/ssv6006c/ssv6006C_reg.h	1777;"	d
+ADR_WIFI_PADPD_5900_GAIN_REGB	smac/hal/ssv6006c/ssv6006C_reg.h	1778;"	d
+ADR_WIFI_PADPD_5900_GAIN_REGC	smac/hal/ssv6006c/ssv6006C_reg.h	1779;"	d
+ADR_WIFI_PADPD_5900_PHASE_REG0	smac/hal/ssv6006c/ssv6006C_reg.h	1780;"	d
+ADR_WIFI_PADPD_5900_PHASE_REG1	smac/hal/ssv6006c/ssv6006C_reg.h	1781;"	d
+ADR_WIFI_PADPD_5900_PHASE_REG2	smac/hal/ssv6006c/ssv6006C_reg.h	1782;"	d
+ADR_WIFI_PADPD_5900_PHASE_REG3	smac/hal/ssv6006c/ssv6006C_reg.h	1783;"	d
+ADR_WIFI_PADPD_5900_PHASE_REG4	smac/hal/ssv6006c/ssv6006C_reg.h	1784;"	d
+ADR_WIFI_PADPD_5900_PHASE_REG5	smac/hal/ssv6006c/ssv6006C_reg.h	1785;"	d
+ADR_WIFI_PADPD_5900_PHASE_REG6	smac/hal/ssv6006c/ssv6006C_reg.h	1786;"	d
+ADR_WIFI_PADPD_5900_PHASE_REG7	smac/hal/ssv6006c/ssv6006C_reg.h	1787;"	d
+ADR_WIFI_PADPD_5900_PHASE_REG8	smac/hal/ssv6006c/ssv6006C_reg.h	1788;"	d
+ADR_WIFI_PADPD_5900_PHASE_REG9	smac/hal/ssv6006c/ssv6006C_reg.h	1789;"	d
+ADR_WIFI_PADPD_5900_PHASE_REGA	smac/hal/ssv6006c/ssv6006C_reg.h	1790;"	d
+ADR_WIFI_PADPD_5900_PHASE_REGB	smac/hal/ssv6006c/ssv6006C_reg.h	1791;"	d
+ADR_WIFI_PADPD_5900_PHASE_REGC	smac/hal/ssv6006c/ssv6006C_reg.h	1792;"	d
+ADR_WIFI_PADPD_5G_BB_GAIN_REG	smac/hal/ssv6006c/ssv6006C_reg.h	1829;"	d
+ADR_WIFI_PADPD_CAL_RX_PADPD_REG	smac/hal/ssv6006c/ssv6006C_reg.h	1794;"	d
+ADR_WIFI_PADPD_CAL_RX_RO	smac/hal/ssv6006c/ssv6006C_reg.h	1795;"	d
+ADR_WIFI_PADPD_CAL_TONEGEN_REG	smac/hal/ssv6006c/ssv6006C_reg.h	1793;"	d
+ADR_WIFI_PADPD_CFR	smac/hal/ssv6006c/ssv6006C_reg.h	1796;"	d
+ADR_WIFI_PADPD_DC_RM	smac/hal/ssv6006c/ssv6006C_reg.h	1797;"	d
+ADR_WIFI_PADPD_RESERVED_REG	smac/hal/ssv6006c/ssv6006C_reg.h	1845;"	d
+ADR_WIFI_PADPD_TXIQ_CLIP_REG	smac/hal/ssv6006c/ssv6006C_reg.h	1798;"	d
+ADR_WIFI_PADPD_TXIQ_CONTROL_REG	smac/hal/ssv6006c/ssv6006C_reg.h	1799;"	d
+ADR_WIFI_PADPD_TXIQ_DC_OFFSET_REG	smac/hal/ssv6006c/ssv6006C_reg.h	1801;"	d
+ADR_WIFI_PADPD_TXIQ_DPD_DC_REG	smac/hal/ssv6006c/ssv6006C_reg.h	1800;"	d
+ADR_WIFI_PADPD_TX_GAIN_0P5DB_REG	smac/hal/ssv6006c/ssv6006C_reg.h	1831;"	d
+ADR_WIFI_PHY_AGC_RELOCK_1	smac/hal/ssv6006c/ssv6006C_reg.h	1912;"	d
+ADR_WIFI_PHY_AGC_RELOCK_2	smac/hal/ssv6006c/ssv6006C_reg.h	1913;"	d
+ADR_WIFI_PHY_AUDIO_CLK_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	1958;"	d
+ADR_WIFI_PHY_COMMON_11BGN_DIGPWR_REG	smac/hal/ssv6006c/ssv6006C_reg.h	1901;"	d
+ADR_WIFI_PHY_COMMON_11B_DAGC_REG0	smac/hal/ssv6006c/ssv6006C_reg.h	1897;"	d
+ADR_WIFI_PHY_COMMON_11B_DAGC_REG1	smac/hal/ssv6006c/ssv6006C_reg.h	1898;"	d
+ADR_WIFI_PHY_COMMON_11GN20_DAGC_REG0	smac/hal/ssv6006c/ssv6006C_reg.h	1899;"	d
+ADR_WIFI_PHY_COMMON_11GN20_DAGC_REG1	smac/hal/ssv6006c/ssv6006C_reg.h	1900;"	d
+ADR_WIFI_PHY_COMMON_11GN40_DAGC_REG0	smac/hal/ssv6006c/ssv6006C_reg.h	1922;"	d
+ADR_WIFI_PHY_COMMON_11GN40_DAGC_REG1	smac/hal/ssv6006c/ssv6006C_reg.h	1923;"	d
+ADR_WIFI_PHY_COMMON_11GN_DAGC_INI_REG	smac/hal/ssv6006c/ssv6006C_reg.h	1924;"	d
+ADR_WIFI_PHY_COMMON_BB_SCALE_REG_0	smac/hal/ssv6006c/ssv6006C_reg.h	1936;"	d
+ADR_WIFI_PHY_COMMON_BB_SCALE_REG_1	smac/hal/ssv6006c/ssv6006C_reg.h	1937;"	d
+ADR_WIFI_PHY_COMMON_BB_SCALE_REG_2	smac/hal/ssv6006c/ssv6006C_reg.h	1938;"	d
+ADR_WIFI_PHY_COMMON_BB_SCALE_REG_3	smac/hal/ssv6006c/ssv6006C_reg.h	1939;"	d
+ADR_WIFI_PHY_COMMON_DES_REG0	smac/hal/ssv6006c/ssv6006C_reg.h	1884;"	d
+ADR_WIFI_PHY_COMMON_DES_REG1	smac/hal/ssv6006c/ssv6006C_reg.h	1885;"	d
+ADR_WIFI_PHY_COMMON_DES_REG2	smac/hal/ssv6006c/ssv6006C_reg.h	1886;"	d
+ADR_WIFI_PHY_COMMON_DES_REG3	smac/hal/ssv6006c/ssv6006C_reg.h	1887;"	d
+ADR_WIFI_PHY_COMMON_DES_REG4	smac/hal/ssv6006c/ssv6006C_reg.h	1888;"	d
+ADR_WIFI_PHY_COMMON_DES_REG5	smac/hal/ssv6006c/ssv6006C_reg.h	1890;"	d
+ADR_WIFI_PHY_COMMON_DES_REG6	smac/hal/ssv6006c/ssv6006C_reg.h	1891;"	d
+ADR_WIFI_PHY_COMMON_EDCCA_0	smac/hal/ssv6006c/ssv6006C_reg.h	1909;"	d
+ADR_WIFI_PHY_COMMON_EDCCA_1	smac/hal/ssv6006c/ssv6006C_reg.h	1910;"	d
+ADR_WIFI_PHY_COMMON_EDCCA_2	smac/hal/ssv6006c/ssv6006C_reg.h	1911;"	d
+ADR_WIFI_PHY_COMMON_ENABLE_REG	smac/hal/ssv6006c/ssv6006C_reg.h	1882;"	d
+ADR_WIFI_PHY_COMMON_MAC_IF_CNT_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	1955;"	d
+ADR_WIFI_PHY_COMMON_MAC_IF_CNT_RO	smac/hal/ssv6006c/ssv6006C_reg.h	1956;"	d
+ADR_WIFI_PHY_COMMON_MAC_PKT_REG_0	smac/hal/ssv6006c/ssv6006C_reg.h	1925;"	d
+ADR_WIFI_PHY_COMMON_MAC_PKT_REG_1	smac/hal/ssv6006c/ssv6006C_reg.h	1926;"	d
+ADR_WIFI_PHY_COMMON_MAC_PKT_REG_2	smac/hal/ssv6006c/ssv6006C_reg.h	1927;"	d
+ADR_WIFI_PHY_COMMON_MAC_PKT_REG_3	smac/hal/ssv6006c/ssv6006C_reg.h	1928;"	d
+ADR_WIFI_PHY_COMMON_MAC_PKT_REG_4	smac/hal/ssv6006c/ssv6006C_reg.h	1929;"	d
+ADR_WIFI_PHY_COMMON_MAC_PKT_REG_5	smac/hal/ssv6006c/ssv6006C_reg.h	1930;"	d
+ADR_WIFI_PHY_COMMON_MAC_PKT_REG_6	smac/hal/ssv6006c/ssv6006C_reg.h	1931;"	d
+ADR_WIFI_PHY_COMMON_MAC_PKT_REG_7	smac/hal/ssv6006c/ssv6006C_reg.h	1932;"	d
+ADR_WIFI_PHY_COMMON_MAC_PKT_REG_8	smac/hal/ssv6006c/ssv6006C_reg.h	1933;"	d
+ADR_WIFI_PHY_COMMON_MAC_PKT_REG_9	smac/hal/ssv6006c/ssv6006C_reg.h	1934;"	d
+ADR_WIFI_PHY_COMMON_MAC_PKT_REG_A	smac/hal/ssv6006c/ssv6006C_reg.h	1935;"	d
+ADR_WIFI_PHY_COMMON_RESERVED_REG	smac/hal/ssv6006c/ssv6006C_reg.h	1960;"	d
+ADR_WIFI_PHY_COMMON_RFAGC_REG0	smac/hal/ssv6006c/ssv6006C_reg.h	1892;"	d
+ADR_WIFI_PHY_COMMON_RFAGC_REG1	smac/hal/ssv6006c/ssv6006C_reg.h	1893;"	d
+ADR_WIFI_PHY_COMMON_RFAGC_REG2	smac/hal/ssv6006c/ssv6006C_reg.h	1894;"	d
+ADR_WIFI_PHY_COMMON_RFAGC_REG3	smac/hal/ssv6006c/ssv6006C_reg.h	1895;"	d
+ADR_WIFI_PHY_COMMON_RFAGC_REG4	smac/hal/ssv6006c/ssv6006C_reg.h	1896;"	d
+ADR_WIFI_PHY_COMMON_RFAGC_RO00	smac/hal/ssv6006c/ssv6006C_reg.h	1902;"	d
+ADR_WIFI_PHY_COMMON_RFAGC_RO01	smac/hal/ssv6006c/ssv6006C_reg.h	1903;"	d
+ADR_WIFI_PHY_COMMON_RFAGC_RO02	smac/hal/ssv6006c/ssv6006C_reg.h	1904;"	d
+ADR_WIFI_PHY_COMMON_RF_PWR_REG_0	smac/hal/ssv6006c/ssv6006C_reg.h	1940;"	d
+ADR_WIFI_PHY_COMMON_RF_PWR_REG_1	smac/hal/ssv6006c/ssv6006C_reg.h	1941;"	d
+ADR_WIFI_PHY_COMMON_RF_PWR_REG_2	smac/hal/ssv6006c/ssv6006C_reg.h	1942;"	d
+ADR_WIFI_PHY_COMMON_RF_PWR_REG_3	smac/hal/ssv6006c/ssv6006C_reg.h	1943;"	d
+ADR_WIFI_PHY_COMMON_RSSI_TBUS_REG	smac/hal/ssv6006c/ssv6006C_reg.h	1907;"	d
+ADR_WIFI_PHY_COMMON_RXDC	smac/hal/ssv6006c/ssv6006C_reg.h	1905;"	d
+ADR_WIFI_PHY_COMMON_RXDC_RO	smac/hal/ssv6006c/ssv6006C_reg.h	1906;"	d
+ADR_WIFI_PHY_COMMON_RX_BKN_MON_RO	smac/hal/ssv6006c/ssv6006C_reg.h	1954;"	d
+ADR_WIFI_PHY_COMMON_RX_EN_CNT_REG	smac/hal/ssv6006c/ssv6006C_reg.h	1908;"	d
+ADR_WIFI_PHY_COMMON_RX_FFT_MEM_BIST_REG	smac/hal/ssv6006c/ssv6006C_reg.h	1957;"	d
+ADR_WIFI_PHY_COMMON_RX_LENGTH_CNT_REG0	smac/hal/ssv6006c/ssv6006C_reg.h	1916;"	d
+ADR_WIFI_PHY_COMMON_RX_LENGTH_CNT_REG1	smac/hal/ssv6006c/ssv6006C_reg.h	1917;"	d
+ADR_WIFI_PHY_COMMON_RX_LENGTH_CNT_RO	smac/hal/ssv6006c/ssv6006C_reg.h	1919;"	d
+ADR_WIFI_PHY_COMMON_RX_MON_0	smac/hal/ssv6006c/ssv6006C_reg.h	1944;"	d
+ADR_WIFI_PHY_COMMON_RX_MON_1	smac/hal/ssv6006c/ssv6006C_reg.h	1945;"	d
+ADR_WIFI_PHY_COMMON_RX_MON_2	smac/hal/ssv6006c/ssv6006C_reg.h	1946;"	d
+ADR_WIFI_PHY_COMMON_RX_MON_3	smac/hal/ssv6006c/ssv6006C_reg.h	1947;"	d
+ADR_WIFI_PHY_COMMON_RX_MON_4	smac/hal/ssv6006c/ssv6006C_reg.h	1948;"	d
+ADR_WIFI_PHY_COMMON_RX_MON_5	smac/hal/ssv6006c/ssv6006C_reg.h	1949;"	d
+ADR_WIFI_PHY_COMMON_RX_MON_6	smac/hal/ssv6006c/ssv6006C_reg.h	1950;"	d
+ADR_WIFI_PHY_COMMON_RX_MON_7	smac/hal/ssv6006c/ssv6006C_reg.h	1951;"	d
+ADR_WIFI_PHY_COMMON_RX_MON_8	smac/hal/ssv6006c/ssv6006C_reg.h	1952;"	d
+ADR_WIFI_PHY_COMMON_RX_TMR_MON_RO	smac/hal/ssv6006c/ssv6006C_reg.h	1953;"	d
+ADR_WIFI_PHY_COMMON_SYS_REG	smac/hal/ssv6006c/ssv6006C_reg.h	1881;"	d
+ADR_WIFI_PHY_COMMON_TOP_STATUS_RO	smac/hal/ssv6006c/ssv6006C_reg.h	1959;"	d
+ADR_WIFI_PHY_COMMON_TRX_TYPE_CNT_REG	smac/hal/ssv6006c/ssv6006C_reg.h	1920;"	d
+ADR_WIFI_PHY_COMMON_TRX_TYPE_CNT_RO	smac/hal/ssv6006c/ssv6006C_reg.h	1921;"	d
+ADR_WIFI_PHY_COMMON_TX_CONTROL	smac/hal/ssv6006c/ssv6006C_reg.h	1889;"	d
+ADR_WIFI_PHY_COMMON_TX_LENGTH_CNT_REG0	smac/hal/ssv6006c/ssv6006C_reg.h	1914;"	d
+ADR_WIFI_PHY_COMMON_TX_LENGTH_CNT_REG1	smac/hal/ssv6006c/ssv6006C_reg.h	1915;"	d
+ADR_WIFI_PHY_COMMON_TX_LENGTH_CNT_RO	smac/hal/ssv6006c/ssv6006C_reg.h	1918;"	d
+ADR_WIFI_PHY_COMMON_VERSION_REG	smac/hal/ssv6006c/ssv6006C_reg.h	1883;"	d
+ADR_WIFI_R2T_TIMER_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1586;"	d
+ADR_WIFI_RADAR_CHIRP_REG	smac/hal/ssv6006c/ssv6006C_reg.h	2066;"	d
+ADR_WIFI_RADAR_REG_00	smac/hal/ssv6006c/ssv6006C_reg.h	2054;"	d
+ADR_WIFI_RADAR_REG_01	smac/hal/ssv6006c/ssv6006C_reg.h	2055;"	d
+ADR_WIFI_RADAR_REG_02	smac/hal/ssv6006c/ssv6006C_reg.h	2056;"	d
+ADR_WIFI_RADAR_REG_03	smac/hal/ssv6006c/ssv6006C_reg.h	2057;"	d
+ADR_WIFI_RADAR_REG_04	smac/hal/ssv6006c/ssv6006C_reg.h	2058;"	d
+ADR_WIFI_RADAR_REG_DB_A0_RO	smac/hal/ssv6006c/ssv6006C_reg.h	2060;"	d
+ADR_WIFI_RADAR_REG_DB_A1_RO	smac/hal/ssv6006c/ssv6006C_reg.h	2061;"	d
+ADR_WIFI_RADAR_REG_DB_A2_RO	smac/hal/ssv6006c/ssv6006C_reg.h	2062;"	d
+ADR_WIFI_RADAR_REG_DB_P0_RO	smac/hal/ssv6006c/ssv6006C_reg.h	2063;"	d
+ADR_WIFI_RADAR_REG_DB_P1_RO	smac/hal/ssv6006c/ssv6006C_reg.h	2064;"	d
+ADR_WIFI_RADAR_REG_DB_P2_RO	smac/hal/ssv6006c/ssv6006C_reg.h	2065;"	d
+ADR_WIFI_RADAR_REG_RO	smac/hal/ssv6006c/ssv6006C_reg.h	2059;"	d
+ADR_WIFI_T2R_TIMER_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1585;"	d
+ADR_WIFI_TX_DAC_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	1530;"	d
+ADR_WR_ALC	include/ssv6200_reg.h	929;"	d
+ADR_WR_ALC	smac/hal/ssv6006c/ssv6006C_reg.h	2107;"	d
+ADR_WSID0	include/ssv6200_reg.h	686;"	d
+ADR_WSID0	smac/hal/ssv6006c/ssv6006C_reg.h	900;"	d
+ADR_WSID0_TID0_RX_SEQ	include/ssv6200_reg.h	602;"	d
+ADR_WSID0_TID1_RX_SEQ	include/ssv6200_reg.h	603;"	d
+ADR_WSID0_TID2_RX_SEQ	include/ssv6200_reg.h	604;"	d
+ADR_WSID0_TID3_RX_SEQ	include/ssv6200_reg.h	605;"	d
+ADR_WSID0_TID4_RX_SEQ	include/ssv6200_reg.h	606;"	d
+ADR_WSID0_TID5_RX_SEQ	include/ssv6200_reg.h	607;"	d
+ADR_WSID0_TID6_RX_SEQ	include/ssv6200_reg.h	608;"	d
+ADR_WSID0_TID7_RX_SEQ	include/ssv6200_reg.h	609;"	d
+ADR_WSID1	include/ssv6200_reg.h	705;"	d
+ADR_WSID1	smac/hal/ssv6006c/ssv6006C_reg.h	919;"	d
+ADR_WSID1_TID0_RX_SEQ	include/ssv6200_reg.h	610;"	d
+ADR_WSID1_TID1_RX_SEQ	include/ssv6200_reg.h	611;"	d
+ADR_WSID1_TID2_RX_SEQ	include/ssv6200_reg.h	612;"	d
+ADR_WSID1_TID3_RX_SEQ	include/ssv6200_reg.h	613;"	d
+ADR_WSID1_TID4_RX_SEQ	include/ssv6200_reg.h	614;"	d
+ADR_WSID1_TID5_RX_SEQ	include/ssv6200_reg.h	615;"	d
+ADR_WSID1_TID6_RX_SEQ	include/ssv6200_reg.h	616;"	d
+ADR_WSID1_TID7_RX_SEQ	include/ssv6200_reg.h	617;"	d
+ADR_WSID2	smac/hal/ssv6006c/ssv6006C_reg.h	1026;"	d
+ADR_WSID3	smac/hal/ssv6006c/ssv6006C_reg.h	1045;"	d
+ADR_WSID4	smac/hal/ssv6006c/ssv6006C_reg.h	1064;"	d
+ADR_WSID5	smac/hal/ssv6006c/ssv6006C_reg.h	1083;"	d
+ADR_WSID6	smac/hal/ssv6006c/ssv6006C_reg.h	1102;"	d
+ADR_WSID7	smac/hal/ssv6006c/ssv6006C_reg.h	1121;"	d
+AD_CIRCUIT_VERSION_HI	include/ssv6200_aux.h	17599;"	d
+AD_CIRCUIT_VERSION_I_MSK	include/ssv6200_aux.h	17597;"	d
+AD_CIRCUIT_VERSION_MSK	include/ssv6200_aux.h	17596;"	d
+AD_CIRCUIT_VERSION_SFT	include/ssv6200_aux.h	17598;"	d
+AD_CIRCUIT_VERSION_SZ	include/ssv6200_aux.h	17600;"	d
+AD_DP_VT_MON_Q_HI	include/ssv6200_aux.h	17579;"	d
+AD_DP_VT_MON_Q_I_MSK	include/ssv6200_aux.h	17577;"	d
+AD_DP_VT_MON_Q_MSK	include/ssv6200_aux.h	17576;"	d
+AD_DP_VT_MON_Q_SFT	include/ssv6200_aux.h	17578;"	d
+AD_DP_VT_MON_Q_SZ	include/ssv6200_aux.h	17580;"	d
+AD_SX_VT_MON_Q_HI	include/ssv6200_aux.h	17574;"	d
+AD_SX_VT_MON_Q_I_MSK	include/ssv6200_aux.h	17572;"	d
+AD_SX_VT_MON_Q_MSK	include/ssv6200_aux.h	17571;"	d
+AD_SX_VT_MON_Q_SFT	include/ssv6200_aux.h	17573;"	d
+AD_SX_VT_MON_Q_SZ	include/ssv6200_aux.h	17575;"	d
+AES_BLOCK_LEN	smac/sec_ccmp.c	33;"	d	file:
+AES_CTX	crypto/aes_glue.c	/^struct AES_CTX {$/;"	s	file:
+AES_CTX::dec_key	crypto/aes_glue.c	/^ AES_KEY dec_key;$/;"	m	struct:AES_CTX	file:	access:public
+AES_CTX::enc_key	crypto/aes_glue.c	/^ AES_KEY enc_key;$/;"	m	struct:AES_CTX	file:	access:public
+AES_KEY	crypto/aes_glue.c	/^} AES_KEY;$/;"	t	typeref:struct:__anon41	file:
+AES_MAXNR	crypto/aes_glue.c	19;"	d	file:
+AES_Td	crypto/aes-armv4.S	/^AES_Td:$/;"	l
+AES_Te	crypto/aes-armv4.S	/^AES_Te:$/;"	l
+AES_decrypt	crypto/aes-armv4.S	/^AES_decrypt:$/;"	l
+AES_decrypt	crypto/aes_glue.c	/^asmlinkage void AES_decrypt(const u8 *in, u8 *out, AES_KEY *ctx);$/;"	p	file:	signature:(const u8 *in, u8 *out, AES_KEY *ctx)
+AES_encrypt	crypto/aes-armv4.S	/^AES_encrypt:$/;"	l
+AES_encrypt	crypto/aes_glue.c	/^asmlinkage void AES_encrypt(const u8 *in, u8 *out, AES_KEY *ctx);$/;"	p	file:	signature:(const u8 *in, u8 *out, AES_KEY *ctx)
+AG_BAND_BOTH	smac/hal/ssv6006c/turismo_common.h	/^    AG_BAND_BOTH = 1,$/;"	e	enum:__anon3
+AHB2PKT_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1244;"	d
+AHB2PKT_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1242;"	d
+AHB2PKT_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1241;"	d
+AHB2PKT_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1243;"	d
+AHB2PKT_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1245;"	d
+AHB_BRIDGE_RESET_HI	include/ssv6200_aux.h	3414;"	d
+AHB_BRIDGE_RESET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2759;"	d
+AHB_BRIDGE_RESET_I_MSK	include/ssv6200_aux.h	3412;"	d
+AHB_BRIDGE_RESET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2757;"	d
+AHB_BRIDGE_RESET_MSK	include/ssv6200_aux.h	3411;"	d
+AHB_BRIDGE_RESET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2756;"	d
+AHB_BRIDGE_RESET_SFT	include/ssv6200_aux.h	3413;"	d
+AHB_BRIDGE_RESET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2758;"	d
+AHB_BRIDGE_RESET_SZ	include/ssv6200_aux.h	3415;"	d
+AHB_BRIDGE_RESET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2760;"	d
+AHB_ERR_RST_HI	include/ssv6200_aux.h	329;"	d
+AHB_ERR_RST_I_MSK	include/ssv6200_aux.h	327;"	d
+AHB_ERR_RST_MSK	include/ssv6200_aux.h	326;"	d
+AHB_ERR_RST_SFT	include/ssv6200_aux.h	328;"	d
+AHB_ERR_RST_SZ	include/ssv6200_aux.h	330;"	d
+AHB_FEN_ADDR_HI	include/ssv6200_aux.h	454;"	d
+AHB_FEN_ADDR_I_MSK	include/ssv6200_aux.h	452;"	d
+AHB_FEN_ADDR_MSK	include/ssv6200_aux.h	451;"	d
+AHB_FEN_ADDR_SFT	include/ssv6200_aux.h	453;"	d
+AHB_FEN_ADDR_SZ	include/ssv6200_aux.h	455;"	d
+AHB_HANG2_HI	include/ssv6200_aux.h	3514;"	d
+AHB_HANG2_I_MSK	include/ssv6200_aux.h	3512;"	d
+AHB_HANG2_MSK	include/ssv6200_aux.h	3511;"	d
+AHB_HANG2_SFT	include/ssv6200_aux.h	3513;"	d
+AHB_HANG2_SZ	include/ssv6200_aux.h	3515;"	d
+AHB_HANG4_HI	include/ssv6200_aux.h	3249;"	d
+AHB_HANG4_I_MSK	include/ssv6200_aux.h	3247;"	d
+AHB_HANG4_MSK	include/ssv6200_aux.h	3246;"	d
+AHB_HANG4_SFT	include/ssv6200_aux.h	3248;"	d
+AHB_HANG4_SZ	include/ssv6200_aux.h	3250;"	d
+AHB_ILL_ADDR_HI	include/ssv6200_aux.h	449;"	d
+AHB_ILL_ADDR_I_MSK	include/ssv6200_aux.h	447;"	d
+AHB_ILL_ADDR_MSK	include/ssv6200_aux.h	446;"	d
+AHB_ILL_ADDR_SFT	include/ssv6200_aux.h	448;"	d
+AHB_ILL_ADDR_SZ	include/ssv6200_aux.h	450;"	d
+AHB_STATUS_HI	include/ssv6200_aux.h	364;"	d
+AHB_STATUS_I_MSK	include/ssv6200_aux.h	362;"	d
+AHB_STATUS_MSK	include/ssv6200_aux.h	361;"	d
+AHB_STATUS_SFT	include/ssv6200_aux.h	363;"	d
+AHB_STATUS_SZ	include/ssv6200_aux.h	365;"	d
+AHB_SW_RST_HI	include/ssv6200_aux.h	324;"	d
+AHB_SW_RST_I_MSK	include/ssv6200_aux.h	322;"	d
+AHB_SW_RST_MSK	include/ssv6200_aux.h	321;"	d
+AHB_SW_RST_SFT	include/ssv6200_aux.h	323;"	d
+AHB_SW_RST_SZ	include/ssv6200_aux.h	325;"	d
+AIRKISS_ENABLE_CRYPT	smartlink/airkiss-lib/airkiss.h	22;"	d
+AIRKISS_ENABLE_CRYPT	smartlink/airkiss-lib/mipsel/airkiss.h	22;"	d
+AIRKISS_ENABLE_CRYPT	smartlink/airkiss-lib/x64/airkiss.h	22;"	d
+AIRKISS_H_	smartlink/airkiss-lib/airkiss.h	17;"	d
+AIRKISS_H_	smartlink/airkiss-lib/mipsel/airkiss.h	17;"	d
+AIRKISS_H_	smartlink/airkiss-lib/x64/airkiss.h	17;"	d
+AIRKISS_LAN_CONTINUE	smartlink/airkiss-lib/airkiss.h	/^ AIRKISS_LAN_CONTINUE = 0,$/;"	e	enum:__anon27
+AIRKISS_LAN_CONTINUE	smartlink/airkiss-lib/mipsel/airkiss.h	/^ AIRKISS_LAN_CONTINUE = 0,$/;"	e	enum:__anon21
+AIRKISS_LAN_CONTINUE	smartlink/airkiss-lib/x64/airkiss.h	/^ AIRKISS_LAN_CONTINUE = 0,$/;"	e	enum:__anon33
+AIRKISS_LAN_ERR_CMD	smartlink/airkiss-lib/airkiss.h	/^ AIRKISS_LAN_ERR_CMD = -4,$/;"	e	enum:__anon27
+AIRKISS_LAN_ERR_CMD	smartlink/airkiss-lib/mipsel/airkiss.h	/^ AIRKISS_LAN_ERR_CMD = -4,$/;"	e	enum:__anon21
+AIRKISS_LAN_ERR_CMD	smartlink/airkiss-lib/x64/airkiss.h	/^ AIRKISS_LAN_ERR_CMD = -4,$/;"	e	enum:__anon33
+AIRKISS_LAN_ERR_OVERFLOW	smartlink/airkiss-lib/airkiss.h	/^ AIRKISS_LAN_ERR_OVERFLOW = -5,$/;"	e	enum:__anon27
+AIRKISS_LAN_ERR_OVERFLOW	smartlink/airkiss-lib/mipsel/airkiss.h	/^ AIRKISS_LAN_ERR_OVERFLOW = -5,$/;"	e	enum:__anon21
+AIRKISS_LAN_ERR_OVERFLOW	smartlink/airkiss-lib/x64/airkiss.h	/^ AIRKISS_LAN_ERR_OVERFLOW = -5,$/;"	e	enum:__anon33
+AIRKISS_LAN_ERR_PAKE	smartlink/airkiss-lib/airkiss.h	/^ AIRKISS_LAN_ERR_PAKE = -3,$/;"	e	enum:__anon27
+AIRKISS_LAN_ERR_PAKE	smartlink/airkiss-lib/mipsel/airkiss.h	/^ AIRKISS_LAN_ERR_PAKE = -3,$/;"	e	enum:__anon21
+AIRKISS_LAN_ERR_PAKE	smartlink/airkiss-lib/x64/airkiss.h	/^ AIRKISS_LAN_ERR_PAKE = -3,$/;"	e	enum:__anon33
+AIRKISS_LAN_ERR_PARA	smartlink/airkiss-lib/airkiss.h	/^ AIRKISS_LAN_ERR_PARA = -2,$/;"	e	enum:__anon27
+AIRKISS_LAN_ERR_PARA	smartlink/airkiss-lib/mipsel/airkiss.h	/^ AIRKISS_LAN_ERR_PARA = -2,$/;"	e	enum:__anon21
+AIRKISS_LAN_ERR_PARA	smartlink/airkiss-lib/x64/airkiss.h	/^ AIRKISS_LAN_ERR_PARA = -2,$/;"	e	enum:__anon33
+AIRKISS_LAN_ERR_PKG	smartlink/airkiss-lib/airkiss.h	/^ AIRKISS_LAN_ERR_PKG = -1,$/;"	e	enum:__anon27
+AIRKISS_LAN_ERR_PKG	smartlink/airkiss-lib/mipsel/airkiss.h	/^ AIRKISS_LAN_ERR_PKG = -1,$/;"	e	enum:__anon21
+AIRKISS_LAN_ERR_PKG	smartlink/airkiss-lib/x64/airkiss.h	/^ AIRKISS_LAN_ERR_PKG = -1,$/;"	e	enum:__anon33
+AIRKISS_LAN_PAKE_READY	smartlink/airkiss-lib/airkiss.h	/^ AIRKISS_LAN_PAKE_READY = 2$/;"	e	enum:__anon27
+AIRKISS_LAN_PAKE_READY	smartlink/airkiss-lib/mipsel/airkiss.h	/^ AIRKISS_LAN_PAKE_READY = 2$/;"	e	enum:__anon21
+AIRKISS_LAN_PAKE_READY	smartlink/airkiss-lib/x64/airkiss.h	/^ AIRKISS_LAN_PAKE_READY = 2$/;"	e	enum:__anon33
+AIRKISS_LAN_SSDP_NOTIFY_CMD	smartlink/airkiss-lib/airkiss.h	/^ AIRKISS_LAN_SSDP_NOTIFY_CMD = 0x1002$/;"	e	enum:__anon28
+AIRKISS_LAN_SSDP_NOTIFY_CMD	smartlink/airkiss-lib/mipsel/airkiss.h	/^ AIRKISS_LAN_SSDP_NOTIFY_CMD = 0x1002$/;"	e	enum:__anon22
+AIRKISS_LAN_SSDP_NOTIFY_CMD	smartlink/airkiss-lib/x64/airkiss.h	/^ AIRKISS_LAN_SSDP_NOTIFY_CMD = 0x1002$/;"	e	enum:__anon34
+AIRKISS_LAN_SSDP_REQ	smartlink/airkiss-lib/airkiss.h	/^ AIRKISS_LAN_SSDP_REQ = 1,$/;"	e	enum:__anon27
+AIRKISS_LAN_SSDP_REQ	smartlink/airkiss-lib/mipsel/airkiss.h	/^ AIRKISS_LAN_SSDP_REQ = 1,$/;"	e	enum:__anon21
+AIRKISS_LAN_SSDP_REQ	smartlink/airkiss-lib/x64/airkiss.h	/^ AIRKISS_LAN_SSDP_REQ = 1,$/;"	e	enum:__anon33
+AIRKISS_LAN_SSDP_REQ_CMD	smartlink/airkiss-lib/airkiss.h	/^ AIRKISS_LAN_SSDP_REQ_CMD = 0x1,$/;"	e	enum:__anon28
+AIRKISS_LAN_SSDP_REQ_CMD	smartlink/airkiss-lib/mipsel/airkiss.h	/^ AIRKISS_LAN_SSDP_REQ_CMD = 0x1,$/;"	e	enum:__anon22
+AIRKISS_LAN_SSDP_REQ_CMD	smartlink/airkiss-lib/x64/airkiss.h	/^ AIRKISS_LAN_SSDP_REQ_CMD = 0x1,$/;"	e	enum:__anon34
+AIRKISS_LAN_SSDP_RESP_CMD	smartlink/airkiss-lib/airkiss.h	/^ AIRKISS_LAN_SSDP_RESP_CMD = 0x1001,$/;"	e	enum:__anon28
+AIRKISS_LAN_SSDP_RESP_CMD	smartlink/airkiss-lib/mipsel/airkiss.h	/^ AIRKISS_LAN_SSDP_RESP_CMD = 0x1001,$/;"	e	enum:__anon22
+AIRKISS_LAN_SSDP_RESP_CMD	smartlink/airkiss-lib/x64/airkiss.h	/^ AIRKISS_LAN_SSDP_RESP_CMD = 0x1001,$/;"	e	enum:__anon34
+AIRKISS_STATUS_CHANNEL_LOCKED	smartlink/airkiss-lib/airkiss.h	/^ AIRKISS_STATUS_CHANNEL_LOCKED = 1,$/;"	e	enum:__anon26
+AIRKISS_STATUS_CHANNEL_LOCKED	smartlink/airkiss-lib/mipsel/airkiss.h	/^ AIRKISS_STATUS_CHANNEL_LOCKED = 1,$/;"	e	enum:__anon20
+AIRKISS_STATUS_CHANNEL_LOCKED	smartlink/airkiss-lib/x64/airkiss.h	/^ AIRKISS_STATUS_CHANNEL_LOCKED = 1,$/;"	e	enum:__anon32
+AIRKISS_STATUS_COMPLETE	smartlink/airkiss-lib/airkiss.h	/^ AIRKISS_STATUS_COMPLETE = 2$/;"	e	enum:__anon26
+AIRKISS_STATUS_COMPLETE	smartlink/airkiss-lib/mipsel/airkiss.h	/^ AIRKISS_STATUS_COMPLETE = 2$/;"	e	enum:__anon20
+AIRKISS_STATUS_COMPLETE	smartlink/airkiss-lib/x64/airkiss.h	/^ AIRKISS_STATUS_COMPLETE = 2$/;"	e	enum:__anon32
+AIRKISS_STATUS_CONTINUE	smartlink/airkiss-lib/airkiss.h	/^ AIRKISS_STATUS_CONTINUE = 0,$/;"	e	enum:__anon26
+AIRKISS_STATUS_CONTINUE	smartlink/airkiss-lib/mipsel/airkiss.h	/^ AIRKISS_STATUS_CONTINUE = 0,$/;"	e	enum:__anon20
+AIRKISS_STATUS_CONTINUE	smartlink/airkiss-lib/x64/airkiss.h	/^ AIRKISS_STATUS_CONTINUE = 0,$/;"	e	enum:__anon32
+ALC_ABT_CLR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34524;"	d
+ALC_ABT_CLR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34522;"	d
+ALC_ABT_CLR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34521;"	d
+ALC_ABT_CLR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34523;"	d
+ALC_ABT_CLR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34525;"	d
+ALC_ABT_ID_HI	include/ssv6200_aux.h	17879;"	d
+ALC_ABT_ID_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34514;"	d
+ALC_ABT_ID_I_MSK	include/ssv6200_aux.h	17877;"	d
+ALC_ABT_ID_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34512;"	d
+ALC_ABT_ID_MSK	include/ssv6200_aux.h	17876;"	d
+ALC_ABT_ID_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34511;"	d
+ALC_ABT_ID_SFT	include/ssv6200_aux.h	17878;"	d
+ALC_ABT_ID_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34513;"	d
+ALC_ABT_ID_SZ	include/ssv6200_aux.h	17880;"	d
+ALC_ABT_ID_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34515;"	d
+ALC_ABT_INT_HI	include/ssv6200_aux.h	17884;"	d
+ALC_ABT_INT_I_MSK	include/ssv6200_aux.h	17882;"	d
+ALC_ABT_INT_MSK	include/ssv6200_aux.h	17881;"	d
+ALC_ABT_INT_SFT	include/ssv6200_aux.h	17883;"	d
+ALC_ABT_INT_SZ	include/ssv6200_aux.h	17885;"	d
+ALC_ABT_STS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34519;"	d
+ALC_ABT_STS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34517;"	d
+ALC_ABT_STS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34516;"	d
+ALC_ABT_STS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34518;"	d
+ALC_ABT_STS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34520;"	d
+ALC_BUSY_HI	include/ssv6200_aux.h	12589;"	d
+ALC_BUSY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34114;"	d
+ALC_BUSY_I_MSK	include/ssv6200_aux.h	12587;"	d
+ALC_BUSY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34112;"	d
+ALC_BUSY_MSK	include/ssv6200_aux.h	12586;"	d
+ALC_BUSY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34111;"	d
+ALC_BUSY_SFT	include/ssv6200_aux.h	12588;"	d
+ALC_BUSY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34113;"	d
+ALC_BUSY_SZ	include/ssv6200_aux.h	12590;"	d
+ALC_BUSY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34115;"	d
+ALC_ERR_CLR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34539;"	d
+ALC_ERR_CLR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34537;"	d
+ALC_ERR_CLR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34536;"	d
+ALC_ERR_CLR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34538;"	d
+ALC_ERR_CLR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34540;"	d
+ALC_ERR_HI	include/ssv6200_aux.h	17914;"	d
+ALC_ERR_ID_HI	include/ssv6200_aux.h	17934;"	d
+ALC_ERR_ID_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34559;"	d
+ALC_ERR_ID_I_MSK	include/ssv6200_aux.h	17932;"	d
+ALC_ERR_ID_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34557;"	d
+ALC_ERR_ID_MSK	include/ssv6200_aux.h	17931;"	d
+ALC_ERR_ID_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34556;"	d
+ALC_ERR_ID_SFT	include/ssv6200_aux.h	17933;"	d
+ALC_ERR_ID_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34558;"	d
+ALC_ERR_ID_SZ	include/ssv6200_aux.h	17935;"	d
+ALC_ERR_ID_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34560;"	d
+ALC_ERR_I_MSK	include/ssv6200_aux.h	17912;"	d
+ALC_ERR_MSK	include/ssv6200_aux.h	17911;"	d
+ALC_ERR_SFT	include/ssv6200_aux.h	17913;"	d
+ALC_ERR_STS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34529;"	d
+ALC_ERR_STS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34527;"	d
+ALC_ERR_STS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34526;"	d
+ALC_ERR_STS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34528;"	d
+ALC_ERR_STS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34530;"	d
+ALC_ERR_SZ	include/ssv6200_aux.h	17915;"	d
+ALC_FAIL_HI	include/ssv6200_aux.h	12584;"	d
+ALC_FAIL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34109;"	d
+ALC_FAIL_I_MSK	include/ssv6200_aux.h	12582;"	d
+ALC_FAIL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34107;"	d
+ALC_FAIL_MSK	include/ssv6200_aux.h	12581;"	d
+ALC_FAIL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34106;"	d
+ALC_FAIL_SFT	include/ssv6200_aux.h	12583;"	d
+ALC_FAIL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34108;"	d
+ALC_FAIL_SZ	include/ssv6200_aux.h	12585;"	d
+ALC_FAIL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34110;"	d
+ALC_INT_ID_HI	include/ssv6200_aux.h	12614;"	d
+ALC_INT_ID_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34139;"	d
+ALC_INT_ID_I_MSK	include/ssv6200_aux.h	12612;"	d
+ALC_INT_ID_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34137;"	d
+ALC_INT_ID_MSK	include/ssv6200_aux.h	12611;"	d
+ALC_INT_ID_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34136;"	d
+ALC_INT_ID_SFT	include/ssv6200_aux.h	12613;"	d
+ALC_INT_ID_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34138;"	d
+ALC_INT_ID_SZ	include/ssv6200_aux.h	12615;"	d
+ALC_INT_ID_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34140;"	d
+ALC_LENG_HI	include/ssv6200_aux.h	12469;"	d
+ALC_LENG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33994;"	d
+ALC_LENG_I_MSK	include/ssv6200_aux.h	12467;"	d
+ALC_LENG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33992;"	d
+ALC_LENG_MSK	include/ssv6200_aux.h	12466;"	d
+ALC_LENG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33991;"	d
+ALC_LENG_SFT	include/ssv6200_aux.h	12468;"	d
+ALC_LENG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33993;"	d
+ALC_LENG_SZ	include/ssv6200_aux.h	12470;"	d
+ALC_LENG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33995;"	d
+ALC_NOCHG_ID_HI	include/ssv6200_aux.h	18124;"	d
+ALC_NOCHG_ID_I_MSK	include/ssv6200_aux.h	18122;"	d
+ALC_NOCHG_ID_MSK	include/ssv6200_aux.h	18121;"	d
+ALC_NOCHG_ID_SFT	include/ssv6200_aux.h	18123;"	d
+ALC_NOCHG_ID_SZ	include/ssv6200_aux.h	18125;"	d
+ALC_NOCHG_INT_HI	include/ssv6200_aux.h	18129;"	d
+ALC_NOCHG_INT_I_MSK	include/ssv6200_aux.h	18127;"	d
+ALC_NOCHG_INT_MSK	include/ssv6200_aux.h	18126;"	d
+ALC_NOCHG_INT_SFT	include/ssv6200_aux.h	18128;"	d
+ALC_NOCHG_INT_SZ	include/ssv6200_aux.h	18130;"	d
+ALC_TIMEOUT_HI	include/ssv6200_aux.h	12619;"	d
+ALC_TIMEOUT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34144;"	d
+ALC_TIMEOUT_INT_EN_HI	include/ssv6200_aux.h	12624;"	d
+ALC_TIMEOUT_INT_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34149;"	d
+ALC_TIMEOUT_INT_EN_I_MSK	include/ssv6200_aux.h	12622;"	d
+ALC_TIMEOUT_INT_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34147;"	d
+ALC_TIMEOUT_INT_EN_MSK	include/ssv6200_aux.h	12621;"	d
+ALC_TIMEOUT_INT_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34146;"	d
+ALC_TIMEOUT_INT_EN_SFT	include/ssv6200_aux.h	12623;"	d
+ALC_TIMEOUT_INT_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34148;"	d
+ALC_TIMEOUT_INT_EN_SZ	include/ssv6200_aux.h	12625;"	d
+ALC_TIMEOUT_INT_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34150;"	d
+ALC_TIMEOUT_INT_HI	include/ssv6200_aux.h	12629;"	d
+ALC_TIMEOUT_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34154;"	d
+ALC_TIMEOUT_INT_I_MSK	include/ssv6200_aux.h	12627;"	d
+ALC_TIMEOUT_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34152;"	d
+ALC_TIMEOUT_INT_MSK	include/ssv6200_aux.h	12626;"	d
+ALC_TIMEOUT_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34151;"	d
+ALC_TIMEOUT_INT_SFT	include/ssv6200_aux.h	12628;"	d
+ALC_TIMEOUT_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34153;"	d
+ALC_TIMEOUT_INT_SZ	include/ssv6200_aux.h	12630;"	d
+ALC_TIMEOUT_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34155;"	d
+ALC_TIMEOUT_I_MSK	include/ssv6200_aux.h	12617;"	d
+ALC_TIMEOUT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34142;"	d
+ALC_TIMEOUT_MSK	include/ssv6200_aux.h	12616;"	d
+ALC_TIMEOUT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34141;"	d
+ALC_TIMEOUT_SFT	include/ssv6200_aux.h	12618;"	d
+ALC_TIMEOUT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34143;"	d
+ALC_TIMEOUT_SZ	include/ssv6200_aux.h	12620;"	d
+ALC_TIMEOUT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34145;"	d
+ALLOCATESTATUS_HI	include/ssv6200_aux.h	3534;"	d
+ALLOCATESTATUS_I_MSK	include/ssv6200_aux.h	3532;"	d
+ALLOCATESTATUS_MSK	include/ssv6200_aux.h	3531;"	d
+ALLOCATESTATUS_SFT	include/ssv6200_aux.h	3533;"	d
+ALLOCATESTATUS_SZ	include/ssv6200_aux.h	3535;"	d
+ALLOCATE_STATUS2_HI	include/ssv6200_aux.h	3494;"	d
+ALLOCATE_STATUS2_I_MSK	include/ssv6200_aux.h	3492;"	d
+ALLOCATE_STATUS2_MSK	include/ssv6200_aux.h	3491;"	d
+ALLOCATE_STATUS2_SFT	include/ssv6200_aux.h	3493;"	d
+ALLOCATE_STATUS2_SZ	include/ssv6200_aux.h	3495;"	d
+ALLOCATE_STATUS_HI	include/ssv6200_aux.h	3234;"	d
+ALLOCATE_STATUS_I_MSK	include/ssv6200_aux.h	3232;"	d
+ALLOCATE_STATUS_MSK	include/ssv6200_aux.h	3231;"	d
+ALLOCATE_STATUS_SFT	include/ssv6200_aux.h	3233;"	d
+ALLOCATE_STATUS_SZ	include/ssv6200_aux.h	3235;"	d
+ALLOW_SD_RESET_HI	include/ssv6200_aux.h	614;"	d
+ALLOW_SD_RESET_I_MSK	include/ssv6200_aux.h	612;"	d
+ALLOW_SD_RESET_MSK	include/ssv6200_aux.h	611;"	d
+ALLOW_SD_RESET_SFT	include/ssv6200_aux.h	613;"	d
+ALLOW_SD_RESET_SZ	include/ssv6200_aux.h	615;"	d
+ALLOW_SD_SPI_RESET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1669;"	d
+ALLOW_SD_SPI_RESET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1667;"	d
+ALLOW_SD_SPI_RESET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1666;"	d
+ALLOW_SD_SPI_RESET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1668;"	d
+ALLOW_SD_SPI_RESET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1670;"	d
+ALL_ID_ALC_LEN_HI	include/ssv6200_aux.h	12749;"	d
+ALL_ID_ALC_LEN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34274;"	d
+ALL_ID_ALC_LEN_I_MSK	include/ssv6200_aux.h	12747;"	d
+ALL_ID_ALC_LEN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34272;"	d
+ALL_ID_ALC_LEN_MSK	include/ssv6200_aux.h	12746;"	d
+ALL_ID_ALC_LEN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34271;"	d
+ALL_ID_ALC_LEN_SFT	include/ssv6200_aux.h	12748;"	d
+ALL_ID_ALC_LEN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34273;"	d
+ALL_ID_ALC_LEN_SZ	include/ssv6200_aux.h	12750;"	d
+ALL_ID_ALC_LEN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34275;"	d
+ALL_ID_LEN_THOLD_HI	include/ssv6200_aux.h	5029;"	d
+ALL_ID_LEN_THOLD_INT_HI	include/ssv6200_aux.h	12719;"	d
+ALL_ID_LEN_THOLD_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34244;"	d
+ALL_ID_LEN_THOLD_INT_I_MSK	include/ssv6200_aux.h	12717;"	d
+ALL_ID_LEN_THOLD_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34242;"	d
+ALL_ID_LEN_THOLD_INT_MSK	include/ssv6200_aux.h	12716;"	d
+ALL_ID_LEN_THOLD_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34241;"	d
+ALL_ID_LEN_THOLD_INT_SFT	include/ssv6200_aux.h	12718;"	d
+ALL_ID_LEN_THOLD_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34243;"	d
+ALL_ID_LEN_THOLD_INT_SZ	include/ssv6200_aux.h	12720;"	d
+ALL_ID_LEN_THOLD_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34245;"	d
+ALL_ID_LEN_THOLD_I_MSK	include/ssv6200_aux.h	5027;"	d
+ALL_ID_LEN_THOLD_MSK	include/ssv6200_aux.h	5026;"	d
+ALL_ID_LEN_THOLD_SD_HI	include/ssv6200_aux.h	5374;"	d
+ALL_ID_LEN_THOLD_SD_I_MSK	include/ssv6200_aux.h	5372;"	d
+ALL_ID_LEN_THOLD_SD_MSK	include/ssv6200_aux.h	5371;"	d
+ALL_ID_LEN_THOLD_SD_SFT	include/ssv6200_aux.h	5373;"	d
+ALL_ID_LEN_THOLD_SD_SZ	include/ssv6200_aux.h	5375;"	d
+ALL_ID_LEN_THOLD_SFT	include/ssv6200_aux.h	5028;"	d
+ALL_ID_LEN_THOLD_SZ	include/ssv6200_aux.h	5030;"	d
+ALL_SW_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1074;"	d
+ALL_SW_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1072;"	d
+ALL_SW_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1071;"	d
+ALL_SW_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1073;"	d
+ALL_SW_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1075;"	d
+ALR_ABT_NOCHG_INT_IRQ_HI	include/ssv6200_aux.h	5059;"	d
+ALR_ABT_NOCHG_INT_IRQ_I_MSK	include/ssv6200_aux.h	5057;"	d
+ALR_ABT_NOCHG_INT_IRQ_MSK	include/ssv6200_aux.h	5056;"	d
+ALR_ABT_NOCHG_INT_IRQ_SD_HI	include/ssv6200_aux.h	5404;"	d
+ALR_ABT_NOCHG_INT_IRQ_SD_I_MSK	include/ssv6200_aux.h	5402;"	d
+ALR_ABT_NOCHG_INT_IRQ_SD_MSK	include/ssv6200_aux.h	5401;"	d
+ALR_ABT_NOCHG_INT_IRQ_SD_SFT	include/ssv6200_aux.h	5403;"	d
+ALR_ABT_NOCHG_INT_IRQ_SD_SZ	include/ssv6200_aux.h	5405;"	d
+ALR_ABT_NOCHG_INT_IRQ_SFT	include/ssv6200_aux.h	5058;"	d
+ALR_ABT_NOCHG_INT_IRQ_SZ	include/ssv6200_aux.h	5060;"	d
+ALR_SW_RST_N_HI	include/ssv6200_aux.h	17704;"	d
+ALR_SW_RST_N_I_MSK	include/ssv6200_aux.h	17702;"	d
+ALR_SW_RST_N_MSK	include/ssv6200_aux.h	17701;"	d
+ALR_SW_RST_N_SFT	include/ssv6200_aux.h	17703;"	d
+ALR_SW_RST_N_SZ	include/ssv6200_aux.h	17705;"	d
+AL_STATE_HI	include/ssv6200_aux.h	17924;"	d
+AL_STATE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34549;"	d
+AL_STATE_I_MSK	include/ssv6200_aux.h	17922;"	d
+AL_STATE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34547;"	d
+AL_STATE_MSK	include/ssv6200_aux.h	17921;"	d
+AL_STATE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34546;"	d
+AL_STATE_SFT	include/ssv6200_aux.h	17923;"	d
+AL_STATE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34548;"	d
+AL_STATE_SZ	include/ssv6200_aux.h	17925;"	d
+AL_STATE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34550;"	d
+AMPDU_BA_FRAME_LEN	smac/dev.h	87;"	d
+AMPDU_BLOCKACK	smac/ampdu.h	/^} AMPDU_BLOCKACK, *p_AMPDU_BLOCKACK;$/;"	t	typeref:struct:AMPDU_BLOCKACK_st
+AMPDU_BLOCKACK_st	smac/ampdu.h	/^typedef struct AMPDU_BLOCKACK_st$/;"	s
+AMPDU_BLOCKACK_st::BA_ack_ploicy	smac/ampdu.h	/^    u16 BA_ack_ploicy:1;$/;"	m	struct:AMPDU_BLOCKACK_st	access:public
+AMPDU_BLOCKACK_st::BA_fragment_sn	smac/ampdu.h	/^    u16 BA_fragment_sn:4;$/;"	m	struct:AMPDU_BLOCKACK_st	access:public
+AMPDU_BLOCKACK_st::BA_sn_bit_map	smac/ampdu.h	/^    u32 BA_sn_bit_map[2];$/;"	m	struct:AMPDU_BLOCKACK_st	access:public
+AMPDU_BLOCKACK_st::BA_ssn	smac/ampdu.h	/^    u16 BA_ssn:12;$/;"	m	struct:AMPDU_BLOCKACK_st	access:public
+AMPDU_BLOCKACK_st::compress_bitmap	smac/ampdu.h	/^    u16 compress_bitmap:1;$/;"	m	struct:AMPDU_BLOCKACK_st	access:public
+AMPDU_BLOCKACK_st::duration	smac/ampdu.h	/^ u16 duration;$/;"	m	struct:AMPDU_BLOCKACK_st	access:public
+AMPDU_BLOCKACK_st::frame_control	smac/ampdu.h	/^ u16 frame_control;$/;"	m	struct:AMPDU_BLOCKACK_st	access:public
+AMPDU_BLOCKACK_st::multi_tid	smac/ampdu.h	/^    u16 multi_tid:1;$/;"	m	struct:AMPDU_BLOCKACK_st	access:public
+AMPDU_BLOCKACK_st::ra_addr	smac/ampdu.h	/^ u8 ra_addr[ETH_ALEN];$/;"	m	struct:AMPDU_BLOCKACK_st	access:public
+AMPDU_BLOCKACK_st::reserved	smac/ampdu.h	/^    u16 reserved:9;$/;"	m	struct:AMPDU_BLOCKACK_st	access:public
+AMPDU_BLOCKACK_st::ta_addr	smac/ampdu.h	/^ u8 ta_addr[ETH_ALEN];$/;"	m	struct:AMPDU_BLOCKACK_st	access:public
+AMPDU_BLOCKACK_st::tid_info	smac/ampdu.h	/^    u16 tid_info:4;$/;"	m	struct:AMPDU_BLOCKACK_st	access:public
+AMPDU_BUFFER_SIZE	smac/ampdu.h	51;"	d
+AMPDU_CHECK_SKB_SEQNO	smac/ampdu.h	31;"	d
+AMPDU_CLK_EN_HI	include/ssv6200_aux.h	9009;"	d
+AMPDU_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8764;"	d
+AMPDU_CLK_EN_I_MSK	include/ssv6200_aux.h	9007;"	d
+AMPDU_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8762;"	d
+AMPDU_CLK_EN_MSK	include/ssv6200_aux.h	9006;"	d
+AMPDU_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8761;"	d
+AMPDU_CLK_EN_SFT	include/ssv6200_aux.h	9008;"	d
+AMPDU_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8763;"	d
+AMPDU_CLK_EN_SZ	include/ssv6200_aux.h	9010;"	d
+AMPDU_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8765;"	d
+AMPDU_CSR_CLK_EN_HI	include/ssv6200_aux.h	9104;"	d
+AMPDU_CSR_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8859;"	d
+AMPDU_CSR_CLK_EN_I_MSK	include/ssv6200_aux.h	9102;"	d
+AMPDU_CSR_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8857;"	d
+AMPDU_CSR_CLK_EN_MSK	include/ssv6200_aux.h	9101;"	d
+AMPDU_CSR_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8856;"	d
+AMPDU_CSR_CLK_EN_SFT	include/ssv6200_aux.h	9103;"	d
+AMPDU_CSR_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8858;"	d
+AMPDU_CSR_CLK_EN_SZ	include/ssv6200_aux.h	9105;"	d
+AMPDU_CSR_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8860;"	d
+AMPDU_CSR_RST_HI	include/ssv6200_aux.h	8964;"	d
+AMPDU_CSR_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8719;"	d
+AMPDU_CSR_RST_I_MSK	include/ssv6200_aux.h	8962;"	d
+AMPDU_CSR_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8717;"	d
+AMPDU_CSR_RST_MSK	include/ssv6200_aux.h	8961;"	d
+AMPDU_CSR_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8716;"	d
+AMPDU_CSR_RST_SFT	include/ssv6200_aux.h	8963;"	d
+AMPDU_CSR_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8718;"	d
+AMPDU_CSR_RST_SZ	include/ssv6200_aux.h	8965;"	d
+AMPDU_CSR_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8720;"	d
+AMPDU_DELIMITER	smac/ampdu.h	/^} AMPDU_DELIMITER, *p_AMPDU_DELIMITER;$/;"	t	typeref:struct:AMPDU_DELIMITER_st
+AMPDU_DELIMITER_LEN	smac/ampdu.h	53;"	d
+AMPDU_DELIMITER_st	smac/ampdu.h	/^typedef struct AMPDU_DELIMITER_st$/;"	s
+AMPDU_DELIMITER_st::crc	smac/ampdu.h	/^    u8 crc;$/;"	m	struct:AMPDU_DELIMITER_st	access:public
+AMPDU_DELIMITER_st::length	smac/ampdu.h	/^    u16 length:12;$/;"	m	struct:AMPDU_DELIMITER_st	access:public
+AMPDU_DELIMITER_st::reserved	smac/ampdu.h	/^    u16 reserved:4;$/;"	m	struct:AMPDU_DELIMITER_st	access:public
+AMPDU_DELIMITER_st::signature	smac/ampdu.h	/^    u8 signature;$/;"	m	struct:AMPDU_DELIMITER_st	access:public
+AMPDU_ENG_CLK_EN_HI	include/ssv6200_aux.h	9069;"	d
+AMPDU_ENG_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8824;"	d
+AMPDU_ENG_CLK_EN_I_MSK	include/ssv6200_aux.h	9067;"	d
+AMPDU_ENG_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8822;"	d
+AMPDU_ENG_CLK_EN_MSK	include/ssv6200_aux.h	9066;"	d
+AMPDU_ENG_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8821;"	d
+AMPDU_ENG_CLK_EN_SFT	include/ssv6200_aux.h	9068;"	d
+AMPDU_ENG_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8823;"	d
+AMPDU_ENG_CLK_EN_SZ	include/ssv6200_aux.h	9070;"	d
+AMPDU_ENG_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8825;"	d
+AMPDU_ENG_RST_HI	include/ssv6200_aux.h	8894;"	d
+AMPDU_ENG_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8649;"	d
+AMPDU_ENG_RST_I_MSK	include/ssv6200_aux.h	8892;"	d
+AMPDU_ENG_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8647;"	d
+AMPDU_ENG_RST_MSK	include/ssv6200_aux.h	8891;"	d
+AMPDU_ENG_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8646;"	d
+AMPDU_ENG_RST_SFT	include/ssv6200_aux.h	8893;"	d
+AMPDU_ENG_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8648;"	d
+AMPDU_ENG_RST_SZ	include/ssv6200_aux.h	8895;"	d
+AMPDU_ENG_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8650;"	d
+AMPDU_FCS_LEN	smac/ampdu.h	54;"	d
+AMPDU_HCI_Q_EMPTY	smac/ampdu.h	101;"	d
+AMPDU_HCI_SEND	smac/ampdu.h	96;"	d
+AMPDU_HCI_SEND_HEAD_WITHOUT_FLOWCTRL	smac/ampdu.h	69;"	d
+AMPDU_HCI_SEND_HEAD_WITH_FLOWCTRL	smac/ampdu.h	67;"	d
+AMPDU_HCI_SEND_TAIL_WITHOUT_FLOWCTRL	smac/ampdu.h	68;"	d
+AMPDU_HCI_SEND_TAIL_WITH_FLOWCTRL	smac/ampdu.h	66;"	d
+AMPDU_MIB	smac/ampdu.h	/^} AMPDU_MIB;$/;"	t	typeref:struct:AMPDU_MIB_st
+AMPDU_MIB_st	smac/ampdu.h	/^typedef struct AMPDU_MIB_st$/;"	s
+AMPDU_MIB_st::ampdu_mib_BA_counter	smac/ampdu.h	/^    u32 ampdu_mib_BA_counter;$/;"	m	struct:AMPDU_MIB_st	access:public
+AMPDU_MIB_st::ampdu_mib_aggr_retry_counter	smac/ampdu.h	/^    u32 ampdu_mib_aggr_retry_counter;$/;"	m	struct:AMPDU_MIB_st	access:public
+AMPDU_MIB_st::ampdu_mib_ampdu_counter	smac/ampdu.h	/^    u32 ampdu_mib_ampdu_counter;$/;"	m	struct:AMPDU_MIB_st	access:public
+AMPDU_MIB_st::ampdu_mib_bar_counter	smac/ampdu.h	/^    u32 ampdu_mib_bar_counter;$/;"	m	struct:AMPDU_MIB_st	access:public
+AMPDU_MIB_st::ampdu_mib_discard_counter	smac/ampdu.h	/^    u32 ampdu_mib_discard_counter;$/;"	m	struct:AMPDU_MIB_st	access:public
+AMPDU_MIB_st::ampdu_mib_dist	smac/ampdu.h	/^    u32 ampdu_mib_dist[SSV_AMPDU_aggr_num_max + 1];$/;"	m	struct:AMPDU_MIB_st	access:public
+AMPDU_MIB_st::ampdu_mib_mpdu_counter	smac/ampdu.h	/^    u32 ampdu_mib_mpdu_counter;$/;"	m	struct:AMPDU_MIB_st	access:public
+AMPDU_MIB_st::ampdu_mib_pass_counter	smac/ampdu.h	/^    u32 ampdu_mib_pass_counter;$/;"	m	struct:AMPDU_MIB_st	access:public
+AMPDU_MIB_st::ampdu_mib_retry_counter	smac/ampdu.h	/^    u32 ampdu_mib_retry_counter;$/;"	m	struct:AMPDU_MIB_st	access:public
+AMPDU_MIB_st::ampdu_mib_total_BA_counter	smac/ampdu.h	/^    u32 ampdu_mib_total_BA_counter;$/;"	m	struct:AMPDU_MIB_st	access:public
+AMPDU_REG_BANK_SIZE	include/ssv6200_reg.h	96;"	d
+AMPDU_REG_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	115;"	d
+AMPDU_REG_BASE	include/ssv6200_reg.h	47;"	d
+AMPDU_REG_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	54;"	d
+AMPDU_REKEY_PAUSE_DEFER	smac/ampdu.h	/^    AMPDU_REKEY_PAUSE_DEFER,$/;"	e	enum:__anon15
+AMPDU_REKEY_PAUSE_HWKEY_SYNC	smac/ampdu.h	/^    AMPDU_REKEY_PAUSE_HWKEY_SYNC,$/;"	e	enum:__anon15
+AMPDU_REKEY_PAUSE_ONGOING	smac/ampdu.h	/^    AMPDU_REKEY_PAUSE_ONGOING,$/;"	e	enum:__anon15
+AMPDU_REKEY_PAUSE_START	smac/ampdu.h	/^    AMPDU_REKEY_PAUSE_START,$/;"	e	enum:__anon15
+AMPDU_REKEY_PAUSE_STATE	smac/ampdu.h	/^}AMPDU_REKEY_PAUSE_STATE;$/;"	t	typeref:enum:__anon15
+AMPDU_REKEY_PAUSE_STOP	smac/ampdu.h	/^    AMPDU_REKEY_PAUSE_STOP=0,$/;"	e	enum:__anon15
+AMPDU_RESERVED_LEN	smac/ampdu.h	55;"	d
+AMPDU_SIGNATURE	smac/ampdu.h	52;"	d
+AMPDU_SIG_HI	include/ssv6200_aux.h	7384;"	d
+AMPDU_SIG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6539;"	d
+AMPDU_SIG_I_MSK	include/ssv6200_aux.h	7382;"	d
+AMPDU_SIG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6537;"	d
+AMPDU_SIG_MSK	include/ssv6200_aux.h	7381;"	d
+AMPDU_SIG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6536;"	d
+AMPDU_SIG_SFT	include/ssv6200_aux.h	7383;"	d
+AMPDU_SIG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6538;"	d
+AMPDU_SIG_SZ	include/ssv6200_aux.h	7385;"	d
+AMPDU_SIG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6540;"	d
+AMPDU_SNIFFER_HI	include/ssv6200_aux.h	9159;"	d
+AMPDU_SNIFFER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8914;"	d
+AMPDU_SNIFFER_I_MSK	include/ssv6200_aux.h	9157;"	d
+AMPDU_SNIFFER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8912;"	d
+AMPDU_SNIFFER_MSK	include/ssv6200_aux.h	9156;"	d
+AMPDU_SNIFFER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8911;"	d
+AMPDU_SNIFFER_SFT	include/ssv6200_aux.h	9158;"	d
+AMPDU_SNIFFER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8913;"	d
+AMPDU_SNIFFER_SZ	include/ssv6200_aux.h	9160;"	d
+AMPDU_SNIFFER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8915;"	d
+AMPDU_STATE_OPERATION	smac/ampdu.h	74;"	d
+AMPDU_STATE_START	smac/ampdu.h	73;"	d
+AMPDU_STATE_STOP	smac/ampdu.h	75;"	d
+AMPDU_ST_AGGREGATED	smac/ampdu.h	/^ AMPDU_ST_AGGREGATED,$/;"	e	enum:AMPDU_TX_STATUS_E
+AMPDU_ST_DONE	smac/ampdu.h	/^ AMPDU_ST_DONE,$/;"	e	enum:AMPDU_TX_STATUS_E
+AMPDU_ST_DROPPED	smac/ampdu.h	/^ AMPDU_ST_DROPPED,$/;"	e	enum:AMPDU_TX_STATUS_E
+AMPDU_ST_NON_AMPDU	smac/ampdu.h	/^ AMPDU_ST_NON_AMPDU,$/;"	e	enum:AMPDU_TX_STATUS_E
+AMPDU_ST_RETRY	smac/ampdu.h	/^ AMPDU_ST_RETRY,$/;"	e	enum:AMPDU_TX_STATUS_E
+AMPDU_ST_RETRY_Q	smac/ampdu.h	/^ AMPDU_ST_RETRY_Q,$/;"	e	enum:AMPDU_TX_STATUS_E
+AMPDU_ST_SENT	smac/ampdu.h	/^ AMPDU_ST_SENT,$/;"	e	enum:AMPDU_TX_STATUS_E
+AMPDU_SW_RST_HI	include/ssv6200_aux.h	8834;"	d
+AMPDU_SW_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8589;"	d
+AMPDU_SW_RST_I_MSK	include/ssv6200_aux.h	8832;"	d
+AMPDU_SW_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8587;"	d
+AMPDU_SW_RST_MSK	include/ssv6200_aux.h	8831;"	d
+AMPDU_SW_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8586;"	d
+AMPDU_SW_RST_SFT	include/ssv6200_aux.h	8833;"	d
+AMPDU_SW_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8588;"	d
+AMPDU_SW_RST_SZ	include/ssv6200_aux.h	8835;"	d
+AMPDU_SW_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8590;"	d
+AMPDU_TID	smac/ampdu.h	/^} AMPDU_TID, *p_AMPDU_TID;$/;"	t	typeref:struct:AMPDU_TID_st
+AMPDU_TID	smac/dev.h	/^typedef struct AMPDU_TID_st AMPDU_TID;$/;"	t	typeref:struct:AMPDU_TID_st
+AMPDU_TID_TO_SC	smac/ampdu.c	27;"	d	file:
+AMPDU_TID_st	smac/ampdu.h	/^typedef struct AMPDU_TID_st$/;"	s
+AMPDU_TID_st::ac	smac/ampdu.h	/^    u16 ac;$/;"	m	struct:AMPDU_TID_st	access:public
+AMPDU_TID_st::agg_num_max	smac/ampdu.h	/^    u8 agg_num_max;$/;"	m	struct:AMPDU_TID_st	access:public
+AMPDU_TID_st::aggr_pkt_num	smac/ampdu.h	/^    volatile u32 aggr_pkt_num;$/;"	m	struct:AMPDU_TID_st	access:public
+AMPDU_TID_st::aggr_pkts	smac/ampdu.h	/^    struct sk_buff *aggr_pkts[SSV_AMPDU_BA_WINDOW_SIZE];$/;"	m	struct:AMPDU_TID_st	typeref:struct:AMPDU_TID_st::sk_buff	access:public
+AMPDU_TID_st::ampdu_mib_reset	smac/ampdu.h	/^    u32 ampdu_mib_reset;$/;"	m	struct:AMPDU_TID_st	access:public
+AMPDU_TID_st::ampdu_skb_tx_queue	smac/ampdu.h	/^    struct sk_buff_head ampdu_skb_tx_queue;$/;"	m	struct:AMPDU_TID_st	typeref:struct:AMPDU_TID_st::sk_buff_head	access:public
+AMPDU_TID_st::ampdu_skb_tx_queue_lock	smac/ampdu.h	/^    spinlock_t ampdu_skb_tx_queue_lock;$/;"	m	struct:AMPDU_TID_st	access:public
+AMPDU_TID_st::ampdu_skb_wait_encry_queue	smac/ampdu.h	/^    struct sk_buff_head ampdu_skb_wait_encry_queue;$/;"	m	struct:AMPDU_TID_st	typeref:struct:AMPDU_TID_st::sk_buff_head	access:public
+AMPDU_TID_st::ba_q	smac/ampdu.h	/^    struct sk_buff_head ba_q;$/;"	m	struct:AMPDU_TID_st	typeref:struct:AMPDU_TID_st::sk_buff_head	access:public
+AMPDU_TID_st::cur_ampdu_pkt	smac/ampdu.h	/^    struct sk_buff *cur_ampdu_pkt;$/;"	m	struct:AMPDU_TID_st	typeref:struct:AMPDU_TID_st::sk_buff	access:public
+AMPDU_TID_st::debugfs_dir	smac/ampdu.h	/^    struct dentry *debugfs_dir;$/;"	m	struct:AMPDU_TID_st	typeref:struct:AMPDU_TID_st::dentry	access:public
+AMPDU_TID_st::early_aggr_ampdu_q	smac/ampdu.h	/^    struct sk_buff_head early_aggr_ampdu_q;$/;"	m	struct:AMPDU_TID_st	typeref:struct:AMPDU_TID_st::sk_buff_head	access:public
+AMPDU_TID_st::early_aggr_skb_num	smac/ampdu.h	/^    u32 early_aggr_skb_num;$/;"	m	struct:AMPDU_TID_st	access:public
+AMPDU_TID_st::last_seqno	smac/ampdu.h	/^    u32 last_seqno;$/;"	m	struct:AMPDU_TID_st	access:public
+AMPDU_TID_st::list	smac/ampdu.h	/^    struct list_head list;$/;"	m	struct:AMPDU_TID_st	typeref:struct:AMPDU_TID_st::list_head	access:public
+AMPDU_TID_st::mib	smac/ampdu.h	/^    struct AMPDU_MIB_st mib;$/;"	m	struct:AMPDU_TID_st	typeref:struct:AMPDU_TID_st::AMPDU_MIB_st	access:public
+AMPDU_TID_st::pkt_array_lock	smac/ampdu.h	/^    spinlock_t pkt_array_lock;$/;"	m	struct:AMPDU_TID_st	access:public
+AMPDU_TID_st::release_queue	smac/ampdu.h	/^    struct sk_buff_head release_queue;$/;"	m	struct:AMPDU_TID_st	typeref:struct:AMPDU_TID_st::sk_buff_head	access:public
+AMPDU_TID_st::retry_queue	smac/ampdu.h	/^    struct sk_buff_head retry_queue;$/;"	m	struct:AMPDU_TID_st	typeref:struct:AMPDU_TID_st::sk_buff_head	access:public
+AMPDU_TID_st::ssv_baw_head	smac/ampdu.h	/^    volatile u16 ssv_baw_head;$/;"	m	struct:AMPDU_TID_st	access:public
+AMPDU_TID_st::ssv_baw_size	smac/ampdu.h	/^    u16 ssv_baw_size;$/;"	m	struct:AMPDU_TID_st	access:public
+AMPDU_TID_st::sta	smac/ampdu.h	/^    struct ieee80211_sta *sta;$/;"	m	struct:AMPDU_TID_st	typeref:struct:AMPDU_TID_st::ieee80211_sta	access:public
+AMPDU_TID_st::state	smac/ampdu.h	/^    u8 state;$/;"	m	struct:AMPDU_TID_st	access:public
+AMPDU_TID_st::tidno	smac/ampdu.h	/^    u32 tidno;$/;"	m	struct:AMPDU_TID_st	access:public
+AMPDU_TID_st::timestamp	smac/ampdu.h	/^    volatile unsigned long timestamp;$/;"	m	struct:AMPDU_TID_st	access:public
+AMPDU_TX_MIB_SUMMARY_BUF_SIZE	smac/ampdu.c	547;"	d	file:
+AMPDU_TX_NAV_MCS_567	smac/ampdu.h	56;"	d
+AMPDU_TX_STATUS_E	smac/ampdu.h	/^enum AMPDU_TX_STATUS_E {$/;"	g
+ASIC_TAG_HI	include/ssv6200_aux.h	8794;"	d
+ASIC_TAG_I_MSK	include/ssv6200_aux.h	8792;"	d
+ASIC_TAG_MSK	include/ssv6200_aux.h	8791;"	d
+ASIC_TAG_SFT	include/ssv6200_aux.h	8793;"	d
+ASIC_TAG_SZ	include/ssv6200_aux.h	8795;"	d
+AUTOSGI_CTL	smac/dev.h	53;"	d
+AUTOSGI_DBG	smac/dev.h	54;"	d
+AUTO_BCN_ONGOING_MASK	smac/ap.c	49;"	d	file:
+AUTO_BCN_ONGOING_SHIFT	smac/ap.c	50;"	d	file:
+AUTO_CSN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6004;"	d
+AUTO_CSN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6002;"	d
+AUTO_CSN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6001;"	d
+AUTO_CSN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6003;"	d
+AUTO_CSN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6005;"	d
+AUTO_REMAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9169;"	d
+AUTO_REMAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9167;"	d
+AUTO_REMAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9166;"	d
+AUTO_REMAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9168;"	d
+AUTO_REMAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9170;"	d
+AUTO_SEQNO_HI	include/ssv6200_aux.h	6064;"	d
+AUTO_SEQNO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5114;"	d
+AUTO_SEQNO_I_MSK	include/ssv6200_aux.h	6062;"	d
+AUTO_SEQNO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5112;"	d
+AUTO_SEQNO_MSK	include/ssv6200_aux.h	6061;"	d
+AUTO_SEQNO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5111;"	d
+AUTO_SEQNO_SFT	include/ssv6200_aux.h	6063;"	d
+AUTO_SEQNO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5113;"	d
+AUTO_SEQNO_SZ	include/ssv6200_aux.h	6065;"	d
+AUTO_SEQNO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5115;"	d
+AVA_TAG_HI	include/ssv6200_aux.h	17984;"	d
+AVA_TAG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34599;"	d
+AVA_TAG_I_MSK	include/ssv6200_aux.h	17982;"	d
+AVA_TAG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34597;"	d
+AVA_TAG_MSK	include/ssv6200_aux.h	17981;"	d
+AVA_TAG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34596;"	d
+AVA_TAG_SFT	include/ssv6200_aux.h	17983;"	d
+AVA_TAG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34598;"	d
+AVA_TAG_SZ	include/ssv6200_aux.h	17985;"	d
+AVA_TAG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34600;"	d
+AVG_PKT_SIZE	smac/ssv_ht_rc.c	25;"	d	file:
+AVG_PKT_SIZE	smac/ssv_rc_minstrel_ht.c	29;"	d	file:
+BACKUP_PG_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5294;"	d
+BACKUP_PG_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5292;"	d
+BACKUP_PG_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5291;"	d
+BACKUP_PG_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5293;"	d
+BACKUP_PG_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5295;"	d
+BACK_DLY_HI	include/ssv6200_aux.h	3964;"	d
+BACK_DLY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3079;"	d
+BACK_DLY_I_MSK	include/ssv6200_aux.h	3962;"	d
+BACK_DLY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3077;"	d
+BACK_DLY_MSK	include/ssv6200_aux.h	3961;"	d
+BACK_DLY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3076;"	d
+BACK_DLY_SFT	include/ssv6200_aux.h	3963;"	d
+BACK_DLY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3078;"	d
+BACK_DLY_SZ	include/ssv6200_aux.h	3965;"	d
+BACK_DLY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3080;"	d
+BAND_2G	smac/hal/ssv6006c/turismo_common.h	/^    BAND_2G,$/;"	e	enum:__anon6
+BAND_5100	smac/hal/ssv6006c/turismo_common.h	/^    BAND_5100,$/;"	e	enum:__anon6
+BAND_5500	smac/hal/ssv6006c/turismo_common.h	/^    BAND_5500,$/;"	e	enum:__anon6
+BAND_5700	smac/hal/ssv6006c/turismo_common.h	/^    BAND_5700,$/;"	e	enum:__anon6
+BAND_5900	smac/hal/ssv6006c/turismo_common.h	/^    BAND_5900,$/;"	e	enum:__anon6
+BANK_COUNT	include/ssv6200_reg_sim.h	17;"	d
+BANK_COUNT	smac/hal/ssv6006c/ssv6006C_reg_sim.h	17;"	d
+BASE_BANK_SSV6200	include/ssv6200_reg_sim.h	/^static const u32 BASE_BANK_SSV6200[] = {$/;"	v
+BASE_BANK_SSV6200	smac/hal/ssv6006c/ssv6006C_reg_sim.h	/^static const u32 BASE_BANK_SSV6200[] = {$/;"	v
+BASE_SDIO	hwif/sdio/sdio_def.h	19;"	d
+BA_AGRE_EN_HI	include/ssv6200_aux.h	7169;"	d
+BA_AGRE_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6344;"	d
+BA_AGRE_EN_I_MSK	include/ssv6200_aux.h	7167;"	d
+BA_AGRE_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6342;"	d
+BA_AGRE_EN_MSK	include/ssv6200_aux.h	7166;"	d
+BA_AGRE_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6341;"	d
+BA_AGRE_EN_SFT	include/ssv6200_aux.h	7168;"	d
+BA_AGRE_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6343;"	d
+BA_AGRE_EN_SZ	include/ssv6200_aux.h	7170;"	d
+BA_AGRE_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6345;"	d
+BA_CTRL_HI	include/ssv6200_aux.h	7159;"	d
+BA_CTRL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6334;"	d
+BA_CTRL_I_MSK	include/ssv6200_aux.h	7157;"	d
+BA_CTRL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6332;"	d
+BA_CTRL_MSK	include/ssv6200_aux.h	7156;"	d
+BA_CTRL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6331;"	d
+BA_CTRL_SFT	include/ssv6200_aux.h	7158;"	d
+BA_CTRL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6333;"	d
+BA_CTRL_SZ	include/ssv6200_aux.h	7160;"	d
+BA_CTRL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6335;"	d
+BA_DBG_EN_HI	include/ssv6200_aux.h	7164;"	d
+BA_DBG_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6339;"	d
+BA_DBG_EN_I_MSK	include/ssv6200_aux.h	7162;"	d
+BA_DBG_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6337;"	d
+BA_DBG_EN_MSK	include/ssv6200_aux.h	7161;"	d
+BA_DBG_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6336;"	d
+BA_DBG_EN_SFT	include/ssv6200_aux.h	7163;"	d
+BA_DBG_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6338;"	d
+BA_DBG_EN_SZ	include/ssv6200_aux.h	7165;"	d
+BA_DBG_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6340;"	d
+BA_GEN_EN_HI	include/ssv6200_aux.h	7214;"	d
+BA_GEN_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6389;"	d
+BA_GEN_EN_I_MSK	include/ssv6200_aux.h	7212;"	d
+BA_GEN_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6387;"	d
+BA_GEN_EN_MSK	include/ssv6200_aux.h	7211;"	d
+BA_GEN_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6386;"	d
+BA_GEN_EN_SFT	include/ssv6200_aux.h	7213;"	d
+BA_GEN_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6388;"	d
+BA_GEN_EN_SZ	include/ssv6200_aux.h	7215;"	d
+BA_GEN_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6390;"	d
+BA_HW_ID_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6514;"	d
+BA_HW_ID_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6512;"	d
+BA_HW_ID_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6511;"	d
+BA_HW_ID_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6513;"	d
+BA_HW_ID_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6515;"	d
+BA_H_QUEUE_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6499;"	d
+BA_H_QUEUE_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6497;"	d
+BA_H_QUEUE_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6496;"	d
+BA_H_QUEUE_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6498;"	d
+BA_H_QUEUE_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6500;"	d
+BA_LEN	smac/dev.h	159;"	d
+BA_SB0_HI	include/ssv6200_aux.h	7194;"	d
+BA_SB0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6369;"	d
+BA_SB0_I_MSK	include/ssv6200_aux.h	7192;"	d
+BA_SB0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6367;"	d
+BA_SB0_MSK	include/ssv6200_aux.h	7191;"	d
+BA_SB0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6366;"	d
+BA_SB0_SFT	include/ssv6200_aux.h	7193;"	d
+BA_SB0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6368;"	d
+BA_SB0_SZ	include/ssv6200_aux.h	7195;"	d
+BA_SB0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6370;"	d
+BA_SB1_HI	include/ssv6200_aux.h	7199;"	d
+BA_SB1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6374;"	d
+BA_SB1_I_MSK	include/ssv6200_aux.h	7197;"	d
+BA_SB1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6372;"	d
+BA_SB1_MSK	include/ssv6200_aux.h	7196;"	d
+BA_SB1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6371;"	d
+BA_SB1_SFT	include/ssv6200_aux.h	7198;"	d
+BA_SB1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6373;"	d
+BA_SB1_SZ	include/ssv6200_aux.h	7200;"	d
+BA_SB1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6375;"	d
+BA_ST_SEQ_HI	include/ssv6200_aux.h	7189;"	d
+BA_ST_SEQ_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6364;"	d
+BA_ST_SEQ_I_MSK	include/ssv6200_aux.h	7187;"	d
+BA_ST_SEQ_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6362;"	d
+BA_ST_SEQ_MSK	include/ssv6200_aux.h	7186;"	d
+BA_ST_SEQ_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6361;"	d
+BA_ST_SEQ_SFT	include/ssv6200_aux.h	7188;"	d
+BA_ST_SEQ_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6363;"	d
+BA_ST_SEQ_SZ	include/ssv6200_aux.h	7190;"	d
+BA_ST_SEQ_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6365;"	d
+BA_TA_31_0_HI	include/ssv6200_aux.h	7174;"	d
+BA_TA_31_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6349;"	d
+BA_TA_31_0_I_MSK	include/ssv6200_aux.h	7172;"	d
+BA_TA_31_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6347;"	d
+BA_TA_31_0_MSK	include/ssv6200_aux.h	7171;"	d
+BA_TA_31_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6346;"	d
+BA_TA_31_0_SFT	include/ssv6200_aux.h	7173;"	d
+BA_TA_31_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6348;"	d
+BA_TA_31_0_SZ	include/ssv6200_aux.h	7175;"	d
+BA_TA_31_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6350;"	d
+BA_TA_47_32_HI	include/ssv6200_aux.h	7179;"	d
+BA_TA_47_32_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6354;"	d
+BA_TA_47_32_I_MSK	include/ssv6200_aux.h	7177;"	d
+BA_TA_47_32_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6352;"	d
+BA_TA_47_32_MSK	include/ssv6200_aux.h	7176;"	d
+BA_TA_47_32_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6351;"	d
+BA_TA_47_32_SFT	include/ssv6200_aux.h	7178;"	d
+BA_TA_47_32_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6353;"	d
+BA_TA_47_32_SZ	include/ssv6200_aux.h	7180;"	d
+BA_TA_47_32_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6355;"	d
+BA_TID_HI	include/ssv6200_aux.h	7184;"	d
+BA_TID_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6359;"	d
+BA_TID_I_MSK	include/ssv6200_aux.h	7182;"	d
+BA_TID_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6357;"	d
+BA_TID_MSK	include/ssv6200_aux.h	7181;"	d
+BA_TID_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6356;"	d
+BA_TID_SFT	include/ssv6200_aux.h	7183;"	d
+BA_TID_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6358;"	d
+BA_TID_SZ	include/ssv6200_aux.h	7185;"	d
+BA_TID_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6360;"	d
+BA_WAIT_TIMEOUT	smac/ampdu.c	26;"	d	file:
+BA_ack_ploicy	smac/ampdu.h	/^    u16 BA_ack_ploicy:1;$/;"	m	struct:AMPDU_BLOCKACK_st	access:public
+BA_fragment_sn	smac/ampdu.h	/^    u16 BA_fragment_sn:4;$/;"	m	struct:AMPDU_BLOCKACK_st	access:public
+BA_sn_bit_map	smac/ampdu.h	/^    u32 BA_sn_bit_map[2];$/;"	m	struct:AMPDU_BLOCKACK_st	access:public
+BA_ssn	smac/ampdu.h	/^    u16 BA_ssn:12;$/;"	m	struct:AMPDU_BLOCKACK_st	access:public
+BCAST_RATEUNKNOW_HI	include/ssv6200_aux.h	8724;"	d
+BCAST_RATEUNKNOW_I_MSK	include/ssv6200_aux.h	8722;"	d
+BCAST_RATEUNKNOW_MSK	include/ssv6200_aux.h	8721;"	d
+BCAST_RATEUNKNOW_SFT	include/ssv6200_aux.h	8723;"	d
+BCAST_RATEUNKNOW_SZ	include/ssv6200_aux.h	8725;"	d
+BEACON_ENABLED	include/hal.h	29;"	d
+BEACON_ENABLED	smac/ap.h	20;"	d
+BEACON_HDR_LEN	smac/hal/ssv6006c/ssv6006C_mac.c	964;"	d	file:
+BEACON_MISS_RSSI_THRESHOLD	smac/dev.c	5881;"	d	file:
+BEACON_TIMEOUT_EN_HI	include/ssv6200_aux.h	9249;"	d
+BEACON_TIMEOUT_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9039;"	d
+BEACON_TIMEOUT_EN_I_MSK	include/ssv6200_aux.h	9247;"	d
+BEACON_TIMEOUT_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9037;"	d
+BEACON_TIMEOUT_EN_MSK	include/ssv6200_aux.h	9246;"	d
+BEACON_TIMEOUT_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9036;"	d
+BEACON_TIMEOUT_EN_SFT	include/ssv6200_aux.h	9248;"	d
+BEACON_TIMEOUT_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9038;"	d
+BEACON_TIMEOUT_EN_SZ	include/ssv6200_aux.h	9250;"	d
+BEACON_TIMEOUT_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9040;"	d
+BEACON_TIMEOUT_HI	include/ssv6200_aux.h	9294;"	d
+BEACON_TIMEOUT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9084;"	d
+BEACON_TIMEOUT_I_MSK	include/ssv6200_aux.h	9292;"	d
+BEACON_TIMEOUT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9082;"	d
+BEACON_TIMEOUT_MSK	include/ssv6200_aux.h	9291;"	d
+BEACON_TIMEOUT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9081;"	d
+BEACON_TIMEOUT_SFT	include/ssv6200_aux.h	9293;"	d
+BEACON_TIMEOUT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9083;"	d
+BEACON_TIMEOUT_SZ	include/ssv6200_aux.h	9295;"	d
+BEACON_TIMEOUT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9085;"	d
+BEACON_WAITING_ENABLED	include/hal.h	28;"	d
+BEACON_WAITING_ENABLED	smac/ap.h	19;"	d
+BFALSE	smac/sec_wpi.h	/^typedef enum {BFALSE = 0,$/;"	e	enum:__anon11
+BIST_CLK_EN_HI	include/ssv6200_aux.h	289;"	d
+BIST_CLK_EN_I_MSK	include/ssv6200_aux.h	287;"	d
+BIST_CLK_EN_MSK	include/ssv6200_aux.h	286;"	d
+BIST_CLK_EN_SFT	include/ssv6200_aux.h	288;"	d
+BIST_CLK_EN_SZ	include/ssv6200_aux.h	290;"	d
+BIT1_RD_CMD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4089;"	d
+BIT1_RD_CMD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4087;"	d
+BIT1_RD_CMD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4086;"	d
+BIT1_RD_CMD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4088;"	d
+BIT1_RD_CMD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4090;"	d
+BIT1_WR_CMD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4084;"	d
+BIT1_WR_CMD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4082;"	d
+BIT1_WR_CMD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4081;"	d
+BIT1_WR_CMD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4083;"	d
+BIT1_WR_CMD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4085;"	d
+BIT2_RD_CMD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4094;"	d
+BIT2_RD_CMD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4092;"	d
+BIT2_RD_CMD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4091;"	d
+BIT2_RD_CMD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4093;"	d
+BIT2_RD_CMD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4095;"	d
+BIT4_RD_CMD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4099;"	d
+BIT4_RD_CMD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4097;"	d
+BIT4_RD_CMD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4096;"	d
+BIT4_RD_CMD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4098;"	d
+BIT4_RD_CMD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4100;"	d
+BIT4_WR_CMD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4104;"	d
+BIT4_WR_CMD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4102;"	d
+BIT4_WR_CMD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4101;"	d
+BIT4_WR_CMD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4103;"	d
+BIT4_WR_CMD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4105;"	d
+BITS_PER_BYTE	smac/dev.h	156;"	d
+BIT_MODE1_HI	include/ssv6200_aux.h	5734;"	d
+BIT_MODE1_I_MSK	include/ssv6200_aux.h	5732;"	d
+BIT_MODE1_MSK	include/ssv6200_aux.h	5731;"	d
+BIT_MODE1_SFT	include/ssv6200_aux.h	5733;"	d
+BIT_MODE1_SZ	include/ssv6200_aux.h	5735;"	d
+BIT_MODE2_HI	include/ssv6200_aux.h	5739;"	d
+BIT_MODE2_I_MSK	include/ssv6200_aux.h	5737;"	d
+BIT_MODE2_MSK	include/ssv6200_aux.h	5736;"	d
+BIT_MODE2_SFT	include/ssv6200_aux.h	5738;"	d
+BIT_MODE2_SZ	include/ssv6200_aux.h	5740;"	d
+BIT_MODE4_HI	include/ssv6200_aux.h	5744;"	d
+BIT_MODE4_I_MSK	include/ssv6200_aux.h	5742;"	d
+BIT_MODE4_MSK	include/ssv6200_aux.h	5741;"	d
+BIT_MODE4_SFT	include/ssv6200_aux.h	5743;"	d
+BIT_MODE4_SZ	include/ssv6200_aux.h	5745;"	d
+BLOCKSIZE	bridge/sdiobridge.c	39;"	d	file:
+BLOCKSIZE	hci_wrapper/ssv_huw.c	30;"	d	file:
+BLOCK_TXQ_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6824;"	d
+BLOCK_TXQ_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6822;"	d
+BLOCK_TXQ_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6821;"	d
+BLOCK_TXQ_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6823;"	d
+BLOCK_TXQ_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6825;"	d
+BOOL_T	smac/sec_wpi.h	/^} BOOL_T;$/;"	t	typeref:enum:__anon11
+BOOT_ADDR_HI	include/ssv6200_aux.h	5654;"	d
+BOOT_ADDR_I_MSK	include/ssv6200_aux.h	5652;"	d
+BOOT_ADDR_MSK	include/ssv6200_aux.h	5651;"	d
+BOOT_ADDR_SFT	include/ssv6200_aux.h	5653;"	d
+BOOT_ADDR_SZ	include/ssv6200_aux.h	5655;"	d
+BOOT_CHECK_SUM_HI	include/ssv6200_aux.h	5749;"	d
+BOOT_CHECK_SUM_I_MSK	include/ssv6200_aux.h	5747;"	d
+BOOT_CHECK_SUM_MSK	include/ssv6200_aux.h	5746;"	d
+BOOT_CHECK_SUM_SFT	include/ssv6200_aux.h	5748;"	d
+BOOT_CHECK_SUM_SZ	include/ssv6200_aux.h	5750;"	d
+BRDC_DIV_HI	include/ssv6200_aux.h	4469;"	d
+BRDC_DIV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3579;"	d
+BRDC_DIV_I_MSK	include/ssv6200_aux.h	4467;"	d
+BRDC_DIV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3577;"	d
+BRDC_DIV_MSK	include/ssv6200_aux.h	4466;"	d
+BRDC_DIV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3576;"	d
+BRDC_DIV_SFT	include/ssv6200_aux.h	4468;"	d
+BRDC_DIV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3578;"	d
+BRDC_DIV_SZ	include/ssv6200_aux.h	4470;"	d
+BRDC_DIV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3580;"	d
+BREAK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3659;"	d
+BREAK_INT_HI	include/ssv6200_aux.h	4409;"	d
+BREAK_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3519;"	d
+BREAK_INT_I_MSK	include/ssv6200_aux.h	4407;"	d
+BREAK_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3517;"	d
+BREAK_INT_MSK	include/ssv6200_aux.h	4406;"	d
+BREAK_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3516;"	d
+BREAK_INT_SFT	include/ssv6200_aux.h	4408;"	d
+BREAK_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3518;"	d
+BREAK_INT_SZ	include/ssv6200_aux.h	4410;"	d
+BREAK_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3520;"	d
+BREAK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3657;"	d
+BREAK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3656;"	d
+BREAK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3658;"	d
+BREAK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3660;"	d
+BRST_MODE_HI	include/ssv6200_aux.h	3949;"	d
+BRST_MODE_I_MSK	include/ssv6200_aux.h	3947;"	d
+BRST_MODE_MSK	include/ssv6200_aux.h	3946;"	d
+BRST_MODE_SFT	include/ssv6200_aux.h	3948;"	d
+BRST_MODE_SZ	include/ssv6200_aux.h	3950;"	d
+BSSID1_31_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8984;"	d
+BSSID1_31_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8982;"	d
+BSSID1_31_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8981;"	d
+BSSID1_31_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8983;"	d
+BSSID1_31_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8985;"	d
+BSSID1_47_32_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8989;"	d
+BSSID1_47_32_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8987;"	d
+BSSID1_47_32_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8986;"	d
+BSSID1_47_32_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8988;"	d
+BSSID1_47_32_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8990;"	d
+BSSID_31_0_HI	include/ssv6200_aux.h	9174;"	d
+BSSID_31_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8939;"	d
+BSSID_31_0_I_MSK	include/ssv6200_aux.h	9172;"	d
+BSSID_31_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8937;"	d
+BSSID_31_0_MSK	include/ssv6200_aux.h	9171;"	d
+BSSID_31_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8936;"	d
+BSSID_31_0_SFT	include/ssv6200_aux.h	9173;"	d
+BSSID_31_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8938;"	d
+BSSID_31_0_SZ	include/ssv6200_aux.h	9175;"	d
+BSSID_31_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8940;"	d
+BSSID_47_32_HI	include/ssv6200_aux.h	9179;"	d
+BSSID_47_32_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8944;"	d
+BSSID_47_32_I_MSK	include/ssv6200_aux.h	9177;"	d
+BSSID_47_32_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8942;"	d
+BSSID_47_32_MSK	include/ssv6200_aux.h	9176;"	d
+BSSID_47_32_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8941;"	d
+BSSID_47_32_SFT	include/ssv6200_aux.h	9178;"	d
+BSSID_47_32_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8943;"	d
+BSSID_47_32_SZ	include/ssv6200_aux.h	9180;"	d
+BSSID_47_32_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8945;"	d
+BSS_CHANGED_SSID	smac/linux_2_6_35.h	34;"	d
+BSS_CHANGED_SSID	smac/linux_3_0_0.h	18;"	d
+BSS_HI	include/ssv6200_aux.h	3734;"	d
+BSS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2869;"	d
+BSS_I_MSK	include/ssv6200_aux.h	3732;"	d
+BSS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2867;"	d
+BSS_MSK	include/ssv6200_aux.h	3731;"	d
+BSS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2866;"	d
+BSS_SFT	include/ssv6200_aux.h	3733;"	d
+BSS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2868;"	d
+BSS_SZ	include/ssv6200_aux.h	3735;"	d
+BSS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2870;"	d
+BTCX_CLK_EN_HI	include/ssv6200_aux.h	239;"	d
+BTCX_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1189;"	d
+BTCX_CLK_EN_I_MSK	include/ssv6200_aux.h	237;"	d
+BTCX_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1187;"	d
+BTCX_CLK_EN_MSK	include/ssv6200_aux.h	236;"	d
+BTCX_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1186;"	d
+BTCX_CLK_EN_SFT	include/ssv6200_aux.h	238;"	d
+BTCX_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1188;"	d
+BTCX_CLK_EN_SZ	include/ssv6200_aux.h	240;"	d
+BTCX_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1190;"	d
+BTCX_CSR_CLK_EN_HI	include/ssv6200_aux.h	299;"	d
+BTCX_CSR_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1309;"	d
+BTCX_CSR_CLK_EN_I_MSK	include/ssv6200_aux.h	297;"	d
+BTCX_CSR_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1307;"	d
+BTCX_CSR_CLK_EN_MSK	include/ssv6200_aux.h	296;"	d
+BTCX_CSR_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1306;"	d
+BTCX_CSR_CLK_EN_SFT	include/ssv6200_aux.h	298;"	d
+BTCX_CSR_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1308;"	d
+BTCX_CSR_CLK_EN_SZ	include/ssv6200_aux.h	300;"	d
+BTCX_CSR_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1310;"	d
+BTCX_INTR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9164;"	d
+BTCX_INTR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9162;"	d
+BTCX_INTR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9161;"	d
+BTCX_INTR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9163;"	d
+BTCX_INTR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9165;"	d
+BTCX_INT_MASK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9159;"	d
+BTCX_INT_MASK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9157;"	d
+BTCX_INT_MASK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9156;"	d
+BTCX_INT_MASK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9158;"	d
+BTCX_INT_MASK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9160;"	d
+BTCX_REG_BANK_SIZE	include/ssv6200_reg.h	106;"	d
+BTCX_REG_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	127;"	d
+BTCX_REG_BASE	include/ssv6200_reg.h	57;"	d
+BTCX_REG_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	66;"	d
+BTCX_SW_RST_HI	include/ssv6200_aux.h	69;"	d
+BTCX_SW_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1024;"	d
+BTCX_SW_RST_I_MSK	include/ssv6200_aux.h	67;"	d
+BTCX_SW_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1022;"	d
+BTCX_SW_RST_MSK	include/ssv6200_aux.h	66;"	d
+BTCX_SW_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1021;"	d
+BTCX_SW_RST_SFT	include/ssv6200_aux.h	68;"	d
+BTCX_SW_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1023;"	d
+BTCX_SW_RST_SZ	include/ssv6200_aux.h	70;"	d
+BTCX_SW_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1025;"	d
+BTRUE	smac/sec_wpi.h	/^              BTRUE = 1$/;"	e	enum:__anon11
+BT_2WIRE_EN_MSK	include/ssv6200.h	95;"	d
+BT_2WIRE_EN_MSK	include/ssv6xxx_cfg.h	93;"	d
+BT_2WIRE_EN_MSK	smac/hal/ssv6006c/ssv6006_cfg.h	79;"	d
+BT_BUSY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7414;"	d
+BT_BUSY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7412;"	d
+BT_BUSY_MANUAL_EN_HI	include/ssv6200_aux.h	9334;"	d
+BT_BUSY_MANUAL_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9124;"	d
+BT_BUSY_MANUAL_EN_I_MSK	include/ssv6200_aux.h	9332;"	d
+BT_BUSY_MANUAL_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9122;"	d
+BT_BUSY_MANUAL_EN_MSK	include/ssv6200_aux.h	9331;"	d
+BT_BUSY_MANUAL_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9121;"	d
+BT_BUSY_MANUAL_EN_SFT	include/ssv6200_aux.h	9333;"	d
+BT_BUSY_MANUAL_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9123;"	d
+BT_BUSY_MANUAL_EN_SZ	include/ssv6200_aux.h	9335;"	d
+BT_BUSY_MANUAL_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9125;"	d
+BT_BUSY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7411;"	d
+BT_BUSY_SET_HI	include/ssv6200_aux.h	9339;"	d
+BT_BUSY_SET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9129;"	d
+BT_BUSY_SET_I_MSK	include/ssv6200_aux.h	9337;"	d
+BT_BUSY_SET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9127;"	d
+BT_BUSY_SET_MSK	include/ssv6200_aux.h	9336;"	d
+BT_BUSY_SET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9126;"	d
+BT_BUSY_SET_SFT	include/ssv6200_aux.h	9338;"	d
+BT_BUSY_SET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9128;"	d
+BT_BUSY_SET_SZ	include/ssv6200_aux.h	9340;"	d
+BT_BUSY_SET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9130;"	d
+BT_BUSY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7413;"	d
+BT_BUSY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7415;"	d
+BT_PRI_SMP_TIME_HI	include/ssv6200_aux.h	9284;"	d
+BT_PRI_SMP_TIME_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9074;"	d
+BT_PRI_SMP_TIME_I_MSK	include/ssv6200_aux.h	9282;"	d
+BT_PRI_SMP_TIME_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9072;"	d
+BT_PRI_SMP_TIME_MSK	include/ssv6200_aux.h	9281;"	d
+BT_PRI_SMP_TIME_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9071;"	d
+BT_PRI_SMP_TIME_SFT	include/ssv6200_aux.h	9283;"	d
+BT_PRI_SMP_TIME_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9073;"	d
+BT_PRI_SMP_TIME_SZ	include/ssv6200_aux.h	9285;"	d
+BT_PRI_SMP_TIME_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9075;"	d
+BT_STA_SMP_TIME_HI	include/ssv6200_aux.h	9289;"	d
+BT_STA_SMP_TIME_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9079;"	d
+BT_STA_SMP_TIME_I_MSK	include/ssv6200_aux.h	9287;"	d
+BT_STA_SMP_TIME_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9077;"	d
+BT_STA_SMP_TIME_MSK	include/ssv6200_aux.h	9286;"	d
+BT_STA_SMP_TIME_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9076;"	d
+BT_STA_SMP_TIME_SFT	include/ssv6200_aux.h	9288;"	d
+BT_STA_SMP_TIME_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9078;"	d
+BT_STA_SMP_TIME_SZ	include/ssv6200_aux.h	9290;"	d
+BT_STA_SMP_TIME_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9080;"	d
+BT_SW_O_C_HI	include/ssv6200_aux.h	989;"	d
+BT_SW_O_C_I_MSK	include/ssv6200_aux.h	987;"	d
+BT_SW_O_C_MSK	include/ssv6200_aux.h	986;"	d
+BT_SW_O_C_SFT	include/ssv6200_aux.h	988;"	d
+BT_SW_O_C_SZ	include/ssv6200_aux.h	990;"	d
+BT_SW_O_OE_HI	include/ssv6200_aux.h	959;"	d
+BT_SW_O_OE_I_MSK	include/ssv6200_aux.h	957;"	d
+BT_SW_O_OE_MSK	include/ssv6200_aux.h	956;"	d
+BT_SW_O_OE_SFT	include/ssv6200_aux.h	958;"	d
+BT_SW_O_OE_SZ	include/ssv6200_aux.h	960;"	d
+BT_SW_O_PE_HI	include/ssv6200_aux.h	964;"	d
+BT_SW_O_PE_I_MSK	include/ssv6200_aux.h	962;"	d
+BT_SW_O_PE_MSK	include/ssv6200_aux.h	961;"	d
+BT_SW_O_PE_SFT	include/ssv6200_aux.h	963;"	d
+BT_SW_O_PE_SZ	include/ssv6200_aux.h	965;"	d
+BT_SW_POL_HI	include/ssv6200_aux.h	9279;"	d
+BT_SW_POL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9069;"	d
+BT_SW_POL_I_MSK	include/ssv6200_aux.h	9277;"	d
+BT_SW_POL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9067;"	d
+BT_SW_POL_MSK	include/ssv6200_aux.h	9276;"	d
+BT_SW_POL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9066;"	d
+BT_SW_POL_SFT	include/ssv6200_aux.h	9278;"	d
+BT_SW_POL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9068;"	d
+BT_SW_POL_SZ	include/ssv6200_aux.h	9280;"	d
+BT_SW_POL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9070;"	d
+BT_TRX_SMP_TIME_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9154;"	d
+BT_TRX_SMP_TIME_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9152;"	d
+BT_TRX_SMP_TIME_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9151;"	d
+BT_TRX_SMP_TIME_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9153;"	d
+BT_TRX_SMP_TIME_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9155;"	d
+BT_TXBAR_MANUAL_EN_HI	include/ssv6200_aux.h	9324;"	d
+BT_TXBAR_MANUAL_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9114;"	d
+BT_TXBAR_MANUAL_EN_I_MSK	include/ssv6200_aux.h	9322;"	d
+BT_TXBAR_MANUAL_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9112;"	d
+BT_TXBAR_MANUAL_EN_MSK	include/ssv6200_aux.h	9321;"	d
+BT_TXBAR_MANUAL_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9111;"	d
+BT_TXBAR_MANUAL_EN_SFT	include/ssv6200_aux.h	9323;"	d
+BT_TXBAR_MANUAL_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9113;"	d
+BT_TXBAR_MANUAL_EN_SZ	include/ssv6200_aux.h	9325;"	d
+BT_TXBAR_MANUAL_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9115;"	d
+BT_TXBAR_SET_HI	include/ssv6200_aux.h	9329;"	d
+BT_TXBAR_SET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9119;"	d
+BT_TXBAR_SET_I_MSK	include/ssv6200_aux.h	9327;"	d
+BT_TXBAR_SET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9117;"	d
+BT_TXBAR_SET_MSK	include/ssv6200_aux.h	9326;"	d
+BT_TXBAR_SET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9116;"	d
+BT_TXBAR_SET_SFT	include/ssv6200_aux.h	9328;"	d
+BT_TXBAR_SET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9118;"	d
+BT_TXBAR_SET_SZ	include/ssv6200_aux.h	9330;"	d
+BT_TXBAR_SET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9120;"	d
+BUSINESS_NAME_AUDIO_MSG	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	22;"	d
+BUSINESS_NAME_IMAGE_MSG	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	21;"	d
+BUSINESS_NAME_NAS_DEVPUSHFILE	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	24;"	d
+BUSINESS_NAME_NAS_DEVPUSHTHUMB	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	25;"	d
+BUSINESS_NAME_VIDEO_MSG	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	23;"	d
+BYPASSS_TX_PARSER_ENCAP_HI	include/ssv6200_aux.h	6069;"	d
+BYPASSS_TX_PARSER_ENCAP_I_MSK	include/ssv6200_aux.h	6067;"	d
+BYPASSS_TX_PARSER_ENCAP_MSK	include/ssv6200_aux.h	6066;"	d
+BYPASSS_TX_PARSER_ENCAP_SFT	include/ssv6200_aux.h	6068;"	d
+BYPASSS_TX_PARSER_ENCAP_SZ	include/ssv6200_aux.h	6070;"	d
+BYPASS_TX_PARSER_ENCAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5119;"	d
+BYPASS_TX_PARSER_ENCAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5117;"	d
+BYPASS_TX_PARSER_ENCAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5116;"	d
+BYPASS_TX_PARSER_ENCAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5118;"	d
+BYPASS_TX_PARSER_ENCAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5120;"	d
+BYTES_PER_WORD	smac/wapi_sms4.c	24;"	d	file:
+BYTE_LEN	smac/wapi_sms4.c	25;"	d	file:
+B_CCA_CNT_HI	include/ssv6200_aux.h	14619;"	d
+B_CCA_CNT_I_MSK	include/ssv6200_aux.h	14617;"	d
+B_CCA_CNT_MSK	include/ssv6200_aux.h	14616;"	d
+B_CCA_CNT_SFT	include/ssv6200_aux.h	14618;"	d
+B_CCA_CNT_SZ	include/ssv6200_aux.h	14620;"	d
+B_FREQ_OS_HI	include/ssv6200_aux.h	14579;"	d
+B_FREQ_OS_I_MSK	include/ssv6200_aux.h	14577;"	d
+B_FREQ_OS_MSK	include/ssv6200_aux.h	14576;"	d
+B_FREQ_OS_SFT	include/ssv6200_aux.h	14578;"	d
+B_FREQ_OS_SZ	include/ssv6200_aux.h	14580;"	d
+B_LENGTH_FIELD_HI	include/ssv6200_aux.h	14624;"	d
+B_LENGTH_FIELD_I_MSK	include/ssv6200_aux.h	14622;"	d
+B_LENGTH_FIELD_MSK	include/ssv6200_aux.h	14621;"	d
+B_LENGTH_FIELD_SFT	include/ssv6200_aux.h	14623;"	d
+B_LENGTH_FIELD_SZ	include/ssv6200_aux.h	14625;"	d
+B_PACKET_CNT_HI	include/ssv6200_aux.h	14614;"	d
+B_PACKET_CNT_I_MSK	include/ssv6200_aux.h	14612;"	d
+B_PACKET_CNT_MSK	include/ssv6200_aux.h	14611;"	d
+B_PACKET_CNT_SFT	include/ssv6200_aux.h	14613;"	d
+B_PACKET_CNT_SZ	include/ssv6200_aux.h	14615;"	d
+B_PACKET_ERR_CNT_HI	include/ssv6200_aux.h	14604;"	d
+B_PACKET_ERR_CNT_I_MSK	include/ssv6200_aux.h	14602;"	d
+B_PACKET_ERR_CNT_MSK	include/ssv6200_aux.h	14601;"	d
+B_PACKET_ERR_CNT_SFT	include/ssv6200_aux.h	14603;"	d
+B_PACKET_ERR_CNT_SZ	include/ssv6200_aux.h	14605;"	d
+B_RCPI_HI	include/ssv6200_aux.h	14589;"	d
+B_RCPI_I_MSK	include/ssv6200_aux.h	14587;"	d
+B_RCPI_MSK	include/ssv6200_aux.h	14586;"	d
+B_RCPI_SFT	include/ssv6200_aux.h	14588;"	d
+B_RCPI_SZ	include/ssv6200_aux.h	14590;"	d
+B_SERVICE_FIELD_HI	include/ssv6200_aux.h	14639;"	d
+B_SERVICE_FIELD_I_MSK	include/ssv6200_aux.h	14637;"	d
+B_SERVICE_FIELD_MSK	include/ssv6200_aux.h	14636;"	d
+B_SERVICE_FIELD_SFT	include/ssv6200_aux.h	14638;"	d
+B_SERVICE_FIELD_SZ	include/ssv6200_aux.h	14640;"	d
+B_SNR_HI	include/ssv6200_aux.h	14584;"	d
+B_SNR_I_MSK	include/ssv6200_aux.h	14582;"	d
+B_SNR_MSK	include/ssv6200_aux.h	14581;"	d
+B_SNR_SFT	include/ssv6200_aux.h	14583;"	d
+B_SNR_SZ	include/ssv6200_aux.h	14585;"	d
+CABRIO_H	include/cabrio.h	17;"	d
+CALCULATE_HI	include/ssv6200_aux.h	6359;"	d
+CALCULATE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5604;"	d
+CALCULATE_I_MSK	include/ssv6200_aux.h	6357;"	d
+CALCULATE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5602;"	d
+CALCULATE_MSK	include/ssv6200_aux.h	6356;"	d
+CALCULATE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5601;"	d
+CALCULATE_SFT	include/ssv6200_aux.h	6358;"	d
+CALCULATE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5603;"	d
+CALCULATE_SZ	include/ssv6200_aux.h	6360;"	d
+CALCULATE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5605;"	d
+CAL_IDX_5G_NONE	smac/hal/ssv6006c/turismo_common.h	/^    CAL_IDX_5G_NONE,$/;"	e	enum:__anon4
+CAL_IDX_5G_NONE2	smac/hal/ssv6006c/turismo_common.h	/^    CAL_IDX_5G_NONE2,$/;"	e	enum:__anon4
+CAL_IDX_BT_RXDC	smac/hal/ssv6006c/turismo_common.h	/^    CAL_IDX_BT_RXDC,$/;"	e	enum:__anon4
+CAL_IDX_BW20_RXRC	smac/hal/ssv6006c/turismo_common.h	/^    CAL_IDX_BW20_RXRC,$/;"	e	enum:__anon4
+CAL_IDX_BW40_RXRC	smac/hal/ssv6006c/turismo_common.h	/^    CAL_IDX_BW40_RXRC,$/;"	e	enum:__anon4
+CAL_IDX_NONE	smac/hal/ssv6006c/turismo_common.h	/^    CAL_IDX_NONE,$/;"	e	enum:__anon4
+CAL_IDX_WIFI2P4G_PADPD	smac/hal/ssv6006c/turismo_common.h	/^    CAL_IDX_WIFI2P4G_PADPD,$/;"	e	enum:__anon4
+CAL_IDX_WIFI2P4G_RXDC	smac/hal/ssv6006c/turismo_common.h	/^    CAL_IDX_WIFI2P4G_RXDC,$/;"	e	enum:__anon4
+CAL_IDX_WIFI2P4G_RXIQ	smac/hal/ssv6006c/turismo_common.h	/^    CAL_IDX_WIFI2P4G_RXIQ,$/;"	e	enum:__anon4
+CAL_IDX_WIFI2P4G_TXIQ	smac/hal/ssv6006c/turismo_common.h	/^    CAL_IDX_WIFI2P4G_TXIQ,$/;"	e	enum:__anon4
+CAL_IDX_WIFI2P4G_TXLO	smac/hal/ssv6006c/turismo_common.h	/^    CAL_IDX_WIFI2P4G_TXLO,$/;"	e	enum:__anon4
+CAL_IDX_WIFI5G_PADPD	smac/hal/ssv6006c/turismo_common.h	/^    CAL_IDX_WIFI5G_PADPD,$/;"	e	enum:__anon4
+CAL_IDX_WIFI5G_RXDC	smac/hal/ssv6006c/turismo_common.h	/^    CAL_IDX_WIFI5G_RXDC,$/;"	e	enum:__anon4
+CAL_IDX_WIFI5G_RXIQ	smac/hal/ssv6006c/turismo_common.h	/^    CAL_IDX_WIFI5G_RXIQ,$/;"	e	enum:__anon4
+CAL_IDX_WIFI5G_TXIQ	smac/hal/ssv6006c/turismo_common.h	/^    CAL_IDX_WIFI5G_TXIQ,$/;"	e	enum:__anon4
+CAL_IDX_WIFI5G_TXLO	smac/hal/ssv6006c/turismo_common.h	/^    CAL_IDX_WIFI5G_TXLO,$/;"	e	enum:__anon4
+CARD_FW_DL_STATUS_HI	include/ssv6200_aux.h	3179;"	d
+CARD_FW_DL_STATUS_I_MSK	include/ssv6200_aux.h	3177;"	d
+CARD_FW_DL_STATUS_MSK	include/ssv6200_aux.h	3176;"	d
+CARD_FW_DL_STATUS_SFT	include/ssv6200_aux.h	3178;"	d
+CARD_FW_DL_STATUS_SZ	include/ssv6200_aux.h	3180;"	d
+CARD_RCA_REG_HI	include/ssv6200_aux.h	3264;"	d
+CARD_RCA_REG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2644;"	d
+CARD_RCA_REG_I_MSK	include/ssv6200_aux.h	3262;"	d
+CARD_RCA_REG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2642;"	d
+CARD_RCA_REG_MSK	include/ssv6200_aux.h	3261;"	d
+CARD_RCA_REG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2641;"	d
+CARD_RCA_REG_SFT	include/ssv6200_aux.h	3263;"	d
+CARD_RCA_REG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2643;"	d
+CARD_RCA_REG_SZ	include/ssv6200_aux.h	3265;"	d
+CARD_RCA_REG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2645;"	d
+CBR_AD_DP_VT_MON_Q_HI	include/ssv6200_aux.h	11219;"	d
+CBR_AD_DP_VT_MON_Q_I_MSK	include/ssv6200_aux.h	11217;"	d
+CBR_AD_DP_VT_MON_Q_MSK	include/ssv6200_aux.h	11216;"	d
+CBR_AD_DP_VT_MON_Q_SFT	include/ssv6200_aux.h	11218;"	d
+CBR_AD_DP_VT_MON_Q_SZ	include/ssv6200_aux.h	11220;"	d
+CBR_AD_SX_VT_MON_Q_HI	include/ssv6200_aux.h	11214;"	d
+CBR_AD_SX_VT_MON_Q_I_MSK	include/ssv6200_aux.h	11212;"	d
+CBR_AD_SX_VT_MON_Q_MSK	include/ssv6200_aux.h	11211;"	d
+CBR_AD_SX_VT_MON_Q_SFT	include/ssv6200_aux.h	11213;"	d
+CBR_AD_SX_VT_MON_Q_SZ	include/ssv6200_aux.h	11215;"	d
+CBR_A_REG_BANK_SIZE	include/ssv6200_reg.h	108;"	d
+CBR_A_REG_BASE	include/ssv6200_reg.h	59;"	d
+CBR_CH_RDY_HI	include/ssv6200_aux.h	11204;"	d
+CBR_CH_RDY_I_MSK	include/ssv6200_aux.h	11202;"	d
+CBR_CH_RDY_MSK	include/ssv6200_aux.h	11201;"	d
+CBR_CH_RDY_SFT	include/ssv6200_aux.h	11203;"	d
+CBR_CH_RDY_SZ	include/ssv6200_aux.h	11205;"	d
+CBR_DATA_OUT_SEL_HI	include/ssv6200_aux.h	11369;"	d
+CBR_DATA_OUT_SEL_I_MSK	include/ssv6200_aux.h	11367;"	d
+CBR_DATA_OUT_SEL_MSK	include/ssv6200_aux.h	11366;"	d
+CBR_DATA_OUT_SEL_SFT	include/ssv6200_aux.h	11368;"	d
+CBR_DATA_OUT_SEL_SZ	include/ssv6200_aux.h	11370;"	d
+CBR_DA_DP_BBPLL_BS_HI	include/ssv6200_aux.h	11234;"	d
+CBR_DA_DP_BBPLL_BS_I_MSK	include/ssv6200_aux.h	11232;"	d
+CBR_DA_DP_BBPLL_BS_MSK	include/ssv6200_aux.h	11231;"	d
+CBR_DA_DP_BBPLL_BS_SFT	include/ssv6200_aux.h	11233;"	d
+CBR_DA_DP_BBPLL_BS_SZ	include/ssv6200_aux.h	11235;"	d
+CBR_DA_LCK_RDY_HI	include/ssv6200_aux.h	11189;"	d
+CBR_DA_LCK_RDY_I_MSK	include/ssv6200_aux.h	11187;"	d
+CBR_DA_LCK_RDY_MSK	include/ssv6200_aux.h	11186;"	d
+CBR_DA_LCK_RDY_SFT	include/ssv6200_aux.h	11188;"	d
+CBR_DA_LCK_RDY_SZ	include/ssv6200_aux.h	11190;"	d
+CBR_DA_R_CAL_CODE_HI	include/ssv6200_aux.h	11224;"	d
+CBR_DA_R_CAL_CODE_I_MSK	include/ssv6200_aux.h	11222;"	d
+CBR_DA_R_CAL_CODE_MSK	include/ssv6200_aux.h	11221;"	d
+CBR_DA_R_CAL_CODE_SFT	include/ssv6200_aux.h	11223;"	d
+CBR_DA_R_CAL_CODE_SZ	include/ssv6200_aux.h	11225;"	d
+CBR_DA_R_CODE_LUT_HI	include/ssv6200_aux.h	11209;"	d
+CBR_DA_R_CODE_LUT_I_MSK	include/ssv6200_aux.h	11207;"	d
+CBR_DA_R_CODE_LUT_MSK	include/ssv6200_aux.h	11206;"	d
+CBR_DA_R_CODE_LUT_SFT	include/ssv6200_aux.h	11208;"	d
+CBR_DA_R_CODE_LUT_SZ	include/ssv6200_aux.h	11210;"	d
+CBR_DA_SX_SUB_SEL_HI	include/ssv6200_aux.h	11229;"	d
+CBR_DA_SX_SUB_SEL_I_MSK	include/ssv6200_aux.h	11227;"	d
+CBR_DA_SX_SUB_SEL_MSK	include/ssv6200_aux.h	11226;"	d
+CBR_DA_SX_SUB_SEL_SFT	include/ssv6200_aux.h	11228;"	d
+CBR_DA_SX_SUB_SEL_SZ	include/ssv6200_aux.h	11230;"	d
+CBR_DBG_EN_HI	include/ssv6200_aux.h	11349;"	d
+CBR_DBG_EN_I_MSK	include/ssv6200_aux.h	11347;"	d
+CBR_DBG_EN_MSK	include/ssv6200_aux.h	11346;"	d
+CBR_DBG_EN_SFT	include/ssv6200_aux.h	11348;"	d
+CBR_DBG_EN_SZ	include/ssv6200_aux.h	11350;"	d
+CBR_DBG_SEL_HI	include/ssv6200_aux.h	11344;"	d
+CBR_DBG_SEL_I_MSK	include/ssv6200_aux.h	11342;"	d
+CBR_DBG_SEL_MSK	include/ssv6200_aux.h	11341;"	d
+CBR_DBG_SEL_SFT	include/ssv6200_aux.h	11343;"	d
+CBR_DBG_SEL_SZ	include/ssv6200_aux.h	11345;"	d
+CBR_DP_VT_MON_RDY_HI	include/ssv6200_aux.h	11199;"	d
+CBR_DP_VT_MON_RDY_I_MSK	include/ssv6200_aux.h	11197;"	d
+CBR_DP_VT_MON_RDY_MSK	include/ssv6200_aux.h	11196;"	d
+CBR_DP_VT_MON_RDY_SFT	include/ssv6200_aux.h	11198;"	d
+CBR_DP_VT_MON_RDY_SZ	include/ssv6200_aux.h	11200;"	d
+CBR_FREQ_SEL_HI	include/ssv6200_aux.h	11379;"	d
+CBR_FREQ_SEL_I_MSK	include/ssv6200_aux.h	11377;"	d
+CBR_FREQ_SEL_MSK	include/ssv6200_aux.h	11376;"	d
+CBR_FREQ_SEL_SFT	include/ssv6200_aux.h	11378;"	d
+CBR_FREQ_SEL_SZ	include/ssv6200_aux.h	11380;"	d
+CBR_IDEAL_IQ_EN_HI	include/ssv6200_aux.h	11364;"	d
+CBR_IDEAL_IQ_EN_I_MSK	include/ssv6200_aux.h	11362;"	d
+CBR_IDEAL_IQ_EN_MSK	include/ssv6200_aux.h	11361;"	d
+CBR_IDEAL_IQ_EN_SFT	include/ssv6200_aux.h	11363;"	d
+CBR_IDEAL_IQ_EN_SZ	include/ssv6200_aux.h	11365;"	d
+CBR_IFS_TIME_HI	include/ssv6200_aux.h	11249;"	d
+CBR_IFS_TIME_I_MSK	include/ssv6200_aux.h	11247;"	d
+CBR_IFS_TIME_MSK	include/ssv6200_aux.h	11246;"	d
+CBR_IFS_TIME_SFT	include/ssv6200_aux.h	11248;"	d
+CBR_IFS_TIME_SZ	include/ssv6200_aux.h	11250;"	d
+CBR_INTP_SEL_HI	include/ssv6200_aux.h	11324;"	d
+CBR_INTP_SEL_I_MSK	include/ssv6200_aux.h	11322;"	d
+CBR_INTP_SEL_MSK	include/ssv6200_aux.h	11321;"	d
+CBR_INTP_SEL_SFT	include/ssv6200_aux.h	11323;"	d
+CBR_INTP_SEL_SZ	include/ssv6200_aux.h	11325;"	d
+CBR_IQ_SCALE_HI	include/ssv6200_aux.h	11384;"	d
+CBR_IQ_SCALE_I_MSK	include/ssv6200_aux.h	11382;"	d
+CBR_IQ_SCALE_MSK	include/ssv6200_aux.h	11381;"	d
+CBR_IQ_SCALE_SFT	include/ssv6200_aux.h	11383;"	d
+CBR_IQ_SCALE_SZ	include/ssv6200_aux.h	11385;"	d
+CBR_IQ_SWP_HI	include/ssv6200_aux.h	11329;"	d
+CBR_IQ_SWP_I_MSK	include/ssv6200_aux.h	11327;"	d
+CBR_IQ_SWP_MSK	include/ssv6200_aux.h	11326;"	d
+CBR_IQ_SWP_SFT	include/ssv6200_aux.h	11328;"	d
+CBR_IQ_SWP_SZ	include/ssv6200_aux.h	11330;"	d
+CBR_LENGTH_TARGET_HI	include/ssv6200_aux.h	11254;"	d
+CBR_LENGTH_TARGET_I_MSK	include/ssv6200_aux.h	11252;"	d
+CBR_LENGTH_TARGET_MSK	include/ssv6200_aux.h	11251;"	d
+CBR_LENGTH_TARGET_SFT	include/ssv6200_aux.h	11253;"	d
+CBR_LENGTH_TARGET_SZ	include/ssv6200_aux.h	11255;"	d
+CBR_PLCP_BYTE_LENGTH_HI	include/ssv6200_aux.h	11279;"	d
+CBR_PLCP_BYTE_LENGTH_I_MSK	include/ssv6200_aux.h	11277;"	d
+CBR_PLCP_BYTE_LENGTH_MSK	include/ssv6200_aux.h	11276;"	d
+CBR_PLCP_BYTE_LENGTH_SFT	include/ssv6200_aux.h	11278;"	d
+CBR_PLCP_BYTE_LENGTH_SZ	include/ssv6200_aux.h	11280;"	d
+CBR_PLCP_PSDU_DATA_MEM_HI	include/ssv6200_aux.h	11269;"	d
+CBR_PLCP_PSDU_DATA_MEM_I_MSK	include/ssv6200_aux.h	11267;"	d
+CBR_PLCP_PSDU_DATA_MEM_MSK	include/ssv6200_aux.h	11266;"	d
+CBR_PLCP_PSDU_DATA_MEM_SFT	include/ssv6200_aux.h	11268;"	d
+CBR_PLCP_PSDU_DATA_MEM_SZ	include/ssv6200_aux.h	11270;"	d
+CBR_PLCP_PSDU_PREAMBLE_SHORT_HI	include/ssv6200_aux.h	11274;"	d
+CBR_PLCP_PSDU_PREAMBLE_SHORT_I_MSK	include/ssv6200_aux.h	11272;"	d
+CBR_PLCP_PSDU_PREAMBLE_SHORT_MSK	include/ssv6200_aux.h	11271;"	d
+CBR_PLCP_PSDU_PREAMBLE_SHORT_SFT	include/ssv6200_aux.h	11273;"	d
+CBR_PLCP_PSDU_PREAMBLE_SHORT_SZ	include/ssv6200_aux.h	11275;"	d
+CBR_PLCP_PSDU_RATE_HI	include/ssv6200_aux.h	11284;"	d
+CBR_PLCP_PSDU_RATE_I_MSK	include/ssv6200_aux.h	11282;"	d
+CBR_PLCP_PSDU_RATE_MSK	include/ssv6200_aux.h	11281;"	d
+CBR_PLCP_PSDU_RATE_SFT	include/ssv6200_aux.h	11283;"	d
+CBR_PLCP_PSDU_RATE_SZ	include/ssv6200_aux.h	11285;"	d
+CBR_RCAL_RDY_HI	include/ssv6200_aux.h	11184;"	d
+CBR_RCAL_RDY_I_MSK	include/ssv6200_aux.h	11182;"	d
+CBR_RCAL_RDY_MSK	include/ssv6200_aux.h	11181;"	d
+CBR_RCAL_RDY_SFT	include/ssv6200_aux.h	11183;"	d
+CBR_RCAL_RDY_SZ	include/ssv6200_aux.h	11185;"	d
+CBR_RG_ADC_CLKSEL_HI	include/ssv6200_aux.h	10379;"	d
+CBR_RG_ADC_CLKSEL_I_MSK	include/ssv6200_aux.h	10377;"	d
+CBR_RG_ADC_CLKSEL_MSK	include/ssv6200_aux.h	10376;"	d
+CBR_RG_ADC_CLKSEL_SFT	include/ssv6200_aux.h	10378;"	d
+CBR_RG_ADC_CLKSEL_SZ	include/ssv6200_aux.h	10380;"	d
+CBR_RG_ADC_DIBIAS_HI	include/ssv6200_aux.h	10384;"	d
+CBR_RG_ADC_DIBIAS_I_MSK	include/ssv6200_aux.h	10382;"	d
+CBR_RG_ADC_DIBIAS_MSK	include/ssv6200_aux.h	10381;"	d
+CBR_RG_ADC_DIBIAS_SFT	include/ssv6200_aux.h	10383;"	d
+CBR_RG_ADC_DIBIAS_SZ	include/ssv6200_aux.h	10385;"	d
+CBR_RG_ADC_DIVR_HI	include/ssv6200_aux.h	10389;"	d
+CBR_RG_ADC_DIVR_I_MSK	include/ssv6200_aux.h	10387;"	d
+CBR_RG_ADC_DIVR_MSK	include/ssv6200_aux.h	10386;"	d
+CBR_RG_ADC_DIVR_SFT	include/ssv6200_aux.h	10388;"	d
+CBR_RG_ADC_DIVR_SZ	include/ssv6200_aux.h	10390;"	d
+CBR_RG_ADC_DVCMI_HI	include/ssv6200_aux.h	10394;"	d
+CBR_RG_ADC_DVCMI_I_MSK	include/ssv6200_aux.h	10392;"	d
+CBR_RG_ADC_DVCMI_MSK	include/ssv6200_aux.h	10391;"	d
+CBR_RG_ADC_DVCMI_SFT	include/ssv6200_aux.h	10393;"	d
+CBR_RG_ADC_DVCMI_SZ	include/ssv6200_aux.h	10395;"	d
+CBR_RG_ADC_SAMSEL_HI	include/ssv6200_aux.h	10399;"	d
+CBR_RG_ADC_SAMSEL_I_MSK	include/ssv6200_aux.h	10397;"	d
+CBR_RG_ADC_SAMSEL_MSK	include/ssv6200_aux.h	10396;"	d
+CBR_RG_ADC_SAMSEL_SFT	include/ssv6200_aux.h	10398;"	d
+CBR_RG_ADC_SAMSEL_SZ	include/ssv6200_aux.h	10400;"	d
+CBR_RG_ADC_STNBY_HI	include/ssv6200_aux.h	10404;"	d
+CBR_RG_ADC_STNBY_I_MSK	include/ssv6200_aux.h	10402;"	d
+CBR_RG_ADC_STNBY_MSK	include/ssv6200_aux.h	10401;"	d
+CBR_RG_ADC_STNBY_SFT	include/ssv6200_aux.h	10403;"	d
+CBR_RG_ADC_STNBY_SZ	include/ssv6200_aux.h	10405;"	d
+CBR_RG_ADC_TESTMODE_HI	include/ssv6200_aux.h	10409;"	d
+CBR_RG_ADC_TESTMODE_I_MSK	include/ssv6200_aux.h	10407;"	d
+CBR_RG_ADC_TESTMODE_MSK	include/ssv6200_aux.h	10406;"	d
+CBR_RG_ADC_TESTMODE_SFT	include/ssv6200_aux.h	10408;"	d
+CBR_RG_ADC_TESTMODE_SZ	include/ssv6200_aux.h	10410;"	d
+CBR_RG_ADC_TSEL_HI	include/ssv6200_aux.h	10414;"	d
+CBR_RG_ADC_TSEL_I_MSK	include/ssv6200_aux.h	10412;"	d
+CBR_RG_ADC_TSEL_MSK	include/ssv6200_aux.h	10411;"	d
+CBR_RG_ADC_TSEL_SFT	include/ssv6200_aux.h	10413;"	d
+CBR_RG_ADC_TSEL_SZ	include/ssv6200_aux.h	10415;"	d
+CBR_RG_ADC_VRSEL_HI	include/ssv6200_aux.h	10419;"	d
+CBR_RG_ADC_VRSEL_I_MSK	include/ssv6200_aux.h	10417;"	d
+CBR_RG_ADC_VRSEL_MSK	include/ssv6200_aux.h	10416;"	d
+CBR_RG_ADC_VRSEL_SFT	include/ssv6200_aux.h	10418;"	d
+CBR_RG_ADC_VRSEL_SZ	include/ssv6200_aux.h	10420;"	d
+CBR_RG_BUCK_LEVEL_HI	include/ssv6200_aux.h	9964;"	d
+CBR_RG_BUCK_LEVEL_I_MSK	include/ssv6200_aux.h	9962;"	d
+CBR_RG_BUCK_LEVEL_MSK	include/ssv6200_aux.h	9961;"	d
+CBR_RG_BUCK_LEVEL_SFT	include/ssv6200_aux.h	9963;"	d
+CBR_RG_BUCK_LEVEL_SZ	include/ssv6200_aux.h	9965;"	d
+CBR_RG_DACI1ST_HI	include/ssv6200_aux.h	10434;"	d
+CBR_RG_DACI1ST_I_MSK	include/ssv6200_aux.h	10432;"	d
+CBR_RG_DACI1ST_MSK	include/ssv6200_aux.h	10431;"	d
+CBR_RG_DACI1ST_SFT	include/ssv6200_aux.h	10433;"	d
+CBR_RG_DACI1ST_SZ	include/ssv6200_aux.h	10435;"	d
+CBR_RG_DCDC_MODE_HI	include/ssv6200_aux.h	9914;"	d
+CBR_RG_DCDC_MODE_I_MSK	include/ssv6200_aux.h	9912;"	d
+CBR_RG_DCDC_MODE_MSK	include/ssv6200_aux.h	9911;"	d
+CBR_RG_DCDC_MODE_SFT	include/ssv6200_aux.h	9913;"	d
+CBR_RG_DCDC_MODE_SZ	include/ssv6200_aux.h	9915;"	d
+CBR_RG_DICMP_HI	include/ssv6200_aux.h	10424;"	d
+CBR_RG_DICMP_I_MSK	include/ssv6200_aux.h	10422;"	d
+CBR_RG_DICMP_MSK	include/ssv6200_aux.h	10421;"	d
+CBR_RG_DICMP_SFT	include/ssv6200_aux.h	10423;"	d
+CBR_RG_DICMP_SZ	include/ssv6200_aux.h	10425;"	d
+CBR_RG_DIOP_HI	include/ssv6200_aux.h	10429;"	d
+CBR_RG_DIOP_I_MSK	include/ssv6200_aux.h	10427;"	d
+CBR_RG_DIOP_MSK	include/ssv6200_aux.h	10426;"	d
+CBR_RG_DIOP_SFT	include/ssv6200_aux.h	10428;"	d
+CBR_RG_DIOP_SZ	include/ssv6200_aux.h	10430;"	d
+CBR_RG_DIS_DA_OFFSET_HI	include/ssv6200_aux.h	11339;"	d
+CBR_RG_DIS_DA_OFFSET_I_MSK	include/ssv6200_aux.h	11337;"	d
+CBR_RG_DIS_DA_OFFSET_MSK	include/ssv6200_aux.h	11336;"	d
+CBR_RG_DIS_DA_OFFSET_SFT	include/ssv6200_aux.h	11338;"	d
+CBR_RG_DIS_DA_OFFSET_SZ	include/ssv6200_aux.h	11340;"	d
+CBR_RG_DP_BBPLL_BP_HI	include/ssv6200_aux.h	10904;"	d
+CBR_RG_DP_BBPLL_BP_I_MSK	include/ssv6200_aux.h	10902;"	d
+CBR_RG_DP_BBPLL_BP_MSK	include/ssv6200_aux.h	10901;"	d
+CBR_RG_DP_BBPLL_BP_SFT	include/ssv6200_aux.h	10903;"	d
+CBR_RG_DP_BBPLL_BP_SZ	include/ssv6200_aux.h	10905;"	d
+CBR_RG_DP_BBPLL_BS_CWD_HI	include/ssv6200_aux.h	11179;"	d
+CBR_RG_DP_BBPLL_BS_CWD_I_MSK	include/ssv6200_aux.h	11177;"	d
+CBR_RG_DP_BBPLL_BS_CWD_MSK	include/ssv6200_aux.h	11176;"	d
+CBR_RG_DP_BBPLL_BS_CWD_SFT	include/ssv6200_aux.h	11178;"	d
+CBR_RG_DP_BBPLL_BS_CWD_SZ	include/ssv6200_aux.h	11180;"	d
+CBR_RG_DP_BBPLL_BS_CWR_HI	include/ssv6200_aux.h	11174;"	d
+CBR_RG_DP_BBPLL_BS_CWR_I_MSK	include/ssv6200_aux.h	11172;"	d
+CBR_RG_DP_BBPLL_BS_CWR_MSK	include/ssv6200_aux.h	11171;"	d
+CBR_RG_DP_BBPLL_BS_CWR_SFT	include/ssv6200_aux.h	11173;"	d
+CBR_RG_DP_BBPLL_BS_CWR_SZ	include/ssv6200_aux.h	11175;"	d
+CBR_RG_DP_BBPLL_ICP_HI	include/ssv6200_aux.h	10909;"	d
+CBR_RG_DP_BBPLL_ICP_I_MSK	include/ssv6200_aux.h	10907;"	d
+CBR_RG_DP_BBPLL_ICP_MSK	include/ssv6200_aux.h	10906;"	d
+CBR_RG_DP_BBPLL_ICP_SFT	include/ssv6200_aux.h	10908;"	d
+CBR_RG_DP_BBPLL_ICP_SZ	include/ssv6200_aux.h	10910;"	d
+CBR_RG_DP_BBPLL_IDUAL_HI	include/ssv6200_aux.h	10914;"	d
+CBR_RG_DP_BBPLL_IDUAL_I_MSK	include/ssv6200_aux.h	10912;"	d
+CBR_RG_DP_BBPLL_IDUAL_MSK	include/ssv6200_aux.h	10911;"	d
+CBR_RG_DP_BBPLL_IDUAL_SFT	include/ssv6200_aux.h	10913;"	d
+CBR_RG_DP_BBPLL_IDUAL_SZ	include/ssv6200_aux.h	10915;"	d
+CBR_RG_DP_BBPLL_OD_TEST_HI	include/ssv6200_aux.h	10919;"	d
+CBR_RG_DP_BBPLL_OD_TEST_I_MSK	include/ssv6200_aux.h	10917;"	d
+CBR_RG_DP_BBPLL_OD_TEST_MSK	include/ssv6200_aux.h	10916;"	d
+CBR_RG_DP_BBPLL_OD_TEST_SFT	include/ssv6200_aux.h	10918;"	d
+CBR_RG_DP_BBPLL_OD_TEST_SZ	include/ssv6200_aux.h	10920;"	d
+CBR_RG_DP_BBPLL_PD_HI	include/ssv6200_aux.h	10924;"	d
+CBR_RG_DP_BBPLL_PD_I_MSK	include/ssv6200_aux.h	10922;"	d
+CBR_RG_DP_BBPLL_PD_MSK	include/ssv6200_aux.h	10921;"	d
+CBR_RG_DP_BBPLL_PD_SFT	include/ssv6200_aux.h	10923;"	d
+CBR_RG_DP_BBPLL_PD_SZ	include/ssv6200_aux.h	10925;"	d
+CBR_RG_DP_BBPLL_PFD_DLY_HI	include/ssv6200_aux.h	10934;"	d
+CBR_RG_DP_BBPLL_PFD_DLY_I_MSK	include/ssv6200_aux.h	10932;"	d
+CBR_RG_DP_BBPLL_PFD_DLY_MSK	include/ssv6200_aux.h	10931;"	d
+CBR_RG_DP_BBPLL_PFD_DLY_SFT	include/ssv6200_aux.h	10933;"	d
+CBR_RG_DP_BBPLL_PFD_DLY_SZ	include/ssv6200_aux.h	10935;"	d
+CBR_RG_DP_BBPLL_TESTSEL_HI	include/ssv6200_aux.h	10929;"	d
+CBR_RG_DP_BBPLL_TESTSEL_I_MSK	include/ssv6200_aux.h	10927;"	d
+CBR_RG_DP_BBPLL_TESTSEL_MSK	include/ssv6200_aux.h	10926;"	d
+CBR_RG_DP_BBPLL_TESTSEL_SFT	include/ssv6200_aux.h	10928;"	d
+CBR_RG_DP_BBPLL_TESTSEL_SZ	include/ssv6200_aux.h	10930;"	d
+CBR_RG_DP_CK320BY2_HI	include/ssv6200_aux.h	10889;"	d
+CBR_RG_DP_CK320BY2_I_MSK	include/ssv6200_aux.h	10887;"	d
+CBR_RG_DP_CK320BY2_MSK	include/ssv6200_aux.h	10886;"	d
+CBR_RG_DP_CK320BY2_SFT	include/ssv6200_aux.h	10888;"	d
+CBR_RG_DP_CK320BY2_SZ	include/ssv6200_aux.h	10890;"	d
+CBR_RG_DP_DCP_HI	include/ssv6200_aux.h	10954;"	d
+CBR_RG_DP_DCP_I_MSK	include/ssv6200_aux.h	10952;"	d
+CBR_RG_DP_DCP_MSK	include/ssv6200_aux.h	10951;"	d
+CBR_RG_DP_DCP_SFT	include/ssv6200_aux.h	10953;"	d
+CBR_RG_DP_DCP_SZ	include/ssv6200_aux.h	10955;"	d
+CBR_RG_DP_DCS_HI	include/ssv6200_aux.h	10959;"	d
+CBR_RG_DP_DCS_I_MSK	include/ssv6200_aux.h	10957;"	d
+CBR_RG_DP_DCS_MSK	include/ssv6200_aux.h	10956;"	d
+CBR_RG_DP_DCS_SFT	include/ssv6200_aux.h	10958;"	d
+CBR_RG_DP_DCS_SZ	include/ssv6200_aux.h	10960;"	d
+CBR_RG_DP_DR3_HI	include/ssv6200_aux.h	10949;"	d
+CBR_RG_DP_DR3_I_MSK	include/ssv6200_aux.h	10947;"	d
+CBR_RG_DP_DR3_MSK	include/ssv6200_aux.h	10946;"	d
+CBR_RG_DP_DR3_SFT	include/ssv6200_aux.h	10948;"	d
+CBR_RG_DP_DR3_SZ	include/ssv6200_aux.h	10950;"	d
+CBR_RG_DP_FBDIV_HI	include/ssv6200_aux.h	10964;"	d
+CBR_RG_DP_FBDIV_I_MSK	include/ssv6200_aux.h	10962;"	d
+CBR_RG_DP_FBDIV_MSK	include/ssv6200_aux.h	10961;"	d
+CBR_RG_DP_FBDIV_SFT	include/ssv6200_aux.h	10963;"	d
+CBR_RG_DP_FBDIV_SZ	include/ssv6200_aux.h	10965;"	d
+CBR_RG_DP_FODIV_HI	include/ssv6200_aux.h	10969;"	d
+CBR_RG_DP_FODIV_I_MSK	include/ssv6200_aux.h	10967;"	d
+CBR_RG_DP_FODIV_MSK	include/ssv6200_aux.h	10966;"	d
+CBR_RG_DP_FODIV_SFT	include/ssv6200_aux.h	10968;"	d
+CBR_RG_DP_FODIV_SZ	include/ssv6200_aux.h	10970;"	d
+CBR_RG_DP_LDO_LEVEL_HI	include/ssv6200_aux.h	9949;"	d
+CBR_RG_DP_LDO_LEVEL_I_MSK	include/ssv6200_aux.h	9947;"	d
+CBR_RG_DP_LDO_LEVEL_MSK	include/ssv6200_aux.h	9946;"	d
+CBR_RG_DP_LDO_LEVEL_SFT	include/ssv6200_aux.h	9948;"	d
+CBR_RG_DP_LDO_LEVEL_SZ	include/ssv6200_aux.h	9950;"	d
+CBR_RG_DP_OD_TEST_HI	include/ssv6200_aux.h	10899;"	d
+CBR_RG_DP_OD_TEST_I_MSK	include/ssv6200_aux.h	10897;"	d
+CBR_RG_DP_OD_TEST_MSK	include/ssv6200_aux.h	10896;"	d
+CBR_RG_DP_OD_TEST_SFT	include/ssv6200_aux.h	10898;"	d
+CBR_RG_DP_OD_TEST_SZ	include/ssv6200_aux.h	10900;"	d
+CBR_RG_DP_REFDIV_HI	include/ssv6200_aux.h	10974;"	d
+CBR_RG_DP_REFDIV_I_MSK	include/ssv6200_aux.h	10972;"	d
+CBR_RG_DP_REFDIV_MSK	include/ssv6200_aux.h	10971;"	d
+CBR_RG_DP_REFDIV_SFT	include/ssv6200_aux.h	10973;"	d
+CBR_RG_DP_REFDIV_SZ	include/ssv6200_aux.h	10975;"	d
+CBR_RG_DP_RHP_HI	include/ssv6200_aux.h	10944;"	d
+CBR_RG_DP_RHP_I_MSK	include/ssv6200_aux.h	10942;"	d
+CBR_RG_DP_RHP_MSK	include/ssv6200_aux.h	10941;"	d
+CBR_RG_DP_RHP_SFT	include/ssv6200_aux.h	10943;"	d
+CBR_RG_DP_RHP_SZ	include/ssv6200_aux.h	10945;"	d
+CBR_RG_DP_RP_HI	include/ssv6200_aux.h	10939;"	d
+CBR_RG_DP_RP_I_MSK	include/ssv6200_aux.h	10937;"	d
+CBR_RG_DP_RP_MSK	include/ssv6200_aux.h	10936;"	d
+CBR_RG_DP_RP_SFT	include/ssv6200_aux.h	10938;"	d
+CBR_RG_DP_RP_SZ	include/ssv6200_aux.h	10940;"	d
+CBR_RG_DP_VT_MON_TMR_HI	include/ssv6200_aux.h	10884;"	d
+CBR_RG_DP_VT_MON_TMR_I_MSK	include/ssv6200_aux.h	10882;"	d
+CBR_RG_DP_VT_MON_TMR_MSK	include/ssv6200_aux.h	10881;"	d
+CBR_RG_DP_VT_MON_TMR_SFT	include/ssv6200_aux.h	10883;"	d
+CBR_RG_DP_VT_MON_TMR_SZ	include/ssv6200_aux.h	10885;"	d
+CBR_RG_DP_VT_TH_HI_HI	include/ssv6200_aux.h	10874;"	d
+CBR_RG_DP_VT_TH_HI_I_MSK	include/ssv6200_aux.h	10872;"	d
+CBR_RG_DP_VT_TH_HI_MSK	include/ssv6200_aux.h	10871;"	d
+CBR_RG_DP_VT_TH_HI_SFT	include/ssv6200_aux.h	10873;"	d
+CBR_RG_DP_VT_TH_HI_SZ	include/ssv6200_aux.h	10875;"	d
+CBR_RG_DP_VT_TH_LO_HI	include/ssv6200_aux.h	10879;"	d
+CBR_RG_DP_VT_TH_LO_I_MSK	include/ssv6200_aux.h	10877;"	d
+CBR_RG_DP_VT_TH_LO_MSK	include/ssv6200_aux.h	10876;"	d
+CBR_RG_DP_VT_TH_LO_SFT	include/ssv6200_aux.h	10878;"	d
+CBR_RG_DP_VT_TH_LO_SZ	include/ssv6200_aux.h	10880;"	d
+CBR_RG_EN_ADC_HI	include/ssv6200_aux.h	9819;"	d
+CBR_RG_EN_ADC_I_MSK	include/ssv6200_aux.h	9817;"	d
+CBR_RG_EN_ADC_MSK	include/ssv6200_aux.h	9816;"	d
+CBR_RG_EN_ADC_SFT	include/ssv6200_aux.h	9818;"	d
+CBR_RG_EN_ADC_SZ	include/ssv6200_aux.h	9820;"	d
+CBR_RG_EN_DP_VT_MON_HI	include/ssv6200_aux.h	10869;"	d
+CBR_RG_EN_DP_VT_MON_I_MSK	include/ssv6200_aux.h	10867;"	d
+CBR_RG_EN_DP_VT_MON_MSK	include/ssv6200_aux.h	10866;"	d
+CBR_RG_EN_DP_VT_MON_SFT	include/ssv6200_aux.h	10868;"	d
+CBR_RG_EN_DP_VT_MON_SZ	include/ssv6200_aux.h	10870;"	d
+CBR_RG_EN_EXT_DA_HI	include/ssv6200_aux.h	11334;"	d
+CBR_RG_EN_EXT_DA_I_MSK	include/ssv6200_aux.h	11332;"	d
+CBR_RG_EN_EXT_DA_MSK	include/ssv6200_aux.h	11331;"	d
+CBR_RG_EN_EXT_DA_SFT	include/ssv6200_aux.h	11333;"	d
+CBR_RG_EN_EXT_DA_SZ	include/ssv6200_aux.h	11335;"	d
+CBR_RG_EN_IREF_RX_HI	include/ssv6200_aux.h	9909;"	d
+CBR_RG_EN_IREF_RX_I_MSK	include/ssv6200_aux.h	9907;"	d
+CBR_RG_EN_IREF_RX_MSK	include/ssv6200_aux.h	9906;"	d
+CBR_RG_EN_IREF_RX_SFT	include/ssv6200_aux.h	9908;"	d
+CBR_RG_EN_IREF_RX_SZ	include/ssv6200_aux.h	9910;"	d
+CBR_RG_EN_LDO_ABB_HI	include/ssv6200_aux.h	9889;"	d
+CBR_RG_EN_LDO_ABB_I_MSK	include/ssv6200_aux.h	9887;"	d
+CBR_RG_EN_LDO_ABB_MSK	include/ssv6200_aux.h	9886;"	d
+CBR_RG_EN_LDO_ABB_SFT	include/ssv6200_aux.h	9888;"	d
+CBR_RG_EN_LDO_ABB_SZ	include/ssv6200_aux.h	9890;"	d
+CBR_RG_EN_LDO_AFE_HI	include/ssv6200_aux.h	9894;"	d
+CBR_RG_EN_LDO_AFE_I_MSK	include/ssv6200_aux.h	9892;"	d
+CBR_RG_EN_LDO_AFE_MSK	include/ssv6200_aux.h	9891;"	d
+CBR_RG_EN_LDO_AFE_SFT	include/ssv6200_aux.h	9893;"	d
+CBR_RG_EN_LDO_AFE_SZ	include/ssv6200_aux.h	9895;"	d
+CBR_RG_EN_LDO_RX_FE_HI	include/ssv6200_aux.h	9884;"	d
+CBR_RG_EN_LDO_RX_FE_I_MSK	include/ssv6200_aux.h	9882;"	d
+CBR_RG_EN_LDO_RX_FE_MSK	include/ssv6200_aux.h	9881;"	d
+CBR_RG_EN_LDO_RX_FE_SFT	include/ssv6200_aux.h	9883;"	d
+CBR_RG_EN_LDO_RX_FE_SZ	include/ssv6200_aux.h	9885;"	d
+CBR_RG_EN_MANUAL_HI	include/ssv6200_aux.h	9724;"	d
+CBR_RG_EN_MANUAL_I_MSK	include/ssv6200_aux.h	9722;"	d
+CBR_RG_EN_MANUAL_MSK	include/ssv6200_aux.h	9721;"	d
+CBR_RG_EN_MANUAL_SFT	include/ssv6200_aux.h	9723;"	d
+CBR_RG_EN_MANUAL_SZ	include/ssv6200_aux.h	9725;"	d
+CBR_RG_EN_RCAL_HI	include/ssv6200_aux.h	11139;"	d
+CBR_RG_EN_RCAL_I_MSK	include/ssv6200_aux.h	11137;"	d
+CBR_RG_EN_RCAL_MSK	include/ssv6200_aux.h	11136;"	d
+CBR_RG_EN_RCAL_SFT	include/ssv6200_aux.h	11138;"	d
+CBR_RG_EN_RCAL_SZ	include/ssv6200_aux.h	11140;"	d
+CBR_RG_EN_RX_DIV2_HI	include/ssv6200_aux.h	9789;"	d
+CBR_RG_EN_RX_DIV2_I_MSK	include/ssv6200_aux.h	9787;"	d
+CBR_RG_EN_RX_DIV2_MSK	include/ssv6200_aux.h	9786;"	d
+CBR_RG_EN_RX_DIV2_SFT	include/ssv6200_aux.h	9788;"	d
+CBR_RG_EN_RX_DIV2_SZ	include/ssv6200_aux.h	9790;"	d
+CBR_RG_EN_RX_FILTER_HI	include/ssv6200_aux.h	9804;"	d
+CBR_RG_EN_RX_FILTER_I_MSK	include/ssv6200_aux.h	9802;"	d
+CBR_RG_EN_RX_FILTER_MSK	include/ssv6200_aux.h	9801;"	d
+CBR_RG_EN_RX_FILTER_SFT	include/ssv6200_aux.h	9803;"	d
+CBR_RG_EN_RX_FILTER_SZ	include/ssv6200_aux.h	9805;"	d
+CBR_RG_EN_RX_HPF_HI	include/ssv6200_aux.h	9809;"	d
+CBR_RG_EN_RX_HPF_I_MSK	include/ssv6200_aux.h	9807;"	d
+CBR_RG_EN_RX_HPF_MSK	include/ssv6200_aux.h	9806;"	d
+CBR_RG_EN_RX_HPF_SFT	include/ssv6200_aux.h	9808;"	d
+CBR_RG_EN_RX_HPF_SZ	include/ssv6200_aux.h	9810;"	d
+CBR_RG_EN_RX_IQCAL_HI	include/ssv6200_aux.h	9864;"	d
+CBR_RG_EN_RX_IQCAL_I_MSK	include/ssv6200_aux.h	9862;"	d
+CBR_RG_EN_RX_IQCAL_MSK	include/ssv6200_aux.h	9861;"	d
+CBR_RG_EN_RX_IQCAL_SFT	include/ssv6200_aux.h	9863;"	d
+CBR_RG_EN_RX_IQCAL_SZ	include/ssv6200_aux.h	9865;"	d
+CBR_RG_EN_RX_LNA_HI	include/ssv6200_aux.h	9779;"	d
+CBR_RG_EN_RX_LNA_I_MSK	include/ssv6200_aux.h	9777;"	d
+CBR_RG_EN_RX_LNA_MSK	include/ssv6200_aux.h	9776;"	d
+CBR_RG_EN_RX_LNA_SFT	include/ssv6200_aux.h	9778;"	d
+CBR_RG_EN_RX_LNA_SZ	include/ssv6200_aux.h	9780;"	d
+CBR_RG_EN_RX_LOBF_HI	include/ssv6200_aux.h	9844;"	d
+CBR_RG_EN_RX_LOBF_I_MSK	include/ssv6200_aux.h	9842;"	d
+CBR_RG_EN_RX_LOBF_MSK	include/ssv6200_aux.h	9841;"	d
+CBR_RG_EN_RX_LOBF_SFT	include/ssv6200_aux.h	9843;"	d
+CBR_RG_EN_RX_LOBF_SZ	include/ssv6200_aux.h	9845;"	d
+CBR_RG_EN_RX_LOBUF_HI	include/ssv6200_aux.h	9794;"	d
+CBR_RG_EN_RX_LOBUF_I_MSK	include/ssv6200_aux.h	9792;"	d
+CBR_RG_EN_RX_LOBUF_MSK	include/ssv6200_aux.h	9791;"	d
+CBR_RG_EN_RX_LOBUF_SFT	include/ssv6200_aux.h	9793;"	d
+CBR_RG_EN_RX_LOBUF_SZ	include/ssv6200_aux.h	9795;"	d
+CBR_RG_EN_RX_MIXER_HI	include/ssv6200_aux.h	9784;"	d
+CBR_RG_EN_RX_MIXER_I_MSK	include/ssv6200_aux.h	9782;"	d
+CBR_RG_EN_RX_MIXER_MSK	include/ssv6200_aux.h	9781;"	d
+CBR_RG_EN_RX_MIXER_SFT	include/ssv6200_aux.h	9783;"	d
+CBR_RG_EN_RX_MIXER_SZ	include/ssv6200_aux.h	9785;"	d
+CBR_RG_EN_RX_PADSW_HI	include/ssv6200_aux.h	9969;"	d
+CBR_RG_EN_RX_PADSW_I_MSK	include/ssv6200_aux.h	9967;"	d
+CBR_RG_EN_RX_PADSW_MSK	include/ssv6200_aux.h	9966;"	d
+CBR_RG_EN_RX_PADSW_SFT	include/ssv6200_aux.h	9968;"	d
+CBR_RG_EN_RX_PADSW_SZ	include/ssv6200_aux.h	9970;"	d
+CBR_RG_EN_RX_RSSI_HI	include/ssv6200_aux.h	9814;"	d
+CBR_RG_EN_RX_RSSI_I_MSK	include/ssv6200_aux.h	9812;"	d
+CBR_RG_EN_RX_RSSI_MSK	include/ssv6200_aux.h	9811;"	d
+CBR_RG_EN_RX_RSSI_SFT	include/ssv6200_aux.h	9813;"	d
+CBR_RG_EN_RX_RSSI_SZ	include/ssv6200_aux.h	9815;"	d
+CBR_RG_EN_RX_RSSI_TESTNODE_HI	include/ssv6200_aux.h	10099;"	d
+CBR_RG_EN_RX_RSSI_TESTNODE_I_MSK	include/ssv6200_aux.h	10097;"	d
+CBR_RG_EN_RX_RSSI_TESTNODE_MSK	include/ssv6200_aux.h	10096;"	d
+CBR_RG_EN_RX_RSSI_TESTNODE_SFT	include/ssv6200_aux.h	10098;"	d
+CBR_RG_EN_RX_RSSI_TESTNODE_SZ	include/ssv6200_aux.h	10100;"	d
+CBR_RG_EN_RX_TESTNODE_HI	include/ssv6200_aux.h	9974;"	d
+CBR_RG_EN_RX_TESTNODE_I_MSK	include/ssv6200_aux.h	9972;"	d
+CBR_RG_EN_RX_TESTNODE_MSK	include/ssv6200_aux.h	9971;"	d
+CBR_RG_EN_RX_TESTNODE_SFT	include/ssv6200_aux.h	9973;"	d
+CBR_RG_EN_RX_TESTNODE_SZ	include/ssv6200_aux.h	9975;"	d
+CBR_RG_EN_RX_TZ_HI	include/ssv6200_aux.h	9799;"	d
+CBR_RG_EN_RX_TZ_I_MSK	include/ssv6200_aux.h	9797;"	d
+CBR_RG_EN_RX_TZ_MSK	include/ssv6200_aux.h	9796;"	d
+CBR_RG_EN_RX_TZ_SFT	include/ssv6200_aux.h	9798;"	d
+CBR_RG_EN_RX_TZ_SZ	include/ssv6200_aux.h	9800;"	d
+CBR_RG_EN_SX_CHPLDO_HI	include/ssv6200_aux.h	9899;"	d
+CBR_RG_EN_SX_CHPLDO_I_MSK	include/ssv6200_aux.h	9897;"	d
+CBR_RG_EN_SX_CHPLDO_MSK	include/ssv6200_aux.h	9896;"	d
+CBR_RG_EN_SX_CHPLDO_SFT	include/ssv6200_aux.h	9898;"	d
+CBR_RG_EN_SX_CHPLDO_SZ	include/ssv6200_aux.h	9900;"	d
+CBR_RG_EN_SX_CHP_HI	include/ssv6200_aux.h	10504;"	d
+CBR_RG_EN_SX_CHP_I_MSK	include/ssv6200_aux.h	10502;"	d
+CBR_RG_EN_SX_CHP_MSK	include/ssv6200_aux.h	10501;"	d
+CBR_RG_EN_SX_CHP_SFT	include/ssv6200_aux.h	10503;"	d
+CBR_RG_EN_SX_CHP_SZ	include/ssv6200_aux.h	10505;"	d
+CBR_RG_EN_SX_CH_HI	include/ssv6200_aux.h	10499;"	d
+CBR_RG_EN_SX_CH_I_MSK	include/ssv6200_aux.h	10497;"	d
+CBR_RG_EN_SX_CH_MSK	include/ssv6200_aux.h	10496;"	d
+CBR_RG_EN_SX_CH_SFT	include/ssv6200_aux.h	10498;"	d
+CBR_RG_EN_SX_CH_SZ	include/ssv6200_aux.h	10500;"	d
+CBR_RG_EN_SX_DELCAL_HI	include/ssv6200_aux.h	10539;"	d
+CBR_RG_EN_SX_DELCAL_I_MSK	include/ssv6200_aux.h	10537;"	d
+CBR_RG_EN_SX_DELCAL_MSK	include/ssv6200_aux.h	10536;"	d
+CBR_RG_EN_SX_DELCAL_SFT	include/ssv6200_aux.h	10538;"	d
+CBR_RG_EN_SX_DELCAL_SZ	include/ssv6200_aux.h	10540;"	d
+CBR_RG_EN_SX_DITHER_HI	include/ssv6200_aux.h	10534;"	d
+CBR_RG_EN_SX_DITHER_I_MSK	include/ssv6200_aux.h	10532;"	d
+CBR_RG_EN_SX_DITHER_MSK	include/ssv6200_aux.h	10531;"	d
+CBR_RG_EN_SX_DITHER_SFT	include/ssv6200_aux.h	10533;"	d
+CBR_RG_EN_SX_DITHER_SZ	include/ssv6200_aux.h	10535;"	d
+CBR_RG_EN_SX_DIVCK_HI	include/ssv6200_aux.h	10509;"	d
+CBR_RG_EN_SX_DIVCK_I_MSK	include/ssv6200_aux.h	10507;"	d
+CBR_RG_EN_SX_DIVCK_MSK	include/ssv6200_aux.h	10506;"	d
+CBR_RG_EN_SX_DIVCK_SFT	include/ssv6200_aux.h	10508;"	d
+CBR_RG_EN_SX_DIVCK_SZ	include/ssv6200_aux.h	10510;"	d
+CBR_RG_EN_SX_DIV_HI	include/ssv6200_aux.h	10559;"	d
+CBR_RG_EN_SX_DIV_I_MSK	include/ssv6200_aux.h	10557;"	d
+CBR_RG_EN_SX_DIV_MSK	include/ssv6200_aux.h	10556;"	d
+CBR_RG_EN_SX_DIV_SFT	include/ssv6200_aux.h	10558;"	d
+CBR_RG_EN_SX_DIV_SZ	include/ssv6200_aux.h	10560;"	d
+CBR_RG_EN_SX_HI	include/ssv6200_aux.h	9774;"	d
+CBR_RG_EN_SX_I_MSK	include/ssv6200_aux.h	9772;"	d
+CBR_RG_EN_SX_LCK_HI	include/ssv6200_aux.h	10529;"	d
+CBR_RG_EN_SX_LCK_I_MSK	include/ssv6200_aux.h	10527;"	d
+CBR_RG_EN_SX_LCK_MSK	include/ssv6200_aux.h	10526;"	d
+CBR_RG_EN_SX_LCK_SFT	include/ssv6200_aux.h	10528;"	d
+CBR_RG_EN_SX_LCK_SZ	include/ssv6200_aux.h	10530;"	d
+CBR_RG_EN_SX_LOBFLDO_HI	include/ssv6200_aux.h	9904;"	d
+CBR_RG_EN_SX_LOBFLDO_I_MSK	include/ssv6200_aux.h	9902;"	d
+CBR_RG_EN_SX_LOBFLDO_MSK	include/ssv6200_aux.h	9901;"	d
+CBR_RG_EN_SX_LOBFLDO_SFT	include/ssv6200_aux.h	9903;"	d
+CBR_RG_EN_SX_LOBFLDO_SZ	include/ssv6200_aux.h	9905;"	d
+CBR_RG_EN_SX_LPF_HI	include/ssv6200_aux.h	10564;"	d
+CBR_RG_EN_SX_LPF_I_MSK	include/ssv6200_aux.h	10562;"	d
+CBR_RG_EN_SX_LPF_MSK	include/ssv6200_aux.h	10561;"	d
+CBR_RG_EN_SX_LPF_SFT	include/ssv6200_aux.h	10563;"	d
+CBR_RG_EN_SX_LPF_SZ	include/ssv6200_aux.h	10565;"	d
+CBR_RG_EN_SX_MOD_HI	include/ssv6200_aux.h	10524;"	d
+CBR_RG_EN_SX_MOD_I_MSK	include/ssv6200_aux.h	10522;"	d
+CBR_RG_EN_SX_MOD_MSK	include/ssv6200_aux.h	10521;"	d
+CBR_RG_EN_SX_MOD_SFT	include/ssv6200_aux.h	10523;"	d
+CBR_RG_EN_SX_MOD_SZ	include/ssv6200_aux.h	10525;"	d
+CBR_RG_EN_SX_MSK	include/ssv6200_aux.h	9771;"	d
+CBR_RG_EN_SX_PC_BYPASS_HI	include/ssv6200_aux.h	10544;"	d
+CBR_RG_EN_SX_PC_BYPASS_I_MSK	include/ssv6200_aux.h	10542;"	d
+CBR_RG_EN_SX_PC_BYPASS_MSK	include/ssv6200_aux.h	10541;"	d
+CBR_RG_EN_SX_PC_BYPASS_SFT	include/ssv6200_aux.h	10543;"	d
+CBR_RG_EN_SX_PC_BYPASS_SZ	include/ssv6200_aux.h	10545;"	d
+CBR_RG_EN_SX_R3_HI	include/ssv6200_aux.h	10494;"	d
+CBR_RG_EN_SX_R3_I_MSK	include/ssv6200_aux.h	10492;"	d
+CBR_RG_EN_SX_R3_MSK	include/ssv6200_aux.h	10491;"	d
+CBR_RG_EN_SX_R3_SFT	include/ssv6200_aux.h	10493;"	d
+CBR_RG_EN_SX_R3_SZ	include/ssv6200_aux.h	10495;"	d
+CBR_RG_EN_SX_SFT	include/ssv6200_aux.h	9773;"	d
+CBR_RG_EN_SX_SZ	include/ssv6200_aux.h	9775;"	d
+CBR_RG_EN_SX_VCOBF_HI	include/ssv6200_aux.h	10514;"	d
+CBR_RG_EN_SX_VCOBF_I_MSK	include/ssv6200_aux.h	10512;"	d
+CBR_RG_EN_SX_VCOBF_MSK	include/ssv6200_aux.h	10511;"	d
+CBR_RG_EN_SX_VCOBF_SFT	include/ssv6200_aux.h	10513;"	d
+CBR_RG_EN_SX_VCOBF_SZ	include/ssv6200_aux.h	10515;"	d
+CBR_RG_EN_SX_VCO_HI	include/ssv6200_aux.h	10519;"	d
+CBR_RG_EN_SX_VCO_I_MSK	include/ssv6200_aux.h	10517;"	d
+CBR_RG_EN_SX_VCO_MSK	include/ssv6200_aux.h	10516;"	d
+CBR_RG_EN_SX_VCO_SFT	include/ssv6200_aux.h	10518;"	d
+CBR_RG_EN_SX_VCO_SZ	include/ssv6200_aux.h	10520;"	d
+CBR_RG_EN_SX_VT_MON_DG_HI	include/ssv6200_aux.h	10554;"	d
+CBR_RG_EN_SX_VT_MON_DG_I_MSK	include/ssv6200_aux.h	10552;"	d
+CBR_RG_EN_SX_VT_MON_DG_MSK	include/ssv6200_aux.h	10551;"	d
+CBR_RG_EN_SX_VT_MON_DG_SFT	include/ssv6200_aux.h	10553;"	d
+CBR_RG_EN_SX_VT_MON_DG_SZ	include/ssv6200_aux.h	10555;"	d
+CBR_RG_EN_SX_VT_MON_HI	include/ssv6200_aux.h	10549;"	d
+CBR_RG_EN_SX_VT_MON_I_MSK	include/ssv6200_aux.h	10547;"	d
+CBR_RG_EN_SX_VT_MON_MSK	include/ssv6200_aux.h	10546;"	d
+CBR_RG_EN_SX_VT_MON_SFT	include/ssv6200_aux.h	10548;"	d
+CBR_RG_EN_SX_VT_MON_SZ	include/ssv6200_aux.h	10550;"	d
+CBR_RG_EN_TX_DAC_CAL_HI	include/ssv6200_aux.h	9869;"	d
+CBR_RG_EN_TX_DAC_CAL_I_MSK	include/ssv6200_aux.h	9867;"	d
+CBR_RG_EN_TX_DAC_CAL_MSK	include/ssv6200_aux.h	9866;"	d
+CBR_RG_EN_TX_DAC_CAL_SFT	include/ssv6200_aux.h	9868;"	d
+CBR_RG_EN_TX_DAC_CAL_SZ	include/ssv6200_aux.h	9870;"	d
+CBR_RG_EN_TX_DAC_OUT_HI	include/ssv6200_aux.h	9879;"	d
+CBR_RG_EN_TX_DAC_OUT_I_MSK	include/ssv6200_aux.h	9877;"	d
+CBR_RG_EN_TX_DAC_OUT_MSK	include/ssv6200_aux.h	9876;"	d
+CBR_RG_EN_TX_DAC_OUT_SFT	include/ssv6200_aux.h	9878;"	d
+CBR_RG_EN_TX_DAC_OUT_SZ	include/ssv6200_aux.h	9880;"	d
+CBR_RG_EN_TX_DIV2_BUF_HI	include/ssv6200_aux.h	9834;"	d
+CBR_RG_EN_TX_DIV2_BUF_I_MSK	include/ssv6200_aux.h	9832;"	d
+CBR_RG_EN_TX_DIV2_BUF_MSK	include/ssv6200_aux.h	9831;"	d
+CBR_RG_EN_TX_DIV2_BUF_SFT	include/ssv6200_aux.h	9833;"	d
+CBR_RG_EN_TX_DIV2_BUF_SZ	include/ssv6200_aux.h	9835;"	d
+CBR_RG_EN_TX_DIV2_HI	include/ssv6200_aux.h	9829;"	d
+CBR_RG_EN_TX_DIV2_I_MSK	include/ssv6200_aux.h	9827;"	d
+CBR_RG_EN_TX_DIV2_MSK	include/ssv6200_aux.h	9826;"	d
+CBR_RG_EN_TX_DIV2_SFT	include/ssv6200_aux.h	9828;"	d
+CBR_RG_EN_TX_DIV2_SZ	include/ssv6200_aux.h	9830;"	d
+CBR_RG_EN_TX_DPD_HI	include/ssv6200_aux.h	9854;"	d
+CBR_RG_EN_TX_DPD_I_MSK	include/ssv6200_aux.h	9852;"	d
+CBR_RG_EN_TX_DPD_MSK	include/ssv6200_aux.h	9851;"	d
+CBR_RG_EN_TX_DPD_SFT	include/ssv6200_aux.h	9853;"	d
+CBR_RG_EN_TX_DPD_SZ	include/ssv6200_aux.h	9855;"	d
+CBR_RG_EN_TX_LOBF_HI	include/ssv6200_aux.h	9839;"	d
+CBR_RG_EN_TX_LOBF_I_MSK	include/ssv6200_aux.h	9837;"	d
+CBR_RG_EN_TX_LOBF_MSK	include/ssv6200_aux.h	9836;"	d
+CBR_RG_EN_TX_LOBF_SFT	include/ssv6200_aux.h	9838;"	d
+CBR_RG_EN_TX_LOBF_SZ	include/ssv6200_aux.h	9840;"	d
+CBR_RG_EN_TX_MOD_HI	include/ssv6200_aux.h	9824;"	d
+CBR_RG_EN_TX_MOD_I_MSK	include/ssv6200_aux.h	9822;"	d
+CBR_RG_EN_TX_MOD_MSK	include/ssv6200_aux.h	9821;"	d
+CBR_RG_EN_TX_MOD_SFT	include/ssv6200_aux.h	9823;"	d
+CBR_RG_EN_TX_MOD_SZ	include/ssv6200_aux.h	9825;"	d
+CBR_RG_EN_TX_SELF_MIXER_HI	include/ssv6200_aux.h	9874;"	d
+CBR_RG_EN_TX_SELF_MIXER_I_MSK	include/ssv6200_aux.h	9872;"	d
+CBR_RG_EN_TX_SELF_MIXER_MSK	include/ssv6200_aux.h	9871;"	d
+CBR_RG_EN_TX_SELF_MIXER_SFT	include/ssv6200_aux.h	9873;"	d
+CBR_RG_EN_TX_SELF_MIXER_SZ	include/ssv6200_aux.h	9875;"	d
+CBR_RG_EN_TX_TRSW_HI	include/ssv6200_aux.h	9769;"	d
+CBR_RG_EN_TX_TRSW_I_MSK	include/ssv6200_aux.h	9767;"	d
+CBR_RG_EN_TX_TRSW_MSK	include/ssv6200_aux.h	9766;"	d
+CBR_RG_EN_TX_TRSW_SFT	include/ssv6200_aux.h	9768;"	d
+CBR_RG_EN_TX_TRSW_SZ	include/ssv6200_aux.h	9770;"	d
+CBR_RG_EN_TX_TSSI_HI	include/ssv6200_aux.h	9859;"	d
+CBR_RG_EN_TX_TSSI_I_MSK	include/ssv6200_aux.h	9857;"	d
+CBR_RG_EN_TX_TSSI_MSK	include/ssv6200_aux.h	9856;"	d
+CBR_RG_EN_TX_TSSI_SFT	include/ssv6200_aux.h	9858;"	d
+CBR_RG_EN_TX_TSSI_SZ	include/ssv6200_aux.h	9860;"	d
+CBR_RG_HPF1_FAST_SET_X_HI	include/ssv6200_aux.h	10339;"	d
+CBR_RG_HPF1_FAST_SET_X_I_MSK	include/ssv6200_aux.h	10337;"	d
+CBR_RG_HPF1_FAST_SET_X_MSK	include/ssv6200_aux.h	10336;"	d
+CBR_RG_HPF1_FAST_SET_X_SFT	include/ssv6200_aux.h	10338;"	d
+CBR_RG_HPF1_FAST_SET_X_SZ	include/ssv6200_aux.h	10340;"	d
+CBR_RG_HPF1_FAST_SET_Y_HI	include/ssv6200_aux.h	10344;"	d
+CBR_RG_HPF1_FAST_SET_Y_I_MSK	include/ssv6200_aux.h	10342;"	d
+CBR_RG_HPF1_FAST_SET_Y_MSK	include/ssv6200_aux.h	10341;"	d
+CBR_RG_HPF1_FAST_SET_Y_SFT	include/ssv6200_aux.h	10343;"	d
+CBR_RG_HPF1_FAST_SET_Y_SZ	include/ssv6200_aux.h	10345;"	d
+CBR_RG_HPF1_FAST_SET_Z_HI	include/ssv6200_aux.h	10349;"	d
+CBR_RG_HPF1_FAST_SET_Z_I_MSK	include/ssv6200_aux.h	10347;"	d
+CBR_RG_HPF1_FAST_SET_Z_MSK	include/ssv6200_aux.h	10346;"	d
+CBR_RG_HPF1_FAST_SET_Z_SFT	include/ssv6200_aux.h	10348;"	d
+CBR_RG_HPF1_FAST_SET_Z_SZ	include/ssv6200_aux.h	10350;"	d
+CBR_RG_HPF_T1A_HI	include/ssv6200_aux.h	10354;"	d
+CBR_RG_HPF_T1A_I_MSK	include/ssv6200_aux.h	10352;"	d
+CBR_RG_HPF_T1A_MSK	include/ssv6200_aux.h	10351;"	d
+CBR_RG_HPF_T1A_SFT	include/ssv6200_aux.h	10353;"	d
+CBR_RG_HPF_T1A_SZ	include/ssv6200_aux.h	10355;"	d
+CBR_RG_HPF_T1B_HI	include/ssv6200_aux.h	10359;"	d
+CBR_RG_HPF_T1B_I_MSK	include/ssv6200_aux.h	10357;"	d
+CBR_RG_HPF_T1B_MSK	include/ssv6200_aux.h	10356;"	d
+CBR_RG_HPF_T1B_SFT	include/ssv6200_aux.h	10358;"	d
+CBR_RG_HPF_T1B_SZ	include/ssv6200_aux.h	10360;"	d
+CBR_RG_HPF_T1C_HI	include/ssv6200_aux.h	10364;"	d
+CBR_RG_HPF_T1C_I_MSK	include/ssv6200_aux.h	10362;"	d
+CBR_RG_HPF_T1C_MSK	include/ssv6200_aux.h	10361;"	d
+CBR_RG_HPF_T1C_SFT	include/ssv6200_aux.h	10363;"	d
+CBR_RG_HPF_T1C_SZ	include/ssv6200_aux.h	10365;"	d
+CBR_RG_IDACAI_PGAG0_HI	include/ssv6200_aux.h	11129;"	d
+CBR_RG_IDACAI_PGAG0_I_MSK	include/ssv6200_aux.h	11127;"	d
+CBR_RG_IDACAI_PGAG0_MSK	include/ssv6200_aux.h	11126;"	d
+CBR_RG_IDACAI_PGAG0_SFT	include/ssv6200_aux.h	11128;"	d
+CBR_RG_IDACAI_PGAG0_SZ	include/ssv6200_aux.h	11130;"	d
+CBR_RG_IDACAI_PGAG10_HI	include/ssv6200_aux.h	11029;"	d
+CBR_RG_IDACAI_PGAG10_I_MSK	include/ssv6200_aux.h	11027;"	d
+CBR_RG_IDACAI_PGAG10_MSK	include/ssv6200_aux.h	11026;"	d
+CBR_RG_IDACAI_PGAG10_SFT	include/ssv6200_aux.h	11028;"	d
+CBR_RG_IDACAI_PGAG10_SZ	include/ssv6200_aux.h	11030;"	d
+CBR_RG_IDACAI_PGAG11_HI	include/ssv6200_aux.h	11019;"	d
+CBR_RG_IDACAI_PGAG11_I_MSK	include/ssv6200_aux.h	11017;"	d
+CBR_RG_IDACAI_PGAG11_MSK	include/ssv6200_aux.h	11016;"	d
+CBR_RG_IDACAI_PGAG11_SFT	include/ssv6200_aux.h	11018;"	d
+CBR_RG_IDACAI_PGAG11_SZ	include/ssv6200_aux.h	11020;"	d
+CBR_RG_IDACAI_PGAG12_HI	include/ssv6200_aux.h	11009;"	d
+CBR_RG_IDACAI_PGAG12_I_MSK	include/ssv6200_aux.h	11007;"	d
+CBR_RG_IDACAI_PGAG12_MSK	include/ssv6200_aux.h	11006;"	d
+CBR_RG_IDACAI_PGAG12_SFT	include/ssv6200_aux.h	11008;"	d
+CBR_RG_IDACAI_PGAG12_SZ	include/ssv6200_aux.h	11010;"	d
+CBR_RG_IDACAI_PGAG13_HI	include/ssv6200_aux.h	10999;"	d
+CBR_RG_IDACAI_PGAG13_I_MSK	include/ssv6200_aux.h	10997;"	d
+CBR_RG_IDACAI_PGAG13_MSK	include/ssv6200_aux.h	10996;"	d
+CBR_RG_IDACAI_PGAG13_SFT	include/ssv6200_aux.h	10998;"	d
+CBR_RG_IDACAI_PGAG13_SZ	include/ssv6200_aux.h	11000;"	d
+CBR_RG_IDACAI_PGAG14_HI	include/ssv6200_aux.h	10989;"	d
+CBR_RG_IDACAI_PGAG14_I_MSK	include/ssv6200_aux.h	10987;"	d
+CBR_RG_IDACAI_PGAG14_MSK	include/ssv6200_aux.h	10986;"	d
+CBR_RG_IDACAI_PGAG14_SFT	include/ssv6200_aux.h	10988;"	d
+CBR_RG_IDACAI_PGAG14_SZ	include/ssv6200_aux.h	10990;"	d
+CBR_RG_IDACAI_PGAG15_HI	include/ssv6200_aux.h	10979;"	d
+CBR_RG_IDACAI_PGAG15_I_MSK	include/ssv6200_aux.h	10977;"	d
+CBR_RG_IDACAI_PGAG15_MSK	include/ssv6200_aux.h	10976;"	d
+CBR_RG_IDACAI_PGAG15_SFT	include/ssv6200_aux.h	10978;"	d
+CBR_RG_IDACAI_PGAG15_SZ	include/ssv6200_aux.h	10980;"	d
+CBR_RG_IDACAI_PGAG1_HI	include/ssv6200_aux.h	11119;"	d
+CBR_RG_IDACAI_PGAG1_I_MSK	include/ssv6200_aux.h	11117;"	d
+CBR_RG_IDACAI_PGAG1_MSK	include/ssv6200_aux.h	11116;"	d
+CBR_RG_IDACAI_PGAG1_SFT	include/ssv6200_aux.h	11118;"	d
+CBR_RG_IDACAI_PGAG1_SZ	include/ssv6200_aux.h	11120;"	d
+CBR_RG_IDACAI_PGAG2_HI	include/ssv6200_aux.h	11109;"	d
+CBR_RG_IDACAI_PGAG2_I_MSK	include/ssv6200_aux.h	11107;"	d
+CBR_RG_IDACAI_PGAG2_MSK	include/ssv6200_aux.h	11106;"	d
+CBR_RG_IDACAI_PGAG2_SFT	include/ssv6200_aux.h	11108;"	d
+CBR_RG_IDACAI_PGAG2_SZ	include/ssv6200_aux.h	11110;"	d
+CBR_RG_IDACAI_PGAG3_HI	include/ssv6200_aux.h	11099;"	d
+CBR_RG_IDACAI_PGAG3_I_MSK	include/ssv6200_aux.h	11097;"	d
+CBR_RG_IDACAI_PGAG3_MSK	include/ssv6200_aux.h	11096;"	d
+CBR_RG_IDACAI_PGAG3_SFT	include/ssv6200_aux.h	11098;"	d
+CBR_RG_IDACAI_PGAG3_SZ	include/ssv6200_aux.h	11100;"	d
+CBR_RG_IDACAI_PGAG4_HI	include/ssv6200_aux.h	11089;"	d
+CBR_RG_IDACAI_PGAG4_I_MSK	include/ssv6200_aux.h	11087;"	d
+CBR_RG_IDACAI_PGAG4_MSK	include/ssv6200_aux.h	11086;"	d
+CBR_RG_IDACAI_PGAG4_SFT	include/ssv6200_aux.h	11088;"	d
+CBR_RG_IDACAI_PGAG4_SZ	include/ssv6200_aux.h	11090;"	d
+CBR_RG_IDACAI_PGAG5_HI	include/ssv6200_aux.h	11079;"	d
+CBR_RG_IDACAI_PGAG5_I_MSK	include/ssv6200_aux.h	11077;"	d
+CBR_RG_IDACAI_PGAG5_MSK	include/ssv6200_aux.h	11076;"	d
+CBR_RG_IDACAI_PGAG5_SFT	include/ssv6200_aux.h	11078;"	d
+CBR_RG_IDACAI_PGAG5_SZ	include/ssv6200_aux.h	11080;"	d
+CBR_RG_IDACAI_PGAG6_HI	include/ssv6200_aux.h	11069;"	d
+CBR_RG_IDACAI_PGAG6_I_MSK	include/ssv6200_aux.h	11067;"	d
+CBR_RG_IDACAI_PGAG6_MSK	include/ssv6200_aux.h	11066;"	d
+CBR_RG_IDACAI_PGAG6_SFT	include/ssv6200_aux.h	11068;"	d
+CBR_RG_IDACAI_PGAG6_SZ	include/ssv6200_aux.h	11070;"	d
+CBR_RG_IDACAI_PGAG7_HI	include/ssv6200_aux.h	11059;"	d
+CBR_RG_IDACAI_PGAG7_I_MSK	include/ssv6200_aux.h	11057;"	d
+CBR_RG_IDACAI_PGAG7_MSK	include/ssv6200_aux.h	11056;"	d
+CBR_RG_IDACAI_PGAG7_SFT	include/ssv6200_aux.h	11058;"	d
+CBR_RG_IDACAI_PGAG7_SZ	include/ssv6200_aux.h	11060;"	d
+CBR_RG_IDACAI_PGAG8_HI	include/ssv6200_aux.h	11049;"	d
+CBR_RG_IDACAI_PGAG8_I_MSK	include/ssv6200_aux.h	11047;"	d
+CBR_RG_IDACAI_PGAG8_MSK	include/ssv6200_aux.h	11046;"	d
+CBR_RG_IDACAI_PGAG8_SFT	include/ssv6200_aux.h	11048;"	d
+CBR_RG_IDACAI_PGAG8_SZ	include/ssv6200_aux.h	11050;"	d
+CBR_RG_IDACAI_PGAG9_HI	include/ssv6200_aux.h	11039;"	d
+CBR_RG_IDACAI_PGAG9_I_MSK	include/ssv6200_aux.h	11037;"	d
+CBR_RG_IDACAI_PGAG9_MSK	include/ssv6200_aux.h	11036;"	d
+CBR_RG_IDACAI_PGAG9_SFT	include/ssv6200_aux.h	11038;"	d
+CBR_RG_IDACAI_PGAG9_SZ	include/ssv6200_aux.h	11040;"	d
+CBR_RG_IDACAQ_PGAG0_HI	include/ssv6200_aux.h	11134;"	d
+CBR_RG_IDACAQ_PGAG0_I_MSK	include/ssv6200_aux.h	11132;"	d
+CBR_RG_IDACAQ_PGAG0_MSK	include/ssv6200_aux.h	11131;"	d
+CBR_RG_IDACAQ_PGAG0_SFT	include/ssv6200_aux.h	11133;"	d
+CBR_RG_IDACAQ_PGAG0_SZ	include/ssv6200_aux.h	11135;"	d
+CBR_RG_IDACAQ_PGAG10_HI	include/ssv6200_aux.h	11034;"	d
+CBR_RG_IDACAQ_PGAG10_I_MSK	include/ssv6200_aux.h	11032;"	d
+CBR_RG_IDACAQ_PGAG10_MSK	include/ssv6200_aux.h	11031;"	d
+CBR_RG_IDACAQ_PGAG10_SFT	include/ssv6200_aux.h	11033;"	d
+CBR_RG_IDACAQ_PGAG10_SZ	include/ssv6200_aux.h	11035;"	d
+CBR_RG_IDACAQ_PGAG11_HI	include/ssv6200_aux.h	11024;"	d
+CBR_RG_IDACAQ_PGAG11_I_MSK	include/ssv6200_aux.h	11022;"	d
+CBR_RG_IDACAQ_PGAG11_MSK	include/ssv6200_aux.h	11021;"	d
+CBR_RG_IDACAQ_PGAG11_SFT	include/ssv6200_aux.h	11023;"	d
+CBR_RG_IDACAQ_PGAG11_SZ	include/ssv6200_aux.h	11025;"	d
+CBR_RG_IDACAQ_PGAG12_HI	include/ssv6200_aux.h	11014;"	d
+CBR_RG_IDACAQ_PGAG12_I_MSK	include/ssv6200_aux.h	11012;"	d
+CBR_RG_IDACAQ_PGAG12_MSK	include/ssv6200_aux.h	11011;"	d
+CBR_RG_IDACAQ_PGAG12_SFT	include/ssv6200_aux.h	11013;"	d
+CBR_RG_IDACAQ_PGAG12_SZ	include/ssv6200_aux.h	11015;"	d
+CBR_RG_IDACAQ_PGAG13_HI	include/ssv6200_aux.h	11004;"	d
+CBR_RG_IDACAQ_PGAG13_I_MSK	include/ssv6200_aux.h	11002;"	d
+CBR_RG_IDACAQ_PGAG13_MSK	include/ssv6200_aux.h	11001;"	d
+CBR_RG_IDACAQ_PGAG13_SFT	include/ssv6200_aux.h	11003;"	d
+CBR_RG_IDACAQ_PGAG13_SZ	include/ssv6200_aux.h	11005;"	d
+CBR_RG_IDACAQ_PGAG14_HI	include/ssv6200_aux.h	10994;"	d
+CBR_RG_IDACAQ_PGAG14_I_MSK	include/ssv6200_aux.h	10992;"	d
+CBR_RG_IDACAQ_PGAG14_MSK	include/ssv6200_aux.h	10991;"	d
+CBR_RG_IDACAQ_PGAG14_SFT	include/ssv6200_aux.h	10993;"	d
+CBR_RG_IDACAQ_PGAG14_SZ	include/ssv6200_aux.h	10995;"	d
+CBR_RG_IDACAQ_PGAG15_HI	include/ssv6200_aux.h	10984;"	d
+CBR_RG_IDACAQ_PGAG15_I_MSK	include/ssv6200_aux.h	10982;"	d
+CBR_RG_IDACAQ_PGAG15_MSK	include/ssv6200_aux.h	10981;"	d
+CBR_RG_IDACAQ_PGAG15_SFT	include/ssv6200_aux.h	10983;"	d
+CBR_RG_IDACAQ_PGAG15_SZ	include/ssv6200_aux.h	10985;"	d
+CBR_RG_IDACAQ_PGAG1_HI	include/ssv6200_aux.h	11124;"	d
+CBR_RG_IDACAQ_PGAG1_I_MSK	include/ssv6200_aux.h	11122;"	d
+CBR_RG_IDACAQ_PGAG1_MSK	include/ssv6200_aux.h	11121;"	d
+CBR_RG_IDACAQ_PGAG1_SFT	include/ssv6200_aux.h	11123;"	d
+CBR_RG_IDACAQ_PGAG1_SZ	include/ssv6200_aux.h	11125;"	d
+CBR_RG_IDACAQ_PGAG2_HI	include/ssv6200_aux.h	11114;"	d
+CBR_RG_IDACAQ_PGAG2_I_MSK	include/ssv6200_aux.h	11112;"	d
+CBR_RG_IDACAQ_PGAG2_MSK	include/ssv6200_aux.h	11111;"	d
+CBR_RG_IDACAQ_PGAG2_SFT	include/ssv6200_aux.h	11113;"	d
+CBR_RG_IDACAQ_PGAG2_SZ	include/ssv6200_aux.h	11115;"	d
+CBR_RG_IDACAQ_PGAG3_HI	include/ssv6200_aux.h	11104;"	d
+CBR_RG_IDACAQ_PGAG3_I_MSK	include/ssv6200_aux.h	11102;"	d
+CBR_RG_IDACAQ_PGAG3_MSK	include/ssv6200_aux.h	11101;"	d
+CBR_RG_IDACAQ_PGAG3_SFT	include/ssv6200_aux.h	11103;"	d
+CBR_RG_IDACAQ_PGAG3_SZ	include/ssv6200_aux.h	11105;"	d
+CBR_RG_IDACAQ_PGAG4_HI	include/ssv6200_aux.h	11094;"	d
+CBR_RG_IDACAQ_PGAG4_I_MSK	include/ssv6200_aux.h	11092;"	d
+CBR_RG_IDACAQ_PGAG4_MSK	include/ssv6200_aux.h	11091;"	d
+CBR_RG_IDACAQ_PGAG4_SFT	include/ssv6200_aux.h	11093;"	d
+CBR_RG_IDACAQ_PGAG4_SZ	include/ssv6200_aux.h	11095;"	d
+CBR_RG_IDACAQ_PGAG5_HI	include/ssv6200_aux.h	11084;"	d
+CBR_RG_IDACAQ_PGAG5_I_MSK	include/ssv6200_aux.h	11082;"	d
+CBR_RG_IDACAQ_PGAG5_MSK	include/ssv6200_aux.h	11081;"	d
+CBR_RG_IDACAQ_PGAG5_SFT	include/ssv6200_aux.h	11083;"	d
+CBR_RG_IDACAQ_PGAG5_SZ	include/ssv6200_aux.h	11085;"	d
+CBR_RG_IDACAQ_PGAG6_HI	include/ssv6200_aux.h	11074;"	d
+CBR_RG_IDACAQ_PGAG6_I_MSK	include/ssv6200_aux.h	11072;"	d
+CBR_RG_IDACAQ_PGAG6_MSK	include/ssv6200_aux.h	11071;"	d
+CBR_RG_IDACAQ_PGAG6_SFT	include/ssv6200_aux.h	11073;"	d
+CBR_RG_IDACAQ_PGAG6_SZ	include/ssv6200_aux.h	11075;"	d
+CBR_RG_IDACAQ_PGAG7_HI	include/ssv6200_aux.h	11064;"	d
+CBR_RG_IDACAQ_PGAG7_I_MSK	include/ssv6200_aux.h	11062;"	d
+CBR_RG_IDACAQ_PGAG7_MSK	include/ssv6200_aux.h	11061;"	d
+CBR_RG_IDACAQ_PGAG7_SFT	include/ssv6200_aux.h	11063;"	d
+CBR_RG_IDACAQ_PGAG7_SZ	include/ssv6200_aux.h	11065;"	d
+CBR_RG_IDACAQ_PGAG8_HI	include/ssv6200_aux.h	11054;"	d
+CBR_RG_IDACAQ_PGAG8_I_MSK	include/ssv6200_aux.h	11052;"	d
+CBR_RG_IDACAQ_PGAG8_MSK	include/ssv6200_aux.h	11051;"	d
+CBR_RG_IDACAQ_PGAG8_SFT	include/ssv6200_aux.h	11053;"	d
+CBR_RG_IDACAQ_PGAG8_SZ	include/ssv6200_aux.h	11055;"	d
+CBR_RG_IDACAQ_PGAG9_HI	include/ssv6200_aux.h	11044;"	d
+CBR_RG_IDACAQ_PGAG9_I_MSK	include/ssv6200_aux.h	11042;"	d
+CBR_RG_IDACAQ_PGAG9_MSK	include/ssv6200_aux.h	11041;"	d
+CBR_RG_IDACAQ_PGAG9_SFT	include/ssv6200_aux.h	11043;"	d
+CBR_RG_IDACAQ_PGAG9_SZ	include/ssv6200_aux.h	11045;"	d
+CBR_RG_IDEAL_CYCLE_HI	include/ssv6200_aux.h	10864;"	d
+CBR_RG_IDEAL_CYCLE_I_MSK	include/ssv6200_aux.h	10862;"	d
+CBR_RG_IDEAL_CYCLE_MSK	include/ssv6200_aux.h	10861;"	d
+CBR_RG_IDEAL_CYCLE_SFT	include/ssv6200_aux.h	10863;"	d
+CBR_RG_IDEAL_CYCLE_SZ	include/ssv6200_aux.h	10865;"	d
+CBR_RG_I_PAD_PD_HI	include/ssv6200_aux.h	11299;"	d
+CBR_RG_I_PAD_PD_I_MSK	include/ssv6200_aux.h	11297;"	d
+CBR_RG_I_PAD_PD_MSK	include/ssv6200_aux.h	11296;"	d
+CBR_RG_I_PAD_PD_SFT	include/ssv6200_aux.h	11298;"	d
+CBR_RG_I_PAD_PD_SZ	include/ssv6200_aux.h	11300;"	d
+CBR_RG_LDO_LEVEL_ABB_HI	include/ssv6200_aux.h	9924;"	d
+CBR_RG_LDO_LEVEL_ABB_I_MSK	include/ssv6200_aux.h	9922;"	d
+CBR_RG_LDO_LEVEL_ABB_MSK	include/ssv6200_aux.h	9921;"	d
+CBR_RG_LDO_LEVEL_ABB_SFT	include/ssv6200_aux.h	9923;"	d
+CBR_RG_LDO_LEVEL_ABB_SZ	include/ssv6200_aux.h	9925;"	d
+CBR_RG_LDO_LEVEL_AFE_HI	include/ssv6200_aux.h	9929;"	d
+CBR_RG_LDO_LEVEL_AFE_I_MSK	include/ssv6200_aux.h	9927;"	d
+CBR_RG_LDO_LEVEL_AFE_MSK	include/ssv6200_aux.h	9926;"	d
+CBR_RG_LDO_LEVEL_AFE_SFT	include/ssv6200_aux.h	9928;"	d
+CBR_RG_LDO_LEVEL_AFE_SZ	include/ssv6200_aux.h	9930;"	d
+CBR_RG_LDO_LEVEL_RX_FE_HI	include/ssv6200_aux.h	9919;"	d
+CBR_RG_LDO_LEVEL_RX_FE_I_MSK	include/ssv6200_aux.h	9917;"	d
+CBR_RG_LDO_LEVEL_RX_FE_MSK	include/ssv6200_aux.h	9916;"	d
+CBR_RG_LDO_LEVEL_RX_FE_SFT	include/ssv6200_aux.h	9918;"	d
+CBR_RG_LDO_LEVEL_RX_FE_SZ	include/ssv6200_aux.h	9920;"	d
+CBR_RG_MODE_HI	include/ssv6200_aux.h	9764;"	d
+CBR_RG_MODE_I_MSK	include/ssv6200_aux.h	9762;"	d
+CBR_RG_MODE_MSK	include/ssv6200_aux.h	9761;"	d
+CBR_RG_MODE_SFT	include/ssv6200_aux.h	9763;"	d
+CBR_RG_MODE_SZ	include/ssv6200_aux.h	9765;"	d
+CBR_RG_O_PAD_PD_HI	include/ssv6200_aux.h	11294;"	d
+CBR_RG_O_PAD_PD_I_MSK	include/ssv6200_aux.h	11292;"	d
+CBR_RG_O_PAD_PD_MSK	include/ssv6200_aux.h	11291;"	d
+CBR_RG_O_PAD_PD_SFT	include/ssv6200_aux.h	11293;"	d
+CBR_RG_O_PAD_PD_SZ	include/ssv6200_aux.h	11295;"	d
+CBR_RG_PABIAS_AB_HI	include/ssv6200_aux.h	10159;"	d
+CBR_RG_PABIAS_AB_I_MSK	include/ssv6200_aux.h	10157;"	d
+CBR_RG_PABIAS_AB_MSK	include/ssv6200_aux.h	10156;"	d
+CBR_RG_PABIAS_AB_SFT	include/ssv6200_aux.h	10158;"	d
+CBR_RG_PABIAS_AB_SZ	include/ssv6200_aux.h	10160;"	d
+CBR_RG_PABIAS_CTRL_HI	include/ssv6200_aux.h	10154;"	d
+CBR_RG_PABIAS_CTRL_I_MSK	include/ssv6200_aux.h	10152;"	d
+CBR_RG_PABIAS_CTRL_MSK	include/ssv6200_aux.h	10151;"	d
+CBR_RG_PABIAS_CTRL_SFT	include/ssv6200_aux.h	10153;"	d
+CBR_RG_PABIAS_CTRL_SZ	include/ssv6200_aux.h	10155;"	d
+CBR_RG_PACELL_EN_HI	include/ssv6200_aux.h	10149;"	d
+CBR_RG_PACELL_EN_I_MSK	include/ssv6200_aux.h	10147;"	d
+CBR_RG_PACELL_EN_MSK	include/ssv6200_aux.h	10146;"	d
+CBR_RG_PACELL_EN_SFT	include/ssv6200_aux.h	10148;"	d
+CBR_RG_PACELL_EN_SZ	include/ssv6200_aux.h	10150;"	d
+CBR_RG_PAD_DS_CLK_HI	include/ssv6200_aux.h	11319;"	d
+CBR_RG_PAD_DS_CLK_I_MSK	include/ssv6200_aux.h	11317;"	d
+CBR_RG_PAD_DS_CLK_MSK	include/ssv6200_aux.h	11316;"	d
+CBR_RG_PAD_DS_CLK_SFT	include/ssv6200_aux.h	11318;"	d
+CBR_RG_PAD_DS_CLK_SZ	include/ssv6200_aux.h	11320;"	d
+CBR_RG_PAD_DS_HI	include/ssv6200_aux.h	11309;"	d
+CBR_RG_PAD_DS_I_MSK	include/ssv6200_aux.h	11307;"	d
+CBR_RG_PAD_DS_MSK	include/ssv6200_aux.h	11306;"	d
+CBR_RG_PAD_DS_SFT	include/ssv6200_aux.h	11308;"	d
+CBR_RG_PAD_DS_SZ	include/ssv6200_aux.h	11310;"	d
+CBR_RG_PGAG_HI	include/ssv6200_aux.h	9759;"	d
+CBR_RG_PGAG_I_MSK	include/ssv6200_aux.h	9757;"	d
+CBR_RG_PGAG_MSK	include/ssv6200_aux.h	9756;"	d
+CBR_RG_PGAG_SFT	include/ssv6200_aux.h	9758;"	d
+CBR_RG_PGAG_SZ	include/ssv6200_aux.h	9760;"	d
+CBR_RG_PKT_GEN_TX_CNT_HI	include/ssv6200_aux.h	11354;"	d
+CBR_RG_PKT_GEN_TX_CNT_I_MSK	include/ssv6200_aux.h	11352;"	d
+CBR_RG_PKT_GEN_TX_CNT_MSK	include/ssv6200_aux.h	11351;"	d
+CBR_RG_PKT_GEN_TX_CNT_SFT	include/ssv6200_aux.h	11353;"	d
+CBR_RG_PKT_GEN_TX_CNT_SZ	include/ssv6200_aux.h	11355;"	d
+CBR_RG_RCAL_CODE_CWD_HI	include/ssv6200_aux.h	11159;"	d
+CBR_RG_RCAL_CODE_CWD_I_MSK	include/ssv6200_aux.h	11157;"	d
+CBR_RG_RCAL_CODE_CWD_MSK	include/ssv6200_aux.h	11156;"	d
+CBR_RG_RCAL_CODE_CWD_SFT	include/ssv6200_aux.h	11158;"	d
+CBR_RG_RCAL_CODE_CWD_SZ	include/ssv6200_aux.h	11160;"	d
+CBR_RG_RCAL_CODE_CWR_HI	include/ssv6200_aux.h	11154;"	d
+CBR_RG_RCAL_CODE_CWR_I_MSK	include/ssv6200_aux.h	11152;"	d
+CBR_RG_RCAL_CODE_CWR_MSK	include/ssv6200_aux.h	11151;"	d
+CBR_RG_RCAL_CODE_CWR_SFT	include/ssv6200_aux.h	11153;"	d
+CBR_RG_RCAL_CODE_CWR_SZ	include/ssv6200_aux.h	11155;"	d
+CBR_RG_RCAL_SPD_HI	include/ssv6200_aux.h	11144;"	d
+CBR_RG_RCAL_SPD_I_MSK	include/ssv6200_aux.h	11142;"	d
+CBR_RG_RCAL_SPD_MSK	include/ssv6200_aux.h	11141;"	d
+CBR_RG_RCAL_SPD_SFT	include/ssv6200_aux.h	11143;"	d
+CBR_RG_RCAL_SPD_SZ	include/ssv6200_aux.h	11145;"	d
+CBR_RG_RCAL_TMR_HI	include/ssv6200_aux.h	11149;"	d
+CBR_RG_RCAL_TMR_I_MSK	include/ssv6200_aux.h	11147;"	d
+CBR_RG_RCAL_TMR_MSK	include/ssv6200_aux.h	11146;"	d
+CBR_RG_RCAL_TMR_SFT	include/ssv6200_aux.h	11148;"	d
+CBR_RG_RCAL_TMR_SZ	include/ssv6200_aux.h	11150;"	d
+CBR_RG_RFG_HI	include/ssv6200_aux.h	9754;"	d
+CBR_RG_RFG_I_MSK	include/ssv6200_aux.h	9752;"	d
+CBR_RG_RFG_MSK	include/ssv6200_aux.h	9751;"	d
+CBR_RG_RFG_SFT	include/ssv6200_aux.h	9753;"	d
+CBR_RG_RFG_SZ	include/ssv6200_aux.h	9755;"	d
+CBR_RG_RSSI_CLOCK_GATING_HI	include/ssv6200_aux.h	10119;"	d
+CBR_RG_RSSI_CLOCK_GATING_I_MSK	include/ssv6200_aux.h	10117;"	d
+CBR_RG_RSSI_CLOCK_GATING_MSK	include/ssv6200_aux.h	10116;"	d
+CBR_RG_RSSI_CLOCK_GATING_SFT	include/ssv6200_aux.h	10118;"	d
+CBR_RG_RSSI_CLOCK_GATING_SZ	include/ssv6200_aux.h	10120;"	d
+CBR_RG_RX_ABBCFIX_HI	include/ssv6200_aux.h	9979;"	d
+CBR_RG_RX_ABBCFIX_I_MSK	include/ssv6200_aux.h	9977;"	d
+CBR_RG_RX_ABBCFIX_MSK	include/ssv6200_aux.h	9976;"	d
+CBR_RG_RX_ABBCFIX_SFT	include/ssv6200_aux.h	9978;"	d
+CBR_RG_RX_ABBCFIX_SZ	include/ssv6200_aux.h	9980;"	d
+CBR_RG_RX_ABBCTUNE_HI	include/ssv6200_aux.h	9984;"	d
+CBR_RG_RX_ABBCTUNE_I_MSK	include/ssv6200_aux.h	9982;"	d
+CBR_RG_RX_ABBCTUNE_MSK	include/ssv6200_aux.h	9981;"	d
+CBR_RG_RX_ABBCTUNE_SFT	include/ssv6200_aux.h	9983;"	d
+CBR_RG_RX_ABBCTUNE_SZ	include/ssv6200_aux.h	9985;"	d
+CBR_RG_RX_ABBOUT_TRI_STATE_HI	include/ssv6200_aux.h	9989;"	d
+CBR_RG_RX_ABBOUT_TRI_STATE_I_MSK	include/ssv6200_aux.h	9987;"	d
+CBR_RG_RX_ABBOUT_TRI_STATE_MSK	include/ssv6200_aux.h	9986;"	d
+CBR_RG_RX_ABBOUT_TRI_STATE_SFT	include/ssv6200_aux.h	9988;"	d
+CBR_RG_RX_ABBOUT_TRI_STATE_SZ	include/ssv6200_aux.h	9990;"	d
+CBR_RG_RX_ABB_N_MODE_HI	include/ssv6200_aux.h	9994;"	d
+CBR_RG_RX_ABB_N_MODE_I_MSK	include/ssv6200_aux.h	9992;"	d
+CBR_RG_RX_ABB_N_MODE_MSK	include/ssv6200_aux.h	9991;"	d
+CBR_RG_RX_ABB_N_MODE_SFT	include/ssv6200_aux.h	9993;"	d
+CBR_RG_RX_ABB_N_MODE_SZ	include/ssv6200_aux.h	9995;"	d
+CBR_RG_RX_ADCRSSI_CLKSEL_HI	include/ssv6200_aux.h	10104;"	d
+CBR_RG_RX_ADCRSSI_CLKSEL_I_MSK	include/ssv6200_aux.h	10102;"	d
+CBR_RG_RX_ADCRSSI_CLKSEL_MSK	include/ssv6200_aux.h	10101;"	d
+CBR_RG_RX_ADCRSSI_CLKSEL_SFT	include/ssv6200_aux.h	10103;"	d
+CBR_RG_RX_ADCRSSI_CLKSEL_SZ	include/ssv6200_aux.h	10105;"	d
+CBR_RG_RX_ADCRSSI_VCM_HI	include/ssv6200_aux.h	10109;"	d
+CBR_RG_RX_ADCRSSI_VCM_I_MSK	include/ssv6200_aux.h	10107;"	d
+CBR_RG_RX_ADCRSSI_VCM_MSK	include/ssv6200_aux.h	10106;"	d
+CBR_RG_RX_ADCRSSI_VCM_SFT	include/ssv6200_aux.h	10108;"	d
+CBR_RG_RX_ADCRSSI_VCM_SZ	include/ssv6200_aux.h	10110;"	d
+CBR_RG_RX_AGC_HI	include/ssv6200_aux.h	9744;"	d
+CBR_RG_RX_AGC_I_MSK	include/ssv6200_aux.h	9742;"	d
+CBR_RG_RX_AGC_MSK	include/ssv6200_aux.h	9741;"	d
+CBR_RG_RX_AGC_SFT	include/ssv6200_aux.h	9743;"	d
+CBR_RG_RX_AGC_SZ	include/ssv6200_aux.h	9745;"	d
+CBR_RG_RX_DIV2_CORE_HI	include/ssv6200_aux.h	10179;"	d
+CBR_RG_RX_DIV2_CORE_I_MSK	include/ssv6200_aux.h	10177;"	d
+CBR_RG_RX_DIV2_CORE_MSK	include/ssv6200_aux.h	10176;"	d
+CBR_RG_RX_DIV2_CORE_SFT	include/ssv6200_aux.h	10178;"	d
+CBR_RG_RX_DIV2_CORE_SZ	include/ssv6200_aux.h	10180;"	d
+CBR_RG_RX_EN_LOOPA_HI	include/ssv6200_aux.h	9999;"	d
+CBR_RG_RX_EN_LOOPA_I_MSK	include/ssv6200_aux.h	9997;"	d
+CBR_RG_RX_EN_LOOPA_MSK	include/ssv6200_aux.h	9996;"	d
+CBR_RG_RX_EN_LOOPA_SFT	include/ssv6200_aux.h	9998;"	d
+CBR_RG_RX_EN_LOOPA_SZ	include/ssv6200_aux.h	10000;"	d
+CBR_RG_RX_FILTERI1ST_HI	include/ssv6200_aux.h	10004;"	d
+CBR_RG_RX_FILTERI1ST_I_MSK	include/ssv6200_aux.h	10002;"	d
+CBR_RG_RX_FILTERI1ST_MSK	include/ssv6200_aux.h	10001;"	d
+CBR_RG_RX_FILTERI1ST_SFT	include/ssv6200_aux.h	10003;"	d
+CBR_RG_RX_FILTERI1ST_SZ	include/ssv6200_aux.h	10005;"	d
+CBR_RG_RX_FILTERI2ND_HI	include/ssv6200_aux.h	10009;"	d
+CBR_RG_RX_FILTERI2ND_I_MSK	include/ssv6200_aux.h	10007;"	d
+CBR_RG_RX_FILTERI2ND_MSK	include/ssv6200_aux.h	10006;"	d
+CBR_RG_RX_FILTERI2ND_SFT	include/ssv6200_aux.h	10008;"	d
+CBR_RG_RX_FILTERI2ND_SZ	include/ssv6200_aux.h	10010;"	d
+CBR_RG_RX_FILTERI3RD_HI	include/ssv6200_aux.h	10014;"	d
+CBR_RG_RX_FILTERI3RD_I_MSK	include/ssv6200_aux.h	10012;"	d
+CBR_RG_RX_FILTERI3RD_MSK	include/ssv6200_aux.h	10011;"	d
+CBR_RG_RX_FILTERI3RD_SFT	include/ssv6200_aux.h	10013;"	d
+CBR_RG_RX_FILTERI3RD_SZ	include/ssv6200_aux.h	10015;"	d
+CBR_RG_RX_FILTERI_COURSE_HI	include/ssv6200_aux.h	10019;"	d
+CBR_RG_RX_FILTERI_COURSE_I_MSK	include/ssv6200_aux.h	10017;"	d
+CBR_RG_RX_FILTERI_COURSE_MSK	include/ssv6200_aux.h	10016;"	d
+CBR_RG_RX_FILTERI_COURSE_SFT	include/ssv6200_aux.h	10018;"	d
+CBR_RG_RX_FILTERI_COURSE_SZ	include/ssv6200_aux.h	10020;"	d
+CBR_RG_RX_FILTERVCM_HI	include/ssv6200_aux.h	10024;"	d
+CBR_RG_RX_FILTERVCM_I_MSK	include/ssv6200_aux.h	10022;"	d
+CBR_RG_RX_FILTERVCM_MSK	include/ssv6200_aux.h	10021;"	d
+CBR_RG_RX_FILTERVCM_SFT	include/ssv6200_aux.h	10023;"	d
+CBR_RG_RX_FILTERVCM_SZ	include/ssv6200_aux.h	10025;"	d
+CBR_RG_RX_GAIN_MANUAL_HI	include/ssv6200_aux.h	9749;"	d
+CBR_RG_RX_GAIN_MANUAL_I_MSK	include/ssv6200_aux.h	9747;"	d
+CBR_RG_RX_GAIN_MANUAL_MSK	include/ssv6200_aux.h	9746;"	d
+CBR_RG_RX_GAIN_MANUAL_SFT	include/ssv6200_aux.h	9748;"	d
+CBR_RG_RX_GAIN_MANUAL_SZ	include/ssv6200_aux.h	9750;"	d
+CBR_RG_RX_HG_LNAHGN_BIAS_HI	include/ssv6200_aux.h	10224;"	d
+CBR_RG_RX_HG_LNAHGN_BIAS_I_MSK	include/ssv6200_aux.h	10222;"	d
+CBR_RG_RX_HG_LNAHGN_BIAS_MSK	include/ssv6200_aux.h	10221;"	d
+CBR_RG_RX_HG_LNAHGN_BIAS_SFT	include/ssv6200_aux.h	10223;"	d
+CBR_RG_RX_HG_LNAHGN_BIAS_SZ	include/ssv6200_aux.h	10225;"	d
+CBR_RG_RX_HG_LNAHGP_BIAS_HI	include/ssv6200_aux.h	10229;"	d
+CBR_RG_RX_HG_LNAHGP_BIAS_I_MSK	include/ssv6200_aux.h	10227;"	d
+CBR_RG_RX_HG_LNAHGP_BIAS_MSK	include/ssv6200_aux.h	10226;"	d
+CBR_RG_RX_HG_LNAHGP_BIAS_SFT	include/ssv6200_aux.h	10228;"	d
+CBR_RG_RX_HG_LNAHGP_BIAS_SZ	include/ssv6200_aux.h	10230;"	d
+CBR_RG_RX_HG_LNALG_BIAS_HI	include/ssv6200_aux.h	10234;"	d
+CBR_RG_RX_HG_LNALG_BIAS_I_MSK	include/ssv6200_aux.h	10232;"	d
+CBR_RG_RX_HG_LNALG_BIAS_MSK	include/ssv6200_aux.h	10231;"	d
+CBR_RG_RX_HG_LNALG_BIAS_SFT	include/ssv6200_aux.h	10233;"	d
+CBR_RG_RX_HG_LNALG_BIAS_SZ	include/ssv6200_aux.h	10235;"	d
+CBR_RG_RX_HG_LNA_GC_HI	include/ssv6200_aux.h	10219;"	d
+CBR_RG_RX_HG_LNA_GC_I_MSK	include/ssv6200_aux.h	10217;"	d
+CBR_RG_RX_HG_LNA_GC_MSK	include/ssv6200_aux.h	10216;"	d
+CBR_RG_RX_HG_LNA_GC_SFT	include/ssv6200_aux.h	10218;"	d
+CBR_RG_RX_HG_LNA_GC_SZ	include/ssv6200_aux.h	10220;"	d
+CBR_RG_RX_HG_TZ_CAP_HI	include/ssv6200_aux.h	10244;"	d
+CBR_RG_RX_HG_TZ_CAP_I_MSK	include/ssv6200_aux.h	10242;"	d
+CBR_RG_RX_HG_TZ_CAP_MSK	include/ssv6200_aux.h	10241;"	d
+CBR_RG_RX_HG_TZ_CAP_SFT	include/ssv6200_aux.h	10243;"	d
+CBR_RG_RX_HG_TZ_CAP_SZ	include/ssv6200_aux.h	10245;"	d
+CBR_RG_RX_HG_TZ_GC_HI	include/ssv6200_aux.h	10239;"	d
+CBR_RG_RX_HG_TZ_GC_I_MSK	include/ssv6200_aux.h	10237;"	d
+CBR_RG_RX_HG_TZ_GC_MSK	include/ssv6200_aux.h	10236;"	d
+CBR_RG_RX_HG_TZ_GC_SFT	include/ssv6200_aux.h	10238;"	d
+CBR_RG_RX_HG_TZ_GC_SZ	include/ssv6200_aux.h	10240;"	d
+CBR_RG_RX_HPF300K_HI	include/ssv6200_aux.h	10034;"	d
+CBR_RG_RX_HPF300K_I_MSK	include/ssv6200_aux.h	10032;"	d
+CBR_RG_RX_HPF300K_MSK	include/ssv6200_aux.h	10031;"	d
+CBR_RG_RX_HPF300K_SFT	include/ssv6200_aux.h	10033;"	d
+CBR_RG_RX_HPF300K_SZ	include/ssv6200_aux.h	10035;"	d
+CBR_RG_RX_HPF3M_HI	include/ssv6200_aux.h	10029;"	d
+CBR_RG_RX_HPF3M_I_MSK	include/ssv6200_aux.h	10027;"	d
+CBR_RG_RX_HPF3M_MSK	include/ssv6200_aux.h	10026;"	d
+CBR_RG_RX_HPF3M_SFT	include/ssv6200_aux.h	10028;"	d
+CBR_RG_RX_HPF3M_SZ	include/ssv6200_aux.h	10030;"	d
+CBR_RG_RX_HPFI_HI	include/ssv6200_aux.h	10039;"	d
+CBR_RG_RX_HPFI_I_MSK	include/ssv6200_aux.h	10037;"	d
+CBR_RG_RX_HPFI_MSK	include/ssv6200_aux.h	10036;"	d
+CBR_RG_RX_HPFI_SFT	include/ssv6200_aux.h	10038;"	d
+CBR_RG_RX_HPFI_SZ	include/ssv6200_aux.h	10040;"	d
+CBR_RG_RX_HPF_FINALCORNER_HI	include/ssv6200_aux.h	10044;"	d
+CBR_RG_RX_HPF_FINALCORNER_I_MSK	include/ssv6200_aux.h	10042;"	d
+CBR_RG_RX_HPF_FINALCORNER_MSK	include/ssv6200_aux.h	10041;"	d
+CBR_RG_RX_HPF_FINALCORNER_SFT	include/ssv6200_aux.h	10043;"	d
+CBR_RG_RX_HPF_FINALCORNER_SZ	include/ssv6200_aux.h	10045;"	d
+CBR_RG_RX_HPF_SETTLE1_C_HI	include/ssv6200_aux.h	10049;"	d
+CBR_RG_RX_HPF_SETTLE1_C_I_MSK	include/ssv6200_aux.h	10047;"	d
+CBR_RG_RX_HPF_SETTLE1_C_MSK	include/ssv6200_aux.h	10046;"	d
+CBR_RG_RX_HPF_SETTLE1_C_SFT	include/ssv6200_aux.h	10048;"	d
+CBR_RG_RX_HPF_SETTLE1_C_SZ	include/ssv6200_aux.h	10050;"	d
+CBR_RG_RX_HPF_SETTLE1_R_HI	include/ssv6200_aux.h	10054;"	d
+CBR_RG_RX_HPF_SETTLE1_R_I_MSK	include/ssv6200_aux.h	10052;"	d
+CBR_RG_RX_HPF_SETTLE1_R_MSK	include/ssv6200_aux.h	10051;"	d
+CBR_RG_RX_HPF_SETTLE1_R_SFT	include/ssv6200_aux.h	10053;"	d
+CBR_RG_RX_HPF_SETTLE1_R_SZ	include/ssv6200_aux.h	10055;"	d
+CBR_RG_RX_HPF_SETTLE2_C_HI	include/ssv6200_aux.h	10059;"	d
+CBR_RG_RX_HPF_SETTLE2_C_I_MSK	include/ssv6200_aux.h	10057;"	d
+CBR_RG_RX_HPF_SETTLE2_C_MSK	include/ssv6200_aux.h	10056;"	d
+CBR_RG_RX_HPF_SETTLE2_C_SFT	include/ssv6200_aux.h	10058;"	d
+CBR_RG_RX_HPF_SETTLE2_C_SZ	include/ssv6200_aux.h	10060;"	d
+CBR_RG_RX_HPF_SETTLE2_R_HI	include/ssv6200_aux.h	10064;"	d
+CBR_RG_RX_HPF_SETTLE2_R_I_MSK	include/ssv6200_aux.h	10062;"	d
+CBR_RG_RX_HPF_SETTLE2_R_MSK	include/ssv6200_aux.h	10061;"	d
+CBR_RG_RX_HPF_SETTLE2_R_SFT	include/ssv6200_aux.h	10063;"	d
+CBR_RG_RX_HPF_SETTLE2_R_SZ	include/ssv6200_aux.h	10065;"	d
+CBR_RG_RX_HPF_VCMCON2_HI	include/ssv6200_aux.h	10069;"	d
+CBR_RG_RX_HPF_VCMCON2_I_MSK	include/ssv6200_aux.h	10067;"	d
+CBR_RG_RX_HPF_VCMCON2_MSK	include/ssv6200_aux.h	10066;"	d
+CBR_RG_RX_HPF_VCMCON2_SFT	include/ssv6200_aux.h	10068;"	d
+CBR_RG_RX_HPF_VCMCON2_SZ	include/ssv6200_aux.h	10070;"	d
+CBR_RG_RX_HPF_VCMCON_HI	include/ssv6200_aux.h	10074;"	d
+CBR_RG_RX_HPF_VCMCON_I_MSK	include/ssv6200_aux.h	10072;"	d
+CBR_RG_RX_HPF_VCMCON_MSK	include/ssv6200_aux.h	10071;"	d
+CBR_RG_RX_HPF_VCMCON_SFT	include/ssv6200_aux.h	10073;"	d
+CBR_RG_RX_HPF_VCMCON_SZ	include/ssv6200_aux.h	10075;"	d
+CBR_RG_RX_LG_LNAHGN_BIAS_HI	include/ssv6200_aux.h	10284;"	d
+CBR_RG_RX_LG_LNAHGN_BIAS_I_MSK	include/ssv6200_aux.h	10282;"	d
+CBR_RG_RX_LG_LNAHGN_BIAS_MSK	include/ssv6200_aux.h	10281;"	d
+CBR_RG_RX_LG_LNAHGN_BIAS_SFT	include/ssv6200_aux.h	10283;"	d
+CBR_RG_RX_LG_LNAHGN_BIAS_SZ	include/ssv6200_aux.h	10285;"	d
+CBR_RG_RX_LG_LNAHGP_BIAS_HI	include/ssv6200_aux.h	10289;"	d
+CBR_RG_RX_LG_LNAHGP_BIAS_I_MSK	include/ssv6200_aux.h	10287;"	d
+CBR_RG_RX_LG_LNAHGP_BIAS_MSK	include/ssv6200_aux.h	10286;"	d
+CBR_RG_RX_LG_LNAHGP_BIAS_SFT	include/ssv6200_aux.h	10288;"	d
+CBR_RG_RX_LG_LNAHGP_BIAS_SZ	include/ssv6200_aux.h	10290;"	d
+CBR_RG_RX_LG_LNALG_BIAS_HI	include/ssv6200_aux.h	10294;"	d
+CBR_RG_RX_LG_LNALG_BIAS_I_MSK	include/ssv6200_aux.h	10292;"	d
+CBR_RG_RX_LG_LNALG_BIAS_MSK	include/ssv6200_aux.h	10291;"	d
+CBR_RG_RX_LG_LNALG_BIAS_SFT	include/ssv6200_aux.h	10293;"	d
+CBR_RG_RX_LG_LNALG_BIAS_SZ	include/ssv6200_aux.h	10295;"	d
+CBR_RG_RX_LG_LNA_GC_HI	include/ssv6200_aux.h	10279;"	d
+CBR_RG_RX_LG_LNA_GC_I_MSK	include/ssv6200_aux.h	10277;"	d
+CBR_RG_RX_LG_LNA_GC_MSK	include/ssv6200_aux.h	10276;"	d
+CBR_RG_RX_LG_LNA_GC_SFT	include/ssv6200_aux.h	10278;"	d
+CBR_RG_RX_LG_LNA_GC_SZ	include/ssv6200_aux.h	10280;"	d
+CBR_RG_RX_LG_TZ_CAP_HI	include/ssv6200_aux.h	10304;"	d
+CBR_RG_RX_LG_TZ_CAP_I_MSK	include/ssv6200_aux.h	10302;"	d
+CBR_RG_RX_LG_TZ_CAP_MSK	include/ssv6200_aux.h	10301;"	d
+CBR_RG_RX_LG_TZ_CAP_SFT	include/ssv6200_aux.h	10303;"	d
+CBR_RG_RX_LG_TZ_CAP_SZ	include/ssv6200_aux.h	10305;"	d
+CBR_RG_RX_LG_TZ_GC_HI	include/ssv6200_aux.h	10299;"	d
+CBR_RG_RX_LG_TZ_GC_I_MSK	include/ssv6200_aux.h	10297;"	d
+CBR_RG_RX_LG_TZ_GC_MSK	include/ssv6200_aux.h	10296;"	d
+CBR_RG_RX_LG_TZ_GC_SFT	include/ssv6200_aux.h	10298;"	d
+CBR_RG_RX_LG_TZ_GC_SZ	include/ssv6200_aux.h	10300;"	d
+CBR_RG_RX_LNA_SETTLE_HI	include/ssv6200_aux.h	10374;"	d
+CBR_RG_RX_LNA_SETTLE_I_MSK	include/ssv6200_aux.h	10372;"	d
+CBR_RG_RX_LNA_SETTLE_MSK	include/ssv6200_aux.h	10371;"	d
+CBR_RG_RX_LNA_SETTLE_SFT	include/ssv6200_aux.h	10373;"	d
+CBR_RG_RX_LNA_SETTLE_SZ	include/ssv6200_aux.h	10375;"	d
+CBR_RG_RX_LNA_TRI_SEL_HI	include/ssv6200_aux.h	10369;"	d
+CBR_RG_RX_LNA_TRI_SEL_I_MSK	include/ssv6200_aux.h	10367;"	d
+CBR_RG_RX_LNA_TRI_SEL_MSK	include/ssv6200_aux.h	10366;"	d
+CBR_RG_RX_LNA_TRI_SEL_SFT	include/ssv6200_aux.h	10368;"	d
+CBR_RG_RX_LNA_TRI_SEL_SZ	include/ssv6200_aux.h	10370;"	d
+CBR_RG_RX_LOBUF_HI	include/ssv6200_aux.h	10184;"	d
+CBR_RG_RX_LOBUF_I_MSK	include/ssv6200_aux.h	10182;"	d
+CBR_RG_RX_LOBUF_MSK	include/ssv6200_aux.h	10181;"	d
+CBR_RG_RX_LOBUF_SFT	include/ssv6200_aux.h	10183;"	d
+CBR_RG_RX_LOBUF_SZ	include/ssv6200_aux.h	10185;"	d
+CBR_RG_RX_MG_LNAHGN_BIAS_HI	include/ssv6200_aux.h	10254;"	d
+CBR_RG_RX_MG_LNAHGN_BIAS_I_MSK	include/ssv6200_aux.h	10252;"	d
+CBR_RG_RX_MG_LNAHGN_BIAS_MSK	include/ssv6200_aux.h	10251;"	d
+CBR_RG_RX_MG_LNAHGN_BIAS_SFT	include/ssv6200_aux.h	10253;"	d
+CBR_RG_RX_MG_LNAHGN_BIAS_SZ	include/ssv6200_aux.h	10255;"	d
+CBR_RG_RX_MG_LNAHGP_BIAS_HI	include/ssv6200_aux.h	10259;"	d
+CBR_RG_RX_MG_LNAHGP_BIAS_I_MSK	include/ssv6200_aux.h	10257;"	d
+CBR_RG_RX_MG_LNAHGP_BIAS_MSK	include/ssv6200_aux.h	10256;"	d
+CBR_RG_RX_MG_LNAHGP_BIAS_SFT	include/ssv6200_aux.h	10258;"	d
+CBR_RG_RX_MG_LNAHGP_BIAS_SZ	include/ssv6200_aux.h	10260;"	d
+CBR_RG_RX_MG_LNALG_BIAS_HI	include/ssv6200_aux.h	10264;"	d
+CBR_RG_RX_MG_LNALG_BIAS_I_MSK	include/ssv6200_aux.h	10262;"	d
+CBR_RG_RX_MG_LNALG_BIAS_MSK	include/ssv6200_aux.h	10261;"	d
+CBR_RG_RX_MG_LNALG_BIAS_SFT	include/ssv6200_aux.h	10263;"	d
+CBR_RG_RX_MG_LNALG_BIAS_SZ	include/ssv6200_aux.h	10265;"	d
+CBR_RG_RX_MG_LNA_GC_HI	include/ssv6200_aux.h	10249;"	d
+CBR_RG_RX_MG_LNA_GC_I_MSK	include/ssv6200_aux.h	10247;"	d
+CBR_RG_RX_MG_LNA_GC_MSK	include/ssv6200_aux.h	10246;"	d
+CBR_RG_RX_MG_LNA_GC_SFT	include/ssv6200_aux.h	10248;"	d
+CBR_RG_RX_MG_LNA_GC_SZ	include/ssv6200_aux.h	10250;"	d
+CBR_RG_RX_MG_TZ_CAP_HI	include/ssv6200_aux.h	10274;"	d
+CBR_RG_RX_MG_TZ_CAP_I_MSK	include/ssv6200_aux.h	10272;"	d
+CBR_RG_RX_MG_TZ_CAP_MSK	include/ssv6200_aux.h	10271;"	d
+CBR_RG_RX_MG_TZ_CAP_SFT	include/ssv6200_aux.h	10273;"	d
+CBR_RG_RX_MG_TZ_CAP_SZ	include/ssv6200_aux.h	10275;"	d
+CBR_RG_RX_MG_TZ_GC_HI	include/ssv6200_aux.h	10269;"	d
+CBR_RG_RX_MG_TZ_GC_I_MSK	include/ssv6200_aux.h	10267;"	d
+CBR_RG_RX_MG_TZ_GC_MSK	include/ssv6200_aux.h	10266;"	d
+CBR_RG_RX_MG_TZ_GC_SFT	include/ssv6200_aux.h	10268;"	d
+CBR_RG_RX_MG_TZ_GC_SZ	include/ssv6200_aux.h	10270;"	d
+CBR_RG_RX_OUTVCM_HI	include/ssv6200_aux.h	10079;"	d
+CBR_RG_RX_OUTVCM_I_MSK	include/ssv6200_aux.h	10077;"	d
+CBR_RG_RX_OUTVCM_MSK	include/ssv6200_aux.h	10076;"	d
+CBR_RG_RX_OUTVCM_SFT	include/ssv6200_aux.h	10078;"	d
+CBR_RG_RX_OUTVCM_SZ	include/ssv6200_aux.h	10080;"	d
+CBR_RG_RX_REC_LPFCORNER_HI	include/ssv6200_aux.h	10114;"	d
+CBR_RG_RX_REC_LPFCORNER_I_MSK	include/ssv6200_aux.h	10112;"	d
+CBR_RG_RX_REC_LPFCORNER_MSK	include/ssv6200_aux.h	10111;"	d
+CBR_RG_RX_REC_LPFCORNER_SFT	include/ssv6200_aux.h	10113;"	d
+CBR_RG_RX_REC_LPFCORNER_SZ	include/ssv6200_aux.h	10115;"	d
+CBR_RG_RX_SQDC_HI	include/ssv6200_aux.h	10174;"	d
+CBR_RG_RX_SQDC_I_MSK	include/ssv6200_aux.h	10172;"	d
+CBR_RG_RX_SQDC_MSK	include/ssv6200_aux.h	10171;"	d
+CBR_RG_RX_SQDC_SFT	include/ssv6200_aux.h	10173;"	d
+CBR_RG_RX_SQDC_SZ	include/ssv6200_aux.h	10175;"	d
+CBR_RG_RX_TZI_HI	include/ssv6200_aux.h	10084;"	d
+CBR_RG_RX_TZI_I_MSK	include/ssv6200_aux.h	10082;"	d
+CBR_RG_RX_TZI_MSK	include/ssv6200_aux.h	10081;"	d
+CBR_RG_RX_TZI_SFT	include/ssv6200_aux.h	10083;"	d
+CBR_RG_RX_TZI_SZ	include/ssv6200_aux.h	10085;"	d
+CBR_RG_RX_TZ_OUT_TRISTATE_HI	include/ssv6200_aux.h	10089;"	d
+CBR_RG_RX_TZ_OUT_TRISTATE_I_MSK	include/ssv6200_aux.h	10087;"	d
+CBR_RG_RX_TZ_OUT_TRISTATE_MSK	include/ssv6200_aux.h	10086;"	d
+CBR_RG_RX_TZ_OUT_TRISTATE_SFT	include/ssv6200_aux.h	10088;"	d
+CBR_RG_RX_TZ_OUT_TRISTATE_SZ	include/ssv6200_aux.h	10090;"	d
+CBR_RG_RX_TZ_VCM_HI	include/ssv6200_aux.h	10094;"	d
+CBR_RG_RX_TZ_VCM_I_MSK	include/ssv6200_aux.h	10092;"	d
+CBR_RG_RX_TZ_VCM_MSK	include/ssv6200_aux.h	10091;"	d
+CBR_RG_RX_TZ_VCM_SFT	include/ssv6200_aux.h	10093;"	d
+CBR_RG_RX_TZ_VCM_SZ	include/ssv6200_aux.h	10095;"	d
+CBR_RG_RX_ULG_LNAHGN_BIAS_HI	include/ssv6200_aux.h	10314;"	d
+CBR_RG_RX_ULG_LNAHGN_BIAS_I_MSK	include/ssv6200_aux.h	10312;"	d
+CBR_RG_RX_ULG_LNAHGN_BIAS_MSK	include/ssv6200_aux.h	10311;"	d
+CBR_RG_RX_ULG_LNAHGN_BIAS_SFT	include/ssv6200_aux.h	10313;"	d
+CBR_RG_RX_ULG_LNAHGN_BIAS_SZ	include/ssv6200_aux.h	10315;"	d
+CBR_RG_RX_ULG_LNAHGP_BIAS_HI	include/ssv6200_aux.h	10319;"	d
+CBR_RG_RX_ULG_LNAHGP_BIAS_I_MSK	include/ssv6200_aux.h	10317;"	d
+CBR_RG_RX_ULG_LNAHGP_BIAS_MSK	include/ssv6200_aux.h	10316;"	d
+CBR_RG_RX_ULG_LNAHGP_BIAS_SFT	include/ssv6200_aux.h	10318;"	d
+CBR_RG_RX_ULG_LNAHGP_BIAS_SZ	include/ssv6200_aux.h	10320;"	d
+CBR_RG_RX_ULG_LNALG_BIAS_HI	include/ssv6200_aux.h	10324;"	d
+CBR_RG_RX_ULG_LNALG_BIAS_I_MSK	include/ssv6200_aux.h	10322;"	d
+CBR_RG_RX_ULG_LNALG_BIAS_MSK	include/ssv6200_aux.h	10321;"	d
+CBR_RG_RX_ULG_LNALG_BIAS_SFT	include/ssv6200_aux.h	10323;"	d
+CBR_RG_RX_ULG_LNALG_BIAS_SZ	include/ssv6200_aux.h	10325;"	d
+CBR_RG_RX_ULG_LNA_GC_HI	include/ssv6200_aux.h	10309;"	d
+CBR_RG_RX_ULG_LNA_GC_I_MSK	include/ssv6200_aux.h	10307;"	d
+CBR_RG_RX_ULG_LNA_GC_MSK	include/ssv6200_aux.h	10306;"	d
+CBR_RG_RX_ULG_LNA_GC_SFT	include/ssv6200_aux.h	10308;"	d
+CBR_RG_RX_ULG_LNA_GC_SZ	include/ssv6200_aux.h	10310;"	d
+CBR_RG_RX_ULG_TZ_CAP_HI	include/ssv6200_aux.h	10334;"	d
+CBR_RG_RX_ULG_TZ_CAP_I_MSK	include/ssv6200_aux.h	10332;"	d
+CBR_RG_RX_ULG_TZ_CAP_MSK	include/ssv6200_aux.h	10331;"	d
+CBR_RG_RX_ULG_TZ_CAP_SFT	include/ssv6200_aux.h	10333;"	d
+CBR_RG_RX_ULG_TZ_CAP_SZ	include/ssv6200_aux.h	10335;"	d
+CBR_RG_RX_ULG_TZ_GC_HI	include/ssv6200_aux.h	10329;"	d
+CBR_RG_RX_ULG_TZ_GC_I_MSK	include/ssv6200_aux.h	10327;"	d
+CBR_RG_RX_ULG_TZ_GC_MSK	include/ssv6200_aux.h	10326;"	d
+CBR_RG_RX_ULG_TZ_GC_SFT	include/ssv6200_aux.h	10328;"	d
+CBR_RG_RX_ULG_TZ_GC_SZ	include/ssv6200_aux.h	10330;"	d
+CBR_RG_SDM_PASS_HI	include/ssv6200_aux.h	10744;"	d
+CBR_RG_SDM_PASS_I_MSK	include/ssv6200_aux.h	10742;"	d
+CBR_RG_SDM_PASS_MSK	include/ssv6200_aux.h	10741;"	d
+CBR_RG_SDM_PASS_SFT	include/ssv6200_aux.h	10743;"	d
+CBR_RG_SDM_PASS_SZ	include/ssv6200_aux.h	10745;"	d
+CBR_RG_SEL_DPLL_CLK_HI	include/ssv6200_aux.h	9849;"	d
+CBR_RG_SEL_DPLL_CLK_I_MSK	include/ssv6200_aux.h	9847;"	d
+CBR_RG_SEL_DPLL_CLK_MSK	include/ssv6200_aux.h	9846;"	d
+CBR_RG_SEL_DPLL_CLK_SFT	include/ssv6200_aux.h	9848;"	d
+CBR_RG_SEL_DPLL_CLK_SZ	include/ssv6200_aux.h	9850;"	d
+CBR_RG_SX_CHP_IOST_HI	include/ssv6200_aux.h	10629;"	d
+CBR_RG_SX_CHP_IOST_I_MSK	include/ssv6200_aux.h	10627;"	d
+CBR_RG_SX_CHP_IOST_MSK	include/ssv6200_aux.h	10626;"	d
+CBR_RG_SX_CHP_IOST_POL_HI	include/ssv6200_aux.h	10624;"	d
+CBR_RG_SX_CHP_IOST_POL_I_MSK	include/ssv6200_aux.h	10622;"	d
+CBR_RG_SX_CHP_IOST_POL_MSK	include/ssv6200_aux.h	10621;"	d
+CBR_RG_SX_CHP_IOST_POL_SFT	include/ssv6200_aux.h	10623;"	d
+CBR_RG_SX_CHP_IOST_POL_SZ	include/ssv6200_aux.h	10625;"	d
+CBR_RG_SX_CHP_IOST_SFT	include/ssv6200_aux.h	10628;"	d
+CBR_RG_SX_CHP_IOST_SZ	include/ssv6200_aux.h	10630;"	d
+CBR_RG_SX_CV_CURVE_SEL_HI	include/ssv6200_aux.h	10804;"	d
+CBR_RG_SX_CV_CURVE_SEL_I_MSK	include/ssv6200_aux.h	10802;"	d
+CBR_RG_SX_CV_CURVE_SEL_MSK	include/ssv6200_aux.h	10801;"	d
+CBR_RG_SX_CV_CURVE_SEL_SFT	include/ssv6200_aux.h	10803;"	d
+CBR_RG_SX_CV_CURVE_SEL_SZ	include/ssv6200_aux.h	10805;"	d
+CBR_RG_SX_DELCTRL_HI	include/ssv6200_aux.h	10894;"	d
+CBR_RG_SX_DELCTRL_I_MSK	include/ssv6200_aux.h	10892;"	d
+CBR_RG_SX_DELCTRL_MSK	include/ssv6200_aux.h	10891;"	d
+CBR_RG_SX_DELCTRL_SFT	include/ssv6200_aux.h	10893;"	d
+CBR_RG_SX_DELCTRL_SZ	include/ssv6200_aux.h	10895;"	d
+CBR_RG_SX_DITHER_WEIGHT_HI	include/ssv6200_aux.h	10719;"	d
+CBR_RG_SX_DITHER_WEIGHT_I_MSK	include/ssv6200_aux.h	10717;"	d
+CBR_RG_SX_DITHER_WEIGHT_MSK	include/ssv6200_aux.h	10716;"	d
+CBR_RG_SX_DITHER_WEIGHT_SFT	include/ssv6200_aux.h	10718;"	d
+CBR_RG_SX_DITHER_WEIGHT_SZ	include/ssv6200_aux.h	10720;"	d
+CBR_RG_SX_DIVBFSEL_HI	include/ssv6200_aux.h	10709;"	d
+CBR_RG_SX_DIVBFSEL_I_MSK	include/ssv6200_aux.h	10707;"	d
+CBR_RG_SX_DIVBFSEL_MSK	include/ssv6200_aux.h	10706;"	d
+CBR_RG_SX_DIVBFSEL_SFT	include/ssv6200_aux.h	10708;"	d
+CBR_RG_SX_DIVBFSEL_SZ	include/ssv6200_aux.h	10710;"	d
+CBR_RG_SX_GNDR_SEL_HI	include/ssv6200_aux.h	10714;"	d
+CBR_RG_SX_GNDR_SEL_I_MSK	include/ssv6200_aux.h	10712;"	d
+CBR_RG_SX_GNDR_SEL_MSK	include/ssv6200_aux.h	10711;"	d
+CBR_RG_SX_GNDR_SEL_SFT	include/ssv6200_aux.h	10713;"	d
+CBR_RG_SX_GNDR_SEL_SZ	include/ssv6200_aux.h	10715;"	d
+CBR_RG_SX_LCKEN_HI	include/ssv6200_aux.h	10779;"	d
+CBR_RG_SX_LCKEN_I_MSK	include/ssv6200_aux.h	10777;"	d
+CBR_RG_SX_LCKEN_MSK	include/ssv6200_aux.h	10776;"	d
+CBR_RG_SX_LCKEN_SFT	include/ssv6200_aux.h	10778;"	d
+CBR_RG_SX_LCKEN_SZ	include/ssv6200_aux.h	10780;"	d
+CBR_RG_SX_LDO_CHP_LEVEL_HI	include/ssv6200_aux.h	9934;"	d
+CBR_RG_SX_LDO_CHP_LEVEL_I_MSK	include/ssv6200_aux.h	9932;"	d
+CBR_RG_SX_LDO_CHP_LEVEL_MSK	include/ssv6200_aux.h	9931;"	d
+CBR_RG_SX_LDO_CHP_LEVEL_SFT	include/ssv6200_aux.h	9933;"	d
+CBR_RG_SX_LDO_CHP_LEVEL_SZ	include/ssv6200_aux.h	9935;"	d
+CBR_RG_SX_LDO_LOBF_LEVEL_HI	include/ssv6200_aux.h	9939;"	d
+CBR_RG_SX_LDO_LOBF_LEVEL_I_MSK	include/ssv6200_aux.h	9937;"	d
+CBR_RG_SX_LDO_LOBF_LEVEL_MSK	include/ssv6200_aux.h	9936;"	d
+CBR_RG_SX_LDO_LOBF_LEVEL_SFT	include/ssv6200_aux.h	9938;"	d
+CBR_RG_SX_LDO_LOBF_LEVEL_SZ	include/ssv6200_aux.h	9940;"	d
+CBR_RG_SX_LDO_VCO_LEVEL_HI	include/ssv6200_aux.h	9954;"	d
+CBR_RG_SX_LDO_VCO_LEVEL_I_MSK	include/ssv6200_aux.h	9952;"	d
+CBR_RG_SX_LDO_VCO_LEVEL_MSK	include/ssv6200_aux.h	9951;"	d
+CBR_RG_SX_LDO_VCO_LEVEL_SFT	include/ssv6200_aux.h	9953;"	d
+CBR_RG_SX_LDO_VCO_LEVEL_SZ	include/ssv6200_aux.h	9955;"	d
+CBR_RG_SX_LDO_XOSC_LEVEL_HI	include/ssv6200_aux.h	9944;"	d
+CBR_RG_SX_LDO_XOSC_LEVEL_I_MSK	include/ssv6200_aux.h	9942;"	d
+CBR_RG_SX_LDO_XOSC_LEVEL_MSK	include/ssv6200_aux.h	9941;"	d
+CBR_RG_SX_LDO_XOSC_LEVEL_SFT	include/ssv6200_aux.h	9943;"	d
+CBR_RG_SX_LDO_XOSC_LEVEL_SZ	include/ssv6200_aux.h	9945;"	d
+CBR_RG_SX_MODDB_HI	include/ssv6200_aux.h	10799;"	d
+CBR_RG_SX_MODDB_I_MSK	include/ssv6200_aux.h	10797;"	d
+CBR_RG_SX_MODDB_MSK	include/ssv6200_aux.h	10796;"	d
+CBR_RG_SX_MODDB_SFT	include/ssv6200_aux.h	10798;"	d
+CBR_RG_SX_MODDB_SZ	include/ssv6200_aux.h	10800;"	d
+CBR_RG_SX_MOD_ERRCMP_HI	include/ssv6200_aux.h	10724;"	d
+CBR_RG_SX_MOD_ERRCMP_I_MSK	include/ssv6200_aux.h	10722;"	d
+CBR_RG_SX_MOD_ERRCMP_MSK	include/ssv6200_aux.h	10721;"	d
+CBR_RG_SX_MOD_ERRCMP_SFT	include/ssv6200_aux.h	10723;"	d
+CBR_RG_SX_MOD_ERRCMP_SZ	include/ssv6200_aux.h	10725;"	d
+CBR_RG_SX_MOD_ERR_DELAY_HI	include/ssv6200_aux.h	10794;"	d
+CBR_RG_SX_MOD_ERR_DELAY_I_MSK	include/ssv6200_aux.h	10792;"	d
+CBR_RG_SX_MOD_ERR_DELAY_MSK	include/ssv6200_aux.h	10791;"	d
+CBR_RG_SX_MOD_ERR_DELAY_SFT	include/ssv6200_aux.h	10793;"	d
+CBR_RG_SX_MOD_ERR_DELAY_SZ	include/ssv6200_aux.h	10795;"	d
+CBR_RG_SX_MOD_ORDER_HI	include/ssv6200_aux.h	10729;"	d
+CBR_RG_SX_MOD_ORDER_I_MSK	include/ssv6200_aux.h	10727;"	d
+CBR_RG_SX_MOD_ORDER_MSK	include/ssv6200_aux.h	10726;"	d
+CBR_RG_SX_MOD_ORDER_SFT	include/ssv6200_aux.h	10728;"	d
+CBR_RG_SX_MOD_ORDER_SZ	include/ssv6200_aux.h	10730;"	d
+CBR_RG_SX_PFDSEL_HI	include/ssv6200_aux.h	10634;"	d
+CBR_RG_SX_PFDSEL_I_MSK	include/ssv6200_aux.h	10632;"	d
+CBR_RG_SX_PFDSEL_MSK	include/ssv6200_aux.h	10631;"	d
+CBR_RG_SX_PFDSEL_SFT	include/ssv6200_aux.h	10633;"	d
+CBR_RG_SX_PFDSEL_SZ	include/ssv6200_aux.h	10635;"	d
+CBR_RG_SX_PFD_RST_H_HI	include/ssv6200_aux.h	10659;"	d
+CBR_RG_SX_PFD_RST_H_I_MSK	include/ssv6200_aux.h	10657;"	d
+CBR_RG_SX_PFD_RST_H_MSK	include/ssv6200_aux.h	10656;"	d
+CBR_RG_SX_PFD_RST_H_SFT	include/ssv6200_aux.h	10658;"	d
+CBR_RG_SX_PFD_RST_H_SZ	include/ssv6200_aux.h	10660;"	d
+CBR_RG_SX_PFD_SET1_HI	include/ssv6200_aux.h	10644;"	d
+CBR_RG_SX_PFD_SET1_I_MSK	include/ssv6200_aux.h	10642;"	d
+CBR_RG_SX_PFD_SET1_MSK	include/ssv6200_aux.h	10641;"	d
+CBR_RG_SX_PFD_SET1_SFT	include/ssv6200_aux.h	10643;"	d
+CBR_RG_SX_PFD_SET1_SZ	include/ssv6200_aux.h	10645;"	d
+CBR_RG_SX_PFD_SET2_HI	include/ssv6200_aux.h	10649;"	d
+CBR_RG_SX_PFD_SET2_I_MSK	include/ssv6200_aux.h	10647;"	d
+CBR_RG_SX_PFD_SET2_MSK	include/ssv6200_aux.h	10646;"	d
+CBR_RG_SX_PFD_SET2_SFT	include/ssv6200_aux.h	10648;"	d
+CBR_RG_SX_PFD_SET2_SZ	include/ssv6200_aux.h	10650;"	d
+CBR_RG_SX_PFD_SET_HI	include/ssv6200_aux.h	10639;"	d
+CBR_RG_SX_PFD_SET_I_MSK	include/ssv6200_aux.h	10637;"	d
+CBR_RG_SX_PFD_SET_MSK	include/ssv6200_aux.h	10636;"	d
+CBR_RG_SX_PFD_SET_SFT	include/ssv6200_aux.h	10638;"	d
+CBR_RG_SX_PFD_SET_SZ	include/ssv6200_aux.h	10640;"	d
+CBR_RG_SX_PFD_TRDN_HI	include/ssv6200_aux.h	10669;"	d
+CBR_RG_SX_PFD_TRDN_I_MSK	include/ssv6200_aux.h	10667;"	d
+CBR_RG_SX_PFD_TRDN_MSK	include/ssv6200_aux.h	10666;"	d
+CBR_RG_SX_PFD_TRDN_SFT	include/ssv6200_aux.h	10668;"	d
+CBR_RG_SX_PFD_TRDN_SZ	include/ssv6200_aux.h	10670;"	d
+CBR_RG_SX_PFD_TRSEL_HI	include/ssv6200_aux.h	10674;"	d
+CBR_RG_SX_PFD_TRSEL_I_MSK	include/ssv6200_aux.h	10672;"	d
+CBR_RG_SX_PFD_TRSEL_MSK	include/ssv6200_aux.h	10671;"	d
+CBR_RG_SX_PFD_TRSEL_SFT	include/ssv6200_aux.h	10673;"	d
+CBR_RG_SX_PFD_TRSEL_SZ	include/ssv6200_aux.h	10675;"	d
+CBR_RG_SX_PFD_TRUP_HI	include/ssv6200_aux.h	10664;"	d
+CBR_RG_SX_PFD_TRUP_I_MSK	include/ssv6200_aux.h	10662;"	d
+CBR_RG_SX_PFD_TRUP_MSK	include/ssv6200_aux.h	10661;"	d
+CBR_RG_SX_PFD_TRUP_SFT	include/ssv6200_aux.h	10663;"	d
+CBR_RG_SX_PFD_TRUP_SZ	include/ssv6200_aux.h	10665;"	d
+CBR_RG_SX_PH_HI	include/ssv6200_aux.h	10829;"	d
+CBR_RG_SX_PH_I_MSK	include/ssv6200_aux.h	10827;"	d
+CBR_RG_SX_PH_MSK	include/ssv6200_aux.h	10826;"	d
+CBR_RG_SX_PH_SFT	include/ssv6200_aux.h	10828;"	d
+CBR_RG_SX_PH_SZ	include/ssv6200_aux.h	10830;"	d
+CBR_RG_SX_PL_HI	include/ssv6200_aux.h	10834;"	d
+CBR_RG_SX_PL_I_MSK	include/ssv6200_aux.h	10832;"	d
+CBR_RG_SX_PL_MSK	include/ssv6200_aux.h	10831;"	d
+CBR_RG_SX_PL_SFT	include/ssv6200_aux.h	10833;"	d
+CBR_RG_SX_PL_SZ	include/ssv6200_aux.h	10835;"	d
+CBR_RG_SX_PREVDD_HI	include/ssv6200_aux.h	10784;"	d
+CBR_RG_SX_PREVDD_I_MSK	include/ssv6200_aux.h	10782;"	d
+CBR_RG_SX_PREVDD_MSK	include/ssv6200_aux.h	10781;"	d
+CBR_RG_SX_PREVDD_SFT	include/ssv6200_aux.h	10783;"	d
+CBR_RG_SX_PREVDD_SZ	include/ssv6200_aux.h	10785;"	d
+CBR_RG_SX_PSCONTERVDD_HI	include/ssv6200_aux.h	10789;"	d
+CBR_RG_SX_PSCONTERVDD_I_MSK	include/ssv6200_aux.h	10787;"	d
+CBR_RG_SX_PSCONTERVDD_MSK	include/ssv6200_aux.h	10786;"	d
+CBR_RG_SX_PSCONTERVDD_SFT	include/ssv6200_aux.h	10788;"	d
+CBR_RG_SX_PSCONTERVDD_SZ	include/ssv6200_aux.h	10790;"	d
+CBR_RG_SX_REFBYTWO_HI	include/ssv6200_aux.h	10764;"	d
+CBR_RG_SX_REFBYTWO_I_MSK	include/ssv6200_aux.h	10762;"	d
+CBR_RG_SX_REFBYTWO_MSK	include/ssv6200_aux.h	10761;"	d
+CBR_RG_SX_REFBYTWO_SFT	include/ssv6200_aux.h	10763;"	d
+CBR_RG_SX_REFBYTWO_SZ	include/ssv6200_aux.h	10765;"	d
+CBR_RG_SX_REF_CYCLE_HI	include/ssv6200_aux.h	10814;"	d
+CBR_RG_SX_REF_CYCLE_I_MSK	include/ssv6200_aux.h	10812;"	d
+CBR_RG_SX_REF_CYCLE_MSK	include/ssv6200_aux.h	10811;"	d
+CBR_RG_SX_REF_CYCLE_SFT	include/ssv6200_aux.h	10813;"	d
+CBR_RG_SX_REF_CYCLE_SZ	include/ssv6200_aux.h	10815;"	d
+CBR_RG_SX_RFCTRL_CH_HI	include/ssv6200_aux.h	10584;"	d
+CBR_RG_SX_RFCTRL_CH_I_MSK	include/ssv6200_aux.h	10582;"	d
+CBR_RG_SX_RFCTRL_CH_MSK	include/ssv6200_aux.h	10581;"	d
+CBR_RG_SX_RFCTRL_CH_SFT	include/ssv6200_aux.h	10583;"	d
+CBR_RG_SX_RFCTRL_CH_SZ	include/ssv6200_aux.h	10585;"	d
+CBR_RG_SX_RFCTRL_F_HI	include/ssv6200_aux.h	10569;"	d
+CBR_RG_SX_RFCTRL_F_I_MSK	include/ssv6200_aux.h	10567;"	d
+CBR_RG_SX_RFCTRL_F_MSK	include/ssv6200_aux.h	10566;"	d
+CBR_RG_SX_RFCTRL_F_SFT	include/ssv6200_aux.h	10568;"	d
+CBR_RG_SX_RFCTRL_F_SZ	include/ssv6200_aux.h	10570;"	d
+CBR_RG_SX_RST_H_DIV_HI	include/ssv6200_aux.h	10749;"	d
+CBR_RG_SX_RST_H_DIV_I_MSK	include/ssv6200_aux.h	10747;"	d
+CBR_RG_SX_RST_H_DIV_MSK	include/ssv6200_aux.h	10746;"	d
+CBR_RG_SX_RST_H_DIV_SFT	include/ssv6200_aux.h	10748;"	d
+CBR_RG_SX_RST_H_DIV_SZ	include/ssv6200_aux.h	10750;"	d
+CBR_RG_SX_RXBFSEL_HI	include/ssv6200_aux.h	10694;"	d
+CBR_RG_SX_RXBFSEL_I_MSK	include/ssv6200_aux.h	10692;"	d
+CBR_RG_SX_RXBFSEL_MSK	include/ssv6200_aux.h	10691;"	d
+CBR_RG_SX_RXBFSEL_SFT	include/ssv6200_aux.h	10693;"	d
+CBR_RG_SX_RXBFSEL_SZ	include/ssv6200_aux.h	10695;"	d
+CBR_RG_SX_SDMLUT_INV_HI	include/ssv6200_aux.h	10774;"	d
+CBR_RG_SX_SDMLUT_INV_I_MSK	include/ssv6200_aux.h	10772;"	d
+CBR_RG_SX_SDMLUT_INV_MSK	include/ssv6200_aux.h	10771;"	d
+CBR_RG_SX_SDMLUT_INV_SFT	include/ssv6200_aux.h	10773;"	d
+CBR_RG_SX_SDMLUT_INV_SZ	include/ssv6200_aux.h	10775;"	d
+CBR_RG_SX_SDM_D1_HI	include/ssv6200_aux.h	10734;"	d
+CBR_RG_SX_SDM_D1_I_MSK	include/ssv6200_aux.h	10732;"	d
+CBR_RG_SX_SDM_D1_MSK	include/ssv6200_aux.h	10731;"	d
+CBR_RG_SX_SDM_D1_SFT	include/ssv6200_aux.h	10733;"	d
+CBR_RG_SX_SDM_D1_SZ	include/ssv6200_aux.h	10735;"	d
+CBR_RG_SX_SDM_D2_HI	include/ssv6200_aux.h	10739;"	d
+CBR_RG_SX_SDM_D2_I_MSK	include/ssv6200_aux.h	10737;"	d
+CBR_RG_SX_SDM_D2_MSK	include/ssv6200_aux.h	10736;"	d
+CBR_RG_SX_SDM_D2_SFT	include/ssv6200_aux.h	10738;"	d
+CBR_RG_SX_SDM_D2_SZ	include/ssv6200_aux.h	10740;"	d
+CBR_RG_SX_SDM_EDGE_HI	include/ssv6200_aux.h	10754;"	d
+CBR_RG_SX_SDM_EDGE_I_MSK	include/ssv6200_aux.h	10752;"	d
+CBR_RG_SX_SDM_EDGE_MSK	include/ssv6200_aux.h	10751;"	d
+CBR_RG_SX_SDM_EDGE_SFT	include/ssv6200_aux.h	10753;"	d
+CBR_RG_SX_SDM_EDGE_SZ	include/ssv6200_aux.h	10755;"	d
+CBR_RG_SX_SEL_C3_HI	include/ssv6200_aux.h	10589;"	d
+CBR_RG_SX_SEL_C3_I_MSK	include/ssv6200_aux.h	10587;"	d
+CBR_RG_SX_SEL_C3_MSK	include/ssv6200_aux.h	10586;"	d
+CBR_RG_SX_SEL_C3_SFT	include/ssv6200_aux.h	10588;"	d
+CBR_RG_SX_SEL_C3_SZ	include/ssv6200_aux.h	10590;"	d
+CBR_RG_SX_SEL_CHP_REGOP_HI	include/ssv6200_aux.h	10614;"	d
+CBR_RG_SX_SEL_CHP_REGOP_I_MSK	include/ssv6200_aux.h	10612;"	d
+CBR_RG_SX_SEL_CHP_REGOP_MSK	include/ssv6200_aux.h	10611;"	d
+CBR_RG_SX_SEL_CHP_REGOP_SFT	include/ssv6200_aux.h	10613;"	d
+CBR_RG_SX_SEL_CHP_REGOP_SZ	include/ssv6200_aux.h	10615;"	d
+CBR_RG_SX_SEL_CHP_UNIOP_HI	include/ssv6200_aux.h	10619;"	d
+CBR_RG_SX_SEL_CHP_UNIOP_I_MSK	include/ssv6200_aux.h	10617;"	d
+CBR_RG_SX_SEL_CHP_UNIOP_MSK	include/ssv6200_aux.h	10616;"	d
+CBR_RG_SX_SEL_CHP_UNIOP_SFT	include/ssv6200_aux.h	10618;"	d
+CBR_RG_SX_SEL_CHP_UNIOP_SZ	include/ssv6200_aux.h	10620;"	d
+CBR_RG_SX_SEL_CP_HI	include/ssv6200_aux.h	10574;"	d
+CBR_RG_SX_SEL_CP_I_MSK	include/ssv6200_aux.h	10572;"	d
+CBR_RG_SX_SEL_CP_MSK	include/ssv6200_aux.h	10571;"	d
+CBR_RG_SX_SEL_CP_SFT	include/ssv6200_aux.h	10573;"	d
+CBR_RG_SX_SEL_CP_SZ	include/ssv6200_aux.h	10575;"	d
+CBR_RG_SX_SEL_CS_HI	include/ssv6200_aux.h	10579;"	d
+CBR_RG_SX_SEL_CS_I_MSK	include/ssv6200_aux.h	10577;"	d
+CBR_RG_SX_SEL_CS_MSK	include/ssv6200_aux.h	10576;"	d
+CBR_RG_SX_SEL_CS_SFT	include/ssv6200_aux.h	10578;"	d
+CBR_RG_SX_SEL_CS_SZ	include/ssv6200_aux.h	10580;"	d
+CBR_RG_SX_SEL_DELAY_HI	include/ssv6200_aux.h	10809;"	d
+CBR_RG_SX_SEL_DELAY_I_MSK	include/ssv6200_aux.h	10807;"	d
+CBR_RG_SX_SEL_DELAY_MSK	include/ssv6200_aux.h	10806;"	d
+CBR_RG_SX_SEL_DELAY_SFT	include/ssv6200_aux.h	10808;"	d
+CBR_RG_SX_SEL_DELAY_SZ	include/ssv6200_aux.h	10810;"	d
+CBR_RG_SX_SEL_ICHP_HI	include/ssv6200_aux.h	10604;"	d
+CBR_RG_SX_SEL_ICHP_I_MSK	include/ssv6200_aux.h	10602;"	d
+CBR_RG_SX_SEL_ICHP_MSK	include/ssv6200_aux.h	10601;"	d
+CBR_RG_SX_SEL_ICHP_SFT	include/ssv6200_aux.h	10603;"	d
+CBR_RG_SX_SEL_ICHP_SZ	include/ssv6200_aux.h	10605;"	d
+CBR_RG_SX_SEL_PCHP_HI	include/ssv6200_aux.h	10609;"	d
+CBR_RG_SX_SEL_PCHP_I_MSK	include/ssv6200_aux.h	10607;"	d
+CBR_RG_SX_SEL_PCHP_MSK	include/ssv6200_aux.h	10606;"	d
+CBR_RG_SX_SEL_PCHP_SFT	include/ssv6200_aux.h	10608;"	d
+CBR_RG_SX_SEL_PCHP_SZ	include/ssv6200_aux.h	10610;"	d
+CBR_RG_SX_SEL_R3_HI	include/ssv6200_aux.h	10599;"	d
+CBR_RG_SX_SEL_R3_I_MSK	include/ssv6200_aux.h	10597;"	d
+CBR_RG_SX_SEL_R3_MSK	include/ssv6200_aux.h	10596;"	d
+CBR_RG_SX_SEL_R3_SFT	include/ssv6200_aux.h	10598;"	d
+CBR_RG_SX_SEL_R3_SZ	include/ssv6200_aux.h	10600;"	d
+CBR_RG_SX_SEL_RS_HI	include/ssv6200_aux.h	10594;"	d
+CBR_RG_SX_SEL_RS_I_MSK	include/ssv6200_aux.h	10592;"	d
+CBR_RG_SX_SEL_RS_MSK	include/ssv6200_aux.h	10591;"	d
+CBR_RG_SX_SEL_RS_SFT	include/ssv6200_aux.h	10593;"	d
+CBR_RG_SX_SEL_RS_SZ	include/ssv6200_aux.h	10595;"	d
+CBR_RG_SX_SUB_SEL_CWD_HI	include/ssv6200_aux.h	11169;"	d
+CBR_RG_SX_SUB_SEL_CWD_I_MSK	include/ssv6200_aux.h	11167;"	d
+CBR_RG_SX_SUB_SEL_CWD_MSK	include/ssv6200_aux.h	11166;"	d
+CBR_RG_SX_SUB_SEL_CWD_SFT	include/ssv6200_aux.h	11168;"	d
+CBR_RG_SX_SUB_SEL_CWD_SZ	include/ssv6200_aux.h	11170;"	d
+CBR_RG_SX_SUB_SEL_CWR_HI	include/ssv6200_aux.h	11164;"	d
+CBR_RG_SX_SUB_SEL_CWR_I_MSK	include/ssv6200_aux.h	11162;"	d
+CBR_RG_SX_SUB_SEL_CWR_MSK	include/ssv6200_aux.h	11161;"	d
+CBR_RG_SX_SUB_SEL_CWR_SFT	include/ssv6200_aux.h	11163;"	d
+CBR_RG_SX_SUB_SEL_CWR_SZ	include/ssv6200_aux.h	11165;"	d
+CBR_RG_SX_TXBFSEL_HI	include/ssv6200_aux.h	10699;"	d
+CBR_RG_SX_TXBFSEL_I_MSK	include/ssv6200_aux.h	10697;"	d
+CBR_RG_SX_TXBFSEL_MSK	include/ssv6200_aux.h	10696;"	d
+CBR_RG_SX_TXBFSEL_SFT	include/ssv6200_aux.h	10698;"	d
+CBR_RG_SX_TXBFSEL_SZ	include/ssv6200_aux.h	10700;"	d
+CBR_RG_SX_VBNCAS_SEL_HI	include/ssv6200_aux.h	10654;"	d
+CBR_RG_SX_VBNCAS_SEL_I_MSK	include/ssv6200_aux.h	10652;"	d
+CBR_RG_SX_VBNCAS_SEL_MSK	include/ssv6200_aux.h	10651;"	d
+CBR_RG_SX_VBNCAS_SEL_SFT	include/ssv6200_aux.h	10653;"	d
+CBR_RG_SX_VBNCAS_SEL_SZ	include/ssv6200_aux.h	10655;"	d
+CBR_RG_SX_VCOBA_R_HI	include/ssv6200_aux.h	10679;"	d
+CBR_RG_SX_VCOBA_R_I_MSK	include/ssv6200_aux.h	10677;"	d
+CBR_RG_SX_VCOBA_R_MSK	include/ssv6200_aux.h	10676;"	d
+CBR_RG_SX_VCOBA_R_SFT	include/ssv6200_aux.h	10678;"	d
+CBR_RG_SX_VCOBA_R_SZ	include/ssv6200_aux.h	10680;"	d
+CBR_RG_SX_VCOBFSEL_HI	include/ssv6200_aux.h	10704;"	d
+CBR_RG_SX_VCOBFSEL_I_MSK	include/ssv6200_aux.h	10702;"	d
+CBR_RG_SX_VCOBFSEL_MSK	include/ssv6200_aux.h	10701;"	d
+CBR_RG_SX_VCOBFSEL_SFT	include/ssv6200_aux.h	10703;"	d
+CBR_RG_SX_VCOBFSEL_SZ	include/ssv6200_aux.h	10705;"	d
+CBR_RG_SX_VCOBY16_HI	include/ssv6200_aux.h	10819;"	d
+CBR_RG_SX_VCOBY16_I_MSK	include/ssv6200_aux.h	10817;"	d
+CBR_RG_SX_VCOBY16_MSK	include/ssv6200_aux.h	10816;"	d
+CBR_RG_SX_VCOBY16_SFT	include/ssv6200_aux.h	10818;"	d
+CBR_RG_SX_VCOBY16_SZ	include/ssv6200_aux.h	10820;"	d
+CBR_RG_SX_VCOBY32_HI	include/ssv6200_aux.h	10824;"	d
+CBR_RG_SX_VCOBY32_I_MSK	include/ssv6200_aux.h	10822;"	d
+CBR_RG_SX_VCOBY32_MSK	include/ssv6200_aux.h	10821;"	d
+CBR_RG_SX_VCOBY32_SFT	include/ssv6200_aux.h	10823;"	d
+CBR_RG_SX_VCOBY32_SZ	include/ssv6200_aux.h	10825;"	d
+CBR_RG_SX_VCOCUSEL_HI	include/ssv6200_aux.h	10689;"	d
+CBR_RG_SX_VCOCUSEL_I_MSK	include/ssv6200_aux.h	10687;"	d
+CBR_RG_SX_VCOCUSEL_MSK	include/ssv6200_aux.h	10686;"	d
+CBR_RG_SX_VCOCUSEL_SFT	include/ssv6200_aux.h	10688;"	d
+CBR_RG_SX_VCOCUSEL_SZ	include/ssv6200_aux.h	10690;"	d
+CBR_RG_SX_VCORSEL_HI	include/ssv6200_aux.h	10684;"	d
+CBR_RG_SX_VCORSEL_I_MSK	include/ssv6200_aux.h	10682;"	d
+CBR_RG_SX_VCORSEL_MSK	include/ssv6200_aux.h	10681;"	d
+CBR_RG_SX_VCORSEL_SFT	include/ssv6200_aux.h	10683;"	d
+CBR_RG_SX_VCORSEL_SZ	include/ssv6200_aux.h	10685;"	d
+CBR_RG_SX_VT_MON_MODE_HI	include/ssv6200_aux.h	10839;"	d
+CBR_RG_SX_VT_MON_MODE_I_MSK	include/ssv6200_aux.h	10837;"	d
+CBR_RG_SX_VT_MON_MODE_MSK	include/ssv6200_aux.h	10836;"	d
+CBR_RG_SX_VT_MON_MODE_SFT	include/ssv6200_aux.h	10838;"	d
+CBR_RG_SX_VT_MON_MODE_SZ	include/ssv6200_aux.h	10840;"	d
+CBR_RG_SX_VT_MON_TMR_HI	include/ssv6200_aux.h	10859;"	d
+CBR_RG_SX_VT_MON_TMR_I_MSK	include/ssv6200_aux.h	10857;"	d
+CBR_RG_SX_VT_MON_TMR_MSK	include/ssv6200_aux.h	10856;"	d
+CBR_RG_SX_VT_MON_TMR_SFT	include/ssv6200_aux.h	10858;"	d
+CBR_RG_SX_VT_MON_TMR_SZ	include/ssv6200_aux.h	10860;"	d
+CBR_RG_SX_VT_SET_HI	include/ssv6200_aux.h	10854;"	d
+CBR_RG_SX_VT_SET_I_MSK	include/ssv6200_aux.h	10852;"	d
+CBR_RG_SX_VT_SET_MSK	include/ssv6200_aux.h	10851;"	d
+CBR_RG_SX_VT_SET_SFT	include/ssv6200_aux.h	10853;"	d
+CBR_RG_SX_VT_SET_SZ	include/ssv6200_aux.h	10855;"	d
+CBR_RG_SX_VT_TH_HI_HI	include/ssv6200_aux.h	10844;"	d
+CBR_RG_SX_VT_TH_HI_I_MSK	include/ssv6200_aux.h	10842;"	d
+CBR_RG_SX_VT_TH_HI_MSK	include/ssv6200_aux.h	10841;"	d
+CBR_RG_SX_VT_TH_HI_SFT	include/ssv6200_aux.h	10843;"	d
+CBR_RG_SX_VT_TH_HI_SZ	include/ssv6200_aux.h	10845;"	d
+CBR_RG_SX_VT_TH_LO_HI	include/ssv6200_aux.h	10849;"	d
+CBR_RG_SX_VT_TH_LO_I_MSK	include/ssv6200_aux.h	10847;"	d
+CBR_RG_SX_VT_TH_LO_MSK	include/ssv6200_aux.h	10846;"	d
+CBR_RG_SX_VT_TH_LO_SFT	include/ssv6200_aux.h	10848;"	d
+CBR_RG_SX_VT_TH_LO_SZ	include/ssv6200_aux.h	10850;"	d
+CBR_RG_SX_XO_GM_HI	include/ssv6200_aux.h	10759;"	d
+CBR_RG_SX_XO_GM_I_MSK	include/ssv6200_aux.h	10757;"	d
+CBR_RG_SX_XO_GM_MSK	include/ssv6200_aux.h	10756;"	d
+CBR_RG_SX_XO_GM_SFT	include/ssv6200_aux.h	10758;"	d
+CBR_RG_SX_XO_GM_SZ	include/ssv6200_aux.h	10760;"	d
+CBR_RG_SX_XO_SWCAP_HI	include/ssv6200_aux.h	10769;"	d
+CBR_RG_SX_XO_SWCAP_I_MSK	include/ssv6200_aux.h	10767;"	d
+CBR_RG_SX_XO_SWCAP_MSK	include/ssv6200_aux.h	10766;"	d
+CBR_RG_SX_XO_SWCAP_SFT	include/ssv6200_aux.h	10768;"	d
+CBR_RG_SX_XO_SWCAP_SZ	include/ssv6200_aux.h	10770;"	d
+CBR_RG_TXLPF_BOOSTI_HI	include/ssv6200_aux.h	10489;"	d
+CBR_RG_TXLPF_BOOSTI_I_MSK	include/ssv6200_aux.h	10487;"	d
+CBR_RG_TXLPF_BOOSTI_MSK	include/ssv6200_aux.h	10486;"	d
+CBR_RG_TXLPF_BOOSTI_SFT	include/ssv6200_aux.h	10488;"	d
+CBR_RG_TXLPF_BOOSTI_SZ	include/ssv6200_aux.h	10490;"	d
+CBR_RG_TXLPF_BYPASS_HI	include/ssv6200_aux.h	10484;"	d
+CBR_RG_TXLPF_BYPASS_I_MSK	include/ssv6200_aux.h	10482;"	d
+CBR_RG_TXLPF_BYPASS_MSK	include/ssv6200_aux.h	10481;"	d
+CBR_RG_TXLPF_BYPASS_SFT	include/ssv6200_aux.h	10483;"	d
+CBR_RG_TXLPF_BYPASS_SZ	include/ssv6200_aux.h	10485;"	d
+CBR_RG_TXLPF_GMCELL_HI	include/ssv6200_aux.h	10144;"	d
+CBR_RG_TXLPF_GMCELL_I_MSK	include/ssv6200_aux.h	10142;"	d
+CBR_RG_TXLPF_GMCELL_MSK	include/ssv6200_aux.h	10141;"	d
+CBR_RG_TXLPF_GMCELL_SFT	include/ssv6200_aux.h	10143;"	d
+CBR_RG_TXLPF_GMCELL_SZ	include/ssv6200_aux.h	10145;"	d
+CBR_RG_TXMOD_GMCELL_HI	include/ssv6200_aux.h	10139;"	d
+CBR_RG_TXMOD_GMCELL_I_MSK	include/ssv6200_aux.h	10137;"	d
+CBR_RG_TXMOD_GMCELL_MSK	include/ssv6200_aux.h	10136;"	d
+CBR_RG_TXMOD_GMCELL_SFT	include/ssv6200_aux.h	10138;"	d
+CBR_RG_TXMOD_GMCELL_SZ	include/ssv6200_aux.h	10140;"	d
+CBR_RG_TXPGA_CAPSW_HI	include/ssv6200_aux.h	10124;"	d
+CBR_RG_TXPGA_CAPSW_I_MSK	include/ssv6200_aux.h	10122;"	d
+CBR_RG_TXPGA_CAPSW_MSK	include/ssv6200_aux.h	10121;"	d
+CBR_RG_TXPGA_CAPSW_SFT	include/ssv6200_aux.h	10123;"	d
+CBR_RG_TXPGA_CAPSW_SZ	include/ssv6200_aux.h	10125;"	d
+CBR_RG_TXPGA_MAIN_HI	include/ssv6200_aux.h	10129;"	d
+CBR_RG_TXPGA_MAIN_I_MSK	include/ssv6200_aux.h	10127;"	d
+CBR_RG_TXPGA_MAIN_MSK	include/ssv6200_aux.h	10126;"	d
+CBR_RG_TXPGA_MAIN_SFT	include/ssv6200_aux.h	10128;"	d
+CBR_RG_TXPGA_MAIN_SZ	include/ssv6200_aux.h	10130;"	d
+CBR_RG_TXPGA_STEER_HI	include/ssv6200_aux.h	10134;"	d
+CBR_RG_TXPGA_STEER_I_MSK	include/ssv6200_aux.h	10132;"	d
+CBR_RG_TXPGA_STEER_MSK	include/ssv6200_aux.h	10131;"	d
+CBR_RG_TXPGA_STEER_SFT	include/ssv6200_aux.h	10133;"	d
+CBR_RG_TXPGA_STEER_SZ	include/ssv6200_aux.h	10135;"	d
+CBR_RG_TX_DACLPF_ICOURSE_HI	include/ssv6200_aux.h	10439;"	d
+CBR_RG_TX_DACLPF_ICOURSE_I_MSK	include/ssv6200_aux.h	10437;"	d
+CBR_RG_TX_DACLPF_ICOURSE_MSK	include/ssv6200_aux.h	10436;"	d
+CBR_RG_TX_DACLPF_ICOURSE_SFT	include/ssv6200_aux.h	10438;"	d
+CBR_RG_TX_DACLPF_ICOURSE_SZ	include/ssv6200_aux.h	10440;"	d
+CBR_RG_TX_DACLPF_IFINE_HI	include/ssv6200_aux.h	10444;"	d
+CBR_RG_TX_DACLPF_IFINE_I_MSK	include/ssv6200_aux.h	10442;"	d
+CBR_RG_TX_DACLPF_IFINE_MSK	include/ssv6200_aux.h	10441;"	d
+CBR_RG_TX_DACLPF_IFINE_SFT	include/ssv6200_aux.h	10443;"	d
+CBR_RG_TX_DACLPF_IFINE_SZ	include/ssv6200_aux.h	10445;"	d
+CBR_RG_TX_DACLPF_VCM_HI	include/ssv6200_aux.h	10449;"	d
+CBR_RG_TX_DACLPF_VCM_I_MSK	include/ssv6200_aux.h	10447;"	d
+CBR_RG_TX_DACLPF_VCM_MSK	include/ssv6200_aux.h	10446;"	d
+CBR_RG_TX_DACLPF_VCM_SFT	include/ssv6200_aux.h	10448;"	d
+CBR_RG_TX_DACLPF_VCM_SZ	include/ssv6200_aux.h	10450;"	d
+CBR_RG_TX_DAC_CKEDGE_SEL_HI	include/ssv6200_aux.h	10454;"	d
+CBR_RG_TX_DAC_CKEDGE_SEL_I_MSK	include/ssv6200_aux.h	10452;"	d
+CBR_RG_TX_DAC_CKEDGE_SEL_MSK	include/ssv6200_aux.h	10451;"	d
+CBR_RG_TX_DAC_CKEDGE_SEL_SFT	include/ssv6200_aux.h	10453;"	d
+CBR_RG_TX_DAC_CKEDGE_SEL_SZ	include/ssv6200_aux.h	10455;"	d
+CBR_RG_TX_DAC_EN_HI	include/ssv6200_aux.h	9739;"	d
+CBR_RG_TX_DAC_EN_I_MSK	include/ssv6200_aux.h	9737;"	d
+CBR_RG_TX_DAC_EN_MSK	include/ssv6200_aux.h	9736;"	d
+CBR_RG_TX_DAC_EN_SFT	include/ssv6200_aux.h	9738;"	d
+CBR_RG_TX_DAC_EN_SZ	include/ssv6200_aux.h	9740;"	d
+CBR_RG_TX_DAC_IBIAS_HI	include/ssv6200_aux.h	10459;"	d
+CBR_RG_TX_DAC_IBIAS_I_MSK	include/ssv6200_aux.h	10457;"	d
+CBR_RG_TX_DAC_IBIAS_MSK	include/ssv6200_aux.h	10456;"	d
+CBR_RG_TX_DAC_IBIAS_SFT	include/ssv6200_aux.h	10458;"	d
+CBR_RG_TX_DAC_IBIAS_SZ	include/ssv6200_aux.h	10460;"	d
+CBR_RG_TX_DAC_OS_HI	include/ssv6200_aux.h	10464;"	d
+CBR_RG_TX_DAC_OS_I_MSK	include/ssv6200_aux.h	10462;"	d
+CBR_RG_TX_DAC_OS_MSK	include/ssv6200_aux.h	10461;"	d
+CBR_RG_TX_DAC_OS_SFT	include/ssv6200_aux.h	10463;"	d
+CBR_RG_TX_DAC_OS_SZ	include/ssv6200_aux.h	10465;"	d
+CBR_RG_TX_DAC_RCAL_HI	include/ssv6200_aux.h	10469;"	d
+CBR_RG_TX_DAC_RCAL_I_MSK	include/ssv6200_aux.h	10467;"	d
+CBR_RG_TX_DAC_RCAL_MSK	include/ssv6200_aux.h	10466;"	d
+CBR_RG_TX_DAC_RCAL_SFT	include/ssv6200_aux.h	10468;"	d
+CBR_RG_TX_DAC_RCAL_SZ	include/ssv6200_aux.h	10470;"	d
+CBR_RG_TX_DAC_TSEL_HI	include/ssv6200_aux.h	10474;"	d
+CBR_RG_TX_DAC_TSEL_I_MSK	include/ssv6200_aux.h	10472;"	d
+CBR_RG_TX_DAC_TSEL_MSK	include/ssv6200_aux.h	10471;"	d
+CBR_RG_TX_DAC_TSEL_SFT	include/ssv6200_aux.h	10473;"	d
+CBR_RG_TX_DAC_TSEL_SZ	include/ssv6200_aux.h	10475;"	d
+CBR_RG_TX_DIV_VSET_HI	include/ssv6200_aux.h	10164;"	d
+CBR_RG_TX_DIV_VSET_I_MSK	include/ssv6200_aux.h	10162;"	d
+CBR_RG_TX_DIV_VSET_MSK	include/ssv6200_aux.h	10161;"	d
+CBR_RG_TX_DIV_VSET_SFT	include/ssv6200_aux.h	10163;"	d
+CBR_RG_TX_DIV_VSET_SZ	include/ssv6200_aux.h	10165;"	d
+CBR_RG_TX_DPDGM_BIAS_HI	include/ssv6200_aux.h	10189;"	d
+CBR_RG_TX_DPDGM_BIAS_I_MSK	include/ssv6200_aux.h	10187;"	d
+CBR_RG_TX_DPDGM_BIAS_MSK	include/ssv6200_aux.h	10186;"	d
+CBR_RG_TX_DPDGM_BIAS_SFT	include/ssv6200_aux.h	10188;"	d
+CBR_RG_TX_DPDGM_BIAS_SZ	include/ssv6200_aux.h	10190;"	d
+CBR_RG_TX_DPD_DIV_HI	include/ssv6200_aux.h	10194;"	d
+CBR_RG_TX_DPD_DIV_I_MSK	include/ssv6200_aux.h	10192;"	d
+CBR_RG_TX_DPD_DIV_MSK	include/ssv6200_aux.h	10191;"	d
+CBR_RG_TX_DPD_DIV_SFT	include/ssv6200_aux.h	10193;"	d
+CBR_RG_TX_DPD_DIV_SZ	include/ssv6200_aux.h	10195;"	d
+CBR_RG_TX_EN_HI	include/ssv6200_aux.h	9729;"	d
+CBR_RG_TX_EN_I_MSK	include/ssv6200_aux.h	9727;"	d
+CBR_RG_TX_EN_MSK	include/ssv6200_aux.h	9726;"	d
+CBR_RG_TX_EN_SFT	include/ssv6200_aux.h	9728;"	d
+CBR_RG_TX_EN_SZ	include/ssv6200_aux.h	9730;"	d
+CBR_RG_TX_EN_VOLTAGE_IN_HI	include/ssv6200_aux.h	10479;"	d
+CBR_RG_TX_EN_VOLTAGE_IN_I_MSK	include/ssv6200_aux.h	10477;"	d
+CBR_RG_TX_EN_VOLTAGE_IN_MSK	include/ssv6200_aux.h	10476;"	d
+CBR_RG_TX_EN_VOLTAGE_IN_SFT	include/ssv6200_aux.h	10478;"	d
+CBR_RG_TX_EN_VOLTAGE_IN_SZ	include/ssv6200_aux.h	10480;"	d
+CBR_RG_TX_LDO_TX_LEVEL_HI	include/ssv6200_aux.h	9959;"	d
+CBR_RG_TX_LDO_TX_LEVEL_I_MSK	include/ssv6200_aux.h	9957;"	d
+CBR_RG_TX_LDO_TX_LEVEL_MSK	include/ssv6200_aux.h	9956;"	d
+CBR_RG_TX_LDO_TX_LEVEL_SFT	include/ssv6200_aux.h	9958;"	d
+CBR_RG_TX_LDO_TX_LEVEL_SZ	include/ssv6200_aux.h	9960;"	d
+CBR_RG_TX_LOBUF_VSET_HI	include/ssv6200_aux.h	10169;"	d
+CBR_RG_TX_LOBUF_VSET_I_MSK	include/ssv6200_aux.h	10167;"	d
+CBR_RG_TX_LOBUF_VSET_MSK	include/ssv6200_aux.h	10166;"	d
+CBR_RG_TX_LOBUF_VSET_SFT	include/ssv6200_aux.h	10168;"	d
+CBR_RG_TX_LOBUF_VSET_SZ	include/ssv6200_aux.h	10170;"	d
+CBR_RG_TX_PA_EN_HI	include/ssv6200_aux.h	9734;"	d
+CBR_RG_TX_PA_EN_I_MSK	include/ssv6200_aux.h	9732;"	d
+CBR_RG_TX_PA_EN_MSK	include/ssv6200_aux.h	9731;"	d
+CBR_RG_TX_PA_EN_SFT	include/ssv6200_aux.h	9733;"	d
+CBR_RG_TX_PA_EN_SZ	include/ssv6200_aux.h	9735;"	d
+CBR_RG_TX_TSSI_BIAS_HI	include/ssv6200_aux.h	10199;"	d
+CBR_RG_TX_TSSI_BIAS_I_MSK	include/ssv6200_aux.h	10197;"	d
+CBR_RG_TX_TSSI_BIAS_MSK	include/ssv6200_aux.h	10196;"	d
+CBR_RG_TX_TSSI_BIAS_SFT	include/ssv6200_aux.h	10198;"	d
+CBR_RG_TX_TSSI_BIAS_SZ	include/ssv6200_aux.h	10200;"	d
+CBR_RG_TX_TSSI_DIV_HI	include/ssv6200_aux.h	10204;"	d
+CBR_RG_TX_TSSI_DIV_I_MSK	include/ssv6200_aux.h	10202;"	d
+CBR_RG_TX_TSSI_DIV_MSK	include/ssv6200_aux.h	10201;"	d
+CBR_RG_TX_TSSI_DIV_SFT	include/ssv6200_aux.h	10203;"	d
+CBR_RG_TX_TSSI_DIV_SZ	include/ssv6200_aux.h	10205;"	d
+CBR_RG_TX_TSSI_TESTMODE_HI	include/ssv6200_aux.h	10209;"	d
+CBR_RG_TX_TSSI_TESTMODE_I_MSK	include/ssv6200_aux.h	10207;"	d
+CBR_RG_TX_TSSI_TESTMODE_MSK	include/ssv6200_aux.h	10206;"	d
+CBR_RG_TX_TSSI_TESTMODE_SFT	include/ssv6200_aux.h	10208;"	d
+CBR_RG_TX_TSSI_TESTMODE_SZ	include/ssv6200_aux.h	10210;"	d
+CBR_RG_TX_TSSI_TEST_HI	include/ssv6200_aux.h	10214;"	d
+CBR_RG_TX_TSSI_TEST_I_MSK	include/ssv6200_aux.h	10212;"	d
+CBR_RG_TX_TSSI_TEST_MSK	include/ssv6200_aux.h	10211;"	d
+CBR_RG_TX_TSSI_TEST_SFT	include/ssv6200_aux.h	10213;"	d
+CBR_RG_TX_TSSI_TEST_SZ	include/ssv6200_aux.h	10215;"	d
+CBR_SEL_ADCKP_INV_HI	include/ssv6200_aux.h	11304;"	d
+CBR_SEL_ADCKP_INV_I_MSK	include/ssv6200_aux.h	11302;"	d
+CBR_SEL_ADCKP_INV_MSK	include/ssv6200_aux.h	11301;"	d
+CBR_SEL_ADCKP_INV_SFT	include/ssv6200_aux.h	11303;"	d
+CBR_SEL_ADCKP_INV_SZ	include/ssv6200_aux.h	11305;"	d
+CBR_SEL_ADCKP_MUX_HI	include/ssv6200_aux.h	11314;"	d
+CBR_SEL_ADCKP_MUX_I_MSK	include/ssv6200_aux.h	11312;"	d
+CBR_SEL_ADCKP_MUX_MSK	include/ssv6200_aux.h	11311;"	d
+CBR_SEL_ADCKP_MUX_SFT	include/ssv6200_aux.h	11313;"	d
+CBR_SEL_ADCKP_MUX_SZ	include/ssv6200_aux.h	11315;"	d
+CBR_TAIL_TIME_HI	include/ssv6200_aux.h	11289;"	d
+CBR_TAIL_TIME_I_MSK	include/ssv6200_aux.h	11287;"	d
+CBR_TAIL_TIME_MSK	include/ssv6200_aux.h	11286;"	d
+CBR_TAIL_TIME_SFT	include/ssv6200_aux.h	11288;"	d
+CBR_TAIL_TIME_SZ	include/ssv6200_aux.h	11290;"	d
+CBR_TC_CNT_TARGET_HI	include/ssv6200_aux.h	11264;"	d
+CBR_TC_CNT_TARGET_I_MSK	include/ssv6200_aux.h	11262;"	d
+CBR_TC_CNT_TARGET_MSK	include/ssv6200_aux.h	11261;"	d
+CBR_TC_CNT_TARGET_SFT	include/ssv6200_aux.h	11263;"	d
+CBR_TC_CNT_TARGET_SZ	include/ssv6200_aux.h	11265;"	d
+CBR_TP_SEL_HI	include/ssv6200_aux.h	11359;"	d
+CBR_TP_SEL_I_MSK	include/ssv6200_aux.h	11357;"	d
+CBR_TP_SEL_MSK	include/ssv6200_aux.h	11356;"	d
+CBR_TP_SEL_SFT	include/ssv6200_aux.h	11358;"	d
+CBR_TP_SEL_SZ	include/ssv6200_aux.h	11360;"	d
+CBR_TWO_TONE_EN_HI	include/ssv6200_aux.h	11374;"	d
+CBR_TWO_TONE_EN_I_MSK	include/ssv6200_aux.h	11372;"	d
+CBR_TWO_TONE_EN_MSK	include/ssv6200_aux.h	11371;"	d
+CBR_TWO_TONE_EN_SFT	include/ssv6200_aux.h	11373;"	d
+CBR_TWO_TONE_EN_SZ	include/ssv6200_aux.h	11375;"	d
+CBR_TX_CNT_RST_HI	include/ssv6200_aux.h	11244;"	d
+CBR_TX_CNT_RST_I_MSK	include/ssv6200_aux.h	11242;"	d
+CBR_TX_CNT_RST_MSK	include/ssv6200_aux.h	11241;"	d
+CBR_TX_CNT_RST_SFT	include/ssv6200_aux.h	11243;"	d
+CBR_TX_CNT_RST_SZ	include/ssv6200_aux.h	11245;"	d
+CBR_TX_CNT_TARGET_HI	include/ssv6200_aux.h	11259;"	d
+CBR_TX_CNT_TARGET_I_MSK	include/ssv6200_aux.h	11257;"	d
+CBR_TX_CNT_TARGET_MSK	include/ssv6200_aux.h	11256;"	d
+CBR_TX_CNT_TARGET_SFT	include/ssv6200_aux.h	11258;"	d
+CBR_TX_CNT_TARGET_SZ	include/ssv6200_aux.h	11260;"	d
+CBR_TX_EN_HI	include/ssv6200_aux.h	11239;"	d
+CBR_TX_EN_I_MSK	include/ssv6200_aux.h	11237;"	d
+CBR_TX_EN_MSK	include/ssv6200_aux.h	11236;"	d
+CBR_TX_EN_SFT	include/ssv6200_aux.h	11238;"	d
+CBR_TX_EN_SZ	include/ssv6200_aux.h	11240;"	d
+CBR_VT_MON_RDY_HI	include/ssv6200_aux.h	11194;"	d
+CBR_VT_MON_RDY_I_MSK	include/ssv6200_aux.h	11192;"	d
+CBR_VT_MON_RDY_MSK	include/ssv6200_aux.h	11191;"	d
+CBR_VT_MON_RDY_SFT	include/ssv6200_aux.h	11193;"	d
+CBR_VT_MON_RDY_SZ	include/ssv6200_aux.h	11195;"	d
+CC	smartlink/qqlink-lib-mipsel/case/ipcamera/Makefile	/^CC:=gcc$/;"	m
+CC	smartlink/qqlink-lib-mipsel/makefile	/^CC:=gcc -m32$/;"	m
+CCCR_00H_REG_HI	include/ssv6200_aux.h	3649;"	d
+CCCR_00H_REG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2774;"	d
+CCCR_00H_REG_I_MSK	include/ssv6200_aux.h	3647;"	d
+CCCR_00H_REG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2772;"	d
+CCCR_00H_REG_MSK	include/ssv6200_aux.h	3646;"	d
+CCCR_00H_REG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2771;"	d
+CCCR_00H_REG_SFT	include/ssv6200_aux.h	3648;"	d
+CCCR_00H_REG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2773;"	d
+CCCR_00H_REG_SZ	include/ssv6200_aux.h	3650;"	d
+CCCR_00H_REG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2775;"	d
+CCCR_02H_REG_HI	include/ssv6200_aux.h	3654;"	d
+CCCR_02H_REG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2779;"	d
+CCCR_02H_REG_I_MSK	include/ssv6200_aux.h	3652;"	d
+CCCR_02H_REG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2777;"	d
+CCCR_02H_REG_MSK	include/ssv6200_aux.h	3651;"	d
+CCCR_02H_REG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2776;"	d
+CCCR_02H_REG_SFT	include/ssv6200_aux.h	3653;"	d
+CCCR_02H_REG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2778;"	d
+CCCR_02H_REG_SZ	include/ssv6200_aux.h	3655;"	d
+CCCR_02H_REG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2780;"	d
+CCCR_03H_REG_HI	include/ssv6200_aux.h	3659;"	d
+CCCR_03H_REG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2784;"	d
+CCCR_03H_REG_I_MSK	include/ssv6200_aux.h	3657;"	d
+CCCR_03H_REG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2782;"	d
+CCCR_03H_REG_MSK	include/ssv6200_aux.h	3656;"	d
+CCCR_03H_REG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2781;"	d
+CCCR_03H_REG_SFT	include/ssv6200_aux.h	3658;"	d
+CCCR_03H_REG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2783;"	d
+CCCR_03H_REG_SZ	include/ssv6200_aux.h	3660;"	d
+CCCR_03H_REG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2785;"	d
+CCCR_04H_REG_HI	include/ssv6200_aux.h	3664;"	d
+CCCR_04H_REG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2789;"	d
+CCCR_04H_REG_I_MSK	include/ssv6200_aux.h	3662;"	d
+CCCR_04H_REG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2787;"	d
+CCCR_04H_REG_MSK	include/ssv6200_aux.h	3661;"	d
+CCCR_04H_REG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2786;"	d
+CCCR_04H_REG_SFT	include/ssv6200_aux.h	3663;"	d
+CCCR_04H_REG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2788;"	d
+CCCR_04H_REG_SZ	include/ssv6200_aux.h	3665;"	d
+CCCR_04H_REG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2790;"	d
+CCCR_05H_REG_HI	include/ssv6200_aux.h	3669;"	d
+CCCR_05H_REG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2794;"	d
+CCCR_05H_REG_I_MSK	include/ssv6200_aux.h	3667;"	d
+CCCR_05H_REG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2792;"	d
+CCCR_05H_REG_MSK	include/ssv6200_aux.h	3666;"	d
+CCCR_05H_REG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2791;"	d
+CCCR_05H_REG_SFT	include/ssv6200_aux.h	3668;"	d
+CCCR_05H_REG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2793;"	d
+CCCR_05H_REG_SZ	include/ssv6200_aux.h	3670;"	d
+CCCR_05H_REG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2795;"	d
+CCCR_06H_REG_HI	include/ssv6200_aux.h	3674;"	d
+CCCR_06H_REG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2799;"	d
+CCCR_06H_REG_I_MSK	include/ssv6200_aux.h	3672;"	d
+CCCR_06H_REG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2797;"	d
+CCCR_06H_REG_MSK	include/ssv6200_aux.h	3671;"	d
+CCCR_06H_REG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2796;"	d
+CCCR_06H_REG_SFT	include/ssv6200_aux.h	3673;"	d
+CCCR_06H_REG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2798;"	d
+CCCR_06H_REG_SZ	include/ssv6200_aux.h	3675;"	d
+CCCR_06H_REG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2800;"	d
+CCCR_07H_REG_HI	include/ssv6200_aux.h	3679;"	d
+CCCR_07H_REG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2804;"	d
+CCCR_07H_REG_I_MSK	include/ssv6200_aux.h	3677;"	d
+CCCR_07H_REG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2802;"	d
+CCCR_07H_REG_MSK	include/ssv6200_aux.h	3676;"	d
+CCCR_07H_REG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2801;"	d
+CCCR_07H_REG_SFT	include/ssv6200_aux.h	3678;"	d
+CCCR_07H_REG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2803;"	d
+CCCR_07H_REG_SZ	include/ssv6200_aux.h	3680;"	d
+CCCR_07H_REG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2805;"	d
+CCI_CTL	smac/dev.h	44;"	d
+CCI_DBG	smac/dev.h	45;"	d
+CCI_P1	smac/dev.h	46;"	d
+CCI_P2	smac/dev.h	47;"	d
+CCI_SMART	smac/dev.h	48;"	d
+CCK_ACK_DURATION	smac/ssv_rc_minstrel_ht.c	64;"	d	file:
+CCK_DURATION	smac/ssv_rc_minstrel_ht.c	60;"	d	file:
+CCK_DURATION_LIST	smac/ssv_rc_minstrel_ht.c	67;"	d	file:
+CCK_GROUP	smac/ssv_rc_minstrel_ht.c	72;"	d	file:
+CCK_PLCP_BITS	smac/dev.h	172;"	d
+CCK_PREAMBLE_BITS	smac/dev.h	171;"	d
+CCK_SIFS_TIME	smac/dev.h	170;"	d
+CCMP_HDR_LEN	smac/sec_ccmp.c	34;"	d	file:
+CCMP_H_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8919;"	d
+CCMP_H_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8917;"	d
+CCMP_H_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8916;"	d
+CCMP_H_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8918;"	d
+CCMP_H_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8920;"	d
+CCMP_MIC_LEN	smac/dev.h	55;"	d
+CCMP_MIC_LEN	smac/sec_ccmp.c	35;"	d	file:
+CCMP_PN_LEN	smac/sec_ccmp.c	36;"	d	file:
+CCMP_TK_LEN	smac/sec.h	25;"	d
+CD_HI	include/ssv6200_aux.h	4464;"	d
+CD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3574;"	d
+CD_I_MSK	include/ssv6200_aux.h	4462;"	d
+CD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3572;"	d
+CD_MSK	include/ssv6200_aux.h	4461;"	d
+CD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3571;"	d
+CD_SFT	include/ssv6200_aux.h	4463;"	d
+CD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3573;"	d
+CD_SZ	include/ssv6200_aux.h	4465;"	d
+CD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3575;"	d
+CH0_DYN_PRI_HI	include/ssv6200_aux.h	12474;"	d
+CH0_DYN_PRI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33999;"	d
+CH0_DYN_PRI_I_MSK	include/ssv6200_aux.h	12472;"	d
+CH0_DYN_PRI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33997;"	d
+CH0_DYN_PRI_MSK	include/ssv6200_aux.h	12471;"	d
+CH0_DYN_PRI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33996;"	d
+CH0_DYN_PRI_SFT	include/ssv6200_aux.h	12473;"	d
+CH0_DYN_PRI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33998;"	d
+CH0_DYN_PRI_SZ	include/ssv6200_aux.h	12475;"	d
+CH0_DYN_PRI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34000;"	d
+CH0_FFO_FULL_HI	include/ssv6200_aux.h	12084;"	d
+CH0_FFO_FULL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33674;"	d
+CH0_FFO_FULL_I_MSK	include/ssv6200_aux.h	12082;"	d
+CH0_FFO_FULL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33672;"	d
+CH0_FFO_FULL_MSK	include/ssv6200_aux.h	12081;"	d
+CH0_FFO_FULL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33671;"	d
+CH0_FFO_FULL_SFT	include/ssv6200_aux.h	12083;"	d
+CH0_FFO_FULL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33673;"	d
+CH0_FFO_FULL_SZ	include/ssv6200_aux.h	12085;"	d
+CH0_FFO_FULL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33675;"	d
+CH0_FULL_ALT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33109;"	d
+CH0_FULL_ALT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33107;"	d
+CH0_FULL_ALT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33106;"	d
+CH0_FULL_ALT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33108;"	d
+CH0_FULL_ALT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33110;"	d
+CH0_FULL_HI	include/ssv6200_aux.h	11424;"	d
+CH0_FULL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32984;"	d
+CH0_FULL_I_MSK	include/ssv6200_aux.h	11422;"	d
+CH0_FULL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32982;"	d
+CH0_FULL_MSK	include/ssv6200_aux.h	11421;"	d
+CH0_FULL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32981;"	d
+CH0_FULL_SFT	include/ssv6200_aux.h	11423;"	d
+CH0_FULL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32983;"	d
+CH0_FULL_SZ	include/ssv6200_aux.h	11425;"	d
+CH0_FULL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32985;"	d
+CH0_INT_ADDR_HI	include/ssv6200_aux.h	11414;"	d
+CH0_INT_ADDR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32964;"	d
+CH0_INT_ADDR_I_MSK	include/ssv6200_aux.h	11412;"	d
+CH0_INT_ADDR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32962;"	d
+CH0_INT_ADDR_MSK	include/ssv6200_aux.h	11411;"	d
+CH0_INT_ADDR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32961;"	d
+CH0_INT_ADDR_SFT	include/ssv6200_aux.h	11413;"	d
+CH0_INT_ADDR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32963;"	d
+CH0_INT_ADDR_SZ	include/ssv6200_aux.h	11415;"	d
+CH0_INT_ADDR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32965;"	d
+CH0_LOWTHOLD_HI	include/ssv6200_aux.h	12249;"	d
+CH0_LOWTHOLD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33839;"	d
+CH0_LOWTHOLD_INT_HI	include/ssv6200_aux.h	12164;"	d
+CH0_LOWTHOLD_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33754;"	d
+CH0_LOWTHOLD_INT_I_MSK	include/ssv6200_aux.h	12162;"	d
+CH0_LOWTHOLD_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33752;"	d
+CH0_LOWTHOLD_INT_MSK	include/ssv6200_aux.h	12161;"	d
+CH0_LOWTHOLD_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33751;"	d
+CH0_LOWTHOLD_INT_SFT	include/ssv6200_aux.h	12163;"	d
+CH0_LOWTHOLD_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33753;"	d
+CH0_LOWTHOLD_INT_SZ	include/ssv6200_aux.h	12165;"	d
+CH0_LOWTHOLD_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33755;"	d
+CH0_LOWTHOLD_I_MSK	include/ssv6200_aux.h	12247;"	d
+CH0_LOWTHOLD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33837;"	d
+CH0_LOWTHOLD_MSK	include/ssv6200_aux.h	12246;"	d
+CH0_LOWTHOLD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33836;"	d
+CH0_LOWTHOLD_SFT	include/ssv6200_aux.h	12248;"	d
+CH0_LOWTHOLD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33838;"	d
+CH0_LOWTHOLD_SZ	include/ssv6200_aux.h	12250;"	d
+CH0_LOWTHOLD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33840;"	d
+CH0_NVLD_HI	include/ssv6200_aux.h	12594;"	d
+CH0_NVLD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34119;"	d
+CH0_NVLD_I_MSK	include/ssv6200_aux.h	12592;"	d
+CH0_NVLD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34117;"	d
+CH0_NVLD_MSK	include/ssv6200_aux.h	12591;"	d
+CH0_NVLD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34116;"	d
+CH0_NVLD_SFT	include/ssv6200_aux.h	12593;"	d
+CH0_NVLD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34118;"	d
+CH0_NVLD_SZ	include/ssv6200_aux.h	12595;"	d
+CH0_NVLD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34120;"	d
+CH0_QUEUE_FLUSH_HI	include/ssv6200_aux.h	11924;"	d
+CH0_QUEUE_FLUSH_I_MSK	include/ssv6200_aux.h	11922;"	d
+CH0_QUEUE_FLUSH_MSK	include/ssv6200_aux.h	11921;"	d
+CH0_QUEUE_FLUSH_SFT	include/ssv6200_aux.h	11923;"	d
+CH0_QUEUE_FLUSH_SZ	include/ssv6200_aux.h	11925;"	d
+CH0_REQ_LOCK_HI	include/ssv6200_aux.h	12549;"	d
+CH0_REQ_LOCK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34074;"	d
+CH0_REQ_LOCK_I_MSK	include/ssv6200_aux.h	12547;"	d
+CH0_REQ_LOCK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34072;"	d
+CH0_REQ_LOCK_MSK	include/ssv6200_aux.h	12546;"	d
+CH0_REQ_LOCK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34071;"	d
+CH0_REQ_LOCK_SFT	include/ssv6200_aux.h	12548;"	d
+CH0_REQ_LOCK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34073;"	d
+CH0_REQ_LOCK_SZ	include/ssv6200_aux.h	12550;"	d
+CH0_REQ_LOCK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34075;"	d
+CH0_STA_PRI_HI	include/ssv6200_aux.h	12484;"	d
+CH0_STA_PRI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34009;"	d
+CH0_STA_PRI_I_MSK	include/ssv6200_aux.h	12482;"	d
+CH0_STA_PRI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34007;"	d
+CH0_STA_PRI_MSK	include/ssv6200_aux.h	12481;"	d
+CH0_STA_PRI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34006;"	d
+CH0_STA_PRI_SFT	include/ssv6200_aux.h	12483;"	d
+CH0_STA_PRI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34008;"	d
+CH0_STA_PRI_SZ	include/ssv6200_aux.h	12485;"	d
+CH0_STA_PRI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34010;"	d
+CH0_WRFF_FLUSH_HI	include/ssv6200_aux.h	12349;"	d
+CH0_WRFF_FLUSH_I_MSK	include/ssv6200_aux.h	12347;"	d
+CH0_WRFF_FLUSH_MSK	include/ssv6200_aux.h	12346;"	d
+CH0_WRFF_FLUSH_SFT	include/ssv6200_aux.h	12348;"	d
+CH0_WRFF_FLUSH_SZ	include/ssv6200_aux.h	12350;"	d
+CH10_FFO_FULL_HI	include/ssv6200_aux.h	12134;"	d
+CH10_FFO_FULL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33724;"	d
+CH10_FFO_FULL_I_MSK	include/ssv6200_aux.h	12132;"	d
+CH10_FFO_FULL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33722;"	d
+CH10_FFO_FULL_MSK	include/ssv6200_aux.h	12131;"	d
+CH10_FFO_FULL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33721;"	d
+CH10_FFO_FULL_SFT	include/ssv6200_aux.h	12133;"	d
+CH10_FFO_FULL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33723;"	d
+CH10_FFO_FULL_SZ	include/ssv6200_aux.h	12135;"	d
+CH10_FFO_FULL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33725;"	d
+CH10_FULL_HI	include/ssv6200_aux.h	11584;"	d
+CH10_FULL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33159;"	d
+CH10_FULL_I_MSK	include/ssv6200_aux.h	11582;"	d
+CH10_FULL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33157;"	d
+CH10_FULL_MSK	include/ssv6200_aux.h	11581;"	d
+CH10_FULL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33156;"	d
+CH10_FULL_SFT	include/ssv6200_aux.h	11583;"	d
+CH10_FULL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33158;"	d
+CH10_FULL_SZ	include/ssv6200_aux.h	11585;"	d
+CH10_FULL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33160;"	d
+CH10_HALT_STS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33334;"	d
+CH10_HALT_STS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33332;"	d
+CH10_HALT_STS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33331;"	d
+CH10_HALT_STS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33333;"	d
+CH10_HALT_STS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33335;"	d
+CH10_LOWTHOLD_HI	include/ssv6200_aux.h	12299;"	d
+CH10_LOWTHOLD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33889;"	d
+CH10_LOWTHOLD_INT_HI	include/ssv6200_aux.h	12214;"	d
+CH10_LOWTHOLD_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33804;"	d
+CH10_LOWTHOLD_INT_I_MSK	include/ssv6200_aux.h	12212;"	d
+CH10_LOWTHOLD_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33802;"	d
+CH10_LOWTHOLD_INT_MSK	include/ssv6200_aux.h	12211;"	d
+CH10_LOWTHOLD_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33801;"	d
+CH10_LOWTHOLD_INT_SFT	include/ssv6200_aux.h	12213;"	d
+CH10_LOWTHOLD_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33803;"	d
+CH10_LOWTHOLD_INT_SZ	include/ssv6200_aux.h	12215;"	d
+CH10_LOWTHOLD_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33805;"	d
+CH10_LOWTHOLD_I_MSK	include/ssv6200_aux.h	12297;"	d
+CH10_LOWTHOLD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33887;"	d
+CH10_LOWTHOLD_MSK	include/ssv6200_aux.h	12296;"	d
+CH10_LOWTHOLD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33886;"	d
+CH10_LOWTHOLD_SFT	include/ssv6200_aux.h	12298;"	d
+CH10_LOWTHOLD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33888;"	d
+CH10_LOWTHOLD_SZ	include/ssv6200_aux.h	12300;"	d
+CH10_LOWTHOLD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33890;"	d
+CH10_QUEUE_FLUSH_HI	include/ssv6200_aux.h	11974;"	d
+CH10_QUEUE_FLUSH_I_MSK	include/ssv6200_aux.h	11972;"	d
+CH10_QUEUE_FLUSH_MSK	include/ssv6200_aux.h	11971;"	d
+CH10_QUEUE_FLUSH_SFT	include/ssv6200_aux.h	11973;"	d
+CH10_QUEUE_FLUSH_SZ	include/ssv6200_aux.h	11975;"	d
+CH10_WRFF_FLUSH_HI	include/ssv6200_aux.h	12399;"	d
+CH10_WRFF_FLUSH_I_MSK	include/ssv6200_aux.h	12397;"	d
+CH10_WRFF_FLUSH_MSK	include/ssv6200_aux.h	12396;"	d
+CH10_WRFF_FLUSH_SFT	include/ssv6200_aux.h	12398;"	d
+CH10_WRFF_FLUSH_SZ	include/ssv6200_aux.h	12400;"	d
+CH11_FFO_FULL_HI	include/ssv6200_aux.h	12139;"	d
+CH11_FFO_FULL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33729;"	d
+CH11_FFO_FULL_I_MSK	include/ssv6200_aux.h	12137;"	d
+CH11_FFO_FULL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33727;"	d
+CH11_FFO_FULL_MSK	include/ssv6200_aux.h	12136;"	d
+CH11_FFO_FULL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33726;"	d
+CH11_FFO_FULL_SFT	include/ssv6200_aux.h	12138;"	d
+CH11_FFO_FULL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33728;"	d
+CH11_FFO_FULL_SZ	include/ssv6200_aux.h	12140;"	d
+CH11_FFO_FULL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33730;"	d
+CH11_FULL_HI	include/ssv6200_aux.h	11589;"	d
+CH11_FULL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33164;"	d
+CH11_FULL_I_MSK	include/ssv6200_aux.h	11587;"	d
+CH11_FULL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33162;"	d
+CH11_FULL_MSK	include/ssv6200_aux.h	11586;"	d
+CH11_FULL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33161;"	d
+CH11_FULL_SFT	include/ssv6200_aux.h	11588;"	d
+CH11_FULL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33163;"	d
+CH11_FULL_SZ	include/ssv6200_aux.h	11590;"	d
+CH11_FULL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33165;"	d
+CH11_HALT_STS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33339;"	d
+CH11_HALT_STS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33337;"	d
+CH11_HALT_STS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33336;"	d
+CH11_HALT_STS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33338;"	d
+CH11_HALT_STS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33340;"	d
+CH11_LOWTHOLD_HI	include/ssv6200_aux.h	12304;"	d
+CH11_LOWTHOLD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33894;"	d
+CH11_LOWTHOLD_INT_HI	include/ssv6200_aux.h	12219;"	d
+CH11_LOWTHOLD_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33809;"	d
+CH11_LOWTHOLD_INT_I_MSK	include/ssv6200_aux.h	12217;"	d
+CH11_LOWTHOLD_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33807;"	d
+CH11_LOWTHOLD_INT_MSK	include/ssv6200_aux.h	12216;"	d
+CH11_LOWTHOLD_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33806;"	d
+CH11_LOWTHOLD_INT_SFT	include/ssv6200_aux.h	12218;"	d
+CH11_LOWTHOLD_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33808;"	d
+CH11_LOWTHOLD_INT_SZ	include/ssv6200_aux.h	12220;"	d
+CH11_LOWTHOLD_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33810;"	d
+CH11_LOWTHOLD_I_MSK	include/ssv6200_aux.h	12302;"	d
+CH11_LOWTHOLD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33892;"	d
+CH11_LOWTHOLD_MSK	include/ssv6200_aux.h	12301;"	d
+CH11_LOWTHOLD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33891;"	d
+CH11_LOWTHOLD_SFT	include/ssv6200_aux.h	12303;"	d
+CH11_LOWTHOLD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33893;"	d
+CH11_LOWTHOLD_SZ	include/ssv6200_aux.h	12305;"	d
+CH11_LOWTHOLD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33895;"	d
+CH11_QUEUE_FLUSH_HI	include/ssv6200_aux.h	11979;"	d
+CH11_QUEUE_FLUSH_I_MSK	include/ssv6200_aux.h	11977;"	d
+CH11_QUEUE_FLUSH_MSK	include/ssv6200_aux.h	11976;"	d
+CH11_QUEUE_FLUSH_SFT	include/ssv6200_aux.h	11978;"	d
+CH11_QUEUE_FLUSH_SZ	include/ssv6200_aux.h	11980;"	d
+CH11_WRFF_FLUSH_HI	include/ssv6200_aux.h	12404;"	d
+CH11_WRFF_FLUSH_I_MSK	include/ssv6200_aux.h	12402;"	d
+CH11_WRFF_FLUSH_MSK	include/ssv6200_aux.h	12401;"	d
+CH11_WRFF_FLUSH_SFT	include/ssv6200_aux.h	12403;"	d
+CH11_WRFF_FLUSH_SZ	include/ssv6200_aux.h	12405;"	d
+CH12_FFO_FULL_HI	include/ssv6200_aux.h	12144;"	d
+CH12_FFO_FULL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33734;"	d
+CH12_FFO_FULL_I_MSK	include/ssv6200_aux.h	12142;"	d
+CH12_FFO_FULL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33732;"	d
+CH12_FFO_FULL_MSK	include/ssv6200_aux.h	12141;"	d
+CH12_FFO_FULL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33731;"	d
+CH12_FFO_FULL_SFT	include/ssv6200_aux.h	12143;"	d
+CH12_FFO_FULL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33733;"	d
+CH12_FFO_FULL_SZ	include/ssv6200_aux.h	12145;"	d
+CH12_FFO_FULL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33735;"	d
+CH12_FULL_HI	include/ssv6200_aux.h	11594;"	d
+CH12_FULL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33169;"	d
+CH12_FULL_I_MSK	include/ssv6200_aux.h	11592;"	d
+CH12_FULL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33167;"	d
+CH12_FULL_MSK	include/ssv6200_aux.h	11591;"	d
+CH12_FULL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33166;"	d
+CH12_FULL_SFT	include/ssv6200_aux.h	11593;"	d
+CH12_FULL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33168;"	d
+CH12_FULL_SZ	include/ssv6200_aux.h	11595;"	d
+CH12_FULL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33170;"	d
+CH12_HALT_STS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33344;"	d
+CH12_HALT_STS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33342;"	d
+CH12_HALT_STS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33341;"	d
+CH12_HALT_STS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33343;"	d
+CH12_HALT_STS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33345;"	d
+CH12_LOWTHOLD_HI	include/ssv6200_aux.h	12309;"	d
+CH12_LOWTHOLD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33899;"	d
+CH12_LOWTHOLD_INT_HI	include/ssv6200_aux.h	12224;"	d
+CH12_LOWTHOLD_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33814;"	d
+CH12_LOWTHOLD_INT_I_MSK	include/ssv6200_aux.h	12222;"	d
+CH12_LOWTHOLD_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33812;"	d
+CH12_LOWTHOLD_INT_MSK	include/ssv6200_aux.h	12221;"	d
+CH12_LOWTHOLD_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33811;"	d
+CH12_LOWTHOLD_INT_SFT	include/ssv6200_aux.h	12223;"	d
+CH12_LOWTHOLD_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33813;"	d
+CH12_LOWTHOLD_INT_SZ	include/ssv6200_aux.h	12225;"	d
+CH12_LOWTHOLD_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33815;"	d
+CH12_LOWTHOLD_I_MSK	include/ssv6200_aux.h	12307;"	d
+CH12_LOWTHOLD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33897;"	d
+CH12_LOWTHOLD_MSK	include/ssv6200_aux.h	12306;"	d
+CH12_LOWTHOLD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33896;"	d
+CH12_LOWTHOLD_SFT	include/ssv6200_aux.h	12308;"	d
+CH12_LOWTHOLD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33898;"	d
+CH12_LOWTHOLD_SZ	include/ssv6200_aux.h	12310;"	d
+CH12_LOWTHOLD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33900;"	d
+CH12_QUEUE_FLUSH_HI	include/ssv6200_aux.h	11984;"	d
+CH12_QUEUE_FLUSH_I_MSK	include/ssv6200_aux.h	11982;"	d
+CH12_QUEUE_FLUSH_MSK	include/ssv6200_aux.h	11981;"	d
+CH12_QUEUE_FLUSH_SFT	include/ssv6200_aux.h	11983;"	d
+CH12_QUEUE_FLUSH_SZ	include/ssv6200_aux.h	11985;"	d
+CH12_WRFF_FLUSH_HI	include/ssv6200_aux.h	12409;"	d
+CH12_WRFF_FLUSH_I_MSK	include/ssv6200_aux.h	12407;"	d
+CH12_WRFF_FLUSH_MSK	include/ssv6200_aux.h	12406;"	d
+CH12_WRFF_FLUSH_SFT	include/ssv6200_aux.h	12408;"	d
+CH12_WRFF_FLUSH_SZ	include/ssv6200_aux.h	12410;"	d
+CH13_FFO_FULL_HI	include/ssv6200_aux.h	12149;"	d
+CH13_FFO_FULL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33739;"	d
+CH13_FFO_FULL_I_MSK	include/ssv6200_aux.h	12147;"	d
+CH13_FFO_FULL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33737;"	d
+CH13_FFO_FULL_MSK	include/ssv6200_aux.h	12146;"	d
+CH13_FFO_FULL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33736;"	d
+CH13_FFO_FULL_SFT	include/ssv6200_aux.h	12148;"	d
+CH13_FFO_FULL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33738;"	d
+CH13_FFO_FULL_SZ	include/ssv6200_aux.h	12150;"	d
+CH13_FFO_FULL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33740;"	d
+CH13_FULL_HI	include/ssv6200_aux.h	11599;"	d
+CH13_FULL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33174;"	d
+CH13_FULL_I_MSK	include/ssv6200_aux.h	11597;"	d
+CH13_FULL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33172;"	d
+CH13_FULL_MSK	include/ssv6200_aux.h	11596;"	d
+CH13_FULL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33171;"	d
+CH13_FULL_SFT	include/ssv6200_aux.h	11598;"	d
+CH13_FULL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33173;"	d
+CH13_FULL_SZ	include/ssv6200_aux.h	11600;"	d
+CH13_FULL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33175;"	d
+CH13_HALT_STS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33349;"	d
+CH13_HALT_STS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33347;"	d
+CH13_HALT_STS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33346;"	d
+CH13_HALT_STS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33348;"	d
+CH13_HALT_STS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33350;"	d
+CH13_LOWTHOLD_HI	include/ssv6200_aux.h	12314;"	d
+CH13_LOWTHOLD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33904;"	d
+CH13_LOWTHOLD_INT_HI	include/ssv6200_aux.h	12229;"	d
+CH13_LOWTHOLD_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33819;"	d
+CH13_LOWTHOLD_INT_I_MSK	include/ssv6200_aux.h	12227;"	d
+CH13_LOWTHOLD_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33817;"	d
+CH13_LOWTHOLD_INT_MSK	include/ssv6200_aux.h	12226;"	d
+CH13_LOWTHOLD_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33816;"	d
+CH13_LOWTHOLD_INT_SFT	include/ssv6200_aux.h	12228;"	d
+CH13_LOWTHOLD_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33818;"	d
+CH13_LOWTHOLD_INT_SZ	include/ssv6200_aux.h	12230;"	d
+CH13_LOWTHOLD_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33820;"	d
+CH13_LOWTHOLD_I_MSK	include/ssv6200_aux.h	12312;"	d
+CH13_LOWTHOLD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33902;"	d
+CH13_LOWTHOLD_MSK	include/ssv6200_aux.h	12311;"	d
+CH13_LOWTHOLD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33901;"	d
+CH13_LOWTHOLD_SFT	include/ssv6200_aux.h	12313;"	d
+CH13_LOWTHOLD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33903;"	d
+CH13_LOWTHOLD_SZ	include/ssv6200_aux.h	12315;"	d
+CH13_LOWTHOLD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33905;"	d
+CH13_QUEUE_FLUSH_HI	include/ssv6200_aux.h	11989;"	d
+CH13_QUEUE_FLUSH_I_MSK	include/ssv6200_aux.h	11987;"	d
+CH13_QUEUE_FLUSH_MSK	include/ssv6200_aux.h	11986;"	d
+CH13_QUEUE_FLUSH_SFT	include/ssv6200_aux.h	11988;"	d
+CH13_QUEUE_FLUSH_SZ	include/ssv6200_aux.h	11990;"	d
+CH13_WRFF_FLUSH_HI	include/ssv6200_aux.h	12414;"	d
+CH13_WRFF_FLUSH_I_MSK	include/ssv6200_aux.h	12412;"	d
+CH13_WRFF_FLUSH_MSK	include/ssv6200_aux.h	12411;"	d
+CH13_WRFF_FLUSH_SFT	include/ssv6200_aux.h	12413;"	d
+CH13_WRFF_FLUSH_SZ	include/ssv6200_aux.h	12415;"	d
+CH14_FFO_FULL_HI	include/ssv6200_aux.h	12154;"	d
+CH14_FFO_FULL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33744;"	d
+CH14_FFO_FULL_I_MSK	include/ssv6200_aux.h	12152;"	d
+CH14_FFO_FULL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33742;"	d
+CH14_FFO_FULL_MSK	include/ssv6200_aux.h	12151;"	d
+CH14_FFO_FULL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33741;"	d
+CH14_FFO_FULL_SFT	include/ssv6200_aux.h	12153;"	d
+CH14_FFO_FULL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33743;"	d
+CH14_FFO_FULL_SZ	include/ssv6200_aux.h	12155;"	d
+CH14_FFO_FULL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33745;"	d
+CH14_FULL_HI	include/ssv6200_aux.h	11604;"	d
+CH14_FULL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33179;"	d
+CH14_FULL_I_MSK	include/ssv6200_aux.h	11602;"	d
+CH14_FULL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33177;"	d
+CH14_FULL_MSK	include/ssv6200_aux.h	11601;"	d
+CH14_FULL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33176;"	d
+CH14_FULL_SFT	include/ssv6200_aux.h	11603;"	d
+CH14_FULL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33178;"	d
+CH14_FULL_SZ	include/ssv6200_aux.h	11605;"	d
+CH14_FULL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33180;"	d
+CH14_HALT_STS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33354;"	d
+CH14_HALT_STS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33352;"	d
+CH14_HALT_STS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33351;"	d
+CH14_HALT_STS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33353;"	d
+CH14_HALT_STS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33355;"	d
+CH14_LOWTHOLD_HI	include/ssv6200_aux.h	12319;"	d
+CH14_LOWTHOLD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33909;"	d
+CH14_LOWTHOLD_INT_HI	include/ssv6200_aux.h	12234;"	d
+CH14_LOWTHOLD_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33824;"	d
+CH14_LOWTHOLD_INT_I_MSK	include/ssv6200_aux.h	12232;"	d
+CH14_LOWTHOLD_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33822;"	d
+CH14_LOWTHOLD_INT_MSK	include/ssv6200_aux.h	12231;"	d
+CH14_LOWTHOLD_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33821;"	d
+CH14_LOWTHOLD_INT_SFT	include/ssv6200_aux.h	12233;"	d
+CH14_LOWTHOLD_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33823;"	d
+CH14_LOWTHOLD_INT_SZ	include/ssv6200_aux.h	12235;"	d
+CH14_LOWTHOLD_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33825;"	d
+CH14_LOWTHOLD_I_MSK	include/ssv6200_aux.h	12317;"	d
+CH14_LOWTHOLD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33907;"	d
+CH14_LOWTHOLD_MSK	include/ssv6200_aux.h	12316;"	d
+CH14_LOWTHOLD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33906;"	d
+CH14_LOWTHOLD_SFT	include/ssv6200_aux.h	12318;"	d
+CH14_LOWTHOLD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33908;"	d
+CH14_LOWTHOLD_SZ	include/ssv6200_aux.h	12320;"	d
+CH14_LOWTHOLD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33910;"	d
+CH14_QUEUE_FLUSH_HI	include/ssv6200_aux.h	11994;"	d
+CH14_QUEUE_FLUSH_I_MSK	include/ssv6200_aux.h	11992;"	d
+CH14_QUEUE_FLUSH_MSK	include/ssv6200_aux.h	11991;"	d
+CH14_QUEUE_FLUSH_SFT	include/ssv6200_aux.h	11993;"	d
+CH14_QUEUE_FLUSH_SZ	include/ssv6200_aux.h	11995;"	d
+CH14_WRFF_FLUSH_HI	include/ssv6200_aux.h	12419;"	d
+CH14_WRFF_FLUSH_I_MSK	include/ssv6200_aux.h	12417;"	d
+CH14_WRFF_FLUSH_MSK	include/ssv6200_aux.h	12416;"	d
+CH14_WRFF_FLUSH_SFT	include/ssv6200_aux.h	12418;"	d
+CH14_WRFF_FLUSH_SZ	include/ssv6200_aux.h	12420;"	d
+CH15_FFO_FULL_HI	include/ssv6200_aux.h	12159;"	d
+CH15_FFO_FULL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33749;"	d
+CH15_FFO_FULL_I_MSK	include/ssv6200_aux.h	12157;"	d
+CH15_FFO_FULL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33747;"	d
+CH15_FFO_FULL_MSK	include/ssv6200_aux.h	12156;"	d
+CH15_FFO_FULL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33746;"	d
+CH15_FFO_FULL_SFT	include/ssv6200_aux.h	12158;"	d
+CH15_FFO_FULL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33748;"	d
+CH15_FFO_FULL_SZ	include/ssv6200_aux.h	12160;"	d
+CH15_FFO_FULL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33750;"	d
+CH15_FULL_HI	include/ssv6200_aux.h	11609;"	d
+CH15_FULL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33184;"	d
+CH15_FULL_I_MSK	include/ssv6200_aux.h	11607;"	d
+CH15_FULL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33182;"	d
+CH15_FULL_MSK	include/ssv6200_aux.h	11606;"	d
+CH15_FULL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33181;"	d
+CH15_FULL_SFT	include/ssv6200_aux.h	11608;"	d
+CH15_FULL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33183;"	d
+CH15_FULL_SZ	include/ssv6200_aux.h	11610;"	d
+CH15_FULL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33185;"	d
+CH15_LOWTHOLD_HI	include/ssv6200_aux.h	12324;"	d
+CH15_LOWTHOLD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33914;"	d
+CH15_LOWTHOLD_INT_HI	include/ssv6200_aux.h	12239;"	d
+CH15_LOWTHOLD_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33829;"	d
+CH15_LOWTHOLD_INT_I_MSK	include/ssv6200_aux.h	12237;"	d
+CH15_LOWTHOLD_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33827;"	d
+CH15_LOWTHOLD_INT_MSK	include/ssv6200_aux.h	12236;"	d
+CH15_LOWTHOLD_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33826;"	d
+CH15_LOWTHOLD_INT_SFT	include/ssv6200_aux.h	12238;"	d
+CH15_LOWTHOLD_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33828;"	d
+CH15_LOWTHOLD_INT_SZ	include/ssv6200_aux.h	12240;"	d
+CH15_LOWTHOLD_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33830;"	d
+CH15_LOWTHOLD_I_MSK	include/ssv6200_aux.h	12322;"	d
+CH15_LOWTHOLD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33912;"	d
+CH15_LOWTHOLD_MSK	include/ssv6200_aux.h	12321;"	d
+CH15_LOWTHOLD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33911;"	d
+CH15_LOWTHOLD_SFT	include/ssv6200_aux.h	12323;"	d
+CH15_LOWTHOLD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33913;"	d
+CH15_LOWTHOLD_SZ	include/ssv6200_aux.h	12325;"	d
+CH15_LOWTHOLD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33915;"	d
+CH15_QUEUE_FLUSH_HI	include/ssv6200_aux.h	11999;"	d
+CH15_QUEUE_FLUSH_I_MSK	include/ssv6200_aux.h	11997;"	d
+CH15_QUEUE_FLUSH_MSK	include/ssv6200_aux.h	11996;"	d
+CH15_QUEUE_FLUSH_SFT	include/ssv6200_aux.h	11998;"	d
+CH15_QUEUE_FLUSH_SZ	include/ssv6200_aux.h	12000;"	d
+CH1_FFO_FULL_HI	include/ssv6200_aux.h	12089;"	d
+CH1_FFO_FULL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33679;"	d
+CH1_FFO_FULL_I_MSK	include/ssv6200_aux.h	12087;"	d
+CH1_FFO_FULL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33677;"	d
+CH1_FFO_FULL_MSK	include/ssv6200_aux.h	12086;"	d
+CH1_FFO_FULL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33676;"	d
+CH1_FFO_FULL_SFT	include/ssv6200_aux.h	12088;"	d
+CH1_FFO_FULL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33678;"	d
+CH1_FFO_FULL_SZ	include/ssv6200_aux.h	12090;"	d
+CH1_FFO_FULL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33680;"	d
+CH1_FULL_HI	include/ssv6200_aux.h	11539;"	d
+CH1_FULL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33114;"	d
+CH1_FULL_I_MSK	include/ssv6200_aux.h	11537;"	d
+CH1_FULL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33112;"	d
+CH1_FULL_MSK	include/ssv6200_aux.h	11536;"	d
+CH1_FULL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33111;"	d
+CH1_FULL_SFT	include/ssv6200_aux.h	11538;"	d
+CH1_FULL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33113;"	d
+CH1_FULL_SZ	include/ssv6200_aux.h	11540;"	d
+CH1_FULL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33115;"	d
+CH1_HALT_STS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33294;"	d
+CH1_HALT_STS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33292;"	d
+CH1_HALT_STS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33291;"	d
+CH1_HALT_STS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33293;"	d
+CH1_HALT_STS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33295;"	d
+CH1_LOWTHOLD_HI	include/ssv6200_aux.h	12254;"	d
+CH1_LOWTHOLD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33844;"	d
+CH1_LOWTHOLD_INT_HI	include/ssv6200_aux.h	12169;"	d
+CH1_LOWTHOLD_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33759;"	d
+CH1_LOWTHOLD_INT_I_MSK	include/ssv6200_aux.h	12167;"	d
+CH1_LOWTHOLD_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33757;"	d
+CH1_LOWTHOLD_INT_MSK	include/ssv6200_aux.h	12166;"	d
+CH1_LOWTHOLD_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33756;"	d
+CH1_LOWTHOLD_INT_SFT	include/ssv6200_aux.h	12168;"	d
+CH1_LOWTHOLD_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33758;"	d
+CH1_LOWTHOLD_INT_SZ	include/ssv6200_aux.h	12170;"	d
+CH1_LOWTHOLD_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33760;"	d
+CH1_LOWTHOLD_I_MSK	include/ssv6200_aux.h	12252;"	d
+CH1_LOWTHOLD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33842;"	d
+CH1_LOWTHOLD_MSK	include/ssv6200_aux.h	12251;"	d
+CH1_LOWTHOLD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33841;"	d
+CH1_LOWTHOLD_SFT	include/ssv6200_aux.h	12253;"	d
+CH1_LOWTHOLD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33843;"	d
+CH1_LOWTHOLD_SZ	include/ssv6200_aux.h	12255;"	d
+CH1_LOWTHOLD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33845;"	d
+CH1_NVLD_HI	include/ssv6200_aux.h	12599;"	d
+CH1_NVLD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34124;"	d
+CH1_NVLD_I_MSK	include/ssv6200_aux.h	12597;"	d
+CH1_NVLD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34122;"	d
+CH1_NVLD_MSK	include/ssv6200_aux.h	12596;"	d
+CH1_NVLD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34121;"	d
+CH1_NVLD_SFT	include/ssv6200_aux.h	12598;"	d
+CH1_NVLD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34123;"	d
+CH1_NVLD_SZ	include/ssv6200_aux.h	12600;"	d
+CH1_NVLD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34125;"	d
+CH1_PRI_HI	include/ssv6200_aux.h	8749;"	d
+CH1_PRI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8504;"	d
+CH1_PRI_I_MSK	include/ssv6200_aux.h	8747;"	d
+CH1_PRI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8502;"	d
+CH1_PRI_MSK	include/ssv6200_aux.h	8746;"	d
+CH1_PRI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8501;"	d
+CH1_PRI_SFT	include/ssv6200_aux.h	8748;"	d
+CH1_PRI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8503;"	d
+CH1_PRI_SZ	include/ssv6200_aux.h	8750;"	d
+CH1_PRI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8505;"	d
+CH1_QUEUE_FLUSH_HI	include/ssv6200_aux.h	11929;"	d
+CH1_QUEUE_FLUSH_I_MSK	include/ssv6200_aux.h	11927;"	d
+CH1_QUEUE_FLUSH_MSK	include/ssv6200_aux.h	11926;"	d
+CH1_QUEUE_FLUSH_SFT	include/ssv6200_aux.h	11928;"	d
+CH1_QUEUE_FLUSH_SZ	include/ssv6200_aux.h	11930;"	d
+CH1_REQ_LOCK_HI	include/ssv6200_aux.h	12554;"	d
+CH1_REQ_LOCK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34079;"	d
+CH1_REQ_LOCK_I_MSK	include/ssv6200_aux.h	12552;"	d
+CH1_REQ_LOCK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34077;"	d
+CH1_REQ_LOCK_MSK	include/ssv6200_aux.h	12551;"	d
+CH1_REQ_LOCK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34076;"	d
+CH1_REQ_LOCK_SFT	include/ssv6200_aux.h	12553;"	d
+CH1_REQ_LOCK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34078;"	d
+CH1_REQ_LOCK_SZ	include/ssv6200_aux.h	12555;"	d
+CH1_REQ_LOCK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34080;"	d
+CH1_STA_PRI_HI	include/ssv6200_aux.h	12489;"	d
+CH1_STA_PRI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34014;"	d
+CH1_STA_PRI_I_MSK	include/ssv6200_aux.h	12487;"	d
+CH1_STA_PRI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34012;"	d
+CH1_STA_PRI_MSK	include/ssv6200_aux.h	12486;"	d
+CH1_STA_PRI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34011;"	d
+CH1_STA_PRI_SFT	include/ssv6200_aux.h	12488;"	d
+CH1_STA_PRI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34013;"	d
+CH1_STA_PRI_SZ	include/ssv6200_aux.h	12490;"	d
+CH1_STA_PRI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34015;"	d
+CH1_WRFF_FLUSH_HI	include/ssv6200_aux.h	12354;"	d
+CH1_WRFF_FLUSH_I_MSK	include/ssv6200_aux.h	12352;"	d
+CH1_WRFF_FLUSH_MSK	include/ssv6200_aux.h	12351;"	d
+CH1_WRFF_FLUSH_SFT	include/ssv6200_aux.h	12353;"	d
+CH1_WRFF_FLUSH_SZ	include/ssv6200_aux.h	12355;"	d
+CH2_FFO_FULL_HI	include/ssv6200_aux.h	12094;"	d
+CH2_FFO_FULL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33684;"	d
+CH2_FFO_FULL_I_MSK	include/ssv6200_aux.h	12092;"	d
+CH2_FFO_FULL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33682;"	d
+CH2_FFO_FULL_MSK	include/ssv6200_aux.h	12091;"	d
+CH2_FFO_FULL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33681;"	d
+CH2_FFO_FULL_SFT	include/ssv6200_aux.h	12093;"	d
+CH2_FFO_FULL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33683;"	d
+CH2_FFO_FULL_SZ	include/ssv6200_aux.h	12095;"	d
+CH2_FFO_FULL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33685;"	d
+CH2_FULL_ALT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33119;"	d
+CH2_FULL_ALT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33117;"	d
+CH2_FULL_ALT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33116;"	d
+CH2_FULL_ALT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33118;"	d
+CH2_FULL_ALT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33120;"	d
+CH2_FULL_HI	include/ssv6200_aux.h	11544;"	d
+CH2_FULL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32994;"	d
+CH2_FULL_I_MSK	include/ssv6200_aux.h	11542;"	d
+CH2_FULL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32992;"	d
+CH2_FULL_MSK	include/ssv6200_aux.h	11541;"	d
+CH2_FULL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32991;"	d
+CH2_FULL_SFT	include/ssv6200_aux.h	11543;"	d
+CH2_FULL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32993;"	d
+CH2_FULL_SZ	include/ssv6200_aux.h	11545;"	d
+CH2_FULL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32995;"	d
+CH2_INT_ADDR_ALT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33204;"	d
+CH2_INT_ADDR_ALT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33202;"	d
+CH2_INT_ADDR_ALT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33201;"	d
+CH2_INT_ADDR_ALT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33203;"	d
+CH2_INT_ADDR_ALT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33205;"	d
+CH2_LOWTHOLD_HI	include/ssv6200_aux.h	12259;"	d
+CH2_LOWTHOLD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33849;"	d
+CH2_LOWTHOLD_INT_HI	include/ssv6200_aux.h	12174;"	d
+CH2_LOWTHOLD_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33764;"	d
+CH2_LOWTHOLD_INT_I_MSK	include/ssv6200_aux.h	12172;"	d
+CH2_LOWTHOLD_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33762;"	d
+CH2_LOWTHOLD_INT_MSK	include/ssv6200_aux.h	12171;"	d
+CH2_LOWTHOLD_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33761;"	d
+CH2_LOWTHOLD_INT_SFT	include/ssv6200_aux.h	12173;"	d
+CH2_LOWTHOLD_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33763;"	d
+CH2_LOWTHOLD_INT_SZ	include/ssv6200_aux.h	12175;"	d
+CH2_LOWTHOLD_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33765;"	d
+CH2_LOWTHOLD_I_MSK	include/ssv6200_aux.h	12257;"	d
+CH2_LOWTHOLD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33847;"	d
+CH2_LOWTHOLD_MSK	include/ssv6200_aux.h	12256;"	d
+CH2_LOWTHOLD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33846;"	d
+CH2_LOWTHOLD_SFT	include/ssv6200_aux.h	12258;"	d
+CH2_LOWTHOLD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33848;"	d
+CH2_LOWTHOLD_SZ	include/ssv6200_aux.h	12260;"	d
+CH2_LOWTHOLD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33850;"	d
+CH2_NVLD_HI	include/ssv6200_aux.h	12604;"	d
+CH2_NVLD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34129;"	d
+CH2_NVLD_I_MSK	include/ssv6200_aux.h	12602;"	d
+CH2_NVLD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34127;"	d
+CH2_NVLD_MSK	include/ssv6200_aux.h	12601;"	d
+CH2_NVLD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34126;"	d
+CH2_NVLD_SFT	include/ssv6200_aux.h	12603;"	d
+CH2_NVLD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34128;"	d
+CH2_NVLD_SZ	include/ssv6200_aux.h	12605;"	d
+CH2_NVLD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34130;"	d
+CH2_PRI_HI	include/ssv6200_aux.h	8754;"	d
+CH2_PRI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8509;"	d
+CH2_PRI_I_MSK	include/ssv6200_aux.h	8752;"	d
+CH2_PRI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8507;"	d
+CH2_PRI_MSK	include/ssv6200_aux.h	8751;"	d
+CH2_PRI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8506;"	d
+CH2_PRI_SFT	include/ssv6200_aux.h	8753;"	d
+CH2_PRI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8508;"	d
+CH2_PRI_SZ	include/ssv6200_aux.h	8755;"	d
+CH2_PRI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8510;"	d
+CH2_QUEUE_FLUSH_HI	include/ssv6200_aux.h	11934;"	d
+CH2_QUEUE_FLUSH_I_MSK	include/ssv6200_aux.h	11932;"	d
+CH2_QUEUE_FLUSH_MSK	include/ssv6200_aux.h	11931;"	d
+CH2_QUEUE_FLUSH_SFT	include/ssv6200_aux.h	11933;"	d
+CH2_QUEUE_FLUSH_SZ	include/ssv6200_aux.h	11935;"	d
+CH2_REQ_LOCK_HI	include/ssv6200_aux.h	12559;"	d
+CH2_REQ_LOCK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34084;"	d
+CH2_REQ_LOCK_I_MSK	include/ssv6200_aux.h	12557;"	d
+CH2_REQ_LOCK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34082;"	d
+CH2_REQ_LOCK_MSK	include/ssv6200_aux.h	12556;"	d
+CH2_REQ_LOCK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34081;"	d
+CH2_REQ_LOCK_SFT	include/ssv6200_aux.h	12558;"	d
+CH2_REQ_LOCK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34083;"	d
+CH2_REQ_LOCK_SZ	include/ssv6200_aux.h	12560;"	d
+CH2_REQ_LOCK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34085;"	d
+CH2_STA_PRI_HI	include/ssv6200_aux.h	12494;"	d
+CH2_STA_PRI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34019;"	d
+CH2_STA_PRI_I_MSK	include/ssv6200_aux.h	12492;"	d
+CH2_STA_PRI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34017;"	d
+CH2_STA_PRI_MSK	include/ssv6200_aux.h	12491;"	d
+CH2_STA_PRI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34016;"	d
+CH2_STA_PRI_SFT	include/ssv6200_aux.h	12493;"	d
+CH2_STA_PRI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34018;"	d
+CH2_STA_PRI_SZ	include/ssv6200_aux.h	12495;"	d
+CH2_STA_PRI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34020;"	d
+CH2_WRFF_FLUSH_HI	include/ssv6200_aux.h	12359;"	d
+CH2_WRFF_FLUSH_I_MSK	include/ssv6200_aux.h	12357;"	d
+CH2_WRFF_FLUSH_MSK	include/ssv6200_aux.h	12356;"	d
+CH2_WRFF_FLUSH_SFT	include/ssv6200_aux.h	12358;"	d
+CH2_WRFF_FLUSH_SZ	include/ssv6200_aux.h	12360;"	d
+CH3_FFO_FULL_HI	include/ssv6200_aux.h	12099;"	d
+CH3_FFO_FULL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33689;"	d
+CH3_FFO_FULL_I_MSK	include/ssv6200_aux.h	12097;"	d
+CH3_FFO_FULL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33687;"	d
+CH3_FFO_FULL_MSK	include/ssv6200_aux.h	12096;"	d
+CH3_FFO_FULL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33686;"	d
+CH3_FFO_FULL_SFT	include/ssv6200_aux.h	12098;"	d
+CH3_FFO_FULL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33688;"	d
+CH3_FFO_FULL_SZ	include/ssv6200_aux.h	12100;"	d
+CH3_FFO_FULL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33690;"	d
+CH3_FULL_HI	include/ssv6200_aux.h	11549;"	d
+CH3_FULL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33124;"	d
+CH3_FULL_I_MSK	include/ssv6200_aux.h	11547;"	d
+CH3_FULL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33122;"	d
+CH3_FULL_MSK	include/ssv6200_aux.h	11546;"	d
+CH3_FULL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33121;"	d
+CH3_FULL_SFT	include/ssv6200_aux.h	11548;"	d
+CH3_FULL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33123;"	d
+CH3_FULL_SZ	include/ssv6200_aux.h	11550;"	d
+CH3_FULL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33125;"	d
+CH3_HALT_STS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33299;"	d
+CH3_HALT_STS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33297;"	d
+CH3_HALT_STS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33296;"	d
+CH3_HALT_STS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33298;"	d
+CH3_HALT_STS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33300;"	d
+CH3_LOWTHOLD_HI	include/ssv6200_aux.h	12264;"	d
+CH3_LOWTHOLD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33854;"	d
+CH3_LOWTHOLD_INT_HI	include/ssv6200_aux.h	12179;"	d
+CH3_LOWTHOLD_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33769;"	d
+CH3_LOWTHOLD_INT_I_MSK	include/ssv6200_aux.h	12177;"	d
+CH3_LOWTHOLD_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33767;"	d
+CH3_LOWTHOLD_INT_MSK	include/ssv6200_aux.h	12176;"	d
+CH3_LOWTHOLD_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33766;"	d
+CH3_LOWTHOLD_INT_SFT	include/ssv6200_aux.h	12178;"	d
+CH3_LOWTHOLD_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33768;"	d
+CH3_LOWTHOLD_INT_SZ	include/ssv6200_aux.h	12180;"	d
+CH3_LOWTHOLD_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33770;"	d
+CH3_LOWTHOLD_I_MSK	include/ssv6200_aux.h	12262;"	d
+CH3_LOWTHOLD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33852;"	d
+CH3_LOWTHOLD_MSK	include/ssv6200_aux.h	12261;"	d
+CH3_LOWTHOLD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33851;"	d
+CH3_LOWTHOLD_SFT	include/ssv6200_aux.h	12263;"	d
+CH3_LOWTHOLD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33853;"	d
+CH3_LOWTHOLD_SZ	include/ssv6200_aux.h	12265;"	d
+CH3_LOWTHOLD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33855;"	d
+CH3_NVLD_HI	include/ssv6200_aux.h	12609;"	d
+CH3_NVLD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34134;"	d
+CH3_NVLD_I_MSK	include/ssv6200_aux.h	12607;"	d
+CH3_NVLD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34132;"	d
+CH3_NVLD_MSK	include/ssv6200_aux.h	12606;"	d
+CH3_NVLD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34131;"	d
+CH3_NVLD_SFT	include/ssv6200_aux.h	12608;"	d
+CH3_NVLD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34133;"	d
+CH3_NVLD_SZ	include/ssv6200_aux.h	12610;"	d
+CH3_NVLD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34135;"	d
+CH3_PRI_HI	include/ssv6200_aux.h	8759;"	d
+CH3_PRI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8514;"	d
+CH3_PRI_I_MSK	include/ssv6200_aux.h	8757;"	d
+CH3_PRI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8512;"	d
+CH3_PRI_MSK	include/ssv6200_aux.h	8756;"	d
+CH3_PRI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8511;"	d
+CH3_PRI_SFT	include/ssv6200_aux.h	8758;"	d
+CH3_PRI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8513;"	d
+CH3_PRI_SZ	include/ssv6200_aux.h	8760;"	d
+CH3_PRI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8515;"	d
+CH3_QUEUE_FLUSH_HI	include/ssv6200_aux.h	11939;"	d
+CH3_QUEUE_FLUSH_I_MSK	include/ssv6200_aux.h	11937;"	d
+CH3_QUEUE_FLUSH_MSK	include/ssv6200_aux.h	11936;"	d
+CH3_QUEUE_FLUSH_SFT	include/ssv6200_aux.h	11938;"	d
+CH3_QUEUE_FLUSH_SZ	include/ssv6200_aux.h	11940;"	d
+CH3_REQ_LOCK_HI	include/ssv6200_aux.h	12564;"	d
+CH3_REQ_LOCK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34089;"	d
+CH3_REQ_LOCK_I_MSK	include/ssv6200_aux.h	12562;"	d
+CH3_REQ_LOCK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34087;"	d
+CH3_REQ_LOCK_MSK	include/ssv6200_aux.h	12561;"	d
+CH3_REQ_LOCK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34086;"	d
+CH3_REQ_LOCK_SFT	include/ssv6200_aux.h	12563;"	d
+CH3_REQ_LOCK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34088;"	d
+CH3_REQ_LOCK_SZ	include/ssv6200_aux.h	12565;"	d
+CH3_REQ_LOCK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34090;"	d
+CH3_STA_PRI_HI	include/ssv6200_aux.h	12499;"	d
+CH3_STA_PRI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34024;"	d
+CH3_STA_PRI_I_MSK	include/ssv6200_aux.h	12497;"	d
+CH3_STA_PRI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34022;"	d
+CH3_STA_PRI_MSK	include/ssv6200_aux.h	12496;"	d
+CH3_STA_PRI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34021;"	d
+CH3_STA_PRI_SFT	include/ssv6200_aux.h	12498;"	d
+CH3_STA_PRI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34023;"	d
+CH3_STA_PRI_SZ	include/ssv6200_aux.h	12500;"	d
+CH3_STA_PRI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34025;"	d
+CH3_WRFF_FLUSH_HI	include/ssv6200_aux.h	12364;"	d
+CH3_WRFF_FLUSH_I_MSK	include/ssv6200_aux.h	12362;"	d
+CH3_WRFF_FLUSH_MSK	include/ssv6200_aux.h	12361;"	d
+CH3_WRFF_FLUSH_SFT	include/ssv6200_aux.h	12363;"	d
+CH3_WRFF_FLUSH_SZ	include/ssv6200_aux.h	12365;"	d
+CH4_FFO_FULL_HI	include/ssv6200_aux.h	12104;"	d
+CH4_FFO_FULL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33694;"	d
+CH4_FFO_FULL_I_MSK	include/ssv6200_aux.h	12102;"	d
+CH4_FFO_FULL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33692;"	d
+CH4_FFO_FULL_MSK	include/ssv6200_aux.h	12101;"	d
+CH4_FFO_FULL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33691;"	d
+CH4_FFO_FULL_SFT	include/ssv6200_aux.h	12103;"	d
+CH4_FFO_FULL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33693;"	d
+CH4_FFO_FULL_SZ	include/ssv6200_aux.h	12105;"	d
+CH4_FFO_FULL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33695;"	d
+CH4_FULL_HI	include/ssv6200_aux.h	11554;"	d
+CH4_FULL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33129;"	d
+CH4_FULL_I_MSK	include/ssv6200_aux.h	11552;"	d
+CH4_FULL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33127;"	d
+CH4_FULL_MSK	include/ssv6200_aux.h	11551;"	d
+CH4_FULL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33126;"	d
+CH4_FULL_SFT	include/ssv6200_aux.h	11553;"	d
+CH4_FULL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33128;"	d
+CH4_FULL_SZ	include/ssv6200_aux.h	11555;"	d
+CH4_FULL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33130;"	d
+CH4_HALT_STS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33304;"	d
+CH4_HALT_STS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33302;"	d
+CH4_HALT_STS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33301;"	d
+CH4_HALT_STS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33303;"	d
+CH4_HALT_STS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33305;"	d
+CH4_LOWTHOLD_HI	include/ssv6200_aux.h	12269;"	d
+CH4_LOWTHOLD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33859;"	d
+CH4_LOWTHOLD_INT_HI	include/ssv6200_aux.h	12184;"	d
+CH4_LOWTHOLD_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33774;"	d
+CH4_LOWTHOLD_INT_I_MSK	include/ssv6200_aux.h	12182;"	d
+CH4_LOWTHOLD_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33772;"	d
+CH4_LOWTHOLD_INT_MSK	include/ssv6200_aux.h	12181;"	d
+CH4_LOWTHOLD_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33771;"	d
+CH4_LOWTHOLD_INT_SFT	include/ssv6200_aux.h	12183;"	d
+CH4_LOWTHOLD_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33773;"	d
+CH4_LOWTHOLD_INT_SZ	include/ssv6200_aux.h	12185;"	d
+CH4_LOWTHOLD_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33775;"	d
+CH4_LOWTHOLD_I_MSK	include/ssv6200_aux.h	12267;"	d
+CH4_LOWTHOLD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33857;"	d
+CH4_LOWTHOLD_MSK	include/ssv6200_aux.h	12266;"	d
+CH4_LOWTHOLD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33856;"	d
+CH4_LOWTHOLD_SFT	include/ssv6200_aux.h	12268;"	d
+CH4_LOWTHOLD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33858;"	d
+CH4_LOWTHOLD_SZ	include/ssv6200_aux.h	12270;"	d
+CH4_LOWTHOLD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33860;"	d
+CH4_QUEUE_FLUSH_HI	include/ssv6200_aux.h	11944;"	d
+CH4_QUEUE_FLUSH_I_MSK	include/ssv6200_aux.h	11942;"	d
+CH4_QUEUE_FLUSH_MSK	include/ssv6200_aux.h	11941;"	d
+CH4_QUEUE_FLUSH_SFT	include/ssv6200_aux.h	11943;"	d
+CH4_QUEUE_FLUSH_SZ	include/ssv6200_aux.h	11945;"	d
+CH4_WRFF_FLUSH_HI	include/ssv6200_aux.h	12369;"	d
+CH4_WRFF_FLUSH_I_MSK	include/ssv6200_aux.h	12367;"	d
+CH4_WRFF_FLUSH_MSK	include/ssv6200_aux.h	12366;"	d
+CH4_WRFF_FLUSH_SFT	include/ssv6200_aux.h	12368;"	d
+CH4_WRFF_FLUSH_SZ	include/ssv6200_aux.h	12370;"	d
+CH5_FFO_FULL_HI	include/ssv6200_aux.h	12109;"	d
+CH5_FFO_FULL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33699;"	d
+CH5_FFO_FULL_I_MSK	include/ssv6200_aux.h	12107;"	d
+CH5_FFO_FULL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33697;"	d
+CH5_FFO_FULL_MSK	include/ssv6200_aux.h	12106;"	d
+CH5_FFO_FULL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33696;"	d
+CH5_FFO_FULL_SFT	include/ssv6200_aux.h	12108;"	d
+CH5_FFO_FULL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33698;"	d
+CH5_FFO_FULL_SZ	include/ssv6200_aux.h	12110;"	d
+CH5_FFO_FULL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33700;"	d
+CH5_FULL_HI	include/ssv6200_aux.h	11559;"	d
+CH5_FULL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33134;"	d
+CH5_FULL_I_MSK	include/ssv6200_aux.h	11557;"	d
+CH5_FULL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33132;"	d
+CH5_FULL_MSK	include/ssv6200_aux.h	11556;"	d
+CH5_FULL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33131;"	d
+CH5_FULL_SFT	include/ssv6200_aux.h	11558;"	d
+CH5_FULL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33133;"	d
+CH5_FULL_SZ	include/ssv6200_aux.h	11560;"	d
+CH5_FULL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33135;"	d
+CH5_HALT_STS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33309;"	d
+CH5_HALT_STS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33307;"	d
+CH5_HALT_STS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33306;"	d
+CH5_HALT_STS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33308;"	d
+CH5_HALT_STS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33310;"	d
+CH5_LOWTHOLD_HI	include/ssv6200_aux.h	12274;"	d
+CH5_LOWTHOLD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33864;"	d
+CH5_LOWTHOLD_INT_HI	include/ssv6200_aux.h	12189;"	d
+CH5_LOWTHOLD_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33779;"	d
+CH5_LOWTHOLD_INT_I_MSK	include/ssv6200_aux.h	12187;"	d
+CH5_LOWTHOLD_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33777;"	d
+CH5_LOWTHOLD_INT_MSK	include/ssv6200_aux.h	12186;"	d
+CH5_LOWTHOLD_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33776;"	d
+CH5_LOWTHOLD_INT_SFT	include/ssv6200_aux.h	12188;"	d
+CH5_LOWTHOLD_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33778;"	d
+CH5_LOWTHOLD_INT_SZ	include/ssv6200_aux.h	12190;"	d
+CH5_LOWTHOLD_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33780;"	d
+CH5_LOWTHOLD_I_MSK	include/ssv6200_aux.h	12272;"	d
+CH5_LOWTHOLD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33862;"	d
+CH5_LOWTHOLD_MSK	include/ssv6200_aux.h	12271;"	d
+CH5_LOWTHOLD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33861;"	d
+CH5_LOWTHOLD_SFT	include/ssv6200_aux.h	12273;"	d
+CH5_LOWTHOLD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33863;"	d
+CH5_LOWTHOLD_SZ	include/ssv6200_aux.h	12275;"	d
+CH5_LOWTHOLD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33865;"	d
+CH5_QUEUE_FLUSH_HI	include/ssv6200_aux.h	11949;"	d
+CH5_QUEUE_FLUSH_I_MSK	include/ssv6200_aux.h	11947;"	d
+CH5_QUEUE_FLUSH_MSK	include/ssv6200_aux.h	11946;"	d
+CH5_QUEUE_FLUSH_SFT	include/ssv6200_aux.h	11948;"	d
+CH5_QUEUE_FLUSH_SZ	include/ssv6200_aux.h	11950;"	d
+CH5_WRFF_FLUSH_HI	include/ssv6200_aux.h	12374;"	d
+CH5_WRFF_FLUSH_I_MSK	include/ssv6200_aux.h	12372;"	d
+CH5_WRFF_FLUSH_MSK	include/ssv6200_aux.h	12371;"	d
+CH5_WRFF_FLUSH_SFT	include/ssv6200_aux.h	12373;"	d
+CH5_WRFF_FLUSH_SZ	include/ssv6200_aux.h	12375;"	d
+CH6_FFO_FULL_HI	include/ssv6200_aux.h	12114;"	d
+CH6_FFO_FULL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33704;"	d
+CH6_FFO_FULL_I_MSK	include/ssv6200_aux.h	12112;"	d
+CH6_FFO_FULL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33702;"	d
+CH6_FFO_FULL_MSK	include/ssv6200_aux.h	12111;"	d
+CH6_FFO_FULL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33701;"	d
+CH6_FFO_FULL_SFT	include/ssv6200_aux.h	12113;"	d
+CH6_FFO_FULL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33703;"	d
+CH6_FFO_FULL_SZ	include/ssv6200_aux.h	12115;"	d
+CH6_FFO_FULL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33705;"	d
+CH6_FULL_HI	include/ssv6200_aux.h	11564;"	d
+CH6_FULL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33139;"	d
+CH6_FULL_I_MSK	include/ssv6200_aux.h	11562;"	d
+CH6_FULL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33137;"	d
+CH6_FULL_MSK	include/ssv6200_aux.h	11561;"	d
+CH6_FULL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33136;"	d
+CH6_FULL_SFT	include/ssv6200_aux.h	11563;"	d
+CH6_FULL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33138;"	d
+CH6_FULL_SZ	include/ssv6200_aux.h	11565;"	d
+CH6_FULL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33140;"	d
+CH6_HALT_STS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33314;"	d
+CH6_HALT_STS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33312;"	d
+CH6_HALT_STS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33311;"	d
+CH6_HALT_STS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33313;"	d
+CH6_HALT_STS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33315;"	d
+CH6_LOWTHOLD_HI	include/ssv6200_aux.h	12279;"	d
+CH6_LOWTHOLD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33869;"	d
+CH6_LOWTHOLD_INT_HI	include/ssv6200_aux.h	12194;"	d
+CH6_LOWTHOLD_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33784;"	d
+CH6_LOWTHOLD_INT_I_MSK	include/ssv6200_aux.h	12192;"	d
+CH6_LOWTHOLD_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33782;"	d
+CH6_LOWTHOLD_INT_MSK	include/ssv6200_aux.h	12191;"	d
+CH6_LOWTHOLD_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33781;"	d
+CH6_LOWTHOLD_INT_SFT	include/ssv6200_aux.h	12193;"	d
+CH6_LOWTHOLD_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33783;"	d
+CH6_LOWTHOLD_INT_SZ	include/ssv6200_aux.h	12195;"	d
+CH6_LOWTHOLD_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33785;"	d
+CH6_LOWTHOLD_I_MSK	include/ssv6200_aux.h	12277;"	d
+CH6_LOWTHOLD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33867;"	d
+CH6_LOWTHOLD_MSK	include/ssv6200_aux.h	12276;"	d
+CH6_LOWTHOLD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33866;"	d
+CH6_LOWTHOLD_SFT	include/ssv6200_aux.h	12278;"	d
+CH6_LOWTHOLD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33868;"	d
+CH6_LOWTHOLD_SZ	include/ssv6200_aux.h	12280;"	d
+CH6_LOWTHOLD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33870;"	d
+CH6_QUEUE_FLUSH_HI	include/ssv6200_aux.h	11954;"	d
+CH6_QUEUE_FLUSH_I_MSK	include/ssv6200_aux.h	11952;"	d
+CH6_QUEUE_FLUSH_MSK	include/ssv6200_aux.h	11951;"	d
+CH6_QUEUE_FLUSH_SFT	include/ssv6200_aux.h	11953;"	d
+CH6_QUEUE_FLUSH_SZ	include/ssv6200_aux.h	11955;"	d
+CH6_WRFF_FLUSH_HI	include/ssv6200_aux.h	12379;"	d
+CH6_WRFF_FLUSH_I_MSK	include/ssv6200_aux.h	12377;"	d
+CH6_WRFF_FLUSH_MSK	include/ssv6200_aux.h	12376;"	d
+CH6_WRFF_FLUSH_SFT	include/ssv6200_aux.h	12378;"	d
+CH6_WRFF_FLUSH_SZ	include/ssv6200_aux.h	12380;"	d
+CH7_FFO_FULL_HI	include/ssv6200_aux.h	12119;"	d
+CH7_FFO_FULL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33709;"	d
+CH7_FFO_FULL_I_MSK	include/ssv6200_aux.h	12117;"	d
+CH7_FFO_FULL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33707;"	d
+CH7_FFO_FULL_MSK	include/ssv6200_aux.h	12116;"	d
+CH7_FFO_FULL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33706;"	d
+CH7_FFO_FULL_SFT	include/ssv6200_aux.h	12118;"	d
+CH7_FFO_FULL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33708;"	d
+CH7_FFO_FULL_SZ	include/ssv6200_aux.h	12120;"	d
+CH7_FFO_FULL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33710;"	d
+CH7_FULL_HI	include/ssv6200_aux.h	11569;"	d
+CH7_FULL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33144;"	d
+CH7_FULL_I_MSK	include/ssv6200_aux.h	11567;"	d
+CH7_FULL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33142;"	d
+CH7_FULL_MSK	include/ssv6200_aux.h	11566;"	d
+CH7_FULL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33141;"	d
+CH7_FULL_SFT	include/ssv6200_aux.h	11568;"	d
+CH7_FULL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33143;"	d
+CH7_FULL_SZ	include/ssv6200_aux.h	11570;"	d
+CH7_FULL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33145;"	d
+CH7_HALT_STS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33319;"	d
+CH7_HALT_STS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33317;"	d
+CH7_HALT_STS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33316;"	d
+CH7_HALT_STS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33318;"	d
+CH7_HALT_STS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33320;"	d
+CH7_LOWTHOLD_HI	include/ssv6200_aux.h	12284;"	d
+CH7_LOWTHOLD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33874;"	d
+CH7_LOWTHOLD_INT_HI	include/ssv6200_aux.h	12199;"	d
+CH7_LOWTHOLD_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33789;"	d
+CH7_LOWTHOLD_INT_I_MSK	include/ssv6200_aux.h	12197;"	d
+CH7_LOWTHOLD_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33787;"	d
+CH7_LOWTHOLD_INT_MSK	include/ssv6200_aux.h	12196;"	d
+CH7_LOWTHOLD_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33786;"	d
+CH7_LOWTHOLD_INT_SFT	include/ssv6200_aux.h	12198;"	d
+CH7_LOWTHOLD_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33788;"	d
+CH7_LOWTHOLD_INT_SZ	include/ssv6200_aux.h	12200;"	d
+CH7_LOWTHOLD_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33790;"	d
+CH7_LOWTHOLD_I_MSK	include/ssv6200_aux.h	12282;"	d
+CH7_LOWTHOLD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33872;"	d
+CH7_LOWTHOLD_MSK	include/ssv6200_aux.h	12281;"	d
+CH7_LOWTHOLD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33871;"	d
+CH7_LOWTHOLD_SFT	include/ssv6200_aux.h	12283;"	d
+CH7_LOWTHOLD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33873;"	d
+CH7_LOWTHOLD_SZ	include/ssv6200_aux.h	12285;"	d
+CH7_LOWTHOLD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33875;"	d
+CH7_QUEUE_FLUSH_HI	include/ssv6200_aux.h	11959;"	d
+CH7_QUEUE_FLUSH_I_MSK	include/ssv6200_aux.h	11957;"	d
+CH7_QUEUE_FLUSH_MSK	include/ssv6200_aux.h	11956;"	d
+CH7_QUEUE_FLUSH_SFT	include/ssv6200_aux.h	11958;"	d
+CH7_QUEUE_FLUSH_SZ	include/ssv6200_aux.h	11960;"	d
+CH7_WRFF_FLUSH_HI	include/ssv6200_aux.h	12384;"	d
+CH7_WRFF_FLUSH_I_MSK	include/ssv6200_aux.h	12382;"	d
+CH7_WRFF_FLUSH_MSK	include/ssv6200_aux.h	12381;"	d
+CH7_WRFF_FLUSH_SFT	include/ssv6200_aux.h	12383;"	d
+CH7_WRFF_FLUSH_SZ	include/ssv6200_aux.h	12385;"	d
+CH8_FFO_FULL_HI	include/ssv6200_aux.h	12124;"	d
+CH8_FFO_FULL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33714;"	d
+CH8_FFO_FULL_I_MSK	include/ssv6200_aux.h	12122;"	d
+CH8_FFO_FULL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33712;"	d
+CH8_FFO_FULL_MSK	include/ssv6200_aux.h	12121;"	d
+CH8_FFO_FULL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33711;"	d
+CH8_FFO_FULL_SFT	include/ssv6200_aux.h	12123;"	d
+CH8_FFO_FULL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33713;"	d
+CH8_FFO_FULL_SZ	include/ssv6200_aux.h	12125;"	d
+CH8_FFO_FULL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33715;"	d
+CH8_FULL_HI	include/ssv6200_aux.h	11574;"	d
+CH8_FULL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33149;"	d
+CH8_FULL_I_MSK	include/ssv6200_aux.h	11572;"	d
+CH8_FULL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33147;"	d
+CH8_FULL_MSK	include/ssv6200_aux.h	11571;"	d
+CH8_FULL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33146;"	d
+CH8_FULL_SFT	include/ssv6200_aux.h	11573;"	d
+CH8_FULL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33148;"	d
+CH8_FULL_SZ	include/ssv6200_aux.h	11575;"	d
+CH8_FULL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33150;"	d
+CH8_HALT_STS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33324;"	d
+CH8_HALT_STS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33322;"	d
+CH8_HALT_STS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33321;"	d
+CH8_HALT_STS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33323;"	d
+CH8_HALT_STS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33325;"	d
+CH8_LOWTHOLD_HI	include/ssv6200_aux.h	12289;"	d
+CH8_LOWTHOLD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33879;"	d
+CH8_LOWTHOLD_INT_HI	include/ssv6200_aux.h	12204;"	d
+CH8_LOWTHOLD_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33794;"	d
+CH8_LOWTHOLD_INT_I_MSK	include/ssv6200_aux.h	12202;"	d
+CH8_LOWTHOLD_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33792;"	d
+CH8_LOWTHOLD_INT_MSK	include/ssv6200_aux.h	12201;"	d
+CH8_LOWTHOLD_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33791;"	d
+CH8_LOWTHOLD_INT_SFT	include/ssv6200_aux.h	12203;"	d
+CH8_LOWTHOLD_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33793;"	d
+CH8_LOWTHOLD_INT_SZ	include/ssv6200_aux.h	12205;"	d
+CH8_LOWTHOLD_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33795;"	d
+CH8_LOWTHOLD_I_MSK	include/ssv6200_aux.h	12287;"	d
+CH8_LOWTHOLD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33877;"	d
+CH8_LOWTHOLD_MSK	include/ssv6200_aux.h	12286;"	d
+CH8_LOWTHOLD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33876;"	d
+CH8_LOWTHOLD_SFT	include/ssv6200_aux.h	12288;"	d
+CH8_LOWTHOLD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33878;"	d
+CH8_LOWTHOLD_SZ	include/ssv6200_aux.h	12290;"	d
+CH8_LOWTHOLD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33880;"	d
+CH8_QUEUE_FLUSH_HI	include/ssv6200_aux.h	11964;"	d
+CH8_QUEUE_FLUSH_I_MSK	include/ssv6200_aux.h	11962;"	d
+CH8_QUEUE_FLUSH_MSK	include/ssv6200_aux.h	11961;"	d
+CH8_QUEUE_FLUSH_SFT	include/ssv6200_aux.h	11963;"	d
+CH8_QUEUE_FLUSH_SZ	include/ssv6200_aux.h	11965;"	d
+CH8_WRFF_FLUSH_HI	include/ssv6200_aux.h	12389;"	d
+CH8_WRFF_FLUSH_I_MSK	include/ssv6200_aux.h	12387;"	d
+CH8_WRFF_FLUSH_MSK	include/ssv6200_aux.h	12386;"	d
+CH8_WRFF_FLUSH_SFT	include/ssv6200_aux.h	12388;"	d
+CH8_WRFF_FLUSH_SZ	include/ssv6200_aux.h	12390;"	d
+CH9_FFO_FULL_HI	include/ssv6200_aux.h	12129;"	d
+CH9_FFO_FULL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33719;"	d
+CH9_FFO_FULL_I_MSK	include/ssv6200_aux.h	12127;"	d
+CH9_FFO_FULL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33717;"	d
+CH9_FFO_FULL_MSK	include/ssv6200_aux.h	12126;"	d
+CH9_FFO_FULL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33716;"	d
+CH9_FFO_FULL_SFT	include/ssv6200_aux.h	12128;"	d
+CH9_FFO_FULL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33718;"	d
+CH9_FFO_FULL_SZ	include/ssv6200_aux.h	12130;"	d
+CH9_FFO_FULL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33720;"	d
+CH9_FULL_HI	include/ssv6200_aux.h	11579;"	d
+CH9_FULL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33154;"	d
+CH9_FULL_I_MSK	include/ssv6200_aux.h	11577;"	d
+CH9_FULL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33152;"	d
+CH9_FULL_MSK	include/ssv6200_aux.h	11576;"	d
+CH9_FULL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33151;"	d
+CH9_FULL_SFT	include/ssv6200_aux.h	11578;"	d
+CH9_FULL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33153;"	d
+CH9_FULL_SZ	include/ssv6200_aux.h	11580;"	d
+CH9_FULL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33155;"	d
+CH9_HALT_STS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33329;"	d
+CH9_HALT_STS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33327;"	d
+CH9_HALT_STS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33326;"	d
+CH9_HALT_STS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33328;"	d
+CH9_HALT_STS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33330;"	d
+CH9_LOWTHOLD_HI	include/ssv6200_aux.h	12294;"	d
+CH9_LOWTHOLD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33884;"	d
+CH9_LOWTHOLD_INT_HI	include/ssv6200_aux.h	12209;"	d
+CH9_LOWTHOLD_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33799;"	d
+CH9_LOWTHOLD_INT_I_MSK	include/ssv6200_aux.h	12207;"	d
+CH9_LOWTHOLD_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33797;"	d
+CH9_LOWTHOLD_INT_MSK	include/ssv6200_aux.h	12206;"	d
+CH9_LOWTHOLD_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33796;"	d
+CH9_LOWTHOLD_INT_SFT	include/ssv6200_aux.h	12208;"	d
+CH9_LOWTHOLD_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33798;"	d
+CH9_LOWTHOLD_INT_SZ	include/ssv6200_aux.h	12210;"	d
+CH9_LOWTHOLD_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33800;"	d
+CH9_LOWTHOLD_I_MSK	include/ssv6200_aux.h	12292;"	d
+CH9_LOWTHOLD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33882;"	d
+CH9_LOWTHOLD_MSK	include/ssv6200_aux.h	12291;"	d
+CH9_LOWTHOLD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33881;"	d
+CH9_LOWTHOLD_SFT	include/ssv6200_aux.h	12293;"	d
+CH9_LOWTHOLD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33883;"	d
+CH9_LOWTHOLD_SZ	include/ssv6200_aux.h	12295;"	d
+CH9_LOWTHOLD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33885;"	d
+CH9_QUEUE_FLUSH_HI	include/ssv6200_aux.h	11969;"	d
+CH9_QUEUE_FLUSH_I_MSK	include/ssv6200_aux.h	11967;"	d
+CH9_QUEUE_FLUSH_MSK	include/ssv6200_aux.h	11966;"	d
+CH9_QUEUE_FLUSH_SFT	include/ssv6200_aux.h	11968;"	d
+CH9_QUEUE_FLUSH_SZ	include/ssv6200_aux.h	11970;"	d
+CH9_WRFF_FLUSH_HI	include/ssv6200_aux.h	12394;"	d
+CH9_WRFF_FLUSH_I_MSK	include/ssv6200_aux.h	12392;"	d
+CH9_WRFF_FLUSH_MSK	include/ssv6200_aux.h	12391;"	d
+CH9_WRFF_FLUSH_SFT	include/ssv6200_aux.h	12393;"	d
+CH9_WRFF_FLUSH_SZ	include/ssv6200_aux.h	12395;"	d
+CHAN2G	smac/init.c	83;"	d	file:
+CHAN5G	smac/init.c	89;"	d	file:
+CHECKSUM_BLOCK_SIZE	include/ssv6xxx_common.h	386;"	d
+CHECK_IO_RET	hwif/sdio/sdio.c	47;"	d	file:
+CHECK_IQK	smac/hal/ssv6006c/turismo_common.h	3462;"	d
+CHECK_IQK	smac/hal/ssv6006c/turismo_common.h	3465;"	d
+CHECK_IQK	smac/hal/ssv6006c/turismo_common.h	3475;"	d
+CHECK_PADPD	smac/hal/ssv6006c/turismo_common.h	3396;"	d
+CHECK_PADPD_GAIN	smac/hal/ssv6006c/turismo_common.h	3199;"	d
+CHECK_PADPD_IQK	smac/hal/ssv6006c/turismo_common.h	3487;"	d
+CHECK_RET	bridge/sdiobridge.c	49;"	d	file:
+CHECK_RET	hci_wrapper/ssv_huw.c	33;"	d	file:
+CHECK_SPUR	smac/hal/ssv6006c/turismo_common.h	3513;"	d
+CHECK_SUM_FAIL_HI	include/ssv6200_aux.h	5659;"	d
+CHECK_SUM_FAIL_I_MSK	include/ssv6200_aux.h	5657;"	d
+CHECK_SUM_FAIL_MSK	include/ssv6200_aux.h	5656;"	d
+CHECK_SUM_FAIL_SFT	include/ssv6200_aux.h	5658;"	d
+CHECK_SUM_FAIL_SZ	include/ssv6200_aux.h	5660;"	d
+CHECK_SUM_HI	include/ssv6200_aux.h	6374;"	d
+CHECK_SUM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5619;"	d
+CHECK_SUM_I_MSK	include/ssv6200_aux.h	6372;"	d
+CHECK_SUM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5617;"	d
+CHECK_SUM_MSK	include/ssv6200_aux.h	6371;"	d
+CHECK_SUM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5616;"	d
+CHECK_SUM_SFT	include/ssv6200_aux.h	6373;"	d
+CHECK_SUM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5618;"	d
+CHECK_SUM_SZ	include/ssv6200_aux.h	6375;"	d
+CHECK_SUM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5620;"	d
+CHECK_SUM_TAG_HI	include/ssv6200_aux.h	5754;"	d
+CHECK_SUM_TAG_I_MSK	include/ssv6200_aux.h	5752;"	d
+CHECK_SUM_TAG_MSK	include/ssv6200_aux.h	5751;"	d
+CHECK_SUM_TAG_SFT	include/ssv6200_aux.h	5753;"	d
+CHECK_SUM_TAG_SZ	include/ssv6200_aux.h	5755;"	d
+CHIP_DATE_00HHMMSS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1599;"	d
+CHIP_DATE_00HHMMSS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1597;"	d
+CHIP_DATE_00HHMMSS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1596;"	d
+CHIP_DATE_00HHMMSS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1598;"	d
+CHIP_DATE_00HHMMSS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1600;"	d
+CHIP_DATE_YYYYMMDD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1594;"	d
+CHIP_DATE_YYYYMMDD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1592;"	d
+CHIP_DATE_YYYYMMDD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1591;"	d
+CHIP_DATE_YYYYMMDD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1593;"	d
+CHIP_DATE_YYYYMMDD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1595;"	d
+CHIP_GITSHA_127_96_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1619;"	d
+CHIP_GITSHA_127_96_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1617;"	d
+CHIP_GITSHA_127_96_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1616;"	d
+CHIP_GITSHA_127_96_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1618;"	d
+CHIP_GITSHA_127_96_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1620;"	d
+CHIP_GITSHA_159_128_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1624;"	d
+CHIP_GITSHA_159_128_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1622;"	d
+CHIP_GITSHA_159_128_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1621;"	d
+CHIP_GITSHA_159_128_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1623;"	d
+CHIP_GITSHA_159_128_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1625;"	d
+CHIP_GITSHA_31_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1604;"	d
+CHIP_GITSHA_31_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1602;"	d
+CHIP_GITSHA_31_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1601;"	d
+CHIP_GITSHA_31_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1603;"	d
+CHIP_GITSHA_31_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1605;"	d
+CHIP_GITSHA_63_32_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1609;"	d
+CHIP_GITSHA_63_32_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1607;"	d
+CHIP_GITSHA_63_32_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1606;"	d
+CHIP_GITSHA_63_32_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1608;"	d
+CHIP_GITSHA_63_32_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1610;"	d
+CHIP_GITSHA_95_64_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1614;"	d
+CHIP_GITSHA_95_64_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1612;"	d
+CHIP_GITSHA_95_64_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1611;"	d
+CHIP_GITSHA_95_64_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1613;"	d
+CHIP_GITSHA_95_64_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1615;"	d
+CHIP_ID_127_96_HI	include/ssv6200_aux.h	174;"	d
+CHIP_ID_127_96_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1124;"	d
+CHIP_ID_127_96_I_MSK	include/ssv6200_aux.h	172;"	d
+CHIP_ID_127_96_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1122;"	d
+CHIP_ID_127_96_MSK	include/ssv6200_aux.h	171;"	d
+CHIP_ID_127_96_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1121;"	d
+CHIP_ID_127_96_SFT	include/ssv6200_aux.h	173;"	d
+CHIP_ID_127_96_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1123;"	d
+CHIP_ID_127_96_SZ	include/ssv6200_aux.h	175;"	d
+CHIP_ID_127_96_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1125;"	d
+CHIP_ID_31_0_HI	include/ssv6200_aux.h	159;"	d
+CHIP_ID_31_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1109;"	d
+CHIP_ID_31_0_I_MSK	include/ssv6200_aux.h	157;"	d
+CHIP_ID_31_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1107;"	d
+CHIP_ID_31_0_MSK	include/ssv6200_aux.h	156;"	d
+CHIP_ID_31_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1106;"	d
+CHIP_ID_31_0_SFT	include/ssv6200_aux.h	158;"	d
+CHIP_ID_31_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1108;"	d
+CHIP_ID_31_0_SZ	include/ssv6200_aux.h	160;"	d
+CHIP_ID_31_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1110;"	d
+CHIP_ID_63_32_HI	include/ssv6200_aux.h	164;"	d
+CHIP_ID_63_32_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1114;"	d
+CHIP_ID_63_32_I_MSK	include/ssv6200_aux.h	162;"	d
+CHIP_ID_63_32_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1112;"	d
+CHIP_ID_63_32_MSK	include/ssv6200_aux.h	161;"	d
+CHIP_ID_63_32_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1111;"	d
+CHIP_ID_63_32_SFT	include/ssv6200_aux.h	163;"	d
+CHIP_ID_63_32_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1113;"	d
+CHIP_ID_63_32_SZ	include/ssv6200_aux.h	165;"	d
+CHIP_ID_63_32_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1115;"	d
+CHIP_ID_95_64_HI	include/ssv6200_aux.h	169;"	d
+CHIP_ID_95_64_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1119;"	d
+CHIP_ID_95_64_I_MSK	include/ssv6200_aux.h	167;"	d
+CHIP_ID_95_64_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1117;"	d
+CHIP_ID_95_64_MSK	include/ssv6200_aux.h	166;"	d
+CHIP_ID_95_64_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1116;"	d
+CHIP_ID_95_64_SFT	include/ssv6200_aux.h	168;"	d
+CHIP_ID_95_64_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1118;"	d
+CHIP_ID_95_64_SZ	include/ssv6200_aux.h	170;"	d
+CHIP_ID_95_64_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1120;"	d
+CHIP_INFO_FPGA_TAG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1644;"	d
+CHIP_INFO_FPGA_TAG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1642;"	d
+CHIP_INFO_FPGA_TAG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1641;"	d
+CHIP_INFO_FPGA_TAG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1643;"	d
+CHIP_INFO_FPGA_TAG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1645;"	d
+CHIP_INFO_ID_31_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1574;"	d
+CHIP_INFO_ID_31_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1572;"	d
+CHIP_INFO_ID_31_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1571;"	d
+CHIP_INFO_ID_31_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1573;"	d
+CHIP_INFO_ID_31_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1575;"	d
+CHIP_INFO_ID_63_32_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1579;"	d
+CHIP_INFO_ID_63_32_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1577;"	d
+CHIP_INFO_ID_63_32_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1576;"	d
+CHIP_INFO_ID_63_32_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1578;"	d
+CHIP_INFO_ID_63_32_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1580;"	d
+CHIP_TYPE_CHIP	smac/hal/ssv6006c/ssv6006_mac.h	24;"	d
+CHIP_TYPE_FPGA	smac/hal/ssv6006c/ssv6006_mac.h	25;"	d
+CHIP_TYPE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1589;"	d
+CHIP_TYPE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1587;"	d
+CHIP_TYPE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1586;"	d
+CHIP_TYPE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1588;"	d
+CHIP_TYPE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1590;"	d
+CHIP_VER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1584;"	d
+CHIP_VER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1582;"	d
+CHIP_VER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1581;"	d
+CHIP_VER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1583;"	d
+CHIP_VER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1585;"	d
+CH_ARB_EN_HI	include/ssv6200_aux.h	12764;"	d
+CH_ARB_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34289;"	d
+CH_ARB_EN_I_MSK	include/ssv6200_aux.h	12762;"	d
+CH_ARB_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34287;"	d
+CH_ARB_EN_MSK	include/ssv6200_aux.h	12761;"	d
+CH_ARB_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34286;"	d
+CH_ARB_EN_SFT	include/ssv6200_aux.h	12763;"	d
+CH_ARB_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34288;"	d
+CH_ARB_EN_SZ	include/ssv6200_aux.h	12765;"	d
+CH_ARB_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34290;"	d
+CH_PRI1_HI	include/ssv6200_aux.h	12769;"	d
+CH_PRI1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34294;"	d
+CH_PRI1_I_MSK	include/ssv6200_aux.h	12767;"	d
+CH_PRI1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34292;"	d
+CH_PRI1_MSK	include/ssv6200_aux.h	12766;"	d
+CH_PRI1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34291;"	d
+CH_PRI1_SFT	include/ssv6200_aux.h	12768;"	d
+CH_PRI1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34293;"	d
+CH_PRI1_SZ	include/ssv6200_aux.h	12770;"	d
+CH_PRI1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34295;"	d
+CH_PRI2_HI	include/ssv6200_aux.h	12774;"	d
+CH_PRI2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34299;"	d
+CH_PRI2_I_MSK	include/ssv6200_aux.h	12772;"	d
+CH_PRI2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34297;"	d
+CH_PRI2_MSK	include/ssv6200_aux.h	12771;"	d
+CH_PRI2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34296;"	d
+CH_PRI2_SFT	include/ssv6200_aux.h	12773;"	d
+CH_PRI2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34298;"	d
+CH_PRI2_SZ	include/ssv6200_aux.h	12775;"	d
+CH_PRI2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34300;"	d
+CH_PRI3_HI	include/ssv6200_aux.h	12779;"	d
+CH_PRI3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34304;"	d
+CH_PRI3_I_MSK	include/ssv6200_aux.h	12777;"	d
+CH_PRI3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34302;"	d
+CH_PRI3_MSK	include/ssv6200_aux.h	12776;"	d
+CH_PRI3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34301;"	d
+CH_PRI3_SFT	include/ssv6200_aux.h	12778;"	d
+CH_PRI3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34303;"	d
+CH_PRI3_SZ	include/ssv6200_aux.h	12780;"	d
+CH_PRI3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34305;"	d
+CH_PRI4_HI	include/ssv6200_aux.h	12784;"	d
+CH_PRI4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34309;"	d
+CH_PRI4_I_MSK	include/ssv6200_aux.h	12782;"	d
+CH_PRI4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34307;"	d
+CH_PRI4_MSK	include/ssv6200_aux.h	12781;"	d
+CH_PRI4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34306;"	d
+CH_PRI4_SFT	include/ssv6200_aux.h	12783;"	d
+CH_PRI4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34308;"	d
+CH_PRI4_SZ	include/ssv6200_aux.h	12785;"	d
+CH_PRI4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34310;"	d
+CH_STA0_DUR_HI	include/ssv6200_aux.h	7794;"	d
+CH_STA0_DUR_I_MSK	include/ssv6200_aux.h	7792;"	d
+CH_STA0_DUR_MSK	include/ssv6200_aux.h	7791;"	d
+CH_STA0_DUR_SFT	include/ssv6200_aux.h	7793;"	d
+CH_STA0_DUR_SZ	include/ssv6200_aux.h	7795;"	d
+CH_STA1_DUR_HI	include/ssv6200_aux.h	7849;"	d
+CH_STA1_DUR_I_MSK	include/ssv6200_aux.h	7847;"	d
+CH_STA1_DUR_MSK	include/ssv6200_aux.h	7846;"	d
+CH_STA1_DUR_SFT	include/ssv6200_aux.h	7848;"	d
+CH_STA1_DUR_SZ	include/ssv6200_aux.h	7850;"	d
+CH_STA2_DUR_HI	include/ssv6200_aux.h	7854;"	d
+CH_STA2_DUR_I_MSK	include/ssv6200_aux.h	7852;"	d
+CH_STA2_DUR_MSK	include/ssv6200_aux.h	7851;"	d
+CH_STA2_DUR_SFT	include/ssv6200_aux.h	7853;"	d
+CH_STA2_DUR_SZ	include/ssv6200_aux.h	7855;"	d
+CH_STA3_DUR_HI	include/ssv6200_aux.h	7884;"	d
+CH_STA3_DUR_I_MSK	include/ssv6200_aux.h	7882;"	d
+CH_STA3_DUR_MSK	include/ssv6200_aux.h	7881;"	d
+CH_STA3_DUR_SFT	include/ssv6200_aux.h	7883;"	d
+CH_STA3_DUR_SZ	include/ssv6200_aux.h	7885;"	d
+CH_STA4_DUR_HI	include/ssv6200_aux.h	7889;"	d
+CH_STA4_DUR_I_MSK	include/ssv6200_aux.h	7887;"	d
+CH_STA4_DUR_MSK	include/ssv6200_aux.h	7886;"	d
+CH_STA4_DUR_SFT	include/ssv6200_aux.h	7888;"	d
+CH_STA4_DUR_SZ	include/ssv6200_aux.h	7890;"	d
+CH_ST_FSM_HI	include/ssv6200_aux.h	7709;"	d
+CH_ST_FSM_I_MSK	include/ssv6200_aux.h	7707;"	d
+CH_ST_FSM_MSK	include/ssv6200_aux.h	7706;"	d
+CH_ST_FSM_SFT	include/ssv6200_aux.h	7708;"	d
+CH_ST_FSM_SZ	include/ssv6200_aux.h	7710;"	d
+CK_INCREMENT	smac/wapi_sms4.c	31;"	d	file:
+CK_SEL_1_0_HI	include/ssv6200_aux.h	179;"	d
+CK_SEL_1_0_I_MSK	include/ssv6200_aux.h	177;"	d
+CK_SEL_1_0_MSK	include/ssv6200_aux.h	176;"	d
+CK_SEL_1_0_SFT	include/ssv6200_aux.h	178;"	d
+CK_SEL_1_0_SZ	include/ssv6200_aux.h	180;"	d
+CK_SEL_2_HI	include/ssv6200_aux.h	184;"	d
+CK_SEL_2_I_MSK	include/ssv6200_aux.h	182;"	d
+CK_SEL_2_MSK	include/ssv6200_aux.h	181;"	d
+CK_SEL_2_SFT	include/ssv6200_aux.h	183;"	d
+CK_SEL_2_SZ	include/ssv6200_aux.h	185;"	d
+CLEAR_BIT	smac/ap.c	39;"	d	file:
+CLI_ARG_SIZE	ssvdevice/ssv_cmd.h	18;"	d
+CLI_VERSION	ssvdevice/ssv_cmd.c	1442;"	d	file:
+CLK_32K	smac/hal/ssv6006c/turismo_common.h	224;"	d
+CLK_40M	smac/hal/ssv6006c/turismo_common.h	226;"	d
+CLK_80M	smac/hal/ssv6006c/turismo_common.h	227;"	d
+CLK_80M_PHY	smac/hal/ssv6006c/ssv6006C_mac.c	926;"	d	file:
+CLK_DIGI_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1129;"	d
+CLK_DIGI_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1127;"	d
+CLK_DIGI_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1126;"	d
+CLK_DIGI_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1128;"	d
+CLK_DIGI_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1130;"	d
+CLK_EN_160M_PHY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1304;"	d
+CLK_EN_160M_PHY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1302;"	d
+CLK_EN_160M_PHY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1301;"	d
+CLK_EN_160M_PHY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1303;"	d
+CLK_EN_160M_PHY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1305;"	d
+CLK_EN_CPUN10_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1554;"	d
+CLK_EN_CPUN10_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1552;"	d
+CLK_EN_CPUN10_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1551;"	d
+CLK_EN_CPUN10_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1553;"	d
+CLK_EN_CPUN10_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1555;"	d
+CLK_EN_MBIST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1314;"	d
+CLK_EN_MBIST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1312;"	d
+CLK_EN_MBIST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1311;"	d
+CLK_EN_MBIST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1313;"	d
+CLK_EN_MBIST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1315;"	d
+CLK_EN_PHYRF40M_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1294;"	d
+CLK_EN_PHYRF40M_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1292;"	d
+CLK_EN_PHYRF40M_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1291;"	d
+CLK_EN_PHYRF40M_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1293;"	d
+CLK_EN_PHYRF40M_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1295;"	d
+CLK_EN_PHYRF80M_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1299;"	d
+CLK_EN_PHYRF80M_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1297;"	d
+CLK_EN_PHYRF80M_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1296;"	d
+CLK_EN_PHYRF80M_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1298;"	d
+CLK_EN_PHYRF80M_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1300;"	d
+CLK_EN_USB_CTRLUTMI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1274;"	d
+CLK_EN_USB_CTRLUTMI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1272;"	d
+CLK_EN_USB_CTRLUTMI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1271;"	d
+CLK_EN_USB_CTRLUTMI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1273;"	d
+CLK_EN_USB_CTRLUTMI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1275;"	d
+CLK_EN_USB_PHY30M_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1269;"	d
+CLK_EN_USB_PHY30M_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1267;"	d
+CLK_EN_USB_PHY30M_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1266;"	d
+CLK_EN_USB_PHY30M_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1268;"	d
+CLK_EN_USB_PHY30M_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1270;"	d
+CLK_FBUS_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1404;"	d
+CLK_FBUS_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1402;"	d
+CLK_FBUS_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1401;"	d
+CLK_FBUS_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1403;"	d
+CLK_FBUS_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1405;"	d
+CLK_SRC_MAX	smac/dev.h	/^    CLK_SRC_MAX,$/;"	e	enum:__anon13
+CLK_SRC_OSC	smac/dev.h	/^ CLK_SRC_OSC,$/;"	e	enum:__anon13
+CLK_SRC_RTC	smac/dev.h	/^    CLK_SRC_RTC,$/;"	e	enum:__anon13
+CLK_SRC_SYNTH_40M	smac/dev.h	/^    CLK_SRC_SYNTH_40M,$/;"	e	enum:__anon13
+CLK_SRC_SYNTH_40M	smac/hal/ssv6006c/ssv6006C_mac.c	925;"	d	file:
+CLK_SRC_SYNTH_80M	smac/dev.h	/^    CLK_SRC_SYNTH_80M,$/;"	e	enum:__anon13
+CLK_USB_PHY30M_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1134;"	d
+CLK_USB_PHY30M_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1132;"	d
+CLK_USB_PHY30M_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1131;"	d
+CLK_USB_PHY30M_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1133;"	d
+CLK_USB_PHY30M_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1135;"	d
+CLK_WIDTH_HI	include/ssv6200_aux.h	3954;"	d
+CLK_WIDTH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3069;"	d
+CLK_WIDTH_I_MSK	include/ssv6200_aux.h	3952;"	d
+CLK_WIDTH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3067;"	d
+CLK_WIDTH_MSK	include/ssv6200_aux.h	3951;"	d
+CLK_WIDTH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3066;"	d
+CLK_WIDTH_SFT	include/ssv6200_aux.h	3953;"	d
+CLK_WIDTH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3068;"	d
+CLK_WIDTH_SZ	include/ssv6200_aux.h	3955;"	d
+CLK_WIDTH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3070;"	d
+CLK_XTAL	smac/hal/ssv6006c/turismo_common.h	225;"	d
+CLR_HI	include/ssv6200_aux.h	6434;"	d
+CLR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5679;"	d
+CLR_I_MSK	include/ssv6200_aux.h	6432;"	d
+CLR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5677;"	d
+CLR_MSK	include/ssv6200_aux.h	6431;"	d
+CLR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5676;"	d
+CLR_SFT	include/ssv6200_aux.h	6433;"	d
+CLR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5678;"	d
+CLR_SZ	include/ssv6200_aux.h	6435;"	d
+CLR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5680;"	d
+CMD52_ABORT_ACTIVE_HI	include/ssv6200_aux.h	3194;"	d
+CMD52_ABORT_ACTIVE_I_MSK	include/ssv6200_aux.h	3192;"	d
+CMD52_ABORT_ACTIVE_MSK	include/ssv6200_aux.h	3191;"	d
+CMD52_ABORT_ACTIVE_SFT	include/ssv6200_aux.h	3193;"	d
+CMD52_ABORT_ACTIVE_SZ	include/ssv6200_aux.h	3195;"	d
+CMD52_ABORT_RESPONSE_HI	include/ssv6200_aux.h	3169;"	d
+CMD52_ABORT_RESPONSE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2639;"	d
+CMD52_ABORT_RESPONSE_I_MSK	include/ssv6200_aux.h	3167;"	d
+CMD52_ABORT_RESPONSE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2637;"	d
+CMD52_ABORT_RESPONSE_MSK	include/ssv6200_aux.h	3166;"	d
+CMD52_ABORT_RESPONSE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2636;"	d
+CMD52_ABORT_RESPONSE_SFT	include/ssv6200_aux.h	3168;"	d
+CMD52_ABORT_RESPONSE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2638;"	d
+CMD52_ABORT_RESPONSE_SZ	include/ssv6200_aux.h	3170;"	d
+CMD52_ABORT_RESPONSE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2640;"	d
+CMD52_RD_ABORT_CNT_HI	include/ssv6200_aux.h	3454;"	d
+CMD52_RD_ABORT_CNT_I_MSK	include/ssv6200_aux.h	3452;"	d
+CMD52_RD_ABORT_CNT_MSK	include/ssv6200_aux.h	3451;"	d
+CMD52_RD_ABORT_CNT_SFT	include/ssv6200_aux.h	3453;"	d
+CMD52_RD_ABORT_CNT_SZ	include/ssv6200_aux.h	3455;"	d
+CMD52_RESET_ACTIVE_HI	include/ssv6200_aux.h	3199;"	d
+CMD52_RESET_ACTIVE_I_MSK	include/ssv6200_aux.h	3197;"	d
+CMD52_RESET_ACTIVE_MSK	include/ssv6200_aux.h	3196;"	d
+CMD52_RESET_ACTIVE_SFT	include/ssv6200_aux.h	3198;"	d
+CMD52_RESET_ACTIVE_SZ	include/ssv6200_aux.h	3200;"	d
+CMD52_WR_ABORT_CNT_HI	include/ssv6200_aux.h	3459;"	d
+CMD52_WR_ABORT_CNT_I_MSK	include/ssv6200_aux.h	3457;"	d
+CMD52_WR_ABORT_CNT_MSK	include/ssv6200_aux.h	3456;"	d
+CMD52_WR_ABORT_CNT_SFT	include/ssv6200_aux.h	3458;"	d
+CMD52_WR_ABORT_CNT_SZ	include/ssv6200_aux.h	3460;"	d
+CMD53_ARG_BLOCK_BASIS	hwif/sdio/sdio_def.h	91;"	d
+CMD53_ARG_FIXED_ADDRESS	hwif/sdio/sdio_def.h	92;"	d
+CMD53_ARG_INCR_ADDRESS	hwif/sdio/sdio_def.h	93;"	d
+CMD53_ARG_READ	hwif/sdio/sdio_def.h	89;"	d
+CMD53_ARG_WRITE	hwif/sdio/sdio_def.h	90;"	d
+CMD_ADDR_HI	include/ssv6200_aux.h	5764;"	d
+CMD_ADDR_I_MSK	include/ssv6200_aux.h	5762;"	d
+CMD_ADDR_MSK	include/ssv6200_aux.h	5761;"	d
+CMD_ADDR_SFT	include/ssv6200_aux.h	5763;"	d
+CMD_ADDR_SZ	include/ssv6200_aux.h	5765;"	d
+CMD_LEN_HI	include/ssv6200_aux.h	5759;"	d
+CMD_LEN_I_MSK	include/ssv6200_aux.h	5757;"	d
+CMD_LEN_MSK	include/ssv6200_aux.h	5756;"	d
+CMD_LEN_SFT	include/ssv6200_aux.h	5758;"	d
+CMD_LEN_SPIMAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6029;"	d
+CMD_LEN_SPIMAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6027;"	d
+CMD_LEN_SPIMAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6026;"	d
+CMD_LEN_SPIMAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6028;"	d
+CMD_LEN_SPIMAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6030;"	d
+CMD_LEN_SZ	include/ssv6200_aux.h	5760;"	d
+CMD_LOG_PART1_HI	include/ssv6200_aux.h	3614;"	d
+CMD_LOG_PART1_I_MSK	include/ssv6200_aux.h	3612;"	d
+CMD_LOG_PART1_MSK	include/ssv6200_aux.h	3611;"	d
+CMD_LOG_PART1_SFT	include/ssv6200_aux.h	3613;"	d
+CMD_LOG_PART1_SZ	include/ssv6200_aux.h	3615;"	d
+CMD_LOG_PART2_HI	include/ssv6200_aux.h	3619;"	d
+CMD_LOG_PART2_I_MSK	include/ssv6200_aux.h	3617;"	d
+CMD_LOG_PART2_MSK	include/ssv6200_aux.h	3616;"	d
+CMD_LOG_PART2_SFT	include/ssv6200_aux.h	3618;"	d
+CMD_LOG_PART2_SZ	include/ssv6200_aux.h	3620;"	d
+COEXIST_EN_HI	include/ssv6200_aux.h	9219;"	d
+COEXIST_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9009;"	d
+COEXIST_EN_I_MSK	include/ssv6200_aux.h	9217;"	d
+COEXIST_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9007;"	d
+COEXIST_EN_MSK	include/ssv6200_aux.h	9216;"	d
+COEXIST_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9006;"	d
+COEXIST_EN_SFT	include/ssv6200_aux.h	9218;"	d
+COEXIST_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9008;"	d
+COEXIST_EN_SZ	include/ssv6200_aux.h	9220;"	d
+COEXIST_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9010;"	d
+COMMAND_COUNTER_HI	include/ssv6200_aux.h	3609;"	d
+COMMAND_COUNTER_I_MSK	include/ssv6200_aux.h	3607;"	d
+COMMAND_COUNTER_MSK	include/ssv6200_aux.h	3606;"	d
+COMMAND_COUNTER_SFT	include/ssv6200_aux.h	3608;"	d
+COMMAND_COUNTER_SZ	include/ssv6200_aux.h	3610;"	d
+COMMON_CIS_PONTER_HI	include/ssv6200_aux.h	3724;"	d
+COMMON_CIS_PONTER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2849;"	d
+COMMON_CIS_PONTER_I_MSK	include/ssv6200_aux.h	3722;"	d
+COMMON_CIS_PONTER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2847;"	d
+COMMON_CIS_PONTER_MSK	include/ssv6200_aux.h	3721;"	d
+COMMON_CIS_PONTER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2846;"	d
+COMMON_CIS_PONTER_SFT	include/ssv6200_aux.h	3723;"	d
+COMMON_CIS_PONTER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2848;"	d
+COMMON_CIS_PONTER_SZ	include/ssv6200_aux.h	3725;"	d
+COMMON_CIS_PONTER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2850;"	d
+COMMON_FOR_SMAC	smac/hal/ssv6006c/ssv6006_priv.h	19;"	d
+COMPACT_MACSTR	smac/p2p.c	41;"	d	file:
+COMPILERDATE	include/ssv_version.h	8;"	d
+COMPILERHOST	include/ssv_version.h	7;"	d
+COMPILEROS	include/ssv_version.h	9;"	d
+COMPILEROSARCH	include/ssv_version.h	10;"	d
+CONDI_NUM_HI	include/ssv6200_aux.h	3934;"	d
+CONDI_NUM_I_MSK	include/ssv6200_aux.h	3932;"	d
+CONDI_NUM_MSK	include/ssv6200_aux.h	3931;"	d
+CONDI_NUM_SFT	include/ssv6200_aux.h	3933;"	d
+CONDI_NUM_SZ	include/ssv6200_aux.h	3935;"	d
+CONFIG_IRQ_DEBUG_COUNT	include/ssv_mod_conf.h	76;"	d
+CONFIG_MAC80211_DEBUGFS	config_common.mak	/^CONFIG_MAC80211_DEBUGFS=y$/;"	m
+CONFIG_MAC80211_LEDS	config_common.mak	/^CONFIG_MAC80211_LEDS=y$/;"	m
+CONFIG_MAC80211_MESH	config_common.mak	/^CONFIG_MAC80211_MESH=y$/;"	m
+CONFIG_MAC80211_RC_MINSTREL	config_common.mak	/^CONFIG_MAC80211_RC_MINSTREL=y$/;"	m
+CONFIG_MAC80211_RC_MINSTREL_HT	config_common.mak	/^CONFIG_MAC80211_RC_MINSTREL_HT=y$/;"	m
+CONFIG_PM	config_common.mak	/^CONFIG_PM=y$/;"	m
+CONFIG_SSV6200_CLI_ENABLE	include/ssv_mod_conf.h	19;"	d
+CONFIG_SSV6200_HAS_RX_WORKQUEUE	include/ssv_mod_conf.h	28;"	d
+CONFIG_SSV6X5X	config_common.mak	/^CONFIG_SSV6X5X=m$/;"	m
+CONFIG_SSV6XXX_DEBUGFS	include/ssv_mod_conf.h	79;"	d
+CONFIG_SSV_CABRIO_E	include/ssv_mod_conf.h	16;"	d
+CONFIG_SSV_CCI_IMPROVEMENT	include/ssv_mod_conf.h	70;"	d
+CONFIG_SSV_TX_LOWTHRESHOLD	include/ssv_mod_conf.h	22;"	d
+CONFIG_SSV_WAPI	include/ssv_mod_conf.h	61;"	d
+CONTINUE_R_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4069;"	d
+CONTINUE_R_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4067;"	d
+CONTINUE_R_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4066;"	d
+CONTINUE_R_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4068;"	d
+CONTINUE_R_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4070;"	d
+CORRECT_RATE_REP_LEN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5509;"	d
+CORRECT_RATE_REP_LEN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5507;"	d
+CORRECT_RATE_REP_LEN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5506;"	d
+CORRECT_RATE_REP_LEN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5508;"	d
+CORRECT_RATE_REP_LEN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5510;"	d
+CO_PROC_CLK_EN_HI	include/ssv6200_aux.h	8989;"	d
+CO_PROC_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8744;"	d
+CO_PROC_CLK_EN_I_MSK	include/ssv6200_aux.h	8987;"	d
+CO_PROC_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8742;"	d
+CO_PROC_CLK_EN_MSK	include/ssv6200_aux.h	8986;"	d
+CO_PROC_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8741;"	d
+CO_PROC_CLK_EN_SFT	include/ssv6200_aux.h	8988;"	d
+CO_PROC_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8743;"	d
+CO_PROC_CLK_EN_SZ	include/ssv6200_aux.h	8990;"	d
+CO_PROC_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8745;"	d
+CO_PROC_CSR_CLK_EN_HI	include/ssv6200_aux.h	9094;"	d
+CO_PROC_CSR_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8849;"	d
+CO_PROC_CSR_CLK_EN_I_MSK	include/ssv6200_aux.h	9092;"	d
+CO_PROC_CSR_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8847;"	d
+CO_PROC_CSR_CLK_EN_MSK	include/ssv6200_aux.h	9091;"	d
+CO_PROC_CSR_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8846;"	d
+CO_PROC_CSR_CLK_EN_SFT	include/ssv6200_aux.h	9093;"	d
+CO_PROC_CSR_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8848;"	d
+CO_PROC_CSR_CLK_EN_SZ	include/ssv6200_aux.h	9095;"	d
+CO_PROC_CSR_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8850;"	d
+CO_PROC_CSR_RST_HI	include/ssv6200_aux.h	8919;"	d
+CO_PROC_CSR_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8674;"	d
+CO_PROC_CSR_RST_I_MSK	include/ssv6200_aux.h	8917;"	d
+CO_PROC_CSR_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8672;"	d
+CO_PROC_CSR_RST_MSK	include/ssv6200_aux.h	8916;"	d
+CO_PROC_CSR_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8671;"	d
+CO_PROC_CSR_RST_SFT	include/ssv6200_aux.h	8918;"	d
+CO_PROC_CSR_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8673;"	d
+CO_PROC_CSR_RST_SZ	include/ssv6200_aux.h	8920;"	d
+CO_PROC_CSR_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8675;"	d
+CO_PROC_ENG_CLK_EN_HI	include/ssv6200_aux.h	9049;"	d
+CO_PROC_ENG_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8804;"	d
+CO_PROC_ENG_CLK_EN_I_MSK	include/ssv6200_aux.h	9047;"	d
+CO_PROC_ENG_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8802;"	d
+CO_PROC_ENG_CLK_EN_MSK	include/ssv6200_aux.h	9046;"	d
+CO_PROC_ENG_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8801;"	d
+CO_PROC_ENG_CLK_EN_SFT	include/ssv6200_aux.h	9048;"	d
+CO_PROC_ENG_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8803;"	d
+CO_PROC_ENG_CLK_EN_SZ	include/ssv6200_aux.h	9050;"	d
+CO_PROC_ENG_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8805;"	d
+CO_PROC_ENG_RST_HI	include/ssv6200_aux.h	8864;"	d
+CO_PROC_ENG_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8619;"	d
+CO_PROC_ENG_RST_I_MSK	include/ssv6200_aux.h	8862;"	d
+CO_PROC_ENG_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8617;"	d
+CO_PROC_ENG_RST_MSK	include/ssv6200_aux.h	8861;"	d
+CO_PROC_ENG_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8616;"	d
+CO_PROC_ENG_RST_SFT	include/ssv6200_aux.h	8863;"	d
+CO_PROC_ENG_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8618;"	d
+CO_PROC_ENG_RST_SZ	include/ssv6200_aux.h	8865;"	d
+CO_PROC_ENG_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8620;"	d
+CO_PROC_SW_RST_HI	include/ssv6200_aux.h	8804;"	d
+CO_PROC_SW_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8554;"	d
+CO_PROC_SW_RST_I_MSK	include/ssv6200_aux.h	8802;"	d
+CO_PROC_SW_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8552;"	d
+CO_PROC_SW_RST_MSK	include/ssv6200_aux.h	8801;"	d
+CO_PROC_SW_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8551;"	d
+CO_PROC_SW_RST_SFT	include/ssv6200_aux.h	8803;"	d
+CO_PROC_SW_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8553;"	d
+CO_PROC_SW_RST_SZ	include/ssv6200_aux.h	8805;"	d
+CO_PROC_SW_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8555;"	d
+CO_REG_BANK_SIZE	include/ssv6200_reg.h	92;"	d
+CO_REG_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	109;"	d
+CO_REG_BASE	include/ssv6200_reg.h	43;"	d
+CO_REG_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	48;"	d
+CPHA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5984;"	d
+CPHA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5982;"	d
+CPHA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5981;"	d
+CPHA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5983;"	d
+CPHA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5985;"	d
+CPOL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5979;"	d
+CPOL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5977;"	d
+CPOL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5976;"	d
+CPOL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5978;"	d
+CPOL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5980;"	d
+CPU_ID_TB0_HI	include/ssv6200_aux.h	11399;"	d
+CPU_ID_TB0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32939;"	d
+CPU_ID_TB0_I_MSK	include/ssv6200_aux.h	11397;"	d
+CPU_ID_TB0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32937;"	d
+CPU_ID_TB0_MSK	include/ssv6200_aux.h	11396;"	d
+CPU_ID_TB0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32936;"	d
+CPU_ID_TB0_SFT	include/ssv6200_aux.h	11398;"	d
+CPU_ID_TB0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32938;"	d
+CPU_ID_TB0_SZ	include/ssv6200_aux.h	11400;"	d
+CPU_ID_TB0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32940;"	d
+CPU_ID_TB1_HI	include/ssv6200_aux.h	11404;"	d
+CPU_ID_TB1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32944;"	d
+CPU_ID_TB1_I_MSK	include/ssv6200_aux.h	11402;"	d
+CPU_ID_TB1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32942;"	d
+CPU_ID_TB1_MSK	include/ssv6200_aux.h	11401;"	d
+CPU_ID_TB1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32941;"	d
+CPU_ID_TB1_SFT	include/ssv6200_aux.h	11403;"	d
+CPU_ID_TB1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32943;"	d
+CPU_ID_TB1_SZ	include/ssv6200_aux.h	11405;"	d
+CPU_ID_TB1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32945;"	d
+CPU_ID_TB2_HI	include/ssv6200_aux.h	12424;"	d
+CPU_ID_TB2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33954;"	d
+CPU_ID_TB2_I_MSK	include/ssv6200_aux.h	12422;"	d
+CPU_ID_TB2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33952;"	d
+CPU_ID_TB2_MSK	include/ssv6200_aux.h	12421;"	d
+CPU_ID_TB2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33951;"	d
+CPU_ID_TB2_SFT	include/ssv6200_aux.h	12423;"	d
+CPU_ID_TB2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33953;"	d
+CPU_ID_TB2_SZ	include/ssv6200_aux.h	12425;"	d
+CPU_ID_TB2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33955;"	d
+CPU_ID_TB3_HI	include/ssv6200_aux.h	12429;"	d
+CPU_ID_TB3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33959;"	d
+CPU_ID_TB3_I_MSK	include/ssv6200_aux.h	12427;"	d
+CPU_ID_TB3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33957;"	d
+CPU_ID_TB3_MSK	include/ssv6200_aux.h	12426;"	d
+CPU_ID_TB3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33956;"	d
+CPU_ID_TB3_SFT	include/ssv6200_aux.h	12428;"	d
+CPU_ID_TB3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33958;"	d
+CPU_ID_TB3_SZ	include/ssv6200_aux.h	12430;"	d
+CPU_ID_TB3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33960;"	d
+CPU_INT_ALT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32924;"	d
+CPU_INT_ALT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32922;"	d
+CPU_INT_ALT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32921;"	d
+CPU_INT_ALT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32923;"	d
+CPU_INT_ALT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32925;"	d
+CPU_INT_HI	include/ssv6200_aux.h	11394;"	d
+CPU_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32934;"	d
+CPU_INT_I_MSK	include/ssv6200_aux.h	11392;"	d
+CPU_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32932;"	d
+CPU_INT_MSK	include/ssv6200_aux.h	11391;"	d
+CPU_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32931;"	d
+CPU_INT_SFT	include/ssv6200_aux.h	11393;"	d
+CPU_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32933;"	d
+CPU_INT_SZ	include/ssv6200_aux.h	11395;"	d
+CPU_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32935;"	d
+CPU_POR0_HI	include/ssv6200_aux.h	17764;"	d
+CPU_POR0_I_MSK	include/ssv6200_aux.h	17762;"	d
+CPU_POR0_MSK	include/ssv6200_aux.h	17761;"	d
+CPU_POR0_SFT	include/ssv6200_aux.h	17763;"	d
+CPU_POR0_SZ	include/ssv6200_aux.h	17765;"	d
+CPU_POR1_HI	include/ssv6200_aux.h	17769;"	d
+CPU_POR1_I_MSK	include/ssv6200_aux.h	17767;"	d
+CPU_POR1_MSK	include/ssv6200_aux.h	17766;"	d
+CPU_POR1_SFT	include/ssv6200_aux.h	17768;"	d
+CPU_POR1_SZ	include/ssv6200_aux.h	17770;"	d
+CPU_POR2_HI	include/ssv6200_aux.h	17774;"	d
+CPU_POR2_I_MSK	include/ssv6200_aux.h	17772;"	d
+CPU_POR2_MSK	include/ssv6200_aux.h	17771;"	d
+CPU_POR2_SFT	include/ssv6200_aux.h	17773;"	d
+CPU_POR2_SZ	include/ssv6200_aux.h	17775;"	d
+CPU_POR3_HI	include/ssv6200_aux.h	17779;"	d
+CPU_POR3_I_MSK	include/ssv6200_aux.h	17777;"	d
+CPU_POR3_MSK	include/ssv6200_aux.h	17776;"	d
+CPU_POR3_SFT	include/ssv6200_aux.h	17778;"	d
+CPU_POR3_SZ	include/ssv6200_aux.h	17780;"	d
+CPU_POR4_HI	include/ssv6200_aux.h	17784;"	d
+CPU_POR4_I_MSK	include/ssv6200_aux.h	17782;"	d
+CPU_POR4_MSK	include/ssv6200_aux.h	17781;"	d
+CPU_POR4_SFT	include/ssv6200_aux.h	17783;"	d
+CPU_POR4_SZ	include/ssv6200_aux.h	17785;"	d
+CPU_POR5_HI	include/ssv6200_aux.h	17789;"	d
+CPU_POR5_I_MSK	include/ssv6200_aux.h	17787;"	d
+CPU_POR5_MSK	include/ssv6200_aux.h	17786;"	d
+CPU_POR5_SFT	include/ssv6200_aux.h	17788;"	d
+CPU_POR5_SZ	include/ssv6200_aux.h	17790;"	d
+CPU_POR6_HI	include/ssv6200_aux.h	17794;"	d
+CPU_POR6_I_MSK	include/ssv6200_aux.h	17792;"	d
+CPU_POR6_MSK	include/ssv6200_aux.h	17791;"	d
+CPU_POR6_SFT	include/ssv6200_aux.h	17793;"	d
+CPU_POR6_SZ	include/ssv6200_aux.h	17795;"	d
+CPU_POR7_HI	include/ssv6200_aux.h	17799;"	d
+CPU_POR7_I_MSK	include/ssv6200_aux.h	17797;"	d
+CPU_POR7_MSK	include/ssv6200_aux.h	17796;"	d
+CPU_POR7_SFT	include/ssv6200_aux.h	17798;"	d
+CPU_POR7_SZ	include/ssv6200_aux.h	17800;"	d
+CPU_POR8_HI	include/ssv6200_aux.h	17804;"	d
+CPU_POR8_I_MSK	include/ssv6200_aux.h	17802;"	d
+CPU_POR8_MSK	include/ssv6200_aux.h	17801;"	d
+CPU_POR8_SFT	include/ssv6200_aux.h	17803;"	d
+CPU_POR8_SZ	include/ssv6200_aux.h	17805;"	d
+CPU_POR9_HI	include/ssv6200_aux.h	17809;"	d
+CPU_POR9_I_MSK	include/ssv6200_aux.h	17807;"	d
+CPU_POR9_MSK	include/ssv6200_aux.h	17806;"	d
+CPU_POR9_SFT	include/ssv6200_aux.h	17808;"	d
+CPU_POR9_SZ	include/ssv6200_aux.h	17810;"	d
+CPU_PORA_HI	include/ssv6200_aux.h	17814;"	d
+CPU_PORA_I_MSK	include/ssv6200_aux.h	17812;"	d
+CPU_PORA_MSK	include/ssv6200_aux.h	17811;"	d
+CPU_PORA_SFT	include/ssv6200_aux.h	17813;"	d
+CPU_PORA_SZ	include/ssv6200_aux.h	17815;"	d
+CPU_PORB_HI	include/ssv6200_aux.h	17819;"	d
+CPU_PORB_I_MSK	include/ssv6200_aux.h	17817;"	d
+CPU_PORB_MSK	include/ssv6200_aux.h	17816;"	d
+CPU_PORB_SFT	include/ssv6200_aux.h	17818;"	d
+CPU_PORB_SZ	include/ssv6200_aux.h	17820;"	d
+CPU_PORC_HI	include/ssv6200_aux.h	17824;"	d
+CPU_PORC_I_MSK	include/ssv6200_aux.h	17822;"	d
+CPU_PORC_MSK	include/ssv6200_aux.h	17821;"	d
+CPU_PORC_SFT	include/ssv6200_aux.h	17823;"	d
+CPU_PORC_SZ	include/ssv6200_aux.h	17825;"	d
+CPU_PORD_HI	include/ssv6200_aux.h	17829;"	d
+CPU_PORD_I_MSK	include/ssv6200_aux.h	17827;"	d
+CPU_PORD_MSK	include/ssv6200_aux.h	17826;"	d
+CPU_PORD_SFT	include/ssv6200_aux.h	17828;"	d
+CPU_PORD_SZ	include/ssv6200_aux.h	17830;"	d
+CPU_PORE_HI	include/ssv6200_aux.h	17834;"	d
+CPU_PORE_I_MSK	include/ssv6200_aux.h	17832;"	d
+CPU_PORE_MSK	include/ssv6200_aux.h	17831;"	d
+CPU_PORE_SFT	include/ssv6200_aux.h	17833;"	d
+CPU_PORE_SZ	include/ssv6200_aux.h	17835;"	d
+CPU_PORF_HI	include/ssv6200_aux.h	17839;"	d
+CPU_PORF_I_MSK	include/ssv6200_aux.h	17837;"	d
+CPU_PORF_MSK	include/ssv6200_aux.h	17836;"	d
+CPU_PORF_SFT	include/ssv6200_aux.h	17838;"	d
+CPU_PORF_SZ	include/ssv6200_aux.h	17840;"	d
+CPU_QUE_POP_ALT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32919;"	d
+CPU_QUE_POP_ALT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32917;"	d
+CPU_QUE_POP_ALT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32916;"	d
+CPU_QUE_POP_ALT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32918;"	d
+CPU_QUE_POP_ALT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32920;"	d
+CPU_QUE_POP_HI	include/ssv6200_aux.h	11389;"	d
+CPU_QUE_POP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32929;"	d
+CPU_QUE_POP_I_MSK	include/ssv6200_aux.h	11387;"	d
+CPU_QUE_POP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32927;"	d
+CPU_QUE_POP_MSK	include/ssv6200_aux.h	11386;"	d
+CPU_QUE_POP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32926;"	d
+CPU_QUE_POP_SFT	include/ssv6200_aux.h	11388;"	d
+CPU_QUE_POP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32928;"	d
+CPU_QUE_POP_SZ	include/ssv6200_aux.h	11390;"	d
+CPU_QUE_POP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32930;"	d
+CRC_CNT_HI	include/ssv6200_aux.h	14594;"	d
+CRC_CNT_I_MSK	include/ssv6200_aux.h	14592;"	d
+CRC_CNT_MSK	include/ssv6200_aux.h	14591;"	d
+CRC_CNT_SFT	include/ssv6200_aux.h	14593;"	d
+CRC_CNT_SZ	include/ssv6200_aux.h	14595;"	d
+CRC_CORRECT_HI	include/ssv6200_aux.h	14644;"	d
+CRC_CORRECT_I_MSK	include/ssv6200_aux.h	14642;"	d
+CRC_CORRECT_MSK	include/ssv6200_aux.h	14641;"	d
+CRC_CORRECT_SFT	include/ssv6200_aux.h	14643;"	d
+CRC_CORRECT_SZ	include/ssv6200_aux.h	14645;"	d
+CRYSTAL_OUT_REQ_SEL_HI	include/ssv6200_aux.h	2944;"	d
+CRYSTAL_OUT_REQ_SEL_I_MSK	include/ssv6200_aux.h	2942;"	d
+CRYSTAL_OUT_REQ_SEL_MSK	include/ssv6200_aux.h	2941;"	d
+CRYSTAL_OUT_REQ_SEL_SFT	include/ssv6200_aux.h	2943;"	d
+CRYSTAL_OUT_REQ_SEL_SZ	include/ssv6200_aux.h	2945;"	d
+CSASUPPORT_HI	include/ssv6200_aux.h	3744;"	d
+CSASUPPORT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2879;"	d
+CSASUPPORT_I_MSK	include/ssv6200_aux.h	3742;"	d
+CSASUPPORT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2877;"	d
+CSASUPPORT_MSK	include/ssv6200_aux.h	3741;"	d
+CSASUPPORT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2876;"	d
+CSASUPPORT_SFT	include/ssv6200_aux.h	3743;"	d
+CSASUPPORT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2878;"	d
+CSASUPPORT_SZ	include/ssv6200_aux.h	3745;"	d
+CSASUPPORT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2880;"	d
+CSN_DLY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4024;"	d
+CSN_DLY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4022;"	d
+CSN_DLY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4021;"	d
+CSN_DLY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4023;"	d
+CSN_DLY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4025;"	d
+CSN_INTER_HI	include/ssv6200_aux.h	3959;"	d
+CSN_INTER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3074;"	d
+CSN_INTER_I_MSK	include/ssv6200_aux.h	3957;"	d
+CSN_INTER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3072;"	d
+CSN_INTER_MSK	include/ssv6200_aux.h	3956;"	d
+CSN_INTER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3071;"	d
+CSN_INTER_SFT	include/ssv6200_aux.h	3958;"	d
+CSN_INTER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3073;"	d
+CSN_INTER_SZ	include/ssv6200_aux.h	3960;"	d
+CSN_INTER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3075;"	d
+CSPOL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5989;"	d
+CSPOL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5987;"	d
+CSPOL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5986;"	d
+CSPOL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5988;"	d
+CSPOL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5990;"	d
+CSR_ALLON_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	83;"	d
+CSR_ALLON_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	22;"	d
+CSR_I2C_MST_BANK_SIZE	include/ssv6200_reg.h	80;"	d
+CSR_I2C_MST_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	99;"	d
+CSR_I2C_MST_BASE	include/ssv6200_reg.h	31;"	d
+CSR_I2C_MST_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	38;"	d
+CSR_I2C_SLV_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	96;"	d
+CSR_I2C_SLV_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	35;"	d
+CSR_PHY_BANK_SIZE	include/ssv6200_reg.h	111;"	d
+CSR_PHY_BASE	include/ssv6200_reg.h	62;"	d
+CSR_PHY_INFO_HI	include/ssv6200_aux.h	7379;"	d
+CSR_PHY_INFO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6534;"	d
+CSR_PHY_INFO_I_MSK	include/ssv6200_aux.h	7377;"	d
+CSR_PHY_INFO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6532;"	d
+CSR_PHY_INFO_MSK	include/ssv6200_aux.h	7376;"	d
+CSR_PHY_INFO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6531;"	d
+CSR_PHY_INFO_SFT	include/ssv6200_aux.h	7378;"	d
+CSR_PHY_INFO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6533;"	d
+CSR_PHY_INFO_SZ	include/ssv6200_aux.h	7380;"	d
+CSR_PHY_INFO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6535;"	d
+CSR_PMU_BANK_SIZE	include/ssv6200_reg.h	87;"	d
+CSR_PMU_BASE	include/ssv6200_reg.h	38;"	d
+CSR_RF_BANK_SIZE	include/ssv6200_reg.h	112;"	d
+CSR_RF_BASE	include/ssv6200_reg.h	63;"	d
+CSR_RTC_BANK_SIZE	include/ssv6200_reg.h	88;"	d
+CSR_RTC_BASE	include/ssv6200_reg.h	39;"	d
+CSR_SPIMAS_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	111;"	d
+CSR_SPIMAS_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	50;"	d
+CSR_TEMP_REG_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	137;"	d
+CSR_TEMP_REG_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	76;"	d
+CSR_TU_PHY_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	133;"	d
+CSR_TU_PHY_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	72;"	d
+CSR_TU_PMU_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	132;"	d
+CSR_TU_PMU_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	71;"	d
+CSR_TU_RF_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	131;"	d
+CSR_TU_RF_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	70;"	d
+CSTATE_HI	include/ssv6200_aux.h	15244;"	d
+CSTATE_I_MSK	include/ssv6200_aux.h	15242;"	d
+CSTATE_MSK	include/ssv6200_aux.h	15241;"	d
+CSTATE_SFT	include/ssv6200_aux.h	15243;"	d
+CSTATE_SZ	include/ssv6200_aux.h	15245;"	d
+CS_ADDER_EN_HI	include/ssv6200_aux.h	6349;"	d
+CS_ADDER_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5594;"	d
+CS_ADDER_EN_I_MSK	include/ssv6200_aux.h	6347;"	d
+CS_ADDER_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5592;"	d
+CS_ADDER_EN_MSK	include/ssv6200_aux.h	6346;"	d
+CS_ADDER_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5591;"	d
+CS_ADDER_EN_SFT	include/ssv6200_aux.h	6348;"	d
+CS_ADDER_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5593;"	d
+CS_ADDER_EN_SZ	include/ssv6200_aux.h	6350;"	d
+CS_ADDER_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5595;"	d
+CS_PKT_ID_HI	include/ssv6200_aux.h	6339;"	d
+CS_PKT_ID_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5584;"	d
+CS_PKT_ID_I_MSK	include/ssv6200_aux.h	6337;"	d
+CS_PKT_ID_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5582;"	d
+CS_PKT_ID_MSK	include/ssv6200_aux.h	6336;"	d
+CS_PKT_ID_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5581;"	d
+CS_PKT_ID_SFT	include/ssv6200_aux.h	6338;"	d
+CS_PKT_ID_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5583;"	d
+CS_PKT_ID_SZ	include/ssv6200_aux.h	6340;"	d
+CS_PKT_ID_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5585;"	d
+CS_START_ADDR_HI	include/ssv6200_aux.h	6334;"	d
+CS_START_ADDR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5579;"	d
+CS_START_ADDR_I_MSK	include/ssv6200_aux.h	6332;"	d
+CS_START_ADDR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5577;"	d
+CS_START_ADDR_MSK	include/ssv6200_aux.h	6331;"	d
+CS_START_ADDR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5576;"	d
+CS_START_ADDR_SFT	include/ssv6200_aux.h	6333;"	d
+CS_START_ADDR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5578;"	d
+CS_START_ADDR_SZ	include/ssv6200_aux.h	6335;"	d
+CS_START_ADDR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5580;"	d
+CTRL_FRAME_INDEX	smac/dev.c	639;"	d	file:
+CTS_HI	include/ssv6200_aux.h	4449;"	d
+CTS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3559;"	d
+CTS_I_MSK	include/ssv6200_aux.h	4447;"	d
+CTS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3557;"	d
+CTS_LEN	smac/dev.h	161;"	d
+CTS_MSK	include/ssv6200_aux.h	4446;"	d
+CTS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3556;"	d
+CTS_SFT	include/ssv6200_aux.h	4448;"	d
+CTS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3558;"	d
+CTS_SZ	include/ssv6200_aux.h	4450;"	d
+CTS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3560;"	d
+CTYPE_RATE_RPT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7139;"	d
+CTYPE_RATE_RPT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7137;"	d
+CTYPE_RATE_RPT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7136;"	d
+CTYPE_RATE_RPT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7138;"	d
+CTYPE_RATE_RPT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7140;"	d
+CXX_EXTERN_BEGIN	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	23;"	d
+CXX_EXTERN_BEGIN	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	28;"	d
+CXX_EXTERN_END	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	24;"	d
+CXX_EXTERN_END	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	29;"	d
+C_EXTERN	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	25;"	d
+C_EXTERN	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	30;"	d
+C_FILES	smartlink/qqlink-lib-mipsel/case/ipcamera/Makefile	/^C_FILES:=\\$/;"	m
+C_FLAGS	smartlink/qqlink-lib-mipsel/case/ipcamera/Makefile	/^C_FLAGS:=-O0 -g3  -m32 -std=c99$/;"	m
+CalculateEnKey	smac/wapi_sms4.c	/^static void CalculateEnKey(u8 *Key, u32 *Key_Store)$/;"	f	file:	signature:(u8 *Key, u32 *Key_Store)
+CipherDataIdx	smac/wapi_sms4.c	/^static const u32 CipherDataIdx[MK_LEN][MK_LEN] =$/;"	v	file:
+CsrBool	smac/wapi_sms4.c	/^}CsrBool;$/;"	t	typeref:enum:__anon7	file:
+D2_DMA_ADR_DST_HI	include/ssv6200_aux.h	5984;"	d
+D2_DMA_ADR_DST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4264;"	d
+D2_DMA_ADR_DST_I_MSK	include/ssv6200_aux.h	5982;"	d
+D2_DMA_ADR_DST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4262;"	d
+D2_DMA_ADR_DST_MSK	include/ssv6200_aux.h	5981;"	d
+D2_DMA_ADR_DST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4261;"	d
+D2_DMA_ADR_DST_SFT	include/ssv6200_aux.h	5983;"	d
+D2_DMA_ADR_DST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4263;"	d
+D2_DMA_ADR_DST_SZ	include/ssv6200_aux.h	5985;"	d
+D2_DMA_ADR_DST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4265;"	d
+D2_DMA_ADR_SRC_HI	include/ssv6200_aux.h	5979;"	d
+D2_DMA_ADR_SRC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4259;"	d
+D2_DMA_ADR_SRC_I_MSK	include/ssv6200_aux.h	5977;"	d
+D2_DMA_ADR_SRC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4257;"	d
+D2_DMA_ADR_SRC_MSK	include/ssv6200_aux.h	5976;"	d
+D2_DMA_ADR_SRC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4256;"	d
+D2_DMA_ADR_SRC_SFT	include/ssv6200_aux.h	5978;"	d
+D2_DMA_ADR_SRC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4258;"	d
+D2_DMA_ADR_SRC_SZ	include/ssv6200_aux.h	5980;"	d
+D2_DMA_ADR_SRC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4260;"	d
+D2_DMA_BADR_EN_HI	include/ssv6200_aux.h	6019;"	d
+D2_DMA_BADR_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4299;"	d
+D2_DMA_BADR_EN_I_MSK	include/ssv6200_aux.h	6017;"	d
+D2_DMA_BADR_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4297;"	d
+D2_DMA_BADR_EN_MSK	include/ssv6200_aux.h	6016;"	d
+D2_DMA_BADR_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4296;"	d
+D2_DMA_BADR_EN_SFT	include/ssv6200_aux.h	6018;"	d
+D2_DMA_BADR_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4298;"	d
+D2_DMA_BADR_EN_SZ	include/ssv6200_aux.h	6020;"	d
+D2_DMA_BADR_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4300;"	d
+D2_DMA_CONST_HI	include/ssv6200_aux.h	6044;"	d
+D2_DMA_CONST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4324;"	d
+D2_DMA_CONST_I_MSK	include/ssv6200_aux.h	6042;"	d
+D2_DMA_CONST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4322;"	d
+D2_DMA_CONST_MSK	include/ssv6200_aux.h	6041;"	d
+D2_DMA_CONST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4321;"	d
+D2_DMA_CONST_SFT	include/ssv6200_aux.h	6043;"	d
+D2_DMA_CONST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4323;"	d
+D2_DMA_CONST_SZ	include/ssv6200_aux.h	6045;"	d
+D2_DMA_CONST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4325;"	d
+D2_DMA_DST_INC_HI	include/ssv6200_aux.h	6004;"	d
+D2_DMA_DST_INC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4284;"	d
+D2_DMA_DST_INC_I_MSK	include/ssv6200_aux.h	6002;"	d
+D2_DMA_DST_INC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4282;"	d
+D2_DMA_DST_INC_MSK	include/ssv6200_aux.h	6001;"	d
+D2_DMA_DST_INC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4281;"	d
+D2_DMA_DST_INC_SFT	include/ssv6200_aux.h	6003;"	d
+D2_DMA_DST_INC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4283;"	d
+D2_DMA_DST_INC_SZ	include/ssv6200_aux.h	6005;"	d
+D2_DMA_DST_INC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4285;"	d
+D2_DMA_DST_SIZE_HI	include/ssv6200_aux.h	5999;"	d
+D2_DMA_DST_SIZE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4279;"	d
+D2_DMA_DST_SIZE_I_MSK	include/ssv6200_aux.h	5997;"	d
+D2_DMA_DST_SIZE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4277;"	d
+D2_DMA_DST_SIZE_MSK	include/ssv6200_aux.h	5996;"	d
+D2_DMA_DST_SIZE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4276;"	d
+D2_DMA_DST_SIZE_SFT	include/ssv6200_aux.h	5998;"	d
+D2_DMA_DST_SIZE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4278;"	d
+D2_DMA_DST_SIZE_SZ	include/ssv6200_aux.h	6000;"	d
+D2_DMA_DST_SIZE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4280;"	d
+D2_DMA_FAST_FILL_HI	include/ssv6200_aux.h	6009;"	d
+D2_DMA_FAST_FILL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4289;"	d
+D2_DMA_FAST_FILL_I_MSK	include/ssv6200_aux.h	6007;"	d
+D2_DMA_FAST_FILL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4287;"	d
+D2_DMA_FAST_FILL_MSK	include/ssv6200_aux.h	6006;"	d
+D2_DMA_FAST_FILL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4286;"	d
+D2_DMA_FAST_FILL_SFT	include/ssv6200_aux.h	6008;"	d
+D2_DMA_FAST_FILL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4288;"	d
+D2_DMA_FAST_FILL_SZ	include/ssv6200_aux.h	6010;"	d
+D2_DMA_FAST_FILL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4290;"	d
+D2_DMA_FINISH_HI	include/ssv6200_aux.h	6039;"	d
+D2_DMA_FINISH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4319;"	d
+D2_DMA_FINISH_I_MSK	include/ssv6200_aux.h	6037;"	d
+D2_DMA_FINISH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4317;"	d
+D2_DMA_FINISH_MSK	include/ssv6200_aux.h	6036;"	d
+D2_DMA_FINISH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4316;"	d
+D2_DMA_FINISH_SFT	include/ssv6200_aux.h	6038;"	d
+D2_DMA_FINISH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4318;"	d
+D2_DMA_FINISH_SZ	include/ssv6200_aux.h	6040;"	d
+D2_DMA_FINISH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4320;"	d
+D2_DMA_INT_MASK_HI	include/ssv6200_aux.h	6029;"	d
+D2_DMA_INT_MASK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4309;"	d
+D2_DMA_INT_MASK_I_MSK	include/ssv6200_aux.h	6027;"	d
+D2_DMA_INT_MASK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4307;"	d
+D2_DMA_INT_MASK_MSK	include/ssv6200_aux.h	6026;"	d
+D2_DMA_INT_MASK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4306;"	d
+D2_DMA_INT_MASK_SFT	include/ssv6200_aux.h	6028;"	d
+D2_DMA_INT_MASK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4308;"	d
+D2_DMA_INT_MASK_SZ	include/ssv6200_aux.h	6030;"	d
+D2_DMA_INT_MASK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4310;"	d
+D2_DMA_LEN_HI	include/ssv6200_aux.h	6024;"	d
+D2_DMA_LEN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4304;"	d
+D2_DMA_LEN_I_MSK	include/ssv6200_aux.h	6022;"	d
+D2_DMA_LEN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4302;"	d
+D2_DMA_LEN_MSK	include/ssv6200_aux.h	6021;"	d
+D2_DMA_LEN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4301;"	d
+D2_DMA_LEN_SFT	include/ssv6200_aux.h	6023;"	d
+D2_DMA_LEN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4303;"	d
+D2_DMA_LEN_SZ	include/ssv6200_aux.h	6025;"	d
+D2_DMA_LEN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4305;"	d
+D2_DMA_REG_BANK_SIZE	include/ssv6200_reg.h	90;"	d
+D2_DMA_REG_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	104;"	d
+D2_DMA_REG_BASE	include/ssv6200_reg.h	41;"	d
+D2_DMA_REG_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	43;"	d
+D2_DMA_SDIO_KICK_HI	include/ssv6200_aux.h	6014;"	d
+D2_DMA_SDIO_KICK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4294;"	d
+D2_DMA_SDIO_KICK_I_MSK	include/ssv6200_aux.h	6012;"	d
+D2_DMA_SDIO_KICK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4292;"	d
+D2_DMA_SDIO_KICK_MSK	include/ssv6200_aux.h	6011;"	d
+D2_DMA_SDIO_KICK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4291;"	d
+D2_DMA_SDIO_KICK_SFT	include/ssv6200_aux.h	6013;"	d
+D2_DMA_SDIO_KICK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4293;"	d
+D2_DMA_SDIO_KICK_SZ	include/ssv6200_aux.h	6015;"	d
+D2_DMA_SDIO_KICK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4295;"	d
+D2_DMA_SRC_INC_HI	include/ssv6200_aux.h	5994;"	d
+D2_DMA_SRC_INC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4274;"	d
+D2_DMA_SRC_INC_I_MSK	include/ssv6200_aux.h	5992;"	d
+D2_DMA_SRC_INC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4272;"	d
+D2_DMA_SRC_INC_MSK	include/ssv6200_aux.h	5991;"	d
+D2_DMA_SRC_INC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4271;"	d
+D2_DMA_SRC_INC_SFT	include/ssv6200_aux.h	5993;"	d
+D2_DMA_SRC_INC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4273;"	d
+D2_DMA_SRC_INC_SZ	include/ssv6200_aux.h	5995;"	d
+D2_DMA_SRC_INC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4275;"	d
+D2_DMA_SRC_SIZE_HI	include/ssv6200_aux.h	5989;"	d
+D2_DMA_SRC_SIZE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4269;"	d
+D2_DMA_SRC_SIZE_I_MSK	include/ssv6200_aux.h	5987;"	d
+D2_DMA_SRC_SIZE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4267;"	d
+D2_DMA_SRC_SIZE_MSK	include/ssv6200_aux.h	5986;"	d
+D2_DMA_SRC_SIZE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4266;"	d
+D2_DMA_SRC_SIZE_SFT	include/ssv6200_aux.h	5988;"	d
+D2_DMA_SRC_SIZE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4268;"	d
+D2_DMA_SRC_SIZE_SZ	include/ssv6200_aux.h	5990;"	d
+D2_DMA_SRC_SIZE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4270;"	d
+D2_DMA_STS_HI	include/ssv6200_aux.h	6034;"	d
+D2_DMA_STS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4314;"	d
+D2_DMA_STS_I_MSK	include/ssv6200_aux.h	6032;"	d
+D2_DMA_STS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4312;"	d
+D2_DMA_STS_MSK	include/ssv6200_aux.h	6031;"	d
+D2_DMA_STS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4311;"	d
+D2_DMA_STS_SFT	include/ssv6200_aux.h	6033;"	d
+D2_DMA_STS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4313;"	d
+D2_DMA_STS_SZ	include/ssv6200_aux.h	6035;"	d
+D2_DMA_STS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4315;"	d
+DATA_FRAMES_HI	smac/hal/ssv6006c/ssv6006C_aux.h	854;"	d
+DATA_FRAMES_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	852;"	d
+DATA_FRAMES_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	851;"	d
+DATA_FRAMES_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	853;"	d
+DATA_FRAMES_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	855;"	d
+DATA_RATE_HI	include/ssv6200_aux.h	6454;"	d
+DATA_RATE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5699;"	d
+DATA_RATE_I_MSK	include/ssv6200_aux.h	6452;"	d
+DATA_RATE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5697;"	d
+DATA_RATE_MSK	include/ssv6200_aux.h	6451;"	d
+DATA_RATE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5696;"	d
+DATA_RATE_SFT	include/ssv6200_aux.h	6453;"	d
+DATA_RATE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5698;"	d
+DATA_RATE_SZ	include/ssv6200_aux.h	6455;"	d
+DATA_RATE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5700;"	d
+DATA_RDY_HI	include/ssv6200_aux.h	4389;"	d
+DATA_RDY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3499;"	d
+DATA_RDY_IE_HI	include/ssv6200_aux.h	4264;"	d
+DATA_RDY_IE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3369;"	d
+DATA_RDY_IE_I_MSK	include/ssv6200_aux.h	4262;"	d
+DATA_RDY_IE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3367;"	d
+DATA_RDY_IE_MSK	include/ssv6200_aux.h	4261;"	d
+DATA_RDY_IE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3366;"	d
+DATA_RDY_IE_SFT	include/ssv6200_aux.h	4263;"	d
+DATA_RDY_IE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3368;"	d
+DATA_RDY_IE_SZ	include/ssv6200_aux.h	4265;"	d
+DATA_RDY_IE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3370;"	d
+DATA_RDY_I_MSK	include/ssv6200_aux.h	4387;"	d
+DATA_RDY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3497;"	d
+DATA_RDY_MSK	include/ssv6200_aux.h	4386;"	d
+DATA_RDY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3496;"	d
+DATA_RDY_SFT	include/ssv6200_aux.h	4388;"	d
+DATA_RDY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3498;"	d
+DATA_RDY_SZ	include/ssv6200_aux.h	4390;"	d
+DATA_RDY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3500;"	d
+DATA_SPI_RESET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1689;"	d
+DATA_SPI_RESET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1687;"	d
+DATA_SPI_RESET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1686;"	d
+DATA_SPI_RESET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1688;"	d
+DATA_SPI_RESET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1690;"	d
+DATA_SPI_WAKEUP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1659;"	d
+DATA_SPI_WAKEUP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1657;"	d
+DATA_SPI_WAKEUP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1656;"	d
+DATA_SPI_WAKEUP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1658;"	d
+DATA_SPI_WAKEUP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1660;"	d
+DATA_UART_W2B_EN_HI	include/ssv6200_aux.h	444;"	d
+DATA_UART_W2B_EN_I_MSK	include/ssv6200_aux.h	442;"	d
+DATA_UART_W2B_EN_MSK	include/ssv6200_aux.h	441;"	d
+DATA_UART_W2B_EN_SFT	include/ssv6200_aux.h	443;"	d
+DATA_UART_W2B_EN_SZ	include/ssv6200_aux.h	445;"	d
+DAT_BRDC_DIV_HI	include/ssv6200_aux.h	4704;"	d
+DAT_BRDC_DIV_I_MSK	include/ssv6200_aux.h	4702;"	d
+DAT_BRDC_DIV_MSK	include/ssv6200_aux.h	4701;"	d
+DAT_BRDC_DIV_SFT	include/ssv6200_aux.h	4703;"	d
+DAT_BRDC_DIV_SZ	include/ssv6200_aux.h	4705;"	d
+DAT_BREAK_INT_HI	include/ssv6200_aux.h	4644;"	d
+DAT_BREAK_INT_I_MSK	include/ssv6200_aux.h	4642;"	d
+DAT_BREAK_INT_MSK	include/ssv6200_aux.h	4641;"	d
+DAT_BREAK_INT_SFT	include/ssv6200_aux.h	4643;"	d
+DAT_BREAK_INT_SZ	include/ssv6200_aux.h	4645;"	d
+DAT_CD_HI	include/ssv6200_aux.h	4699;"	d
+DAT_CD_I_MSK	include/ssv6200_aux.h	4697;"	d
+DAT_CD_MSK	include/ssv6200_aux.h	4696;"	d
+DAT_CD_SFT	include/ssv6200_aux.h	4698;"	d
+DAT_CD_SZ	include/ssv6200_aux.h	4700;"	d
+DAT_CTS_HI	include/ssv6200_aux.h	4684;"	d
+DAT_CTS_I_MSK	include/ssv6200_aux.h	4682;"	d
+DAT_CTS_MSK	include/ssv6200_aux.h	4681;"	d
+DAT_CTS_SFT	include/ssv6200_aux.h	4683;"	d
+DAT_CTS_SZ	include/ssv6200_aux.h	4685;"	d
+DAT_DATA_RDY_HI	include/ssv6200_aux.h	4624;"	d
+DAT_DATA_RDY_IE_HI	include/ssv6200_aux.h	4499;"	d
+DAT_DATA_RDY_IE_I_MSK	include/ssv6200_aux.h	4497;"	d
+DAT_DATA_RDY_IE_MSK	include/ssv6200_aux.h	4496;"	d
+DAT_DATA_RDY_IE_SFT	include/ssv6200_aux.h	4498;"	d
+DAT_DATA_RDY_IE_SZ	include/ssv6200_aux.h	4500;"	d
+DAT_DATA_RDY_I_MSK	include/ssv6200_aux.h	4622;"	d
+DAT_DATA_RDY_MSK	include/ssv6200_aux.h	4621;"	d
+DAT_DATA_RDY_SFT	include/ssv6200_aux.h	4623;"	d
+DAT_DATA_RDY_SZ	include/ssv6200_aux.h	4625;"	d
+DAT_DELTA_CD_HI	include/ssv6200_aux.h	4679;"	d
+DAT_DELTA_CD_I_MSK	include/ssv6200_aux.h	4677;"	d
+DAT_DELTA_CD_MSK	include/ssv6200_aux.h	4676;"	d
+DAT_DELTA_CD_SFT	include/ssv6200_aux.h	4678;"	d
+DAT_DELTA_CD_SZ	include/ssv6200_aux.h	4680;"	d
+DAT_DELTA_CTS_HI	include/ssv6200_aux.h	4664;"	d
+DAT_DELTA_CTS_I_MSK	include/ssv6200_aux.h	4662;"	d
+DAT_DELTA_CTS_MSK	include/ssv6200_aux.h	4661;"	d
+DAT_DELTA_CTS_SFT	include/ssv6200_aux.h	4663;"	d
+DAT_DELTA_CTS_SZ	include/ssv6200_aux.h	4665;"	d
+DAT_DELTA_DSR_HI	include/ssv6200_aux.h	4669;"	d
+DAT_DELTA_DSR_I_MSK	include/ssv6200_aux.h	4667;"	d
+DAT_DELTA_DSR_MSK	include/ssv6200_aux.h	4666;"	d
+DAT_DELTA_DSR_SFT	include/ssv6200_aux.h	4668;"	d
+DAT_DELTA_DSR_SZ	include/ssv6200_aux.h	4670;"	d
+DAT_DLAB_HI	include/ssv6200_aux.h	4594;"	d
+DAT_DLAB_I_MSK	include/ssv6200_aux.h	4592;"	d
+DAT_DLAB_MSK	include/ssv6200_aux.h	4591;"	d
+DAT_DLAB_SFT	include/ssv6200_aux.h	4593;"	d
+DAT_DLAB_SZ	include/ssv6200_aux.h	4595;"	d
+DAT_DMA_MODE_HI	include/ssv6200_aux.h	4544;"	d
+DAT_DMA_MODE_I_MSK	include/ssv6200_aux.h	4542;"	d
+DAT_DMA_MODE_MSK	include/ssv6200_aux.h	4541;"	d
+DAT_DMA_MODE_SFT	include/ssv6200_aux.h	4543;"	d
+DAT_DMA_MODE_SZ	include/ssv6200_aux.h	4545;"	d
+DAT_DMA_RXEND_IE_HI	include/ssv6200_aux.h	4519;"	d
+DAT_DMA_RXEND_IE_I_MSK	include/ssv6200_aux.h	4517;"	d
+DAT_DMA_RXEND_IE_MSK	include/ssv6200_aux.h	4516;"	d
+DAT_DMA_RXEND_IE_SFT	include/ssv6200_aux.h	4518;"	d
+DAT_DMA_RXEND_IE_SZ	include/ssv6200_aux.h	4520;"	d
+DAT_DMA_TXEND_IE_HI	include/ssv6200_aux.h	4524;"	d
+DAT_DMA_TXEND_IE_I_MSK	include/ssv6200_aux.h	4522;"	d
+DAT_DMA_TXEND_IE_MSK	include/ssv6200_aux.h	4521;"	d
+DAT_DMA_TXEND_IE_SFT	include/ssv6200_aux.h	4523;"	d
+DAT_DMA_TXEND_IE_SZ	include/ssv6200_aux.h	4525;"	d
+DAT_DSR_HI	include/ssv6200_aux.h	4689;"	d
+DAT_DSR_I_MSK	include/ssv6200_aux.h	4687;"	d
+DAT_DSR_MSK	include/ssv6200_aux.h	4686;"	d
+DAT_DSR_SFT	include/ssv6200_aux.h	4688;"	d
+DAT_DSR_SZ	include/ssv6200_aux.h	4690;"	d
+DAT_DTR_HI	include/ssv6200_aux.h	4599;"	d
+DAT_DTR_I_MSK	include/ssv6200_aux.h	4597;"	d
+DAT_DTR_MSK	include/ssv6200_aux.h	4596;"	d
+DAT_DTR_SFT	include/ssv6200_aux.h	4598;"	d
+DAT_DTR_SZ	include/ssv6200_aux.h	4600;"	d
+DAT_EN_AUTO_CTS_HI	include/ssv6200_aux.h	4554;"	d
+DAT_EN_AUTO_CTS_I_MSK	include/ssv6200_aux.h	4552;"	d
+DAT_EN_AUTO_CTS_MSK	include/ssv6200_aux.h	4551;"	d
+DAT_EN_AUTO_CTS_SFT	include/ssv6200_aux.h	4553;"	d
+DAT_EN_AUTO_CTS_SZ	include/ssv6200_aux.h	4555;"	d
+DAT_EN_AUTO_RTS_HI	include/ssv6200_aux.h	4549;"	d
+DAT_EN_AUTO_RTS_I_MSK	include/ssv6200_aux.h	4547;"	d
+DAT_EN_AUTO_RTS_MSK	include/ssv6200_aux.h	4546;"	d
+DAT_EN_AUTO_RTS_SFT	include/ssv6200_aux.h	4548;"	d
+DAT_EN_AUTO_RTS_SZ	include/ssv6200_aux.h	4550;"	d
+DAT_EVEN_PARITY_HI	include/ssv6200_aux.h	4579;"	d
+DAT_EVEN_PARITY_I_MSK	include/ssv6200_aux.h	4577;"	d
+DAT_EVEN_PARITY_MSK	include/ssv6200_aux.h	4576;"	d
+DAT_EVEN_PARITY_SFT	include/ssv6200_aux.h	4578;"	d
+DAT_EVEN_PARITY_SZ	include/ssv6200_aux.h	4580;"	d
+DAT_FIFODATA_ERR_HI	include/ssv6200_aux.h	4659;"	d
+DAT_FIFODATA_ERR_I_MSK	include/ssv6200_aux.h	4657;"	d
+DAT_FIFODATA_ERR_MSK	include/ssv6200_aux.h	4656;"	d
+DAT_FIFODATA_ERR_SFT	include/ssv6200_aux.h	4658;"	d
+DAT_FIFODATA_ERR_SZ	include/ssv6200_aux.h	4660;"	d
+DAT_FIFOS_ENABLED_HI	include/ssv6200_aux.h	4724;"	d
+DAT_FIFOS_ENABLED_I_MSK	include/ssv6200_aux.h	4722;"	d
+DAT_FIFOS_ENABLED_MSK	include/ssv6200_aux.h	4721;"	d
+DAT_FIFOS_ENABLED_SFT	include/ssv6200_aux.h	4723;"	d
+DAT_FIFOS_ENABLED_SZ	include/ssv6200_aux.h	4725;"	d
+DAT_FIFO_EN_HI	include/ssv6200_aux.h	4529;"	d
+DAT_FIFO_EN_I_MSK	include/ssv6200_aux.h	4527;"	d
+DAT_FIFO_EN_MSK	include/ssv6200_aux.h	4526;"	d
+DAT_FIFO_EN_SFT	include/ssv6200_aux.h	4528;"	d
+DAT_FIFO_EN_SZ	include/ssv6200_aux.h	4530;"	d
+DAT_FORCE_PARITY_HI	include/ssv6200_aux.h	4584;"	d
+DAT_FORCE_PARITY_I_MSK	include/ssv6200_aux.h	4582;"	d
+DAT_FORCE_PARITY_MSK	include/ssv6200_aux.h	4581;"	d
+DAT_FORCE_PARITY_SFT	include/ssv6200_aux.h	4583;"	d
+DAT_FORCE_PARITY_SZ	include/ssv6200_aux.h	4585;"	d
+DAT_FRAMING_ERR_HI	include/ssv6200_aux.h	4639;"	d
+DAT_FRAMING_ERR_I_MSK	include/ssv6200_aux.h	4637;"	d
+DAT_FRAMING_ERR_MSK	include/ssv6200_aux.h	4636;"	d
+DAT_FRAMING_ERR_SFT	include/ssv6200_aux.h	4638;"	d
+DAT_FRAMING_ERR_SZ	include/ssv6200_aux.h	4640;"	d
+DAT_INT_IDCODE_HI	include/ssv6200_aux.h	4719;"	d
+DAT_INT_IDCODE_I_MSK	include/ssv6200_aux.h	4717;"	d
+DAT_INT_IDCODE_MSK	include/ssv6200_aux.h	4716;"	d
+DAT_INT_IDCODE_SFT	include/ssv6200_aux.h	4718;"	d
+DAT_INT_IDCODE_SZ	include/ssv6200_aux.h	4720;"	d
+DAT_LOOP_BACK_HI	include/ssv6200_aux.h	4619;"	d
+DAT_LOOP_BACK_I_MSK	include/ssv6200_aux.h	4617;"	d
+DAT_LOOP_BACK_MSK	include/ssv6200_aux.h	4616;"	d
+DAT_LOOP_BACK_SFT	include/ssv6200_aux.h	4618;"	d
+DAT_LOOP_BACK_SZ	include/ssv6200_aux.h	4620;"	d
+DAT_MDM_STS_IE_HI	include/ssv6200_aux.h	4514;"	d
+DAT_MDM_STS_IE_I_MSK	include/ssv6200_aux.h	4512;"	d
+DAT_MDM_STS_IE_MSK	include/ssv6200_aux.h	4511;"	d
+DAT_MDM_STS_IE_SFT	include/ssv6200_aux.h	4513;"	d
+DAT_MDM_STS_IE_SZ	include/ssv6200_aux.h	4515;"	d
+DAT_MODE_OFF_HI	include/ssv6200_aux.h	4099;"	d
+DAT_MODE_OFF_I_MSK	include/ssv6200_aux.h	4097;"	d
+DAT_MODE_OFF_MSK	include/ssv6200_aux.h	4096;"	d
+DAT_MODE_OFF_SFT	include/ssv6200_aux.h	4098;"	d
+DAT_MODE_OFF_SZ	include/ssv6200_aux.h	4100;"	d
+DAT_OUT_1_HI	include/ssv6200_aux.h	4609;"	d
+DAT_OUT_1_I_MSK	include/ssv6200_aux.h	4607;"	d
+DAT_OUT_1_MSK	include/ssv6200_aux.h	4606;"	d
+DAT_OUT_1_SFT	include/ssv6200_aux.h	4608;"	d
+DAT_OUT_1_SZ	include/ssv6200_aux.h	4610;"	d
+DAT_OUT_2_HI	include/ssv6200_aux.h	4614;"	d
+DAT_OUT_2_I_MSK	include/ssv6200_aux.h	4612;"	d
+DAT_OUT_2_MSK	include/ssv6200_aux.h	4611;"	d
+DAT_OUT_2_SFT	include/ssv6200_aux.h	4613;"	d
+DAT_OUT_2_SZ	include/ssv6200_aux.h	4615;"	d
+DAT_OUT_EDGE_HI	include/ssv6200_aux.h	3349;"	d
+DAT_OUT_EDGE_I_MSK	include/ssv6200_aux.h	3347;"	d
+DAT_OUT_EDGE_MSK	include/ssv6200_aux.h	3346;"	d
+DAT_OUT_EDGE_SFT	include/ssv6200_aux.h	3348;"	d
+DAT_OUT_EDGE_SZ	include/ssv6200_aux.h	3350;"	d
+DAT_OVERRUN_ERR_HI	include/ssv6200_aux.h	4629;"	d
+DAT_OVERRUN_ERR_I_MSK	include/ssv6200_aux.h	4627;"	d
+DAT_OVERRUN_ERR_MSK	include/ssv6200_aux.h	4626;"	d
+DAT_OVERRUN_ERR_SFT	include/ssv6200_aux.h	4628;"	d
+DAT_OVERRUN_ERR_SZ	include/ssv6200_aux.h	4630;"	d
+DAT_PARITY_EN_HI	include/ssv6200_aux.h	4574;"	d
+DAT_PARITY_EN_I_MSK	include/ssv6200_aux.h	4572;"	d
+DAT_PARITY_EN_MSK	include/ssv6200_aux.h	4571;"	d
+DAT_PARITY_EN_SFT	include/ssv6200_aux.h	4573;"	d
+DAT_PARITY_EN_SZ	include/ssv6200_aux.h	4575;"	d
+DAT_PARITY_ERR_HI	include/ssv6200_aux.h	4634;"	d
+DAT_PARITY_ERR_I_MSK	include/ssv6200_aux.h	4632;"	d
+DAT_PARITY_ERR_MSK	include/ssv6200_aux.h	4631;"	d
+DAT_PARITY_ERR_SFT	include/ssv6200_aux.h	4633;"	d
+DAT_PARITY_ERR_SZ	include/ssv6200_aux.h	4635;"	d
+DAT_RI_HI	include/ssv6200_aux.h	4694;"	d
+DAT_RI_I_MSK	include/ssv6200_aux.h	4692;"	d
+DAT_RI_MSK	include/ssv6200_aux.h	4691;"	d
+DAT_RI_SFT	include/ssv6200_aux.h	4693;"	d
+DAT_RI_SZ	include/ssv6200_aux.h	4695;"	d
+DAT_RTHR_H_HI	include/ssv6200_aux.h	4714;"	d
+DAT_RTHR_H_I_MSK	include/ssv6200_aux.h	4712;"	d
+DAT_RTHR_H_MSK	include/ssv6200_aux.h	4711;"	d
+DAT_RTHR_H_SFT	include/ssv6200_aux.h	4713;"	d
+DAT_RTHR_H_SZ	include/ssv6200_aux.h	4715;"	d
+DAT_RTHR_L_HI	include/ssv6200_aux.h	4709;"	d
+DAT_RTHR_L_I_MSK	include/ssv6200_aux.h	4707;"	d
+DAT_RTHR_L_MSK	include/ssv6200_aux.h	4706;"	d
+DAT_RTHR_L_SFT	include/ssv6200_aux.h	4708;"	d
+DAT_RTHR_L_SZ	include/ssv6200_aux.h	4710;"	d
+DAT_RTS_HI	include/ssv6200_aux.h	4604;"	d
+DAT_RTS_I_MSK	include/ssv6200_aux.h	4602;"	d
+DAT_RTS_MSK	include/ssv6200_aux.h	4601;"	d
+DAT_RTS_SFT	include/ssv6200_aux.h	4603;"	d
+DAT_RTS_SZ	include/ssv6200_aux.h	4605;"	d
+DAT_RXFIFO_RST_HI	include/ssv6200_aux.h	4534;"	d
+DAT_RXFIFO_RST_I_MSK	include/ssv6200_aux.h	4532;"	d
+DAT_RXFIFO_RST_MSK	include/ssv6200_aux.h	4531;"	d
+DAT_RXFIFO_RST_SFT	include/ssv6200_aux.h	4533;"	d
+DAT_RXFIFO_RST_SZ	include/ssv6200_aux.h	4535;"	d
+DAT_RXFIFO_TRGLVL_HI	include/ssv6200_aux.h	4559;"	d
+DAT_RXFIFO_TRGLVL_I_MSK	include/ssv6200_aux.h	4557;"	d
+DAT_RXFIFO_TRGLVL_MSK	include/ssv6200_aux.h	4556;"	d
+DAT_RXFIFO_TRGLVL_SFT	include/ssv6200_aux.h	4558;"	d
+DAT_RXFIFO_TRGLVL_SZ	include/ssv6200_aux.h	4560;"	d
+DAT_RX_LINESTS_IE_HI	include/ssv6200_aux.h	4509;"	d
+DAT_RX_LINESTS_IE_I_MSK	include/ssv6200_aux.h	4507;"	d
+DAT_RX_LINESTS_IE_MSK	include/ssv6200_aux.h	4506;"	d
+DAT_RX_LINESTS_IE_SFT	include/ssv6200_aux.h	4508;"	d
+DAT_RX_LINESTS_IE_SZ	include/ssv6200_aux.h	4510;"	d
+DAT_SET_BREAK_HI	include/ssv6200_aux.h	4589;"	d
+DAT_SET_BREAK_I_MSK	include/ssv6200_aux.h	4587;"	d
+DAT_SET_BREAK_MSK	include/ssv6200_aux.h	4586;"	d
+DAT_SET_BREAK_SFT	include/ssv6200_aux.h	4588;"	d
+DAT_SET_BREAK_SZ	include/ssv6200_aux.h	4590;"	d
+DAT_STOP_BIT_HI	include/ssv6200_aux.h	4569;"	d
+DAT_STOP_BIT_I_MSK	include/ssv6200_aux.h	4567;"	d
+DAT_STOP_BIT_MSK	include/ssv6200_aux.h	4566;"	d
+DAT_STOP_BIT_SFT	include/ssv6200_aux.h	4568;"	d
+DAT_STOP_BIT_SZ	include/ssv6200_aux.h	4570;"	d
+DAT_THR_EMPTY_HI	include/ssv6200_aux.h	4649;"	d
+DAT_THR_EMPTY_IE_HI	include/ssv6200_aux.h	4504;"	d
+DAT_THR_EMPTY_IE_I_MSK	include/ssv6200_aux.h	4502;"	d
+DAT_THR_EMPTY_IE_MSK	include/ssv6200_aux.h	4501;"	d
+DAT_THR_EMPTY_IE_SFT	include/ssv6200_aux.h	4503;"	d
+DAT_THR_EMPTY_IE_SZ	include/ssv6200_aux.h	4505;"	d
+DAT_THR_EMPTY_I_MSK	include/ssv6200_aux.h	4647;"	d
+DAT_THR_EMPTY_MSK	include/ssv6200_aux.h	4646;"	d
+DAT_THR_EMPTY_SFT	include/ssv6200_aux.h	4648;"	d
+DAT_THR_EMPTY_SZ	include/ssv6200_aux.h	4650;"	d
+DAT_TRAILEDGE_RI_HI	include/ssv6200_aux.h	4674;"	d
+DAT_TRAILEDGE_RI_I_MSK	include/ssv6200_aux.h	4672;"	d
+DAT_TRAILEDGE_RI_MSK	include/ssv6200_aux.h	4671;"	d
+DAT_TRAILEDGE_RI_SFT	include/ssv6200_aux.h	4673;"	d
+DAT_TRAILEDGE_RI_SZ	include/ssv6200_aux.h	4675;"	d
+DAT_TXFIFO_RST_HI	include/ssv6200_aux.h	4539;"	d
+DAT_TXFIFO_RST_I_MSK	include/ssv6200_aux.h	4537;"	d
+DAT_TXFIFO_RST_MSK	include/ssv6200_aux.h	4536;"	d
+DAT_TXFIFO_RST_SFT	include/ssv6200_aux.h	4538;"	d
+DAT_TXFIFO_RST_SZ	include/ssv6200_aux.h	4540;"	d
+DAT_TX_EMPTY_HI	include/ssv6200_aux.h	4654;"	d
+DAT_TX_EMPTY_I_MSK	include/ssv6200_aux.h	4652;"	d
+DAT_TX_EMPTY_MSK	include/ssv6200_aux.h	4651;"	d
+DAT_TX_EMPTY_SFT	include/ssv6200_aux.h	4653;"	d
+DAT_TX_EMPTY_SZ	include/ssv6200_aux.h	4655;"	d
+DAT_UART_DATA_HI	include/ssv6200_aux.h	4494;"	d
+DAT_UART_DATA_I_MSK	include/ssv6200_aux.h	4492;"	d
+DAT_UART_DATA_MSK	include/ssv6200_aux.h	4491;"	d
+DAT_UART_DATA_SFT	include/ssv6200_aux.h	4493;"	d
+DAT_UART_DATA_SZ	include/ssv6200_aux.h	4495;"	d
+DAT_UART_MULTI_IRQ_HI	include/ssv6200_aux.h	5054;"	d
+DAT_UART_MULTI_IRQ_I_MSK	include/ssv6200_aux.h	5052;"	d
+DAT_UART_MULTI_IRQ_MSK	include/ssv6200_aux.h	5051;"	d
+DAT_UART_MULTI_IRQ_SD_HI	include/ssv6200_aux.h	5399;"	d
+DAT_UART_MULTI_IRQ_SD_I_MSK	include/ssv6200_aux.h	5397;"	d
+DAT_UART_MULTI_IRQ_SD_MSK	include/ssv6200_aux.h	5396;"	d
+DAT_UART_MULTI_IRQ_SD_SFT	include/ssv6200_aux.h	5398;"	d
+DAT_UART_MULTI_IRQ_SD_SZ	include/ssv6200_aux.h	5400;"	d
+DAT_UART_MULTI_IRQ_SFT	include/ssv6200_aux.h	5053;"	d
+DAT_UART_MULTI_IRQ_SZ	include/ssv6200_aux.h	5055;"	d
+DAT_UART_NCTS_SEL_HI	include/ssv6200_aux.h	2969;"	d
+DAT_UART_NCTS_SEL_I_MSK	include/ssv6200_aux.h	2967;"	d
+DAT_UART_NCTS_SEL_MSK	include/ssv6200_aux.h	2966;"	d
+DAT_UART_NCTS_SEL_SFT	include/ssv6200_aux.h	2968;"	d
+DAT_UART_NCTS_SEL_SZ	include/ssv6200_aux.h	2970;"	d
+DAT_UART_REG_BANK_SIZE	include/ssv6200_reg.h	82;"	d
+DAT_UART_REG_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	101;"	d
+DAT_UART_REG_BASE	include/ssv6200_reg.h	33;"	d
+DAT_UART_REG_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	40;"	d
+DAT_UART_RXD_SEL_0_HI	include/ssv6200_aux.h	3019;"	d
+DAT_UART_RXD_SEL_0_I_MSK	include/ssv6200_aux.h	3017;"	d
+DAT_UART_RXD_SEL_0_MSK	include/ssv6200_aux.h	3016;"	d
+DAT_UART_RXD_SEL_0_SFT	include/ssv6200_aux.h	3018;"	d
+DAT_UART_RXD_SEL_0_SZ	include/ssv6200_aux.h	3020;"	d
+DAT_UART_RXD_SEL_1_HI	include/ssv6200_aux.h	3024;"	d
+DAT_UART_RXD_SEL_1_I_MSK	include/ssv6200_aux.h	3022;"	d
+DAT_UART_RXD_SEL_1_MSK	include/ssv6200_aux.h	3021;"	d
+DAT_UART_RXD_SEL_1_SFT	include/ssv6200_aux.h	3023;"	d
+DAT_UART_RXD_SEL_1_SZ	include/ssv6200_aux.h	3025;"	d
+DAT_UART_RX_TIMEOUT_HI	include/ssv6200_aux.h	5049;"	d
+DAT_UART_RX_TIMEOUT_I_MSK	include/ssv6200_aux.h	5047;"	d
+DAT_UART_RX_TIMEOUT_MSK	include/ssv6200_aux.h	5046;"	d
+DAT_UART_RX_TIMEOUT_SD_HI	include/ssv6200_aux.h	5394;"	d
+DAT_UART_RX_TIMEOUT_SD_I_MSK	include/ssv6200_aux.h	5392;"	d
+DAT_UART_RX_TIMEOUT_SD_MSK	include/ssv6200_aux.h	5391;"	d
+DAT_UART_RX_TIMEOUT_SD_SFT	include/ssv6200_aux.h	5393;"	d
+DAT_UART_RX_TIMEOUT_SD_SZ	include/ssv6200_aux.h	5395;"	d
+DAT_UART_RX_TIMEOUT_SFT	include/ssv6200_aux.h	5048;"	d
+DAT_UART_RX_TIMEOUT_SZ	include/ssv6200_aux.h	5050;"	d
+DAT_UART_SW_RST_HI	include/ssv6200_aux.h	129;"	d
+DAT_UART_SW_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1079;"	d
+DAT_UART_SW_RST_I_MSK	include/ssv6200_aux.h	127;"	d
+DAT_UART_SW_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1077;"	d
+DAT_UART_SW_RST_MSK	include/ssv6200_aux.h	126;"	d
+DAT_UART_SW_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1076;"	d
+DAT_UART_SW_RST_SFT	include/ssv6200_aux.h	128;"	d
+DAT_UART_SW_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1078;"	d
+DAT_UART_SW_RST_SZ	include/ssv6200_aux.h	130;"	d
+DAT_UART_SW_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1080;"	d
+DAT_WORD_LEN_HI	include/ssv6200_aux.h	4564;"	d
+DAT_WORD_LEN_I_MSK	include/ssv6200_aux.h	4562;"	d
+DAT_WORD_LEN_MSK	include/ssv6200_aux.h	4561;"	d
+DAT_WORD_LEN_SFT	include/ssv6200_aux.h	4563;"	d
+DAT_WORD_LEN_SZ	include/ssv6200_aux.h	4565;"	d
+DA_R_CAL_CODE_HI	include/ssv6200_aux.h	17604;"	d
+DA_R_CAL_CODE_I_MSK	include/ssv6200_aux.h	17602;"	d
+DA_R_CAL_CODE_MSK	include/ssv6200_aux.h	17601;"	d
+DA_R_CAL_CODE_SFT	include/ssv6200_aux.h	17603;"	d
+DA_R_CAL_CODE_SZ	include/ssv6200_aux.h	17605;"	d
+DA_R_CODE_LUT_HI	include/ssv6200_aux.h	17569;"	d
+DA_R_CODE_LUT_I_MSK	include/ssv6200_aux.h	17567;"	d
+DA_R_CODE_LUT_MSK	include/ssv6200_aux.h	17566;"	d
+DA_R_CODE_LUT_SFT	include/ssv6200_aux.h	17568;"	d
+DA_R_CODE_LUT_SZ	include/ssv6200_aux.h	17570;"	d
+DA_SX_SUB_SEL_HI	include/ssv6200_aux.h	17609;"	d
+DA_SX_SUB_SEL_I_MSK	include/ssv6200_aux.h	17607;"	d
+DA_SX_SUB_SEL_MSK	include/ssv6200_aux.h	17606;"	d
+DA_SX_SUB_SEL_SFT	include/ssv6200_aux.h	17608;"	d
+DA_SX_SUB_SEL_SZ	include/ssv6200_aux.h	17610;"	d
+DBG_ADDR_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5249;"	d
+DBG_ADDR_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5247;"	d
+DBG_ADDR_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5246;"	d
+DBG_ADDR_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5248;"	d
+DBG_ADDR_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5250;"	d
+DBG_ADDR_FENCE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5254;"	d
+DBG_ADDR_FENCE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5252;"	d
+DBG_ADDR_FENCE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5251;"	d
+DBG_ADDR_FENCE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5253;"	d
+DBG_ADDR_FENCE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5255;"	d
+DBG_ALC_LOG_EN_HI	include/ssv6200_aux.h	11729;"	d
+DBG_ALC_LOG_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33384;"	d
+DBG_ALC_LOG_EN_I_MSK	include/ssv6200_aux.h	11727;"	d
+DBG_ALC_LOG_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33382;"	d
+DBG_ALC_LOG_EN_MSK	include/ssv6200_aux.h	11726;"	d
+DBG_ALC_LOG_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33381;"	d
+DBG_ALC_LOG_EN_SFT	include/ssv6200_aux.h	11728;"	d
+DBG_ALC_LOG_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33383;"	d
+DBG_ALC_LOG_EN_SZ	include/ssv6200_aux.h	11730;"	d
+DBG_ALC_LOG_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33385;"	d
+DBG_AMPDU_FAIL_HI	include/ssv6200_aux.h	9709;"	d
+DBG_AMPDU_FAIL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9544;"	d
+DBG_AMPDU_FAIL_I_MSK	include/ssv6200_aux.h	9707;"	d
+DBG_AMPDU_FAIL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9542;"	d
+DBG_AMPDU_FAIL_MSK	include/ssv6200_aux.h	9706;"	d
+DBG_AMPDU_FAIL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9541;"	d
+DBG_AMPDU_FAIL_SFT	include/ssv6200_aux.h	9708;"	d
+DBG_AMPDU_FAIL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9543;"	d
+DBG_AMPDU_FAIL_SZ	include/ssv6200_aux.h	9710;"	d
+DBG_AMPDU_FAIL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9545;"	d
+DBG_AMPDU_PASS_HI	include/ssv6200_aux.h	9704;"	d
+DBG_AMPDU_PASS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9539;"	d
+DBG_AMPDU_PASS_I_MSK	include/ssv6200_aux.h	9702;"	d
+DBG_AMPDU_PASS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9537;"	d
+DBG_AMPDU_PASS_MSK	include/ssv6200_aux.h	9701;"	d
+DBG_AMPDU_PASS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9536;"	d
+DBG_AMPDU_PASS_SFT	include/ssv6200_aux.h	9703;"	d
+DBG_AMPDU_PASS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9538;"	d
+DBG_AMPDU_PASS_SZ	include/ssv6200_aux.h	9705;"	d
+DBG_AMPDU_PASS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9540;"	d
+DBG_BACK_DLY_HI	include/ssv6200_aux.h	5454;"	d
+DBG_BACK_DLY_I_MSK	include/ssv6200_aux.h	5452;"	d
+DBG_BACK_DLY_MSK	include/ssv6200_aux.h	5451;"	d
+DBG_BACK_DLY_SFT	include/ssv6200_aux.h	5453;"	d
+DBG_BACK_DLY_SZ	include/ssv6200_aux.h	5455;"	d
+DBG_BA_SEQ_HI	include/ssv6200_aux.h	6969;"	d
+DBG_BA_SEQ_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6144;"	d
+DBG_BA_SEQ_I_MSK	include/ssv6200_aux.h	6967;"	d
+DBG_BA_SEQ_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6142;"	d
+DBG_BA_SEQ_MSK	include/ssv6200_aux.h	6966;"	d
+DBG_BA_SEQ_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6141;"	d
+DBG_BA_SEQ_SFT	include/ssv6200_aux.h	6968;"	d
+DBG_BA_SEQ_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6143;"	d
+DBG_BA_SEQ_SZ	include/ssv6200_aux.h	6970;"	d
+DBG_BA_SEQ_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6145;"	d
+DBG_BA_TYPE_HI	include/ssv6200_aux.h	6964;"	d
+DBG_BA_TYPE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6139;"	d
+DBG_BA_TYPE_I_MSK	include/ssv6200_aux.h	6962;"	d
+DBG_BA_TYPE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6137;"	d
+DBG_BA_TYPE_MSK	include/ssv6200_aux.h	6961;"	d
+DBG_BA_TYPE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6136;"	d
+DBG_BA_TYPE_SFT	include/ssv6200_aux.h	6963;"	d
+DBG_BA_TYPE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6138;"	d
+DBG_BA_TYPE_SZ	include/ssv6200_aux.h	6965;"	d
+DBG_BA_TYPE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6140;"	d
+DBG_BRST_MODE_HI	include/ssv6200_aux.h	5439;"	d
+DBG_BRST_MODE_I_MSK	include/ssv6200_aux.h	5437;"	d
+DBG_BRST_MODE_MSK	include/ssv6200_aux.h	5436;"	d
+DBG_BRST_MODE_SFT	include/ssv6200_aux.h	5438;"	d
+DBG_BRST_MODE_SZ	include/ssv6200_aux.h	5440;"	d
+DBG_CFRM_BUSY_HI	include/ssv6200_aux.h	7754;"	d
+DBG_CFRM_BUSY_I_MSK	include/ssv6200_aux.h	7752;"	d
+DBG_CFRM_BUSY_MSK	include/ssv6200_aux.h	7751;"	d
+DBG_CFRM_BUSY_SFT	include/ssv6200_aux.h	7753;"	d
+DBG_CFRM_BUSY_SZ	include/ssv6200_aux.h	7755;"	d
+DBG_CLK_WIDTH_HI	include/ssv6200_aux.h	5444;"	d
+DBG_CLK_WIDTH_I_MSK	include/ssv6200_aux.h	5442;"	d
+DBG_CLK_WIDTH_MSK	include/ssv6200_aux.h	5441;"	d
+DBG_CLK_WIDTH_SFT	include/ssv6200_aux.h	5443;"	d
+DBG_CLK_WIDTH_SZ	include/ssv6200_aux.h	5445;"	d
+DBG_CONDI_NUM_HI	include/ssv6200_aux.h	5424;"	d
+DBG_CONDI_NUM_I_MSK	include/ssv6200_aux.h	5422;"	d
+DBG_CONDI_NUM_MSK	include/ssv6200_aux.h	5421;"	d
+DBG_CONDI_NUM_SFT	include/ssv6200_aux.h	5423;"	d
+DBG_CONDI_NUM_SZ	include/ssv6200_aux.h	5425;"	d
+DBG_CSN_INTER_HI	include/ssv6200_aux.h	5449;"	d
+DBG_CSN_INTER_I_MSK	include/ssv6200_aux.h	5447;"	d
+DBG_CSN_INTER_MSK	include/ssv6200_aux.h	5446;"	d
+DBG_CSN_INTER_SFT	include/ssv6200_aux.h	5448;"	d
+DBG_CSN_INTER_SZ	include/ssv6200_aux.h	5450;"	d
+DBG_DAT_MODE_OFF_HI	include/ssv6200_aux.h	5589;"	d
+DBG_DAT_MODE_OFF_I_MSK	include/ssv6200_aux.h	5587;"	d
+DBG_DAT_MODE_OFF_MSK	include/ssv6200_aux.h	5586;"	d
+DBG_DAT_MODE_OFF_SFT	include/ssv6200_aux.h	5588;"	d
+DBG_DAT_MODE_OFF_SZ	include/ssv6200_aux.h	5590;"	d
+DBG_DMA_RDY_HI	include/ssv6200_aux.h	7744;"	d
+DBG_DMA_RDY_I_MSK	include/ssv6200_aux.h	7742;"	d
+DBG_DMA_RDY_MSK	include/ssv6200_aux.h	7741;"	d
+DBG_DMA_RDY_SFT	include/ssv6200_aux.h	7743;"	d
+DBG_DMA_RDY_SZ	include/ssv6200_aux.h	7745;"	d
+DBG_EDCA0_LOWTHOLD_INT_HI	include/ssv6200_aux.h	5614;"	d
+DBG_EDCA0_LOWTHOLD_INT_I_MSK	include/ssv6200_aux.h	5612;"	d
+DBG_EDCA0_LOWTHOLD_INT_MSK	include/ssv6200_aux.h	5611;"	d
+DBG_EDCA0_LOWTHOLD_INT_SFT	include/ssv6200_aux.h	5613;"	d
+DBG_EDCA0_LOWTHOLD_INT_SZ	include/ssv6200_aux.h	5615;"	d
+DBG_EDCA1_LOWTHOLD_INT_HI	include/ssv6200_aux.h	5619;"	d
+DBG_EDCA1_LOWTHOLD_INT_I_MSK	include/ssv6200_aux.h	5617;"	d
+DBG_EDCA1_LOWTHOLD_INT_MSK	include/ssv6200_aux.h	5616;"	d
+DBG_EDCA1_LOWTHOLD_INT_SFT	include/ssv6200_aux.h	5618;"	d
+DBG_EDCA1_LOWTHOLD_INT_SZ	include/ssv6200_aux.h	5620;"	d
+DBG_EDCA2_LOWTHOLD_INT_HI	include/ssv6200_aux.h	5624;"	d
+DBG_EDCA2_LOWTHOLD_INT_I_MSK	include/ssv6200_aux.h	5622;"	d
+DBG_EDCA2_LOWTHOLD_INT_MSK	include/ssv6200_aux.h	5621;"	d
+DBG_EDCA2_LOWTHOLD_INT_SFT	include/ssv6200_aux.h	5623;"	d
+DBG_EDCA2_LOWTHOLD_INT_SZ	include/ssv6200_aux.h	5625;"	d
+DBG_EDCA3_LOWTHOLD_INT_HI	include/ssv6200_aux.h	5629;"	d
+DBG_EDCA3_LOWTHOLD_INT_I_MSK	include/ssv6200_aux.h	5627;"	d
+DBG_EDCA3_LOWTHOLD_INT_MSK	include/ssv6200_aux.h	5626;"	d
+DBG_EDCA3_LOWTHOLD_INT_SFT	include/ssv6200_aux.h	5628;"	d
+DBG_EDCA3_LOWTHOLD_INT_SZ	include/ssv6200_aux.h	5630;"	d
+DBG_FF_FULL_CLR_HI	include/ssv6200_aux.h	7134;"	d
+DBG_FF_FULL_CLR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6309;"	d
+DBG_FF_FULL_CLR_I_MSK	include/ssv6200_aux.h	7132;"	d
+DBG_FF_FULL_CLR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6307;"	d
+DBG_FF_FULL_CLR_MSK	include/ssv6200_aux.h	7131;"	d
+DBG_FF_FULL_CLR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6306;"	d
+DBG_FF_FULL_CLR_SFT	include/ssv6200_aux.h	7133;"	d
+DBG_FF_FULL_CLR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6308;"	d
+DBG_FF_FULL_CLR_SZ	include/ssv6200_aux.h	7135;"	d
+DBG_FF_FULL_CLR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6310;"	d
+DBG_FF_FULL_HI	include/ssv6200_aux.h	7129;"	d
+DBG_FF_FULL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6304;"	d
+DBG_FF_FULL_I_MSK	include/ssv6200_aux.h	7127;"	d
+DBG_FF_FULL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6302;"	d
+DBG_FF_FULL_MSK	include/ssv6200_aux.h	7126;"	d
+DBG_FF_FULL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6301;"	d
+DBG_FF_FULL_SFT	include/ssv6200_aux.h	7128;"	d
+DBG_FF_FULL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6303;"	d
+DBG_FF_FULL_SZ	include/ssv6200_aux.h	7130;"	d
+DBG_FF_FULL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6305;"	d
+DBG_FRONT_DLY_HI	include/ssv6200_aux.h	5459;"	d
+DBG_FRONT_DLY_I_MSK	include/ssv6200_aux.h	5457;"	d
+DBG_FRONT_DLY_MSK	include/ssv6200_aux.h	5456;"	d
+DBG_FRONT_DLY_SFT	include/ssv6200_aux.h	5458;"	d
+DBG_FRONT_DLY_SZ	include/ssv6200_aux.h	5460;"	d
+DBG_HOST_PATH_HI	include/ssv6200_aux.h	5429;"	d
+DBG_HOST_PATH_I_MSK	include/ssv6200_aux.h	5427;"	d
+DBG_HOST_PATH_MSK	include/ssv6200_aux.h	5426;"	d
+DBG_HOST_PATH_SFT	include/ssv6200_aux.h	5428;"	d
+DBG_HOST_PATH_SZ	include/ssv6200_aux.h	5430;"	d
+DBG_HWID0_RD_EN_HI	include/ssv6200_aux.h	11839;"	d
+DBG_HWID0_RD_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33494;"	d
+DBG_HWID0_RD_EN_I_MSK	include/ssv6200_aux.h	11837;"	d
+DBG_HWID0_RD_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33492;"	d
+DBG_HWID0_RD_EN_MSK	include/ssv6200_aux.h	11836;"	d
+DBG_HWID0_RD_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33491;"	d
+DBG_HWID0_RD_EN_SFT	include/ssv6200_aux.h	11838;"	d
+DBG_HWID0_RD_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33493;"	d
+DBG_HWID0_RD_EN_SZ	include/ssv6200_aux.h	11840;"	d
+DBG_HWID0_RD_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33495;"	d
+DBG_HWID0_WR_EN_HI	include/ssv6200_aux.h	11759;"	d
+DBG_HWID0_WR_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33414;"	d
+DBG_HWID0_WR_EN_I_MSK	include/ssv6200_aux.h	11757;"	d
+DBG_HWID0_WR_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33412;"	d
+DBG_HWID0_WR_EN_MSK	include/ssv6200_aux.h	11756;"	d
+DBG_HWID0_WR_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33411;"	d
+DBG_HWID0_WR_EN_SFT	include/ssv6200_aux.h	11758;"	d
+DBG_HWID0_WR_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33413;"	d
+DBG_HWID0_WR_EN_SZ	include/ssv6200_aux.h	11760;"	d
+DBG_HWID0_WR_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33415;"	d
+DBG_HWID10_RD_EN_HI	include/ssv6200_aux.h	11889;"	d
+DBG_HWID10_RD_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33544;"	d
+DBG_HWID10_RD_EN_I_MSK	include/ssv6200_aux.h	11887;"	d
+DBG_HWID10_RD_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33542;"	d
+DBG_HWID10_RD_EN_MSK	include/ssv6200_aux.h	11886;"	d
+DBG_HWID10_RD_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33541;"	d
+DBG_HWID10_RD_EN_SFT	include/ssv6200_aux.h	11888;"	d
+DBG_HWID10_RD_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33543;"	d
+DBG_HWID10_RD_EN_SZ	include/ssv6200_aux.h	11890;"	d
+DBG_HWID10_RD_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33545;"	d
+DBG_HWID10_WR_EN_HI	include/ssv6200_aux.h	11809;"	d
+DBG_HWID10_WR_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33464;"	d
+DBG_HWID10_WR_EN_I_MSK	include/ssv6200_aux.h	11807;"	d
+DBG_HWID10_WR_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33462;"	d
+DBG_HWID10_WR_EN_MSK	include/ssv6200_aux.h	11806;"	d
+DBG_HWID10_WR_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33461;"	d
+DBG_HWID10_WR_EN_SFT	include/ssv6200_aux.h	11808;"	d
+DBG_HWID10_WR_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33463;"	d
+DBG_HWID10_WR_EN_SZ	include/ssv6200_aux.h	11810;"	d
+DBG_HWID10_WR_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33465;"	d
+DBG_HWID11_RD_EN_HI	include/ssv6200_aux.h	11894;"	d
+DBG_HWID11_RD_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33549;"	d
+DBG_HWID11_RD_EN_I_MSK	include/ssv6200_aux.h	11892;"	d
+DBG_HWID11_RD_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33547;"	d
+DBG_HWID11_RD_EN_MSK	include/ssv6200_aux.h	11891;"	d
+DBG_HWID11_RD_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33546;"	d
+DBG_HWID11_RD_EN_SFT	include/ssv6200_aux.h	11893;"	d
+DBG_HWID11_RD_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33548;"	d
+DBG_HWID11_RD_EN_SZ	include/ssv6200_aux.h	11895;"	d
+DBG_HWID11_RD_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33550;"	d
+DBG_HWID11_WR_EN_HI	include/ssv6200_aux.h	11814;"	d
+DBG_HWID11_WR_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33469;"	d
+DBG_HWID11_WR_EN_I_MSK	include/ssv6200_aux.h	11812;"	d
+DBG_HWID11_WR_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33467;"	d
+DBG_HWID11_WR_EN_MSK	include/ssv6200_aux.h	11811;"	d
+DBG_HWID11_WR_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33466;"	d
+DBG_HWID11_WR_EN_SFT	include/ssv6200_aux.h	11813;"	d
+DBG_HWID11_WR_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33468;"	d
+DBG_HWID11_WR_EN_SZ	include/ssv6200_aux.h	11815;"	d
+DBG_HWID11_WR_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33470;"	d
+DBG_HWID12_RD_EN_HI	include/ssv6200_aux.h	11899;"	d
+DBG_HWID12_RD_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33554;"	d
+DBG_HWID12_RD_EN_I_MSK	include/ssv6200_aux.h	11897;"	d
+DBG_HWID12_RD_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33552;"	d
+DBG_HWID12_RD_EN_MSK	include/ssv6200_aux.h	11896;"	d
+DBG_HWID12_RD_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33551;"	d
+DBG_HWID12_RD_EN_SFT	include/ssv6200_aux.h	11898;"	d
+DBG_HWID12_RD_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33553;"	d
+DBG_HWID12_RD_EN_SZ	include/ssv6200_aux.h	11900;"	d
+DBG_HWID12_RD_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33555;"	d
+DBG_HWID12_WR_EN_HI	include/ssv6200_aux.h	11819;"	d
+DBG_HWID12_WR_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33474;"	d
+DBG_HWID12_WR_EN_I_MSK	include/ssv6200_aux.h	11817;"	d
+DBG_HWID12_WR_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33472;"	d
+DBG_HWID12_WR_EN_MSK	include/ssv6200_aux.h	11816;"	d
+DBG_HWID12_WR_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33471;"	d
+DBG_HWID12_WR_EN_SFT	include/ssv6200_aux.h	11818;"	d
+DBG_HWID12_WR_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33473;"	d
+DBG_HWID12_WR_EN_SZ	include/ssv6200_aux.h	11820;"	d
+DBG_HWID12_WR_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33475;"	d
+DBG_HWID13_RD_EN_HI	include/ssv6200_aux.h	11904;"	d
+DBG_HWID13_RD_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33559;"	d
+DBG_HWID13_RD_EN_I_MSK	include/ssv6200_aux.h	11902;"	d
+DBG_HWID13_RD_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33557;"	d
+DBG_HWID13_RD_EN_MSK	include/ssv6200_aux.h	11901;"	d
+DBG_HWID13_RD_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33556;"	d
+DBG_HWID13_RD_EN_SFT	include/ssv6200_aux.h	11903;"	d
+DBG_HWID13_RD_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33558;"	d
+DBG_HWID13_RD_EN_SZ	include/ssv6200_aux.h	11905;"	d
+DBG_HWID13_RD_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33560;"	d
+DBG_HWID13_WR_EN_HI	include/ssv6200_aux.h	11824;"	d
+DBG_HWID13_WR_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33479;"	d
+DBG_HWID13_WR_EN_I_MSK	include/ssv6200_aux.h	11822;"	d
+DBG_HWID13_WR_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33477;"	d
+DBG_HWID13_WR_EN_MSK	include/ssv6200_aux.h	11821;"	d
+DBG_HWID13_WR_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33476;"	d
+DBG_HWID13_WR_EN_SFT	include/ssv6200_aux.h	11823;"	d
+DBG_HWID13_WR_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33478;"	d
+DBG_HWID13_WR_EN_SZ	include/ssv6200_aux.h	11825;"	d
+DBG_HWID13_WR_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33480;"	d
+DBG_HWID14_RD_EN_HI	include/ssv6200_aux.h	11909;"	d
+DBG_HWID14_RD_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33564;"	d
+DBG_HWID14_RD_EN_I_MSK	include/ssv6200_aux.h	11907;"	d
+DBG_HWID14_RD_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33562;"	d
+DBG_HWID14_RD_EN_MSK	include/ssv6200_aux.h	11906;"	d
+DBG_HWID14_RD_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33561;"	d
+DBG_HWID14_RD_EN_SFT	include/ssv6200_aux.h	11908;"	d
+DBG_HWID14_RD_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33563;"	d
+DBG_HWID14_RD_EN_SZ	include/ssv6200_aux.h	11910;"	d
+DBG_HWID14_RD_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33565;"	d
+DBG_HWID14_WR_EN_HI	include/ssv6200_aux.h	11829;"	d
+DBG_HWID14_WR_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33484;"	d
+DBG_HWID14_WR_EN_I_MSK	include/ssv6200_aux.h	11827;"	d
+DBG_HWID14_WR_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33482;"	d
+DBG_HWID14_WR_EN_MSK	include/ssv6200_aux.h	11826;"	d
+DBG_HWID14_WR_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33481;"	d
+DBG_HWID14_WR_EN_SFT	include/ssv6200_aux.h	11828;"	d
+DBG_HWID14_WR_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33483;"	d
+DBG_HWID14_WR_EN_SZ	include/ssv6200_aux.h	11830;"	d
+DBG_HWID14_WR_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33485;"	d
+DBG_HWID15_RD_EN_HI	include/ssv6200_aux.h	11914;"	d
+DBG_HWID15_RD_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33569;"	d
+DBG_HWID15_RD_EN_I_MSK	include/ssv6200_aux.h	11912;"	d
+DBG_HWID15_RD_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33567;"	d
+DBG_HWID15_RD_EN_MSK	include/ssv6200_aux.h	11911;"	d
+DBG_HWID15_RD_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33566;"	d
+DBG_HWID15_RD_EN_SFT	include/ssv6200_aux.h	11913;"	d
+DBG_HWID15_RD_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33568;"	d
+DBG_HWID15_RD_EN_SZ	include/ssv6200_aux.h	11915;"	d
+DBG_HWID15_RD_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33570;"	d
+DBG_HWID15_WR_EN_HI	include/ssv6200_aux.h	11834;"	d
+DBG_HWID15_WR_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33489;"	d
+DBG_HWID15_WR_EN_I_MSK	include/ssv6200_aux.h	11832;"	d
+DBG_HWID15_WR_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33487;"	d
+DBG_HWID15_WR_EN_MSK	include/ssv6200_aux.h	11831;"	d
+DBG_HWID15_WR_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33486;"	d
+DBG_HWID15_WR_EN_SFT	include/ssv6200_aux.h	11833;"	d
+DBG_HWID15_WR_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33488;"	d
+DBG_HWID15_WR_EN_SZ	include/ssv6200_aux.h	11835;"	d
+DBG_HWID15_WR_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33490;"	d
+DBG_HWID1_RD_EN_HI	include/ssv6200_aux.h	11844;"	d
+DBG_HWID1_RD_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33499;"	d
+DBG_HWID1_RD_EN_I_MSK	include/ssv6200_aux.h	11842;"	d
+DBG_HWID1_RD_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33497;"	d
+DBG_HWID1_RD_EN_MSK	include/ssv6200_aux.h	11841;"	d
+DBG_HWID1_RD_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33496;"	d
+DBG_HWID1_RD_EN_SFT	include/ssv6200_aux.h	11843;"	d
+DBG_HWID1_RD_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33498;"	d
+DBG_HWID1_RD_EN_SZ	include/ssv6200_aux.h	11845;"	d
+DBG_HWID1_RD_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33500;"	d
+DBG_HWID1_WR_EN_HI	include/ssv6200_aux.h	11764;"	d
+DBG_HWID1_WR_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33419;"	d
+DBG_HWID1_WR_EN_I_MSK	include/ssv6200_aux.h	11762;"	d
+DBG_HWID1_WR_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33417;"	d
+DBG_HWID1_WR_EN_MSK	include/ssv6200_aux.h	11761;"	d
+DBG_HWID1_WR_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33416;"	d
+DBG_HWID1_WR_EN_SFT	include/ssv6200_aux.h	11763;"	d
+DBG_HWID1_WR_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33418;"	d
+DBG_HWID1_WR_EN_SZ	include/ssv6200_aux.h	11765;"	d
+DBG_HWID1_WR_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33420;"	d
+DBG_HWID2_RD_EN_HI	include/ssv6200_aux.h	11849;"	d
+DBG_HWID2_RD_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33504;"	d
+DBG_HWID2_RD_EN_I_MSK	include/ssv6200_aux.h	11847;"	d
+DBG_HWID2_RD_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33502;"	d
+DBG_HWID2_RD_EN_MSK	include/ssv6200_aux.h	11846;"	d
+DBG_HWID2_RD_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33501;"	d
+DBG_HWID2_RD_EN_SFT	include/ssv6200_aux.h	11848;"	d
+DBG_HWID2_RD_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33503;"	d
+DBG_HWID2_RD_EN_SZ	include/ssv6200_aux.h	11850;"	d
+DBG_HWID2_RD_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33505;"	d
+DBG_HWID2_WR_EN_HI	include/ssv6200_aux.h	11769;"	d
+DBG_HWID2_WR_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33424;"	d
+DBG_HWID2_WR_EN_I_MSK	include/ssv6200_aux.h	11767;"	d
+DBG_HWID2_WR_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33422;"	d
+DBG_HWID2_WR_EN_MSK	include/ssv6200_aux.h	11766;"	d
+DBG_HWID2_WR_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33421;"	d
+DBG_HWID2_WR_EN_SFT	include/ssv6200_aux.h	11768;"	d
+DBG_HWID2_WR_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33423;"	d
+DBG_HWID2_WR_EN_SZ	include/ssv6200_aux.h	11770;"	d
+DBG_HWID2_WR_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33425;"	d
+DBG_HWID3_RD_EN_HI	include/ssv6200_aux.h	11854;"	d
+DBG_HWID3_RD_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33509;"	d
+DBG_HWID3_RD_EN_I_MSK	include/ssv6200_aux.h	11852;"	d
+DBG_HWID3_RD_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33507;"	d
+DBG_HWID3_RD_EN_MSK	include/ssv6200_aux.h	11851;"	d
+DBG_HWID3_RD_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33506;"	d
+DBG_HWID3_RD_EN_SFT	include/ssv6200_aux.h	11853;"	d
+DBG_HWID3_RD_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33508;"	d
+DBG_HWID3_RD_EN_SZ	include/ssv6200_aux.h	11855;"	d
+DBG_HWID3_RD_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33510;"	d
+DBG_HWID3_WR_EN_HI	include/ssv6200_aux.h	11774;"	d
+DBG_HWID3_WR_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33429;"	d
+DBG_HWID3_WR_EN_I_MSK	include/ssv6200_aux.h	11772;"	d
+DBG_HWID3_WR_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33427;"	d
+DBG_HWID3_WR_EN_MSK	include/ssv6200_aux.h	11771;"	d
+DBG_HWID3_WR_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33426;"	d
+DBG_HWID3_WR_EN_SFT	include/ssv6200_aux.h	11773;"	d
+DBG_HWID3_WR_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33428;"	d
+DBG_HWID3_WR_EN_SZ	include/ssv6200_aux.h	11775;"	d
+DBG_HWID3_WR_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33430;"	d
+DBG_HWID4_RD_EN_HI	include/ssv6200_aux.h	11859;"	d
+DBG_HWID4_RD_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33514;"	d
+DBG_HWID4_RD_EN_I_MSK	include/ssv6200_aux.h	11857;"	d
+DBG_HWID4_RD_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33512;"	d
+DBG_HWID4_RD_EN_MSK	include/ssv6200_aux.h	11856;"	d
+DBG_HWID4_RD_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33511;"	d
+DBG_HWID4_RD_EN_SFT	include/ssv6200_aux.h	11858;"	d
+DBG_HWID4_RD_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33513;"	d
+DBG_HWID4_RD_EN_SZ	include/ssv6200_aux.h	11860;"	d
+DBG_HWID4_RD_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33515;"	d
+DBG_HWID4_WR_EN_HI	include/ssv6200_aux.h	11779;"	d
+DBG_HWID4_WR_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33434;"	d
+DBG_HWID4_WR_EN_I_MSK	include/ssv6200_aux.h	11777;"	d
+DBG_HWID4_WR_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33432;"	d
+DBG_HWID4_WR_EN_MSK	include/ssv6200_aux.h	11776;"	d
+DBG_HWID4_WR_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33431;"	d
+DBG_HWID4_WR_EN_SFT	include/ssv6200_aux.h	11778;"	d
+DBG_HWID4_WR_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33433;"	d
+DBG_HWID4_WR_EN_SZ	include/ssv6200_aux.h	11780;"	d
+DBG_HWID4_WR_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33435;"	d
+DBG_HWID5_RD_EN_HI	include/ssv6200_aux.h	11864;"	d
+DBG_HWID5_RD_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33519;"	d
+DBG_HWID5_RD_EN_I_MSK	include/ssv6200_aux.h	11862;"	d
+DBG_HWID5_RD_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33517;"	d
+DBG_HWID5_RD_EN_MSK	include/ssv6200_aux.h	11861;"	d
+DBG_HWID5_RD_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33516;"	d
+DBG_HWID5_RD_EN_SFT	include/ssv6200_aux.h	11863;"	d
+DBG_HWID5_RD_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33518;"	d
+DBG_HWID5_RD_EN_SZ	include/ssv6200_aux.h	11865;"	d
+DBG_HWID5_RD_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33520;"	d
+DBG_HWID5_WR_EN_HI	include/ssv6200_aux.h	11784;"	d
+DBG_HWID5_WR_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33439;"	d
+DBG_HWID5_WR_EN_I_MSK	include/ssv6200_aux.h	11782;"	d
+DBG_HWID5_WR_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33437;"	d
+DBG_HWID5_WR_EN_MSK	include/ssv6200_aux.h	11781;"	d
+DBG_HWID5_WR_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33436;"	d
+DBG_HWID5_WR_EN_SFT	include/ssv6200_aux.h	11783;"	d
+DBG_HWID5_WR_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33438;"	d
+DBG_HWID5_WR_EN_SZ	include/ssv6200_aux.h	11785;"	d
+DBG_HWID5_WR_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33440;"	d
+DBG_HWID6_RD_EN_HI	include/ssv6200_aux.h	11869;"	d
+DBG_HWID6_RD_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33524;"	d
+DBG_HWID6_RD_EN_I_MSK	include/ssv6200_aux.h	11867;"	d
+DBG_HWID6_RD_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33522;"	d
+DBG_HWID6_RD_EN_MSK	include/ssv6200_aux.h	11866;"	d
+DBG_HWID6_RD_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33521;"	d
+DBG_HWID6_RD_EN_SFT	include/ssv6200_aux.h	11868;"	d
+DBG_HWID6_RD_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33523;"	d
+DBG_HWID6_RD_EN_SZ	include/ssv6200_aux.h	11870;"	d
+DBG_HWID6_RD_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33525;"	d
+DBG_HWID6_WR_EN_HI	include/ssv6200_aux.h	11789;"	d
+DBG_HWID6_WR_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33444;"	d
+DBG_HWID6_WR_EN_I_MSK	include/ssv6200_aux.h	11787;"	d
+DBG_HWID6_WR_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33442;"	d
+DBG_HWID6_WR_EN_MSK	include/ssv6200_aux.h	11786;"	d
+DBG_HWID6_WR_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33441;"	d
+DBG_HWID6_WR_EN_SFT	include/ssv6200_aux.h	11788;"	d
+DBG_HWID6_WR_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33443;"	d
+DBG_HWID6_WR_EN_SZ	include/ssv6200_aux.h	11790;"	d
+DBG_HWID6_WR_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33445;"	d
+DBG_HWID7_RD_EN_HI	include/ssv6200_aux.h	11874;"	d
+DBG_HWID7_RD_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33529;"	d
+DBG_HWID7_RD_EN_I_MSK	include/ssv6200_aux.h	11872;"	d
+DBG_HWID7_RD_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33527;"	d
+DBG_HWID7_RD_EN_MSK	include/ssv6200_aux.h	11871;"	d
+DBG_HWID7_RD_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33526;"	d
+DBG_HWID7_RD_EN_SFT	include/ssv6200_aux.h	11873;"	d
+DBG_HWID7_RD_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33528;"	d
+DBG_HWID7_RD_EN_SZ	include/ssv6200_aux.h	11875;"	d
+DBG_HWID7_RD_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33530;"	d
+DBG_HWID7_WR_EN_HI	include/ssv6200_aux.h	11794;"	d
+DBG_HWID7_WR_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33449;"	d
+DBG_HWID7_WR_EN_I_MSK	include/ssv6200_aux.h	11792;"	d
+DBG_HWID7_WR_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33447;"	d
+DBG_HWID7_WR_EN_MSK	include/ssv6200_aux.h	11791;"	d
+DBG_HWID7_WR_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33446;"	d
+DBG_HWID7_WR_EN_SFT	include/ssv6200_aux.h	11793;"	d
+DBG_HWID7_WR_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33448;"	d
+DBG_HWID7_WR_EN_SZ	include/ssv6200_aux.h	11795;"	d
+DBG_HWID7_WR_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33450;"	d
+DBG_HWID8_RD_EN_HI	include/ssv6200_aux.h	11879;"	d
+DBG_HWID8_RD_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33534;"	d
+DBG_HWID8_RD_EN_I_MSK	include/ssv6200_aux.h	11877;"	d
+DBG_HWID8_RD_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33532;"	d
+DBG_HWID8_RD_EN_MSK	include/ssv6200_aux.h	11876;"	d
+DBG_HWID8_RD_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33531;"	d
+DBG_HWID8_RD_EN_SFT	include/ssv6200_aux.h	11878;"	d
+DBG_HWID8_RD_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33533;"	d
+DBG_HWID8_RD_EN_SZ	include/ssv6200_aux.h	11880;"	d
+DBG_HWID8_RD_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33535;"	d
+DBG_HWID8_WR_EN_HI	include/ssv6200_aux.h	11799;"	d
+DBG_HWID8_WR_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33454;"	d
+DBG_HWID8_WR_EN_I_MSK	include/ssv6200_aux.h	11797;"	d
+DBG_HWID8_WR_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33452;"	d
+DBG_HWID8_WR_EN_MSK	include/ssv6200_aux.h	11796;"	d
+DBG_HWID8_WR_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33451;"	d
+DBG_HWID8_WR_EN_SFT	include/ssv6200_aux.h	11798;"	d
+DBG_HWID8_WR_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33453;"	d
+DBG_HWID8_WR_EN_SZ	include/ssv6200_aux.h	11800;"	d
+DBG_HWID8_WR_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33455;"	d
+DBG_HWID9_RD_EN_HI	include/ssv6200_aux.h	11884;"	d
+DBG_HWID9_RD_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33539;"	d
+DBG_HWID9_RD_EN_I_MSK	include/ssv6200_aux.h	11882;"	d
+DBG_HWID9_RD_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33537;"	d
+DBG_HWID9_RD_EN_MSK	include/ssv6200_aux.h	11881;"	d
+DBG_HWID9_RD_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33536;"	d
+DBG_HWID9_RD_EN_SFT	include/ssv6200_aux.h	11883;"	d
+DBG_HWID9_RD_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33538;"	d
+DBG_HWID9_RD_EN_SZ	include/ssv6200_aux.h	11885;"	d
+DBG_HWID9_RD_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33540;"	d
+DBG_HWID9_WR_EN_HI	include/ssv6200_aux.h	11804;"	d
+DBG_HWID9_WR_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33459;"	d
+DBG_HWID9_WR_EN_I_MSK	include/ssv6200_aux.h	11802;"	d
+DBG_HWID9_WR_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33457;"	d
+DBG_HWID9_WR_EN_MSK	include/ssv6200_aux.h	11801;"	d
+DBG_HWID9_WR_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33456;"	d
+DBG_HWID9_WR_EN_SFT	include/ssv6200_aux.h	11803;"	d
+DBG_HWID9_WR_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33458;"	d
+DBG_HWID9_WR_EN_SZ	include/ssv6200_aux.h	11805;"	d
+DBG_HWID9_WR_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33460;"	d
+DBG_JUDGE_CNT_CLR_HI	include/ssv6200_aux.h	5554;"	d
+DBG_JUDGE_CNT_CLR_I_MSK	include/ssv6200_aux.h	5552;"	d
+DBG_JUDGE_CNT_CLR_MSK	include/ssv6200_aux.h	5551;"	d
+DBG_JUDGE_CNT_CLR_SFT	include/ssv6200_aux.h	5553;"	d
+DBG_JUDGE_CNT_CLR_SZ	include/ssv6200_aux.h	5555;"	d
+DBG_JUDGE_CNT_HI	include/ssv6200_aux.h	5539;"	d
+DBG_JUDGE_CNT_I_MSK	include/ssv6200_aux.h	5537;"	d
+DBG_JUDGE_CNT_MSK	include/ssv6200_aux.h	5536;"	d
+DBG_JUDGE_CNT_SFT	include/ssv6200_aux.h	5538;"	d
+DBG_JUDGE_CNT_SZ	include/ssv6200_aux.h	5540;"	d
+DBG_LEN_ALC_FAIL_HI	include/ssv6200_aux.h	9699;"	d
+DBG_LEN_ALC_FAIL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9534;"	d
+DBG_LEN_ALC_FAIL_I_MSK	include/ssv6200_aux.h	9697;"	d
+DBG_LEN_ALC_FAIL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9532;"	d
+DBG_LEN_ALC_FAIL_MSK	include/ssv6200_aux.h	9696;"	d
+DBG_LEN_ALC_FAIL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9531;"	d
+DBG_LEN_ALC_FAIL_SFT	include/ssv6200_aux.h	9698;"	d
+DBG_LEN_ALC_FAIL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9533;"	d
+DBG_LEN_ALC_FAIL_SZ	include/ssv6200_aux.h	9700;"	d
+DBG_LEN_ALC_FAIL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9535;"	d
+DBG_LEN_CRC_FAIL_HI	include/ssv6200_aux.h	9694;"	d
+DBG_LEN_CRC_FAIL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9529;"	d
+DBG_LEN_CRC_FAIL_I_MSK	include/ssv6200_aux.h	9692;"	d
+DBG_LEN_CRC_FAIL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9527;"	d
+DBG_LEN_CRC_FAIL_MSK	include/ssv6200_aux.h	9691;"	d
+DBG_LEN_CRC_FAIL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9526;"	d
+DBG_LEN_CRC_FAIL_SFT	include/ssv6200_aux.h	9693;"	d
+DBG_LEN_CRC_FAIL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9528;"	d
+DBG_LEN_CRC_FAIL_SZ	include/ssv6200_aux.h	9695;"	d
+DBG_LEN_CRC_FAIL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9530;"	d
+DBG_MB_FULL_CLR_HI	include/ssv6200_aux.h	7154;"	d
+DBG_MB_FULL_CLR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6329;"	d
+DBG_MB_FULL_CLR_I_MSK	include/ssv6200_aux.h	7152;"	d
+DBG_MB_FULL_CLR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6327;"	d
+DBG_MB_FULL_CLR_MSK	include/ssv6200_aux.h	7151;"	d
+DBG_MB_FULL_CLR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6326;"	d
+DBG_MB_FULL_CLR_SFT	include/ssv6200_aux.h	7153;"	d
+DBG_MB_FULL_CLR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6328;"	d
+DBG_MB_FULL_CLR_SZ	include/ssv6200_aux.h	7155;"	d
+DBG_MB_FULL_CLR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6330;"	d
+DBG_MB_FULL_HI	include/ssv6200_aux.h	7149;"	d
+DBG_MB_FULL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6324;"	d
+DBG_MB_FULL_I_MSK	include/ssv6200_aux.h	7147;"	d
+DBG_MB_FULL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6322;"	d
+DBG_MB_FULL_MSK	include/ssv6200_aux.h	7146;"	d
+DBG_MB_FULL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6321;"	d
+DBG_MB_FULL_SFT	include/ssv6200_aux.h	7148;"	d
+DBG_MB_FULL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6323;"	d
+DBG_MB_FULL_SZ	include/ssv6200_aux.h	7150;"	d
+DBG_MB_FULL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6325;"	d
+DBG_MODE_HI	include/ssv6200_aux.h	7764;"	d
+DBG_MODE_I_MSK	include/ssv6200_aux.h	7762;"	d
+DBG_MODE_MSK	include/ssv6200_aux.h	7761;"	d
+DBG_MODE_SFT	include/ssv6200_aux.h	7763;"	d
+DBG_MODE_SZ	include/ssv6200_aux.h	7765;"	d
+DBG_MTX_IGNORE_NAV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7184;"	d
+DBG_MTX_IGNORE_NAV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7182;"	d
+DBG_MTX_IGNORE_NAV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7181;"	d
+DBG_MTX_IGNORE_NAV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7183;"	d
+DBG_MTX_IGNORE_NAV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7185;"	d
+DBG_PHYTXIP_TIMEOUT_RECOVERY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7179;"	d
+DBG_PHYTXIP_TIMEOUT_RECOVERY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7177;"	d
+DBG_PHYTXIP_TIMEOUT_RECOVERY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7176;"	d
+DBG_PHYTXIP_TIMEOUT_RECOVERY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7178;"	d
+DBG_PHYTXIP_TIMEOUT_RECOVERY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7180;"	d
+DBG_PHYTX_PROCEED_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6839;"	d
+DBG_PHYTX_PROCEED_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6837;"	d
+DBG_PHYTX_PROCEED_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6836;"	d
+DBG_PHYTX_PROCEED_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6838;"	d
+DBG_PHYTX_PROCEED_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6840;"	d
+DBG_PRTC_PRD_HI	include/ssv6200_aux.h	7739;"	d
+DBG_PRTC_PRD_I_MSK	include/ssv6200_aux.h	7737;"	d
+DBG_PRTC_PRD_MSK	include/ssv6200_aux.h	7736;"	d
+DBG_PRTC_PRD_SFT	include/ssv6200_aux.h	7738;"	d
+DBG_PRTC_PRD_SZ	include/ssv6200_aux.h	7740;"	d
+DBG_Q0_ACK_FAIL_HI	include/ssv6200_aux.h	9604;"	d
+DBG_Q0_ACK_FAIL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9439;"	d
+DBG_Q0_ACK_FAIL_I_MSK	include/ssv6200_aux.h	9602;"	d
+DBG_Q0_ACK_FAIL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9437;"	d
+DBG_Q0_ACK_FAIL_MSK	include/ssv6200_aux.h	9601;"	d
+DBG_Q0_ACK_FAIL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9436;"	d
+DBG_Q0_ACK_FAIL_SFT	include/ssv6200_aux.h	9603;"	d
+DBG_Q0_ACK_FAIL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9438;"	d
+DBG_Q0_ACK_FAIL_SZ	include/ssv6200_aux.h	9605;"	d
+DBG_Q0_ACK_FAIL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9440;"	d
+DBG_Q0_ACK_SUCC_HI	include/ssv6200_aux.h	9599;"	d
+DBG_Q0_ACK_SUCC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9434;"	d
+DBG_Q0_ACK_SUCC_I_MSK	include/ssv6200_aux.h	9597;"	d
+DBG_Q0_ACK_SUCC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9432;"	d
+DBG_Q0_ACK_SUCC_MSK	include/ssv6200_aux.h	9596;"	d
+DBG_Q0_ACK_SUCC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9431;"	d
+DBG_Q0_ACK_SUCC_SFT	include/ssv6200_aux.h	9598;"	d
+DBG_Q0_ACK_SUCC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9433;"	d
+DBG_Q0_ACK_SUCC_SZ	include/ssv6200_aux.h	9600;"	d
+DBG_Q0_ACK_SUCC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9435;"	d
+DBG_Q0_FAIL_HI	include/ssv6200_aux.h	9594;"	d
+DBG_Q0_FAIL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9429;"	d
+DBG_Q0_FAIL_I_MSK	include/ssv6200_aux.h	9592;"	d
+DBG_Q0_FAIL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9427;"	d
+DBG_Q0_FAIL_MSK	include/ssv6200_aux.h	9591;"	d
+DBG_Q0_FAIL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9426;"	d
+DBG_Q0_FAIL_SFT	include/ssv6200_aux.h	9593;"	d
+DBG_Q0_FAIL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9428;"	d
+DBG_Q0_FAIL_SZ	include/ssv6200_aux.h	9595;"	d
+DBG_Q0_FAIL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9430;"	d
+DBG_Q0_SUCC_HI	include/ssv6200_aux.h	9589;"	d
+DBG_Q0_SUCC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9424;"	d
+DBG_Q0_SUCC_I_MSK	include/ssv6200_aux.h	9587;"	d
+DBG_Q0_SUCC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9422;"	d
+DBG_Q0_SUCC_MSK	include/ssv6200_aux.h	9586;"	d
+DBG_Q0_SUCC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9421;"	d
+DBG_Q0_SUCC_SFT	include/ssv6200_aux.h	9588;"	d
+DBG_Q0_SUCC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9423;"	d
+DBG_Q0_SUCC_SZ	include/ssv6200_aux.h	9590;"	d
+DBG_Q0_SUCC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9425;"	d
+DBG_Q1_ACK_FAIL_HI	include/ssv6200_aux.h	9624;"	d
+DBG_Q1_ACK_FAIL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9459;"	d
+DBG_Q1_ACK_FAIL_I_MSK	include/ssv6200_aux.h	9622;"	d
+DBG_Q1_ACK_FAIL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9457;"	d
+DBG_Q1_ACK_FAIL_MSK	include/ssv6200_aux.h	9621;"	d
+DBG_Q1_ACK_FAIL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9456;"	d
+DBG_Q1_ACK_FAIL_SFT	include/ssv6200_aux.h	9623;"	d
+DBG_Q1_ACK_FAIL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9458;"	d
+DBG_Q1_ACK_FAIL_SZ	include/ssv6200_aux.h	9625;"	d
+DBG_Q1_ACK_FAIL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9460;"	d
+DBG_Q1_ACK_SUCC_HI	include/ssv6200_aux.h	9619;"	d
+DBG_Q1_ACK_SUCC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9454;"	d
+DBG_Q1_ACK_SUCC_I_MSK	include/ssv6200_aux.h	9617;"	d
+DBG_Q1_ACK_SUCC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9452;"	d
+DBG_Q1_ACK_SUCC_MSK	include/ssv6200_aux.h	9616;"	d
+DBG_Q1_ACK_SUCC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9451;"	d
+DBG_Q1_ACK_SUCC_SFT	include/ssv6200_aux.h	9618;"	d
+DBG_Q1_ACK_SUCC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9453;"	d
+DBG_Q1_ACK_SUCC_SZ	include/ssv6200_aux.h	9620;"	d
+DBG_Q1_ACK_SUCC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9455;"	d
+DBG_Q1_FAIL_HI	include/ssv6200_aux.h	9614;"	d
+DBG_Q1_FAIL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9449;"	d
+DBG_Q1_FAIL_I_MSK	include/ssv6200_aux.h	9612;"	d
+DBG_Q1_FAIL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9447;"	d
+DBG_Q1_FAIL_MSK	include/ssv6200_aux.h	9611;"	d
+DBG_Q1_FAIL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9446;"	d
+DBG_Q1_FAIL_SFT	include/ssv6200_aux.h	9613;"	d
+DBG_Q1_FAIL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9448;"	d
+DBG_Q1_FAIL_SZ	include/ssv6200_aux.h	9615;"	d
+DBG_Q1_FAIL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9450;"	d
+DBG_Q1_SUCC_HI	include/ssv6200_aux.h	9609;"	d
+DBG_Q1_SUCC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9444;"	d
+DBG_Q1_SUCC_I_MSK	include/ssv6200_aux.h	9607;"	d
+DBG_Q1_SUCC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9442;"	d
+DBG_Q1_SUCC_MSK	include/ssv6200_aux.h	9606;"	d
+DBG_Q1_SUCC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9441;"	d
+DBG_Q1_SUCC_SFT	include/ssv6200_aux.h	9608;"	d
+DBG_Q1_SUCC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9443;"	d
+DBG_Q1_SUCC_SZ	include/ssv6200_aux.h	9610;"	d
+DBG_Q1_SUCC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9445;"	d
+DBG_Q2_ACK_FAIL_HI	include/ssv6200_aux.h	9644;"	d
+DBG_Q2_ACK_FAIL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9479;"	d
+DBG_Q2_ACK_FAIL_I_MSK	include/ssv6200_aux.h	9642;"	d
+DBG_Q2_ACK_FAIL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9477;"	d
+DBG_Q2_ACK_FAIL_MSK	include/ssv6200_aux.h	9641;"	d
+DBG_Q2_ACK_FAIL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9476;"	d
+DBG_Q2_ACK_FAIL_SFT	include/ssv6200_aux.h	9643;"	d
+DBG_Q2_ACK_FAIL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9478;"	d
+DBG_Q2_ACK_FAIL_SZ	include/ssv6200_aux.h	9645;"	d
+DBG_Q2_ACK_FAIL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9480;"	d
+DBG_Q2_ACK_SUCC_HI	include/ssv6200_aux.h	9639;"	d
+DBG_Q2_ACK_SUCC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9474;"	d
+DBG_Q2_ACK_SUCC_I_MSK	include/ssv6200_aux.h	9637;"	d
+DBG_Q2_ACK_SUCC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9472;"	d
+DBG_Q2_ACK_SUCC_MSK	include/ssv6200_aux.h	9636;"	d
+DBG_Q2_ACK_SUCC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9471;"	d
+DBG_Q2_ACK_SUCC_SFT	include/ssv6200_aux.h	9638;"	d
+DBG_Q2_ACK_SUCC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9473;"	d
+DBG_Q2_ACK_SUCC_SZ	include/ssv6200_aux.h	9640;"	d
+DBG_Q2_ACK_SUCC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9475;"	d
+DBG_Q2_FAIL_HI	include/ssv6200_aux.h	9634;"	d
+DBG_Q2_FAIL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9469;"	d
+DBG_Q2_FAIL_I_MSK	include/ssv6200_aux.h	9632;"	d
+DBG_Q2_FAIL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9467;"	d
+DBG_Q2_FAIL_MSK	include/ssv6200_aux.h	9631;"	d
+DBG_Q2_FAIL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9466;"	d
+DBG_Q2_FAIL_SFT	include/ssv6200_aux.h	9633;"	d
+DBG_Q2_FAIL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9468;"	d
+DBG_Q2_FAIL_SZ	include/ssv6200_aux.h	9635;"	d
+DBG_Q2_FAIL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9470;"	d
+DBG_Q2_SUCC_HI	include/ssv6200_aux.h	9629;"	d
+DBG_Q2_SUCC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9464;"	d
+DBG_Q2_SUCC_I_MSK	include/ssv6200_aux.h	9627;"	d
+DBG_Q2_SUCC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9462;"	d
+DBG_Q2_SUCC_MSK	include/ssv6200_aux.h	9626;"	d
+DBG_Q2_SUCC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9461;"	d
+DBG_Q2_SUCC_SFT	include/ssv6200_aux.h	9628;"	d
+DBG_Q2_SUCC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9463;"	d
+DBG_Q2_SUCC_SZ	include/ssv6200_aux.h	9630;"	d
+DBG_Q2_SUCC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9465;"	d
+DBG_Q3_ACK_FAIL_HI	include/ssv6200_aux.h	9664;"	d
+DBG_Q3_ACK_FAIL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9499;"	d
+DBG_Q3_ACK_FAIL_I_MSK	include/ssv6200_aux.h	9662;"	d
+DBG_Q3_ACK_FAIL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9497;"	d
+DBG_Q3_ACK_FAIL_MSK	include/ssv6200_aux.h	9661;"	d
+DBG_Q3_ACK_FAIL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9496;"	d
+DBG_Q3_ACK_FAIL_SFT	include/ssv6200_aux.h	9663;"	d
+DBG_Q3_ACK_FAIL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9498;"	d
+DBG_Q3_ACK_FAIL_SZ	include/ssv6200_aux.h	9665;"	d
+DBG_Q3_ACK_FAIL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9500;"	d
+DBG_Q3_ACK_SUCC_HI	include/ssv6200_aux.h	9659;"	d
+DBG_Q3_ACK_SUCC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9494;"	d
+DBG_Q3_ACK_SUCC_I_MSK	include/ssv6200_aux.h	9657;"	d
+DBG_Q3_ACK_SUCC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9492;"	d
+DBG_Q3_ACK_SUCC_MSK	include/ssv6200_aux.h	9656;"	d
+DBG_Q3_ACK_SUCC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9491;"	d
+DBG_Q3_ACK_SUCC_SFT	include/ssv6200_aux.h	9658;"	d
+DBG_Q3_ACK_SUCC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9493;"	d
+DBG_Q3_ACK_SUCC_SZ	include/ssv6200_aux.h	9660;"	d
+DBG_Q3_ACK_SUCC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9495;"	d
+DBG_Q3_FAIL_HI	include/ssv6200_aux.h	9654;"	d
+DBG_Q3_FAIL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9489;"	d
+DBG_Q3_FAIL_I_MSK	include/ssv6200_aux.h	9652;"	d
+DBG_Q3_FAIL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9487;"	d
+DBG_Q3_FAIL_MSK	include/ssv6200_aux.h	9651;"	d
+DBG_Q3_FAIL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9486;"	d
+DBG_Q3_FAIL_SFT	include/ssv6200_aux.h	9653;"	d
+DBG_Q3_FAIL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9488;"	d
+DBG_Q3_FAIL_SZ	include/ssv6200_aux.h	9655;"	d
+DBG_Q3_FAIL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9490;"	d
+DBG_Q3_SUCC_HI	include/ssv6200_aux.h	9649;"	d
+DBG_Q3_SUCC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9484;"	d
+DBG_Q3_SUCC_I_MSK	include/ssv6200_aux.h	9647;"	d
+DBG_Q3_SUCC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9482;"	d
+DBG_Q3_SUCC_MSK	include/ssv6200_aux.h	9646;"	d
+DBG_Q3_SUCC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9481;"	d
+DBG_Q3_SUCC_SFT	include/ssv6200_aux.h	9648;"	d
+DBG_Q3_SUCC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9483;"	d
+DBG_Q3_SUCC_SZ	include/ssv6200_aux.h	9650;"	d
+DBG_Q3_SUCC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9485;"	d
+DBG_RDATA_RDY_HI	include/ssv6200_aux.h	5494;"	d
+DBG_RDATA_RDY_I_MSK	include/ssv6200_aux.h	5492;"	d
+DBG_RDATA_RDY_MSK	include/ssv6200_aux.h	5491;"	d
+DBG_RDATA_RDY_SFT	include/ssv6200_aux.h	5493;"	d
+DBG_RDATA_RDY_SZ	include/ssv6200_aux.h	5495;"	d
+DBG_RD_DAT_CNT_CLR_HI	include/ssv6200_aux.h	5549;"	d
+DBG_RD_DAT_CNT_CLR_I_MSK	include/ssv6200_aux.h	5547;"	d
+DBG_RD_DAT_CNT_CLR_MSK	include/ssv6200_aux.h	5546;"	d
+DBG_RD_DAT_CNT_CLR_SFT	include/ssv6200_aux.h	5548;"	d
+DBG_RD_DAT_CNT_CLR_SZ	include/ssv6200_aux.h	5550;"	d
+DBG_RD_DAT_CNT_HI	include/ssv6200_aux.h	5529;"	d
+DBG_RD_DAT_CNT_I_MSK	include/ssv6200_aux.h	5527;"	d
+DBG_RD_DAT_CNT_MSK	include/ssv6200_aux.h	5526;"	d
+DBG_RD_DAT_CNT_SFT	include/ssv6200_aux.h	5528;"	d
+DBG_RD_DAT_CNT_SZ	include/ssv6200_aux.h	5530;"	d
+DBG_RD_STS_CNT_CLR_HI	include/ssv6200_aux.h	5544;"	d
+DBG_RD_STS_CNT_CLR_I_MSK	include/ssv6200_aux.h	5542;"	d
+DBG_RD_STS_CNT_CLR_MSK	include/ssv6200_aux.h	5541;"	d
+DBG_RD_STS_CNT_CLR_SFT	include/ssv6200_aux.h	5543;"	d
+DBG_RD_STS_CNT_CLR_SZ	include/ssv6200_aux.h	5545;"	d
+DBG_RD_STS_CNT_HI	include/ssv6200_aux.h	5534;"	d
+DBG_RD_STS_CNT_I_MSK	include/ssv6200_aux.h	5532;"	d
+DBG_RD_STS_CNT_MSK	include/ssv6200_aux.h	5531;"	d
+DBG_RD_STS_CNT_SFT	include/ssv6200_aux.h	5533;"	d
+DBG_RD_STS_CNT_SZ	include/ssv6200_aux.h	5535;"	d
+DBG_RST_HI	include/ssv6200_aux.h	7759;"	d
+DBG_RST_I_MSK	include/ssv6200_aux.h	7757;"	d
+DBG_RST_MSK	include/ssv6200_aux.h	7756;"	d
+DBG_RST_SFT	include/ssv6200_aux.h	7758;"	d
+DBG_RST_SZ	include/ssv6200_aux.h	7760;"	d
+DBG_RX_FIFO_FAIL_HI	include/ssv6200_aux.h	5464;"	d
+DBG_RX_FIFO_FAIL_I_MSK	include/ssv6200_aux.h	5462;"	d
+DBG_RX_FIFO_FAIL_MSK	include/ssv6200_aux.h	5461;"	d
+DBG_RX_FIFO_FAIL_SFT	include/ssv6200_aux.h	5463;"	d
+DBG_RX_FIFO_FAIL_SZ	include/ssv6200_aux.h	5465;"	d
+DBG_RX_FIFO_RESIDUE_HI	include/ssv6200_aux.h	5599;"	d
+DBG_RX_FIFO_RESIDUE_I_MSK	include/ssv6200_aux.h	5597;"	d
+DBG_RX_FIFO_RESIDUE_MSK	include/ssv6200_aux.h	5596;"	d
+DBG_RX_FIFO_RESIDUE_SFT	include/ssv6200_aux.h	5598;"	d
+DBG_RX_FIFO_RESIDUE_SZ	include/ssv6200_aux.h	5600;"	d
+DBG_RX_HOST_FAIL_HI	include/ssv6200_aux.h	5469;"	d
+DBG_RX_HOST_FAIL_I_MSK	include/ssv6200_aux.h	5467;"	d
+DBG_RX_HOST_FAIL_MSK	include/ssv6200_aux.h	5466;"	d
+DBG_RX_HOST_FAIL_SFT	include/ssv6200_aux.h	5468;"	d
+DBG_RX_HOST_FAIL_SZ	include/ssv6200_aux.h	5470;"	d
+DBG_RX_LEN_HI	include/ssv6200_aux.h	5509;"	d
+DBG_RX_LEN_I_MSK	include/ssv6200_aux.h	5507;"	d
+DBG_RX_LEN_MSK	include/ssv6200_aux.h	5506;"	d
+DBG_RX_LEN_SFT	include/ssv6200_aux.h	5508;"	d
+DBG_RX_LEN_SZ	include/ssv6200_aux.h	5510;"	d
+DBG_RX_QUOTA_HI	include/ssv6200_aux.h	5419;"	d
+DBG_RX_QUOTA_I_MSK	include/ssv6200_aux.h	5417;"	d
+DBG_RX_QUOTA_MSK	include/ssv6200_aux.h	5416;"	d
+DBG_RX_QUOTA_SFT	include/ssv6200_aux.h	5418;"	d
+DBG_RX_QUOTA_SZ	include/ssv6200_aux.h	5420;"	d
+DBG_RX_RDY_HI	include/ssv6200_aux.h	5604;"	d
+DBG_RX_RDY_I_MSK	include/ssv6200_aux.h	5602;"	d
+DBG_RX_RDY_MSK	include/ssv6200_aux.h	5601;"	d
+DBG_RX_RDY_SFT	include/ssv6200_aux.h	5603;"	d
+DBG_RX_RDY_SZ	include/ssv6200_aux.h	5605;"	d
+DBG_SDIO_SYS_INT_HI	include/ssv6200_aux.h	5609;"	d
+DBG_SDIO_SYS_INT_I_MSK	include/ssv6200_aux.h	5607;"	d
+DBG_SDIO_SYS_INT_MSK	include/ssv6200_aux.h	5606;"	d
+DBG_SDIO_SYS_INT_SFT	include/ssv6200_aux.h	5608;"	d
+DBG_SDIO_SYS_INT_SZ	include/ssv6200_aux.h	5610;"	d
+DBG_SPI_ALLOC_STATUS_HI	include/ssv6200_aux.h	5499;"	d
+DBG_SPI_ALLOC_STATUS_I_MSK	include/ssv6200_aux.h	5497;"	d
+DBG_SPI_ALLOC_STATUS_MSK	include/ssv6200_aux.h	5496;"	d
+DBG_SPI_ALLOC_STATUS_SFT	include/ssv6200_aux.h	5498;"	d
+DBG_SPI_ALLOC_STATUS_SZ	include/ssv6200_aux.h	5500;"	d
+DBG_SPI_CLK_EN_INT_HI	include/ssv6200_aux.h	5644;"	d
+DBG_SPI_CLK_EN_INT_I_MSK	include/ssv6200_aux.h	5642;"	d
+DBG_SPI_CLK_EN_INT_MSK	include/ssv6200_aux.h	5641;"	d
+DBG_SPI_CLK_EN_INT_SFT	include/ssv6200_aux.h	5643;"	d
+DBG_SPI_CLK_EN_INT_SZ	include/ssv6200_aux.h	5645;"	d
+DBG_SPI_DBG_WR_FIFO_FULL_HI	include/ssv6200_aux.h	5504;"	d
+DBG_SPI_DBG_WR_FIFO_FULL_I_MSK	include/ssv6200_aux.h	5502;"	d
+DBG_SPI_DBG_WR_FIFO_FULL_MSK	include/ssv6200_aux.h	5501;"	d
+DBG_SPI_DBG_WR_FIFO_FULL_SFT	include/ssv6200_aux.h	5503;"	d
+DBG_SPI_DBG_WR_FIFO_FULL_SZ	include/ssv6200_aux.h	5505;"	d
+DBG_SPI_DOUBLE_ALLOC_HI	include/ssv6200_aux.h	5484;"	d
+DBG_SPI_DOUBLE_ALLOC_I_MSK	include/ssv6200_aux.h	5482;"	d
+DBG_SPI_DOUBLE_ALLOC_MSK	include/ssv6200_aux.h	5481;"	d
+DBG_SPI_DOUBLE_ALLOC_SFT	include/ssv6200_aux.h	5483;"	d
+DBG_SPI_DOUBLE_ALLOC_SZ	include/ssv6200_aux.h	5485;"	d
+DBG_SPI_FN1_HI	include/ssv6200_aux.h	5639;"	d
+DBG_SPI_FN1_I_MSK	include/ssv6200_aux.h	5637;"	d
+DBG_SPI_FN1_MSK	include/ssv6200_aux.h	5636;"	d
+DBG_SPI_FN1_SFT	include/ssv6200_aux.h	5638;"	d
+DBG_SPI_FN1_SZ	include/ssv6200_aux.h	5640;"	d
+DBG_SPI_HOST_MASK_HI	include/ssv6200_aux.h	5649;"	d
+DBG_SPI_HOST_MASK_I_MSK	include/ssv6200_aux.h	5647;"	d
+DBG_SPI_HOST_MASK_MSK	include/ssv6200_aux.h	5646;"	d
+DBG_SPI_HOST_MASK_SFT	include/ssv6200_aux.h	5648;"	d
+DBG_SPI_HOST_MASK_SZ	include/ssv6200_aux.h	5650;"	d
+DBG_SPI_HOST_TX_ALLOC_PKBUF_HI	include/ssv6200_aux.h	5519;"	d
+DBG_SPI_HOST_TX_ALLOC_PKBUF_I_MSK	include/ssv6200_aux.h	5517;"	d
+DBG_SPI_HOST_TX_ALLOC_PKBUF_MSK	include/ssv6200_aux.h	5516;"	d
+DBG_SPI_HOST_TX_ALLOC_PKBUF_SFT	include/ssv6200_aux.h	5518;"	d
+DBG_SPI_HOST_TX_ALLOC_PKBUF_SZ	include/ssv6200_aux.h	5520;"	d
+DBG_SPI_MODE_HI	include/ssv6200_aux.h	5414;"	d
+DBG_SPI_MODE_I_MSK	include/ssv6200_aux.h	5412;"	d
+DBG_SPI_MODE_MSK	include/ssv6200_aux.h	5411;"	d
+DBG_SPI_MODE_SFT	include/ssv6200_aux.h	5413;"	d
+DBG_SPI_MODE_SZ	include/ssv6200_aux.h	5415;"	d
+DBG_SPI_REG_BANK_SIZE	include/ssv6200_reg.h	84;"	d
+DBG_SPI_REG_BASE	include/ssv6200_reg.h	35;"	d
+DBG_SPI_TX_ALLOC_SIZE_HI	include/ssv6200_aux.h	5524;"	d
+DBG_SPI_TX_ALLOC_SIZE_I_MSK	include/ssv6200_aux.h	5522;"	d
+DBG_SPI_TX_ALLOC_SIZE_MSK	include/ssv6200_aux.h	5521;"	d
+DBG_SPI_TX_ALLOC_SIZE_SFT	include/ssv6200_aux.h	5523;"	d
+DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_HI	include/ssv6200_aux.h	5514;"	d
+DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_I_MSK	include/ssv6200_aux.h	5512;"	d
+DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_MSK	include/ssv6200_aux.h	5511;"	d
+DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_SFT	include/ssv6200_aux.h	5513;"	d
+DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_SZ	include/ssv6200_aux.h	5515;"	d
+DBG_SPI_TX_ALLOC_SIZE_SZ	include/ssv6200_aux.h	5525;"	d
+DBG_SPI_TX_NO_ALLOC_HI	include/ssv6200_aux.h	5489;"	d
+DBG_SPI_TX_NO_ALLOC_I_MSK	include/ssv6200_aux.h	5487;"	d
+DBG_SPI_TX_NO_ALLOC_MSK	include/ssv6200_aux.h	5486;"	d
+DBG_SPI_TX_NO_ALLOC_SFT	include/ssv6200_aux.h	5488;"	d
+DBG_SPI_TX_NO_ALLOC_SZ	include/ssv6200_aux.h	5490;"	d
+DBG_TX_DISCARD_CNT_CLR_HI	include/ssv6200_aux.h	5574;"	d
+DBG_TX_DISCARD_CNT_CLR_I_MSK	include/ssv6200_aux.h	5572;"	d
+DBG_TX_DISCARD_CNT_CLR_MSK	include/ssv6200_aux.h	5571;"	d
+DBG_TX_DISCARD_CNT_CLR_SFT	include/ssv6200_aux.h	5573;"	d
+DBG_TX_DISCARD_CNT_CLR_SZ	include/ssv6200_aux.h	5575;"	d
+DBG_TX_DISCARD_CNT_HI	include/ssv6200_aux.h	5564;"	d
+DBG_TX_DISCARD_CNT_I_MSK	include/ssv6200_aux.h	5562;"	d
+DBG_TX_DISCARD_CNT_MSK	include/ssv6200_aux.h	5561;"	d
+DBG_TX_DISCARD_CNT_SFT	include/ssv6200_aux.h	5563;"	d
+DBG_TX_DISCARD_CNT_SZ	include/ssv6200_aux.h	5565;"	d
+DBG_TX_DONE_CNT_CLR_HI	include/ssv6200_aux.h	5579;"	d
+DBG_TX_DONE_CNT_CLR_I_MSK	include/ssv6200_aux.h	5577;"	d
+DBG_TX_DONE_CNT_CLR_MSK	include/ssv6200_aux.h	5576;"	d
+DBG_TX_DONE_CNT_CLR_SFT	include/ssv6200_aux.h	5578;"	d
+DBG_TX_DONE_CNT_CLR_SZ	include/ssv6200_aux.h	5580;"	d
+DBG_TX_DONE_CNT_HI	include/ssv6200_aux.h	5559;"	d
+DBG_TX_DONE_CNT_I_MSK	include/ssv6200_aux.h	5557;"	d
+DBG_TX_DONE_CNT_MSK	include/ssv6200_aux.h	5556;"	d
+DBG_TX_DONE_CNT_SFT	include/ssv6200_aux.h	5558;"	d
+DBG_TX_DONE_CNT_SZ	include/ssv6200_aux.h	5560;"	d
+DBG_TX_FIFO_FAIL_HI	include/ssv6200_aux.h	5474;"	d
+DBG_TX_FIFO_FAIL_I_MSK	include/ssv6200_aux.h	5472;"	d
+DBG_TX_FIFO_FAIL_MSK	include/ssv6200_aux.h	5471;"	d
+DBG_TX_FIFO_FAIL_SFT	include/ssv6200_aux.h	5473;"	d
+DBG_TX_FIFO_FAIL_SZ	include/ssv6200_aux.h	5475;"	d
+DBG_TX_FIFO_RESIDUE_HI	include/ssv6200_aux.h	5594;"	d
+DBG_TX_FIFO_RESIDUE_I_MSK	include/ssv6200_aux.h	5592;"	d
+DBG_TX_FIFO_RESIDUE_MSK	include/ssv6200_aux.h	5591;"	d
+DBG_TX_FIFO_RESIDUE_SFT	include/ssv6200_aux.h	5593;"	d
+DBG_TX_FIFO_RESIDUE_SZ	include/ssv6200_aux.h	5595;"	d
+DBG_TX_HOST_FAIL_HI	include/ssv6200_aux.h	5479;"	d
+DBG_TX_HOST_FAIL_I_MSK	include/ssv6200_aux.h	5477;"	d
+DBG_TX_HOST_FAIL_MSK	include/ssv6200_aux.h	5476;"	d
+DBG_TX_HOST_FAIL_SFT	include/ssv6200_aux.h	5478;"	d
+DBG_TX_HOST_FAIL_SZ	include/ssv6200_aux.h	5480;"	d
+DBG_TX_LIMIT_INT_IN_HI	include/ssv6200_aux.h	5634;"	d
+DBG_TX_LIMIT_INT_IN_I_MSK	include/ssv6200_aux.h	5632;"	d
+DBG_TX_LIMIT_INT_IN_MSK	include/ssv6200_aux.h	5631;"	d
+DBG_TX_LIMIT_INT_IN_SFT	include/ssv6200_aux.h	5633;"	d
+DBG_TX_LIMIT_INT_IN_SZ	include/ssv6200_aux.h	5635;"	d
+DBG_TX_SEG_HI	include/ssv6200_aux.h	5434;"	d
+DBG_TX_SEG_I_MSK	include/ssv6200_aux.h	5432;"	d
+DBG_TX_SEG_MSK	include/ssv6200_aux.h	5431;"	d
+DBG_TX_SEG_SFT	include/ssv6200_aux.h	5433;"	d
+DBG_TX_SEG_SZ	include/ssv6200_aux.h	5435;"	d
+DBG_TX_SET_CNT_CLR_HI	include/ssv6200_aux.h	5584;"	d
+DBG_TX_SET_CNT_CLR_I_MSK	include/ssv6200_aux.h	5582;"	d
+DBG_TX_SET_CNT_CLR_MSK	include/ssv6200_aux.h	5581;"	d
+DBG_TX_SET_CNT_CLR_SFT	include/ssv6200_aux.h	5583;"	d
+DBG_TX_SET_CNT_CLR_SZ	include/ssv6200_aux.h	5585;"	d
+DBG_TX_SET_CNT_HI	include/ssv6200_aux.h	5569;"	d
+DBG_TX_SET_CNT_I_MSK	include/ssv6200_aux.h	5567;"	d
+DBG_TX_SET_CNT_MSK	include/ssv6200_aux.h	5566;"	d
+DBG_TX_SET_CNT_SFT	include/ssv6200_aux.h	5568;"	d
+DBG_TX_SET_CNT_SZ	include/ssv6200_aux.h	5570;"	d
+DBG_TYPE_HI	include/ssv6200_aux.h	11719;"	d
+DBG_TYPE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33374;"	d
+DBG_TYPE_I_MSK	include/ssv6200_aux.h	11717;"	d
+DBG_TYPE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33372;"	d
+DBG_TYPE_MSK	include/ssv6200_aux.h	11716;"	d
+DBG_TYPE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33371;"	d
+DBG_TYPE_SFT	include/ssv6200_aux.h	11718;"	d
+DBG_TYPE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33373;"	d
+DBG_TYPE_SZ	include/ssv6200_aux.h	11720;"	d
+DBG_TYPE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33375;"	d
+DBG_WAIT_RSP_HI	include/ssv6200_aux.h	7749;"	d
+DBG_WAIT_RSP_I_MSK	include/ssv6200_aux.h	7747;"	d
+DBG_WAIT_RSP_MSK	include/ssv6200_aux.h	7746;"	d
+DBG_WAIT_RSP_SFT	include/ssv6200_aux.h	7748;"	d
+DBG_WAIT_RSP_SZ	include/ssv6200_aux.h	7750;"	d
+DBG_WFF_FULL_CLR_HI	include/ssv6200_aux.h	7144;"	d
+DBG_WFF_FULL_CLR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6319;"	d
+DBG_WFF_FULL_CLR_I_MSK	include/ssv6200_aux.h	7142;"	d
+DBG_WFF_FULL_CLR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6317;"	d
+DBG_WFF_FULL_CLR_MSK	include/ssv6200_aux.h	7141;"	d
+DBG_WFF_FULL_CLR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6316;"	d
+DBG_WFF_FULL_CLR_SFT	include/ssv6200_aux.h	7143;"	d
+DBG_WFF_FULL_CLR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6318;"	d
+DBG_WFF_FULL_CLR_SZ	include/ssv6200_aux.h	7145;"	d
+DBG_WFF_FULL_CLR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6320;"	d
+DBG_WFF_FULL_HI	include/ssv6200_aux.h	7139;"	d
+DBG_WFF_FULL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6314;"	d
+DBG_WFF_FULL_I_MSK	include/ssv6200_aux.h	7137;"	d
+DBG_WFF_FULL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6312;"	d
+DBG_WFF_FULL_MSK	include/ssv6200_aux.h	7136;"	d
+DBG_WFF_FULL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6311;"	d
+DBG_WFF_FULL_SFT	include/ssv6200_aux.h	7138;"	d
+DBG_WFF_FULL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6313;"	d
+DBG_WFF_FULL_SZ	include/ssv6200_aux.h	7140;"	d
+DBG_WFF_FULL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6315;"	d
+DBG_WRITE_TO_FINISH_SIM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1654;"	d
+DBG_WRITE_TO_FINISH_SIM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1652;"	d
+DBG_WRITE_TO_FINISH_SIM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1651;"	d
+DBG_WRITE_TO_FINISH_SIM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1653;"	d
+DBG_WRITE_TO_FINISH_SIM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1655;"	d
+DBIST_MODE_HI	include/ssv6200_aux.h	394;"	d
+DBIST_MODE_I_MSK	include/ssv6200_aux.h	392;"	d
+DBIST_MODE_MSK	include/ssv6200_aux.h	391;"	d
+DBIST_MODE_SFT	include/ssv6200_aux.h	393;"	d
+DBIST_MODE_SZ	include/ssv6200_aux.h	395;"	d
+DB_AD_ADC_I_OUT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24804;"	d
+DB_AD_ADC_I_OUT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24802;"	d
+DB_AD_ADC_I_OUT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24801;"	d
+DB_AD_ADC_I_OUT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24803;"	d
+DB_AD_ADC_I_OUT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24805;"	d
+DB_AD_ADC_Q_OUT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24809;"	d
+DB_AD_ADC_Q_OUT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24807;"	d
+DB_AD_ADC_Q_OUT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24806;"	d
+DB_AD_ADC_Q_OUT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24808;"	d
+DB_AD_ADC_Q_OUT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24810;"	d
+DB_AD_DP_VT_MON_Q_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24849;"	d
+DB_AD_DP_VT_MON_Q_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24847;"	d
+DB_AD_DP_VT_MON_Q_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24846;"	d
+DB_AD_DP_VT_MON_Q_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24848;"	d
+DB_AD_DP_VT_MON_Q_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24850;"	d
+DB_AD_IOT_ADC_OUT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24854;"	d
+DB_AD_IOT_ADC_OUT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24852;"	d
+DB_AD_IOT_ADC_OUT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24851;"	d
+DB_AD_IOT_ADC_OUT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24853;"	d
+DB_AD_IOT_ADC_OUT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24855;"	d
+DB_AD_RX_RSSIADC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24814;"	d
+DB_AD_RX_RSSIADC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24812;"	d
+DB_AD_RX_RSSIADC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24811;"	d
+DB_AD_RX_RSSIADC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24813;"	d
+DB_AD_RX_RSSIADC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24815;"	d
+DB_AD_SX5GB_AAC_COMPOUT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26909;"	d
+DB_AD_SX5GB_AAC_COMPOUT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26907;"	d
+DB_AD_SX5GB_AAC_COMPOUT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26906;"	d
+DB_AD_SX5GB_AAC_COMPOUT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26908;"	d
+DB_AD_SX5GB_AAC_COMPOUT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26910;"	d
+DB_DA_SARADC_BIT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24819;"	d
+DB_DA_SARADC_BIT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24817;"	d
+DB_DA_SARADC_BIT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24816;"	d
+DB_DA_SARADC_BIT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24818;"	d
+DB_DA_SARADC_BIT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24820;"	d
+DB_DA_SX5GB_SUB_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26879;"	d
+DB_DA_SX5GB_SUB_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26877;"	d
+DB_DA_SX5GB_SUB_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26876;"	d
+DB_DA_SX5GB_SUB_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26878;"	d
+DB_DA_SX5GB_SUB_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26880;"	d
+DB_DA_SX5GB_VCO_ISEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26884;"	d
+DB_DA_SX5GB_VCO_ISEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26882;"	d
+DB_DA_SX5GB_VCO_ISEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26881;"	d
+DB_DA_SX5GB_VCO_ISEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26883;"	d
+DB_DA_SX5GB_VCO_ISEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26885;"	d
+DB_DA_SXMIX_GMSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26894;"	d
+DB_DA_SXMIX_GMSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26892;"	d
+DB_DA_SXMIX_GMSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26891;"	d
+DB_DA_SXMIX_GMSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26893;"	d
+DB_DA_SXMIX_GMSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26895;"	d
+DB_DA_SXMIX_SCA_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26889;"	d
+DB_DA_SXMIX_SCA_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26887;"	d
+DB_DA_SXMIX_SCA_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26886;"	d
+DB_DA_SXMIX_SCA_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26888;"	d
+DB_DA_SXMIX_SCA_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26890;"	d
+DB_DA_SXREP_CSSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26904;"	d
+DB_DA_SXREP_CSSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26902;"	d
+DB_DA_SXREP_CSSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26901;"	d
+DB_DA_SXREP_CSSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26903;"	d
+DB_DA_SXREP_CSSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26905;"	d
+DB_DA_SXREP_SCA_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26899;"	d
+DB_DA_SXREP_SCA_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26897;"	d
+DB_DA_SXREP_SCA_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26896;"	d
+DB_DA_SXREP_SCA_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26898;"	d
+DB_DA_SXREP_SCA_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26900;"	d
+DB_DA_SX_SUB_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24829;"	d
+DB_DA_SX_SUB_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24827;"	d
+DB_DA_SX_SUB_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24826;"	d
+DB_DA_SX_SUB_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24828;"	d
+DB_DA_SX_SUB_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24830;"	d
+DB_DA_SX_VCO_ISEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24834;"	d
+DB_DA_SX_VCO_ISEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24832;"	d
+DB_DA_SX_VCO_ISEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24831;"	d
+DB_DA_SX_VCO_ISEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24833;"	d
+DB_DA_SX_VCO_ISEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24835;"	d
+DB_GEMINIA_AD_ADC_I_OUT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13399;"	d
+DB_GEMINIA_AD_ADC_I_OUT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13397;"	d
+DB_GEMINIA_AD_ADC_I_OUT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13396;"	d
+DB_GEMINIA_AD_ADC_I_OUT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13398;"	d
+DB_GEMINIA_AD_ADC_I_OUT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13400;"	d
+DB_GEMINIA_AD_ADC_Q_OUT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13404;"	d
+DB_GEMINIA_AD_ADC_Q_OUT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13402;"	d
+DB_GEMINIA_AD_ADC_Q_OUT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13401;"	d
+DB_GEMINIA_AD_ADC_Q_OUT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13403;"	d
+DB_GEMINIA_AD_ADC_Q_OUT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13405;"	d
+DB_GEMINIA_AD_DP_VT_MON_Q_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13444;"	d
+DB_GEMINIA_AD_DP_VT_MON_Q_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13442;"	d
+DB_GEMINIA_AD_DP_VT_MON_Q_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13441;"	d
+DB_GEMINIA_AD_DP_VT_MON_Q_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13443;"	d
+DB_GEMINIA_AD_DP_VT_MON_Q_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13445;"	d
+DB_GEMINIA_AD_RX_RSSIADC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13409;"	d
+DB_GEMINIA_AD_RX_RSSIADC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13407;"	d
+DB_GEMINIA_AD_RX_RSSIADC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13406;"	d
+DB_GEMINIA_AD_RX_RSSIADC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13408;"	d
+DB_GEMINIA_AD_RX_RSSIADC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13410;"	d
+DB_GEMINIA_DA_SARADC_BIT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13414;"	d
+DB_GEMINIA_DA_SARADC_BIT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13412;"	d
+DB_GEMINIA_DA_SARADC_BIT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13411;"	d
+DB_GEMINIA_DA_SARADC_BIT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13413;"	d
+DB_GEMINIA_DA_SARADC_BIT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13415;"	d
+DB_GEMINIA_DA_SX_SUB_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13424;"	d
+DB_GEMINIA_DA_SX_SUB_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13422;"	d
+DB_GEMINIA_DA_SX_SUB_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13421;"	d
+DB_GEMINIA_DA_SX_SUB_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13423;"	d
+DB_GEMINIA_DA_SX_SUB_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13425;"	d
+DB_GEMINIA_DA_SX_VCO_ISEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13429;"	d
+DB_GEMINIA_DA_SX_VCO_ISEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13427;"	d
+DB_GEMINIA_DA_SX_VCO_ISEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13426;"	d
+DB_GEMINIA_DA_SX_VCO_ISEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13428;"	d
+DB_GEMINIA_DA_SX_VCO_ISEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13430;"	d
+DB_GEMINIA_SX_SBCAL_NCOUNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13449;"	d
+DB_GEMINIA_SX_SBCAL_NCOUNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13447;"	d
+DB_GEMINIA_SX_SBCAL_NCOUNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13446;"	d
+DB_GEMINIA_SX_SBCAL_NCOUNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13448;"	d
+DB_GEMINIA_SX_SBCAL_NCOUNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13450;"	d
+DB_GEMINIA_SX_SBCAL_NTARGET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13454;"	d
+DB_GEMINIA_SX_SBCAL_NTARGET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13452;"	d
+DB_GEMINIA_SX_SBCAL_NTARGET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13451;"	d
+DB_GEMINIA_SX_SBCAL_NTARGET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13453;"	d
+DB_GEMINIA_SX_SBCAL_NTARGET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13455;"	d
+DB_GEMINIA_SX_TTL_VT_DET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13439;"	d
+DB_GEMINIA_SX_TTL_VT_DET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13437;"	d
+DB_GEMINIA_SX_TTL_VT_DET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13436;"	d
+DB_GEMINIA_SX_TTL_VT_DET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13438;"	d
+DB_GEMINIA_SX_TTL_VT_DET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13440;"	d
+DB_GEMINIA_VO_AAC_COMPOUT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13434;"	d
+DB_GEMINIA_VO_AAC_COMPOUT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13432;"	d
+DB_GEMINIA_VO_AAC_COMPOUT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13431;"	d
+DB_GEMINIA_VO_AAC_COMPOUT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13433;"	d
+DB_GEMINIA_VO_AAC_COMPOUT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13435;"	d
+DB_SX5GB_SBCAL_NCOUNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26939;"	d
+DB_SX5GB_SBCAL_NCOUNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26937;"	d
+DB_SX5GB_SBCAL_NCOUNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26936;"	d
+DB_SX5GB_SBCAL_NCOUNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26938;"	d
+DB_SX5GB_SBCAL_NCOUNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26940;"	d
+DB_SX5GB_SBCAL_NTARGET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26944;"	d
+DB_SX5GB_SBCAL_NTARGET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26942;"	d
+DB_SX5GB_SBCAL_NTARGET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26941;"	d
+DB_SX5GB_SBCAL_NTARGET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26943;"	d
+DB_SX5GB_SBCAL_NTARGET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26945;"	d
+DB_SX5GB_TTL_VT_DET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26914;"	d
+DB_SX5GB_TTL_VT_DET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26912;"	d
+DB_SX5GB_TTL_VT_DET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26911;"	d
+DB_SX5GB_TTL_VT_DET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26913;"	d
+DB_SX5GB_TTL_VT_DET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26915;"	d
+DB_SXMIX_SCA_SEL_A1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26919;"	d
+DB_SXMIX_SCA_SEL_A1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26917;"	d
+DB_SXMIX_SCA_SEL_A1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26916;"	d
+DB_SXMIX_SCA_SEL_A1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26918;"	d
+DB_SXMIX_SCA_SEL_A1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26920;"	d
+DB_SXMIX_SCA_SEL_A2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26924;"	d
+DB_SXMIX_SCA_SEL_A2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26922;"	d
+DB_SXMIX_SCA_SEL_A2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26921;"	d
+DB_SXMIX_SCA_SEL_A2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26923;"	d
+DB_SXMIX_SCA_SEL_A2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26925;"	d
+DB_SXREP_SCA_SEL_B1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26929;"	d
+DB_SXREP_SCA_SEL_B1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26927;"	d
+DB_SXREP_SCA_SEL_B1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26926;"	d
+DB_SXREP_SCA_SEL_B1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26928;"	d
+DB_SXREP_SCA_SEL_B1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26930;"	d
+DB_SXREP_SCA_SEL_B2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26934;"	d
+DB_SXREP_SCA_SEL_B2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26932;"	d
+DB_SXREP_SCA_SEL_B2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26931;"	d
+DB_SXREP_SCA_SEL_B2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26933;"	d
+DB_SXREP_SCA_SEL_B2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26935;"	d
+DB_SX_SBCAL_NCOUNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24859;"	d
+DB_SX_SBCAL_NCOUNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24857;"	d
+DB_SX_SBCAL_NCOUNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24856;"	d
+DB_SX_SBCAL_NCOUNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24858;"	d
+DB_SX_SBCAL_NCOUNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24860;"	d
+DB_SX_SBCAL_NTARGET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24864;"	d
+DB_SX_SBCAL_NTARGET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24862;"	d
+DB_SX_SBCAL_NTARGET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24861;"	d
+DB_SX_SBCAL_NTARGET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24863;"	d
+DB_SX_SBCAL_NTARGET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24865;"	d
+DB_SX_TTL_VT_DET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24844;"	d
+DB_SX_TTL_VT_DET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24842;"	d
+DB_SX_TTL_VT_DET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24841;"	d
+DB_SX_TTL_VT_DET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24843;"	d
+DB_SX_TTL_VT_DET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24845;"	d
+DB_TURISMO_TRX_AD_ADC_I_OUT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17954;"	d
+DB_TURISMO_TRX_AD_ADC_I_OUT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17952;"	d
+DB_TURISMO_TRX_AD_ADC_I_OUT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17951;"	d
+DB_TURISMO_TRX_AD_ADC_I_OUT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17953;"	d
+DB_TURISMO_TRX_AD_ADC_I_OUT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17955;"	d
+DB_TURISMO_TRX_AD_ADC_Q_OUT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17959;"	d
+DB_TURISMO_TRX_AD_ADC_Q_OUT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17957;"	d
+DB_TURISMO_TRX_AD_ADC_Q_OUT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17956;"	d
+DB_TURISMO_TRX_AD_ADC_Q_OUT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17958;"	d
+DB_TURISMO_TRX_AD_ADC_Q_OUT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17960;"	d
+DB_TURISMO_TRX_AD_DP_VT_MON_Q_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17999;"	d
+DB_TURISMO_TRX_AD_DP_VT_MON_Q_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17997;"	d
+DB_TURISMO_TRX_AD_DP_VT_MON_Q_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17996;"	d
+DB_TURISMO_TRX_AD_DP_VT_MON_Q_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17998;"	d
+DB_TURISMO_TRX_AD_DP_VT_MON_Q_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18000;"	d
+DB_TURISMO_TRX_AD_IOT_ADC_OUT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18004;"	d
+DB_TURISMO_TRX_AD_IOT_ADC_OUT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18002;"	d
+DB_TURISMO_TRX_AD_IOT_ADC_OUT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18001;"	d
+DB_TURISMO_TRX_AD_IOT_ADC_OUT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18003;"	d
+DB_TURISMO_TRX_AD_IOT_ADC_OUT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18005;"	d
+DB_TURISMO_TRX_AD_RX_RSSIADC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17964;"	d
+DB_TURISMO_TRX_AD_RX_RSSIADC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17962;"	d
+DB_TURISMO_TRX_AD_RX_RSSIADC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17961;"	d
+DB_TURISMO_TRX_AD_RX_RSSIADC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17963;"	d
+DB_TURISMO_TRX_AD_RX_RSSIADC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17965;"	d
+DB_TURISMO_TRX_AD_SX5GB_AAC_COMPOUT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20004;"	d
+DB_TURISMO_TRX_AD_SX5GB_AAC_COMPOUT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20002;"	d
+DB_TURISMO_TRX_AD_SX5GB_AAC_COMPOUT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20001;"	d
+DB_TURISMO_TRX_AD_SX5GB_AAC_COMPOUT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20003;"	d
+DB_TURISMO_TRX_AD_SX5GB_AAC_COMPOUT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20005;"	d
+DB_TURISMO_TRX_DA_SARADC_BIT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17969;"	d
+DB_TURISMO_TRX_DA_SARADC_BIT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17967;"	d
+DB_TURISMO_TRX_DA_SARADC_BIT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17966;"	d
+DB_TURISMO_TRX_DA_SARADC_BIT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17968;"	d
+DB_TURISMO_TRX_DA_SARADC_BIT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17970;"	d
+DB_TURISMO_TRX_DA_SX5GB_SUB_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19974;"	d
+DB_TURISMO_TRX_DA_SX5GB_SUB_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19972;"	d
+DB_TURISMO_TRX_DA_SX5GB_SUB_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19971;"	d
+DB_TURISMO_TRX_DA_SX5GB_SUB_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19973;"	d
+DB_TURISMO_TRX_DA_SX5GB_SUB_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19975;"	d
+DB_TURISMO_TRX_DA_SX5GB_VCO_ISEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19979;"	d
+DB_TURISMO_TRX_DA_SX5GB_VCO_ISEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19977;"	d
+DB_TURISMO_TRX_DA_SX5GB_VCO_ISEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19976;"	d
+DB_TURISMO_TRX_DA_SX5GB_VCO_ISEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19978;"	d
+DB_TURISMO_TRX_DA_SX5GB_VCO_ISEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19980;"	d
+DB_TURISMO_TRX_DA_SXMIX_GMSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19989;"	d
+DB_TURISMO_TRX_DA_SXMIX_GMSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19987;"	d
+DB_TURISMO_TRX_DA_SXMIX_GMSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19986;"	d
+DB_TURISMO_TRX_DA_SXMIX_GMSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19988;"	d
+DB_TURISMO_TRX_DA_SXMIX_GMSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19990;"	d
+DB_TURISMO_TRX_DA_SXMIX_SCA_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19984;"	d
+DB_TURISMO_TRX_DA_SXMIX_SCA_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19982;"	d
+DB_TURISMO_TRX_DA_SXMIX_SCA_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19981;"	d
+DB_TURISMO_TRX_DA_SXMIX_SCA_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19983;"	d
+DB_TURISMO_TRX_DA_SXMIX_SCA_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19985;"	d
+DB_TURISMO_TRX_DA_SXREP_CSSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19999;"	d
+DB_TURISMO_TRX_DA_SXREP_CSSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19997;"	d
+DB_TURISMO_TRX_DA_SXREP_CSSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19996;"	d
+DB_TURISMO_TRX_DA_SXREP_CSSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19998;"	d
+DB_TURISMO_TRX_DA_SXREP_CSSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20000;"	d
+DB_TURISMO_TRX_DA_SXREP_SCA_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19994;"	d
+DB_TURISMO_TRX_DA_SXREP_SCA_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19992;"	d
+DB_TURISMO_TRX_DA_SXREP_SCA_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19991;"	d
+DB_TURISMO_TRX_DA_SXREP_SCA_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19993;"	d
+DB_TURISMO_TRX_DA_SXREP_SCA_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19995;"	d
+DB_TURISMO_TRX_DA_SX_SUB_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17979;"	d
+DB_TURISMO_TRX_DA_SX_SUB_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17977;"	d
+DB_TURISMO_TRX_DA_SX_SUB_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17976;"	d
+DB_TURISMO_TRX_DA_SX_SUB_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17978;"	d
+DB_TURISMO_TRX_DA_SX_SUB_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17980;"	d
+DB_TURISMO_TRX_DA_SX_VCO_ISEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17984;"	d
+DB_TURISMO_TRX_DA_SX_VCO_ISEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17982;"	d
+DB_TURISMO_TRX_DA_SX_VCO_ISEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17981;"	d
+DB_TURISMO_TRX_DA_SX_VCO_ISEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17983;"	d
+DB_TURISMO_TRX_DA_SX_VCO_ISEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17985;"	d
+DB_TURISMO_TRX_SX5GB_SBCAL_NCOUNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20034;"	d
+DB_TURISMO_TRX_SX5GB_SBCAL_NCOUNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20032;"	d
+DB_TURISMO_TRX_SX5GB_SBCAL_NCOUNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20031;"	d
+DB_TURISMO_TRX_SX5GB_SBCAL_NCOUNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20033;"	d
+DB_TURISMO_TRX_SX5GB_SBCAL_NCOUNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20035;"	d
+DB_TURISMO_TRX_SX5GB_SBCAL_NTARGET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20039;"	d
+DB_TURISMO_TRX_SX5GB_SBCAL_NTARGET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20037;"	d
+DB_TURISMO_TRX_SX5GB_SBCAL_NTARGET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20036;"	d
+DB_TURISMO_TRX_SX5GB_SBCAL_NTARGET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20038;"	d
+DB_TURISMO_TRX_SX5GB_SBCAL_NTARGET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20040;"	d
+DB_TURISMO_TRX_SX5GB_TTL_VT_DET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20009;"	d
+DB_TURISMO_TRX_SX5GB_TTL_VT_DET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20007;"	d
+DB_TURISMO_TRX_SX5GB_TTL_VT_DET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20006;"	d
+DB_TURISMO_TRX_SX5GB_TTL_VT_DET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20008;"	d
+DB_TURISMO_TRX_SX5GB_TTL_VT_DET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20010;"	d
+DB_TURISMO_TRX_SXMIX_SCA_SEL_A1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20014;"	d
+DB_TURISMO_TRX_SXMIX_SCA_SEL_A1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20012;"	d
+DB_TURISMO_TRX_SXMIX_SCA_SEL_A1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20011;"	d
+DB_TURISMO_TRX_SXMIX_SCA_SEL_A1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20013;"	d
+DB_TURISMO_TRX_SXMIX_SCA_SEL_A1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20015;"	d
+DB_TURISMO_TRX_SXMIX_SCA_SEL_A2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20019;"	d
+DB_TURISMO_TRX_SXMIX_SCA_SEL_A2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20017;"	d
+DB_TURISMO_TRX_SXMIX_SCA_SEL_A2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20016;"	d
+DB_TURISMO_TRX_SXMIX_SCA_SEL_A2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20018;"	d
+DB_TURISMO_TRX_SXMIX_SCA_SEL_A2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20020;"	d
+DB_TURISMO_TRX_SXREP_SCA_SEL_B1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20024;"	d
+DB_TURISMO_TRX_SXREP_SCA_SEL_B1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20022;"	d
+DB_TURISMO_TRX_SXREP_SCA_SEL_B1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20021;"	d
+DB_TURISMO_TRX_SXREP_SCA_SEL_B1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20023;"	d
+DB_TURISMO_TRX_SXREP_SCA_SEL_B1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20025;"	d
+DB_TURISMO_TRX_SXREP_SCA_SEL_B2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20029;"	d
+DB_TURISMO_TRX_SXREP_SCA_SEL_B2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20027;"	d
+DB_TURISMO_TRX_SXREP_SCA_SEL_B2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20026;"	d
+DB_TURISMO_TRX_SXREP_SCA_SEL_B2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20028;"	d
+DB_TURISMO_TRX_SXREP_SCA_SEL_B2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20030;"	d
+DB_TURISMO_TRX_SX_SBCAL_NCOUNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18009;"	d
+DB_TURISMO_TRX_SX_SBCAL_NCOUNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18007;"	d
+DB_TURISMO_TRX_SX_SBCAL_NCOUNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18006;"	d
+DB_TURISMO_TRX_SX_SBCAL_NCOUNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18008;"	d
+DB_TURISMO_TRX_SX_SBCAL_NCOUNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18010;"	d
+DB_TURISMO_TRX_SX_SBCAL_NTARGET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18014;"	d
+DB_TURISMO_TRX_SX_SBCAL_NTARGET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18012;"	d
+DB_TURISMO_TRX_SX_SBCAL_NTARGET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18011;"	d
+DB_TURISMO_TRX_SX_SBCAL_NTARGET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18013;"	d
+DB_TURISMO_TRX_SX_SBCAL_NTARGET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18015;"	d
+DB_TURISMO_TRX_SX_TTL_VT_DET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17994;"	d
+DB_TURISMO_TRX_SX_TTL_VT_DET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17992;"	d
+DB_TURISMO_TRX_SX_TTL_VT_DET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17991;"	d
+DB_TURISMO_TRX_SX_TTL_VT_DET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17993;"	d
+DB_TURISMO_TRX_SX_TTL_VT_DET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17995;"	d
+DB_TURISMO_TRX_VO_AAC_COMPOUT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17989;"	d
+DB_TURISMO_TRX_VO_AAC_COMPOUT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17987;"	d
+DB_TURISMO_TRX_VO_AAC_COMPOUT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17986;"	d
+DB_TURISMO_TRX_VO_AAC_COMPOUT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17988;"	d
+DB_TURISMO_TRX_VO_AAC_COMPOUT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17990;"	d
+DB_VO_AAC_COMPOUT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24839;"	d
+DB_VO_AAC_COMPOUT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24837;"	d
+DB_VO_AAC_COMPOUT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24836;"	d
+DB_VO_AAC_COMPOUT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24838;"	d
+DB_VO_AAC_COMPOUT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24840;"	d
+DEAUTH_DISASSOC_LEN	smac/ssv_pm.c	44;"	d	file:
+DEBUG	include/ssv_mod_conf.h	7;"	d
+DEBUGFS_ADD_BOOL	smac/ssv6xxx_debugfs.c	160;"	d	file:
+DEBUGFS_ADD_FILE	smac/ssv6xxx_debugfs.c	155;"	d	file:
+DEBUGFS_ADD_U32	smac/ssv6xxx_debugfs.c	174;"	d	file:
+DEBUGFS_ADD_X32	smac/ssv6xxx_debugfs.c	167;"	d	file:
+DEBUGFS_READ_FILE_OPS	smac/ssv6xxx_debugfs.c	189;"	d	file:
+DEBUGFS_READ_FUNC	smac/ssv6xxx_debugfs.c	181;"	d	file:
+DEBUGFS_READ_WRITE_FILE_OPS	smac/ssv6xxx_debugfs.c	203;"	d	file:
+DEBUGFS_WRITE_FILE_OPS	smac/ssv6xxx_debugfs.c	196;"	d	file:
+DEBUGFS_WRITE_FUNC	smac/ssv6xxx_debugfs.c	185;"	d	file:
+DEBUG_2P4G_RXDC_CAL	smac/hal/ssv6006c/turismo_common.h	1875;"	d
+DEBUG_5G_RXDC_CAL	smac/hal/ssv6006c/turismo_common.h	1942;"	d
+DEBUG_5G_RXIQ_CAL	smac/hal/ssv6006c/turismo_common.h	2501;"	d
+DEBUG_CTL_HI	include/ssv6200_aux.h	17899;"	d
+DEBUG_CTL_I_MSK	include/ssv6200_aux.h	17897;"	d
+DEBUG_CTL_MSK	include/ssv6200_aux.h	17896;"	d
+DEBUG_CTL_SFT	include/ssv6200_aux.h	17898;"	d
+DEBUG_CTL_SZ	include/ssv6200_aux.h	17900;"	d
+DEBUG_H	bridge/debug.h	17;"	d
+DEBUG_H16_HI	include/ssv6200_aux.h	17904;"	d
+DEBUG_H16_I_MSK	include/ssv6200_aux.h	17902;"	d
+DEBUG_H16_MSK	include/ssv6200_aux.h	17901;"	d
+DEBUG_H16_SFT	include/ssv6200_aux.h	17903;"	d
+DEBUG_H16_SZ	include/ssv6200_aux.h	17905;"	d
+DEBUG_MITIGATE_CCI	smac/hal/ssv6006c/ssv6006_phy.c	37;"	d	file:
+DEBUG_OUT_HI	include/ssv6200_aux.h	17909;"	d
+DEBUG_OUT_I_MSK	include/ssv6200_aux.h	17907;"	d
+DEBUG_OUT_MSK	include/ssv6200_aux.h	17906;"	d
+DEBUG_OUT_SFT	include/ssv6200_aux.h	17908;"	d
+DEBUG_OUT_SZ	include/ssv6200_aux.h	17910;"	d
+DEBUG_RX_IQ_CAL	smac/hal/ssv6006c/turismo_common.h	2193;"	d
+DEBUG_SEL_HI	include/ssv6200_aux.h	14649;"	d
+DEBUG_SEL_I_MSK	include/ssv6200_aux.h	14647;"	d
+DEBUG_SEL_MSK	include/ssv6200_aux.h	14646;"	d
+DEBUG_SEL_SFT	include/ssv6200_aux.h	14648;"	d
+DEBUG_SEL_SZ	include/ssv6200_aux.h	14650;"	d
+DEC_DIN_MSB_HI	include/ssv6200_aux.h	6709;"	d
+DEC_DIN_MSB_I_MSK	include/ssv6200_aux.h	6707;"	d
+DEC_DIN_MSB_MSK	include/ssv6200_aux.h	6706;"	d
+DEC_DIN_MSB_SFT	include/ssv6200_aux.h	6708;"	d
+DEC_DIN_MSB_SZ	include/ssv6200_aux.h	6710;"	d
+DEC_DOUT_MSB_HI	include/ssv6200_aux.h	6704;"	d
+DEC_DOUT_MSB_I_MSK	include/ssv6200_aux.h	6702;"	d
+DEC_DOUT_MSB_MSK	include/ssv6200_aux.h	6701;"	d
+DEC_DOUT_MSB_SFT	include/ssv6200_aux.h	6703;"	d
+DEC_DOUT_MSB_SZ	include/ssv6200_aux.h	6705;"	d
+DEFAULT_CFG_BIN_NAME	smac/hal/ssv6006c/ssv6006_mac.h	111;"	d
+DEFAULT_DPD_BBSCALE_2500	smac/hal/ssv6006c/turismoC_wifi_phy_reg.c	97;"	d	file:
+DEFAULT_DPD_BBSCALE_2500	smac/hal/ssv6006c/turismo_common.h	218;"	d
+DEFAULT_DPD_BBSCALE_5100	smac/hal/ssv6006c/turismoC_wifi_phy_reg.c	98;"	d	file:
+DEFAULT_DPD_BBSCALE_5100	smac/hal/ssv6006c/turismo_common.h	219;"	d
+DEFAULT_DPD_BBSCALE_5500	smac/hal/ssv6006c/turismoC_wifi_phy_reg.c	99;"	d	file:
+DEFAULT_DPD_BBSCALE_5500	smac/hal/ssv6006c/turismo_common.h	220;"	d
+DEFAULT_DPD_BBSCALE_5700	smac/hal/ssv6006c/turismoC_wifi_phy_reg.c	100;"	d	file:
+DEFAULT_DPD_BBSCALE_5700	smac/hal/ssv6006c/turismo_common.h	221;"	d
+DEFAULT_DPD_BBSCALE_5900	smac/hal/ssv6006c/turismoC_wifi_phy_reg.c	101;"	d	file:
+DEFAULT_DPD_BBSCALE_5900	smac/hal/ssv6006c/turismo_common.h	222;"	d
+DEF_2_4G_CALIBRATION__AMP__TEST_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17350;"	d
+DEF_2_4G_LDO_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17351;"	d
+DEF_2_4G_RX_FE_HG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17359;"	d
+DEF_2_4G_RX_FE_LG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17361;"	d
+DEF_2_4G_RX_FE_MG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17360;"	d
+DEF_2_4G_RX_FE_ULG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17362;"	d
+DEF_2_4G_RX_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17355;"	d
+DEF_2_4G_TRX_DUMMY_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17425;"	d
+DEF_2_4G_TRX_MANUAL_ENABLE_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17349;"	d
+DEF_2_4G_TX_FE_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17356;"	d
+DEF_2_4G_TX_PA_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17357;"	d
+DEF_2_4G_TX_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17358;"	d
+DEF_5G_CALIBRATION_GAIN_REGISTER1	smac/hal/ssv6006c/ssv6006C_reg.h	17476;"	d
+DEF_5G_CALIBRATION_TIMER_GAIN_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17475;"	d
+DEF_5G_DCOC_IDAC_REGISTER1	smac/hal/ssv6006c/ssv6006C_reg.h	17451;"	d
+DEF_5G_DCOC_IDAC_REGISTER10	smac/hal/ssv6006c/ssv6006C_reg.h	17460;"	d
+DEF_5G_DCOC_IDAC_REGISTER11	smac/hal/ssv6006c/ssv6006C_reg.h	17461;"	d
+DEF_5G_DCOC_IDAC_REGISTER12	smac/hal/ssv6006c/ssv6006C_reg.h	17462;"	d
+DEF_5G_DCOC_IDAC_REGISTER13	smac/hal/ssv6006c/ssv6006C_reg.h	17463;"	d
+DEF_5G_DCOC_IDAC_REGISTER14	smac/hal/ssv6006c/ssv6006C_reg.h	17464;"	d
+DEF_5G_DCOC_IDAC_REGISTER15	smac/hal/ssv6006c/ssv6006C_reg.h	17465;"	d
+DEF_5G_DCOC_IDAC_REGISTER16	smac/hal/ssv6006c/ssv6006C_reg.h	17466;"	d
+DEF_5G_DCOC_IDAC_REGISTER17	smac/hal/ssv6006c/ssv6006C_reg.h	17467;"	d
+DEF_5G_DCOC_IDAC_REGISTER18	smac/hal/ssv6006c/ssv6006C_reg.h	17468;"	d
+DEF_5G_DCOC_IDAC_REGISTER19	smac/hal/ssv6006c/ssv6006C_reg.h	17469;"	d
+DEF_5G_DCOC_IDAC_REGISTER2	smac/hal/ssv6006c/ssv6006C_reg.h	17452;"	d
+DEF_5G_DCOC_IDAC_REGISTER20	smac/hal/ssv6006c/ssv6006C_reg.h	17470;"	d
+DEF_5G_DCOC_IDAC_REGISTER21	smac/hal/ssv6006c/ssv6006C_reg.h	17471;"	d
+DEF_5G_DCOC_IDAC_REGISTER3	smac/hal/ssv6006c/ssv6006C_reg.h	17453;"	d
+DEF_5G_DCOC_IDAC_REGISTER4	smac/hal/ssv6006c/ssv6006C_reg.h	17454;"	d
+DEF_5G_DCOC_IDAC_REGISTER5	smac/hal/ssv6006c/ssv6006C_reg.h	17455;"	d
+DEF_5G_DCOC_IDAC_REGISTER6	smac/hal/ssv6006c/ssv6006C_reg.h	17456;"	d
+DEF_5G_DCOC_IDAC_REGISTER7	smac/hal/ssv6006c/ssv6006C_reg.h	17457;"	d
+DEF_5G_DCOC_IDAC_REGISTER8	smac/hal/ssv6006c/ssv6006C_reg.h	17458;"	d
+DEF_5G_DCOC_IDAC_REGISTER9	smac/hal/ssv6006c/ssv6006C_reg.h	17459;"	d
+DEF_5G_LDO_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17430;"	d
+DEF_5G_MODE_DECODER_TIMER_REGISTER1	smac/hal/ssv6006c/ssv6006C_reg.h	17472;"	d
+DEF_5G_R2T_TIMER_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17474;"	d
+DEF_5G_RX_FE_HG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17435;"	d
+DEF_5G_RX_FE_LG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17437;"	d
+DEF_5G_RX_FE_MG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17436;"	d
+DEF_5G_RX_FE_ULG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17438;"	d
+DEF_5G_RX_LNA_LOAD_SCA_CONTROL	smac/hal/ssv6006c/ssv6006C_reg.h	17483;"	d
+DEF_5G_RX_LNA_MATCHING_SCA_CONTROL	smac/hal/ssv6006c/ssv6006C_reg.h	17482;"	d
+DEF_5G_RX_REGISTER1	smac/hal/ssv6006c/ssv6006C_reg.h	17431;"	d
+DEF_5G_RX_REGISTER2	smac/hal/ssv6006c/ssv6006C_reg.h	17432;"	d
+DEF_5G_T2R_TIMER_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17473;"	d
+DEF_5G_TRX_DUMMY_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17477;"	d
+DEF_5G_TRX_MANUAL_ENABLE_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17429;"	d
+DEF_5G_TX_DAC_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17439;"	d
+DEF_5G_TX_FE_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17433;"	d
+DEF_5G_TX_GAIN_PAFB_CONTROL	smac/hal/ssv6006c/ssv6006C_reg.h	17486;"	d
+DEF_5G_TX_PGA_CAPSW_CONTROL_I	smac/hal/ssv6006c/ssv6006C_reg.h	17484;"	d
+DEF_5G_TX_PGA_CAPSW_CONTROL_II	smac/hal/ssv6006c/ssv6006C_reg.h	17485;"	d
+DEF_5G_TX_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17434;"	d
+DEF_ABB_REGISTER_1	include/ssv6200_reg.h	9614;"	d
+DEF_ABB_REGISTER_2	include/ssv6200_reg.h	9615;"	d
+DEF_ACK_GEN_EN	include/ssv6200_reg.h	9027;"	d
+DEF_ACK_GEN_EN	smac/hal/ssv6006c/ssv6006C_reg.h	16553;"	d
+DEF_ACK_GEN_PARA	include/ssv6200_reg.h	9028;"	d
+DEF_ACK_GEN_PARA	smac/hal/ssv6006c/ssv6006C_reg.h	16554;"	d
+DEF_ACK_GEN_RA_0	include/ssv6200_reg.h	9029;"	d
+DEF_ACK_GEN_RA_0	smac/hal/ssv6006c/ssv6006C_reg.h	16555;"	d
+DEF_ACK_GEN_RA_1	include/ssv6200_reg.h	9030;"	d
+DEF_ACK_GEN_RA_1	smac/hal/ssv6006c/ssv6006C_reg.h	16556;"	d
+DEF_AHB_BRG_STATUS	include/ssv6200_reg.h	8559;"	d
+DEF_AHB_FEN_ADDR	include/ssv6200_reg.h	8569;"	d
+DEF_AHB_ILLFEN_STATUS	include/ssv6200_reg.h	8570;"	d
+DEF_AHB_ILL_ADDR	include/ssv6200_reg.h	8568;"	d
+DEF_ALC_ABORT	smac/hal/ssv6006c/ssv6006C_reg.h	17976;"	d
+DEF_ALC_ID_INF1	include/ssv6200_reg.h	9393;"	d
+DEF_ALC_ID_INF1	smac/hal/ssv6006c/ssv6006C_reg.h	17975;"	d
+DEF_ALC_ID_INFO	include/ssv6200_reg.h	9392;"	d
+DEF_ALC_ID_INFO	smac/hal/ssv6006c/ssv6006C_reg.h	17974;"	d
+DEF_ALC_NOCHG_ID_STATUS	include/ssv6200_reg.h	9685;"	d
+DEF_ALC_RLS_ABORT	include/ssv6200_reg.h	9658;"	d
+DEF_ALC_RLS_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	17977;"	d
+DEF_ALC_STA	include/ssv6200_reg.h	9367;"	d
+DEF_ALC_STA	smac/hal/ssv6006c/ssv6006C_reg.h	17949;"	d
+DEF_ALL_SOFTWARE_RESET	include/ssv6200_reg.h	9204;"	d
+DEF_ALL_SOFTWARE_RESET	smac/hal/ssv6006c/ssv6006C_reg.h	16778;"	d
+DEF_ALWAYS_ON_CFG00	smac/hal/ssv6006c/ssv6006C_reg.h	16122;"	d
+DEF_AMPDU_SCOREBOAD_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	16564;"	d
+DEF_AMPDU_SIG	include/ssv6200_reg.h	9054;"	d
+DEF_AMPDU_SIG	smac/hal/ssv6006c/ssv6006C_reg.h	16571;"	d
+DEF_AUDIO_CTRL_REG	smac/hal/ssv6006c/ssv6006C_reg.h	17520;"	d
+DEF_AUDIO_PDM_REG	smac/hal/ssv6006c/ssv6006C_reg.h	17521;"	d
+DEF_BA_CTRL	include/ssv6200_reg.h	9019;"	d
+DEF_BA_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	16545;"	d
+DEF_BA_SB0	include/ssv6200_reg.h	9024;"	d
+DEF_BA_SB0	smac/hal/ssv6006c/ssv6006C_reg.h	16550;"	d
+DEF_BA_SB1	include/ssv6200_reg.h	9025;"	d
+DEF_BA_SB1	smac/hal/ssv6006c/ssv6006C_reg.h	16551;"	d
+DEF_BA_ST_SEQ	include/ssv6200_reg.h	9023;"	d
+DEF_BA_ST_SEQ	smac/hal/ssv6006c/ssv6006C_reg.h	16549;"	d
+DEF_BA_TA_0	include/ssv6200_reg.h	9020;"	d
+DEF_BA_TA_0	smac/hal/ssv6006c/ssv6006C_reg.h	16546;"	d
+DEF_BA_TA_1	include/ssv6200_reg.h	9021;"	d
+DEF_BA_TA_1	smac/hal/ssv6006c/ssv6006C_reg.h	16547;"	d
+DEF_BA_TID	include/ssv6200_reg.h	9022;"	d
+DEF_BA_TID	smac/hal/ssv6006c/ssv6006C_reg.h	16548;"	d
+DEF_BIST_BIST_CTRL	include/ssv6200_reg.h	8560;"	d
+DEF_BIST_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	16186;"	d
+DEF_BIST_CTRL1	smac/hal/ssv6006c/ssv6006C_reg.h	16187;"	d
+DEF_BIST_CTRL2	smac/hal/ssv6006c/ssv6006C_reg.h	16188;"	d
+DEF_BIST_MODE_REG_IN	include/ssv6200_reg.h	8561;"	d
+DEF_BIST_MODE_REG_IN_MMU	include/ssv6200_reg.h	8576;"	d
+DEF_BIST_MODE_REG_OUT	include/ssv6200_reg.h	8562;"	d
+DEF_BIST_MODE_REG_OUT_MMU	include/ssv6200_reg.h	8577;"	d
+DEF_BIST_MONITOR_BUS_LSB	include/ssv6200_reg.h	8563;"	d
+DEF_BIST_MONITOR_BUS_MMU	include/ssv6200_reg.h	8578;"	d
+DEF_BIST_MONITOR_BUS_MSB	include/ssv6200_reg.h	8564;"	d
+DEF_BOOT	include/ssv6200_reg.h	8549;"	d
+DEF_BOOT	smac/hal/ssv6006c/ssv6006C_reg.h	16075;"	d
+DEF_BOOTSTRAP_SAMPLE	smac/hal/ssv6006c/ssv6006C_reg.h	16083;"	d
+DEF_BOOT_ADDR	include/ssv6200_reg.h	8818;"	d
+DEF_BOOT_INFO	include/ssv6200_reg.h	8580;"	d
+DEF_BOOT_INFO	smac/hal/ssv6006c/ssv6006C_reg.h	16124;"	d
+DEF_BRG_SW_RST	include/ssv6200_reg.h	8548;"	d
+DEF_BRG_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	16074;"	d
+DEF_BROWNOUT_INT	smac/hal/ssv6006c/ssv6006C_reg.h	16391;"	d
+DEF_BROWNOUT_SETUP	smac/hal/ssv6006c/ssv6006C_reg.h	16392;"	d
+DEF_BSSID1_0	smac/hal/ssv6006c/ssv6006C_reg.h	16793;"	d
+DEF_BSSID1_1	smac/hal/ssv6006c/ssv6006C_reg.h	16794;"	d
+DEF_BSSID_0	include/ssv6200_reg.h	9213;"	d
+DEF_BSSID_0	smac/hal/ssv6006c/ssv6006C_reg.h	16787;"	d
+DEF_BSSID_1	include/ssv6200_reg.h	9214;"	d
+DEF_BSSID_1	smac/hal/ssv6006c/ssv6006C_reg.h	16788;"	d
+DEF_BTCX0	include/ssv6200_reg.h	9219;"	d
+DEF_BTCX0	smac/hal/ssv6006c/ssv6006C_reg.h	16798;"	d
+DEF_BTCX1	include/ssv6200_reg.h	9220;"	d
+DEF_BTCX1	smac/hal/ssv6006c/ssv6006C_reg.h	16799;"	d
+DEF_BTCX_MISC_CTL	smac/hal/ssv6006c/ssv6006C_reg.h	16802;"	d
+DEF_BT_DCOC_IDAC_REGISTER1	smac/hal/ssv6006c/ssv6006C_reg.h	17403;"	d
+DEF_BT_DCOC_IDAC_REGISTER10	smac/hal/ssv6006c/ssv6006C_reg.h	17412;"	d
+DEF_BT_DCOC_IDAC_REGISTER11	smac/hal/ssv6006c/ssv6006C_reg.h	17413;"	d
+DEF_BT_DCOC_IDAC_REGISTER12	smac/hal/ssv6006c/ssv6006C_reg.h	17414;"	d
+DEF_BT_DCOC_IDAC_REGISTER13	smac/hal/ssv6006c/ssv6006C_reg.h	17415;"	d
+DEF_BT_DCOC_IDAC_REGISTER14	smac/hal/ssv6006c/ssv6006C_reg.h	17416;"	d
+DEF_BT_DCOC_IDAC_REGISTER15	smac/hal/ssv6006c/ssv6006C_reg.h	17417;"	d
+DEF_BT_DCOC_IDAC_REGISTER16	smac/hal/ssv6006c/ssv6006C_reg.h	17418;"	d
+DEF_BT_DCOC_IDAC_REGISTER2	smac/hal/ssv6006c/ssv6006C_reg.h	17404;"	d
+DEF_BT_DCOC_IDAC_REGISTER3	smac/hal/ssv6006c/ssv6006C_reg.h	17405;"	d
+DEF_BT_DCOC_IDAC_REGISTER4	smac/hal/ssv6006c/ssv6006C_reg.h	17406;"	d
+DEF_BT_DCOC_IDAC_REGISTER5	smac/hal/ssv6006c/ssv6006C_reg.h	17407;"	d
+DEF_BT_DCOC_IDAC_REGISTER6	smac/hal/ssv6006c/ssv6006C_reg.h	17408;"	d
+DEF_BT_DCOC_IDAC_REGISTER7	smac/hal/ssv6006c/ssv6006C_reg.h	17409;"	d
+DEF_BT_DCOC_IDAC_REGISTER8	smac/hal/ssv6006c/ssv6006C_reg.h	17410;"	d
+DEF_BT_DCOC_IDAC_REGISTER9	smac/hal/ssv6006c/ssv6006C_reg.h	17411;"	d
+DEF_BT_RX_FE_HG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17363;"	d
+DEF_BT_RX_FE_LG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17365;"	d
+DEF_BT_RX_FE_MG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17364;"	d
+DEF_BT_RX_FE_ULG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17366;"	d
+DEF_BT_RX_FILTER_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17354;"	d
+DEF_BT_TX_DAC_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17369;"	d
+DEF_BUFFER_CLEAR_ERROR_FLAG_CLEAR	smac/hal/ssv6006c/ssv6006C_reg.h	16316;"	d
+DEF_CALIBRATION_GAIN_REGISTER0	smac/hal/ssv6006c/ssv6006C_reg.h	17423;"	d
+DEF_CALIBRATION_GAIN_REGISTER1	smac/hal/ssv6006c/ssv6006C_reg.h	17424;"	d
+DEF_CALIBRATION_TIMER_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17422;"	d
+DEF_CARD_PKT_STATUS_TEST	include/ssv6200_reg.h	8674;"	d
+DEF_CARD_RCA_REG	include/ssv6200_reg.h	8676;"	d
+DEF_CARD_RCA_REG	smac/hal/ssv6006c/ssv6006C_reg.h	16198;"	d
+DEF_CBR_ABB_REGISTER_1	include/ssv6200_reg.h	9286;"	d
+DEF_CBR_ABB_REGISTER_2	include/ssv6200_reg.h	9287;"	d
+DEF_CBR_DCOC_IDAC_REGISTER1	include/ssv6200_reg.h	9308;"	d
+DEF_CBR_DCOC_IDAC_REGISTER2	include/ssv6200_reg.h	9309;"	d
+DEF_CBR_DCOC_IDAC_REGISTER3	include/ssv6200_reg.h	9310;"	d
+DEF_CBR_DCOC_IDAC_REGISTER4	include/ssv6200_reg.h	9311;"	d
+DEF_CBR_DCOC_IDAC_REGISTER5	include/ssv6200_reg.h	9312;"	d
+DEF_CBR_DCOC_IDAC_REGISTER6	include/ssv6200_reg.h	9313;"	d
+DEF_CBR_DCOC_IDAC_REGISTER7	include/ssv6200_reg.h	9314;"	d
+DEF_CBR_DCOC_IDAC_REGISTER8	include/ssv6200_reg.h	9315;"	d
+DEF_CBR_DPLL_CP_PFD_REGISTER	include/ssv6200_reg.h	9306;"	d
+DEF_CBR_DPLL_DIVIDER_REGISTER	include/ssv6200_reg.h	9307;"	d
+DEF_CBR_DPLL_VCO_REGISTER	include/ssv6200_reg.h	9305;"	d
+DEF_CBR_HARD_WIRE_PIN_REGISTER	include/ssv6200_reg.h	9283;"	d
+DEF_CBR_LDO_REGISTER	include/ssv6200_reg.h	9285;"	d
+DEF_CBR_MANUAL_ENABLE_REGISTER	include/ssv6200_reg.h	9284;"	d
+DEF_CBR_MANUAL_REGISTER	include/ssv6200_reg.h	9317;"	d
+DEF_CBR_PATTERN_GEN	include/ssv6200_reg.h	9325;"	d
+DEF_CBR_RCAL_REGISTER	include/ssv6200_reg.h	9316;"	d
+DEF_CBR_RG_INTEGRATION	include/ssv6200_reg.h	9323;"	d
+DEF_CBR_RG_PKT_GEN_0	include/ssv6200_reg.h	9320;"	d
+DEF_CBR_RG_PKT_GEN_1	include/ssv6200_reg.h	9321;"	d
+DEF_CBR_RG_PKT_GEN_2	include/ssv6200_reg.h	9322;"	d
+DEF_CBR_RG_PKT_GEN_TXCNT	include/ssv6200_reg.h	9324;"	d
+DEF_CBR_RX_ADC_REGISTER	include/ssv6200_reg.h	9295;"	d
+DEF_CBR_RX_FE_GAIN_DECODER_REGISTER_1	include/ssv6200_reg.h	9290;"	d
+DEF_CBR_RX_FE_GAIN_DECODER_REGISTER_2	include/ssv6200_reg.h	9291;"	d
+DEF_CBR_RX_FE_GAIN_DECODER_REGISTER_3	include/ssv6200_reg.h	9292;"	d
+DEF_CBR_RX_FE_GAIN_DECODER_REGISTER_4	include/ssv6200_reg.h	9293;"	d
+DEF_CBR_RX_FE_REGISTER_1	include/ssv6200_reg.h	9289;"	d
+DEF_CBR_RX_FSM_REGISTER	include/ssv6200_reg.h	9294;"	d
+DEF_CBR_SX_DUMMY_REGISTER	include/ssv6200_reg.h	9319;"	d
+DEF_CBR_SX_ENABLE_RGISTER	include/ssv6200_reg.h	9297;"	d
+DEF_CBR_SYN_DIV_SDM_XOSC	include/ssv6200_reg.h	9302;"	d
+DEF_CBR_SYN_LCK1	include/ssv6200_reg.h	9303;"	d
+DEF_CBR_SYN_LCK2	include/ssv6200_reg.h	9304;"	d
+DEF_CBR_SYN_PFD_CHP	include/ssv6200_reg.h	9300;"	d
+DEF_CBR_SYN_RGISTER_1	include/ssv6200_reg.h	9298;"	d
+DEF_CBR_SYN_RGISTER_2	include/ssv6200_reg.h	9299;"	d
+DEF_CBR_SYN_VCO_LOBF	include/ssv6200_reg.h	9301;"	d
+DEF_CBR_TRX_DUMMY_REGISTER	include/ssv6200_reg.h	9318;"	d
+DEF_CBR_TX_DAC_REGISTER	include/ssv6200_reg.h	9296;"	d
+DEF_CBR_TX_FE_REGISTER	include/ssv6200_reg.h	9288;"	d
+DEF_CCCR_00H_REG	include/ssv6200_reg.h	8705;"	d
+DEF_CCCR_00H_REG	smac/hal/ssv6006c/ssv6006C_reg.h	16208;"	d
+DEF_CCCR_04H_REG	include/ssv6200_reg.h	8706;"	d
+DEF_CCCR_04H_REG	smac/hal/ssv6006c/ssv6006C_reg.h	16209;"	d
+DEF_CCCR_08H_REG	include/ssv6200_reg.h	8707;"	d
+DEF_CCCR_08H_REG	smac/hal/ssv6006c/ssv6006C_reg.h	16210;"	d
+DEF_CCCR_13H_REG	include/ssv6200_reg.h	8708;"	d
+DEF_CCCR_13H_REG	smac/hal/ssv6006c/ssv6006C_reg.h	16212;"	d
+DEF_CCCR_14H_REG	smac/hal/ssv6006c/ssv6006C_reg.h	16211;"	d
+DEF_CH0_PRI_TRIG	include/ssv6200_reg.h	9331;"	d
+DEF_CH0_PRI_TRIG	smac/hal/ssv6006c/ssv6006C_reg.h	17908;"	d
+DEF_CH0_TRIG_0	include/ssv6200_reg.h	9330;"	d
+DEF_CH0_TRIG_0	smac/hal/ssv6006c/ssv6006C_reg.h	17907;"	d
+DEF_CH0_TRIG_1	include/ssv6200_reg.h	9329;"	d
+DEF_CH0_TRIG_1	smac/hal/ssv6006c/ssv6006C_reg.h	17906;"	d
+DEF_CH2_INT_ADDR_ALT	smac/hal/ssv6006c/ssv6006C_reg.h	17914;"	d
+DEF_CH2_TRIG_ALT	smac/hal/ssv6006c/ssv6006C_reg.h	17913;"	d
+DEF_CHANNEL	smac/hal/ssv6006c/ssv6006C_reg.h	16565;"	d
+DEF_CHECK_SUM_IN_FILE	include/ssv6200_reg.h	8826;"	d
+DEF_CHECK_SUM_RESULT	include/ssv6200_reg.h	8825;"	d
+DEF_CHIP_DATE_00HHMMSS	smac/hal/ssv6006c/ssv6006C_reg.h	16110;"	d
+DEF_CHIP_DATE_YYYYMMDD	smac/hal/ssv6006c/ssv6006C_reg.h	16109;"	d
+DEF_CHIP_GITSHA_0	smac/hal/ssv6006c/ssv6006C_reg.h	16111;"	d
+DEF_CHIP_GITSHA_1	smac/hal/ssv6006c/ssv6006C_reg.h	16112;"	d
+DEF_CHIP_GITSHA_2	smac/hal/ssv6006c/ssv6006C_reg.h	16113;"	d
+DEF_CHIP_GITSHA_3	smac/hal/ssv6006c/ssv6006C_reg.h	16114;"	d
+DEF_CHIP_GITSHA_4	smac/hal/ssv6006c/ssv6006C_reg.h	16115;"	d
+DEF_CHIP_ID_0	include/ssv6200_reg.h	8550;"	d
+DEF_CHIP_ID_0	smac/hal/ssv6006c/ssv6006C_reg.h	16076;"	d
+DEF_CHIP_ID_1	include/ssv6200_reg.h	8551;"	d
+DEF_CHIP_ID_1	smac/hal/ssv6006c/ssv6006C_reg.h	16077;"	d
+DEF_CHIP_ID_2	include/ssv6200_reg.h	8552;"	d
+DEF_CHIP_ID_2	smac/hal/ssv6006c/ssv6006C_reg.h	16078;"	d
+DEF_CHIP_ID_3	include/ssv6200_reg.h	8553;"	d
+DEF_CHIP_ID_3	smac/hal/ssv6006c/ssv6006C_reg.h	16079;"	d
+DEF_CHIP_INFO_FPGATAG	smac/hal/ssv6006c/ssv6006C_reg.h	16119;"	d
+DEF_CHIP_INFO_ID_0	smac/hal/ssv6006c/ssv6006C_reg.h	16106;"	d
+DEF_CHIP_INFO_ID_1	smac/hal/ssv6006c/ssv6006C_reg.h	16107;"	d
+DEF_CHIP_TYPE_VER	smac/hal/ssv6006c/ssv6006C_reg.h	16108;"	d
+DEF_CH_ARB_PRI	include/ssv6200_reg.h	9377;"	d
+DEF_CH_ARB_PRI	smac/hal/ssv6006c/ssv6006C_reg.h	17959;"	d
+DEF_CH_STA_PRI	include/ssv6200_reg.h	9362;"	d
+DEF_CH_STA_PRI	smac/hal/ssv6006c/ssv6006C_reg.h	17944;"	d
+DEF_CLOCK_SELECTION	include/ssv6200_reg.h	8554;"	d
+DEF_CLOCK_SELECTION	smac/hal/ssv6006c/ssv6006C_reg.h	16080;"	d
+DEF_CLR_INT_STS0	smac/hal/ssv6006c/ssv6006C_reg.h	16362;"	d
+DEF_CLR_INT_STS1	smac/hal/ssv6006c/ssv6006C_reg.h	16361;"	d
+DEF_CLR_INT_STS2	smac/hal/ssv6006c/ssv6006C_reg.h	16360;"	d
+DEF_CMD52_DATA_FOR_LAST_TIME	include/ssv6200_reg.h	8689;"	d
+DEF_CMD_SET	smac/hal/ssv6006c/ssv6006C_reg.h	16310;"	d
+DEF_CMD_SET_1	smac/hal/ssv6006c/ssv6006C_reg.h	16311;"	d
+DEF_COMMAND_ADDR	include/ssv6200_reg.h	8828;"	d
+DEF_COMMAND_LEN	include/ssv6200_reg.h	8827;"	d
+DEF_CONDITION_NUMBER	include/ssv6200_reg.h	8745;"	d
+DEF_CONTROL	include/ssv6200_reg.h	8848;"	d
+DEF_CONTROL	smac/hal/ssv6006c/ssv6006C_reg.h	16393;"	d
+DEF_CORRECT_RATE_REPORT_LENGTH	smac/hal/ssv6006c/ssv6006C_reg.h	16439;"	d
+DEF_CO_NAV	include/ssv6200_reg.h	8899;"	d
+DEF_CO_NAV	smac/hal/ssv6006c/ssv6006C_reg.h	16463;"	d
+DEF_CPU_ID_TB0	include/ssv6200_reg.h	9327;"	d
+DEF_CPU_ID_TB0	smac/hal/ssv6006c/ssv6006C_reg.h	17904;"	d
+DEF_CPU_ID_TB1	include/ssv6200_reg.h	9328;"	d
+DEF_CPU_ID_TB1	smac/hal/ssv6006c/ssv6006C_reg.h	17905;"	d
+DEF_CPU_ID_TB2	include/ssv6200_reg.h	9354;"	d
+DEF_CPU_ID_TB2	smac/hal/ssv6006c/ssv6006C_reg.h	17936;"	d
+DEF_CPU_ID_TB3	include/ssv6200_reg.h	9355;"	d
+DEF_CPU_ID_TB3	smac/hal/ssv6006c/ssv6006C_reg.h	17937;"	d
+DEF_CPU_POR0_7	include/ssv6200_reg.h	9654;"	d
+DEF_CPU_POR8_F	include/ssv6200_reg.h	9655;"	d
+DEF_CSR_SOFTWARE_RESET	include/ssv6200_reg.h	9206;"	d
+DEF_CSR_SOFTWARE_RESET	smac/hal/ssv6006c/ssv6006C_reg.h	16780;"	d
+DEF_CS_ADD_LEN	include/ssv6200_reg.h	8883;"	d
+DEF_CS_ADD_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	16447;"	d
+DEF_CS_CHECK_SUM	include/ssv6200_reg.h	8887;"	d
+DEF_CS_CHECK_SUM	smac/hal/ssv6006c/ssv6006C_reg.h	16451;"	d
+DEF_CS_CMD	include/ssv6200_reg.h	8884;"	d
+DEF_CS_CMD	smac/hal/ssv6006c/ssv6006C_reg.h	16448;"	d
+DEF_CS_INI_BUF	include/ssv6200_reg.h	8885;"	d
+DEF_CS_INI_BUF	smac/hal/ssv6006c/ssv6006C_reg.h	16449;"	d
+DEF_CS_PSEUDO_BUF	include/ssv6200_reg.h	8886;"	d
+DEF_CS_PSEUDO_BUF	smac/hal/ssv6006c/ssv6006C_reg.h	16450;"	d
+DEF_CS_START_ADDR	include/ssv6200_reg.h	8882;"	d
+DEF_CS_START_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	16446;"	d
+DEF_D2_DMA_ADR_DST	include/ssv6200_reg.h	8844;"	d
+DEF_D2_DMA_ADR_DST	smac/hal/ssv6006c/ssv6006C_reg.h	16323;"	d
+DEF_D2_DMA_ADR_SRC	include/ssv6200_reg.h	8843;"	d
+DEF_D2_DMA_ADR_SRC	smac/hal/ssv6006c/ssv6006C_reg.h	16322;"	d
+DEF_D2_DMA_CTRL	include/ssv6200_reg.h	8845;"	d
+DEF_D2_DMA_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	16324;"	d
+DEF_D2_DMA_FILL_CONST	include/ssv6200_reg.h	8847;"	d
+DEF_D2_DMA_FILL_CONST	smac/hal/ssv6006c/ssv6006C_reg.h	16326;"	d
+DEF_D2_DMA_INT	include/ssv6200_reg.h	8846;"	d
+DEF_D2_DMA_INT	smac/hal/ssv6006c/ssv6006C_reg.h	16325;"	d
+DEF_DAT_UART_DATA	include/ssv6200_reg.h	8775;"	d
+DEF_DAT_UART_FCR	include/ssv6200_reg.h	8777;"	d
+DEF_DAT_UART_IER	include/ssv6200_reg.h	8776;"	d
+DEF_DAT_UART_ISR	include/ssv6200_reg.h	8784;"	d
+DEF_DAT_UART_LCR	include/ssv6200_reg.h	8778;"	d
+DEF_DAT_UART_LSR	include/ssv6200_reg.h	8780;"	d
+DEF_DAT_UART_MCR	include/ssv6200_reg.h	8779;"	d
+DEF_DAT_UART_MSR	include/ssv6200_reg.h	8781;"	d
+DEF_DAT_UART_RTHR	include/ssv6200_reg.h	8783;"	d
+DEF_DAT_UART_SPR	include/ssv6200_reg.h	8782;"	d
+DEF_DBG_AMPDU_FAIL	include/ssv6200_reg.h	9280;"	d
+DEF_DBG_AMPDU_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	16861;"	d
+DEF_DBG_AMPDU_PASS	include/ssv6200_reg.h	9279;"	d
+DEF_DBG_AMPDU_PASS	smac/hal/ssv6006c/ssv6006C_reg.h	16860;"	d
+DEF_DBG_CNT	include/ssv6200_reg.h	8754;"	d
+DEF_DBG_CNT2	include/ssv6200_reg.h	8755;"	d
+DEF_DBG_CNT3	include/ssv6200_reg.h	8756;"	d
+DEF_DBG_CNT4	include/ssv6200_reg.h	8757;"	d
+DEF_DBG_CONDITION_NUMBER	include/ssv6200_reg.h	8804;"	d
+DEF_DBG_DBG_CNT	include/ssv6200_reg.h	8813;"	d
+DEF_DBG_DBG_CNT2	include/ssv6200_reg.h	8814;"	d
+DEF_DBG_DBG_CNT3	include/ssv6200_reg.h	8815;"	d
+DEF_DBG_DBG_CNT4	include/ssv6200_reg.h	8816;"	d
+DEF_DBG_DEBUG_BURST_MODE	include/ssv6200_reg.h	8807;"	d
+DEF_DBG_FF_FULL	include/ssv6200_reg.h	9016;"	d
+DEF_DBG_FF_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	16542;"	d
+DEF_DBG_HOST_PATH	include/ssv6200_reg.h	8805;"	d
+DEF_DBG_INT_TAG	include/ssv6200_reg.h	8817;"	d
+DEF_DBG_LEN_ALC_FAIL	include/ssv6200_reg.h	9278;"	d
+DEF_DBG_LEN_ALC_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	16859;"	d
+DEF_DBG_LEN_CRC_FAIL	include/ssv6200_reg.h	9277;"	d
+DEF_DBG_LEN_CRC_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	16858;"	d
+DEF_DBG_MB_FULL	include/ssv6200_reg.h	9018;"	d
+DEF_DBG_MB_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	16544;"	d
+DEF_DBG_Q0_ACK_FAIL	include/ssv6200_reg.h	9259;"	d
+DEF_DBG_Q0_ACK_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	16840;"	d
+DEF_DBG_Q0_ACK_SUCCESS	include/ssv6200_reg.h	9258;"	d
+DEF_DBG_Q0_ACK_SUCCESS	smac/hal/ssv6006c/ssv6006C_reg.h	16839;"	d
+DEF_DBG_Q0_FRM_FAIL	include/ssv6200_reg.h	9257;"	d
+DEF_DBG_Q0_FRM_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	16838;"	d
+DEF_DBG_Q0_FRM_SUCCESS	include/ssv6200_reg.h	9256;"	d
+DEF_DBG_Q0_FRM_SUCCESS	smac/hal/ssv6006c/ssv6006C_reg.h	16837;"	d
+DEF_DBG_Q1_ACK_FAIL	include/ssv6200_reg.h	9263;"	d
+DEF_DBG_Q1_ACK_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	16844;"	d
+DEF_DBG_Q1_ACK_SUCCESS	include/ssv6200_reg.h	9262;"	d
+DEF_DBG_Q1_ACK_SUCCESS	smac/hal/ssv6006c/ssv6006C_reg.h	16843;"	d
+DEF_DBG_Q1_FRM_FAIL	include/ssv6200_reg.h	9261;"	d
+DEF_DBG_Q1_FRM_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	16842;"	d
+DEF_DBG_Q1_FRM_SUCCESS	include/ssv6200_reg.h	9260;"	d
+DEF_DBG_Q1_FRM_SUCCESS	smac/hal/ssv6006c/ssv6006C_reg.h	16841;"	d
+DEF_DBG_Q2_ACK_FAIL	include/ssv6200_reg.h	9267;"	d
+DEF_DBG_Q2_ACK_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	16848;"	d
+DEF_DBG_Q2_ACK_SUCCESS	include/ssv6200_reg.h	9266;"	d
+DEF_DBG_Q2_ACK_SUCCESS	smac/hal/ssv6006c/ssv6006C_reg.h	16847;"	d
+DEF_DBG_Q2_FRM_FAIL	include/ssv6200_reg.h	9265;"	d
+DEF_DBG_Q2_FRM_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	16846;"	d
+DEF_DBG_Q2_FRM_SUCCESS	include/ssv6200_reg.h	9264;"	d
+DEF_DBG_Q2_FRM_SUCCESS	smac/hal/ssv6006c/ssv6006C_reg.h	16845;"	d
+DEF_DBG_Q3_ACK_FAIL	include/ssv6200_reg.h	9271;"	d
+DEF_DBG_Q3_ACK_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	16852;"	d
+DEF_DBG_Q3_ACK_SUCCESS	include/ssv6200_reg.h	9270;"	d
+DEF_DBG_Q3_ACK_SUCCESS	smac/hal/ssv6006c/ssv6006C_reg.h	16851;"	d
+DEF_DBG_Q3_FRM_FAIL	include/ssv6200_reg.h	9269;"	d
+DEF_DBG_Q3_FRM_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	16850;"	d
+DEF_DBG_Q3_FRM_SUCCESS	include/ssv6200_reg.h	9268;"	d
+DEF_DBG_Q3_FRM_SUCCESS	smac/hal/ssv6006c/ssv6006C_reg.h	16849;"	d
+DEF_DBG_RX_QUOTA	include/ssv6200_reg.h	8803;"	d
+DEF_DBG_SPI_MODE	include/ssv6200_reg.h	8802;"	d
+DEF_DBG_SPI_STS	include/ssv6200_reg.h	8810;"	d
+DEF_DBG_SPI_TO_PHY_PARAM1	include/ssv6200_reg.h	8808;"	d
+DEF_DBG_SPI_TO_PHY_PARAM2	include/ssv6200_reg.h	8809;"	d
+DEF_DBG_TX_ALLOC	include/ssv6200_reg.h	8812;"	d
+DEF_DBG_TX_ALLOC_SET	include/ssv6200_reg.h	8811;"	d
+DEF_DBG_TX_SEG	include/ssv6200_reg.h	8806;"	d
+DEF_DBG_WFF_FULL	include/ssv6200_reg.h	9017;"	d
+DEF_DBG_WFF_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	16543;"	d
+DEF_DCOC_IDAC_REGISTER1	include/ssv6200_reg.h	9636;"	d
+DEF_DCOC_IDAC_REGISTER2	include/ssv6200_reg.h	9637;"	d
+DEF_DCOC_IDAC_REGISTER3	include/ssv6200_reg.h	9638;"	d
+DEF_DCOC_IDAC_REGISTER4	include/ssv6200_reg.h	9639;"	d
+DEF_DCOC_IDAC_REGISTER5	include/ssv6200_reg.h	9640;"	d
+DEF_DCOC_IDAC_REGISTER6	include/ssv6200_reg.h	9641;"	d
+DEF_DCOC_IDAC_REGISTER7	include/ssv6200_reg.h	9642;"	d
+DEF_DCOC_IDAC_REGISTER8	include/ssv6200_reg.h	9643;"	d
+DEF_DEBUG_BURST_MODE	include/ssv6200_reg.h	8748;"	d
+DEF_DEBUG_CTL	include/ssv6200_reg.h	9659;"	d
+DEF_DEBUG_FIRMWARE_EVENT_FLAG	smac/hal/ssv6006c/ssv6006C_reg.h	16104;"	d
+DEF_DEBUG_HOST_EVENT_FLAG	smac/hal/ssv6006c/ssv6006C_reg.h	16105;"	d
+DEF_DEBUG_OUT	include/ssv6200_reg.h	9660;"	d
+DEF_DEBUG_SIM_FINISH	smac/hal/ssv6006c/ssv6006C_reg.h	16121;"	d
+DEF_DESIGN_FOR_TEST	smac/hal/ssv6006c/ssv6006C_reg.h	16136;"	d
+DEF_DESIGN_FOR_TEST_ASSERTION	smac/hal/ssv6006c/ssv6006C_reg.h	16129;"	d
+DEF_DIGITAL_ADD_ON_0	smac/hal/ssv6006c/ssv6006C_reg.h	17487;"	d
+DEF_DIGITAL_ADD_ON_1	smac/hal/ssv6006c/ssv6006C_reg.h	17488;"	d
+DEF_DIGITAL_ADD_ON_2	smac/hal/ssv6006c/ssv6006C_reg.h	17489;"	d
+DEF_DIGITAL_ADD_ON_3	smac/hal/ssv6006c/ssv6006C_reg.h	17490;"	d
+DEF_DIGITAL_ADD_ON_4	smac/hal/ssv6006c/ssv6006C_reg.h	17491;"	d
+DEF_DIGITAL_ADD_ON_5	smac/hal/ssv6006c/ssv6006C_reg.h	17492;"	d
+DEF_DIGITAL_ADD_ON_6	smac/hal/ssv6006c/ssv6006C_reg.h	17493;"	d
+DEF_DMA_ADR_DST	include/ssv6200_reg.h	8830;"	d
+DEF_DMA_ADR_DST	smac/hal/ssv6006c/ssv6006C_reg.h	16318;"	d
+DEF_DMA_ADR_SRC	include/ssv6200_reg.h	8829;"	d
+DEF_DMA_ADR_SRC	smac/hal/ssv6006c/ssv6006C_reg.h	16317;"	d
+DEF_DMA_CLR	include/ssv6200_reg.h	8897;"	d
+DEF_DMA_CLR	smac/hal/ssv6006c/ssv6006C_reg.h	16461;"	d
+DEF_DMA_CTRL	include/ssv6200_reg.h	8831;"	d
+DEF_DMA_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	16319;"	d
+DEF_DMA_FILL_CONST	include/ssv6200_reg.h	8833;"	d
+DEF_DMA_FILL_CONST	smac/hal/ssv6006c/ssv6006C_reg.h	16321;"	d
+DEF_DMA_INT	include/ssv6200_reg.h	8832;"	d
+DEF_DMA_INT	smac/hal/ssv6006c/ssv6006C_reg.h	16320;"	d
+DEF_DMA_LEN	include/ssv6200_reg.h	8896;"	d
+DEF_DMA_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	16460;"	d
+DEF_DMA_RDATA	include/ssv6200_reg.h	8894;"	d
+DEF_DMA_RDATA	smac/hal/ssv6006c/ssv6006C_reg.h	16458;"	d
+DEF_DMA_WDATA	include/ssv6200_reg.h	8895;"	d
+DEF_DMA_WDATA	smac/hal/ssv6006c/ssv6006C_reg.h	16459;"	d
+DEF_DMN_IDTBL_0_STATUS	include/ssv6200_reg.h	9673;"	d
+DEF_DMN_IDTBL_1_STATUS	include/ssv6200_reg.h	9674;"	d
+DEF_DMN_IDTBL_2_STATUS	include/ssv6200_reg.h	9675;"	d
+DEF_DMN_IDTBL_3_STATUS	include/ssv6200_reg.h	9676;"	d
+DEF_DMN_MCU_STATUS	include/ssv6200_reg.h	9664;"	d
+DEF_DMN_READ_BYPASS	include/ssv6200_reg.h	9657;"	d
+DEF_DMN_STATUS	include/ssv6200_reg.h	9662;"	d
+DEF_DMN_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	17978;"	d
+DEF_DPD_CONTROL	include/ssv6200_reg.h	9580;"	d
+DEF_DPD_GAIN_ESTIMATION_0	include/ssv6200_reg.h	9607;"	d
+DEF_DPD_GAIN_ESTIMATION_1	include/ssv6200_reg.h	9608;"	d
+DEF_DPD_GAIN_ESTIMATION_2	include/ssv6200_reg.h	9609;"	d
+DEF_DPD_GAIN_TABLE_0	include/ssv6200_reg.h	9581;"	d
+DEF_DPD_GAIN_TABLE_1	include/ssv6200_reg.h	9582;"	d
+DEF_DPD_GAIN_TABLE_2	include/ssv6200_reg.h	9583;"	d
+DEF_DPD_GAIN_TABLE_3	include/ssv6200_reg.h	9584;"	d
+DEF_DPD_GAIN_TABLE_4	include/ssv6200_reg.h	9585;"	d
+DEF_DPD_GAIN_TABLE_5	include/ssv6200_reg.h	9586;"	d
+DEF_DPD_GAIN_TABLE_6	include/ssv6200_reg.h	9587;"	d
+DEF_DPD_GAIN_TABLE_7	include/ssv6200_reg.h	9588;"	d
+DEF_DPD_GAIN_TABLE_8	include/ssv6200_reg.h	9589;"	d
+DEF_DPD_GAIN_TABLE_9	include/ssv6200_reg.h	9590;"	d
+DEF_DPD_GAIN_TABLE_A	include/ssv6200_reg.h	9591;"	d
+DEF_DPD_GAIN_TABLE_B	include/ssv6200_reg.h	9592;"	d
+DEF_DPD_GAIN_TABLE_C	include/ssv6200_reg.h	9593;"	d
+DEF_DPD_PH_TABLE_0	include/ssv6200_reg.h	9594;"	d
+DEF_DPD_PH_TABLE_1	include/ssv6200_reg.h	9595;"	d
+DEF_DPD_PH_TABLE_2	include/ssv6200_reg.h	9596;"	d
+DEF_DPD_PH_TABLE_3	include/ssv6200_reg.h	9597;"	d
+DEF_DPD_PH_TABLE_4	include/ssv6200_reg.h	9598;"	d
+DEF_DPD_PH_TABLE_5	include/ssv6200_reg.h	9599;"	d
+DEF_DPD_PH_TABLE_6	include/ssv6200_reg.h	9600;"	d
+DEF_DPD_PH_TABLE_7	include/ssv6200_reg.h	9601;"	d
+DEF_DPD_PH_TABLE_8	include/ssv6200_reg.h	9602;"	d
+DEF_DPD_PH_TABLE_9	include/ssv6200_reg.h	9603;"	d
+DEF_DPD_PH_TABLE_A	include/ssv6200_reg.h	9604;"	d
+DEF_DPD_PH_TABLE_B	include/ssv6200_reg.h	9605;"	d
+DEF_DPD_PH_TABLE_C	include/ssv6200_reg.h	9606;"	d
+DEF_DPLL_CP_PFD_REGISTER	include/ssv6200_reg.h	9634;"	d
+DEF_DPLL_DIVIDER_REGISTER	include/ssv6200_reg.h	9635;"	d
+DEF_DPLL_FB_DIVIDER_REGISTERS_II	include/ssv6200_reg.h	9648;"	d
+DEF_DPLL_VCO_REGISTER	include/ssv6200_reg.h	9633;"	d
+DEF_DUAL_IDX_EXTEND	smac/hal/ssv6006c/ssv6006C_reg.h	16567;"	d
+DEF_EFUSE_AHB_RDATA_0	include/ssv6200_reg.h	8905;"	d
+DEF_EFUSE_AHB_RDATA_1	include/ssv6200_reg.h	8907;"	d
+DEF_EFUSE_AHB_RDATA_2	include/ssv6200_reg.h	8909;"	d
+DEF_EFUSE_AHB_RDATA_3	include/ssv6200_reg.h	8911;"	d
+DEF_EFUSE_AHB_RDATA_4	include/ssv6200_reg.h	8913;"	d
+DEF_EFUSE_AHB_RDATA_5	include/ssv6200_reg.h	8915;"	d
+DEF_EFUSE_AHB_RDATA_6	include/ssv6200_reg.h	8917;"	d
+DEF_EFUSE_AHB_RDATA_7	include/ssv6200_reg.h	8919;"	d
+DEF_EFUSE_CLK_FREQ	include/ssv6200_reg.h	8903;"	d
+DEF_EFUSE_CLK_FREQ	smac/hal/ssv6006c/ssv6006C_reg.h	16467;"	d
+DEF_EFUSE_LDO_TIME	include/ssv6200_reg.h	8904;"	d
+DEF_EFUSE_LDO_TIME	smac/hal/ssv6006c/ssv6006C_reg.h	16468;"	d
+DEF_EFUSE_RD_KICK	smac/hal/ssv6006c/ssv6006C_reg.h	16472;"	d
+DEF_EFUSE_SPI_BUSY	include/ssv6200_reg.h	8929;"	d
+DEF_EFUSE_SPI_RD0_EN	include/ssv6200_reg.h	8921;"	d
+DEF_EFUSE_SPI_RD1_EN	include/ssv6200_reg.h	8922;"	d
+DEF_EFUSE_SPI_RD2_EN	include/ssv6200_reg.h	8923;"	d
+DEF_EFUSE_SPI_RD3_EN	include/ssv6200_reg.h	8924;"	d
+DEF_EFUSE_SPI_RD4_EN	include/ssv6200_reg.h	8925;"	d
+DEF_EFUSE_SPI_RD5_EN	include/ssv6200_reg.h	8926;"	d
+DEF_EFUSE_SPI_RD6_EN	include/ssv6200_reg.h	8927;"	d
+DEF_EFUSE_SPI_RD7_EN	include/ssv6200_reg.h	8928;"	d
+DEF_EFUSE_SPI_RDATA_0	include/ssv6200_reg.h	8930;"	d
+DEF_EFUSE_SPI_RDATA_1	include/ssv6200_reg.h	8931;"	d
+DEF_EFUSE_SPI_RDATA_2	include/ssv6200_reg.h	8932;"	d
+DEF_EFUSE_SPI_RDATA_3	include/ssv6200_reg.h	8933;"	d
+DEF_EFUSE_SPI_RDATA_4	include/ssv6200_reg.h	8934;"	d
+DEF_EFUSE_SPI_RDATA_5	include/ssv6200_reg.h	8935;"	d
+DEF_EFUSE_SPI_RDATA_6	include/ssv6200_reg.h	8936;"	d
+DEF_EFUSE_SPI_RDATA_7	include/ssv6200_reg.h	8937;"	d
+DEF_EFUSE_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	16469;"	d
+DEF_EFUSE_STATUS2	smac/hal/ssv6006c/ssv6006C_reg.h	16470;"	d
+DEF_EFUSE_VDDQ_EN	smac/hal/ssv6006c/ssv6006C_reg.h	16473;"	d
+DEF_EFUSE_WDATA_0	include/ssv6200_reg.h	8906;"	d
+DEF_EFUSE_WDATA_0_0	smac/hal/ssv6006c/ssv6006C_reg.h	16474;"	d
+DEF_EFUSE_WDATA_0_1	smac/hal/ssv6006c/ssv6006C_reg.h	16475;"	d
+DEF_EFUSE_WDATA_0_2	smac/hal/ssv6006c/ssv6006C_reg.h	16476;"	d
+DEF_EFUSE_WDATA_0_3	smac/hal/ssv6006c/ssv6006C_reg.h	16477;"	d
+DEF_EFUSE_WDATA_0_4	smac/hal/ssv6006c/ssv6006C_reg.h	16478;"	d
+DEF_EFUSE_WDATA_0_5	smac/hal/ssv6006c/ssv6006C_reg.h	16479;"	d
+DEF_EFUSE_WDATA_0_6	smac/hal/ssv6006c/ssv6006C_reg.h	16480;"	d
+DEF_EFUSE_WDATA_0_7	smac/hal/ssv6006c/ssv6006C_reg.h	16481;"	d
+DEF_EFUSE_WDATA_1	include/ssv6200_reg.h	8908;"	d
+DEF_EFUSE_WDATA_2	include/ssv6200_reg.h	8910;"	d
+DEF_EFUSE_WDATA_3	include/ssv6200_reg.h	8912;"	d
+DEF_EFUSE_WDATA_4	include/ssv6200_reg.h	8914;"	d
+DEF_EFUSE_WDATA_5	include/ssv6200_reg.h	8916;"	d
+DEF_EFUSE_WDATA_6	include/ssv6200_reg.h	8918;"	d
+DEF_EFUSE_WDATA_7	include/ssv6200_reg.h	8920;"	d
+DEF_EFUSE_WR_KICK	smac/hal/ssv6006c/ssv6006C_reg.h	16471;"	d
+DEF_ENG_SOFTWARE_RESET	include/ssv6200_reg.h	9205;"	d
+DEF_ENG_SOFTWARE_RESET	smac/hal/ssv6006c/ssv6006C_reg.h	16779;"	d
+DEF_F0_CIS_CONTENT_REG_0	include/ssv6200_reg.h	8711;"	d
+DEF_F0_CIS_CONTENT_REG_0	smac/hal/ssv6006c/ssv6006C_reg.h	16215;"	d
+DEF_F0_CIS_CONTENT_REG_1	include/ssv6200_reg.h	8712;"	d
+DEF_F0_CIS_CONTENT_REG_1	smac/hal/ssv6006c/ssv6006C_reg.h	16216;"	d
+DEF_F0_CIS_CONTENT_REG_10	include/ssv6200_reg.h	8721;"	d
+DEF_F0_CIS_CONTENT_REG_10	smac/hal/ssv6006c/ssv6006C_reg.h	16225;"	d
+DEF_F0_CIS_CONTENT_REG_11	include/ssv6200_reg.h	8722;"	d
+DEF_F0_CIS_CONTENT_REG_11	smac/hal/ssv6006c/ssv6006C_reg.h	16226;"	d
+DEF_F0_CIS_CONTENT_REG_12	include/ssv6200_reg.h	8723;"	d
+DEF_F0_CIS_CONTENT_REG_12	smac/hal/ssv6006c/ssv6006C_reg.h	16227;"	d
+DEF_F0_CIS_CONTENT_REG_13	include/ssv6200_reg.h	8724;"	d
+DEF_F0_CIS_CONTENT_REG_13	smac/hal/ssv6006c/ssv6006C_reg.h	16228;"	d
+DEF_F0_CIS_CONTENT_REG_14	include/ssv6200_reg.h	8725;"	d
+DEF_F0_CIS_CONTENT_REG_14	smac/hal/ssv6006c/ssv6006C_reg.h	16229;"	d
+DEF_F0_CIS_CONTENT_REG_15	include/ssv6200_reg.h	8726;"	d
+DEF_F0_CIS_CONTENT_REG_15	smac/hal/ssv6006c/ssv6006C_reg.h	16230;"	d
+DEF_F0_CIS_CONTENT_REG_2	include/ssv6200_reg.h	8713;"	d
+DEF_F0_CIS_CONTENT_REG_2	smac/hal/ssv6006c/ssv6006C_reg.h	16217;"	d
+DEF_F0_CIS_CONTENT_REG_3	include/ssv6200_reg.h	8714;"	d
+DEF_F0_CIS_CONTENT_REG_3	smac/hal/ssv6006c/ssv6006C_reg.h	16218;"	d
+DEF_F0_CIS_CONTENT_REG_4	include/ssv6200_reg.h	8715;"	d
+DEF_F0_CIS_CONTENT_REG_4	smac/hal/ssv6006c/ssv6006C_reg.h	16219;"	d
+DEF_F0_CIS_CONTENT_REG_5	include/ssv6200_reg.h	8716;"	d
+DEF_F0_CIS_CONTENT_REG_5	smac/hal/ssv6006c/ssv6006C_reg.h	16220;"	d
+DEF_F0_CIS_CONTENT_REG_6	include/ssv6200_reg.h	8717;"	d
+DEF_F0_CIS_CONTENT_REG_6	smac/hal/ssv6006c/ssv6006C_reg.h	16221;"	d
+DEF_F0_CIS_CONTENT_REG_7	include/ssv6200_reg.h	8718;"	d
+DEF_F0_CIS_CONTENT_REG_7	smac/hal/ssv6006c/ssv6006C_reg.h	16222;"	d
+DEF_F0_CIS_CONTENT_REG_8	include/ssv6200_reg.h	8719;"	d
+DEF_F0_CIS_CONTENT_REG_8	smac/hal/ssv6006c/ssv6006C_reg.h	16223;"	d
+DEF_F0_CIS_CONTENT_REG_9	include/ssv6200_reg.h	8720;"	d
+DEF_F0_CIS_CONTENT_REG_9	smac/hal/ssv6006c/ssv6006C_reg.h	16224;"	d
+DEF_F1_BLOCK_SIZE_0_REG	include/ssv6200_reg.h	8701;"	d
+DEF_F1_CIS_CONTENT_REG_0	include/ssv6200_reg.h	8727;"	d
+DEF_F1_CIS_CONTENT_REG_0	smac/hal/ssv6006c/ssv6006C_reg.h	16231;"	d
+DEF_F1_CIS_CONTENT_REG_1	include/ssv6200_reg.h	8728;"	d
+DEF_F1_CIS_CONTENT_REG_1	smac/hal/ssv6006c/ssv6006C_reg.h	16232;"	d
+DEF_F1_CIS_CONTENT_REG_10	include/ssv6200_reg.h	8737;"	d
+DEF_F1_CIS_CONTENT_REG_10	smac/hal/ssv6006c/ssv6006C_reg.h	16241;"	d
+DEF_F1_CIS_CONTENT_REG_11	include/ssv6200_reg.h	8738;"	d
+DEF_F1_CIS_CONTENT_REG_11	smac/hal/ssv6006c/ssv6006C_reg.h	16242;"	d
+DEF_F1_CIS_CONTENT_REG_12	include/ssv6200_reg.h	8739;"	d
+DEF_F1_CIS_CONTENT_REG_12	smac/hal/ssv6006c/ssv6006C_reg.h	16243;"	d
+DEF_F1_CIS_CONTENT_REG_13	include/ssv6200_reg.h	8740;"	d
+DEF_F1_CIS_CONTENT_REG_13	smac/hal/ssv6006c/ssv6006C_reg.h	16244;"	d
+DEF_F1_CIS_CONTENT_REG_14	include/ssv6200_reg.h	8741;"	d
+DEF_F1_CIS_CONTENT_REG_14	smac/hal/ssv6006c/ssv6006C_reg.h	16245;"	d
+DEF_F1_CIS_CONTENT_REG_15	include/ssv6200_reg.h	8742;"	d
+DEF_F1_CIS_CONTENT_REG_15	smac/hal/ssv6006c/ssv6006C_reg.h	16246;"	d
+DEF_F1_CIS_CONTENT_REG_2	include/ssv6200_reg.h	8729;"	d
+DEF_F1_CIS_CONTENT_REG_2	smac/hal/ssv6006c/ssv6006C_reg.h	16233;"	d
+DEF_F1_CIS_CONTENT_REG_3	include/ssv6200_reg.h	8730;"	d
+DEF_F1_CIS_CONTENT_REG_3	smac/hal/ssv6006c/ssv6006C_reg.h	16234;"	d
+DEF_F1_CIS_CONTENT_REG_4	include/ssv6200_reg.h	8731;"	d
+DEF_F1_CIS_CONTENT_REG_4	smac/hal/ssv6006c/ssv6006C_reg.h	16235;"	d
+DEF_F1_CIS_CONTENT_REG_5	include/ssv6200_reg.h	8732;"	d
+DEF_F1_CIS_CONTENT_REG_5	smac/hal/ssv6006c/ssv6006C_reg.h	16236;"	d
+DEF_F1_CIS_CONTENT_REG_6	include/ssv6200_reg.h	8733;"	d
+DEF_F1_CIS_CONTENT_REG_6	smac/hal/ssv6006c/ssv6006C_reg.h	16237;"	d
+DEF_F1_CIS_CONTENT_REG_7	include/ssv6200_reg.h	8734;"	d
+DEF_F1_CIS_CONTENT_REG_7	smac/hal/ssv6006c/ssv6006C_reg.h	16238;"	d
+DEF_F1_CIS_CONTENT_REG_8	include/ssv6200_reg.h	8735;"	d
+DEF_F1_CIS_CONTENT_REG_8	smac/hal/ssv6006c/ssv6006C_reg.h	16239;"	d
+DEF_F1_CIS_CONTENT_REG_9	include/ssv6200_reg.h	8736;"	d
+DEF_F1_CIS_CONTENT_REG_9	smac/hal/ssv6006c/ssv6006C_reg.h	16240;"	d
+DEF_FBR_100H_REG	include/ssv6200_reg.h	8709;"	d
+DEF_FBR_100H_REG	smac/hal/ssv6006c/ssv6006C_reg.h	16213;"	d
+DEF_FBR_109H_REG	include/ssv6200_reg.h	8710;"	d
+DEF_FBR_109H_REG	smac/hal/ssv6006c/ssv6006C_reg.h	16214;"	d
+DEF_FBUS_CFG0_1	smac/hal/ssv6006c/ssv6006C_reg.h	15980;"	d
+DEF_FBUS_CFG0_2	smac/hal/ssv6006c/ssv6006C_reg.h	15981;"	d
+DEF_FBUS_CFG1_1	smac/hal/ssv6006c/ssv6006C_reg.h	15986;"	d
+DEF_FBUS_CFG1_2	smac/hal/ssv6006c/ssv6006C_reg.h	15987;"	d
+DEF_FBUS_CH_EN	smac/hal/ssv6006c/ssv6006C_reg.h	16001;"	d
+DEF_FBUS_CLK_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	16093;"	d
+DEF_FBUS_CLRERR	smac/hal/ssv6006c/ssv6006C_reg.h	15995;"	d
+DEF_FBUS_CLRTR	smac/hal/ssv6006c/ssv6006C_reg.h	15994;"	d
+DEF_FBUS_CTL0_1	smac/hal/ssv6006c/ssv6006C_reg.h	15978;"	d
+DEF_FBUS_CTL0_2	smac/hal/ssv6006c/ssv6006C_reg.h	15979;"	d
+DEF_FBUS_CTL1_1	smac/hal/ssv6006c/ssv6006C_reg.h	15984;"	d
+DEF_FBUS_CTL1_2	smac/hal/ssv6006c/ssv6006C_reg.h	15985;"	d
+DEF_FBUS_DAR0	smac/hal/ssv6006c/ssv6006C_reg.h	15977;"	d
+DEF_FBUS_DAR1	smac/hal/ssv6006c/ssv6006C_reg.h	15983;"	d
+DEF_FBUS_DMA_EN	smac/hal/ssv6006c/ssv6006C_reg.h	16000;"	d
+DEF_FBUS_MASKERR	smac/hal/ssv6006c/ssv6006C_reg.h	15993;"	d
+DEF_FBUS_MASKTR	smac/hal/ssv6006c/ssv6006C_reg.h	15992;"	d
+DEF_FBUS_RAWERR	smac/hal/ssv6006c/ssv6006C_reg.h	15989;"	d
+DEF_FBUS_RAWTR	smac/hal/ssv6006c/ssv6006C_reg.h	15988;"	d
+DEF_FBUS_SAR0	smac/hal/ssv6006c/ssv6006C_reg.h	15976;"	d
+DEF_FBUS_SAR1	smac/hal/ssv6006c/ssv6006C_reg.h	15982;"	d
+DEF_FBUS_SHS_DST_REQ_CFG	smac/hal/ssv6006c/ssv6006C_reg.h	15997;"	d
+DEF_FBUS_SHS_DST_SREQ_CFG	smac/hal/ssv6006c/ssv6006C_reg.h	15999;"	d
+DEF_FBUS_SHS_SRC_REQ_CFG	smac/hal/ssv6006c/ssv6006C_reg.h	15996;"	d
+DEF_FBUS_SHS_SRC_SREQ_CFG	smac/hal/ssv6006c/ssv6006C_reg.h	15998;"	d
+DEF_FBUS_STATUSERR	smac/hal/ssv6006c/ssv6006C_reg.h	15991;"	d
+DEF_FBUS_STATUSTR	smac/hal/ssv6006c/ssv6006C_reg.h	15990;"	d
+DEF_FENCE_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	16098;"	d
+DEF_FENCE_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	16099;"	d
+DEF_FIFO_PTR_READ_BLOCK_CNT	include/ssv6200_reg.h	8697;"	d
+DEF_FLASH_ADDR	include/ssv6200_reg.h	8820;"	d
+DEF_FLASH_IO0_DLY	smac/hal/ssv6006c/ssv6006C_reg.h	16312;"	d
+DEF_FLASH_IO1_DLY	smac/hal/ssv6006c/ssv6006C_reg.h	16313;"	d
+DEF_FN1_DMA_RD_START_ADDR_REG	smac/hal/ssv6006c/ssv6006C_reg.h	16207;"	d
+DEF_FN1_DMA_START_ADDR_REG	include/ssv6200_reg.h	8690;"	d
+DEF_FN1_DMA_START_ADDR_REG	smac/hal/ssv6006c/ssv6006C_reg.h	16204;"	d
+DEF_FN1_INT_CTRL_RESET	include/ssv6200_reg.h	8691;"	d
+DEF_FN1_INT_CTRL_RESET	smac/hal/ssv6006c/ssv6006C_reg.h	16205;"	d
+DEF_FN1_STATUS_REG	include/ssv6200_reg.h	8673;"	d
+DEF_FN1_STATUS_REG	smac/hal/ssv6006c/ssv6006C_reg.h	16197;"	d
+DEF_FORCE_RX_AGGREGATION_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	16445;"	d
+DEF_FPGA_GEMINIARF_SWITCH	smac/hal/ssv6006c/ssv6006C_reg.h	17989;"	d
+DEF_FRAME_TYPE_CNTR_SET	include/ssv6200_reg.h	9052;"	d
+DEF_FRAME_TYPE_CNTR_SET	smac/hal/ssv6006c/ssv6006C_reg.h	16563;"	d
+DEF_GEMINIA_3_WIRE_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	16978;"	d
+DEF_GEMINIA_BT_DCOC_IDAC_REGISTER1	smac/hal/ssv6006c/ssv6006C_reg.h	17036;"	d
+DEF_GEMINIA_BT_DCOC_IDAC_REGISTER10	smac/hal/ssv6006c/ssv6006C_reg.h	17045;"	d
+DEF_GEMINIA_BT_DCOC_IDAC_REGISTER11	smac/hal/ssv6006c/ssv6006C_reg.h	17046;"	d
+DEF_GEMINIA_BT_DCOC_IDAC_REGISTER12	smac/hal/ssv6006c/ssv6006C_reg.h	17047;"	d
+DEF_GEMINIA_BT_DCOC_IDAC_REGISTER13	smac/hal/ssv6006c/ssv6006C_reg.h	17048;"	d
+DEF_GEMINIA_BT_DCOC_IDAC_REGISTER14	smac/hal/ssv6006c/ssv6006C_reg.h	17049;"	d
+DEF_GEMINIA_BT_DCOC_IDAC_REGISTER15	smac/hal/ssv6006c/ssv6006C_reg.h	17050;"	d
+DEF_GEMINIA_BT_DCOC_IDAC_REGISTER16	smac/hal/ssv6006c/ssv6006C_reg.h	17051;"	d
+DEF_GEMINIA_BT_DCOC_IDAC_REGISTER2	smac/hal/ssv6006c/ssv6006C_reg.h	17037;"	d
+DEF_GEMINIA_BT_DCOC_IDAC_REGISTER3	smac/hal/ssv6006c/ssv6006C_reg.h	17038;"	d
+DEF_GEMINIA_BT_DCOC_IDAC_REGISTER4	smac/hal/ssv6006c/ssv6006C_reg.h	17039;"	d
+DEF_GEMINIA_BT_DCOC_IDAC_REGISTER5	smac/hal/ssv6006c/ssv6006C_reg.h	17040;"	d
+DEF_GEMINIA_BT_DCOC_IDAC_REGISTER6	smac/hal/ssv6006c/ssv6006C_reg.h	17041;"	d
+DEF_GEMINIA_BT_DCOC_IDAC_REGISTER7	smac/hal/ssv6006c/ssv6006C_reg.h	17042;"	d
+DEF_GEMINIA_BT_DCOC_IDAC_REGISTER8	smac/hal/ssv6006c/ssv6006C_reg.h	17043;"	d
+DEF_GEMINIA_BT_DCOC_IDAC_REGISTER9	smac/hal/ssv6006c/ssv6006C_reg.h	17044;"	d
+DEF_GEMINIA_BT_RX_FE_HG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	16992;"	d
+DEF_GEMINIA_BT_RX_FE_LG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	16994;"	d
+DEF_GEMINIA_BT_RX_FE_MG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	16993;"	d
+DEF_GEMINIA_BT_RX_FE_ULG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	16995;"	d
+DEF_GEMINIA_BT_RX_FILTER_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	16983;"	d
+DEF_GEMINIA_BT_TX_DAC_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	16998;"	d
+DEF_GEMINIA_CALIBRATION_GAIN_REGISTER0	smac/hal/ssv6006c/ssv6006C_reg.h	17056;"	d
+DEF_GEMINIA_CALIBRATION_GAIN_REGISTER1	smac/hal/ssv6006c/ssv6006C_reg.h	17057;"	d
+DEF_GEMINIA_CALIBRATION_TEST_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	16980;"	d
+DEF_GEMINIA_CALIBRATION_TIMER_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17055;"	d
+DEF_GEMINIA_DIGITAL_ADD_ON_R0	smac/hal/ssv6006c/ssv6006C_reg.h	17063;"	d
+DEF_GEMINIA_DIGITAL_ADD_ON_R1	smac/hal/ssv6006c/ssv6006C_reg.h	17064;"	d
+DEF_GEMINIA_DIGITAL_ADD_ON_R2	smac/hal/ssv6006c/ssv6006C_reg.h	17065;"	d
+DEF_GEMINIA_DIGITAL_ADD_ON_R3	smac/hal/ssv6006c/ssv6006C_reg.h	17066;"	d
+DEF_GEMINIA_DIGITAL_ADD_ON_R4	smac/hal/ssv6006c/ssv6006C_reg.h	17067;"	d
+DEF_GEMINIA_DIGITAL_ADD_ON_R5	smac/hal/ssv6006c/ssv6006C_reg.h	17068;"	d
+DEF_GEMINIA_DIGITAL_ADD_ON_R6	smac/hal/ssv6006c/ssv6006C_reg.h	17069;"	d
+DEF_GEMINIA_DPLL_CKT_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17012;"	d
+DEF_GEMINIA_DPLL_FB_DIVISION_REGISTERS	smac/hal/ssv6006c/ssv6006C_reg.h	17013;"	d
+DEF_GEMINIA_DPLL_TOP_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17011;"	d
+DEF_GEMINIA_IO_REG_0	smac/hal/ssv6006c/ssv6006C_reg.h	17093;"	d
+DEF_GEMINIA_IO_REG_1	smac/hal/ssv6006c/ssv6006C_reg.h	17094;"	d
+DEF_GEMINIA_IO_REG_2	smac/hal/ssv6006c/ssv6006C_reg.h	17095;"	d
+DEF_GEMINIA_LDO_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	16981;"	d
+DEF_GEMINIA_MANUAL_ENABLE_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	16979;"	d
+DEF_GEMINIA_MCU_REG_0	smac/hal/ssv6006c/ssv6006C_reg.h	17096;"	d
+DEF_GEMINIA_MODE_DECODER_TIMER_REGISTER1	smac/hal/ssv6006c/ssv6006C_reg.h	17052;"	d
+DEF_GEMINIA_PMU_BT_CLK	smac/hal/ssv6006c/ssv6006C_reg.h	17086;"	d
+DEF_GEMINIA_PMU_FDB_REG_0	smac/hal/ssv6006c/ssv6006C_reg.h	17092;"	d
+DEF_GEMINIA_PMU_RAM_00	smac/hal/ssv6006c/ssv6006C_reg.h	17097;"	d
+DEF_GEMINIA_PMU_RAM_01	smac/hal/ssv6006c/ssv6006C_reg.h	17098;"	d
+DEF_GEMINIA_PMU_RAM_02	smac/hal/ssv6006c/ssv6006C_reg.h	17099;"	d
+DEF_GEMINIA_PMU_RAM_03	smac/hal/ssv6006c/ssv6006C_reg.h	17100;"	d
+DEF_GEMINIA_PMU_RAM_04	smac/hal/ssv6006c/ssv6006C_reg.h	17101;"	d
+DEF_GEMINIA_PMU_RAM_05	smac/hal/ssv6006c/ssv6006C_reg.h	17102;"	d
+DEF_GEMINIA_PMU_RAM_06	smac/hal/ssv6006c/ssv6006C_reg.h	17103;"	d
+DEF_GEMINIA_PMU_RAM_07	smac/hal/ssv6006c/ssv6006C_reg.h	17104;"	d
+DEF_GEMINIA_PMU_RAM_08	smac/hal/ssv6006c/ssv6006C_reg.h	17105;"	d
+DEF_GEMINIA_PMU_RAM_09	smac/hal/ssv6006c/ssv6006C_reg.h	17106;"	d
+DEF_GEMINIA_PMU_RAM_10	smac/hal/ssv6006c/ssv6006C_reg.h	17107;"	d
+DEF_GEMINIA_PMU_RAM_11	smac/hal/ssv6006c/ssv6006C_reg.h	17108;"	d
+DEF_GEMINIA_PMU_RAM_12	smac/hal/ssv6006c/ssv6006C_reg.h	17109;"	d
+DEF_GEMINIA_PMU_RAM_13	smac/hal/ssv6006c/ssv6006C_reg.h	17110;"	d
+DEF_GEMINIA_PMU_RAM_14	smac/hal/ssv6006c/ssv6006C_reg.h	17111;"	d
+DEF_GEMINIA_PMU_RAM_15	smac/hal/ssv6006c/ssv6006C_reg.h	17112;"	d
+DEF_GEMINIA_PMU_RAM_16	smac/hal/ssv6006c/ssv6006C_reg.h	17113;"	d
+DEF_GEMINIA_PMU_RAM_17	smac/hal/ssv6006c/ssv6006C_reg.h	17114;"	d
+DEF_GEMINIA_PMU_RAM_18	smac/hal/ssv6006c/ssv6006C_reg.h	17115;"	d
+DEF_GEMINIA_PMU_RAM_19	smac/hal/ssv6006c/ssv6006C_reg.h	17116;"	d
+DEF_GEMINIA_PMU_RAM_20	smac/hal/ssv6006c/ssv6006C_reg.h	17117;"	d
+DEF_GEMINIA_PMU_RAM_21	smac/hal/ssv6006c/ssv6006C_reg.h	17118;"	d
+DEF_GEMINIA_PMU_RAM_22	smac/hal/ssv6006c/ssv6006C_reg.h	17119;"	d
+DEF_GEMINIA_PMU_RAM_23	smac/hal/ssv6006c/ssv6006C_reg.h	17120;"	d
+DEF_GEMINIA_PMU_RAM_24	smac/hal/ssv6006c/ssv6006C_reg.h	17121;"	d
+DEF_GEMINIA_PMU_RAM_25	smac/hal/ssv6006c/ssv6006C_reg.h	17122;"	d
+DEF_GEMINIA_PMU_RAM_26	smac/hal/ssv6006c/ssv6006C_reg.h	17123;"	d
+DEF_GEMINIA_PMU_RAM_27	smac/hal/ssv6006c/ssv6006C_reg.h	17124;"	d
+DEF_GEMINIA_PMU_RAM_28	smac/hal/ssv6006c/ssv6006C_reg.h	17125;"	d
+DEF_GEMINIA_PMU_RAM_29	smac/hal/ssv6006c/ssv6006C_reg.h	17126;"	d
+DEF_GEMINIA_PMU_RAM_30	smac/hal/ssv6006c/ssv6006C_reg.h	17127;"	d
+DEF_GEMINIA_PMU_RAM_31	smac/hal/ssv6006c/ssv6006C_reg.h	17128;"	d
+DEF_GEMINIA_PMU_REG_1	smac/hal/ssv6006c/ssv6006C_reg.h	17080;"	d
+DEF_GEMINIA_PMU_REG_2	smac/hal/ssv6006c/ssv6006C_reg.h	17081;"	d
+DEF_GEMINIA_PMU_REG_3	smac/hal/ssv6006c/ssv6006C_reg.h	17082;"	d
+DEF_GEMINIA_PMU_REG_4	smac/hal/ssv6006c/ssv6006C_reg.h	17083;"	d
+DEF_GEMINIA_PMU_REG_5	smac/hal/ssv6006c/ssv6006C_reg.h	17084;"	d
+DEF_GEMINIA_PMU_REG_6	smac/hal/ssv6006c/ssv6006C_reg.h	17085;"	d
+DEF_GEMINIA_PMU_RTC_REG_0	smac/hal/ssv6006c/ssv6006C_reg.h	17088;"	d
+DEF_GEMINIA_PMU_RTC_REG_1	smac/hal/ssv6006c/ssv6006C_reg.h	17089;"	d
+DEF_GEMINIA_PMU_RTC_REG_2	smac/hal/ssv6006c/ssv6006C_reg.h	17090;"	d
+DEF_GEMINIA_PMU_RTC_REG_3	smac/hal/ssv6006c/ssv6006C_reg.h	17091;"	d
+DEF_GEMINIA_PMU_SLEEP_REG	smac/hal/ssv6006c/ssv6006C_reg.h	17087;"	d
+DEF_GEMINIA_READ_ONLY_FLAGS_ADC	smac/hal/ssv6006c/ssv6006C_reg.h	17060;"	d
+DEF_GEMINIA_READ_ONLY_FLAGS_SX1	smac/hal/ssv6006c/ssv6006C_reg.h	17061;"	d
+DEF_GEMINIA_READ_ONLY_FLAGS_SX2	smac/hal/ssv6006c/ssv6006C_reg.h	17062;"	d
+DEF_GEMINIA_RF_D_CAL_TOP_R0	smac/hal/ssv6006c/ssv6006C_reg.h	17076;"	d
+DEF_GEMINIA_RF_D_CAL_TOP_R1	smac/hal/ssv6006c/ssv6006C_reg.h	17077;"	d
+DEF_GEMINIA_RF_D_CAL_TOP_R2	smac/hal/ssv6006c/ssv6006C_reg.h	17078;"	d
+DEF_GEMINIA_RF_D_CAL_TOP_R3	smac/hal/ssv6006c/ssv6006C_reg.h	17079;"	d
+DEF_GEMINIA_RX_ADC_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	16996;"	d
+DEF_GEMINIA_RX_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	16984;"	d
+DEF_GEMINIA_SX_DUMMY_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17059;"	d
+DEF_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER	smac/hal/ssv6006c/ssv6006C_reg.h	16999;"	d
+DEF_GEMINIA_SX_LDO_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17000;"	d
+DEF_GEMINIA_SYN_AAC	smac/hal/ssv6006c/ssv6006C_reg.h	17009;"	d
+DEF_GEMINIA_SYN_DIV_SDM	smac/hal/ssv6006c/ssv6006C_reg.h	17007;"	d
+DEF_GEMINIA_SYN_FRACTIONAL_AND_INTEGER_8BITS	smac/hal/ssv6006c/ssv6006C_reg.h	17001;"	d
+DEF_GEMINIA_SYN_LPF	smac/hal/ssv6006c/ssv6006C_reg.h	17004;"	d
+DEF_GEMINIA_SYN_PFD_CHP_	smac/hal/ssv6006c/ssv6006C_reg.h	17003;"	d
+DEF_GEMINIA_SYN_REGISTER_INT3BIT_CH_TABLE	smac/hal/ssv6006c/ssv6006C_reg.h	17002;"	d
+DEF_GEMINIA_SYN_SBCAL	smac/hal/ssv6006c/ssv6006C_reg.h	17008;"	d
+DEF_GEMINIA_SYN_TTL	smac/hal/ssv6006c/ssv6006C_reg.h	17010;"	d
+DEF_GEMINIA_SYN_VCO	smac/hal/ssv6006c/ssv6006C_reg.h	17005;"	d
+DEF_GEMINIA_SYN_VCOBF	smac/hal/ssv6006c/ssv6006C_reg.h	17006;"	d
+DEF_GEMINIA_TRX_DUMMY_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17058;"	d
+DEF_GEMINIA_TX_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	16987;"	d
+DEF_GEMINIA_TX_UP8X_COEF_R0	smac/hal/ssv6006c/ssv6006C_reg.h	17070;"	d
+DEF_GEMINIA_TX_UP8X_COEF_R1	smac/hal/ssv6006c/ssv6006C_reg.h	17071;"	d
+DEF_GEMINIA_TX_UP8X_COEF_R2	smac/hal/ssv6006c/ssv6006C_reg.h	17072;"	d
+DEF_GEMINIA_TX_UP8X_COEF_R3	smac/hal/ssv6006c/ssv6006C_reg.h	17073;"	d
+DEF_GEMINIA_TX_UP8X_COEF_R4	smac/hal/ssv6006c/ssv6006C_reg.h	17074;"	d
+DEF_GEMINIA_TX_UP8X_COEF_R5	smac/hal/ssv6006c/ssv6006C_reg.h	17075;"	d
+DEF_GEMINIA_WBT_TX_FE_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	16985;"	d
+DEF_GEMINIA_WBT_TX_PA_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	16986;"	d
+DEF_GEMINIA_WF_DCOC_IDAC_REGISTER1	smac/hal/ssv6006c/ssv6006C_reg.h	17014;"	d
+DEF_GEMINIA_WF_DCOC_IDAC_REGISTER10	smac/hal/ssv6006c/ssv6006C_reg.h	17023;"	d
+DEF_GEMINIA_WF_DCOC_IDAC_REGISTER11	smac/hal/ssv6006c/ssv6006C_reg.h	17024;"	d
+DEF_GEMINIA_WF_DCOC_IDAC_REGISTER12	smac/hal/ssv6006c/ssv6006C_reg.h	17025;"	d
+DEF_GEMINIA_WF_DCOC_IDAC_REGISTER13	smac/hal/ssv6006c/ssv6006C_reg.h	17026;"	d
+DEF_GEMINIA_WF_DCOC_IDAC_REGISTER14	smac/hal/ssv6006c/ssv6006C_reg.h	17027;"	d
+DEF_GEMINIA_WF_DCOC_IDAC_REGISTER15	smac/hal/ssv6006c/ssv6006C_reg.h	17028;"	d
+DEF_GEMINIA_WF_DCOC_IDAC_REGISTER16	smac/hal/ssv6006c/ssv6006C_reg.h	17029;"	d
+DEF_GEMINIA_WF_DCOC_IDAC_REGISTER17	smac/hal/ssv6006c/ssv6006C_reg.h	17030;"	d
+DEF_GEMINIA_WF_DCOC_IDAC_REGISTER18	smac/hal/ssv6006c/ssv6006C_reg.h	17031;"	d
+DEF_GEMINIA_WF_DCOC_IDAC_REGISTER19	smac/hal/ssv6006c/ssv6006C_reg.h	17032;"	d
+DEF_GEMINIA_WF_DCOC_IDAC_REGISTER2	smac/hal/ssv6006c/ssv6006C_reg.h	17015;"	d
+DEF_GEMINIA_WF_DCOC_IDAC_REGISTER20	smac/hal/ssv6006c/ssv6006C_reg.h	17033;"	d
+DEF_GEMINIA_WF_DCOC_IDAC_REGISTER21	smac/hal/ssv6006c/ssv6006C_reg.h	17034;"	d
+DEF_GEMINIA_WF_DCOC_IDAC_REGISTER22	smac/hal/ssv6006c/ssv6006C_reg.h	17035;"	d
+DEF_GEMINIA_WF_DCOC_IDAC_REGISTER3	smac/hal/ssv6006c/ssv6006C_reg.h	17016;"	d
+DEF_GEMINIA_WF_DCOC_IDAC_REGISTER4	smac/hal/ssv6006c/ssv6006C_reg.h	17017;"	d
+DEF_GEMINIA_WF_DCOC_IDAC_REGISTER5	smac/hal/ssv6006c/ssv6006C_reg.h	17018;"	d
+DEF_GEMINIA_WF_DCOC_IDAC_REGISTER6	smac/hal/ssv6006c/ssv6006C_reg.h	17019;"	d
+DEF_GEMINIA_WF_DCOC_IDAC_REGISTER7	smac/hal/ssv6006c/ssv6006C_reg.h	17020;"	d
+DEF_GEMINIA_WF_DCOC_IDAC_REGISTER8	smac/hal/ssv6006c/ssv6006C_reg.h	17021;"	d
+DEF_GEMINIA_WF_DCOC_IDAC_REGISTER9	smac/hal/ssv6006c/ssv6006C_reg.h	17022;"	d
+DEF_GEMINIA_WIFI_R2T_TIMER_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17054;"	d
+DEF_GEMINIA_WIFI_RX_FE_HG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	16988;"	d
+DEF_GEMINIA_WIFI_RX_FE_LG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	16990;"	d
+DEF_GEMINIA_WIFI_RX_FE_MG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	16989;"	d
+DEF_GEMINIA_WIFI_RX_FE_ULG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	16991;"	d
+DEF_GEMINIA_WIFI_RX_FILTER_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	16982;"	d
+DEF_GEMINIA_WIFI_T2R_TIMER_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17053;"	d
+DEF_GEMINIA_WIFI_TX_DAC_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	16997;"	d
+DEF_GETID	include/ssv6200_reg.h	9361;"	d
+DEF_GETID	smac/hal/ssv6006c/ssv6006C_reg.h	17943;"	d
+DEF_GLBLE_SET	include/ssv6200_reg.h	9210;"	d
+DEF_GLBLE_SET	smac/hal/ssv6006c/ssv6006C_reg.h	16784;"	d
+DEF_GLOBAL_SEQUENCE	include/ssv6200_reg.h	8854;"	d
+DEF_GLOBAL_SEQUENCE	smac/hal/ssv6006c/ssv6006C_reg.h	16402;"	d
+DEF_GPIO_INTERRUPT_BANK_00_TO_07	smac/hal/ssv6006c/ssv6006C_reg.h	16353;"	d
+DEF_GPIO_INTERRUPT_BANK_08_TO_15	smac/hal/ssv6006c/ssv6006C_reg.h	16354;"	d
+DEF_GPIO_INTERRUPT_BANK_16_TO_22	smac/hal/ssv6006c/ssv6006C_reg.h	16355;"	d
+DEF_GPIO_INTERRUPT_MODE_00_TO_07	smac/hal/ssv6006c/ssv6006C_reg.h	16356;"	d
+DEF_GPIO_INTERRUPT_MODE_08_TO_15	smac/hal/ssv6006c/ssv6006C_reg.h	16357;"	d
+DEF_GPIO_INTERRUPT_MODE_16_TO_22	smac/hal/ssv6006c/ssv6006C_reg.h	16358;"	d
+DEF_GPIO_IQ_LOG_STOP	smac/hal/ssv6006c/ssv6006C_reg.h	16088;"	d
+DEF_GROUP_WSID	smac/hal/ssv6006c/ssv6006C_reg.h	16561;"	d
+DEF_HARD_WIRE_PIN_REGISTER	include/ssv6200_reg.h	9611;"	d
+DEF_HBURST_LOCK	include/ssv6200_reg.h	8574;"	d
+DEF_HBURST_LOCK	smac/hal/ssv6006c/ssv6006C_reg.h	16097;"	d
+DEF_HBUSREQ_LOCK	include/ssv6200_reg.h	8573;"	d
+DEF_HBUSREQ_LOCK	smac/hal/ssv6006c/ssv6006C_reg.h	16096;"	d
+DEF_HCI_BULK_IN_TIME_OUT_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	16418;"	d
+DEF_HCI_FORCE_PRE_BULK_IN	smac/hal/ssv6006c/ssv6006C_reg.h	16417;"	d
+DEF_HCI_MANUAL_ALLOC	smac/hal/ssv6006c/ssv6006C_reg.h	16407;"	d
+DEF_HCI_MANUAL_ALLOC_ACTION	smac/hal/ssv6006c/ssv6006C_reg.h	16408;"	d
+DEF_HCI_MANUAL_ALLOC_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	16409;"	d
+DEF_HCI_REG_0X2C	smac/hal/ssv6006c/ssv6006C_reg.h	16403;"	d
+DEF_HCI_STATE_DEBUG_MODE_0	include/ssv6200_reg.h	8871;"	d
+DEF_HCI_STATE_DEBUG_MODE_0	smac/hal/ssv6006c/ssv6006C_reg.h	16419;"	d
+DEF_HCI_STATE_DEBUG_MODE_1	include/ssv6200_reg.h	8872;"	d
+DEF_HCI_STATE_DEBUG_MODE_10	include/ssv6200_reg.h	8881;"	d
+DEF_HCI_STATE_DEBUG_MODE_2	include/ssv6200_reg.h	8873;"	d
+DEF_HCI_STATE_DEBUG_MODE_2	smac/hal/ssv6006c/ssv6006C_reg.h	16420;"	d
+DEF_HCI_STATE_DEBUG_MODE_3	include/ssv6200_reg.h	8874;"	d
+DEF_HCI_STATE_DEBUG_MODE_3	smac/hal/ssv6006c/ssv6006C_reg.h	16421;"	d
+DEF_HCI_STATE_DEBUG_MODE_4	include/ssv6200_reg.h	8875;"	d
+DEF_HCI_STATE_DEBUG_MODE_4	smac/hal/ssv6006c/ssv6006C_reg.h	16422;"	d
+DEF_HCI_STATE_DEBUG_MODE_5	include/ssv6200_reg.h	8876;"	d
+DEF_HCI_STATE_DEBUG_MODE_5	smac/hal/ssv6006c/ssv6006C_reg.h	16423;"	d
+DEF_HCI_STATE_DEBUG_MODE_6	include/ssv6200_reg.h	8877;"	d
+DEF_HCI_STATE_DEBUG_MODE_6	smac/hal/ssv6006c/ssv6006C_reg.h	16424;"	d
+DEF_HCI_STATE_DEBUG_MODE_7	include/ssv6200_reg.h	8878;"	d
+DEF_HCI_STATE_DEBUG_MODE_7	smac/hal/ssv6006c/ssv6006C_reg.h	16425;"	d
+DEF_HCI_STATE_DEBUG_MODE_8	include/ssv6200_reg.h	8879;"	d
+DEF_HCI_STATE_DEBUG_MODE_9	include/ssv6200_reg.h	8880;"	d
+DEF_HCI_TO_PKTBUF_SETTING	smac/hal/ssv6006c/ssv6006C_reg.h	16406;"	d
+DEF_HCI_TRX_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	16394;"	d
+DEF_HCI_TX_ALLOC_SPENDING_TIME	smac/hal/ssv6006c/ssv6006C_reg.h	16428;"	d
+DEF_HCI_TX_ALLOC_SUCCESS_COUNT	smac/hal/ssv6006c/ssv6006C_reg.h	16427;"	d
+DEF_HCI_TX_INFO_CLEAR	include/ssv6200_reg.h	8856;"	d
+DEF_HCI_TX_INFO_CLEAR	smac/hal/ssv6006c/ssv6006C_reg.h	16405;"	d
+DEF_HCI_TX_ON_DEMAND_LENGTH	smac/hal/ssv6006c/ssv6006C_reg.h	16426;"	d
+DEF_HCI_TX_RX_INFO_SIZE	include/ssv6200_reg.h	8855;"	d
+DEF_HCI_TX_RX_INFO_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	16404;"	d
+DEF_HDR_ADDR_SEL	include/ssv6200_reg.h	9051;"	d
+DEF_HDR_ADDR_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	16562;"	d
+DEF_HIGH_PRIORITY_FRM_HW_ID	smac/hal/ssv6006c/ssv6006C_reg.h	16566;"	d
+DEF_HOST_PATH	include/ssv6200_reg.h	8746;"	d
+DEF_HOST_WAKE_WIFI_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	16127;"	d
+DEF_HS3W_CTRL1	smac/hal/ssv6006c/ssv6006C_reg.h	17510;"	d
+DEF_HS3W_CTRL2	smac/hal/ssv6006c/ssv6006C_reg.h	17511;"	d
+DEF_HS3W_CTRL3	smac/hal/ssv6006c/ssv6006C_reg.h	17512;"	d
+DEF_HS3W_READ_OUT_1	smac/hal/ssv6006c/ssv6006C_reg.h	17514;"	d
+DEF_HS3W_READ_OUT_2_	smac/hal/ssv6006c/ssv6006C_reg.h	17515;"	d
+DEF_HS3W_READ_OUT_3	smac/hal/ssv6006c/ssv6006C_reg.h	17516;"	d
+DEF_HS5W_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	17668;"	d
+DEF_HS5W_MAN_SET_ADD0	smac/hal/ssv6006c/ssv6006C_reg.h	17669;"	d
+DEF_HS5W_MAN_SET_ADD1	smac/hal/ssv6006c/ssv6006C_reg.h	17670;"	d
+DEF_HS5W_MAN_SET_ADD2	smac/hal/ssv6006c/ssv6006C_reg.h	17671;"	d
+DEF_HS5W_MAN_SET_ADD3	smac/hal/ssv6006c/ssv6006C_reg.h	17672;"	d
+DEF_HS5W_MAN_SET_ADD4_CH	smac/hal/ssv6006c/ssv6006C_reg.h	17673;"	d
+DEF_HS5W_MAN_SET_ADD4_CH_5GB	smac/hal/ssv6006c/ssv6006C_reg.h	17674;"	d
+DEF_HS5W_MAN_SET_ADD4_F	smac/hal/ssv6006c/ssv6006C_reg.h	17675;"	d
+DEF_HS5W_MAN_SET_ADD4_F_5GB	smac/hal/ssv6006c/ssv6006C_reg.h	17676;"	d
+DEF_HS5W_MAN_SET_ADD5	smac/hal/ssv6006c/ssv6006C_reg.h	17677;"	d
+DEF_HS5W_MAN_SET_ADD5_5GB	smac/hal/ssv6006c/ssv6006C_reg.h	17678;"	d
+DEF_HS5W_MAN_SET_ADD6	smac/hal/ssv6006c/ssv6006C_reg.h	17679;"	d
+DEF_HS5W_MD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	17667;"	d
+DEF_HSUART_DIV_FRAC	smac/hal/ssv6006c/ssv6006C_reg.h	16294;"	d
+DEF_HSUART_DMA_RX_END_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	16297;"	d
+DEF_HSUART_DMA_RX_RPT	smac/hal/ssv6006c/ssv6006C_reg.h	16299;"	d
+DEF_HSUART_DMA_RX_STR_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	16296;"	d
+DEF_HSUART_DMA_RX_WPT	smac/hal/ssv6006c/ssv6006C_reg.h	16298;"	d
+DEF_HSUART_DMA_TX_END_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	16301;"	d
+DEF_HSUART_DMA_TX_RPT	smac/hal/ssv6006c/ssv6006C_reg.h	16303;"	d
+DEF_HSUART_DMA_TX_STR_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	16300;"	d
+DEF_HSUART_DMA_TX_WPT	smac/hal/ssv6006c/ssv6006C_reg.h	16302;"	d
+DEF_HSUART_EXPANSION_INTERRUPT_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	16295;"	d
+DEF_HSUART_FIFO_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	16286;"	d
+DEF_HSUART_FIFO_THRESHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	16292;"	d
+DEF_HSUART_INTERRUPT_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	16293;"	d
+DEF_HSUART_INTRRUPT_ENABLE	smac/hal/ssv6006c/ssv6006C_reg.h	16285;"	d
+DEF_HSUART_LINE_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	16287;"	d
+DEF_HSUART_LINE_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	16289;"	d
+DEF_HSUART_MODEM_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	16288;"	d
+DEF_HSUART_MODEM_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	16290;"	d
+DEF_HSUART_SCRATCH_BOARD	smac/hal/ssv6006c/ssv6006C_reg.h	16291;"	d
+DEF_HSUART_TRX_CHAR	smac/hal/ssv6006c/ssv6006C_reg.h	16284;"	d
+DEF_HS_CTRL	include/ssv6200_reg.h	9653;"	d
+DEF_I2CMST_CFG0	smac/hal/ssv6006c/ssv6006C_reg.h	16051;"	d
+DEF_I2CMST_ENABLE	smac/hal/ssv6006c/ssv6006C_reg.h	16061;"	d
+DEF_I2CMST_INT	smac/hal/ssv6006c/ssv6006C_reg.h	16056;"	d
+DEF_I2CMST_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	16057;"	d
+DEF_I2CMST_INT_STA	smac/hal/ssv6006c/ssv6006C_reg.h	16058;"	d
+DEF_I2CMST_RX_FIFO_TH	smac/hal/ssv6006c/ssv6006C_reg.h	16059;"	d
+DEF_I2CMST_SCLK_H_WIDTH	smac/hal/ssv6006c/ssv6006C_reg.h	16054;"	d
+DEF_I2CMST_SCLK_L_WIDTH	smac/hal/ssv6006c/ssv6006C_reg.h	16055;"	d
+DEF_I2CMST_TAR	smac/hal/ssv6006c/ssv6006C_reg.h	16052;"	d
+DEF_I2CMST_TRX_CMD_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	16053;"	d
+DEF_I2CMST_TX_FIFO_TH	smac/hal/ssv6006c/ssv6006C_reg.h	16060;"	d
+DEF_I2CM_DEV_A	include/ssv6200_reg.h	8760;"	d
+DEF_I2CM_DEV_A	smac/hal/ssv6006c/ssv6006C_reg.h	16265;"	d
+DEF_I2CM_EN	include/ssv6200_reg.h	8759;"	d
+DEF_I2CM_EN	smac/hal/ssv6006c/ssv6006C_reg.h	16264;"	d
+DEF_I2CM_EN_2	include/ssv6200_reg.h	8764;"	d
+DEF_I2CM_EN_2	smac/hal/ssv6006c/ssv6006C_reg.h	16269;"	d
+DEF_I2CM_LEN	include/ssv6200_reg.h	8761;"	d
+DEF_I2CM_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	16266;"	d
+DEF_I2CM_RDAT	include/ssv6200_reg.h	8763;"	d
+DEF_I2CM_RDAT	smac/hal/ssv6006c/ssv6006C_reg.h	16268;"	d
+DEF_I2CM_START_STOP_PERIOD	smac/hal/ssv6006c/ssv6006C_reg.h	16270;"	d
+DEF_I2CM_WDAT	include/ssv6200_reg.h	8762;"	d
+DEF_I2CM_WDAT	smac/hal/ssv6006c/ssv6006C_reg.h	16267;"	d
+DEF_I2CS_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	16193;"	d
+DEF_I2CS_ID_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	16189;"	d
+DEF_I2CS_STATE	smac/hal/ssv6006c/ssv6006C_reg.h	16192;"	d
+DEF_I2CS_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	16190;"	d
+DEF_I2CS_TIME_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	16191;"	d
+DEF_I2SMAS_CFG	smac/hal/ssv6006c/ssv6006C_reg.h	16095;"	d
+DEF_I2S_EN	smac/hal/ssv6006c/ssv6006C_reg.h	16028;"	d
+DEF_I2S_INTR	smac/hal/ssv6006c/ssv6006C_reg.h	16041;"	d
+DEF_I2S_INTR_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	16042;"	d
+DEF_I2S_RXFO	smac/hal/ssv6006c/ssv6006C_reg.h	16043;"	d
+DEF_I2S_RX_CH_EN	smac/hal/ssv6006c/ssv6006C_reg.h	16037;"	d
+DEF_I2S_RX_DMA	smac/hal/ssv6006c/ssv6006C_reg.h	16049;"	d
+DEF_I2S_RX_EN	smac/hal/ssv6006c/ssv6006C_reg.h	16029;"	d
+DEF_I2S_RX_FIFO_FLUSH	smac/hal/ssv6006c/ssv6006C_reg.h	16047;"	d
+DEF_I2S_RX_FIFO_TH	smac/hal/ssv6006c/ssv6006C_reg.h	16045;"	d
+DEF_I2S_RX_WORD_RES	smac/hal/ssv6006c/ssv6006C_reg.h	16039;"	d
+DEF_I2S_SCLK_SCR_EN	smac/hal/ssv6006c/ssv6006C_reg.h	16031;"	d
+DEF_I2S_TXFO	smac/hal/ssv6006c/ssv6006C_reg.h	16044;"	d
+DEF_I2S_TX_CH_EN	smac/hal/ssv6006c/ssv6006C_reg.h	16038;"	d
+DEF_I2S_TX_DMA	smac/hal/ssv6006c/ssv6006C_reg.h	16050;"	d
+DEF_I2S_TX_EN	smac/hal/ssv6006c/ssv6006C_reg.h	16030;"	d
+DEF_I2S_TX_FIFO_FLUSH	smac/hal/ssv6006c/ssv6006C_reg.h	16048;"	d
+DEF_I2S_TX_FIFO_TH	smac/hal/ssv6006c/ssv6006C_reg.h	16046;"	d
+DEF_I2S_TX_WORD_RES	smac/hal/ssv6006c/ssv6006C_reg.h	16040;"	d
+DEF_I2S_WS_DEF	smac/hal/ssv6006c/ssv6006C_reg.h	16032;"	d
+DEF_IC_TIME_TAG_0	include/ssv6200_reg.h	9200;"	d
+DEF_IC_TIME_TAG_1	include/ssv6200_reg.h	9201;"	d
+DEF_ID_ALC_FAIL1	include/ssv6200_reg.h	9281;"	d
+DEF_ID_ALC_FAIL1	smac/hal/ssv6006c/ssv6006C_reg.h	16862;"	d
+DEF_ID_ALC_FAIL2	include/ssv6200_reg.h	9282;"	d
+DEF_ID_ALC_FAIL2	smac/hal/ssv6006c/ssv6006C_reg.h	16863;"	d
+DEF_ID_INFO_STA	include/ssv6200_reg.h	9379;"	d
+DEF_ID_INFO_STA	smac/hal/ssv6006c/ssv6006C_reg.h	17961;"	d
+DEF_ID_IN_USE	include/ssv6200_reg.h	9033;"	d
+DEF_ID_IN_USE	smac/hal/ssv6006c/ssv6006C_reg.h	16559;"	d
+DEF_ID_LEN_THREADSHOLD1	include/ssv6200_reg.h	9375;"	d
+DEF_ID_LEN_THREADSHOLD1	smac/hal/ssv6006c/ssv6006C_reg.h	17957;"	d
+DEF_ID_LEN_THREADSHOLD2	include/ssv6200_reg.h	9376;"	d
+DEF_ID_LEN_THREADSHOLD2	smac/hal/ssv6006c/ssv6006C_reg.h	17958;"	d
+DEF_IMD_CFG	include/ssv6200_reg.h	9365;"	d
+DEF_IMD_CFG	smac/hal/ssv6006c/ssv6006C_reg.h	17947;"	d
+DEF_IMD_STA	include/ssv6200_reg.h	9366;"	d
+DEF_IMD_STA	smac/hal/ssv6006c/ssv6006C_reg.h	17948;"	d
+DEF_INFO0	include/ssv6200_reg.h	9157;"	d
+DEF_INFO1	include/ssv6200_reg.h	9158;"	d
+DEF_INFO10	include/ssv6200_reg.h	9167;"	d
+DEF_INFO11	include/ssv6200_reg.h	9168;"	d
+DEF_INFO12	include/ssv6200_reg.h	9169;"	d
+DEF_INFO13	include/ssv6200_reg.h	9170;"	d
+DEF_INFO14	include/ssv6200_reg.h	9171;"	d
+DEF_INFO15	include/ssv6200_reg.h	9172;"	d
+DEF_INFO16	include/ssv6200_reg.h	9173;"	d
+DEF_INFO17	include/ssv6200_reg.h	9174;"	d
+DEF_INFO18	include/ssv6200_reg.h	9175;"	d
+DEF_INFO19	include/ssv6200_reg.h	9176;"	d
+DEF_INFO2	include/ssv6200_reg.h	9159;"	d
+DEF_INFO20	include/ssv6200_reg.h	9177;"	d
+DEF_INFO21	include/ssv6200_reg.h	9178;"	d
+DEF_INFO22	include/ssv6200_reg.h	9179;"	d
+DEF_INFO23	include/ssv6200_reg.h	9180;"	d
+DEF_INFO24	include/ssv6200_reg.h	9181;"	d
+DEF_INFO25	include/ssv6200_reg.h	9182;"	d
+DEF_INFO26	include/ssv6200_reg.h	9183;"	d
+DEF_INFO27	include/ssv6200_reg.h	9184;"	d
+DEF_INFO28	include/ssv6200_reg.h	9185;"	d
+DEF_INFO29	include/ssv6200_reg.h	9186;"	d
+DEF_INFO3	include/ssv6200_reg.h	9160;"	d
+DEF_INFO30	include/ssv6200_reg.h	9187;"	d
+DEF_INFO31	include/ssv6200_reg.h	9188;"	d
+DEF_INFO32	include/ssv6200_reg.h	9189;"	d
+DEF_INFO33	include/ssv6200_reg.h	9190;"	d
+DEF_INFO34	include/ssv6200_reg.h	9191;"	d
+DEF_INFO35	include/ssv6200_reg.h	9192;"	d
+DEF_INFO36	include/ssv6200_reg.h	9193;"	d
+DEF_INFO37	include/ssv6200_reg.h	9194;"	d
+DEF_INFO38	include/ssv6200_reg.h	9195;"	d
+DEF_INFO4	include/ssv6200_reg.h	9161;"	d
+DEF_INFO5	include/ssv6200_reg.h	9162;"	d
+DEF_INFO6	include/ssv6200_reg.h	9163;"	d
+DEF_INFO7	include/ssv6200_reg.h	9164;"	d
+DEF_INFO8	include/ssv6200_reg.h	9165;"	d
+DEF_INFO9	include/ssv6200_reg.h	9166;"	d
+DEF_INFO_IDX_ADDR	include/ssv6200_reg.h	9198;"	d
+DEF_INFO_LEN_ADDR	include/ssv6200_reg.h	9199;"	d
+DEF_INFO_MASK	include/ssv6200_reg.h	9196;"	d
+DEF_INFO_RATE_OFFSET	include/ssv6200_reg.h	9197;"	d
+DEF_INS_SPACE_END_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	16315;"	d
+DEF_INS_SPACE_START_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	16314;"	d
+DEF_INT_FIQ_RAW	include/ssv6200_reg.h	8790;"	d
+DEF_INT_FIQ_STS	include/ssv6200_reg.h	8788;"	d
+DEF_INT_GPI_CFG	include/ssv6200_reg.h	8794;"	d
+DEF_INT_IRQ_RAW	include/ssv6200_reg.h	8789;"	d
+DEF_INT_IRQ_STS	include/ssv6200_reg.h	8787;"	d
+DEF_INT_MASK	include/ssv6200_reg.h	8785;"	d
+DEF_INT_MASK_REG	include/ssv6200_reg.h	8671;"	d
+DEF_INT_MASK_REG	smac/hal/ssv6006c/ssv6006C_reg.h	16195;"	d
+DEF_INT_MODE	include/ssv6200_reg.h	8786;"	d
+DEF_INT_PERI_MASK	include/ssv6200_reg.h	8791;"	d
+DEF_INT_PERI_RAW	include/ssv6200_reg.h	8793;"	d
+DEF_INT_PERI_STS	include/ssv6200_reg.h	8792;"	d
+DEF_INT_STATUS_REG	include/ssv6200_reg.h	8672;"	d
+DEF_INT_STATUS_REG	smac/hal/ssv6006c/ssv6006C_reg.h	16196;"	d
+DEF_INT_TAG	include/ssv6200_reg.h	8758;"	d
+DEF_INT_THRU_GPIO	smac/hal/ssv6006c/ssv6006C_reg.h	16185;"	d
+DEF_IO_DS	smac/hal/ssv6006c/ssv6006C_reg.h	16183;"	d
+DEF_IO_FUNC_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	16184;"	d
+DEF_IO_PDE	smac/hal/ssv6006c/ssv6006C_reg.h	16182;"	d
+DEF_IO_PI	smac/hal/ssv6006c/ssv6006C_reg.h	16178;"	d
+DEF_IO_PIE	smac/hal/ssv6006c/ssv6006C_reg.h	16179;"	d
+DEF_IO_PO	smac/hal/ssv6006c/ssv6006C_reg.h	16177;"	d
+DEF_IO_POEN	smac/hal/ssv6006c/ssv6006C_reg.h	16180;"	d
+DEF_IO_PORT_REG	include/ssv6200_reg.h	8670;"	d
+DEF_IO_PORT_REG	smac/hal/ssv6006c/ssv6006C_reg.h	16194;"	d
+DEF_IO_PUE	smac/hal/ssv6006c/ssv6006C_reg.h	16181;"	d
+DEF_IO_REG_PORT_REG	include/ssv6200_reg.h	8692;"	d
+DEF_IPC_INTERRUPT	smac/hal/ssv6006c/ssv6006C_reg.h	16359;"	d
+DEF_LDO_REGISTER	include/ssv6200_reg.h	9613;"	d
+DEF_LEN	include/ssv6200_reg.h	8822;"	d
+DEF_LEN_FLT	include/ssv6200_reg.h	9056;"	d
+DEF_LEN_FLT	smac/hal/ssv6006c/ssv6006C_reg.h	16573;"	d
+DEF_L_TRX_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	16035;"	d
+DEF_MAC_CLOCK_ENABLE	include/ssv6200_reg.h	9207;"	d
+DEF_MAC_CLOCK_ENABLE	smac/hal/ssv6006c/ssv6006C_reg.h	16781;"	d
+DEF_MAC_CSR_CLOCK_ENABLE	include/ssv6200_reg.h	9209;"	d
+DEF_MAC_CSR_CLOCK_ENABLE	smac/hal/ssv6006c/ssv6006C_reg.h	16783;"	d
+DEF_MAC_ENGINE_CLOCK_ENABLE	include/ssv6200_reg.h	9208;"	d
+DEF_MAC_ENGINE_CLOCK_ENABLE	smac/hal/ssv6006c/ssv6006C_reg.h	16782;"	d
+DEF_MAC_MODE	include/ssv6200_reg.h	9203;"	d
+DEF_MAC_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	16777;"	d
+DEF_MANUAL_DS	smac/hal/ssv6006c/ssv6006C_reg.h	16176;"	d
+DEF_MANUAL_ENABLE_REGISTER	include/ssv6200_reg.h	9612;"	d
+DEF_MANUAL_IO	smac/hal/ssv6006c/ssv6006C_reg.h	16173;"	d
+DEF_MANUAL_MODE_RX_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	16305;"	d
+DEF_MANUAL_MODE_TX_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	16304;"	d
+DEF_MANUAL_PD	smac/hal/ssv6006c/ssv6006C_reg.h	16175;"	d
+DEF_MANUAL_PU	smac/hal/ssv6006c/ssv6006C_reg.h	16174;"	d
+DEF_MANUAL_RESET_N	smac/hal/ssv6006c/ssv6006C_reg.h	16103;"	d
+DEF_MASK_TYPHOST_INT_MAP	smac/hal/ssv6006c/ssv6006C_reg.h	16336;"	d
+DEF_MASK_TYPHOST_INT_MAP_02	smac/hal/ssv6006c/ssv6006C_reg.h	16327;"	d
+DEF_MASK_TYPHOST_INT_MAP_15	smac/hal/ssv6006c/ssv6006C_reg.h	16330;"	d
+DEF_MASK_TYPHOST_INT_MAP_31	smac/hal/ssv6006c/ssv6006C_reg.h	16333;"	d
+DEF_MASK_TYPMCU_INT_MAP	smac/hal/ssv6006c/ssv6006C_reg.h	16349;"	d
+DEF_MASK_TYPMCU_INT_MAP_02	smac/hal/ssv6006c/ssv6006C_reg.h	16340;"	d
+DEF_MASK_TYPMCU_INT_MAP_15	smac/hal/ssv6006c/ssv6006C_reg.h	16343;"	d
+DEF_MASK_TYPMCU_INT_MAP_31	smac/hal/ssv6006c/ssv6006C_reg.h	16346;"	d
+DEF_MBOX_HALT_CFG	include/ssv6200_reg.h	9336;"	d
+DEF_MBOX_HALT_CFG	smac/hal/ssv6006c/ssv6006C_reg.h	17915;"	d
+DEF_MBOX_HALT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	17916;"	d
+DEF_MB_CPU_INT	include/ssv6200_reg.h	9326;"	d
+DEF_MB_CPU_INT	smac/hal/ssv6006c/ssv6006C_reg.h	17903;"	d
+DEF_MB_CPU_INT_ALT	smac/hal/ssv6006c/ssv6006C_reg.h	17902;"	d
+DEF_MB_DBG_CFG1	include/ssv6200_reg.h	9337;"	d
+DEF_MB_DBG_CFG1	smac/hal/ssv6006c/ssv6006C_reg.h	17917;"	d
+DEF_MB_DBG_CFG2	include/ssv6200_reg.h	9338;"	d
+DEF_MB_DBG_CFG2	smac/hal/ssv6006c/ssv6006C_reg.h	17918;"	d
+DEF_MB_DBG_CFG3	include/ssv6200_reg.h	9339;"	d
+DEF_MB_DBG_CFG3	smac/hal/ssv6006c/ssv6006C_reg.h	17919;"	d
+DEF_MB_DBG_CFG4	include/ssv6200_reg.h	9340;"	d
+DEF_MB_DBG_CFG4	smac/hal/ssv6006c/ssv6006C_reg.h	17920;"	d
+DEF_MB_IDTBL_0_STATUS	include/ssv6200_reg.h	9665;"	d
+DEF_MB_IDTBL_1_STATUS	include/ssv6200_reg.h	9666;"	d
+DEF_MB_IDTBL_2_STATUS	include/ssv6200_reg.h	9667;"	d
+DEF_MB_IDTBL_3_STATUS	include/ssv6200_reg.h	9668;"	d
+DEF_MB_IN_FF_FLUSH	include/ssv6200_reg.h	9353;"	d
+DEF_MB_IN_FF_FLUSH	smac/hal/ssv6006c/ssv6006C_reg.h	17934;"	d
+DEF_MB_IN_FF_FLUSH	smac/hal/ssv6006c/ssv6006C_reg.h	17935;"	d
+DEF_MB_NEQID_0_STATUS	include/ssv6200_reg.h	9677;"	d
+DEF_MB_NEQID_1_STATUS	include/ssv6200_reg.h	9678;"	d
+DEF_MB_NEQID_2_STATUS	include/ssv6200_reg.h	9679;"	d
+DEF_MB_NEQID_3_STATUS	include/ssv6200_reg.h	9680;"	d
+DEF_MB_OUT_QUEUE_CFG	include/ssv6200_reg.h	9341;"	d
+DEF_MB_OUT_QUEUE_CFG	smac/hal/ssv6006c/ssv6006C_reg.h	17921;"	d
+DEF_MB_OUT_QUEUE_FLUSH	include/ssv6200_reg.h	9342;"	d
+DEF_MB_OUT_QUEUE_FLUSH	smac/hal/ssv6006c/ssv6006C_reg.h	17922;"	d
+DEF_MB_OUT_QUEUE_FLUSH	smac/hal/ssv6006c/ssv6006C_reg.h	17923;"	d
+DEF_MB_THRESHOLD10	include/ssv6200_reg.h	9351;"	d
+DEF_MB_THRESHOLD10	smac/hal/ssv6006c/ssv6006C_reg.h	17932;"	d
+DEF_MB_THRESHOLD6	include/ssv6200_reg.h	9347;"	d
+DEF_MB_THRESHOLD6	smac/hal/ssv6006c/ssv6006C_reg.h	17928;"	d
+DEF_MB_THRESHOLD7	include/ssv6200_reg.h	9348;"	d
+DEF_MB_THRESHOLD7	smac/hal/ssv6006c/ssv6006C_reg.h	17929;"	d
+DEF_MB_THRESHOLD8	include/ssv6200_reg.h	9349;"	d
+DEF_MB_THRESHOLD8	smac/hal/ssv6006c/ssv6006C_reg.h	17930;"	d
+DEF_MB_THRESHOLD9	include/ssv6200_reg.h	9350;"	d
+DEF_MB_THRESHOLD9	smac/hal/ssv6006c/ssv6006C_reg.h	17931;"	d
+DEF_MB_TRASH_CFG	include/ssv6200_reg.h	9352;"	d
+DEF_MB_TRASH_CFG	smac/hal/ssv6006c/ssv6006C_reg.h	17933;"	d
+DEF_MCU_DBG_DATA	include/ssv6200_reg.h	8558;"	d
+DEF_MCU_DBG_SEL	include/ssv6200_reg.h	8557;"	d
+DEF_MCU_NOTIFY_HOST_EVENT	smac/hal/ssv6006c/ssv6006C_reg.h	16206;"	d
+DEF_MCU_STATUS	include/ssv6200_reg.h	9332;"	d
+DEF_MCU_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	17909;"	d
+DEF_MCU_WDOG_REG	include/ssv6200_reg.h	8615;"	d
+DEF_MCU_WDOG_REG	smac/hal/ssv6006c/ssv6006C_reg.h	16161;"	d
+DEF_MIB_AMPDU	include/ssv6200_reg.h	9055;"	d
+DEF_MIB_AMPDU	smac/hal/ssv6006c/ssv6006C_reg.h	16572;"	d
+DEF_MIB_DELIMITER	include/ssv6200_reg.h	9057;"	d
+DEF_MIB_DELIMITER	smac/hal/ssv6006c/ssv6006C_reg.h	16574;"	d
+DEF_MIB_EN	include/ssv6200_reg.h	9222;"	d
+DEF_MIB_EN	smac/hal/ssv6006c/ssv6006C_reg.h	16803;"	d
+DEF_MIB_LEN_FAIL	include/ssv6200_reg.h	9031;"	d
+DEF_MIB_LEN_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	16557;"	d
+DEF_MIB_SCRT_CCMP0	include/ssv6200_reg.h	9275;"	d
+DEF_MIB_SCRT_CCMP0	smac/hal/ssv6006c/ssv6006C_reg.h	16856;"	d
+DEF_MIB_SCRT_CCMP1	include/ssv6200_reg.h	9276;"	d
+DEF_MIB_SCRT_CCMP1	smac/hal/ssv6006c/ssv6006C_reg.h	16857;"	d
+DEF_MIB_SCRT_TKIP0	include/ssv6200_reg.h	9272;"	d
+DEF_MIB_SCRT_TKIP0	smac/hal/ssv6006c/ssv6006C_reg.h	16853;"	d
+DEF_MIB_SCRT_TKIP1	include/ssv6200_reg.h	9273;"	d
+DEF_MIB_SCRT_TKIP1	smac/hal/ssv6006c/ssv6006C_reg.h	16854;"	d
+DEF_MIB_SCRT_TKIP2	include/ssv6200_reg.h	9274;"	d
+DEF_MIB_SCRT_TKIP2	smac/hal/ssv6006c/ssv6006C_reg.h	16855;"	d
+DEF_MMU_CTRL	include/ssv6200_reg.h	9652;"	d
+DEF_MMU_STATUS	include/ssv6200_reg.h	9661;"	d
+DEF_MODE_DECODER_TIMER_REGISTER1	smac/hal/ssv6006c/ssv6006C_reg.h	17419;"	d
+DEF_MODE_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17348;"	d
+DEF_MRX_ACK_NTF	include/ssv6200_reg.h	9247;"	d
+DEF_MRX_ACK_NTF	smac/hal/ssv6006c/ssv6006C_reg.h	16828;"	d
+DEF_MRX_ALC_FAIL	include/ssv6200_reg.h	9243;"	d
+DEF_MRX_ALC_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	16824;"	d
+DEF_MRX_BAR_NTF	include/ssv6200_reg.h	9252;"	d
+DEF_MRX_BAR_NTF	smac/hal/ssv6006c/ssv6006C_reg.h	16833;"	d
+DEF_MRX_BA_DBG	include/ssv6200_reg.h	8985;"	d
+DEF_MRX_BA_DBG	smac/hal/ssv6006c/ssv6006C_reg.h	16511;"	d
+DEF_MRX_BA_NTF	include/ssv6200_reg.h	9248;"	d
+DEF_MRX_BA_NTF	smac/hal/ssv6006c/ssv6006C_reg.h	16829;"	d
+DEF_MRX_CSR_NTF	include/ssv6200_reg.h	9255;"	d
+DEF_MRX_CSR_NTF	smac/hal/ssv6006c/ssv6006C_reg.h	16836;"	d
+DEF_MRX_CTS_NTF	include/ssv6200_reg.h	9246;"	d
+DEF_MRX_CTS_NTF	smac/hal/ssv6006c/ssv6006C_reg.h	16827;"	d
+DEF_MRX_DATA_NTF	include/ssv6200_reg.h	9249;"	d
+DEF_MRX_DATA_NTF	smac/hal/ssv6006c/ssv6006C_reg.h	16830;"	d
+DEF_MRX_DAT_CRC_NTF	include/ssv6200_reg.h	9251;"	d
+DEF_MRX_DAT_CRC_NTF	smac/hal/ssv6006c/ssv6006C_reg.h	16832;"	d
+DEF_MRX_DAT_NTF	include/ssv6200_reg.h	9244;"	d
+DEF_MRX_DAT_NTF	smac/hal/ssv6006c/ssv6006C_reg.h	16825;"	d
+DEF_MRX_DUP_FRM	include/ssv6200_reg.h	9237;"	d
+DEF_MRX_DUP_FRM	smac/hal/ssv6006c/ssv6006C_reg.h	16818;"	d
+DEF_MRX_ERR	include/ssv6200_reg.h	9034;"	d
+DEF_MRX_ERR	smac/hal/ssv6006c/ssv6006C_reg.h	16560;"	d
+DEF_MRX_FCS_ERR	include/ssv6200_reg.h	9240;"	d
+DEF_MRX_FCS_ERR	smac/hal/ssv6006c/ssv6006C_reg.h	16821;"	d
+DEF_MRX_FCS_SUCC	include/ssv6200_reg.h	9241;"	d
+DEF_MRX_FCS_SUCC	smac/hal/ssv6006c/ssv6006C_reg.h	16822;"	d
+DEF_MRX_FLT_EN0	include/ssv6200_reg.h	9002;"	d
+DEF_MRX_FLT_EN0	smac/hal/ssv6006c/ssv6006C_reg.h	16528;"	d
+DEF_MRX_FLT_EN1	include/ssv6200_reg.h	9003;"	d
+DEF_MRX_FLT_EN1	smac/hal/ssv6006c/ssv6006C_reg.h	16529;"	d
+DEF_MRX_FLT_EN10	smac/hal/ssv6006c/ssv6006C_reg.h	16569;"	d
+DEF_MRX_FLT_EN2	include/ssv6200_reg.h	9004;"	d
+DEF_MRX_FLT_EN2	smac/hal/ssv6006c/ssv6006C_reg.h	16530;"	d
+DEF_MRX_FLT_EN3	include/ssv6200_reg.h	9005;"	d
+DEF_MRX_FLT_EN3	smac/hal/ssv6006c/ssv6006C_reg.h	16531;"	d
+DEF_MRX_FLT_EN4	include/ssv6200_reg.h	9006;"	d
+DEF_MRX_FLT_EN4	smac/hal/ssv6006c/ssv6006C_reg.h	16532;"	d
+DEF_MRX_FLT_EN5	include/ssv6200_reg.h	9007;"	d
+DEF_MRX_FLT_EN5	smac/hal/ssv6006c/ssv6006C_reg.h	16533;"	d
+DEF_MRX_FLT_EN6	include/ssv6200_reg.h	9008;"	d
+DEF_MRX_FLT_EN6	smac/hal/ssv6006c/ssv6006C_reg.h	16534;"	d
+DEF_MRX_FLT_EN7	include/ssv6200_reg.h	9009;"	d
+DEF_MRX_FLT_EN7	smac/hal/ssv6006c/ssv6006C_reg.h	16535;"	d
+DEF_MRX_FLT_EN8	include/ssv6200_reg.h	9010;"	d
+DEF_MRX_FLT_EN8	smac/hal/ssv6006c/ssv6006C_reg.h	16536;"	d
+DEF_MRX_FLT_EN9	smac/hal/ssv6006c/ssv6006C_reg.h	16568;"	d
+DEF_MRX_FLT_TB0	include/ssv6200_reg.h	8986;"	d
+DEF_MRX_FLT_TB0	smac/hal/ssv6006c/ssv6006C_reg.h	16512;"	d
+DEF_MRX_FLT_TB1	include/ssv6200_reg.h	8987;"	d
+DEF_MRX_FLT_TB1	smac/hal/ssv6006c/ssv6006C_reg.h	16513;"	d
+DEF_MRX_FLT_TB10	include/ssv6200_reg.h	8996;"	d
+DEF_MRX_FLT_TB10	smac/hal/ssv6006c/ssv6006C_reg.h	16522;"	d
+DEF_MRX_FLT_TB11	include/ssv6200_reg.h	8997;"	d
+DEF_MRX_FLT_TB11	smac/hal/ssv6006c/ssv6006C_reg.h	16523;"	d
+DEF_MRX_FLT_TB12	include/ssv6200_reg.h	8998;"	d
+DEF_MRX_FLT_TB12	smac/hal/ssv6006c/ssv6006C_reg.h	16524;"	d
+DEF_MRX_FLT_TB13	include/ssv6200_reg.h	8999;"	d
+DEF_MRX_FLT_TB13	smac/hal/ssv6006c/ssv6006C_reg.h	16525;"	d
+DEF_MRX_FLT_TB14	include/ssv6200_reg.h	9000;"	d
+DEF_MRX_FLT_TB14	smac/hal/ssv6006c/ssv6006C_reg.h	16526;"	d
+DEF_MRX_FLT_TB15	include/ssv6200_reg.h	9001;"	d
+DEF_MRX_FLT_TB15	smac/hal/ssv6006c/ssv6006C_reg.h	16527;"	d
+DEF_MRX_FLT_TB2	include/ssv6200_reg.h	8988;"	d
+DEF_MRX_FLT_TB2	smac/hal/ssv6006c/ssv6006C_reg.h	16514;"	d
+DEF_MRX_FLT_TB3	include/ssv6200_reg.h	8989;"	d
+DEF_MRX_FLT_TB3	smac/hal/ssv6006c/ssv6006C_reg.h	16515;"	d
+DEF_MRX_FLT_TB4	include/ssv6200_reg.h	8990;"	d
+DEF_MRX_FLT_TB4	smac/hal/ssv6006c/ssv6006C_reg.h	16516;"	d
+DEF_MRX_FLT_TB5	include/ssv6200_reg.h	8991;"	d
+DEF_MRX_FLT_TB5	smac/hal/ssv6006c/ssv6006C_reg.h	16517;"	d
+DEF_MRX_FLT_TB6	include/ssv6200_reg.h	8992;"	d
+DEF_MRX_FLT_TB6	smac/hal/ssv6006c/ssv6006C_reg.h	16518;"	d
+DEF_MRX_FLT_TB7	include/ssv6200_reg.h	8993;"	d
+DEF_MRX_FLT_TB7	smac/hal/ssv6006c/ssv6006C_reg.h	16519;"	d
+DEF_MRX_FLT_TB8	include/ssv6200_reg.h	8994;"	d
+DEF_MRX_FLT_TB8	smac/hal/ssv6006c/ssv6006C_reg.h	16520;"	d
+DEF_MRX_FLT_TB9	include/ssv6200_reg.h	8995;"	d
+DEF_MRX_FLT_TB9	smac/hal/ssv6006c/ssv6006C_reg.h	16521;"	d
+DEF_MRX_FRG_FRM	include/ssv6200_reg.h	9238;"	d
+DEF_MRX_FRG_FRM	smac/hal/ssv6006c/ssv6006C_reg.h	16819;"	d
+DEF_MRX_GROUP_FRM	include/ssv6200_reg.h	9239;"	d
+DEF_MRX_GROUP_FRM	smac/hal/ssv6006c/ssv6006C_reg.h	16820;"	d
+DEF_MRX_LEN_FLT	include/ssv6200_reg.h	9011;"	d
+DEF_MRX_LEN_FLT	smac/hal/ssv6006c/ssv6006C_reg.h	16537;"	d
+DEF_MRX_MB_MISS	include/ssv6200_reg.h	9253;"	d
+DEF_MRX_MB_MISS	smac/hal/ssv6006c/ssv6006C_reg.h	16834;"	d
+DEF_MRX_MCAST_CTRL0	include/ssv6200_reg.h	8968;"	d
+DEF_MRX_MCAST_CTRL0	smac/hal/ssv6006c/ssv6006C_reg.h	16494;"	d
+DEF_MRX_MCAST_CTRL1	include/ssv6200_reg.h	8973;"	d
+DEF_MRX_MCAST_CTRL1	smac/hal/ssv6006c/ssv6006C_reg.h	16499;"	d
+DEF_MRX_MCAST_CTRL2	include/ssv6200_reg.h	8978;"	d
+DEF_MRX_MCAST_CTRL2	smac/hal/ssv6006c/ssv6006C_reg.h	16504;"	d
+DEF_MRX_MCAST_CTRL3	include/ssv6200_reg.h	8983;"	d
+DEF_MRX_MCAST_CTRL3	smac/hal/ssv6006c/ssv6006C_reg.h	16509;"	d
+DEF_MRX_MCAST_MK0_0	include/ssv6200_reg.h	8966;"	d
+DEF_MRX_MCAST_MK0_0	smac/hal/ssv6006c/ssv6006C_reg.h	16492;"	d
+DEF_MRX_MCAST_MK0_1	include/ssv6200_reg.h	8967;"	d
+DEF_MRX_MCAST_MK0_1	smac/hal/ssv6006c/ssv6006C_reg.h	16493;"	d
+DEF_MRX_MCAST_MK1_0	include/ssv6200_reg.h	8971;"	d
+DEF_MRX_MCAST_MK1_0	smac/hal/ssv6006c/ssv6006C_reg.h	16497;"	d
+DEF_MRX_MCAST_MK1_1	include/ssv6200_reg.h	8972;"	d
+DEF_MRX_MCAST_MK1_1	smac/hal/ssv6006c/ssv6006C_reg.h	16498;"	d
+DEF_MRX_MCAST_MK2_0	include/ssv6200_reg.h	8976;"	d
+DEF_MRX_MCAST_MK2_0	smac/hal/ssv6006c/ssv6006C_reg.h	16502;"	d
+DEF_MRX_MCAST_MK2_1	include/ssv6200_reg.h	8977;"	d
+DEF_MRX_MCAST_MK2_1	smac/hal/ssv6006c/ssv6006C_reg.h	16503;"	d
+DEF_MRX_MCAST_MK3_0	include/ssv6200_reg.h	8981;"	d
+DEF_MRX_MCAST_MK3_0	smac/hal/ssv6006c/ssv6006C_reg.h	16507;"	d
+DEF_MRX_MCAST_MK3_1	include/ssv6200_reg.h	8982;"	d
+DEF_MRX_MCAST_MK3_1	smac/hal/ssv6006c/ssv6006C_reg.h	16508;"	d
+DEF_MRX_MCAST_TB0_0	include/ssv6200_reg.h	8964;"	d
+DEF_MRX_MCAST_TB0_0	smac/hal/ssv6006c/ssv6006C_reg.h	16490;"	d
+DEF_MRX_MCAST_TB0_1	include/ssv6200_reg.h	8965;"	d
+DEF_MRX_MCAST_TB0_1	smac/hal/ssv6006c/ssv6006C_reg.h	16491;"	d
+DEF_MRX_MCAST_TB1_0	include/ssv6200_reg.h	8969;"	d
+DEF_MRX_MCAST_TB1_0	smac/hal/ssv6006c/ssv6006C_reg.h	16495;"	d
+DEF_MRX_MCAST_TB1_1	include/ssv6200_reg.h	8970;"	d
+DEF_MRX_MCAST_TB1_1	smac/hal/ssv6006c/ssv6006C_reg.h	16496;"	d
+DEF_MRX_MCAST_TB2_0	include/ssv6200_reg.h	8974;"	d
+DEF_MRX_MCAST_TB2_0	smac/hal/ssv6006c/ssv6006C_reg.h	16500;"	d
+DEF_MRX_MCAST_TB2_1	include/ssv6200_reg.h	8975;"	d
+DEF_MRX_MCAST_TB2_1	smac/hal/ssv6006c/ssv6006C_reg.h	16501;"	d
+DEF_MRX_MCAST_TB3_0	include/ssv6200_reg.h	8979;"	d
+DEF_MRX_MCAST_TB3_0	smac/hal/ssv6006c/ssv6006C_reg.h	16505;"	d
+DEF_MRX_MCAST_TB3_1	include/ssv6200_reg.h	8980;"	d
+DEF_MRX_MCAST_TB3_1	smac/hal/ssv6006c/ssv6006C_reg.h	16506;"	d
+DEF_MRX_MISS	include/ssv6200_reg.h	9242;"	d
+DEF_MRX_MISS	smac/hal/ssv6006c/ssv6006C_reg.h	16823;"	d
+DEF_MRX_MNG_NTF	include/ssv6200_reg.h	9250;"	d
+DEF_MRX_MNG_NTF	smac/hal/ssv6006c/ssv6006C_reg.h	16831;"	d
+DEF_MRX_NIDLE_MISS	include/ssv6200_reg.h	9254;"	d
+DEF_MRX_NIDLE_MISS	smac/hal/ssv6006c/ssv6006C_reg.h	16835;"	d
+DEF_MRX_PHY_INFO	include/ssv6200_reg.h	8984;"	d
+DEF_MRX_PHY_INFO	smac/hal/ssv6006c/ssv6006C_reg.h	16510;"	d
+DEF_MRX_RTS_NTF	include/ssv6200_reg.h	9245;"	d
+DEF_MRX_RTS_NTF	smac/hal/ssv6006c/ssv6006C_reg.h	16826;"	d
+DEF_MRX_WATCH_DOG	include/ssv6200_reg.h	9026;"	d
+DEF_MRX_WATCH_DOG	smac/hal/ssv6006c/ssv6006C_reg.h	16552;"	d
+DEF_MTX_ACK_FAIL	include/ssv6200_reg.h	9233;"	d
+DEF_MTX_ACK_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	16814;"	d
+DEF_MTX_ACK_TX	include/ssv6200_reg.h	9235;"	d
+DEF_MTX_ACK_TX	smac/hal/ssv6006c/ssv6006C_reg.h	16816;"	d
+DEF_MTX_BCN_CFG0	include/ssv6200_reg.h	9069;"	d
+DEF_MTX_BCN_CFG1	include/ssv6200_reg.h	9070;"	d
+DEF_MTX_BCN_DTIM_CONFG	smac/hal/ssv6006c/ssv6006C_reg.h	16606;"	d
+DEF_MTX_BCN_DTIM_INT_W1CLR	smac/hal/ssv6006c/ssv6006C_reg.h	16607;"	d
+DEF_MTX_BCN_DTIM_SET0	smac/hal/ssv6006c/ssv6006C_reg.h	16604;"	d
+DEF_MTX_BCN_DTIM_SET1	smac/hal/ssv6006c/ssv6006C_reg.h	16605;"	d
+DEF_MTX_BCN_EN_INT	include/ssv6200_reg.h	9063;"	d
+DEF_MTX_BCN_EN_INT	smac/hal/ssv6006c/ssv6006C_reg.h	16609;"	d
+DEF_MTX_BCN_EN_MISC	include/ssv6200_reg.h	9064;"	d
+DEF_MTX_BCN_EN_MISC	smac/hal/ssv6006c/ssv6006C_reg.h	16610;"	d
+DEF_MTX_BCN_INT_STS	include/ssv6200_reg.h	9062;"	d
+DEF_MTX_BCN_INT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	16608;"	d
+DEF_MTX_BCN_MISC	include/ssv6200_reg.h	9065;"	d
+DEF_MTX_BCN_MISC	smac/hal/ssv6006c/ssv6006C_reg.h	16611;"	d
+DEF_MTX_BCN_PKT_SET0	smac/hal/ssv6006c/ssv6006C_reg.h	16602;"	d
+DEF_MTX_BCN_PKT_SET1	smac/hal/ssv6006c/ssv6006C_reg.h	16603;"	d
+DEF_MTX_BCN_PRD	include/ssv6200_reg.h	9066;"	d
+DEF_MTX_BCN_PRD	smac/hal/ssv6006c/ssv6006C_reg.h	16612;"	d
+DEF_MTX_BCN_TSF_L	include/ssv6200_reg.h	9067;"	d
+DEF_MTX_BCN_TSF_L	smac/hal/ssv6006c/ssv6006C_reg.h	16613;"	d
+DEF_MTX_BCN_TSF_U	include/ssv6200_reg.h	9068;"	d
+DEF_MTX_BCN_TSF_U	smac/hal/ssv6006c/ssv6006C_reg.h	16614;"	d
+DEF_MTX_CTS_TX	include/ssv6200_reg.h	9236;"	d
+DEF_MTX_CTS_TX	smac/hal/ssv6006c/ssv6006C_reg.h	16817;"	d
+DEF_MTX_DBGOPT_FORCE_RATE	smac/hal/ssv6006c/ssv6006C_reg.h	16596;"	d
+DEF_MTX_DBGOPT_FORCE_RATE_ENABLE	smac/hal/ssv6006c/ssv6006C_reg.h	16597;"	d
+DEF_MTX_DBG_CTRL	include/ssv6200_reg.h	9072;"	d
+DEF_MTX_DBG_DAT0	include/ssv6200_reg.h	9073;"	d
+DEF_MTX_DBG_DAT1	include/ssv6200_reg.h	9074;"	d
+DEF_MTX_DBG_DAT2	include/ssv6200_reg.h	9075;"	d
+DEF_MTX_DBG_DAT3	include/ssv6200_reg.h	9079;"	d
+DEF_MTX_DBG_DAT4	include/ssv6200_reg.h	9083;"	d
+DEF_MTX_DBG_IFSAIRRO0	smac/hal/ssv6006c/ssv6006C_reg.h	16620;"	d
+DEF_MTX_DBG_IFSAIRRO1	smac/hal/ssv6006c/ssv6006C_reg.h	16621;"	d
+DEF_MTX_DBG_IFSAIRRO2	smac/hal/ssv6006c/ssv6006C_reg.h	16622;"	d
+DEF_MTX_DBG_IFSAIRRO3	smac/hal/ssv6006c/ssv6006C_reg.h	16623;"	d
+DEF_MTX_DBG_MORE	smac/hal/ssv6006c/ssv6006C_reg.h	16599;"	d
+DEF_MTX_DBG_PHYTXIPTIMEOUT	smac/hal/ssv6006c/ssv6006C_reg.h	16598;"	d
+DEF_MTX_DBG_ROIFSAIR1	smac/hal/ssv6006c/ssv6006C_reg.h	16600;"	d
+DEF_MTX_DBG_ROIFSAIR2	smac/hal/ssv6006c/ssv6006C_reg.h	16601;"	d
+DEF_MTX_DBG_RO_BASE1	smac/hal/ssv6006c/ssv6006C_reg.h	16625;"	d
+DEF_MTX_DBG_RO_BASE2	smac/hal/ssv6006c/ssv6006C_reg.h	16626;"	d
+DEF_MTX_DBG_RO_BASE3	smac/hal/ssv6006c/ssv6006C_reg.h	16627;"	d
+DEF_MTX_DUR_IFS	include/ssv6200_reg.h	9077;"	d
+DEF_MTX_DUR_SIFS_G	include/ssv6200_reg.h	9078;"	d
+DEF_MTX_DUR_TOUT	include/ssv6200_reg.h	9076;"	d
+DEF_MTX_EDCCA_TOUT	include/ssv6200_reg.h	9061;"	d
+DEF_MTX_FAIL	include/ssv6200_reg.h	9228;"	d
+DEF_MTX_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	16809;"	d
+DEF_MTX_FRM	include/ssv6200_reg.h	9234;"	d
+DEF_MTX_FRM	smac/hal/ssv6006c/ssv6006C_reg.h	16815;"	d
+DEF_MTX_GROUP	include/ssv6200_reg.h	9227;"	d
+DEF_MTX_GROUP	smac/hal/ssv6006c/ssv6006C_reg.h	16808;"	d
+DEF_MTX_HALT_OPTION	smac/hal/ssv6006c/ssv6006C_reg.h	16581;"	d
+DEF_MTX_INT_EN	include/ssv6200_reg.h	9059;"	d
+DEF_MTX_INT_EN	smac/hal/ssv6006c/ssv6006C_reg.h	16576;"	d
+DEF_MTX_INT_STS	include/ssv6200_reg.h	9058;"	d
+DEF_MTX_INT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	16575;"	d
+DEF_MTX_MIB_WSID0	include/ssv6200_reg.h	9081;"	d
+DEF_MTX_MIB_WSID0	smac/hal/ssv6006c/ssv6006C_reg.h	16583;"	d
+DEF_MTX_MIB_WSID1	include/ssv6200_reg.h	9082;"	d
+DEF_MTX_MIB_WSID1	smac/hal/ssv6006c/ssv6006C_reg.h	16584;"	d
+DEF_MTX_MIB_WSID2	smac/hal/ssv6006c/ssv6006C_reg.h	16585;"	d
+DEF_MTX_MIB_WSID3	smac/hal/ssv6006c/ssv6006C_reg.h	16586;"	d
+DEF_MTX_MIB_WSID4	smac/hal/ssv6006c/ssv6006C_reg.h	16587;"	d
+DEF_MTX_MIB_WSID5	smac/hal/ssv6006c/ssv6006C_reg.h	16588;"	d
+DEF_MTX_MIB_WSID6	smac/hal/ssv6006c/ssv6006C_reg.h	16589;"	d
+DEF_MTX_MIB_WSID7	smac/hal/ssv6006c/ssv6006C_reg.h	16590;"	d
+DEF_MTX_MISC_EN	include/ssv6200_reg.h	9060;"	d
+DEF_MTX_MISC_EN	smac/hal/ssv6006c/ssv6006C_reg.h	16577;"	d
+DEF_MTX_MULTI_RETRY	include/ssv6200_reg.h	9230;"	d
+DEF_MTX_MULTI_RETRY	smac/hal/ssv6006c/ssv6006C_reg.h	16811;"	d
+DEF_MTX_NAV	include/ssv6200_reg.h	9080;"	d
+DEF_MTX_NAV	smac/hal/ssv6006c/ssv6006C_reg.h	16624;"	d
+DEF_MTX_PEER_LOCK_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	16594;"	d
+DEF_MTX_PEER_PS_LOCK	smac/hal/ssv6006c/ssv6006C_reg.h	16593;"	d
+DEF_MTX_PHYRXIFS_DBG	smac/hal/ssv6006c/ssv6006C_reg.h	16619;"	d
+DEF_MTX_PHYTX_DBG1	smac/hal/ssv6006c/ssv6006C_reg.h	16582;"	d
+DEF_MTX_RATERPT	smac/hal/ssv6006c/ssv6006C_reg.h	16595;"	d
+DEF_MTX_RESPFRM_INFO_00	smac/hal/ssv6006c/ssv6006C_reg.h	16699;"	d
+DEF_MTX_RESPFRM_INFO_01	smac/hal/ssv6006c/ssv6006C_reg.h	16700;"	d
+DEF_MTX_RESPFRM_INFO_02	smac/hal/ssv6006c/ssv6006C_reg.h	16701;"	d
+DEF_MTX_RESPFRM_INFO_03	smac/hal/ssv6006c/ssv6006C_reg.h	16702;"	d
+DEF_MTX_RESPFRM_INFO_11	smac/hal/ssv6006c/ssv6006C_reg.h	16703;"	d
+DEF_MTX_RESPFRM_INFO_12	smac/hal/ssv6006c/ssv6006C_reg.h	16704;"	d
+DEF_MTX_RESPFRM_INFO_13	smac/hal/ssv6006c/ssv6006C_reg.h	16705;"	d
+DEF_MTX_RESPFRM_INFO_90_B0	smac/hal/ssv6006c/ssv6006C_reg.h	16706;"	d
+DEF_MTX_RESPFRM_INFO_91_B1	smac/hal/ssv6006c/ssv6006C_reg.h	16707;"	d
+DEF_MTX_RESPFRM_INFO_92_B2	smac/hal/ssv6006c/ssv6006C_reg.h	16708;"	d
+DEF_MTX_RESPFRM_INFO_93_B3	smac/hal/ssv6006c/ssv6006C_reg.h	16709;"	d
+DEF_MTX_RESPFRM_INFO_94_B4	smac/hal/ssv6006c/ssv6006C_reg.h	16710;"	d
+DEF_MTX_RESPFRM_INFO_95_B5	smac/hal/ssv6006c/ssv6006C_reg.h	16711;"	d
+DEF_MTX_RESPFRM_INFO_96_B6	smac/hal/ssv6006c/ssv6006C_reg.h	16712;"	d
+DEF_MTX_RESPFRM_INFO_97_B7	smac/hal/ssv6006c/ssv6006C_reg.h	16713;"	d
+DEF_MTX_RESPFRM_INFO_C0	smac/hal/ssv6006c/ssv6006C_reg.h	16714;"	d
+DEF_MTX_RESPFRM_INFO_C1	smac/hal/ssv6006c/ssv6006C_reg.h	16715;"	d
+DEF_MTX_RESPFRM_INFO_C2	smac/hal/ssv6006c/ssv6006C_reg.h	16716;"	d
+DEF_MTX_RESPFRM_INFO_C3	smac/hal/ssv6006c/ssv6006C_reg.h	16717;"	d
+DEF_MTX_RESPFRM_INFO_C4	smac/hal/ssv6006c/ssv6006C_reg.h	16718;"	d
+DEF_MTX_RESPFRM_INFO_C5	smac/hal/ssv6006c/ssv6006C_reg.h	16719;"	d
+DEF_MTX_RESPFRM_INFO_C6	smac/hal/ssv6006c/ssv6006C_reg.h	16720;"	d
+DEF_MTX_RESPFRM_INFO_C7	smac/hal/ssv6006c/ssv6006C_reg.h	16721;"	d
+DEF_MTX_RESPFRM_INFO_D0	smac/hal/ssv6006c/ssv6006C_reg.h	16722;"	d
+DEF_MTX_RESPFRM_INFO_D1	smac/hal/ssv6006c/ssv6006C_reg.h	16723;"	d
+DEF_MTX_RESPFRM_INFO_D2	smac/hal/ssv6006c/ssv6006C_reg.h	16724;"	d
+DEF_MTX_RESPFRM_INFO_D3	smac/hal/ssv6006c/ssv6006C_reg.h	16725;"	d
+DEF_MTX_RESPFRM_INFO_D4	smac/hal/ssv6006c/ssv6006C_reg.h	16726;"	d
+DEF_MTX_RESPFRM_INFO_D5	smac/hal/ssv6006c/ssv6006C_reg.h	16727;"	d
+DEF_MTX_RESPFRM_INFO_D6	smac/hal/ssv6006c/ssv6006C_reg.h	16728;"	d
+DEF_MTX_RESPFRM_INFO_D7	smac/hal/ssv6006c/ssv6006C_reg.h	16729;"	d
+DEF_MTX_RESPFRM_INFO_D8	smac/hal/ssv6006c/ssv6006C_reg.h	16730;"	d
+DEF_MTX_RESPFRM_INFO_D9	smac/hal/ssv6006c/ssv6006C_reg.h	16731;"	d
+DEF_MTX_RESPFRM_INFO_DA	smac/hal/ssv6006c/ssv6006C_reg.h	16732;"	d
+DEF_MTX_RESPFRM_INFO_DB	smac/hal/ssv6006c/ssv6006C_reg.h	16733;"	d
+DEF_MTX_RESPFRM_INFO_DC	smac/hal/ssv6006c/ssv6006C_reg.h	16734;"	d
+DEF_MTX_RESPFRM_INFO_DD	smac/hal/ssv6006c/ssv6006C_reg.h	16735;"	d
+DEF_MTX_RESPFRM_INFO_DE	smac/hal/ssv6006c/ssv6006C_reg.h	16736;"	d
+DEF_MTX_RESPFRM_INFO_DF	smac/hal/ssv6006c/ssv6006C_reg.h	16737;"	d
+DEF_MTX_RESPFRM_INFO_TABLE_EXCEPTION	smac/hal/ssv6006c/ssv6006C_reg.h	16698;"	d
+DEF_MTX_RESPFRM_RATE_TABLE_00	smac/hal/ssv6006c/ssv6006C_reg.h	16659;"	d
+DEF_MTX_RESPFRM_RATE_TABLE_01	smac/hal/ssv6006c/ssv6006C_reg.h	16660;"	d
+DEF_MTX_RESPFRM_RATE_TABLE_02	smac/hal/ssv6006c/ssv6006C_reg.h	16661;"	d
+DEF_MTX_RESPFRM_RATE_TABLE_03	smac/hal/ssv6006c/ssv6006C_reg.h	16662;"	d
+DEF_MTX_RESPFRM_RATE_TABLE_11	smac/hal/ssv6006c/ssv6006C_reg.h	16663;"	d
+DEF_MTX_RESPFRM_RATE_TABLE_12	smac/hal/ssv6006c/ssv6006C_reg.h	16664;"	d
+DEF_MTX_RESPFRM_RATE_TABLE_13	smac/hal/ssv6006c/ssv6006C_reg.h	16665;"	d
+DEF_MTX_RESPFRM_RATE_TABLE_90_B0	smac/hal/ssv6006c/ssv6006C_reg.h	16666;"	d
+DEF_MTX_RESPFRM_RATE_TABLE_91_B1	smac/hal/ssv6006c/ssv6006C_reg.h	16667;"	d
+DEF_MTX_RESPFRM_RATE_TABLE_92_B2	smac/hal/ssv6006c/ssv6006C_reg.h	16668;"	d
+DEF_MTX_RESPFRM_RATE_TABLE_93_B3	smac/hal/ssv6006c/ssv6006C_reg.h	16669;"	d
+DEF_MTX_RESPFRM_RATE_TABLE_94_B4	smac/hal/ssv6006c/ssv6006C_reg.h	16670;"	d
+DEF_MTX_RESPFRM_RATE_TABLE_95_B5	smac/hal/ssv6006c/ssv6006C_reg.h	16671;"	d
+DEF_MTX_RESPFRM_RATE_TABLE_96_B6	smac/hal/ssv6006c/ssv6006C_reg.h	16672;"	d
+DEF_MTX_RESPFRM_RATE_TABLE_97_B7	smac/hal/ssv6006c/ssv6006C_reg.h	16673;"	d
+DEF_MTX_RESPFRM_RATE_TABLE_C0_E0	smac/hal/ssv6006c/ssv6006C_reg.h	16674;"	d
+DEF_MTX_RESPFRM_RATE_TABLE_C1_E1	smac/hal/ssv6006c/ssv6006C_reg.h	16675;"	d
+DEF_MTX_RESPFRM_RATE_TABLE_C2_E2	smac/hal/ssv6006c/ssv6006C_reg.h	16676;"	d
+DEF_MTX_RESPFRM_RATE_TABLE_C3_E3	smac/hal/ssv6006c/ssv6006C_reg.h	16677;"	d
+DEF_MTX_RESPFRM_RATE_TABLE_C4_E4	smac/hal/ssv6006c/ssv6006C_reg.h	16678;"	d
+DEF_MTX_RESPFRM_RATE_TABLE_C5_E5	smac/hal/ssv6006c/ssv6006C_reg.h	16679;"	d
+DEF_MTX_RESPFRM_RATE_TABLE_C6_E6	smac/hal/ssv6006c/ssv6006C_reg.h	16680;"	d
+DEF_MTX_RESPFRM_RATE_TABLE_C7_E7	smac/hal/ssv6006c/ssv6006C_reg.h	16681;"	d
+DEF_MTX_RESPFRM_RATE_TABLE_D0_F0	smac/hal/ssv6006c/ssv6006C_reg.h	16682;"	d
+DEF_MTX_RESPFRM_RATE_TABLE_D1_F1	smac/hal/ssv6006c/ssv6006C_reg.h	16683;"	d
+DEF_MTX_RESPFRM_RATE_TABLE_D2_F2	smac/hal/ssv6006c/ssv6006C_reg.h	16684;"	d
+DEF_MTX_RESPFRM_RATE_TABLE_D3_F3	smac/hal/ssv6006c/ssv6006C_reg.h	16685;"	d
+DEF_MTX_RESPFRM_RATE_TABLE_D4_F4	smac/hal/ssv6006c/ssv6006C_reg.h	16686;"	d
+DEF_MTX_RESPFRM_RATE_TABLE_D5_F5	smac/hal/ssv6006c/ssv6006C_reg.h	16687;"	d
+DEF_MTX_RESPFRM_RATE_TABLE_D6_F6	smac/hal/ssv6006c/ssv6006C_reg.h	16688;"	d
+DEF_MTX_RESPFRM_RATE_TABLE_D7_F7	smac/hal/ssv6006c/ssv6006C_reg.h	16689;"	d
+DEF_MTX_RESPFRM_RATE_TABLE_D8_F8	smac/hal/ssv6006c/ssv6006C_reg.h	16690;"	d
+DEF_MTX_RESPFRM_RATE_TABLE_D9_F9	smac/hal/ssv6006c/ssv6006C_reg.h	16691;"	d
+DEF_MTX_RESPFRM_RATE_TABLE_DA_FA	smac/hal/ssv6006c/ssv6006C_reg.h	16692;"	d
+DEF_MTX_RESPFRM_RATE_TABLE_DB_FB	smac/hal/ssv6006c/ssv6006C_reg.h	16693;"	d
+DEF_MTX_RESPFRM_RATE_TABLE_DC_FC	smac/hal/ssv6006c/ssv6006C_reg.h	16694;"	d
+DEF_MTX_RESPFRM_RATE_TABLE_DD_FD	smac/hal/ssv6006c/ssv6006C_reg.h	16695;"	d
+DEF_MTX_RESPFRM_RATE_TABLE_DE_FE	smac/hal/ssv6006c/ssv6006C_reg.h	16696;"	d
+DEF_MTX_RESPFRM_RATE_TABLE_DF_FF	smac/hal/ssv6006c/ssv6006C_reg.h	16697;"	d
+DEF_MTX_RESPFRM_RATE_TABLE_EXCEPTION	smac/hal/ssv6006c/ssv6006C_reg.h	16658;"	d
+DEF_MTX_RETRY	include/ssv6200_reg.h	9229;"	d
+DEF_MTX_RETRY	smac/hal/ssv6006c/ssv6006C_reg.h	16810;"	d
+DEF_MTX_RTS_FAIL	include/ssv6200_reg.h	9232;"	d
+DEF_MTX_RTS_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	16813;"	d
+DEF_MTX_RTS_SUCCESS	include/ssv6200_reg.h	9231;"	d
+DEF_MTX_RTS_SUCCESS	smac/hal/ssv6006c/ssv6006C_reg.h	16812;"	d
+DEF_MTX_STATUS	include/ssv6200_reg.h	9071;"	d
+DEF_MTX_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	16618;"	d
+DEF_MTX_STATUS0	smac/hal/ssv6006c/ssv6006C_reg.h	16579;"	d
+DEF_MTX_STATUS4	smac/hal/ssv6006c/ssv6006C_reg.h	16580;"	d
+DEF_MTX_TIME_FINETUNE	smac/hal/ssv6006c/ssv6006C_reg.h	16617;"	d
+DEF_MTX_TIME_IFS	smac/hal/ssv6006c/ssv6006C_reg.h	16616;"	d
+DEF_MTX_TIME_TOUT	smac/hal/ssv6006c/ssv6006C_reg.h	16615;"	d
+DEF_MTX_TX_REPORT_OPTION	smac/hal/ssv6006c/ssv6006C_reg.h	16578;"	d
+DEF_MTX_WSID0_FRM	include/ssv6200_reg.h	9224;"	d
+DEF_MTX_WSID0_FRM	smac/hal/ssv6006c/ssv6006C_reg.h	16805;"	d
+DEF_MTX_WSID0_RETRY	include/ssv6200_reg.h	9225;"	d
+DEF_MTX_WSID0_RETRY	smac/hal/ssv6006c/ssv6006C_reg.h	16806;"	d
+DEF_MTX_WSID0_SUCC	include/ssv6200_reg.h	9223;"	d
+DEF_MTX_WSID0_SUCC	smac/hal/ssv6006c/ssv6006C_reg.h	16804;"	d
+DEF_MTX_WSID0_TOTAL	include/ssv6200_reg.h	9226;"	d
+DEF_MTX_WSID0_TOTAL	smac/hal/ssv6006c/ssv6006C_reg.h	16807;"	d
+DEF_MUL_ANS0	include/ssv6200_reg.h	8892;"	d
+DEF_MUL_ANS0	smac/hal/ssv6006c/ssv6006C_reg.h	16456;"	d
+DEF_MUL_ANS1	include/ssv6200_reg.h	8893;"	d
+DEF_MUL_ANS1	smac/hal/ssv6006c/ssv6006C_reg.h	16457;"	d
+DEF_MUL_OP1	include/ssv6200_reg.h	8890;"	d
+DEF_MUL_OP1	smac/hal/ssv6006c/ssv6006C_reg.h	16454;"	d
+DEF_MUL_OP2	include/ssv6200_reg.h	8891;"	d
+DEF_MUL_OP2	smac/hal/ssv6006c/ssv6006C_reg.h	16455;"	d
+DEF_N10CFG_DEF_IVB	smac/hal/ssv6006c/ssv6006C_reg.h	16116;"	d
+DEF_N10CFG_SETTING	smac/hal/ssv6006c/ssv6006C_reg.h	16117;"	d
+DEF_N10_DBG1	smac/hal/ssv6006c/ssv6006C_reg.h	16084;"	d
+DEF_N10_DBG2	smac/hal/ssv6006c/ssv6006C_reg.h	16085;"	d
+DEF_NAV_DATA	include/ssv6200_reg.h	8898;"	d
+DEF_NAV_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	16462;"	d
+DEF_OP_MODE1	smac/hal/ssv6006c/ssv6006C_reg.h	16797;"	d
+DEF_PACKET_COUNTER_INFO_0	include/ssv6200_reg.h	8861;"	d
+DEF_PACKET_COUNTER_INFO_1	include/ssv6200_reg.h	8862;"	d
+DEF_PACKET_COUNTER_INFO_2	include/ssv6200_reg.h	8863;"	d
+DEF_PACKET_COUNTER_INFO_3	include/ssv6200_reg.h	8864;"	d
+DEF_PACKET_COUNTER_INFO_4	include/ssv6200_reg.h	8865;"	d
+DEF_PACKET_COUNTER_INFO_5	include/ssv6200_reg.h	8866;"	d
+DEF_PACKET_COUNTER_INFO_6	include/ssv6200_reg.h	8867;"	d
+DEF_PACKET_COUNTER_INFO_7	include/ssv6200_reg.h	8868;"	d
+DEF_PACKET_ID_ALLOCATION_PRIORITY	include/ssv6200_reg.h	9202;"	d
+DEF_PACKET_ID_ALLOCATION_PRIORITY	smac/hal/ssv6006c/ssv6006C_reg.h	16776;"	d
+DEF_PAD11	include/ssv6200_reg.h	8621;"	d
+DEF_PAD15	include/ssv6200_reg.h	8622;"	d
+DEF_PAD16	include/ssv6200_reg.h	8623;"	d
+DEF_PAD17	include/ssv6200_reg.h	8624;"	d
+DEF_PAD18	include/ssv6200_reg.h	8625;"	d
+DEF_PAD19	include/ssv6200_reg.h	8626;"	d
+DEF_PAD20	include/ssv6200_reg.h	8627;"	d
+DEF_PAD21	include/ssv6200_reg.h	8628;"	d
+DEF_PAD22	include/ssv6200_reg.h	8629;"	d
+DEF_PAD231	include/ssv6200_reg.h	8667;"	d
+DEF_PAD24	include/ssv6200_reg.h	8630;"	d
+DEF_PAD25	include/ssv6200_reg.h	8631;"	d
+DEF_PAD27	include/ssv6200_reg.h	8632;"	d
+DEF_PAD28	include/ssv6200_reg.h	8633;"	d
+DEF_PAD29	include/ssv6200_reg.h	8634;"	d
+DEF_PAD30	include/ssv6200_reg.h	8635;"	d
+DEF_PAD31	include/ssv6200_reg.h	8636;"	d
+DEF_PAD32	include/ssv6200_reg.h	8637;"	d
+DEF_PAD33	include/ssv6200_reg.h	8638;"	d
+DEF_PAD34	include/ssv6200_reg.h	8639;"	d
+DEF_PAD42	include/ssv6200_reg.h	8640;"	d
+DEF_PAD43	include/ssv6200_reg.h	8641;"	d
+DEF_PAD44	include/ssv6200_reg.h	8642;"	d
+DEF_PAD45	include/ssv6200_reg.h	8643;"	d
+DEF_PAD46	include/ssv6200_reg.h	8644;"	d
+DEF_PAD47	include/ssv6200_reg.h	8645;"	d
+DEF_PAD48	include/ssv6200_reg.h	8646;"	d
+DEF_PAD49	include/ssv6200_reg.h	8647;"	d
+DEF_PAD50	include/ssv6200_reg.h	8648;"	d
+DEF_PAD51	include/ssv6200_reg.h	8649;"	d
+DEF_PAD52	include/ssv6200_reg.h	8650;"	d
+DEF_PAD53	include/ssv6200_reg.h	8651;"	d
+DEF_PAD54	include/ssv6200_reg.h	8652;"	d
+DEF_PAD56	include/ssv6200_reg.h	8653;"	d
+DEF_PAD57	include/ssv6200_reg.h	8654;"	d
+DEF_PAD58	include/ssv6200_reg.h	8655;"	d
+DEF_PAD59	include/ssv6200_reg.h	8656;"	d
+DEF_PAD6	include/ssv6200_reg.h	8617;"	d
+DEF_PAD60	include/ssv6200_reg.h	8657;"	d
+DEF_PAD61	include/ssv6200_reg.h	8658;"	d
+DEF_PAD62	include/ssv6200_reg.h	8659;"	d
+DEF_PAD64	include/ssv6200_reg.h	8660;"	d
+DEF_PAD65	include/ssv6200_reg.h	8661;"	d
+DEF_PAD66	include/ssv6200_reg.h	8662;"	d
+DEF_PAD67	include/ssv6200_reg.h	8664;"	d
+DEF_PAD68	include/ssv6200_reg.h	8663;"	d
+DEF_PAD69	include/ssv6200_reg.h	8665;"	d
+DEF_PAD7	include/ssv6200_reg.h	8618;"	d
+DEF_PAD70	include/ssv6200_reg.h	8666;"	d
+DEF_PAD8	include/ssv6200_reg.h	8619;"	d
+DEF_PAD9	include/ssv6200_reg.h	8620;"	d
+DEF_PAGE_TAG_STATUS_0	smac/hal/ssv6006c/ssv6006C_reg.h	17981;"	d
+DEF_PAGE_TAG_STATUS_1	smac/hal/ssv6006c/ssv6006C_reg.h	17982;"	d
+DEF_PAGE_TAG_STATUS_2	smac/hal/ssv6006c/ssv6006C_reg.h	17983;"	d
+DEF_PAGE_TAG_STATUS_3	smac/hal/ssv6006c/ssv6006C_reg.h	17984;"	d
+DEF_PAGE_TAG_STATUS_4	smac/hal/ssv6006c/ssv6006C_reg.h	17985;"	d
+DEF_PAGE_TAG_STATUS_5	smac/hal/ssv6006c/ssv6006C_reg.h	17986;"	d
+DEF_PAGE_TAG_STATUS_6	smac/hal/ssv6006c/ssv6006C_reg.h	17987;"	d
+DEF_PAGE_TAG_STATUS_7	smac/hal/ssv6006c/ssv6006C_reg.h	17988;"	d
+DEF_PEER_MAC0_0	include/ssv6200_reg.h	9120;"	d
+DEF_PEER_MAC0_0	smac/hal/ssv6006c/ssv6006C_reg.h	16739;"	d
+DEF_PEER_MAC0_1	include/ssv6200_reg.h	9121;"	d
+DEF_PEER_MAC0_1	smac/hal/ssv6006c/ssv6006C_reg.h	16740;"	d
+DEF_PEER_MAC1_0	include/ssv6200_reg.h	9139;"	d
+DEF_PEER_MAC1_0	smac/hal/ssv6006c/ssv6006C_reg.h	16758;"	d
+DEF_PEER_MAC1_1	include/ssv6200_reg.h	9140;"	d
+DEF_PEER_MAC1_1	smac/hal/ssv6006c/ssv6006C_reg.h	16759;"	d
+DEF_PEER_MAC2_0	smac/hal/ssv6006c/ssv6006C_reg.h	16865;"	d
+DEF_PEER_MAC2_1	smac/hal/ssv6006c/ssv6006C_reg.h	16866;"	d
+DEF_PEER_MAC3_0	smac/hal/ssv6006c/ssv6006C_reg.h	16884;"	d
+DEF_PEER_MAC3_1	smac/hal/ssv6006c/ssv6006C_reg.h	16885;"	d
+DEF_PEER_MAC4_0	smac/hal/ssv6006c/ssv6006C_reg.h	16903;"	d
+DEF_PEER_MAC4_1	smac/hal/ssv6006c/ssv6006C_reg.h	16904;"	d
+DEF_PEER_MAC5_0	smac/hal/ssv6006c/ssv6006C_reg.h	16922;"	d
+DEF_PEER_MAC5_1	smac/hal/ssv6006c/ssv6006C_reg.h	16923;"	d
+DEF_PEER_MAC6_0	smac/hal/ssv6006c/ssv6006C_reg.h	16941;"	d
+DEF_PEER_MAC6_1	smac/hal/ssv6006c/ssv6006C_reg.h	16942;"	d
+DEF_PEER_MAC7_0	smac/hal/ssv6006c/ssv6006C_reg.h	16960;"	d
+DEF_PEER_MAC7_1	smac/hal/ssv6006c/ssv6006C_reg.h	16961;"	d
+DEF_PHY_EN_0	include/ssv6200_reg.h	9394;"	d
+DEF_PHY_EN_1	include/ssv6200_reg.h	9395;"	d
+DEF_PHY_INFO	include/ssv6200_reg.h	9053;"	d
+DEF_PHY_INFO	smac/hal/ssv6006c/ssv6006C_reg.h	16570;"	d
+DEF_PHY_IQ_LOG_CFG0	include/ssv6200_reg.h	9356;"	d
+DEF_PHY_IQ_LOG_CFG0	smac/hal/ssv6006c/ssv6006C_reg.h	17938;"	d
+DEF_PHY_IQ_LOG_CFG1	include/ssv6200_reg.h	9357;"	d
+DEF_PHY_IQ_LOG_CFG1	smac/hal/ssv6006c/ssv6006C_reg.h	17939;"	d
+DEF_PHY_IQ_LOG_LEN	include/ssv6200_reg.h	9358;"	d
+DEF_PHY_IQ_LOG_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	17940;"	d
+DEF_PHY_IQ_LOG_PTR	include/ssv6200_reg.h	9359;"	d
+DEF_PHY_IQ_LOG_PTR	smac/hal/ssv6006c/ssv6006C_reg.h	17941;"	d
+DEF_PHY_PKT_GEN_0	include/ssv6200_reg.h	9397;"	d
+DEF_PHY_PKT_GEN_1	include/ssv6200_reg.h	9398;"	d
+DEF_PHY_PKT_GEN_2	include/ssv6200_reg.h	9399;"	d
+DEF_PHY_PKT_GEN_3	include/ssv6200_reg.h	9400;"	d
+DEF_PHY_PKT_GEN_4	include/ssv6200_reg.h	9401;"	d
+DEF_PHY_READ_REG_00_DIG_PWR	include/ssv6200_reg.h	9412;"	d
+DEF_PHY_READ_REG_01_RF_GAIN_PWR	include/ssv6200_reg.h	9413;"	d
+DEF_PHY_READ_REG_02_RF_GAIN_PWR	include/ssv6200_reg.h	9414;"	d
+DEF_PHY_READ_REG_03_RF_GAIN_PWR	include/ssv6200_reg.h	9415;"	d
+DEF_PHY_READ_REG_04	include/ssv6200_reg.h	9434;"	d
+DEF_PHY_READ_REG_05	include/ssv6200_reg.h	9435;"	d
+DEF_PHY_READ_REG_06_BIST	include/ssv6200_reg.h	9437;"	d
+DEF_PHY_READ_REG_07_BIST	include/ssv6200_reg.h	9438;"	d
+DEF_PHY_READ_REG_08_MTRX_MAC	include/ssv6200_reg.h	9440;"	d
+DEF_PHY_READ_REG_09_MTRX_MAC	include/ssv6200_reg.h	9441;"	d
+DEF_PHY_READ_TBUS	include/ssv6200_reg.h	9445;"	d
+DEF_PHY_REG_00	include/ssv6200_reg.h	9402;"	d
+DEF_PHY_REG_01	include/ssv6200_reg.h	9403;"	d
+DEF_PHY_REG_02_AGC	include/ssv6200_reg.h	9404;"	d
+DEF_PHY_REG_03_AGC	include/ssv6200_reg.h	9405;"	d
+DEF_PHY_REG_04_AGC	include/ssv6200_reg.h	9406;"	d
+DEF_PHY_REG_05_AGC	include/ssv6200_reg.h	9407;"	d
+DEF_PHY_REG_06_11B_DAGC	include/ssv6200_reg.h	9408;"	d
+DEF_PHY_REG_07_11B_DAGC	include/ssv6200_reg.h	9409;"	d
+DEF_PHY_REG_08_11GN_DAGC	include/ssv6200_reg.h	9410;"	d
+DEF_PHY_REG_09_11GN_DAGC	include/ssv6200_reg.h	9411;"	d
+DEF_PHY_REG_10_TX_DES	include/ssv6200_reg.h	9416;"	d
+DEF_PHY_REG_11_TX_DES	include/ssv6200_reg.h	9417;"	d
+DEF_PHY_REG_12_TX_DES	include/ssv6200_reg.h	9418;"	d
+DEF_PHY_REG_13_RX_DES	include/ssv6200_reg.h	9419;"	d
+DEF_PHY_REG_14_RX_DES	include/ssv6200_reg.h	9420;"	d
+DEF_PHY_REG_15_RX_DES	include/ssv6200_reg.h	9421;"	d
+DEF_PHY_REG_16_TX_DES_EXCP	include/ssv6200_reg.h	9422;"	d
+DEF_PHY_REG_17_TX_DES_EXCP	include/ssv6200_reg.h	9423;"	d
+DEF_PHY_REG_18_RSSI_SNR	include/ssv6200_reg.h	9424;"	d
+DEF_PHY_REG_19_DAC_MANUAL	include/ssv6200_reg.h	9425;"	d
+DEF_PHY_REG_20_MRX_CNT	include/ssv6200_reg.h	9426;"	d
+DEF_PHY_REG_21_TRX_RAMP	include/ssv6200_reg.h	9427;"	d
+DEF_PHY_REG_22_TRX_RAMP	include/ssv6200_reg.h	9428;"	d
+DEF_PHY_REG_23_ANT	include/ssv6200_reg.h	9429;"	d
+DEF_PHY_REG_24_MTX_LEN_CNT	include/ssv6200_reg.h	9430;"	d
+DEF_PHY_REG_25_MTX_LEN_CNT	include/ssv6200_reg.h	9431;"	d
+DEF_PHY_REG_26_MRX_LEN_CNT	include/ssv6200_reg.h	9432;"	d
+DEF_PHY_REG_27_MRX_LEN_CNT	include/ssv6200_reg.h	9433;"	d
+DEF_PHY_REG_28_BIST	include/ssv6200_reg.h	9436;"	d
+DEF_PHY_REG_29_MTRX_MAC	include/ssv6200_reg.h	9439;"	d
+DEF_PHY_REG_30_TX_UP_FIL	include/ssv6200_reg.h	9442;"	d
+DEF_PHY_REG_31_TX_UP_FIL	include/ssv6200_reg.h	9443;"	d
+DEF_PHY_REG_32_TX_UP_FIL	include/ssv6200_reg.h	9444;"	d
+DEF_PIN_SEL_0	include/ssv6200_reg.h	8668;"	d
+DEF_PIN_SEL_1	include/ssv6200_reg.h	8669;"	d
+DEF_PKT_IDTBL_0_STATUS	include/ssv6200_reg.h	9669;"	d
+DEF_PKT_IDTBL_1_STATUS	include/ssv6200_reg.h	9670;"	d
+DEF_PKT_IDTBL_2_STATUS	include/ssv6200_reg.h	9671;"	d
+DEF_PKT_IDTBL_3_STATUS	include/ssv6200_reg.h	9672;"	d
+DEF_PKT_NEQID_0_STATUS	include/ssv6200_reg.h	9681;"	d
+DEF_PKT_NEQID_1_STATUS	include/ssv6200_reg.h	9682;"	d
+DEF_PKT_NEQID_2_STATUS	include/ssv6200_reg.h	9683;"	d
+DEF_PKT_NEQID_3_STATUS	include/ssv6200_reg.h	9684;"	d
+DEF_PLATFORM_CLOCK_ENABLE	include/ssv6200_reg.h	8555;"	d
+DEF_PLATFORM_CLOCK_ENABLE	smac/hal/ssv6006c/ssv6006C_reg.h	16081;"	d
+DEF_PMU_0	include/ssv6200_reg.h	8834;"	d
+DEF_PMU_1	include/ssv6200_reg.h	8835;"	d
+DEF_PMU_2	include/ssv6200_reg.h	8836;"	d
+DEF_PMU_3	include/ssv6200_reg.h	8837;"	d
+DEF_PMU_CTRL_REG	smac/hal/ssv6006c/ssv6006C_reg.h	17693;"	d
+DEF_PMU_DPLL_REG_0	smac/hal/ssv6006c/ssv6006C_reg.h	17695;"	d
+DEF_PMU_DPLL_REG_1	smac/hal/ssv6006c/ssv6006C_reg.h	17696;"	d
+DEF_PMU_DPLL_REG_2	smac/hal/ssv6006c/ssv6006C_reg.h	17697;"	d
+DEF_PMU_DPLL_REG_3	smac/hal/ssv6006c/ssv6006C_reg.h	17698;"	d
+DEF_PMU_MODE_TRAN_INT	smac/hal/ssv6006c/ssv6006C_reg.h	16120;"	d
+DEF_PMU_RAM_00	smac/hal/ssv6006c/ssv6006C_reg.h	17700;"	d
+DEF_PMU_RAM_01	smac/hal/ssv6006c/ssv6006C_reg.h	17701;"	d
+DEF_PMU_RAM_02	smac/hal/ssv6006c/ssv6006C_reg.h	17702;"	d
+DEF_PMU_RAM_03	smac/hal/ssv6006c/ssv6006C_reg.h	17703;"	d
+DEF_PMU_RAM_04	smac/hal/ssv6006c/ssv6006C_reg.h	17704;"	d
+DEF_PMU_RAM_05	smac/hal/ssv6006c/ssv6006C_reg.h	17705;"	d
+DEF_PMU_RAM_06	smac/hal/ssv6006c/ssv6006C_reg.h	17706;"	d
+DEF_PMU_RAM_07	smac/hal/ssv6006c/ssv6006C_reg.h	17707;"	d
+DEF_PMU_RAM_08	smac/hal/ssv6006c/ssv6006C_reg.h	17708;"	d
+DEF_PMU_RAM_09	smac/hal/ssv6006c/ssv6006C_reg.h	17709;"	d
+DEF_PMU_RAM_10	smac/hal/ssv6006c/ssv6006C_reg.h	17710;"	d
+DEF_PMU_RAM_11	smac/hal/ssv6006c/ssv6006C_reg.h	17711;"	d
+DEF_PMU_RAM_12	smac/hal/ssv6006c/ssv6006C_reg.h	17712;"	d
+DEF_PMU_RAM_13	smac/hal/ssv6006c/ssv6006C_reg.h	17713;"	d
+DEF_PMU_RAM_14	smac/hal/ssv6006c/ssv6006C_reg.h	17714;"	d
+DEF_PMU_RAM_15	smac/hal/ssv6006c/ssv6006C_reg.h	17715;"	d
+DEF_PMU_REG_1	smac/hal/ssv6006c/ssv6006C_reg.h	17681;"	d
+DEF_PMU_REG_2	smac/hal/ssv6006c/ssv6006C_reg.h	17682;"	d
+DEF_PMU_REG_3	smac/hal/ssv6006c/ssv6006C_reg.h	17683;"	d
+DEF_PMU_REG_4	smac/hal/ssv6006c/ssv6006C_reg.h	17684;"	d
+DEF_PMU_REG_5	smac/hal/ssv6006c/ssv6006C_reg.h	17685;"	d
+DEF_PMU_REG_6	smac/hal/ssv6006c/ssv6006C_reg.h	17686;"	d
+DEF_PMU_RTC_REG_0	smac/hal/ssv6006c/ssv6006C_reg.h	17689;"	d
+DEF_PMU_RTC_REG_1	smac/hal/ssv6006c/ssv6006C_reg.h	17690;"	d
+DEF_PMU_RTC_REG_2	smac/hal/ssv6006c/ssv6006C_reg.h	17691;"	d
+DEF_PMU_RTC_REG_3	smac/hal/ssv6006c/ssv6006C_reg.h	17692;"	d
+DEF_PMU_SLEEP_MODE_REG	smac/hal/ssv6006c/ssv6006C_reg.h	17699;"	d
+DEF_PMU_SLEEP_REG_1	smac/hal/ssv6006c/ssv6006C_reg.h	17687;"	d
+DEF_PMU_SLEEP_REG_2	smac/hal/ssv6006c/ssv6006C_reg.h	17688;"	d
+DEF_PMU_STATE_REG	smac/hal/ssv6006c/ssv6006C_reg.h	17694;"	d
+DEF_POSTMASK_TYPHOST_INT_MAP	smac/hal/ssv6006c/ssv6006C_reg.h	16338;"	d
+DEF_POSTMASK_TYPHOST_INT_MAP_02	smac/hal/ssv6006c/ssv6006C_reg.h	16329;"	d
+DEF_POSTMASK_TYPHOST_INT_MAP_15	smac/hal/ssv6006c/ssv6006C_reg.h	16332;"	d
+DEF_POSTMASK_TYPHOST_INT_MAP_31	smac/hal/ssv6006c/ssv6006C_reg.h	16335;"	d
+DEF_POSTMASK_TYPMCU_INT_MAP	smac/hal/ssv6006c/ssv6006C_reg.h	16351;"	d
+DEF_POSTMASK_TYPMCU_INT_MAP_02	smac/hal/ssv6006c/ssv6006C_reg.h	16342;"	d
+DEF_POSTMASK_TYPMCU_INT_MAP_15	smac/hal/ssv6006c/ssv6006C_reg.h	16345;"	d
+DEF_POSTMASK_TYPMCU_INT_MAP_31	smac/hal/ssv6006c/ssv6006C_reg.h	16348;"	d
+DEF_POWER_ON_OFF_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	16126;"	d
+DEF_POWER_SAVING_PEER_REJECT_FUNCTION	smac/hal/ssv6006c/ssv6006C_reg.h	16441;"	d
+DEF_POWER_SW_INFO	smac/hal/ssv6006c/ssv6006C_reg.h	16100;"	d
+DEF_PRESCALER_USTIMER	include/ssv6200_reg.h	8575;"	d
+DEF_PRESCALER_USTIMER	smac/hal/ssv6006c/ssv6006C_reg.h	16128;"	d
+DEF_PWM_0_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	16163;"	d
+DEF_PWM_0_SET	smac/hal/ssv6006c/ssv6006C_reg.h	16164;"	d
+DEF_PWM_1_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	16165;"	d
+DEF_PWM_1_SET	smac/hal/ssv6006c/ssv6006C_reg.h	16166;"	d
+DEF_PWM_2_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	16167;"	d
+DEF_PWM_2_SET	smac/hal/ssv6006c/ssv6006C_reg.h	16168;"	d
+DEF_PWM_3_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	16169;"	d
+DEF_PWM_3_SET	smac/hal/ssv6006c/ssv6006C_reg.h	16170;"	d
+DEF_PWM_4_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	16171;"	d
+DEF_PWM_4_SET	smac/hal/ssv6006c/ssv6006C_reg.h	16172;"	d
+DEF_PWM_A	include/ssv6200_reg.h	8571;"	d
+DEF_PWM_B	include/ssv6200_reg.h	8572;"	d
+DEF_R5_RESP_FLAG_OUT_TIMING	include/ssv6200_reg.h	8688;"	d
+DEF_R5_RESP_FLAG_OUT_TIMING	smac/hal/ssv6006c/ssv6006C_reg.h	16201;"	d
+DEF_RANDOM_CTL	smac/hal/ssv6006c/ssv6006C_reg.h	16801;"	d
+DEF_RAND_EN	include/ssv6200_reg.h	8888;"	d
+DEF_RAND_EN	smac/hal/ssv6006c/ssv6006C_reg.h	16452;"	d
+DEF_RAND_NUM	include/ssv6200_reg.h	8889;"	d
+DEF_RAND_NUM	smac/hal/ssv6006c/ssv6006C_reg.h	16453;"	d
+DEF_RAW_TYPHOST_INT_MAP	smac/hal/ssv6006c/ssv6006C_reg.h	16337;"	d
+DEF_RAW_TYPHOST_INT_MAP_02	smac/hal/ssv6006c/ssv6006C_reg.h	16328;"	d
+DEF_RAW_TYPHOST_INT_MAP_15	smac/hal/ssv6006c/ssv6006C_reg.h	16331;"	d
+DEF_RAW_TYPHOST_INT_MAP_31	smac/hal/ssv6006c/ssv6006C_reg.h	16334;"	d
+DEF_RAW_TYPMCU_INT_MAP	smac/hal/ssv6006c/ssv6006C_reg.h	16350;"	d
+DEF_RAW_TYPMCU_INT_MAP_02	smac/hal/ssv6006c/ssv6006C_reg.h	16341;"	d
+DEF_RAW_TYPMCU_INT_MAP_15	smac/hal/ssv6006c/ssv6006C_reg.h	16344;"	d
+DEF_RAW_TYPMCU_INT_MAP_31	smac/hal/ssv6006c/ssv6006C_reg.h	16347;"	d
+DEF_RCAL_REGISTER	include/ssv6200_reg.h	9644;"	d
+DEF_RC_OSC_32K_CAL_REGISTERS	include/ssv6200_reg.h	9650;"	d
+DEF_RD_FFIN_FULL	include/ssv6200_reg.h	9335;"	d
+DEF_RD_FFIN_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	17912;"	d
+DEF_RD_FFOUT_CNT1	include/ssv6200_reg.h	9343;"	d
+DEF_RD_FFOUT_CNT1	smac/hal/ssv6006c/ssv6006C_reg.h	17924;"	d
+DEF_RD_FFOUT_CNT2	include/ssv6200_reg.h	9344;"	d
+DEF_RD_FFOUT_CNT2	smac/hal/ssv6006c/ssv6006C_reg.h	17925;"	d
+DEF_RD_FFOUT_CNT3	include/ssv6200_reg.h	9345;"	d
+DEF_RD_FFOUT_CNT3	smac/hal/ssv6006c/ssv6006C_reg.h	17926;"	d
+DEF_RD_FFOUT_FULL	include/ssv6200_reg.h	9346;"	d
+DEF_RD_FFOUT_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	17927;"	d
+DEF_RD_ID0	include/ssv6200_reg.h	9363;"	d
+DEF_RD_ID0	smac/hal/ssv6006c/ssv6006C_reg.h	17945;"	d
+DEF_RD_ID1	include/ssv6200_reg.h	9364;"	d
+DEF_RD_ID1	smac/hal/ssv6006c/ssv6006C_reg.h	17946;"	d
+DEF_RD_ID2	include/ssv6200_reg.h	9382;"	d
+DEF_RD_ID2	smac/hal/ssv6006c/ssv6006C_reg.h	17964;"	d
+DEF_RD_ID3	include/ssv6200_reg.h	9383;"	d
+DEF_RD_ID3	smac/hal/ssv6006c/ssv6006C_reg.h	17965;"	d
+DEF_RD_IN_FFCNT1	include/ssv6200_reg.h	9333;"	d
+DEF_RD_IN_FFCNT1	smac/hal/ssv6006c/ssv6006C_reg.h	17910;"	d
+DEF_RD_IN_FFCNT2	include/ssv6200_reg.h	9334;"	d
+DEF_RD_IN_FFCNT2	smac/hal/ssv6006c/ssv6006C_reg.h	17911;"	d
+DEF_READ_ONLY_FLAGS_ADC	smac/hal/ssv6006c/ssv6006C_reg.h	17426;"	d
+DEF_READ_ONLY_FLAGS_SX_2_4GB_1	smac/hal/ssv6006c/ssv6006C_reg.h	17427;"	d
+DEF_READ_ONLY_FLAGS_SX_2_4GB_2	smac/hal/ssv6006c/ssv6006C_reg.h	17428;"	d
+DEF_READ_ONLY_FLAGS_SX_5GB_1	smac/hal/ssv6006c/ssv6006C_reg.h	17479;"	d
+DEF_READ_ONLY_FLAGS_SX_5GB_2	smac/hal/ssv6006c/ssv6006C_reg.h	17480;"	d
+DEF_READ_ONLY_FLAGS_SX_5GB_3	smac/hal/ssv6006c/ssv6006C_reg.h	17481;"	d
+DEF_REASON_TRAP0	include/ssv6200_reg.h	9211;"	d
+DEF_REASON_TRAP0	smac/hal/ssv6006c/ssv6006C_reg.h	16785;"	d
+DEF_REASON_TRAP1	include/ssv6200_reg.h	9212;"	d
+DEF_REASON_TRAP1	smac/hal/ssv6006c/ssv6006C_reg.h	16786;"	d
+DEF_REG_LEN_CTRL	include/ssv6200_reg.h	9656;"	d
+DEF_REMAINING_RX_PACKET_LENGTH	smac/hal/ssv6006c/ssv6006C_reg.h	16397;"	d
+DEF_REQ_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	17980;"	d
+DEF_RESET_RX_FIFO	smac/hal/ssv6006c/ssv6006C_reg.h	16033;"	d
+DEF_RESET_TX_FIFO	smac/hal/ssv6006c/ssv6006C_reg.h	16034;"	d
+DEF_RF_5G_TX_PARTITION_BAND1	smac/hal/ssv6006c/ssv6006C_reg.h	17522;"	d
+DEF_RF_5G_TX_PARTITION_BAND2	smac/hal/ssv6006c/ssv6006C_reg.h	17523;"	d
+DEF_RF_CONTROL_0	include/ssv6200_reg.h	9565;"	d
+DEF_RF_CONTROL_1	include/ssv6200_reg.h	9566;"	d
+DEF_RF_D_CAL_TOP_0	smac/hal/ssv6006c/ssv6006C_reg.h	17500;"	d
+DEF_RF_D_CAL_TOP_1	smac/hal/ssv6006c/ssv6006C_reg.h	17501;"	d
+DEF_RF_D_CAL_TOP_2	smac/hal/ssv6006c/ssv6006C_reg.h	17502;"	d
+DEF_RF_D_CAL_TOP_3	smac/hal/ssv6006c/ssv6006C_reg.h	17503;"	d
+DEF_RF_D_CAL_TOP_4	smac/hal/ssv6006c/ssv6006C_reg.h	17504;"	d
+DEF_RF_D_CAL_TOP_5	smac/hal/ssv6006c/ssv6006C_reg.h	17505;"	d
+DEF_RF_D_CAL_TOP_6	smac/hal/ssv6006c/ssv6006C_reg.h	17506;"	d
+DEF_RF_D_CAL_TOP_7	smac/hal/ssv6006c/ssv6006C_reg.h	17507;"	d
+DEF_RF_D_CAL_TOP_8	smac/hal/ssv6006c/ssv6006C_reg.h	17508;"	d
+DEF_RF_D_CAL_TOP_9	smac/hal/ssv6006c/ssv6006C_reg.h	17509;"	d
+DEF_RF_D_DIGITAL_DEBUG_PORT_REGISTER	include/ssv6200_reg.h	9651;"	d
+DEF_RF_D_MODE_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	17513;"	d
+DEF_RF_IQ_CONTROL_0	include/ssv6200_reg.h	9576;"	d
+DEF_RF_IQ_CONTROL_1	include/ssv6200_reg.h	9577;"	d
+DEF_RF_IQ_CONTROL_2	include/ssv6200_reg.h	9578;"	d
+DEF_RF_IQ_CONTROL_3	include/ssv6200_reg.h	9579;"	d
+DEF_ROM_PATCH00_0	smac/hal/ssv6006c/ssv6006C_reg.h	16132;"	d
+DEF_ROM_PATCH00_1	smac/hal/ssv6006c/ssv6006C_reg.h	16133;"	d
+DEF_ROM_PATCH01_0	smac/hal/ssv6006c/ssv6006C_reg.h	16134;"	d
+DEF_ROM_PATCH01_1	smac/hal/ssv6006c/ssv6006C_reg.h	16135;"	d
+DEF_ROM_PATCH02_0	smac/hal/ssv6006c/ssv6006C_reg.h	16363;"	d
+DEF_ROM_PATCH02_1	smac/hal/ssv6006c/ssv6006C_reg.h	16364;"	d
+DEF_ROM_PATCH03_0	smac/hal/ssv6006c/ssv6006C_reg.h	16365;"	d
+DEF_ROM_PATCH03_1	smac/hal/ssv6006c/ssv6006C_reg.h	16366;"	d
+DEF_ROM_PATCH04_0	smac/hal/ssv6006c/ssv6006C_reg.h	16367;"	d
+DEF_ROM_PATCH04_1	smac/hal/ssv6006c/ssv6006C_reg.h	16368;"	d
+DEF_ROM_PATCH05_0	smac/hal/ssv6006c/ssv6006C_reg.h	16369;"	d
+DEF_ROM_PATCH05_1	smac/hal/ssv6006c/ssv6006C_reg.h	16370;"	d
+DEF_ROM_PATCH06_0	smac/hal/ssv6006c/ssv6006C_reg.h	16371;"	d
+DEF_ROM_PATCH06_1	smac/hal/ssv6006c/ssv6006C_reg.h	16372;"	d
+DEF_ROM_PATCH07_0	smac/hal/ssv6006c/ssv6006C_reg.h	16373;"	d
+DEF_ROM_PATCH07_1	smac/hal/ssv6006c/ssv6006C_reg.h	16374;"	d
+DEF_ROM_PATCH08_0	smac/hal/ssv6006c/ssv6006C_reg.h	16375;"	d
+DEF_ROM_PATCH08_1	smac/hal/ssv6006c/ssv6006C_reg.h	16376;"	d
+DEF_ROM_PATCH09_0	smac/hal/ssv6006c/ssv6006C_reg.h	16377;"	d
+DEF_ROM_PATCH09_1	smac/hal/ssv6006c/ssv6006C_reg.h	16378;"	d
+DEF_ROM_PATCH10_0	smac/hal/ssv6006c/ssv6006C_reg.h	16379;"	d
+DEF_ROM_PATCH10_1	smac/hal/ssv6006c/ssv6006C_reg.h	16380;"	d
+DEF_ROM_PATCH11_0	smac/hal/ssv6006c/ssv6006C_reg.h	16381;"	d
+DEF_ROM_PATCH11_1	smac/hal/ssv6006c/ssv6006C_reg.h	16382;"	d
+DEF_ROM_PATCH12_0	smac/hal/ssv6006c/ssv6006C_reg.h	16383;"	d
+DEF_ROM_PATCH12_1	smac/hal/ssv6006c/ssv6006C_reg.h	16384;"	d
+DEF_ROM_PATCH13_0	smac/hal/ssv6006c/ssv6006C_reg.h	16385;"	d
+DEF_ROM_PATCH13_1	smac/hal/ssv6006c/ssv6006C_reg.h	16386;"	d
+DEF_ROM_PATCH14_0	smac/hal/ssv6006c/ssv6006C_reg.h	16387;"	d
+DEF_ROM_PATCH14_1	smac/hal/ssv6006c/ssv6006C_reg.h	16388;"	d
+DEF_ROM_PATCH15_0	smac/hal/ssv6006c/ssv6006C_reg.h	16389;"	d
+DEF_ROM_PATCH15_1	smac/hal/ssv6006c/ssv6006C_reg.h	16390;"	d
+DEF_ROM_READ_PROT	smac/hal/ssv6006c/ssv6006C_reg.h	16087;"	d
+DEF_ROPMUSTATE	smac/hal/ssv6006c/ssv6006C_reg.h	16086;"	d
+DEF_RTC_1	include/ssv6200_reg.h	8838;"	d
+DEF_RTC_2	include/ssv6200_reg.h	8839;"	d
+DEF_RTC_3R	include/ssv6200_reg.h	8841;"	d
+DEF_RTC_3W	include/ssv6200_reg.h	8840;"	d
+DEF_RTC_4	include/ssv6200_reg.h	8842;"	d
+DEF_RTN_STA	include/ssv6200_reg.h	9374;"	d
+DEF_RTN_STA	smac/hal/ssv6006c/ssv6006C_reg.h	17956;"	d
+DEF_RX_11B_CCA_0	include/ssv6200_reg.h	9493;"	d
+DEF_RX_11B_CCA_1	include/ssv6200_reg.h	9494;"	d
+DEF_RX_11B_CCA_CONTROL	include/ssv6200_reg.h	9507;"	d
+DEF_RX_11B_CE_CNT_THRESHOLD	include/ssv6200_reg.h	9497;"	d
+DEF_RX_11B_CE_MU_0	include/ssv6200_reg.h	9498;"	d
+DEF_RX_11B_CE_MU_1	include/ssv6200_reg.h	9499;"	d
+DEF_RX_11B_CIT_CNT_THRESHOLD	include/ssv6200_reg.h	9504;"	d
+DEF_RX_11B_DES_DLY	include/ssv6200_reg.h	9492;"	d
+DEF_RX_11B_EQ_CH_MAIN_TAP	include/ssv6200_reg.h	9505;"	d
+DEF_RX_11B_EQ_CR_KP_KI	include/ssv6200_reg.h	9502;"	d
+DEF_RX_11B_EQ_MU_0	include/ssv6200_reg.h	9500;"	d
+DEF_RX_11B_EQ_MU_1	include/ssv6200_reg.h	9501;"	d
+DEF_RX_11B_FREQUENCY_OFFSET	include/ssv6200_reg.h	9508;"	d
+DEF_RX_11B_LPF_RATE	include/ssv6200_reg.h	9503;"	d
+DEF_RX_11B_PKT_CCA_AND_PKT_CNT	include/ssv6200_reg.h	9512;"	d
+DEF_RX_11B_PKT_ERR_AND_PKT_ERR_CNT	include/ssv6200_reg.h	9511;"	d
+DEF_RX_11B_PKT_STAT_EN	include/ssv6200_reg.h	9515;"	d
+DEF_RX_11B_SEARCH_CNT_TH	include/ssv6200_reg.h	9506;"	d
+DEF_RX_11B_SFD_CRC_CNT	include/ssv6200_reg.h	9510;"	d
+DEF_RX_11B_SFD_FIELD_1	include/ssv6200_reg.h	9514;"	d
+DEF_RX_11B_SFD_FILED_0	include/ssv6200_reg.h	9513;"	d
+DEF_RX_11B_SNR_RSSI	include/ssv6200_reg.h	9509;"	d
+DEF_RX_11B_SOFT_RST	include/ssv6200_reg.h	9516;"	d
+DEF_RX_11B_TR_KP_KI_0	include/ssv6200_reg.h	9495;"	d
+DEF_RX_11B_TR_KP_KI_1	include/ssv6200_reg.h	9496;"	d
+DEF_RX_11GN_BIST_0	include/ssv6200_reg.h	9548;"	d
+DEF_RX_11GN_BIST_1	include/ssv6200_reg.h	9549;"	d
+DEF_RX_11GN_BIST_2	include/ssv6200_reg.h	9550;"	d
+DEF_RX_11GN_BIST_3	include/ssv6200_reg.h	9551;"	d
+DEF_RX_11GN_BIST_4	include/ssv6200_reg.h	9552;"	d
+DEF_RX_11GN_BIST_5	include/ssv6200_reg.h	9553;"	d
+DEF_RX_11GN_CCA_0	include/ssv6200_reg.h	9525;"	d
+DEF_RX_11GN_CCA_1	include/ssv6200_reg.h	9526;"	d
+DEF_RX_11GN_CCA_2	include/ssv6200_reg.h	9527;"	d
+DEF_RX_11GN_CCA_ATCOR_RE_CHECK	include/ssv6200_reg.h	9539;"	d
+DEF_RX_11GN_CCA_CNT	include/ssv6200_reg.h	9538;"	d
+DEF_RX_11GN_CCA_FFT_SCALE	include/ssv6200_reg.h	9528;"	d
+DEF_RX_11GN_CCA_PWR	include/ssv6200_reg.h	9537;"	d
+DEF_RX_11GN_CHANNEL_UPDATE	include/ssv6200_reg.h	9543;"	d
+DEF_RX_11GN_DES_DLY	include/ssv6200_reg.h	9521;"	d
+DEF_RX_11GN_ERR_UPDATE	include/ssv6200_reg.h	9541;"	d
+DEF_RX_11GN_FREQ_OFFSET	include/ssv6200_reg.h	9556;"	d
+DEF_RX_11GN_PKT_CCA_AND_PKT_CNT	include/ssv6200_reg.h	9560;"	d
+DEF_RX_11GN_PKT_ERR_CNT	include/ssv6200_reg.h	9559;"	d
+DEF_RX_11GN_PKT_FORMAT_0	include/ssv6200_reg.h	9544;"	d
+DEF_RX_11GN_PKT_FORMAT_1	include/ssv6200_reg.h	9545;"	d
+DEF_RX_11GN_RATE	include/ssv6200_reg.h	9562;"	d
+DEF_RX_11GN_READ_0	include/ssv6200_reg.h	9555;"	d
+DEF_RX_11GN_SERVICE_LENGTH_FIELD	include/ssv6200_reg.h	9561;"	d
+DEF_RX_11GN_SHORT_GI	include/ssv6200_reg.h	9542;"	d
+DEF_RX_11GN_SIGNAL_FIELD_0	include/ssv6200_reg.h	9557;"	d
+DEF_RX_11GN_SIGNAL_FIELD_1	include/ssv6200_reg.h	9558;"	d
+DEF_RX_11GN_SOFT_DEMAP_0	include/ssv6200_reg.h	9529;"	d
+DEF_RX_11GN_SOFT_DEMAP_1	include/ssv6200_reg.h	9530;"	d
+DEF_RX_11GN_SOFT_DEMAP_2	include/ssv6200_reg.h	9531;"	d
+DEF_RX_11GN_SOFT_DEMAP_3	include/ssv6200_reg.h	9532;"	d
+DEF_RX_11GN_SOFT_DEMAP_4	include/ssv6200_reg.h	9533;"	d
+DEF_RX_11GN_SOFT_DEMAP_5	include/ssv6200_reg.h	9534;"	d
+DEF_RX_11GN_SOFT_RST	include/ssv6200_reg.h	9564;"	d
+DEF_RX_11GN_SPECTRUM_ANALYZER	include/ssv6200_reg.h	9554;"	d
+DEF_RX_11GN_STAT_EN	include/ssv6200_reg.h	9563;"	d
+DEF_RX_11GN_STBC_TR_KP_KI	include/ssv6200_reg.h	9547;"	d
+DEF_RX_11GN_SYM_BOUND_0	include/ssv6200_reg.h	9535;"	d
+DEF_RX_11GN_SYM_BOUND_1	include/ssv6200_reg.h	9536;"	d
+DEF_RX_11GN_TR_0	include/ssv6200_reg.h	9522;"	d
+DEF_RX_11GN_TR_1	include/ssv6200_reg.h	9523;"	d
+DEF_RX_11GN_TR_2	include/ssv6200_reg.h	9524;"	d
+DEF_RX_11GN_TX_TIME	include/ssv6200_reg.h	9546;"	d
+DEF_RX_11GN_VTB_TB	include/ssv6200_reg.h	9540;"	d
+DEF_RX_ADC_REGISTER	include/ssv6200_reg.h	9623;"	d
+DEF_RX_COMPENSATION_CONTROL	include/ssv6200_reg.h	9571;"	d
+DEF_RX_DATA_CMD52_ABORT_COUNT	include/ssv6200_reg.h	8696;"	d
+DEF_RX_DC_CAL_RESULT	smac/hal/ssv6006c/ssv6006C_reg.h	17519;"	d
+DEF_RX_DROP_COUNT	smac/hal/ssv6006c/ssv6006C_reg.h	16431;"	d
+DEF_RX_ETHER_TYPE_0	include/ssv6200_reg.h	8859;"	d
+DEF_RX_ETHER_TYPE_0	smac/hal/ssv6006c/ssv6006C_reg.h	16412;"	d
+DEF_RX_ETHER_TYPE_1	include/ssv6200_reg.h	8860;"	d
+DEF_RX_ETHER_TYPE_1	smac/hal/ssv6006c/ssv6006C_reg.h	16413;"	d
+DEF_RX_FE_GAIN_DECODER_REGISTER_1	include/ssv6200_reg.h	9618;"	d
+DEF_RX_FE_GAIN_DECODER_REGISTER_2	include/ssv6200_reg.h	9619;"	d
+DEF_RX_FE_GAIN_DECODER_REGISTER_3	include/ssv6200_reg.h	9620;"	d
+DEF_RX_FE_GAIN_DECODER_REGISTER_4	include/ssv6200_reg.h	9621;"	d
+DEF_RX_FE_REGISTER_1	include/ssv6200_reg.h	9617;"	d
+DEF_RX_FLOW_CTRL	include/ssv6200_reg.h	9014;"	d
+DEF_RX_FLOW_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	16540;"	d
+DEF_RX_FLOW_DATA	include/ssv6200_reg.h	9012;"	d
+DEF_RX_FLOW_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	16538;"	d
+DEF_RX_FLOW_MNG	include/ssv6200_reg.h	9013;"	d
+DEF_RX_FLOW_MNG	smac/hal/ssv6006c/ssv6006C_reg.h	16539;"	d
+DEF_RX_HCI_EXP_0_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	16443;"	d
+DEF_RX_HCI_EXP_0_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	16444;"	d
+DEF_RX_HOST_EVENT_COUNT	smac/hal/ssv6006c/ssv6006C_reg.h	16433;"	d
+DEF_RX_ID0	include/ssv6200_reg.h	9372;"	d
+DEF_RX_ID0	smac/hal/ssv6006c/ssv6006C_reg.h	17954;"	d
+DEF_RX_ID1	include/ssv6200_reg.h	9373;"	d
+DEF_RX_ID1	smac/hal/ssv6006c/ssv6006C_reg.h	17955;"	d
+DEF_RX_ID2	include/ssv6200_reg.h	9386;"	d
+DEF_RX_ID2	smac/hal/ssv6006c/ssv6006C_reg.h	17968;"	d
+DEF_RX_ID3	include/ssv6200_reg.h	9387;"	d
+DEF_RX_ID3	smac/hal/ssv6006c/ssv6006C_reg.h	17969;"	d
+DEF_RX_OBSERVATION_CIRCUIT_0	include/ssv6200_reg.h	9572;"	d
+DEF_RX_OBSERVATION_CIRCUIT_1	include/ssv6200_reg.h	9573;"	d
+DEF_RX_OBSERVATION_CIRCUIT_2	include/ssv6200_reg.h	9574;"	d
+DEF_RX_OBSERVATION_CIRCUIT_3	include/ssv6200_reg.h	9575;"	d
+DEF_RX_PACKET_COUNTER	smac/hal/ssv6006c/ssv6006C_reg.h	16435;"	d
+DEF_RX_PACKET_LENGTH_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	16398;"	d
+DEF_RX_QUOTA	include/ssv6200_reg.h	8744;"	d
+DEF_RX_RC_VALUE_TUNE	smac/hal/ssv6006c/ssv6006C_reg.h	17494;"	d
+DEF_RX_RESCUE_HELPER	smac/hal/ssv6006c/ssv6006C_reg.h	16416;"	d
+DEF_RX_TIME_STAMP_CFG	include/ssv6200_reg.h	9015;"	d
+DEF_RX_TIME_STAMP_CFG	smac/hal/ssv6006c/ssv6006C_reg.h	16541;"	d
+DEF_RX_TRAP_COUNT	smac/hal/ssv6006c/ssv6006C_reg.h	16429;"	d
+DEF_RX_TX_FSM_REGISTER	include/ssv6200_reg.h	9622;"	d
+DEF_R_TRX_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	16036;"	d
+DEF_SBUS_CFG0_1	smac/hal/ssv6006c/ssv6006C_reg.h	16006;"	d
+DEF_SBUS_CFG0_2	smac/hal/ssv6006c/ssv6006C_reg.h	16007;"	d
+DEF_SBUS_CFG1_1	smac/hal/ssv6006c/ssv6006C_reg.h	16012;"	d
+DEF_SBUS_CFG1_2	smac/hal/ssv6006c/ssv6006C_reg.h	16013;"	d
+DEF_SBUS_CH_EN	smac/hal/ssv6006c/ssv6006C_reg.h	16027;"	d
+DEF_SBUS_CLRERR	smac/hal/ssv6006c/ssv6006C_reg.h	16021;"	d
+DEF_SBUS_CLRTR	smac/hal/ssv6006c/ssv6006C_reg.h	16020;"	d
+DEF_SBUS_CTL0_1	smac/hal/ssv6006c/ssv6006C_reg.h	16004;"	d
+DEF_SBUS_CTL0_2	smac/hal/ssv6006c/ssv6006C_reg.h	16005;"	d
+DEF_SBUS_CTL1_1	smac/hal/ssv6006c/ssv6006C_reg.h	16010;"	d
+DEF_SBUS_CTL1_2	smac/hal/ssv6006c/ssv6006C_reg.h	16011;"	d
+DEF_SBUS_DAR0	smac/hal/ssv6006c/ssv6006C_reg.h	16003;"	d
+DEF_SBUS_DAR1	smac/hal/ssv6006c/ssv6006C_reg.h	16009;"	d
+DEF_SBUS_DMA_EN	smac/hal/ssv6006c/ssv6006C_reg.h	16026;"	d
+DEF_SBUS_MASKERR	smac/hal/ssv6006c/ssv6006C_reg.h	16019;"	d
+DEF_SBUS_MASKTR	smac/hal/ssv6006c/ssv6006C_reg.h	16018;"	d
+DEF_SBUS_RAWERR	smac/hal/ssv6006c/ssv6006C_reg.h	16015;"	d
+DEF_SBUS_RAWTR	smac/hal/ssv6006c/ssv6006C_reg.h	16014;"	d
+DEF_SBUS_SAR0	smac/hal/ssv6006c/ssv6006C_reg.h	16002;"	d
+DEF_SBUS_SAR1	smac/hal/ssv6006c/ssv6006C_reg.h	16008;"	d
+DEF_SBUS_SHS_DST_REQ_CFG	smac/hal/ssv6006c/ssv6006C_reg.h	16023;"	d
+DEF_SBUS_SHS_DST_SREQ_CFG	smac/hal/ssv6006c/ssv6006C_reg.h	16025;"	d
+DEF_SBUS_SHS_SRC_REQ_CFG	smac/hal/ssv6006c/ssv6006C_reg.h	16022;"	d
+DEF_SBUS_SHS_SRC_SREQ_CFG	smac/hal/ssv6006c/ssv6006C_reg.h	16024;"	d
+DEF_SBUS_STATUSERR	smac/hal/ssv6006c/ssv6006C_reg.h	16017;"	d
+DEF_SBUS_STATUSTR	smac/hal/ssv6006c/ssv6006C_reg.h	16016;"	d
+DEF_SCRT_SET	include/ssv6200_reg.h	9218;"	d
+DEF_SCRT_SET	smac/hal/ssv6006c/ssv6006C_reg.h	16791;"	d
+DEF_SCRT_STATE	include/ssv6200_reg.h	9215;"	d
+DEF_SCRT_STATE	smac/hal/ssv6006c/ssv6006C_reg.h	16792;"	d
+DEF_SDIO_BLOCK_CNT_INFO	include/ssv6200_reg.h	8695;"	d
+DEF_SDIO_BUS_STATE_DEBUG_MONITOR	include/ssv6200_reg.h	8686;"	d
+DEF_SDIO_BYTE_MODE_BATCH_SIZE_REG	include/ssv6200_reg.h	8683;"	d
+DEF_SDIO_BYTE_MODE_BATCH_SIZE_REG	smac/hal/ssv6006c/ssv6006C_reg.h	16199;"	d
+DEF_SDIO_CARD_STATUS_REG	include/ssv6200_reg.h	8687;"	d
+DEF_SDIO_CARD_STATUS_REG	smac/hal/ssv6006c/ssv6006C_reg.h	16200;"	d
+DEF_SDIO_COMMAND_LOG_DATA_31_0	include/ssv6200_reg.h	8702;"	d
+DEF_SDIO_COMMAND_LOG_DATA_63_32	include/ssv6200_reg.h	8703;"	d
+DEF_SDIO_CRC7_CRC16_ERROR_REG	include/ssv6200_reg.h	8694;"	d
+DEF_SDIO_DELAY_CHAIN_0	smac/hal/ssv6006c/ssv6006C_reg.h	16202;"	d
+DEF_SDIO_DELAY_CHAIN_1	smac/hal/ssv6006c/ssv6006C_reg.h	16203;"	d
+DEF_SDIO_FIFO_ERROR_CNT	include/ssv6200_reg.h	8693;"	d
+DEF_SDIO_FIFO_WR_LIMIT_REG	include/ssv6200_reg.h	8678;"	d
+DEF_SDIO_FIFO_WR_THLD_REG	include/ssv6200_reg.h	8677;"	d
+DEF_SDIO_IPC	include/ssv6200_reg.h	8797;"	d
+DEF_SDIO_IRQ_STS	include/ssv6200_reg.h	8799;"	d
+DEF_SDIO_LAST_CMD_ARG_REG	include/ssv6200_reg.h	8685;"	d
+DEF_SDIO_LAST_CMD_INDEX_CRC_REG	include/ssv6200_reg.h	8684;"	d
+DEF_SDIO_LOG_START_END_DATA_REG	include/ssv6200_reg.h	8682;"	d
+DEF_SDIO_MASK	include/ssv6200_reg.h	8798;"	d
+DEF_SDIO_RESET_WAKE_CFG	smac/hal/ssv6006c/ssv6006C_reg.h	16123;"	d
+DEF_SDIO_RX_DATA_BATCH_SIZE_REG	include/ssv6200_reg.h	8681;"	d
+DEF_SDIO_RX_FAIL_COUNT	smac/hal/ssv6006c/ssv6006C_reg.h	16437;"	d
+DEF_SDIO_THLD_FOR_CMD53RD_REG	include/ssv6200_reg.h	8680;"	d
+DEF_SDIO_TX_ALLOC_REG	include/ssv6200_reg.h	8699;"	d
+DEF_SDIO_TX_DATA_BATCH_SIZE_REG	include/ssv6200_reg.h	8679;"	d
+DEF_SDIO_TX_FAIL_COUNT	smac/hal/ssv6006c/ssv6006C_reg.h	16438;"	d
+DEF_SDIO_TX_INFORM	include/ssv6200_reg.h	8700;"	d
+DEF_SDIO_TX_RX_FAIL_COUNTER_0	include/ssv6200_reg.h	8869;"	d
+DEF_SDIO_TX_RX_FAIL_COUNTER_1	include/ssv6200_reg.h	8870;"	d
+DEF_SDIO_WAKE_MODE	include/ssv6200_reg.h	8849;"	d
+DEF_SD_INIT_CFG	include/ssv6200_reg.h	8581;"	d
+DEF_SD_PERI_MASK	include/ssv6200_reg.h	8800;"	d
+DEF_SD_PERI_STS	include/ssv6200_reg.h	8801;"	d
+DEF_SHA_DST_ADDR	include/ssv6200_reg.h	8900;"	d
+DEF_SHA_DST_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	16464;"	d
+DEF_SHA_SETTING	include/ssv6200_reg.h	8902;"	d
+DEF_SHA_SETTING	smac/hal/ssv6006c/ssv6006C_reg.h	16466;"	d
+DEF_SHA_SRC_ADDR	include/ssv6200_reg.h	8901;"	d
+DEF_SHA_SRC_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	16465;"	d
+DEF_SMS4_CFG1	include/ssv6200_reg.h	8938;"	d
+DEF_SMS4_CFG2	include/ssv6200_reg.h	8939;"	d
+DEF_SMS4_DATA_IN0	include/ssv6200_reg.h	8944;"	d
+DEF_SMS4_DATA_IN1	include/ssv6200_reg.h	8945;"	d
+DEF_SMS4_DATA_IN2	include/ssv6200_reg.h	8946;"	d
+DEF_SMS4_DATA_IN3	include/ssv6200_reg.h	8947;"	d
+DEF_SMS4_DATA_OUT0	include/ssv6200_reg.h	8948;"	d
+DEF_SMS4_DATA_OUT1	include/ssv6200_reg.h	8949;"	d
+DEF_SMS4_DATA_OUT2	include/ssv6200_reg.h	8950;"	d
+DEF_SMS4_DATA_OUT3	include/ssv6200_reg.h	8951;"	d
+DEF_SMS4_KEY_0	include/ssv6200_reg.h	8952;"	d
+DEF_SMS4_KEY_1	include/ssv6200_reg.h	8953;"	d
+DEF_SMS4_KEY_2	include/ssv6200_reg.h	8954;"	d
+DEF_SMS4_KEY_3	include/ssv6200_reg.h	8955;"	d
+DEF_SMS4_MODE1	include/ssv6200_reg.h	8940;"	d
+DEF_SMS4_MODE_IV0	include/ssv6200_reg.h	8956;"	d
+DEF_SMS4_MODE_IV1	include/ssv6200_reg.h	8957;"	d
+DEF_SMS4_MODE_IV2	include/ssv6200_reg.h	8958;"	d
+DEF_SMS4_MODE_IV3	include/ssv6200_reg.h	8959;"	d
+DEF_SMS4_OFB_ENC0	include/ssv6200_reg.h	8960;"	d
+DEF_SMS4_OFB_ENC1	include/ssv6200_reg.h	8961;"	d
+DEF_SMS4_OFB_ENC2	include/ssv6200_reg.h	8962;"	d
+DEF_SMS4_OFB_ENC3	include/ssv6200_reg.h	8963;"	d
+DEF_SMS4_STATUS1	include/ssv6200_reg.h	8942;"	d
+DEF_SMS4_STATUS2	include/ssv6200_reg.h	8943;"	d
+DEF_SMS4_TRIG	include/ssv6200_reg.h	8941;"	d
+DEF_SPARE_UART_INFO	include/ssv6200_reg.h	8582;"	d
+DEF_SPARE_UART_INFO	smac/hal/ssv6006c/ssv6006C_reg.h	16125;"	d
+DEF_SPIMST_CEN	smac/hal/ssv6006c/ssv6006C_reg.h	16065;"	d
+DEF_SPIMST_CFG0	smac/hal/ssv6006c/ssv6006C_reg.h	16062;"	d
+DEF_SPIMST_CFG1	smac/hal/ssv6006c/ssv6006C_reg.h	16063;"	d
+DEF_SPIMST_EN	smac/hal/ssv6006c/ssv6006C_reg.h	16064;"	d
+DEF_SPIMST_INT	smac/hal/ssv6006c/ssv6006C_reg.h	16071;"	d
+DEF_SPIMST_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	16070;"	d
+DEF_SPIMST_RXFIFO_TH	smac/hal/ssv6006c/ssv6006C_reg.h	16068;"	d
+DEF_SPIMST_RX_SAMPLE_DLY	smac/hal/ssv6006c/ssv6006C_reg.h	16073;"	d
+DEF_SPIMST_SCLK_RATE	smac/hal/ssv6006c/ssv6006C_reg.h	16066;"	d
+DEF_SPIMST_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	16069;"	d
+DEF_SPIMST_TRX_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	16072;"	d
+DEF_SPIMST_TXFIFO_TH	smac/hal/ssv6006c/ssv6006C_reg.h	16067;"	d
+DEF_SPI_BUSY	smac/hal/ssv6006c/ssv6006C_reg.h	16484;"	d
+DEF_SPI_CFG	smac/hal/ssv6006c/ssv6006C_reg.h	16488;"	d
+DEF_SPI_CLK_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	16483;"	d
+DEF_SPI_CLR	smac/hal/ssv6006c/ssv6006C_reg.h	16485;"	d
+DEF_SPI_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	16482;"	d
+DEF_SPI_IPC	include/ssv6200_reg.h	8796;"	d
+DEF_SPI_MAS_COMMAND_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	16489;"	d
+DEF_SPI_MAS_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	16486;"	d
+DEF_SPI_MODE	include/ssv6200_reg.h	8743;"	d
+DEF_SPI_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	16247;"	d
+DEF_SPI_M_CFG	smac/hal/ssv6006c/ssv6006C_reg.h	16487;"	d
+DEF_SPI_PARAM	include/ssv6200_reg.h	8823;"	d
+DEF_SPI_PARAM	smac/hal/ssv6006c/ssv6006C_reg.h	16306;"	d
+DEF_SPI_PARAM2	include/ssv6200_reg.h	8824;"	d
+DEF_SPI_PARAM2	smac/hal/ssv6006c/ssv6006C_reg.h	16307;"	d
+DEF_SPI_RX_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	16309;"	d
+DEF_SPI_STS	include/ssv6200_reg.h	8751;"	d
+DEF_SPI_TO_PHY_PARAM1	include/ssv6200_reg.h	8749;"	d
+DEF_SPI_TO_PHY_PARAM1	smac/hal/ssv6006c/ssv6006C_reg.h	16249;"	d
+DEF_SPI_TO_PHY_PARAM2	include/ssv6200_reg.h	8750;"	d
+DEF_SPI_TO_PHY_PARAM2	smac/hal/ssv6006c/ssv6006C_reg.h	16250;"	d
+DEF_SPI_TX_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	16308;"	d
+DEF_SRAMCFG_SETTING	smac/hal/ssv6006c/ssv6006C_reg.h	16131;"	d
+DEF_SRAM_ADDR	include/ssv6200_reg.h	8821;"	d
+DEF_STAT_CONF0	smac/hal/ssv6006c/ssv6006C_reg.h	16591;"	d
+DEF_STAT_CONF1	smac/hal/ssv6006c/ssv6006C_reg.h	16592;"	d
+DEF_STA_MAC1_0	smac/hal/ssv6006c/ssv6006C_reg.h	16795;"	d
+DEF_STA_MAC1_1	smac/hal/ssv6006c/ssv6006C_reg.h	16796;"	d
+DEF_STA_MAC_0	include/ssv6200_reg.h	9216;"	d
+DEF_STA_MAC_0	smac/hal/ssv6006c/ssv6006C_reg.h	16789;"	d
+DEF_STA_MAC_1	include/ssv6200_reg.h	9217;"	d
+DEF_STA_MAC_1	smac/hal/ssv6006c/ssv6006C_reg.h	16790;"	d
+DEF_SUMMARY_TYPHOST_INT_MAP	smac/hal/ssv6006c/ssv6006C_reg.h	16339;"	d
+DEF_SUMMARY_TYPMCU_INT_MAP	smac/hal/ssv6006c/ssv6006C_reg.h	16352;"	d
+DEF_SVN_VERSION_REG	include/ssv6200_reg.h	9396;"	d
+DEF_SWITCH_CTL	include/ssv6200_reg.h	9221;"	d
+DEF_SWITCH_CTL	smac/hal/ssv6006c/ssv6006C_reg.h	16800;"	d
+DEF_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE	smac/hal/ssv6006c/ssv6006C_reg.h	17373;"	d
+DEF_SX_2_4GB_AAC	smac/hal/ssv6006c/ssv6006C_reg.h	17380;"	d
+DEF_SX_2_4GB_DIV_SDM	smac/hal/ssv6006c/ssv6006C_reg.h	17378;"	d
+DEF_SX_2_4GB_FRACTIONAL_AND_INTEGER_8BITS	smac/hal/ssv6006c/ssv6006C_reg.h	17372;"	d
+DEF_SX_2_4GB_LPF	smac/hal/ssv6006c/ssv6006C_reg.h	17375;"	d
+DEF_SX_2_4GB_PFD_CHP_	smac/hal/ssv6006c/ssv6006C_reg.h	17374;"	d
+DEF_SX_2_4GB_SBCAL	smac/hal/ssv6006c/ssv6006C_reg.h	17379;"	d
+DEF_SX_2_4GB_TTL	smac/hal/ssv6006c/ssv6006C_reg.h	17381;"	d
+DEF_SX_2_4GB_VCO	smac/hal/ssv6006c/ssv6006C_reg.h	17376;"	d
+DEF_SX_2_4GB_VCOBF	smac/hal/ssv6006c/ssv6006C_reg.h	17377;"	d
+DEF_SX_2_4G_LDO_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17371;"	d
+DEF_SX_5GB_DIV_SDM	smac/hal/ssv6006c/ssv6006C_reg.h	17447;"	d
+DEF_SX_5GB_DUMMY_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17478;"	d
+DEF_SX_5GB_ENABLE_TOP_CONTROLLER	smac/hal/ssv6006c/ssv6006C_reg.h	17442;"	d
+DEF_SX_5GB_FRACTIONAL_AND_INTEGER_8BITS	smac/hal/ssv6006c/ssv6006C_reg.h	17440;"	d
+DEF_SX_5GB_LDO_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17443;"	d
+DEF_SX_5GB_LOGEN_CALIBRATION	smac/hal/ssv6006c/ssv6006C_reg.h	17450;"	d
+DEF_SX_5GB_LPF_TTL	smac/hal/ssv6006c/ssv6006C_reg.h	17445;"	d
+DEF_SX_5GB_PFD_CHP_	smac/hal/ssv6006c/ssv6006C_reg.h	17444;"	d
+DEF_SX_5GB_REGISTER_INT3BIT___CH_TABLE	smac/hal/ssv6006c/ssv6006C_reg.h	17441;"	d
+DEF_SX_5GB_SBCAL	smac/hal/ssv6006c/ssv6006C_reg.h	17448;"	d
+DEF_SX_5GB_VCO_AAC_LOGEN_CALIBRATION	smac/hal/ssv6006c/ssv6006C_reg.h	17449;"	d
+DEF_SX_5GB_VCO_LOGEN	smac/hal/ssv6006c/ssv6006C_reg.h	17446;"	d
+DEF_SX_DUMMY_REGISTER	include/ssv6200_reg.h	9647;"	d
+DEF_SX_ENABLE_REGISTER	include/ssv6200_reg.h	9625;"	d
+DEF_SX_ENABLE_REGISTER_TOP_CONTROLLER	smac/hal/ssv6006c/ssv6006C_reg.h	17370;"	d
+DEF_SX_LCK_BIN_REGISTERS_I	include/ssv6200_reg.h	9645;"	d
+DEF_SX_LCK_BIN_REGISTERS_II	include/ssv6200_reg.h	9649;"	d
+DEF_SX_LOCK_FREQ_1	smac/hal/ssv6006c/ssv6006C_reg.h	17517;"	d
+DEF_SX_LOCK_FREQ_2	smac/hal/ssv6006c/ssv6006C_reg.h	17518;"	d
+DEF_SYN_DIV_SDM_XOSC	include/ssv6200_reg.h	9630;"	d
+DEF_SYN_KVCO_XO_FINE_TUNE_CBANK	include/ssv6200_reg.h	9631;"	d
+DEF_SYN_LCK_VT	include/ssv6200_reg.h	9632;"	d
+DEF_SYN_PFD_CHP	include/ssv6200_reg.h	9628;"	d
+DEF_SYN_REGISTER_1	include/ssv6200_reg.h	9626;"	d
+DEF_SYN_REGISTER_2	include/ssv6200_reg.h	9627;"	d
+DEF_SYN_VCO_LOBF	include/ssv6200_reg.h	9629;"	d
+DEF_SYSCTRL_COMMAND	smac/hal/ssv6006c/ssv6006C_reg.h	16092;"	d
+DEF_SYSCTRL_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	16094;"	d
+DEF_SYSTEM_INFORMATION_REG	include/ssv6200_reg.h	8675;"	d
+DEF_SYSTEM_INFORMATION_REGISTER	include/ssv6200_reg.h	8704;"	d
+DEF_SYS_CSR_CLOCK_ENABLE	include/ssv6200_reg.h	8556;"	d
+DEF_SYS_CSR_CLOCK_ENABLE	smac/hal/ssv6006c/ssv6006C_reg.h	16082;"	d
+DEF_SYS_INT_FOR_HOST	include/ssv6200_reg.h	8795;"	d
+DEF_SYS_WDOG_REG	include/ssv6200_reg.h	8616;"	d
+DEF_SYS_WDOG_REG	smac/hal/ssv6006c/ssv6006C_reg.h	16162;"	d
+DEF_TAG_SRAM0_F_STATUS_0	include/ssv6200_reg.h	9686;"	d
+DEF_TAG_SRAM0_F_STATUS_1	include/ssv6200_reg.h	9687;"	d
+DEF_TAG_SRAM0_F_STATUS_2	include/ssv6200_reg.h	9688;"	d
+DEF_TAG_SRAM0_F_STATUS_3	include/ssv6200_reg.h	9689;"	d
+DEF_TAG_SRAM0_F_STATUS_4	include/ssv6200_reg.h	9690;"	d
+DEF_TAG_SRAM0_F_STATUS_5	include/ssv6200_reg.h	9691;"	d
+DEF_TAG_SRAM0_F_STATUS_6	include/ssv6200_reg.h	9692;"	d
+DEF_TAG_SRAM0_F_STATUS_7	include/ssv6200_reg.h	9693;"	d
+DEF_TAG_STATUS	include/ssv6200_reg.h	9663;"	d
+DEF_TAG_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	17979;"	d
+DEF_TB_ADR_SEL	include/ssv6200_reg.h	8565;"	d
+DEF_TB_ADR_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	16089;"	d
+DEF_TB_RDATA	include/ssv6200_reg.h	8566;"	d
+DEF_TB_RDATA	smac/hal/ssv6006c/ssv6006C_reg.h	16090;"	d
+DEF_TEST_MODE	include/ssv6200_reg.h	8579;"	d
+DEF_TEST_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	16102;"	d
+DEF_THREASHOLD	include/ssv6200_reg.h	8852;"	d
+DEF_THRESHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	16399;"	d
+DEF_TM0_CURRENT_MILISECOND_TIME_VALUE	include/ssv6200_reg.h	8600;"	d
+DEF_TM0_CURRENT_MILLISECOND_TIME_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	16150;"	d
+DEF_TM0_DUMMY_BIT_0	include/ssv6200_reg.h	8601;"	d
+DEF_TM0_DUMMY_BIT_1	include/ssv6200_reg.h	8602;"	d
+DEF_TM0_MILISECOND_TIMER	include/ssv6200_reg.h	8599;"	d
+DEF_TM0_MILLISECOND_TIMER	smac/hal/ssv6006c/ssv6006C_reg.h	16149;"	d
+DEF_TM0_MILLISECOND_TIMER_PRESCALE	smac/hal/ssv6006c/ssv6006C_reg.h	16151;"	d
+DEF_TM1_CURRENT_MILISECOND_TIME_VALUE	include/ssv6200_reg.h	8604;"	d
+DEF_TM1_CURRENT_MILLISECOND_TIME_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	16153;"	d
+DEF_TM1_DUMMY_BIT_0	include/ssv6200_reg.h	8605;"	d
+DEF_TM1_DUMMY_BIT_1	include/ssv6200_reg.h	8606;"	d
+DEF_TM1_MILISECOND_TIMER	include/ssv6200_reg.h	8603;"	d
+DEF_TM1_MILLISECOND_TIMER	smac/hal/ssv6006c/ssv6006C_reg.h	16152;"	d
+DEF_TM1_MILLISECOND_TIMER_PRESCALE	smac/hal/ssv6006c/ssv6006C_reg.h	16154;"	d
+DEF_TM2_CURRENT_MILISECOND_TIME_VALUE	include/ssv6200_reg.h	8608;"	d
+DEF_TM2_CURRENT_MILLISECOND_TIME_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	16156;"	d
+DEF_TM2_DUMMY_BIT_0	include/ssv6200_reg.h	8609;"	d
+DEF_TM2_DUMMY_BIT_1	include/ssv6200_reg.h	8610;"	d
+DEF_TM2_MILISECOND_TIMER	include/ssv6200_reg.h	8607;"	d
+DEF_TM2_MILLISECOND_TIMER	smac/hal/ssv6006c/ssv6006C_reg.h	16155;"	d
+DEF_TM2_MILLISECOND_TIMER_PRESCALE	smac/hal/ssv6006c/ssv6006C_reg.h	16157;"	d
+DEF_TM3_CURRENT_MILISECOND_TIME_VALUE	include/ssv6200_reg.h	8612;"	d
+DEF_TM3_CURRENT_MILLISECOND_TIME_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	16159;"	d
+DEF_TM3_DUMMY_BIT_0	include/ssv6200_reg.h	8613;"	d
+DEF_TM3_DUMMY_BIT_1	include/ssv6200_reg.h	8614;"	d
+DEF_TM3_MILISECOND_TIMER	include/ssv6200_reg.h	8611;"	d
+DEF_TM3_MILLISECOND_TIMER	smac/hal/ssv6006c/ssv6006C_reg.h	16158;"	d
+DEF_TM3_MILLISECOND_TIMER_PRESCALE	smac/hal/ssv6006c/ssv6006C_reg.h	16160;"	d
+DEF_TRAP_HW_ID	include/ssv6200_reg.h	9032;"	d
+DEF_TRAP_HW_ID	smac/hal/ssv6006c/ssv6006C_reg.h	16558;"	d
+DEF_TRX_DUMMY_REGISTER	include/ssv6200_reg.h	9646;"	d
+DEF_TRX_ID_COUNT	include/ssv6200_reg.h	9368;"	d
+DEF_TRX_ID_COUNT	smac/hal/ssv6006c/ssv6006C_reg.h	17950;"	d
+DEF_TRX_ID_THRESHOLD	include/ssv6200_reg.h	9369;"	d
+DEF_TRX_ID_THRESHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	17951;"	d
+DEF_TRX_IQ_COMP_2G	smac/hal/ssv6006c/ssv6006C_reg.h	17495;"	d
+DEF_TRX_IQ_COMP_5G_0	smac/hal/ssv6006c/ssv6006C_reg.h	17496;"	d
+DEF_TRX_IQ_COMP_5G_1	smac/hal/ssv6006c/ssv6006C_reg.h	17497;"	d
+DEF_TRX_IQ_COMP_5G_2	smac/hal/ssv6006c/ssv6006C_reg.h	17498;"	d
+DEF_TRX_IQ_COMP_5G_3	smac/hal/ssv6006c/ssv6006C_reg.h	17499;"	d
+DEF_TU0_CURRENT_MICROSECOND_TIME_VALUE	include/ssv6200_reg.h	8584;"	d
+DEF_TU0_CURRENT_MICROSECOND_TIME_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	16138;"	d
+DEF_TU0_DUMMY_BIT_0	include/ssv6200_reg.h	8585;"	d
+DEF_TU0_DUMMY_BIT_1	include/ssv6200_reg.h	8586;"	d
+DEF_TU0_MICROSECOND_TIMER	include/ssv6200_reg.h	8583;"	d
+DEF_TU0_MICROSECOND_TIMER	smac/hal/ssv6006c/ssv6006C_reg.h	16137;"	d
+DEF_TU0_MICROSECOND_TIMER_LOCAL_PRESCALE	smac/hal/ssv6006c/ssv6006C_reg.h	16139;"	d
+DEF_TU1_CURRENT_MICROSECOND_TIME_VALUE	include/ssv6200_reg.h	8588;"	d
+DEF_TU1_CURRENT_MICROSECOND_TIME_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	16141;"	d
+DEF_TU1_DUMMY_BIT_0	include/ssv6200_reg.h	8589;"	d
+DEF_TU1_DUMMY_BIT_1	include/ssv6200_reg.h	8590;"	d
+DEF_TU1_MICROSECOND_TIMER	include/ssv6200_reg.h	8587;"	d
+DEF_TU1_MICROSECOND_TIMER	smac/hal/ssv6006c/ssv6006C_reg.h	16140;"	d
+DEF_TU1_MICROSECOND_TIMER_LOCAL_PRESCALE	smac/hal/ssv6006c/ssv6006C_reg.h	16142;"	d
+DEF_TU2_CURRENT_MICROSECOND_TIME_VALUE	include/ssv6200_reg.h	8592;"	d
+DEF_TU2_CURRENT_MICROSECOND_TIME_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	16144;"	d
+DEF_TU2_DUMMY_BIT_0	include/ssv6200_reg.h	8593;"	d
+DEF_TU2_DUMMY_BIT_1	include/ssv6200_reg.h	8594;"	d
+DEF_TU2_MICROSECOND_TIMER	include/ssv6200_reg.h	8591;"	d
+DEF_TU2_MICROSECOND_TIMER	smac/hal/ssv6006c/ssv6006C_reg.h	16143;"	d
+DEF_TU2_MICROSECOND_TIMER_LOCAL_PRESCALE	smac/hal/ssv6006c/ssv6006C_reg.h	16145;"	d
+DEF_TU3_CURRENT_MICROSECOND_TIME_VALUE	include/ssv6200_reg.h	8596;"	d
+DEF_TU3_CURRENT_MICROSECOND_TIME_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	16147;"	d
+DEF_TU3_DUMMY_BIT_0	include/ssv6200_reg.h	8597;"	d
+DEF_TU3_DUMMY_BIT_1	include/ssv6200_reg.h	8598;"	d
+DEF_TU3_MICROSECOND_TIMER	include/ssv6200_reg.h	8595;"	d
+DEF_TU3_MICROSECOND_TIMER	smac/hal/ssv6006c/ssv6006C_reg.h	16146;"	d
+DEF_TU3_MICROSECOND_TIMER_LOCAL_PRESCALE	smac/hal/ssv6006c/ssv6006C_reg.h	16148;"	d
+DEF_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17131;"	d
+DEF_TURISMO_TRX_2_4G_LDO_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17132;"	d
+DEF_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17140;"	d
+DEF_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17142;"	d
+DEF_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17141;"	d
+DEF_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17143;"	d
+DEF_TURISMO_TRX_2_4G_RX_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17136;"	d
+DEF_TURISMO_TRX_2_4G_TRX_DUMMY_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17209;"	d
+DEF_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17130;"	d
+DEF_TURISMO_TRX_2_4G_TX_FE_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17137;"	d
+DEF_TURISMO_TRX_2_4G_TX_PA_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17138;"	d
+DEF_TURISMO_TRX_2_4G_TX_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17139;"	d
+DEF_TURISMO_TRX_5G_CALIBRATION_GAIN_REGISTER1	smac/hal/ssv6006c/ssv6006C_reg.h	17260;"	d
+DEF_TURISMO_TRX_5G_CALIBRATION_TIMER_GAIN_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17259;"	d
+DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER1	smac/hal/ssv6006c/ssv6006C_reg.h	17235;"	d
+DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER10	smac/hal/ssv6006c/ssv6006C_reg.h	17244;"	d
+DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER11	smac/hal/ssv6006c/ssv6006C_reg.h	17245;"	d
+DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER12	smac/hal/ssv6006c/ssv6006C_reg.h	17246;"	d
+DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER13	smac/hal/ssv6006c/ssv6006C_reg.h	17247;"	d
+DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER14	smac/hal/ssv6006c/ssv6006C_reg.h	17248;"	d
+DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER15	smac/hal/ssv6006c/ssv6006C_reg.h	17249;"	d
+DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER16	smac/hal/ssv6006c/ssv6006C_reg.h	17250;"	d
+DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER17	smac/hal/ssv6006c/ssv6006C_reg.h	17251;"	d
+DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER18	smac/hal/ssv6006c/ssv6006C_reg.h	17252;"	d
+DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER19	smac/hal/ssv6006c/ssv6006C_reg.h	17253;"	d
+DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER2	smac/hal/ssv6006c/ssv6006C_reg.h	17236;"	d
+DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER20	smac/hal/ssv6006c/ssv6006C_reg.h	17254;"	d
+DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER21	smac/hal/ssv6006c/ssv6006C_reg.h	17255;"	d
+DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER3	smac/hal/ssv6006c/ssv6006C_reg.h	17237;"	d
+DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER4	smac/hal/ssv6006c/ssv6006C_reg.h	17238;"	d
+DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER5	smac/hal/ssv6006c/ssv6006C_reg.h	17239;"	d
+DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER6	smac/hal/ssv6006c/ssv6006C_reg.h	17240;"	d
+DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER7	smac/hal/ssv6006c/ssv6006C_reg.h	17241;"	d
+DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER8	smac/hal/ssv6006c/ssv6006C_reg.h	17242;"	d
+DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER9	smac/hal/ssv6006c/ssv6006C_reg.h	17243;"	d
+DEF_TURISMO_TRX_5G_LDO_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17214;"	d
+DEF_TURISMO_TRX_5G_MODE_DECODER_TIMER_REGISTER1	smac/hal/ssv6006c/ssv6006C_reg.h	17256;"	d
+DEF_TURISMO_TRX_5G_R2T_TIMER_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17258;"	d
+DEF_TURISMO_TRX_5G_RX_FE_HG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17219;"	d
+DEF_TURISMO_TRX_5G_RX_FE_LG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17221;"	d
+DEF_TURISMO_TRX_5G_RX_FE_MG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17220;"	d
+DEF_TURISMO_TRX_5G_RX_FE_ULG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17222;"	d
+DEF_TURISMO_TRX_5G_RX_LNA_LOAD_SCA_CONTROL	smac/hal/ssv6006c/ssv6006C_reg.h	17267;"	d
+DEF_TURISMO_TRX_5G_RX_LNA_MATCHING_SCA_CONTROL	smac/hal/ssv6006c/ssv6006C_reg.h	17266;"	d
+DEF_TURISMO_TRX_5G_RX_REGISTER1	smac/hal/ssv6006c/ssv6006C_reg.h	17215;"	d
+DEF_TURISMO_TRX_5G_RX_REGISTER2	smac/hal/ssv6006c/ssv6006C_reg.h	17216;"	d
+DEF_TURISMO_TRX_5G_T2R_TIMER_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17257;"	d
+DEF_TURISMO_TRX_5G_TRX_DUMMY_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17261;"	d
+DEF_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17213;"	d
+DEF_TURISMO_TRX_5G_TX_DAC_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17223;"	d
+DEF_TURISMO_TRX_5G_TX_FE_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17217;"	d
+DEF_TURISMO_TRX_5G_TX_PGA_CAPSW_CONTROL	smac/hal/ssv6006c/ssv6006C_reg.h	17268;"	d
+DEF_TURISMO_TRX_5G_TX_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17218;"	d
+DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER1	smac/hal/ssv6006c/ssv6006C_reg.h	17187;"	d
+DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER10	smac/hal/ssv6006c/ssv6006C_reg.h	17196;"	d
+DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER11	smac/hal/ssv6006c/ssv6006C_reg.h	17197;"	d
+DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER12	smac/hal/ssv6006c/ssv6006C_reg.h	17198;"	d
+DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER13	smac/hal/ssv6006c/ssv6006C_reg.h	17199;"	d
+DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER14	smac/hal/ssv6006c/ssv6006C_reg.h	17200;"	d
+DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER15	smac/hal/ssv6006c/ssv6006C_reg.h	17201;"	d
+DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER16	smac/hal/ssv6006c/ssv6006C_reg.h	17202;"	d
+DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER2	smac/hal/ssv6006c/ssv6006C_reg.h	17188;"	d
+DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER3	smac/hal/ssv6006c/ssv6006C_reg.h	17189;"	d
+DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER4	smac/hal/ssv6006c/ssv6006C_reg.h	17190;"	d
+DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER5	smac/hal/ssv6006c/ssv6006C_reg.h	17191;"	d
+DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER6	smac/hal/ssv6006c/ssv6006C_reg.h	17192;"	d
+DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER7	smac/hal/ssv6006c/ssv6006C_reg.h	17193;"	d
+DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER8	smac/hal/ssv6006c/ssv6006C_reg.h	17194;"	d
+DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER9	smac/hal/ssv6006c/ssv6006C_reg.h	17195;"	d
+DEF_TURISMO_TRX_BT_RX_FE_HG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17144;"	d
+DEF_TURISMO_TRX_BT_RX_FE_LG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17146;"	d
+DEF_TURISMO_TRX_BT_RX_FE_MG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17145;"	d
+DEF_TURISMO_TRX_BT_RX_FE_ULG_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17147;"	d
+DEF_TURISMO_TRX_BT_RX_FILTER_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17135;"	d
+DEF_TURISMO_TRX_BT_TX_DAC_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17150;"	d
+DEF_TURISMO_TRX_CALIBRATION_GAIN_REGISTER0	smac/hal/ssv6006c/ssv6006C_reg.h	17207;"	d
+DEF_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1	smac/hal/ssv6006c/ssv6006C_reg.h	17208;"	d
+DEF_TURISMO_TRX_CALIBRATION_TIMER_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17206;"	d
+DEF_TURISMO_TRX_DIGITAL_ADD_ON_0	smac/hal/ssv6006c/ssv6006C_reg.h	17269;"	d
+DEF_TURISMO_TRX_DIGITAL_ADD_ON_1	smac/hal/ssv6006c/ssv6006C_reg.h	17270;"	d
+DEF_TURISMO_TRX_DIGITAL_ADD_ON_2	smac/hal/ssv6006c/ssv6006C_reg.h	17271;"	d
+DEF_TURISMO_TRX_DIGITAL_ADD_ON_3	smac/hal/ssv6006c/ssv6006C_reg.h	17272;"	d
+DEF_TURISMO_TRX_DIGITAL_ADD_ON_4	smac/hal/ssv6006c/ssv6006C_reg.h	17273;"	d
+DEF_TURISMO_TRX_DIGITAL_ADD_ON_5	smac/hal/ssv6006c/ssv6006C_reg.h	17274;"	d
+DEF_TURISMO_TRX_DIGITAL_ADD_ON_6	smac/hal/ssv6006c/ssv6006C_reg.h	17275;"	d
+DEF_TURISMO_TRX_DPLL_CKT_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17164;"	d
+DEF_TURISMO_TRX_DPLL_FB_DIVISION__REGISTERS	smac/hal/ssv6006c/ssv6006C_reg.h	17165;"	d
+DEF_TURISMO_TRX_DPLL_TOP_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17163;"	d
+DEF_TURISMO_TRX_HS3W_CTRL1	smac/hal/ssv6006c/ssv6006C_reg.h	17292;"	d
+DEF_TURISMO_TRX_HS3W_CTRL2	smac/hal/ssv6006c/ssv6006C_reg.h	17293;"	d
+DEF_TURISMO_TRX_HS3W_CTRL3	smac/hal/ssv6006c/ssv6006C_reg.h	17294;"	d
+DEF_TURISMO_TRX_IO_REG_0	smac/hal/ssv6006c/ssv6006C_reg.h	17312;"	d
+DEF_TURISMO_TRX_IO_REG_1	smac/hal/ssv6006c/ssv6006C_reg.h	17313;"	d
+DEF_TURISMO_TRX_IO_REG_2	smac/hal/ssv6006c/ssv6006C_reg.h	17314;"	d
+DEF_TURISMO_TRX_MCU_REG_0	smac/hal/ssv6006c/ssv6006C_reg.h	17315;"	d
+DEF_TURISMO_TRX_MODE_DECODER_TIMER_REGISTER1	smac/hal/ssv6006c/ssv6006C_reg.h	17203;"	d
+DEF_TURISMO_TRX_MODE_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17129;"	d
+DEF_TURISMO_TRX_PMU_BT_CLK	smac/hal/ssv6006c/ssv6006C_reg.h	17311;"	d
+DEF_TURISMO_TRX_PMU_CTRL_REG	smac/hal/ssv6006c/ssv6006C_reg.h	17309;"	d
+DEF_TURISMO_TRX_PMU_RAM_00	smac/hal/ssv6006c/ssv6006C_reg.h	17316;"	d
+DEF_TURISMO_TRX_PMU_RAM_01	smac/hal/ssv6006c/ssv6006C_reg.h	17317;"	d
+DEF_TURISMO_TRX_PMU_RAM_02	smac/hal/ssv6006c/ssv6006C_reg.h	17318;"	d
+DEF_TURISMO_TRX_PMU_RAM_03	smac/hal/ssv6006c/ssv6006C_reg.h	17319;"	d
+DEF_TURISMO_TRX_PMU_RAM_04	smac/hal/ssv6006c/ssv6006C_reg.h	17320;"	d
+DEF_TURISMO_TRX_PMU_RAM_05	smac/hal/ssv6006c/ssv6006C_reg.h	17321;"	d
+DEF_TURISMO_TRX_PMU_RAM_06	smac/hal/ssv6006c/ssv6006C_reg.h	17322;"	d
+DEF_TURISMO_TRX_PMU_RAM_07	smac/hal/ssv6006c/ssv6006C_reg.h	17323;"	d
+DEF_TURISMO_TRX_PMU_RAM_08	smac/hal/ssv6006c/ssv6006C_reg.h	17324;"	d
+DEF_TURISMO_TRX_PMU_RAM_09	smac/hal/ssv6006c/ssv6006C_reg.h	17325;"	d
+DEF_TURISMO_TRX_PMU_RAM_10	smac/hal/ssv6006c/ssv6006C_reg.h	17326;"	d
+DEF_TURISMO_TRX_PMU_RAM_11	smac/hal/ssv6006c/ssv6006C_reg.h	17327;"	d
+DEF_TURISMO_TRX_PMU_RAM_12	smac/hal/ssv6006c/ssv6006C_reg.h	17328;"	d
+DEF_TURISMO_TRX_PMU_RAM_13	smac/hal/ssv6006c/ssv6006C_reg.h	17329;"	d
+DEF_TURISMO_TRX_PMU_RAM_14	smac/hal/ssv6006c/ssv6006C_reg.h	17330;"	d
+DEF_TURISMO_TRX_PMU_RAM_15	smac/hal/ssv6006c/ssv6006C_reg.h	17331;"	d
+DEF_TURISMO_TRX_PMU_RAM_16	smac/hal/ssv6006c/ssv6006C_reg.h	17332;"	d
+DEF_TURISMO_TRX_PMU_RAM_17	smac/hal/ssv6006c/ssv6006C_reg.h	17333;"	d
+DEF_TURISMO_TRX_PMU_RAM_18	smac/hal/ssv6006c/ssv6006C_reg.h	17334;"	d
+DEF_TURISMO_TRX_PMU_RAM_19	smac/hal/ssv6006c/ssv6006C_reg.h	17335;"	d
+DEF_TURISMO_TRX_PMU_RAM_20	smac/hal/ssv6006c/ssv6006C_reg.h	17336;"	d
+DEF_TURISMO_TRX_PMU_RAM_21	smac/hal/ssv6006c/ssv6006C_reg.h	17337;"	d
+DEF_TURISMO_TRX_PMU_RAM_22	smac/hal/ssv6006c/ssv6006C_reg.h	17338;"	d
+DEF_TURISMO_TRX_PMU_RAM_23	smac/hal/ssv6006c/ssv6006C_reg.h	17339;"	d
+DEF_TURISMO_TRX_PMU_RAM_24	smac/hal/ssv6006c/ssv6006C_reg.h	17340;"	d
+DEF_TURISMO_TRX_PMU_RAM_25	smac/hal/ssv6006c/ssv6006C_reg.h	17341;"	d
+DEF_TURISMO_TRX_PMU_RAM_26	smac/hal/ssv6006c/ssv6006C_reg.h	17342;"	d
+DEF_TURISMO_TRX_PMU_RAM_27	smac/hal/ssv6006c/ssv6006C_reg.h	17343;"	d
+DEF_TURISMO_TRX_PMU_RAM_28	smac/hal/ssv6006c/ssv6006C_reg.h	17344;"	d
+DEF_TURISMO_TRX_PMU_RAM_29	smac/hal/ssv6006c/ssv6006C_reg.h	17345;"	d
+DEF_TURISMO_TRX_PMU_RAM_30	smac/hal/ssv6006c/ssv6006C_reg.h	17346;"	d
+DEF_TURISMO_TRX_PMU_RAM_31	smac/hal/ssv6006c/ssv6006C_reg.h	17347;"	d
+DEF_TURISMO_TRX_PMU_REG_1	smac/hal/ssv6006c/ssv6006C_reg.h	17297;"	d
+DEF_TURISMO_TRX_PMU_REG_2	smac/hal/ssv6006c/ssv6006C_reg.h	17298;"	d
+DEF_TURISMO_TRX_PMU_REG_3	smac/hal/ssv6006c/ssv6006C_reg.h	17299;"	d
+DEF_TURISMO_TRX_PMU_REG_4	smac/hal/ssv6006c/ssv6006C_reg.h	17300;"	d
+DEF_TURISMO_TRX_PMU_REG_5	smac/hal/ssv6006c/ssv6006C_reg.h	17301;"	d
+DEF_TURISMO_TRX_PMU_REG_6	smac/hal/ssv6006c/ssv6006C_reg.h	17302;"	d
+DEF_TURISMO_TRX_PMU_RTC_REG_0	smac/hal/ssv6006c/ssv6006C_reg.h	17305;"	d
+DEF_TURISMO_TRX_PMU_RTC_REG_1	smac/hal/ssv6006c/ssv6006C_reg.h	17306;"	d
+DEF_TURISMO_TRX_PMU_RTC_REG_2	smac/hal/ssv6006c/ssv6006C_reg.h	17307;"	d
+DEF_TURISMO_TRX_PMU_RTC_REG_3	smac/hal/ssv6006c/ssv6006C_reg.h	17308;"	d
+DEF_TURISMO_TRX_PMU_SLEEP_REG_1	smac/hal/ssv6006c/ssv6006C_reg.h	17303;"	d
+DEF_TURISMO_TRX_PMU_SLEEP_REG_2	smac/hal/ssv6006c/ssv6006C_reg.h	17304;"	d
+DEF_TURISMO_TRX_PMU_STATE_REG	smac/hal/ssv6006c/ssv6006C_reg.h	17310;"	d
+DEF_TURISMO_TRX_READ_ONLY_FLAGS_ADC	smac/hal/ssv6006c/ssv6006C_reg.h	17210;"	d
+DEF_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_1	smac/hal/ssv6006c/ssv6006C_reg.h	17211;"	d
+DEF_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_2	smac/hal/ssv6006c/ssv6006C_reg.h	17212;"	d
+DEF_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_1	smac/hal/ssv6006c/ssv6006C_reg.h	17263;"	d
+DEF_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_2	smac/hal/ssv6006c/ssv6006C_reg.h	17264;"	d
+DEF_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_3	smac/hal/ssv6006c/ssv6006C_reg.h	17265;"	d
+DEF_TURISMO_TRX_RF_D_CAL_TOP_0	smac/hal/ssv6006c/ssv6006C_reg.h	17282;"	d
+DEF_TURISMO_TRX_RF_D_CAL_TOP_1	smac/hal/ssv6006c/ssv6006C_reg.h	17283;"	d
+DEF_TURISMO_TRX_RF_D_CAL_TOP_2	smac/hal/ssv6006c/ssv6006C_reg.h	17284;"	d
+DEF_TURISMO_TRX_RF_D_CAL_TOP_3	smac/hal/ssv6006c/ssv6006C_reg.h	17285;"	d
+DEF_TURISMO_TRX_RF_D_CAL_TOP_4	smac/hal/ssv6006c/ssv6006C_reg.h	17286;"	d
+DEF_TURISMO_TRX_RF_D_CAL_TOP_5	smac/hal/ssv6006c/ssv6006C_reg.h	17287;"	d
+DEF_TURISMO_TRX_RF_D_CAL_TOP_6	smac/hal/ssv6006c/ssv6006C_reg.h	17288;"	d
+DEF_TURISMO_TRX_RF_D_CAL_TOP_7	smac/hal/ssv6006c/ssv6006C_reg.h	17289;"	d
+DEF_TURISMO_TRX_RF_D_CAL_TOP_8	smac/hal/ssv6006c/ssv6006C_reg.h	17290;"	d
+DEF_TURISMO_TRX_RF_D_CAL_TOP_9	smac/hal/ssv6006c/ssv6006C_reg.h	17291;"	d
+DEF_TURISMO_TRX_RF_D_MODE_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	17295;"	d
+DEF_TURISMO_TRX_RX_DC_CAL_RESULT	smac/hal/ssv6006c/ssv6006C_reg.h	17296;"	d
+DEF_TURISMO_TRX_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE	smac/hal/ssv6006c/ssv6006C_reg.h	17154;"	d
+DEF_TURISMO_TRX_SX_2_4GB_AAC	smac/hal/ssv6006c/ssv6006C_reg.h	17161;"	d
+DEF_TURISMO_TRX_SX_2_4GB_DIV_SDM	smac/hal/ssv6006c/ssv6006C_reg.h	17159;"	d
+DEF_TURISMO_TRX_SX_2_4GB_FRACTIONAL_AND_INTEGER_8BITS	smac/hal/ssv6006c/ssv6006C_reg.h	17153;"	d
+DEF_TURISMO_TRX_SX_2_4GB_LPF	smac/hal/ssv6006c/ssv6006C_reg.h	17156;"	d
+DEF_TURISMO_TRX_SX_2_4GB_PFD_CHP_	smac/hal/ssv6006c/ssv6006C_reg.h	17155;"	d
+DEF_TURISMO_TRX_SX_2_4GB_SBCAL	smac/hal/ssv6006c/ssv6006C_reg.h	17160;"	d
+DEF_TURISMO_TRX_SX_2_4GB_TTL	smac/hal/ssv6006c/ssv6006C_reg.h	17162;"	d
+DEF_TURISMO_TRX_SX_2_4GB_VCO	smac/hal/ssv6006c/ssv6006C_reg.h	17157;"	d
+DEF_TURISMO_TRX_SX_2_4GB_VCOBF	smac/hal/ssv6006c/ssv6006C_reg.h	17158;"	d
+DEF_TURISMO_TRX_SX_2_4G_LDO_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17152;"	d
+DEF_TURISMO_TRX_SX_5GB_DIV_SDM	smac/hal/ssv6006c/ssv6006C_reg.h	17231;"	d
+DEF_TURISMO_TRX_SX_5GB_DUMMY_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17262;"	d
+DEF_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER	smac/hal/ssv6006c/ssv6006C_reg.h	17226;"	d
+DEF_TURISMO_TRX_SX_5GB_FRACTIONAL_AND_INTEGER_8BITS	smac/hal/ssv6006c/ssv6006C_reg.h	17224;"	d
+DEF_TURISMO_TRX_SX_5GB_LDO_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17227;"	d
+DEF_TURISMO_TRX_SX_5GB_LOGEN_CALIBRATION	smac/hal/ssv6006c/ssv6006C_reg.h	17234;"	d
+DEF_TURISMO_TRX_SX_5GB_LPF_TTL	smac/hal/ssv6006c/ssv6006C_reg.h	17229;"	d
+DEF_TURISMO_TRX_SX_5GB_PFD_CHP_	smac/hal/ssv6006c/ssv6006C_reg.h	17228;"	d
+DEF_TURISMO_TRX_SX_5GB_REGISTER_INT3BIT___CH_TABLE	smac/hal/ssv6006c/ssv6006C_reg.h	17225;"	d
+DEF_TURISMO_TRX_SX_5GB_SBCAL	smac/hal/ssv6006c/ssv6006C_reg.h	17232;"	d
+DEF_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION	smac/hal/ssv6006c/ssv6006C_reg.h	17233;"	d
+DEF_TURISMO_TRX_SX_5GB_VCO_LOGEN	smac/hal/ssv6006c/ssv6006C_reg.h	17230;"	d
+DEF_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER	smac/hal/ssv6006c/ssv6006C_reg.h	17151;"	d
+DEF_TURISMO_TRX_TX_BW20_FIR_COEF_00	smac/hal/ssv6006c/ssv6006C_reg.h	17276;"	d
+DEF_TURISMO_TRX_TX_BW20_FIR_COEF_01	smac/hal/ssv6006c/ssv6006C_reg.h	17277;"	d
+DEF_TURISMO_TRX_TX_BW20_FIR_COEF_02	smac/hal/ssv6006c/ssv6006C_reg.h	17278;"	d
+DEF_TURISMO_TRX_TX_BW20_FIR_COEF_03	smac/hal/ssv6006c/ssv6006C_reg.h	17279;"	d
+DEF_TURISMO_TRX_TX_BW20_FIR_COEF_04	smac/hal/ssv6006c/ssv6006C_reg.h	17280;"	d
+DEF_TURISMO_TRX_TX_BW20_FIR_COEF_05	smac/hal/ssv6006c/ssv6006C_reg.h	17281;"	d
+DEF_TURISMO_TRX_WBT_RX_ADC_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17148;"	d
+DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER1	smac/hal/ssv6006c/ssv6006C_reg.h	17166;"	d
+DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER10	smac/hal/ssv6006c/ssv6006C_reg.h	17175;"	d
+DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER11	smac/hal/ssv6006c/ssv6006C_reg.h	17176;"	d
+DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER12	smac/hal/ssv6006c/ssv6006C_reg.h	17177;"	d
+DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER13	smac/hal/ssv6006c/ssv6006C_reg.h	17178;"	d
+DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER14	smac/hal/ssv6006c/ssv6006C_reg.h	17179;"	d
+DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER15	smac/hal/ssv6006c/ssv6006C_reg.h	17180;"	d
+DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER16	smac/hal/ssv6006c/ssv6006C_reg.h	17181;"	d
+DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER17	smac/hal/ssv6006c/ssv6006C_reg.h	17182;"	d
+DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER18	smac/hal/ssv6006c/ssv6006C_reg.h	17183;"	d
+DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER19	smac/hal/ssv6006c/ssv6006C_reg.h	17184;"	d
+DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER2	smac/hal/ssv6006c/ssv6006C_reg.h	17167;"	d
+DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER20	smac/hal/ssv6006c/ssv6006C_reg.h	17185;"	d
+DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER21	smac/hal/ssv6006c/ssv6006C_reg.h	17186;"	d
+DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER3	smac/hal/ssv6006c/ssv6006C_reg.h	17168;"	d
+DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER4	smac/hal/ssv6006c/ssv6006C_reg.h	17169;"	d
+DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER5	smac/hal/ssv6006c/ssv6006C_reg.h	17170;"	d
+DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER6	smac/hal/ssv6006c/ssv6006C_reg.h	17171;"	d
+DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER7	smac/hal/ssv6006c/ssv6006C_reg.h	17172;"	d
+DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER8	smac/hal/ssv6006c/ssv6006C_reg.h	17173;"	d
+DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER9	smac/hal/ssv6006c/ssv6006C_reg.h	17174;"	d
+DEF_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17133;"	d
+DEF_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17134;"	d
+DEF_TURISMO_TRX_WIFI_R2T_TIMER_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17205;"	d
+DEF_TURISMO_TRX_WIFI_T2R_TIMER_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17204;"	d
+DEF_TURISMO_TRX_WIFI_TX_DAC_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17149;"	d
+DEF_TWIM_DELAY_ACK	smac/hal/ssv6006c/ssv6006C_reg.h	16263;"	d
+DEF_TWIM_DEV_A	smac/hal/ssv6006c/ssv6006C_reg.h	16258;"	d
+DEF_TWIM_EN	smac/hal/ssv6006c/ssv6006C_reg.h	16251;"	d
+DEF_TWIM_INTERRUPT	smac/hal/ssv6006c/ssv6006C_reg.h	16254;"	d
+DEF_TWIM_INTERRUPT_EN	smac/hal/ssv6006c/ssv6006C_reg.h	16253;"	d
+DEF_TWIM_INTERRUPT_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	16255;"	d
+DEF_TWIM_PSCL	smac/hal/ssv6006c/ssv6006C_reg.h	16261;"	d
+DEF_TWIM_RXD_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	16260;"	d
+DEF_TWIM_STATUS_RECORD_0	smac/hal/ssv6006c/ssv6006C_reg.h	16256;"	d
+DEF_TWIM_STATUS_RECORD_1	smac/hal/ssv6006c/ssv6006C_reg.h	16257;"	d
+DEF_TWIM_STATUS_SETTING	smac/hal/ssv6006c/ssv6006C_reg.h	16252;"	d
+DEF_TWIM_TRANS_PSDA	smac/hal/ssv6006c/ssv6006C_reg.h	16262;"	d
+DEF_TWIM_TXD_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	16259;"	d
+DEF_TXFID_INCREASE	include/ssv6200_reg.h	8853;"	d
+DEF_TXFID_INCREASE	smac/hal/ssv6006c/ssv6006C_reg.h	16401;"	d
+DEF_TXQ0_MTX_Q_AIFSN	include/ssv6200_reg.h	9085;"	d
+DEF_TXQ0_MTX_Q_AIFSN	smac/hal/ssv6006c/ssv6006C_reg.h	16629;"	d
+DEF_TXQ0_MTX_Q_BKF_CNT	include/ssv6200_reg.h	9086;"	d
+DEF_TXQ0_MTX_Q_BKF_CNT_DBG	smac/hal/ssv6006c/ssv6006C_reg.h	16630;"	d
+DEF_TXQ0_MTX_Q_HWDBG	smac/hal/ssv6006c/ssv6006C_reg.h	16631;"	d
+DEF_TXQ0_MTX_Q_HWDBG2	smac/hal/ssv6006c/ssv6006C_reg.h	16632;"	d
+DEF_TXQ0_MTX_Q_ID_MAP_L	include/ssv6200_reg.h	9088;"	d
+DEF_TXQ0_MTX_Q_MISC_EN	include/ssv6200_reg.h	9084;"	d
+DEF_TXQ0_MTX_Q_MISC_EN	smac/hal/ssv6006c/ssv6006C_reg.h	16628;"	d
+DEF_TXQ0_MTX_Q_RC_LIMIT	include/ssv6200_reg.h	9087;"	d
+DEF_TXQ0_MTX_Q_TXOP_CH_THD	include/ssv6200_reg.h	9089;"	d
+DEF_TXQ0_MTX_Q_TXOP_OV_THD	include/ssv6200_reg.h	9090;"	d
+DEF_TXQ1_MTX_Q_AIFSN	include/ssv6200_reg.h	9092;"	d
+DEF_TXQ1_MTX_Q_AIFSN	smac/hal/ssv6006c/ssv6006C_reg.h	16634;"	d
+DEF_TXQ1_MTX_Q_BKF_CNT	include/ssv6200_reg.h	9093;"	d
+DEF_TXQ1_MTX_Q_BKF_CNT_DBG	smac/hal/ssv6006c/ssv6006C_reg.h	16635;"	d
+DEF_TXQ1_MTX_Q_HWDBG	smac/hal/ssv6006c/ssv6006C_reg.h	16636;"	d
+DEF_TXQ1_MTX_Q_HWDBG2	smac/hal/ssv6006c/ssv6006C_reg.h	16637;"	d
+DEF_TXQ1_MTX_Q_ID_MAP_L	include/ssv6200_reg.h	9095;"	d
+DEF_TXQ1_MTX_Q_MISC_EN	include/ssv6200_reg.h	9091;"	d
+DEF_TXQ1_MTX_Q_MISC_EN	smac/hal/ssv6006c/ssv6006C_reg.h	16633;"	d
+DEF_TXQ1_MTX_Q_RC_LIMIT	include/ssv6200_reg.h	9094;"	d
+DEF_TXQ1_MTX_Q_TXOP_CH_THD	include/ssv6200_reg.h	9096;"	d
+DEF_TXQ1_MTX_Q_TXOP_OV_THD	include/ssv6200_reg.h	9097;"	d
+DEF_TXQ2_MTX_Q_AIFSN	include/ssv6200_reg.h	9099;"	d
+DEF_TXQ2_MTX_Q_AIFSN	smac/hal/ssv6006c/ssv6006C_reg.h	16639;"	d
+DEF_TXQ2_MTX_Q_BKF_CNT	include/ssv6200_reg.h	9100;"	d
+DEF_TXQ2_MTX_Q_BKF_CNT_DBG	smac/hal/ssv6006c/ssv6006C_reg.h	16640;"	d
+DEF_TXQ2_MTX_Q_HWDBG	smac/hal/ssv6006c/ssv6006C_reg.h	16641;"	d
+DEF_TXQ2_MTX_Q_HWDBG2	smac/hal/ssv6006c/ssv6006C_reg.h	16642;"	d
+DEF_TXQ2_MTX_Q_ID_MAP_L	include/ssv6200_reg.h	9102;"	d
+DEF_TXQ2_MTX_Q_MISC_EN	include/ssv6200_reg.h	9098;"	d
+DEF_TXQ2_MTX_Q_MISC_EN	smac/hal/ssv6006c/ssv6006C_reg.h	16638;"	d
+DEF_TXQ2_MTX_Q_RC_LIMIT	include/ssv6200_reg.h	9101;"	d
+DEF_TXQ2_MTX_Q_TXOP_CH_THD	include/ssv6200_reg.h	9103;"	d
+DEF_TXQ2_MTX_Q_TXOP_OV_THD	include/ssv6200_reg.h	9104;"	d
+DEF_TXQ3_MTX_Q_AIFSN	include/ssv6200_reg.h	9106;"	d
+DEF_TXQ3_MTX_Q_AIFSN	smac/hal/ssv6006c/ssv6006C_reg.h	16644;"	d
+DEF_TXQ3_MTX_Q_BKF_CNT	include/ssv6200_reg.h	9107;"	d
+DEF_TXQ3_MTX_Q_BKF_CNT_DBG	smac/hal/ssv6006c/ssv6006C_reg.h	16645;"	d
+DEF_TXQ3_MTX_Q_HWDBG	smac/hal/ssv6006c/ssv6006C_reg.h	16646;"	d
+DEF_TXQ3_MTX_Q_HWDBG2	smac/hal/ssv6006c/ssv6006C_reg.h	16647;"	d
+DEF_TXQ3_MTX_Q_ID_MAP_L	include/ssv6200_reg.h	9109;"	d
+DEF_TXQ3_MTX_Q_MISC_EN	include/ssv6200_reg.h	9105;"	d
+DEF_TXQ3_MTX_Q_MISC_EN	smac/hal/ssv6006c/ssv6006C_reg.h	16643;"	d
+DEF_TXQ3_MTX_Q_RC_LIMIT	include/ssv6200_reg.h	9108;"	d
+DEF_TXQ3_MTX_Q_TXOP_CH_THD	include/ssv6200_reg.h	9110;"	d
+DEF_TXQ3_MTX_Q_TXOP_OV_THD	include/ssv6200_reg.h	9111;"	d
+DEF_TXQ4_MTX_Q_AIFSN	include/ssv6200_reg.h	9113;"	d
+DEF_TXQ4_MTX_Q_AIFSN	smac/hal/ssv6006c/ssv6006C_reg.h	16649;"	d
+DEF_TXQ4_MTX_Q_BKF_CNT	include/ssv6200_reg.h	9114;"	d
+DEF_TXQ4_MTX_Q_BKF_CNT_DBG	smac/hal/ssv6006c/ssv6006C_reg.h	16650;"	d
+DEF_TXQ4_MTX_Q_HWDBG	smac/hal/ssv6006c/ssv6006C_reg.h	16651;"	d
+DEF_TXQ4_MTX_Q_HWDBG2	smac/hal/ssv6006c/ssv6006C_reg.h	16652;"	d
+DEF_TXQ4_MTX_Q_ID_MAP_L	include/ssv6200_reg.h	9116;"	d
+DEF_TXQ4_MTX_Q_MISC_EN	include/ssv6200_reg.h	9112;"	d
+DEF_TXQ4_MTX_Q_MISC_EN	smac/hal/ssv6006c/ssv6006C_reg.h	16648;"	d
+DEF_TXQ4_MTX_Q_RC_LIMIT	include/ssv6200_reg.h	9115;"	d
+DEF_TXQ4_MTX_Q_TXOP_CH_THD	include/ssv6200_reg.h	9117;"	d
+DEF_TXQ4_MTX_Q_TXOP_OV_THD	include/ssv6200_reg.h	9118;"	d
+DEF_TXQ5_MTX_Q_AIFSN	smac/hal/ssv6006c/ssv6006C_reg.h	16654;"	d
+DEF_TXQ5_MTX_Q_BKF_CNT_DBG	smac/hal/ssv6006c/ssv6006C_reg.h	16655;"	d
+DEF_TXQ5_MTX_Q_HWDBG	smac/hal/ssv6006c/ssv6006C_reg.h	16656;"	d
+DEF_TXQ5_MTX_Q_HWDBG2	smac/hal/ssv6006c/ssv6006C_reg.h	16657;"	d
+DEF_TXQ5_MTX_Q_MISC_EN	smac/hal/ssv6006c/ssv6006C_reg.h	16653;"	d
+DEF_TX_11B_EN_CNT	include/ssv6200_reg.h	9490;"	d
+DEF_TX_11B_EN_CNT_RST_N	include/ssv6200_reg.h	9489;"	d
+DEF_TX_11B_FIL_COEF_00	include/ssv6200_reg.h	9446;"	d
+DEF_TX_11B_FIL_COEF_01	include/ssv6200_reg.h	9447;"	d
+DEF_TX_11B_FIL_COEF_02	include/ssv6200_reg.h	9448;"	d
+DEF_TX_11B_FIL_COEF_03	include/ssv6200_reg.h	9449;"	d
+DEF_TX_11B_FIL_COEF_04	include/ssv6200_reg.h	9450;"	d
+DEF_TX_11B_FIL_COEF_05	include/ssv6200_reg.h	9451;"	d
+DEF_TX_11B_FIL_COEF_06	include/ssv6200_reg.h	9452;"	d
+DEF_TX_11B_FIL_COEF_07	include/ssv6200_reg.h	9453;"	d
+DEF_TX_11B_FIL_COEF_08	include/ssv6200_reg.h	9454;"	d
+DEF_TX_11B_FIL_COEF_09	include/ssv6200_reg.h	9455;"	d
+DEF_TX_11B_FIL_COEF_10	include/ssv6200_reg.h	9456;"	d
+DEF_TX_11B_FIL_COEF_11	include/ssv6200_reg.h	9457;"	d
+DEF_TX_11B_FIL_COEF_12	include/ssv6200_reg.h	9458;"	d
+DEF_TX_11B_FIL_COEF_13	include/ssv6200_reg.h	9459;"	d
+DEF_TX_11B_FIL_COEF_14	include/ssv6200_reg.h	9460;"	d
+DEF_TX_11B_FIL_COEF_15	include/ssv6200_reg.h	9461;"	d
+DEF_TX_11B_FIL_COEF_16	include/ssv6200_reg.h	9462;"	d
+DEF_TX_11B_FIL_COEF_17	include/ssv6200_reg.h	9463;"	d
+DEF_TX_11B_FIL_COEF_18	include/ssv6200_reg.h	9464;"	d
+DEF_TX_11B_FIL_COEF_19	include/ssv6200_reg.h	9465;"	d
+DEF_TX_11B_FIL_COEF_20	include/ssv6200_reg.h	9466;"	d
+DEF_TX_11B_FIL_COEF_21	include/ssv6200_reg.h	9467;"	d
+DEF_TX_11B_FIL_COEF_22	include/ssv6200_reg.h	9468;"	d
+DEF_TX_11B_FIL_COEF_23	include/ssv6200_reg.h	9469;"	d
+DEF_TX_11B_FIL_COEF_24	include/ssv6200_reg.h	9470;"	d
+DEF_TX_11B_FIL_COEF_25	include/ssv6200_reg.h	9471;"	d
+DEF_TX_11B_FIL_COEF_26	include/ssv6200_reg.h	9472;"	d
+DEF_TX_11B_FIL_COEF_27	include/ssv6200_reg.h	9473;"	d
+DEF_TX_11B_FIL_COEF_28	include/ssv6200_reg.h	9474;"	d
+DEF_TX_11B_FIL_COEF_29	include/ssv6200_reg.h	9475;"	d
+DEF_TX_11B_FIL_COEF_30	include/ssv6200_reg.h	9476;"	d
+DEF_TX_11B_FIL_COEF_31	include/ssv6200_reg.h	9477;"	d
+DEF_TX_11B_FIL_COEF_32	include/ssv6200_reg.h	9478;"	d
+DEF_TX_11B_FIL_COEF_33	include/ssv6200_reg.h	9479;"	d
+DEF_TX_11B_FIL_COEF_34	include/ssv6200_reg.h	9480;"	d
+DEF_TX_11B_FIL_COEF_35	include/ssv6200_reg.h	9481;"	d
+DEF_TX_11B_FIL_COEF_36	include/ssv6200_reg.h	9482;"	d
+DEF_TX_11B_FIL_COEF_37	include/ssv6200_reg.h	9483;"	d
+DEF_TX_11B_FIL_COEF_38	include/ssv6200_reg.h	9484;"	d
+DEF_TX_11B_FIL_COEF_39	include/ssv6200_reg.h	9485;"	d
+DEF_TX_11B_FIL_COEF_40	include/ssv6200_reg.h	9486;"	d
+DEF_TX_11B_PKT_GEN_CNT	include/ssv6200_reg.h	9491;"	d
+DEF_TX_11B_PLCP	include/ssv6200_reg.h	9487;"	d
+DEF_TX_11B_RAMP	include/ssv6200_reg.h	9488;"	d
+DEF_TX_11GN_PKT_GEN_CNT	include/ssv6200_reg.h	9519;"	d
+DEF_TX_11GN_PLCP	include/ssv6200_reg.h	9518;"	d
+DEF_TX_11GN_PLCP_CRC_ERR_CNT	include/ssv6200_reg.h	9520;"	d
+DEF_TX_11GN_RAMP	include/ssv6200_reg.h	9517;"	d
+DEF_TX_ACK_POLICY_0_0	include/ssv6200_reg.h	9122;"	d
+DEF_TX_ACK_POLICY_0_0	smac/hal/ssv6006c/ssv6006C_reg.h	16741;"	d
+DEF_TX_ACK_POLICY_0_1	include/ssv6200_reg.h	9124;"	d
+DEF_TX_ACK_POLICY_0_1	smac/hal/ssv6006c/ssv6006C_reg.h	16743;"	d
+DEF_TX_ACK_POLICY_0_2	include/ssv6200_reg.h	9126;"	d
+DEF_TX_ACK_POLICY_0_2	smac/hal/ssv6006c/ssv6006C_reg.h	16745;"	d
+DEF_TX_ACK_POLICY_0_3	include/ssv6200_reg.h	9128;"	d
+DEF_TX_ACK_POLICY_0_3	smac/hal/ssv6006c/ssv6006C_reg.h	16747;"	d
+DEF_TX_ACK_POLICY_0_4	include/ssv6200_reg.h	9130;"	d
+DEF_TX_ACK_POLICY_0_4	smac/hal/ssv6006c/ssv6006C_reg.h	16749;"	d
+DEF_TX_ACK_POLICY_0_5	include/ssv6200_reg.h	9132;"	d
+DEF_TX_ACK_POLICY_0_5	smac/hal/ssv6006c/ssv6006C_reg.h	16751;"	d
+DEF_TX_ACK_POLICY_0_6	include/ssv6200_reg.h	9134;"	d
+DEF_TX_ACK_POLICY_0_6	smac/hal/ssv6006c/ssv6006C_reg.h	16753;"	d
+DEF_TX_ACK_POLICY_0_7	include/ssv6200_reg.h	9136;"	d
+DEF_TX_ACK_POLICY_0_7	smac/hal/ssv6006c/ssv6006C_reg.h	16755;"	d
+DEF_TX_ACK_POLICY_1_0	include/ssv6200_reg.h	9141;"	d
+DEF_TX_ACK_POLICY_1_0	smac/hal/ssv6006c/ssv6006C_reg.h	16760;"	d
+DEF_TX_ACK_POLICY_1_1	include/ssv6200_reg.h	9143;"	d
+DEF_TX_ACK_POLICY_1_1	smac/hal/ssv6006c/ssv6006C_reg.h	16762;"	d
+DEF_TX_ACK_POLICY_1_2	include/ssv6200_reg.h	9145;"	d
+DEF_TX_ACK_POLICY_1_2	smac/hal/ssv6006c/ssv6006C_reg.h	16764;"	d
+DEF_TX_ACK_POLICY_1_3	include/ssv6200_reg.h	9147;"	d
+DEF_TX_ACK_POLICY_1_3	smac/hal/ssv6006c/ssv6006C_reg.h	16766;"	d
+DEF_TX_ACK_POLICY_1_4	include/ssv6200_reg.h	9149;"	d
+DEF_TX_ACK_POLICY_1_4	smac/hal/ssv6006c/ssv6006C_reg.h	16768;"	d
+DEF_TX_ACK_POLICY_1_5	include/ssv6200_reg.h	9151;"	d
+DEF_TX_ACK_POLICY_1_5	smac/hal/ssv6006c/ssv6006C_reg.h	16770;"	d
+DEF_TX_ACK_POLICY_1_6	include/ssv6200_reg.h	9153;"	d
+DEF_TX_ACK_POLICY_1_6	smac/hal/ssv6006c/ssv6006C_reg.h	16772;"	d
+DEF_TX_ACK_POLICY_1_7	include/ssv6200_reg.h	9155;"	d
+DEF_TX_ACK_POLICY_1_7	smac/hal/ssv6006c/ssv6006C_reg.h	16774;"	d
+DEF_TX_ACK_POLICY_2_0	smac/hal/ssv6006c/ssv6006C_reg.h	16867;"	d
+DEF_TX_ACK_POLICY_2_1	smac/hal/ssv6006c/ssv6006C_reg.h	16869;"	d
+DEF_TX_ACK_POLICY_2_2	smac/hal/ssv6006c/ssv6006C_reg.h	16871;"	d
+DEF_TX_ACK_POLICY_2_3	smac/hal/ssv6006c/ssv6006C_reg.h	16873;"	d
+DEF_TX_ACK_POLICY_2_4	smac/hal/ssv6006c/ssv6006C_reg.h	16875;"	d
+DEF_TX_ACK_POLICY_2_5	smac/hal/ssv6006c/ssv6006C_reg.h	16877;"	d
+DEF_TX_ACK_POLICY_2_6	smac/hal/ssv6006c/ssv6006C_reg.h	16879;"	d
+DEF_TX_ACK_POLICY_2_7	smac/hal/ssv6006c/ssv6006C_reg.h	16881;"	d
+DEF_TX_ACK_POLICY_3_0	smac/hal/ssv6006c/ssv6006C_reg.h	16886;"	d
+DEF_TX_ACK_POLICY_3_1	smac/hal/ssv6006c/ssv6006C_reg.h	16888;"	d
+DEF_TX_ACK_POLICY_3_2	smac/hal/ssv6006c/ssv6006C_reg.h	16890;"	d
+DEF_TX_ACK_POLICY_3_3	smac/hal/ssv6006c/ssv6006C_reg.h	16892;"	d
+DEF_TX_ACK_POLICY_3_4	smac/hal/ssv6006c/ssv6006C_reg.h	16894;"	d
+DEF_TX_ACK_POLICY_3_5	smac/hal/ssv6006c/ssv6006C_reg.h	16896;"	d
+DEF_TX_ACK_POLICY_3_6	smac/hal/ssv6006c/ssv6006C_reg.h	16898;"	d
+DEF_TX_ACK_POLICY_3_7	smac/hal/ssv6006c/ssv6006C_reg.h	16900;"	d
+DEF_TX_ACK_POLICY_4_0	smac/hal/ssv6006c/ssv6006C_reg.h	16905;"	d
+DEF_TX_ACK_POLICY_4_1	smac/hal/ssv6006c/ssv6006C_reg.h	16907;"	d
+DEF_TX_ACK_POLICY_4_2	smac/hal/ssv6006c/ssv6006C_reg.h	16909;"	d
+DEF_TX_ACK_POLICY_4_3	smac/hal/ssv6006c/ssv6006C_reg.h	16911;"	d
+DEF_TX_ACK_POLICY_4_4	smac/hal/ssv6006c/ssv6006C_reg.h	16913;"	d
+DEF_TX_ACK_POLICY_4_5	smac/hal/ssv6006c/ssv6006C_reg.h	16915;"	d
+DEF_TX_ACK_POLICY_4_6	smac/hal/ssv6006c/ssv6006C_reg.h	16917;"	d
+DEF_TX_ACK_POLICY_4_7	smac/hal/ssv6006c/ssv6006C_reg.h	16919;"	d
+DEF_TX_ACK_POLICY_5_0	smac/hal/ssv6006c/ssv6006C_reg.h	16924;"	d
+DEF_TX_ACK_POLICY_5_1	smac/hal/ssv6006c/ssv6006C_reg.h	16926;"	d
+DEF_TX_ACK_POLICY_5_2	smac/hal/ssv6006c/ssv6006C_reg.h	16928;"	d
+DEF_TX_ACK_POLICY_5_3	smac/hal/ssv6006c/ssv6006C_reg.h	16930;"	d
+DEF_TX_ACK_POLICY_5_4	smac/hal/ssv6006c/ssv6006C_reg.h	16932;"	d
+DEF_TX_ACK_POLICY_5_5	smac/hal/ssv6006c/ssv6006C_reg.h	16934;"	d
+DEF_TX_ACK_POLICY_5_6	smac/hal/ssv6006c/ssv6006C_reg.h	16936;"	d
+DEF_TX_ACK_POLICY_5_7	smac/hal/ssv6006c/ssv6006C_reg.h	16938;"	d
+DEF_TX_ACK_POLICY_6_0	smac/hal/ssv6006c/ssv6006C_reg.h	16943;"	d
+DEF_TX_ACK_POLICY_6_1	smac/hal/ssv6006c/ssv6006C_reg.h	16945;"	d
+DEF_TX_ACK_POLICY_6_2	smac/hal/ssv6006c/ssv6006C_reg.h	16947;"	d
+DEF_TX_ACK_POLICY_6_3	smac/hal/ssv6006c/ssv6006C_reg.h	16949;"	d
+DEF_TX_ACK_POLICY_6_4	smac/hal/ssv6006c/ssv6006C_reg.h	16951;"	d
+DEF_TX_ACK_POLICY_6_5	smac/hal/ssv6006c/ssv6006C_reg.h	16953;"	d
+DEF_TX_ACK_POLICY_6_6	smac/hal/ssv6006c/ssv6006C_reg.h	16955;"	d
+DEF_TX_ACK_POLICY_6_7	smac/hal/ssv6006c/ssv6006C_reg.h	16957;"	d
+DEF_TX_ACK_POLICY_7_0	smac/hal/ssv6006c/ssv6006C_reg.h	16962;"	d
+DEF_TX_ACK_POLICY_7_1	smac/hal/ssv6006c/ssv6006C_reg.h	16964;"	d
+DEF_TX_ACK_POLICY_7_2	smac/hal/ssv6006c/ssv6006C_reg.h	16966;"	d
+DEF_TX_ACK_POLICY_7_3	smac/hal/ssv6006c/ssv6006C_reg.h	16968;"	d
+DEF_TX_ACK_POLICY_7_4	smac/hal/ssv6006c/ssv6006C_reg.h	16970;"	d
+DEF_TX_ACK_POLICY_7_5	smac/hal/ssv6006c/ssv6006C_reg.h	16972;"	d
+DEF_TX_ACK_POLICY_7_6	smac/hal/ssv6006c/ssv6006C_reg.h	16974;"	d
+DEF_TX_ACK_POLICY_7_7	smac/hal/ssv6006c/ssv6006C_reg.h	16976;"	d
+DEF_TX_ALLOC	include/ssv6200_reg.h	8753;"	d
+DEF_TX_ALLOC_SET	include/ssv6200_reg.h	8752;"	d
+DEF_TX_COMPENSATION_CONTROL	include/ssv6200_reg.h	9570;"	d
+DEF_TX_DAC_REGISTER	include/ssv6200_reg.h	9624;"	d
+DEF_TX_DROP_COUNT	smac/hal/ssv6006c/ssv6006C_reg.h	16432;"	d
+DEF_TX_ERROR_RECEOVERY	smac/hal/ssv6006c/ssv6006C_reg.h	16400;"	d
+DEF_TX_ETHER_TYPE_0	include/ssv6200_reg.h	8857;"	d
+DEF_TX_ETHER_TYPE_0	smac/hal/ssv6006c/ssv6006C_reg.h	16410;"	d
+DEF_TX_ETHER_TYPE_1	include/ssv6200_reg.h	8858;"	d
+DEF_TX_ETHER_TYPE_1	smac/hal/ssv6006c/ssv6006C_reg.h	16411;"	d
+DEF_TX_FE_REGISTER	include/ssv6200_reg.h	9616;"	d
+DEF_TX_FLOW_0	include/ssv6200_reg.h	8850;"	d
+DEF_TX_FLOW_0	smac/hal/ssv6006c/ssv6006C_reg.h	16395;"	d
+DEF_TX_FLOW_1	include/ssv6200_reg.h	8851;"	d
+DEF_TX_FLOW_1	smac/hal/ssv6006c/ssv6006C_reg.h	16396;"	d
+DEF_TX_GAIN_FACTOR	include/ssv6200_reg.h	9610;"	d
+DEF_TX_HOST_COMMAND_COUNT	smac/hal/ssv6006c/ssv6006C_reg.h	16434;"	d
+DEF_TX_ID0	include/ssv6200_reg.h	9370;"	d
+DEF_TX_ID0	smac/hal/ssv6006c/ssv6006C_reg.h	17952;"	d
+DEF_TX_ID1	include/ssv6200_reg.h	9371;"	d
+DEF_TX_ID1	smac/hal/ssv6006c/ssv6006C_reg.h	17953;"	d
+DEF_TX_ID2	include/ssv6200_reg.h	9384;"	d
+DEF_TX_ID2	smac/hal/ssv6006c/ssv6006C_reg.h	17966;"	d
+DEF_TX_ID3	include/ssv6200_reg.h	9385;"	d
+DEF_TX_ID3	smac/hal/ssv6006c/ssv6006C_reg.h	17967;"	d
+DEF_TX_ID_ALL_INFO	include/ssv6200_reg.h	9381;"	d
+DEF_TX_ID_ALL_INFO	smac/hal/ssv6006c/ssv6006C_reg.h	17963;"	d
+DEF_TX_ID_ALL_INFO2	include/ssv6200_reg.h	9388;"	d
+DEF_TX_ID_ALL_INFO2	smac/hal/ssv6006c/ssv6006C_reg.h	17970;"	d
+DEF_TX_ID_ALL_INFO_A	include/ssv6200_reg.h	9389;"	d
+DEF_TX_ID_ALL_INFO_A	smac/hal/ssv6006c/ssv6006C_reg.h	17971;"	d
+DEF_TX_ID_ALL_INFO_B	include/ssv6200_reg.h	9390;"	d
+DEF_TX_ID_ALL_INFO_B	smac/hal/ssv6006c/ssv6006C_reg.h	17972;"	d
+DEF_TX_ID_REMAIN_STATUS	include/ssv6200_reg.h	9378;"	d
+DEF_TX_ID_REMAIN_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	17960;"	d
+DEF_TX_ID_REMAIN_STATUS2	include/ssv6200_reg.h	9391;"	d
+DEF_TX_ID_REMAIN_STATUS2	smac/hal/ssv6006c/ssv6006C_reg.h	17973;"	d
+DEF_TX_IQ_CONTROL_0	include/ssv6200_reg.h	9567;"	d
+DEF_TX_IQ_CONTROL_1	include/ssv6200_reg.h	9568;"	d
+DEF_TX_IQ_CONTROL_2	include/ssv6200_reg.h	9569;"	d
+DEF_TX_LIMIT_INTR	include/ssv6200_reg.h	9380;"	d
+DEF_TX_LIMIT_INTR	smac/hal/ssv6006c/ssv6006C_reg.h	17962;"	d
+DEF_TX_PACKET_COUNTER	smac/hal/ssv6006c/ssv6006C_reg.h	16436;"	d
+DEF_TX_PACKET_ID	smac/hal/ssv6006c/ssv6006C_reg.h	16415;"	d
+DEF_TX_PACKET_LENGTH	smac/hal/ssv6006c/ssv6006C_reg.h	16414;"	d
+DEF_TX_PACKET_SEND_TO_RX_DIRECTLY	smac/hal/ssv6006c/ssv6006C_reg.h	16440;"	d
+DEF_TX_RX_TRAP_HW_ID_SELECTION_FUNCTION	smac/hal/ssv6006c/ssv6006C_reg.h	16442;"	d
+DEF_TX_SEG	include/ssv6200_reg.h	8747;"	d
+DEF_TX_SEG	smac/hal/ssv6006c/ssv6006C_reg.h	16248;"	d
+DEF_TX_SEQ_CTRL_0_0	include/ssv6200_reg.h	9123;"	d
+DEF_TX_SEQ_CTRL_0_0	smac/hal/ssv6006c/ssv6006C_reg.h	16742;"	d
+DEF_TX_SEQ_CTRL_0_1	include/ssv6200_reg.h	9125;"	d
+DEF_TX_SEQ_CTRL_0_1	smac/hal/ssv6006c/ssv6006C_reg.h	16744;"	d
+DEF_TX_SEQ_CTRL_0_2	include/ssv6200_reg.h	9127;"	d
+DEF_TX_SEQ_CTRL_0_2	smac/hal/ssv6006c/ssv6006C_reg.h	16746;"	d
+DEF_TX_SEQ_CTRL_0_3	include/ssv6200_reg.h	9129;"	d
+DEF_TX_SEQ_CTRL_0_3	smac/hal/ssv6006c/ssv6006C_reg.h	16748;"	d
+DEF_TX_SEQ_CTRL_0_4	include/ssv6200_reg.h	9131;"	d
+DEF_TX_SEQ_CTRL_0_4	smac/hal/ssv6006c/ssv6006C_reg.h	16750;"	d
+DEF_TX_SEQ_CTRL_0_5	include/ssv6200_reg.h	9133;"	d
+DEF_TX_SEQ_CTRL_0_5	smac/hal/ssv6006c/ssv6006C_reg.h	16752;"	d
+DEF_TX_SEQ_CTRL_0_6	include/ssv6200_reg.h	9135;"	d
+DEF_TX_SEQ_CTRL_0_6	smac/hal/ssv6006c/ssv6006C_reg.h	16754;"	d
+DEF_TX_SEQ_CTRL_0_7	include/ssv6200_reg.h	9137;"	d
+DEF_TX_SEQ_CTRL_0_7	smac/hal/ssv6006c/ssv6006C_reg.h	16756;"	d
+DEF_TX_SEQ_CTRL_1_0	include/ssv6200_reg.h	9142;"	d
+DEF_TX_SEQ_CTRL_1_0	smac/hal/ssv6006c/ssv6006C_reg.h	16761;"	d
+DEF_TX_SEQ_CTRL_1_1	include/ssv6200_reg.h	9144;"	d
+DEF_TX_SEQ_CTRL_1_1	smac/hal/ssv6006c/ssv6006C_reg.h	16763;"	d
+DEF_TX_SEQ_CTRL_1_2	include/ssv6200_reg.h	9146;"	d
+DEF_TX_SEQ_CTRL_1_2	smac/hal/ssv6006c/ssv6006C_reg.h	16765;"	d
+DEF_TX_SEQ_CTRL_1_3	include/ssv6200_reg.h	9148;"	d
+DEF_TX_SEQ_CTRL_1_3	smac/hal/ssv6006c/ssv6006C_reg.h	16767;"	d
+DEF_TX_SEQ_CTRL_1_4	include/ssv6200_reg.h	9150;"	d
+DEF_TX_SEQ_CTRL_1_4	smac/hal/ssv6006c/ssv6006C_reg.h	16769;"	d
+DEF_TX_SEQ_CTRL_1_5	include/ssv6200_reg.h	9152;"	d
+DEF_TX_SEQ_CTRL_1_5	smac/hal/ssv6006c/ssv6006C_reg.h	16771;"	d
+DEF_TX_SEQ_CTRL_1_6	include/ssv6200_reg.h	9154;"	d
+DEF_TX_SEQ_CTRL_1_6	smac/hal/ssv6006c/ssv6006C_reg.h	16773;"	d
+DEF_TX_SEQ_CTRL_1_7	include/ssv6200_reg.h	9156;"	d
+DEF_TX_SEQ_CTRL_1_7	smac/hal/ssv6006c/ssv6006C_reg.h	16775;"	d
+DEF_TX_SEQ_CTRL_2_0	smac/hal/ssv6006c/ssv6006C_reg.h	16868;"	d
+DEF_TX_SEQ_CTRL_2_1	smac/hal/ssv6006c/ssv6006C_reg.h	16870;"	d
+DEF_TX_SEQ_CTRL_2_2	smac/hal/ssv6006c/ssv6006C_reg.h	16872;"	d
+DEF_TX_SEQ_CTRL_2_3	smac/hal/ssv6006c/ssv6006C_reg.h	16874;"	d
+DEF_TX_SEQ_CTRL_2_4	smac/hal/ssv6006c/ssv6006C_reg.h	16876;"	d
+DEF_TX_SEQ_CTRL_2_5	smac/hal/ssv6006c/ssv6006C_reg.h	16878;"	d
+DEF_TX_SEQ_CTRL_2_6	smac/hal/ssv6006c/ssv6006C_reg.h	16880;"	d
+DEF_TX_SEQ_CTRL_2_7	smac/hal/ssv6006c/ssv6006C_reg.h	16882;"	d
+DEF_TX_SEQ_CTRL_3_0	smac/hal/ssv6006c/ssv6006C_reg.h	16887;"	d
+DEF_TX_SEQ_CTRL_3_1	smac/hal/ssv6006c/ssv6006C_reg.h	16889;"	d
+DEF_TX_SEQ_CTRL_3_2	smac/hal/ssv6006c/ssv6006C_reg.h	16891;"	d
+DEF_TX_SEQ_CTRL_3_3	smac/hal/ssv6006c/ssv6006C_reg.h	16893;"	d
+DEF_TX_SEQ_CTRL_3_4	smac/hal/ssv6006c/ssv6006C_reg.h	16895;"	d
+DEF_TX_SEQ_CTRL_3_5	smac/hal/ssv6006c/ssv6006C_reg.h	16897;"	d
+DEF_TX_SEQ_CTRL_3_6	smac/hal/ssv6006c/ssv6006C_reg.h	16899;"	d
+DEF_TX_SEQ_CTRL_3_7	smac/hal/ssv6006c/ssv6006C_reg.h	16901;"	d
+DEF_TX_SEQ_CTRL_4_0	smac/hal/ssv6006c/ssv6006C_reg.h	16906;"	d
+DEF_TX_SEQ_CTRL_4_1	smac/hal/ssv6006c/ssv6006C_reg.h	16908;"	d
+DEF_TX_SEQ_CTRL_4_2	smac/hal/ssv6006c/ssv6006C_reg.h	16910;"	d
+DEF_TX_SEQ_CTRL_4_3	smac/hal/ssv6006c/ssv6006C_reg.h	16912;"	d
+DEF_TX_SEQ_CTRL_4_4	smac/hal/ssv6006c/ssv6006C_reg.h	16914;"	d
+DEF_TX_SEQ_CTRL_4_5	smac/hal/ssv6006c/ssv6006C_reg.h	16916;"	d
+DEF_TX_SEQ_CTRL_4_6	smac/hal/ssv6006c/ssv6006C_reg.h	16918;"	d
+DEF_TX_SEQ_CTRL_4_7	smac/hal/ssv6006c/ssv6006C_reg.h	16920;"	d
+DEF_TX_SEQ_CTRL_5_0	smac/hal/ssv6006c/ssv6006C_reg.h	16925;"	d
+DEF_TX_SEQ_CTRL_5_1	smac/hal/ssv6006c/ssv6006C_reg.h	16927;"	d
+DEF_TX_SEQ_CTRL_5_2	smac/hal/ssv6006c/ssv6006C_reg.h	16929;"	d
+DEF_TX_SEQ_CTRL_5_3	smac/hal/ssv6006c/ssv6006C_reg.h	16931;"	d
+DEF_TX_SEQ_CTRL_5_4	smac/hal/ssv6006c/ssv6006C_reg.h	16933;"	d
+DEF_TX_SEQ_CTRL_5_5	smac/hal/ssv6006c/ssv6006C_reg.h	16935;"	d
+DEF_TX_SEQ_CTRL_5_6	smac/hal/ssv6006c/ssv6006C_reg.h	16937;"	d
+DEF_TX_SEQ_CTRL_5_7	smac/hal/ssv6006c/ssv6006C_reg.h	16939;"	d
+DEF_TX_SEQ_CTRL_6_0	smac/hal/ssv6006c/ssv6006C_reg.h	16944;"	d
+DEF_TX_SEQ_CTRL_6_1	smac/hal/ssv6006c/ssv6006C_reg.h	16946;"	d
+DEF_TX_SEQ_CTRL_6_2	smac/hal/ssv6006c/ssv6006C_reg.h	16948;"	d
+DEF_TX_SEQ_CTRL_6_3	smac/hal/ssv6006c/ssv6006C_reg.h	16950;"	d
+DEF_TX_SEQ_CTRL_6_4	smac/hal/ssv6006c/ssv6006C_reg.h	16952;"	d
+DEF_TX_SEQ_CTRL_6_5	smac/hal/ssv6006c/ssv6006C_reg.h	16954;"	d
+DEF_TX_SEQ_CTRL_6_6	smac/hal/ssv6006c/ssv6006C_reg.h	16956;"	d
+DEF_TX_SEQ_CTRL_6_7	smac/hal/ssv6006c/ssv6006C_reg.h	16958;"	d
+DEF_TX_SEQ_CTRL_7_0	smac/hal/ssv6006c/ssv6006C_reg.h	16963;"	d
+DEF_TX_SEQ_CTRL_7_1	smac/hal/ssv6006c/ssv6006C_reg.h	16965;"	d
+DEF_TX_SEQ_CTRL_7_2	smac/hal/ssv6006c/ssv6006C_reg.h	16967;"	d
+DEF_TX_SEQ_CTRL_7_3	smac/hal/ssv6006c/ssv6006C_reg.h	16969;"	d
+DEF_TX_SEQ_CTRL_7_4	smac/hal/ssv6006c/ssv6006C_reg.h	16971;"	d
+DEF_TX_SEQ_CTRL_7_5	smac/hal/ssv6006c/ssv6006C_reg.h	16973;"	d
+DEF_TX_SEQ_CTRL_7_6	smac/hal/ssv6006c/ssv6006C_reg.h	16975;"	d
+DEF_TX_SEQ_CTRL_7_7	smac/hal/ssv6006c/ssv6006C_reg.h	16977;"	d
+DEF_TX_TIME_OUT_READ_CTRL	include/ssv6200_reg.h	8698;"	d
+DEF_TX_TRAP_COUNT	smac/hal/ssv6006c/ssv6006C_reg.h	16430;"	d
+DEF_UART_DATA	include/ssv6200_reg.h	8765;"	d
+DEF_UART_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	16271;"	d
+DEF_UART_FCR	include/ssv6200_reg.h	8767;"	d
+DEF_UART_FCR	smac/hal/ssv6006c/ssv6006C_reg.h	16273;"	d
+DEF_UART_IER	include/ssv6200_reg.h	8766;"	d
+DEF_UART_IER	smac/hal/ssv6006c/ssv6006C_reg.h	16272;"	d
+DEF_UART_INT_MAP	smac/hal/ssv6006c/ssv6006C_reg.h	16282;"	d
+DEF_UART_ISR	include/ssv6200_reg.h	8774;"	d
+DEF_UART_ISR	smac/hal/ssv6006c/ssv6006C_reg.h	16280;"	d
+DEF_UART_LCR	include/ssv6200_reg.h	8768;"	d
+DEF_UART_LCR	smac/hal/ssv6006c/ssv6006C_reg.h	16274;"	d
+DEF_UART_LSR	include/ssv6200_reg.h	8770;"	d
+DEF_UART_LSR	smac/hal/ssv6006c/ssv6006C_reg.h	16276;"	d
+DEF_UART_MCR	include/ssv6200_reg.h	8769;"	d
+DEF_UART_MCR	smac/hal/ssv6006c/ssv6006C_reg.h	16275;"	d
+DEF_UART_MSR	include/ssv6200_reg.h	8771;"	d
+DEF_UART_MSR	smac/hal/ssv6006c/ssv6006C_reg.h	16277;"	d
+DEF_UART_POINTER	smac/hal/ssv6006c/ssv6006C_reg.h	16283;"	d
+DEF_UART_RTHR	include/ssv6200_reg.h	8773;"	d
+DEF_UART_RTHR	smac/hal/ssv6006c/ssv6006C_reg.h	16279;"	d
+DEF_UART_SPR	include/ssv6200_reg.h	8772;"	d
+DEF_UART_SPR	smac/hal/ssv6006c/ssv6006C_reg.h	16278;"	d
+DEF_UART_TTHR	smac/hal/ssv6006c/ssv6006C_reg.h	16281;"	d
+DEF_UART_W2B	include/ssv6200_reg.h	8567;"	d
+DEF_UART_W2B	smac/hal/ssv6006c/ssv6006C_reg.h	16091;"	d
+DEF_USB20_HOST_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	16118;"	d
+DEF_VERIFY_DATA	include/ssv6200_reg.h	8819;"	d
+DEF_VIAROM_EMA	smac/hal/ssv6006c/ssv6006C_reg.h	16101;"	d
+DEF_WAKE_PMU_ENABLE	smac/hal/ssv6006c/ssv6006C_reg.h	16130;"	d
+DEF_WBT_RX_ADC_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17367;"	d
+DEF_WF_DCOC_IDAC_REGISTER1	smac/hal/ssv6006c/ssv6006C_reg.h	17382;"	d
+DEF_WF_DCOC_IDAC_REGISTER10	smac/hal/ssv6006c/ssv6006C_reg.h	17391;"	d
+DEF_WF_DCOC_IDAC_REGISTER11	smac/hal/ssv6006c/ssv6006C_reg.h	17392;"	d
+DEF_WF_DCOC_IDAC_REGISTER12	smac/hal/ssv6006c/ssv6006C_reg.h	17393;"	d
+DEF_WF_DCOC_IDAC_REGISTER13	smac/hal/ssv6006c/ssv6006C_reg.h	17394;"	d
+DEF_WF_DCOC_IDAC_REGISTER14	smac/hal/ssv6006c/ssv6006C_reg.h	17395;"	d
+DEF_WF_DCOC_IDAC_REGISTER15	smac/hal/ssv6006c/ssv6006C_reg.h	17396;"	d
+DEF_WF_DCOC_IDAC_REGISTER16	smac/hal/ssv6006c/ssv6006C_reg.h	17397;"	d
+DEF_WF_DCOC_IDAC_REGISTER17	smac/hal/ssv6006c/ssv6006C_reg.h	17398;"	d
+DEF_WF_DCOC_IDAC_REGISTER18	smac/hal/ssv6006c/ssv6006C_reg.h	17399;"	d
+DEF_WF_DCOC_IDAC_REGISTER19	smac/hal/ssv6006c/ssv6006C_reg.h	17400;"	d
+DEF_WF_DCOC_IDAC_REGISTER2	smac/hal/ssv6006c/ssv6006C_reg.h	17383;"	d
+DEF_WF_DCOC_IDAC_REGISTER20	smac/hal/ssv6006c/ssv6006C_reg.h	17401;"	d
+DEF_WF_DCOC_IDAC_REGISTER21	smac/hal/ssv6006c/ssv6006C_reg.h	17402;"	d
+DEF_WF_DCOC_IDAC_REGISTER3	smac/hal/ssv6006c/ssv6006C_reg.h	17384;"	d
+DEF_WF_DCOC_IDAC_REGISTER4	smac/hal/ssv6006c/ssv6006C_reg.h	17385;"	d
+DEF_WF_DCOC_IDAC_REGISTER5	smac/hal/ssv6006c/ssv6006C_reg.h	17386;"	d
+DEF_WF_DCOC_IDAC_REGISTER6	smac/hal/ssv6006c/ssv6006C_reg.h	17387;"	d
+DEF_WF_DCOC_IDAC_REGISTER7	smac/hal/ssv6006c/ssv6006C_reg.h	17388;"	d
+DEF_WF_DCOC_IDAC_REGISTER8	smac/hal/ssv6006c/ssv6006C_reg.h	17389;"	d
+DEF_WF_DCOC_IDAC_REGISTER9	smac/hal/ssv6006c/ssv6006C_reg.h	17390;"	d
+DEF_WIFI_11B_RX_REG_000	smac/hal/ssv6006c/ssv6006C_reg.h	17800;"	d
+DEF_WIFI_11B_RX_REG_001	smac/hal/ssv6006c/ssv6006C_reg.h	17801;"	d
+DEF_WIFI_11B_RX_REG_002	smac/hal/ssv6006c/ssv6006C_reg.h	17802;"	d
+DEF_WIFI_11B_RX_REG_003	smac/hal/ssv6006c/ssv6006C_reg.h	17803;"	d
+DEF_WIFI_11B_RX_REG_004	smac/hal/ssv6006c/ssv6006C_reg.h	17804;"	d
+DEF_WIFI_11B_RX_REG_005	smac/hal/ssv6006c/ssv6006C_reg.h	17805;"	d
+DEF_WIFI_11B_RX_REG_006	smac/hal/ssv6006c/ssv6006C_reg.h	17806;"	d
+DEF_WIFI_11B_RX_REG_007	smac/hal/ssv6006c/ssv6006C_reg.h	17807;"	d
+DEF_WIFI_11B_RX_REG_008	smac/hal/ssv6006c/ssv6006C_reg.h	17808;"	d
+DEF_WIFI_11B_RX_REG_009	smac/hal/ssv6006c/ssv6006C_reg.h	17809;"	d
+DEF_WIFI_11B_RX_REG_010	smac/hal/ssv6006c/ssv6006C_reg.h	17810;"	d
+DEF_WIFI_11B_RX_REG_011	smac/hal/ssv6006c/ssv6006C_reg.h	17811;"	d
+DEF_WIFI_11B_RX_REG_012	smac/hal/ssv6006c/ssv6006C_reg.h	17812;"	d
+DEF_WIFI_11B_RX_REG_013	smac/hal/ssv6006c/ssv6006C_reg.h	17813;"	d
+DEF_WIFI_11B_RX_REG_014	smac/hal/ssv6006c/ssv6006C_reg.h	17814;"	d
+DEF_WIFI_11B_RX_REG_039	smac/hal/ssv6006c/ssv6006C_reg.h	17815;"	d
+DEF_WIFI_11B_RX_REG_040	smac/hal/ssv6006c/ssv6006C_reg.h	17816;"	d
+DEF_WIFI_11B_RX_REG_041	smac/hal/ssv6006c/ssv6006C_reg.h	17817;"	d
+DEF_WIFI_11B_RX_REG_240	smac/hal/ssv6006c/ssv6006C_reg.h	17818;"	d
+DEF_WIFI_11B_RX_REG_241	smac/hal/ssv6006c/ssv6006C_reg.h	17819;"	d
+DEF_WIFI_11B_RX_REG_244	smac/hal/ssv6006c/ssv6006C_reg.h	17820;"	d
+DEF_WIFI_11B_RX_REG_245	smac/hal/ssv6006c/ssv6006C_reg.h	17821;"	d
+DEF_WIFI_11B_RX_REG_246	smac/hal/ssv6006c/ssv6006C_reg.h	17822;"	d
+DEF_WIFI_11B_RX_REG_249	smac/hal/ssv6006c/ssv6006C_reg.h	17823;"	d
+DEF_WIFI_11B_RX_REG_250	smac/hal/ssv6006c/ssv6006C_reg.h	17824;"	d
+DEF_WIFI_11B_RX_REG_251	smac/hal/ssv6006c/ssv6006C_reg.h	17825;"	d
+DEF_WIFI_11B_RX_REG_252	smac/hal/ssv6006c/ssv6006C_reg.h	17826;"	d
+DEF_WIFI_11B_RX_REG_253	smac/hal/ssv6006c/ssv6006C_reg.h	17827;"	d
+DEF_WIFI_11B_RX_REG_254	smac/hal/ssv6006c/ssv6006C_reg.h	17828;"	d
+DEF_WIFI_11B_RX_REG_255	smac/hal/ssv6006c/ssv6006C_reg.h	17829;"	d
+DEF_WIFI_11B_TX_BB_RAMP_REG	smac/hal/ssv6006c/ssv6006C_reg.h	17796;"	d
+DEF_WIFI_11B_TX_DEBUG_SEL_REG	smac/hal/ssv6006c/ssv6006C_reg.h	17798;"	d
+DEF_WIFI_11B_TX_PKT_CNT_SENT_REG	smac/hal/ssv6006c/ssv6006C_reg.h	17797;"	d
+DEF_WIFI_11B_TX_RESERVED_REG	smac/hal/ssv6006c/ssv6006C_reg.h	17799;"	d
+DEF_WIFI_11GN_RX_REG_000	smac/hal/ssv6006c/ssv6006C_reg.h	17839;"	d
+DEF_WIFI_11GN_RX_REG_001	smac/hal/ssv6006c/ssv6006C_reg.h	17840;"	d
+DEF_WIFI_11GN_RX_REG_002	smac/hal/ssv6006c/ssv6006C_reg.h	17841;"	d
+DEF_WIFI_11GN_RX_REG_003	smac/hal/ssv6006c/ssv6006C_reg.h	17842;"	d
+DEF_WIFI_11GN_RX_REG_004_	smac/hal/ssv6006c/ssv6006C_reg.h	17843;"	d
+DEF_WIFI_11GN_RX_REG_005	smac/hal/ssv6006c/ssv6006C_reg.h	17844;"	d
+DEF_WIFI_11GN_RX_REG_006_	smac/hal/ssv6006c/ssv6006C_reg.h	17845;"	d
+DEF_WIFI_11GN_RX_REG_007_	smac/hal/ssv6006c/ssv6006C_reg.h	17846;"	d
+DEF_WIFI_11GN_RX_REG_008	smac/hal/ssv6006c/ssv6006C_reg.h	17847;"	d
+DEF_WIFI_11GN_RX_REG_009	smac/hal/ssv6006c/ssv6006C_reg.h	17848;"	d
+DEF_WIFI_11GN_RX_REG_010_	smac/hal/ssv6006c/ssv6006C_reg.h	17849;"	d
+DEF_WIFI_11GN_RX_REG_011	smac/hal/ssv6006c/ssv6006C_reg.h	17850;"	d
+DEF_WIFI_11GN_RX_REG_012	smac/hal/ssv6006c/ssv6006C_reg.h	17851;"	d
+DEF_WIFI_11GN_RX_REG_013	smac/hal/ssv6006c/ssv6006C_reg.h	17852;"	d
+DEF_WIFI_11GN_RX_REG_014	smac/hal/ssv6006c/ssv6006C_reg.h	17853;"	d
+DEF_WIFI_11GN_RX_REG_015	smac/hal/ssv6006c/ssv6006C_reg.h	17854;"	d
+DEF_WIFI_11GN_RX_REG_016	smac/hal/ssv6006c/ssv6006C_reg.h	17855;"	d
+DEF_WIFI_11GN_RX_REG_017	smac/hal/ssv6006c/ssv6006C_reg.h	17856;"	d
+DEF_WIFI_11GN_RX_REG_032	smac/hal/ssv6006c/ssv6006C_reg.h	17857;"	d
+DEF_WIFI_11GN_RX_REG_033	smac/hal/ssv6006c/ssv6006C_reg.h	17858;"	d
+DEF_WIFI_11GN_RX_REG_039	smac/hal/ssv6006c/ssv6006C_reg.h	17859;"	d
+DEF_WIFI_11GN_RX_REG_040	smac/hal/ssv6006c/ssv6006C_reg.h	17860;"	d
+DEF_WIFI_11GN_RX_REG_048	smac/hal/ssv6006c/ssv6006C_reg.h	17861;"	d
+DEF_WIFI_11GN_RX_REG_049	smac/hal/ssv6006c/ssv6006C_reg.h	17862;"	d
+DEF_WIFI_11GN_RX_REG_050	smac/hal/ssv6006c/ssv6006C_reg.h	17863;"	d
+DEF_WIFI_11GN_RX_REG_051	smac/hal/ssv6006c/ssv6006C_reg.h	17864;"	d
+DEF_WIFI_11GN_RX_REG_052	smac/hal/ssv6006c/ssv6006C_reg.h	17865;"	d
+DEF_WIFI_11GN_RX_REG_076	smac/hal/ssv6006c/ssv6006C_reg.h	17866;"	d
+DEF_WIFI_11GN_RX_REG_087	smac/hal/ssv6006c/ssv6006C_reg.h	17867;"	d
+DEF_WIFI_11GN_RX_REG_088	smac/hal/ssv6006c/ssv6006C_reg.h	17868;"	d
+DEF_WIFI_11GN_RX_REG_089	smac/hal/ssv6006c/ssv6006C_reg.h	17869;"	d
+DEF_WIFI_11GN_RX_REG_096	smac/hal/ssv6006c/ssv6006C_reg.h	17870;"	d
+DEF_WIFI_11GN_RX_REG_098	smac/hal/ssv6006c/ssv6006C_reg.h	17871;"	d
+DEF_WIFI_11GN_RX_REG_100	smac/hal/ssv6006c/ssv6006C_reg.h	17872;"	d
+DEF_WIFI_11GN_RX_REG_101	smac/hal/ssv6006c/ssv6006C_reg.h	17873;"	d
+DEF_WIFI_11GN_RX_REG_102	smac/hal/ssv6006c/ssv6006C_reg.h	17874;"	d
+DEF_WIFI_11GN_RX_REG_103	smac/hal/ssv6006c/ssv6006C_reg.h	17875;"	d
+DEF_WIFI_11GN_RX_REG_241	smac/hal/ssv6006c/ssv6006C_reg.h	17876;"	d
+DEF_WIFI_11GN_RX_REG_244	smac/hal/ssv6006c/ssv6006C_reg.h	17877;"	d
+DEF_WIFI_11GN_RX_REG_245	smac/hal/ssv6006c/ssv6006C_reg.h	17878;"	d
+DEF_WIFI_11GN_RX_REG_246	smac/hal/ssv6006c/ssv6006C_reg.h	17879;"	d
+DEF_WIFI_11GN_RX_REG_247	smac/hal/ssv6006c/ssv6006C_reg.h	17880;"	d
+DEF_WIFI_11GN_RX_REG_248	smac/hal/ssv6006c/ssv6006C_reg.h	17881;"	d
+DEF_WIFI_11GN_RX_REG_249	smac/hal/ssv6006c/ssv6006C_reg.h	17882;"	d
+DEF_WIFI_11GN_RX_REG_250	smac/hal/ssv6006c/ssv6006C_reg.h	17883;"	d
+DEF_WIFI_11GN_RX_REG_251	smac/hal/ssv6006c/ssv6006C_reg.h	17884;"	d
+DEF_WIFI_11GN_RX_REG_252	smac/hal/ssv6006c/ssv6006C_reg.h	17885;"	d
+DEF_WIFI_11GN_RX_REG_253	smac/hal/ssv6006c/ssv6006C_reg.h	17886;"	d
+DEF_WIFI_11GN_RX_REG_254	smac/hal/ssv6006c/ssv6006C_reg.h	17887;"	d
+DEF_WIFI_11GN_RX_REG_255	smac/hal/ssv6006c/ssv6006C_reg.h	17888;"	d
+DEF_WIFI_11GN_TX_BB_RAMP_REG	smac/hal/ssv6006c/ssv6006C_reg.h	17831;"	d
+DEF_WIFI_11GN_TX_CONTROL_REG	smac/hal/ssv6006c/ssv6006C_reg.h	17832;"	d
+DEF_WIFI_11GN_TX_DEBUG_SEL_REG	smac/hal/ssv6006c/ssv6006C_reg.h	17837;"	d
+DEF_WIFI_11GN_TX_FFT_SCALE_REG0	smac/hal/ssv6006c/ssv6006C_reg.h	17834;"	d
+DEF_WIFI_11GN_TX_FFT_SCALE_REG1	smac/hal/ssv6006c/ssv6006C_reg.h	17835;"	d
+DEF_WIFI_11GN_TX_MEM_BIST_REG	smac/hal/ssv6006c/ssv6006C_reg.h	17830;"	d
+DEF_WIFI_11GN_TX_PKT_CNT_SENT_REG	smac/hal/ssv6006c/ssv6006C_reg.h	17836;"	d
+DEF_WIFI_11GN_TX_RESERVED_REG	smac/hal/ssv6006c/ssv6006C_reg.h	17838;"	d
+DEF_WIFI_11GN_TX_STS_SCALE_REG	smac/hal/ssv6006c/ssv6006C_reg.h	17833;"	d
+DEF_WIFI_HT20_RX_FILTER_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17352;"	d
+DEF_WIFI_HT40_RX_FILTER_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17353;"	d
+DEF_WIFI_PADPD_2G_BB_GAIN_REG	smac/hal/ssv6006c/ssv6006C_reg.h	17665;"	d
+DEF_WIFI_PADPD_2G_CONTROL_REG	smac/hal/ssv6006c/ssv6006C_reg.h	17637;"	d
+DEF_WIFI_PADPD_2G_GAIN_REG0	smac/hal/ssv6006c/ssv6006C_reg.h	17638;"	d
+DEF_WIFI_PADPD_2G_GAIN_REG1	smac/hal/ssv6006c/ssv6006C_reg.h	17639;"	d
+DEF_WIFI_PADPD_2G_GAIN_REG2	smac/hal/ssv6006c/ssv6006C_reg.h	17640;"	d
+DEF_WIFI_PADPD_2G_GAIN_REG3	smac/hal/ssv6006c/ssv6006C_reg.h	17641;"	d
+DEF_WIFI_PADPD_2G_GAIN_REG4	smac/hal/ssv6006c/ssv6006C_reg.h	17642;"	d
+DEF_WIFI_PADPD_2G_GAIN_REG5	smac/hal/ssv6006c/ssv6006C_reg.h	17643;"	d
+DEF_WIFI_PADPD_2G_GAIN_REG6	smac/hal/ssv6006c/ssv6006C_reg.h	17644;"	d
+DEF_WIFI_PADPD_2G_GAIN_REG7	smac/hal/ssv6006c/ssv6006C_reg.h	17645;"	d
+DEF_WIFI_PADPD_2G_GAIN_REG8	smac/hal/ssv6006c/ssv6006C_reg.h	17646;"	d
+DEF_WIFI_PADPD_2G_GAIN_REG9	smac/hal/ssv6006c/ssv6006C_reg.h	17647;"	d
+DEF_WIFI_PADPD_2G_GAIN_REGA	smac/hal/ssv6006c/ssv6006C_reg.h	17648;"	d
+DEF_WIFI_PADPD_2G_GAIN_REGB	smac/hal/ssv6006c/ssv6006C_reg.h	17649;"	d
+DEF_WIFI_PADPD_2G_GAIN_REGC	smac/hal/ssv6006c/ssv6006C_reg.h	17650;"	d
+DEF_WIFI_PADPD_2G_PHASE_REG0	smac/hal/ssv6006c/ssv6006C_reg.h	17651;"	d
+DEF_WIFI_PADPD_2G_PHASE_REG1	smac/hal/ssv6006c/ssv6006C_reg.h	17652;"	d
+DEF_WIFI_PADPD_2G_PHASE_REG2	smac/hal/ssv6006c/ssv6006C_reg.h	17653;"	d
+DEF_WIFI_PADPD_2G_PHASE_REG3	smac/hal/ssv6006c/ssv6006C_reg.h	17654;"	d
+DEF_WIFI_PADPD_2G_PHASE_REG4	smac/hal/ssv6006c/ssv6006C_reg.h	17655;"	d
+DEF_WIFI_PADPD_2G_PHASE_REG5	smac/hal/ssv6006c/ssv6006C_reg.h	17656;"	d
+DEF_WIFI_PADPD_2G_PHASE_REG6	smac/hal/ssv6006c/ssv6006C_reg.h	17657;"	d
+DEF_WIFI_PADPD_2G_PHASE_REG7	smac/hal/ssv6006c/ssv6006C_reg.h	17658;"	d
+DEF_WIFI_PADPD_2G_PHASE_REG8	smac/hal/ssv6006c/ssv6006C_reg.h	17659;"	d
+DEF_WIFI_PADPD_2G_PHASE_REG9	smac/hal/ssv6006c/ssv6006C_reg.h	17660;"	d
+DEF_WIFI_PADPD_2G_PHASE_REGA	smac/hal/ssv6006c/ssv6006C_reg.h	17661;"	d
+DEF_WIFI_PADPD_2G_PHASE_REGB	smac/hal/ssv6006c/ssv6006C_reg.h	17662;"	d
+DEF_WIFI_PADPD_2G_PHASE_REGC	smac/hal/ssv6006c/ssv6006C_reg.h	17663;"	d
+DEF_WIFI_PADPD_5100_GAIN_REG0	smac/hal/ssv6006c/ssv6006C_reg.h	17524;"	d
+DEF_WIFI_PADPD_5100_GAIN_REG1	smac/hal/ssv6006c/ssv6006C_reg.h	17525;"	d
+DEF_WIFI_PADPD_5100_GAIN_REG2	smac/hal/ssv6006c/ssv6006C_reg.h	17526;"	d
+DEF_WIFI_PADPD_5100_GAIN_REG3	smac/hal/ssv6006c/ssv6006C_reg.h	17527;"	d
+DEF_WIFI_PADPD_5100_GAIN_REG4	smac/hal/ssv6006c/ssv6006C_reg.h	17528;"	d
+DEF_WIFI_PADPD_5100_GAIN_REG5	smac/hal/ssv6006c/ssv6006C_reg.h	17529;"	d
+DEF_WIFI_PADPD_5100_GAIN_REG6	smac/hal/ssv6006c/ssv6006C_reg.h	17530;"	d
+DEF_WIFI_PADPD_5100_GAIN_REG7	smac/hal/ssv6006c/ssv6006C_reg.h	17531;"	d
+DEF_WIFI_PADPD_5100_GAIN_REG8	smac/hal/ssv6006c/ssv6006C_reg.h	17532;"	d
+DEF_WIFI_PADPD_5100_GAIN_REG9	smac/hal/ssv6006c/ssv6006C_reg.h	17533;"	d
+DEF_WIFI_PADPD_5100_GAIN_REGA	smac/hal/ssv6006c/ssv6006C_reg.h	17534;"	d
+DEF_WIFI_PADPD_5100_GAIN_REGB	smac/hal/ssv6006c/ssv6006C_reg.h	17535;"	d
+DEF_WIFI_PADPD_5100_GAIN_REGC	smac/hal/ssv6006c/ssv6006C_reg.h	17536;"	d
+DEF_WIFI_PADPD_5100_PHASE_REG0	smac/hal/ssv6006c/ssv6006C_reg.h	17537;"	d
+DEF_WIFI_PADPD_5100_PHASE_REG1	smac/hal/ssv6006c/ssv6006C_reg.h	17538;"	d
+DEF_WIFI_PADPD_5100_PHASE_REG2	smac/hal/ssv6006c/ssv6006C_reg.h	17539;"	d
+DEF_WIFI_PADPD_5100_PHASE_REG3	smac/hal/ssv6006c/ssv6006C_reg.h	17540;"	d
+DEF_WIFI_PADPD_5100_PHASE_REG4	smac/hal/ssv6006c/ssv6006C_reg.h	17541;"	d
+DEF_WIFI_PADPD_5100_PHASE_REG5	smac/hal/ssv6006c/ssv6006C_reg.h	17542;"	d
+DEF_WIFI_PADPD_5100_PHASE_REG6	smac/hal/ssv6006c/ssv6006C_reg.h	17543;"	d
+DEF_WIFI_PADPD_5100_PHASE_REG7	smac/hal/ssv6006c/ssv6006C_reg.h	17544;"	d
+DEF_WIFI_PADPD_5100_PHASE_REG8	smac/hal/ssv6006c/ssv6006C_reg.h	17545;"	d
+DEF_WIFI_PADPD_5100_PHASE_REG9	smac/hal/ssv6006c/ssv6006C_reg.h	17546;"	d
+DEF_WIFI_PADPD_5100_PHASE_REGA	smac/hal/ssv6006c/ssv6006C_reg.h	17547;"	d
+DEF_WIFI_PADPD_5100_PHASE_REGB	smac/hal/ssv6006c/ssv6006C_reg.h	17548;"	d
+DEF_WIFI_PADPD_5100_PHASE_REGC	smac/hal/ssv6006c/ssv6006C_reg.h	17549;"	d
+DEF_WIFI_PADPD_5500_GAIN_REG0	smac/hal/ssv6006c/ssv6006C_reg.h	17550;"	d
+DEF_WIFI_PADPD_5500_GAIN_REG1	smac/hal/ssv6006c/ssv6006C_reg.h	17551;"	d
+DEF_WIFI_PADPD_5500_GAIN_REG2	smac/hal/ssv6006c/ssv6006C_reg.h	17552;"	d
+DEF_WIFI_PADPD_5500_GAIN_REG3	smac/hal/ssv6006c/ssv6006C_reg.h	17553;"	d
+DEF_WIFI_PADPD_5500_GAIN_REG4	smac/hal/ssv6006c/ssv6006C_reg.h	17554;"	d
+DEF_WIFI_PADPD_5500_GAIN_REG5	smac/hal/ssv6006c/ssv6006C_reg.h	17555;"	d
+DEF_WIFI_PADPD_5500_GAIN_REG6	smac/hal/ssv6006c/ssv6006C_reg.h	17556;"	d
+DEF_WIFI_PADPD_5500_GAIN_REG7	smac/hal/ssv6006c/ssv6006C_reg.h	17557;"	d
+DEF_WIFI_PADPD_5500_GAIN_REG8	smac/hal/ssv6006c/ssv6006C_reg.h	17558;"	d
+DEF_WIFI_PADPD_5500_GAIN_REG9	smac/hal/ssv6006c/ssv6006C_reg.h	17559;"	d
+DEF_WIFI_PADPD_5500_GAIN_REGA	smac/hal/ssv6006c/ssv6006C_reg.h	17560;"	d
+DEF_WIFI_PADPD_5500_GAIN_REGB	smac/hal/ssv6006c/ssv6006C_reg.h	17561;"	d
+DEF_WIFI_PADPD_5500_GAIN_REGC	smac/hal/ssv6006c/ssv6006C_reg.h	17562;"	d
+DEF_WIFI_PADPD_5500_PHASE_REG0	smac/hal/ssv6006c/ssv6006C_reg.h	17563;"	d
+DEF_WIFI_PADPD_5500_PHASE_REG1	smac/hal/ssv6006c/ssv6006C_reg.h	17564;"	d
+DEF_WIFI_PADPD_5500_PHASE_REG2	smac/hal/ssv6006c/ssv6006C_reg.h	17565;"	d
+DEF_WIFI_PADPD_5500_PHASE_REG3	smac/hal/ssv6006c/ssv6006C_reg.h	17566;"	d
+DEF_WIFI_PADPD_5500_PHASE_REG4	smac/hal/ssv6006c/ssv6006C_reg.h	17567;"	d
+DEF_WIFI_PADPD_5500_PHASE_REG5	smac/hal/ssv6006c/ssv6006C_reg.h	17568;"	d
+DEF_WIFI_PADPD_5500_PHASE_REG6	smac/hal/ssv6006c/ssv6006C_reg.h	17569;"	d
+DEF_WIFI_PADPD_5500_PHASE_REG7	smac/hal/ssv6006c/ssv6006C_reg.h	17570;"	d
+DEF_WIFI_PADPD_5500_PHASE_REG8	smac/hal/ssv6006c/ssv6006C_reg.h	17571;"	d
+DEF_WIFI_PADPD_5500_PHASE_REG9	smac/hal/ssv6006c/ssv6006C_reg.h	17572;"	d
+DEF_WIFI_PADPD_5500_PHASE_REGA	smac/hal/ssv6006c/ssv6006C_reg.h	17573;"	d
+DEF_WIFI_PADPD_5500_PHASE_REGB	smac/hal/ssv6006c/ssv6006C_reg.h	17574;"	d
+DEF_WIFI_PADPD_5500_PHASE_REGC	smac/hal/ssv6006c/ssv6006C_reg.h	17575;"	d
+DEF_WIFI_PADPD_5700_GAIN_REG0	smac/hal/ssv6006c/ssv6006C_reg.h	17576;"	d
+DEF_WIFI_PADPD_5700_GAIN_REG1	smac/hal/ssv6006c/ssv6006C_reg.h	17577;"	d
+DEF_WIFI_PADPD_5700_GAIN_REG2	smac/hal/ssv6006c/ssv6006C_reg.h	17578;"	d
+DEF_WIFI_PADPD_5700_GAIN_REG3	smac/hal/ssv6006c/ssv6006C_reg.h	17579;"	d
+DEF_WIFI_PADPD_5700_GAIN_REG4	smac/hal/ssv6006c/ssv6006C_reg.h	17580;"	d
+DEF_WIFI_PADPD_5700_GAIN_REG5	smac/hal/ssv6006c/ssv6006C_reg.h	17581;"	d
+DEF_WIFI_PADPD_5700_GAIN_REG6	smac/hal/ssv6006c/ssv6006C_reg.h	17582;"	d
+DEF_WIFI_PADPD_5700_GAIN_REG7	smac/hal/ssv6006c/ssv6006C_reg.h	17583;"	d
+DEF_WIFI_PADPD_5700_GAIN_REG8	smac/hal/ssv6006c/ssv6006C_reg.h	17584;"	d
+DEF_WIFI_PADPD_5700_GAIN_REG9	smac/hal/ssv6006c/ssv6006C_reg.h	17585;"	d
+DEF_WIFI_PADPD_5700_GAIN_REGA	smac/hal/ssv6006c/ssv6006C_reg.h	17586;"	d
+DEF_WIFI_PADPD_5700_GAIN_REGB	smac/hal/ssv6006c/ssv6006C_reg.h	17587;"	d
+DEF_WIFI_PADPD_5700_GAIN_REGC	smac/hal/ssv6006c/ssv6006C_reg.h	17588;"	d
+DEF_WIFI_PADPD_5700_PHASE_REG0	smac/hal/ssv6006c/ssv6006C_reg.h	17589;"	d
+DEF_WIFI_PADPD_5700_PHASE_REG1	smac/hal/ssv6006c/ssv6006C_reg.h	17590;"	d
+DEF_WIFI_PADPD_5700_PHASE_REG2	smac/hal/ssv6006c/ssv6006C_reg.h	17591;"	d
+DEF_WIFI_PADPD_5700_PHASE_REG3	smac/hal/ssv6006c/ssv6006C_reg.h	17592;"	d
+DEF_WIFI_PADPD_5700_PHASE_REG4	smac/hal/ssv6006c/ssv6006C_reg.h	17593;"	d
+DEF_WIFI_PADPD_5700_PHASE_REG5	smac/hal/ssv6006c/ssv6006C_reg.h	17594;"	d
+DEF_WIFI_PADPD_5700_PHASE_REG6	smac/hal/ssv6006c/ssv6006C_reg.h	17595;"	d
+DEF_WIFI_PADPD_5700_PHASE_REG7	smac/hal/ssv6006c/ssv6006C_reg.h	17596;"	d
+DEF_WIFI_PADPD_5700_PHASE_REG8	smac/hal/ssv6006c/ssv6006C_reg.h	17597;"	d
+DEF_WIFI_PADPD_5700_PHASE_REG9	smac/hal/ssv6006c/ssv6006C_reg.h	17598;"	d
+DEF_WIFI_PADPD_5700_PHASE_REGA	smac/hal/ssv6006c/ssv6006C_reg.h	17599;"	d
+DEF_WIFI_PADPD_5700_PHASE_REGB	smac/hal/ssv6006c/ssv6006C_reg.h	17600;"	d
+DEF_WIFI_PADPD_5700_PHASE_REGC	smac/hal/ssv6006c/ssv6006C_reg.h	17601;"	d
+DEF_WIFI_PADPD_5900_GAIN_REG0	smac/hal/ssv6006c/ssv6006C_reg.h	17602;"	d
+DEF_WIFI_PADPD_5900_GAIN_REG1	smac/hal/ssv6006c/ssv6006C_reg.h	17603;"	d
+DEF_WIFI_PADPD_5900_GAIN_REG2	smac/hal/ssv6006c/ssv6006C_reg.h	17604;"	d
+DEF_WIFI_PADPD_5900_GAIN_REG3	smac/hal/ssv6006c/ssv6006C_reg.h	17605;"	d
+DEF_WIFI_PADPD_5900_GAIN_REG4	smac/hal/ssv6006c/ssv6006C_reg.h	17606;"	d
+DEF_WIFI_PADPD_5900_GAIN_REG5	smac/hal/ssv6006c/ssv6006C_reg.h	17607;"	d
+DEF_WIFI_PADPD_5900_GAIN_REG6	smac/hal/ssv6006c/ssv6006C_reg.h	17608;"	d
+DEF_WIFI_PADPD_5900_GAIN_REG7	smac/hal/ssv6006c/ssv6006C_reg.h	17609;"	d
+DEF_WIFI_PADPD_5900_GAIN_REG8	smac/hal/ssv6006c/ssv6006C_reg.h	17610;"	d
+DEF_WIFI_PADPD_5900_GAIN_REG9	smac/hal/ssv6006c/ssv6006C_reg.h	17611;"	d
+DEF_WIFI_PADPD_5900_GAIN_REGA	smac/hal/ssv6006c/ssv6006C_reg.h	17612;"	d
+DEF_WIFI_PADPD_5900_GAIN_REGB	smac/hal/ssv6006c/ssv6006C_reg.h	17613;"	d
+DEF_WIFI_PADPD_5900_GAIN_REGC	smac/hal/ssv6006c/ssv6006C_reg.h	17614;"	d
+DEF_WIFI_PADPD_5900_PHASE_REG0	smac/hal/ssv6006c/ssv6006C_reg.h	17615;"	d
+DEF_WIFI_PADPD_5900_PHASE_REG1	smac/hal/ssv6006c/ssv6006C_reg.h	17616;"	d
+DEF_WIFI_PADPD_5900_PHASE_REG2	smac/hal/ssv6006c/ssv6006C_reg.h	17617;"	d
+DEF_WIFI_PADPD_5900_PHASE_REG3	smac/hal/ssv6006c/ssv6006C_reg.h	17618;"	d
+DEF_WIFI_PADPD_5900_PHASE_REG4	smac/hal/ssv6006c/ssv6006C_reg.h	17619;"	d
+DEF_WIFI_PADPD_5900_PHASE_REG5	smac/hal/ssv6006c/ssv6006C_reg.h	17620;"	d
+DEF_WIFI_PADPD_5900_PHASE_REG6	smac/hal/ssv6006c/ssv6006C_reg.h	17621;"	d
+DEF_WIFI_PADPD_5900_PHASE_REG7	smac/hal/ssv6006c/ssv6006C_reg.h	17622;"	d
+DEF_WIFI_PADPD_5900_PHASE_REG8	smac/hal/ssv6006c/ssv6006C_reg.h	17623;"	d
+DEF_WIFI_PADPD_5900_PHASE_REG9	smac/hal/ssv6006c/ssv6006C_reg.h	17624;"	d
+DEF_WIFI_PADPD_5900_PHASE_REGA	smac/hal/ssv6006c/ssv6006C_reg.h	17625;"	d
+DEF_WIFI_PADPD_5900_PHASE_REGB	smac/hal/ssv6006c/ssv6006C_reg.h	17626;"	d
+DEF_WIFI_PADPD_5900_PHASE_REGC	smac/hal/ssv6006c/ssv6006C_reg.h	17627;"	d
+DEF_WIFI_PADPD_5G_BB_GAIN_REG	smac/hal/ssv6006c/ssv6006C_reg.h	17664;"	d
+DEF_WIFI_PADPD_CAL_RX_PADPD_REG	smac/hal/ssv6006c/ssv6006C_reg.h	17629;"	d
+DEF_WIFI_PADPD_CAL_RX_RO	smac/hal/ssv6006c/ssv6006C_reg.h	17630;"	d
+DEF_WIFI_PADPD_CAL_TONEGEN_REG	smac/hal/ssv6006c/ssv6006C_reg.h	17628;"	d
+DEF_WIFI_PADPD_CFR	smac/hal/ssv6006c/ssv6006C_reg.h	17631;"	d
+DEF_WIFI_PADPD_DC_RM	smac/hal/ssv6006c/ssv6006C_reg.h	17632;"	d
+DEF_WIFI_PADPD_RESERVED_REG	smac/hal/ssv6006c/ssv6006C_reg.h	17680;"	d
+DEF_WIFI_PADPD_TXIQ_CLIP_REG	smac/hal/ssv6006c/ssv6006C_reg.h	17633;"	d
+DEF_WIFI_PADPD_TXIQ_CONTROL_REG	smac/hal/ssv6006c/ssv6006C_reg.h	17634;"	d
+DEF_WIFI_PADPD_TXIQ_DC_OFFSET_REG	smac/hal/ssv6006c/ssv6006C_reg.h	17636;"	d
+DEF_WIFI_PADPD_TXIQ_DPD_DC_REG	smac/hal/ssv6006c/ssv6006C_reg.h	17635;"	d
+DEF_WIFI_PADPD_TX_GAIN_0P5DB_REG	smac/hal/ssv6006c/ssv6006C_reg.h	17666;"	d
+DEF_WIFI_PHY_AGC_RELOCK_1	smac/hal/ssv6006c/ssv6006C_reg.h	17747;"	d
+DEF_WIFI_PHY_AGC_RELOCK_2	smac/hal/ssv6006c/ssv6006C_reg.h	17748;"	d
+DEF_WIFI_PHY_AUDIO_CLK_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	17793;"	d
+DEF_WIFI_PHY_COMMON_11BGN_DIGPWR_REG	smac/hal/ssv6006c/ssv6006C_reg.h	17736;"	d
+DEF_WIFI_PHY_COMMON_11B_DAGC_REG0	smac/hal/ssv6006c/ssv6006C_reg.h	17732;"	d
+DEF_WIFI_PHY_COMMON_11B_DAGC_REG1	smac/hal/ssv6006c/ssv6006C_reg.h	17733;"	d
+DEF_WIFI_PHY_COMMON_11GN20_DAGC_REG0	smac/hal/ssv6006c/ssv6006C_reg.h	17734;"	d
+DEF_WIFI_PHY_COMMON_11GN20_DAGC_REG1	smac/hal/ssv6006c/ssv6006C_reg.h	17735;"	d
+DEF_WIFI_PHY_COMMON_11GN40_DAGC_REG0	smac/hal/ssv6006c/ssv6006C_reg.h	17757;"	d
+DEF_WIFI_PHY_COMMON_11GN40_DAGC_REG1	smac/hal/ssv6006c/ssv6006C_reg.h	17758;"	d
+DEF_WIFI_PHY_COMMON_11GN_DAGC_INI_REG	smac/hal/ssv6006c/ssv6006C_reg.h	17759;"	d
+DEF_WIFI_PHY_COMMON_BB_SCALE_REG_0	smac/hal/ssv6006c/ssv6006C_reg.h	17771;"	d
+DEF_WIFI_PHY_COMMON_BB_SCALE_REG_1	smac/hal/ssv6006c/ssv6006C_reg.h	17772;"	d
+DEF_WIFI_PHY_COMMON_BB_SCALE_REG_2	smac/hal/ssv6006c/ssv6006C_reg.h	17773;"	d
+DEF_WIFI_PHY_COMMON_BB_SCALE_REG_3	smac/hal/ssv6006c/ssv6006C_reg.h	17774;"	d
+DEF_WIFI_PHY_COMMON_DES_REG0	smac/hal/ssv6006c/ssv6006C_reg.h	17719;"	d
+DEF_WIFI_PHY_COMMON_DES_REG1	smac/hal/ssv6006c/ssv6006C_reg.h	17720;"	d
+DEF_WIFI_PHY_COMMON_DES_REG2	smac/hal/ssv6006c/ssv6006C_reg.h	17721;"	d
+DEF_WIFI_PHY_COMMON_DES_REG3	smac/hal/ssv6006c/ssv6006C_reg.h	17722;"	d
+DEF_WIFI_PHY_COMMON_DES_REG4	smac/hal/ssv6006c/ssv6006C_reg.h	17723;"	d
+DEF_WIFI_PHY_COMMON_DES_REG5	smac/hal/ssv6006c/ssv6006C_reg.h	17725;"	d
+DEF_WIFI_PHY_COMMON_DES_REG6	smac/hal/ssv6006c/ssv6006C_reg.h	17726;"	d
+DEF_WIFI_PHY_COMMON_EDCCA_0	smac/hal/ssv6006c/ssv6006C_reg.h	17744;"	d
+DEF_WIFI_PHY_COMMON_EDCCA_1	smac/hal/ssv6006c/ssv6006C_reg.h	17745;"	d
+DEF_WIFI_PHY_COMMON_EDCCA_2	smac/hal/ssv6006c/ssv6006C_reg.h	17746;"	d
+DEF_WIFI_PHY_COMMON_ENABLE_REG	smac/hal/ssv6006c/ssv6006C_reg.h	17717;"	d
+DEF_WIFI_PHY_COMMON_MAC_IF_CNT_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	17790;"	d
+DEF_WIFI_PHY_COMMON_MAC_IF_CNT_RO	smac/hal/ssv6006c/ssv6006C_reg.h	17791;"	d
+DEF_WIFI_PHY_COMMON_MAC_PKT_REG_0	smac/hal/ssv6006c/ssv6006C_reg.h	17760;"	d
+DEF_WIFI_PHY_COMMON_MAC_PKT_REG_1	smac/hal/ssv6006c/ssv6006C_reg.h	17761;"	d
+DEF_WIFI_PHY_COMMON_MAC_PKT_REG_2	smac/hal/ssv6006c/ssv6006C_reg.h	17762;"	d
+DEF_WIFI_PHY_COMMON_MAC_PKT_REG_3	smac/hal/ssv6006c/ssv6006C_reg.h	17763;"	d
+DEF_WIFI_PHY_COMMON_MAC_PKT_REG_4	smac/hal/ssv6006c/ssv6006C_reg.h	17764;"	d
+DEF_WIFI_PHY_COMMON_MAC_PKT_REG_5	smac/hal/ssv6006c/ssv6006C_reg.h	17765;"	d
+DEF_WIFI_PHY_COMMON_MAC_PKT_REG_6	smac/hal/ssv6006c/ssv6006C_reg.h	17766;"	d
+DEF_WIFI_PHY_COMMON_MAC_PKT_REG_7	smac/hal/ssv6006c/ssv6006C_reg.h	17767;"	d
+DEF_WIFI_PHY_COMMON_MAC_PKT_REG_8	smac/hal/ssv6006c/ssv6006C_reg.h	17768;"	d
+DEF_WIFI_PHY_COMMON_MAC_PKT_REG_9	smac/hal/ssv6006c/ssv6006C_reg.h	17769;"	d
+DEF_WIFI_PHY_COMMON_MAC_PKT_REG_A	smac/hal/ssv6006c/ssv6006C_reg.h	17770;"	d
+DEF_WIFI_PHY_COMMON_RESERVED_REG	smac/hal/ssv6006c/ssv6006C_reg.h	17795;"	d
+DEF_WIFI_PHY_COMMON_RFAGC_REG0	smac/hal/ssv6006c/ssv6006C_reg.h	17727;"	d
+DEF_WIFI_PHY_COMMON_RFAGC_REG1	smac/hal/ssv6006c/ssv6006C_reg.h	17728;"	d
+DEF_WIFI_PHY_COMMON_RFAGC_REG2	smac/hal/ssv6006c/ssv6006C_reg.h	17729;"	d
+DEF_WIFI_PHY_COMMON_RFAGC_REG3	smac/hal/ssv6006c/ssv6006C_reg.h	17730;"	d
+DEF_WIFI_PHY_COMMON_RFAGC_REG4	smac/hal/ssv6006c/ssv6006C_reg.h	17731;"	d
+DEF_WIFI_PHY_COMMON_RFAGC_RO00	smac/hal/ssv6006c/ssv6006C_reg.h	17737;"	d
+DEF_WIFI_PHY_COMMON_RFAGC_RO01	smac/hal/ssv6006c/ssv6006C_reg.h	17738;"	d
+DEF_WIFI_PHY_COMMON_RFAGC_RO02	smac/hal/ssv6006c/ssv6006C_reg.h	17739;"	d
+DEF_WIFI_PHY_COMMON_RF_PWR_REG_0	smac/hal/ssv6006c/ssv6006C_reg.h	17775;"	d
+DEF_WIFI_PHY_COMMON_RF_PWR_REG_1	smac/hal/ssv6006c/ssv6006C_reg.h	17776;"	d
+DEF_WIFI_PHY_COMMON_RF_PWR_REG_2	smac/hal/ssv6006c/ssv6006C_reg.h	17777;"	d
+DEF_WIFI_PHY_COMMON_RF_PWR_REG_3	smac/hal/ssv6006c/ssv6006C_reg.h	17778;"	d
+DEF_WIFI_PHY_COMMON_RSSI_TBUS_REG	smac/hal/ssv6006c/ssv6006C_reg.h	17742;"	d
+DEF_WIFI_PHY_COMMON_RXDC	smac/hal/ssv6006c/ssv6006C_reg.h	17740;"	d
+DEF_WIFI_PHY_COMMON_RXDC_RO	smac/hal/ssv6006c/ssv6006C_reg.h	17741;"	d
+DEF_WIFI_PHY_COMMON_RX_BKN_MON_RO	smac/hal/ssv6006c/ssv6006C_reg.h	17789;"	d
+DEF_WIFI_PHY_COMMON_RX_EN_CNT_REG	smac/hal/ssv6006c/ssv6006C_reg.h	17743;"	d
+DEF_WIFI_PHY_COMMON_RX_FFT_MEM_BIST_REG	smac/hal/ssv6006c/ssv6006C_reg.h	17792;"	d
+DEF_WIFI_PHY_COMMON_RX_LENGTH_CNT_REG0	smac/hal/ssv6006c/ssv6006C_reg.h	17751;"	d
+DEF_WIFI_PHY_COMMON_RX_LENGTH_CNT_REG1	smac/hal/ssv6006c/ssv6006C_reg.h	17752;"	d
+DEF_WIFI_PHY_COMMON_RX_LENGTH_CNT_RO	smac/hal/ssv6006c/ssv6006C_reg.h	17754;"	d
+DEF_WIFI_PHY_COMMON_RX_MON_0	smac/hal/ssv6006c/ssv6006C_reg.h	17779;"	d
+DEF_WIFI_PHY_COMMON_RX_MON_1	smac/hal/ssv6006c/ssv6006C_reg.h	17780;"	d
+DEF_WIFI_PHY_COMMON_RX_MON_2	smac/hal/ssv6006c/ssv6006C_reg.h	17781;"	d
+DEF_WIFI_PHY_COMMON_RX_MON_3	smac/hal/ssv6006c/ssv6006C_reg.h	17782;"	d
+DEF_WIFI_PHY_COMMON_RX_MON_4	smac/hal/ssv6006c/ssv6006C_reg.h	17783;"	d
+DEF_WIFI_PHY_COMMON_RX_MON_5	smac/hal/ssv6006c/ssv6006C_reg.h	17784;"	d
+DEF_WIFI_PHY_COMMON_RX_MON_6	smac/hal/ssv6006c/ssv6006C_reg.h	17785;"	d
+DEF_WIFI_PHY_COMMON_RX_MON_7	smac/hal/ssv6006c/ssv6006C_reg.h	17786;"	d
+DEF_WIFI_PHY_COMMON_RX_MON_8	smac/hal/ssv6006c/ssv6006C_reg.h	17787;"	d
+DEF_WIFI_PHY_COMMON_RX_TMR_MON_RO	smac/hal/ssv6006c/ssv6006C_reg.h	17788;"	d
+DEF_WIFI_PHY_COMMON_SYS_REG	smac/hal/ssv6006c/ssv6006C_reg.h	17716;"	d
+DEF_WIFI_PHY_COMMON_TOP_STATUS_RO	smac/hal/ssv6006c/ssv6006C_reg.h	17794;"	d
+DEF_WIFI_PHY_COMMON_TRX_TYPE_CNT_REG	smac/hal/ssv6006c/ssv6006C_reg.h	17755;"	d
+DEF_WIFI_PHY_COMMON_TRX_TYPE_CNT_RO	smac/hal/ssv6006c/ssv6006C_reg.h	17756;"	d
+DEF_WIFI_PHY_COMMON_TX_CONTROL	smac/hal/ssv6006c/ssv6006C_reg.h	17724;"	d
+DEF_WIFI_PHY_COMMON_TX_LENGTH_CNT_REG0	smac/hal/ssv6006c/ssv6006C_reg.h	17749;"	d
+DEF_WIFI_PHY_COMMON_TX_LENGTH_CNT_REG1	smac/hal/ssv6006c/ssv6006C_reg.h	17750;"	d
+DEF_WIFI_PHY_COMMON_TX_LENGTH_CNT_RO	smac/hal/ssv6006c/ssv6006C_reg.h	17753;"	d
+DEF_WIFI_PHY_COMMON_VERSION_REG	smac/hal/ssv6006c/ssv6006C_reg.h	17718;"	d
+DEF_WIFI_R2T_TIMER_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17421;"	d
+DEF_WIFI_RADAR_CHIRP_REG	smac/hal/ssv6006c/ssv6006C_reg.h	17901;"	d
+DEF_WIFI_RADAR_REG_00	smac/hal/ssv6006c/ssv6006C_reg.h	17889;"	d
+DEF_WIFI_RADAR_REG_01	smac/hal/ssv6006c/ssv6006C_reg.h	17890;"	d
+DEF_WIFI_RADAR_REG_02	smac/hal/ssv6006c/ssv6006C_reg.h	17891;"	d
+DEF_WIFI_RADAR_REG_03	smac/hal/ssv6006c/ssv6006C_reg.h	17892;"	d
+DEF_WIFI_RADAR_REG_04	smac/hal/ssv6006c/ssv6006C_reg.h	17893;"	d
+DEF_WIFI_RADAR_REG_DB_A0_RO	smac/hal/ssv6006c/ssv6006C_reg.h	17895;"	d
+DEF_WIFI_RADAR_REG_DB_A1_RO	smac/hal/ssv6006c/ssv6006C_reg.h	17896;"	d
+DEF_WIFI_RADAR_REG_DB_A2_RO	smac/hal/ssv6006c/ssv6006C_reg.h	17897;"	d
+DEF_WIFI_RADAR_REG_DB_P0_RO	smac/hal/ssv6006c/ssv6006C_reg.h	17898;"	d
+DEF_WIFI_RADAR_REG_DB_P1_RO	smac/hal/ssv6006c/ssv6006C_reg.h	17899;"	d
+DEF_WIFI_RADAR_REG_DB_P2_RO	smac/hal/ssv6006c/ssv6006C_reg.h	17900;"	d
+DEF_WIFI_RADAR_REG_RO	smac/hal/ssv6006c/ssv6006C_reg.h	17894;"	d
+DEF_WIFI_T2R_TIMER_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17420;"	d
+DEF_WIFI_TX_DAC_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	17368;"	d
+DEF_WR_ALC	include/ssv6200_reg.h	9360;"	d
+DEF_WR_ALC	smac/hal/ssv6006c/ssv6006C_reg.h	17942;"	d
+DEF_WSID0	include/ssv6200_reg.h	9119;"	d
+DEF_WSID0	smac/hal/ssv6006c/ssv6006C_reg.h	16738;"	d
+DEF_WSID0_TID0_RX_SEQ	include/ssv6200_reg.h	9035;"	d
+DEF_WSID0_TID1_RX_SEQ	include/ssv6200_reg.h	9036;"	d
+DEF_WSID0_TID2_RX_SEQ	include/ssv6200_reg.h	9037;"	d
+DEF_WSID0_TID3_RX_SEQ	include/ssv6200_reg.h	9038;"	d
+DEF_WSID0_TID4_RX_SEQ	include/ssv6200_reg.h	9039;"	d
+DEF_WSID0_TID5_RX_SEQ	include/ssv6200_reg.h	9040;"	d
+DEF_WSID0_TID6_RX_SEQ	include/ssv6200_reg.h	9041;"	d
+DEF_WSID0_TID7_RX_SEQ	include/ssv6200_reg.h	9042;"	d
+DEF_WSID1	include/ssv6200_reg.h	9138;"	d
+DEF_WSID1	smac/hal/ssv6006c/ssv6006C_reg.h	16757;"	d
+DEF_WSID1_TID0_RX_SEQ	include/ssv6200_reg.h	9043;"	d
+DEF_WSID1_TID1_RX_SEQ	include/ssv6200_reg.h	9044;"	d
+DEF_WSID1_TID2_RX_SEQ	include/ssv6200_reg.h	9045;"	d
+DEF_WSID1_TID3_RX_SEQ	include/ssv6200_reg.h	9046;"	d
+DEF_WSID1_TID4_RX_SEQ	include/ssv6200_reg.h	9047;"	d
+DEF_WSID1_TID5_RX_SEQ	include/ssv6200_reg.h	9048;"	d
+DEF_WSID1_TID6_RX_SEQ	include/ssv6200_reg.h	9049;"	d
+DEF_WSID1_TID7_RX_SEQ	include/ssv6200_reg.h	9050;"	d
+DEF_WSID2	smac/hal/ssv6006c/ssv6006C_reg.h	16864;"	d
+DEF_WSID3	smac/hal/ssv6006c/ssv6006C_reg.h	16883;"	d
+DEF_WSID4	smac/hal/ssv6006c/ssv6006C_reg.h	16902;"	d
+DEF_WSID5	smac/hal/ssv6006c/ssv6006C_reg.h	16921;"	d
+DEF_WSID6	smac/hal/ssv6006c/ssv6006C_reg.h	16940;"	d
+DEF_WSID7	smac/hal/ssv6006c/ssv6006C_reg.h	16959;"	d
+DELTA_CD_HI	include/ssv6200_aux.h	4444;"	d
+DELTA_CD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3554;"	d
+DELTA_CD_I_MSK	include/ssv6200_aux.h	4442;"	d
+DELTA_CD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3552;"	d
+DELTA_CD_MSK	include/ssv6200_aux.h	4441;"	d
+DELTA_CD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3551;"	d
+DELTA_CD_SFT	include/ssv6200_aux.h	4443;"	d
+DELTA_CD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3553;"	d
+DELTA_CD_SZ	include/ssv6200_aux.h	4445;"	d
+DELTA_CD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3555;"	d
+DELTA_CTS_HI	include/ssv6200_aux.h	4429;"	d
+DELTA_CTS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3539;"	d
+DELTA_CTS_I_MSK	include/ssv6200_aux.h	4427;"	d
+DELTA_CTS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3537;"	d
+DELTA_CTS_MSK	include/ssv6200_aux.h	4426;"	d
+DELTA_CTS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3536;"	d
+DELTA_CTS_SFT	include/ssv6200_aux.h	4428;"	d
+DELTA_CTS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3538;"	d
+DELTA_CTS_SZ	include/ssv6200_aux.h	4430;"	d
+DELTA_CTS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3540;"	d
+DELTA_DSR_HI	include/ssv6200_aux.h	4434;"	d
+DELTA_DSR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3544;"	d
+DELTA_DSR_I_MSK	include/ssv6200_aux.h	4432;"	d
+DELTA_DSR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3542;"	d
+DELTA_DSR_MSK	include/ssv6200_aux.h	4431;"	d
+DELTA_DSR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3541;"	d
+DELTA_DSR_SFT	include/ssv6200_aux.h	4433;"	d
+DELTA_DSR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3543;"	d
+DELTA_DSR_SZ	include/ssv6200_aux.h	4435;"	d
+DELTA_DSR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3545;"	d
+DE_RTS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3494;"	d
+DE_RTS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3492;"	d
+DE_RTS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3491;"	d
+DE_RTS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3493;"	d
+DE_RTS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3495;"	d
+DIGI_TOP_POR_MASK_HI	include/ssv6200_aux.h	5914;"	d
+DIGI_TOP_POR_MASK_I_MSK	include/ssv6200_aux.h	5912;"	d
+DIGI_TOP_POR_MASK_MSK	include/ssv6200_aux.h	5911;"	d
+DIGI_TOP_POR_MASK_SFT	include/ssv6200_aux.h	5913;"	d
+DIGI_TOP_POR_MASK_SZ	include/ssv6200_aux.h	5915;"	d
+DIRECT_INT_MUX_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2674;"	d
+DIRECT_INT_MUX_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2672;"	d
+DIRECT_INT_MUX_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2671;"	d
+DIRECT_INT_MUX_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2673;"	d
+DIRECT_INT_MUX_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2675;"	d
+DIRECT_MODE_HI	include/ssv6200_aux.h	17659;"	d
+DIRECT_MODE_I_MSK	include/ssv6200_aux.h	17657;"	d
+DIRECT_MODE_MSK	include/ssv6200_aux.h	17656;"	d
+DIRECT_MODE_SFT	include/ssv6200_aux.h	17658;"	d
+DIRECT_MODE_SZ	include/ssv6200_aux.h	17660;"	d
+DIS_DEMAND_HI	include/ssv6200_aux.h	17669;"	d
+DIS_DEMAND_I_MSK	include/ssv6200_aux.h	17667;"	d
+DIS_DEMAND_MSK	include/ssv6200_aux.h	17666;"	d
+DIS_DEMAND_SFT	include/ssv6200_aux.h	17668;"	d
+DIS_DEMAND_SZ	include/ssv6200_aux.h	17670;"	d
+DLAB_HI	include/ssv6200_aux.h	4359;"	d
+DLAB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3464;"	d
+DLAB_I_MSK	include/ssv6200_aux.h	4357;"	d
+DLAB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3462;"	d
+DLAB_MSK	include/ssv6200_aux.h	4356;"	d
+DLAB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3461;"	d
+DLAB_SFT	include/ssv6200_aux.h	4358;"	d
+DLAB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3463;"	d
+DLAB_SZ	include/ssv6200_aux.h	4360;"	d
+DLAB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3465;"	d
+DMA_ADR_DST_HI	include/ssv6200_aux.h	5774;"	d
+DMA_ADR_DST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4194;"	d
+DMA_ADR_DST_I_MSK	include/ssv6200_aux.h	5772;"	d
+DMA_ADR_DST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4192;"	d
+DMA_ADR_DST_MSK	include/ssv6200_aux.h	5771;"	d
+DMA_ADR_DST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4191;"	d
+DMA_ADR_DST_SFT	include/ssv6200_aux.h	5773;"	d
+DMA_ADR_DST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4193;"	d
+DMA_ADR_DST_SZ	include/ssv6200_aux.h	5775;"	d
+DMA_ADR_DST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4195;"	d
+DMA_ADR_SRC_HI	include/ssv6200_aux.h	5769;"	d
+DMA_ADR_SRC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4189;"	d
+DMA_ADR_SRC_I_MSK	include/ssv6200_aux.h	5767;"	d
+DMA_ADR_SRC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4187;"	d
+DMA_ADR_SRC_MSK	include/ssv6200_aux.h	5766;"	d
+DMA_ADR_SRC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4186;"	d
+DMA_ADR_SRC_SFT	include/ssv6200_aux.h	5768;"	d
+DMA_ADR_SRC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4188;"	d
+DMA_ADR_SRC_SZ	include/ssv6200_aux.h	5770;"	d
+DMA_ADR_SRC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4190;"	d
+DMA_BADR_EN_HI	include/ssv6200_aux.h	5809;"	d
+DMA_BADR_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4229;"	d
+DMA_BADR_EN_I_MSK	include/ssv6200_aux.h	5807;"	d
+DMA_BADR_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4227;"	d
+DMA_BADR_EN_MSK	include/ssv6200_aux.h	5806;"	d
+DMA_BADR_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4226;"	d
+DMA_BADR_EN_SFT	include/ssv6200_aux.h	5808;"	d
+DMA_BADR_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4228;"	d
+DMA_BADR_EN_SZ	include/ssv6200_aux.h	5810;"	d
+DMA_BADR_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4230;"	d
+DMA_BUSY_HI	include/ssv6200_aux.h	5689;"	d
+DMA_BUSY_I_MSK	include/ssv6200_aux.h	5687;"	d
+DMA_BUSY_MSK	include/ssv6200_aux.h	5686;"	d
+DMA_BUSY_SFT	include/ssv6200_aux.h	5688;"	d
+DMA_BUSY_SZ	include/ssv6200_aux.h	5690;"	d
+DMA_CLK_EN_HI	include/ssv6200_aux.h	219;"	d
+DMA_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1169;"	d
+DMA_CLK_EN_I_MSK	include/ssv6200_aux.h	217;"	d
+DMA_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1167;"	d
+DMA_CLK_EN_MSK	include/ssv6200_aux.h	216;"	d
+DMA_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1166;"	d
+DMA_CLK_EN_SFT	include/ssv6200_aux.h	218;"	d
+DMA_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1168;"	d
+DMA_CLK_EN_SZ	include/ssv6200_aux.h	220;"	d
+DMA_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1170;"	d
+DMA_CONST_HI	include/ssv6200_aux.h	5834;"	d
+DMA_CONST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4254;"	d
+DMA_CONST_I_MSK	include/ssv6200_aux.h	5832;"	d
+DMA_CONST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4252;"	d
+DMA_CONST_MSK	include/ssv6200_aux.h	5831;"	d
+DMA_CONST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4251;"	d
+DMA_CONST_SFT	include/ssv6200_aux.h	5833;"	d
+DMA_CONST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4253;"	d
+DMA_CONST_SZ	include/ssv6200_aux.h	5835;"	d
+DMA_CONST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4255;"	d
+DMA_DST_INC_HI	include/ssv6200_aux.h	5794;"	d
+DMA_DST_INC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4214;"	d
+DMA_DST_INC_I_MSK	include/ssv6200_aux.h	5792;"	d
+DMA_DST_INC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4212;"	d
+DMA_DST_INC_MSK	include/ssv6200_aux.h	5791;"	d
+DMA_DST_INC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4211;"	d
+DMA_DST_INC_SFT	include/ssv6200_aux.h	5793;"	d
+DMA_DST_INC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4213;"	d
+DMA_DST_INC_SZ	include/ssv6200_aux.h	5795;"	d
+DMA_DST_INC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4215;"	d
+DMA_DST_SIZE_HI	include/ssv6200_aux.h	5789;"	d
+DMA_DST_SIZE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4209;"	d
+DMA_DST_SIZE_I_MSK	include/ssv6200_aux.h	5787;"	d
+DMA_DST_SIZE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4207;"	d
+DMA_DST_SIZE_MSK	include/ssv6200_aux.h	5786;"	d
+DMA_DST_SIZE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4206;"	d
+DMA_DST_SIZE_SFT	include/ssv6200_aux.h	5788;"	d
+DMA_DST_SIZE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4208;"	d
+DMA_DST_SIZE_SZ	include/ssv6200_aux.h	5790;"	d
+DMA_DST_SIZE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4210;"	d
+DMA_EN_HI	include/ssv6200_aux.h	5684;"	d
+DMA_EN_I_MSK	include/ssv6200_aux.h	5682;"	d
+DMA_EN_MSK	include/ssv6200_aux.h	5681;"	d
+DMA_EN_SFT	include/ssv6200_aux.h	5683;"	d
+DMA_EN_SZ	include/ssv6200_aux.h	5685;"	d
+DMA_FAST_FILL_HI	include/ssv6200_aux.h	5799;"	d
+DMA_FAST_FILL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4219;"	d
+DMA_FAST_FILL_I_MSK	include/ssv6200_aux.h	5797;"	d
+DMA_FAST_FILL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4217;"	d
+DMA_FAST_FILL_MSK	include/ssv6200_aux.h	5796;"	d
+DMA_FAST_FILL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4216;"	d
+DMA_FAST_FILL_SFT	include/ssv6200_aux.h	5798;"	d
+DMA_FAST_FILL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4218;"	d
+DMA_FAST_FILL_SZ	include/ssv6200_aux.h	5800;"	d
+DMA_FAST_FILL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4220;"	d
+DMA_FINISH_HI	include/ssv6200_aux.h	5829;"	d
+DMA_FINISH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4249;"	d
+DMA_FINISH_I_MSK	include/ssv6200_aux.h	5827;"	d
+DMA_FINISH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4247;"	d
+DMA_FINISH_MSK	include/ssv6200_aux.h	5826;"	d
+DMA_FINISH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4246;"	d
+DMA_FINISH_SFT	include/ssv6200_aux.h	5828;"	d
+DMA_FINISH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4248;"	d
+DMA_FINISH_SZ	include/ssv6200_aux.h	5830;"	d
+DMA_FINISH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4250;"	d
+DMA_INT_MASK_HI	include/ssv6200_aux.h	5819;"	d
+DMA_INT_MASK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4239;"	d
+DMA_INT_MASK_I_MSK	include/ssv6200_aux.h	5817;"	d
+DMA_INT_MASK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4237;"	d
+DMA_INT_MASK_MSK	include/ssv6200_aux.h	5816;"	d
+DMA_INT_MASK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4236;"	d
+DMA_INT_MASK_SFT	include/ssv6200_aux.h	5818;"	d
+DMA_INT_MASK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4238;"	d
+DMA_INT_MASK_SZ	include/ssv6200_aux.h	5820;"	d
+DMA_INT_MASK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4240;"	d
+DMA_LEN_HI	include/ssv6200_aux.h	5814;"	d
+DMA_LEN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4234;"	d
+DMA_LEN_I_MSK	include/ssv6200_aux.h	5812;"	d
+DMA_LEN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4232;"	d
+DMA_LEN_MSK	include/ssv6200_aux.h	5811;"	d
+DMA_LEN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4231;"	d
+DMA_LEN_SFT	include/ssv6200_aux.h	5813;"	d
+DMA_LEN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4233;"	d
+DMA_LEN_SZ	include/ssv6200_aux.h	5815;"	d
+DMA_LEN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4235;"	d
+DMA_MODE_HI	include/ssv6200_aux.h	4309;"	d
+DMA_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3414;"	d
+DMA_MODE_I_MSK	include/ssv6200_aux.h	4307;"	d
+DMA_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3412;"	d
+DMA_MODE_MSK	include/ssv6200_aux.h	4306;"	d
+DMA_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3411;"	d
+DMA_MODE_SFT	include/ssv6200_aux.h	4308;"	d
+DMA_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3413;"	d
+DMA_MODE_SZ	include/ssv6200_aux.h	4310;"	d
+DMA_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3415;"	d
+DMA_REG_BANK_SIZE	include/ssv6200_reg.h	86;"	d
+DMA_REG_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	103;"	d
+DMA_REG_BASE	include/ssv6200_reg.h	37;"	d
+DMA_REG_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	42;"	d
+DMA_RXEND_IE_HI	include/ssv6200_aux.h	4284;"	d
+DMA_RXEND_IE_I_MSK	include/ssv6200_aux.h	4282;"	d
+DMA_RXEND_IE_MSK	include/ssv6200_aux.h	4281;"	d
+DMA_RXEND_IE_SFT	include/ssv6200_aux.h	4283;"	d
+DMA_RXEND_IE_SZ	include/ssv6200_aux.h	4285;"	d
+DMA_SDIO_KICK_HI	include/ssv6200_aux.h	5804;"	d
+DMA_SDIO_KICK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4224;"	d
+DMA_SDIO_KICK_I_MSK	include/ssv6200_aux.h	5802;"	d
+DMA_SDIO_KICK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4222;"	d
+DMA_SDIO_KICK_MSK	include/ssv6200_aux.h	5801;"	d
+DMA_SDIO_KICK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4221;"	d
+DMA_SDIO_KICK_SFT	include/ssv6200_aux.h	5803;"	d
+DMA_SDIO_KICK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4223;"	d
+DMA_SDIO_KICK_SZ	include/ssv6200_aux.h	5805;"	d
+DMA_SDIO_KICK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4225;"	d
+DMA_SRC_INC_HI	include/ssv6200_aux.h	5784;"	d
+DMA_SRC_INC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4204;"	d
+DMA_SRC_INC_I_MSK	include/ssv6200_aux.h	5782;"	d
+DMA_SRC_INC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4202;"	d
+DMA_SRC_INC_MSK	include/ssv6200_aux.h	5781;"	d
+DMA_SRC_INC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4201;"	d
+DMA_SRC_INC_SFT	include/ssv6200_aux.h	5783;"	d
+DMA_SRC_INC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4203;"	d
+DMA_SRC_INC_SZ	include/ssv6200_aux.h	5785;"	d
+DMA_SRC_INC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4205;"	d
+DMA_SRC_SIZE_HI	include/ssv6200_aux.h	5779;"	d
+DMA_SRC_SIZE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4199;"	d
+DMA_SRC_SIZE_I_MSK	include/ssv6200_aux.h	5777;"	d
+DMA_SRC_SIZE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4197;"	d
+DMA_SRC_SIZE_MSK	include/ssv6200_aux.h	5776;"	d
+DMA_SRC_SIZE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4196;"	d
+DMA_SRC_SIZE_SFT	include/ssv6200_aux.h	5778;"	d
+DMA_SRC_SIZE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4198;"	d
+DMA_SRC_SIZE_SZ	include/ssv6200_aux.h	5780;"	d
+DMA_SRC_SIZE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4200;"	d
+DMA_STS_HI	include/ssv6200_aux.h	5824;"	d
+DMA_STS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4244;"	d
+DMA_STS_I_MSK	include/ssv6200_aux.h	5822;"	d
+DMA_STS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4242;"	d
+DMA_STS_MSK	include/ssv6200_aux.h	5821;"	d
+DMA_STS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4241;"	d
+DMA_STS_SFT	include/ssv6200_aux.h	5823;"	d
+DMA_STS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4243;"	d
+DMA_STS_SZ	include/ssv6200_aux.h	5825;"	d
+DMA_STS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4245;"	d
+DMA_SW_RST_HI	include/ssv6200_aux.h	49;"	d
+DMA_SW_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1004;"	d
+DMA_SW_RST_I_MSK	include/ssv6200_aux.h	47;"	d
+DMA_SW_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1002;"	d
+DMA_SW_RST_MSK	include/ssv6200_aux.h	46;"	d
+DMA_SW_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1001;"	d
+DMA_SW_RST_SFT	include/ssv6200_aux.h	48;"	d
+DMA_SW_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1003;"	d
+DMA_SW_RST_SZ	include/ssv6200_aux.h	50;"	d
+DMA_SW_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1005;"	d
+DMA_TXEND_IE_HI	include/ssv6200_aux.h	4289;"	d
+DMA_TXEND_IE_I_MSK	include/ssv6200_aux.h	4287;"	d
+DMA_TXEND_IE_MSK	include/ssv6200_aux.h	4286;"	d
+DMA_TXEND_IE_SFT	include/ssv6200_aux.h	4288;"	d
+DMA_TXEND_IE_SZ	include/ssv6200_aux.h	4290;"	d
+DMN_FLAG_CLR_HI	include/ssv6200_aux.h	17694;"	d
+DMN_FLAG_CLR_I_MSK	include/ssv6200_aux.h	17692;"	d
+DMN_FLAG_CLR_MSK	include/ssv6200_aux.h	17691;"	d
+DMN_FLAG_CLR_SFT	include/ssv6200_aux.h	17693;"	d
+DMN_FLAG_CLR_SZ	include/ssv6200_aux.h	17695;"	d
+DMN_FLAG_HI	include/ssv6200_aux.h	17949;"	d
+DMN_FLAG_I_MSK	include/ssv6200_aux.h	17947;"	d
+DMN_FLAG_MSK	include/ssv6200_aux.h	17946;"	d
+DMN_FLAG_SFT	include/ssv6200_aux.h	17948;"	d
+DMN_FLAG_SZ	include/ssv6200_aux.h	17950;"	d
+DMN_IDTBL_127_96_HI	include/ssv6200_aux.h	18079;"	d
+DMN_IDTBL_127_96_I_MSK	include/ssv6200_aux.h	18077;"	d
+DMN_IDTBL_127_96_MSK	include/ssv6200_aux.h	18076;"	d
+DMN_IDTBL_127_96_SFT	include/ssv6200_aux.h	18078;"	d
+DMN_IDTBL_127_96_SZ	include/ssv6200_aux.h	18080;"	d
+DMN_IDTBL_31_0_HI	include/ssv6200_aux.h	18064;"	d
+DMN_IDTBL_31_0_I_MSK	include/ssv6200_aux.h	18062;"	d
+DMN_IDTBL_31_0_MSK	include/ssv6200_aux.h	18061;"	d
+DMN_IDTBL_31_0_SFT	include/ssv6200_aux.h	18063;"	d
+DMN_IDTBL_31_0_SZ	include/ssv6200_aux.h	18065;"	d
+DMN_IDTBL_63_32_HI	include/ssv6200_aux.h	18069;"	d
+DMN_IDTBL_63_32_I_MSK	include/ssv6200_aux.h	18067;"	d
+DMN_IDTBL_63_32_MSK	include/ssv6200_aux.h	18066;"	d
+DMN_IDTBL_63_32_SFT	include/ssv6200_aux.h	18068;"	d
+DMN_IDTBL_63_32_SZ	include/ssv6200_aux.h	18070;"	d
+DMN_IDTBL_95_64_HI	include/ssv6200_aux.h	18074;"	d
+DMN_IDTBL_95_64_I_MSK	include/ssv6200_aux.h	18072;"	d
+DMN_IDTBL_95_64_MSK	include/ssv6200_aux.h	18071;"	d
+DMN_IDTBL_95_64_SFT	include/ssv6200_aux.h	18073;"	d
+DMN_IDTBL_95_64_SZ	include/ssv6200_aux.h	18075;"	d
+DMN_MCU_ADDR_HI	include/ssv6200_aux.h	18019;"	d
+DMN_MCU_ADDR_I_MSK	include/ssv6200_aux.h	18017;"	d
+DMN_MCU_ADDR_MSK	include/ssv6200_aux.h	18016;"	d
+DMN_MCU_ADDR_SFT	include/ssv6200_aux.h	18018;"	d
+DMN_MCU_ADDR_SZ	include/ssv6200_aux.h	18020;"	d
+DMN_MCU_FLAG_HI	include/ssv6200_aux.h	17999;"	d
+DMN_MCU_FLAG_I_MSK	include/ssv6200_aux.h	17997;"	d
+DMN_MCU_FLAG_MSK	include/ssv6200_aux.h	17996;"	d
+DMN_MCU_FLAG_SFT	include/ssv6200_aux.h	17998;"	d
+DMN_MCU_FLAG_SZ	include/ssv6200_aux.h	18000;"	d
+DMN_MCU_ID_HI	include/ssv6200_aux.h	18014;"	d
+DMN_MCU_ID_I_MSK	include/ssv6200_aux.h	18012;"	d
+DMN_MCU_ID_MSK	include/ssv6200_aux.h	18011;"	d
+DMN_MCU_ID_SFT	include/ssv6200_aux.h	18013;"	d
+DMN_MCU_ID_SZ	include/ssv6200_aux.h	18015;"	d
+DMN_MCU_INT_HI	include/ssv6200_aux.h	5034;"	d
+DMN_MCU_INT_I_MSK	include/ssv6200_aux.h	5032;"	d
+DMN_MCU_INT_MSK	include/ssv6200_aux.h	5031;"	d
+DMN_MCU_INT_SD_HI	include/ssv6200_aux.h	5379;"	d
+DMN_MCU_INT_SD_I_MSK	include/ssv6200_aux.h	5377;"	d
+DMN_MCU_INT_SD_MSK	include/ssv6200_aux.h	5376;"	d
+DMN_MCU_INT_SD_SFT	include/ssv6200_aux.h	5378;"	d
+DMN_MCU_INT_SD_SZ	include/ssv6200_aux.h	5380;"	d
+DMN_MCU_INT_SFT	include/ssv6200_aux.h	5033;"	d
+DMN_MCU_INT_SZ	include/ssv6200_aux.h	5035;"	d
+DMN_MCU_PORT_HI	include/ssv6200_aux.h	18009;"	d
+DMN_MCU_PORT_I_MSK	include/ssv6200_aux.h	18007;"	d
+DMN_MCU_PORT_MSK	include/ssv6200_aux.h	18006;"	d
+DMN_MCU_PORT_SFT	include/ssv6200_aux.h	18008;"	d
+DMN_MCU_PORT_SZ	include/ssv6200_aux.h	18010;"	d
+DMN_MCU_WR_HI	include/ssv6200_aux.h	18004;"	d
+DMN_MCU_WR_I_MSK	include/ssv6200_aux.h	18002;"	d
+DMN_MCU_WR_MSK	include/ssv6200_aux.h	18001;"	d
+DMN_MCU_WR_SFT	include/ssv6200_aux.h	18003;"	d
+DMN_MCU_WR_SZ	include/ssv6200_aux.h	18005;"	d
+DMN_NHIT_ADDR_HI	include/ssv6200_aux.h	17969;"	d
+DMN_NHIT_ADDR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34594;"	d
+DMN_NHIT_ADDR_I_MSK	include/ssv6200_aux.h	17967;"	d
+DMN_NHIT_ADDR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34592;"	d
+DMN_NHIT_ADDR_MSK	include/ssv6200_aux.h	17966;"	d
+DMN_NHIT_ADDR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34591;"	d
+DMN_NHIT_ADDR_SFT	include/ssv6200_aux.h	17968;"	d
+DMN_NHIT_ADDR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34593;"	d
+DMN_NHIT_ADDR_SZ	include/ssv6200_aux.h	17970;"	d
+DMN_NHIT_ADDR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34595;"	d
+DMN_NHIT_ID_HI	include/ssv6200_aux.h	17964;"	d
+DMN_NHIT_ID_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34589;"	d
+DMN_NHIT_ID_I_MSK	include/ssv6200_aux.h	17962;"	d
+DMN_NHIT_ID_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34587;"	d
+DMN_NHIT_ID_MSK	include/ssv6200_aux.h	17961;"	d
+DMN_NHIT_ID_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34586;"	d
+DMN_NHIT_ID_SFT	include/ssv6200_aux.h	17963;"	d
+DMN_NHIT_ID_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34588;"	d
+DMN_NHIT_ID_SZ	include/ssv6200_aux.h	17965;"	d
+DMN_NHIT_ID_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34590;"	d
+DMN_NOHIT_CLR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34574;"	d
+DMN_NOHIT_CLR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34572;"	d
+DMN_NOHIT_CLR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34571;"	d
+DMN_NOHIT_CLR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34573;"	d
+DMN_NOHIT_CLR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34575;"	d
+DMN_NOHIT_FLAG_HI	include/ssv6200_aux.h	17944;"	d
+DMN_NOHIT_FLAG_I_MSK	include/ssv6200_aux.h	17942;"	d
+DMN_NOHIT_FLAG_MSK	include/ssv6200_aux.h	17941;"	d
+DMN_NOHIT_FLAG_SFT	include/ssv6200_aux.h	17943;"	d
+DMN_NOHIT_FLAG_SZ	include/ssv6200_aux.h	17945;"	d
+DMN_NOHIT_INT_HI	include/ssv6200_aux.h	4999;"	d
+DMN_NOHIT_INT_I_MSK	include/ssv6200_aux.h	4997;"	d
+DMN_NOHIT_INT_MSK	include/ssv6200_aux.h	4996;"	d
+DMN_NOHIT_INT_SD_HI	include/ssv6200_aux.h	5344;"	d
+DMN_NOHIT_INT_SD_I_MSK	include/ssv6200_aux.h	5342;"	d
+DMN_NOHIT_INT_SD_MSK	include/ssv6200_aux.h	5341;"	d
+DMN_NOHIT_INT_SD_SFT	include/ssv6200_aux.h	5343;"	d
+DMN_NOHIT_INT_SD_SZ	include/ssv6200_aux.h	5345;"	d
+DMN_NOHIT_INT_SFT	include/ssv6200_aux.h	4998;"	d
+DMN_NOHIT_INT_SZ	include/ssv6200_aux.h	5000;"	d
+DMN_NOHIT_MCU_HI	include/ssv6200_aux.h	17994;"	d
+DMN_NOHIT_MCU_I_MSK	include/ssv6200_aux.h	17992;"	d
+DMN_NOHIT_MCU_MSK	include/ssv6200_aux.h	17991;"	d
+DMN_NOHIT_MCU_SFT	include/ssv6200_aux.h	17993;"	d
+DMN_NOHIT_MCU_SZ	include/ssv6200_aux.h	17995;"	d
+DMN_NOHIT_STS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34569;"	d
+DMN_NOHIT_STS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34567;"	d
+DMN_NOHIT_STS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34566;"	d
+DMN_NOHIT_STS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34568;"	d
+DMN_NOHIT_STS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34570;"	d
+DMN_PORT_HI	include/ssv6200_aux.h	17959;"	d
+DMN_PORT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34584;"	d
+DMN_PORT_I_MSK	include/ssv6200_aux.h	17957;"	d
+DMN_PORT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34582;"	d
+DMN_PORT_MSK	include/ssv6200_aux.h	17956;"	d
+DMN_PORT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34581;"	d
+DMN_PORT_SFT	include/ssv6200_aux.h	17958;"	d
+DMN_PORT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34583;"	d
+DMN_PORT_SZ	include/ssv6200_aux.h	17960;"	d
+DMN_PORT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34585;"	d
+DMN_R_PASS_HI	include/ssv6200_aux.h	17864;"	d
+DMN_R_PASS_I_MSK	include/ssv6200_aux.h	17862;"	d
+DMN_R_PASS_MSK	include/ssv6200_aux.h	17861;"	d
+DMN_R_PASS_SFT	include/ssv6200_aux.h	17863;"	d
+DMN_R_PASS_SZ	include/ssv6200_aux.h	17865;"	d
+DMN_WR_HI	include/ssv6200_aux.h	17954;"	d
+DMN_WR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34579;"	d
+DMN_WR_I_MSK	include/ssv6200_aux.h	17952;"	d
+DMN_WR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34577;"	d
+DMN_WR_MSK	include/ssv6200_aux.h	17951;"	d
+DMN_WR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34576;"	d
+DMN_WR_SFT	include/ssv6200_aux.h	17953;"	d
+DMN_WR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34578;"	d
+DMN_WR_SZ	include/ssv6200_aux.h	17955;"	d
+DMN_WR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34580;"	d
+DOT11RTSTHRESHOLD_HI	include/ssv6200_aux.h	6149;"	d
+DOT11RTSTHRESHOLD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5219;"	d
+DOT11RTSTHRESHOLD_I_MSK	include/ssv6200_aux.h	6147;"	d
+DOT11RTSTHRESHOLD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5217;"	d
+DOT11RTSTHRESHOLD_MSK	include/ssv6200_aux.h	6146;"	d
+DOT11RTSTHRESHOLD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5216;"	d
+DOT11RTSTHRESHOLD_SFT	include/ssv6200_aux.h	6148;"	d
+DOT11RTSTHRESHOLD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5218;"	d
+DOT11RTSTHRESHOLD_SZ	include/ssv6200_aux.h	6150;"	d
+DOT11RTSTHRESHOLD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5220;"	d
+DOT11_G_RATE_IDX_OFFSET	smac/hal/ssv6006c/ssv6006_mac.h	68;"	d
+DOUBLE_ALLOCATE_ERROR_HI	include/ssv6200_aux.h	3504;"	d
+DOUBLE_ALLOCATE_ERROR_I_MSK	include/ssv6200_aux.h	3502;"	d
+DOUBLE_ALLOCATE_ERROR_MSK	include/ssv6200_aux.h	3501;"	d
+DOUBLE_ALLOCATE_ERROR_SFT	include/ssv6200_aux.h	3503;"	d
+DOUBLE_ALLOCATE_ERROR_SZ	include/ssv6200_aux.h	3505;"	d
+DOUBLE_ALLOC_ERR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5319;"	d
+DOUBLE_ALLOC_ERR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5317;"	d
+DOUBLE_ALLOC_ERR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5316;"	d
+DOUBLE_ALLOC_ERR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5318;"	d
+DOUBLE_ALLOC_ERR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5320;"	d
+DOUBLE_RLS_ID_HI	include/ssv6200_aux.h	12709;"	d
+DOUBLE_RLS_ID_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34234;"	d
+DOUBLE_RLS_ID_I_MSK	include/ssv6200_aux.h	12707;"	d
+DOUBLE_RLS_ID_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34232;"	d
+DOUBLE_RLS_ID_MSK	include/ssv6200_aux.h	12706;"	d
+DOUBLE_RLS_ID_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34231;"	d
+DOUBLE_RLS_ID_SFT	include/ssv6200_aux.h	12708;"	d
+DOUBLE_RLS_ID_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34233;"	d
+DOUBLE_RLS_ID_SZ	include/ssv6200_aux.h	12710;"	d
+DOUBLE_RLS_ID_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34235;"	d
+DOUBLE_RLS_INT_EN_HI	include/ssv6200_aux.h	12699;"	d
+DOUBLE_RLS_INT_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34224;"	d
+DOUBLE_RLS_INT_EN_I_MSK	include/ssv6200_aux.h	12697;"	d
+DOUBLE_RLS_INT_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34222;"	d
+DOUBLE_RLS_INT_EN_MSK	include/ssv6200_aux.h	12696;"	d
+DOUBLE_RLS_INT_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34221;"	d
+DOUBLE_RLS_INT_EN_SFT	include/ssv6200_aux.h	12698;"	d
+DOUBLE_RLS_INT_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34223;"	d
+DOUBLE_RLS_INT_EN_SZ	include/ssv6200_aux.h	12700;"	d
+DOUBLE_RLS_INT_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34225;"	d
+DPD_SET_TXSCALE_GET_RESULT	smac/hal/ssv6006c/turismo_common.h	3089;"	d
+DPLL_CKT_REGISTER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23854;"	d
+DPLL_CKT_REGISTER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23852;"	d
+DPLL_CKT_REGISTER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23851;"	d
+DPLL_CKT_REGISTER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23853;"	d
+DPLL_CKT_REGISTER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23855;"	d
+DPLL_FB_DIVISION__REGISTERS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23859;"	d
+DPLL_FB_DIVISION__REGISTERS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23857;"	d
+DPLL_FB_DIVISION__REGISTERS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23856;"	d
+DPLL_FB_DIVISION__REGISTERS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23858;"	d
+DPLL_FB_DIVISION__REGISTERS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23860;"	d
+DPLL_TOP_REGISTER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23849;"	d
+DPLL_TOP_REGISTER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23847;"	d
+DPLL_TOP_REGISTER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23846;"	d
+DPLL_TOP_REGISTER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23848;"	d
+DPLL_TOP_REGISTER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23850;"	d
+DRVPATH	config.mak	/^DRVPATH=kernel\/drivers\/net\/wireless\/ssv6200$/;"	m
+DSR_HI	include/ssv6200_aux.h	4454;"	d
+DSR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3564;"	d
+DSR_I_MSK	include/ssv6200_aux.h	4452;"	d
+DSR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3562;"	d
+DSR_MSK	include/ssv6200_aux.h	4451;"	d
+DSR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3561;"	d
+DSR_SFT	include/ssv6200_aux.h	4453;"	d
+DSR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3563;"	d
+DSR_SZ	include/ssv6200_aux.h	4455;"	d
+DSR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3565;"	d
+DTR_HI	include/ssv6200_aux.h	4364;"	d
+DTR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3469;"	d
+DTR_I_MSK	include/ssv6200_aux.h	4362;"	d
+DTR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3467;"	d
+DTR_MSK	include/ssv6200_aux.h	4361;"	d
+DTR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3466;"	d
+DTR_SFT	include/ssv6200_aux.h	4363;"	d
+DTR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3468;"	d
+DTR_SZ	include/ssv6200_aux.h	4365;"	d
+DTR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3470;"	d
+DUAL_ANT_EN_HI	include/ssv6200_aux.h	9259;"	d
+DUAL_ANT_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9049;"	d
+DUAL_ANT_EN_I_MSK	include/ssv6200_aux.h	9257;"	d
+DUAL_ANT_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9047;"	d
+DUAL_ANT_EN_MSK	include/ssv6200_aux.h	9256;"	d
+DUAL_ANT_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9046;"	d
+DUAL_ANT_EN_SFT	include/ssv6200_aux.h	9258;"	d
+DUAL_ANT_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9048;"	d
+DUAL_ANT_EN_SZ	include/ssv6200_aux.h	9260;"	d
+DUAL_ANT_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9050;"	d
+DUAL_BAND_ID	smac/hal/ssv6006c/turismo_common.h	2816;"	d
+DUMY_DLY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4034;"	d
+DUMY_DLY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4032;"	d
+DUMY_DLY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4031;"	d
+DUMY_DLY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4033;"	d
+DUMY_DLY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4035;"	d
+DUP_FLT_HI	include/ssv6200_aux.h	9149;"	d
+DUP_FLT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8904;"	d
+DUP_FLT_I_MSK	include/ssv6200_aux.h	9147;"	d
+DUP_FLT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8902;"	d
+DUP_FLT_MSK	include/ssv6200_aux.h	9146;"	d
+DUP_FLT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8901;"	d
+DUP_FLT_SFT	include/ssv6200_aux.h	9148;"	d
+DUP_FLT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8903;"	d
+DUP_FLT_SZ	include/ssv6200_aux.h	9150;"	d
+DUP_FLT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8905;"	d
+DURATION_HI	include/ssv6200_aux.h	6469;"	d
+DURATION_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5714;"	d
+DURATION_I_MSK	include/ssv6200_aux.h	6467;"	d
+DURATION_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5712;"	d
+DURATION_MSK	include/ssv6200_aux.h	6466;"	d
+DURATION_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5711;"	d
+DURATION_SFT	include/ssv6200_aux.h	6468;"	d
+DURATION_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5713;"	d
+DURATION_SZ	include/ssv6200_aux.h	6470;"	d
+DURATION_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5715;"	d
+EARLY_SAMPLE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6019;"	d
+EARLY_SAMPLE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6017;"	d
+EARLY_SAMPLE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6016;"	d
+EARLY_SAMPLE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6018;"	d
+EARLY_SAMPLE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6020;"	d
+EDCA0_FFO_CNT_HI	include/ssv6200_aux.h	12834;"	d
+EDCA0_FFO_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34359;"	d
+EDCA0_FFO_CNT_I_MSK	include/ssv6200_aux.h	12832;"	d
+EDCA0_FFO_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34357;"	d
+EDCA0_FFO_CNT_MSK	include/ssv6200_aux.h	12831;"	d
+EDCA0_FFO_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34356;"	d
+EDCA0_FFO_CNT_SFT	include/ssv6200_aux.h	12833;"	d
+EDCA0_FFO_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34358;"	d
+EDCA0_FFO_CNT_SZ	include/ssv6200_aux.h	12835;"	d
+EDCA0_FFO_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34360;"	d
+EDCA0_LOWTHOLD_INT_HI	include/ssv6200_aux.h	4124;"	d
+EDCA0_LOWTHOLD_INT_I_MSK	include/ssv6200_aux.h	4122;"	d
+EDCA0_LOWTHOLD_INT_MSK	include/ssv6200_aux.h	4121;"	d
+EDCA0_LOWTHOLD_INT_SFT	include/ssv6200_aux.h	4123;"	d
+EDCA0_LOWTHOLD_INT_SZ	include/ssv6200_aux.h	4125;"	d
+EDCA0_LOW_THR_INT_MASK_HI	include/ssv6200_aux.h	3054;"	d
+EDCA0_LOW_THR_INT_MASK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2524;"	d
+EDCA0_LOW_THR_INT_MASK_I_MSK	include/ssv6200_aux.h	3052;"	d
+EDCA0_LOW_THR_INT_MASK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2522;"	d
+EDCA0_LOW_THR_INT_MASK_MSK	include/ssv6200_aux.h	3051;"	d
+EDCA0_LOW_THR_INT_MASK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2521;"	d
+EDCA0_LOW_THR_INT_MASK_SFT	include/ssv6200_aux.h	3053;"	d
+EDCA0_LOW_THR_INT_MASK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2523;"	d
+EDCA0_LOW_THR_INT_MASK_SZ	include/ssv6200_aux.h	3055;"	d
+EDCA0_LOW_THR_INT_MASK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2525;"	d
+EDCA0_LOW_THR_INT_STS_HI	include/ssv6200_aux.h	3094;"	d
+EDCA0_LOW_THR_INT_STS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2564;"	d
+EDCA0_LOW_THR_INT_STS_I_MSK	include/ssv6200_aux.h	3092;"	d
+EDCA0_LOW_THR_INT_STS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2562;"	d
+EDCA0_LOW_THR_INT_STS_MSK	include/ssv6200_aux.h	3091;"	d
+EDCA0_LOW_THR_INT_STS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2561;"	d
+EDCA0_LOW_THR_INT_STS_SFT	include/ssv6200_aux.h	3093;"	d
+EDCA0_LOW_THR_INT_STS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2563;"	d
+EDCA0_LOW_THR_INT_STS_SZ	include/ssv6200_aux.h	3095;"	d
+EDCA0_LOW_THR_INT_STS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2565;"	d
+EDCA0_UPTHOLD_INT_HI	include/ssv6200_aux.h	3554;"	d
+EDCA0_UPTHOLD_INT_I_MSK	include/ssv6200_aux.h	3552;"	d
+EDCA0_UPTHOLD_INT_MSK	include/ssv6200_aux.h	3551;"	d
+EDCA0_UPTHOLD_INT_SFT	include/ssv6200_aux.h	3553;"	d
+EDCA0_UPTHOLD_INT_SZ	include/ssv6200_aux.h	3555;"	d
+EDCA1_FFO_CNT2_HI	include/ssv6200_aux.h	12909;"	d
+EDCA1_FFO_CNT2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34439;"	d
+EDCA1_FFO_CNT2_I_MSK	include/ssv6200_aux.h	12907;"	d
+EDCA1_FFO_CNT2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34437;"	d
+EDCA1_FFO_CNT2_MSK	include/ssv6200_aux.h	12906;"	d
+EDCA1_FFO_CNT2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34436;"	d
+EDCA1_FFO_CNT2_SFT	include/ssv6200_aux.h	12908;"	d
+EDCA1_FFO_CNT2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34438;"	d
+EDCA1_FFO_CNT2_SZ	include/ssv6200_aux.h	12910;"	d
+EDCA1_FFO_CNT2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34440;"	d
+EDCA1_FFO_CNT_3_0_HI	include/ssv6200_aux.h	12839;"	d
+EDCA1_FFO_CNT_3_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34364;"	d
+EDCA1_FFO_CNT_3_0_I_MSK	include/ssv6200_aux.h	12837;"	d
+EDCA1_FFO_CNT_3_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34362;"	d
+EDCA1_FFO_CNT_3_0_MSK	include/ssv6200_aux.h	12836;"	d
+EDCA1_FFO_CNT_3_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34361;"	d
+EDCA1_FFO_CNT_3_0_SFT	include/ssv6200_aux.h	12838;"	d
+EDCA1_FFO_CNT_3_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34363;"	d
+EDCA1_FFO_CNT_3_0_SZ	include/ssv6200_aux.h	12840;"	d
+EDCA1_FFO_CNT_3_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34365;"	d
+EDCA1_LOWTHOLD_INT_HI	include/ssv6200_aux.h	4129;"	d
+EDCA1_LOWTHOLD_INT_I_MSK	include/ssv6200_aux.h	4127;"	d
+EDCA1_LOWTHOLD_INT_MSK	include/ssv6200_aux.h	4126;"	d
+EDCA1_LOWTHOLD_INT_SFT	include/ssv6200_aux.h	4128;"	d
+EDCA1_LOWTHOLD_INT_SZ	include/ssv6200_aux.h	4130;"	d
+EDCA1_LOW_THR_INT_MASK_HI	include/ssv6200_aux.h	3059;"	d
+EDCA1_LOW_THR_INT_MASK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2529;"	d
+EDCA1_LOW_THR_INT_MASK_I_MSK	include/ssv6200_aux.h	3057;"	d
+EDCA1_LOW_THR_INT_MASK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2527;"	d
+EDCA1_LOW_THR_INT_MASK_MSK	include/ssv6200_aux.h	3056;"	d
+EDCA1_LOW_THR_INT_MASK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2526;"	d
+EDCA1_LOW_THR_INT_MASK_SFT	include/ssv6200_aux.h	3058;"	d
+EDCA1_LOW_THR_INT_MASK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2528;"	d
+EDCA1_LOW_THR_INT_MASK_SZ	include/ssv6200_aux.h	3060;"	d
+EDCA1_LOW_THR_INT_MASK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2530;"	d
+EDCA1_LOW_THR_INT_STS_HI	include/ssv6200_aux.h	3099;"	d
+EDCA1_LOW_THR_INT_STS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2569;"	d
+EDCA1_LOW_THR_INT_STS_I_MSK	include/ssv6200_aux.h	3097;"	d
+EDCA1_LOW_THR_INT_STS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2567;"	d
+EDCA1_LOW_THR_INT_STS_MSK	include/ssv6200_aux.h	3096;"	d
+EDCA1_LOW_THR_INT_STS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2566;"	d
+EDCA1_LOW_THR_INT_STS_SFT	include/ssv6200_aux.h	3098;"	d
+EDCA1_LOW_THR_INT_STS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2568;"	d
+EDCA1_LOW_THR_INT_STS_SZ	include/ssv6200_aux.h	3100;"	d
+EDCA1_LOW_THR_INT_STS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2570;"	d
+EDCA1_UPTHOLD_INT_HI	include/ssv6200_aux.h	3559;"	d
+EDCA1_UPTHOLD_INT_I_MSK	include/ssv6200_aux.h	3557;"	d
+EDCA1_UPTHOLD_INT_MSK	include/ssv6200_aux.h	3556;"	d
+EDCA1_UPTHOLD_INT_SFT	include/ssv6200_aux.h	3558;"	d
+EDCA1_UPTHOLD_INT_SZ	include/ssv6200_aux.h	3560;"	d
+EDCA2_FFO_CNT2_HI	include/ssv6200_aux.h	12929;"	d
+EDCA2_FFO_CNT2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34464;"	d
+EDCA2_FFO_CNT2_I_MSK	include/ssv6200_aux.h	12927;"	d
+EDCA2_FFO_CNT2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34462;"	d
+EDCA2_FFO_CNT2_MSK	include/ssv6200_aux.h	12926;"	d
+EDCA2_FFO_CNT2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34461;"	d
+EDCA2_FFO_CNT2_SFT	include/ssv6200_aux.h	12928;"	d
+EDCA2_FFO_CNT2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34463;"	d
+EDCA2_FFO_CNT2_SZ	include/ssv6200_aux.h	12930;"	d
+EDCA2_FFO_CNT2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34465;"	d
+EDCA2_FFO_CNT_HI	include/ssv6200_aux.h	12844;"	d
+EDCA2_FFO_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34369;"	d
+EDCA2_FFO_CNT_I_MSK	include/ssv6200_aux.h	12842;"	d
+EDCA2_FFO_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34367;"	d
+EDCA2_FFO_CNT_MSK	include/ssv6200_aux.h	12841;"	d
+EDCA2_FFO_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34366;"	d
+EDCA2_FFO_CNT_SFT	include/ssv6200_aux.h	12843;"	d
+EDCA2_FFO_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34368;"	d
+EDCA2_FFO_CNT_SZ	include/ssv6200_aux.h	12845;"	d
+EDCA2_FFO_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34370;"	d
+EDCA2_LOWTHOLD_INT_HI	include/ssv6200_aux.h	4134;"	d
+EDCA2_LOWTHOLD_INT_I_MSK	include/ssv6200_aux.h	4132;"	d
+EDCA2_LOWTHOLD_INT_MSK	include/ssv6200_aux.h	4131;"	d
+EDCA2_LOWTHOLD_INT_SFT	include/ssv6200_aux.h	4133;"	d
+EDCA2_LOWTHOLD_INT_SZ	include/ssv6200_aux.h	4135;"	d
+EDCA2_LOW_THR_INT_MASK_HI	include/ssv6200_aux.h	3064;"	d
+EDCA2_LOW_THR_INT_MASK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2534;"	d
+EDCA2_LOW_THR_INT_MASK_I_MSK	include/ssv6200_aux.h	3062;"	d
+EDCA2_LOW_THR_INT_MASK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2532;"	d
+EDCA2_LOW_THR_INT_MASK_MSK	include/ssv6200_aux.h	3061;"	d
+EDCA2_LOW_THR_INT_MASK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2531;"	d
+EDCA2_LOW_THR_INT_MASK_SFT	include/ssv6200_aux.h	3063;"	d
+EDCA2_LOW_THR_INT_MASK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2533;"	d
+EDCA2_LOW_THR_INT_MASK_SZ	include/ssv6200_aux.h	3065;"	d
+EDCA2_LOW_THR_INT_MASK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2535;"	d
+EDCA2_LOW_THR_INT_STS_HI	include/ssv6200_aux.h	3104;"	d
+EDCA2_LOW_THR_INT_STS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2574;"	d
+EDCA2_LOW_THR_INT_STS_I_MSK	include/ssv6200_aux.h	3102;"	d
+EDCA2_LOW_THR_INT_STS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2572;"	d
+EDCA2_LOW_THR_INT_STS_MSK	include/ssv6200_aux.h	3101;"	d
+EDCA2_LOW_THR_INT_STS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2571;"	d
+EDCA2_LOW_THR_INT_STS_SFT	include/ssv6200_aux.h	3103;"	d
+EDCA2_LOW_THR_INT_STS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2573;"	d
+EDCA2_LOW_THR_INT_STS_SZ	include/ssv6200_aux.h	3105;"	d
+EDCA2_LOW_THR_INT_STS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2575;"	d
+EDCA2_UPTHOLD_INT_HI	include/ssv6200_aux.h	3564;"	d
+EDCA2_UPTHOLD_INT_I_MSK	include/ssv6200_aux.h	3562;"	d
+EDCA2_UPTHOLD_INT_MSK	include/ssv6200_aux.h	3561;"	d
+EDCA2_UPTHOLD_INT_SFT	include/ssv6200_aux.h	3563;"	d
+EDCA2_UPTHOLD_INT_SZ	include/ssv6200_aux.h	3565;"	d
+EDCA3_FFO_CNT2_HI	include/ssv6200_aux.h	12934;"	d
+EDCA3_FFO_CNT2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34469;"	d
+EDCA3_FFO_CNT2_I_MSK	include/ssv6200_aux.h	12932;"	d
+EDCA3_FFO_CNT2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34467;"	d
+EDCA3_FFO_CNT2_MSK	include/ssv6200_aux.h	12931;"	d
+EDCA3_FFO_CNT2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34466;"	d
+EDCA3_FFO_CNT2_SFT	include/ssv6200_aux.h	12933;"	d
+EDCA3_FFO_CNT2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34468;"	d
+EDCA3_FFO_CNT2_SZ	include/ssv6200_aux.h	12935;"	d
+EDCA3_FFO_CNT2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34470;"	d
+EDCA3_FFO_CNT_HI	include/ssv6200_aux.h	12849;"	d
+EDCA3_FFO_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34374;"	d
+EDCA3_FFO_CNT_I_MSK	include/ssv6200_aux.h	12847;"	d
+EDCA3_FFO_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34372;"	d
+EDCA3_FFO_CNT_MSK	include/ssv6200_aux.h	12846;"	d
+EDCA3_FFO_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34371;"	d
+EDCA3_FFO_CNT_SFT	include/ssv6200_aux.h	12848;"	d
+EDCA3_FFO_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34373;"	d
+EDCA3_FFO_CNT_SZ	include/ssv6200_aux.h	12850;"	d
+EDCA3_FFO_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34375;"	d
+EDCA3_LOWTHOLD_INT_HI	include/ssv6200_aux.h	4139;"	d
+EDCA3_LOWTHOLD_INT_I_MSK	include/ssv6200_aux.h	4137;"	d
+EDCA3_LOWTHOLD_INT_MSK	include/ssv6200_aux.h	4136;"	d
+EDCA3_LOWTHOLD_INT_SFT	include/ssv6200_aux.h	4138;"	d
+EDCA3_LOWTHOLD_INT_SZ	include/ssv6200_aux.h	4140;"	d
+EDCA3_LOW_THR_INT_MASK_HI	include/ssv6200_aux.h	3069;"	d
+EDCA3_LOW_THR_INT_MASK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2539;"	d
+EDCA3_LOW_THR_INT_MASK_I_MSK	include/ssv6200_aux.h	3067;"	d
+EDCA3_LOW_THR_INT_MASK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2537;"	d
+EDCA3_LOW_THR_INT_MASK_MSK	include/ssv6200_aux.h	3066;"	d
+EDCA3_LOW_THR_INT_MASK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2536;"	d
+EDCA3_LOW_THR_INT_MASK_SFT	include/ssv6200_aux.h	3068;"	d
+EDCA3_LOW_THR_INT_MASK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2538;"	d
+EDCA3_LOW_THR_INT_MASK_SZ	include/ssv6200_aux.h	3070;"	d
+EDCA3_LOW_THR_INT_MASK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2540;"	d
+EDCA3_LOW_THR_INT_STS_HI	include/ssv6200_aux.h	3109;"	d
+EDCA3_LOW_THR_INT_STS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2579;"	d
+EDCA3_LOW_THR_INT_STS_I_MSK	include/ssv6200_aux.h	3107;"	d
+EDCA3_LOW_THR_INT_STS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2577;"	d
+EDCA3_LOW_THR_INT_STS_MSK	include/ssv6200_aux.h	3106;"	d
+EDCA3_LOW_THR_INT_STS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2576;"	d
+EDCA3_LOW_THR_INT_STS_SFT	include/ssv6200_aux.h	3108;"	d
+EDCA3_LOW_THR_INT_STS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2578;"	d
+EDCA3_LOW_THR_INT_STS_SZ	include/ssv6200_aux.h	3110;"	d
+EDCA3_LOW_THR_INT_STS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2580;"	d
+EDCA3_UPTHOLD_INT_HI	include/ssv6200_aux.h	3569;"	d
+EDCA3_UPTHOLD_INT_I_MSK	include/ssv6200_aux.h	3567;"	d
+EDCA3_UPTHOLD_INT_MSK	include/ssv6200_aux.h	3566;"	d
+EDCA3_UPTHOLD_INT_SFT	include/ssv6200_aux.h	3568;"	d
+EDCA3_UPTHOLD_INT_SZ	include/ssv6200_aux.h	3570;"	d
+EDCA4_FFO_CNT2_HI	include/ssv6200_aux.h	12914;"	d
+EDCA4_FFO_CNT2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34444;"	d
+EDCA4_FFO_CNT2_I_MSK	include/ssv6200_aux.h	12912;"	d
+EDCA4_FFO_CNT2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34442;"	d
+EDCA4_FFO_CNT2_MSK	include/ssv6200_aux.h	12911;"	d
+EDCA4_FFO_CNT2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34441;"	d
+EDCA4_FFO_CNT2_SFT	include/ssv6200_aux.h	12913;"	d
+EDCA4_FFO_CNT2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34443;"	d
+EDCA4_FFO_CNT2_SZ	include/ssv6200_aux.h	12915;"	d
+EDCA4_FFO_CNT2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34445;"	d
+EDCA4_FFO_CNT_HI	include/ssv6200_aux.h	12894;"	d
+EDCA4_FFO_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34419;"	d
+EDCA4_FFO_CNT_I_MSK	include/ssv6200_aux.h	12892;"	d
+EDCA4_FFO_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34417;"	d
+EDCA4_FFO_CNT_MSK	include/ssv6200_aux.h	12891;"	d
+EDCA4_FFO_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34416;"	d
+EDCA4_FFO_CNT_SFT	include/ssv6200_aux.h	12893;"	d
+EDCA4_FFO_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34418;"	d
+EDCA4_FFO_CNT_SZ	include/ssv6200_aux.h	12895;"	d
+EDCA4_FFO_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34420;"	d
+EDCA4_LOW_THR_INT_MASK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2514;"	d
+EDCA4_LOW_THR_INT_MASK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2512;"	d
+EDCA4_LOW_THR_INT_MASK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2511;"	d
+EDCA4_LOW_THR_INT_MASK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2513;"	d
+EDCA4_LOW_THR_INT_MASK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2515;"	d
+EDCA4_LOW_THR_INT_STS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2554;"	d
+EDCA4_LOW_THR_INT_STS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2552;"	d
+EDCA4_LOW_THR_INT_STS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2551;"	d
+EDCA4_LOW_THR_INT_STS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2553;"	d
+EDCA4_LOW_THR_INT_STS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2555;"	d
+EDCA5_FFO_CNT2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34449;"	d
+EDCA5_FFO_CNT2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34447;"	d
+EDCA5_FFO_CNT2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34446;"	d
+EDCA5_FFO_CNT2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34448;"	d
+EDCA5_FFO_CNT2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34450;"	d
+EDCA5_FFO_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34424;"	d
+EDCA5_FFO_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34422;"	d
+EDCA5_FFO_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34421;"	d
+EDCA5_FFO_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34423;"	d
+EDCA5_FFO_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34425;"	d
+EDLM_SRAM_ERRCK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1454;"	d
+EDLM_SRAM_ERRCK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1452;"	d
+EDLM_SRAM_ERRCK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1451;"	d
+EDLM_SRAM_ERRCK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1453;"	d
+EDLM_SRAM_ERRCK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1455;"	d
+EDLM_SRAM_ERR_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1479;"	d
+EDLM_SRAM_ERR_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1477;"	d
+EDLM_SRAM_ERR_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1476;"	d
+EDLM_SRAM_ERR_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1478;"	d
+EDLM_SRAM_ERR_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1480;"	d
+EFS_BYTE_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5794;"	d
+EFS_BYTE_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5792;"	d
+EFS_BYTE_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5791;"	d
+EFS_BYTE_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5793;"	d
+EFS_BYTE_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5795;"	d
+EFS_BYTE_10_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5844;"	d
+EFS_BYTE_10_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5842;"	d
+EFS_BYTE_10_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5841;"	d
+EFS_BYTE_10_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5843;"	d
+EFS_BYTE_10_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5845;"	d
+EFS_BYTE_11_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5849;"	d
+EFS_BYTE_11_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5847;"	d
+EFS_BYTE_11_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5846;"	d
+EFS_BYTE_11_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5848;"	d
+EFS_BYTE_11_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5850;"	d
+EFS_BYTE_12_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5854;"	d
+EFS_BYTE_12_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5852;"	d
+EFS_BYTE_12_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5851;"	d
+EFS_BYTE_12_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5853;"	d
+EFS_BYTE_12_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5855;"	d
+EFS_BYTE_13_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5859;"	d
+EFS_BYTE_13_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5857;"	d
+EFS_BYTE_13_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5856;"	d
+EFS_BYTE_13_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5858;"	d
+EFS_BYTE_13_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5860;"	d
+EFS_BYTE_14_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5864;"	d
+EFS_BYTE_14_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5862;"	d
+EFS_BYTE_14_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5861;"	d
+EFS_BYTE_14_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5863;"	d
+EFS_BYTE_14_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5865;"	d
+EFS_BYTE_15_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5869;"	d
+EFS_BYTE_15_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5867;"	d
+EFS_BYTE_15_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5866;"	d
+EFS_BYTE_15_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5868;"	d
+EFS_BYTE_15_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5870;"	d
+EFS_BYTE_16_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5874;"	d
+EFS_BYTE_16_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5872;"	d
+EFS_BYTE_16_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5871;"	d
+EFS_BYTE_16_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5873;"	d
+EFS_BYTE_16_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5875;"	d
+EFS_BYTE_17_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5879;"	d
+EFS_BYTE_17_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5877;"	d
+EFS_BYTE_17_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5876;"	d
+EFS_BYTE_17_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5878;"	d
+EFS_BYTE_17_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5880;"	d
+EFS_BYTE_18_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5884;"	d
+EFS_BYTE_18_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5882;"	d
+EFS_BYTE_18_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5881;"	d
+EFS_BYTE_18_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5883;"	d
+EFS_BYTE_18_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5885;"	d
+EFS_BYTE_19_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5889;"	d
+EFS_BYTE_19_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5887;"	d
+EFS_BYTE_19_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5886;"	d
+EFS_BYTE_19_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5888;"	d
+EFS_BYTE_19_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5890;"	d
+EFS_BYTE_1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5799;"	d
+EFS_BYTE_1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5797;"	d
+EFS_BYTE_1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5796;"	d
+EFS_BYTE_1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5798;"	d
+EFS_BYTE_1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5800;"	d
+EFS_BYTE_20_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5894;"	d
+EFS_BYTE_20_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5892;"	d
+EFS_BYTE_20_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5891;"	d
+EFS_BYTE_20_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5893;"	d
+EFS_BYTE_20_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5895;"	d
+EFS_BYTE_21_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5899;"	d
+EFS_BYTE_21_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5897;"	d
+EFS_BYTE_21_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5896;"	d
+EFS_BYTE_21_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5898;"	d
+EFS_BYTE_21_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5900;"	d
+EFS_BYTE_22_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5904;"	d
+EFS_BYTE_22_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5902;"	d
+EFS_BYTE_22_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5901;"	d
+EFS_BYTE_22_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5903;"	d
+EFS_BYTE_22_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5905;"	d
+EFS_BYTE_23_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5909;"	d
+EFS_BYTE_23_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5907;"	d
+EFS_BYTE_23_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5906;"	d
+EFS_BYTE_23_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5908;"	d
+EFS_BYTE_23_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5910;"	d
+EFS_BYTE_24_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5914;"	d
+EFS_BYTE_24_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5912;"	d
+EFS_BYTE_24_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5911;"	d
+EFS_BYTE_24_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5913;"	d
+EFS_BYTE_24_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5915;"	d
+EFS_BYTE_25_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5919;"	d
+EFS_BYTE_25_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5917;"	d
+EFS_BYTE_25_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5916;"	d
+EFS_BYTE_25_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5918;"	d
+EFS_BYTE_25_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5920;"	d
+EFS_BYTE_26_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5924;"	d
+EFS_BYTE_26_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5922;"	d
+EFS_BYTE_26_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5921;"	d
+EFS_BYTE_26_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5923;"	d
+EFS_BYTE_26_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5925;"	d
+EFS_BYTE_27_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5929;"	d
+EFS_BYTE_27_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5927;"	d
+EFS_BYTE_27_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5926;"	d
+EFS_BYTE_27_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5928;"	d
+EFS_BYTE_27_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5930;"	d
+EFS_BYTE_28_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5934;"	d
+EFS_BYTE_28_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5932;"	d
+EFS_BYTE_28_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5931;"	d
+EFS_BYTE_28_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5933;"	d
+EFS_BYTE_28_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5935;"	d
+EFS_BYTE_29_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5939;"	d
+EFS_BYTE_29_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5937;"	d
+EFS_BYTE_29_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5936;"	d
+EFS_BYTE_29_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5938;"	d
+EFS_BYTE_29_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5940;"	d
+EFS_BYTE_2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5804;"	d
+EFS_BYTE_2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5802;"	d
+EFS_BYTE_2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5801;"	d
+EFS_BYTE_2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5803;"	d
+EFS_BYTE_2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5805;"	d
+EFS_BYTE_30_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5944;"	d
+EFS_BYTE_30_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5942;"	d
+EFS_BYTE_30_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5941;"	d
+EFS_BYTE_30_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5943;"	d
+EFS_BYTE_30_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5945;"	d
+EFS_BYTE_31_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5949;"	d
+EFS_BYTE_31_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5947;"	d
+EFS_BYTE_31_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5946;"	d
+EFS_BYTE_31_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5948;"	d
+EFS_BYTE_31_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5950;"	d
+EFS_BYTE_3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5809;"	d
+EFS_BYTE_3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5807;"	d
+EFS_BYTE_3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5806;"	d
+EFS_BYTE_3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5808;"	d
+EFS_BYTE_3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5810;"	d
+EFS_BYTE_4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5814;"	d
+EFS_BYTE_4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5812;"	d
+EFS_BYTE_4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5811;"	d
+EFS_BYTE_4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5813;"	d
+EFS_BYTE_4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5815;"	d
+EFS_BYTE_5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5819;"	d
+EFS_BYTE_5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5817;"	d
+EFS_BYTE_5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5816;"	d
+EFS_BYTE_5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5818;"	d
+EFS_BYTE_5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5820;"	d
+EFS_BYTE_6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5824;"	d
+EFS_BYTE_6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5822;"	d
+EFS_BYTE_6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5821;"	d
+EFS_BYTE_6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5823;"	d
+EFS_BYTE_6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5825;"	d
+EFS_BYTE_7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5829;"	d
+EFS_BYTE_7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5827;"	d
+EFS_BYTE_7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5826;"	d
+EFS_BYTE_7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5828;"	d
+EFS_BYTE_7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5830;"	d
+EFS_BYTE_8_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5834;"	d
+EFS_BYTE_8_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5832;"	d
+EFS_BYTE_8_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5831;"	d
+EFS_BYTE_8_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5833;"	d
+EFS_BYTE_8_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5835;"	d
+EFS_BYTE_9_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5839;"	d
+EFS_BYTE_9_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5837;"	d
+EFS_BYTE_9_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5836;"	d
+EFS_BYTE_9_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5838;"	d
+EFS_BYTE_9_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5840;"	d
+EFS_CLKFREQ_HI	include/ssv6200_aux.h	6494;"	d
+EFS_CLKFREQ_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5739;"	d
+EFS_CLKFREQ_I_MSK	include/ssv6200_aux.h	6492;"	d
+EFS_CLKFREQ_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5737;"	d
+EFS_CLKFREQ_MSK	include/ssv6200_aux.h	6491;"	d
+EFS_CLKFREQ_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5736;"	d
+EFS_CLKFREQ_RD_HI	include/ssv6200_aux.h	6504;"	d
+EFS_CLKFREQ_RD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5749;"	d
+EFS_CLKFREQ_RD_I_MSK	include/ssv6200_aux.h	6502;"	d
+EFS_CLKFREQ_RD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5747;"	d
+EFS_CLKFREQ_RD_MSK	include/ssv6200_aux.h	6501;"	d
+EFS_CLKFREQ_RD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5746;"	d
+EFS_CLKFREQ_RD_SFT	include/ssv6200_aux.h	6503;"	d
+EFS_CLKFREQ_RD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5748;"	d
+EFS_CLKFREQ_RD_SZ	include/ssv6200_aux.h	6505;"	d
+EFS_CLKFREQ_RD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5750;"	d
+EFS_CLKFREQ_SFT	include/ssv6200_aux.h	6493;"	d
+EFS_CLKFREQ_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5738;"	d
+EFS_CLKFREQ_SZ	include/ssv6200_aux.h	6495;"	d
+EFS_CLKFREQ_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5740;"	d
+EFS_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1194;"	d
+EFS_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1192;"	d
+EFS_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1191;"	d
+EFS_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1193;"	d
+EFS_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1195;"	d
+EFS_LDO_OFF_HI	include/ssv6200_aux.h	6519;"	d
+EFS_LDO_OFF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5764;"	d
+EFS_LDO_OFF_I_MSK	include/ssv6200_aux.h	6517;"	d
+EFS_LDO_OFF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5762;"	d
+EFS_LDO_OFF_MSK	include/ssv6200_aux.h	6516;"	d
+EFS_LDO_OFF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5761;"	d
+EFS_LDO_OFF_SFT	include/ssv6200_aux.h	6518;"	d
+EFS_LDO_OFF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5763;"	d
+EFS_LDO_OFF_SZ	include/ssv6200_aux.h	6520;"	d
+EFS_LDO_OFF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5765;"	d
+EFS_LDO_ON_HI	include/ssv6200_aux.h	6514;"	d
+EFS_LDO_ON_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5759;"	d
+EFS_LDO_ON_I_MSK	include/ssv6200_aux.h	6512;"	d
+EFS_LDO_ON_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5757;"	d
+EFS_LDO_ON_MSK	include/ssv6200_aux.h	6511;"	d
+EFS_LDO_ON_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5756;"	d
+EFS_LDO_ON_SFT	include/ssv6200_aux.h	6513;"	d
+EFS_LDO_ON_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5758;"	d
+EFS_LDO_ON_SZ	include/ssv6200_aux.h	6515;"	d
+EFS_LDO_ON_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5760;"	d
+EFS_PRE_RD_HI	include/ssv6200_aux.h	6509;"	d
+EFS_PRE_RD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5754;"	d
+EFS_PRE_RD_I_MSK	include/ssv6200_aux.h	6507;"	d
+EFS_PRE_RD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5752;"	d
+EFS_PRE_RD_MSK	include/ssv6200_aux.h	6506;"	d
+EFS_PRE_RD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5751;"	d
+EFS_PRE_RD_SFT	include/ssv6200_aux.h	6508;"	d
+EFS_PRE_RD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5753;"	d
+EFS_PRE_RD_SZ	include/ssv6200_aux.h	6510;"	d
+EFS_PRE_RD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5755;"	d
+EFS_PROGRESS_DONE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5774;"	d
+EFS_PROGRESS_DONE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5772;"	d
+EFS_PROGRESS_DONE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5771;"	d
+EFS_PROGRESS_DONE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5773;"	d
+EFS_PROGRESS_DONE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5775;"	d
+EFS_RDATA_0_HI	include/ssv6200_aux.h	6524;"	d
+EFS_RDATA_0_I_MSK	include/ssv6200_aux.h	6522;"	d
+EFS_RDATA_0_MSK	include/ssv6200_aux.h	6521;"	d
+EFS_RDATA_0_SFT	include/ssv6200_aux.h	6523;"	d
+EFS_RDATA_0_SZ	include/ssv6200_aux.h	6525;"	d
+EFS_RDATA_1_HI	include/ssv6200_aux.h	6534;"	d
+EFS_RDATA_1_I_MSK	include/ssv6200_aux.h	6532;"	d
+EFS_RDATA_1_MSK	include/ssv6200_aux.h	6531;"	d
+EFS_RDATA_1_SFT	include/ssv6200_aux.h	6533;"	d
+EFS_RDATA_1_SZ	include/ssv6200_aux.h	6535;"	d
+EFS_RDATA_2_HI	include/ssv6200_aux.h	6544;"	d
+EFS_RDATA_2_I_MSK	include/ssv6200_aux.h	6542;"	d
+EFS_RDATA_2_MSK	include/ssv6200_aux.h	6541;"	d
+EFS_RDATA_2_SFT	include/ssv6200_aux.h	6543;"	d
+EFS_RDATA_2_SZ	include/ssv6200_aux.h	6545;"	d
+EFS_RDATA_3_HI	include/ssv6200_aux.h	6554;"	d
+EFS_RDATA_3_I_MSK	include/ssv6200_aux.h	6552;"	d
+EFS_RDATA_3_MSK	include/ssv6200_aux.h	6551;"	d
+EFS_RDATA_3_SFT	include/ssv6200_aux.h	6553;"	d
+EFS_RDATA_3_SZ	include/ssv6200_aux.h	6555;"	d
+EFS_RDATA_4_HI	include/ssv6200_aux.h	6564;"	d
+EFS_RDATA_4_I_MSK	include/ssv6200_aux.h	6562;"	d
+EFS_RDATA_4_MSK	include/ssv6200_aux.h	6561;"	d
+EFS_RDATA_4_SFT	include/ssv6200_aux.h	6563;"	d
+EFS_RDATA_4_SZ	include/ssv6200_aux.h	6565;"	d
+EFS_RDATA_5_HI	include/ssv6200_aux.h	6574;"	d
+EFS_RDATA_5_I_MSK	include/ssv6200_aux.h	6572;"	d
+EFS_RDATA_5_MSK	include/ssv6200_aux.h	6571;"	d
+EFS_RDATA_5_SFT	include/ssv6200_aux.h	6573;"	d
+EFS_RDATA_5_SZ	include/ssv6200_aux.h	6575;"	d
+EFS_RDATA_6_HI	include/ssv6200_aux.h	6584;"	d
+EFS_RDATA_6_I_MSK	include/ssv6200_aux.h	6582;"	d
+EFS_RDATA_6_MSK	include/ssv6200_aux.h	6581;"	d
+EFS_RDATA_6_SFT	include/ssv6200_aux.h	6583;"	d
+EFS_RDATA_6_SZ	include/ssv6200_aux.h	6585;"	d
+EFS_RDATA_7_HI	include/ssv6200_aux.h	6594;"	d
+EFS_RDATA_7_I_MSK	include/ssv6200_aux.h	6592;"	d
+EFS_RDATA_7_MSK	include/ssv6200_aux.h	6591;"	d
+EFS_RDATA_7_SFT	include/ssv6200_aux.h	6593;"	d
+EFS_RDATA_7_SZ	include/ssv6200_aux.h	6595;"	d
+EFS_RD_FLAG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5769;"	d
+EFS_RD_FLAG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5767;"	d
+EFS_RD_FLAG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5766;"	d
+EFS_RD_FLAG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5768;"	d
+EFS_RD_FLAG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5770;"	d
+EFS_RD_KICK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5784;"	d
+EFS_RD_KICK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5782;"	d
+EFS_RD_KICK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5781;"	d
+EFS_RD_KICK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5783;"	d
+EFS_RD_KICK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5785;"	d
+EFS_REG_BANK_SIZE	include/ssv6200_reg.h	93;"	d
+EFS_REG_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	110;"	d
+EFS_REG_BASE	include/ssv6200_reg.h	44;"	d
+EFS_REG_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	49;"	d
+EFS_SPI_RBUSY_HI	include/ssv6200_aux.h	6644;"	d
+EFS_SPI_RBUSY_I_MSK	include/ssv6200_aux.h	6642;"	d
+EFS_SPI_RBUSY_MSK	include/ssv6200_aux.h	6641;"	d
+EFS_SPI_RBUSY_SFT	include/ssv6200_aux.h	6643;"	d
+EFS_SPI_RBUSY_SZ	include/ssv6200_aux.h	6645;"	d
+EFS_SPI_RD0_EN_HI	include/ssv6200_aux.h	6604;"	d
+EFS_SPI_RD0_EN_I_MSK	include/ssv6200_aux.h	6602;"	d
+EFS_SPI_RD0_EN_MSK	include/ssv6200_aux.h	6601;"	d
+EFS_SPI_RD0_EN_SFT	include/ssv6200_aux.h	6603;"	d
+EFS_SPI_RD0_EN_SZ	include/ssv6200_aux.h	6605;"	d
+EFS_SPI_RD1_EN_HI	include/ssv6200_aux.h	6609;"	d
+EFS_SPI_RD1_EN_I_MSK	include/ssv6200_aux.h	6607;"	d
+EFS_SPI_RD1_EN_MSK	include/ssv6200_aux.h	6606;"	d
+EFS_SPI_RD1_EN_SFT	include/ssv6200_aux.h	6608;"	d
+EFS_SPI_RD1_EN_SZ	include/ssv6200_aux.h	6610;"	d
+EFS_SPI_RD2_EN_HI	include/ssv6200_aux.h	6614;"	d
+EFS_SPI_RD2_EN_I_MSK	include/ssv6200_aux.h	6612;"	d
+EFS_SPI_RD2_EN_MSK	include/ssv6200_aux.h	6611;"	d
+EFS_SPI_RD2_EN_SFT	include/ssv6200_aux.h	6613;"	d
+EFS_SPI_RD2_EN_SZ	include/ssv6200_aux.h	6615;"	d
+EFS_SPI_RD3_EN_HI	include/ssv6200_aux.h	6619;"	d
+EFS_SPI_RD3_EN_I_MSK	include/ssv6200_aux.h	6617;"	d
+EFS_SPI_RD3_EN_MSK	include/ssv6200_aux.h	6616;"	d
+EFS_SPI_RD3_EN_SFT	include/ssv6200_aux.h	6618;"	d
+EFS_SPI_RD3_EN_SZ	include/ssv6200_aux.h	6620;"	d
+EFS_SPI_RD4_EN_HI	include/ssv6200_aux.h	6624;"	d
+EFS_SPI_RD4_EN_I_MSK	include/ssv6200_aux.h	6622;"	d
+EFS_SPI_RD4_EN_MSK	include/ssv6200_aux.h	6621;"	d
+EFS_SPI_RD4_EN_SFT	include/ssv6200_aux.h	6623;"	d
+EFS_SPI_RD4_EN_SZ	include/ssv6200_aux.h	6625;"	d
+EFS_SPI_RD5_EN_HI	include/ssv6200_aux.h	6629;"	d
+EFS_SPI_RD5_EN_I_MSK	include/ssv6200_aux.h	6627;"	d
+EFS_SPI_RD5_EN_MSK	include/ssv6200_aux.h	6626;"	d
+EFS_SPI_RD5_EN_SFT	include/ssv6200_aux.h	6628;"	d
+EFS_SPI_RD5_EN_SZ	include/ssv6200_aux.h	6630;"	d
+EFS_SPI_RD6_EN_HI	include/ssv6200_aux.h	6634;"	d
+EFS_SPI_RD6_EN_I_MSK	include/ssv6200_aux.h	6632;"	d
+EFS_SPI_RD6_EN_MSK	include/ssv6200_aux.h	6631;"	d
+EFS_SPI_RD6_EN_SFT	include/ssv6200_aux.h	6633;"	d
+EFS_SPI_RD6_EN_SZ	include/ssv6200_aux.h	6635;"	d
+EFS_SPI_RD7_EN_HI	include/ssv6200_aux.h	6639;"	d
+EFS_SPI_RD7_EN_I_MSK	include/ssv6200_aux.h	6637;"	d
+EFS_SPI_RD7_EN_MSK	include/ssv6200_aux.h	6636;"	d
+EFS_SPI_RD7_EN_SFT	include/ssv6200_aux.h	6638;"	d
+EFS_SPI_RD7_EN_SZ	include/ssv6200_aux.h	6640;"	d
+EFS_SPI_RDATA_0_HI	include/ssv6200_aux.h	6649;"	d
+EFS_SPI_RDATA_0_I_MSK	include/ssv6200_aux.h	6647;"	d
+EFS_SPI_RDATA_0_MSK	include/ssv6200_aux.h	6646;"	d
+EFS_SPI_RDATA_0_SFT	include/ssv6200_aux.h	6648;"	d
+EFS_SPI_RDATA_0_SZ	include/ssv6200_aux.h	6650;"	d
+EFS_SPI_RDATA_1_HI	include/ssv6200_aux.h	6654;"	d
+EFS_SPI_RDATA_1_I_MSK	include/ssv6200_aux.h	6652;"	d
+EFS_SPI_RDATA_1_MSK	include/ssv6200_aux.h	6651;"	d
+EFS_SPI_RDATA_1_SFT	include/ssv6200_aux.h	6653;"	d
+EFS_SPI_RDATA_1_SZ	include/ssv6200_aux.h	6655;"	d
+EFS_SPI_RDATA_2_HI	include/ssv6200_aux.h	6659;"	d
+EFS_SPI_RDATA_2_I_MSK	include/ssv6200_aux.h	6657;"	d
+EFS_SPI_RDATA_2_MSK	include/ssv6200_aux.h	6656;"	d
+EFS_SPI_RDATA_2_SFT	include/ssv6200_aux.h	6658;"	d
+EFS_SPI_RDATA_2_SZ	include/ssv6200_aux.h	6660;"	d
+EFS_SPI_RDATA_3_HI	include/ssv6200_aux.h	6664;"	d
+EFS_SPI_RDATA_3_I_MSK	include/ssv6200_aux.h	6662;"	d
+EFS_SPI_RDATA_3_MSK	include/ssv6200_aux.h	6661;"	d
+EFS_SPI_RDATA_3_SFT	include/ssv6200_aux.h	6663;"	d
+EFS_SPI_RDATA_3_SZ	include/ssv6200_aux.h	6665;"	d
+EFS_SPI_RDATA_4_HI	include/ssv6200_aux.h	6669;"	d
+EFS_SPI_RDATA_4_I_MSK	include/ssv6200_aux.h	6667;"	d
+EFS_SPI_RDATA_4_MSK	include/ssv6200_aux.h	6666;"	d
+EFS_SPI_RDATA_4_SFT	include/ssv6200_aux.h	6668;"	d
+EFS_SPI_RDATA_4_SZ	include/ssv6200_aux.h	6670;"	d
+EFS_SPI_RDATA_5_HI	include/ssv6200_aux.h	6674;"	d
+EFS_SPI_RDATA_5_I_MSK	include/ssv6200_aux.h	6672;"	d
+EFS_SPI_RDATA_5_MSK	include/ssv6200_aux.h	6671;"	d
+EFS_SPI_RDATA_5_SFT	include/ssv6200_aux.h	6673;"	d
+EFS_SPI_RDATA_5_SZ	include/ssv6200_aux.h	6675;"	d
+EFS_SPI_RDATA_6_HI	include/ssv6200_aux.h	6679;"	d
+EFS_SPI_RDATA_6_I_MSK	include/ssv6200_aux.h	6677;"	d
+EFS_SPI_RDATA_6_MSK	include/ssv6200_aux.h	6676;"	d
+EFS_SPI_RDATA_6_SFT	include/ssv6200_aux.h	6678;"	d
+EFS_SPI_RDATA_6_SZ	include/ssv6200_aux.h	6680;"	d
+EFS_SPI_RDATA_7_HI	include/ssv6200_aux.h	6684;"	d
+EFS_SPI_RDATA_7_I_MSK	include/ssv6200_aux.h	6682;"	d
+EFS_SPI_RDATA_7_MSK	include/ssv6200_aux.h	6681;"	d
+EFS_SPI_RDATA_7_SFT	include/ssv6200_aux.h	6683;"	d
+EFS_SPI_RDATA_7_SZ	include/ssv6200_aux.h	6685;"	d
+EFS_VDDQ_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5789;"	d
+EFS_VDDQ_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5787;"	d
+EFS_VDDQ_EN_LOW_ACTIVE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5744;"	d
+EFS_VDDQ_EN_LOW_ACTIVE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5742;"	d
+EFS_VDDQ_EN_LOW_ACTIVE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5741;"	d
+EFS_VDDQ_EN_LOW_ACTIVE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5743;"	d
+EFS_VDDQ_EN_LOW_ACTIVE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5745;"	d
+EFS_VDDQ_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5786;"	d
+EFS_VDDQ_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5788;"	d
+EFS_VDDQ_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5790;"	d
+EFS_WDATA_0_HI	include/ssv6200_aux.h	6529;"	d
+EFS_WDATA_0_I_MSK	include/ssv6200_aux.h	6527;"	d
+EFS_WDATA_0_MSK	include/ssv6200_aux.h	6526;"	d
+EFS_WDATA_0_SFT	include/ssv6200_aux.h	6528;"	d
+EFS_WDATA_0_SZ	include/ssv6200_aux.h	6530;"	d
+EFS_WDATA_1_HI	include/ssv6200_aux.h	6539;"	d
+EFS_WDATA_1_I_MSK	include/ssv6200_aux.h	6537;"	d
+EFS_WDATA_1_MSK	include/ssv6200_aux.h	6536;"	d
+EFS_WDATA_1_SFT	include/ssv6200_aux.h	6538;"	d
+EFS_WDATA_1_SZ	include/ssv6200_aux.h	6540;"	d
+EFS_WDATA_2_HI	include/ssv6200_aux.h	6549;"	d
+EFS_WDATA_2_I_MSK	include/ssv6200_aux.h	6547;"	d
+EFS_WDATA_2_MSK	include/ssv6200_aux.h	6546;"	d
+EFS_WDATA_2_SFT	include/ssv6200_aux.h	6548;"	d
+EFS_WDATA_2_SZ	include/ssv6200_aux.h	6550;"	d
+EFS_WDATA_3_HI	include/ssv6200_aux.h	6559;"	d
+EFS_WDATA_3_I_MSK	include/ssv6200_aux.h	6557;"	d
+EFS_WDATA_3_MSK	include/ssv6200_aux.h	6556;"	d
+EFS_WDATA_3_SFT	include/ssv6200_aux.h	6558;"	d
+EFS_WDATA_3_SZ	include/ssv6200_aux.h	6560;"	d
+EFS_WDATA_4_HI	include/ssv6200_aux.h	6569;"	d
+EFS_WDATA_4_I_MSK	include/ssv6200_aux.h	6567;"	d
+EFS_WDATA_4_MSK	include/ssv6200_aux.h	6566;"	d
+EFS_WDATA_4_SFT	include/ssv6200_aux.h	6568;"	d
+EFS_WDATA_4_SZ	include/ssv6200_aux.h	6570;"	d
+EFS_WDATA_5_HI	include/ssv6200_aux.h	6579;"	d
+EFS_WDATA_5_I_MSK	include/ssv6200_aux.h	6577;"	d
+EFS_WDATA_5_MSK	include/ssv6200_aux.h	6576;"	d
+EFS_WDATA_5_SFT	include/ssv6200_aux.h	6578;"	d
+EFS_WDATA_5_SZ	include/ssv6200_aux.h	6580;"	d
+EFS_WDATA_6_HI	include/ssv6200_aux.h	6589;"	d
+EFS_WDATA_6_I_MSK	include/ssv6200_aux.h	6587;"	d
+EFS_WDATA_6_MSK	include/ssv6200_aux.h	6586;"	d
+EFS_WDATA_6_SFT	include/ssv6200_aux.h	6588;"	d
+EFS_WDATA_6_SZ	include/ssv6200_aux.h	6590;"	d
+EFS_WDATA_7_HI	include/ssv6200_aux.h	6599;"	d
+EFS_WDATA_7_I_MSK	include/ssv6200_aux.h	6597;"	d
+EFS_WDATA_7_MSK	include/ssv6200_aux.h	6596;"	d
+EFS_WDATA_7_SFT	include/ssv6200_aux.h	6598;"	d
+EFS_WDATA_7_SZ	include/ssv6200_aux.h	6600;"	d
+EFS_WR_KICK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5779;"	d
+EFS_WR_KICK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5777;"	d
+EFS_WR_KICK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5776;"	d
+EFS_WR_KICK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5778;"	d
+EFS_WR_KICK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5780;"	d
+EFUSE_CHIP_ID	smac/efuse.h	/^   EFUSE_CHIP_ID,$/;"	e	enum:efuse_data_item
+EFUSE_CRYSTAL_FREQUENCY_OFFSET	smac/efuse.h	/^   EFUSE_CRYSTAL_FREQUENCY_OFFSET,$/;"	e	enum:efuse_data_item
+EFUSE_HWSET_MAX_SIZE	include/hal.h	26;"	d
+EFUSE_HWSET_MAX_SIZE	smac/efuse.h	43;"	d
+EFUSE_MAC	smac/efuse.h	/^   EFUSE_MAC,$/;"	e	enum:efuse_data_item
+EFUSE_MAC_NEW	smac/efuse.h	/^   EFUSE_MAC_NEW,$/;"	e	enum:efuse_data_item
+EFUSE_MAX_SECTION_MAP	include/hal.h	27;"	d
+EFUSE_MAX_SECTION_MAP	smac/efuse.h	44;"	d
+EFUSE_PID	smac/efuse.h	/^   EFUSE_PID,$/;"	e	enum:efuse_data_item
+EFUSE_RATE_TABLE_1	smac/efuse.h	/^   EFUSE_RATE_TABLE_1,$/;"	e	enum:efuse_data_item
+EFUSE_RATE_TABLE_2	smac/efuse.h	/^   EFUSE_RATE_TABLE_2$/;"	e	enum:efuse_data_item
+EFUSE_R_CALIBRATION_RESULT	smac/efuse.h	/^   EFUSE_R_CALIBRATION_RESULT = 1,$/;"	e	enum:efuse_data_item
+EFUSE_SAR_RESULT	smac/efuse.h	/^   EFUSE_SAR_RESULT,$/;"	e	enum:efuse_data_item
+EFUSE_TX_POWER_INDEX_1	smac/efuse.h	/^   EFUSE_TX_POWER_INDEX_1,$/;"	e	enum:efuse_data_item
+EFUSE_TX_POWER_INDEX_2	smac/efuse.h	/^   EFUSE_TX_POWER_INDEX_2,$/;"	e	enum:efuse_data_item
+EFUSE_VID	smac/efuse.h	/^   EFUSE_VID,$/;"	e	enum:efuse_data_item
+EIFS_IN_SLOT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7324;"	d
+EIFS_IN_SLOT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7322;"	d
+EIFS_IN_SLOT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7321;"	d
+EIFS_IN_SLOT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7323;"	d
+EIFS_IN_SLOT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7325;"	d
+EILM_ROM_ERRCK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1459;"	d
+EILM_ROM_ERRCK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1457;"	d
+EILM_ROM_ERRCK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1456;"	d
+EILM_ROM_ERRCK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1458;"	d
+EILM_ROM_ERRCK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1460;"	d
+EILM_ROM_ERR_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1484;"	d
+EILM_ROM_ERR_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1482;"	d
+EILM_ROM_ERR_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1481;"	d
+EILM_ROM_ERR_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1483;"	d
+EILM_ROM_ERR_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1485;"	d
+EILM_SRAM_ERRCK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1464;"	d
+EILM_SRAM_ERRCK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1462;"	d
+EILM_SRAM_ERRCK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1461;"	d
+EILM_SRAM_ERRCK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1463;"	d
+EILM_SRAM_ERRCK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1465;"	d
+EILM_SRAM_ERR_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1489;"	d
+EILM_SRAM_ERR_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1487;"	d
+EILM_SRAM_ERR_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1486;"	d
+EILM_SRAM_ERR_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1488;"	d
+EILM_SRAM_ERR_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1490;"	d
+ENABLECSA_HI	include/ssv6200_aux.h	3749;"	d
+ENABLECSA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2884;"	d
+ENABLECSA_I_MSK	include/ssv6200_aux.h	3747;"	d
+ENABLECSA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2882;"	d
+ENABLECSA_MSK	include/ssv6200_aux.h	3746;"	d
+ENABLECSA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2881;"	d
+ENABLECSA_SFT	include/ssv6200_aux.h	3748;"	d
+ENABLECSA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2883;"	d
+ENABLECSA_SZ	include/ssv6200_aux.h	3750;"	d
+ENABLECSA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2885;"	d
+ENABLE_AGGREGATE_IN_TIME	include/ssv_mod_conf.h	37;"	d
+ENABLE_BLOCK_GAP_INTERRUPT_HI	include/ssv6200_aux.h	3709;"	d
+ENABLE_BLOCK_GAP_INTERRUPT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2834;"	d
+ENABLE_BLOCK_GAP_INTERRUPT_I_MSK	include/ssv6200_aux.h	3707;"	d
+ENABLE_BLOCK_GAP_INTERRUPT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2832;"	d
+ENABLE_BLOCK_GAP_INTERRUPT_MSK	include/ssv6200_aux.h	3706;"	d
+ENABLE_BLOCK_GAP_INTERRUPT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2831;"	d
+ENABLE_BLOCK_GAP_INTERRUPT_SFT	include/ssv6200_aux.h	3708;"	d
+ENABLE_BLOCK_GAP_INTERRUPT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2833;"	d
+ENABLE_BLOCK_GAP_INTERRUPT_SZ	include/ssv6200_aux.h	3710;"	d
+ENABLE_BLOCK_GAP_INTERRUPT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2835;"	d
+ENABLE_FW_SELF_CHECK	include/ssv6xxx_common.h	383;"	d
+ENABLE_INCREMENTAL_AGGREGATION	include/ssv_mod_conf.h	40;"	d
+ENC_DIN_MSB_HI	include/ssv6200_aux.h	6719;"	d
+ENC_DIN_MSB_I_MSK	include/ssv6200_aux.h	6717;"	d
+ENC_DIN_MSB_MSK	include/ssv6200_aux.h	6716;"	d
+ENC_DIN_MSB_SFT	include/ssv6200_aux.h	6718;"	d
+ENC_DIN_MSB_SZ	include/ssv6200_aux.h	6720;"	d
+ENC_DOUT_MSB_HI	include/ssv6200_aux.h	6714;"	d
+ENC_DOUT_MSB_I_MSK	include/ssv6200_aux.h	6712;"	d
+ENC_DOUT_MSB_MSK	include/ssv6200_aux.h	6711;"	d
+ENC_DOUT_MSB_SFT	include/ssv6200_aux.h	6713;"	d
+ENC_DOUT_MSB_SZ	include/ssv6200_aux.h	6715;"	d
+ENDIAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6014;"	d
+ENDIAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6012;"	d
+ENDIAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6011;"	d
+ENDIAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6013;"	d
+ENDIAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6015;"	d
+END_BYTE_VALUE2_HI	include/ssv6200_aux.h	3624;"	d
+END_BYTE_VALUE2_I_MSK	include/ssv6200_aux.h	3622;"	d
+END_BYTE_VALUE2_MSK	include/ssv6200_aux.h	3621;"	d
+END_BYTE_VALUE2_SFT	include/ssv6200_aux.h	3623;"	d
+END_BYTE_VALUE2_SZ	include/ssv6200_aux.h	3625;"	d
+END_BYTE_VALUE_HI	include/ssv6200_aux.h	3299;"	d
+END_BYTE_VALUE_I_MSK	include/ssv6200_aux.h	3297;"	d
+END_BYTE_VALUE_MSK	include/ssv6200_aux.h	3296;"	d
+END_BYTE_VALUE_SFT	include/ssv6200_aux.h	3298;"	d
+END_BYTE_VALUE_SZ	include/ssv6200_aux.h	3300;"	d
+END_READ_CRYPTO_DATA	smac/dev.h	1110;"	d
+END_READ_CRYPTO_DATA	smac/dev.h	1120;"	d
+END_WRITE_CRYPTO_DATA	smac/dev.h	1102;"	d
+END_WRITE_CRYPTO_DATA	smac/dev.h	1118;"	d
+ENHANCE_PWR	smac/dev.h	574;"	d
+EN_AUTO_CTS_HI	include/ssv6200_aux.h	4319;"	d
+EN_AUTO_CTS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3424;"	d
+EN_AUTO_CTS_I_MSK	include/ssv6200_aux.h	4317;"	d
+EN_AUTO_CTS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3422;"	d
+EN_AUTO_CTS_MSK	include/ssv6200_aux.h	4316;"	d
+EN_AUTO_CTS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3421;"	d
+EN_AUTO_CTS_SFT	include/ssv6200_aux.h	4318;"	d
+EN_AUTO_CTS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3423;"	d
+EN_AUTO_CTS_SZ	include/ssv6200_aux.h	4320;"	d
+EN_AUTO_CTS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3425;"	d
+EN_AUTO_RTS_HI	include/ssv6200_aux.h	4314;"	d
+EN_AUTO_RTS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3419;"	d
+EN_AUTO_RTS_I_MSK	include/ssv6200_aux.h	4312;"	d
+EN_AUTO_RTS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3417;"	d
+EN_AUTO_RTS_MSK	include/ssv6200_aux.h	4311;"	d
+EN_AUTO_RTS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3416;"	d
+EN_AUTO_RTS_SFT	include/ssv6200_aux.h	4313;"	d
+EN_AUTO_RTS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3418;"	d
+EN_AUTO_RTS_SZ	include/ssv6200_aux.h	4315;"	d
+EN_AUTO_RTS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3420;"	d
+EN_STAT_FINISH_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7049;"	d
+EN_STAT_FINISH_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7047;"	d
+EN_STAT_FINISH_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7046;"	d
+EN_STAT_FINISH_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7048;"	d
+EN_STAT_FINISH_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7050;"	d
+EN_UNEXPECT_WSID_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7044;"	d
+EN_UNEXPECT_WSID_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7042;"	d
+EN_UNEXPECT_WSID_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7041;"	d
+EN_UNEXPECT_WSID_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7043;"	d
+EN_UNEXPECT_WSID_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7045;"	d
+EOSP_HW_ID_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6509;"	d
+EOSP_HW_ID_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6507;"	d
+EOSP_HW_ID_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6506;"	d
+EOSP_HW_ID_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6508;"	d
+EOSP_HW_ID_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6510;"	d
+EOSP_H_QUEUE_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6504;"	d
+EOSP_H_QUEUE_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6502;"	d
+EOSP_H_QUEUE_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6501;"	d
+EOSP_H_QUEUE_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6503;"	d
+EOSP_H_QUEUE_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6505;"	d
+ERP_PROTECT_HI	include/ssv6200_aux.h	6079;"	d
+ERP_PROTECT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5129;"	d
+ERP_PROTECT_I_MSK	include/ssv6200_aux.h	6077;"	d
+ERP_PROTECT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5127;"	d
+ERP_PROTECT_MSK	include/ssv6200_aux.h	6076;"	d
+ERP_PROTECT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5126;"	d
+ERP_PROTECT_SFT	include/ssv6200_aux.h	6078;"	d
+ERP_PROTECT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5128;"	d
+ERP_PROTECT_SZ	include/ssv6200_aux.h	6080;"	d
+ERP_PROTECT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5130;"	d
+ERROR_CREATE_LOCK_FAIL	smartlink/qqlink-lib-mipsel/include/TXVoiceLink.h	/^ ERROR_CREATE_LOCK_FAIL = 3,$/;"	e	enum:RESULT
+ERROR_CREATE_THREAD_FAIL	smartlink/qqlink-lib-mipsel/include/TXVoiceLink.h	/^ ERROR_CREATE_THREAD_FAIL = 4,$/;"	e	enum:RESULT
+ERROR_INITED	smartlink/qqlink-lib-mipsel/include/TXVoiceLink.h	/^ ERROR_INITED = 1,$/;"	e	enum:RESULT
+ERROR_NO_MEMORY	smartlink/qqlink-lib-mipsel/include/TXVoiceLink.h	/^ ERROR_NO_MEMORY = 2,$/;"	e	enum:RESULT
+ERROR_NULL	smartlink/qqlink-lib-mipsel/include/TXVoiceLink.h	/^ ERROR_NULL = 0,$/;"	e	enum:RESULT
+ERR_FLAG_CLR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4184;"	d
+ERR_FLAG_CLR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4182;"	d
+ERR_FLAG_CLR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4181;"	d
+ERR_FLAG_CLR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4183;"	d
+ERR_FLAG_CLR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4185;"	d
+ERR_SW_RST_N_HI	include/ssv6200_aux.h	17699;"	d
+ERR_SW_RST_N_I_MSK	include/ssv6200_aux.h	17697;"	d
+ERR_SW_RST_N_MSK	include/ssv6200_aux.h	17696;"	d
+ERR_SW_RST_N_SFT	include/ssv6200_aux.h	17698;"	d
+ERR_SW_RST_N_SZ	include/ssv6200_aux.h	17700;"	d
+EVEN_PARITY_HI	include/ssv6200_aux.h	4344;"	d
+EVEN_PARITY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3449;"	d
+EVEN_PARITY_I_MSK	include/ssv6200_aux.h	4342;"	d
+EVEN_PARITY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3447;"	d
+EVEN_PARITY_MSK	include/ssv6200_aux.h	4341;"	d
+EVEN_PARITY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3446;"	d
+EVEN_PARITY_SFT	include/ssv6200_aux.h	4343;"	d
+EVEN_PARITY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3448;"	d
+EVEN_PARITY_SZ	include/ssv6200_aux.h	4345;"	d
+EVEN_PARITY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3450;"	d
+EWMA_LEVEL	smac/ssv_ht_rc.c	27;"	d	file:
+EWMA_LEVEL	smac/ssv_rc_minstrel_ht.h	18;"	d
+EXTERNEL_CONFIG_SUPPORT	include/ssv_cfg.h	33;"	d
+EXTRA_CFLAGS	config.mak	/^EXTRA_CFLAGS := -I$(KBUILD_TOP) $/;"	m
+EXT_32K_SEL_HI	include/ssv6200_aux.h	2989;"	d
+EXT_32K_SEL_I_MSK	include/ssv6200_aux.h	2987;"	d
+EXT_32K_SEL_MSK	include/ssv6200_aux.h	2986;"	d
+EXT_32K_SEL_SFT	include/ssv6200_aux.h	2988;"	d
+EXT_32K_SEL_SZ	include/ssv6200_aux.h	2990;"	d
+EXT_MAC_MODE_HI	include/ssv6200_aux.h	8784;"	d
+EXT_MAC_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8539;"	d
+EXT_MAC_MODE_I_MSK	include/ssv6200_aux.h	8782;"	d
+EXT_MAC_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8537;"	d
+EXT_MAC_MODE_MSK	include/ssv6200_aux.h	8781;"	d
+EXT_MAC_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8536;"	d
+EXT_MAC_MODE_SFT	include/ssv6200_aux.h	8783;"	d
+EXT_MAC_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8538;"	d
+EXT_MAC_MODE_SZ	include/ssv6200_aux.h	8785;"	d
+EXT_MAC_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8540;"	d
+EXT_PHY_MODE_HI	include/ssv6200_aux.h	8789;"	d
+EXT_PHY_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8544;"	d
+EXT_PHY_MODE_I_MSK	include/ssv6200_aux.h	8787;"	d
+EXT_PHY_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8542;"	d
+EXT_PHY_MODE_MSK	include/ssv6200_aux.h	8786;"	d
+EXT_PHY_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8541;"	d
+EXT_PHY_MODE_SFT	include/ssv6200_aux.h	8788;"	d
+EXT_PHY_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8543;"	d
+EXT_PHY_MODE_SZ	include/ssv6200_aux.h	8790;"	d
+EXT_PHY_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8545;"	d
+Enable_AMPDU_Live_Time	smac/ampdu.h	23;"	d
+Enable_AMPDU_Rx	smac/ampdu.h	25;"	d
+Enable_AMPDU_Tx	smac/ampdu.h	26;"	d
+Enable_AMPDU_delay_work	smac/ampdu.h	27;"	d
+Enable_HW_AUTO_CRC_32	smac/ampdu.h	24;"	d
+Enable_ampdu_debug_log	smac/ampdu.h	22;"	d
+EncoderThread	smartlink/qqlink-lib-mipsel/case/ipcamera/audiovideo.c	/^static void* EncoderThread(void* pThreadData) {$/;"	f	file:	signature:(void* pThreadData)
+EncoderThread	smartlink/qqlink-lib-mipsel/demo_video.c	/^static void* EncoderThread(void* pThreadData) {$/;"	f	file:	signature:(void* pThreadData)
+F0_CIS_CONTENT_REG_127_96_HI	include/ssv6200_aux.h	3779;"	d
+F0_CIS_CONTENT_REG_127_96_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2914;"	d
+F0_CIS_CONTENT_REG_127_96_I_MSK	include/ssv6200_aux.h	3777;"	d
+F0_CIS_CONTENT_REG_127_96_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2912;"	d
+F0_CIS_CONTENT_REG_127_96_MSK	include/ssv6200_aux.h	3776;"	d
+F0_CIS_CONTENT_REG_127_96_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2911;"	d
+F0_CIS_CONTENT_REG_127_96_SFT	include/ssv6200_aux.h	3778;"	d
+F0_CIS_CONTENT_REG_127_96_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2913;"	d
+F0_CIS_CONTENT_REG_127_96_SZ	include/ssv6200_aux.h	3780;"	d
+F0_CIS_CONTENT_REG_127_96_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2915;"	d
+F0_CIS_CONTENT_REG_159_128_HI	include/ssv6200_aux.h	3784;"	d
+F0_CIS_CONTENT_REG_159_128_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2919;"	d
+F0_CIS_CONTENT_REG_159_128_I_MSK	include/ssv6200_aux.h	3782;"	d
+F0_CIS_CONTENT_REG_159_128_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2917;"	d
+F0_CIS_CONTENT_REG_159_128_MSK	include/ssv6200_aux.h	3781;"	d
+F0_CIS_CONTENT_REG_159_128_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2916;"	d
+F0_CIS_CONTENT_REG_159_128_SFT	include/ssv6200_aux.h	3783;"	d
+F0_CIS_CONTENT_REG_159_128_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2918;"	d
+F0_CIS_CONTENT_REG_159_128_SZ	include/ssv6200_aux.h	3785;"	d
+F0_CIS_CONTENT_REG_159_128_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2920;"	d
+F0_CIS_CONTENT_REG_191_160_HI	include/ssv6200_aux.h	3789;"	d
+F0_CIS_CONTENT_REG_191_160_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2924;"	d
+F0_CIS_CONTENT_REG_191_160_I_MSK	include/ssv6200_aux.h	3787;"	d
+F0_CIS_CONTENT_REG_191_160_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2922;"	d
+F0_CIS_CONTENT_REG_191_160_MSK	include/ssv6200_aux.h	3786;"	d
+F0_CIS_CONTENT_REG_191_160_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2921;"	d
+F0_CIS_CONTENT_REG_191_160_SFT	include/ssv6200_aux.h	3788;"	d
+F0_CIS_CONTENT_REG_191_160_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2923;"	d
+F0_CIS_CONTENT_REG_191_160_SZ	include/ssv6200_aux.h	3790;"	d
+F0_CIS_CONTENT_REG_191_160_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2925;"	d
+F0_CIS_CONTENT_REG_223_192_HI	include/ssv6200_aux.h	3794;"	d
+F0_CIS_CONTENT_REG_223_192_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2929;"	d
+F0_CIS_CONTENT_REG_223_192_I_MSK	include/ssv6200_aux.h	3792;"	d
+F0_CIS_CONTENT_REG_223_192_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2927;"	d
+F0_CIS_CONTENT_REG_223_192_MSK	include/ssv6200_aux.h	3791;"	d
+F0_CIS_CONTENT_REG_223_192_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2926;"	d
+F0_CIS_CONTENT_REG_223_192_SFT	include/ssv6200_aux.h	3793;"	d
+F0_CIS_CONTENT_REG_223_192_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2928;"	d
+F0_CIS_CONTENT_REG_223_192_SZ	include/ssv6200_aux.h	3795;"	d
+F0_CIS_CONTENT_REG_223_192_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2930;"	d
+F0_CIS_CONTENT_REG_255_224_HI	include/ssv6200_aux.h	3799;"	d
+F0_CIS_CONTENT_REG_255_224_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2934;"	d
+F0_CIS_CONTENT_REG_255_224_I_MSK	include/ssv6200_aux.h	3797;"	d
+F0_CIS_CONTENT_REG_255_224_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2932;"	d
+F0_CIS_CONTENT_REG_255_224_MSK	include/ssv6200_aux.h	3796;"	d
+F0_CIS_CONTENT_REG_255_224_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2931;"	d
+F0_CIS_CONTENT_REG_255_224_SFT	include/ssv6200_aux.h	3798;"	d
+F0_CIS_CONTENT_REG_255_224_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2933;"	d
+F0_CIS_CONTENT_REG_255_224_SZ	include/ssv6200_aux.h	3800;"	d
+F0_CIS_CONTENT_REG_255_224_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2935;"	d
+F0_CIS_CONTENT_REG_287_256_HI	include/ssv6200_aux.h	3804;"	d
+F0_CIS_CONTENT_REG_287_256_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2939;"	d
+F0_CIS_CONTENT_REG_287_256_I_MSK	include/ssv6200_aux.h	3802;"	d
+F0_CIS_CONTENT_REG_287_256_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2937;"	d
+F0_CIS_CONTENT_REG_287_256_MSK	include/ssv6200_aux.h	3801;"	d
+F0_CIS_CONTENT_REG_287_256_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2936;"	d
+F0_CIS_CONTENT_REG_287_256_SFT	include/ssv6200_aux.h	3803;"	d
+F0_CIS_CONTENT_REG_287_256_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2938;"	d
+F0_CIS_CONTENT_REG_287_256_SZ	include/ssv6200_aux.h	3805;"	d
+F0_CIS_CONTENT_REG_287_256_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2940;"	d
+F0_CIS_CONTENT_REG_319_288_HI	include/ssv6200_aux.h	3809;"	d
+F0_CIS_CONTENT_REG_319_288_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2944;"	d
+F0_CIS_CONTENT_REG_319_288_I_MSK	include/ssv6200_aux.h	3807;"	d
+F0_CIS_CONTENT_REG_319_288_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2942;"	d
+F0_CIS_CONTENT_REG_319_288_MSK	include/ssv6200_aux.h	3806;"	d
+F0_CIS_CONTENT_REG_319_288_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2941;"	d
+F0_CIS_CONTENT_REG_319_288_SFT	include/ssv6200_aux.h	3808;"	d
+F0_CIS_CONTENT_REG_319_288_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2943;"	d
+F0_CIS_CONTENT_REG_319_288_SZ	include/ssv6200_aux.h	3810;"	d
+F0_CIS_CONTENT_REG_319_288_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2945;"	d
+F0_CIS_CONTENT_REG_31_0_HI	include/ssv6200_aux.h	3764;"	d
+F0_CIS_CONTENT_REG_31_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2899;"	d
+F0_CIS_CONTENT_REG_31_0_I_MSK	include/ssv6200_aux.h	3762;"	d
+F0_CIS_CONTENT_REG_31_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2897;"	d
+F0_CIS_CONTENT_REG_31_0_MSK	include/ssv6200_aux.h	3761;"	d
+F0_CIS_CONTENT_REG_31_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2896;"	d
+F0_CIS_CONTENT_REG_31_0_SFT	include/ssv6200_aux.h	3763;"	d
+F0_CIS_CONTENT_REG_31_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2898;"	d
+F0_CIS_CONTENT_REG_31_0_SZ	include/ssv6200_aux.h	3765;"	d
+F0_CIS_CONTENT_REG_31_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2900;"	d
+F0_CIS_CONTENT_REG_351_320_HI	include/ssv6200_aux.h	3814;"	d
+F0_CIS_CONTENT_REG_351_320_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2949;"	d
+F0_CIS_CONTENT_REG_351_320_I_MSK	include/ssv6200_aux.h	3812;"	d
+F0_CIS_CONTENT_REG_351_320_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2947;"	d
+F0_CIS_CONTENT_REG_351_320_MSK	include/ssv6200_aux.h	3811;"	d
+F0_CIS_CONTENT_REG_351_320_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2946;"	d
+F0_CIS_CONTENT_REG_351_320_SFT	include/ssv6200_aux.h	3813;"	d
+F0_CIS_CONTENT_REG_351_320_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2948;"	d
+F0_CIS_CONTENT_REG_351_320_SZ	include/ssv6200_aux.h	3815;"	d
+F0_CIS_CONTENT_REG_351_320_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2950;"	d
+F0_CIS_CONTENT_REG_383_352_HI	include/ssv6200_aux.h	3819;"	d
+F0_CIS_CONTENT_REG_383_352_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2954;"	d
+F0_CIS_CONTENT_REG_383_352_I_MSK	include/ssv6200_aux.h	3817;"	d
+F0_CIS_CONTENT_REG_383_352_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2952;"	d
+F0_CIS_CONTENT_REG_383_352_MSK	include/ssv6200_aux.h	3816;"	d
+F0_CIS_CONTENT_REG_383_352_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2951;"	d
+F0_CIS_CONTENT_REG_383_352_SFT	include/ssv6200_aux.h	3818;"	d
+F0_CIS_CONTENT_REG_383_352_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2953;"	d
+F0_CIS_CONTENT_REG_383_352_SZ	include/ssv6200_aux.h	3820;"	d
+F0_CIS_CONTENT_REG_383_352_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2955;"	d
+F0_CIS_CONTENT_REG_415_384_HI	include/ssv6200_aux.h	3824;"	d
+F0_CIS_CONTENT_REG_415_384_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2959;"	d
+F0_CIS_CONTENT_REG_415_384_I_MSK	include/ssv6200_aux.h	3822;"	d
+F0_CIS_CONTENT_REG_415_384_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2957;"	d
+F0_CIS_CONTENT_REG_415_384_MSK	include/ssv6200_aux.h	3821;"	d
+F0_CIS_CONTENT_REG_415_384_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2956;"	d
+F0_CIS_CONTENT_REG_415_384_SFT	include/ssv6200_aux.h	3823;"	d
+F0_CIS_CONTENT_REG_415_384_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2958;"	d
+F0_CIS_CONTENT_REG_415_384_SZ	include/ssv6200_aux.h	3825;"	d
+F0_CIS_CONTENT_REG_415_384_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2960;"	d
+F0_CIS_CONTENT_REG_447_416_HI	include/ssv6200_aux.h	3829;"	d
+F0_CIS_CONTENT_REG_447_416_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2964;"	d
+F0_CIS_CONTENT_REG_447_416_I_MSK	include/ssv6200_aux.h	3827;"	d
+F0_CIS_CONTENT_REG_447_416_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2962;"	d
+F0_CIS_CONTENT_REG_447_416_MSK	include/ssv6200_aux.h	3826;"	d
+F0_CIS_CONTENT_REG_447_416_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2961;"	d
+F0_CIS_CONTENT_REG_447_416_SFT	include/ssv6200_aux.h	3828;"	d
+F0_CIS_CONTENT_REG_447_416_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2963;"	d
+F0_CIS_CONTENT_REG_447_416_SZ	include/ssv6200_aux.h	3830;"	d
+F0_CIS_CONTENT_REG_447_416_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2965;"	d
+F0_CIS_CONTENT_REG_479_448_HI	include/ssv6200_aux.h	3834;"	d
+F0_CIS_CONTENT_REG_479_448_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2969;"	d
+F0_CIS_CONTENT_REG_479_448_I_MSK	include/ssv6200_aux.h	3832;"	d
+F0_CIS_CONTENT_REG_479_448_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2967;"	d
+F0_CIS_CONTENT_REG_479_448_MSK	include/ssv6200_aux.h	3831;"	d
+F0_CIS_CONTENT_REG_479_448_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2966;"	d
+F0_CIS_CONTENT_REG_479_448_SFT	include/ssv6200_aux.h	3833;"	d
+F0_CIS_CONTENT_REG_479_448_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2968;"	d
+F0_CIS_CONTENT_REG_479_448_SZ	include/ssv6200_aux.h	3835;"	d
+F0_CIS_CONTENT_REG_479_448_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2970;"	d
+F0_CIS_CONTENT_REG_511_480_HI	include/ssv6200_aux.h	3839;"	d
+F0_CIS_CONTENT_REG_511_480_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2974;"	d
+F0_CIS_CONTENT_REG_511_480_I_MSK	include/ssv6200_aux.h	3837;"	d
+F0_CIS_CONTENT_REG_511_480_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2972;"	d
+F0_CIS_CONTENT_REG_511_480_MSK	include/ssv6200_aux.h	3836;"	d
+F0_CIS_CONTENT_REG_511_480_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2971;"	d
+F0_CIS_CONTENT_REG_511_480_SFT	include/ssv6200_aux.h	3838;"	d
+F0_CIS_CONTENT_REG_511_480_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2973;"	d
+F0_CIS_CONTENT_REG_511_480_SZ	include/ssv6200_aux.h	3840;"	d
+F0_CIS_CONTENT_REG_511_480_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2975;"	d
+F0_CIS_CONTENT_REG_63_32_HI	include/ssv6200_aux.h	3769;"	d
+F0_CIS_CONTENT_REG_63_32_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2904;"	d
+F0_CIS_CONTENT_REG_63_32_I_MSK	include/ssv6200_aux.h	3767;"	d
+F0_CIS_CONTENT_REG_63_32_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2902;"	d
+F0_CIS_CONTENT_REG_63_32_MSK	include/ssv6200_aux.h	3766;"	d
+F0_CIS_CONTENT_REG_63_32_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2901;"	d
+F0_CIS_CONTENT_REG_63_32_SFT	include/ssv6200_aux.h	3768;"	d
+F0_CIS_CONTENT_REG_63_32_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2903;"	d
+F0_CIS_CONTENT_REG_63_32_SZ	include/ssv6200_aux.h	3770;"	d
+F0_CIS_CONTENT_REG_63_32_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2905;"	d
+F0_CIS_CONTENT_REG_95_64_HI	include/ssv6200_aux.h	3774;"	d
+F0_CIS_CONTENT_REG_95_64_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2909;"	d
+F0_CIS_CONTENT_REG_95_64_I_MSK	include/ssv6200_aux.h	3772;"	d
+F0_CIS_CONTENT_REG_95_64_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2907;"	d
+F0_CIS_CONTENT_REG_95_64_MSK	include/ssv6200_aux.h	3771;"	d
+F0_CIS_CONTENT_REG_95_64_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2906;"	d
+F0_CIS_CONTENT_REG_95_64_SFT	include/ssv6200_aux.h	3773;"	d
+F0_CIS_CONTENT_REG_95_64_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2908;"	d
+F0_CIS_CONTENT_REG_95_64_SZ	include/ssv6200_aux.h	3775;"	d
+F0_CIS_CONTENT_REG_95_64_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2910;"	d
+F1_BLOCK_SIZE_0_REG_HI	include/ssv6200_aux.h	3599;"	d
+F1_BLOCK_SIZE_0_REG_I_MSK	include/ssv6200_aux.h	3597;"	d
+F1_BLOCK_SIZE_0_REG_MSK	include/ssv6200_aux.h	3596;"	d
+F1_BLOCK_SIZE_0_REG_SFT	include/ssv6200_aux.h	3598;"	d
+F1_BLOCK_SIZE_0_REG_SZ	include/ssv6200_aux.h	3600;"	d
+F1_CIS_CONTENT_REG_127_96_HI	include/ssv6200_aux.h	3859;"	d
+F1_CIS_CONTENT_REG_127_96_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2994;"	d
+F1_CIS_CONTENT_REG_127_96_I_MSK	include/ssv6200_aux.h	3857;"	d
+F1_CIS_CONTENT_REG_127_96_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2992;"	d
+F1_CIS_CONTENT_REG_127_96_MSK	include/ssv6200_aux.h	3856;"	d
+F1_CIS_CONTENT_REG_127_96_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2991;"	d
+F1_CIS_CONTENT_REG_127_96_SFT	include/ssv6200_aux.h	3858;"	d
+F1_CIS_CONTENT_REG_127_96_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2993;"	d
+F1_CIS_CONTENT_REG_127_96_SZ	include/ssv6200_aux.h	3860;"	d
+F1_CIS_CONTENT_REG_127_96_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2995;"	d
+F1_CIS_CONTENT_REG_159_128_HI	include/ssv6200_aux.h	3864;"	d
+F1_CIS_CONTENT_REG_159_128_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2999;"	d
+F1_CIS_CONTENT_REG_159_128_I_MSK	include/ssv6200_aux.h	3862;"	d
+F1_CIS_CONTENT_REG_159_128_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2997;"	d
+F1_CIS_CONTENT_REG_159_128_MSK	include/ssv6200_aux.h	3861;"	d
+F1_CIS_CONTENT_REG_159_128_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2996;"	d
+F1_CIS_CONTENT_REG_159_128_SFT	include/ssv6200_aux.h	3863;"	d
+F1_CIS_CONTENT_REG_159_128_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2998;"	d
+F1_CIS_CONTENT_REG_159_128_SZ	include/ssv6200_aux.h	3865;"	d
+F1_CIS_CONTENT_REG_159_128_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3000;"	d
+F1_CIS_CONTENT_REG_191_160_HI	include/ssv6200_aux.h	3869;"	d
+F1_CIS_CONTENT_REG_191_160_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3004;"	d
+F1_CIS_CONTENT_REG_191_160_I_MSK	include/ssv6200_aux.h	3867;"	d
+F1_CIS_CONTENT_REG_191_160_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3002;"	d
+F1_CIS_CONTENT_REG_191_160_MSK	include/ssv6200_aux.h	3866;"	d
+F1_CIS_CONTENT_REG_191_160_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3001;"	d
+F1_CIS_CONTENT_REG_191_160_SFT	include/ssv6200_aux.h	3868;"	d
+F1_CIS_CONTENT_REG_191_160_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3003;"	d
+F1_CIS_CONTENT_REG_191_160_SZ	include/ssv6200_aux.h	3870;"	d
+F1_CIS_CONTENT_REG_191_160_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3005;"	d
+F1_CIS_CONTENT_REG_223_192_HI	include/ssv6200_aux.h	3874;"	d
+F1_CIS_CONTENT_REG_223_192_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3009;"	d
+F1_CIS_CONTENT_REG_223_192_I_MSK	include/ssv6200_aux.h	3872;"	d
+F1_CIS_CONTENT_REG_223_192_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3007;"	d
+F1_CIS_CONTENT_REG_223_192_MSK	include/ssv6200_aux.h	3871;"	d
+F1_CIS_CONTENT_REG_223_192_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3006;"	d
+F1_CIS_CONTENT_REG_223_192_SFT	include/ssv6200_aux.h	3873;"	d
+F1_CIS_CONTENT_REG_223_192_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3008;"	d
+F1_CIS_CONTENT_REG_223_192_SZ	include/ssv6200_aux.h	3875;"	d
+F1_CIS_CONTENT_REG_223_192_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3010;"	d
+F1_CIS_CONTENT_REG_255_224_HI	include/ssv6200_aux.h	3879;"	d
+F1_CIS_CONTENT_REG_255_224_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3014;"	d
+F1_CIS_CONTENT_REG_255_224_I_MSK	include/ssv6200_aux.h	3877;"	d
+F1_CIS_CONTENT_REG_255_224_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3012;"	d
+F1_CIS_CONTENT_REG_255_224_MSK	include/ssv6200_aux.h	3876;"	d
+F1_CIS_CONTENT_REG_255_224_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3011;"	d
+F1_CIS_CONTENT_REG_255_224_SFT	include/ssv6200_aux.h	3878;"	d
+F1_CIS_CONTENT_REG_255_224_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3013;"	d
+F1_CIS_CONTENT_REG_255_224_SZ	include/ssv6200_aux.h	3880;"	d
+F1_CIS_CONTENT_REG_255_224_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3015;"	d
+F1_CIS_CONTENT_REG_287_256_HI	include/ssv6200_aux.h	3884;"	d
+F1_CIS_CONTENT_REG_287_256_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3019;"	d
+F1_CIS_CONTENT_REG_287_256_I_MSK	include/ssv6200_aux.h	3882;"	d
+F1_CIS_CONTENT_REG_287_256_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3017;"	d
+F1_CIS_CONTENT_REG_287_256_MSK	include/ssv6200_aux.h	3881;"	d
+F1_CIS_CONTENT_REG_287_256_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3016;"	d
+F1_CIS_CONTENT_REG_287_256_SFT	include/ssv6200_aux.h	3883;"	d
+F1_CIS_CONTENT_REG_287_256_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3018;"	d
+F1_CIS_CONTENT_REG_287_256_SZ	include/ssv6200_aux.h	3885;"	d
+F1_CIS_CONTENT_REG_287_256_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3020;"	d
+F1_CIS_CONTENT_REG_319_288_HI	include/ssv6200_aux.h	3889;"	d
+F1_CIS_CONTENT_REG_319_288_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3024;"	d
+F1_CIS_CONTENT_REG_319_288_I_MSK	include/ssv6200_aux.h	3887;"	d
+F1_CIS_CONTENT_REG_319_288_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3022;"	d
+F1_CIS_CONTENT_REG_319_288_MSK	include/ssv6200_aux.h	3886;"	d
+F1_CIS_CONTENT_REG_319_288_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3021;"	d
+F1_CIS_CONTENT_REG_319_288_SFT	include/ssv6200_aux.h	3888;"	d
+F1_CIS_CONTENT_REG_319_288_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3023;"	d
+F1_CIS_CONTENT_REG_319_288_SZ	include/ssv6200_aux.h	3890;"	d
+F1_CIS_CONTENT_REG_319_288_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3025;"	d
+F1_CIS_CONTENT_REG_31_0_HI	include/ssv6200_aux.h	3844;"	d
+F1_CIS_CONTENT_REG_31_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2979;"	d
+F1_CIS_CONTENT_REG_31_0_I_MSK	include/ssv6200_aux.h	3842;"	d
+F1_CIS_CONTENT_REG_31_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2977;"	d
+F1_CIS_CONTENT_REG_31_0_MSK	include/ssv6200_aux.h	3841;"	d
+F1_CIS_CONTENT_REG_31_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2976;"	d
+F1_CIS_CONTENT_REG_31_0_SFT	include/ssv6200_aux.h	3843;"	d
+F1_CIS_CONTENT_REG_31_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2978;"	d
+F1_CIS_CONTENT_REG_31_0_SZ	include/ssv6200_aux.h	3845;"	d
+F1_CIS_CONTENT_REG_31_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2980;"	d
+F1_CIS_CONTENT_REG_351_320_HI	include/ssv6200_aux.h	3894;"	d
+F1_CIS_CONTENT_REG_351_320_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3029;"	d
+F1_CIS_CONTENT_REG_351_320_I_MSK	include/ssv6200_aux.h	3892;"	d
+F1_CIS_CONTENT_REG_351_320_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3027;"	d
+F1_CIS_CONTENT_REG_351_320_MSK	include/ssv6200_aux.h	3891;"	d
+F1_CIS_CONTENT_REG_351_320_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3026;"	d
+F1_CIS_CONTENT_REG_351_320_SFT	include/ssv6200_aux.h	3893;"	d
+F1_CIS_CONTENT_REG_351_320_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3028;"	d
+F1_CIS_CONTENT_REG_351_320_SZ	include/ssv6200_aux.h	3895;"	d
+F1_CIS_CONTENT_REG_351_320_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3030;"	d
+F1_CIS_CONTENT_REG_383_352_HI	include/ssv6200_aux.h	3899;"	d
+F1_CIS_CONTENT_REG_383_352_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3034;"	d
+F1_CIS_CONTENT_REG_383_352_I_MSK	include/ssv6200_aux.h	3897;"	d
+F1_CIS_CONTENT_REG_383_352_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3032;"	d
+F1_CIS_CONTENT_REG_383_352_MSK	include/ssv6200_aux.h	3896;"	d
+F1_CIS_CONTENT_REG_383_352_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3031;"	d
+F1_CIS_CONTENT_REG_383_352_SFT	include/ssv6200_aux.h	3898;"	d
+F1_CIS_CONTENT_REG_383_352_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3033;"	d
+F1_CIS_CONTENT_REG_383_352_SZ	include/ssv6200_aux.h	3900;"	d
+F1_CIS_CONTENT_REG_383_352_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3035;"	d
+F1_CIS_CONTENT_REG_415_384_HI	include/ssv6200_aux.h	3904;"	d
+F1_CIS_CONTENT_REG_415_384_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3039;"	d
+F1_CIS_CONTENT_REG_415_384_I_MSK	include/ssv6200_aux.h	3902;"	d
+F1_CIS_CONTENT_REG_415_384_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3037;"	d
+F1_CIS_CONTENT_REG_415_384_MSK	include/ssv6200_aux.h	3901;"	d
+F1_CIS_CONTENT_REG_415_384_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3036;"	d
+F1_CIS_CONTENT_REG_415_384_SFT	include/ssv6200_aux.h	3903;"	d
+F1_CIS_CONTENT_REG_415_384_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3038;"	d
+F1_CIS_CONTENT_REG_415_384_SZ	include/ssv6200_aux.h	3905;"	d
+F1_CIS_CONTENT_REG_415_384_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3040;"	d
+F1_CIS_CONTENT_REG_447_416_HI	include/ssv6200_aux.h	3909;"	d
+F1_CIS_CONTENT_REG_447_416_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3044;"	d
+F1_CIS_CONTENT_REG_447_416_I_MSK	include/ssv6200_aux.h	3907;"	d
+F1_CIS_CONTENT_REG_447_416_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3042;"	d
+F1_CIS_CONTENT_REG_447_416_MSK	include/ssv6200_aux.h	3906;"	d
+F1_CIS_CONTENT_REG_447_416_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3041;"	d
+F1_CIS_CONTENT_REG_447_416_SFT	include/ssv6200_aux.h	3908;"	d
+F1_CIS_CONTENT_REG_447_416_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3043;"	d
+F1_CIS_CONTENT_REG_447_416_SZ	include/ssv6200_aux.h	3910;"	d
+F1_CIS_CONTENT_REG_447_416_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3045;"	d
+F1_CIS_CONTENT_REG_479_448_HI	include/ssv6200_aux.h	3914;"	d
+F1_CIS_CONTENT_REG_479_448_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3049;"	d
+F1_CIS_CONTENT_REG_479_448_I_MSK	include/ssv6200_aux.h	3912;"	d
+F1_CIS_CONTENT_REG_479_448_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3047;"	d
+F1_CIS_CONTENT_REG_479_448_MSK	include/ssv6200_aux.h	3911;"	d
+F1_CIS_CONTENT_REG_479_448_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3046;"	d
+F1_CIS_CONTENT_REG_479_448_SFT	include/ssv6200_aux.h	3913;"	d
+F1_CIS_CONTENT_REG_479_448_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3048;"	d
+F1_CIS_CONTENT_REG_479_448_SZ	include/ssv6200_aux.h	3915;"	d
+F1_CIS_CONTENT_REG_479_448_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3050;"	d
+F1_CIS_CONTENT_REG_511_480_HI	include/ssv6200_aux.h	3919;"	d
+F1_CIS_CONTENT_REG_511_480_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3054;"	d
+F1_CIS_CONTENT_REG_511_480_I_MSK	include/ssv6200_aux.h	3917;"	d
+F1_CIS_CONTENT_REG_511_480_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3052;"	d
+F1_CIS_CONTENT_REG_511_480_MSK	include/ssv6200_aux.h	3916;"	d
+F1_CIS_CONTENT_REG_511_480_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3051;"	d
+F1_CIS_CONTENT_REG_511_480_SFT	include/ssv6200_aux.h	3918;"	d
+F1_CIS_CONTENT_REG_511_480_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3053;"	d
+F1_CIS_CONTENT_REG_511_480_SZ	include/ssv6200_aux.h	3920;"	d
+F1_CIS_CONTENT_REG_511_480_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3055;"	d
+F1_CIS_CONTENT_REG_63_32_HI	include/ssv6200_aux.h	3849;"	d
+F1_CIS_CONTENT_REG_63_32_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2984;"	d
+F1_CIS_CONTENT_REG_63_32_I_MSK	include/ssv6200_aux.h	3847;"	d
+F1_CIS_CONTENT_REG_63_32_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2982;"	d
+F1_CIS_CONTENT_REG_63_32_MSK	include/ssv6200_aux.h	3846;"	d
+F1_CIS_CONTENT_REG_63_32_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2981;"	d
+F1_CIS_CONTENT_REG_63_32_SFT	include/ssv6200_aux.h	3848;"	d
+F1_CIS_CONTENT_REG_63_32_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2983;"	d
+F1_CIS_CONTENT_REG_63_32_SZ	include/ssv6200_aux.h	3850;"	d
+F1_CIS_CONTENT_REG_63_32_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2985;"	d
+F1_CIS_CONTENT_REG_95_64_HI	include/ssv6200_aux.h	3854;"	d
+F1_CIS_CONTENT_REG_95_64_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2989;"	d
+F1_CIS_CONTENT_REG_95_64_I_MSK	include/ssv6200_aux.h	3852;"	d
+F1_CIS_CONTENT_REG_95_64_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2987;"	d
+F1_CIS_CONTENT_REG_95_64_MSK	include/ssv6200_aux.h	3851;"	d
+F1_CIS_CONTENT_REG_95_64_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2986;"	d
+F1_CIS_CONTENT_REG_95_64_SFT	include/ssv6200_aux.h	3853;"	d
+F1_CIS_CONTENT_REG_95_64_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2988;"	d
+F1_CIS_CONTENT_REG_95_64_SZ	include/ssv6200_aux.h	3855;"	d
+F1_CIS_CONTENT_REG_95_64_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2990;"	d
+FAIL_MAX	smac/dev.c	431;"	d	file:
+FALSE	smac/wapi_sms4.c	/^    FALSE = 0,$/;"	e	enum:__anon7	file:
+FAST_CLK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5999;"	d
+FAST_CLK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5997;"	d
+FAST_CLK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5996;"	d
+FAST_CLK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5998;"	d
+FAST_CLK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6000;"	d
+FBR_100H_REG_HI	include/ssv6200_aux.h	3739;"	d
+FBR_100H_REG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2874;"	d
+FBR_100H_REG_I_MSK	include/ssv6200_aux.h	3737;"	d
+FBR_100H_REG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2872;"	d
+FBR_100H_REG_MSK	include/ssv6200_aux.h	3736;"	d
+FBR_100H_REG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2871;"	d
+FBR_100H_REG_SFT	include/ssv6200_aux.h	3738;"	d
+FBR_100H_REG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2873;"	d
+FBR_100H_REG_SZ	include/ssv6200_aux.h	3740;"	d
+FBR_100H_REG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2875;"	d
+FBR_101H_REG_HI	include/ssv6200_aux.h	3754;"	d
+FBR_101H_REG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2889;"	d
+FBR_101H_REG_I_MSK	include/ssv6200_aux.h	3752;"	d
+FBR_101H_REG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2887;"	d
+FBR_101H_REG_MSK	include/ssv6200_aux.h	3751;"	d
+FBR_101H_REG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2886;"	d
+FBR_101H_REG_SFT	include/ssv6200_aux.h	3753;"	d
+FBR_101H_REG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2888;"	d
+FBR_101H_REG_SZ	include/ssv6200_aux.h	3755;"	d
+FBR_101H_REG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2890;"	d
+FBR_109H_REG_HI	include/ssv6200_aux.h	3759;"	d
+FBR_109H_REG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2894;"	d
+FBR_109H_REG_I_MSK	include/ssv6200_aux.h	3757;"	d
+FBR_109H_REG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2892;"	d
+FBR_109H_REG_MSK	include/ssv6200_aux.h	3756;"	d
+FBR_109H_REG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2891;"	d
+FBR_109H_REG_SFT	include/ssv6200_aux.h	3758;"	d
+FBR_109H_REG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2893;"	d
+FBR_109H_REG_SZ	include/ssv6200_aux.h	3760;"	d
+FBR_109H_REG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2895;"	d
+FBUS_DMAC_BLOCK0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	69;"	d
+FBUS_DMAC_BLOCK0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	67;"	d
+FBUS_DMAC_BLOCK0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	66;"	d
+FBUS_DMAC_BLOCK0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	68;"	d
+FBUS_DMAC_BLOCK0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	70;"	d
+FBUS_DMAC_BLOCK1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	154;"	d
+FBUS_DMAC_BLOCK1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	152;"	d
+FBUS_DMAC_BLOCK1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	151;"	d
+FBUS_DMAC_BLOCK1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	153;"	d
+FBUS_DMAC_BLOCK1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	155;"	d
+FBUS_DMAC_CH0_CLR_ERR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	229;"	d
+FBUS_DMAC_CH0_CLR_ERR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	227;"	d
+FBUS_DMAC_CH0_CLR_ERR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	226;"	d
+FBUS_DMAC_CH0_CLR_ERR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	228;"	d
+FBUS_DMAC_CH0_CLR_ERR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	230;"	d
+FBUS_DMAC_CH0_CLR_TR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	219;"	d
+FBUS_DMAC_CH0_CLR_TR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	217;"	d
+FBUS_DMAC_CH0_CLR_TR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	216;"	d
+FBUS_DMAC_CH0_CLR_TR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	218;"	d
+FBUS_DMAC_CH0_CLR_TR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	220;"	d
+FBUS_DMAC_CH0_PRIOR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	74;"	d
+FBUS_DMAC_CH0_PRIOR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	72;"	d
+FBUS_DMAC_CH0_PRIOR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	71;"	d
+FBUS_DMAC_CH0_PRIOR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	73;"	d
+FBUS_DMAC_CH0_PRIOR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	75;"	d
+FBUS_DMAC_CH1_CLR_ERR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	234;"	d
+FBUS_DMAC_CH1_CLR_ERR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	232;"	d
+FBUS_DMAC_CH1_CLR_ERR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	231;"	d
+FBUS_DMAC_CH1_CLR_ERR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	233;"	d
+FBUS_DMAC_CH1_CLR_ERR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	235;"	d
+FBUS_DMAC_CH1_CLR_TR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	224;"	d
+FBUS_DMAC_CH1_CLR_TR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	222;"	d
+FBUS_DMAC_CH1_CLR_TR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	221;"	d
+FBUS_DMAC_CH1_CLR_TR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	223;"	d
+FBUS_DMAC_CH1_CLR_TR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	225;"	d
+FBUS_DMAC_CH1_PRIOR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	159;"	d
+FBUS_DMAC_CH1_PRIOR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	157;"	d
+FBUS_DMAC_CH1_PRIOR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	156;"	d
+FBUS_DMAC_CH1_PRIOR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	158;"	d
+FBUS_DMAC_CH1_PRIOR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	160;"	d
+FBUS_DMAC_CH_DEMASK_ERR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	214;"	d
+FBUS_DMAC_CH_DEMASK_ERR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	212;"	d
+FBUS_DMAC_CH_DEMASK_ERR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	211;"	d
+FBUS_DMAC_CH_DEMASK_ERR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	213;"	d
+FBUS_DMAC_CH_DEMASK_ERR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	215;"	d
+FBUS_DMAC_CH_DEMASK_TR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	209;"	d
+FBUS_DMAC_CH_DEMASK_TR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	207;"	d
+FBUS_DMAC_CH_DEMASK_TR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	206;"	d
+FBUS_DMAC_CH_DEMASK_TR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	208;"	d
+FBUS_DMAC_CH_DEMASK_TR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	210;"	d
+FBUS_DMAC_CH_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	264;"	d
+FBUS_DMAC_CH_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	262;"	d
+FBUS_DMAC_CH_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	261;"	d
+FBUS_DMAC_CH_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	263;"	d
+FBUS_DMAC_CH_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	265;"	d
+FBUS_DMAC_CH_ERR_TR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	194;"	d
+FBUS_DMAC_CH_ERR_TR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	192;"	d
+FBUS_DMAC_CH_ERR_TR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	191;"	d
+FBUS_DMAC_CH_ERR_TR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	193;"	d
+FBUS_DMAC_CH_ERR_TR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	195;"	d
+FBUS_DMAC_CH_RAW_TR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	189;"	d
+FBUS_DMAC_CH_RAW_TR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	187;"	d
+FBUS_DMAC_CH_RAW_TR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	186;"	d
+FBUS_DMAC_CH_RAW_TR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	188;"	d
+FBUS_DMAC_CH_RAW_TR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	190;"	d
+FBUS_DMAC_CH_STATUSERR_TR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	204;"	d
+FBUS_DMAC_CH_STATUSERR_TR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	202;"	d
+FBUS_DMAC_CH_STATUSERR_TR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	201;"	d
+FBUS_DMAC_CH_STATUSERR_TR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	203;"	d
+FBUS_DMAC_CH_STATUSERR_TR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	205;"	d
+FBUS_DMAC_CH_STATUSTR_TR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	199;"	d
+FBUS_DMAC_CH_STATUSTR_TR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	197;"	d
+FBUS_DMAC_CH_STATUSTR_TR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	196;"	d
+FBUS_DMAC_CH_STATUSTR_TR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	198;"	d
+FBUS_DMAC_CH_STATUSTR_TR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	200;"	d
+FBUS_DMAC_DAR0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24;"	d
+FBUS_DMAC_DAR0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22;"	d
+FBUS_DMAC_DAR0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21;"	d
+FBUS_DMAC_DAR0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23;"	d
+FBUS_DMAC_DAR0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25;"	d
+FBUS_DMAC_DAR1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	109;"	d
+FBUS_DMAC_DAR1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	107;"	d
+FBUS_DMAC_DAR1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	106;"	d
+FBUS_DMAC_DAR1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	108;"	d
+FBUS_DMAC_DAR1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	110;"	d
+FBUS_DMAC_DINC0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	44;"	d
+FBUS_DMAC_DINC0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	42;"	d
+FBUS_DMAC_DINC0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	41;"	d
+FBUS_DMAC_DINC0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	43;"	d
+FBUS_DMAC_DINC0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	45;"	d
+FBUS_DMAC_DINC1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	129;"	d
+FBUS_DMAC_DINC1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	127;"	d
+FBUS_DMAC_DINC1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	126;"	d
+FBUS_DMAC_DINC1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	128;"	d
+FBUS_DMAC_DINC1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	130;"	d
+FBUS_DMAC_DISEN_SHS_DST_REQ_HI	smac/hal/ssv6006c/ssv6006C_aux.h	244;"	d
+FBUS_DMAC_DISEN_SHS_DST_REQ_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	242;"	d
+FBUS_DMAC_DISEN_SHS_DST_REQ_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	241;"	d
+FBUS_DMAC_DISEN_SHS_DST_REQ_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	243;"	d
+FBUS_DMAC_DISEN_SHS_DST_REQ_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	245;"	d
+FBUS_DMAC_DISEN_SHS_DST_SREQ_HI	smac/hal/ssv6006c/ssv6006C_aux.h	254;"	d
+FBUS_DMAC_DISEN_SHS_DST_SREQ_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	252;"	d
+FBUS_DMAC_DISEN_SHS_DST_SREQ_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	251;"	d
+FBUS_DMAC_DISEN_SHS_DST_SREQ_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	253;"	d
+FBUS_DMAC_DISEN_SHS_DST_SREQ_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	255;"	d
+FBUS_DMAC_DISEN_SHS_SRC_REQ_HI	smac/hal/ssv6006c/ssv6006C_aux.h	239;"	d
+FBUS_DMAC_DISEN_SHS_SRC_REQ_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	237;"	d
+FBUS_DMAC_DISEN_SHS_SRC_REQ_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	236;"	d
+FBUS_DMAC_DISEN_SHS_SRC_REQ_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	238;"	d
+FBUS_DMAC_DISEN_SHS_SRC_REQ_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	240;"	d
+FBUS_DMAC_DISEN_SHS_SRC_SREQ_HI	smac/hal/ssv6006c/ssv6006C_aux.h	249;"	d
+FBUS_DMAC_DISEN_SHS_SRC_SREQ_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	247;"	d
+FBUS_DMAC_DISEN_SHS_SRC_SREQ_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	246;"	d
+FBUS_DMAC_DISEN_SHS_SRC_SREQ_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	248;"	d
+FBUS_DMAC_DISEN_SHS_SRC_SREQ_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	250;"	d
+FBUS_DMAC_DST_HS_BUS_SEL0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	99;"	d
+FBUS_DMAC_DST_HS_BUS_SEL0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	97;"	d
+FBUS_DMAC_DST_HS_BUS_SEL0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	96;"	d
+FBUS_DMAC_DST_HS_BUS_SEL0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	98;"	d
+FBUS_DMAC_DST_HS_BUS_SEL0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	100;"	d
+FBUS_DMAC_DST_HS_BUS_SEL1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	184;"	d
+FBUS_DMAC_DST_HS_BUS_SEL1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	182;"	d
+FBUS_DMAC_DST_HS_BUS_SEL1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	181;"	d
+FBUS_DMAC_DST_HS_BUS_SEL1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	183;"	d
+FBUS_DMAC_DST_HS_BUS_SEL1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	185;"	d
+FBUS_DMAC_DST_MSIZE0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	54;"	d
+FBUS_DMAC_DST_MSIZE0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	52;"	d
+FBUS_DMAC_DST_MSIZE0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	51;"	d
+FBUS_DMAC_DST_MSIZE0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	53;"	d
+FBUS_DMAC_DST_MSIZE0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	55;"	d
+FBUS_DMAC_DST_MSIZE1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	139;"	d
+FBUS_DMAC_DST_MSIZE1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	137;"	d
+FBUS_DMAC_DST_MSIZE1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	136;"	d
+FBUS_DMAC_DST_MSIZE1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	138;"	d
+FBUS_DMAC_DST_MSIZE1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	140;"	d
+FBUS_DMAC_DST_TR_WIDTH0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34;"	d
+FBUS_DMAC_DST_TR_WIDTH0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32;"	d
+FBUS_DMAC_DST_TR_WIDTH0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31;"	d
+FBUS_DMAC_DST_TR_WIDTH0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33;"	d
+FBUS_DMAC_DST_TR_WIDTH0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	35;"	d
+FBUS_DMAC_DST_TR_WIDTH1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	119;"	d
+FBUS_DMAC_DST_TR_WIDTH1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	117;"	d
+FBUS_DMAC_DST_TR_WIDTH1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	116;"	d
+FBUS_DMAC_DST_TR_WIDTH1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	118;"	d
+FBUS_DMAC_DST_TR_WIDTH1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	120;"	d
+FBUS_DMAC_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	259;"	d
+FBUS_DMAC_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	257;"	d
+FBUS_DMAC_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	256;"	d
+FBUS_DMAC_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	258;"	d
+FBUS_DMAC_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	260;"	d
+FBUS_DMAC_FC_MODE0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	64;"	d
+FBUS_DMAC_FC_MODE0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	62;"	d
+FBUS_DMAC_FC_MODE0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	61;"	d
+FBUS_DMAC_FC_MODE0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	63;"	d
+FBUS_DMAC_FC_MODE0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	65;"	d
+FBUS_DMAC_FC_MODE1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	149;"	d
+FBUS_DMAC_FC_MODE1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	147;"	d
+FBUS_DMAC_FC_MODE1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	146;"	d
+FBUS_DMAC_FC_MODE1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	148;"	d
+FBUS_DMAC_FC_MODE1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	150;"	d
+FBUS_DMAC_HS_SEL_DST0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	79;"	d
+FBUS_DMAC_HS_SEL_DST0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	77;"	d
+FBUS_DMAC_HS_SEL_DST0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	76;"	d
+FBUS_DMAC_HS_SEL_DST0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	78;"	d
+FBUS_DMAC_HS_SEL_DST0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	80;"	d
+FBUS_DMAC_HS_SEL_DST1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	164;"	d
+FBUS_DMAC_HS_SEL_DST1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	162;"	d
+FBUS_DMAC_HS_SEL_DST1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	161;"	d
+FBUS_DMAC_HS_SEL_DST1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	163;"	d
+FBUS_DMAC_HS_SEL_DST1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	165;"	d
+FBUS_DMAC_HS_SEL_SRC0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	84;"	d
+FBUS_DMAC_HS_SEL_SRC0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	82;"	d
+FBUS_DMAC_HS_SEL_SRC0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	81;"	d
+FBUS_DMAC_HS_SEL_SRC0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	83;"	d
+FBUS_DMAC_HS_SEL_SRC0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	85;"	d
+FBUS_DMAC_HS_SEL_SRC1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	169;"	d
+FBUS_DMAC_HS_SEL_SRC1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	167;"	d
+FBUS_DMAC_HS_SEL_SRC1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	166;"	d
+FBUS_DMAC_HS_SEL_SRC1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	168;"	d
+FBUS_DMAC_HS_SEL_SRC1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	170;"	d
+FBUS_DMAC_INTR_EN0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29;"	d
+FBUS_DMAC_INTR_EN0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27;"	d
+FBUS_DMAC_INTR_EN0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26;"	d
+FBUS_DMAC_INTR_EN0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28;"	d
+FBUS_DMAC_INTR_EN0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30;"	d
+FBUS_DMAC_INTR_EN1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	114;"	d
+FBUS_DMAC_INTR_EN1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	112;"	d
+FBUS_DMAC_INTR_EN1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	111;"	d
+FBUS_DMAC_INTR_EN1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	113;"	d
+FBUS_DMAC_INTR_EN1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	115;"	d
+FBUS_DMAC_MAX_BURST_LEN0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	89;"	d
+FBUS_DMAC_MAX_BURST_LEN0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	87;"	d
+FBUS_DMAC_MAX_BURST_LEN0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	86;"	d
+FBUS_DMAC_MAX_BURST_LEN0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	88;"	d
+FBUS_DMAC_MAX_BURST_LEN0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	90;"	d
+FBUS_DMAC_MAX_BURST_LEN1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	174;"	d
+FBUS_DMAC_MAX_BURST_LEN1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	172;"	d
+FBUS_DMAC_MAX_BURST_LEN1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	171;"	d
+FBUS_DMAC_MAX_BURST_LEN1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	173;"	d
+FBUS_DMAC_MAX_BURST_LEN1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	175;"	d
+FBUS_DMAC_REG_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	77;"	d
+FBUS_DMAC_REG_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	16;"	d
+FBUS_DMAC_SAR0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19;"	d
+FBUS_DMAC_SAR0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17;"	d
+FBUS_DMAC_SAR0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16;"	d
+FBUS_DMAC_SAR0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18;"	d
+FBUS_DMAC_SAR0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20;"	d
+FBUS_DMAC_SAR1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	104;"	d
+FBUS_DMAC_SAR1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	102;"	d
+FBUS_DMAC_SAR1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	101;"	d
+FBUS_DMAC_SAR1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	103;"	d
+FBUS_DMAC_SAR1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	105;"	d
+FBUS_DMAC_SINC0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	49;"	d
+FBUS_DMAC_SINC0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	47;"	d
+FBUS_DMAC_SINC0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	46;"	d
+FBUS_DMAC_SINC0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	48;"	d
+FBUS_DMAC_SINC0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	50;"	d
+FBUS_DMAC_SINC1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	134;"	d
+FBUS_DMAC_SINC1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	132;"	d
+FBUS_DMAC_SINC1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	131;"	d
+FBUS_DMAC_SINC1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	133;"	d
+FBUS_DMAC_SINC1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	135;"	d
+FBUS_DMAC_SRC_HS_BUS_SEL0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	94;"	d
+FBUS_DMAC_SRC_HS_BUS_SEL0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	92;"	d
+FBUS_DMAC_SRC_HS_BUS_SEL0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	91;"	d
+FBUS_DMAC_SRC_HS_BUS_SEL0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	93;"	d
+FBUS_DMAC_SRC_HS_BUS_SEL0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	95;"	d
+FBUS_DMAC_SRC_HS_BUS_SEL1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	179;"	d
+FBUS_DMAC_SRC_HS_BUS_SEL1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	177;"	d
+FBUS_DMAC_SRC_HS_BUS_SEL1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	176;"	d
+FBUS_DMAC_SRC_HS_BUS_SEL1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	178;"	d
+FBUS_DMAC_SRC_HS_BUS_SEL1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	180;"	d
+FBUS_DMAC_SRC_MSIZE0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	59;"	d
+FBUS_DMAC_SRC_MSIZE0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	57;"	d
+FBUS_DMAC_SRC_MSIZE0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	56;"	d
+FBUS_DMAC_SRC_MSIZE0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	58;"	d
+FBUS_DMAC_SRC_MSIZE0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	60;"	d
+FBUS_DMAC_SRC_MSIZE1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	144;"	d
+FBUS_DMAC_SRC_MSIZE1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	142;"	d
+FBUS_DMAC_SRC_MSIZE1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	141;"	d
+FBUS_DMAC_SRC_MSIZE1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	143;"	d
+FBUS_DMAC_SRC_MSIZE1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	145;"	d
+FBUS_DMAC_SRC_TR_WIDTH0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	39;"	d
+FBUS_DMAC_SRC_TR_WIDTH0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	37;"	d
+FBUS_DMAC_SRC_TR_WIDTH0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	36;"	d
+FBUS_DMAC_SRC_TR_WIDTH0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	38;"	d
+FBUS_DMAC_SRC_TR_WIDTH0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	40;"	d
+FBUS_DMAC_SRC_TR_WIDTH1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	124;"	d
+FBUS_DMAC_SRC_TR_WIDTH1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	122;"	d
+FBUS_DMAC_SRC_TR_WIDTH1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	121;"	d
+FBUS_DMAC_SRC_TR_WIDTH1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	123;"	d
+FBUS_DMAC_SRC_TR_WIDTH1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	125;"	d
+FBUS_SRAM_ERRCK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1469;"	d
+FBUS_SRAM_ERRCK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1467;"	d
+FBUS_SRAM_ERRCK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1466;"	d
+FBUS_SRAM_ERRCK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1468;"	d
+FBUS_SRAM_ERRCK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1470;"	d
+FBUS_SRAM_ERR_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1494;"	d
+FBUS_SRAM_ERR_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1492;"	d
+FBUS_SRAM_ERR_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1491;"	d
+FBUS_SRAM_ERR_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1493;"	d
+FBUS_SRAM_ERR_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1495;"	d
+FENCE_HIT_ADR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1449;"	d
+FENCE_HIT_ADR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1447;"	d
+FENCE_HIT_ADR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1446;"	d
+FENCE_HIT_ADR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1448;"	d
+FENCE_HIT_ADR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1450;"	d
+FENCE_HIT_CLR_HI	include/ssv6200_aux.h	464;"	d
+FENCE_HIT_CLR_I_MSK	include/ssv6200_aux.h	462;"	d
+FENCE_HIT_CLR_MSK	include/ssv6200_aux.h	461;"	d
+FENCE_HIT_CLR_SFT	include/ssv6200_aux.h	463;"	d
+FENCE_HIT_CLR_SZ	include/ssv6200_aux.h	465;"	d
+FENCE_HIT_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1474;"	d
+FENCE_HIT_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1472;"	d
+FENCE_HIT_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1471;"	d
+FENCE_HIT_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1473;"	d
+FENCE_HIT_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1475;"	d
+FENCE_HIT_INT_HI	include/ssv6200_aux.h	474;"	d
+FENCE_HIT_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1499;"	d
+FENCE_HIT_INT_I_MSK	include/ssv6200_aux.h	472;"	d
+FENCE_HIT_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1497;"	d
+FENCE_HIT_INT_MSK	include/ssv6200_aux.h	471;"	d
+FENCE_HIT_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1496;"	d
+FENCE_HIT_INT_SFT	include/ssv6200_aux.h	473;"	d
+FENCE_HIT_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1498;"	d
+FENCE_HIT_INT_SZ	include/ssv6200_aux.h	475;"	d
+FENCE_HIT_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1500;"	d
+FF0_CNT_HI	include/ssv6200_aux.h	11459;"	d
+FF0_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33029;"	d
+FF0_CNT_I_MSK	include/ssv6200_aux.h	11457;"	d
+FF0_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33027;"	d
+FF0_CNT_MSK	include/ssv6200_aux.h	11456;"	d
+FF0_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33026;"	d
+FF0_CNT_SFT	include/ssv6200_aux.h	11458;"	d
+FF0_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33028;"	d
+FF0_CNT_SZ	include/ssv6200_aux.h	11460;"	d
+FF0_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33030;"	d
+FF0_EMPTY_HI	include/ssv6200_aux.h	11429;"	d
+FF0_EMPTY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32989;"	d
+FF0_EMPTY_I_MSK	include/ssv6200_aux.h	11427;"	d
+FF0_EMPTY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32987;"	d
+FF0_EMPTY_MSK	include/ssv6200_aux.h	11426;"	d
+FF0_EMPTY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32986;"	d
+FF0_EMPTY_SFT	include/ssv6200_aux.h	11428;"	d
+FF0_EMPTY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32988;"	d
+FF0_EMPTY_SZ	include/ssv6200_aux.h	11430;"	d
+FF0_EMPTY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32990;"	d
+FF10_CNT_HI	include/ssv6200_aux.h	11499;"	d
+FF10_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33069;"	d
+FF10_CNT_I_MSK	include/ssv6200_aux.h	11497;"	d
+FF10_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33067;"	d
+FF10_CNT_MSK	include/ssv6200_aux.h	11496;"	d
+FF10_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33066;"	d
+FF10_CNT_SFT	include/ssv6200_aux.h	11498;"	d
+FF10_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33068;"	d
+FF10_CNT_SZ	include/ssv6200_aux.h	11500;"	d
+FF10_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33070;"	d
+FF11_CNT_HI	include/ssv6200_aux.h	11504;"	d
+FF11_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33074;"	d
+FF11_CNT_I_MSK	include/ssv6200_aux.h	11502;"	d
+FF11_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33072;"	d
+FF11_CNT_MSK	include/ssv6200_aux.h	11501;"	d
+FF11_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33071;"	d
+FF11_CNT_SFT	include/ssv6200_aux.h	11503;"	d
+FF11_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33073;"	d
+FF11_CNT_SZ	include/ssv6200_aux.h	11505;"	d
+FF11_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33075;"	d
+FF12_CNT_HI	include/ssv6200_aux.h	11509;"	d
+FF12_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33079;"	d
+FF12_CNT_I_MSK	include/ssv6200_aux.h	11507;"	d
+FF12_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33077;"	d
+FF12_CNT_MSK	include/ssv6200_aux.h	11506;"	d
+FF12_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33076;"	d
+FF12_CNT_SFT	include/ssv6200_aux.h	11508;"	d
+FF12_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33078;"	d
+FF12_CNT_SZ	include/ssv6200_aux.h	11510;"	d
+FF12_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33080;"	d
+FF13_CNT_HI	include/ssv6200_aux.h	11514;"	d
+FF13_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33084;"	d
+FF13_CNT_I_MSK	include/ssv6200_aux.h	11512;"	d
+FF13_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33082;"	d
+FF13_CNT_MSK	include/ssv6200_aux.h	11511;"	d
+FF13_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33081;"	d
+FF13_CNT_SFT	include/ssv6200_aux.h	11513;"	d
+FF13_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33083;"	d
+FF13_CNT_SZ	include/ssv6200_aux.h	11515;"	d
+FF13_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33085;"	d
+FF14_CNT_HI	include/ssv6200_aux.h	11519;"	d
+FF14_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33089;"	d
+FF14_CNT_I_MSK	include/ssv6200_aux.h	11517;"	d
+FF14_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33087;"	d
+FF14_CNT_MSK	include/ssv6200_aux.h	11516;"	d
+FF14_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33086;"	d
+FF14_CNT_SFT	include/ssv6200_aux.h	11518;"	d
+FF14_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33088;"	d
+FF14_CNT_SZ	include/ssv6200_aux.h	11520;"	d
+FF14_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33090;"	d
+FF15_CNT_HI	include/ssv6200_aux.h	11524;"	d
+FF15_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33094;"	d
+FF15_CNT_I_MSK	include/ssv6200_aux.h	11522;"	d
+FF15_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33092;"	d
+FF15_CNT_MSK	include/ssv6200_aux.h	11521;"	d
+FF15_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33091;"	d
+FF15_CNT_SFT	include/ssv6200_aux.h	11523;"	d
+FF15_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33093;"	d
+FF15_CNT_SZ	include/ssv6200_aux.h	11525;"	d
+FF15_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33095;"	d
+FF1_CNT_HI	include/ssv6200_aux.h	11464;"	d
+FF1_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33034;"	d
+FF1_CNT_I_MSK	include/ssv6200_aux.h	11462;"	d
+FF1_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33032;"	d
+FF1_CNT_MSK	include/ssv6200_aux.h	11461;"	d
+FF1_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33031;"	d
+FF1_CNT_SFT	include/ssv6200_aux.h	11463;"	d
+FF1_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33033;"	d
+FF1_CNT_SZ	include/ssv6200_aux.h	11465;"	d
+FF1_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33035;"	d
+FF2_CNT_HI	include/ssv6200_aux.h	11534;"	d
+FF2_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33104;"	d
+FF2_CNT_I_MSK	include/ssv6200_aux.h	11532;"	d
+FF2_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33102;"	d
+FF2_CNT_MSK	include/ssv6200_aux.h	11531;"	d
+FF2_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33101;"	d
+FF2_CNT_SFT	include/ssv6200_aux.h	11533;"	d
+FF2_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33103;"	d
+FF2_CNT_SZ	include/ssv6200_aux.h	11535;"	d
+FF2_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33105;"	d
+FF2_EMPTY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32999;"	d
+FF2_EMPTY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32997;"	d
+FF2_EMPTY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32996;"	d
+FF2_EMPTY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32998;"	d
+FF2_EMPTY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33000;"	d
+FF3_CNT_HI	include/ssv6200_aux.h	11469;"	d
+FF3_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33039;"	d
+FF3_CNT_I_MSK	include/ssv6200_aux.h	11467;"	d
+FF3_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33037;"	d
+FF3_CNT_MSK	include/ssv6200_aux.h	11466;"	d
+FF3_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33036;"	d
+FF3_CNT_SFT	include/ssv6200_aux.h	11468;"	d
+FF3_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33038;"	d
+FF3_CNT_SZ	include/ssv6200_aux.h	11470;"	d
+FF3_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33040;"	d
+FF4_CNT_HI	include/ssv6200_aux.h	11529;"	d
+FF4_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33099;"	d
+FF4_CNT_I_MSK	include/ssv6200_aux.h	11527;"	d
+FF4_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33097;"	d
+FF4_CNT_MSK	include/ssv6200_aux.h	11526;"	d
+FF4_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33096;"	d
+FF4_CNT_SFT	include/ssv6200_aux.h	11528;"	d
+FF4_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33098;"	d
+FF4_CNT_SZ	include/ssv6200_aux.h	11530;"	d
+FF4_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33100;"	d
+FF5_CNT_HI	include/ssv6200_aux.h	11474;"	d
+FF5_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33044;"	d
+FF5_CNT_I_MSK	include/ssv6200_aux.h	11472;"	d
+FF5_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33042;"	d
+FF5_CNT_MSK	include/ssv6200_aux.h	11471;"	d
+FF5_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33041;"	d
+FF5_CNT_SFT	include/ssv6200_aux.h	11473;"	d
+FF5_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33043;"	d
+FF5_CNT_SZ	include/ssv6200_aux.h	11475;"	d
+FF5_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33045;"	d
+FF6_CNT_HI	include/ssv6200_aux.h	11479;"	d
+FF6_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33049;"	d
+FF6_CNT_I_MSK	include/ssv6200_aux.h	11477;"	d
+FF6_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33047;"	d
+FF6_CNT_MSK	include/ssv6200_aux.h	11476;"	d
+FF6_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33046;"	d
+FF6_CNT_SFT	include/ssv6200_aux.h	11478;"	d
+FF6_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33048;"	d
+FF6_CNT_SZ	include/ssv6200_aux.h	11480;"	d
+FF6_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33050;"	d
+FF7_CNT_HI	include/ssv6200_aux.h	11484;"	d
+FF7_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33054;"	d
+FF7_CNT_I_MSK	include/ssv6200_aux.h	11482;"	d
+FF7_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33052;"	d
+FF7_CNT_MSK	include/ssv6200_aux.h	11481;"	d
+FF7_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33051;"	d
+FF7_CNT_SFT	include/ssv6200_aux.h	11483;"	d
+FF7_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33053;"	d
+FF7_CNT_SZ	include/ssv6200_aux.h	11485;"	d
+FF7_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33055;"	d
+FF8_CNT_HI	include/ssv6200_aux.h	11489;"	d
+FF8_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33059;"	d
+FF8_CNT_I_MSK	include/ssv6200_aux.h	11487;"	d
+FF8_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33057;"	d
+FF8_CNT_MSK	include/ssv6200_aux.h	11486;"	d
+FF8_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33056;"	d
+FF8_CNT_SFT	include/ssv6200_aux.h	11488;"	d
+FF8_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33058;"	d
+FF8_CNT_SZ	include/ssv6200_aux.h	11490;"	d
+FF8_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33060;"	d
+FF9_CNT_HI	include/ssv6200_aux.h	11494;"	d
+FF9_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33064;"	d
+FF9_CNT_I_MSK	include/ssv6200_aux.h	11492;"	d
+FF9_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33062;"	d
+FF9_CNT_MSK	include/ssv6200_aux.h	11491;"	d
+FF9_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33061;"	d
+FF9_CNT_SFT	include/ssv6200_aux.h	11493;"	d
+FF9_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33063;"	d
+FF9_CNT_SZ	include/ssv6200_aux.h	11495;"	d
+FF9_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33065;"	d
+FFO0_CNT_HI	include/ssv6200_aux.h	12004;"	d
+FFO0_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33594;"	d
+FFO0_CNT_I_MSK	include/ssv6200_aux.h	12002;"	d
+FFO0_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33592;"	d
+FFO0_CNT_MSK	include/ssv6200_aux.h	12001;"	d
+FFO0_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33591;"	d
+FFO0_CNT_SFT	include/ssv6200_aux.h	12003;"	d
+FFO0_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33593;"	d
+FFO0_CNT_SZ	include/ssv6200_aux.h	12005;"	d
+FFO0_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33595;"	d
+FFO10_CNT_HI	include/ssv6200_aux.h	12054;"	d
+FFO10_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33644;"	d
+FFO10_CNT_I_MSK	include/ssv6200_aux.h	12052;"	d
+FFO10_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33642;"	d
+FFO10_CNT_MSK	include/ssv6200_aux.h	12051;"	d
+FFO10_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33641;"	d
+FFO10_CNT_SFT	include/ssv6200_aux.h	12053;"	d
+FFO10_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33643;"	d
+FFO10_CNT_SZ	include/ssv6200_aux.h	12055;"	d
+FFO10_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33645;"	d
+FFO11_CNT_HI	include/ssv6200_aux.h	12059;"	d
+FFO11_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33649;"	d
+FFO11_CNT_I_MSK	include/ssv6200_aux.h	12057;"	d
+FFO11_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33647;"	d
+FFO11_CNT_MSK	include/ssv6200_aux.h	12056;"	d
+FFO11_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33646;"	d
+FFO11_CNT_SFT	include/ssv6200_aux.h	12058;"	d
+FFO11_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33648;"	d
+FFO11_CNT_SZ	include/ssv6200_aux.h	12060;"	d
+FFO11_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33650;"	d
+FFO12_CNT_HI	include/ssv6200_aux.h	12064;"	d
+FFO12_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33654;"	d
+FFO12_CNT_I_MSK	include/ssv6200_aux.h	12062;"	d
+FFO12_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33652;"	d
+FFO12_CNT_MSK	include/ssv6200_aux.h	12061;"	d
+FFO12_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33651;"	d
+FFO12_CNT_SFT	include/ssv6200_aux.h	12063;"	d
+FFO12_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33653;"	d
+FFO12_CNT_SZ	include/ssv6200_aux.h	12065;"	d
+FFO12_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33655;"	d
+FFO13_CNT_HI	include/ssv6200_aux.h	12069;"	d
+FFO13_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33659;"	d
+FFO13_CNT_I_MSK	include/ssv6200_aux.h	12067;"	d
+FFO13_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33657;"	d
+FFO13_CNT_MSK	include/ssv6200_aux.h	12066;"	d
+FFO13_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33656;"	d
+FFO13_CNT_SFT	include/ssv6200_aux.h	12068;"	d
+FFO13_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33658;"	d
+FFO13_CNT_SZ	include/ssv6200_aux.h	12070;"	d
+FFO13_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33660;"	d
+FFO14_CNT_HI	include/ssv6200_aux.h	12074;"	d
+FFO14_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33664;"	d
+FFO14_CNT_I_MSK	include/ssv6200_aux.h	12072;"	d
+FFO14_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33662;"	d
+FFO14_CNT_MSK	include/ssv6200_aux.h	12071;"	d
+FFO14_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33661;"	d
+FFO14_CNT_SFT	include/ssv6200_aux.h	12073;"	d
+FFO14_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33663;"	d
+FFO14_CNT_SZ	include/ssv6200_aux.h	12075;"	d
+FFO14_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33665;"	d
+FFO15_CNT_HI	include/ssv6200_aux.h	12079;"	d
+FFO15_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33669;"	d
+FFO15_CNT_I_MSK	include/ssv6200_aux.h	12077;"	d
+FFO15_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33667;"	d
+FFO15_CNT_MSK	include/ssv6200_aux.h	12076;"	d
+FFO15_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33666;"	d
+FFO15_CNT_SFT	include/ssv6200_aux.h	12078;"	d
+FFO15_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33668;"	d
+FFO15_CNT_SZ	include/ssv6200_aux.h	12080;"	d
+FFO15_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33670;"	d
+FFO1_CNT_HI	include/ssv6200_aux.h	12009;"	d
+FFO1_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33599;"	d
+FFO1_CNT_I_MSK	include/ssv6200_aux.h	12007;"	d
+FFO1_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33597;"	d
+FFO1_CNT_MSK	include/ssv6200_aux.h	12006;"	d
+FFO1_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33596;"	d
+FFO1_CNT_SFT	include/ssv6200_aux.h	12008;"	d
+FFO1_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33598;"	d
+FFO1_CNT_SZ	include/ssv6200_aux.h	12010;"	d
+FFO1_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33600;"	d
+FFO2_CNT_HI	include/ssv6200_aux.h	12014;"	d
+FFO2_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33604;"	d
+FFO2_CNT_I_MSK	include/ssv6200_aux.h	12012;"	d
+FFO2_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33602;"	d
+FFO2_CNT_MSK	include/ssv6200_aux.h	12011;"	d
+FFO2_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33601;"	d
+FFO2_CNT_SFT	include/ssv6200_aux.h	12013;"	d
+FFO2_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33603;"	d
+FFO2_CNT_SZ	include/ssv6200_aux.h	12015;"	d
+FFO2_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33605;"	d
+FFO3_CNT_HI	include/ssv6200_aux.h	12019;"	d
+FFO3_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33609;"	d
+FFO3_CNT_I_MSK	include/ssv6200_aux.h	12017;"	d
+FFO3_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33607;"	d
+FFO3_CNT_MSK	include/ssv6200_aux.h	12016;"	d
+FFO3_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33606;"	d
+FFO3_CNT_SFT	include/ssv6200_aux.h	12018;"	d
+FFO3_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33608;"	d
+FFO3_CNT_SZ	include/ssv6200_aux.h	12020;"	d
+FFO3_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33610;"	d
+FFO4_CNT_HI	include/ssv6200_aux.h	12024;"	d
+FFO4_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33614;"	d
+FFO4_CNT_I_MSK	include/ssv6200_aux.h	12022;"	d
+FFO4_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33612;"	d
+FFO4_CNT_MSK	include/ssv6200_aux.h	12021;"	d
+FFO4_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33611;"	d
+FFO4_CNT_SFT	include/ssv6200_aux.h	12023;"	d
+FFO4_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33613;"	d
+FFO4_CNT_SZ	include/ssv6200_aux.h	12025;"	d
+FFO4_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33615;"	d
+FFO5_CNT_HI	include/ssv6200_aux.h	12029;"	d
+FFO5_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33619;"	d
+FFO5_CNT_I_MSK	include/ssv6200_aux.h	12027;"	d
+FFO5_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33617;"	d
+FFO5_CNT_MSK	include/ssv6200_aux.h	12026;"	d
+FFO5_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33616;"	d
+FFO5_CNT_SFT	include/ssv6200_aux.h	12028;"	d
+FFO5_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33618;"	d
+FFO5_CNT_SZ	include/ssv6200_aux.h	12030;"	d
+FFO5_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33620;"	d
+FFO6_CNT_HI	include/ssv6200_aux.h	12034;"	d
+FFO6_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33624;"	d
+FFO6_CNT_I_MSK	include/ssv6200_aux.h	12032;"	d
+FFO6_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33622;"	d
+FFO6_CNT_MSK	include/ssv6200_aux.h	12031;"	d
+FFO6_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33621;"	d
+FFO6_CNT_SFT	include/ssv6200_aux.h	12033;"	d
+FFO6_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33623;"	d
+FFO6_CNT_SZ	include/ssv6200_aux.h	12035;"	d
+FFO6_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33625;"	d
+FFO7_CNT_HI	include/ssv6200_aux.h	12039;"	d
+FFO7_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33629;"	d
+FFO7_CNT_I_MSK	include/ssv6200_aux.h	12037;"	d
+FFO7_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33627;"	d
+FFO7_CNT_MSK	include/ssv6200_aux.h	12036;"	d
+FFO7_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33626;"	d
+FFO7_CNT_SFT	include/ssv6200_aux.h	12038;"	d
+FFO7_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33628;"	d
+FFO7_CNT_SZ	include/ssv6200_aux.h	12040;"	d
+FFO7_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33630;"	d
+FFO8_CNT_HI	include/ssv6200_aux.h	12044;"	d
+FFO8_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33634;"	d
+FFO8_CNT_I_MSK	include/ssv6200_aux.h	12042;"	d
+FFO8_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33632;"	d
+FFO8_CNT_MSK	include/ssv6200_aux.h	12041;"	d
+FFO8_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33631;"	d
+FFO8_CNT_SFT	include/ssv6200_aux.h	12043;"	d
+FFO8_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33633;"	d
+FFO8_CNT_SZ	include/ssv6200_aux.h	12045;"	d
+FFO8_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33635;"	d
+FFO9_CNT_HI	include/ssv6200_aux.h	12049;"	d
+FFO9_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33639;"	d
+FFO9_CNT_I_MSK	include/ssv6200_aux.h	12047;"	d
+FFO9_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33637;"	d
+FFO9_CNT_MSK	include/ssv6200_aux.h	12046;"	d
+FFO9_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33636;"	d
+FFO9_CNT_SFT	include/ssv6200_aux.h	12048;"	d
+FFO9_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33638;"	d
+FFO9_CNT_SZ	include/ssv6200_aux.h	12050;"	d
+FFO9_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33640;"	d
+FIFODATA_ERR_HI	include/ssv6200_aux.h	4424;"	d
+FIFODATA_ERR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3534;"	d
+FIFODATA_ERR_I_MSK	include/ssv6200_aux.h	4422;"	d
+FIFODATA_ERR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3532;"	d
+FIFODATA_ERR_MSK	include/ssv6200_aux.h	4421;"	d
+FIFODATA_ERR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3531;"	d
+FIFODATA_ERR_SFT	include/ssv6200_aux.h	4423;"	d
+FIFODATA_ERR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3533;"	d
+FIFODATA_ERR_SZ	include/ssv6200_aux.h	4425;"	d
+FIFODATA_ERR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3535;"	d
+FIFOS_ENABLED_HI	include/ssv6200_aux.h	4489;"	d
+FIFOS_ENABLED_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3609;"	d
+FIFOS_ENABLED_I_MSK	include/ssv6200_aux.h	4487;"	d
+FIFOS_ENABLED_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3607;"	d
+FIFOS_ENABLED_MSK	include/ssv6200_aux.h	4486;"	d
+FIFOS_ENABLED_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3606;"	d
+FIFOS_ENABLED_SFT	include/ssv6200_aux.h	4488;"	d
+FIFOS_ENABLED_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3608;"	d
+FIFOS_ENABLED_SZ	include/ssv6200_aux.h	4490;"	d
+FIFOS_ENABLED_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3610;"	d
+FIFO_EN_HI	include/ssv6200_aux.h	4294;"	d
+FIFO_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3399;"	d
+FIFO_EN_I_MSK	include/ssv6200_aux.h	4292;"	d
+FIFO_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3397;"	d
+FIFO_EN_MSK	include/ssv6200_aux.h	4291;"	d
+FIFO_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3396;"	d
+FIFO_EN_SFT	include/ssv6200_aux.h	4293;"	d
+FIFO_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3398;"	d
+FIFO_EN_SZ	include/ssv6200_aux.h	4295;"	d
+FIFO_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3400;"	d
+FIF_PROBE_REQ	smac/linux_2_6_35.h	33;"	d
+FILE_DEVICE_SSVSDIO	bridge/sdiobridge_pub.h	38;"	d
+FILE_DEVICE_SSVSDIO	hci_wrapper/ssv_huw.h	32;"	d
+FILE_DEVICE_SSVSDIO_NAME	bridge/sdiobridge_pub.h	40;"	d
+FILE_DEVICE_SSVSDIO_NAME	hci_wrapper/ssv_huw.h	34;"	d
+FILE_DEVICE_SSVSDIO_SEQ	bridge/sdiobridge_pub.h	39;"	d
+FILE_DEVICE_SSVSDIO_SEQ	hci_wrapper/ssv_huw.h	33;"	d
+FIQ_RAW_HI	include/ssv6200_aux.h	4904;"	d
+FIQ_RAW_I_MSK	include/ssv6200_aux.h	4902;"	d
+FIQ_RAW_MSK	include/ssv6200_aux.h	4901;"	d
+FIQ_RAW_SFT	include/ssv6200_aux.h	4903;"	d
+FIQ_RAW_SZ	include/ssv6200_aux.h	4905;"	d
+FIQ_STATUS_HI	include/ssv6200_aux.h	4894;"	d
+FIQ_STATUS_I_MSK	include/ssv6200_aux.h	4892;"	d
+FIQ_STATUS_MSK	include/ssv6200_aux.h	4891;"	d
+FIQ_STATUS_SFT	include/ssv6200_aux.h	4893;"	d
+FIQ_STATUS_SZ	include/ssv6200_aux.h	4895;"	d
+FIRMWARE_DOWNLOAD	hwif/usb/usb.h	21;"	d
+FIRWARE_NOT_MATCH_CODE	include/ssv6xxx_common.h	20;"	d
+FK_PARAMETER_0	smac/wapi_sms4.c	34;"	d	file:
+FK_PARAMETER_1	smac/wapi_sms4.c	35;"	d	file:
+FK_PARAMETER_2	smac/wapi_sms4.c	36;"	d	file:
+FK_PARAMETER_3	smac/wapi_sms4.c	37;"	d	file:
+FK_Parameter	smac/wapi_sms4.c	/^static const u32 FK_Parameter[] = { FK_PARAMETER_0, FK_PARAMETER_1, FK_PARAMETER_2, FK_PARAMETER_3 };$/;"	v	file:
+FLASH_ADDR_HI	include/ssv6200_aux.h	5669;"	d
+FLASH_ADDR_I_MSK	include/ssv6200_aux.h	5667;"	d
+FLASH_ADDR_MSK	include/ssv6200_aux.h	5666;"	d
+FLASH_ADDR_SFT	include/ssv6200_aux.h	5668;"	d
+FLASH_ADDR_SZ	include/ssv6200_aux.h	5670;"	d
+FLASH_BACK_DLY_HI	include/ssv6200_aux.h	5709;"	d
+FLASH_BACK_DLY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4019;"	d
+FLASH_BACK_DLY_I_MSK	include/ssv6200_aux.h	5707;"	d
+FLASH_BACK_DLY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4017;"	d
+FLASH_BACK_DLY_MSK	include/ssv6200_aux.h	5706;"	d
+FLASH_BACK_DLY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4016;"	d
+FLASH_BACK_DLY_SFT	include/ssv6200_aux.h	5708;"	d
+FLASH_BACK_DLY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4018;"	d
+FLASH_BACK_DLY_SZ	include/ssv6200_aux.h	5710;"	d
+FLASH_BACK_DLY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4020;"	d
+FLASH_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1149;"	d
+FLASH_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1147;"	d
+FLASH_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1146;"	d
+FLASH_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1148;"	d
+FLASH_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1150;"	d
+FLASH_CLK_WIDTH_HI	include/ssv6200_aux.h	5714;"	d
+FLASH_CLK_WIDTH_I_MSK	include/ssv6200_aux.h	5712;"	d
+FLASH_CLK_WIDTH_MSK	include/ssv6200_aux.h	5711;"	d
+FLASH_CLK_WIDTH_SFT	include/ssv6200_aux.h	5713;"	d
+FLASH_CLK_WIDTH_SZ	include/ssv6200_aux.h	5715;"	d
+FLASH_CMD_CLR_HI	include/ssv6200_aux.h	5674;"	d
+FLASH_CMD_CLR_I_MSK	include/ssv6200_aux.h	5672;"	d
+FLASH_CMD_CLR_MSK	include/ssv6200_aux.h	5671;"	d
+FLASH_CMD_CLR_SFT	include/ssv6200_aux.h	5673;"	d
+FLASH_CMD_CLR_SZ	include/ssv6200_aux.h	5675;"	d
+FLASH_DMA_CLR_HI	include/ssv6200_aux.h	5679;"	d
+FLASH_DMA_CLR_I_MSK	include/ssv6200_aux.h	5677;"	d
+FLASH_DMA_CLR_MSK	include/ssv6200_aux.h	5676;"	d
+FLASH_DMA_CLR_SFT	include/ssv6200_aux.h	5678;"	d
+FLASH_DMA_CLR_SZ	include/ssv6200_aux.h	5680;"	d
+FLASH_DMA_LEN_HI	include/ssv6200_aux.h	5699;"	d
+FLASH_DMA_LEN_I_MSK	include/ssv6200_aux.h	5697;"	d
+FLASH_DMA_LEN_MSK	include/ssv6200_aux.h	5696;"	d
+FLASH_DMA_LEN_SFT	include/ssv6200_aux.h	5698;"	d
+FLASH_DMA_LEN_SZ	include/ssv6200_aux.h	5700;"	d
+FLASH_FRONT_DLY_HI	include/ssv6200_aux.h	5704;"	d
+FLASH_FRONT_DLY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4014;"	d
+FLASH_FRONT_DLY_I_MSK	include/ssv6200_aux.h	5702;"	d
+FLASH_FRONT_DLY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4012;"	d
+FLASH_FRONT_DLY_MSK	include/ssv6200_aux.h	5701;"	d
+FLASH_FRONT_DLY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4011;"	d
+FLASH_FRONT_DLY_SFT	include/ssv6200_aux.h	5703;"	d
+FLASH_FRONT_DLY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4013;"	d
+FLASH_FRONT_DLY_SZ	include/ssv6200_aux.h	5705;"	d
+FLASH_FRONT_DLY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4015;"	d
+FLASH_SPI_REG_BANK_SIZE	include/ssv6200_reg.h	85;"	d
+FLASH_SPI_REG_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	102;"	d
+FLASH_SPI_REG_BASE	include/ssv6200_reg.h	36;"	d
+FLASH_SPI_REG_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	41;"	d
+FLS_CLK_IN_DLY_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4109;"	d
+FLS_CLK_IN_DLY_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4107;"	d
+FLS_CLK_IN_DLY_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4106;"	d
+FLS_CLK_IN_DLY_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4108;"	d
+FLS_CLK_IN_DLY_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4110;"	d
+FLS_CLK_OUT_DLY_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4114;"	d
+FLS_CLK_OUT_DLY_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4112;"	d
+FLS_CLK_OUT_DLY_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4111;"	d
+FLS_CLK_OUT_DLY_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4113;"	d
+FLS_CLK_OUT_DLY_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4115;"	d
+FLS_MISO_IN_DLY_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4129;"	d
+FLS_MISO_IN_DLY_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4127;"	d
+FLS_MISO_IN_DLY_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4126;"	d
+FLS_MISO_IN_DLY_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4128;"	d
+FLS_MISO_IN_DLY_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4130;"	d
+FLS_MISO_OUT_DLY_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4134;"	d
+FLS_MISO_OUT_DLY_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4132;"	d
+FLS_MISO_OUT_DLY_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4131;"	d
+FLS_MISO_OUT_DLY_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4133;"	d
+FLS_MISO_OUT_DLY_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4135;"	d
+FLS_MOSI_IN_DLY_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4119;"	d
+FLS_MOSI_IN_DLY_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4117;"	d
+FLS_MOSI_IN_DLY_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4116;"	d
+FLS_MOSI_IN_DLY_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4118;"	d
+FLS_MOSI_IN_DLY_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4120;"	d
+FLS_MOSI_OUT_DLY_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4124;"	d
+FLS_MOSI_OUT_DLY_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4122;"	d
+FLS_MOSI_OUT_DLY_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4121;"	d
+FLS_MOSI_OUT_DLY_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4123;"	d
+FLS_MOSI_OUT_DLY_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4125;"	d
+FLS_NC_IN_DLY_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4149;"	d
+FLS_NC_IN_DLY_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4147;"	d
+FLS_NC_IN_DLY_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4146;"	d
+FLS_NC_IN_DLY_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4148;"	d
+FLS_NC_IN_DLY_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4150;"	d
+FLS_NC_OUT_DLY_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4154;"	d
+FLS_NC_OUT_DLY_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4152;"	d
+FLS_NC_OUT_DLY_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4151;"	d
+FLS_NC_OUT_DLY_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4153;"	d
+FLS_NC_OUT_DLY_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4155;"	d
+FLS_REMAP_HI	include/ssv6200_aux.h	5724;"	d
+FLS_REMAP_I_MSK	include/ssv6200_aux.h	5722;"	d
+FLS_REMAP_MSK	include/ssv6200_aux.h	5721;"	d
+FLS_REMAP_SFT	include/ssv6200_aux.h	5723;"	d
+FLS_REMAP_SZ	include/ssv6200_aux.h	5725;"	d
+FLS_WP_IN_DLY_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4139;"	d
+FLS_WP_IN_DLY_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4137;"	d
+FLS_WP_IN_DLY_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4136;"	d
+FLS_WP_IN_DLY_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4138;"	d
+FLS_WP_IN_DLY_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4140;"	d
+FLS_WP_OUT_DLY_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4144;"	d
+FLS_WP_OUT_DLY_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4142;"	d
+FLS_WP_OUT_DLY_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4141;"	d
+FLS_WP_OUT_DLY_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4143;"	d
+FLS_WP_OUT_DLY_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4145;"	d
+FN1_DMA_RD_START_ADDR_REG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2769;"	d
+FN1_DMA_RD_START_ADDR_REG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2767;"	d
+FN1_DMA_RD_START_ADDR_REG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2766;"	d
+FN1_DMA_RD_START_ADDR_REG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2768;"	d
+FN1_DMA_RD_START_ADDR_REG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2770;"	d
+FN1_DMA_START_ADDR_REG_HI	include/ssv6200_aux.h	3384;"	d
+FN1_DMA_START_ADDR_REG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2729;"	d
+FN1_DMA_START_ADDR_REG_I_MSK	include/ssv6200_aux.h	3382;"	d
+FN1_DMA_START_ADDR_REG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2727;"	d
+FN1_DMA_START_ADDR_REG_MSK	include/ssv6200_aux.h	3381;"	d
+FN1_DMA_START_ADDR_REG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2726;"	d
+FN1_DMA_START_ADDR_REG_SFT	include/ssv6200_aux.h	3383;"	d
+FN1_DMA_START_ADDR_REG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2728;"	d
+FN1_DMA_START_ADDR_REG_SZ	include/ssv6200_aux.h	3385;"	d
+FN1_DMA_START_ADDR_REG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2730;"	d
+FORCE_GET_RK_HI	include/ssv6200_aux.h	6694;"	d
+FORCE_GET_RK_I_MSK	include/ssv6200_aux.h	6692;"	d
+FORCE_GET_RK_MSK	include/ssv6200_aux.h	6691;"	d
+FORCE_GET_RK_SFT	include/ssv6200_aux.h	6693;"	d
+FORCE_GET_RK_SZ	include/ssv6200_aux.h	6695;"	d
+FORCE_PARITY_HI	include/ssv6200_aux.h	4349;"	d
+FORCE_PARITY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3454;"	d
+FORCE_PARITY_I_MSK	include/ssv6200_aux.h	4347;"	d
+FORCE_PARITY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3452;"	d
+FORCE_PARITY_MSK	include/ssv6200_aux.h	4346;"	d
+FORCE_PARITY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3451;"	d
+FORCE_PARITY_SFT	include/ssv6200_aux.h	4348;"	d
+FORCE_PARITY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3453;"	d
+FORCE_PARITY_SZ	include/ssv6200_aux.h	4350;"	d
+FORCE_PARITY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3455;"	d
+FPGA_PHY_4	smac/hal/ssv6006c/ssv6006_mac.h	19;"	d
+FPGA_PHY_5	smac/hal/ssv6006c/ssv6006_mac.h	18;"	d
+FPGA_TO_GEMINIA_ADC_EDGE_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34664;"	d
+FPGA_TO_GEMINIA_ADC_EDGE_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34662;"	d
+FPGA_TO_GEMINIA_ADC_EDGE_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34661;"	d
+FPGA_TO_GEMINIA_ADC_EDGE_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34663;"	d
+FPGA_TO_GEMINIA_ADC_EDGE_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34665;"	d
+FPGA_TO_GEMINIA_DAC_EDGE_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34659;"	d
+FPGA_TO_GEMINIA_DAC_EDGE_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34657;"	d
+FPGA_TO_GEMINIA_DAC_EDGE_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34656;"	d
+FPGA_TO_GEMINIA_DAC_EDGE_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34658;"	d
+FPGA_TO_GEMINIA_DAC_EDGE_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34660;"	d
+FPGA_TO_GEMINIA_DAC_SIGN_SWAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34654;"	d
+FPGA_TO_GEMINIA_DAC_SIGN_SWAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34652;"	d
+FPGA_TO_GEMINIA_DAC_SIGN_SWAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34651;"	d
+FPGA_TO_GEMINIA_DAC_SIGN_SWAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34653;"	d
+FPGA_TO_GEMINIA_DAC_SIGN_SWAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34655;"	d
+FRAME_ACCEPT	smac/dev_tbl.h	34;"	d
+FRAME_DROP	smac/dev_tbl.h	35;"	d
+FRAME_LEN_HI	include/ssv6200_aux.h	6464;"	d
+FRAME_LEN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5709;"	d
+FRAME_LEN_I_MSK	include/ssv6200_aux.h	6462;"	d
+FRAME_LEN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5707;"	d
+FRAME_LEN_MSK	include/ssv6200_aux.h	6461;"	d
+FRAME_LEN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5706;"	d
+FRAME_LEN_SFT	include/ssv6200_aux.h	6463;"	d
+FRAME_LEN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5708;"	d
+FRAME_LEN_SZ	include/ssv6200_aux.h	6465;"	d
+FRAME_LEN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5710;"	d
+FRAMING_ERR_HI	include/ssv6200_aux.h	4404;"	d
+FRAMING_ERR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3514;"	d
+FRAMING_ERR_I_MSK	include/ssv6200_aux.h	4402;"	d
+FRAMING_ERR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3512;"	d
+FRAMING_ERR_MSK	include/ssv6200_aux.h	4401;"	d
+FRAMING_ERR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3511;"	d
+FRAMING_ERR_SFT	include/ssv6200_aux.h	4403;"	d
+FRAMING_ERR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3513;"	d
+FRAMING_ERR_SZ	include/ssv6200_aux.h	4405;"	d
+FRAMING_ERR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3515;"	d
+FRAMING_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3654;"	d
+FRAMING_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3652;"	d
+FRAMING_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3651;"	d
+FRAMING_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3653;"	d
+FRAMING_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3655;"	d
+FRIMWARE_COMPILERDATE	include/ssv_firmware_version.h	21;"	d
+FRIMWARE_COMPILERHOST	include/ssv_firmware_version.h	20;"	d
+FRIMWARE_COMPILEROS	include/ssv_firmware_version.h	22;"	d
+FRIMWARE_COMPILEROSARCH	include/ssv_firmware_version.h	23;"	d
+FRM_CTRL_HI	include/ssv6200_aux.h	7374;"	d
+FRM_CTRL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6474;"	d
+FRM_CTRL_I_MSK	include/ssv6200_aux.h	7372;"	d
+FRM_CTRL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6472;"	d
+FRM_CTRL_MSK	include/ssv6200_aux.h	7371;"	d
+FRM_CTRL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6471;"	d
+FRM_CTRL_SFT	include/ssv6200_aux.h	7373;"	d
+FRM_CTRL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6473;"	d
+FRM_CTRL_SZ	include/ssv6200_aux.h	7375;"	d
+FRM_CTRL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6475;"	d
+FRONT_DLY_HI	include/ssv6200_aux.h	3969;"	d
+FRONT_DLY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3084;"	d
+FRONT_DLY_I_MSK	include/ssv6200_aux.h	3967;"	d
+FRONT_DLY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3082;"	d
+FRONT_DLY_MSK	include/ssv6200_aux.h	3966;"	d
+FRONT_DLY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3081;"	d
+FRONT_DLY_SFT	include/ssv6200_aux.h	3968;"	d
+FRONT_DLY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3083;"	d
+FRONT_DLY_SZ	include/ssv6200_aux.h	3970;"	d
+FRONT_DLY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3085;"	d
+FSM_SYSCTRL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1419;"	d
+FSM_SYSCTRL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1417;"	d
+FSM_SYSCTRL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1416;"	d
+FSM_SYSCTRL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1418;"	d
+FSM_SYSCTRL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1420;"	d
+FUNC_HOP	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	/^typedef void (* FUNC_HOP)(int nchannel);$/;"	t
+FUNC_NOTIFY	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	/^typedef void (* FUNC_NOTIFY)(tx_wifi_sync_param *pwifi_sync_param, void *puserdata);$/;"	t
+FW_BLOCK_SIZE	include/ssv6xxx_common.h	385;"	d
+FW_CHECKSUM_INIT	include/ssv6xxx_common.h	387;"	d
+FW_EVENT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1564;"	d
+FW_EVENT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1562;"	d
+FW_EVENT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1561;"	d
+FW_EVENT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1563;"	d
+FW_EVENT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1565;"	d
+FW_START_ADDR	hwif/usb/usb.h	20;"	d
+FW_START_SRAM_ADDR	include/ssv6xxx_common.h	384;"	d
+FW_STATUS_MASK	include/ssv6xxx_common.h	388;"	d
+FW_VERSION_REG	include/ssv6200_common.h	19;"	d
+FW_VERSION_REG	smac/hal/ssv6006c/ssv6006_common.h	19;"	d
+G0_PKT_CLS_MIB_EN_HI	include/ssv6200_aux.h	9344;"	d
+G0_PKT_CLS_MIB_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9179;"	d
+G0_PKT_CLS_MIB_EN_I_MSK	include/ssv6200_aux.h	9342;"	d
+G0_PKT_CLS_MIB_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9177;"	d
+G0_PKT_CLS_MIB_EN_MSK	include/ssv6200_aux.h	9341;"	d
+G0_PKT_CLS_MIB_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9176;"	d
+G0_PKT_CLS_MIB_EN_SFT	include/ssv6200_aux.h	9343;"	d
+G0_PKT_CLS_MIB_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9178;"	d
+G0_PKT_CLS_MIB_EN_SZ	include/ssv6200_aux.h	9345;"	d
+G0_PKT_CLS_MIB_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9180;"	d
+G0_PKT_CLS_ONGOING_HI	include/ssv6200_aux.h	9349;"	d
+G0_PKT_CLS_ONGOING_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9184;"	d
+G0_PKT_CLS_ONGOING_I_MSK	include/ssv6200_aux.h	9347;"	d
+G0_PKT_CLS_ONGOING_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9182;"	d
+G0_PKT_CLS_ONGOING_MSK	include/ssv6200_aux.h	9346;"	d
+G0_PKT_CLS_ONGOING_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9181;"	d
+G0_PKT_CLS_ONGOING_SFT	include/ssv6200_aux.h	9348;"	d
+G0_PKT_CLS_ONGOING_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9183;"	d
+G0_PKT_CLS_ONGOING_SZ	include/ssv6200_aux.h	9350;"	d
+G0_PKT_CLS_ONGOING_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9185;"	d
+G1_PKT_CLS_MIB_EN_HI	include/ssv6200_aux.h	9354;"	d
+G1_PKT_CLS_MIB_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9189;"	d
+G1_PKT_CLS_MIB_EN_I_MSK	include/ssv6200_aux.h	9352;"	d
+G1_PKT_CLS_MIB_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9187;"	d
+G1_PKT_CLS_MIB_EN_MSK	include/ssv6200_aux.h	9351;"	d
+G1_PKT_CLS_MIB_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9186;"	d
+G1_PKT_CLS_MIB_EN_SFT	include/ssv6200_aux.h	9353;"	d
+G1_PKT_CLS_MIB_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9188;"	d
+G1_PKT_CLS_MIB_EN_SZ	include/ssv6200_aux.h	9355;"	d
+G1_PKT_CLS_MIB_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9190;"	d
+G1_PKT_CLS_ONGOING_HI	include/ssv6200_aux.h	9359;"	d
+G1_PKT_CLS_ONGOING_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9194;"	d
+G1_PKT_CLS_ONGOING_I_MSK	include/ssv6200_aux.h	9357;"	d
+G1_PKT_CLS_ONGOING_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9192;"	d
+G1_PKT_CLS_ONGOING_MSK	include/ssv6200_aux.h	9356;"	d
+G1_PKT_CLS_ONGOING_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9191;"	d
+G1_PKT_CLS_ONGOING_SFT	include/ssv6200_aux.h	9358;"	d
+G1_PKT_CLS_ONGOING_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9193;"	d
+G1_PKT_CLS_ONGOING_SZ	include/ssv6200_aux.h	9360;"	d
+G1_PKT_CLS_ONGOING_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9195;"	d
+GEMINIA_SAR_ADC_FSM_RDY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13419;"	d
+GEMINIA_SAR_ADC_FSM_RDY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13417;"	d
+GEMINIA_SAR_ADC_FSM_RDY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13416;"	d
+GEMINIA_SAR_ADC_FSM_RDY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13418;"	d
+GEMINIA_SAR_ADC_FSM_RDY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13420;"	d
+GENLMSG_DATA	smartlink/ssv_smartlink.c	64;"	d	file:
+GENLMSG_PAYLOAD	smartlink/ssv_smartlink.c	65;"	d	file:
+GET_ABT_SW_RST_N	include/ssv6200_reg.h	4806;"	d
+GET_ACC_RD_LEN	include/ssv6200_reg.h	4832;"	d
+GET_ACC_WR_LEN	include/ssv6200_reg.h	4831;"	d
+GET_ACK_GEN_DUR	include/ssv6200_reg.h	2706;"	d
+GET_ACK_GEN_DUR	smac/hal/ssv6006c/ssv6006C_reg.h	3430;"	d
+GET_ACK_GEN_EN	include/ssv6200_reg.h	2704;"	d
+GET_ACK_GEN_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3428;"	d
+GET_ACK_GEN_INFO	include/ssv6200_reg.h	2707;"	d
+GET_ACK_GEN_INFO	smac/hal/ssv6006c/ssv6006C_reg.h	3431;"	d
+GET_ACK_GEN_RA_31_0	include/ssv6200_reg.h	2708;"	d
+GET_ACK_GEN_RA_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	3432;"	d
+GET_ACK_GEN_RA_47_32	include/ssv6200_reg.h	2709;"	d
+GET_ACK_GEN_RA_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	3433;"	d
+GET_ADDR1A_SEL	include/ssv6200_reg.h	2730;"	d
+GET_ADDR1A_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	3439;"	d
+GET_ADDR1B_SEL	include/ssv6200_reg.h	2733;"	d
+GET_ADDR1B_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	3442;"	d
+GET_ADDR2A_SEL	include/ssv6200_reg.h	2731;"	d
+GET_ADDR2A_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	3440;"	d
+GET_ADDR2B_SEL	include/ssv6200_reg.h	2734;"	d
+GET_ADDR2B_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	3443;"	d
+GET_ADDR3A_SEL	include/ssv6200_reg.h	2732;"	d
+GET_ADDR3A_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	3441;"	d
+GET_ADDR3B_SEL	include/ssv6200_reg.h	2735;"	d
+GET_ADDR3B_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	3444;"	d
+GET_ADDR3C_SEL	include/ssv6200_reg.h	2736;"	d
+GET_ADDR3C_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	3445;"	d
+GET_ADD_LEN	include/ssv6200_reg.h	2531;"	d
+GET_ADD_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	3269;"	d
+GET_AD_CIRCUIT_VERSION	include/ssv6200_reg.h	4782;"	d
+GET_AD_DP_VT_MON_Q	include/ssv6200_reg.h	4778;"	d
+GET_AD_SX_VT_MON_Q	include/ssv6200_reg.h	4777;"	d
+GET_AHB2PKT_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2400;"	d
+GET_AHB_BRIDGE_RESET	include/ssv6200_reg.h	1945;"	d
+GET_AHB_BRIDGE_RESET	smac/hal/ssv6006c/ssv6006C_reg.h	2703;"	d
+GET_AHB_ERR_RST	include/ssv6200_reg.h	1328;"	d
+GET_AHB_FEN_ADDR	include/ssv6200_reg.h	1353;"	d
+GET_AHB_HANG2	include/ssv6200_reg.h	1965;"	d
+GET_AHB_HANG4	include/ssv6200_reg.h	1912;"	d
+GET_AHB_ILL_ADDR	include/ssv6200_reg.h	1352;"	d
+GET_AHB_STATUS	include/ssv6200_reg.h	1335;"	d
+GET_AHB_SW_RST	include/ssv6200_reg.h	1327;"	d
+GET_ALC_ABT_CLR	smac/hal/ssv6006c/ssv6006C_reg.h	9045;"	d
+GET_ALC_ABT_ID	include/ssv6200_reg.h	4838;"	d
+GET_ALC_ABT_ID	smac/hal/ssv6006c/ssv6006C_reg.h	9043;"	d
+GET_ALC_ABT_INT	include/ssv6200_reg.h	4839;"	d
+GET_ALC_ABT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	9044;"	d
+GET_ALC_BUSY	include/ssv6200_reg.h	3780;"	d
+GET_ALC_BUSY	smac/hal/ssv6006c/ssv6006C_reg.h	8963;"	d
+GET_ALC_ERR	include/ssv6200_reg.h	4845;"	d
+GET_ALC_ERR_CLR	smac/hal/ssv6006c/ssv6006C_reg.h	9048;"	d
+GET_ALC_ERR_ID	include/ssv6200_reg.h	4849;"	d
+GET_ALC_ERR_ID	smac/hal/ssv6006c/ssv6006C_reg.h	9052;"	d
+GET_ALC_ERR_STS	smac/hal/ssv6006c/ssv6006C_reg.h	9046;"	d
+GET_ALC_FAIL	include/ssv6200_reg.h	3779;"	d
+GET_ALC_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	8962;"	d
+GET_ALC_INT_ID	include/ssv6200_reg.h	3785;"	d
+GET_ALC_INT_ID	smac/hal/ssv6006c/ssv6006C_reg.h	8968;"	d
+GET_ALC_LENG	include/ssv6200_reg.h	3756;"	d
+GET_ALC_LENG	smac/hal/ssv6006c/ssv6006C_reg.h	8939;"	d
+GET_ALC_NOCHG_ID	include/ssv6200_reg.h	4887;"	d
+GET_ALC_NOCHG_INT	include/ssv6200_reg.h	4888;"	d
+GET_ALC_TIMEOUT	include/ssv6200_reg.h	3786;"	d
+GET_ALC_TIMEOUT	smac/hal/ssv6006c/ssv6006C_reg.h	8969;"	d
+GET_ALC_TIMEOUT_INT	include/ssv6200_reg.h	3788;"	d
+GET_ALC_TIMEOUT_INT	smac/hal/ssv6006c/ssv6006C_reg.h	8971;"	d
+GET_ALC_TIMEOUT_INT_EN	include/ssv6200_reg.h	3787;"	d
+GET_ALC_TIMEOUT_INT_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8970;"	d
+GET_ALLOCATESTATUS	include/ssv6200_reg.h	1969;"	d
+GET_ALLOCATE_STATUS	include/ssv6200_reg.h	1909;"	d
+GET_ALLOCATE_STATUS2	include/ssv6200_reg.h	1961;"	d
+GET_ALLOW_SD_RESET	include/ssv6200_reg.h	1385;"	d
+GET_ALLOW_SD_SPI_RESET	smac/hal/ssv6006c/ssv6006C_reg.h	2485;"	d
+GET_ALL_ID_ALC_LEN	include/ssv6200_reg.h	3812;"	d
+GET_ALL_ID_ALC_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	8995;"	d
+GET_ALL_ID_LEN_THOLD	include/ssv6200_reg.h	2268;"	d
+GET_ALL_ID_LEN_THOLD_INT	include/ssv6200_reg.h	3806;"	d
+GET_ALL_ID_LEN_THOLD_INT	smac/hal/ssv6006c/ssv6006C_reg.h	8989;"	d
+GET_ALL_ID_LEN_THOLD_SD	include/ssv6200_reg.h	2337;"	d
+GET_ALL_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	2366;"	d
+GET_ALR_ABT_NOCHG_INT_IRQ	include/ssv6200_reg.h	2274;"	d
+GET_ALR_ABT_NOCHG_INT_IRQ_SD	include/ssv6200_reg.h	2343;"	d
+GET_ALR_SW_RST_N	include/ssv6200_reg.h	4803;"	d
+GET_AL_STATE	include/ssv6200_reg.h	4847;"	d
+GET_AL_STATE	smac/hal/ssv6006c/ssv6006C_reg.h	9050;"	d
+GET_AMPDU_CLK_EN	include/ssv6200_reg.h	3064;"	d
+GET_AMPDU_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3896;"	d
+GET_AMPDU_CSR_CLK_EN	include/ssv6200_reg.h	3083;"	d
+GET_AMPDU_CSR_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3915;"	d
+GET_AMPDU_CSR_RST	include/ssv6200_reg.h	3055;"	d
+GET_AMPDU_CSR_RST	smac/hal/ssv6006c/ssv6006C_reg.h	3887;"	d
+GET_AMPDU_ENG_CLK_EN	include/ssv6200_reg.h	3076;"	d
+GET_AMPDU_ENG_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3908;"	d
+GET_AMPDU_ENG_RST	include/ssv6200_reg.h	3041;"	d
+GET_AMPDU_ENG_RST	smac/hal/ssv6006c/ssv6006C_reg.h	3873;"	d
+GET_AMPDU_SIG	include/ssv6200_reg.h	2739;"	d
+GET_AMPDU_SIG	smac/hal/ssv6006c/ssv6006C_reg.h	3459;"	d
+GET_AMPDU_SNIFFER	include/ssv6200_reg.h	3094;"	d
+GET_AMPDU_SNIFFER	smac/hal/ssv6006c/ssv6006C_reg.h	3926;"	d
+GET_AMPDU_SW_RST	include/ssv6200_reg.h	3029;"	d
+GET_AMPDU_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	3861;"	d
+GET_ASIC_TAG	include/ssv6200_reg.h	3021;"	d
+GET_AUTO_CSN	smac/hal/ssv6006c/ssv6006C_reg.h	3352;"	d
+GET_AUTO_REMAIN	smac/hal/ssv6006c/ssv6006C_reg.h	3977;"	d
+GET_AUTO_SEQNO	include/ssv6200_reg.h	2475;"	d
+GET_AUTO_SEQNO	smac/hal/ssv6006c/ssv6006C_reg.h	3174;"	d
+GET_AVA_TAG	include/ssv6200_reg.h	4859;"	d
+GET_AVA_TAG	smac/hal/ssv6006c/ssv6006C_reg.h	9060;"	d
+GET_BACKUP_PG_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	3210;"	d
+GET_BACK_DLY	include/ssv6200_reg.h	2055;"	d
+GET_BACK_DLY	smac/hal/ssv6006c/ssv6006C_reg.h	2767;"	d
+GET_BA_AGRE_EN	include/ssv6200_reg.h	2696;"	d
+GET_BA_AGRE_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3420;"	d
+GET_BA_CTRL	include/ssv6200_reg.h	2694;"	d
+GET_BA_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	3418;"	d
+GET_BA_DBG_EN	include/ssv6200_reg.h	2695;"	d
+GET_BA_DBG_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3419;"	d
+GET_BA_GEN_EN	include/ssv6200_reg.h	2705;"	d
+GET_BA_GEN_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3429;"	d
+GET_BA_HW_ID	smac/hal/ssv6006c/ssv6006C_reg.h	3454;"	d
+GET_BA_H_QUEUE_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3451;"	d
+GET_BA_SB0	include/ssv6200_reg.h	2701;"	d
+GET_BA_SB0	smac/hal/ssv6006c/ssv6006C_reg.h	3425;"	d
+GET_BA_SB1	include/ssv6200_reg.h	2702;"	d
+GET_BA_SB1	smac/hal/ssv6006c/ssv6006C_reg.h	3426;"	d
+GET_BA_ST_SEQ	include/ssv6200_reg.h	2700;"	d
+GET_BA_ST_SEQ	smac/hal/ssv6006c/ssv6006C_reg.h	3424;"	d
+GET_BA_TA_31_0	include/ssv6200_reg.h	2697;"	d
+GET_BA_TA_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	3421;"	d
+GET_BA_TA_47_32	include/ssv6200_reg.h	2698;"	d
+GET_BA_TA_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	3422;"	d
+GET_BA_TID	include/ssv6200_reg.h	2699;"	d
+GET_BA_TID	smac/hal/ssv6006c/ssv6006C_reg.h	3423;"	d
+GET_BCAST_RATEUNKNOW	include/ssv6200_reg.h	3007;"	d
+GET_BEACON_TIMEOUT	include/ssv6200_reg.h	3121;"	d
+GET_BEACON_TIMEOUT	smac/hal/ssv6006c/ssv6006C_reg.h	3960;"	d
+GET_BEACON_TIMEOUT_EN	include/ssv6200_reg.h	3112;"	d
+GET_BEACON_TIMEOUT_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3951;"	d
+GET_BIST_CLK_EN	include/ssv6200_reg.h	1320;"	d
+GET_BIT1_RD_CMD	smac/hal/ssv6006c/ssv6006C_reg.h	2969;"	d
+GET_BIT1_WR_CMD	smac/hal/ssv6006c/ssv6006C_reg.h	2968;"	d
+GET_BIT2_RD_CMD	smac/hal/ssv6006c/ssv6006C_reg.h	2970;"	d
+GET_BIT4_RD_CMD	smac/hal/ssv6006c/ssv6006C_reg.h	2971;"	d
+GET_BIT4_WR_CMD	smac/hal/ssv6006c/ssv6006C_reg.h	2972;"	d
+GET_BIT_MODE1	include/ssv6200_reg.h	2409;"	d
+GET_BIT_MODE2	include/ssv6200_reg.h	2410;"	d
+GET_BIT_MODE4	include/ssv6200_reg.h	2411;"	d
+GET_BLOCK_TXQ	smac/hal/ssv6006c/ssv6006C_reg.h	3516;"	d
+GET_BOOT_ADDR	include/ssv6200_reg.h	2393;"	d
+GET_BOOT_CHECK_SUM	include/ssv6200_reg.h	2412;"	d
+GET_BRDC_DIV	include/ssv6200_reg.h	2156;"	d
+GET_BRDC_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	2867;"	d
+GET_BREAK	smac/hal/ssv6006c/ssv6006C_reg.h	2883;"	d
+GET_BREAK_INT	include/ssv6200_reg.h	2144;"	d
+GET_BREAK_INT	smac/hal/ssv6006c/ssv6006C_reg.h	2855;"	d
+GET_BRST_MODE	include/ssv6200_reg.h	2052;"	d
+GET_BSS	include/ssv6200_reg.h	2009;"	d
+GET_BSS	smac/hal/ssv6006c/ssv6006C_reg.h	2725;"	d
+GET_BSSID1_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	3940;"	d
+GET_BSSID1_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	3941;"	d
+GET_BSSID_31_0	include/ssv6200_reg.h	3097;"	d
+GET_BSSID_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	3931;"	d
+GET_BSSID_47_32	include/ssv6200_reg.h	3098;"	d
+GET_BSSID_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	3932;"	d
+GET_BTCX_CLK_EN	include/ssv6200_reg.h	1310;"	d
+GET_BTCX_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2389;"	d
+GET_BTCX_CSR_CLK_EN	include/ssv6200_reg.h	1322;"	d
+GET_BTCX_CSR_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2413;"	d
+GET_BTCX_INTR	smac/hal/ssv6006c/ssv6006C_reg.h	3976;"	d
+GET_BTCX_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	3975;"	d
+GET_BTCX_SW_RST	include/ssv6200_reg.h	1276;"	d
+GET_BTCX_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	2356;"	d
+GET_BT_BUSY	smac/hal/ssv6006c/ssv6006C_reg.h	3626;"	d
+GET_BT_BUSY_MANUAL_EN	include/ssv6200_reg.h	3129;"	d
+GET_BT_BUSY_MANUAL_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3968;"	d
+GET_BT_BUSY_SET	include/ssv6200_reg.h	3130;"	d
+GET_BT_BUSY_SET	smac/hal/ssv6006c/ssv6006C_reg.h	3969;"	d
+GET_BT_PRI_SMP_TIME	include/ssv6200_reg.h	3119;"	d
+GET_BT_PRI_SMP_TIME	smac/hal/ssv6006c/ssv6006C_reg.h	3958;"	d
+GET_BT_STA_SMP_TIME	include/ssv6200_reg.h	3120;"	d
+GET_BT_STA_SMP_TIME	smac/hal/ssv6006c/ssv6006C_reg.h	3959;"	d
+GET_BT_SW_O_C	include/ssv6200_reg.h	1460;"	d
+GET_BT_SW_O_OE	include/ssv6200_reg.h	1454;"	d
+GET_BT_SW_O_PE	include/ssv6200_reg.h	1455;"	d
+GET_BT_SW_POL	include/ssv6200_reg.h	3118;"	d
+GET_BT_SW_POL	smac/hal/ssv6006c/ssv6006C_reg.h	3957;"	d
+GET_BT_TRX_SMP_TIME	smac/hal/ssv6006c/ssv6006C_reg.h	3974;"	d
+GET_BT_TXBAR_MANUAL_EN	include/ssv6200_reg.h	3127;"	d
+GET_BT_TXBAR_MANUAL_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3966;"	d
+GET_BT_TXBAR_SET	include/ssv6200_reg.h	3128;"	d
+GET_BT_TXBAR_SET	smac/hal/ssv6006c/ssv6006C_reg.h	3967;"	d
+GET_BYPASSS_TX_PARSER_ENCAP	include/ssv6200_reg.h	2476;"	d
+GET_BYPASS_TX_PARSER_ENCAP	smac/hal/ssv6006c/ssv6006C_reg.h	3175;"	d
+GET_B_CCA_CNT	include/ssv6200_reg.h	4186;"	d
+GET_B_FREQ_OS	include/ssv6200_reg.h	4178;"	d
+GET_B_LENGTH_FIELD	include/ssv6200_reg.h	4187;"	d
+GET_B_PACKET_CNT	include/ssv6200_reg.h	4185;"	d
+GET_B_PACKET_ERR_CNT	include/ssv6200_reg.h	4183;"	d
+GET_B_RCPI	include/ssv6200_reg.h	4180;"	d
+GET_B_SERVICE_FIELD	include/ssv6200_reg.h	4190;"	d
+GET_B_SNR	include/ssv6200_reg.h	4179;"	d
+GET_CALCULATE	include/ssv6200_reg.h	2534;"	d
+GET_CALCULATE	smac/hal/ssv6006c/ssv6006C_reg.h	3272;"	d
+GET_CARD_FW_DL_STATUS	include/ssv6200_reg.h	1898;"	d
+GET_CARD_RCA_REG	include/ssv6200_reg.h	1915;"	d
+GET_CARD_RCA_REG	smac/hal/ssv6006c/ssv6006C_reg.h	2680;"	d
+GET_CBR_AD_DP_VT_MON_Q	include/ssv6200_reg.h	3506;"	d
+GET_CBR_AD_SX_VT_MON_Q	include/ssv6200_reg.h	3505;"	d
+GET_CBR_CH_RDY	include/ssv6200_reg.h	3503;"	d
+GET_CBR_DATA_OUT_SEL	include/ssv6200_reg.h	3536;"	d
+GET_CBR_DA_DP_BBPLL_BS	include/ssv6200_reg.h	3509;"	d
+GET_CBR_DA_LCK_RDY	include/ssv6200_reg.h	3500;"	d
+GET_CBR_DA_R_CAL_CODE	include/ssv6200_reg.h	3507;"	d
+GET_CBR_DA_R_CODE_LUT	include/ssv6200_reg.h	3504;"	d
+GET_CBR_DA_SX_SUB_SEL	include/ssv6200_reg.h	3508;"	d
+GET_CBR_DBG_EN	include/ssv6200_reg.h	3532;"	d
+GET_CBR_DBG_SEL	include/ssv6200_reg.h	3531;"	d
+GET_CBR_DP_VT_MON_RDY	include/ssv6200_reg.h	3502;"	d
+GET_CBR_FREQ_SEL	include/ssv6200_reg.h	3538;"	d
+GET_CBR_IDEAL_IQ_EN	include/ssv6200_reg.h	3535;"	d
+GET_CBR_IFS_TIME	include/ssv6200_reg.h	3512;"	d
+GET_CBR_INTP_SEL	include/ssv6200_reg.h	3527;"	d
+GET_CBR_IQ_SCALE	include/ssv6200_reg.h	3539;"	d
+GET_CBR_IQ_SWP	include/ssv6200_reg.h	3528;"	d
+GET_CBR_LENGTH_TARGET	include/ssv6200_reg.h	3513;"	d
+GET_CBR_PLCP_BYTE_LENGTH	include/ssv6200_reg.h	3518;"	d
+GET_CBR_PLCP_PSDU_DATA_MEM	include/ssv6200_reg.h	3516;"	d
+GET_CBR_PLCP_PSDU_PREAMBLE_SHORT	include/ssv6200_reg.h	3517;"	d
+GET_CBR_PLCP_PSDU_RATE	include/ssv6200_reg.h	3519;"	d
+GET_CBR_RCAL_RDY	include/ssv6200_reg.h	3499;"	d
+GET_CBR_RG_ADC_CLKSEL	include/ssv6200_reg.h	3338;"	d
+GET_CBR_RG_ADC_DIBIAS	include/ssv6200_reg.h	3339;"	d
+GET_CBR_RG_ADC_DIVR	include/ssv6200_reg.h	3340;"	d
+GET_CBR_RG_ADC_DVCMI	include/ssv6200_reg.h	3341;"	d
+GET_CBR_RG_ADC_SAMSEL	include/ssv6200_reg.h	3342;"	d
+GET_CBR_RG_ADC_STNBY	include/ssv6200_reg.h	3343;"	d
+GET_CBR_RG_ADC_TESTMODE	include/ssv6200_reg.h	3344;"	d
+GET_CBR_RG_ADC_TSEL	include/ssv6200_reg.h	3345;"	d
+GET_CBR_RG_ADC_VRSEL	include/ssv6200_reg.h	3346;"	d
+GET_CBR_RG_BUCK_LEVEL	include/ssv6200_reg.h	3255;"	d
+GET_CBR_RG_DACI1ST	include/ssv6200_reg.h	3349;"	d
+GET_CBR_RG_DCDC_MODE	include/ssv6200_reg.h	3245;"	d
+GET_CBR_RG_DICMP	include/ssv6200_reg.h	3347;"	d
+GET_CBR_RG_DIOP	include/ssv6200_reg.h	3348;"	d
+GET_CBR_RG_DIS_DA_OFFSET	include/ssv6200_reg.h	3530;"	d
+GET_CBR_RG_DP_BBPLL_BP	include/ssv6200_reg.h	3443;"	d
+GET_CBR_RG_DP_BBPLL_BS_CWD	include/ssv6200_reg.h	3498;"	d
+GET_CBR_RG_DP_BBPLL_BS_CWR	include/ssv6200_reg.h	3497;"	d
+GET_CBR_RG_DP_BBPLL_ICP	include/ssv6200_reg.h	3444;"	d
+GET_CBR_RG_DP_BBPLL_IDUAL	include/ssv6200_reg.h	3445;"	d
+GET_CBR_RG_DP_BBPLL_OD_TEST	include/ssv6200_reg.h	3446;"	d
+GET_CBR_RG_DP_BBPLL_PD	include/ssv6200_reg.h	3447;"	d
+GET_CBR_RG_DP_BBPLL_PFD_DLY	include/ssv6200_reg.h	3449;"	d
+GET_CBR_RG_DP_BBPLL_TESTSEL	include/ssv6200_reg.h	3448;"	d
+GET_CBR_RG_DP_CK320BY2	include/ssv6200_reg.h	3440;"	d
+GET_CBR_RG_DP_DCP	include/ssv6200_reg.h	3453;"	d
+GET_CBR_RG_DP_DCS	include/ssv6200_reg.h	3454;"	d
+GET_CBR_RG_DP_DR3	include/ssv6200_reg.h	3452;"	d
+GET_CBR_RG_DP_FBDIV	include/ssv6200_reg.h	3455;"	d
+GET_CBR_RG_DP_FODIV	include/ssv6200_reg.h	3456;"	d
+GET_CBR_RG_DP_LDO_LEVEL	include/ssv6200_reg.h	3252;"	d
+GET_CBR_RG_DP_OD_TEST	include/ssv6200_reg.h	3442;"	d
+GET_CBR_RG_DP_REFDIV	include/ssv6200_reg.h	3457;"	d
+GET_CBR_RG_DP_RHP	include/ssv6200_reg.h	3451;"	d
+GET_CBR_RG_DP_RP	include/ssv6200_reg.h	3450;"	d
+GET_CBR_RG_DP_VT_MON_TMR	include/ssv6200_reg.h	3439;"	d
+GET_CBR_RG_DP_VT_TH_HI	include/ssv6200_reg.h	3437;"	d
+GET_CBR_RG_DP_VT_TH_LO	include/ssv6200_reg.h	3438;"	d
+GET_CBR_RG_EN_ADC	include/ssv6200_reg.h	3226;"	d
+GET_CBR_RG_EN_DP_VT_MON	include/ssv6200_reg.h	3436;"	d
+GET_CBR_RG_EN_EXT_DA	include/ssv6200_reg.h	3529;"	d
+GET_CBR_RG_EN_IREF_RX	include/ssv6200_reg.h	3244;"	d
+GET_CBR_RG_EN_LDO_ABB	include/ssv6200_reg.h	3240;"	d
+GET_CBR_RG_EN_LDO_AFE	include/ssv6200_reg.h	3241;"	d
+GET_CBR_RG_EN_LDO_RX_FE	include/ssv6200_reg.h	3239;"	d
+GET_CBR_RG_EN_MANUAL	include/ssv6200_reg.h	3207;"	d
+GET_CBR_RG_EN_RCAL	include/ssv6200_reg.h	3490;"	d
+GET_CBR_RG_EN_RX_DIV2	include/ssv6200_reg.h	3220;"	d
+GET_CBR_RG_EN_RX_FILTER	include/ssv6200_reg.h	3223;"	d
+GET_CBR_RG_EN_RX_HPF	include/ssv6200_reg.h	3224;"	d
+GET_CBR_RG_EN_RX_IQCAL	include/ssv6200_reg.h	3235;"	d
+GET_CBR_RG_EN_RX_LNA	include/ssv6200_reg.h	3218;"	d
+GET_CBR_RG_EN_RX_LOBF	include/ssv6200_reg.h	3231;"	d
+GET_CBR_RG_EN_RX_LOBUF	include/ssv6200_reg.h	3221;"	d
+GET_CBR_RG_EN_RX_MIXER	include/ssv6200_reg.h	3219;"	d
+GET_CBR_RG_EN_RX_PADSW	include/ssv6200_reg.h	3256;"	d
+GET_CBR_RG_EN_RX_RSSI	include/ssv6200_reg.h	3225;"	d
+GET_CBR_RG_EN_RX_RSSI_TESTNODE	include/ssv6200_reg.h	3282;"	d
+GET_CBR_RG_EN_RX_TESTNODE	include/ssv6200_reg.h	3257;"	d
+GET_CBR_RG_EN_RX_TZ	include/ssv6200_reg.h	3222;"	d
+GET_CBR_RG_EN_SX	include/ssv6200_reg.h	3217;"	d
+GET_CBR_RG_EN_SX_CH	include/ssv6200_reg.h	3362;"	d
+GET_CBR_RG_EN_SX_CHP	include/ssv6200_reg.h	3363;"	d
+GET_CBR_RG_EN_SX_CHPLDO	include/ssv6200_reg.h	3242;"	d
+GET_CBR_RG_EN_SX_DELCAL	include/ssv6200_reg.h	3370;"	d
+GET_CBR_RG_EN_SX_DITHER	include/ssv6200_reg.h	3369;"	d
+GET_CBR_RG_EN_SX_DIV	include/ssv6200_reg.h	3374;"	d
+GET_CBR_RG_EN_SX_DIVCK	include/ssv6200_reg.h	3364;"	d
+GET_CBR_RG_EN_SX_LCK	include/ssv6200_reg.h	3368;"	d
+GET_CBR_RG_EN_SX_LOBFLDO	include/ssv6200_reg.h	3243;"	d
+GET_CBR_RG_EN_SX_LPF	include/ssv6200_reg.h	3375;"	d
+GET_CBR_RG_EN_SX_MOD	include/ssv6200_reg.h	3367;"	d
+GET_CBR_RG_EN_SX_PC_BYPASS	include/ssv6200_reg.h	3371;"	d
+GET_CBR_RG_EN_SX_R3	include/ssv6200_reg.h	3361;"	d
+GET_CBR_RG_EN_SX_VCO	include/ssv6200_reg.h	3366;"	d
+GET_CBR_RG_EN_SX_VCOBF	include/ssv6200_reg.h	3365;"	d
+GET_CBR_RG_EN_SX_VT_MON	include/ssv6200_reg.h	3372;"	d
+GET_CBR_RG_EN_SX_VT_MON_DG	include/ssv6200_reg.h	3373;"	d
+GET_CBR_RG_EN_TX_DAC_CAL	include/ssv6200_reg.h	3236;"	d
+GET_CBR_RG_EN_TX_DAC_OUT	include/ssv6200_reg.h	3238;"	d
+GET_CBR_RG_EN_TX_DIV2	include/ssv6200_reg.h	3228;"	d
+GET_CBR_RG_EN_TX_DIV2_BUF	include/ssv6200_reg.h	3229;"	d
+GET_CBR_RG_EN_TX_DPD	include/ssv6200_reg.h	3233;"	d
+GET_CBR_RG_EN_TX_LOBF	include/ssv6200_reg.h	3230;"	d
+GET_CBR_RG_EN_TX_MOD	include/ssv6200_reg.h	3227;"	d
+GET_CBR_RG_EN_TX_SELF_MIXER	include/ssv6200_reg.h	3237;"	d
+GET_CBR_RG_EN_TX_TRSW	include/ssv6200_reg.h	3216;"	d
+GET_CBR_RG_EN_TX_TSSI	include/ssv6200_reg.h	3234;"	d
+GET_CBR_RG_HPF1_FAST_SET_X	include/ssv6200_reg.h	3330;"	d
+GET_CBR_RG_HPF1_FAST_SET_Y	include/ssv6200_reg.h	3331;"	d
+GET_CBR_RG_HPF1_FAST_SET_Z	include/ssv6200_reg.h	3332;"	d
+GET_CBR_RG_HPF_T1A	include/ssv6200_reg.h	3333;"	d
+GET_CBR_RG_HPF_T1B	include/ssv6200_reg.h	3334;"	d
+GET_CBR_RG_HPF_T1C	include/ssv6200_reg.h	3335;"	d
+GET_CBR_RG_IDACAI_PGAG0	include/ssv6200_reg.h	3488;"	d
+GET_CBR_RG_IDACAI_PGAG1	include/ssv6200_reg.h	3486;"	d
+GET_CBR_RG_IDACAI_PGAG10	include/ssv6200_reg.h	3468;"	d
+GET_CBR_RG_IDACAI_PGAG11	include/ssv6200_reg.h	3466;"	d
+GET_CBR_RG_IDACAI_PGAG12	include/ssv6200_reg.h	3464;"	d
+GET_CBR_RG_IDACAI_PGAG13	include/ssv6200_reg.h	3462;"	d
+GET_CBR_RG_IDACAI_PGAG14	include/ssv6200_reg.h	3460;"	d
+GET_CBR_RG_IDACAI_PGAG15	include/ssv6200_reg.h	3458;"	d
+GET_CBR_RG_IDACAI_PGAG2	include/ssv6200_reg.h	3484;"	d
+GET_CBR_RG_IDACAI_PGAG3	include/ssv6200_reg.h	3482;"	d
+GET_CBR_RG_IDACAI_PGAG4	include/ssv6200_reg.h	3480;"	d
+GET_CBR_RG_IDACAI_PGAG5	include/ssv6200_reg.h	3478;"	d
+GET_CBR_RG_IDACAI_PGAG6	include/ssv6200_reg.h	3476;"	d
+GET_CBR_RG_IDACAI_PGAG7	include/ssv6200_reg.h	3474;"	d
+GET_CBR_RG_IDACAI_PGAG8	include/ssv6200_reg.h	3472;"	d
+GET_CBR_RG_IDACAI_PGAG9	include/ssv6200_reg.h	3470;"	d
+GET_CBR_RG_IDACAQ_PGAG0	include/ssv6200_reg.h	3489;"	d
+GET_CBR_RG_IDACAQ_PGAG1	include/ssv6200_reg.h	3487;"	d
+GET_CBR_RG_IDACAQ_PGAG10	include/ssv6200_reg.h	3469;"	d
+GET_CBR_RG_IDACAQ_PGAG11	include/ssv6200_reg.h	3467;"	d
+GET_CBR_RG_IDACAQ_PGAG12	include/ssv6200_reg.h	3465;"	d
+GET_CBR_RG_IDACAQ_PGAG13	include/ssv6200_reg.h	3463;"	d
+GET_CBR_RG_IDACAQ_PGAG14	include/ssv6200_reg.h	3461;"	d
+GET_CBR_RG_IDACAQ_PGAG15	include/ssv6200_reg.h	3459;"	d
+GET_CBR_RG_IDACAQ_PGAG2	include/ssv6200_reg.h	3485;"	d
+GET_CBR_RG_IDACAQ_PGAG3	include/ssv6200_reg.h	3483;"	d
+GET_CBR_RG_IDACAQ_PGAG4	include/ssv6200_reg.h	3481;"	d
+GET_CBR_RG_IDACAQ_PGAG5	include/ssv6200_reg.h	3479;"	d
+GET_CBR_RG_IDACAQ_PGAG6	include/ssv6200_reg.h	3477;"	d
+GET_CBR_RG_IDACAQ_PGAG7	include/ssv6200_reg.h	3475;"	d
+GET_CBR_RG_IDACAQ_PGAG8	include/ssv6200_reg.h	3473;"	d
+GET_CBR_RG_IDACAQ_PGAG9	include/ssv6200_reg.h	3471;"	d
+GET_CBR_RG_IDEAL_CYCLE	include/ssv6200_reg.h	3435;"	d
+GET_CBR_RG_I_PAD_PD	include/ssv6200_reg.h	3522;"	d
+GET_CBR_RG_LDO_LEVEL_ABB	include/ssv6200_reg.h	3247;"	d
+GET_CBR_RG_LDO_LEVEL_AFE	include/ssv6200_reg.h	3248;"	d
+GET_CBR_RG_LDO_LEVEL_RX_FE	include/ssv6200_reg.h	3246;"	d
+GET_CBR_RG_MODE	include/ssv6200_reg.h	3215;"	d
+GET_CBR_RG_O_PAD_PD	include/ssv6200_reg.h	3521;"	d
+GET_CBR_RG_PABIAS_AB	include/ssv6200_reg.h	3294;"	d
+GET_CBR_RG_PABIAS_CTRL	include/ssv6200_reg.h	3293;"	d
+GET_CBR_RG_PACELL_EN	include/ssv6200_reg.h	3292;"	d
+GET_CBR_RG_PAD_DS	include/ssv6200_reg.h	3524;"	d
+GET_CBR_RG_PAD_DS_CLK	include/ssv6200_reg.h	3526;"	d
+GET_CBR_RG_PGAG	include/ssv6200_reg.h	3214;"	d
+GET_CBR_RG_PKT_GEN_TX_CNT	include/ssv6200_reg.h	3533;"	d
+GET_CBR_RG_RCAL_CODE_CWD	include/ssv6200_reg.h	3494;"	d
+GET_CBR_RG_RCAL_CODE_CWR	include/ssv6200_reg.h	3493;"	d
+GET_CBR_RG_RCAL_SPD	include/ssv6200_reg.h	3491;"	d
+GET_CBR_RG_RCAL_TMR	include/ssv6200_reg.h	3492;"	d
+GET_CBR_RG_RFG	include/ssv6200_reg.h	3213;"	d
+GET_CBR_RG_RSSI_CLOCK_GATING	include/ssv6200_reg.h	3286;"	d
+GET_CBR_RG_RX_ABBCFIX	include/ssv6200_reg.h	3258;"	d
+GET_CBR_RG_RX_ABBCTUNE	include/ssv6200_reg.h	3259;"	d
+GET_CBR_RG_RX_ABBOUT_TRI_STATE	include/ssv6200_reg.h	3260;"	d
+GET_CBR_RG_RX_ABB_N_MODE	include/ssv6200_reg.h	3261;"	d
+GET_CBR_RG_RX_ADCRSSI_CLKSEL	include/ssv6200_reg.h	3283;"	d
+GET_CBR_RG_RX_ADCRSSI_VCM	include/ssv6200_reg.h	3284;"	d
+GET_CBR_RG_RX_AGC	include/ssv6200_reg.h	3211;"	d
+GET_CBR_RG_RX_DIV2_CORE	include/ssv6200_reg.h	3298;"	d
+GET_CBR_RG_RX_EN_LOOPA	include/ssv6200_reg.h	3262;"	d
+GET_CBR_RG_RX_FILTERI1ST	include/ssv6200_reg.h	3263;"	d
+GET_CBR_RG_RX_FILTERI2ND	include/ssv6200_reg.h	3264;"	d
+GET_CBR_RG_RX_FILTERI3RD	include/ssv6200_reg.h	3265;"	d
+GET_CBR_RG_RX_FILTERI_COURSE	include/ssv6200_reg.h	3266;"	d
+GET_CBR_RG_RX_FILTERVCM	include/ssv6200_reg.h	3267;"	d
+GET_CBR_RG_RX_GAIN_MANUAL	include/ssv6200_reg.h	3212;"	d
+GET_CBR_RG_RX_HG_LNAHGN_BIAS	include/ssv6200_reg.h	3307;"	d
+GET_CBR_RG_RX_HG_LNAHGP_BIAS	include/ssv6200_reg.h	3308;"	d
+GET_CBR_RG_RX_HG_LNALG_BIAS	include/ssv6200_reg.h	3309;"	d
+GET_CBR_RG_RX_HG_LNA_GC	include/ssv6200_reg.h	3306;"	d
+GET_CBR_RG_RX_HG_TZ_CAP	include/ssv6200_reg.h	3311;"	d
+GET_CBR_RG_RX_HG_TZ_GC	include/ssv6200_reg.h	3310;"	d
+GET_CBR_RG_RX_HPF300K	include/ssv6200_reg.h	3269;"	d
+GET_CBR_RG_RX_HPF3M	include/ssv6200_reg.h	3268;"	d
+GET_CBR_RG_RX_HPFI	include/ssv6200_reg.h	3270;"	d
+GET_CBR_RG_RX_HPF_FINALCORNER	include/ssv6200_reg.h	3271;"	d
+GET_CBR_RG_RX_HPF_SETTLE1_C	include/ssv6200_reg.h	3272;"	d
+GET_CBR_RG_RX_HPF_SETTLE1_R	include/ssv6200_reg.h	3273;"	d
+GET_CBR_RG_RX_HPF_SETTLE2_C	include/ssv6200_reg.h	3274;"	d
+GET_CBR_RG_RX_HPF_SETTLE2_R	include/ssv6200_reg.h	3275;"	d
+GET_CBR_RG_RX_HPF_VCMCON	include/ssv6200_reg.h	3277;"	d
+GET_CBR_RG_RX_HPF_VCMCON2	include/ssv6200_reg.h	3276;"	d
+GET_CBR_RG_RX_LG_LNAHGN_BIAS	include/ssv6200_reg.h	3319;"	d
+GET_CBR_RG_RX_LG_LNAHGP_BIAS	include/ssv6200_reg.h	3320;"	d
+GET_CBR_RG_RX_LG_LNALG_BIAS	include/ssv6200_reg.h	3321;"	d
+GET_CBR_RG_RX_LG_LNA_GC	include/ssv6200_reg.h	3318;"	d
+GET_CBR_RG_RX_LG_TZ_CAP	include/ssv6200_reg.h	3323;"	d
+GET_CBR_RG_RX_LG_TZ_GC	include/ssv6200_reg.h	3322;"	d
+GET_CBR_RG_RX_LNA_SETTLE	include/ssv6200_reg.h	3337;"	d
+GET_CBR_RG_RX_LNA_TRI_SEL	include/ssv6200_reg.h	3336;"	d
+GET_CBR_RG_RX_LOBUF	include/ssv6200_reg.h	3299;"	d
+GET_CBR_RG_RX_MG_LNAHGN_BIAS	include/ssv6200_reg.h	3313;"	d
+GET_CBR_RG_RX_MG_LNAHGP_BIAS	include/ssv6200_reg.h	3314;"	d
+GET_CBR_RG_RX_MG_LNALG_BIAS	include/ssv6200_reg.h	3315;"	d
+GET_CBR_RG_RX_MG_LNA_GC	include/ssv6200_reg.h	3312;"	d
+GET_CBR_RG_RX_MG_TZ_CAP	include/ssv6200_reg.h	3317;"	d
+GET_CBR_RG_RX_MG_TZ_GC	include/ssv6200_reg.h	3316;"	d
+GET_CBR_RG_RX_OUTVCM	include/ssv6200_reg.h	3278;"	d
+GET_CBR_RG_RX_REC_LPFCORNER	include/ssv6200_reg.h	3285;"	d
+GET_CBR_RG_RX_SQDC	include/ssv6200_reg.h	3297;"	d
+GET_CBR_RG_RX_TZI	include/ssv6200_reg.h	3279;"	d
+GET_CBR_RG_RX_TZ_OUT_TRISTATE	include/ssv6200_reg.h	3280;"	d
+GET_CBR_RG_RX_TZ_VCM	include/ssv6200_reg.h	3281;"	d
+GET_CBR_RG_RX_ULG_LNAHGN_BIAS	include/ssv6200_reg.h	3325;"	d
+GET_CBR_RG_RX_ULG_LNAHGP_BIAS	include/ssv6200_reg.h	3326;"	d
+GET_CBR_RG_RX_ULG_LNALG_BIAS	include/ssv6200_reg.h	3327;"	d
+GET_CBR_RG_RX_ULG_LNA_GC	include/ssv6200_reg.h	3324;"	d
+GET_CBR_RG_RX_ULG_TZ_CAP	include/ssv6200_reg.h	3329;"	d
+GET_CBR_RG_RX_ULG_TZ_GC	include/ssv6200_reg.h	3328;"	d
+GET_CBR_RG_SDM_PASS	include/ssv6200_reg.h	3411;"	d
+GET_CBR_RG_SEL_DPLL_CLK	include/ssv6200_reg.h	3232;"	d
+GET_CBR_RG_SX_CHP_IOST	include/ssv6200_reg.h	3388;"	d
+GET_CBR_RG_SX_CHP_IOST_POL	include/ssv6200_reg.h	3387;"	d
+GET_CBR_RG_SX_CV_CURVE_SEL	include/ssv6200_reg.h	3423;"	d
+GET_CBR_RG_SX_DELCTRL	include/ssv6200_reg.h	3441;"	d
+GET_CBR_RG_SX_DITHER_WEIGHT	include/ssv6200_reg.h	3406;"	d
+GET_CBR_RG_SX_DIVBFSEL	include/ssv6200_reg.h	3404;"	d
+GET_CBR_RG_SX_GNDR_SEL	include/ssv6200_reg.h	3405;"	d
+GET_CBR_RG_SX_LCKEN	include/ssv6200_reg.h	3418;"	d
+GET_CBR_RG_SX_LDO_CHP_LEVEL	include/ssv6200_reg.h	3249;"	d
+GET_CBR_RG_SX_LDO_LOBF_LEVEL	include/ssv6200_reg.h	3250;"	d
+GET_CBR_RG_SX_LDO_VCO_LEVEL	include/ssv6200_reg.h	3253;"	d
+GET_CBR_RG_SX_LDO_XOSC_LEVEL	include/ssv6200_reg.h	3251;"	d
+GET_CBR_RG_SX_MODDB	include/ssv6200_reg.h	3422;"	d
+GET_CBR_RG_SX_MOD_ERRCMP	include/ssv6200_reg.h	3407;"	d
+GET_CBR_RG_SX_MOD_ERR_DELAY	include/ssv6200_reg.h	3421;"	d
+GET_CBR_RG_SX_MOD_ORDER	include/ssv6200_reg.h	3408;"	d
+GET_CBR_RG_SX_PFDSEL	include/ssv6200_reg.h	3389;"	d
+GET_CBR_RG_SX_PFD_RST_H	include/ssv6200_reg.h	3394;"	d
+GET_CBR_RG_SX_PFD_SET	include/ssv6200_reg.h	3390;"	d
+GET_CBR_RG_SX_PFD_SET1	include/ssv6200_reg.h	3391;"	d
+GET_CBR_RG_SX_PFD_SET2	include/ssv6200_reg.h	3392;"	d
+GET_CBR_RG_SX_PFD_TRDN	include/ssv6200_reg.h	3396;"	d
+GET_CBR_RG_SX_PFD_TRSEL	include/ssv6200_reg.h	3397;"	d
+GET_CBR_RG_SX_PFD_TRUP	include/ssv6200_reg.h	3395;"	d
+GET_CBR_RG_SX_PH	include/ssv6200_reg.h	3428;"	d
+GET_CBR_RG_SX_PL	include/ssv6200_reg.h	3429;"	d
+GET_CBR_RG_SX_PREVDD	include/ssv6200_reg.h	3419;"	d
+GET_CBR_RG_SX_PSCONTERVDD	include/ssv6200_reg.h	3420;"	d
+GET_CBR_RG_SX_REFBYTWO	include/ssv6200_reg.h	3415;"	d
+GET_CBR_RG_SX_REF_CYCLE	include/ssv6200_reg.h	3425;"	d
+GET_CBR_RG_SX_RFCTRL_CH	include/ssv6200_reg.h	3379;"	d
+GET_CBR_RG_SX_RFCTRL_F	include/ssv6200_reg.h	3376;"	d
+GET_CBR_RG_SX_RST_H_DIV	include/ssv6200_reg.h	3412;"	d
+GET_CBR_RG_SX_RXBFSEL	include/ssv6200_reg.h	3401;"	d
+GET_CBR_RG_SX_SDMLUT_INV	include/ssv6200_reg.h	3417;"	d
+GET_CBR_RG_SX_SDM_D1	include/ssv6200_reg.h	3409;"	d
+GET_CBR_RG_SX_SDM_D2	include/ssv6200_reg.h	3410;"	d
+GET_CBR_RG_SX_SDM_EDGE	include/ssv6200_reg.h	3413;"	d
+GET_CBR_RG_SX_SEL_C3	include/ssv6200_reg.h	3380;"	d
+GET_CBR_RG_SX_SEL_CHP_REGOP	include/ssv6200_reg.h	3385;"	d
+GET_CBR_RG_SX_SEL_CHP_UNIOP	include/ssv6200_reg.h	3386;"	d
+GET_CBR_RG_SX_SEL_CP	include/ssv6200_reg.h	3377;"	d
+GET_CBR_RG_SX_SEL_CS	include/ssv6200_reg.h	3378;"	d
+GET_CBR_RG_SX_SEL_DELAY	include/ssv6200_reg.h	3424;"	d
+GET_CBR_RG_SX_SEL_ICHP	include/ssv6200_reg.h	3383;"	d
+GET_CBR_RG_SX_SEL_PCHP	include/ssv6200_reg.h	3384;"	d
+GET_CBR_RG_SX_SEL_R3	include/ssv6200_reg.h	3382;"	d
+GET_CBR_RG_SX_SEL_RS	include/ssv6200_reg.h	3381;"	d
+GET_CBR_RG_SX_SUB_SEL_CWD	include/ssv6200_reg.h	3496;"	d
+GET_CBR_RG_SX_SUB_SEL_CWR	include/ssv6200_reg.h	3495;"	d
+GET_CBR_RG_SX_TXBFSEL	include/ssv6200_reg.h	3402;"	d
+GET_CBR_RG_SX_VBNCAS_SEL	include/ssv6200_reg.h	3393;"	d
+GET_CBR_RG_SX_VCOBA_R	include/ssv6200_reg.h	3398;"	d
+GET_CBR_RG_SX_VCOBFSEL	include/ssv6200_reg.h	3403;"	d
+GET_CBR_RG_SX_VCOBY16	include/ssv6200_reg.h	3426;"	d
+GET_CBR_RG_SX_VCOBY32	include/ssv6200_reg.h	3427;"	d
+GET_CBR_RG_SX_VCOCUSEL	include/ssv6200_reg.h	3400;"	d
+GET_CBR_RG_SX_VCORSEL	include/ssv6200_reg.h	3399;"	d
+GET_CBR_RG_SX_VT_MON_MODE	include/ssv6200_reg.h	3430;"	d
+GET_CBR_RG_SX_VT_MON_TMR	include/ssv6200_reg.h	3434;"	d
+GET_CBR_RG_SX_VT_SET	include/ssv6200_reg.h	3433;"	d
+GET_CBR_RG_SX_VT_TH_HI	include/ssv6200_reg.h	3431;"	d
+GET_CBR_RG_SX_VT_TH_LO	include/ssv6200_reg.h	3432;"	d
+GET_CBR_RG_SX_XO_GM	include/ssv6200_reg.h	3414;"	d
+GET_CBR_RG_SX_XO_SWCAP	include/ssv6200_reg.h	3416;"	d
+GET_CBR_RG_TXLPF_BOOSTI	include/ssv6200_reg.h	3360;"	d
+GET_CBR_RG_TXLPF_BYPASS	include/ssv6200_reg.h	3359;"	d
+GET_CBR_RG_TXLPF_GMCELL	include/ssv6200_reg.h	3291;"	d
+GET_CBR_RG_TXMOD_GMCELL	include/ssv6200_reg.h	3290;"	d
+GET_CBR_RG_TXPGA_CAPSW	include/ssv6200_reg.h	3287;"	d
+GET_CBR_RG_TXPGA_MAIN	include/ssv6200_reg.h	3288;"	d
+GET_CBR_RG_TXPGA_STEER	include/ssv6200_reg.h	3289;"	d
+GET_CBR_RG_TX_DACLPF_ICOURSE	include/ssv6200_reg.h	3350;"	d
+GET_CBR_RG_TX_DACLPF_IFINE	include/ssv6200_reg.h	3351;"	d
+GET_CBR_RG_TX_DACLPF_VCM	include/ssv6200_reg.h	3352;"	d
+GET_CBR_RG_TX_DAC_CKEDGE_SEL	include/ssv6200_reg.h	3353;"	d
+GET_CBR_RG_TX_DAC_EN	include/ssv6200_reg.h	3210;"	d
+GET_CBR_RG_TX_DAC_IBIAS	include/ssv6200_reg.h	3354;"	d
+GET_CBR_RG_TX_DAC_OS	include/ssv6200_reg.h	3355;"	d
+GET_CBR_RG_TX_DAC_RCAL	include/ssv6200_reg.h	3356;"	d
+GET_CBR_RG_TX_DAC_TSEL	include/ssv6200_reg.h	3357;"	d
+GET_CBR_RG_TX_DIV_VSET	include/ssv6200_reg.h	3295;"	d
+GET_CBR_RG_TX_DPDGM_BIAS	include/ssv6200_reg.h	3300;"	d
+GET_CBR_RG_TX_DPD_DIV	include/ssv6200_reg.h	3301;"	d
+GET_CBR_RG_TX_EN	include/ssv6200_reg.h	3208;"	d
+GET_CBR_RG_TX_EN_VOLTAGE_IN	include/ssv6200_reg.h	3358;"	d
+GET_CBR_RG_TX_LDO_TX_LEVEL	include/ssv6200_reg.h	3254;"	d
+GET_CBR_RG_TX_LOBUF_VSET	include/ssv6200_reg.h	3296;"	d
+GET_CBR_RG_TX_PA_EN	include/ssv6200_reg.h	3209;"	d
+GET_CBR_RG_TX_TSSI_BIAS	include/ssv6200_reg.h	3302;"	d
+GET_CBR_RG_TX_TSSI_DIV	include/ssv6200_reg.h	3303;"	d
+GET_CBR_RG_TX_TSSI_TEST	include/ssv6200_reg.h	3305;"	d
+GET_CBR_RG_TX_TSSI_TESTMODE	include/ssv6200_reg.h	3304;"	d
+GET_CBR_SEL_ADCKP_INV	include/ssv6200_reg.h	3523;"	d
+GET_CBR_SEL_ADCKP_MUX	include/ssv6200_reg.h	3525;"	d
+GET_CBR_TAIL_TIME	include/ssv6200_reg.h	3520;"	d
+GET_CBR_TC_CNT_TARGET	include/ssv6200_reg.h	3515;"	d
+GET_CBR_TP_SEL	include/ssv6200_reg.h	3534;"	d
+GET_CBR_TWO_TONE_EN	include/ssv6200_reg.h	3537;"	d
+GET_CBR_TX_CNT_RST	include/ssv6200_reg.h	3511;"	d
+GET_CBR_TX_CNT_TARGET	include/ssv6200_reg.h	3514;"	d
+GET_CBR_TX_EN	include/ssv6200_reg.h	3510;"	d
+GET_CBR_VT_MON_RDY	include/ssv6200_reg.h	3501;"	d
+GET_CCCR_00H_REG	include/ssv6200_reg.h	1992;"	d
+GET_CCCR_00H_REG	smac/hal/ssv6006c/ssv6006C_reg.h	2706;"	d
+GET_CCCR_02H_REG	include/ssv6200_reg.h	1993;"	d
+GET_CCCR_02H_REG	smac/hal/ssv6006c/ssv6006C_reg.h	2707;"	d
+GET_CCCR_03H_REG	include/ssv6200_reg.h	1994;"	d
+GET_CCCR_03H_REG	smac/hal/ssv6006c/ssv6006C_reg.h	2708;"	d
+GET_CCCR_04H_REG	include/ssv6200_reg.h	1995;"	d
+GET_CCCR_04H_REG	smac/hal/ssv6006c/ssv6006C_reg.h	2709;"	d
+GET_CCCR_05H_REG	include/ssv6200_reg.h	1996;"	d
+GET_CCCR_05H_REG	smac/hal/ssv6006c/ssv6006C_reg.h	2710;"	d
+GET_CCCR_06H_REG	include/ssv6200_reg.h	1997;"	d
+GET_CCCR_06H_REG	smac/hal/ssv6006c/ssv6006C_reg.h	2711;"	d
+GET_CCCR_07H_REG	include/ssv6200_reg.h	1998;"	d
+GET_CCCR_07H_REG	smac/hal/ssv6006c/ssv6006C_reg.h	2712;"	d
+GET_CCK_RATE_INDEX	smac/ssv_rc_minstrel_ht.h	27;"	d
+GET_CCMP_H_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	3927;"	d
+GET_CD	include/ssv6200_reg.h	2155;"	d
+GET_CD	smac/hal/ssv6006c/ssv6006C_reg.h	2866;"	d
+GET_CH0_DYN_PRI	include/ssv6200_reg.h	3757;"	d
+GET_CH0_DYN_PRI	smac/hal/ssv6006c/ssv6006C_reg.h	8940;"	d
+GET_CH0_FFO_FULL	include/ssv6200_reg.h	3679;"	d
+GET_CH0_FFO_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	8875;"	d
+GET_CH0_FULL	include/ssv6200_reg.h	3547;"	d
+GET_CH0_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	8738;"	d
+GET_CH0_FULL_ALT	smac/hal/ssv6006c/ssv6006C_reg.h	8763;"	d
+GET_CH0_INT_ADDR	include/ssv6200_reg.h	3545;"	d
+GET_CH0_INT_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	8735;"	d
+GET_CH0_LOWTHOLD	include/ssv6200_reg.h	3712;"	d
+GET_CH0_LOWTHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	8908;"	d
+GET_CH0_LOWTHOLD_INT	include/ssv6200_reg.h	3695;"	d
+GET_CH0_LOWTHOLD_INT	smac/hal/ssv6006c/ssv6006C_reg.h	8891;"	d
+GET_CH0_NVLD	include/ssv6200_reg.h	3781;"	d
+GET_CH0_NVLD	smac/hal/ssv6006c/ssv6006C_reg.h	8964;"	d
+GET_CH0_QUEUE_FLUSH	include/ssv6200_reg.h	3647;"	d
+GET_CH0_REQ_LOCK	include/ssv6200_reg.h	3772;"	d
+GET_CH0_REQ_LOCK	smac/hal/ssv6006c/ssv6006C_reg.h	8955;"	d
+GET_CH0_STA_PRI	include/ssv6200_reg.h	3759;"	d
+GET_CH0_STA_PRI	smac/hal/ssv6006c/ssv6006C_reg.h	8942;"	d
+GET_CH0_WRFF_FLUSH	include/ssv6200_reg.h	3732;"	d
+GET_CH10_FFO_FULL	include/ssv6200_reg.h	3689;"	d
+GET_CH10_FFO_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	8885;"	d
+GET_CH10_FULL	include/ssv6200_reg.h	3579;"	d
+GET_CH10_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	8773;"	d
+GET_CH10_HALT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	8807;"	d
+GET_CH10_LOWTHOLD	include/ssv6200_reg.h	3722;"	d
+GET_CH10_LOWTHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	8918;"	d
+GET_CH10_LOWTHOLD_INT	include/ssv6200_reg.h	3705;"	d
+GET_CH10_LOWTHOLD_INT	smac/hal/ssv6006c/ssv6006C_reg.h	8901;"	d
+GET_CH10_QUEUE_FLUSH	include/ssv6200_reg.h	3657;"	d
+GET_CH10_WRFF_FLUSH	include/ssv6200_reg.h	3742;"	d
+GET_CH11_FFO_FULL	include/ssv6200_reg.h	3690;"	d
+GET_CH11_FFO_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	8886;"	d
+GET_CH11_FULL	include/ssv6200_reg.h	3580;"	d
+GET_CH11_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	8774;"	d
+GET_CH11_HALT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	8808;"	d
+GET_CH11_LOWTHOLD	include/ssv6200_reg.h	3723;"	d
+GET_CH11_LOWTHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	8919;"	d
+GET_CH11_LOWTHOLD_INT	include/ssv6200_reg.h	3706;"	d
+GET_CH11_LOWTHOLD_INT	smac/hal/ssv6006c/ssv6006C_reg.h	8902;"	d
+GET_CH11_QUEUE_FLUSH	include/ssv6200_reg.h	3658;"	d
+GET_CH11_WRFF_FLUSH	include/ssv6200_reg.h	3743;"	d
+GET_CH12_FFO_FULL	include/ssv6200_reg.h	3691;"	d
+GET_CH12_FFO_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	8887;"	d
+GET_CH12_FULL	include/ssv6200_reg.h	3581;"	d
+GET_CH12_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	8775;"	d
+GET_CH12_HALT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	8809;"	d
+GET_CH12_LOWTHOLD	include/ssv6200_reg.h	3724;"	d
+GET_CH12_LOWTHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	8920;"	d
+GET_CH12_LOWTHOLD_INT	include/ssv6200_reg.h	3707;"	d
+GET_CH12_LOWTHOLD_INT	smac/hal/ssv6006c/ssv6006C_reg.h	8903;"	d
+GET_CH12_QUEUE_FLUSH	include/ssv6200_reg.h	3659;"	d
+GET_CH12_WRFF_FLUSH	include/ssv6200_reg.h	3744;"	d
+GET_CH13_FFO_FULL	include/ssv6200_reg.h	3692;"	d
+GET_CH13_FFO_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	8888;"	d
+GET_CH13_FULL	include/ssv6200_reg.h	3582;"	d
+GET_CH13_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	8776;"	d
+GET_CH13_HALT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	8810;"	d
+GET_CH13_LOWTHOLD	include/ssv6200_reg.h	3725;"	d
+GET_CH13_LOWTHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	8921;"	d
+GET_CH13_LOWTHOLD_INT	include/ssv6200_reg.h	3708;"	d
+GET_CH13_LOWTHOLD_INT	smac/hal/ssv6006c/ssv6006C_reg.h	8904;"	d
+GET_CH13_QUEUE_FLUSH	include/ssv6200_reg.h	3660;"	d
+GET_CH13_WRFF_FLUSH	include/ssv6200_reg.h	3745;"	d
+GET_CH14_FFO_FULL	include/ssv6200_reg.h	3693;"	d
+GET_CH14_FFO_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	8889;"	d
+GET_CH14_FULL	include/ssv6200_reg.h	3583;"	d
+GET_CH14_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	8777;"	d
+GET_CH14_HALT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	8811;"	d
+GET_CH14_LOWTHOLD	include/ssv6200_reg.h	3726;"	d
+GET_CH14_LOWTHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	8922;"	d
+GET_CH14_LOWTHOLD_INT	include/ssv6200_reg.h	3709;"	d
+GET_CH14_LOWTHOLD_INT	smac/hal/ssv6006c/ssv6006C_reg.h	8905;"	d
+GET_CH14_QUEUE_FLUSH	include/ssv6200_reg.h	3661;"	d
+GET_CH14_WRFF_FLUSH	include/ssv6200_reg.h	3746;"	d
+GET_CH15_FFO_FULL	include/ssv6200_reg.h	3694;"	d
+GET_CH15_FFO_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	8890;"	d
+GET_CH15_FULL	include/ssv6200_reg.h	3584;"	d
+GET_CH15_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	8778;"	d
+GET_CH15_LOWTHOLD	include/ssv6200_reg.h	3727;"	d
+GET_CH15_LOWTHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	8923;"	d
+GET_CH15_LOWTHOLD_INT	include/ssv6200_reg.h	3710;"	d
+GET_CH15_LOWTHOLD_INT	smac/hal/ssv6006c/ssv6006C_reg.h	8906;"	d
+GET_CH15_QUEUE_FLUSH	include/ssv6200_reg.h	3662;"	d
+GET_CH1_FFO_FULL	include/ssv6200_reg.h	3680;"	d
+GET_CH1_FFO_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	8876;"	d
+GET_CH1_FULL	include/ssv6200_reg.h	3570;"	d
+GET_CH1_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	8764;"	d
+GET_CH1_HALT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	8799;"	d
+GET_CH1_LOWTHOLD	include/ssv6200_reg.h	3713;"	d
+GET_CH1_LOWTHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	8909;"	d
+GET_CH1_LOWTHOLD_INT	include/ssv6200_reg.h	3696;"	d
+GET_CH1_LOWTHOLD_INT	smac/hal/ssv6006c/ssv6006C_reg.h	8892;"	d
+GET_CH1_NVLD	include/ssv6200_reg.h	3782;"	d
+GET_CH1_NVLD	smac/hal/ssv6006c/ssv6006C_reg.h	8965;"	d
+GET_CH1_PRI	include/ssv6200_reg.h	3012;"	d
+GET_CH1_PRI	smac/hal/ssv6006c/ssv6006C_reg.h	3844;"	d
+GET_CH1_QUEUE_FLUSH	include/ssv6200_reg.h	3648;"	d
+GET_CH1_REQ_LOCK	include/ssv6200_reg.h	3773;"	d
+GET_CH1_REQ_LOCK	smac/hal/ssv6006c/ssv6006C_reg.h	8956;"	d
+GET_CH1_STA_PRI	include/ssv6200_reg.h	3760;"	d
+GET_CH1_STA_PRI	smac/hal/ssv6006c/ssv6006C_reg.h	8943;"	d
+GET_CH1_WRFF_FLUSH	include/ssv6200_reg.h	3733;"	d
+GET_CH2_FFO_FULL	include/ssv6200_reg.h	3681;"	d
+GET_CH2_FFO_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	8877;"	d
+GET_CH2_FULL	include/ssv6200_reg.h	3571;"	d
+GET_CH2_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	8740;"	d
+GET_CH2_FULL_ALT	smac/hal/ssv6006c/ssv6006C_reg.h	8765;"	d
+GET_CH2_INT_ADDR_ALT	smac/hal/ssv6006c/ssv6006C_reg.h	8781;"	d
+GET_CH2_LOWTHOLD	include/ssv6200_reg.h	3714;"	d
+GET_CH2_LOWTHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	8910;"	d
+GET_CH2_LOWTHOLD_INT	include/ssv6200_reg.h	3697;"	d
+GET_CH2_LOWTHOLD_INT	smac/hal/ssv6006c/ssv6006C_reg.h	8893;"	d
+GET_CH2_NVLD	include/ssv6200_reg.h	3783;"	d
+GET_CH2_NVLD	smac/hal/ssv6006c/ssv6006C_reg.h	8966;"	d
+GET_CH2_PRI	include/ssv6200_reg.h	3013;"	d
+GET_CH2_PRI	smac/hal/ssv6006c/ssv6006C_reg.h	3845;"	d
+GET_CH2_QUEUE_FLUSH	include/ssv6200_reg.h	3649;"	d
+GET_CH2_REQ_LOCK	include/ssv6200_reg.h	3774;"	d
+GET_CH2_REQ_LOCK	smac/hal/ssv6006c/ssv6006C_reg.h	8957;"	d
+GET_CH2_STA_PRI	include/ssv6200_reg.h	3761;"	d
+GET_CH2_STA_PRI	smac/hal/ssv6006c/ssv6006C_reg.h	8944;"	d
+GET_CH2_WRFF_FLUSH	include/ssv6200_reg.h	3734;"	d
+GET_CH3_FFO_FULL	include/ssv6200_reg.h	3682;"	d
+GET_CH3_FFO_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	8878;"	d
+GET_CH3_FULL	include/ssv6200_reg.h	3572;"	d
+GET_CH3_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	8766;"	d
+GET_CH3_HALT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	8800;"	d
+GET_CH3_LOWTHOLD	include/ssv6200_reg.h	3715;"	d
+GET_CH3_LOWTHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	8911;"	d
+GET_CH3_LOWTHOLD_INT	include/ssv6200_reg.h	3698;"	d
+GET_CH3_LOWTHOLD_INT	smac/hal/ssv6006c/ssv6006C_reg.h	8894;"	d
+GET_CH3_NVLD	include/ssv6200_reg.h	3784;"	d
+GET_CH3_NVLD	smac/hal/ssv6006c/ssv6006C_reg.h	8967;"	d
+GET_CH3_PRI	include/ssv6200_reg.h	3014;"	d
+GET_CH3_PRI	smac/hal/ssv6006c/ssv6006C_reg.h	3846;"	d
+GET_CH3_QUEUE_FLUSH	include/ssv6200_reg.h	3650;"	d
+GET_CH3_REQ_LOCK	include/ssv6200_reg.h	3775;"	d
+GET_CH3_REQ_LOCK	smac/hal/ssv6006c/ssv6006C_reg.h	8958;"	d
+GET_CH3_STA_PRI	include/ssv6200_reg.h	3762;"	d
+GET_CH3_STA_PRI	smac/hal/ssv6006c/ssv6006C_reg.h	8945;"	d
+GET_CH3_WRFF_FLUSH	include/ssv6200_reg.h	3735;"	d
+GET_CH4_FFO_FULL	include/ssv6200_reg.h	3683;"	d
+GET_CH4_FFO_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	8879;"	d
+GET_CH4_FULL	include/ssv6200_reg.h	3573;"	d
+GET_CH4_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	8767;"	d
+GET_CH4_HALT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	8801;"	d
+GET_CH4_LOWTHOLD	include/ssv6200_reg.h	3716;"	d
+GET_CH4_LOWTHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	8912;"	d
+GET_CH4_LOWTHOLD_INT	include/ssv6200_reg.h	3699;"	d
+GET_CH4_LOWTHOLD_INT	smac/hal/ssv6006c/ssv6006C_reg.h	8895;"	d
+GET_CH4_QUEUE_FLUSH	include/ssv6200_reg.h	3651;"	d
+GET_CH4_WRFF_FLUSH	include/ssv6200_reg.h	3736;"	d
+GET_CH5_FFO_FULL	include/ssv6200_reg.h	3684;"	d
+GET_CH5_FFO_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	8880;"	d
+GET_CH5_FULL	include/ssv6200_reg.h	3574;"	d
+GET_CH5_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	8768;"	d
+GET_CH5_HALT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	8802;"	d
+GET_CH5_LOWTHOLD	include/ssv6200_reg.h	3717;"	d
+GET_CH5_LOWTHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	8913;"	d
+GET_CH5_LOWTHOLD_INT	include/ssv6200_reg.h	3700;"	d
+GET_CH5_LOWTHOLD_INT	smac/hal/ssv6006c/ssv6006C_reg.h	8896;"	d
+GET_CH5_QUEUE_FLUSH	include/ssv6200_reg.h	3652;"	d
+GET_CH5_WRFF_FLUSH	include/ssv6200_reg.h	3737;"	d
+GET_CH6_FFO_FULL	include/ssv6200_reg.h	3685;"	d
+GET_CH6_FFO_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	8881;"	d
+GET_CH6_FULL	include/ssv6200_reg.h	3575;"	d
+GET_CH6_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	8769;"	d
+GET_CH6_HALT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	8803;"	d
+GET_CH6_LOWTHOLD	include/ssv6200_reg.h	3718;"	d
+GET_CH6_LOWTHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	8914;"	d
+GET_CH6_LOWTHOLD_INT	include/ssv6200_reg.h	3701;"	d
+GET_CH6_LOWTHOLD_INT	smac/hal/ssv6006c/ssv6006C_reg.h	8897;"	d
+GET_CH6_QUEUE_FLUSH	include/ssv6200_reg.h	3653;"	d
+GET_CH6_WRFF_FLUSH	include/ssv6200_reg.h	3738;"	d
+GET_CH7_FFO_FULL	include/ssv6200_reg.h	3686;"	d
+GET_CH7_FFO_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	8882;"	d
+GET_CH7_FULL	include/ssv6200_reg.h	3576;"	d
+GET_CH7_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	8770;"	d
+GET_CH7_HALT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	8804;"	d
+GET_CH7_LOWTHOLD	include/ssv6200_reg.h	3719;"	d
+GET_CH7_LOWTHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	8915;"	d
+GET_CH7_LOWTHOLD_INT	include/ssv6200_reg.h	3702;"	d
+GET_CH7_LOWTHOLD_INT	smac/hal/ssv6006c/ssv6006C_reg.h	8898;"	d
+GET_CH7_QUEUE_FLUSH	include/ssv6200_reg.h	3654;"	d
+GET_CH7_WRFF_FLUSH	include/ssv6200_reg.h	3739;"	d
+GET_CH8_FFO_FULL	include/ssv6200_reg.h	3687;"	d
+GET_CH8_FFO_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	8883;"	d
+GET_CH8_FULL	include/ssv6200_reg.h	3577;"	d
+GET_CH8_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	8771;"	d
+GET_CH8_HALT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	8805;"	d
+GET_CH8_LOWTHOLD	include/ssv6200_reg.h	3720;"	d
+GET_CH8_LOWTHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	8916;"	d
+GET_CH8_LOWTHOLD_INT	include/ssv6200_reg.h	3703;"	d
+GET_CH8_LOWTHOLD_INT	smac/hal/ssv6006c/ssv6006C_reg.h	8899;"	d
+GET_CH8_QUEUE_FLUSH	include/ssv6200_reg.h	3655;"	d
+GET_CH8_WRFF_FLUSH	include/ssv6200_reg.h	3740;"	d
+GET_CH9_FFO_FULL	include/ssv6200_reg.h	3688;"	d
+GET_CH9_FFO_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	8884;"	d
+GET_CH9_FULL	include/ssv6200_reg.h	3578;"	d
+GET_CH9_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	8772;"	d
+GET_CH9_HALT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	8806;"	d
+GET_CH9_LOWTHOLD	include/ssv6200_reg.h	3721;"	d
+GET_CH9_LOWTHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	8917;"	d
+GET_CH9_LOWTHOLD_INT	include/ssv6200_reg.h	3704;"	d
+GET_CH9_LOWTHOLD_INT	smac/hal/ssv6006c/ssv6006C_reg.h	8900;"	d
+GET_CH9_QUEUE_FLUSH	include/ssv6200_reg.h	3656;"	d
+GET_CH9_WRFF_FLUSH	include/ssv6200_reg.h	3741;"	d
+GET_CHECK_SUM	include/ssv6200_reg.h	2537;"	d
+GET_CHECK_SUM	smac/hal/ssv6006c/ssv6006C_reg.h	3275;"	d
+GET_CHECK_SUM_FAIL	include/ssv6200_reg.h	2394;"	d
+GET_CHECK_SUM_TAG	include/ssv6200_reg.h	2413;"	d
+GET_CHIP_DATE_00HHMMSS	smac/hal/ssv6006c/ssv6006C_reg.h	2471;"	d
+GET_CHIP_DATE_YYYYMMDD	smac/hal/ssv6006c/ssv6006C_reg.h	2470;"	d
+GET_CHIP_GITSHA_127_96	smac/hal/ssv6006c/ssv6006C_reg.h	2475;"	d
+GET_CHIP_GITSHA_159_128	smac/hal/ssv6006c/ssv6006C_reg.h	2476;"	d
+GET_CHIP_GITSHA_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	2472;"	d
+GET_CHIP_GITSHA_63_32	smac/hal/ssv6006c/ssv6006C_reg.h	2473;"	d
+GET_CHIP_GITSHA_95_64	smac/hal/ssv6006c/ssv6006C_reg.h	2474;"	d
+GET_CHIP_ID_127_96	include/ssv6200_reg.h	1297;"	d
+GET_CHIP_ID_127_96	smac/hal/ssv6006c/ssv6006C_reg.h	2376;"	d
+GET_CHIP_ID_31_0	include/ssv6200_reg.h	1294;"	d
+GET_CHIP_ID_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	2373;"	d
+GET_CHIP_ID_63_32	include/ssv6200_reg.h	1295;"	d
+GET_CHIP_ID_63_32	smac/hal/ssv6006c/ssv6006C_reg.h	2374;"	d
+GET_CHIP_ID_95_64	include/ssv6200_reg.h	1296;"	d
+GET_CHIP_ID_95_64	smac/hal/ssv6006c/ssv6006C_reg.h	2375;"	d
+GET_CHIP_INFO_FPGA_TAG	smac/hal/ssv6006c/ssv6006C_reg.h	2480;"	d
+GET_CHIP_INFO_ID_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	2466;"	d
+GET_CHIP_INFO_ID_63_32	smac/hal/ssv6006c/ssv6006C_reg.h	2467;"	d
+GET_CHIP_TYPE	smac/hal/ssv6006c/ssv6006C_reg.h	2469;"	d
+GET_CHIP_VER	smac/hal/ssv6006c/ssv6006C_reg.h	2468;"	d
+GET_CH_ARB_EN	include/ssv6200_reg.h	3815;"	d
+GET_CH_ARB_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8998;"	d
+GET_CH_PRI1	include/ssv6200_reg.h	3816;"	d
+GET_CH_PRI1	smac/hal/ssv6006c/ssv6006C_reg.h	8999;"	d
+GET_CH_PRI2	include/ssv6200_reg.h	3817;"	d
+GET_CH_PRI2	smac/hal/ssv6006c/ssv6006C_reg.h	9000;"	d
+GET_CH_PRI3	include/ssv6200_reg.h	3818;"	d
+GET_CH_PRI3	smac/hal/ssv6006c/ssv6006C_reg.h	9001;"	d
+GET_CH_PRI4	include/ssv6200_reg.h	3819;"	d
+GET_CH_PRI4	smac/hal/ssv6006c/ssv6006C_reg.h	9002;"	d
+GET_CH_STA0_DUR	include/ssv6200_reg.h	2821;"	d
+GET_CH_STA1_DUR	include/ssv6200_reg.h	2832;"	d
+GET_CH_STA2_DUR	include/ssv6200_reg.h	2833;"	d
+GET_CH_STA3_DUR	include/ssv6200_reg.h	2839;"	d
+GET_CH_STA4_DUR	include/ssv6200_reg.h	2840;"	d
+GET_CH_ST_FSM	include/ssv6200_reg.h	2804;"	d
+GET_CK_SEL_1_0	include/ssv6200_reg.h	1298;"	d
+GET_CK_SEL_2	include/ssv6200_reg.h	1299;"	d
+GET_CLK_DIGI_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	2377;"	d
+GET_CLK_EN_160M_PHY	smac/hal/ssv6006c/ssv6006C_reg.h	2412;"	d
+GET_CLK_EN_CPUN10	smac/hal/ssv6006c/ssv6006C_reg.h	2462;"	d
+GET_CLK_EN_MBIST	smac/hal/ssv6006c/ssv6006C_reg.h	2414;"	d
+GET_CLK_EN_PHYRF40M	smac/hal/ssv6006c/ssv6006C_reg.h	2410;"	d
+GET_CLK_EN_PHYRF80M	smac/hal/ssv6006c/ssv6006C_reg.h	2411;"	d
+GET_CLK_EN_USB_CTRLUTMI	smac/hal/ssv6006c/ssv6006C_reg.h	2406;"	d
+GET_CLK_EN_USB_PHY30M	smac/hal/ssv6006c/ssv6006C_reg.h	2405;"	d
+GET_CLK_FBUS_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	2432;"	d
+GET_CLK_USB_PHY30M_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	2378;"	d
+GET_CLK_WIDTH	include/ssv6200_reg.h	2053;"	d
+GET_CLK_WIDTH	smac/hal/ssv6006c/ssv6006C_reg.h	2765;"	d
+GET_CLR	include/ssv6200_reg.h	2549;"	d
+GET_CLR	smac/hal/ssv6006c/ssv6006C_reg.h	3287;"	d
+GET_CMD52_ABORT_ACTIVE	include/ssv6200_reg.h	1901;"	d
+GET_CMD52_ABORT_RESPONSE	include/ssv6200_reg.h	1896;"	d
+GET_CMD52_ABORT_RESPONSE	smac/hal/ssv6006c/ssv6006C_reg.h	2679;"	d
+GET_CMD52_RD_ABORT_CNT	include/ssv6200_reg.h	1953;"	d
+GET_CMD52_RESET_ACTIVE	include/ssv6200_reg.h	1902;"	d
+GET_CMD52_WR_ABORT_CNT	include/ssv6200_reg.h	1954;"	d
+GET_CMD_ADDR	include/ssv6200_reg.h	2415;"	d
+GET_CMD_LEN	include/ssv6200_reg.h	2414;"	d
+GET_CMD_LEN_SPIMAS	smac/hal/ssv6006c/ssv6006C_reg.h	3357;"	d
+GET_CMD_LOG_PART1	include/ssv6200_reg.h	1985;"	d
+GET_CMD_LOG_PART2	include/ssv6200_reg.h	1986;"	d
+GET_COEXIST_EN	include/ssv6200_reg.h	3106;"	d
+GET_COEXIST_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3945;"	d
+GET_COMMAND_COUNTER	include/ssv6200_reg.h	1984;"	d
+GET_COMMON_CIS_PONTER	include/ssv6200_reg.h	2007;"	d
+GET_COMMON_CIS_PONTER	smac/hal/ssv6006c/ssv6006C_reg.h	2721;"	d
+GET_CONDI_NUM	include/ssv6200_reg.h	2049;"	d
+GET_CONTINUE_R_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2965;"	d
+GET_CORRECT_RATE_REP_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	3253;"	d
+GET_CO_PROC_CLK_EN	include/ssv6200_reg.h	3060;"	d
+GET_CO_PROC_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3892;"	d
+GET_CO_PROC_CSR_CLK_EN	include/ssv6200_reg.h	3081;"	d
+GET_CO_PROC_CSR_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3913;"	d
+GET_CO_PROC_CSR_RST	include/ssv6200_reg.h	3046;"	d
+GET_CO_PROC_CSR_RST	smac/hal/ssv6006c/ssv6006C_reg.h	3878;"	d
+GET_CO_PROC_ENG_CLK_EN	include/ssv6200_reg.h	3072;"	d
+GET_CO_PROC_ENG_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3904;"	d
+GET_CO_PROC_ENG_RST	include/ssv6200_reg.h	3035;"	d
+GET_CO_PROC_ENG_RST	smac/hal/ssv6006c/ssv6006C_reg.h	3867;"	d
+GET_CO_PROC_SW_RST	include/ssv6200_reg.h	3023;"	d
+GET_CO_PROC_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	3854;"	d
+GET_CPHA	smac/hal/ssv6006c/ssv6006C_reg.h	3348;"	d
+GET_CPOL	smac/hal/ssv6006c/ssv6006C_reg.h	3347;"	d
+GET_CPU_ID_TB0	include/ssv6200_reg.h	3542;"	d
+GET_CPU_ID_TB0	smac/hal/ssv6006c/ssv6006C_reg.h	8731;"	d
+GET_CPU_ID_TB1	include/ssv6200_reg.h	3543;"	d
+GET_CPU_ID_TB1	smac/hal/ssv6006c/ssv6006C_reg.h	8732;"	d
+GET_CPU_ID_TB2	include/ssv6200_reg.h	3747;"	d
+GET_CPU_ID_TB2	smac/hal/ssv6006c/ssv6006C_reg.h	8931;"	d
+GET_CPU_ID_TB3	include/ssv6200_reg.h	3748;"	d
+GET_CPU_ID_TB3	smac/hal/ssv6006c/ssv6006C_reg.h	8932;"	d
+GET_CPU_INT	include/ssv6200_reg.h	3541;"	d
+GET_CPU_INT	smac/hal/ssv6006c/ssv6006C_reg.h	8730;"	d
+GET_CPU_INT_ALT	smac/hal/ssv6006c/ssv6006C_reg.h	8728;"	d
+GET_CPU_POR0	include/ssv6200_reg.h	4815;"	d
+GET_CPU_POR1	include/ssv6200_reg.h	4816;"	d
+GET_CPU_POR2	include/ssv6200_reg.h	4817;"	d
+GET_CPU_POR3	include/ssv6200_reg.h	4818;"	d
+GET_CPU_POR4	include/ssv6200_reg.h	4819;"	d
+GET_CPU_POR5	include/ssv6200_reg.h	4820;"	d
+GET_CPU_POR6	include/ssv6200_reg.h	4821;"	d
+GET_CPU_POR7	include/ssv6200_reg.h	4822;"	d
+GET_CPU_POR8	include/ssv6200_reg.h	4823;"	d
+GET_CPU_POR9	include/ssv6200_reg.h	4824;"	d
+GET_CPU_PORA	include/ssv6200_reg.h	4825;"	d
+GET_CPU_PORB	include/ssv6200_reg.h	4826;"	d
+GET_CPU_PORC	include/ssv6200_reg.h	4827;"	d
+GET_CPU_PORD	include/ssv6200_reg.h	4828;"	d
+GET_CPU_PORE	include/ssv6200_reg.h	4829;"	d
+GET_CPU_PORF	include/ssv6200_reg.h	4830;"	d
+GET_CPU_QUE_POP	include/ssv6200_reg.h	3540;"	d
+GET_CPU_QUE_POP	smac/hal/ssv6006c/ssv6006C_reg.h	8729;"	d
+GET_CPU_QUE_POP_ALT	smac/hal/ssv6006c/ssv6006C_reg.h	8727;"	d
+GET_CRC_CNT	include/ssv6200_reg.h	4181;"	d
+GET_CRC_CORRECT	include/ssv6200_reg.h	4191;"	d
+GET_CRYSTAL_OUT_REQ_SEL	include/ssv6200_reg.h	1851;"	d
+GET_CSASUPPORT	include/ssv6200_reg.h	2011;"	d
+GET_CSASUPPORT	smac/hal/ssv6006c/ssv6006C_reg.h	2727;"	d
+GET_CSN_DLY	smac/hal/ssv6006c/ssv6006C_reg.h	2956;"	d
+GET_CSN_INTER	include/ssv6200_reg.h	2054;"	d
+GET_CSN_INTER	smac/hal/ssv6006c/ssv6006C_reg.h	2766;"	d
+GET_CSPOL	smac/hal/ssv6006c/ssv6006C_reg.h	3349;"	d
+GET_CSR_PHY_INFO	include/ssv6200_reg.h	2738;"	d
+GET_CSR_PHY_INFO	smac/hal/ssv6006c/ssv6006C_reg.h	3458;"	d
+GET_CSTATE	include/ssv6200_reg.h	4311;"	d
+GET_CS_ADDER_EN	include/ssv6200_reg.h	2532;"	d
+GET_CS_ADDER_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3270;"	d
+GET_CS_PKT_ID	include/ssv6200_reg.h	2530;"	d
+GET_CS_PKT_ID	smac/hal/ssv6006c/ssv6006C_reg.h	3268;"	d
+GET_CS_START_ADDR	include/ssv6200_reg.h	2529;"	d
+GET_CS_START_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	3267;"	d
+GET_CTS	include/ssv6200_reg.h	2152;"	d
+GET_CTS	smac/hal/ssv6006c/ssv6006C_reg.h	2863;"	d
+GET_CTYPE_RATE_RPT	smac/hal/ssv6006c/ssv6006C_reg.h	3571;"	d
+GET_D2_DMA_ADR_DST	include/ssv6200_reg.h	2459;"	d
+GET_D2_DMA_ADR_DST	smac/hal/ssv6006c/ssv6006C_reg.h	3004;"	d
+GET_D2_DMA_ADR_SRC	include/ssv6200_reg.h	2458;"	d
+GET_D2_DMA_ADR_SRC	smac/hal/ssv6006c/ssv6006C_reg.h	3003;"	d
+GET_D2_DMA_BADR_EN	include/ssv6200_reg.h	2466;"	d
+GET_D2_DMA_BADR_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3011;"	d
+GET_D2_DMA_CONST	include/ssv6200_reg.h	2471;"	d
+GET_D2_DMA_CONST	smac/hal/ssv6006c/ssv6006C_reg.h	3016;"	d
+GET_D2_DMA_DST_INC	include/ssv6200_reg.h	2463;"	d
+GET_D2_DMA_DST_INC	smac/hal/ssv6006c/ssv6006C_reg.h	3008;"	d
+GET_D2_DMA_DST_SIZE	include/ssv6200_reg.h	2462;"	d
+GET_D2_DMA_DST_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	3007;"	d
+GET_D2_DMA_FAST_FILL	include/ssv6200_reg.h	2464;"	d
+GET_D2_DMA_FAST_FILL	smac/hal/ssv6006c/ssv6006C_reg.h	3009;"	d
+GET_D2_DMA_FINISH	include/ssv6200_reg.h	2470;"	d
+GET_D2_DMA_FINISH	smac/hal/ssv6006c/ssv6006C_reg.h	3015;"	d
+GET_D2_DMA_INT_MASK	include/ssv6200_reg.h	2468;"	d
+GET_D2_DMA_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	3013;"	d
+GET_D2_DMA_LEN	include/ssv6200_reg.h	2467;"	d
+GET_D2_DMA_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	3012;"	d
+GET_D2_DMA_SDIO_KICK	include/ssv6200_reg.h	2465;"	d
+GET_D2_DMA_SDIO_KICK	smac/hal/ssv6006c/ssv6006C_reg.h	3010;"	d
+GET_D2_DMA_SRC_INC	include/ssv6200_reg.h	2461;"	d
+GET_D2_DMA_SRC_INC	smac/hal/ssv6006c/ssv6006C_reg.h	3006;"	d
+GET_D2_DMA_SRC_SIZE	include/ssv6200_reg.h	2460;"	d
+GET_D2_DMA_SRC_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	3005;"	d
+GET_D2_DMA_STS	include/ssv6200_reg.h	2469;"	d
+GET_D2_DMA_STS	smac/hal/ssv6006c/ssv6006C_reg.h	3014;"	d
+GET_DATA_FRAMES	smac/hal/ssv6006c/ssv6006C_reg.h	2322;"	d
+GET_DATA_RATE	include/ssv6200_reg.h	2553;"	d
+GET_DATA_RATE	smac/hal/ssv6006c/ssv6006C_reg.h	3291;"	d
+GET_DATA_RDY	include/ssv6200_reg.h	2140;"	d
+GET_DATA_RDY	smac/hal/ssv6006c/ssv6006C_reg.h	2851;"	d
+GET_DATA_RDY_IE	include/ssv6200_reg.h	2115;"	d
+GET_DATA_RDY_IE	smac/hal/ssv6006c/ssv6006C_reg.h	2825;"	d
+GET_DATA_SPI_RESET	smac/hal/ssv6006c/ssv6006C_reg.h	2489;"	d
+GET_DATA_SPI_WAKEUP	smac/hal/ssv6006c/ssv6006C_reg.h	2483;"	d
+GET_DATA_UART_W2B_EN	include/ssv6200_reg.h	1351;"	d
+GET_DAT_BRDC_DIV	include/ssv6200_reg.h	2203;"	d
+GET_DAT_BREAK_INT	include/ssv6200_reg.h	2191;"	d
+GET_DAT_CD	include/ssv6200_reg.h	2202;"	d
+GET_DAT_CTS	include/ssv6200_reg.h	2199;"	d
+GET_DAT_DATA_RDY	include/ssv6200_reg.h	2187;"	d
+GET_DAT_DATA_RDY_IE	include/ssv6200_reg.h	2162;"	d
+GET_DAT_DELTA_CD	include/ssv6200_reg.h	2198;"	d
+GET_DAT_DELTA_CTS	include/ssv6200_reg.h	2195;"	d
+GET_DAT_DELTA_DSR	include/ssv6200_reg.h	2196;"	d
+GET_DAT_DLAB	include/ssv6200_reg.h	2181;"	d
+GET_DAT_DMA_MODE	include/ssv6200_reg.h	2171;"	d
+GET_DAT_DMA_RXEND_IE	include/ssv6200_reg.h	2166;"	d
+GET_DAT_DMA_TXEND_IE	include/ssv6200_reg.h	2167;"	d
+GET_DAT_DSR	include/ssv6200_reg.h	2200;"	d
+GET_DAT_DTR	include/ssv6200_reg.h	2182;"	d
+GET_DAT_EN_AUTO_CTS	include/ssv6200_reg.h	2173;"	d
+GET_DAT_EN_AUTO_RTS	include/ssv6200_reg.h	2172;"	d
+GET_DAT_EVEN_PARITY	include/ssv6200_reg.h	2178;"	d
+GET_DAT_FIFODATA_ERR	include/ssv6200_reg.h	2194;"	d
+GET_DAT_FIFOS_ENABLED	include/ssv6200_reg.h	2207;"	d
+GET_DAT_FIFO_EN	include/ssv6200_reg.h	2168;"	d
+GET_DAT_FORCE_PARITY	include/ssv6200_reg.h	2179;"	d
+GET_DAT_FRAMING_ERR	include/ssv6200_reg.h	2190;"	d
+GET_DAT_INT_IDCODE	include/ssv6200_reg.h	2206;"	d
+GET_DAT_LOOP_BACK	include/ssv6200_reg.h	2186;"	d
+GET_DAT_MDM_STS_IE	include/ssv6200_reg.h	2165;"	d
+GET_DAT_MODE_OFF	include/ssv6200_reg.h	2082;"	d
+GET_DAT_OUT_1	include/ssv6200_reg.h	2184;"	d
+GET_DAT_OUT_2	include/ssv6200_reg.h	2185;"	d
+GET_DAT_OUT_EDGE	include/ssv6200_reg.h	1932;"	d
+GET_DAT_OVERRUN_ERR	include/ssv6200_reg.h	2188;"	d
+GET_DAT_PARITY_EN	include/ssv6200_reg.h	2177;"	d
+GET_DAT_PARITY_ERR	include/ssv6200_reg.h	2189;"	d
+GET_DAT_RI	include/ssv6200_reg.h	2201;"	d
+GET_DAT_RTHR_H	include/ssv6200_reg.h	2205;"	d
+GET_DAT_RTHR_L	include/ssv6200_reg.h	2204;"	d
+GET_DAT_RTS	include/ssv6200_reg.h	2183;"	d
+GET_DAT_RXFIFO_RST	include/ssv6200_reg.h	2169;"	d
+GET_DAT_RXFIFO_TRGLVL	include/ssv6200_reg.h	2174;"	d
+GET_DAT_RX_LINESTS_IE	include/ssv6200_reg.h	2164;"	d
+GET_DAT_SET_BREAK	include/ssv6200_reg.h	2180;"	d
+GET_DAT_STOP_BIT	include/ssv6200_reg.h	2176;"	d
+GET_DAT_THR_EMPTY	include/ssv6200_reg.h	2192;"	d
+GET_DAT_THR_EMPTY_IE	include/ssv6200_reg.h	2163;"	d
+GET_DAT_TRAILEDGE_RI	include/ssv6200_reg.h	2197;"	d
+GET_DAT_TXFIFO_RST	include/ssv6200_reg.h	2170;"	d
+GET_DAT_TX_EMPTY	include/ssv6200_reg.h	2193;"	d
+GET_DAT_UART_DATA	include/ssv6200_reg.h	2161;"	d
+GET_DAT_UART_MULTI_IRQ	include/ssv6200_reg.h	2273;"	d
+GET_DAT_UART_MULTI_IRQ_SD	include/ssv6200_reg.h	2342;"	d
+GET_DAT_UART_NCTS_SEL	include/ssv6200_reg.h	1856;"	d
+GET_DAT_UART_RXD_SEL_0	include/ssv6200_reg.h	1866;"	d
+GET_DAT_UART_RXD_SEL_1	include/ssv6200_reg.h	1867;"	d
+GET_DAT_UART_RX_TIMEOUT	include/ssv6200_reg.h	2272;"	d
+GET_DAT_UART_RX_TIMEOUT_SD	include/ssv6200_reg.h	2341;"	d
+GET_DAT_UART_SW_RST	include/ssv6200_reg.h	1288;"	d
+GET_DAT_UART_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	2367;"	d
+GET_DAT_WORD_LEN	include/ssv6200_reg.h	2175;"	d
+GET_DA_R_CAL_CODE	include/ssv6200_reg.h	4783;"	d
+GET_DA_R_CODE_LUT	include/ssv6200_reg.h	4776;"	d
+GET_DA_SX_SUB_SEL	include/ssv6200_reg.h	4784;"	d
+GET_DBG_ADDR_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3201;"	d
+GET_DBG_ADDR_FENCE	smac/hal/ssv6006c/ssv6006C_reg.h	3202;"	d
+GET_DBG_ALC_LOG_EN	include/ssv6200_reg.h	3608;"	d
+GET_DBG_ALC_LOG_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8817;"	d
+GET_DBG_AMPDU_FAIL	include/ssv6200_reg.h	3204;"	d
+GET_DBG_AMPDU_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	4052;"	d
+GET_DBG_AMPDU_PASS	include/ssv6200_reg.h	3203;"	d
+GET_DBG_AMPDU_PASS	smac/hal/ssv6006c/ssv6006C_reg.h	4051;"	d
+GET_DBG_BACK_DLY	include/ssv6200_reg.h	2353;"	d
+GET_DBG_BA_SEQ	include/ssv6200_reg.h	2656;"	d
+GET_DBG_BA_SEQ	smac/hal/ssv6006c/ssv6006C_reg.h	3380;"	d
+GET_DBG_BA_TYPE	include/ssv6200_reg.h	2655;"	d
+GET_DBG_BA_TYPE	smac/hal/ssv6006c/ssv6006C_reg.h	3379;"	d
+GET_DBG_BRST_MODE	include/ssv6200_reg.h	2350;"	d
+GET_DBG_CFRM_BUSY	include/ssv6200_reg.h	2813;"	d
+GET_DBG_CLK_WIDTH	include/ssv6200_reg.h	2351;"	d
+GET_DBG_CONDI_NUM	include/ssv6200_reg.h	2347;"	d
+GET_DBG_CSN_INTER	include/ssv6200_reg.h	2352;"	d
+GET_DBG_DAT_MODE_OFF	include/ssv6200_reg.h	2380;"	d
+GET_DBG_DMA_RDY	include/ssv6200_reg.h	2811;"	d
+GET_DBG_EDCA0_LOWTHOLD_INT	include/ssv6200_reg.h	2385;"	d
+GET_DBG_EDCA1_LOWTHOLD_INT	include/ssv6200_reg.h	2386;"	d
+GET_DBG_EDCA2_LOWTHOLD_INT	include/ssv6200_reg.h	2387;"	d
+GET_DBG_EDCA3_LOWTHOLD_INT	include/ssv6200_reg.h	2388;"	d
+GET_DBG_FF_FULL	include/ssv6200_reg.h	2688;"	d
+GET_DBG_FF_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	3412;"	d
+GET_DBG_FF_FULL_CLR	include/ssv6200_reg.h	2689;"	d
+GET_DBG_FF_FULL_CLR	smac/hal/ssv6006c/ssv6006C_reg.h	3413;"	d
+GET_DBG_FRONT_DLY	include/ssv6200_reg.h	2354;"	d
+GET_DBG_HOST_PATH	include/ssv6200_reg.h	2348;"	d
+GET_DBG_HWID0_RD_EN	include/ssv6200_reg.h	3630;"	d
+GET_DBG_HWID0_RD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8839;"	d
+GET_DBG_HWID0_WR_EN	include/ssv6200_reg.h	3614;"	d
+GET_DBG_HWID0_WR_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8823;"	d
+GET_DBG_HWID10_RD_EN	include/ssv6200_reg.h	3640;"	d
+GET_DBG_HWID10_RD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8849;"	d
+GET_DBG_HWID10_WR_EN	include/ssv6200_reg.h	3624;"	d
+GET_DBG_HWID10_WR_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8833;"	d
+GET_DBG_HWID11_RD_EN	include/ssv6200_reg.h	3641;"	d
+GET_DBG_HWID11_RD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8850;"	d
+GET_DBG_HWID11_WR_EN	include/ssv6200_reg.h	3625;"	d
+GET_DBG_HWID11_WR_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8834;"	d
+GET_DBG_HWID12_RD_EN	include/ssv6200_reg.h	3642;"	d
+GET_DBG_HWID12_RD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8851;"	d
+GET_DBG_HWID12_WR_EN	include/ssv6200_reg.h	3626;"	d
+GET_DBG_HWID12_WR_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8835;"	d
+GET_DBG_HWID13_RD_EN	include/ssv6200_reg.h	3643;"	d
+GET_DBG_HWID13_RD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8852;"	d
+GET_DBG_HWID13_WR_EN	include/ssv6200_reg.h	3627;"	d
+GET_DBG_HWID13_WR_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8836;"	d
+GET_DBG_HWID14_RD_EN	include/ssv6200_reg.h	3644;"	d
+GET_DBG_HWID14_RD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8853;"	d
+GET_DBG_HWID14_WR_EN	include/ssv6200_reg.h	3628;"	d
+GET_DBG_HWID14_WR_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8837;"	d
+GET_DBG_HWID15_RD_EN	include/ssv6200_reg.h	3645;"	d
+GET_DBG_HWID15_RD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8854;"	d
+GET_DBG_HWID15_WR_EN	include/ssv6200_reg.h	3629;"	d
+GET_DBG_HWID15_WR_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8838;"	d
+GET_DBG_HWID1_RD_EN	include/ssv6200_reg.h	3631;"	d
+GET_DBG_HWID1_RD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8840;"	d
+GET_DBG_HWID1_WR_EN	include/ssv6200_reg.h	3615;"	d
+GET_DBG_HWID1_WR_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8824;"	d
+GET_DBG_HWID2_RD_EN	include/ssv6200_reg.h	3632;"	d
+GET_DBG_HWID2_RD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8841;"	d
+GET_DBG_HWID2_WR_EN	include/ssv6200_reg.h	3616;"	d
+GET_DBG_HWID2_WR_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8825;"	d
+GET_DBG_HWID3_RD_EN	include/ssv6200_reg.h	3633;"	d
+GET_DBG_HWID3_RD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8842;"	d
+GET_DBG_HWID3_WR_EN	include/ssv6200_reg.h	3617;"	d
+GET_DBG_HWID3_WR_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8826;"	d
+GET_DBG_HWID4_RD_EN	include/ssv6200_reg.h	3634;"	d
+GET_DBG_HWID4_RD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8843;"	d
+GET_DBG_HWID4_WR_EN	include/ssv6200_reg.h	3618;"	d
+GET_DBG_HWID4_WR_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8827;"	d
+GET_DBG_HWID5_RD_EN	include/ssv6200_reg.h	3635;"	d
+GET_DBG_HWID5_RD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8844;"	d
+GET_DBG_HWID5_WR_EN	include/ssv6200_reg.h	3619;"	d
+GET_DBG_HWID5_WR_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8828;"	d
+GET_DBG_HWID6_RD_EN	include/ssv6200_reg.h	3636;"	d
+GET_DBG_HWID6_RD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8845;"	d
+GET_DBG_HWID6_WR_EN	include/ssv6200_reg.h	3620;"	d
+GET_DBG_HWID6_WR_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8829;"	d
+GET_DBG_HWID7_RD_EN	include/ssv6200_reg.h	3637;"	d
+GET_DBG_HWID7_RD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8846;"	d
+GET_DBG_HWID7_WR_EN	include/ssv6200_reg.h	3621;"	d
+GET_DBG_HWID7_WR_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8830;"	d
+GET_DBG_HWID8_RD_EN	include/ssv6200_reg.h	3638;"	d
+GET_DBG_HWID8_RD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8847;"	d
+GET_DBG_HWID8_WR_EN	include/ssv6200_reg.h	3622;"	d
+GET_DBG_HWID8_WR_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8831;"	d
+GET_DBG_HWID9_RD_EN	include/ssv6200_reg.h	3639;"	d
+GET_DBG_HWID9_RD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8848;"	d
+GET_DBG_HWID9_WR_EN	include/ssv6200_reg.h	3623;"	d
+GET_DBG_HWID9_WR_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8832;"	d
+GET_DBG_JUDGE_CNT	include/ssv6200_reg.h	2370;"	d
+GET_DBG_JUDGE_CNT_CLR	include/ssv6200_reg.h	2373;"	d
+GET_DBG_LEN_ALC_FAIL	include/ssv6200_reg.h	3202;"	d
+GET_DBG_LEN_ALC_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	4050;"	d
+GET_DBG_LEN_CRC_FAIL	include/ssv6200_reg.h	3201;"	d
+GET_DBG_LEN_CRC_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	4049;"	d
+GET_DBG_MB_FULL	include/ssv6200_reg.h	2692;"	d
+GET_DBG_MB_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	3416;"	d
+GET_DBG_MB_FULL_CLR	include/ssv6200_reg.h	2693;"	d
+GET_DBG_MB_FULL_CLR	smac/hal/ssv6006c/ssv6006C_reg.h	3417;"	d
+GET_DBG_MODE	include/ssv6200_reg.h	2815;"	d
+GET_DBG_MTX_IGNORE_NAV	smac/hal/ssv6006c/ssv6006C_reg.h	3580;"	d
+GET_DBG_PHYTXIP_TIMEOUT_RECOVERY	smac/hal/ssv6006c/ssv6006C_reg.h	3579;"	d
+GET_DBG_PHYTX_PROCEED	smac/hal/ssv6006c/ssv6006C_reg.h	3519;"	d
+GET_DBG_PRTC_PRD	include/ssv6200_reg.h	2810;"	d
+GET_DBG_Q0_ACK_FAIL	include/ssv6200_reg.h	3183;"	d
+GET_DBG_Q0_ACK_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	4031;"	d
+GET_DBG_Q0_ACK_SUCC	include/ssv6200_reg.h	3182;"	d
+GET_DBG_Q0_ACK_SUCC	smac/hal/ssv6006c/ssv6006C_reg.h	4030;"	d
+GET_DBG_Q0_FAIL	include/ssv6200_reg.h	3181;"	d
+GET_DBG_Q0_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	4029;"	d
+GET_DBG_Q0_SUCC	include/ssv6200_reg.h	3180;"	d
+GET_DBG_Q0_SUCC	smac/hal/ssv6006c/ssv6006C_reg.h	4028;"	d
+GET_DBG_Q1_ACK_FAIL	include/ssv6200_reg.h	3187;"	d
+GET_DBG_Q1_ACK_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	4035;"	d
+GET_DBG_Q1_ACK_SUCC	include/ssv6200_reg.h	3186;"	d
+GET_DBG_Q1_ACK_SUCC	smac/hal/ssv6006c/ssv6006C_reg.h	4034;"	d
+GET_DBG_Q1_FAIL	include/ssv6200_reg.h	3185;"	d
+GET_DBG_Q1_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	4033;"	d
+GET_DBG_Q1_SUCC	include/ssv6200_reg.h	3184;"	d
+GET_DBG_Q1_SUCC	smac/hal/ssv6006c/ssv6006C_reg.h	4032;"	d
+GET_DBG_Q2_ACK_FAIL	include/ssv6200_reg.h	3191;"	d
+GET_DBG_Q2_ACK_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	4039;"	d
+GET_DBG_Q2_ACK_SUCC	include/ssv6200_reg.h	3190;"	d
+GET_DBG_Q2_ACK_SUCC	smac/hal/ssv6006c/ssv6006C_reg.h	4038;"	d
+GET_DBG_Q2_FAIL	include/ssv6200_reg.h	3189;"	d
+GET_DBG_Q2_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	4037;"	d
+GET_DBG_Q2_SUCC	include/ssv6200_reg.h	3188;"	d
+GET_DBG_Q2_SUCC	smac/hal/ssv6006c/ssv6006C_reg.h	4036;"	d
+GET_DBG_Q3_ACK_FAIL	include/ssv6200_reg.h	3195;"	d
+GET_DBG_Q3_ACK_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	4043;"	d
+GET_DBG_Q3_ACK_SUCC	include/ssv6200_reg.h	3194;"	d
+GET_DBG_Q3_ACK_SUCC	smac/hal/ssv6006c/ssv6006C_reg.h	4042;"	d
+GET_DBG_Q3_FAIL	include/ssv6200_reg.h	3193;"	d
+GET_DBG_Q3_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	4041;"	d
+GET_DBG_Q3_SUCC	include/ssv6200_reg.h	3192;"	d
+GET_DBG_Q3_SUCC	smac/hal/ssv6006c/ssv6006C_reg.h	4040;"	d
+GET_DBG_RDATA_RDY	include/ssv6200_reg.h	2361;"	d
+GET_DBG_RD_DAT_CNT	include/ssv6200_reg.h	2368;"	d
+GET_DBG_RD_DAT_CNT_CLR	include/ssv6200_reg.h	2372;"	d
+GET_DBG_RD_STS_CNT	include/ssv6200_reg.h	2369;"	d
+GET_DBG_RD_STS_CNT_CLR	include/ssv6200_reg.h	2371;"	d
+GET_DBG_RST	include/ssv6200_reg.h	2814;"	d
+GET_DBG_RX_FIFO_FAIL	include/ssv6200_reg.h	2355;"	d
+GET_DBG_RX_FIFO_RESIDUE	include/ssv6200_reg.h	2382;"	d
+GET_DBG_RX_HOST_FAIL	include/ssv6200_reg.h	2356;"	d
+GET_DBG_RX_LEN	include/ssv6200_reg.h	2364;"	d
+GET_DBG_RX_QUOTA	include/ssv6200_reg.h	2346;"	d
+GET_DBG_RX_RDY	include/ssv6200_reg.h	2383;"	d
+GET_DBG_SDIO_SYS_INT	include/ssv6200_reg.h	2384;"	d
+GET_DBG_SPI_ALLOC_STATUS	include/ssv6200_reg.h	2362;"	d
+GET_DBG_SPI_CLK_EN_INT	include/ssv6200_reg.h	2391;"	d
+GET_DBG_SPI_DBG_WR_FIFO_FULL	include/ssv6200_reg.h	2363;"	d
+GET_DBG_SPI_DOUBLE_ALLOC	include/ssv6200_reg.h	2359;"	d
+GET_DBG_SPI_FN1	include/ssv6200_reg.h	2390;"	d
+GET_DBG_SPI_HOST_MASK	include/ssv6200_reg.h	2392;"	d
+GET_DBG_SPI_HOST_TX_ALLOC_PKBUF	include/ssv6200_reg.h	2366;"	d
+GET_DBG_SPI_MODE	include/ssv6200_reg.h	2345;"	d
+GET_DBG_SPI_TX_ALLOC_SIZE	include/ssv6200_reg.h	2367;"	d
+GET_DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS	include/ssv6200_reg.h	2365;"	d
+GET_DBG_SPI_TX_NO_ALLOC	include/ssv6200_reg.h	2360;"	d
+GET_DBG_TX_DISCARD_CNT	include/ssv6200_reg.h	2375;"	d
+GET_DBG_TX_DISCARD_CNT_CLR	include/ssv6200_reg.h	2377;"	d
+GET_DBG_TX_DONE_CNT	include/ssv6200_reg.h	2374;"	d
+GET_DBG_TX_DONE_CNT_CLR	include/ssv6200_reg.h	2378;"	d
+GET_DBG_TX_FIFO_FAIL	include/ssv6200_reg.h	2357;"	d
+GET_DBG_TX_FIFO_RESIDUE	include/ssv6200_reg.h	2381;"	d
+GET_DBG_TX_HOST_FAIL	include/ssv6200_reg.h	2358;"	d
+GET_DBG_TX_LIMIT_INT_IN	include/ssv6200_reg.h	2389;"	d
+GET_DBG_TX_SEG	include/ssv6200_reg.h	2349;"	d
+GET_DBG_TX_SET_CNT	include/ssv6200_reg.h	2376;"	d
+GET_DBG_TX_SET_CNT_CLR	include/ssv6200_reg.h	2379;"	d
+GET_DBG_TYPE	include/ssv6200_reg.h	3606;"	d
+GET_DBG_TYPE	smac/hal/ssv6006c/ssv6006C_reg.h	8815;"	d
+GET_DBG_WAIT_RSP	include/ssv6200_reg.h	2812;"	d
+GET_DBG_WFF_FULL	include/ssv6200_reg.h	2690;"	d
+GET_DBG_WFF_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	3414;"	d
+GET_DBG_WFF_FULL_CLR	include/ssv6200_reg.h	2691;"	d
+GET_DBG_WFF_FULL_CLR	smac/hal/ssv6006c/ssv6006C_reg.h	3415;"	d
+GET_DBG_WRITE_TO_FINISH_SIM	smac/hal/ssv6006c/ssv6006C_reg.h	2482;"	d
+GET_DBIST_MODE	include/ssv6200_reg.h	1341;"	d
+GET_DB_AD_ADC_I_OUT	smac/hal/ssv6006c/ssv6006C_reg.h	7104;"	d
+GET_DB_AD_ADC_Q_OUT	smac/hal/ssv6006c/ssv6006C_reg.h	7105;"	d
+GET_DB_AD_DP_VT_MON_Q	smac/hal/ssv6006c/ssv6006C_reg.h	7113;"	d
+GET_DB_AD_IOT_ADC_OUT	smac/hal/ssv6006c/ssv6006C_reg.h	7114;"	d
+GET_DB_AD_RX_RSSIADC	smac/hal/ssv6006c/ssv6006C_reg.h	7106;"	d
+GET_DB_AD_SX5GB_AAC_COMPOUT	smac/hal/ssv6006c/ssv6006C_reg.h	7525;"	d
+GET_DB_DA_SARADC_BIT	smac/hal/ssv6006c/ssv6006C_reg.h	7107;"	d
+GET_DB_DA_SX5GB_SUB_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	7519;"	d
+GET_DB_DA_SX5GB_VCO_ISEL	smac/hal/ssv6006c/ssv6006C_reg.h	7520;"	d
+GET_DB_DA_SXMIX_GMSEL	smac/hal/ssv6006c/ssv6006C_reg.h	7522;"	d
+GET_DB_DA_SXMIX_SCA_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	7521;"	d
+GET_DB_DA_SXREP_CSSEL	smac/hal/ssv6006c/ssv6006C_reg.h	7524;"	d
+GET_DB_DA_SXREP_SCA_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	7523;"	d
+GET_DB_DA_SX_SUB_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	7109;"	d
+GET_DB_DA_SX_VCO_ISEL	smac/hal/ssv6006c/ssv6006C_reg.h	7110;"	d
+GET_DB_GEMINIA_AD_ADC_I_OUT	smac/hal/ssv6006c/ssv6006C_reg.h	4823;"	d
+GET_DB_GEMINIA_AD_ADC_Q_OUT	smac/hal/ssv6006c/ssv6006C_reg.h	4824;"	d
+GET_DB_GEMINIA_AD_DP_VT_MON_Q	smac/hal/ssv6006c/ssv6006C_reg.h	4832;"	d
+GET_DB_GEMINIA_AD_RX_RSSIADC	smac/hal/ssv6006c/ssv6006C_reg.h	4825;"	d
+GET_DB_GEMINIA_DA_SARADC_BIT	smac/hal/ssv6006c/ssv6006C_reg.h	4826;"	d
+GET_DB_GEMINIA_DA_SX_SUB_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	4828;"	d
+GET_DB_GEMINIA_DA_SX_VCO_ISEL	smac/hal/ssv6006c/ssv6006C_reg.h	4829;"	d
+GET_DB_GEMINIA_SX_SBCAL_NCOUNT	smac/hal/ssv6006c/ssv6006C_reg.h	4833;"	d
+GET_DB_GEMINIA_SX_SBCAL_NTARGET	smac/hal/ssv6006c/ssv6006C_reg.h	4834;"	d
+GET_DB_GEMINIA_SX_TTL_VT_DET	smac/hal/ssv6006c/ssv6006C_reg.h	4831;"	d
+GET_DB_GEMINIA_VO_AAC_COMPOUT	smac/hal/ssv6006c/ssv6006C_reg.h	4830;"	d
+GET_DB_SX5GB_SBCAL_NCOUNT	smac/hal/ssv6006c/ssv6006C_reg.h	7531;"	d
+GET_DB_SX5GB_SBCAL_NTARGET	smac/hal/ssv6006c/ssv6006C_reg.h	7532;"	d
+GET_DB_SX5GB_TTL_VT_DET	smac/hal/ssv6006c/ssv6006C_reg.h	7526;"	d
+GET_DB_SXMIX_SCA_SEL_A1	smac/hal/ssv6006c/ssv6006C_reg.h	7527;"	d
+GET_DB_SXMIX_SCA_SEL_A2	smac/hal/ssv6006c/ssv6006C_reg.h	7528;"	d
+GET_DB_SXREP_SCA_SEL_B1	smac/hal/ssv6006c/ssv6006C_reg.h	7529;"	d
+GET_DB_SXREP_SCA_SEL_B2	smac/hal/ssv6006c/ssv6006C_reg.h	7530;"	d
+GET_DB_SX_SBCAL_NCOUNT	smac/hal/ssv6006c/ssv6006C_reg.h	7115;"	d
+GET_DB_SX_SBCAL_NTARGET	smac/hal/ssv6006c/ssv6006C_reg.h	7116;"	d
+GET_DB_SX_TTL_VT_DET	smac/hal/ssv6006c/ssv6006C_reg.h	7112;"	d
+GET_DB_TURISMO_TRX_AD_ADC_I_OUT	smac/hal/ssv6006c/ssv6006C_reg.h	5734;"	d
+GET_DB_TURISMO_TRX_AD_ADC_Q_OUT	smac/hal/ssv6006c/ssv6006C_reg.h	5735;"	d
+GET_DB_TURISMO_TRX_AD_DP_VT_MON_Q	smac/hal/ssv6006c/ssv6006C_reg.h	5743;"	d
+GET_DB_TURISMO_TRX_AD_IOT_ADC_OUT	smac/hal/ssv6006c/ssv6006C_reg.h	5744;"	d
+GET_DB_TURISMO_TRX_AD_RX_RSSIADC	smac/hal/ssv6006c/ssv6006C_reg.h	5736;"	d
+GET_DB_TURISMO_TRX_AD_SX5GB_AAC_COMPOUT	smac/hal/ssv6006c/ssv6006C_reg.h	6144;"	d
+GET_DB_TURISMO_TRX_DA_SARADC_BIT	smac/hal/ssv6006c/ssv6006C_reg.h	5737;"	d
+GET_DB_TURISMO_TRX_DA_SX5GB_SUB_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	6138;"	d
+GET_DB_TURISMO_TRX_DA_SX5GB_VCO_ISEL	smac/hal/ssv6006c/ssv6006C_reg.h	6139;"	d
+GET_DB_TURISMO_TRX_DA_SXMIX_GMSEL	smac/hal/ssv6006c/ssv6006C_reg.h	6141;"	d
+GET_DB_TURISMO_TRX_DA_SXMIX_SCA_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	6140;"	d
+GET_DB_TURISMO_TRX_DA_SXREP_CSSEL	smac/hal/ssv6006c/ssv6006C_reg.h	6143;"	d
+GET_DB_TURISMO_TRX_DA_SXREP_SCA_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	6142;"	d
+GET_DB_TURISMO_TRX_DA_SX_SUB_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	5739;"	d
+GET_DB_TURISMO_TRX_DA_SX_VCO_ISEL	smac/hal/ssv6006c/ssv6006C_reg.h	5740;"	d
+GET_DB_TURISMO_TRX_SX5GB_SBCAL_NCOUNT	smac/hal/ssv6006c/ssv6006C_reg.h	6150;"	d
+GET_DB_TURISMO_TRX_SX5GB_SBCAL_NTARGET	smac/hal/ssv6006c/ssv6006C_reg.h	6151;"	d
+GET_DB_TURISMO_TRX_SX5GB_TTL_VT_DET	smac/hal/ssv6006c/ssv6006C_reg.h	6145;"	d
+GET_DB_TURISMO_TRX_SXMIX_SCA_SEL_A1	smac/hal/ssv6006c/ssv6006C_reg.h	6146;"	d
+GET_DB_TURISMO_TRX_SXMIX_SCA_SEL_A2	smac/hal/ssv6006c/ssv6006C_reg.h	6147;"	d
+GET_DB_TURISMO_TRX_SXREP_SCA_SEL_B1	smac/hal/ssv6006c/ssv6006C_reg.h	6148;"	d
+GET_DB_TURISMO_TRX_SXREP_SCA_SEL_B2	smac/hal/ssv6006c/ssv6006C_reg.h	6149;"	d
+GET_DB_TURISMO_TRX_SX_SBCAL_NCOUNT	smac/hal/ssv6006c/ssv6006C_reg.h	5745;"	d
+GET_DB_TURISMO_TRX_SX_SBCAL_NTARGET	smac/hal/ssv6006c/ssv6006C_reg.h	5746;"	d
+GET_DB_TURISMO_TRX_SX_TTL_VT_DET	smac/hal/ssv6006c/ssv6006C_reg.h	5742;"	d
+GET_DB_TURISMO_TRX_VO_AAC_COMPOUT	smac/hal/ssv6006c/ssv6006C_reg.h	5741;"	d
+GET_DB_VO_AAC_COMPOUT	smac/hal/ssv6006c/ssv6006C_reg.h	7111;"	d
+GET_DEBUG_CTL	include/ssv6200_reg.h	4842;"	d
+GET_DEBUG_H16	include/ssv6200_reg.h	4843;"	d
+GET_DEBUG_OUT	include/ssv6200_reg.h	4844;"	d
+GET_DEBUG_SEL	include/ssv6200_reg.h	4192;"	d
+GET_DEC_DIN_MSB	include/ssv6200_reg.h	2604;"	d
+GET_DEC_DOUT_MSB	include/ssv6200_reg.h	2603;"	d
+GET_DELTA_CD	include/ssv6200_reg.h	2151;"	d
+GET_DELTA_CD	smac/hal/ssv6006c/ssv6006C_reg.h	2862;"	d
+GET_DELTA_CTS	include/ssv6200_reg.h	2148;"	d
+GET_DELTA_CTS	smac/hal/ssv6006c/ssv6006C_reg.h	2859;"	d
+GET_DELTA_DSR	include/ssv6200_reg.h	2149;"	d
+GET_DELTA_DSR	smac/hal/ssv6006c/ssv6006C_reg.h	2860;"	d
+GET_DE_RTS	smac/hal/ssv6006c/ssv6006C_reg.h	2850;"	d
+GET_DIGI_TOP_POR_MASK	include/ssv6200_reg.h	2445;"	d
+GET_DIRECT_INT_MUX_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	2686;"	d
+GET_DIRECT_MODE	include/ssv6200_reg.h	4794;"	d
+GET_DIS_DEMAND	include/ssv6200_reg.h	4796;"	d
+GET_DLAB	include/ssv6200_reg.h	2134;"	d
+GET_DLAB	smac/hal/ssv6006c/ssv6006C_reg.h	2844;"	d
+GET_DMA_ADR_DST	include/ssv6200_reg.h	2417;"	d
+GET_DMA_ADR_DST	smac/hal/ssv6006c/ssv6006C_reg.h	2990;"	d
+GET_DMA_ADR_SRC	include/ssv6200_reg.h	2416;"	d
+GET_DMA_ADR_SRC	smac/hal/ssv6006c/ssv6006C_reg.h	2989;"	d
+GET_DMA_BADR_EN	include/ssv6200_reg.h	2424;"	d
+GET_DMA_BADR_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2997;"	d
+GET_DMA_BUSY	include/ssv6200_reg.h	2400;"	d
+GET_DMA_CLK_EN	include/ssv6200_reg.h	1306;"	d
+GET_DMA_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2385;"	d
+GET_DMA_CONST	include/ssv6200_reg.h	2429;"	d
+GET_DMA_CONST	smac/hal/ssv6006c/ssv6006C_reg.h	3002;"	d
+GET_DMA_DST_INC	include/ssv6200_reg.h	2421;"	d
+GET_DMA_DST_INC	smac/hal/ssv6006c/ssv6006C_reg.h	2994;"	d
+GET_DMA_DST_SIZE	include/ssv6200_reg.h	2420;"	d
+GET_DMA_DST_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	2993;"	d
+GET_DMA_EN	include/ssv6200_reg.h	2399;"	d
+GET_DMA_FAST_FILL	include/ssv6200_reg.h	2422;"	d
+GET_DMA_FAST_FILL	smac/hal/ssv6006c/ssv6006C_reg.h	2995;"	d
+GET_DMA_FINISH	include/ssv6200_reg.h	2428;"	d
+GET_DMA_FINISH	smac/hal/ssv6006c/ssv6006C_reg.h	3001;"	d
+GET_DMA_INT_MASK	include/ssv6200_reg.h	2426;"	d
+GET_DMA_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	2999;"	d
+GET_DMA_LEN	include/ssv6200_reg.h	2425;"	d
+GET_DMA_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	2998;"	d
+GET_DMA_MODE	include/ssv6200_reg.h	2124;"	d
+GET_DMA_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	2834;"	d
+GET_DMA_RXEND_IE	include/ssv6200_reg.h	2119;"	d
+GET_DMA_SDIO_KICK	include/ssv6200_reg.h	2423;"	d
+GET_DMA_SDIO_KICK	smac/hal/ssv6006c/ssv6006C_reg.h	2996;"	d
+GET_DMA_SRC_INC	include/ssv6200_reg.h	2419;"	d
+GET_DMA_SRC_INC	smac/hal/ssv6006c/ssv6006C_reg.h	2992;"	d
+GET_DMA_SRC_SIZE	include/ssv6200_reg.h	2418;"	d
+GET_DMA_SRC_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	2991;"	d
+GET_DMA_STS	include/ssv6200_reg.h	2427;"	d
+GET_DMA_STS	smac/hal/ssv6006c/ssv6006C_reg.h	3000;"	d
+GET_DMA_SW_RST	include/ssv6200_reg.h	1272;"	d
+GET_DMA_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	2352;"	d
+GET_DMA_TXEND_IE	include/ssv6200_reg.h	2120;"	d
+GET_DMN_FLAG	include/ssv6200_reg.h	4852;"	d
+GET_DMN_FLAG_CLR	include/ssv6200_reg.h	4801;"	d
+GET_DMN_IDTBL_127_96	include/ssv6200_reg.h	4878;"	d
+GET_DMN_IDTBL_31_0	include/ssv6200_reg.h	4875;"	d
+GET_DMN_IDTBL_63_32	include/ssv6200_reg.h	4876;"	d
+GET_DMN_IDTBL_95_64	include/ssv6200_reg.h	4877;"	d
+GET_DMN_MCU_ADDR	include/ssv6200_reg.h	4866;"	d
+GET_DMN_MCU_FLAG	include/ssv6200_reg.h	4862;"	d
+GET_DMN_MCU_ID	include/ssv6200_reg.h	4865;"	d
+GET_DMN_MCU_INT	include/ssv6200_reg.h	2269;"	d
+GET_DMN_MCU_INT_SD	include/ssv6200_reg.h	2338;"	d
+GET_DMN_MCU_PORT	include/ssv6200_reg.h	4864;"	d
+GET_DMN_MCU_WR	include/ssv6200_reg.h	4863;"	d
+GET_DMN_NHIT_ADDR	include/ssv6200_reg.h	4856;"	d
+GET_DMN_NHIT_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	9059;"	d
+GET_DMN_NHIT_ID	include/ssv6200_reg.h	4855;"	d
+GET_DMN_NHIT_ID	smac/hal/ssv6006c/ssv6006C_reg.h	9058;"	d
+GET_DMN_NOHIT_CLR	smac/hal/ssv6006c/ssv6006C_reg.h	9055;"	d
+GET_DMN_NOHIT_FLAG	include/ssv6200_reg.h	4851;"	d
+GET_DMN_NOHIT_INT	include/ssv6200_reg.h	2262;"	d
+GET_DMN_NOHIT_INT_SD	include/ssv6200_reg.h	2331;"	d
+GET_DMN_NOHIT_MCU	include/ssv6200_reg.h	4861;"	d
+GET_DMN_NOHIT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	9054;"	d
+GET_DMN_PORT	include/ssv6200_reg.h	4854;"	d
+GET_DMN_PORT	smac/hal/ssv6006c/ssv6006C_reg.h	9057;"	d
+GET_DMN_R_PASS	include/ssv6200_reg.h	4835;"	d
+GET_DMN_WR	include/ssv6200_reg.h	4853;"	d
+GET_DMN_WR	smac/hal/ssv6006c/ssv6006C_reg.h	9056;"	d
+GET_DOT11RTSTHRESHOLD	include/ssv6200_reg.h	2492;"	d
+GET_DOT11RTSTHRESHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	3195;"	d
+GET_DOUBLE_ALLOCATE_ERROR	include/ssv6200_reg.h	1963;"	d
+GET_DOUBLE_ALLOC_ERR	smac/hal/ssv6006c/ssv6006C_reg.h	3215;"	d
+GET_DOUBLE_RLS_ID	include/ssv6200_reg.h	3804;"	d
+GET_DOUBLE_RLS_ID	smac/hal/ssv6006c/ssv6006C_reg.h	8987;"	d
+GET_DOUBLE_RLS_INT_EN	include/ssv6200_reg.h	3802;"	d
+GET_DOUBLE_RLS_INT_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8985;"	d
+GET_DPLL_CKT_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	6914;"	d
+GET_DPLL_FB_DIVISION__REGISTERS	smac/hal/ssv6006c/ssv6006C_reg.h	6915;"	d
+GET_DPLL_TOP_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	6913;"	d
+GET_DSR	include/ssv6200_reg.h	2153;"	d
+GET_DSR	smac/hal/ssv6006c/ssv6006C_reg.h	2864;"	d
+GET_DTR	include/ssv6200_reg.h	2135;"	d
+GET_DTR	smac/hal/ssv6006c/ssv6006C_reg.h	2845;"	d
+GET_DUAL_ANT_EN	include/ssv6200_reg.h	3114;"	d
+GET_DUAL_ANT_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3953;"	d
+GET_DUMY_DLY	smac/hal/ssv6006c/ssv6006C_reg.h	2958;"	d
+GET_DUP_FLT	include/ssv6200_reg.h	3092;"	d
+GET_DUP_FLT	smac/hal/ssv6006c/ssv6006C_reg.h	3924;"	d
+GET_DURATION	include/ssv6200_reg.h	2556;"	d
+GET_DURATION	smac/hal/ssv6006c/ssv6006C_reg.h	3294;"	d
+GET_EARLY_SAMPLE	smac/hal/ssv6006c/ssv6006C_reg.h	3355;"	d
+GET_EDCA0_FFO_CNT	include/ssv6200_reg.h	3829;"	d
+GET_EDCA0_FFO_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	9012;"	d
+GET_EDCA0_LOWTHOLD_INT	include/ssv6200_reg.h	2087;"	d
+GET_EDCA0_LOW_THR_INT_MASK	include/ssv6200_reg.h	1873;"	d
+GET_EDCA0_LOW_THR_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	2656;"	d
+GET_EDCA0_LOW_THR_INT_STS	include/ssv6200_reg.h	1881;"	d
+GET_EDCA0_LOW_THR_INT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	2664;"	d
+GET_EDCA0_UPTHOLD_INT	include/ssv6200_reg.h	1973;"	d
+GET_EDCA1_FFO_CNT2	include/ssv6200_reg.h	3844;"	d
+GET_EDCA1_FFO_CNT2	smac/hal/ssv6006c/ssv6006C_reg.h	9028;"	d
+GET_EDCA1_FFO_CNT_3_0	include/ssv6200_reg.h	3830;"	d
+GET_EDCA1_FFO_CNT_3_0	smac/hal/ssv6006c/ssv6006C_reg.h	9013;"	d
+GET_EDCA1_LOWTHOLD_INT	include/ssv6200_reg.h	2088;"	d
+GET_EDCA1_LOW_THR_INT_MASK	include/ssv6200_reg.h	1874;"	d
+GET_EDCA1_LOW_THR_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	2657;"	d
+GET_EDCA1_LOW_THR_INT_STS	include/ssv6200_reg.h	1882;"	d
+GET_EDCA1_LOW_THR_INT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	2665;"	d
+GET_EDCA1_UPTHOLD_INT	include/ssv6200_reg.h	1974;"	d
+GET_EDCA2_FFO_CNT	include/ssv6200_reg.h	3831;"	d
+GET_EDCA2_FFO_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	9014;"	d
+GET_EDCA2_FFO_CNT2	include/ssv6200_reg.h	3848;"	d
+GET_EDCA2_FFO_CNT2	smac/hal/ssv6006c/ssv6006C_reg.h	9033;"	d
+GET_EDCA2_LOWTHOLD_INT	include/ssv6200_reg.h	2089;"	d
+GET_EDCA2_LOW_THR_INT_MASK	include/ssv6200_reg.h	1875;"	d
+GET_EDCA2_LOW_THR_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	2658;"	d
+GET_EDCA2_LOW_THR_INT_STS	include/ssv6200_reg.h	1883;"	d
+GET_EDCA2_LOW_THR_INT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	2666;"	d
+GET_EDCA2_UPTHOLD_INT	include/ssv6200_reg.h	1975;"	d
+GET_EDCA3_FFO_CNT	include/ssv6200_reg.h	3832;"	d
+GET_EDCA3_FFO_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	9015;"	d
+GET_EDCA3_FFO_CNT2	include/ssv6200_reg.h	3849;"	d
+GET_EDCA3_FFO_CNT2	smac/hal/ssv6006c/ssv6006C_reg.h	9034;"	d
+GET_EDCA3_LOWTHOLD_INT	include/ssv6200_reg.h	2090;"	d
+GET_EDCA3_LOW_THR_INT_MASK	include/ssv6200_reg.h	1876;"	d
+GET_EDCA3_LOW_THR_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	2659;"	d
+GET_EDCA3_LOW_THR_INT_STS	include/ssv6200_reg.h	1884;"	d
+GET_EDCA3_LOW_THR_INT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	2667;"	d
+GET_EDCA3_UPTHOLD_INT	include/ssv6200_reg.h	1976;"	d
+GET_EDCA4_FFO_CNT	include/ssv6200_reg.h	3841;"	d
+GET_EDCA4_FFO_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	9024;"	d
+GET_EDCA4_FFO_CNT2	include/ssv6200_reg.h	3845;"	d
+GET_EDCA4_FFO_CNT2	smac/hal/ssv6006c/ssv6006C_reg.h	9029;"	d
+GET_EDCA4_LOW_THR_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	2654;"	d
+GET_EDCA4_LOW_THR_INT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	2662;"	d
+GET_EDCA5_FFO_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	9025;"	d
+GET_EDCA5_FFO_CNT2	smac/hal/ssv6006c/ssv6006C_reg.h	9030;"	d
+GET_EDLM_SRAM_ERRCK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2442;"	d
+GET_EDLM_SRAM_ERR_INT	smac/hal/ssv6006c/ssv6006C_reg.h	2447;"	d
+GET_EFS_BYTE_0	smac/hal/ssv6006c/ssv6006C_reg.h	3310;"	d
+GET_EFS_BYTE_1	smac/hal/ssv6006c/ssv6006C_reg.h	3311;"	d
+GET_EFS_BYTE_10	smac/hal/ssv6006c/ssv6006C_reg.h	3320;"	d
+GET_EFS_BYTE_11	smac/hal/ssv6006c/ssv6006C_reg.h	3321;"	d
+GET_EFS_BYTE_12	smac/hal/ssv6006c/ssv6006C_reg.h	3322;"	d
+GET_EFS_BYTE_13	smac/hal/ssv6006c/ssv6006C_reg.h	3323;"	d
+GET_EFS_BYTE_14	smac/hal/ssv6006c/ssv6006C_reg.h	3324;"	d
+GET_EFS_BYTE_15	smac/hal/ssv6006c/ssv6006C_reg.h	3325;"	d
+GET_EFS_BYTE_16	smac/hal/ssv6006c/ssv6006C_reg.h	3326;"	d
+GET_EFS_BYTE_17	smac/hal/ssv6006c/ssv6006C_reg.h	3327;"	d
+GET_EFS_BYTE_18	smac/hal/ssv6006c/ssv6006C_reg.h	3328;"	d
+GET_EFS_BYTE_19	smac/hal/ssv6006c/ssv6006C_reg.h	3329;"	d
+GET_EFS_BYTE_2	smac/hal/ssv6006c/ssv6006C_reg.h	3312;"	d
+GET_EFS_BYTE_20	smac/hal/ssv6006c/ssv6006C_reg.h	3330;"	d
+GET_EFS_BYTE_21	smac/hal/ssv6006c/ssv6006C_reg.h	3331;"	d
+GET_EFS_BYTE_22	smac/hal/ssv6006c/ssv6006C_reg.h	3332;"	d
+GET_EFS_BYTE_23	smac/hal/ssv6006c/ssv6006C_reg.h	3333;"	d
+GET_EFS_BYTE_24	smac/hal/ssv6006c/ssv6006C_reg.h	3334;"	d
+GET_EFS_BYTE_25	smac/hal/ssv6006c/ssv6006C_reg.h	3335;"	d
+GET_EFS_BYTE_26	smac/hal/ssv6006c/ssv6006C_reg.h	3336;"	d
+GET_EFS_BYTE_27	smac/hal/ssv6006c/ssv6006C_reg.h	3337;"	d
+GET_EFS_BYTE_28	smac/hal/ssv6006c/ssv6006C_reg.h	3338;"	d
+GET_EFS_BYTE_29	smac/hal/ssv6006c/ssv6006C_reg.h	3339;"	d
+GET_EFS_BYTE_3	smac/hal/ssv6006c/ssv6006C_reg.h	3313;"	d
+GET_EFS_BYTE_30	smac/hal/ssv6006c/ssv6006C_reg.h	3340;"	d
+GET_EFS_BYTE_31	smac/hal/ssv6006c/ssv6006C_reg.h	3341;"	d
+GET_EFS_BYTE_4	smac/hal/ssv6006c/ssv6006C_reg.h	3314;"	d
+GET_EFS_BYTE_5	smac/hal/ssv6006c/ssv6006C_reg.h	3315;"	d
+GET_EFS_BYTE_6	smac/hal/ssv6006c/ssv6006C_reg.h	3316;"	d
+GET_EFS_BYTE_7	smac/hal/ssv6006c/ssv6006C_reg.h	3317;"	d
+GET_EFS_BYTE_8	smac/hal/ssv6006c/ssv6006C_reg.h	3318;"	d
+GET_EFS_BYTE_9	smac/hal/ssv6006c/ssv6006C_reg.h	3319;"	d
+GET_EFS_CLKFREQ	include/ssv6200_reg.h	2561;"	d
+GET_EFS_CLKFREQ	smac/hal/ssv6006c/ssv6006C_reg.h	3299;"	d
+GET_EFS_CLKFREQ_RD	include/ssv6200_reg.h	2563;"	d
+GET_EFS_CLKFREQ_RD	smac/hal/ssv6006c/ssv6006C_reg.h	3301;"	d
+GET_EFS_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2390;"	d
+GET_EFS_LDO_OFF	include/ssv6200_reg.h	2566;"	d
+GET_EFS_LDO_OFF	smac/hal/ssv6006c/ssv6006C_reg.h	3304;"	d
+GET_EFS_LDO_ON	include/ssv6200_reg.h	2565;"	d
+GET_EFS_LDO_ON	smac/hal/ssv6006c/ssv6006C_reg.h	3303;"	d
+GET_EFS_PRE_RD	include/ssv6200_reg.h	2564;"	d
+GET_EFS_PRE_RD	smac/hal/ssv6006c/ssv6006C_reg.h	3302;"	d
+GET_EFS_PROGRESS_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	3306;"	d
+GET_EFS_RDATA_0	include/ssv6200_reg.h	2567;"	d
+GET_EFS_RDATA_1	include/ssv6200_reg.h	2569;"	d
+GET_EFS_RDATA_2	include/ssv6200_reg.h	2571;"	d
+GET_EFS_RDATA_3	include/ssv6200_reg.h	2573;"	d
+GET_EFS_RDATA_4	include/ssv6200_reg.h	2575;"	d
+GET_EFS_RDATA_5	include/ssv6200_reg.h	2577;"	d
+GET_EFS_RDATA_6	include/ssv6200_reg.h	2579;"	d
+GET_EFS_RDATA_7	include/ssv6200_reg.h	2581;"	d
+GET_EFS_RD_FLAG	smac/hal/ssv6006c/ssv6006C_reg.h	3305;"	d
+GET_EFS_RD_KICK	smac/hal/ssv6006c/ssv6006C_reg.h	3308;"	d
+GET_EFS_SPI_RBUSY	include/ssv6200_reg.h	2591;"	d
+GET_EFS_SPI_RD0_EN	include/ssv6200_reg.h	2583;"	d
+GET_EFS_SPI_RD1_EN	include/ssv6200_reg.h	2584;"	d
+GET_EFS_SPI_RD2_EN	include/ssv6200_reg.h	2585;"	d
+GET_EFS_SPI_RD3_EN	include/ssv6200_reg.h	2586;"	d
+GET_EFS_SPI_RD4_EN	include/ssv6200_reg.h	2587;"	d
+GET_EFS_SPI_RD5_EN	include/ssv6200_reg.h	2588;"	d
+GET_EFS_SPI_RD6_EN	include/ssv6200_reg.h	2589;"	d
+GET_EFS_SPI_RD7_EN	include/ssv6200_reg.h	2590;"	d
+GET_EFS_SPI_RDATA_0	include/ssv6200_reg.h	2592;"	d
+GET_EFS_SPI_RDATA_1	include/ssv6200_reg.h	2593;"	d
+GET_EFS_SPI_RDATA_2	include/ssv6200_reg.h	2594;"	d
+GET_EFS_SPI_RDATA_3	include/ssv6200_reg.h	2595;"	d
+GET_EFS_SPI_RDATA_4	include/ssv6200_reg.h	2596;"	d
+GET_EFS_SPI_RDATA_5	include/ssv6200_reg.h	2597;"	d
+GET_EFS_SPI_RDATA_6	include/ssv6200_reg.h	2598;"	d
+GET_EFS_SPI_RDATA_7	include/ssv6200_reg.h	2599;"	d
+GET_EFS_VDDQ_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3309;"	d
+GET_EFS_VDDQ_EN_LOW_ACTIVE	smac/hal/ssv6006c/ssv6006C_reg.h	3300;"	d
+GET_EFS_WDATA_0	include/ssv6200_reg.h	2568;"	d
+GET_EFS_WDATA_1	include/ssv6200_reg.h	2570;"	d
+GET_EFS_WDATA_2	include/ssv6200_reg.h	2572;"	d
+GET_EFS_WDATA_3	include/ssv6200_reg.h	2574;"	d
+GET_EFS_WDATA_4	include/ssv6200_reg.h	2576;"	d
+GET_EFS_WDATA_5	include/ssv6200_reg.h	2578;"	d
+GET_EFS_WDATA_6	include/ssv6200_reg.h	2580;"	d
+GET_EFS_WDATA_7	include/ssv6200_reg.h	2582;"	d
+GET_EFS_WR_KICK	smac/hal/ssv6006c/ssv6006C_reg.h	3307;"	d
+GET_EIFS_IN_SLOT	smac/hal/ssv6006c/ssv6006C_reg.h	3608;"	d
+GET_EILM_ROM_ERRCK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2443;"	d
+GET_EILM_ROM_ERR_INT	smac/hal/ssv6006c/ssv6006C_reg.h	2448;"	d
+GET_EILM_SRAM_ERRCK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2444;"	d
+GET_EILM_SRAM_ERR_INT	smac/hal/ssv6006c/ssv6006C_reg.h	2449;"	d
+GET_ENABLECSA	include/ssv6200_reg.h	2012;"	d
+GET_ENABLECSA	smac/hal/ssv6006c/ssv6006C_reg.h	2728;"	d
+GET_ENABLE_BLOCK_GAP_INTERRUPT	include/ssv6200_reg.h	2004;"	d
+GET_ENABLE_BLOCK_GAP_INTERRUPT	smac/hal/ssv6006c/ssv6006C_reg.h	2718;"	d
+GET_ENC_DIN_MSB	include/ssv6200_reg.h	2606;"	d
+GET_ENC_DOUT_MSB	include/ssv6200_reg.h	2605;"	d
+GET_ENDIAN	smac/hal/ssv6006c/ssv6006C_reg.h	3354;"	d
+GET_END_BYTE_VALUE	include/ssv6200_reg.h	1922;"	d
+GET_END_BYTE_VALUE2	include/ssv6200_reg.h	1987;"	d
+GET_EN_AUTO_CTS	include/ssv6200_reg.h	2126;"	d
+GET_EN_AUTO_CTS	smac/hal/ssv6006c/ssv6006C_reg.h	2836;"	d
+GET_EN_AUTO_RTS	include/ssv6200_reg.h	2125;"	d
+GET_EN_AUTO_RTS	smac/hal/ssv6006c/ssv6006C_reg.h	2835;"	d
+GET_EN_STAT_FINISH_INT	smac/hal/ssv6006c/ssv6006C_reg.h	3553;"	d
+GET_EN_UNEXPECT_WSID	smac/hal/ssv6006c/ssv6006C_reg.h	3552;"	d
+GET_EOSP_HW_ID	smac/hal/ssv6006c/ssv6006C_reg.h	3453;"	d
+GET_EOSP_H_QUEUE_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3452;"	d
+GET_ERP_PROTECT	include/ssv6200_reg.h	2478;"	d
+GET_ERP_PROTECT	smac/hal/ssv6006c/ssv6006C_reg.h	3177;"	d
+GET_ERR_FLAG_CLR	smac/hal/ssv6006c/ssv6006C_reg.h	2988;"	d
+GET_ERR_SW_RST_N	include/ssv6200_reg.h	4802;"	d
+GET_EVEN_PARITY	include/ssv6200_reg.h	2131;"	d
+GET_EVEN_PARITY	smac/hal/ssv6006c/ssv6006C_reg.h	2841;"	d
+GET_EXT_32K_SEL	include/ssv6200_reg.h	1860;"	d
+GET_EXT_MAC_MODE	include/ssv6200_reg.h	3019;"	d
+GET_EXT_MAC_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	3851;"	d
+GET_EXT_PHY_MODE	include/ssv6200_reg.h	3020;"	d
+GET_EXT_PHY_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	3852;"	d
+GET_F0_CIS_CONTENT_REG_127_96	include/ssv6200_reg.h	2018;"	d
+GET_F0_CIS_CONTENT_REG_127_96	smac/hal/ssv6006c/ssv6006C_reg.h	2734;"	d
+GET_F0_CIS_CONTENT_REG_159_128	include/ssv6200_reg.h	2019;"	d
+GET_F0_CIS_CONTENT_REG_159_128	smac/hal/ssv6006c/ssv6006C_reg.h	2735;"	d
+GET_F0_CIS_CONTENT_REG_191_160	include/ssv6200_reg.h	2020;"	d
+GET_F0_CIS_CONTENT_REG_191_160	smac/hal/ssv6006c/ssv6006C_reg.h	2736;"	d
+GET_F0_CIS_CONTENT_REG_223_192	include/ssv6200_reg.h	2021;"	d
+GET_F0_CIS_CONTENT_REG_223_192	smac/hal/ssv6006c/ssv6006C_reg.h	2737;"	d
+GET_F0_CIS_CONTENT_REG_255_224	include/ssv6200_reg.h	2022;"	d
+GET_F0_CIS_CONTENT_REG_255_224	smac/hal/ssv6006c/ssv6006C_reg.h	2738;"	d
+GET_F0_CIS_CONTENT_REG_287_256	include/ssv6200_reg.h	2023;"	d
+GET_F0_CIS_CONTENT_REG_287_256	smac/hal/ssv6006c/ssv6006C_reg.h	2739;"	d
+GET_F0_CIS_CONTENT_REG_319_288	include/ssv6200_reg.h	2024;"	d
+GET_F0_CIS_CONTENT_REG_319_288	smac/hal/ssv6006c/ssv6006C_reg.h	2740;"	d
+GET_F0_CIS_CONTENT_REG_31_0	include/ssv6200_reg.h	2015;"	d
+GET_F0_CIS_CONTENT_REG_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	2731;"	d
+GET_F0_CIS_CONTENT_REG_351_320	include/ssv6200_reg.h	2025;"	d
+GET_F0_CIS_CONTENT_REG_351_320	smac/hal/ssv6006c/ssv6006C_reg.h	2741;"	d
+GET_F0_CIS_CONTENT_REG_383_352	include/ssv6200_reg.h	2026;"	d
+GET_F0_CIS_CONTENT_REG_383_352	smac/hal/ssv6006c/ssv6006C_reg.h	2742;"	d
+GET_F0_CIS_CONTENT_REG_415_384	include/ssv6200_reg.h	2027;"	d
+GET_F0_CIS_CONTENT_REG_415_384	smac/hal/ssv6006c/ssv6006C_reg.h	2743;"	d
+GET_F0_CIS_CONTENT_REG_447_416	include/ssv6200_reg.h	2028;"	d
+GET_F0_CIS_CONTENT_REG_447_416	smac/hal/ssv6006c/ssv6006C_reg.h	2744;"	d
+GET_F0_CIS_CONTENT_REG_479_448	include/ssv6200_reg.h	2029;"	d
+GET_F0_CIS_CONTENT_REG_479_448	smac/hal/ssv6006c/ssv6006C_reg.h	2745;"	d
+GET_F0_CIS_CONTENT_REG_511_480	include/ssv6200_reg.h	2030;"	d
+GET_F0_CIS_CONTENT_REG_511_480	smac/hal/ssv6006c/ssv6006C_reg.h	2746;"	d
+GET_F0_CIS_CONTENT_REG_63_32	include/ssv6200_reg.h	2016;"	d
+GET_F0_CIS_CONTENT_REG_63_32	smac/hal/ssv6006c/ssv6006C_reg.h	2732;"	d
+GET_F0_CIS_CONTENT_REG_95_64	include/ssv6200_reg.h	2017;"	d
+GET_F0_CIS_CONTENT_REG_95_64	smac/hal/ssv6006c/ssv6006C_reg.h	2733;"	d
+GET_F1_BLOCK_SIZE_0_REG	include/ssv6200_reg.h	1982;"	d
+GET_F1_CIS_CONTENT_REG_127_96	include/ssv6200_reg.h	2034;"	d
+GET_F1_CIS_CONTENT_REG_127_96	smac/hal/ssv6006c/ssv6006C_reg.h	2750;"	d
+GET_F1_CIS_CONTENT_REG_159_128	include/ssv6200_reg.h	2035;"	d
+GET_F1_CIS_CONTENT_REG_159_128	smac/hal/ssv6006c/ssv6006C_reg.h	2751;"	d
+GET_F1_CIS_CONTENT_REG_191_160	include/ssv6200_reg.h	2036;"	d
+GET_F1_CIS_CONTENT_REG_191_160	smac/hal/ssv6006c/ssv6006C_reg.h	2752;"	d
+GET_F1_CIS_CONTENT_REG_223_192	include/ssv6200_reg.h	2037;"	d
+GET_F1_CIS_CONTENT_REG_223_192	smac/hal/ssv6006c/ssv6006C_reg.h	2753;"	d
+GET_F1_CIS_CONTENT_REG_255_224	include/ssv6200_reg.h	2038;"	d
+GET_F1_CIS_CONTENT_REG_255_224	smac/hal/ssv6006c/ssv6006C_reg.h	2754;"	d
+GET_F1_CIS_CONTENT_REG_287_256	include/ssv6200_reg.h	2039;"	d
+GET_F1_CIS_CONTENT_REG_287_256	smac/hal/ssv6006c/ssv6006C_reg.h	2755;"	d
+GET_F1_CIS_CONTENT_REG_319_288	include/ssv6200_reg.h	2040;"	d
+GET_F1_CIS_CONTENT_REG_319_288	smac/hal/ssv6006c/ssv6006C_reg.h	2756;"	d
+GET_F1_CIS_CONTENT_REG_31_0	include/ssv6200_reg.h	2031;"	d
+GET_F1_CIS_CONTENT_REG_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	2747;"	d
+GET_F1_CIS_CONTENT_REG_351_320	include/ssv6200_reg.h	2041;"	d
+GET_F1_CIS_CONTENT_REG_351_320	smac/hal/ssv6006c/ssv6006C_reg.h	2757;"	d
+GET_F1_CIS_CONTENT_REG_383_352	include/ssv6200_reg.h	2042;"	d
+GET_F1_CIS_CONTENT_REG_383_352	smac/hal/ssv6006c/ssv6006C_reg.h	2758;"	d
+GET_F1_CIS_CONTENT_REG_415_384	include/ssv6200_reg.h	2043;"	d
+GET_F1_CIS_CONTENT_REG_415_384	smac/hal/ssv6006c/ssv6006C_reg.h	2759;"	d
+GET_F1_CIS_CONTENT_REG_447_416	include/ssv6200_reg.h	2044;"	d
+GET_F1_CIS_CONTENT_REG_447_416	smac/hal/ssv6006c/ssv6006C_reg.h	2760;"	d
+GET_F1_CIS_CONTENT_REG_479_448	include/ssv6200_reg.h	2045;"	d
+GET_F1_CIS_CONTENT_REG_479_448	smac/hal/ssv6006c/ssv6006C_reg.h	2761;"	d
+GET_F1_CIS_CONTENT_REG_511_480	include/ssv6200_reg.h	2046;"	d
+GET_F1_CIS_CONTENT_REG_511_480	smac/hal/ssv6006c/ssv6006C_reg.h	2762;"	d
+GET_F1_CIS_CONTENT_REG_63_32	include/ssv6200_reg.h	2032;"	d
+GET_F1_CIS_CONTENT_REG_63_32	smac/hal/ssv6006c/ssv6006C_reg.h	2748;"	d
+GET_F1_CIS_CONTENT_REG_95_64	include/ssv6200_reg.h	2033;"	d
+GET_F1_CIS_CONTENT_REG_95_64	smac/hal/ssv6006c/ssv6006C_reg.h	2749;"	d
+GET_FAST_CLK	smac/hal/ssv6006c/ssv6006C_reg.h	3351;"	d
+GET_FBR_100H_REG	include/ssv6200_reg.h	2010;"	d
+GET_FBR_100H_REG	smac/hal/ssv6006c/ssv6006C_reg.h	2726;"	d
+GET_FBR_101H_REG	include/ssv6200_reg.h	2013;"	d
+GET_FBR_101H_REG	smac/hal/ssv6006c/ssv6006C_reg.h	2729;"	d
+GET_FBR_109H_REG	include/ssv6200_reg.h	2014;"	d
+GET_FBR_109H_REG	smac/hal/ssv6006c/ssv6006C_reg.h	2730;"	d
+GET_FBUS_DMAC_BLOCK0	smac/hal/ssv6006c/ssv6006C_reg.h	2165;"	d
+GET_FBUS_DMAC_BLOCK1	smac/hal/ssv6006c/ssv6006C_reg.h	2182;"	d
+GET_FBUS_DMAC_CH0_CLR_ERR	smac/hal/ssv6006c/ssv6006C_reg.h	2197;"	d
+GET_FBUS_DMAC_CH0_CLR_TR	smac/hal/ssv6006c/ssv6006C_reg.h	2195;"	d
+GET_FBUS_DMAC_CH0_PRIOR	smac/hal/ssv6006c/ssv6006C_reg.h	2166;"	d
+GET_FBUS_DMAC_CH1_CLR_ERR	smac/hal/ssv6006c/ssv6006C_reg.h	2198;"	d
+GET_FBUS_DMAC_CH1_CLR_TR	smac/hal/ssv6006c/ssv6006C_reg.h	2196;"	d
+GET_FBUS_DMAC_CH1_PRIOR	smac/hal/ssv6006c/ssv6006C_reg.h	2183;"	d
+GET_FBUS_DMAC_CH_DEMASK_ERR	smac/hal/ssv6006c/ssv6006C_reg.h	2194;"	d
+GET_FBUS_DMAC_CH_DEMASK_TR	smac/hal/ssv6006c/ssv6006C_reg.h	2193;"	d
+GET_FBUS_DMAC_CH_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2204;"	d
+GET_FBUS_DMAC_CH_ERR_TR	smac/hal/ssv6006c/ssv6006C_reg.h	2190;"	d
+GET_FBUS_DMAC_CH_RAW_TR	smac/hal/ssv6006c/ssv6006C_reg.h	2189;"	d
+GET_FBUS_DMAC_CH_STATUSERR_TR	smac/hal/ssv6006c/ssv6006C_reg.h	2192;"	d
+GET_FBUS_DMAC_CH_STATUSTR_TR	smac/hal/ssv6006c/ssv6006C_reg.h	2191;"	d
+GET_FBUS_DMAC_DAR0	smac/hal/ssv6006c/ssv6006C_reg.h	2156;"	d
+GET_FBUS_DMAC_DAR1	smac/hal/ssv6006c/ssv6006C_reg.h	2173;"	d
+GET_FBUS_DMAC_DINC0	smac/hal/ssv6006c/ssv6006C_reg.h	2160;"	d
+GET_FBUS_DMAC_DINC1	smac/hal/ssv6006c/ssv6006C_reg.h	2177;"	d
+GET_FBUS_DMAC_DISEN_SHS_DST_REQ	smac/hal/ssv6006c/ssv6006C_reg.h	2200;"	d
+GET_FBUS_DMAC_DISEN_SHS_DST_SREQ	smac/hal/ssv6006c/ssv6006C_reg.h	2202;"	d
+GET_FBUS_DMAC_DISEN_SHS_SRC_REQ	smac/hal/ssv6006c/ssv6006C_reg.h	2199;"	d
+GET_FBUS_DMAC_DISEN_SHS_SRC_SREQ	smac/hal/ssv6006c/ssv6006C_reg.h	2201;"	d
+GET_FBUS_DMAC_DST_HS_BUS_SEL0	smac/hal/ssv6006c/ssv6006C_reg.h	2171;"	d
+GET_FBUS_DMAC_DST_HS_BUS_SEL1	smac/hal/ssv6006c/ssv6006C_reg.h	2188;"	d
+GET_FBUS_DMAC_DST_MSIZE0	smac/hal/ssv6006c/ssv6006C_reg.h	2162;"	d
+GET_FBUS_DMAC_DST_MSIZE1	smac/hal/ssv6006c/ssv6006C_reg.h	2179;"	d
+GET_FBUS_DMAC_DST_TR_WIDTH0	smac/hal/ssv6006c/ssv6006C_reg.h	2158;"	d
+GET_FBUS_DMAC_DST_TR_WIDTH1	smac/hal/ssv6006c/ssv6006C_reg.h	2175;"	d
+GET_FBUS_DMAC_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2203;"	d
+GET_FBUS_DMAC_FC_MODE0	smac/hal/ssv6006c/ssv6006C_reg.h	2164;"	d
+GET_FBUS_DMAC_FC_MODE1	smac/hal/ssv6006c/ssv6006C_reg.h	2181;"	d
+GET_FBUS_DMAC_HS_SEL_DST0	smac/hal/ssv6006c/ssv6006C_reg.h	2167;"	d
+GET_FBUS_DMAC_HS_SEL_DST1	smac/hal/ssv6006c/ssv6006C_reg.h	2184;"	d
+GET_FBUS_DMAC_HS_SEL_SRC0	smac/hal/ssv6006c/ssv6006C_reg.h	2168;"	d
+GET_FBUS_DMAC_HS_SEL_SRC1	smac/hal/ssv6006c/ssv6006C_reg.h	2185;"	d
+GET_FBUS_DMAC_INTR_EN0	smac/hal/ssv6006c/ssv6006C_reg.h	2157;"	d
+GET_FBUS_DMAC_INTR_EN1	smac/hal/ssv6006c/ssv6006C_reg.h	2174;"	d
+GET_FBUS_DMAC_MAX_BURST_LEN0	smac/hal/ssv6006c/ssv6006C_reg.h	2169;"	d
+GET_FBUS_DMAC_MAX_BURST_LEN1	smac/hal/ssv6006c/ssv6006C_reg.h	2186;"	d
+GET_FBUS_DMAC_SAR0	smac/hal/ssv6006c/ssv6006C_reg.h	2155;"	d
+GET_FBUS_DMAC_SAR1	smac/hal/ssv6006c/ssv6006C_reg.h	2172;"	d
+GET_FBUS_DMAC_SINC0	smac/hal/ssv6006c/ssv6006C_reg.h	2161;"	d
+GET_FBUS_DMAC_SINC1	smac/hal/ssv6006c/ssv6006C_reg.h	2178;"	d
+GET_FBUS_DMAC_SRC_HS_BUS_SEL0	smac/hal/ssv6006c/ssv6006C_reg.h	2170;"	d
+GET_FBUS_DMAC_SRC_HS_BUS_SEL1	smac/hal/ssv6006c/ssv6006C_reg.h	2187;"	d
+GET_FBUS_DMAC_SRC_MSIZE0	smac/hal/ssv6006c/ssv6006C_reg.h	2163;"	d
+GET_FBUS_DMAC_SRC_MSIZE1	smac/hal/ssv6006c/ssv6006C_reg.h	2180;"	d
+GET_FBUS_DMAC_SRC_TR_WIDTH0	smac/hal/ssv6006c/ssv6006C_reg.h	2159;"	d
+GET_FBUS_DMAC_SRC_TR_WIDTH1	smac/hal/ssv6006c/ssv6006C_reg.h	2176;"	d
+GET_FBUS_SRAM_ERRCK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2445;"	d
+GET_FBUS_SRAM_ERR_INT	smac/hal/ssv6006c/ssv6006C_reg.h	2450;"	d
+GET_FENCE_HIT_ADR	smac/hal/ssv6006c/ssv6006C_reg.h	2441;"	d
+GET_FENCE_HIT_CLR	include/ssv6200_reg.h	1355;"	d
+GET_FENCE_HIT_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2446;"	d
+GET_FENCE_HIT_INT	include/ssv6200_reg.h	1357;"	d
+GET_FENCE_HIT_INT	smac/hal/ssv6006c/ssv6006C_reg.h	2451;"	d
+GET_FF0_CNT	include/ssv6200_reg.h	3554;"	d
+GET_FF0_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8747;"	d
+GET_FF0_EMPTY	include/ssv6200_reg.h	3548;"	d
+GET_FF0_EMPTY	smac/hal/ssv6006c/ssv6006C_reg.h	8739;"	d
+GET_FF10_CNT	include/ssv6200_reg.h	3562;"	d
+GET_FF10_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8755;"	d
+GET_FF11_CNT	include/ssv6200_reg.h	3563;"	d
+GET_FF11_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8756;"	d
+GET_FF12_CNT	include/ssv6200_reg.h	3564;"	d
+GET_FF12_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8757;"	d
+GET_FF13_CNT	include/ssv6200_reg.h	3565;"	d
+GET_FF13_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8758;"	d
+GET_FF14_CNT	include/ssv6200_reg.h	3566;"	d
+GET_FF14_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8759;"	d
+GET_FF15_CNT	include/ssv6200_reg.h	3567;"	d
+GET_FF15_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8760;"	d
+GET_FF1_CNT	include/ssv6200_reg.h	3555;"	d
+GET_FF1_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8748;"	d
+GET_FF2_CNT	include/ssv6200_reg.h	3569;"	d
+GET_FF2_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8762;"	d
+GET_FF2_EMPTY	smac/hal/ssv6006c/ssv6006C_reg.h	8741;"	d
+GET_FF3_CNT	include/ssv6200_reg.h	3556;"	d
+GET_FF3_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8749;"	d
+GET_FF4_CNT	include/ssv6200_reg.h	3568;"	d
+GET_FF4_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8761;"	d
+GET_FF5_CNT	include/ssv6200_reg.h	3557;"	d
+GET_FF5_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8750;"	d
+GET_FF6_CNT	include/ssv6200_reg.h	3558;"	d
+GET_FF6_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8751;"	d
+GET_FF7_CNT	include/ssv6200_reg.h	3559;"	d
+GET_FF7_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8752;"	d
+GET_FF8_CNT	include/ssv6200_reg.h	3560;"	d
+GET_FF8_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8753;"	d
+GET_FF9_CNT	include/ssv6200_reg.h	3561;"	d
+GET_FF9_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8754;"	d
+GET_FFO0_CNT	include/ssv6200_reg.h	3663;"	d
+GET_FFO0_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8859;"	d
+GET_FFO10_CNT	include/ssv6200_reg.h	3673;"	d
+GET_FFO10_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8869;"	d
+GET_FFO11_CNT	include/ssv6200_reg.h	3674;"	d
+GET_FFO11_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8870;"	d
+GET_FFO12_CNT	include/ssv6200_reg.h	3675;"	d
+GET_FFO12_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8871;"	d
+GET_FFO13_CNT	include/ssv6200_reg.h	3676;"	d
+GET_FFO13_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8872;"	d
+GET_FFO14_CNT	include/ssv6200_reg.h	3677;"	d
+GET_FFO14_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8873;"	d
+GET_FFO15_CNT	include/ssv6200_reg.h	3678;"	d
+GET_FFO15_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8874;"	d
+GET_FFO1_CNT	include/ssv6200_reg.h	3664;"	d
+GET_FFO1_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8860;"	d
+GET_FFO2_CNT	include/ssv6200_reg.h	3665;"	d
+GET_FFO2_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8861;"	d
+GET_FFO3_CNT	include/ssv6200_reg.h	3666;"	d
+GET_FFO3_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8862;"	d
+GET_FFO4_CNT	include/ssv6200_reg.h	3667;"	d
+GET_FFO4_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8863;"	d
+GET_FFO5_CNT	include/ssv6200_reg.h	3668;"	d
+GET_FFO5_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8864;"	d
+GET_FFO6_CNT	include/ssv6200_reg.h	3669;"	d
+GET_FFO6_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8865;"	d
+GET_FFO7_CNT	include/ssv6200_reg.h	3670;"	d
+GET_FFO7_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8866;"	d
+GET_FFO8_CNT	include/ssv6200_reg.h	3671;"	d
+GET_FFO8_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8867;"	d
+GET_FFO9_CNT	include/ssv6200_reg.h	3672;"	d
+GET_FFO9_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8868;"	d
+GET_FIFODATA_ERR	include/ssv6200_reg.h	2147;"	d
+GET_FIFODATA_ERR	smac/hal/ssv6006c/ssv6006C_reg.h	2858;"	d
+GET_FIFOS_ENABLED	include/ssv6200_reg.h	2160;"	d
+GET_FIFOS_ENABLED	smac/hal/ssv6006c/ssv6006C_reg.h	2873;"	d
+GET_FIFO_EN	include/ssv6200_reg.h	2121;"	d
+GET_FIFO_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2831;"	d
+GET_FIQ_RAW	include/ssv6200_reg.h	2243;"	d
+GET_FIQ_STATUS	include/ssv6200_reg.h	2241;"	d
+GET_FLASH_ADDR	include/ssv6200_reg.h	2396;"	d
+GET_FLASH_BACK_DLY	include/ssv6200_reg.h	2404;"	d
+GET_FLASH_BACK_DLY	smac/hal/ssv6006c/ssv6006C_reg.h	2955;"	d
+GET_FLASH_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2381;"	d
+GET_FLASH_CLK_WIDTH	include/ssv6200_reg.h	2405;"	d
+GET_FLASH_CMD_CLR	include/ssv6200_reg.h	2397;"	d
+GET_FLASH_DMA_CLR	include/ssv6200_reg.h	2398;"	d
+GET_FLASH_DMA_LEN	include/ssv6200_reg.h	2402;"	d
+GET_FLASH_FRONT_DLY	include/ssv6200_reg.h	2403;"	d
+GET_FLASH_FRONT_DLY	smac/hal/ssv6006c/ssv6006C_reg.h	2954;"	d
+GET_FLS_CLK_IN_DLY_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	2973;"	d
+GET_FLS_CLK_OUT_DLY_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	2974;"	d
+GET_FLS_MISO_IN_DLY_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	2977;"	d
+GET_FLS_MISO_OUT_DLY_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	2978;"	d
+GET_FLS_MOSI_IN_DLY_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	2975;"	d
+GET_FLS_MOSI_OUT_DLY_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	2976;"	d
+GET_FLS_NC_IN_DLY_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	2981;"	d
+GET_FLS_NC_OUT_DLY_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	2982;"	d
+GET_FLS_REMAP	include/ssv6200_reg.h	2407;"	d
+GET_FLS_WP_IN_DLY_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	2979;"	d
+GET_FLS_WP_OUT_DLY_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	2980;"	d
+GET_FN1_DMA_RD_START_ADDR_REG	smac/hal/ssv6006c/ssv6006C_reg.h	2705;"	d
+GET_FN1_DMA_START_ADDR_REG	include/ssv6200_reg.h	1939;"	d
+GET_FN1_DMA_START_ADDR_REG	smac/hal/ssv6006c/ssv6006C_reg.h	2697;"	d
+GET_FORCE_GET_RK	include/ssv6200_reg.h	2601;"	d
+GET_FORCE_PARITY	include/ssv6200_reg.h	2132;"	d
+GET_FORCE_PARITY	smac/hal/ssv6006c/ssv6006C_reg.h	2842;"	d
+GET_FPGA_TO_GEMINIA_ADC_EDGE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	9073;"	d
+GET_FPGA_TO_GEMINIA_DAC_EDGE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	9072;"	d
+GET_FPGA_TO_GEMINIA_DAC_SIGN_SWAP	smac/hal/ssv6006c/ssv6006C_reg.h	9071;"	d
+GET_FRAME_LEN	include/ssv6200_reg.h	2555;"	d
+GET_FRAME_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	3293;"	d
+GET_FRAMING	smac/hal/ssv6006c/ssv6006C_reg.h	2882;"	d
+GET_FRAMING_ERR	include/ssv6200_reg.h	2143;"	d
+GET_FRAMING_ERR	smac/hal/ssv6006c/ssv6006C_reg.h	2854;"	d
+GET_FRM_CTRL	include/ssv6200_reg.h	2737;"	d
+GET_FRM_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	3446;"	d
+GET_FRONT_DLY	include/ssv6200_reg.h	2056;"	d
+GET_FRONT_DLY	smac/hal/ssv6006c/ssv6006C_reg.h	2768;"	d
+GET_FSM_SYSCTRL	smac/hal/ssv6006c/ssv6006C_reg.h	2435;"	d
+GET_FW_EVENT	smac/hal/ssv6006c/ssv6006C_reg.h	2464;"	d
+GET_G0_PKT_CLS_MIB_EN	include/ssv6200_reg.h	3131;"	d
+GET_G0_PKT_CLS_MIB_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3979;"	d
+GET_G0_PKT_CLS_ONGOING	include/ssv6200_reg.h	3132;"	d
+GET_G0_PKT_CLS_ONGOING	smac/hal/ssv6006c/ssv6006C_reg.h	3980;"	d
+GET_G1_PKT_CLS_MIB_EN	include/ssv6200_reg.h	3133;"	d
+GET_G1_PKT_CLS_MIB_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3981;"	d
+GET_G1_PKT_CLS_ONGOING	include/ssv6200_reg.h	3134;"	d
+GET_G1_PKT_CLS_ONGOING	smac/hal/ssv6006c/ssv6006C_reg.h	3982;"	d
+GET_GEMINIA_SAR_ADC_FSM_RDY	smac/hal/ssv6006c/ssv6006C_reg.h	4827;"	d
+GET_GET_RK	include/ssv6200_reg.h	2600;"	d
+GET_GN_CCA_CNT	include/ssv6200_reg.h	4316;"	d
+GET_GN_LENGTH_FIELD	include/ssv6200_reg.h	4317;"	d
+GET_GN_NOISE_PWR	include/ssv6200_reg.h	4307;"	d
+GET_GN_PACKET_CNT	include/ssv6200_reg.h	4315;"	d
+GET_GN_PACKET_ERR_CNT	include/ssv6200_reg.h	4314;"	d
+GET_GN_RCPI	include/ssv6200_reg.h	4308;"	d
+GET_GN_SERVICE_FIELD	include/ssv6200_reg.h	4318;"	d
+GET_GN_SIGNAL_PWR	include/ssv6200_reg.h	4309;"	d
+GET_GN_SNR	include/ssv6200_reg.h	4306;"	d
+GET_GPIO_10_ID	include/ssv6200_reg.h	1675;"	d
+GET_GPIO_11_ID	include/ssv6200_reg.h	1684;"	d
+GET_GPIO_12_ID	include/ssv6200_reg.h	1693;"	d
+GET_GPIO_13_ID	include/ssv6200_reg.h	1702;"	d
+GET_GPIO_14_ID	include/ssv6200_reg.h	1710;"	d
+GET_GPIO_15_IP_ID	include/ssv6200_reg.h	1787;"	d
+GET_GPIO_17_QP_ID	include/ssv6200_reg.h	1803;"	d
+GET_GPIO_19_ID	include/ssv6200_reg.h	1810;"	d
+GET_GPIO_1_ID	include/ssv6200_reg.h	1552;"	d
+GET_GPIO_20_ID	include/ssv6200_reg.h	1827;"	d
+GET_GPIO_21_ID	include/ssv6200_reg.h	1835;"	d
+GET_GPIO_2_ID	include/ssv6200_reg.h	1560;"	d
+GET_GPIO_3_ID	include/ssv6200_reg.h	1569;"	d
+GET_GPIO_9_ID	include/ssv6200_reg.h	1665;"	d
+GET_GPIO_CLK_EN	include/ssv6200_reg.h	1311;"	d
+GET_GPIO_INT_TRIGGER_OPTION	include/ssv6200_reg.h	1894;"	d
+GET_GPIO_INT_TRIGGER_OPTION	smac/hal/ssv6006c/ssv6006C_reg.h	2677;"	d
+GET_GPIO_LOG_STOP_SEL	include/ssv6200_reg.h	1857;"	d
+GET_GPIO_STOP_EN	include/ssv6200_reg.h	3751;"	d
+GET_GPIO_STOP_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2426;"	d
+GET_GPIO_STOP_POL	include/ssv6200_reg.h	3752;"	d
+GET_GPIO_STOP_POL	smac/hal/ssv6006c/ssv6006C_reg.h	2425;"	d
+GET_GPIO_STOP_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	2424;"	d
+GET_GPIO_SW_RST	include/ssv6200_reg.h	1277;"	d
+GET_GPIO_TEST_1_ID	include/ssv6200_reg.h	1516;"	d
+GET_GPIO_TEST_2_ID	include/ssv6200_reg.h	1525;"	d
+GET_GPIO_TEST_3_ID	include/ssv6200_reg.h	1534;"	d
+GET_GPIO_TEST_4_ID	include/ssv6200_reg.h	1542;"	d
+GET_GPIO_TEST_5_ID	include/ssv6200_reg.h	1577;"	d
+GET_GPIO_TEST_7_IN_ID	include/ssv6200_reg.h	1795;"	d
+GET_GPIO_TEST_8_QN_ID	include/ssv6200_reg.h	1818;"	d
+GET_GPO_INT_POL	smac/hal/ssv6006c/ssv6006C_reg.h	3089;"	d
+GET_GRP_SCRT	include/ssv6200_reg.h	3103;"	d
+GET_GRP_SCRT	smac/hal/ssv6006c/ssv6006C_reg.h	3936;"	d
+GET_GRP_WSID	smac/hal/ssv6006c/ssv6006C_reg.h	3438;"	d
+GET_GURAN_USE_CTRL	include/ssv6200_reg.h	3111;"	d
+GET_GURAN_USE_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	3950;"	d
+GET_GURAN_USE_EN	include/ssv6200_reg.h	3110;"	d
+GET_GURAN_USE_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3949;"	d
+GET_HALT_CH0	include/ssv6200_reg.h	3585;"	d
+GET_HALT_CH1	include/ssv6200_reg.h	3586;"	d
+GET_HALT_CH1	smac/hal/ssv6006c/ssv6006C_reg.h	8782;"	d
+GET_HALT_CH10	include/ssv6200_reg.h	3595;"	d
+GET_HALT_CH10	smac/hal/ssv6006c/ssv6006C_reg.h	8790;"	d
+GET_HALT_CH11	include/ssv6200_reg.h	3596;"	d
+GET_HALT_CH11	smac/hal/ssv6006c/ssv6006C_reg.h	8791;"	d
+GET_HALT_CH12	include/ssv6200_reg.h	3597;"	d
+GET_HALT_CH12	smac/hal/ssv6006c/ssv6006C_reg.h	8792;"	d
+GET_HALT_CH13	include/ssv6200_reg.h	3598;"	d
+GET_HALT_CH13	smac/hal/ssv6006c/ssv6006C_reg.h	8793;"	d
+GET_HALT_CH14	include/ssv6200_reg.h	3599;"	d
+GET_HALT_CH14	smac/hal/ssv6006c/ssv6006C_reg.h	8794;"	d
+GET_HALT_CH15	include/ssv6200_reg.h	3600;"	d
+GET_HALT_CH2	include/ssv6200_reg.h	3587;"	d
+GET_HALT_CH3	include/ssv6200_reg.h	3588;"	d
+GET_HALT_CH3	smac/hal/ssv6006c/ssv6006C_reg.h	8783;"	d
+GET_HALT_CH4	include/ssv6200_reg.h	3589;"	d
+GET_HALT_CH4	smac/hal/ssv6006c/ssv6006C_reg.h	8784;"	d
+GET_HALT_CH5	include/ssv6200_reg.h	3590;"	d
+GET_HALT_CH5	smac/hal/ssv6006c/ssv6006C_reg.h	8785;"	d
+GET_HALT_CH6	include/ssv6200_reg.h	3591;"	d
+GET_HALT_CH6	smac/hal/ssv6006c/ssv6006C_reg.h	8786;"	d
+GET_HALT_CH7	include/ssv6200_reg.h	3592;"	d
+GET_HALT_CH7	smac/hal/ssv6006c/ssv6006C_reg.h	8787;"	d
+GET_HALT_CH8	include/ssv6200_reg.h	3593;"	d
+GET_HALT_CH8	smac/hal/ssv6006c/ssv6006C_reg.h	8788;"	d
+GET_HALT_CH9	include/ssv6200_reg.h	3594;"	d
+GET_HALT_CH9	smac/hal/ssv6006c/ssv6006C_reg.h	8789;"	d
+GET_HAS_MANUAL_BUF	smac/hal/ssv6006c/ssv6006C_reg.h	3214;"	d
+GET_HBURST_LOCK	include/ssv6200_reg.h	1371;"	d
+GET_HBURST_LOCK	smac/hal/ssv6006c/ssv6006C_reg.h	2440;"	d
+GET_HBUSREQ_LOCK	include/ssv6200_reg.h	1370;"	d
+GET_HBUSREQ_LOCK	smac/hal/ssv6006c/ssv6006C_reg.h	2439;"	d
+GET_HCI_BULK_IN_HOST_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	3229;"	d
+GET_HCI_BULK_IN_TIME_OUT	smac/hal/ssv6006c/ssv6006C_reg.h	3230;"	d
+GET_HCI_CLK_EN	include/ssv6200_reg.h	3059;"	d
+GET_HCI_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3891;"	d
+GET_HCI_ENG_CLK_EN	include/ssv6200_reg.h	3071;"	d
+GET_HCI_ENG_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3903;"	d
+GET_HCI_INPUT_FF_CNT	include/ssv6200_reg.h	1910;"	d
+GET_HCI_INPUT_FF_CNT2	include/ssv6200_reg.h	1981;"	d
+GET_HCI_INPUT_QUEUE_FULL	include/ssv6200_reg.h	1968;"	d
+GET_HCI_INQ_SEL	include/ssv6200_reg.h	2486;"	d
+GET_HCI_INT_1	include/ssv6200_reg.h	2258;"	d
+GET_HCI_INT_1_SD	include/ssv6200_reg.h	2327;"	d
+GET_HCI_IN_QUE_EMPTY	include/ssv6200_reg.h	1913;"	d
+GET_HCI_IN_QUE_EMPTY2	include/ssv6200_reg.h	1971;"	d
+GET_HCI_MB_MAX_CNT	include/ssv6200_reg.h	2522;"	d
+GET_HCI_MB_MAX_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	3237;"	d
+GET_HCI_MONITOR_REG0	smac/hal/ssv6006c/ssv6006C_reg.h	3231;"	d
+GET_HCI_MONITOR_REG1	include/ssv6200_reg.h	2518;"	d
+GET_HCI_MONITOR_REG2	include/ssv6200_reg.h	2519;"	d
+GET_HCI_MONITOR_REG2	smac/hal/ssv6006c/ssv6006C_reg.h	3232;"	d
+GET_HCI_MONITOR_REG3	smac/hal/ssv6006c/ssv6006C_reg.h	3233;"	d
+GET_HCI_MONITOR_REG4	smac/hal/ssv6006c/ssv6006C_reg.h	3234;"	d
+GET_HCI_MONITOR_REG5	smac/hal/ssv6006c/ssv6006C_reg.h	3235;"	d
+GET_HCI_OUTPUT_FF_CNT	include/ssv6200_reg.h	1911;"	d
+GET_HCI_OUTPUT_FF_CNT2	include/ssv6200_reg.h	1980;"	d
+GET_HCI_OUTPUT_FF_CNT_0	include/ssv6200_reg.h	1979;"	d
+GET_HCI_PENDING_RX_MPDU_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	3224;"	d
+GET_HCI_PROC_CNT	include/ssv6200_reg.h	2525;"	d
+GET_HCI_PROC_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	3238;"	d
+GET_HCI_RX_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3186;"	d
+GET_HCI_RX_FORM_0	smac/hal/ssv6006c/ssv6006C_reg.h	3188;"	d
+GET_HCI_RX_FORM_1	smac/hal/ssv6006c/ssv6006C_reg.h	3187;"	d
+GET_HCI_RX_HALT	smac/hal/ssv6006c/ssv6006C_reg.h	3225;"	d
+GET_HCI_RX_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	3194;"	d
+GET_HCI_RX_MPDU_DEQUE	smac/hal/ssv6006c/ssv6006C_reg.h	3228;"	d
+GET_HCI_STATE_MONITOR	include/ssv6200_reg.h	2515;"	d
+GET_HCI_ST_TIMEOUT_MONITOR	include/ssv6200_reg.h	2516;"	d
+GET_HCI_SW_RST	include/ssv6200_reg.h	3022;"	d
+GET_HCI_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	3853;"	d
+GET_HCI_TRX_FINISH	include/ssv6200_reg.h	1908;"	d
+GET_HCI_TRX_FINISH2	include/ssv6200_reg.h	1966;"	d
+GET_HCI_TRX_FINISH3	include/ssv6200_reg.h	1970;"	d
+GET_HCI_TX_AGG_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3185;"	d
+GET_HCI_TX_ALLOC_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	3241;"	d
+GET_HCI_TX_ALLOC_CNT_31_0	include/ssv6200_reg.h	2523;"	d
+GET_HCI_TX_ALLOC_CNT_47_32	include/ssv6200_reg.h	2524;"	d
+GET_HCI_TX_ALLOC_TIME	smac/hal/ssv6006c/ssv6006C_reg.h	3242;"	d
+GET_HCI_TX_ALLOC_TIME_31_0	include/ssv6200_reg.h	2520;"	d
+GET_HCI_TX_ALLOC_TIME_47_32	include/ssv6200_reg.h	2521;"	d
+GET_HDR_STRIP	include/ssv6200_reg.h	2477;"	d
+GET_HDR_STRIP	smac/hal/ssv6006c/ssv6006C_reg.h	3176;"	d
+GET_HIF_LOOP_BACK	smac/hal/ssv6006c/ssv6006C_reg.h	3226;"	d
+GET_HOST_CMD_COUNTER	include/ssv6200_reg.h	2507;"	d
+GET_HOST_CMD_COUNTER	smac/hal/ssv6006c/ssv6006C_reg.h	3248;"	d
+GET_HOST_EVENT	smac/hal/ssv6006c/ssv6006C_reg.h	2465;"	d
+GET_HOST_EVENT_COUNTER	include/ssv6200_reg.h	2508;"	d
+GET_HOST_EVENT_COUNTER	smac/hal/ssv6006c/ssv6006C_reg.h	3247;"	d
+GET_HOST_PATH	include/ssv6200_reg.h	2050;"	d
+GET_HOST_RX_FAIL_COUNTER	include/ssv6200_reg.h	2514;"	d
+GET_HOST_RX_FAIL_COUNTER	smac/hal/ssv6006c/ssv6006C_reg.h	3251;"	d
+GET_HOST_TRIGGERED_RX_INT	include/ssv6200_reg.h	1886;"	d
+GET_HOST_TRIGGERED_RX_INT	smac/hal/ssv6006c/ssv6006C_reg.h	2669;"	d
+GET_HOST_TRIGGERED_TX_INT	include/ssv6200_reg.h	1887;"	d
+GET_HOST_TRIGGERED_TX_INT	smac/hal/ssv6006c/ssv6006C_reg.h	2670;"	d
+GET_HOST_TX_FAIL_COUNTER	include/ssv6200_reg.h	2513;"	d
+GET_HOST_TX_FAIL_COUNTER	smac/hal/ssv6006c/ssv6006C_reg.h	3252;"	d
+GET_HOST_WAKE_WIFI	smac/hal/ssv6006c/ssv6006C_reg.h	2504;"	d
+GET_HOST_WAKE_WIFI_POL	smac/hal/ssv6006c/ssv6006C_reg.h	2505;"	d
+GET_HSUART_ACTS	smac/hal/ssv6006c/ssv6006C_reg.h	2915;"	d
+GET_HSUART_ARTS	smac/hal/ssv6006c/ssv6006C_reg.h	2914;"	d
+GET_HSUART_BI	smac/hal/ssv6006c/ssv6006C_reg.h	2920;"	d
+GET_HSUART_CTS	smac/hal/ssv6006c/ssv6006C_reg.h	2928;"	d
+GET_HSUART_DCR	smac/hal/ssv6006c/ssv6006C_reg.h	2931;"	d
+GET_HSUART_DCTS	smac/hal/ssv6006c/ssv6006C_reg.h	2924;"	d
+GET_HSUART_DDCD	smac/hal/ssv6006c/ssv6006C_reg.h	2927;"	d
+GET_HSUART_DDSR	smac/hal/ssv6006c/ssv6006C_reg.h	2925;"	d
+GET_HSUART_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	2941;"	d
+GET_HSUART_DLAB	smac/hal/ssv6006c/ssv6006C_reg.h	2908;"	d
+GET_HSUART_DMA	smac/hal/ssv6006c/ssv6006C_reg.h	2901;"	d
+GET_HSUART_DMA_RX_END_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	2945;"	d
+GET_HSUART_DMA_RX_RPT	smac/hal/ssv6006c/ssv6006C_reg.h	2947;"	d
+GET_HSUART_DMA_RX_STR_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	2944;"	d
+GET_HSUART_DMA_RX_WPT	smac/hal/ssv6006c/ssv6006C_reg.h	2946;"	d
+GET_HSUART_DMA_TX_END_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	2949;"	d
+GET_HSUART_DMA_TX_RPT	smac/hal/ssv6006c/ssv6006C_reg.h	2951;"	d
+GET_HSUART_DMA_TX_STR_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	2948;"	d
+GET_HSUART_DMA_TX_WPT	smac/hal/ssv6006c/ssv6006C_reg.h	2950;"	d
+GET_HSUART_DR	smac/hal/ssv6006c/ssv6006C_reg.h	2916;"	d
+GET_HSUART_DSR	smac/hal/ssv6006c/ssv6006C_reg.h	2929;"	d
+GET_HSUART_DTS	smac/hal/ssv6006c/ssv6006C_reg.h	2909;"	d
+GET_HSUART_ENABCTXTHR	smac/hal/ssv6006c/ssv6006C_reg.h	2895;"	d
+GET_HSUART_ENABDMARXEND	smac/hal/ssv6006c/ssv6006C_reg.h	2896;"	d
+GET_HSUART_ENABDMATXEND	smac/hal/ssv6006c/ssv6006C_reg.h	2897;"	d
+GET_HSUART_ENABLNSTAT	smac/hal/ssv6006c/ssv6006C_reg.h	2893;"	d
+GET_HSUART_ENABMDSTAT	smac/hal/ssv6006c/ssv6006C_reg.h	2894;"	d
+GET_HSUART_ENABRXBUFF	smac/hal/ssv6006c/ssv6006C_reg.h	2891;"	d
+GET_HSUART_ENABTXBUFF	smac/hal/ssv6006c/ssv6006C_reg.h	2892;"	d
+GET_HSUART_ERF	smac/hal/ssv6006c/ssv6006C_reg.h	2923;"	d
+GET_HSUART_FE	smac/hal/ssv6006c/ssv6006C_reg.h	2919;"	d
+GET_HSUART_FIFOE	smac/hal/ssv6006c/ssv6006C_reg.h	2898;"	d
+GET_HSUART_FRAC	smac/hal/ssv6006c/ssv6006C_reg.h	2942;"	d
+GET_HSUART_IFIFOE1	smac/hal/ssv6006c/ssv6006C_reg.h	2940;"	d
+GET_HSUART_IFOFOE0	smac/hal/ssv6006c/ssv6006C_reg.h	2939;"	d
+GET_HSUART_IIR	smac/hal/ssv6006c/ssv6006C_reg.h	2937;"	d
+GET_HSUART_INT	smac/hal/ssv6006c/ssv6006C_reg.h	2943;"	d
+GET_HSUART_LOOP1	smac/hal/ssv6006c/ssv6006C_reg.h	2913;"	d
+GET_HSUART_OE	smac/hal/ssv6006c/ssv6006C_reg.h	2917;"	d
+GET_HSUART_OUT1	smac/hal/ssv6006c/ssv6006C_reg.h	2911;"	d
+GET_HSUART_OUT2	smac/hal/ssv6006c/ssv6006C_reg.h	2912;"	d
+GET_HSUART_PE	smac/hal/ssv6006c/ssv6006C_reg.h	2918;"	d
+GET_HSUART_PEN	smac/hal/ssv6006c/ssv6006C_reg.h	2905;"	d
+GET_HSUART_RI	smac/hal/ssv6006c/ssv6006C_reg.h	2930;"	d
+GET_HSUART_RTS	smac/hal/ssv6006c/ssv6006C_reg.h	2910;"	d
+GET_HSUART_RTS_AUTO_TH_H	smac/hal/ssv6006c/ssv6006C_reg.h	2934;"	d
+GET_HSUART_RTS_AUTO_TH_L	smac/hal/ssv6006c/ssv6006C_reg.h	2933;"	d
+GET_HSUART_RXD	smac/hal/ssv6006c/ssv6006C_reg.h	2890;"	d
+GET_HSUART_RX_FIFO_RST	smac/hal/ssv6006c/ssv6006C_reg.h	2899;"	d
+GET_HSUART_RX_TRIG_LV	smac/hal/ssv6006c/ssv6006C_reg.h	2902;"	d
+GET_HSUART_SB	smac/hal/ssv6006c/ssv6006C_reg.h	2907;"	d
+GET_HSUART_SCR	smac/hal/ssv6006c/ssv6006C_reg.h	2932;"	d
+GET_HSUART_SP_EPS	smac/hal/ssv6006c/ssv6006C_reg.h	2906;"	d
+GET_HSUART_STB	smac/hal/ssv6006c/ssv6006C_reg.h	2904;"	d
+GET_HSUART_TERI	smac/hal/ssv6006c/ssv6006C_reg.h	2926;"	d
+GET_HSUART_THRE	smac/hal/ssv6006c/ssv6006C_reg.h	2921;"	d
+GET_HSUART_TSRE	smac/hal/ssv6006c/ssv6006C_reg.h	2922;"	d
+GET_HSUART_TXDMA_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	2938;"	d
+GET_HSUART_TX_FIFO_RST	smac/hal/ssv6006c/ssv6006C_reg.h	2900;"	d
+GET_HSUART_TX_THR_H	smac/hal/ssv6006c/ssv6006C_reg.h	2936;"	d
+GET_HSUART_TX_THR_L	smac/hal/ssv6006c/ssv6006C_reg.h	2935;"	d
+GET_HSUART_WLS	smac/hal/ssv6006c/ssv6006C_reg.h	2903;"	d
+GET_HS_ACCESS_MD	include/ssv6200_reg.h	4798;"	d
+GET_HS_CHANNEL	include/ssv6200_reg.h	4812;"	d
+GET_HS_DATA	include/ssv6200_reg.h	4814;"	d
+GET_HS_FLAG	include/ssv6200_reg.h	4810;"	d
+GET_HS_ID	include/ssv6200_reg.h	4811;"	d
+GET_HS_PAGE	include/ssv6200_reg.h	4813;"	d
+GET_HS_WR	include/ssv6200_reg.h	4809;"	d
+GET_HT_MODE	include/ssv6200_reg.h	3088;"	d
+GET_HT_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	3920;"	d
+GET_HWID	smac/hal/ssv6006c/ssv6006C_reg.h	8734;"	d
+GET_HWID_ALT	smac/hal/ssv6006c/ssv6006C_reg.h	8780;"	d
+GET_HW_PKTID	include/ssv6200_reg.h	3544;"	d
+GET_I2CMST_DISABLE_SLAVE	smac/hal/ssv6006c/ssv6006C_reg.h	2288;"	d
+GET_I2CMST_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2317;"	d
+GET_I2CMST_ENABLE_MASTER	smac/hal/ssv6006c/ssv6006C_reg.h	2285;"	d
+GET_I2CMST_RESTART_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2287;"	d
+GET_I2CMST_RXDONE_INT	smac/hal/ssv6006c/ssv6006C_reg.h	2302;"	d
+GET_I2CMST_RXDONE_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	2308;"	d
+GET_I2CMST_RXDONE_INT_STAR	smac/hal/ssv6006c/ssv6006C_reg.h	2314;"	d
+GET_I2CMST_RXF_INT	smac/hal/ssv6006c/ssv6006C_reg.h	2299;"	d
+GET_I2CMST_RXF_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	2305;"	d
+GET_I2CMST_RXF_INT_STAR	smac/hal/ssv6006c/ssv6006C_reg.h	2311;"	d
+GET_I2CMST_RXO_INT	smac/hal/ssv6006c/ssv6006C_reg.h	2298;"	d
+GET_I2CMST_RXO_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	2304;"	d
+GET_I2CMST_RXO_INT_STAR	smac/hal/ssv6006c/ssv6006C_reg.h	2310;"	d
+GET_I2CMST_RXU_INT	smac/hal/ssv6006c/ssv6006C_reg.h	2297;"	d
+GET_I2CMST_RXU_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	2303;"	d
+GET_I2CMST_RXU_INT_STAR	smac/hal/ssv6006c/ssv6006C_reg.h	2309;"	d
+GET_I2CMST_RX_1STBRDYR	smac/hal/ssv6006c/ssv6006C_reg.h	2294;"	d
+GET_I2CMST_RX_FIFO_TH	smac/hal/ssv6006c/ssv6006C_reg.h	2315;"	d
+GET_I2CMST_SCLK_H_WIDTH	smac/hal/ssv6006c/ssv6006C_reg.h	2295;"	d
+GET_I2CMST_SCLK_L_WIDTH	smac/hal/ssv6006c/ssv6006C_reg.h	2296;"	d
+GET_I2CMST_SPEED	smac/hal/ssv6006c/ssv6006C_reg.h	2286;"	d
+GET_I2CMST_TAR	smac/hal/ssv6006c/ssv6006C_reg.h	2289;"	d
+GET_I2CMST_TRX_CMDW	smac/hal/ssv6006c/ssv6006C_reg.h	2291;"	d
+GET_I2CMST_TRX_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	2290;"	d
+GET_I2CMST_TRX_RESTARTW	smac/hal/ssv6006c/ssv6006C_reg.h	2293;"	d
+GET_I2CMST_TRX_STOPW	smac/hal/ssv6006c/ssv6006C_reg.h	2292;"	d
+GET_I2CMST_TXE_INT	smac/hal/ssv6006c/ssv6006C_reg.h	2301;"	d
+GET_I2CMST_TXE_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	2307;"	d
+GET_I2CMST_TXE_INT_STAR	smac/hal/ssv6006c/ssv6006C_reg.h	2313;"	d
+GET_I2CMST_TXO_INT	smac/hal/ssv6006c/ssv6006C_reg.h	2300;"	d
+GET_I2CMST_TXO_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	2306;"	d
+GET_I2CMST_TXO_INT_STAR	smac/hal/ssv6006c/ssv6006C_reg.h	2312;"	d
+GET_I2CMST_TX_FIFO_TH	smac/hal/ssv6006c/ssv6006C_reg.h	2316;"	d
+GET_I2CM_DEV_A	include/ssv6200_reg.h	2103;"	d
+GET_I2CM_DEV_A	smac/hal/ssv6006c/ssv6006C_reg.h	2812;"	d
+GET_I2CM_DEV_A10B	include/ssv6200_reg.h	2104;"	d
+GET_I2CM_DEV_A10B	smac/hal/ssv6006c/ssv6006C_reg.h	2813;"	d
+GET_I2CM_IDLE	include/ssv6200_reg.h	2097;"	d
+GET_I2CM_IDLE	smac/hal/ssv6006c/ssv6006C_reg.h	2806;"	d
+GET_I2CM_INT_MISMATCH	include/ssv6200_reg.h	2098;"	d
+GET_I2CM_INT_MISMATCH	smac/hal/ssv6006c/ssv6006C_reg.h	2807;"	d
+GET_I2CM_INT_RDATA_NEED	include/ssv6200_reg.h	2102;"	d
+GET_I2CM_INT_RDATA_NEED	smac/hal/ssv6006c/ssv6006C_reg.h	2811;"	d
+GET_I2CM_INT_RDONE	include/ssv6200_reg.h	2096;"	d
+GET_I2CM_INT_RDONE	smac/hal/ssv6006c/ssv6006C_reg.h	2805;"	d
+GET_I2CM_INT_WDATA_NEED	include/ssv6200_reg.h	2101;"	d
+GET_I2CM_INT_WDATA_NEED	smac/hal/ssv6006c/ssv6006C_reg.h	2810;"	d
+GET_I2CM_INT_WDONE	include/ssv6200_reg.h	2095;"	d
+GET_I2CM_INT_WDONE	smac/hal/ssv6006c/ssv6006C_reg.h	2804;"	d
+GET_I2CM_LEN	include/ssv6200_reg.h	2106;"	d
+GET_I2CM_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	2815;"	d
+GET_I2CM_MANUAL_MODE	include/ssv6200_reg.h	2100;"	d
+GET_I2CM_MANUAL_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	2809;"	d
+GET_I2CM_PSCL	include/ssv6200_reg.h	2099;"	d
+GET_I2CM_PSCL	smac/hal/ssv6006c/ssv6006C_reg.h	2808;"	d
+GET_I2CM_RDAT	include/ssv6200_reg.h	2110;"	d
+GET_I2CM_RDAT	smac/hal/ssv6006c/ssv6006C_reg.h	2819;"	d
+GET_I2CM_REPEAT_START	include/ssv6200_reg.h	2113;"	d
+GET_I2CM_REPEAT_START	smac/hal/ssv6006c/ssv6006C_reg.h	2822;"	d
+GET_I2CM_RX	include/ssv6200_reg.h	2105;"	d
+GET_I2CM_RX	smac/hal/ssv6006c/ssv6006C_reg.h	2814;"	d
+GET_I2CM_R_GET	include/ssv6200_reg.h	2108;"	d
+GET_I2CM_R_GET	smac/hal/ssv6006c/ssv6006C_reg.h	2817;"	d
+GET_I2CM_SCL_ID_SEL	include/ssv6200_reg.h	1864;"	d
+GET_I2CM_SDA_ID_SEL	include/ssv6200_reg.h	1850;"	d
+GET_I2CM_SR_LEN	include/ssv6200_reg.h	2111;"	d
+GET_I2CM_SR_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	2820;"	d
+GET_I2CM_SR_RX	include/ssv6200_reg.h	2112;"	d
+GET_I2CM_SR_RX	smac/hal/ssv6006c/ssv6006C_reg.h	2821;"	d
+GET_I2CM_STA_STO_PSCL	smac/hal/ssv6006c/ssv6006C_reg.h	2823;"	d
+GET_I2CM_T_LEFT	include/ssv6200_reg.h	2107;"	d
+GET_I2CM_T_LEFT	smac/hal/ssv6006c/ssv6006C_reg.h	2816;"	d
+GET_I2CM_WDAT	include/ssv6200_reg.h	2109;"	d
+GET_I2CM_WDAT	smac/hal/ssv6006c/ssv6006C_reg.h	2818;"	d
+GET_I2CS_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	2645;"	d
+GET_I2CS_ADDR_DC	smac/hal/ssv6006c/ssv6006C_reg.h	2644;"	d
+GET_I2CS_DATA_CONFIG	smac/hal/ssv6006c/ssv6006C_reg.h	2650;"	d
+GET_I2CS_HOLD_BUS_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2651;"	d
+GET_I2CS_IDLE	smac/hal/ssv6006c/ssv6006C_reg.h	2647;"	d
+GET_I2CS_INT	smac/hal/ssv6006c/ssv6006C_reg.h	2646;"	d
+GET_I2CS_STATE	smac/hal/ssv6006c/ssv6006C_reg.h	2649;"	d
+GET_I2CS_TIME_OUT_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	2648;"	d
+GET_I2C_MST_CLK_EN	include/ssv6200_reg.h	1321;"	d
+GET_I2C_MST_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2402;"	d
+GET_I2C_MST_SW_RST	include/ssv6200_reg.h	1289;"	d
+GET_I2C_MST_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	2368;"	d
+GET_I2C_SLV_CLK_EN	include/ssv6200_reg.h	1308;"	d
+GET_I2C_SLV_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2387;"	d
+GET_I2C_SLV_SW_RST	include/ssv6200_reg.h	1274;"	d
+GET_I2C_SLV_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	2354;"	d
+GET_I2SMAS_CLK_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	2436;"	d
+GET_I2S_ENABLE	smac/hal/ssv6006c/ssv6006C_reg.h	2255;"	d
+GET_I2S_INTR_RXDA	smac/hal/ssv6006c/ssv6006C_reg.h	2269;"	d
+GET_I2S_INTR_RXFA_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	2273;"	d
+GET_I2S_INTR_RXFE	smac/hal/ssv6006c/ssv6006C_reg.h	2271;"	d
+GET_I2S_INTR_RXFO	smac/hal/ssv6006c/ssv6006C_reg.h	2270;"	d
+GET_I2S_INTR_RXFO_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	2274;"	d
+GET_I2S_INTR_TXFE_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	2275;"	d
+GET_I2S_INTR_TXFO	smac/hal/ssv6006c/ssv6006C_reg.h	2272;"	d
+GET_I2S_INTR_TXFO_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	2276;"	d
+GET_I2S_L_TRX_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	2263;"	d
+GET_I2S_MASTER	smac/hal/ssv6006c/ssv6006C_reg.h	2438;"	d
+GET_I2S_MCLK_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	2437;"	d
+GET_I2S_PCLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2409;"	d
+GET_I2S_RAW_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	2637;"	d
+GET_I2S_RST_RXFIFO	smac/hal/ssv6006c/ssv6006C_reg.h	2261;"	d
+GET_I2S_RST_TXFIFO	smac/hal/ssv6006c/ssv6006C_reg.h	2262;"	d
+GET_I2S_RXFO	smac/hal/ssv6006c/ssv6006C_reg.h	2277;"	d
+GET_I2S_RX_CH_ENABLE	smac/hal/ssv6006c/ssv6006C_reg.h	2265;"	d
+GET_I2S_RX_DMA	smac/hal/ssv6006c/ssv6006C_reg.h	2283;"	d
+GET_I2S_RX_ENABLE	smac/hal/ssv6006c/ssv6006C_reg.h	2256;"	d
+GET_I2S_RX_FIFO_FLUSH	smac/hal/ssv6006c/ssv6006C_reg.h	2281;"	d
+GET_I2S_RX_FIFO_TH	smac/hal/ssv6006c/ssv6006C_reg.h	2279;"	d
+GET_I2S_RX_WD_RES	smac/hal/ssv6006c/ssv6006C_reg.h	2267;"	d
+GET_I2S_R_TRX_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	2264;"	d
+GET_I2S_SCLK_GATE	smac/hal/ssv6006c/ssv6006C_reg.h	2259;"	d
+GET_I2S_SCLK_SOURCE_ENABLE	smac/hal/ssv6006c/ssv6006C_reg.h	2258;"	d
+GET_I2S_TXFO	smac/hal/ssv6006c/ssv6006C_reg.h	2278;"	d
+GET_I2S_TX_CH_ENABLE	smac/hal/ssv6006c/ssv6006C_reg.h	2266;"	d
+GET_I2S_TX_DMA	smac/hal/ssv6006c/ssv6006C_reg.h	2284;"	d
+GET_I2S_TX_ENABLE	smac/hal/ssv6006c/ssv6006C_reg.h	2257;"	d
+GET_I2S_TX_FIFO_FLUSH	smac/hal/ssv6006c/ssv6006C_reg.h	2282;"	d
+GET_I2S_TX_FIFO_TH	smac/hal/ssv6006c/ssv6006C_reg.h	2280;"	d
+GET_I2S_TX_WD_RES	smac/hal/ssv6006c/ssv6006C_reg.h	2268;"	d
+GET_I2S_WS_LENGTH	smac/hal/ssv6006c/ssv6006C_reg.h	2260;"	d
+GET_IC_TAG_31_0	include/ssv6200_reg.h	3010;"	d
+GET_IC_TAG_63_32	include/ssv6200_reg.h	3011;"	d
+GET_IDX_EXTEND	smac/hal/ssv6006c/ssv6006C_reg.h	3455;"	d
+GET_ID_DOUBLE_RLS	include/ssv6200_reg.h	2265;"	d
+GET_ID_DOUBLE_RLS_INT	include/ssv6200_reg.h	3803;"	d
+GET_ID_DOUBLE_RLS_INT	smac/hal/ssv6006c/ssv6006C_reg.h	8986;"	d
+GET_ID_DOUBLE_RLS_SD	include/ssv6200_reg.h	2334;"	d
+GET_ID_EXCEPT_FLG	include/ssv6200_reg.h	3768;"	d
+GET_ID_EXCEPT_FLG	smac/hal/ssv6006c/ssv6006C_reg.h	8951;"	d
+GET_ID_EXCEPT_FLG_CLR	include/ssv6200_reg.h	3767;"	d
+GET_ID_EXCEPT_FLG_CLR	smac/hal/ssv6006c/ssv6006C_reg.h	8950;"	d
+GET_ID_FULL	include/ssv6200_reg.h	3769;"	d
+GET_ID_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	8952;"	d
+GET_ID_IN_USE	include/ssv6200_reg.h	2712;"	d
+GET_ID_IN_USE	smac/hal/ssv6006c/ssv6006C_reg.h	3436;"	d
+GET_ID_LEN_THOLD	include/ssv6200_reg.h	3811;"	d
+GET_ID_LEN_THOLD	smac/hal/ssv6006c/ssv6006C_reg.h	8994;"	d
+GET_ID_LEN_THOLD_INT_EN	include/ssv6200_reg.h	3805;"	d
+GET_ID_LEN_THOLD_INT_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8988;"	d
+GET_ID_MNG_BUSY	include/ssv6200_reg.h	3770;"	d
+GET_ID_MNG_BUSY	smac/hal/ssv6006c/ssv6006C_reg.h	8953;"	d
+GET_ID_MNG_CLK_EN	include/ssv6200_reg.h	3066;"	d
+GET_ID_MNG_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3898;"	d
+GET_ID_MNG_CSR_CLK_EN	include/ssv6200_reg.h	3085;"	d
+GET_ID_MNG_CSR_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3917;"	d
+GET_ID_MNG_CSR_RST	include/ssv6200_reg.h	3057;"	d
+GET_ID_MNG_CSR_RST	smac/hal/ssv6006c/ssv6006C_reg.h	3889;"	d
+GET_ID_MNG_ENG_CLK_EN	include/ssv6200_reg.h	3077;"	d
+GET_ID_MNG_ENG_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3909;"	d
+GET_ID_MNG_ENG_RST	include/ssv6200_reg.h	3042;"	d
+GET_ID_MNG_ENG_RST	smac/hal/ssv6006c/ssv6006C_reg.h	3874;"	d
+GET_ID_MNG_ERR_HALT_EN	include/ssv6200_reg.h	3766;"	d
+GET_ID_MNG_ERR_HALT_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8949;"	d
+GET_ID_MNG_HALT	include/ssv6200_reg.h	3765;"	d
+GET_ID_MNG_HALT	smac/hal/ssv6006c/ssv6006C_reg.h	8948;"	d
+GET_ID_MNG_INT_1	include/ssv6200_reg.h	2254;"	d
+GET_ID_MNG_INT_1_SD	include/ssv6200_reg.h	2323;"	d
+GET_ID_MNG_INT_2	include/ssv6200_reg.h	2261;"	d
+GET_ID_MNG_INT_2_SD	include/ssv6200_reg.h	2330;"	d
+GET_ID_MNG_SW_RST	include/ssv6200_reg.h	3031;"	d
+GET_ID_MNG_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	3863;"	d
+GET_ID_PAGE_MAX_SIZE	include/ssv6200_reg.h	3822;"	d
+GET_ID_PAGE_MAX_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	9005;"	d
+GET_ID_RX_LEN_THOLD	include/ssv6200_reg.h	3810;"	d
+GET_ID_RX_LEN_THOLD	smac/hal/ssv6006c/ssv6006C_reg.h	8993;"	d
+GET_ID_TB0	include/ssv6200_reg.h	3763;"	d
+GET_ID_TB0	smac/hal/ssv6006c/ssv6006C_reg.h	8946;"	d
+GET_ID_TB1	include/ssv6200_reg.h	3764;"	d
+GET_ID_TB1	smac/hal/ssv6006c/ssv6006C_reg.h	8947;"	d
+GET_ID_TB2	include/ssv6200_reg.h	3833;"	d
+GET_ID_TB2	smac/hal/ssv6006c/ssv6006C_reg.h	9016;"	d
+GET_ID_TB3	include/ssv6200_reg.h	3834;"	d
+GET_ID_TB3	smac/hal/ssv6006c/ssv6006C_reg.h	9017;"	d
+GET_ID_THOLD_INT_EN	include/ssv6200_reg.h	3797;"	d
+GET_ID_THOLD_INT_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8980;"	d
+GET_ID_THOLD_RX	include/ssv6200_reg.h	2263;"	d
+GET_ID_THOLD_RX_INT	include/ssv6200_reg.h	3793;"	d
+GET_ID_THOLD_RX_INT	smac/hal/ssv6006c/ssv6006C_reg.h	8976;"	d
+GET_ID_THOLD_RX_SD	include/ssv6200_reg.h	2332;"	d
+GET_ID_THOLD_TX	include/ssv6200_reg.h	2264;"	d
+GET_ID_THOLD_TX_INT	include/ssv6200_reg.h	3795;"	d
+GET_ID_THOLD_TX_INT	smac/hal/ssv6006c/ssv6006C_reg.h	8978;"	d
+GET_ID_THOLD_TX_SD	include/ssv6200_reg.h	2333;"	d
+GET_ID_TX_LEN_THOLD	include/ssv6200_reg.h	3809;"	d
+GET_ID_TX_LEN_THOLD	smac/hal/ssv6006c/ssv6006C_reg.h	8992;"	d
+GET_ILLEGAL_CMD_RESP_OPTION	include/ssv6200_reg.h	1892;"	d
+GET_ILLEGAL_CMD_RESP_OPTION	smac/hal/ssv6006c/ssv6006C_reg.h	2675;"	d
+GET_ILL_ADDR_CLR	include/ssv6200_reg.h	1354;"	d
+GET_ILL_ADDR_INT	include/ssv6200_reg.h	1356;"	d
+GET_ILM160KB_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2509;"	d
+GET_INDICATOR	smac/hal/ssv6006c/ssv6006C_reg.h	2957;"	d
+GET_INFO0	include/ssv6200_reg.h	2965;"	d
+GET_INFO1	include/ssv6200_reg.h	2966;"	d
+GET_INFO10	include/ssv6200_reg.h	2975;"	d
+GET_INFO11	include/ssv6200_reg.h	2976;"	d
+GET_INFO12	include/ssv6200_reg.h	2977;"	d
+GET_INFO13	include/ssv6200_reg.h	2978;"	d
+GET_INFO14	include/ssv6200_reg.h	2979;"	d
+GET_INFO15	include/ssv6200_reg.h	2980;"	d
+GET_INFO16	include/ssv6200_reg.h	2981;"	d
+GET_INFO17	include/ssv6200_reg.h	2982;"	d
+GET_INFO18	include/ssv6200_reg.h	2983;"	d
+GET_INFO19	include/ssv6200_reg.h	2984;"	d
+GET_INFO2	include/ssv6200_reg.h	2967;"	d
+GET_INFO20	include/ssv6200_reg.h	2985;"	d
+GET_INFO21	include/ssv6200_reg.h	2986;"	d
+GET_INFO22	include/ssv6200_reg.h	2987;"	d
+GET_INFO23	include/ssv6200_reg.h	2988;"	d
+GET_INFO24	include/ssv6200_reg.h	2989;"	d
+GET_INFO25	include/ssv6200_reg.h	2990;"	d
+GET_INFO26	include/ssv6200_reg.h	2991;"	d
+GET_INFO27	include/ssv6200_reg.h	2992;"	d
+GET_INFO28	include/ssv6200_reg.h	2993;"	d
+GET_INFO29	include/ssv6200_reg.h	2994;"	d
+GET_INFO3	include/ssv6200_reg.h	2968;"	d
+GET_INFO30	include/ssv6200_reg.h	2995;"	d
+GET_INFO31	include/ssv6200_reg.h	2996;"	d
+GET_INFO32	include/ssv6200_reg.h	2997;"	d
+GET_INFO33	include/ssv6200_reg.h	2998;"	d
+GET_INFO34	include/ssv6200_reg.h	2999;"	d
+GET_INFO35	include/ssv6200_reg.h	3000;"	d
+GET_INFO36	include/ssv6200_reg.h	3001;"	d
+GET_INFO37	include/ssv6200_reg.h	3002;"	d
+GET_INFO38	include/ssv6200_reg.h	3003;"	d
+GET_INFO4	include/ssv6200_reg.h	2969;"	d
+GET_INFO5	include/ssv6200_reg.h	2970;"	d
+GET_INFO6	include/ssv6200_reg.h	2971;"	d
+GET_INFO7	include/ssv6200_reg.h	2972;"	d
+GET_INFO8	include/ssv6200_reg.h	2973;"	d
+GET_INFO9	include/ssv6200_reg.h	2974;"	d
+GET_INFO_DEF_RATE	include/ssv6200_reg.h	3005;"	d
+GET_INFO_IDX_TBL_ADDR	include/ssv6200_reg.h	3008;"	d
+GET_INFO_LEN_TBL_ADDR	include/ssv6200_reg.h	3009;"	d
+GET_INFO_MASK	include/ssv6200_reg.h	3004;"	d
+GET_INFO_MRX_OFFSET	include/ssv6200_reg.h	3006;"	d
+GET_INS_BUF_CLR	smac/hal/ssv6006c/ssv6006C_reg.h	2986;"	d
+GET_INS_END_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	2985;"	d
+GET_INS_START_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	2984;"	d
+GET_INTR_GPI00_CFG	include/ssv6200_reg.h	2277;"	d
+GET_INTR_GPI01_CFG	include/ssv6200_reg.h	2278;"	d
+GET_INTR_PERI_RAW	include/ssv6200_reg.h	2276;"	d
+GET_INTR_RX	include/ssv6200_reg.h	1967;"	d
+GET_INT_ALC_TIMEOUT	smac/hal/ssv6006c/ssv6006C_reg.h	3094;"	d
+GET_INT_ALL_ID_LEN_THOLD	smac/hal/ssv6006c/ssv6006C_reg.h	3102;"	d
+GET_INT_BROWNOUT_LOWBATTERY	smac/hal/ssv6006c/ssv6006C_reg.h	3170;"	d
+GET_INT_CO_DMA	smac/hal/ssv6006c/ssv6006C_reg.h	3127;"	d
+GET_INT_CPU	smac/hal/ssv6006c/ssv6006C_reg.h	3116;"	d
+GET_INT_CPU_ALT	smac/hal/ssv6006c/ssv6006C_reg.h	3115;"	d
+GET_INT_CTL_CLK_EN	include/ssv6200_reg.h	1309;"	d
+GET_INT_CTL_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2388;"	d
+GET_INT_CTL_SW_RST	include/ssv6200_reg.h	1275;"	d
+GET_INT_CTL_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	2355;"	d
+GET_INT_DMAC_INT_COMBINED	smac/hal/ssv6006c/ssv6006C_reg.h	3113;"	d
+GET_INT_EDCA0_LOWTHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	3105;"	d
+GET_INT_EDCA1_LOWTHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	3106;"	d
+GET_INT_EDCA2_LOWTHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	3107;"	d
+GET_INT_EDCA3_LOWTHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	3108;"	d
+GET_INT_FBUSDMAC_INT_COMBINED	smac/hal/ssv6006c/ssv6006C_reg.h	3112;"	d
+GET_INT_FLASH_DMA_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	3111;"	d
+GET_INT_GPI_MODE_00	smac/hal/ssv6006c/ssv6006C_reg.h	3066;"	d
+GET_INT_GPI_MODE_01	smac/hal/ssv6006c/ssv6006C_reg.h	3067;"	d
+GET_INT_GPI_MODE_02	smac/hal/ssv6006c/ssv6006C_reg.h	3068;"	d
+GET_INT_GPI_MODE_03	smac/hal/ssv6006c/ssv6006C_reg.h	3069;"	d
+GET_INT_GPI_MODE_04	smac/hal/ssv6006c/ssv6006C_reg.h	3070;"	d
+GET_INT_GPI_MODE_05	smac/hal/ssv6006c/ssv6006C_reg.h	3071;"	d
+GET_INT_GPI_MODE_06	smac/hal/ssv6006c/ssv6006C_reg.h	3072;"	d
+GET_INT_GPI_MODE_07	smac/hal/ssv6006c/ssv6006C_reg.h	3073;"	d
+GET_INT_GPI_MODE_08	smac/hal/ssv6006c/ssv6006C_reg.h	3074;"	d
+GET_INT_GPI_MODE_09	smac/hal/ssv6006c/ssv6006C_reg.h	3075;"	d
+GET_INT_GPI_MODE_10	smac/hal/ssv6006c/ssv6006C_reg.h	3076;"	d
+GET_INT_GPI_MODE_11	smac/hal/ssv6006c/ssv6006C_reg.h	3077;"	d
+GET_INT_GPI_MODE_12	smac/hal/ssv6006c/ssv6006C_reg.h	3078;"	d
+GET_INT_GPI_MODE_13	smac/hal/ssv6006c/ssv6006C_reg.h	3079;"	d
+GET_INT_GPI_MODE_14	smac/hal/ssv6006c/ssv6006C_reg.h	3080;"	d
+GET_INT_GPI_MODE_15	smac/hal/ssv6006c/ssv6006C_reg.h	3081;"	d
+GET_INT_GPI_MODE_16	smac/hal/ssv6006c/ssv6006C_reg.h	3082;"	d
+GET_INT_GPI_MODE_17	smac/hal/ssv6006c/ssv6006C_reg.h	3083;"	d
+GET_INT_GPI_MODE_18	smac/hal/ssv6006c/ssv6006C_reg.h	3084;"	d
+GET_INT_GPI_MODE_19	smac/hal/ssv6006c/ssv6006C_reg.h	3085;"	d
+GET_INT_GPI_MODE_20	smac/hal/ssv6006c/ssv6006C_reg.h	3086;"	d
+GET_INT_GPI_MODE_21	smac/hal/ssv6006c/ssv6006C_reg.h	3087;"	d
+GET_INT_GPI_MODE_22	smac/hal/ssv6006c/ssv6006C_reg.h	3088;"	d
+GET_INT_GPI_SUB_00	smac/hal/ssv6006c/ssv6006C_reg.h	3043;"	d
+GET_INT_GPI_SUB_01	smac/hal/ssv6006c/ssv6006C_reg.h	3044;"	d
+GET_INT_GPI_SUB_02	smac/hal/ssv6006c/ssv6006C_reg.h	3045;"	d
+GET_INT_GPI_SUB_03	smac/hal/ssv6006c/ssv6006C_reg.h	3046;"	d
+GET_INT_GPI_SUB_04	smac/hal/ssv6006c/ssv6006C_reg.h	3047;"	d
+GET_INT_GPI_SUB_05	smac/hal/ssv6006c/ssv6006C_reg.h	3048;"	d
+GET_INT_GPI_SUB_06	smac/hal/ssv6006c/ssv6006C_reg.h	3049;"	d
+GET_INT_GPI_SUB_07	smac/hal/ssv6006c/ssv6006C_reg.h	3050;"	d
+GET_INT_GPI_SUB_08	smac/hal/ssv6006c/ssv6006C_reg.h	3051;"	d
+GET_INT_GPI_SUB_09	smac/hal/ssv6006c/ssv6006C_reg.h	3052;"	d
+GET_INT_GPI_SUB_10	smac/hal/ssv6006c/ssv6006C_reg.h	3053;"	d
+GET_INT_GPI_SUB_11	smac/hal/ssv6006c/ssv6006C_reg.h	3054;"	d
+GET_INT_GPI_SUB_12	smac/hal/ssv6006c/ssv6006C_reg.h	3055;"	d
+GET_INT_GPI_SUB_13	smac/hal/ssv6006c/ssv6006C_reg.h	3056;"	d
+GET_INT_GPI_SUB_14	smac/hal/ssv6006c/ssv6006C_reg.h	3057;"	d
+GET_INT_GPI_SUB_15	smac/hal/ssv6006c/ssv6006C_reg.h	3058;"	d
+GET_INT_GPI_SUB_16	smac/hal/ssv6006c/ssv6006C_reg.h	3059;"	d
+GET_INT_GPI_SUB_17	smac/hal/ssv6006c/ssv6006C_reg.h	3060;"	d
+GET_INT_GPI_SUB_18	smac/hal/ssv6006c/ssv6006C_reg.h	3061;"	d
+GET_INT_GPI_SUB_19	smac/hal/ssv6006c/ssv6006C_reg.h	3062;"	d
+GET_INT_GPI_SUB_20	smac/hal/ssv6006c/ssv6006C_reg.h	3063;"	d
+GET_INT_GPI_SUB_21	smac/hal/ssv6006c/ssv6006C_reg.h	3064;"	d
+GET_INT_GPI_SUB_22	smac/hal/ssv6006c/ssv6006C_reg.h	3065;"	d
+GET_INT_HCI	smac/hal/ssv6006c/ssv6006C_reg.h	3126;"	d
+GET_INT_I2CMST	smac/hal/ssv6006c/ssv6006C_reg.h	3125;"	d
+GET_INT_I2S	smac/hal/ssv6006c/ssv6006C_reg.h	3114;"	d
+GET_INT_IDCODE	include/ssv6200_reg.h	2159;"	d
+GET_INT_IDCODE	smac/hal/ssv6006c/ssv6006C_reg.h	2870;"	d
+GET_INT_ID_DOUBLE_RLS	smac/hal/ssv6006c/ssv6006C_reg.h	3099;"	d
+GET_INT_ID_THOLD_RX	smac/hal/ssv6006c/ssv6006C_reg.h	3097;"	d
+GET_INT_ID_THOLD_TX	smac/hal/ssv6006c/ssv6006C_reg.h	3098;"	d
+GET_INT_IPC_RAW	smac/hal/ssv6006c/ssv6006C_reg.h	3090;"	d
+GET_INT_MB_LOWTHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	3104;"	d
+GET_INT_MODE	include/ssv6200_reg.h	2209;"	d
+GET_INT_MS_TIMER_0	smac/hal/ssv6006c/ssv6006C_reg.h	3121;"	d
+GET_INT_MS_TIMER_1	smac/hal/ssv6006c/ssv6006C_reg.h	3122;"	d
+GET_INT_MS_TIMER_2	smac/hal/ssv6006c/ssv6006C_reg.h	3123;"	d
+GET_INT_MS_TIMER_3	smac/hal/ssv6006c/ssv6006C_reg.h	3124;"	d
+GET_INT_PERI_MASK	include/ssv6200_reg.h	2244;"	d
+GET_INT_PERI_MASK_SD	include/ssv6200_reg.h	2313;"	d
+GET_INT_REQ_LOCK	smac/hal/ssv6006c/ssv6006C_reg.h	3095;"	d
+GET_INT_RX_ID_LEN_THOLD	smac/hal/ssv6006c/ssv6006C_reg.h	3100;"	d
+GET_INT_SDIO_WAKE	smac/hal/ssv6006c/ssv6006C_reg.h	3109;"	d
+GET_INT_SPI_M_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	3110;"	d
+GET_INT_THROUGH_PIN	include/ssv6200_reg.h	1934;"	d
+GET_INT_THROUGH_PIN	smac/hal/ssv6006c/ssv6006C_reg.h	2685;"	d
+GET_INT_TRASH_CAN	smac/hal/ssv6006c/ssv6006C_reg.h	3103;"	d
+GET_INT_TX_ID_LEN_THOLD	smac/hal/ssv6006c/ssv6006C_reg.h	3101;"	d
+GET_INT_TX_LIMIT	smac/hal/ssv6006c/ssv6006C_reg.h	3096;"	d
+GET_INT_UART_DATA_RX_TOUT	smac/hal/ssv6006c/ssv6006C_reg.h	3093;"	d
+GET_INT_UART_DBG_RX_TOUT	smac/hal/ssv6006c/ssv6006C_reg.h	3092;"	d
+GET_INT_US_TIMER_0	smac/hal/ssv6006c/ssv6006C_reg.h	3117;"	d
+GET_INT_US_TIMER_1	smac/hal/ssv6006c/ssv6006C_reg.h	3118;"	d
+GET_INT_US_TIMER_2	smac/hal/ssv6006c/ssv6006C_reg.h	3119;"	d
+GET_INT_US_TIMER_3	smac/hal/ssv6006c/ssv6006C_reg.h	3120;"	d
+GET_INT_WIFI_PHY	smac/hal/ssv6006c/ssv6006C_reg.h	3091;"	d
+GET_INV_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	3350;"	d
+GET_IN_FIFO_FLUSH_ID	smac/hal/ssv6006c/ssv6006C_reg.h	8928;"	d
+GET_IN_FIFO_FLUSH_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	8929;"	d
+GET_IN_FIFO_FLUSH_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	8930;"	d
+GET_IO_DS	smac/hal/ssv6006c/ssv6006C_reg.h	2617;"	d
+GET_IO_PDE	smac/hal/ssv6006c/ssv6006C_reg.h	2616;"	d
+GET_IO_PI	smac/hal/ssv6006c/ssv6006C_reg.h	2612;"	d
+GET_IO_PIE	smac/hal/ssv6006c/ssv6006C_reg.h	2613;"	d
+GET_IO_PO	smac/hal/ssv6006c/ssv6006C_reg.h	2611;"	d
+GET_IO_POEN	smac/hal/ssv6006c/ssv6006C_reg.h	2614;"	d
+GET_IO_PORT_REG	include/ssv6200_reg.h	1869;"	d
+GET_IO_PORT_REG	smac/hal/ssv6006c/ssv6006C_reg.h	2652;"	d
+GET_IO_PUE	smac/hal/ssv6006c/ssv6006C_reg.h	2615;"	d
+GET_IO_REG_PORT_REG	include/ssv6200_reg.h	1946;"	d
+GET_IQCAL_RF_PGAG	include/ssv6200_reg.h	4339;"	d
+GET_IQCAL_RF_RFG	include/ssv6200_reg.h	4340;"	d
+GET_IQCAL_RF_RX_AGC	include/ssv6200_reg.h	4338;"	d
+GET_IQCAL_RF_TX_DAC_EN	include/ssv6200_reg.h	4337;"	d
+GET_IQCAL_RF_TX_EN	include/ssv6200_reg.h	4335;"	d
+GET_IQCAL_RF_TX_PA_EN	include/ssv6200_reg.h	4336;"	d
+GET_IQ_LOG_EN	include/ssv6200_reg.h	3749;"	d
+GET_IQ_LOG_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8933;"	d
+GET_IQ_LOG_LEN	include/ssv6200_reg.h	3754;"	d
+GET_IQ_LOG_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	8936;"	d
+GET_IQ_LOG_STOP_MODE	include/ssv6200_reg.h	3750;"	d
+GET_IQ_LOG_STOP_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	8934;"	d
+GET_IQ_LOG_ST_ADR	smac/hal/ssv6006c/ssv6006C_reg.h	8937;"	d
+GET_IQ_LOG_TAIL_ADR	include/ssv6200_reg.h	3755;"	d
+GET_IQ_LOG_TAIL_ADR	smac/hal/ssv6006c/ssv6006C_reg.h	8938;"	d
+GET_IQ_LOG_TIMER	include/ssv6200_reg.h	3753;"	d
+GET_IQ_LOG_TIMER	smac/hal/ssv6006c/ssv6006C_reg.h	8935;"	d
+GET_IQ_SRAM_SEL_0	include/ssv6200_reg.h	1332;"	d
+GET_IQ_SRAM_SEL_1	include/ssv6200_reg.h	1333;"	d
+GET_IQ_SRAM_SEL_2	include/ssv6200_reg.h	1334;"	d
+GET_IRQ_BEACON	include/ssv6200_reg.h	2214;"	d
+GET_IRQ_BEACON_DONE	include/ssv6200_reg.h	2213;"	d
+GET_IRQ_BEACON_DONE_SD	include/ssv6200_reg.h	2285;"	d
+GET_IRQ_BEACON_DTIM	include/ssv6200_reg.h	2221;"	d
+GET_IRQ_BEACON_DTIM_SD	include/ssv6200_reg.h	2293;"	d
+GET_IRQ_BEACON_SD	include/ssv6200_reg.h	2286;"	d
+GET_IRQ_CO_DMA	include/ssv6200_reg.h	2239;"	d
+GET_IRQ_CO_DMA_SD	include/ssv6200_reg.h	2311;"	d
+GET_IRQ_DAT_UART_RX	include/ssv6200_reg.h	2271;"	d
+GET_IRQ_DAT_UART_RX_SD	include/ssv6200_reg.h	2340;"	d
+GET_IRQ_DAT_UART_TX	include/ssv6200_reg.h	2270;"	d
+GET_IRQ_DAT_UART_TX_SD	include/ssv6200_reg.h	2339;"	d
+GET_IRQ_DMA0	include/ssv6200_reg.h	2238;"	d
+GET_IRQ_DMA0_SD	include/ssv6200_reg.h	2310;"	d
+GET_IRQ_EDCA0_LOWTHOLD_INT	include/ssv6200_reg.h	2222;"	d
+GET_IRQ_EDCA0_LOWTHOLD_INT_SD	include/ssv6200_reg.h	2294;"	d
+GET_IRQ_EDCA0_TX_DONE	include/ssv6200_reg.h	2216;"	d
+GET_IRQ_EDCA0_TX_DONE_SD	include/ssv6200_reg.h	2288;"	d
+GET_IRQ_EDCA1_LOWTHOLD_INT	include/ssv6200_reg.h	2223;"	d
+GET_IRQ_EDCA1_LOWTHOLD_INT_SD	include/ssv6200_reg.h	2295;"	d
+GET_IRQ_EDCA1_TX_DONE	include/ssv6200_reg.h	2217;"	d
+GET_IRQ_EDCA1_TX_DONE_SD	include/ssv6200_reg.h	2289;"	d
+GET_IRQ_EDCA2_LOWTHOLD_INT	include/ssv6200_reg.h	2224;"	d
+GET_IRQ_EDCA2_LOWTHOLD_INT_SD	include/ssv6200_reg.h	2296;"	d
+GET_IRQ_EDCA2_TX_DONE	include/ssv6200_reg.h	2218;"	d
+GET_IRQ_EDCA2_TX_DONE_SD	include/ssv6200_reg.h	2290;"	d
+GET_IRQ_EDCA3_LOWTHOLD_INT	include/ssv6200_reg.h	2225;"	d
+GET_IRQ_EDCA3_LOWTHOLD_INT_SD	include/ssv6200_reg.h	2297;"	d
+GET_IRQ_EDCA3_TX_DONE	include/ssv6200_reg.h	2219;"	d
+GET_IRQ_EDCA3_TX_DONE_SD	include/ssv6200_reg.h	2291;"	d
+GET_IRQ_EDCA4_TX_DONE	include/ssv6200_reg.h	2220;"	d
+GET_IRQ_EDCA4_TX_DONE_SD	include/ssv6200_reg.h	2292;"	d
+GET_IRQ_FENCE_HIT_INT	include/ssv6200_reg.h	2226;"	d
+GET_IRQ_FENCE_HIT_INT_SD	include/ssv6200_reg.h	2298;"	d
+GET_IRQ_ILL_ADDR_INT	include/ssv6200_reg.h	2227;"	d
+GET_IRQ_ILL_ADDR_INT_SD	include/ssv6200_reg.h	2299;"	d
+GET_IRQ_MBOX	include/ssv6200_reg.h	2228;"	d
+GET_IRQ_MBOX_SD	include/ssv6200_reg.h	2300;"	d
+GET_IRQ_MS_TIMER0	include/ssv6200_reg.h	2233;"	d
+GET_IRQ_MS_TIMER0_SD	include/ssv6200_reg.h	2305;"	d
+GET_IRQ_MS_TIMER1	include/ssv6200_reg.h	2234;"	d
+GET_IRQ_MS_TIMER1_SD	include/ssv6200_reg.h	2306;"	d
+GET_IRQ_MS_TIMER2	include/ssv6200_reg.h	2235;"	d
+GET_IRQ_MS_TIMER2_SD	include/ssv6200_reg.h	2307;"	d
+GET_IRQ_MS_TIMER3	include/ssv6200_reg.h	2236;"	d
+GET_IRQ_MS_TIMER3_SD	include/ssv6200_reg.h	2308;"	d
+GET_IRQ_PERI_GROUP	include/ssv6200_reg.h	2240;"	d
+GET_IRQ_PERI_GROUP_SD	include/ssv6200_reg.h	2312;"	d
+GET_IRQ_PHY_0	include/ssv6200_reg.h	2210;"	d
+GET_IRQ_PHY_0_SD	include/ssv6200_reg.h	2282;"	d
+GET_IRQ_PHY_1	include/ssv6200_reg.h	2211;"	d
+GET_IRQ_PHY_1_SD	include/ssv6200_reg.h	2283;"	d
+GET_IRQ_PRE_BEACON	include/ssv6200_reg.h	2215;"	d
+GET_IRQ_PRE_BEACON_SD	include/ssv6200_reg.h	2287;"	d
+GET_IRQ_RAW	include/ssv6200_reg.h	2242;"	d
+GET_IRQ_SDIO	include/ssv6200_reg.h	2212;"	d
+GET_IRQ_SDIO_SD	include/ssv6200_reg.h	2284;"	d
+GET_IRQ_SPI_IPC	include/ssv6200_reg.h	2249;"	d
+GET_IRQ_SPI_IPC_SD	include/ssv6200_reg.h	2318;"	d
+GET_IRQ_TX_LIMIT_INT	include/ssv6200_reg.h	2237;"	d
+GET_IRQ_TX_LIMIT_INT_SD	include/ssv6200_reg.h	2309;"	d
+GET_IRQ_UART0_RX	include/ssv6200_reg.h	2247;"	d
+GET_IRQ_UART0_RX_SD	include/ssv6200_reg.h	2316;"	d
+GET_IRQ_UART0_TX	include/ssv6200_reg.h	2246;"	d
+GET_IRQ_UART0_TX_SD	include/ssv6200_reg.h	2315;"	d
+GET_IRQ_US_TIMER0	include/ssv6200_reg.h	2229;"	d
+GET_IRQ_US_TIMER0_SD	include/ssv6200_reg.h	2301;"	d
+GET_IRQ_US_TIMER1	include/ssv6200_reg.h	2230;"	d
+GET_IRQ_US_TIMER1_SD	include/ssv6200_reg.h	2302;"	d
+GET_IRQ_US_TIMER2	include/ssv6200_reg.h	2231;"	d
+GET_IRQ_US_TIMER2_SD	include/ssv6200_reg.h	2303;"	d
+GET_IRQ_US_TIMER3	include/ssv6200_reg.h	2232;"	d
+GET_IRQ_US_TIMER3_SD	include/ssv6200_reg.h	2304;"	d
+GET_JTAG_TCK_ID	include/ssv6200_reg.h	1724;"	d
+GET_JTAG_TDI_ID	include/ssv6200_reg.h	1729;"	d
+GET_JTAG_TDO_ID	include/ssv6200_reg.h	1738;"	d
+GET_JTAG_TMS_ID	include/ssv6200_reg.h	1718;"	d
+GET_JUDGE_CNT	include/ssv6200_reg.h	2072;"	d
+GET_JUDGE_CNT_CLR	include/ssv6200_reg.h	2075;"	d
+GET_KEY_DIN_MSB	include/ssv6200_reg.h	2607;"	d
+GET_L4_LEN	include/ssv6200_reg.h	2535;"	d
+GET_L4_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	3273;"	d
+GET_L4_PROTOL	include/ssv6200_reg.h	2536;"	d
+GET_L4_PROTOL	smac/hal/ssv6006c/ssv6006C_reg.h	3274;"	d
+GET_LCK_BIN_RDY	include/ssv6200_reg.h	4774;"	d
+GET_LEN	include/ssv6200_reg.h	2548;"	d
+GET_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	3286;"	d
+GET_LEN_FLT	include/ssv6200_reg.h	2741;"	d
+GET_LEN_FLT	smac/hal/ssv6006c/ssv6006C_reg.h	3461;"	d
+GET_LOOP_BACK	include/ssv6200_reg.h	2139;"	d
+GET_LOOP_BACK	smac/hal/ssv6006c/ssv6006C_reg.h	2849;"	d
+GET_LOWBATTERY_SAMPLE_MIN_COUNT	smac/hal/ssv6006c/ssv6006C_reg.h	3171;"	d
+GET_LOW_ACTIVE	include/ssv6200_reg.h	2562;"	d
+GET_LOW_SPEED_CARD	include/ssv6200_reg.h	2005;"	d
+GET_LOW_SPEED_CARD	smac/hal/ssv6006c/ssv6006C_reg.h	2719;"	d
+GET_LOW_SPEED_CARD_4BIT	include/ssv6200_reg.h	2006;"	d
+GET_LOW_SPEED_CARD_4BIT	smac/hal/ssv6006c/ssv6006C_reg.h	2720;"	d
+GET_LUT_SEL_V2	smac/hal/ssv6006c/ssv6006C_reg.h	3928;"	d
+GET_MAC_ALL_RESET	include/ssv6200_reg.h	1944;"	d
+GET_MAC_ALL_RESET	smac/hal/ssv6006c/ssv6006C_reg.h	2702;"	d
+GET_MAC_CLK_80M	smac/hal/ssv6006c/ssv6006C_reg.h	3617;"	d
+GET_MAC_CLK_EN	include/ssv6200_reg.h	1301;"	d
+GET_MAC_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2380;"	d
+GET_MAC_SW_RST	include/ssv6200_reg.h	1267;"	d
+GET_MAC_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	2347;"	d
+GET_MAC_TX_PEER_PS_LOCK_AUTOLOCK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3567;"	d
+GET_MAC_TX_PEER_PS_LOCK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3566;"	d
+GET_MAC_TX_PS_LOCK	smac/hal/ssv6006c/ssv6006C_reg.h	3568;"	d
+GET_MAC_TX_PS_LOCK_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	3569;"	d
+GET_MAC_TX_PS_UNLOCK	smac/hal/ssv6006c/ssv6006C_reg.h	3565;"	d
+GET_MANUAL_ALLOC_ID	smac/hal/ssv6006c/ssv6006C_reg.h	3213;"	d
+GET_MANUAL_DS	smac/hal/ssv6006c/ssv6006C_reg.h	2610;"	d
+GET_MANUAL_HCI_ALLOC_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3211;"	d
+GET_MANUAL_HCI_ALLOC_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	3212;"	d
+GET_MANUAL_IO	smac/hal/ssv6006c/ssv6006C_reg.h	2607;"	d
+GET_MANUAL_MODE_BUSY	smac/hal/ssv6006c/ssv6006C_reg.h	2962;"	d
+GET_MANUAL_PD	smac/hal/ssv6006c/ssv6006C_reg.h	2609;"	d
+GET_MANUAL_PU	smac/hal/ssv6006c/ssv6006C_reg.h	2608;"	d
+GET_MANUAL_R_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	2953;"	d
+GET_MANUAL_R_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	2967;"	d
+GET_MANUAL_T_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	2952;"	d
+GET_MANUAL_T_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	2966;"	d
+GET_MASK_ABNORMAL_CRC	smac/hal/ssv6006c/ssv6006C_reg.h	3448;"	d
+GET_MASK_RX_INT	include/ssv6200_reg.h	1870;"	d
+GET_MASK_RX_INT	smac/hal/ssv6006c/ssv6006C_reg.h	2653;"	d
+GET_MASK_SOC_SYSTEM_INT	include/ssv6200_reg.h	1872;"	d
+GET_MASK_SOC_SYSTEM_INT	smac/hal/ssv6006c/ssv6006C_reg.h	2655;"	d
+GET_MASK_TOP	include/ssv6200_reg.h	2208;"	d
+GET_MASK_TX_INT	include/ssv6200_reg.h	1871;"	d
+GET_MASK_TYPHOST_INT_MAP	smac/hal/ssv6006c/ssv6006C_reg.h	3026;"	d
+GET_MASK_TYPHOST_INT_MAP_02	smac/hal/ssv6006c/ssv6006C_reg.h	3017;"	d
+GET_MASK_TYPHOST_INT_MAP_15	smac/hal/ssv6006c/ssv6006C_reg.h	3020;"	d
+GET_MASK_TYPHOST_INT_MAP_31	smac/hal/ssv6006c/ssv6006C_reg.h	3023;"	d
+GET_MASK_TYPMCU_INT_MAP	smac/hal/ssv6006c/ssv6006C_reg.h	3039;"	d
+GET_MASK_TYPMCU_INT_MAP_02	smac/hal/ssv6006c/ssv6006C_reg.h	3030;"	d
+GET_MASK_TYPMCU_INT_MAP_15	smac/hal/ssv6006c/ssv6006C_reg.h	3033;"	d
+GET_MASK_TYPMCU_INT_MAP_31	smac/hal/ssv6006c/ssv6006C_reg.h	3036;"	d
+GET_MAX_ALL_ALC_ID_CNT	include/ssv6200_reg.h	3852;"	d
+GET_MAX_ALL_ALC_ID_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	9037;"	d
+GET_MAX_ALL_ID_ALC_LEN	include/ssv6200_reg.h	3855;"	d
+GET_MAX_ALL_ID_ALC_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	9040;"	d
+GET_MAX_RX_ALC_ID_CNT	include/ssv6200_reg.h	3854;"	d
+GET_MAX_RX_ALC_ID_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	9039;"	d
+GET_MAX_RX_ID_ALC_LEN	include/ssv6200_reg.h	3857;"	d
+GET_MAX_RX_ID_ALC_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	9042;"	d
+GET_MAX_TX_ALC_ID_CNT	include/ssv6200_reg.h	3853;"	d
+GET_MAX_TX_ALC_ID_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	9038;"	d
+GET_MAX_TX_ID_ALC_LEN	include/ssv6200_reg.h	3856;"	d
+GET_MAX_TX_ID_ALC_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	9041;"	d
+GET_MBOX_CLK_EN	include/ssv6200_reg.h	3067;"	d
+GET_MBOX_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3899;"	d
+GET_MBOX_CSR_CLK_EN	include/ssv6200_reg.h	3086;"	d
+GET_MBOX_CSR_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3918;"	d
+GET_MBOX_CSR_RST	include/ssv6200_reg.h	3058;"	d
+GET_MBOX_CSR_RST	smac/hal/ssv6006c/ssv6006C_reg.h	3890;"	d
+GET_MBOX_ENG_CLK_EN	include/ssv6200_reg.h	3078;"	d
+GET_MBOX_ENG_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3910;"	d
+GET_MBOX_ENG_RST	include/ssv6200_reg.h	3043;"	d
+GET_MBOX_ENG_RST	smac/hal/ssv6006c/ssv6006C_reg.h	3875;"	d
+GET_MBOX_INT_1	include/ssv6200_reg.h	2255;"	d
+GET_MBOX_INT_1_SD	include/ssv6200_reg.h	2324;"	d
+GET_MBOX_INT_2	include/ssv6200_reg.h	2256;"	d
+GET_MBOX_INT_2_SD	include/ssv6200_reg.h	2325;"	d
+GET_MBOX_INT_3	include/ssv6200_reg.h	2257;"	d
+GET_MBOX_INT_3_SD	include/ssv6200_reg.h	2326;"	d
+GET_MBOX_SW_RST	include/ssv6200_reg.h	3032;"	d
+GET_MBOX_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	3864;"	d
+GET_MBRUN	include/ssv6200_reg.h	1337;"	d
+GET_MB_DBG_CFG_ADDR	include/ssv6200_reg.h	3613;"	d
+GET_MB_DBG_CFG_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	8822;"	d
+GET_MB_DBG_CLR	include/ssv6200_reg.h	3607;"	d
+GET_MB_DBG_CLR	smac/hal/ssv6006c/ssv6006C_reg.h	8816;"	d
+GET_MB_DBG_COUNTER_EN	include/ssv6200_reg.h	3609;"	d
+GET_MB_DBG_COUNTER_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8818;"	d
+GET_MB_DBG_EN	include/ssv6200_reg.h	3610;"	d
+GET_MB_DBG_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8819;"	d
+GET_MB_DBG_LENGTH	include/ssv6200_reg.h	3612;"	d
+GET_MB_DBG_LENGTH	smac/hal/ssv6006c/ssv6006C_reg.h	8821;"	d
+GET_MB_DBG_RECORD_CNT	include/ssv6200_reg.h	3611;"	d
+GET_MB_DBG_RECORD_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8820;"	d
+GET_MB_DBG_TIME_STEP	include/ssv6200_reg.h	3605;"	d
+GET_MB_DBG_TIME_STEP	smac/hal/ssv6006c/ssv6006C_reg.h	8814;"	d
+GET_MB_ERR_AUTO_HALT_EN	include/ssv6200_reg.h	3602;"	d
+GET_MB_ERR_AUTO_HALT_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8797;"	d
+GET_MB_EXCEPT_CASE	include/ssv6200_reg.h	3604;"	d
+GET_MB_EXCEPT_CASE	smac/hal/ssv6006c/ssv6006C_reg.h	8813;"	d
+GET_MB_EXCEPT_CLR	include/ssv6200_reg.h	3603;"	d
+GET_MB_EXCEPT_CLR	smac/hal/ssv6006c/ssv6006C_reg.h	8798;"	d
+GET_MB_IDTBL_127_96	include/ssv6200_reg.h	4870;"	d
+GET_MB_IDTBL_31_0	include/ssv6200_reg.h	4867;"	d
+GET_MB_IDTBL_63_32	include/ssv6200_reg.h	4868;"	d
+GET_MB_IDTBL_95_64	include/ssv6200_reg.h	4869;"	d
+GET_MB_LOW_THOLD_EN	include/ssv6200_reg.h	3711;"	d
+GET_MB_LOW_THOLD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8907;"	d
+GET_MB_OUT_QUEUE_EN	include/ssv6200_reg.h	3646;"	d
+GET_MB_OUT_QUEUE_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8855;"	d
+GET_MB_REQ_DUR	include/ssv6200_reg.h	2816;"	d
+GET_MCH_SW_RST_N	include/ssv6200_reg.h	4804;"	d
+GET_MCS	include/ssv6200_reg.h	2554;"	d
+GET_MCS	smac/hal/ssv6006c/ssv6006C_reg.h	3292;"	d
+GET_MCU_ALC_READY	include/ssv6200_reg.h	3778;"	d
+GET_MCU_ALC_READY	smac/hal/ssv6006c/ssv6006C_reg.h	8961;"	d
+GET_MCU_CLK_EN	include/ssv6200_reg.h	1302;"	d
+GET_MCU_DBG_DATA	include/ssv6200_reg.h	1326;"	d
+GET_MCU_DBG_SEL	include/ssv6200_reg.h	1323;"	d
+GET_MCU_ENABLE	include/ssv6200_reg.h	1266;"	d
+GET_MCU_ENABLE	smac/hal/ssv6006c/ssv6006C_reg.h	2346;"	d
+GET_MCU_PKTID	include/ssv6200_reg.h	3758;"	d
+GET_MCU_PKTID	smac/hal/ssv6006c/ssv6006C_reg.h	8941;"	d
+GET_MCU_STOP_ANYTIME	include/ssv6200_reg.h	1325;"	d
+GET_MCU_STOP_NOGRANT	include/ssv6200_reg.h	1324;"	d
+GET_MCU_SW_RST	include/ssv6200_reg.h	1268;"	d
+GET_MCU_TO_SDIO_INFO	smac/hal/ssv6006c/ssv6006C_reg.h	2704;"	d
+GET_MCU_TO_SDIO_INFO_MASK	include/ssv6200_reg.h	1933;"	d
+GET_MCU_TO_SDIO_INFO_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	2684;"	d
+GET_MCU_WDOG_ENA	include/ssv6200_reg.h	1430;"	d
+GET_MCU_WDOG_ENA	smac/hal/ssv6006c/ssv6006C_reg.h	2567;"	d
+GET_MCU_WDT_INT_CNT_OFS	smac/hal/ssv6006c/ssv6006C_reg.h	2565;"	d
+GET_MCU_WDT_STATUS	include/ssv6200_reg.h	1429;"	d
+GET_MCU_WDT_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	2566;"	d
+GET_MCU_WDT_TIME_CNT	include/ssv6200_reg.h	1428;"	d
+GET_MCU_WDT_TIME_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	2564;"	d
+GET_MDM_STS_IE	include/ssv6200_reg.h	2118;"	d
+GET_MDM_STS_IE	smac/hal/ssv6006c/ssv6006C_reg.h	2828;"	d
+GET_MEM_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	2959;"	d
+GET_MIB_AMPDU	include/ssv6200_reg.h	2740;"	d
+GET_MIB_AMPDU	smac/hal/ssv6006c/ssv6006C_reg.h	3460;"	d
+GET_MIB_CLK_EN	include/ssv6200_reg.h	3070;"	d
+GET_MIB_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3902;"	d
+GET_MIB_DELIMITER	include/ssv6200_reg.h	2742;"	d
+GET_MIB_DELIMITER	smac/hal/ssv6006c/ssv6006C_reg.h	3462;"	d
+GET_MIB_LEN_FAIL	include/ssv6200_reg.h	2710;"	d
+GET_MIB_LEN_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	3434;"	d
+GET_MIC_CLK_EN	include/ssv6200_reg.h	3069;"	d
+GET_MIC_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3901;"	d
+GET_MIC_ENG_CLK_EN	include/ssv6200_reg.h	3080;"	d
+GET_MIC_ENG_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3912;"	d
+GET_MIC_ENG_RST	include/ssv6200_reg.h	3045;"	d
+GET_MIC_ENG_RST	smac/hal/ssv6006c/ssv6006C_reg.h	3877;"	d
+GET_MIC_SW_RST	include/ssv6200_reg.h	3034;"	d
+GET_MIC_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	3866;"	d
+GET_MISC_PKT_CLS_MIB_EN	include/ssv6200_reg.h	3145;"	d
+GET_MISC_PKT_CLS_MIB_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3993;"	d
+GET_MISC_PKT_CLS_ONGOING	include/ssv6200_reg.h	3146;"	d
+GET_MISC_PKT_CLS_ONGOING	smac/hal/ssv6006c/ssv6006C_reg.h	3994;"	d
+GET_MMU_ALC_ERR	include/ssv6200_reg.h	2252;"	d
+GET_MMU_ALC_ERR_SD	include/ssv6200_reg.h	2321;"	d
+GET_MMU_CLK_EN	include/ssv6200_reg.h	3065;"	d
+GET_MMU_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3897;"	d
+GET_MMU_RLS_ERR	include/ssv6200_reg.h	2253;"	d
+GET_MMU_RLS_ERR_SD	include/ssv6200_reg.h	2322;"	d
+GET_MMU_SHARE_MCU	include/ssv6200_reg.h	4808;"	d
+GET_MMU_SW_RST	include/ssv6200_reg.h	3030;"	d
+GET_MMU_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	3862;"	d
+GET_MMU_VER	include/ssv6200_reg.h	4807;"	d
+GET_MODEN_INT	smac/hal/ssv6006c/ssv6006C_reg.h	2885;"	d
+GET_MODE_REG_IN	include/ssv6200_reg.h	1342;"	d
+GET_MODE_REG_IN_MMU	include/ssv6200_reg.h	1373;"	d
+GET_MODE_REG_OUT_MCU	include/ssv6200_reg.h	1343;"	d
+GET_MODE_REG_OUT_MMU	include/ssv6200_reg.h	1374;"	d
+GET_MODE_REG_SI	include/ssv6200_reg.h	1339;"	d
+GET_MODE_REG_SO_MCU	include/ssv6200_reg.h	1344;"	d
+GET_MODE_REG_SO_MMU	include/ssv6200_reg.h	1375;"	d
+GET_MONITOR_BUS_MCU_31_0	include/ssv6200_reg.h	1345;"	d
+GET_MONITOR_BUS_MCU_33_32	include/ssv6200_reg.h	1346;"	d
+GET_MONITOR_BUS_MMU	include/ssv6200_reg.h	1376;"	d
+GET_MP_MRX_RX_EN_SEL	include/ssv6200_reg.h	1865;"	d
+GET_MP_PHY2RX_DATA__0_SEL	include/ssv6200_reg.h	1842;"	d
+GET_MP_PHY2RX_DATA__1_SEL	include/ssv6200_reg.h	1843;"	d
+GET_MP_PHY2RX_DATA__2_SEL	include/ssv6200_reg.h	1848;"	d
+GET_MP_PHY2RX_DATA__3_SEL	include/ssv6200_reg.h	1853;"	d
+GET_MP_PHY2RX_DATA__4_SEL	include/ssv6200_reg.h	1849;"	d
+GET_MP_PHY2RX_DATA__5_SEL	include/ssv6200_reg.h	1852;"	d
+GET_MP_PHY2RX_DATA__6_SEL	include/ssv6200_reg.h	1855;"	d
+GET_MP_PHY2RX_DATA__7_SEL	include/ssv6200_reg.h	1861;"	d
+GET_MP_PHY_RX_WRST_N_SEL	include/ssv6200_reg.h	1859;"	d
+GET_MP_RX_FF_WPTR__0_SEL	include/ssv6200_reg.h	1847;"	d
+GET_MP_RX_FF_WPTR__1_SEL	include/ssv6200_reg.h	1846;"	d
+GET_MP_RX_FF_WPTR__2_SEL	include/ssv6200_reg.h	1845;"	d
+GET_MP_TX_FF_RPTR__0_SEL	include/ssv6200_reg.h	1858;"	d
+GET_MP_TX_FF_RPTR__1_SEL	include/ssv6200_reg.h	1844;"	d
+GET_MP_TX_FF_RPTR__2_SEL	include/ssv6200_reg.h	1862;"	d
+GET_MRX_ACK_NTF	include/ssv6200_reg.h	3171;"	d
+GET_MRX_ACK_NTF	smac/hal/ssv6006c/ssv6006C_reg.h	4019;"	d
+GET_MRX_ALC_FAIL	include/ssv6200_reg.h	3167;"	d
+GET_MRX_ALC_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	4015;"	d
+GET_MRX_BAR_NTF	include/ssv6200_reg.h	3176;"	d
+GET_MRX_BAR_NTF	smac/hal/ssv6006c/ssv6006C_reg.h	4024;"	d
+GET_MRX_BA_NTF	include/ssv6200_reg.h	3172;"	d
+GET_MRX_BA_NTF	smac/hal/ssv6006c/ssv6006C_reg.h	4020;"	d
+GET_MRX_CCA	include/ssv6200_reg.h	2802;"	d
+GET_MRX_CLK_EN	include/ssv6200_reg.h	3063;"	d
+GET_MRX_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3895;"	d
+GET_MRX_CSR_CLK_EN	include/ssv6200_reg.h	3082;"	d
+GET_MRX_CSR_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3914;"	d
+GET_MRX_CSR_NTF	include/ssv6200_reg.h	3179;"	d
+GET_MRX_CSR_NTF	smac/hal/ssv6006c/ssv6006C_reg.h	4027;"	d
+GET_MRX_CSR_RST	include/ssv6200_reg.h	3054;"	d
+GET_MRX_CSR_RST	smac/hal/ssv6006c/ssv6006C_reg.h	3886;"	d
+GET_MRX_CTS_NTF	include/ssv6200_reg.h	3170;"	d
+GET_MRX_CTS_NTF	smac/hal/ssv6006c/ssv6006C_reg.h	4018;"	d
+GET_MRX_DATA_NTF	include/ssv6200_reg.h	3173;"	d
+GET_MRX_DATA_NTF	smac/hal/ssv6006c/ssv6006C_reg.h	4021;"	d
+GET_MRX_DAT_CRC_NTF	include/ssv6200_reg.h	3175;"	d
+GET_MRX_DAT_CRC_NTF	smac/hal/ssv6006c/ssv6006C_reg.h	4023;"	d
+GET_MRX_DAT_NTF	include/ssv6200_reg.h	3168;"	d
+GET_MRX_DAT_NTF	smac/hal/ssv6006c/ssv6006C_reg.h	4016;"	d
+GET_MRX_DUP	include/ssv6200_reg.h	3161;"	d
+GET_MRX_DUP	smac/hal/ssv6006c/ssv6006C_reg.h	4009;"	d
+GET_MRX_ENG_CLK_EN	include/ssv6200_reg.h	3075;"	d
+GET_MRX_ENG_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3907;"	d
+GET_MRX_ENG_RST	include/ssv6200_reg.h	3040;"	d
+GET_MRX_ENG_RST	smac/hal/ssv6006c/ssv6006C_reg.h	3872;"	d
+GET_MRX_ERR	include/ssv6200_reg.h	2713;"	d
+GET_MRX_ERR	smac/hal/ssv6006c/ssv6006C_reg.h	3437;"	d
+GET_MRX_FCS_ERR	include/ssv6200_reg.h	3164;"	d
+GET_MRX_FCS_ERR	smac/hal/ssv6006c/ssv6006C_reg.h	4012;"	d
+GET_MRX_FCS_SUC	include/ssv6200_reg.h	3165;"	d
+GET_MRX_FCS_SUC	smac/hal/ssv6006c/ssv6006C_reg.h	4013;"	d
+GET_MRX_FLT_EN0	include/ssv6200_reg.h	2673;"	d
+GET_MRX_FLT_EN0	smac/hal/ssv6006c/ssv6006C_reg.h	3397;"	d
+GET_MRX_FLT_EN1	include/ssv6200_reg.h	2674;"	d
+GET_MRX_FLT_EN1	smac/hal/ssv6006c/ssv6006C_reg.h	3398;"	d
+GET_MRX_FLT_EN10	smac/hal/ssv6006c/ssv6006C_reg.h	3457;"	d
+GET_MRX_FLT_EN2	include/ssv6200_reg.h	2675;"	d
+GET_MRX_FLT_EN2	smac/hal/ssv6006c/ssv6006C_reg.h	3399;"	d
+GET_MRX_FLT_EN3	include/ssv6200_reg.h	2676;"	d
+GET_MRX_FLT_EN3	smac/hal/ssv6006c/ssv6006C_reg.h	3400;"	d
+GET_MRX_FLT_EN4	include/ssv6200_reg.h	2677;"	d
+GET_MRX_FLT_EN4	smac/hal/ssv6006c/ssv6006C_reg.h	3401;"	d
+GET_MRX_FLT_EN5	include/ssv6200_reg.h	2678;"	d
+GET_MRX_FLT_EN5	smac/hal/ssv6006c/ssv6006C_reg.h	3402;"	d
+GET_MRX_FLT_EN6	include/ssv6200_reg.h	2679;"	d
+GET_MRX_FLT_EN6	smac/hal/ssv6006c/ssv6006C_reg.h	3403;"	d
+GET_MRX_FLT_EN7	include/ssv6200_reg.h	2680;"	d
+GET_MRX_FLT_EN7	smac/hal/ssv6006c/ssv6006C_reg.h	3404;"	d
+GET_MRX_FLT_EN8	include/ssv6200_reg.h	2681;"	d
+GET_MRX_FLT_EN8	smac/hal/ssv6006c/ssv6006C_reg.h	3405;"	d
+GET_MRX_FLT_EN9	smac/hal/ssv6006c/ssv6006C_reg.h	3456;"	d
+GET_MRX_FLT_TB0	include/ssv6200_reg.h	2657;"	d
+GET_MRX_FLT_TB0	smac/hal/ssv6006c/ssv6006C_reg.h	3381;"	d
+GET_MRX_FLT_TB1	include/ssv6200_reg.h	2658;"	d
+GET_MRX_FLT_TB1	smac/hal/ssv6006c/ssv6006C_reg.h	3382;"	d
+GET_MRX_FLT_TB10	include/ssv6200_reg.h	2667;"	d
+GET_MRX_FLT_TB10	smac/hal/ssv6006c/ssv6006C_reg.h	3391;"	d
+GET_MRX_FLT_TB11	include/ssv6200_reg.h	2668;"	d
+GET_MRX_FLT_TB11	smac/hal/ssv6006c/ssv6006C_reg.h	3392;"	d
+GET_MRX_FLT_TB12	include/ssv6200_reg.h	2669;"	d
+GET_MRX_FLT_TB12	smac/hal/ssv6006c/ssv6006C_reg.h	3393;"	d
+GET_MRX_FLT_TB13	include/ssv6200_reg.h	2670;"	d
+GET_MRX_FLT_TB13	smac/hal/ssv6006c/ssv6006C_reg.h	3394;"	d
+GET_MRX_FLT_TB14	include/ssv6200_reg.h	2671;"	d
+GET_MRX_FLT_TB14	smac/hal/ssv6006c/ssv6006C_reg.h	3395;"	d
+GET_MRX_FLT_TB15	include/ssv6200_reg.h	2672;"	d
+GET_MRX_FLT_TB15	smac/hal/ssv6006c/ssv6006C_reg.h	3396;"	d
+GET_MRX_FLT_TB2	include/ssv6200_reg.h	2659;"	d
+GET_MRX_FLT_TB2	smac/hal/ssv6006c/ssv6006C_reg.h	3383;"	d
+GET_MRX_FLT_TB3	include/ssv6200_reg.h	2660;"	d
+GET_MRX_FLT_TB3	smac/hal/ssv6006c/ssv6006C_reg.h	3384;"	d
+GET_MRX_FLT_TB4	include/ssv6200_reg.h	2661;"	d
+GET_MRX_FLT_TB4	smac/hal/ssv6006c/ssv6006C_reg.h	3385;"	d
+GET_MRX_FLT_TB5	include/ssv6200_reg.h	2662;"	d
+GET_MRX_FLT_TB5	smac/hal/ssv6006c/ssv6006C_reg.h	3386;"	d
+GET_MRX_FLT_TB6	include/ssv6200_reg.h	2663;"	d
+GET_MRX_FLT_TB6	smac/hal/ssv6006c/ssv6006C_reg.h	3387;"	d
+GET_MRX_FLT_TB7	include/ssv6200_reg.h	2664;"	d
+GET_MRX_FLT_TB7	smac/hal/ssv6006c/ssv6006C_reg.h	3388;"	d
+GET_MRX_FLT_TB8	include/ssv6200_reg.h	2665;"	d
+GET_MRX_FLT_TB8	smac/hal/ssv6006c/ssv6006C_reg.h	3389;"	d
+GET_MRX_FLT_TB9	include/ssv6200_reg.h	2666;"	d
+GET_MRX_FLT_TB9	smac/hal/ssv6006c/ssv6006C_reg.h	3390;"	d
+GET_MRX_FRG	include/ssv6200_reg.h	3162;"	d
+GET_MRX_FRG	smac/hal/ssv6006c/ssv6006C_reg.h	4010;"	d
+GET_MRX_GRP	include/ssv6200_reg.h	3163;"	d
+GET_MRX_GRP	smac/hal/ssv6006c/ssv6006C_reg.h	4011;"	d
+GET_MRX_LEN_FLT	include/ssv6200_reg.h	2682;"	d
+GET_MRX_LEN_FLT	smac/hal/ssv6006c/ssv6006C_reg.h	3406;"	d
+GET_MRX_MB_MISS	include/ssv6200_reg.h	3177;"	d
+GET_MRX_MB_MISS	smac/hal/ssv6006c/ssv6006C_reg.h	4025;"	d
+GET_MRX_MCAST_CTRL_0	include/ssv6200_reg.h	2638;"	d
+GET_MRX_MCAST_CTRL_0	smac/hal/ssv6006c/ssv6006C_reg.h	3362;"	d
+GET_MRX_MCAST_CTRL_1	include/ssv6200_reg.h	2643;"	d
+GET_MRX_MCAST_CTRL_1	smac/hal/ssv6006c/ssv6006C_reg.h	3367;"	d
+GET_MRX_MCAST_CTRL_2	include/ssv6200_reg.h	2648;"	d
+GET_MRX_MCAST_CTRL_2	smac/hal/ssv6006c/ssv6006C_reg.h	3372;"	d
+GET_MRX_MCAST_CTRL_3	include/ssv6200_reg.h	2653;"	d
+GET_MRX_MCAST_CTRL_3	smac/hal/ssv6006c/ssv6006C_reg.h	3377;"	d
+GET_MRX_MCAST_MASK0_31_0	include/ssv6200_reg.h	2636;"	d
+GET_MRX_MCAST_MASK0_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	3360;"	d
+GET_MRX_MCAST_MASK0_47_32	include/ssv6200_reg.h	2637;"	d
+GET_MRX_MCAST_MASK0_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	3361;"	d
+GET_MRX_MCAST_MASK1_31_0	include/ssv6200_reg.h	2641;"	d
+GET_MRX_MCAST_MASK1_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	3365;"	d
+GET_MRX_MCAST_MASK1_47_32	include/ssv6200_reg.h	2642;"	d
+GET_MRX_MCAST_MASK1_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	3366;"	d
+GET_MRX_MCAST_MASK2_31_0	include/ssv6200_reg.h	2646;"	d
+GET_MRX_MCAST_MASK2_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	3370;"	d
+GET_MRX_MCAST_MASK2_47_32	include/ssv6200_reg.h	2647;"	d
+GET_MRX_MCAST_MASK2_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	3371;"	d
+GET_MRX_MCAST_MASK3_31_0	include/ssv6200_reg.h	2651;"	d
+GET_MRX_MCAST_MASK3_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	3375;"	d
+GET_MRX_MCAST_MASK3_47_32	include/ssv6200_reg.h	2652;"	d
+GET_MRX_MCAST_MASK3_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	3376;"	d
+GET_MRX_MCAST_TB0_31_0	include/ssv6200_reg.h	2634;"	d
+GET_MRX_MCAST_TB0_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	3358;"	d
+GET_MRX_MCAST_TB0_47_32	include/ssv6200_reg.h	2635;"	d
+GET_MRX_MCAST_TB0_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	3359;"	d
+GET_MRX_MCAST_TB1_31_0	include/ssv6200_reg.h	2639;"	d
+GET_MRX_MCAST_TB1_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	3363;"	d
+GET_MRX_MCAST_TB1_47_32	include/ssv6200_reg.h	2640;"	d
+GET_MRX_MCAST_TB1_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	3364;"	d
+GET_MRX_MCAST_TB2_31_0	include/ssv6200_reg.h	2644;"	d
+GET_MRX_MCAST_TB2_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	3368;"	d
+GET_MRX_MCAST_TB2_47_32	include/ssv6200_reg.h	2645;"	d
+GET_MRX_MCAST_TB2_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	3369;"	d
+GET_MRX_MCAST_TB3_31_0	include/ssv6200_reg.h	2649;"	d
+GET_MRX_MCAST_TB3_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	3373;"	d
+GET_MRX_MCAST_TB3_47_32	include/ssv6200_reg.h	2650;"	d
+GET_MRX_MCAST_TB3_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	3374;"	d
+GET_MRX_MISS	include/ssv6200_reg.h	3166;"	d
+GET_MRX_MISS	smac/hal/ssv6006c/ssv6006C_reg.h	4014;"	d
+GET_MRX_MNG_NTF	include/ssv6200_reg.h	3174;"	d
+GET_MRX_MNG_NTF	smac/hal/ssv6006c/ssv6006C_reg.h	4022;"	d
+GET_MRX_NIDLE_MISS	include/ssv6200_reg.h	3178;"	d
+GET_MRX_NIDLE_MISS	smac/hal/ssv6006c/ssv6006C_reg.h	4026;"	d
+GET_MRX_PHY_INFO	include/ssv6200_reg.h	2654;"	d
+GET_MRX_PHY_INFO	smac/hal/ssv6006c/ssv6006C_reg.h	3378;"	d
+GET_MRX_RTS_NTF	include/ssv6200_reg.h	3169;"	d
+GET_MRX_RTS_NTF	smac/hal/ssv6006c/ssv6006C_reg.h	4017;"	d
+GET_MRX_RX_EN	include/ssv6200_reg.h	2809;"	d
+GET_MRX_STP_EN	include/ssv6200_reg.h	2686;"	d
+GET_MRX_STP_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3410;"	d
+GET_MRX_STP_OFST	include/ssv6200_reg.h	2687;"	d
+GET_MRX_STP_OFST	smac/hal/ssv6006c/ssv6006C_reg.h	3411;"	d
+GET_MRX_SW_RST	include/ssv6200_reg.h	3028;"	d
+GET_MRX_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	3860;"	d
+GET_MRX_WD	include/ssv6200_reg.h	2703;"	d
+GET_MRX_WD	smac/hal/ssv6006c/ssv6006C_reg.h	3427;"	d
+GET_MS0TMR_CLK_EN	include/ssv6200_reg.h	1316;"	d
+GET_MS0TMR_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2395;"	d
+GET_MS0TMR_SW_RST	include/ssv6200_reg.h	1282;"	d
+GET_MS0TMR_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	2361;"	d
+GET_MS1TMR_CLK_EN	include/ssv6200_reg.h	1317;"	d
+GET_MS1TMR_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2396;"	d
+GET_MS1TMR_SW_RST	include/ssv6200_reg.h	1283;"	d
+GET_MS1TMR_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	2362;"	d
+GET_MS2TMR_CLK_EN	include/ssv6200_reg.h	1318;"	d
+GET_MS2TMR_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2397;"	d
+GET_MS2TMR_SW_RST	include/ssv6200_reg.h	1284;"	d
+GET_MS2TMR_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	2363;"	d
+GET_MS3TMR_CLK_EN	include/ssv6200_reg.h	1319;"	d
+GET_MS3TMR_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2398;"	d
+GET_MS3TMR_SW_RST	include/ssv6200_reg.h	1285;"	d
+GET_MS3TMR_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	2364;"	d
+GET_MTX_ACK_DUR0	include/ssv6200_reg.h	2768;"	d
+GET_MTX_ACK_FAIL	include/ssv6200_reg.h	3157;"	d
+GET_MTX_ACK_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	4005;"	d
+GET_MTX_ACK_TX	include/ssv6200_reg.h	3159;"	d
+GET_MTX_ACK_TX	smac/hal/ssv6006c/ssv6006C_reg.h	4007;"	d
+GET_MTX_AMPDU_CRC8_AUTO	smac/hal/ssv6006c/ssv6006C_reg.h	3489;"	d
+GET_MTX_AMPDU_CRC_AUTO	include/ssv6200_reg.h	2765;"	d
+GET_MTX_AMPDU_SET_DIF	include/ssv6200_reg.h	2777;"	d
+GET_MTX_AUTO_BCN_ONGOING	include/ssv6200_reg.h	2791;"	d
+GET_MTX_AUTO_BCN_ONGOING	smac/hal/ssv6006c/ssv6006C_reg.h	3601;"	d
+GET_MTX_AUTO_FLUSH_Q4	include/ssv6200_reg.h	2788;"	d
+GET_MTX_BCN_AUTO_SEQ_NO	smac/hal/ssv6006c/ssv6006C_reg.h	3598;"	d
+GET_MTX_BCN_CFG_VLD	include/ssv6200_reg.h	2790;"	d
+GET_MTX_BCN_CFG_VLD	smac/hal/ssv6006c/ssv6006C_reg.h	3600;"	d
+GET_MTX_BCN_ENG_RST	include/ssv6200_reg.h	3039;"	d
+GET_MTX_BCN_ENG_RST	smac/hal/ssv6006c/ssv6006C_reg.h	3871;"	d
+GET_MTX_BCN_PERIOD	include/ssv6200_reg.h	2793;"	d
+GET_MTX_BCN_PERIOD	smac/hal/ssv6006c/ssv6006C_reg.h	3603;"	d
+GET_MTX_BCN_PKTID_CH_LOCK	include/ssv6200_reg.h	2789;"	d
+GET_MTX_BCN_PKTID_CH_LOCK	smac/hal/ssv6006c/ssv6006C_reg.h	3599;"	d
+GET_MTX_BCN_PKT_ID0	include/ssv6200_reg.h	2797;"	d
+GET_MTX_BCN_PKT_ID0	smac/hal/ssv6006c/ssv6006C_reg.h	3583;"	d
+GET_MTX_BCN_PKT_ID1	include/ssv6200_reg.h	2799;"	d
+GET_MTX_BCN_PKT_ID1	smac/hal/ssv6006c/ssv6006C_reg.h	3584;"	d
+GET_MTX_BCN_SW_RST	include/ssv6200_reg.h	3027;"	d
+GET_MTX_BCN_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	3859;"	d
+GET_MTX_BCN_TIMER	include/ssv6200_reg.h	2792;"	d
+GET_MTX_BCN_TIMER	smac/hal/ssv6006c/ssv6006C_reg.h	3602;"	d
+GET_MTX_BCN_TIMER_EN	include/ssv6200_reg.h	2783;"	d
+GET_MTX_BCN_TIMER_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3593;"	d
+GET_MTX_BCN_TSF_L	include/ssv6200_reg.h	2795;"	d
+GET_MTX_BCN_TSF_L	smac/hal/ssv6006c/ssv6006C_reg.h	3604;"	d
+GET_MTX_BCN_TSF_U	include/ssv6200_reg.h	2796;"	d
+GET_MTX_BCN_TSF_U	smac/hal/ssv6006c/ssv6006C_reg.h	3605;"	d
+GET_MTX_BLOCKTX_IGNORE_BT_BUSY	smac/hal/ssv6006c/ssv6006C_reg.h	3490;"	d
+GET_MTX_BLOCKTX_IGNORE_TOMAC_CCA_CS	smac/hal/ssv6006c/ssv6006C_reg.h	3494;"	d
+GET_MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_PRIMARY	smac/hal/ssv6006c/ssv6006C_reg.h	3496;"	d
+GET_MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_SECONDARY	smac/hal/ssv6006c/ssv6006C_reg.h	3495;"	d
+GET_MTX_BLOCKTX_IGNORE_TOMAC_RX_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3493;"	d
+GET_MTX_BLOCKTX_IGNORE_TOMAC_TX_IP	smac/hal/ssv6006c/ssv6006C_reg.h	3492;"	d
+GET_MTX_CCA	include/ssv6200_reg.h	2801;"	d
+GET_MTX_CHST_ENG_RST	include/ssv6200_reg.h	3038;"	d
+GET_MTX_CHST_ENG_RST	smac/hal/ssv6006c/ssv6006C_reg.h	3870;"	d
+GET_MTX_CHST_SW_RST	include/ssv6200_reg.h	3026;"	d
+GET_MTX_CHST_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	3858;"	d
+GET_MTX_CTS_SET_DIF	include/ssv6200_reg.h	2776;"	d
+GET_MTX_CTS_TX	include/ssv6200_reg.h	3160;"	d
+GET_MTX_CTS_TX	smac/hal/ssv6006c/ssv6006C_reg.h	4008;"	d
+GET_MTX_DBGOPT_FORCE_DO_RTS_CTS_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	3574;"	d
+GET_MTX_DBGOPT_FORCE_DO_RTS_CTS_MODE_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3577;"	d
+GET_MTX_DBGOPT_FORCE_TXCTRL_RATE	smac/hal/ssv6006c/ssv6006C_reg.h	3573;"	d
+GET_MTX_DBGOPT_FORCE_TXCTRL_RATE_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3576;"	d
+GET_MTX_DBGOPT_FORCE_TXMAJOR_RATE	smac/hal/ssv6006c/ssv6006C_reg.h	3572;"	d
+GET_MTX_DBGOPT_FORCE_TXMAJOR_RATE_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3575;"	d
+GET_MTX_DBG_PHYRX_IFS_DELTATIME	smac/hal/ssv6006c/ssv6006C_reg.h	3627;"	d
+GET_MTX_DMA_FSM	include/ssv6200_reg.h	2803;"	d
+GET_MTX_DMA_REQ	include/ssv6200_reg.h	2806;"	d
+GET_MTX_DTIM_CNT_AUTO_FILL	smac/hal/ssv6006c/ssv6006C_reg.h	3595;"	d
+GET_MTX_DTIM_NUM	include/ssv6200_reg.h	2794;"	d
+GET_MTX_DTIM_NUM	smac/hal/ssv6006c/ssv6006C_reg.h	3587;"	d
+GET_MTX_DTIM_OFST0	include/ssv6200_reg.h	2798;"	d
+GET_MTX_DTIM_OFST0	smac/hal/ssv6006c/ssv6006C_reg.h	3585;"	d
+GET_MTX_DTIM_OFST1	include/ssv6200_reg.h	2800;"	d
+GET_MTX_DTIM_OFST1	smac/hal/ssv6006c/ssv6006C_reg.h	3586;"	d
+GET_MTX_DUR_BURST_SIFS	include/ssv6200_reg.h	2825;"	d
+GET_MTX_DUR_BURST_SIFS_G	include/ssv6200_reg.h	2829;"	d
+GET_MTX_DUR_RSP_EIFS	include/ssv6200_reg.h	2827;"	d
+GET_MTX_DUR_RSP_EIFS_G	include/ssv6200_reg.h	2831;"	d
+GET_MTX_DUR_RSP_SIFS	include/ssv6200_reg.h	2824;"	d
+GET_MTX_DUR_RSP_SIFS_G	include/ssv6200_reg.h	2828;"	d
+GET_MTX_DUR_RSP_TOUT_B	include/ssv6200_reg.h	2822;"	d
+GET_MTX_DUR_RSP_TOUT_G	include/ssv6200_reg.h	2823;"	d
+GET_MTX_DUR_SLOT	include/ssv6200_reg.h	2826;"	d
+GET_MTX_DUR_SLOT_G	include/ssv6200_reg.h	2830;"	d
+GET_MTX_EDCCA_TOUT	include/ssv6200_reg.h	2778;"	d
+GET_MTX_EN_INT_BCN	include/ssv6200_reg.h	2781;"	d
+GET_MTX_EN_INT_BCN	smac/hal/ssv6006c/ssv6006C_reg.h	3591;"	d
+GET_MTX_EN_INT_DTIM	include/ssv6200_reg.h	2782;"	d
+GET_MTX_EN_INT_DTIM	smac/hal/ssv6006c/ssv6006C_reg.h	3592;"	d
+GET_MTX_EN_INT_Q0_Q_EMPTY	include/ssv6200_reg.h	2753;"	d
+GET_MTX_EN_INT_Q0_Q_EMPTY	smac/hal/ssv6006c/ssv6006C_reg.h	3475;"	d
+GET_MTX_EN_INT_Q0_TXOP_RUNOUT	include/ssv6200_reg.h	2754;"	d
+GET_MTX_EN_INT_Q0_TXOP_RUNOUT	smac/hal/ssv6006c/ssv6006C_reg.h	3476;"	d
+GET_MTX_EN_INT_Q1_Q_EMPTY	include/ssv6200_reg.h	2755;"	d
+GET_MTX_EN_INT_Q1_Q_EMPTY	smac/hal/ssv6006c/ssv6006C_reg.h	3477;"	d
+GET_MTX_EN_INT_Q1_TXOP_RUNOUT	include/ssv6200_reg.h	2756;"	d
+GET_MTX_EN_INT_Q1_TXOP_RUNOUT	smac/hal/ssv6006c/ssv6006C_reg.h	3478;"	d
+GET_MTX_EN_INT_Q2_Q_EMPTY	include/ssv6200_reg.h	2757;"	d
+GET_MTX_EN_INT_Q2_Q_EMPTY	smac/hal/ssv6006c/ssv6006C_reg.h	3479;"	d
+GET_MTX_EN_INT_Q2_TXOP_RUNOUT	include/ssv6200_reg.h	2758;"	d
+GET_MTX_EN_INT_Q2_TXOP_RUNOUT	smac/hal/ssv6006c/ssv6006C_reg.h	3480;"	d
+GET_MTX_EN_INT_Q3_Q_EMPTY	include/ssv6200_reg.h	2759;"	d
+GET_MTX_EN_INT_Q3_Q_EMPTY	smac/hal/ssv6006c/ssv6006C_reg.h	3481;"	d
+GET_MTX_EN_INT_Q3_TXOP_RUNOUT	include/ssv6200_reg.h	2760;"	d
+GET_MTX_EN_INT_Q3_TXOP_RUNOUT	smac/hal/ssv6006c/ssv6006C_reg.h	3482;"	d
+GET_MTX_EN_INT_Q4_Q_EMPTY	include/ssv6200_reg.h	2761;"	d
+GET_MTX_EN_INT_Q4_Q_EMPTY	smac/hal/ssv6006c/ssv6006C_reg.h	3483;"	d
+GET_MTX_EN_INT_Q4_TXOP_RUNOUT	include/ssv6200_reg.h	2762;"	d
+GET_MTX_EN_INT_Q4_TXOP_RUNOUT	smac/hal/ssv6006c/ssv6006C_reg.h	3484;"	d
+GET_MTX_EN_INT_Q5_Q_EMPTY	smac/hal/ssv6006c/ssv6006C_reg.h	3485;"	d
+GET_MTX_EN_INT_Q5_TXOP_RUNOUT	smac/hal/ssv6006c/ssv6006C_reg.h	3486;"	d
+GET_MTX_FAIL	include/ssv6200_reg.h	3152;"	d
+GET_MTX_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	4000;"	d
+GET_MTX_FAST_RSP_MODE	include/ssv6200_reg.h	2766;"	d
+GET_MTX_FORCE_BKF_RXEN0	include/ssv6200_reg.h	2772;"	d
+GET_MTX_FORCE_CS_IDLE	include/ssv6200_reg.h	2771;"	d
+GET_MTX_FORCE_DMA_RXEN0	include/ssv6200_reg.h	2773;"	d
+GET_MTX_FORCE_RXEN0	include/ssv6200_reg.h	2774;"	d
+GET_MTX_FRM	include/ssv6200_reg.h	3158;"	d
+GET_MTX_FRM	smac/hal/ssv6006c/ssv6006C_reg.h	4006;"	d
+GET_MTX_GNT_LOCK	include/ssv6200_reg.h	2805;"	d
+GET_MTX_GRP	include/ssv6200_reg.h	3151;"	d
+GET_MTX_GRP	smac/hal/ssv6006c/ssv6006C_reg.h	3999;"	d
+GET_MTX_HALT_IGNORE_RXREQ_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3518;"	d
+GET_MTX_HALT_IGNORE_TXREQ_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3517;"	d
+GET_MTX_HALT_MNG_UNTIL_DTIM	include/ssv6200_reg.h	2786;"	d
+GET_MTX_HALT_MODE0	smac/hal/ssv6006c/ssv6006C_reg.h	3515;"	d
+GET_MTX_HALT_Q_MB	include/ssv6200_reg.h	2775;"	d
+GET_MTX_HALT_Q_MB	smac/hal/ssv6006c/ssv6006C_reg.h	3497;"	d
+GET_MTX_IGNORE_PHYRX_IFS_DELTATIME	smac/hal/ssv6006c/ssv6006C_reg.h	3498;"	d
+GET_MTX_INT_BCN	include/ssv6200_reg.h	2779;"	d
+GET_MTX_INT_BCN	smac/hal/ssv6006c/ssv6006C_reg.h	3590;"	d
+GET_MTX_INT_DTIM	include/ssv6200_reg.h	2780;"	d
+GET_MTX_INT_DTIM	smac/hal/ssv6006c/ssv6006C_reg.h	3589;"	d
+GET_MTX_INT_DTIM_NUM	include/ssv6200_reg.h	2787;"	d
+GET_MTX_INT_DTIM_NUM	smac/hal/ssv6006c/ssv6006C_reg.h	3588;"	d
+GET_MTX_INT_Q0_Q_EMPTY	include/ssv6200_reg.h	2743;"	d
+GET_MTX_INT_Q0_Q_EMPTY	smac/hal/ssv6006c/ssv6006C_reg.h	3463;"	d
+GET_MTX_INT_Q0_TXOP_RUNOUT	include/ssv6200_reg.h	2744;"	d
+GET_MTX_INT_Q0_TXOP_RUNOUT	smac/hal/ssv6006c/ssv6006C_reg.h	3464;"	d
+GET_MTX_INT_Q1_Q_EMPTY	include/ssv6200_reg.h	2745;"	d
+GET_MTX_INT_Q1_Q_EMPTY	smac/hal/ssv6006c/ssv6006C_reg.h	3465;"	d
+GET_MTX_INT_Q1_TXOP_RUNOUT	include/ssv6200_reg.h	2746;"	d
+GET_MTX_INT_Q1_TXOP_RUNOUT	smac/hal/ssv6006c/ssv6006C_reg.h	3466;"	d
+GET_MTX_INT_Q2_Q_EMPTY	include/ssv6200_reg.h	2747;"	d
+GET_MTX_INT_Q2_Q_EMPTY	smac/hal/ssv6006c/ssv6006C_reg.h	3467;"	d
+GET_MTX_INT_Q2_TXOP_RUNOUT	include/ssv6200_reg.h	2748;"	d
+GET_MTX_INT_Q2_TXOP_RUNOUT	smac/hal/ssv6006c/ssv6006C_reg.h	3468;"	d
+GET_MTX_INT_Q3_Q_EMPTY	include/ssv6200_reg.h	2749;"	d
+GET_MTX_INT_Q3_Q_EMPTY	smac/hal/ssv6006c/ssv6006C_reg.h	3469;"	d
+GET_MTX_INT_Q3_TXOP_RUNOUT	include/ssv6200_reg.h	2750;"	d
+GET_MTX_INT_Q3_TXOP_RUNOUT	smac/hal/ssv6006c/ssv6006C_reg.h	3470;"	d
+GET_MTX_INT_Q4_Q_EMPTY	include/ssv6200_reg.h	2751;"	d
+GET_MTX_INT_Q4_Q_EMPTY	smac/hal/ssv6006c/ssv6006C_reg.h	3471;"	d
+GET_MTX_INT_Q4_TXOP_RUNOUT	include/ssv6200_reg.h	2752;"	d
+GET_MTX_INT_Q4_TXOP_RUNOUT	smac/hal/ssv6006c/ssv6006C_reg.h	3472;"	d
+GET_MTX_INT_Q5_Q_EMPTY	smac/hal/ssv6006c/ssv6006C_reg.h	3473;"	d
+GET_MTX_INT_Q5_TXOP_RUNOUT	smac/hal/ssv6006c/ssv6006C_reg.h	3474;"	d
+GET_MTX_M2M_SLOW_PRD	include/ssv6200_reg.h	2764;"	d
+GET_MTX_M2M_SLOW_PRD	smac/hal/ssv6006c/ssv6006C_reg.h	3488;"	d
+GET_MTX_MIB_CNT0	include/ssv6200_reg.h	2835;"	d
+GET_MTX_MIB_CNT0_ATTEMPT	smac/hal/ssv6006c/ssv6006C_reg.h	3521;"	d
+GET_MTX_MIB_CNT0_FRAME	smac/hal/ssv6006c/ssv6006C_reg.h	3520;"	d
+GET_MTX_MIB_CNT0_SUCC	smac/hal/ssv6006c/ssv6006C_reg.h	3522;"	d
+GET_MTX_MIB_CNT1	include/ssv6200_reg.h	2837;"	d
+GET_MTX_MIB_CNT1_ATTEMPT	smac/hal/ssv6006c/ssv6006C_reg.h	3525;"	d
+GET_MTX_MIB_CNT1_FRAME	smac/hal/ssv6006c/ssv6006C_reg.h	3524;"	d
+GET_MTX_MIB_CNT1_SUCC	smac/hal/ssv6006c/ssv6006C_reg.h	3526;"	d
+GET_MTX_MIB_CNT2_ATTEMPT	smac/hal/ssv6006c/ssv6006C_reg.h	3529;"	d
+GET_MTX_MIB_CNT2_FRAME	smac/hal/ssv6006c/ssv6006C_reg.h	3528;"	d
+GET_MTX_MIB_CNT2_SUCC	smac/hal/ssv6006c/ssv6006C_reg.h	3530;"	d
+GET_MTX_MIB_CNT3_ATTEMPT	smac/hal/ssv6006c/ssv6006C_reg.h	3533;"	d
+GET_MTX_MIB_CNT3_FRAME	smac/hal/ssv6006c/ssv6006C_reg.h	3532;"	d
+GET_MTX_MIB_CNT3_SUCC	smac/hal/ssv6006c/ssv6006C_reg.h	3534;"	d
+GET_MTX_MIB_CNT4_ATTEMPT	smac/hal/ssv6006c/ssv6006C_reg.h	3537;"	d
+GET_MTX_MIB_CNT4_FRAME	smac/hal/ssv6006c/ssv6006C_reg.h	3536;"	d
+GET_MTX_MIB_CNT4_SUCC	smac/hal/ssv6006c/ssv6006C_reg.h	3538;"	d
+GET_MTX_MIB_CNT5_ATTEMPT	smac/hal/ssv6006c/ssv6006C_reg.h	3541;"	d
+GET_MTX_MIB_CNT5_FRAME	smac/hal/ssv6006c/ssv6006C_reg.h	3540;"	d
+GET_MTX_MIB_CNT5_SUCC	smac/hal/ssv6006c/ssv6006C_reg.h	3542;"	d
+GET_MTX_MIB_CNT6_ATTEMPT	smac/hal/ssv6006c/ssv6006C_reg.h	3545;"	d
+GET_MTX_MIB_CNT6_FRAME	smac/hal/ssv6006c/ssv6006C_reg.h	3544;"	d
+GET_MTX_MIB_CNT6_SUCC	smac/hal/ssv6006c/ssv6006C_reg.h	3546;"	d
+GET_MTX_MIB_CNT7_ATTEMPT	smac/hal/ssv6006c/ssv6006C_reg.h	3549;"	d
+GET_MTX_MIB_CNT7_FRAME	smac/hal/ssv6006c/ssv6006C_reg.h	3548;"	d
+GET_MTX_MIB_CNT7_SUCC	smac/hal/ssv6006c/ssv6006C_reg.h	3550;"	d
+GET_MTX_MIB_EN0	include/ssv6200_reg.h	2836;"	d
+GET_MTX_MIB_EN0	smac/hal/ssv6006c/ssv6006C_reg.h	3523;"	d
+GET_MTX_MIB_EN1	include/ssv6200_reg.h	2838;"	d
+GET_MTX_MIB_EN1	smac/hal/ssv6006c/ssv6006C_reg.h	3527;"	d
+GET_MTX_MIB_EN2	smac/hal/ssv6006c/ssv6006C_reg.h	3531;"	d
+GET_MTX_MIB_EN3	smac/hal/ssv6006c/ssv6006C_reg.h	3535;"	d
+GET_MTX_MIB_EN4	smac/hal/ssv6006c/ssv6006C_reg.h	3539;"	d
+GET_MTX_MIB_EN5	smac/hal/ssv6006c/ssv6006C_reg.h	3543;"	d
+GET_MTX_MIB_EN6	smac/hal/ssv6006c/ssv6006C_reg.h	3547;"	d
+GET_MTX_MIB_EN7	smac/hal/ssv6006c/ssv6006C_reg.h	3551;"	d
+GET_MTX_MISC_CLK_EN	include/ssv6200_reg.h	3061;"	d
+GET_MTX_MISC_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3893;"	d
+GET_MTX_MISC_CSR_RST	include/ssv6200_reg.h	3047;"	d
+GET_MTX_MISC_CSR_RST	smac/hal/ssv6006c/ssv6006C_reg.h	3879;"	d
+GET_MTX_MISC_ENG_CLK_EN	include/ssv6200_reg.h	3073;"	d
+GET_MTX_MISC_ENG_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3905;"	d
+GET_MTX_MISC_ENG_RST	include/ssv6200_reg.h	3036;"	d
+GET_MTX_MISC_ENG_RST	smac/hal/ssv6006c/ssv6006C_reg.h	3868;"	d
+GET_MTX_MISC_SW_RST	include/ssv6200_reg.h	3024;"	d
+GET_MTX_MISC_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	3856;"	d
+GET_MTX_MNG_UPTHOLD_INT	include/ssv6200_reg.h	1972;"	d
+GET_MTX_MTX2PHY_SLOW	include/ssv6200_reg.h	2763;"	d
+GET_MTX_MTX2PHY_SLOW	smac/hal/ssv6006c/ssv6006C_reg.h	3487;"	d
+GET_MTX_MULTI_RETRY	include/ssv6200_reg.h	3154;"	d
+GET_MTX_MULTI_RETRY	smac/hal/ssv6006c/ssv6006C_reg.h	4002;"	d
+GET_MTX_NAV	include/ssv6200_reg.h	2834;"	d
+GET_MTX_NAV	smac/hal/ssv6006c/ssv6006C_reg.h	3632;"	d
+GET_MTX_QUE0_CSR_RST	include/ssv6200_reg.h	3048;"	d
+GET_MTX_QUE0_CSR_RST	smac/hal/ssv6006c/ssv6006C_reg.h	3880;"	d
+GET_MTX_QUE1_CSR_RST	include/ssv6200_reg.h	3049;"	d
+GET_MTX_QUE1_CSR_RST	smac/hal/ssv6006c/ssv6006C_reg.h	3881;"	d
+GET_MTX_QUE2_CSR_RST	include/ssv6200_reg.h	3050;"	d
+GET_MTX_QUE2_CSR_RST	smac/hal/ssv6006c/ssv6006C_reg.h	3882;"	d
+GET_MTX_QUE3_CSR_RST	include/ssv6200_reg.h	3051;"	d
+GET_MTX_QUE3_CSR_RST	smac/hal/ssv6006c/ssv6006C_reg.h	3883;"	d
+GET_MTX_QUE4_CSR_RST	include/ssv6200_reg.h	3052;"	d
+GET_MTX_QUE4_CSR_RST	smac/hal/ssv6006c/ssv6006C_reg.h	3884;"	d
+GET_MTX_QUE5_CSR_RST	include/ssv6200_reg.h	3053;"	d
+GET_MTX_QUE5_CSR_RST	smac/hal/ssv6006c/ssv6006C_reg.h	3885;"	d
+GET_MTX_QUE_CLK_EN	include/ssv6200_reg.h	3062;"	d
+GET_MTX_QUE_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3894;"	d
+GET_MTX_QUE_ENG_CLK_EN	include/ssv6200_reg.h	3074;"	d
+GET_MTX_QUE_ENG_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3906;"	d
+GET_MTX_QUE_ENG_RST	include/ssv6200_reg.h	3037;"	d
+GET_MTX_QUE_ENG_RST	smac/hal/ssv6006c/ssv6006C_reg.h	3869;"	d
+GET_MTX_QUE_SW_RST	include/ssv6200_reg.h	3025;"	d
+GET_MTX_QUE_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	3857;"	d
+GET_MTX_Q_REQ	include/ssv6200_reg.h	2807;"	d
+GET_MTX_RATERPT_HWID	smac/hal/ssv6006c/ssv6006C_reg.h	3570;"	d
+GET_MTX_RAW_DATA_MODE	include/ssv6200_reg.h	2767;"	d
+GET_MTX_RAW_DATA_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	3491;"	d
+GET_MTX_RESPFRM_INFO_00	smac/hal/ssv6006c/ssv6006C_reg.h	3761;"	d
+GET_MTX_RESPFRM_INFO_01	smac/hal/ssv6006c/ssv6006C_reg.h	3762;"	d
+GET_MTX_RESPFRM_INFO_02	smac/hal/ssv6006c/ssv6006C_reg.h	3763;"	d
+GET_MTX_RESPFRM_INFO_03	smac/hal/ssv6006c/ssv6006C_reg.h	3764;"	d
+GET_MTX_RESPFRM_INFO_11	smac/hal/ssv6006c/ssv6006C_reg.h	3765;"	d
+GET_MTX_RESPFRM_INFO_12	smac/hal/ssv6006c/ssv6006C_reg.h	3766;"	d
+GET_MTX_RESPFRM_INFO_13	smac/hal/ssv6006c/ssv6006C_reg.h	3767;"	d
+GET_MTX_RESPFRM_INFO_90_B0	smac/hal/ssv6006c/ssv6006C_reg.h	3768;"	d
+GET_MTX_RESPFRM_INFO_91_B1	smac/hal/ssv6006c/ssv6006C_reg.h	3769;"	d
+GET_MTX_RESPFRM_INFO_92_B2	smac/hal/ssv6006c/ssv6006C_reg.h	3770;"	d
+GET_MTX_RESPFRM_INFO_93_B3	smac/hal/ssv6006c/ssv6006C_reg.h	3771;"	d
+GET_MTX_RESPFRM_INFO_94_B4	smac/hal/ssv6006c/ssv6006C_reg.h	3772;"	d
+GET_MTX_RESPFRM_INFO_95_B5	smac/hal/ssv6006c/ssv6006C_reg.h	3773;"	d
+GET_MTX_RESPFRM_INFO_96_B6	smac/hal/ssv6006c/ssv6006C_reg.h	3774;"	d
+GET_MTX_RESPFRM_INFO_97_B7	smac/hal/ssv6006c/ssv6006C_reg.h	3775;"	d
+GET_MTX_RESPFRM_INFO_C0	smac/hal/ssv6006c/ssv6006C_reg.h	3776;"	d
+GET_MTX_RESPFRM_INFO_C1	smac/hal/ssv6006c/ssv6006C_reg.h	3777;"	d
+GET_MTX_RESPFRM_INFO_C2	smac/hal/ssv6006c/ssv6006C_reg.h	3778;"	d
+GET_MTX_RESPFRM_INFO_C3	smac/hal/ssv6006c/ssv6006C_reg.h	3779;"	d
+GET_MTX_RESPFRM_INFO_C4	smac/hal/ssv6006c/ssv6006C_reg.h	3780;"	d
+GET_MTX_RESPFRM_INFO_C5	smac/hal/ssv6006c/ssv6006C_reg.h	3781;"	d
+GET_MTX_RESPFRM_INFO_C6	smac/hal/ssv6006c/ssv6006C_reg.h	3782;"	d
+GET_MTX_RESPFRM_INFO_C7	smac/hal/ssv6006c/ssv6006C_reg.h	3783;"	d
+GET_MTX_RESPFRM_INFO_D0	smac/hal/ssv6006c/ssv6006C_reg.h	3784;"	d
+GET_MTX_RESPFRM_INFO_D1	smac/hal/ssv6006c/ssv6006C_reg.h	3785;"	d
+GET_MTX_RESPFRM_INFO_D2	smac/hal/ssv6006c/ssv6006C_reg.h	3786;"	d
+GET_MTX_RESPFRM_INFO_D3	smac/hal/ssv6006c/ssv6006C_reg.h	3787;"	d
+GET_MTX_RESPFRM_INFO_D4	smac/hal/ssv6006c/ssv6006C_reg.h	3788;"	d
+GET_MTX_RESPFRM_INFO_D5	smac/hal/ssv6006c/ssv6006C_reg.h	3789;"	d
+GET_MTX_RESPFRM_INFO_D6	smac/hal/ssv6006c/ssv6006C_reg.h	3790;"	d
+GET_MTX_RESPFRM_INFO_D7	smac/hal/ssv6006c/ssv6006C_reg.h	3791;"	d
+GET_MTX_RESPFRM_INFO_D8	smac/hal/ssv6006c/ssv6006C_reg.h	3792;"	d
+GET_MTX_RESPFRM_INFO_D9	smac/hal/ssv6006c/ssv6006C_reg.h	3793;"	d
+GET_MTX_RESPFRM_INFO_DA	smac/hal/ssv6006c/ssv6006C_reg.h	3794;"	d
+GET_MTX_RESPFRM_INFO_DB	smac/hal/ssv6006c/ssv6006C_reg.h	3795;"	d
+GET_MTX_RESPFRM_INFO_DC	smac/hal/ssv6006c/ssv6006C_reg.h	3796;"	d
+GET_MTX_RESPFRM_INFO_DD	smac/hal/ssv6006c/ssv6006C_reg.h	3797;"	d
+GET_MTX_RESPFRM_INFO_DE	smac/hal/ssv6006c/ssv6006C_reg.h	3798;"	d
+GET_MTX_RESPFRM_INFO_DF	smac/hal/ssv6006c/ssv6006C_reg.h	3799;"	d
+GET_MTX_RESPFRM_INFO_EXCEPTION	smac/hal/ssv6006c/ssv6006C_reg.h	3760;"	d
+GET_MTX_RESPFRM_RATE_00	smac/hal/ssv6006c/ssv6006C_reg.h	3721;"	d
+GET_MTX_RESPFRM_RATE_01	smac/hal/ssv6006c/ssv6006C_reg.h	3722;"	d
+GET_MTX_RESPFRM_RATE_02	smac/hal/ssv6006c/ssv6006C_reg.h	3723;"	d
+GET_MTX_RESPFRM_RATE_03	smac/hal/ssv6006c/ssv6006C_reg.h	3724;"	d
+GET_MTX_RESPFRM_RATE_11	smac/hal/ssv6006c/ssv6006C_reg.h	3725;"	d
+GET_MTX_RESPFRM_RATE_12	smac/hal/ssv6006c/ssv6006C_reg.h	3726;"	d
+GET_MTX_RESPFRM_RATE_13	smac/hal/ssv6006c/ssv6006C_reg.h	3727;"	d
+GET_MTX_RESPFRM_RATE_90_B0	smac/hal/ssv6006c/ssv6006C_reg.h	3728;"	d
+GET_MTX_RESPFRM_RATE_91_B1	smac/hal/ssv6006c/ssv6006C_reg.h	3729;"	d
+GET_MTX_RESPFRM_RATE_92_B2	smac/hal/ssv6006c/ssv6006C_reg.h	3730;"	d
+GET_MTX_RESPFRM_RATE_93_B3	smac/hal/ssv6006c/ssv6006C_reg.h	3731;"	d
+GET_MTX_RESPFRM_RATE_94_B4	smac/hal/ssv6006c/ssv6006C_reg.h	3732;"	d
+GET_MTX_RESPFRM_RATE_95_B5	smac/hal/ssv6006c/ssv6006C_reg.h	3733;"	d
+GET_MTX_RESPFRM_RATE_96_B6	smac/hal/ssv6006c/ssv6006C_reg.h	3734;"	d
+GET_MTX_RESPFRM_RATE_97_B7	smac/hal/ssv6006c/ssv6006C_reg.h	3735;"	d
+GET_MTX_RESPFRM_RATE_C0_E0	smac/hal/ssv6006c/ssv6006C_reg.h	3736;"	d
+GET_MTX_RESPFRM_RATE_C1_E1	smac/hal/ssv6006c/ssv6006C_reg.h	3737;"	d
+GET_MTX_RESPFRM_RATE_C2_E2	smac/hal/ssv6006c/ssv6006C_reg.h	3738;"	d
+GET_MTX_RESPFRM_RATE_C3_E3	smac/hal/ssv6006c/ssv6006C_reg.h	3739;"	d
+GET_MTX_RESPFRM_RATE_C4_E4	smac/hal/ssv6006c/ssv6006C_reg.h	3740;"	d
+GET_MTX_RESPFRM_RATE_C5_E5	smac/hal/ssv6006c/ssv6006C_reg.h	3741;"	d
+GET_MTX_RESPFRM_RATE_C6_E6	smac/hal/ssv6006c/ssv6006C_reg.h	3742;"	d
+GET_MTX_RESPFRM_RATE_C7_E7	smac/hal/ssv6006c/ssv6006C_reg.h	3743;"	d
+GET_MTX_RESPFRM_RATE_D0_F0	smac/hal/ssv6006c/ssv6006C_reg.h	3744;"	d
+GET_MTX_RESPFRM_RATE_D1_F1	smac/hal/ssv6006c/ssv6006C_reg.h	3745;"	d
+GET_MTX_RESPFRM_RATE_D2_F2	smac/hal/ssv6006c/ssv6006C_reg.h	3746;"	d
+GET_MTX_RESPFRM_RATE_D3_F3	smac/hal/ssv6006c/ssv6006C_reg.h	3747;"	d
+GET_MTX_RESPFRM_RATE_D4_F4	smac/hal/ssv6006c/ssv6006C_reg.h	3748;"	d
+GET_MTX_RESPFRM_RATE_D5_F5	smac/hal/ssv6006c/ssv6006C_reg.h	3749;"	d
+GET_MTX_RESPFRM_RATE_D6_F6	smac/hal/ssv6006c/ssv6006C_reg.h	3750;"	d
+GET_MTX_RESPFRM_RATE_D7_F7	smac/hal/ssv6006c/ssv6006C_reg.h	3751;"	d
+GET_MTX_RESPFRM_RATE_D8_F8	smac/hal/ssv6006c/ssv6006C_reg.h	3752;"	d
+GET_MTX_RESPFRM_RATE_D9_F9	smac/hal/ssv6006c/ssv6006C_reg.h	3753;"	d
+GET_MTX_RESPFRM_RATE_DA_FA	smac/hal/ssv6006c/ssv6006C_reg.h	3754;"	d
+GET_MTX_RESPFRM_RATE_DB_FB	smac/hal/ssv6006c/ssv6006C_reg.h	3755;"	d
+GET_MTX_RESPFRM_RATE_DC_FC	smac/hal/ssv6006c/ssv6006C_reg.h	3756;"	d
+GET_MTX_RESPFRM_RATE_DD_FD	smac/hal/ssv6006c/ssv6006C_reg.h	3757;"	d
+GET_MTX_RESPFRM_RATE_DE_FE	smac/hal/ssv6006c/ssv6006C_reg.h	3758;"	d
+GET_MTX_RESPFRM_RATE_DF_FF	smac/hal/ssv6006c/ssv6006C_reg.h	3759;"	d
+GET_MTX_RESPFRM_RATE_EXCEPTION	smac/hal/ssv6006c/ssv6006C_reg.h	3720;"	d
+GET_MTX_RETRY	include/ssv6200_reg.h	3153;"	d
+GET_MTX_RETRY	smac/hal/ssv6006c/ssv6006C_reg.h	4001;"	d
+GET_MTX_RTS_FAIL	include/ssv6200_reg.h	3156;"	d
+GET_MTX_RTS_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	4004;"	d
+GET_MTX_RTS_SUCC	include/ssv6200_reg.h	3155;"	d
+GET_MTX_RTS_SUCC	smac/hal/ssv6006c/ssv6006C_reg.h	4003;"	d
+GET_MTX_SELFSTA_PS	smac/hal/ssv6006c/ssv6006C_reg.h	3499;"	d
+GET_MTX_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	3855;"	d
+GET_MTX_TIME_STAMP_AUTO_FILL	include/ssv6200_reg.h	2784;"	d
+GET_MTX_TIME_STAMP_AUTO_FILL	smac/hal/ssv6006c/ssv6006C_reg.h	3594;"	d
+GET_MTX_TSF_AUTO_BCN	include/ssv6200_reg.h	2769;"	d
+GET_MTX_TSF_AUTO_MISC	include/ssv6200_reg.h	2770;"	d
+GET_MTX_TSF_TIMER_EN	include/ssv6200_reg.h	2785;"	d
+GET_MTX_TSF_TIMER_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3596;"	d
+GET_MTX_TX_EN	include/ssv6200_reg.h	2808;"	d
+GET_MTX_WSID0_FRM	include/ssv6200_reg.h	3148;"	d
+GET_MTX_WSID0_FRM	smac/hal/ssv6006c/ssv6006C_reg.h	3996;"	d
+GET_MTX_WSID0_RETRY	include/ssv6200_reg.h	3149;"	d
+GET_MTX_WSID0_RETRY	smac/hal/ssv6006c/ssv6006C_reg.h	3997;"	d
+GET_MTX_WSID0_SUCC	include/ssv6200_reg.h	3147;"	d
+GET_MTX_WSID0_SUCC	smac/hal/ssv6006c/ssv6006C_reg.h	3995;"	d
+GET_MTX_WSID0_TOTAL	include/ssv6200_reg.h	3150;"	d
+GET_MTX_WSID0_TOTAL	smac/hal/ssv6006c/ssv6006C_reg.h	3998;"	d
+GET_MULTI_AMPDU_W_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3450;"	d
+GET_MUL_ANS0	include/ssv6200_reg.h	2542;"	d
+GET_MUL_ANS0	smac/hal/ssv6006c/ssv6006C_reg.h	3280;"	d
+GET_MUL_ANS1	include/ssv6200_reg.h	2543;"	d
+GET_MUL_ANS1	smac/hal/ssv6006c/ssv6006C_reg.h	3281;"	d
+GET_MUL_OP1	include/ssv6200_reg.h	2540;"	d
+GET_MUL_OP1	smac/hal/ssv6006c/ssv6006C_reg.h	3278;"	d
+GET_MUL_OP2	include/ssv6200_reg.h	2541;"	d
+GET_MUL_OP2	smac/hal/ssv6006c/ssv6006C_reg.h	3279;"	d
+GET_N10CFG_DEFAULT_IVB	smac/hal/ssv6006c/ssv6006C_reg.h	2477;"	d
+GET_N10_CORE_CURRENT_PC	smac/hal/ssv6006c/ssv6006C_reg.h	2416;"	d
+GET_N10_CORE_DEBUG_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	2419;"	d
+GET_N10_CORE_STANDBY_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	2418;"	d
+GET_N10_STANDBY	smac/hal/ssv6006c/ssv6006C_reg.h	2420;"	d
+GET_N10_STANDBY_REQ	smac/hal/ssv6006c/ssv6006C_reg.h	2417;"	d
+GET_N10_WAKEUP_OK	smac/hal/ssv6006c/ssv6006C_reg.h	2421;"	d
+GET_N10_WARM_RESET_N	smac/hal/ssv6006c/ssv6006C_reg.h	2463;"	d
+GET_NACK_FLAG_BUS	include/ssv6200_reg.h	4834;"	d
+GET_NAVCS_PHYCS_FALL_OFFSET_STEP	smac/hal/ssv6006c/ssv6006C_reg.h	3613;"	d
+GET_NEQ_MB_FLAG	include/ssv6200_reg.h	4890;"	d
+GET_NEQ_MB_ID_127_96	include/ssv6200_reg.h	4882;"	d
+GET_NEQ_MB_ID_31_0	include/ssv6200_reg.h	4879;"	d
+GET_NEQ_MB_ID_63_32	include/ssv6200_reg.h	4880;"	d
+GET_NEQ_MB_ID_95_64	include/ssv6200_reg.h	4881;"	d
+GET_NEQ_PKT_FLAG	include/ssv6200_reg.h	4889;"	d
+GET_NEQ_PKT_ID_127_96	include/ssv6200_reg.h	4886;"	d
+GET_NEQ_PKT_ID_31_0	include/ssv6200_reg.h	4883;"	d
+GET_NEQ_PKT_ID_63_32	include/ssv6200_reg.h	4884;"	d
+GET_NEQ_PKT_ID_95_64	include/ssv6200_reg.h	4885;"	d
+GET_NOHIT_RPASS_MD	include/ssv6200_reg.h	4800;"	d
+GET_NORMAL_ISO_ON1	smac/hal/ssv6006c/ssv6006C_reg.h	2498;"	d
+GET_NORMAL_ISO_ON2	smac/hal/ssv6006c/ssv6006C_reg.h	2499;"	d
+GET_NORMAL_ISO_ON3	smac/hal/ssv6006c/ssv6006C_reg.h	2500;"	d
+GET_NORMAL_PWR_ON1	smac/hal/ssv6006c/ssv6006C_reg.h	2492;"	d
+GET_NORMAL_PWR_ON2	smac/hal/ssv6006c/ssv6006C_reg.h	2493;"	d
+GET_NORMAL_PWR_ON3	smac/hal/ssv6006c/ssv6006C_reg.h	2494;"	d
+GET_NO_ALLOCATE_SEND_ERROR	include/ssv6200_reg.h	1962;"	d
+GET_NO_ALLOC_ERR	smac/hal/ssv6006c/ssv6006C_reg.h	3216;"	d
+GET_NO_PKT_BUF_REDUCTION	smac/hal/ssv6006c/ssv6006C_reg.h	3500;"	d
+GET_NO_REDUCE_PKT_PEERPS_AMPDUV1P2	smac/hal/ssv6006c/ssv6006C_reg.h	3503;"	d
+GET_NO_REDUCE_PKT_PEERPS_AMPDUV1P3	smac/hal/ssv6006c/ssv6006C_reg.h	3504;"	d
+GET_NO_REDUCE_PKT_PEERPS_MPDU	smac/hal/ssv6006c/ssv6006C_reg.h	3502;"	d
+GET_NO_REDUCE_TXALLFAIL_PKT	smac/hal/ssv6006c/ssv6006C_reg.h	3501;"	d
+GET_OP_MODE	include/ssv6200_reg.h	3087;"	d
+GET_OP_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	3919;"	d
+GET_OP_MODE1	smac/hal/ssv6006c/ssv6006C_reg.h	3944;"	d
+GET_OUT_1	include/ssv6200_reg.h	2137;"	d
+GET_OUT_1	smac/hal/ssv6006c/ssv6006C_reg.h	2847;"	d
+GET_OUT_2	include/ssv6200_reg.h	2138;"	d
+GET_OUT_2	smac/hal/ssv6006c/ssv6006C_reg.h	2848;"	d
+GET_OUT_QUEUE_FLUSH_ID	smac/hal/ssv6006c/ssv6006C_reg.h	8856;"	d
+GET_OUT_QUEUE_FLUSH_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	8857;"	d
+GET_OUT_QUEUE_FLUSH_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	8858;"	d
+GET_OVERRUN	smac/hal/ssv6006c/ssv6006C_reg.h	2881;"	d
+GET_OVERRUN_ERR	include/ssv6200_reg.h	2141;"	d
+GET_OVERRUN_ERR	smac/hal/ssv6006c/ssv6006C_reg.h	2852;"	d
+GET_PACKET_ERR	include/ssv6200_reg.h	4184;"	d
+GET_PAD11_IE	include/ssv6200_reg.h	1463;"	d
+GET_PAD11_OD	include/ssv6200_reg.h	1465;"	d
+GET_PAD11_SEL_I	include/ssv6200_reg.h	1464;"	d
+GET_PAD11_SEL_O	include/ssv6200_reg.h	1466;"	d
+GET_PAD15_DS	include/ssv6200_reg.h	1470;"	d
+GET_PAD15_IE	include/ssv6200_reg.h	1471;"	d
+GET_PAD15_OD	include/ssv6200_reg.h	1473;"	d
+GET_PAD15_OE	include/ssv6200_reg.h	1468;"	d
+GET_PAD15_PE	include/ssv6200_reg.h	1469;"	d
+GET_PAD15_SEL_I	include/ssv6200_reg.h	1472;"	d
+GET_PAD15_SEL_O	include/ssv6200_reg.h	1474;"	d
+GET_PAD16_DS	include/ssv6200_reg.h	1478;"	d
+GET_PAD16_IE	include/ssv6200_reg.h	1479;"	d
+GET_PAD16_OD	include/ssv6200_reg.h	1481;"	d
+GET_PAD16_OE	include/ssv6200_reg.h	1476;"	d
+GET_PAD16_PE	include/ssv6200_reg.h	1477;"	d
+GET_PAD16_SEL_I	include/ssv6200_reg.h	1480;"	d
+GET_PAD16_SEL_O	include/ssv6200_reg.h	1482;"	d
+GET_PAD17_DS	include/ssv6200_reg.h	1486;"	d
+GET_PAD17_IE	include/ssv6200_reg.h	1487;"	d
+GET_PAD17_OD	include/ssv6200_reg.h	1489;"	d
+GET_PAD17_OE	include/ssv6200_reg.h	1484;"	d
+GET_PAD17_PE	include/ssv6200_reg.h	1485;"	d
+GET_PAD17_SEL_I	include/ssv6200_reg.h	1488;"	d
+GET_PAD17_SEL_O	include/ssv6200_reg.h	1490;"	d
+GET_PAD18_DS	include/ssv6200_reg.h	1494;"	d
+GET_PAD18_IE	include/ssv6200_reg.h	1495;"	d
+GET_PAD18_OD	include/ssv6200_reg.h	1497;"	d
+GET_PAD18_OE	include/ssv6200_reg.h	1492;"	d
+GET_PAD18_PE	include/ssv6200_reg.h	1493;"	d
+GET_PAD18_SEL_I	include/ssv6200_reg.h	1496;"	d
+GET_PAD18_SEL_O	include/ssv6200_reg.h	1498;"	d
+GET_PAD19_DS	include/ssv6200_reg.h	1502;"	d
+GET_PAD19_IE	include/ssv6200_reg.h	1503;"	d
+GET_PAD19_OD	include/ssv6200_reg.h	1505;"	d
+GET_PAD19_OE	include/ssv6200_reg.h	1500;"	d
+GET_PAD19_PE	include/ssv6200_reg.h	1501;"	d
+GET_PAD19_SEL_I	include/ssv6200_reg.h	1504;"	d
+GET_PAD19_SEL_O	include/ssv6200_reg.h	1506;"	d
+GET_PAD20_DS	include/ssv6200_reg.h	1510;"	d
+GET_PAD20_IE	include/ssv6200_reg.h	1511;"	d
+GET_PAD20_OD	include/ssv6200_reg.h	1513;"	d
+GET_PAD20_OE	include/ssv6200_reg.h	1508;"	d
+GET_PAD20_PE	include/ssv6200_reg.h	1509;"	d
+GET_PAD20_SEL_I	include/ssv6200_reg.h	1512;"	d
+GET_PAD20_SEL_O	include/ssv6200_reg.h	1514;"	d
+GET_PAD21_DS	include/ssv6200_reg.h	1519;"	d
+GET_PAD21_IE	include/ssv6200_reg.h	1520;"	d
+GET_PAD21_OD	include/ssv6200_reg.h	1522;"	d
+GET_PAD21_OE	include/ssv6200_reg.h	1517;"	d
+GET_PAD21_PE	include/ssv6200_reg.h	1518;"	d
+GET_PAD21_SEL_I	include/ssv6200_reg.h	1521;"	d
+GET_PAD21_SEL_O	include/ssv6200_reg.h	1523;"	d
+GET_PAD22_DS	include/ssv6200_reg.h	1528;"	d
+GET_PAD22_IE	include/ssv6200_reg.h	1529;"	d
+GET_PAD22_OD	include/ssv6200_reg.h	1531;"	d
+GET_PAD22_OE	include/ssv6200_reg.h	1526;"	d
+GET_PAD22_PE	include/ssv6200_reg.h	1527;"	d
+GET_PAD22_SEL_I	include/ssv6200_reg.h	1530;"	d
+GET_PAD22_SEL_O	include/ssv6200_reg.h	1532;"	d
+GET_PAD22_SEL_OE	include/ssv6200_reg.h	1533;"	d
+GET_PAD231_DS	include/ssv6200_reg.h	1838;"	d
+GET_PAD231_IE	include/ssv6200_reg.h	1839;"	d
+GET_PAD231_OD	include/ssv6200_reg.h	1840;"	d
+GET_PAD231_OE	include/ssv6200_reg.h	1836;"	d
+GET_PAD231_PE	include/ssv6200_reg.h	1837;"	d
+GET_PAD24_DS	include/ssv6200_reg.h	1537;"	d
+GET_PAD24_IE	include/ssv6200_reg.h	1538;"	d
+GET_PAD24_OD	include/ssv6200_reg.h	1540;"	d
+GET_PAD24_OE	include/ssv6200_reg.h	1535;"	d
+GET_PAD24_PE	include/ssv6200_reg.h	1536;"	d
+GET_PAD24_SEL_I	include/ssv6200_reg.h	1539;"	d
+GET_PAD24_SEL_O	include/ssv6200_reg.h	1541;"	d
+GET_PAD25_DS	include/ssv6200_reg.h	1545;"	d
+GET_PAD25_IE	include/ssv6200_reg.h	1546;"	d
+GET_PAD25_OD	include/ssv6200_reg.h	1548;"	d
+GET_PAD25_OE	include/ssv6200_reg.h	1543;"	d
+GET_PAD25_PE	include/ssv6200_reg.h	1544;"	d
+GET_PAD25_SEL_I	include/ssv6200_reg.h	1547;"	d
+GET_PAD25_SEL_O	include/ssv6200_reg.h	1549;"	d
+GET_PAD25_SEL_OE	include/ssv6200_reg.h	1550;"	d
+GET_PAD27_DS	include/ssv6200_reg.h	1555;"	d
+GET_PAD27_IE	include/ssv6200_reg.h	1556;"	d
+GET_PAD27_OD	include/ssv6200_reg.h	1558;"	d
+GET_PAD27_OE	include/ssv6200_reg.h	1553;"	d
+GET_PAD27_PE	include/ssv6200_reg.h	1554;"	d
+GET_PAD27_SEL_I	include/ssv6200_reg.h	1557;"	d
+GET_PAD27_SEL_O	include/ssv6200_reg.h	1559;"	d
+GET_PAD28_DS	include/ssv6200_reg.h	1563;"	d
+GET_PAD28_IE	include/ssv6200_reg.h	1564;"	d
+GET_PAD28_OD	include/ssv6200_reg.h	1566;"	d
+GET_PAD28_OE	include/ssv6200_reg.h	1561;"	d
+GET_PAD28_PE	include/ssv6200_reg.h	1562;"	d
+GET_PAD28_SEL_I	include/ssv6200_reg.h	1565;"	d
+GET_PAD28_SEL_O	include/ssv6200_reg.h	1567;"	d
+GET_PAD28_SEL_OE	include/ssv6200_reg.h	1568;"	d
+GET_PAD29_DS	include/ssv6200_reg.h	1572;"	d
+GET_PAD29_IE	include/ssv6200_reg.h	1573;"	d
+GET_PAD29_OD	include/ssv6200_reg.h	1575;"	d
+GET_PAD29_OE	include/ssv6200_reg.h	1570;"	d
+GET_PAD29_PE	include/ssv6200_reg.h	1571;"	d
+GET_PAD29_SEL_I	include/ssv6200_reg.h	1574;"	d
+GET_PAD29_SEL_O	include/ssv6200_reg.h	1576;"	d
+GET_PAD30_DS	include/ssv6200_reg.h	1580;"	d
+GET_PAD30_IE	include/ssv6200_reg.h	1581;"	d
+GET_PAD30_OD	include/ssv6200_reg.h	1583;"	d
+GET_PAD30_OE	include/ssv6200_reg.h	1578;"	d
+GET_PAD30_PE	include/ssv6200_reg.h	1579;"	d
+GET_PAD30_SEL_I	include/ssv6200_reg.h	1582;"	d
+GET_PAD30_SEL_O	include/ssv6200_reg.h	1584;"	d
+GET_PAD31_DS	include/ssv6200_reg.h	1588;"	d
+GET_PAD31_IE	include/ssv6200_reg.h	1589;"	d
+GET_PAD31_OD	include/ssv6200_reg.h	1591;"	d
+GET_PAD31_OE	include/ssv6200_reg.h	1586;"	d
+GET_PAD31_PE	include/ssv6200_reg.h	1587;"	d
+GET_PAD31_SEL_I	include/ssv6200_reg.h	1590;"	d
+GET_PAD31_SEL_O	include/ssv6200_reg.h	1592;"	d
+GET_PAD32_DS	include/ssv6200_reg.h	1596;"	d
+GET_PAD32_IE	include/ssv6200_reg.h	1597;"	d
+GET_PAD32_OD	include/ssv6200_reg.h	1599;"	d
+GET_PAD32_OE	include/ssv6200_reg.h	1594;"	d
+GET_PAD32_PE	include/ssv6200_reg.h	1595;"	d
+GET_PAD32_SEL_I	include/ssv6200_reg.h	1598;"	d
+GET_PAD32_SEL_O	include/ssv6200_reg.h	1600;"	d
+GET_PAD33_DS	include/ssv6200_reg.h	1604;"	d
+GET_PAD33_IE	include/ssv6200_reg.h	1605;"	d
+GET_PAD33_OD	include/ssv6200_reg.h	1607;"	d
+GET_PAD33_OE	include/ssv6200_reg.h	1602;"	d
+GET_PAD33_PE	include/ssv6200_reg.h	1603;"	d
+GET_PAD33_SEL_I	include/ssv6200_reg.h	1606;"	d
+GET_PAD33_SEL_O	include/ssv6200_reg.h	1608;"	d
+GET_PAD34_DS	include/ssv6200_reg.h	1612;"	d
+GET_PAD34_IE	include/ssv6200_reg.h	1613;"	d
+GET_PAD34_OD	include/ssv6200_reg.h	1615;"	d
+GET_PAD34_OE	include/ssv6200_reg.h	1610;"	d
+GET_PAD34_PE	include/ssv6200_reg.h	1611;"	d
+GET_PAD34_SEL_I	include/ssv6200_reg.h	1614;"	d
+GET_PAD34_SEL_O	include/ssv6200_reg.h	1616;"	d
+GET_PAD42_DS	include/ssv6200_reg.h	1620;"	d
+GET_PAD42_IE	include/ssv6200_reg.h	1621;"	d
+GET_PAD42_OD	include/ssv6200_reg.h	1623;"	d
+GET_PAD42_OE	include/ssv6200_reg.h	1618;"	d
+GET_PAD42_PE	include/ssv6200_reg.h	1619;"	d
+GET_PAD42_SEL_I	include/ssv6200_reg.h	1622;"	d
+GET_PAD42_SEL_O	include/ssv6200_reg.h	1624;"	d
+GET_PAD43_DS	include/ssv6200_reg.h	1628;"	d
+GET_PAD43_IE	include/ssv6200_reg.h	1629;"	d
+GET_PAD43_OD	include/ssv6200_reg.h	1631;"	d
+GET_PAD43_OE	include/ssv6200_reg.h	1626;"	d
+GET_PAD43_PE	include/ssv6200_reg.h	1627;"	d
+GET_PAD43_SEL_I	include/ssv6200_reg.h	1630;"	d
+GET_PAD43_SEL_O	include/ssv6200_reg.h	1632;"	d
+GET_PAD44_DS	include/ssv6200_reg.h	1636;"	d
+GET_PAD44_IE	include/ssv6200_reg.h	1637;"	d
+GET_PAD44_OD	include/ssv6200_reg.h	1639;"	d
+GET_PAD44_OE	include/ssv6200_reg.h	1634;"	d
+GET_PAD44_PE	include/ssv6200_reg.h	1635;"	d
+GET_PAD44_SEL_I	include/ssv6200_reg.h	1638;"	d
+GET_PAD44_SEL_O	include/ssv6200_reg.h	1640;"	d
+GET_PAD45_DS	include/ssv6200_reg.h	1644;"	d
+GET_PAD45_IE	include/ssv6200_reg.h	1645;"	d
+GET_PAD45_OD	include/ssv6200_reg.h	1647;"	d
+GET_PAD45_OE	include/ssv6200_reg.h	1642;"	d
+GET_PAD45_PE	include/ssv6200_reg.h	1643;"	d
+GET_PAD45_SEL_I	include/ssv6200_reg.h	1646;"	d
+GET_PAD45_SEL_O	include/ssv6200_reg.h	1648;"	d
+GET_PAD46_DS	include/ssv6200_reg.h	1652;"	d
+GET_PAD46_IE	include/ssv6200_reg.h	1653;"	d
+GET_PAD46_OD	include/ssv6200_reg.h	1655;"	d
+GET_PAD46_OE	include/ssv6200_reg.h	1650;"	d
+GET_PAD46_PE	include/ssv6200_reg.h	1651;"	d
+GET_PAD46_SEL_I	include/ssv6200_reg.h	1654;"	d
+GET_PAD46_SEL_O	include/ssv6200_reg.h	1656;"	d
+GET_PAD47_DS	include/ssv6200_reg.h	1660;"	d
+GET_PAD47_OD	include/ssv6200_reg.h	1662;"	d
+GET_PAD47_OE	include/ssv6200_reg.h	1658;"	d
+GET_PAD47_PE	include/ssv6200_reg.h	1659;"	d
+GET_PAD47_SEL_I	include/ssv6200_reg.h	1661;"	d
+GET_PAD47_SEL_O	include/ssv6200_reg.h	1663;"	d
+GET_PAD47_SEL_OE	include/ssv6200_reg.h	1664;"	d
+GET_PAD48_DS	include/ssv6200_reg.h	1668;"	d
+GET_PAD48_IE	include/ssv6200_reg.h	1669;"	d
+GET_PAD48_OD	include/ssv6200_reg.h	1671;"	d
+GET_PAD48_OE	include/ssv6200_reg.h	1666;"	d
+GET_PAD48_PE	include/ssv6200_reg.h	1667;"	d
+GET_PAD48_PE_SEL	include/ssv6200_reg.h	1672;"	d
+GET_PAD48_SEL_I	include/ssv6200_reg.h	1670;"	d
+GET_PAD48_SEL_O	include/ssv6200_reg.h	1673;"	d
+GET_PAD48_SEL_OE	include/ssv6200_reg.h	1674;"	d
+GET_PAD49_DS	include/ssv6200_reg.h	1678;"	d
+GET_PAD49_IE	include/ssv6200_reg.h	1679;"	d
+GET_PAD49_OD	include/ssv6200_reg.h	1681;"	d
+GET_PAD49_OE	include/ssv6200_reg.h	1676;"	d
+GET_PAD49_PE	include/ssv6200_reg.h	1677;"	d
+GET_PAD49_SEL_I	include/ssv6200_reg.h	1680;"	d
+GET_PAD49_SEL_O	include/ssv6200_reg.h	1682;"	d
+GET_PAD49_SEL_OE	include/ssv6200_reg.h	1683;"	d
+GET_PAD50_DS	include/ssv6200_reg.h	1687;"	d
+GET_PAD50_IE	include/ssv6200_reg.h	1688;"	d
+GET_PAD50_OD	include/ssv6200_reg.h	1690;"	d
+GET_PAD50_OE	include/ssv6200_reg.h	1685;"	d
+GET_PAD50_PE	include/ssv6200_reg.h	1686;"	d
+GET_PAD50_SEL_I	include/ssv6200_reg.h	1689;"	d
+GET_PAD50_SEL_O	include/ssv6200_reg.h	1691;"	d
+GET_PAD50_SEL_OE	include/ssv6200_reg.h	1692;"	d
+GET_PAD51_DS	include/ssv6200_reg.h	1696;"	d
+GET_PAD51_IE	include/ssv6200_reg.h	1697;"	d
+GET_PAD51_OD	include/ssv6200_reg.h	1699;"	d
+GET_PAD51_OE	include/ssv6200_reg.h	1694;"	d
+GET_PAD51_PE	include/ssv6200_reg.h	1695;"	d
+GET_PAD51_SEL_I	include/ssv6200_reg.h	1698;"	d
+GET_PAD51_SEL_O	include/ssv6200_reg.h	1700;"	d
+GET_PAD51_SEL_OE	include/ssv6200_reg.h	1701;"	d
+GET_PAD52_DS	include/ssv6200_reg.h	1705;"	d
+GET_PAD52_OD	include/ssv6200_reg.h	1707;"	d
+GET_PAD52_OE	include/ssv6200_reg.h	1703;"	d
+GET_PAD52_PE	include/ssv6200_reg.h	1704;"	d
+GET_PAD52_SEL_I	include/ssv6200_reg.h	1706;"	d
+GET_PAD52_SEL_O	include/ssv6200_reg.h	1708;"	d
+GET_PAD52_SEL_OE	include/ssv6200_reg.h	1709;"	d
+GET_PAD53_DS	include/ssv6200_reg.h	1713;"	d
+GET_PAD53_IE	include/ssv6200_reg.h	1714;"	d
+GET_PAD53_OD	include/ssv6200_reg.h	1716;"	d
+GET_PAD53_OE	include/ssv6200_reg.h	1711;"	d
+GET_PAD53_PE	include/ssv6200_reg.h	1712;"	d
+GET_PAD53_SEL_I	include/ssv6200_reg.h	1715;"	d
+GET_PAD53_SEL_O	include/ssv6200_reg.h	1717;"	d
+GET_PAD54_DS	include/ssv6200_reg.h	1721;"	d
+GET_PAD54_OD	include/ssv6200_reg.h	1722;"	d
+GET_PAD54_OE	include/ssv6200_reg.h	1719;"	d
+GET_PAD54_PE	include/ssv6200_reg.h	1720;"	d
+GET_PAD54_SEL_O	include/ssv6200_reg.h	1723;"	d
+GET_PAD56_DS	include/ssv6200_reg.h	1726;"	d
+GET_PAD56_OD	include/ssv6200_reg.h	1728;"	d
+GET_PAD56_PE	include/ssv6200_reg.h	1725;"	d
+GET_PAD56_SEL_I	include/ssv6200_reg.h	1727;"	d
+GET_PAD57_DS	include/ssv6200_reg.h	1732;"	d
+GET_PAD57_IE	include/ssv6200_reg.h	1733;"	d
+GET_PAD57_OD	include/ssv6200_reg.h	1735;"	d
+GET_PAD57_OE	include/ssv6200_reg.h	1730;"	d
+GET_PAD57_PE	include/ssv6200_reg.h	1731;"	d
+GET_PAD57_SEL_I	include/ssv6200_reg.h	1734;"	d
+GET_PAD57_SEL_O	include/ssv6200_reg.h	1736;"	d
+GET_PAD57_SEL_OE	include/ssv6200_reg.h	1737;"	d
+GET_PAD58_DS	include/ssv6200_reg.h	1741;"	d
+GET_PAD58_IE	include/ssv6200_reg.h	1742;"	d
+GET_PAD58_OD	include/ssv6200_reg.h	1744;"	d
+GET_PAD58_OE	include/ssv6200_reg.h	1739;"	d
+GET_PAD58_PE	include/ssv6200_reg.h	1740;"	d
+GET_PAD58_SEL_I	include/ssv6200_reg.h	1743;"	d
+GET_PAD58_SEL_O	include/ssv6200_reg.h	1745;"	d
+GET_PAD59_DS	include/ssv6200_reg.h	1749;"	d
+GET_PAD59_IE	include/ssv6200_reg.h	1750;"	d
+GET_PAD59_OD	include/ssv6200_reg.h	1752;"	d
+GET_PAD59_OE	include/ssv6200_reg.h	1747;"	d
+GET_PAD59_PE	include/ssv6200_reg.h	1748;"	d
+GET_PAD59_SEL_I	include/ssv6200_reg.h	1751;"	d
+GET_PAD59_SEL_O	include/ssv6200_reg.h	1753;"	d
+GET_PAD60_DS	include/ssv6200_reg.h	1757;"	d
+GET_PAD60_IE	include/ssv6200_reg.h	1758;"	d
+GET_PAD60_OD	include/ssv6200_reg.h	1760;"	d
+GET_PAD60_OE	include/ssv6200_reg.h	1755;"	d
+GET_PAD60_PE	include/ssv6200_reg.h	1756;"	d
+GET_PAD60_SEL_I	include/ssv6200_reg.h	1759;"	d
+GET_PAD60_SEL_O	include/ssv6200_reg.h	1761;"	d
+GET_PAD61_DS	include/ssv6200_reg.h	1765;"	d
+GET_PAD61_IE	include/ssv6200_reg.h	1766;"	d
+GET_PAD61_OD	include/ssv6200_reg.h	1768;"	d
+GET_PAD61_OE	include/ssv6200_reg.h	1763;"	d
+GET_PAD61_PE	include/ssv6200_reg.h	1764;"	d
+GET_PAD61_SEL_I	include/ssv6200_reg.h	1767;"	d
+GET_PAD61_SEL_O	include/ssv6200_reg.h	1769;"	d
+GET_PAD62_DS	include/ssv6200_reg.h	1773;"	d
+GET_PAD62_IE	include/ssv6200_reg.h	1774;"	d
+GET_PAD62_OD	include/ssv6200_reg.h	1776;"	d
+GET_PAD62_OE	include/ssv6200_reg.h	1771;"	d
+GET_PAD62_PE	include/ssv6200_reg.h	1772;"	d
+GET_PAD62_SEL_I	include/ssv6200_reg.h	1775;"	d
+GET_PAD62_SEL_O	include/ssv6200_reg.h	1777;"	d
+GET_PAD64_DS	include/ssv6200_reg.h	1781;"	d
+GET_PAD64_IE	include/ssv6200_reg.h	1782;"	d
+GET_PAD64_OD	include/ssv6200_reg.h	1784;"	d
+GET_PAD64_OE	include/ssv6200_reg.h	1779;"	d
+GET_PAD64_PE	include/ssv6200_reg.h	1780;"	d
+GET_PAD64_SEL_I	include/ssv6200_reg.h	1783;"	d
+GET_PAD64_SEL_O	include/ssv6200_reg.h	1785;"	d
+GET_PAD64_SEL_OE	include/ssv6200_reg.h	1786;"	d
+GET_PAD65_DS	include/ssv6200_reg.h	1790;"	d
+GET_PAD65_IE	include/ssv6200_reg.h	1791;"	d
+GET_PAD65_OD	include/ssv6200_reg.h	1793;"	d
+GET_PAD65_OE	include/ssv6200_reg.h	1788;"	d
+GET_PAD65_PE	include/ssv6200_reg.h	1789;"	d
+GET_PAD65_SEL_I	include/ssv6200_reg.h	1792;"	d
+GET_PAD65_SEL_O	include/ssv6200_reg.h	1794;"	d
+GET_PAD66_DS	include/ssv6200_reg.h	1798;"	d
+GET_PAD66_IE	include/ssv6200_reg.h	1799;"	d
+GET_PAD66_OD	include/ssv6200_reg.h	1801;"	d
+GET_PAD66_OE	include/ssv6200_reg.h	1796;"	d
+GET_PAD66_PE	include/ssv6200_reg.h	1797;"	d
+GET_PAD66_SEL_I	include/ssv6200_reg.h	1800;"	d
+GET_PAD66_SEL_O	include/ssv6200_reg.h	1802;"	d
+GET_PAD67_DS	include/ssv6200_reg.h	1813;"	d
+GET_PAD67_IE	include/ssv6200_reg.h	1814;"	d
+GET_PAD67_OD	include/ssv6200_reg.h	1816;"	d
+GET_PAD67_OE	include/ssv6200_reg.h	1811;"	d
+GET_PAD67_PE	include/ssv6200_reg.h	1812;"	d
+GET_PAD67_SEL_I	include/ssv6200_reg.h	1815;"	d
+GET_PAD67_SEL_O	include/ssv6200_reg.h	1817;"	d
+GET_PAD68_DS	include/ssv6200_reg.h	1806;"	d
+GET_PAD68_IE	include/ssv6200_reg.h	1807;"	d
+GET_PAD68_OD	include/ssv6200_reg.h	1808;"	d
+GET_PAD68_OE	include/ssv6200_reg.h	1804;"	d
+GET_PAD68_PE	include/ssv6200_reg.h	1805;"	d
+GET_PAD68_SEL_O	include/ssv6200_reg.h	1809;"	d
+GET_PAD69_DS	include/ssv6200_reg.h	1821;"	d
+GET_PAD69_IE	include/ssv6200_reg.h	1822;"	d
+GET_PAD69_OD	include/ssv6200_reg.h	1824;"	d
+GET_PAD69_OE	include/ssv6200_reg.h	1819;"	d
+GET_PAD69_PE	include/ssv6200_reg.h	1820;"	d
+GET_PAD69_SEL_I	include/ssv6200_reg.h	1823;"	d
+GET_PAD69_SEL_O	include/ssv6200_reg.h	1825;"	d
+GET_PAD6_IE	include/ssv6200_reg.h	1436;"	d
+GET_PAD6_OD	include/ssv6200_reg.h	1438;"	d
+GET_PAD6_SEL_I	include/ssv6200_reg.h	1437;"	d
+GET_PAD6_SEL_O	include/ssv6200_reg.h	1439;"	d
+GET_PAD70_DS	include/ssv6200_reg.h	1830;"	d
+GET_PAD70_IE	include/ssv6200_reg.h	1831;"	d
+GET_PAD70_OD	include/ssv6200_reg.h	1833;"	d
+GET_PAD70_OE	include/ssv6200_reg.h	1828;"	d
+GET_PAD70_PE	include/ssv6200_reg.h	1829;"	d
+GET_PAD70_SEL_I	include/ssv6200_reg.h	1832;"	d
+GET_PAD70_SEL_O	include/ssv6200_reg.h	1834;"	d
+GET_PAD7_IE	include/ssv6200_reg.h	1443;"	d
+GET_PAD7_OD	include/ssv6200_reg.h	1445;"	d
+GET_PAD7_SEL_I	include/ssv6200_reg.h	1444;"	d
+GET_PAD7_SEL_O	include/ssv6200_reg.h	1446;"	d
+GET_PAD8_IE	include/ssv6200_reg.h	1450;"	d
+GET_PAD8_OD	include/ssv6200_reg.h	1452;"	d
+GET_PAD8_SEL_I	include/ssv6200_reg.h	1451;"	d
+GET_PAD9_IE	include/ssv6200_reg.h	1456;"	d
+GET_PAD9_OD	include/ssv6200_reg.h	1458;"	d
+GET_PAD9_SEL_I	include/ssv6200_reg.h	1457;"	d
+GET_PAD9_SEL_O	include/ssv6200_reg.h	1459;"	d
+GET_PAIR_SCRT	include/ssv6200_reg.h	3102;"	d
+GET_PAIR_SCRT	smac/hal/ssv6006c/ssv6006C_reg.h	3935;"	d
+GET_PARALLEL_DR	include/ssv6200_reg.h	1336;"	d
+GET_PARA_ALC_RLS	include/ssv6200_reg.h	4836;"	d
+GET_PARITY	smac/hal/ssv6006c/ssv6006C_reg.h	2884;"	d
+GET_PARITY_EN	include/ssv6200_reg.h	2130;"	d
+GET_PARITY_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2840;"	d
+GET_PARITY_ERR	include/ssv6200_reg.h	2142;"	d
+GET_PARITY_ERR	smac/hal/ssv6006c/ssv6006C_reg.h	2853;"	d
+GET_PATCH00_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	2511;"	d
+GET_PATCH00_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	2512;"	d
+GET_PATCH00_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2510;"	d
+GET_PATCH01_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	2514;"	d
+GET_PATCH01_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	2515;"	d
+GET_PATCH01_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2513;"	d
+GET_PATCH02_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	3129;"	d
+GET_PATCH02_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	3130;"	d
+GET_PATCH02_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3128;"	d
+GET_PATCH03_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	3132;"	d
+GET_PATCH03_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	3133;"	d
+GET_PATCH03_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3131;"	d
+GET_PATCH04_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	3135;"	d
+GET_PATCH04_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	3136;"	d
+GET_PATCH04_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3134;"	d
+GET_PATCH05_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	3138;"	d
+GET_PATCH05_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	3139;"	d
+GET_PATCH05_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3137;"	d
+GET_PATCH06_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	3141;"	d
+GET_PATCH06_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	3142;"	d
+GET_PATCH06_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3140;"	d
+GET_PATCH07_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	3144;"	d
+GET_PATCH07_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	3145;"	d
+GET_PATCH07_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3143;"	d
+GET_PATCH08_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	3147;"	d
+GET_PATCH08_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	3148;"	d
+GET_PATCH08_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3146;"	d
+GET_PATCH09_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	3150;"	d
+GET_PATCH09_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	3151;"	d
+GET_PATCH09_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3149;"	d
+GET_PATCH10_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	3153;"	d
+GET_PATCH10_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	3154;"	d
+GET_PATCH10_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3152;"	d
+GET_PATCH11_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	3156;"	d
+GET_PATCH11_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	3157;"	d
+GET_PATCH11_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3155;"	d
+GET_PATCH12_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	3159;"	d
+GET_PATCH12_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	3160;"	d
+GET_PATCH12_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3158;"	d
+GET_PATCH13_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	3162;"	d
+GET_PATCH13_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	3163;"	d
+GET_PATCH13_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3161;"	d
+GET_PATCH14_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	3165;"	d
+GET_PATCH14_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	3166;"	d
+GET_PATCH14_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3164;"	d
+GET_PATCH15_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	3168;"	d
+GET_PATCH15_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	3169;"	d
+GET_PATCH15_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3167;"	d
+GET_PBUS_SWP	include/ssv6200_reg.h	2408;"	d
+GET_PB_OFFSET	include/ssv6200_reg.h	3090;"	d
+GET_PB_OFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	3922;"	d
+GET_PEERPS_REJECT_ENABLE	smac/hal/ssv6006c/ssv6006C_reg.h	3255;"	d
+GET_PEER_HT_MODE0	include/ssv6200_reg.h	2924;"	d
+GET_PEER_HT_MODE0	smac/hal/ssv6006c/ssv6006C_reg.h	3803;"	d
+GET_PEER_HT_MODE1	include/ssv6200_reg.h	2946;"	d
+GET_PEER_HT_MODE1	smac/hal/ssv6006c/ssv6006C_reg.h	3825;"	d
+GET_PEER_HT_MODE2	smac/hal/ssv6006c/ssv6006C_reg.h	4058;"	d
+GET_PEER_HT_MODE3	smac/hal/ssv6006c/ssv6006C_reg.h	4080;"	d
+GET_PEER_HT_MODE4	smac/hal/ssv6006c/ssv6006C_reg.h	4102;"	d
+GET_PEER_HT_MODE5	smac/hal/ssv6006c/ssv6006C_reg.h	4124;"	d
+GET_PEER_HT_MODE6	smac/hal/ssv6006c/ssv6006C_reg.h	4146;"	d
+GET_PEER_HT_MODE7	smac/hal/ssv6006c/ssv6006C_reg.h	4168;"	d
+GET_PEER_MAC0_31_0	include/ssv6200_reg.h	2925;"	d
+GET_PEER_MAC0_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	3804;"	d
+GET_PEER_MAC0_47_32	include/ssv6200_reg.h	2926;"	d
+GET_PEER_MAC0_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	3805;"	d
+GET_PEER_MAC1_31_0	include/ssv6200_reg.h	2947;"	d
+GET_PEER_MAC1_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	3826;"	d
+GET_PEER_MAC1_47_32	include/ssv6200_reg.h	2948;"	d
+GET_PEER_MAC1_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	3827;"	d
+GET_PEER_MAC2_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	4059;"	d
+GET_PEER_MAC2_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	4060;"	d
+GET_PEER_MAC3_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	4081;"	d
+GET_PEER_MAC3_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	4082;"	d
+GET_PEER_MAC4_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	4103;"	d
+GET_PEER_MAC4_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	4104;"	d
+GET_PEER_MAC5_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	4125;"	d
+GET_PEER_MAC5_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	4126;"	d
+GET_PEER_MAC6_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	4147;"	d
+GET_PEER_MAC6_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	4148;"	d
+GET_PEER_MAC7_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	4169;"	d
+GET_PEER_MAC7_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	4170;"	d
+GET_PEER_OP_MODE0	include/ssv6200_reg.h	2923;"	d
+GET_PEER_OP_MODE0	smac/hal/ssv6006c/ssv6006C_reg.h	3802;"	d
+GET_PEER_OP_MODE1	include/ssv6200_reg.h	2945;"	d
+GET_PEER_OP_MODE1	smac/hal/ssv6006c/ssv6006C_reg.h	3824;"	d
+GET_PEER_OP_MODE2	smac/hal/ssv6006c/ssv6006C_reg.h	4057;"	d
+GET_PEER_OP_MODE3	smac/hal/ssv6006c/ssv6006C_reg.h	4079;"	d
+GET_PEER_OP_MODE4	smac/hal/ssv6006c/ssv6006C_reg.h	4101;"	d
+GET_PEER_OP_MODE5	smac/hal/ssv6006c/ssv6006C_reg.h	4123;"	d
+GET_PEER_OP_MODE6	smac/hal/ssv6006c/ssv6006C_reg.h	4145;"	d
+GET_PEER_OP_MODE7	smac/hal/ssv6006c/ssv6006C_reg.h	4167;"	d
+GET_PEER_QOS_EN0	include/ssv6200_reg.h	2922;"	d
+GET_PEER_QOS_EN0	smac/hal/ssv6006c/ssv6006C_reg.h	3801;"	d
+GET_PEER_QOS_EN1	include/ssv6200_reg.h	2944;"	d
+GET_PEER_QOS_EN1	smac/hal/ssv6006c/ssv6006C_reg.h	3823;"	d
+GET_PEER_QOS_EN2	smac/hal/ssv6006c/ssv6006C_reg.h	4056;"	d
+GET_PEER_QOS_EN3	smac/hal/ssv6006c/ssv6006C_reg.h	4078;"	d
+GET_PEER_QOS_EN4	smac/hal/ssv6006c/ssv6006C_reg.h	4100;"	d
+GET_PEER_QOS_EN5	smac/hal/ssv6006c/ssv6006C_reg.h	4122;"	d
+GET_PEER_QOS_EN6	smac/hal/ssv6006c/ssv6006C_reg.h	4144;"	d
+GET_PEER_QOS_EN7	smac/hal/ssv6006c/ssv6006C_reg.h	4166;"	d
+GET_PERI_GPI_1_0	include/ssv6200_reg.h	2250;"	d
+GET_PERI_GPI_2	include/ssv6200_reg.h	2248;"	d
+GET_PERI_GPI_SD_1_0	include/ssv6200_reg.h	2319;"	d
+GET_PERI_GPI_SD_2	include/ssv6200_reg.h	2317;"	d
+GET_PERI_MAC_ALL_RESET	include/ssv6200_reg.h	1943;"	d
+GET_PERI_MAC_ALL_RESET	smac/hal/ssv6006c/ssv6006C_reg.h	2701;"	d
+GET_PERI_RTC	include/ssv6200_reg.h	2245;"	d
+GET_PERI_RTC_SD	include/ssv6200_reg.h	2314;"	d
+GET_PG_TAG_127_96	smac/hal/ssv6006c/ssv6006C_reg.h	9066;"	d
+GET_PG_TAG_159_128	smac/hal/ssv6006c/ssv6006C_reg.h	9067;"	d
+GET_PG_TAG_191_160	smac/hal/ssv6006c/ssv6006C_reg.h	9068;"	d
+GET_PG_TAG_223_192	smac/hal/ssv6006c/ssv6006C_reg.h	9069;"	d
+GET_PG_TAG_255_224	smac/hal/ssv6006c/ssv6006C_reg.h	9070;"	d
+GET_PG_TAG_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	9063;"	d
+GET_PG_TAG_63_32	smac/hal/ssv6006c/ssv6006C_reg.h	9064;"	d
+GET_PG_TAG_95_64	smac/hal/ssv6006c/ssv6006C_reg.h	9065;"	d
+GET_PHYTXSTART_NCYCLE	smac/hal/ssv6006c/ssv6006C_reg.h	3615;"	d
+GET_PHY_IQ_LOG_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2407;"	d
+GET_PHY_MODE	include/ssv6200_reg.h	2550;"	d
+GET_PHY_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	3288;"	d
+GET_PIN_40_OR_56_ID	include/ssv6200_reg.h	1841;"	d
+GET_PKTBUF_FULL	include/ssv6200_reg.h	4860;"	d
+GET_PKTBUF_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	9061;"	d
+GET_PKTID	smac/hal/ssv6006c/ssv6006C_reg.h	8733;"	d
+GET_PKTID_ALT	smac/hal/ssv6006c/ssv6006C_reg.h	8779;"	d
+GET_PKT_IDTBL_127_96	include/ssv6200_reg.h	4874;"	d
+GET_PKT_IDTBL_31_0	include/ssv6200_reg.h	4871;"	d
+GET_PKT_IDTBL_63_32	include/ssv6200_reg.h	4872;"	d
+GET_PKT_IDTBL_95_64	include/ssv6200_reg.h	4873;"	d
+GET_PKT_REQ_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	9062;"	d
+GET_PLF_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	2365;"	d
+GET_PMUINT_WAKE_SEL	include/ssv6200_reg.h	1863;"	d
+GET_PMU_ENTER_SLEEP_MODE	include/ssv6200_reg.h	2446;"	d
+GET_PMU_WAKE_TRIG_EVENT	include/ssv6200_reg.h	2444;"	d
+GET_POSTMASK_TYPHOST_INT_MAP	smac/hal/ssv6006c/ssv6006C_reg.h	3028;"	d
+GET_POSTMASK_TYPHOST_INT_MAP_02	smac/hal/ssv6006c/ssv6006C_reg.h	3019;"	d
+GET_POSTMASK_TYPHOST_INT_MAP_15	smac/hal/ssv6006c/ssv6006C_reg.h	3022;"	d
+GET_POSTMASK_TYPHOST_INT_MAP_31	smac/hal/ssv6006c/ssv6006C_reg.h	3025;"	d
+GET_POSTMASK_TYPMCU_INT_MAP	smac/hal/ssv6006c/ssv6006C_reg.h	3041;"	d
+GET_POSTMASK_TYPMCU_INT_MAP_02	smac/hal/ssv6006c/ssv6006C_reg.h	3032;"	d
+GET_POSTMASK_TYPMCU_INT_MAP_15	smac/hal/ssv6006c/ssv6006C_reg.h	3035;"	d
+GET_POSTMASK_TYPMCU_INT_MAP_31	smac/hal/ssv6006c/ssv6006C_reg.h	3038;"	d
+GET_PREDE_BT_TX	smac/hal/ssv6006c/ssv6006C_reg.h	3978;"	d
+GET_PREFETCH_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2963;"	d
+GET_PRESCALER_US	smac/hal/ssv6006c/ssv6006C_reg.h	2506;"	d
+GET_PRESCALER_USTIMER	include/ssv6200_reg.h	1372;"	d
+GET_PRIHWID	smac/hal/ssv6006c/ssv6006C_reg.h	8737;"	d
+GET_PRIMARY_EDCA	smac/dev.h	201;"	d
+GET_PRIPKTID	smac/hal/ssv6006c/ssv6006C_reg.h	8736;"	d
+GET_PRI_HW_PKTID	include/ssv6200_reg.h	3546;"	d
+GET_PRO_VER	include/ssv6200_reg.h	2479;"	d
+GET_PRO_VER	smac/hal/ssv6006c/ssv6006C_reg.h	3178;"	d
+GET_PSEUDO	include/ssv6200_reg.h	2533;"	d
+GET_PSEUDO	smac/hal/ssv6006c/ssv6006C_reg.h	3271;"	d
+GET_PS_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3449;"	d
+GET_PWM_ALWAYSON_0	smac/hal/ssv6006c/ssv6006C_reg.h	2574;"	d
+GET_PWM_ALWAYSON_1	smac/hal/ssv6006c/ssv6006C_reg.h	2581;"	d
+GET_PWM_ALWAYSON_2	smac/hal/ssv6006c/ssv6006C_reg.h	2588;"	d
+GET_PWM_ALWAYSON_3	smac/hal/ssv6006c/ssv6006C_reg.h	2595;"	d
+GET_PWM_ALWAYSON_4	smac/hal/ssv6006c/ssv6006C_reg.h	2602;"	d
+GET_PWM_ALWAYSON_A	include/ssv6200_reg.h	1361;"	d
+GET_PWM_ALWAYSON_B	include/ssv6200_reg.h	1367;"	d
+GET_PWM_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2401;"	d
+GET_PWM_ENABLE_0	smac/hal/ssv6006c/ssv6006C_reg.h	2576;"	d
+GET_PWM_ENABLE_1	smac/hal/ssv6006c/ssv6006C_reg.h	2583;"	d
+GET_PWM_ENABLE_2	smac/hal/ssv6006c/ssv6006C_reg.h	2590;"	d
+GET_PWM_ENABLE_3	smac/hal/ssv6006c/ssv6006C_reg.h	2597;"	d
+GET_PWM_ENABLE_4	smac/hal/ssv6006c/ssv6006C_reg.h	2604;"	d
+GET_PWM_ENABLE_A	include/ssv6200_reg.h	1363;"	d
+GET_PWM_ENABLE_B	include/ssv6200_reg.h	1369;"	d
+GET_PWM_INI_VALUE_N_A	include/ssv6200_reg.h	1359;"	d
+GET_PWM_INI_VALUE_N_B	include/ssv6200_reg.h	1365;"	d
+GET_PWM_INI_VALUE_PERIOD_0	smac/hal/ssv6006c/ssv6006C_reg.h	2577;"	d
+GET_PWM_INI_VALUE_PERIOD_1	smac/hal/ssv6006c/ssv6006C_reg.h	2584;"	d
+GET_PWM_INI_VALUE_PERIOD_2	smac/hal/ssv6006c/ssv6006C_reg.h	2591;"	d
+GET_PWM_INI_VALUE_PERIOD_3	smac/hal/ssv6006c/ssv6006C_reg.h	2598;"	d
+GET_PWM_INI_VALUE_PERIOD_4	smac/hal/ssv6006c/ssv6006C_reg.h	2605;"	d
+GET_PWM_INI_VALUE_P_0	smac/hal/ssv6006c/ssv6006C_reg.h	2578;"	d
+GET_PWM_INI_VALUE_P_1	smac/hal/ssv6006c/ssv6006C_reg.h	2585;"	d
+GET_PWM_INI_VALUE_P_2	smac/hal/ssv6006c/ssv6006C_reg.h	2592;"	d
+GET_PWM_INI_VALUE_P_3	smac/hal/ssv6006c/ssv6006C_reg.h	2599;"	d
+GET_PWM_INI_VALUE_P_4	smac/hal/ssv6006c/ssv6006C_reg.h	2606;"	d
+GET_PWM_INI_VALUE_P_A	include/ssv6200_reg.h	1358;"	d
+GET_PWM_INI_VALUE_P_B	include/ssv6200_reg.h	1364;"	d
+GET_PWM_INVERT_0	smac/hal/ssv6006c/ssv6006C_reg.h	2575;"	d
+GET_PWM_INVERT_1	smac/hal/ssv6006c/ssv6006C_reg.h	2582;"	d
+GET_PWM_INVERT_2	smac/hal/ssv6006c/ssv6006C_reg.h	2589;"	d
+GET_PWM_INVERT_3	smac/hal/ssv6006c/ssv6006C_reg.h	2596;"	d
+GET_PWM_INVERT_4	smac/hal/ssv6006c/ssv6006C_reg.h	2603;"	d
+GET_PWM_INVERT_A	include/ssv6200_reg.h	1362;"	d
+GET_PWM_INVERT_B	include/ssv6200_reg.h	1368;"	d
+GET_PWM_POST_SCALER_0	smac/hal/ssv6006c/ssv6006C_reg.h	2572;"	d
+GET_PWM_POST_SCALER_1	smac/hal/ssv6006c/ssv6006C_reg.h	2579;"	d
+GET_PWM_POST_SCALER_2	smac/hal/ssv6006c/ssv6006C_reg.h	2586;"	d
+GET_PWM_POST_SCALER_3	smac/hal/ssv6006c/ssv6006C_reg.h	2593;"	d
+GET_PWM_POST_SCALER_4	smac/hal/ssv6006c/ssv6006C_reg.h	2600;"	d
+GET_PWM_POST_SCALER_A	include/ssv6200_reg.h	1360;"	d
+GET_PWM_POST_SCALER_B	include/ssv6200_reg.h	1366;"	d
+GET_PWM_SETTING_UPDATE_0	smac/hal/ssv6006c/ssv6006C_reg.h	2573;"	d
+GET_PWM_SETTING_UPDATE_1	smac/hal/ssv6006c/ssv6006C_reg.h	2580;"	d
+GET_PWM_SETTING_UPDATE_2	smac/hal/ssv6006c/ssv6006C_reg.h	2587;"	d
+GET_PWM_SETTING_UPDATE_3	smac/hal/ssv6006c/ssv6006C_reg.h	2594;"	d
+GET_PWM_SETTING_UPDATE_4	smac/hal/ssv6006c/ssv6006C_reg.h	2601;"	d
+GET_Q0_PKT_CLS_MIB_EN	include/ssv6200_reg.h	3135;"	d
+GET_Q0_PKT_CLS_MIB_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3983;"	d
+GET_Q0_PKT_CLS_ONGOING	include/ssv6200_reg.h	3136;"	d
+GET_Q0_PKT_CLS_ONGOING	smac/hal/ssv6006c/ssv6006C_reg.h	3984;"	d
+GET_Q1_PKT_CLS_MIB_EN	include/ssv6200_reg.h	3137;"	d
+GET_Q1_PKT_CLS_MIB_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3985;"	d
+GET_Q1_PKT_CLS_ONGOING	include/ssv6200_reg.h	3138;"	d
+GET_Q1_PKT_CLS_ONGOING	smac/hal/ssv6006c/ssv6006C_reg.h	3986;"	d
+GET_Q2_PKT_CLS_MIB_EN	include/ssv6200_reg.h	3139;"	d
+GET_Q2_PKT_CLS_MIB_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3987;"	d
+GET_Q2_PKT_CLS_ONGOING	include/ssv6200_reg.h	3140;"	d
+GET_Q2_PKT_CLS_ONGOING	smac/hal/ssv6006c/ssv6006C_reg.h	3988;"	d
+GET_Q3_PKT_CLS_MIB_EN	include/ssv6200_reg.h	3141;"	d
+GET_Q3_PKT_CLS_MIB_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3989;"	d
+GET_Q3_PKT_CLS_ONGOING	include/ssv6200_reg.h	3142;"	d
+GET_Q3_PKT_CLS_ONGOING	smac/hal/ssv6006c/ssv6006C_reg.h	3990;"	d
+GET_QOS_EN	include/ssv6200_reg.h	3089;"	d
+GET_QOS_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3921;"	d
+GET_Q_REQ_DUR	include/ssv6200_reg.h	2820;"	d
+GET_R5_RESPONSE_FLAG	include/ssv6200_reg.h	1930;"	d
+GET_R5_RESPONSE_FLAG	smac/hal/ssv6006c/ssv6006C_reg.h	2683;"	d
+GET_RANDOM_SEED1	smac/hal/ssv6006c/ssv6006C_reg.h	3973;"	d
+GET_RANDOM_SEED2	smac/hal/ssv6006c/ssv6006C_reg.h	3972;"	d
+GET_RANDOM_SEED3	smac/hal/ssv6006c/ssv6006C_reg.h	3971;"	d
+GET_RAND_EN	include/ssv6200_reg.h	2538;"	d
+GET_RAND_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3276;"	d
+GET_RAND_NUM	include/ssv6200_reg.h	2539;"	d
+GET_RAND_NUM	smac/hal/ssv6006c/ssv6006C_reg.h	3277;"	d
+GET_RATE_INDEX	smac/ssv_rc_minstrel_ht.h	26;"	d
+GET_RAW_TYPHOST_INT_MAP	smac/hal/ssv6006c/ssv6006C_reg.h	3027;"	d
+GET_RAW_TYPHOST_INT_MAP_02	smac/hal/ssv6006c/ssv6006C_reg.h	3018;"	d
+GET_RAW_TYPHOST_INT_MAP_15	smac/hal/ssv6006c/ssv6006C_reg.h	3021;"	d
+GET_RAW_TYPHOST_INT_MAP_31	smac/hal/ssv6006c/ssv6006C_reg.h	3024;"	d
+GET_RAW_TYPMCU_INT_MAP	smac/hal/ssv6006c/ssv6006C_reg.h	3040;"	d
+GET_RAW_TYPMCU_INT_MAP_02	smac/hal/ssv6006c/ssv6006C_reg.h	3031;"	d
+GET_RAW_TYPMCU_INT_MAP_15	smac/hal/ssv6006c/ssv6006C_reg.h	3034;"	d
+GET_RAW_TYPMCU_INT_MAP_31	smac/hal/ssv6006c/ssv6006C_reg.h	3037;"	d
+GET_RCAL_RDY	include/ssv6200_reg.h	4773;"	d
+GET_RDATA_RDY	include/ssv6200_reg.h	2063;"	d
+GET_RDY_FOR_FW_DOWNLOAD	include/ssv6200_reg.h	1891;"	d
+GET_RDY_FOR_FW_DOWNLOAD	smac/hal/ssv6006c/ssv6006C_reg.h	2674;"	d
+GET_RDY_FOR_TX_RX	include/ssv6200_reg.h	1890;"	d
+GET_RDY_FOR_TX_RX	smac/hal/ssv6006c/ssv6006C_reg.h	2673;"	d
+GET_RD_ADDR	include/ssv6200_reg.h	2544;"	d
+GET_RD_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	3282;"	d
+GET_RD_DAT_CNT	include/ssv6200_reg.h	2070;"	d
+GET_RD_DAT_CNT_CLR	include/ssv6200_reg.h	2074;"	d
+GET_RD_ID	include/ssv6200_reg.h	2545;"	d
+GET_RD_ID	smac/hal/ssv6006c/ssv6006C_reg.h	3283;"	d
+GET_RD_STS_CNT	include/ssv6200_reg.h	2071;"	d
+GET_RD_STS_CNT_CLR	include/ssv6200_reg.h	2073;"	d
+GET_READ_ADDRESS	include/ssv6200_reg.h	1938;"	d
+GET_READ_DATA	include/ssv6200_reg.h	1937;"	d
+GET_REASON_TRAP0	include/ssv6200_reg.h	3095;"	d
+GET_REASON_TRAP0	smac/hal/ssv6006c/ssv6006C_reg.h	3929;"	d
+GET_REASON_TRAP1	include/ssv6200_reg.h	3096;"	d
+GET_REASON_TRAP1	smac/hal/ssv6006c/ssv6006C_reg.h	3930;"	d
+GET_REG_AHB_DEBUG_MX	include/ssv6200_reg.h	1329;"	d
+GET_REG_PKT_R_NBRT	include/ssv6200_reg.h	1331;"	d
+GET_REG_PKT_W_NBRT	include/ssv6200_reg.h	1330;"	d
+GET_REQ_LOCK	include/ssv6200_reg.h	3771;"	d
+GET_REQ_LOCK	smac/hal/ssv6006c/ssv6006C_reg.h	8954;"	d
+GET_REQ_LOCK_INT	include/ssv6200_reg.h	3777;"	d
+GET_REQ_LOCK_INT	smac/hal/ssv6006c/ssv6006C_reg.h	8960;"	d
+GET_REQ_LOCK_INT_EN	include/ssv6200_reg.h	3776;"	d
+GET_REQ_LOCK_INT_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8959;"	d
+GET_REQ_NACK_CLR	include/ssv6200_reg.h	4833;"	d
+GET_REQ_PORNS_CHGEN	include/ssv6200_reg.h	4837;"	d
+GET_RESET_N_CPUN10	smac/hal/ssv6006c/ssv6006C_reg.h	2403;"	d
+GET_RESP_OUT_EDGE	include/ssv6200_reg.h	1931;"	d
+GET_RF_BB_SW_RST	include/ssv6200_reg.h	1286;"	d
+GET_RG_11B_ACI_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	8194;"	d
+GET_RG_40M_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	7576;"	d
+GET_RG_5G_BYPASS_COARSE_FREQ	smac/hal/ssv6006c/ssv6006C_reg.h	8633;"	d
+GET_RG_5G_CCFO_CNT_LMT	smac/hal/ssv6006c/ssv6006C_reg.h	8632;"	d
+GET_RG_5G_CCFO_GAIN_BY2	smac/hal/ssv6006c/ssv6006C_reg.h	8634;"	d
+GET_RG_5G_DC_RM_LEAKY_FACTOR_T1	smac/hal/ssv6006c/ssv6006C_reg.h	8298;"	d
+GET_RG_5G_DC_RM_LEAKY_FACTOR_T2	smac/hal/ssv6006c/ssv6006C_reg.h	8297;"	d
+GET_RG_5G_DC_RM_LEAKY_FACTOR_T3	smac/hal/ssv6006c/ssv6006C_reg.h	8296;"	d
+GET_RG_5G_EN_IREF_RX	smac/hal/ssv6006c/ssv6006C_reg.h	7156;"	d
+GET_RG_5G_EN_LDO_RX_FE	smac/hal/ssv6006c/ssv6006C_reg.h	7155;"	d
+GET_RG_5G_EN_LDO_RX_FE_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	7147;"	d
+GET_RG_5G_EN_LDO_RX_FE_FC	smac/hal/ssv6006c/ssv6006C_reg.h	7157;"	d
+GET_RG_5G_EN_LDO_RX_FE_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	7158;"	d
+GET_RG_5G_EN_RX_DIV2	smac/hal/ssv6006c/ssv6006C_reg.h	7124;"	d
+GET_RG_5G_EN_RX_IQCAL	smac/hal/ssv6006c/ssv6006C_reg.h	7142;"	d
+GET_RG_5G_EN_RX_LNA	smac/hal/ssv6006c/ssv6006C_reg.h	7120;"	d
+GET_RG_5G_EN_RX_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	7126;"	d
+GET_RG_5G_EN_RX_MIXER	smac/hal/ssv6006c/ssv6006C_reg.h	7122;"	d
+GET_RG_5G_EN_RX_TZ	smac/hal/ssv6006c/ssv6006C_reg.h	7128;"	d
+GET_RG_5G_EN_TX_DIV2	smac/hal/ssv6006c/ssv6006C_reg.h	7134;"	d
+GET_RG_5G_EN_TX_DIV2_BUF	smac/hal/ssv6006c/ssv6006C_reg.h	7136;"	d
+GET_RG_5G_EN_TX_DPD	smac/hal/ssv6006c/ssv6006C_reg.h	7144;"	d
+GET_RG_5G_EN_TX_MOD	smac/hal/ssv6006c/ssv6006C_reg.h	7132;"	d
+GET_RG_5G_EN_TX_PA	smac/hal/ssv6006c/ssv6006C_reg.h	7130;"	d
+GET_RG_5G_EN_TX_SELF_MIXER	smac/hal/ssv6006c/ssv6006C_reg.h	7140;"	d
+GET_RG_5G_EN_TX_TRSW	smac/hal/ssv6006c/ssv6006C_reg.h	7118;"	d
+GET_RG_5G_EN_TX_TSSI	smac/hal/ssv6006c/ssv6006C_reg.h	7145;"	d
+GET_RG_5G_GM_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	7164;"	d
+GET_RG_5G_IDACAI_TZ0_COARSE0	smac/hal/ssv6006c/ssv6006C_reg.h	7481;"	d
+GET_RG_5G_IDACAI_TZ0_COARSE1	smac/hal/ssv6006c/ssv6006C_reg.h	7479;"	d
+GET_RG_5G_IDACAI_TZ0_COARSE2	smac/hal/ssv6006c/ssv6006C_reg.h	7477;"	d
+GET_RG_5G_IDACAI_TZ0_COARSE3	smac/hal/ssv6006c/ssv6006C_reg.h	7475;"	d
+GET_RG_5G_IDACAI_TZ0_COARSE4	smac/hal/ssv6006c/ssv6006C_reg.h	7473;"	d
+GET_RG_5G_IDACAI_TZ0_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	7439;"	d
+GET_RG_5G_IDACAI_TZ0_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	7437;"	d
+GET_RG_5G_IDACAI_TZ0_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	7419;"	d
+GET_RG_5G_IDACAI_TZ0_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	7417;"	d
+GET_RG_5G_IDACAI_TZ0_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	7415;"	d
+GET_RG_5G_IDACAI_TZ0_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	7413;"	d
+GET_RG_5G_IDACAI_TZ0_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	7411;"	d
+GET_RG_5G_IDACAI_TZ0_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	7409;"	d
+GET_RG_5G_IDACAI_TZ0_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	7435;"	d
+GET_RG_5G_IDACAI_TZ0_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	7433;"	d
+GET_RG_5G_IDACAI_TZ0_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	7431;"	d
+GET_RG_5G_IDACAI_TZ0_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	7429;"	d
+GET_RG_5G_IDACAI_TZ0_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	7427;"	d
+GET_RG_5G_IDACAI_TZ0_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	7425;"	d
+GET_RG_5G_IDACAI_TZ0_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	7423;"	d
+GET_RG_5G_IDACAI_TZ0_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	7421;"	d
+GET_RG_5G_IDACAI_TZ1_COARSE0	smac/hal/ssv6006c/ssv6006C_reg.h	7491;"	d
+GET_RG_5G_IDACAI_TZ1_COARSE1	smac/hal/ssv6006c/ssv6006C_reg.h	7489;"	d
+GET_RG_5G_IDACAI_TZ1_COARSE2	smac/hal/ssv6006c/ssv6006C_reg.h	7487;"	d
+GET_RG_5G_IDACAI_TZ1_COARSE3	smac/hal/ssv6006c/ssv6006C_reg.h	7485;"	d
+GET_RG_5G_IDACAI_TZ1_COARSE4	smac/hal/ssv6006c/ssv6006C_reg.h	7483;"	d
+GET_RG_5G_IDACAI_TZ1_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	7471;"	d
+GET_RG_5G_IDACAI_TZ1_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	7469;"	d
+GET_RG_5G_IDACAI_TZ1_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	7451;"	d
+GET_RG_5G_IDACAI_TZ1_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	7449;"	d
+GET_RG_5G_IDACAI_TZ1_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	7447;"	d
+GET_RG_5G_IDACAI_TZ1_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	7445;"	d
+GET_RG_5G_IDACAI_TZ1_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	7443;"	d
+GET_RG_5G_IDACAI_TZ1_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	7441;"	d
+GET_RG_5G_IDACAI_TZ1_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	7467;"	d
+GET_RG_5G_IDACAI_TZ1_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	7465;"	d
+GET_RG_5G_IDACAI_TZ1_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	7463;"	d
+GET_RG_5G_IDACAI_TZ1_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	7461;"	d
+GET_RG_5G_IDACAI_TZ1_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	7459;"	d
+GET_RG_5G_IDACAI_TZ1_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	7457;"	d
+GET_RG_5G_IDACAI_TZ1_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	7455;"	d
+GET_RG_5G_IDACAI_TZ1_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	7453;"	d
+GET_RG_5G_IDACAQ_TZ0_COARSE0	smac/hal/ssv6006c/ssv6006C_reg.h	7482;"	d
+GET_RG_5G_IDACAQ_TZ0_COARSE1	smac/hal/ssv6006c/ssv6006C_reg.h	7480;"	d
+GET_RG_5G_IDACAQ_TZ0_COARSE2	smac/hal/ssv6006c/ssv6006C_reg.h	7478;"	d
+GET_RG_5G_IDACAQ_TZ0_COARSE3	smac/hal/ssv6006c/ssv6006C_reg.h	7476;"	d
+GET_RG_5G_IDACAQ_TZ0_COARSE4	smac/hal/ssv6006c/ssv6006C_reg.h	7474;"	d
+GET_RG_5G_IDACAQ_TZ0_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	7440;"	d
+GET_RG_5G_IDACAQ_TZ0_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	7438;"	d
+GET_RG_5G_IDACAQ_TZ0_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	7420;"	d
+GET_RG_5G_IDACAQ_TZ0_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	7418;"	d
+GET_RG_5G_IDACAQ_TZ0_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	7416;"	d
+GET_RG_5G_IDACAQ_TZ0_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	7414;"	d
+GET_RG_5G_IDACAQ_TZ0_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	7412;"	d
+GET_RG_5G_IDACAQ_TZ0_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	7410;"	d
+GET_RG_5G_IDACAQ_TZ0_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	7436;"	d
+GET_RG_5G_IDACAQ_TZ0_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	7434;"	d
+GET_RG_5G_IDACAQ_TZ0_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	7432;"	d
+GET_RG_5G_IDACAQ_TZ0_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	7430;"	d
+GET_RG_5G_IDACAQ_TZ0_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	7428;"	d
+GET_RG_5G_IDACAQ_TZ0_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	7426;"	d
+GET_RG_5G_IDACAQ_TZ0_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	7424;"	d
+GET_RG_5G_IDACAQ_TZ0_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	7422;"	d
+GET_RG_5G_IDACAQ_TZ1_COARSE0	smac/hal/ssv6006c/ssv6006C_reg.h	7492;"	d
+GET_RG_5G_IDACAQ_TZ1_COARSE1	smac/hal/ssv6006c/ssv6006C_reg.h	7490;"	d
+GET_RG_5G_IDACAQ_TZ1_COARSE2	smac/hal/ssv6006c/ssv6006C_reg.h	7488;"	d
+GET_RG_5G_IDACAQ_TZ1_COARSE3	smac/hal/ssv6006c/ssv6006C_reg.h	7486;"	d
+GET_RG_5G_IDACAQ_TZ1_COARSE4	smac/hal/ssv6006c/ssv6006C_reg.h	7484;"	d
+GET_RG_5G_IDACAQ_TZ1_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	7472;"	d
+GET_RG_5G_IDACAQ_TZ1_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	7470;"	d
+GET_RG_5G_IDACAQ_TZ1_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	7452;"	d
+GET_RG_5G_IDACAQ_TZ1_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	7450;"	d
+GET_RG_5G_IDACAQ_TZ1_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	7448;"	d
+GET_RG_5G_IDACAQ_TZ1_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	7446;"	d
+GET_RG_5G_IDACAQ_TZ1_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	7444;"	d
+GET_RG_5G_IDACAQ_TZ1_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	7442;"	d
+GET_RG_5G_IDACAQ_TZ1_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	7468;"	d
+GET_RG_5G_IDACAQ_TZ1_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	7466;"	d
+GET_RG_5G_IDACAQ_TZ1_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	7464;"	d
+GET_RG_5G_IDACAQ_TZ1_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	7462;"	d
+GET_RG_5G_IDACAQ_TZ1_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	7460;"	d
+GET_RG_5G_IDACAQ_TZ1_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	7458;"	d
+GET_RG_5G_IDACAQ_TZ1_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	7456;"	d
+GET_RG_5G_IDACAQ_TZ1_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	7454;"	d
+GET_RG_5G_LDO_LEVEL_RX_FE	smac/hal/ssv6006c/ssv6006C_reg.h	7146;"	d
+GET_RG_5G_PABIAS_2X	smac/hal/ssv6006c/ssv6006C_reg.h	7189;"	d
+GET_RG_5G_PABIAS_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	7185;"	d
+GET_RG_5G_PABIAS_CTRL_F0	smac/hal/ssv6006c/ssv6006C_reg.h	7548;"	d
+GET_RG_5G_PABIAS_CTRL_F1	smac/hal/ssv6006c/ssv6006C_reg.h	7553;"	d
+GET_RG_5G_PABIAS_CTRL_F2	smac/hal/ssv6006c/ssv6006C_reg.h	7558;"	d
+GET_RG_5G_PABIAS_CTRL_F3	smac/hal/ssv6006c/ssv6006C_reg.h	7563;"	d
+GET_RG_5G_PACELL_EN	smac/hal/ssv6006c/ssv6006C_reg.h	7184;"	d
+GET_RG_5G_PGAG_DPDCAL	smac/hal/ssv6006c/ssv6006C_reg.h	7517;"	d
+GET_RG_5G_PGAG_RCCAL	smac/hal/ssv6006c/ssv6006C_reg.h	7512;"	d
+GET_RG_5G_PGAG_RXIQCAL	smac/hal/ssv6006c/ssv6006C_reg.h	7514;"	d
+GET_RG_5G_PGAG_TXCAL	smac/hal/ssv6006c/ssv6006C_reg.h	7510;"	d
+GET_RG_5G_RFG_DPDCAL	smac/hal/ssv6006c/ssv6006C_reg.h	7516;"	d
+GET_RG_5G_RFG_RXIQCAL	smac/hal/ssv6006c/ssv6006C_reg.h	7513;"	d
+GET_RG_5G_RXRF_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	7497;"	d
+GET_RG_5G_RXRF_R2T_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	7505;"	d
+GET_RG_5G_RXRF_T2R_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	7501;"	d
+GET_RG_5G_RX_ADC_CLOAD	smac/hal/ssv6006c/ssv6006C_reg.h	7178;"	d
+GET_RG_5G_RX_ADC_ICMP	smac/hal/ssv6006c/ssv6006C_reg.h	7176;"	d
+GET_RG_5G_RX_ADC_PSW	smac/hal/ssv6006c/ssv6006C_reg.h	7179;"	d
+GET_RG_5G_RX_ADC_VCMI	smac/hal/ssv6006c/ssv6006C_reg.h	7177;"	d
+GET_RG_5G_RX_DCCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	7506;"	d
+GET_RG_5G_RX_DIV2_BUF	smac/hal/ssv6006c/ssv6006C_reg.h	7165;"	d
+GET_RG_5G_RX_DIV2_CML	smac/hal/ssv6006c/ssv6006C_reg.h	7166;"	d
+GET_RG_5G_RX_DIV2_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	7123;"	d
+GET_RG_5G_RX_DIV_CMLISEL	smac/hal/ssv6006c/ssv6006C_reg.h	7167;"	d
+GET_RG_5G_RX_DIV_PREBUFS2	smac/hal/ssv6006c/ssv6006C_reg.h	7168;"	d
+GET_RG_5G_RX_HG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	7212;"	d
+GET_RG_5G_RX_HG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	7207;"	d
+GET_RG_5G_RX_HG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	7208;"	d
+GET_RG_5G_RX_HG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	7209;"	d
+GET_RG_5G_RX_HG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	7205;"	d
+GET_RG_5G_RX_HG_SQDC	smac/hal/ssv6006c/ssv6006C_reg.h	7211;"	d
+GET_RG_5G_RX_HG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	7214;"	d
+GET_RG_5G_RX_HG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	7210;"	d
+GET_RG_5G_RX_HG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	7206;"	d
+GET_RG_5G_RX_HG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	7213;"	d
+GET_RG_5G_RX_HG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	7215;"	d
+GET_RG_5G_RX_IQCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	7509;"	d
+GET_RG_5G_RX_IQCAL_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	7141;"	d
+GET_RG_5G_RX_LG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	7234;"	d
+GET_RG_5G_RX_LG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	7229;"	d
+GET_RG_5G_RX_LG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	7230;"	d
+GET_RG_5G_RX_LG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	7231;"	d
+GET_RG_5G_RX_LG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	7227;"	d
+GET_RG_5G_RX_LG_SQDC	smac/hal/ssv6006c/ssv6006C_reg.h	7233;"	d
+GET_RG_5G_RX_LG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	7236;"	d
+GET_RG_5G_RX_LG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	7232;"	d
+GET_RG_5G_RX_LG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	7228;"	d
+GET_RG_5G_RX_LG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	7235;"	d
+GET_RG_5G_RX_LG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	7237;"	d
+GET_RG_5G_RX_LNA_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	7119;"	d
+GET_RG_5G_RX_LNA_SETTLE	smac/hal/ssv6006c/ssv6006C_reg.h	7163;"	d
+GET_RG_5G_RX_LNA_TRI_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	7162;"	d
+GET_RG_5G_RX_LOBUF_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	7125;"	d
+GET_RG_5G_RX_MG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	7223;"	d
+GET_RG_5G_RX_MG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	7218;"	d
+GET_RG_5G_RX_MG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	7219;"	d
+GET_RG_5G_RX_MG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	7220;"	d
+GET_RG_5G_RX_MG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	7216;"	d
+GET_RG_5G_RX_MG_SQDC	smac/hal/ssv6006c/ssv6006C_reg.h	7222;"	d
+GET_RG_5G_RX_MG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	7225;"	d
+GET_RG_5G_RX_MG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	7221;"	d
+GET_RG_5G_RX_MG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	7217;"	d
+GET_RG_5G_RX_MG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	7224;"	d
+GET_RG_5G_RX_MG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	7226;"	d
+GET_RG_5G_RX_MIXER_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	7121;"	d
+GET_RG_5G_RX_SCA_LOAD	smac/hal/ssv6006c/ssv6006C_reg.h	7161;"	d
+GET_RG_5G_RX_SCA_MA	smac/hal/ssv6006c/ssv6006C_reg.h	7160;"	d
+GET_RG_5G_RX_SCA_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	7159;"	d
+GET_RG_5G_RX_TZ_CMZ_C	smac/hal/ssv6006c/ssv6006C_reg.h	7180;"	d
+GET_RG_5G_RX_TZ_CMZ_R	smac/hal/ssv6006c/ssv6006C_reg.h	7181;"	d
+GET_RG_5G_RX_TZ_COURSE	smac/hal/ssv6006c/ssv6006C_reg.h	7169;"	d
+GET_RG_5G_RX_TZ_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	7127;"	d
+GET_RG_5G_RX_TZ_OUT_TRISTATE	smac/hal/ssv6006c/ssv6006C_reg.h	7138;"	d
+GET_RG_5G_RX_TZ_OUT_TRISTATE_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	7137;"	d
+GET_RG_5G_RX_ULG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	7245;"	d
+GET_RG_5G_RX_ULG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	7240;"	d
+GET_RG_5G_RX_ULG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	7241;"	d
+GET_RG_5G_RX_ULG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	7242;"	d
+GET_RG_5G_RX_ULG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	7238;"	d
+GET_RG_5G_RX_ULG_SQDC	smac/hal/ssv6006c/ssv6006C_reg.h	7244;"	d
+GET_RG_5G_RX_ULG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	7247;"	d
+GET_RG_5G_RX_ULG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	7243;"	d
+GET_RG_5G_RX_ULG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	7239;"	d
+GET_RG_5G_RX_ULG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	7246;"	d
+GET_RG_5G_RX_ULG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	7248;"	d
+GET_RG_5G_TXDAC_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	7494;"	d
+GET_RG_5G_TXDAC_R2T_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	7502;"	d
+GET_RG_5G_TXDAC_T2R_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	7498;"	d
+GET_RG_5G_TXLPF_BOOSTI	smac/hal/ssv6006c/ssv6006C_reg.h	7255;"	d
+GET_RG_5G_TXLPF_GMCELL	smac/hal/ssv6006c/ssv6006C_reg.h	7199;"	d
+GET_RG_5G_TXMOD_GMCELL	smac/hal/ssv6006c/ssv6006C_reg.h	7198;"	d
+GET_RG_5G_TXMOD_LOBIAS	smac/hal/ssv6006c/ssv6006C_reg.h	7203;"	d
+GET_RG_5G_TXMOD_PGABIAS	smac/hal/ssv6006c/ssv6006C_reg.h	7204;"	d
+GET_RG_5G_TXPAPGA_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	7182;"	d
+GET_RG_5G_TXPA_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	7496;"	d
+GET_RG_5G_TXPA_R2T_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	7504;"	d
+GET_RG_5G_TXPA_T2R_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	7500;"	d
+GET_RG_5G_TXPGA_CAPSW	smac/hal/ssv6006c/ssv6006C_reg.h	7183;"	d
+GET_RG_5G_TXPGA_CAPSW_F0	smac/hal/ssv6006c/ssv6006C_reg.h	7547;"	d
+GET_RG_5G_TXPGA_CAPSW_F1	smac/hal/ssv6006c/ssv6006C_reg.h	7552;"	d
+GET_RG_5G_TXPGA_CAPSW_F2	smac/hal/ssv6006c/ssv6006C_reg.h	7557;"	d
+GET_RG_5G_TXPGA_CAPSW_F3	smac/hal/ssv6006c/ssv6006C_reg.h	7562;"	d
+GET_RG_5G_TXPGA_MAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7196;"	d
+GET_RG_5G_TXPGA_STEER	smac/hal/ssv6006c/ssv6006C_reg.h	7197;"	d
+GET_RG_5G_TXRF_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	7495;"	d
+GET_RG_5G_TXRF_R2T_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	7503;"	d
+GET_RG_5G_TXRF_T2R_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	7499;"	d
+GET_RG_5G_TX_ADDGMCELL	smac/hal/ssv6006c/ssv6006C_reg.h	7202;"	d
+GET_RG_5G_TX_BAND_F0	smac/hal/ssv6006c/ssv6006C_reg.h	7716;"	d
+GET_RG_5G_TX_BAND_F1	smac/hal/ssv6006c/ssv6006C_reg.h	7715;"	d
+GET_RG_5G_TX_BAND_F2	smac/hal/ssv6006c/ssv6006C_reg.h	7717;"	d
+GET_RG_5G_TX_DACI1ST	smac/hal/ssv6006c/ssv6006C_reg.h	7249;"	d
+GET_RG_5G_TX_DACLPF_ICOARSE	smac/hal/ssv6006c/ssv6006C_reg.h	7250;"	d
+GET_RG_5G_TX_DACLPF_IFINE	smac/hal/ssv6006c/ssv6006C_reg.h	7251;"	d
+GET_RG_5G_TX_DACLPF_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	7252;"	d
+GET_RG_5G_TX_DAC_CKEDGE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	7257;"	d
+GET_RG_5G_TX_DAC_IATTN	smac/hal/ssv6006c/ssv6006C_reg.h	7254;"	d
+GET_RG_5G_TX_DAC_IBIAS	smac/hal/ssv6006c/ssv6006C_reg.h	7253;"	d
+GET_RG_5G_TX_DAC_IOFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	7259;"	d
+GET_RG_5G_TX_DAC_OS	smac/hal/ssv6006c/ssv6006C_reg.h	7258;"	d
+GET_RG_5G_TX_DAC_QOFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	7260;"	d
+GET_RG_5G_TX_DAC_RCAL	smac/hal/ssv6006c/ssv6006C_reg.h	7256;"	d
+GET_RG_5G_TX_DCCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	7507;"	d
+GET_RG_5G_TX_DIV2_BUF_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	7135;"	d
+GET_RG_5G_TX_DIV2_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	7133;"	d
+GET_RG_5G_TX_DIV_CMLISEL	smac/hal/ssv6006c/ssv6006C_reg.h	7192;"	d
+GET_RG_5G_TX_DIV_CMLVSEL	smac/hal/ssv6006c/ssv6006C_reg.h	7193;"	d
+GET_RG_5G_TX_DIV_PREBUFS2	smac/hal/ssv6006c/ssv6006C_reg.h	7191;"	d
+GET_RG_5G_TX_DIV_VSET	smac/hal/ssv6006c/ssv6006C_reg.h	7194;"	d
+GET_RG_5G_TX_DPDGM_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	7170;"	d
+GET_RG_5G_TX_DPD_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	7171;"	d
+GET_RG_5G_TX_DPD_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	7143;"	d
+GET_RG_5G_TX_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7201;"	d
+GET_RG_5G_TX_GAIN_DPDCAL	smac/hal/ssv6006c/ssv6006C_reg.h	7518;"	d
+GET_RG_5G_TX_GAIN_F0	smac/hal/ssv6006c/ssv6006C_reg.h	7571;"	d
+GET_RG_5G_TX_GAIN_F1	smac/hal/ssv6006c/ssv6006C_reg.h	7572;"	d
+GET_RG_5G_TX_GAIN_F2	smac/hal/ssv6006c/ssv6006C_reg.h	7573;"	d
+GET_RG_5G_TX_GAIN_F3	smac/hal/ssv6006c/ssv6006C_reg.h	7574;"	d
+GET_RG_5G_TX_GAIN_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	6460;"	d
+GET_RG_5G_TX_GAIN_OFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	7200;"	d
+GET_RG_5G_TX_GAIN_RXIQCAL	smac/hal/ssv6006c/ssv6006C_reg.h	7515;"	d
+GET_RG_5G_TX_GAIN_TXCAL	smac/hal/ssv6006c/ssv6006C_reg.h	7511;"	d
+GET_RG_5G_TX_IQCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	7508;"	d
+GET_RG_5G_TX_LOBUF_VSET	smac/hal/ssv6006c/ssv6006C_reg.h	7195;"	d
+GET_RG_5G_TX_MOD_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	7131;"	d
+GET_RG_5G_TX_PA1_VCAS	smac/hal/ssv6006c/ssv6006C_reg.h	7187;"	d
+GET_RG_5G_TX_PA1_VCAS_F0	smac/hal/ssv6006c/ssv6006C_reg.h	7549;"	d
+GET_RG_5G_TX_PA1_VCAS_F1	smac/hal/ssv6006c/ssv6006C_reg.h	7554;"	d
+GET_RG_5G_TX_PA1_VCAS_F2	smac/hal/ssv6006c/ssv6006C_reg.h	7559;"	d
+GET_RG_5G_TX_PA1_VCAS_F3	smac/hal/ssv6006c/ssv6006C_reg.h	7564;"	d
+GET_RG_5G_TX_PA2_VCAS	smac/hal/ssv6006c/ssv6006C_reg.h	7188;"	d
+GET_RG_5G_TX_PA2_VCAS_F0	smac/hal/ssv6006c/ssv6006C_reg.h	7550;"	d
+GET_RG_5G_TX_PA2_VCAS_F1	smac/hal/ssv6006c/ssv6006C_reg.h	7555;"	d
+GET_RG_5G_TX_PA2_VCAS_F2	smac/hal/ssv6006c/ssv6006C_reg.h	7560;"	d
+GET_RG_5G_TX_PA2_VCAS_F3	smac/hal/ssv6006c/ssv6006C_reg.h	7565;"	d
+GET_RG_5G_TX_PA3_VCAS	smac/hal/ssv6006c/ssv6006C_reg.h	7190;"	d
+GET_RG_5G_TX_PA3_VCAS_F0	smac/hal/ssv6006c/ssv6006C_reg.h	7551;"	d
+GET_RG_5G_TX_PA3_VCAS_F1	smac/hal/ssv6006c/ssv6006C_reg.h	7556;"	d
+GET_RG_5G_TX_PA3_VCAS_F2	smac/hal/ssv6006c/ssv6006C_reg.h	7561;"	d
+GET_RG_5G_TX_PA3_VCAS_F3	smac/hal/ssv6006c/ssv6006C_reg.h	7566;"	d
+GET_RG_5G_TX_PAFB_EN	smac/hal/ssv6006c/ssv6006C_reg.h	7186;"	d
+GET_RG_5G_TX_PAFB_EN_F0	smac/hal/ssv6006c/ssv6006C_reg.h	7567;"	d
+GET_RG_5G_TX_PAFB_EN_F1	smac/hal/ssv6006c/ssv6006C_reg.h	7568;"	d
+GET_RG_5G_TX_PAFB_EN_F2	smac/hal/ssv6006c/ssv6006C_reg.h	7569;"	d
+GET_RG_5G_TX_PAFB_EN_F3	smac/hal/ssv6006c/ssv6006C_reg.h	7570;"	d
+GET_RG_5G_TX_PA_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	7129;"	d
+GET_RG_5G_TX_SELF_MIXER_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	7139;"	d
+GET_RG_5G_TX_TRSW_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	7117;"	d
+GET_RG_5G_TX_TSSI_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	7172;"	d
+GET_RG_5G_TX_TSSI_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	7173;"	d
+GET_RG_5G_TX_TSSI_TEST	smac/hal/ssv6006c/ssv6006C_reg.h	7174;"	d
+GET_RG_5G_TX_TSSI_TESTMODE	smac/hal/ssv6006c/ssv6006C_reg.h	7175;"	d
+GET_RG_AAC5GB_PDSW_EN_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	7397;"	d
+GET_RG_AAC5GB_TAR_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	7396;"	d
+GET_RG_ACI_DAGC_DONE_CNT_LMT_11GN	include/ssv6200_reg.h	3956;"	d
+GET_RG_ACI_DAGC_DONE_CNT_LMT_11GN	smac/hal/ssv6006c/ssv6006C_reg.h	8275;"	d
+GET_RG_ACI_DAGC_LEAKY_FACTOR_11B	include/ssv6200_reg.h	3949;"	d
+GET_RG_ACI_DAGC_LEAKY_FACTOR_11B	smac/hal/ssv6006c/ssv6006C_reg.h	8266;"	d
+GET_RG_ACI_DAGC_LEAKY_FACTOR_11GN	include/ssv6200_reg.h	3955;"	d
+GET_RG_ACI_DAGC_LEAKY_FACTOR_11GN_HT20	smac/hal/ssv6006c/ssv6006C_reg.h	8273;"	d
+GET_RG_ACI_DAGC_LEAKY_FACTOR_11GN_HT40	smac/hal/ssv6006c/ssv6006C_reg.h	8343;"	d
+GET_RG_ACI_DAGC_PWR_SEL_11B	smac/hal/ssv6006c/ssv6006C_reg.h	8267;"	d
+GET_RG_ACI_DAGC_PWR_SEL_11GN_HT20	smac/hal/ssv6006c/ssv6006C_reg.h	8274;"	d
+GET_RG_ACI_DAGC_PWR_SEL_11GN_HT40	smac/hal/ssv6006c/ssv6006C_reg.h	8344;"	d
+GET_RG_ACI_DAGC_SET_VALUE_11B	include/ssv6200_reg.h	3952;"	d
+GET_RG_ACI_DAGC_SET_VALUE_11GN	include/ssv6200_reg.h	3957;"	d
+GET_RG_ACI_DAGC_TARGET_11B	smac/hal/ssv6006c/ssv6006C_reg.h	8268;"	d
+GET_RG_ACI_DAGC_TARGET_11GN_HT20	smac/hal/ssv6006c/ssv6006C_reg.h	8276;"	d
+GET_RG_ACI_DAGC_TARGET_11GN_HT40	smac/hal/ssv6006c/ssv6006C_reg.h	8345;"	d
+GET_RG_ACI_GAIN	include/ssv6200_reg.h	4399;"	d
+GET_RG_ACI_GAIN_INI_11B	smac/hal/ssv6006c/ssv6006C_reg.h	8269;"	d
+GET_RG_ACI_GAIN_INI_11GN_HT20	smac/hal/ssv6006c/ssv6006C_reg.h	8349;"	d
+GET_RG_ACI_GAIN_INI_11GN_HT40	smac/hal/ssv6006c/ssv6006C_reg.h	8348;"	d
+GET_RG_ACI_GAIN_INI_VAL_11GN	include/ssv6200_reg.h	3958;"	d
+GET_RG_ACI_GAIN_OW_11B	smac/hal/ssv6006c/ssv6006C_reg.h	8271;"	d
+GET_RG_ACI_GAIN_OW_11GN	include/ssv6200_reg.h	3960;"	d
+GET_RG_ACI_GAIN_OW_11GN_HT20	smac/hal/ssv6006c/ssv6006C_reg.h	8278;"	d
+GET_RG_ACI_GAIN_OW_11GN_HT40	smac/hal/ssv6006c/ssv6006C_reg.h	8347;"	d
+GET_RG_ACI_GAIN_OW_VAL_11GN	include/ssv6200_reg.h	3959;"	d
+GET_RG_ACI_GAIN_SET_11B	smac/hal/ssv6006c/ssv6006C_reg.h	8270;"	d
+GET_RG_ACI_GAIN_SET_11GN_HT20	smac/hal/ssv6006c/ssv6006C_reg.h	8277;"	d
+GET_RG_ACI_GAIN_SET_11GN_HT40	smac/hal/ssv6006c/ssv6006C_reg.h	8346;"	d
+GET_RG_ACI_POINT_CNT_LMT_11B	include/ssv6200_reg.h	3948;"	d
+GET_RG_ACI_POINT_CNT_LMT_11B	smac/hal/ssv6006c/ssv6006C_reg.h	8265;"	d
+GET_RG_ACI_POINT_CNT_LMT_11GN	include/ssv6200_reg.h	3954;"	d
+GET_RG_ACI_POINT_CNT_LMT_11GN_HT20	smac/hal/ssv6006c/ssv6006C_reg.h	8272;"	d
+GET_RG_ACI_POINT_CNT_LMT_11GN_HT40	smac/hal/ssv6006c/ssv6006C_reg.h	8342;"	d
+GET_RG_ACS_INI_PM_ALL0	smac/hal/ssv6006c/ssv6006C_reg.h	8635;"	d
+GET_RG_ADC2LA_CLKPH	include/ssv6200_reg.h	4407;"	d
+GET_RG_ADC2LA_SEL	include/ssv6200_reg.h	4406;"	d
+GET_RG_ADC_CLKSEL	include/ssv6200_reg.h	4614;"	d
+GET_RG_ADC_DIBIAS	include/ssv6200_reg.h	4615;"	d
+GET_RG_ADC_DIVR	include/ssv6200_reg.h	4616;"	d
+GET_RG_ADC_DVCMI	include/ssv6200_reg.h	4617;"	d
+GET_RG_ADC_EDGE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	7586;"	d
+GET_RG_ADC_SAMSEL	include/ssv6200_reg.h	4618;"	d
+GET_RG_ADC_STNBY	include/ssv6200_reg.h	4619;"	d
+GET_RG_ADC_TESTMODE	include/ssv6200_reg.h	4620;"	d
+GET_RG_ADC_TSEL	include/ssv6200_reg.h	4621;"	d
+GET_RG_ADC_VRSEL	include/ssv6200_reg.h	4622;"	d
+GET_RG_ADEDGE_SEL	include/ssv6200_reg.h	3860;"	d
+GET_RG_AGC_RELOCK_11B	smac/hal/ssv6006c/ssv6006C_reg.h	8321;"	d
+GET_RG_AGC_RELOCK_11GN	smac/hal/ssv6006c/ssv6006C_reg.h	8320;"	d
+GET_RG_AGC_RELOCK_CNT_DIFFDB_TH	smac/hal/ssv6006c/ssv6006C_reg.h	8323;"	d
+GET_RG_AGC_RELOCK_CNT_TH	smac/hal/ssv6006c/ssv6006C_reg.h	8317;"	d
+GET_RG_AGC_RELOCK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8319;"	d
+GET_RG_AGC_RELOCK_PWR_DIFFDB_TH	smac/hal/ssv6006c/ssv6006C_reg.h	8322;"	d
+GET_RG_AGC_RELOCK_PWR_TH	smac/hal/ssv6006c/ssv6006C_reg.h	8316;"	d
+GET_RG_AGC_RELOCK_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	8318;"	d
+GET_RG_AGC_THRESHOLD	include/ssv6200_reg.h	3947;"	d
+GET_RG_AGC_THRESHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	8264;"	d
+GET_RG_AGGREGATE	include/ssv6200_reg.h	3900;"	d
+GET_RG_AGGREGATE	smac/hal/ssv6006c/ssv6006C_reg.h	8219;"	d
+GET_RG_ALPHA_COARSE	smac/hal/ssv6006c/ssv6006C_reg.h	8705;"	d
+GET_RG_ALPHA_FINE	smac/hal/ssv6006c/ssv6006C_reg.h	8704;"	d
+GET_RG_ALPHA_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	7637;"	d
+GET_RG_ANT_SW_0	include/ssv6200_reg.h	4036;"	d
+GET_RG_ANT_SW_1	include/ssv6200_reg.h	4037;"	d
+GET_RG_ATCOR16_CCA_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	8657;"	d
+GET_RG_ATCOR16_CNT_LMT1	include/ssv6200_reg.h	4226;"	d
+GET_RG_ATCOR16_CNT_LMT1	smac/hal/ssv6006c/ssv6006C_reg.h	8555;"	d
+GET_RG_ATCOR16_CNT_LMT2	include/ssv6200_reg.h	4225;"	d
+GET_RG_ATCOR16_CNT_LMT2	smac/hal/ssv6006c/ssv6006C_reg.h	8554;"	d
+GET_RG_ATCOR16_CNT_PLUS_LMT1	include/ssv6200_reg.h	4250;"	d
+GET_RG_ATCOR16_CNT_PLUS_LMT1	smac/hal/ssv6006c/ssv6006C_reg.h	8579;"	d
+GET_RG_ATCOR16_CNT_PLUS_LMT2	include/ssv6200_reg.h	4249;"	d
+GET_RG_ATCOR16_CNT_PLUS_LMT2	smac/hal/ssv6006c/ssv6006C_reg.h	8578;"	d
+GET_RG_ATCOR16_CNT_TH	include/ssv6200_reg.h	4232;"	d
+GET_RG_ATCOR16_CNT_TH	smac/hal/ssv6006c/ssv6006C_reg.h	8561;"	d
+GET_RG_ATCOR16_RATIO_CCD	include/ssv6200_reg.h	4260;"	d
+GET_RG_ATCOR16_RATIO_CCD	smac/hal/ssv6006c/ssv6006C_reg.h	8625;"	d
+GET_RG_ATCOR16_RATIO_SB	include/ssv6200_reg.h	4227;"	d
+GET_RG_ATCOR16_RATIO_SB	smac/hal/ssv6006c/ssv6006C_reg.h	8556;"	d
+GET_RG_ATCOR16_SHORT_CNT_LMT	include/ssv6200_reg.h	4259;"	d
+GET_RG_ATCOR16_SHORT_CNT_LMT	smac/hal/ssv6006c/ssv6006C_reg.h	8624;"	d
+GET_RG_ATCOR16_SHORT_CNT_LMT2	include/ssv6200_reg.h	4262;"	d
+GET_RG_ATCOR16_SHORT_CNT_LMT2	smac/hal/ssv6006c/ssv6006C_reg.h	8627;"	d
+GET_RG_ATCOR64_ACC_LMT	include/ssv6200_reg.h	4261;"	d
+GET_RG_ATCOR64_ACC_LMT	smac/hal/ssv6006c/ssv6006C_reg.h	8626;"	d
+GET_RG_ATCOR64_CNT_LMT	include/ssv6200_reg.h	4224;"	d
+GET_RG_ATCOR64_CNT_LMT	smac/hal/ssv6006c/ssv6006C_reg.h	8553;"	d
+GET_RG_ATCOR64_FREQ_START	smac/hal/ssv6006c/ssv6006C_reg.h	8655;"	d
+GET_RG_AUDIO_ALPHA	smac/hal/ssv6006c/ssv6006C_reg.h	7706;"	d
+GET_RG_AUDIO_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8428;"	d
+GET_RG_AUDIO_CLK_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	8429;"	d
+GET_RG_AUDIO_FIL_EN	smac/hal/ssv6006c/ssv6006C_reg.h	7707;"	d
+GET_RG_AUDIO_TYPE	smac/hal/ssv6006c/ssv6006C_reg.h	7712;"	d
+GET_RG_AUDIO_VOLUME	smac/hal/ssv6006c/ssv6006C_reg.h	7705;"	d
+GET_RG_BB_11B_FALL_TIME	include/ssv6200_reg.h	4123;"	d
+GET_RG_BB_11B_RISE_TIME	include/ssv6200_reg.h	4122;"	d
+GET_RG_BB_11GN_FALL_TIME	include/ssv6200_reg.h	4199;"	d
+GET_RG_BB_11GN_RISE_TIME	include/ssv6200_reg.h	4198;"	d
+GET_RG_BB_CLK_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	8195;"	d
+GET_RG_BB_FALL_TIME_11B_TX	smac/hal/ssv6006c/ssv6006C_reg.h	8440;"	d
+GET_RG_BB_FALL_TIME_11GN_TX	smac/hal/ssv6006c/ssv6006C_reg.h	8527;"	d
+GET_RG_BB_RISE_TIME_11B_TX	smac/hal/ssv6006c/ssv6006C_reg.h	8439;"	d
+GET_RG_BB_RISE_TIME_11GN_TX	smac/hal/ssv6006c/ssv6006C_reg.h	8526;"	d
+GET_RG_BB_SCALE	smac/hal/ssv6006c/ssv6006C_reg.h	8224;"	d
+GET_RG_BB_SCALE_BARKER_CCK	smac/hal/ssv6006c/ssv6006C_reg.h	8369;"	d
+GET_RG_BB_SCALE_HT20_16QAM	smac/hal/ssv6006c/ssv6006C_reg.h	8376;"	d
+GET_RG_BB_SCALE_HT20_64QAM	smac/hal/ssv6006c/ssv6006C_reg.h	8375;"	d
+GET_RG_BB_SCALE_HT20_BPSK	smac/hal/ssv6006c/ssv6006C_reg.h	8378;"	d
+GET_RG_BB_SCALE_HT20_QPSK	smac/hal/ssv6006c/ssv6006C_reg.h	8377;"	d
+GET_RG_BB_SCALE_HT40_16QAM	smac/hal/ssv6006c/ssv6006C_reg.h	8380;"	d
+GET_RG_BB_SCALE_HT40_64QAM	smac/hal/ssv6006c/ssv6006C_reg.h	8379;"	d
+GET_RG_BB_SCALE_HT40_BPSK	smac/hal/ssv6006c/ssv6006C_reg.h	8382;"	d
+GET_RG_BB_SCALE_HT40_QPSK	smac/hal/ssv6006c/ssv6006C_reg.h	8381;"	d
+GET_RG_BB_SCALE_LEGACY_16QAM	smac/hal/ssv6006c/ssv6006C_reg.h	8372;"	d
+GET_RG_BB_SCALE_LEGACY_64QAM	smac/hal/ssv6006c/ssv6006C_reg.h	8371;"	d
+GET_RG_BB_SCALE_LEGACY_BPSK	smac/hal/ssv6006c/ssv6006C_reg.h	8374;"	d
+GET_RG_BB_SCALE_LEGACY_QPSK	smac/hal/ssv6006c/ssv6006C_reg.h	8373;"	d
+GET_RG_BB_SCALE_MAN_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8370;"	d
+GET_RG_BB_SIG_EN	smac/hal/ssv6006c/ssv6006C_reg.h	7598;"	d
+GET_RG_BIST_EN_CCFO	smac/hal/ssv6006c/ssv6006C_reg.h	8598;"	d
+GET_RG_BIST_EN_RX_FFT	smac/hal/ssv6006c/ssv6006C_reg.h	8422;"	d
+GET_RG_BIST_EN_TX_FFT	smac/hal/ssv6006c/ssv6006C_reg.h	8520;"	d
+GET_RG_BIST_EN_VTB	smac/hal/ssv6006c/ssv6006C_reg.h	8604;"	d
+GET_RG_BIST_MODE_CCFO	smac/hal/ssv6006c/ssv6006C_reg.h	8599;"	d
+GET_RG_BIST_MODE_RX_FFT	smac/hal/ssv6006c/ssv6006C_reg.h	8423;"	d
+GET_RG_BIST_MODE_TX_FFT	smac/hal/ssv6006c/ssv6006C_reg.h	8521;"	d
+GET_RG_BIST_MODE_VTB	smac/hal/ssv6006c/ssv6006C_reg.h	8605;"	d
+GET_RG_BIT_REVERSE	include/ssv6200_reg.h	4194;"	d
+GET_RG_BIT_REVERSE	smac/hal/ssv6006c/ssv6006C_reg.h	8515;"	d
+GET_RG_BP_SMB	include/ssv6200_reg.h	4119;"	d
+GET_RG_BP_SMB	smac/hal/ssv6006c/ssv6006C_reg.h	8441;"	d
+GET_RG_BTRX_BTPASW	smac/hal/ssv6006c/ssv6006C_reg.h	6616;"	d
+GET_RG_BTTX_BTPASW	smac/hal/ssv6006c/ssv6006C_reg.h	6617;"	d
+GET_RG_BT_IDACAI_TZ0_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	7030;"	d
+GET_RG_BT_IDACAI_TZ0_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	7028;"	d
+GET_RG_BT_IDACAI_TZ0_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	7010;"	d
+GET_RG_BT_IDACAI_TZ0_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	7008;"	d
+GET_RG_BT_IDACAI_TZ0_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	7006;"	d
+GET_RG_BT_IDACAI_TZ0_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	7004;"	d
+GET_RG_BT_IDACAI_TZ0_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	7002;"	d
+GET_RG_BT_IDACAI_TZ0_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	7000;"	d
+GET_RG_BT_IDACAI_TZ0_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	7026;"	d
+GET_RG_BT_IDACAI_TZ0_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	7024;"	d
+GET_RG_BT_IDACAI_TZ0_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	7022;"	d
+GET_RG_BT_IDACAI_TZ0_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	7020;"	d
+GET_RG_BT_IDACAI_TZ0_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	7018;"	d
+GET_RG_BT_IDACAI_TZ0_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	7016;"	d
+GET_RG_BT_IDACAI_TZ0_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	7014;"	d
+GET_RG_BT_IDACAI_TZ0_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	7012;"	d
+GET_RG_BT_IDACAI_TZ1_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	7062;"	d
+GET_RG_BT_IDACAI_TZ1_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	7060;"	d
+GET_RG_BT_IDACAI_TZ1_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	7042;"	d
+GET_RG_BT_IDACAI_TZ1_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	7040;"	d
+GET_RG_BT_IDACAI_TZ1_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	7038;"	d
+GET_RG_BT_IDACAI_TZ1_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	7036;"	d
+GET_RG_BT_IDACAI_TZ1_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	7034;"	d
+GET_RG_BT_IDACAI_TZ1_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	7032;"	d
+GET_RG_BT_IDACAI_TZ1_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	7058;"	d
+GET_RG_BT_IDACAI_TZ1_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	7056;"	d
+GET_RG_BT_IDACAI_TZ1_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	7054;"	d
+GET_RG_BT_IDACAI_TZ1_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	7052;"	d
+GET_RG_BT_IDACAI_TZ1_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	7050;"	d
+GET_RG_BT_IDACAI_TZ1_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	7048;"	d
+GET_RG_BT_IDACAI_TZ1_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	7046;"	d
+GET_RG_BT_IDACAI_TZ1_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	7044;"	d
+GET_RG_BT_IDACAQ_TZ0_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	7031;"	d
+GET_RG_BT_IDACAQ_TZ0_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	7029;"	d
+GET_RG_BT_IDACAQ_TZ0_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	7011;"	d
+GET_RG_BT_IDACAQ_TZ0_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	7009;"	d
+GET_RG_BT_IDACAQ_TZ0_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	7007;"	d
+GET_RG_BT_IDACAQ_TZ0_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	7005;"	d
+GET_RG_BT_IDACAQ_TZ0_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	7003;"	d
+GET_RG_BT_IDACAQ_TZ0_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	7001;"	d
+GET_RG_BT_IDACAQ_TZ0_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	7027;"	d
+GET_RG_BT_IDACAQ_TZ0_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	7025;"	d
+GET_RG_BT_IDACAQ_TZ0_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	7023;"	d
+GET_RG_BT_IDACAQ_TZ0_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	7021;"	d
+GET_RG_BT_IDACAQ_TZ0_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	7019;"	d
+GET_RG_BT_IDACAQ_TZ0_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	7017;"	d
+GET_RG_BT_IDACAQ_TZ0_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	7015;"	d
+GET_RG_BT_IDACAQ_TZ0_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	7013;"	d
+GET_RG_BT_IDACAQ_TZ1_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	7063;"	d
+GET_RG_BT_IDACAQ_TZ1_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	7061;"	d
+GET_RG_BT_IDACAQ_TZ1_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	7043;"	d
+GET_RG_BT_IDACAQ_TZ1_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	7041;"	d
+GET_RG_BT_IDACAQ_TZ1_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	7039;"	d
+GET_RG_BT_IDACAQ_TZ1_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	7037;"	d
+GET_RG_BT_IDACAQ_TZ1_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	7035;"	d
+GET_RG_BT_IDACAQ_TZ1_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	7033;"	d
+GET_RG_BT_IDACAQ_TZ1_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	7059;"	d
+GET_RG_BT_IDACAQ_TZ1_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	7057;"	d
+GET_RG_BT_IDACAQ_TZ1_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	7055;"	d
+GET_RG_BT_IDACAQ_TZ1_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	7053;"	d
+GET_RG_BT_IDACAQ_TZ1_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	7051;"	d
+GET_RG_BT_IDACAQ_TZ1_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	7049;"	d
+GET_RG_BT_IDACAQ_TZ1_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	7047;"	d
+GET_RG_BT_IDACAQ_TZ1_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	7045;"	d
+GET_RG_BT_PABIAS_2X	smac/hal/ssv6006c/ssv6006C_reg.h	6618;"	d
+GET_RG_BT_PABIAS_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	6619;"	d
+GET_RG_BT_RX_ABBCFIX	smac/hal/ssv6006c/ssv6006C_reg.h	6579;"	d
+GET_RG_BT_RX_ABBCTUNE	smac/hal/ssv6006c/ssv6006C_reg.h	6573;"	d
+GET_RG_BT_RX_ABB_BT_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	6581;"	d
+GET_RG_BT_RX_ABB_IDIV3	smac/hal/ssv6006c/ssv6006C_reg.h	6582;"	d
+GET_RG_BT_RX_ABB_N_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	6580;"	d
+GET_RG_BT_RX_ADC_CLOAD	smac/hal/ssv6006c/ssv6006C_reg.h	6730;"	d
+GET_RG_BT_RX_ADC_ICMP	smac/hal/ssv6006c/ssv6006C_reg.h	6728;"	d
+GET_RG_BT_RX_ADC_PSW	smac/hal/ssv6006c/ssv6006C_reg.h	6731;"	d
+GET_RG_BT_RX_ADC_VCMI	smac/hal/ssv6006c/ssv6006C_reg.h	6729;"	d
+GET_RG_BT_RX_DCCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	7079;"	d
+GET_RG_BT_RX_EN_IDACA_COARSE	smac/hal/ssv6006c/ssv6006C_reg.h	6583;"	d
+GET_RG_BT_RX_EN_LOOPA	smac/hal/ssv6006c/ssv6006C_reg.h	6584;"	d
+GET_RG_BT_RX_FILTERI1ST	smac/hal/ssv6006c/ssv6006C_reg.h	6576;"	d
+GET_RG_BT_RX_FILTERI2ND	smac/hal/ssv6006c/ssv6006C_reg.h	6577;"	d
+GET_RG_BT_RX_FILTERI3RD	smac/hal/ssv6006c/ssv6006C_reg.h	6578;"	d
+GET_RG_BT_RX_FILTERI_COARSE	smac/hal/ssv6006c/ssv6006C_reg.h	6575;"	d
+GET_RG_BT_RX_FILTERVCM	smac/hal/ssv6006c/ssv6006C_reg.h	6586;"	d
+GET_RG_BT_RX_HG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	6682;"	d
+GET_RG_BT_RX_HG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	6677;"	d
+GET_RG_BT_RX_HG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	6678;"	d
+GET_RG_BT_RX_HG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	6679;"	d
+GET_RG_BT_RX_HG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	6675;"	d
+GET_RG_BT_RX_HG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	6683;"	d
+GET_RG_BT_RX_HG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	6684;"	d
+GET_RG_BT_RX_HG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	6680;"	d
+GET_RG_BT_RX_HG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	6676;"	d
+GET_RG_BT_RX_HG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	6681;"	d
+GET_RG_BT_RX_HG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	6685;"	d
+GET_RG_BT_RX_LG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	6704;"	d
+GET_RG_BT_RX_LG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	6699;"	d
+GET_RG_BT_RX_LG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	6700;"	d
+GET_RG_BT_RX_LG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	6701;"	d
+GET_RG_BT_RX_LG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	6697;"	d
+GET_RG_BT_RX_LG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	6705;"	d
+GET_RG_BT_RX_LG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	6706;"	d
+GET_RG_BT_RX_LG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	6702;"	d
+GET_RG_BT_RX_LG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	6698;"	d
+GET_RG_BT_RX_LG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	6703;"	d
+GET_RG_BT_RX_LG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	6707;"	d
+GET_RG_BT_RX_MG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	6693;"	d
+GET_RG_BT_RX_MG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	6688;"	d
+GET_RG_BT_RX_MG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	6689;"	d
+GET_RG_BT_RX_MG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	6690;"	d
+GET_RG_BT_RX_MG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	6686;"	d
+GET_RG_BT_RX_MG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	6694;"	d
+GET_RG_BT_RX_MG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	6695;"	d
+GET_RG_BT_RX_MG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	6691;"	d
+GET_RG_BT_RX_MG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	6687;"	d
+GET_RG_BT_RX_MG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	6692;"	d
+GET_RG_BT_RX_MG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	6696;"	d
+GET_RG_BT_RX_OUTVCM	smac/hal/ssv6006c/ssv6006C_reg.h	6587;"	d
+GET_RG_BT_RX_TZ_CMZ_C	smac/hal/ssv6006c/ssv6006C_reg.h	6574;"	d
+GET_RG_BT_RX_TZ_CMZ_R	smac/hal/ssv6006c/ssv6006C_reg.h	6585;"	d
+GET_RG_BT_RX_ULG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	6715;"	d
+GET_RG_BT_RX_ULG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	6710;"	d
+GET_RG_BT_RX_ULG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	6711;"	d
+GET_RG_BT_RX_ULG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	6712;"	d
+GET_RG_BT_RX_ULG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	6708;"	d
+GET_RG_BT_RX_ULG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	6716;"	d
+GET_RG_BT_RX_ULG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	6717;"	d
+GET_RG_BT_RX_ULG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	6713;"	d
+GET_RG_BT_RX_ULG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	6709;"	d
+GET_RG_BT_RX_ULG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	6714;"	d
+GET_RG_BT_RX_ULG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	6718;"	d
+GET_RG_BT_TRX_IF	smac/hal/ssv6006c/ssv6006C_reg.h	7578;"	d
+GET_RG_BT_TXLPF_BOOSTI	smac/hal/ssv6006c/ssv6006C_reg.h	6757;"	d
+GET_RG_BT_TXMOD_GMCELL_FINE	smac/hal/ssv6006c/ssv6006C_reg.h	6609;"	d
+GET_RG_BT_TXPGA_CAPSW	smac/hal/ssv6006c/ssv6006C_reg.h	6606;"	d
+GET_RG_BT_TX_DACI1ST	smac/hal/ssv6006c/ssv6006C_reg.h	6751;"	d
+GET_RG_BT_TX_DACLPF_ICOARSE	smac/hal/ssv6006c/ssv6006C_reg.h	6752;"	d
+GET_RG_BT_TX_DACLPF_IFINE	smac/hal/ssv6006c/ssv6006C_reg.h	6753;"	d
+GET_RG_BT_TX_DACLPF_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	6754;"	d
+GET_RG_BT_TX_DAC_CKEDGE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	6759;"	d
+GET_RG_BT_TX_DAC_IATTN	smac/hal/ssv6006c/ssv6006C_reg.h	6756;"	d
+GET_RG_BT_TX_DAC_IBIAS	smac/hal/ssv6006c/ssv6006C_reg.h	6755;"	d
+GET_RG_BT_TX_DAC_IOFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	6761;"	d
+GET_RG_BT_TX_DAC_OS	smac/hal/ssv6006c/ssv6006C_reg.h	6760;"	d
+GET_RG_BT_TX_DAC_QOFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	6762;"	d
+GET_RG_BT_TX_DAC_RCAL	smac/hal/ssv6006c/ssv6006C_reg.h	6758;"	d
+GET_RG_BT_TX_DIV_VSET	smac/hal/ssv6006c/ssv6006C_reg.h	6607;"	d
+GET_RG_BT_TX_GAIN_OFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	6626;"	d
+GET_RG_BT_TX_LOBUF_VSET	smac/hal/ssv6006c/ssv6006C_reg.h	6608;"	d
+GET_RG_BT_TX_PA_VCAS	smac/hal/ssv6006c/ssv6006C_reg.h	6620;"	d
+GET_RG_BUCK_EN_PSM	include/ssv6200_reg.h	2439;"	d
+GET_RG_BUCK_EN_PSM	smac/hal/ssv6006c/ssv6006C_reg.h	8070;"	d
+GET_RG_BUCK_LEVEL	include/ssv6200_reg.h	2433;"	d
+GET_RG_BUCK_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	8068;"	d
+GET_RG_BUCK_LEVEL_SLP	smac/hal/ssv6006c/ssv6006C_reg.h	8159;"	d
+GET_RG_BUCK_PSM_VTH	include/ssv6200_reg.h	2440;"	d
+GET_RG_BUCK_PSM_VTH	smac/hal/ssv6006c/ssv6006C_reg.h	8071;"	d
+GET_RG_BUCK_RCZERO	smac/hal/ssv6006c/ssv6006C_reg.h	8081;"	d
+GET_RG_BUCK_SLOP	smac/hal/ssv6006c/ssv6006C_reg.h	8082;"	d
+GET_RG_BUCK_VREF_SEL	include/ssv6200_reg.h	2434;"	d
+GET_RG_BUCK_VREF_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	8072;"	d
+GET_RG_BW_HT40	smac/hal/ssv6006c/ssv6006C_reg.h	6469;"	d
+GET_RG_BW_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	6470;"	d
+GET_RG_BYPASS_ACI	include/ssv6200_reg.h	3865;"	d
+GET_RG_BYPASS_ACI	smac/hal/ssv6006c/ssv6006C_reg.h	8188;"	d
+GET_RG_BYPASS_AGC	include/ssv6200_reg.h	4131;"	d
+GET_RG_BYPASS_AUDIO_LWDF	smac/hal/ssv6006c/ssv6006C_reg.h	7710;"	d
+GET_RG_BYPASS_COARSE_FREQ	smac/hal/ssv6006c/ssv6006C_reg.h	8629;"	d
+GET_RG_BYPASS_CPE_MA	include/ssv6200_reg.h	4266;"	d
+GET_RG_BYPASS_CPE_MA	smac/hal/ssv6006c/ssv6006C_reg.h	8645;"	d
+GET_RG_BYPASS_DESCRAMBLER	include/ssv6200_reg.h	4130;"	d
+GET_RG_BYPASS_DESCRAMBLER	smac/hal/ssv6006c/ssv6006C_reg.h	8449;"	d
+GET_RG_CAL_INDEX	smac/hal/ssv6006c/ssv6006C_reg.h	6466;"	d
+GET_RG_CBW_20_40	smac/hal/ssv6006c/ssv6006C_reg.h	7604;"	d
+GET_RG_CCA_BIT_CNT_LMT_RX	include/ssv6200_reg.h	4132;"	d
+GET_RG_CCA_BIT_CNT_TH	smac/hal/ssv6006c/ssv6006C_reg.h	8450;"	d
+GET_RG_CCA_POW_CNT_TH	smac/hal/ssv6006c/ssv6006C_reg.h	8616;"	d
+GET_RG_CCA_POW_SHORT_CNT_LMT	smac/hal/ssv6006c/ssv6006C_reg.h	8617;"	d
+GET_RG_CCA_POW_TH	smac/hal/ssv6006c/ssv6006C_reg.h	8618;"	d
+GET_RG_CCA_PWR_CNT_TH	include/ssv6200_reg.h	4177;"	d
+GET_RG_CCA_PWR_SEL	include/ssv6200_reg.h	4330;"	d
+GET_RG_CCA_PWR_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	8689;"	d
+GET_RG_CCA_PWR_TH_RX	include/ssv6200_reg.h	4176;"	d
+GET_RG_CCA_RE_CHK_BIT_CNT_TH	smac/hal/ssv6006c/ssv6006C_reg.h	8447;"	d
+GET_RG_CCA_SCALE_BF	include/ssv6200_reg.h	4133;"	d
+GET_RG_CCA_SCALE_BF	smac/hal/ssv6006c/ssv6006C_reg.h	8451;"	d
+GET_RG_CCA_XSCOR_AVGPWR_SEL	include/ssv6200_reg.h	4332;"	d
+GET_RG_CCA_XSCOR_AVGPWR_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	8691;"	d
+GET_RG_CCA_XSCOR_PWR_SEL	include/ssv6200_reg.h	4331;"	d
+GET_RG_CCA_XSCOR_PWR_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	8690;"	d
+GET_RG_CCFO_CNT_LMT	smac/hal/ssv6006c/ssv6006C_reg.h	8628;"	d
+GET_RG_CCFO_GAIN_BY2	smac/hal/ssv6006c/ssv6006C_reg.h	8630;"	d
+GET_RG_CCK_TR_KI_T2	smac/hal/ssv6006c/ssv6006C_reg.h	8486;"	d
+GET_RG_CCK_TR_KP_T2	smac/hal/ssv6006c/ssv6006C_reg.h	8487;"	d
+GET_RG_CE_BIT_CNT_LMT	include/ssv6200_reg.h	4167;"	d
+GET_RG_CE_BIT_CNT_LMT	smac/hal/ssv6006c/ssv6006C_reg.h	8479;"	d
+GET_RG_CE_BYPASS_TAP	include/ssv6200_reg.h	4196;"	d
+GET_RG_CE_BYPASS_TAP	smac/hal/ssv6006c/ssv6006C_reg.h	8517;"	d
+GET_RG_CE_CH_MAIN_SET	include/ssv6200_reg.h	4168;"	d
+GET_RG_CE_CH_MAIN_SET	smac/hal/ssv6006c/ssv6006C_reg.h	8480;"	d
+GET_RG_CE_DLY_SEL	include/ssv6200_reg.h	4146;"	d
+GET_RG_CE_DLY_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	8462;"	d
+GET_RG_CE_MU_T1	include/ssv6200_reg.h	4145;"	d
+GET_RG_CE_MU_T1	smac/hal/ssv6006c/ssv6006C_reg.h	8461;"	d
+GET_RG_CE_MU_T2	include/ssv6200_reg.h	4153;"	d
+GET_RG_CE_MU_T2	smac/hal/ssv6006c/ssv6006C_reg.h	8465;"	d
+GET_RG_CE_MU_T3	include/ssv6200_reg.h	4152;"	d
+GET_RG_CE_MU_T3	smac/hal/ssv6006c/ssv6006C_reg.h	8464;"	d
+GET_RG_CE_MU_T4	include/ssv6200_reg.h	4151;"	d
+GET_RG_CE_MU_T4	smac/hal/ssv6006c/ssv6006C_reg.h	8463;"	d
+GET_RG_CE_MU_T5	include/ssv6200_reg.h	4150;"	d
+GET_RG_CE_MU_T6	include/ssv6200_reg.h	4149;"	d
+GET_RG_CE_MU_T7	include/ssv6200_reg.h	4148;"	d
+GET_RG_CE_MU_T8	include/ssv6200_reg.h	4147;"	d
+GET_RG_CE_T2_CNT_LMT	include/ssv6200_reg.h	4144;"	d
+GET_RG_CE_T2_CNT_LMT	smac/hal/ssv6006c/ssv6006C_reg.h	8460;"	d
+GET_RG_CE_T3_CNT_LMT	include/ssv6200_reg.h	4143;"	d
+GET_RG_CE_T4_CNT_LMT	include/ssv6200_reg.h	4142;"	d
+GET_RG_CFR_EN	smac/hal/ssv6006c/ssv6006C_reg.h	7938;"	d
+GET_RG_CFR_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7936;"	d
+GET_RG_CFR_PEAK	smac/hal/ssv6006c/ssv6006C_reg.h	7937;"	d
+GET_RG_CHEST_DD_FACTOR	include/ssv6200_reg.h	4272;"	d
+GET_RG_CHEST_DD_FACTOR	smac/hal/ssv6006c/ssv6006C_reg.h	8648;"	d
+GET_RG_CHIP_CNT_SLICER	include/ssv6200_reg.h	4141;"	d
+GET_RG_CHIP_CNT_SLICER	smac/hal/ssv6006c/ssv6006C_reg.h	8459;"	d
+GET_RG_CHSMTH_COEF	include/ssv6200_reg.h	4270;"	d
+GET_RG_CHSMTH_COEF	smac/hal/ssv6006c/ssv6006C_reg.h	8646;"	d
+GET_RG_CHSMTH_EN	include/ssv6200_reg.h	4271;"	d
+GET_RG_CHSMTH_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8647;"	d
+GET_RG_CH_BW	include/ssv6200_reg.h	3891;"	d
+GET_RG_CH_BW	smac/hal/ssv6006c/ssv6006C_reg.h	8210;"	d
+GET_RG_CH_UPDATE	include/ssv6200_reg.h	4273;"	d
+GET_RG_CH_UPDATE	smac/hal/ssv6006c/ssv6006C_reg.h	8649;"	d
+GET_RG_CLK_320M_INV	smac/hal/ssv6006c/ssv6006C_reg.h	7602;"	d
+GET_RG_CLK_RTC_SW	smac/hal/ssv6006c/ssv6006C_reg.h	8111;"	d
+GET_RG_CLK_SAR_SEL	include/ssv6200_reg.h	4629;"	d
+GET_RG_CLK_SAR_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	6737;"	d
+GET_RG_CLOCK_BF_MUAL	smac/hal/ssv6006c/ssv6006C_reg.h	8056;"	d
+GET_RG_CNT_CCA_LMT	include/ssv6200_reg.h	4129;"	d
+GET_RG_CNT_CCA_RE_CHK_LMT	smac/hal/ssv6006c/ssv6006C_reg.h	8448;"	d
+GET_RG_CONTINUOUS_DATA	include/ssv6200_reg.h	3907;"	d
+GET_RG_CONTINUOUS_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	8227;"	d
+GET_RG_CONTINUOUS_DATA_11GN	include/ssv6200_reg.h	4204;"	d
+GET_RG_COR_SEL	include/ssv6200_reg.h	4326;"	d
+GET_RG_COR_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	8687;"	d
+GET_RG_CPE_SEL_16QAM	smac/hal/ssv6006c/ssv6006C_reg.h	8642;"	d
+GET_RG_CPE_SEL_64QAM	smac/hal/ssv6006c/ssv6006C_reg.h	8641;"	d
+GET_RG_CPE_SEL_BPSK	smac/hal/ssv6006c/ssv6006C_reg.h	8644;"	d
+GET_RG_CPE_SEL_QPSK	smac/hal/ssv6006c/ssv6006C_reg.h	8643;"	d
+GET_RG_CR_BIT_CNT_LMT	include/ssv6200_reg.h	4170;"	d
+GET_RG_CR_BIT_CNT_LMT	smac/hal/ssv6006c/ssv6006C_reg.h	8482;"	d
+GET_RG_CR_CNT_UPDATE	include/ssv6200_reg.h	4264;"	d
+GET_RG_CR_CNT_UPDATE	smac/hal/ssv6006c/ssv6006C_reg.h	8639;"	d
+GET_RG_CR_CNT_UPDATE_SGI	smac/hal/ssv6006c/ssv6006C_reg.h	8637;"	d
+GET_RG_CR_KI_T1	include/ssv6200_reg.h	4139;"	d
+GET_RG_CR_KI_T1	smac/hal/ssv6006c/ssv6006C_reg.h	8457;"	d
+GET_RG_CR_KP_T1	include/ssv6200_reg.h	4140;"	d
+GET_RG_CR_KP_T1	smac/hal/ssv6006c/ssv6006C_reg.h	8458;"	d
+GET_RG_CR_LPF_KI_G	include/ssv6200_reg.h	4221;"	d
+GET_RG_CR_LPF_KI_GN	smac/hal/ssv6006c/ssv6006C_reg.h	8550;"	d
+GET_RG_DACI1ST	include/ssv6200_reg.h	4631;"	d
+GET_RG_DAC_DBG_MODE	include/ssv6200_reg.h	3912;"	d
+GET_RG_DAC_DCEN	include/ssv6200_reg.h	3918;"	d
+GET_RG_DAC_DCI	include/ssv6200_reg.h	3920;"	d
+GET_RG_DAC_DCQ	include/ssv6200_reg.h	3919;"	d
+GET_RG_DAC_DC_I	smac/hal/ssv6006c/ssv6006C_reg.h	7606;"	d
+GET_RG_DAC_DC_Q	smac/hal/ssv6006c/ssv6006C_reg.h	7605;"	d
+GET_RG_DAC_EN_MAN	include/ssv6200_reg.h	4022;"	d
+GET_RG_DAC_FALL_TIME	include/ssv6200_reg.h	4034;"	d
+GET_RG_DAC_I_SET	include/ssv6200_reg.h	4021;"	d
+GET_RG_DAC_I_SET	smac/hal/ssv6006c/ssv6006C_reg.h	7609;"	d
+GET_RG_DAC_LBK_EDGE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	8182;"	d
+GET_RG_DAC_MAN_I_EN	include/ssv6200_reg.h	4025;"	d
+GET_RG_DAC_MAN_I_EN	smac/hal/ssv6006c/ssv6006C_reg.h	7610;"	d
+GET_RG_DAC_MAN_Q_EN	include/ssv6200_reg.h	4024;"	d
+GET_RG_DAC_MAN_Q_EN	smac/hal/ssv6006c/ssv6006C_reg.h	7608;"	d
+GET_RG_DAC_Q_SET	include/ssv6200_reg.h	4020;"	d
+GET_RG_DAC_Q_SET	smac/hal/ssv6006c/ssv6006C_reg.h	7607;"	d
+GET_RG_DAC_RISE_TIME	include/ssv6200_reg.h	4030;"	d
+GET_RG_DAC_SGN_SWAP	include/ssv6200_reg.h	3913;"	d
+GET_RG_DAGC_CNT_TH	include/ssv6200_reg.h	4321;"	d
+GET_RG_DAGC_CNT_TH	smac/hal/ssv6006c/ssv6006C_reg.h	8681;"	d
+GET_RG_DATA_SEL	include/ssv6200_reg.h	3908;"	d
+GET_RG_DATA_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	8228;"	d
+GET_RG_DBIST_MODE_16	include/ssv6200_reg.h	4060;"	d
+GET_RG_DBIST_MODE_64	include/ssv6200_reg.h	4298;"	d
+GET_RG_DBIST_MODE_80	include/ssv6200_reg.h	4291;"	d
+GET_RG_DCDC_CLK	smac/hal/ssv6006c/ssv6006C_reg.h	8080;"	d
+GET_RG_DCDC_MODE	include/ssv6200_reg.h	2438;"	d
+GET_RG_DCDC_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	8066;"	d
+GET_RG_DCDC_MODE_SLP	smac/hal/ssv6006c/ssv6006C_reg.h	8157;"	d
+GET_RG_DCDC_PULLLOW_CON	smac/hal/ssv6006c/ssv6006C_reg.h	8075;"	d
+GET_RG_DCDC_RES2_CON	smac/hal/ssv6006c/ssv6006C_reg.h	8076;"	d
+GET_RG_DCDC_RES_CON	smac/hal/ssv6006c/ssv6006C_reg.h	8077;"	d
+GET_RG_DC_RM_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	8299;"	d
+GET_RG_DC_RM_LEAKY_FACTOR_T1	smac/hal/ssv6006c/ssv6006C_reg.h	8302;"	d
+GET_RG_DC_RM_LEAKY_FACTOR_T2	smac/hal/ssv6006c/ssv6006C_reg.h	8301;"	d
+GET_RG_DC_RM_LEAKY_FACTOR_T3	smac/hal/ssv6006c/ssv6006C_reg.h	8300;"	d
+GET_RG_DEBUG_SEL	include/ssv6200_reg.h	4333;"	d
+GET_RG_DEBUG_SEL_11B_RX	smac/hal/ssv6006c/ssv6006C_reg.h	8519;"	d
+GET_RG_DEBUG_SEL_11B_TX	smac/hal/ssv6006c/ssv6006C_reg.h	8443;"	d
+GET_RG_DEBUG_SEL_11GN_RX	smac/hal/ssv6006c/ssv6006C_reg.h	8692;"	d
+GET_RG_DEBUG_SEL_11GN_TX	smac/hal/ssv6006c/ssv6006C_reg.h	8539;"	d
+GET_RG_DES_MAN_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8235;"	d
+GET_RG_DES_RATE	smac/hal/ssv6006c/ssv6006C_reg.h	8234;"	d
+GET_RG_DES_SPD	include/ssv6200_reg.h	4121;"	d
+GET_RG_DICMP	include/ssv6200_reg.h	4623;"	d
+GET_RG_DIOP	include/ssv6200_reg.h	4624;"	d
+GET_RG_DIS_DAC_OFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	7601;"	d
+GET_RG_DLDO_BOOST_IQ	include/ssv6200_reg.h	2432;"	d
+GET_RG_DLDO_BOOST_IQ	smac/hal/ssv6006c/ssv6006C_reg.h	8069;"	d
+GET_RG_DLDO_LEVEL	include/ssv6200_reg.h	2431;"	d
+GET_RG_DLDO_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	8067;"	d
+GET_RG_DLDO_LEVEL_SLP	smac/hal/ssv6006c/ssv6006C_reg.h	8158;"	d
+GET_RG_DO_NOT_CHECK_L_RATE	include/ssv6200_reg.h	4276;"	d
+GET_RG_DO_NOT_CHECK_L_RATE	smac/hal/ssv6006c/ssv6006C_reg.h	8652;"	d
+GET_RG_DPD_020_GAIN	include/ssv6200_reg.h	4413;"	d
+GET_RG_DPD_020_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7954;"	d
+GET_RG_DPD_020_PH	include/ssv6200_reg.h	4439;"	d
+GET_RG_DPD_020_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7980;"	d
+GET_RG_DPD_040_GAIN	include/ssv6200_reg.h	4414;"	d
+GET_RG_DPD_040_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7955;"	d
+GET_RG_DPD_040_PH	include/ssv6200_reg.h	4440;"	d
+GET_RG_DPD_040_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7981;"	d
+GET_RG_DPD_060_GAIN	include/ssv6200_reg.h	4415;"	d
+GET_RG_DPD_060_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7956;"	d
+GET_RG_DPD_060_PH	include/ssv6200_reg.h	4441;"	d
+GET_RG_DPD_060_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7982;"	d
+GET_RG_DPD_080_GAIN	include/ssv6200_reg.h	4416;"	d
+GET_RG_DPD_080_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7957;"	d
+GET_RG_DPD_080_PH	include/ssv6200_reg.h	4442;"	d
+GET_RG_DPD_080_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7983;"	d
+GET_RG_DPD_0A0_GAIN	include/ssv6200_reg.h	4417;"	d
+GET_RG_DPD_0A0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7958;"	d
+GET_RG_DPD_0A0_PH	include/ssv6200_reg.h	4443;"	d
+GET_RG_DPD_0A0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7984;"	d
+GET_RG_DPD_0C0_GAIN	include/ssv6200_reg.h	4418;"	d
+GET_RG_DPD_0C0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7959;"	d
+GET_RG_DPD_0C0_PH	include/ssv6200_reg.h	4444;"	d
+GET_RG_DPD_0C0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7985;"	d
+GET_RG_DPD_0D0_GAIN	include/ssv6200_reg.h	4419;"	d
+GET_RG_DPD_0D0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7960;"	d
+GET_RG_DPD_0D0_PH	include/ssv6200_reg.h	4445;"	d
+GET_RG_DPD_0D0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7986;"	d
+GET_RG_DPD_0E0_GAIN	include/ssv6200_reg.h	4420;"	d
+GET_RG_DPD_0E0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7961;"	d
+GET_RG_DPD_0E0_PH	include/ssv6200_reg.h	4446;"	d
+GET_RG_DPD_0E0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7987;"	d
+GET_RG_DPD_0F0_GAIN	include/ssv6200_reg.h	4421;"	d
+GET_RG_DPD_0F0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7962;"	d
+GET_RG_DPD_0F0_PH	include/ssv6200_reg.h	4447;"	d
+GET_RG_DPD_0F0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7988;"	d
+GET_RG_DPD_100_GAIN	include/ssv6200_reg.h	4422;"	d
+GET_RG_DPD_100_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7963;"	d
+GET_RG_DPD_100_PH	include/ssv6200_reg.h	4448;"	d
+GET_RG_DPD_100_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7989;"	d
+GET_RG_DPD_110_GAIN	include/ssv6200_reg.h	4423;"	d
+GET_RG_DPD_110_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7964;"	d
+GET_RG_DPD_110_PH	include/ssv6200_reg.h	4449;"	d
+GET_RG_DPD_110_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7990;"	d
+GET_RG_DPD_120_GAIN	include/ssv6200_reg.h	4424;"	d
+GET_RG_DPD_120_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7965;"	d
+GET_RG_DPD_120_PH	include/ssv6200_reg.h	4450;"	d
+GET_RG_DPD_120_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7991;"	d
+GET_RG_DPD_130_GAIN	include/ssv6200_reg.h	4425;"	d
+GET_RG_DPD_130_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7966;"	d
+GET_RG_DPD_130_PH	include/ssv6200_reg.h	4451;"	d
+GET_RG_DPD_130_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7992;"	d
+GET_RG_DPD_140_GAIN	include/ssv6200_reg.h	4426;"	d
+GET_RG_DPD_140_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7967;"	d
+GET_RG_DPD_140_PH	include/ssv6200_reg.h	4452;"	d
+GET_RG_DPD_140_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7993;"	d
+GET_RG_DPD_150_GAIN	include/ssv6200_reg.h	4427;"	d
+GET_RG_DPD_150_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7968;"	d
+GET_RG_DPD_150_PH	include/ssv6200_reg.h	4453;"	d
+GET_RG_DPD_150_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7994;"	d
+GET_RG_DPD_160_GAIN	include/ssv6200_reg.h	4428;"	d
+GET_RG_DPD_160_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7969;"	d
+GET_RG_DPD_160_PH	include/ssv6200_reg.h	4454;"	d
+GET_RG_DPD_160_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7995;"	d
+GET_RG_DPD_170_GAIN	include/ssv6200_reg.h	4429;"	d
+GET_RG_DPD_170_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7970;"	d
+GET_RG_DPD_170_PH	include/ssv6200_reg.h	4455;"	d
+GET_RG_DPD_170_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7996;"	d
+GET_RG_DPD_180_GAIN	include/ssv6200_reg.h	4430;"	d
+GET_RG_DPD_180_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7971;"	d
+GET_RG_DPD_180_PH	include/ssv6200_reg.h	4456;"	d
+GET_RG_DPD_180_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7997;"	d
+GET_RG_DPD_190_GAIN	include/ssv6200_reg.h	4431;"	d
+GET_RG_DPD_190_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7972;"	d
+GET_RG_DPD_190_PH	include/ssv6200_reg.h	4457;"	d
+GET_RG_DPD_190_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7998;"	d
+GET_RG_DPD_1A0_GAIN	include/ssv6200_reg.h	4432;"	d
+GET_RG_DPD_1A0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7973;"	d
+GET_RG_DPD_1A0_PH	include/ssv6200_reg.h	4458;"	d
+GET_RG_DPD_1A0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7999;"	d
+GET_RG_DPD_1B0_GAIN	include/ssv6200_reg.h	4433;"	d
+GET_RG_DPD_1B0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7974;"	d
+GET_RG_DPD_1B0_PH	include/ssv6200_reg.h	4459;"	d
+GET_RG_DPD_1B0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	8000;"	d
+GET_RG_DPD_1C0_GAIN	include/ssv6200_reg.h	4434;"	d
+GET_RG_DPD_1C0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7975;"	d
+GET_RG_DPD_1C0_PH	include/ssv6200_reg.h	4460;"	d
+GET_RG_DPD_1C0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	8001;"	d
+GET_RG_DPD_1D0_GAIN	include/ssv6200_reg.h	4435;"	d
+GET_RG_DPD_1D0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7976;"	d
+GET_RG_DPD_1D0_PH	include/ssv6200_reg.h	4461;"	d
+GET_RG_DPD_1D0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	8002;"	d
+GET_RG_DPD_1E0_GAIN	include/ssv6200_reg.h	4436;"	d
+GET_RG_DPD_1E0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7977;"	d
+GET_RG_DPD_1E0_PH	include/ssv6200_reg.h	4462;"	d
+GET_RG_DPD_1E0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	8003;"	d
+GET_RG_DPD_1F0_GAIN	include/ssv6200_reg.h	4437;"	d
+GET_RG_DPD_1F0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7978;"	d
+GET_RG_DPD_1F0_PH	include/ssv6200_reg.h	4463;"	d
+GET_RG_DPD_1F0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	8004;"	d
+GET_RG_DPD_200_GAIN	include/ssv6200_reg.h	4438;"	d
+GET_RG_DPD_200_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7979;"	d
+GET_RG_DPD_200_PH	include/ssv6200_reg.h	4464;"	d
+GET_RG_DPD_200_PH	smac/hal/ssv6006c/ssv6006C_reg.h	8005;"	d
+GET_RG_DPD_5100_020_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7718;"	d
+GET_RG_DPD_5100_020_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7744;"	d
+GET_RG_DPD_5100_040_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7719;"	d
+GET_RG_DPD_5100_040_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7745;"	d
+GET_RG_DPD_5100_060_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7720;"	d
+GET_RG_DPD_5100_060_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7746;"	d
+GET_RG_DPD_5100_080_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7721;"	d
+GET_RG_DPD_5100_080_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7747;"	d
+GET_RG_DPD_5100_0A0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7722;"	d
+GET_RG_DPD_5100_0A0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7748;"	d
+GET_RG_DPD_5100_0C0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7723;"	d
+GET_RG_DPD_5100_0C0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7749;"	d
+GET_RG_DPD_5100_0D0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7724;"	d
+GET_RG_DPD_5100_0D0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7750;"	d
+GET_RG_DPD_5100_0E0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7725;"	d
+GET_RG_DPD_5100_0E0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7751;"	d
+GET_RG_DPD_5100_0F0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7726;"	d
+GET_RG_DPD_5100_0F0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7752;"	d
+GET_RG_DPD_5100_100_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7727;"	d
+GET_RG_DPD_5100_100_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7753;"	d
+GET_RG_DPD_5100_110_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7728;"	d
+GET_RG_DPD_5100_110_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7754;"	d
+GET_RG_DPD_5100_120_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7729;"	d
+GET_RG_DPD_5100_120_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7755;"	d
+GET_RG_DPD_5100_130_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7730;"	d
+GET_RG_DPD_5100_130_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7756;"	d
+GET_RG_DPD_5100_140_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7731;"	d
+GET_RG_DPD_5100_140_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7757;"	d
+GET_RG_DPD_5100_150_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7732;"	d
+GET_RG_DPD_5100_150_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7758;"	d
+GET_RG_DPD_5100_160_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7733;"	d
+GET_RG_DPD_5100_160_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7759;"	d
+GET_RG_DPD_5100_170_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7734;"	d
+GET_RG_DPD_5100_170_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7760;"	d
+GET_RG_DPD_5100_180_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7735;"	d
+GET_RG_DPD_5100_180_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7761;"	d
+GET_RG_DPD_5100_190_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7736;"	d
+GET_RG_DPD_5100_190_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7762;"	d
+GET_RG_DPD_5100_1A0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7737;"	d
+GET_RG_DPD_5100_1A0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7763;"	d
+GET_RG_DPD_5100_1B0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7738;"	d
+GET_RG_DPD_5100_1B0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7764;"	d
+GET_RG_DPD_5100_1C0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7739;"	d
+GET_RG_DPD_5100_1C0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7765;"	d
+GET_RG_DPD_5100_1D0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7740;"	d
+GET_RG_DPD_5100_1D0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7766;"	d
+GET_RG_DPD_5100_1E0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7741;"	d
+GET_RG_DPD_5100_1E0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7767;"	d
+GET_RG_DPD_5100_1F0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7742;"	d
+GET_RG_DPD_5100_1F0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7768;"	d
+GET_RG_DPD_5100_200_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7743;"	d
+GET_RG_DPD_5100_200_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7769;"	d
+GET_RG_DPD_5500_020_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7770;"	d
+GET_RG_DPD_5500_020_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7796;"	d
+GET_RG_DPD_5500_040_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7771;"	d
+GET_RG_DPD_5500_040_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7797;"	d
+GET_RG_DPD_5500_060_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7772;"	d
+GET_RG_DPD_5500_060_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7798;"	d
+GET_RG_DPD_5500_080_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7773;"	d
+GET_RG_DPD_5500_080_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7799;"	d
+GET_RG_DPD_5500_0A0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7774;"	d
+GET_RG_DPD_5500_0A0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7800;"	d
+GET_RG_DPD_5500_0C0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7775;"	d
+GET_RG_DPD_5500_0C0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7801;"	d
+GET_RG_DPD_5500_0D0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7776;"	d
+GET_RG_DPD_5500_0D0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7802;"	d
+GET_RG_DPD_5500_0E0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7777;"	d
+GET_RG_DPD_5500_0E0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7803;"	d
+GET_RG_DPD_5500_0F0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7778;"	d
+GET_RG_DPD_5500_0F0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7804;"	d
+GET_RG_DPD_5500_100_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7779;"	d
+GET_RG_DPD_5500_100_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7805;"	d
+GET_RG_DPD_5500_110_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7780;"	d
+GET_RG_DPD_5500_110_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7806;"	d
+GET_RG_DPD_5500_120_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7781;"	d
+GET_RG_DPD_5500_120_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7807;"	d
+GET_RG_DPD_5500_130_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7782;"	d
+GET_RG_DPD_5500_130_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7808;"	d
+GET_RG_DPD_5500_140_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7783;"	d
+GET_RG_DPD_5500_140_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7809;"	d
+GET_RG_DPD_5500_150_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7784;"	d
+GET_RG_DPD_5500_150_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7810;"	d
+GET_RG_DPD_5500_160_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7785;"	d
+GET_RG_DPD_5500_160_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7811;"	d
+GET_RG_DPD_5500_170_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7786;"	d
+GET_RG_DPD_5500_170_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7812;"	d
+GET_RG_DPD_5500_180_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7787;"	d
+GET_RG_DPD_5500_180_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7813;"	d
+GET_RG_DPD_5500_190_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7788;"	d
+GET_RG_DPD_5500_190_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7814;"	d
+GET_RG_DPD_5500_1A0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7789;"	d
+GET_RG_DPD_5500_1A0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7815;"	d
+GET_RG_DPD_5500_1B0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7790;"	d
+GET_RG_DPD_5500_1B0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7816;"	d
+GET_RG_DPD_5500_1C0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7791;"	d
+GET_RG_DPD_5500_1C0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7817;"	d
+GET_RG_DPD_5500_1D0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7792;"	d
+GET_RG_DPD_5500_1D0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7818;"	d
+GET_RG_DPD_5500_1E0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7793;"	d
+GET_RG_DPD_5500_1E0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7819;"	d
+GET_RG_DPD_5500_1F0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7794;"	d
+GET_RG_DPD_5500_1F0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7820;"	d
+GET_RG_DPD_5500_200_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7795;"	d
+GET_RG_DPD_5500_200_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7821;"	d
+GET_RG_DPD_5700_020_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7822;"	d
+GET_RG_DPD_5700_020_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7848;"	d
+GET_RG_DPD_5700_040_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7823;"	d
+GET_RG_DPD_5700_040_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7849;"	d
+GET_RG_DPD_5700_060_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7824;"	d
+GET_RG_DPD_5700_060_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7850;"	d
+GET_RG_DPD_5700_080_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7825;"	d
+GET_RG_DPD_5700_080_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7851;"	d
+GET_RG_DPD_5700_0A0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7826;"	d
+GET_RG_DPD_5700_0A0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7852;"	d
+GET_RG_DPD_5700_0C0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7827;"	d
+GET_RG_DPD_5700_0C0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7853;"	d
+GET_RG_DPD_5700_0D0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7828;"	d
+GET_RG_DPD_5700_0D0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7854;"	d
+GET_RG_DPD_5700_0E0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7829;"	d
+GET_RG_DPD_5700_0E0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7855;"	d
+GET_RG_DPD_5700_0F0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7830;"	d
+GET_RG_DPD_5700_0F0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7856;"	d
+GET_RG_DPD_5700_100_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7831;"	d
+GET_RG_DPD_5700_100_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7857;"	d
+GET_RG_DPD_5700_110_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7832;"	d
+GET_RG_DPD_5700_110_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7858;"	d
+GET_RG_DPD_5700_120_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7833;"	d
+GET_RG_DPD_5700_120_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7859;"	d
+GET_RG_DPD_5700_130_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7834;"	d
+GET_RG_DPD_5700_130_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7860;"	d
+GET_RG_DPD_5700_140_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7835;"	d
+GET_RG_DPD_5700_140_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7861;"	d
+GET_RG_DPD_5700_150_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7836;"	d
+GET_RG_DPD_5700_150_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7862;"	d
+GET_RG_DPD_5700_160_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7837;"	d
+GET_RG_DPD_5700_160_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7863;"	d
+GET_RG_DPD_5700_170_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7838;"	d
+GET_RG_DPD_5700_170_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7864;"	d
+GET_RG_DPD_5700_180_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7839;"	d
+GET_RG_DPD_5700_180_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7865;"	d
+GET_RG_DPD_5700_190_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7840;"	d
+GET_RG_DPD_5700_190_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7866;"	d
+GET_RG_DPD_5700_1A0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7841;"	d
+GET_RG_DPD_5700_1A0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7867;"	d
+GET_RG_DPD_5700_1B0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7842;"	d
+GET_RG_DPD_5700_1B0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7868;"	d
+GET_RG_DPD_5700_1C0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7843;"	d
+GET_RG_DPD_5700_1C0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7869;"	d
+GET_RG_DPD_5700_1D0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7844;"	d
+GET_RG_DPD_5700_1D0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7870;"	d
+GET_RG_DPD_5700_1E0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7845;"	d
+GET_RG_DPD_5700_1E0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7871;"	d
+GET_RG_DPD_5700_1F0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7846;"	d
+GET_RG_DPD_5700_1F0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7872;"	d
+GET_RG_DPD_5700_200_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7847;"	d
+GET_RG_DPD_5700_200_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7873;"	d
+GET_RG_DPD_5900_020_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7874;"	d
+GET_RG_DPD_5900_020_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7900;"	d
+GET_RG_DPD_5900_040_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7875;"	d
+GET_RG_DPD_5900_040_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7901;"	d
+GET_RG_DPD_5900_060_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7876;"	d
+GET_RG_DPD_5900_060_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7902;"	d
+GET_RG_DPD_5900_080_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7877;"	d
+GET_RG_DPD_5900_080_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7903;"	d
+GET_RG_DPD_5900_0A0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7878;"	d
+GET_RG_DPD_5900_0A0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7904;"	d
+GET_RG_DPD_5900_0C0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7879;"	d
+GET_RG_DPD_5900_0C0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7905;"	d
+GET_RG_DPD_5900_0D0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7880;"	d
+GET_RG_DPD_5900_0D0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7906;"	d
+GET_RG_DPD_5900_0E0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7881;"	d
+GET_RG_DPD_5900_0E0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7907;"	d
+GET_RG_DPD_5900_0F0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7882;"	d
+GET_RG_DPD_5900_0F0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7908;"	d
+GET_RG_DPD_5900_100_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7883;"	d
+GET_RG_DPD_5900_100_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7909;"	d
+GET_RG_DPD_5900_110_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7884;"	d
+GET_RG_DPD_5900_110_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7910;"	d
+GET_RG_DPD_5900_120_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7885;"	d
+GET_RG_DPD_5900_120_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7911;"	d
+GET_RG_DPD_5900_130_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7886;"	d
+GET_RG_DPD_5900_130_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7912;"	d
+GET_RG_DPD_5900_140_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7887;"	d
+GET_RG_DPD_5900_140_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7913;"	d
+GET_RG_DPD_5900_150_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7888;"	d
+GET_RG_DPD_5900_150_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7914;"	d
+GET_RG_DPD_5900_160_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7889;"	d
+GET_RG_DPD_5900_160_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7915;"	d
+GET_RG_DPD_5900_170_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7890;"	d
+GET_RG_DPD_5900_170_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7916;"	d
+GET_RG_DPD_5900_180_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7891;"	d
+GET_RG_DPD_5900_180_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7917;"	d
+GET_RG_DPD_5900_190_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7892;"	d
+GET_RG_DPD_5900_190_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7918;"	d
+GET_RG_DPD_5900_1A0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7893;"	d
+GET_RG_DPD_5900_1A0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7919;"	d
+GET_RG_DPD_5900_1B0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7894;"	d
+GET_RG_DPD_5900_1B0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7920;"	d
+GET_RG_DPD_5900_1C0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7895;"	d
+GET_RG_DPD_5900_1C0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7921;"	d
+GET_RG_DPD_5900_1D0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7896;"	d
+GET_RG_DPD_5900_1D0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7922;"	d
+GET_RG_DPD_5900_1E0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7897;"	d
+GET_RG_DPD_5900_1E0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7923;"	d
+GET_RG_DPD_5900_1F0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7898;"	d
+GET_RG_DPD_5900_1F0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7924;"	d
+GET_RG_DPD_5900_200_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7899;"	d
+GET_RG_DPD_5900_200_PH	smac/hal/ssv6006c/ssv6006C_reg.h	7925;"	d
+GET_RG_DPD_AM_EN	include/ssv6200_reg.h	4410;"	d
+GET_RG_DPD_AM_EN	smac/hal/ssv6006c/ssv6006C_reg.h	7951;"	d
+GET_RG_DPD_BB_SCALE_2500	smac/hal/ssv6006c/ssv6006C_reg.h	8010;"	d
+GET_RG_DPD_BB_SCALE_5100	smac/hal/ssv6006c/ssv6006C_reg.h	8009;"	d
+GET_RG_DPD_BB_SCALE_5500	smac/hal/ssv6006c/ssv6006C_reg.h	8008;"	d
+GET_RG_DPD_BB_SCALE_5700	smac/hal/ssv6006c/ssv6006C_reg.h	8007;"	d
+GET_RG_DPD_BB_SCALE_5900	smac/hal/ssv6006c/ssv6006C_reg.h	8006;"	d
+GET_RG_DPD_GAIN_EST_EN	include/ssv6200_reg.h	4378;"	d
+GET_RG_DPD_GAIN_EST_X0	include/ssv6200_reg.h	4468;"	d
+GET_RG_DPD_GAIN_EST_Y0	include/ssv6200_reg.h	4465;"	d
+GET_RG_DPD_GAIN_EST_Y1	include/ssv6200_reg.h	4466;"	d
+GET_RG_DPD_LOOP_GAIN	include/ssv6200_reg.h	4467;"	d
+GET_RG_DPD_PM_AMSEL	include/ssv6200_reg.h	4412;"	d
+GET_RG_DPD_PM_AMSEL	smac/hal/ssv6006c/ssv6006C_reg.h	7953;"	d
+GET_RG_DPD_PM_EN	include/ssv6200_reg.h	4411;"	d
+GET_RG_DPD_PM_EN	smac/hal/ssv6006c/ssv6006C_reg.h	7952;"	d
+GET_RG_DPLL_CLK320BY2	smac/hal/ssv6006c/ssv6006C_reg.h	7603;"	d
+GET_RG_DPL_MOD_ORDER	include/ssv6200_reg.h	4658;"	d
+GET_RG_DPL_MOD_ORDER	smac/hal/ssv6006c/ssv6006C_reg.h	8136;"	d
+GET_RG_DPL_RFCTRL_CH	include/ssv6200_reg.h	4785;"	d
+GET_RG_DPL_RFCTRL_CH	smac/hal/ssv6006c/ssv6006C_reg.h	8156;"	d
+GET_RG_DPL_RFCTRL_F	include/ssv6200_reg.h	4789;"	d
+GET_RG_DPL_RFCTRL_F	smac/hal/ssv6006c/ssv6006C_reg.h	8155;"	d
+GET_RG_DPL_SETTLING_TIMMER	smac/hal/ssv6006c/ssv6006C_reg.h	8060;"	d
+GET_RG_DP_ADC320_DIVBY2_BT	smac/hal/ssv6006c/ssv6006C_reg.h	8133;"	d
+GET_RG_DP_ADC320_DIVBY2_WF	smac/hal/ssv6006c/ssv6006C_reg.h	8134;"	d
+GET_RG_DP_AUTOMAP_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8117;"	d
+GET_RG_DP_BBPLL_BP	include/ssv6200_reg.h	4712;"	d
+GET_RG_DP_BBPLL_BP	smac/hal/ssv6006c/ssv6006C_reg.h	8129;"	d
+GET_RG_DP_BBPLL_BS	include/ssv6200_reg.h	4728;"	d
+GET_RG_DP_BBPLL_BS	smac/hal/ssv6006c/ssv6006C_reg.h	8153;"	d
+GET_RG_DP_BBPLL_ICP	include/ssv6200_reg.h	4713;"	d
+GET_RG_DP_BBPLL_ICP	smac/hal/ssv6006c/ssv6006C_reg.h	8142;"	d
+GET_RG_DP_BBPLL_IDUAL	include/ssv6200_reg.h	4714;"	d
+GET_RG_DP_BBPLL_IDUAL	smac/hal/ssv6006c/ssv6006C_reg.h	8143;"	d
+GET_RG_DP_BBPLL_OD_TEST	include/ssv6200_reg.h	4715;"	d
+GET_RG_DP_BBPLL_PD	include/ssv6200_reg.h	4716;"	d
+GET_RG_DP_BBPLL_PD	smac/hal/ssv6006c/ssv6006C_reg.h	8128;"	d
+GET_RG_DP_BBPLL_PFD_DLY	include/ssv6200_reg.h	4718;"	d
+GET_RG_DP_BBPLL_PFD_DLY	smac/hal/ssv6006c/ssv6006C_reg.h	8147;"	d
+GET_RG_DP_BBPLL_SDM_EDGE	include/ssv6200_reg.h	4721;"	d
+GET_RG_DP_BBPLL_SDM_EDGE	smac/hal/ssv6006c/ssv6006C_reg.h	8154;"	d
+GET_RG_DP_BBPLL_TESTSEL	include/ssv6200_reg.h	4717;"	d
+GET_RG_DP_BBPLL_TESTSEL	smac/hal/ssv6006c/ssv6006C_reg.h	8141;"	d
+GET_RG_DP_CK320BY2	include/ssv6200_reg.h	4710;"	d
+GET_RG_DP_CP_IOST	smac/hal/ssv6006c/ssv6006C_reg.h	8145;"	d
+GET_RG_DP_CP_IOSTPOL	smac/hal/ssv6006c/ssv6006C_reg.h	8144;"	d
+GET_RG_DP_DAC320_DIVBY2	smac/hal/ssv6006c/ssv6006C_reg.h	8132;"	d
+GET_RG_DP_FODIV	include/ssv6200_reg.h	4722;"	d
+GET_RG_DP_FODIV	smac/hal/ssv6006c/ssv6006C_reg.h	8138;"	d
+GET_RG_DP_FREF_DOUB	smac/hal/ssv6006c/ssv6006C_reg.h	8131;"	d
+GET_RG_DP_LDO_LEVEL	include/ssv6200_reg.h	4525;"	d
+GET_RG_DP_LDO_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	8115;"	d
+GET_RG_DP_OD_TEST	include/ssv6200_reg.h	4711;"	d
+GET_RG_DP_OD_TEST	smac/hal/ssv6006c/ssv6006C_reg.h	8140;"	d
+GET_RG_DP_PFD_PFDSEL	smac/hal/ssv6006c/ssv6006C_reg.h	8146;"	d
+GET_RG_DP_REFDIV	include/ssv6200_reg.h	4723;"	d
+GET_RG_DP_REFDIV	smac/hal/ssv6006c/ssv6006C_reg.h	8137;"	d
+GET_RG_DP_RHP	include/ssv6200_reg.h	4720;"	d
+GET_RG_DP_RHP	smac/hal/ssv6006c/ssv6006C_reg.h	8149;"	d
+GET_RG_DP_RP	include/ssv6200_reg.h	4719;"	d
+GET_RG_DP_RP	smac/hal/ssv6006c/ssv6006C_reg.h	8148;"	d
+GET_RG_DP_VT_TH_HI	include/ssv6200_reg.h	4708;"	d
+GET_RG_DP_VT_TH_HI	smac/hal/ssv6006c/ssv6006C_reg.h	8151;"	d
+GET_RG_DP_VT_TH_LO	include/ssv6200_reg.h	4709;"	d
+GET_RG_DP_VT_TH_LO	smac/hal/ssv6006c/ssv6006C_reg.h	8152;"	d
+GET_RG_DP_XTAL_FREQ	smac/hal/ssv6006c/ssv6006C_reg.h	8127;"	d
+GET_RG_EDCCA_AVG_T	smac/hal/ssv6006c/ssv6006C_reg.h	8310;"	d
+GET_RG_EDCCA_STAT_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8311;"	d
+GET_RG_EN_AAC5GB_MXPDSW	smac/hal/ssv6006c/ssv6006C_reg.h	7399;"	d
+GET_RG_EN_AAC5GB_RPPDSW	smac/hal/ssv6006c/ssv6006C_reg.h	7400;"	d
+GET_RG_EN_AAC5GB_VOPDSW	smac/hal/ssv6006c/ssv6006C_reg.h	7398;"	d
+GET_RG_EN_ADC	include/ssv6200_reg.h	4493;"	d
+GET_RG_EN_ADC_320M	smac/hal/ssv6006c/ssv6006C_reg.h	8118;"	d
+GET_RG_EN_CLK_960MBY13_UART	include/ssv6200_reg.h	4500;"	d
+GET_RG_EN_DLDO_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	8042;"	d
+GET_RG_EN_DLDO_BYP_AUTO	smac/hal/ssv6006c/ssv6006C_reg.h	8163;"	d
+GET_RG_EN_DLDO_HALF_IQ	smac/hal/ssv6006c/ssv6006C_reg.h	8043;"	d
+GET_RG_EN_DLDO_HALF_IQ_SLP	smac/hal/ssv6006c/ssv6006C_reg.h	8162;"	d
+GET_RG_EN_DPL_MOD	include/ssv6200_reg.h	4657;"	d
+GET_RG_EN_DPL_MOD	smac/hal/ssv6006c/ssv6006C_reg.h	8135;"	d
+GET_RG_EN_DP_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	8130;"	d
+GET_RG_EN_DP_VT_MON	include/ssv6200_reg.h	4707;"	d
+GET_RG_EN_DP_VT_MON	smac/hal/ssv6006c/ssv6006C_reg.h	8150;"	d
+GET_RG_EN_FDB	smac/hal/ssv6006c/ssv6006C_reg.h	8046;"	d
+GET_RG_EN_FDB_DCC_MUAL	smac/hal/ssv6006c/ssv6006C_reg.h	8051;"	d
+GET_RG_EN_FDB_DELAYC_MUAL	smac/hal/ssv6006c/ssv6006C_reg.h	8052;"	d
+GET_RG_EN_FDB_DELAYF_MUAL	smac/hal/ssv6006c/ssv6006C_reg.h	8053;"	d
+GET_RG_EN_FDB_PHASESWAP_MUAL	smac/hal/ssv6006c/ssv6006C_reg.h	8054;"	d
+GET_RG_EN_FDB_RECAL	smac/hal/ssv6006c/ssv6006C_reg.h	8064;"	d
+GET_RG_EN_HSDIV_OBF_MX	smac/hal/ssv6006c/ssv6006C_reg.h	7284;"	d
+GET_RG_EN_HSDIV_OBF_MX_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	7283;"	d
+GET_RG_EN_HSDIV_OBF_SX	smac/hal/ssv6006c/ssv6006C_reg.h	7282;"	d
+GET_RG_EN_HSDIV_OBF_SX_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	7281;"	d
+GET_RG_EN_IOTADC_160M	smac/hal/ssv6006c/ssv6006C_reg.h	8119;"	d
+GET_RG_EN_IOT_ADC	smac/hal/ssv6006c/ssv6006C_reg.h	6503;"	d
+GET_RG_EN_IOT_ADC_BUF	smac/hal/ssv6006c/ssv6006C_reg.h	6502;"	d
+GET_RG_EN_IQPAD_IOSW	include/ssv6200_reg.h	4516;"	d
+GET_RG_EN_IREF_RX	include/ssv6200_reg.h	4512;"	d
+GET_RG_EN_IREF_RX	smac/hal/ssv6006c/ssv6006C_reg.h	6506;"	d
+GET_RG_EN_LDO_5G_CP	smac/hal/ssv6006c/ssv6006C_reg.h	7298;"	d
+GET_RG_EN_LDO_5G_CP_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	7149;"	d
+GET_RG_EN_LDO_5G_CP_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	7306;"	d
+GET_RG_EN_LDO_5G_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	7299;"	d
+GET_RG_EN_LDO_5G_DIV_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	7154;"	d
+GET_RG_EN_LDO_5G_DIV_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	7307;"	d
+GET_RG_EN_LDO_5G_LO	smac/hal/ssv6006c/ssv6006C_reg.h	7300;"	d
+GET_RG_EN_LDO_5G_LO_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	7151;"	d
+GET_RG_EN_LDO_5G_LO_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	7308;"	d
+GET_RG_EN_LDO_5G_VCO	smac/hal/ssv6006c/ssv6006C_reg.h	7301;"	d
+GET_RG_EN_LDO_5G_VCO_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	7309;"	d
+GET_RG_EN_LDO_5G_VCO_PSW	smac/hal/ssv6006c/ssv6006C_reg.h	7304;"	d
+GET_RG_EN_LDO_5G_VCO_VDD33	smac/hal/ssv6006c/ssv6006C_reg.h	7305;"	d
+GET_RG_EN_LDO_ABB	include/ssv6200_reg.h	4508;"	d
+GET_RG_EN_LDO_AFE	include/ssv6200_reg.h	4509;"	d
+GET_RG_EN_LDO_AFE	smac/hal/ssv6006c/ssv6006C_reg.h	6505;"	d
+GET_RG_EN_LDO_CP	smac/hal/ssv6006c/ssv6006C_reg.h	6791;"	d
+GET_RG_EN_LDO_CP_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	6537;"	d
+GET_RG_EN_LDO_CP_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	6797;"	d
+GET_RG_EN_LDO_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	6792;"	d
+GET_RG_EN_LDO_DIV_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	6542;"	d
+GET_RG_EN_LDO_DIV_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	6798;"	d
+GET_RG_EN_LDO_DP_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	8116;"	d
+GET_RG_EN_LDO_DP_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	8139;"	d
+GET_RG_EN_LDO_EFUSE	smac/hal/ssv6006c/ssv6006C_reg.h	8074;"	d
+GET_RG_EN_LDO_LO	smac/hal/ssv6006c/ssv6006C_reg.h	6793;"	d
+GET_RG_EN_LDO_LO_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	6539;"	d
+GET_RG_EN_LDO_LO_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	6799;"	d
+GET_RG_EN_LDO_RX_AFE_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	6535;"	d
+GET_RG_EN_LDO_RX_AFE_FC	smac/hal/ssv6006c/ssv6006C_reg.h	6528;"	d
+GET_RG_EN_LDO_RX_AFE_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	6530;"	d
+GET_RG_EN_LDO_RX_FE	include/ssv6200_reg.h	4507;"	d
+GET_RG_EN_LDO_RX_FE	smac/hal/ssv6006c/ssv6006C_reg.h	6504;"	d
+GET_RG_EN_LDO_RX_FE_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	6533;"	d
+GET_RG_EN_LDO_RX_FE_FC	smac/hal/ssv6006c/ssv6006C_reg.h	6527;"	d
+GET_RG_EN_LDO_RX_FE_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	6529;"	d
+GET_RG_EN_LDO_VCO	smac/hal/ssv6006c/ssv6006C_reg.h	6794;"	d
+GET_RG_EN_LDO_VCO_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	6800;"	d
+GET_RG_EN_LDO_VCO_PSW	smac/hal/ssv6006c/ssv6006C_reg.h	6795;"	d
+GET_RG_EN_LDO_VCO_VDD33	smac/hal/ssv6006c/ssv6006C_reg.h	6796;"	d
+GET_RG_EN_LDO_XO_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	8041;"	d
+GET_RG_EN_LDO_XO_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	8040;"	d
+GET_RG_EN_MAC_120M	smac/hal/ssv6006c/ssv6006C_reg.h	8122;"	d
+GET_RG_EN_MAC_160M	smac/hal/ssv6006c/ssv6006C_reg.h	8126;"	d
+GET_RG_EN_MAC_80M	smac/hal/ssv6006c/ssv6006C_reg.h	8120;"	d
+GET_RG_EN_MAC_96M	smac/hal/ssv6006c/ssv6006C_reg.h	8121;"	d
+GET_RG_EN_MANUAL	include/ssv6200_reg.h	4474;"	d
+GET_RG_EN_PHY_160M	smac/hal/ssv6006c/ssv6006C_reg.h	8124;"	d
+GET_RG_EN_PHY_320M	smac/hal/ssv6006c/ssv6006C_reg.h	8125;"	d
+GET_RG_EN_PHY_80M	smac/hal/ssv6006c/ssv6006C_reg.h	8123;"	d
+GET_RG_EN_RCAL	include/ssv6200_reg.h	4757;"	d
+GET_RG_EN_RTC_CAL	smac/hal/ssv6006c/ssv6006C_reg.h	8089;"	d
+GET_RG_EN_RX_ADC	smac/hal/ssv6006c/ssv6006C_reg.h	6487;"	d
+GET_RG_EN_RX_DIV2	include/ssv6200_reg.h	4487;"	d
+GET_RG_EN_RX_DIV2	smac/hal/ssv6006c/ssv6006C_reg.h	6479;"	d
+GET_RG_EN_RX_FILTER	include/ssv6200_reg.h	4490;"	d
+GET_RG_EN_RX_FILTER	smac/hal/ssv6006c/ssv6006C_reg.h	6485;"	d
+GET_RG_EN_RX_HPF	include/ssv6200_reg.h	4491;"	d
+GET_RG_EN_RX_IQCAL	include/ssv6200_reg.h	4503;"	d
+GET_RG_EN_RX_IQCAL	smac/hal/ssv6006c/ssv6006C_reg.h	6514;"	d
+GET_RG_EN_RX_LNA	include/ssv6200_reg.h	4485;"	d
+GET_RG_EN_RX_LNA	smac/hal/ssv6006c/ssv6006C_reg.h	6475;"	d
+GET_RG_EN_RX_LOBF	include/ssv6200_reg.h	4498;"	d
+GET_RG_EN_RX_LOBUF	include/ssv6200_reg.h	4488;"	d
+GET_RG_EN_RX_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	6481;"	d
+GET_RG_EN_RX_MIXER	include/ssv6200_reg.h	4486;"	d
+GET_RG_EN_RX_MIXER	smac/hal/ssv6006c/ssv6006C_reg.h	6477;"	d
+GET_RG_EN_RX_PADSW	include/ssv6200_reg.h	4528;"	d
+GET_RG_EN_RX_PADSW	smac/hal/ssv6006c/ssv6006C_reg.h	6526;"	d
+GET_RG_EN_RX_RSSI	include/ssv6200_reg.h	4492;"	d
+GET_RG_EN_RX_RSSI	smac/hal/ssv6006c/ssv6006C_reg.h	6489;"	d
+GET_RG_EN_RX_RSSI_TESTNODE	include/ssv6200_reg.h	4554;"	d
+GET_RG_EN_RX_RSSI_TESTNODE	smac/hal/ssv6006c/ssv6006C_reg.h	6599;"	d
+GET_RG_EN_RX_TESTNODE	include/ssv6200_reg.h	4529;"	d
+GET_RG_EN_RX_TESTNODE	smac/hal/ssv6006c/ssv6006C_reg.h	6525;"	d
+GET_RG_EN_RX_TZ	include/ssv6200_reg.h	4489;"	d
+GET_RG_EN_RX_TZ	smac/hal/ssv6006c/ssv6006C_reg.h	6483;"	d
+GET_RG_EN_SARADC	include/ssv6200_reg.h	4630;"	d
+GET_RG_EN_SARADC	smac/hal/ssv6006c/ssv6006C_reg.h	6518;"	d
+GET_RG_EN_SAR_TEST	include/ssv6200_reg.h	4626;"	d
+GET_RG_EN_SAR_TEST	smac/hal/ssv6006c/ssv6006C_reg.h	6734;"	d
+GET_RG_EN_SRVC	include/ssv6200_reg.h	4120;"	d
+GET_RG_EN_SX	include/ssv6200_reg.h	4484;"	d
+GET_RG_EN_SX5GB_CP	smac/hal/ssv6006c/ssv6006C_reg.h	7270;"	d
+GET_RG_EN_SX5GB_CP_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	7269;"	d
+GET_RG_EN_SX5GB_DITHER	smac/hal/ssv6006c/ssv6006C_reg.h	7371;"	d
+GET_RG_EN_SX5GB_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	7272;"	d
+GET_RG_EN_SX5GB_DIV_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	7271;"	d
+GET_RG_EN_SX5GB_HSDIV	smac/hal/ssv6006c/ssv6006C_reg.h	7280;"	d
+GET_RG_EN_SX5GB_HSDIV_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	7279;"	d
+GET_RG_EN_SX5GB_LDO_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	7297;"	d
+GET_RG_EN_SX5GB_MOD	smac/hal/ssv6006c/ssv6006C_reg.h	7370;"	d
+GET_RG_EN_SX5GB_VCO	smac/hal/ssv6006c/ssv6006C_reg.h	7274;"	d
+GET_RG_EN_SX5GB_VCOMON	smac/hal/ssv6006c/ssv6006C_reg.h	7364;"	d
+GET_RG_EN_SX5GB_VCO_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	7273;"	d
+GET_RG_EN_SXMIX_INBF	smac/hal/ssv6006c/ssv6006C_reg.h	7303;"	d
+GET_RG_EN_SXMIX_INBF_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	7302;"	d
+GET_RG_EN_SX_CH	include/ssv6200_reg.h	4646;"	d
+GET_RG_EN_SX_CHP	include/ssv6200_reg.h	4647;"	d
+GET_RG_EN_SX_CHPLDO	include/ssv6200_reg.h	4510;"	d
+GET_RG_EN_SX_CP	smac/hal/ssv6006c/ssv6006C_reg.h	6766;"	d
+GET_RG_EN_SX_CP_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	6765;"	d
+GET_RG_EN_SX_DITHER	include/ssv6200_reg.h	4652;"	d
+GET_RG_EN_SX_DITHER	smac/hal/ssv6006c/ssv6006C_reg.h	6880;"	d
+GET_RG_EN_SX_DIV	include/ssv6200_reg.h	4655;"	d
+GET_RG_EN_SX_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	6768;"	d
+GET_RG_EN_SX_DIVCK	include/ssv6200_reg.h	4648;"	d
+GET_RG_EN_SX_DIV_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	6767;"	d
+GET_RG_EN_SX_LCK_BIN	include/ssv6200_reg.h	4514;"	d
+GET_RG_EN_SX_LDO_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	6790;"	d
+GET_RG_EN_SX_LOBFLDO	include/ssv6200_reg.h	4511;"	d
+GET_RG_EN_SX_LPF	include/ssv6200_reg.h	4656;"	d
+GET_RG_EN_SX_MIX	smac/hal/ssv6006c/ssv6006C_reg.h	7286;"	d
+GET_RG_EN_SX_MIX_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	7285;"	d
+GET_RG_EN_SX_MOD	include/ssv6200_reg.h	4651;"	d
+GET_RG_EN_SX_MOD	smac/hal/ssv6006c/ssv6006C_reg.h	6879;"	d
+GET_RG_EN_SX_R3	include/ssv6200_reg.h	4645;"	d
+GET_RG_EN_SX_REP	smac/hal/ssv6006c/ssv6006C_reg.h	7288;"	d
+GET_RG_EN_SX_REP_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	7287;"	d
+GET_RG_EN_SX_VCO	include/ssv6200_reg.h	4650;"	d
+GET_RG_EN_SX_VCO	smac/hal/ssv6006c/ssv6006C_reg.h	6770;"	d
+GET_RG_EN_SX_VCOBF	include/ssv6200_reg.h	4649;"	d
+GET_RG_EN_SX_VCOMON	smac/hal/ssv6006c/ssv6006C_reg.h	6873;"	d
+GET_RG_EN_SX_VCO_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	6769;"	d
+GET_RG_EN_SX_VT_MON	include/ssv6200_reg.h	4653;"	d
+GET_RG_EN_SX_VT_MON_DG	include/ssv6200_reg.h	4654;"	d
+GET_RG_EN_TESTPAD_IOSW	include/ssv6200_reg.h	4517;"	d
+GET_RG_EN_TRXBF_BYPASS	include/ssv6200_reg.h	4518;"	d
+GET_RG_EN_TX_BT_PA	smac/hal/ssv6006c/ssv6006C_reg.h	6501;"	d
+GET_RG_EN_TX_DAC	smac/hal/ssv6006c/ssv6006C_reg.h	6495;"	d
+GET_RG_EN_TX_DAC_CAL	include/ssv6200_reg.h	4504;"	d
+GET_RG_EN_TX_DAC_CAL	smac/hal/ssv6006c/ssv6006C_reg.h	6508;"	d
+GET_RG_EN_TX_DAC_OUT	include/ssv6200_reg.h	4506;"	d
+GET_RG_EN_TX_DAC_OUT	smac/hal/ssv6006c/ssv6006C_reg.h	6522;"	d
+GET_RG_EN_TX_DAC_VOUT	include/ssv6200_reg.h	4513;"	d
+GET_RG_EN_TX_DAC_VOUT	smac/hal/ssv6006c/ssv6006C_reg.h	6523;"	d
+GET_RG_EN_TX_DIV2	include/ssv6200_reg.h	4495;"	d
+GET_RG_EN_TX_DIV2	smac/hal/ssv6006c/ssv6006C_reg.h	6497;"	d
+GET_RG_EN_TX_DIV2_BUF	include/ssv6200_reg.h	4496;"	d
+GET_RG_EN_TX_DIV2_BUF	smac/hal/ssv6006c/ssv6006C_reg.h	6499;"	d
+GET_RG_EN_TX_DPD	include/ssv6200_reg.h	4501;"	d
+GET_RG_EN_TX_DPD	smac/hal/ssv6006c/ssv6006C_reg.h	6516;"	d
+GET_RG_EN_TX_LOBF	include/ssv6200_reg.h	4497;"	d
+GET_RG_EN_TX_MOD	include/ssv6200_reg.h	4494;"	d
+GET_RG_EN_TX_MOD	smac/hal/ssv6006c/ssv6006C_reg.h	6493;"	d
+GET_RG_EN_TX_PA	smac/hal/ssv6006c/ssv6006C_reg.h	6491;"	d
+GET_RG_EN_TX_SELF_MIXER	include/ssv6200_reg.h	4505;"	d
+GET_RG_EN_TX_SELF_MIXER	smac/hal/ssv6006c/ssv6006C_reg.h	6512;"	d
+GET_RG_EN_TX_TRSW	include/ssv6200_reg.h	4483;"	d
+GET_RG_EN_TX_TRSW	smac/hal/ssv6006c/ssv6006C_reg.h	6473;"	d
+GET_RG_EN_TX_TSSI	include/ssv6200_reg.h	4502;"	d
+GET_RG_EN_TX_TSSI	smac/hal/ssv6006c/ssv6006C_reg.h	6517;"	d
+GET_RG_EN_TX_VTOI_2ND	smac/hal/ssv6006c/ssv6006C_reg.h	6519;"	d
+GET_RG_EN_VCOBF_DIVCK	smac/hal/ssv6006c/ssv6006C_reg.h	6784;"	d
+GET_RG_EN_VCOBF_DIVCK_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	6783;"	d
+GET_RG_EN_VCOBF_RXMB	smac/hal/ssv6006c/ssv6006C_reg.h	6780;"	d
+GET_RG_EN_VCOBF_RXMB_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	6779;"	d
+GET_RG_EN_VCOBF_RXOB	smac/hal/ssv6006c/ssv6006C_reg.h	6782;"	d
+GET_RG_EN_VCOBF_RXOB_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	6781;"	d
+GET_RG_EN_VCOBF_TXMB	smac/hal/ssv6006c/ssv6006C_reg.h	6776;"	d
+GET_RG_EN_VCOBF_TXMB_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	6775;"	d
+GET_RG_EN_VCOBF_TXOB	smac/hal/ssv6006c/ssv6006C_reg.h	6778;"	d
+GET_RG_EN_VCOBF_TXOB_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	6777;"	d
+GET_RG_EN_XOTEST	smac/hal/ssv6006c/ssv6006C_reg.h	8049;"	d
+GET_RG_EQ_BYPASS_FBW_TAP	include/ssv6200_reg.h	4197;"	d
+GET_RG_EQ_BYPASS_FBW_TAP	smac/hal/ssv6006c/ssv6006C_reg.h	8518;"	d
+GET_RG_EQ_KI_T1	include/ssv6200_reg.h	4164;"	d
+GET_RG_EQ_KI_T1	smac/hal/ssv6006c/ssv6006C_reg.h	8476;"	d
+GET_RG_EQ_KI_T2	include/ssv6200_reg.h	4162;"	d
+GET_RG_EQ_KI_T2	smac/hal/ssv6006c/ssv6006C_reg.h	8474;"	d
+GET_RG_EQ_KP_T1	include/ssv6200_reg.h	4165;"	d
+GET_RG_EQ_KP_T1	smac/hal/ssv6006c/ssv6006C_reg.h	8477;"	d
+GET_RG_EQ_KP_T2	include/ssv6200_reg.h	4163;"	d
+GET_RG_EQ_KP_T2	smac/hal/ssv6006c/ssv6006C_reg.h	8475;"	d
+GET_RG_EQ_MAIN_TAP_COEF	include/ssv6200_reg.h	4173;"	d
+GET_RG_EQ_MAIN_TAP_COEF	smac/hal/ssv6006c/ssv6006C_reg.h	8485;"	d
+GET_RG_EQ_MAIN_TAP_MAN	include/ssv6200_reg.h	4172;"	d
+GET_RG_EQ_MAIN_TAP_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	8484;"	d
+GET_RG_EQ_MU_FB_T1	include/ssv6200_reg.h	4156;"	d
+GET_RG_EQ_MU_FB_T1	smac/hal/ssv6006c/ssv6006C_reg.h	8468;"	d
+GET_RG_EQ_MU_FB_T2	include/ssv6200_reg.h	4154;"	d
+GET_RG_EQ_MU_FB_T2	smac/hal/ssv6006c/ssv6006C_reg.h	8466;"	d
+GET_RG_EQ_MU_FB_T3	include/ssv6200_reg.h	4160;"	d
+GET_RG_EQ_MU_FB_T3	smac/hal/ssv6006c/ssv6006C_reg.h	8472;"	d
+GET_RG_EQ_MU_FB_T4	include/ssv6200_reg.h	4158;"	d
+GET_RG_EQ_MU_FB_T4	smac/hal/ssv6006c/ssv6006C_reg.h	8470;"	d
+GET_RG_EQ_MU_FF_T1	include/ssv6200_reg.h	4157;"	d
+GET_RG_EQ_MU_FF_T1	smac/hal/ssv6006c/ssv6006C_reg.h	8469;"	d
+GET_RG_EQ_MU_FF_T2	include/ssv6200_reg.h	4155;"	d
+GET_RG_EQ_MU_FF_T2	smac/hal/ssv6006c/ssv6006C_reg.h	8467;"	d
+GET_RG_EQ_MU_FF_T3	include/ssv6200_reg.h	4161;"	d
+GET_RG_EQ_MU_FF_T3	smac/hal/ssv6006c/ssv6006C_reg.h	8473;"	d
+GET_RG_EQ_MU_FF_T4	include/ssv6200_reg.h	4159;"	d
+GET_RG_EQ_MU_FF_T4	smac/hal/ssv6006c/ssv6006C_reg.h	8471;"	d
+GET_RG_EQ_SHORT_GI_SHIFT	include/ssv6200_reg.h	4268;"	d
+GET_RG_ERASE_SC_NUM0	smac/hal/ssv6006c/ssv6006C_reg.h	8588;"	d
+GET_RG_ERASE_SC_NUM1	smac/hal/ssv6006c/ssv6006C_reg.h	8586;"	d
+GET_RG_ERASE_SC_NUM2	smac/hal/ssv6006c/ssv6006C_reg.h	8584;"	d
+GET_RG_ERASE_SC_NUM3	smac/hal/ssv6006c/ssv6006C_reg.h	8582;"	d
+GET_RG_ERASE_SC_NUM4	smac/hal/ssv6006c/ssv6006C_reg.h	8596;"	d
+GET_RG_ERASE_SC_NUM5	smac/hal/ssv6006c/ssv6006C_reg.h	8594;"	d
+GET_RG_ERASE_SC_NUM6	smac/hal/ssv6006c/ssv6006C_reg.h	8592;"	d
+GET_RG_ERASE_SC_NUM7	smac/hal/ssv6006c/ssv6006C_reg.h	8590;"	d
+GET_RG_FDB_BYPASS	smac/hal/ssv6006c/ssv6006C_reg.h	8047;"	d
+GET_RG_FDB_CDELAY_MUAL	smac/hal/ssv6006c/ssv6006C_reg.h	8057;"	d
+GET_RG_FDB_DUTY_LTH	smac/hal/ssv6006c/ssv6006C_reg.h	8048;"	d
+GET_RG_FDB_FDELAY_MUAL	smac/hal/ssv6006c/ssv6006C_reg.h	8058;"	d
+GET_RG_FDB_PHASESWAP_MUAL	smac/hal/ssv6006c/ssv6006C_reg.h	8055;"	d
+GET_RG_FDB_RDELAYF	smac/hal/ssv6006c/ssv6006C_reg.h	8061;"	d
+GET_RG_FDB_RDELAYS	smac/hal/ssv6006c/ssv6006C_reg.h	8062;"	d
+GET_RG_FDB_RECAL_TIMMER	smac/hal/ssv6006c/ssv6006C_reg.h	8063;"	d
+GET_RG_FEC	include/ssv6200_reg.h	3902;"	d
+GET_RG_FEC	smac/hal/ssv6006c/ssv6006C_reg.h	8221;"	d
+GET_RG_FFT_EN	include/ssv6200_reg.h	4400;"	d
+GET_RG_FFT_ENRG_FREQ	include/ssv6200_reg.h	4403;"	d
+GET_RG_FFT_IFFT_MODE	include/ssv6200_reg.h	3911;"	d
+GET_RG_FFT_MEM_CLK_EN_RX	include/ssv6200_reg.h	3884;"	d
+GET_RG_FFT_MEM_CLK_EN_TX	include/ssv6200_reg.h	3885;"	d
+GET_RG_FFT_MOD	include/ssv6200_reg.h	4401;"	d
+GET_RG_FFT_SCALE	include/ssv6200_reg.h	4402;"	d
+GET_RG_FFT_SCALE_104	smac/hal/ssv6006c/ssv6006C_reg.h	8532;"	d
+GET_RG_FFT_SCALE_114	smac/hal/ssv6006c/ssv6006C_reg.h	8533;"	d
+GET_RG_FFT_SCALE_52	smac/hal/ssv6006c/ssv6006C_reg.h	8534;"	d
+GET_RG_FFT_SCALE_56	smac/hal/ssv6006c/ssv6006C_reg.h	8535;"	d
+GET_RG_FFT_WDW_SHORT_SHIFT	include/ssv6200_reg.h	4269;"	d
+GET_RG_FILTER_AVERAGE_EN	smac/hal/ssv6006c/ssv6006C_reg.h	7673;"	d
+GET_RG_FMT_DET_GF_TH	include/ssv6200_reg.h	4275;"	d
+GET_RG_FMT_DET_GF_TH	smac/hal/ssv6006c/ssv6006C_reg.h	8651;"	d
+GET_RG_FMT_DET_LENGTH_TH	include/ssv6200_reg.h	4277;"	d
+GET_RG_FMT_DET_MM_TH	include/ssv6200_reg.h	4274;"	d
+GET_RG_FMT_DET_MM_TH	smac/hal/ssv6006c/ssv6006C_reg.h	8650;"	d
+GET_RG_FORCE_11B_EN	include/ssv6200_reg.h	3883;"	d
+GET_RG_FORCE_11B_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8205;"	d
+GET_RG_FORCE_11GN_EN	include/ssv6200_reg.h	3882;"	d
+GET_RG_FORCE_11GN_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8204;"	d
+GET_RG_FPGA_80M_PH_STP	include/ssv6200_reg.h	4405;"	d
+GET_RG_FPGA_80M_PH_UP	include/ssv6200_reg.h	4404;"	d
+GET_RG_FPGA_CLK_REF_40M_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8110;"	d
+GET_RG_GEMINIA_40M_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	4836;"	d
+GET_RG_GEMINIA_ADC_EDGE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	4844;"	d
+GET_RG_GEMINIA_ALPHA_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	4880;"	d
+GET_RG_GEMINIA_BT_CLK32K_CAL_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	4944;"	d
+GET_RG_GEMINIA_BT_CLK_SW	smac/hal/ssv6006c/ssv6006C_reg.h	4943;"	d
+GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	4760;"	d
+GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	4758;"	d
+GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	4740;"	d
+GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	4738;"	d
+GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	4736;"	d
+GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	4734;"	d
+GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	4732;"	d
+GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	4730;"	d
+GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	4756;"	d
+GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	4754;"	d
+GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	4752;"	d
+GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	4750;"	d
+GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	4748;"	d
+GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	4746;"	d
+GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	4744;"	d
+GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	4742;"	d
+GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	4792;"	d
+GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	4790;"	d
+GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	4772;"	d
+GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	4770;"	d
+GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	4768;"	d
+GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	4766;"	d
+GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	4764;"	d
+GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	4762;"	d
+GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	4788;"	d
+GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	4786;"	d
+GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	4784;"	d
+GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	4782;"	d
+GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	4780;"	d
+GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	4778;"	d
+GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	4776;"	d
+GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	4774;"	d
+GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	4761;"	d
+GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	4759;"	d
+GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	4741;"	d
+GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	4739;"	d
+GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	4737;"	d
+GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	4735;"	d
+GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	4733;"	d
+GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	4731;"	d
+GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	4757;"	d
+GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	4755;"	d
+GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	4753;"	d
+GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	4751;"	d
+GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	4749;"	d
+GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	4747;"	d
+GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	4745;"	d
+GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	4743;"	d
+GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	4793;"	d
+GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	4791;"	d
+GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	4773;"	d
+GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	4771;"	d
+GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	4769;"	d
+GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	4767;"	d
+GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	4765;"	d
+GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	4763;"	d
+GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	4789;"	d
+GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	4787;"	d
+GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	4785;"	d
+GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	4783;"	d
+GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	4781;"	d
+GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	4779;"	d
+GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	4777;"	d
+GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	4775;"	d
+GET_RG_GEMINIA_BT_PABIAS_2X	smac/hal/ssv6006c/ssv6006C_reg.h	4324;"	d
+GET_RG_GEMINIA_BT_PABIAS_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	4325;"	d
+GET_RG_GEMINIA_BT_PA_CAPSEL	smac/hal/ssv6006c/ssv6006C_reg.h	4323;"	d
+GET_RG_GEMINIA_BT_RX_ABBCFIX	smac/hal/ssv6006c/ssv6006C_reg.h	4289;"	d
+GET_RG_GEMINIA_BT_RX_ABBCTUNEI	smac/hal/ssv6006c/ssv6006C_reg.h	4283;"	d
+GET_RG_GEMINIA_BT_RX_ABBCTUNEQ	smac/hal/ssv6006c/ssv6006C_reg.h	4284;"	d
+GET_RG_GEMINIA_BT_RX_ABB_BT_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	4291;"	d
+GET_RG_GEMINIA_BT_RX_ABB_IDIV3	smac/hal/ssv6006c/ssv6006C_reg.h	4292;"	d
+GET_RG_GEMINIA_BT_RX_ABB_N_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	4290;"	d
+GET_RG_GEMINIA_BT_RX_ADC_CLOAD	smac/hal/ssv6006c/ssv6006C_reg.h	4435;"	d
+GET_RG_GEMINIA_BT_RX_ADC_ICMP	smac/hal/ssv6006c/ssv6006C_reg.h	4433;"	d
+GET_RG_GEMINIA_BT_RX_ADC_VCMI	smac/hal/ssv6006c/ssv6006C_reg.h	4434;"	d
+GET_RG_GEMINIA_BT_RX_DCCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	4809;"	d
+GET_RG_GEMINIA_BT_RX_EN_IDACA_COARSE	smac/hal/ssv6006c/ssv6006C_reg.h	4293;"	d
+GET_RG_GEMINIA_BT_RX_EN_LOOPA	smac/hal/ssv6006c/ssv6006C_reg.h	4294;"	d
+GET_RG_GEMINIA_BT_RX_FILTERI1ST	smac/hal/ssv6006c/ssv6006C_reg.h	4286;"	d
+GET_RG_GEMINIA_BT_RX_FILTERI2ND	smac/hal/ssv6006c/ssv6006C_reg.h	4287;"	d
+GET_RG_GEMINIA_BT_RX_FILTERI3RD	smac/hal/ssv6006c/ssv6006C_reg.h	4288;"	d
+GET_RG_GEMINIA_BT_RX_FILTERI_COARSE	smac/hal/ssv6006c/ssv6006C_reg.h	4285;"	d
+GET_RG_GEMINIA_BT_RX_FILTERVCM	smac/hal/ssv6006c/ssv6006C_reg.h	4295;"	d
+GET_RG_GEMINIA_BT_RX_HG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	4388;"	d
+GET_RG_GEMINIA_BT_RX_HG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	4383;"	d
+GET_RG_GEMINIA_BT_RX_HG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	4384;"	d
+GET_RG_GEMINIA_BT_RX_HG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	4385;"	d
+GET_RG_GEMINIA_BT_RX_HG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	4381;"	d
+GET_RG_GEMINIA_BT_RX_HG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	4389;"	d
+GET_RG_GEMINIA_BT_RX_HG_SQDC	smac/hal/ssv6006c/ssv6006C_reg.h	4387;"	d
+GET_RG_GEMINIA_BT_RX_HG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	4390;"	d
+GET_RG_GEMINIA_BT_RX_HG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	4386;"	d
+GET_RG_GEMINIA_BT_RX_HG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	4382;"	d
+GET_RG_GEMINIA_BT_RX_HG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	4391;"	d
+GET_RG_GEMINIA_BT_RX_LG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	4410;"	d
+GET_RG_GEMINIA_BT_RX_LG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	4405;"	d
+GET_RG_GEMINIA_BT_RX_LG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	4406;"	d
+GET_RG_GEMINIA_BT_RX_LG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	4407;"	d
+GET_RG_GEMINIA_BT_RX_LG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	4403;"	d
+GET_RG_GEMINIA_BT_RX_LG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	4411;"	d
+GET_RG_GEMINIA_BT_RX_LG_SQDC	smac/hal/ssv6006c/ssv6006C_reg.h	4409;"	d
+GET_RG_GEMINIA_BT_RX_LG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	4412;"	d
+GET_RG_GEMINIA_BT_RX_LG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	4408;"	d
+GET_RG_GEMINIA_BT_RX_LG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	4404;"	d
+GET_RG_GEMINIA_BT_RX_LG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	4413;"	d
+GET_RG_GEMINIA_BT_RX_MG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	4399;"	d
+GET_RG_GEMINIA_BT_RX_MG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	4394;"	d
+GET_RG_GEMINIA_BT_RX_MG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	4395;"	d
+GET_RG_GEMINIA_BT_RX_MG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	4396;"	d
+GET_RG_GEMINIA_BT_RX_MG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	4392;"	d
+GET_RG_GEMINIA_BT_RX_MG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	4400;"	d
+GET_RG_GEMINIA_BT_RX_MG_SQDC	smac/hal/ssv6006c/ssv6006C_reg.h	4398;"	d
+GET_RG_GEMINIA_BT_RX_MG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	4401;"	d
+GET_RG_GEMINIA_BT_RX_MG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	4397;"	d
+GET_RG_GEMINIA_BT_RX_MG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	4393;"	d
+GET_RG_GEMINIA_BT_RX_MG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	4402;"	d
+GET_RG_GEMINIA_BT_RX_OUTVCM	smac/hal/ssv6006c/ssv6006C_reg.h	4296;"	d
+GET_RG_GEMINIA_BT_RX_ULG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	4421;"	d
+GET_RG_GEMINIA_BT_RX_ULG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	4416;"	d
+GET_RG_GEMINIA_BT_RX_ULG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	4417;"	d
+GET_RG_GEMINIA_BT_RX_ULG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	4418;"	d
+GET_RG_GEMINIA_BT_RX_ULG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	4414;"	d
+GET_RG_GEMINIA_BT_RX_ULG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	4422;"	d
+GET_RG_GEMINIA_BT_RX_ULG_SQDC	smac/hal/ssv6006c/ssv6006C_reg.h	4420;"	d
+GET_RG_GEMINIA_BT_RX_ULG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	4423;"	d
+GET_RG_GEMINIA_BT_RX_ULG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	4419;"	d
+GET_RG_GEMINIA_BT_RX_ULG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	4415;"	d
+GET_RG_GEMINIA_BT_RX_ULG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	4424;"	d
+GET_RG_GEMINIA_BT_TXLPF_BOOSTI	smac/hal/ssv6006c/ssv6006C_reg.h	4460;"	d
+GET_RG_GEMINIA_BT_TXPGA_CAPSW	smac/hal/ssv6006c/ssv6006C_reg.h	4314;"	d
+GET_RG_GEMINIA_BT_TX_DACI1ST	smac/hal/ssv6006c/ssv6006C_reg.h	4454;"	d
+GET_RG_GEMINIA_BT_TX_DACLPF_ICOARSE	smac/hal/ssv6006c/ssv6006C_reg.h	4455;"	d
+GET_RG_GEMINIA_BT_TX_DACLPF_IFINE	smac/hal/ssv6006c/ssv6006C_reg.h	4456;"	d
+GET_RG_GEMINIA_BT_TX_DACLPF_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	4457;"	d
+GET_RG_GEMINIA_BT_TX_DAC_CKEDGE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	4462;"	d
+GET_RG_GEMINIA_BT_TX_DAC_IATTN	smac/hal/ssv6006c/ssv6006C_reg.h	4459;"	d
+GET_RG_GEMINIA_BT_TX_DAC_IBIAS	smac/hal/ssv6006c/ssv6006C_reg.h	4458;"	d
+GET_RG_GEMINIA_BT_TX_DAC_IOFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	4464;"	d
+GET_RG_GEMINIA_BT_TX_DAC_OS	smac/hal/ssv6006c/ssv6006C_reg.h	4463;"	d
+GET_RG_GEMINIA_BT_TX_DAC_QOFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	4465;"	d
+GET_RG_GEMINIA_BT_TX_DAC_RCAL	smac/hal/ssv6006c/ssv6006C_reg.h	4461;"	d
+GET_RG_GEMINIA_BT_TX_DIV_VSET	smac/hal/ssv6006c/ssv6006C_reg.h	4315;"	d
+GET_RG_GEMINIA_BT_TX_GAIN_OFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	4332;"	d
+GET_RG_GEMINIA_BT_TX_LOBUF_VSET	smac/hal/ssv6006c/ssv6006C_reg.h	4316;"	d
+GET_RG_GEMINIA_BT_TX_PA_VCAS	smac/hal/ssv6006c/ssv6006C_reg.h	4326;"	d
+GET_RG_GEMINIA_BT_TX_VDDSW	smac/hal/ssv6006c/ssv6006C_reg.h	4317;"	d
+GET_RG_GEMINIA_BUCK_EN_PSM	smac/hal/ssv6006c/ssv6006C_reg.h	4923;"	d
+GET_RG_GEMINIA_BUCK_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	4920;"	d
+GET_RG_GEMINIA_BUCK_PSM_VTH	smac/hal/ssv6006c/ssv6006C_reg.h	4924;"	d
+GET_RG_GEMINIA_BUCK_VREF_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	4925;"	d
+GET_RG_GEMINIA_BW20_HB_COEF_00	smac/hal/ssv6006c/ssv6006C_reg.h	4867;"	d
+GET_RG_GEMINIA_BW20_HB_COEF_01	smac/hal/ssv6006c/ssv6006C_reg.h	4866;"	d
+GET_RG_GEMINIA_BW20_HB_COEF_02	smac/hal/ssv6006c/ssv6006C_reg.h	4869;"	d
+GET_RG_GEMINIA_BW20_HB_COEF_03	smac/hal/ssv6006c/ssv6006C_reg.h	4868;"	d
+GET_RG_GEMINIA_BW20_HB_COEF_04	smac/hal/ssv6006c/ssv6006C_reg.h	4871;"	d
+GET_RG_GEMINIA_BW20_HB_COEF_05	smac/hal/ssv6006c/ssv6006C_reg.h	4870;"	d
+GET_RG_GEMINIA_BW20_HB_COEF_06	smac/hal/ssv6006c/ssv6006C_reg.h	4873;"	d
+GET_RG_GEMINIA_BW20_HB_COEF_07	smac/hal/ssv6006c/ssv6006C_reg.h	4872;"	d
+GET_RG_GEMINIA_BW20_HB_COEF_08	smac/hal/ssv6006c/ssv6006C_reg.h	4875;"	d
+GET_RG_GEMINIA_BW20_HB_COEF_09	smac/hal/ssv6006c/ssv6006C_reg.h	4874;"	d
+GET_RG_GEMINIA_BW20_HB_COEF_10	smac/hal/ssv6006c/ssv6006C_reg.h	4877;"	d
+GET_RG_GEMINIA_BW20_HB_COEF_11	smac/hal/ssv6006c/ssv6006C_reg.h	4876;"	d
+GET_RG_GEMINIA_CAL_INDEX	smac/hal/ssv6006c/ssv6006C_reg.h	4195;"	d
+GET_RG_GEMINIA_CBW_20_40	smac/hal/ssv6006c/ssv6006C_reg.h	4859;"	d
+GET_RG_GEMINIA_CLK_RTC_SW	smac/hal/ssv6006c/ssv6006C_reg.h	4948;"	d
+GET_RG_GEMINIA_CLK_SAR_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	4440;"	d
+GET_RG_GEMINIA_DAC_DC_I	smac/hal/ssv6006c/ssv6006C_reg.h	4861;"	d
+GET_RG_GEMINIA_DAC_DC_Q	smac/hal/ssv6006c/ssv6006C_reg.h	4860;"	d
+GET_RG_GEMINIA_DAC_I_SET	smac/hal/ssv6006c/ssv6006C_reg.h	4864;"	d
+GET_RG_GEMINIA_DAC_MAN_I_EN	smac/hal/ssv6006c/ssv6006C_reg.h	4865;"	d
+GET_RG_GEMINIA_DAC_MAN_Q_EN	smac/hal/ssv6006c/ssv6006C_reg.h	4863;"	d
+GET_RG_GEMINIA_DAC_Q_SET	smac/hal/ssv6006c/ssv6006C_reg.h	4862;"	d
+GET_RG_GEMINIA_DCDC_CLK	smac/hal/ssv6006c/ssv6006C_reg.h	4933;"	d
+GET_RG_GEMINIA_DCDC_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	4919;"	d
+GET_RG_GEMINIA_DCDC_PULLLOW_CON	smac/hal/ssv6006c/ssv6006C_reg.h	4928;"	d
+GET_RG_GEMINIA_DCDC_RES2_CON	smac/hal/ssv6006c/ssv6006C_reg.h	4929;"	d
+GET_RG_GEMINIA_DCDC_RES_CON	smac/hal/ssv6006c/ssv6006C_reg.h	4930;"	d
+GET_RG_GEMINIA_DIS_DAC_OFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	4856;"	d
+GET_RG_GEMINIA_DLDO_BOOST_IQ	smac/hal/ssv6006c/ssv6006C_reg.h	4922;"	d
+GET_RG_GEMINIA_DLDO_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	4921;"	d
+GET_RG_GEMINIA_DPLL_CLK320BY2	smac/hal/ssv6006c/ssv6006C_reg.h	4858;"	d
+GET_RG_GEMINIA_DPL_MOD_ORDER	smac/hal/ssv6006c/ssv6006C_reg.h	4624;"	d
+GET_RG_GEMINIA_DPL_RFCTRL_CH	smac/hal/ssv6006c/ssv6006C_reg.h	4645;"	d
+GET_RG_GEMINIA_DPL_RFCTRL_F	smac/hal/ssv6006c/ssv6006C_reg.h	4644;"	d
+GET_RG_GEMINIA_DPL_SETTLING_TIMMER	smac/hal/ssv6006c/ssv6006C_reg.h	4913;"	d
+GET_RG_GEMINIA_DP_ADC320_DIVBY2_BT	smac/hal/ssv6006c/ssv6006C_reg.h	4621;"	d
+GET_RG_GEMINIA_DP_ADC320_DIVBY2_WF	smac/hal/ssv6006c/ssv6006C_reg.h	4622;"	d
+GET_RG_GEMINIA_DP_BBPLL_BP	smac/hal/ssv6006c/ssv6006C_reg.h	4617;"	d
+GET_RG_GEMINIA_DP_BBPLL_BS	smac/hal/ssv6006c/ssv6006C_reg.h	4642;"	d
+GET_RG_GEMINIA_DP_BBPLL_ICP	smac/hal/ssv6006c/ssv6006C_reg.h	4631;"	d
+GET_RG_GEMINIA_DP_BBPLL_IDUAL	smac/hal/ssv6006c/ssv6006C_reg.h	4632;"	d
+GET_RG_GEMINIA_DP_BBPLL_PD	smac/hal/ssv6006c/ssv6006C_reg.h	4616;"	d
+GET_RG_GEMINIA_DP_BBPLL_PFD_DLY	smac/hal/ssv6006c/ssv6006C_reg.h	4636;"	d
+GET_RG_GEMINIA_DP_BBPLL_SDM_EDGE	smac/hal/ssv6006c/ssv6006C_reg.h	4643;"	d
+GET_RG_GEMINIA_DP_BBPLL_TESTSEL	smac/hal/ssv6006c/ssv6006C_reg.h	4630;"	d
+GET_RG_GEMINIA_DP_CP_IOST	smac/hal/ssv6006c/ssv6006C_reg.h	4634;"	d
+GET_RG_GEMINIA_DP_CP_IOSTPOL	smac/hal/ssv6006c/ssv6006C_reg.h	4633;"	d
+GET_RG_GEMINIA_DP_DAC320_DIVBY2	smac/hal/ssv6006c/ssv6006C_reg.h	4620;"	d
+GET_RG_GEMINIA_DP_FODIV	smac/hal/ssv6006c/ssv6006C_reg.h	4626;"	d
+GET_RG_GEMINIA_DP_FREF_DOUB	smac/hal/ssv6006c/ssv6006C_reg.h	4619;"	d
+GET_RG_GEMINIA_DP_LDO_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	4266;"	d
+GET_RG_GEMINIA_DP_OD_TEST	smac/hal/ssv6006c/ssv6006C_reg.h	4629;"	d
+GET_RG_GEMINIA_DP_PFD_PFDSEL	smac/hal/ssv6006c/ssv6006C_reg.h	4635;"	d
+GET_RG_GEMINIA_DP_REFDIV	smac/hal/ssv6006c/ssv6006C_reg.h	4625;"	d
+GET_RG_GEMINIA_DP_RHP	smac/hal/ssv6006c/ssv6006C_reg.h	4638;"	d
+GET_RG_GEMINIA_DP_RP	smac/hal/ssv6006c/ssv6006C_reg.h	4637;"	d
+GET_RG_GEMINIA_DP_VT_TH_HI	smac/hal/ssv6006c/ssv6006C_reg.h	4640;"	d
+GET_RG_GEMINIA_DP_VT_TH_LO	smac/hal/ssv6006c/ssv6006C_reg.h	4641;"	d
+GET_RG_GEMINIA_EN_DPL_MOD	smac/hal/ssv6006c/ssv6006C_reg.h	4623;"	d
+GET_RG_GEMINIA_EN_DP_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	4618;"	d
+GET_RG_GEMINIA_EN_DP_VT_MON	smac/hal/ssv6006c/ssv6006C_reg.h	4639;"	d
+GET_RG_GEMINIA_EN_FDB	smac/hal/ssv6006c/ssv6006C_reg.h	4901;"	d
+GET_RG_GEMINIA_EN_FDB_DCC_MUAL	smac/hal/ssv6006c/ssv6006C_reg.h	4905;"	d
+GET_RG_GEMINIA_EN_FDB_DELAYC_MUAL	smac/hal/ssv6006c/ssv6006C_reg.h	4906;"	d
+GET_RG_GEMINIA_EN_FDB_DELAYF_MUAL	smac/hal/ssv6006c/ssv6006C_reg.h	4907;"	d
+GET_RG_GEMINIA_EN_FDB_PHASESWAP_MUAL	smac/hal/ssv6006c/ssv6006C_reg.h	4908;"	d
+GET_RG_GEMINIA_EN_FDB_RECAL	smac/hal/ssv6006c/ssv6006C_reg.h	4917;"	d
+GET_RG_GEMINIA_EN_IREF_RX	smac/hal/ssv6006c/ssv6006C_reg.h	4233;"	d
+GET_RG_GEMINIA_EN_LDO_ABB	smac/hal/ssv6006c/ssv6006C_reg.h	4230;"	d
+GET_RG_GEMINIA_EN_LDO_ADC	smac/hal/ssv6006c/ssv6006C_reg.h	4231;"	d
+GET_RG_GEMINIA_EN_LDO_CP	smac/hal/ssv6006c/ssv6006C_reg.h	4494;"	d
+GET_RG_GEMINIA_EN_LDO_CP_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	4498;"	d
+GET_RG_GEMINIA_EN_LDO_CP_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	4503;"	d
+GET_RG_GEMINIA_EN_LDO_DAC	smac/hal/ssv6006c/ssv6006C_reg.h	4232;"	d
+GET_RG_GEMINIA_EN_LDO_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	4495;"	d
+GET_RG_GEMINIA_EN_LDO_DIV_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	4499;"	d
+GET_RG_GEMINIA_EN_LDO_DIV_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	4504;"	d
+GET_RG_GEMINIA_EN_LDO_DP_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	4627;"	d
+GET_RG_GEMINIA_EN_LDO_DP_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	4628;"	d
+GET_RG_GEMINIA_EN_LDO_EFUSE	smac/hal/ssv6006c/ssv6006C_reg.h	4927;"	d
+GET_RG_GEMINIA_EN_LDO_LO	smac/hal/ssv6006c/ssv6006C_reg.h	4496;"	d
+GET_RG_GEMINIA_EN_LDO_LO_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	4500;"	d
+GET_RG_GEMINIA_EN_LDO_LO_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	4505;"	d
+GET_RG_GEMINIA_EN_LDO_RX_ADC_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	4259;"	d
+GET_RG_GEMINIA_EN_LDO_RX_FE	smac/hal/ssv6006c/ssv6006C_reg.h	4229;"	d
+GET_RG_GEMINIA_EN_LDO_VCO	smac/hal/ssv6006c/ssv6006C_reg.h	4497;"	d
+GET_RG_GEMINIA_EN_LDO_VCO_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	4506;"	d
+GET_RG_GEMINIA_EN_LDO_VCO_PSW	smac/hal/ssv6006c/ssv6006C_reg.h	4501;"	d
+GET_RG_GEMINIA_EN_LDO_VCO_VDD33	smac/hal/ssv6006c/ssv6006C_reg.h	4502;"	d
+GET_RG_GEMINIA_EN_LDO_XO_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	4896;"	d
+GET_RG_GEMINIA_EN_LDO_XO_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	4897;"	d
+GET_RG_GEMINIA_EN_RTC_CAL	smac/hal/ssv6006c/ssv6006C_reg.h	4940;"	d
+GET_RG_GEMINIA_EN_RX_ADC	smac/hal/ssv6006c/ssv6006C_reg.h	4214;"	d
+GET_RG_GEMINIA_EN_RX_DIV2	smac/hal/ssv6006c/ssv6006C_reg.h	4206;"	d
+GET_RG_GEMINIA_EN_RX_FILTER	smac/hal/ssv6006c/ssv6006C_reg.h	4212;"	d
+GET_RG_GEMINIA_EN_RX_IQCAL	smac/hal/ssv6006c/ssv6006C_reg.h	4241;"	d
+GET_RG_GEMINIA_EN_RX_LNA	smac/hal/ssv6006c/ssv6006C_reg.h	4202;"	d
+GET_RG_GEMINIA_EN_RX_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	4208;"	d
+GET_RG_GEMINIA_EN_RX_MIXER	smac/hal/ssv6006c/ssv6006C_reg.h	4204;"	d
+GET_RG_GEMINIA_EN_RX_PADSW	smac/hal/ssv6006c/ssv6006C_reg.h	4254;"	d
+GET_RG_GEMINIA_EN_RX_RSSI	smac/hal/ssv6006c/ssv6006C_reg.h	4216;"	d
+GET_RG_GEMINIA_EN_RX_RSSI_TESTNODE	smac/hal/ssv6006c/ssv6006C_reg.h	4307;"	d
+GET_RG_GEMINIA_EN_RX_TESTNODE	smac/hal/ssv6006c/ssv6006C_reg.h	4253;"	d
+GET_RG_GEMINIA_EN_RX_TZ	smac/hal/ssv6006c/ssv6006C_reg.h	4210;"	d
+GET_RG_GEMINIA_EN_SARADC	smac/hal/ssv6006c/ssv6006C_reg.h	4246;"	d
+GET_RG_GEMINIA_EN_SAR_TEST	smac/hal/ssv6006c/ssv6006C_reg.h	4437;"	d
+GET_RG_GEMINIA_EN_SX_CP	smac/hal/ssv6006c/ssv6006C_reg.h	4469;"	d
+GET_RG_GEMINIA_EN_SX_CP_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	4468;"	d
+GET_RG_GEMINIA_EN_SX_DITHER	smac/hal/ssv6006c/ssv6006C_reg.h	4583;"	d
+GET_RG_GEMINIA_EN_SX_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	4471;"	d
+GET_RG_GEMINIA_EN_SX_DIV_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	4470;"	d
+GET_RG_GEMINIA_EN_SX_LDO_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	4493;"	d
+GET_RG_GEMINIA_EN_SX_MOD	smac/hal/ssv6006c/ssv6006C_reg.h	4582;"	d
+GET_RG_GEMINIA_EN_SX_VCO	smac/hal/ssv6006c/ssv6006C_reg.h	4473;"	d
+GET_RG_GEMINIA_EN_SX_VCOMON	smac/hal/ssv6006c/ssv6006C_reg.h	4576;"	d
+GET_RG_GEMINIA_EN_SX_VCO_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	4472;"	d
+GET_RG_GEMINIA_EN_TX_BT_PA	smac/hal/ssv6006c/ssv6006C_reg.h	4228;"	d
+GET_RG_GEMINIA_EN_TX_DAC	smac/hal/ssv6006c/ssv6006C_reg.h	4222;"	d
+GET_RG_GEMINIA_EN_TX_DAC_CAL	smac/hal/ssv6006c/ssv6006C_reg.h	4235;"	d
+GET_RG_GEMINIA_EN_TX_DAC_OUT	smac/hal/ssv6006c/ssv6006C_reg.h	4250;"	d
+GET_RG_GEMINIA_EN_TX_DAC_VOUT	smac/hal/ssv6006c/ssv6006C_reg.h	4251;"	d
+GET_RG_GEMINIA_EN_TX_DIV2	smac/hal/ssv6006c/ssv6006C_reg.h	4224;"	d
+GET_RG_GEMINIA_EN_TX_DIV2_BUF	smac/hal/ssv6006c/ssv6006C_reg.h	4226;"	d
+GET_RG_GEMINIA_EN_TX_DPD	smac/hal/ssv6006c/ssv6006C_reg.h	4243;"	d
+GET_RG_GEMINIA_EN_TX_MOD	smac/hal/ssv6006c/ssv6006C_reg.h	4220;"	d
+GET_RG_GEMINIA_EN_TX_PA	smac/hal/ssv6006c/ssv6006C_reg.h	4218;"	d
+GET_RG_GEMINIA_EN_TX_SELF_MIXER	smac/hal/ssv6006c/ssv6006C_reg.h	4239;"	d
+GET_RG_GEMINIA_EN_TX_TRSW	smac/hal/ssv6006c/ssv6006C_reg.h	4200;"	d
+GET_RG_GEMINIA_EN_TX_TSSI	smac/hal/ssv6006c/ssv6006C_reg.h	4245;"	d
+GET_RG_GEMINIA_EN_TX_VTOI_2ND	smac/hal/ssv6006c/ssv6006C_reg.h	4247;"	d
+GET_RG_GEMINIA_EN_VCOBF_DIVCK	smac/hal/ssv6006c/ssv6006C_reg.h	4487;"	d
+GET_RG_GEMINIA_EN_VCOBF_DIVCK_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	4486;"	d
+GET_RG_GEMINIA_EN_VCOBF_RXMB	smac/hal/ssv6006c/ssv6006C_reg.h	4483;"	d
+GET_RG_GEMINIA_EN_VCOBF_RXMB_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	4482;"	d
+GET_RG_GEMINIA_EN_VCOBF_RXOB	smac/hal/ssv6006c/ssv6006C_reg.h	4485;"	d
+GET_RG_GEMINIA_EN_VCOBF_RXOB_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	4484;"	d
+GET_RG_GEMINIA_EN_VCOBF_TXMB	smac/hal/ssv6006c/ssv6006C_reg.h	4479;"	d
+GET_RG_GEMINIA_EN_VCOBF_TXMB_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	4478;"	d
+GET_RG_GEMINIA_EN_VCOBF_TXOB	smac/hal/ssv6006c/ssv6006C_reg.h	4481;"	d
+GET_RG_GEMINIA_EN_VCOBF_TXOB_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	4480;"	d
+GET_RG_GEMINIA_EN_XOTEST	smac/hal/ssv6006c/ssv6006C_reg.h	4904;"	d
+GET_RG_GEMINIA_EXT_DAC_EN	smac/hal/ssv6006c/ssv6006C_reg.h	4857;"	d
+GET_RG_GEMINIA_EXT_MCU_PWRUP	smac/hal/ssv6006c/ssv6006C_reg.h	5031;"	d
+GET_RG_GEMINIA_FDB_BYPASS	smac/hal/ssv6006c/ssv6006C_reg.h	4902;"	d
+GET_RG_GEMINIA_FDB_CDELAY_MUAL	smac/hal/ssv6006c/ssv6006C_reg.h	4910;"	d
+GET_RG_GEMINIA_FDB_DUTY_LTH	smac/hal/ssv6006c/ssv6006C_reg.h	4903;"	d
+GET_RG_GEMINIA_FDB_FDELAY_MUAL	smac/hal/ssv6006c/ssv6006C_reg.h	4911;"	d
+GET_RG_GEMINIA_FDB_PHASESWAP_MUAL	smac/hal/ssv6006c/ssv6006C_reg.h	4909;"	d
+GET_RG_GEMINIA_FDB_RDELAYF	smac/hal/ssv6006c/ssv6006C_reg.h	4914;"	d
+GET_RG_GEMINIA_FDB_RDELAYS	smac/hal/ssv6006c/ssv6006C_reg.h	4915;"	d
+GET_RG_GEMINIA_FDB_RECAL_TIMMER	smac/hal/ssv6006c/ssv6006C_reg.h	4916;"	d
+GET_RG_GEMINIA_FPGA_CLK_REF_40M_DS	smac/hal/ssv6006c/ssv6006C_reg.h	4976;"	d
+GET_RG_GEMINIA_FPGA_CLK_REF_40M_OE	smac/hal/ssv6006c/ssv6006C_reg.h	4978;"	d
+GET_RG_GEMINIA_FPGA_CLK_REF_40M_PD	smac/hal/ssv6006c/ssv6006C_reg.h	4977;"	d
+GET_RG_GEMINIA_GPIO00_DS	smac/hal/ssv6006c/ssv6006C_reg.h	5003;"	d
+GET_RG_GEMINIA_GPIO00_OE	smac/hal/ssv6006c/ssv6006C_reg.h	5005;"	d
+GET_RG_GEMINIA_GPIO00_PD	smac/hal/ssv6006c/ssv6006C_reg.h	5004;"	d
+GET_RG_GEMINIA_GPIO01_DS	smac/hal/ssv6006c/ssv6006C_reg.h	5006;"	d
+GET_RG_GEMINIA_GPIO01_OE	smac/hal/ssv6006c/ssv6006C_reg.h	5008;"	d
+GET_RG_GEMINIA_GPIO01_PD	smac/hal/ssv6006c/ssv6006C_reg.h	5007;"	d
+GET_RG_GEMINIA_GPIO02_DS	smac/hal/ssv6006c/ssv6006C_reg.h	5009;"	d
+GET_RG_GEMINIA_GPIO02_OE	smac/hal/ssv6006c/ssv6006C_reg.h	5011;"	d
+GET_RG_GEMINIA_GPIO02_PD	smac/hal/ssv6006c/ssv6006C_reg.h	5010;"	d
+GET_RG_GEMINIA_GPIO03_DS	smac/hal/ssv6006c/ssv6006C_reg.h	5012;"	d
+GET_RG_GEMINIA_GPIO03_OE	smac/hal/ssv6006c/ssv6006C_reg.h	5014;"	d
+GET_RG_GEMINIA_GPIO03_PD	smac/hal/ssv6006c/ssv6006C_reg.h	5013;"	d
+GET_RG_GEMINIA_GPIO04_DS	smac/hal/ssv6006c/ssv6006C_reg.h	5015;"	d
+GET_RG_GEMINIA_GPIO04_OE	smac/hal/ssv6006c/ssv6006C_reg.h	5017;"	d
+GET_RG_GEMINIA_GPIO04_PD	smac/hal/ssv6006c/ssv6006C_reg.h	5016;"	d
+GET_RG_GEMINIA_GPIO05_DS	smac/hal/ssv6006c/ssv6006C_reg.h	5018;"	d
+GET_RG_GEMINIA_GPIO05_OE	smac/hal/ssv6006c/ssv6006C_reg.h	5020;"	d
+GET_RG_GEMINIA_GPIO05_PD	smac/hal/ssv6006c/ssv6006C_reg.h	5019;"	d
+GET_RG_GEMINIA_GPIO06_DS	smac/hal/ssv6006c/ssv6006C_reg.h	5021;"	d
+GET_RG_GEMINIA_GPIO06_OE	smac/hal/ssv6006c/ssv6006C_reg.h	5023;"	d
+GET_RG_GEMINIA_GPIO06_PD	smac/hal/ssv6006c/ssv6006C_reg.h	5022;"	d
+GET_RG_GEMINIA_GPIO07_DS	smac/hal/ssv6006c/ssv6006C_reg.h	5024;"	d
+GET_RG_GEMINIA_GPIO07_OE	smac/hal/ssv6006c/ssv6006C_reg.h	5026;"	d
+GET_RG_GEMINIA_GPIO07_PD	smac/hal/ssv6006c/ssv6006C_reg.h	5025;"	d
+GET_RG_GEMINIA_GPIO08_DS	smac/hal/ssv6006c/ssv6006C_reg.h	4979;"	d
+GET_RG_GEMINIA_GPIO08_OE	smac/hal/ssv6006c/ssv6006C_reg.h	4981;"	d
+GET_RG_GEMINIA_GPIO08_PD	smac/hal/ssv6006c/ssv6006C_reg.h	4980;"	d
+GET_RG_GEMINIA_GPIO09_DS	smac/hal/ssv6006c/ssv6006C_reg.h	4982;"	d
+GET_RG_GEMINIA_GPIO09_OE	smac/hal/ssv6006c/ssv6006C_reg.h	4984;"	d
+GET_RG_GEMINIA_GPIO09_PD	smac/hal/ssv6006c/ssv6006C_reg.h	4983;"	d
+GET_RG_GEMINIA_GPIO10_DS	smac/hal/ssv6006c/ssv6006C_reg.h	4985;"	d
+GET_RG_GEMINIA_GPIO10_OE	smac/hal/ssv6006c/ssv6006C_reg.h	4987;"	d
+GET_RG_GEMINIA_GPIO10_PD	smac/hal/ssv6006c/ssv6006C_reg.h	4986;"	d
+GET_RG_GEMINIA_GPIO11_DS	smac/hal/ssv6006c/ssv6006C_reg.h	4988;"	d
+GET_RG_GEMINIA_GPIO11_OE	smac/hal/ssv6006c/ssv6006C_reg.h	4990;"	d
+GET_RG_GEMINIA_GPIO11_PD	smac/hal/ssv6006c/ssv6006C_reg.h	4989;"	d
+GET_RG_GEMINIA_GPIO12_DS	smac/hal/ssv6006c/ssv6006C_reg.h	4991;"	d
+GET_RG_GEMINIA_GPIO12_OE	smac/hal/ssv6006c/ssv6006C_reg.h	4993;"	d
+GET_RG_GEMINIA_GPIO12_PD	smac/hal/ssv6006c/ssv6006C_reg.h	4992;"	d
+GET_RG_GEMINIA_GPIO13_DS	smac/hal/ssv6006c/ssv6006C_reg.h	4994;"	d
+GET_RG_GEMINIA_GPIO13_OE	smac/hal/ssv6006c/ssv6006C_reg.h	4996;"	d
+GET_RG_GEMINIA_GPIO13_PD	smac/hal/ssv6006c/ssv6006C_reg.h	4995;"	d
+GET_RG_GEMINIA_GPIO14_DS	smac/hal/ssv6006c/ssv6006C_reg.h	4997;"	d
+GET_RG_GEMINIA_GPIO14_OE	smac/hal/ssv6006c/ssv6006C_reg.h	4999;"	d
+GET_RG_GEMINIA_GPIO14_PD	smac/hal/ssv6006c/ssv6006C_reg.h	4998;"	d
+GET_RG_GEMINIA_GPIO15_DS	smac/hal/ssv6006c/ssv6006C_reg.h	5000;"	d
+GET_RG_GEMINIA_GPIO15_OE	smac/hal/ssv6006c/ssv6006C_reg.h	5002;"	d
+GET_RG_GEMINIA_GPIO15_PD	smac/hal/ssv6006c/ssv6006C_reg.h	5001;"	d
+GET_RG_GEMINIA_GPIO16_DS	smac/hal/ssv6006c/ssv6006C_reg.h	4960;"	d
+GET_RG_GEMINIA_GPIO16_OE	smac/hal/ssv6006c/ssv6006C_reg.h	4962;"	d
+GET_RG_GEMINIA_GPIO16_PD	smac/hal/ssv6006c/ssv6006C_reg.h	4961;"	d
+GET_RG_GEMINIA_GPIO17_DS	smac/hal/ssv6006c/ssv6006C_reg.h	4963;"	d
+GET_RG_GEMINIA_GPIO17_OE	smac/hal/ssv6006c/ssv6006C_reg.h	4965;"	d
+GET_RG_GEMINIA_GPIO17_PD	smac/hal/ssv6006c/ssv6006C_reg.h	4964;"	d
+GET_RG_GEMINIA_GPIO18_DS	smac/hal/ssv6006c/ssv6006C_reg.h	4966;"	d
+GET_RG_GEMINIA_GPIO18_OE	smac/hal/ssv6006c/ssv6006C_reg.h	4968;"	d
+GET_RG_GEMINIA_GPIO18_PD	smac/hal/ssv6006c/ssv6006C_reg.h	4967;"	d
+GET_RG_GEMINIA_GPIO19_DS	smac/hal/ssv6006c/ssv6006C_reg.h	4969;"	d
+GET_RG_GEMINIA_GPIO19_OE	smac/hal/ssv6006c/ssv6006C_reg.h	4971;"	d
+GET_RG_GEMINIA_GPIO19_PD	smac/hal/ssv6006c/ssv6006C_reg.h	4970;"	d
+GET_RG_GEMINIA_GPIO20_DS	smac/hal/ssv6006c/ssv6006C_reg.h	4972;"	d
+GET_RG_GEMINIA_GPIO20_OE	smac/hal/ssv6006c/ssv6006C_reg.h	4974;"	d
+GET_RG_GEMINIA_GPIO20_PD	smac/hal/ssv6006c/ssv6006C_reg.h	4973;"	d
+GET_RG_GEMINIA_HS_3WIRE_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	4188;"	d
+GET_RG_GEMINIA_HW_PINSEL	smac/hal/ssv6006c/ssv6006C_reg.h	4187;"	d
+GET_RG_GEMINIA_IDACAI_TZ0_COARSE0	smac/hal/ssv6006c/ssv6006C_reg.h	4718;"	d
+GET_RG_GEMINIA_IDACAI_TZ0_COARSE1	smac/hal/ssv6006c/ssv6006C_reg.h	4716;"	d
+GET_RG_GEMINIA_IDACAI_TZ0_COARSE2	smac/hal/ssv6006c/ssv6006C_reg.h	4714;"	d
+GET_RG_GEMINIA_IDACAI_TZ0_COARSE3	smac/hal/ssv6006c/ssv6006C_reg.h	4712;"	d
+GET_RG_GEMINIA_IDACAI_TZ0_COARSE4	smac/hal/ssv6006c/ssv6006C_reg.h	4710;"	d
+GET_RG_GEMINIA_IDACAI_TZ1_COARSE0	smac/hal/ssv6006c/ssv6006C_reg.h	4728;"	d
+GET_RG_GEMINIA_IDACAI_TZ1_COARSE1	smac/hal/ssv6006c/ssv6006C_reg.h	4726;"	d
+GET_RG_GEMINIA_IDACAI_TZ1_COARSE2	smac/hal/ssv6006c/ssv6006C_reg.h	4724;"	d
+GET_RG_GEMINIA_IDACAI_TZ1_COARSE3	smac/hal/ssv6006c/ssv6006C_reg.h	4722;"	d
+GET_RG_GEMINIA_IDACAI_TZ1_COARSE4	smac/hal/ssv6006c/ssv6006C_reg.h	4720;"	d
+GET_RG_GEMINIA_IDACAQ_TZ0_COARSE0	smac/hal/ssv6006c/ssv6006C_reg.h	4719;"	d
+GET_RG_GEMINIA_IDACAQ_TZ0_COARSE1	smac/hal/ssv6006c/ssv6006C_reg.h	4717;"	d
+GET_RG_GEMINIA_IDACAQ_TZ0_COARSE2	smac/hal/ssv6006c/ssv6006C_reg.h	4715;"	d
+GET_RG_GEMINIA_IDACAQ_TZ0_COARSE3	smac/hal/ssv6006c/ssv6006C_reg.h	4713;"	d
+GET_RG_GEMINIA_IDACAQ_TZ0_COARSE4	smac/hal/ssv6006c/ssv6006C_reg.h	4711;"	d
+GET_RG_GEMINIA_IDACAQ_TZ1_COARSE0	smac/hal/ssv6006c/ssv6006C_reg.h	4729;"	d
+GET_RG_GEMINIA_IDACAQ_TZ1_COARSE1	smac/hal/ssv6006c/ssv6006C_reg.h	4727;"	d
+GET_RG_GEMINIA_IDACAQ_TZ1_COARSE2	smac/hal/ssv6006c/ssv6006C_reg.h	4725;"	d
+GET_RG_GEMINIA_IDACAQ_TZ1_COARSE3	smac/hal/ssv6006c/ssv6006C_reg.h	4723;"	d
+GET_RG_GEMINIA_IDACAQ_TZ1_COARSE4	smac/hal/ssv6006c/ssv6006C_reg.h	4721;"	d
+GET_RG_GEMINIA_IQ_SWAP	smac/hal/ssv6006c/ssv6006C_reg.h	4847;"	d
+GET_RG_GEMINIA_I_INV	smac/hal/ssv6006c/ssv6006C_reg.h	4846;"	d
+GET_RG_GEMINIA_LDO_CP_FC	smac/hal/ssv6006c/ssv6006C_reg.h	4509;"	d
+GET_RG_GEMINIA_LDO_CP_FC_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	4508;"	d
+GET_RG_GEMINIA_LDO_DIV_FC	smac/hal/ssv6006c/ssv6006C_reg.h	4511;"	d
+GET_RG_GEMINIA_LDO_DIV_FC_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	4510;"	d
+GET_RG_GEMINIA_LDO_LEVEL_ABB	smac/hal/ssv6006c/ssv6006C_reg.h	4261;"	d
+GET_RG_GEMINIA_LDO_LEVEL_ADC	smac/hal/ssv6006c/ssv6006C_reg.h	4262;"	d
+GET_RG_GEMINIA_LDO_LEVEL_DAC	smac/hal/ssv6006c/ssv6006C_reg.h	4263;"	d
+GET_RG_GEMINIA_LDO_LEVEL_EFUSE	smac/hal/ssv6006c/ssv6006C_reg.h	4926;"	d
+GET_RG_GEMINIA_LDO_LEVEL_RX_FE	smac/hal/ssv6006c/ssv6006C_reg.h	4260;"	d
+GET_RG_GEMINIA_LDO_LO_FC	smac/hal/ssv6006c/ssv6006C_reg.h	4513;"	d
+GET_RG_GEMINIA_LDO_LO_FC_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	4512;"	d
+GET_RG_GEMINIA_LDO_RX_ABB_EN_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	4256;"	d
+GET_RG_GEMINIA_LDO_RX_ADC_EN_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	4257;"	d
+GET_RG_GEMINIA_LDO_RX_FE_EN_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	4255;"	d
+GET_RG_GEMINIA_LDO_TX_DAC_EN_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	4258;"	d
+GET_RG_GEMINIA_LDO_VCO_FC	smac/hal/ssv6006c/ssv6006C_reg.h	4515;"	d
+GET_RG_GEMINIA_LDO_VCO_FC_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	4514;"	d
+GET_RG_GEMINIA_LDO_VCO_RCF	smac/hal/ssv6006c/ssv6006C_reg.h	4516;"	d
+GET_RG_GEMINIA_LOAD_RFTABLE_RDY	smac/hal/ssv6006c/ssv6006C_reg.h	4918;"	d
+GET_RG_GEMINIA_LO_UP_CH	smac/hal/ssv6006c/ssv6006C_reg.h	4837;"	d
+GET_RG_GEMINIA_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	4194;"	d
+GET_RG_GEMINIA_MODE_LATCH_LMT	smac/hal/ssv6006c/ssv6006C_reg.h	5030;"	d
+GET_RG_GEMINIA_MODE_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	4189;"	d
+GET_RG_GEMINIA_NFRAC_DELTA	smac/hal/ssv6006c/ssv6006C_reg.h	4835;"	d
+GET_RG_GEMINIA_PAD_MUX_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	5029;"	d
+GET_RG_GEMINIA_PGAG	smac/hal/ssv6006c/ssv6006C_reg.h	4197;"	d
+GET_RG_GEMINIA_PGAG_DPDCAL	smac/hal/ssv6006c/ssv6006C_reg.h	4821;"	d
+GET_RG_GEMINIA_PGAG_RCCAL	smac/hal/ssv6006c/ssv6006C_reg.h	4814;"	d
+GET_RG_GEMINIA_PGAG_RXIQCAL	smac/hal/ssv6006c/ssv6006C_reg.h	4818;"	d
+GET_RG_GEMINIA_PGAG_TXCAL	smac/hal/ssv6006c/ssv6006C_reg.h	4815;"	d
+GET_RG_GEMINIA_PHASE_17P5M	smac/hal/ssv6006c/ssv6006C_reg.h	4892;"	d
+GET_RG_GEMINIA_PHASE_1M	smac/hal/ssv6006c/ssv6006C_reg.h	4895;"	d
+GET_RG_GEMINIA_PHASE_2P5M	smac/hal/ssv6006c/ssv6006C_reg.h	4893;"	d
+GET_RG_GEMINIA_PHASE_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	4879;"	d
+GET_RG_GEMINIA_PHASE_RXIQ_1M	smac/hal/ssv6006c/ssv6006C_reg.h	4894;"	d
+GET_RG_GEMINIA_PHASE_STEP_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	4878;"	d
+GET_RG_GEMINIA_PMU_ENTER_SLEEP_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	4946;"	d
+GET_RG_GEMINIA_Q_INV	smac/hal/ssv6006c/ssv6006C_reg.h	4845;"	d
+GET_RG_GEMINIA_RAM_00	smac/hal/ssv6006c/ssv6006C_reg.h	5032;"	d
+GET_RG_GEMINIA_RAM_01	smac/hal/ssv6006c/ssv6006C_reg.h	5033;"	d
+GET_RG_GEMINIA_RAM_02	smac/hal/ssv6006c/ssv6006C_reg.h	5034;"	d
+GET_RG_GEMINIA_RAM_03	smac/hal/ssv6006c/ssv6006C_reg.h	5035;"	d
+GET_RG_GEMINIA_RAM_04	smac/hal/ssv6006c/ssv6006C_reg.h	5036;"	d
+GET_RG_GEMINIA_RAM_05	smac/hal/ssv6006c/ssv6006C_reg.h	5037;"	d
+GET_RG_GEMINIA_RAM_06	smac/hal/ssv6006c/ssv6006C_reg.h	5038;"	d
+GET_RG_GEMINIA_RAM_07	smac/hal/ssv6006c/ssv6006C_reg.h	5039;"	d
+GET_RG_GEMINIA_RAM_08	smac/hal/ssv6006c/ssv6006C_reg.h	5040;"	d
+GET_RG_GEMINIA_RAM_09	smac/hal/ssv6006c/ssv6006C_reg.h	5041;"	d
+GET_RG_GEMINIA_RAM_10	smac/hal/ssv6006c/ssv6006C_reg.h	5042;"	d
+GET_RG_GEMINIA_RAM_11	smac/hal/ssv6006c/ssv6006C_reg.h	5043;"	d
+GET_RG_GEMINIA_RAM_12	smac/hal/ssv6006c/ssv6006C_reg.h	5044;"	d
+GET_RG_GEMINIA_RAM_13	smac/hal/ssv6006c/ssv6006C_reg.h	5045;"	d
+GET_RG_GEMINIA_RAM_14	smac/hal/ssv6006c/ssv6006C_reg.h	5046;"	d
+GET_RG_GEMINIA_RAM_15	smac/hal/ssv6006c/ssv6006C_reg.h	5047;"	d
+GET_RG_GEMINIA_RAM_16	smac/hal/ssv6006c/ssv6006C_reg.h	5048;"	d
+GET_RG_GEMINIA_RAM_17	smac/hal/ssv6006c/ssv6006C_reg.h	5049;"	d
+GET_RG_GEMINIA_RAM_18	smac/hal/ssv6006c/ssv6006C_reg.h	5050;"	d
+GET_RG_GEMINIA_RAM_19	smac/hal/ssv6006c/ssv6006C_reg.h	5051;"	d
+GET_RG_GEMINIA_RAM_20	smac/hal/ssv6006c/ssv6006C_reg.h	5052;"	d
+GET_RG_GEMINIA_RAM_21	smac/hal/ssv6006c/ssv6006C_reg.h	5053;"	d
+GET_RG_GEMINIA_RAM_22	smac/hal/ssv6006c/ssv6006C_reg.h	5054;"	d
+GET_RG_GEMINIA_RAM_23	smac/hal/ssv6006c/ssv6006C_reg.h	5055;"	d
+GET_RG_GEMINIA_RAM_24	smac/hal/ssv6006c/ssv6006C_reg.h	5056;"	d
+GET_RG_GEMINIA_RAM_25	smac/hal/ssv6006c/ssv6006C_reg.h	5057;"	d
+GET_RG_GEMINIA_RAM_26	smac/hal/ssv6006c/ssv6006C_reg.h	5058;"	d
+GET_RG_GEMINIA_RAM_27	smac/hal/ssv6006c/ssv6006C_reg.h	5059;"	d
+GET_RG_GEMINIA_RAM_28	smac/hal/ssv6006c/ssv6006C_reg.h	5060;"	d
+GET_RG_GEMINIA_RAM_29	smac/hal/ssv6006c/ssv6006C_reg.h	5061;"	d
+GET_RG_GEMINIA_RAM_30	smac/hal/ssv6006c/ssv6006C_reg.h	5062;"	d
+GET_RG_GEMINIA_RAM_31	smac/hal/ssv6006c/ssv6006C_reg.h	5063;"	d
+GET_RG_GEMINIA_RCCAL_POLAR_INV	smac/hal/ssv6006c/ssv6006C_reg.h	4885;"	d
+GET_RG_GEMINIA_RFG	smac/hal/ssv6006c/ssv6006C_reg.h	4196;"	d
+GET_RG_GEMINIA_RFG_DPDCAL	smac/hal/ssv6006c/ssv6006C_reg.h	4820;"	d
+GET_RG_GEMINIA_RFG_RXIQCAL	smac/hal/ssv6006c/ssv6006C_reg.h	4817;"	d
+GET_RG_GEMINIA_RF_PHY_MODE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	5027;"	d
+GET_RG_GEMINIA_RF_PHY_MODE_WIFI_MAC	smac/hal/ssv6006c/ssv6006C_reg.h	5028;"	d
+GET_RG_GEMINIA_RSSI_CLOCK_GATING	smac/hal/ssv6006c/ssv6006C_reg.h	4300;"	d
+GET_RG_GEMINIA_RSSI_EDGE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	4843;"	d
+GET_RG_GEMINIA_RTC_CAL_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	4937;"	d
+GET_RG_GEMINIA_RTC_CAL_TARGET_COUNT	smac/hal/ssv6006c/ssv6006C_reg.h	4935;"	d
+GET_RG_GEMINIA_RTC_EN	smac/hal/ssv6006c/ssv6006C_reg.h	4947;"	d
+GET_RG_GEMINIA_RTC_INT_ALARM_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	4952;"	d
+GET_RG_GEMINIA_RTC_INT_SEC_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	4951;"	d
+GET_RG_GEMINIA_RTC_OFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	4934;"	d
+GET_RG_GEMINIA_RTC_OSC_RES_SW_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	4936;"	d
+GET_RG_GEMINIA_RTC_OSC_RES_SW_MANUAL_EN	smac/hal/ssv6006c/ssv6006C_reg.h	4939;"	d
+GET_RG_GEMINIA_RTC_RS1	smac/hal/ssv6006c/ssv6006C_reg.h	4931;"	d
+GET_RG_GEMINIA_RTC_RS2	smac/hal/ssv6006c/ssv6006C_reg.h	4932;"	d
+GET_RG_GEMINIA_RTC_SEC_ALARM_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	4956;"	d
+GET_RG_GEMINIA_RTC_SEC_START_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	4955;"	d
+GET_RG_GEMINIA_RXIQ_NOSHRK	smac/hal/ssv6006c/ssv6006C_reg.h	4841;"	d
+GET_RG_GEMINIA_RXRCCALQ_EN_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	4244;"	d
+GET_RG_GEMINIA_RXRF_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	4798;"	d
+GET_RG_GEMINIA_RXRF_R2T_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	4807;"	d
+GET_RG_GEMINIA_RXRF_T2R_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	4803;"	d
+GET_RG_GEMINIA_RX_ABBOUT_TRI_STATE	smac/hal/ssv6006c/ssv6006C_reg.h	4252;"	d
+GET_RG_GEMINIA_RX_ADCRSSI_CLKSEL	smac/hal/ssv6006c/ssv6006C_reg.h	4299;"	d
+GET_RG_GEMINIA_RX_ADCRSSI_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	4297;"	d
+GET_RG_GEMINIA_RX_ADC_CLKSEL	smac/hal/ssv6006c/ssv6006C_reg.h	4425;"	d
+GET_RG_GEMINIA_RX_ADC_DNLEN	smac/hal/ssv6006c/ssv6006C_reg.h	4426;"	d
+GET_RG_GEMINIA_RX_ADC_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	4213;"	d
+GET_RG_GEMINIA_RX_ADC_METAEN	smac/hal/ssv6006c/ssv6006C_reg.h	4427;"	d
+GET_RG_GEMINIA_RX_ADC_TFLAG	smac/hal/ssv6006c/ssv6006C_reg.h	4428;"	d
+GET_RG_GEMINIA_RX_ADC_TSEL	smac/hal/ssv6006c/ssv6006C_reg.h	4429;"	d
+GET_RG_GEMINIA_RX_AGC	smac/hal/ssv6006c/ssv6006C_reg.h	4193;"	d
+GET_RG_GEMINIA_RX_DC_POLAR_INV	smac/hal/ssv6006c/ssv6006C_reg.h	4884;"	d
+GET_RG_GEMINIA_RX_DIV2_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	4205;"	d
+GET_RG_GEMINIA_RX_FILTER_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	4211;"	d
+GET_RG_GEMINIA_RX_GAIN_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	4190;"	d
+GET_RG_GEMINIA_RX_IQCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	4813;"	d
+GET_RG_GEMINIA_RX_IQCAL_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	4240;"	d
+GET_RG_GEMINIA_RX_IQ_ALPHA	smac/hal/ssv6006c/ssv6006C_reg.h	4838;"	d
+GET_RG_GEMINIA_RX_IQ_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	4840;"	d
+GET_RG_GEMINIA_RX_IQ_THETA	smac/hal/ssv6006c/ssv6006C_reg.h	4839;"	d
+GET_RG_GEMINIA_RX_LNA_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	4201;"	d
+GET_RG_GEMINIA_RX_LNA_SETTLE	smac/hal/ssv6006c/ssv6006C_reg.h	4309;"	d
+GET_RG_GEMINIA_RX_LNA_TRI_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	4308;"	d
+GET_RG_GEMINIA_RX_LOBUF_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	4207;"	d
+GET_RG_GEMINIA_RX_MIXER_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	4203;"	d
+GET_RG_GEMINIA_RX_RCCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	4810;"	d
+GET_RG_GEMINIA_RX_RCCAL_TARG	smac/hal/ssv6006c/ssv6006C_reg.h	4883;"	d
+GET_RG_GEMINIA_RX_REC_LPFCORNER	smac/hal/ssv6006c/ssv6006C_reg.h	4298;"	d
+GET_RG_GEMINIA_RX_RSSIADC_TH	smac/hal/ssv6006c/ssv6006C_reg.h	4842;"	d
+GET_RG_GEMINIA_RX_RSSI_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	4215;"	d
+GET_RG_GEMINIA_RX_TZ_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	4209;"	d
+GET_RG_GEMINIA_RX_TZ_OUT_TRISTATE	smac/hal/ssv6006c/ssv6006C_reg.h	4237;"	d
+GET_RG_GEMINIA_RX_TZ_OUT_TRISTATE_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	4236;"	d
+GET_RG_GEMINIA_SARADC_THERMAL	smac/hal/ssv6006c/ssv6006C_reg.h	4438;"	d
+GET_RG_GEMINIA_SARADC_TSSI	smac/hal/ssv6006c/ssv6006C_reg.h	4439;"	d
+GET_RG_GEMINIA_SARADC_VRSEL	smac/hal/ssv6006c/ssv6006C_reg.h	4436;"	d
+GET_RG_GEMINIA_SEL_DPLL_CLK	smac/hal/ssv6006c/ssv6006C_reg.h	4938;"	d
+GET_RG_GEMINIA_SIGN_SWAP	smac/hal/ssv6006c/ssv6006C_reg.h	4848;"	d
+GET_RG_GEMINIA_SLEEP_WAKE_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	4945;"	d
+GET_RG_GEMINIA_SPECTRUM_BW	smac/hal/ssv6006c/ssv6006C_reg.h	4881;"	d
+GET_RG_GEMINIA_SPECTRUM_EN	smac/hal/ssv6006c/ssv6006C_reg.h	4882;"	d
+GET_RG_GEMINIA_SPIS_MISO_DS	smac/hal/ssv6006c/ssv6006C_reg.h	4975;"	d
+GET_RG_GEMINIA_SX_AAC_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	4490;"	d
+GET_RG_GEMINIA_SX_BTRX_SIDE	smac/hal/ssv6006c/ssv6006C_reg.h	4523;"	d
+GET_RG_GEMINIA_SX_CAL_INIT	smac/hal/ssv6006c/ssv6006C_reg.h	4492;"	d
+GET_RG_GEMINIA_SX_CHANNEL	smac/hal/ssv6006c/ssv6006C_reg.h	4525;"	d
+GET_RG_GEMINIA_SX_CP_IOST	smac/hal/ssv6006c/ssv6006C_reg.h	4533;"	d
+GET_RG_GEMINIA_SX_CP_IOST_POL	smac/hal/ssv6006c/ssv6006C_reg.h	4532;"	d
+GET_RG_GEMINIA_SX_CP_ISEL50U_BT	smac/hal/ssv6006c/ssv6006C_reg.h	4527;"	d
+GET_RG_GEMINIA_SX_CP_ISEL50U_WF	smac/hal/ssv6006c/ssv6006C_reg.h	4530;"	d
+GET_RG_GEMINIA_SX_CP_ISEL_BT	smac/hal/ssv6006c/ssv6006C_reg.h	4526;"	d
+GET_RG_GEMINIA_SX_CP_ISEL_WF	smac/hal/ssv6006c/ssv6006C_reg.h	4529;"	d
+GET_RG_GEMINIA_SX_CP_KP_DOUB_BT	smac/hal/ssv6006c/ssv6006C_reg.h	4528;"	d
+GET_RG_GEMINIA_SX_CP_KP_DOUB_WF	smac/hal/ssv6006c/ssv6006C_reg.h	4531;"	d
+GET_RG_GEMINIA_SX_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	4794;"	d
+GET_RG_GEMINIA_SX_DITHER_WEIGHT	smac/hal/ssv6006c/ssv6006C_reg.h	4585;"	d
+GET_RG_GEMINIA_SX_DIV_DMYBUF_EN	smac/hal/ssv6006c/ssv6006C_reg.h	4581;"	d
+GET_RG_GEMINIA_SX_DIV_PREVDD	smac/hal/ssv6006c/ssv6006C_reg.h	4577;"	d
+GET_RG_GEMINIA_SX_DIV_PSCVDD	smac/hal/ssv6006c/ssv6006C_reg.h	4578;"	d
+GET_RG_GEMINIA_SX_DIV_RST_H	smac/hal/ssv6006c/ssv6006C_reg.h	4579;"	d
+GET_RG_GEMINIA_SX_DIV_SDM_EDGE	smac/hal/ssv6006c/ssv6006C_reg.h	4580;"	d
+GET_RG_GEMINIA_SX_EN	smac/hal/ssv6006c/ssv6006C_reg.h	4467;"	d
+GET_RG_GEMINIA_SX_EN_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	4466;"	d
+GET_RG_GEMINIA_SX_FREF_DOUB	smac/hal/ssv6006c/ssv6006C_reg.h	4522;"	d
+GET_RG_GEMINIA_SX_LDO_CP_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	4264;"	d
+GET_RG_GEMINIA_SX_LDO_DIV_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	4268;"	d
+GET_RG_GEMINIA_SX_LDO_FCOFFT	smac/hal/ssv6006c/ssv6006C_reg.h	4507;"	d
+GET_RG_GEMINIA_SX_LDO_LO_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	4265;"	d
+GET_RG_GEMINIA_SX_LDO_VCO_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	4267;"	d
+GET_RG_GEMINIA_SX_LO_TIMES	smac/hal/ssv6006c/ssv6006C_reg.h	4524;"	d
+GET_RG_GEMINIA_SX_LPF_C1_BT	smac/hal/ssv6006c/ssv6006C_reg.h	4541;"	d
+GET_RG_GEMINIA_SX_LPF_C1_WF	smac/hal/ssv6006c/ssv6006C_reg.h	4546;"	d
+GET_RG_GEMINIA_SX_LPF_C2_BT	smac/hal/ssv6006c/ssv6006C_reg.h	4542;"	d
+GET_RG_GEMINIA_SX_LPF_C2_WF	smac/hal/ssv6006c/ssv6006C_reg.h	4547;"	d
+GET_RG_GEMINIA_SX_LPF_C3_BT	smac/hal/ssv6006c/ssv6006C_reg.h	4543;"	d
+GET_RG_GEMINIA_SX_LPF_C3_WF	smac/hal/ssv6006c/ssv6006C_reg.h	4548;"	d
+GET_RG_GEMINIA_SX_LPF_R2_BT	smac/hal/ssv6006c/ssv6006C_reg.h	4544;"	d
+GET_RG_GEMINIA_SX_LPF_R2_WF	smac/hal/ssv6006c/ssv6006C_reg.h	4549;"	d
+GET_RG_GEMINIA_SX_LPF_R3_BT	smac/hal/ssv6006c/ssv6006C_reg.h	4545;"	d
+GET_RG_GEMINIA_SX_LPF_R3_WF	smac/hal/ssv6006c/ssv6006C_reg.h	4550;"	d
+GET_RG_GEMINIA_SX_LPF_VTUNE_TEST	smac/hal/ssv6006c/ssv6006C_reg.h	4615;"	d
+GET_RG_GEMINIA_SX_MOD_ORDER	smac/hal/ssv6006c/ssv6006C_reg.h	4584;"	d
+GET_RG_GEMINIA_SX_PFD_RST	smac/hal/ssv6006c/ssv6006C_reg.h	4475;"	d
+GET_RG_GEMINIA_SX_PFD_RST_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	4474;"	d
+GET_RG_GEMINIA_SX_PFD_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	4534;"	d
+GET_RG_GEMINIA_SX_PFD_SET	smac/hal/ssv6006c/ssv6006C_reg.h	4535;"	d
+GET_RG_GEMINIA_SX_PFD_SET1	smac/hal/ssv6006c/ssv6006C_reg.h	4536;"	d
+GET_RG_GEMINIA_SX_PFD_SET2	smac/hal/ssv6006c/ssv6006C_reg.h	4537;"	d
+GET_RG_GEMINIA_SX_PFD_TLSEL	smac/hal/ssv6006c/ssv6006C_reg.h	4540;"	d
+GET_RG_GEMINIA_SX_PFD_TRDN	smac/hal/ssv6006c/ssv6006C_reg.h	4539;"	d
+GET_RG_GEMINIA_SX_PFD_TRUP	smac/hal/ssv6006c/ssv6006C_reg.h	4538;"	d
+GET_RG_GEMINIA_SX_RFCH_MAP_EN	smac/hal/ssv6006c/ssv6006C_reg.h	4520;"	d
+GET_RG_GEMINIA_SX_RFCTRL_CH_10_8	smac/hal/ssv6006c/ssv6006C_reg.h	4519;"	d
+GET_RG_GEMINIA_SX_RFCTRL_CH_7_0	smac/hal/ssv6006c/ssv6006C_reg.h	4518;"	d
+GET_RG_GEMINIA_SX_RFCTRL_F	smac/hal/ssv6006c/ssv6006C_reg.h	4517;"	d
+GET_RG_GEMINIA_SX_SBCAL_AW	smac/hal/ssv6006c/ssv6006C_reg.h	4489;"	d
+GET_RG_GEMINIA_SX_SBCAL_CT	smac/hal/ssv6006c/ssv6006C_reg.h	4589;"	d
+GET_RG_GEMINIA_SX_SBCAL_DIFFMIN	smac/hal/ssv6006c/ssv6006C_reg.h	4591;"	d
+GET_RG_GEMINIA_SX_SBCAL_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	4488;"	d
+GET_RG_GEMINIA_SX_SBCAL_NTARG	smac/hal/ssv6006c/ssv6006C_reg.h	4593;"	d
+GET_RG_GEMINIA_SX_SBCAL_NTARG_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	4592;"	d
+GET_RG_GEMINIA_SX_SBCAL_WT	smac/hal/ssv6006c/ssv6006C_reg.h	4590;"	d
+GET_RG_GEMINIA_SX_SUB_C0P5_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	4588;"	d
+GET_RG_GEMINIA_SX_SUB_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	4587;"	d
+GET_RG_GEMINIA_SX_SUB_SEL_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	4586;"	d
+GET_RG_GEMINIA_SX_TTL_ACCUM	smac/hal/ssv6006c/ssv6006C_reg.h	4610;"	d
+GET_RG_GEMINIA_SX_TTL_CPT	smac/hal/ssv6006c/ssv6006C_reg.h	4609;"	d
+GET_RG_GEMINIA_SX_TTL_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	4491;"	d
+GET_RG_GEMINIA_SX_TTL_FPT	smac/hal/ssv6006c/ssv6006C_reg.h	4608;"	d
+GET_RG_GEMINIA_SX_TTL_INIT	smac/hal/ssv6006c/ssv6006C_reg.h	4607;"	d
+GET_RG_GEMINIA_SX_TTL_SUB	smac/hal/ssv6006c/ssv6006C_reg.h	4611;"	d
+GET_RG_GEMINIA_SX_TTL_SUB_INV	smac/hal/ssv6006c/ssv6006C_reg.h	4612;"	d
+GET_RG_GEMINIA_SX_TTL_VH	smac/hal/ssv6006c/ssv6006C_reg.h	4613;"	d
+GET_RG_GEMINIA_SX_TTL_VL	smac/hal/ssv6006c/ssv6006C_reg.h	4614;"	d
+GET_RG_GEMINIA_SX_UOP_EN	smac/hal/ssv6006c/ssv6006C_reg.h	4477;"	d
+GET_RG_GEMINIA_SX_UOP_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	4476;"	d
+GET_RG_GEMINIA_SX_VCO_CS_AWH	smac/hal/ssv6006c/ssv6006C_reg.h	4562;"	d
+GET_RG_GEMINIA_SX_VCO_ISEL_BT	smac/hal/ssv6006c/ssv6006C_reg.h	4552;"	d
+GET_RG_GEMINIA_SX_VCO_ISEL_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	4551;"	d
+GET_RG_GEMINIA_SX_VCO_ISEL_WF	smac/hal/ssv6006c/ssv6006C_reg.h	4556;"	d
+GET_RG_GEMINIA_SX_VCO_KVDOUB_BT	smac/hal/ssv6006c/ssv6006C_reg.h	4555;"	d
+GET_RG_GEMINIA_SX_VCO_KVDOUB_WF	smac/hal/ssv6006c/ssv6006C_reg.h	4559;"	d
+GET_RG_GEMINIA_SX_VCO_LPM_BT	smac/hal/ssv6006c/ssv6006C_reg.h	4553;"	d
+GET_RG_GEMINIA_SX_VCO_LPM_WF	smac/hal/ssv6006c/ssv6006C_reg.h	4557;"	d
+GET_RG_GEMINIA_SX_VCO_RTAIL_SHIFT	smac/hal/ssv6006c/ssv6006C_reg.h	4561;"	d
+GET_RG_GEMINIA_SX_VCO_RXOB_AW	smac/hal/ssv6006c/ssv6006C_reg.h	4573;"	d
+GET_RG_GEMINIA_SX_VCO_TXOB_AW	smac/hal/ssv6006c/ssv6006C_reg.h	4572;"	d
+GET_RG_GEMINIA_SX_VCO_VARBSEL	smac/hal/ssv6006c/ssv6006C_reg.h	4560;"	d
+GET_RG_GEMINIA_SX_VCO_VCCBSEL_BT	smac/hal/ssv6006c/ssv6006C_reg.h	4554;"	d
+GET_RG_GEMINIA_SX_VCO_VCCBSEL_WF	smac/hal/ssv6006c/ssv6006C_reg.h	4558;"	d
+GET_RG_GEMINIA_SX_XTAL_FREQ	smac/hal/ssv6006c/ssv6006C_reg.h	4521;"	d
+GET_RG_GEMINIA_TONE_SCALE	smac/hal/ssv6006c/ssv6006C_reg.h	4854;"	d
+GET_RG_GEMINIA_TXBTPA_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	4799;"	d
+GET_RG_GEMINIA_TXDAC_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	4795;"	d
+GET_RG_GEMINIA_TXDAC_R2T_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	4804;"	d
+GET_RG_GEMINIA_TXDAC_T2R_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	4800;"	d
+GET_RG_GEMINIA_TXGAIN_PHYCTRL	smac/hal/ssv6006c/ssv6006C_reg.h	4192;"	d
+GET_RG_GEMINIA_TXIQ_NOSHRK	smac/hal/ssv6006c/ssv6006C_reg.h	4852;"	d
+GET_RG_GEMINIA_TXLPF_BYPASS	smac/hal/ssv6006c/ssv6006C_reg.h	4248;"	d
+GET_RG_GEMINIA_TXLPF_GMCELL	smac/hal/ssv6006c/ssv6006C_reg.h	4330;"	d
+GET_RG_GEMINIA_TXMOD_GMCELL	smac/hal/ssv6006c/ssv6006C_reg.h	4329;"	d
+GET_RG_GEMINIA_TXPA_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	4797;"	d
+GET_RG_GEMINIA_TXPA_R2T_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	4806;"	d
+GET_RG_GEMINIA_TXPA_T2R_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	4802;"	d
+GET_RG_GEMINIA_TXPGA_MAIN	smac/hal/ssv6006c/ssv6006C_reg.h	4327;"	d
+GET_RG_GEMINIA_TXPGA_STEER	smac/hal/ssv6006c/ssv6006C_reg.h	4328;"	d
+GET_RG_GEMINIA_TXRF_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	4796;"	d
+GET_RG_GEMINIA_TXRF_R2T_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	4805;"	d
+GET_RG_GEMINIA_TXRF_T2R_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	4801;"	d
+GET_RG_GEMINIA_TX_BT_PA_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	4227;"	d
+GET_RG_GEMINIA_TX_DAC_CAL_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	4234;"	d
+GET_RG_GEMINIA_TX_DAC_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	4221;"	d
+GET_RG_GEMINIA_TX_DAC_TSEL	smac/hal/ssv6006c/ssv6006C_reg.h	4453;"	d
+GET_RG_GEMINIA_TX_DIV2_BUF_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	4225;"	d
+GET_RG_GEMINIA_TX_DIV2_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	4223;"	d
+GET_RG_GEMINIA_TX_DPDGM_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	4301;"	d
+GET_RG_GEMINIA_TX_DPD_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	4302;"	d
+GET_RG_GEMINIA_TX_DPD_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	4242;"	d
+GET_RG_GEMINIA_TX_EN_VOLTAGE_IN	smac/hal/ssv6006c/ssv6006C_reg.h	4249;"	d
+GET_RG_GEMINIA_TX_FREQ_OFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	4853;"	d
+GET_RG_GEMINIA_TX_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	4198;"	d
+GET_RG_GEMINIA_TX_GAIN_DPDCAL	smac/hal/ssv6006c/ssv6006C_reg.h	4822;"	d
+GET_RG_GEMINIA_TX_GAIN_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	4191;"	d
+GET_RG_GEMINIA_TX_GAIN_RXIQCAL	smac/hal/ssv6006c/ssv6006C_reg.h	4819;"	d
+GET_RG_GEMINIA_TX_GAIN_TXCAL	smac/hal/ssv6006c/ssv6006C_reg.h	4816;"	d
+GET_RG_GEMINIA_TX_IQCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	4812;"	d
+GET_RG_GEMINIA_TX_IQ_ALPHA	smac/hal/ssv6006c/ssv6006C_reg.h	4849;"	d
+GET_RG_GEMINIA_TX_IQ_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	4851;"	d
+GET_RG_GEMINIA_TX_IQ_THETA	smac/hal/ssv6006c/ssv6006C_reg.h	4850;"	d
+GET_RG_GEMINIA_TX_LOCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	4811;"	d
+GET_RG_GEMINIA_TX_MOD_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	4219;"	d
+GET_RG_GEMINIA_TX_PA_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	4217;"	d
+GET_RG_GEMINIA_TX_SELF_MIXER_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	4238;"	d
+GET_RG_GEMINIA_TX_TRSW_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	4199;"	d
+GET_RG_GEMINIA_TX_TSSI_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	4303;"	d
+GET_RG_GEMINIA_TX_TSSI_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	4304;"	d
+GET_RG_GEMINIA_TX_TSSI_TEST	smac/hal/ssv6006c/ssv6006C_reg.h	4305;"	d
+GET_RG_GEMINIA_TX_TSSI_TESTMODE	smac/hal/ssv6006c/ssv6006C_reg.h	4306;"	d
+GET_RG_GEMINIA_TX_UP8X_MAN_EN	smac/hal/ssv6006c/ssv6006C_reg.h	4855;"	d
+GET_RG_GEMINIA_TX_VTOI_CURRENT	smac/hal/ssv6006c/ssv6006C_reg.h	4333;"	d
+GET_RG_GEMINIA_TX_VTOI_FS	smac/hal/ssv6006c/ssv6006C_reg.h	4336;"	d
+GET_RG_GEMINIA_TX_VTOI_GM	smac/hal/ssv6006c/ssv6006C_reg.h	4334;"	d
+GET_RG_GEMINIA_TX_VTOI_OPTION	smac/hal/ssv6006c/ssv6006C_reg.h	4335;"	d
+GET_RG_GEMINIA_VOBF_CAPIMB	smac/hal/ssv6006c/ssv6006C_reg.h	4575;"	d
+GET_RG_GEMINIA_VOBF_CAPIMB_POL	smac/hal/ssv6006c/ssv6006C_reg.h	4574;"	d
+GET_RG_GEMINIA_VOBF_DIVBFSEL	smac/hal/ssv6006c/ssv6006C_reg.h	4571;"	d
+GET_RG_GEMINIA_VOBF_RXMBSEL_BT	smac/hal/ssv6006c/ssv6006C_reg.h	4565;"	d
+GET_RG_GEMINIA_VOBF_RXMBSEL_WF	smac/hal/ssv6006c/ssv6006C_reg.h	4569;"	d
+GET_RG_GEMINIA_VOBF_RXOBSEL_BT	smac/hal/ssv6006c/ssv6006C_reg.h	4566;"	d
+GET_RG_GEMINIA_VOBF_RXOBSEL_WF	smac/hal/ssv6006c/ssv6006C_reg.h	4570;"	d
+GET_RG_GEMINIA_VOBF_TXMBSEL_BT	smac/hal/ssv6006c/ssv6006C_reg.h	4563;"	d
+GET_RG_GEMINIA_VOBF_TXMBSEL_WF	smac/hal/ssv6006c/ssv6006C_reg.h	4567;"	d
+GET_RG_GEMINIA_VOBF_TXOBSEL_BT	smac/hal/ssv6006c/ssv6006C_reg.h	4564;"	d
+GET_RG_GEMINIA_VOBF_TXOBSEL_WF	smac/hal/ssv6006c/ssv6006C_reg.h	4568;"	d
+GET_RG_GEMINIA_VO_AAC_EN	smac/hal/ssv6006c/ssv6006C_reg.h	4602;"	d
+GET_RG_GEMINIA_VO_AAC_EN_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	4601;"	d
+GET_RG_GEMINIA_VO_AAC_EVA	smac/hal/ssv6006c/ssv6006C_reg.h	4604;"	d
+GET_RG_GEMINIA_VO_AAC_EVA_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	4603;"	d
+GET_RG_GEMINIA_VO_AAC_EVA_TS	smac/hal/ssv6006c/ssv6006C_reg.h	4600;"	d
+GET_RG_GEMINIA_VO_AAC_IMAX	smac/hal/ssv6006c/ssv6006C_reg.h	4598;"	d
+GET_RG_GEMINIA_VO_AAC_INIT	smac/hal/ssv6006c/ssv6006C_reg.h	4599;"	d
+GET_RG_GEMINIA_VO_AAC_IOST_BT	smac/hal/ssv6006c/ssv6006C_reg.h	4595;"	d
+GET_RG_GEMINIA_VO_AAC_IOST_WF	smac/hal/ssv6006c/ssv6006C_reg.h	4597;"	d
+GET_RG_GEMINIA_VO_AAC_TAR_BT	smac/hal/ssv6006c/ssv6006C_reg.h	4594;"	d
+GET_RG_GEMINIA_VO_AAC_TAR_WF	smac/hal/ssv6006c/ssv6006C_reg.h	4596;"	d
+GET_RG_GEMINIA_VO_AAC_TEST_EN	smac/hal/ssv6006c/ssv6006C_reg.h	4605;"	d
+GET_RG_GEMINIA_VO_AAC_TEST_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	4606;"	d
+GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	4676;"	d
+GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	4674;"	d
+GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	4656;"	d
+GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	4654;"	d
+GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	4652;"	d
+GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	4650;"	d
+GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	4648;"	d
+GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	4646;"	d
+GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	4672;"	d
+GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	4670;"	d
+GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	4668;"	d
+GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	4666;"	d
+GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	4664;"	d
+GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	4662;"	d
+GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	4660;"	d
+GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	4658;"	d
+GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	4708;"	d
+GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	4706;"	d
+GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	4688;"	d
+GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	4686;"	d
+GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	4684;"	d
+GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	4682;"	d
+GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	4680;"	d
+GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	4678;"	d
+GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	4704;"	d
+GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	4702;"	d
+GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	4700;"	d
+GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	4698;"	d
+GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	4696;"	d
+GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	4694;"	d
+GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	4692;"	d
+GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	4690;"	d
+GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	4677;"	d
+GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	4675;"	d
+GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	4657;"	d
+GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	4655;"	d
+GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	4653;"	d
+GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	4651;"	d
+GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	4649;"	d
+GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	4647;"	d
+GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	4673;"	d
+GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	4671;"	d
+GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	4669;"	d
+GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	4667;"	d
+GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	4665;"	d
+GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	4663;"	d
+GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	4661;"	d
+GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	4659;"	d
+GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	4709;"	d
+GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	4707;"	d
+GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	4689;"	d
+GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	4687;"	d
+GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	4685;"	d
+GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	4683;"	d
+GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	4681;"	d
+GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	4679;"	d
+GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	4705;"	d
+GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	4703;"	d
+GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	4701;"	d
+GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	4699;"	d
+GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	4697;"	d
+GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	4695;"	d
+GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	4693;"	d
+GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	4691;"	d
+GET_RG_GEMINIA_WF_PABIAS_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	4319;"	d
+GET_RG_GEMINIA_WF_PACELL_EN	smac/hal/ssv6006c/ssv6006C_reg.h	4318;"	d
+GET_RG_GEMINIA_WF_RX_ABBCFIX	smac/hal/ssv6006c/ssv6006C_reg.h	4275;"	d
+GET_RG_GEMINIA_WF_RX_ABBCTUNEI	smac/hal/ssv6006c/ssv6006C_reg.h	4269;"	d
+GET_RG_GEMINIA_WF_RX_ABBCTUNEQ	smac/hal/ssv6006c/ssv6006C_reg.h	4270;"	d
+GET_RG_GEMINIA_WF_RX_ABB_BT_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	4277;"	d
+GET_RG_GEMINIA_WF_RX_ABB_IDIV3	smac/hal/ssv6006c/ssv6006C_reg.h	4278;"	d
+GET_RG_GEMINIA_WF_RX_ABB_N_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	4276;"	d
+GET_RG_GEMINIA_WF_RX_ADC_CLOAD	smac/hal/ssv6006c/ssv6006C_reg.h	4432;"	d
+GET_RG_GEMINIA_WF_RX_ADC_ICMP	smac/hal/ssv6006c/ssv6006C_reg.h	4430;"	d
+GET_RG_GEMINIA_WF_RX_ADC_VCMI	smac/hal/ssv6006c/ssv6006C_reg.h	4431;"	d
+GET_RG_GEMINIA_WF_RX_DCCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	4808;"	d
+GET_RG_GEMINIA_WF_RX_EN_IDACA_COARSE	smac/hal/ssv6006c/ssv6006C_reg.h	4279;"	d
+GET_RG_GEMINIA_WF_RX_EN_LOOPA	smac/hal/ssv6006c/ssv6006C_reg.h	4280;"	d
+GET_RG_GEMINIA_WF_RX_FILTERI1ST	smac/hal/ssv6006c/ssv6006C_reg.h	4272;"	d
+GET_RG_GEMINIA_WF_RX_FILTERI2ND	smac/hal/ssv6006c/ssv6006C_reg.h	4273;"	d
+GET_RG_GEMINIA_WF_RX_FILTERI3RD	smac/hal/ssv6006c/ssv6006C_reg.h	4274;"	d
+GET_RG_GEMINIA_WF_RX_FILTERI_COARSE	smac/hal/ssv6006c/ssv6006C_reg.h	4271;"	d
+GET_RG_GEMINIA_WF_RX_FILTERVCM	smac/hal/ssv6006c/ssv6006C_reg.h	4281;"	d
+GET_RG_GEMINIA_WF_RX_HG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	4344;"	d
+GET_RG_GEMINIA_WF_RX_HG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	4339;"	d
+GET_RG_GEMINIA_WF_RX_HG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	4340;"	d
+GET_RG_GEMINIA_WF_RX_HG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	4341;"	d
+GET_RG_GEMINIA_WF_RX_HG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	4337;"	d
+GET_RG_GEMINIA_WF_RX_HG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	4345;"	d
+GET_RG_GEMINIA_WF_RX_HG_SQDC	smac/hal/ssv6006c/ssv6006C_reg.h	4343;"	d
+GET_RG_GEMINIA_WF_RX_HG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	4346;"	d
+GET_RG_GEMINIA_WF_RX_HG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	4342;"	d
+GET_RG_GEMINIA_WF_RX_HG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	4338;"	d
+GET_RG_GEMINIA_WF_RX_HG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	4347;"	d
+GET_RG_GEMINIA_WF_RX_LG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	4366;"	d
+GET_RG_GEMINIA_WF_RX_LG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	4361;"	d
+GET_RG_GEMINIA_WF_RX_LG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	4362;"	d
+GET_RG_GEMINIA_WF_RX_LG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	4363;"	d
+GET_RG_GEMINIA_WF_RX_LG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	4359;"	d
+GET_RG_GEMINIA_WF_RX_LG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	4367;"	d
+GET_RG_GEMINIA_WF_RX_LG_SQDC	smac/hal/ssv6006c/ssv6006C_reg.h	4365;"	d
+GET_RG_GEMINIA_WF_RX_LG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	4368;"	d
+GET_RG_GEMINIA_WF_RX_LG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	4364;"	d
+GET_RG_GEMINIA_WF_RX_LG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	4360;"	d
+GET_RG_GEMINIA_WF_RX_LG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	4369;"	d
+GET_RG_GEMINIA_WF_RX_MG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	4355;"	d
+GET_RG_GEMINIA_WF_RX_MG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	4350;"	d
+GET_RG_GEMINIA_WF_RX_MG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	4351;"	d
+GET_RG_GEMINIA_WF_RX_MG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	4352;"	d
+GET_RG_GEMINIA_WF_RX_MG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	4348;"	d
+GET_RG_GEMINIA_WF_RX_MG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	4356;"	d
+GET_RG_GEMINIA_WF_RX_MG_SQDC	smac/hal/ssv6006c/ssv6006C_reg.h	4354;"	d
+GET_RG_GEMINIA_WF_RX_MG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	4357;"	d
+GET_RG_GEMINIA_WF_RX_MG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	4353;"	d
+GET_RG_GEMINIA_WF_RX_MG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	4349;"	d
+GET_RG_GEMINIA_WF_RX_MG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	4358;"	d
+GET_RG_GEMINIA_WF_RX_OUTVCM	smac/hal/ssv6006c/ssv6006C_reg.h	4282;"	d
+GET_RG_GEMINIA_WF_RX_ULG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	4377;"	d
+GET_RG_GEMINIA_WF_RX_ULG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	4372;"	d
+GET_RG_GEMINIA_WF_RX_ULG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	4373;"	d
+GET_RG_GEMINIA_WF_RX_ULG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	4374;"	d
+GET_RG_GEMINIA_WF_RX_ULG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	4370;"	d
+GET_RG_GEMINIA_WF_RX_ULG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	4378;"	d
+GET_RG_GEMINIA_WF_RX_ULG_SQDC	smac/hal/ssv6006c/ssv6006C_reg.h	4376;"	d
+GET_RG_GEMINIA_WF_RX_ULG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	4379;"	d
+GET_RG_GEMINIA_WF_RX_ULG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	4375;"	d
+GET_RG_GEMINIA_WF_RX_ULG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	4371;"	d
+GET_RG_GEMINIA_WF_RX_ULG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	4380;"	d
+GET_RG_GEMINIA_WF_TXLPF_BOOSTI	smac/hal/ssv6006c/ssv6006C_reg.h	4447;"	d
+GET_RG_GEMINIA_WF_TXPGA_CAPSW	smac/hal/ssv6006c/ssv6006C_reg.h	4310;"	d
+GET_RG_GEMINIA_WF_TX_DACI1ST	smac/hal/ssv6006c/ssv6006C_reg.h	4441;"	d
+GET_RG_GEMINIA_WF_TX_DACLPF_ICOARSE	smac/hal/ssv6006c/ssv6006C_reg.h	4442;"	d
+GET_RG_GEMINIA_WF_TX_DACLPF_IFINE	smac/hal/ssv6006c/ssv6006C_reg.h	4443;"	d
+GET_RG_GEMINIA_WF_TX_DACLPF_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	4444;"	d
+GET_RG_GEMINIA_WF_TX_DAC_CKEDGE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	4449;"	d
+GET_RG_GEMINIA_WF_TX_DAC_IATTN	smac/hal/ssv6006c/ssv6006C_reg.h	4446;"	d
+GET_RG_GEMINIA_WF_TX_DAC_IBIAS	smac/hal/ssv6006c/ssv6006C_reg.h	4445;"	d
+GET_RG_GEMINIA_WF_TX_DAC_IOFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	4451;"	d
+GET_RG_GEMINIA_WF_TX_DAC_OS	smac/hal/ssv6006c/ssv6006C_reg.h	4450;"	d
+GET_RG_GEMINIA_WF_TX_DAC_QOFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	4452;"	d
+GET_RG_GEMINIA_WF_TX_DAC_RCAL	smac/hal/ssv6006c/ssv6006C_reg.h	4448;"	d
+GET_RG_GEMINIA_WF_TX_DIV_VSET	smac/hal/ssv6006c/ssv6006C_reg.h	4311;"	d
+GET_RG_GEMINIA_WF_TX_GAIN_OFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	4331;"	d
+GET_RG_GEMINIA_WF_TX_LOBUF_VSET	smac/hal/ssv6006c/ssv6006C_reg.h	4312;"	d
+GET_RG_GEMINIA_WF_TX_PA1_VCAS	smac/hal/ssv6006c/ssv6006C_reg.h	4320;"	d
+GET_RG_GEMINIA_WF_TX_PA2_VCAS	smac/hal/ssv6006c/ssv6006C_reg.h	4321;"	d
+GET_RG_GEMINIA_WF_TX_PA3_VCAS	smac/hal/ssv6006c/ssv6006C_reg.h	4322;"	d
+GET_RG_GEMINIA_WF_TX_VDDSW	smac/hal/ssv6006c/ssv6006C_reg.h	4313;"	d
+GET_RG_GEMINIA_XO_CBANKI	smac/hal/ssv6006c/ssv6006C_reg.h	4899;"	d
+GET_RG_GEMINIA_XO_CBANKO	smac/hal/ssv6006c/ssv6006C_reg.h	4900;"	d
+GET_RG_GEMINIA_XO_LDO_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	4898;"	d
+GET_RG_GEMINIA_XO_TIMMER	smac/hal/ssv6006c/ssv6006C_reg.h	4912;"	d
+GET_RG_GP_DIV_EN	include/ssv6200_reg.h	4377;"	d
+GET_RG_HB_COEF0	include/ssv6200_reg.h	4072;"	d
+GET_RG_HB_COEF1	include/ssv6200_reg.h	4073;"	d
+GET_RG_HB_COEF2	include/ssv6200_reg.h	4074;"	d
+GET_RG_HB_COEF3	include/ssv6200_reg.h	4075;"	d
+GET_RG_HB_COEF4	include/ssv6200_reg.h	4076;"	d
+GET_RG_HG_PGA_SAT1_PGA_GAIN	include/ssv6200_reg.h	3940;"	d
+GET_RG_HG_PGA_SAT1_PGA_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	8259;"	d
+GET_RG_HG_PGA_SAT2_PGA_GAIN	include/ssv6200_reg.h	3939;"	d
+GET_RG_HG_PGA_SAT2_PGA_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	8258;"	d
+GET_RG_HG_RF_SAT_PGA_GAIN	include/ssv6200_reg.h	3941;"	d
+GET_RG_HG_RF_SAT_PGA_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	8260;"	d
+GET_RG_HPF1_FAST_SET_X	include/ssv6200_reg.h	4602;"	d
+GET_RG_HPF1_FAST_SET_Y	include/ssv6200_reg.h	4603;"	d
+GET_RG_HPF1_FAST_SET_Z	include/ssv6200_reg.h	4604;"	d
+GET_RG_HPF_T1A	include/ssv6200_reg.h	4605;"	d
+GET_RG_HPF_T1B	include/ssv6200_reg.h	4606;"	d
+GET_RG_HPF_T1C	include/ssv6200_reg.h	4607;"	d
+GET_RG_HS3W_COMM_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	7682;"	d
+GET_RG_HS3W_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	7681;"	d
+GET_RG_HS3W_PGAGC	smac/hal/ssv6006c/ssv6006C_reg.h	7677;"	d
+GET_RG_HS3W_RFGC	smac/hal/ssv6006c/ssv6006C_reg.h	7678;"	d
+GET_RG_HS3W_RF_PHY_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	7680;"	d
+GET_RG_HS3W_RXAGC	smac/hal/ssv6006c/ssv6006C_reg.h	7679;"	d
+GET_RG_HS3W_START_SENT	smac/hal/ssv6006c/ssv6006C_reg.h	7683;"	d
+GET_RG_HS3W_SX_CHANNEL_INT	smac/hal/ssv6006c/ssv6006C_reg.h	7686;"	d
+GET_RG_HS3W_SX_RFCH_MAP_EN_INT	smac/hal/ssv6006c/ssv6006C_reg.h	7685;"	d
+GET_RG_HS3W_SX_RFCTRL_CH_INT_10_8	smac/hal/ssv6006c/ssv6006C_reg.h	7684;"	d
+GET_RG_HS3W_SX_RFCTRL_CH_INT_7_0	smac/hal/ssv6006c/ssv6006C_reg.h	7688;"	d
+GET_RG_HS3W_SX_RFCTRL_F_INT	smac/hal/ssv6006c/ssv6006C_reg.h	7687;"	d
+GET_RG_HS3W_TX_RF_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	7676;"	d
+GET_RG_HS5W_M_CAL_INDEX	smac/hal/ssv6006c/ssv6006C_reg.h	8025;"	d
+GET_RG_HS5W_M_CMD0_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8023;"	d
+GET_RG_HS5W_M_CMD1_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8022;"	d
+GET_RG_HS5W_M_CMD2_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8021;"	d
+GET_RG_HS5W_M_CMD3_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8020;"	d
+GET_RG_HS5W_M_CMD4_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8019;"	d
+GET_RG_HS5W_M_CMD5_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8018;"	d
+GET_RG_HS5W_M_CMD6_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8017;"	d
+GET_RG_HS5W_M_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	8016;"	d
+GET_RG_HS5W_M_MD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8015;"	d
+GET_RG_HS5W_M_PGAGC	smac/hal/ssv6006c/ssv6006C_reg.h	8026;"	d
+GET_RG_HS5W_M_PHY_BW	smac/hal/ssv6006c/ssv6006C_reg.h	8037;"	d
+GET_RG_HS5W_M_RFGC	smac/hal/ssv6006c/ssv6006C_reg.h	8027;"	d
+GET_RG_HS5W_M_RF_PHY_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	8024;"	d
+GET_RG_HS5W_M_SX5GB_CHANNEL	smac/hal/ssv6006c/ssv6006C_reg.h	8036;"	d
+GET_RG_HS5W_M_SX5GB_RFCH_MAP_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8034;"	d
+GET_RG_HS5W_M_SX5GB_RFCTRL_CH	smac/hal/ssv6006c/ssv6006C_reg.h	8030;"	d
+GET_RG_HS5W_M_SX5GB_RFCTRL_F	smac/hal/ssv6006c/ssv6006C_reg.h	8033;"	d
+GET_RG_HS5W_M_SX_CHANNEL	smac/hal/ssv6006c/ssv6006C_reg.h	8035;"	d
+GET_RG_HS5W_M_SX_RFCH_MAP_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8032;"	d
+GET_RG_HS5W_M_SX_RFCTRL_CH	smac/hal/ssv6006c/ssv6006C_reg.h	8029;"	d
+GET_RG_HS5W_M_SX_RFCTRL_F	smac/hal/ssv6006c/ssv6006C_reg.h	8031;"	d
+GET_RG_HS5W_M_TXPWRLVL	smac/hal/ssv6006c/ssv6006C_reg.h	8028;"	d
+GET_RG_HSDIV_INBFSEL	smac/hal/ssv6006c/ssv6006C_reg.h	7355;"	d
+GET_RG_HSDIV_OBFMX_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	7356;"	d
+GET_RG_HSDIV_OBFSX_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	7357;"	d
+GET_RG_HSDIV_VRSEL	smac/hal/ssv6006c/ssv6006C_reg.h	7358;"	d
+GET_RG_HS_3WIRE_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	6458;"	d
+GET_RG_HT20_RX_FFT_SCALE	smac/hal/ssv6006c/ssv6006C_reg.h	8559;"	d
+GET_RG_HT20_SYM_BOUND_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8551;"	d
+GET_RG_HT20_TR_LPF_KI	smac/hal/ssv6006c/ssv6006C_reg.h	8547;"	d
+GET_RG_HT20_TR_LPF_KP	smac/hal/ssv6006c/ssv6006C_reg.h	8548;"	d
+GET_RG_HT40_RX_FFT_SCALE	smac/hal/ssv6006c/ssv6006C_reg.h	8581;"	d
+GET_RG_HT40_SYM_BOUND_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8546;"	d
+GET_RG_HT40_TR_LPF_KI	smac/hal/ssv6006c/ssv6006C_reg.h	8544;"	d
+GET_RG_HT40_TR_LPF_KP	smac/hal/ssv6006c/ssv6006C_reg.h	8545;"	d
+GET_RG_HTCARR52_FFT_SCALE	include/ssv6200_reg.h	4200;"	d
+GET_RG_HTCARR56_FFT_SCALE	include/ssv6200_reg.h	4201;"	d
+GET_RG_HT_LTF_SEL_EQ	include/ssv6200_reg.h	4328;"	d
+GET_RG_HT_LTF_SEL_PILOT	include/ssv6200_reg.h	4329;"	d
+GET_RG_HW_PINSEL	smac/hal/ssv6006c/ssv6006C_reg.h	6457;"	d
+GET_RG_HW_WAKE_XOSC	smac/hal/ssv6006c/ssv6006C_reg.h	8050;"	d
+GET_RG_HW_WAKE_XOSC_SLP	smac/hal/ssv6006c/ssv6006C_reg.h	8164;"	d
+GET_RG_IDACAI_PGAG0	include/ssv6200_reg.h	4755;"	d
+GET_RG_IDACAI_PGAG1	include/ssv6200_reg.h	4753;"	d
+GET_RG_IDACAI_PGAG10	include/ssv6200_reg.h	4735;"	d
+GET_RG_IDACAI_PGAG11	include/ssv6200_reg.h	4733;"	d
+GET_RG_IDACAI_PGAG12	include/ssv6200_reg.h	4731;"	d
+GET_RG_IDACAI_PGAG13	include/ssv6200_reg.h	4729;"	d
+GET_RG_IDACAI_PGAG14	include/ssv6200_reg.h	4726;"	d
+GET_RG_IDACAI_PGAG15	include/ssv6200_reg.h	4724;"	d
+GET_RG_IDACAI_PGAG2	include/ssv6200_reg.h	4751;"	d
+GET_RG_IDACAI_PGAG3	include/ssv6200_reg.h	4749;"	d
+GET_RG_IDACAI_PGAG4	include/ssv6200_reg.h	4747;"	d
+GET_RG_IDACAI_PGAG5	include/ssv6200_reg.h	4745;"	d
+GET_RG_IDACAI_PGAG6	include/ssv6200_reg.h	4743;"	d
+GET_RG_IDACAI_PGAG7	include/ssv6200_reg.h	4741;"	d
+GET_RG_IDACAI_PGAG8	include/ssv6200_reg.h	4739;"	d
+GET_RG_IDACAI_PGAG9	include/ssv6200_reg.h	4737;"	d
+GET_RG_IDACAI_TZ0_COARSE0	smac/hal/ssv6006c/ssv6006C_reg.h	6988;"	d
+GET_RG_IDACAI_TZ0_COARSE1	smac/hal/ssv6006c/ssv6006C_reg.h	6986;"	d
+GET_RG_IDACAI_TZ0_COARSE2	smac/hal/ssv6006c/ssv6006C_reg.h	6984;"	d
+GET_RG_IDACAI_TZ0_COARSE3	smac/hal/ssv6006c/ssv6006C_reg.h	6982;"	d
+GET_RG_IDACAI_TZ0_COARSE4	smac/hal/ssv6006c/ssv6006C_reg.h	6980;"	d
+GET_RG_IDACAI_TZ1_COARSE0	smac/hal/ssv6006c/ssv6006C_reg.h	6998;"	d
+GET_RG_IDACAI_TZ1_COARSE1	smac/hal/ssv6006c/ssv6006C_reg.h	6996;"	d
+GET_RG_IDACAI_TZ1_COARSE2	smac/hal/ssv6006c/ssv6006C_reg.h	6994;"	d
+GET_RG_IDACAI_TZ1_COARSE3	smac/hal/ssv6006c/ssv6006C_reg.h	6992;"	d
+GET_RG_IDACAI_TZ1_COARSE4	smac/hal/ssv6006c/ssv6006C_reg.h	6990;"	d
+GET_RG_IDACAQ_PGAG0	include/ssv6200_reg.h	4756;"	d
+GET_RG_IDACAQ_PGAG1	include/ssv6200_reg.h	4754;"	d
+GET_RG_IDACAQ_PGAG10	include/ssv6200_reg.h	4736;"	d
+GET_RG_IDACAQ_PGAG11	include/ssv6200_reg.h	4734;"	d
+GET_RG_IDACAQ_PGAG12	include/ssv6200_reg.h	4732;"	d
+GET_RG_IDACAQ_PGAG13	include/ssv6200_reg.h	4730;"	d
+GET_RG_IDACAQ_PGAG14	include/ssv6200_reg.h	4727;"	d
+GET_RG_IDACAQ_PGAG15	include/ssv6200_reg.h	4725;"	d
+GET_RG_IDACAQ_PGAG2	include/ssv6200_reg.h	4752;"	d
+GET_RG_IDACAQ_PGAG3	include/ssv6200_reg.h	4750;"	d
+GET_RG_IDACAQ_PGAG4	include/ssv6200_reg.h	4748;"	d
+GET_RG_IDACAQ_PGAG5	include/ssv6200_reg.h	4746;"	d
+GET_RG_IDACAQ_PGAG6	include/ssv6200_reg.h	4744;"	d
+GET_RG_IDACAQ_PGAG7	include/ssv6200_reg.h	4742;"	d
+GET_RG_IDACAQ_PGAG8	include/ssv6200_reg.h	4740;"	d
+GET_RG_IDACAQ_PGAG9	include/ssv6200_reg.h	4738;"	d
+GET_RG_IDACAQ_TZ0_COARSE0	smac/hal/ssv6006c/ssv6006C_reg.h	6989;"	d
+GET_RG_IDACAQ_TZ0_COARSE1	smac/hal/ssv6006c/ssv6006C_reg.h	6987;"	d
+GET_RG_IDACAQ_TZ0_COARSE2	smac/hal/ssv6006c/ssv6006C_reg.h	6985;"	d
+GET_RG_IDACAQ_TZ0_COARSE3	smac/hal/ssv6006c/ssv6006C_reg.h	6983;"	d
+GET_RG_IDACAQ_TZ0_COARSE4	smac/hal/ssv6006c/ssv6006C_reg.h	6981;"	d
+GET_RG_IDACAQ_TZ1_COARSE0	smac/hal/ssv6006c/ssv6006C_reg.h	6999;"	d
+GET_RG_IDACAQ_TZ1_COARSE1	smac/hal/ssv6006c/ssv6006C_reg.h	6997;"	d
+GET_RG_IDACAQ_TZ1_COARSE2	smac/hal/ssv6006c/ssv6006C_reg.h	6995;"	d
+GET_RG_IDACAQ_TZ1_COARSE3	smac/hal/ssv6006c/ssv6006C_reg.h	6993;"	d
+GET_RG_IDACAQ_TZ1_COARSE4	smac/hal/ssv6006c/ssv6006C_reg.h	6991;"	d
+GET_RG_IFS_TIME	include/ssv6200_reg.h	3906;"	d
+GET_RG_IFS_TIME	smac/hal/ssv6006c/ssv6006C_reg.h	8226;"	d
+GET_RG_IFS_TIME_EXT	smac/hal/ssv6006c/ssv6006C_reg.h	8230;"	d
+GET_RG_INI_PHASE	include/ssv6200_reg.h	4327;"	d
+GET_RG_INI_PHASE	smac/hal/ssv6006c/ssv6006C_reg.h	8688;"	d
+GET_RG_INTG_MU	include/ssv6200_reg.h	4368;"	d
+GET_RG_INTG_PH	include/ssv6200_reg.h	4366;"	d
+GET_RG_INTG_PRD	include/ssv6200_reg.h	4367;"	d
+GET_RG_INTRUP_RX_11B_CLEAR	smac/hal/ssv6006c/ssv6006C_reg.h	8495;"	d
+GET_RG_INTRUP_RX_11B_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	8496;"	d
+GET_RG_INTRUP_RX_11B_TRIG	smac/hal/ssv6006c/ssv6006C_reg.h	8497;"	d
+GET_RG_INTRUP_RX_11GN_CLEAR	smac/hal/ssv6006c/ssv6006C_reg.h	8661;"	d
+GET_RG_INTRUP_RX_11GN_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	8662;"	d
+GET_RG_INTRUP_RX_11GN_TRIG	smac/hal/ssv6006c/ssv6006C_reg.h	8663;"	d
+GET_RG_INT_PMU_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	8098;"	d
+GET_RG_IOT_ADC_CLKSEL	smac/hal/ssv6006c/ssv6006C_reg.h	7094;"	d
+GET_RG_IOT_ADC_CLK_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	7101;"	d
+GET_RG_IOT_ADC_CLK_SH_DUTY	smac/hal/ssv6006c/ssv6006C_reg.h	7102;"	d
+GET_RG_IOT_ADC_CLOAD	smac/hal/ssv6006c/ssv6006C_reg.h	7100;"	d
+GET_RG_IOT_ADC_DNLEN	smac/hal/ssv6006c/ssv6006C_reg.h	7095;"	d
+GET_RG_IOT_ADC_EDGE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	7709;"	d
+GET_RG_IOT_ADC_ICMP	smac/hal/ssv6006c/ssv6006C_reg.h	7098;"	d
+GET_RG_IOT_ADC_METAEN	smac/hal/ssv6006c/ssv6006C_reg.h	7096;"	d
+GET_RG_IOT_ADC_SIGN_SWAP	smac/hal/ssv6006c/ssv6006C_reg.h	7708;"	d
+GET_RG_IOT_ADC_TFLAG	smac/hal/ssv6006c/ssv6006C_reg.h	7097;"	d
+GET_RG_IOT_ADC_VCMI	smac/hal/ssv6006c/ssv6006C_reg.h	7099;"	d
+GET_RG_IOT_ADC_VSEN_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	7103;"	d
+GET_RG_IQCAL_ALPHA_ESTM_EN	include/ssv6200_reg.h	4373;"	d
+GET_RG_IQCAL_BP_ACI	include/ssv6200_reg.h	4409;"	d
+GET_RG_IQCAL_DC_EN	include/ssv6200_reg.h	4374;"	d
+GET_RG_IQCAL_IQCOL_EN	include/ssv6200_reg.h	4372;"	d
+GET_RG_IQCAL_MULT_OP0	include/ssv6200_reg.h	4379;"	d
+GET_RG_IQCAL_MULT_OP1	include/ssv6200_reg.h	4380;"	d
+GET_RG_IQCAL_SPRM_EN	include/ssv6200_reg.h	4370;"	d
+GET_RG_IQCAL_SPRM_FREQ	include/ssv6200_reg.h	4371;"	d
+GET_RG_IQCAL_SPRM_SELQ	include/ssv6200_reg.h	4369;"	d
+GET_RG_IQC_FFT_EN	include/ssv6200_reg.h	4023;"	d
+GET_RG_IQ_DC_BYP	include/ssv6200_reg.h	3916;"	d
+GET_RG_IQ_DC_LEAKY_FACTOR	include/ssv6200_reg.h	3917;"	d
+GET_RG_IQ_SWAP	include/ssv6200_reg.h	3862;"	d
+GET_RG_IQ_SWAP	smac/hal/ssv6006c/ssv6006C_reg.h	7589;"	d
+GET_RG_IQ_SWAP_BB	smac/hal/ssv6006c/ssv6006C_reg.h	8185;"	d
+GET_RG_I_INV	include/ssv6200_reg.h	3864;"	d
+GET_RG_I_INV	smac/hal/ssv6006c/ssv6006C_reg.h	7588;"	d
+GET_RG_I_INV_BB	smac/hal/ssv6006c/ssv6006C_reg.h	8187;"	d
+GET_RG_LBK_ANA_PATH	include/ssv6200_reg.h	3866;"	d
+GET_RG_LBK_ANA_PATH	smac/hal/ssv6006c/ssv6006C_reg.h	8189;"	d
+GET_RG_LBK_DIG_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	8190;"	d
+GET_RG_LDO_5G_CP_FC	smac/hal/ssv6006c/ssv6006C_reg.h	7312;"	d
+GET_RG_LDO_5G_CP_FC_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	7311;"	d
+GET_RG_LDO_5G_DIV_FC	smac/hal/ssv6006c/ssv6006C_reg.h	7314;"	d
+GET_RG_LDO_5G_DIV_FC_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	7313;"	d
+GET_RG_LDO_5G_LO_FC	smac/hal/ssv6006c/ssv6006C_reg.h	7316;"	d
+GET_RG_LDO_5G_LO_FC_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	7315;"	d
+GET_RG_LDO_5G_VCO_FC	smac/hal/ssv6006c/ssv6006C_reg.h	7318;"	d
+GET_RG_LDO_5G_VCO_FC_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	7317;"	d
+GET_RG_LDO_5G_VCO_RCF	smac/hal/ssv6006c/ssv6006C_reg.h	7319;"	d
+GET_RG_LDO_CP_FC	smac/hal/ssv6006c/ssv6006C_reg.h	6803;"	d
+GET_RG_LDO_CP_FC_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	6802;"	d
+GET_RG_LDO_DIV_FC	smac/hal/ssv6006c/ssv6006C_reg.h	6805;"	d
+GET_RG_LDO_DIV_FC_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	6804;"	d
+GET_RG_LDO_LEVEL_ABB	include/ssv6200_reg.h	4520;"	d
+GET_RG_LDO_LEVEL_AFE	include/ssv6200_reg.h	4521;"	d
+GET_RG_LDO_LEVEL_AFE	smac/hal/ssv6006c/ssv6006C_reg.h	6534;"	d
+GET_RG_LDO_LEVEL_EFUSE	smac/hal/ssv6006c/ssv6006C_reg.h	8073;"	d
+GET_RG_LDO_LEVEL_RX_FE	include/ssv6200_reg.h	4519;"	d
+GET_RG_LDO_LEVEL_RX_FE	smac/hal/ssv6006c/ssv6006C_reg.h	6532;"	d
+GET_RG_LDO_LO_FC	smac/hal/ssv6006c/ssv6006C_reg.h	6807;"	d
+GET_RG_LDO_LO_FC_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	6806;"	d
+GET_RG_LDO_VCO_FC	smac/hal/ssv6006c/ssv6006C_reg.h	6809;"	d
+GET_RG_LDO_VCO_FC_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	6808;"	d
+GET_RG_LDO_VCO_RCF	smac/hal/ssv6006c/ssv6006C_reg.h	6810;"	d
+GET_RG_LENGTH	include/ssv6200_reg.h	3889;"	d
+GET_RG_LENGTH	smac/hal/ssv6006c/ssv6006C_reg.h	8208;"	d
+GET_RG_LG_PGA_SAT_PGA_GAIN	include/ssv6200_reg.h	3936;"	d
+GET_RG_LG_PGA_SAT_PGA_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	8255;"	d
+GET_RG_LG_PGA_UND_PGA_GAIN	include/ssv6200_reg.h	3935;"	d
+GET_RG_LG_PGA_UND_PGA_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	8254;"	d
+GET_RG_LG_RF_SAT_PGA_GAIN	include/ssv6200_reg.h	3937;"	d
+GET_RG_LG_RF_SAT_PGA_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	8256;"	d
+GET_RG_LOAD_RFTABLE_RDY	smac/hal/ssv6006c/ssv6006C_reg.h	8065;"	d
+GET_RG_LO_UP_CH	smac/hal/ssv6006c/ssv6006C_reg.h	7577;"	d
+GET_RG_LPBK_RX_EN	include/ssv6200_reg.h	3018;"	d
+GET_RG_LPBK_RX_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3850;"	d
+GET_RG_LPF4_00	include/ssv6200_reg.h	4078;"	d
+GET_RG_LPF4_01	include/ssv6200_reg.h	4079;"	d
+GET_RG_LPF4_02	include/ssv6200_reg.h	4080;"	d
+GET_RG_LPF4_03	include/ssv6200_reg.h	4081;"	d
+GET_RG_LPF4_04	include/ssv6200_reg.h	4082;"	d
+GET_RG_LPF4_05	include/ssv6200_reg.h	4083;"	d
+GET_RG_LPF4_06	include/ssv6200_reg.h	4084;"	d
+GET_RG_LPF4_07	include/ssv6200_reg.h	4085;"	d
+GET_RG_LPF4_08	include/ssv6200_reg.h	4086;"	d
+GET_RG_LPF4_09	include/ssv6200_reg.h	4087;"	d
+GET_RG_LPF4_10	include/ssv6200_reg.h	4088;"	d
+GET_RG_LPF4_11	include/ssv6200_reg.h	4089;"	d
+GET_RG_LPF4_12	include/ssv6200_reg.h	4090;"	d
+GET_RG_LPF4_13	include/ssv6200_reg.h	4091;"	d
+GET_RG_LPF4_14	include/ssv6200_reg.h	4092;"	d
+GET_RG_LPF4_15	include/ssv6200_reg.h	4093;"	d
+GET_RG_LPF4_16	include/ssv6200_reg.h	4094;"	d
+GET_RG_LPF4_17	include/ssv6200_reg.h	4095;"	d
+GET_RG_LPF4_18	include/ssv6200_reg.h	4096;"	d
+GET_RG_LPF4_19	include/ssv6200_reg.h	4097;"	d
+GET_RG_LPF4_20	include/ssv6200_reg.h	4098;"	d
+GET_RG_LPF4_21	include/ssv6200_reg.h	4099;"	d
+GET_RG_LPF4_22	include/ssv6200_reg.h	4100;"	d
+GET_RG_LPF4_23	include/ssv6200_reg.h	4101;"	d
+GET_RG_LPF4_24	include/ssv6200_reg.h	4102;"	d
+GET_RG_LPF4_25	include/ssv6200_reg.h	4103;"	d
+GET_RG_LPF4_26	include/ssv6200_reg.h	4104;"	d
+GET_RG_LPF4_27	include/ssv6200_reg.h	4105;"	d
+GET_RG_LPF4_28	include/ssv6200_reg.h	4106;"	d
+GET_RG_LPF4_29	include/ssv6200_reg.h	4107;"	d
+GET_RG_LPF4_30	include/ssv6200_reg.h	4108;"	d
+GET_RG_LPF4_31	include/ssv6200_reg.h	4109;"	d
+GET_RG_LPF4_32	include/ssv6200_reg.h	4110;"	d
+GET_RG_LPF4_33	include/ssv6200_reg.h	4111;"	d
+GET_RG_LPF4_34	include/ssv6200_reg.h	4112;"	d
+GET_RG_LPF4_35	include/ssv6200_reg.h	4113;"	d
+GET_RG_LPF4_36	include/ssv6200_reg.h	4114;"	d
+GET_RG_LPF4_37	include/ssv6200_reg.h	4115;"	d
+GET_RG_LPF4_38	include/ssv6200_reg.h	4116;"	d
+GET_RG_LPF4_39	include/ssv6200_reg.h	4117;"	d
+GET_RG_LPF4_40	include/ssv6200_reg.h	4118;"	d
+GET_RG_L_LENGTH	include/ssv6200_reg.h	3895;"	d
+GET_RG_L_LENGTH	smac/hal/ssv6006c/ssv6006C_reg.h	8214;"	d
+GET_RG_L_LENGTH_MAX	include/ssv6200_reg.h	4278;"	d
+GET_RG_L_LENGTH_MAX	smac/hal/ssv6006c/ssv6006C_reg.h	8656;"	d
+GET_RG_L_RATE	include/ssv6200_reg.h	3896;"	d
+GET_RG_L_RATE	smac/hal/ssv6006c/ssv6006C_reg.h	8215;"	d
+GET_RG_MAC_DES_SPACE	include/ssv6200_reg.h	4280;"	d
+GET_RG_MAC_LPBK	include/ssv6200_reg.h	3015;"	d
+GET_RG_MAC_LPBK	smac/hal/ssv6006c/ssv6006C_reg.h	3847;"	d
+GET_RG_MAC_M2M	include/ssv6200_reg.h	3016;"	d
+GET_RG_MAC_M2M	smac/hal/ssv6006c/ssv6006C_reg.h	3848;"	d
+GET_RG_MAC_PKT_ADDR1_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	8360;"	d
+GET_RG_MAC_PKT_ADDR1_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	8361;"	d
+GET_RG_MAC_PKT_ADDR2_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	8362;"	d
+GET_RG_MAC_PKT_ADDR2_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	8363;"	d
+GET_RG_MAC_PKT_ADDR2_ON	smac/hal/ssv6006c/ssv6006C_reg.h	8355;"	d
+GET_RG_MAC_PKT_ADDR3_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	8364;"	d
+GET_RG_MAC_PKT_ADDR3_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	8365;"	d
+GET_RG_MAC_PKT_ADDR3_ON	smac/hal/ssv6006c/ssv6006C_reg.h	8354;"	d
+GET_RG_MAC_PKT_ADDR4_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	8367;"	d
+GET_RG_MAC_PKT_ADDR4_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	8368;"	d
+GET_RG_MAC_PKT_ADDR4_ON	smac/hal/ssv6006c/ssv6006C_reg.h	8352;"	d
+GET_RG_MAC_PKT_AGGREGATE	smac/hal/ssv6006c/ssv6006C_reg.h	8351;"	d
+GET_RG_MAC_PKT_AGGREGATE_NUM	smac/hal/ssv6006c/ssv6006C_reg.h	8356;"	d
+GET_RG_MAC_PKT_DUR	smac/hal/ssv6006c/ssv6006C_reg.h	8358;"	d
+GET_RG_MAC_PKT_FC	smac/hal/ssv6006c/ssv6006C_reg.h	8359;"	d
+GET_RG_MAC_PKT_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	8350;"	d
+GET_RG_MAC_PKT_PLD_LENGTH	smac/hal/ssv6006c/ssv6006C_reg.h	8357;"	d
+GET_RG_MAC_PKT_SEQ	smac/hal/ssv6006c/ssv6006C_reg.h	8366;"	d
+GET_RG_MAC_PKT_SEQ_ON	smac/hal/ssv6006c/ssv6006C_reg.h	8353;"	d
+GET_RG_MA_DPTH	include/ssv6200_reg.h	4365;"	d
+GET_RG_MA_PGA_HIGH_TH_CNT_LMT	include/ssv6200_reg.h	3946;"	d
+GET_RG_MA_PGA_HIGH_TH_CNT_LMT	smac/hal/ssv6006c/ssv6006C_reg.h	8263;"	d
+GET_RG_MA_PGA_LOW_TH_CNT_LMT	include/ssv6200_reg.h	3943;"	d
+GET_RG_MA_PGA_LOW_TH_CNT_LMT	smac/hal/ssv6006c/ssv6006C_reg.h	8262;"	d
+GET_RG_MBRUN_16	include/ssv6200_reg.h	4056;"	d
+GET_RG_MBRUN_64	include/ssv6200_reg.h	4294;"	d
+GET_RG_MBRUN_80	include/ssv6200_reg.h	4287;"	d
+GET_RG_MG_PGA_JB_TH	include/ssv6200_reg.h	3942;"	d
+GET_RG_MG_PGA_JB_TH	smac/hal/ssv6006c/ssv6006C_reg.h	8261;"	d
+GET_RG_MG_RF_SAT_PGANOREF_PGA_GAIN	include/ssv6200_reg.h	3938;"	d
+GET_RG_MG_RF_SAT_PGANOREF_PGA_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	8257;"	d
+GET_RG_MODE	include/ssv6200_reg.h	4482;"	d
+GET_RG_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	6465;"	d
+GET_RG_MODE_BY_HS_3WIRE	smac/hal/ssv6006c/ssv6006C_reg.h	7689;"	d
+GET_RG_MODE_BY_HWPIN	smac/hal/ssv6006c/ssv6006C_reg.h	7691;"	d
+GET_RG_MODE_BY_PHY	smac/hal/ssv6006c/ssv6006C_reg.h	7690;"	d
+GET_RG_MODE_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	6459;"	d
+GET_RG_MODE_REG_IN_16	include/ssv6200_reg.h	4054;"	d
+GET_RG_MODE_REG_IN_64	include/ssv6200_reg.h	4292;"	d
+GET_RG_MODE_REG_IN_80	include/ssv6200_reg.h	4285;"	d
+GET_RG_MODE_REG_SI_16	include/ssv6200_reg.h	4058;"	d
+GET_RG_MODE_REG_SI_64	include/ssv6200_reg.h	4296;"	d
+GET_RG_MODE_REG_SI_80	include/ssv6200_reg.h	4289;"	d
+GET_RG_MRX_EN_CNT_RST_N	include/ssv6200_reg.h	4027;"	d
+GET_RG_MRX_EN_CNT_RST_N	smac/hal/ssv6006c/ssv6006C_reg.h	8309;"	d
+GET_RG_MRX_LEN_CNT_EN_0	include/ssv6200_reg.h	4046;"	d
+GET_RG_MRX_LEN_CNT_EN_1	include/ssv6200_reg.h	4049;"	d
+GET_RG_MRX_LEN_LOWER_TH_0	include/ssv6200_reg.h	4044;"	d
+GET_RG_MRX_LEN_LOWER_TH_0	smac/hal/ssv6006c/ssv6006C_reg.h	8328;"	d
+GET_RG_MRX_LEN_LOWER_TH_1	include/ssv6200_reg.h	4047;"	d
+GET_RG_MRX_LEN_LOWER_TH_1	smac/hal/ssv6006c/ssv6006C_reg.h	8330;"	d
+GET_RG_MRX_LEN_UPPER_TH_0	include/ssv6200_reg.h	4045;"	d
+GET_RG_MRX_LEN_UPPER_TH_0	smac/hal/ssv6006c/ssv6006C_reg.h	8329;"	d
+GET_RG_MRX_LEN_UPPER_TH_1	include/ssv6200_reg.h	4048;"	d
+GET_RG_MRX_LEN_UPPER_TH_1	smac/hal/ssv6006c/ssv6006C_reg.h	8331;"	d
+GET_RG_MRX_TYPE	smac/hal/ssv6006c/ssv6006C_reg.h	8336;"	d
+GET_RG_MRX_TYPE_0	include/ssv6200_reg.h	4065;"	d
+GET_RG_MRX_TYPE_1	include/ssv6200_reg.h	4064;"	d
+GET_RG_MRX_TYPE_CNT_LMT	smac/hal/ssv6006c/ssv6006C_reg.h	8337;"	d
+GET_RG_MTX_LEN_CNT_EN_0	include/ssv6200_reg.h	4040;"	d
+GET_RG_MTX_LEN_CNT_EN_1	include/ssv6200_reg.h	4043;"	d
+GET_RG_MTX_LEN_LOWER_TH_0	include/ssv6200_reg.h	4038;"	d
+GET_RG_MTX_LEN_LOWER_TH_0	smac/hal/ssv6006c/ssv6006C_reg.h	8324;"	d
+GET_RG_MTX_LEN_LOWER_TH_1	include/ssv6200_reg.h	4041;"	d
+GET_RG_MTX_LEN_LOWER_TH_1	smac/hal/ssv6006c/ssv6006C_reg.h	8326;"	d
+GET_RG_MTX_LEN_UPPER_TH_0	include/ssv6200_reg.h	4039;"	d
+GET_RG_MTX_LEN_UPPER_TH_0	smac/hal/ssv6006c/ssv6006C_reg.h	8325;"	d
+GET_RG_MTX_LEN_UPPER_TH_1	include/ssv6200_reg.h	4042;"	d
+GET_RG_MTX_LEN_UPPER_TH_1	smac/hal/ssv6006c/ssv6006C_reg.h	8327;"	d
+GET_RG_MTX_TYPE	smac/hal/ssv6006c/ssv6006C_reg.h	8338;"	d
+GET_RG_MTX_TYPE_0	include/ssv6200_reg.h	4067;"	d
+GET_RG_MTX_TYPE_1	include/ssv6200_reg.h	4066;"	d
+GET_RG_MTX_TYPE_CNT_LMT	smac/hal/ssv6006c/ssv6006C_reg.h	8339;"	d
+GET_RG_NEW_PILOT_AVG	smac/hal/ssv6006c/ssv6006C_reg.h	8653;"	d
+GET_RG_NEW_SB	smac/hal/ssv6006c/ssv6006C_reg.h	8654;"	d
+GET_RG_NFRAC_DELTA	smac/hal/ssv6006c/ssv6006C_reg.h	7575;"	d
+GET_RG_NORMSQUARE_LOW_SNR_4	include/ssv6200_reg.h	4236;"	d
+GET_RG_NORMSQUARE_LOW_SNR_4	smac/hal/ssv6006c/ssv6006C_reg.h	8565;"	d
+GET_RG_NORMSQUARE_LOW_SNR_5	include/ssv6200_reg.h	4235;"	d
+GET_RG_NORMSQUARE_LOW_SNR_5	smac/hal/ssv6006c/ssv6006C_reg.h	8564;"	d
+GET_RG_NORMSQUARE_LOW_SNR_6	include/ssv6200_reg.h	4234;"	d
+GET_RG_NORMSQUARE_LOW_SNR_6	smac/hal/ssv6006c/ssv6006C_reg.h	8563;"	d
+GET_RG_NORMSQUARE_LOW_SNR_7	include/ssv6200_reg.h	4233;"	d
+GET_RG_NORMSQUARE_LOW_SNR_7	smac/hal/ssv6006c/ssv6006C_reg.h	8562;"	d
+GET_RG_NORMSQUARE_LOW_SNR_8	include/ssv6200_reg.h	4237;"	d
+GET_RG_NORMSQUARE_LOW_SNR_8	smac/hal/ssv6006c/ssv6006C_reg.h	8566;"	d
+GET_RG_NORMSQUARE_SNR_0	include/ssv6200_reg.h	4241;"	d
+GET_RG_NORMSQUARE_SNR_0	smac/hal/ssv6006c/ssv6006C_reg.h	8570;"	d
+GET_RG_NORMSQUARE_SNR_1	include/ssv6200_reg.h	4240;"	d
+GET_RG_NORMSQUARE_SNR_1	smac/hal/ssv6006c/ssv6006C_reg.h	8569;"	d
+GET_RG_NORMSQUARE_SNR_2	include/ssv6200_reg.h	4239;"	d
+GET_RG_NORMSQUARE_SNR_2	smac/hal/ssv6006c/ssv6006C_reg.h	8568;"	d
+GET_RG_NORMSQUARE_SNR_3	include/ssv6200_reg.h	4238;"	d
+GET_RG_NORMSQUARE_SNR_3	smac/hal/ssv6006c/ssv6006C_reg.h	8567;"	d
+GET_RG_NORMSQUARE_SNR_4	include/ssv6200_reg.h	4245;"	d
+GET_RG_NORMSQUARE_SNR_4	smac/hal/ssv6006c/ssv6006C_reg.h	8574;"	d
+GET_RG_NORMSQUARE_SNR_5	include/ssv6200_reg.h	4244;"	d
+GET_RG_NORMSQUARE_SNR_5	smac/hal/ssv6006c/ssv6006C_reg.h	8573;"	d
+GET_RG_NORMSQUARE_SNR_6	include/ssv6200_reg.h	4243;"	d
+GET_RG_NORMSQUARE_SNR_6	smac/hal/ssv6006c/ssv6006C_reg.h	8572;"	d
+GET_RG_NORMSQUARE_SNR_7	include/ssv6200_reg.h	4242;"	d
+GET_RG_NORMSQUARE_SNR_7	smac/hal/ssv6006c/ssv6006C_reg.h	8571;"	d
+GET_RG_NORMSQUARE_SNR_8	include/ssv6200_reg.h	4246;"	d
+GET_RG_NORMSQUARE_SNR_8	smac/hal/ssv6006c/ssv6006C_reg.h	8575;"	d
+GET_RG_NO_SOUND	include/ssv6200_reg.h	3899;"	d
+GET_RG_NO_SOUND	smac/hal/ssv6006c/ssv6006C_reg.h	8218;"	d
+GET_RG_N_ESS	include/ssv6200_reg.h	3903;"	d
+GET_RG_N_ESS	smac/hal/ssv6006c/ssv6006C_reg.h	8222;"	d
+GET_RG_PABIAS_CTRL	include/ssv6200_reg.h	4565;"	d
+GET_RG_PACASCODE_CTRL	include/ssv6200_reg.h	4577;"	d
+GET_RG_PACELL_EN	include/ssv6200_reg.h	4564;"	d
+GET_RG_PACKET_STAT_EN	include/ssv6200_reg.h	4202;"	d
+GET_RG_PACKET_STAT_EN_11B	include/ssv6200_reg.h	4193;"	d
+GET_RG_PACKET_STAT_EN_11B_RX	smac/hal/ssv6006c/ssv6006C_reg.h	8514;"	d
+GET_RG_PACKET_STAT_EN_11GN	include/ssv6200_reg.h	4322;"	d
+GET_RG_PACKET_STAT_EN_11GN_RX	smac/hal/ssv6006c/ssv6006C_reg.h	8683;"	d
+GET_RG_PARALLEL_DR_16	include/ssv6200_reg.h	4055;"	d
+GET_RG_PARALLEL_DR_64	include/ssv6200_reg.h	4293;"	d
+GET_RG_PARALLEL_DR_80	include/ssv6200_reg.h	4286;"	d
+GET_RG_PA_FALL_TIME	include/ssv6200_reg.h	4032;"	d
+GET_RG_PA_RISE_TIME	include/ssv6200_reg.h	4028;"	d
+GET_RG_PDM_EDGE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	7711;"	d
+GET_RG_PDM_HIGH_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	7714;"	d
+GET_RG_PDM_LOW_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	7713;"	d
+GET_RG_PEAK_IDX_CNT_SEL	include/ssv6200_reg.h	4134;"	d
+GET_RG_PEAK_IDX_CNT_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	8452;"	d
+GET_RG_PERIOD_MAX	smac/hal/ssv6006c/ssv6006C_reg.h	8701;"	d
+GET_RG_PERIOD_MIN	smac/hal/ssv6006c/ssv6006C_reg.h	8700;"	d
+GET_RG_PGAG	include/ssv6200_reg.h	4481;"	d
+GET_RG_PGAG	smac/hal/ssv6006c/ssv6006C_reg.h	6468;"	d
+GET_RG_PGAGC_OW	include/ssv6200_reg.h	3926;"	d
+GET_RG_PGAGC_OW	smac/hal/ssv6006c/ssv6006C_reg.h	8245;"	d
+GET_RG_PGAGC_SET	include/ssv6200_reg.h	3925;"	d
+GET_RG_PGAGC_SET	smac/hal/ssv6006c/ssv6006C_reg.h	8244;"	d
+GET_RG_PGAG_DPDCAL	smac/hal/ssv6006c/ssv6006C_reg.h	7092;"	d
+GET_RG_PGAG_RCCAL	smac/hal/ssv6006c/ssv6006C_reg.h	7085;"	d
+GET_RG_PGAG_RXIQCAL	smac/hal/ssv6006c/ssv6006C_reg.h	7089;"	d
+GET_RG_PGAG_TXCAL	smac/hal/ssv6006c/ssv6006C_reg.h	7086;"	d
+GET_RG_PGA_REFDB_SAT	include/ssv6200_reg.h	3921;"	d
+GET_RG_PGA_REFDB_SAT_B	smac/hal/ssv6006c/ssv6006C_reg.h	8236;"	d
+GET_RG_PGA_REFDB_SAT_GN	smac/hal/ssv6006c/ssv6006C_reg.h	8240;"	d
+GET_RG_PGA_REFDB_TOP	include/ssv6200_reg.h	3922;"	d
+GET_RG_PGA_REFDB_TOP_B	smac/hal/ssv6006c/ssv6006C_reg.h	8237;"	d
+GET_RG_PGA_REFDB_TOP_GN	smac/hal/ssv6006c/ssv6006C_reg.h	8241;"	d
+GET_RG_PGA_REF_UND	include/ssv6200_reg.h	3923;"	d
+GET_RG_PGA_REF_UND_B	smac/hal/ssv6006c/ssv6006C_reg.h	8238;"	d
+GET_RG_PGA_REF_UND_GN	smac/hal/ssv6006c/ssv6006C_reg.h	8242;"	d
+GET_RG_PHASE_17P5M	smac/hal/ssv6006c/ssv6006C_reg.h	7651;"	d
+GET_RG_PHASE_1M	smac/hal/ssv6006c/ssv6006C_reg.h	7654;"	d
+GET_RG_PHASE_2P5M	smac/hal/ssv6006c/ssv6006C_reg.h	7652;"	d
+GET_RG_PHASE_35M	smac/hal/ssv6006c/ssv6006C_reg.h	7655;"	d
+GET_RG_PHASE_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	7636;"	d
+GET_RG_PHASE_RND_EN	smac/hal/ssv6006c/ssv6006C_reg.h	7674;"	d
+GET_RG_PHASE_RXIQ_1M	smac/hal/ssv6006c/ssv6006C_reg.h	7653;"	d
+GET_RG_PHASE_STEP_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	7635;"	d
+GET_RG_PHEST_EN	include/ssv6200_reg.h	4376;"	d
+GET_RG_PHEST_STBY	include/ssv6200_reg.h	4375;"	d
+GET_RG_PHY11BGN_MD_EN	include/ssv6200_reg.h	3881;"	d
+GET_RG_PHY11BGN_MD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8203;"	d
+GET_RG_PHY11B_MD_EN	include/ssv6200_reg.h	3878;"	d
+GET_RG_PHY11B_MD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8200;"	d
+GET_RG_PHY11GN_MD_EN	include/ssv6200_reg.h	3877;"	d
+GET_RG_PHY11GN_MD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8199;"	d
+GET_RG_PHYRXFIFO_MD_EN	include/ssv6200_reg.h	3879;"	d
+GET_RG_PHYRXFIFO_MD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8201;"	d
+GET_RG_PHYRX_MD_EN	include/ssv6200_reg.h	3875;"	d
+GET_RG_PHYRX_MD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8197;"	d
+GET_RG_PHYTXFIFO_MD_EN	include/ssv6200_reg.h	3880;"	d
+GET_RG_PHYTXFIFO_MD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8202;"	d
+GET_RG_PHYTX_MD_EN	include/ssv6200_reg.h	3876;"	d
+GET_RG_PHYTX_MD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8198;"	d
+GET_RG_PHY_IQ_TRIG_SEL	include/ssv6200_reg.h	3886;"	d
+GET_RG_PHY_IQ_TRIG_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	8206;"	d
+GET_RG_PHY_LPBK	include/ssv6200_reg.h	3017;"	d
+GET_RG_PHY_LPBK	smac/hal/ssv6006c/ssv6006C_reg.h	3849;"	d
+GET_RG_PHY_MD_EN	include/ssv6200_reg.h	3874;"	d
+GET_RG_PHY_MD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8196;"	d
+GET_RG_PHY_RST_N	smac/hal/ssv6006c/ssv6006C_reg.h	8112;"	d
+GET_RG_PILOT_BNDRY_SHIFT	include/ssv6200_reg.h	4267;"	d
+GET_RG_PKT_MODE	include/ssv6200_reg.h	3890;"	d
+GET_RG_PKT_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	8209;"	d
+GET_RG_PMDLBK	include/ssv6200_reg.h	3858;"	d
+GET_RG_PMDLBK	smac/hal/ssv6006c/ssv6006C_reg.h	8181;"	d
+GET_RG_PMU_ENTER_SLEEP_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	8096;"	d
+GET_RG_POST_CLK_EN	include/ssv6200_reg.h	4334;"	d
+GET_RG_POST_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8693;"	d
+GET_RG_POS_DES_11B_L_EXT	include/ssv6200_reg.h	4127;"	d
+GET_RG_POS_DES_11GN_L_EXT	include/ssv6200_reg.h	4207;"	d
+GET_RG_POS_DES_L_EXT_11B_RX	smac/hal/ssv6006c/ssv6006C_reg.h	8445;"	d
+GET_RG_POS_DES_L_EXT_11GN_RX	smac/hal/ssv6006c/ssv6006C_reg.h	8541;"	d
+GET_RG_POW16_CNT_TH	include/ssv6200_reg.h	4254;"	d
+GET_RG_POW16_CNT_TH	smac/hal/ssv6006c/ssv6006C_reg.h	8619;"	d
+GET_RG_POW16_SHORT_CNT_LMT	include/ssv6200_reg.h	4255;"	d
+GET_RG_POW16_SHORT_CNT_LMT	smac/hal/ssv6006c/ssv6006C_reg.h	8620;"	d
+GET_RG_POW16_TH_L	include/ssv6200_reg.h	4256;"	d
+GET_RG_POW16_TH_L	smac/hal/ssv6006c/ssv6006C_reg.h	8621;"	d
+GET_RG_PRE_DC_AUTO	smac/hal/ssv6006c/ssv6006C_reg.h	7672;"	d
+GET_RG_PRE_DC_POLA_INV	smac/hal/ssv6006c/ssv6006C_reg.h	7670;"	d
+GET_RG_PRE_DES_11B_DLY	include/ssv6200_reg.h	4128;"	d
+GET_RG_PRE_DES_11GN_DLY	include/ssv6200_reg.h	4208;"	d
+GET_RG_PRE_DES_DLY_11B_RX	smac/hal/ssv6006c/ssv6006C_reg.h	8446;"	d
+GET_RG_PRE_DES_DLY_11GN_RX	smac/hal/ssv6006c/ssv6006C_reg.h	8542;"	d
+GET_RG_PRIMARY_CH_SIDE	smac/hal/ssv6006c/ssv6006C_reg.h	8192;"	d
+GET_RG_PRM	include/ssv6200_reg.h	3892;"	d
+GET_RG_PRM	smac/hal/ssv6006c/ssv6006C_reg.h	8211;"	d
+GET_RG_PROC_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	7669;"	d
+GET_RG_PSDU_TIME_OFFSET_11B	smac/hal/ssv6006c/ssv6006C_reg.h	8493;"	d
+GET_RG_PSDU_TIME_OFFSET_GF	smac/hal/ssv6006c/ssv6006C_reg.h	8658;"	d
+GET_RG_PSDU_TIME_OFFSET_LEGACY	smac/hal/ssv6006c/ssv6006C_reg.h	8660;"	d
+GET_RG_PSDU_TIME_OFFSET_MF	smac/hal/ssv6006c/ssv6006C_reg.h	8659;"	d
+GET_RG_PULSE_NUMBER	smac/hal/ssv6006c/ssv6006C_reg.h	8703;"	d
+GET_RG_PWRON_DLY_TH_11B	include/ssv6200_reg.h	4174;"	d
+GET_RG_PWRON_DLY_TH_11B_RX	smac/hal/ssv6006c/ssv6006C_reg.h	8488;"	d
+GET_RG_PWRON_DLY_TH_11GN	include/ssv6200_reg.h	4252;"	d
+GET_RG_PWRON_DLY_TH_11GN_RX	smac/hal/ssv6006c/ssv6006C_reg.h	8614;"	d
+GET_RG_PWR_BIT_CNT_TH	smac/hal/ssv6006c/ssv6006C_reg.h	8492;"	d
+GET_RG_PWR_CNT_TH	smac/hal/ssv6006c/ssv6006C_reg.h	8491;"	d
+GET_RG_PWR_TH	smac/hal/ssv6006c/ssv6006C_reg.h	8490;"	d
+GET_RG_PW_CHIRP_MAX	smac/hal/ssv6006c/ssv6006C_reg.h	8726;"	d
+GET_RG_PW_CHIRP_MIN	smac/hal/ssv6006c/ssv6006C_reg.h	8725;"	d
+GET_RG_PW_MAX	smac/hal/ssv6006c/ssv6006C_reg.h	8699;"	d
+GET_RG_PW_MIN	smac/hal/ssv6006c/ssv6006C_reg.h	8698;"	d
+GET_RG_Q_INV	include/ssv6200_reg.h	3863;"	d
+GET_RG_Q_INV	smac/hal/ssv6006c/ssv6006C_reg.h	7587;"	d
+GET_RG_Q_INV_BB	smac/hal/ssv6006c/ssv6006C_reg.h	8186;"	d
+GET_RG_RADAR_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8706;"	d
+GET_RG_RAM_00	smac/hal/ssv6006c/ssv6006C_reg.h	8165;"	d
+GET_RG_RAM_01	smac/hal/ssv6006c/ssv6006C_reg.h	8166;"	d
+GET_RG_RAM_02	smac/hal/ssv6006c/ssv6006C_reg.h	8167;"	d
+GET_RG_RAM_03	smac/hal/ssv6006c/ssv6006C_reg.h	8168;"	d
+GET_RG_RAM_04	smac/hal/ssv6006c/ssv6006C_reg.h	8169;"	d
+GET_RG_RAM_05	smac/hal/ssv6006c/ssv6006C_reg.h	8170;"	d
+GET_RG_RAM_06	smac/hal/ssv6006c/ssv6006C_reg.h	8171;"	d
+GET_RG_RAM_07	smac/hal/ssv6006c/ssv6006C_reg.h	8172;"	d
+GET_RG_RAM_08	smac/hal/ssv6006c/ssv6006C_reg.h	8173;"	d
+GET_RG_RAM_09	smac/hal/ssv6006c/ssv6006C_reg.h	8174;"	d
+GET_RG_RAM_10	smac/hal/ssv6006c/ssv6006C_reg.h	8175;"	d
+GET_RG_RAM_11	smac/hal/ssv6006c/ssv6006C_reg.h	8176;"	d
+GET_RG_RAM_12	smac/hal/ssv6006c/ssv6006C_reg.h	8177;"	d
+GET_RG_RAM_13	smac/hal/ssv6006c/ssv6006C_reg.h	8178;"	d
+GET_RG_RAM_14	smac/hal/ssv6006c/ssv6006C_reg.h	8179;"	d
+GET_RG_RAM_15	smac/hal/ssv6006c/ssv6006C_reg.h	8180;"	d
+GET_RG_RATE	include/ssv6200_reg.h	3894;"	d
+GET_RG_RATE	smac/hal/ssv6006c/ssv6006C_reg.h	8213;"	d
+GET_RG_RATE_MCS_STAT	smac/hal/ssv6006c/ssv6006C_reg.h	8682;"	d
+GET_RG_RATE_STAT	smac/hal/ssv6006c/ssv6006C_reg.h	8513;"	d
+GET_RG_RCAL_CODE_CWD	include/ssv6200_reg.h	4761;"	d
+GET_RG_RCAL_CODE_CWR	include/ssv6200_reg.h	4760;"	d
+GET_RG_RCAL_SPD	include/ssv6200_reg.h	4758;"	d
+GET_RG_RCAL_TMR	include/ssv6200_reg.h	4759;"	d
+GET_RG_RCCAL_DATA_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	7675;"	d
+GET_RG_RCCAL_POLAR_INV	smac/hal/ssv6006c/ssv6006C_reg.h	7662;"	d
+GET_RG_RDYACK_SEL	include/ssv6200_reg.h	3859;"	d
+GET_RG_REBOOT	include/ssv6200_reg.h	1290;"	d
+GET_RG_REBOOT	smac/hal/ssv6006c/ssv6006C_reg.h	2369;"	d
+GET_RG_RESERVED_11B_RX	smac/hal/ssv6006c/ssv6006C_reg.h	8494;"	d
+GET_RG_RESERVED_11B_TX	smac/hal/ssv6006c/ssv6006C_reg.h	8444;"	d
+GET_RG_RESERVED_11GN_RX	smac/hal/ssv6006c/ssv6006C_reg.h	8543;"	d
+GET_RG_RESERVED_11GN_TX	smac/hal/ssv6006c/ssv6006C_reg.h	8540;"	d
+GET_RG_RESERVED_CMM	smac/hal/ssv6006c/ssv6006C_reg.h	8438;"	d
+GET_RG_RESERVED_DPD	smac/hal/ssv6006c/ssv6006C_reg.h	8038;"	d
+GET_RG_RFG	include/ssv6200_reg.h	4480;"	d
+GET_RG_RFG	smac/hal/ssv6006c/ssv6006C_reg.h	6467;"	d
+GET_RG_RFGC_OW	include/ssv6200_reg.h	3928;"	d
+GET_RG_RFGC_OW	smac/hal/ssv6006c/ssv6006C_reg.h	8247;"	d
+GET_RG_RFGC_SET	include/ssv6200_reg.h	3927;"	d
+GET_RG_RFGC_SET	smac/hal/ssv6006c/ssv6006C_reg.h	8246;"	d
+GET_RG_RFG_DPDCAL	smac/hal/ssv6006c/ssv6006C_reg.h	7091;"	d
+GET_RG_RFG_RXIQCAL	smac/hal/ssv6006c/ssv6006C_reg.h	7088;"	d
+GET_RG_RFTX_FALL_TIME	include/ssv6200_reg.h	4033;"	d
+GET_RG_RFTX_RISE_TIME	include/ssv6200_reg.h	4029;"	d
+GET_RG_RF_5G_BAND	smac/hal/ssv6006c/ssv6006C_reg.h	8191;"	d
+GET_RG_RF_BB_CLK_SEL	include/ssv6200_reg.h	3873;"	d
+GET_RG_RF_D_REG	include/ssv6200_reg.h	4793;"	d
+GET_RG_RF_PWR_BARKER_CCK	smac/hal/ssv6006c/ssv6006C_reg.h	8383;"	d
+GET_RG_RF_PWR_HT20_16QAM	smac/hal/ssv6006c/ssv6006C_reg.h	8390;"	d
+GET_RG_RF_PWR_HT20_64QAM	smac/hal/ssv6006c/ssv6006C_reg.h	8389;"	d
+GET_RG_RF_PWR_HT20_BPSK	smac/hal/ssv6006c/ssv6006C_reg.h	8392;"	d
+GET_RG_RF_PWR_HT20_QPSK	smac/hal/ssv6006c/ssv6006C_reg.h	8391;"	d
+GET_RG_RF_PWR_HT40_16QAM	smac/hal/ssv6006c/ssv6006C_reg.h	8394;"	d
+GET_RG_RF_PWR_HT40_64QAM	smac/hal/ssv6006c/ssv6006C_reg.h	8393;"	d
+GET_RG_RF_PWR_HT40_BPSK	smac/hal/ssv6006c/ssv6006C_reg.h	8396;"	d
+GET_RG_RF_PWR_HT40_QPSK	smac/hal/ssv6006c/ssv6006C_reg.h	8395;"	d
+GET_RG_RF_PWR_LEGACY_16QAM	smac/hal/ssv6006c/ssv6006C_reg.h	8386;"	d
+GET_RG_RF_PWR_LEGACY_64QAM	smac/hal/ssv6006c/ssv6006C_reg.h	8385;"	d
+GET_RG_RF_PWR_LEGACY_BPSK	smac/hal/ssv6006c/ssv6006C_reg.h	8388;"	d
+GET_RG_RF_PWR_LEGACY_QPSK	smac/hal/ssv6006c/ssv6006C_reg.h	8387;"	d
+GET_RG_RF_PWR_MAN_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8384;"	d
+GET_RG_RF_REF_SAT	include/ssv6200_reg.h	3924;"	d
+GET_RG_RF_REF_SAT_B	smac/hal/ssv6006c/ssv6006C_reg.h	8239;"	d
+GET_RG_RF_REF_SAT_GN	smac/hal/ssv6006c/ssv6006C_reg.h	8243;"	d
+GET_RG_RIFS_EN	include/ssv6200_reg.h	4324;"	d
+GET_RG_RIFS_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8685;"	d
+GET_RG_RSSIADC_RO_BIT	include/ssv6200_reg.h	4786;"	d
+GET_RG_RSSI_CLOCK_GATING	include/ssv6200_reg.h	4558;"	d
+GET_RG_RSSI_CLOCK_GATING	smac/hal/ssv6006c/ssv6006C_reg.h	6591;"	d
+GET_RG_RSSI_EDGE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	7585;"	d
+GET_RG_RSSI_EDGE_SEL_BB	smac/hal/ssv6006c/ssv6006C_reg.h	8183;"	d
+GET_RG_RSSI_INV	include/ssv6200_reg.h	4017;"	d
+GET_RG_RSSI_INV	smac/hal/ssv6006c/ssv6006C_reg.h	8307;"	d
+GET_RG_RSSI_OFFSET	include/ssv6200_reg.h	4016;"	d
+GET_RG_RSSI_OFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	8306;"	d
+GET_RG_RTC_CAL_MODE	include/ssv6200_reg.h	4515;"	d
+GET_RG_RTC_CAL_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	8086;"	d
+GET_RG_RTC_CAL_TARGET_COUNT	include/ssv6200_reg.h	4792;"	d
+GET_RG_RTC_CAL_TARGET_COUNT	smac/hal/ssv6006c/ssv6006C_reg.h	8084;"	d
+GET_RG_RTC_DUMMIES	include/ssv6200_reg.h	2447;"	d
+GET_RG_RTC_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8101;"	d
+GET_RG_RTC_INT_ALARM_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	8104;"	d
+GET_RG_RTC_INT_SEC_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	8103;"	d
+GET_RG_RTC_OFFSET	include/ssv6200_reg.h	4791;"	d
+GET_RG_RTC_OFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	8083;"	d
+GET_RG_RTC_OSC_RES_SW	include/ssv6200_reg.h	2436;"	d
+GET_RG_RTC_OSC_RES_SW_MANUAL	include/ssv6200_reg.h	2435;"	d
+GET_RG_RTC_OSC_RES_SW_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	8085;"	d
+GET_RG_RTC_OSC_RES_SW_MANUAL_EN	include/ssv6200_reg.h	2441;"	d
+GET_RG_RTC_OSC_RES_SW_MANUAL_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8088;"	d
+GET_RG_RTC_RDY_DEGLITCH_TIMER	include/ssv6200_reg.h	2442;"	d
+GET_RG_RTC_RS1	smac/hal/ssv6006c/ssv6006C_reg.h	8078;"	d
+GET_RG_RTC_RS2	smac/hal/ssv6006c/ssv6006C_reg.h	8079;"	d
+GET_RG_RTC_SEC_ALARM_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	8109;"	d
+GET_RG_RTC_SEC_START_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8108;"	d
+GET_RG_RXAGC_OW	include/ssv6200_reg.h	3931;"	d
+GET_RG_RXAGC_OW	smac/hal/ssv6006c/ssv6006C_reg.h	8250;"	d
+GET_RG_RXAGC_SET	include/ssv6200_reg.h	3930;"	d
+GET_RG_RXAGC_SET	smac/hal/ssv6006c/ssv6006C_reg.h	8249;"	d
+GET_RG_RXIQ_EMU_IDX	include/ssv6200_reg.h	4408;"	d
+GET_RG_RXIQ_NOSHRINK	include/ssv6200_reg.h	4364;"	d
+GET_RG_RXIQ_NOSHRK	smac/hal/ssv6006c/ssv6006C_reg.h	7582;"	d
+GET_RG_RXRF_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	7068;"	d
+GET_RG_RXRF_R2T_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	7077;"	d
+GET_RG_RXRF_T2R_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	7073;"	d
+GET_RG_RX_ABBCFIX	include/ssv6200_reg.h	4530;"	d
+GET_RG_RX_ABBCTUNE	include/ssv6200_reg.h	4531;"	d
+GET_RG_RX_ABBOUT_TRI_STATE	include/ssv6200_reg.h	4532;"	d
+GET_RG_RX_ABBOUT_TRI_STATE	smac/hal/ssv6006c/ssv6006C_reg.h	6524;"	d
+GET_RG_RX_ABB_N_MODE	include/ssv6200_reg.h	4533;"	d
+GET_RG_RX_ADCRSSI_CLKSEL	include/ssv6200_reg.h	4555;"	d
+GET_RG_RX_ADCRSSI_CLKSEL	smac/hal/ssv6006c/ssv6006C_reg.h	6590;"	d
+GET_RG_RX_ADCRSSI_VCM	include/ssv6200_reg.h	4556;"	d
+GET_RG_RX_ADCRSSI_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	6588;"	d
+GET_RG_RX_ADC_CLKSEL	smac/hal/ssv6006c/ssv6006C_reg.h	6719;"	d
+GET_RG_RX_ADC_DNLEN	smac/hal/ssv6006c/ssv6006C_reg.h	6720;"	d
+GET_RG_RX_ADC_I_RO_BIT	include/ssv6200_reg.h	4787;"	d
+GET_RG_RX_ADC_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	6486;"	d
+GET_RG_RX_ADC_METAEN	smac/hal/ssv6006c/ssv6006C_reg.h	6721;"	d
+GET_RG_RX_ADC_Q_RO_BIT	include/ssv6200_reg.h	4788;"	d
+GET_RG_RX_ADC_TFLAG	smac/hal/ssv6006c/ssv6006C_reg.h	6722;"	d
+GET_RG_RX_ADC_TSEL	smac/hal/ssv6006c/ssv6006C_reg.h	6723;"	d
+GET_RG_RX_AGC	include/ssv6200_reg.h	4478;"	d
+GET_RG_RX_AGC	smac/hal/ssv6006c/ssv6006C_reg.h	6464;"	d
+GET_RG_RX_BEACON_CRC_BYPASS	smac/hal/ssv6006c/ssv6006C_reg.h	8404;"	d
+GET_RG_RX_BEACON_INTERVAL	smac/hal/ssv6006c/ssv6006C_reg.h	8405;"	d
+GET_RG_RX_BEACON_LOSS_CNT_LMT	smac/hal/ssv6006c/ssv6006C_reg.h	8403;"	d
+GET_RG_RX_BEACON_TU	smac/hal/ssv6006c/ssv6006C_reg.h	8401;"	d
+GET_RG_RX_DC_POLAR_INV	smac/hal/ssv6006c/ssv6006C_reg.h	7661;"	d
+GET_RG_RX_DC_RESOLUTION	smac/hal/ssv6006c/ssv6006C_reg.h	7663;"	d
+GET_RG_RX_DES_LEN_LO	include/ssv6200_reg.h	3992;"	d
+GET_RG_RX_DES_LEN_UP	include/ssv6200_reg.h	3993;"	d
+GET_RG_RX_DES_L_LEN_LO	include/ssv6200_reg.h	3995;"	d
+GET_RG_RX_DES_L_LEN_UP	include/ssv6200_reg.h	3996;"	d
+GET_RG_RX_DES_L_LEN_UP_COMB	include/ssv6200_reg.h	3998;"	d
+GET_RG_RX_DES_MODE	include/ssv6200_reg.h	3991;"	d
+GET_RG_RX_DES_MODE_COMB	include/ssv6200_reg.h	4001;"	d
+GET_RG_RX_DES_RATE	include/ssv6200_reg.h	3990;"	d
+GET_RG_RX_DES_RATE_COMB	include/ssv6200_reg.h	4000;"	d
+GET_RG_RX_DES_RCPI	include/ssv6200_reg.h	4003;"	d
+GET_RG_RX_DES_RCPI_GN	include/ssv6200_reg.h	4014;"	d
+GET_RG_RX_DES_SNR	include/ssv6200_reg.h	4002;"	d
+GET_RG_RX_DES_SNR_GN	include/ssv6200_reg.h	4013;"	d
+GET_RG_RX_DES_SRVC_LO	include/ssv6200_reg.h	4004;"	d
+GET_RG_RX_DES_SRVC_UP	include/ssv6200_reg.h	3994;"	d
+GET_RG_RX_DES_TYPE	include/ssv6200_reg.h	3997;"	d
+GET_RG_RX_DES_TYPE_COMB	include/ssv6200_reg.h	3999;"	d
+GET_RG_RX_DIV2_CORE	include/ssv6200_reg.h	4569;"	d
+GET_RG_RX_DIV2_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	6478;"	d
+GET_RG_RX_EN_LOOPA	include/ssv6200_reg.h	4534;"	d
+GET_RG_RX_FFT_SCALE	include/ssv6200_reg.h	4230;"	d
+GET_RG_RX_FIFO_FULL_CNT_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8418;"	d
+GET_RG_RX_FILTERI1ST	include/ssv6200_reg.h	4535;"	d
+GET_RG_RX_FILTERI2ND	include/ssv6200_reg.h	4536;"	d
+GET_RG_RX_FILTERI3RD	include/ssv6200_reg.h	4537;"	d
+GET_RG_RX_FILTERI_COURSE	include/ssv6200_reg.h	4538;"	d
+GET_RG_RX_FILTERVCM	include/ssv6200_reg.h	4539;"	d
+GET_RG_RX_FILTER_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	6484;"	d
+GET_RG_RX_GAIN_MANUAL	include/ssv6200_reg.h	4479;"	d
+GET_RG_RX_GAIN_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	6461;"	d
+GET_RG_RX_HG_LNAHGN_BIAS	include/ssv6200_reg.h	4579;"	d
+GET_RG_RX_HG_LNAHGP_BIAS	include/ssv6200_reg.h	4580;"	d
+GET_RG_RX_HG_LNALG_BIAS	include/ssv6200_reg.h	4581;"	d
+GET_RG_RX_HG_LNA_GC	include/ssv6200_reg.h	4578;"	d
+GET_RG_RX_HG_TZ_CAP	include/ssv6200_reg.h	4583;"	d
+GET_RG_RX_HG_TZ_GC	include/ssv6200_reg.h	4582;"	d
+GET_RG_RX_HPF300K	include/ssv6200_reg.h	4541;"	d
+GET_RG_RX_HPF3M	include/ssv6200_reg.h	4540;"	d
+GET_RG_RX_HPFI	include/ssv6200_reg.h	4542;"	d
+GET_RG_RX_HPF_FINALCORNER	include/ssv6200_reg.h	4543;"	d
+GET_RG_RX_HPF_SETTLE1_C	include/ssv6200_reg.h	4544;"	d
+GET_RG_RX_HPF_SETTLE1_R	include/ssv6200_reg.h	4545;"	d
+GET_RG_RX_HPF_SETTLE2_C	include/ssv6200_reg.h	4546;"	d
+GET_RG_RX_HPF_SETTLE2_R	include/ssv6200_reg.h	4547;"	d
+GET_RG_RX_HPF_VCMCON	include/ssv6200_reg.h	4549;"	d
+GET_RG_RX_HPF_VCMCON2	include/ssv6200_reg.h	4548;"	d
+GET_RG_RX_IDACA_COARSE_PMOS_ON	smac/hal/ssv6006c/ssv6006C_reg.h	6592;"	d
+GET_RG_RX_IQCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	7083;"	d
+GET_RG_RX_IQCAL_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	6513;"	d
+GET_RG_RX_IQ_2500_ALPHA	smac/hal/ssv6006c/ssv6006C_reg.h	7615;"	d
+GET_RG_RX_IQ_2500_THETA	smac/hal/ssv6006c/ssv6006C_reg.h	7616;"	d
+GET_RG_RX_IQ_5100_ALPHA	smac/hal/ssv6006c/ssv6006C_reg.h	7619;"	d
+GET_RG_RX_IQ_5100_THETA	smac/hal/ssv6006c/ssv6006C_reg.h	7620;"	d
+GET_RG_RX_IQ_5500_ALPHA	smac/hal/ssv6006c/ssv6006C_reg.h	7623;"	d
+GET_RG_RX_IQ_5500_THETA	smac/hal/ssv6006c/ssv6006C_reg.h	7624;"	d
+GET_RG_RX_IQ_5700_ALPHA	smac/hal/ssv6006c/ssv6006C_reg.h	7627;"	d
+GET_RG_RX_IQ_5700_THETA	smac/hal/ssv6006c/ssv6006C_reg.h	7628;"	d
+GET_RG_RX_IQ_5900_ALPHA	smac/hal/ssv6006c/ssv6006C_reg.h	7631;"	d
+GET_RG_RX_IQ_5900_THETA	smac/hal/ssv6006c/ssv6006C_reg.h	7632;"	d
+GET_RG_RX_IQ_ALPHA	include/ssv6200_reg.h	4363;"	d
+GET_RG_RX_IQ_ALPHA	smac/hal/ssv6006c/ssv6006C_reg.h	7579;"	d
+GET_RG_RX_IQ_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	7581;"	d
+GET_RG_RX_IQ_SRC	include/ssv6200_reg.h	4398;"	d
+GET_RG_RX_IQ_SWP	include/ssv6200_reg.h	4396;"	d
+GET_RG_RX_IQ_THETA	include/ssv6200_reg.h	4362;"	d
+GET_RG_RX_IQ_THETA	smac/hal/ssv6006c/ssv6006C_reg.h	7580;"	d
+GET_RG_RX_I_OFFSET	include/ssv6200_reg.h	4394;"	d
+GET_RG_RX_I_SCALE	include/ssv6200_reg.h	4392;"	d
+GET_RG_RX_LG_LNAHGN_BIAS	include/ssv6200_reg.h	4591;"	d
+GET_RG_RX_LG_LNAHGP_BIAS	include/ssv6200_reg.h	4592;"	d
+GET_RG_RX_LG_LNALG_BIAS	include/ssv6200_reg.h	4593;"	d
+GET_RG_RX_LG_LNA_GC	include/ssv6200_reg.h	4590;"	d
+GET_RG_RX_LG_TZ_CAP	include/ssv6200_reg.h	4595;"	d
+GET_RG_RX_LG_TZ_GC	include/ssv6200_reg.h	4594;"	d
+GET_RG_RX_LNA_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	6474;"	d
+GET_RG_RX_LNA_SETTLE	include/ssv6200_reg.h	4609;"	d
+GET_RG_RX_LNA_SETTLE	smac/hal/ssv6006c/ssv6006C_reg.h	6601;"	d
+GET_RG_RX_LNA_TRI_SEL	include/ssv6200_reg.h	4608;"	d
+GET_RG_RX_LNA_TRI_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	6600;"	d
+GET_RG_RX_LOBUF	include/ssv6200_reg.h	4570;"	d
+GET_RG_RX_LOBUF_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	6480;"	d
+GET_RG_RX_MG_LNAHGN_BIAS	include/ssv6200_reg.h	4585;"	d
+GET_RG_RX_MG_LNAHGP_BIAS	include/ssv6200_reg.h	4586;"	d
+GET_RG_RX_MG_LNALG_BIAS	include/ssv6200_reg.h	4587;"	d
+GET_RG_RX_MG_LNA_GC	include/ssv6200_reg.h	4584;"	d
+GET_RG_RX_MG_TZ_CAP	include/ssv6200_reg.h	4589;"	d
+GET_RG_RX_MG_TZ_GC	include/ssv6200_reg.h	4588;"	d
+GET_RG_RX_MIXER_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	6476;"	d
+GET_RG_RX_MONITOR_ON	smac/hal/ssv6006c/ssv6006C_reg.h	8397;"	d
+GET_RG_RX_N_RCCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	7084;"	d
+GET_RG_RX_OUTVCM	include/ssv6200_reg.h	4550;"	d
+GET_RG_RX_PADPD_DATA_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	7931;"	d
+GET_RG_RX_PADPD_DC_RM_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	7940;"	d
+GET_RG_RX_PADPD_DC_RM_LEAKY_FACTOR	smac/hal/ssv6006c/ssv6006C_reg.h	7939;"	d
+GET_RG_RX_PADPD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	7928;"	d
+GET_RG_RX_PADPD_LATCH	smac/hal/ssv6006c/ssv6006C_reg.h	7930;"	d
+GET_RG_RX_PADPD_LEAKY_FACTOR	smac/hal/ssv6006c/ssv6006C_reg.h	7929;"	d
+GET_RG_RX_PADPD_RATE	smac/hal/ssv6006c/ssv6006C_reg.h	7933;"	d
+GET_RG_RX_PADPD_TONE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	7932;"	d
+GET_RG_RX_PKT_ADDR1_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	8407;"	d
+GET_RG_RX_PKT_ADDR1_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	8408;"	d
+GET_RG_RX_PKT_ADDR1_ON	smac/hal/ssv6006c/ssv6006C_reg.h	8400;"	d
+GET_RG_RX_PKT_ADDR2_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	8409;"	d
+GET_RG_RX_PKT_ADDR2_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	8410;"	d
+GET_RG_RX_PKT_ADDR2_ON	smac/hal/ssv6006c/ssv6006C_reg.h	8399;"	d
+GET_RG_RX_PKT_ADDR3_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	8411;"	d
+GET_RG_RX_PKT_ADDR3_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	8412;"	d
+GET_RG_RX_PKT_ADDR3_ON	smac/hal/ssv6006c/ssv6006C_reg.h	8398;"	d
+GET_RG_RX_PKT_FC	smac/hal/ssv6006c/ssv6006C_reg.h	8406;"	d
+GET_RG_RX_PKT_TIMER_LMT	smac/hal/ssv6006c/ssv6006C_reg.h	8402;"	d
+GET_RG_RX_PRE_DC_RESOLUTION	smac/hal/ssv6006c/ssv6006C_reg.h	7671;"	d
+GET_RG_RX_Q_OFFSET	include/ssv6200_reg.h	4395;"	d
+GET_RG_RX_Q_SCALE	include/ssv6200_reg.h	4393;"	d
+GET_RG_RX_RCCAL_40M_TARG	smac/hal/ssv6006c/ssv6006C_reg.h	7664;"	d
+GET_RG_RX_RCCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	7080;"	d
+GET_RG_RX_RCCAL_TARG	smac/hal/ssv6006c/ssv6006C_reg.h	7660;"	d
+GET_RG_RX_REC_LPFCORNER	include/ssv6200_reg.h	4557;"	d
+GET_RG_RX_REC_LPFCORNER	smac/hal/ssv6006c/ssv6006C_reg.h	6589;"	d
+GET_RG_RX_RSSIADC_TH	smac/hal/ssv6006c/ssv6006C_reg.h	7583;"	d
+GET_RG_RX_RSSI_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	6488;"	d
+GET_RG_RX_SCALOAD_STEP0	smac/hal/ssv6006c/ssv6006C_reg.h	7540;"	d
+GET_RG_RX_SCALOAD_STEP1	smac/hal/ssv6006c/ssv6006C_reg.h	7541;"	d
+GET_RG_RX_SCALOAD_STEP2	smac/hal/ssv6006c/ssv6006C_reg.h	7542;"	d
+GET_RG_RX_SCALOAD_STEP3	smac/hal/ssv6006c/ssv6006C_reg.h	7543;"	d
+GET_RG_RX_SCALOAD_STEP4	smac/hal/ssv6006c/ssv6006C_reg.h	7544;"	d
+GET_RG_RX_SCALOAD_STEP5	smac/hal/ssv6006c/ssv6006C_reg.h	7545;"	d
+GET_RG_RX_SCALOAD_STEP6	smac/hal/ssv6006c/ssv6006C_reg.h	7546;"	d
+GET_RG_RX_SCAMA_STEP0	smac/hal/ssv6006c/ssv6006C_reg.h	7533;"	d
+GET_RG_RX_SCAMA_STEP1	smac/hal/ssv6006c/ssv6006C_reg.h	7534;"	d
+GET_RG_RX_SCAMA_STEP2	smac/hal/ssv6006c/ssv6006C_reg.h	7535;"	d
+GET_RG_RX_SCAMA_STEP3	smac/hal/ssv6006c/ssv6006C_reg.h	7536;"	d
+GET_RG_RX_SCAMA_STEP4	smac/hal/ssv6006c/ssv6006C_reg.h	7537;"	d
+GET_RG_RX_SCAMA_STEP5	smac/hal/ssv6006c/ssv6006C_reg.h	7538;"	d
+GET_RG_RX_SCAMA_STEP6	smac/hal/ssv6006c/ssv6006C_reg.h	7539;"	d
+GET_RG_RX_SGN_IN	include/ssv6200_reg.h	4397;"	d
+GET_RG_RX_SQDC	include/ssv6200_reg.h	4568;"	d
+GET_RG_RX_SQDC	smac/hal/ssv6006c/ssv6006C_reg.h	6531;"	d
+GET_RG_RX_TZI	include/ssv6200_reg.h	4551;"	d
+GET_RG_RX_TZ_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	6482;"	d
+GET_RG_RX_TZ_OUT_TRISTATE	include/ssv6200_reg.h	4552;"	d
+GET_RG_RX_TZ_OUT_TRISTATE	smac/hal/ssv6006c/ssv6006C_reg.h	6510;"	d
+GET_RG_RX_TZ_OUT_TRISTATE_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	6509;"	d
+GET_RG_RX_TZ_VCM	include/ssv6200_reg.h	4553;"	d
+GET_RG_RX_ULG_LNAHGN_BIAS	include/ssv6200_reg.h	4597;"	d
+GET_RG_RX_ULG_LNAHGP_BIAS	include/ssv6200_reg.h	4598;"	d
+GET_RG_RX_ULG_LNALG_BIAS	include/ssv6200_reg.h	4599;"	d
+GET_RG_RX_ULG_LNA_GC	include/ssv6200_reg.h	4596;"	d
+GET_RG_RX_ULG_TZ_CAP	include/ssv6200_reg.h	4601;"	d
+GET_RG_RX_ULG_TZ_GC	include/ssv6200_reg.h	4600;"	d
+GET_RG_SARADC_5G_TSSI	smac/hal/ssv6006c/ssv6006C_reg.h	6732;"	d
+GET_RG_SARADC_BIT	include/ssv6200_reg.h	4780;"	d
+GET_RG_SARADC_THERMAL	include/ssv6200_reg.h	4627;"	d
+GET_RG_SARADC_THERMAL	smac/hal/ssv6006c/ssv6006C_reg.h	6735;"	d
+GET_RG_SARADC_TSSI	include/ssv6200_reg.h	4628;"	d
+GET_RG_SARADC_TSSI	smac/hal/ssv6006c/ssv6006C_reg.h	6736;"	d
+GET_RG_SARADC_VRSEL	include/ssv6200_reg.h	4625;"	d
+GET_RG_SARADC_VRSEL	smac/hal/ssv6006c/ssv6006C_reg.h	6733;"	d
+GET_RG_SB_START_CNT	include/ssv6200_reg.h	4253;"	d
+GET_RG_SB_START_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8615;"	d
+GET_RG_SCR_INIT_SEED	smac/hal/ssv6006c/ssv6006C_reg.h	8536;"	d
+GET_RG_SCR_SEED_MANUANL	smac/hal/ssv6006c/ssv6006C_reg.h	8537;"	d
+GET_RG_SC_CTRL0	smac/hal/ssv6006c/ssv6006C_reg.h	8589;"	d
+GET_RG_SC_CTRL1	smac/hal/ssv6006c/ssv6006C_reg.h	8587;"	d
+GET_RG_SC_CTRL2	smac/hal/ssv6006c/ssv6006C_reg.h	8585;"	d
+GET_RG_SC_CTRL3	smac/hal/ssv6006c/ssv6006C_reg.h	8583;"	d
+GET_RG_SC_CTRL4	smac/hal/ssv6006c/ssv6006C_reg.h	8597;"	d
+GET_RG_SC_CTRL5	smac/hal/ssv6006c/ssv6006C_reg.h	8595;"	d
+GET_RG_SC_CTRL6	smac/hal/ssv6006c/ssv6006C_reg.h	8593;"	d
+GET_RG_SC_CTRL7	smac/hal/ssv6006c/ssv6006C_reg.h	8591;"	d
+GET_RG_SEC_CNT_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	8100;"	d
+GET_RG_SEL_DPLL_CLK	include/ssv6200_reg.h	4499;"	d
+GET_RG_SEL_DPLL_CLK	smac/hal/ssv6006c/ssv6006C_reg.h	8087;"	d
+GET_RG_SERVICE	include/ssv6200_reg.h	3897;"	d
+GET_RG_SERVICE	smac/hal/ssv6006c/ssv6006C_reg.h	8216;"	d
+GET_RG_SFD_BIT_CNT_LMT	include/ssv6200_reg.h	4175;"	d
+GET_RG_SFD_BIT_CNT_LMT	smac/hal/ssv6006c/ssv6006C_reg.h	8489;"	d
+GET_RG_SHIFT_DR_16	include/ssv6200_reg.h	4057;"	d
+GET_RG_SHIFT_DR_64	include/ssv6200_reg.h	4295;"	d
+GET_RG_SHIFT_DR_80	include/ssv6200_reg.h	4288;"	d
+GET_RG_SHORTGI	include/ssv6200_reg.h	3893;"	d
+GET_RG_SHORTGI	smac/hal/ssv6006c/ssv6006C_reg.h	8212;"	d
+GET_RG_SHORT_GI_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8529;"	d
+GET_RG_SIGN_SWAP	include/ssv6200_reg.h	3861;"	d
+GET_RG_SIGN_SWAP	smac/hal/ssv6006c/ssv6006C_reg.h	7590;"	d
+GET_RG_SIGN_SWAP_BB	smac/hal/ssv6006c/ssv6006C_reg.h	8184;"	d
+GET_RG_SIMULATION_MODE_16	include/ssv6200_reg.h	4059;"	d
+GET_RG_SIMULATION_MODE_64	include/ssv6200_reg.h	4297;"	d
+GET_RG_SIMULATION_MODE_80	include/ssv6200_reg.h	4290;"	d
+GET_RG_SLEEP_METHOD	smac/hal/ssv6006c/ssv6006C_reg.h	8097;"	d
+GET_RG_SLEEP_WAKE_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8099;"	d
+GET_RG_SMB_DEF	include/ssv6200_reg.h	4203;"	d
+GET_RG_SMOOTHING	include/ssv6200_reg.h	3898;"	d
+GET_RG_SMOOTHING	smac/hal/ssv6006c/ssv6006C_reg.h	8217;"	d
+GET_RG_SNR_TH_16QAM	include/ssv6200_reg.h	4248;"	d
+GET_RG_SNR_TH_16QAM	smac/hal/ssv6006c/ssv6006C_reg.h	8577;"	d
+GET_RG_SNR_TH_64QAM	include/ssv6200_reg.h	4247;"	d
+GET_RG_SNR_TH_64QAM	smac/hal/ssv6006c/ssv6006C_reg.h	8576;"	d
+GET_RG_SOFT_RST_N_11B_RX	smac/hal/ssv6006c/ssv6006C_reg.h	8516;"	d
+GET_RG_SOFT_RST_N_11GN_RX	smac/hal/ssv6006c/ssv6006C_reg.h	8684;"	d
+GET_RG_SPECTRUM_BW	include/ssv6200_reg.h	3868;"	d
+GET_RG_SPECTRUM_BW	smac/hal/ssv6006c/ssv6006C_reg.h	7638;"	d
+GET_RG_SPECTRUM_EN	include/ssv6200_reg.h	3870;"	d
+GET_RG_SPECTRUM_EN	smac/hal/ssv6006c/ssv6006C_reg.h	7639;"	d
+GET_RG_SPECTRUM_FREQ	include/ssv6200_reg.h	3887;"	d
+GET_RG_SPECTRUM_FREQ_MANUAL	include/ssv6200_reg.h	3869;"	d
+GET_RG_SPECTRUM_LEAKY_FACTOR	include/ssv6200_reg.h	3867;"	d
+GET_RG_SPECTRUM_LO_FIX	smac/hal/ssv6006c/ssv6006C_reg.h	7666;"	d
+GET_RG_SPECTRUM_PWR_UPDATE	smac/hal/ssv6006c/ssv6006C_reg.h	7667;"	d
+GET_RG_STBC	include/ssv6200_reg.h	3901;"	d
+GET_RG_STBC	smac/hal/ssv6006c/ssv6006C_reg.h	8220;"	d
+GET_RG_STBC_EN	include/ssv6200_reg.h	4325;"	d
+GET_RG_STBC_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8686;"	d
+GET_RG_STF_SCALE_20	smac/hal/ssv6006c/ssv6006C_reg.h	8530;"	d
+GET_RG_STF_SCALE_40	smac/hal/ssv6006c/ssv6006C_reg.h	8531;"	d
+GET_RG_SUB_DC	smac/hal/ssv6006c/ssv6006C_reg.h	7584;"	d
+GET_RG_SW_FALL_TIME	include/ssv6200_reg.h	4035;"	d
+GET_RG_SW_RISE_TIME	include/ssv6200_reg.h	4031;"	d
+GET_RG_SX5GB_AAC_ACCUMH	smac/hal/ssv6006c/ssv6006C_reg.h	7388;"	d
+GET_RG_SX5GB_AAC_ACCUML	smac/hal/ssv6006c/ssv6006C_reg.h	7389;"	d
+GET_RG_SX5GB_AAC_EN	smac/hal/ssv6006c/ssv6006C_reg.h	7393;"	d
+GET_RG_SX5GB_AAC_EN_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	7392;"	d
+GET_RG_SX5GB_AAC_EVA	smac/hal/ssv6006c/ssv6006C_reg.h	7395;"	d
+GET_RG_SX5GB_AAC_EVA_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	7394;"	d
+GET_RG_SX5GB_AAC_EVA_TS	smac/hal/ssv6006c/ssv6006C_reg.h	7391;"	d
+GET_RG_SX5GB_AAC_INIT	smac/hal/ssv6006c/ssv6006C_reg.h	7390;"	d
+GET_RG_SX5GB_AAC_TEST_EN	smac/hal/ssv6006c/ssv6006C_reg.h	7401;"	d
+GET_RG_SX5GB_AAC_TEST_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	7402;"	d
+GET_RG_SX5GB_CAL_INIT	smac/hal/ssv6006c/ssv6006C_reg.h	7296;"	d
+GET_RG_SX5GB_CHANNEL	smac/hal/ssv6006c/ssv6006C_reg.h	7266;"	d
+GET_RG_SX5GB_CP_IOST	smac/hal/ssv6006c/ssv6006C_reg.h	7324;"	d
+GET_RG_SX5GB_CP_IOST_POL	smac/hal/ssv6006c/ssv6006C_reg.h	7323;"	d
+GET_RG_SX5GB_CP_ISEL	smac/hal/ssv6006c/ssv6006C_reg.h	7320;"	d
+GET_RG_SX5GB_CP_ISEL50U	smac/hal/ssv6006c/ssv6006C_reg.h	7321;"	d
+GET_RG_SX5GB_CP_KP_DOUB	smac/hal/ssv6006c/ssv6006C_reg.h	7322;"	d
+GET_RG_SX5GB_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	7493;"	d
+GET_RG_SX5GB_DITHER_WEIGHT	smac/hal/ssv6006c/ssv6006C_reg.h	7373;"	d
+GET_RG_SX5GB_DIV_DMYBUF_EN	smac/hal/ssv6006c/ssv6006C_reg.h	7369;"	d
+GET_RG_SX5GB_DIV_PREVDD	smac/hal/ssv6006c/ssv6006C_reg.h	7365;"	d
+GET_RG_SX5GB_DIV_PSCVDD	smac/hal/ssv6006c/ssv6006C_reg.h	7366;"	d
+GET_RG_SX5GB_DIV_RST_H	smac/hal/ssv6006c/ssv6006C_reg.h	7367;"	d
+GET_RG_SX5GB_DIV_SDM_EDGE	smac/hal/ssv6006c/ssv6006C_reg.h	7368;"	d
+GET_RG_SX5GB_LDO_CP_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	7148;"	d
+GET_RG_SX5GB_LDO_DIV_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	7153;"	d
+GET_RG_SX5GB_LDO_FCOFFT	smac/hal/ssv6006c/ssv6006C_reg.h	7310;"	d
+GET_RG_SX5GB_LDO_LO_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	7150;"	d
+GET_RG_SX5GB_LDO_VCO_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	7152;"	d
+GET_RG_SX5GB_LO_TIMES	smac/hal/ssv6006c/ssv6006C_reg.h	7265;"	d
+GET_RG_SX5GB_LPF_C1	smac/hal/ssv6006c/ssv6006C_reg.h	7334;"	d
+GET_RG_SX5GB_LPF_C2	smac/hal/ssv6006c/ssv6006C_reg.h	7335;"	d
+GET_RG_SX5GB_LPF_C3	smac/hal/ssv6006c/ssv6006C_reg.h	7336;"	d
+GET_RG_SX5GB_LPF_R2	smac/hal/ssv6006c/ssv6006C_reg.h	7337;"	d
+GET_RG_SX5GB_LPF_R3	smac/hal/ssv6006c/ssv6006C_reg.h	7338;"	d
+GET_RG_SX5GB_LPF_VTUNE_TEST	smac/hal/ssv6006c/ssv6006C_reg.h	7347;"	d
+GET_RG_SX5GB_MIXAAC_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	7293;"	d
+GET_RG_SX5GB_MIXAAC_TAR	smac/hal/ssv6006c/ssv6006C_reg.h	7403;"	d
+GET_RG_SX5GB_MOD_ORDER	smac/hal/ssv6006c/ssv6006C_reg.h	7372;"	d
+GET_RG_SX5GB_PFD_DIV_EDGE	smac/hal/ssv6006c/ssv6006C_reg.h	7333;"	d
+GET_RG_SX5GB_PFD_REF_EDGE	smac/hal/ssv6006c/ssv6006C_reg.h	7332;"	d
+GET_RG_SX5GB_PFD_RST	smac/hal/ssv6006c/ssv6006C_reg.h	7276;"	d
+GET_RG_SX5GB_PFD_RST_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	7275;"	d
+GET_RG_SX5GB_PFD_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	7325;"	d
+GET_RG_SX5GB_PFD_SET	smac/hal/ssv6006c/ssv6006C_reg.h	7326;"	d
+GET_RG_SX5GB_PFD_SET1	smac/hal/ssv6006c/ssv6006C_reg.h	7327;"	d
+GET_RG_SX5GB_PFD_SET2	smac/hal/ssv6006c/ssv6006C_reg.h	7328;"	d
+GET_RG_SX5GB_PFD_TLSEL	smac/hal/ssv6006c/ssv6006C_reg.h	7331;"	d
+GET_RG_SX5GB_PFD_TRDN	smac/hal/ssv6006c/ssv6006C_reg.h	7330;"	d
+GET_RG_SX5GB_PFD_TRUP	smac/hal/ssv6006c/ssv6006C_reg.h	7329;"	d
+GET_RG_SX5GB_REPAAC_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	7294;"	d
+GET_RG_SX5GB_REPAAC_TAR	smac/hal/ssv6006c/ssv6006C_reg.h	7406;"	d
+GET_RG_SX5GB_RFCH_MAP_EN	smac/hal/ssv6006c/ssv6006C_reg.h	7264;"	d
+GET_RG_SX5GB_RFCTRL_CH_10_8	smac/hal/ssv6006c/ssv6006C_reg.h	7263;"	d
+GET_RG_SX5GB_RFCTRL_CH_7_0	smac/hal/ssv6006c/ssv6006C_reg.h	7262;"	d
+GET_RG_SX5GB_RFCTRL_F	smac/hal/ssv6006c/ssv6006C_reg.h	7261;"	d
+GET_RG_SX5GB_SBCAL_2ND_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	7290;"	d
+GET_RG_SX5GB_SBCAL_AW	smac/hal/ssv6006c/ssv6006C_reg.h	7291;"	d
+GET_RG_SX5GB_SBCAL_CT	smac/hal/ssv6006c/ssv6006C_reg.h	7380;"	d
+GET_RG_SX5GB_SBCAL_DIFFMIN	smac/hal/ssv6006c/ssv6006C_reg.h	7382;"	d
+GET_RG_SX5GB_SBCAL_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	7289;"	d
+GET_RG_SX5GB_SBCAL_NTARG	smac/hal/ssv6006c/ssv6006C_reg.h	7384;"	d
+GET_RG_SX5GB_SBCAL_NTARG_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	7383;"	d
+GET_RG_SX5GB_SBCAL_WT	smac/hal/ssv6006c/ssv6006C_reg.h	7381;"	d
+GET_RG_SX5GB_SUB_C0P5_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	7379;"	d
+GET_RG_SX5GB_SUB_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	7378;"	d
+GET_RG_SX5GB_SUB_SEL_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	7377;"	d
+GET_RG_SX5GB_TTL_ACCUM	smac/hal/ssv6006c/ssv6006C_reg.h	7342;"	d
+GET_RG_SX5GB_TTL_CPT	smac/hal/ssv6006c/ssv6006C_reg.h	7341;"	d
+GET_RG_SX5GB_TTL_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	7295;"	d
+GET_RG_SX5GB_TTL_FPT	smac/hal/ssv6006c/ssv6006C_reg.h	7340;"	d
+GET_RG_SX5GB_TTL_INIT	smac/hal/ssv6006c/ssv6006C_reg.h	7339;"	d
+GET_RG_SX5GB_TTL_SUB	smac/hal/ssv6006c/ssv6006C_reg.h	7343;"	d
+GET_RG_SX5GB_TTL_SUB_INV	smac/hal/ssv6006c/ssv6006C_reg.h	7344;"	d
+GET_RG_SX5GB_TTL_VH	smac/hal/ssv6006c/ssv6006C_reg.h	7345;"	d
+GET_RG_SX5GB_TTL_VL	smac/hal/ssv6006c/ssv6006C_reg.h	7346;"	d
+GET_RG_SX5GB_UOP_EN	smac/hal/ssv6006c/ssv6006C_reg.h	7278;"	d
+GET_RG_SX5GB_UOP_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	7277;"	d
+GET_RG_SX5GB_VCO_CS_AWH	smac/hal/ssv6006c/ssv6006C_reg.h	7354;"	d
+GET_RG_SX5GB_VCO_ISEL	smac/hal/ssv6006c/ssv6006C_reg.h	7349;"	d
+GET_RG_SX5GB_VCO_ISEL_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	7348;"	d
+GET_RG_SX5GB_VCO_KVDOUB	smac/hal/ssv6006c/ssv6006C_reg.h	7351;"	d
+GET_RG_SX5GB_VCO_RTAIL_SHIFT	smac/hal/ssv6006c/ssv6006C_reg.h	7353;"	d
+GET_RG_SX5GB_VCO_VARBSEL	smac/hal/ssv6006c/ssv6006C_reg.h	7352;"	d
+GET_RG_SX5GB_VCO_VCCBSEL	smac/hal/ssv6006c/ssv6006C_reg.h	7350;"	d
+GET_RG_SX5GB_VOAAC_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	7292;"	d
+GET_RG_SX5GB_VOAAC_TAR	smac/hal/ssv6006c/ssv6006C_reg.h	7385;"	d
+GET_RG_SXMIX_GMBIAS_OP1	smac/hal/ssv6006c/ssv6006C_reg.h	7375;"	d
+GET_RG_SXMIX_GMSEL	smac/hal/ssv6006c/ssv6006C_reg.h	7361;"	d
+GET_RG_SXMIX_IBIAS_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	7359;"	d
+GET_RG_SXMIX_INBF_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	7374;"	d
+GET_RG_SXMIX_SCA_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	7405;"	d
+GET_RG_SXMIX_SCA_SEL_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	7404;"	d
+GET_RG_SXMIX_SWBIAS_OP1	smac/hal/ssv6006c/ssv6006C_reg.h	7376;"	d
+GET_RG_SXMIX_SWB_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	7360;"	d
+GET_RG_SXREP_CSSEL	smac/hal/ssv6006c/ssv6006C_reg.h	7363;"	d
+GET_RG_SXREP_SCA_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	7408;"	d
+GET_RG_SXREP_SCA_SEL_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	7407;"	d
+GET_RG_SXREP_SWB_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	7362;"	d
+GET_RG_SX_5GB_EN	smac/hal/ssv6006c/ssv6006C_reg.h	7268;"	d
+GET_RG_SX_5GB_EN_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	7267;"	d
+GET_RG_SX_AAC_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	6787;"	d
+GET_RG_SX_BTRX_SIDE	smac/hal/ssv6006c/ssv6006C_reg.h	6817;"	d
+GET_RG_SX_CAL_INIT	smac/hal/ssv6006c/ssv6006C_reg.h	6789;"	d
+GET_RG_SX_CHANNEL	smac/hal/ssv6006c/ssv6006C_reg.h	6819;"	d
+GET_RG_SX_CHP_IOST	include/ssv6200_reg.h	4671;"	d
+GET_RG_SX_CHP_IOST_POL	include/ssv6200_reg.h	4670;"	d
+GET_RG_SX_CP_IOST	smac/hal/ssv6006c/ssv6006C_reg.h	6828;"	d
+GET_RG_SX_CP_IOST_POL	smac/hal/ssv6006c/ssv6006C_reg.h	6827;"	d
+GET_RG_SX_CP_ISEL50U_BT	smac/hal/ssv6006c/ssv6006C_reg.h	6822;"	d
+GET_RG_SX_CP_ISEL50U_WF	smac/hal/ssv6006c/ssv6006C_reg.h	6825;"	d
+GET_RG_SX_CP_ISEL_BT	smac/hal/ssv6006c/ssv6006C_reg.h	6821;"	d
+GET_RG_SX_CP_ISEL_WF	smac/hal/ssv6006c/ssv6006C_reg.h	6824;"	d
+GET_RG_SX_CP_KP_DOUB_BT	smac/hal/ssv6006c/ssv6006C_reg.h	6823;"	d
+GET_RG_SX_CP_KP_DOUB_WF	smac/hal/ssv6006c/ssv6006C_reg.h	6826;"	d
+GET_RG_SX_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	7064;"	d
+GET_RG_SX_DITHER_WEIGHT	include/ssv6200_reg.h	4689;"	d
+GET_RG_SX_DITHER_WEIGHT	smac/hal/ssv6006c/ssv6006C_reg.h	6882;"	d
+GET_RG_SX_DIVBFSEL	include/ssv6200_reg.h	4687;"	d
+GET_RG_SX_DIV_DMYBUF_EN	smac/hal/ssv6006c/ssv6006C_reg.h	6878;"	d
+GET_RG_SX_DIV_PREVDD	smac/hal/ssv6006c/ssv6006C_reg.h	6874;"	d
+GET_RG_SX_DIV_PSCVDD	smac/hal/ssv6006c/ssv6006C_reg.h	6875;"	d
+GET_RG_SX_DIV_RST_H	smac/hal/ssv6006c/ssv6006C_reg.h	6876;"	d
+GET_RG_SX_DIV_SDM_EDGE	smac/hal/ssv6006c/ssv6006C_reg.h	6877;"	d
+GET_RG_SX_DUMMMY	include/ssv6200_reg.h	4772;"	d
+GET_RG_SX_EN	smac/hal/ssv6006c/ssv6006C_reg.h	6764;"	d
+GET_RG_SX_EN_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	6763;"	d
+GET_RG_SX_FREF_DOUB	smac/hal/ssv6006c/ssv6006C_reg.h	6816;"	d
+GET_RG_SX_FREF_DOUB_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	6815;"	d
+GET_RG_SX_GNDR_SEL	include/ssv6200_reg.h	4688;"	d
+GET_RG_SX_LCKEN	include/ssv6200_reg.h	4695;"	d
+GET_RG_SX_LCK_BIN_OFFSET	include/ssv6200_reg.h	4764;"	d
+GET_RG_SX_LCK_BIN_PRECISION	include/ssv6200_reg.h	4765;"	d
+GET_RG_SX_LDO_CHP_LEVEL	include/ssv6200_reg.h	4522;"	d
+GET_RG_SX_LDO_CP_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	6536;"	d
+GET_RG_SX_LDO_DIV_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	6541;"	d
+GET_RG_SX_LDO_FCOFFT	smac/hal/ssv6006c/ssv6006C_reg.h	6801;"	d
+GET_RG_SX_LDO_LOBF_LEVEL	include/ssv6200_reg.h	4523;"	d
+GET_RG_SX_LDO_LO_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	6538;"	d
+GET_RG_SX_LDO_VCO_LEVEL	include/ssv6200_reg.h	4526;"	d
+GET_RG_SX_LDO_VCO_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	6540;"	d
+GET_RG_SX_LDO_XOSC_LEVEL	include/ssv6200_reg.h	4524;"	d
+GET_RG_SX_LOCK_EN_N	include/ssv6200_reg.h	4766;"	d
+GET_RG_SX_LOCK_MANUAL	include/ssv6200_reg.h	4767;"	d
+GET_RG_SX_LO_TIMES	smac/hal/ssv6006c/ssv6006C_reg.h	6818;"	d
+GET_RG_SX_LPF_C1_BT	smac/hal/ssv6006c/ssv6006C_reg.h	6838;"	d
+GET_RG_SX_LPF_C1_WF	smac/hal/ssv6006c/ssv6006C_reg.h	6843;"	d
+GET_RG_SX_LPF_C2_BT	smac/hal/ssv6006c/ssv6006C_reg.h	6839;"	d
+GET_RG_SX_LPF_C2_WF	smac/hal/ssv6006c/ssv6006C_reg.h	6844;"	d
+GET_RG_SX_LPF_C3_BT	smac/hal/ssv6006c/ssv6006C_reg.h	6840;"	d
+GET_RG_SX_LPF_C3_WF	smac/hal/ssv6006c/ssv6006C_reg.h	6845;"	d
+GET_RG_SX_LPF_R2_BT	smac/hal/ssv6006c/ssv6006C_reg.h	6841;"	d
+GET_RG_SX_LPF_R2_WF	smac/hal/ssv6006c/ssv6006C_reg.h	6846;"	d
+GET_RG_SX_LPF_R3_BT	smac/hal/ssv6006c/ssv6006C_reg.h	6842;"	d
+GET_RG_SX_LPF_R3_WF	smac/hal/ssv6006c/ssv6006C_reg.h	6847;"	d
+GET_RG_SX_LPF_VTUNE_TEST	smac/hal/ssv6006c/ssv6006C_reg.h	6912;"	d
+GET_RG_SX_MOD_ORDER	include/ssv6200_reg.h	4690;"	d
+GET_RG_SX_MOD_ORDER	smac/hal/ssv6006c/ssv6006C_reg.h	6881;"	d
+GET_RG_SX_MUX_SEL_VTH_BINL	include/ssv6200_reg.h	4770;"	d
+GET_RG_SX_PFDSEL	include/ssv6200_reg.h	4672;"	d
+GET_RG_SX_PFD_DIV_EDGE	smac/hal/ssv6006c/ssv6006C_reg.h	6834;"	d
+GET_RG_SX_PFD_REF_EDGE	smac/hal/ssv6006c/ssv6006C_reg.h	6833;"	d
+GET_RG_SX_PFD_RST	smac/hal/ssv6006c/ssv6006C_reg.h	6772;"	d
+GET_RG_SX_PFD_RST_H	include/ssv6200_reg.h	4677;"	d
+GET_RG_SX_PFD_RST_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	6771;"	d
+GET_RG_SX_PFD_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	6829;"	d
+GET_RG_SX_PFD_SET	include/ssv6200_reg.h	4673;"	d
+GET_RG_SX_PFD_SET	smac/hal/ssv6006c/ssv6006C_reg.h	6830;"	d
+GET_RG_SX_PFD_SET1	include/ssv6200_reg.h	4674;"	d
+GET_RG_SX_PFD_SET1	smac/hal/ssv6006c/ssv6006C_reg.h	6831;"	d
+GET_RG_SX_PFD_SET2	include/ssv6200_reg.h	4675;"	d
+GET_RG_SX_PFD_SET2	smac/hal/ssv6006c/ssv6006C_reg.h	6832;"	d
+GET_RG_SX_PFD_TLSEL	smac/hal/ssv6006c/ssv6006C_reg.h	6837;"	d
+GET_RG_SX_PFD_TRDN	include/ssv6200_reg.h	4679;"	d
+GET_RG_SX_PFD_TRDN	smac/hal/ssv6006c/ssv6006C_reg.h	6836;"	d
+GET_RG_SX_PFD_TRSEL	include/ssv6200_reg.h	4680;"	d
+GET_RG_SX_PFD_TRUP	include/ssv6200_reg.h	4678;"	d
+GET_RG_SX_PFD_TRUP	smac/hal/ssv6006c/ssv6006C_reg.h	6835;"	d
+GET_RG_SX_PH	include/ssv6200_reg.h	4698;"	d
+GET_RG_SX_PL	include/ssv6200_reg.h	4699;"	d
+GET_RG_SX_PREVDD	include/ssv6200_reg.h	4696;"	d
+GET_RG_SX_PSCONTERVDD	include/ssv6200_reg.h	4697;"	d
+GET_RG_SX_REFBYTWO	include/ssv6200_reg.h	4694;"	d
+GET_RG_SX_RFCH_MAP_EN	smac/hal/ssv6006c/ssv6006C_reg.h	6814;"	d
+GET_RG_SX_RFCTRL_CH	include/ssv6200_reg.h	4662;"	d
+GET_RG_SX_RFCTRL_CH_10_8	smac/hal/ssv6006c/ssv6006C_reg.h	6813;"	d
+GET_RG_SX_RFCTRL_CH_7_0	smac/hal/ssv6006c/ssv6006C_reg.h	6812;"	d
+GET_RG_SX_RFCTRL_F	include/ssv6200_reg.h	4659;"	d
+GET_RG_SX_RFCTRL_F	smac/hal/ssv6006c/ssv6006C_reg.h	6811;"	d
+GET_RG_SX_RST_H_DIV	include/ssv6200_reg.h	4691;"	d
+GET_RG_SX_RXBFSEL	include/ssv6200_reg.h	4684;"	d
+GET_RG_SX_SBCAL_AW	smac/hal/ssv6006c/ssv6006C_reg.h	6786;"	d
+GET_RG_SX_SBCAL_CT	smac/hal/ssv6006c/ssv6006C_reg.h	6886;"	d
+GET_RG_SX_SBCAL_DIFFMIN	smac/hal/ssv6006c/ssv6006C_reg.h	6888;"	d
+GET_RG_SX_SBCAL_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	6785;"	d
+GET_RG_SX_SBCAL_NTARG	smac/hal/ssv6006c/ssv6006C_reg.h	6890;"	d
+GET_RG_SX_SBCAL_NTARG_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	6889;"	d
+GET_RG_SX_SBCAL_WT	smac/hal/ssv6006c/ssv6006C_reg.h	6887;"	d
+GET_RG_SX_SDM_EDGE	include/ssv6200_reg.h	4692;"	d
+GET_RG_SX_SEL_C3	include/ssv6200_reg.h	4663;"	d
+GET_RG_SX_SEL_CHP_REGOP	include/ssv6200_reg.h	4668;"	d
+GET_RG_SX_SEL_CHP_UNIOP	include/ssv6200_reg.h	4669;"	d
+GET_RG_SX_SEL_CP	include/ssv6200_reg.h	4660;"	d
+GET_RG_SX_SEL_CS	include/ssv6200_reg.h	4661;"	d
+GET_RG_SX_SEL_ICHP	include/ssv6200_reg.h	4666;"	d
+GET_RG_SX_SEL_PCHP	include/ssv6200_reg.h	4667;"	d
+GET_RG_SX_SEL_R3	include/ssv6200_reg.h	4665;"	d
+GET_RG_SX_SEL_RS	include/ssv6200_reg.h	4664;"	d
+GET_RG_SX_SUB_C0P5_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	6885;"	d
+GET_RG_SX_SUB_MANUAL	include/ssv6200_reg.h	4768;"	d
+GET_RG_SX_SUB_SEL	include/ssv6200_reg.h	4769;"	d
+GET_RG_SX_SUB_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	6884;"	d
+GET_RG_SX_SUB_SEL_CWD	include/ssv6200_reg.h	4763;"	d
+GET_RG_SX_SUB_SEL_CWR	include/ssv6200_reg.h	4762;"	d
+GET_RG_SX_SUB_SEL_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	6883;"	d
+GET_RG_SX_TARGET_CNT	include/ssv6200_reg.h	4790;"	d
+GET_RG_SX_TTL_ACCUM	smac/hal/ssv6006c/ssv6006C_reg.h	6907;"	d
+GET_RG_SX_TTL_CPT	smac/hal/ssv6006c/ssv6006C_reg.h	6906;"	d
+GET_RG_SX_TTL_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	6788;"	d
+GET_RG_SX_TTL_FPT	smac/hal/ssv6006c/ssv6006C_reg.h	6905;"	d
+GET_RG_SX_TTL_INIT	smac/hal/ssv6006c/ssv6006C_reg.h	6904;"	d
+GET_RG_SX_TTL_SUB	smac/hal/ssv6006c/ssv6006C_reg.h	6908;"	d
+GET_RG_SX_TTL_SUB_INV	smac/hal/ssv6006c/ssv6006C_reg.h	6909;"	d
+GET_RG_SX_TTL_VH	smac/hal/ssv6006c/ssv6006C_reg.h	6910;"	d
+GET_RG_SX_TTL_VL	smac/hal/ssv6006c/ssv6006C_reg.h	6911;"	d
+GET_RG_SX_TXBFSEL	include/ssv6200_reg.h	4685;"	d
+GET_RG_SX_UOP_EN	smac/hal/ssv6006c/ssv6006C_reg.h	6774;"	d
+GET_RG_SX_UOP_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	6773;"	d
+GET_RG_SX_VBNCAS_SEL	include/ssv6200_reg.h	4676;"	d
+GET_RG_SX_VCOBA_R	include/ssv6200_reg.h	4681;"	d
+GET_RG_SX_VCOBFSEL	include/ssv6200_reg.h	4686;"	d
+GET_RG_SX_VCOCUSEL	include/ssv6200_reg.h	4683;"	d
+GET_RG_SX_VCORSEL	include/ssv6200_reg.h	4682;"	d
+GET_RG_SX_VCO_CS_AWH	smac/hal/ssv6006c/ssv6006C_reg.h	6859;"	d
+GET_RG_SX_VCO_ISEL_BT	smac/hal/ssv6006c/ssv6006C_reg.h	6849;"	d
+GET_RG_SX_VCO_ISEL_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	6848;"	d
+GET_RG_SX_VCO_ISEL_WF	smac/hal/ssv6006c/ssv6006C_reg.h	6853;"	d
+GET_RG_SX_VCO_KVDOUB_BT	smac/hal/ssv6006c/ssv6006C_reg.h	6852;"	d
+GET_RG_SX_VCO_KVDOUB_WF	smac/hal/ssv6006c/ssv6006C_reg.h	6856;"	d
+GET_RG_SX_VCO_LPM_BT	smac/hal/ssv6006c/ssv6006C_reg.h	6850;"	d
+GET_RG_SX_VCO_LPM_WF	smac/hal/ssv6006c/ssv6006C_reg.h	6854;"	d
+GET_RG_SX_VCO_RTAIL_SHIFT	smac/hal/ssv6006c/ssv6006C_reg.h	6858;"	d
+GET_RG_SX_VCO_RXOB_AW	smac/hal/ssv6006c/ssv6006C_reg.h	6870;"	d
+GET_RG_SX_VCO_TXOB_AW	smac/hal/ssv6006c/ssv6006C_reg.h	6869;"	d
+GET_RG_SX_VCO_VARBSEL	smac/hal/ssv6006c/ssv6006C_reg.h	6857;"	d
+GET_RG_SX_VCO_VCCBSEL_BT	smac/hal/ssv6006c/ssv6006C_reg.h	6851;"	d
+GET_RG_SX_VCO_VCCBSEL_WF	smac/hal/ssv6006c/ssv6006C_reg.h	6855;"	d
+GET_RG_SX_VT_MON_MODE	include/ssv6200_reg.h	4702;"	d
+GET_RG_SX_VT_MON_TMR	include/ssv6200_reg.h	4706;"	d
+GET_RG_SX_VT_SET	include/ssv6200_reg.h	4705;"	d
+GET_RG_SX_VT_TH_HI	include/ssv6200_reg.h	4703;"	d
+GET_RG_SX_VT_TH_LO	include/ssv6200_reg.h	4704;"	d
+GET_RG_SX_XO_GM	include/ssv6200_reg.h	4693;"	d
+GET_RG_SX_XTAL_FREQ	smac/hal/ssv6006c/ssv6006C_reg.h	6820;"	d
+GET_RG_SYM_BOUND_CNT	include/ssv6200_reg.h	4222;"	d
+GET_RG_SYM_BOUND_METHOD	include/ssv6200_reg.h	4251;"	d
+GET_RG_SYM_BOUND_METHOD	smac/hal/ssv6006c/ssv6006C_reg.h	8580;"	d
+GET_RG_SYSTEM_BW	smac/hal/ssv6006c/ssv6006C_reg.h	8193;"	d
+GET_RG_TBUS_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	8305;"	d
+GET_RG_TC_BIT_CNT_LMT	include/ssv6200_reg.h	4169;"	d
+GET_RG_TC_BIT_CNT_LMT	smac/hal/ssv6006c/ssv6006C_reg.h	8481;"	d
+GET_RG_THH_ED	smac/hal/ssv6006c/ssv6006C_reg.h	8695;"	d
+GET_RG_THH_RATIO	smac/hal/ssv6006c/ssv6006C_reg.h	8697;"	d
+GET_RG_THL_ED	smac/hal/ssv6006c/ssv6006C_reg.h	8694;"	d
+GET_RG_THL_RATIO	smac/hal/ssv6006c/ssv6006C_reg.h	8696;"	d
+GET_RG_TIME_PERIOD	smac/hal/ssv6006c/ssv6006C_reg.h	8702;"	d
+GET_RG_TOLERANCE_PERIOD	smac/hal/ssv6006c/ssv6006C_reg.h	8707;"	d
+GET_RG_TOLERANCE_PW	smac/hal/ssv6006c/ssv6006C_reg.h	8708;"	d
+GET_RG_TONEGEN2_EN	include/ssv6200_reg.h	4345;"	d
+GET_RG_TONEGEN2_FREQ	include/ssv6200_reg.h	4344;"	d
+GET_RG_TONEGEN2_SCALE	include/ssv6200_reg.h	4346;"	d
+GET_RG_TONEGEN_EN	include/ssv6200_reg.h	4342;"	d
+GET_RG_TONEGEN_FREQ	include/ssv6200_reg.h	4341;"	d
+GET_RG_TONEGEN_INIT_PH	include/ssv6200_reg.h	4343;"	d
+GET_RG_TONE_1_RATE	smac/hal/ssv6006c/ssv6006C_reg.h	7927;"	d
+GET_RG_TONE_GEN_EN	smac/hal/ssv6006c/ssv6006C_reg.h	7599;"	d
+GET_RG_TONE_SCALE	smac/hal/ssv6006c/ssv6006C_reg.h	7597;"	d
+GET_RG_TONE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	7926;"	d
+GET_RG_TRX_DUMMMY	include/ssv6200_reg.h	4771;"	d
+GET_RG_TR_BIT_CNT_LMT	include/ssv6200_reg.h	4171;"	d
+GET_RG_TR_BIT_CNT_LMT	smac/hal/ssv6006c/ssv6006C_reg.h	8483;"	d
+GET_RG_TR_CNT_T0	include/ssv6200_reg.h	4214;"	d
+GET_RG_TR_CNT_T1	include/ssv6200_reg.h	4211;"	d
+GET_RG_TR_CNT_T2	include/ssv6200_reg.h	4217;"	d
+GET_RG_TR_CNT_UPDATE	include/ssv6200_reg.h	4265;"	d
+GET_RG_TR_CNT_UPDATE	smac/hal/ssv6006c/ssv6006C_reg.h	8640;"	d
+GET_RG_TR_CNT_UPDATE_SGI	smac/hal/ssv6006c/ssv6006C_reg.h	8638;"	d
+GET_RG_TR_KI_T1	include/ssv6200_reg.h	4137;"	d
+GET_RG_TR_KI_T1	smac/hal/ssv6006c/ssv6006C_reg.h	8455;"	d
+GET_RG_TR_KI_T2	include/ssv6200_reg.h	4135;"	d
+GET_RG_TR_KI_T2	smac/hal/ssv6006c/ssv6006C_reg.h	8453;"	d
+GET_RG_TR_KP_T1	include/ssv6200_reg.h	4138;"	d
+GET_RG_TR_KP_T1	smac/hal/ssv6006c/ssv6006C_reg.h	8456;"	d
+GET_RG_TR_KP_T2	include/ssv6200_reg.h	4136;"	d
+GET_RG_TR_KP_T2	smac/hal/ssv6006c/ssv6006C_reg.h	8454;"	d
+GET_RG_TR_LPF_KI_G	include/ssv6200_reg.h	4218;"	d
+GET_RG_TR_LPF_KI_G_T0	include/ssv6200_reg.h	4212;"	d
+GET_RG_TR_LPF_KI_G_T1	include/ssv6200_reg.h	4209;"	d
+GET_RG_TR_LPF_KI_G_T2	include/ssv6200_reg.h	4215;"	d
+GET_RG_TR_LPF_KP_G	include/ssv6200_reg.h	4219;"	d
+GET_RG_TR_LPF_KP_G_T0	include/ssv6200_reg.h	4213;"	d
+GET_RG_TR_LPF_KP_G_T1	include/ssv6200_reg.h	4210;"	d
+GET_RG_TR_LPF_KP_G_T2	include/ssv6200_reg.h	4216;"	d
+GET_RG_TR_LPF_RATE	include/ssv6200_reg.h	4166;"	d
+GET_RG_TR_LPF_RATE	smac/hal/ssv6006c/ssv6006C_reg.h	8478;"	d
+GET_RG_TR_LPF_RATE_G	include/ssv6200_reg.h	4220;"	d
+GET_RG_TR_LPF_RATE_GN	smac/hal/ssv6006c/ssv6006C_reg.h	8549;"	d
+GET_RG_TR_LPF_STBC_GF_KI_G	include/ssv6200_reg.h	4281;"	d
+GET_RG_TR_LPF_STBC_GF_KP_G	include/ssv6200_reg.h	4282;"	d
+GET_RG_TR_LPF_STBC_MF_KI_G	include/ssv6200_reg.h	4283;"	d
+GET_RG_TR_LPF_STBC_MF_KP_G	include/ssv6200_reg.h	4284;"	d
+GET_RG_TST_ADC_ON	include/ssv6200_reg.h	4018;"	d
+GET_RG_TST_EXT_GAIN	include/ssv6200_reg.h	4019;"	d
+GET_RG_TST_TBUS_SEL	include/ssv6200_reg.h	4015;"	d
+GET_RG_TURISMO_TRX_40M_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	6174;"	d
+GET_RG_TURISMO_TRX_5G_EN_IREF_RX	smac/hal/ssv6006c/ssv6006C_reg.h	5786;"	d
+GET_RG_TURISMO_TRX_5G_EN_LDO_RX_FE	smac/hal/ssv6006c/ssv6006C_reg.h	5785;"	d
+GET_RG_TURISMO_TRX_5G_EN_LDO_RX_FE_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	5777;"	d
+GET_RG_TURISMO_TRX_5G_EN_LDO_RX_FE_FC	smac/hal/ssv6006c/ssv6006C_reg.h	5787;"	d
+GET_RG_TURISMO_TRX_5G_EN_LDO_RX_FE_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	5788;"	d
+GET_RG_TURISMO_TRX_5G_EN_RX_DIV2	smac/hal/ssv6006c/ssv6006C_reg.h	5754;"	d
+GET_RG_TURISMO_TRX_5G_EN_RX_IQCAL	smac/hal/ssv6006c/ssv6006C_reg.h	5772;"	d
+GET_RG_TURISMO_TRX_5G_EN_RX_LNA	smac/hal/ssv6006c/ssv6006C_reg.h	5750;"	d
+GET_RG_TURISMO_TRX_5G_EN_RX_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	5756;"	d
+GET_RG_TURISMO_TRX_5G_EN_RX_MIXER	smac/hal/ssv6006c/ssv6006C_reg.h	5752;"	d
+GET_RG_TURISMO_TRX_5G_EN_RX_TZ	smac/hal/ssv6006c/ssv6006C_reg.h	5758;"	d
+GET_RG_TURISMO_TRX_5G_EN_TX_DIV2	smac/hal/ssv6006c/ssv6006C_reg.h	5764;"	d
+GET_RG_TURISMO_TRX_5G_EN_TX_DIV2_BUF	smac/hal/ssv6006c/ssv6006C_reg.h	5766;"	d
+GET_RG_TURISMO_TRX_5G_EN_TX_DPD	smac/hal/ssv6006c/ssv6006C_reg.h	5774;"	d
+GET_RG_TURISMO_TRX_5G_EN_TX_MOD	smac/hal/ssv6006c/ssv6006C_reg.h	5762;"	d
+GET_RG_TURISMO_TRX_5G_EN_TX_PA	smac/hal/ssv6006c/ssv6006C_reg.h	5760;"	d
+GET_RG_TURISMO_TRX_5G_EN_TX_SELF_MIXER	smac/hal/ssv6006c/ssv6006C_reg.h	5770;"	d
+GET_RG_TURISMO_TRX_5G_EN_TX_TRSW	smac/hal/ssv6006c/ssv6006C_reg.h	5748;"	d
+GET_RG_TURISMO_TRX_5G_EN_TX_TSSI	smac/hal/ssv6006c/ssv6006C_reg.h	5775;"	d
+GET_RG_TURISMO_TRX_5G_GM_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	5795;"	d
+GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE0	smac/hal/ssv6006c/ssv6006C_reg.h	6100;"	d
+GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE1	smac/hal/ssv6006c/ssv6006C_reg.h	6098;"	d
+GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE2	smac/hal/ssv6006c/ssv6006C_reg.h	6096;"	d
+GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE3	smac/hal/ssv6006c/ssv6006C_reg.h	6094;"	d
+GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE4	smac/hal/ssv6006c/ssv6006C_reg.h	6092;"	d
+GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	6058;"	d
+GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	6056;"	d
+GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	6038;"	d
+GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	6036;"	d
+GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	6034;"	d
+GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	6032;"	d
+GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	6030;"	d
+GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	6028;"	d
+GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	6054;"	d
+GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	6052;"	d
+GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	6050;"	d
+GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	6048;"	d
+GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	6046;"	d
+GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	6044;"	d
+GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	6042;"	d
+GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	6040;"	d
+GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE0	smac/hal/ssv6006c/ssv6006C_reg.h	6110;"	d
+GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE1	smac/hal/ssv6006c/ssv6006C_reg.h	6108;"	d
+GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE2	smac/hal/ssv6006c/ssv6006C_reg.h	6106;"	d
+GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE3	smac/hal/ssv6006c/ssv6006C_reg.h	6104;"	d
+GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE4	smac/hal/ssv6006c/ssv6006C_reg.h	6102;"	d
+GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	6090;"	d
+GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	6088;"	d
+GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	6070;"	d
+GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	6068;"	d
+GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	6066;"	d
+GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	6064;"	d
+GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	6062;"	d
+GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	6060;"	d
+GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	6086;"	d
+GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	6084;"	d
+GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	6082;"	d
+GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	6080;"	d
+GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	6078;"	d
+GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	6076;"	d
+GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	6074;"	d
+GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	6072;"	d
+GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE0	smac/hal/ssv6006c/ssv6006C_reg.h	6101;"	d
+GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE1	smac/hal/ssv6006c/ssv6006C_reg.h	6099;"	d
+GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE2	smac/hal/ssv6006c/ssv6006C_reg.h	6097;"	d
+GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE3	smac/hal/ssv6006c/ssv6006C_reg.h	6095;"	d
+GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE4	smac/hal/ssv6006c/ssv6006C_reg.h	6093;"	d
+GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	6059;"	d
+GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	6057;"	d
+GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	6039;"	d
+GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	6037;"	d
+GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	6035;"	d
+GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	6033;"	d
+GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	6031;"	d
+GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	6029;"	d
+GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	6055;"	d
+GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	6053;"	d
+GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	6051;"	d
+GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	6049;"	d
+GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	6047;"	d
+GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	6045;"	d
+GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	6043;"	d
+GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	6041;"	d
+GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE0	smac/hal/ssv6006c/ssv6006C_reg.h	6111;"	d
+GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE1	smac/hal/ssv6006c/ssv6006C_reg.h	6109;"	d
+GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE2	smac/hal/ssv6006c/ssv6006C_reg.h	6107;"	d
+GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE3	smac/hal/ssv6006c/ssv6006C_reg.h	6105;"	d
+GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE4	smac/hal/ssv6006c/ssv6006C_reg.h	6103;"	d
+GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	6091;"	d
+GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	6089;"	d
+GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	6071;"	d
+GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	6069;"	d
+GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	6067;"	d
+GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	6065;"	d
+GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	6063;"	d
+GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	6061;"	d
+GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	6087;"	d
+GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	6085;"	d
+GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	6083;"	d
+GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	6081;"	d
+GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	6079;"	d
+GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	6077;"	d
+GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	6075;"	d
+GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	6073;"	d
+GET_RG_TURISMO_TRX_5G_LDO_LEVEL_RX_FE	smac/hal/ssv6006c/ssv6006C_reg.h	5776;"	d
+GET_RG_TURISMO_TRX_5G_PABIAS_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	5814;"	d
+GET_RG_TURISMO_TRX_5G_PACELL_EN	smac/hal/ssv6006c/ssv6006C_reg.h	5813;"	d
+GET_RG_TURISMO_TRX_5G_PGAG_DPDCAL	smac/hal/ssv6006c/ssv6006C_reg.h	6136;"	d
+GET_RG_TURISMO_TRX_5G_PGAG_RCCAL	smac/hal/ssv6006c/ssv6006C_reg.h	6131;"	d
+GET_RG_TURISMO_TRX_5G_PGAG_RXIQCAL	smac/hal/ssv6006c/ssv6006C_reg.h	6133;"	d
+GET_RG_TURISMO_TRX_5G_PGAG_TXCAL	smac/hal/ssv6006c/ssv6006C_reg.h	6129;"	d
+GET_RG_TURISMO_TRX_5G_RFG_DPDCAL	smac/hal/ssv6006c/ssv6006C_reg.h	6135;"	d
+GET_RG_TURISMO_TRX_5G_RFG_RXIQCAL	smac/hal/ssv6006c/ssv6006C_reg.h	6132;"	d
+GET_RG_TURISMO_TRX_5G_RXRF_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	6116;"	d
+GET_RG_TURISMO_TRX_5G_RXRF_R2T_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	6124;"	d
+GET_RG_TURISMO_TRX_5G_RXRF_T2R_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	6120;"	d
+GET_RG_TURISMO_TRX_5G_RX_ADC_CLOAD	smac/hal/ssv6006c/ssv6006C_reg.h	5809;"	d
+GET_RG_TURISMO_TRX_5G_RX_ADC_ICMP	smac/hal/ssv6006c/ssv6006C_reg.h	5807;"	d
+GET_RG_TURISMO_TRX_5G_RX_ADC_VCMI	smac/hal/ssv6006c/ssv6006C_reg.h	5808;"	d
+GET_RG_TURISMO_TRX_5G_RX_DCCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	6125;"	d
+GET_RG_TURISMO_TRX_5G_RX_DIV2_BUF	smac/hal/ssv6006c/ssv6006C_reg.h	5796;"	d
+GET_RG_TURISMO_TRX_5G_RX_DIV2_CML	smac/hal/ssv6006c/ssv6006C_reg.h	5797;"	d
+GET_RG_TURISMO_TRX_5G_RX_DIV2_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	5753;"	d
+GET_RG_TURISMO_TRX_5G_RX_DIV_CMLISEL	smac/hal/ssv6006c/ssv6006C_reg.h	5798;"	d
+GET_RG_TURISMO_TRX_5G_RX_DIV_PREBUFS2	smac/hal/ssv6006c/ssv6006C_reg.h	5799;"	d
+GET_RG_TURISMO_TRX_5G_RX_GM_IDB	smac/hal/ssv6006c/ssv6006C_reg.h	5794;"	d
+GET_RG_TURISMO_TRX_5G_RX_HG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	5836;"	d
+GET_RG_TURISMO_TRX_5G_RX_HG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	5831;"	d
+GET_RG_TURISMO_TRX_5G_RX_HG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	5832;"	d
+GET_RG_TURISMO_TRX_5G_RX_HG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	5833;"	d
+GET_RG_TURISMO_TRX_5G_RX_HG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	5829;"	d
+GET_RG_TURISMO_TRX_5G_RX_HG_SQDC	smac/hal/ssv6006c/ssv6006C_reg.h	5835;"	d
+GET_RG_TURISMO_TRX_5G_RX_HG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	5838;"	d
+GET_RG_TURISMO_TRX_5G_RX_HG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	5834;"	d
+GET_RG_TURISMO_TRX_5G_RX_HG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	5830;"	d
+GET_RG_TURISMO_TRX_5G_RX_HG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	5837;"	d
+GET_RG_TURISMO_TRX_5G_RX_HG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	5839;"	d
+GET_RG_TURISMO_TRX_5G_RX_IQCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	6128;"	d
+GET_RG_TURISMO_TRX_5G_RX_IQCAL_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	5771;"	d
+GET_RG_TURISMO_TRX_5G_RX_LG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	5858;"	d
+GET_RG_TURISMO_TRX_5G_RX_LG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	5853;"	d
+GET_RG_TURISMO_TRX_5G_RX_LG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	5854;"	d
+GET_RG_TURISMO_TRX_5G_RX_LG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	5855;"	d
+GET_RG_TURISMO_TRX_5G_RX_LG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	5851;"	d
+GET_RG_TURISMO_TRX_5G_RX_LG_SQDC	smac/hal/ssv6006c/ssv6006C_reg.h	5857;"	d
+GET_RG_TURISMO_TRX_5G_RX_LG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	5860;"	d
+GET_RG_TURISMO_TRX_5G_RX_LG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	5856;"	d
+GET_RG_TURISMO_TRX_5G_RX_LG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	5852;"	d
+GET_RG_TURISMO_TRX_5G_RX_LG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	5859;"	d
+GET_RG_TURISMO_TRX_5G_RX_LG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	5861;"	d
+GET_RG_TURISMO_TRX_5G_RX_LNA_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	5749;"	d
+GET_RG_TURISMO_TRX_5G_RX_LNA_SETTLE	smac/hal/ssv6006c/ssv6006C_reg.h	5793;"	d
+GET_RG_TURISMO_TRX_5G_RX_LNA_TRI_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	5792;"	d
+GET_RG_TURISMO_TRX_5G_RX_LOBUF_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	5755;"	d
+GET_RG_TURISMO_TRX_5G_RX_MG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	5847;"	d
+GET_RG_TURISMO_TRX_5G_RX_MG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	5842;"	d
+GET_RG_TURISMO_TRX_5G_RX_MG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	5843;"	d
+GET_RG_TURISMO_TRX_5G_RX_MG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	5844;"	d
+GET_RG_TURISMO_TRX_5G_RX_MG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	5840;"	d
+GET_RG_TURISMO_TRX_5G_RX_MG_SQDC	smac/hal/ssv6006c/ssv6006C_reg.h	5846;"	d
+GET_RG_TURISMO_TRX_5G_RX_MG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	5849;"	d
+GET_RG_TURISMO_TRX_5G_RX_MG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	5845;"	d
+GET_RG_TURISMO_TRX_5G_RX_MG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	5841;"	d
+GET_RG_TURISMO_TRX_5G_RX_MG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	5848;"	d
+GET_RG_TURISMO_TRX_5G_RX_MG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	5850;"	d
+GET_RG_TURISMO_TRX_5G_RX_MIXER_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	5751;"	d
+GET_RG_TURISMO_TRX_5G_RX_SCA_LOAD	smac/hal/ssv6006c/ssv6006C_reg.h	5791;"	d
+GET_RG_TURISMO_TRX_5G_RX_SCA_MA	smac/hal/ssv6006c/ssv6006C_reg.h	5790;"	d
+GET_RG_TURISMO_TRX_5G_RX_SCA_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	5789;"	d
+GET_RG_TURISMO_TRX_5G_RX_TZ_COURSE	smac/hal/ssv6006c/ssv6006C_reg.h	5800;"	d
+GET_RG_TURISMO_TRX_5G_RX_TZ_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	5757;"	d
+GET_RG_TURISMO_TRX_5G_RX_TZ_OUT_TRISTATE	smac/hal/ssv6006c/ssv6006C_reg.h	5768;"	d
+GET_RG_TURISMO_TRX_5G_RX_TZ_OUT_TRISTATE_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	5767;"	d
+GET_RG_TURISMO_TRX_5G_RX_ULG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	5869;"	d
+GET_RG_TURISMO_TRX_5G_RX_ULG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	5864;"	d
+GET_RG_TURISMO_TRX_5G_RX_ULG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	5865;"	d
+GET_RG_TURISMO_TRX_5G_RX_ULG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	5866;"	d
+GET_RG_TURISMO_TRX_5G_RX_ULG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	5862;"	d
+GET_RG_TURISMO_TRX_5G_RX_ULG_SQDC	smac/hal/ssv6006c/ssv6006C_reg.h	5868;"	d
+GET_RG_TURISMO_TRX_5G_RX_ULG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	5871;"	d
+GET_RG_TURISMO_TRX_5G_RX_ULG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	5867;"	d
+GET_RG_TURISMO_TRX_5G_RX_ULG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	5863;"	d
+GET_RG_TURISMO_TRX_5G_RX_ULG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	5870;"	d
+GET_RG_TURISMO_TRX_5G_RX_ULG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	5872;"	d
+GET_RG_TURISMO_TRX_5G_TXDAC_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	6113;"	d
+GET_RG_TURISMO_TRX_5G_TXDAC_R2T_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	6121;"	d
+GET_RG_TURISMO_TRX_5G_TXDAC_T2R_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	6117;"	d
+GET_RG_TURISMO_TRX_5G_TXLPF_BOOSTI	smac/hal/ssv6006c/ssv6006C_reg.h	5879;"	d
+GET_RG_TURISMO_TRX_5G_TXMOD_GMCELL	smac/hal/ssv6006c/ssv6006C_reg.h	5826;"	d
+GET_RG_TURISMO_TRX_5G_TXPA_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	6115;"	d
+GET_RG_TURISMO_TRX_5G_TXPA_R2T_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	6123;"	d
+GET_RG_TURISMO_TRX_5G_TXPA_T2R_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	6119;"	d
+GET_RG_TURISMO_TRX_5G_TXPGA_CAPSW	smac/hal/ssv6006c/ssv6006C_reg.h	5811;"	d
+GET_RG_TURISMO_TRX_5G_TXPGA_CAPSW_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	5810;"	d
+GET_RG_TURISMO_TRX_5G_TXPGA_MAIN	smac/hal/ssv6006c/ssv6006C_reg.h	5824;"	d
+GET_RG_TURISMO_TRX_5G_TXPGA_STEER	smac/hal/ssv6006c/ssv6006C_reg.h	5825;"	d
+GET_RG_TURISMO_TRX_5G_TXRF_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	6114;"	d
+GET_RG_TURISMO_TRX_5G_TXRF_R2T_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	6122;"	d
+GET_RG_TURISMO_TRX_5G_TXRF_T2R_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	6118;"	d
+GET_RG_TURISMO_TRX_5G_TX_ADDGMCELL	smac/hal/ssv6006c/ssv6006C_reg.h	5812;"	d
+GET_RG_TURISMO_TRX_5G_TX_DACI1ST	smac/hal/ssv6006c/ssv6006C_reg.h	5873;"	d
+GET_RG_TURISMO_TRX_5G_TX_DACLPF_ICOARSE	smac/hal/ssv6006c/ssv6006C_reg.h	5874;"	d
+GET_RG_TURISMO_TRX_5G_TX_DACLPF_IFINE	smac/hal/ssv6006c/ssv6006C_reg.h	5875;"	d
+GET_RG_TURISMO_TRX_5G_TX_DACLPF_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	5876;"	d
+GET_RG_TURISMO_TRX_5G_TX_DAC_CKEDGE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	5881;"	d
+GET_RG_TURISMO_TRX_5G_TX_DAC_IATTN	smac/hal/ssv6006c/ssv6006C_reg.h	5878;"	d
+GET_RG_TURISMO_TRX_5G_TX_DAC_IBIAS	smac/hal/ssv6006c/ssv6006C_reg.h	5877;"	d
+GET_RG_TURISMO_TRX_5G_TX_DAC_IOFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	5883;"	d
+GET_RG_TURISMO_TRX_5G_TX_DAC_OS	smac/hal/ssv6006c/ssv6006C_reg.h	5882;"	d
+GET_RG_TURISMO_TRX_5G_TX_DAC_QOFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	5884;"	d
+GET_RG_TURISMO_TRX_5G_TX_DAC_RCAL	smac/hal/ssv6006c/ssv6006C_reg.h	5880;"	d
+GET_RG_TURISMO_TRX_5G_TX_DCCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	6126;"	d
+GET_RG_TURISMO_TRX_5G_TX_DIV2_BUF_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	5765;"	d
+GET_RG_TURISMO_TRX_5G_TX_DIV2_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	5763;"	d
+GET_RG_TURISMO_TRX_5G_TX_DIV_CMLISEL	smac/hal/ssv6006c/ssv6006C_reg.h	5820;"	d
+GET_RG_TURISMO_TRX_5G_TX_DIV_CMLVSEL	smac/hal/ssv6006c/ssv6006C_reg.h	5821;"	d
+GET_RG_TURISMO_TRX_5G_TX_DIV_PREBUFS2	smac/hal/ssv6006c/ssv6006C_reg.h	5819;"	d
+GET_RG_TURISMO_TRX_5G_TX_DIV_VSET	smac/hal/ssv6006c/ssv6006C_reg.h	5822;"	d
+GET_RG_TURISMO_TRX_5G_TX_DPDGM_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	5801;"	d
+GET_RG_TURISMO_TRX_5G_TX_DPD_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	5802;"	d
+GET_RG_TURISMO_TRX_5G_TX_DPD_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	5773;"	d
+GET_RG_TURISMO_TRX_5G_TX_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	5828;"	d
+GET_RG_TURISMO_TRX_5G_TX_GAIN_DPDCAL	smac/hal/ssv6006c/ssv6006C_reg.h	6137;"	d
+GET_RG_TURISMO_TRX_5G_TX_GAIN_OFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	5827;"	d
+GET_RG_TURISMO_TRX_5G_TX_GAIN_RXIQCAL	smac/hal/ssv6006c/ssv6006C_reg.h	6134;"	d
+GET_RG_TURISMO_TRX_5G_TX_GAIN_TXCAL	smac/hal/ssv6006c/ssv6006C_reg.h	6130;"	d
+GET_RG_TURISMO_TRX_5G_TX_IQCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	6127;"	d
+GET_RG_TURISMO_TRX_5G_TX_LOBUF_VSET	smac/hal/ssv6006c/ssv6006C_reg.h	5823;"	d
+GET_RG_TURISMO_TRX_5G_TX_MOD_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	5761;"	d
+GET_RG_TURISMO_TRX_5G_TX_PA1_VCAS	smac/hal/ssv6006c/ssv6006C_reg.h	5816;"	d
+GET_RG_TURISMO_TRX_5G_TX_PA2_VCAS	smac/hal/ssv6006c/ssv6006C_reg.h	5817;"	d
+GET_RG_TURISMO_TRX_5G_TX_PA3_VCAS	smac/hal/ssv6006c/ssv6006C_reg.h	5818;"	d
+GET_RG_TURISMO_TRX_5G_TX_PAFB_EN	smac/hal/ssv6006c/ssv6006C_reg.h	5815;"	d
+GET_RG_TURISMO_TRX_5G_TX_PA_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	5759;"	d
+GET_RG_TURISMO_TRX_5G_TX_SELF_MIXER_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	5769;"	d
+GET_RG_TURISMO_TRX_5G_TX_TRSW_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	5747;"	d
+GET_RG_TURISMO_TRX_5G_TX_TSSI_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	5803;"	d
+GET_RG_TURISMO_TRX_5G_TX_TSSI_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	5804;"	d
+GET_RG_TURISMO_TRX_5G_TX_TSSI_TEST	smac/hal/ssv6006c/ssv6006C_reg.h	5805;"	d
+GET_RG_TURISMO_TRX_5G_TX_TSSI_TESTMODE	smac/hal/ssv6006c/ssv6006C_reg.h	5806;"	d
+GET_RG_TURISMO_TRX_AAC5GB_PDSW_EN_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	6016;"	d
+GET_RG_TURISMO_TRX_AAC5GB_TAR_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	6015;"	d
+GET_RG_TURISMO_TRX_ADC_EDGE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	6185;"	d
+GET_RG_TURISMO_TRX_ALPHA_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	6224;"	d
+GET_RG_TURISMO_TRX_BB_SIG_EN	smac/hal/ssv6006c/ssv6006C_reg.h	6197;"	d
+GET_RG_TURISMO_TRX_BT_CLK32K_CAL_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	6351;"	d
+GET_RG_TURISMO_TRX_BT_CLK_SW	smac/hal/ssv6006c/ssv6006C_reg.h	6350;"	d
+GET_RG_TURISMO_TRX_BT_EN_TX_PA_VIN33	smac/hal/ssv6006c/ssv6006C_reg.h	5214;"	d
+GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	5661;"	d
+GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	5659;"	d
+GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	5641;"	d
+GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	5639;"	d
+GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	5637;"	d
+GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	5635;"	d
+GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	5633;"	d
+GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	5631;"	d
+GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	5657;"	d
+GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	5655;"	d
+GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	5653;"	d
+GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	5651;"	d
+GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	5649;"	d
+GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	5647;"	d
+GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	5645;"	d
+GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	5643;"	d
+GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	5693;"	d
+GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	5691;"	d
+GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	5673;"	d
+GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	5671;"	d
+GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	5669;"	d
+GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	5667;"	d
+GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	5665;"	d
+GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	5663;"	d
+GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	5689;"	d
+GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	5687;"	d
+GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	5685;"	d
+GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	5683;"	d
+GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	5681;"	d
+GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	5679;"	d
+GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	5677;"	d
+GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	5675;"	d
+GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	5662;"	d
+GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	5660;"	d
+GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	5642;"	d
+GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	5640;"	d
+GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	5638;"	d
+GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	5636;"	d
+GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	5634;"	d
+GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	5632;"	d
+GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	5658;"	d
+GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	5656;"	d
+GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	5654;"	d
+GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	5652;"	d
+GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	5650;"	d
+GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	5648;"	d
+GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	5646;"	d
+GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	5644;"	d
+GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	5694;"	d
+GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	5692;"	d
+GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	5674;"	d
+GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	5672;"	d
+GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	5670;"	d
+GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	5668;"	d
+GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	5666;"	d
+GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	5664;"	d
+GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	5690;"	d
+GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	5688;"	d
+GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	5686;"	d
+GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	5684;"	d
+GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	5682;"	d
+GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	5680;"	d
+GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	5678;"	d
+GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	5676;"	d
+GET_RG_TURISMO_TRX_BT_PABIAS_2X	smac/hal/ssv6006c/ssv6006C_reg.h	5225;"	d
+GET_RG_TURISMO_TRX_BT_PABIAS_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	5226;"	d
+GET_RG_TURISMO_TRX_BT_RX_ABBCFIX	smac/hal/ssv6006c/ssv6006C_reg.h	5183;"	d
+GET_RG_TURISMO_TRX_BT_RX_ABBCTUNE	smac/hal/ssv6006c/ssv6006C_reg.h	5178;"	d
+GET_RG_TURISMO_TRX_BT_RX_ABB_BT_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	5185;"	d
+GET_RG_TURISMO_TRX_BT_RX_ABB_IDIV3	smac/hal/ssv6006c/ssv6006C_reg.h	5186;"	d
+GET_RG_TURISMO_TRX_BT_RX_ABB_N_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	5184;"	d
+GET_RG_TURISMO_TRX_BT_RX_ADC_CLOAD	smac/hal/ssv6006c/ssv6006C_reg.h	5337;"	d
+GET_RG_TURISMO_TRX_BT_RX_ADC_ICMP	smac/hal/ssv6006c/ssv6006C_reg.h	5335;"	d
+GET_RG_TURISMO_TRX_BT_RX_ADC_VCMI	smac/hal/ssv6006c/ssv6006C_reg.h	5336;"	d
+GET_RG_TURISMO_TRX_BT_RX_DCCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	5710;"	d
+GET_RG_TURISMO_TRX_BT_RX_EN_IDACA_COARSE	smac/hal/ssv6006c/ssv6006C_reg.h	5187;"	d
+GET_RG_TURISMO_TRX_BT_RX_EN_LOOPA	smac/hal/ssv6006c/ssv6006C_reg.h	5188;"	d
+GET_RG_TURISMO_TRX_BT_RX_FILTERI1ST	smac/hal/ssv6006c/ssv6006C_reg.h	5180;"	d
+GET_RG_TURISMO_TRX_BT_RX_FILTERI2ND	smac/hal/ssv6006c/ssv6006C_reg.h	5181;"	d
+GET_RG_TURISMO_TRX_BT_RX_FILTERI3RD	smac/hal/ssv6006c/ssv6006C_reg.h	5182;"	d
+GET_RG_TURISMO_TRX_BT_RX_FILTERI_COARSE	smac/hal/ssv6006c/ssv6006C_reg.h	5179;"	d
+GET_RG_TURISMO_TRX_BT_RX_FILTERVCM	smac/hal/ssv6006c/ssv6006C_reg.h	5189;"	d
+GET_RG_TURISMO_TRX_BT_RX_HG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	5290;"	d
+GET_RG_TURISMO_TRX_BT_RX_HG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	5285;"	d
+GET_RG_TURISMO_TRX_BT_RX_HG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	5286;"	d
+GET_RG_TURISMO_TRX_BT_RX_HG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	5287;"	d
+GET_RG_TURISMO_TRX_BT_RX_HG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	5283;"	d
+GET_RG_TURISMO_TRX_BT_RX_HG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	5291;"	d
+GET_RG_TURISMO_TRX_BT_RX_HG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	5292;"	d
+GET_RG_TURISMO_TRX_BT_RX_HG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	5288;"	d
+GET_RG_TURISMO_TRX_BT_RX_HG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	5284;"	d
+GET_RG_TURISMO_TRX_BT_RX_HG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	5289;"	d
+GET_RG_TURISMO_TRX_BT_RX_HG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	5293;"	d
+GET_RG_TURISMO_TRX_BT_RX_LG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	5312;"	d
+GET_RG_TURISMO_TRX_BT_RX_LG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	5307;"	d
+GET_RG_TURISMO_TRX_BT_RX_LG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	5308;"	d
+GET_RG_TURISMO_TRX_BT_RX_LG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	5309;"	d
+GET_RG_TURISMO_TRX_BT_RX_LG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	5305;"	d
+GET_RG_TURISMO_TRX_BT_RX_LG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	5313;"	d
+GET_RG_TURISMO_TRX_BT_RX_LG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	5314;"	d
+GET_RG_TURISMO_TRX_BT_RX_LG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	5310;"	d
+GET_RG_TURISMO_TRX_BT_RX_LG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	5306;"	d
+GET_RG_TURISMO_TRX_BT_RX_LG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	5311;"	d
+GET_RG_TURISMO_TRX_BT_RX_LG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	5315;"	d
+GET_RG_TURISMO_TRX_BT_RX_MG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	5301;"	d
+GET_RG_TURISMO_TRX_BT_RX_MG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	5296;"	d
+GET_RG_TURISMO_TRX_BT_RX_MG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	5297;"	d
+GET_RG_TURISMO_TRX_BT_RX_MG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	5298;"	d
+GET_RG_TURISMO_TRX_BT_RX_MG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	5294;"	d
+GET_RG_TURISMO_TRX_BT_RX_MG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	5302;"	d
+GET_RG_TURISMO_TRX_BT_RX_MG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	5303;"	d
+GET_RG_TURISMO_TRX_BT_RX_MG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	5299;"	d
+GET_RG_TURISMO_TRX_BT_RX_MG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	5295;"	d
+GET_RG_TURISMO_TRX_BT_RX_MG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	5300;"	d
+GET_RG_TURISMO_TRX_BT_RX_MG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	5304;"	d
+GET_RG_TURISMO_TRX_BT_RX_OUTVCM	smac/hal/ssv6006c/ssv6006C_reg.h	5190;"	d
+GET_RG_TURISMO_TRX_BT_RX_ULG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	5323;"	d
+GET_RG_TURISMO_TRX_BT_RX_ULG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	5318;"	d
+GET_RG_TURISMO_TRX_BT_RX_ULG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	5319;"	d
+GET_RG_TURISMO_TRX_BT_RX_ULG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	5320;"	d
+GET_RG_TURISMO_TRX_BT_RX_ULG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	5316;"	d
+GET_RG_TURISMO_TRX_BT_RX_ULG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	5324;"	d
+GET_RG_TURISMO_TRX_BT_RX_ULG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	5325;"	d
+GET_RG_TURISMO_TRX_BT_RX_ULG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	5321;"	d
+GET_RG_TURISMO_TRX_BT_RX_ULG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	5317;"	d
+GET_RG_TURISMO_TRX_BT_RX_ULG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	5322;"	d
+GET_RG_TURISMO_TRX_BT_RX_ULG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	5326;"	d
+GET_RG_TURISMO_TRX_BT_TRX_IF	smac/hal/ssv6006c/ssv6006C_reg.h	6176;"	d
+GET_RG_TURISMO_TRX_BT_TXLPF_BOOSTI	smac/hal/ssv6006c/ssv6006C_reg.h	5363;"	d
+GET_RG_TURISMO_TRX_BT_TXPGA_CAPSW	smac/hal/ssv6006c/ssv6006C_reg.h	5210;"	d
+GET_RG_TURISMO_TRX_BT_TX_BTPASW	smac/hal/ssv6006c/ssv6006C_reg.h	5213;"	d
+GET_RG_TURISMO_TRX_BT_TX_DACI1ST	smac/hal/ssv6006c/ssv6006C_reg.h	5357;"	d
+GET_RG_TURISMO_TRX_BT_TX_DACLPF_ICOARSE	smac/hal/ssv6006c/ssv6006C_reg.h	5358;"	d
+GET_RG_TURISMO_TRX_BT_TX_DACLPF_IFINE	smac/hal/ssv6006c/ssv6006C_reg.h	5359;"	d
+GET_RG_TURISMO_TRX_BT_TX_DACLPF_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	5360;"	d
+GET_RG_TURISMO_TRX_BT_TX_DAC_CKEDGE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	5365;"	d
+GET_RG_TURISMO_TRX_BT_TX_DAC_IATTN	smac/hal/ssv6006c/ssv6006C_reg.h	5362;"	d
+GET_RG_TURISMO_TRX_BT_TX_DAC_IBIAS	smac/hal/ssv6006c/ssv6006C_reg.h	5361;"	d
+GET_RG_TURISMO_TRX_BT_TX_DAC_IOFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	5367;"	d
+GET_RG_TURISMO_TRX_BT_TX_DAC_OS	smac/hal/ssv6006c/ssv6006C_reg.h	5366;"	d
+GET_RG_TURISMO_TRX_BT_TX_DAC_QOFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	5368;"	d
+GET_RG_TURISMO_TRX_BT_TX_DAC_RCAL	smac/hal/ssv6006c/ssv6006C_reg.h	5364;"	d
+GET_RG_TURISMO_TRX_BT_TX_DIV_VSET	smac/hal/ssv6006c/ssv6006C_reg.h	5211;"	d
+GET_RG_TURISMO_TRX_BT_TX_GAIN_OFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	5234;"	d
+GET_RG_TURISMO_TRX_BT_TX_LOBUF_VSET	smac/hal/ssv6006c/ssv6006C_reg.h	5212;"	d
+GET_RG_TURISMO_TRX_BT_TX_MOD_CS	smac/hal/ssv6006c/ssv6006C_reg.h	5228;"	d
+GET_RG_TURISMO_TRX_BT_TX_PA_VCAS	smac/hal/ssv6006c/ssv6006C_reg.h	5227;"	d
+GET_RG_TURISMO_TRX_BUCK_EN_PSM	smac/hal/ssv6006c/ssv6006C_reg.h	6305;"	d
+GET_RG_TURISMO_TRX_BUCK_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	6303;"	d
+GET_RG_TURISMO_TRX_BUCK_PSM_VTH	smac/hal/ssv6006c/ssv6006C_reg.h	6306;"	d
+GET_RG_TURISMO_TRX_BUCK_RCZERO	smac/hal/ssv6006c/ssv6006C_reg.h	6316;"	d
+GET_RG_TURISMO_TRX_BUCK_SLOP	smac/hal/ssv6006c/ssv6006C_reg.h	6317;"	d
+GET_RG_TURISMO_TRX_BUCK_VREF_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	6307;"	d
+GET_RG_TURISMO_TRX_BW20_HB_COEF_00	smac/hal/ssv6006c/ssv6006C_reg.h	6211;"	d
+GET_RG_TURISMO_TRX_BW20_HB_COEF_01	smac/hal/ssv6006c/ssv6006C_reg.h	6210;"	d
+GET_RG_TURISMO_TRX_BW20_HB_COEF_02	smac/hal/ssv6006c/ssv6006C_reg.h	6213;"	d
+GET_RG_TURISMO_TRX_BW20_HB_COEF_03	smac/hal/ssv6006c/ssv6006C_reg.h	6212;"	d
+GET_RG_TURISMO_TRX_BW20_HB_COEF_04	smac/hal/ssv6006c/ssv6006C_reg.h	6215;"	d
+GET_RG_TURISMO_TRX_BW20_HB_COEF_05	smac/hal/ssv6006c/ssv6006C_reg.h	6214;"	d
+GET_RG_TURISMO_TRX_BW20_HB_COEF_06	smac/hal/ssv6006c/ssv6006C_reg.h	6217;"	d
+GET_RG_TURISMO_TRX_BW20_HB_COEF_07	smac/hal/ssv6006c/ssv6006C_reg.h	6216;"	d
+GET_RG_TURISMO_TRX_BW20_HB_COEF_08	smac/hal/ssv6006c/ssv6006C_reg.h	6219;"	d
+GET_RG_TURISMO_TRX_BW20_HB_COEF_09	smac/hal/ssv6006c/ssv6006C_reg.h	6218;"	d
+GET_RG_TURISMO_TRX_BW20_HB_COEF_10	smac/hal/ssv6006c/ssv6006C_reg.h	6221;"	d
+GET_RG_TURISMO_TRX_BW20_HB_COEF_11	smac/hal/ssv6006c/ssv6006C_reg.h	6220;"	d
+GET_RG_TURISMO_TRX_BW_HT40	smac/hal/ssv6006c/ssv6006C_reg.h	5075;"	d
+GET_RG_TURISMO_TRX_BW_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	5076;"	d
+GET_RG_TURISMO_TRX_CAL_INDEX	smac/hal/ssv6006c/ssv6006C_reg.h	5072;"	d
+GET_RG_TURISMO_TRX_CBW_20_40	smac/hal/ssv6006c/ssv6006C_reg.h	6203;"	d
+GET_RG_TURISMO_TRX_CLK_320M_INV	smac/hal/ssv6006c/ssv6006C_reg.h	6201;"	d
+GET_RG_TURISMO_TRX_CLK_MON_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	6423;"	d
+GET_RG_TURISMO_TRX_CLK_RTC_SW	smac/hal/ssv6006c/ssv6006C_reg.h	6346;"	d
+GET_RG_TURISMO_TRX_CLK_SAR_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	5343;"	d
+GET_RG_TURISMO_TRX_DAC_DC_I	smac/hal/ssv6006c/ssv6006C_reg.h	6205;"	d
+GET_RG_TURISMO_TRX_DAC_DC_Q	smac/hal/ssv6006c/ssv6006C_reg.h	6204;"	d
+GET_RG_TURISMO_TRX_DAC_I_SET	smac/hal/ssv6006c/ssv6006C_reg.h	6208;"	d
+GET_RG_TURISMO_TRX_DAC_MAN_I_EN	smac/hal/ssv6006c/ssv6006C_reg.h	6209;"	d
+GET_RG_TURISMO_TRX_DAC_MAN_Q_EN	smac/hal/ssv6006c/ssv6006C_reg.h	6207;"	d
+GET_RG_TURISMO_TRX_DAC_Q_SET	smac/hal/ssv6006c/ssv6006C_reg.h	6206;"	d
+GET_RG_TURISMO_TRX_DCDC_CLK	smac/hal/ssv6006c/ssv6006C_reg.h	6315;"	d
+GET_RG_TURISMO_TRX_DCDC_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	6301;"	d
+GET_RG_TURISMO_TRX_DCDC_PULLLOW_CON	smac/hal/ssv6006c/ssv6006C_reg.h	6310;"	d
+GET_RG_TURISMO_TRX_DCDC_RES2_CON	smac/hal/ssv6006c/ssv6006C_reg.h	6311;"	d
+GET_RG_TURISMO_TRX_DCDC_RES_CON	smac/hal/ssv6006c/ssv6006C_reg.h	6312;"	d
+GET_RG_TURISMO_TRX_DIS_DAC_OFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	6200;"	d
+GET_RG_TURISMO_TRX_DLDO_BOOST_IQ	smac/hal/ssv6006c/ssv6006C_reg.h	6304;"	d
+GET_RG_TURISMO_TRX_DLDO_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	6302;"	d
+GET_RG_TURISMO_TRX_DPLL_CLK320BY2	smac/hal/ssv6006c/ssv6006C_reg.h	6202;"	d
+GET_RG_TURISMO_TRX_DPL_MOD_ORDER	smac/hal/ssv6006c/ssv6006C_reg.h	5526;"	d
+GET_RG_TURISMO_TRX_DPL_RFCTRL_CH	smac/hal/ssv6006c/ssv6006C_reg.h	5546;"	d
+GET_RG_TURISMO_TRX_DPL_RFCTRL_F	smac/hal/ssv6006c/ssv6006C_reg.h	5545;"	d
+GET_RG_TURISMO_TRX_DPL_SETTLING_TIMMER	smac/hal/ssv6006c/ssv6006C_reg.h	6295;"	d
+GET_RG_TURISMO_TRX_DP_ADC320_DIVBY2_BT	smac/hal/ssv6006c/ssv6006C_reg.h	5523;"	d
+GET_RG_TURISMO_TRX_DP_ADC320_DIVBY2_WF	smac/hal/ssv6006c/ssv6006C_reg.h	5524;"	d
+GET_RG_TURISMO_TRX_DP_BBPLL_BP	smac/hal/ssv6006c/ssv6006C_reg.h	5519;"	d
+GET_RG_TURISMO_TRX_DP_BBPLL_BS	smac/hal/ssv6006c/ssv6006C_reg.h	5543;"	d
+GET_RG_TURISMO_TRX_DP_BBPLL_ICP	smac/hal/ssv6006c/ssv6006C_reg.h	5532;"	d
+GET_RG_TURISMO_TRX_DP_BBPLL_IDUAL	smac/hal/ssv6006c/ssv6006C_reg.h	5533;"	d
+GET_RG_TURISMO_TRX_DP_BBPLL_PD	smac/hal/ssv6006c/ssv6006C_reg.h	5518;"	d
+GET_RG_TURISMO_TRX_DP_BBPLL_PFD_DLY	smac/hal/ssv6006c/ssv6006C_reg.h	5537;"	d
+GET_RG_TURISMO_TRX_DP_BBPLL_SDM_EDGE	smac/hal/ssv6006c/ssv6006C_reg.h	5544;"	d
+GET_RG_TURISMO_TRX_DP_BBPLL_TESTSEL	smac/hal/ssv6006c/ssv6006C_reg.h	5531;"	d
+GET_RG_TURISMO_TRX_DP_CP_IOST	smac/hal/ssv6006c/ssv6006C_reg.h	5535;"	d
+GET_RG_TURISMO_TRX_DP_CP_IOSTPOL	smac/hal/ssv6006c/ssv6006C_reg.h	5534;"	d
+GET_RG_TURISMO_TRX_DP_DAC320_DIVBY2	smac/hal/ssv6006c/ssv6006C_reg.h	5522;"	d
+GET_RG_TURISMO_TRX_DP_FODIV	smac/hal/ssv6006c/ssv6006C_reg.h	5528;"	d
+GET_RG_TURISMO_TRX_DP_FREF_DOUB	smac/hal/ssv6006c/ssv6006C_reg.h	5521;"	d
+GET_RG_TURISMO_TRX_DP_LDO_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	5143;"	d
+GET_RG_TURISMO_TRX_DP_OD_TEST	smac/hal/ssv6006c/ssv6006C_reg.h	5530;"	d
+GET_RG_TURISMO_TRX_DP_PFD_PFDSEL	smac/hal/ssv6006c/ssv6006C_reg.h	5536;"	d
+GET_RG_TURISMO_TRX_DP_REFDIV	smac/hal/ssv6006c/ssv6006C_reg.h	5527;"	d
+GET_RG_TURISMO_TRX_DP_RHP	smac/hal/ssv6006c/ssv6006C_reg.h	5539;"	d
+GET_RG_TURISMO_TRX_DP_RP	smac/hal/ssv6006c/ssv6006C_reg.h	5538;"	d
+GET_RG_TURISMO_TRX_DP_VT_TH_HI	smac/hal/ssv6006c/ssv6006C_reg.h	5541;"	d
+GET_RG_TURISMO_TRX_DP_VT_TH_LO	smac/hal/ssv6006c/ssv6006C_reg.h	5542;"	d
+GET_RG_TURISMO_TRX_EN_AAC5GB_MXPDSW	smac/hal/ssv6006c/ssv6006C_reg.h	6018;"	d
+GET_RG_TURISMO_TRX_EN_AAC5GB_RPPDSW	smac/hal/ssv6006c/ssv6006C_reg.h	6019;"	d
+GET_RG_TURISMO_TRX_EN_AAC5GB_VOPDSW	smac/hal/ssv6006c/ssv6006C_reg.h	6017;"	d
+GET_RG_TURISMO_TRX_EN_DLDO_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	6280;"	d
+GET_RG_TURISMO_TRX_EN_DPL_MOD	smac/hal/ssv6006c/ssv6006C_reg.h	5525;"	d
+GET_RG_TURISMO_TRX_EN_DP_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	5520;"	d
+GET_RG_TURISMO_TRX_EN_DP_VT_MON	smac/hal/ssv6006c/ssv6006C_reg.h	5540;"	d
+GET_RG_TURISMO_TRX_EN_FDB	smac/hal/ssv6006c/ssv6006C_reg.h	6283;"	d
+GET_RG_TURISMO_TRX_EN_FDB_DCC_MUAL	smac/hal/ssv6006c/ssv6006C_reg.h	6287;"	d
+GET_RG_TURISMO_TRX_EN_FDB_DELAYC_MUAL	smac/hal/ssv6006c/ssv6006C_reg.h	6288;"	d
+GET_RG_TURISMO_TRX_EN_FDB_DELAYF_MUAL	smac/hal/ssv6006c/ssv6006C_reg.h	6289;"	d
+GET_RG_TURISMO_TRX_EN_FDB_PHASESWAP_MUAL	smac/hal/ssv6006c/ssv6006C_reg.h	6290;"	d
+GET_RG_TURISMO_TRX_EN_FDB_RECAL	smac/hal/ssv6006c/ssv6006C_reg.h	6299;"	d
+GET_RG_TURISMO_TRX_EN_HSDIV_OBF_MX	smac/hal/ssv6006c/ssv6006C_reg.h	5908;"	d
+GET_RG_TURISMO_TRX_EN_HSDIV_OBF_MX_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	5907;"	d
+GET_RG_TURISMO_TRX_EN_HSDIV_OBF_SX	smac/hal/ssv6006c/ssv6006C_reg.h	5906;"	d
+GET_RG_TURISMO_TRX_EN_HSDIV_OBF_SX_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	5905;"	d
+GET_RG_TURISMO_TRX_EN_IOT_ADC	smac/hal/ssv6006c/ssv6006C_reg.h	5109;"	d
+GET_RG_TURISMO_TRX_EN_IOT_ADC_BUF	smac/hal/ssv6006c/ssv6006C_reg.h	5108;"	d
+GET_RG_TURISMO_TRX_EN_IREF_RX	smac/hal/ssv6006c/ssv6006C_reg.h	5112;"	d
+GET_RG_TURISMO_TRX_EN_LDO_5G_CP	smac/hal/ssv6006c/ssv6006C_reg.h	5922;"	d
+GET_RG_TURISMO_TRX_EN_LDO_5G_CP_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	5779;"	d
+GET_RG_TURISMO_TRX_EN_LDO_5G_CP_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	5928;"	d
+GET_RG_TURISMO_TRX_EN_LDO_5G_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	5923;"	d
+GET_RG_TURISMO_TRX_EN_LDO_5G_DIV_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	5784;"	d
+GET_RG_TURISMO_TRX_EN_LDO_5G_DIV_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	5929;"	d
+GET_RG_TURISMO_TRX_EN_LDO_5G_LO	smac/hal/ssv6006c/ssv6006C_reg.h	5924;"	d
+GET_RG_TURISMO_TRX_EN_LDO_5G_LO_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	5781;"	d
+GET_RG_TURISMO_TRX_EN_LDO_5G_LO_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	5930;"	d
+GET_RG_TURISMO_TRX_EN_LDO_5G_VCO	smac/hal/ssv6006c/ssv6006C_reg.h	5925;"	d
+GET_RG_TURISMO_TRX_EN_LDO_5G_VCO_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	5931;"	d
+GET_RG_TURISMO_TRX_EN_LDO_5G_VCO_PSW	smac/hal/ssv6006c/ssv6006C_reg.h	5926;"	d
+GET_RG_TURISMO_TRX_EN_LDO_5G_VCO_VDD33	smac/hal/ssv6006c/ssv6006C_reg.h	5927;"	d
+GET_RG_TURISMO_TRX_EN_LDO_AFE	smac/hal/ssv6006c/ssv6006C_reg.h	5111;"	d
+GET_RG_TURISMO_TRX_EN_LDO_CP	smac/hal/ssv6006c/ssv6006C_reg.h	5397;"	d
+GET_RG_TURISMO_TRX_EN_LDO_CP_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	5146;"	d
+GET_RG_TURISMO_TRX_EN_LDO_CP_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	5403;"	d
+GET_RG_TURISMO_TRX_EN_LDO_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	5398;"	d
+GET_RG_TURISMO_TRX_EN_LDO_DIV_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	5151;"	d
+GET_RG_TURISMO_TRX_EN_LDO_DIV_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	5404;"	d
+GET_RG_TURISMO_TRX_EN_LDO_DP_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	5144;"	d
+GET_RG_TURISMO_TRX_EN_LDO_DP_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	5529;"	d
+GET_RG_TURISMO_TRX_EN_LDO_EFUSE	smac/hal/ssv6006c/ssv6006C_reg.h	6309;"	d
+GET_RG_TURISMO_TRX_EN_LDO_LO	smac/hal/ssv6006c/ssv6006C_reg.h	5399;"	d
+GET_RG_TURISMO_TRX_EN_LDO_LO_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	5148;"	d
+GET_RG_TURISMO_TRX_EN_LDO_LO_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	5405;"	d
+GET_RG_TURISMO_TRX_EN_LDO_RX_AFE_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	5141;"	d
+GET_RG_TURISMO_TRX_EN_LDO_RX_AFE_FC	smac/hal/ssv6006c/ssv6006C_reg.h	5134;"	d
+GET_RG_TURISMO_TRX_EN_LDO_RX_AFE_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	5136;"	d
+GET_RG_TURISMO_TRX_EN_LDO_RX_FE	smac/hal/ssv6006c/ssv6006C_reg.h	5110;"	d
+GET_RG_TURISMO_TRX_EN_LDO_RX_FE_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	5139;"	d
+GET_RG_TURISMO_TRX_EN_LDO_RX_FE_FC	smac/hal/ssv6006c/ssv6006C_reg.h	5133;"	d
+GET_RG_TURISMO_TRX_EN_LDO_RX_FE_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	5135;"	d
+GET_RG_TURISMO_TRX_EN_LDO_TX_PA	smac/hal/ssv6006c/ssv6006C_reg.h	5216;"	d
+GET_RG_TURISMO_TRX_EN_LDO_VCO	smac/hal/ssv6006c/ssv6006C_reg.h	5400;"	d
+GET_RG_TURISMO_TRX_EN_LDO_VCO_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	5406;"	d
+GET_RG_TURISMO_TRX_EN_LDO_VCO_PSW	smac/hal/ssv6006c/ssv6006C_reg.h	5401;"	d
+GET_RG_TURISMO_TRX_EN_LDO_VCO_VDD33	smac/hal/ssv6006c/ssv6006C_reg.h	5402;"	d
+GET_RG_TURISMO_TRX_EN_LDO_XO_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	6279;"	d
+GET_RG_TURISMO_TRX_EN_LDO_XO_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	6278;"	d
+GET_RG_TURISMO_TRX_EN_RTC_CAL	smac/hal/ssv6006c/ssv6006C_reg.h	6324;"	d
+GET_RG_TURISMO_TRX_EN_RX_ADC	smac/hal/ssv6006c/ssv6006C_reg.h	5093;"	d
+GET_RG_TURISMO_TRX_EN_RX_DIV2	smac/hal/ssv6006c/ssv6006C_reg.h	5085;"	d
+GET_RG_TURISMO_TRX_EN_RX_FILTER	smac/hal/ssv6006c/ssv6006C_reg.h	5091;"	d
+GET_RG_TURISMO_TRX_EN_RX_IQCAL	smac/hal/ssv6006c/ssv6006C_reg.h	5120;"	d
+GET_RG_TURISMO_TRX_EN_RX_LNA	smac/hal/ssv6006c/ssv6006C_reg.h	5081;"	d
+GET_RG_TURISMO_TRX_EN_RX_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	5087;"	d
+GET_RG_TURISMO_TRX_EN_RX_MIXER	smac/hal/ssv6006c/ssv6006C_reg.h	5083;"	d
+GET_RG_TURISMO_TRX_EN_RX_PADSW	smac/hal/ssv6006c/ssv6006C_reg.h	5132;"	d
+GET_RG_TURISMO_TRX_EN_RX_RSSI	smac/hal/ssv6006c/ssv6006C_reg.h	5095;"	d
+GET_RG_TURISMO_TRX_EN_RX_RSSI_TESTNODE	smac/hal/ssv6006c/ssv6006C_reg.h	5202;"	d
+GET_RG_TURISMO_TRX_EN_RX_TESTNODE	smac/hal/ssv6006c/ssv6006C_reg.h	5131;"	d
+GET_RG_TURISMO_TRX_EN_RX_TZ	smac/hal/ssv6006c/ssv6006C_reg.h	5089;"	d
+GET_RG_TURISMO_TRX_EN_SARADC	smac/hal/ssv6006c/ssv6006C_reg.h	5124;"	d
+GET_RG_TURISMO_TRX_EN_SAR_TEST	smac/hal/ssv6006c/ssv6006C_reg.h	5340;"	d
+GET_RG_TURISMO_TRX_EN_SX5GB_CP	smac/hal/ssv6006c/ssv6006C_reg.h	5894;"	d
+GET_RG_TURISMO_TRX_EN_SX5GB_CP_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	5893;"	d
+GET_RG_TURISMO_TRX_EN_SX5GB_DITHER	smac/hal/ssv6006c/ssv6006C_reg.h	5993;"	d
+GET_RG_TURISMO_TRX_EN_SX5GB_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	5896;"	d
+GET_RG_TURISMO_TRX_EN_SX5GB_DIV_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	5895;"	d
+GET_RG_TURISMO_TRX_EN_SX5GB_HSDIV	smac/hal/ssv6006c/ssv6006C_reg.h	5904;"	d
+GET_RG_TURISMO_TRX_EN_SX5GB_HSDIV_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	5903;"	d
+GET_RG_TURISMO_TRX_EN_SX5GB_LDO_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	5921;"	d
+GET_RG_TURISMO_TRX_EN_SX5GB_MOD	smac/hal/ssv6006c/ssv6006C_reg.h	5992;"	d
+GET_RG_TURISMO_TRX_EN_SX5GB_VCO	smac/hal/ssv6006c/ssv6006C_reg.h	5898;"	d
+GET_RG_TURISMO_TRX_EN_SX5GB_VCOMON	smac/hal/ssv6006c/ssv6006C_reg.h	5986;"	d
+GET_RG_TURISMO_TRX_EN_SX5GB_VCO_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	5897;"	d
+GET_RG_TURISMO_TRX_EN_SX_CP	smac/hal/ssv6006c/ssv6006C_reg.h	5372;"	d
+GET_RG_TURISMO_TRX_EN_SX_CP_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	5371;"	d
+GET_RG_TURISMO_TRX_EN_SX_DITHER	smac/hal/ssv6006c/ssv6006C_reg.h	5485;"	d
+GET_RG_TURISMO_TRX_EN_SX_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	5374;"	d
+GET_RG_TURISMO_TRX_EN_SX_DIV_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	5373;"	d
+GET_RG_TURISMO_TRX_EN_SX_LDO_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	5396;"	d
+GET_RG_TURISMO_TRX_EN_SX_MIX	smac/hal/ssv6006c/ssv6006C_reg.h	5910;"	d
+GET_RG_TURISMO_TRX_EN_SX_MIX_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	5909;"	d
+GET_RG_TURISMO_TRX_EN_SX_MOD	smac/hal/ssv6006c/ssv6006C_reg.h	5484;"	d
+GET_RG_TURISMO_TRX_EN_SX_REP	smac/hal/ssv6006c/ssv6006C_reg.h	5912;"	d
+GET_RG_TURISMO_TRX_EN_SX_REP_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	5911;"	d
+GET_RG_TURISMO_TRX_EN_SX_VCO	smac/hal/ssv6006c/ssv6006C_reg.h	5376;"	d
+GET_RG_TURISMO_TRX_EN_SX_VCOMON	smac/hal/ssv6006c/ssv6006C_reg.h	5478;"	d
+GET_RG_TURISMO_TRX_EN_SX_VCO_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	5375;"	d
+GET_RG_TURISMO_TRX_EN_TX_BT_PA	smac/hal/ssv6006c/ssv6006C_reg.h	5107;"	d
+GET_RG_TURISMO_TRX_EN_TX_DAC	smac/hal/ssv6006c/ssv6006C_reg.h	5101;"	d
+GET_RG_TURISMO_TRX_EN_TX_DAC_CAL	smac/hal/ssv6006c/ssv6006C_reg.h	5114;"	d
+GET_RG_TURISMO_TRX_EN_TX_DAC_OUT	smac/hal/ssv6006c/ssv6006C_reg.h	5128;"	d
+GET_RG_TURISMO_TRX_EN_TX_DAC_VOUT	smac/hal/ssv6006c/ssv6006C_reg.h	5129;"	d
+GET_RG_TURISMO_TRX_EN_TX_DIV2	smac/hal/ssv6006c/ssv6006C_reg.h	5103;"	d
+GET_RG_TURISMO_TRX_EN_TX_DIV2_BUF	smac/hal/ssv6006c/ssv6006C_reg.h	5105;"	d
+GET_RG_TURISMO_TRX_EN_TX_DPD	smac/hal/ssv6006c/ssv6006C_reg.h	5122;"	d
+GET_RG_TURISMO_TRX_EN_TX_MOD	smac/hal/ssv6006c/ssv6006C_reg.h	5099;"	d
+GET_RG_TURISMO_TRX_EN_TX_PA	smac/hal/ssv6006c/ssv6006C_reg.h	5097;"	d
+GET_RG_TURISMO_TRX_EN_TX_PA_LDO_FC	smac/hal/ssv6006c/ssv6006C_reg.h	5217;"	d
+GET_RG_TURISMO_TRX_EN_TX_PA_LDO_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	5218;"	d
+GET_RG_TURISMO_TRX_EN_TX_PA_LDO_VTH	smac/hal/ssv6006c/ssv6006C_reg.h	5219;"	d
+GET_RG_TURISMO_TRX_EN_TX_SELF_MIXER	smac/hal/ssv6006c/ssv6006C_reg.h	5118;"	d
+GET_RG_TURISMO_TRX_EN_TX_TRSW	smac/hal/ssv6006c/ssv6006C_reg.h	5079;"	d
+GET_RG_TURISMO_TRX_EN_TX_TSSI	smac/hal/ssv6006c/ssv6006C_reg.h	5123;"	d
+GET_RG_TURISMO_TRX_EN_TX_VTOI_2ND	smac/hal/ssv6006c/ssv6006C_reg.h	5125;"	d
+GET_RG_TURISMO_TRX_EN_VCOBF_DIVCK	smac/hal/ssv6006c/ssv6006C_reg.h	5390;"	d
+GET_RG_TURISMO_TRX_EN_VCOBF_DIVCK_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	5389;"	d
+GET_RG_TURISMO_TRX_EN_VCOBF_RXMB	smac/hal/ssv6006c/ssv6006C_reg.h	5386;"	d
+GET_RG_TURISMO_TRX_EN_VCOBF_RXMB_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	5385;"	d
+GET_RG_TURISMO_TRX_EN_VCOBF_RXOB	smac/hal/ssv6006c/ssv6006C_reg.h	5388;"	d
+GET_RG_TURISMO_TRX_EN_VCOBF_RXOB_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	5387;"	d
+GET_RG_TURISMO_TRX_EN_VCOBF_TXMB	smac/hal/ssv6006c/ssv6006C_reg.h	5382;"	d
+GET_RG_TURISMO_TRX_EN_VCOBF_TXMB_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	5381;"	d
+GET_RG_TURISMO_TRX_EN_VCOBF_TXOB	smac/hal/ssv6006c/ssv6006C_reg.h	5384;"	d
+GET_RG_TURISMO_TRX_EN_VCOBF_TXOB_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	5383;"	d
+GET_RG_TURISMO_TRX_EN_XOTEST	smac/hal/ssv6006c/ssv6006C_reg.h	6286;"	d
+GET_RG_TURISMO_TRX_EXT_MCU_PWRUP	smac/hal/ssv6006c/ssv6006C_reg.h	6424;"	d
+GET_RG_TURISMO_TRX_FDB_BYPASS	smac/hal/ssv6006c/ssv6006C_reg.h	6284;"	d
+GET_RG_TURISMO_TRX_FDB_CDELAY_MUAL	smac/hal/ssv6006c/ssv6006C_reg.h	6292;"	d
+GET_RG_TURISMO_TRX_FDB_DUTY_LTH	smac/hal/ssv6006c/ssv6006C_reg.h	6285;"	d
+GET_RG_TURISMO_TRX_FDB_FDELAY_MUAL	smac/hal/ssv6006c/ssv6006C_reg.h	6293;"	d
+GET_RG_TURISMO_TRX_FDB_PHASESWAP_MUAL	smac/hal/ssv6006c/ssv6006C_reg.h	6291;"	d
+GET_RG_TURISMO_TRX_FDB_RDELAYF	smac/hal/ssv6006c/ssv6006C_reg.h	6296;"	d
+GET_RG_TURISMO_TRX_FDB_RDELAYS	smac/hal/ssv6006c/ssv6006C_reg.h	6297;"	d
+GET_RG_TURISMO_TRX_FDB_RECAL_TIMMER	smac/hal/ssv6006c/ssv6006C_reg.h	6298;"	d
+GET_RG_TURISMO_TRX_FPGA_CLK_REF_40M_DS	smac/hal/ssv6006c/ssv6006C_reg.h	6368;"	d
+GET_RG_TURISMO_TRX_FPGA_CLK_REF_40M_EN	smac/hal/ssv6006c/ssv6006C_reg.h	6345;"	d
+GET_RG_TURISMO_TRX_FPGA_CLK_REF_40M_OE	smac/hal/ssv6006c/ssv6006C_reg.h	6370;"	d
+GET_RG_TURISMO_TRX_FPGA_CLK_REF_40M_PD	smac/hal/ssv6006c/ssv6006C_reg.h	6369;"	d
+GET_RG_TURISMO_TRX_GPIO00_DS	smac/hal/ssv6006c/ssv6006C_reg.h	6395;"	d
+GET_RG_TURISMO_TRX_GPIO00_OE	smac/hal/ssv6006c/ssv6006C_reg.h	6397;"	d
+GET_RG_TURISMO_TRX_GPIO00_PD	smac/hal/ssv6006c/ssv6006C_reg.h	6396;"	d
+GET_RG_TURISMO_TRX_GPIO01_DS	smac/hal/ssv6006c/ssv6006C_reg.h	6398;"	d
+GET_RG_TURISMO_TRX_GPIO01_OE	smac/hal/ssv6006c/ssv6006C_reg.h	6400;"	d
+GET_RG_TURISMO_TRX_GPIO01_PD	smac/hal/ssv6006c/ssv6006C_reg.h	6399;"	d
+GET_RG_TURISMO_TRX_GPIO02_DS	smac/hal/ssv6006c/ssv6006C_reg.h	6401;"	d
+GET_RG_TURISMO_TRX_GPIO02_OE	smac/hal/ssv6006c/ssv6006C_reg.h	6403;"	d
+GET_RG_TURISMO_TRX_GPIO02_PD	smac/hal/ssv6006c/ssv6006C_reg.h	6402;"	d
+GET_RG_TURISMO_TRX_GPIO03_DS	smac/hal/ssv6006c/ssv6006C_reg.h	6404;"	d
+GET_RG_TURISMO_TRX_GPIO03_OE	smac/hal/ssv6006c/ssv6006C_reg.h	6406;"	d
+GET_RG_TURISMO_TRX_GPIO03_PD	smac/hal/ssv6006c/ssv6006C_reg.h	6405;"	d
+GET_RG_TURISMO_TRX_GPIO04_DS	smac/hal/ssv6006c/ssv6006C_reg.h	6407;"	d
+GET_RG_TURISMO_TRX_GPIO04_OE	smac/hal/ssv6006c/ssv6006C_reg.h	6409;"	d
+GET_RG_TURISMO_TRX_GPIO04_PD	smac/hal/ssv6006c/ssv6006C_reg.h	6408;"	d
+GET_RG_TURISMO_TRX_GPIO05_DS	smac/hal/ssv6006c/ssv6006C_reg.h	6410;"	d
+GET_RG_TURISMO_TRX_GPIO05_OE	smac/hal/ssv6006c/ssv6006C_reg.h	6412;"	d
+GET_RG_TURISMO_TRX_GPIO05_PD	smac/hal/ssv6006c/ssv6006C_reg.h	6411;"	d
+GET_RG_TURISMO_TRX_GPIO06_DS	smac/hal/ssv6006c/ssv6006C_reg.h	6413;"	d
+GET_RG_TURISMO_TRX_GPIO06_OE	smac/hal/ssv6006c/ssv6006C_reg.h	6415;"	d
+GET_RG_TURISMO_TRX_GPIO06_PD	smac/hal/ssv6006c/ssv6006C_reg.h	6414;"	d
+GET_RG_TURISMO_TRX_GPIO07_DS	smac/hal/ssv6006c/ssv6006C_reg.h	6416;"	d
+GET_RG_TURISMO_TRX_GPIO07_OE	smac/hal/ssv6006c/ssv6006C_reg.h	6418;"	d
+GET_RG_TURISMO_TRX_GPIO07_PD	smac/hal/ssv6006c/ssv6006C_reg.h	6417;"	d
+GET_RG_TURISMO_TRX_GPIO08_DS	smac/hal/ssv6006c/ssv6006C_reg.h	6371;"	d
+GET_RG_TURISMO_TRX_GPIO08_OE	smac/hal/ssv6006c/ssv6006C_reg.h	6373;"	d
+GET_RG_TURISMO_TRX_GPIO08_PD	smac/hal/ssv6006c/ssv6006C_reg.h	6372;"	d
+GET_RG_TURISMO_TRX_GPIO09_DS	smac/hal/ssv6006c/ssv6006C_reg.h	6374;"	d
+GET_RG_TURISMO_TRX_GPIO09_OE	smac/hal/ssv6006c/ssv6006C_reg.h	6376;"	d
+GET_RG_TURISMO_TRX_GPIO09_PD	smac/hal/ssv6006c/ssv6006C_reg.h	6375;"	d
+GET_RG_TURISMO_TRX_GPIO10_DS	smac/hal/ssv6006c/ssv6006C_reg.h	6377;"	d
+GET_RG_TURISMO_TRX_GPIO10_OE	smac/hal/ssv6006c/ssv6006C_reg.h	6379;"	d
+GET_RG_TURISMO_TRX_GPIO10_PD	smac/hal/ssv6006c/ssv6006C_reg.h	6378;"	d
+GET_RG_TURISMO_TRX_GPIO11_DS	smac/hal/ssv6006c/ssv6006C_reg.h	6380;"	d
+GET_RG_TURISMO_TRX_GPIO11_OE	smac/hal/ssv6006c/ssv6006C_reg.h	6382;"	d
+GET_RG_TURISMO_TRX_GPIO11_PD	smac/hal/ssv6006c/ssv6006C_reg.h	6381;"	d
+GET_RG_TURISMO_TRX_GPIO12_DS	smac/hal/ssv6006c/ssv6006C_reg.h	6383;"	d
+GET_RG_TURISMO_TRX_GPIO12_OE	smac/hal/ssv6006c/ssv6006C_reg.h	6385;"	d
+GET_RG_TURISMO_TRX_GPIO12_PD	smac/hal/ssv6006c/ssv6006C_reg.h	6384;"	d
+GET_RG_TURISMO_TRX_GPIO13_DS	smac/hal/ssv6006c/ssv6006C_reg.h	6386;"	d
+GET_RG_TURISMO_TRX_GPIO13_OE	smac/hal/ssv6006c/ssv6006C_reg.h	6388;"	d
+GET_RG_TURISMO_TRX_GPIO13_PD	smac/hal/ssv6006c/ssv6006C_reg.h	6387;"	d
+GET_RG_TURISMO_TRX_GPIO14_DS	smac/hal/ssv6006c/ssv6006C_reg.h	6389;"	d
+GET_RG_TURISMO_TRX_GPIO14_OE	smac/hal/ssv6006c/ssv6006C_reg.h	6391;"	d
+GET_RG_TURISMO_TRX_GPIO14_PD	smac/hal/ssv6006c/ssv6006C_reg.h	6390;"	d
+GET_RG_TURISMO_TRX_GPIO15_DS	smac/hal/ssv6006c/ssv6006C_reg.h	6392;"	d
+GET_RG_TURISMO_TRX_GPIO15_OE	smac/hal/ssv6006c/ssv6006C_reg.h	6394;"	d
+GET_RG_TURISMO_TRX_GPIO15_PD	smac/hal/ssv6006c/ssv6006C_reg.h	6393;"	d
+GET_RG_TURISMO_TRX_GPIO16_DS	smac/hal/ssv6006c/ssv6006C_reg.h	6352;"	d
+GET_RG_TURISMO_TRX_GPIO16_OE	smac/hal/ssv6006c/ssv6006C_reg.h	6354;"	d
+GET_RG_TURISMO_TRX_GPIO16_PD	smac/hal/ssv6006c/ssv6006C_reg.h	6353;"	d
+GET_RG_TURISMO_TRX_GPIO17_DS	smac/hal/ssv6006c/ssv6006C_reg.h	6355;"	d
+GET_RG_TURISMO_TRX_GPIO17_OE	smac/hal/ssv6006c/ssv6006C_reg.h	6357;"	d
+GET_RG_TURISMO_TRX_GPIO17_PD	smac/hal/ssv6006c/ssv6006C_reg.h	6356;"	d
+GET_RG_TURISMO_TRX_GPIO18_DS	smac/hal/ssv6006c/ssv6006C_reg.h	6358;"	d
+GET_RG_TURISMO_TRX_GPIO18_OE	smac/hal/ssv6006c/ssv6006C_reg.h	6360;"	d
+GET_RG_TURISMO_TRX_GPIO18_PD	smac/hal/ssv6006c/ssv6006C_reg.h	6359;"	d
+GET_RG_TURISMO_TRX_GPIO19_DS	smac/hal/ssv6006c/ssv6006C_reg.h	6361;"	d
+GET_RG_TURISMO_TRX_GPIO19_OE	smac/hal/ssv6006c/ssv6006C_reg.h	6363;"	d
+GET_RG_TURISMO_TRX_GPIO19_PD	smac/hal/ssv6006c/ssv6006C_reg.h	6362;"	d
+GET_RG_TURISMO_TRX_GPIO20_DS	smac/hal/ssv6006c/ssv6006C_reg.h	6364;"	d
+GET_RG_TURISMO_TRX_GPIO20_OE	smac/hal/ssv6006c/ssv6006C_reg.h	6366;"	d
+GET_RG_TURISMO_TRX_GPIO20_PD	smac/hal/ssv6006c/ssv6006C_reg.h	6365;"	d
+GET_RG_TURISMO_TRX_HS3W_COMM_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	6267;"	d
+GET_RG_TURISMO_TRX_HS3W_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	6266;"	d
+GET_RG_TURISMO_TRX_HS3W_PGAGC	smac/hal/ssv6006c/ssv6006C_reg.h	6262;"	d
+GET_RG_TURISMO_TRX_HS3W_RFGC	smac/hal/ssv6006c/ssv6006C_reg.h	6263;"	d
+GET_RG_TURISMO_TRX_HS3W_RF_PHY_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	6265;"	d
+GET_RG_TURISMO_TRX_HS3W_RXAGC	smac/hal/ssv6006c/ssv6006C_reg.h	6264;"	d
+GET_RG_TURISMO_TRX_HS3W_START_SENT	smac/hal/ssv6006c/ssv6006C_reg.h	6268;"	d
+GET_RG_TURISMO_TRX_HS3W_SX_CHANNEL_INT	smac/hal/ssv6006c/ssv6006C_reg.h	6271;"	d
+GET_RG_TURISMO_TRX_HS3W_SX_RFCH_MAP_EN_INT	smac/hal/ssv6006c/ssv6006C_reg.h	6270;"	d
+GET_RG_TURISMO_TRX_HS3W_SX_RFCTRL_CH_INT_10_8	smac/hal/ssv6006c/ssv6006C_reg.h	6269;"	d
+GET_RG_TURISMO_TRX_HS3W_SX_RFCTRL_CH_INT_7_0	smac/hal/ssv6006c/ssv6006C_reg.h	6273;"	d
+GET_RG_TURISMO_TRX_HS3W_SX_RFCTRL_F_INT	smac/hal/ssv6006c/ssv6006C_reg.h	6272;"	d
+GET_RG_TURISMO_TRX_HS3W_TX_RF_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	6261;"	d
+GET_RG_TURISMO_TRX_HSDIV_INBFSEL	smac/hal/ssv6006c/ssv6006C_reg.h	5977;"	d
+GET_RG_TURISMO_TRX_HSDIV_OBFMX_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	5978;"	d
+GET_RG_TURISMO_TRX_HSDIV_OBFSX_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	5979;"	d
+GET_RG_TURISMO_TRX_HSDIV_VRSEL	smac/hal/ssv6006c/ssv6006C_reg.h	5980;"	d
+GET_RG_TURISMO_TRX_HS_3WIRE_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	5065;"	d
+GET_RG_TURISMO_TRX_HW_PINSEL	smac/hal/ssv6006c/ssv6006C_reg.h	5064;"	d
+GET_RG_TURISMO_TRX_IDACAI_TZ0_COARSE0	smac/hal/ssv6006c/ssv6006C_reg.h	5619;"	d
+GET_RG_TURISMO_TRX_IDACAI_TZ0_COARSE1	smac/hal/ssv6006c/ssv6006C_reg.h	5617;"	d
+GET_RG_TURISMO_TRX_IDACAI_TZ0_COARSE2	smac/hal/ssv6006c/ssv6006C_reg.h	5615;"	d
+GET_RG_TURISMO_TRX_IDACAI_TZ0_COARSE3	smac/hal/ssv6006c/ssv6006C_reg.h	5613;"	d
+GET_RG_TURISMO_TRX_IDACAI_TZ0_COARSE4	smac/hal/ssv6006c/ssv6006C_reg.h	5611;"	d
+GET_RG_TURISMO_TRX_IDACAI_TZ1_COARSE0	smac/hal/ssv6006c/ssv6006C_reg.h	5629;"	d
+GET_RG_TURISMO_TRX_IDACAI_TZ1_COARSE1	smac/hal/ssv6006c/ssv6006C_reg.h	5627;"	d
+GET_RG_TURISMO_TRX_IDACAI_TZ1_COARSE2	smac/hal/ssv6006c/ssv6006C_reg.h	5625;"	d
+GET_RG_TURISMO_TRX_IDACAI_TZ1_COARSE3	smac/hal/ssv6006c/ssv6006C_reg.h	5623;"	d
+GET_RG_TURISMO_TRX_IDACAI_TZ1_COARSE4	smac/hal/ssv6006c/ssv6006C_reg.h	5621;"	d
+GET_RG_TURISMO_TRX_IDACAQ_TZ0_COARSE0	smac/hal/ssv6006c/ssv6006C_reg.h	5620;"	d
+GET_RG_TURISMO_TRX_IDACAQ_TZ0_COARSE1	smac/hal/ssv6006c/ssv6006C_reg.h	5618;"	d
+GET_RG_TURISMO_TRX_IDACAQ_TZ0_COARSE2	smac/hal/ssv6006c/ssv6006C_reg.h	5616;"	d
+GET_RG_TURISMO_TRX_IDACAQ_TZ0_COARSE3	smac/hal/ssv6006c/ssv6006C_reg.h	5614;"	d
+GET_RG_TURISMO_TRX_IDACAQ_TZ0_COARSE4	smac/hal/ssv6006c/ssv6006C_reg.h	5612;"	d
+GET_RG_TURISMO_TRX_IDACAQ_TZ1_COARSE0	smac/hal/ssv6006c/ssv6006C_reg.h	5630;"	d
+GET_RG_TURISMO_TRX_IDACAQ_TZ1_COARSE1	smac/hal/ssv6006c/ssv6006C_reg.h	5628;"	d
+GET_RG_TURISMO_TRX_IDACAQ_TZ1_COARSE2	smac/hal/ssv6006c/ssv6006C_reg.h	5626;"	d
+GET_RG_TURISMO_TRX_IDACAQ_TZ1_COARSE3	smac/hal/ssv6006c/ssv6006C_reg.h	5624;"	d
+GET_RG_TURISMO_TRX_IDACAQ_TZ1_COARSE4	smac/hal/ssv6006c/ssv6006C_reg.h	5622;"	d
+GET_RG_TURISMO_TRX_INT_PMU_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	6333;"	d
+GET_RG_TURISMO_TRX_IOT_ADC_CLKSEL	smac/hal/ssv6006c/ssv6006C_reg.h	5725;"	d
+GET_RG_TURISMO_TRX_IOT_ADC_CLK_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	5732;"	d
+GET_RG_TURISMO_TRX_IOT_ADC_CLK_SH_DUTY	smac/hal/ssv6006c/ssv6006C_reg.h	5733;"	d
+GET_RG_TURISMO_TRX_IOT_ADC_CLOAD	smac/hal/ssv6006c/ssv6006C_reg.h	5731;"	d
+GET_RG_TURISMO_TRX_IOT_ADC_DNLEN	smac/hal/ssv6006c/ssv6006C_reg.h	5726;"	d
+GET_RG_TURISMO_TRX_IOT_ADC_EDGE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	6183;"	d
+GET_RG_TURISMO_TRX_IOT_ADC_ICMP	smac/hal/ssv6006c/ssv6006C_reg.h	5729;"	d
+GET_RG_TURISMO_TRX_IOT_ADC_METAEN	smac/hal/ssv6006c/ssv6006C_reg.h	5727;"	d
+GET_RG_TURISMO_TRX_IOT_ADC_TFLAG	smac/hal/ssv6006c/ssv6006C_reg.h	5728;"	d
+GET_RG_TURISMO_TRX_IOT_ADC_VCMI	smac/hal/ssv6006c/ssv6006C_reg.h	5730;"	d
+GET_RG_TURISMO_TRX_IQ_SWAP	smac/hal/ssv6006c/ssv6006C_reg.h	6188;"	d
+GET_RG_TURISMO_TRX_I_INV	smac/hal/ssv6006c/ssv6006C_reg.h	6187;"	d
+GET_RG_TURISMO_TRX_LDO_5G_CP_FC	smac/hal/ssv6006c/ssv6006C_reg.h	5934;"	d
+GET_RG_TURISMO_TRX_LDO_5G_CP_FC_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	5933;"	d
+GET_RG_TURISMO_TRX_LDO_5G_DIV_FC	smac/hal/ssv6006c/ssv6006C_reg.h	5936;"	d
+GET_RG_TURISMO_TRX_LDO_5G_DIV_FC_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	5935;"	d
+GET_RG_TURISMO_TRX_LDO_5G_LO_FC	smac/hal/ssv6006c/ssv6006C_reg.h	5938;"	d
+GET_RG_TURISMO_TRX_LDO_5G_LO_FC_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	5937;"	d
+GET_RG_TURISMO_TRX_LDO_5G_VCO_FC	smac/hal/ssv6006c/ssv6006C_reg.h	5940;"	d
+GET_RG_TURISMO_TRX_LDO_5G_VCO_FC_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	5939;"	d
+GET_RG_TURISMO_TRX_LDO_5G_VCO_RCF	smac/hal/ssv6006c/ssv6006C_reg.h	5941;"	d
+GET_RG_TURISMO_TRX_LDO_CP_FC	smac/hal/ssv6006c/ssv6006C_reg.h	5409;"	d
+GET_RG_TURISMO_TRX_LDO_CP_FC_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	5408;"	d
+GET_RG_TURISMO_TRX_LDO_DIV_FC	smac/hal/ssv6006c/ssv6006C_reg.h	5411;"	d
+GET_RG_TURISMO_TRX_LDO_DIV_FC_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	5410;"	d
+GET_RG_TURISMO_TRX_LDO_LEVEL_AFE	smac/hal/ssv6006c/ssv6006C_reg.h	5140;"	d
+GET_RG_TURISMO_TRX_LDO_LEVEL_EFUSE	smac/hal/ssv6006c/ssv6006C_reg.h	6308;"	d
+GET_RG_TURISMO_TRX_LDO_LEVEL_RX_FE	smac/hal/ssv6006c/ssv6006C_reg.h	5138;"	d
+GET_RG_TURISMO_TRX_LDO_LO_FC	smac/hal/ssv6006c/ssv6006C_reg.h	5413;"	d
+GET_RG_TURISMO_TRX_LDO_LO_FC_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	5412;"	d
+GET_RG_TURISMO_TRX_LDO_VCO_FC	smac/hal/ssv6006c/ssv6006C_reg.h	5415;"	d
+GET_RG_TURISMO_TRX_LDO_VCO_FC_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	5414;"	d
+GET_RG_TURISMO_TRX_LDO_VCO_RCF	smac/hal/ssv6006c/ssv6006C_reg.h	5416;"	d
+GET_RG_TURISMO_TRX_LOAD_RFTABLE_RDY	smac/hal/ssv6006c/ssv6006C_reg.h	6300;"	d
+GET_RG_TURISMO_TRX_LO_UP_CH	smac/hal/ssv6006c/ssv6006C_reg.h	6175;"	d
+GET_RG_TURISMO_TRX_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	5071;"	d
+GET_RG_TURISMO_TRX_MODE_BY_HS_3WIRE	smac/hal/ssv6006c/ssv6006C_reg.h	6274;"	d
+GET_RG_TURISMO_TRX_MODE_LATCH_LMT	smac/hal/ssv6006c/ssv6006C_reg.h	6422;"	d
+GET_RG_TURISMO_TRX_MODE_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	5066;"	d
+GET_RG_TURISMO_TRX_NFRAC_DELTA	smac/hal/ssv6006c/ssv6006C_reg.h	6173;"	d
+GET_RG_TURISMO_TRX_PAD_MUX_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	6421;"	d
+GET_RG_TURISMO_TRX_PGAG	smac/hal/ssv6006c/ssv6006C_reg.h	5074;"	d
+GET_RG_TURISMO_TRX_PGAG_DPDCAL	smac/hal/ssv6006c/ssv6006C_reg.h	5723;"	d
+GET_RG_TURISMO_TRX_PGAG_RCCAL	smac/hal/ssv6006c/ssv6006C_reg.h	5716;"	d
+GET_RG_TURISMO_TRX_PGAG_RXIQCAL	smac/hal/ssv6006c/ssv6006C_reg.h	5720;"	d
+GET_RG_TURISMO_TRX_PGAG_TXCAL	smac/hal/ssv6006c/ssv6006C_reg.h	5717;"	d
+GET_RG_TURISMO_TRX_PHASE_17P5M	smac/hal/ssv6006c/ssv6006C_reg.h	6238;"	d
+GET_RG_TURISMO_TRX_PHASE_1M	smac/hal/ssv6006c/ssv6006C_reg.h	6241;"	d
+GET_RG_TURISMO_TRX_PHASE_2P5M	smac/hal/ssv6006c/ssv6006C_reg.h	6239;"	d
+GET_RG_TURISMO_TRX_PHASE_35M	smac/hal/ssv6006c/ssv6006C_reg.h	6243;"	d
+GET_RG_TURISMO_TRX_PHASE_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	6223;"	d
+GET_RG_TURISMO_TRX_PHASE_PADPD	smac/hal/ssv6006c/ssv6006C_reg.h	6242;"	d
+GET_RG_TURISMO_TRX_PHASE_RXIQ_1M	smac/hal/ssv6006c/ssv6006C_reg.h	6240;"	d
+GET_RG_TURISMO_TRX_PHASE_STEP_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	6222;"	d
+GET_RG_TURISMO_TRX_PHY_RST_N	smac/hal/ssv6006c/ssv6006C_reg.h	6347;"	d
+GET_RG_TURISMO_TRX_PMU_ENTER_SLEEP_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	6331;"	d
+GET_RG_TURISMO_TRX_PRE_DC_AUTO	smac/hal/ssv6006c/ssv6006C_reg.h	6260;"	d
+GET_RG_TURISMO_TRX_PRE_DC_POLA_INV	smac/hal/ssv6006c/ssv6006C_reg.h	6258;"	d
+GET_RG_TURISMO_TRX_PROC_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	6257;"	d
+GET_RG_TURISMO_TRX_Q_INV	smac/hal/ssv6006c/ssv6006C_reg.h	6186;"	d
+GET_RG_TURISMO_TRX_RAM_00	smac/hal/ssv6006c/ssv6006C_reg.h	6425;"	d
+GET_RG_TURISMO_TRX_RAM_01	smac/hal/ssv6006c/ssv6006C_reg.h	6426;"	d
+GET_RG_TURISMO_TRX_RAM_02	smac/hal/ssv6006c/ssv6006C_reg.h	6427;"	d
+GET_RG_TURISMO_TRX_RAM_03	smac/hal/ssv6006c/ssv6006C_reg.h	6428;"	d
+GET_RG_TURISMO_TRX_RAM_04	smac/hal/ssv6006c/ssv6006C_reg.h	6429;"	d
+GET_RG_TURISMO_TRX_RAM_05	smac/hal/ssv6006c/ssv6006C_reg.h	6430;"	d
+GET_RG_TURISMO_TRX_RAM_06	smac/hal/ssv6006c/ssv6006C_reg.h	6431;"	d
+GET_RG_TURISMO_TRX_RAM_07	smac/hal/ssv6006c/ssv6006C_reg.h	6432;"	d
+GET_RG_TURISMO_TRX_RAM_08	smac/hal/ssv6006c/ssv6006C_reg.h	6433;"	d
+GET_RG_TURISMO_TRX_RAM_09	smac/hal/ssv6006c/ssv6006C_reg.h	6434;"	d
+GET_RG_TURISMO_TRX_RAM_10	smac/hal/ssv6006c/ssv6006C_reg.h	6435;"	d
+GET_RG_TURISMO_TRX_RAM_11	smac/hal/ssv6006c/ssv6006C_reg.h	6436;"	d
+GET_RG_TURISMO_TRX_RAM_12	smac/hal/ssv6006c/ssv6006C_reg.h	6437;"	d
+GET_RG_TURISMO_TRX_RAM_13	smac/hal/ssv6006c/ssv6006C_reg.h	6438;"	d
+GET_RG_TURISMO_TRX_RAM_14	smac/hal/ssv6006c/ssv6006C_reg.h	6439;"	d
+GET_RG_TURISMO_TRX_RAM_15	smac/hal/ssv6006c/ssv6006C_reg.h	6440;"	d
+GET_RG_TURISMO_TRX_RAM_16	smac/hal/ssv6006c/ssv6006C_reg.h	6441;"	d
+GET_RG_TURISMO_TRX_RAM_17	smac/hal/ssv6006c/ssv6006C_reg.h	6442;"	d
+GET_RG_TURISMO_TRX_RAM_18	smac/hal/ssv6006c/ssv6006C_reg.h	6443;"	d
+GET_RG_TURISMO_TRX_RAM_19	smac/hal/ssv6006c/ssv6006C_reg.h	6444;"	d
+GET_RG_TURISMO_TRX_RAM_20	smac/hal/ssv6006c/ssv6006C_reg.h	6445;"	d
+GET_RG_TURISMO_TRX_RAM_21	smac/hal/ssv6006c/ssv6006C_reg.h	6446;"	d
+GET_RG_TURISMO_TRX_RAM_22	smac/hal/ssv6006c/ssv6006C_reg.h	6447;"	d
+GET_RG_TURISMO_TRX_RAM_23	smac/hal/ssv6006c/ssv6006C_reg.h	6448;"	d
+GET_RG_TURISMO_TRX_RAM_24	smac/hal/ssv6006c/ssv6006C_reg.h	6449;"	d
+GET_RG_TURISMO_TRX_RAM_25	smac/hal/ssv6006c/ssv6006C_reg.h	6450;"	d
+GET_RG_TURISMO_TRX_RAM_26	smac/hal/ssv6006c/ssv6006C_reg.h	6451;"	d
+GET_RG_TURISMO_TRX_RAM_27	smac/hal/ssv6006c/ssv6006C_reg.h	6452;"	d
+GET_RG_TURISMO_TRX_RAM_28	smac/hal/ssv6006c/ssv6006C_reg.h	6453;"	d
+GET_RG_TURISMO_TRX_RAM_29	smac/hal/ssv6006c/ssv6006C_reg.h	6454;"	d
+GET_RG_TURISMO_TRX_RAM_30	smac/hal/ssv6006c/ssv6006C_reg.h	6455;"	d
+GET_RG_TURISMO_TRX_RAM_31	smac/hal/ssv6006c/ssv6006C_reg.h	6456;"	d
+GET_RG_TURISMO_TRX_RCCAL_POLAR_INV	smac/hal/ssv6006c/ssv6006C_reg.h	6250;"	d
+GET_RG_TURISMO_TRX_RFG	smac/hal/ssv6006c/ssv6006C_reg.h	5073;"	d
+GET_RG_TURISMO_TRX_RFG_DPDCAL	smac/hal/ssv6006c/ssv6006C_reg.h	5722;"	d
+GET_RG_TURISMO_TRX_RFG_RXIQCAL	smac/hal/ssv6006c/ssv6006C_reg.h	5719;"	d
+GET_RG_TURISMO_TRX_RF_PHY_MODE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	6419;"	d
+GET_RG_TURISMO_TRX_RF_PHY_MODE_WIFI_MAC	smac/hal/ssv6006c/ssv6006C_reg.h	6420;"	d
+GET_RG_TURISMO_TRX_RSSI_CLOCK_GATING	smac/hal/ssv6006c/ssv6006C_reg.h	5194;"	d
+GET_RG_TURISMO_TRX_RSSI_EDGE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	6184;"	d
+GET_RG_TURISMO_TRX_RTC_CAL_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	6321;"	d
+GET_RG_TURISMO_TRX_RTC_CAL_TARGET_COUNT	smac/hal/ssv6006c/ssv6006C_reg.h	6319;"	d
+GET_RG_TURISMO_TRX_RTC_EN	smac/hal/ssv6006c/ssv6006C_reg.h	6336;"	d
+GET_RG_TURISMO_TRX_RTC_INT_ALARM_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	6339;"	d
+GET_RG_TURISMO_TRX_RTC_INT_SEC_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	6338;"	d
+GET_RG_TURISMO_TRX_RTC_OFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	6318;"	d
+GET_RG_TURISMO_TRX_RTC_OSC_RES_SW_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	6320;"	d
+GET_RG_TURISMO_TRX_RTC_OSC_RES_SW_MANUAL_EN	smac/hal/ssv6006c/ssv6006C_reg.h	6323;"	d
+GET_RG_TURISMO_TRX_RTC_RS1	smac/hal/ssv6006c/ssv6006C_reg.h	6313;"	d
+GET_RG_TURISMO_TRX_RTC_RS2	smac/hal/ssv6006c/ssv6006C_reg.h	6314;"	d
+GET_RG_TURISMO_TRX_RTC_SEC_ALARM_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	6344;"	d
+GET_RG_TURISMO_TRX_RTC_SEC_START_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	6343;"	d
+GET_RG_TURISMO_TRX_RXIQ_NOSHRK	smac/hal/ssv6006c/ssv6006C_reg.h	6180;"	d
+GET_RG_TURISMO_TRX_RXRF_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	5699;"	d
+GET_RG_TURISMO_TRX_RXRF_R2T_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	5708;"	d
+GET_RG_TURISMO_TRX_RXRF_T2R_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	5704;"	d
+GET_RG_TURISMO_TRX_RX_ABBOUT_TRI_STATE	smac/hal/ssv6006c/ssv6006C_reg.h	5130;"	d
+GET_RG_TURISMO_TRX_RX_ADCRSSI_CLKSEL	smac/hal/ssv6006c/ssv6006C_reg.h	5193;"	d
+GET_RG_TURISMO_TRX_RX_ADCRSSI_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	5191;"	d
+GET_RG_TURISMO_TRX_RX_ADC_CLKSEL	smac/hal/ssv6006c/ssv6006C_reg.h	5327;"	d
+GET_RG_TURISMO_TRX_RX_ADC_DNLEN	smac/hal/ssv6006c/ssv6006C_reg.h	5328;"	d
+GET_RG_TURISMO_TRX_RX_ADC_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	5092;"	d
+GET_RG_TURISMO_TRX_RX_ADC_METAEN	smac/hal/ssv6006c/ssv6006C_reg.h	5329;"	d
+GET_RG_TURISMO_TRX_RX_ADC_TFLAG	smac/hal/ssv6006c/ssv6006C_reg.h	5330;"	d
+GET_RG_TURISMO_TRX_RX_ADC_TSEL	smac/hal/ssv6006c/ssv6006C_reg.h	5331;"	d
+GET_RG_TURISMO_TRX_RX_AGC	smac/hal/ssv6006c/ssv6006C_reg.h	5070;"	d
+GET_RG_TURISMO_TRX_RX_DC_POLAR_INV	smac/hal/ssv6006c/ssv6006C_reg.h	6249;"	d
+GET_RG_TURISMO_TRX_RX_DC_RESOLUTION	smac/hal/ssv6006c/ssv6006C_reg.h	6251;"	d
+GET_RG_TURISMO_TRX_RX_DIV2_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	5084;"	d
+GET_RG_TURISMO_TRX_RX_FILTER_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	5090;"	d
+GET_RG_TURISMO_TRX_RX_GAIN_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	5067;"	d
+GET_RG_TURISMO_TRX_RX_IDACA_COARSE_PMOS_ON	smac/hal/ssv6006c/ssv6006C_reg.h	5195;"	d
+GET_RG_TURISMO_TRX_RX_IQCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	5714;"	d
+GET_RG_TURISMO_TRX_RX_IQCAL_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	5119;"	d
+GET_RG_TURISMO_TRX_RX_IQ_ALPHA	smac/hal/ssv6006c/ssv6006C_reg.h	6177;"	d
+GET_RG_TURISMO_TRX_RX_IQ_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	6179;"	d
+GET_RG_TURISMO_TRX_RX_IQ_THETA	smac/hal/ssv6006c/ssv6006C_reg.h	6178;"	d
+GET_RG_TURISMO_TRX_RX_LNA_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	5080;"	d
+GET_RG_TURISMO_TRX_RX_LNA_SETTLE	smac/hal/ssv6006c/ssv6006C_reg.h	5204;"	d
+GET_RG_TURISMO_TRX_RX_LNA_TRI_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	5203;"	d
+GET_RG_TURISMO_TRX_RX_LOBUF_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	5086;"	d
+GET_RG_TURISMO_TRX_RX_MIXER_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	5082;"	d
+GET_RG_TURISMO_TRX_RX_N_RCCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	5715;"	d
+GET_RG_TURISMO_TRX_RX_PRE_DC_RESOLUTION	smac/hal/ssv6006c/ssv6006C_reg.h	6259;"	d
+GET_RG_TURISMO_TRX_RX_RCCAL_40M_TARG	smac/hal/ssv6006c/ssv6006C_reg.h	6252;"	d
+GET_RG_TURISMO_TRX_RX_RCCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	5711;"	d
+GET_RG_TURISMO_TRX_RX_RCCAL_TARG	smac/hal/ssv6006c/ssv6006C_reg.h	6248;"	d
+GET_RG_TURISMO_TRX_RX_REC_LPFCORNER	smac/hal/ssv6006c/ssv6006C_reg.h	5192;"	d
+GET_RG_TURISMO_TRX_RX_RSSIADC_TH	smac/hal/ssv6006c/ssv6006C_reg.h	6181;"	d
+GET_RG_TURISMO_TRX_RX_RSSI_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	5094;"	d
+GET_RG_TURISMO_TRX_RX_SCALOAD_STEP0	smac/hal/ssv6006c/ssv6006C_reg.h	6159;"	d
+GET_RG_TURISMO_TRX_RX_SCALOAD_STEP1	smac/hal/ssv6006c/ssv6006C_reg.h	6160;"	d
+GET_RG_TURISMO_TRX_RX_SCALOAD_STEP2	smac/hal/ssv6006c/ssv6006C_reg.h	6161;"	d
+GET_RG_TURISMO_TRX_RX_SCALOAD_STEP3	smac/hal/ssv6006c/ssv6006C_reg.h	6162;"	d
+GET_RG_TURISMO_TRX_RX_SCALOAD_STEP4	smac/hal/ssv6006c/ssv6006C_reg.h	6163;"	d
+GET_RG_TURISMO_TRX_RX_SCALOAD_STEP5	smac/hal/ssv6006c/ssv6006C_reg.h	6164;"	d
+GET_RG_TURISMO_TRX_RX_SCALOAD_STEP6	smac/hal/ssv6006c/ssv6006C_reg.h	6165;"	d
+GET_RG_TURISMO_TRX_RX_SCAMA_STEP0	smac/hal/ssv6006c/ssv6006C_reg.h	6152;"	d
+GET_RG_TURISMO_TRX_RX_SCAMA_STEP1	smac/hal/ssv6006c/ssv6006C_reg.h	6153;"	d
+GET_RG_TURISMO_TRX_RX_SCAMA_STEP2	smac/hal/ssv6006c/ssv6006C_reg.h	6154;"	d
+GET_RG_TURISMO_TRX_RX_SCAMA_STEP3	smac/hal/ssv6006c/ssv6006C_reg.h	6155;"	d
+GET_RG_TURISMO_TRX_RX_SCAMA_STEP4	smac/hal/ssv6006c/ssv6006C_reg.h	6156;"	d
+GET_RG_TURISMO_TRX_RX_SCAMA_STEP5	smac/hal/ssv6006c/ssv6006C_reg.h	6157;"	d
+GET_RG_TURISMO_TRX_RX_SCAMA_STEP6	smac/hal/ssv6006c/ssv6006C_reg.h	6158;"	d
+GET_RG_TURISMO_TRX_RX_SQDC	smac/hal/ssv6006c/ssv6006C_reg.h	5137;"	d
+GET_RG_TURISMO_TRX_RX_TZ_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	5088;"	d
+GET_RG_TURISMO_TRX_RX_TZ_OUT_TRISTATE	smac/hal/ssv6006c/ssv6006C_reg.h	5116;"	d
+GET_RG_TURISMO_TRX_RX_TZ_OUT_TRISTATE_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	5115;"	d
+GET_RG_TURISMO_TRX_SARADC_5G_TSSI	smac/hal/ssv6006c/ssv6006C_reg.h	5338;"	d
+GET_RG_TURISMO_TRX_SARADC_THERMAL	smac/hal/ssv6006c/ssv6006C_reg.h	5341;"	d
+GET_RG_TURISMO_TRX_SARADC_TSSI	smac/hal/ssv6006c/ssv6006C_reg.h	5342;"	d
+GET_RG_TURISMO_TRX_SARADC_VRSEL	smac/hal/ssv6006c/ssv6006C_reg.h	5339;"	d
+GET_RG_TURISMO_TRX_SEC_CNT_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	6335;"	d
+GET_RG_TURISMO_TRX_SEL_DPLL_CLK	smac/hal/ssv6006c/ssv6006C_reg.h	6322;"	d
+GET_RG_TURISMO_TRX_SIGN_SWAP	smac/hal/ssv6006c/ssv6006C_reg.h	6189;"	d
+GET_RG_TURISMO_TRX_SLEEP_METHOD	smac/hal/ssv6006c/ssv6006C_reg.h	6332;"	d
+GET_RG_TURISMO_TRX_SLEEP_WAKE_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	6334;"	d
+GET_RG_TURISMO_TRX_SPECTRUM_BW	smac/hal/ssv6006c/ssv6006C_reg.h	6225;"	d
+GET_RG_TURISMO_TRX_SPECTRUM_EN	smac/hal/ssv6006c/ssv6006C_reg.h	6226;"	d
+GET_RG_TURISMO_TRX_SPECTRUM_LO_FIX	smac/hal/ssv6006c/ssv6006C_reg.h	6254;"	d
+GET_RG_TURISMO_TRX_SPECTRUM_PWR_UPDATE	smac/hal/ssv6006c/ssv6006C_reg.h	6255;"	d
+GET_RG_TURISMO_TRX_SPIS_MISO_DS	smac/hal/ssv6006c/ssv6006C_reg.h	6367;"	d
+GET_RG_TURISMO_TRX_SUB_DC	smac/hal/ssv6006c/ssv6006C_reg.h	6182;"	d
+GET_RG_TURISMO_TRX_SX5GB_AAC_ACCUMH	smac/hal/ssv6006c/ssv6006C_reg.h	6007;"	d
+GET_RG_TURISMO_TRX_SX5GB_AAC_ACCUML	smac/hal/ssv6006c/ssv6006C_reg.h	6008;"	d
+GET_RG_TURISMO_TRX_SX5GB_AAC_EN	smac/hal/ssv6006c/ssv6006C_reg.h	6012;"	d
+GET_RG_TURISMO_TRX_SX5GB_AAC_EN_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	6011;"	d
+GET_RG_TURISMO_TRX_SX5GB_AAC_EVA	smac/hal/ssv6006c/ssv6006C_reg.h	6014;"	d
+GET_RG_TURISMO_TRX_SX5GB_AAC_EVA_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	6013;"	d
+GET_RG_TURISMO_TRX_SX5GB_AAC_EVA_TS	smac/hal/ssv6006c/ssv6006C_reg.h	6010;"	d
+GET_RG_TURISMO_TRX_SX5GB_AAC_INIT	smac/hal/ssv6006c/ssv6006C_reg.h	6009;"	d
+GET_RG_TURISMO_TRX_SX5GB_AAC_TEST_EN	smac/hal/ssv6006c/ssv6006C_reg.h	6020;"	d
+GET_RG_TURISMO_TRX_SX5GB_AAC_TEST_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	6021;"	d
+GET_RG_TURISMO_TRX_SX5GB_CAL_INIT	smac/hal/ssv6006c/ssv6006C_reg.h	5920;"	d
+GET_RG_TURISMO_TRX_SX5GB_CHANNEL	smac/hal/ssv6006c/ssv6006C_reg.h	5890;"	d
+GET_RG_TURISMO_TRX_SX5GB_CP_IOST	smac/hal/ssv6006c/ssv6006C_reg.h	5946;"	d
+GET_RG_TURISMO_TRX_SX5GB_CP_IOST_POL	smac/hal/ssv6006c/ssv6006C_reg.h	5945;"	d
+GET_RG_TURISMO_TRX_SX5GB_CP_ISEL	smac/hal/ssv6006c/ssv6006C_reg.h	5942;"	d
+GET_RG_TURISMO_TRX_SX5GB_CP_ISEL50U	smac/hal/ssv6006c/ssv6006C_reg.h	5943;"	d
+GET_RG_TURISMO_TRX_SX5GB_CP_KP_DOUB	smac/hal/ssv6006c/ssv6006C_reg.h	5944;"	d
+GET_RG_TURISMO_TRX_SX5GB_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	6112;"	d
+GET_RG_TURISMO_TRX_SX5GB_DITHER_WEIGHT	smac/hal/ssv6006c/ssv6006C_reg.h	5995;"	d
+GET_RG_TURISMO_TRX_SX5GB_DIV_DMYBUF_EN	smac/hal/ssv6006c/ssv6006C_reg.h	5991;"	d
+GET_RG_TURISMO_TRX_SX5GB_DIV_PREVDD	smac/hal/ssv6006c/ssv6006C_reg.h	5987;"	d
+GET_RG_TURISMO_TRX_SX5GB_DIV_PSCVDD	smac/hal/ssv6006c/ssv6006C_reg.h	5988;"	d
+GET_RG_TURISMO_TRX_SX5GB_DIV_RST_H	smac/hal/ssv6006c/ssv6006C_reg.h	5989;"	d
+GET_RG_TURISMO_TRX_SX5GB_DIV_SDM_EDGE	smac/hal/ssv6006c/ssv6006C_reg.h	5990;"	d
+GET_RG_TURISMO_TRX_SX5GB_LDO_CP_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	5778;"	d
+GET_RG_TURISMO_TRX_SX5GB_LDO_DIV_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	5783;"	d
+GET_RG_TURISMO_TRX_SX5GB_LDO_FCOFFT	smac/hal/ssv6006c/ssv6006C_reg.h	5932;"	d
+GET_RG_TURISMO_TRX_SX5GB_LDO_LO_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	5780;"	d
+GET_RG_TURISMO_TRX_SX5GB_LDO_VCO_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	5782;"	d
+GET_RG_TURISMO_TRX_SX5GB_LO_TIMES	smac/hal/ssv6006c/ssv6006C_reg.h	5889;"	d
+GET_RG_TURISMO_TRX_SX5GB_LPF_C1	smac/hal/ssv6006c/ssv6006C_reg.h	5956;"	d
+GET_RG_TURISMO_TRX_SX5GB_LPF_C2	smac/hal/ssv6006c/ssv6006C_reg.h	5957;"	d
+GET_RG_TURISMO_TRX_SX5GB_LPF_C3	smac/hal/ssv6006c/ssv6006C_reg.h	5958;"	d
+GET_RG_TURISMO_TRX_SX5GB_LPF_R2	smac/hal/ssv6006c/ssv6006C_reg.h	5959;"	d
+GET_RG_TURISMO_TRX_SX5GB_LPF_R3	smac/hal/ssv6006c/ssv6006C_reg.h	5960;"	d
+GET_RG_TURISMO_TRX_SX5GB_LPF_VTUNE_TEST	smac/hal/ssv6006c/ssv6006C_reg.h	5969;"	d
+GET_RG_TURISMO_TRX_SX5GB_MIXAAC_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	5917;"	d
+GET_RG_TURISMO_TRX_SX5GB_MIXAAC_TAR	smac/hal/ssv6006c/ssv6006C_reg.h	6022;"	d
+GET_RG_TURISMO_TRX_SX5GB_MOD_ORDER	smac/hal/ssv6006c/ssv6006C_reg.h	5994;"	d
+GET_RG_TURISMO_TRX_SX5GB_PFD_DIV_EDGE	smac/hal/ssv6006c/ssv6006C_reg.h	5955;"	d
+GET_RG_TURISMO_TRX_SX5GB_PFD_REF_EDGE	smac/hal/ssv6006c/ssv6006C_reg.h	5954;"	d
+GET_RG_TURISMO_TRX_SX5GB_PFD_RST	smac/hal/ssv6006c/ssv6006C_reg.h	5900;"	d
+GET_RG_TURISMO_TRX_SX5GB_PFD_RST_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	5899;"	d
+GET_RG_TURISMO_TRX_SX5GB_PFD_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	5947;"	d
+GET_RG_TURISMO_TRX_SX5GB_PFD_SET	smac/hal/ssv6006c/ssv6006C_reg.h	5948;"	d
+GET_RG_TURISMO_TRX_SX5GB_PFD_SET1	smac/hal/ssv6006c/ssv6006C_reg.h	5949;"	d
+GET_RG_TURISMO_TRX_SX5GB_PFD_SET2	smac/hal/ssv6006c/ssv6006C_reg.h	5950;"	d
+GET_RG_TURISMO_TRX_SX5GB_PFD_TLSEL	smac/hal/ssv6006c/ssv6006C_reg.h	5953;"	d
+GET_RG_TURISMO_TRX_SX5GB_PFD_TRDN	smac/hal/ssv6006c/ssv6006C_reg.h	5952;"	d
+GET_RG_TURISMO_TRX_SX5GB_PFD_TRUP	smac/hal/ssv6006c/ssv6006C_reg.h	5951;"	d
+GET_RG_TURISMO_TRX_SX5GB_REPAAC_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	5918;"	d
+GET_RG_TURISMO_TRX_SX5GB_REPAAC_TAR	smac/hal/ssv6006c/ssv6006C_reg.h	6025;"	d
+GET_RG_TURISMO_TRX_SX5GB_RFCH_MAP_EN	smac/hal/ssv6006c/ssv6006C_reg.h	5888;"	d
+GET_RG_TURISMO_TRX_SX5GB_RFCTRL_CH_10_8	smac/hal/ssv6006c/ssv6006C_reg.h	5887;"	d
+GET_RG_TURISMO_TRX_SX5GB_RFCTRL_CH_7_0	smac/hal/ssv6006c/ssv6006C_reg.h	5886;"	d
+GET_RG_TURISMO_TRX_SX5GB_RFCTRL_F	smac/hal/ssv6006c/ssv6006C_reg.h	5885;"	d
+GET_RG_TURISMO_TRX_SX5GB_SBCAL_2ND_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	5914;"	d
+GET_RG_TURISMO_TRX_SX5GB_SBCAL_AW	smac/hal/ssv6006c/ssv6006C_reg.h	5915;"	d
+GET_RG_TURISMO_TRX_SX5GB_SBCAL_CT	smac/hal/ssv6006c/ssv6006C_reg.h	5999;"	d
+GET_RG_TURISMO_TRX_SX5GB_SBCAL_DIFFMIN	smac/hal/ssv6006c/ssv6006C_reg.h	6001;"	d
+GET_RG_TURISMO_TRX_SX5GB_SBCAL_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	5913;"	d
+GET_RG_TURISMO_TRX_SX5GB_SBCAL_NTARG	smac/hal/ssv6006c/ssv6006C_reg.h	6003;"	d
+GET_RG_TURISMO_TRX_SX5GB_SBCAL_NTARG_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	6002;"	d
+GET_RG_TURISMO_TRX_SX5GB_SBCAL_WT	smac/hal/ssv6006c/ssv6006C_reg.h	6000;"	d
+GET_RG_TURISMO_TRX_SX5GB_SUB_C0P5_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	5998;"	d
+GET_RG_TURISMO_TRX_SX5GB_SUB_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	5997;"	d
+GET_RG_TURISMO_TRX_SX5GB_SUB_SEL_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	5996;"	d
+GET_RG_TURISMO_TRX_SX5GB_TTL_ACCUM	smac/hal/ssv6006c/ssv6006C_reg.h	5964;"	d
+GET_RG_TURISMO_TRX_SX5GB_TTL_CPT	smac/hal/ssv6006c/ssv6006C_reg.h	5963;"	d
+GET_RG_TURISMO_TRX_SX5GB_TTL_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	5919;"	d
+GET_RG_TURISMO_TRX_SX5GB_TTL_FPT	smac/hal/ssv6006c/ssv6006C_reg.h	5962;"	d
+GET_RG_TURISMO_TRX_SX5GB_TTL_INIT	smac/hal/ssv6006c/ssv6006C_reg.h	5961;"	d
+GET_RG_TURISMO_TRX_SX5GB_TTL_SUB	smac/hal/ssv6006c/ssv6006C_reg.h	5965;"	d
+GET_RG_TURISMO_TRX_SX5GB_TTL_SUB_INV	smac/hal/ssv6006c/ssv6006C_reg.h	5966;"	d
+GET_RG_TURISMO_TRX_SX5GB_TTL_VH	smac/hal/ssv6006c/ssv6006C_reg.h	5967;"	d
+GET_RG_TURISMO_TRX_SX5GB_TTL_VL	smac/hal/ssv6006c/ssv6006C_reg.h	5968;"	d
+GET_RG_TURISMO_TRX_SX5GB_UOP_EN	smac/hal/ssv6006c/ssv6006C_reg.h	5902;"	d
+GET_RG_TURISMO_TRX_SX5GB_UOP_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	5901;"	d
+GET_RG_TURISMO_TRX_SX5GB_VCO_CS_AWH	smac/hal/ssv6006c/ssv6006C_reg.h	5976;"	d
+GET_RG_TURISMO_TRX_SX5GB_VCO_ISEL	smac/hal/ssv6006c/ssv6006C_reg.h	5971;"	d
+GET_RG_TURISMO_TRX_SX5GB_VCO_ISEL_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	5970;"	d
+GET_RG_TURISMO_TRX_SX5GB_VCO_KVDOUB	smac/hal/ssv6006c/ssv6006C_reg.h	5973;"	d
+GET_RG_TURISMO_TRX_SX5GB_VCO_RTAIL_SHIFT	smac/hal/ssv6006c/ssv6006C_reg.h	5975;"	d
+GET_RG_TURISMO_TRX_SX5GB_VCO_VARBSEL	smac/hal/ssv6006c/ssv6006C_reg.h	5974;"	d
+GET_RG_TURISMO_TRX_SX5GB_VCO_VCCBSEL	smac/hal/ssv6006c/ssv6006C_reg.h	5972;"	d
+GET_RG_TURISMO_TRX_SX5GB_VOAAC_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	5916;"	d
+GET_RG_TURISMO_TRX_SX5GB_VOAAC_TAR	smac/hal/ssv6006c/ssv6006C_reg.h	6004;"	d
+GET_RG_TURISMO_TRX_SXMIX_GMSEL	smac/hal/ssv6006c/ssv6006C_reg.h	5983;"	d
+GET_RG_TURISMO_TRX_SXMIX_IBIAS_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	5981;"	d
+GET_RG_TURISMO_TRX_SXMIX_SCA_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	6024;"	d
+GET_RG_TURISMO_TRX_SXMIX_SCA_SEL_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	6023;"	d
+GET_RG_TURISMO_TRX_SXMIX_SWB_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	5982;"	d
+GET_RG_TURISMO_TRX_SXREP_CSSEL	smac/hal/ssv6006c/ssv6006C_reg.h	5985;"	d
+GET_RG_TURISMO_TRX_SXREP_SCA_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	6027;"	d
+GET_RG_TURISMO_TRX_SXREP_SCA_SEL_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	6026;"	d
+GET_RG_TURISMO_TRX_SXREP_SWB_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	5984;"	d
+GET_RG_TURISMO_TRX_SX_5GB_EN	smac/hal/ssv6006c/ssv6006C_reg.h	5892;"	d
+GET_RG_TURISMO_TRX_SX_5GB_EN_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	5891;"	d
+GET_RG_TURISMO_TRX_SX_AAC_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	5393;"	d
+GET_RG_TURISMO_TRX_SX_BTRX_SIDE	smac/hal/ssv6006c/ssv6006C_reg.h	5423;"	d
+GET_RG_TURISMO_TRX_SX_CAL_INIT	smac/hal/ssv6006c/ssv6006C_reg.h	5395;"	d
+GET_RG_TURISMO_TRX_SX_CHANNEL	smac/hal/ssv6006c/ssv6006C_reg.h	5425;"	d
+GET_RG_TURISMO_TRX_SX_CP_IOST	smac/hal/ssv6006c/ssv6006C_reg.h	5433;"	d
+GET_RG_TURISMO_TRX_SX_CP_IOST_POL	smac/hal/ssv6006c/ssv6006C_reg.h	5432;"	d
+GET_RG_TURISMO_TRX_SX_CP_ISEL50U_BT	smac/hal/ssv6006c/ssv6006C_reg.h	5427;"	d
+GET_RG_TURISMO_TRX_SX_CP_ISEL50U_WF	smac/hal/ssv6006c/ssv6006C_reg.h	5430;"	d
+GET_RG_TURISMO_TRX_SX_CP_ISEL_BT	smac/hal/ssv6006c/ssv6006C_reg.h	5426;"	d
+GET_RG_TURISMO_TRX_SX_CP_ISEL_WF	smac/hal/ssv6006c/ssv6006C_reg.h	5429;"	d
+GET_RG_TURISMO_TRX_SX_CP_KP_DOUB_BT	smac/hal/ssv6006c/ssv6006C_reg.h	5428;"	d
+GET_RG_TURISMO_TRX_SX_CP_KP_DOUB_WF	smac/hal/ssv6006c/ssv6006C_reg.h	5431;"	d
+GET_RG_TURISMO_TRX_SX_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	5695;"	d
+GET_RG_TURISMO_TRX_SX_DITHER_WEIGHT	smac/hal/ssv6006c/ssv6006C_reg.h	5487;"	d
+GET_RG_TURISMO_TRX_SX_DIV_DMYBUF_EN	smac/hal/ssv6006c/ssv6006C_reg.h	5483;"	d
+GET_RG_TURISMO_TRX_SX_DIV_PREVDD	smac/hal/ssv6006c/ssv6006C_reg.h	5479;"	d
+GET_RG_TURISMO_TRX_SX_DIV_PSCVDD	smac/hal/ssv6006c/ssv6006C_reg.h	5480;"	d
+GET_RG_TURISMO_TRX_SX_DIV_RST_H	smac/hal/ssv6006c/ssv6006C_reg.h	5481;"	d
+GET_RG_TURISMO_TRX_SX_DIV_SDM_EDGE	smac/hal/ssv6006c/ssv6006C_reg.h	5482;"	d
+GET_RG_TURISMO_TRX_SX_EN	smac/hal/ssv6006c/ssv6006C_reg.h	5370;"	d
+GET_RG_TURISMO_TRX_SX_EN_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	5369;"	d
+GET_RG_TURISMO_TRX_SX_FREF_DOUB	smac/hal/ssv6006c/ssv6006C_reg.h	5422;"	d
+GET_RG_TURISMO_TRX_SX_LDO_CP_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	5145;"	d
+GET_RG_TURISMO_TRX_SX_LDO_DIV_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	5150;"	d
+GET_RG_TURISMO_TRX_SX_LDO_FCOFFT	smac/hal/ssv6006c/ssv6006C_reg.h	5407;"	d
+GET_RG_TURISMO_TRX_SX_LDO_LO_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	5147;"	d
+GET_RG_TURISMO_TRX_SX_LDO_VCO_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	5149;"	d
+GET_RG_TURISMO_TRX_SX_LO_TIMES	smac/hal/ssv6006c/ssv6006C_reg.h	5424;"	d
+GET_RG_TURISMO_TRX_SX_LPF_C1_BT	smac/hal/ssv6006c/ssv6006C_reg.h	5443;"	d
+GET_RG_TURISMO_TRX_SX_LPF_C1_WF	smac/hal/ssv6006c/ssv6006C_reg.h	5448;"	d
+GET_RG_TURISMO_TRX_SX_LPF_C2_BT	smac/hal/ssv6006c/ssv6006C_reg.h	5444;"	d
+GET_RG_TURISMO_TRX_SX_LPF_C2_WF	smac/hal/ssv6006c/ssv6006C_reg.h	5449;"	d
+GET_RG_TURISMO_TRX_SX_LPF_C3_BT	smac/hal/ssv6006c/ssv6006C_reg.h	5445;"	d
+GET_RG_TURISMO_TRX_SX_LPF_C3_WF	smac/hal/ssv6006c/ssv6006C_reg.h	5450;"	d
+GET_RG_TURISMO_TRX_SX_LPF_R2_BT	smac/hal/ssv6006c/ssv6006C_reg.h	5446;"	d
+GET_RG_TURISMO_TRX_SX_LPF_R2_WF	smac/hal/ssv6006c/ssv6006C_reg.h	5451;"	d
+GET_RG_TURISMO_TRX_SX_LPF_R3_BT	smac/hal/ssv6006c/ssv6006C_reg.h	5447;"	d
+GET_RG_TURISMO_TRX_SX_LPF_R3_WF	smac/hal/ssv6006c/ssv6006C_reg.h	5452;"	d
+GET_RG_TURISMO_TRX_SX_LPF_VTUNE_TEST	smac/hal/ssv6006c/ssv6006C_reg.h	5517;"	d
+GET_RG_TURISMO_TRX_SX_MOD_ORDER	smac/hal/ssv6006c/ssv6006C_reg.h	5486;"	d
+GET_RG_TURISMO_TRX_SX_PFD_DIV_EDGE	smac/hal/ssv6006c/ssv6006C_reg.h	5439;"	d
+GET_RG_TURISMO_TRX_SX_PFD_REF_EDGE	smac/hal/ssv6006c/ssv6006C_reg.h	5438;"	d
+GET_RG_TURISMO_TRX_SX_PFD_RST	smac/hal/ssv6006c/ssv6006C_reg.h	5378;"	d
+GET_RG_TURISMO_TRX_SX_PFD_RST_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	5377;"	d
+GET_RG_TURISMO_TRX_SX_PFD_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	5434;"	d
+GET_RG_TURISMO_TRX_SX_PFD_SET	smac/hal/ssv6006c/ssv6006C_reg.h	5435;"	d
+GET_RG_TURISMO_TRX_SX_PFD_SET1	smac/hal/ssv6006c/ssv6006C_reg.h	5436;"	d
+GET_RG_TURISMO_TRX_SX_PFD_SET2	smac/hal/ssv6006c/ssv6006C_reg.h	5437;"	d
+GET_RG_TURISMO_TRX_SX_PFD_TLSEL	smac/hal/ssv6006c/ssv6006C_reg.h	5442;"	d
+GET_RG_TURISMO_TRX_SX_PFD_TRDN	smac/hal/ssv6006c/ssv6006C_reg.h	5441;"	d
+GET_RG_TURISMO_TRX_SX_PFD_TRUP	smac/hal/ssv6006c/ssv6006C_reg.h	5440;"	d
+GET_RG_TURISMO_TRX_SX_RFCH_MAP_EN	smac/hal/ssv6006c/ssv6006C_reg.h	5420;"	d
+GET_RG_TURISMO_TRX_SX_RFCTRL_CH_10_8	smac/hal/ssv6006c/ssv6006C_reg.h	5419;"	d
+GET_RG_TURISMO_TRX_SX_RFCTRL_CH_7_0	smac/hal/ssv6006c/ssv6006C_reg.h	5418;"	d
+GET_RG_TURISMO_TRX_SX_RFCTRL_F	smac/hal/ssv6006c/ssv6006C_reg.h	5417;"	d
+GET_RG_TURISMO_TRX_SX_SBCAL_AW	smac/hal/ssv6006c/ssv6006C_reg.h	5392;"	d
+GET_RG_TURISMO_TRX_SX_SBCAL_CT	smac/hal/ssv6006c/ssv6006C_reg.h	5491;"	d
+GET_RG_TURISMO_TRX_SX_SBCAL_DIFFMIN	smac/hal/ssv6006c/ssv6006C_reg.h	5493;"	d
+GET_RG_TURISMO_TRX_SX_SBCAL_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	5391;"	d
+GET_RG_TURISMO_TRX_SX_SBCAL_NTARG	smac/hal/ssv6006c/ssv6006C_reg.h	5495;"	d
+GET_RG_TURISMO_TRX_SX_SBCAL_NTARG_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	5494;"	d
+GET_RG_TURISMO_TRX_SX_SBCAL_WT	smac/hal/ssv6006c/ssv6006C_reg.h	5492;"	d
+GET_RG_TURISMO_TRX_SX_SUB_C0P5_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	5490;"	d
+GET_RG_TURISMO_TRX_SX_SUB_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	5489;"	d
+GET_RG_TURISMO_TRX_SX_SUB_SEL_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	5488;"	d
+GET_RG_TURISMO_TRX_SX_TTL_ACCUM	smac/hal/ssv6006c/ssv6006C_reg.h	5512;"	d
+GET_RG_TURISMO_TRX_SX_TTL_CPT	smac/hal/ssv6006c/ssv6006C_reg.h	5511;"	d
+GET_RG_TURISMO_TRX_SX_TTL_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	5394;"	d
+GET_RG_TURISMO_TRX_SX_TTL_FPT	smac/hal/ssv6006c/ssv6006C_reg.h	5510;"	d
+GET_RG_TURISMO_TRX_SX_TTL_INIT	smac/hal/ssv6006c/ssv6006C_reg.h	5509;"	d
+GET_RG_TURISMO_TRX_SX_TTL_SUB	smac/hal/ssv6006c/ssv6006C_reg.h	5513;"	d
+GET_RG_TURISMO_TRX_SX_TTL_SUB_INV	smac/hal/ssv6006c/ssv6006C_reg.h	5514;"	d
+GET_RG_TURISMO_TRX_SX_TTL_VH	smac/hal/ssv6006c/ssv6006C_reg.h	5515;"	d
+GET_RG_TURISMO_TRX_SX_TTL_VL	smac/hal/ssv6006c/ssv6006C_reg.h	5516;"	d
+GET_RG_TURISMO_TRX_SX_UOP_EN	smac/hal/ssv6006c/ssv6006C_reg.h	5380;"	d
+GET_RG_TURISMO_TRX_SX_UOP_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	5379;"	d
+GET_RG_TURISMO_TRX_SX_VCO_CS_AWH	smac/hal/ssv6006c/ssv6006C_reg.h	5464;"	d
+GET_RG_TURISMO_TRX_SX_VCO_ISEL_BT	smac/hal/ssv6006c/ssv6006C_reg.h	5454;"	d
+GET_RG_TURISMO_TRX_SX_VCO_ISEL_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	5453;"	d
+GET_RG_TURISMO_TRX_SX_VCO_ISEL_WF	smac/hal/ssv6006c/ssv6006C_reg.h	5458;"	d
+GET_RG_TURISMO_TRX_SX_VCO_KVDOUB_BT	smac/hal/ssv6006c/ssv6006C_reg.h	5457;"	d
+GET_RG_TURISMO_TRX_SX_VCO_KVDOUB_WF	smac/hal/ssv6006c/ssv6006C_reg.h	5461;"	d
+GET_RG_TURISMO_TRX_SX_VCO_LPM_BT	smac/hal/ssv6006c/ssv6006C_reg.h	5455;"	d
+GET_RG_TURISMO_TRX_SX_VCO_LPM_WF	smac/hal/ssv6006c/ssv6006C_reg.h	5459;"	d
+GET_RG_TURISMO_TRX_SX_VCO_RTAIL_SHIFT	smac/hal/ssv6006c/ssv6006C_reg.h	5463;"	d
+GET_RG_TURISMO_TRX_SX_VCO_RXOB_AW	smac/hal/ssv6006c/ssv6006C_reg.h	5475;"	d
+GET_RG_TURISMO_TRX_SX_VCO_TXOB_AW	smac/hal/ssv6006c/ssv6006C_reg.h	5474;"	d
+GET_RG_TURISMO_TRX_SX_VCO_VARBSEL	smac/hal/ssv6006c/ssv6006C_reg.h	5462;"	d
+GET_RG_TURISMO_TRX_SX_VCO_VCCBSEL_BT	smac/hal/ssv6006c/ssv6006C_reg.h	5456;"	d
+GET_RG_TURISMO_TRX_SX_VCO_VCCBSEL_WF	smac/hal/ssv6006c/ssv6006C_reg.h	5460;"	d
+GET_RG_TURISMO_TRX_SX_XTAL_FREQ	smac/hal/ssv6006c/ssv6006C_reg.h	5421;"	d
+GET_RG_TURISMO_TRX_TONE_GEN_EN	smac/hal/ssv6006c/ssv6006C_reg.h	6198;"	d
+GET_RG_TURISMO_TRX_TONE_SCALE	smac/hal/ssv6006c/ssv6006C_reg.h	6196;"	d
+GET_RG_TURISMO_TRX_TXBTPA_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	5700;"	d
+GET_RG_TURISMO_TRX_TXDAC_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	5696;"	d
+GET_RG_TURISMO_TRX_TXDAC_R2T_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	5705;"	d
+GET_RG_TURISMO_TRX_TXDAC_T2R_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	5701;"	d
+GET_RG_TURISMO_TRX_TXGAIN_PHYCTRL	smac/hal/ssv6006c/ssv6006C_reg.h	5069;"	d
+GET_RG_TURISMO_TRX_TXIQ_NOSHRK	smac/hal/ssv6006c/ssv6006C_reg.h	6193;"	d
+GET_RG_TURISMO_TRX_TXLPF_BYPASS	smac/hal/ssv6006c/ssv6006C_reg.h	5126;"	d
+GET_RG_TURISMO_TRX_TXLPF_GMCELL	smac/hal/ssv6006c/ssv6006C_reg.h	5232;"	d
+GET_RG_TURISMO_TRX_TXMOD_GMCELL	smac/hal/ssv6006c/ssv6006C_reg.h	5231;"	d
+GET_RG_TURISMO_TRX_TXPA_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	5698;"	d
+GET_RG_TURISMO_TRX_TXPA_R2T_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	5707;"	d
+GET_RG_TURISMO_TRX_TXPA_T2R_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	5703;"	d
+GET_RG_TURISMO_TRX_TXPGA_MAIN	smac/hal/ssv6006c/ssv6006C_reg.h	5229;"	d
+GET_RG_TURISMO_TRX_TXPGA_STEER	smac/hal/ssv6006c/ssv6006C_reg.h	5230;"	d
+GET_RG_TURISMO_TRX_TXRF_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	5697;"	d
+GET_RG_TURISMO_TRX_TXRF_R2T_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	5706;"	d
+GET_RG_TURISMO_TRX_TXRF_T2R_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	5702;"	d
+GET_RG_TURISMO_TRX_TX_BT_PA_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	5106;"	d
+GET_RG_TURISMO_TRX_TX_CAPSW_STEP0	smac/hal/ssv6006c/ssv6006C_reg.h	6166;"	d
+GET_RG_TURISMO_TRX_TX_CAPSW_STEP1	smac/hal/ssv6006c/ssv6006C_reg.h	6167;"	d
+GET_RG_TURISMO_TRX_TX_CAPSW_STEP2	smac/hal/ssv6006c/ssv6006C_reg.h	6168;"	d
+GET_RG_TURISMO_TRX_TX_CAPSW_STEP3	smac/hal/ssv6006c/ssv6006C_reg.h	6169;"	d
+GET_RG_TURISMO_TRX_TX_CAPSW_STEP4	smac/hal/ssv6006c/ssv6006C_reg.h	6170;"	d
+GET_RG_TURISMO_TRX_TX_CAPSW_STEP5	smac/hal/ssv6006c/ssv6006C_reg.h	6171;"	d
+GET_RG_TURISMO_TRX_TX_CAPSW_STEP6	smac/hal/ssv6006c/ssv6006C_reg.h	6172;"	d
+GET_RG_TURISMO_TRX_TX_DAC_CAL_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	5113;"	d
+GET_RG_TURISMO_TRX_TX_DAC_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	5100;"	d
+GET_RG_TURISMO_TRX_TX_DAC_TSEL	smac/hal/ssv6006c/ssv6006C_reg.h	5356;"	d
+GET_RG_TURISMO_TRX_TX_DCCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	5712;"	d
+GET_RG_TURISMO_TRX_TX_DIV2_BUF_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	5104;"	d
+GET_RG_TURISMO_TRX_TX_DIV2_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	5102;"	d
+GET_RG_TURISMO_TRX_TX_DPDGM_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	5196;"	d
+GET_RG_TURISMO_TRX_TX_DPD_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	5197;"	d
+GET_RG_TURISMO_TRX_TX_DPD_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	5121;"	d
+GET_RG_TURISMO_TRX_TX_EN_VOLTAGE_IN	smac/hal/ssv6006c/ssv6006C_reg.h	5127;"	d
+GET_RG_TURISMO_TRX_TX_FREQ_OFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	6195;"	d
+GET_RG_TURISMO_TRX_TX_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	5077;"	d
+GET_RG_TURISMO_TRX_TX_GAIN_DPDCAL	smac/hal/ssv6006c/ssv6006C_reg.h	5724;"	d
+GET_RG_TURISMO_TRX_TX_GAIN_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	5068;"	d
+GET_RG_TURISMO_TRX_TX_GAIN_RXIQCAL	smac/hal/ssv6006c/ssv6006C_reg.h	5721;"	d
+GET_RG_TURISMO_TRX_TX_GAIN_TXCAL	smac/hal/ssv6006c/ssv6006C_reg.h	5718;"	d
+GET_RG_TURISMO_TRX_TX_IQCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	5713;"	d
+GET_RG_TURISMO_TRX_TX_IQCAL_TIME	smac/hal/ssv6006c/ssv6006C_reg.h	6194;"	d
+GET_RG_TURISMO_TRX_TX_IQ_ALPHA	smac/hal/ssv6006c/ssv6006C_reg.h	6190;"	d
+GET_RG_TURISMO_TRX_TX_IQ_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	6192;"	d
+GET_RG_TURISMO_TRX_TX_IQ_THETA	smac/hal/ssv6006c/ssv6006C_reg.h	6191;"	d
+GET_RG_TURISMO_TRX_TX_MOD_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	5098;"	d
+GET_RG_TURISMO_TRX_TX_PA_LDO_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	5142;"	d
+GET_RG_TURISMO_TRX_TX_PA_LDO_SEL_RES	smac/hal/ssv6006c/ssv6006C_reg.h	5215;"	d
+GET_RG_TURISMO_TRX_TX_PA_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	5096;"	d
+GET_RG_TURISMO_TRX_TX_SELF_MIXER_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	5117;"	d
+GET_RG_TURISMO_TRX_TX_TRSW_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	5078;"	d
+GET_RG_TURISMO_TRX_TX_TSSI_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	5198;"	d
+GET_RG_TURISMO_TRX_TX_TSSI_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	5199;"	d
+GET_RG_TURISMO_TRX_TX_TSSI_TEST	smac/hal/ssv6006c/ssv6006C_reg.h	5200;"	d
+GET_RG_TURISMO_TRX_TX_TSSI_TESTMODE	smac/hal/ssv6006c/ssv6006C_reg.h	5201;"	d
+GET_RG_TURISMO_TRX_TX_UP8X_MAN_EN	smac/hal/ssv6006c/ssv6006C_reg.h	6199;"	d
+GET_RG_TURISMO_TRX_TX_VTOI_CURRENT	smac/hal/ssv6006c/ssv6006C_reg.h	5235;"	d
+GET_RG_TURISMO_TRX_TX_VTOI_FS	smac/hal/ssv6006c/ssv6006C_reg.h	5238;"	d
+GET_RG_TURISMO_TRX_TX_VTOI_GM	smac/hal/ssv6006c/ssv6006C_reg.h	5236;"	d
+GET_RG_TURISMO_TRX_TX_VTOI_OPTION	smac/hal/ssv6006c/ssv6006C_reg.h	5237;"	d
+GET_RG_TURISMO_TRX_VO5GB_AAC_IMAX	smac/hal/ssv6006c/ssv6006C_reg.h	6006;"	d
+GET_RG_TURISMO_TRX_VO5GB_AAC_IOST	smac/hal/ssv6006c/ssv6006C_reg.h	6005;"	d
+GET_RG_TURISMO_TRX_VOBF_CAPIMB	smac/hal/ssv6006c/ssv6006C_reg.h	5477;"	d
+GET_RG_TURISMO_TRX_VOBF_CAPIMB_POL	smac/hal/ssv6006c/ssv6006C_reg.h	5476;"	d
+GET_RG_TURISMO_TRX_VOBF_DIVBFSEL	smac/hal/ssv6006c/ssv6006C_reg.h	5473;"	d
+GET_RG_TURISMO_TRX_VOBF_RXMBSEL_BT	smac/hal/ssv6006c/ssv6006C_reg.h	5467;"	d
+GET_RG_TURISMO_TRX_VOBF_RXMBSEL_WF	smac/hal/ssv6006c/ssv6006C_reg.h	5471;"	d
+GET_RG_TURISMO_TRX_VOBF_RXOBSEL_BT	smac/hal/ssv6006c/ssv6006C_reg.h	5468;"	d
+GET_RG_TURISMO_TRX_VOBF_RXOBSEL_WF	smac/hal/ssv6006c/ssv6006C_reg.h	5472;"	d
+GET_RG_TURISMO_TRX_VOBF_TXMBSEL_BT	smac/hal/ssv6006c/ssv6006C_reg.h	5465;"	d
+GET_RG_TURISMO_TRX_VOBF_TXMBSEL_WF	smac/hal/ssv6006c/ssv6006C_reg.h	5469;"	d
+GET_RG_TURISMO_TRX_VOBF_TXOBSEL_BT	smac/hal/ssv6006c/ssv6006C_reg.h	5466;"	d
+GET_RG_TURISMO_TRX_VOBF_TXOBSEL_WF	smac/hal/ssv6006c/ssv6006C_reg.h	5470;"	d
+GET_RG_TURISMO_TRX_VO_AAC_EN	smac/hal/ssv6006c/ssv6006C_reg.h	5504;"	d
+GET_RG_TURISMO_TRX_VO_AAC_EN_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	5503;"	d
+GET_RG_TURISMO_TRX_VO_AAC_EVA	smac/hal/ssv6006c/ssv6006C_reg.h	5506;"	d
+GET_RG_TURISMO_TRX_VO_AAC_EVA_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	5505;"	d
+GET_RG_TURISMO_TRX_VO_AAC_EVA_TS	smac/hal/ssv6006c/ssv6006C_reg.h	5502;"	d
+GET_RG_TURISMO_TRX_VO_AAC_IMAX	smac/hal/ssv6006c/ssv6006C_reg.h	5500;"	d
+GET_RG_TURISMO_TRX_VO_AAC_INIT	smac/hal/ssv6006c/ssv6006C_reg.h	5501;"	d
+GET_RG_TURISMO_TRX_VO_AAC_IOST_BT	smac/hal/ssv6006c/ssv6006C_reg.h	5497;"	d
+GET_RG_TURISMO_TRX_VO_AAC_IOST_WF	smac/hal/ssv6006c/ssv6006C_reg.h	5499;"	d
+GET_RG_TURISMO_TRX_VO_AAC_TAR_BT	smac/hal/ssv6006c/ssv6006C_reg.h	5496;"	d
+GET_RG_TURISMO_TRX_VO_AAC_TAR_WF	smac/hal/ssv6006c/ssv6006C_reg.h	5498;"	d
+GET_RG_TURISMO_TRX_VO_AAC_TEST_EN	smac/hal/ssv6006c/ssv6006C_reg.h	5507;"	d
+GET_RG_TURISMO_TRX_VO_AAC_TEST_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	5508;"	d
+GET_RG_TURISMO_TRX_WF_EN_TX_PA_VIN33	smac/hal/ssv6006c/ssv6006C_reg.h	5209;"	d
+GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	5577;"	d
+GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	5575;"	d
+GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	5557;"	d
+GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	5555;"	d
+GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	5553;"	d
+GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	5551;"	d
+GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	5549;"	d
+GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	5547;"	d
+GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	5573;"	d
+GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	5571;"	d
+GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	5569;"	d
+GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	5567;"	d
+GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	5565;"	d
+GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	5563;"	d
+GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	5561;"	d
+GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	5559;"	d
+GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	5609;"	d
+GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	5607;"	d
+GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	5589;"	d
+GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	5587;"	d
+GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	5585;"	d
+GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	5583;"	d
+GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	5581;"	d
+GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	5579;"	d
+GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	5605;"	d
+GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	5603;"	d
+GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	5601;"	d
+GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	5599;"	d
+GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	5597;"	d
+GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	5595;"	d
+GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	5593;"	d
+GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	5591;"	d
+GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	5578;"	d
+GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	5576;"	d
+GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	5558;"	d
+GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	5556;"	d
+GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	5554;"	d
+GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	5552;"	d
+GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	5550;"	d
+GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	5548;"	d
+GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	5574;"	d
+GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	5572;"	d
+GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	5570;"	d
+GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	5568;"	d
+GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	5566;"	d
+GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	5564;"	d
+GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	5562;"	d
+GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	5560;"	d
+GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	5610;"	d
+GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	5608;"	d
+GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	5590;"	d
+GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	5588;"	d
+GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	5586;"	d
+GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	5584;"	d
+GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	5582;"	d
+GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	5580;"	d
+GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	5606;"	d
+GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	5604;"	d
+GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	5602;"	d
+GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	5600;"	d
+GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	5598;"	d
+GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	5596;"	d
+GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	5594;"	d
+GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	5592;"	d
+GET_RG_TURISMO_TRX_WF_N_RX_ABBCFIX	smac/hal/ssv6006c/ssv6006C_reg.h	5170;"	d
+GET_RG_TURISMO_TRX_WF_N_RX_ABBCTUNE	smac/hal/ssv6006c/ssv6006C_reg.h	5165;"	d
+GET_RG_TURISMO_TRX_WF_N_RX_ABB_BT_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	5172;"	d
+GET_RG_TURISMO_TRX_WF_N_RX_ABB_IDIV3	smac/hal/ssv6006c/ssv6006C_reg.h	5173;"	d
+GET_RG_TURISMO_TRX_WF_N_RX_ABB_N_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	5171;"	d
+GET_RG_TURISMO_TRX_WF_N_RX_EN_IDACA_COARSE	smac/hal/ssv6006c/ssv6006C_reg.h	5174;"	d
+GET_RG_TURISMO_TRX_WF_N_RX_EN_LOOPA	smac/hal/ssv6006c/ssv6006C_reg.h	5175;"	d
+GET_RG_TURISMO_TRX_WF_N_RX_FILTERI1ST	smac/hal/ssv6006c/ssv6006C_reg.h	5167;"	d
+GET_RG_TURISMO_TRX_WF_N_RX_FILTERI2ND	smac/hal/ssv6006c/ssv6006C_reg.h	5168;"	d
+GET_RG_TURISMO_TRX_WF_N_RX_FILTERI3RD	smac/hal/ssv6006c/ssv6006C_reg.h	5169;"	d
+GET_RG_TURISMO_TRX_WF_N_RX_FILTERI_COARSE	smac/hal/ssv6006c/ssv6006C_reg.h	5166;"	d
+GET_RG_TURISMO_TRX_WF_N_RX_FILTERVCM	smac/hal/ssv6006c/ssv6006C_reg.h	5176;"	d
+GET_RG_TURISMO_TRX_WF_N_RX_OUTVCM	smac/hal/ssv6006c/ssv6006C_reg.h	5177;"	d
+GET_RG_TURISMO_TRX_WF_PABIAS_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	5221;"	d
+GET_RG_TURISMO_TRX_WF_PACELL_EN	smac/hal/ssv6006c/ssv6006C_reg.h	5220;"	d
+GET_RG_TURISMO_TRX_WF_RX_ABBCFIX	smac/hal/ssv6006c/ssv6006C_reg.h	5157;"	d
+GET_RG_TURISMO_TRX_WF_RX_ABBCTUNE	smac/hal/ssv6006c/ssv6006C_reg.h	5152;"	d
+GET_RG_TURISMO_TRX_WF_RX_ABB_BT_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	5159;"	d
+GET_RG_TURISMO_TRX_WF_RX_ABB_IDIV3	smac/hal/ssv6006c/ssv6006C_reg.h	5160;"	d
+GET_RG_TURISMO_TRX_WF_RX_ABB_N_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	5158;"	d
+GET_RG_TURISMO_TRX_WF_RX_ADC_CLOAD	smac/hal/ssv6006c/ssv6006C_reg.h	5334;"	d
+GET_RG_TURISMO_TRX_WF_RX_ADC_ICMP	smac/hal/ssv6006c/ssv6006C_reg.h	5332;"	d
+GET_RG_TURISMO_TRX_WF_RX_ADC_VCMI	smac/hal/ssv6006c/ssv6006C_reg.h	5333;"	d
+GET_RG_TURISMO_TRX_WF_RX_DCCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	5709;"	d
+GET_RG_TURISMO_TRX_WF_RX_EN_IDACA_COARSE	smac/hal/ssv6006c/ssv6006C_reg.h	5161;"	d
+GET_RG_TURISMO_TRX_WF_RX_EN_LOOPA	smac/hal/ssv6006c/ssv6006C_reg.h	5162;"	d
+GET_RG_TURISMO_TRX_WF_RX_FILTERI1ST	smac/hal/ssv6006c/ssv6006C_reg.h	5154;"	d
+GET_RG_TURISMO_TRX_WF_RX_FILTERI2ND	smac/hal/ssv6006c/ssv6006C_reg.h	5155;"	d
+GET_RG_TURISMO_TRX_WF_RX_FILTERI3RD	smac/hal/ssv6006c/ssv6006C_reg.h	5156;"	d
+GET_RG_TURISMO_TRX_WF_RX_FILTERI_COARSE	smac/hal/ssv6006c/ssv6006C_reg.h	5153;"	d
+GET_RG_TURISMO_TRX_WF_RX_FILTERVCM	smac/hal/ssv6006c/ssv6006C_reg.h	5163;"	d
+GET_RG_TURISMO_TRX_WF_RX_HG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	5246;"	d
+GET_RG_TURISMO_TRX_WF_RX_HG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	5241;"	d
+GET_RG_TURISMO_TRX_WF_RX_HG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	5242;"	d
+GET_RG_TURISMO_TRX_WF_RX_HG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	5243;"	d
+GET_RG_TURISMO_TRX_WF_RX_HG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	5239;"	d
+GET_RG_TURISMO_TRX_WF_RX_HG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	5247;"	d
+GET_RG_TURISMO_TRX_WF_RX_HG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	5248;"	d
+GET_RG_TURISMO_TRX_WF_RX_HG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	5244;"	d
+GET_RG_TURISMO_TRX_WF_RX_HG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	5240;"	d
+GET_RG_TURISMO_TRX_WF_RX_HG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	5245;"	d
+GET_RG_TURISMO_TRX_WF_RX_HG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	5249;"	d
+GET_RG_TURISMO_TRX_WF_RX_LG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	5268;"	d
+GET_RG_TURISMO_TRX_WF_RX_LG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	5263;"	d
+GET_RG_TURISMO_TRX_WF_RX_LG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	5264;"	d
+GET_RG_TURISMO_TRX_WF_RX_LG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	5265;"	d
+GET_RG_TURISMO_TRX_WF_RX_LG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	5261;"	d
+GET_RG_TURISMO_TRX_WF_RX_LG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	5269;"	d
+GET_RG_TURISMO_TRX_WF_RX_LG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	5270;"	d
+GET_RG_TURISMO_TRX_WF_RX_LG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	5266;"	d
+GET_RG_TURISMO_TRX_WF_RX_LG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	5262;"	d
+GET_RG_TURISMO_TRX_WF_RX_LG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	5267;"	d
+GET_RG_TURISMO_TRX_WF_RX_LG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	5271;"	d
+GET_RG_TURISMO_TRX_WF_RX_MG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	5257;"	d
+GET_RG_TURISMO_TRX_WF_RX_MG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	5252;"	d
+GET_RG_TURISMO_TRX_WF_RX_MG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	5253;"	d
+GET_RG_TURISMO_TRX_WF_RX_MG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	5254;"	d
+GET_RG_TURISMO_TRX_WF_RX_MG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	5250;"	d
+GET_RG_TURISMO_TRX_WF_RX_MG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	5258;"	d
+GET_RG_TURISMO_TRX_WF_RX_MG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	5259;"	d
+GET_RG_TURISMO_TRX_WF_RX_MG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	5255;"	d
+GET_RG_TURISMO_TRX_WF_RX_MG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	5251;"	d
+GET_RG_TURISMO_TRX_WF_RX_MG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	5256;"	d
+GET_RG_TURISMO_TRX_WF_RX_MG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	5260;"	d
+GET_RG_TURISMO_TRX_WF_RX_OUTVCM	smac/hal/ssv6006c/ssv6006C_reg.h	5164;"	d
+GET_RG_TURISMO_TRX_WF_RX_ULG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	5279;"	d
+GET_RG_TURISMO_TRX_WF_RX_ULG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	5274;"	d
+GET_RG_TURISMO_TRX_WF_RX_ULG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	5275;"	d
+GET_RG_TURISMO_TRX_WF_RX_ULG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	5276;"	d
+GET_RG_TURISMO_TRX_WF_RX_ULG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	5272;"	d
+GET_RG_TURISMO_TRX_WF_RX_ULG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	5280;"	d
+GET_RG_TURISMO_TRX_WF_RX_ULG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	5281;"	d
+GET_RG_TURISMO_TRX_WF_RX_ULG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	5277;"	d
+GET_RG_TURISMO_TRX_WF_RX_ULG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	5273;"	d
+GET_RG_TURISMO_TRX_WF_RX_ULG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	5278;"	d
+GET_RG_TURISMO_TRX_WF_RX_ULG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	5282;"	d
+GET_RG_TURISMO_TRX_WF_TXLPF_BOOSTI	smac/hal/ssv6006c/ssv6006C_reg.h	5350;"	d
+GET_RG_TURISMO_TRX_WF_TXPGA_CAPSW	smac/hal/ssv6006c/ssv6006C_reg.h	5205;"	d
+GET_RG_TURISMO_TRX_WF_TX_BTPASW	smac/hal/ssv6006c/ssv6006C_reg.h	5208;"	d
+GET_RG_TURISMO_TRX_WF_TX_DACI1ST	smac/hal/ssv6006c/ssv6006C_reg.h	5344;"	d
+GET_RG_TURISMO_TRX_WF_TX_DACLPF_ICOARSE	smac/hal/ssv6006c/ssv6006C_reg.h	5345;"	d
+GET_RG_TURISMO_TRX_WF_TX_DACLPF_IFINE	smac/hal/ssv6006c/ssv6006C_reg.h	5346;"	d
+GET_RG_TURISMO_TRX_WF_TX_DACLPF_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	5347;"	d
+GET_RG_TURISMO_TRX_WF_TX_DAC_CKEDGE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	5352;"	d
+GET_RG_TURISMO_TRX_WF_TX_DAC_IATTN	smac/hal/ssv6006c/ssv6006C_reg.h	5349;"	d
+GET_RG_TURISMO_TRX_WF_TX_DAC_IBIAS	smac/hal/ssv6006c/ssv6006C_reg.h	5348;"	d
+GET_RG_TURISMO_TRX_WF_TX_DAC_IOFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	5354;"	d
+GET_RG_TURISMO_TRX_WF_TX_DAC_OS	smac/hal/ssv6006c/ssv6006C_reg.h	5353;"	d
+GET_RG_TURISMO_TRX_WF_TX_DAC_QOFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	5355;"	d
+GET_RG_TURISMO_TRX_WF_TX_DAC_RCAL	smac/hal/ssv6006c/ssv6006C_reg.h	5351;"	d
+GET_RG_TURISMO_TRX_WF_TX_DIV_VSET	smac/hal/ssv6006c/ssv6006C_reg.h	5206;"	d
+GET_RG_TURISMO_TRX_WF_TX_GAIN_OFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	5233;"	d
+GET_RG_TURISMO_TRX_WF_TX_LOBUF_VSET	smac/hal/ssv6006c/ssv6006C_reg.h	5207;"	d
+GET_RG_TURISMO_TRX_WF_TX_PA1_VCAS	smac/hal/ssv6006c/ssv6006C_reg.h	5222;"	d
+GET_RG_TURISMO_TRX_WF_TX_PA2_VCAS	smac/hal/ssv6006c/ssv6006C_reg.h	5223;"	d
+GET_RG_TURISMO_TRX_WF_TX_PA3_VCAS	smac/hal/ssv6006c/ssv6006C_reg.h	5224;"	d
+GET_RG_TURISMO_TRX_XO_CBANKI	smac/hal/ssv6006c/ssv6006C_reg.h	6281;"	d
+GET_RG_TURISMO_TRX_XO_CBANKO	smac/hal/ssv6006c/ssv6006C_reg.h	6282;"	d
+GET_RG_TURISMO_TRX_XO_LDO_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	6277;"	d
+GET_RG_TURISMO_TRX_XO_TIMMER	smac/hal/ssv6006c/ssv6006C_reg.h	6294;"	d
+GET_RG_TXBTPA_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	7069;"	d
+GET_RG_TXDAC_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	7065;"	d
+GET_RG_TXDAC_R2T_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	7074;"	d
+GET_RG_TXDAC_T2R_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	7070;"	d
+GET_RG_TXD_SEL	include/ssv6200_reg.h	3914;"	d
+GET_RG_TXD_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	8232;"	d
+GET_RG_TXGAIN_MANUAL	include/ssv6200_reg.h	4612;"	d
+GET_RG_TXGAIN_PHYCTRL	include/ssv6200_reg.h	4610;"	d
+GET_RG_TXGAIN_PHYCTRL	smac/hal/ssv6006c/ssv6006C_reg.h	6463;"	d
+GET_RG_TXIQ_CLP_THD_I	include/ssv6200_reg.h	4347;"	d
+GET_RG_TXIQ_CLP_THD_I	smac/hal/ssv6006c/ssv6006C_reg.h	7941;"	d
+GET_RG_TXIQ_CLP_THD_Q	include/ssv6200_reg.h	4348;"	d
+GET_RG_TXIQ_CLP_THD_Q	smac/hal/ssv6006c/ssv6006C_reg.h	7942;"	d
+GET_RG_TXIQ_EMU_IDX	include/ssv6200_reg.h	4353;"	d
+GET_RG_TXIQ_NOSHRINK	include/ssv6200_reg.h	4359;"	d
+GET_RG_TXIQ_NOSHRK	smac/hal/ssv6006c/ssv6006C_reg.h	7594;"	d
+GET_RG_TXLPF_BOOSTI	include/ssv6200_reg.h	4642;"	d
+GET_RG_TXLPF_BYPASS	include/ssv6200_reg.h	4641;"	d
+GET_RG_TXLPF_BYPASS	smac/hal/ssv6006c/ssv6006C_reg.h	6520;"	d
+GET_RG_TXLPF_GMCELL	include/ssv6200_reg.h	4563;"	d
+GET_RG_TXLPF_GMCELL	smac/hal/ssv6006c/ssv6006C_reg.h	6624;"	d
+GET_RG_TXMOD_GMCELL	include/ssv6200_reg.h	4562;"	d
+GET_RG_TXMOD_GMCELL	smac/hal/ssv6006c/ssv6006C_reg.h	6623;"	d
+GET_RG_TXPA_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	7067;"	d
+GET_RG_TXPA_R2T_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	7076;"	d
+GET_RG_TXPA_T2R_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	7072;"	d
+GET_RG_TXPGA_CAPSW	include/ssv6200_reg.h	4559;"	d
+GET_RG_TXPGA_MAIN	include/ssv6200_reg.h	4560;"	d
+GET_RG_TXPGA_MAIN	smac/hal/ssv6006c/ssv6006C_reg.h	6621;"	d
+GET_RG_TXPGA_STEER	include/ssv6200_reg.h	4561;"	d
+GET_RG_TXPGA_STEER	smac/hal/ssv6006c/ssv6006C_reg.h	6622;"	d
+GET_RG_TXPWRLVL	include/ssv6200_reg.h	3904;"	d
+GET_RG_TXPWRLVL	smac/hal/ssv6006c/ssv6006C_reg.h	8223;"	d
+GET_RG_TXPWRLVL_SEL	include/ssv6200_reg.h	3872;"	d
+GET_RG_TXPWRLVL_SET	include/ssv6200_reg.h	3871;"	d
+GET_RG_TXRF_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	7066;"	d
+GET_RG_TXRF_R2T_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	7075;"	d
+GET_RG_TXRF_T2R_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	7071;"	d
+GET_RG_TX_BB_SCALE_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	7945;"	d
+GET_RG_TX_BT_PA_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	6500;"	d
+GET_RG_TX_CLK_OUTER_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8528;"	d
+GET_RG_TX_CNT_TARGET	include/ssv6200_reg.h	3910;"	d
+GET_RG_TX_CNT_TARGET	smac/hal/ssv6006c/ssv6006C_reg.h	8231;"	d
+GET_RG_TX_D	include/ssv6200_reg.h	3909;"	d
+GET_RG_TX_D	smac/hal/ssv6006c/ssv6006C_reg.h	8229;"	d
+GET_RG_TX_DACLPF_ICOURSE	include/ssv6200_reg.h	4632;"	d
+GET_RG_TX_DACLPF_IFINE	include/ssv6200_reg.h	4633;"	d
+GET_RG_TX_DACLPF_VCM	include/ssv6200_reg.h	4634;"	d
+GET_RG_TX_DAC_CAL_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	6507;"	d
+GET_RG_TX_DAC_CKEDGE_SEL	include/ssv6200_reg.h	4635;"	d
+GET_RG_TX_DAC_EN	include/ssv6200_reg.h	4477;"	d
+GET_RG_TX_DAC_IBIAS	include/ssv6200_reg.h	4636;"	d
+GET_RG_TX_DAC_IOFFSET	include/ssv6200_reg.h	4643;"	d
+GET_RG_TX_DAC_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	6494;"	d
+GET_RG_TX_DAC_OS	include/ssv6200_reg.h	4637;"	d
+GET_RG_TX_DAC_QOFFSET	include/ssv6200_reg.h	4644;"	d
+GET_RG_TX_DAC_RCAL	include/ssv6200_reg.h	4638;"	d
+GET_RG_TX_DAC_TSEL	include/ssv6200_reg.h	4639;"	d
+GET_RG_TX_DAC_TSEL	smac/hal/ssv6006c/ssv6006C_reg.h	6750;"	d
+GET_RG_TX_DCCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	7081;"	d
+GET_RG_TX_DES_ACK_PRD	include/ssv6200_reg.h	4012;"	d
+GET_RG_TX_DES_ACK_WIDTH	include/ssv6200_reg.h	4011;"	d
+GET_RG_TX_DES_EXCP_CLR	include/ssv6200_reg.h	4010;"	d
+GET_RG_TX_DES_EXCP_MODE_DEFAULT	include/ssv6200_reg.h	4009;"	d
+GET_RG_TX_DES_EXCP_RATE_DEFAULT	include/ssv6200_reg.h	4008;"	d
+GET_RG_TX_DES_LEN_LO	include/ssv6200_reg.h	3978;"	d
+GET_RG_TX_DES_LEN_UP	include/ssv6200_reg.h	3979;"	d
+GET_RG_TX_DES_L_LEN_LO	include/ssv6200_reg.h	3981;"	d
+GET_RG_TX_DES_L_LEN_UP	include/ssv6200_reg.h	3982;"	d
+GET_RG_TX_DES_L_LEN_UP_COMB	include/ssv6200_reg.h	3984;"	d
+GET_RG_TX_DES_MODE	include/ssv6200_reg.h	3977;"	d
+GET_RG_TX_DES_MODE_COMB	include/ssv6200_reg.h	3987;"	d
+GET_RG_TX_DES_PWRLVL	include/ssv6200_reg.h	3988;"	d
+GET_RG_TX_DES_RATE	include/ssv6200_reg.h	3976;"	d
+GET_RG_TX_DES_RATE_COMB	include/ssv6200_reg.h	3986;"	d
+GET_RG_TX_DES_SRVC_LO	include/ssv6200_reg.h	3989;"	d
+GET_RG_TX_DES_SRVC_UP	include/ssv6200_reg.h	3980;"	d
+GET_RG_TX_DES_TYPE	include/ssv6200_reg.h	3983;"	d
+GET_RG_TX_DES_TYPE_COMB	include/ssv6200_reg.h	3985;"	d
+GET_RG_TX_DIV2_BUF_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	6498;"	d
+GET_RG_TX_DIV2_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	6496;"	d
+GET_RG_TX_DIV_VSET	include/ssv6200_reg.h	4566;"	d
+GET_RG_TX_DPDGM_BIAS	include/ssv6200_reg.h	4571;"	d
+GET_RG_TX_DPDGM_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	6593;"	d
+GET_RG_TX_DPD_DIV	include/ssv6200_reg.h	4572;"	d
+GET_RG_TX_DPD_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	6594;"	d
+GET_RG_TX_DPD_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	6515;"	d
+GET_RG_TX_EN	include/ssv6200_reg.h	4475;"	d
+GET_RG_TX_EN_VOLTAGE_IN	include/ssv6200_reg.h	4640;"	d
+GET_RG_TX_EN_VOLTAGE_IN	smac/hal/ssv6006c/ssv6006C_reg.h	6521;"	d
+GET_RG_TX_FIFO_EMPTY_CNT_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8419;"	d
+GET_RG_TX_FREQ_OFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	7596;"	d
+GET_RG_TX_FREQ_OFFSET_DES	smac/hal/ssv6006c/ssv6006C_reg.h	8233;"	d
+GET_RG_TX_GAIN	include/ssv6200_reg.h	4611;"	d
+GET_RG_TX_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	6471;"	d
+GET_RG_TX_GAIN_DPDCAL	smac/hal/ssv6006c/ssv6006C_reg.h	7093;"	d
+GET_RG_TX_GAIN_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	6462;"	d
+GET_RG_TX_GAIN_OFFSET	include/ssv6200_reg.h	4613;"	d
+GET_RG_TX_GAIN_RXIQCAL	smac/hal/ssv6006c/ssv6006C_reg.h	7090;"	d
+GET_RG_TX_GAIN_TXCAL	smac/hal/ssv6006c/ssv6006C_reg.h	7087;"	d
+GET_RG_TX_IQCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	7082;"	d
+GET_RG_TX_IQCAL_TIME	smac/hal/ssv6006c/ssv6006C_reg.h	7595;"	d
+GET_RG_TX_IQ_2500_ALPHA	smac/hal/ssv6006c/ssv6006C_reg.h	7617;"	d
+GET_RG_TX_IQ_2500_THETA	smac/hal/ssv6006c/ssv6006C_reg.h	7618;"	d
+GET_RG_TX_IQ_5100_ALPHA	smac/hal/ssv6006c/ssv6006C_reg.h	7621;"	d
+GET_RG_TX_IQ_5100_THETA	smac/hal/ssv6006c/ssv6006C_reg.h	7622;"	d
+GET_RG_TX_IQ_5500_ALPHA	smac/hal/ssv6006c/ssv6006C_reg.h	7625;"	d
+GET_RG_TX_IQ_5500_THETA	smac/hal/ssv6006c/ssv6006C_reg.h	7626;"	d
+GET_RG_TX_IQ_5700_ALPHA	smac/hal/ssv6006c/ssv6006C_reg.h	7629;"	d
+GET_RG_TX_IQ_5700_THETA	smac/hal/ssv6006c/ssv6006C_reg.h	7630;"	d
+GET_RG_TX_IQ_5900_ALPHA	smac/hal/ssv6006c/ssv6006C_reg.h	7633;"	d
+GET_RG_TX_IQ_5900_THETA	smac/hal/ssv6006c/ssv6006C_reg.h	7634;"	d
+GET_RG_TX_IQ_ALPHA	include/ssv6200_reg.h	4358;"	d
+GET_RG_TX_IQ_ALPHA	smac/hal/ssv6006c/ssv6006C_reg.h	7591;"	d
+GET_RG_TX_IQ_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	7593;"	d
+GET_RG_TX_IQ_SRC	include/ssv6200_reg.h	4354;"	d
+GET_RG_TX_IQ_SRC	smac/hal/ssv6006c/ssv6006C_reg.h	7946;"	d
+GET_RG_TX_IQ_SWP	include/ssv6200_reg.h	4351;"	d
+GET_RG_TX_IQ_SWP	smac/hal/ssv6006c/ssv6006C_reg.h	7944;"	d
+GET_RG_TX_IQ_THETA	include/ssv6200_reg.h	4357;"	d
+GET_RG_TX_IQ_THETA	smac/hal/ssv6006c/ssv6006C_reg.h	7592;"	d
+GET_RG_TX_I_DC	include/ssv6200_reg.h	4355;"	d
+GET_RG_TX_I_DC	smac/hal/ssv6006c/ssv6006C_reg.h	7947;"	d
+GET_RG_TX_I_OFFSET	include/ssv6200_reg.h	4360;"	d
+GET_RG_TX_I_OFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	7949;"	d
+GET_RG_TX_I_SCALE	include/ssv6200_reg.h	4349;"	d
+GET_RG_TX_LDO_TX_LEVEL	include/ssv6200_reg.h	4527;"	d
+GET_RG_TX_LOBUF_VSET	include/ssv6200_reg.h	4567;"	d
+GET_RG_TX_MOD_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	6492;"	d
+GET_RG_TX_PA_EN	include/ssv6200_reg.h	4476;"	d
+GET_RG_TX_PA_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	6490;"	d
+GET_RG_TX_Q_DC	include/ssv6200_reg.h	4356;"	d
+GET_RG_TX_Q_DC	smac/hal/ssv6006c/ssv6006C_reg.h	7948;"	d
+GET_RG_TX_Q_OFFSET	include/ssv6200_reg.h	4361;"	d
+GET_RG_TX_Q_OFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	7950;"	d
+GET_RG_TX_Q_SCALE	include/ssv6200_reg.h	4350;"	d
+GET_RG_TX_SCALE	smac/hal/ssv6006c/ssv6006C_reg.h	7943;"	d
+GET_RG_TX_SCALE_11B	smac/hal/ssv6006c/ssv6006C_reg.h	8011;"	d
+GET_RG_TX_SCALE_11B_P0D5	smac/hal/ssv6006c/ssv6006C_reg.h	8012;"	d
+GET_RG_TX_SCALE_11G	smac/hal/ssv6006c/ssv6006C_reg.h	8013;"	d
+GET_RG_TX_SCALE_11G_P0D5	smac/hal/ssv6006c/ssv6006C_reg.h	8014;"	d
+GET_RG_TX_SELF_MIXER_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	6511;"	d
+GET_RG_TX_SGN_OUT	include/ssv6200_reg.h	4352;"	d
+GET_RG_TX_START	include/ssv6200_reg.h	3905;"	d
+GET_RG_TX_START	smac/hal/ssv6006c/ssv6006C_reg.h	8225;"	d
+GET_RG_TX_TIME_EXT	include/ssv6200_reg.h	4279;"	d
+GET_RG_TX_TRSW_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	6472;"	d
+GET_RG_TX_TSSI_BIAS	include/ssv6200_reg.h	4573;"	d
+GET_RG_TX_TSSI_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	6595;"	d
+GET_RG_TX_TSSI_DIV	include/ssv6200_reg.h	4574;"	d
+GET_RG_TX_TSSI_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	6596;"	d
+GET_RG_TX_TSSI_TEST	include/ssv6200_reg.h	4576;"	d
+GET_RG_TX_TSSI_TEST	smac/hal/ssv6006c/ssv6006C_reg.h	6597;"	d
+GET_RG_TX_TSSI_TESTMODE	include/ssv6200_reg.h	4575;"	d
+GET_RG_TX_TSSI_TESTMODE	smac/hal/ssv6006c/ssv6006C_reg.h	6598;"	d
+GET_RG_TX_UP8X_MAN_EN	smac/hal/ssv6006c/ssv6006C_reg.h	7600;"	d
+GET_RG_TX_VTOI_CURRENT	smac/hal/ssv6006c/ssv6006C_reg.h	6627;"	d
+GET_RG_TX_VTOI_FS	smac/hal/ssv6006c/ssv6006C_reg.h	6630;"	d
+GET_RG_TX_VTOI_GM	smac/hal/ssv6006c/ssv6006C_reg.h	6628;"	d
+GET_RG_TX_VTOI_OPTION	smac/hal/ssv6006c/ssv6006C_reg.h	6629;"	d
+GET_RG_ULG_PGA_SAT_PGA_GAIN	include/ssv6200_reg.h	3934;"	d
+GET_RG_ULG_PGA_SAT_PGA_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	8253;"	d
+GET_RG_UP8X	include/ssv6200_reg.h	3915;"	d
+GET_RG_VITERBI_AB_SWAP	include/ssv6200_reg.h	4231;"	d
+GET_RG_VITERBI_AB_SWAP	smac/hal/ssv6006c/ssv6006C_reg.h	8560;"	d
+GET_RG_VITERBI_TB_BITS	include/ssv6200_reg.h	4263;"	d
+GET_RG_VITERBI_TB_BITS	smac/hal/ssv6006c/ssv6006C_reg.h	8636;"	d
+GET_RG_VO5GB_AAC_IMAX	smac/hal/ssv6006c/ssv6006C_reg.h	7387;"	d
+GET_RG_VO5GB_AAC_IOST	smac/hal/ssv6006c/ssv6006C_reg.h	7386;"	d
+GET_RG_VOBF_CAPIMB	smac/hal/ssv6006c/ssv6006C_reg.h	6872;"	d
+GET_RG_VOBF_CAPIMB_POL	smac/hal/ssv6006c/ssv6006C_reg.h	6871;"	d
+GET_RG_VOBF_DIVBFSEL	smac/hal/ssv6006c/ssv6006C_reg.h	6868;"	d
+GET_RG_VOBF_RXMBSEL_BT	smac/hal/ssv6006c/ssv6006C_reg.h	6862;"	d
+GET_RG_VOBF_RXMBSEL_WF	smac/hal/ssv6006c/ssv6006C_reg.h	6866;"	d
+GET_RG_VOBF_RXOBSEL_BT	smac/hal/ssv6006c/ssv6006C_reg.h	6863;"	d
+GET_RG_VOBF_RXOBSEL_WF	smac/hal/ssv6006c/ssv6006C_reg.h	6867;"	d
+GET_RG_VOBF_TXMBSEL_BT	smac/hal/ssv6006c/ssv6006C_reg.h	6860;"	d
+GET_RG_VOBF_TXMBSEL_WF	smac/hal/ssv6006c/ssv6006C_reg.h	6864;"	d
+GET_RG_VOBF_TXOBSEL_BT	smac/hal/ssv6006c/ssv6006C_reg.h	6861;"	d
+GET_RG_VOBF_TXOBSEL_WF	smac/hal/ssv6006c/ssv6006C_reg.h	6865;"	d
+GET_RG_VO_AAC_EN	smac/hal/ssv6006c/ssv6006C_reg.h	6899;"	d
+GET_RG_VO_AAC_EN_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	6898;"	d
+GET_RG_VO_AAC_EVA	smac/hal/ssv6006c/ssv6006C_reg.h	6901;"	d
+GET_RG_VO_AAC_EVA_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	6900;"	d
+GET_RG_VO_AAC_EVA_TS	smac/hal/ssv6006c/ssv6006C_reg.h	6897;"	d
+GET_RG_VO_AAC_IMAX	smac/hal/ssv6006c/ssv6006C_reg.h	6895;"	d
+GET_RG_VO_AAC_INIT	smac/hal/ssv6006c/ssv6006C_reg.h	6896;"	d
+GET_RG_VO_AAC_IOST_BT	smac/hal/ssv6006c/ssv6006C_reg.h	6892;"	d
+GET_RG_VO_AAC_IOST_WF	smac/hal/ssv6006c/ssv6006C_reg.h	6894;"	d
+GET_RG_VO_AAC_TAR_BT	smac/hal/ssv6006c/ssv6006C_reg.h	6891;"	d
+GET_RG_VO_AAC_TAR_WF	smac/hal/ssv6006c/ssv6006C_reg.h	6893;"	d
+GET_RG_VO_AAC_TEST_EN	smac/hal/ssv6006c/ssv6006C_reg.h	6902;"	d
+GET_RG_VO_AAC_TEST_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	6903;"	d
+GET_RG_WAIT_T	include/ssv6200_reg.h	3933;"	d
+GET_RG_WAIT_T	smac/hal/ssv6006c/ssv6006C_reg.h	8252;"	d
+GET_RG_WAIT_T_FINAL	include/ssv6200_reg.h	3932;"	d
+GET_RG_WAIT_T_FINAL	smac/hal/ssv6006c/ssv6006C_reg.h	8251;"	d
+GET_RG_WAIT_T_RXAGC	include/ssv6200_reg.h	3929;"	d
+GET_RG_WAIT_T_RXAGC	smac/hal/ssv6006c/ssv6006C_reg.h	8248;"	d
+GET_RG_WF_BTPASW	smac/hal/ssv6006c/ssv6006C_reg.h	6615;"	d
+GET_RG_WF_IDACAI_TZ0_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	6946;"	d
+GET_RG_WF_IDACAI_TZ0_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	6944;"	d
+GET_RG_WF_IDACAI_TZ0_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	6926;"	d
+GET_RG_WF_IDACAI_TZ0_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	6924;"	d
+GET_RG_WF_IDACAI_TZ0_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	6922;"	d
+GET_RG_WF_IDACAI_TZ0_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	6920;"	d
+GET_RG_WF_IDACAI_TZ0_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	6918;"	d
+GET_RG_WF_IDACAI_TZ0_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	6916;"	d
+GET_RG_WF_IDACAI_TZ0_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	6942;"	d
+GET_RG_WF_IDACAI_TZ0_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	6940;"	d
+GET_RG_WF_IDACAI_TZ0_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	6938;"	d
+GET_RG_WF_IDACAI_TZ0_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	6936;"	d
+GET_RG_WF_IDACAI_TZ0_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	6934;"	d
+GET_RG_WF_IDACAI_TZ0_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	6932;"	d
+GET_RG_WF_IDACAI_TZ0_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	6930;"	d
+GET_RG_WF_IDACAI_TZ0_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	6928;"	d
+GET_RG_WF_IDACAI_TZ1_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	6978;"	d
+GET_RG_WF_IDACAI_TZ1_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	6976;"	d
+GET_RG_WF_IDACAI_TZ1_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	6958;"	d
+GET_RG_WF_IDACAI_TZ1_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	6956;"	d
+GET_RG_WF_IDACAI_TZ1_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	6954;"	d
+GET_RG_WF_IDACAI_TZ1_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	6952;"	d
+GET_RG_WF_IDACAI_TZ1_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	6950;"	d
+GET_RG_WF_IDACAI_TZ1_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	6948;"	d
+GET_RG_WF_IDACAI_TZ1_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	6974;"	d
+GET_RG_WF_IDACAI_TZ1_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	6972;"	d
+GET_RG_WF_IDACAI_TZ1_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	6970;"	d
+GET_RG_WF_IDACAI_TZ1_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	6968;"	d
+GET_RG_WF_IDACAI_TZ1_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	6966;"	d
+GET_RG_WF_IDACAI_TZ1_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	6964;"	d
+GET_RG_WF_IDACAI_TZ1_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	6962;"	d
+GET_RG_WF_IDACAI_TZ1_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	6960;"	d
+GET_RG_WF_IDACAQ_TZ0_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	6947;"	d
+GET_RG_WF_IDACAQ_TZ0_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	6945;"	d
+GET_RG_WF_IDACAQ_TZ0_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	6927;"	d
+GET_RG_WF_IDACAQ_TZ0_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	6925;"	d
+GET_RG_WF_IDACAQ_TZ0_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	6923;"	d
+GET_RG_WF_IDACAQ_TZ0_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	6921;"	d
+GET_RG_WF_IDACAQ_TZ0_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	6919;"	d
+GET_RG_WF_IDACAQ_TZ0_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	6917;"	d
+GET_RG_WF_IDACAQ_TZ0_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	6943;"	d
+GET_RG_WF_IDACAQ_TZ0_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	6941;"	d
+GET_RG_WF_IDACAQ_TZ0_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	6939;"	d
+GET_RG_WF_IDACAQ_TZ0_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	6937;"	d
+GET_RG_WF_IDACAQ_TZ0_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	6935;"	d
+GET_RG_WF_IDACAQ_TZ0_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	6933;"	d
+GET_RG_WF_IDACAQ_TZ0_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	6931;"	d
+GET_RG_WF_IDACAQ_TZ0_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	6929;"	d
+GET_RG_WF_IDACAQ_TZ1_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	6979;"	d
+GET_RG_WF_IDACAQ_TZ1_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	6977;"	d
+GET_RG_WF_IDACAQ_TZ1_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	6959;"	d
+GET_RG_WF_IDACAQ_TZ1_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	6957;"	d
+GET_RG_WF_IDACAQ_TZ1_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	6955;"	d
+GET_RG_WF_IDACAQ_TZ1_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	6953;"	d
+GET_RG_WF_IDACAQ_TZ1_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	6951;"	d
+GET_RG_WF_IDACAQ_TZ1_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	6949;"	d
+GET_RG_WF_IDACAQ_TZ1_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	6975;"	d
+GET_RG_WF_IDACAQ_TZ1_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	6973;"	d
+GET_RG_WF_IDACAQ_TZ1_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	6971;"	d
+GET_RG_WF_IDACAQ_TZ1_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	6969;"	d
+GET_RG_WF_IDACAQ_TZ1_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	6967;"	d
+GET_RG_WF_IDACAQ_TZ1_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	6965;"	d
+GET_RG_WF_IDACAQ_TZ1_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	6963;"	d
+GET_RG_WF_IDACAQ_TZ1_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	6961;"	d
+GET_RG_WF_N_RX_ABBCFIX	smac/hal/ssv6006c/ssv6006C_reg.h	6564;"	d
+GET_RG_WF_N_RX_ABBCTUNE	smac/hal/ssv6006c/ssv6006C_reg.h	6558;"	d
+GET_RG_WF_N_RX_ABBCTUNE_TUNE	smac/hal/ssv6006c/ssv6006C_reg.h	7613;"	d
+GET_RG_WF_N_RX_ABBCTUNE_TUNE_EN	smac/hal/ssv6006c/ssv6006C_reg.h	7614;"	d
+GET_RG_WF_N_RX_ABB_BT_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	6566;"	d
+GET_RG_WF_N_RX_ABB_IDIV3	smac/hal/ssv6006c/ssv6006C_reg.h	6567;"	d
+GET_RG_WF_N_RX_ABB_N_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	6565;"	d
+GET_RG_WF_N_RX_EN_IDACA_COARSE	smac/hal/ssv6006c/ssv6006C_reg.h	6568;"	d
+GET_RG_WF_N_RX_EN_LOOPA	smac/hal/ssv6006c/ssv6006C_reg.h	6569;"	d
+GET_RG_WF_N_RX_FILTERI1ST	smac/hal/ssv6006c/ssv6006C_reg.h	6561;"	d
+GET_RG_WF_N_RX_FILTERI2ND	smac/hal/ssv6006c/ssv6006C_reg.h	6562;"	d
+GET_RG_WF_N_RX_FILTERI3RD	smac/hal/ssv6006c/ssv6006C_reg.h	6563;"	d
+GET_RG_WF_N_RX_FILTERI_COARSE	smac/hal/ssv6006c/ssv6006C_reg.h	6560;"	d
+GET_RG_WF_N_RX_FILTERVCM	smac/hal/ssv6006c/ssv6006C_reg.h	6571;"	d
+GET_RG_WF_N_RX_OUTVCM	smac/hal/ssv6006c/ssv6006C_reg.h	6572;"	d
+GET_RG_WF_N_RX_TZ_CMZ_C	smac/hal/ssv6006c/ssv6006C_reg.h	6559;"	d
+GET_RG_WF_N_RX_TZ_CMZ_R	smac/hal/ssv6006c/ssv6006C_reg.h	6570;"	d
+GET_RG_WF_PABIAS_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	6611;"	d
+GET_RG_WF_PACELL_EN	smac/hal/ssv6006c/ssv6006C_reg.h	6610;"	d
+GET_RG_WF_RX_ABBCFIX	smac/hal/ssv6006c/ssv6006C_reg.h	6549;"	d
+GET_RG_WF_RX_ABBCTUNE	smac/hal/ssv6006c/ssv6006C_reg.h	6543;"	d
+GET_RG_WF_RX_ABBCTUNE_TUNE	smac/hal/ssv6006c/ssv6006C_reg.h	7611;"	d
+GET_RG_WF_RX_ABBCTUNE_TUNE_EN	smac/hal/ssv6006c/ssv6006C_reg.h	7612;"	d
+GET_RG_WF_RX_ABB_BT_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	6551;"	d
+GET_RG_WF_RX_ABB_IDIV3	smac/hal/ssv6006c/ssv6006C_reg.h	6552;"	d
+GET_RG_WF_RX_ABB_N_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	6550;"	d
+GET_RG_WF_RX_ADC_CLOAD	smac/hal/ssv6006c/ssv6006C_reg.h	6726;"	d
+GET_RG_WF_RX_ADC_ICMP	smac/hal/ssv6006c/ssv6006C_reg.h	6724;"	d
+GET_RG_WF_RX_ADC_PSW	smac/hal/ssv6006c/ssv6006C_reg.h	6727;"	d
+GET_RG_WF_RX_ADC_VCMI	smac/hal/ssv6006c/ssv6006C_reg.h	6725;"	d
+GET_RG_WF_RX_DCCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	7078;"	d
+GET_RG_WF_RX_EN_IDACA_COARSE	smac/hal/ssv6006c/ssv6006C_reg.h	6553;"	d
+GET_RG_WF_RX_EN_LOOPA	smac/hal/ssv6006c/ssv6006C_reg.h	6554;"	d
+GET_RG_WF_RX_FILTERI1ST	smac/hal/ssv6006c/ssv6006C_reg.h	6546;"	d
+GET_RG_WF_RX_FILTERI2ND	smac/hal/ssv6006c/ssv6006C_reg.h	6547;"	d
+GET_RG_WF_RX_FILTERI3RD	smac/hal/ssv6006c/ssv6006C_reg.h	6548;"	d
+GET_RG_WF_RX_FILTERI_COARSE	smac/hal/ssv6006c/ssv6006C_reg.h	6545;"	d
+GET_RG_WF_RX_FILTERVCM	smac/hal/ssv6006c/ssv6006C_reg.h	6556;"	d
+GET_RG_WF_RX_HG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	6638;"	d
+GET_RG_WF_RX_HG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	6633;"	d
+GET_RG_WF_RX_HG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	6634;"	d
+GET_RG_WF_RX_HG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	6635;"	d
+GET_RG_WF_RX_HG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	6631;"	d
+GET_RG_WF_RX_HG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	6639;"	d
+GET_RG_WF_RX_HG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	6640;"	d
+GET_RG_WF_RX_HG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	6636;"	d
+GET_RG_WF_RX_HG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	6632;"	d
+GET_RG_WF_RX_HG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	6637;"	d
+GET_RG_WF_RX_HG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	6641;"	d
+GET_RG_WF_RX_LG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	6660;"	d
+GET_RG_WF_RX_LG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	6655;"	d
+GET_RG_WF_RX_LG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	6656;"	d
+GET_RG_WF_RX_LG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	6657;"	d
+GET_RG_WF_RX_LG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	6653;"	d
+GET_RG_WF_RX_LG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	6661;"	d
+GET_RG_WF_RX_LG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	6662;"	d
+GET_RG_WF_RX_LG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	6658;"	d
+GET_RG_WF_RX_LG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	6654;"	d
+GET_RG_WF_RX_LG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	6659;"	d
+GET_RG_WF_RX_LG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	6663;"	d
+GET_RG_WF_RX_MG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	6649;"	d
+GET_RG_WF_RX_MG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	6644;"	d
+GET_RG_WF_RX_MG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	6645;"	d
+GET_RG_WF_RX_MG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	6646;"	d
+GET_RG_WF_RX_MG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	6642;"	d
+GET_RG_WF_RX_MG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	6650;"	d
+GET_RG_WF_RX_MG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	6651;"	d
+GET_RG_WF_RX_MG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	6647;"	d
+GET_RG_WF_RX_MG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	6643;"	d
+GET_RG_WF_RX_MG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	6648;"	d
+GET_RG_WF_RX_MG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	6652;"	d
+GET_RG_WF_RX_OUTVCM	smac/hal/ssv6006c/ssv6006C_reg.h	6557;"	d
+GET_RG_WF_RX_TZ_CMZ_C	smac/hal/ssv6006c/ssv6006C_reg.h	6544;"	d
+GET_RG_WF_RX_TZ_CMZ_R	smac/hal/ssv6006c/ssv6006C_reg.h	6555;"	d
+GET_RG_WF_RX_ULG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	6671;"	d
+GET_RG_WF_RX_ULG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	6666;"	d
+GET_RG_WF_RX_ULG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	6667;"	d
+GET_RG_WF_RX_ULG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	6668;"	d
+GET_RG_WF_RX_ULG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	6664;"	d
+GET_RG_WF_RX_ULG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	6672;"	d
+GET_RG_WF_RX_ULG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	6673;"	d
+GET_RG_WF_RX_ULG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	6669;"	d
+GET_RG_WF_RX_ULG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	6665;"	d
+GET_RG_WF_RX_ULG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	6670;"	d
+GET_RG_WF_RX_ULG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	6674;"	d
+GET_RG_WF_TXLPF_BOOSTI	smac/hal/ssv6006c/ssv6006C_reg.h	6744;"	d
+GET_RG_WF_TXMOD_GMCELL_FINE	smac/hal/ssv6006c/ssv6006C_reg.h	6605;"	d
+GET_RG_WF_TXPGA_CAPSW	smac/hal/ssv6006c/ssv6006C_reg.h	6602;"	d
+GET_RG_WF_TX_DACI1ST	smac/hal/ssv6006c/ssv6006C_reg.h	6738;"	d
+GET_RG_WF_TX_DACLPF_ICOARSE	smac/hal/ssv6006c/ssv6006C_reg.h	6739;"	d
+GET_RG_WF_TX_DACLPF_IFINE	smac/hal/ssv6006c/ssv6006C_reg.h	6740;"	d
+GET_RG_WF_TX_DACLPF_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	6741;"	d
+GET_RG_WF_TX_DAC_CKEDGE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	6746;"	d
+GET_RG_WF_TX_DAC_IATTN	smac/hal/ssv6006c/ssv6006C_reg.h	6743;"	d
+GET_RG_WF_TX_DAC_IBIAS	smac/hal/ssv6006c/ssv6006C_reg.h	6742;"	d
+GET_RG_WF_TX_DAC_IOFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	6748;"	d
+GET_RG_WF_TX_DAC_OS	smac/hal/ssv6006c/ssv6006C_reg.h	6747;"	d
+GET_RG_WF_TX_DAC_QOFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	6749;"	d
+GET_RG_WF_TX_DAC_RCAL	smac/hal/ssv6006c/ssv6006C_reg.h	6745;"	d
+GET_RG_WF_TX_DIV_VSET	smac/hal/ssv6006c/ssv6006C_reg.h	6603;"	d
+GET_RG_WF_TX_GAIN_OFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	6625;"	d
+GET_RG_WF_TX_LOBUF_VSET	smac/hal/ssv6006c/ssv6006C_reg.h	6604;"	d
+GET_RG_WF_TX_PA1_VCAS	smac/hal/ssv6006c/ssv6006C_reg.h	6612;"	d
+GET_RG_WF_TX_PA2_VCAS	smac/hal/ssv6006c/ssv6006C_reg.h	6613;"	d
+GET_RG_WF_TX_PA3_VCAS	smac/hal/ssv6006c/ssv6006C_reg.h	6614;"	d
+GET_RG_WR_ACI_GAIN_INI_SEL_11B	include/ssv6200_reg.h	3950;"	d
+GET_RG_WR_ACI_GAIN_OW_11B	include/ssv6200_reg.h	3953;"	d
+GET_RG_WR_ACI_GAIN_SEL_11B	include/ssv6200_reg.h	3951;"	d
+GET_RG_WR_RFGC_INIT_EN	include/ssv6200_reg.h	3945;"	d
+GET_RG_WR_RFGC_INIT_SET	include/ssv6200_reg.h	3944;"	d
+GET_RG_WR_TX_EN_CNT_RST_N	include/ssv6200_reg.h	4124;"	d
+GET_RG_XOSC_CBANK_XI	include/ssv6200_reg.h	4701;"	d
+GET_RG_XOSC_CBANK_XO	include/ssv6200_reg.h	4700;"	d
+GET_RG_XO_CBANKI	smac/hal/ssv6006c/ssv6006C_reg.h	8044;"	d
+GET_RG_XO_CBANKI_SLP	smac/hal/ssv6006c/ssv6006C_reg.h	8160;"	d
+GET_RG_XO_CBANKO	smac/hal/ssv6006c/ssv6006C_reg.h	8045;"	d
+GET_RG_XO_CBANKO_SLP	smac/hal/ssv6006c/ssv6006C_reg.h	8161;"	d
+GET_RG_XO_LDO_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	8039;"	d
+GET_RG_XO_TIMMER	smac/hal/ssv6006c/ssv6006C_reg.h	8059;"	d
+GET_RG_XSCOR16_RATIO	include/ssv6200_reg.h	4258;"	d
+GET_RG_XSCOR16_RATIO	smac/hal/ssv6006c/ssv6006C_reg.h	8623;"	d
+GET_RG_XSCOR16_SHORT_CNT_LMT	include/ssv6200_reg.h	4257;"	d
+GET_RG_XSCOR16_SHORT_CNT_LMT	smac/hal/ssv6006c/ssv6006C_reg.h	8622;"	d
+GET_RG_XSCOR32_RATIO	include/ssv6200_reg.h	4223;"	d
+GET_RG_XSCOR32_RATIO	smac/hal/ssv6006c/ssv6006C_reg.h	8552;"	d
+GET_RG_XSCOR64_CNT_LMT1	include/ssv6200_reg.h	4229;"	d
+GET_RG_XSCOR64_CNT_LMT1	smac/hal/ssv6006c/ssv6006C_reg.h	8558;"	d
+GET_RG_XSCOR64_CNT_LMT2	include/ssv6200_reg.h	4228;"	d
+GET_RG_XSCOR64_CNT_LMT2	smac/hal/ssv6006c/ssv6006C_reg.h	8557;"	d
+GET_RG_XSCOR64_RATIO_SB	smac/hal/ssv6006c/ssv6006C_reg.h	8631;"	d
+GET_RI	include/ssv6200_reg.h	2154;"	d
+GET_RI	smac/hal/ssv6006c/ssv6006C_reg.h	2865;"	d
+GET_RIP_A	smac/hal/ssv6006c/ssv6006C_reg.h	2887;"	d
+GET_RK_HI	include/ssv6200_aux.h	6689;"	d
+GET_RK_I_MSK	include/ssv6200_aux.h	6687;"	d
+GET_RK_MSK	include/ssv6200_aux.h	6686;"	d
+GET_RK_SFT	include/ssv6200_aux.h	6688;"	d
+GET_RK_SZ	include/ssv6200_aux.h	6690;"	d
+GET_RLS_ABT_ID	include/ssv6200_reg.h	4840;"	d
+GET_RLS_ABT_INT	include/ssv6200_reg.h	4841;"	d
+GET_RLS_BUSY	include/ssv6200_reg.h	3549;"	d
+GET_RLS_BUSY	smac/hal/ssv6006c/ssv6006C_reg.h	8742;"	d
+GET_RLS_COUNT	include/ssv6200_reg.h	3552;"	d
+GET_RLS_COUNT	smac/hal/ssv6006c/ssv6006C_reg.h	8745;"	d
+GET_RLS_COUNT_CLR	include/ssv6200_reg.h	3550;"	d
+GET_RLS_COUNT_CLR	smac/hal/ssv6006c/ssv6006C_reg.h	8743;"	d
+GET_RLS_ERR	include/ssv6200_reg.h	4846;"	d
+GET_RLS_ERR_CLR	smac/hal/ssv6006c/ssv6006C_reg.h	9049;"	d
+GET_RLS_ERR_ID	include/ssv6200_reg.h	4850;"	d
+GET_RLS_ERR_ID	smac/hal/ssv6006c/ssv6006C_reg.h	9053;"	d
+GET_RLS_ERR_STS	smac/hal/ssv6006c/ssv6006C_reg.h	9047;"	d
+GET_RL_STATE	include/ssv6200_reg.h	4848;"	d
+GET_RL_STATE	smac/hal/ssv6006c/ssv6006C_reg.h	9051;"	d
+GET_ROMCRC32_GOLDEN	smac/hal/ssv6006c/ssv6006C_reg.h	2642;"	d
+GET_ROMCRC32_RESULT	smac/hal/ssv6006c/ssv6006C_reg.h	2643;"	d
+GET_ROM_END_INDEX	smac/hal/ssv6006c/ssv6006C_reg.h	2641;"	d
+GET_ROM_READ_PROT	smac/hal/ssv6006c/ssv6006C_reg.h	2423;"	d
+GET_ROM_START_INDEX	smac/hal/ssv6006c/ssv6006C_reg.h	2640;"	d
+GET_ROP_A	smac/hal/ssv6006c/ssv6006C_reg.h	2886;"	d
+GET_RO_11B_CCA_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8507;"	d
+GET_RO_11B_CRC_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8502;"	d
+GET_RO_11B_CRC_CORRECT	smac/hal/ssv6006c/ssv6006C_reg.h	8512;"	d
+GET_RO_11B_FREQ_OS	smac/hal/ssv6006c/ssv6006C_reg.h	8499;"	d
+GET_RO_11B_LENGTH_FIELD	smac/hal/ssv6006c/ssv6006C_reg.h	8508;"	d
+GET_RO_11B_PACKET_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8506;"	d
+GET_RO_11B_PACKET_ERR	smac/hal/ssv6006c/ssv6006C_reg.h	8505;"	d
+GET_RO_11B_PACKET_ERR_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8504;"	d
+GET_RO_11B_RCPI	smac/hal/ssv6006c/ssv6006C_reg.h	8501;"	d
+GET_RO_11B_SERVICE_FIELD	smac/hal/ssv6006c/ssv6006C_reg.h	8511;"	d
+GET_RO_11B_SFD_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8503;"	d
+GET_RO_11B_SFD_FIELD	smac/hal/ssv6006c/ssv6006C_reg.h	8509;"	d
+GET_RO_11B_SIGNAL_FIELD	smac/hal/ssv6006c/ssv6006C_reg.h	8510;"	d
+GET_RO_11B_SNR	smac/hal/ssv6006c/ssv6006C_reg.h	8500;"	d
+GET_RO_11GN_CCA_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8677;"	d
+GET_RO_11GN_FREQ_OS_LTS	smac/hal/ssv6006c/ssv6006C_reg.h	8671;"	d
+GET_RO_11GN_HT_SIGNAL_FIELD_23_0	smac/hal/ssv6006c/ssv6006C_reg.h	8673;"	d
+GET_RO_11GN_HT_SIGNAL_FIELD_47_24	smac/hal/ssv6006c/ssv6006C_reg.h	8672;"	d
+GET_RO_11GN_L_SIGNAL_FIELD	smac/hal/ssv6006c/ssv6006C_reg.h	8678;"	d
+GET_RO_11GN_NOISE_PWR	smac/hal/ssv6006c/ssv6006C_reg.h	8668;"	d
+GET_RO_11GN_PACKET_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8676;"	d
+GET_RO_11GN_PACKET_ERR_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8674;"	d
+GET_RO_11GN_RCPI	smac/hal/ssv6006c/ssv6006C_reg.h	8669;"	d
+GET_RO_11GN_SERVICE_FIELD	smac/hal/ssv6006c/ssv6006C_reg.h	8675;"	d
+GET_RO_11GN_SIGNAL_PWR	smac/hal/ssv6006c/ssv6006C_reg.h	8670;"	d
+GET_RO_11GN_SNR	smac/hal/ssv6006c/ssv6006C_reg.h	8667;"	d
+GET_RO_2ND_ED_STATE	smac/hal/ssv6006c/ssv6006C_reg.h	8283;"	d
+GET_RO_5G_DCCAL_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	7649;"	d
+GET_RO_5G_RXIQ_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	7648;"	d
+GET_RO_5G_TXDC_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	7646;"	d
+GET_RO_5G_TXIQ_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	7647;"	d
+GET_RO_ABBPGA	smac/hal/ssv6006c/ssv6006C_reg.h	7696;"	d
+GET_RO_ACT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	3507;"	d
+GET_RO_AD_VBAT_OK	smac/hal/ssv6006c/ssv6006C_reg.h	8114;"	d
+GET_RO_AGC_START_80M	smac/hal/ssv6006c/ssv6006C_reg.h	8433;"	d
+GET_RO_AMPDU_PACKET_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8679;"	d
+GET_RO_AMPDU_PACKET_ERR_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8680;"	d
+GET_RO_AMP_O	include/ssv6200_reg.h	4391;"	d
+GET_RO_BIST_DONE_CCFO_0	smac/hal/ssv6006c/ssv6006C_reg.h	8602;"	d
+GET_RO_BIST_DONE_CCFO_1	smac/hal/ssv6006c/ssv6006C_reg.h	8600;"	d
+GET_RO_BIST_DONE_RX_FFT_0	smac/hal/ssv6006c/ssv6006C_reg.h	8426;"	d
+GET_RO_BIST_DONE_RX_FFT_1	smac/hal/ssv6006c/ssv6006C_reg.h	8424;"	d
+GET_RO_BIST_DONE_TX_FFT_0	smac/hal/ssv6006c/ssv6006C_reg.h	8524;"	d
+GET_RO_BIST_DONE_TX_FFT_1	smac/hal/ssv6006c/ssv6006C_reg.h	8522;"	d
+GET_RO_BIST_DONE_VTB_0	smac/hal/ssv6006c/ssv6006C_reg.h	8612;"	d
+GET_RO_BIST_DONE_VTB_1	smac/hal/ssv6006c/ssv6006C_reg.h	8610;"	d
+GET_RO_BIST_DONE_VTB_2	smac/hal/ssv6006c/ssv6006C_reg.h	8608;"	d
+GET_RO_BIST_DONE_VTB_3	smac/hal/ssv6006c/ssv6006C_reg.h	8606;"	d
+GET_RO_BIST_FAIL_CCFO_0	smac/hal/ssv6006c/ssv6006C_reg.h	8603;"	d
+GET_RO_BIST_FAIL_CCFO_1	smac/hal/ssv6006c/ssv6006C_reg.h	8601;"	d
+GET_RO_BIST_FAIL_RX_FFT_0	smac/hal/ssv6006c/ssv6006C_reg.h	8427;"	d
+GET_RO_BIST_FAIL_RX_FFT_1	smac/hal/ssv6006c/ssv6006C_reg.h	8425;"	d
+GET_RO_BIST_FAIL_TX_FFT_0	smac/hal/ssv6006c/ssv6006C_reg.h	8525;"	d
+GET_RO_BIST_FAIL_TX_FFT_1	smac/hal/ssv6006c/ssv6006C_reg.h	8523;"	d
+GET_RO_BIST_FAIL_VTB_0	smac/hal/ssv6006c/ssv6006C_reg.h	8613;"	d
+GET_RO_BIST_FAIL_VTB_1	smac/hal/ssv6006c/ssv6006C_reg.h	8611;"	d
+GET_RO_BIST_FAIL_VTB_2	smac/hal/ssv6006c/ssv6006C_reg.h	8609;"	d
+GET_RO_BIST_FAIL_VTB_3	smac/hal/ssv6006c/ssv6006C_reg.h	8607;"	d
+GET_RO_BT_DCCAL_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	7641;"	d
+GET_RO_CAND_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	3508;"	d
+GET_RO_CCA_PWR_MA_11B	include/ssv6200_reg.h	3963;"	d
+GET_RO_CCA_PWR_MA_11B	smac/hal/ssv6006c/ssv6006C_reg.h	8281;"	d
+GET_RO_CCA_PWR_MA_11GN	include/ssv6200_reg.h	3961;"	d
+GET_RO_CCA_PWR_MA_11GN_HT20	smac/hal/ssv6006c/ssv6006C_reg.h	8280;"	d
+GET_RO_CCA_PWR_MA_11GN_HT40	smac/hal/ssv6006c/ssv6006C_reg.h	8279;"	d
+GET_RO_CSTATE_AGC	smac/hal/ssv6006c/ssv6006C_reg.h	8432;"	d
+GET_RO_CSTATE_PKT	smac/hal/ssv6006c/ssv6006C_reg.h	8430;"	d
+GET_RO_CSTATE_RX	smac/hal/ssv6006c/ssv6006C_reg.h	8434;"	d
+GET_RO_CSTATE_TX	smac/hal/ssv6006c/ssv6006C_reg.h	8436;"	d
+GET_RO_DA_RX_AGC	smac/hal/ssv6006c/ssv6006C_reg.h	7698;"	d
+GET_RO_DC_CAL_I	smac/hal/ssv6006c/ssv6006C_reg.h	7704;"	d
+GET_RO_DC_CAL_Q	smac/hal/ssv6006c/ssv6006C_reg.h	7703;"	d
+GET_RO_DPD_GAIN	include/ssv6200_reg.h	4469;"	d
+GET_RO_EDCCA_PRIMARY_PRD	smac/hal/ssv6006c/ssv6006C_reg.h	8312;"	d
+GET_RO_EDCCA_SECONDARY_PRD	smac/hal/ssv6006c/ssv6006C_reg.h	8314;"	d
+GET_RO_ED_STATE	include/ssv6200_reg.h	3962;"	d
+GET_RO_ED_STATE	smac/hal/ssv6006c/ssv6006C_reg.h	8282;"	d
+GET_RO_FDB_CDELAY	smac/hal/ssv6006c/ssv6006C_reg.h	8090;"	d
+GET_RO_FDB_FDELAY	smac/hal/ssv6006c/ssv6006C_reg.h	8091;"	d
+GET_RO_FDB_PHASESWAP	smac/hal/ssv6006c/ssv6006C_reg.h	8092;"	d
+GET_RO_FFT_ENRG_RDY	include/ssv6200_reg.h	4387;"	d
+GET_RO_FREQ_OS_LTS	include/ssv6200_reg.h	4310;"	d
+GET_RO_FSM_MTXDMA	smac/hal/ssv6006c/ssv6006C_reg.h	3511;"	d
+GET_RO_FSM_MTXHALT	smac/hal/ssv6006c/ssv6006C_reg.h	3510;"	d
+GET_RO_FSM_MTXPHYTX	smac/hal/ssv6006c/ssv6006C_reg.h	3512;"	d
+GET_RO_FSM_MTXPTC	smac/hal/ssv6006c/ssv6006C_reg.h	3506;"	d
+GET_RO_GAIN_EST_RDY	include/ssv6200_reg.h	4390;"	d
+GET_RO_GAIN_TX	smac/hal/ssv6006c/ssv6006C_reg.h	7695;"	d
+GET_RO_GEMINIA_BT_DCCAL_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	4887;"	d
+GET_RO_GEMINIA_FDB_CDELAY	smac/hal/ssv6006c/ssv6006C_reg.h	4957;"	d
+GET_RO_GEMINIA_FDB_FDELAY	smac/hal/ssv6006c/ssv6006C_reg.h	4958;"	d
+GET_RO_GEMINIA_FDB_PHASESWAP	smac/hal/ssv6006c/ssv6006C_reg.h	4959;"	d
+GET_RO_GEMINIA_PMU_WAKE_TRIG_EVENT	smac/hal/ssv6006c/ssv6006C_reg.h	4949;"	d
+GET_RO_GEMINIA_RCCAL_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	4888;"	d
+GET_RO_GEMINIA_RTC_INT_ALARM	smac/hal/ssv6006c/ssv6006C_reg.h	4954;"	d
+GET_RO_GEMINIA_RTC_INT_SEC	smac/hal/ssv6006c/ssv6006C_reg.h	4953;"	d
+GET_RO_GEMINIA_RTC_OSC_CAL_RES_RDY	smac/hal/ssv6006c/ssv6006C_reg.h	4942;"	d
+GET_RO_GEMINIA_RTC_OSC_RES_SW	smac/hal/ssv6006c/ssv6006C_reg.h	4941;"	d
+GET_RO_GEMINIA_RTC_TICK_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	4950;"	d
+GET_RO_GEMINIA_RXIQ_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	4891;"	d
+GET_RO_GEMINIA_TXDC_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	4889;"	d
+GET_RO_GEMINIA_TXIQ_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	4890;"	d
+GET_RO_GEMINIA_WF_DCCAL_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	4886;"	d
+GET_RO_GP_DIV_RDY	include/ssv6200_reg.h	4389;"	d
+GET_RO_HS3W_SX_CHANNEL	smac/hal/ssv6006c/ssv6006C_reg.h	7693;"	d
+GET_RO_HS3W_SX_RFCH_MAP_EN	smac/hal/ssv6006c/ssv6006C_reg.h	7694;"	d
+GET_RO_HS3W_SX_RFCTRL_CH	smac/hal/ssv6006c/ssv6006C_reg.h	7699;"	d
+GET_RO_HS3W_SX_RFCTRL_F	smac/hal/ssv6006c/ssv6006C_reg.h	7700;"	d
+GET_RO_HT_MCS_40M	include/ssv6200_reg.h	4319;"	d
+GET_RO_IFSAIR1	smac/hal/ssv6006c/ssv6006C_reg.h	3581;"	d
+GET_RO_IFSAIR2	smac/hal/ssv6006c/ssv6006C_reg.h	3582;"	d
+GET_RO_IFSST0	smac/hal/ssv6006c/ssv6006C_reg.h	3628;"	d
+GET_RO_IFSST1	smac/hal/ssv6006c/ssv6006C_reg.h	3629;"	d
+GET_RO_IFSST2	smac/hal/ssv6006c/ssv6006C_reg.h	3630;"	d
+GET_RO_IFSST3	smac/hal/ssv6006c/ssv6006C_reg.h	3631;"	d
+GET_RO_INTRP_RX_BEACON_LOSS	smac/hal/ssv6006c/ssv6006C_reg.h	8415;"	d
+GET_RO_INTRP_RX_LOSS	smac/hal/ssv6006c/ssv6006C_reg.h	8413;"	d
+GET_RO_INTRUP_RX_11B	smac/hal/ssv6006c/ssv6006C_reg.h	8498;"	d
+GET_RO_INTRUP_RX_11GN	smac/hal/ssv6006c/ssv6006C_reg.h	8664;"	d
+GET_RO_IQCAL_ALPHA_ESTM_RDY	include/ssv6200_reg.h	4384;"	d
+GET_RO_IQCAL_DC_RDY	include/ssv6200_reg.h	4385;"	d
+GET_RO_IQCAL_IQCOL_RDY	include/ssv6200_reg.h	4383;"	d
+GET_RO_IQCAL_MULT_RDY	include/ssv6200_reg.h	4386;"	d
+GET_RO_IQCAL_O	include/ssv6200_reg.h	4381;"	d
+GET_RO_IQCAL_SPRM_RDY	include/ssv6200_reg.h	4382;"	d
+GET_RO_I_DC_OUT	smac/hal/ssv6006c/ssv6006C_reg.h	8304;"	d
+GET_RO_L_RATE_40M	include/ssv6200_reg.h	4320;"	d
+GET_RO_MAC_PHY_TRX_EN_SYNC	smac/hal/ssv6006c/ssv6006C_reg.h	8437;"	d
+GET_RO_MAC_TX_FIFO_WEMPTY	smac/hal/ssv6006c/ssv6006C_reg.h	3621;"	d
+GET_RO_MAC_TX_FIFO_WFULL_MX	smac/hal/ssv6006c/ssv6006C_reg.h	3620;"	d
+GET_RO_MAC_TX_FIFO_WINC	smac/hal/ssv6006c/ssv6006C_reg.h	3619;"	d
+GET_RO_MODE_REG_OUT_16	include/ssv6200_reg.h	4061;"	d
+GET_RO_MODE_REG_OUT_64	include/ssv6200_reg.h	4302;"	d
+GET_RO_MODE_REG_OUT_80	include/ssv6200_reg.h	4299;"	d
+GET_RO_MODE_REG_SO_16	include/ssv6200_reg.h	4062;"	d
+GET_RO_MODE_REG_SO_64	include/ssv6200_reg.h	4303;"	d
+GET_RO_MODE_REG_SO_80	include/ssv6200_reg.h	4300;"	d
+GET_RO_MONITOR_BUS_16	include/ssv6200_reg.h	4063;"	d
+GET_RO_MONITOR_BUS_64	include/ssv6200_reg.h	4304;"	d
+GET_RO_MONITOR_BUS_80	include/ssv6200_reg.h	4301;"	d
+GET_RO_MRX_EN_CNT	include/ssv6200_reg.h	4026;"	d
+GET_RO_MRX_EN_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8308;"	d
+GET_RO_MRX_LEN_CNT_0	include/ssv6200_reg.h	4053;"	d
+GET_RO_MRX_LEN_CNT_0	smac/hal/ssv6006c/ssv6006C_reg.h	8335;"	d
+GET_RO_MRX_LEN_CNT_1	include/ssv6200_reg.h	4052;"	d
+GET_RO_MRX_LEN_CNT_1	smac/hal/ssv6006c/ssv6006C_reg.h	8334;"	d
+GET_RO_MRX_RX_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8431;"	d
+GET_RO_MRX_TYPE_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8340;"	d
+GET_RO_MRX_TYPE_CNT_0	include/ssv6200_reg.h	4071;"	d
+GET_RO_MRX_TYPE_CNT_1	include/ssv6200_reg.h	4070;"	d
+GET_RO_MTXDMA_CMD	smac/hal/ssv6006c/ssv6006C_reg.h	3513;"	d
+GET_RO_MTX_BASE1	smac/hal/ssv6006c/ssv6006C_reg.h	3633;"	d
+GET_RO_MTX_BASE2	smac/hal/ssv6006c/ssv6006C_reg.h	3634;"	d
+GET_RO_MTX_BASE3	smac/hal/ssv6006c/ssv6006C_reg.h	3635;"	d
+GET_RO_MTX_LEN_CNT_0	include/ssv6200_reg.h	4051;"	d
+GET_RO_MTX_LEN_CNT_0	smac/hal/ssv6006c/ssv6006C_reg.h	8333;"	d
+GET_RO_MTX_LEN_CNT_1	include/ssv6200_reg.h	4050;"	d
+GET_RO_MTX_LEN_CNT_1	smac/hal/ssv6006c/ssv6006C_reg.h	8332;"	d
+GET_RO_MTX_TX_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3618;"	d
+GET_RO_MTX_TYPE_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8341;"	d
+GET_RO_MTX_TYPE_CNT_0	include/ssv6200_reg.h	4069;"	d
+GET_RO_MTX_TYPE_CNT_1	include/ssv6200_reg.h	4068;"	d
+GET_RO_PACKET_ERR_CNT	include/ssv6200_reg.h	4206;"	d
+GET_RO_PERIOD_ARRAY_0	smac/hal/ssv6006c/ssv6006C_reg.h	8719;"	d
+GET_RO_PERIOD_ARRAY_1	smac/hal/ssv6006c/ssv6006C_reg.h	8720;"	d
+GET_RO_PERIOD_ARRAY_2	smac/hal/ssv6006c/ssv6006C_reg.h	8721;"	d
+GET_RO_PERIOD_ARRAY_3	smac/hal/ssv6006c/ssv6006C_reg.h	8722;"	d
+GET_RO_PERIOD_ARRAY_4	smac/hal/ssv6006c/ssv6006C_reg.h	8723;"	d
+GET_RO_PERIOD_ARRAY_5	smac/hal/ssv6006c/ssv6006C_reg.h	8724;"	d
+GET_RO_PGAGC_FF1	include/ssv6200_reg.h	3966;"	d
+GET_RO_PGAGC_FF1	smac/hal/ssv6006c/ssv6006C_reg.h	8286;"	d
+GET_RO_PGAGC_FF2	include/ssv6200_reg.h	3970;"	d
+GET_RO_PGAGC_FF2	smac/hal/ssv6006c/ssv6006C_reg.h	8290;"	d
+GET_RO_PGAGC_FF3	include/ssv6200_reg.h	3974;"	d
+GET_RO_PGAGC_FF3	smac/hal/ssv6006c/ssv6006C_reg.h	8294;"	d
+GET_RO_PGA_PWR_FF1	include/ssv6200_reg.h	3964;"	d
+GET_RO_PGA_PWR_FF1	smac/hal/ssv6006c/ssv6006C_reg.h	8284;"	d
+GET_RO_PGA_PWR_FF2	include/ssv6200_reg.h	3968;"	d
+GET_RO_PGA_PWR_FF2	smac/hal/ssv6006c/ssv6006C_reg.h	8288;"	d
+GET_RO_PGA_PWR_FF3	include/ssv6200_reg.h	3972;"	d
+GET_RO_PGA_PWR_FF3	smac/hal/ssv6006c/ssv6006C_reg.h	8292;"	d
+GET_RO_PHEST_RDY	include/ssv6200_reg.h	4388;"	d
+GET_RO_PHYTXIP_TIMEOUT_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	3578;"	d
+GET_RO_PMU_STATE	smac/hal/ssv6006c/ssv6006C_reg.h	8113;"	d
+GET_RO_PMU_WAKE_TRIG_EVENT	smac/hal/ssv6006c/ssv6006C_reg.h	8105;"	d
+GET_RO_PRE_DC_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	7650;"	d
+GET_RO_PRIMARY_EDCCA	smac/hal/ssv6006c/ssv6006C_reg.h	8313;"	d
+GET_RO_PTC_SCHEDULE	smac/hal/ssv6006c/ssv6006C_reg.h	3505;"	d
+GET_RO_PW	smac/hal/ssv6006c/ssv6006C_reg.h	8712;"	d
+GET_RO_PW_ARRAY_0	smac/hal/ssv6006c/ssv6006C_reg.h	8713;"	d
+GET_RO_PW_ARRAY_1	smac/hal/ssv6006c/ssv6006C_reg.h	8714;"	d
+GET_RO_PW_ARRAY_2	smac/hal/ssv6006c/ssv6006C_reg.h	8715;"	d
+GET_RO_PW_ARRAY_3	smac/hal/ssv6006c/ssv6006C_reg.h	8716;"	d
+GET_RO_PW_ARRAY_4	smac/hal/ssv6006c/ssv6006C_reg.h	8717;"	d
+GET_RO_PW_ARRAY_5	smac/hal/ssv6006c/ssv6006C_reg.h	8718;"	d
+GET_RO_Q_DC_OUT	smac/hal/ssv6006c/ssv6006C_reg.h	8303;"	d
+GET_RO_RADAR_DET_NUM	smac/hal/ssv6006c/ssv6006C_reg.h	8709;"	d
+GET_RO_RADAR_DET_OUT	smac/hal/ssv6006c/ssv6006C_reg.h	8710;"	d
+GET_RO_RADAR_VALID	smac/hal/ssv6006c/ssv6006C_reg.h	8711;"	d
+GET_RO_RCCAL_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	7642;"	d
+GET_RO_REFREG_KHZ_OUT	smac/hal/ssv6006c/ssv6006C_reg.h	7701;"	d
+GET_RO_RFGC_FF1	include/ssv6200_reg.h	3967;"	d
+GET_RO_RFGC_FF1	smac/hal/ssv6006c/ssv6006C_reg.h	8287;"	d
+GET_RO_RFGC_FF2	include/ssv6200_reg.h	3971;"	d
+GET_RO_RFGC_FF2	smac/hal/ssv6006c/ssv6006C_reg.h	8291;"	d
+GET_RO_RFGC_FF3	include/ssv6200_reg.h	3975;"	d
+GET_RO_RFGC_FF3	smac/hal/ssv6006c/ssv6006C_reg.h	8295;"	d
+GET_RO_RFPGA	smac/hal/ssv6006c/ssv6006C_reg.h	7697;"	d
+GET_RO_RF_CH_FREQ	smac/hal/ssv6006c/ssv6006C_reg.h	7702;"	d
+GET_RO_RF_PHY_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	7692;"	d
+GET_RO_RF_PWR_FF1	include/ssv6200_reg.h	3965;"	d
+GET_RO_RF_PWR_FF1	smac/hal/ssv6006c/ssv6006C_reg.h	8285;"	d
+GET_RO_RF_PWR_FF2	include/ssv6200_reg.h	3969;"	d
+GET_RO_RF_PWR_FF2	smac/hal/ssv6006c/ssv6006C_reg.h	8289;"	d
+GET_RO_RF_PWR_FF3	include/ssv6200_reg.h	3973;"	d
+GET_RO_RF_PWR_FF3	smac/hal/ssv6006c/ssv6006C_reg.h	8293;"	d
+GET_RO_RTC_INT_ALARM	smac/hal/ssv6006c/ssv6006C_reg.h	8107;"	d
+GET_RO_RTC_INT_SEC	smac/hal/ssv6006c/ssv6006C_reg.h	8106;"	d
+GET_RO_RTC_OSC_CAL_RES_RDY	smac/hal/ssv6006c/ssv6006C_reg.h	8094;"	d
+GET_RO_RTC_OSC_RES_SW	smac/hal/ssv6006c/ssv6006C_reg.h	8095;"	d
+GET_RO_RTC_TICK_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8102;"	d
+GET_RO_RXIQ_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	7645;"	d
+GET_RO_RX_AMP	smac/hal/ssv6006c/ssv6006C_reg.h	7935;"	d
+GET_RO_RX_BEACON_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8417;"	d
+GET_RO_RX_BEACON_LOSS_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8416;"	d
+GET_RO_RX_FIFO_FULL_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8420;"	d
+GET_RO_RX_IQ_ALPHA	smac/hal/ssv6006c/ssv6006C_reg.h	7657;"	d
+GET_RO_RX_IQ_THETA	smac/hal/ssv6006c/ssv6006C_reg.h	7656;"	d
+GET_RO_RX_PHI	smac/hal/ssv6006c/ssv6006C_reg.h	7934;"	d
+GET_RO_RX_PKT_TIMER	smac/hal/ssv6006c/ssv6006C_reg.h	8414;"	d
+GET_RO_SECONDARY_EDCCA	smac/hal/ssv6006c/ssv6006C_reg.h	8315;"	d
+GET_RO_SPECTRUM_DATA	include/ssv6200_reg.h	4305;"	d
+GET_RO_SPECTRUM_IQ_PWR_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	7668;"	d
+GET_RO_SPECTRUM_IQ_PWR_39_32	smac/hal/ssv6006c/ssv6006C_reg.h	7665;"	d
+GET_RO_STBC_PACKET_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8665;"	d
+GET_RO_STBC_PACKET_ERR_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8666;"	d
+GET_RO_TBUS_O	include/ssv6200_reg.h	4077;"	d
+GET_RO_TURISMO_TRX_5G_DCCAL_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	6236;"	d
+GET_RO_TURISMO_TRX_5G_RXIQ_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	6235;"	d
+GET_RO_TURISMO_TRX_5G_TXDC_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	6233;"	d
+GET_RO_TURISMO_TRX_5G_TXIQ_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	6234;"	d
+GET_RO_TURISMO_TRX_AD_VBAT_OK	smac/hal/ssv6006c/ssv6006C_reg.h	6349;"	d
+GET_RO_TURISMO_TRX_BT_DCCAL_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	6228;"	d
+GET_RO_TURISMO_TRX_DC_CAL_I	smac/hal/ssv6006c/ssv6006C_reg.h	6276;"	d
+GET_RO_TURISMO_TRX_DC_CAL_Q	smac/hal/ssv6006c/ssv6006C_reg.h	6275;"	d
+GET_RO_TURISMO_TRX_FDB_CDELAY	smac/hal/ssv6006c/ssv6006C_reg.h	6325;"	d
+GET_RO_TURISMO_TRX_FDB_FDELAY	smac/hal/ssv6006c/ssv6006C_reg.h	6326;"	d
+GET_RO_TURISMO_TRX_FDB_PHASESWAP	smac/hal/ssv6006c/ssv6006C_reg.h	6327;"	d
+GET_RO_TURISMO_TRX_PMU_STATE	smac/hal/ssv6006c/ssv6006C_reg.h	6348;"	d
+GET_RO_TURISMO_TRX_PMU_WAKE_TRIG_EVENT	smac/hal/ssv6006c/ssv6006C_reg.h	6340;"	d
+GET_RO_TURISMO_TRX_PRE_DC_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	6237;"	d
+GET_RO_TURISMO_TRX_RCCAL_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	6229;"	d
+GET_RO_TURISMO_TRX_RTC_INT_ALARM	smac/hal/ssv6006c/ssv6006C_reg.h	6342;"	d
+GET_RO_TURISMO_TRX_RTC_INT_SEC	smac/hal/ssv6006c/ssv6006C_reg.h	6341;"	d
+GET_RO_TURISMO_TRX_RTC_OSC_CAL_RES_RDY	smac/hal/ssv6006c/ssv6006C_reg.h	6329;"	d
+GET_RO_TURISMO_TRX_RTC_OSC_RES_SW	smac/hal/ssv6006c/ssv6006C_reg.h	6330;"	d
+GET_RO_TURISMO_TRX_RTC_TICK_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	6337;"	d
+GET_RO_TURISMO_TRX_RXIQ_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	6232;"	d
+GET_RO_TURISMO_TRX_RX_IQ_ALPHA	smac/hal/ssv6006c/ssv6006C_reg.h	6245;"	d
+GET_RO_TURISMO_TRX_RX_IQ_THETA	smac/hal/ssv6006c/ssv6006C_reg.h	6244;"	d
+GET_RO_TURISMO_TRX_SPECTRUM_IQ_PWR_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	6256;"	d
+GET_RO_TURISMO_TRX_SPECTRUM_IQ_PWR_39_32	smac/hal/ssv6006c/ssv6006C_reg.h	6253;"	d
+GET_RO_TURISMO_TRX_TXDC_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	6230;"	d
+GET_RO_TURISMO_TRX_TXIQ_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	6231;"	d
+GET_RO_TURISMO_TRX_TX_IQ_ALPHA	smac/hal/ssv6006c/ssv6006C_reg.h	6247;"	d
+GET_RO_TURISMO_TRX_TX_IQ_THETA	smac/hal/ssv6006c/ssv6006C_reg.h	6246;"	d
+GET_RO_TURISMO_TRX_WF_DCCAL_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	6227;"	d
+GET_RO_TURISMO_TRX_XO_RDY	smac/hal/ssv6006c/ssv6006C_reg.h	6328;"	d
+GET_RO_TXDC_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	7643;"	d
+GET_RO_TXIQ_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	7644;"	d
+GET_RO_TXOP_INTERVAL	smac/hal/ssv6006c/ssv6006C_reg.h	3514;"	d
+GET_RO_TX_CNT	include/ssv6200_reg.h	4126;"	d
+GET_RO_TX_CNT_R	include/ssv6200_reg.h	4205;"	d
+GET_RO_TX_CNT_R_11B_TX	smac/hal/ssv6006c/ssv6006C_reg.h	8442;"	d
+GET_RO_TX_CNT_R_11GN_TX	smac/hal/ssv6006c/ssv6006C_reg.h	8538;"	d
+GET_RO_TX_DES_EXCP_CH_BW_CNT	include/ssv6200_reg.h	4006;"	d
+GET_RO_TX_DES_EXCP_MODE_CNT	include/ssv6200_reg.h	4007;"	d
+GET_RO_TX_DES_EXCP_RATE_CNT	include/ssv6200_reg.h	4005;"	d
+GET_RO_TX_EN_CNT	include/ssv6200_reg.h	4125;"	d
+GET_RO_TX_FIFO_EMPTY_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	8421;"	d
+GET_RO_TX_IP	smac/hal/ssv6006c/ssv6006C_reg.h	8435;"	d
+GET_RO_TX_IQ_ALPHA	smac/hal/ssv6006c/ssv6006C_reg.h	7659;"	d
+GET_RO_TX_IQ_THETA	smac/hal/ssv6006c/ssv6006C_reg.h	7658;"	d
+GET_RO_WAIT_RESPONSE_PHASE	smac/hal/ssv6006c/ssv6006C_reg.h	3509;"	d
+GET_RO_WF_DCCAL_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	7640;"	d
+GET_RO_XO_RDY	smac/hal/ssv6006c/ssv6006C_reg.h	8093;"	d
+GET_RTC_CAL_ENA	include/ssv6200_reg.h	2443;"	d
+GET_RTC_CAL_RDY	include/ssv6200_reg.h	4779;"	d
+GET_RTC_EN	include/ssv6200_reg.h	2448;"	d
+GET_RTC_INT_ALARM	include/ssv6200_reg.h	2454;"	d
+GET_RTC_INT_ALARM_MASK	include/ssv6200_reg.h	2452;"	d
+GET_RTC_INT_SEC	include/ssv6200_reg.h	2453;"	d
+GET_RTC_INT_SEC_MASK	include/ssv6200_reg.h	2451;"	d
+GET_RTC_OSC_CAL_RES_RDY	include/ssv6200_reg.h	2437;"	d
+GET_RTC_SEC_ALARM_VALUE	include/ssv6200_reg.h	2457;"	d
+GET_RTC_SEC_CNT	include/ssv6200_reg.h	2456;"	d
+GET_RTC_SEC_START_CNT	include/ssv6200_reg.h	2455;"	d
+GET_RTC_SRC	include/ssv6200_reg.h	2449;"	d
+GET_RTC_TICK_CNT	include/ssv6200_reg.h	2450;"	d
+GET_RTC_TIMER_WAKE_PMU_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2507;"	d
+GET_RTHR_H	include/ssv6200_reg.h	2158;"	d
+GET_RTHR_H	smac/hal/ssv6006c/ssv6006C_reg.h	2869;"	d
+GET_RTHR_L	include/ssv6200_reg.h	2157;"	d
+GET_RTHR_L	smac/hal/ssv6006c/ssv6006C_reg.h	2868;"	d
+GET_RTN_COUNT	include/ssv6200_reg.h	3553;"	d
+GET_RTN_COUNT	smac/hal/ssv6006c/ssv6006C_reg.h	8746;"	d
+GET_RTN_COUNT_CLR	include/ssv6200_reg.h	3551;"	d
+GET_RTN_COUNT_CLR	smac/hal/ssv6006c/ssv6006C_reg.h	8744;"	d
+GET_RTS	include/ssv6200_reg.h	2136;"	d
+GET_RTS	smac/hal/ssv6006c/ssv6006C_reg.h	2846;"	d
+GET_RW_BUF_CLR	smac/hal/ssv6006c/ssv6006C_reg.h	2987;"	d
+GET_RXFIFO_RST	include/ssv6200_reg.h	2122;"	d
+GET_RXFIFO_RST	smac/hal/ssv6006c/ssv6006C_reg.h	2832;"	d
+GET_RXFIFO_TRGLVL	include/ssv6200_reg.h	2127;"	d
+GET_RXFIFO_TRGLVL	smac/hal/ssv6006c/ssv6006C_reg.h	2837;"	d
+GET_RXFULLFLAG	smac/hal/ssv6006c/ssv6006C_reg.h	2332;"	d
+GET_RXID_ALC_CNT_FAIL	include/ssv6200_reg.h	3205;"	d
+GET_RXID_ALC_CNT_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	4053;"	d
+GET_RXID_ALC_LEN_FAIL	include/ssv6200_reg.h	3206;"	d
+GET_RXID_ALC_LEN_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	4054;"	d
+GET_RXNOTEMPTYFLAG	smac/hal/ssv6006c/ssv6006C_reg.h	2331;"	d
+GET_RXTRAP_ETHTYPE0	include/ssv6200_reg.h	2504;"	d
+GET_RXTRAP_ETHTYPE0	smac/hal/ssv6006c/ssv6006C_reg.h	3220;"	d
+GET_RXTRAP_ETHTYPE1	include/ssv6200_reg.h	2503;"	d
+GET_RXTRAP_ETHTYPE1	smac/hal/ssv6006c/ssv6006C_reg.h	3219;"	d
+GET_RX_2_HOST	include/ssv6200_reg.h	2474;"	d
+GET_RX_2_HOST	smac/hal/ssv6006c/ssv6006C_reg.h	3173;"	d
+GET_RX_ACCU_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	3193;"	d
+GET_RX_AGG_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	3264;"	d
+GET_RX_AGG_METHOD_3	smac/hal/ssv6006c/ssv6006C_reg.h	3265;"	d
+GET_RX_AGG_TIMER_RELOAD_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	3266;"	d
+GET_RX_CS_DUR	include/ssv6200_reg.h	2818;"	d
+GET_RX_DEBUG_HCI_EXP_0	smac/hal/ssv6006c/ssv6006C_reg.h	3260;"	d
+GET_RX_DEBUG_HCI_EXP_0_LENGHT_LIMIT_MAX	smac/hal/ssv6006c/ssv6006C_reg.h	3263;"	d
+GET_RX_DEBUG_HCI_EXP_0_LENGHT_LIMIT_MIN	smac/hal/ssv6006c/ssv6006C_reg.h	3262;"	d
+GET_RX_DEBUG_HCI_EXP_0_RND_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	3261;"	d
+GET_RX_EN_DUR	include/ssv6200_reg.h	2817;"	d
+GET_RX_ETHER_TRAP_EN	include/ssv6200_reg.h	2483;"	d
+GET_RX_ETHER_TRAP_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3182;"	d
+GET_RX_FIFO_FAIL	include/ssv6200_reg.h	2057;"	d
+GET_RX_FIFO_RESIDUE	include/ssv6200_reg.h	2084;"	d
+GET_RX_FIFO_TO	smac/hal/ssv6006c/ssv6006C_reg.h	2877;"	d
+GET_RX_FLOW_CTRL	include/ssv6200_reg.h	2685;"	d
+GET_RX_FLOW_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	3409;"	d
+GET_RX_FLOW_DATA	include/ssv6200_reg.h	2683;"	d
+GET_RX_FLOW_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	3407;"	d
+GET_RX_FLOW_MNG	include/ssv6200_reg.h	2684;"	d
+GET_RX_FLOW_MNG	smac/hal/ssv6006c/ssv6006C_reg.h	3408;"	d
+GET_RX_GET_TX_QUEUE_EN	include/ssv6200_reg.h	2485;"	d
+GET_RX_HOST_FAIL	include/ssv6200_reg.h	2058;"	d
+GET_RX_IDLE	smac/hal/ssv6006c/ssv6006C_reg.h	2871;"	d
+GET_RX_ID_ALC_LEN	include/ssv6200_reg.h	3814;"	d
+GET_RX_ID_ALC_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	8997;"	d
+GET_RX_ID_COUNT	include/ssv6200_reg.h	3790;"	d
+GET_RX_ID_COUNT	smac/hal/ssv6006c/ssv6006C_reg.h	8973;"	d
+GET_RX_ID_IFO_LEN	include/ssv6200_reg.h	3851;"	d
+GET_RX_ID_IFO_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	9036;"	d
+GET_RX_ID_LEN_THOLD	include/ssv6200_reg.h	2266;"	d
+GET_RX_ID_LEN_THOLD_INT	include/ssv6200_reg.h	3808;"	d
+GET_RX_ID_LEN_THOLD_INT	smac/hal/ssv6006c/ssv6006C_reg.h	8991;"	d
+GET_RX_ID_LEN_THOLD_SD	include/ssv6200_reg.h	2335;"	d
+GET_RX_ID_TB0	include/ssv6200_reg.h	3800;"	d
+GET_RX_ID_TB0	smac/hal/ssv6006c/ssv6006C_reg.h	8983;"	d
+GET_RX_ID_TB1	include/ssv6200_reg.h	3801;"	d
+GET_RX_ID_TB1	smac/hal/ssv6006c/ssv6006C_reg.h	8984;"	d
+GET_RX_ID_TB2	include/ssv6200_reg.h	3837;"	d
+GET_RX_ID_TB2	smac/hal/ssv6006c/ssv6006C_reg.h	9020;"	d
+GET_RX_ID_TB3	include/ssv6200_reg.h	3838;"	d
+GET_RX_ID_TB3	smac/hal/ssv6006c/ssv6006C_reg.h	9021;"	d
+GET_RX_ID_THOLD	include/ssv6200_reg.h	3792;"	d
+GET_RX_ID_THOLD	smac/hal/ssv6006c/ssv6006C_reg.h	8975;"	d
+GET_RX_INFO_SIZE	include/ssv6200_reg.h	2497;"	d
+GET_RX_INFO_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	3205;"	d
+GET_RX_INT	include/ssv6200_reg.h	1878;"	d
+GET_RX_INT	smac/hal/ssv6006c/ssv6006C_reg.h	2661;"	d
+GET_RX_INT1	include/ssv6200_reg.h	1906;"	d
+GET_RX_INT3	include/ssv6200_reg.h	1989;"	d
+GET_RX_INT_CH	include/ssv6200_reg.h	3794;"	d
+GET_RX_INT_CH	smac/hal/ssv6006c/ssv6006C_reg.h	8977;"	d
+GET_RX_INT_TIMEOUT	smac/hal/ssv6006c/ssv6006C_reg.h	3198;"	d
+GET_RX_LAST_PHY_SIZE	include/ssv6200_reg.h	2498;"	d
+GET_RX_LAST_PHY_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	3206;"	d
+GET_RX_LEN	include/ssv6200_reg.h	2066;"	d
+GET_RX_LINESTS_IE	include/ssv6200_reg.h	2117;"	d
+GET_RX_LINESTS_IE	smac/hal/ssv6006c/ssv6006C_reg.h	2827;"	d
+GET_RX_MOUNT	include/ssv6200_reg.h	4858;"	d
+GET_RX_NULL_TRAP_EN	include/ssv6200_reg.h	2484;"	d
+GET_RX_NULL_TRAP_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3183;"	d
+GET_RX_PACKET_LENGTH	include/ssv6200_reg.h	1897;"	d
+GET_RX_PACKET_LENGTH2	include/ssv6200_reg.h	1905;"	d
+GET_RX_PACKET_LENGTH3	include/ssv6200_reg.h	1988;"	d
+GET_RX_PER_RD_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	3209;"	d
+GET_RX_PHY_11B_SOFT_RST_N	include/ssv6200_reg.h	4195;"	d
+GET_RX_PHY_11GN_SOFT_RST_N	include/ssv6200_reg.h	4323;"	d
+GET_RX_PKT_COUNTER	include/ssv6200_reg.h	2506;"	d
+GET_RX_PKT_COUNTER	smac/hal/ssv6006c/ssv6006C_reg.h	3249;"	d
+GET_RX_PKT_DROP_COUNTER	include/ssv6200_reg.h	2510;"	d
+GET_RX_PKT_DROP_COUNTER	smac/hal/ssv6006c/ssv6006C_reg.h	3245;"	d
+GET_RX_PKT_TRAP_COUNTER	include/ssv6200_reg.h	2512;"	d
+GET_RX_PKT_TRAP_COUNTER	smac/hal/ssv6006c/ssv6006C_reg.h	3243;"	d
+GET_RX_QUOTA	include/ssv6200_reg.h	2048;"	d
+GET_RX_RDY	include/ssv6200_reg.h	2085;"	d
+GET_RX_RECIEVED	smac/hal/ssv6006c/ssv6006C_reg.h	2876;"	d
+GET_RX_TRAP_HW_ID	smac/hal/ssv6006c/ssv6006C_reg.h	3259;"	d
+GET_R_BOOTSTRAP_SAMPLE	smac/hal/ssv6006c/ssv6006C_reg.h	2415;"	d
+GET_SAME_ID_ALLOC_MD	include/ssv6200_reg.h	4797;"	d
+GET_SAR_ADC_FSM_RDY	include/ssv6200_reg.h	4781;"	d
+GET_SAR_ADC_FSM_RDY	smac/hal/ssv6006c/ssv6006C_reg.h	7108;"	d
+GET_SBUS_DMAC_BLOCK0	smac/hal/ssv6006c/ssv6006C_reg.h	2215;"	d
+GET_SBUS_DMAC_BLOCK1	smac/hal/ssv6006c/ssv6006C_reg.h	2232;"	d
+GET_SBUS_DMAC_CH0_CLR_ERR	smac/hal/ssv6006c/ssv6006C_reg.h	2247;"	d
+GET_SBUS_DMAC_CH0_CLR_TR	smac/hal/ssv6006c/ssv6006C_reg.h	2245;"	d
+GET_SBUS_DMAC_CH0_PRIOR	smac/hal/ssv6006c/ssv6006C_reg.h	2216;"	d
+GET_SBUS_DMAC_CH1_CLR_ERR	smac/hal/ssv6006c/ssv6006C_reg.h	2248;"	d
+GET_SBUS_DMAC_CH1_CLR_TR	smac/hal/ssv6006c/ssv6006C_reg.h	2246;"	d
+GET_SBUS_DMAC_CH1_PRIOR	smac/hal/ssv6006c/ssv6006C_reg.h	2233;"	d
+GET_SBUS_DMAC_CH_DEMASK_ERR	smac/hal/ssv6006c/ssv6006C_reg.h	2244;"	d
+GET_SBUS_DMAC_CH_DEMASK_TR	smac/hal/ssv6006c/ssv6006C_reg.h	2243;"	d
+GET_SBUS_DMAC_CH_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2254;"	d
+GET_SBUS_DMAC_CH_ERR_TR	smac/hal/ssv6006c/ssv6006C_reg.h	2240;"	d
+GET_SBUS_DMAC_CH_RAW_TR	smac/hal/ssv6006c/ssv6006C_reg.h	2239;"	d
+GET_SBUS_DMAC_CH_STATUSERR_TR	smac/hal/ssv6006c/ssv6006C_reg.h	2242;"	d
+GET_SBUS_DMAC_CH_STATUSTR_TR	smac/hal/ssv6006c/ssv6006C_reg.h	2241;"	d
+GET_SBUS_DMAC_DAR0	smac/hal/ssv6006c/ssv6006C_reg.h	2206;"	d
+GET_SBUS_DMAC_DAR1	smac/hal/ssv6006c/ssv6006C_reg.h	2223;"	d
+GET_SBUS_DMAC_DINC0	smac/hal/ssv6006c/ssv6006C_reg.h	2210;"	d
+GET_SBUS_DMAC_DINC1	smac/hal/ssv6006c/ssv6006C_reg.h	2227;"	d
+GET_SBUS_DMAC_DISEN_SHS_DST_REQ	smac/hal/ssv6006c/ssv6006C_reg.h	2250;"	d
+GET_SBUS_DMAC_DISEN_SHS_DST_SREQ	smac/hal/ssv6006c/ssv6006C_reg.h	2252;"	d
+GET_SBUS_DMAC_DISEN_SHS_SRC_REQ	smac/hal/ssv6006c/ssv6006C_reg.h	2249;"	d
+GET_SBUS_DMAC_DISEN_SHS_SRC_SREQ	smac/hal/ssv6006c/ssv6006C_reg.h	2251;"	d
+GET_SBUS_DMAC_DST_HS_BUS_SEL0	smac/hal/ssv6006c/ssv6006C_reg.h	2221;"	d
+GET_SBUS_DMAC_DST_HS_BUS_SEL1	smac/hal/ssv6006c/ssv6006C_reg.h	2238;"	d
+GET_SBUS_DMAC_DST_MSIZE0	smac/hal/ssv6006c/ssv6006C_reg.h	2212;"	d
+GET_SBUS_DMAC_DST_MSIZE1	smac/hal/ssv6006c/ssv6006C_reg.h	2229;"	d
+GET_SBUS_DMAC_DST_TR_WIDTH0	smac/hal/ssv6006c/ssv6006C_reg.h	2208;"	d
+GET_SBUS_DMAC_DST_TR_WIDTH1	smac/hal/ssv6006c/ssv6006C_reg.h	2225;"	d
+GET_SBUS_DMAC_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2253;"	d
+GET_SBUS_DMAC_FC_MODE0	smac/hal/ssv6006c/ssv6006C_reg.h	2214;"	d
+GET_SBUS_DMAC_FC_MODE1	smac/hal/ssv6006c/ssv6006C_reg.h	2231;"	d
+GET_SBUS_DMAC_HS_SEL_DST0	smac/hal/ssv6006c/ssv6006C_reg.h	2217;"	d
+GET_SBUS_DMAC_HS_SEL_DST1	smac/hal/ssv6006c/ssv6006C_reg.h	2234;"	d
+GET_SBUS_DMAC_HS_SEL_SRC0	smac/hal/ssv6006c/ssv6006C_reg.h	2218;"	d
+GET_SBUS_DMAC_HS_SEL_SRC1	smac/hal/ssv6006c/ssv6006C_reg.h	2235;"	d
+GET_SBUS_DMAC_INTR_EN0	smac/hal/ssv6006c/ssv6006C_reg.h	2207;"	d
+GET_SBUS_DMAC_INTR_EN1	smac/hal/ssv6006c/ssv6006C_reg.h	2224;"	d
+GET_SBUS_DMAC_MAX_BURST_LEN0	smac/hal/ssv6006c/ssv6006C_reg.h	2219;"	d
+GET_SBUS_DMAC_MAX_BURST_LEN1	smac/hal/ssv6006c/ssv6006C_reg.h	2236;"	d
+GET_SBUS_DMAC_SAR0	smac/hal/ssv6006c/ssv6006C_reg.h	2205;"	d
+GET_SBUS_DMAC_SAR1	smac/hal/ssv6006c/ssv6006C_reg.h	2222;"	d
+GET_SBUS_DMAC_SINC0	smac/hal/ssv6006c/ssv6006C_reg.h	2211;"	d
+GET_SBUS_DMAC_SINC1	smac/hal/ssv6006c/ssv6006C_reg.h	2228;"	d
+GET_SBUS_DMAC_SRC_HS_BUS_SEL0	smac/hal/ssv6006c/ssv6006C_reg.h	2220;"	d
+GET_SBUS_DMAC_SRC_HS_BUS_SEL1	smac/hal/ssv6006c/ssv6006C_reg.h	2237;"	d
+GET_SBUS_DMAC_SRC_MSIZE0	smac/hal/ssv6006c/ssv6006C_reg.h	2213;"	d
+GET_SBUS_DMAC_SRC_MSIZE1	smac/hal/ssv6006c/ssv6006C_reg.h	2230;"	d
+GET_SBUS_DMAC_SRC_TR_WIDTH0	smac/hal/ssv6006c/ssv6006C_reg.h	2209;"	d
+GET_SBUS_DMAC_SRC_TR_WIDTH1	smac/hal/ssv6006c/ssv6006C_reg.h	2226;"	d
+GET_SCL	smac/hal/ssv6006c/ssv6006C_reg.h	2774;"	d
+GET_SCOREBOAD_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	3447;"	d
+GET_SCRT_CCMP_CERR	include/ssv6200_reg.h	3200;"	d
+GET_SCRT_CCMP_CERR	smac/hal/ssv6006c/ssv6006C_reg.h	4048;"	d
+GET_SCRT_CCMP_RPLY	include/ssv6200_reg.h	3199;"	d
+GET_SCRT_CCMP_RPLY	smac/hal/ssv6006c/ssv6006C_reg.h	4047;"	d
+GET_SCRT_CLK_EN	include/ssv6200_reg.h	3068;"	d
+GET_SCRT_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3900;"	d
+GET_SCRT_CSR_CLK_EN	include/ssv6200_reg.h	3084;"	d
+GET_SCRT_CSR_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3916;"	d
+GET_SCRT_CSR_RST	include/ssv6200_reg.h	3056;"	d
+GET_SCRT_CSR_RST	smac/hal/ssv6006c/ssv6006C_reg.h	3888;"	d
+GET_SCRT_ENG_CLK_EN	include/ssv6200_reg.h	3079;"	d
+GET_SCRT_ENG_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3911;"	d
+GET_SCRT_ENG_RST	include/ssv6200_reg.h	3044;"	d
+GET_SCRT_ENG_RST	smac/hal/ssv6006c/ssv6006C_reg.h	3876;"	d
+GET_SCRT_INT_1	include/ssv6200_reg.h	2251;"	d
+GET_SCRT_INT_1_SD	include/ssv6200_reg.h	2320;"	d
+GET_SCRT_PKT_CLS_MIB_EN	include/ssv6200_reg.h	3143;"	d
+GET_SCRT_PKT_CLS_MIB_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3991;"	d
+GET_SCRT_PKT_CLS_ONGOING	include/ssv6200_reg.h	3144;"	d
+GET_SCRT_PKT_CLS_ONGOING	smac/hal/ssv6006c/ssv6006C_reg.h	3992;"	d
+GET_SCRT_PKT_ID	include/ssv6200_reg.h	3104;"	d
+GET_SCRT_PKT_ID	smac/hal/ssv6006c/ssv6006C_reg.h	3937;"	d
+GET_SCRT_RPLY_IGNORE	include/ssv6200_reg.h	3105;"	d
+GET_SCRT_RPLY_IGNORE	smac/hal/ssv6006c/ssv6006C_reg.h	3938;"	d
+GET_SCRT_STATE	include/ssv6200_reg.h	3099;"	d
+GET_SCRT_STATE	smac/hal/ssv6006c/ssv6006C_reg.h	3939;"	d
+GET_SCRT_SW_RST	include/ssv6200_reg.h	3033;"	d
+GET_SCRT_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	3865;"	d
+GET_SCRT_TKIP_CERR	include/ssv6200_reg.h	3196;"	d
+GET_SCRT_TKIP_CERR	smac/hal/ssv6006c/ssv6006C_reg.h	4044;"	d
+GET_SCRT_TKIP_MIC_ERR	include/ssv6200_reg.h	3197;"	d
+GET_SCRT_TKIP_MIC_ERR	smac/hal/ssv6006c/ssv6006C_reg.h	4045;"	d
+GET_SCRT_TKIP_RPLY	include/ssv6200_reg.h	3198;"	d
+GET_SCRT_TKIP_RPLY	smac/hal/ssv6006c/ssv6006C_reg.h	4046;"	d
+GET_SDA	smac/hal/ssv6006c/ssv6006C_reg.h	2775;"	d
+GET_SDIO_ALL_RESET	include/ssv6200_reg.h	1942;"	d
+GET_SDIO_ALL_RESET	smac/hal/ssv6006c/ssv6006C_reg.h	2700;"	d
+GET_SDIO_ALL_RESE_ACTIVE	include/ssv6200_reg.h	1904;"	d
+GET_SDIO_BUSY_LONG_CNT	include/ssv6200_reg.h	1928;"	d
+GET_SDIO_BUS_STATE_REG	include/ssv6200_reg.h	1927;"	d
+GET_SDIO_BYTE_MODE_BATCH_SIZE_REG	include/ssv6200_reg.h	1923;"	d
+GET_SDIO_BYTE_MODE_BATCH_SIZE_REG	smac/hal/ssv6006c/ssv6006C_reg.h	2681;"	d
+GET_SDIO_CARD_STATUS_REG	include/ssv6200_reg.h	1929;"	d
+GET_SDIO_CARD_STATUS_REG	smac/hal/ssv6006c/ssv6006C_reg.h	2682;"	d
+GET_SDIO_CLK_EN	include/ssv6200_reg.h	1303;"	d
+GET_SDIO_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2382;"	d
+GET_SDIO_CMD52_06H_RESET	smac/hal/ssv6006c/ssv6006C_reg.h	2488;"	d
+GET_SDIO_CRC16_ERROR_CNT	include/ssv6200_reg.h	1950;"	d
+GET_SDIO_CRC7_ERROR_CNT	include/ssv6200_reg.h	1949;"	d
+GET_SDIO_FIFO_EMPTY_CNT	include/ssv6200_reg.h	1947;"	d
+GET_SDIO_FIFO_FULL_CNT	include/ssv6200_reg.h	1948;"	d
+GET_SDIO_FIFO_RD_PTR_REG	include/ssv6200_reg.h	1956;"	d
+GET_SDIO_FIFO_WR_LIMIT_REG	include/ssv6200_reg.h	1917;"	d
+GET_SDIO_FIFO_WR_PTR_REG	include/ssv6200_reg.h	1955;"	d
+GET_SDIO_FIFO_WR_THLD_REG	include/ssv6200_reg.h	1916;"	d
+GET_SDIO_LAST_CMD_ARG_REG	include/ssv6200_reg.h	1926;"	d
+GET_SDIO_LAST_CMD_CRC_REG	include/ssv6200_reg.h	1925;"	d
+GET_SDIO_LAST_CMD_INDEX_REG	include/ssv6200_reg.h	1924;"	d
+GET_SDIO_LOOP_BACK_TEST	include/ssv6200_reg.h	1900;"	d
+GET_SDIO_PARTIAL_RESET	include/ssv6200_reg.h	1941;"	d
+GET_SDIO_PARTIAL_RESET	smac/hal/ssv6006c/ssv6006C_reg.h	2699;"	d
+GET_SDIO_PARTIAL_RESET_ACTIVE	include/ssv6200_reg.h	1903;"	d
+GET_SDIO_RD_BLOCK_CNT	include/ssv6200_reg.h	1951;"	d
+GET_SDIO_READ_DATA_CTRL	include/ssv6200_reg.h	1957;"	d
+GET_SDIO_RX_DATA_BATCH_SIZE_REG	include/ssv6200_reg.h	1920;"	d
+GET_SDIO_SW_RST	include/ssv6200_reg.h	1269;"	d
+GET_SDIO_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	2349;"	d
+GET_SDIO_SYS_INT	include/ssv6200_reg.h	2086;"	d
+GET_SDIO_THLD_FOR_CMD53RD_REG	include/ssv6200_reg.h	1919;"	d
+GET_SDIO_TO_MCU_INFO	include/ssv6200_reg.h	1940;"	d
+GET_SDIO_TO_MCU_INFO	smac/hal/ssv6006c/ssv6006C_reg.h	2698;"	d
+GET_SDIO_TRANS_CNT	include/ssv6200_reg.h	2526;"	d
+GET_SDIO_TRANS_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	3239;"	d
+GET_SDIO_TRX_DATA_SEQUENCE	include/ssv6200_reg.h	1893;"	d
+GET_SDIO_TRX_DATA_SEQUENCE	smac/hal/ssv6006c/ssv6006C_reg.h	2676;"	d
+GET_SDIO_TX_ALLOC_STATE	include/ssv6200_reg.h	1960;"	d
+GET_SDIO_TX_DATA_BATCH_SIZE_REG	include/ssv6200_reg.h	1918;"	d
+GET_SDIO_TX_INVALID_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	3236;"	d
+GET_SDIO_TX_INVALID_CNT_31_0	include/ssv6200_reg.h	2527;"	d
+GET_SDIO_TX_INVALID_CNT_47_32	include/ssv6200_reg.h	2528;"	d
+GET_SDIO_WR_BLOCK_CNT	include/ssv6200_reg.h	1952;"	d
+GET_SD_CMD_IN_DLY_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	2687;"	d
+GET_SD_CMD_OUT_DLY_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	2688;"	d
+GET_SD_DAT_0_IN_DLY_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	2695;"	d
+GET_SD_DAT_0_OUT_DLY_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	2696;"	d
+GET_SD_DAT_1_IN_DLY_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	2693;"	d
+GET_SD_DAT_1_OUT_DLY_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	2694;"	d
+GET_SD_DAT_2_IN_DLY_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	2691;"	d
+GET_SD_DAT_2_OUT_DLY_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	2692;"	d
+GET_SD_DAT_3_IN_DLY_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	2689;"	d
+GET_SD_DAT_3_OUT_DLY_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	2690;"	d
+GET_SD_HOST_INIT	include/ssv6200_reg.h	1384;"	d
+GET_SD_MASK_TOP	include/ssv6200_reg.h	2281;"	d
+GET_SD_RX_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	3192;"	d
+GET_SD_SSDR104	smac/hal/ssv6006c/ssv6006C_reg.h	2723;"	d
+GET_SD_SSDR50	smac/hal/ssv6006c/ssv6006C_reg.h	2722;"	d
+GET_SECONDARY_EDCA	smac/dev.h	202;"	d
+GET_SEL_BTCX	smac/hal/ssv6006c/ssv6006C_reg.h	2627;"	d
+GET_SEL_DEBUG_I	smac/hal/ssv6006c/ssv6006C_reg.h	2631;"	d
+GET_SEL_DEBUG_II	smac/hal/ssv6006c/ssv6006C_reg.h	2632;"	d
+GET_SEL_FLASH	smac/hal/ssv6006c/ssv6006C_reg.h	2628;"	d
+GET_SEL_GPO_INT	smac/hal/ssv6006c/ssv6006C_reg.h	2639;"	d
+GET_SEL_I2C_MST_I	smac/hal/ssv6006c/ssv6006C_reg.h	2624;"	d
+GET_SEL_I2C_MST_II	smac/hal/ssv6006c/ssv6006C_reg.h	2623;"	d
+GET_SEL_I2C_SLV	smac/hal/ssv6006c/ssv6006C_reg.h	2622;"	d
+GET_SEL_I2STRX_I	smac/hal/ssv6006c/ssv6006C_reg.h	2619;"	d
+GET_SEL_I2STRX_II	smac/hal/ssv6006c/ssv6006C_reg.h	2618;"	d
+GET_SEL_MEM_BIST	smac/hal/ssv6006c/ssv6006C_reg.h	2633;"	d
+GET_SEL_PWM	smac/hal/ssv6006c/ssv6006C_reg.h	2630;"	d
+GET_SEL_RF	smac/hal/ssv6006c/ssv6006C_reg.h	2629;"	d
+GET_SEL_SPI_MST	smac/hal/ssv6006c/ssv6006C_reg.h	2621;"	d
+GET_SEL_SPI_SLV	smac/hal/ssv6006c/ssv6006C_reg.h	2620;"	d
+GET_SEL_UART0_I	smac/hal/ssv6006c/ssv6006C_reg.h	2626;"	d
+GET_SEL_UART0_II	smac/hal/ssv6006c/ssv6006C_reg.h	2625;"	d
+GET_SEL_USB_BIST	smac/hal/ssv6006c/ssv6006C_reg.h	2634;"	d
+GET_SEL_USB_IDDQ	smac/hal/ssv6006c/ssv6006C_reg.h	2636;"	d
+GET_SEL_USB_TEST	smac/hal/ssv6006c/ssv6006C_reg.h	2635;"	d
+GET_SEQ_CTRL	include/ssv6200_reg.h	2494;"	d
+GET_SEQ_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	3200;"	d
+GET_SET_BREAK	include/ssv6200_reg.h	2133;"	d
+GET_SET_BREAK	smac/hal/ssv6006c/ssv6006C_reg.h	2843;"	d
+GET_SFD_CNT	include/ssv6200_reg.h	4182;"	d
+GET_SFD_FIELD	include/ssv6200_reg.h	4188;"	d
+GET_SHA_BUSY	include/ssv6200_reg.h	2559;"	d
+GET_SHA_BUSY	smac/hal/ssv6006c/ssv6006C_reg.h	3297;"	d
+GET_SHA_DST_ADDR	include/ssv6200_reg.h	2557;"	d
+GET_SHA_DST_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	3295;"	d
+GET_SHA_ENDIAN	include/ssv6200_reg.h	2560;"	d
+GET_SHA_ENDIAN	smac/hal/ssv6006c/ssv6006C_reg.h	3298;"	d
+GET_SHA_SRC_ADDR	include/ssv6200_reg.h	2558;"	d
+GET_SHA_SRC_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	3296;"	d
+GET_SHIFT_DR	include/ssv6200_reg.h	1338;"	d
+GET_SHORT_TO_20_ID	include/ssv6200_reg.h	1507;"	d
+GET_SHRT_GI	include/ssv6200_reg.h	2552;"	d
+GET_SHRT_GI	smac/hal/ssv6006c/ssv6006C_reg.h	3290;"	d
+GET_SHRT_PREAM	include/ssv6200_reg.h	2551;"	d
+GET_SHRT_PREAM	smac/hal/ssv6006c/ssv6006C_reg.h	3289;"	d
+GET_SIFS	smac/hal/ssv6006c/ssv6006C_reg.h	3612;"	d
+GET_SIGEXT	smac/hal/ssv6006c/ssv6006C_reg.h	3616;"	d
+GET_SIGNAL_FIELD	include/ssv6200_reg.h	4189;"	d
+GET_SIGNAL_FIELD0	include/ssv6200_reg.h	4312;"	d
+GET_SIGNAL_FIELD1	include/ssv6200_reg.h	4313;"	d
+GET_SIMPLING_INFO	smartlink/qqlink-lib-mipsel/include/TXAudioVideo.h	29;"	d
+GET_SIMULATION_MODE	include/ssv6200_reg.h	1340;"	d
+GET_SLEEP_WAKE_CNT	include/ssv6200_reg.h	2430;"	d
+GET_SLOTTIME	smac/hal/ssv6006c/ssv6006C_reg.h	3611;"	d
+GET_SMS4_BUSY	include/ssv6200_reg.h	2612;"	d
+GET_SMS4_CBC_EN	include/ssv6200_reg.h	2608;"	d
+GET_SMS4_CFB_EN	include/ssv6200_reg.h	2609;"	d
+GET_SMS4_DATAIN_0	include/ssv6200_reg.h	2614;"	d
+GET_SMS4_DATAIN_1	include/ssv6200_reg.h	2615;"	d
+GET_SMS4_DATAIN_2	include/ssv6200_reg.h	2616;"	d
+GET_SMS4_DATAIN_3	include/ssv6200_reg.h	2617;"	d
+GET_SMS4_DATAOUT_0	include/ssv6200_reg.h	2618;"	d
+GET_SMS4_DATAOUT_1	include/ssv6200_reg.h	2619;"	d
+GET_SMS4_DATAOUT_2	include/ssv6200_reg.h	2620;"	d
+GET_SMS4_DATAOUT_3	include/ssv6200_reg.h	2621;"	d
+GET_SMS4_DESCRY_EN	include/ssv6200_reg.h	2602;"	d
+GET_SMS4_DONE	include/ssv6200_reg.h	2613;"	d
+GET_SMS4_KEY_0	include/ssv6200_reg.h	2622;"	d
+GET_SMS4_KEY_1	include/ssv6200_reg.h	2623;"	d
+GET_SMS4_KEY_2	include/ssv6200_reg.h	2624;"	d
+GET_SMS4_KEY_3	include/ssv6200_reg.h	2625;"	d
+GET_SMS4_MODE_IV0	include/ssv6200_reg.h	2626;"	d
+GET_SMS4_MODE_IV1	include/ssv6200_reg.h	2627;"	d
+GET_SMS4_MODE_IV2	include/ssv6200_reg.h	2628;"	d
+GET_SMS4_MODE_IV3	include/ssv6200_reg.h	2629;"	d
+GET_SMS4_OFB_EN	include/ssv6200_reg.h	2610;"	d
+GET_SMS4_OFB_ENC0	include/ssv6200_reg.h	2630;"	d
+GET_SMS4_OFB_ENC1	include/ssv6200_reg.h	2631;"	d
+GET_SMS4_OFB_ENC2	include/ssv6200_reg.h	2632;"	d
+GET_SMS4_OFB_ENC3	include/ssv6200_reg.h	2633;"	d
+GET_SMS4_START_TRIG	include/ssv6200_reg.h	2611;"	d
+GET_SNIFFER_MODE	include/ssv6200_reg.h	3091;"	d
+GET_SNIFFER_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	3923;"	d
+GET_SOC_SYSTEM_INT_STATUS	include/ssv6200_reg.h	1880;"	d
+GET_SOC_SYSTEM_INT_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	2663;"	d
+GET_SOC_TRIGGER_RX_INT	include/ssv6200_reg.h	1888;"	d
+GET_SOC_TRIGGER_RX_INT	smac/hal/ssv6006c/ssv6006C_reg.h	2671;"	d
+GET_SOC_TRIGGER_TX_INT	include/ssv6200_reg.h	1889;"	d
+GET_SOC_TRIGGER_TX_INT	smac/hal/ssv6006c/ssv6006C_reg.h	2672;"	d
+GET_SPARE_MEM	smac/hal/ssv6006c/ssv6006C_reg.h	2763;"	d
+GET_SPIMAS_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2408;"	d
+GET_SPIMST_CEN_ENABLE	smac/hal/ssv6006c/ssv6006C_reg.h	2324;"	d
+GET_SPIMST_CPHA	smac/hal/ssv6006c/ssv6006C_reg.h	2319;"	d
+GET_SPIMST_CPOL	smac/hal/ssv6006c/ssv6006C_reg.h	2320;"	d
+GET_SPIMST_DATA_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	2318;"	d
+GET_SPIMST_ENABLE	smac/hal/ssv6006c/ssv6006C_reg.h	2323;"	d
+GET_SPIMST_RXFIFO_TH	smac/hal/ssv6006c/ssv6006C_reg.h	2327;"	d
+GET_SPIMST_RXF_INT	smac/hal/ssv6006c/ssv6006C_reg.h	2343;"	d
+GET_SPIMST_RXF_INT_UNMASK	smac/hal/ssv6006c/ssv6006C_reg.h	2338;"	d
+GET_SPIMST_RXO_INT	smac/hal/ssv6006c/ssv6006C_reg.h	2342;"	d
+GET_SPIMST_RXO_INT_UNMASK	smac/hal/ssv6006c/ssv6006C_reg.h	2337;"	d
+GET_SPIMST_RXU_INT	smac/hal/ssv6006c/ssv6006C_reg.h	2341;"	d
+GET_SPIMST_RXU_INT_UNMASK	smac/hal/ssv6006c/ssv6006C_reg.h	2336;"	d
+GET_SPIMST_RX_SAMPLE_DLY	smac/hal/ssv6006c/ssv6006C_reg.h	2345;"	d
+GET_SPIMST_SCLK_RATE	smac/hal/ssv6006c/ssv6006C_reg.h	2325;"	d
+GET_SPIMST_TRX_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	2344;"	d
+GET_SPIMST_TXE_INT	smac/hal/ssv6006c/ssv6006C_reg.h	2339;"	d
+GET_SPIMST_TXE_INT_UNMASK	smac/hal/ssv6006c/ssv6006C_reg.h	2334;"	d
+GET_SPIMST_TXFIFO_TH	smac/hal/ssv6006c/ssv6006C_reg.h	2326;"	d
+GET_SPIMST_TXO_INT	smac/hal/ssv6006c/ssv6006C_reg.h	2340;"	d
+GET_SPIMST_TXO_INT_UNMASK	smac/hal/ssv6006c/ssv6006C_reg.h	2335;"	d
+GET_SPI_ALLOC_STATUS	include/ssv6200_reg.h	2064;"	d
+GET_SPI_BUSY	include/ssv6200_reg.h	2406;"	d
+GET_SPI_BUSY	smac/hal/ssv6006c/ssv6006C_reg.h	2960;"	d
+GET_SPI_CLK_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	3344;"	d
+GET_SPI_CLK_EN_INT	include/ssv6200_reg.h	2093;"	d
+GET_SPI_CLR	smac/hal/ssv6006c/ssv6006C_reg.h	3346;"	d
+GET_SPI_CSN	smac/hal/ssv6006c/ssv6006C_reg.h	3356;"	d
+GET_SPI_DBG_WR_FIFO_FULL	include/ssv6200_reg.h	2065;"	d
+GET_SPI_DI_SEL	include/ssv6200_reg.h	1868;"	d
+GET_SPI_DOUBLE_ALLOC	include/ssv6200_reg.h	2061;"	d
+GET_SPI_FLASH_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	2961;"	d
+GET_SPI_FN1	include/ssv6200_reg.h	2092;"	d
+GET_SPI_F_MISO_CLK_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	2983;"	d
+GET_SPI_HOST_MASK	include/ssv6200_reg.h	2094;"	d
+GET_SPI_HOST_TX_ALLOC_PKBUF	include/ssv6200_reg.h	2068;"	d
+GET_SPI_IPC_ADDR	include/ssv6200_reg.h	2280;"	d
+GET_SPI_MASTER_BUSY	smac/hal/ssv6006c/ssv6006C_reg.h	3345;"	d
+GET_SPI_MODE	include/ssv6200_reg.h	2047;"	d
+GET_SPI_MST2CBRA_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2399;"	d
+GET_SPI_M_BACK_DLY	smac/hal/ssv6006c/ssv6006C_reg.h	3343;"	d
+GET_SPI_M_FRONT_DLY	smac/hal/ssv6006c/ssv6006C_reg.h	3342;"	d
+GET_SPI_RAW_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	2638;"	d
+GET_SPI_SLV_CLK_EN	include/ssv6200_reg.h	1304;"	d
+GET_SPI_SLV_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2383;"	d
+GET_SPI_SLV_SW_RST	include/ssv6200_reg.h	1270;"	d
+GET_SPI_SLV_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	2350;"	d
+GET_SPI_TX_ALLOC_SIZE	include/ssv6200_reg.h	2069;"	d
+GET_SPI_TX_ALLOC_SIZE_SHIFT_BITS	include/ssv6200_reg.h	2067;"	d
+GET_SPI_TX_NO_ALLOC	include/ssv6200_reg.h	2062;"	d
+GET_SRAM_ACCESS_MD	include/ssv6200_reg.h	4799;"	d
+GET_SRAM_ADDR	include/ssv6200_reg.h	2401;"	d
+GET_SRAM_TAG_0	include/ssv6200_reg.h	4891;"	d
+GET_SRAM_TAG_1	include/ssv6200_reg.h	4892;"	d
+GET_SRAM_TAG_10	include/ssv6200_reg.h	4901;"	d
+GET_SRAM_TAG_11	include/ssv6200_reg.h	4902;"	d
+GET_SRAM_TAG_12	include/ssv6200_reg.h	4903;"	d
+GET_SRAM_TAG_13	include/ssv6200_reg.h	4904;"	d
+GET_SRAM_TAG_14	include/ssv6200_reg.h	4905;"	d
+GET_SRAM_TAG_15	include/ssv6200_reg.h	4906;"	d
+GET_SRAM_TAG_2	include/ssv6200_reg.h	4893;"	d
+GET_SRAM_TAG_3	include/ssv6200_reg.h	4894;"	d
+GET_SRAM_TAG_4	include/ssv6200_reg.h	4895;"	d
+GET_SRAM_TAG_5	include/ssv6200_reg.h	4896;"	d
+GET_SRAM_TAG_6	include/ssv6200_reg.h	4897;"	d
+GET_SRAM_TAG_7	include/ssv6200_reg.h	4898;"	d
+GET_SRAM_TAG_8	include/ssv6200_reg.h	4899;"	d
+GET_SRAM_TAG_9	include/ssv6200_reg.h	4900;"	d
+GET_START_BYTE_VALUE	include/ssv6200_reg.h	1921;"	d
+GET_START_BYTE_VALUE2	include/ssv6200_reg.h	1983;"	d
+GET_STAT_CLR	smac/hal/ssv6006c/ssv6006C_reg.h	3563;"	d
+GET_STAT_CLR_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	3564;"	d
+GET_STAT_ENABLE	smac/hal/ssv6006c/ssv6006C_reg.h	3560;"	d
+GET_STAT_EN_MB	smac/hal/ssv6006c/ssv6006C_reg.h	3554;"	d
+GET_STAT_FINISH	smac/hal/ssv6006c/ssv6006C_reg.h	3557;"	d
+GET_STAT_FREEZE	smac/hal/ssv6006c/ssv6006C_reg.h	3562;"	d
+GET_STAT_FSM	smac/hal/ssv6006c/ssv6006C_reg.h	3559;"	d
+GET_STAT_MB_TARGET	smac/hal/ssv6006c/ssv6006C_reg.h	3555;"	d
+GET_STAT_PKT_ID	smac/hal/ssv6006c/ssv6006C_reg.h	3558;"	d
+GET_STAT_UNEXPECT_WSID	smac/hal/ssv6006c/ssv6006C_reg.h	3556;"	d
+GET_STAT_WSID	smac/hal/ssv6006c/ssv6006C_reg.h	3561;"	d
+GET_STA_MAC1_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	3942;"	d
+GET_STA_MAC1_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	3943;"	d
+GET_STA_MAC_31_0	include/ssv6200_reg.h	3100;"	d
+GET_STA_MAC_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	3933;"	d
+GET_STA_MAC_47_32	include/ssv6200_reg.h	3101;"	d
+GET_STA_MAC_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	3934;"	d
+GET_STOP_BIT	include/ssv6200_reg.h	2129;"	d
+GET_STOP_BIT	smac/hal/ssv6006c/ssv6006C_reg.h	2839;"	d
+GET_STOP_MBOX	include/ssv6200_reg.h	3601;"	d
+GET_STOP_MBOX_IN	smac/hal/ssv6006c/ssv6006C_reg.h	8796;"	d
+GET_STOP_MBOX_OUT	smac/hal/ssv6006c/ssv6006C_reg.h	8795;"	d
+GET_STOP_MBOX_OUT_SUCCESS	smac/hal/ssv6006c/ssv6006C_reg.h	8812;"	d
+GET_STRAP0	include/ssv6200_reg.h	1515;"	d
+GET_STRAP1	include/ssv6200_reg.h	1551;"	d
+GET_STRAP2	include/ssv6200_reg.h	1826;"	d
+GET_STRAP3	include/ssv6200_reg.h	1524;"	d
+GET_SUMMARY_TYPHOST_INT_MAP	smac/hal/ssv6006c/ssv6006C_reg.h	3029;"	d
+GET_SUMMARY_TYPMCU_INT_MAP	smac/hal/ssv6006c/ssv6006C_reg.h	3042;"	d
+GET_SUPPORT_BLOCK_GAP_INTERRUPT	include/ssv6200_reg.h	2003;"	d
+GET_SUPPORT_BLOCK_GAP_INTERRUPT	smac/hal/ssv6006c/ssv6006C_reg.h	2717;"	d
+GET_SUPPORT_BUS_CONTROL	include/ssv6200_reg.h	2002;"	d
+GET_SUPPORT_BUS_CONTROL	smac/hal/ssv6006c/ssv6006C_reg.h	2716;"	d
+GET_SUPPORT_DIRECT_COMMAND_SDIO	include/ssv6200_reg.h	1999;"	d
+GET_SUPPORT_DIRECT_COMMAND_SDIO	smac/hal/ssv6006c/ssv6006C_reg.h	2713;"	d
+GET_SUPPORT_HIGH_SPEED	include/ssv6200_reg.h	2008;"	d
+GET_SUPPORT_HIGH_SPEED	smac/hal/ssv6006c/ssv6006C_reg.h	2724;"	d
+GET_SUPPORT_MULTIPLE_BLOCK_TRANSFER	include/ssv6200_reg.h	2000;"	d
+GET_SUPPORT_MULTIPLE_BLOCK_TRANSFER	smac/hal/ssv6006c/ssv6006C_reg.h	2714;"	d
+GET_SUPPORT_READ_WAIT	include/ssv6200_reg.h	2001;"	d
+GET_SUPPORT_READ_WAIT	smac/hal/ssv6006c/ssv6006C_reg.h	2715;"	d
+GET_SUSPEND_PWR_ON1	smac/hal/ssv6006c/ssv6006C_reg.h	2495;"	d
+GET_SUSPEND_PWR_ON2	smac/hal/ssv6006c/ssv6006C_reg.h	2496;"	d
+GET_SUSPEND_PWR_ON3	smac/hal/ssv6006c/ssv6006C_reg.h	2497;"	d
+GET_SVN_VERSION	include/ssv6200_reg.h	3888;"	d
+GET_SVN_VERSION	smac/hal/ssv6006c/ssv6006C_reg.h	8207;"	d
+GET_SWITCH_2WIRE_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3970;"	d
+GET_SW_BT_TRX	include/ssv6200_reg.h	3126;"	d
+GET_SW_BT_TRX	smac/hal/ssv6006c/ssv6006C_reg.h	3965;"	d
+GET_SW_MANUAL_EN	include/ssv6200_reg.h	3123;"	d
+GET_SW_MANUAL_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3962;"	d
+GET_SW_WL_RX	include/ssv6200_reg.h	3125;"	d
+GET_SW_WL_RX	smac/hal/ssv6006c/ssv6006C_reg.h	3964;"	d
+GET_SW_WL_TX	include/ssv6200_reg.h	3124;"	d
+GET_SW_WL_TX	smac/hal/ssv6006c/ssv6006C_reg.h	3963;"	d
+GET_SYSCTRL_CMD	smac/hal/ssv6006c/ssv6006C_reg.h	2431;"	d
+GET_SYSTEM_INT	include/ssv6200_reg.h	1914;"	d
+GET_SYS_ALL_RST	include/ssv6200_reg.h	1287;"	d
+GET_SYS_CLK_EN	include/ssv6200_reg.h	1300;"	d
+GET_SYS_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2379;"	d
+GET_SYS_CLOCK_STATE	smac/hal/ssv6006c/ssv6006C_reg.h	2422;"	d
+GET_SYS_DPLL_ON	smac/hal/ssv6006c/ssv6006C_reg.h	2434;"	d
+GET_SYS_N10_IVB_VAL	smac/hal/ssv6006c/ssv6006C_reg.h	2478;"	d
+GET_SYS_PMU_MODE_TRAN_INT	smac/hal/ssv6006c/ssv6006C_reg.h	2481;"	d
+GET_SYS_RST_INT	include/ssv6200_reg.h	2279;"	d
+GET_SYS_WDOG_ENA	include/ssv6200_reg.h	1433;"	d
+GET_SYS_WDOG_ENA	smac/hal/ssv6006c/ssv6006C_reg.h	2571;"	d
+GET_SYS_WDT_INT_CNT_OFS	smac/hal/ssv6006c/ssv6006C_reg.h	2569;"	d
+GET_SYS_WDT_STATUS	include/ssv6200_reg.h	1432;"	d
+GET_SYS_WDT_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	2570;"	d
+GET_SYS_WDT_TIME_CNT	include/ssv6200_reg.h	1431;"	d
+GET_SYS_WDT_TIME_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	2568;"	d
+GET_SYS_XOSC_ON	smac/hal/ssv6006c/ssv6006C_reg.h	2433;"	d
+GET_TAG_INTERLEAVE_MD	include/ssv6200_reg.h	4795;"	d
+GET_TAG_SW_RST_N	include/ssv6200_reg.h	4805;"	d
+GET_TBLNEQ_MNGPKT_INT_IRQ	include/ssv6200_reg.h	2275;"	d
+GET_TBLNEQ_MNGPKT_INT_IRQ_SD	include/ssv6200_reg.h	2344;"	d
+GET_TB_ADR_SEL	include/ssv6200_reg.h	1347;"	d
+GET_TB_ADR_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	2427;"	d
+GET_TB_CS	include/ssv6200_reg.h	1348;"	d
+GET_TB_CS	smac/hal/ssv6006c/ssv6006C_reg.h	2428;"	d
+GET_TB_RDATA	include/ssv6200_reg.h	1349;"	d
+GET_TB_RDATA	smac/hal/ssv6006c/ssv6006C_reg.h	2429;"	d
+GET_TEST_10_ID	include/ssv6200_reg.h	1617;"	d
+GET_TEST_11_ID	include/ssv6200_reg.h	1625;"	d
+GET_TEST_12_ID	include/ssv6200_reg.h	1633;"	d
+GET_TEST_13_ID	include/ssv6200_reg.h	1641;"	d
+GET_TEST_14_ID	include/ssv6200_reg.h	1649;"	d
+GET_TEST_15_ID	include/ssv6200_reg.h	1657;"	d
+GET_TEST_16_ID	include/ssv6200_reg.h	1746;"	d
+GET_TEST_17_ID	include/ssv6200_reg.h	1754;"	d
+GET_TEST_18_ID	include/ssv6200_reg.h	1762;"	d
+GET_TEST_19_ID	include/ssv6200_reg.h	1770;"	d
+GET_TEST_1_ID	include/ssv6200_reg.h	1475;"	d
+GET_TEST_20_ID	include/ssv6200_reg.h	1778;"	d
+GET_TEST_2_ID	include/ssv6200_reg.h	1483;"	d
+GET_TEST_3_ID	include/ssv6200_reg.h	1491;"	d
+GET_TEST_4_ID	include/ssv6200_reg.h	1499;"	d
+GET_TEST_6_ID	include/ssv6200_reg.h	1585;"	d
+GET_TEST_7_ID	include/ssv6200_reg.h	1593;"	d
+GET_TEST_8_ID	include/ssv6200_reg.h	1601;"	d
+GET_TEST_9_ID	include/ssv6200_reg.h	1609;"	d
+GET_TEST_MODE0	include/ssv6200_reg.h	1377;"	d
+GET_TEST_MODE0	smac/hal/ssv6006c/ssv6006C_reg.h	2456;"	d
+GET_TEST_MODE1	include/ssv6200_reg.h	1378;"	d
+GET_TEST_MODE1	smac/hal/ssv6006c/ssv6006C_reg.h	2457;"	d
+GET_TEST_MODE2	include/ssv6200_reg.h	1379;"	d
+GET_TEST_MODE2	smac/hal/ssv6006c/ssv6006C_reg.h	2458;"	d
+GET_TEST_MODE3	include/ssv6200_reg.h	1380;"	d
+GET_TEST_MODE3	smac/hal/ssv6006c/ssv6006C_reg.h	2459;"	d
+GET_TEST_MODE4	include/ssv6200_reg.h	1381;"	d
+GET_TEST_MODE4	smac/hal/ssv6006c/ssv6006C_reg.h	2460;"	d
+GET_TEST_MODE_ALL	include/ssv6200_reg.h	1382;"	d
+GET_TEST_MODE_ALL	smac/hal/ssv6006c/ssv6006C_reg.h	2461;"	d
+GET_THREE_WIRE	smac/hal/ssv6006c/ssv6006C_reg.h	3353;"	d
+GET_THR_EMPTY	include/ssv6200_reg.h	2145;"	d
+GET_THR_EMPTY	smac/hal/ssv6006c/ssv6006C_reg.h	2856;"	d
+GET_THR_EMPTY_IE	include/ssv6200_reg.h	2116;"	d
+GET_THR_EMPTY_IE	smac/hal/ssv6006c/ssv6006C_reg.h	2826;"	d
+GET_TIP_A	smac/hal/ssv6006c/ssv6006C_reg.h	2889;"	d
+GET_TM0_PRESCALER_USTIMER_LOCAL	smac/hal/ssv6006c/ssv6006C_reg.h	2545;"	d
+GET_TM0_TM_CUR_VALUE	include/ssv6200_reg.h	1412;"	d
+GET_TM0_TM_CUR_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	2544;"	d
+GET_TM0_TM_INIT_VALUE	include/ssv6200_reg.h	1408;"	d
+GET_TM0_TM_INIT_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	2540;"	d
+GET_TM0_TM_INT_MASK	include/ssv6200_reg.h	1411;"	d
+GET_TM0_TM_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	2543;"	d
+GET_TM0_TM_INT_STS_DONE	include/ssv6200_reg.h	1410;"	d
+GET_TM0_TM_INT_STS_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	2542;"	d
+GET_TM0_TM_MODE	include/ssv6200_reg.h	1409;"	d
+GET_TM0_TM_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	2541;"	d
+GET_TM1_PRESCALER_USTIMER_LOCAL	smac/hal/ssv6006c/ssv6006C_reg.h	2551;"	d
+GET_TM1_TM_CUR_VALUE	include/ssv6200_reg.h	1417;"	d
+GET_TM1_TM_CUR_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	2550;"	d
+GET_TM1_TM_INIT_VALUE	include/ssv6200_reg.h	1413;"	d
+GET_TM1_TM_INIT_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	2546;"	d
+GET_TM1_TM_INT_MASK	include/ssv6200_reg.h	1416;"	d
+GET_TM1_TM_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	2549;"	d
+GET_TM1_TM_INT_STS_DONE	include/ssv6200_reg.h	1415;"	d
+GET_TM1_TM_INT_STS_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	2548;"	d
+GET_TM1_TM_MODE	include/ssv6200_reg.h	1414;"	d
+GET_TM1_TM_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	2547;"	d
+GET_TM2_PRESCALER_USTIMER_LOCAL	smac/hal/ssv6006c/ssv6006C_reg.h	2557;"	d
+GET_TM2_TM_CUR_VALUE	include/ssv6200_reg.h	1422;"	d
+GET_TM2_TM_CUR_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	2556;"	d
+GET_TM2_TM_INIT_VALUE	include/ssv6200_reg.h	1418;"	d
+GET_TM2_TM_INIT_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	2552;"	d
+GET_TM2_TM_INT_MASK	include/ssv6200_reg.h	1421;"	d
+GET_TM2_TM_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	2555;"	d
+GET_TM2_TM_INT_STS_DONE	include/ssv6200_reg.h	1420;"	d
+GET_TM2_TM_INT_STS_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	2554;"	d
+GET_TM2_TM_MODE	include/ssv6200_reg.h	1419;"	d
+GET_TM2_TM_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	2553;"	d
+GET_TM3_PRESCALER_USTIMER_LOCAL	smac/hal/ssv6006c/ssv6006C_reg.h	2563;"	d
+GET_TM3_TM_CUR_VALUE	include/ssv6200_reg.h	1427;"	d
+GET_TM3_TM_CUR_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	2562;"	d
+GET_TM3_TM_INIT_VALUE	include/ssv6200_reg.h	1423;"	d
+GET_TM3_TM_INIT_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	2558;"	d
+GET_TM3_TM_INT_MASK	include/ssv6200_reg.h	1426;"	d
+GET_TM3_TM_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	2561;"	d
+GET_TM3_TM_INT_STS_DONE	include/ssv6200_reg.h	1425;"	d
+GET_TM3_TM_INT_STS_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	2560;"	d
+GET_TM3_TM_MODE	include/ssv6200_reg.h	1424;"	d
+GET_TM3_TM_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	2559;"	d
+GET_TOMAC_CS_CCA_MX	smac/hal/ssv6006c/ssv6006C_reg.h	3625;"	d
+GET_TOMAC_ED_CCA_PRIMARY_MX	smac/hal/ssv6006c/ssv6006C_reg.h	3623;"	d
+GET_TOMAC_ED_CCA_SECONDARY_MX	smac/hal/ssv6006c/ssv6006C_reg.h	3624;"	d
+GET_TOMAC_TX_IP	smac/hal/ssv6006c/ssv6006C_reg.h	3622;"	d
+GET_TOP_A	smac/hal/ssv6006c/ssv6006C_reg.h	2888;"	d
+GET_TOP_ON1_RST_N	smac/hal/ssv6006c/ssv6006C_reg.h	2501;"	d
+GET_TOP_ON2_RST_N	smac/hal/ssv6006c/ssv6006C_reg.h	2502;"	d
+GET_TOP_ON3_RST_N	smac/hal/ssv6006c/ssv6006C_reg.h	2503;"	d
+GET_TOP_SW_PWR_ON1_OUTPUT_PWR_ON1_1_0_0	smac/hal/ssv6006c/ssv6006C_reg.h	2452;"	d
+GET_TOP_SW_PWR_ON2_OUTPUT_PWR_ON2_1_0_0	smac/hal/ssv6006c/ssv6006C_reg.h	2453;"	d
+GET_TOP_SW_PWR_ON3_OUTPUT_PWR_ON3_1_0_0	smac/hal/ssv6006c/ssv6006C_reg.h	2454;"	d
+GET_TOUT_AGN	smac/hal/ssv6006c/ssv6006C_reg.h	3607;"	d
+GET_TOUT_B	smac/hal/ssv6006c/ssv6006C_reg.h	3606;"	d
+GET_TRAILEDGE_RI	include/ssv6200_reg.h	2150;"	d
+GET_TRAILEDGE_RI	smac/hal/ssv6006c/ssv6006C_reg.h	2861;"	d
+GET_TRANS_FULL_PKT_AMPDU1P2	smac/hal/ssv6006c/ssv6006C_reg.h	3256;"	d
+GET_TRAP_BOOT_FLS	include/ssv6200_reg.h	1293;"	d
+GET_TRAP_BOOT_FLS	smac/hal/ssv6006c/ssv6006C_reg.h	2372;"	d
+GET_TRAP_HW_ID	include/ssv6200_reg.h	2711;"	d
+GET_TRAP_HW_ID	smac/hal/ssv6006c/ssv6006C_reg.h	3435;"	d
+GET_TRAP_IMG_FLS	include/ssv6200_reg.h	1291;"	d
+GET_TRAP_IMG_FLS	smac/hal/ssv6006c/ssv6006C_reg.h	2370;"	d
+GET_TRAP_REBOOT	include/ssv6200_reg.h	1292;"	d
+GET_TRAP_REBOOT	smac/hal/ssv6006c/ssv6006C_reg.h	2371;"	d
+GET_TRAP_UNKNOWN_TYPE	include/ssv6200_reg.h	2472;"	d
+GET_TRASH_CAN_INT	include/ssv6200_reg.h	3729;"	d
+GET_TRASH_CAN_INT	smac/hal/ssv6006c/ssv6006C_reg.h	8925;"	d
+GET_TRASH_INT_ID	include/ssv6200_reg.h	3730;"	d
+GET_TRASH_INT_ID	smac/hal/ssv6006c/ssv6006C_reg.h	8926;"	d
+GET_TRASH_TIMEOUT	include/ssv6200_reg.h	3731;"	d
+GET_TRASH_TIMEOUT	smac/hal/ssv6006c/ssv6006C_reg.h	8927;"	d
+GET_TRASH_TIMEOUT_EN	include/ssv6200_reg.h	3728;"	d
+GET_TRASH_TIMEOUT_EN	smac/hal/ssv6006c/ssv6006C_reg.h	8924;"	d
+GET_TRIGGER_FUNCTION_SETTING	include/ssv6200_reg.h	1895;"	d
+GET_TRIGGER_FUNCTION_SETTING	smac/hal/ssv6006c/ssv6006C_reg.h	2678;"	d
+GET_TRSW_PHY_POL	include/ssv6200_reg.h	3115;"	d
+GET_TRSW_PHY_POL	smac/hal/ssv6006c/ssv6006C_reg.h	3954;"	d
+GET_TRXBUSYFLAG	smac/hal/ssv6006c/ssv6006C_reg.h	2328;"	d
+GET_TRX_DEBUG_CNT_ENA	include/ssv6200_reg.h	2487;"	d
+GET_TRX_DEBUG_CNT_ENA	smac/hal/ssv6006c/ssv6006C_reg.h	3184;"	d
+GET_TRX_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	2321;"	d
+GET_TTHR_H	smac/hal/ssv6006c/ssv6006C_reg.h	2875;"	d
+GET_TTHR_L	smac/hal/ssv6006c/ssv6006C_reg.h	2874;"	d
+GET_TU0_PRESCALER_USTIMER_LOCAL	smac/hal/ssv6006c/ssv6006C_reg.h	2521;"	d
+GET_TU0_TM_CUR_VALUE	include/ssv6200_reg.h	1392;"	d
+GET_TU0_TM_CUR_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	2520;"	d
+GET_TU0_TM_INIT_VALUE	include/ssv6200_reg.h	1388;"	d
+GET_TU0_TM_INIT_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	2516;"	d
+GET_TU0_TM_INT_MASK	include/ssv6200_reg.h	1391;"	d
+GET_TU0_TM_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	2519;"	d
+GET_TU0_TM_INT_STS_DONE	include/ssv6200_reg.h	1390;"	d
+GET_TU0_TM_INT_STS_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	2518;"	d
+GET_TU0_TM_MODE	include/ssv6200_reg.h	1389;"	d
+GET_TU0_TM_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	2517;"	d
+GET_TU1_PRESCALER_USTIMER_LOCAL	smac/hal/ssv6006c/ssv6006C_reg.h	2527;"	d
+GET_TU1_TM_CUR_VALUE	include/ssv6200_reg.h	1397;"	d
+GET_TU1_TM_CUR_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	2526;"	d
+GET_TU1_TM_INIT_VALUE	include/ssv6200_reg.h	1393;"	d
+GET_TU1_TM_INIT_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	2522;"	d
+GET_TU1_TM_INT_MASK	include/ssv6200_reg.h	1396;"	d
+GET_TU1_TM_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	2525;"	d
+GET_TU1_TM_INT_STS_DONE	include/ssv6200_reg.h	1395;"	d
+GET_TU1_TM_INT_STS_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	2524;"	d
+GET_TU1_TM_MODE	include/ssv6200_reg.h	1394;"	d
+GET_TU1_TM_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	2523;"	d
+GET_TU2_PRESCALER_USTIMER_LOCAL	smac/hal/ssv6006c/ssv6006C_reg.h	2533;"	d
+GET_TU2_TM_CUR_VALUE	include/ssv6200_reg.h	1402;"	d
+GET_TU2_TM_CUR_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	2532;"	d
+GET_TU2_TM_INIT_VALUE	include/ssv6200_reg.h	1398;"	d
+GET_TU2_TM_INIT_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	2528;"	d
+GET_TU2_TM_INT_MASK	include/ssv6200_reg.h	1401;"	d
+GET_TU2_TM_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	2531;"	d
+GET_TU2_TM_INT_STS_DONE	include/ssv6200_reg.h	1400;"	d
+GET_TU2_TM_INT_STS_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	2530;"	d
+GET_TU2_TM_MODE	include/ssv6200_reg.h	1399;"	d
+GET_TU2_TM_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	2529;"	d
+GET_TU3_PRESCALER_USTIMER_LOCAL	smac/hal/ssv6006c/ssv6006C_reg.h	2539;"	d
+GET_TU3_TM_CUR_VALUE	include/ssv6200_reg.h	1407;"	d
+GET_TU3_TM_CUR_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	2538;"	d
+GET_TU3_TM_INIT_VALUE	include/ssv6200_reg.h	1403;"	d
+GET_TU3_TM_INIT_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	2534;"	d
+GET_TU3_TM_INT_MASK	include/ssv6200_reg.h	1406;"	d
+GET_TU3_TM_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	2537;"	d
+GET_TU3_TM_INT_STS_DONE	include/ssv6200_reg.h	1405;"	d
+GET_TU3_TM_INT_STS_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	2536;"	d
+GET_TU3_TM_MODE	include/ssv6200_reg.h	1404;"	d
+GET_TU3_TM_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	2535;"	d
+GET_TURISMO_TRX_SAR_ADC_FSM_RDY	smac/hal/ssv6006c/ssv6006C_reg.h	5738;"	d
+GET_TWI_DELAY_ACK	smac/hal/ssv6006c/ssv6006C_reg.h	2803;"	d
+GET_TWI_DEV_A10B	smac/hal/ssv6006c/ssv6006C_reg.h	2797;"	d
+GET_TWI_DEV_A_10B	smac/hal/ssv6006c/ssv6006C_reg.h	2772;"	d
+GET_TWI_INT_HOLD_BUS	smac/hal/ssv6006c/ssv6006C_reg.h	2787;"	d
+GET_TWI_INT_HOLD_BUS_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2781;"	d
+GET_TWI_INT_HOLD_BUS_ST	smac/hal/ssv6006c/ssv6006C_reg.h	2793;"	d
+GET_TWI_INT_MISMATCH	smac/hal/ssv6006c/ssv6006C_reg.h	2785;"	d
+GET_TWI_INT_MISMATCH_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2779;"	d
+GET_TWI_INT_MISMATCH_ST	smac/hal/ssv6006c/ssv6006C_reg.h	2791;"	d
+GET_TWI_INT_RXD_STALL	smac/hal/ssv6006c/ssv6006C_reg.h	2783;"	d
+GET_TWI_INT_RXD_STALL_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2777;"	d
+GET_TWI_INT_RXD_STALL_ST	smac/hal/ssv6006c/ssv6006C_reg.h	2789;"	d
+GET_TWI_INT_TRANS_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	2786;"	d
+GET_TWI_INT_TRANS_FAIL_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2780;"	d
+GET_TWI_INT_TRANS_FAIL_ST	smac/hal/ssv6006c/ssv6006C_reg.h	2792;"	d
+GET_TWI_INT_TRANS_FINISH	smac/hal/ssv6006c/ssv6006C_reg.h	2784;"	d
+GET_TWI_INT_TRANS_FINISH_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2778;"	d
+GET_TWI_INT_TRANS_FINISH_ST	smac/hal/ssv6006c/ssv6006C_reg.h	2790;"	d
+GET_TWI_INT_TXD_STALL	smac/hal/ssv6006c/ssv6006C_reg.h	2782;"	d
+GET_TWI_INT_TXD_STALL_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2776;"	d
+GET_TWI_INT_TXD_STALL_ST	smac/hal/ssv6006c/ssv6006C_reg.h	2788;"	d
+GET_TWI_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	2773;"	d
+GET_TWI_PSCL	smac/hal/ssv6006c/ssv6006C_reg.h	2800;"	d
+GET_TWI_RX	smac/hal/ssv6006c/ssv6006C_reg.h	2796;"	d
+GET_TWI_RXD_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	2799;"	d
+GET_TWI_START_TRIG	smac/hal/ssv6006c/ssv6006C_reg.h	2769;"	d
+GET_TWI_STATUS_RECORD_0	smac/hal/ssv6006c/ssv6006C_reg.h	2794;"	d
+GET_TWI_STATUS_RECORD_1	smac/hal/ssv6006c/ssv6006C_reg.h	2795;"	d
+GET_TWI_STA_STO_PSCL	smac/hal/ssv6006c/ssv6006C_reg.h	2801;"	d
+GET_TWI_STOP_TRIG	smac/hal/ssv6006c/ssv6006C_reg.h	2770;"	d
+GET_TWI_TRANS_CONTINUE	smac/hal/ssv6006c/ssv6006C_reg.h	2771;"	d
+GET_TWI_TRANS_PSDA	smac/hal/ssv6006c/ssv6006C_reg.h	2802;"	d
+GET_TWI_TXD_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	2798;"	d
+GET_TXEMPTYFLAG	smac/hal/ssv6006c/ssv6006C_reg.h	2330;"	d
+GET_TXERRORFLAG	smac/hal/ssv6006c/ssv6006C_reg.h	2333;"	d
+GET_TXFIFO_RST	include/ssv6200_reg.h	2123;"	d
+GET_TXFIFO_RST	smac/hal/ssv6006c/ssv6006C_reg.h	2833;"	d
+GET_TXF_ID	include/ssv6200_reg.h	2493;"	d
+GET_TXF_ID	smac/hal/ssv6006c/ssv6006C_reg.h	3199;"	d
+GET_TXNOTFULLFLAG	smac/hal/ssv6006c/ssv6006C_reg.h	2329;"	d
+GET_TXQ0_MTX_Q_AIFSN	include/ssv6200_reg.h	2847;"	d
+GET_TXQ0_MTX_Q_AIFSN	smac/hal/ssv6006c/ssv6006C_reg.h	3639;"	d
+GET_TXQ0_MTX_Q_BKF_CNT	include/ssv6200_reg.h	2851;"	d
+GET_TXQ0_MTX_Q_BKF_CNT_FIX	smac/hal/ssv6006c/ssv6006C_reg.h	3643;"	d
+GET_TXQ0_MTX_Q_BKF_CNT_FIXED	include/ssv6200_reg.h	2842;"	d
+GET_TXQ0_MTX_Q_ECWMAX	include/ssv6200_reg.h	2849;"	d
+GET_TXQ0_MTX_Q_ECWMAX	smac/hal/ssv6006c/ssv6006C_reg.h	3641;"	d
+GET_TXQ0_MTX_Q_ECWMIN	include/ssv6200_reg.h	2848;"	d
+GET_TXQ0_MTX_Q_ECWMIN	smac/hal/ssv6006c/ssv6006C_reg.h	3640;"	d
+GET_TXQ0_MTX_Q_ID_MAP_L	include/ssv6200_reg.h	2854;"	d
+GET_TXQ0_MTX_Q_LRC_LIMIT	include/ssv6200_reg.h	2853;"	d
+GET_TXQ0_MTX_Q_MB_NO_RLS	include/ssv6200_reg.h	2844;"	d
+GET_TXQ0_MTX_Q_MB_NO_RLS	smac/hal/ssv6006c/ssv6006C_reg.h	3637;"	d
+GET_TXQ0_MTX_Q_PRE_LD	include/ssv6200_reg.h	2841;"	d
+GET_TXQ0_MTX_Q_RND_MODE	include/ssv6200_reg.h	2846;"	d
+GET_TXQ0_MTX_Q_RND_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	3636;"	d
+GET_TXQ0_MTX_Q_SRC_LIMIT	include/ssv6200_reg.h	2852;"	d
+GET_TXQ0_MTX_Q_TXOP_CH_THD	include/ssv6200_reg.h	2855;"	d
+GET_TXQ0_MTX_Q_TXOP_FRC_BUR	include/ssv6200_reg.h	2845;"	d
+GET_TXQ0_MTX_Q_TXOP_LIMIT	include/ssv6200_reg.h	2850;"	d
+GET_TXQ0_MTX_Q_TXOP_LIMIT	smac/hal/ssv6006c/ssv6006C_reg.h	3642;"	d
+GET_TXQ0_MTX_Q_TXOP_OV_THD	include/ssv6200_reg.h	2856;"	d
+GET_TXQ0_MTX_Q_TXOP_SUB_FRM_TIME	include/ssv6200_reg.h	2843;"	d
+GET_TXQ0_Q_NULLDATAFRAME_GEN_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3638;"	d
+GET_TXQ0_RO_AIFS_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	3647;"	d
+GET_TXQ0_RO_BKF_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	3648;"	d
+GET_TXQ0_RO_FSM_TXQ	smac/hal/ssv6006c/ssv6006C_reg.h	3644;"	d
+GET_TXQ0_RO_PKTID	smac/hal/ssv6006c/ssv6006C_reg.h	3649;"	d
+GET_TXQ0_RO_RATESET_IDX	smac/hal/ssv6006c/ssv6006C_reg.h	3646;"	d
+GET_TXQ0_RO_TRY_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	3645;"	d
+GET_TXQ1_MTX_Q_AIFSN	include/ssv6200_reg.h	2863;"	d
+GET_TXQ1_MTX_Q_AIFSN	smac/hal/ssv6006c/ssv6006C_reg.h	3653;"	d
+GET_TXQ1_MTX_Q_BKF_CNT	include/ssv6200_reg.h	2867;"	d
+GET_TXQ1_MTX_Q_BKF_CNT_FIX	smac/hal/ssv6006c/ssv6006C_reg.h	3657;"	d
+GET_TXQ1_MTX_Q_BKF_CNT_FIXED	include/ssv6200_reg.h	2858;"	d
+GET_TXQ1_MTX_Q_ECWMAX	include/ssv6200_reg.h	2865;"	d
+GET_TXQ1_MTX_Q_ECWMAX	smac/hal/ssv6006c/ssv6006C_reg.h	3655;"	d
+GET_TXQ1_MTX_Q_ECWMIN	include/ssv6200_reg.h	2864;"	d
+GET_TXQ1_MTX_Q_ECWMIN	smac/hal/ssv6006c/ssv6006C_reg.h	3654;"	d
+GET_TXQ1_MTX_Q_ID_MAP_L	include/ssv6200_reg.h	2870;"	d
+GET_TXQ1_MTX_Q_LRC_LIMIT	include/ssv6200_reg.h	2869;"	d
+GET_TXQ1_MTX_Q_MB_NO_RLS	include/ssv6200_reg.h	2860;"	d
+GET_TXQ1_MTX_Q_MB_NO_RLS	smac/hal/ssv6006c/ssv6006C_reg.h	3651;"	d
+GET_TXQ1_MTX_Q_PRE_LD	include/ssv6200_reg.h	2857;"	d
+GET_TXQ1_MTX_Q_RND_MODE	include/ssv6200_reg.h	2862;"	d
+GET_TXQ1_MTX_Q_RND_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	3650;"	d
+GET_TXQ1_MTX_Q_SRC_LIMIT	include/ssv6200_reg.h	2868;"	d
+GET_TXQ1_MTX_Q_TXOP_CH_THD	include/ssv6200_reg.h	2871;"	d
+GET_TXQ1_MTX_Q_TXOP_FRC_BUR	include/ssv6200_reg.h	2861;"	d
+GET_TXQ1_MTX_Q_TXOP_LIMIT	include/ssv6200_reg.h	2866;"	d
+GET_TXQ1_MTX_Q_TXOP_LIMIT	smac/hal/ssv6006c/ssv6006C_reg.h	3656;"	d
+GET_TXQ1_MTX_Q_TXOP_OV_THD	include/ssv6200_reg.h	2872;"	d
+GET_TXQ1_MTX_Q_TXOP_SUB_FRM_TIME	include/ssv6200_reg.h	2859;"	d
+GET_TXQ1_Q_NULLDATAFRAME_GEN_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3652;"	d
+GET_TXQ1_RO_AIFS_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	3661;"	d
+GET_TXQ1_RO_BKF_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	3662;"	d
+GET_TXQ1_RO_FSM_TXQ	smac/hal/ssv6006c/ssv6006C_reg.h	3658;"	d
+GET_TXQ1_RO_PKTID	smac/hal/ssv6006c/ssv6006C_reg.h	3663;"	d
+GET_TXQ1_RO_RATESET_IDX	smac/hal/ssv6006c/ssv6006C_reg.h	3660;"	d
+GET_TXQ1_RO_TRY_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	3659;"	d
+GET_TXQ2_MTX_Q_AIFSN	include/ssv6200_reg.h	2879;"	d
+GET_TXQ2_MTX_Q_AIFSN	smac/hal/ssv6006c/ssv6006C_reg.h	3667;"	d
+GET_TXQ2_MTX_Q_BKF_CNT	include/ssv6200_reg.h	2883;"	d
+GET_TXQ2_MTX_Q_BKF_CNT_FIX	smac/hal/ssv6006c/ssv6006C_reg.h	3671;"	d
+GET_TXQ2_MTX_Q_BKF_CNT_FIXED	include/ssv6200_reg.h	2874;"	d
+GET_TXQ2_MTX_Q_ECWMAX	include/ssv6200_reg.h	2881;"	d
+GET_TXQ2_MTX_Q_ECWMAX	smac/hal/ssv6006c/ssv6006C_reg.h	3669;"	d
+GET_TXQ2_MTX_Q_ECWMIN	include/ssv6200_reg.h	2880;"	d
+GET_TXQ2_MTX_Q_ECWMIN	smac/hal/ssv6006c/ssv6006C_reg.h	3668;"	d
+GET_TXQ2_MTX_Q_ID_MAP_L	include/ssv6200_reg.h	2886;"	d
+GET_TXQ2_MTX_Q_LRC_LIMIT	include/ssv6200_reg.h	2885;"	d
+GET_TXQ2_MTX_Q_MB_NO_RLS	include/ssv6200_reg.h	2876;"	d
+GET_TXQ2_MTX_Q_MB_NO_RLS	smac/hal/ssv6006c/ssv6006C_reg.h	3665;"	d
+GET_TXQ2_MTX_Q_PRE_LD	include/ssv6200_reg.h	2873;"	d
+GET_TXQ2_MTX_Q_RND_MODE	include/ssv6200_reg.h	2878;"	d
+GET_TXQ2_MTX_Q_RND_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	3664;"	d
+GET_TXQ2_MTX_Q_SRC_LIMIT	include/ssv6200_reg.h	2884;"	d
+GET_TXQ2_MTX_Q_TXOP_CH_THD	include/ssv6200_reg.h	2887;"	d
+GET_TXQ2_MTX_Q_TXOP_FRC_BUR	include/ssv6200_reg.h	2877;"	d
+GET_TXQ2_MTX_Q_TXOP_LIMIT	include/ssv6200_reg.h	2882;"	d
+GET_TXQ2_MTX_Q_TXOP_LIMIT	smac/hal/ssv6006c/ssv6006C_reg.h	3670;"	d
+GET_TXQ2_MTX_Q_TXOP_OV_THD	include/ssv6200_reg.h	2888;"	d
+GET_TXQ2_MTX_Q_TXOP_SUB_FRM_TIME	include/ssv6200_reg.h	2875;"	d
+GET_TXQ2_Q_NULLDATAFRAME_GEN_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3666;"	d
+GET_TXQ2_RO_AIFS_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	3675;"	d
+GET_TXQ2_RO_BKF_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	3676;"	d
+GET_TXQ2_RO_FSM_TXQ	smac/hal/ssv6006c/ssv6006C_reg.h	3672;"	d
+GET_TXQ2_RO_PKTID	smac/hal/ssv6006c/ssv6006C_reg.h	3677;"	d
+GET_TXQ2_RO_RATESET_IDX	smac/hal/ssv6006c/ssv6006C_reg.h	3674;"	d
+GET_TXQ2_RO_TRY_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	3673;"	d
+GET_TXQ3_MTX_Q_AIFSN	include/ssv6200_reg.h	2895;"	d
+GET_TXQ3_MTX_Q_AIFSN	smac/hal/ssv6006c/ssv6006C_reg.h	3681;"	d
+GET_TXQ3_MTX_Q_BKF_CNT	include/ssv6200_reg.h	2899;"	d
+GET_TXQ3_MTX_Q_BKF_CNT_FIX	smac/hal/ssv6006c/ssv6006C_reg.h	3685;"	d
+GET_TXQ3_MTX_Q_BKF_CNT_FIXED	include/ssv6200_reg.h	2890;"	d
+GET_TXQ3_MTX_Q_ECWMAX	include/ssv6200_reg.h	2897;"	d
+GET_TXQ3_MTX_Q_ECWMAX	smac/hal/ssv6006c/ssv6006C_reg.h	3683;"	d
+GET_TXQ3_MTX_Q_ECWMIN	include/ssv6200_reg.h	2896;"	d
+GET_TXQ3_MTX_Q_ECWMIN	smac/hal/ssv6006c/ssv6006C_reg.h	3682;"	d
+GET_TXQ3_MTX_Q_ID_MAP_L	include/ssv6200_reg.h	2902;"	d
+GET_TXQ3_MTX_Q_LRC_LIMIT	include/ssv6200_reg.h	2901;"	d
+GET_TXQ3_MTX_Q_MB_NO_RLS	include/ssv6200_reg.h	2892;"	d
+GET_TXQ3_MTX_Q_MB_NO_RLS	smac/hal/ssv6006c/ssv6006C_reg.h	3679;"	d
+GET_TXQ3_MTX_Q_PRE_LD	include/ssv6200_reg.h	2889;"	d
+GET_TXQ3_MTX_Q_RND_MODE	include/ssv6200_reg.h	2894;"	d
+GET_TXQ3_MTX_Q_RND_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	3678;"	d
+GET_TXQ3_MTX_Q_SRC_LIMIT	include/ssv6200_reg.h	2900;"	d
+GET_TXQ3_MTX_Q_TXOP_CH_THD	include/ssv6200_reg.h	2903;"	d
+GET_TXQ3_MTX_Q_TXOP_FRC_BUR	include/ssv6200_reg.h	2893;"	d
+GET_TXQ3_MTX_Q_TXOP_LIMIT	include/ssv6200_reg.h	2898;"	d
+GET_TXQ3_MTX_Q_TXOP_LIMIT	smac/hal/ssv6006c/ssv6006C_reg.h	3684;"	d
+GET_TXQ3_MTX_Q_TXOP_OV_THD	include/ssv6200_reg.h	2904;"	d
+GET_TXQ3_MTX_Q_TXOP_SUB_FRM_TIME	include/ssv6200_reg.h	2891;"	d
+GET_TXQ3_Q_NULLDATAFRAME_GEN_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3680;"	d
+GET_TXQ3_RO_AIFS_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	3689;"	d
+GET_TXQ3_RO_BKF_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	3690;"	d
+GET_TXQ3_RO_FSM_TXQ	smac/hal/ssv6006c/ssv6006C_reg.h	3686;"	d
+GET_TXQ3_RO_PKTID	smac/hal/ssv6006c/ssv6006C_reg.h	3691;"	d
+GET_TXQ3_RO_RATESET_IDX	smac/hal/ssv6006c/ssv6006C_reg.h	3688;"	d
+GET_TXQ3_RO_TRY_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	3687;"	d
+GET_TXQ4_MTX_Q_AIFSN	include/ssv6200_reg.h	2911;"	d
+GET_TXQ4_MTX_Q_AIFSN	smac/hal/ssv6006c/ssv6006C_reg.h	3695;"	d
+GET_TXQ4_MTX_Q_BKF_CNT	include/ssv6200_reg.h	2915;"	d
+GET_TXQ4_MTX_Q_BKF_CNT_FIX	smac/hal/ssv6006c/ssv6006C_reg.h	3699;"	d
+GET_TXQ4_MTX_Q_BKF_CNT_FIXED	include/ssv6200_reg.h	2906;"	d
+GET_TXQ4_MTX_Q_ECWMAX	include/ssv6200_reg.h	2913;"	d
+GET_TXQ4_MTX_Q_ECWMAX	smac/hal/ssv6006c/ssv6006C_reg.h	3697;"	d
+GET_TXQ4_MTX_Q_ECWMIN	include/ssv6200_reg.h	2912;"	d
+GET_TXQ4_MTX_Q_ECWMIN	smac/hal/ssv6006c/ssv6006C_reg.h	3696;"	d
+GET_TXQ4_MTX_Q_ID_MAP_L	include/ssv6200_reg.h	2918;"	d
+GET_TXQ4_MTX_Q_LRC_LIMIT	include/ssv6200_reg.h	2917;"	d
+GET_TXQ4_MTX_Q_MB_NO_RLS	include/ssv6200_reg.h	2908;"	d
+GET_TXQ4_MTX_Q_MB_NO_RLS	smac/hal/ssv6006c/ssv6006C_reg.h	3693;"	d
+GET_TXQ4_MTX_Q_PRE_LD	include/ssv6200_reg.h	2905;"	d
+GET_TXQ4_MTX_Q_RND_MODE	include/ssv6200_reg.h	2910;"	d
+GET_TXQ4_MTX_Q_RND_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	3692;"	d
+GET_TXQ4_MTX_Q_SRC_LIMIT	include/ssv6200_reg.h	2916;"	d
+GET_TXQ4_MTX_Q_TXOP_CH_THD	include/ssv6200_reg.h	2919;"	d
+GET_TXQ4_MTX_Q_TXOP_FRC_BUR	include/ssv6200_reg.h	2909;"	d
+GET_TXQ4_MTX_Q_TXOP_LIMIT	include/ssv6200_reg.h	2914;"	d
+GET_TXQ4_MTX_Q_TXOP_LIMIT	smac/hal/ssv6006c/ssv6006C_reg.h	3698;"	d
+GET_TXQ4_MTX_Q_TXOP_OV_THD	include/ssv6200_reg.h	2920;"	d
+GET_TXQ4_MTX_Q_TXOP_SUB_FRM_TIME	include/ssv6200_reg.h	2907;"	d
+GET_TXQ4_Q_NULLDATAFRAME_GEN_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3694;"	d
+GET_TXQ4_RO_AIFS_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	3703;"	d
+GET_TXQ4_RO_BKF_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	3704;"	d
+GET_TXQ4_RO_FSM_TXQ	smac/hal/ssv6006c/ssv6006C_reg.h	3700;"	d
+GET_TXQ4_RO_PKTID	smac/hal/ssv6006c/ssv6006C_reg.h	3705;"	d
+GET_TXQ4_RO_RATESET_IDX	smac/hal/ssv6006c/ssv6006C_reg.h	3702;"	d
+GET_TXQ4_RO_TRY_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	3701;"	d
+GET_TXQ5_DTIM_BEACON_BURST_MNG	smac/hal/ssv6006c/ssv6006C_reg.h	3597;"	d
+GET_TXQ5_MTX_Q_AIFSN	smac/hal/ssv6006c/ssv6006C_reg.h	3709;"	d
+GET_TXQ5_MTX_Q_BKF_CNT_FIX	smac/hal/ssv6006c/ssv6006C_reg.h	3713;"	d
+GET_TXQ5_MTX_Q_ECWMAX	smac/hal/ssv6006c/ssv6006C_reg.h	3711;"	d
+GET_TXQ5_MTX_Q_ECWMIN	smac/hal/ssv6006c/ssv6006C_reg.h	3710;"	d
+GET_TXQ5_MTX_Q_MB_NO_RLS	smac/hal/ssv6006c/ssv6006C_reg.h	3707;"	d
+GET_TXQ5_MTX_Q_RND_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	3706;"	d
+GET_TXQ5_MTX_Q_TXOP_LIMIT	smac/hal/ssv6006c/ssv6006C_reg.h	3712;"	d
+GET_TXQ5_Q_NULLDATAFRAME_GEN_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3708;"	d
+GET_TXQ5_RO_AIFS_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	3717;"	d
+GET_TXQ5_RO_BKF_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	3718;"	d
+GET_TXQ5_RO_FSM_TXQ	smac/hal/ssv6006c/ssv6006C_reg.h	3714;"	d
+GET_TXQ5_RO_PKTID	smac/hal/ssv6006c/ssv6006C_reg.h	3719;"	d
+GET_TXQ5_RO_RATESET_IDX	smac/hal/ssv6006c/ssv6006C_reg.h	3716;"	d
+GET_TXQ5_RO_TRY_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	3715;"	d
+GET_TXQ_ID0	include/ssv6200_reg.h	2480;"	d
+GET_TXQ_ID0	smac/hal/ssv6006c/ssv6006C_reg.h	3179;"	d
+GET_TXQ_ID1	include/ssv6200_reg.h	2481;"	d
+GET_TXQ_ID1	smac/hal/ssv6006c/ssv6006C_reg.h	3180;"	d
+GET_TXSIFS_SUB_MAX	smac/hal/ssv6006c/ssv6006C_reg.h	3610;"	d
+GET_TXSIFS_SUB_MIN	smac/hal/ssv6006c/ssv6006C_reg.h	3609;"	d
+GET_TXTRAP_ETHTYPE0	include/ssv6200_reg.h	2502;"	d
+GET_TXTRAP_ETHTYPE0	smac/hal/ssv6006c/ssv6006C_reg.h	3218;"	d
+GET_TXTRAP_ETHTYPE1	include/ssv6200_reg.h	2501;"	d
+GET_TXTRAP_ETHTYPE1	smac/hal/ssv6006c/ssv6006C_reg.h	3217;"	d
+GET_TX_ACK_POLICY_0_0	include/ssv6200_reg.h	2927;"	d
+GET_TX_ACK_POLICY_0_0	smac/hal/ssv6006c/ssv6006C_reg.h	3806;"	d
+GET_TX_ACK_POLICY_0_1	include/ssv6200_reg.h	2929;"	d
+GET_TX_ACK_POLICY_0_1	smac/hal/ssv6006c/ssv6006C_reg.h	3808;"	d
+GET_TX_ACK_POLICY_0_2	include/ssv6200_reg.h	2931;"	d
+GET_TX_ACK_POLICY_0_2	smac/hal/ssv6006c/ssv6006C_reg.h	3810;"	d
+GET_TX_ACK_POLICY_0_3	include/ssv6200_reg.h	2933;"	d
+GET_TX_ACK_POLICY_0_3	smac/hal/ssv6006c/ssv6006C_reg.h	3812;"	d
+GET_TX_ACK_POLICY_0_4	include/ssv6200_reg.h	2935;"	d
+GET_TX_ACK_POLICY_0_4	smac/hal/ssv6006c/ssv6006C_reg.h	3814;"	d
+GET_TX_ACK_POLICY_0_5	include/ssv6200_reg.h	2937;"	d
+GET_TX_ACK_POLICY_0_5	smac/hal/ssv6006c/ssv6006C_reg.h	3816;"	d
+GET_TX_ACK_POLICY_0_6	include/ssv6200_reg.h	2939;"	d
+GET_TX_ACK_POLICY_0_6	smac/hal/ssv6006c/ssv6006C_reg.h	3818;"	d
+GET_TX_ACK_POLICY_0_7	include/ssv6200_reg.h	2941;"	d
+GET_TX_ACK_POLICY_0_7	smac/hal/ssv6006c/ssv6006C_reg.h	3820;"	d
+GET_TX_ACK_POLICY_1_0	include/ssv6200_reg.h	2949;"	d
+GET_TX_ACK_POLICY_1_0	smac/hal/ssv6006c/ssv6006C_reg.h	3828;"	d
+GET_TX_ACK_POLICY_1_1	include/ssv6200_reg.h	2951;"	d
+GET_TX_ACK_POLICY_1_1	smac/hal/ssv6006c/ssv6006C_reg.h	3830;"	d
+GET_TX_ACK_POLICY_1_2	include/ssv6200_reg.h	2953;"	d
+GET_TX_ACK_POLICY_1_2	smac/hal/ssv6006c/ssv6006C_reg.h	3832;"	d
+GET_TX_ACK_POLICY_1_3	include/ssv6200_reg.h	2955;"	d
+GET_TX_ACK_POLICY_1_3	smac/hal/ssv6006c/ssv6006C_reg.h	3834;"	d
+GET_TX_ACK_POLICY_1_4	include/ssv6200_reg.h	2957;"	d
+GET_TX_ACK_POLICY_1_4	smac/hal/ssv6006c/ssv6006C_reg.h	3836;"	d
+GET_TX_ACK_POLICY_1_5	include/ssv6200_reg.h	2959;"	d
+GET_TX_ACK_POLICY_1_5	smac/hal/ssv6006c/ssv6006C_reg.h	3838;"	d
+GET_TX_ACK_POLICY_1_6	include/ssv6200_reg.h	2961;"	d
+GET_TX_ACK_POLICY_1_6	smac/hal/ssv6006c/ssv6006C_reg.h	3840;"	d
+GET_TX_ACK_POLICY_1_7	include/ssv6200_reg.h	2963;"	d
+GET_TX_ACK_POLICY_1_7	smac/hal/ssv6006c/ssv6006C_reg.h	3842;"	d
+GET_TX_ACK_POLICY_2_0	smac/hal/ssv6006c/ssv6006C_reg.h	4061;"	d
+GET_TX_ACK_POLICY_2_1	smac/hal/ssv6006c/ssv6006C_reg.h	4063;"	d
+GET_TX_ACK_POLICY_2_2	smac/hal/ssv6006c/ssv6006C_reg.h	4065;"	d
+GET_TX_ACK_POLICY_2_3	smac/hal/ssv6006c/ssv6006C_reg.h	4067;"	d
+GET_TX_ACK_POLICY_2_4	smac/hal/ssv6006c/ssv6006C_reg.h	4069;"	d
+GET_TX_ACK_POLICY_2_5	smac/hal/ssv6006c/ssv6006C_reg.h	4071;"	d
+GET_TX_ACK_POLICY_2_6	smac/hal/ssv6006c/ssv6006C_reg.h	4073;"	d
+GET_TX_ACK_POLICY_2_7	smac/hal/ssv6006c/ssv6006C_reg.h	4075;"	d
+GET_TX_ACK_POLICY_3_0	smac/hal/ssv6006c/ssv6006C_reg.h	4083;"	d
+GET_TX_ACK_POLICY_3_1	smac/hal/ssv6006c/ssv6006C_reg.h	4085;"	d
+GET_TX_ACK_POLICY_3_2	smac/hal/ssv6006c/ssv6006C_reg.h	4087;"	d
+GET_TX_ACK_POLICY_3_3	smac/hal/ssv6006c/ssv6006C_reg.h	4089;"	d
+GET_TX_ACK_POLICY_3_4	smac/hal/ssv6006c/ssv6006C_reg.h	4091;"	d
+GET_TX_ACK_POLICY_3_5	smac/hal/ssv6006c/ssv6006C_reg.h	4093;"	d
+GET_TX_ACK_POLICY_3_6	smac/hal/ssv6006c/ssv6006C_reg.h	4095;"	d
+GET_TX_ACK_POLICY_3_7	smac/hal/ssv6006c/ssv6006C_reg.h	4097;"	d
+GET_TX_ACK_POLICY_4_0	smac/hal/ssv6006c/ssv6006C_reg.h	4105;"	d
+GET_TX_ACK_POLICY_4_1	smac/hal/ssv6006c/ssv6006C_reg.h	4107;"	d
+GET_TX_ACK_POLICY_4_2	smac/hal/ssv6006c/ssv6006C_reg.h	4109;"	d
+GET_TX_ACK_POLICY_4_3	smac/hal/ssv6006c/ssv6006C_reg.h	4111;"	d
+GET_TX_ACK_POLICY_4_4	smac/hal/ssv6006c/ssv6006C_reg.h	4113;"	d
+GET_TX_ACK_POLICY_4_5	smac/hal/ssv6006c/ssv6006C_reg.h	4115;"	d
+GET_TX_ACK_POLICY_4_6	smac/hal/ssv6006c/ssv6006C_reg.h	4117;"	d
+GET_TX_ACK_POLICY_4_7	smac/hal/ssv6006c/ssv6006C_reg.h	4119;"	d
+GET_TX_ACK_POLICY_5_0	smac/hal/ssv6006c/ssv6006C_reg.h	4127;"	d
+GET_TX_ACK_POLICY_5_1	smac/hal/ssv6006c/ssv6006C_reg.h	4129;"	d
+GET_TX_ACK_POLICY_5_2	smac/hal/ssv6006c/ssv6006C_reg.h	4131;"	d
+GET_TX_ACK_POLICY_5_3	smac/hal/ssv6006c/ssv6006C_reg.h	4133;"	d
+GET_TX_ACK_POLICY_5_4	smac/hal/ssv6006c/ssv6006C_reg.h	4135;"	d
+GET_TX_ACK_POLICY_5_5	smac/hal/ssv6006c/ssv6006C_reg.h	4137;"	d
+GET_TX_ACK_POLICY_5_6	smac/hal/ssv6006c/ssv6006C_reg.h	4139;"	d
+GET_TX_ACK_POLICY_5_7	smac/hal/ssv6006c/ssv6006C_reg.h	4141;"	d
+GET_TX_ACK_POLICY_6_0	smac/hal/ssv6006c/ssv6006C_reg.h	4149;"	d
+GET_TX_ACK_POLICY_6_1	smac/hal/ssv6006c/ssv6006C_reg.h	4151;"	d
+GET_TX_ACK_POLICY_6_2	smac/hal/ssv6006c/ssv6006C_reg.h	4153;"	d
+GET_TX_ACK_POLICY_6_3	smac/hal/ssv6006c/ssv6006C_reg.h	4155;"	d
+GET_TX_ACK_POLICY_6_4	smac/hal/ssv6006c/ssv6006C_reg.h	4157;"	d
+GET_TX_ACK_POLICY_6_5	smac/hal/ssv6006c/ssv6006C_reg.h	4159;"	d
+GET_TX_ACK_POLICY_6_6	smac/hal/ssv6006c/ssv6006C_reg.h	4161;"	d
+GET_TX_ACK_POLICY_6_7	smac/hal/ssv6006c/ssv6006C_reg.h	4163;"	d
+GET_TX_ACK_POLICY_7_0	smac/hal/ssv6006c/ssv6006C_reg.h	4171;"	d
+GET_TX_ACK_POLICY_7_1	smac/hal/ssv6006c/ssv6006C_reg.h	4173;"	d
+GET_TX_ACK_POLICY_7_2	smac/hal/ssv6006c/ssv6006C_reg.h	4175;"	d
+GET_TX_ACK_POLICY_7_3	smac/hal/ssv6006c/ssv6006C_reg.h	4177;"	d
+GET_TX_ACK_POLICY_7_4	smac/hal/ssv6006c/ssv6006C_reg.h	4179;"	d
+GET_TX_ACK_POLICY_7_5	smac/hal/ssv6006c/ssv6006C_reg.h	4181;"	d
+GET_TX_ACK_POLICY_7_6	smac/hal/ssv6006c/ssv6006C_reg.h	4183;"	d
+GET_TX_ACK_POLICY_7_7	smac/hal/ssv6006c/ssv6006C_reg.h	4185;"	d
+GET_TX_CCA_DUR	include/ssv6200_reg.h	2819;"	d
+GET_TX_COMPLETE_INT	include/ssv6200_reg.h	1879;"	d
+GET_TX_COUNT_LIMIT	include/ssv6200_reg.h	3824;"	d
+GET_TX_COUNT_LIMIT	smac/hal/ssv6006c/ssv6006C_reg.h	9007;"	d
+GET_TX_DISCARD_CNT	include/ssv6200_reg.h	2077;"	d
+GET_TX_DISCARD_CNT_CLR	include/ssv6200_reg.h	2079;"	d
+GET_TX_DONE	include/ssv6200_reg.h	1907;"	d
+GET_TX_DONE_CNT	include/ssv6200_reg.h	2076;"	d
+GET_TX_DONE_CNT_CLR	include/ssv6200_reg.h	2080;"	d
+GET_TX_DONE_STATUS	include/ssv6200_reg.h	1964;"	d
+GET_TX_EMPTY	include/ssv6200_reg.h	2146;"	d
+GET_TX_EMPTY	smac/hal/ssv6006c/ssv6006C_reg.h	2857;"	d
+GET_TX_EMPTY2	smac/hal/ssv6006c/ssv6006C_reg.h	2880;"	d
+GET_TX_ERR_FIRST_4B_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3197;"	d
+GET_TX_ERR_RECOVER	smac/hal/ssv6006c/ssv6006C_reg.h	3196;"	d
+GET_TX_ETHER_TRAP_EN	include/ssv6200_reg.h	2482;"	d
+GET_TX_ETHER_TRAP_EN	smac/hal/ssv6006c/ssv6006C_reg.h	3181;"	d
+GET_TX_FIFO_FAIL	include/ssv6200_reg.h	2059;"	d
+GET_TX_FIFO_RESIDUE	include/ssv6200_reg.h	2083;"	d
+GET_TX_FLOW_CTRL	include/ssv6200_reg.h	2489;"	d
+GET_TX_FLOW_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	3189;"	d
+GET_TX_FLOW_DATA	include/ssv6200_reg.h	2491;"	d
+GET_TX_FLOW_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	3191;"	d
+GET_TX_FLOW_MGMT	include/ssv6200_reg.h	2490;"	d
+GET_TX_FLOW_MGMT	smac/hal/ssv6006c/ssv6006C_reg.h	3190;"	d
+GET_TX_H	smac/hal/ssv6006c/ssv6006C_reg.h	2879;"	d
+GET_TX_HOST_FAIL	include/ssv6200_reg.h	2060;"	d
+GET_TX_IDLE	smac/hal/ssv6006c/ssv6006C_reg.h	2872;"	d
+GET_TX_ID_ALC_LEN	include/ssv6200_reg.h	3813;"	d
+GET_TX_ID_ALC_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	8996;"	d
+GET_TX_ID_COUNT	include/ssv6200_reg.h	3789;"	d
+GET_TX_ID_COUNT	smac/hal/ssv6006c/ssv6006C_reg.h	8972;"	d
+GET_TX_ID_IFO_LEN	include/ssv6200_reg.h	3850;"	d
+GET_TX_ID_IFO_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	9035;"	d
+GET_TX_ID_LEN_THOLD	include/ssv6200_reg.h	2267;"	d
+GET_TX_ID_LEN_THOLD_INT	include/ssv6200_reg.h	3807;"	d
+GET_TX_ID_LEN_THOLD_INT	smac/hal/ssv6006c/ssv6006C_reg.h	8990;"	d
+GET_TX_ID_LEN_THOLD_SD	include/ssv6200_reg.h	2336;"	d
+GET_TX_ID_REMAIN	include/ssv6200_reg.h	3820;"	d
+GET_TX_ID_REMAIN	smac/hal/ssv6006c/ssv6006C_reg.h	9003;"	d
+GET_TX_ID_REMAIN2	include/ssv6200_reg.h	1990;"	d
+GET_TX_ID_REMAIN3	include/ssv6200_reg.h	1978;"	d
+GET_TX_ID_TB0	include/ssv6200_reg.h	3798;"	d
+GET_TX_ID_TB0	smac/hal/ssv6006c/ssv6006C_reg.h	8981;"	d
+GET_TX_ID_TB1	include/ssv6200_reg.h	3799;"	d
+GET_TX_ID_TB1	smac/hal/ssv6006c/ssv6006C_reg.h	8982;"	d
+GET_TX_ID_TB2	include/ssv6200_reg.h	3835;"	d
+GET_TX_ID_TB2	smac/hal/ssv6006c/ssv6006C_reg.h	9018;"	d
+GET_TX_ID_TB3	include/ssv6200_reg.h	3836;"	d
+GET_TX_ID_TB3	smac/hal/ssv6006c/ssv6006C_reg.h	9019;"	d
+GET_TX_ID_THOLD	include/ssv6200_reg.h	3791;"	d
+GET_TX_ID_THOLD	smac/hal/ssv6006c/ssv6006C_reg.h	8974;"	d
+GET_TX_ID_USE2	include/ssv6200_reg.h	3840;"	d
+GET_TX_ID_USE2	smac/hal/ssv6006c/ssv6006C_reg.h	9023;"	d
+GET_TX_ID_USE3	include/ssv6200_reg.h	3843;"	d
+GET_TX_ID_USE3	smac/hal/ssv6006c/ssv6006C_reg.h	9027;"	d
+GET_TX_ID_USE4	include/ssv6200_reg.h	3847;"	d
+GET_TX_ID_USE4	smac/hal/ssv6006c/ssv6006C_reg.h	9032;"	d
+GET_TX_ID_USE_5_0	include/ssv6200_reg.h	3828;"	d
+GET_TX_ID_USE_5_0	smac/hal/ssv6006c/ssv6006C_reg.h	9011;"	d
+GET_TX_INFO_CLEAR_ENABLE	include/ssv6200_reg.h	2500;"	d
+GET_TX_INFO_CLEAR_ENABLE	smac/hal/ssv6006c/ssv6006C_reg.h	3208;"	d
+GET_TX_INFO_CLEAR_SIZE	include/ssv6200_reg.h	2499;"	d
+GET_TX_INFO_CLEAR_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	3207;"	d
+GET_TX_INFO_SIZE	include/ssv6200_reg.h	2496;"	d
+GET_TX_INFO_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	3204;"	d
+GET_TX_INT_CH	include/ssv6200_reg.h	3796;"	d
+GET_TX_INT_CH	smac/hal/ssv6006c/ssv6006C_reg.h	8979;"	d
+GET_TX_IP_FALL_OFFSET_STEP	smac/hal/ssv6006c/ssv6006C_reg.h	3614;"	d
+GET_TX_L	smac/hal/ssv6006c/ssv6006C_reg.h	2878;"	d
+GET_TX_LIMIT_INT	include/ssv6200_reg.h	3825;"	d
+GET_TX_LIMIT_INT	smac/hal/ssv6006c/ssv6006C_reg.h	9008;"	d
+GET_TX_LIMIT_INT_EN	include/ssv6200_reg.h	3826;"	d
+GET_TX_LIMIT_INT_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9009;"	d
+GET_TX_LIMIT_INT_IN	include/ssv6200_reg.h	2091;"	d
+GET_TX_LIMIT_INT_MASK	include/ssv6200_reg.h	1877;"	d
+GET_TX_LIMIT_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	2660;"	d
+GET_TX_LIMIT_INT_STS	include/ssv6200_reg.h	1885;"	d
+GET_TX_LIMIT_INT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	2668;"	d
+GET_TX_MOUNT	include/ssv6200_reg.h	4857;"	d
+GET_TX_ON_DEMAND_ENA	include/ssv6200_reg.h	2473;"	d
+GET_TX_ON_DEMAND_ENA	smac/hal/ssv6006c/ssv6006C_reg.h	3172;"	d
+GET_TX_ON_DEMAND_LENGTH	include/ssv6200_reg.h	2517;"	d
+GET_TX_ON_DEMAND_LENGTH	smac/hal/ssv6006c/ssv6006C_reg.h	3240;"	d
+GET_TX_PAGE_LIMIT	include/ssv6200_reg.h	3823;"	d
+GET_TX_PAGE_LIMIT	smac/hal/ssv6006c/ssv6006C_reg.h	9006;"	d
+GET_TX_PAGE_REMAIN	include/ssv6200_reg.h	3821;"	d
+GET_TX_PAGE_REMAIN	smac/hal/ssv6006c/ssv6006C_reg.h	9004;"	d
+GET_TX_PAGE_REMAIN2	include/ssv6200_reg.h	1977;"	d
+GET_TX_PAGE_REMAIN3	include/ssv6200_reg.h	1991;"	d
+GET_TX_PAGE_USE2	include/ssv6200_reg.h	3839;"	d
+GET_TX_PAGE_USE2	smac/hal/ssv6006c/ssv6006C_reg.h	9022;"	d
+GET_TX_PAGE_USE3	include/ssv6200_reg.h	3842;"	d
+GET_TX_PAGE_USE3	smac/hal/ssv6006c/ssv6006C_reg.h	9026;"	d
+GET_TX_PAGE_USE4	include/ssv6200_reg.h	3846;"	d
+GET_TX_PAGE_USE4	smac/hal/ssv6006c/ssv6006C_reg.h	9031;"	d
+GET_TX_PAGE_USE_7_0	include/ssv6200_reg.h	3827;"	d
+GET_TX_PAGE_USE_7_0	smac/hal/ssv6006c/ssv6006C_reg.h	9010;"	d
+GET_TX_PBOFFSET	include/ssv6200_reg.h	2495;"	d
+GET_TX_PBOFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	3203;"	d
+GET_TX_PKT_COUNTER	include/ssv6200_reg.h	2505;"	d
+GET_TX_PKT_COUNTER	smac/hal/ssv6006c/ssv6006C_reg.h	3250;"	d
+GET_TX_PKT_DROP_COUNTER	include/ssv6200_reg.h	2509;"	d
+GET_TX_PKT_DROP_COUNTER	smac/hal/ssv6006c/ssv6006C_reg.h	3246;"	d
+GET_TX_PKT_RSVD	include/ssv6200_reg.h	3093;"	d
+GET_TX_PKT_RSVD	smac/hal/ssv6006c/ssv6006C_reg.h	3925;"	d
+GET_TX_PKT_SEND_ID	smac/hal/ssv6006c/ssv6006C_reg.h	3223;"	d
+GET_TX_PKT_SEND_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	3221;"	d
+GET_TX_PKT_SEND_TO_RX	smac/hal/ssv6006c/ssv6006C_reg.h	3254;"	d
+GET_TX_PKT_TRAP_COUNTER	include/ssv6200_reg.h	2511;"	d
+GET_TX_PKT_TRAP_COUNTER	smac/hal/ssv6006c/ssv6006C_reg.h	3244;"	d
+GET_TX_RX_LOOP_BACK_TEST	include/ssv6200_reg.h	1899;"	d
+GET_TX_RX_TRAP_HW_ID_SELECT_ENABLE	smac/hal/ssv6006c/ssv6006C_reg.h	3257;"	d
+GET_TX_SCALE_11B	include/ssv6200_reg.h	4470;"	d
+GET_TX_SCALE_11B_P0D5	include/ssv6200_reg.h	4471;"	d
+GET_TX_SCALE_11G	include/ssv6200_reg.h	4472;"	d
+GET_TX_SCALE_11G_P0D5	include/ssv6200_reg.h	4473;"	d
+GET_TX_SDIO_PKT_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	3222;"	d
+GET_TX_SEG	include/ssv6200_reg.h	2051;"	d
+GET_TX_SEG	smac/hal/ssv6006c/ssv6006C_reg.h	2764;"	d
+GET_TX_SEQ_CTRL_0_0	include/ssv6200_reg.h	2928;"	d
+GET_TX_SEQ_CTRL_0_0	smac/hal/ssv6006c/ssv6006C_reg.h	3807;"	d
+GET_TX_SEQ_CTRL_0_1	include/ssv6200_reg.h	2930;"	d
+GET_TX_SEQ_CTRL_0_1	smac/hal/ssv6006c/ssv6006C_reg.h	3809;"	d
+GET_TX_SEQ_CTRL_0_2	include/ssv6200_reg.h	2932;"	d
+GET_TX_SEQ_CTRL_0_2	smac/hal/ssv6006c/ssv6006C_reg.h	3811;"	d
+GET_TX_SEQ_CTRL_0_3	include/ssv6200_reg.h	2934;"	d
+GET_TX_SEQ_CTRL_0_3	smac/hal/ssv6006c/ssv6006C_reg.h	3813;"	d
+GET_TX_SEQ_CTRL_0_4	include/ssv6200_reg.h	2936;"	d
+GET_TX_SEQ_CTRL_0_4	smac/hal/ssv6006c/ssv6006C_reg.h	3815;"	d
+GET_TX_SEQ_CTRL_0_5	include/ssv6200_reg.h	2938;"	d
+GET_TX_SEQ_CTRL_0_5	smac/hal/ssv6006c/ssv6006C_reg.h	3817;"	d
+GET_TX_SEQ_CTRL_0_6	include/ssv6200_reg.h	2940;"	d
+GET_TX_SEQ_CTRL_0_6	smac/hal/ssv6006c/ssv6006C_reg.h	3819;"	d
+GET_TX_SEQ_CTRL_0_7	include/ssv6200_reg.h	2942;"	d
+GET_TX_SEQ_CTRL_0_7	smac/hal/ssv6006c/ssv6006C_reg.h	3821;"	d
+GET_TX_SEQ_CTRL_1_0	include/ssv6200_reg.h	2950;"	d
+GET_TX_SEQ_CTRL_1_0	smac/hal/ssv6006c/ssv6006C_reg.h	3829;"	d
+GET_TX_SEQ_CTRL_1_1	include/ssv6200_reg.h	2952;"	d
+GET_TX_SEQ_CTRL_1_1	smac/hal/ssv6006c/ssv6006C_reg.h	3831;"	d
+GET_TX_SEQ_CTRL_1_2	include/ssv6200_reg.h	2954;"	d
+GET_TX_SEQ_CTRL_1_2	smac/hal/ssv6006c/ssv6006C_reg.h	3833;"	d
+GET_TX_SEQ_CTRL_1_3	include/ssv6200_reg.h	2956;"	d
+GET_TX_SEQ_CTRL_1_3	smac/hal/ssv6006c/ssv6006C_reg.h	3835;"	d
+GET_TX_SEQ_CTRL_1_4	include/ssv6200_reg.h	2958;"	d
+GET_TX_SEQ_CTRL_1_4	smac/hal/ssv6006c/ssv6006C_reg.h	3837;"	d
+GET_TX_SEQ_CTRL_1_5	include/ssv6200_reg.h	2960;"	d
+GET_TX_SEQ_CTRL_1_5	smac/hal/ssv6006c/ssv6006C_reg.h	3839;"	d
+GET_TX_SEQ_CTRL_1_6	include/ssv6200_reg.h	2962;"	d
+GET_TX_SEQ_CTRL_1_6	smac/hal/ssv6006c/ssv6006C_reg.h	3841;"	d
+GET_TX_SEQ_CTRL_1_7	include/ssv6200_reg.h	2964;"	d
+GET_TX_SEQ_CTRL_1_7	smac/hal/ssv6006c/ssv6006C_reg.h	3843;"	d
+GET_TX_SEQ_CTRL_2_0	smac/hal/ssv6006c/ssv6006C_reg.h	4062;"	d
+GET_TX_SEQ_CTRL_2_1	smac/hal/ssv6006c/ssv6006C_reg.h	4064;"	d
+GET_TX_SEQ_CTRL_2_2	smac/hal/ssv6006c/ssv6006C_reg.h	4066;"	d
+GET_TX_SEQ_CTRL_2_3	smac/hal/ssv6006c/ssv6006C_reg.h	4068;"	d
+GET_TX_SEQ_CTRL_2_4	smac/hal/ssv6006c/ssv6006C_reg.h	4070;"	d
+GET_TX_SEQ_CTRL_2_5	smac/hal/ssv6006c/ssv6006C_reg.h	4072;"	d
+GET_TX_SEQ_CTRL_2_6	smac/hal/ssv6006c/ssv6006C_reg.h	4074;"	d
+GET_TX_SEQ_CTRL_2_7	smac/hal/ssv6006c/ssv6006C_reg.h	4076;"	d
+GET_TX_SEQ_CTRL_3_0	smac/hal/ssv6006c/ssv6006C_reg.h	4084;"	d
+GET_TX_SEQ_CTRL_3_1	smac/hal/ssv6006c/ssv6006C_reg.h	4086;"	d
+GET_TX_SEQ_CTRL_3_2	smac/hal/ssv6006c/ssv6006C_reg.h	4088;"	d
+GET_TX_SEQ_CTRL_3_3	smac/hal/ssv6006c/ssv6006C_reg.h	4090;"	d
+GET_TX_SEQ_CTRL_3_4	smac/hal/ssv6006c/ssv6006C_reg.h	4092;"	d
+GET_TX_SEQ_CTRL_3_5	smac/hal/ssv6006c/ssv6006C_reg.h	4094;"	d
+GET_TX_SEQ_CTRL_3_6	smac/hal/ssv6006c/ssv6006C_reg.h	4096;"	d
+GET_TX_SEQ_CTRL_3_7	smac/hal/ssv6006c/ssv6006C_reg.h	4098;"	d
+GET_TX_SEQ_CTRL_4_0	smac/hal/ssv6006c/ssv6006C_reg.h	4106;"	d
+GET_TX_SEQ_CTRL_4_1	smac/hal/ssv6006c/ssv6006C_reg.h	4108;"	d
+GET_TX_SEQ_CTRL_4_2	smac/hal/ssv6006c/ssv6006C_reg.h	4110;"	d
+GET_TX_SEQ_CTRL_4_3	smac/hal/ssv6006c/ssv6006C_reg.h	4112;"	d
+GET_TX_SEQ_CTRL_4_4	smac/hal/ssv6006c/ssv6006C_reg.h	4114;"	d
+GET_TX_SEQ_CTRL_4_5	smac/hal/ssv6006c/ssv6006C_reg.h	4116;"	d
+GET_TX_SEQ_CTRL_4_6	smac/hal/ssv6006c/ssv6006C_reg.h	4118;"	d
+GET_TX_SEQ_CTRL_4_7	smac/hal/ssv6006c/ssv6006C_reg.h	4120;"	d
+GET_TX_SEQ_CTRL_5_0	smac/hal/ssv6006c/ssv6006C_reg.h	4128;"	d
+GET_TX_SEQ_CTRL_5_1	smac/hal/ssv6006c/ssv6006C_reg.h	4130;"	d
+GET_TX_SEQ_CTRL_5_2	smac/hal/ssv6006c/ssv6006C_reg.h	4132;"	d
+GET_TX_SEQ_CTRL_5_3	smac/hal/ssv6006c/ssv6006C_reg.h	4134;"	d
+GET_TX_SEQ_CTRL_5_4	smac/hal/ssv6006c/ssv6006C_reg.h	4136;"	d
+GET_TX_SEQ_CTRL_5_5	smac/hal/ssv6006c/ssv6006C_reg.h	4138;"	d
+GET_TX_SEQ_CTRL_5_6	smac/hal/ssv6006c/ssv6006C_reg.h	4140;"	d
+GET_TX_SEQ_CTRL_5_7	smac/hal/ssv6006c/ssv6006C_reg.h	4142;"	d
+GET_TX_SEQ_CTRL_6_0	smac/hal/ssv6006c/ssv6006C_reg.h	4150;"	d
+GET_TX_SEQ_CTRL_6_1	smac/hal/ssv6006c/ssv6006C_reg.h	4152;"	d
+GET_TX_SEQ_CTRL_6_2	smac/hal/ssv6006c/ssv6006C_reg.h	4154;"	d
+GET_TX_SEQ_CTRL_6_3	smac/hal/ssv6006c/ssv6006C_reg.h	4156;"	d
+GET_TX_SEQ_CTRL_6_4	smac/hal/ssv6006c/ssv6006C_reg.h	4158;"	d
+GET_TX_SEQ_CTRL_6_5	smac/hal/ssv6006c/ssv6006C_reg.h	4160;"	d
+GET_TX_SEQ_CTRL_6_6	smac/hal/ssv6006c/ssv6006C_reg.h	4162;"	d
+GET_TX_SEQ_CTRL_6_7	smac/hal/ssv6006c/ssv6006C_reg.h	4164;"	d
+GET_TX_SEQ_CTRL_7_0	smac/hal/ssv6006c/ssv6006C_reg.h	4172;"	d
+GET_TX_SEQ_CTRL_7_1	smac/hal/ssv6006c/ssv6006C_reg.h	4174;"	d
+GET_TX_SEQ_CTRL_7_2	smac/hal/ssv6006c/ssv6006C_reg.h	4176;"	d
+GET_TX_SEQ_CTRL_7_3	smac/hal/ssv6006c/ssv6006C_reg.h	4178;"	d
+GET_TX_SEQ_CTRL_7_4	smac/hal/ssv6006c/ssv6006C_reg.h	4180;"	d
+GET_TX_SEQ_CTRL_7_5	smac/hal/ssv6006c/ssv6006C_reg.h	4182;"	d
+GET_TX_SEQ_CTRL_7_6	smac/hal/ssv6006c/ssv6006C_reg.h	4184;"	d
+GET_TX_SEQ_CTRL_7_7	smac/hal/ssv6006c/ssv6006C_reg.h	4186;"	d
+GET_TX_SET_CNT	include/ssv6200_reg.h	2078;"	d
+GET_TX_SET_CNT_CLR	include/ssv6200_reg.h	2081;"	d
+GET_TX_SIZE_BEFORE_SHIFT	include/ssv6200_reg.h	1958;"	d
+GET_TX_SIZE_SHIFT_BITS	include/ssv6200_reg.h	1959;"	d
+GET_TX_THRH_IE	smac/hal/ssv6006c/ssv6006C_reg.h	2829;"	d
+GET_TX_THRL_IE	smac/hal/ssv6006c/ssv6006C_reg.h	2830;"	d
+GET_TX_TRAP_HW_ID	smac/hal/ssv6006c/ssv6006C_reg.h	3258;"	d
+GET_UART_CLK_EN	include/ssv6200_reg.h	1305;"	d
+GET_UART_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2384;"	d
+GET_UART_DATA	include/ssv6200_reg.h	2114;"	d
+GET_UART_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	2824;"	d
+GET_UART_MULTI_IRQ	include/ssv6200_reg.h	2260;"	d
+GET_UART_MULTI_IRQ_SD	include/ssv6200_reg.h	2329;"	d
+GET_UART_NCTS	include/ssv6200_reg.h	1387;"	d
+GET_UART_NCTS	smac/hal/ssv6006c/ssv6006C_reg.h	2491;"	d
+GET_UART_NRTS	include/ssv6200_reg.h	1386;"	d
+GET_UART_NRTS	smac/hal/ssv6006c/ssv6006C_reg.h	2490;"	d
+GET_UART_RXD_SEL	include/ssv6200_reg.h	1854;"	d
+GET_UART_RX_TIMEOUT	include/ssv6200_reg.h	2259;"	d
+GET_UART_RX_TIMEOUT_SD	include/ssv6200_reg.h	2328;"	d
+GET_UART_SW_RST	include/ssv6200_reg.h	1271;"	d
+GET_UART_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	2351;"	d
+GET_UART_W2B_EN	include/ssv6200_reg.h	1350;"	d
+GET_UART_W2B_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2430;"	d
+GET_US0TMR_CLK_EN	include/ssv6200_reg.h	1312;"	d
+GET_US0TMR_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2391;"	d
+GET_US0TMR_SW_RST	include/ssv6200_reg.h	1278;"	d
+GET_US0TMR_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	2357;"	d
+GET_US1TMR_CLK_EN	include/ssv6200_reg.h	1313;"	d
+GET_US1TMR_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2392;"	d
+GET_US1TMR_SW_RST	include/ssv6200_reg.h	1279;"	d
+GET_US1TMR_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	2358;"	d
+GET_US2TMR_CLK_EN	include/ssv6200_reg.h	1314;"	d
+GET_US2TMR_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2393;"	d
+GET_US2TMR_SW_RST	include/ssv6200_reg.h	1280;"	d
+GET_US2TMR_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	2359;"	d
+GET_US3TMR_CLK_EN	include/ssv6200_reg.h	1315;"	d
+GET_US3TMR_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2394;"	d
+GET_US3TMR_SW_RST	include/ssv6200_reg.h	1281;"	d
+GET_US3TMR_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	2360;"	d
+GET_USB20_HOST_SELRW	smac/hal/ssv6006c/ssv6006C_reg.h	2479;"	d
+GET_USB_BULK_IN_LEN_INIT	smac/hal/ssv6006c/ssv6006C_reg.h	3227;"	d
+GET_USB_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2404;"	d
+GET_USB_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	2348;"	d
+GET_USB_WAKE_PMU_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2508;"	d
+GET_VALID0	include/ssv6200_reg.h	2921;"	d
+GET_VALID0	smac/hal/ssv6006c/ssv6006C_reg.h	3800;"	d
+GET_VALID1	include/ssv6200_reg.h	2943;"	d
+GET_VALID1	smac/hal/ssv6006c/ssv6006C_reg.h	3822;"	d
+GET_VALID2	smac/hal/ssv6006c/ssv6006C_reg.h	4055;"	d
+GET_VALID3	smac/hal/ssv6006c/ssv6006C_reg.h	4077;"	d
+GET_VALID4	smac/hal/ssv6006c/ssv6006C_reg.h	4099;"	d
+GET_VALID5	smac/hal/ssv6006c/ssv6006C_reg.h	4121;"	d
+GET_VALID6	smac/hal/ssv6006c/ssv6006C_reg.h	4143;"	d
+GET_VALID7	smac/hal/ssv6006c/ssv6006C_reg.h	4165;"	d
+GET_VERIFY_DATA	include/ssv6200_reg.h	2395;"	d
+GET_VIAROM_EMA	smac/hal/ssv6006c/ssv6006C_reg.h	2455;"	d
+GET_VT_MON_RDY	include/ssv6200_reg.h	4775;"	d
+GET_W0_T0_SEQ	include/ssv6200_reg.h	2714;"	d
+GET_W0_T1_SEQ	include/ssv6200_reg.h	2715;"	d
+GET_W0_T2_SEQ	include/ssv6200_reg.h	2716;"	d
+GET_W0_T3_SEQ	include/ssv6200_reg.h	2717;"	d
+GET_W0_T4_SEQ	include/ssv6200_reg.h	2718;"	d
+GET_W0_T5_SEQ	include/ssv6200_reg.h	2719;"	d
+GET_W0_T6_SEQ	include/ssv6200_reg.h	2720;"	d
+GET_W0_T7_SEQ	include/ssv6200_reg.h	2721;"	d
+GET_W1_T0_SEQ	include/ssv6200_reg.h	2722;"	d
+GET_W1_T1_SEQ	include/ssv6200_reg.h	2723;"	d
+GET_W1_T2_SEQ	include/ssv6200_reg.h	2724;"	d
+GET_W1_T3_SEQ	include/ssv6200_reg.h	2725;"	d
+GET_W1_T4_SEQ	include/ssv6200_reg.h	2726;"	d
+GET_W1_T5_SEQ	include/ssv6200_reg.h	2727;"	d
+GET_W1_T6_SEQ	include/ssv6200_reg.h	2728;"	d
+GET_W1_T7_SEQ	include/ssv6200_reg.h	2729;"	d
+GET_WAKE_SOON_WITH_SCK	include/ssv6200_reg.h	2488;"	d
+GET_WAKE_SOON_WITH_SCK	smac/hal/ssv6006c/ssv6006C_reg.h	2484;"	d
+GET_WDT_CLK_EN	include/ssv6200_reg.h	1307;"	d
+GET_WDT_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2386;"	d
+GET_WDT_INIT	include/ssv6200_reg.h	1383;"	d
+GET_WDT_MCU_RESET	smac/hal/ssv6006c/ssv6006C_reg.h	2486;"	d
+GET_WDT_SW_RST	include/ssv6200_reg.h	1273;"	d
+GET_WDT_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	2353;"	d
+GET_WDT_SYS_RESET	smac/hal/ssv6006c/ssv6006C_reg.h	2487;"	d
+GET_WIFI_RX_SW_O_C	include/ssv6200_reg.h	1453;"	d
+GET_WIFI_RX_SW_O_OE	include/ssv6200_reg.h	1448;"	d
+GET_WIFI_RX_SW_O_PE	include/ssv6200_reg.h	1449;"	d
+GET_WIFI_RX_SW_POL	include/ssv6200_reg.h	3117;"	d
+GET_WIFI_RX_SW_POL	smac/hal/ssv6006c/ssv6006C_reg.h	3956;"	d
+GET_WIFI_TX_SW_O_C	include/ssv6200_reg.h	1447;"	d
+GET_WIFI_TX_SW_O_OE	include/ssv6200_reg.h	1441;"	d
+GET_WIFI_TX_SW_O_PE	include/ssv6200_reg.h	1442;"	d
+GET_WIFI_TX_SW_POL	include/ssv6200_reg.h	3116;"	d
+GET_WIFI_TX_SW_POL	smac/hal/ssv6006c/ssv6006C_reg.h	3955;"	d
+GET_WIRE_MODE	include/ssv6200_reg.h	3107;"	d
+GET_WIRE_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	3946;"	d
+GET_WLAN_ACT_POL	include/ssv6200_reg.h	3113;"	d
+GET_WLAN_ACT_POL	smac/hal/ssv6006c/ssv6006C_reg.h	3952;"	d
+GET_WLAN_REMAIN_TIME	include/ssv6200_reg.h	3122;"	d
+GET_WLAN_REMAIN_TIME	smac/hal/ssv6006c/ssv6006C_reg.h	3961;"	d
+GET_WL_RX_PRI	include/ssv6200_reg.h	3108;"	d
+GET_WL_RX_PRI	smac/hal/ssv6006c/ssv6006C_reg.h	3947;"	d
+GET_WL_TX_PRI	include/ssv6200_reg.h	3109;"	d
+GET_WL_TX_PRI	smac/hal/ssv6006c/ssv6006C_reg.h	3948;"	d
+GET_WORD_LEN	include/ssv6200_reg.h	2128;"	d
+GET_WORD_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	2838;"	d
+GET_WRAP_EN	smac/hal/ssv6006c/ssv6006C_reg.h	2964;"	d
+GET_WRITE_ADDRESS	include/ssv6200_reg.h	1936;"	d
+GET_WRITE_DATA	include/ssv6200_reg.h	1935;"	d
+GET_WR_ADDR	include/ssv6200_reg.h	2546;"	d
+GET_WR_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	3284;"	d
+GET_WR_ID	include/ssv6200_reg.h	2547;"	d
+GET_WR_ID	smac/hal/ssv6006c/ssv6006C_reg.h	3285;"	d
+GET_XLNA_EN_O_C	include/ssv6200_reg.h	1440;"	d
+GET_XLNA_EN_O_OE	include/ssv6200_reg.h	1434;"	d
+GET_XLNA_EN_O_PE	include/ssv6200_reg.h	1435;"	d
+GET_XPA_EN_O_C	include/ssv6200_reg.h	1467;"	d
+GET_XPA_EN_O_OE	include/ssv6200_reg.h	1461;"	d
+GET_XPA_EN_O_PE	include/ssv6200_reg.h	1462;"	d
+GLOBAL_NL_ID	smac/ksmartlink.c	35;"	d	file:
+GLOBAL_NL_ID	smartlink/ssv_smartlink.c	26;"	d	file:
+GN_CCA_CNT_HI	include/ssv6200_aux.h	15269;"	d
+GN_CCA_CNT_I_MSK	include/ssv6200_aux.h	15267;"	d
+GN_CCA_CNT_MSK	include/ssv6200_aux.h	15266;"	d
+GN_CCA_CNT_SFT	include/ssv6200_aux.h	15268;"	d
+GN_CCA_CNT_SZ	include/ssv6200_aux.h	15270;"	d
+GN_LENGTH_FIELD_HI	include/ssv6200_aux.h	15274;"	d
+GN_LENGTH_FIELD_I_MSK	include/ssv6200_aux.h	15272;"	d
+GN_LENGTH_FIELD_MSK	include/ssv6200_aux.h	15271;"	d
+GN_LENGTH_FIELD_SFT	include/ssv6200_aux.h	15273;"	d
+GN_LENGTH_FIELD_SZ	include/ssv6200_aux.h	15275;"	d
+GN_NOISE_PWR_HI	include/ssv6200_aux.h	15224;"	d
+GN_NOISE_PWR_I_MSK	include/ssv6200_aux.h	15222;"	d
+GN_NOISE_PWR_MSK	include/ssv6200_aux.h	15221;"	d
+GN_NOISE_PWR_SFT	include/ssv6200_aux.h	15223;"	d
+GN_NOISE_PWR_SZ	include/ssv6200_aux.h	15225;"	d
+GN_PACKET_CNT_HI	include/ssv6200_aux.h	15264;"	d
+GN_PACKET_CNT_I_MSK	include/ssv6200_aux.h	15262;"	d
+GN_PACKET_CNT_MSK	include/ssv6200_aux.h	15261;"	d
+GN_PACKET_CNT_SFT	include/ssv6200_aux.h	15263;"	d
+GN_PACKET_CNT_SZ	include/ssv6200_aux.h	15265;"	d
+GN_PACKET_ERR_CNT_HI	include/ssv6200_aux.h	15259;"	d
+GN_PACKET_ERR_CNT_I_MSK	include/ssv6200_aux.h	15257;"	d
+GN_PACKET_ERR_CNT_MSK	include/ssv6200_aux.h	15256;"	d
+GN_PACKET_ERR_CNT_SFT	include/ssv6200_aux.h	15258;"	d
+GN_PACKET_ERR_CNT_SZ	include/ssv6200_aux.h	15260;"	d
+GN_RCPI_HI	include/ssv6200_aux.h	15229;"	d
+GN_RCPI_I_MSK	include/ssv6200_aux.h	15227;"	d
+GN_RCPI_MSK	include/ssv6200_aux.h	15226;"	d
+GN_RCPI_SFT	include/ssv6200_aux.h	15228;"	d
+GN_RCPI_SZ	include/ssv6200_aux.h	15230;"	d
+GN_SERVICE_FIELD_HI	include/ssv6200_aux.h	15279;"	d
+GN_SERVICE_FIELD_I_MSK	include/ssv6200_aux.h	15277;"	d
+GN_SERVICE_FIELD_MSK	include/ssv6200_aux.h	15276;"	d
+GN_SERVICE_FIELD_SFT	include/ssv6200_aux.h	15278;"	d
+GN_SERVICE_FIELD_SZ	include/ssv6200_aux.h	15280;"	d
+GN_SIGNAL_PWR_HI	include/ssv6200_aux.h	15234;"	d
+GN_SIGNAL_PWR_I_MSK	include/ssv6200_aux.h	15232;"	d
+GN_SIGNAL_PWR_MSK	include/ssv6200_aux.h	15231;"	d
+GN_SIGNAL_PWR_SFT	include/ssv6200_aux.h	15233;"	d
+GN_SIGNAL_PWR_SZ	include/ssv6200_aux.h	15235;"	d
+GN_SNR_HI	include/ssv6200_aux.h	15219;"	d
+GN_SNR_I_MSK	include/ssv6200_aux.h	15217;"	d
+GN_SNR_MSK	include/ssv6200_aux.h	15216;"	d
+GN_SNR_SFT	include/ssv6200_aux.h	15218;"	d
+GN_SNR_SZ	include/ssv6200_aux.h	15220;"	d
+GPIO_10_ID_HI	include/ssv6200_aux.h	2064;"	d
+GPIO_10_ID_I_MSK	include/ssv6200_aux.h	2062;"	d
+GPIO_10_ID_MSK	include/ssv6200_aux.h	2061;"	d
+GPIO_10_ID_SFT	include/ssv6200_aux.h	2063;"	d
+GPIO_10_ID_SZ	include/ssv6200_aux.h	2065;"	d
+GPIO_11_ID_HI	include/ssv6200_aux.h	2109;"	d
+GPIO_11_ID_I_MSK	include/ssv6200_aux.h	2107;"	d
+GPIO_11_ID_MSK	include/ssv6200_aux.h	2106;"	d
+GPIO_11_ID_SFT	include/ssv6200_aux.h	2108;"	d
+GPIO_11_ID_SZ	include/ssv6200_aux.h	2110;"	d
+GPIO_12_ID_HI	include/ssv6200_aux.h	2154;"	d
+GPIO_12_ID_I_MSK	include/ssv6200_aux.h	2152;"	d
+GPIO_12_ID_MSK	include/ssv6200_aux.h	2151;"	d
+GPIO_12_ID_SFT	include/ssv6200_aux.h	2153;"	d
+GPIO_12_ID_SZ	include/ssv6200_aux.h	2155;"	d
+GPIO_13_ID_HI	include/ssv6200_aux.h	2199;"	d
+GPIO_13_ID_I_MSK	include/ssv6200_aux.h	2197;"	d
+GPIO_13_ID_MSK	include/ssv6200_aux.h	2196;"	d
+GPIO_13_ID_SFT	include/ssv6200_aux.h	2198;"	d
+GPIO_13_ID_SZ	include/ssv6200_aux.h	2200;"	d
+GPIO_14_ID_HI	include/ssv6200_aux.h	2239;"	d
+GPIO_14_ID_I_MSK	include/ssv6200_aux.h	2237;"	d
+GPIO_14_ID_MSK	include/ssv6200_aux.h	2236;"	d
+GPIO_14_ID_SFT	include/ssv6200_aux.h	2238;"	d
+GPIO_14_ID_SZ	include/ssv6200_aux.h	2240;"	d
+GPIO_15_IP_ID_HI	include/ssv6200_aux.h	2624;"	d
+GPIO_15_IP_ID_I_MSK	include/ssv6200_aux.h	2622;"	d
+GPIO_15_IP_ID_MSK	include/ssv6200_aux.h	2621;"	d
+GPIO_15_IP_ID_SFT	include/ssv6200_aux.h	2623;"	d
+GPIO_15_IP_ID_SZ	include/ssv6200_aux.h	2625;"	d
+GPIO_17_QP_ID_HI	include/ssv6200_aux.h	2704;"	d
+GPIO_17_QP_ID_I_MSK	include/ssv6200_aux.h	2702;"	d
+GPIO_17_QP_ID_MSK	include/ssv6200_aux.h	2701;"	d
+GPIO_17_QP_ID_SFT	include/ssv6200_aux.h	2703;"	d
+GPIO_17_QP_ID_SZ	include/ssv6200_aux.h	2705;"	d
+GPIO_19_ID_HI	include/ssv6200_aux.h	2739;"	d
+GPIO_19_ID_I_MSK	include/ssv6200_aux.h	2737;"	d
+GPIO_19_ID_MSK	include/ssv6200_aux.h	2736;"	d
+GPIO_19_ID_SFT	include/ssv6200_aux.h	2738;"	d
+GPIO_19_ID_SZ	include/ssv6200_aux.h	2740;"	d
+GPIO_1_ID_HI	include/ssv6200_aux.h	1449;"	d
+GPIO_1_ID_I_MSK	include/ssv6200_aux.h	1447;"	d
+GPIO_1_ID_MSK	include/ssv6200_aux.h	1446;"	d
+GPIO_1_ID_SFT	include/ssv6200_aux.h	1448;"	d
+GPIO_1_ID_SZ	include/ssv6200_aux.h	1450;"	d
+GPIO_20_ID_HI	include/ssv6200_aux.h	2824;"	d
+GPIO_20_ID_I_MSK	include/ssv6200_aux.h	2822;"	d
+GPIO_20_ID_MSK	include/ssv6200_aux.h	2821;"	d
+GPIO_20_ID_SFT	include/ssv6200_aux.h	2823;"	d
+GPIO_20_ID_SZ	include/ssv6200_aux.h	2825;"	d
+GPIO_21_ID_HI	include/ssv6200_aux.h	2864;"	d
+GPIO_21_ID_I_MSK	include/ssv6200_aux.h	2862;"	d
+GPIO_21_ID_MSK	include/ssv6200_aux.h	2861;"	d
+GPIO_21_ID_SFT	include/ssv6200_aux.h	2863;"	d
+GPIO_21_ID_SZ	include/ssv6200_aux.h	2865;"	d
+GPIO_2_ID_HI	include/ssv6200_aux.h	1489;"	d
+GPIO_2_ID_I_MSK	include/ssv6200_aux.h	1487;"	d
+GPIO_2_ID_MSK	include/ssv6200_aux.h	1486;"	d
+GPIO_2_ID_SFT	include/ssv6200_aux.h	1488;"	d
+GPIO_2_ID_SZ	include/ssv6200_aux.h	1490;"	d
+GPIO_3_ID_HI	include/ssv6200_aux.h	1534;"	d
+GPIO_3_ID_I_MSK	include/ssv6200_aux.h	1532;"	d
+GPIO_3_ID_MSK	include/ssv6200_aux.h	1531;"	d
+GPIO_3_ID_SFT	include/ssv6200_aux.h	1533;"	d
+GPIO_3_ID_SZ	include/ssv6200_aux.h	1535;"	d
+GPIO_9_ID_HI	include/ssv6200_aux.h	2014;"	d
+GPIO_9_ID_I_MSK	include/ssv6200_aux.h	2012;"	d
+GPIO_9_ID_MSK	include/ssv6200_aux.h	2011;"	d
+GPIO_9_ID_SFT	include/ssv6200_aux.h	2013;"	d
+GPIO_9_ID_SZ	include/ssv6200_aux.h	2015;"	d
+GPIO_CLK_EN_HI	include/ssv6200_aux.h	244;"	d
+GPIO_CLK_EN_I_MSK	include/ssv6200_aux.h	242;"	d
+GPIO_CLK_EN_MSK	include/ssv6200_aux.h	241;"	d
+GPIO_CLK_EN_SFT	include/ssv6200_aux.h	243;"	d
+GPIO_CLK_EN_SZ	include/ssv6200_aux.h	245;"	d
+GPIO_INT_TRIGGER_OPTION_HI	include/ssv6200_aux.h	3159;"	d
+GPIO_INT_TRIGGER_OPTION_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2629;"	d
+GPIO_INT_TRIGGER_OPTION_I_MSK	include/ssv6200_aux.h	3157;"	d
+GPIO_INT_TRIGGER_OPTION_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2627;"	d
+GPIO_INT_TRIGGER_OPTION_MSK	include/ssv6200_aux.h	3156;"	d
+GPIO_INT_TRIGGER_OPTION_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2626;"	d
+GPIO_INT_TRIGGER_OPTION_SFT	include/ssv6200_aux.h	3158;"	d
+GPIO_INT_TRIGGER_OPTION_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2628;"	d
+GPIO_INT_TRIGGER_OPTION_SZ	include/ssv6200_aux.h	3160;"	d
+GPIO_INT_TRIGGER_OPTION_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2630;"	d
+GPIO_LOG_STOP_SEL_HI	include/ssv6200_aux.h	2974;"	d
+GPIO_LOG_STOP_SEL_I_MSK	include/ssv6200_aux.h	2972;"	d
+GPIO_LOG_STOP_SEL_MSK	include/ssv6200_aux.h	2971;"	d
+GPIO_LOG_STOP_SEL_SFT	include/ssv6200_aux.h	2973;"	d
+GPIO_LOG_STOP_SEL_SZ	include/ssv6200_aux.h	2975;"	d
+GPIO_REG_BANK_SIZE	include/ssv6200_reg.h	77;"	d
+GPIO_REG_BASE	include/ssv6200_reg.h	28;"	d
+GPIO_REG_WRITEL	platforms/aml-s805-generic-wlan.c	35;"	d	file:
+GPIO_REG_WRITEL	platforms/aml-s905-generic-wlan.c	35;"	d	file:
+GPIO_REG_WRITEL	platforms/h3-generic-wlan.c	47;"	d	file:
+GPIO_REG_WRITEL	platforms/h8-generic-wlan.c	47;"	d	file:
+GPIO_REG_WRITEL	platforms/rk3036-generic-wlan.c	36;"	d	file:
+GPIO_REG_WRITEL	platforms/rk3126-generic-wlan.c	52;"	d	file:
+GPIO_REG_WRITEL	platforms/rk3128-generic-wlan.c	33;"	d	file:
+GPIO_REG_WRITEL	platforms/rk322x-generic-wlan.c	36;"	d	file:
+GPIO_REG_WRITEL	platforms/t10-generic-wlan.c	46;"	d	file:
+GPIO_REG_WRITEL	platforms/x1000-generic-wlan.c	46;"	d	file:
+GPIO_REG_WRITEL	platforms/xm-hi3518-generic-wlan.c	31;"	d	file:
+GPIO_STOP_EN_HI	include/ssv6200_aux.h	12444;"	d
+GPIO_STOP_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1374;"	d
+GPIO_STOP_EN_I_MSK	include/ssv6200_aux.h	12442;"	d
+GPIO_STOP_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1372;"	d
+GPIO_STOP_EN_MSK	include/ssv6200_aux.h	12441;"	d
+GPIO_STOP_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1371;"	d
+GPIO_STOP_EN_SFT	include/ssv6200_aux.h	12443;"	d
+GPIO_STOP_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1373;"	d
+GPIO_STOP_EN_SZ	include/ssv6200_aux.h	12445;"	d
+GPIO_STOP_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1375;"	d
+GPIO_STOP_POL_HI	include/ssv6200_aux.h	12449;"	d
+GPIO_STOP_POL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1369;"	d
+GPIO_STOP_POL_I_MSK	include/ssv6200_aux.h	12447;"	d
+GPIO_STOP_POL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1367;"	d
+GPIO_STOP_POL_MSK	include/ssv6200_aux.h	12446;"	d
+GPIO_STOP_POL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1366;"	d
+GPIO_STOP_POL_SFT	include/ssv6200_aux.h	12448;"	d
+GPIO_STOP_POL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1368;"	d
+GPIO_STOP_POL_SZ	include/ssv6200_aux.h	12450;"	d
+GPIO_STOP_POL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1370;"	d
+GPIO_STOP_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1364;"	d
+GPIO_STOP_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1362;"	d
+GPIO_STOP_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1361;"	d
+GPIO_STOP_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1363;"	d
+GPIO_STOP_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1365;"	d
+GPIO_SW_RST_HI	include/ssv6200_aux.h	74;"	d
+GPIO_SW_RST_I_MSK	include/ssv6200_aux.h	72;"	d
+GPIO_SW_RST_MSK	include/ssv6200_aux.h	71;"	d
+GPIO_SW_RST_SFT	include/ssv6200_aux.h	73;"	d
+GPIO_SW_RST_SZ	include/ssv6200_aux.h	75;"	d
+GPIO_TEST_1_ID_HI	include/ssv6200_aux.h	1269;"	d
+GPIO_TEST_1_ID_I_MSK	include/ssv6200_aux.h	1267;"	d
+GPIO_TEST_1_ID_MSK	include/ssv6200_aux.h	1266;"	d
+GPIO_TEST_1_ID_SFT	include/ssv6200_aux.h	1268;"	d
+GPIO_TEST_1_ID_SZ	include/ssv6200_aux.h	1270;"	d
+GPIO_TEST_2_ID_HI	include/ssv6200_aux.h	1314;"	d
+GPIO_TEST_2_ID_I_MSK	include/ssv6200_aux.h	1312;"	d
+GPIO_TEST_2_ID_MSK	include/ssv6200_aux.h	1311;"	d
+GPIO_TEST_2_ID_SFT	include/ssv6200_aux.h	1313;"	d
+GPIO_TEST_2_ID_SZ	include/ssv6200_aux.h	1315;"	d
+GPIO_TEST_3_ID_HI	include/ssv6200_aux.h	1359;"	d
+GPIO_TEST_3_ID_I_MSK	include/ssv6200_aux.h	1357;"	d
+GPIO_TEST_3_ID_MSK	include/ssv6200_aux.h	1356;"	d
+GPIO_TEST_3_ID_SFT	include/ssv6200_aux.h	1358;"	d
+GPIO_TEST_3_ID_SZ	include/ssv6200_aux.h	1360;"	d
+GPIO_TEST_4_ID_HI	include/ssv6200_aux.h	1399;"	d
+GPIO_TEST_4_ID_I_MSK	include/ssv6200_aux.h	1397;"	d
+GPIO_TEST_4_ID_MSK	include/ssv6200_aux.h	1396;"	d
+GPIO_TEST_4_ID_SFT	include/ssv6200_aux.h	1398;"	d
+GPIO_TEST_4_ID_SZ	include/ssv6200_aux.h	1400;"	d
+GPIO_TEST_5_ID_HI	include/ssv6200_aux.h	1574;"	d
+GPIO_TEST_5_ID_I_MSK	include/ssv6200_aux.h	1572;"	d
+GPIO_TEST_5_ID_MSK	include/ssv6200_aux.h	1571;"	d
+GPIO_TEST_5_ID_SFT	include/ssv6200_aux.h	1573;"	d
+GPIO_TEST_5_ID_SZ	include/ssv6200_aux.h	1575;"	d
+GPIO_TEST_7_IN_ID_HI	include/ssv6200_aux.h	2664;"	d
+GPIO_TEST_7_IN_ID_I_MSK	include/ssv6200_aux.h	2662;"	d
+GPIO_TEST_7_IN_ID_MSK	include/ssv6200_aux.h	2661;"	d
+GPIO_TEST_7_IN_ID_SFT	include/ssv6200_aux.h	2663;"	d
+GPIO_TEST_7_IN_ID_SZ	include/ssv6200_aux.h	2665;"	d
+GPIO_TEST_8_QN_ID_HI	include/ssv6200_aux.h	2779;"	d
+GPIO_TEST_8_QN_ID_I_MSK	include/ssv6200_aux.h	2777;"	d
+GPIO_TEST_8_QN_ID_MSK	include/ssv6200_aux.h	2776;"	d
+GPIO_TEST_8_QN_ID_SFT	include/ssv6200_aux.h	2778;"	d
+GPIO_TEST_8_QN_ID_SZ	include/ssv6200_aux.h	2780;"	d
+GPO_INT_POL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4689;"	d
+GPO_INT_POL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4687;"	d
+GPO_INT_POL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4686;"	d
+GPO_INT_POL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4688;"	d
+GPO_INT_POL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4690;"	d
+GREEN_PWR	smac/dev.h	575;"	d
+GROUP_IDX	smac/ssv_rc_minstrel_ht.c	39;"	d	file:
+GRP_SCRT_HI	include/ssv6200_aux.h	9204;"	d
+GRP_SCRT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8964;"	d
+GRP_SCRT_I_MSK	include/ssv6200_aux.h	9202;"	d
+GRP_SCRT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8962;"	d
+GRP_SCRT_MSK	include/ssv6200_aux.h	9201;"	d
+GRP_SCRT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8961;"	d
+GRP_SCRT_SFT	include/ssv6200_aux.h	9203;"	d
+GRP_SCRT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8963;"	d
+GRP_SCRT_SZ	include/ssv6200_aux.h	9205;"	d
+GRP_SCRT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8965;"	d
+GRP_WSID_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6434;"	d
+GRP_WSID_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6432;"	d
+GRP_WSID_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6431;"	d
+GRP_WSID_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6433;"	d
+GRP_WSID_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6435;"	d
+GT_DBG	smac/dev.h	52;"	d
+GT_ENABLE	smac/dev.h	51;"	d
+GT_PWR_START_MASK	smac/dev.h	50;"	d
+GURAN_USE_CTRL_HI	include/ssv6200_aux.h	9244;"	d
+GURAN_USE_CTRL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9034;"	d
+GURAN_USE_CTRL_I_MSK	include/ssv6200_aux.h	9242;"	d
+GURAN_USE_CTRL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9032;"	d
+GURAN_USE_CTRL_MSK	include/ssv6200_aux.h	9241;"	d
+GURAN_USE_CTRL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9031;"	d
+GURAN_USE_CTRL_SFT	include/ssv6200_aux.h	9243;"	d
+GURAN_USE_CTRL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9033;"	d
+GURAN_USE_CTRL_SZ	include/ssv6200_aux.h	9245;"	d
+GURAN_USE_CTRL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9035;"	d
+GURAN_USE_EN_HI	include/ssv6200_aux.h	9239;"	d
+GURAN_USE_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9029;"	d
+GURAN_USE_EN_I_MSK	include/ssv6200_aux.h	9237;"	d
+GURAN_USE_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9027;"	d
+GURAN_USE_EN_MSK	include/ssv6200_aux.h	9236;"	d
+GURAN_USE_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9026;"	d
+GURAN_USE_EN_SFT	include/ssv6200_aux.h	9238;"	d
+GURAN_USE_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9028;"	d
+GURAN_USE_EN_SZ	include/ssv6200_aux.h	9240;"	d
+GURAN_USE_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9030;"	d
+G_BAND_ONLY	smac/hal/ssv6006c/turismo_common.h	/^    G_BAND_ONLY = 0,$/;"	e	enum:__anon3
+HALT_CH0_HI	include/ssv6200_aux.h	11614;"	d
+HALT_CH0_I_MSK	include/ssv6200_aux.h	11612;"	d
+HALT_CH0_MSK	include/ssv6200_aux.h	11611;"	d
+HALT_CH0_SFT	include/ssv6200_aux.h	11613;"	d
+HALT_CH0_SZ	include/ssv6200_aux.h	11615;"	d
+HALT_CH10_HI	include/ssv6200_aux.h	11664;"	d
+HALT_CH10_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33249;"	d
+HALT_CH10_I_MSK	include/ssv6200_aux.h	11662;"	d
+HALT_CH10_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33247;"	d
+HALT_CH10_MSK	include/ssv6200_aux.h	11661;"	d
+HALT_CH10_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33246;"	d
+HALT_CH10_SFT	include/ssv6200_aux.h	11663;"	d
+HALT_CH10_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33248;"	d
+HALT_CH10_SZ	include/ssv6200_aux.h	11665;"	d
+HALT_CH10_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33250;"	d
+HALT_CH11_HI	include/ssv6200_aux.h	11669;"	d
+HALT_CH11_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33254;"	d
+HALT_CH11_I_MSK	include/ssv6200_aux.h	11667;"	d
+HALT_CH11_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33252;"	d
+HALT_CH11_MSK	include/ssv6200_aux.h	11666;"	d
+HALT_CH11_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33251;"	d
+HALT_CH11_SFT	include/ssv6200_aux.h	11668;"	d
+HALT_CH11_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33253;"	d
+HALT_CH11_SZ	include/ssv6200_aux.h	11670;"	d
+HALT_CH11_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33255;"	d
+HALT_CH12_HI	include/ssv6200_aux.h	11674;"	d
+HALT_CH12_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33259;"	d
+HALT_CH12_I_MSK	include/ssv6200_aux.h	11672;"	d
+HALT_CH12_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33257;"	d
+HALT_CH12_MSK	include/ssv6200_aux.h	11671;"	d
+HALT_CH12_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33256;"	d
+HALT_CH12_SFT	include/ssv6200_aux.h	11673;"	d
+HALT_CH12_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33258;"	d
+HALT_CH12_SZ	include/ssv6200_aux.h	11675;"	d
+HALT_CH12_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33260;"	d
+HALT_CH13_HI	include/ssv6200_aux.h	11679;"	d
+HALT_CH13_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33264;"	d
+HALT_CH13_I_MSK	include/ssv6200_aux.h	11677;"	d
+HALT_CH13_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33262;"	d
+HALT_CH13_MSK	include/ssv6200_aux.h	11676;"	d
+HALT_CH13_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33261;"	d
+HALT_CH13_SFT	include/ssv6200_aux.h	11678;"	d
+HALT_CH13_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33263;"	d
+HALT_CH13_SZ	include/ssv6200_aux.h	11680;"	d
+HALT_CH13_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33265;"	d
+HALT_CH14_HI	include/ssv6200_aux.h	11684;"	d
+HALT_CH14_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33269;"	d
+HALT_CH14_I_MSK	include/ssv6200_aux.h	11682;"	d
+HALT_CH14_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33267;"	d
+HALT_CH14_MSK	include/ssv6200_aux.h	11681;"	d
+HALT_CH14_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33266;"	d
+HALT_CH14_SFT	include/ssv6200_aux.h	11683;"	d
+HALT_CH14_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33268;"	d
+HALT_CH14_SZ	include/ssv6200_aux.h	11685;"	d
+HALT_CH14_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33270;"	d
+HALT_CH15_HI	include/ssv6200_aux.h	11689;"	d
+HALT_CH15_I_MSK	include/ssv6200_aux.h	11687;"	d
+HALT_CH15_MSK	include/ssv6200_aux.h	11686;"	d
+HALT_CH15_SFT	include/ssv6200_aux.h	11688;"	d
+HALT_CH15_SZ	include/ssv6200_aux.h	11690;"	d
+HALT_CH1_HI	include/ssv6200_aux.h	11619;"	d
+HALT_CH1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33209;"	d
+HALT_CH1_I_MSK	include/ssv6200_aux.h	11617;"	d
+HALT_CH1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33207;"	d
+HALT_CH1_MSK	include/ssv6200_aux.h	11616;"	d
+HALT_CH1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33206;"	d
+HALT_CH1_SFT	include/ssv6200_aux.h	11618;"	d
+HALT_CH1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33208;"	d
+HALT_CH1_SZ	include/ssv6200_aux.h	11620;"	d
+HALT_CH1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33210;"	d
+HALT_CH2_HI	include/ssv6200_aux.h	11624;"	d
+HALT_CH2_I_MSK	include/ssv6200_aux.h	11622;"	d
+HALT_CH2_MSK	include/ssv6200_aux.h	11621;"	d
+HALT_CH2_SFT	include/ssv6200_aux.h	11623;"	d
+HALT_CH2_SZ	include/ssv6200_aux.h	11625;"	d
+HALT_CH3_HI	include/ssv6200_aux.h	11629;"	d
+HALT_CH3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33214;"	d
+HALT_CH3_I_MSK	include/ssv6200_aux.h	11627;"	d
+HALT_CH3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33212;"	d
+HALT_CH3_MSK	include/ssv6200_aux.h	11626;"	d
+HALT_CH3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33211;"	d
+HALT_CH3_SFT	include/ssv6200_aux.h	11628;"	d
+HALT_CH3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33213;"	d
+HALT_CH3_SZ	include/ssv6200_aux.h	11630;"	d
+HALT_CH3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33215;"	d
+HALT_CH4_HI	include/ssv6200_aux.h	11634;"	d
+HALT_CH4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33219;"	d
+HALT_CH4_I_MSK	include/ssv6200_aux.h	11632;"	d
+HALT_CH4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33217;"	d
+HALT_CH4_MSK	include/ssv6200_aux.h	11631;"	d
+HALT_CH4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33216;"	d
+HALT_CH4_SFT	include/ssv6200_aux.h	11633;"	d
+HALT_CH4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33218;"	d
+HALT_CH4_SZ	include/ssv6200_aux.h	11635;"	d
+HALT_CH4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33220;"	d
+HALT_CH5_HI	include/ssv6200_aux.h	11639;"	d
+HALT_CH5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33224;"	d
+HALT_CH5_I_MSK	include/ssv6200_aux.h	11637;"	d
+HALT_CH5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33222;"	d
+HALT_CH5_MSK	include/ssv6200_aux.h	11636;"	d
+HALT_CH5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33221;"	d
+HALT_CH5_SFT	include/ssv6200_aux.h	11638;"	d
+HALT_CH5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33223;"	d
+HALT_CH5_SZ	include/ssv6200_aux.h	11640;"	d
+HALT_CH5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33225;"	d
+HALT_CH6_HI	include/ssv6200_aux.h	11644;"	d
+HALT_CH6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33229;"	d
+HALT_CH6_I_MSK	include/ssv6200_aux.h	11642;"	d
+HALT_CH6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33227;"	d
+HALT_CH6_MSK	include/ssv6200_aux.h	11641;"	d
+HALT_CH6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33226;"	d
+HALT_CH6_SFT	include/ssv6200_aux.h	11643;"	d
+HALT_CH6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33228;"	d
+HALT_CH6_SZ	include/ssv6200_aux.h	11645;"	d
+HALT_CH6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33230;"	d
+HALT_CH7_HI	include/ssv6200_aux.h	11649;"	d
+HALT_CH7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33234;"	d
+HALT_CH7_I_MSK	include/ssv6200_aux.h	11647;"	d
+HALT_CH7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33232;"	d
+HALT_CH7_MSK	include/ssv6200_aux.h	11646;"	d
+HALT_CH7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33231;"	d
+HALT_CH7_SFT	include/ssv6200_aux.h	11648;"	d
+HALT_CH7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33233;"	d
+HALT_CH7_SZ	include/ssv6200_aux.h	11650;"	d
+HALT_CH7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33235;"	d
+HALT_CH8_HI	include/ssv6200_aux.h	11654;"	d
+HALT_CH8_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33239;"	d
+HALT_CH8_I_MSK	include/ssv6200_aux.h	11652;"	d
+HALT_CH8_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33237;"	d
+HALT_CH8_MSK	include/ssv6200_aux.h	11651;"	d
+HALT_CH8_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33236;"	d
+HALT_CH8_SFT	include/ssv6200_aux.h	11653;"	d
+HALT_CH8_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33238;"	d
+HALT_CH8_SZ	include/ssv6200_aux.h	11655;"	d
+HALT_CH8_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33240;"	d
+HALT_CH9_HI	include/ssv6200_aux.h	11659;"	d
+HALT_CH9_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33244;"	d
+HALT_CH9_I_MSK	include/ssv6200_aux.h	11657;"	d
+HALT_CH9_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33242;"	d
+HALT_CH9_MSK	include/ssv6200_aux.h	11656;"	d
+HALT_CH9_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33241;"	d
+HALT_CH9_SFT	include/ssv6200_aux.h	11658;"	d
+HALT_CH9_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33243;"	d
+HALT_CH9_SZ	include/ssv6200_aux.h	11660;"	d
+HALT_CH9_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33245;"	d
+HAL_ADD_AMPDU_TXINFO	include/hal.h	242;"	d
+HAL_ADD_FW_WSID	include/hal.h	60;"	d
+HAL_ADD_TXINFO	include/hal.h	238;"	d
+HAL_ADJ_CONFIG	include/hal.h	36;"	d
+HAL_ALLOC_PBUF	include/hal.h	136;"	d
+HAL_AMPDU_AUTO_CRC_EN	include/hal.h	139;"	d
+HAL_AMPDU_BA_HANDLER	include/hal.h	309;"	d
+HAL_AMPDU_MAX_TRANSMIT_LENGTH	include/hal.h	312;"	d
+HAL_AMPDU_RX_START	include/hal.h	307;"	d
+HAL_AUTO_GEN_NULLPKT	include/hal.h	198;"	d
+HAL_BEACON_ENABLE	include/hal.h	151;"	d
+HAL_BEACON_GET_VALID_CFG	include/hal.h	144;"	d
+HAL_BEACON_LOSS_CONFIG	include/hal.h	157;"	d
+HAL_BEACON_LOSS_DISABLE	include/hal.h	156;"	d
+HAL_BEACON_LOSS_ENABLE	include/hal.h	155;"	d
+HAL_BURST_READ_REG	include/hal.h	194;"	d
+HAL_BURST_WRITE_REG	include/hal.h	196;"	d
+HAL_CHG_CLK_SRC	include/hal.h	324;"	d
+HAL_CHG_IPD_PHYINFO	include/hal.h	337;"	d
+HAL_CHG_PAD_SETTING	include/hal.h	323;"	d
+HAL_CHK_DUAL_VIF_CHG_RX_FLOW	include/hal.h	94;"	d
+HAL_CHK_IF_SUPPORT_HW_BSSID	include/hal.h	92;"	d
+HAL_CHK_LPBK_RX_RATE_DESC	include/hal.h	259;"	d
+HAL_CMD_CALI	include/hal.h	192;"	d
+HAL_CMD_CCI	include/hal.h	302;"	d
+HAL_CMD_EFUSE	include/hal.h	296;"	d
+HAL_CMD_HWINFO	include/hal.h	301;"	d
+HAL_CMD_HWQ_LIMIT	include/hal.h	306;"	d
+HAL_CMD_LOOPBACK	include/hal.h	298;"	d
+HAL_CMD_LOOPBACK_SETUP_ENV	include/hal.h	300;"	d
+HAL_CMD_LOOPBACK_START	include/hal.h	299;"	d
+HAL_CMD_MIB	include/hal.h	187;"	d
+HAL_CMD_POWER_SAVING	include/hal.h	188;"	d
+HAL_CMD_RC	include/hal.h	295;"	d
+HAL_CMD_RF	include/hal.h	304;"	d
+HAL_CMD_SPECTRUM	include/hal.h	297;"	d
+HAL_CMD_TXGEN	include/hal.h	303;"	d
+HAL_DEL_FW_WSID	include/hal.h	62;"	d
+HAL_DEL_HW_WSID	include/hal.h	59;"	d
+HAL_DETACH_USB_HCI	include/hal.h	237;"	d
+HAL_DISABLE_FW_WSID	include/hal.h	68;"	d
+HAL_DISABLE_USB_ACC	include/hal.h	230;"	d
+HAL_DO_IQ_CAL	include/hal.h	330;"	d
+HAL_DO_TEMPERATURE_COMPENSATION	include/hal.h	326;"	d
+HAL_DPD_ENABLE	include/hal.h	333;"	d
+HAL_DUMP_DECISION	include/hal.h	169;"	d
+HAL_DUMP_MIB_RX_PHY	include/hal.h	285;"	d
+HAL_DUMP_PHY_REG	include/hal.h	171;"	d
+HAL_DUMP_RF_REG	include/hal.h	173;"	d
+HAL_DUMP_WSID	include/hal.h	167;"	d
+HAL_EDCA_ENABLE	include/hal.h	282;"	d
+HAL_EDCA_STAT	include/hal.h	283;"	d
+HAL_ENABLE_FW_WSID	include/hal.h	66;"	d
+HAL_ENABLE_USB_ACC	include/hal.h	229;"	d
+HAL_FILL_BCN	include/hal.h	149;"	d
+HAL_FILL_BEACON_TX_DESC	include/hal.h	255;"	d
+HAL_FILL_LPBK_TX_DESC	include/hal.h	257;"	d
+HAL_FLASH_READ_ALL_MAP	include/hal.h	235;"	d
+HAL_FREE_PBUF	include/hal.h	138;"	d
+HAL_GET_BCN_ONGOING	include/hal.h	154;"	d
+HAL_GET_CHIP_ID	include/hal.h	52;"	d
+HAL_GET_FFOUT_CNT	include/hal.h	175;"	d
+HAL_GET_FW_NAME	include/hal.h	233;"	d
+HAL_GET_FW_VERSION	include/hal.h	119;"	d
+HAL_GET_IC_TIME_TAG	include/hal.h	51;"	d
+HAL_GET_IN_FFCNT	include/hal.h	177;"	d
+HAL_GET_MRX_MODE	include/hal.h	122;"	d
+HAL_GET_PHY_TABLE_SIZE	include/hal.h	315;"	d
+HAL_GET_RD_ID_ADR	include/hal.h	190;"	d
+HAL_GET_RF_TABLE_SIZE	include/hal.h	317;"	d
+HAL_GET_RX_DESC_CTYPE	include/hal.h	272;"	d
+HAL_GET_RX_DESC_HDR_OFFSET	include/hal.h	274;"	d
+HAL_GET_RX_DESC_INFO	include/hal.h	276;"	d
+HAL_GET_RX_DESC_LENGTH	include/hal.h	264;"	d
+HAL_GET_RX_DESC_MNG_USED	include/hal.h	269;"	d
+HAL_GET_RX_DESC_RATE_IDX	include/hal.h	267;"	d
+HAL_GET_RX_DESC_SIZE	include/hal.h	263;"	d
+HAL_GET_RX_DESC_WSID	include/hal.h	265;"	d
+HAL_GET_SEC_DECODE_ERR	include/hal.h	261;"	d
+HAL_GET_TX_DESC_CTYPE	include/hal.h	247;"	d
+HAL_GET_TX_DESC_REASON	include/hal.h	249;"	d
+HAL_GET_TX_DESC_SIZE	include/hal.h	246;"	d
+HAL_GET_TX_DESC_TXQ_IDX	include/hal.h	251;"	d
+HAL_GET_WSID	include/hal.h	56;"	d
+HAL_GROUP_WPA_USE_HW_CIPHER	include/hal.h	74;"	d
+HAL_HALT_MNGQ_UNTIL_DTIM	include/hal.h	124;"	d
+HAL_HT_RATE_UPDATE	include/hal.h	213;"	d
+HAL_HW_CRYPTO_KEY_WRITE_WEP	include/hal.h	98;"	d
+HAL_IF_CHK_MAC2	include/hal.h	53;"	d
+HAL_INIT_CH_CFG	include/hal.h	334;"	d
+HAL_INIT_GPIO_CFG	include/hal.h	340;"	d
+HAL_INIT_IQK	include/hal.h	41;"	d
+HAL_INIT_MAC	include/hal.h	38;"	d
+HAL_INIT_PLL	include/hal.h	318;"	d
+HAL_INIT_RX_CFG	include/hal.h	135;"	d
+HAL_INIT_TX_CFG	include/hal.h	134;"	d
+HAL_INI_HW_SEC_PHY_TABLE	include/hal.h	40;"	d
+HAL_IS_LEGACY_RATE	include/hal.h	311;"	d
+HAL_IS_RX_AGGR	include/hal.h	271;"	d
+HAL_JUMP_TO_ROM	include/hal.h	232;"	d
+HAL_LOAD_FW_DISABLE_MCU	include/hal.h	218;"	d
+HAL_LOAD_FW_ENABLE_MCU	include/hal.h	217;"	d
+HAL_LOAD_FW_GET_STATUS	include/hal.h	221;"	d
+HAL_LOAD_FW_POST_CONFIG_DEVICE	include/hal.h	225;"	d
+HAL_LOAD_FW_PRE_CONFIG_DEVICE	include/hal.h	223;"	d
+HAL_LOAD_FW_SET_STATUS	include/hal.h	219;"	d
+HAL_LOAD_PHY_TABLE	include/hal.h	314;"	d
+HAL_LOAD_RF_TABLE	include/hal.h	316;"	d
+HAL_NEED_SW_CIPHER	include/hal.h	37;"	d
+HAL_NULLFUN_FRAME_FILTER	include/hal.h	278;"	d
+HAL_PAIRWISE_WPA_USE_HW_CIPHER	include/hal.h	72;"	d
+HAL_PHY_ENABLE	include/hal.h	281;"	d
+HAL_PLL_CHK	include/hal.h	55;"	d
+HAL_PMU_AWAKE	include/hal.h	111;"	d
+HAL_PUT_MIC_SPACE_FOR_HW_CCMP_ENCRYPT	include/hal.h	104;"	d
+HAL_RATE_REPORT_HANDLER	include/hal.h	207;"	d
+HAL_RC_ALGORITHM	include/hal.h	200;"	d
+HAL_RC_HT_STA_CURRENT_RATE_IS_CCK	include/hal.h	215;"	d
+HAL_RC_LEGACY_BITRATE_TO_RATE_DESC	include/hal.h	203;"	d
+HAL_RC_MAC80211_RATE_IDX	include/hal.h	287;"	d
+HAL_RC_PROCESS_RATE_REPORT	include/hal.h	209;"	d
+HAL_RC_RX_DATA_HANDLER	include/hal.h	205;"	d
+HAL_RC_UPDATE_BASIC_RATE	include/hal.h	211;"	d
+HAL_READRG_HCI_INQ_INFO	include/hal.h	161;"	d
+HAL_READRG_TXQ_INFO	include/hal.h	163;"	d
+HAL_READRG_TXQ_INFO2	include/hal.h	165;"	d
+HAL_READ_EFUSE	include/hal.h	142;"	d
+HAL_READ_FFOUT_CNT	include/hal.h	179;"	d
+HAL_READ_ID_LEN_THRESHOLD	include/hal.h	183;"	d
+HAL_READ_IN_FFCNT	include/hal.h	181;"	d
+HAL_READ_TAG_STATUS	include/hal.h	185;"	d
+HAL_RECOVERY_SCAN_CCI_SETTING	include/hal.h	293;"	d
+HAL_RESET_CPU	include/hal.h	227;"	d
+HAL_RESET_MIB_PHY	include/hal.h	284;"	d
+HAL_RESET_SYSPLF	include/hal.h	39;"	d
+HAL_RESTORE_RX_FLOW	include/hal.h	96;"	d
+HAL_RESTORE_TRAP_REASON	include/hal.h	109;"	d
+HAL_SAVE_CLEAR_TRAP_REASON	include/hal.h	107;"	d
+HAL_SAVE_DEFAULT_IPD_CHCFG	include/hal.h	335;"	d
+HAL_SAVE_HW_STATUS	include/hal.h	54;"	d
+HAL_SEND_TX_POLL_CMD	include/hal.h	234;"	d
+HAL_SET_80211HW_RATE_CONFIG	include/hal.h	201;"	d
+HAL_SET_AES_TKIP_HW_CRYPTO_GROUP_KEY	include/hal.h	76;"	d
+HAL_SET_BCN_ID_DTIM	include/hal.h	147;"	d
+HAL_SET_BCN_IFNO	include/hal.h	152;"	d
+HAL_SET_BEACON_REG_LOCK	include/hal.h	145;"	d
+HAL_SET_BSSID	include/hal.h	49;"	d
+HAL_SET_CHANNEL	include/hal.h	329;"	d
+HAL_SET_CHANNEL	smac/dev.h	1033;"	d
+HAL_SET_DUR_BURST_SIFS_G	include/hal.h	126;"	d
+HAL_SET_DUR_SLOT	include/hal.h	128;"	d
+HAL_SET_FW_HWWSID_SEC_TYPE	include/hal.h	64;"	d
+HAL_SET_GROUP_CIPHER_TYPE	include/hal.h	88;"	d
+HAL_SET_HW_WSID	include/hal.h	57;"	d
+HAL_SET_MACADDR	include/hal.h	48;"	d
+HAL_SET_MRX_MODE	include/hal.h	121;"	d
+HAL_SET_ON3_ENABLE	include/hal.h	339;"	d
+HAL_SET_OP_MODE	include/hal.h	123;"	d
+HAL_SET_PAIRWISE_CIPHER_TYPE	include/hal.h	90;"	d
+HAL_SET_PHY_MODE	include/hal.h	280;"	d
+HAL_SET_PLL_PHY_RF	include/hal.h	331;"	d
+HAL_SET_QOS_ENABLE	include/hal.h	130;"	d
+HAL_SET_REPLAY_IGNORE	include/hal.h	114;"	d
+HAL_SET_RF_ENABLE	include/hal.h	338;"	d
+HAL_SET_RX_BA	include/hal.h	140;"	d
+HAL_SET_RX_CTRL_FLOW	include/hal.h	47;"	d
+HAL_SET_RX_FLOW	include/hal.h	45;"	d
+HAL_SET_SIFS	include/hal.h	129;"	d
+HAL_SET_SRAM_MODE	include/hal.h	228;"	d
+HAL_SET_USB_LPM	include/hal.h	231;"	d
+HAL_SET_WEP_HW_CRYPTO_KEY	include/hal.h	100;"	d
+HAL_SET_WMM_PARAM	include/hal.h	131;"	d
+HAL_STORE_WEP_KEY	include/hal.h	102;"	d
+HAL_SUPPORT_IQK_CMD	include/hal.h	189;"	d
+HAL_TXTPUT_SET_DESC	include/hal.h	254;"	d
+HAL_TX_RATE_UPDATE	include/hal.h	253;"	d
+HAL_UPDATE_AMPDU_TXINFO	include/hal.h	240;"	d
+HAL_UPDATE_CFG_HW_PATCH	include/hal.h	319;"	d
+HAL_UPDATE_DECISION_TABLE	include/hal.h	118;"	d
+HAL_UPDATE_DECISION_TABLE_6	include/hal.h	116;"	d
+HAL_UPDATE_EFUSE_SETTING	include/hal.h	325;"	d
+HAL_UPDATE_HW_CONFIG	include/hal.h	321;"	d
+HAL_UPDATE_NULL_FUNC_TXINFO	include/hal.h	244;"	d
+HAL_UPDATE_PAGE_ID	include/hal.h	133;"	d
+HAL_UPDATE_PRODUCT_HW_SETTING	include/hal.h	328;"	d
+HAL_UPDATE_RF_PWR	include/hal.h	305;"	d
+HAL_UPDATE_RXSTATUS	include/hal.h	289;"	d
+HAL_UPDATE_SCAN_CCI_SETTING	include/hal.h	292;"	d
+HAL_UPDATE_TXINFO	include/hal.h	239;"	d
+HAL_UPDATE_TXQ_MASK	include/hal.h	159;"	d
+HAL_USE_HW_ENCRYPT	include/hal.h	43;"	d
+HAL_WAIT_USB_ROM_READY	include/hal.h	236;"	d
+HAL_WEP_USE_HW_CIPHER	include/hal.h	70;"	d
+HAL_WRITE_EFUSE	include/hal.h	143;"	d
+HAL_WRITE_GROUP_KEYIDX_TO_HW	include/hal.h	80;"	d
+HAL_WRITE_GROUP_KEY_TO_HW	include/hal.h	84;"	d
+HAL_WRITE_KEY_TO_HW	include/hal.h	86;"	d
+HAL_WRITE_MAC_INI	include/hal.h	42;"	d
+HAL_WRITE_PAIRWISE_KEYIDX_TO_HW	include/hal.h	78;"	d
+HAL_WRITE_PAIRWISE_KEY_TO_HW	include/hal.h	82;"	d
+HAS_CRYPTO_LOCK	include/ssv_mod_conf.h	64;"	d
+HAS_MANUAL_BUF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5314;"	d
+HAS_MANUAL_BUF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5312;"	d
+HAS_MANUAL_BUF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5311;"	d
+HAS_MANUAL_BUF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5313;"	d
+HAS_MANUAL_BUF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5315;"	d
+HBURST_LOCK_HI	include/ssv6200_aux.h	544;"	d
+HBURST_LOCK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1444;"	d
+HBURST_LOCK_I_MSK	include/ssv6200_aux.h	542;"	d
+HBURST_LOCK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1442;"	d
+HBURST_LOCK_MSK	include/ssv6200_aux.h	541;"	d
+HBURST_LOCK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1441;"	d
+HBURST_LOCK_SFT	include/ssv6200_aux.h	543;"	d
+HBURST_LOCK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1443;"	d
+HBURST_LOCK_SZ	include/ssv6200_aux.h	545;"	d
+HBURST_LOCK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1445;"	d
+HBUSREQ_LOCK_HI	include/ssv6200_aux.h	539;"	d
+HBUSREQ_LOCK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1439;"	d
+HBUSREQ_LOCK_I_MSK	include/ssv6200_aux.h	537;"	d
+HBUSREQ_LOCK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1437;"	d
+HBUSREQ_LOCK_MSK	include/ssv6200_aux.h	536;"	d
+HBUSREQ_LOCK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1436;"	d
+HBUSREQ_LOCK_SFT	include/ssv6200_aux.h	538;"	d
+HBUSREQ_LOCK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1438;"	d
+HBUSREQ_LOCK_SZ	include/ssv6200_aux.h	540;"	d
+HBUSREQ_LOCK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1440;"	d
+HCI_BULK_IN_HOST_SIZE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5389;"	d
+HCI_BULK_IN_HOST_SIZE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5387;"	d
+HCI_BULK_IN_HOST_SIZE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5386;"	d
+HCI_BULK_IN_HOST_SIZE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5388;"	d
+HCI_BULK_IN_HOST_SIZE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5390;"	d
+HCI_BULK_IN_TIME_OUT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5394;"	d
+HCI_BULK_IN_TIME_OUT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5392;"	d
+HCI_BULK_IN_TIME_OUT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5391;"	d
+HCI_BULK_IN_TIME_OUT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5393;"	d
+HCI_BULK_IN_TIME_OUT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5395;"	d
+HCI_BURST_REG_READ	hci/hctrl.h	34;"	d
+HCI_BURST_REG_SAFE_READ	hci/hctrl.h	36;"	d
+HCI_BURST_REG_SAFE_WRITE	hci/hctrl.h	37;"	d
+HCI_BURST_REG_WRITE	hci/hctrl.h	35;"	d
+HCI_CLK_EN_HI	include/ssv6200_aux.h	8984;"	d
+HCI_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8739;"	d
+HCI_CLK_EN_I_MSK	include/ssv6200_aux.h	8982;"	d
+HCI_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8737;"	d
+HCI_CLK_EN_MSK	include/ssv6200_aux.h	8981;"	d
+HCI_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8736;"	d
+HCI_CLK_EN_SFT	include/ssv6200_aux.h	8983;"	d
+HCI_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8738;"	d
+HCI_CLK_EN_SZ	include/ssv6200_aux.h	8985;"	d
+HCI_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8740;"	d
+HCI_DBG_PRINT	hci/ssv_hci.h	40;"	d
+HCI_DEVICE_TYPE	hci/hctrl.h	254;"	d
+HCI_ENG_CLK_EN_HI	include/ssv6200_aux.h	9044;"	d
+HCI_ENG_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8799;"	d
+HCI_ENG_CLK_EN_I_MSK	include/ssv6200_aux.h	9042;"	d
+HCI_ENG_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8797;"	d
+HCI_ENG_CLK_EN_MSK	include/ssv6200_aux.h	9041;"	d
+HCI_ENG_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8796;"	d
+HCI_ENG_CLK_EN_SFT	include/ssv6200_aux.h	9043;"	d
+HCI_ENG_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8798;"	d
+HCI_ENG_CLK_EN_SZ	include/ssv6200_aux.h	9045;"	d
+HCI_ENG_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8800;"	d
+HCI_FLAGS_ENQUEUE_HEAD	hci/ssv_hci.h	38;"	d
+HCI_FLAGS_NO_FLOWCTRL	hci/ssv_hci.h	39;"	d
+HCI_HWIF_PROPERTY	hci/hctrl.h	245;"	d
+HCI_HWIF_READY	hci/hctrl.h	244;"	d
+HCI_IFC_RESET	hci/hctrl.h	249;"	d
+HCI_INPUT_FF_CNT2_HI	include/ssv6200_aux.h	3594;"	d
+HCI_INPUT_FF_CNT2_I_MSK	include/ssv6200_aux.h	3592;"	d
+HCI_INPUT_FF_CNT2_MSK	include/ssv6200_aux.h	3591;"	d
+HCI_INPUT_FF_CNT2_SFT	include/ssv6200_aux.h	3593;"	d
+HCI_INPUT_FF_CNT2_SZ	include/ssv6200_aux.h	3595;"	d
+HCI_INPUT_FF_CNT_HI	include/ssv6200_aux.h	3239;"	d
+HCI_INPUT_FF_CNT_I_MSK	include/ssv6200_aux.h	3237;"	d
+HCI_INPUT_FF_CNT_MSK	include/ssv6200_aux.h	3236;"	d
+HCI_INPUT_FF_CNT_SFT	include/ssv6200_aux.h	3238;"	d
+HCI_INPUT_FF_CNT_SZ	include/ssv6200_aux.h	3240;"	d
+HCI_INPUT_QUEUE_FULL_HI	include/ssv6200_aux.h	3529;"	d
+HCI_INPUT_QUEUE_FULL_I_MSK	include/ssv6200_aux.h	3527;"	d
+HCI_INPUT_QUEUE_FULL_MSK	include/ssv6200_aux.h	3526;"	d
+HCI_INPUT_QUEUE_FULL_SFT	include/ssv6200_aux.h	3528;"	d
+HCI_INPUT_QUEUE_FULL_SZ	include/ssv6200_aux.h	3530;"	d
+HCI_INQ_SEL_HI	include/ssv6200_aux.h	6119;"	d
+HCI_INQ_SEL_I_MSK	include/ssv6200_aux.h	6117;"	d
+HCI_INQ_SEL_MSK	include/ssv6200_aux.h	6116;"	d
+HCI_INQ_SEL_SFT	include/ssv6200_aux.h	6118;"	d
+HCI_INQ_SEL_SZ	include/ssv6200_aux.h	6120;"	d
+HCI_INT_1_HI	include/ssv6200_aux.h	4979;"	d
+HCI_INT_1_I_MSK	include/ssv6200_aux.h	4977;"	d
+HCI_INT_1_MSK	include/ssv6200_aux.h	4976;"	d
+HCI_INT_1_SD_HI	include/ssv6200_aux.h	5324;"	d
+HCI_INT_1_SD_I_MSK	include/ssv6200_aux.h	5322;"	d
+HCI_INT_1_SD_MSK	include/ssv6200_aux.h	5321;"	d
+HCI_INT_1_SD_SFT	include/ssv6200_aux.h	5323;"	d
+HCI_INT_1_SD_SZ	include/ssv6200_aux.h	5325;"	d
+HCI_INT_1_SFT	include/ssv6200_aux.h	4978;"	d
+HCI_INT_1_SZ	include/ssv6200_aux.h	4980;"	d
+HCI_IN_QUE_EMPTY2_HI	include/ssv6200_aux.h	3544;"	d
+HCI_IN_QUE_EMPTY2_I_MSK	include/ssv6200_aux.h	3542;"	d
+HCI_IN_QUE_EMPTY2_MSK	include/ssv6200_aux.h	3541;"	d
+HCI_IN_QUE_EMPTY2_SFT	include/ssv6200_aux.h	3543;"	d
+HCI_IN_QUE_EMPTY2_SZ	include/ssv6200_aux.h	3545;"	d
+HCI_IN_QUE_EMPTY_HI	include/ssv6200_aux.h	3254;"	d
+HCI_IN_QUE_EMPTY_I_MSK	include/ssv6200_aux.h	3252;"	d
+HCI_IN_QUE_EMPTY_MSK	include/ssv6200_aux.h	3251;"	d
+HCI_IN_QUE_EMPTY_SFT	include/ssv6200_aux.h	3253;"	d
+HCI_IN_QUE_EMPTY_SZ	include/ssv6200_aux.h	3255;"	d
+HCI_IRQ_DISABLE	hci/hctrl.h	238;"	d
+HCI_IRQ_ENABLE	hci/hctrl.h	237;"	d
+HCI_IRQ_REQUEST	hci/hctrl.h	236;"	d
+HCI_IRQ_SET_MASK	hci/hctrl.h	240;"	d
+HCI_IRQ_STATUS	hci/hctrl.h	239;"	d
+HCI_IRQ_TRIGGER	hci/hctrl.h	241;"	d
+HCI_JUMP_TO_ROM	hci/hctrl.h	252;"	d
+HCI_LOAD_FW	hci/hctrl.h	48;"	d
+HCI_LOAD_FW_POST_CONFIG_DEVICE	hci/hctrl.h	247;"	d
+HCI_LOAD_FW_PRE_CONFIG_DEVICE	hci/hctrl.h	246;"	d
+HCI_MB_MAX_CNT_HI	include/ssv6200_aux.h	6299;"	d
+HCI_MB_MAX_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5429;"	d
+HCI_MB_MAX_CNT_I_MSK	include/ssv6200_aux.h	6297;"	d
+HCI_MB_MAX_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5427;"	d
+HCI_MB_MAX_CNT_MSK	include/ssv6200_aux.h	6296;"	d
+HCI_MB_MAX_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5426;"	d
+HCI_MB_MAX_CNT_SFT	include/ssv6200_aux.h	6298;"	d
+HCI_MB_MAX_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5428;"	d
+HCI_MB_MAX_CNT_SZ	include/ssv6200_aux.h	6300;"	d
+HCI_MB_MAX_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5430;"	d
+HCI_MONITOR_REG0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5399;"	d
+HCI_MONITOR_REG0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5397;"	d
+HCI_MONITOR_REG0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5396;"	d
+HCI_MONITOR_REG0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5398;"	d
+HCI_MONITOR_REG0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5400;"	d
+HCI_MONITOR_REG1_HI	include/ssv6200_aux.h	6279;"	d
+HCI_MONITOR_REG1_I_MSK	include/ssv6200_aux.h	6277;"	d
+HCI_MONITOR_REG1_MSK	include/ssv6200_aux.h	6276;"	d
+HCI_MONITOR_REG1_SFT	include/ssv6200_aux.h	6278;"	d
+HCI_MONITOR_REG1_SZ	include/ssv6200_aux.h	6280;"	d
+HCI_MONITOR_REG2_HI	include/ssv6200_aux.h	6284;"	d
+HCI_MONITOR_REG2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5404;"	d
+HCI_MONITOR_REG2_I_MSK	include/ssv6200_aux.h	6282;"	d
+HCI_MONITOR_REG2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5402;"	d
+HCI_MONITOR_REG2_MSK	include/ssv6200_aux.h	6281;"	d
+HCI_MONITOR_REG2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5401;"	d
+HCI_MONITOR_REG2_SFT	include/ssv6200_aux.h	6283;"	d
+HCI_MONITOR_REG2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5403;"	d
+HCI_MONITOR_REG2_SZ	include/ssv6200_aux.h	6285;"	d
+HCI_MONITOR_REG2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5405;"	d
+HCI_MONITOR_REG3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5409;"	d
+HCI_MONITOR_REG3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5407;"	d
+HCI_MONITOR_REG3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5406;"	d
+HCI_MONITOR_REG3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5408;"	d
+HCI_MONITOR_REG3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5410;"	d
+HCI_MONITOR_REG4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5414;"	d
+HCI_MONITOR_REG4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5412;"	d
+HCI_MONITOR_REG4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5411;"	d
+HCI_MONITOR_REG4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5413;"	d
+HCI_MONITOR_REG4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5415;"	d
+HCI_MONITOR_REG5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5419;"	d
+HCI_MONITOR_REG5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5417;"	d
+HCI_MONITOR_REG5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5416;"	d
+HCI_MONITOR_REG5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5418;"	d
+HCI_MONITOR_REG5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5420;"	d
+HCI_OUTPUT_FF_CNT2_HI	include/ssv6200_aux.h	3589;"	d
+HCI_OUTPUT_FF_CNT2_I_MSK	include/ssv6200_aux.h	3587;"	d
+HCI_OUTPUT_FF_CNT2_MSK	include/ssv6200_aux.h	3586;"	d
+HCI_OUTPUT_FF_CNT2_SFT	include/ssv6200_aux.h	3588;"	d
+HCI_OUTPUT_FF_CNT2_SZ	include/ssv6200_aux.h	3590;"	d
+HCI_OUTPUT_FF_CNT_0_HI	include/ssv6200_aux.h	3584;"	d
+HCI_OUTPUT_FF_CNT_0_I_MSK	include/ssv6200_aux.h	3582;"	d
+HCI_OUTPUT_FF_CNT_0_MSK	include/ssv6200_aux.h	3581;"	d
+HCI_OUTPUT_FF_CNT_0_SFT	include/ssv6200_aux.h	3583;"	d
+HCI_OUTPUT_FF_CNT_0_SZ	include/ssv6200_aux.h	3585;"	d
+HCI_OUTPUT_FF_CNT_HI	include/ssv6200_aux.h	3244;"	d
+HCI_OUTPUT_FF_CNT_I_MSK	include/ssv6200_aux.h	3242;"	d
+HCI_OUTPUT_FF_CNT_MSK	include/ssv6200_aux.h	3241;"	d
+HCI_OUTPUT_FF_CNT_SFT	include/ssv6200_aux.h	3243;"	d
+HCI_OUTPUT_FF_CNT_SZ	include/ssv6200_aux.h	3245;"	d
+HCI_PAUSE	hci_wrapper/ssv_huw.c	50;"	d	file:
+HCI_PAUSE	smac/dev.h	231;"	d
+HCI_PENDING_RX_MPDU_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5364;"	d
+HCI_PENDING_RX_MPDU_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5362;"	d
+HCI_PENDING_RX_MPDU_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5361;"	d
+HCI_PENDING_RX_MPDU_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5363;"	d
+HCI_PENDING_RX_MPDU_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5365;"	d
+HCI_PMU_WAKEUP	hci/hctrl.h	242;"	d
+HCI_PROC_CNT_HI	include/ssv6200_aux.h	6314;"	d
+HCI_PROC_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5434;"	d
+HCI_PROC_CNT_I_MSK	include/ssv6200_aux.h	6312;"	d
+HCI_PROC_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5432;"	d
+HCI_PROC_CNT_MSK	include/ssv6200_aux.h	6311;"	d
+HCI_PROC_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5431;"	d
+HCI_PROC_CNT_SFT	include/ssv6200_aux.h	6313;"	d
+HCI_PROC_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5433;"	d
+HCI_PROC_CNT_SZ	include/ssv6200_aux.h	6315;"	d
+HCI_PROC_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5435;"	d
+HCI_REG_BANK_SIZE	include/ssv6200_reg.h	91;"	d
+HCI_REG_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	108;"	d
+HCI_REG_BASE	include/ssv6200_reg.h	42;"	d
+HCI_REG_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	47;"	d
+HCI_REG_READ	hci/hctrl.h	30;"	d
+HCI_REG_SAFE_READ	hci/hctrl.h	32;"	d
+HCI_REG_SAFE_WRITE	hci/hctrl.h	33;"	d
+HCI_REG_SET_BITS	hci/hctrl.h	38;"	d
+HCI_REG_WRITE	hci/hctrl.h	31;"	d
+HCI_RESUME	hci_wrapper/ssv_huw.c	52;"	d	file:
+HCI_RESUME	smac/dev.h	236;"	d
+HCI_RX_AGGR_SIZE	include/ssv6xxx_common.h	24;"	d
+HCI_RX_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5174;"	d
+HCI_RX_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5172;"	d
+HCI_RX_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5171;"	d
+HCI_RX_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5173;"	d
+HCI_RX_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5175;"	d
+HCI_RX_FORM_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5184;"	d
+HCI_RX_FORM_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5182;"	d
+HCI_RX_FORM_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5181;"	d
+HCI_RX_FORM_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5183;"	d
+HCI_RX_FORM_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5185;"	d
+HCI_RX_FORM_1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5179;"	d
+HCI_RX_FORM_1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5177;"	d
+HCI_RX_FORM_1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5176;"	d
+HCI_RX_FORM_1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5178;"	d
+HCI_RX_FORM_1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5180;"	d
+HCI_RX_HALT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5369;"	d
+HCI_RX_HALT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5367;"	d
+HCI_RX_HALT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5366;"	d
+HCI_RX_HALT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5368;"	d
+HCI_RX_HALT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5370;"	d
+HCI_RX_LEN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5214;"	d
+HCI_RX_LEN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5212;"	d
+HCI_RX_LEN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5211;"	d
+HCI_RX_LEN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5213;"	d
+HCI_RX_LEN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5215;"	d
+HCI_RX_MPDU_DEQUE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5384;"	d
+HCI_RX_MPDU_DEQUE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5382;"	d
+HCI_RX_MPDU_DEQUE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5381;"	d
+HCI_RX_MPDU_DEQUE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5383;"	d
+HCI_RX_MPDU_DEQUE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5385;"	d
+HCI_RX_TASK	hci/hctrl.h	248;"	d
+HCI_SEND	hci_wrapper/ssv_huw.c	48;"	d	file:
+HCI_SEND	smac/dev.h	226;"	d
+HCI_SEND_CMD	hci_wrapper/ssv_huw.c	62;"	d	file:
+HCI_SEND_CMD	smac/dev.h	261;"	d
+HCI_SRAM_WRITE	hci/hctrl.h	243;"	d
+HCI_START	hci_wrapper/ssv_huw.c	44;"	d	file:
+HCI_START	smac/dev.h	206;"	d
+HCI_START_USB_ACC	hci/hctrl.h	250;"	d
+HCI_STATE_MONITOR_HI	include/ssv6200_aux.h	6264;"	d
+HCI_STATE_MONITOR_I_MSK	include/ssv6200_aux.h	6262;"	d
+HCI_STATE_MONITOR_MSK	include/ssv6200_aux.h	6261;"	d
+HCI_STATE_MONITOR_SFT	include/ssv6200_aux.h	6263;"	d
+HCI_STATE_MONITOR_SZ	include/ssv6200_aux.h	6265;"	d
+HCI_STOP	hci_wrapper/ssv_huw.c	46;"	d	file:
+HCI_STOP	smac/dev.h	211;"	d
+HCI_STOP_USB_ACC	hci/hctrl.h	251;"	d
+HCI_ST_TIMEOUT_MONITOR_HI	include/ssv6200_aux.h	6269;"	d
+HCI_ST_TIMEOUT_MONITOR_I_MSK	include/ssv6200_aux.h	6267;"	d
+HCI_ST_TIMEOUT_MONITOR_MSK	include/ssv6200_aux.h	6266;"	d
+HCI_ST_TIMEOUT_MONITOR_SFT	include/ssv6200_aux.h	6268;"	d
+HCI_ST_TIMEOUT_MONITOR_SZ	include/ssv6200_aux.h	6270;"	d
+HCI_SW_RST_HI	include/ssv6200_aux.h	8799;"	d
+HCI_SW_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8549;"	d
+HCI_SW_RST_I_MSK	include/ssv6200_aux.h	8797;"	d
+HCI_SW_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8547;"	d
+HCI_SW_RST_MSK	include/ssv6200_aux.h	8796;"	d
+HCI_SW_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8546;"	d
+HCI_SW_RST_SFT	include/ssv6200_aux.h	8798;"	d
+HCI_SW_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8548;"	d
+HCI_SW_RST_SZ	include/ssv6200_aux.h	8800;"	d
+HCI_SW_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8550;"	d
+HCI_SYSPLF_RESET	hci/hctrl.h	253;"	d
+HCI_TRX_FINISH2_HI	include/ssv6200_aux.h	3519;"	d
+HCI_TRX_FINISH2_I_MSK	include/ssv6200_aux.h	3517;"	d
+HCI_TRX_FINISH2_MSK	include/ssv6200_aux.h	3516;"	d
+HCI_TRX_FINISH2_SFT	include/ssv6200_aux.h	3518;"	d
+HCI_TRX_FINISH2_SZ	include/ssv6200_aux.h	3520;"	d
+HCI_TRX_FINISH3_HI	include/ssv6200_aux.h	3539;"	d
+HCI_TRX_FINISH3_I_MSK	include/ssv6200_aux.h	3537;"	d
+HCI_TRX_FINISH3_MSK	include/ssv6200_aux.h	3536;"	d
+HCI_TRX_FINISH3_SFT	include/ssv6200_aux.h	3538;"	d
+HCI_TRX_FINISH3_SZ	include/ssv6200_aux.h	3540;"	d
+HCI_TRX_FINISH_HI	include/ssv6200_aux.h	3229;"	d
+HCI_TRX_FINISH_I_MSK	include/ssv6200_aux.h	3227;"	d
+HCI_TRX_FINISH_MSK	include/ssv6200_aux.h	3226;"	d
+HCI_TRX_FINISH_SFT	include/ssv6200_aux.h	3228;"	d
+HCI_TRX_FINISH_SZ	include/ssv6200_aux.h	3230;"	d
+HCI_TXQ_EMPTY	hci_wrapper/ssv_huw.c	58;"	d	file:
+HCI_TXQ_EMPTY	smac/dev.h	251;"	d
+HCI_TXQ_FLUSH	hci_wrapper/ssv_huw.c	54;"	d	file:
+HCI_TXQ_FLUSH	smac/dev.h	241;"	d
+HCI_TXQ_FLUSH_BY_STA	hci_wrapper/ssv_huw.c	56;"	d	file:
+HCI_TXQ_FLUSH_BY_STA	smac/dev.h	246;"	d
+HCI_TX_AGG_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5169;"	d
+HCI_TX_AGG_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5167;"	d
+HCI_TX_AGG_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5166;"	d
+HCI_TX_AGG_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5168;"	d
+HCI_TX_AGG_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5170;"	d
+HCI_TX_ALLOC_CNT_31_0_HI	include/ssv6200_aux.h	6304;"	d
+HCI_TX_ALLOC_CNT_31_0_I_MSK	include/ssv6200_aux.h	6302;"	d
+HCI_TX_ALLOC_CNT_31_0_MSK	include/ssv6200_aux.h	6301;"	d
+HCI_TX_ALLOC_CNT_31_0_SFT	include/ssv6200_aux.h	6303;"	d
+HCI_TX_ALLOC_CNT_31_0_SZ	include/ssv6200_aux.h	6305;"	d
+HCI_TX_ALLOC_CNT_47_32_HI	include/ssv6200_aux.h	6309;"	d
+HCI_TX_ALLOC_CNT_47_32_I_MSK	include/ssv6200_aux.h	6307;"	d
+HCI_TX_ALLOC_CNT_47_32_MSK	include/ssv6200_aux.h	6306;"	d
+HCI_TX_ALLOC_CNT_47_32_SFT	include/ssv6200_aux.h	6308;"	d
+HCI_TX_ALLOC_CNT_47_32_SZ	include/ssv6200_aux.h	6310;"	d
+HCI_TX_ALLOC_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5449;"	d
+HCI_TX_ALLOC_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5447;"	d
+HCI_TX_ALLOC_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5446;"	d
+HCI_TX_ALLOC_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5448;"	d
+HCI_TX_ALLOC_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5450;"	d
+HCI_TX_ALLOC_TIME_31_0_HI	include/ssv6200_aux.h	6289;"	d
+HCI_TX_ALLOC_TIME_31_0_I_MSK	include/ssv6200_aux.h	6287;"	d
+HCI_TX_ALLOC_TIME_31_0_MSK	include/ssv6200_aux.h	6286;"	d
+HCI_TX_ALLOC_TIME_31_0_SFT	include/ssv6200_aux.h	6288;"	d
+HCI_TX_ALLOC_TIME_31_0_SZ	include/ssv6200_aux.h	6290;"	d
+HCI_TX_ALLOC_TIME_47_32_HI	include/ssv6200_aux.h	6294;"	d
+HCI_TX_ALLOC_TIME_47_32_I_MSK	include/ssv6200_aux.h	6292;"	d
+HCI_TX_ALLOC_TIME_47_32_MSK	include/ssv6200_aux.h	6291;"	d
+HCI_TX_ALLOC_TIME_47_32_SFT	include/ssv6200_aux.h	6293;"	d
+HCI_TX_ALLOC_TIME_47_32_SZ	include/ssv6200_aux.h	6295;"	d
+HCI_TX_ALLOC_TIME_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5454;"	d
+HCI_TX_ALLOC_TIME_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5452;"	d
+HCI_TX_ALLOC_TIME_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5451;"	d
+HCI_TX_ALLOC_TIME_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5453;"	d
+HCI_TX_ALLOC_TIME_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5455;"	d
+HCI_WAKEUP_PMU	hci_wrapper/ssv_huw.c	60;"	d	file:
+HCI_WAKEUP_PMU	smac/dev.h	256;"	d
+HCI_WRITE_HW_CONFIG_OFF	smac/dev.h	221;"	d
+HCI_WRITE_HW_CONFIG_ON	smac/dev.h	216;"	d
+HDR_HostCmd	include/ssv6xxx_common.h	/^} HDR_HostCmd;$/;"	t	typeref:struct:cfg_host_cmd
+HDR_HostEvent	include/ssv6xxx_common.h	/^} HDR_HostEvent;$/;"	t	typeref:struct:cfg_host_event
+HDR_STRIP_HI	include/ssv6200_aux.h	6074;"	d
+HDR_STRIP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5124;"	d
+HDR_STRIP_I_MSK	include/ssv6200_aux.h	6072;"	d
+HDR_STRIP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5122;"	d
+HDR_STRIP_MSK	include/ssv6200_aux.h	6071;"	d
+HDR_STRIP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5121;"	d
+HDR_STRIP_SFT	include/ssv6200_aux.h	6073;"	d
+HDR_STRIP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5123;"	d
+HDR_STRIP_SZ	include/ssv6200_aux.h	6075;"	d
+HDR_STRIP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5125;"	d
+HIF_INFO_BANK_SIZE	include/ssv6200_reg.h	103;"	d
+HIF_INFO_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	124;"	d
+HIF_INFO_BASE	include/ssv6200_reg.h	54;"	d
+HIF_INFO_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	63;"	d
+HIF_LOOP_BACK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5374;"	d
+HIF_LOOP_BACK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5372;"	d
+HIF_LOOP_BACK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5371;"	d
+HIF_LOOP_BACK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5373;"	d
+HIF_LOOP_BACK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5375;"	d
+HIGH_SPEED_SDIO_CLOCK	hwif/sdio/sdio.c	42;"	d	file:
+HOST_CMD	include/ssv6xxx_common.h	69;"	d
+HOST_CMD	smac/hal/ssv6006c/ssv6006_common.h	55;"	d
+HOST_CMD_COUNTER_HI	include/ssv6200_aux.h	6224;"	d
+HOST_CMD_COUNTER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5484;"	d
+HOST_CMD_COUNTER_I_MSK	include/ssv6200_aux.h	6222;"	d
+HOST_CMD_COUNTER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5482;"	d
+HOST_CMD_COUNTER_MSK	include/ssv6200_aux.h	6221;"	d
+HOST_CMD_COUNTER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5481;"	d
+HOST_CMD_COUNTER_SFT	include/ssv6200_aux.h	6223;"	d
+HOST_CMD_COUNTER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5483;"	d
+HOST_CMD_COUNTER_SZ	include/ssv6200_aux.h	6225;"	d
+HOST_CMD_COUNTER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5485;"	d
+HOST_CMD_DUMMY_LEN	include/ssv6xxx_common.h	102;"	d
+HOST_CMD_HDR_LEN	include/ssv6xxx_common.h	101;"	d
+HOST_EVENT	include/ssv6xxx_common.h	70;"	d
+HOST_EVENT	smac/hal/ssv6006c/ssv6006_common.h	56;"	d
+HOST_EVENT_COUNTER_HI	include/ssv6200_aux.h	6229;"	d
+HOST_EVENT_COUNTER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5479;"	d
+HOST_EVENT_COUNTER_I_MSK	include/ssv6200_aux.h	6227;"	d
+HOST_EVENT_COUNTER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5477;"	d
+HOST_EVENT_COUNTER_MSK	include/ssv6200_aux.h	6226;"	d
+HOST_EVENT_COUNTER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5476;"	d
+HOST_EVENT_COUNTER_SFT	include/ssv6200_aux.h	6228;"	d
+HOST_EVENT_COUNTER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5478;"	d
+HOST_EVENT_COUNTER_SZ	include/ssv6200_aux.h	6230;"	d
+HOST_EVENT_COUNTER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5480;"	d
+HOST_EVENT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1569;"	d
+HOST_EVENT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1567;"	d
+HOST_EVENT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1566;"	d
+HOST_EVENT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1568;"	d
+HOST_EVENT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1570;"	d
+HOST_PATH_HI	include/ssv6200_aux.h	3939;"	d
+HOST_PATH_I_MSK	include/ssv6200_aux.h	3937;"	d
+HOST_PATH_MSK	include/ssv6200_aux.h	3936;"	d
+HOST_PATH_SFT	include/ssv6200_aux.h	3938;"	d
+HOST_PATH_SZ	include/ssv6200_aux.h	3940;"	d
+HOST_RX_FAIL_COUNTER_HI	include/ssv6200_aux.h	6259;"	d
+HOST_RX_FAIL_COUNTER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5499;"	d
+HOST_RX_FAIL_COUNTER_I_MSK	include/ssv6200_aux.h	6257;"	d
+HOST_RX_FAIL_COUNTER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5497;"	d
+HOST_RX_FAIL_COUNTER_MSK	include/ssv6200_aux.h	6256;"	d
+HOST_RX_FAIL_COUNTER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5496;"	d
+HOST_RX_FAIL_COUNTER_SFT	include/ssv6200_aux.h	6258;"	d
+HOST_RX_FAIL_COUNTER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5498;"	d
+HOST_RX_FAIL_COUNTER_SZ	include/ssv6200_aux.h	6260;"	d
+HOST_RX_FAIL_COUNTER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5500;"	d
+HOST_TRIGGERED_RX_INT_HI	include/ssv6200_aux.h	3119;"	d
+HOST_TRIGGERED_RX_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2589;"	d
+HOST_TRIGGERED_RX_INT_I_MSK	include/ssv6200_aux.h	3117;"	d
+HOST_TRIGGERED_RX_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2587;"	d
+HOST_TRIGGERED_RX_INT_MSK	include/ssv6200_aux.h	3116;"	d
+HOST_TRIGGERED_RX_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2586;"	d
+HOST_TRIGGERED_RX_INT_SFT	include/ssv6200_aux.h	3118;"	d
+HOST_TRIGGERED_RX_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2588;"	d
+HOST_TRIGGERED_RX_INT_SZ	include/ssv6200_aux.h	3120;"	d
+HOST_TRIGGERED_RX_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2590;"	d
+HOST_TRIGGERED_TX_INT_HI	include/ssv6200_aux.h	3124;"	d
+HOST_TRIGGERED_TX_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2594;"	d
+HOST_TRIGGERED_TX_INT_I_MSK	include/ssv6200_aux.h	3122;"	d
+HOST_TRIGGERED_TX_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2592;"	d
+HOST_TRIGGERED_TX_INT_MSK	include/ssv6200_aux.h	3121;"	d
+HOST_TRIGGERED_TX_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2591;"	d
+HOST_TRIGGERED_TX_INT_SFT	include/ssv6200_aux.h	3123;"	d
+HOST_TRIGGERED_TX_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2593;"	d
+HOST_TRIGGERED_TX_INT_SZ	include/ssv6200_aux.h	3125;"	d
+HOST_TRIGGERED_TX_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2595;"	d
+HOST_TX_FAIL_COUNTER_HI	include/ssv6200_aux.h	6254;"	d
+HOST_TX_FAIL_COUNTER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5504;"	d
+HOST_TX_FAIL_COUNTER_I_MSK	include/ssv6200_aux.h	6252;"	d
+HOST_TX_FAIL_COUNTER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5502;"	d
+HOST_TX_FAIL_COUNTER_MSK	include/ssv6200_aux.h	6251;"	d
+HOST_TX_FAIL_COUNTER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5501;"	d
+HOST_TX_FAIL_COUNTER_SFT	include/ssv6200_aux.h	6253;"	d
+HOST_TX_FAIL_COUNTER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5503;"	d
+HOST_TX_FAIL_COUNTER_SZ	include/ssv6200_aux.h	6255;"	d
+HOST_TX_FAIL_COUNTER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5505;"	d
+HOST_WAKE_WIFI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1764;"	d
+HOST_WAKE_WIFI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1762;"	d
+HOST_WAKE_WIFI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1761;"	d
+HOST_WAKE_WIFI_POL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1769;"	d
+HOST_WAKE_WIFI_POL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1767;"	d
+HOST_WAKE_WIFI_POL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1766;"	d
+HOST_WAKE_WIFI_POL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1768;"	d
+HOST_WAKE_WIFI_POL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1770;"	d
+HOST_WAKE_WIFI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1763;"	d
+HOST_WAKE_WIFI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1765;"	d
+HOUSE_KEEPING_10_SEC	smac/dev.h	180;"	d
+HOUSE_KEEPING_1_SEC	smac/dev.h	179;"	d
+HOUSE_KEEPING_TIMEOUT	smac/dev.h	177;"	d
+HSUART_ACTS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3819;"	d
+HSUART_ACTS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3817;"	d
+HSUART_ACTS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3816;"	d
+HSUART_ACTS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3818;"	d
+HSUART_ACTS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3820;"	d
+HSUART_ARTS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3814;"	d
+HSUART_ARTS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3812;"	d
+HSUART_ARTS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3811;"	d
+HSUART_ARTS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3813;"	d
+HSUART_ARTS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3815;"	d
+HSUART_BI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3844;"	d
+HSUART_BI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3842;"	d
+HSUART_BI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3841;"	d
+HSUART_BI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3843;"	d
+HSUART_BI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3845;"	d
+HSUART_CTS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3884;"	d
+HSUART_CTS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3882;"	d
+HSUART_CTS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3881;"	d
+HSUART_CTS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3883;"	d
+HSUART_CTS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3885;"	d
+HSUART_DCR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3899;"	d
+HSUART_DCR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3897;"	d
+HSUART_DCR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3896;"	d
+HSUART_DCR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3898;"	d
+HSUART_DCR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3900;"	d
+HSUART_DCTS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3864;"	d
+HSUART_DCTS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3862;"	d
+HSUART_DCTS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3861;"	d
+HSUART_DCTS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3863;"	d
+HSUART_DCTS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3865;"	d
+HSUART_DDCD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3879;"	d
+HSUART_DDCD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3877;"	d
+HSUART_DDCD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3876;"	d
+HSUART_DDCD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3878;"	d
+HSUART_DDCD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3880;"	d
+HSUART_DDSR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3869;"	d
+HSUART_DDSR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3867;"	d
+HSUART_DDSR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3866;"	d
+HSUART_DDSR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3868;"	d
+HSUART_DDSR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3870;"	d
+HSUART_DIV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3949;"	d
+HSUART_DIV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3947;"	d
+HSUART_DIV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3946;"	d
+HSUART_DIV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3948;"	d
+HSUART_DIV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3950;"	d
+HSUART_DLAB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3784;"	d
+HSUART_DLAB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3782;"	d
+HSUART_DLAB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3781;"	d
+HSUART_DLAB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3783;"	d
+HSUART_DLAB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3785;"	d
+HSUART_DMA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3749;"	d
+HSUART_DMA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3747;"	d
+HSUART_DMA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3746;"	d
+HSUART_DMA_RX_END_ADDR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3969;"	d
+HSUART_DMA_RX_END_ADDR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3967;"	d
+HSUART_DMA_RX_END_ADDR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3966;"	d
+HSUART_DMA_RX_END_ADDR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3968;"	d
+HSUART_DMA_RX_END_ADDR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3970;"	d
+HSUART_DMA_RX_RPT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3979;"	d
+HSUART_DMA_RX_RPT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3977;"	d
+HSUART_DMA_RX_RPT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3976;"	d
+HSUART_DMA_RX_RPT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3978;"	d
+HSUART_DMA_RX_RPT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3980;"	d
+HSUART_DMA_RX_STR_ADDR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3964;"	d
+HSUART_DMA_RX_STR_ADDR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3962;"	d
+HSUART_DMA_RX_STR_ADDR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3961;"	d
+HSUART_DMA_RX_STR_ADDR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3963;"	d
+HSUART_DMA_RX_STR_ADDR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3965;"	d
+HSUART_DMA_RX_WPT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3974;"	d
+HSUART_DMA_RX_WPT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3972;"	d
+HSUART_DMA_RX_WPT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3971;"	d
+HSUART_DMA_RX_WPT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3973;"	d
+HSUART_DMA_RX_WPT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3975;"	d
+HSUART_DMA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3748;"	d
+HSUART_DMA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3750;"	d
+HSUART_DMA_TX_END_ADDR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3989;"	d
+HSUART_DMA_TX_END_ADDR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3987;"	d
+HSUART_DMA_TX_END_ADDR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3986;"	d
+HSUART_DMA_TX_END_ADDR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3988;"	d
+HSUART_DMA_TX_END_ADDR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3990;"	d
+HSUART_DMA_TX_RPT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3999;"	d
+HSUART_DMA_TX_RPT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3997;"	d
+HSUART_DMA_TX_RPT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3996;"	d
+HSUART_DMA_TX_RPT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3998;"	d
+HSUART_DMA_TX_RPT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4000;"	d
+HSUART_DMA_TX_STR_ADDR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3984;"	d
+HSUART_DMA_TX_STR_ADDR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3982;"	d
+HSUART_DMA_TX_STR_ADDR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3981;"	d
+HSUART_DMA_TX_STR_ADDR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3983;"	d
+HSUART_DMA_TX_STR_ADDR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3985;"	d
+HSUART_DMA_TX_WPT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3994;"	d
+HSUART_DMA_TX_WPT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3992;"	d
+HSUART_DMA_TX_WPT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3991;"	d
+HSUART_DMA_TX_WPT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3993;"	d
+HSUART_DMA_TX_WPT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3995;"	d
+HSUART_DR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3824;"	d
+HSUART_DR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3822;"	d
+HSUART_DR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3821;"	d
+HSUART_DR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3823;"	d
+HSUART_DR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3825;"	d
+HSUART_DSR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3889;"	d
+HSUART_DSR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3887;"	d
+HSUART_DSR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3886;"	d
+HSUART_DSR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3888;"	d
+HSUART_DSR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3890;"	d
+HSUART_DTS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3789;"	d
+HSUART_DTS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3787;"	d
+HSUART_DTS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3786;"	d
+HSUART_DTS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3788;"	d
+HSUART_DTS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3790;"	d
+HSUART_ENABCTXTHR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3719;"	d
+HSUART_ENABCTXTHR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3717;"	d
+HSUART_ENABCTXTHR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3716;"	d
+HSUART_ENABCTXTHR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3718;"	d
+HSUART_ENABCTXTHR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3720;"	d
+HSUART_ENABDMARXEND_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3724;"	d
+HSUART_ENABDMARXEND_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3722;"	d
+HSUART_ENABDMARXEND_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3721;"	d
+HSUART_ENABDMARXEND_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3723;"	d
+HSUART_ENABDMARXEND_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3725;"	d
+HSUART_ENABDMATXEND_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3729;"	d
+HSUART_ENABDMATXEND_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3727;"	d
+HSUART_ENABDMATXEND_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3726;"	d
+HSUART_ENABDMATXEND_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3728;"	d
+HSUART_ENABDMATXEND_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3730;"	d
+HSUART_ENABLNSTAT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3709;"	d
+HSUART_ENABLNSTAT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3707;"	d
+HSUART_ENABLNSTAT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3706;"	d
+HSUART_ENABLNSTAT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3708;"	d
+HSUART_ENABLNSTAT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3710;"	d
+HSUART_ENABMDSTAT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3714;"	d
+HSUART_ENABMDSTAT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3712;"	d
+HSUART_ENABMDSTAT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3711;"	d
+HSUART_ENABMDSTAT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3713;"	d
+HSUART_ENABMDSTAT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3715;"	d
+HSUART_ENABRXBUFF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3699;"	d
+HSUART_ENABRXBUFF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3697;"	d
+HSUART_ENABRXBUFF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3696;"	d
+HSUART_ENABRXBUFF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3698;"	d
+HSUART_ENABRXBUFF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3700;"	d
+HSUART_ENABTXBUFF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3704;"	d
+HSUART_ENABTXBUFF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3702;"	d
+HSUART_ENABTXBUFF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3701;"	d
+HSUART_ENABTXBUFF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3703;"	d
+HSUART_ENABTXBUFF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3705;"	d
+HSUART_ERF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3859;"	d
+HSUART_ERF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3857;"	d
+HSUART_ERF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3856;"	d
+HSUART_ERF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3858;"	d
+HSUART_ERF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3860;"	d
+HSUART_FE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3839;"	d
+HSUART_FE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3837;"	d
+HSUART_FE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3836;"	d
+HSUART_FE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3838;"	d
+HSUART_FE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3840;"	d
+HSUART_FIFOE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3734;"	d
+HSUART_FIFOE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3732;"	d
+HSUART_FIFOE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3731;"	d
+HSUART_FIFOE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3733;"	d
+HSUART_FIFOE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3735;"	d
+HSUART_FRAC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3954;"	d
+HSUART_FRAC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3952;"	d
+HSUART_FRAC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3951;"	d
+HSUART_FRAC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3953;"	d
+HSUART_FRAC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3955;"	d
+HSUART_IFIFOE1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3944;"	d
+HSUART_IFIFOE1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3942;"	d
+HSUART_IFIFOE1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3941;"	d
+HSUART_IFIFOE1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3943;"	d
+HSUART_IFIFOE1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3945;"	d
+HSUART_IFOFOE0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3939;"	d
+HSUART_IFOFOE0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3937;"	d
+HSUART_IFOFOE0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3936;"	d
+HSUART_IFOFOE0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3938;"	d
+HSUART_IFOFOE0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3940;"	d
+HSUART_IIR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3929;"	d
+HSUART_IIR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3927;"	d
+HSUART_IIR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3926;"	d
+HSUART_IIR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3928;"	d
+HSUART_IIR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3930;"	d
+HSUART_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3959;"	d
+HSUART_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3957;"	d
+HSUART_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3956;"	d
+HSUART_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3958;"	d
+HSUART_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3960;"	d
+HSUART_LOOP1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3809;"	d
+HSUART_LOOP1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3807;"	d
+HSUART_LOOP1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3806;"	d
+HSUART_LOOP1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3808;"	d
+HSUART_LOOP1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3810;"	d
+HSUART_OE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3829;"	d
+HSUART_OE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3827;"	d
+HSUART_OE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3826;"	d
+HSUART_OE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3828;"	d
+HSUART_OE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3830;"	d
+HSUART_OUT1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3799;"	d
+HSUART_OUT1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3797;"	d
+HSUART_OUT1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3796;"	d
+HSUART_OUT1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3798;"	d
+HSUART_OUT1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3800;"	d
+HSUART_OUT2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3804;"	d
+HSUART_OUT2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3802;"	d
+HSUART_OUT2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3801;"	d
+HSUART_OUT2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3803;"	d
+HSUART_OUT2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3805;"	d
+HSUART_PEN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3769;"	d
+HSUART_PEN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3767;"	d
+HSUART_PEN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3766;"	d
+HSUART_PEN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3768;"	d
+HSUART_PEN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3770;"	d
+HSUART_PE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3834;"	d
+HSUART_PE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3832;"	d
+HSUART_PE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3831;"	d
+HSUART_PE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3833;"	d
+HSUART_PE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3835;"	d
+HSUART_RI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3894;"	d
+HSUART_RI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3892;"	d
+HSUART_RI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3891;"	d
+HSUART_RI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3893;"	d
+HSUART_RI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3895;"	d
+HSUART_RTS_AUTO_TH_H_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3914;"	d
+HSUART_RTS_AUTO_TH_H_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3912;"	d
+HSUART_RTS_AUTO_TH_H_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3911;"	d
+HSUART_RTS_AUTO_TH_H_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3913;"	d
+HSUART_RTS_AUTO_TH_H_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3915;"	d
+HSUART_RTS_AUTO_TH_L_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3909;"	d
+HSUART_RTS_AUTO_TH_L_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3907;"	d
+HSUART_RTS_AUTO_TH_L_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3906;"	d
+HSUART_RTS_AUTO_TH_L_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3908;"	d
+HSUART_RTS_AUTO_TH_L_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3910;"	d
+HSUART_RTS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3794;"	d
+HSUART_RTS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3792;"	d
+HSUART_RTS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3791;"	d
+HSUART_RTS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3793;"	d
+HSUART_RTS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3795;"	d
+HSUART_RXD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3694;"	d
+HSUART_RXD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3692;"	d
+HSUART_RXD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3691;"	d
+HSUART_RXD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3693;"	d
+HSUART_RXD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3695;"	d
+HSUART_RX_FIFO_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3739;"	d
+HSUART_RX_FIFO_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3737;"	d
+HSUART_RX_FIFO_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3736;"	d
+HSUART_RX_FIFO_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3738;"	d
+HSUART_RX_FIFO_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3740;"	d
+HSUART_RX_TRIG_LV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3754;"	d
+HSUART_RX_TRIG_LV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3752;"	d
+HSUART_RX_TRIG_LV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3751;"	d
+HSUART_RX_TRIG_LV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3753;"	d
+HSUART_RX_TRIG_LV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3755;"	d
+HSUART_SB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3779;"	d
+HSUART_SB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3777;"	d
+HSUART_SB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3776;"	d
+HSUART_SB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3778;"	d
+HSUART_SB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3780;"	d
+HSUART_SCR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3904;"	d
+HSUART_SCR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3902;"	d
+HSUART_SCR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3901;"	d
+HSUART_SCR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3903;"	d
+HSUART_SCR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3905;"	d
+HSUART_SP_EPS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3774;"	d
+HSUART_SP_EPS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3772;"	d
+HSUART_SP_EPS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3771;"	d
+HSUART_SP_EPS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3773;"	d
+HSUART_SP_EPS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3775;"	d
+HSUART_STB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3764;"	d
+HSUART_STB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3762;"	d
+HSUART_STB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3761;"	d
+HSUART_STB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3763;"	d
+HSUART_STB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3765;"	d
+HSUART_TERI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3874;"	d
+HSUART_TERI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3872;"	d
+HSUART_TERI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3871;"	d
+HSUART_TERI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3873;"	d
+HSUART_TERI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3875;"	d
+HSUART_THRE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3849;"	d
+HSUART_THRE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3847;"	d
+HSUART_THRE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3846;"	d
+HSUART_THRE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3848;"	d
+HSUART_THRE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3850;"	d
+HSUART_TSRE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3854;"	d
+HSUART_TSRE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3852;"	d
+HSUART_TSRE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3851;"	d
+HSUART_TSRE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3853;"	d
+HSUART_TSRE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3855;"	d
+HSUART_TXDMA_DONE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3934;"	d
+HSUART_TXDMA_DONE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3932;"	d
+HSUART_TXDMA_DONE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3931;"	d
+HSUART_TXDMA_DONE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3933;"	d
+HSUART_TXDMA_DONE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3935;"	d
+HSUART_TX_FIFO_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3744;"	d
+HSUART_TX_FIFO_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3742;"	d
+HSUART_TX_FIFO_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3741;"	d
+HSUART_TX_FIFO_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3743;"	d
+HSUART_TX_FIFO_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3745;"	d
+HSUART_TX_THR_H_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3924;"	d
+HSUART_TX_THR_H_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3922;"	d
+HSUART_TX_THR_H_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3921;"	d
+HSUART_TX_THR_H_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3923;"	d
+HSUART_TX_THR_H_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3925;"	d
+HSUART_TX_THR_L_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3919;"	d
+HSUART_TX_THR_L_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3917;"	d
+HSUART_TX_THR_L_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3916;"	d
+HSUART_TX_THR_L_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3918;"	d
+HSUART_TX_THR_L_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3920;"	d
+HSUART_WLS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3759;"	d
+HSUART_WLS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3757;"	d
+HSUART_WLS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3756;"	d
+HSUART_WLS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3758;"	d
+HSUART_WLS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3760;"	d
+HS_ACCESS_MD_HI	include/ssv6200_aux.h	17679;"	d
+HS_ACCESS_MD_I_MSK	include/ssv6200_aux.h	17677;"	d
+HS_ACCESS_MD_MSK	include/ssv6200_aux.h	17676;"	d
+HS_ACCESS_MD_SFT	include/ssv6200_aux.h	17678;"	d
+HS_ACCESS_MD_SZ	include/ssv6200_aux.h	17680;"	d
+HS_CHANNEL_HI	include/ssv6200_aux.h	17749;"	d
+HS_CHANNEL_I_MSK	include/ssv6200_aux.h	17747;"	d
+HS_CHANNEL_MSK	include/ssv6200_aux.h	17746;"	d
+HS_CHANNEL_SFT	include/ssv6200_aux.h	17748;"	d
+HS_CHANNEL_SZ	include/ssv6200_aux.h	17750;"	d
+HS_DATA_HI	include/ssv6200_aux.h	17759;"	d
+HS_DATA_I_MSK	include/ssv6200_aux.h	17757;"	d
+HS_DATA_MSK	include/ssv6200_aux.h	17756;"	d
+HS_DATA_SFT	include/ssv6200_aux.h	17758;"	d
+HS_DATA_SZ	include/ssv6200_aux.h	17760;"	d
+HS_FLAG_HI	include/ssv6200_aux.h	17739;"	d
+HS_FLAG_I_MSK	include/ssv6200_aux.h	17737;"	d
+HS_FLAG_MSK	include/ssv6200_aux.h	17736;"	d
+HS_FLAG_SFT	include/ssv6200_aux.h	17738;"	d
+HS_FLAG_SZ	include/ssv6200_aux.h	17740;"	d
+HS_ID_HI	include/ssv6200_aux.h	17744;"	d
+HS_ID_I_MSK	include/ssv6200_aux.h	17742;"	d
+HS_ID_MSK	include/ssv6200_aux.h	17741;"	d
+HS_ID_SFT	include/ssv6200_aux.h	17743;"	d
+HS_ID_SZ	include/ssv6200_aux.h	17745;"	d
+HS_PAGE_HI	include/ssv6200_aux.h	17754;"	d
+HS_PAGE_I_MSK	include/ssv6200_aux.h	17752;"	d
+HS_PAGE_MSK	include/ssv6200_aux.h	17751;"	d
+HS_PAGE_SFT	include/ssv6200_aux.h	17753;"	d
+HS_PAGE_SZ	include/ssv6200_aux.h	17755;"	d
+HS_WR_HI	include/ssv6200_aux.h	17734;"	d
+HS_WR_I_MSK	include/ssv6200_aux.h	17732;"	d
+HS_WR_MSK	include/ssv6200_aux.h	17731;"	d
+HS_WR_SFT	include/ssv6200_aux.h	17733;"	d
+HS_WR_SZ	include/ssv6200_aux.h	17735;"	d
+HT_CAP_RX_STBC_ONE_STREAM	smac/init.c	221;"	d	file:
+HT_CW_MIN	smac/ssv_ht_rc.c	23;"	d	file:
+HT_LTF	smac/dev.h	167;"	d
+HT_MODE_HI	include/ssv6200_aux.h	9129;"	d
+HT_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8884;"	d
+HT_MODE_I_MSK	include/ssv6200_aux.h	9127;"	d
+HT_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8882;"	d
+HT_MODE_MSK	include/ssv6200_aux.h	9126;"	d
+HT_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8881;"	d
+HT_MODE_SFT	include/ssv6200_aux.h	9128;"	d
+HT_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8883;"	d
+HT_MODE_SZ	include/ssv6200_aux.h	9130;"	d
+HT_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8885;"	d
+HT_RC_2_STREAMS	smac/dev.h	157;"	d
+HT_RC_UPDATE_INTERVAL	smac/ssv_rc_common.h	180;"	d
+HT_SEGMENT_SIZE	smac/ssv_ht_rc.c	24;"	d	file:
+HT_SIFS_TIME	smac/dev.h	155;"	d
+HT_SIG	smac/dev.h	165;"	d
+HT_SIGNAL_EXT	smac/dev.h	154;"	d
+HT_STF	smac/dev.h	166;"	d
+HWID_ALT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33199;"	d
+HWID_ALT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33197;"	d
+HWID_ALT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33196;"	d
+HWID_ALT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33198;"	d
+HWID_ALT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33200;"	d
+HWID_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32959;"	d
+HWID_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32957;"	d
+HWID_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32956;"	d
+HWID_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32958;"	d
+HWID_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32960;"	d
+HWIF_DBG_PRINT	hwif/hwif.h	38;"	d
+HW_ID_OFFSET	include/hal.h	32;"	d
+HW_ID_OFFSET	smac/dev.c	209;"	d	file:
+HW_MAX_RATE_TRIES	smac/dev.h	129;"	d
+HW_MMU_PAGE_MASK	include/ssv6200.h	91;"	d
+HW_MMU_PAGE_MASK	include/ssv6xxx_cfg.h	89;"	d
+HW_MMU_PAGE_MASK	smac/hal/ssv6006c/ssv6006_cfg.h	72;"	d
+HW_MMU_PAGE_SHIFT	include/ssv6200.h	90;"	d
+HW_MMU_PAGE_SHIFT	include/ssv6xxx_cfg.h	88;"	d
+HW_MMU_PAGE_SHIFT	smac/hal/ssv6006c/ssv6006_cfg.h	71;"	d
+HW_PKTID_ALT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33189;"	d
+HW_PKTID_ALT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33187;"	d
+HW_PKTID_ALT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33186;"	d
+HW_PKTID_ALT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33188;"	d
+HW_PKTID_ALT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33190;"	d
+HW_PKTID_HI	include/ssv6200_aux.h	11409;"	d
+HW_PKTID_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32949;"	d
+HW_PKTID_I_MSK	include/ssv6200_aux.h	11407;"	d
+HW_PKTID_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32947;"	d
+HW_PKTID_MSK	include/ssv6200_aux.h	11406;"	d
+HW_PKTID_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32946;"	d
+HW_PKTID_SFT	include/ssv6200_aux.h	11408;"	d
+HW_PKTID_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32948;"	d
+HW_PKTID_SZ	include/ssv6200_aux.h	11410;"	d
+HW_PKTID_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32950;"	d
+Hi16	smac/sec_tkip.c	/^static inline u16 Hi16(u32 val)$/;"	f	file:	signature:(u32 val)
+Hi8	smac/sec_tkip.c	/^static inline u8 Hi8(u16 val)$/;"	f	file:	signature:(u16 val)
+I2CMST_DISABLE_SLAVE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	684;"	d
+I2CMST_DISABLE_SLAVE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	682;"	d
+I2CMST_DISABLE_SLAVE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	681;"	d
+I2CMST_DISABLE_SLAVE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	683;"	d
+I2CMST_DISABLE_SLAVE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	685;"	d
+I2CMST_ENABLE_MASTER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	669;"	d
+I2CMST_ENABLE_MASTER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	667;"	d
+I2CMST_ENABLE_MASTER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	666;"	d
+I2CMST_ENABLE_MASTER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	668;"	d
+I2CMST_ENABLE_MASTER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	670;"	d
+I2CMST_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	829;"	d
+I2CMST_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	827;"	d
+I2CMST_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	826;"	d
+I2CMST_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	828;"	d
+I2CMST_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	830;"	d
+I2CMST_REG_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	80;"	d
+I2CMST_REG_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	19;"	d
+I2CMST_RESTART_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	679;"	d
+I2CMST_RESTART_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	677;"	d
+I2CMST_RESTART_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	676;"	d
+I2CMST_RESTART_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	678;"	d
+I2CMST_RESTART_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	680;"	d
+I2CMST_RXDONE_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	754;"	d
+I2CMST_RXDONE_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	752;"	d
+I2CMST_RXDONE_INT_MASK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	784;"	d
+I2CMST_RXDONE_INT_MASK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	782;"	d
+I2CMST_RXDONE_INT_MASK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	781;"	d
+I2CMST_RXDONE_INT_MASK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	783;"	d
+I2CMST_RXDONE_INT_MASK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	785;"	d
+I2CMST_RXDONE_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	751;"	d
+I2CMST_RXDONE_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	753;"	d
+I2CMST_RXDONE_INT_STAR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	814;"	d
+I2CMST_RXDONE_INT_STAR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	812;"	d
+I2CMST_RXDONE_INT_STAR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	811;"	d
+I2CMST_RXDONE_INT_STAR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	813;"	d
+I2CMST_RXDONE_INT_STAR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	815;"	d
+I2CMST_RXDONE_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	755;"	d
+I2CMST_RXF_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	739;"	d
+I2CMST_RXF_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	737;"	d
+I2CMST_RXF_INT_MASK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	769;"	d
+I2CMST_RXF_INT_MASK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	767;"	d
+I2CMST_RXF_INT_MASK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	766;"	d
+I2CMST_RXF_INT_MASK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	768;"	d
+I2CMST_RXF_INT_MASK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	770;"	d
+I2CMST_RXF_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	736;"	d
+I2CMST_RXF_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	738;"	d
+I2CMST_RXF_INT_STAR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	799;"	d
+I2CMST_RXF_INT_STAR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	797;"	d
+I2CMST_RXF_INT_STAR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	796;"	d
+I2CMST_RXF_INT_STAR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	798;"	d
+I2CMST_RXF_INT_STAR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	800;"	d
+I2CMST_RXF_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	740;"	d
+I2CMST_RXO_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	734;"	d
+I2CMST_RXO_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	732;"	d
+I2CMST_RXO_INT_MASK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	764;"	d
+I2CMST_RXO_INT_MASK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	762;"	d
+I2CMST_RXO_INT_MASK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	761;"	d
+I2CMST_RXO_INT_MASK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	763;"	d
+I2CMST_RXO_INT_MASK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	765;"	d
+I2CMST_RXO_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	731;"	d
+I2CMST_RXO_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	733;"	d
+I2CMST_RXO_INT_STAR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	794;"	d
+I2CMST_RXO_INT_STAR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	792;"	d
+I2CMST_RXO_INT_STAR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	791;"	d
+I2CMST_RXO_INT_STAR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	793;"	d
+I2CMST_RXO_INT_STAR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	795;"	d
+I2CMST_RXO_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	735;"	d
+I2CMST_RXU_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	729;"	d
+I2CMST_RXU_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	727;"	d
+I2CMST_RXU_INT_MASK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	759;"	d
+I2CMST_RXU_INT_MASK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	757;"	d
+I2CMST_RXU_INT_MASK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	756;"	d
+I2CMST_RXU_INT_MASK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	758;"	d
+I2CMST_RXU_INT_MASK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	760;"	d
+I2CMST_RXU_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	726;"	d
+I2CMST_RXU_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	728;"	d
+I2CMST_RXU_INT_STAR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	789;"	d
+I2CMST_RXU_INT_STAR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	787;"	d
+I2CMST_RXU_INT_STAR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	786;"	d
+I2CMST_RXU_INT_STAR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	788;"	d
+I2CMST_RXU_INT_STAR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	790;"	d
+I2CMST_RXU_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	730;"	d
+I2CMST_RX_1STBRDYR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	714;"	d
+I2CMST_RX_1STBRDYR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	712;"	d
+I2CMST_RX_1STBRDYR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	711;"	d
+I2CMST_RX_1STBRDYR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	713;"	d
+I2CMST_RX_1STBRDYR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	715;"	d
+I2CMST_RX_FIFO_TH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	819;"	d
+I2CMST_RX_FIFO_TH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	817;"	d
+I2CMST_RX_FIFO_TH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	816;"	d
+I2CMST_RX_FIFO_TH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	818;"	d
+I2CMST_RX_FIFO_TH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	820;"	d
+I2CMST_SCLK_H_WIDTH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	719;"	d
+I2CMST_SCLK_H_WIDTH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	717;"	d
+I2CMST_SCLK_H_WIDTH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	716;"	d
+I2CMST_SCLK_H_WIDTH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	718;"	d
+I2CMST_SCLK_H_WIDTH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	720;"	d
+I2CMST_SCLK_L_WIDTH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	724;"	d
+I2CMST_SCLK_L_WIDTH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	722;"	d
+I2CMST_SCLK_L_WIDTH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	721;"	d
+I2CMST_SCLK_L_WIDTH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	723;"	d
+I2CMST_SCLK_L_WIDTH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	725;"	d
+I2CMST_SPEED_HI	smac/hal/ssv6006c/ssv6006C_aux.h	674;"	d
+I2CMST_SPEED_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	672;"	d
+I2CMST_SPEED_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	671;"	d
+I2CMST_SPEED_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	673;"	d
+I2CMST_SPEED_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	675;"	d
+I2CMST_TAR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	689;"	d
+I2CMST_TAR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	687;"	d
+I2CMST_TAR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	686;"	d
+I2CMST_TAR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	688;"	d
+I2CMST_TAR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	690;"	d
+I2CMST_TRX_CMDW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	699;"	d
+I2CMST_TRX_CMDW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	697;"	d
+I2CMST_TRX_CMDW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	696;"	d
+I2CMST_TRX_CMDW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	698;"	d
+I2CMST_TRX_CMDW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	700;"	d
+I2CMST_TRX_DATA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	694;"	d
+I2CMST_TRX_DATA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	692;"	d
+I2CMST_TRX_DATA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	691;"	d
+I2CMST_TRX_DATA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	693;"	d
+I2CMST_TRX_DATA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	695;"	d
+I2CMST_TRX_RESTARTW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	709;"	d
+I2CMST_TRX_RESTARTW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	707;"	d
+I2CMST_TRX_RESTARTW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	706;"	d
+I2CMST_TRX_RESTARTW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	708;"	d
+I2CMST_TRX_RESTARTW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	710;"	d
+I2CMST_TRX_STOPW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	704;"	d
+I2CMST_TRX_STOPW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	702;"	d
+I2CMST_TRX_STOPW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	701;"	d
+I2CMST_TRX_STOPW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	703;"	d
+I2CMST_TRX_STOPW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	705;"	d
+I2CMST_TXE_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	749;"	d
+I2CMST_TXE_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	747;"	d
+I2CMST_TXE_INT_MASK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	779;"	d
+I2CMST_TXE_INT_MASK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	777;"	d
+I2CMST_TXE_INT_MASK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	776;"	d
+I2CMST_TXE_INT_MASK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	778;"	d
+I2CMST_TXE_INT_MASK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	780;"	d
+I2CMST_TXE_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	746;"	d
+I2CMST_TXE_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	748;"	d
+I2CMST_TXE_INT_STAR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	809;"	d
+I2CMST_TXE_INT_STAR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	807;"	d
+I2CMST_TXE_INT_STAR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	806;"	d
+I2CMST_TXE_INT_STAR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	808;"	d
+I2CMST_TXE_INT_STAR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	810;"	d
+I2CMST_TXE_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	750;"	d
+I2CMST_TXO_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	744;"	d
+I2CMST_TXO_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	742;"	d
+I2CMST_TXO_INT_MASK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	774;"	d
+I2CMST_TXO_INT_MASK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	772;"	d
+I2CMST_TXO_INT_MASK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	771;"	d
+I2CMST_TXO_INT_MASK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	773;"	d
+I2CMST_TXO_INT_MASK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	775;"	d
+I2CMST_TXO_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	741;"	d
+I2CMST_TXO_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	743;"	d
+I2CMST_TXO_INT_STAR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	804;"	d
+I2CMST_TXO_INT_STAR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	802;"	d
+I2CMST_TXO_INT_STAR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	801;"	d
+I2CMST_TXO_INT_STAR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	803;"	d
+I2CMST_TXO_INT_STAR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	805;"	d
+I2CMST_TXO_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	745;"	d
+I2CMST_TX_FIFO_TH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	824;"	d
+I2CMST_TX_FIFO_TH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	822;"	d
+I2CMST_TX_FIFO_TH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	821;"	d
+I2CMST_TX_FIFO_TH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	823;"	d
+I2CMST_TX_FIFO_TH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	825;"	d
+I2CM_DEV_A10B_HI	include/ssv6200_aux.h	4209;"	d
+I2CM_DEV_A10B_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3309;"	d
+I2CM_DEV_A10B_I_MSK	include/ssv6200_aux.h	4207;"	d
+I2CM_DEV_A10B_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3307;"	d
+I2CM_DEV_A10B_MSK	include/ssv6200_aux.h	4206;"	d
+I2CM_DEV_A10B_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3306;"	d
+I2CM_DEV_A10B_SFT	include/ssv6200_aux.h	4208;"	d
+I2CM_DEV_A10B_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3308;"	d
+I2CM_DEV_A10B_SZ	include/ssv6200_aux.h	4210;"	d
+I2CM_DEV_A10B_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3310;"	d
+I2CM_DEV_A_HI	include/ssv6200_aux.h	4204;"	d
+I2CM_DEV_A_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3304;"	d
+I2CM_DEV_A_I_MSK	include/ssv6200_aux.h	4202;"	d
+I2CM_DEV_A_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3302;"	d
+I2CM_DEV_A_MSK	include/ssv6200_aux.h	4201;"	d
+I2CM_DEV_A_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3301;"	d
+I2CM_DEV_A_SFT	include/ssv6200_aux.h	4203;"	d
+I2CM_DEV_A_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3303;"	d
+I2CM_DEV_A_SZ	include/ssv6200_aux.h	4205;"	d
+I2CM_DEV_A_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3305;"	d
+I2CM_IDLE_HI	include/ssv6200_aux.h	4174;"	d
+I2CM_IDLE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3274;"	d
+I2CM_IDLE_I_MSK	include/ssv6200_aux.h	4172;"	d
+I2CM_IDLE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3272;"	d
+I2CM_IDLE_MSK	include/ssv6200_aux.h	4171;"	d
+I2CM_IDLE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3271;"	d
+I2CM_IDLE_SFT	include/ssv6200_aux.h	4173;"	d
+I2CM_IDLE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3273;"	d
+I2CM_IDLE_SZ	include/ssv6200_aux.h	4175;"	d
+I2CM_IDLE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3275;"	d
+I2CM_INT_MISMATCH_HI	include/ssv6200_aux.h	4179;"	d
+I2CM_INT_MISMATCH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3279;"	d
+I2CM_INT_MISMATCH_I_MSK	include/ssv6200_aux.h	4177;"	d
+I2CM_INT_MISMATCH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3277;"	d
+I2CM_INT_MISMATCH_MSK	include/ssv6200_aux.h	4176;"	d
+I2CM_INT_MISMATCH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3276;"	d
+I2CM_INT_MISMATCH_SFT	include/ssv6200_aux.h	4178;"	d
+I2CM_INT_MISMATCH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3278;"	d
+I2CM_INT_MISMATCH_SZ	include/ssv6200_aux.h	4180;"	d
+I2CM_INT_MISMATCH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3280;"	d
+I2CM_INT_RDATA_NEED_HI	include/ssv6200_aux.h	4199;"	d
+I2CM_INT_RDATA_NEED_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3299;"	d
+I2CM_INT_RDATA_NEED_I_MSK	include/ssv6200_aux.h	4197;"	d
+I2CM_INT_RDATA_NEED_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3297;"	d
+I2CM_INT_RDATA_NEED_MSK	include/ssv6200_aux.h	4196;"	d
+I2CM_INT_RDATA_NEED_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3296;"	d
+I2CM_INT_RDATA_NEED_SFT	include/ssv6200_aux.h	4198;"	d
+I2CM_INT_RDATA_NEED_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3298;"	d
+I2CM_INT_RDATA_NEED_SZ	include/ssv6200_aux.h	4200;"	d
+I2CM_INT_RDATA_NEED_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3300;"	d
+I2CM_INT_RDONE_HI	include/ssv6200_aux.h	4169;"	d
+I2CM_INT_RDONE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3269;"	d
+I2CM_INT_RDONE_I_MSK	include/ssv6200_aux.h	4167;"	d
+I2CM_INT_RDONE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3267;"	d
+I2CM_INT_RDONE_MSK	include/ssv6200_aux.h	4166;"	d
+I2CM_INT_RDONE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3266;"	d
+I2CM_INT_RDONE_SFT	include/ssv6200_aux.h	4168;"	d
+I2CM_INT_RDONE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3268;"	d
+I2CM_INT_RDONE_SZ	include/ssv6200_aux.h	4170;"	d
+I2CM_INT_RDONE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3270;"	d
+I2CM_INT_WDATA_NEED_HI	include/ssv6200_aux.h	4194;"	d
+I2CM_INT_WDATA_NEED_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3294;"	d
+I2CM_INT_WDATA_NEED_I_MSK	include/ssv6200_aux.h	4192;"	d
+I2CM_INT_WDATA_NEED_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3292;"	d
+I2CM_INT_WDATA_NEED_MSK	include/ssv6200_aux.h	4191;"	d
+I2CM_INT_WDATA_NEED_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3291;"	d
+I2CM_INT_WDATA_NEED_SFT	include/ssv6200_aux.h	4193;"	d
+I2CM_INT_WDATA_NEED_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3293;"	d
+I2CM_INT_WDATA_NEED_SZ	include/ssv6200_aux.h	4195;"	d
+I2CM_INT_WDATA_NEED_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3295;"	d
+I2CM_INT_WDONE_HI	include/ssv6200_aux.h	4164;"	d
+I2CM_INT_WDONE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3264;"	d
+I2CM_INT_WDONE_I_MSK	include/ssv6200_aux.h	4162;"	d
+I2CM_INT_WDONE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3262;"	d
+I2CM_INT_WDONE_MSK	include/ssv6200_aux.h	4161;"	d
+I2CM_INT_WDONE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3261;"	d
+I2CM_INT_WDONE_SFT	include/ssv6200_aux.h	4163;"	d
+I2CM_INT_WDONE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3263;"	d
+I2CM_INT_WDONE_SZ	include/ssv6200_aux.h	4165;"	d
+I2CM_INT_WDONE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3265;"	d
+I2CM_LEN_HI	include/ssv6200_aux.h	4219;"	d
+I2CM_LEN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3319;"	d
+I2CM_LEN_I_MSK	include/ssv6200_aux.h	4217;"	d
+I2CM_LEN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3317;"	d
+I2CM_LEN_MSK	include/ssv6200_aux.h	4216;"	d
+I2CM_LEN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3316;"	d
+I2CM_LEN_SFT	include/ssv6200_aux.h	4218;"	d
+I2CM_LEN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3318;"	d
+I2CM_LEN_SZ	include/ssv6200_aux.h	4220;"	d
+I2CM_LEN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3320;"	d
+I2CM_MANUAL_MODE_HI	include/ssv6200_aux.h	4189;"	d
+I2CM_MANUAL_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3289;"	d
+I2CM_MANUAL_MODE_I_MSK	include/ssv6200_aux.h	4187;"	d
+I2CM_MANUAL_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3287;"	d
+I2CM_MANUAL_MODE_MSK	include/ssv6200_aux.h	4186;"	d
+I2CM_MANUAL_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3286;"	d
+I2CM_MANUAL_MODE_SFT	include/ssv6200_aux.h	4188;"	d
+I2CM_MANUAL_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3288;"	d
+I2CM_MANUAL_MODE_SZ	include/ssv6200_aux.h	4190;"	d
+I2CM_MANUAL_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3290;"	d
+I2CM_PSCL_HI	include/ssv6200_aux.h	4184;"	d
+I2CM_PSCL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3284;"	d
+I2CM_PSCL_I_MSK	include/ssv6200_aux.h	4182;"	d
+I2CM_PSCL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3282;"	d
+I2CM_PSCL_MSK	include/ssv6200_aux.h	4181;"	d
+I2CM_PSCL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3281;"	d
+I2CM_PSCL_SFT	include/ssv6200_aux.h	4183;"	d
+I2CM_PSCL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3283;"	d
+I2CM_PSCL_SZ	include/ssv6200_aux.h	4185;"	d
+I2CM_PSCL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3285;"	d
+I2CM_RDAT_HI	include/ssv6200_aux.h	4239;"	d
+I2CM_RDAT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3339;"	d
+I2CM_RDAT_I_MSK	include/ssv6200_aux.h	4237;"	d
+I2CM_RDAT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3337;"	d
+I2CM_RDAT_MSK	include/ssv6200_aux.h	4236;"	d
+I2CM_RDAT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3336;"	d
+I2CM_RDAT_SFT	include/ssv6200_aux.h	4238;"	d
+I2CM_RDAT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3338;"	d
+I2CM_RDAT_SZ	include/ssv6200_aux.h	4240;"	d
+I2CM_RDAT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3340;"	d
+I2CM_REPEAT_START_HI	include/ssv6200_aux.h	4254;"	d
+I2CM_REPEAT_START_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3354;"	d
+I2CM_REPEAT_START_I_MSK	include/ssv6200_aux.h	4252;"	d
+I2CM_REPEAT_START_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3352;"	d
+I2CM_REPEAT_START_MSK	include/ssv6200_aux.h	4251;"	d
+I2CM_REPEAT_START_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3351;"	d
+I2CM_REPEAT_START_SFT	include/ssv6200_aux.h	4253;"	d
+I2CM_REPEAT_START_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3353;"	d
+I2CM_REPEAT_START_SZ	include/ssv6200_aux.h	4255;"	d
+I2CM_REPEAT_START_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3355;"	d
+I2CM_RX_HI	include/ssv6200_aux.h	4214;"	d
+I2CM_RX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3314;"	d
+I2CM_RX_I_MSK	include/ssv6200_aux.h	4212;"	d
+I2CM_RX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3312;"	d
+I2CM_RX_MSK	include/ssv6200_aux.h	4211;"	d
+I2CM_RX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3311;"	d
+I2CM_RX_SFT	include/ssv6200_aux.h	4213;"	d
+I2CM_RX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3313;"	d
+I2CM_RX_SZ	include/ssv6200_aux.h	4215;"	d
+I2CM_RX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3315;"	d
+I2CM_R_GET_HI	include/ssv6200_aux.h	4229;"	d
+I2CM_R_GET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3329;"	d
+I2CM_R_GET_I_MSK	include/ssv6200_aux.h	4227;"	d
+I2CM_R_GET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3327;"	d
+I2CM_R_GET_MSK	include/ssv6200_aux.h	4226;"	d
+I2CM_R_GET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3326;"	d
+I2CM_R_GET_SFT	include/ssv6200_aux.h	4228;"	d
+I2CM_R_GET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3328;"	d
+I2CM_R_GET_SZ	include/ssv6200_aux.h	4230;"	d
+I2CM_R_GET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3330;"	d
+I2CM_SCL_ID_SEL_HI	include/ssv6200_aux.h	3009;"	d
+I2CM_SCL_ID_SEL_I_MSK	include/ssv6200_aux.h	3007;"	d
+I2CM_SCL_ID_SEL_MSK	include/ssv6200_aux.h	3006;"	d
+I2CM_SCL_ID_SEL_SFT	include/ssv6200_aux.h	3008;"	d
+I2CM_SCL_ID_SEL_SZ	include/ssv6200_aux.h	3010;"	d
+I2CM_SDA_ID_SEL_HI	include/ssv6200_aux.h	2939;"	d
+I2CM_SDA_ID_SEL_I_MSK	include/ssv6200_aux.h	2937;"	d
+I2CM_SDA_ID_SEL_MSK	include/ssv6200_aux.h	2936;"	d
+I2CM_SDA_ID_SEL_SFT	include/ssv6200_aux.h	2938;"	d
+I2CM_SDA_ID_SEL_SZ	include/ssv6200_aux.h	2940;"	d
+I2CM_SR_LEN_HI	include/ssv6200_aux.h	4244;"	d
+I2CM_SR_LEN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3344;"	d
+I2CM_SR_LEN_I_MSK	include/ssv6200_aux.h	4242;"	d
+I2CM_SR_LEN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3342;"	d
+I2CM_SR_LEN_MSK	include/ssv6200_aux.h	4241;"	d
+I2CM_SR_LEN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3341;"	d
+I2CM_SR_LEN_SFT	include/ssv6200_aux.h	4243;"	d
+I2CM_SR_LEN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3343;"	d
+I2CM_SR_LEN_SZ	include/ssv6200_aux.h	4245;"	d
+I2CM_SR_LEN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3345;"	d
+I2CM_SR_RX_HI	include/ssv6200_aux.h	4249;"	d
+I2CM_SR_RX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3349;"	d
+I2CM_SR_RX_I_MSK	include/ssv6200_aux.h	4247;"	d
+I2CM_SR_RX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3347;"	d
+I2CM_SR_RX_MSK	include/ssv6200_aux.h	4246;"	d
+I2CM_SR_RX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3346;"	d
+I2CM_SR_RX_SFT	include/ssv6200_aux.h	4248;"	d
+I2CM_SR_RX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3348;"	d
+I2CM_SR_RX_SZ	include/ssv6200_aux.h	4250;"	d
+I2CM_SR_RX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3350;"	d
+I2CM_STA_STO_PSCL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3359;"	d
+I2CM_STA_STO_PSCL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3357;"	d
+I2CM_STA_STO_PSCL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3356;"	d
+I2CM_STA_STO_PSCL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3358;"	d
+I2CM_STA_STO_PSCL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3360;"	d
+I2CM_T_LEFT_HI	include/ssv6200_aux.h	4224;"	d
+I2CM_T_LEFT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3324;"	d
+I2CM_T_LEFT_I_MSK	include/ssv6200_aux.h	4222;"	d
+I2CM_T_LEFT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3322;"	d
+I2CM_T_LEFT_MSK	include/ssv6200_aux.h	4221;"	d
+I2CM_T_LEFT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3321;"	d
+I2CM_T_LEFT_SFT	include/ssv6200_aux.h	4223;"	d
+I2CM_T_LEFT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3323;"	d
+I2CM_T_LEFT_SZ	include/ssv6200_aux.h	4225;"	d
+I2CM_T_LEFT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3325;"	d
+I2CM_WDAT_HI	include/ssv6200_aux.h	4234;"	d
+I2CM_WDAT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3334;"	d
+I2CM_WDAT_I_MSK	include/ssv6200_aux.h	4232;"	d
+I2CM_WDAT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3332;"	d
+I2CM_WDAT_MSK	include/ssv6200_aux.h	4231;"	d
+I2CM_WDAT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3331;"	d
+I2CM_WDAT_SFT	include/ssv6200_aux.h	4233;"	d
+I2CM_WDAT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3333;"	d
+I2CM_WDAT_SZ	include/ssv6200_aux.h	4235;"	d
+I2CM_WDAT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3335;"	d
+I2CS_ADDR_DC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2464;"	d
+I2CS_ADDR_DC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2462;"	d
+I2CS_ADDR_DC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2461;"	d
+I2CS_ADDR_DC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2463;"	d
+I2CS_ADDR_DC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2465;"	d
+I2CS_ADDR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2469;"	d
+I2CS_ADDR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2467;"	d
+I2CS_ADDR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2466;"	d
+I2CS_ADDR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2468;"	d
+I2CS_ADDR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2470;"	d
+I2CS_DATA_CONFIG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2494;"	d
+I2CS_DATA_CONFIG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2492;"	d
+I2CS_DATA_CONFIG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2491;"	d
+I2CS_DATA_CONFIG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2493;"	d
+I2CS_DATA_CONFIG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2495;"	d
+I2CS_HOLD_BUS_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2499;"	d
+I2CS_HOLD_BUS_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2497;"	d
+I2CS_HOLD_BUS_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2496;"	d
+I2CS_HOLD_BUS_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2498;"	d
+I2CS_HOLD_BUS_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2500;"	d
+I2CS_IDLE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2479;"	d
+I2CS_IDLE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2477;"	d
+I2CS_IDLE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2476;"	d
+I2CS_IDLE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2478;"	d
+I2CS_IDLE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2480;"	d
+I2CS_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2474;"	d
+I2CS_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2472;"	d
+I2CS_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2471;"	d
+I2CS_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2473;"	d
+I2CS_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2475;"	d
+I2CS_STATE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2489;"	d
+I2CS_STATE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2487;"	d
+I2CS_STATE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2486;"	d
+I2CS_STATE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2488;"	d
+I2CS_STATE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2490;"	d
+I2CS_TIME_OUT_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2484;"	d
+I2CS_TIME_OUT_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2482;"	d
+I2CS_TIME_OUT_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2481;"	d
+I2CS_TIME_OUT_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2483;"	d
+I2CS_TIME_OUT_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2485;"	d
+I2C_MST_CLK_EN_HI	include/ssv6200_aux.h	294;"	d
+I2C_MST_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1254;"	d
+I2C_MST_CLK_EN_I_MSK	include/ssv6200_aux.h	292;"	d
+I2C_MST_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1252;"	d
+I2C_MST_CLK_EN_MSK	include/ssv6200_aux.h	291;"	d
+I2C_MST_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1251;"	d
+I2C_MST_CLK_EN_SFT	include/ssv6200_aux.h	293;"	d
+I2C_MST_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1253;"	d
+I2C_MST_CLK_EN_SZ	include/ssv6200_aux.h	295;"	d
+I2C_MST_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1255;"	d
+I2C_MST_SW_RST_HI	include/ssv6200_aux.h	134;"	d
+I2C_MST_SW_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1084;"	d
+I2C_MST_SW_RST_I_MSK	include/ssv6200_aux.h	132;"	d
+I2C_MST_SW_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1082;"	d
+I2C_MST_SW_RST_MSK	include/ssv6200_aux.h	131;"	d
+I2C_MST_SW_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1081;"	d
+I2C_MST_SW_RST_SFT	include/ssv6200_aux.h	133;"	d
+I2C_MST_SW_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1083;"	d
+I2C_MST_SW_RST_SZ	include/ssv6200_aux.h	135;"	d
+I2C_MST_SW_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1085;"	d
+I2C_SLV_CLK_EN_HI	include/ssv6200_aux.h	229;"	d
+I2C_SLV_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1179;"	d
+I2C_SLV_CLK_EN_I_MSK	include/ssv6200_aux.h	227;"	d
+I2C_SLV_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1177;"	d
+I2C_SLV_CLK_EN_MSK	include/ssv6200_aux.h	226;"	d
+I2C_SLV_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1176;"	d
+I2C_SLV_CLK_EN_SFT	include/ssv6200_aux.h	228;"	d
+I2C_SLV_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1178;"	d
+I2C_SLV_CLK_EN_SZ	include/ssv6200_aux.h	230;"	d
+I2C_SLV_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1180;"	d
+I2C_SLV_SW_RST_HI	include/ssv6200_aux.h	59;"	d
+I2C_SLV_SW_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1014;"	d
+I2C_SLV_SW_RST_I_MSK	include/ssv6200_aux.h	57;"	d
+I2C_SLV_SW_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1012;"	d
+I2C_SLV_SW_RST_MSK	include/ssv6200_aux.h	56;"	d
+I2C_SLV_SW_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1011;"	d
+I2C_SLV_SW_RST_SFT	include/ssv6200_aux.h	58;"	d
+I2C_SLV_SW_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1013;"	d
+I2C_SLV_SW_RST_SZ	include/ssv6200_aux.h	60;"	d
+I2C_SLV_SW_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1015;"	d
+I2SMAS_CLK_DIV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1424;"	d
+I2SMAS_CLK_DIV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1422;"	d
+I2SMAS_CLK_DIV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1421;"	d
+I2SMAS_CLK_DIV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1423;"	d
+I2SMAS_CLK_DIV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1425;"	d
+I2S_ENABLE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	519;"	d
+I2S_ENABLE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	517;"	d
+I2S_ENABLE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	516;"	d
+I2S_ENABLE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	518;"	d
+I2S_ENABLE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	520;"	d
+I2S_INTR_RXDA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	589;"	d
+I2S_INTR_RXDA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	587;"	d
+I2S_INTR_RXDA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	586;"	d
+I2S_INTR_RXDA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	588;"	d
+I2S_INTR_RXDA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	590;"	d
+I2S_INTR_RXFA_MASK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	609;"	d
+I2S_INTR_RXFA_MASK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	607;"	d
+I2S_INTR_RXFA_MASK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	606;"	d
+I2S_INTR_RXFA_MASK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	608;"	d
+I2S_INTR_RXFA_MASK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	610;"	d
+I2S_INTR_RXFE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	599;"	d
+I2S_INTR_RXFE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	597;"	d
+I2S_INTR_RXFE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	596;"	d
+I2S_INTR_RXFE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	598;"	d
+I2S_INTR_RXFE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	600;"	d
+I2S_INTR_RXFO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	594;"	d
+I2S_INTR_RXFO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	592;"	d
+I2S_INTR_RXFO_MASK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	614;"	d
+I2S_INTR_RXFO_MASK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	612;"	d
+I2S_INTR_RXFO_MASK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	611;"	d
+I2S_INTR_RXFO_MASK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	613;"	d
+I2S_INTR_RXFO_MASK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	615;"	d
+I2S_INTR_RXFO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	591;"	d
+I2S_INTR_RXFO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	593;"	d
+I2S_INTR_RXFO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	595;"	d
+I2S_INTR_TXFE_MASK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	619;"	d
+I2S_INTR_TXFE_MASK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	617;"	d
+I2S_INTR_TXFE_MASK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	616;"	d
+I2S_INTR_TXFE_MASK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	618;"	d
+I2S_INTR_TXFE_MASK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	620;"	d
+I2S_INTR_TXFO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	604;"	d
+I2S_INTR_TXFO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	602;"	d
+I2S_INTR_TXFO_MASK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	624;"	d
+I2S_INTR_TXFO_MASK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	622;"	d
+I2S_INTR_TXFO_MASK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	621;"	d
+I2S_INTR_TXFO_MASK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	623;"	d
+I2S_INTR_TXFO_MASK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	625;"	d
+I2S_INTR_TXFO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	601;"	d
+I2S_INTR_TXFO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	603;"	d
+I2S_INTR_TXFO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	605;"	d
+I2S_L_TRX_DATA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	559;"	d
+I2S_L_TRX_DATA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	557;"	d
+I2S_L_TRX_DATA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	556;"	d
+I2S_L_TRX_DATA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	558;"	d
+I2S_L_TRX_DATA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	560;"	d
+I2S_MASTER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1434;"	d
+I2S_MASTER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1432;"	d
+I2S_MASTER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1431;"	d
+I2S_MASTER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1433;"	d
+I2S_MASTER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1435;"	d
+I2S_MCLK_DIV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1429;"	d
+I2S_MCLK_DIV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1427;"	d
+I2S_MCLK_DIV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1426;"	d
+I2S_MCLK_DIV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1428;"	d
+I2S_MCLK_DIV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1430;"	d
+I2S_PCLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1289;"	d
+I2S_PCLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1287;"	d
+I2S_PCLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1286;"	d
+I2S_PCLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1288;"	d
+I2S_PCLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1290;"	d
+I2S_RAW_DATA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2429;"	d
+I2S_RAW_DATA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2427;"	d
+I2S_RAW_DATA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2426;"	d
+I2S_RAW_DATA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2428;"	d
+I2S_RAW_DATA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2430;"	d
+I2S_RST_RXFIFO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	549;"	d
+I2S_RST_RXFIFO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	547;"	d
+I2S_RST_RXFIFO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	546;"	d
+I2S_RST_RXFIFO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	548;"	d
+I2S_RST_RXFIFO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	550;"	d
+I2S_RST_TXFIFO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	554;"	d
+I2S_RST_TXFIFO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	552;"	d
+I2S_RST_TXFIFO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	551;"	d
+I2S_RST_TXFIFO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	553;"	d
+I2S_RST_TXFIFO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	555;"	d
+I2S_RXFO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	629;"	d
+I2S_RXFO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	627;"	d
+I2S_RXFO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	626;"	d
+I2S_RXFO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	628;"	d
+I2S_RXFO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	630;"	d
+I2S_RX_CH_ENABLE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	569;"	d
+I2S_RX_CH_ENABLE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	567;"	d
+I2S_RX_CH_ENABLE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	566;"	d
+I2S_RX_CH_ENABLE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	568;"	d
+I2S_RX_CH_ENABLE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	570;"	d
+I2S_RX_DMA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	659;"	d
+I2S_RX_DMA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	657;"	d
+I2S_RX_DMA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	656;"	d
+I2S_RX_DMA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	658;"	d
+I2S_RX_DMA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	660;"	d
+I2S_RX_ENABLE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	524;"	d
+I2S_RX_ENABLE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	522;"	d
+I2S_RX_ENABLE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	521;"	d
+I2S_RX_ENABLE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	523;"	d
+I2S_RX_ENABLE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	525;"	d
+I2S_RX_FIFO_FLUSH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	649;"	d
+I2S_RX_FIFO_FLUSH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	647;"	d
+I2S_RX_FIFO_FLUSH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	646;"	d
+I2S_RX_FIFO_FLUSH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	648;"	d
+I2S_RX_FIFO_FLUSH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	650;"	d
+I2S_RX_FIFO_TH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	639;"	d
+I2S_RX_FIFO_TH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	637;"	d
+I2S_RX_FIFO_TH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	636;"	d
+I2S_RX_FIFO_TH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	638;"	d
+I2S_RX_FIFO_TH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	640;"	d
+I2S_RX_WD_RES_HI	smac/hal/ssv6006c/ssv6006C_aux.h	579;"	d
+I2S_RX_WD_RES_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	577;"	d
+I2S_RX_WD_RES_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	576;"	d
+I2S_RX_WD_RES_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	578;"	d
+I2S_RX_WD_RES_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	580;"	d
+I2S_R_TRX_DATA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	564;"	d
+I2S_R_TRX_DATA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	562;"	d
+I2S_R_TRX_DATA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	561;"	d
+I2S_R_TRX_DATA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	563;"	d
+I2S_R_TRX_DATA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	565;"	d
+I2S_SCLK_GATE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	539;"	d
+I2S_SCLK_GATE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	537;"	d
+I2S_SCLK_GATE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	536;"	d
+I2S_SCLK_GATE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	538;"	d
+I2S_SCLK_GATE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	540;"	d
+I2S_SCLK_SOURCE_ENABLE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	534;"	d
+I2S_SCLK_SOURCE_ENABLE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	532;"	d
+I2S_SCLK_SOURCE_ENABLE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	531;"	d
+I2S_SCLK_SOURCE_ENABLE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	533;"	d
+I2S_SCLK_SOURCE_ENABLE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	535;"	d
+I2S_TRX_REG_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	79;"	d
+I2S_TRX_REG_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	18;"	d
+I2S_TXFO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	634;"	d
+I2S_TXFO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	632;"	d
+I2S_TXFO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	631;"	d
+I2S_TXFO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	633;"	d
+I2S_TXFO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	635;"	d
+I2S_TX_CH_ENABLE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	574;"	d
+I2S_TX_CH_ENABLE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	572;"	d
+I2S_TX_CH_ENABLE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	571;"	d
+I2S_TX_CH_ENABLE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	573;"	d
+I2S_TX_CH_ENABLE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	575;"	d
+I2S_TX_DMA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	664;"	d
+I2S_TX_DMA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	662;"	d
+I2S_TX_DMA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	661;"	d
+I2S_TX_DMA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	663;"	d
+I2S_TX_DMA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	665;"	d
+I2S_TX_ENABLE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	529;"	d
+I2S_TX_ENABLE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	527;"	d
+I2S_TX_ENABLE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	526;"	d
+I2S_TX_ENABLE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	528;"	d
+I2S_TX_ENABLE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	530;"	d
+I2S_TX_FIFO_FLUSH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	654;"	d
+I2S_TX_FIFO_FLUSH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	652;"	d
+I2S_TX_FIFO_FLUSH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	651;"	d
+I2S_TX_FIFO_FLUSH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	653;"	d
+I2S_TX_FIFO_FLUSH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	655;"	d
+I2S_TX_FIFO_TH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	644;"	d
+I2S_TX_FIFO_TH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	642;"	d
+I2S_TX_FIFO_TH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	641;"	d
+I2S_TX_FIFO_TH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	643;"	d
+I2S_TX_FIFO_TH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	645;"	d
+I2S_TX_WD_RES_HI	smac/hal/ssv6006c/ssv6006C_aux.h	584;"	d
+I2S_TX_WD_RES_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	582;"	d
+I2S_TX_WD_RES_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	581;"	d
+I2S_TX_WD_RES_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	583;"	d
+I2S_TX_WD_RES_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	585;"	d
+I2S_WS_LENGTH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	544;"	d
+I2S_WS_LENGTH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	542;"	d
+I2S_WS_LENGTH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	541;"	d
+I2S_WS_LENGTH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	543;"	d
+I2S_WS_LENGTH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	545;"	d
+IC_TAG_31_0_HI	include/ssv6200_aux.h	8739;"	d
+IC_TAG_31_0_I_MSK	include/ssv6200_aux.h	8737;"	d
+IC_TAG_31_0_MSK	include/ssv6200_aux.h	8736;"	d
+IC_TAG_31_0_SFT	include/ssv6200_aux.h	8738;"	d
+IC_TAG_31_0_SZ	include/ssv6200_aux.h	8740;"	d
+IC_TAG_63_32_HI	include/ssv6200_aux.h	8744;"	d
+IC_TAG_63_32_I_MSK	include/ssv6200_aux.h	8742;"	d
+IC_TAG_63_32_MSK	include/ssv6200_aux.h	8741;"	d
+IC_TAG_63_32_SFT	include/ssv6200_aux.h	8743;"	d
+IC_TAG_63_32_SZ	include/ssv6200_aux.h	8745;"	d
+IDX_EXTEND_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6519;"	d
+IDX_EXTEND_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6517;"	d
+IDX_EXTEND_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6516;"	d
+IDX_EXTEND_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6518;"	d
+IDX_EXTEND_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6520;"	d
+ID_DOUBLE_RLS_HI	include/ssv6200_aux.h	5014;"	d
+ID_DOUBLE_RLS_INT_HI	include/ssv6200_aux.h	12704;"	d
+ID_DOUBLE_RLS_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34229;"	d
+ID_DOUBLE_RLS_INT_I_MSK	include/ssv6200_aux.h	12702;"	d
+ID_DOUBLE_RLS_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34227;"	d
+ID_DOUBLE_RLS_INT_MSK	include/ssv6200_aux.h	12701;"	d
+ID_DOUBLE_RLS_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34226;"	d
+ID_DOUBLE_RLS_INT_SFT	include/ssv6200_aux.h	12703;"	d
+ID_DOUBLE_RLS_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34228;"	d
+ID_DOUBLE_RLS_INT_SZ	include/ssv6200_aux.h	12705;"	d
+ID_DOUBLE_RLS_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34230;"	d
+ID_DOUBLE_RLS_I_MSK	include/ssv6200_aux.h	5012;"	d
+ID_DOUBLE_RLS_MSK	include/ssv6200_aux.h	5011;"	d
+ID_DOUBLE_RLS_SD_HI	include/ssv6200_aux.h	5359;"	d
+ID_DOUBLE_RLS_SD_I_MSK	include/ssv6200_aux.h	5357;"	d
+ID_DOUBLE_RLS_SD_MSK	include/ssv6200_aux.h	5356;"	d
+ID_DOUBLE_RLS_SD_SFT	include/ssv6200_aux.h	5358;"	d
+ID_DOUBLE_RLS_SD_SZ	include/ssv6200_aux.h	5360;"	d
+ID_DOUBLE_RLS_SFT	include/ssv6200_aux.h	5013;"	d
+ID_DOUBLE_RLS_SZ	include/ssv6200_aux.h	5015;"	d
+ID_EXCEPT_FLG_CLR_HI	include/ssv6200_aux.h	12524;"	d
+ID_EXCEPT_FLG_CLR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34049;"	d
+ID_EXCEPT_FLG_CLR_I_MSK	include/ssv6200_aux.h	12522;"	d
+ID_EXCEPT_FLG_CLR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34047;"	d
+ID_EXCEPT_FLG_CLR_MSK	include/ssv6200_aux.h	12521;"	d
+ID_EXCEPT_FLG_CLR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34046;"	d
+ID_EXCEPT_FLG_CLR_SFT	include/ssv6200_aux.h	12523;"	d
+ID_EXCEPT_FLG_CLR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34048;"	d
+ID_EXCEPT_FLG_CLR_SZ	include/ssv6200_aux.h	12525;"	d
+ID_EXCEPT_FLG_CLR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34050;"	d
+ID_EXCEPT_FLG_HI	include/ssv6200_aux.h	12529;"	d
+ID_EXCEPT_FLG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34054;"	d
+ID_EXCEPT_FLG_I_MSK	include/ssv6200_aux.h	12527;"	d
+ID_EXCEPT_FLG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34052;"	d
+ID_EXCEPT_FLG_MSK	include/ssv6200_aux.h	12526;"	d
+ID_EXCEPT_FLG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34051;"	d
+ID_EXCEPT_FLG_SFT	include/ssv6200_aux.h	12528;"	d
+ID_EXCEPT_FLG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34053;"	d
+ID_EXCEPT_FLG_SZ	include/ssv6200_aux.h	12530;"	d
+ID_EXCEPT_FLG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34055;"	d
+ID_FULL_HI	include/ssv6200_aux.h	12534;"	d
+ID_FULL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34059;"	d
+ID_FULL_I_MSK	include/ssv6200_aux.h	12532;"	d
+ID_FULL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34057;"	d
+ID_FULL_MSK	include/ssv6200_aux.h	12531;"	d
+ID_FULL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34056;"	d
+ID_FULL_SFT	include/ssv6200_aux.h	12533;"	d
+ID_FULL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34058;"	d
+ID_FULL_SZ	include/ssv6200_aux.h	12535;"	d
+ID_FULL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34060;"	d
+ID_IN_USE_HI	include/ssv6200_aux.h	7249;"	d
+ID_IN_USE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6424;"	d
+ID_IN_USE_I_MSK	include/ssv6200_aux.h	7247;"	d
+ID_IN_USE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6422;"	d
+ID_IN_USE_MSK	include/ssv6200_aux.h	7246;"	d
+ID_IN_USE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6421;"	d
+ID_IN_USE_SFT	include/ssv6200_aux.h	7248;"	d
+ID_IN_USE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6423;"	d
+ID_IN_USE_SZ	include/ssv6200_aux.h	7250;"	d
+ID_IN_USE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6425;"	d
+ID_LEN_THOLD_HI	include/ssv6200_aux.h	12744;"	d
+ID_LEN_THOLD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34269;"	d
+ID_LEN_THOLD_INT_EN_HI	include/ssv6200_aux.h	12714;"	d
+ID_LEN_THOLD_INT_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34239;"	d
+ID_LEN_THOLD_INT_EN_I_MSK	include/ssv6200_aux.h	12712;"	d
+ID_LEN_THOLD_INT_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34237;"	d
+ID_LEN_THOLD_INT_EN_MSK	include/ssv6200_aux.h	12711;"	d
+ID_LEN_THOLD_INT_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34236;"	d
+ID_LEN_THOLD_INT_EN_SFT	include/ssv6200_aux.h	12713;"	d
+ID_LEN_THOLD_INT_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34238;"	d
+ID_LEN_THOLD_INT_EN_SZ	include/ssv6200_aux.h	12715;"	d
+ID_LEN_THOLD_INT_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34240;"	d
+ID_LEN_THOLD_I_MSK	include/ssv6200_aux.h	12742;"	d
+ID_LEN_THOLD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34267;"	d
+ID_LEN_THOLD_MSK	include/ssv6200_aux.h	12741;"	d
+ID_LEN_THOLD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34266;"	d
+ID_LEN_THOLD_SFT	include/ssv6200_aux.h	12743;"	d
+ID_LEN_THOLD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34268;"	d
+ID_LEN_THOLD_SZ	include/ssv6200_aux.h	12745;"	d
+ID_LEN_THOLD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34270;"	d
+ID_MNG_BUSY_HI	include/ssv6200_aux.h	12539;"	d
+ID_MNG_BUSY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34064;"	d
+ID_MNG_BUSY_I_MSK	include/ssv6200_aux.h	12537;"	d
+ID_MNG_BUSY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34062;"	d
+ID_MNG_BUSY_MSK	include/ssv6200_aux.h	12536;"	d
+ID_MNG_BUSY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34061;"	d
+ID_MNG_BUSY_SFT	include/ssv6200_aux.h	12538;"	d
+ID_MNG_BUSY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34063;"	d
+ID_MNG_BUSY_SZ	include/ssv6200_aux.h	12540;"	d
+ID_MNG_BUSY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34065;"	d
+ID_MNG_CLK_EN_HI	include/ssv6200_aux.h	9019;"	d
+ID_MNG_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8774;"	d
+ID_MNG_CLK_EN_I_MSK	include/ssv6200_aux.h	9017;"	d
+ID_MNG_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8772;"	d
+ID_MNG_CLK_EN_MSK	include/ssv6200_aux.h	9016;"	d
+ID_MNG_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8771;"	d
+ID_MNG_CLK_EN_SFT	include/ssv6200_aux.h	9018;"	d
+ID_MNG_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8773;"	d
+ID_MNG_CLK_EN_SZ	include/ssv6200_aux.h	9020;"	d
+ID_MNG_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8775;"	d
+ID_MNG_CSR_CLK_EN_HI	include/ssv6200_aux.h	9114;"	d
+ID_MNG_CSR_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8869;"	d
+ID_MNG_CSR_CLK_EN_I_MSK	include/ssv6200_aux.h	9112;"	d
+ID_MNG_CSR_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8867;"	d
+ID_MNG_CSR_CLK_EN_MSK	include/ssv6200_aux.h	9111;"	d
+ID_MNG_CSR_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8866;"	d
+ID_MNG_CSR_CLK_EN_SFT	include/ssv6200_aux.h	9113;"	d
+ID_MNG_CSR_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8868;"	d
+ID_MNG_CSR_CLK_EN_SZ	include/ssv6200_aux.h	9115;"	d
+ID_MNG_CSR_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8870;"	d
+ID_MNG_CSR_RST_HI	include/ssv6200_aux.h	8974;"	d
+ID_MNG_CSR_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8729;"	d
+ID_MNG_CSR_RST_I_MSK	include/ssv6200_aux.h	8972;"	d
+ID_MNG_CSR_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8727;"	d
+ID_MNG_CSR_RST_MSK	include/ssv6200_aux.h	8971;"	d
+ID_MNG_CSR_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8726;"	d
+ID_MNG_CSR_RST_SFT	include/ssv6200_aux.h	8973;"	d
+ID_MNG_CSR_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8728;"	d
+ID_MNG_CSR_RST_SZ	include/ssv6200_aux.h	8975;"	d
+ID_MNG_CSR_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8730;"	d
+ID_MNG_ENG_CLK_EN_HI	include/ssv6200_aux.h	9074;"	d
+ID_MNG_ENG_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8829;"	d
+ID_MNG_ENG_CLK_EN_I_MSK	include/ssv6200_aux.h	9072;"	d
+ID_MNG_ENG_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8827;"	d
+ID_MNG_ENG_CLK_EN_MSK	include/ssv6200_aux.h	9071;"	d
+ID_MNG_ENG_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8826;"	d
+ID_MNG_ENG_CLK_EN_SFT	include/ssv6200_aux.h	9073;"	d
+ID_MNG_ENG_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8828;"	d
+ID_MNG_ENG_CLK_EN_SZ	include/ssv6200_aux.h	9075;"	d
+ID_MNG_ENG_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8830;"	d
+ID_MNG_ENG_RST_HI	include/ssv6200_aux.h	8899;"	d
+ID_MNG_ENG_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8654;"	d
+ID_MNG_ENG_RST_I_MSK	include/ssv6200_aux.h	8897;"	d
+ID_MNG_ENG_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8652;"	d
+ID_MNG_ENG_RST_MSK	include/ssv6200_aux.h	8896;"	d
+ID_MNG_ENG_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8651;"	d
+ID_MNG_ENG_RST_SFT	include/ssv6200_aux.h	8898;"	d
+ID_MNG_ENG_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8653;"	d
+ID_MNG_ENG_RST_SZ	include/ssv6200_aux.h	8900;"	d
+ID_MNG_ENG_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8655;"	d
+ID_MNG_ERR_HALT_EN_HI	include/ssv6200_aux.h	12519;"	d
+ID_MNG_ERR_HALT_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34044;"	d
+ID_MNG_ERR_HALT_EN_I_MSK	include/ssv6200_aux.h	12517;"	d
+ID_MNG_ERR_HALT_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34042;"	d
+ID_MNG_ERR_HALT_EN_MSK	include/ssv6200_aux.h	12516;"	d
+ID_MNG_ERR_HALT_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34041;"	d
+ID_MNG_ERR_HALT_EN_SFT	include/ssv6200_aux.h	12518;"	d
+ID_MNG_ERR_HALT_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34043;"	d
+ID_MNG_ERR_HALT_EN_SZ	include/ssv6200_aux.h	12520;"	d
+ID_MNG_ERR_HALT_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34045;"	d
+ID_MNG_HALT_HI	include/ssv6200_aux.h	12514;"	d
+ID_MNG_HALT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34039;"	d
+ID_MNG_HALT_I_MSK	include/ssv6200_aux.h	12512;"	d
+ID_MNG_HALT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34037;"	d
+ID_MNG_HALT_MSK	include/ssv6200_aux.h	12511;"	d
+ID_MNG_HALT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34036;"	d
+ID_MNG_HALT_SFT	include/ssv6200_aux.h	12513;"	d
+ID_MNG_HALT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34038;"	d
+ID_MNG_HALT_SZ	include/ssv6200_aux.h	12515;"	d
+ID_MNG_HALT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34040;"	d
+ID_MNG_INT_1_HI	include/ssv6200_aux.h	4959;"	d
+ID_MNG_INT_1_I_MSK	include/ssv6200_aux.h	4957;"	d
+ID_MNG_INT_1_MSK	include/ssv6200_aux.h	4956;"	d
+ID_MNG_INT_1_SD_HI	include/ssv6200_aux.h	5304;"	d
+ID_MNG_INT_1_SD_I_MSK	include/ssv6200_aux.h	5302;"	d
+ID_MNG_INT_1_SD_MSK	include/ssv6200_aux.h	5301;"	d
+ID_MNG_INT_1_SD_SFT	include/ssv6200_aux.h	5303;"	d
+ID_MNG_INT_1_SD_SZ	include/ssv6200_aux.h	5305;"	d
+ID_MNG_INT_1_SFT	include/ssv6200_aux.h	4958;"	d
+ID_MNG_INT_1_SZ	include/ssv6200_aux.h	4960;"	d
+ID_MNG_INT_2_HI	include/ssv6200_aux.h	4994;"	d
+ID_MNG_INT_2_I_MSK	include/ssv6200_aux.h	4992;"	d
+ID_MNG_INT_2_MSK	include/ssv6200_aux.h	4991;"	d
+ID_MNG_INT_2_SD_HI	include/ssv6200_aux.h	5339;"	d
+ID_MNG_INT_2_SD_I_MSK	include/ssv6200_aux.h	5337;"	d
+ID_MNG_INT_2_SD_MSK	include/ssv6200_aux.h	5336;"	d
+ID_MNG_INT_2_SD_SFT	include/ssv6200_aux.h	5338;"	d
+ID_MNG_INT_2_SD_SZ	include/ssv6200_aux.h	5340;"	d
+ID_MNG_INT_2_SFT	include/ssv6200_aux.h	4993;"	d
+ID_MNG_INT_2_SZ	include/ssv6200_aux.h	4995;"	d
+ID_MNG_REG_BANK_SIZE	include/ssv6200_reg.h	110;"	d
+ID_MNG_REG_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	135;"	d
+ID_MNG_REG_BASE	include/ssv6200_reg.h	61;"	d
+ID_MNG_REG_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	74;"	d
+ID_MNG_SW_RST_HI	include/ssv6200_aux.h	8844;"	d
+ID_MNG_SW_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8599;"	d
+ID_MNG_SW_RST_I_MSK	include/ssv6200_aux.h	8842;"	d
+ID_MNG_SW_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8597;"	d
+ID_MNG_SW_RST_MSK	include/ssv6200_aux.h	8841;"	d
+ID_MNG_SW_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8596;"	d
+ID_MNG_SW_RST_SFT	include/ssv6200_aux.h	8843;"	d
+ID_MNG_SW_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8598;"	d
+ID_MNG_SW_RST_SZ	include/ssv6200_aux.h	8845;"	d
+ID_MNG_SW_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8600;"	d
+ID_PAGE_MAX_SIZE_HI	include/ssv6200_aux.h	12799;"	d
+ID_PAGE_MAX_SIZE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34324;"	d
+ID_PAGE_MAX_SIZE_I_MSK	include/ssv6200_aux.h	12797;"	d
+ID_PAGE_MAX_SIZE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34322;"	d
+ID_PAGE_MAX_SIZE_MSK	include/ssv6200_aux.h	12796;"	d
+ID_PAGE_MAX_SIZE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34321;"	d
+ID_PAGE_MAX_SIZE_SFT	include/ssv6200_aux.h	12798;"	d
+ID_PAGE_MAX_SIZE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34323;"	d
+ID_PAGE_MAX_SIZE_SZ	include/ssv6200_aux.h	12800;"	d
+ID_PAGE_MAX_SIZE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34325;"	d
+ID_RX_LEN_THOLD_HI	include/ssv6200_aux.h	12739;"	d
+ID_RX_LEN_THOLD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34264;"	d
+ID_RX_LEN_THOLD_I_MSK	include/ssv6200_aux.h	12737;"	d
+ID_RX_LEN_THOLD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34262;"	d
+ID_RX_LEN_THOLD_MSK	include/ssv6200_aux.h	12736;"	d
+ID_RX_LEN_THOLD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34261;"	d
+ID_RX_LEN_THOLD_SFT	include/ssv6200_aux.h	12738;"	d
+ID_RX_LEN_THOLD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34263;"	d
+ID_RX_LEN_THOLD_SZ	include/ssv6200_aux.h	12740;"	d
+ID_RX_LEN_THOLD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34265;"	d
+ID_TB0_HI	include/ssv6200_aux.h	12504;"	d
+ID_TB0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34029;"	d
+ID_TB0_I_MSK	include/ssv6200_aux.h	12502;"	d
+ID_TB0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34027;"	d
+ID_TB0_MSK	include/ssv6200_aux.h	12501;"	d
+ID_TB0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34026;"	d
+ID_TB0_SFT	include/ssv6200_aux.h	12503;"	d
+ID_TB0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34028;"	d
+ID_TB0_SZ	include/ssv6200_aux.h	12505;"	d
+ID_TB0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34030;"	d
+ID_TB1_HI	include/ssv6200_aux.h	12509;"	d
+ID_TB1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34034;"	d
+ID_TB1_I_MSK	include/ssv6200_aux.h	12507;"	d
+ID_TB1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34032;"	d
+ID_TB1_MSK	include/ssv6200_aux.h	12506;"	d
+ID_TB1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34031;"	d
+ID_TB1_SFT	include/ssv6200_aux.h	12508;"	d
+ID_TB1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34033;"	d
+ID_TB1_SZ	include/ssv6200_aux.h	12510;"	d
+ID_TB1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34035;"	d
+ID_TB2_HI	include/ssv6200_aux.h	12854;"	d
+ID_TB2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34379;"	d
+ID_TB2_I_MSK	include/ssv6200_aux.h	12852;"	d
+ID_TB2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34377;"	d
+ID_TB2_MSK	include/ssv6200_aux.h	12851;"	d
+ID_TB2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34376;"	d
+ID_TB2_SFT	include/ssv6200_aux.h	12853;"	d
+ID_TB2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34378;"	d
+ID_TB2_SZ	include/ssv6200_aux.h	12855;"	d
+ID_TB2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34380;"	d
+ID_TB3_HI	include/ssv6200_aux.h	12859;"	d
+ID_TB3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34384;"	d
+ID_TB3_I_MSK	include/ssv6200_aux.h	12857;"	d
+ID_TB3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34382;"	d
+ID_TB3_MSK	include/ssv6200_aux.h	12856;"	d
+ID_TB3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34381;"	d
+ID_TB3_SFT	include/ssv6200_aux.h	12858;"	d
+ID_TB3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34383;"	d
+ID_TB3_SZ	include/ssv6200_aux.h	12860;"	d
+ID_TB3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34385;"	d
+ID_THOLD_INT_EN_HI	include/ssv6200_aux.h	12674;"	d
+ID_THOLD_INT_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34199;"	d
+ID_THOLD_INT_EN_I_MSK	include/ssv6200_aux.h	12672;"	d
+ID_THOLD_INT_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34197;"	d
+ID_THOLD_INT_EN_MSK	include/ssv6200_aux.h	12671;"	d
+ID_THOLD_INT_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34196;"	d
+ID_THOLD_INT_EN_SFT	include/ssv6200_aux.h	12673;"	d
+ID_THOLD_INT_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34198;"	d
+ID_THOLD_INT_EN_SZ	include/ssv6200_aux.h	12675;"	d
+ID_THOLD_INT_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34200;"	d
+ID_THOLD_RX_HI	include/ssv6200_aux.h	5004;"	d
+ID_THOLD_RX_INT_HI	include/ssv6200_aux.h	12654;"	d
+ID_THOLD_RX_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34179;"	d
+ID_THOLD_RX_INT_I_MSK	include/ssv6200_aux.h	12652;"	d
+ID_THOLD_RX_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34177;"	d
+ID_THOLD_RX_INT_MSK	include/ssv6200_aux.h	12651;"	d
+ID_THOLD_RX_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34176;"	d
+ID_THOLD_RX_INT_SFT	include/ssv6200_aux.h	12653;"	d
+ID_THOLD_RX_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34178;"	d
+ID_THOLD_RX_INT_SZ	include/ssv6200_aux.h	12655;"	d
+ID_THOLD_RX_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34180;"	d
+ID_THOLD_RX_I_MSK	include/ssv6200_aux.h	5002;"	d
+ID_THOLD_RX_MSK	include/ssv6200_aux.h	5001;"	d
+ID_THOLD_RX_SD_HI	include/ssv6200_aux.h	5349;"	d
+ID_THOLD_RX_SD_I_MSK	include/ssv6200_aux.h	5347;"	d
+ID_THOLD_RX_SD_MSK	include/ssv6200_aux.h	5346;"	d
+ID_THOLD_RX_SD_SFT	include/ssv6200_aux.h	5348;"	d
+ID_THOLD_RX_SD_SZ	include/ssv6200_aux.h	5350;"	d
+ID_THOLD_RX_SFT	include/ssv6200_aux.h	5003;"	d
+ID_THOLD_RX_SZ	include/ssv6200_aux.h	5005;"	d
+ID_THOLD_TX_HI	include/ssv6200_aux.h	5009;"	d
+ID_THOLD_TX_INT_HI	include/ssv6200_aux.h	12664;"	d
+ID_THOLD_TX_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34189;"	d
+ID_THOLD_TX_INT_I_MSK	include/ssv6200_aux.h	12662;"	d
+ID_THOLD_TX_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34187;"	d
+ID_THOLD_TX_INT_MSK	include/ssv6200_aux.h	12661;"	d
+ID_THOLD_TX_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34186;"	d
+ID_THOLD_TX_INT_SFT	include/ssv6200_aux.h	12663;"	d
+ID_THOLD_TX_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34188;"	d
+ID_THOLD_TX_INT_SZ	include/ssv6200_aux.h	12665;"	d
+ID_THOLD_TX_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34190;"	d
+ID_THOLD_TX_I_MSK	include/ssv6200_aux.h	5007;"	d
+ID_THOLD_TX_MSK	include/ssv6200_aux.h	5006;"	d
+ID_THOLD_TX_SD_HI	include/ssv6200_aux.h	5354;"	d
+ID_THOLD_TX_SD_I_MSK	include/ssv6200_aux.h	5352;"	d
+ID_THOLD_TX_SD_MSK	include/ssv6200_aux.h	5351;"	d
+ID_THOLD_TX_SD_SFT	include/ssv6200_aux.h	5353;"	d
+ID_THOLD_TX_SD_SZ	include/ssv6200_aux.h	5355;"	d
+ID_THOLD_TX_SFT	include/ssv6200_aux.h	5008;"	d
+ID_THOLD_TX_SZ	include/ssv6200_aux.h	5010;"	d
+ID_TRAP_SW_TXTPUT	include/ssv6200_common.h	48;"	d
+ID_TRAP_SW_TXTPUT	smac/hal/ssv6006c/ssv6006_common.h	48;"	d
+ID_TX_LEN_THOLD_HI	include/ssv6200_aux.h	12734;"	d
+ID_TX_LEN_THOLD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34259;"	d
+ID_TX_LEN_THOLD_I_MSK	include/ssv6200_aux.h	12732;"	d
+ID_TX_LEN_THOLD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34257;"	d
+ID_TX_LEN_THOLD_MSK	include/ssv6200_aux.h	12731;"	d
+ID_TX_LEN_THOLD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34256;"	d
+ID_TX_LEN_THOLD_SFT	include/ssv6200_aux.h	12733;"	d
+ID_TX_LEN_THOLD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34258;"	d
+ID_TX_LEN_THOLD_SZ	include/ssv6200_aux.h	12735;"	d
+ID_TX_LEN_THOLD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34260;"	d
+IEEE80211_AC_BE	smac/linux_2_6_35.h	/^ IEEE80211_AC_BE = 2,$/;"	e	enum:ieee80211_ac_numbers
+IEEE80211_AC_BK	smac/linux_2_6_35.h	/^ IEEE80211_AC_BK = 3,$/;"	e	enum:ieee80211_ac_numbers
+IEEE80211_AC_VI	smac/linux_2_6_35.h	/^ IEEE80211_AC_VI = 1,$/;"	e	enum:ieee80211_ac_numbers
+IEEE80211_AC_VO	smac/linux_2_6_35.h	/^ IEEE80211_AC_VO = 0,$/;"	e	enum:ieee80211_ac_numbers
+IEEE80211_AMPDU_BA_LEN	smac/ampdu.h	60;"	d
+IEEE80211_CONF_OFFCHANNEL	smac/linux_2_6_35.h	32;"	d
+IEEE80211_HDRLEN	smac/p2p.c	56;"	d	file:
+IEEE80211_NUM_ACS	smac/linux_2_6_35.h	29;"	d
+IEEE80211_SEQ_SEQ_SHIFT	smac/ampdu.h	59;"	d
+IFDEV	hci/hctrl.h	28;"	d
+IFOPS	hci/hctrl.h	29;"	d
+IF_RECV	hci/hctrl.h	47;"	d
+IF_SEND	hci/hctrl.h	46;"	d
+ILLEGAL_CMD_RESP_OPTION_HI	include/ssv6200_aux.h	3149;"	d
+ILLEGAL_CMD_RESP_OPTION_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2619;"	d
+ILLEGAL_CMD_RESP_OPTION_I_MSK	include/ssv6200_aux.h	3147;"	d
+ILLEGAL_CMD_RESP_OPTION_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2617;"	d
+ILLEGAL_CMD_RESP_OPTION_MSK	include/ssv6200_aux.h	3146;"	d
+ILLEGAL_CMD_RESP_OPTION_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2616;"	d
+ILLEGAL_CMD_RESP_OPTION_SFT	include/ssv6200_aux.h	3148;"	d
+ILLEGAL_CMD_RESP_OPTION_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2618;"	d
+ILLEGAL_CMD_RESP_OPTION_SZ	include/ssv6200_aux.h	3150;"	d
+ILLEGAL_CMD_RESP_OPTION_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2620;"	d
+ILL_ADDR_CLR_HI	include/ssv6200_aux.h	459;"	d
+ILL_ADDR_CLR_I_MSK	include/ssv6200_aux.h	457;"	d
+ILL_ADDR_CLR_MSK	include/ssv6200_aux.h	456;"	d
+ILL_ADDR_CLR_SFT	include/ssv6200_aux.h	458;"	d
+ILL_ADDR_CLR_SZ	include/ssv6200_aux.h	460;"	d
+ILL_ADDR_INT_HI	include/ssv6200_aux.h	469;"	d
+ILL_ADDR_INT_I_MSK	include/ssv6200_aux.h	467;"	d
+ILL_ADDR_INT_MSK	include/ssv6200_aux.h	466;"	d
+ILL_ADDR_INT_SFT	include/ssv6200_aux.h	468;"	d
+ILL_ADDR_INT_SZ	include/ssv6200_aux.h	470;"	d
+ILM160KB_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1789;"	d
+ILM160KB_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1787;"	d
+ILM160KB_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1786;"	d
+ILM160KB_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1788;"	d
+ILM160KB_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1790;"	d
+INC_PKT_SN	smac/ampdu.c	44;"	d	file:
+INDEX_80211_BAND_2GHZ	include/linux_80211.h	19;"	d
+INDEX_80211_BAND_2GHZ	include/linux_80211.h	23;"	d
+INDEX_80211_BAND_5GHZ	include/linux_80211.h	20;"	d
+INDEX_80211_BAND_5GHZ	include/linux_80211.h	24;"	d
+INDEX_80211_BAND_60GHZ	include/linux_80211.h	21;"	d
+INDEX_80211_BAND_60GHZ	include/linux_80211.h	25;"	d
+INDEX_PKT_BY_SSN	smac/dev.h	88;"	d
+INDICATOR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4029;"	d
+INDICATOR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4027;"	d
+INDICATOR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4026;"	d
+INDICATOR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4028;"	d
+INDICATOR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4030;"	d
+INFO0_HI	include/ssv6200_aux.h	8514;"	d
+INFO0_I_MSK	include/ssv6200_aux.h	8512;"	d
+INFO0_MSK	include/ssv6200_aux.h	8511;"	d
+INFO0_SFT	include/ssv6200_aux.h	8513;"	d
+INFO0_SZ	include/ssv6200_aux.h	8515;"	d
+INFO10_HI	include/ssv6200_aux.h	8564;"	d
+INFO10_I_MSK	include/ssv6200_aux.h	8562;"	d
+INFO10_MSK	include/ssv6200_aux.h	8561;"	d
+INFO10_SFT	include/ssv6200_aux.h	8563;"	d
+INFO10_SZ	include/ssv6200_aux.h	8565;"	d
+INFO11_HI	include/ssv6200_aux.h	8569;"	d
+INFO11_I_MSK	include/ssv6200_aux.h	8567;"	d
+INFO11_MSK	include/ssv6200_aux.h	8566;"	d
+INFO11_SFT	include/ssv6200_aux.h	8568;"	d
+INFO11_SZ	include/ssv6200_aux.h	8570;"	d
+INFO12_HI	include/ssv6200_aux.h	8574;"	d
+INFO12_I_MSK	include/ssv6200_aux.h	8572;"	d
+INFO12_MSK	include/ssv6200_aux.h	8571;"	d
+INFO12_SFT	include/ssv6200_aux.h	8573;"	d
+INFO12_SZ	include/ssv6200_aux.h	8575;"	d
+INFO13_HI	include/ssv6200_aux.h	8579;"	d
+INFO13_I_MSK	include/ssv6200_aux.h	8577;"	d
+INFO13_MSK	include/ssv6200_aux.h	8576;"	d
+INFO13_SFT	include/ssv6200_aux.h	8578;"	d
+INFO13_SZ	include/ssv6200_aux.h	8580;"	d
+INFO14_HI	include/ssv6200_aux.h	8584;"	d
+INFO14_I_MSK	include/ssv6200_aux.h	8582;"	d
+INFO14_MSK	include/ssv6200_aux.h	8581;"	d
+INFO14_SFT	include/ssv6200_aux.h	8583;"	d
+INFO14_SZ	include/ssv6200_aux.h	8585;"	d
+INFO15_HI	include/ssv6200_aux.h	8589;"	d
+INFO15_I_MSK	include/ssv6200_aux.h	8587;"	d
+INFO15_MSK	include/ssv6200_aux.h	8586;"	d
+INFO15_SFT	include/ssv6200_aux.h	8588;"	d
+INFO15_SZ	include/ssv6200_aux.h	8590;"	d
+INFO16_HI	include/ssv6200_aux.h	8594;"	d
+INFO16_I_MSK	include/ssv6200_aux.h	8592;"	d
+INFO16_MSK	include/ssv6200_aux.h	8591;"	d
+INFO16_SFT	include/ssv6200_aux.h	8593;"	d
+INFO16_SZ	include/ssv6200_aux.h	8595;"	d
+INFO17_HI	include/ssv6200_aux.h	8599;"	d
+INFO17_I_MSK	include/ssv6200_aux.h	8597;"	d
+INFO17_MSK	include/ssv6200_aux.h	8596;"	d
+INFO17_SFT	include/ssv6200_aux.h	8598;"	d
+INFO17_SZ	include/ssv6200_aux.h	8600;"	d
+INFO18_HI	include/ssv6200_aux.h	8604;"	d
+INFO18_I_MSK	include/ssv6200_aux.h	8602;"	d
+INFO18_MSK	include/ssv6200_aux.h	8601;"	d
+INFO18_SFT	include/ssv6200_aux.h	8603;"	d
+INFO18_SZ	include/ssv6200_aux.h	8605;"	d
+INFO19_HI	include/ssv6200_aux.h	8609;"	d
+INFO19_I_MSK	include/ssv6200_aux.h	8607;"	d
+INFO19_MSK	include/ssv6200_aux.h	8606;"	d
+INFO19_SFT	include/ssv6200_aux.h	8608;"	d
+INFO19_SZ	include/ssv6200_aux.h	8610;"	d
+INFO1_HI	include/ssv6200_aux.h	8519;"	d
+INFO1_I_MSK	include/ssv6200_aux.h	8517;"	d
+INFO1_MSK	include/ssv6200_aux.h	8516;"	d
+INFO1_SFT	include/ssv6200_aux.h	8518;"	d
+INFO1_SZ	include/ssv6200_aux.h	8520;"	d
+INFO20_HI	include/ssv6200_aux.h	8614;"	d
+INFO20_I_MSK	include/ssv6200_aux.h	8612;"	d
+INFO20_MSK	include/ssv6200_aux.h	8611;"	d
+INFO20_SFT	include/ssv6200_aux.h	8613;"	d
+INFO20_SZ	include/ssv6200_aux.h	8615;"	d
+INFO21_HI	include/ssv6200_aux.h	8619;"	d
+INFO21_I_MSK	include/ssv6200_aux.h	8617;"	d
+INFO21_MSK	include/ssv6200_aux.h	8616;"	d
+INFO21_SFT	include/ssv6200_aux.h	8618;"	d
+INFO21_SZ	include/ssv6200_aux.h	8620;"	d
+INFO22_HI	include/ssv6200_aux.h	8624;"	d
+INFO22_I_MSK	include/ssv6200_aux.h	8622;"	d
+INFO22_MSK	include/ssv6200_aux.h	8621;"	d
+INFO22_SFT	include/ssv6200_aux.h	8623;"	d
+INFO22_SZ	include/ssv6200_aux.h	8625;"	d
+INFO23_HI	include/ssv6200_aux.h	8629;"	d
+INFO23_I_MSK	include/ssv6200_aux.h	8627;"	d
+INFO23_MSK	include/ssv6200_aux.h	8626;"	d
+INFO23_SFT	include/ssv6200_aux.h	8628;"	d
+INFO23_SZ	include/ssv6200_aux.h	8630;"	d
+INFO24_HI	include/ssv6200_aux.h	8634;"	d
+INFO24_I_MSK	include/ssv6200_aux.h	8632;"	d
+INFO24_MSK	include/ssv6200_aux.h	8631;"	d
+INFO24_SFT	include/ssv6200_aux.h	8633;"	d
+INFO24_SZ	include/ssv6200_aux.h	8635;"	d
+INFO25_HI	include/ssv6200_aux.h	8639;"	d
+INFO25_I_MSK	include/ssv6200_aux.h	8637;"	d
+INFO25_MSK	include/ssv6200_aux.h	8636;"	d
+INFO25_SFT	include/ssv6200_aux.h	8638;"	d
+INFO25_SZ	include/ssv6200_aux.h	8640;"	d
+INFO26_HI	include/ssv6200_aux.h	8644;"	d
+INFO26_I_MSK	include/ssv6200_aux.h	8642;"	d
+INFO26_MSK	include/ssv6200_aux.h	8641;"	d
+INFO26_SFT	include/ssv6200_aux.h	8643;"	d
+INFO26_SZ	include/ssv6200_aux.h	8645;"	d
+INFO27_HI	include/ssv6200_aux.h	8649;"	d
+INFO27_I_MSK	include/ssv6200_aux.h	8647;"	d
+INFO27_MSK	include/ssv6200_aux.h	8646;"	d
+INFO27_SFT	include/ssv6200_aux.h	8648;"	d
+INFO27_SZ	include/ssv6200_aux.h	8650;"	d
+INFO28_HI	include/ssv6200_aux.h	8654;"	d
+INFO28_I_MSK	include/ssv6200_aux.h	8652;"	d
+INFO28_MSK	include/ssv6200_aux.h	8651;"	d
+INFO28_SFT	include/ssv6200_aux.h	8653;"	d
+INFO28_SZ	include/ssv6200_aux.h	8655;"	d
+INFO29_HI	include/ssv6200_aux.h	8659;"	d
+INFO29_I_MSK	include/ssv6200_aux.h	8657;"	d
+INFO29_MSK	include/ssv6200_aux.h	8656;"	d
+INFO29_SFT	include/ssv6200_aux.h	8658;"	d
+INFO29_SZ	include/ssv6200_aux.h	8660;"	d
+INFO2_HI	include/ssv6200_aux.h	8524;"	d
+INFO2_I_MSK	include/ssv6200_aux.h	8522;"	d
+INFO2_MSK	include/ssv6200_aux.h	8521;"	d
+INFO2_SFT	include/ssv6200_aux.h	8523;"	d
+INFO2_SZ	include/ssv6200_aux.h	8525;"	d
+INFO30_HI	include/ssv6200_aux.h	8664;"	d
+INFO30_I_MSK	include/ssv6200_aux.h	8662;"	d
+INFO30_MSK	include/ssv6200_aux.h	8661;"	d
+INFO30_SFT	include/ssv6200_aux.h	8663;"	d
+INFO30_SZ	include/ssv6200_aux.h	8665;"	d
+INFO31_HI	include/ssv6200_aux.h	8669;"	d
+INFO31_I_MSK	include/ssv6200_aux.h	8667;"	d
+INFO31_MSK	include/ssv6200_aux.h	8666;"	d
+INFO31_SFT	include/ssv6200_aux.h	8668;"	d
+INFO31_SZ	include/ssv6200_aux.h	8670;"	d
+INFO32_HI	include/ssv6200_aux.h	8674;"	d
+INFO32_I_MSK	include/ssv6200_aux.h	8672;"	d
+INFO32_MSK	include/ssv6200_aux.h	8671;"	d
+INFO32_SFT	include/ssv6200_aux.h	8673;"	d
+INFO32_SZ	include/ssv6200_aux.h	8675;"	d
+INFO33_HI	include/ssv6200_aux.h	8679;"	d
+INFO33_I_MSK	include/ssv6200_aux.h	8677;"	d
+INFO33_MSK	include/ssv6200_aux.h	8676;"	d
+INFO33_SFT	include/ssv6200_aux.h	8678;"	d
+INFO33_SZ	include/ssv6200_aux.h	8680;"	d
+INFO34_HI	include/ssv6200_aux.h	8684;"	d
+INFO34_I_MSK	include/ssv6200_aux.h	8682;"	d
+INFO34_MSK	include/ssv6200_aux.h	8681;"	d
+INFO34_SFT	include/ssv6200_aux.h	8683;"	d
+INFO34_SZ	include/ssv6200_aux.h	8685;"	d
+INFO35_HI	include/ssv6200_aux.h	8689;"	d
+INFO35_I_MSK	include/ssv6200_aux.h	8687;"	d
+INFO35_MSK	include/ssv6200_aux.h	8686;"	d
+INFO35_SFT	include/ssv6200_aux.h	8688;"	d
+INFO35_SZ	include/ssv6200_aux.h	8690;"	d
+INFO36_HI	include/ssv6200_aux.h	8694;"	d
+INFO36_I_MSK	include/ssv6200_aux.h	8692;"	d
+INFO36_MSK	include/ssv6200_aux.h	8691;"	d
+INFO36_SFT	include/ssv6200_aux.h	8693;"	d
+INFO36_SZ	include/ssv6200_aux.h	8695;"	d
+INFO37_HI	include/ssv6200_aux.h	8699;"	d
+INFO37_I_MSK	include/ssv6200_aux.h	8697;"	d
+INFO37_MSK	include/ssv6200_aux.h	8696;"	d
+INFO37_SFT	include/ssv6200_aux.h	8698;"	d
+INFO37_SZ	include/ssv6200_aux.h	8700;"	d
+INFO38_HI	include/ssv6200_aux.h	8704;"	d
+INFO38_I_MSK	include/ssv6200_aux.h	8702;"	d
+INFO38_MSK	include/ssv6200_aux.h	8701;"	d
+INFO38_SFT	include/ssv6200_aux.h	8703;"	d
+INFO38_SZ	include/ssv6200_aux.h	8705;"	d
+INFO3_HI	include/ssv6200_aux.h	8529;"	d
+INFO3_I_MSK	include/ssv6200_aux.h	8527;"	d
+INFO3_MSK	include/ssv6200_aux.h	8526;"	d
+INFO3_SFT	include/ssv6200_aux.h	8528;"	d
+INFO3_SZ	include/ssv6200_aux.h	8530;"	d
+INFO4_HI	include/ssv6200_aux.h	8534;"	d
+INFO4_I_MSK	include/ssv6200_aux.h	8532;"	d
+INFO4_MSK	include/ssv6200_aux.h	8531;"	d
+INFO4_SFT	include/ssv6200_aux.h	8533;"	d
+INFO4_SZ	include/ssv6200_aux.h	8535;"	d
+INFO5_HI	include/ssv6200_aux.h	8539;"	d
+INFO5_I_MSK	include/ssv6200_aux.h	8537;"	d
+INFO5_MSK	include/ssv6200_aux.h	8536;"	d
+INFO5_SFT	include/ssv6200_aux.h	8538;"	d
+INFO5_SZ	include/ssv6200_aux.h	8540;"	d
+INFO6_HI	include/ssv6200_aux.h	8544;"	d
+INFO6_I_MSK	include/ssv6200_aux.h	8542;"	d
+INFO6_MSK	include/ssv6200_aux.h	8541;"	d
+INFO6_SFT	include/ssv6200_aux.h	8543;"	d
+INFO6_SZ	include/ssv6200_aux.h	8545;"	d
+INFO7_HI	include/ssv6200_aux.h	8549;"	d
+INFO7_I_MSK	include/ssv6200_aux.h	8547;"	d
+INFO7_MSK	include/ssv6200_aux.h	8546;"	d
+INFO7_SFT	include/ssv6200_aux.h	8548;"	d
+INFO7_SZ	include/ssv6200_aux.h	8550;"	d
+INFO8_HI	include/ssv6200_aux.h	8554;"	d
+INFO8_I_MSK	include/ssv6200_aux.h	8552;"	d
+INFO8_MSK	include/ssv6200_aux.h	8551;"	d
+INFO8_SFT	include/ssv6200_aux.h	8553;"	d
+INFO8_SZ	include/ssv6200_aux.h	8555;"	d
+INFO9_HI	include/ssv6200_aux.h	8559;"	d
+INFO9_I_MSK	include/ssv6200_aux.h	8557;"	d
+INFO9_MSK	include/ssv6200_aux.h	8556;"	d
+INFO9_SFT	include/ssv6200_aux.h	8558;"	d
+INFO9_SZ	include/ssv6200_aux.h	8560;"	d
+INFO_DEF_RATE_HI	include/ssv6200_aux.h	8714;"	d
+INFO_DEF_RATE_I_MSK	include/ssv6200_aux.h	8712;"	d
+INFO_DEF_RATE_MSK	include/ssv6200_aux.h	8711;"	d
+INFO_DEF_RATE_SFT	include/ssv6200_aux.h	8713;"	d
+INFO_DEF_RATE_SZ	include/ssv6200_aux.h	8715;"	d
+INFO_IDX_TBL_ADDR_HI	include/ssv6200_aux.h	8729;"	d
+INFO_IDX_TBL_ADDR_I_MSK	include/ssv6200_aux.h	8727;"	d
+INFO_IDX_TBL_ADDR_MSK	include/ssv6200_aux.h	8726;"	d
+INFO_IDX_TBL_ADDR_SFT	include/ssv6200_aux.h	8728;"	d
+INFO_IDX_TBL_ADDR_SZ	include/ssv6200_aux.h	8730;"	d
+INFO_LEN_TBL_ADDR_HI	include/ssv6200_aux.h	8734;"	d
+INFO_LEN_TBL_ADDR_I_MSK	include/ssv6200_aux.h	8732;"	d
+INFO_LEN_TBL_ADDR_MSK	include/ssv6200_aux.h	8731;"	d
+INFO_LEN_TBL_ADDR_SFT	include/ssv6200_aux.h	8733;"	d
+INFO_LEN_TBL_ADDR_SZ	include/ssv6200_aux.h	8735;"	d
+INFO_MASK_HI	include/ssv6200_aux.h	8709;"	d
+INFO_MASK_I_MSK	include/ssv6200_aux.h	8707;"	d
+INFO_MASK_MSK	include/ssv6200_aux.h	8706;"	d
+INFO_MASK_SFT	include/ssv6200_aux.h	8708;"	d
+INFO_MASK_SZ	include/ssv6200_aux.h	8710;"	d
+INFO_MRX_OFFSET_HI	include/ssv6200_aux.h	8719;"	d
+INFO_MRX_OFFSET_I_MSK	include/ssv6200_aux.h	8717;"	d
+INFO_MRX_OFFSET_MSK	include/ssv6200_aux.h	8716;"	d
+INFO_MRX_OFFSET_SFT	include/ssv6200_aux.h	8718;"	d
+INFO_MRX_OFFSET_SZ	include/ssv6200_aux.h	8720;"	d
+INIT_TURISMOA_SYS	smac/hal/ssv6006c/turismo_common.h	1020;"	d
+INIT_TURISMOB_SYS	smac/hal/ssv6006c/turismo_common.h	1681;"	d
+INIT_TURISMOC_SYS	smac/hal/ssv6006c/turismo_common.h	2909;"	d
+INIT_TURISMOC_SYS_IQK	smac/hal/ssv6006c/turismo_common.h	2923;"	d
+INIT_WRITE_CRYPTO_DATA	smac/dev.h	1095;"	d
+INIT_WRITE_CRYPTO_DATA	smac/dev.h	1115;"	d
+INS_BUF_CLR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4174;"	d
+INS_BUF_CLR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4172;"	d
+INS_BUF_CLR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4171;"	d
+INS_BUF_CLR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4173;"	d
+INS_BUF_CLR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4175;"	d
+INS_END_ADDR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4169;"	d
+INS_END_ADDR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4167;"	d
+INS_END_ADDR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4166;"	d
+INS_END_ADDR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4168;"	d
+INS_END_ADDR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4170;"	d
+INS_START_ADDR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4164;"	d
+INS_START_ADDR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4162;"	d
+INS_START_ADDR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4161;"	d
+INS_START_ADDR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4163;"	d
+INS_START_ADDR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4165;"	d
+INTR_GPI00_CFG_HI	include/ssv6200_aux.h	5074;"	d
+INTR_GPI00_CFG_I_MSK	include/ssv6200_aux.h	5072;"	d
+INTR_GPI00_CFG_MSK	include/ssv6200_aux.h	5071;"	d
+INTR_GPI00_CFG_SFT	include/ssv6200_aux.h	5073;"	d
+INTR_GPI00_CFG_SZ	include/ssv6200_aux.h	5075;"	d
+INTR_GPI01_CFG_HI	include/ssv6200_aux.h	5079;"	d
+INTR_GPI01_CFG_I_MSK	include/ssv6200_aux.h	5077;"	d
+INTR_GPI01_CFG_MSK	include/ssv6200_aux.h	5076;"	d
+INTR_GPI01_CFG_SFT	include/ssv6200_aux.h	5078;"	d
+INTR_GPI01_CFG_SZ	include/ssv6200_aux.h	5080;"	d
+INTR_PERI_RAW_HI	include/ssv6200_aux.h	5069;"	d
+INTR_PERI_RAW_I_MSK	include/ssv6200_aux.h	5067;"	d
+INTR_PERI_RAW_MSK	include/ssv6200_aux.h	5066;"	d
+INTR_PERI_RAW_SFT	include/ssv6200_aux.h	5068;"	d
+INTR_PERI_RAW_SZ	include/ssv6200_aux.h	5070;"	d
+INTR_RX_HI	include/ssv6200_aux.h	3524;"	d
+INTR_RX_I_MSK	include/ssv6200_aux.h	3522;"	d
+INTR_RX_MSK	include/ssv6200_aux.h	3521;"	d
+INTR_RX_SFT	include/ssv6200_aux.h	3523;"	d
+INTR_RX_SZ	include/ssv6200_aux.h	3525;"	d
+INT_ALC_TIMEOUT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4714;"	d
+INT_ALC_TIMEOUT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4712;"	d
+INT_ALC_TIMEOUT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4711;"	d
+INT_ALC_TIMEOUT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4713;"	d
+INT_ALC_TIMEOUT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4715;"	d
+INT_ALL_ID_LEN_THOLD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4754;"	d
+INT_ALL_ID_LEN_THOLD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4752;"	d
+INT_ALL_ID_LEN_THOLD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4751;"	d
+INT_ALL_ID_LEN_THOLD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4753;"	d
+INT_ALL_ID_LEN_THOLD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4755;"	d
+INT_BROWNOUT_LOWBATTERY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5094;"	d
+INT_BROWNOUT_LOWBATTERY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5092;"	d
+INT_BROWNOUT_LOWBATTERY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5091;"	d
+INT_BROWNOUT_LOWBATTERY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5093;"	d
+INT_BROWNOUT_LOWBATTERY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5095;"	d
+INT_CO_DMA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4879;"	d
+INT_CO_DMA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4877;"	d
+INT_CO_DMA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4876;"	d
+INT_CO_DMA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4878;"	d
+INT_CO_DMA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4880;"	d
+INT_CPU_ALT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4819;"	d
+INT_CPU_ALT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4817;"	d
+INT_CPU_ALT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4816;"	d
+INT_CPU_ALT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4818;"	d
+INT_CPU_ALT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4820;"	d
+INT_CPU_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4824;"	d
+INT_CPU_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4822;"	d
+INT_CPU_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4821;"	d
+INT_CPU_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4823;"	d
+INT_CPU_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4825;"	d
+INT_CTL_CLK_EN_HI	include/ssv6200_aux.h	234;"	d
+INT_CTL_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1184;"	d
+INT_CTL_CLK_EN_I_MSK	include/ssv6200_aux.h	232;"	d
+INT_CTL_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1182;"	d
+INT_CTL_CLK_EN_MSK	include/ssv6200_aux.h	231;"	d
+INT_CTL_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1181;"	d
+INT_CTL_CLK_EN_SFT	include/ssv6200_aux.h	233;"	d
+INT_CTL_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1183;"	d
+INT_CTL_CLK_EN_SZ	include/ssv6200_aux.h	235;"	d
+INT_CTL_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1185;"	d
+INT_CTL_SW_RST_HI	include/ssv6200_aux.h	64;"	d
+INT_CTL_SW_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1019;"	d
+INT_CTL_SW_RST_I_MSK	include/ssv6200_aux.h	62;"	d
+INT_CTL_SW_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1017;"	d
+INT_CTL_SW_RST_MSK	include/ssv6200_aux.h	61;"	d
+INT_CTL_SW_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1016;"	d
+INT_CTL_SW_RST_SFT	include/ssv6200_aux.h	63;"	d
+INT_CTL_SW_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1018;"	d
+INT_CTL_SW_RST_SZ	include/ssv6200_aux.h	65;"	d
+INT_CTL_SW_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1020;"	d
+INT_CTRL_REG_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	105;"	d
+INT_CTRL_REG_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	44;"	d
+INT_DMAC_INT_COMBINED_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4809;"	d
+INT_DMAC_INT_COMBINED_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4807;"	d
+INT_DMAC_INT_COMBINED_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4806;"	d
+INT_DMAC_INT_COMBINED_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4808;"	d
+INT_DMAC_INT_COMBINED_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4810;"	d
+INT_EDCA0_LOWTHOLD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4769;"	d
+INT_EDCA0_LOWTHOLD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4767;"	d
+INT_EDCA0_LOWTHOLD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4766;"	d
+INT_EDCA0_LOWTHOLD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4768;"	d
+INT_EDCA0_LOWTHOLD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4770;"	d
+INT_EDCA1_LOWTHOLD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4774;"	d
+INT_EDCA1_LOWTHOLD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4772;"	d
+INT_EDCA1_LOWTHOLD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4771;"	d
+INT_EDCA1_LOWTHOLD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4773;"	d
+INT_EDCA1_LOWTHOLD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4775;"	d
+INT_EDCA2_LOWTHOLD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4779;"	d
+INT_EDCA2_LOWTHOLD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4777;"	d
+INT_EDCA2_LOWTHOLD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4776;"	d
+INT_EDCA2_LOWTHOLD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4778;"	d
+INT_EDCA2_LOWTHOLD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4780;"	d
+INT_EDCA3_LOWTHOLD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4784;"	d
+INT_EDCA3_LOWTHOLD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4782;"	d
+INT_EDCA3_LOWTHOLD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4781;"	d
+INT_EDCA3_LOWTHOLD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4783;"	d
+INT_EDCA3_LOWTHOLD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4785;"	d
+INT_FBUSDMAC_INT_COMBINED_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4804;"	d
+INT_FBUSDMAC_INT_COMBINED_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4802;"	d
+INT_FBUSDMAC_INT_COMBINED_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4801;"	d
+INT_FBUSDMAC_INT_COMBINED_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4803;"	d
+INT_FBUSDMAC_INT_COMBINED_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4805;"	d
+INT_FLASH_DMA_DONE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4799;"	d
+INT_FLASH_DMA_DONE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4797;"	d
+INT_FLASH_DMA_DONE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4796;"	d
+INT_FLASH_DMA_DONE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4798;"	d
+INT_FLASH_DMA_DONE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4800;"	d
+INT_GPI_MODE_00_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4574;"	d
+INT_GPI_MODE_00_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4572;"	d
+INT_GPI_MODE_00_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4571;"	d
+INT_GPI_MODE_00_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4573;"	d
+INT_GPI_MODE_00_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4575;"	d
+INT_GPI_MODE_01_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4579;"	d
+INT_GPI_MODE_01_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4577;"	d
+INT_GPI_MODE_01_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4576;"	d
+INT_GPI_MODE_01_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4578;"	d
+INT_GPI_MODE_01_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4580;"	d
+INT_GPI_MODE_02_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4584;"	d
+INT_GPI_MODE_02_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4582;"	d
+INT_GPI_MODE_02_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4581;"	d
+INT_GPI_MODE_02_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4583;"	d
+INT_GPI_MODE_02_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4585;"	d
+INT_GPI_MODE_03_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4589;"	d
+INT_GPI_MODE_03_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4587;"	d
+INT_GPI_MODE_03_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4586;"	d
+INT_GPI_MODE_03_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4588;"	d
+INT_GPI_MODE_03_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4590;"	d
+INT_GPI_MODE_04_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4594;"	d
+INT_GPI_MODE_04_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4592;"	d
+INT_GPI_MODE_04_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4591;"	d
+INT_GPI_MODE_04_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4593;"	d
+INT_GPI_MODE_04_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4595;"	d
+INT_GPI_MODE_05_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4599;"	d
+INT_GPI_MODE_05_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4597;"	d
+INT_GPI_MODE_05_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4596;"	d
+INT_GPI_MODE_05_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4598;"	d
+INT_GPI_MODE_05_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4600;"	d
+INT_GPI_MODE_06_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4604;"	d
+INT_GPI_MODE_06_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4602;"	d
+INT_GPI_MODE_06_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4601;"	d
+INT_GPI_MODE_06_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4603;"	d
+INT_GPI_MODE_06_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4605;"	d
+INT_GPI_MODE_07_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4609;"	d
+INT_GPI_MODE_07_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4607;"	d
+INT_GPI_MODE_07_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4606;"	d
+INT_GPI_MODE_07_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4608;"	d
+INT_GPI_MODE_07_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4610;"	d
+INT_GPI_MODE_08_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4614;"	d
+INT_GPI_MODE_08_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4612;"	d
+INT_GPI_MODE_08_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4611;"	d
+INT_GPI_MODE_08_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4613;"	d
+INT_GPI_MODE_08_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4615;"	d
+INT_GPI_MODE_09_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4619;"	d
+INT_GPI_MODE_09_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4617;"	d
+INT_GPI_MODE_09_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4616;"	d
+INT_GPI_MODE_09_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4618;"	d
+INT_GPI_MODE_09_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4620;"	d
+INT_GPI_MODE_10_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4624;"	d
+INT_GPI_MODE_10_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4622;"	d
+INT_GPI_MODE_10_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4621;"	d
+INT_GPI_MODE_10_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4623;"	d
+INT_GPI_MODE_10_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4625;"	d
+INT_GPI_MODE_11_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4629;"	d
+INT_GPI_MODE_11_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4627;"	d
+INT_GPI_MODE_11_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4626;"	d
+INT_GPI_MODE_11_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4628;"	d
+INT_GPI_MODE_11_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4630;"	d
+INT_GPI_MODE_12_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4634;"	d
+INT_GPI_MODE_12_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4632;"	d
+INT_GPI_MODE_12_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4631;"	d
+INT_GPI_MODE_12_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4633;"	d
+INT_GPI_MODE_12_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4635;"	d
+INT_GPI_MODE_13_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4639;"	d
+INT_GPI_MODE_13_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4637;"	d
+INT_GPI_MODE_13_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4636;"	d
+INT_GPI_MODE_13_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4638;"	d
+INT_GPI_MODE_13_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4640;"	d
+INT_GPI_MODE_14_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4644;"	d
+INT_GPI_MODE_14_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4642;"	d
+INT_GPI_MODE_14_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4641;"	d
+INT_GPI_MODE_14_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4643;"	d
+INT_GPI_MODE_14_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4645;"	d
+INT_GPI_MODE_15_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4649;"	d
+INT_GPI_MODE_15_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4647;"	d
+INT_GPI_MODE_15_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4646;"	d
+INT_GPI_MODE_15_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4648;"	d
+INT_GPI_MODE_15_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4650;"	d
+INT_GPI_MODE_16_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4654;"	d
+INT_GPI_MODE_16_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4652;"	d
+INT_GPI_MODE_16_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4651;"	d
+INT_GPI_MODE_16_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4653;"	d
+INT_GPI_MODE_16_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4655;"	d
+INT_GPI_MODE_17_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4659;"	d
+INT_GPI_MODE_17_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4657;"	d
+INT_GPI_MODE_17_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4656;"	d
+INT_GPI_MODE_17_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4658;"	d
+INT_GPI_MODE_17_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4660;"	d
+INT_GPI_MODE_18_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4664;"	d
+INT_GPI_MODE_18_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4662;"	d
+INT_GPI_MODE_18_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4661;"	d
+INT_GPI_MODE_18_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4663;"	d
+INT_GPI_MODE_18_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4665;"	d
+INT_GPI_MODE_19_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4669;"	d
+INT_GPI_MODE_19_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4667;"	d
+INT_GPI_MODE_19_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4666;"	d
+INT_GPI_MODE_19_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4668;"	d
+INT_GPI_MODE_19_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4670;"	d
+INT_GPI_MODE_20_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4674;"	d
+INT_GPI_MODE_20_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4672;"	d
+INT_GPI_MODE_20_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4671;"	d
+INT_GPI_MODE_20_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4673;"	d
+INT_GPI_MODE_20_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4675;"	d
+INT_GPI_MODE_21_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4679;"	d
+INT_GPI_MODE_21_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4677;"	d
+INT_GPI_MODE_21_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4676;"	d
+INT_GPI_MODE_21_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4678;"	d
+INT_GPI_MODE_21_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4680;"	d
+INT_GPI_MODE_22_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4684;"	d
+INT_GPI_MODE_22_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4682;"	d
+INT_GPI_MODE_22_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4681;"	d
+INT_GPI_MODE_22_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4683;"	d
+INT_GPI_MODE_22_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4685;"	d
+INT_GPI_SUB_00_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4459;"	d
+INT_GPI_SUB_00_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4457;"	d
+INT_GPI_SUB_00_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4456;"	d
+INT_GPI_SUB_00_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4458;"	d
+INT_GPI_SUB_00_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4460;"	d
+INT_GPI_SUB_01_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4464;"	d
+INT_GPI_SUB_01_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4462;"	d
+INT_GPI_SUB_01_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4461;"	d
+INT_GPI_SUB_01_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4463;"	d
+INT_GPI_SUB_01_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4465;"	d
+INT_GPI_SUB_02_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4469;"	d
+INT_GPI_SUB_02_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4467;"	d
+INT_GPI_SUB_02_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4466;"	d
+INT_GPI_SUB_02_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4468;"	d
+INT_GPI_SUB_02_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4470;"	d
+INT_GPI_SUB_03_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4474;"	d
+INT_GPI_SUB_03_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4472;"	d
+INT_GPI_SUB_03_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4471;"	d
+INT_GPI_SUB_03_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4473;"	d
+INT_GPI_SUB_03_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4475;"	d
+INT_GPI_SUB_04_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4479;"	d
+INT_GPI_SUB_04_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4477;"	d
+INT_GPI_SUB_04_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4476;"	d
+INT_GPI_SUB_04_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4478;"	d
+INT_GPI_SUB_04_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4480;"	d
+INT_GPI_SUB_05_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4484;"	d
+INT_GPI_SUB_05_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4482;"	d
+INT_GPI_SUB_05_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4481;"	d
+INT_GPI_SUB_05_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4483;"	d
+INT_GPI_SUB_05_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4485;"	d
+INT_GPI_SUB_06_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4489;"	d
+INT_GPI_SUB_06_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4487;"	d
+INT_GPI_SUB_06_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4486;"	d
+INT_GPI_SUB_06_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4488;"	d
+INT_GPI_SUB_06_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4490;"	d
+INT_GPI_SUB_07_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4494;"	d
+INT_GPI_SUB_07_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4492;"	d
+INT_GPI_SUB_07_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4491;"	d
+INT_GPI_SUB_07_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4493;"	d
+INT_GPI_SUB_07_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4495;"	d
+INT_GPI_SUB_08_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4499;"	d
+INT_GPI_SUB_08_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4497;"	d
+INT_GPI_SUB_08_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4496;"	d
+INT_GPI_SUB_08_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4498;"	d
+INT_GPI_SUB_08_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4500;"	d
+INT_GPI_SUB_09_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4504;"	d
+INT_GPI_SUB_09_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4502;"	d
+INT_GPI_SUB_09_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4501;"	d
+INT_GPI_SUB_09_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4503;"	d
+INT_GPI_SUB_09_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4505;"	d
+INT_GPI_SUB_10_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4509;"	d
+INT_GPI_SUB_10_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4507;"	d
+INT_GPI_SUB_10_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4506;"	d
+INT_GPI_SUB_10_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4508;"	d
+INT_GPI_SUB_10_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4510;"	d
+INT_GPI_SUB_11_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4514;"	d
+INT_GPI_SUB_11_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4512;"	d
+INT_GPI_SUB_11_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4511;"	d
+INT_GPI_SUB_11_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4513;"	d
+INT_GPI_SUB_11_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4515;"	d
+INT_GPI_SUB_12_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4519;"	d
+INT_GPI_SUB_12_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4517;"	d
+INT_GPI_SUB_12_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4516;"	d
+INT_GPI_SUB_12_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4518;"	d
+INT_GPI_SUB_12_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4520;"	d
+INT_GPI_SUB_13_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4524;"	d
+INT_GPI_SUB_13_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4522;"	d
+INT_GPI_SUB_13_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4521;"	d
+INT_GPI_SUB_13_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4523;"	d
+INT_GPI_SUB_13_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4525;"	d
+INT_GPI_SUB_14_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4529;"	d
+INT_GPI_SUB_14_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4527;"	d
+INT_GPI_SUB_14_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4526;"	d
+INT_GPI_SUB_14_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4528;"	d
+INT_GPI_SUB_14_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4530;"	d
+INT_GPI_SUB_15_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4534;"	d
+INT_GPI_SUB_15_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4532;"	d
+INT_GPI_SUB_15_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4531;"	d
+INT_GPI_SUB_15_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4533;"	d
+INT_GPI_SUB_15_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4535;"	d
+INT_GPI_SUB_16_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4539;"	d
+INT_GPI_SUB_16_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4537;"	d
+INT_GPI_SUB_16_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4536;"	d
+INT_GPI_SUB_16_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4538;"	d
+INT_GPI_SUB_16_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4540;"	d
+INT_GPI_SUB_17_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4544;"	d
+INT_GPI_SUB_17_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4542;"	d
+INT_GPI_SUB_17_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4541;"	d
+INT_GPI_SUB_17_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4543;"	d
+INT_GPI_SUB_17_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4545;"	d
+INT_GPI_SUB_18_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4549;"	d
+INT_GPI_SUB_18_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4547;"	d
+INT_GPI_SUB_18_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4546;"	d
+INT_GPI_SUB_18_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4548;"	d
+INT_GPI_SUB_18_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4550;"	d
+INT_GPI_SUB_19_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4554;"	d
+INT_GPI_SUB_19_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4552;"	d
+INT_GPI_SUB_19_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4551;"	d
+INT_GPI_SUB_19_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4553;"	d
+INT_GPI_SUB_19_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4555;"	d
+INT_GPI_SUB_20_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4559;"	d
+INT_GPI_SUB_20_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4557;"	d
+INT_GPI_SUB_20_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4556;"	d
+INT_GPI_SUB_20_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4558;"	d
+INT_GPI_SUB_20_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4560;"	d
+INT_GPI_SUB_21_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4564;"	d
+INT_GPI_SUB_21_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4562;"	d
+INT_GPI_SUB_21_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4561;"	d
+INT_GPI_SUB_21_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4563;"	d
+INT_GPI_SUB_21_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4565;"	d
+INT_GPI_SUB_22_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4569;"	d
+INT_GPI_SUB_22_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4567;"	d
+INT_GPI_SUB_22_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4566;"	d
+INT_GPI_SUB_22_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4568;"	d
+INT_GPI_SUB_22_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4570;"	d
+INT_HCI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4874;"	d
+INT_HCI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4872;"	d
+INT_HCI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4871;"	d
+INT_HCI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4873;"	d
+INT_HCI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4875;"	d
+INT_I2CMST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4869;"	d
+INT_I2CMST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4867;"	d
+INT_I2CMST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4866;"	d
+INT_I2CMST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4868;"	d
+INT_I2CMST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4870;"	d
+INT_I2S_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4814;"	d
+INT_I2S_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4812;"	d
+INT_I2S_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4811;"	d
+INT_I2S_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4813;"	d
+INT_I2S_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4815;"	d
+INT_IDCODE_HI	include/ssv6200_aux.h	4484;"	d
+INT_IDCODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3594;"	d
+INT_IDCODE_I_MSK	include/ssv6200_aux.h	4482;"	d
+INT_IDCODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3592;"	d
+INT_IDCODE_MSK	include/ssv6200_aux.h	4481;"	d
+INT_IDCODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3591;"	d
+INT_IDCODE_SFT	include/ssv6200_aux.h	4483;"	d
+INT_IDCODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3593;"	d
+INT_IDCODE_SZ	include/ssv6200_aux.h	4485;"	d
+INT_IDCODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3595;"	d
+INT_ID_DOUBLE_RLS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4739;"	d
+INT_ID_DOUBLE_RLS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4737;"	d
+INT_ID_DOUBLE_RLS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4736;"	d
+INT_ID_DOUBLE_RLS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4738;"	d
+INT_ID_DOUBLE_RLS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4740;"	d
+INT_ID_THOLD_RX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4729;"	d
+INT_ID_THOLD_RX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4727;"	d
+INT_ID_THOLD_RX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4726;"	d
+INT_ID_THOLD_RX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4728;"	d
+INT_ID_THOLD_RX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4730;"	d
+INT_ID_THOLD_TX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4734;"	d
+INT_ID_THOLD_TX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4732;"	d
+INT_ID_THOLD_TX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4731;"	d
+INT_ID_THOLD_TX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4733;"	d
+INT_ID_THOLD_TX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4735;"	d
+INT_IPC_RAW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4694;"	d
+INT_IPC_RAW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4692;"	d
+INT_IPC_RAW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4691;"	d
+INT_IPC_RAW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4693;"	d
+INT_IPC_RAW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4695;"	d
+INT_MB_LOWTHOLD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4764;"	d
+INT_MB_LOWTHOLD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4762;"	d
+INT_MB_LOWTHOLD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4761;"	d
+INT_MB_LOWTHOLD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4763;"	d
+INT_MB_LOWTHOLD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4765;"	d
+INT_MODE_HI	include/ssv6200_aux.h	4734;"	d
+INT_MODE_I_MSK	include/ssv6200_aux.h	4732;"	d
+INT_MODE_MSK	include/ssv6200_aux.h	4731;"	d
+INT_MODE_SFT	include/ssv6200_aux.h	4733;"	d
+INT_MODE_SZ	include/ssv6200_aux.h	4735;"	d
+INT_MS_TIMER_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4849;"	d
+INT_MS_TIMER_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4847;"	d
+INT_MS_TIMER_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4846;"	d
+INT_MS_TIMER_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4848;"	d
+INT_MS_TIMER_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4850;"	d
+INT_MS_TIMER_1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4854;"	d
+INT_MS_TIMER_1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4852;"	d
+INT_MS_TIMER_1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4851;"	d
+INT_MS_TIMER_1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4853;"	d
+INT_MS_TIMER_1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4855;"	d
+INT_MS_TIMER_2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4859;"	d
+INT_MS_TIMER_2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4857;"	d
+INT_MS_TIMER_2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4856;"	d
+INT_MS_TIMER_2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4858;"	d
+INT_MS_TIMER_2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4860;"	d
+INT_MS_TIMER_3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4864;"	d
+INT_MS_TIMER_3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4862;"	d
+INT_MS_TIMER_3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4861;"	d
+INT_MS_TIMER_3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4863;"	d
+INT_MS_TIMER_3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4865;"	d
+INT_PERI_MASK_HI	include/ssv6200_aux.h	4909;"	d
+INT_PERI_MASK_I_MSK	include/ssv6200_aux.h	4907;"	d
+INT_PERI_MASK_MSK	include/ssv6200_aux.h	4906;"	d
+INT_PERI_MASK_SD_HI	include/ssv6200_aux.h	5254;"	d
+INT_PERI_MASK_SD_I_MSK	include/ssv6200_aux.h	5252;"	d
+INT_PERI_MASK_SD_MSK	include/ssv6200_aux.h	5251;"	d
+INT_PERI_MASK_SD_SFT	include/ssv6200_aux.h	5253;"	d
+INT_PERI_MASK_SD_SZ	include/ssv6200_aux.h	5255;"	d
+INT_PERI_MASK_SFT	include/ssv6200_aux.h	4908;"	d
+INT_PERI_MASK_SZ	include/ssv6200_aux.h	4910;"	d
+INT_REG_BANK_SIZE	include/ssv6200_reg.h	83;"	d
+INT_REG_BASE	include/ssv6200_reg.h	34;"	d
+INT_REQ_LOCK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4719;"	d
+INT_REQ_LOCK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4717;"	d
+INT_REQ_LOCK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4716;"	d
+INT_REQ_LOCK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4718;"	d
+INT_REQ_LOCK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4720;"	d
+INT_RX_ID_LEN_THOLD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4744;"	d
+INT_RX_ID_LEN_THOLD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4742;"	d
+INT_RX_ID_LEN_THOLD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4741;"	d
+INT_RX_ID_LEN_THOLD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4743;"	d
+INT_RX_ID_LEN_THOLD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4745;"	d
+INT_SDIO_WAKE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4789;"	d
+INT_SDIO_WAKE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4787;"	d
+INT_SDIO_WAKE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4786;"	d
+INT_SDIO_WAKE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4788;"	d
+INT_SDIO_WAKE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4790;"	d
+INT_SPI_M_DONE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4794;"	d
+INT_SPI_M_DONE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4792;"	d
+INT_SPI_M_DONE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4791;"	d
+INT_SPI_M_DONE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4793;"	d
+INT_SPI_M_DONE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4795;"	d
+INT_THROUGH_PIN_HI	include/ssv6200_aux.h	3359;"	d
+INT_THROUGH_PIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2669;"	d
+INT_THROUGH_PIN_I_MSK	include/ssv6200_aux.h	3357;"	d
+INT_THROUGH_PIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2667;"	d
+INT_THROUGH_PIN_MSK	include/ssv6200_aux.h	3356;"	d
+INT_THROUGH_PIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2666;"	d
+INT_THROUGH_PIN_SFT	include/ssv6200_aux.h	3358;"	d
+INT_THROUGH_PIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2668;"	d
+INT_THROUGH_PIN_SZ	include/ssv6200_aux.h	3360;"	d
+INT_THROUGH_PIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2670;"	d
+INT_TRASH_CAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4759;"	d
+INT_TRASH_CAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4757;"	d
+INT_TRASH_CAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4756;"	d
+INT_TRASH_CAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4758;"	d
+INT_TRASH_CAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4760;"	d
+INT_TX_ID_LEN_THOLD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4749;"	d
+INT_TX_ID_LEN_THOLD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4747;"	d
+INT_TX_ID_LEN_THOLD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4746;"	d
+INT_TX_ID_LEN_THOLD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4748;"	d
+INT_TX_ID_LEN_THOLD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4750;"	d
+INT_TX_LIMIT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4724;"	d
+INT_TX_LIMIT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4722;"	d
+INT_TX_LIMIT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4721;"	d
+INT_TX_LIMIT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4723;"	d
+INT_TX_LIMIT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4725;"	d
+INT_UART_DATA_RX_TOUT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4709;"	d
+INT_UART_DATA_RX_TOUT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4707;"	d
+INT_UART_DATA_RX_TOUT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4706;"	d
+INT_UART_DATA_RX_TOUT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4708;"	d
+INT_UART_DATA_RX_TOUT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4710;"	d
+INT_UART_DBG_RX_TOUT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4704;"	d
+INT_UART_DBG_RX_TOUT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4702;"	d
+INT_UART_DBG_RX_TOUT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4701;"	d
+INT_UART_DBG_RX_TOUT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4703;"	d
+INT_UART_DBG_RX_TOUT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4705;"	d
+INT_US_TIMER_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4829;"	d
+INT_US_TIMER_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4827;"	d
+INT_US_TIMER_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4826;"	d
+INT_US_TIMER_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4828;"	d
+INT_US_TIMER_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4830;"	d
+INT_US_TIMER_1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4834;"	d
+INT_US_TIMER_1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4832;"	d
+INT_US_TIMER_1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4831;"	d
+INT_US_TIMER_1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4833;"	d
+INT_US_TIMER_1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4835;"	d
+INT_US_TIMER_2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4839;"	d
+INT_US_TIMER_2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4837;"	d
+INT_US_TIMER_2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4836;"	d
+INT_US_TIMER_2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4838;"	d
+INT_US_TIMER_2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4840;"	d
+INT_US_TIMER_3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4844;"	d
+INT_US_TIMER_3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4842;"	d
+INT_US_TIMER_3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4841;"	d
+INT_US_TIMER_3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4843;"	d
+INT_US_TIMER_3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4845;"	d
+INT_WIFI_PHY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4699;"	d
+INT_WIFI_PHY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4697;"	d
+INT_WIFI_PHY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4696;"	d
+INT_WIFI_PHY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4698;"	d
+INT_WIFI_PHY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4700;"	d
+INVALID	smac/kssvsmart.c	31;"	d	file:
+INV_DATA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5994;"	d
+INV_DATA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5992;"	d
+INV_DATA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5991;"	d
+INV_DATA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5993;"	d
+INV_DATA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5995;"	d
+IN_FIFO_FLUSH_ID_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33939;"	d
+IN_FIFO_FLUSH_ID_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33937;"	d
+IN_FIFO_FLUSH_ID_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33936;"	d
+IN_FIFO_FLUSH_ID_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33938;"	d
+IN_FIFO_FLUSH_ID_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33940;"	d
+IN_FIFO_FLUSH_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33944;"	d
+IN_FIFO_FLUSH_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33942;"	d
+IN_FIFO_FLUSH_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33941;"	d
+IN_FIFO_FLUSH_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33943;"	d
+IN_FIFO_FLUSH_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33945;"	d
+IN_FIFO_FLUSH_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33949;"	d
+IN_FIFO_FLUSH_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33947;"	d
+IN_FIFO_FLUSH_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33946;"	d
+IN_FIFO_FLUSH_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33948;"	d
+IN_FIFO_FLUSH_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33950;"	d
+IOCTL_SSVSDIO_GET_BLOCKLEN	bridge/sdiobridge_pub.h	65;"	d
+IOCTL_SSVSDIO_GET_BUS_CLOCK	bridge/sdiobridge_pub.h	55;"	d
+IOCTL_SSVSDIO_GET_BUS_WIDTH	bridge/sdiobridge_pub.h	51;"	d
+IOCTL_SSVSDIO_GET_FUNCTION_FOCUS	bridge/sdiobridge_pub.h	47;"	d
+IOCTL_SSVSDIO_GET_MULTI_BYTE_IO_PORT	bridge/sdiobridge_pub.h	93;"	d
+IOCTL_SSVSDIO_GET_MULTI_BYTE_REG_IO_PORT	bridge/sdiobridge_pub.h	101;"	d
+IOCTL_SSVSDIO_READ_BYTE	bridge/sdiobridge_pub.h	89;"	d
+IOCTL_SSVSDIO_READ_DATA	bridge/sdiobridge_pub.h	109;"	d
+IOCTL_SSVSDIO_READ_DATA	hci_wrapper/ssv_huw.h	99;"	d
+IOCTL_SSVSDIO_READ_MULTI_BYTE	bridge/sdiobridge_pub.h	97;"	d
+IOCTL_SSVSDIO_READ_REG	bridge/sdiobridge_pub.h	105;"	d
+IOCTL_SSVSDIO_READ_REG	hci_wrapper/ssv_huw.h	95;"	d
+IOCTL_SSVSDIO_SET_BLOCKLEN	bridge/sdiobridge_pub.h	67;"	d
+IOCTL_SSVSDIO_SET_BUS_CLOCK	bridge/sdiobridge_pub.h	57;"	d
+IOCTL_SSVSDIO_SET_BUS_WIDTH	bridge/sdiobridge_pub.h	53;"	d
+IOCTL_SSVSDIO_SET_FUNCTION_FOCUS	bridge/sdiobridge_pub.h	49;"	d
+IOCTL_SSVSDIO_SET_MULTI_BYTE_IO_PORT	bridge/sdiobridge_pub.h	95;"	d
+IOCTL_SSVSDIO_SET_MULTI_BYTE_REG_IO_PORT	bridge/sdiobridge_pub.h	103;"	d
+IOCTL_SSVSDIO_START	hci_wrapper/ssv_huw.h	103;"	d
+IOCTL_SSVSDIO_STOP	hci_wrapper/ssv_huw.h	105;"	d
+IOCTL_SSVSDIO_WRITE_BYTE	bridge/sdiobridge_pub.h	91;"	d
+IOCTL_SSVSDIO_WRITE_MULTI_BYTE	bridge/sdiobridge_pub.h	99;"	d
+IOCTL_SSVSDIO_WRITE_REG	bridge/sdiobridge_pub.h	107;"	d
+IOCTL_SSVSDIO_WRITE_REG	hci_wrapper/ssv_huw.h	97;"	d
+IOCTL_SSVSDIO_WRITE_SRAM	hci_wrapper/ssv_huw.h	101;"	d
+IO_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2329;"	d
+IO_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2327;"	d
+IO_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2326;"	d
+IO_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2328;"	d
+IO_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2330;"	d
+IO_PDE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2324;"	d
+IO_PDE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2322;"	d
+IO_PDE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2321;"	d
+IO_PDE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2323;"	d
+IO_PDE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2325;"	d
+IO_PIE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2309;"	d
+IO_PIE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2307;"	d
+IO_PIE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2306;"	d
+IO_PIE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2308;"	d
+IO_PIE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2310;"	d
+IO_PI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2304;"	d
+IO_PI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2302;"	d
+IO_PI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2301;"	d
+IO_PI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2303;"	d
+IO_PI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2305;"	d
+IO_POEN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2314;"	d
+IO_POEN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2312;"	d
+IO_POEN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2311;"	d
+IO_POEN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2313;"	d
+IO_POEN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2315;"	d
+IO_PORT_REG_HI	include/ssv6200_aux.h	3034;"	d
+IO_PORT_REG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2504;"	d
+IO_PORT_REG_I_MSK	include/ssv6200_aux.h	3032;"	d
+IO_PORT_REG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2502;"	d
+IO_PORT_REG_MSK	include/ssv6200_aux.h	3031;"	d
+IO_PORT_REG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2501;"	d
+IO_PORT_REG_SFT	include/ssv6200_aux.h	3033;"	d
+IO_PORT_REG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2503;"	d
+IO_PORT_REG_SZ	include/ssv6200_aux.h	3035;"	d
+IO_PORT_REG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2505;"	d
+IO_PO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2299;"	d
+IO_PO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2297;"	d
+IO_PO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2296;"	d
+IO_PO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2298;"	d
+IO_PO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2300;"	d
+IO_PUE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2319;"	d
+IO_PUE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2317;"	d
+IO_PUE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2316;"	d
+IO_PUE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2318;"	d
+IO_PUE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2320;"	d
+IO_REG_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	95;"	d
+IO_REG_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	34;"	d
+IO_REG_BURST_RD_PORT_REG	hwif/sdio/sdio_def.h	100;"	d
+IO_REG_BURST_WR_PORT_REG	hwif/sdio/sdio_def.h	101;"	d
+IO_REG_PORT_REG_HI	include/ssv6200_aux.h	3419;"	d
+IO_REG_PORT_REG_I_MSK	include/ssv6200_aux.h	3417;"	d
+IO_REG_PORT_REG_MSK	include/ssv6200_aux.h	3416;"	d
+IO_REG_PORT_REG_SFT	include/ssv6200_aux.h	3418;"	d
+IO_REG_PORT_REG_SZ	include/ssv6200_aux.h	3420;"	d
+IQCAL_RF_PGAG_HI	include/ssv6200_aux.h	15384;"	d
+IQCAL_RF_PGAG_I_MSK	include/ssv6200_aux.h	15382;"	d
+IQCAL_RF_PGAG_MSK	include/ssv6200_aux.h	15381;"	d
+IQCAL_RF_PGAG_SFT	include/ssv6200_aux.h	15383;"	d
+IQCAL_RF_PGAG_SZ	include/ssv6200_aux.h	15385;"	d
+IQCAL_RF_RFG_HI	include/ssv6200_aux.h	15389;"	d
+IQCAL_RF_RFG_I_MSK	include/ssv6200_aux.h	15387;"	d
+IQCAL_RF_RFG_MSK	include/ssv6200_aux.h	15386;"	d
+IQCAL_RF_RFG_SFT	include/ssv6200_aux.h	15388;"	d
+IQCAL_RF_RFG_SZ	include/ssv6200_aux.h	15390;"	d
+IQCAL_RF_RX_AGC_HI	include/ssv6200_aux.h	15379;"	d
+IQCAL_RF_RX_AGC_I_MSK	include/ssv6200_aux.h	15377;"	d
+IQCAL_RF_RX_AGC_MSK	include/ssv6200_aux.h	15376;"	d
+IQCAL_RF_RX_AGC_SFT	include/ssv6200_aux.h	15378;"	d
+IQCAL_RF_RX_AGC_SZ	include/ssv6200_aux.h	15380;"	d
+IQCAL_RF_TX_DAC_EN_HI	include/ssv6200_aux.h	15374;"	d
+IQCAL_RF_TX_DAC_EN_I_MSK	include/ssv6200_aux.h	15372;"	d
+IQCAL_RF_TX_DAC_EN_MSK	include/ssv6200_aux.h	15371;"	d
+IQCAL_RF_TX_DAC_EN_SFT	include/ssv6200_aux.h	15373;"	d
+IQCAL_RF_TX_DAC_EN_SZ	include/ssv6200_aux.h	15375;"	d
+IQCAL_RF_TX_EN_HI	include/ssv6200_aux.h	15364;"	d
+IQCAL_RF_TX_EN_I_MSK	include/ssv6200_aux.h	15362;"	d
+IQCAL_RF_TX_EN_MSK	include/ssv6200_aux.h	15361;"	d
+IQCAL_RF_TX_EN_SFT	include/ssv6200_aux.h	15363;"	d
+IQCAL_RF_TX_EN_SZ	include/ssv6200_aux.h	15365;"	d
+IQCAL_RF_TX_PA_EN_HI	include/ssv6200_aux.h	15369;"	d
+IQCAL_RF_TX_PA_EN_I_MSK	include/ssv6200_aux.h	15367;"	d
+IQCAL_RF_TX_PA_EN_MSK	include/ssv6200_aux.h	15366;"	d
+IQCAL_RF_TX_PA_EN_SFT	include/ssv6200_aux.h	15368;"	d
+IQCAL_RF_TX_PA_EN_SZ	include/ssv6200_aux.h	15370;"	d
+IQK_CFG_LEN	include/ssv6xxx_common.h	240;"	d
+IQ_CALI_FAILED	smac/dev.h	/^    IQ_CALI_FAILED$/;"	e	enum:__anon14
+IQ_CALI_OK	smac/dev.h	/^    IQ_CALI_OK,$/;"	e	enum:__anon14
+IQ_CALI_RUNNING	smac/dev.h	/^    IQ_CALI_RUNNING,$/;"	e	enum:__anon14
+IQ_LOG_EN_HI	include/ssv6200_aux.h	12434;"	d
+IQ_LOG_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33964;"	d
+IQ_LOG_EN_I_MSK	include/ssv6200_aux.h	12432;"	d
+IQ_LOG_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33962;"	d
+IQ_LOG_EN_MSK	include/ssv6200_aux.h	12431;"	d
+IQ_LOG_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33961;"	d
+IQ_LOG_EN_SFT	include/ssv6200_aux.h	12433;"	d
+IQ_LOG_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33963;"	d
+IQ_LOG_EN_SZ	include/ssv6200_aux.h	12435;"	d
+IQ_LOG_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33965;"	d
+IQ_LOG_LEN_HI	include/ssv6200_aux.h	12459;"	d
+IQ_LOG_LEN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33979;"	d
+IQ_LOG_LEN_I_MSK	include/ssv6200_aux.h	12457;"	d
+IQ_LOG_LEN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33977;"	d
+IQ_LOG_LEN_MSK	include/ssv6200_aux.h	12456;"	d
+IQ_LOG_LEN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33976;"	d
+IQ_LOG_LEN_SFT	include/ssv6200_aux.h	12458;"	d
+IQ_LOG_LEN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33978;"	d
+IQ_LOG_LEN_SZ	include/ssv6200_aux.h	12460;"	d
+IQ_LOG_LEN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33980;"	d
+IQ_LOG_STOP_MODE_HI	include/ssv6200_aux.h	12439;"	d
+IQ_LOG_STOP_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33969;"	d
+IQ_LOG_STOP_MODE_I_MSK	include/ssv6200_aux.h	12437;"	d
+IQ_LOG_STOP_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33967;"	d
+IQ_LOG_STOP_MODE_MSK	include/ssv6200_aux.h	12436;"	d
+IQ_LOG_STOP_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33966;"	d
+IQ_LOG_STOP_MODE_SFT	include/ssv6200_aux.h	12438;"	d
+IQ_LOG_STOP_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33968;"	d
+IQ_LOG_STOP_MODE_SZ	include/ssv6200_aux.h	12440;"	d
+IQ_LOG_STOP_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33970;"	d
+IQ_LOG_ST_ADR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33984;"	d
+IQ_LOG_ST_ADR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33982;"	d
+IQ_LOG_ST_ADR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33981;"	d
+IQ_LOG_ST_ADR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33983;"	d
+IQ_LOG_ST_ADR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33985;"	d
+IQ_LOG_TAIL_ADR_HI	include/ssv6200_aux.h	12464;"	d
+IQ_LOG_TAIL_ADR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33989;"	d
+IQ_LOG_TAIL_ADR_I_MSK	include/ssv6200_aux.h	12462;"	d
+IQ_LOG_TAIL_ADR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33987;"	d
+IQ_LOG_TAIL_ADR_MSK	include/ssv6200_aux.h	12461;"	d
+IQ_LOG_TAIL_ADR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33986;"	d
+IQ_LOG_TAIL_ADR_SFT	include/ssv6200_aux.h	12463;"	d
+IQ_LOG_TAIL_ADR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33988;"	d
+IQ_LOG_TAIL_ADR_SZ	include/ssv6200_aux.h	12465;"	d
+IQ_LOG_TAIL_ADR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33990;"	d
+IQ_LOG_TIMER_HI	include/ssv6200_aux.h	12454;"	d
+IQ_LOG_TIMER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33974;"	d
+IQ_LOG_TIMER_I_MSK	include/ssv6200_aux.h	12452;"	d
+IQ_LOG_TIMER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33972;"	d
+IQ_LOG_TIMER_MSK	include/ssv6200_aux.h	12451;"	d
+IQ_LOG_TIMER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33971;"	d
+IQ_LOG_TIMER_SFT	include/ssv6200_aux.h	12453;"	d
+IQ_LOG_TIMER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33973;"	d
+IQ_LOG_TIMER_SZ	include/ssv6200_aux.h	12455;"	d
+IQ_LOG_TIMER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33975;"	d
+IQ_SRAM_SEL_0_HI	include/ssv6200_aux.h	349;"	d
+IQ_SRAM_SEL_0_I_MSK	include/ssv6200_aux.h	347;"	d
+IQ_SRAM_SEL_0_MSK	include/ssv6200_aux.h	346;"	d
+IQ_SRAM_SEL_0_SFT	include/ssv6200_aux.h	348;"	d
+IQ_SRAM_SEL_0_SZ	include/ssv6200_aux.h	350;"	d
+IQ_SRAM_SEL_1_HI	include/ssv6200_aux.h	354;"	d
+IQ_SRAM_SEL_1_I_MSK	include/ssv6200_aux.h	352;"	d
+IQ_SRAM_SEL_1_MSK	include/ssv6200_aux.h	351;"	d
+IQ_SRAM_SEL_1_SFT	include/ssv6200_aux.h	353;"	d
+IQ_SRAM_SEL_1_SZ	include/ssv6200_aux.h	355;"	d
+IQ_SRAM_SEL_2_HI	include/ssv6200_aux.h	359;"	d
+IQ_SRAM_SEL_2_I_MSK	include/ssv6200_aux.h	357;"	d
+IQ_SRAM_SEL_2_MSK	include/ssv6200_aux.h	356;"	d
+IQ_SRAM_SEL_2_SFT	include/ssv6200_aux.h	358;"	d
+IQ_SRAM_SEL_2_SZ	include/ssv6200_aux.h	360;"	d
+IRQ_BEACON_DONE_HI	include/ssv6200_aux.h	4754;"	d
+IRQ_BEACON_DONE_I_MSK	include/ssv6200_aux.h	4752;"	d
+IRQ_BEACON_DONE_MSK	include/ssv6200_aux.h	4751;"	d
+IRQ_BEACON_DONE_SD_HI	include/ssv6200_aux.h	5114;"	d
+IRQ_BEACON_DONE_SD_I_MSK	include/ssv6200_aux.h	5112;"	d
+IRQ_BEACON_DONE_SD_MSK	include/ssv6200_aux.h	5111;"	d
+IRQ_BEACON_DONE_SD_SFT	include/ssv6200_aux.h	5113;"	d
+IRQ_BEACON_DONE_SD_SZ	include/ssv6200_aux.h	5115;"	d
+IRQ_BEACON_DONE_SFT	include/ssv6200_aux.h	4753;"	d
+IRQ_BEACON_DONE_SZ	include/ssv6200_aux.h	4755;"	d
+IRQ_BEACON_DTIM_HI	include/ssv6200_aux.h	4794;"	d
+IRQ_BEACON_DTIM_I_MSK	include/ssv6200_aux.h	4792;"	d
+IRQ_BEACON_DTIM_MSK	include/ssv6200_aux.h	4791;"	d
+IRQ_BEACON_DTIM_SD_HI	include/ssv6200_aux.h	5154;"	d
+IRQ_BEACON_DTIM_SD_I_MSK	include/ssv6200_aux.h	5152;"	d
+IRQ_BEACON_DTIM_SD_MSK	include/ssv6200_aux.h	5151;"	d
+IRQ_BEACON_DTIM_SD_SFT	include/ssv6200_aux.h	5153;"	d
+IRQ_BEACON_DTIM_SD_SZ	include/ssv6200_aux.h	5155;"	d
+IRQ_BEACON_DTIM_SFT	include/ssv6200_aux.h	4793;"	d
+IRQ_BEACON_DTIM_SZ	include/ssv6200_aux.h	4795;"	d
+IRQ_BEACON_HI	include/ssv6200_aux.h	4759;"	d
+IRQ_BEACON_I_MSK	include/ssv6200_aux.h	4757;"	d
+IRQ_BEACON_MSK	include/ssv6200_aux.h	4756;"	d
+IRQ_BEACON_SD_HI	include/ssv6200_aux.h	5119;"	d
+IRQ_BEACON_SD_I_MSK	include/ssv6200_aux.h	5117;"	d
+IRQ_BEACON_SD_MSK	include/ssv6200_aux.h	5116;"	d
+IRQ_BEACON_SD_SFT	include/ssv6200_aux.h	5118;"	d
+IRQ_BEACON_SD_SZ	include/ssv6200_aux.h	5120;"	d
+IRQ_BEACON_SFT	include/ssv6200_aux.h	4758;"	d
+IRQ_BEACON_SZ	include/ssv6200_aux.h	4760;"	d
+IRQ_CO_DMA_HI	include/ssv6200_aux.h	4884;"	d
+IRQ_CO_DMA_I_MSK	include/ssv6200_aux.h	4882;"	d
+IRQ_CO_DMA_MSK	include/ssv6200_aux.h	4881;"	d
+IRQ_CO_DMA_SD_HI	include/ssv6200_aux.h	5244;"	d
+IRQ_CO_DMA_SD_I_MSK	include/ssv6200_aux.h	5242;"	d
+IRQ_CO_DMA_SD_MSK	include/ssv6200_aux.h	5241;"	d
+IRQ_CO_DMA_SD_SFT	include/ssv6200_aux.h	5243;"	d
+IRQ_CO_DMA_SD_SZ	include/ssv6200_aux.h	5245;"	d
+IRQ_CO_DMA_SFT	include/ssv6200_aux.h	4883;"	d
+IRQ_CO_DMA_SZ	include/ssv6200_aux.h	4885;"	d
+IRQ_DAT_UART_RX_HI	include/ssv6200_aux.h	5044;"	d
+IRQ_DAT_UART_RX_I_MSK	include/ssv6200_aux.h	5042;"	d
+IRQ_DAT_UART_RX_MSK	include/ssv6200_aux.h	5041;"	d
+IRQ_DAT_UART_RX_SD_HI	include/ssv6200_aux.h	5389;"	d
+IRQ_DAT_UART_RX_SD_I_MSK	include/ssv6200_aux.h	5387;"	d
+IRQ_DAT_UART_RX_SD_MSK	include/ssv6200_aux.h	5386;"	d
+IRQ_DAT_UART_RX_SD_SFT	include/ssv6200_aux.h	5388;"	d
+IRQ_DAT_UART_RX_SD_SZ	include/ssv6200_aux.h	5390;"	d
+IRQ_DAT_UART_RX_SFT	include/ssv6200_aux.h	5043;"	d
+IRQ_DAT_UART_RX_SZ	include/ssv6200_aux.h	5045;"	d
+IRQ_DAT_UART_TX_HI	include/ssv6200_aux.h	5039;"	d
+IRQ_DAT_UART_TX_I_MSK	include/ssv6200_aux.h	5037;"	d
+IRQ_DAT_UART_TX_MSK	include/ssv6200_aux.h	5036;"	d
+IRQ_DAT_UART_TX_SD_HI	include/ssv6200_aux.h	5384;"	d
+IRQ_DAT_UART_TX_SD_I_MSK	include/ssv6200_aux.h	5382;"	d
+IRQ_DAT_UART_TX_SD_MSK	include/ssv6200_aux.h	5381;"	d
+IRQ_DAT_UART_TX_SD_SFT	include/ssv6200_aux.h	5383;"	d
+IRQ_DAT_UART_TX_SD_SZ	include/ssv6200_aux.h	5385;"	d
+IRQ_DAT_UART_TX_SFT	include/ssv6200_aux.h	5038;"	d
+IRQ_DAT_UART_TX_SZ	include/ssv6200_aux.h	5040;"	d
+IRQ_DMA0_HI	include/ssv6200_aux.h	4879;"	d
+IRQ_DMA0_I_MSK	include/ssv6200_aux.h	4877;"	d
+IRQ_DMA0_MSK	include/ssv6200_aux.h	4876;"	d
+IRQ_DMA0_SD_HI	include/ssv6200_aux.h	5239;"	d
+IRQ_DMA0_SD_I_MSK	include/ssv6200_aux.h	5237;"	d
+IRQ_DMA0_SD_MSK	include/ssv6200_aux.h	5236;"	d
+IRQ_DMA0_SD_SFT	include/ssv6200_aux.h	5238;"	d
+IRQ_DMA0_SD_SZ	include/ssv6200_aux.h	5240;"	d
+IRQ_DMA0_SFT	include/ssv6200_aux.h	4878;"	d
+IRQ_DMA0_SZ	include/ssv6200_aux.h	4880;"	d
+IRQ_EDCA0_LOWTHOLD_INT_HI	include/ssv6200_aux.h	4799;"	d
+IRQ_EDCA0_LOWTHOLD_INT_I_MSK	include/ssv6200_aux.h	4797;"	d
+IRQ_EDCA0_LOWTHOLD_INT_MSK	include/ssv6200_aux.h	4796;"	d
+IRQ_EDCA0_LOWTHOLD_INT_SD_HI	include/ssv6200_aux.h	5159;"	d
+IRQ_EDCA0_LOWTHOLD_INT_SD_I_MSK	include/ssv6200_aux.h	5157;"	d
+IRQ_EDCA0_LOWTHOLD_INT_SD_MSK	include/ssv6200_aux.h	5156;"	d
+IRQ_EDCA0_LOWTHOLD_INT_SD_SFT	include/ssv6200_aux.h	5158;"	d
+IRQ_EDCA0_LOWTHOLD_INT_SD_SZ	include/ssv6200_aux.h	5160;"	d
+IRQ_EDCA0_LOWTHOLD_INT_SFT	include/ssv6200_aux.h	4798;"	d
+IRQ_EDCA0_LOWTHOLD_INT_SZ	include/ssv6200_aux.h	4800;"	d
+IRQ_EDCA0_TX_DONE_HI	include/ssv6200_aux.h	4769;"	d
+IRQ_EDCA0_TX_DONE_I_MSK	include/ssv6200_aux.h	4767;"	d
+IRQ_EDCA0_TX_DONE_MSK	include/ssv6200_aux.h	4766;"	d
+IRQ_EDCA0_TX_DONE_SD_HI	include/ssv6200_aux.h	5129;"	d
+IRQ_EDCA0_TX_DONE_SD_I_MSK	include/ssv6200_aux.h	5127;"	d
+IRQ_EDCA0_TX_DONE_SD_MSK	include/ssv6200_aux.h	5126;"	d
+IRQ_EDCA0_TX_DONE_SD_SFT	include/ssv6200_aux.h	5128;"	d
+IRQ_EDCA0_TX_DONE_SD_SZ	include/ssv6200_aux.h	5130;"	d
+IRQ_EDCA0_TX_DONE_SFT	include/ssv6200_aux.h	4768;"	d
+IRQ_EDCA0_TX_DONE_SZ	include/ssv6200_aux.h	4770;"	d
+IRQ_EDCA1_LOWTHOLD_INT_HI	include/ssv6200_aux.h	4804;"	d
+IRQ_EDCA1_LOWTHOLD_INT_I_MSK	include/ssv6200_aux.h	4802;"	d
+IRQ_EDCA1_LOWTHOLD_INT_MSK	include/ssv6200_aux.h	4801;"	d
+IRQ_EDCA1_LOWTHOLD_INT_SD_HI	include/ssv6200_aux.h	5164;"	d
+IRQ_EDCA1_LOWTHOLD_INT_SD_I_MSK	include/ssv6200_aux.h	5162;"	d
+IRQ_EDCA1_LOWTHOLD_INT_SD_MSK	include/ssv6200_aux.h	5161;"	d
+IRQ_EDCA1_LOWTHOLD_INT_SD_SFT	include/ssv6200_aux.h	5163;"	d
+IRQ_EDCA1_LOWTHOLD_INT_SD_SZ	include/ssv6200_aux.h	5165;"	d
+IRQ_EDCA1_LOWTHOLD_INT_SFT	include/ssv6200_aux.h	4803;"	d
+IRQ_EDCA1_LOWTHOLD_INT_SZ	include/ssv6200_aux.h	4805;"	d
+IRQ_EDCA1_TX_DONE_HI	include/ssv6200_aux.h	4774;"	d
+IRQ_EDCA1_TX_DONE_I_MSK	include/ssv6200_aux.h	4772;"	d
+IRQ_EDCA1_TX_DONE_MSK	include/ssv6200_aux.h	4771;"	d
+IRQ_EDCA1_TX_DONE_SD_HI	include/ssv6200_aux.h	5134;"	d
+IRQ_EDCA1_TX_DONE_SD_I_MSK	include/ssv6200_aux.h	5132;"	d
+IRQ_EDCA1_TX_DONE_SD_MSK	include/ssv6200_aux.h	5131;"	d
+IRQ_EDCA1_TX_DONE_SD_SFT	include/ssv6200_aux.h	5133;"	d
+IRQ_EDCA1_TX_DONE_SD_SZ	include/ssv6200_aux.h	5135;"	d
+IRQ_EDCA1_TX_DONE_SFT	include/ssv6200_aux.h	4773;"	d
+IRQ_EDCA1_TX_DONE_SZ	include/ssv6200_aux.h	4775;"	d
+IRQ_EDCA2_LOWTHOLD_INT_HI	include/ssv6200_aux.h	4809;"	d
+IRQ_EDCA2_LOWTHOLD_INT_I_MSK	include/ssv6200_aux.h	4807;"	d
+IRQ_EDCA2_LOWTHOLD_INT_MSK	include/ssv6200_aux.h	4806;"	d
+IRQ_EDCA2_LOWTHOLD_INT_SD_HI	include/ssv6200_aux.h	5169;"	d
+IRQ_EDCA2_LOWTHOLD_INT_SD_I_MSK	include/ssv6200_aux.h	5167;"	d
+IRQ_EDCA2_LOWTHOLD_INT_SD_MSK	include/ssv6200_aux.h	5166;"	d
+IRQ_EDCA2_LOWTHOLD_INT_SD_SFT	include/ssv6200_aux.h	5168;"	d
+IRQ_EDCA2_LOWTHOLD_INT_SD_SZ	include/ssv6200_aux.h	5170;"	d
+IRQ_EDCA2_LOWTHOLD_INT_SFT	include/ssv6200_aux.h	4808;"	d
+IRQ_EDCA2_LOWTHOLD_INT_SZ	include/ssv6200_aux.h	4810;"	d
+IRQ_EDCA2_TX_DONE_HI	include/ssv6200_aux.h	4779;"	d
+IRQ_EDCA2_TX_DONE_I_MSK	include/ssv6200_aux.h	4777;"	d
+IRQ_EDCA2_TX_DONE_MSK	include/ssv6200_aux.h	4776;"	d
+IRQ_EDCA2_TX_DONE_SD_HI	include/ssv6200_aux.h	5139;"	d
+IRQ_EDCA2_TX_DONE_SD_I_MSK	include/ssv6200_aux.h	5137;"	d
+IRQ_EDCA2_TX_DONE_SD_MSK	include/ssv6200_aux.h	5136;"	d
+IRQ_EDCA2_TX_DONE_SD_SFT	include/ssv6200_aux.h	5138;"	d
+IRQ_EDCA2_TX_DONE_SD_SZ	include/ssv6200_aux.h	5140;"	d
+IRQ_EDCA2_TX_DONE_SFT	include/ssv6200_aux.h	4778;"	d
+IRQ_EDCA2_TX_DONE_SZ	include/ssv6200_aux.h	4780;"	d
+IRQ_EDCA3_LOWTHOLD_INT_HI	include/ssv6200_aux.h	4814;"	d
+IRQ_EDCA3_LOWTHOLD_INT_I_MSK	include/ssv6200_aux.h	4812;"	d
+IRQ_EDCA3_LOWTHOLD_INT_MSK	include/ssv6200_aux.h	4811;"	d
+IRQ_EDCA3_LOWTHOLD_INT_SD_HI	include/ssv6200_aux.h	5174;"	d
+IRQ_EDCA3_LOWTHOLD_INT_SD_I_MSK	include/ssv6200_aux.h	5172;"	d
+IRQ_EDCA3_LOWTHOLD_INT_SD_MSK	include/ssv6200_aux.h	5171;"	d
+IRQ_EDCA3_LOWTHOLD_INT_SD_SFT	include/ssv6200_aux.h	5173;"	d
+IRQ_EDCA3_LOWTHOLD_INT_SD_SZ	include/ssv6200_aux.h	5175;"	d
+IRQ_EDCA3_LOWTHOLD_INT_SFT	include/ssv6200_aux.h	4813;"	d
+IRQ_EDCA3_LOWTHOLD_INT_SZ	include/ssv6200_aux.h	4815;"	d
+IRQ_EDCA3_TX_DONE_HI	include/ssv6200_aux.h	4784;"	d
+IRQ_EDCA3_TX_DONE_I_MSK	include/ssv6200_aux.h	4782;"	d
+IRQ_EDCA3_TX_DONE_MSK	include/ssv6200_aux.h	4781;"	d
+IRQ_EDCA3_TX_DONE_SD_HI	include/ssv6200_aux.h	5144;"	d
+IRQ_EDCA3_TX_DONE_SD_I_MSK	include/ssv6200_aux.h	5142;"	d
+IRQ_EDCA3_TX_DONE_SD_MSK	include/ssv6200_aux.h	5141;"	d
+IRQ_EDCA3_TX_DONE_SD_SFT	include/ssv6200_aux.h	5143;"	d
+IRQ_EDCA3_TX_DONE_SD_SZ	include/ssv6200_aux.h	5145;"	d
+IRQ_EDCA3_TX_DONE_SFT	include/ssv6200_aux.h	4783;"	d
+IRQ_EDCA3_TX_DONE_SZ	include/ssv6200_aux.h	4785;"	d
+IRQ_EDCA4_TX_DONE_HI	include/ssv6200_aux.h	4789;"	d
+IRQ_EDCA4_TX_DONE_I_MSK	include/ssv6200_aux.h	4787;"	d
+IRQ_EDCA4_TX_DONE_MSK	include/ssv6200_aux.h	4786;"	d
+IRQ_EDCA4_TX_DONE_SD_HI	include/ssv6200_aux.h	5149;"	d
+IRQ_EDCA4_TX_DONE_SD_I_MSK	include/ssv6200_aux.h	5147;"	d
+IRQ_EDCA4_TX_DONE_SD_MSK	include/ssv6200_aux.h	5146;"	d
+IRQ_EDCA4_TX_DONE_SD_SFT	include/ssv6200_aux.h	5148;"	d
+IRQ_EDCA4_TX_DONE_SD_SZ	include/ssv6200_aux.h	5150;"	d
+IRQ_EDCA4_TX_DONE_SFT	include/ssv6200_aux.h	4788;"	d
+IRQ_EDCA4_TX_DONE_SZ	include/ssv6200_aux.h	4790;"	d
+IRQ_FENCE_HIT_INT_HI	include/ssv6200_aux.h	4819;"	d
+IRQ_FENCE_HIT_INT_I_MSK	include/ssv6200_aux.h	4817;"	d
+IRQ_FENCE_HIT_INT_MSK	include/ssv6200_aux.h	4816;"	d
+IRQ_FENCE_HIT_INT_SD_HI	include/ssv6200_aux.h	5179;"	d
+IRQ_FENCE_HIT_INT_SD_I_MSK	include/ssv6200_aux.h	5177;"	d
+IRQ_FENCE_HIT_INT_SD_MSK	include/ssv6200_aux.h	5176;"	d
+IRQ_FENCE_HIT_INT_SD_SFT	include/ssv6200_aux.h	5178;"	d
+IRQ_FENCE_HIT_INT_SD_SZ	include/ssv6200_aux.h	5180;"	d
+IRQ_FENCE_HIT_INT_SFT	include/ssv6200_aux.h	4818;"	d
+IRQ_FENCE_HIT_INT_SZ	include/ssv6200_aux.h	4820;"	d
+IRQ_ILL_ADDR_INT_HI	include/ssv6200_aux.h	4824;"	d
+IRQ_ILL_ADDR_INT_I_MSK	include/ssv6200_aux.h	4822;"	d
+IRQ_ILL_ADDR_INT_MSK	include/ssv6200_aux.h	4821;"	d
+IRQ_ILL_ADDR_INT_SD_HI	include/ssv6200_aux.h	5184;"	d
+IRQ_ILL_ADDR_INT_SD_I_MSK	include/ssv6200_aux.h	5182;"	d
+IRQ_ILL_ADDR_INT_SD_MSK	include/ssv6200_aux.h	5181;"	d
+IRQ_ILL_ADDR_INT_SD_SFT	include/ssv6200_aux.h	5183;"	d
+IRQ_ILL_ADDR_INT_SD_SZ	include/ssv6200_aux.h	5185;"	d
+IRQ_ILL_ADDR_INT_SFT	include/ssv6200_aux.h	4823;"	d
+IRQ_ILL_ADDR_INT_SZ	include/ssv6200_aux.h	4825;"	d
+IRQ_MBOX_HI	include/ssv6200_aux.h	4829;"	d
+IRQ_MBOX_I_MSK	include/ssv6200_aux.h	4827;"	d
+IRQ_MBOX_MSK	include/ssv6200_aux.h	4826;"	d
+IRQ_MBOX_SD_HI	include/ssv6200_aux.h	5189;"	d
+IRQ_MBOX_SD_I_MSK	include/ssv6200_aux.h	5187;"	d
+IRQ_MBOX_SD_MSK	include/ssv6200_aux.h	5186;"	d
+IRQ_MBOX_SD_SFT	include/ssv6200_aux.h	5188;"	d
+IRQ_MBOX_SD_SZ	include/ssv6200_aux.h	5190;"	d
+IRQ_MBOX_SFT	include/ssv6200_aux.h	4828;"	d
+IRQ_MBOX_SZ	include/ssv6200_aux.h	4830;"	d
+IRQ_MS_TIMER0_HI	include/ssv6200_aux.h	4854;"	d
+IRQ_MS_TIMER0_I_MSK	include/ssv6200_aux.h	4852;"	d
+IRQ_MS_TIMER0_MSK	include/ssv6200_aux.h	4851;"	d
+IRQ_MS_TIMER0_SD_HI	include/ssv6200_aux.h	5214;"	d
+IRQ_MS_TIMER0_SD_I_MSK	include/ssv6200_aux.h	5212;"	d
+IRQ_MS_TIMER0_SD_MSK	include/ssv6200_aux.h	5211;"	d
+IRQ_MS_TIMER0_SD_SFT	include/ssv6200_aux.h	5213;"	d
+IRQ_MS_TIMER0_SD_SZ	include/ssv6200_aux.h	5215;"	d
+IRQ_MS_TIMER0_SFT	include/ssv6200_aux.h	4853;"	d
+IRQ_MS_TIMER0_SZ	include/ssv6200_aux.h	4855;"	d
+IRQ_MS_TIMER1_HI	include/ssv6200_aux.h	4859;"	d
+IRQ_MS_TIMER1_I_MSK	include/ssv6200_aux.h	4857;"	d
+IRQ_MS_TIMER1_MSK	include/ssv6200_aux.h	4856;"	d
+IRQ_MS_TIMER1_SD_HI	include/ssv6200_aux.h	5219;"	d
+IRQ_MS_TIMER1_SD_I_MSK	include/ssv6200_aux.h	5217;"	d
+IRQ_MS_TIMER1_SD_MSK	include/ssv6200_aux.h	5216;"	d
+IRQ_MS_TIMER1_SD_SFT	include/ssv6200_aux.h	5218;"	d
+IRQ_MS_TIMER1_SD_SZ	include/ssv6200_aux.h	5220;"	d
+IRQ_MS_TIMER1_SFT	include/ssv6200_aux.h	4858;"	d
+IRQ_MS_TIMER1_SZ	include/ssv6200_aux.h	4860;"	d
+IRQ_MS_TIMER2_HI	include/ssv6200_aux.h	4864;"	d
+IRQ_MS_TIMER2_I_MSK	include/ssv6200_aux.h	4862;"	d
+IRQ_MS_TIMER2_MSK	include/ssv6200_aux.h	4861;"	d
+IRQ_MS_TIMER2_SD_HI	include/ssv6200_aux.h	5224;"	d
+IRQ_MS_TIMER2_SD_I_MSK	include/ssv6200_aux.h	5222;"	d
+IRQ_MS_TIMER2_SD_MSK	include/ssv6200_aux.h	5221;"	d
+IRQ_MS_TIMER2_SD_SFT	include/ssv6200_aux.h	5223;"	d
+IRQ_MS_TIMER2_SD_SZ	include/ssv6200_aux.h	5225;"	d
+IRQ_MS_TIMER2_SFT	include/ssv6200_aux.h	4863;"	d
+IRQ_MS_TIMER2_SZ	include/ssv6200_aux.h	4865;"	d
+IRQ_MS_TIMER3_HI	include/ssv6200_aux.h	4869;"	d
+IRQ_MS_TIMER3_I_MSK	include/ssv6200_aux.h	4867;"	d
+IRQ_MS_TIMER3_MSK	include/ssv6200_aux.h	4866;"	d
+IRQ_MS_TIMER3_SD_HI	include/ssv6200_aux.h	5229;"	d
+IRQ_MS_TIMER3_SD_I_MSK	include/ssv6200_aux.h	5227;"	d
+IRQ_MS_TIMER3_SD_MSK	include/ssv6200_aux.h	5226;"	d
+IRQ_MS_TIMER3_SD_SFT	include/ssv6200_aux.h	5228;"	d
+IRQ_MS_TIMER3_SD_SZ	include/ssv6200_aux.h	5230;"	d
+IRQ_MS_TIMER3_SFT	include/ssv6200_aux.h	4868;"	d
+IRQ_MS_TIMER3_SZ	include/ssv6200_aux.h	4870;"	d
+IRQ_PERI_GROUP_HI	include/ssv6200_aux.h	4889;"	d
+IRQ_PERI_GROUP_I_MSK	include/ssv6200_aux.h	4887;"	d
+IRQ_PERI_GROUP_MSK	include/ssv6200_aux.h	4886;"	d
+IRQ_PERI_GROUP_SD_HI	include/ssv6200_aux.h	5249;"	d
+IRQ_PERI_GROUP_SD_I_MSK	include/ssv6200_aux.h	5247;"	d
+IRQ_PERI_GROUP_SD_MSK	include/ssv6200_aux.h	5246;"	d
+IRQ_PERI_GROUP_SD_SFT	include/ssv6200_aux.h	5248;"	d
+IRQ_PERI_GROUP_SD_SZ	include/ssv6200_aux.h	5250;"	d
+IRQ_PERI_GROUP_SFT	include/ssv6200_aux.h	4888;"	d
+IRQ_PERI_GROUP_SZ	include/ssv6200_aux.h	4890;"	d
+IRQ_PHY_0_HI	include/ssv6200_aux.h	4739;"	d
+IRQ_PHY_0_I_MSK	include/ssv6200_aux.h	4737;"	d
+IRQ_PHY_0_MSK	include/ssv6200_aux.h	4736;"	d
+IRQ_PHY_0_SD_HI	include/ssv6200_aux.h	5099;"	d
+IRQ_PHY_0_SD_I_MSK	include/ssv6200_aux.h	5097;"	d
+IRQ_PHY_0_SD_MSK	include/ssv6200_aux.h	5096;"	d
+IRQ_PHY_0_SD_SFT	include/ssv6200_aux.h	5098;"	d
+IRQ_PHY_0_SD_SZ	include/ssv6200_aux.h	5100;"	d
+IRQ_PHY_0_SFT	include/ssv6200_aux.h	4738;"	d
+IRQ_PHY_0_SZ	include/ssv6200_aux.h	4740;"	d
+IRQ_PHY_1_HI	include/ssv6200_aux.h	4744;"	d
+IRQ_PHY_1_I_MSK	include/ssv6200_aux.h	4742;"	d
+IRQ_PHY_1_MSK	include/ssv6200_aux.h	4741;"	d
+IRQ_PHY_1_SD_HI	include/ssv6200_aux.h	5104;"	d
+IRQ_PHY_1_SD_I_MSK	include/ssv6200_aux.h	5102;"	d
+IRQ_PHY_1_SD_MSK	include/ssv6200_aux.h	5101;"	d
+IRQ_PHY_1_SD_SFT	include/ssv6200_aux.h	5103;"	d
+IRQ_PHY_1_SD_SZ	include/ssv6200_aux.h	5105;"	d
+IRQ_PHY_1_SFT	include/ssv6200_aux.h	4743;"	d
+IRQ_PHY_1_SZ	include/ssv6200_aux.h	4745;"	d
+IRQ_PRE_BEACON_HI	include/ssv6200_aux.h	4764;"	d
+IRQ_PRE_BEACON_I_MSK	include/ssv6200_aux.h	4762;"	d
+IRQ_PRE_BEACON_MSK	include/ssv6200_aux.h	4761;"	d
+IRQ_PRE_BEACON_SD_HI	include/ssv6200_aux.h	5124;"	d
+IRQ_PRE_BEACON_SD_I_MSK	include/ssv6200_aux.h	5122;"	d
+IRQ_PRE_BEACON_SD_MSK	include/ssv6200_aux.h	5121;"	d
+IRQ_PRE_BEACON_SD_SFT	include/ssv6200_aux.h	5123;"	d
+IRQ_PRE_BEACON_SD_SZ	include/ssv6200_aux.h	5125;"	d
+IRQ_PRE_BEACON_SFT	include/ssv6200_aux.h	4763;"	d
+IRQ_PRE_BEACON_SZ	include/ssv6200_aux.h	4765;"	d
+IRQ_RAW_HI	include/ssv6200_aux.h	4899;"	d
+IRQ_RAW_I_MSK	include/ssv6200_aux.h	4897;"	d
+IRQ_RAW_MSK	include/ssv6200_aux.h	4896;"	d
+IRQ_RAW_SFT	include/ssv6200_aux.h	4898;"	d
+IRQ_RAW_SZ	include/ssv6200_aux.h	4900;"	d
+IRQ_RES_NAME	platforms/a33-generic-wlan.c	63;"	d	file:
+IRQ_RES_NAME	platforms/atm7039-action-generic-wlan.c	74;"	d	file:
+IRQ_RES_NAME	platforms/h3-generic-wlan.c	54;"	d	file:
+IRQ_RES_NAME	platforms/h8-generic-wlan.c	54;"	d	file:
+IRQ_RES_NAME	platforms/t10-generic-wlan.c	53;"	d	file:
+IRQ_RES_NAME	platforms/x1000-generic-wlan.c	53;"	d	file:
+IRQ_SDIO_HI	include/ssv6200_aux.h	4749;"	d
+IRQ_SDIO_I_MSK	include/ssv6200_aux.h	4747;"	d
+IRQ_SDIO_MSK	include/ssv6200_aux.h	4746;"	d
+IRQ_SDIO_SD_HI	include/ssv6200_aux.h	5109;"	d
+IRQ_SDIO_SD_I_MSK	include/ssv6200_aux.h	5107;"	d
+IRQ_SDIO_SD_MSK	include/ssv6200_aux.h	5106;"	d
+IRQ_SDIO_SD_SFT	include/ssv6200_aux.h	5108;"	d
+IRQ_SDIO_SD_SZ	include/ssv6200_aux.h	5110;"	d
+IRQ_SDIO_SFT	include/ssv6200_aux.h	4748;"	d
+IRQ_SDIO_SZ	include/ssv6200_aux.h	4750;"	d
+IRQ_SPI_IPC_HI	include/ssv6200_aux.h	4934;"	d
+IRQ_SPI_IPC_I_MSK	include/ssv6200_aux.h	4932;"	d
+IRQ_SPI_IPC_MSK	include/ssv6200_aux.h	4931;"	d
+IRQ_SPI_IPC_SD_HI	include/ssv6200_aux.h	5279;"	d
+IRQ_SPI_IPC_SD_I_MSK	include/ssv6200_aux.h	5277;"	d
+IRQ_SPI_IPC_SD_MSK	include/ssv6200_aux.h	5276;"	d
+IRQ_SPI_IPC_SD_SFT	include/ssv6200_aux.h	5278;"	d
+IRQ_SPI_IPC_SD_SZ	include/ssv6200_aux.h	5280;"	d
+IRQ_SPI_IPC_SFT	include/ssv6200_aux.h	4933;"	d
+IRQ_SPI_IPC_SZ	include/ssv6200_aux.h	4935;"	d
+IRQ_TX_LIMIT_INT_HI	include/ssv6200_aux.h	4874;"	d
+IRQ_TX_LIMIT_INT_I_MSK	include/ssv6200_aux.h	4872;"	d
+IRQ_TX_LIMIT_INT_MSK	include/ssv6200_aux.h	4871;"	d
+IRQ_TX_LIMIT_INT_SD_HI	include/ssv6200_aux.h	5234;"	d
+IRQ_TX_LIMIT_INT_SD_I_MSK	include/ssv6200_aux.h	5232;"	d
+IRQ_TX_LIMIT_INT_SD_MSK	include/ssv6200_aux.h	5231;"	d
+IRQ_TX_LIMIT_INT_SD_SFT	include/ssv6200_aux.h	5233;"	d
+IRQ_TX_LIMIT_INT_SD_SZ	include/ssv6200_aux.h	5235;"	d
+IRQ_TX_LIMIT_INT_SFT	include/ssv6200_aux.h	4873;"	d
+IRQ_TX_LIMIT_INT_SZ	include/ssv6200_aux.h	4875;"	d
+IRQ_UART0_RX_HI	include/ssv6200_aux.h	4924;"	d
+IRQ_UART0_RX_I_MSK	include/ssv6200_aux.h	4922;"	d
+IRQ_UART0_RX_MSK	include/ssv6200_aux.h	4921;"	d
+IRQ_UART0_RX_SD_HI	include/ssv6200_aux.h	5269;"	d
+IRQ_UART0_RX_SD_I_MSK	include/ssv6200_aux.h	5267;"	d
+IRQ_UART0_RX_SD_MSK	include/ssv6200_aux.h	5266;"	d
+IRQ_UART0_RX_SD_SFT	include/ssv6200_aux.h	5268;"	d
+IRQ_UART0_RX_SD_SZ	include/ssv6200_aux.h	5270;"	d
+IRQ_UART0_RX_SFT	include/ssv6200_aux.h	4923;"	d
+IRQ_UART0_RX_SZ	include/ssv6200_aux.h	4925;"	d
+IRQ_UART0_TX_HI	include/ssv6200_aux.h	4919;"	d
+IRQ_UART0_TX_I_MSK	include/ssv6200_aux.h	4917;"	d
+IRQ_UART0_TX_MSK	include/ssv6200_aux.h	4916;"	d
+IRQ_UART0_TX_SD_HI	include/ssv6200_aux.h	5264;"	d
+IRQ_UART0_TX_SD_I_MSK	include/ssv6200_aux.h	5262;"	d
+IRQ_UART0_TX_SD_MSK	include/ssv6200_aux.h	5261;"	d
+IRQ_UART0_TX_SD_SFT	include/ssv6200_aux.h	5263;"	d
+IRQ_UART0_TX_SD_SZ	include/ssv6200_aux.h	5265;"	d
+IRQ_UART0_TX_SFT	include/ssv6200_aux.h	4918;"	d
+IRQ_UART0_TX_SZ	include/ssv6200_aux.h	4920;"	d
+IRQ_US_TIMER0_HI	include/ssv6200_aux.h	4834;"	d
+IRQ_US_TIMER0_I_MSK	include/ssv6200_aux.h	4832;"	d
+IRQ_US_TIMER0_MSK	include/ssv6200_aux.h	4831;"	d
+IRQ_US_TIMER0_SD_HI	include/ssv6200_aux.h	5194;"	d
+IRQ_US_TIMER0_SD_I_MSK	include/ssv6200_aux.h	5192;"	d
+IRQ_US_TIMER0_SD_MSK	include/ssv6200_aux.h	5191;"	d
+IRQ_US_TIMER0_SD_SFT	include/ssv6200_aux.h	5193;"	d
+IRQ_US_TIMER0_SD_SZ	include/ssv6200_aux.h	5195;"	d
+IRQ_US_TIMER0_SFT	include/ssv6200_aux.h	4833;"	d
+IRQ_US_TIMER0_SZ	include/ssv6200_aux.h	4835;"	d
+IRQ_US_TIMER1_HI	include/ssv6200_aux.h	4839;"	d
+IRQ_US_TIMER1_I_MSK	include/ssv6200_aux.h	4837;"	d
+IRQ_US_TIMER1_MSK	include/ssv6200_aux.h	4836;"	d
+IRQ_US_TIMER1_SD_HI	include/ssv6200_aux.h	5199;"	d
+IRQ_US_TIMER1_SD_I_MSK	include/ssv6200_aux.h	5197;"	d
+IRQ_US_TIMER1_SD_MSK	include/ssv6200_aux.h	5196;"	d
+IRQ_US_TIMER1_SD_SFT	include/ssv6200_aux.h	5198;"	d
+IRQ_US_TIMER1_SD_SZ	include/ssv6200_aux.h	5200;"	d
+IRQ_US_TIMER1_SFT	include/ssv6200_aux.h	4838;"	d
+IRQ_US_TIMER1_SZ	include/ssv6200_aux.h	4840;"	d
+IRQ_US_TIMER2_HI	include/ssv6200_aux.h	4844;"	d
+IRQ_US_TIMER2_I_MSK	include/ssv6200_aux.h	4842;"	d
+IRQ_US_TIMER2_MSK	include/ssv6200_aux.h	4841;"	d
+IRQ_US_TIMER2_SD_HI	include/ssv6200_aux.h	5204;"	d
+IRQ_US_TIMER2_SD_I_MSK	include/ssv6200_aux.h	5202;"	d
+IRQ_US_TIMER2_SD_MSK	include/ssv6200_aux.h	5201;"	d
+IRQ_US_TIMER2_SD_SFT	include/ssv6200_aux.h	5203;"	d
+IRQ_US_TIMER2_SD_SZ	include/ssv6200_aux.h	5205;"	d
+IRQ_US_TIMER2_SFT	include/ssv6200_aux.h	4843;"	d
+IRQ_US_TIMER2_SZ	include/ssv6200_aux.h	4845;"	d
+IRQ_US_TIMER3_HI	include/ssv6200_aux.h	4849;"	d
+IRQ_US_TIMER3_I_MSK	include/ssv6200_aux.h	4847;"	d
+IRQ_US_TIMER3_MSK	include/ssv6200_aux.h	4846;"	d
+IRQ_US_TIMER3_SD_HI	include/ssv6200_aux.h	5209;"	d
+IRQ_US_TIMER3_SD_I_MSK	include/ssv6200_aux.h	5207;"	d
+IRQ_US_TIMER3_SD_MSK	include/ssv6200_aux.h	5206;"	d
+IRQ_US_TIMER3_SD_SFT	include/ssv6200_aux.h	5208;"	d
+IRQ_US_TIMER3_SD_SZ	include/ssv6200_aux.h	5210;"	d
+IRQ_US_TIMER3_SFT	include/ssv6200_aux.h	4848;"	d
+IRQ_US_TIMER3_SZ	include/ssv6200_aux.h	4850;"	d
+IS_ALLOW_SCAN	smac/dev.h	796;"	d
+IS_BIT_SET	smac/ap.c	40;"	d	file:
+IS_EQUAL	smac/ap.c	37;"	d	file:
+IS_GLUE_INVALID	hwif/sdio/sdio.c	77;"	d	file:
+IS_GLUE_INVALID	hwif/usb/usb.c	45;"	d	file:
+IS_MGMT_AND_BLOCK_CNTL	smac/dev.h	799;"	d
+IS_NONE_STA_CONNECTED_IN_AP_MODE	smac/dev.h	798;"	d
+IS_NON_AP_MODE	smac/dev.h	797;"	d
+IS_SSV_HT	smac/dev.h	192;"	d
+IS_SSV_HT_GF	smac/dev.h	194;"	d
+IS_SSV_SHORT_GI	smac/dev.h	193;"	d
+IS_SSV_SHORT_PRE	smac/dev.h	195;"	d
+IWAPIELEMENT	smac/sec_wpi.c	29;"	d	file:
+Iterate	smac/wapi_sms4.c	/^static u32 Iterate(CsrBool Key, u32 Next_Input, u32 *Cipher_Text, u32 curIdx)$/;"	f	file:	signature:(CsrBool Key, u32 Next_Input, u32 *Cipher_Text, u32 curIdx)
+JTAG_TCK_ID_HI	include/ssv6200_aux.h	2309;"	d
+JTAG_TCK_ID_I_MSK	include/ssv6200_aux.h	2307;"	d
+JTAG_TCK_ID_MSK	include/ssv6200_aux.h	2306;"	d
+JTAG_TCK_ID_SFT	include/ssv6200_aux.h	2308;"	d
+JTAG_TCK_ID_SZ	include/ssv6200_aux.h	2310;"	d
+JTAG_TDI_ID_HI	include/ssv6200_aux.h	2334;"	d
+JTAG_TDI_ID_I_MSK	include/ssv6200_aux.h	2332;"	d
+JTAG_TDI_ID_MSK	include/ssv6200_aux.h	2331;"	d
+JTAG_TDI_ID_SFT	include/ssv6200_aux.h	2333;"	d
+JTAG_TDI_ID_SZ	include/ssv6200_aux.h	2335;"	d
+JTAG_TDO_ID_HI	include/ssv6200_aux.h	2379;"	d
+JTAG_TDO_ID_I_MSK	include/ssv6200_aux.h	2377;"	d
+JTAG_TDO_ID_MSK	include/ssv6200_aux.h	2376;"	d
+JTAG_TDO_ID_SFT	include/ssv6200_aux.h	2378;"	d
+JTAG_TDO_ID_SZ	include/ssv6200_aux.h	2380;"	d
+JTAG_TMS_ID_HI	include/ssv6200_aux.h	2279;"	d
+JTAG_TMS_ID_I_MSK	include/ssv6200_aux.h	2277;"	d
+JTAG_TMS_ID_MSK	include/ssv6200_aux.h	2276;"	d
+JTAG_TMS_ID_SFT	include/ssv6200_aux.h	2278;"	d
+JTAG_TMS_ID_SZ	include/ssv6200_aux.h	2280;"	d
+JUDGE_CNT_CLR_HI	include/ssv6200_aux.h	4064;"	d
+JUDGE_CNT_CLR_I_MSK	include/ssv6200_aux.h	4062;"	d
+JUDGE_CNT_CLR_MSK	include/ssv6200_aux.h	4061;"	d
+JUDGE_CNT_CLR_SFT	include/ssv6200_aux.h	4063;"	d
+JUDGE_CNT_CLR_SZ	include/ssv6200_aux.h	4065;"	d
+JUDGE_CNT_HI	include/ssv6200_aux.h	4049;"	d
+JUDGE_CNT_I_MSK	include/ssv6200_aux.h	4047;"	d
+JUDGE_CNT_MSK	include/ssv6200_aux.h	4046;"	d
+JUDGE_CNT_SFT	include/ssv6200_aux.h	4048;"	d
+JUDGE_CNT_SZ	include/ssv6200_aux.h	4050;"	d
+KBUILD_DIR	bridge/Makefile	/^    KBUILD_DIR := $(KBUILD_EXTMOD)$/;"	m
+KBUILD_DIR	bridge/Makefile	/^    KBUILD_DIR := $(PWD)$/;"	m
+KBUILD_DIR	hci/Makefile	/^    KBUILD_DIR := $(KBUILD_EXTMOD)$/;"	m
+KBUILD_DIR	hci/Makefile	/^    KBUILD_DIR := $(PWD)$/;"	m
+KBUILD_DIR	hci_wrapper/Makefile	/^    KBUILD_DIR := $(KBUILD_EXTMOD)$/;"	m
+KBUILD_DIR	hci_wrapper/Makefile	/^    KBUILD_DIR := $(PWD)$/;"	m
+KBUILD_DIR	hwif/sdio/Makefile	/^    KBUILD_DIR := $(KBUILD_EXTMOD)$/;"	m
+KBUILD_DIR	hwif/sdio/Makefile	/^    KBUILD_DIR := $(PWD)$/;"	m
+KBUILD_DIR	hwif/usb/Makefile	/^    KBUILD_DIR := $(KBUILD_EXTMOD)$/;"	m
+KBUILD_DIR	hwif/usb/Makefile	/^    KBUILD_DIR := $(PWD)$/;"	m
+KBUILD_DIR	smac/Makefile	/^    KBUILD_DIR := $(KBUILD_EXTMOD)$/;"	m
+KBUILD_DIR	smac/Makefile	/^    KBUILD_DIR := $(PWD)$/;"	m
+KBUILD_DIR	ssvdevice/Makefile	/^    KBUILD_DIR := $(KBUILD_EXTMOD)$/;"	m
+KBUILD_DIR	ssvdevice/Makefile	/^    KBUILD_DIR := $(PWD)$/;"	m
+KBUILD_DIR	umac/Makefile	/^    KBUILD_DIR := $(KBUILD_EXTMOD)$/;"	m
+KBUILD_DIR	umac/Makefile	/^    KBUILD_DIR := $(PWD)$/;"	m
+KBUILD_TOP	Makefile	/^KBUILD_TOP := $(KBUILD_EXTMOD)$/;"	m
+KBUILD_TOP	Makefile	/^KBUILD_TOP := $(PWD)$/;"	m
+KBUILD_TOP	bridge/Makefile	/^KBUILD_TOP := $(KBUILD_DIR)\/..\/$/;"	m
+KBUILD_TOP	hci/Makefile	/^KBUILD_TOP := $(KBUILD_DIR)\/..\/$/;"	m
+KBUILD_TOP	hci_wrapper/Makefile	/^KBUILD_TOP := $(KBUILD_DIR)\/..\/$/;"	m
+KBUILD_TOP	hwif/sdio/Makefile	/^KBUILD_TOP := $(KBUILD_DIR)\/..\/..\/$/;"	m
+KBUILD_TOP	hwif/usb/Makefile	/^KBUILD_TOP := $(KBUILD_DIR)\/..\/..\/$/;"	m
+KBUILD_TOP	smac/Makefile	/^KBUILD_TOP := $(KBUILD_DIR)\/..\/$/;"	m
+KBUILD_TOP	ssvdevice/Makefile	/^KBUILD_TOP := $(KBUILD_DIR)\/..\/$/;"	m
+KBUILD_TOP	umac/Makefile	/^KBUILD_TOP := $(KBUILD_DIR)\/..\/$/;"	m
+KDIR	bridge/aaa.mk	/^KDIR=\/lib\/modules\/`uname -r`\/build$/;"	m
+KERNEL_MODULES	Makefile	/^KERNEL_MODULES := ssvdevice$/;"	m
+KERN_SRCS	bridge/Makefile	/^KERN_SRCS := sdiobridge.c$/;"	m
+KERN_SRCS	hci_wrapper/Makefile	/^KERN_SRCS := ssv_huw.c$/;"	m
+KERN_SRCS	hwif/sdio/Makefile	/^KERN_SRCS := sdio.c$/;"	m
+KERN_SRCS	hwif/usb/Makefile	/^KERN_SRCS := usb.c$/;"	m
+KERN_SRCS	smac/Makefile	/^KERN_SRCS := init.c$/;"	m
+KERN_SRCS	ssvdevice/Makefile	/^KERN_SRCS := ssvdevice.c$/;"	m
+KERN_SRCS	umac/Makefile	/^KERN_SRCS := ssv6xxx_netlink_core.c$/;"	m
+KEY_DIN_MSB_HI	include/ssv6200_aux.h	6724;"	d
+KEY_DIN_MSB_I_MSK	include/ssv6200_aux.h	6722;"	d
+KEY_DIN_MSB_MSK	include/ssv6200_aux.h	6721;"	d
+KEY_DIN_MSB_SFT	include/ssv6200_aux.h	6723;"	d
+KEY_DIN_MSB_SZ	include/ssv6200_aux.h	6725;"	d
+KEY_MULTIPLIER	smac/wapi_sms4.c	32;"	d	file:
+KMODULE_NAME	bridge/Makefile	/^KMODULE_NAME=ssv6200_sdiobridge$/;"	m
+KMODULE_NAME	hci/Makefile	/^KMODULE_NAME=ssv6200_hci$/;"	m
+KMODULE_NAME	hci_wrapper/Makefile	/^KMODULE_NAME=hci_wrapper$/;"	m
+KMODULE_NAME	hwif/sdio/Makefile	/^KMODULE_NAME=ssv6200_sdio$/;"	m
+KMODULE_NAME	hwif/usb/Makefile	/^KMODULE_NAME=ssv6200_usb$/;"	m
+KMODULE_NAME	smac/Makefile	/^KMODULE_NAME=ssv6200s_core$/;"	m
+KMODULE_NAME	ssvdevice/Makefile	/^KMODULE_NAME=ssvdevicetype$/;"	m
+KMODULE_NAME	umac/Makefile	/^KMODULE_NAME=ssv6xxx_umac_core$/;"	m
+KSMARTLINK_ATTR_CHANNEL	smac/ksmartlink.c	/^    KSMARTLINK_ATTR_CHANNEL,$/;"	e	enum:__anon9	file:
+KSMARTLINK_ATTR_CHANNEL	smartlink/ssv_smartlink.c	/^    KSMARTLINK_ATTR_CHANNEL,$/;"	e	enum:__anon36	file:
+KSMARTLINK_ATTR_ENABLE	smac/ksmartlink.c	/^    KSMARTLINK_ATTR_ENABLE,$/;"	e	enum:__anon9	file:
+KSMARTLINK_ATTR_ENABLE	smartlink/ssv_smartlink.c	/^    KSMARTLINK_ATTR_ENABLE,$/;"	e	enum:__anon36	file:
+KSMARTLINK_ATTR_MAX	smac/ksmartlink.c	49;"	d	file:
+KSMARTLINK_ATTR_MAX	smartlink/ssv_smartlink.c	40;"	d	file:
+KSMARTLINK_ATTR_PROMISC	smac/ksmartlink.c	/^    KSMARTLINK_ATTR_PROMISC,$/;"	e	enum:__anon9	file:
+KSMARTLINK_ATTR_PROMISC	smartlink/ssv_smartlink.c	/^    KSMARTLINK_ATTR_PROMISC,$/;"	e	enum:__anon36	file:
+KSMARTLINK_ATTR_RXFRAME	smac/ksmartlink.c	/^    KSMARTLINK_ATTR_RXFRAME,$/;"	e	enum:__anon9	file:
+KSMARTLINK_ATTR_RXFRAME	smartlink/ssv_smartlink.c	/^    KSMARTLINK_ATTR_RXFRAME,$/;"	e	enum:__anon36	file:
+KSMARTLINK_ATTR_SI_CMD	smac/ksmartlink.c	/^    KSMARTLINK_ATTR_SI_CMD,$/;"	e	enum:__anon9	file:
+KSMARTLINK_ATTR_SI_CMD	smartlink/ssv_smartlink.c	/^    KSMARTLINK_ATTR_SI_CMD,$/;"	e	enum:__anon36	file:
+KSMARTLINK_ATTR_SI_PASS	smac/ksmartlink.c	/^    KSMARTLINK_ATTR_SI_PASS,$/;"	e	enum:__anon9	file:
+KSMARTLINK_ATTR_SI_PASS	smartlink/ssv_smartlink.c	/^    KSMARTLINK_ATTR_SI_PASS,$/;"	e	enum:__anon36	file:
+KSMARTLINK_ATTR_SI_SSID	smac/ksmartlink.c	/^    KSMARTLINK_ATTR_SI_SSID,$/;"	e	enum:__anon9	file:
+KSMARTLINK_ATTR_SI_SSID	smartlink/ssv_smartlink.c	/^    KSMARTLINK_ATTR_SI_SSID,$/;"	e	enum:__anon36	file:
+KSMARTLINK_ATTR_SI_STATUS	smac/ksmartlink.c	/^    KSMARTLINK_ATTR_SI_STATUS,$/;"	e	enum:__anon9	file:
+KSMARTLINK_ATTR_SI_STATUS	smartlink/ssv_smartlink.c	/^    KSMARTLINK_ATTR_SI_STATUS,$/;"	e	enum:__anon36	file:
+KSMARTLINK_ATTR_SUCCESS	smac/ksmartlink.c	/^    KSMARTLINK_ATTR_SUCCESS,$/;"	e	enum:__anon9	file:
+KSMARTLINK_ATTR_SUCCESS	smartlink/ssv_smartlink.c	/^    KSMARTLINK_ATTR_SUCCESS,$/;"	e	enum:__anon36	file:
+KSMARTLINK_ATTR_UNSPEC	smac/ksmartlink.c	/^    KSMARTLINK_ATTR_UNSPEC,$/;"	e	enum:__anon9	file:
+KSMARTLINK_ATTR_UNSPEC	smartlink/ssv_smartlink.c	/^    KSMARTLINK_ATTR_UNSPEC,$/;"	e	enum:__anon36	file:
+KSMARTLINK_CMD_GET_CHANNEL	smac/ksmartlink.c	/^    KSMARTLINK_CMD_GET_CHANNEL,$/;"	e	enum:__anon10	file:
+KSMARTLINK_CMD_GET_CHANNEL	smartlink/ssv_smartlink.c	/^    KSMARTLINK_CMD_GET_CHANNEL,$/;"	e	enum:__anon37	file:
+KSMARTLINK_CMD_GET_PROMISC	smac/ksmartlink.c	/^    KSMARTLINK_CMD_GET_PROMISC,$/;"	e	enum:__anon10	file:
+KSMARTLINK_CMD_GET_PROMISC	smartlink/ssv_smartlink.c	/^    KSMARTLINK_CMD_GET_PROMISC,$/;"	e	enum:__anon37	file:
+KSMARTLINK_CMD_GET_SI_PASS	smac/ksmartlink.c	/^    KSMARTLINK_CMD_GET_SI_PASS,$/;"	e	enum:__anon10	file:
+KSMARTLINK_CMD_GET_SI_PASS	smartlink/ssv_smartlink.c	/^    KSMARTLINK_CMD_GET_SI_PASS,$/;"	e	enum:__anon37	file:
+KSMARTLINK_CMD_GET_SI_SSID	smac/ksmartlink.c	/^    KSMARTLINK_CMD_GET_SI_SSID,$/;"	e	enum:__anon10	file:
+KSMARTLINK_CMD_GET_SI_SSID	smartlink/ssv_smartlink.c	/^    KSMARTLINK_CMD_GET_SI_SSID,$/;"	e	enum:__anon37	file:
+KSMARTLINK_CMD_GET_SI_STATUS	smac/ksmartlink.c	/^    KSMARTLINK_CMD_GET_SI_STATUS,$/;"	e	enum:__anon10	file:
+KSMARTLINK_CMD_GET_SI_STATUS	smartlink/ssv_smartlink.c	/^    KSMARTLINK_CMD_GET_SI_STATUS,$/;"	e	enum:__anon37	file:
+KSMARTLINK_CMD_MAX	smac/ksmartlink.c	83;"	d	file:
+KSMARTLINK_CMD_MAX	smartlink/ssv_smartlink.c	56;"	d	file:
+KSMARTLINK_CMD_RX_FRAME	smac/ksmartlink.c	/^    KSMARTLINK_CMD_RX_FRAME,$/;"	e	enum:__anon10	file:
+KSMARTLINK_CMD_RX_FRAME	smartlink/ssv_smartlink.c	/^    KSMARTLINK_CMD_RX_FRAME,$/;"	e	enum:__anon37	file:
+KSMARTLINK_CMD_SET_CHANNEL	smac/ksmartlink.c	/^    KSMARTLINK_CMD_SET_CHANNEL,$/;"	e	enum:__anon10	file:
+KSMARTLINK_CMD_SET_CHANNEL	smartlink/ssv_smartlink.c	/^    KSMARTLINK_CMD_SET_CHANNEL,$/;"	e	enum:__anon37	file:
+KSMARTLINK_CMD_SET_PROMISC	smac/ksmartlink.c	/^    KSMARTLINK_CMD_SET_PROMISC,$/;"	e	enum:__anon10	file:
+KSMARTLINK_CMD_SET_PROMISC	smartlink/ssv_smartlink.c	/^    KSMARTLINK_CMD_SET_PROMISC,$/;"	e	enum:__anon37	file:
+KSMARTLINK_CMD_SET_SI_CMD	smac/ksmartlink.c	/^    KSMARTLINK_CMD_SET_SI_CMD,$/;"	e	enum:__anon10	file:
+KSMARTLINK_CMD_SET_SI_CMD	smartlink/ssv_smartlink.c	/^    KSMARTLINK_CMD_SET_SI_CMD,$/;"	e	enum:__anon37	file:
+KSMARTLINK_CMD_SMARTICOMM	smac/ksmartlink.c	/^    KSMARTLINK_CMD_SMARTICOMM,$/;"	e	enum:__anon10	file:
+KSMARTLINK_CMD_SMARTICOMM	smartlink/ssv_smartlink.c	/^    KSMARTLINK_CMD_SMARTICOMM,$/;"	e	enum:__anon37	file:
+KSMARTLINK_CMD_SMARTLINK	smac/ksmartlink.c	/^    KSMARTLINK_CMD_SMARTLINK,$/;"	e	enum:__anon10	file:
+KSMARTLINK_CMD_SMARTLINK	smartlink/ssv_smartlink.c	/^    KSMARTLINK_CMD_SMARTLINK,$/;"	e	enum:__anon37	file:
+KSMARTLINK_CMD_UNSPEC	smac/ksmartlink.c	/^    KSMARTLINK_CMD_UNSPEC,$/;"	e	enum:__anon10	file:
+KSMARTLINK_CMD_UNSPEC	smartlink/ssv_smartlink.c	/^    KSMARTLINK_CMD_UNSPEC,$/;"	e	enum:__anon37	file:
+KVERSION	config.mak	/^KVERSION="`uname -r`"$/;"	m
+L4_LEN_HI	include/ssv6200_aux.h	6364;"	d
+L4_LEN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5609;"	d
+L4_LEN_I_MSK	include/ssv6200_aux.h	6362;"	d
+L4_LEN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5607;"	d
+L4_LEN_MSK	include/ssv6200_aux.h	6361;"	d
+L4_LEN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5606;"	d
+L4_LEN_SFT	include/ssv6200_aux.h	6363;"	d
+L4_LEN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5608;"	d
+L4_LEN_SZ	include/ssv6200_aux.h	6365;"	d
+L4_LEN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5610;"	d
+L4_PROTOL_HI	include/ssv6200_aux.h	6369;"	d
+L4_PROTOL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5614;"	d
+L4_PROTOL_I_MSK	include/ssv6200_aux.h	6367;"	d
+L4_PROTOL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5612;"	d
+L4_PROTOL_MSK	include/ssv6200_aux.h	6366;"	d
+L4_PROTOL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5611;"	d
+L4_PROTOL_SFT	include/ssv6200_aux.h	6368;"	d
+L4_PROTOL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5613;"	d
+L4_PROTOL_SZ	include/ssv6200_aux.h	6370;"	d
+L4_PROTOL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5615;"	d
+LCK_BIN_RDY_HI	include/ssv6200_aux.h	17559;"	d
+LCK_BIN_RDY_I_MSK	include/ssv6200_aux.h	17557;"	d
+LCK_BIN_RDY_MSK	include/ssv6200_aux.h	17556;"	d
+LCK_BIN_RDY_SFT	include/ssv6200_aux.h	17558;"	d
+LCK_BIN_RDY_SZ	include/ssv6200_aux.h	17560;"	d
+LEN_FLT_HI	include/ssv6200_aux.h	7394;"	d
+LEN_FLT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6549;"	d
+LEN_FLT_I_MSK	include/ssv6200_aux.h	7392;"	d
+LEN_FLT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6547;"	d
+LEN_FLT_MSK	include/ssv6200_aux.h	7391;"	d
+LEN_FLT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6546;"	d
+LEN_FLT_SFT	include/ssv6200_aux.h	7393;"	d
+LEN_FLT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6548;"	d
+LEN_FLT_SZ	include/ssv6200_aux.h	7395;"	d
+LEN_FLT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6550;"	d
+LEN_HI	include/ssv6200_aux.h	6429;"	d
+LEN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5674;"	d
+LEN_I_MSK	include/ssv6200_aux.h	6427;"	d
+LEN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5672;"	d
+LEN_MSK	include/ssv6200_aux.h	6426;"	d
+LEN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5671;"	d
+LEN_RAW_PACKET	ssvdevice/ssv_cmd.c	1673;"	d	file:
+LEN_SFT	include/ssv6200_aux.h	6428;"	d
+LEN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5673;"	d
+LEN_SZ	include/ssv6200_aux.h	6430;"	d
+LEN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5675;"	d
+LOAD_TURISMOA_PHY_TABLE	smac/hal/ssv6006c/turismo_common.h	599;"	d
+LOAD_TURISMOA_RF_TABLE	smac/hal/ssv6006c/turismo_common.h	589;"	d
+LOAD_TURISMOB_PHY_TABLE	smac/hal/ssv6006c/turismo_common.h	1672;"	d
+LOAD_TURISMOB_RF_TABLE	smac/hal/ssv6006c/turismo_common.h	1662;"	d
+LOAD_TURISMOC_PHY_TABLE	smac/hal/ssv6006c/turismo_common.h	1866;"	d
+LOAD_TURISMOC_RF_TABLE	smac/hal/ssv6006c/turismo_common.h	1848;"	d
+LOG_AMPDU_DBG	include/ssv6xxx_common.h	37;"	d
+LOG_AMPDU_ERR	include/ssv6xxx_common.h	38;"	d
+LOG_AMPDU_SSN	include/ssv6xxx_common.h	36;"	d
+LOG_BEACON	include/ssv6xxx_common.h	39;"	d
+LOG_FLASH_BIN	include/ssv6xxx_common.h	48;"	d
+LOG_HAL	include/ssv6xxx_common.h	46;"	d
+LOG_HCI	include/ssv6xxx_common.h	44;"	d
+LOG_HWIF	include/ssv6xxx_common.h	45;"	d
+LOG_RATE_CONTROL	include/ssv6xxx_common.h	40;"	d
+LOG_RATE_REPORT	include/ssv6xxx_common.h	41;"	d
+LOG_REGW	include/ssv6xxx_common.h	47;"	d
+LOG_RX_DESC	include/ssv6xxx_common.h	43;"	d
+LOG_TX_DESC	include/ssv6xxx_common.h	35;"	d
+LOG_TX_FRAME	include/ssv6xxx_common.h	42;"	d
+LOOP_BACK_HI	include/ssv6200_aux.h	4384;"	d
+LOOP_BACK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3489;"	d
+LOOP_BACK_I_MSK	include/ssv6200_aux.h	4382;"	d
+LOOP_BACK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3487;"	d
+LOOP_BACK_MSK	include/ssv6200_aux.h	4381;"	d
+LOOP_BACK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3486;"	d
+LOOP_BACK_SFT	include/ssv6200_aux.h	4383;"	d
+LOOP_BACK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3488;"	d
+LOOP_BACK_SZ	include/ssv6200_aux.h	4385;"	d
+LOOP_BACK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3490;"	d
+LOWBATTERY_SAMPLE_MIN_COUNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5099;"	d
+LOWBATTERY_SAMPLE_MIN_COUNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5097;"	d
+LOWBATTERY_SAMPLE_MIN_COUNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5096;"	d
+LOWBATTERY_SAMPLE_MIN_COUNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5098;"	d
+LOWBATTERY_SAMPLE_MIN_COUNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5100;"	d
+LOW_ACTIVE_HI	include/ssv6200_aux.h	6499;"	d
+LOW_ACTIVE_I_MSK	include/ssv6200_aux.h	6497;"	d
+LOW_ACTIVE_MSK	include/ssv6200_aux.h	6496;"	d
+LOW_ACTIVE_SFT	include/ssv6200_aux.h	6498;"	d
+LOW_ACTIVE_SZ	include/ssv6200_aux.h	6500;"	d
+LOW_CRYPTO_Q_LEN	smac/dev.c	59;"	d	file:
+LOW_SPEED_CARD_4BIT_HI	include/ssv6200_aux.h	3719;"	d
+LOW_SPEED_CARD_4BIT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2844;"	d
+LOW_SPEED_CARD_4BIT_I_MSK	include/ssv6200_aux.h	3717;"	d
+LOW_SPEED_CARD_4BIT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2842;"	d
+LOW_SPEED_CARD_4BIT_MSK	include/ssv6200_aux.h	3716;"	d
+LOW_SPEED_CARD_4BIT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2841;"	d
+LOW_SPEED_CARD_4BIT_SFT	include/ssv6200_aux.h	3718;"	d
+LOW_SPEED_CARD_4BIT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2843;"	d
+LOW_SPEED_CARD_4BIT_SZ	include/ssv6200_aux.h	3720;"	d
+LOW_SPEED_CARD_4BIT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2845;"	d
+LOW_SPEED_CARD_HI	include/ssv6200_aux.h	3714;"	d
+LOW_SPEED_CARD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2839;"	d
+LOW_SPEED_CARD_I_MSK	include/ssv6200_aux.h	3712;"	d
+LOW_SPEED_CARD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2837;"	d
+LOW_SPEED_CARD_MSK	include/ssv6200_aux.h	3711;"	d
+LOW_SPEED_CARD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2836;"	d
+LOW_SPEED_CARD_SFT	include/ssv6200_aux.h	3713;"	d
+LOW_SPEED_CARD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2838;"	d
+LOW_SPEED_CARD_SZ	include/ssv6200_aux.h	3715;"	d
+LOW_SPEED_CARD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2840;"	d
+LOW_SPEED_SDIO_CLOCK	hwif/sdio/sdio.c	41;"	d	file:
+LOW_TX_Q_LEN	smac/dev.c	62;"	d	file:
+LUT_SEL_V2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8924;"	d
+LUT_SEL_V2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8922;"	d
+LUT_SEL_V2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8921;"	d
+LUT_SEL_V2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8923;"	d
+LUT_SEL_V2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8925;"	d
+L_LTF	smac/dev.h	163;"	d
+L_SIG	smac/dev.h	164;"	d
+L_STF	smac/dev.h	162;"	d
+L_TRANSFORM_MACRO	smac/wapi_sms4.c	94;"	d	file:
+Lo16	smac/sec_tkip.c	/^static inline u16 Lo16(u32 val)$/;"	f	file:	signature:(u32 val)
+Lo8	smac/sec_tkip.c	/^static inline u8 Lo8(u16 val)$/;"	f	file:	signature:(u16 val)
+M0_RXEVENT	include/ssv6xxx_common.h	67;"	d
+M0_RXEVENT	smac/hal/ssv6006c/ssv6006_common.h	53;"	d
+M0_TXREQ	include/ssv6xxx_common.h	64;"	d
+M0_TXREQ	smac/hal/ssv6006c/ssv6006_common.h	50;"	d
+M1_TXREQ	include/ssv6xxx_common.h	65;"	d
+M1_TXREQ	smac/hal/ssv6006c/ssv6006_common.h	51;"	d
+M2_RXEVENT	include/ssv6xxx_common.h	68;"	d
+M2_RXEVENT	smac/hal/ssv6006c/ssv6006_common.h	54;"	d
+M2_TXREQ	include/ssv6xxx_common.h	66;"	d
+M2_TXREQ	smac/hal/ssv6006c/ssv6006_common.h	52;"	d
+MAC2STR	smac/p2p.c	39;"	d	file:
+MACSTR	smac/p2p.c	40;"	d	file:
+MAC_ALL_RESET_HI	include/ssv6200_aux.h	3409;"	d
+MAC_ALL_RESET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2754;"	d
+MAC_ALL_RESET_I_MSK	include/ssv6200_aux.h	3407;"	d
+MAC_ALL_RESET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2752;"	d
+MAC_ALL_RESET_MSK	include/ssv6200_aux.h	3406;"	d
+MAC_ALL_RESET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2751;"	d
+MAC_ALL_RESET_SFT	include/ssv6200_aux.h	3408;"	d
+MAC_ALL_RESET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2753;"	d
+MAC_ALL_RESET_SZ	include/ssv6200_aux.h	3410;"	d
+MAC_ALL_RESET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2755;"	d
+MAC_CLK_80M_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7369;"	d
+MAC_CLK_80M_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7367;"	d
+MAC_CLK_80M_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7366;"	d
+MAC_CLK_80M_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7368;"	d
+MAC_CLK_80M_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7370;"	d
+MAC_CLK_EN_HI	include/ssv6200_aux.h	194;"	d
+MAC_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1144;"	d
+MAC_CLK_EN_I_MSK	include/ssv6200_aux.h	192;"	d
+MAC_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1142;"	d
+MAC_CLK_EN_MSK	include/ssv6200_aux.h	191;"	d
+MAC_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1141;"	d
+MAC_CLK_EN_SFT	include/ssv6200_aux.h	193;"	d
+MAC_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1143;"	d
+MAC_CLK_EN_SZ	include/ssv6200_aux.h	195;"	d
+MAC_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1145;"	d
+MAC_DECITBL1_SIZE	smac/dev.h	130;"	d
+MAC_DECITBL2_SIZE	smac/dev.h	131;"	d
+MAC_GLB_SET_BANK_SIZE	include/ssv6200_reg.h	105;"	d
+MAC_GLB_SET_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	126;"	d
+MAC_GLB_SET_BASE	include/ssv6200_reg.h	56;"	d
+MAC_GLB_SET_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	65;"	d
+MAC_SW_RST_HI	include/ssv6200_aux.h	24;"	d
+MAC_SW_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	979;"	d
+MAC_SW_RST_I_MSK	include/ssv6200_aux.h	22;"	d
+MAC_SW_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	977;"	d
+MAC_SW_RST_MSK	include/ssv6200_aux.h	21;"	d
+MAC_SW_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	976;"	d
+MAC_SW_RST_SFT	include/ssv6200_aux.h	23;"	d
+MAC_SW_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	978;"	d
+MAC_SW_RST_SZ	include/ssv6200_aux.h	25;"	d
+MAC_SW_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	980;"	d
+MAC_TX_PEER_PS_LOCK_AUTOLOCK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7119;"	d
+MAC_TX_PEER_PS_LOCK_AUTOLOCK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7117;"	d
+MAC_TX_PEER_PS_LOCK_AUTOLOCK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7116;"	d
+MAC_TX_PEER_PS_LOCK_AUTOLOCK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7118;"	d
+MAC_TX_PEER_PS_LOCK_AUTOLOCK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7120;"	d
+MAC_TX_PEER_PS_LOCK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7114;"	d
+MAC_TX_PEER_PS_LOCK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7112;"	d
+MAC_TX_PEER_PS_LOCK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7111;"	d
+MAC_TX_PEER_PS_LOCK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7113;"	d
+MAC_TX_PEER_PS_LOCK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7115;"	d
+MAC_TX_PS_LOCK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7124;"	d
+MAC_TX_PS_LOCK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7122;"	d
+MAC_TX_PS_LOCK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7121;"	d
+MAC_TX_PS_LOCK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7123;"	d
+MAC_TX_PS_LOCK_STATUS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7129;"	d
+MAC_TX_PS_LOCK_STATUS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7127;"	d
+MAC_TX_PS_LOCK_STATUS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7126;"	d
+MAC_TX_PS_LOCK_STATUS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7128;"	d
+MAC_TX_PS_LOCK_STATUS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7130;"	d
+MAC_TX_PS_LOCK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7125;"	d
+MAC_TX_PS_UNLOCK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7109;"	d
+MAC_TX_PS_UNLOCK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7107;"	d
+MAC_TX_PS_UNLOCK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7106;"	d
+MAC_TX_PS_UNLOCK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7108;"	d
+MAC_TX_PS_UNLOCK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7110;"	d
+MANUAL_ALLOC_ID_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5309;"	d
+MANUAL_ALLOC_ID_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5307;"	d
+MANUAL_ALLOC_ID_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5306;"	d
+MANUAL_ALLOC_ID_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5308;"	d
+MANUAL_ALLOC_ID_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5310;"	d
+MANUAL_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2294;"	d
+MANUAL_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2292;"	d
+MANUAL_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2291;"	d
+MANUAL_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2293;"	d
+MANUAL_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2295;"	d
+MANUAL_HCI_ALLOC_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5299;"	d
+MANUAL_HCI_ALLOC_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5297;"	d
+MANUAL_HCI_ALLOC_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5296;"	d
+MANUAL_HCI_ALLOC_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5298;"	d
+MANUAL_HCI_ALLOC_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5300;"	d
+MANUAL_HCI_ALLOC_SIZE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5304;"	d
+MANUAL_HCI_ALLOC_SIZE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5302;"	d
+MANUAL_HCI_ALLOC_SIZE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5301;"	d
+MANUAL_HCI_ALLOC_SIZE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5303;"	d
+MANUAL_HCI_ALLOC_SIZE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5305;"	d
+MANUAL_IO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2279;"	d
+MANUAL_IO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2277;"	d
+MANUAL_IO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2276;"	d
+MANUAL_IO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2278;"	d
+MANUAL_IO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2280;"	d
+MANUAL_MODE_BUSY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4054;"	d
+MANUAL_MODE_BUSY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4052;"	d
+MANUAL_MODE_BUSY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4051;"	d
+MANUAL_MODE_BUSY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4053;"	d
+MANUAL_MODE_BUSY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4055;"	d
+MANUAL_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2289;"	d
+MANUAL_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2287;"	d
+MANUAL_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2286;"	d
+MANUAL_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2288;"	d
+MANUAL_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2290;"	d
+MANUAL_PU_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2284;"	d
+MANUAL_PU_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2282;"	d
+MANUAL_PU_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2281;"	d
+MANUAL_PU_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2283;"	d
+MANUAL_PU_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2285;"	d
+MANUAL_R_ADDR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4009;"	d
+MANUAL_R_ADDR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4007;"	d
+MANUAL_R_ADDR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4006;"	d
+MANUAL_R_ADDR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4008;"	d
+MANUAL_R_ADDR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4010;"	d
+MANUAL_R_LEN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4079;"	d
+MANUAL_R_LEN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4077;"	d
+MANUAL_R_LEN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4076;"	d
+MANUAL_R_LEN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4078;"	d
+MANUAL_R_LEN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4080;"	d
+MANUAL_T_ADDR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4004;"	d
+MANUAL_T_ADDR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4002;"	d
+MANUAL_T_ADDR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4001;"	d
+MANUAL_T_ADDR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4003;"	d
+MANUAL_T_ADDR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4005;"	d
+MANUAL_T_LEN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4074;"	d
+MANUAL_T_LEN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4072;"	d
+MANUAL_T_LEN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4071;"	d
+MANUAL_T_LEN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4073;"	d
+MANUAL_T_LEN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4075;"	d
+MANUFACTURER_ID_CABRIO_BASE	bridge/sdiobridge.h	47;"	d
+MANUFACTURER_SSV_CODE	bridge/sdiobridge.h	46;"	d
+MASK_ABNORMAL_CRC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6484;"	d
+MASK_ABNORMAL_CRC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6482;"	d
+MASK_ABNORMAL_CRC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6481;"	d
+MASK_ABNORMAL_CRC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6483;"	d
+MASK_ABNORMAL_CRC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6485;"	d
+MASK_RX_INT_HI	include/ssv6200_aux.h	3039;"	d
+MASK_RX_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2509;"	d
+MASK_RX_INT_I_MSK	include/ssv6200_aux.h	3037;"	d
+MASK_RX_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2507;"	d
+MASK_RX_INT_MSK	include/ssv6200_aux.h	3036;"	d
+MASK_RX_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2506;"	d
+MASK_RX_INT_SFT	include/ssv6200_aux.h	3038;"	d
+MASK_RX_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2508;"	d
+MASK_RX_INT_SZ	include/ssv6200_aux.h	3040;"	d
+MASK_RX_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2510;"	d
+MASK_SOC_SYSTEM_INT_HI	include/ssv6200_aux.h	3049;"	d
+MASK_SOC_SYSTEM_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2519;"	d
+MASK_SOC_SYSTEM_INT_I_MSK	include/ssv6200_aux.h	3047;"	d
+MASK_SOC_SYSTEM_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2517;"	d
+MASK_SOC_SYSTEM_INT_MSK	include/ssv6200_aux.h	3046;"	d
+MASK_SOC_SYSTEM_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2516;"	d
+MASK_SOC_SYSTEM_INT_SFT	include/ssv6200_aux.h	3048;"	d
+MASK_SOC_SYSTEM_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2518;"	d
+MASK_SOC_SYSTEM_INT_SZ	include/ssv6200_aux.h	3050;"	d
+MASK_SOC_SYSTEM_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2520;"	d
+MASK_TOP_HI	include/ssv6200_aux.h	4729;"	d
+MASK_TOP_I_MSK	include/ssv6200_aux.h	4727;"	d
+MASK_TOP_MSK	include/ssv6200_aux.h	4726;"	d
+MASK_TOP_SFT	include/ssv6200_aux.h	4728;"	d
+MASK_TOP_SZ	include/ssv6200_aux.h	4730;"	d
+MASK_TX_INT_HI	include/ssv6200_aux.h	3044;"	d
+MASK_TX_INT_I_MSK	include/ssv6200_aux.h	3042;"	d
+MASK_TX_INT_MSK	include/ssv6200_aux.h	3041;"	d
+MASK_TX_INT_SFT	include/ssv6200_aux.h	3043;"	d
+MASK_TX_INT_SZ	include/ssv6200_aux.h	3045;"	d
+MASK_TYPHOST_INT_MAP_02_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4329;"	d
+MASK_TYPHOST_INT_MAP_02_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4327;"	d
+MASK_TYPHOST_INT_MAP_02_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4326;"	d
+MASK_TYPHOST_INT_MAP_02_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4328;"	d
+MASK_TYPHOST_INT_MAP_02_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4330;"	d
+MASK_TYPHOST_INT_MAP_15_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4344;"	d
+MASK_TYPHOST_INT_MAP_15_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4342;"	d
+MASK_TYPHOST_INT_MAP_15_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4341;"	d
+MASK_TYPHOST_INT_MAP_15_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4343;"	d
+MASK_TYPHOST_INT_MAP_15_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4345;"	d
+MASK_TYPHOST_INT_MAP_31_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4359;"	d
+MASK_TYPHOST_INT_MAP_31_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4357;"	d
+MASK_TYPHOST_INT_MAP_31_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4356;"	d
+MASK_TYPHOST_INT_MAP_31_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4358;"	d
+MASK_TYPHOST_INT_MAP_31_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4360;"	d
+MASK_TYPHOST_INT_MAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4374;"	d
+MASK_TYPHOST_INT_MAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4372;"	d
+MASK_TYPHOST_INT_MAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4371;"	d
+MASK_TYPHOST_INT_MAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4373;"	d
+MASK_TYPHOST_INT_MAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4375;"	d
+MASK_TYPMCU_INT_MAP_02_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4394;"	d
+MASK_TYPMCU_INT_MAP_02_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4392;"	d
+MASK_TYPMCU_INT_MAP_02_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4391;"	d
+MASK_TYPMCU_INT_MAP_02_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4393;"	d
+MASK_TYPMCU_INT_MAP_02_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4395;"	d
+MASK_TYPMCU_INT_MAP_15_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4409;"	d
+MASK_TYPMCU_INT_MAP_15_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4407;"	d
+MASK_TYPMCU_INT_MAP_15_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4406;"	d
+MASK_TYPMCU_INT_MAP_15_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4408;"	d
+MASK_TYPMCU_INT_MAP_15_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4410;"	d
+MASK_TYPMCU_INT_MAP_31_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4424;"	d
+MASK_TYPMCU_INT_MAP_31_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4422;"	d
+MASK_TYPMCU_INT_MAP_31_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4421;"	d
+MASK_TYPMCU_INT_MAP_31_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4423;"	d
+MASK_TYPMCU_INT_MAP_31_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4425;"	d
+MASK_TYPMCU_INT_MAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4439;"	d
+MASK_TYPMCU_INT_MAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4437;"	d
+MASK_TYPMCU_INT_MAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4436;"	d
+MASK_TYPMCU_INT_MAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4438;"	d
+MASK_TYPMCU_INT_MAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4440;"	d
+MAXPROBES	smac/ssv_rc.h	29;"	d
+MAX_AGGR_NUM	include/ssv6xxx_common.h	49;"	d
+MAX_ALL_ALC_ID_CNT_HI	include/ssv6200_aux.h	12949;"	d
+MAX_ALL_ALC_ID_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34484;"	d
+MAX_ALL_ALC_ID_CNT_I_MSK	include/ssv6200_aux.h	12947;"	d
+MAX_ALL_ALC_ID_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34482;"	d
+MAX_ALL_ALC_ID_CNT_MSK	include/ssv6200_aux.h	12946;"	d
+MAX_ALL_ALC_ID_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34481;"	d
+MAX_ALL_ALC_ID_CNT_SFT	include/ssv6200_aux.h	12948;"	d
+MAX_ALL_ALC_ID_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34483;"	d
+MAX_ALL_ALC_ID_CNT_SZ	include/ssv6200_aux.h	12950;"	d
+MAX_ALL_ALC_ID_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34485;"	d
+MAX_ALL_ID_ALC_LEN_HI	include/ssv6200_aux.h	12964;"	d
+MAX_ALL_ID_ALC_LEN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34499;"	d
+MAX_ALL_ID_ALC_LEN_I_MSK	include/ssv6200_aux.h	12962;"	d
+MAX_ALL_ID_ALC_LEN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34497;"	d
+MAX_ALL_ID_ALC_LEN_MSK	include/ssv6200_aux.h	12961;"	d
+MAX_ALL_ID_ALC_LEN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34496;"	d
+MAX_ALL_ID_ALC_LEN_SFT	include/ssv6200_aux.h	12963;"	d
+MAX_ALL_ID_ALC_LEN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34498;"	d
+MAX_ALL_ID_ALC_LEN_SZ	include/ssv6200_aux.h	12965;"	d
+MAX_ALL_ID_ALC_LEN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34500;"	d
+MAX_BAND	smac/hal/ssv6006c/turismo_common.h	/^    MAX_BAND,$/;"	e	enum:__anon6
+MAX_BURST_READ_REG_AMOUNT	hwif/sdio/sdio_def.h	102;"	d
+MAX_BURST_WRITE_REG_AMOUNT	hwif/sdio/sdio_def.h	103;"	d
+MAX_CCI_LEVEL	smac/dev.c	5389;"	d	file:
+MAX_CCI_LEVEL	smac/dev.h	49;"	d
+MAX_CHARS_PER_LINE	ssvdevice/ssv_cmd.h	25;"	d
+MAX_CONCUR_AMPDU	smac/dev.h	90;"	d
+MAX_CRYPTO_Q_LEN	smac/dev.c	58;"	d	file:
+MAX_ERR_COUNT	hwif/sdio/sdio.c	55;"	d	file:
+MAX_FAIL_COUNT	include/hal.h	30;"	d
+MAX_FAIL_COUNT	smac/dev.c	210;"	d	file:
+MAX_FRAME_SIZE	include/ssv6xxx_common.h	22;"	d
+MAX_FRAME_SIZE_DMG	include/ssv6xxx_common.h	23;"	d
+MAX_FRM_SIZE	ssvdevice/ssv_cmd.c	1578;"	d	file:
+MAX_HCI_RX_AGGR_SIZE	include/ssv6xxx_common.h	25;"	d
+MAX_HCI_TX_TASK_SEND_FAIL	hci/ssv_hci.c	1755;"	d	file:
+MAX_HW_TXQ_INFO_LEN	smac/hal/ssv6006c/ssv6006C_mac.c	1120;"	d	file:
+MAX_IP_LEN	smartlink/qqlink-lib-mipsel/include/TXVoiceLink.h	30;"	d
+MAX_NR_RECVBUFF	hwif/usb/usb.h	64;"	d
+MAX_OFDM_RATE_GAIN_INDEX	smac/hal/ssv6006c/ssv6006_turismoC.c	2462;"	d	file:
+MAX_PADPD_TONE	smac/dev.h	568;"	d
+MAX_PADPD_TONE	smac/hal/ssv6006c/turismo_common.h	175;"	d
+MAX_PADPD_TONE	smac/hal/ssv6006c/turismo_common.h	283;"	d
+MAX_PAYLOAD	smartlink/ssv_smartlink.h	18;"	d
+MAX_PHY_SETTING_TABLE_SIZE	include/ssv6xxx_common.h	242;"	d
+MAX_PSWD_LEN	smartlink/qqlink-lib-mipsel/include/TXVoiceLink.h	29;"	d
+MAX_REG_RETRY_CNT	hwif/sdio/sdio.c	44;"	d	file:
+MAX_RETRY_COUNT	include/hal.h	31;"	d
+MAX_RETRY_COUNT	smac/dev.c	211;"	d	file:
+MAX_RETRY_SSV6XXX_ALLOC_BUF	hwif/usb/usb.c	44;"	d	file:
+MAX_RF_SETTING_TABLE_SIZE	include/ssv6xxx_common.h	243;"	d
+MAX_RX_ALC_ID_CNT_HI	include/ssv6200_aux.h	12959;"	d
+MAX_RX_ALC_ID_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34494;"	d
+MAX_RX_ALC_ID_CNT_I_MSK	include/ssv6200_aux.h	12957;"	d
+MAX_RX_ALC_ID_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34492;"	d
+MAX_RX_ALC_ID_CNT_MSK	include/ssv6200_aux.h	12956;"	d
+MAX_RX_ALC_ID_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34491;"	d
+MAX_RX_ALC_ID_CNT_SFT	include/ssv6200_aux.h	12958;"	d
+MAX_RX_ALC_ID_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34493;"	d
+MAX_RX_ALC_ID_CNT_SZ	include/ssv6200_aux.h	12960;"	d
+MAX_RX_ALC_ID_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34495;"	d
+MAX_RX_BURSTREAD_CNT	include/ssv6xxx_common.h	33;"	d
+MAX_RX_BURSTREAD_LENGTH	include/ssv6xxx_common.h	34;"	d
+MAX_RX_FRAME_SIZE	hwif/sdio/sdio.c	43;"	d	file:
+MAX_RX_IDLE_INTERVAL	smac/dev.h	178;"	d
+MAX_RX_ID_ALC_LEN_HI	include/ssv6200_aux.h	12974;"	d
+MAX_RX_ID_ALC_LEN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34509;"	d
+MAX_RX_ID_ALC_LEN_I_MSK	include/ssv6200_aux.h	12972;"	d
+MAX_RX_ID_ALC_LEN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34507;"	d
+MAX_RX_ID_ALC_LEN_MSK	include/ssv6200_aux.h	12971;"	d
+MAX_RX_ID_ALC_LEN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34506;"	d
+MAX_RX_ID_ALC_LEN_SFT	include/ssv6200_aux.h	12973;"	d
+MAX_RX_ID_ALC_LEN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34508;"	d
+MAX_RX_ID_ALC_LEN_SZ	include/ssv6200_aux.h	12975;"	d
+MAX_RX_ID_ALC_LEN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34510;"	d
+MAX_RX_PKT_RSVD	include/ssv6xxx_common.h	21;"	d
+MAX_SCATTER_ENTRIES_PER_REQ	hwif/sdio/sdio_def.h	75;"	d
+MAX_SMART_ICOMM	include/ssv6xxx_common.h	/^    MAX_SMART_ICOMM$/;"	e	enum:ssv_smart_icomm_cmd
+MAX_SMART_ICOMM	smartlink/ssv_smartlink.h	/^    MAX_SMART_ICOMM$/;"	e	enum:ssv_smart_icomm_cmd
+MAX_SSID_LEN	smartlink/qqlink-lib-mipsel/include/TXVoiceLink.h	28;"	d
+MAX_SSV6006_CMD_LPBK_SEC	smac/hal/ssv6006c/ssv6006_mac.h	/^    MAX_SSV6006_CMD_LPBK_SEC$/;"	e	enum:ssv6006_lpbk_sec
+MAX_SSV6006_CMD_LPBK_TYPE	smac/hal/ssv6006c/ssv6006_mac.h	/^    MAX_SSV6006_CMD_LPBK_TYPE$/;"	e	enum:ssv6006_lpbk_type
+MAX_SSV_WIRELESS_PATTERN	umac/ssv6xxx_netlink_core.c	36;"	d	file:
+MAX_TID	smac/dev.h	814;"	d
+MAX_TX_ALC_ID_CNT_HI	include/ssv6200_aux.h	12954;"	d
+MAX_TX_ALC_ID_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34489;"	d
+MAX_TX_ALC_ID_CNT_I_MSK	include/ssv6200_aux.h	12952;"	d
+MAX_TX_ALC_ID_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34487;"	d
+MAX_TX_ALC_ID_CNT_MSK	include/ssv6200_aux.h	12951;"	d
+MAX_TX_ALC_ID_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34486;"	d
+MAX_TX_ALC_ID_CNT_SFT	include/ssv6200_aux.h	12953;"	d
+MAX_TX_ALC_ID_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34488;"	d
+MAX_TX_ALC_ID_CNT_SZ	include/ssv6200_aux.h	12955;"	d
+MAX_TX_ALC_ID_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34490;"	d
+MAX_TX_ID_ALC_LEN_HI	include/ssv6200_aux.h	12969;"	d
+MAX_TX_ID_ALC_LEN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34504;"	d
+MAX_TX_ID_ALC_LEN_I_MSK	include/ssv6200_aux.h	12967;"	d
+MAX_TX_ID_ALC_LEN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34502;"	d
+MAX_TX_ID_ALC_LEN_MSK	include/ssv6200_aux.h	12966;"	d
+MAX_TX_ID_ALC_LEN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34501;"	d
+MAX_TX_ID_ALC_LEN_SFT	include/ssv6200_aux.h	12968;"	d
+MAX_TX_ID_ALC_LEN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34503;"	d
+MAX_TX_ID_ALC_LEN_SZ	include/ssv6200_aux.h	12970;"	d
+MAX_TX_ID_ALC_LEN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34505;"	d
+MAX_TX_Q_LEN	smac/dev.c	61;"	d	file:
+MBOX_CLK_EN_HI	include/ssv6200_aux.h	9024;"	d
+MBOX_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8779;"	d
+MBOX_CLK_EN_I_MSK	include/ssv6200_aux.h	9022;"	d
+MBOX_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8777;"	d
+MBOX_CLK_EN_MSK	include/ssv6200_aux.h	9021;"	d
+MBOX_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8776;"	d
+MBOX_CLK_EN_SFT	include/ssv6200_aux.h	9023;"	d
+MBOX_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8778;"	d
+MBOX_CLK_EN_SZ	include/ssv6200_aux.h	9025;"	d
+MBOX_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8780;"	d
+MBOX_CSR_CLK_EN_HI	include/ssv6200_aux.h	9119;"	d
+MBOX_CSR_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8874;"	d
+MBOX_CSR_CLK_EN_I_MSK	include/ssv6200_aux.h	9117;"	d
+MBOX_CSR_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8872;"	d
+MBOX_CSR_CLK_EN_MSK	include/ssv6200_aux.h	9116;"	d
+MBOX_CSR_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8871;"	d
+MBOX_CSR_CLK_EN_SFT	include/ssv6200_aux.h	9118;"	d
+MBOX_CSR_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8873;"	d
+MBOX_CSR_CLK_EN_SZ	include/ssv6200_aux.h	9120;"	d
+MBOX_CSR_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8875;"	d
+MBOX_CSR_RST_HI	include/ssv6200_aux.h	8979;"	d
+MBOX_CSR_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8734;"	d
+MBOX_CSR_RST_I_MSK	include/ssv6200_aux.h	8977;"	d
+MBOX_CSR_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8732;"	d
+MBOX_CSR_RST_MSK	include/ssv6200_aux.h	8976;"	d
+MBOX_CSR_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8731;"	d
+MBOX_CSR_RST_SFT	include/ssv6200_aux.h	8978;"	d
+MBOX_CSR_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8733;"	d
+MBOX_CSR_RST_SZ	include/ssv6200_aux.h	8980;"	d
+MBOX_CSR_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8735;"	d
+MBOX_ENG_CLK_EN_HI	include/ssv6200_aux.h	9079;"	d
+MBOX_ENG_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8834;"	d
+MBOX_ENG_CLK_EN_I_MSK	include/ssv6200_aux.h	9077;"	d
+MBOX_ENG_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8832;"	d
+MBOX_ENG_CLK_EN_MSK	include/ssv6200_aux.h	9076;"	d
+MBOX_ENG_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8831;"	d
+MBOX_ENG_CLK_EN_SFT	include/ssv6200_aux.h	9078;"	d
+MBOX_ENG_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8833;"	d
+MBOX_ENG_CLK_EN_SZ	include/ssv6200_aux.h	9080;"	d
+MBOX_ENG_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8835;"	d
+MBOX_ENG_RST_HI	include/ssv6200_aux.h	8904;"	d
+MBOX_ENG_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8659;"	d
+MBOX_ENG_RST_I_MSK	include/ssv6200_aux.h	8902;"	d
+MBOX_ENG_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8657;"	d
+MBOX_ENG_RST_MSK	include/ssv6200_aux.h	8901;"	d
+MBOX_ENG_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8656;"	d
+MBOX_ENG_RST_SFT	include/ssv6200_aux.h	8903;"	d
+MBOX_ENG_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8658;"	d
+MBOX_ENG_RST_SZ	include/ssv6200_aux.h	8905;"	d
+MBOX_ENG_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8660;"	d
+MBOX_INT_1_HI	include/ssv6200_aux.h	4964;"	d
+MBOX_INT_1_I_MSK	include/ssv6200_aux.h	4962;"	d
+MBOX_INT_1_MSK	include/ssv6200_aux.h	4961;"	d
+MBOX_INT_1_SD_HI	include/ssv6200_aux.h	5309;"	d
+MBOX_INT_1_SD_I_MSK	include/ssv6200_aux.h	5307;"	d
+MBOX_INT_1_SD_MSK	include/ssv6200_aux.h	5306;"	d
+MBOX_INT_1_SD_SFT	include/ssv6200_aux.h	5308;"	d
+MBOX_INT_1_SD_SZ	include/ssv6200_aux.h	5310;"	d
+MBOX_INT_1_SFT	include/ssv6200_aux.h	4963;"	d
+MBOX_INT_1_SZ	include/ssv6200_aux.h	4965;"	d
+MBOX_INT_2_HI	include/ssv6200_aux.h	4969;"	d
+MBOX_INT_2_I_MSK	include/ssv6200_aux.h	4967;"	d
+MBOX_INT_2_MSK	include/ssv6200_aux.h	4966;"	d
+MBOX_INT_2_SD_HI	include/ssv6200_aux.h	5314;"	d
+MBOX_INT_2_SD_I_MSK	include/ssv6200_aux.h	5312;"	d
+MBOX_INT_2_SD_MSK	include/ssv6200_aux.h	5311;"	d
+MBOX_INT_2_SD_SFT	include/ssv6200_aux.h	5313;"	d
+MBOX_INT_2_SD_SZ	include/ssv6200_aux.h	5315;"	d
+MBOX_INT_2_SFT	include/ssv6200_aux.h	4968;"	d
+MBOX_INT_2_SZ	include/ssv6200_aux.h	4970;"	d
+MBOX_INT_3_HI	include/ssv6200_aux.h	4974;"	d
+MBOX_INT_3_I_MSK	include/ssv6200_aux.h	4972;"	d
+MBOX_INT_3_MSK	include/ssv6200_aux.h	4971;"	d
+MBOX_INT_3_SD_HI	include/ssv6200_aux.h	5319;"	d
+MBOX_INT_3_SD_I_MSK	include/ssv6200_aux.h	5317;"	d
+MBOX_INT_3_SD_MSK	include/ssv6200_aux.h	5316;"	d
+MBOX_INT_3_SD_SFT	include/ssv6200_aux.h	5318;"	d
+MBOX_INT_3_SD_SZ	include/ssv6200_aux.h	5320;"	d
+MBOX_INT_3_SFT	include/ssv6200_aux.h	4973;"	d
+MBOX_INT_3_SZ	include/ssv6200_aux.h	4975;"	d
+MBOX_SW_RST_HI	include/ssv6200_aux.h	8849;"	d
+MBOX_SW_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8604;"	d
+MBOX_SW_RST_I_MSK	include/ssv6200_aux.h	8847;"	d
+MBOX_SW_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8602;"	d
+MBOX_SW_RST_MSK	include/ssv6200_aux.h	8846;"	d
+MBOX_SW_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8601;"	d
+MBOX_SW_RST_SFT	include/ssv6200_aux.h	8848;"	d
+MBOX_SW_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8603;"	d
+MBOX_SW_RST_SZ	include/ssv6200_aux.h	8850;"	d
+MBOX_SW_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8605;"	d
+MBRUN_HI	include/ssv6200_aux.h	374;"	d
+MBRUN_I_MSK	include/ssv6200_aux.h	372;"	d
+MBRUN_MSK	include/ssv6200_aux.h	371;"	d
+MBRUN_SFT	include/ssv6200_aux.h	373;"	d
+MBRUN_SZ	include/ssv6200_aux.h	375;"	d
+MB_DBG_CFG_ADDR_HI	include/ssv6200_aux.h	11754;"	d
+MB_DBG_CFG_ADDR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33409;"	d
+MB_DBG_CFG_ADDR_I_MSK	include/ssv6200_aux.h	11752;"	d
+MB_DBG_CFG_ADDR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33407;"	d
+MB_DBG_CFG_ADDR_MSK	include/ssv6200_aux.h	11751;"	d
+MB_DBG_CFG_ADDR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33406;"	d
+MB_DBG_CFG_ADDR_SFT	include/ssv6200_aux.h	11753;"	d
+MB_DBG_CFG_ADDR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33408;"	d
+MB_DBG_CFG_ADDR_SZ	include/ssv6200_aux.h	11755;"	d
+MB_DBG_CFG_ADDR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33410;"	d
+MB_DBG_CLR_HI	include/ssv6200_aux.h	11724;"	d
+MB_DBG_CLR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33379;"	d
+MB_DBG_CLR_I_MSK	include/ssv6200_aux.h	11722;"	d
+MB_DBG_CLR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33377;"	d
+MB_DBG_CLR_MSK	include/ssv6200_aux.h	11721;"	d
+MB_DBG_CLR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33376;"	d
+MB_DBG_CLR_SFT	include/ssv6200_aux.h	11723;"	d
+MB_DBG_CLR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33378;"	d
+MB_DBG_CLR_SZ	include/ssv6200_aux.h	11725;"	d
+MB_DBG_CLR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33380;"	d
+MB_DBG_COUNTER_EN_HI	include/ssv6200_aux.h	11734;"	d
+MB_DBG_COUNTER_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33389;"	d
+MB_DBG_COUNTER_EN_I_MSK	include/ssv6200_aux.h	11732;"	d
+MB_DBG_COUNTER_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33387;"	d
+MB_DBG_COUNTER_EN_MSK	include/ssv6200_aux.h	11731;"	d
+MB_DBG_COUNTER_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33386;"	d
+MB_DBG_COUNTER_EN_SFT	include/ssv6200_aux.h	11733;"	d
+MB_DBG_COUNTER_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33388;"	d
+MB_DBG_COUNTER_EN_SZ	include/ssv6200_aux.h	11735;"	d
+MB_DBG_COUNTER_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33390;"	d
+MB_DBG_EN_HI	include/ssv6200_aux.h	11739;"	d
+MB_DBG_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33394;"	d
+MB_DBG_EN_I_MSK	include/ssv6200_aux.h	11737;"	d
+MB_DBG_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33392;"	d
+MB_DBG_EN_MSK	include/ssv6200_aux.h	11736;"	d
+MB_DBG_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33391;"	d
+MB_DBG_EN_SFT	include/ssv6200_aux.h	11738;"	d
+MB_DBG_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33393;"	d
+MB_DBG_EN_SZ	include/ssv6200_aux.h	11740;"	d
+MB_DBG_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33395;"	d
+MB_DBG_LENGTH_HI	include/ssv6200_aux.h	11749;"	d
+MB_DBG_LENGTH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33404;"	d
+MB_DBG_LENGTH_I_MSK	include/ssv6200_aux.h	11747;"	d
+MB_DBG_LENGTH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33402;"	d
+MB_DBG_LENGTH_MSK	include/ssv6200_aux.h	11746;"	d
+MB_DBG_LENGTH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33401;"	d
+MB_DBG_LENGTH_SFT	include/ssv6200_aux.h	11748;"	d
+MB_DBG_LENGTH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33403;"	d
+MB_DBG_LENGTH_SZ	include/ssv6200_aux.h	11750;"	d
+MB_DBG_LENGTH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33405;"	d
+MB_DBG_RECORD_CNT_HI	include/ssv6200_aux.h	11744;"	d
+MB_DBG_RECORD_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33399;"	d
+MB_DBG_RECORD_CNT_I_MSK	include/ssv6200_aux.h	11742;"	d
+MB_DBG_RECORD_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33397;"	d
+MB_DBG_RECORD_CNT_MSK	include/ssv6200_aux.h	11741;"	d
+MB_DBG_RECORD_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33396;"	d
+MB_DBG_RECORD_CNT_SFT	include/ssv6200_aux.h	11743;"	d
+MB_DBG_RECORD_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33398;"	d
+MB_DBG_RECORD_CNT_SZ	include/ssv6200_aux.h	11745;"	d
+MB_DBG_RECORD_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33400;"	d
+MB_DBG_TIME_STEP_HI	include/ssv6200_aux.h	11714;"	d
+MB_DBG_TIME_STEP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33369;"	d
+MB_DBG_TIME_STEP_I_MSK	include/ssv6200_aux.h	11712;"	d
+MB_DBG_TIME_STEP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33367;"	d
+MB_DBG_TIME_STEP_MSK	include/ssv6200_aux.h	11711;"	d
+MB_DBG_TIME_STEP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33366;"	d
+MB_DBG_TIME_STEP_SFT	include/ssv6200_aux.h	11713;"	d
+MB_DBG_TIME_STEP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33368;"	d
+MB_DBG_TIME_STEP_SZ	include/ssv6200_aux.h	11715;"	d
+MB_DBG_TIME_STEP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33370;"	d
+MB_ERR_AUTO_HALT_EN_HI	include/ssv6200_aux.h	11699;"	d
+MB_ERR_AUTO_HALT_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33284;"	d
+MB_ERR_AUTO_HALT_EN_I_MSK	include/ssv6200_aux.h	11697;"	d
+MB_ERR_AUTO_HALT_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33282;"	d
+MB_ERR_AUTO_HALT_EN_MSK	include/ssv6200_aux.h	11696;"	d
+MB_ERR_AUTO_HALT_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33281;"	d
+MB_ERR_AUTO_HALT_EN_SFT	include/ssv6200_aux.h	11698;"	d
+MB_ERR_AUTO_HALT_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33283;"	d
+MB_ERR_AUTO_HALT_EN_SZ	include/ssv6200_aux.h	11700;"	d
+MB_ERR_AUTO_HALT_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33285;"	d
+MB_EXCEPT_CASE_HI	include/ssv6200_aux.h	11709;"	d
+MB_EXCEPT_CASE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33364;"	d
+MB_EXCEPT_CASE_I_MSK	include/ssv6200_aux.h	11707;"	d
+MB_EXCEPT_CASE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33362;"	d
+MB_EXCEPT_CASE_MSK	include/ssv6200_aux.h	11706;"	d
+MB_EXCEPT_CASE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33361;"	d
+MB_EXCEPT_CASE_SFT	include/ssv6200_aux.h	11708;"	d
+MB_EXCEPT_CASE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33363;"	d
+MB_EXCEPT_CASE_SZ	include/ssv6200_aux.h	11710;"	d
+MB_EXCEPT_CASE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33365;"	d
+MB_EXCEPT_CLR_HI	include/ssv6200_aux.h	11704;"	d
+MB_EXCEPT_CLR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33289;"	d
+MB_EXCEPT_CLR_I_MSK	include/ssv6200_aux.h	11702;"	d
+MB_EXCEPT_CLR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33287;"	d
+MB_EXCEPT_CLR_MSK	include/ssv6200_aux.h	11701;"	d
+MB_EXCEPT_CLR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33286;"	d
+MB_EXCEPT_CLR_SFT	include/ssv6200_aux.h	11703;"	d
+MB_EXCEPT_CLR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33288;"	d
+MB_EXCEPT_CLR_SZ	include/ssv6200_aux.h	11705;"	d
+MB_EXCEPT_CLR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33290;"	d
+MB_IDTBL_127_96_HI	include/ssv6200_aux.h	18039;"	d
+MB_IDTBL_127_96_I_MSK	include/ssv6200_aux.h	18037;"	d
+MB_IDTBL_127_96_MSK	include/ssv6200_aux.h	18036;"	d
+MB_IDTBL_127_96_SFT	include/ssv6200_aux.h	18038;"	d
+MB_IDTBL_127_96_SZ	include/ssv6200_aux.h	18040;"	d
+MB_IDTBL_31_0_HI	include/ssv6200_aux.h	18024;"	d
+MB_IDTBL_31_0_I_MSK	include/ssv6200_aux.h	18022;"	d
+MB_IDTBL_31_0_MSK	include/ssv6200_aux.h	18021;"	d
+MB_IDTBL_31_0_SFT	include/ssv6200_aux.h	18023;"	d
+MB_IDTBL_31_0_SZ	include/ssv6200_aux.h	18025;"	d
+MB_IDTBL_63_32_HI	include/ssv6200_aux.h	18029;"	d
+MB_IDTBL_63_32_I_MSK	include/ssv6200_aux.h	18027;"	d
+MB_IDTBL_63_32_MSK	include/ssv6200_aux.h	18026;"	d
+MB_IDTBL_63_32_SFT	include/ssv6200_aux.h	18028;"	d
+MB_IDTBL_63_32_SZ	include/ssv6200_aux.h	18030;"	d
+MB_IDTBL_95_64_HI	include/ssv6200_aux.h	18034;"	d
+MB_IDTBL_95_64_I_MSK	include/ssv6200_aux.h	18032;"	d
+MB_IDTBL_95_64_MSK	include/ssv6200_aux.h	18031;"	d
+MB_IDTBL_95_64_SFT	include/ssv6200_aux.h	18033;"	d
+MB_IDTBL_95_64_SZ	include/ssv6200_aux.h	18035;"	d
+MB_LOW_THOLD_EN_HI	include/ssv6200_aux.h	12244;"	d
+MB_LOW_THOLD_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33834;"	d
+MB_LOW_THOLD_EN_I_MSK	include/ssv6200_aux.h	12242;"	d
+MB_LOW_THOLD_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33832;"	d
+MB_LOW_THOLD_EN_MSK	include/ssv6200_aux.h	12241;"	d
+MB_LOW_THOLD_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33831;"	d
+MB_LOW_THOLD_EN_SFT	include/ssv6200_aux.h	12243;"	d
+MB_LOW_THOLD_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33833;"	d
+MB_LOW_THOLD_EN_SZ	include/ssv6200_aux.h	12245;"	d
+MB_LOW_THOLD_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33835;"	d
+MB_OUT_QUEUE_EN_HI	include/ssv6200_aux.h	11919;"	d
+MB_OUT_QUEUE_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33574;"	d
+MB_OUT_QUEUE_EN_I_MSK	include/ssv6200_aux.h	11917;"	d
+MB_OUT_QUEUE_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33572;"	d
+MB_OUT_QUEUE_EN_MSK	include/ssv6200_aux.h	11916;"	d
+MB_OUT_QUEUE_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33571;"	d
+MB_OUT_QUEUE_EN_SFT	include/ssv6200_aux.h	11918;"	d
+MB_OUT_QUEUE_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33573;"	d
+MB_OUT_QUEUE_EN_SZ	include/ssv6200_aux.h	11920;"	d
+MB_OUT_QUEUE_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33575;"	d
+MB_REG_BANK_SIZE	include/ssv6200_reg.h	109;"	d
+MB_REG_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	134;"	d
+MB_REG_BASE	include/ssv6200_reg.h	60;"	d
+MB_REG_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	73;"	d
+MB_REQ_DUR_HI	include/ssv6200_aux.h	7769;"	d
+MB_REQ_DUR_I_MSK	include/ssv6200_aux.h	7767;"	d
+MB_REQ_DUR_MSK	include/ssv6200_aux.h	7766;"	d
+MB_REQ_DUR_SFT	include/ssv6200_aux.h	7768;"	d
+MB_REQ_DUR_SZ	include/ssv6200_aux.h	7770;"	d
+MCH_SW_RST_N_HI	include/ssv6200_aux.h	17709;"	d
+MCH_SW_RST_N_I_MSK	include/ssv6200_aux.h	17707;"	d
+MCH_SW_RST_N_MSK	include/ssv6200_aux.h	17706;"	d
+MCH_SW_RST_N_SFT	include/ssv6200_aux.h	17708;"	d
+MCH_SW_RST_N_SZ	include/ssv6200_aux.h	17710;"	d
+MCS_DURATION	smac/ssv_ht_rc.c	35;"	d	file:
+MCS_DURATION	smac/ssv_rc_minstrel_ht.c	38;"	d	file:
+MCS_GROUP	smac/ssv_ht_rc.c	36;"	d	file:
+MCS_GROUP	smac/ssv_rc_minstrel_ht.c	43;"	d	file:
+MCS_GROUP_RATES	smac/ssv_rc_common.h	19;"	d
+MCS_GROUP_RATES	smac/ssv_rc_minstrel_ht.h	24;"	d
+MCS_HI	include/ssv6200_aux.h	6459;"	d
+MCS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5704;"	d
+MCS_I_MSK	include/ssv6200_aux.h	6457;"	d
+MCS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5702;"	d
+MCS_MSK	include/ssv6200_aux.h	6456;"	d
+MCS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5701;"	d
+MCS_NBITS	smac/ssv_ht_rc.c	28;"	d	file:
+MCS_NBITS	smac/ssv_rc_minstrel_ht.c	31;"	d	file:
+MCS_NSYMS	smac/ssv_ht_rc.c	29;"	d	file:
+MCS_NSYMS	smac/ssv_rc_minstrel_ht.c	32;"	d	file:
+MCS_SFT	include/ssv6200_aux.h	6458;"	d
+MCS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5703;"	d
+MCS_SYMBOL_TIME	smac/ssv_ht_rc.c	30;"	d	file:
+MCS_SYMBOL_TIME	smac/ssv_rc_minstrel_ht.c	33;"	d	file:
+MCS_SZ	include/ssv6200_aux.h	6460;"	d
+MCS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5705;"	d
+MCU_ALC_READY_HI	include/ssv6200_aux.h	12579;"	d
+MCU_ALC_READY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34104;"	d
+MCU_ALC_READY_I_MSK	include/ssv6200_aux.h	12577;"	d
+MCU_ALC_READY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34102;"	d
+MCU_ALC_READY_MSK	include/ssv6200_aux.h	12576;"	d
+MCU_ALC_READY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34101;"	d
+MCU_ALC_READY_SFT	include/ssv6200_aux.h	12578;"	d
+MCU_ALC_READY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34103;"	d
+MCU_ALC_READY_SZ	include/ssv6200_aux.h	12580;"	d
+MCU_ALC_READY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34105;"	d
+MCU_CLK_EN_HI	include/ssv6200_aux.h	199;"	d
+MCU_CLK_EN_I_MSK	include/ssv6200_aux.h	197;"	d
+MCU_CLK_EN_MSK	include/ssv6200_aux.h	196;"	d
+MCU_CLK_EN_SFT	include/ssv6200_aux.h	198;"	d
+MCU_CLK_EN_SZ	include/ssv6200_aux.h	200;"	d
+MCU_DBG_DATA_HI	include/ssv6200_aux.h	319;"	d
+MCU_DBG_DATA_I_MSK	include/ssv6200_aux.h	317;"	d
+MCU_DBG_DATA_MSK	include/ssv6200_aux.h	316;"	d
+MCU_DBG_DATA_SFT	include/ssv6200_aux.h	318;"	d
+MCU_DBG_DATA_SZ	include/ssv6200_aux.h	320;"	d
+MCU_DBG_SEL_HI	include/ssv6200_aux.h	304;"	d
+MCU_DBG_SEL_I_MSK	include/ssv6200_aux.h	302;"	d
+MCU_DBG_SEL_MSK	include/ssv6200_aux.h	301;"	d
+MCU_DBG_SEL_SFT	include/ssv6200_aux.h	303;"	d
+MCU_DBG_SEL_SZ	include/ssv6200_aux.h	305;"	d
+MCU_ENABLE_HI	include/ssv6200_aux.h	19;"	d
+MCU_ENABLE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	974;"	d
+MCU_ENABLE_I_MSK	include/ssv6200_aux.h	17;"	d
+MCU_ENABLE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	972;"	d
+MCU_ENABLE_MSK	include/ssv6200_aux.h	16;"	d
+MCU_ENABLE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	971;"	d
+MCU_ENABLE_SFT	include/ssv6200_aux.h	18;"	d
+MCU_ENABLE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	973;"	d
+MCU_ENABLE_SZ	include/ssv6200_aux.h	20;"	d
+MCU_ENABLE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	975;"	d
+MCU_NOTIFY_HOST_CFG	hwif/sdio/sdio_def.h	38;"	d
+MCU_PKTID_HI	include/ssv6200_aux.h	12479;"	d
+MCU_PKTID_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34004;"	d
+MCU_PKTID_I_MSK	include/ssv6200_aux.h	12477;"	d
+MCU_PKTID_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34002;"	d
+MCU_PKTID_MSK	include/ssv6200_aux.h	12476;"	d
+MCU_PKTID_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34001;"	d
+MCU_PKTID_SFT	include/ssv6200_aux.h	12478;"	d
+MCU_PKTID_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34003;"	d
+MCU_PKTID_SZ	include/ssv6200_aux.h	12480;"	d
+MCU_PKTID_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34005;"	d
+MCU_STOP_ANYTIME_HI	include/ssv6200_aux.h	314;"	d
+MCU_STOP_ANYTIME_I_MSK	include/ssv6200_aux.h	312;"	d
+MCU_STOP_ANYTIME_MSK	include/ssv6200_aux.h	311;"	d
+MCU_STOP_ANYTIME_SFT	include/ssv6200_aux.h	313;"	d
+MCU_STOP_ANYTIME_SZ	include/ssv6200_aux.h	315;"	d
+MCU_STOP_NOGRANT_HI	include/ssv6200_aux.h	309;"	d
+MCU_STOP_NOGRANT_I_MSK	include/ssv6200_aux.h	307;"	d
+MCU_STOP_NOGRANT_MSK	include/ssv6200_aux.h	306;"	d
+MCU_STOP_NOGRANT_SFT	include/ssv6200_aux.h	308;"	d
+MCU_STOP_NOGRANT_SZ	include/ssv6200_aux.h	310;"	d
+MCU_SW_RST_HI	include/ssv6200_aux.h	29;"	d
+MCU_SW_RST_I_MSK	include/ssv6200_aux.h	27;"	d
+MCU_SW_RST_MSK	include/ssv6200_aux.h	26;"	d
+MCU_SW_RST_SFT	include/ssv6200_aux.h	28;"	d
+MCU_SW_RST_SZ	include/ssv6200_aux.h	30;"	d
+MCU_TO_SDIO_INFO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2764;"	d
+MCU_TO_SDIO_INFO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2762;"	d
+MCU_TO_SDIO_INFO_MASK_HI	include/ssv6200_aux.h	3354;"	d
+MCU_TO_SDIO_INFO_MASK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2664;"	d
+MCU_TO_SDIO_INFO_MASK_I_MSK	include/ssv6200_aux.h	3352;"	d
+MCU_TO_SDIO_INFO_MASK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2662;"	d
+MCU_TO_SDIO_INFO_MASK_MSK	include/ssv6200_aux.h	3351;"	d
+MCU_TO_SDIO_INFO_MASK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2661;"	d
+MCU_TO_SDIO_INFO_MASK_SFT	include/ssv6200_aux.h	3353;"	d
+MCU_TO_SDIO_INFO_MASK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2663;"	d
+MCU_TO_SDIO_INFO_MASK_SZ	include/ssv6200_aux.h	3355;"	d
+MCU_TO_SDIO_INFO_MASK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2665;"	d
+MCU_TO_SDIO_INFO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2761;"	d
+MCU_TO_SDIO_INFO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2763;"	d
+MCU_TO_SDIO_INFO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2765;"	d
+MCU_WDOG_ENA_HI	include/ssv6200_aux.h	839;"	d
+MCU_WDOG_ENA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2079;"	d
+MCU_WDOG_ENA_I_MSK	include/ssv6200_aux.h	837;"	d
+MCU_WDOG_ENA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2077;"	d
+MCU_WDOG_ENA_MSK	include/ssv6200_aux.h	836;"	d
+MCU_WDOG_ENA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2076;"	d
+MCU_WDOG_ENA_SFT	include/ssv6200_aux.h	838;"	d
+MCU_WDOG_ENA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2078;"	d
+MCU_WDOG_ENA_SZ	include/ssv6200_aux.h	840;"	d
+MCU_WDOG_ENA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2080;"	d
+MCU_WDT_INT_CNT_OFS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2069;"	d
+MCU_WDT_INT_CNT_OFS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2067;"	d
+MCU_WDT_INT_CNT_OFS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2066;"	d
+MCU_WDT_INT_CNT_OFS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2068;"	d
+MCU_WDT_INT_CNT_OFS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2070;"	d
+MCU_WDT_REG_BANK_SIZE	include/ssv6200_reg.h	75;"	d
+MCU_WDT_REG_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	92;"	d
+MCU_WDT_REG_BASE	include/ssv6200_reg.h	26;"	d
+MCU_WDT_REG_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	31;"	d
+MCU_WDT_STATUS_HI	include/ssv6200_aux.h	834;"	d
+MCU_WDT_STATUS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2074;"	d
+MCU_WDT_STATUS_I_MSK	include/ssv6200_aux.h	832;"	d
+MCU_WDT_STATUS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2072;"	d
+MCU_WDT_STATUS_MSK	include/ssv6200_aux.h	831;"	d
+MCU_WDT_STATUS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2071;"	d
+MCU_WDT_STATUS_SFT	include/ssv6200_aux.h	833;"	d
+MCU_WDT_STATUS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2073;"	d
+MCU_WDT_STATUS_SZ	include/ssv6200_aux.h	835;"	d
+MCU_WDT_STATUS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2075;"	d
+MCU_WDT_TIME_CNT_HI	include/ssv6200_aux.h	829;"	d
+MCU_WDT_TIME_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2064;"	d
+MCU_WDT_TIME_CNT_I_MSK	include/ssv6200_aux.h	827;"	d
+MCU_WDT_TIME_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2062;"	d
+MCU_WDT_TIME_CNT_MSK	include/ssv6200_aux.h	826;"	d
+MCU_WDT_TIME_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2061;"	d
+MCU_WDT_TIME_CNT_SFT	include/ssv6200_aux.h	828;"	d
+MCU_WDT_TIME_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2063;"	d
+MCU_WDT_TIME_CNT_SZ	include/ssv6200_aux.h	830;"	d
+MCU_WDT_TIME_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2065;"	d
+MDELAY	smac/hal/ssv6006c/ssv6006_priv.h	26;"	d
+MDELAY	smac/hal/ssv6006c/turismo_common.h	307;"	d
+MDM_STS_IE_HI	include/ssv6200_aux.h	4279;"	d
+MDM_STS_IE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3384;"	d
+MDM_STS_IE_I_MSK	include/ssv6200_aux.h	4277;"	d
+MDM_STS_IE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3382;"	d
+MDM_STS_IE_MSK	include/ssv6200_aux.h	4276;"	d
+MDM_STS_IE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3381;"	d
+MDM_STS_IE_SFT	include/ssv6200_aux.h	4278;"	d
+MDM_STS_IE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3383;"	d
+MDM_STS_IE_SZ	include/ssv6200_aux.h	4280;"	d
+MDM_STS_IE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3385;"	d
+MEM_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4039;"	d
+MEM_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4037;"	d
+MEM_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4036;"	d
+MEM_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4038;"	d
+MEM_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4040;"	d
+ME_CCMP	smac/drv_comm.h	40;"	d
+ME_NONE	smac/drv_comm.h	36;"	d
+ME_SMS4	smac/drv_comm.h	41;"	d
+ME_TKIP	smac/drv_comm.h	39;"	d
+ME_WEP104	smac/drv_comm.h	38;"	d
+ME_WEP40	smac/drv_comm.h	37;"	d
+MIB_AMPDU_HI	include/ssv6200_aux.h	7389;"	d
+MIB_AMPDU_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6544;"	d
+MIB_AMPDU_I_MSK	include/ssv6200_aux.h	7387;"	d
+MIB_AMPDU_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6542;"	d
+MIB_AMPDU_MSK	include/ssv6200_aux.h	7386;"	d
+MIB_AMPDU_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6541;"	d
+MIB_AMPDU_SFT	include/ssv6200_aux.h	7388;"	d
+MIB_AMPDU_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6543;"	d
+MIB_AMPDU_SZ	include/ssv6200_aux.h	7390;"	d
+MIB_AMPDU_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6545;"	d
+MIB_CLK_EN_HI	include/ssv6200_aux.h	9039;"	d
+MIB_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8794;"	d
+MIB_CLK_EN_I_MSK	include/ssv6200_aux.h	9037;"	d
+MIB_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8792;"	d
+MIB_CLK_EN_MSK	include/ssv6200_aux.h	9036;"	d
+MIB_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8791;"	d
+MIB_CLK_EN_SFT	include/ssv6200_aux.h	9038;"	d
+MIB_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8793;"	d
+MIB_CLK_EN_SZ	include/ssv6200_aux.h	9040;"	d
+MIB_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8795;"	d
+MIB_DELIMITER_HI	include/ssv6200_aux.h	7399;"	d
+MIB_DELIMITER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6554;"	d
+MIB_DELIMITER_I_MSK	include/ssv6200_aux.h	7397;"	d
+MIB_DELIMITER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6552;"	d
+MIB_DELIMITER_MSK	include/ssv6200_aux.h	7396;"	d
+MIB_DELIMITER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6551;"	d
+MIB_DELIMITER_SFT	include/ssv6200_aux.h	7398;"	d
+MIB_DELIMITER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6553;"	d
+MIB_DELIMITER_SZ	include/ssv6200_aux.h	7400;"	d
+MIB_DELIMITER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6555;"	d
+MIB_LEN_FAIL_HI	include/ssv6200_aux.h	7239;"	d
+MIB_LEN_FAIL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6414;"	d
+MIB_LEN_FAIL_I_MSK	include/ssv6200_aux.h	7237;"	d
+MIB_LEN_FAIL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6412;"	d
+MIB_LEN_FAIL_MSK	include/ssv6200_aux.h	7236;"	d
+MIB_LEN_FAIL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6411;"	d
+MIB_LEN_FAIL_SFT	include/ssv6200_aux.h	7238;"	d
+MIB_LEN_FAIL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6413;"	d
+MIB_LEN_FAIL_SZ	include/ssv6200_aux.h	7240;"	d
+MIB_LEN_FAIL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6415;"	d
+MIB_REG_BANK_SIZE	include/ssv6200_reg.h	107;"	d
+MIB_REG_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	128;"	d
+MIB_REG_BASE	include/ssv6200_reg.h	58;"	d
+MIB_REG_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	67;"	d
+MIC_CLK_EN_HI	include/ssv6200_aux.h	9034;"	d
+MIC_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8789;"	d
+MIC_CLK_EN_I_MSK	include/ssv6200_aux.h	9032;"	d
+MIC_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8787;"	d
+MIC_CLK_EN_MSK	include/ssv6200_aux.h	9031;"	d
+MIC_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8786;"	d
+MIC_CLK_EN_SFT	include/ssv6200_aux.h	9033;"	d
+MIC_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8788;"	d
+MIC_CLK_EN_SZ	include/ssv6200_aux.h	9035;"	d
+MIC_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8790;"	d
+MIC_ENG_CLK_EN_HI	include/ssv6200_aux.h	9089;"	d
+MIC_ENG_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8844;"	d
+MIC_ENG_CLK_EN_I_MSK	include/ssv6200_aux.h	9087;"	d
+MIC_ENG_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8842;"	d
+MIC_ENG_CLK_EN_MSK	include/ssv6200_aux.h	9086;"	d
+MIC_ENG_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8841;"	d
+MIC_ENG_CLK_EN_SFT	include/ssv6200_aux.h	9088;"	d
+MIC_ENG_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8843;"	d
+MIC_ENG_CLK_EN_SZ	include/ssv6200_aux.h	9090;"	d
+MIC_ENG_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8845;"	d
+MIC_ENG_RST_HI	include/ssv6200_aux.h	8914;"	d
+MIC_ENG_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8669;"	d
+MIC_ENG_RST_I_MSK	include/ssv6200_aux.h	8912;"	d
+MIC_ENG_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8667;"	d
+MIC_ENG_RST_MSK	include/ssv6200_aux.h	8911;"	d
+MIC_ENG_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8666;"	d
+MIC_ENG_RST_SFT	include/ssv6200_aux.h	8913;"	d
+MIC_ENG_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8668;"	d
+MIC_ENG_RST_SZ	include/ssv6200_aux.h	8915;"	d
+MIC_ENG_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8670;"	d
+MIC_SW_RST_HI	include/ssv6200_aux.h	8859;"	d
+MIC_SW_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8614;"	d
+MIC_SW_RST_I_MSK	include/ssv6200_aux.h	8857;"	d
+MIC_SW_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8612;"	d
+MIC_SW_RST_MSK	include/ssv6200_aux.h	8856;"	d
+MIC_SW_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8611;"	d
+MIC_SW_RST_SFT	include/ssv6200_aux.h	8858;"	d
+MIC_SW_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8613;"	d
+MIC_SW_RST_SZ	include/ssv6200_aux.h	8860;"	d
+MIC_SW_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8615;"	d
+MINSTREL_FRAC	smac/ssv_ht_rc.h	20;"	d
+MINSTREL_FRAC	smac/ssv_rc_minstrel_ht.h	22;"	d
+MINSTREL_MAX_STREAMS	smac/ssv_rc_minstrel_ht.h	19;"	d
+MINSTREL_SCALE	smac/ssv_ht_rc.h	19;"	d
+MINSTREL_SCALE	smac/ssv_rc_minstrel_ht.h	21;"	d
+MINSTREL_STREAM_GROUPS	smac/ssv_rc_minstrel_ht.h	20;"	d
+MINSTREL_TRUNC	smac/ssv_ht_rc.h	21;"	d
+MINSTREL_TRUNC	smac/ssv_rc_minstrel_ht.h	23;"	d
+MIN_NR_RECVBUFF	hwif/usb/usb.h	65;"	d
+MISC_PKT_CLS_MIB_EN_HI	include/ssv6200_aux.h	9414;"	d
+MISC_PKT_CLS_MIB_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9249;"	d
+MISC_PKT_CLS_MIB_EN_I_MSK	include/ssv6200_aux.h	9412;"	d
+MISC_PKT_CLS_MIB_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9247;"	d
+MISC_PKT_CLS_MIB_EN_MSK	include/ssv6200_aux.h	9411;"	d
+MISC_PKT_CLS_MIB_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9246;"	d
+MISC_PKT_CLS_MIB_EN_SFT	include/ssv6200_aux.h	9413;"	d
+MISC_PKT_CLS_MIB_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9248;"	d
+MISC_PKT_CLS_MIB_EN_SZ	include/ssv6200_aux.h	9415;"	d
+MISC_PKT_CLS_MIB_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9250;"	d
+MISC_PKT_CLS_ONGOING_HI	include/ssv6200_aux.h	9419;"	d
+MISC_PKT_CLS_ONGOING_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9254;"	d
+MISC_PKT_CLS_ONGOING_I_MSK	include/ssv6200_aux.h	9417;"	d
+MISC_PKT_CLS_ONGOING_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9252;"	d
+MISC_PKT_CLS_ONGOING_MSK	include/ssv6200_aux.h	9416;"	d
+MISC_PKT_CLS_ONGOING_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9251;"	d
+MISC_PKT_CLS_ONGOING_SFT	include/ssv6200_aux.h	9418;"	d
+MISC_PKT_CLS_ONGOING_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9253;"	d
+MISC_PKT_CLS_ONGOING_SZ	include/ssv6200_aux.h	9420;"	d
+MISC_PKT_CLS_ONGOING_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9255;"	d
+MK_LEN	smac/wapi_sms4.c	28;"	d	file:
+MMU_ALC_ERR_HI	include/ssv6200_aux.h	4949;"	d
+MMU_ALC_ERR_I_MSK	include/ssv6200_aux.h	4947;"	d
+MMU_ALC_ERR_MSK	include/ssv6200_aux.h	4946;"	d
+MMU_ALC_ERR_SD_HI	include/ssv6200_aux.h	5294;"	d
+MMU_ALC_ERR_SD_I_MSK	include/ssv6200_aux.h	5292;"	d
+MMU_ALC_ERR_SD_MSK	include/ssv6200_aux.h	5291;"	d
+MMU_ALC_ERR_SD_SFT	include/ssv6200_aux.h	5293;"	d
+MMU_ALC_ERR_SD_SZ	include/ssv6200_aux.h	5295;"	d
+MMU_ALC_ERR_SFT	include/ssv6200_aux.h	4948;"	d
+MMU_ALC_ERR_SZ	include/ssv6200_aux.h	4950;"	d
+MMU_CLK_EN_HI	include/ssv6200_aux.h	9014;"	d
+MMU_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8769;"	d
+MMU_CLK_EN_I_MSK	include/ssv6200_aux.h	9012;"	d
+MMU_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8767;"	d
+MMU_CLK_EN_MSK	include/ssv6200_aux.h	9011;"	d
+MMU_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8766;"	d
+MMU_CLK_EN_SFT	include/ssv6200_aux.h	9013;"	d
+MMU_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8768;"	d
+MMU_CLK_EN_SZ	include/ssv6200_aux.h	9015;"	d
+MMU_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8770;"	d
+MMU_REG_BANK_SIZE	include/ssv6200_reg.h	113;"	d
+MMU_REG_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	136;"	d
+MMU_REG_BASE	include/ssv6200_reg.h	64;"	d
+MMU_REG_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	75;"	d
+MMU_RLS_ERR_HI	include/ssv6200_aux.h	4954;"	d
+MMU_RLS_ERR_I_MSK	include/ssv6200_aux.h	4952;"	d
+MMU_RLS_ERR_MSK	include/ssv6200_aux.h	4951;"	d
+MMU_RLS_ERR_SD_HI	include/ssv6200_aux.h	5299;"	d
+MMU_RLS_ERR_SD_I_MSK	include/ssv6200_aux.h	5297;"	d
+MMU_RLS_ERR_SD_MSK	include/ssv6200_aux.h	5296;"	d
+MMU_RLS_ERR_SD_SFT	include/ssv6200_aux.h	5298;"	d
+MMU_RLS_ERR_SD_SZ	include/ssv6200_aux.h	5300;"	d
+MMU_RLS_ERR_SFT	include/ssv6200_aux.h	4953;"	d
+MMU_RLS_ERR_SZ	include/ssv6200_aux.h	4955;"	d
+MMU_SHARE_MCU_HI	include/ssv6200_aux.h	17729;"	d
+MMU_SHARE_MCU_I_MSK	include/ssv6200_aux.h	17727;"	d
+MMU_SHARE_MCU_MSK	include/ssv6200_aux.h	17726;"	d
+MMU_SHARE_MCU_SFT	include/ssv6200_aux.h	17728;"	d
+MMU_SHARE_MCU_SZ	include/ssv6200_aux.h	17730;"	d
+MMU_SW_RST_HI	include/ssv6200_aux.h	8839;"	d
+MMU_SW_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8594;"	d
+MMU_SW_RST_I_MSK	include/ssv6200_aux.h	8837;"	d
+MMU_SW_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8592;"	d
+MMU_SW_RST_MSK	include/ssv6200_aux.h	8836;"	d
+MMU_SW_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8591;"	d
+MMU_SW_RST_SFT	include/ssv6200_aux.h	8838;"	d
+MMU_SW_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8593;"	d
+MMU_SW_RST_SZ	include/ssv6200_aux.h	8840;"	d
+MMU_SW_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8595;"	d
+MMU_VER_HI	include/ssv6200_aux.h	17724;"	d
+MMU_VER_I_MSK	include/ssv6200_aux.h	17722;"	d
+MMU_VER_MSK	include/ssv6200_aux.h	17721;"	d
+MMU_VER_SFT	include/ssv6200_aux.h	17723;"	d
+MMU_VER_SZ	include/ssv6200_aux.h	17725;"	d
+MODEN_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3669;"	d
+MODEN_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3667;"	d
+MODEN_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3666;"	d
+MODEN_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3668;"	d
+MODEN_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3670;"	d
+MODE_BT_RX	smac/hal/ssv6006c/turismo_common.h	/^    MODE_BT_RX,$/;"	e	enum:__anon5
+MODE_BT_TX	smac/hal/ssv6006c/turismo_common.h	/^    MODE_BT_TX,$/;"	e	enum:__anon5
+MODE_CALIBRATION	smac/hal/ssv6006c/turismo_common.h	/^    MODE_CALIBRATION,$/;"	e	enum:__anon5
+MODE_REG_IN_HI	include/ssv6200_aux.h	399;"	d
+MODE_REG_IN_I_MSK	include/ssv6200_aux.h	397;"	d
+MODE_REG_IN_MMU_HI	include/ssv6200_aux.h	554;"	d
+MODE_REG_IN_MMU_I_MSK	include/ssv6200_aux.h	552;"	d
+MODE_REG_IN_MMU_MSK	include/ssv6200_aux.h	551;"	d
+MODE_REG_IN_MMU_SFT	include/ssv6200_aux.h	553;"	d
+MODE_REG_IN_MMU_SZ	include/ssv6200_aux.h	555;"	d
+MODE_REG_IN_MSK	include/ssv6200_aux.h	396;"	d
+MODE_REG_IN_SFT	include/ssv6200_aux.h	398;"	d
+MODE_REG_IN_SZ	include/ssv6200_aux.h	400;"	d
+MODE_REG_OUT_MCU_HI	include/ssv6200_aux.h	404;"	d
+MODE_REG_OUT_MCU_I_MSK	include/ssv6200_aux.h	402;"	d
+MODE_REG_OUT_MCU_MSK	include/ssv6200_aux.h	401;"	d
+MODE_REG_OUT_MCU_SFT	include/ssv6200_aux.h	403;"	d
+MODE_REG_OUT_MCU_SZ	include/ssv6200_aux.h	405;"	d
+MODE_REG_OUT_MMU_HI	include/ssv6200_aux.h	559;"	d
+MODE_REG_OUT_MMU_I_MSK	include/ssv6200_aux.h	557;"	d
+MODE_REG_OUT_MMU_MSK	include/ssv6200_aux.h	556;"	d
+MODE_REG_OUT_MMU_SFT	include/ssv6200_aux.h	558;"	d
+MODE_REG_OUT_MMU_SZ	include/ssv6200_aux.h	560;"	d
+MODE_REG_SI_HI	include/ssv6200_aux.h	384;"	d
+MODE_REG_SI_I_MSK	include/ssv6200_aux.h	382;"	d
+MODE_REG_SI_MSK	include/ssv6200_aux.h	381;"	d
+MODE_REG_SI_SFT	include/ssv6200_aux.h	383;"	d
+MODE_REG_SI_SZ	include/ssv6200_aux.h	385;"	d
+MODE_REG_SO_MCU_HI	include/ssv6200_aux.h	409;"	d
+MODE_REG_SO_MCU_I_MSK	include/ssv6200_aux.h	407;"	d
+MODE_REG_SO_MCU_MSK	include/ssv6200_aux.h	406;"	d
+MODE_REG_SO_MCU_SFT	include/ssv6200_aux.h	408;"	d
+MODE_REG_SO_MCU_SZ	include/ssv6200_aux.h	410;"	d
+MODE_REG_SO_MMU_HI	include/ssv6200_aux.h	564;"	d
+MODE_REG_SO_MMU_I_MSK	include/ssv6200_aux.h	562;"	d
+MODE_REG_SO_MMU_MSK	include/ssv6200_aux.h	561;"	d
+MODE_REG_SO_MMU_SFT	include/ssv6200_aux.h	563;"	d
+MODE_REG_SO_MMU_SZ	include/ssv6200_aux.h	565;"	d
+MODE_STANDBY	smac/hal/ssv6006c/turismo_common.h	/^    MODE_STANDBY,$/;"	e	enum:__anon5
+MODE_WIFI2P4G_RX	smac/hal/ssv6006c/turismo_common.h	/^    MODE_WIFI2P4G_RX,$/;"	e	enum:__anon5
+MODE_WIFI2P4G_TX	smac/hal/ssv6006c/turismo_common.h	/^    MODE_WIFI2P4G_TX,$/;"	e	enum:__anon5
+MODE_WIFI5G_RX	smac/hal/ssv6006c/turismo_common.h	/^    MODE_WIFI5G_RX,$/;"	e	enum:__anon5
+MODE_WIFI5G_TX	smac/hal/ssv6006c/turismo_common.h	/^    MODE_WIFI5G_TX,$/;"	e	enum:__anon5
+MOD_DEF_H	Makefile	/^MOD_DEF_H = include\/ssv_mod_conf.h$/;"	m
+MONITOR_BUS_MCU_31_0_HI	include/ssv6200_aux.h	414;"	d
+MONITOR_BUS_MCU_31_0_I_MSK	include/ssv6200_aux.h	412;"	d
+MONITOR_BUS_MCU_31_0_MSK	include/ssv6200_aux.h	411;"	d
+MONITOR_BUS_MCU_31_0_SFT	include/ssv6200_aux.h	413;"	d
+MONITOR_BUS_MCU_31_0_SZ	include/ssv6200_aux.h	415;"	d
+MONITOR_BUS_MCU_33_32_HI	include/ssv6200_aux.h	419;"	d
+MONITOR_BUS_MCU_33_32_I_MSK	include/ssv6200_aux.h	417;"	d
+MONITOR_BUS_MCU_33_32_MSK	include/ssv6200_aux.h	416;"	d
+MONITOR_BUS_MCU_33_32_SFT	include/ssv6200_aux.h	418;"	d
+MONITOR_BUS_MCU_33_32_SZ	include/ssv6200_aux.h	420;"	d
+MONITOR_BUS_MMU_HI	include/ssv6200_aux.h	569;"	d
+MONITOR_BUS_MMU_I_MSK	include/ssv6200_aux.h	567;"	d
+MONITOR_BUS_MMU_MSK	include/ssv6200_aux.h	566;"	d
+MONITOR_BUS_MMU_SFT	include/ssv6200_aux.h	568;"	d
+MONITOR_BUS_MMU_SZ	include/ssv6200_aux.h	570;"	d
+MONITOR_NOA_CONF_ADD	smac/p2p.h	/^ MONITOR_NOA_CONF_ADD,$/;"	e	enum:ssv6xxx_noa_conf
+MONITOR_NOA_CONF_REMOVE	smac/p2p.h	/^ MONITOR_NOA_CONF_REMOVE,$/;"	e	enum:ssv6xxx_noa_conf
+MP_MRX_RX_EN_SEL_HI	include/ssv6200_aux.h	3014;"	d
+MP_MRX_RX_EN_SEL_I_MSK	include/ssv6200_aux.h	3012;"	d
+MP_MRX_RX_EN_SEL_MSK	include/ssv6200_aux.h	3011;"	d
+MP_MRX_RX_EN_SEL_SFT	include/ssv6200_aux.h	3013;"	d
+MP_MRX_RX_EN_SEL_SZ	include/ssv6200_aux.h	3015;"	d
+MP_PHY2RX_DATA__0_SEL_HI	include/ssv6200_aux.h	2899;"	d
+MP_PHY2RX_DATA__0_SEL_I_MSK	include/ssv6200_aux.h	2897;"	d
+MP_PHY2RX_DATA__0_SEL_MSK	include/ssv6200_aux.h	2896;"	d
+MP_PHY2RX_DATA__0_SEL_SFT	include/ssv6200_aux.h	2898;"	d
+MP_PHY2RX_DATA__0_SEL_SZ	include/ssv6200_aux.h	2900;"	d
+MP_PHY2RX_DATA__1_SEL_HI	include/ssv6200_aux.h	2904;"	d
+MP_PHY2RX_DATA__1_SEL_I_MSK	include/ssv6200_aux.h	2902;"	d
+MP_PHY2RX_DATA__1_SEL_MSK	include/ssv6200_aux.h	2901;"	d
+MP_PHY2RX_DATA__1_SEL_SFT	include/ssv6200_aux.h	2903;"	d
+MP_PHY2RX_DATA__1_SEL_SZ	include/ssv6200_aux.h	2905;"	d
+MP_PHY2RX_DATA__2_SEL_HI	include/ssv6200_aux.h	2929;"	d
+MP_PHY2RX_DATA__2_SEL_I_MSK	include/ssv6200_aux.h	2927;"	d
+MP_PHY2RX_DATA__2_SEL_MSK	include/ssv6200_aux.h	2926;"	d
+MP_PHY2RX_DATA__2_SEL_SFT	include/ssv6200_aux.h	2928;"	d
+MP_PHY2RX_DATA__2_SEL_SZ	include/ssv6200_aux.h	2930;"	d
+MP_PHY2RX_DATA__3_SEL_HI	include/ssv6200_aux.h	2954;"	d
+MP_PHY2RX_DATA__3_SEL_I_MSK	include/ssv6200_aux.h	2952;"	d
+MP_PHY2RX_DATA__3_SEL_MSK	include/ssv6200_aux.h	2951;"	d
+MP_PHY2RX_DATA__3_SEL_SFT	include/ssv6200_aux.h	2953;"	d
+MP_PHY2RX_DATA__3_SEL_SZ	include/ssv6200_aux.h	2955;"	d
+MP_PHY2RX_DATA__4_SEL_HI	include/ssv6200_aux.h	2934;"	d
+MP_PHY2RX_DATA__4_SEL_I_MSK	include/ssv6200_aux.h	2932;"	d
+MP_PHY2RX_DATA__4_SEL_MSK	include/ssv6200_aux.h	2931;"	d
+MP_PHY2RX_DATA__4_SEL_SFT	include/ssv6200_aux.h	2933;"	d
+MP_PHY2RX_DATA__4_SEL_SZ	include/ssv6200_aux.h	2935;"	d
+MP_PHY2RX_DATA__5_SEL_HI	include/ssv6200_aux.h	2949;"	d
+MP_PHY2RX_DATA__5_SEL_I_MSK	include/ssv6200_aux.h	2947;"	d
+MP_PHY2RX_DATA__5_SEL_MSK	include/ssv6200_aux.h	2946;"	d
+MP_PHY2RX_DATA__5_SEL_SFT	include/ssv6200_aux.h	2948;"	d
+MP_PHY2RX_DATA__5_SEL_SZ	include/ssv6200_aux.h	2950;"	d
+MP_PHY2RX_DATA__6_SEL_HI	include/ssv6200_aux.h	2964;"	d
+MP_PHY2RX_DATA__6_SEL_I_MSK	include/ssv6200_aux.h	2962;"	d
+MP_PHY2RX_DATA__6_SEL_MSK	include/ssv6200_aux.h	2961;"	d
+MP_PHY2RX_DATA__6_SEL_SFT	include/ssv6200_aux.h	2963;"	d
+MP_PHY2RX_DATA__6_SEL_SZ	include/ssv6200_aux.h	2965;"	d
+MP_PHY2RX_DATA__7_SEL_HI	include/ssv6200_aux.h	2994;"	d
+MP_PHY2RX_DATA__7_SEL_I_MSK	include/ssv6200_aux.h	2992;"	d
+MP_PHY2RX_DATA__7_SEL_MSK	include/ssv6200_aux.h	2991;"	d
+MP_PHY2RX_DATA__7_SEL_SFT	include/ssv6200_aux.h	2993;"	d
+MP_PHY2RX_DATA__7_SEL_SZ	include/ssv6200_aux.h	2995;"	d
+MP_PHY_RX_WRST_N_SEL_HI	include/ssv6200_aux.h	2984;"	d
+MP_PHY_RX_WRST_N_SEL_I_MSK	include/ssv6200_aux.h	2982;"	d
+MP_PHY_RX_WRST_N_SEL_MSK	include/ssv6200_aux.h	2981;"	d
+MP_PHY_RX_WRST_N_SEL_SFT	include/ssv6200_aux.h	2983;"	d
+MP_PHY_RX_WRST_N_SEL_SZ	include/ssv6200_aux.h	2985;"	d
+MP_RX_FF_WPTR__0_SEL_HI	include/ssv6200_aux.h	2924;"	d
+MP_RX_FF_WPTR__0_SEL_I_MSK	include/ssv6200_aux.h	2922;"	d
+MP_RX_FF_WPTR__0_SEL_MSK	include/ssv6200_aux.h	2921;"	d
+MP_RX_FF_WPTR__0_SEL_SFT	include/ssv6200_aux.h	2923;"	d
+MP_RX_FF_WPTR__0_SEL_SZ	include/ssv6200_aux.h	2925;"	d
+MP_RX_FF_WPTR__1_SEL_HI	include/ssv6200_aux.h	2919;"	d
+MP_RX_FF_WPTR__1_SEL_I_MSK	include/ssv6200_aux.h	2917;"	d
+MP_RX_FF_WPTR__1_SEL_MSK	include/ssv6200_aux.h	2916;"	d
+MP_RX_FF_WPTR__1_SEL_SFT	include/ssv6200_aux.h	2918;"	d
+MP_RX_FF_WPTR__1_SEL_SZ	include/ssv6200_aux.h	2920;"	d
+MP_RX_FF_WPTR__2_SEL_HI	include/ssv6200_aux.h	2914;"	d
+MP_RX_FF_WPTR__2_SEL_I_MSK	include/ssv6200_aux.h	2912;"	d
+MP_RX_FF_WPTR__2_SEL_MSK	include/ssv6200_aux.h	2911;"	d
+MP_RX_FF_WPTR__2_SEL_SFT	include/ssv6200_aux.h	2913;"	d
+MP_RX_FF_WPTR__2_SEL_SZ	include/ssv6200_aux.h	2915;"	d
+MP_TX_FF_RPTR__0_SEL_HI	include/ssv6200_aux.h	2979;"	d
+MP_TX_FF_RPTR__0_SEL_I_MSK	include/ssv6200_aux.h	2977;"	d
+MP_TX_FF_RPTR__0_SEL_MSK	include/ssv6200_aux.h	2976;"	d
+MP_TX_FF_RPTR__0_SEL_SFT	include/ssv6200_aux.h	2978;"	d
+MP_TX_FF_RPTR__0_SEL_SZ	include/ssv6200_aux.h	2980;"	d
+MP_TX_FF_RPTR__1_SEL_HI	include/ssv6200_aux.h	2909;"	d
+MP_TX_FF_RPTR__1_SEL_I_MSK	include/ssv6200_aux.h	2907;"	d
+MP_TX_FF_RPTR__1_SEL_MSK	include/ssv6200_aux.h	2906;"	d
+MP_TX_FF_RPTR__1_SEL_SFT	include/ssv6200_aux.h	2908;"	d
+MP_TX_FF_RPTR__1_SEL_SZ	include/ssv6200_aux.h	2910;"	d
+MP_TX_FF_RPTR__2_SEL_HI	include/ssv6200_aux.h	2999;"	d
+MP_TX_FF_RPTR__2_SEL_I_MSK	include/ssv6200_aux.h	2997;"	d
+MP_TX_FF_RPTR__2_SEL_MSK	include/ssv6200_aux.h	2996;"	d
+MP_TX_FF_RPTR__2_SEL_SFT	include/ssv6200_aux.h	2998;"	d
+MP_TX_FF_RPTR__2_SEL_SZ	include/ssv6200_aux.h	3000;"	d
+MRX_ACK_NTF_HI	include/ssv6200_aux.h	9544;"	d
+MRX_ACK_NTF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9379;"	d
+MRX_ACK_NTF_I_MSK	include/ssv6200_aux.h	9542;"	d
+MRX_ACK_NTF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9377;"	d
+MRX_ACK_NTF_MSK	include/ssv6200_aux.h	9541;"	d
+MRX_ACK_NTF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9376;"	d
+MRX_ACK_NTF_SFT	include/ssv6200_aux.h	9543;"	d
+MRX_ACK_NTF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9378;"	d
+MRX_ACK_NTF_SZ	include/ssv6200_aux.h	9545;"	d
+MRX_ACK_NTF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9380;"	d
+MRX_ALC_FAIL_HI	include/ssv6200_aux.h	9524;"	d
+MRX_ALC_FAIL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9359;"	d
+MRX_ALC_FAIL_I_MSK	include/ssv6200_aux.h	9522;"	d
+MRX_ALC_FAIL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9357;"	d
+MRX_ALC_FAIL_MSK	include/ssv6200_aux.h	9521;"	d
+MRX_ALC_FAIL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9356;"	d
+MRX_ALC_FAIL_SFT	include/ssv6200_aux.h	9523;"	d
+MRX_ALC_FAIL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9358;"	d
+MRX_ALC_FAIL_SZ	include/ssv6200_aux.h	9525;"	d
+MRX_ALC_FAIL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9360;"	d
+MRX_BAR_NTF_HI	include/ssv6200_aux.h	9569;"	d
+MRX_BAR_NTF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9404;"	d
+MRX_BAR_NTF_I_MSK	include/ssv6200_aux.h	9567;"	d
+MRX_BAR_NTF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9402;"	d
+MRX_BAR_NTF_MSK	include/ssv6200_aux.h	9566;"	d
+MRX_BAR_NTF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9401;"	d
+MRX_BAR_NTF_SFT	include/ssv6200_aux.h	9568;"	d
+MRX_BAR_NTF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9403;"	d
+MRX_BAR_NTF_SZ	include/ssv6200_aux.h	9570;"	d
+MRX_BAR_NTF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9405;"	d
+MRX_BA_NTF_HI	include/ssv6200_aux.h	9549;"	d
+MRX_BA_NTF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9384;"	d
+MRX_BA_NTF_I_MSK	include/ssv6200_aux.h	9547;"	d
+MRX_BA_NTF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9382;"	d
+MRX_BA_NTF_MSK	include/ssv6200_aux.h	9546;"	d
+MRX_BA_NTF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9381;"	d
+MRX_BA_NTF_SFT	include/ssv6200_aux.h	9548;"	d
+MRX_BA_NTF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9383;"	d
+MRX_BA_NTF_SZ	include/ssv6200_aux.h	9550;"	d
+MRX_BA_NTF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9385;"	d
+MRX_CCA_HI	include/ssv6200_aux.h	7699;"	d
+MRX_CCA_I_MSK	include/ssv6200_aux.h	7697;"	d
+MRX_CCA_MSK	include/ssv6200_aux.h	7696;"	d
+MRX_CCA_SFT	include/ssv6200_aux.h	7698;"	d
+MRX_CCA_SZ	include/ssv6200_aux.h	7700;"	d
+MRX_CLK_EN_HI	include/ssv6200_aux.h	9004;"	d
+MRX_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8759;"	d
+MRX_CLK_EN_I_MSK	include/ssv6200_aux.h	9002;"	d
+MRX_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8757;"	d
+MRX_CLK_EN_MSK	include/ssv6200_aux.h	9001;"	d
+MRX_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8756;"	d
+MRX_CLK_EN_SFT	include/ssv6200_aux.h	9003;"	d
+MRX_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8758;"	d
+MRX_CLK_EN_SZ	include/ssv6200_aux.h	9005;"	d
+MRX_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8760;"	d
+MRX_CSR_CLK_EN_HI	include/ssv6200_aux.h	9099;"	d
+MRX_CSR_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8854;"	d
+MRX_CSR_CLK_EN_I_MSK	include/ssv6200_aux.h	9097;"	d
+MRX_CSR_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8852;"	d
+MRX_CSR_CLK_EN_MSK	include/ssv6200_aux.h	9096;"	d
+MRX_CSR_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8851;"	d
+MRX_CSR_CLK_EN_SFT	include/ssv6200_aux.h	9098;"	d
+MRX_CSR_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8853;"	d
+MRX_CSR_CLK_EN_SZ	include/ssv6200_aux.h	9100;"	d
+MRX_CSR_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8855;"	d
+MRX_CSR_NTF_HI	include/ssv6200_aux.h	9584;"	d
+MRX_CSR_NTF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9419;"	d
+MRX_CSR_NTF_I_MSK	include/ssv6200_aux.h	9582;"	d
+MRX_CSR_NTF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9417;"	d
+MRX_CSR_NTF_MSK	include/ssv6200_aux.h	9581;"	d
+MRX_CSR_NTF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9416;"	d
+MRX_CSR_NTF_SFT	include/ssv6200_aux.h	9583;"	d
+MRX_CSR_NTF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9418;"	d
+MRX_CSR_NTF_SZ	include/ssv6200_aux.h	9585;"	d
+MRX_CSR_NTF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9420;"	d
+MRX_CSR_RST_HI	include/ssv6200_aux.h	8959;"	d
+MRX_CSR_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8714;"	d
+MRX_CSR_RST_I_MSK	include/ssv6200_aux.h	8957;"	d
+MRX_CSR_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8712;"	d
+MRX_CSR_RST_MSK	include/ssv6200_aux.h	8956;"	d
+MRX_CSR_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8711;"	d
+MRX_CSR_RST_SFT	include/ssv6200_aux.h	8958;"	d
+MRX_CSR_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8713;"	d
+MRX_CSR_RST_SZ	include/ssv6200_aux.h	8960;"	d
+MRX_CSR_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8715;"	d
+MRX_CTS_NTF_HI	include/ssv6200_aux.h	9539;"	d
+MRX_CTS_NTF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9374;"	d
+MRX_CTS_NTF_I_MSK	include/ssv6200_aux.h	9537;"	d
+MRX_CTS_NTF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9372;"	d
+MRX_CTS_NTF_MSK	include/ssv6200_aux.h	9536;"	d
+MRX_CTS_NTF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9371;"	d
+MRX_CTS_NTF_SFT	include/ssv6200_aux.h	9538;"	d
+MRX_CTS_NTF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9373;"	d
+MRX_CTS_NTF_SZ	include/ssv6200_aux.h	9540;"	d
+MRX_CTS_NTF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9375;"	d
+MRX_DATA_NTF_HI	include/ssv6200_aux.h	9554;"	d
+MRX_DATA_NTF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9389;"	d
+MRX_DATA_NTF_I_MSK	include/ssv6200_aux.h	9552;"	d
+MRX_DATA_NTF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9387;"	d
+MRX_DATA_NTF_MSK	include/ssv6200_aux.h	9551;"	d
+MRX_DATA_NTF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9386;"	d
+MRX_DATA_NTF_SFT	include/ssv6200_aux.h	9553;"	d
+MRX_DATA_NTF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9388;"	d
+MRX_DATA_NTF_SZ	include/ssv6200_aux.h	9555;"	d
+MRX_DATA_NTF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9390;"	d
+MRX_DAT_CRC_NTF_HI	include/ssv6200_aux.h	9564;"	d
+MRX_DAT_CRC_NTF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9399;"	d
+MRX_DAT_CRC_NTF_I_MSK	include/ssv6200_aux.h	9562;"	d
+MRX_DAT_CRC_NTF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9397;"	d
+MRX_DAT_CRC_NTF_MSK	include/ssv6200_aux.h	9561;"	d
+MRX_DAT_CRC_NTF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9396;"	d
+MRX_DAT_CRC_NTF_SFT	include/ssv6200_aux.h	9563;"	d
+MRX_DAT_CRC_NTF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9398;"	d
+MRX_DAT_CRC_NTF_SZ	include/ssv6200_aux.h	9565;"	d
+MRX_DAT_CRC_NTF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9400;"	d
+MRX_DAT_NTF_HI	include/ssv6200_aux.h	9529;"	d
+MRX_DAT_NTF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9364;"	d
+MRX_DAT_NTF_I_MSK	include/ssv6200_aux.h	9527;"	d
+MRX_DAT_NTF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9362;"	d
+MRX_DAT_NTF_MSK	include/ssv6200_aux.h	9526;"	d
+MRX_DAT_NTF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9361;"	d
+MRX_DAT_NTF_SFT	include/ssv6200_aux.h	9528;"	d
+MRX_DAT_NTF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9363;"	d
+MRX_DAT_NTF_SZ	include/ssv6200_aux.h	9530;"	d
+MRX_DAT_NTF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9365;"	d
+MRX_DUP_HI	include/ssv6200_aux.h	9494;"	d
+MRX_DUP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9329;"	d
+MRX_DUP_I_MSK	include/ssv6200_aux.h	9492;"	d
+MRX_DUP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9327;"	d
+MRX_DUP_MSK	include/ssv6200_aux.h	9491;"	d
+MRX_DUP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9326;"	d
+MRX_DUP_SFT	include/ssv6200_aux.h	9493;"	d
+MRX_DUP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9328;"	d
+MRX_DUP_SZ	include/ssv6200_aux.h	9495;"	d
+MRX_DUP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9330;"	d
+MRX_ENG_CLK_EN_HI	include/ssv6200_aux.h	9064;"	d
+MRX_ENG_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8819;"	d
+MRX_ENG_CLK_EN_I_MSK	include/ssv6200_aux.h	9062;"	d
+MRX_ENG_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8817;"	d
+MRX_ENG_CLK_EN_MSK	include/ssv6200_aux.h	9061;"	d
+MRX_ENG_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8816;"	d
+MRX_ENG_CLK_EN_SFT	include/ssv6200_aux.h	9063;"	d
+MRX_ENG_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8818;"	d
+MRX_ENG_CLK_EN_SZ	include/ssv6200_aux.h	9065;"	d
+MRX_ENG_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8820;"	d
+MRX_ENG_RST_HI	include/ssv6200_aux.h	8889;"	d
+MRX_ENG_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8644;"	d
+MRX_ENG_RST_I_MSK	include/ssv6200_aux.h	8887;"	d
+MRX_ENG_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8642;"	d
+MRX_ENG_RST_MSK	include/ssv6200_aux.h	8886;"	d
+MRX_ENG_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8641;"	d
+MRX_ENG_RST_SFT	include/ssv6200_aux.h	8888;"	d
+MRX_ENG_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8643;"	d
+MRX_ENG_RST_SZ	include/ssv6200_aux.h	8890;"	d
+MRX_ENG_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8645;"	d
+MRX_ERR_HI	include/ssv6200_aux.h	7254;"	d
+MRX_ERR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6429;"	d
+MRX_ERR_I_MSK	include/ssv6200_aux.h	7252;"	d
+MRX_ERR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6427;"	d
+MRX_ERR_MSK	include/ssv6200_aux.h	7251;"	d
+MRX_ERR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6426;"	d
+MRX_ERR_SFT	include/ssv6200_aux.h	7253;"	d
+MRX_ERR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6428;"	d
+MRX_ERR_SZ	include/ssv6200_aux.h	7255;"	d
+MRX_ERR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6430;"	d
+MRX_FCS_ERR_HI	include/ssv6200_aux.h	9509;"	d
+MRX_FCS_ERR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9344;"	d
+MRX_FCS_ERR_I_MSK	include/ssv6200_aux.h	9507;"	d
+MRX_FCS_ERR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9342;"	d
+MRX_FCS_ERR_MSK	include/ssv6200_aux.h	9506;"	d
+MRX_FCS_ERR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9341;"	d
+MRX_FCS_ERR_SFT	include/ssv6200_aux.h	9508;"	d
+MRX_FCS_ERR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9343;"	d
+MRX_FCS_ERR_SZ	include/ssv6200_aux.h	9510;"	d
+MRX_FCS_ERR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9345;"	d
+MRX_FCS_SUC_HI	include/ssv6200_aux.h	9514;"	d
+MRX_FCS_SUC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9349;"	d
+MRX_FCS_SUC_I_MSK	include/ssv6200_aux.h	9512;"	d
+MRX_FCS_SUC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9347;"	d
+MRX_FCS_SUC_MSK	include/ssv6200_aux.h	9511;"	d
+MRX_FCS_SUC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9346;"	d
+MRX_FCS_SUC_SFT	include/ssv6200_aux.h	9513;"	d
+MRX_FCS_SUC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9348;"	d
+MRX_FCS_SUC_SZ	include/ssv6200_aux.h	9515;"	d
+MRX_FCS_SUC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9350;"	d
+MRX_FLT_EN0_HI	include/ssv6200_aux.h	7054;"	d
+MRX_FLT_EN0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6229;"	d
+MRX_FLT_EN0_I_MSK	include/ssv6200_aux.h	7052;"	d
+MRX_FLT_EN0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6227;"	d
+MRX_FLT_EN0_MSK	include/ssv6200_aux.h	7051;"	d
+MRX_FLT_EN0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6226;"	d
+MRX_FLT_EN0_SFT	include/ssv6200_aux.h	7053;"	d
+MRX_FLT_EN0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6228;"	d
+MRX_FLT_EN0_SZ	include/ssv6200_aux.h	7055;"	d
+MRX_FLT_EN0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6230;"	d
+MRX_FLT_EN10_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6529;"	d
+MRX_FLT_EN10_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6527;"	d
+MRX_FLT_EN10_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6526;"	d
+MRX_FLT_EN10_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6528;"	d
+MRX_FLT_EN10_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6530;"	d
+MRX_FLT_EN1_HI	include/ssv6200_aux.h	7059;"	d
+MRX_FLT_EN1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6234;"	d
+MRX_FLT_EN1_I_MSK	include/ssv6200_aux.h	7057;"	d
+MRX_FLT_EN1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6232;"	d
+MRX_FLT_EN1_MSK	include/ssv6200_aux.h	7056;"	d
+MRX_FLT_EN1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6231;"	d
+MRX_FLT_EN1_SFT	include/ssv6200_aux.h	7058;"	d
+MRX_FLT_EN1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6233;"	d
+MRX_FLT_EN1_SZ	include/ssv6200_aux.h	7060;"	d
+MRX_FLT_EN1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6235;"	d
+MRX_FLT_EN2_HI	include/ssv6200_aux.h	7064;"	d
+MRX_FLT_EN2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6239;"	d
+MRX_FLT_EN2_I_MSK	include/ssv6200_aux.h	7062;"	d
+MRX_FLT_EN2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6237;"	d
+MRX_FLT_EN2_MSK	include/ssv6200_aux.h	7061;"	d
+MRX_FLT_EN2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6236;"	d
+MRX_FLT_EN2_SFT	include/ssv6200_aux.h	7063;"	d
+MRX_FLT_EN2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6238;"	d
+MRX_FLT_EN2_SZ	include/ssv6200_aux.h	7065;"	d
+MRX_FLT_EN2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6240;"	d
+MRX_FLT_EN3_HI	include/ssv6200_aux.h	7069;"	d
+MRX_FLT_EN3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6244;"	d
+MRX_FLT_EN3_I_MSK	include/ssv6200_aux.h	7067;"	d
+MRX_FLT_EN3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6242;"	d
+MRX_FLT_EN3_MSK	include/ssv6200_aux.h	7066;"	d
+MRX_FLT_EN3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6241;"	d
+MRX_FLT_EN3_SFT	include/ssv6200_aux.h	7068;"	d
+MRX_FLT_EN3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6243;"	d
+MRX_FLT_EN3_SZ	include/ssv6200_aux.h	7070;"	d
+MRX_FLT_EN3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6245;"	d
+MRX_FLT_EN4_HI	include/ssv6200_aux.h	7074;"	d
+MRX_FLT_EN4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6249;"	d
+MRX_FLT_EN4_I_MSK	include/ssv6200_aux.h	7072;"	d
+MRX_FLT_EN4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6247;"	d
+MRX_FLT_EN4_MSK	include/ssv6200_aux.h	7071;"	d
+MRX_FLT_EN4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6246;"	d
+MRX_FLT_EN4_SFT	include/ssv6200_aux.h	7073;"	d
+MRX_FLT_EN4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6248;"	d
+MRX_FLT_EN4_SZ	include/ssv6200_aux.h	7075;"	d
+MRX_FLT_EN4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6250;"	d
+MRX_FLT_EN5_HI	include/ssv6200_aux.h	7079;"	d
+MRX_FLT_EN5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6254;"	d
+MRX_FLT_EN5_I_MSK	include/ssv6200_aux.h	7077;"	d
+MRX_FLT_EN5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6252;"	d
+MRX_FLT_EN5_MSK	include/ssv6200_aux.h	7076;"	d
+MRX_FLT_EN5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6251;"	d
+MRX_FLT_EN5_SFT	include/ssv6200_aux.h	7078;"	d
+MRX_FLT_EN5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6253;"	d
+MRX_FLT_EN5_SZ	include/ssv6200_aux.h	7080;"	d
+MRX_FLT_EN5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6255;"	d
+MRX_FLT_EN6_HI	include/ssv6200_aux.h	7084;"	d
+MRX_FLT_EN6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6259;"	d
+MRX_FLT_EN6_I_MSK	include/ssv6200_aux.h	7082;"	d
+MRX_FLT_EN6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6257;"	d
+MRX_FLT_EN6_MSK	include/ssv6200_aux.h	7081;"	d
+MRX_FLT_EN6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6256;"	d
+MRX_FLT_EN6_SFT	include/ssv6200_aux.h	7083;"	d
+MRX_FLT_EN6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6258;"	d
+MRX_FLT_EN6_SZ	include/ssv6200_aux.h	7085;"	d
+MRX_FLT_EN6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6260;"	d
+MRX_FLT_EN7_HI	include/ssv6200_aux.h	7089;"	d
+MRX_FLT_EN7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6264;"	d
+MRX_FLT_EN7_I_MSK	include/ssv6200_aux.h	7087;"	d
+MRX_FLT_EN7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6262;"	d
+MRX_FLT_EN7_MSK	include/ssv6200_aux.h	7086;"	d
+MRX_FLT_EN7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6261;"	d
+MRX_FLT_EN7_SFT	include/ssv6200_aux.h	7088;"	d
+MRX_FLT_EN7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6263;"	d
+MRX_FLT_EN7_SZ	include/ssv6200_aux.h	7090;"	d
+MRX_FLT_EN7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6265;"	d
+MRX_FLT_EN8_HI	include/ssv6200_aux.h	7094;"	d
+MRX_FLT_EN8_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6269;"	d
+MRX_FLT_EN8_I_MSK	include/ssv6200_aux.h	7092;"	d
+MRX_FLT_EN8_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6267;"	d
+MRX_FLT_EN8_MSK	include/ssv6200_aux.h	7091;"	d
+MRX_FLT_EN8_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6266;"	d
+MRX_FLT_EN8_SFT	include/ssv6200_aux.h	7093;"	d
+MRX_FLT_EN8_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6268;"	d
+MRX_FLT_EN8_SZ	include/ssv6200_aux.h	7095;"	d
+MRX_FLT_EN8_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6270;"	d
+MRX_FLT_EN9_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6524;"	d
+MRX_FLT_EN9_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6522;"	d
+MRX_FLT_EN9_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6521;"	d
+MRX_FLT_EN9_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6523;"	d
+MRX_FLT_EN9_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6525;"	d
+MRX_FLT_TB0_HI	include/ssv6200_aux.h	6974;"	d
+MRX_FLT_TB0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6149;"	d
+MRX_FLT_TB0_I_MSK	include/ssv6200_aux.h	6972;"	d
+MRX_FLT_TB0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6147;"	d
+MRX_FLT_TB0_MSK	include/ssv6200_aux.h	6971;"	d
+MRX_FLT_TB0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6146;"	d
+MRX_FLT_TB0_SFT	include/ssv6200_aux.h	6973;"	d
+MRX_FLT_TB0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6148;"	d
+MRX_FLT_TB0_SZ	include/ssv6200_aux.h	6975;"	d
+MRX_FLT_TB0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6150;"	d
+MRX_FLT_TB10_HI	include/ssv6200_aux.h	7024;"	d
+MRX_FLT_TB10_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6199;"	d
+MRX_FLT_TB10_I_MSK	include/ssv6200_aux.h	7022;"	d
+MRX_FLT_TB10_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6197;"	d
+MRX_FLT_TB10_MSK	include/ssv6200_aux.h	7021;"	d
+MRX_FLT_TB10_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6196;"	d
+MRX_FLT_TB10_SFT	include/ssv6200_aux.h	7023;"	d
+MRX_FLT_TB10_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6198;"	d
+MRX_FLT_TB10_SZ	include/ssv6200_aux.h	7025;"	d
+MRX_FLT_TB10_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6200;"	d
+MRX_FLT_TB11_HI	include/ssv6200_aux.h	7029;"	d
+MRX_FLT_TB11_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6204;"	d
+MRX_FLT_TB11_I_MSK	include/ssv6200_aux.h	7027;"	d
+MRX_FLT_TB11_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6202;"	d
+MRX_FLT_TB11_MSK	include/ssv6200_aux.h	7026;"	d
+MRX_FLT_TB11_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6201;"	d
+MRX_FLT_TB11_SFT	include/ssv6200_aux.h	7028;"	d
+MRX_FLT_TB11_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6203;"	d
+MRX_FLT_TB11_SZ	include/ssv6200_aux.h	7030;"	d
+MRX_FLT_TB11_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6205;"	d
+MRX_FLT_TB12_HI	include/ssv6200_aux.h	7034;"	d
+MRX_FLT_TB12_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6209;"	d
+MRX_FLT_TB12_I_MSK	include/ssv6200_aux.h	7032;"	d
+MRX_FLT_TB12_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6207;"	d
+MRX_FLT_TB12_MSK	include/ssv6200_aux.h	7031;"	d
+MRX_FLT_TB12_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6206;"	d
+MRX_FLT_TB12_SFT	include/ssv6200_aux.h	7033;"	d
+MRX_FLT_TB12_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6208;"	d
+MRX_FLT_TB12_SZ	include/ssv6200_aux.h	7035;"	d
+MRX_FLT_TB12_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6210;"	d
+MRX_FLT_TB13_HI	include/ssv6200_aux.h	7039;"	d
+MRX_FLT_TB13_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6214;"	d
+MRX_FLT_TB13_I_MSK	include/ssv6200_aux.h	7037;"	d
+MRX_FLT_TB13_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6212;"	d
+MRX_FLT_TB13_MSK	include/ssv6200_aux.h	7036;"	d
+MRX_FLT_TB13_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6211;"	d
+MRX_FLT_TB13_SFT	include/ssv6200_aux.h	7038;"	d
+MRX_FLT_TB13_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6213;"	d
+MRX_FLT_TB13_SZ	include/ssv6200_aux.h	7040;"	d
+MRX_FLT_TB13_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6215;"	d
+MRX_FLT_TB14_HI	include/ssv6200_aux.h	7044;"	d
+MRX_FLT_TB14_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6219;"	d
+MRX_FLT_TB14_I_MSK	include/ssv6200_aux.h	7042;"	d
+MRX_FLT_TB14_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6217;"	d
+MRX_FLT_TB14_MSK	include/ssv6200_aux.h	7041;"	d
+MRX_FLT_TB14_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6216;"	d
+MRX_FLT_TB14_SFT	include/ssv6200_aux.h	7043;"	d
+MRX_FLT_TB14_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6218;"	d
+MRX_FLT_TB14_SZ	include/ssv6200_aux.h	7045;"	d
+MRX_FLT_TB14_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6220;"	d
+MRX_FLT_TB15_HI	include/ssv6200_aux.h	7049;"	d
+MRX_FLT_TB15_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6224;"	d
+MRX_FLT_TB15_I_MSK	include/ssv6200_aux.h	7047;"	d
+MRX_FLT_TB15_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6222;"	d
+MRX_FLT_TB15_MSK	include/ssv6200_aux.h	7046;"	d
+MRX_FLT_TB15_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6221;"	d
+MRX_FLT_TB15_SFT	include/ssv6200_aux.h	7048;"	d
+MRX_FLT_TB15_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6223;"	d
+MRX_FLT_TB15_SZ	include/ssv6200_aux.h	7050;"	d
+MRX_FLT_TB15_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6225;"	d
+MRX_FLT_TB1_HI	include/ssv6200_aux.h	6979;"	d
+MRX_FLT_TB1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6154;"	d
+MRX_FLT_TB1_I_MSK	include/ssv6200_aux.h	6977;"	d
+MRX_FLT_TB1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6152;"	d
+MRX_FLT_TB1_MSK	include/ssv6200_aux.h	6976;"	d
+MRX_FLT_TB1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6151;"	d
+MRX_FLT_TB1_SFT	include/ssv6200_aux.h	6978;"	d
+MRX_FLT_TB1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6153;"	d
+MRX_FLT_TB1_SZ	include/ssv6200_aux.h	6980;"	d
+MRX_FLT_TB1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6155;"	d
+MRX_FLT_TB2_HI	include/ssv6200_aux.h	6984;"	d
+MRX_FLT_TB2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6159;"	d
+MRX_FLT_TB2_I_MSK	include/ssv6200_aux.h	6982;"	d
+MRX_FLT_TB2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6157;"	d
+MRX_FLT_TB2_MSK	include/ssv6200_aux.h	6981;"	d
+MRX_FLT_TB2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6156;"	d
+MRX_FLT_TB2_SFT	include/ssv6200_aux.h	6983;"	d
+MRX_FLT_TB2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6158;"	d
+MRX_FLT_TB2_SZ	include/ssv6200_aux.h	6985;"	d
+MRX_FLT_TB2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6160;"	d
+MRX_FLT_TB3_HI	include/ssv6200_aux.h	6989;"	d
+MRX_FLT_TB3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6164;"	d
+MRX_FLT_TB3_I_MSK	include/ssv6200_aux.h	6987;"	d
+MRX_FLT_TB3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6162;"	d
+MRX_FLT_TB3_MSK	include/ssv6200_aux.h	6986;"	d
+MRX_FLT_TB3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6161;"	d
+MRX_FLT_TB3_SFT	include/ssv6200_aux.h	6988;"	d
+MRX_FLT_TB3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6163;"	d
+MRX_FLT_TB3_SZ	include/ssv6200_aux.h	6990;"	d
+MRX_FLT_TB3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6165;"	d
+MRX_FLT_TB4_HI	include/ssv6200_aux.h	6994;"	d
+MRX_FLT_TB4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6169;"	d
+MRX_FLT_TB4_I_MSK	include/ssv6200_aux.h	6992;"	d
+MRX_FLT_TB4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6167;"	d
+MRX_FLT_TB4_MSK	include/ssv6200_aux.h	6991;"	d
+MRX_FLT_TB4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6166;"	d
+MRX_FLT_TB4_SFT	include/ssv6200_aux.h	6993;"	d
+MRX_FLT_TB4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6168;"	d
+MRX_FLT_TB4_SZ	include/ssv6200_aux.h	6995;"	d
+MRX_FLT_TB4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6170;"	d
+MRX_FLT_TB5_HI	include/ssv6200_aux.h	6999;"	d
+MRX_FLT_TB5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6174;"	d
+MRX_FLT_TB5_I_MSK	include/ssv6200_aux.h	6997;"	d
+MRX_FLT_TB5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6172;"	d
+MRX_FLT_TB5_MSK	include/ssv6200_aux.h	6996;"	d
+MRX_FLT_TB5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6171;"	d
+MRX_FLT_TB5_SFT	include/ssv6200_aux.h	6998;"	d
+MRX_FLT_TB5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6173;"	d
+MRX_FLT_TB5_SZ	include/ssv6200_aux.h	7000;"	d
+MRX_FLT_TB5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6175;"	d
+MRX_FLT_TB6_HI	include/ssv6200_aux.h	7004;"	d
+MRX_FLT_TB6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6179;"	d
+MRX_FLT_TB6_I_MSK	include/ssv6200_aux.h	7002;"	d
+MRX_FLT_TB6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6177;"	d
+MRX_FLT_TB6_MSK	include/ssv6200_aux.h	7001;"	d
+MRX_FLT_TB6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6176;"	d
+MRX_FLT_TB6_SFT	include/ssv6200_aux.h	7003;"	d
+MRX_FLT_TB6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6178;"	d
+MRX_FLT_TB6_SZ	include/ssv6200_aux.h	7005;"	d
+MRX_FLT_TB6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6180;"	d
+MRX_FLT_TB7_HI	include/ssv6200_aux.h	7009;"	d
+MRX_FLT_TB7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6184;"	d
+MRX_FLT_TB7_I_MSK	include/ssv6200_aux.h	7007;"	d
+MRX_FLT_TB7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6182;"	d
+MRX_FLT_TB7_MSK	include/ssv6200_aux.h	7006;"	d
+MRX_FLT_TB7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6181;"	d
+MRX_FLT_TB7_SFT	include/ssv6200_aux.h	7008;"	d
+MRX_FLT_TB7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6183;"	d
+MRX_FLT_TB7_SZ	include/ssv6200_aux.h	7010;"	d
+MRX_FLT_TB7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6185;"	d
+MRX_FLT_TB8_HI	include/ssv6200_aux.h	7014;"	d
+MRX_FLT_TB8_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6189;"	d
+MRX_FLT_TB8_I_MSK	include/ssv6200_aux.h	7012;"	d
+MRX_FLT_TB8_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6187;"	d
+MRX_FLT_TB8_MSK	include/ssv6200_aux.h	7011;"	d
+MRX_FLT_TB8_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6186;"	d
+MRX_FLT_TB8_SFT	include/ssv6200_aux.h	7013;"	d
+MRX_FLT_TB8_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6188;"	d
+MRX_FLT_TB8_SZ	include/ssv6200_aux.h	7015;"	d
+MRX_FLT_TB8_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6190;"	d
+MRX_FLT_TB9_HI	include/ssv6200_aux.h	7019;"	d
+MRX_FLT_TB9_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6194;"	d
+MRX_FLT_TB9_I_MSK	include/ssv6200_aux.h	7017;"	d
+MRX_FLT_TB9_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6192;"	d
+MRX_FLT_TB9_MSK	include/ssv6200_aux.h	7016;"	d
+MRX_FLT_TB9_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6191;"	d
+MRX_FLT_TB9_SFT	include/ssv6200_aux.h	7018;"	d
+MRX_FLT_TB9_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6193;"	d
+MRX_FLT_TB9_SZ	include/ssv6200_aux.h	7020;"	d
+MRX_FLT_TB9_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6195;"	d
+MRX_FRG_HI	include/ssv6200_aux.h	9499;"	d
+MRX_FRG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9334;"	d
+MRX_FRG_I_MSK	include/ssv6200_aux.h	9497;"	d
+MRX_FRG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9332;"	d
+MRX_FRG_MSK	include/ssv6200_aux.h	9496;"	d
+MRX_FRG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9331;"	d
+MRX_FRG_SFT	include/ssv6200_aux.h	9498;"	d
+MRX_FRG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9333;"	d
+MRX_FRG_SZ	include/ssv6200_aux.h	9500;"	d
+MRX_FRG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9335;"	d
+MRX_GRP_HI	include/ssv6200_aux.h	9504;"	d
+MRX_GRP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9339;"	d
+MRX_GRP_I_MSK	include/ssv6200_aux.h	9502;"	d
+MRX_GRP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9337;"	d
+MRX_GRP_MSK	include/ssv6200_aux.h	9501;"	d
+MRX_GRP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9336;"	d
+MRX_GRP_SFT	include/ssv6200_aux.h	9503;"	d
+MRX_GRP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9338;"	d
+MRX_GRP_SZ	include/ssv6200_aux.h	9505;"	d
+MRX_GRP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9340;"	d
+MRX_LEN_FLT_HI	include/ssv6200_aux.h	7099;"	d
+MRX_LEN_FLT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6274;"	d
+MRX_LEN_FLT_I_MSK	include/ssv6200_aux.h	7097;"	d
+MRX_LEN_FLT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6272;"	d
+MRX_LEN_FLT_MSK	include/ssv6200_aux.h	7096;"	d
+MRX_LEN_FLT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6271;"	d
+MRX_LEN_FLT_SFT	include/ssv6200_aux.h	7098;"	d
+MRX_LEN_FLT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6273;"	d
+MRX_LEN_FLT_SZ	include/ssv6200_aux.h	7100;"	d
+MRX_LEN_FLT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6275;"	d
+MRX_MB_MISS_HI	include/ssv6200_aux.h	9574;"	d
+MRX_MB_MISS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9409;"	d
+MRX_MB_MISS_I_MSK	include/ssv6200_aux.h	9572;"	d
+MRX_MB_MISS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9407;"	d
+MRX_MB_MISS_MSK	include/ssv6200_aux.h	9571;"	d
+MRX_MB_MISS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9406;"	d
+MRX_MB_MISS_SFT	include/ssv6200_aux.h	9573;"	d
+MRX_MB_MISS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9408;"	d
+MRX_MB_MISS_SZ	include/ssv6200_aux.h	9575;"	d
+MRX_MB_MISS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9410;"	d
+MRX_MCAST_CTRL_0_HI	include/ssv6200_aux.h	6879;"	d
+MRX_MCAST_CTRL_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6054;"	d
+MRX_MCAST_CTRL_0_I_MSK	include/ssv6200_aux.h	6877;"	d
+MRX_MCAST_CTRL_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6052;"	d
+MRX_MCAST_CTRL_0_MSK	include/ssv6200_aux.h	6876;"	d
+MRX_MCAST_CTRL_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6051;"	d
+MRX_MCAST_CTRL_0_SFT	include/ssv6200_aux.h	6878;"	d
+MRX_MCAST_CTRL_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6053;"	d
+MRX_MCAST_CTRL_0_SZ	include/ssv6200_aux.h	6880;"	d
+MRX_MCAST_CTRL_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6055;"	d
+MRX_MCAST_CTRL_1_HI	include/ssv6200_aux.h	6904;"	d
+MRX_MCAST_CTRL_1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6079;"	d
+MRX_MCAST_CTRL_1_I_MSK	include/ssv6200_aux.h	6902;"	d
+MRX_MCAST_CTRL_1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6077;"	d
+MRX_MCAST_CTRL_1_MSK	include/ssv6200_aux.h	6901;"	d
+MRX_MCAST_CTRL_1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6076;"	d
+MRX_MCAST_CTRL_1_SFT	include/ssv6200_aux.h	6903;"	d
+MRX_MCAST_CTRL_1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6078;"	d
+MRX_MCAST_CTRL_1_SZ	include/ssv6200_aux.h	6905;"	d
+MRX_MCAST_CTRL_1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6080;"	d
+MRX_MCAST_CTRL_2_HI	include/ssv6200_aux.h	6929;"	d
+MRX_MCAST_CTRL_2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6104;"	d
+MRX_MCAST_CTRL_2_I_MSK	include/ssv6200_aux.h	6927;"	d
+MRX_MCAST_CTRL_2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6102;"	d
+MRX_MCAST_CTRL_2_MSK	include/ssv6200_aux.h	6926;"	d
+MRX_MCAST_CTRL_2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6101;"	d
+MRX_MCAST_CTRL_2_SFT	include/ssv6200_aux.h	6928;"	d
+MRX_MCAST_CTRL_2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6103;"	d
+MRX_MCAST_CTRL_2_SZ	include/ssv6200_aux.h	6930;"	d
+MRX_MCAST_CTRL_2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6105;"	d
+MRX_MCAST_CTRL_3_HI	include/ssv6200_aux.h	6954;"	d
+MRX_MCAST_CTRL_3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6129;"	d
+MRX_MCAST_CTRL_3_I_MSK	include/ssv6200_aux.h	6952;"	d
+MRX_MCAST_CTRL_3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6127;"	d
+MRX_MCAST_CTRL_3_MSK	include/ssv6200_aux.h	6951;"	d
+MRX_MCAST_CTRL_3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6126;"	d
+MRX_MCAST_CTRL_3_SFT	include/ssv6200_aux.h	6953;"	d
+MRX_MCAST_CTRL_3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6128;"	d
+MRX_MCAST_CTRL_3_SZ	include/ssv6200_aux.h	6955;"	d
+MRX_MCAST_CTRL_3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6130;"	d
+MRX_MCAST_MASK0_31_0_HI	include/ssv6200_aux.h	6869;"	d
+MRX_MCAST_MASK0_31_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6044;"	d
+MRX_MCAST_MASK0_31_0_I_MSK	include/ssv6200_aux.h	6867;"	d
+MRX_MCAST_MASK0_31_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6042;"	d
+MRX_MCAST_MASK0_31_0_MSK	include/ssv6200_aux.h	6866;"	d
+MRX_MCAST_MASK0_31_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6041;"	d
+MRX_MCAST_MASK0_31_0_SFT	include/ssv6200_aux.h	6868;"	d
+MRX_MCAST_MASK0_31_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6043;"	d
+MRX_MCAST_MASK0_31_0_SZ	include/ssv6200_aux.h	6870;"	d
+MRX_MCAST_MASK0_31_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6045;"	d
+MRX_MCAST_MASK0_47_32_HI	include/ssv6200_aux.h	6874;"	d
+MRX_MCAST_MASK0_47_32_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6049;"	d
+MRX_MCAST_MASK0_47_32_I_MSK	include/ssv6200_aux.h	6872;"	d
+MRX_MCAST_MASK0_47_32_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6047;"	d
+MRX_MCAST_MASK0_47_32_MSK	include/ssv6200_aux.h	6871;"	d
+MRX_MCAST_MASK0_47_32_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6046;"	d
+MRX_MCAST_MASK0_47_32_SFT	include/ssv6200_aux.h	6873;"	d
+MRX_MCAST_MASK0_47_32_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6048;"	d
+MRX_MCAST_MASK0_47_32_SZ	include/ssv6200_aux.h	6875;"	d
+MRX_MCAST_MASK0_47_32_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6050;"	d
+MRX_MCAST_MASK1_31_0_HI	include/ssv6200_aux.h	6894;"	d
+MRX_MCAST_MASK1_31_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6069;"	d
+MRX_MCAST_MASK1_31_0_I_MSK	include/ssv6200_aux.h	6892;"	d
+MRX_MCAST_MASK1_31_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6067;"	d
+MRX_MCAST_MASK1_31_0_MSK	include/ssv6200_aux.h	6891;"	d
+MRX_MCAST_MASK1_31_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6066;"	d
+MRX_MCAST_MASK1_31_0_SFT	include/ssv6200_aux.h	6893;"	d
+MRX_MCAST_MASK1_31_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6068;"	d
+MRX_MCAST_MASK1_31_0_SZ	include/ssv6200_aux.h	6895;"	d
+MRX_MCAST_MASK1_31_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6070;"	d
+MRX_MCAST_MASK1_47_32_HI	include/ssv6200_aux.h	6899;"	d
+MRX_MCAST_MASK1_47_32_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6074;"	d
+MRX_MCAST_MASK1_47_32_I_MSK	include/ssv6200_aux.h	6897;"	d
+MRX_MCAST_MASK1_47_32_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6072;"	d
+MRX_MCAST_MASK1_47_32_MSK	include/ssv6200_aux.h	6896;"	d
+MRX_MCAST_MASK1_47_32_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6071;"	d
+MRX_MCAST_MASK1_47_32_SFT	include/ssv6200_aux.h	6898;"	d
+MRX_MCAST_MASK1_47_32_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6073;"	d
+MRX_MCAST_MASK1_47_32_SZ	include/ssv6200_aux.h	6900;"	d
+MRX_MCAST_MASK1_47_32_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6075;"	d
+MRX_MCAST_MASK2_31_0_HI	include/ssv6200_aux.h	6919;"	d
+MRX_MCAST_MASK2_31_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6094;"	d
+MRX_MCAST_MASK2_31_0_I_MSK	include/ssv6200_aux.h	6917;"	d
+MRX_MCAST_MASK2_31_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6092;"	d
+MRX_MCAST_MASK2_31_0_MSK	include/ssv6200_aux.h	6916;"	d
+MRX_MCAST_MASK2_31_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6091;"	d
+MRX_MCAST_MASK2_31_0_SFT	include/ssv6200_aux.h	6918;"	d
+MRX_MCAST_MASK2_31_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6093;"	d
+MRX_MCAST_MASK2_31_0_SZ	include/ssv6200_aux.h	6920;"	d
+MRX_MCAST_MASK2_31_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6095;"	d
+MRX_MCAST_MASK2_47_32_HI	include/ssv6200_aux.h	6924;"	d
+MRX_MCAST_MASK2_47_32_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6099;"	d
+MRX_MCAST_MASK2_47_32_I_MSK	include/ssv6200_aux.h	6922;"	d
+MRX_MCAST_MASK2_47_32_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6097;"	d
+MRX_MCAST_MASK2_47_32_MSK	include/ssv6200_aux.h	6921;"	d
+MRX_MCAST_MASK2_47_32_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6096;"	d
+MRX_MCAST_MASK2_47_32_SFT	include/ssv6200_aux.h	6923;"	d
+MRX_MCAST_MASK2_47_32_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6098;"	d
+MRX_MCAST_MASK2_47_32_SZ	include/ssv6200_aux.h	6925;"	d
+MRX_MCAST_MASK2_47_32_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6100;"	d
+MRX_MCAST_MASK3_31_0_HI	include/ssv6200_aux.h	6944;"	d
+MRX_MCAST_MASK3_31_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6119;"	d
+MRX_MCAST_MASK3_31_0_I_MSK	include/ssv6200_aux.h	6942;"	d
+MRX_MCAST_MASK3_31_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6117;"	d
+MRX_MCAST_MASK3_31_0_MSK	include/ssv6200_aux.h	6941;"	d
+MRX_MCAST_MASK3_31_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6116;"	d
+MRX_MCAST_MASK3_31_0_SFT	include/ssv6200_aux.h	6943;"	d
+MRX_MCAST_MASK3_31_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6118;"	d
+MRX_MCAST_MASK3_31_0_SZ	include/ssv6200_aux.h	6945;"	d
+MRX_MCAST_MASK3_31_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6120;"	d
+MRX_MCAST_MASK3_47_32_HI	include/ssv6200_aux.h	6949;"	d
+MRX_MCAST_MASK3_47_32_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6124;"	d
+MRX_MCAST_MASK3_47_32_I_MSK	include/ssv6200_aux.h	6947;"	d
+MRX_MCAST_MASK3_47_32_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6122;"	d
+MRX_MCAST_MASK3_47_32_MSK	include/ssv6200_aux.h	6946;"	d
+MRX_MCAST_MASK3_47_32_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6121;"	d
+MRX_MCAST_MASK3_47_32_SFT	include/ssv6200_aux.h	6948;"	d
+MRX_MCAST_MASK3_47_32_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6123;"	d
+MRX_MCAST_MASK3_47_32_SZ	include/ssv6200_aux.h	6950;"	d
+MRX_MCAST_MASK3_47_32_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6125;"	d
+MRX_MCAST_TB0_31_0_HI	include/ssv6200_aux.h	6859;"	d
+MRX_MCAST_TB0_31_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6034;"	d
+MRX_MCAST_TB0_31_0_I_MSK	include/ssv6200_aux.h	6857;"	d
+MRX_MCAST_TB0_31_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6032;"	d
+MRX_MCAST_TB0_31_0_MSK	include/ssv6200_aux.h	6856;"	d
+MRX_MCAST_TB0_31_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6031;"	d
+MRX_MCAST_TB0_31_0_SFT	include/ssv6200_aux.h	6858;"	d
+MRX_MCAST_TB0_31_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6033;"	d
+MRX_MCAST_TB0_31_0_SZ	include/ssv6200_aux.h	6860;"	d
+MRX_MCAST_TB0_31_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6035;"	d
+MRX_MCAST_TB0_47_32_HI	include/ssv6200_aux.h	6864;"	d
+MRX_MCAST_TB0_47_32_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6039;"	d
+MRX_MCAST_TB0_47_32_I_MSK	include/ssv6200_aux.h	6862;"	d
+MRX_MCAST_TB0_47_32_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6037;"	d
+MRX_MCAST_TB0_47_32_MSK	include/ssv6200_aux.h	6861;"	d
+MRX_MCAST_TB0_47_32_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6036;"	d
+MRX_MCAST_TB0_47_32_SFT	include/ssv6200_aux.h	6863;"	d
+MRX_MCAST_TB0_47_32_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6038;"	d
+MRX_MCAST_TB0_47_32_SZ	include/ssv6200_aux.h	6865;"	d
+MRX_MCAST_TB0_47_32_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6040;"	d
+MRX_MCAST_TB1_31_0_HI	include/ssv6200_aux.h	6884;"	d
+MRX_MCAST_TB1_31_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6059;"	d
+MRX_MCAST_TB1_31_0_I_MSK	include/ssv6200_aux.h	6882;"	d
+MRX_MCAST_TB1_31_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6057;"	d
+MRX_MCAST_TB1_31_0_MSK	include/ssv6200_aux.h	6881;"	d
+MRX_MCAST_TB1_31_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6056;"	d
+MRX_MCAST_TB1_31_0_SFT	include/ssv6200_aux.h	6883;"	d
+MRX_MCAST_TB1_31_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6058;"	d
+MRX_MCAST_TB1_31_0_SZ	include/ssv6200_aux.h	6885;"	d
+MRX_MCAST_TB1_31_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6060;"	d
+MRX_MCAST_TB1_47_32_HI	include/ssv6200_aux.h	6889;"	d
+MRX_MCAST_TB1_47_32_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6064;"	d
+MRX_MCAST_TB1_47_32_I_MSK	include/ssv6200_aux.h	6887;"	d
+MRX_MCAST_TB1_47_32_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6062;"	d
+MRX_MCAST_TB1_47_32_MSK	include/ssv6200_aux.h	6886;"	d
+MRX_MCAST_TB1_47_32_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6061;"	d
+MRX_MCAST_TB1_47_32_SFT	include/ssv6200_aux.h	6888;"	d
+MRX_MCAST_TB1_47_32_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6063;"	d
+MRX_MCAST_TB1_47_32_SZ	include/ssv6200_aux.h	6890;"	d
+MRX_MCAST_TB1_47_32_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6065;"	d
+MRX_MCAST_TB2_31_0_HI	include/ssv6200_aux.h	6909;"	d
+MRX_MCAST_TB2_31_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6084;"	d
+MRX_MCAST_TB2_31_0_I_MSK	include/ssv6200_aux.h	6907;"	d
+MRX_MCAST_TB2_31_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6082;"	d
+MRX_MCAST_TB2_31_0_MSK	include/ssv6200_aux.h	6906;"	d
+MRX_MCAST_TB2_31_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6081;"	d
+MRX_MCAST_TB2_31_0_SFT	include/ssv6200_aux.h	6908;"	d
+MRX_MCAST_TB2_31_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6083;"	d
+MRX_MCAST_TB2_31_0_SZ	include/ssv6200_aux.h	6910;"	d
+MRX_MCAST_TB2_31_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6085;"	d
+MRX_MCAST_TB2_47_32_HI	include/ssv6200_aux.h	6914;"	d
+MRX_MCAST_TB2_47_32_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6089;"	d
+MRX_MCAST_TB2_47_32_I_MSK	include/ssv6200_aux.h	6912;"	d
+MRX_MCAST_TB2_47_32_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6087;"	d
+MRX_MCAST_TB2_47_32_MSK	include/ssv6200_aux.h	6911;"	d
+MRX_MCAST_TB2_47_32_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6086;"	d
+MRX_MCAST_TB2_47_32_SFT	include/ssv6200_aux.h	6913;"	d
+MRX_MCAST_TB2_47_32_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6088;"	d
+MRX_MCAST_TB2_47_32_SZ	include/ssv6200_aux.h	6915;"	d
+MRX_MCAST_TB2_47_32_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6090;"	d
+MRX_MCAST_TB3_31_0_HI	include/ssv6200_aux.h	6934;"	d
+MRX_MCAST_TB3_31_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6109;"	d
+MRX_MCAST_TB3_31_0_I_MSK	include/ssv6200_aux.h	6932;"	d
+MRX_MCAST_TB3_31_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6107;"	d
+MRX_MCAST_TB3_31_0_MSK	include/ssv6200_aux.h	6931;"	d
+MRX_MCAST_TB3_31_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6106;"	d
+MRX_MCAST_TB3_31_0_SFT	include/ssv6200_aux.h	6933;"	d
+MRX_MCAST_TB3_31_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6108;"	d
+MRX_MCAST_TB3_31_0_SZ	include/ssv6200_aux.h	6935;"	d
+MRX_MCAST_TB3_31_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6110;"	d
+MRX_MCAST_TB3_47_32_HI	include/ssv6200_aux.h	6939;"	d
+MRX_MCAST_TB3_47_32_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6114;"	d
+MRX_MCAST_TB3_47_32_I_MSK	include/ssv6200_aux.h	6937;"	d
+MRX_MCAST_TB3_47_32_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6112;"	d
+MRX_MCAST_TB3_47_32_MSK	include/ssv6200_aux.h	6936;"	d
+MRX_MCAST_TB3_47_32_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6111;"	d
+MRX_MCAST_TB3_47_32_SFT	include/ssv6200_aux.h	6938;"	d
+MRX_MCAST_TB3_47_32_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6113;"	d
+MRX_MCAST_TB3_47_32_SZ	include/ssv6200_aux.h	6940;"	d
+MRX_MCAST_TB3_47_32_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6115;"	d
+MRX_MISS_HI	include/ssv6200_aux.h	9519;"	d
+MRX_MISS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9354;"	d
+MRX_MISS_I_MSK	include/ssv6200_aux.h	9517;"	d
+MRX_MISS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9352;"	d
+MRX_MISS_MSK	include/ssv6200_aux.h	9516;"	d
+MRX_MISS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9351;"	d
+MRX_MISS_SFT	include/ssv6200_aux.h	9518;"	d
+MRX_MISS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9353;"	d
+MRX_MISS_SZ	include/ssv6200_aux.h	9520;"	d
+MRX_MISS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9355;"	d
+MRX_MNG_NTF_HI	include/ssv6200_aux.h	9559;"	d
+MRX_MNG_NTF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9394;"	d
+MRX_MNG_NTF_I_MSK	include/ssv6200_aux.h	9557;"	d
+MRX_MNG_NTF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9392;"	d
+MRX_MNG_NTF_MSK	include/ssv6200_aux.h	9556;"	d
+MRX_MNG_NTF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9391;"	d
+MRX_MNG_NTF_SFT	include/ssv6200_aux.h	9558;"	d
+MRX_MNG_NTF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9393;"	d
+MRX_MNG_NTF_SZ	include/ssv6200_aux.h	9560;"	d
+MRX_MNG_NTF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9395;"	d
+MRX_MODE_NORMAL	smac/dev.h	43;"	d
+MRX_MODE_PROMISCUOUS	smac/dev.h	42;"	d
+MRX_NIDLE_MISS_HI	include/ssv6200_aux.h	9579;"	d
+MRX_NIDLE_MISS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9414;"	d
+MRX_NIDLE_MISS_I_MSK	include/ssv6200_aux.h	9577;"	d
+MRX_NIDLE_MISS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9412;"	d
+MRX_NIDLE_MISS_MSK	include/ssv6200_aux.h	9576;"	d
+MRX_NIDLE_MISS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9411;"	d
+MRX_NIDLE_MISS_SFT	include/ssv6200_aux.h	9578;"	d
+MRX_NIDLE_MISS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9413;"	d
+MRX_NIDLE_MISS_SZ	include/ssv6200_aux.h	9580;"	d
+MRX_NIDLE_MISS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9415;"	d
+MRX_PHY_INFO_HI	include/ssv6200_aux.h	6959;"	d
+MRX_PHY_INFO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6134;"	d
+MRX_PHY_INFO_I_MSK	include/ssv6200_aux.h	6957;"	d
+MRX_PHY_INFO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6132;"	d
+MRX_PHY_INFO_MSK	include/ssv6200_aux.h	6956;"	d
+MRX_PHY_INFO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6131;"	d
+MRX_PHY_INFO_SFT	include/ssv6200_aux.h	6958;"	d
+MRX_PHY_INFO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6133;"	d
+MRX_PHY_INFO_SZ	include/ssv6200_aux.h	6960;"	d
+MRX_PHY_INFO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6135;"	d
+MRX_REG_BANK_SIZE	include/ssv6200_reg.h	95;"	d
+MRX_REG_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	114;"	d
+MRX_REG_BASE	include/ssv6200_reg.h	46;"	d
+MRX_REG_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	53;"	d
+MRX_RTS_NTF_HI	include/ssv6200_aux.h	9534;"	d
+MRX_RTS_NTF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9369;"	d
+MRX_RTS_NTF_I_MSK	include/ssv6200_aux.h	9532;"	d
+MRX_RTS_NTF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9367;"	d
+MRX_RTS_NTF_MSK	include/ssv6200_aux.h	9531;"	d
+MRX_RTS_NTF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9366;"	d
+MRX_RTS_NTF_SFT	include/ssv6200_aux.h	9533;"	d
+MRX_RTS_NTF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9368;"	d
+MRX_RTS_NTF_SZ	include/ssv6200_aux.h	9535;"	d
+MRX_RTS_NTF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9370;"	d
+MRX_RX_EN_HI	include/ssv6200_aux.h	7734;"	d
+MRX_RX_EN_I_MSK	include/ssv6200_aux.h	7732;"	d
+MRX_RX_EN_MSK	include/ssv6200_aux.h	7731;"	d
+MRX_RX_EN_SFT	include/ssv6200_aux.h	7733;"	d
+MRX_RX_EN_SZ	include/ssv6200_aux.h	7735;"	d
+MRX_STP_EN_HI	include/ssv6200_aux.h	7119;"	d
+MRX_STP_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6294;"	d
+MRX_STP_EN_I_MSK	include/ssv6200_aux.h	7117;"	d
+MRX_STP_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6292;"	d
+MRX_STP_EN_MSK	include/ssv6200_aux.h	7116;"	d
+MRX_STP_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6291;"	d
+MRX_STP_EN_SFT	include/ssv6200_aux.h	7118;"	d
+MRX_STP_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6293;"	d
+MRX_STP_EN_SZ	include/ssv6200_aux.h	7120;"	d
+MRX_STP_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6295;"	d
+MRX_STP_OFST_HI	include/ssv6200_aux.h	7124;"	d
+MRX_STP_OFST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6299;"	d
+MRX_STP_OFST_I_MSK	include/ssv6200_aux.h	7122;"	d
+MRX_STP_OFST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6297;"	d
+MRX_STP_OFST_MSK	include/ssv6200_aux.h	7121;"	d
+MRX_STP_OFST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6296;"	d
+MRX_STP_OFST_SFT	include/ssv6200_aux.h	7123;"	d
+MRX_STP_OFST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6298;"	d
+MRX_STP_OFST_SZ	include/ssv6200_aux.h	7125;"	d
+MRX_STP_OFST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6300;"	d
+MRX_SW_RST_HI	include/ssv6200_aux.h	8829;"	d
+MRX_SW_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8584;"	d
+MRX_SW_RST_I_MSK	include/ssv6200_aux.h	8827;"	d
+MRX_SW_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8582;"	d
+MRX_SW_RST_MSK	include/ssv6200_aux.h	8826;"	d
+MRX_SW_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8581;"	d
+MRX_SW_RST_SFT	include/ssv6200_aux.h	8828;"	d
+MRX_SW_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8583;"	d
+MRX_SW_RST_SZ	include/ssv6200_aux.h	8830;"	d
+MRX_SW_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8585;"	d
+MRX_WD_HI	include/ssv6200_aux.h	7204;"	d
+MRX_WD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6379;"	d
+MRX_WD_I_MSK	include/ssv6200_aux.h	7202;"	d
+MRX_WD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6377;"	d
+MRX_WD_MSK	include/ssv6200_aux.h	7201;"	d
+MRX_WD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6376;"	d
+MRX_WD_SFT	include/ssv6200_aux.h	7203;"	d
+MRX_WD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6378;"	d
+MRX_WD_SZ	include/ssv6200_aux.h	7205;"	d
+MRX_WD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6380;"	d
+MS0TMR_CLK_EN_HI	include/ssv6200_aux.h	269;"	d
+MS0TMR_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1219;"	d
+MS0TMR_CLK_EN_I_MSK	include/ssv6200_aux.h	267;"	d
+MS0TMR_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1217;"	d
+MS0TMR_CLK_EN_MSK	include/ssv6200_aux.h	266;"	d
+MS0TMR_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1216;"	d
+MS0TMR_CLK_EN_SFT	include/ssv6200_aux.h	268;"	d
+MS0TMR_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1218;"	d
+MS0TMR_CLK_EN_SZ	include/ssv6200_aux.h	270;"	d
+MS0TMR_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1220;"	d
+MS0TMR_SW_RST_HI	include/ssv6200_aux.h	99;"	d
+MS0TMR_SW_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1049;"	d
+MS0TMR_SW_RST_I_MSK	include/ssv6200_aux.h	97;"	d
+MS0TMR_SW_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1047;"	d
+MS0TMR_SW_RST_MSK	include/ssv6200_aux.h	96;"	d
+MS0TMR_SW_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1046;"	d
+MS0TMR_SW_RST_SFT	include/ssv6200_aux.h	98;"	d
+MS0TMR_SW_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1048;"	d
+MS0TMR_SW_RST_SZ	include/ssv6200_aux.h	100;"	d
+MS0TMR_SW_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1050;"	d
+MS1TMR_CLK_EN_HI	include/ssv6200_aux.h	274;"	d
+MS1TMR_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1224;"	d
+MS1TMR_CLK_EN_I_MSK	include/ssv6200_aux.h	272;"	d
+MS1TMR_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1222;"	d
+MS1TMR_CLK_EN_MSK	include/ssv6200_aux.h	271;"	d
+MS1TMR_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1221;"	d
+MS1TMR_CLK_EN_SFT	include/ssv6200_aux.h	273;"	d
+MS1TMR_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1223;"	d
+MS1TMR_CLK_EN_SZ	include/ssv6200_aux.h	275;"	d
+MS1TMR_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1225;"	d
+MS1TMR_SW_RST_HI	include/ssv6200_aux.h	104;"	d
+MS1TMR_SW_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1054;"	d
+MS1TMR_SW_RST_I_MSK	include/ssv6200_aux.h	102;"	d
+MS1TMR_SW_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1052;"	d
+MS1TMR_SW_RST_MSK	include/ssv6200_aux.h	101;"	d
+MS1TMR_SW_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1051;"	d
+MS1TMR_SW_RST_SFT	include/ssv6200_aux.h	103;"	d
+MS1TMR_SW_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1053;"	d
+MS1TMR_SW_RST_SZ	include/ssv6200_aux.h	105;"	d
+MS1TMR_SW_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1055;"	d
+MS2TMR_CLK_EN_HI	include/ssv6200_aux.h	279;"	d
+MS2TMR_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1229;"	d
+MS2TMR_CLK_EN_I_MSK	include/ssv6200_aux.h	277;"	d
+MS2TMR_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1227;"	d
+MS2TMR_CLK_EN_MSK	include/ssv6200_aux.h	276;"	d
+MS2TMR_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1226;"	d
+MS2TMR_CLK_EN_SFT	include/ssv6200_aux.h	278;"	d
+MS2TMR_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1228;"	d
+MS2TMR_CLK_EN_SZ	include/ssv6200_aux.h	280;"	d
+MS2TMR_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1230;"	d
+MS2TMR_SW_RST_HI	include/ssv6200_aux.h	109;"	d
+MS2TMR_SW_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1059;"	d
+MS2TMR_SW_RST_I_MSK	include/ssv6200_aux.h	107;"	d
+MS2TMR_SW_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1057;"	d
+MS2TMR_SW_RST_MSK	include/ssv6200_aux.h	106;"	d
+MS2TMR_SW_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1056;"	d
+MS2TMR_SW_RST_SFT	include/ssv6200_aux.h	108;"	d
+MS2TMR_SW_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1058;"	d
+MS2TMR_SW_RST_SZ	include/ssv6200_aux.h	110;"	d
+MS2TMR_SW_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1060;"	d
+MS3TMR_CLK_EN_HI	include/ssv6200_aux.h	284;"	d
+MS3TMR_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1234;"	d
+MS3TMR_CLK_EN_I_MSK	include/ssv6200_aux.h	282;"	d
+MS3TMR_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1232;"	d
+MS3TMR_CLK_EN_MSK	include/ssv6200_aux.h	281;"	d
+MS3TMR_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1231;"	d
+MS3TMR_CLK_EN_SFT	include/ssv6200_aux.h	283;"	d
+MS3TMR_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1233;"	d
+MS3TMR_CLK_EN_SZ	include/ssv6200_aux.h	285;"	d
+MS3TMR_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1235;"	d
+MS3TMR_SW_RST_HI	include/ssv6200_aux.h	114;"	d
+MS3TMR_SW_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1064;"	d
+MS3TMR_SW_RST_I_MSK	include/ssv6200_aux.h	112;"	d
+MS3TMR_SW_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1062;"	d
+MS3TMR_SW_RST_MSK	include/ssv6200_aux.h	111;"	d
+MS3TMR_SW_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1061;"	d
+MS3TMR_SW_RST_SFT	include/ssv6200_aux.h	113;"	d
+MS3TMR_SW_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1063;"	d
+MS3TMR_SW_RST_SZ	include/ssv6200_aux.h	115;"	d
+MS3TMR_SW_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1065;"	d
+MSLEEP	smac/hal/ssv6006c/ssv6006_priv.h	25;"	d
+MSLEEP	smac/hal/ssv6006c/turismo_common.h	306;"	d
+MTX_ACK_DUR0_HI	include/ssv6200_aux.h	7529;"	d
+MTX_ACK_DUR0_I_MSK	include/ssv6200_aux.h	7527;"	d
+MTX_ACK_DUR0_MSK	include/ssv6200_aux.h	7526;"	d
+MTX_ACK_DUR0_SFT	include/ssv6200_aux.h	7528;"	d
+MTX_ACK_DUR0_SZ	include/ssv6200_aux.h	7530;"	d
+MTX_ACK_FAIL_HI	include/ssv6200_aux.h	9474;"	d
+MTX_ACK_FAIL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9309;"	d
+MTX_ACK_FAIL_I_MSK	include/ssv6200_aux.h	9472;"	d
+MTX_ACK_FAIL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9307;"	d
+MTX_ACK_FAIL_MSK	include/ssv6200_aux.h	9471;"	d
+MTX_ACK_FAIL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9306;"	d
+MTX_ACK_FAIL_SFT	include/ssv6200_aux.h	9473;"	d
+MTX_ACK_FAIL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9308;"	d
+MTX_ACK_FAIL_SZ	include/ssv6200_aux.h	9475;"	d
+MTX_ACK_FAIL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9310;"	d
+MTX_ACK_TX_HI	include/ssv6200_aux.h	9484;"	d
+MTX_ACK_TX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9319;"	d
+MTX_ACK_TX_I_MSK	include/ssv6200_aux.h	9482;"	d
+MTX_ACK_TX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9317;"	d
+MTX_ACK_TX_MSK	include/ssv6200_aux.h	9481;"	d
+MTX_ACK_TX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9316;"	d
+MTX_ACK_TX_SFT	include/ssv6200_aux.h	9483;"	d
+MTX_ACK_TX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9318;"	d
+MTX_ACK_TX_SZ	include/ssv6200_aux.h	9485;"	d
+MTX_ACK_TX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9320;"	d
+MTX_AMPDU_CRC8_AUTO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6689;"	d
+MTX_AMPDU_CRC8_AUTO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6687;"	d
+MTX_AMPDU_CRC8_AUTO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6686;"	d
+MTX_AMPDU_CRC8_AUTO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6688;"	d
+MTX_AMPDU_CRC8_AUTO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6690;"	d
+MTX_AMPDU_CRC_AUTO_HI	include/ssv6200_aux.h	7514;"	d
+MTX_AMPDU_CRC_AUTO_I_MSK	include/ssv6200_aux.h	7512;"	d
+MTX_AMPDU_CRC_AUTO_MSK	include/ssv6200_aux.h	7511;"	d
+MTX_AMPDU_CRC_AUTO_SFT	include/ssv6200_aux.h	7513;"	d
+MTX_AMPDU_CRC_AUTO_SZ	include/ssv6200_aux.h	7515;"	d
+MTX_AMPDU_SET_DIF_HI	include/ssv6200_aux.h	7574;"	d
+MTX_AMPDU_SET_DIF_I_MSK	include/ssv6200_aux.h	7572;"	d
+MTX_AMPDU_SET_DIF_MSK	include/ssv6200_aux.h	7571;"	d
+MTX_AMPDU_SET_DIF_SFT	include/ssv6200_aux.h	7573;"	d
+MTX_AMPDU_SET_DIF_SZ	include/ssv6200_aux.h	7575;"	d
+MTX_AUTO_BCN_ONGOING_HI	include/ssv6200_aux.h	7644;"	d
+MTX_AUTO_BCN_ONGOING_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7289;"	d
+MTX_AUTO_BCN_ONGOING_I_MSK	include/ssv6200_aux.h	7642;"	d
+MTX_AUTO_BCN_ONGOING_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7287;"	d
+MTX_AUTO_BCN_ONGOING_MSK	include/ssv6200_aux.h	7641;"	d
+MTX_AUTO_BCN_ONGOING_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7286;"	d
+MTX_AUTO_BCN_ONGOING_SFT	include/ssv6200_aux.h	7643;"	d
+MTX_AUTO_BCN_ONGOING_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7288;"	d
+MTX_AUTO_BCN_ONGOING_SZ	include/ssv6200_aux.h	7645;"	d
+MTX_AUTO_BCN_ONGOING_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7290;"	d
+MTX_AUTO_FLUSH_Q4_HI	include/ssv6200_aux.h	7629;"	d
+MTX_AUTO_FLUSH_Q4_I_MSK	include/ssv6200_aux.h	7627;"	d
+MTX_AUTO_FLUSH_Q4_MSK	include/ssv6200_aux.h	7626;"	d
+MTX_AUTO_FLUSH_Q4_SFT	include/ssv6200_aux.h	7628;"	d
+MTX_AUTO_FLUSH_Q4_SZ	include/ssv6200_aux.h	7630;"	d
+MTX_BCN_AUTO_SEQ_NO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7274;"	d
+MTX_BCN_AUTO_SEQ_NO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7272;"	d
+MTX_BCN_AUTO_SEQ_NO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7271;"	d
+MTX_BCN_AUTO_SEQ_NO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7273;"	d
+MTX_BCN_AUTO_SEQ_NO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7275;"	d
+MTX_BCN_CFG_VLD_HI	include/ssv6200_aux.h	7639;"	d
+MTX_BCN_CFG_VLD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7284;"	d
+MTX_BCN_CFG_VLD_I_MSK	include/ssv6200_aux.h	7637;"	d
+MTX_BCN_CFG_VLD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7282;"	d
+MTX_BCN_CFG_VLD_MASK	smac/ap.c	48;"	d	file:
+MTX_BCN_CFG_VLD_MSK	include/ssv6200_aux.h	7636;"	d
+MTX_BCN_CFG_VLD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7281;"	d
+MTX_BCN_CFG_VLD_SFT	include/ssv6200_aux.h	7638;"	d
+MTX_BCN_CFG_VLD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7283;"	d
+MTX_BCN_CFG_VLD_SHIFT	smac/ap.c	47;"	d	file:
+MTX_BCN_CFG_VLD_SZ	include/ssv6200_aux.h	7640;"	d
+MTX_BCN_CFG_VLD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7285;"	d
+MTX_BCN_ENABLE_MASK	smac/ap.c	54;"	d	file:
+MTX_BCN_ENG_RST_HI	include/ssv6200_aux.h	8884;"	d
+MTX_BCN_ENG_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8639;"	d
+MTX_BCN_ENG_RST_I_MSK	include/ssv6200_aux.h	8882;"	d
+MTX_BCN_ENG_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8637;"	d
+MTX_BCN_ENG_RST_MSK	include/ssv6200_aux.h	8881;"	d
+MTX_BCN_ENG_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8636;"	d
+MTX_BCN_ENG_RST_SFT	include/ssv6200_aux.h	8883;"	d
+MTX_BCN_ENG_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8638;"	d
+MTX_BCN_ENG_RST_SZ	include/ssv6200_aux.h	8885;"	d
+MTX_BCN_ENG_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8640;"	d
+MTX_BCN_PERIOD_HI	include/ssv6200_aux.h	7654;"	d
+MTX_BCN_PERIOD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7299;"	d
+MTX_BCN_PERIOD_I_MSK	include/ssv6200_aux.h	7652;"	d
+MTX_BCN_PERIOD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7297;"	d
+MTX_BCN_PERIOD_MSK	include/ssv6200_aux.h	7651;"	d
+MTX_BCN_PERIOD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7296;"	d
+MTX_BCN_PERIOD_SFT	include/ssv6200_aux.h	7653;"	d
+MTX_BCN_PERIOD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7298;"	d
+MTX_BCN_PERIOD_SHIFT	smac/ap.c	55;"	d	file:
+MTX_BCN_PERIOD_SZ	include/ssv6200_aux.h	7655;"	d
+MTX_BCN_PERIOD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7300;"	d
+MTX_BCN_PKTID_CH_LOCK_HI	include/ssv6200_aux.h	7634;"	d
+MTX_BCN_PKTID_CH_LOCK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7279;"	d
+MTX_BCN_PKTID_CH_LOCK_I_MSK	include/ssv6200_aux.h	7632;"	d
+MTX_BCN_PKTID_CH_LOCK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7277;"	d
+MTX_BCN_PKTID_CH_LOCK_MSK	include/ssv6200_aux.h	7631;"	d
+MTX_BCN_PKTID_CH_LOCK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7276;"	d
+MTX_BCN_PKTID_CH_LOCK_SFT	include/ssv6200_aux.h	7633;"	d
+MTX_BCN_PKTID_CH_LOCK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7278;"	d
+MTX_BCN_PKTID_CH_LOCK_SHIFT	smac/ap.c	46;"	d	file:
+MTX_BCN_PKTID_CH_LOCK_SZ	include/ssv6200_aux.h	7635;"	d
+MTX_BCN_PKTID_CH_LOCK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7280;"	d
+MTX_BCN_PKT_ID0_HI	include/ssv6200_aux.h	7674;"	d
+MTX_BCN_PKT_ID0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7199;"	d
+MTX_BCN_PKT_ID0_I_MSK	include/ssv6200_aux.h	7672;"	d
+MTX_BCN_PKT_ID0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7197;"	d
+MTX_BCN_PKT_ID0_MSK	include/ssv6200_aux.h	7671;"	d
+MTX_BCN_PKT_ID0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7196;"	d
+MTX_BCN_PKT_ID0_SFT	include/ssv6200_aux.h	7673;"	d
+MTX_BCN_PKT_ID0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7198;"	d
+MTX_BCN_PKT_ID0_SZ	include/ssv6200_aux.h	7675;"	d
+MTX_BCN_PKT_ID0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7200;"	d
+MTX_BCN_PKT_ID1_HI	include/ssv6200_aux.h	7684;"	d
+MTX_BCN_PKT_ID1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7204;"	d
+MTX_BCN_PKT_ID1_I_MSK	include/ssv6200_aux.h	7682;"	d
+MTX_BCN_PKT_ID1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7202;"	d
+MTX_BCN_PKT_ID1_MSK	include/ssv6200_aux.h	7681;"	d
+MTX_BCN_PKT_ID1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7201;"	d
+MTX_BCN_PKT_ID1_SFT	include/ssv6200_aux.h	7683;"	d
+MTX_BCN_PKT_ID1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7203;"	d
+MTX_BCN_PKT_ID1_SZ	include/ssv6200_aux.h	7685;"	d
+MTX_BCN_PKT_ID1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7205;"	d
+MTX_BCN_SW_RST_HI	include/ssv6200_aux.h	8824;"	d
+MTX_BCN_SW_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8579;"	d
+MTX_BCN_SW_RST_I_MSK	include/ssv6200_aux.h	8822;"	d
+MTX_BCN_SW_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8577;"	d
+MTX_BCN_SW_RST_MSK	include/ssv6200_aux.h	8821;"	d
+MTX_BCN_SW_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8576;"	d
+MTX_BCN_SW_RST_SFT	include/ssv6200_aux.h	8823;"	d
+MTX_BCN_SW_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8578;"	d
+MTX_BCN_SW_RST_SZ	include/ssv6200_aux.h	8825;"	d
+MTX_BCN_SW_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8580;"	d
+MTX_BCN_TIMER_EN_HI	include/ssv6200_aux.h	7604;"	d
+MTX_BCN_TIMER_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7249;"	d
+MTX_BCN_TIMER_EN_I_MSK	include/ssv6200_aux.h	7602;"	d
+MTX_BCN_TIMER_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7247;"	d
+MTX_BCN_TIMER_EN_MSK	include/ssv6200_aux.h	7601;"	d
+MTX_BCN_TIMER_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7246;"	d
+MTX_BCN_TIMER_EN_SFT	include/ssv6200_aux.h	7603;"	d
+MTX_BCN_TIMER_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7248;"	d
+MTX_BCN_TIMER_EN_SHIFT	smac/ap.c	51;"	d	file:
+MTX_BCN_TIMER_EN_SZ	include/ssv6200_aux.h	7605;"	d
+MTX_BCN_TIMER_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7250;"	d
+MTX_BCN_TIMER_HI	include/ssv6200_aux.h	7649;"	d
+MTX_BCN_TIMER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7294;"	d
+MTX_BCN_TIMER_I_MSK	include/ssv6200_aux.h	7647;"	d
+MTX_BCN_TIMER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7292;"	d
+MTX_BCN_TIMER_MSK	include/ssv6200_aux.h	7646;"	d
+MTX_BCN_TIMER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7291;"	d
+MTX_BCN_TIMER_SFT	include/ssv6200_aux.h	7648;"	d
+MTX_BCN_TIMER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7293;"	d
+MTX_BCN_TIMER_SZ	include/ssv6200_aux.h	7650;"	d
+MTX_BCN_TIMER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7295;"	d
+MTX_BCN_TSF_L_HI	include/ssv6200_aux.h	7664;"	d
+MTX_BCN_TSF_L_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7304;"	d
+MTX_BCN_TSF_L_I_MSK	include/ssv6200_aux.h	7662;"	d
+MTX_BCN_TSF_L_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7302;"	d
+MTX_BCN_TSF_L_MSK	include/ssv6200_aux.h	7661;"	d
+MTX_BCN_TSF_L_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7301;"	d
+MTX_BCN_TSF_L_SFT	include/ssv6200_aux.h	7663;"	d
+MTX_BCN_TSF_L_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7303;"	d
+MTX_BCN_TSF_L_SZ	include/ssv6200_aux.h	7665;"	d
+MTX_BCN_TSF_L_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7305;"	d
+MTX_BCN_TSF_U_HI	include/ssv6200_aux.h	7669;"	d
+MTX_BCN_TSF_U_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7309;"	d
+MTX_BCN_TSF_U_I_MSK	include/ssv6200_aux.h	7667;"	d
+MTX_BCN_TSF_U_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7307;"	d
+MTX_BCN_TSF_U_MSK	include/ssv6200_aux.h	7666;"	d
+MTX_BCN_TSF_U_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7306;"	d
+MTX_BCN_TSF_U_SFT	include/ssv6200_aux.h	7668;"	d
+MTX_BCN_TSF_U_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7308;"	d
+MTX_BCN_TSF_U_SZ	include/ssv6200_aux.h	7670;"	d
+MTX_BCN_TSF_U_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7310;"	d
+MTX_BLOCKTX_IGNORE_BT_BUSY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6694;"	d
+MTX_BLOCKTX_IGNORE_BT_BUSY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6692;"	d
+MTX_BLOCKTX_IGNORE_BT_BUSY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6691;"	d
+MTX_BLOCKTX_IGNORE_BT_BUSY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6693;"	d
+MTX_BLOCKTX_IGNORE_BT_BUSY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6695;"	d
+MTX_BLOCKTX_IGNORE_TOMAC_CCA_CS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6714;"	d
+MTX_BLOCKTX_IGNORE_TOMAC_CCA_CS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6712;"	d
+MTX_BLOCKTX_IGNORE_TOMAC_CCA_CS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6711;"	d
+MTX_BLOCKTX_IGNORE_TOMAC_CCA_CS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6713;"	d
+MTX_BLOCKTX_IGNORE_TOMAC_CCA_CS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6715;"	d
+MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_PRIMARY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6724;"	d
+MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_PRIMARY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6722;"	d
+MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_PRIMARY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6721;"	d
+MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_PRIMARY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6723;"	d
+MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_PRIMARY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6725;"	d
+MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_SECONDARY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6719;"	d
+MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_SECONDARY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6717;"	d
+MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_SECONDARY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6716;"	d
+MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_SECONDARY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6718;"	d
+MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_SECONDARY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6720;"	d
+MTX_BLOCKTX_IGNORE_TOMAC_RX_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6709;"	d
+MTX_BLOCKTX_IGNORE_TOMAC_RX_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6707;"	d
+MTX_BLOCKTX_IGNORE_TOMAC_RX_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6706;"	d
+MTX_BLOCKTX_IGNORE_TOMAC_RX_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6708;"	d
+MTX_BLOCKTX_IGNORE_TOMAC_RX_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6710;"	d
+MTX_BLOCKTX_IGNORE_TOMAC_TX_IP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6704;"	d
+MTX_BLOCKTX_IGNORE_TOMAC_TX_IP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6702;"	d
+MTX_BLOCKTX_IGNORE_TOMAC_TX_IP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6701;"	d
+MTX_BLOCKTX_IGNORE_TOMAC_TX_IP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6703;"	d
+MTX_BLOCKTX_IGNORE_TOMAC_TX_IP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6705;"	d
+MTX_CCA_HI	include/ssv6200_aux.h	7694;"	d
+MTX_CCA_I_MSK	include/ssv6200_aux.h	7692;"	d
+MTX_CCA_MSK	include/ssv6200_aux.h	7691;"	d
+MTX_CCA_SFT	include/ssv6200_aux.h	7693;"	d
+MTX_CCA_SZ	include/ssv6200_aux.h	7695;"	d
+MTX_CHST_ENG_RST_HI	include/ssv6200_aux.h	8879;"	d
+MTX_CHST_ENG_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8634;"	d
+MTX_CHST_ENG_RST_I_MSK	include/ssv6200_aux.h	8877;"	d
+MTX_CHST_ENG_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8632;"	d
+MTX_CHST_ENG_RST_MSK	include/ssv6200_aux.h	8876;"	d
+MTX_CHST_ENG_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8631;"	d
+MTX_CHST_ENG_RST_SFT	include/ssv6200_aux.h	8878;"	d
+MTX_CHST_ENG_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8633;"	d
+MTX_CHST_ENG_RST_SZ	include/ssv6200_aux.h	8880;"	d
+MTX_CHST_ENG_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8635;"	d
+MTX_CHST_SW_RST_HI	include/ssv6200_aux.h	8819;"	d
+MTX_CHST_SW_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8574;"	d
+MTX_CHST_SW_RST_I_MSK	include/ssv6200_aux.h	8817;"	d
+MTX_CHST_SW_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8572;"	d
+MTX_CHST_SW_RST_MSK	include/ssv6200_aux.h	8816;"	d
+MTX_CHST_SW_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8571;"	d
+MTX_CHST_SW_RST_SFT	include/ssv6200_aux.h	8818;"	d
+MTX_CHST_SW_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8573;"	d
+MTX_CHST_SW_RST_SZ	include/ssv6200_aux.h	8820;"	d
+MTX_CHST_SW_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8575;"	d
+MTX_CTS_SET_DIF_HI	include/ssv6200_aux.h	7569;"	d
+MTX_CTS_SET_DIF_I_MSK	include/ssv6200_aux.h	7567;"	d
+MTX_CTS_SET_DIF_MSK	include/ssv6200_aux.h	7566;"	d
+MTX_CTS_SET_DIF_SFT	include/ssv6200_aux.h	7568;"	d
+MTX_CTS_SET_DIF_SZ	include/ssv6200_aux.h	7570;"	d
+MTX_CTS_TX_HI	include/ssv6200_aux.h	9489;"	d
+MTX_CTS_TX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9324;"	d
+MTX_CTS_TX_I_MSK	include/ssv6200_aux.h	9487;"	d
+MTX_CTS_TX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9322;"	d
+MTX_CTS_TX_MSK	include/ssv6200_aux.h	9486;"	d
+MTX_CTS_TX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9321;"	d
+MTX_CTS_TX_SFT	include/ssv6200_aux.h	9488;"	d
+MTX_CTS_TX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9323;"	d
+MTX_CTS_TX_SZ	include/ssv6200_aux.h	9490;"	d
+MTX_CTS_TX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9325;"	d
+MTX_DBGOPT_FORCE_DO_RTS_CTS_MODE_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7169;"	d
+MTX_DBGOPT_FORCE_DO_RTS_CTS_MODE_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7167;"	d
+MTX_DBGOPT_FORCE_DO_RTS_CTS_MODE_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7166;"	d
+MTX_DBGOPT_FORCE_DO_RTS_CTS_MODE_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7168;"	d
+MTX_DBGOPT_FORCE_DO_RTS_CTS_MODE_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7170;"	d
+MTX_DBGOPT_FORCE_DO_RTS_CTS_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7154;"	d
+MTX_DBGOPT_FORCE_DO_RTS_CTS_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7152;"	d
+MTX_DBGOPT_FORCE_DO_RTS_CTS_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7151;"	d
+MTX_DBGOPT_FORCE_DO_RTS_CTS_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7153;"	d
+MTX_DBGOPT_FORCE_DO_RTS_CTS_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7155;"	d
+MTX_DBGOPT_FORCE_TXCTRL_RATE_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7164;"	d
+MTX_DBGOPT_FORCE_TXCTRL_RATE_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7162;"	d
+MTX_DBGOPT_FORCE_TXCTRL_RATE_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7161;"	d
+MTX_DBGOPT_FORCE_TXCTRL_RATE_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7163;"	d
+MTX_DBGOPT_FORCE_TXCTRL_RATE_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7165;"	d
+MTX_DBGOPT_FORCE_TXCTRL_RATE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7149;"	d
+MTX_DBGOPT_FORCE_TXCTRL_RATE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7147;"	d
+MTX_DBGOPT_FORCE_TXCTRL_RATE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7146;"	d
+MTX_DBGOPT_FORCE_TXCTRL_RATE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7148;"	d
+MTX_DBGOPT_FORCE_TXCTRL_RATE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7150;"	d
+MTX_DBGOPT_FORCE_TXMAJOR_RATE_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7159;"	d
+MTX_DBGOPT_FORCE_TXMAJOR_RATE_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7157;"	d
+MTX_DBGOPT_FORCE_TXMAJOR_RATE_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7156;"	d
+MTX_DBGOPT_FORCE_TXMAJOR_RATE_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7158;"	d
+MTX_DBGOPT_FORCE_TXMAJOR_RATE_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7160;"	d
+MTX_DBGOPT_FORCE_TXMAJOR_RATE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7144;"	d
+MTX_DBGOPT_FORCE_TXMAJOR_RATE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7142;"	d
+MTX_DBGOPT_FORCE_TXMAJOR_RATE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7141;"	d
+MTX_DBGOPT_FORCE_TXMAJOR_RATE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7143;"	d
+MTX_DBGOPT_FORCE_TXMAJOR_RATE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7145;"	d
+MTX_DBG_PHYRX_IFS_DELTATIME_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7419;"	d
+MTX_DBG_PHYRX_IFS_DELTATIME_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7417;"	d
+MTX_DBG_PHYRX_IFS_DELTATIME_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7416;"	d
+MTX_DBG_PHYRX_IFS_DELTATIME_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7418;"	d
+MTX_DBG_PHYRX_IFS_DELTATIME_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7420;"	d
+MTX_DMA_FSM_HI	include/ssv6200_aux.h	7704;"	d
+MTX_DMA_FSM_I_MSK	include/ssv6200_aux.h	7702;"	d
+MTX_DMA_FSM_MSK	include/ssv6200_aux.h	7701;"	d
+MTX_DMA_FSM_SFT	include/ssv6200_aux.h	7703;"	d
+MTX_DMA_FSM_SZ	include/ssv6200_aux.h	7705;"	d
+MTX_DMA_REQ_HI	include/ssv6200_aux.h	7719;"	d
+MTX_DMA_REQ_I_MSK	include/ssv6200_aux.h	7717;"	d
+MTX_DMA_REQ_MSK	include/ssv6200_aux.h	7716;"	d
+MTX_DMA_REQ_SFT	include/ssv6200_aux.h	7718;"	d
+MTX_DMA_REQ_SZ	include/ssv6200_aux.h	7720;"	d
+MTX_DTIM_CNT_AUTO_FILL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7259;"	d
+MTX_DTIM_CNT_AUTO_FILL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7257;"	d
+MTX_DTIM_CNT_AUTO_FILL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7256;"	d
+MTX_DTIM_CNT_AUTO_FILL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7258;"	d
+MTX_DTIM_CNT_AUTO_FILL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7260;"	d
+MTX_DTIM_NUM_HI	include/ssv6200_aux.h	7659;"	d
+MTX_DTIM_NUM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7219;"	d
+MTX_DTIM_NUM_I_MSK	include/ssv6200_aux.h	7657;"	d
+MTX_DTIM_NUM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7217;"	d
+MTX_DTIM_NUM_MSK	include/ssv6200_aux.h	7656;"	d
+MTX_DTIM_NUM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7216;"	d
+MTX_DTIM_NUM_SFT	include/ssv6200_aux.h	7658;"	d
+MTX_DTIM_NUM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7218;"	d
+MTX_DTIM_NUM_SHIFT	smac/ap.c	56;"	d	file:
+MTX_DTIM_NUM_SZ	include/ssv6200_aux.h	7660;"	d
+MTX_DTIM_NUM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7220;"	d
+MTX_DTIM_OFST0	smac/ap.c	57;"	d	file:
+MTX_DTIM_OFST0_HI	include/ssv6200_aux.h	7679;"	d
+MTX_DTIM_OFST0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7209;"	d
+MTX_DTIM_OFST0_I_MSK	include/ssv6200_aux.h	7677;"	d
+MTX_DTIM_OFST0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7207;"	d
+MTX_DTIM_OFST0_MSK	include/ssv6200_aux.h	7676;"	d
+MTX_DTIM_OFST0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7206;"	d
+MTX_DTIM_OFST0_SFT	include/ssv6200_aux.h	7678;"	d
+MTX_DTIM_OFST0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7208;"	d
+MTX_DTIM_OFST0_SZ	include/ssv6200_aux.h	7680;"	d
+MTX_DTIM_OFST0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7210;"	d
+MTX_DTIM_OFST1_HI	include/ssv6200_aux.h	7689;"	d
+MTX_DTIM_OFST1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7214;"	d
+MTX_DTIM_OFST1_I_MSK	include/ssv6200_aux.h	7687;"	d
+MTX_DTIM_OFST1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7212;"	d
+MTX_DTIM_OFST1_MSK	include/ssv6200_aux.h	7686;"	d
+MTX_DTIM_OFST1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7211;"	d
+MTX_DTIM_OFST1_SFT	include/ssv6200_aux.h	7688;"	d
+MTX_DTIM_OFST1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7213;"	d
+MTX_DTIM_OFST1_SZ	include/ssv6200_aux.h	7690;"	d
+MTX_DTIM_OFST1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7215;"	d
+MTX_DUR_BURST_SIFS_G_HI	include/ssv6200_aux.h	7834;"	d
+MTX_DUR_BURST_SIFS_G_I_MSK	include/ssv6200_aux.h	7832;"	d
+MTX_DUR_BURST_SIFS_G_MSK	include/ssv6200_aux.h	7831;"	d
+MTX_DUR_BURST_SIFS_G_SFT	include/ssv6200_aux.h	7833;"	d
+MTX_DUR_BURST_SIFS_G_SZ	include/ssv6200_aux.h	7835;"	d
+MTX_DUR_BURST_SIFS_HI	include/ssv6200_aux.h	7814;"	d
+MTX_DUR_BURST_SIFS_I_MSK	include/ssv6200_aux.h	7812;"	d
+MTX_DUR_BURST_SIFS_MSK	include/ssv6200_aux.h	7811;"	d
+MTX_DUR_BURST_SIFS_SFT	include/ssv6200_aux.h	7813;"	d
+MTX_DUR_BURST_SIFS_SZ	include/ssv6200_aux.h	7815;"	d
+MTX_DUR_RSP_EIFS_G_HI	include/ssv6200_aux.h	7844;"	d
+MTX_DUR_RSP_EIFS_G_I_MSK	include/ssv6200_aux.h	7842;"	d
+MTX_DUR_RSP_EIFS_G_MSK	include/ssv6200_aux.h	7841;"	d
+MTX_DUR_RSP_EIFS_G_SFT	include/ssv6200_aux.h	7843;"	d
+MTX_DUR_RSP_EIFS_G_SZ	include/ssv6200_aux.h	7845;"	d
+MTX_DUR_RSP_EIFS_HI	include/ssv6200_aux.h	7824;"	d
+MTX_DUR_RSP_EIFS_I_MSK	include/ssv6200_aux.h	7822;"	d
+MTX_DUR_RSP_EIFS_MSK	include/ssv6200_aux.h	7821;"	d
+MTX_DUR_RSP_EIFS_SFT	include/ssv6200_aux.h	7823;"	d
+MTX_DUR_RSP_EIFS_SZ	include/ssv6200_aux.h	7825;"	d
+MTX_DUR_RSP_SIFS_G_HI	include/ssv6200_aux.h	7829;"	d
+MTX_DUR_RSP_SIFS_G_I_MSK	include/ssv6200_aux.h	7827;"	d
+MTX_DUR_RSP_SIFS_G_MSK	include/ssv6200_aux.h	7826;"	d
+MTX_DUR_RSP_SIFS_G_SFT	include/ssv6200_aux.h	7828;"	d
+MTX_DUR_RSP_SIFS_G_SZ	include/ssv6200_aux.h	7830;"	d
+MTX_DUR_RSP_SIFS_HI	include/ssv6200_aux.h	7809;"	d
+MTX_DUR_RSP_SIFS_I_MSK	include/ssv6200_aux.h	7807;"	d
+MTX_DUR_RSP_SIFS_MSK	include/ssv6200_aux.h	7806;"	d
+MTX_DUR_RSP_SIFS_SFT	include/ssv6200_aux.h	7808;"	d
+MTX_DUR_RSP_SIFS_SZ	include/ssv6200_aux.h	7810;"	d
+MTX_DUR_RSP_TOUT_B_HI	include/ssv6200_aux.h	7799;"	d
+MTX_DUR_RSP_TOUT_B_I_MSK	include/ssv6200_aux.h	7797;"	d
+MTX_DUR_RSP_TOUT_B_MSK	include/ssv6200_aux.h	7796;"	d
+MTX_DUR_RSP_TOUT_B_SFT	include/ssv6200_aux.h	7798;"	d
+MTX_DUR_RSP_TOUT_B_SZ	include/ssv6200_aux.h	7800;"	d
+MTX_DUR_RSP_TOUT_G_HI	include/ssv6200_aux.h	7804;"	d
+MTX_DUR_RSP_TOUT_G_I_MSK	include/ssv6200_aux.h	7802;"	d
+MTX_DUR_RSP_TOUT_G_MSK	include/ssv6200_aux.h	7801;"	d
+MTX_DUR_RSP_TOUT_G_SFT	include/ssv6200_aux.h	7803;"	d
+MTX_DUR_RSP_TOUT_G_SZ	include/ssv6200_aux.h	7805;"	d
+MTX_DUR_SLOT_G_HI	include/ssv6200_aux.h	7839;"	d
+MTX_DUR_SLOT_G_I_MSK	include/ssv6200_aux.h	7837;"	d
+MTX_DUR_SLOT_G_MSK	include/ssv6200_aux.h	7836;"	d
+MTX_DUR_SLOT_G_SFT	include/ssv6200_aux.h	7838;"	d
+MTX_DUR_SLOT_G_SZ	include/ssv6200_aux.h	7840;"	d
+MTX_DUR_SLOT_HI	include/ssv6200_aux.h	7819;"	d
+MTX_DUR_SLOT_I_MSK	include/ssv6200_aux.h	7817;"	d
+MTX_DUR_SLOT_MSK	include/ssv6200_aux.h	7816;"	d
+MTX_DUR_SLOT_SFT	include/ssv6200_aux.h	7818;"	d
+MTX_DUR_SLOT_SZ	include/ssv6200_aux.h	7820;"	d
+MTX_EDCCA_TOUT_HI	include/ssv6200_aux.h	7579;"	d
+MTX_EDCCA_TOUT_I_MSK	include/ssv6200_aux.h	7577;"	d
+MTX_EDCCA_TOUT_MSK	include/ssv6200_aux.h	7576;"	d
+MTX_EDCCA_TOUT_SFT	include/ssv6200_aux.h	7578;"	d
+MTX_EDCCA_TOUT_SZ	include/ssv6200_aux.h	7580;"	d
+MTX_EN_INT_BCN_HI	include/ssv6200_aux.h	7594;"	d
+MTX_EN_INT_BCN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7239;"	d
+MTX_EN_INT_BCN_I_MSK	include/ssv6200_aux.h	7592;"	d
+MTX_EN_INT_BCN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7237;"	d
+MTX_EN_INT_BCN_MSK	include/ssv6200_aux.h	7591;"	d
+MTX_EN_INT_BCN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7236;"	d
+MTX_EN_INT_BCN_SFT	include/ssv6200_aux.h	7593;"	d
+MTX_EN_INT_BCN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7238;"	d
+MTX_EN_INT_BCN_SZ	include/ssv6200_aux.h	7595;"	d
+MTX_EN_INT_BCN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7240;"	d
+MTX_EN_INT_DTIM_HI	include/ssv6200_aux.h	7599;"	d
+MTX_EN_INT_DTIM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7244;"	d
+MTX_EN_INT_DTIM_I_MSK	include/ssv6200_aux.h	7597;"	d
+MTX_EN_INT_DTIM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7242;"	d
+MTX_EN_INT_DTIM_MSK	include/ssv6200_aux.h	7596;"	d
+MTX_EN_INT_DTIM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7241;"	d
+MTX_EN_INT_DTIM_SFT	include/ssv6200_aux.h	7598;"	d
+MTX_EN_INT_DTIM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7243;"	d
+MTX_EN_INT_DTIM_SZ	include/ssv6200_aux.h	7600;"	d
+MTX_EN_INT_DTIM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7245;"	d
+MTX_EN_INT_Q0_Q_EMPTY_HI	include/ssv6200_aux.h	7454;"	d
+MTX_EN_INT_Q0_Q_EMPTY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6619;"	d
+MTX_EN_INT_Q0_Q_EMPTY_I_MSK	include/ssv6200_aux.h	7452;"	d
+MTX_EN_INT_Q0_Q_EMPTY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6617;"	d
+MTX_EN_INT_Q0_Q_EMPTY_MSK	include/ssv6200_aux.h	7451;"	d
+MTX_EN_INT_Q0_Q_EMPTY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6616;"	d
+MTX_EN_INT_Q0_Q_EMPTY_SFT	include/ssv6200_aux.h	7453;"	d
+MTX_EN_INT_Q0_Q_EMPTY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6618;"	d
+MTX_EN_INT_Q0_Q_EMPTY_SZ	include/ssv6200_aux.h	7455;"	d
+MTX_EN_INT_Q0_Q_EMPTY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6620;"	d
+MTX_EN_INT_Q0_TXOP_RUNOUT_HI	include/ssv6200_aux.h	7459;"	d
+MTX_EN_INT_Q0_TXOP_RUNOUT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6624;"	d
+MTX_EN_INT_Q0_TXOP_RUNOUT_I_MSK	include/ssv6200_aux.h	7457;"	d
+MTX_EN_INT_Q0_TXOP_RUNOUT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6622;"	d
+MTX_EN_INT_Q0_TXOP_RUNOUT_MSK	include/ssv6200_aux.h	7456;"	d
+MTX_EN_INT_Q0_TXOP_RUNOUT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6621;"	d
+MTX_EN_INT_Q0_TXOP_RUNOUT_SFT	include/ssv6200_aux.h	7458;"	d
+MTX_EN_INT_Q0_TXOP_RUNOUT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6623;"	d
+MTX_EN_INT_Q0_TXOP_RUNOUT_SZ	include/ssv6200_aux.h	7460;"	d
+MTX_EN_INT_Q0_TXOP_RUNOUT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6625;"	d
+MTX_EN_INT_Q1_Q_EMPTY_HI	include/ssv6200_aux.h	7464;"	d
+MTX_EN_INT_Q1_Q_EMPTY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6629;"	d
+MTX_EN_INT_Q1_Q_EMPTY_I_MSK	include/ssv6200_aux.h	7462;"	d
+MTX_EN_INT_Q1_Q_EMPTY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6627;"	d
+MTX_EN_INT_Q1_Q_EMPTY_MSK	include/ssv6200_aux.h	7461;"	d
+MTX_EN_INT_Q1_Q_EMPTY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6626;"	d
+MTX_EN_INT_Q1_Q_EMPTY_SFT	include/ssv6200_aux.h	7463;"	d
+MTX_EN_INT_Q1_Q_EMPTY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6628;"	d
+MTX_EN_INT_Q1_Q_EMPTY_SZ	include/ssv6200_aux.h	7465;"	d
+MTX_EN_INT_Q1_Q_EMPTY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6630;"	d
+MTX_EN_INT_Q1_TXOP_RUNOUT_HI	include/ssv6200_aux.h	7469;"	d
+MTX_EN_INT_Q1_TXOP_RUNOUT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6634;"	d
+MTX_EN_INT_Q1_TXOP_RUNOUT_I_MSK	include/ssv6200_aux.h	7467;"	d
+MTX_EN_INT_Q1_TXOP_RUNOUT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6632;"	d
+MTX_EN_INT_Q1_TXOP_RUNOUT_MSK	include/ssv6200_aux.h	7466;"	d
+MTX_EN_INT_Q1_TXOP_RUNOUT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6631;"	d
+MTX_EN_INT_Q1_TXOP_RUNOUT_SFT	include/ssv6200_aux.h	7468;"	d
+MTX_EN_INT_Q1_TXOP_RUNOUT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6633;"	d
+MTX_EN_INT_Q1_TXOP_RUNOUT_SZ	include/ssv6200_aux.h	7470;"	d
+MTX_EN_INT_Q1_TXOP_RUNOUT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6635;"	d
+MTX_EN_INT_Q2_Q_EMPTY_HI	include/ssv6200_aux.h	7474;"	d
+MTX_EN_INT_Q2_Q_EMPTY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6639;"	d
+MTX_EN_INT_Q2_Q_EMPTY_I_MSK	include/ssv6200_aux.h	7472;"	d
+MTX_EN_INT_Q2_Q_EMPTY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6637;"	d
+MTX_EN_INT_Q2_Q_EMPTY_MSK	include/ssv6200_aux.h	7471;"	d
+MTX_EN_INT_Q2_Q_EMPTY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6636;"	d
+MTX_EN_INT_Q2_Q_EMPTY_SFT	include/ssv6200_aux.h	7473;"	d
+MTX_EN_INT_Q2_Q_EMPTY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6638;"	d
+MTX_EN_INT_Q2_Q_EMPTY_SZ	include/ssv6200_aux.h	7475;"	d
+MTX_EN_INT_Q2_Q_EMPTY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6640;"	d
+MTX_EN_INT_Q2_TXOP_RUNOUT_HI	include/ssv6200_aux.h	7479;"	d
+MTX_EN_INT_Q2_TXOP_RUNOUT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6644;"	d
+MTX_EN_INT_Q2_TXOP_RUNOUT_I_MSK	include/ssv6200_aux.h	7477;"	d
+MTX_EN_INT_Q2_TXOP_RUNOUT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6642;"	d
+MTX_EN_INT_Q2_TXOP_RUNOUT_MSK	include/ssv6200_aux.h	7476;"	d
+MTX_EN_INT_Q2_TXOP_RUNOUT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6641;"	d
+MTX_EN_INT_Q2_TXOP_RUNOUT_SFT	include/ssv6200_aux.h	7478;"	d
+MTX_EN_INT_Q2_TXOP_RUNOUT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6643;"	d
+MTX_EN_INT_Q2_TXOP_RUNOUT_SZ	include/ssv6200_aux.h	7480;"	d
+MTX_EN_INT_Q2_TXOP_RUNOUT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6645;"	d
+MTX_EN_INT_Q3_Q_EMPTY_HI	include/ssv6200_aux.h	7484;"	d
+MTX_EN_INT_Q3_Q_EMPTY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6649;"	d
+MTX_EN_INT_Q3_Q_EMPTY_I_MSK	include/ssv6200_aux.h	7482;"	d
+MTX_EN_INT_Q3_Q_EMPTY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6647;"	d
+MTX_EN_INT_Q3_Q_EMPTY_MSK	include/ssv6200_aux.h	7481;"	d
+MTX_EN_INT_Q3_Q_EMPTY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6646;"	d
+MTX_EN_INT_Q3_Q_EMPTY_SFT	include/ssv6200_aux.h	7483;"	d
+MTX_EN_INT_Q3_Q_EMPTY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6648;"	d
+MTX_EN_INT_Q3_Q_EMPTY_SZ	include/ssv6200_aux.h	7485;"	d
+MTX_EN_INT_Q3_Q_EMPTY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6650;"	d
+MTX_EN_INT_Q3_TXOP_RUNOUT_HI	include/ssv6200_aux.h	7489;"	d
+MTX_EN_INT_Q3_TXOP_RUNOUT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6654;"	d
+MTX_EN_INT_Q3_TXOP_RUNOUT_I_MSK	include/ssv6200_aux.h	7487;"	d
+MTX_EN_INT_Q3_TXOP_RUNOUT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6652;"	d
+MTX_EN_INT_Q3_TXOP_RUNOUT_MSK	include/ssv6200_aux.h	7486;"	d
+MTX_EN_INT_Q3_TXOP_RUNOUT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6651;"	d
+MTX_EN_INT_Q3_TXOP_RUNOUT_SFT	include/ssv6200_aux.h	7488;"	d
+MTX_EN_INT_Q3_TXOP_RUNOUT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6653;"	d
+MTX_EN_INT_Q3_TXOP_RUNOUT_SZ	include/ssv6200_aux.h	7490;"	d
+MTX_EN_INT_Q3_TXOP_RUNOUT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6655;"	d
+MTX_EN_INT_Q4_Q_EMPTY_HI	include/ssv6200_aux.h	7494;"	d
+MTX_EN_INT_Q4_Q_EMPTY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6659;"	d
+MTX_EN_INT_Q4_Q_EMPTY_I_MSK	include/ssv6200_aux.h	7492;"	d
+MTX_EN_INT_Q4_Q_EMPTY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6657;"	d
+MTX_EN_INT_Q4_Q_EMPTY_MSK	include/ssv6200_aux.h	7491;"	d
+MTX_EN_INT_Q4_Q_EMPTY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6656;"	d
+MTX_EN_INT_Q4_Q_EMPTY_SFT	include/ssv6200_aux.h	7493;"	d
+MTX_EN_INT_Q4_Q_EMPTY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6658;"	d
+MTX_EN_INT_Q4_Q_EMPTY_SZ	include/ssv6200_aux.h	7495;"	d
+MTX_EN_INT_Q4_Q_EMPTY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6660;"	d
+MTX_EN_INT_Q4_TXOP_RUNOUT_HI	include/ssv6200_aux.h	7499;"	d
+MTX_EN_INT_Q4_TXOP_RUNOUT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6664;"	d
+MTX_EN_INT_Q4_TXOP_RUNOUT_I_MSK	include/ssv6200_aux.h	7497;"	d
+MTX_EN_INT_Q4_TXOP_RUNOUT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6662;"	d
+MTX_EN_INT_Q4_TXOP_RUNOUT_MSK	include/ssv6200_aux.h	7496;"	d
+MTX_EN_INT_Q4_TXOP_RUNOUT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6661;"	d
+MTX_EN_INT_Q4_TXOP_RUNOUT_SFT	include/ssv6200_aux.h	7498;"	d
+MTX_EN_INT_Q4_TXOP_RUNOUT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6663;"	d
+MTX_EN_INT_Q4_TXOP_RUNOUT_SZ	include/ssv6200_aux.h	7500;"	d
+MTX_EN_INT_Q4_TXOP_RUNOUT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6665;"	d
+MTX_EN_INT_Q5_Q_EMPTY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6669;"	d
+MTX_EN_INT_Q5_Q_EMPTY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6667;"	d
+MTX_EN_INT_Q5_Q_EMPTY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6666;"	d
+MTX_EN_INT_Q5_Q_EMPTY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6668;"	d
+MTX_EN_INT_Q5_Q_EMPTY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6670;"	d
+MTX_EN_INT_Q5_TXOP_RUNOUT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6674;"	d
+MTX_EN_INT_Q5_TXOP_RUNOUT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6672;"	d
+MTX_EN_INT_Q5_TXOP_RUNOUT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6671;"	d
+MTX_EN_INT_Q5_TXOP_RUNOUT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6673;"	d
+MTX_EN_INT_Q5_TXOP_RUNOUT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6675;"	d
+MTX_FAIL_HI	include/ssv6200_aux.h	9449;"	d
+MTX_FAIL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9284;"	d
+MTX_FAIL_I_MSK	include/ssv6200_aux.h	9447;"	d
+MTX_FAIL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9282;"	d
+MTX_FAIL_MSK	include/ssv6200_aux.h	9446;"	d
+MTX_FAIL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9281;"	d
+MTX_FAIL_SFT	include/ssv6200_aux.h	9448;"	d
+MTX_FAIL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9283;"	d
+MTX_FAIL_SZ	include/ssv6200_aux.h	9450;"	d
+MTX_FAIL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9285;"	d
+MTX_FAST_RSP_MODE_HI	include/ssv6200_aux.h	7519;"	d
+MTX_FAST_RSP_MODE_I_MSK	include/ssv6200_aux.h	7517;"	d
+MTX_FAST_RSP_MODE_MSK	include/ssv6200_aux.h	7516;"	d
+MTX_FAST_RSP_MODE_SFT	include/ssv6200_aux.h	7518;"	d
+MTX_FAST_RSP_MODE_SZ	include/ssv6200_aux.h	7520;"	d
+MTX_FORCE_BKF_RXEN0_HI	include/ssv6200_aux.h	7549;"	d
+MTX_FORCE_BKF_RXEN0_I_MSK	include/ssv6200_aux.h	7547;"	d
+MTX_FORCE_BKF_RXEN0_MSK	include/ssv6200_aux.h	7546;"	d
+MTX_FORCE_BKF_RXEN0_SFT	include/ssv6200_aux.h	7548;"	d
+MTX_FORCE_BKF_RXEN0_SZ	include/ssv6200_aux.h	7550;"	d
+MTX_FORCE_CS_IDLE_HI	include/ssv6200_aux.h	7544;"	d
+MTX_FORCE_CS_IDLE_I_MSK	include/ssv6200_aux.h	7542;"	d
+MTX_FORCE_CS_IDLE_MSK	include/ssv6200_aux.h	7541;"	d
+MTX_FORCE_CS_IDLE_SFT	include/ssv6200_aux.h	7543;"	d
+MTX_FORCE_CS_IDLE_SZ	include/ssv6200_aux.h	7545;"	d
+MTX_FORCE_DMA_RXEN0_HI	include/ssv6200_aux.h	7554;"	d
+MTX_FORCE_DMA_RXEN0_I_MSK	include/ssv6200_aux.h	7552;"	d
+MTX_FORCE_DMA_RXEN0_MSK	include/ssv6200_aux.h	7551;"	d
+MTX_FORCE_DMA_RXEN0_SFT	include/ssv6200_aux.h	7553;"	d
+MTX_FORCE_DMA_RXEN0_SZ	include/ssv6200_aux.h	7555;"	d
+MTX_FORCE_RXEN0_HI	include/ssv6200_aux.h	7559;"	d
+MTX_FORCE_RXEN0_I_MSK	include/ssv6200_aux.h	7557;"	d
+MTX_FORCE_RXEN0_MSK	include/ssv6200_aux.h	7556;"	d
+MTX_FORCE_RXEN0_SFT	include/ssv6200_aux.h	7558;"	d
+MTX_FORCE_RXEN0_SZ	include/ssv6200_aux.h	7560;"	d
+MTX_FRM_HI	include/ssv6200_aux.h	9479;"	d
+MTX_FRM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9314;"	d
+MTX_FRM_I_MSK	include/ssv6200_aux.h	9477;"	d
+MTX_FRM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9312;"	d
+MTX_FRM_MSK	include/ssv6200_aux.h	9476;"	d
+MTX_FRM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9311;"	d
+MTX_FRM_SFT	include/ssv6200_aux.h	9478;"	d
+MTX_FRM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9313;"	d
+MTX_FRM_SZ	include/ssv6200_aux.h	9480;"	d
+MTX_FRM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9315;"	d
+MTX_GNT_LOCK_HI	include/ssv6200_aux.h	7714;"	d
+MTX_GNT_LOCK_I_MSK	include/ssv6200_aux.h	7712;"	d
+MTX_GNT_LOCK_MSK	include/ssv6200_aux.h	7711;"	d
+MTX_GNT_LOCK_SFT	include/ssv6200_aux.h	7713;"	d
+MTX_GNT_LOCK_SZ	include/ssv6200_aux.h	7715;"	d
+MTX_GRP_HI	include/ssv6200_aux.h	9444;"	d
+MTX_GRP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9279;"	d
+MTX_GRP_I_MSK	include/ssv6200_aux.h	9442;"	d
+MTX_GRP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9277;"	d
+MTX_GRP_MSK	include/ssv6200_aux.h	9441;"	d
+MTX_GRP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9276;"	d
+MTX_GRP_SFT	include/ssv6200_aux.h	9443;"	d
+MTX_GRP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9278;"	d
+MTX_GRP_SZ	include/ssv6200_aux.h	9445;"	d
+MTX_GRP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9280;"	d
+MTX_HALT_IGNORE_RXREQ_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6834;"	d
+MTX_HALT_IGNORE_RXREQ_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6832;"	d
+MTX_HALT_IGNORE_RXREQ_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6831;"	d
+MTX_HALT_IGNORE_RXREQ_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6833;"	d
+MTX_HALT_IGNORE_RXREQ_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6835;"	d
+MTX_HALT_IGNORE_TXREQ_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6829;"	d
+MTX_HALT_IGNORE_TXREQ_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6827;"	d
+MTX_HALT_IGNORE_TXREQ_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6826;"	d
+MTX_HALT_IGNORE_TXREQ_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6828;"	d
+MTX_HALT_IGNORE_TXREQ_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6830;"	d
+MTX_HALT_MNG_UNTIL_DTIM_HI	include/ssv6200_aux.h	7619;"	d
+MTX_HALT_MNG_UNTIL_DTIM_I_MSK	include/ssv6200_aux.h	7617;"	d
+MTX_HALT_MNG_UNTIL_DTIM_MSK	include/ssv6200_aux.h	7616;"	d
+MTX_HALT_MNG_UNTIL_DTIM_SFT	include/ssv6200_aux.h	7618;"	d
+MTX_HALT_MNG_UNTIL_DTIM_SHIFT	smac/ap.c	53;"	d	file:
+MTX_HALT_MNG_UNTIL_DTIM_SZ	include/ssv6200_aux.h	7620;"	d
+MTX_HALT_MODE0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6819;"	d
+MTX_HALT_MODE0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6817;"	d
+MTX_HALT_MODE0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6816;"	d
+MTX_HALT_MODE0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6818;"	d
+MTX_HALT_MODE0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6820;"	d
+MTX_HALT_Q_MB_HI	include/ssv6200_aux.h	7564;"	d
+MTX_HALT_Q_MB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6729;"	d
+MTX_HALT_Q_MB_I_MSK	include/ssv6200_aux.h	7562;"	d
+MTX_HALT_Q_MB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6727;"	d
+MTX_HALT_Q_MB_MSK	include/ssv6200_aux.h	7561;"	d
+MTX_HALT_Q_MB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6726;"	d
+MTX_HALT_Q_MB_SFT	include/ssv6200_aux.h	7563;"	d
+MTX_HALT_Q_MB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6728;"	d
+MTX_HALT_Q_MB_SZ	include/ssv6200_aux.h	7565;"	d
+MTX_HALT_Q_MB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6730;"	d
+MTX_IGNORE_PHYRX_IFS_DELTATIME_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6734;"	d
+MTX_IGNORE_PHYRX_IFS_DELTATIME_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6732;"	d
+MTX_IGNORE_PHYRX_IFS_DELTATIME_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6731;"	d
+MTX_IGNORE_PHYRX_IFS_DELTATIME_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6733;"	d
+MTX_IGNORE_PHYRX_IFS_DELTATIME_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6735;"	d
+MTX_INT_BCN_HI	include/ssv6200_aux.h	7584;"	d
+MTX_INT_BCN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7234;"	d
+MTX_INT_BCN_I_MSK	include/ssv6200_aux.h	7582;"	d
+MTX_INT_BCN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7232;"	d
+MTX_INT_BCN_MSK	include/ssv6200_aux.h	7581;"	d
+MTX_INT_BCN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7231;"	d
+MTX_INT_BCN_SFT	include/ssv6200_aux.h	7583;"	d
+MTX_INT_BCN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7233;"	d
+MTX_INT_BCN_SZ	include/ssv6200_aux.h	7585;"	d
+MTX_INT_BCN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7235;"	d
+MTX_INT_DTIM_HI	include/ssv6200_aux.h	7589;"	d
+MTX_INT_DTIM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7229;"	d
+MTX_INT_DTIM_I_MSK	include/ssv6200_aux.h	7587;"	d
+MTX_INT_DTIM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7227;"	d
+MTX_INT_DTIM_MSK	include/ssv6200_aux.h	7586;"	d
+MTX_INT_DTIM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7226;"	d
+MTX_INT_DTIM_NUM_HI	include/ssv6200_aux.h	7624;"	d
+MTX_INT_DTIM_NUM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7224;"	d
+MTX_INT_DTIM_NUM_I_MSK	include/ssv6200_aux.h	7622;"	d
+MTX_INT_DTIM_NUM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7222;"	d
+MTX_INT_DTIM_NUM_MSK	include/ssv6200_aux.h	7621;"	d
+MTX_INT_DTIM_NUM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7221;"	d
+MTX_INT_DTIM_NUM_SFT	include/ssv6200_aux.h	7623;"	d
+MTX_INT_DTIM_NUM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7223;"	d
+MTX_INT_DTIM_NUM_SZ	include/ssv6200_aux.h	7625;"	d
+MTX_INT_DTIM_NUM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7225;"	d
+MTX_INT_DTIM_SFT	include/ssv6200_aux.h	7588;"	d
+MTX_INT_DTIM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7228;"	d
+MTX_INT_DTIM_SZ	include/ssv6200_aux.h	7590;"	d
+MTX_INT_DTIM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7230;"	d
+MTX_INT_Q0_Q_EMPTY_HI	include/ssv6200_aux.h	7404;"	d
+MTX_INT_Q0_Q_EMPTY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6559;"	d
+MTX_INT_Q0_Q_EMPTY_I_MSK	include/ssv6200_aux.h	7402;"	d
+MTX_INT_Q0_Q_EMPTY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6557;"	d
+MTX_INT_Q0_Q_EMPTY_MSK	include/ssv6200_aux.h	7401;"	d
+MTX_INT_Q0_Q_EMPTY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6556;"	d
+MTX_INT_Q0_Q_EMPTY_SFT	include/ssv6200_aux.h	7403;"	d
+MTX_INT_Q0_Q_EMPTY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6558;"	d
+MTX_INT_Q0_Q_EMPTY_SZ	include/ssv6200_aux.h	7405;"	d
+MTX_INT_Q0_Q_EMPTY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6560;"	d
+MTX_INT_Q0_TXOP_RUNOUT_HI	include/ssv6200_aux.h	7409;"	d
+MTX_INT_Q0_TXOP_RUNOUT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6564;"	d
+MTX_INT_Q0_TXOP_RUNOUT_I_MSK	include/ssv6200_aux.h	7407;"	d
+MTX_INT_Q0_TXOP_RUNOUT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6562;"	d
+MTX_INT_Q0_TXOP_RUNOUT_MSK	include/ssv6200_aux.h	7406;"	d
+MTX_INT_Q0_TXOP_RUNOUT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6561;"	d
+MTX_INT_Q0_TXOP_RUNOUT_SFT	include/ssv6200_aux.h	7408;"	d
+MTX_INT_Q0_TXOP_RUNOUT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6563;"	d
+MTX_INT_Q0_TXOP_RUNOUT_SZ	include/ssv6200_aux.h	7410;"	d
+MTX_INT_Q0_TXOP_RUNOUT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6565;"	d
+MTX_INT_Q1_Q_EMPTY_HI	include/ssv6200_aux.h	7414;"	d
+MTX_INT_Q1_Q_EMPTY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6569;"	d
+MTX_INT_Q1_Q_EMPTY_I_MSK	include/ssv6200_aux.h	7412;"	d
+MTX_INT_Q1_Q_EMPTY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6567;"	d
+MTX_INT_Q1_Q_EMPTY_MSK	include/ssv6200_aux.h	7411;"	d
+MTX_INT_Q1_Q_EMPTY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6566;"	d
+MTX_INT_Q1_Q_EMPTY_SFT	include/ssv6200_aux.h	7413;"	d
+MTX_INT_Q1_Q_EMPTY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6568;"	d
+MTX_INT_Q1_Q_EMPTY_SZ	include/ssv6200_aux.h	7415;"	d
+MTX_INT_Q1_Q_EMPTY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6570;"	d
+MTX_INT_Q1_TXOP_RUNOUT_HI	include/ssv6200_aux.h	7419;"	d
+MTX_INT_Q1_TXOP_RUNOUT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6574;"	d
+MTX_INT_Q1_TXOP_RUNOUT_I_MSK	include/ssv6200_aux.h	7417;"	d
+MTX_INT_Q1_TXOP_RUNOUT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6572;"	d
+MTX_INT_Q1_TXOP_RUNOUT_MSK	include/ssv6200_aux.h	7416;"	d
+MTX_INT_Q1_TXOP_RUNOUT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6571;"	d
+MTX_INT_Q1_TXOP_RUNOUT_SFT	include/ssv6200_aux.h	7418;"	d
+MTX_INT_Q1_TXOP_RUNOUT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6573;"	d
+MTX_INT_Q1_TXOP_RUNOUT_SZ	include/ssv6200_aux.h	7420;"	d
+MTX_INT_Q1_TXOP_RUNOUT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6575;"	d
+MTX_INT_Q2_Q_EMPTY_HI	include/ssv6200_aux.h	7424;"	d
+MTX_INT_Q2_Q_EMPTY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6579;"	d
+MTX_INT_Q2_Q_EMPTY_I_MSK	include/ssv6200_aux.h	7422;"	d
+MTX_INT_Q2_Q_EMPTY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6577;"	d
+MTX_INT_Q2_Q_EMPTY_MSK	include/ssv6200_aux.h	7421;"	d
+MTX_INT_Q2_Q_EMPTY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6576;"	d
+MTX_INT_Q2_Q_EMPTY_SFT	include/ssv6200_aux.h	7423;"	d
+MTX_INT_Q2_Q_EMPTY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6578;"	d
+MTX_INT_Q2_Q_EMPTY_SZ	include/ssv6200_aux.h	7425;"	d
+MTX_INT_Q2_Q_EMPTY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6580;"	d
+MTX_INT_Q2_TXOP_RUNOUT_HI	include/ssv6200_aux.h	7429;"	d
+MTX_INT_Q2_TXOP_RUNOUT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6584;"	d
+MTX_INT_Q2_TXOP_RUNOUT_I_MSK	include/ssv6200_aux.h	7427;"	d
+MTX_INT_Q2_TXOP_RUNOUT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6582;"	d
+MTX_INT_Q2_TXOP_RUNOUT_MSK	include/ssv6200_aux.h	7426;"	d
+MTX_INT_Q2_TXOP_RUNOUT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6581;"	d
+MTX_INT_Q2_TXOP_RUNOUT_SFT	include/ssv6200_aux.h	7428;"	d
+MTX_INT_Q2_TXOP_RUNOUT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6583;"	d
+MTX_INT_Q2_TXOP_RUNOUT_SZ	include/ssv6200_aux.h	7430;"	d
+MTX_INT_Q2_TXOP_RUNOUT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6585;"	d
+MTX_INT_Q3_Q_EMPTY_HI	include/ssv6200_aux.h	7434;"	d
+MTX_INT_Q3_Q_EMPTY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6589;"	d
+MTX_INT_Q3_Q_EMPTY_I_MSK	include/ssv6200_aux.h	7432;"	d
+MTX_INT_Q3_Q_EMPTY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6587;"	d
+MTX_INT_Q3_Q_EMPTY_MSK	include/ssv6200_aux.h	7431;"	d
+MTX_INT_Q3_Q_EMPTY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6586;"	d
+MTX_INT_Q3_Q_EMPTY_SFT	include/ssv6200_aux.h	7433;"	d
+MTX_INT_Q3_Q_EMPTY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6588;"	d
+MTX_INT_Q3_Q_EMPTY_SZ	include/ssv6200_aux.h	7435;"	d
+MTX_INT_Q3_Q_EMPTY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6590;"	d
+MTX_INT_Q3_TXOP_RUNOUT_HI	include/ssv6200_aux.h	7439;"	d
+MTX_INT_Q3_TXOP_RUNOUT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6594;"	d
+MTX_INT_Q3_TXOP_RUNOUT_I_MSK	include/ssv6200_aux.h	7437;"	d
+MTX_INT_Q3_TXOP_RUNOUT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6592;"	d
+MTX_INT_Q3_TXOP_RUNOUT_MSK	include/ssv6200_aux.h	7436;"	d
+MTX_INT_Q3_TXOP_RUNOUT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6591;"	d
+MTX_INT_Q3_TXOP_RUNOUT_SFT	include/ssv6200_aux.h	7438;"	d
+MTX_INT_Q3_TXOP_RUNOUT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6593;"	d
+MTX_INT_Q3_TXOP_RUNOUT_SZ	include/ssv6200_aux.h	7440;"	d
+MTX_INT_Q3_TXOP_RUNOUT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6595;"	d
+MTX_INT_Q4_Q_EMPTY_HI	include/ssv6200_aux.h	7444;"	d
+MTX_INT_Q4_Q_EMPTY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6599;"	d
+MTX_INT_Q4_Q_EMPTY_I_MSK	include/ssv6200_aux.h	7442;"	d
+MTX_INT_Q4_Q_EMPTY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6597;"	d
+MTX_INT_Q4_Q_EMPTY_MSK	include/ssv6200_aux.h	7441;"	d
+MTX_INT_Q4_Q_EMPTY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6596;"	d
+MTX_INT_Q4_Q_EMPTY_SFT	include/ssv6200_aux.h	7443;"	d
+MTX_INT_Q4_Q_EMPTY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6598;"	d
+MTX_INT_Q4_Q_EMPTY_SZ	include/ssv6200_aux.h	7445;"	d
+MTX_INT_Q4_Q_EMPTY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6600;"	d
+MTX_INT_Q4_TXOP_RUNOUT_HI	include/ssv6200_aux.h	7449;"	d
+MTX_INT_Q4_TXOP_RUNOUT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6604;"	d
+MTX_INT_Q4_TXOP_RUNOUT_I_MSK	include/ssv6200_aux.h	7447;"	d
+MTX_INT_Q4_TXOP_RUNOUT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6602;"	d
+MTX_INT_Q4_TXOP_RUNOUT_MSK	include/ssv6200_aux.h	7446;"	d
+MTX_INT_Q4_TXOP_RUNOUT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6601;"	d
+MTX_INT_Q4_TXOP_RUNOUT_SFT	include/ssv6200_aux.h	7448;"	d
+MTX_INT_Q4_TXOP_RUNOUT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6603;"	d
+MTX_INT_Q4_TXOP_RUNOUT_SZ	include/ssv6200_aux.h	7450;"	d
+MTX_INT_Q4_TXOP_RUNOUT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6605;"	d
+MTX_INT_Q5_Q_EMPTY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6609;"	d
+MTX_INT_Q5_Q_EMPTY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6607;"	d
+MTX_INT_Q5_Q_EMPTY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6606;"	d
+MTX_INT_Q5_Q_EMPTY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6608;"	d
+MTX_INT_Q5_Q_EMPTY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6610;"	d
+MTX_INT_Q5_TXOP_RUNOUT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6614;"	d
+MTX_INT_Q5_TXOP_RUNOUT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6612;"	d
+MTX_INT_Q5_TXOP_RUNOUT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6611;"	d
+MTX_INT_Q5_TXOP_RUNOUT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6613;"	d
+MTX_INT_Q5_TXOP_RUNOUT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6615;"	d
+MTX_M2M_SLOW_PRD_HI	include/ssv6200_aux.h	7509;"	d
+MTX_M2M_SLOW_PRD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6684;"	d
+MTX_M2M_SLOW_PRD_I_MSK	include/ssv6200_aux.h	7507;"	d
+MTX_M2M_SLOW_PRD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6682;"	d
+MTX_M2M_SLOW_PRD_MSK	include/ssv6200_aux.h	7506;"	d
+MTX_M2M_SLOW_PRD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6681;"	d
+MTX_M2M_SLOW_PRD_SFT	include/ssv6200_aux.h	7508;"	d
+MTX_M2M_SLOW_PRD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6683;"	d
+MTX_M2M_SLOW_PRD_SZ	include/ssv6200_aux.h	7510;"	d
+MTX_M2M_SLOW_PRD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6685;"	d
+MTX_MIB_CNT0_ATTEMPT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6854;"	d
+MTX_MIB_CNT0_ATTEMPT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6852;"	d
+MTX_MIB_CNT0_ATTEMPT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6851;"	d
+MTX_MIB_CNT0_ATTEMPT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6853;"	d
+MTX_MIB_CNT0_ATTEMPT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6855;"	d
+MTX_MIB_CNT0_FRAME_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6849;"	d
+MTX_MIB_CNT0_FRAME_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6847;"	d
+MTX_MIB_CNT0_FRAME_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6846;"	d
+MTX_MIB_CNT0_FRAME_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6848;"	d
+MTX_MIB_CNT0_FRAME_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6850;"	d
+MTX_MIB_CNT0_HI	include/ssv6200_aux.h	7864;"	d
+MTX_MIB_CNT0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6844;"	d
+MTX_MIB_CNT0_I_MSK	include/ssv6200_aux.h	7862;"	d
+MTX_MIB_CNT0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6842;"	d
+MTX_MIB_CNT0_MSK	include/ssv6200_aux.h	7861;"	d
+MTX_MIB_CNT0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6841;"	d
+MTX_MIB_CNT0_SFT	include/ssv6200_aux.h	7863;"	d
+MTX_MIB_CNT0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6843;"	d
+MTX_MIB_CNT0_SUCC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6859;"	d
+MTX_MIB_CNT0_SUCC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6857;"	d
+MTX_MIB_CNT0_SUCC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6856;"	d
+MTX_MIB_CNT0_SUCC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6858;"	d
+MTX_MIB_CNT0_SUCC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6860;"	d
+MTX_MIB_CNT0_SZ	include/ssv6200_aux.h	7865;"	d
+MTX_MIB_CNT0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6845;"	d
+MTX_MIB_CNT1_ATTEMPT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6879;"	d
+MTX_MIB_CNT1_ATTEMPT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6877;"	d
+MTX_MIB_CNT1_ATTEMPT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6876;"	d
+MTX_MIB_CNT1_ATTEMPT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6878;"	d
+MTX_MIB_CNT1_ATTEMPT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6880;"	d
+MTX_MIB_CNT1_FRAME_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6874;"	d
+MTX_MIB_CNT1_FRAME_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6872;"	d
+MTX_MIB_CNT1_FRAME_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6871;"	d
+MTX_MIB_CNT1_FRAME_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6873;"	d
+MTX_MIB_CNT1_FRAME_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6875;"	d
+MTX_MIB_CNT1_HI	include/ssv6200_aux.h	7874;"	d
+MTX_MIB_CNT1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6869;"	d
+MTX_MIB_CNT1_I_MSK	include/ssv6200_aux.h	7872;"	d
+MTX_MIB_CNT1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6867;"	d
+MTX_MIB_CNT1_MSK	include/ssv6200_aux.h	7871;"	d
+MTX_MIB_CNT1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6866;"	d
+MTX_MIB_CNT1_SFT	include/ssv6200_aux.h	7873;"	d
+MTX_MIB_CNT1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6868;"	d
+MTX_MIB_CNT1_SUCC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6884;"	d
+MTX_MIB_CNT1_SUCC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6882;"	d
+MTX_MIB_CNT1_SUCC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6881;"	d
+MTX_MIB_CNT1_SUCC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6883;"	d
+MTX_MIB_CNT1_SUCC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6885;"	d
+MTX_MIB_CNT1_SZ	include/ssv6200_aux.h	7875;"	d
+MTX_MIB_CNT1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6870;"	d
+MTX_MIB_CNT2_ATTEMPT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6904;"	d
+MTX_MIB_CNT2_ATTEMPT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6902;"	d
+MTX_MIB_CNT2_ATTEMPT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6901;"	d
+MTX_MIB_CNT2_ATTEMPT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6903;"	d
+MTX_MIB_CNT2_ATTEMPT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6905;"	d
+MTX_MIB_CNT2_FRAME_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6899;"	d
+MTX_MIB_CNT2_FRAME_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6897;"	d
+MTX_MIB_CNT2_FRAME_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6896;"	d
+MTX_MIB_CNT2_FRAME_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6898;"	d
+MTX_MIB_CNT2_FRAME_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6900;"	d
+MTX_MIB_CNT2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6894;"	d
+MTX_MIB_CNT2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6892;"	d
+MTX_MIB_CNT2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6891;"	d
+MTX_MIB_CNT2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6893;"	d
+MTX_MIB_CNT2_SUCC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6909;"	d
+MTX_MIB_CNT2_SUCC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6907;"	d
+MTX_MIB_CNT2_SUCC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6906;"	d
+MTX_MIB_CNT2_SUCC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6908;"	d
+MTX_MIB_CNT2_SUCC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6910;"	d
+MTX_MIB_CNT2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6895;"	d
+MTX_MIB_CNT3_ATTEMPT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6929;"	d
+MTX_MIB_CNT3_ATTEMPT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6927;"	d
+MTX_MIB_CNT3_ATTEMPT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6926;"	d
+MTX_MIB_CNT3_ATTEMPT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6928;"	d
+MTX_MIB_CNT3_ATTEMPT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6930;"	d
+MTX_MIB_CNT3_FRAME_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6924;"	d
+MTX_MIB_CNT3_FRAME_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6922;"	d
+MTX_MIB_CNT3_FRAME_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6921;"	d
+MTX_MIB_CNT3_FRAME_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6923;"	d
+MTX_MIB_CNT3_FRAME_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6925;"	d
+MTX_MIB_CNT3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6919;"	d
+MTX_MIB_CNT3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6917;"	d
+MTX_MIB_CNT3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6916;"	d
+MTX_MIB_CNT3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6918;"	d
+MTX_MIB_CNT3_SUCC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6934;"	d
+MTX_MIB_CNT3_SUCC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6932;"	d
+MTX_MIB_CNT3_SUCC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6931;"	d
+MTX_MIB_CNT3_SUCC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6933;"	d
+MTX_MIB_CNT3_SUCC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6935;"	d
+MTX_MIB_CNT3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6920;"	d
+MTX_MIB_CNT4_ATTEMPT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6954;"	d
+MTX_MIB_CNT4_ATTEMPT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6952;"	d
+MTX_MIB_CNT4_ATTEMPT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6951;"	d
+MTX_MIB_CNT4_ATTEMPT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6953;"	d
+MTX_MIB_CNT4_ATTEMPT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6955;"	d
+MTX_MIB_CNT4_FRAME_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6949;"	d
+MTX_MIB_CNT4_FRAME_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6947;"	d
+MTX_MIB_CNT4_FRAME_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6946;"	d
+MTX_MIB_CNT4_FRAME_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6948;"	d
+MTX_MIB_CNT4_FRAME_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6950;"	d
+MTX_MIB_CNT4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6944;"	d
+MTX_MIB_CNT4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6942;"	d
+MTX_MIB_CNT4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6941;"	d
+MTX_MIB_CNT4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6943;"	d
+MTX_MIB_CNT4_SUCC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6959;"	d
+MTX_MIB_CNT4_SUCC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6957;"	d
+MTX_MIB_CNT4_SUCC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6956;"	d
+MTX_MIB_CNT4_SUCC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6958;"	d
+MTX_MIB_CNT4_SUCC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6960;"	d
+MTX_MIB_CNT4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6945;"	d
+MTX_MIB_CNT5_ATTEMPT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6979;"	d
+MTX_MIB_CNT5_ATTEMPT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6977;"	d
+MTX_MIB_CNT5_ATTEMPT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6976;"	d
+MTX_MIB_CNT5_ATTEMPT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6978;"	d
+MTX_MIB_CNT5_ATTEMPT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6980;"	d
+MTX_MIB_CNT5_FRAME_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6974;"	d
+MTX_MIB_CNT5_FRAME_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6972;"	d
+MTX_MIB_CNT5_FRAME_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6971;"	d
+MTX_MIB_CNT5_FRAME_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6973;"	d
+MTX_MIB_CNT5_FRAME_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6975;"	d
+MTX_MIB_CNT5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6969;"	d
+MTX_MIB_CNT5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6967;"	d
+MTX_MIB_CNT5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6966;"	d
+MTX_MIB_CNT5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6968;"	d
+MTX_MIB_CNT5_SUCC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6984;"	d
+MTX_MIB_CNT5_SUCC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6982;"	d
+MTX_MIB_CNT5_SUCC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6981;"	d
+MTX_MIB_CNT5_SUCC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6983;"	d
+MTX_MIB_CNT5_SUCC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6985;"	d
+MTX_MIB_CNT5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6970;"	d
+MTX_MIB_CNT6_ATTEMPT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7004;"	d
+MTX_MIB_CNT6_ATTEMPT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7002;"	d
+MTX_MIB_CNT6_ATTEMPT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7001;"	d
+MTX_MIB_CNT6_ATTEMPT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7003;"	d
+MTX_MIB_CNT6_ATTEMPT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7005;"	d
+MTX_MIB_CNT6_FRAME_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6999;"	d
+MTX_MIB_CNT6_FRAME_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6997;"	d
+MTX_MIB_CNT6_FRAME_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6996;"	d
+MTX_MIB_CNT6_FRAME_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6998;"	d
+MTX_MIB_CNT6_FRAME_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7000;"	d
+MTX_MIB_CNT6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6994;"	d
+MTX_MIB_CNT6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6992;"	d
+MTX_MIB_CNT6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6991;"	d
+MTX_MIB_CNT6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6993;"	d
+MTX_MIB_CNT6_SUCC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7009;"	d
+MTX_MIB_CNT6_SUCC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7007;"	d
+MTX_MIB_CNT6_SUCC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7006;"	d
+MTX_MIB_CNT6_SUCC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7008;"	d
+MTX_MIB_CNT6_SUCC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7010;"	d
+MTX_MIB_CNT6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6995;"	d
+MTX_MIB_CNT7_ATTEMPT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7029;"	d
+MTX_MIB_CNT7_ATTEMPT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7027;"	d
+MTX_MIB_CNT7_ATTEMPT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7026;"	d
+MTX_MIB_CNT7_ATTEMPT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7028;"	d
+MTX_MIB_CNT7_ATTEMPT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7030;"	d
+MTX_MIB_CNT7_FRAME_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7024;"	d
+MTX_MIB_CNT7_FRAME_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7022;"	d
+MTX_MIB_CNT7_FRAME_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7021;"	d
+MTX_MIB_CNT7_FRAME_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7023;"	d
+MTX_MIB_CNT7_FRAME_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7025;"	d
+MTX_MIB_CNT7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7019;"	d
+MTX_MIB_CNT7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7017;"	d
+MTX_MIB_CNT7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7016;"	d
+MTX_MIB_CNT7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7018;"	d
+MTX_MIB_CNT7_SUCC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7034;"	d
+MTX_MIB_CNT7_SUCC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7032;"	d
+MTX_MIB_CNT7_SUCC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7031;"	d
+MTX_MIB_CNT7_SUCC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7033;"	d
+MTX_MIB_CNT7_SUCC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7035;"	d
+MTX_MIB_CNT7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7020;"	d
+MTX_MIB_EN0_HI	include/ssv6200_aux.h	7869;"	d
+MTX_MIB_EN0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6864;"	d
+MTX_MIB_EN0_I_MSK	include/ssv6200_aux.h	7867;"	d
+MTX_MIB_EN0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6862;"	d
+MTX_MIB_EN0_MSK	include/ssv6200_aux.h	7866;"	d
+MTX_MIB_EN0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6861;"	d
+MTX_MIB_EN0_SFT	include/ssv6200_aux.h	7868;"	d
+MTX_MIB_EN0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6863;"	d
+MTX_MIB_EN0_SZ	include/ssv6200_aux.h	7870;"	d
+MTX_MIB_EN0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6865;"	d
+MTX_MIB_EN1_HI	include/ssv6200_aux.h	7879;"	d
+MTX_MIB_EN1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6889;"	d
+MTX_MIB_EN1_I_MSK	include/ssv6200_aux.h	7877;"	d
+MTX_MIB_EN1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6887;"	d
+MTX_MIB_EN1_MSK	include/ssv6200_aux.h	7876;"	d
+MTX_MIB_EN1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6886;"	d
+MTX_MIB_EN1_SFT	include/ssv6200_aux.h	7878;"	d
+MTX_MIB_EN1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6888;"	d
+MTX_MIB_EN1_SZ	include/ssv6200_aux.h	7880;"	d
+MTX_MIB_EN1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6890;"	d
+MTX_MIB_EN2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6914;"	d
+MTX_MIB_EN2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6912;"	d
+MTX_MIB_EN2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6911;"	d
+MTX_MIB_EN2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6913;"	d
+MTX_MIB_EN2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6915;"	d
+MTX_MIB_EN3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6939;"	d
+MTX_MIB_EN3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6937;"	d
+MTX_MIB_EN3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6936;"	d
+MTX_MIB_EN3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6938;"	d
+MTX_MIB_EN3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6940;"	d
+MTX_MIB_EN4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6964;"	d
+MTX_MIB_EN4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6962;"	d
+MTX_MIB_EN4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6961;"	d
+MTX_MIB_EN4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6963;"	d
+MTX_MIB_EN4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6965;"	d
+MTX_MIB_EN5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6989;"	d
+MTX_MIB_EN5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6987;"	d
+MTX_MIB_EN5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6986;"	d
+MTX_MIB_EN5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6988;"	d
+MTX_MIB_EN5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6990;"	d
+MTX_MIB_EN6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7014;"	d
+MTX_MIB_EN6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7012;"	d
+MTX_MIB_EN6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7011;"	d
+MTX_MIB_EN6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7013;"	d
+MTX_MIB_EN6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7015;"	d
+MTX_MIB_EN7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7039;"	d
+MTX_MIB_EN7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7037;"	d
+MTX_MIB_EN7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7036;"	d
+MTX_MIB_EN7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7038;"	d
+MTX_MIB_EN7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7040;"	d
+MTX_MISC_CLK_EN_HI	include/ssv6200_aux.h	8994;"	d
+MTX_MISC_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8749;"	d
+MTX_MISC_CLK_EN_I_MSK	include/ssv6200_aux.h	8992;"	d
+MTX_MISC_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8747;"	d
+MTX_MISC_CLK_EN_MSK	include/ssv6200_aux.h	8991;"	d
+MTX_MISC_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8746;"	d
+MTX_MISC_CLK_EN_SFT	include/ssv6200_aux.h	8993;"	d
+MTX_MISC_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8748;"	d
+MTX_MISC_CLK_EN_SZ	include/ssv6200_aux.h	8995;"	d
+MTX_MISC_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8750;"	d
+MTX_MISC_CSR_RST_HI	include/ssv6200_aux.h	8924;"	d
+MTX_MISC_CSR_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8679;"	d
+MTX_MISC_CSR_RST_I_MSK	include/ssv6200_aux.h	8922;"	d
+MTX_MISC_CSR_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8677;"	d
+MTX_MISC_CSR_RST_MSK	include/ssv6200_aux.h	8921;"	d
+MTX_MISC_CSR_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8676;"	d
+MTX_MISC_CSR_RST_SFT	include/ssv6200_aux.h	8923;"	d
+MTX_MISC_CSR_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8678;"	d
+MTX_MISC_CSR_RST_SZ	include/ssv6200_aux.h	8925;"	d
+MTX_MISC_CSR_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8680;"	d
+MTX_MISC_ENG_CLK_EN_HI	include/ssv6200_aux.h	9054;"	d
+MTX_MISC_ENG_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8809;"	d
+MTX_MISC_ENG_CLK_EN_I_MSK	include/ssv6200_aux.h	9052;"	d
+MTX_MISC_ENG_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8807;"	d
+MTX_MISC_ENG_CLK_EN_MSK	include/ssv6200_aux.h	9051;"	d
+MTX_MISC_ENG_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8806;"	d
+MTX_MISC_ENG_CLK_EN_SFT	include/ssv6200_aux.h	9053;"	d
+MTX_MISC_ENG_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8808;"	d
+MTX_MISC_ENG_CLK_EN_SZ	include/ssv6200_aux.h	9055;"	d
+MTX_MISC_ENG_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8810;"	d
+MTX_MISC_ENG_RST_HI	include/ssv6200_aux.h	8869;"	d
+MTX_MISC_ENG_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8624;"	d
+MTX_MISC_ENG_RST_I_MSK	include/ssv6200_aux.h	8867;"	d
+MTX_MISC_ENG_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8622;"	d
+MTX_MISC_ENG_RST_MSK	include/ssv6200_aux.h	8866;"	d
+MTX_MISC_ENG_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8621;"	d
+MTX_MISC_ENG_RST_SFT	include/ssv6200_aux.h	8868;"	d
+MTX_MISC_ENG_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8623;"	d
+MTX_MISC_ENG_RST_SZ	include/ssv6200_aux.h	8870;"	d
+MTX_MISC_ENG_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8625;"	d
+MTX_MISC_SW_RST_HI	include/ssv6200_aux.h	8809;"	d
+MTX_MISC_SW_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8564;"	d
+MTX_MISC_SW_RST_I_MSK	include/ssv6200_aux.h	8807;"	d
+MTX_MISC_SW_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8562;"	d
+MTX_MISC_SW_RST_MSK	include/ssv6200_aux.h	8806;"	d
+MTX_MISC_SW_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8561;"	d
+MTX_MISC_SW_RST_SFT	include/ssv6200_aux.h	8808;"	d
+MTX_MISC_SW_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8563;"	d
+MTX_MISC_SW_RST_SZ	include/ssv6200_aux.h	8810;"	d
+MTX_MISC_SW_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8565;"	d
+MTX_MNG_UPTHOLD_INT_HI	include/ssv6200_aux.h	3549;"	d
+MTX_MNG_UPTHOLD_INT_I_MSK	include/ssv6200_aux.h	3547;"	d
+MTX_MNG_UPTHOLD_INT_MSK	include/ssv6200_aux.h	3546;"	d
+MTX_MNG_UPTHOLD_INT_SFT	include/ssv6200_aux.h	3548;"	d
+MTX_MNG_UPTHOLD_INT_SZ	include/ssv6200_aux.h	3550;"	d
+MTX_MTX2PHY_SLOW_HI	include/ssv6200_aux.h	7504;"	d
+MTX_MTX2PHY_SLOW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6679;"	d
+MTX_MTX2PHY_SLOW_I_MSK	include/ssv6200_aux.h	7502;"	d
+MTX_MTX2PHY_SLOW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6677;"	d
+MTX_MTX2PHY_SLOW_MSK	include/ssv6200_aux.h	7501;"	d
+MTX_MTX2PHY_SLOW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6676;"	d
+MTX_MTX2PHY_SLOW_SFT	include/ssv6200_aux.h	7503;"	d
+MTX_MTX2PHY_SLOW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6678;"	d
+MTX_MTX2PHY_SLOW_SZ	include/ssv6200_aux.h	7505;"	d
+MTX_MTX2PHY_SLOW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6680;"	d
+MTX_MULTI_RETRY_HI	include/ssv6200_aux.h	9459;"	d
+MTX_MULTI_RETRY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9294;"	d
+MTX_MULTI_RETRY_I_MSK	include/ssv6200_aux.h	9457;"	d
+MTX_MULTI_RETRY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9292;"	d
+MTX_MULTI_RETRY_MSK	include/ssv6200_aux.h	9456;"	d
+MTX_MULTI_RETRY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9291;"	d
+MTX_MULTI_RETRY_SFT	include/ssv6200_aux.h	9458;"	d
+MTX_MULTI_RETRY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9293;"	d
+MTX_MULTI_RETRY_SZ	include/ssv6200_aux.h	9460;"	d
+MTX_MULTI_RETRY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9295;"	d
+MTX_NAV_HI	include/ssv6200_aux.h	7859;"	d
+MTX_NAV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7444;"	d
+MTX_NAV_I_MSK	include/ssv6200_aux.h	7857;"	d
+MTX_NAV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7442;"	d
+MTX_NAV_MSK	include/ssv6200_aux.h	7856;"	d
+MTX_NAV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7441;"	d
+MTX_NAV_SFT	include/ssv6200_aux.h	7858;"	d
+MTX_NAV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7443;"	d
+MTX_NAV_SZ	include/ssv6200_aux.h	7860;"	d
+MTX_NAV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7445;"	d
+MTX_QUE0_CSR_RST_HI	include/ssv6200_aux.h	8929;"	d
+MTX_QUE0_CSR_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8684;"	d
+MTX_QUE0_CSR_RST_I_MSK	include/ssv6200_aux.h	8927;"	d
+MTX_QUE0_CSR_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8682;"	d
+MTX_QUE0_CSR_RST_MSK	include/ssv6200_aux.h	8926;"	d
+MTX_QUE0_CSR_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8681;"	d
+MTX_QUE0_CSR_RST_SFT	include/ssv6200_aux.h	8928;"	d
+MTX_QUE0_CSR_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8683;"	d
+MTX_QUE0_CSR_RST_SZ	include/ssv6200_aux.h	8930;"	d
+MTX_QUE0_CSR_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8685;"	d
+MTX_QUE1_CSR_RST_HI	include/ssv6200_aux.h	8934;"	d
+MTX_QUE1_CSR_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8689;"	d
+MTX_QUE1_CSR_RST_I_MSK	include/ssv6200_aux.h	8932;"	d
+MTX_QUE1_CSR_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8687;"	d
+MTX_QUE1_CSR_RST_MSK	include/ssv6200_aux.h	8931;"	d
+MTX_QUE1_CSR_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8686;"	d
+MTX_QUE1_CSR_RST_SFT	include/ssv6200_aux.h	8933;"	d
+MTX_QUE1_CSR_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8688;"	d
+MTX_QUE1_CSR_RST_SZ	include/ssv6200_aux.h	8935;"	d
+MTX_QUE1_CSR_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8690;"	d
+MTX_QUE2_CSR_RST_HI	include/ssv6200_aux.h	8939;"	d
+MTX_QUE2_CSR_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8694;"	d
+MTX_QUE2_CSR_RST_I_MSK	include/ssv6200_aux.h	8937;"	d
+MTX_QUE2_CSR_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8692;"	d
+MTX_QUE2_CSR_RST_MSK	include/ssv6200_aux.h	8936;"	d
+MTX_QUE2_CSR_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8691;"	d
+MTX_QUE2_CSR_RST_SFT	include/ssv6200_aux.h	8938;"	d
+MTX_QUE2_CSR_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8693;"	d
+MTX_QUE2_CSR_RST_SZ	include/ssv6200_aux.h	8940;"	d
+MTX_QUE2_CSR_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8695;"	d
+MTX_QUE3_CSR_RST_HI	include/ssv6200_aux.h	8944;"	d
+MTX_QUE3_CSR_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8699;"	d
+MTX_QUE3_CSR_RST_I_MSK	include/ssv6200_aux.h	8942;"	d
+MTX_QUE3_CSR_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8697;"	d
+MTX_QUE3_CSR_RST_MSK	include/ssv6200_aux.h	8941;"	d
+MTX_QUE3_CSR_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8696;"	d
+MTX_QUE3_CSR_RST_SFT	include/ssv6200_aux.h	8943;"	d
+MTX_QUE3_CSR_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8698;"	d
+MTX_QUE3_CSR_RST_SZ	include/ssv6200_aux.h	8945;"	d
+MTX_QUE3_CSR_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8700;"	d
+MTX_QUE4_CSR_RST_HI	include/ssv6200_aux.h	8949;"	d
+MTX_QUE4_CSR_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8704;"	d
+MTX_QUE4_CSR_RST_I_MSK	include/ssv6200_aux.h	8947;"	d
+MTX_QUE4_CSR_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8702;"	d
+MTX_QUE4_CSR_RST_MSK	include/ssv6200_aux.h	8946;"	d
+MTX_QUE4_CSR_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8701;"	d
+MTX_QUE4_CSR_RST_SFT	include/ssv6200_aux.h	8948;"	d
+MTX_QUE4_CSR_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8703;"	d
+MTX_QUE4_CSR_RST_SZ	include/ssv6200_aux.h	8950;"	d
+MTX_QUE4_CSR_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8705;"	d
+MTX_QUE5_CSR_RST_HI	include/ssv6200_aux.h	8954;"	d
+MTX_QUE5_CSR_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8709;"	d
+MTX_QUE5_CSR_RST_I_MSK	include/ssv6200_aux.h	8952;"	d
+MTX_QUE5_CSR_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8707;"	d
+MTX_QUE5_CSR_RST_MSK	include/ssv6200_aux.h	8951;"	d
+MTX_QUE5_CSR_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8706;"	d
+MTX_QUE5_CSR_RST_SFT	include/ssv6200_aux.h	8953;"	d
+MTX_QUE5_CSR_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8708;"	d
+MTX_QUE5_CSR_RST_SZ	include/ssv6200_aux.h	8955;"	d
+MTX_QUE5_CSR_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8710;"	d
+MTX_QUE_CLK_EN_HI	include/ssv6200_aux.h	8999;"	d
+MTX_QUE_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8754;"	d
+MTX_QUE_CLK_EN_I_MSK	include/ssv6200_aux.h	8997;"	d
+MTX_QUE_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8752;"	d
+MTX_QUE_CLK_EN_MSK	include/ssv6200_aux.h	8996;"	d
+MTX_QUE_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8751;"	d
+MTX_QUE_CLK_EN_SFT	include/ssv6200_aux.h	8998;"	d
+MTX_QUE_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8753;"	d
+MTX_QUE_CLK_EN_SZ	include/ssv6200_aux.h	9000;"	d
+MTX_QUE_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8755;"	d
+MTX_QUE_ENG_CLK_EN_HI	include/ssv6200_aux.h	9059;"	d
+MTX_QUE_ENG_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8814;"	d
+MTX_QUE_ENG_CLK_EN_I_MSK	include/ssv6200_aux.h	9057;"	d
+MTX_QUE_ENG_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8812;"	d
+MTX_QUE_ENG_CLK_EN_MSK	include/ssv6200_aux.h	9056;"	d
+MTX_QUE_ENG_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8811;"	d
+MTX_QUE_ENG_CLK_EN_SFT	include/ssv6200_aux.h	9058;"	d
+MTX_QUE_ENG_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8813;"	d
+MTX_QUE_ENG_CLK_EN_SZ	include/ssv6200_aux.h	9060;"	d
+MTX_QUE_ENG_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8815;"	d
+MTX_QUE_ENG_RST_HI	include/ssv6200_aux.h	8874;"	d
+MTX_QUE_ENG_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8629;"	d
+MTX_QUE_ENG_RST_I_MSK	include/ssv6200_aux.h	8872;"	d
+MTX_QUE_ENG_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8627;"	d
+MTX_QUE_ENG_RST_MSK	include/ssv6200_aux.h	8871;"	d
+MTX_QUE_ENG_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8626;"	d
+MTX_QUE_ENG_RST_SFT	include/ssv6200_aux.h	8873;"	d
+MTX_QUE_ENG_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8628;"	d
+MTX_QUE_ENG_RST_SZ	include/ssv6200_aux.h	8875;"	d
+MTX_QUE_ENG_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8630;"	d
+MTX_QUE_SW_RST_HI	include/ssv6200_aux.h	8814;"	d
+MTX_QUE_SW_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8569;"	d
+MTX_QUE_SW_RST_I_MSK	include/ssv6200_aux.h	8812;"	d
+MTX_QUE_SW_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8567;"	d
+MTX_QUE_SW_RST_MSK	include/ssv6200_aux.h	8811;"	d
+MTX_QUE_SW_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8566;"	d
+MTX_QUE_SW_RST_SFT	include/ssv6200_aux.h	8813;"	d
+MTX_QUE_SW_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8568;"	d
+MTX_QUE_SW_RST_SZ	include/ssv6200_aux.h	8815;"	d
+MTX_QUE_SW_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8570;"	d
+MTX_Q_REQ_HI	include/ssv6200_aux.h	7724;"	d
+MTX_Q_REQ_I_MSK	include/ssv6200_aux.h	7722;"	d
+MTX_Q_REQ_MSK	include/ssv6200_aux.h	7721;"	d
+MTX_Q_REQ_SFT	include/ssv6200_aux.h	7723;"	d
+MTX_Q_REQ_SZ	include/ssv6200_aux.h	7725;"	d
+MTX_RATERPT_HWID_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7134;"	d
+MTX_RATERPT_HWID_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7132;"	d
+MTX_RATERPT_HWID_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7131;"	d
+MTX_RATERPT_HWID_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7133;"	d
+MTX_RATERPT_HWID_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7135;"	d
+MTX_RAW_DATA_MODE_HI	include/ssv6200_aux.h	7524;"	d
+MTX_RAW_DATA_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6699;"	d
+MTX_RAW_DATA_MODE_I_MSK	include/ssv6200_aux.h	7522;"	d
+MTX_RAW_DATA_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6697;"	d
+MTX_RAW_DATA_MODE_MSK	include/ssv6200_aux.h	7521;"	d
+MTX_RAW_DATA_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6696;"	d
+MTX_RAW_DATA_MODE_SFT	include/ssv6200_aux.h	7523;"	d
+MTX_RAW_DATA_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6698;"	d
+MTX_RAW_DATA_MODE_SZ	include/ssv6200_aux.h	7525;"	d
+MTX_RAW_DATA_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6700;"	d
+MTX_RESPFRM_INFO_00_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8089;"	d
+MTX_RESPFRM_INFO_00_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8087;"	d
+MTX_RESPFRM_INFO_00_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8086;"	d
+MTX_RESPFRM_INFO_00_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8088;"	d
+MTX_RESPFRM_INFO_00_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8090;"	d
+MTX_RESPFRM_INFO_01_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8094;"	d
+MTX_RESPFRM_INFO_01_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8092;"	d
+MTX_RESPFRM_INFO_01_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8091;"	d
+MTX_RESPFRM_INFO_01_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8093;"	d
+MTX_RESPFRM_INFO_01_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8095;"	d
+MTX_RESPFRM_INFO_02_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8099;"	d
+MTX_RESPFRM_INFO_02_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8097;"	d
+MTX_RESPFRM_INFO_02_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8096;"	d
+MTX_RESPFRM_INFO_02_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8098;"	d
+MTX_RESPFRM_INFO_02_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8100;"	d
+MTX_RESPFRM_INFO_03_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8104;"	d
+MTX_RESPFRM_INFO_03_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8102;"	d
+MTX_RESPFRM_INFO_03_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8101;"	d
+MTX_RESPFRM_INFO_03_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8103;"	d
+MTX_RESPFRM_INFO_03_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8105;"	d
+MTX_RESPFRM_INFO_11_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8109;"	d
+MTX_RESPFRM_INFO_11_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8107;"	d
+MTX_RESPFRM_INFO_11_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8106;"	d
+MTX_RESPFRM_INFO_11_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8108;"	d
+MTX_RESPFRM_INFO_11_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8110;"	d
+MTX_RESPFRM_INFO_12_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8114;"	d
+MTX_RESPFRM_INFO_12_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8112;"	d
+MTX_RESPFRM_INFO_12_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8111;"	d
+MTX_RESPFRM_INFO_12_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8113;"	d
+MTX_RESPFRM_INFO_12_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8115;"	d
+MTX_RESPFRM_INFO_13_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8119;"	d
+MTX_RESPFRM_INFO_13_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8117;"	d
+MTX_RESPFRM_INFO_13_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8116;"	d
+MTX_RESPFRM_INFO_13_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8118;"	d
+MTX_RESPFRM_INFO_13_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8120;"	d
+MTX_RESPFRM_INFO_90_B0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8124;"	d
+MTX_RESPFRM_INFO_90_B0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8122;"	d
+MTX_RESPFRM_INFO_90_B0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8121;"	d
+MTX_RESPFRM_INFO_90_B0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8123;"	d
+MTX_RESPFRM_INFO_90_B0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8125;"	d
+MTX_RESPFRM_INFO_91_B1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8129;"	d
+MTX_RESPFRM_INFO_91_B1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8127;"	d
+MTX_RESPFRM_INFO_91_B1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8126;"	d
+MTX_RESPFRM_INFO_91_B1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8128;"	d
+MTX_RESPFRM_INFO_91_B1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8130;"	d
+MTX_RESPFRM_INFO_92_B2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8134;"	d
+MTX_RESPFRM_INFO_92_B2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8132;"	d
+MTX_RESPFRM_INFO_92_B2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8131;"	d
+MTX_RESPFRM_INFO_92_B2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8133;"	d
+MTX_RESPFRM_INFO_92_B2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8135;"	d
+MTX_RESPFRM_INFO_93_B3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8139;"	d
+MTX_RESPFRM_INFO_93_B3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8137;"	d
+MTX_RESPFRM_INFO_93_B3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8136;"	d
+MTX_RESPFRM_INFO_93_B3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8138;"	d
+MTX_RESPFRM_INFO_93_B3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8140;"	d
+MTX_RESPFRM_INFO_94_B4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8144;"	d
+MTX_RESPFRM_INFO_94_B4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8142;"	d
+MTX_RESPFRM_INFO_94_B4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8141;"	d
+MTX_RESPFRM_INFO_94_B4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8143;"	d
+MTX_RESPFRM_INFO_94_B4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8145;"	d
+MTX_RESPFRM_INFO_95_B5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8149;"	d
+MTX_RESPFRM_INFO_95_B5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8147;"	d
+MTX_RESPFRM_INFO_95_B5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8146;"	d
+MTX_RESPFRM_INFO_95_B5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8148;"	d
+MTX_RESPFRM_INFO_95_B5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8150;"	d
+MTX_RESPFRM_INFO_96_B6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8154;"	d
+MTX_RESPFRM_INFO_96_B6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8152;"	d
+MTX_RESPFRM_INFO_96_B6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8151;"	d
+MTX_RESPFRM_INFO_96_B6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8153;"	d
+MTX_RESPFRM_INFO_96_B6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8155;"	d
+MTX_RESPFRM_INFO_97_B7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8159;"	d
+MTX_RESPFRM_INFO_97_B7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8157;"	d
+MTX_RESPFRM_INFO_97_B7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8156;"	d
+MTX_RESPFRM_INFO_97_B7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8158;"	d
+MTX_RESPFRM_INFO_97_B7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8160;"	d
+MTX_RESPFRM_INFO_C0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8164;"	d
+MTX_RESPFRM_INFO_C0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8162;"	d
+MTX_RESPFRM_INFO_C0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8161;"	d
+MTX_RESPFRM_INFO_C0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8163;"	d
+MTX_RESPFRM_INFO_C0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8165;"	d
+MTX_RESPFRM_INFO_C1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8169;"	d
+MTX_RESPFRM_INFO_C1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8167;"	d
+MTX_RESPFRM_INFO_C1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8166;"	d
+MTX_RESPFRM_INFO_C1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8168;"	d
+MTX_RESPFRM_INFO_C1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8170;"	d
+MTX_RESPFRM_INFO_C2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8174;"	d
+MTX_RESPFRM_INFO_C2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8172;"	d
+MTX_RESPFRM_INFO_C2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8171;"	d
+MTX_RESPFRM_INFO_C2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8173;"	d
+MTX_RESPFRM_INFO_C2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8175;"	d
+MTX_RESPFRM_INFO_C3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8179;"	d
+MTX_RESPFRM_INFO_C3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8177;"	d
+MTX_RESPFRM_INFO_C3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8176;"	d
+MTX_RESPFRM_INFO_C3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8178;"	d
+MTX_RESPFRM_INFO_C3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8180;"	d
+MTX_RESPFRM_INFO_C4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8184;"	d
+MTX_RESPFRM_INFO_C4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8182;"	d
+MTX_RESPFRM_INFO_C4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8181;"	d
+MTX_RESPFRM_INFO_C4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8183;"	d
+MTX_RESPFRM_INFO_C4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8185;"	d
+MTX_RESPFRM_INFO_C5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8189;"	d
+MTX_RESPFRM_INFO_C5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8187;"	d
+MTX_RESPFRM_INFO_C5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8186;"	d
+MTX_RESPFRM_INFO_C5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8188;"	d
+MTX_RESPFRM_INFO_C5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8190;"	d
+MTX_RESPFRM_INFO_C6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8194;"	d
+MTX_RESPFRM_INFO_C6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8192;"	d
+MTX_RESPFRM_INFO_C6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8191;"	d
+MTX_RESPFRM_INFO_C6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8193;"	d
+MTX_RESPFRM_INFO_C6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8195;"	d
+MTX_RESPFRM_INFO_C7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8199;"	d
+MTX_RESPFRM_INFO_C7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8197;"	d
+MTX_RESPFRM_INFO_C7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8196;"	d
+MTX_RESPFRM_INFO_C7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8198;"	d
+MTX_RESPFRM_INFO_C7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8200;"	d
+MTX_RESPFRM_INFO_D0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8204;"	d
+MTX_RESPFRM_INFO_D0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8202;"	d
+MTX_RESPFRM_INFO_D0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8201;"	d
+MTX_RESPFRM_INFO_D0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8203;"	d
+MTX_RESPFRM_INFO_D0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8205;"	d
+MTX_RESPFRM_INFO_D1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8209;"	d
+MTX_RESPFRM_INFO_D1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8207;"	d
+MTX_RESPFRM_INFO_D1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8206;"	d
+MTX_RESPFRM_INFO_D1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8208;"	d
+MTX_RESPFRM_INFO_D1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8210;"	d
+MTX_RESPFRM_INFO_D2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8214;"	d
+MTX_RESPFRM_INFO_D2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8212;"	d
+MTX_RESPFRM_INFO_D2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8211;"	d
+MTX_RESPFRM_INFO_D2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8213;"	d
+MTX_RESPFRM_INFO_D2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8215;"	d
+MTX_RESPFRM_INFO_D3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8219;"	d
+MTX_RESPFRM_INFO_D3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8217;"	d
+MTX_RESPFRM_INFO_D3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8216;"	d
+MTX_RESPFRM_INFO_D3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8218;"	d
+MTX_RESPFRM_INFO_D3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8220;"	d
+MTX_RESPFRM_INFO_D4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8224;"	d
+MTX_RESPFRM_INFO_D4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8222;"	d
+MTX_RESPFRM_INFO_D4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8221;"	d
+MTX_RESPFRM_INFO_D4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8223;"	d
+MTX_RESPFRM_INFO_D4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8225;"	d
+MTX_RESPFRM_INFO_D5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8229;"	d
+MTX_RESPFRM_INFO_D5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8227;"	d
+MTX_RESPFRM_INFO_D5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8226;"	d
+MTX_RESPFRM_INFO_D5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8228;"	d
+MTX_RESPFRM_INFO_D5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8230;"	d
+MTX_RESPFRM_INFO_D6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8234;"	d
+MTX_RESPFRM_INFO_D6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8232;"	d
+MTX_RESPFRM_INFO_D6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8231;"	d
+MTX_RESPFRM_INFO_D6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8233;"	d
+MTX_RESPFRM_INFO_D6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8235;"	d
+MTX_RESPFRM_INFO_D7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8239;"	d
+MTX_RESPFRM_INFO_D7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8237;"	d
+MTX_RESPFRM_INFO_D7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8236;"	d
+MTX_RESPFRM_INFO_D7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8238;"	d
+MTX_RESPFRM_INFO_D7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8240;"	d
+MTX_RESPFRM_INFO_D8_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8244;"	d
+MTX_RESPFRM_INFO_D8_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8242;"	d
+MTX_RESPFRM_INFO_D8_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8241;"	d
+MTX_RESPFRM_INFO_D8_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8243;"	d
+MTX_RESPFRM_INFO_D8_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8245;"	d
+MTX_RESPFRM_INFO_D9_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8249;"	d
+MTX_RESPFRM_INFO_D9_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8247;"	d
+MTX_RESPFRM_INFO_D9_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8246;"	d
+MTX_RESPFRM_INFO_D9_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8248;"	d
+MTX_RESPFRM_INFO_D9_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8250;"	d
+MTX_RESPFRM_INFO_DA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8254;"	d
+MTX_RESPFRM_INFO_DA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8252;"	d
+MTX_RESPFRM_INFO_DA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8251;"	d
+MTX_RESPFRM_INFO_DA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8253;"	d
+MTX_RESPFRM_INFO_DA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8255;"	d
+MTX_RESPFRM_INFO_DB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8259;"	d
+MTX_RESPFRM_INFO_DB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8257;"	d
+MTX_RESPFRM_INFO_DB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8256;"	d
+MTX_RESPFRM_INFO_DB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8258;"	d
+MTX_RESPFRM_INFO_DB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8260;"	d
+MTX_RESPFRM_INFO_DC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8264;"	d
+MTX_RESPFRM_INFO_DC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8262;"	d
+MTX_RESPFRM_INFO_DC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8261;"	d
+MTX_RESPFRM_INFO_DC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8263;"	d
+MTX_RESPFRM_INFO_DC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8265;"	d
+MTX_RESPFRM_INFO_DD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8269;"	d
+MTX_RESPFRM_INFO_DD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8267;"	d
+MTX_RESPFRM_INFO_DD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8266;"	d
+MTX_RESPFRM_INFO_DD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8268;"	d
+MTX_RESPFRM_INFO_DD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8270;"	d
+MTX_RESPFRM_INFO_DE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8274;"	d
+MTX_RESPFRM_INFO_DE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8272;"	d
+MTX_RESPFRM_INFO_DE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8271;"	d
+MTX_RESPFRM_INFO_DE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8273;"	d
+MTX_RESPFRM_INFO_DE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8275;"	d
+MTX_RESPFRM_INFO_DF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8279;"	d
+MTX_RESPFRM_INFO_DF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8277;"	d
+MTX_RESPFRM_INFO_DF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8276;"	d
+MTX_RESPFRM_INFO_DF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8278;"	d
+MTX_RESPFRM_INFO_DF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8280;"	d
+MTX_RESPFRM_INFO_EXCEPTION_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8084;"	d
+MTX_RESPFRM_INFO_EXCEPTION_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8082;"	d
+MTX_RESPFRM_INFO_EXCEPTION_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8081;"	d
+MTX_RESPFRM_INFO_EXCEPTION_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8083;"	d
+MTX_RESPFRM_INFO_EXCEPTION_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8085;"	d
+MTX_RESPFRM_RATE_00_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7889;"	d
+MTX_RESPFRM_RATE_00_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7887;"	d
+MTX_RESPFRM_RATE_00_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7886;"	d
+MTX_RESPFRM_RATE_00_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7888;"	d
+MTX_RESPFRM_RATE_00_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7890;"	d
+MTX_RESPFRM_RATE_01_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7894;"	d
+MTX_RESPFRM_RATE_01_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7892;"	d
+MTX_RESPFRM_RATE_01_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7891;"	d
+MTX_RESPFRM_RATE_01_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7893;"	d
+MTX_RESPFRM_RATE_01_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7895;"	d
+MTX_RESPFRM_RATE_02_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7899;"	d
+MTX_RESPFRM_RATE_02_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7897;"	d
+MTX_RESPFRM_RATE_02_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7896;"	d
+MTX_RESPFRM_RATE_02_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7898;"	d
+MTX_RESPFRM_RATE_02_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7900;"	d
+MTX_RESPFRM_RATE_03_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7904;"	d
+MTX_RESPFRM_RATE_03_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7902;"	d
+MTX_RESPFRM_RATE_03_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7901;"	d
+MTX_RESPFRM_RATE_03_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7903;"	d
+MTX_RESPFRM_RATE_03_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7905;"	d
+MTX_RESPFRM_RATE_11_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7909;"	d
+MTX_RESPFRM_RATE_11_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7907;"	d
+MTX_RESPFRM_RATE_11_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7906;"	d
+MTX_RESPFRM_RATE_11_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7908;"	d
+MTX_RESPFRM_RATE_11_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7910;"	d
+MTX_RESPFRM_RATE_12_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7914;"	d
+MTX_RESPFRM_RATE_12_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7912;"	d
+MTX_RESPFRM_RATE_12_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7911;"	d
+MTX_RESPFRM_RATE_12_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7913;"	d
+MTX_RESPFRM_RATE_12_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7915;"	d
+MTX_RESPFRM_RATE_13_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7919;"	d
+MTX_RESPFRM_RATE_13_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7917;"	d
+MTX_RESPFRM_RATE_13_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7916;"	d
+MTX_RESPFRM_RATE_13_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7918;"	d
+MTX_RESPFRM_RATE_13_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7920;"	d
+MTX_RESPFRM_RATE_90_B0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7924;"	d
+MTX_RESPFRM_RATE_90_B0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7922;"	d
+MTX_RESPFRM_RATE_90_B0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7921;"	d
+MTX_RESPFRM_RATE_90_B0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7923;"	d
+MTX_RESPFRM_RATE_90_B0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7925;"	d
+MTX_RESPFRM_RATE_91_B1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7929;"	d
+MTX_RESPFRM_RATE_91_B1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7927;"	d
+MTX_RESPFRM_RATE_91_B1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7926;"	d
+MTX_RESPFRM_RATE_91_B1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7928;"	d
+MTX_RESPFRM_RATE_91_B1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7930;"	d
+MTX_RESPFRM_RATE_92_B2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7934;"	d
+MTX_RESPFRM_RATE_92_B2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7932;"	d
+MTX_RESPFRM_RATE_92_B2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7931;"	d
+MTX_RESPFRM_RATE_92_B2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7933;"	d
+MTX_RESPFRM_RATE_92_B2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7935;"	d
+MTX_RESPFRM_RATE_93_B3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7939;"	d
+MTX_RESPFRM_RATE_93_B3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7937;"	d
+MTX_RESPFRM_RATE_93_B3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7936;"	d
+MTX_RESPFRM_RATE_93_B3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7938;"	d
+MTX_RESPFRM_RATE_93_B3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7940;"	d
+MTX_RESPFRM_RATE_94_B4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7944;"	d
+MTX_RESPFRM_RATE_94_B4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7942;"	d
+MTX_RESPFRM_RATE_94_B4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7941;"	d
+MTX_RESPFRM_RATE_94_B4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7943;"	d
+MTX_RESPFRM_RATE_94_B4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7945;"	d
+MTX_RESPFRM_RATE_95_B5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7949;"	d
+MTX_RESPFRM_RATE_95_B5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7947;"	d
+MTX_RESPFRM_RATE_95_B5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7946;"	d
+MTX_RESPFRM_RATE_95_B5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7948;"	d
+MTX_RESPFRM_RATE_95_B5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7950;"	d
+MTX_RESPFRM_RATE_96_B6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7954;"	d
+MTX_RESPFRM_RATE_96_B6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7952;"	d
+MTX_RESPFRM_RATE_96_B6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7951;"	d
+MTX_RESPFRM_RATE_96_B6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7953;"	d
+MTX_RESPFRM_RATE_96_B6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7955;"	d
+MTX_RESPFRM_RATE_97_B7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7959;"	d
+MTX_RESPFRM_RATE_97_B7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7957;"	d
+MTX_RESPFRM_RATE_97_B7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7956;"	d
+MTX_RESPFRM_RATE_97_B7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7958;"	d
+MTX_RESPFRM_RATE_97_B7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7960;"	d
+MTX_RESPFRM_RATE_C0_E0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7964;"	d
+MTX_RESPFRM_RATE_C0_E0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7962;"	d
+MTX_RESPFRM_RATE_C0_E0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7961;"	d
+MTX_RESPFRM_RATE_C0_E0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7963;"	d
+MTX_RESPFRM_RATE_C0_E0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7965;"	d
+MTX_RESPFRM_RATE_C1_E1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7969;"	d
+MTX_RESPFRM_RATE_C1_E1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7967;"	d
+MTX_RESPFRM_RATE_C1_E1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7966;"	d
+MTX_RESPFRM_RATE_C1_E1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7968;"	d
+MTX_RESPFRM_RATE_C1_E1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7970;"	d
+MTX_RESPFRM_RATE_C2_E2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7974;"	d
+MTX_RESPFRM_RATE_C2_E2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7972;"	d
+MTX_RESPFRM_RATE_C2_E2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7971;"	d
+MTX_RESPFRM_RATE_C2_E2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7973;"	d
+MTX_RESPFRM_RATE_C2_E2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7975;"	d
+MTX_RESPFRM_RATE_C3_E3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7979;"	d
+MTX_RESPFRM_RATE_C3_E3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7977;"	d
+MTX_RESPFRM_RATE_C3_E3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7976;"	d
+MTX_RESPFRM_RATE_C3_E3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7978;"	d
+MTX_RESPFRM_RATE_C3_E3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7980;"	d
+MTX_RESPFRM_RATE_C4_E4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7984;"	d
+MTX_RESPFRM_RATE_C4_E4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7982;"	d
+MTX_RESPFRM_RATE_C4_E4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7981;"	d
+MTX_RESPFRM_RATE_C4_E4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7983;"	d
+MTX_RESPFRM_RATE_C4_E4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7985;"	d
+MTX_RESPFRM_RATE_C5_E5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7989;"	d
+MTX_RESPFRM_RATE_C5_E5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7987;"	d
+MTX_RESPFRM_RATE_C5_E5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7986;"	d
+MTX_RESPFRM_RATE_C5_E5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7988;"	d
+MTX_RESPFRM_RATE_C5_E5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7990;"	d
+MTX_RESPFRM_RATE_C6_E6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7994;"	d
+MTX_RESPFRM_RATE_C6_E6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7992;"	d
+MTX_RESPFRM_RATE_C6_E6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7991;"	d
+MTX_RESPFRM_RATE_C6_E6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7993;"	d
+MTX_RESPFRM_RATE_C6_E6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7995;"	d
+MTX_RESPFRM_RATE_C7_E7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7999;"	d
+MTX_RESPFRM_RATE_C7_E7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7997;"	d
+MTX_RESPFRM_RATE_C7_E7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7996;"	d
+MTX_RESPFRM_RATE_C7_E7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7998;"	d
+MTX_RESPFRM_RATE_C7_E7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8000;"	d
+MTX_RESPFRM_RATE_D0_F0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8004;"	d
+MTX_RESPFRM_RATE_D0_F0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8002;"	d
+MTX_RESPFRM_RATE_D0_F0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8001;"	d
+MTX_RESPFRM_RATE_D0_F0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8003;"	d
+MTX_RESPFRM_RATE_D0_F0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8005;"	d
+MTX_RESPFRM_RATE_D1_F1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8009;"	d
+MTX_RESPFRM_RATE_D1_F1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8007;"	d
+MTX_RESPFRM_RATE_D1_F1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8006;"	d
+MTX_RESPFRM_RATE_D1_F1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8008;"	d
+MTX_RESPFRM_RATE_D1_F1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8010;"	d
+MTX_RESPFRM_RATE_D2_F2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8014;"	d
+MTX_RESPFRM_RATE_D2_F2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8012;"	d
+MTX_RESPFRM_RATE_D2_F2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8011;"	d
+MTX_RESPFRM_RATE_D2_F2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8013;"	d
+MTX_RESPFRM_RATE_D2_F2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8015;"	d
+MTX_RESPFRM_RATE_D3_F3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8019;"	d
+MTX_RESPFRM_RATE_D3_F3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8017;"	d
+MTX_RESPFRM_RATE_D3_F3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8016;"	d
+MTX_RESPFRM_RATE_D3_F3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8018;"	d
+MTX_RESPFRM_RATE_D3_F3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8020;"	d
+MTX_RESPFRM_RATE_D4_F4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8024;"	d
+MTX_RESPFRM_RATE_D4_F4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8022;"	d
+MTX_RESPFRM_RATE_D4_F4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8021;"	d
+MTX_RESPFRM_RATE_D4_F4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8023;"	d
+MTX_RESPFRM_RATE_D4_F4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8025;"	d
+MTX_RESPFRM_RATE_D5_F5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8029;"	d
+MTX_RESPFRM_RATE_D5_F5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8027;"	d
+MTX_RESPFRM_RATE_D5_F5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8026;"	d
+MTX_RESPFRM_RATE_D5_F5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8028;"	d
+MTX_RESPFRM_RATE_D5_F5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8030;"	d
+MTX_RESPFRM_RATE_D6_F6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8034;"	d
+MTX_RESPFRM_RATE_D6_F6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8032;"	d
+MTX_RESPFRM_RATE_D6_F6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8031;"	d
+MTX_RESPFRM_RATE_D6_F6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8033;"	d
+MTX_RESPFRM_RATE_D6_F6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8035;"	d
+MTX_RESPFRM_RATE_D7_F7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8039;"	d
+MTX_RESPFRM_RATE_D7_F7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8037;"	d
+MTX_RESPFRM_RATE_D7_F7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8036;"	d
+MTX_RESPFRM_RATE_D7_F7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8038;"	d
+MTX_RESPFRM_RATE_D7_F7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8040;"	d
+MTX_RESPFRM_RATE_D8_F8_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8044;"	d
+MTX_RESPFRM_RATE_D8_F8_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8042;"	d
+MTX_RESPFRM_RATE_D8_F8_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8041;"	d
+MTX_RESPFRM_RATE_D8_F8_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8043;"	d
+MTX_RESPFRM_RATE_D8_F8_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8045;"	d
+MTX_RESPFRM_RATE_D9_F9_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8049;"	d
+MTX_RESPFRM_RATE_D9_F9_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8047;"	d
+MTX_RESPFRM_RATE_D9_F9_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8046;"	d
+MTX_RESPFRM_RATE_D9_F9_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8048;"	d
+MTX_RESPFRM_RATE_D9_F9_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8050;"	d
+MTX_RESPFRM_RATE_DA_FA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8054;"	d
+MTX_RESPFRM_RATE_DA_FA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8052;"	d
+MTX_RESPFRM_RATE_DA_FA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8051;"	d
+MTX_RESPFRM_RATE_DA_FA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8053;"	d
+MTX_RESPFRM_RATE_DA_FA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8055;"	d
+MTX_RESPFRM_RATE_DB_FB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8059;"	d
+MTX_RESPFRM_RATE_DB_FB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8057;"	d
+MTX_RESPFRM_RATE_DB_FB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8056;"	d
+MTX_RESPFRM_RATE_DB_FB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8058;"	d
+MTX_RESPFRM_RATE_DB_FB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8060;"	d
+MTX_RESPFRM_RATE_DC_FC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8064;"	d
+MTX_RESPFRM_RATE_DC_FC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8062;"	d
+MTX_RESPFRM_RATE_DC_FC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8061;"	d
+MTX_RESPFRM_RATE_DC_FC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8063;"	d
+MTX_RESPFRM_RATE_DC_FC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8065;"	d
+MTX_RESPFRM_RATE_DD_FD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8069;"	d
+MTX_RESPFRM_RATE_DD_FD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8067;"	d
+MTX_RESPFRM_RATE_DD_FD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8066;"	d
+MTX_RESPFRM_RATE_DD_FD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8068;"	d
+MTX_RESPFRM_RATE_DD_FD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8070;"	d
+MTX_RESPFRM_RATE_DE_FE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8074;"	d
+MTX_RESPFRM_RATE_DE_FE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8072;"	d
+MTX_RESPFRM_RATE_DE_FE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8071;"	d
+MTX_RESPFRM_RATE_DE_FE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8073;"	d
+MTX_RESPFRM_RATE_DE_FE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8075;"	d
+MTX_RESPFRM_RATE_DF_FF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8079;"	d
+MTX_RESPFRM_RATE_DF_FF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8077;"	d
+MTX_RESPFRM_RATE_DF_FF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8076;"	d
+MTX_RESPFRM_RATE_DF_FF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8078;"	d
+MTX_RESPFRM_RATE_DF_FF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8080;"	d
+MTX_RESPFRM_RATE_EXCEPTION_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7884;"	d
+MTX_RESPFRM_RATE_EXCEPTION_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7882;"	d
+MTX_RESPFRM_RATE_EXCEPTION_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7881;"	d
+MTX_RESPFRM_RATE_EXCEPTION_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7883;"	d
+MTX_RESPFRM_RATE_EXCEPTION_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7885;"	d
+MTX_RETRY_HI	include/ssv6200_aux.h	9454;"	d
+MTX_RETRY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9289;"	d
+MTX_RETRY_I_MSK	include/ssv6200_aux.h	9452;"	d
+MTX_RETRY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9287;"	d
+MTX_RETRY_MSK	include/ssv6200_aux.h	9451;"	d
+MTX_RETRY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9286;"	d
+MTX_RETRY_SFT	include/ssv6200_aux.h	9453;"	d
+MTX_RETRY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9288;"	d
+MTX_RETRY_SZ	include/ssv6200_aux.h	9455;"	d
+MTX_RETRY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9290;"	d
+MTX_RTS_FAIL_HI	include/ssv6200_aux.h	9469;"	d
+MTX_RTS_FAIL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9304;"	d
+MTX_RTS_FAIL_I_MSK	include/ssv6200_aux.h	9467;"	d
+MTX_RTS_FAIL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9302;"	d
+MTX_RTS_FAIL_MSK	include/ssv6200_aux.h	9466;"	d
+MTX_RTS_FAIL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9301;"	d
+MTX_RTS_FAIL_SFT	include/ssv6200_aux.h	9468;"	d
+MTX_RTS_FAIL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9303;"	d
+MTX_RTS_FAIL_SZ	include/ssv6200_aux.h	9470;"	d
+MTX_RTS_FAIL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9305;"	d
+MTX_RTS_SUCC_HI	include/ssv6200_aux.h	9464;"	d
+MTX_RTS_SUCC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9299;"	d
+MTX_RTS_SUCC_I_MSK	include/ssv6200_aux.h	9462;"	d
+MTX_RTS_SUCC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9297;"	d
+MTX_RTS_SUCC_MSK	include/ssv6200_aux.h	9461;"	d
+MTX_RTS_SUCC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9296;"	d
+MTX_RTS_SUCC_SFT	include/ssv6200_aux.h	9463;"	d
+MTX_RTS_SUCC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9298;"	d
+MTX_RTS_SUCC_SZ	include/ssv6200_aux.h	9465;"	d
+MTX_RTS_SUCC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9300;"	d
+MTX_SELFSTA_PS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6739;"	d
+MTX_SELFSTA_PS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6737;"	d
+MTX_SELFSTA_PS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6736;"	d
+MTX_SELFSTA_PS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6738;"	d
+MTX_SELFSTA_PS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6740;"	d
+MTX_SW_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8559;"	d
+MTX_SW_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8557;"	d
+MTX_SW_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8556;"	d
+MTX_SW_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8558;"	d
+MTX_SW_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8560;"	d
+MTX_TIME_STAMP_AUTO_FILL_HI	include/ssv6200_aux.h	7609;"	d
+MTX_TIME_STAMP_AUTO_FILL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7254;"	d
+MTX_TIME_STAMP_AUTO_FILL_I_MSK	include/ssv6200_aux.h	7607;"	d
+MTX_TIME_STAMP_AUTO_FILL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7252;"	d
+MTX_TIME_STAMP_AUTO_FILL_MSK	include/ssv6200_aux.h	7606;"	d
+MTX_TIME_STAMP_AUTO_FILL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7251;"	d
+MTX_TIME_STAMP_AUTO_FILL_SFT	include/ssv6200_aux.h	7608;"	d
+MTX_TIME_STAMP_AUTO_FILL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7253;"	d
+MTX_TIME_STAMP_AUTO_FILL_SZ	include/ssv6200_aux.h	7610;"	d
+MTX_TIME_STAMP_AUTO_FILL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7255;"	d
+MTX_TSF_AUTO_BCN_HI	include/ssv6200_aux.h	7534;"	d
+MTX_TSF_AUTO_BCN_I_MSK	include/ssv6200_aux.h	7532;"	d
+MTX_TSF_AUTO_BCN_MSK	include/ssv6200_aux.h	7531;"	d
+MTX_TSF_AUTO_BCN_SFT	include/ssv6200_aux.h	7533;"	d
+MTX_TSF_AUTO_BCN_SZ	include/ssv6200_aux.h	7535;"	d
+MTX_TSF_AUTO_MISC_HI	include/ssv6200_aux.h	7539;"	d
+MTX_TSF_AUTO_MISC_I_MSK	include/ssv6200_aux.h	7537;"	d
+MTX_TSF_AUTO_MISC_MSK	include/ssv6200_aux.h	7536;"	d
+MTX_TSF_AUTO_MISC_SFT	include/ssv6200_aux.h	7538;"	d
+MTX_TSF_AUTO_MISC_SZ	include/ssv6200_aux.h	7540;"	d
+MTX_TSF_TIMER_EN_HI	include/ssv6200_aux.h	7614;"	d
+MTX_TSF_TIMER_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7264;"	d
+MTX_TSF_TIMER_EN_I_MSK	include/ssv6200_aux.h	7612;"	d
+MTX_TSF_TIMER_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7262;"	d
+MTX_TSF_TIMER_EN_MSK	include/ssv6200_aux.h	7611;"	d
+MTX_TSF_TIMER_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7261;"	d
+MTX_TSF_TIMER_EN_SFT	include/ssv6200_aux.h	7613;"	d
+MTX_TSF_TIMER_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7263;"	d
+MTX_TSF_TIMER_EN_SHIFT	smac/ap.c	52;"	d	file:
+MTX_TSF_TIMER_EN_SZ	include/ssv6200_aux.h	7615;"	d
+MTX_TSF_TIMER_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7265;"	d
+MTX_TX_EN_HI	include/ssv6200_aux.h	7729;"	d
+MTX_TX_EN_I_MSK	include/ssv6200_aux.h	7727;"	d
+MTX_TX_EN_MSK	include/ssv6200_aux.h	7726;"	d
+MTX_TX_EN_SFT	include/ssv6200_aux.h	7728;"	d
+MTX_TX_EN_SZ	include/ssv6200_aux.h	7730;"	d
+MTX_WSID0_FRM_HI	include/ssv6200_aux.h	9429;"	d
+MTX_WSID0_FRM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9264;"	d
+MTX_WSID0_FRM_I_MSK	include/ssv6200_aux.h	9427;"	d
+MTX_WSID0_FRM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9262;"	d
+MTX_WSID0_FRM_MSK	include/ssv6200_aux.h	9426;"	d
+MTX_WSID0_FRM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9261;"	d
+MTX_WSID0_FRM_SFT	include/ssv6200_aux.h	9428;"	d
+MTX_WSID0_FRM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9263;"	d
+MTX_WSID0_FRM_SZ	include/ssv6200_aux.h	9430;"	d
+MTX_WSID0_FRM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9265;"	d
+MTX_WSID0_RETRY_HI	include/ssv6200_aux.h	9434;"	d
+MTX_WSID0_RETRY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9269;"	d
+MTX_WSID0_RETRY_I_MSK	include/ssv6200_aux.h	9432;"	d
+MTX_WSID0_RETRY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9267;"	d
+MTX_WSID0_RETRY_MSK	include/ssv6200_aux.h	9431;"	d
+MTX_WSID0_RETRY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9266;"	d
+MTX_WSID0_RETRY_SFT	include/ssv6200_aux.h	9433;"	d
+MTX_WSID0_RETRY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9268;"	d
+MTX_WSID0_RETRY_SZ	include/ssv6200_aux.h	9435;"	d
+MTX_WSID0_RETRY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9270;"	d
+MTX_WSID0_SUCC_HI	include/ssv6200_aux.h	9424;"	d
+MTX_WSID0_SUCC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9259;"	d
+MTX_WSID0_SUCC_I_MSK	include/ssv6200_aux.h	9422;"	d
+MTX_WSID0_SUCC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9257;"	d
+MTX_WSID0_SUCC_MSK	include/ssv6200_aux.h	9421;"	d
+MTX_WSID0_SUCC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9256;"	d
+MTX_WSID0_SUCC_SFT	include/ssv6200_aux.h	9423;"	d
+MTX_WSID0_SUCC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9258;"	d
+MTX_WSID0_SUCC_SZ	include/ssv6200_aux.h	9425;"	d
+MTX_WSID0_SUCC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9260;"	d
+MTX_WSID0_TOTAL_HI	include/ssv6200_aux.h	9439;"	d
+MTX_WSID0_TOTAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9274;"	d
+MTX_WSID0_TOTAL_I_MSK	include/ssv6200_aux.h	9437;"	d
+MTX_WSID0_TOTAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9272;"	d
+MTX_WSID0_TOTAL_MSK	include/ssv6200_aux.h	9436;"	d
+MTX_WSID0_TOTAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9271;"	d
+MTX_WSID0_TOTAL_SFT	include/ssv6200_aux.h	9438;"	d
+MTX_WSID0_TOTAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9273;"	d
+MTX_WSID0_TOTAL_SZ	include/ssv6200_aux.h	9440;"	d
+MTX_WSID0_TOTAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9275;"	d
+MT_REG_CSR_BANK_SIZE	include/ssv6200_reg.h	97;"	d
+MT_REG_CSR_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	116;"	d
+MT_REG_CSR_BASE	include/ssv6200_reg.h	48;"	d
+MT_REG_CSR_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	55;"	d
+MT_RESPFRM_REG_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	123;"	d
+MT_RESPFRM_REG_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	62;"	d
+MULTIPLIER	smac/hal/ssv6006c/ssv6006_turismoC.c	914;"	d	file:
+MULTIPLIER	smac/hal/ssv6006c/turismo_common.h	3088;"	d
+MULTI_AMPDU_W_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6494;"	d
+MULTI_AMPDU_W_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6492;"	d
+MULTI_AMPDU_W_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6491;"	d
+MULTI_AMPDU_W_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6493;"	d
+MULTI_AMPDU_W_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6495;"	d
+MUL_ANS0_HI	include/ssv6200_aux.h	6399;"	d
+MUL_ANS0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5644;"	d
+MUL_ANS0_I_MSK	include/ssv6200_aux.h	6397;"	d
+MUL_ANS0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5642;"	d
+MUL_ANS0_MSK	include/ssv6200_aux.h	6396;"	d
+MUL_ANS0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5641;"	d
+MUL_ANS0_SFT	include/ssv6200_aux.h	6398;"	d
+MUL_ANS0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5643;"	d
+MUL_ANS0_SZ	include/ssv6200_aux.h	6400;"	d
+MUL_ANS0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5645;"	d
+MUL_ANS1_HI	include/ssv6200_aux.h	6404;"	d
+MUL_ANS1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5649;"	d
+MUL_ANS1_I_MSK	include/ssv6200_aux.h	6402;"	d
+MUL_ANS1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5647;"	d
+MUL_ANS1_MSK	include/ssv6200_aux.h	6401;"	d
+MUL_ANS1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5646;"	d
+MUL_ANS1_SFT	include/ssv6200_aux.h	6403;"	d
+MUL_ANS1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5648;"	d
+MUL_ANS1_SZ	include/ssv6200_aux.h	6405;"	d
+MUL_ANS1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5650;"	d
+MUL_OP1_HI	include/ssv6200_aux.h	6389;"	d
+MUL_OP1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5634;"	d
+MUL_OP1_I_MSK	include/ssv6200_aux.h	6387;"	d
+MUL_OP1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5632;"	d
+MUL_OP1_MSK	include/ssv6200_aux.h	6386;"	d
+MUL_OP1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5631;"	d
+MUL_OP1_SFT	include/ssv6200_aux.h	6388;"	d
+MUL_OP1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5633;"	d
+MUL_OP1_SZ	include/ssv6200_aux.h	6390;"	d
+MUL_OP1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5635;"	d
+MUL_OP2_HI	include/ssv6200_aux.h	6394;"	d
+MUL_OP2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5639;"	d
+MUL_OP2_I_MSK	include/ssv6200_aux.h	6392;"	d
+MUL_OP2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5637;"	d
+MUL_OP2_MSK	include/ssv6200_aux.h	6391;"	d
+MUL_OP2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5636;"	d
+MUL_OP2_SFT	include/ssv6200_aux.h	6393;"	d
+MUL_OP2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5638;"	d
+MUL_OP2_SZ	include/ssv6200_aux.h	6395;"	d
+MUL_OP2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5640;"	d
+M_CPU_DEFRAG	include/ssv6200_common.h	40;"	d
+M_CPU_DEFRAG	smac/hal/ssv6006c/ssv6006_common.h	40;"	d
+M_CPU_EDCATX	include/ssv6200_common.h	41;"	d
+M_CPU_EDCATX	smac/hal/ssv6006c/ssv6006_common.h	41;"	d
+M_CPU_FRAG	include/ssv6200_common.h	45;"	d
+M_CPU_FRAG	smac/hal/ssv6006c/ssv6006_common.h	45;"	d
+M_CPU_HWENG	include/ssv6200_common.h	37;"	d
+M_CPU_HWENG	smac/hal/ssv6006c/ssv6006_common.h	37;"	d
+M_CPU_RXCTRL	include/ssv6200_common.h	44;"	d
+M_CPU_RXCTRL	smac/hal/ssv6006c/ssv6006_common.h	44;"	d
+M_CPU_RXDATA	include/ssv6200_common.h	42;"	d
+M_CPU_RXDATA	smac/hal/ssv6006c/ssv6006_common.h	42;"	d
+M_CPU_RXL34CS	include/ssv6200_common.h	39;"	d
+M_CPU_RXL34CS	smac/hal/ssv6006c/ssv6006_common.h	39;"	d
+M_CPU_RXMGMT	include/ssv6200_common.h	43;"	d
+M_CPU_RXMGMT	smac/hal/ssv6006c/ssv6006_common.h	43;"	d
+M_CPU_TXL34CS	include/ssv6200_common.h	38;"	d
+M_CPU_TXL34CS	smac/hal/ssv6006c/ssv6006_common.h	38;"	d
+M_CPU_TXTPUT	include/ssv6200_common.h	46;"	d
+M_CPU_TXTPUT	smac/hal/ssv6006c/ssv6006_common.h	46;"	d
+M_ENG_CPU	include/ssv6200_common.h	20;"	d
+M_ENG_CPU	smac/hal/ssv6006c/ssv6006_common.h	20;"	d
+M_ENG_EMPTY	include/ssv6200_common.h	22;"	d
+M_ENG_EMPTY	smac/hal/ssv6006c/ssv6006_common.h	22;"	d
+M_ENG_ENCRYPT	include/ssv6200_common.h	23;"	d
+M_ENG_ENCRYPT	smac/hal/ssv6006c/ssv6006_common.h	23;"	d
+M_ENG_ENCRYPT_SEC	include/ssv6200_common.h	31;"	d
+M_ENG_ENCRYPT_SEC	smac/hal/ssv6006c/ssv6006_common.h	31;"	d
+M_ENG_HWHCI	include/ssv6200_common.h	21;"	d
+M_ENG_HWHCI	smac/hal/ssv6006c/ssv6006_common.h	21;"	d
+M_ENG_MACRX	include/ssv6200_common.h	24;"	d
+M_ENG_MACRX	smac/hal/ssv6006c/ssv6006_common.h	24;"	d
+M_ENG_MAX	include/ssv6200_common.h	36;"	d
+M_ENG_MAX	smac/hal/ssv6006c/ssv6006_common.h	36;"	d
+M_ENG_MIC	include/ssv6200_common.h	25;"	d
+M_ENG_MIC	smac/hal/ssv6006c/ssv6006_common.h	25;"	d
+M_ENG_MIC_SEC	include/ssv6200_common.h	32;"	d
+M_ENG_MIC_SEC	smac/hal/ssv6006c/ssv6006_common.h	32;"	d
+M_ENG_RESERVED_1	include/ssv6200_common.h	33;"	d
+M_ENG_RESERVED_1	smac/hal/ssv6006c/ssv6006_common.h	33;"	d
+M_ENG_RESERVED_2	include/ssv6200_common.h	34;"	d
+M_ENG_RESERVED_2	smac/hal/ssv6006c/ssv6006_common.h	34;"	d
+M_ENG_TRASH_CAN	include/ssv6200_common.h	35;"	d
+M_ENG_TRASH_CAN	smac/hal/ssv6006c/ssv6006_common.h	35;"	d
+M_ENG_TX_EDCA0	include/ssv6200_common.h	26;"	d
+M_ENG_TX_EDCA0	smac/hal/ssv6006c/ssv6006_common.h	26;"	d
+M_ENG_TX_EDCA1	include/ssv6200_common.h	27;"	d
+M_ENG_TX_EDCA1	smac/hal/ssv6006c/ssv6006_common.h	27;"	d
+M_ENG_TX_EDCA2	include/ssv6200_common.h	28;"	d
+M_ENG_TX_EDCA2	smac/hal/ssv6006c/ssv6006_common.h	28;"	d
+M_ENG_TX_EDCA3	include/ssv6200_common.h	29;"	d
+M_ENG_TX_EDCA3	smac/hal/ssv6006c/ssv6006_common.h	29;"	d
+M_ENG_TX_MNG	include/ssv6200_common.h	30;"	d
+M_ENG_TX_MNG	smac/hal/ssv6006c/ssv6006_common.h	30;"	d
+Mk16	smac/sec_tkip.c	/^static inline u16 Mk16(u8 hi, u8 lo)$/;"	f	file:	signature:(u8 hi, u8 lo)
+Mk16_le	smac/sec_tkip.c	/^static inline u16 Mk16_le(__le16 * v)$/;"	f	file:	signature:(__le16 * v)
+MultiplyCircular	smac/wapi_sms4.c	/^static u32 MultiplyCircular(u32 Word, u32 Basis)$/;"	f	file:	signature:(u32 Word, u32 Basis)
+N10CFG_DEFAULT_IVB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1629;"	d
+N10CFG_DEFAULT_IVB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1627;"	d
+N10CFG_DEFAULT_IVB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1626;"	d
+N10CFG_DEFAULT_IVB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1628;"	d
+N10CFG_DEFAULT_IVB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1630;"	d
+N10_CORE_CURRENT_PC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1324;"	d
+N10_CORE_CURRENT_PC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1322;"	d
+N10_CORE_CURRENT_PC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1321;"	d
+N10_CORE_CURRENT_PC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1323;"	d
+N10_CORE_CURRENT_PC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1325;"	d
+N10_CORE_DEBUG_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1339;"	d
+N10_CORE_DEBUG_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1337;"	d
+N10_CORE_DEBUG_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1336;"	d
+N10_CORE_DEBUG_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1338;"	d
+N10_CORE_DEBUG_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1340;"	d
+N10_CORE_STANDBY_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1334;"	d
+N10_CORE_STANDBY_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1332;"	d
+N10_CORE_STANDBY_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1331;"	d
+N10_CORE_STANDBY_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1333;"	d
+N10_CORE_STANDBY_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1335;"	d
+N10_STANDBY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1344;"	d
+N10_STANDBY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1342;"	d
+N10_STANDBY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1341;"	d
+N10_STANDBY_REQ_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1329;"	d
+N10_STANDBY_REQ_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1327;"	d
+N10_STANDBY_REQ_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1326;"	d
+N10_STANDBY_REQ_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1328;"	d
+N10_STANDBY_REQ_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1330;"	d
+N10_STANDBY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1343;"	d
+N10_STANDBY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1345;"	d
+N10_WAKEUP_OK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1349;"	d
+N10_WAKEUP_OK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1347;"	d
+N10_WAKEUP_OK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1346;"	d
+N10_WAKEUP_OK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1348;"	d
+N10_WAKEUP_OK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1350;"	d
+N10_WARM_RESET_N_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1559;"	d
+N10_WARM_RESET_N_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1557;"	d
+N10_WARM_RESET_N_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1556;"	d
+N10_WARM_RESET_N_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1558;"	d
+N10_WARM_RESET_N_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1560;"	d
+NACK_FLAG_BUS_HI	include/ssv6200_aux.h	17859;"	d
+NACK_FLAG_BUS_I_MSK	include/ssv6200_aux.h	17857;"	d
+NACK_FLAG_BUS_MSK	include/ssv6200_aux.h	17856;"	d
+NACK_FLAG_BUS_SFT	include/ssv6200_aux.h	17858;"	d
+NACK_FLAG_BUS_SZ	include/ssv6200_aux.h	17860;"	d
+NAVCS_PHYCS_FALL_OFFSET_STEP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7349;"	d
+NAVCS_PHYCS_FALL_OFFSET_STEP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7347;"	d
+NAVCS_PHYCS_FALL_OFFSET_STEP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7346;"	d
+NAVCS_PHYCS_FALL_OFFSET_STEP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7348;"	d
+NAVCS_PHYCS_FALL_OFFSET_STEP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7350;"	d
+NEQ_MB_FLAG_HI	include/ssv6200_aux.h	18139;"	d
+NEQ_MB_FLAG_I_MSK	include/ssv6200_aux.h	18137;"	d
+NEQ_MB_FLAG_MSK	include/ssv6200_aux.h	18136;"	d
+NEQ_MB_FLAG_SFT	include/ssv6200_aux.h	18138;"	d
+NEQ_MB_FLAG_SZ	include/ssv6200_aux.h	18140;"	d
+NEQ_MB_ID_127_96_HI	include/ssv6200_aux.h	18099;"	d
+NEQ_MB_ID_127_96_I_MSK	include/ssv6200_aux.h	18097;"	d
+NEQ_MB_ID_127_96_MSK	include/ssv6200_aux.h	18096;"	d
+NEQ_MB_ID_127_96_SFT	include/ssv6200_aux.h	18098;"	d
+NEQ_MB_ID_127_96_SZ	include/ssv6200_aux.h	18100;"	d
+NEQ_MB_ID_31_0_HI	include/ssv6200_aux.h	18084;"	d
+NEQ_MB_ID_31_0_I_MSK	include/ssv6200_aux.h	18082;"	d
+NEQ_MB_ID_31_0_MSK	include/ssv6200_aux.h	18081;"	d
+NEQ_MB_ID_31_0_SFT	include/ssv6200_aux.h	18083;"	d
+NEQ_MB_ID_31_0_SZ	include/ssv6200_aux.h	18085;"	d
+NEQ_MB_ID_63_32_HI	include/ssv6200_aux.h	18089;"	d
+NEQ_MB_ID_63_32_I_MSK	include/ssv6200_aux.h	18087;"	d
+NEQ_MB_ID_63_32_MSK	include/ssv6200_aux.h	18086;"	d
+NEQ_MB_ID_63_32_SFT	include/ssv6200_aux.h	18088;"	d
+NEQ_MB_ID_63_32_SZ	include/ssv6200_aux.h	18090;"	d
+NEQ_MB_ID_95_64_HI	include/ssv6200_aux.h	18094;"	d
+NEQ_MB_ID_95_64_I_MSK	include/ssv6200_aux.h	18092;"	d
+NEQ_MB_ID_95_64_MSK	include/ssv6200_aux.h	18091;"	d
+NEQ_MB_ID_95_64_SFT	include/ssv6200_aux.h	18093;"	d
+NEQ_MB_ID_95_64_SZ	include/ssv6200_aux.h	18095;"	d
+NEQ_PKT_FLAG_HI	include/ssv6200_aux.h	18134;"	d
+NEQ_PKT_FLAG_I_MSK	include/ssv6200_aux.h	18132;"	d
+NEQ_PKT_FLAG_MSK	include/ssv6200_aux.h	18131;"	d
+NEQ_PKT_FLAG_SFT	include/ssv6200_aux.h	18133;"	d
+NEQ_PKT_FLAG_SZ	include/ssv6200_aux.h	18135;"	d
+NEQ_PKT_ID_127_96_HI	include/ssv6200_aux.h	18119;"	d
+NEQ_PKT_ID_127_96_I_MSK	include/ssv6200_aux.h	18117;"	d
+NEQ_PKT_ID_127_96_MSK	include/ssv6200_aux.h	18116;"	d
+NEQ_PKT_ID_127_96_SFT	include/ssv6200_aux.h	18118;"	d
+NEQ_PKT_ID_127_96_SZ	include/ssv6200_aux.h	18120;"	d
+NEQ_PKT_ID_31_0_HI	include/ssv6200_aux.h	18104;"	d
+NEQ_PKT_ID_31_0_I_MSK	include/ssv6200_aux.h	18102;"	d
+NEQ_PKT_ID_31_0_MSK	include/ssv6200_aux.h	18101;"	d
+NEQ_PKT_ID_31_0_SFT	include/ssv6200_aux.h	18103;"	d
+NEQ_PKT_ID_31_0_SZ	include/ssv6200_aux.h	18105;"	d
+NEQ_PKT_ID_63_32_HI	include/ssv6200_aux.h	18109;"	d
+NEQ_PKT_ID_63_32_I_MSK	include/ssv6200_aux.h	18107;"	d
+NEQ_PKT_ID_63_32_MSK	include/ssv6200_aux.h	18106;"	d
+NEQ_PKT_ID_63_32_SFT	include/ssv6200_aux.h	18108;"	d
+NEQ_PKT_ID_63_32_SZ	include/ssv6200_aux.h	18110;"	d
+NEQ_PKT_ID_95_64_HI	include/ssv6200_aux.h	18114;"	d
+NEQ_PKT_ID_95_64_I_MSK	include/ssv6200_aux.h	18112;"	d
+NEQ_PKT_ID_95_64_MSK	include/ssv6200_aux.h	18111;"	d
+NEQ_PKT_ID_95_64_SFT	include/ssv6200_aux.h	18113;"	d
+NEQ_PKT_ID_95_64_SZ	include/ssv6200_aux.h	18115;"	d
+NEXT_PKT_SN	smac/ampdu.c	42;"	d	file:
+NLA_DATA	smartlink/ssv_smartlink.c	66;"	d	file:
+NOHIT_RPASS_MD_HI	include/ssv6200_aux.h	17689;"	d
+NOHIT_RPASS_MD_I_MSK	include/ssv6200_aux.h	17687;"	d
+NOHIT_RPASS_MD_MSK	include/ssv6200_aux.h	17686;"	d
+NOHIT_RPASS_MD_SFT	include/ssv6200_aux.h	17688;"	d
+NOHIT_RPASS_MD_SZ	include/ssv6200_aux.h	17690;"	d
+NONE	smac/kssvsmart.c	32;"	d	file:
+NORMAL_ISO_ON1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1734;"	d
+NORMAL_ISO_ON1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1732;"	d
+NORMAL_ISO_ON1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1731;"	d
+NORMAL_ISO_ON1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1733;"	d
+NORMAL_ISO_ON1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1735;"	d
+NORMAL_ISO_ON2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1739;"	d
+NORMAL_ISO_ON2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1737;"	d
+NORMAL_ISO_ON2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1736;"	d
+NORMAL_ISO_ON2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1738;"	d
+NORMAL_ISO_ON2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1740;"	d
+NORMAL_ISO_ON3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1744;"	d
+NORMAL_ISO_ON3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1742;"	d
+NORMAL_ISO_ON3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1741;"	d
+NORMAL_ISO_ON3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1743;"	d
+NORMAL_ISO_ON3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1745;"	d
+NORMAL_PWR	smac/dev.h	573;"	d
+NORMAL_PWR_ON1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1704;"	d
+NORMAL_PWR_ON1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1702;"	d
+NORMAL_PWR_ON1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1701;"	d
+NORMAL_PWR_ON1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1703;"	d
+NORMAL_PWR_ON1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1705;"	d
+NORMAL_PWR_ON2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1709;"	d
+NORMAL_PWR_ON2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1707;"	d
+NORMAL_PWR_ON2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1706;"	d
+NORMAL_PWR_ON2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1708;"	d
+NORMAL_PWR_ON2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1710;"	d
+NORMAL_PWR_ON3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1714;"	d
+NORMAL_PWR_ON3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1712;"	d
+NORMAL_PWR_ON3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1711;"	d
+NORMAL_PWR_ON3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1713;"	d
+NORMAL_PWR_ON3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1715;"	d
+NOTYPE_BUF	include/ssv6xxx_common.h	/^    NOTYPE_BUF = 0,$/;"	e	enum:__PBuf_Type_E
+NO_ALLOCATE_SEND_ERROR_HI	include/ssv6200_aux.h	3499;"	d
+NO_ALLOCATE_SEND_ERROR_I_MSK	include/ssv6200_aux.h	3497;"	d
+NO_ALLOCATE_SEND_ERROR_MSK	include/ssv6200_aux.h	3496;"	d
+NO_ALLOCATE_SEND_ERROR_SFT	include/ssv6200_aux.h	3498;"	d
+NO_ALLOCATE_SEND_ERROR_SZ	include/ssv6200_aux.h	3500;"	d
+NO_ALLOC_ERR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5324;"	d
+NO_ALLOC_ERR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5322;"	d
+NO_ALLOC_ERR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5321;"	d
+NO_ALLOC_ERR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5323;"	d
+NO_ALLOC_ERR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5325;"	d
+NO_PKT_BUF_REDUCTION_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6744;"	d
+NO_PKT_BUF_REDUCTION_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6742;"	d
+NO_PKT_BUF_REDUCTION_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6741;"	d
+NO_PKT_BUF_REDUCTION_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6743;"	d
+NO_PKT_BUF_REDUCTION_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6745;"	d
+NO_REDUCE_PKT_PEERPS_AMPDUV1P2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6759;"	d
+NO_REDUCE_PKT_PEERPS_AMPDUV1P2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6757;"	d
+NO_REDUCE_PKT_PEERPS_AMPDUV1P2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6756;"	d
+NO_REDUCE_PKT_PEERPS_AMPDUV1P2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6758;"	d
+NO_REDUCE_PKT_PEERPS_AMPDUV1P2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6760;"	d
+NO_REDUCE_PKT_PEERPS_AMPDUV1P3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6764;"	d
+NO_REDUCE_PKT_PEERPS_AMPDUV1P3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6762;"	d
+NO_REDUCE_PKT_PEERPS_AMPDUV1P3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6761;"	d
+NO_REDUCE_PKT_PEERPS_AMPDUV1P3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6763;"	d
+NO_REDUCE_PKT_PEERPS_AMPDUV1P3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6765;"	d
+NO_REDUCE_PKT_PEERPS_MPDU_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6754;"	d
+NO_REDUCE_PKT_PEERPS_MPDU_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6752;"	d
+NO_REDUCE_PKT_PEERPS_MPDU_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6751;"	d
+NO_REDUCE_PKT_PEERPS_MPDU_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6753;"	d
+NO_REDUCE_PKT_PEERPS_MPDU_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6755;"	d
+NO_REDUCE_TXALLFAIL_PKT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6749;"	d
+NO_REDUCE_TXALLFAIL_PKT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6747;"	d
+NO_REDUCE_TXALLFAIL_PKT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6746;"	d
+NO_REDUCE_TXALLFAIL_PKT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6748;"	d
+NO_REDUCE_TXALLFAIL_PKT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6750;"	d
+NO_USE	smac/efuse.h	/^   NO_USE,$/;"	e	enum:efuse_data_item
+NO_USE_RXQ_LOCK	smac/dev.c	52;"	d	file:
+NUMBER_OF_MCS	smac/hal/ssv6006c/ssv6006_phy.c	2245;"	d	file:
+OFDM_PLCP_BITS	smac/dev.h	175;"	d
+OFDM_PREAMBLE_TIME	smac/dev.h	174;"	d
+OFDM_RATE_GAIN_16QAM_OFFSET	smac/hal/ssv6006c/ssv6006_turismoC.c	2464;"	d	file:
+OFDM_RATE_GAIN_64QAM_OFFSET	smac/hal/ssv6006c/ssv6006_turismoC.c	2463;"	d	file:
+OFDM_RATE_GAIN_BPSK_OFFSET	smac/hal/ssv6006c/ssv6006_turismoC.c	2466;"	d	file:
+OFDM_RATE_GAIN_QPSK_OFFSET	smac/hal/ssv6006c/ssv6006_turismoC.c	2465;"	d	file:
+OFDM_SIFS_TIME	smac/dev.h	173;"	d
+OFDM_SYMBOL_TIME	smac/dev.h	176;"	d
+ONLINE_RESET_EDCA_THRESHOLD_MASK	include/ssv_cfg.h	40;"	d
+ONLINE_RESET_EDCA_THRESHOLD_SFT	include/ssv_cfg.h	41;"	d
+ONLINE_RESET_ENABLE	include/ssv_cfg.h	39;"	d
+OP_MODE1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9004;"	d
+OP_MODE1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9002;"	d
+OP_MODE1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9001;"	d
+OP_MODE1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9003;"	d
+OP_MODE1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9005;"	d
+OP_MODE_HI	include/ssv6200_aux.h	9124;"	d
+OP_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8879;"	d
+OP_MODE_I_MSK	include/ssv6200_aux.h	9122;"	d
+OP_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8877;"	d
+OP_MODE_MSK	include/ssv6200_aux.h	9121;"	d
+OP_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8876;"	d
+OP_MODE_SFT	include/ssv6200_aux.h	9123;"	d
+OP_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8878;"	d
+OP_MODE_SZ	include/ssv6200_aux.h	9125;"	d
+OP_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8880;"	d
+OUTPUT_HEADER	ver_info.pl	/^OUTPUT_HEADER:$/;"	l
+OUT_1_HI	include/ssv6200_aux.h	4374;"	d
+OUT_1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3479;"	d
+OUT_1_I_MSK	include/ssv6200_aux.h	4372;"	d
+OUT_1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3477;"	d
+OUT_1_MSK	include/ssv6200_aux.h	4371;"	d
+OUT_1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3476;"	d
+OUT_1_SFT	include/ssv6200_aux.h	4373;"	d
+OUT_1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3478;"	d
+OUT_1_SZ	include/ssv6200_aux.h	4375;"	d
+OUT_1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3480;"	d
+OUT_2_HI	include/ssv6200_aux.h	4379;"	d
+OUT_2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3484;"	d
+OUT_2_I_MSK	include/ssv6200_aux.h	4377;"	d
+OUT_2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3482;"	d
+OUT_2_MSK	include/ssv6200_aux.h	4376;"	d
+OUT_2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3481;"	d
+OUT_2_SFT	include/ssv6200_aux.h	4378;"	d
+OUT_2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3483;"	d
+OUT_2_SZ	include/ssv6200_aux.h	4380;"	d
+OUT_2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3485;"	d
+OUT_QUEUE_FLUSH_ID_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33579;"	d
+OUT_QUEUE_FLUSH_ID_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33577;"	d
+OUT_QUEUE_FLUSH_ID_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33576;"	d
+OUT_QUEUE_FLUSH_ID_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33578;"	d
+OUT_QUEUE_FLUSH_ID_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33580;"	d
+OUT_QUEUE_FLUSH_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33584;"	d
+OUT_QUEUE_FLUSH_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33582;"	d
+OUT_QUEUE_FLUSH_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33581;"	d
+OUT_QUEUE_FLUSH_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33583;"	d
+OUT_QUEUE_FLUSH_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33585;"	d
+OUT_QUEUE_FLUSH_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33589;"	d
+OUT_QUEUE_FLUSH_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33587;"	d
+OUT_QUEUE_FLUSH_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33586;"	d
+OUT_QUEUE_FLUSH_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33588;"	d
+OUT_QUEUE_FLUSH_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33590;"	d
+OVERRUN_ERR_HI	include/ssv6200_aux.h	4394;"	d
+OVERRUN_ERR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3504;"	d
+OVERRUN_ERR_I_MSK	include/ssv6200_aux.h	4392;"	d
+OVERRUN_ERR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3502;"	d
+OVERRUN_ERR_MSK	include/ssv6200_aux.h	4391;"	d
+OVERRUN_ERR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3501;"	d
+OVERRUN_ERR_SFT	include/ssv6200_aux.h	4393;"	d
+OVERRUN_ERR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3503;"	d
+OVERRUN_ERR_SZ	include/ssv6200_aux.h	4395;"	d
+OVERRUN_ERR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3505;"	d
+OVERRUN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3649;"	d
+OVERRUN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3647;"	d
+OVERRUN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3646;"	d
+OVERRUN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3648;"	d
+OVERRUN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3650;"	d
+P2P_ATTR_CAPABILITY	smac/p2p.c	/^ P2P_ATTR_CAPABILITY = 2,$/;"	e	enum:p2p_attr_id	file:
+P2P_ATTR_CHANNEL_LIST	smac/p2p.c	/^ P2P_ATTR_CHANNEL_LIST = 11,$/;"	e	enum:p2p_attr_id	file:
+P2P_ATTR_CONFIGURATION_TIMEOUT	smac/p2p.c	/^ P2P_ATTR_CONFIGURATION_TIMEOUT = 5,$/;"	e	enum:p2p_attr_id	file:
+P2P_ATTR_DEVICE_ID	smac/p2p.c	/^ P2P_ATTR_DEVICE_ID = 3,$/;"	e	enum:p2p_attr_id	file:
+P2P_ATTR_DEVICE_INFO	smac/p2p.c	/^ P2P_ATTR_DEVICE_INFO = 13,$/;"	e	enum:p2p_attr_id	file:
+P2P_ATTR_EXT_LISTEN_TIMING	smac/p2p.c	/^ P2P_ATTR_EXT_LISTEN_TIMING = 8,$/;"	e	enum:p2p_attr_id	file:
+P2P_ATTR_GROUP_BSSID	smac/p2p.c	/^ P2P_ATTR_GROUP_BSSID = 7,$/;"	e	enum:p2p_attr_id	file:
+P2P_ATTR_GROUP_ID	smac/p2p.c	/^ P2P_ATTR_GROUP_ID = 15,$/;"	e	enum:p2p_attr_id	file:
+P2P_ATTR_GROUP_INFO	smac/p2p.c	/^ P2P_ATTR_GROUP_INFO = 14,$/;"	e	enum:p2p_attr_id	file:
+P2P_ATTR_GROUP_OWNER_INTENT	smac/p2p.c	/^ P2P_ATTR_GROUP_OWNER_INTENT = 4,$/;"	e	enum:p2p_attr_id	file:
+P2P_ATTR_INTENDED_INTERFACE_ADDR	smac/p2p.c	/^ P2P_ATTR_INTENDED_INTERFACE_ADDR = 9,$/;"	e	enum:p2p_attr_id	file:
+P2P_ATTR_INTERFACE	smac/p2p.c	/^ P2P_ATTR_INTERFACE = 16,$/;"	e	enum:p2p_attr_id	file:
+P2P_ATTR_INVITATION_FLAGS	smac/p2p.c	/^ P2P_ATTR_INVITATION_FLAGS = 18,$/;"	e	enum:p2p_attr_id	file:
+P2P_ATTR_LISTEN_CHANNEL	smac/p2p.c	/^ P2P_ATTR_LISTEN_CHANNEL = 6,$/;"	e	enum:p2p_attr_id	file:
+P2P_ATTR_MANAGEABILITY	smac/p2p.c	/^ P2P_ATTR_MANAGEABILITY = 10,$/;"	e	enum:p2p_attr_id	file:
+P2P_ATTR_MINOR_REASON_CODE	smac/p2p.c	/^ P2P_ATTR_MINOR_REASON_CODE = 1,$/;"	e	enum:p2p_attr_id	file:
+P2P_ATTR_NOTICE_OF_ABSENCE	smac/p2p.c	/^ P2P_ATTR_NOTICE_OF_ABSENCE = 12,$/;"	e	enum:p2p_attr_id	file:
+P2P_ATTR_OOB_GO_NEG_CHANNEL	smac/p2p.c	/^ P2P_ATTR_OOB_GO_NEG_CHANNEL = 19,$/;"	e	enum:p2p_attr_id	file:
+P2P_ATTR_OPERATING_CHANNEL	smac/p2p.c	/^ P2P_ATTR_OPERATING_CHANNEL = 17,$/;"	e	enum:p2p_attr_id	file:
+P2P_ATTR_STATUS	smac/p2p.c	/^ P2P_ATTR_STATUS = 0,$/;"	e	enum:p2p_attr_id	file:
+P2P_ATTR_VENDOR_SPECIFIC	smac/p2p.c	/^ P2P_ATTR_VENDOR_SPECIFIC = 221$/;"	e	enum:p2p_attr_id	file:
+P2P_IE_VENDOR_TYPE	smac/p2p.c	36;"	d	file:
+P2P_MAX_NOA_INTERFACE	smac/p2p.h	26;"	d
+P2P_NOA_DETECT_INTERVAL	smac/p2p.c	37;"	d	file:
+PACKET_ADDR_2_ID	include/ssv6200.h	83;"	d
+PACKET_ADDR_2_ID	include/ssv6xxx_cfg.h	81;"	d
+PACKET_ADDR_2_ID	smac/hal/ssv6006c/ssv6006_cfg.h	64;"	d
+PACKET_ERR_HI	include/ssv6200_aux.h	14609;"	d
+PACKET_ERR_I_MSK	include/ssv6200_aux.h	14607;"	d
+PACKET_ERR_MSK	include/ssv6200_aux.h	14606;"	d
+PACKET_ERR_SFT	include/ssv6200_aux.h	14608;"	d
+PACKET_ERR_SZ	include/ssv6200_aux.h	14610;"	d
+PAD11_IE_HI	include/ssv6200_aux.h	1004;"	d
+PAD11_IE_I_MSK	include/ssv6200_aux.h	1002;"	d
+PAD11_IE_MSK	include/ssv6200_aux.h	1001;"	d
+PAD11_IE_SFT	include/ssv6200_aux.h	1003;"	d
+PAD11_IE_SZ	include/ssv6200_aux.h	1005;"	d
+PAD11_OD_HI	include/ssv6200_aux.h	1014;"	d
+PAD11_OD_I_MSK	include/ssv6200_aux.h	1012;"	d
+PAD11_OD_MSK	include/ssv6200_aux.h	1011;"	d
+PAD11_OD_SFT	include/ssv6200_aux.h	1013;"	d
+PAD11_OD_SZ	include/ssv6200_aux.h	1015;"	d
+PAD11_SEL_I_HI	include/ssv6200_aux.h	1009;"	d
+PAD11_SEL_I_I_MSK	include/ssv6200_aux.h	1007;"	d
+PAD11_SEL_I_MSK	include/ssv6200_aux.h	1006;"	d
+PAD11_SEL_I_SFT	include/ssv6200_aux.h	1008;"	d
+PAD11_SEL_I_SZ	include/ssv6200_aux.h	1010;"	d
+PAD11_SEL_O_HI	include/ssv6200_aux.h	1019;"	d
+PAD11_SEL_O_I_MSK	include/ssv6200_aux.h	1017;"	d
+PAD11_SEL_O_MSK	include/ssv6200_aux.h	1016;"	d
+PAD11_SEL_O_SFT	include/ssv6200_aux.h	1018;"	d
+PAD11_SEL_O_SZ	include/ssv6200_aux.h	1020;"	d
+PAD15_DS_HI	include/ssv6200_aux.h	1039;"	d
+PAD15_DS_I_MSK	include/ssv6200_aux.h	1037;"	d
+PAD15_DS_MSK	include/ssv6200_aux.h	1036;"	d
+PAD15_DS_SFT	include/ssv6200_aux.h	1038;"	d
+PAD15_DS_SZ	include/ssv6200_aux.h	1040;"	d
+PAD15_IE_HI	include/ssv6200_aux.h	1044;"	d
+PAD15_IE_I_MSK	include/ssv6200_aux.h	1042;"	d
+PAD15_IE_MSK	include/ssv6200_aux.h	1041;"	d
+PAD15_IE_SFT	include/ssv6200_aux.h	1043;"	d
+PAD15_IE_SZ	include/ssv6200_aux.h	1045;"	d
+PAD15_OD_HI	include/ssv6200_aux.h	1054;"	d
+PAD15_OD_I_MSK	include/ssv6200_aux.h	1052;"	d
+PAD15_OD_MSK	include/ssv6200_aux.h	1051;"	d
+PAD15_OD_SFT	include/ssv6200_aux.h	1053;"	d
+PAD15_OD_SZ	include/ssv6200_aux.h	1055;"	d
+PAD15_OE_HI	include/ssv6200_aux.h	1029;"	d
+PAD15_OE_I_MSK	include/ssv6200_aux.h	1027;"	d
+PAD15_OE_MSK	include/ssv6200_aux.h	1026;"	d
+PAD15_OE_SFT	include/ssv6200_aux.h	1028;"	d
+PAD15_OE_SZ	include/ssv6200_aux.h	1030;"	d
+PAD15_PE_HI	include/ssv6200_aux.h	1034;"	d
+PAD15_PE_I_MSK	include/ssv6200_aux.h	1032;"	d
+PAD15_PE_MSK	include/ssv6200_aux.h	1031;"	d
+PAD15_PE_SFT	include/ssv6200_aux.h	1033;"	d
+PAD15_PE_SZ	include/ssv6200_aux.h	1035;"	d
+PAD15_SEL_I_HI	include/ssv6200_aux.h	1049;"	d
+PAD15_SEL_I_I_MSK	include/ssv6200_aux.h	1047;"	d
+PAD15_SEL_I_MSK	include/ssv6200_aux.h	1046;"	d
+PAD15_SEL_I_SFT	include/ssv6200_aux.h	1048;"	d
+PAD15_SEL_I_SZ	include/ssv6200_aux.h	1050;"	d
+PAD15_SEL_O_HI	include/ssv6200_aux.h	1059;"	d
+PAD15_SEL_O_I_MSK	include/ssv6200_aux.h	1057;"	d
+PAD15_SEL_O_MSK	include/ssv6200_aux.h	1056;"	d
+PAD15_SEL_O_SFT	include/ssv6200_aux.h	1058;"	d
+PAD15_SEL_O_SZ	include/ssv6200_aux.h	1060;"	d
+PAD16_DS_HI	include/ssv6200_aux.h	1079;"	d
+PAD16_DS_I_MSK	include/ssv6200_aux.h	1077;"	d
+PAD16_DS_MSK	include/ssv6200_aux.h	1076;"	d
+PAD16_DS_SFT	include/ssv6200_aux.h	1078;"	d
+PAD16_DS_SZ	include/ssv6200_aux.h	1080;"	d
+PAD16_IE_HI	include/ssv6200_aux.h	1084;"	d
+PAD16_IE_I_MSK	include/ssv6200_aux.h	1082;"	d
+PAD16_IE_MSK	include/ssv6200_aux.h	1081;"	d
+PAD16_IE_SFT	include/ssv6200_aux.h	1083;"	d
+PAD16_IE_SZ	include/ssv6200_aux.h	1085;"	d
+PAD16_OD_HI	include/ssv6200_aux.h	1094;"	d
+PAD16_OD_I_MSK	include/ssv6200_aux.h	1092;"	d
+PAD16_OD_MSK	include/ssv6200_aux.h	1091;"	d
+PAD16_OD_SFT	include/ssv6200_aux.h	1093;"	d
+PAD16_OD_SZ	include/ssv6200_aux.h	1095;"	d
+PAD16_OE_HI	include/ssv6200_aux.h	1069;"	d
+PAD16_OE_I_MSK	include/ssv6200_aux.h	1067;"	d
+PAD16_OE_MSK	include/ssv6200_aux.h	1066;"	d
+PAD16_OE_SFT	include/ssv6200_aux.h	1068;"	d
+PAD16_OE_SZ	include/ssv6200_aux.h	1070;"	d
+PAD16_PE_HI	include/ssv6200_aux.h	1074;"	d
+PAD16_PE_I_MSK	include/ssv6200_aux.h	1072;"	d
+PAD16_PE_MSK	include/ssv6200_aux.h	1071;"	d
+PAD16_PE_SFT	include/ssv6200_aux.h	1073;"	d
+PAD16_PE_SZ	include/ssv6200_aux.h	1075;"	d
+PAD16_SEL_I_HI	include/ssv6200_aux.h	1089;"	d
+PAD16_SEL_I_I_MSK	include/ssv6200_aux.h	1087;"	d
+PAD16_SEL_I_MSK	include/ssv6200_aux.h	1086;"	d
+PAD16_SEL_I_SFT	include/ssv6200_aux.h	1088;"	d
+PAD16_SEL_I_SZ	include/ssv6200_aux.h	1090;"	d
+PAD16_SEL_O_HI	include/ssv6200_aux.h	1099;"	d
+PAD16_SEL_O_I_MSK	include/ssv6200_aux.h	1097;"	d
+PAD16_SEL_O_MSK	include/ssv6200_aux.h	1096;"	d
+PAD16_SEL_O_SFT	include/ssv6200_aux.h	1098;"	d
+PAD16_SEL_O_SZ	include/ssv6200_aux.h	1100;"	d
+PAD17_DS_HI	include/ssv6200_aux.h	1119;"	d
+PAD17_DS_I_MSK	include/ssv6200_aux.h	1117;"	d
+PAD17_DS_MSK	include/ssv6200_aux.h	1116;"	d
+PAD17_DS_SFT	include/ssv6200_aux.h	1118;"	d
+PAD17_DS_SZ	include/ssv6200_aux.h	1120;"	d
+PAD17_IE_HI	include/ssv6200_aux.h	1124;"	d
+PAD17_IE_I_MSK	include/ssv6200_aux.h	1122;"	d
+PAD17_IE_MSK	include/ssv6200_aux.h	1121;"	d
+PAD17_IE_SFT	include/ssv6200_aux.h	1123;"	d
+PAD17_IE_SZ	include/ssv6200_aux.h	1125;"	d
+PAD17_OD_HI	include/ssv6200_aux.h	1134;"	d
+PAD17_OD_I_MSK	include/ssv6200_aux.h	1132;"	d
+PAD17_OD_MSK	include/ssv6200_aux.h	1131;"	d
+PAD17_OD_SFT	include/ssv6200_aux.h	1133;"	d
+PAD17_OD_SZ	include/ssv6200_aux.h	1135;"	d
+PAD17_OE_HI	include/ssv6200_aux.h	1109;"	d
+PAD17_OE_I_MSK	include/ssv6200_aux.h	1107;"	d
+PAD17_OE_MSK	include/ssv6200_aux.h	1106;"	d
+PAD17_OE_SFT	include/ssv6200_aux.h	1108;"	d
+PAD17_OE_SZ	include/ssv6200_aux.h	1110;"	d
+PAD17_PE_HI	include/ssv6200_aux.h	1114;"	d
+PAD17_PE_I_MSK	include/ssv6200_aux.h	1112;"	d
+PAD17_PE_MSK	include/ssv6200_aux.h	1111;"	d
+PAD17_PE_SFT	include/ssv6200_aux.h	1113;"	d
+PAD17_PE_SZ	include/ssv6200_aux.h	1115;"	d
+PAD17_SEL_I_HI	include/ssv6200_aux.h	1129;"	d
+PAD17_SEL_I_I_MSK	include/ssv6200_aux.h	1127;"	d
+PAD17_SEL_I_MSK	include/ssv6200_aux.h	1126;"	d
+PAD17_SEL_I_SFT	include/ssv6200_aux.h	1128;"	d
+PAD17_SEL_I_SZ	include/ssv6200_aux.h	1130;"	d
+PAD17_SEL_O_HI	include/ssv6200_aux.h	1139;"	d
+PAD17_SEL_O_I_MSK	include/ssv6200_aux.h	1137;"	d
+PAD17_SEL_O_MSK	include/ssv6200_aux.h	1136;"	d
+PAD17_SEL_O_SFT	include/ssv6200_aux.h	1138;"	d
+PAD17_SEL_O_SZ	include/ssv6200_aux.h	1140;"	d
+PAD18_DS_HI	include/ssv6200_aux.h	1159;"	d
+PAD18_DS_I_MSK	include/ssv6200_aux.h	1157;"	d
+PAD18_DS_MSK	include/ssv6200_aux.h	1156;"	d
+PAD18_DS_SFT	include/ssv6200_aux.h	1158;"	d
+PAD18_DS_SZ	include/ssv6200_aux.h	1160;"	d
+PAD18_IE_HI	include/ssv6200_aux.h	1164;"	d
+PAD18_IE_I_MSK	include/ssv6200_aux.h	1162;"	d
+PAD18_IE_MSK	include/ssv6200_aux.h	1161;"	d
+PAD18_IE_SFT	include/ssv6200_aux.h	1163;"	d
+PAD18_IE_SZ	include/ssv6200_aux.h	1165;"	d
+PAD18_OD_HI	include/ssv6200_aux.h	1174;"	d
+PAD18_OD_I_MSK	include/ssv6200_aux.h	1172;"	d
+PAD18_OD_MSK	include/ssv6200_aux.h	1171;"	d
+PAD18_OD_SFT	include/ssv6200_aux.h	1173;"	d
+PAD18_OD_SZ	include/ssv6200_aux.h	1175;"	d
+PAD18_OE_HI	include/ssv6200_aux.h	1149;"	d
+PAD18_OE_I_MSK	include/ssv6200_aux.h	1147;"	d
+PAD18_OE_MSK	include/ssv6200_aux.h	1146;"	d
+PAD18_OE_SFT	include/ssv6200_aux.h	1148;"	d
+PAD18_OE_SZ	include/ssv6200_aux.h	1150;"	d
+PAD18_PE_HI	include/ssv6200_aux.h	1154;"	d
+PAD18_PE_I_MSK	include/ssv6200_aux.h	1152;"	d
+PAD18_PE_MSK	include/ssv6200_aux.h	1151;"	d
+PAD18_PE_SFT	include/ssv6200_aux.h	1153;"	d
+PAD18_PE_SZ	include/ssv6200_aux.h	1155;"	d
+PAD18_SEL_I_HI	include/ssv6200_aux.h	1169;"	d
+PAD18_SEL_I_I_MSK	include/ssv6200_aux.h	1167;"	d
+PAD18_SEL_I_MSK	include/ssv6200_aux.h	1166;"	d
+PAD18_SEL_I_SFT	include/ssv6200_aux.h	1168;"	d
+PAD18_SEL_I_SZ	include/ssv6200_aux.h	1170;"	d
+PAD18_SEL_O_HI	include/ssv6200_aux.h	1179;"	d
+PAD18_SEL_O_I_MSK	include/ssv6200_aux.h	1177;"	d
+PAD18_SEL_O_MSK	include/ssv6200_aux.h	1176;"	d
+PAD18_SEL_O_SFT	include/ssv6200_aux.h	1178;"	d
+PAD18_SEL_O_SZ	include/ssv6200_aux.h	1180;"	d
+PAD19_DS_HI	include/ssv6200_aux.h	1199;"	d
+PAD19_DS_I_MSK	include/ssv6200_aux.h	1197;"	d
+PAD19_DS_MSK	include/ssv6200_aux.h	1196;"	d
+PAD19_DS_SFT	include/ssv6200_aux.h	1198;"	d
+PAD19_DS_SZ	include/ssv6200_aux.h	1200;"	d
+PAD19_IE_HI	include/ssv6200_aux.h	1204;"	d
+PAD19_IE_I_MSK	include/ssv6200_aux.h	1202;"	d
+PAD19_IE_MSK	include/ssv6200_aux.h	1201;"	d
+PAD19_IE_SFT	include/ssv6200_aux.h	1203;"	d
+PAD19_IE_SZ	include/ssv6200_aux.h	1205;"	d
+PAD19_OD_HI	include/ssv6200_aux.h	1214;"	d
+PAD19_OD_I_MSK	include/ssv6200_aux.h	1212;"	d
+PAD19_OD_MSK	include/ssv6200_aux.h	1211;"	d
+PAD19_OD_SFT	include/ssv6200_aux.h	1213;"	d
+PAD19_OD_SZ	include/ssv6200_aux.h	1215;"	d
+PAD19_OE_HI	include/ssv6200_aux.h	1189;"	d
+PAD19_OE_I_MSK	include/ssv6200_aux.h	1187;"	d
+PAD19_OE_MSK	include/ssv6200_aux.h	1186;"	d
+PAD19_OE_SFT	include/ssv6200_aux.h	1188;"	d
+PAD19_OE_SZ	include/ssv6200_aux.h	1190;"	d
+PAD19_PE_HI	include/ssv6200_aux.h	1194;"	d
+PAD19_PE_I_MSK	include/ssv6200_aux.h	1192;"	d
+PAD19_PE_MSK	include/ssv6200_aux.h	1191;"	d
+PAD19_PE_SFT	include/ssv6200_aux.h	1193;"	d
+PAD19_PE_SZ	include/ssv6200_aux.h	1195;"	d
+PAD19_SEL_I_HI	include/ssv6200_aux.h	1209;"	d
+PAD19_SEL_I_I_MSK	include/ssv6200_aux.h	1207;"	d
+PAD19_SEL_I_MSK	include/ssv6200_aux.h	1206;"	d
+PAD19_SEL_I_SFT	include/ssv6200_aux.h	1208;"	d
+PAD19_SEL_I_SZ	include/ssv6200_aux.h	1210;"	d
+PAD19_SEL_O_HI	include/ssv6200_aux.h	1219;"	d
+PAD19_SEL_O_I_MSK	include/ssv6200_aux.h	1217;"	d
+PAD19_SEL_O_MSK	include/ssv6200_aux.h	1216;"	d
+PAD19_SEL_O_SFT	include/ssv6200_aux.h	1218;"	d
+PAD19_SEL_O_SZ	include/ssv6200_aux.h	1220;"	d
+PAD20_DS_HI	include/ssv6200_aux.h	1239;"	d
+PAD20_DS_I_MSK	include/ssv6200_aux.h	1237;"	d
+PAD20_DS_MSK	include/ssv6200_aux.h	1236;"	d
+PAD20_DS_SFT	include/ssv6200_aux.h	1238;"	d
+PAD20_DS_SZ	include/ssv6200_aux.h	1240;"	d
+PAD20_IE_HI	include/ssv6200_aux.h	1244;"	d
+PAD20_IE_I_MSK	include/ssv6200_aux.h	1242;"	d
+PAD20_IE_MSK	include/ssv6200_aux.h	1241;"	d
+PAD20_IE_SFT	include/ssv6200_aux.h	1243;"	d
+PAD20_IE_SZ	include/ssv6200_aux.h	1245;"	d
+PAD20_OD_HI	include/ssv6200_aux.h	1254;"	d
+PAD20_OD_I_MSK	include/ssv6200_aux.h	1252;"	d
+PAD20_OD_MSK	include/ssv6200_aux.h	1251;"	d
+PAD20_OD_SFT	include/ssv6200_aux.h	1253;"	d
+PAD20_OD_SZ	include/ssv6200_aux.h	1255;"	d
+PAD20_OE_HI	include/ssv6200_aux.h	1229;"	d
+PAD20_OE_I_MSK	include/ssv6200_aux.h	1227;"	d
+PAD20_OE_MSK	include/ssv6200_aux.h	1226;"	d
+PAD20_OE_SFT	include/ssv6200_aux.h	1228;"	d
+PAD20_OE_SZ	include/ssv6200_aux.h	1230;"	d
+PAD20_PE_HI	include/ssv6200_aux.h	1234;"	d
+PAD20_PE_I_MSK	include/ssv6200_aux.h	1232;"	d
+PAD20_PE_MSK	include/ssv6200_aux.h	1231;"	d
+PAD20_PE_SFT	include/ssv6200_aux.h	1233;"	d
+PAD20_PE_SZ	include/ssv6200_aux.h	1235;"	d
+PAD20_SEL_I_HI	include/ssv6200_aux.h	1249;"	d
+PAD20_SEL_I_I_MSK	include/ssv6200_aux.h	1247;"	d
+PAD20_SEL_I_MSK	include/ssv6200_aux.h	1246;"	d
+PAD20_SEL_I_SFT	include/ssv6200_aux.h	1248;"	d
+PAD20_SEL_I_SZ	include/ssv6200_aux.h	1250;"	d
+PAD20_SEL_O_HI	include/ssv6200_aux.h	1259;"	d
+PAD20_SEL_O_I_MSK	include/ssv6200_aux.h	1257;"	d
+PAD20_SEL_O_MSK	include/ssv6200_aux.h	1256;"	d
+PAD20_SEL_O_SFT	include/ssv6200_aux.h	1258;"	d
+PAD20_SEL_O_SZ	include/ssv6200_aux.h	1260;"	d
+PAD21_DS_HI	include/ssv6200_aux.h	1284;"	d
+PAD21_DS_I_MSK	include/ssv6200_aux.h	1282;"	d
+PAD21_DS_MSK	include/ssv6200_aux.h	1281;"	d
+PAD21_DS_SFT	include/ssv6200_aux.h	1283;"	d
+PAD21_DS_SZ	include/ssv6200_aux.h	1285;"	d
+PAD21_IE_HI	include/ssv6200_aux.h	1289;"	d
+PAD21_IE_I_MSK	include/ssv6200_aux.h	1287;"	d
+PAD21_IE_MSK	include/ssv6200_aux.h	1286;"	d
+PAD21_IE_SFT	include/ssv6200_aux.h	1288;"	d
+PAD21_IE_SZ	include/ssv6200_aux.h	1290;"	d
+PAD21_OD_HI	include/ssv6200_aux.h	1299;"	d
+PAD21_OD_I_MSK	include/ssv6200_aux.h	1297;"	d
+PAD21_OD_MSK	include/ssv6200_aux.h	1296;"	d
+PAD21_OD_SFT	include/ssv6200_aux.h	1298;"	d
+PAD21_OD_SZ	include/ssv6200_aux.h	1300;"	d
+PAD21_OE_HI	include/ssv6200_aux.h	1274;"	d
+PAD21_OE_I_MSK	include/ssv6200_aux.h	1272;"	d
+PAD21_OE_MSK	include/ssv6200_aux.h	1271;"	d
+PAD21_OE_SFT	include/ssv6200_aux.h	1273;"	d
+PAD21_OE_SZ	include/ssv6200_aux.h	1275;"	d
+PAD21_PE_HI	include/ssv6200_aux.h	1279;"	d
+PAD21_PE_I_MSK	include/ssv6200_aux.h	1277;"	d
+PAD21_PE_MSK	include/ssv6200_aux.h	1276;"	d
+PAD21_PE_SFT	include/ssv6200_aux.h	1278;"	d
+PAD21_PE_SZ	include/ssv6200_aux.h	1280;"	d
+PAD21_SEL_I_HI	include/ssv6200_aux.h	1294;"	d
+PAD21_SEL_I_I_MSK	include/ssv6200_aux.h	1292;"	d
+PAD21_SEL_I_MSK	include/ssv6200_aux.h	1291;"	d
+PAD21_SEL_I_SFT	include/ssv6200_aux.h	1293;"	d
+PAD21_SEL_I_SZ	include/ssv6200_aux.h	1295;"	d
+PAD21_SEL_O_HI	include/ssv6200_aux.h	1304;"	d
+PAD21_SEL_O_I_MSK	include/ssv6200_aux.h	1302;"	d
+PAD21_SEL_O_MSK	include/ssv6200_aux.h	1301;"	d
+PAD21_SEL_O_SFT	include/ssv6200_aux.h	1303;"	d
+PAD21_SEL_O_SZ	include/ssv6200_aux.h	1305;"	d
+PAD22_DS_HI	include/ssv6200_aux.h	1329;"	d
+PAD22_DS_I_MSK	include/ssv6200_aux.h	1327;"	d
+PAD22_DS_MSK	include/ssv6200_aux.h	1326;"	d
+PAD22_DS_SFT	include/ssv6200_aux.h	1328;"	d
+PAD22_DS_SZ	include/ssv6200_aux.h	1330;"	d
+PAD22_IE_HI	include/ssv6200_aux.h	1334;"	d
+PAD22_IE_I_MSK	include/ssv6200_aux.h	1332;"	d
+PAD22_IE_MSK	include/ssv6200_aux.h	1331;"	d
+PAD22_IE_SFT	include/ssv6200_aux.h	1333;"	d
+PAD22_IE_SZ	include/ssv6200_aux.h	1335;"	d
+PAD22_OD_HI	include/ssv6200_aux.h	1344;"	d
+PAD22_OD_I_MSK	include/ssv6200_aux.h	1342;"	d
+PAD22_OD_MSK	include/ssv6200_aux.h	1341;"	d
+PAD22_OD_SFT	include/ssv6200_aux.h	1343;"	d
+PAD22_OD_SZ	include/ssv6200_aux.h	1345;"	d
+PAD22_OE_HI	include/ssv6200_aux.h	1319;"	d
+PAD22_OE_I_MSK	include/ssv6200_aux.h	1317;"	d
+PAD22_OE_MSK	include/ssv6200_aux.h	1316;"	d
+PAD22_OE_SFT	include/ssv6200_aux.h	1318;"	d
+PAD22_OE_SZ	include/ssv6200_aux.h	1320;"	d
+PAD22_PE_HI	include/ssv6200_aux.h	1324;"	d
+PAD22_PE_I_MSK	include/ssv6200_aux.h	1322;"	d
+PAD22_PE_MSK	include/ssv6200_aux.h	1321;"	d
+PAD22_PE_SFT	include/ssv6200_aux.h	1323;"	d
+PAD22_PE_SZ	include/ssv6200_aux.h	1325;"	d
+PAD22_SEL_I_HI	include/ssv6200_aux.h	1339;"	d
+PAD22_SEL_I_I_MSK	include/ssv6200_aux.h	1337;"	d
+PAD22_SEL_I_MSK	include/ssv6200_aux.h	1336;"	d
+PAD22_SEL_I_SFT	include/ssv6200_aux.h	1338;"	d
+PAD22_SEL_I_SZ	include/ssv6200_aux.h	1340;"	d
+PAD22_SEL_OE_HI	include/ssv6200_aux.h	1354;"	d
+PAD22_SEL_OE_I_MSK	include/ssv6200_aux.h	1352;"	d
+PAD22_SEL_OE_MSK	include/ssv6200_aux.h	1351;"	d
+PAD22_SEL_OE_SFT	include/ssv6200_aux.h	1353;"	d
+PAD22_SEL_OE_SZ	include/ssv6200_aux.h	1355;"	d
+PAD22_SEL_O_HI	include/ssv6200_aux.h	1349;"	d
+PAD22_SEL_O_I_MSK	include/ssv6200_aux.h	1347;"	d
+PAD22_SEL_O_MSK	include/ssv6200_aux.h	1346;"	d
+PAD22_SEL_O_SFT	include/ssv6200_aux.h	1348;"	d
+PAD22_SEL_O_SZ	include/ssv6200_aux.h	1350;"	d
+PAD231_DS_HI	include/ssv6200_aux.h	2879;"	d
+PAD231_DS_I_MSK	include/ssv6200_aux.h	2877;"	d
+PAD231_DS_MSK	include/ssv6200_aux.h	2876;"	d
+PAD231_DS_SFT	include/ssv6200_aux.h	2878;"	d
+PAD231_DS_SZ	include/ssv6200_aux.h	2880;"	d
+PAD231_IE_HI	include/ssv6200_aux.h	2884;"	d
+PAD231_IE_I_MSK	include/ssv6200_aux.h	2882;"	d
+PAD231_IE_MSK	include/ssv6200_aux.h	2881;"	d
+PAD231_IE_SFT	include/ssv6200_aux.h	2883;"	d
+PAD231_IE_SZ	include/ssv6200_aux.h	2885;"	d
+PAD231_OD_HI	include/ssv6200_aux.h	2889;"	d
+PAD231_OD_I_MSK	include/ssv6200_aux.h	2887;"	d
+PAD231_OD_MSK	include/ssv6200_aux.h	2886;"	d
+PAD231_OD_SFT	include/ssv6200_aux.h	2888;"	d
+PAD231_OD_SZ	include/ssv6200_aux.h	2890;"	d
+PAD231_OE_HI	include/ssv6200_aux.h	2869;"	d
+PAD231_OE_I_MSK	include/ssv6200_aux.h	2867;"	d
+PAD231_OE_MSK	include/ssv6200_aux.h	2866;"	d
+PAD231_OE_SFT	include/ssv6200_aux.h	2868;"	d
+PAD231_OE_SZ	include/ssv6200_aux.h	2870;"	d
+PAD231_PE_HI	include/ssv6200_aux.h	2874;"	d
+PAD231_PE_I_MSK	include/ssv6200_aux.h	2872;"	d
+PAD231_PE_MSK	include/ssv6200_aux.h	2871;"	d
+PAD231_PE_SFT	include/ssv6200_aux.h	2873;"	d
+PAD231_PE_SZ	include/ssv6200_aux.h	2875;"	d
+PAD24_DS_HI	include/ssv6200_aux.h	1374;"	d
+PAD24_DS_I_MSK	include/ssv6200_aux.h	1372;"	d
+PAD24_DS_MSK	include/ssv6200_aux.h	1371;"	d
+PAD24_DS_SFT	include/ssv6200_aux.h	1373;"	d
+PAD24_DS_SZ	include/ssv6200_aux.h	1375;"	d
+PAD24_IE_HI	include/ssv6200_aux.h	1379;"	d
+PAD24_IE_I_MSK	include/ssv6200_aux.h	1377;"	d
+PAD24_IE_MSK	include/ssv6200_aux.h	1376;"	d
+PAD24_IE_SFT	include/ssv6200_aux.h	1378;"	d
+PAD24_IE_SZ	include/ssv6200_aux.h	1380;"	d
+PAD24_OD_HI	include/ssv6200_aux.h	1389;"	d
+PAD24_OD_I_MSK	include/ssv6200_aux.h	1387;"	d
+PAD24_OD_MSK	include/ssv6200_aux.h	1386;"	d
+PAD24_OD_SFT	include/ssv6200_aux.h	1388;"	d
+PAD24_OD_SZ	include/ssv6200_aux.h	1390;"	d
+PAD24_OE_HI	include/ssv6200_aux.h	1364;"	d
+PAD24_OE_I_MSK	include/ssv6200_aux.h	1362;"	d
+PAD24_OE_MSK	include/ssv6200_aux.h	1361;"	d
+PAD24_OE_SFT	include/ssv6200_aux.h	1363;"	d
+PAD24_OE_SZ	include/ssv6200_aux.h	1365;"	d
+PAD24_PE_HI	include/ssv6200_aux.h	1369;"	d
+PAD24_PE_I_MSK	include/ssv6200_aux.h	1367;"	d
+PAD24_PE_MSK	include/ssv6200_aux.h	1366;"	d
+PAD24_PE_SFT	include/ssv6200_aux.h	1368;"	d
+PAD24_PE_SZ	include/ssv6200_aux.h	1370;"	d
+PAD24_SEL_I_HI	include/ssv6200_aux.h	1384;"	d
+PAD24_SEL_I_I_MSK	include/ssv6200_aux.h	1382;"	d
+PAD24_SEL_I_MSK	include/ssv6200_aux.h	1381;"	d
+PAD24_SEL_I_SFT	include/ssv6200_aux.h	1383;"	d
+PAD24_SEL_I_SZ	include/ssv6200_aux.h	1385;"	d
+PAD24_SEL_O_HI	include/ssv6200_aux.h	1394;"	d
+PAD24_SEL_O_I_MSK	include/ssv6200_aux.h	1392;"	d
+PAD24_SEL_O_MSK	include/ssv6200_aux.h	1391;"	d
+PAD24_SEL_O_SFT	include/ssv6200_aux.h	1393;"	d
+PAD24_SEL_O_SZ	include/ssv6200_aux.h	1395;"	d
+PAD25_DS_HI	include/ssv6200_aux.h	1414;"	d
+PAD25_DS_I_MSK	include/ssv6200_aux.h	1412;"	d
+PAD25_DS_MSK	include/ssv6200_aux.h	1411;"	d
+PAD25_DS_SFT	include/ssv6200_aux.h	1413;"	d
+PAD25_DS_SZ	include/ssv6200_aux.h	1415;"	d
+PAD25_IE_HI	include/ssv6200_aux.h	1419;"	d
+PAD25_IE_I_MSK	include/ssv6200_aux.h	1417;"	d
+PAD25_IE_MSK	include/ssv6200_aux.h	1416;"	d
+PAD25_IE_SFT	include/ssv6200_aux.h	1418;"	d
+PAD25_IE_SZ	include/ssv6200_aux.h	1420;"	d
+PAD25_OD_HI	include/ssv6200_aux.h	1429;"	d
+PAD25_OD_I_MSK	include/ssv6200_aux.h	1427;"	d
+PAD25_OD_MSK	include/ssv6200_aux.h	1426;"	d
+PAD25_OD_SFT	include/ssv6200_aux.h	1428;"	d
+PAD25_OD_SZ	include/ssv6200_aux.h	1430;"	d
+PAD25_OE_HI	include/ssv6200_aux.h	1404;"	d
+PAD25_OE_I_MSK	include/ssv6200_aux.h	1402;"	d
+PAD25_OE_MSK	include/ssv6200_aux.h	1401;"	d
+PAD25_OE_SFT	include/ssv6200_aux.h	1403;"	d
+PAD25_OE_SZ	include/ssv6200_aux.h	1405;"	d
+PAD25_PE_HI	include/ssv6200_aux.h	1409;"	d
+PAD25_PE_I_MSK	include/ssv6200_aux.h	1407;"	d
+PAD25_PE_MSK	include/ssv6200_aux.h	1406;"	d
+PAD25_PE_SFT	include/ssv6200_aux.h	1408;"	d
+PAD25_PE_SZ	include/ssv6200_aux.h	1410;"	d
+PAD25_SEL_I_HI	include/ssv6200_aux.h	1424;"	d
+PAD25_SEL_I_I_MSK	include/ssv6200_aux.h	1422;"	d
+PAD25_SEL_I_MSK	include/ssv6200_aux.h	1421;"	d
+PAD25_SEL_I_SFT	include/ssv6200_aux.h	1423;"	d
+PAD25_SEL_I_SZ	include/ssv6200_aux.h	1425;"	d
+PAD25_SEL_OE_HI	include/ssv6200_aux.h	1439;"	d
+PAD25_SEL_OE_I_MSK	include/ssv6200_aux.h	1437;"	d
+PAD25_SEL_OE_MSK	include/ssv6200_aux.h	1436;"	d
+PAD25_SEL_OE_SFT	include/ssv6200_aux.h	1438;"	d
+PAD25_SEL_OE_SZ	include/ssv6200_aux.h	1440;"	d
+PAD25_SEL_O_HI	include/ssv6200_aux.h	1434;"	d
+PAD25_SEL_O_I_MSK	include/ssv6200_aux.h	1432;"	d
+PAD25_SEL_O_MSK	include/ssv6200_aux.h	1431;"	d
+PAD25_SEL_O_SFT	include/ssv6200_aux.h	1433;"	d
+PAD25_SEL_O_SZ	include/ssv6200_aux.h	1435;"	d
+PAD27_DS_HI	include/ssv6200_aux.h	1464;"	d
+PAD27_DS_I_MSK	include/ssv6200_aux.h	1462;"	d
+PAD27_DS_MSK	include/ssv6200_aux.h	1461;"	d
+PAD27_DS_SFT	include/ssv6200_aux.h	1463;"	d
+PAD27_DS_SZ	include/ssv6200_aux.h	1465;"	d
+PAD27_IE_HI	include/ssv6200_aux.h	1469;"	d
+PAD27_IE_I_MSK	include/ssv6200_aux.h	1467;"	d
+PAD27_IE_MSK	include/ssv6200_aux.h	1466;"	d
+PAD27_IE_SFT	include/ssv6200_aux.h	1468;"	d
+PAD27_IE_SZ	include/ssv6200_aux.h	1470;"	d
+PAD27_OD_HI	include/ssv6200_aux.h	1479;"	d
+PAD27_OD_I_MSK	include/ssv6200_aux.h	1477;"	d
+PAD27_OD_MSK	include/ssv6200_aux.h	1476;"	d
+PAD27_OD_SFT	include/ssv6200_aux.h	1478;"	d
+PAD27_OD_SZ	include/ssv6200_aux.h	1480;"	d
+PAD27_OE_HI	include/ssv6200_aux.h	1454;"	d
+PAD27_OE_I_MSK	include/ssv6200_aux.h	1452;"	d
+PAD27_OE_MSK	include/ssv6200_aux.h	1451;"	d
+PAD27_OE_SFT	include/ssv6200_aux.h	1453;"	d
+PAD27_OE_SZ	include/ssv6200_aux.h	1455;"	d
+PAD27_PE_HI	include/ssv6200_aux.h	1459;"	d
+PAD27_PE_I_MSK	include/ssv6200_aux.h	1457;"	d
+PAD27_PE_MSK	include/ssv6200_aux.h	1456;"	d
+PAD27_PE_SFT	include/ssv6200_aux.h	1458;"	d
+PAD27_PE_SZ	include/ssv6200_aux.h	1460;"	d
+PAD27_SEL_I_HI	include/ssv6200_aux.h	1474;"	d
+PAD27_SEL_I_I_MSK	include/ssv6200_aux.h	1472;"	d
+PAD27_SEL_I_MSK	include/ssv6200_aux.h	1471;"	d
+PAD27_SEL_I_SFT	include/ssv6200_aux.h	1473;"	d
+PAD27_SEL_I_SZ	include/ssv6200_aux.h	1475;"	d
+PAD27_SEL_O_HI	include/ssv6200_aux.h	1484;"	d
+PAD27_SEL_O_I_MSK	include/ssv6200_aux.h	1482;"	d
+PAD27_SEL_O_MSK	include/ssv6200_aux.h	1481;"	d
+PAD27_SEL_O_SFT	include/ssv6200_aux.h	1483;"	d
+PAD27_SEL_O_SZ	include/ssv6200_aux.h	1485;"	d
+PAD28_DS_HI	include/ssv6200_aux.h	1504;"	d
+PAD28_DS_I_MSK	include/ssv6200_aux.h	1502;"	d
+PAD28_DS_MSK	include/ssv6200_aux.h	1501;"	d
+PAD28_DS_SFT	include/ssv6200_aux.h	1503;"	d
+PAD28_DS_SZ	include/ssv6200_aux.h	1505;"	d
+PAD28_IE_HI	include/ssv6200_aux.h	1509;"	d
+PAD28_IE_I_MSK	include/ssv6200_aux.h	1507;"	d
+PAD28_IE_MSK	include/ssv6200_aux.h	1506;"	d
+PAD28_IE_SFT	include/ssv6200_aux.h	1508;"	d
+PAD28_IE_SZ	include/ssv6200_aux.h	1510;"	d
+PAD28_OD_HI	include/ssv6200_aux.h	1519;"	d
+PAD28_OD_I_MSK	include/ssv6200_aux.h	1517;"	d
+PAD28_OD_MSK	include/ssv6200_aux.h	1516;"	d
+PAD28_OD_SFT	include/ssv6200_aux.h	1518;"	d
+PAD28_OD_SZ	include/ssv6200_aux.h	1520;"	d
+PAD28_OE_HI	include/ssv6200_aux.h	1494;"	d
+PAD28_OE_I_MSK	include/ssv6200_aux.h	1492;"	d
+PAD28_OE_MSK	include/ssv6200_aux.h	1491;"	d
+PAD28_OE_SFT	include/ssv6200_aux.h	1493;"	d
+PAD28_OE_SZ	include/ssv6200_aux.h	1495;"	d
+PAD28_PE_HI	include/ssv6200_aux.h	1499;"	d
+PAD28_PE_I_MSK	include/ssv6200_aux.h	1497;"	d
+PAD28_PE_MSK	include/ssv6200_aux.h	1496;"	d
+PAD28_PE_SFT	include/ssv6200_aux.h	1498;"	d
+PAD28_PE_SZ	include/ssv6200_aux.h	1500;"	d
+PAD28_SEL_I_HI	include/ssv6200_aux.h	1514;"	d
+PAD28_SEL_I_I_MSK	include/ssv6200_aux.h	1512;"	d
+PAD28_SEL_I_MSK	include/ssv6200_aux.h	1511;"	d
+PAD28_SEL_I_SFT	include/ssv6200_aux.h	1513;"	d
+PAD28_SEL_I_SZ	include/ssv6200_aux.h	1515;"	d
+PAD28_SEL_OE_HI	include/ssv6200_aux.h	1529;"	d
+PAD28_SEL_OE_I_MSK	include/ssv6200_aux.h	1527;"	d
+PAD28_SEL_OE_MSK	include/ssv6200_aux.h	1526;"	d
+PAD28_SEL_OE_SFT	include/ssv6200_aux.h	1528;"	d
+PAD28_SEL_OE_SZ	include/ssv6200_aux.h	1530;"	d
+PAD28_SEL_O_HI	include/ssv6200_aux.h	1524;"	d
+PAD28_SEL_O_I_MSK	include/ssv6200_aux.h	1522;"	d
+PAD28_SEL_O_MSK	include/ssv6200_aux.h	1521;"	d
+PAD28_SEL_O_SFT	include/ssv6200_aux.h	1523;"	d
+PAD28_SEL_O_SZ	include/ssv6200_aux.h	1525;"	d
+PAD29_DS_HI	include/ssv6200_aux.h	1549;"	d
+PAD29_DS_I_MSK	include/ssv6200_aux.h	1547;"	d
+PAD29_DS_MSK	include/ssv6200_aux.h	1546;"	d
+PAD29_DS_SFT	include/ssv6200_aux.h	1548;"	d
+PAD29_DS_SZ	include/ssv6200_aux.h	1550;"	d
+PAD29_IE_HI	include/ssv6200_aux.h	1554;"	d
+PAD29_IE_I_MSK	include/ssv6200_aux.h	1552;"	d
+PAD29_IE_MSK	include/ssv6200_aux.h	1551;"	d
+PAD29_IE_SFT	include/ssv6200_aux.h	1553;"	d
+PAD29_IE_SZ	include/ssv6200_aux.h	1555;"	d
+PAD29_OD_HI	include/ssv6200_aux.h	1564;"	d
+PAD29_OD_I_MSK	include/ssv6200_aux.h	1562;"	d
+PAD29_OD_MSK	include/ssv6200_aux.h	1561;"	d
+PAD29_OD_SFT	include/ssv6200_aux.h	1563;"	d
+PAD29_OD_SZ	include/ssv6200_aux.h	1565;"	d
+PAD29_OE_HI	include/ssv6200_aux.h	1539;"	d
+PAD29_OE_I_MSK	include/ssv6200_aux.h	1537;"	d
+PAD29_OE_MSK	include/ssv6200_aux.h	1536;"	d
+PAD29_OE_SFT	include/ssv6200_aux.h	1538;"	d
+PAD29_OE_SZ	include/ssv6200_aux.h	1540;"	d
+PAD29_PE_HI	include/ssv6200_aux.h	1544;"	d
+PAD29_PE_I_MSK	include/ssv6200_aux.h	1542;"	d
+PAD29_PE_MSK	include/ssv6200_aux.h	1541;"	d
+PAD29_PE_SFT	include/ssv6200_aux.h	1543;"	d
+PAD29_PE_SZ	include/ssv6200_aux.h	1545;"	d
+PAD29_SEL_I_HI	include/ssv6200_aux.h	1559;"	d
+PAD29_SEL_I_I_MSK	include/ssv6200_aux.h	1557;"	d
+PAD29_SEL_I_MSK	include/ssv6200_aux.h	1556;"	d
+PAD29_SEL_I_SFT	include/ssv6200_aux.h	1558;"	d
+PAD29_SEL_I_SZ	include/ssv6200_aux.h	1560;"	d
+PAD29_SEL_O_HI	include/ssv6200_aux.h	1569;"	d
+PAD29_SEL_O_I_MSK	include/ssv6200_aux.h	1567;"	d
+PAD29_SEL_O_MSK	include/ssv6200_aux.h	1566;"	d
+PAD29_SEL_O_SFT	include/ssv6200_aux.h	1568;"	d
+PAD29_SEL_O_SZ	include/ssv6200_aux.h	1570;"	d
+PAD30_DS_HI	include/ssv6200_aux.h	1589;"	d
+PAD30_DS_I_MSK	include/ssv6200_aux.h	1587;"	d
+PAD30_DS_MSK	include/ssv6200_aux.h	1586;"	d
+PAD30_DS_SFT	include/ssv6200_aux.h	1588;"	d
+PAD30_DS_SZ	include/ssv6200_aux.h	1590;"	d
+PAD30_IE_HI	include/ssv6200_aux.h	1594;"	d
+PAD30_IE_I_MSK	include/ssv6200_aux.h	1592;"	d
+PAD30_IE_MSK	include/ssv6200_aux.h	1591;"	d
+PAD30_IE_SFT	include/ssv6200_aux.h	1593;"	d
+PAD30_IE_SZ	include/ssv6200_aux.h	1595;"	d
+PAD30_OD_HI	include/ssv6200_aux.h	1604;"	d
+PAD30_OD_I_MSK	include/ssv6200_aux.h	1602;"	d
+PAD30_OD_MSK	include/ssv6200_aux.h	1601;"	d
+PAD30_OD_SFT	include/ssv6200_aux.h	1603;"	d
+PAD30_OD_SZ	include/ssv6200_aux.h	1605;"	d
+PAD30_OE_HI	include/ssv6200_aux.h	1579;"	d
+PAD30_OE_I_MSK	include/ssv6200_aux.h	1577;"	d
+PAD30_OE_MSK	include/ssv6200_aux.h	1576;"	d
+PAD30_OE_SFT	include/ssv6200_aux.h	1578;"	d
+PAD30_OE_SZ	include/ssv6200_aux.h	1580;"	d
+PAD30_PE_HI	include/ssv6200_aux.h	1584;"	d
+PAD30_PE_I_MSK	include/ssv6200_aux.h	1582;"	d
+PAD30_PE_MSK	include/ssv6200_aux.h	1581;"	d
+PAD30_PE_SFT	include/ssv6200_aux.h	1583;"	d
+PAD30_PE_SZ	include/ssv6200_aux.h	1585;"	d
+PAD30_SEL_I_HI	include/ssv6200_aux.h	1599;"	d
+PAD30_SEL_I_I_MSK	include/ssv6200_aux.h	1597;"	d
+PAD30_SEL_I_MSK	include/ssv6200_aux.h	1596;"	d
+PAD30_SEL_I_SFT	include/ssv6200_aux.h	1598;"	d
+PAD30_SEL_I_SZ	include/ssv6200_aux.h	1600;"	d
+PAD30_SEL_O_HI	include/ssv6200_aux.h	1609;"	d
+PAD30_SEL_O_I_MSK	include/ssv6200_aux.h	1607;"	d
+PAD30_SEL_O_MSK	include/ssv6200_aux.h	1606;"	d
+PAD30_SEL_O_SFT	include/ssv6200_aux.h	1608;"	d
+PAD30_SEL_O_SZ	include/ssv6200_aux.h	1610;"	d
+PAD31_DS_HI	include/ssv6200_aux.h	1629;"	d
+PAD31_DS_I_MSK	include/ssv6200_aux.h	1627;"	d
+PAD31_DS_MSK	include/ssv6200_aux.h	1626;"	d
+PAD31_DS_SFT	include/ssv6200_aux.h	1628;"	d
+PAD31_DS_SZ	include/ssv6200_aux.h	1630;"	d
+PAD31_IE_HI	include/ssv6200_aux.h	1634;"	d
+PAD31_IE_I_MSK	include/ssv6200_aux.h	1632;"	d
+PAD31_IE_MSK	include/ssv6200_aux.h	1631;"	d
+PAD31_IE_SFT	include/ssv6200_aux.h	1633;"	d
+PAD31_IE_SZ	include/ssv6200_aux.h	1635;"	d
+PAD31_OD_HI	include/ssv6200_aux.h	1644;"	d
+PAD31_OD_I_MSK	include/ssv6200_aux.h	1642;"	d
+PAD31_OD_MSK	include/ssv6200_aux.h	1641;"	d
+PAD31_OD_SFT	include/ssv6200_aux.h	1643;"	d
+PAD31_OD_SZ	include/ssv6200_aux.h	1645;"	d
+PAD31_OE_HI	include/ssv6200_aux.h	1619;"	d
+PAD31_OE_I_MSK	include/ssv6200_aux.h	1617;"	d
+PAD31_OE_MSK	include/ssv6200_aux.h	1616;"	d
+PAD31_OE_SFT	include/ssv6200_aux.h	1618;"	d
+PAD31_OE_SZ	include/ssv6200_aux.h	1620;"	d
+PAD31_PE_HI	include/ssv6200_aux.h	1624;"	d
+PAD31_PE_I_MSK	include/ssv6200_aux.h	1622;"	d
+PAD31_PE_MSK	include/ssv6200_aux.h	1621;"	d
+PAD31_PE_SFT	include/ssv6200_aux.h	1623;"	d
+PAD31_PE_SZ	include/ssv6200_aux.h	1625;"	d
+PAD31_SEL_I_HI	include/ssv6200_aux.h	1639;"	d
+PAD31_SEL_I_I_MSK	include/ssv6200_aux.h	1637;"	d
+PAD31_SEL_I_MSK	include/ssv6200_aux.h	1636;"	d
+PAD31_SEL_I_SFT	include/ssv6200_aux.h	1638;"	d
+PAD31_SEL_I_SZ	include/ssv6200_aux.h	1640;"	d
+PAD31_SEL_O_HI	include/ssv6200_aux.h	1649;"	d
+PAD31_SEL_O_I_MSK	include/ssv6200_aux.h	1647;"	d
+PAD31_SEL_O_MSK	include/ssv6200_aux.h	1646;"	d
+PAD31_SEL_O_SFT	include/ssv6200_aux.h	1648;"	d
+PAD31_SEL_O_SZ	include/ssv6200_aux.h	1650;"	d
+PAD32_DS_HI	include/ssv6200_aux.h	1669;"	d
+PAD32_DS_I_MSK	include/ssv6200_aux.h	1667;"	d
+PAD32_DS_MSK	include/ssv6200_aux.h	1666;"	d
+PAD32_DS_SFT	include/ssv6200_aux.h	1668;"	d
+PAD32_DS_SZ	include/ssv6200_aux.h	1670;"	d
+PAD32_IE_HI	include/ssv6200_aux.h	1674;"	d
+PAD32_IE_I_MSK	include/ssv6200_aux.h	1672;"	d
+PAD32_IE_MSK	include/ssv6200_aux.h	1671;"	d
+PAD32_IE_SFT	include/ssv6200_aux.h	1673;"	d
+PAD32_IE_SZ	include/ssv6200_aux.h	1675;"	d
+PAD32_OD_HI	include/ssv6200_aux.h	1684;"	d
+PAD32_OD_I_MSK	include/ssv6200_aux.h	1682;"	d
+PAD32_OD_MSK	include/ssv6200_aux.h	1681;"	d
+PAD32_OD_SFT	include/ssv6200_aux.h	1683;"	d
+PAD32_OD_SZ	include/ssv6200_aux.h	1685;"	d
+PAD32_OE_HI	include/ssv6200_aux.h	1659;"	d
+PAD32_OE_I_MSK	include/ssv6200_aux.h	1657;"	d
+PAD32_OE_MSK	include/ssv6200_aux.h	1656;"	d
+PAD32_OE_SFT	include/ssv6200_aux.h	1658;"	d
+PAD32_OE_SZ	include/ssv6200_aux.h	1660;"	d
+PAD32_PE_HI	include/ssv6200_aux.h	1664;"	d
+PAD32_PE_I_MSK	include/ssv6200_aux.h	1662;"	d
+PAD32_PE_MSK	include/ssv6200_aux.h	1661;"	d
+PAD32_PE_SFT	include/ssv6200_aux.h	1663;"	d
+PAD32_PE_SZ	include/ssv6200_aux.h	1665;"	d
+PAD32_SEL_I_HI	include/ssv6200_aux.h	1679;"	d
+PAD32_SEL_I_I_MSK	include/ssv6200_aux.h	1677;"	d
+PAD32_SEL_I_MSK	include/ssv6200_aux.h	1676;"	d
+PAD32_SEL_I_SFT	include/ssv6200_aux.h	1678;"	d
+PAD32_SEL_I_SZ	include/ssv6200_aux.h	1680;"	d
+PAD32_SEL_O_HI	include/ssv6200_aux.h	1689;"	d
+PAD32_SEL_O_I_MSK	include/ssv6200_aux.h	1687;"	d
+PAD32_SEL_O_MSK	include/ssv6200_aux.h	1686;"	d
+PAD32_SEL_O_SFT	include/ssv6200_aux.h	1688;"	d
+PAD32_SEL_O_SZ	include/ssv6200_aux.h	1690;"	d
+PAD33_DS_HI	include/ssv6200_aux.h	1709;"	d
+PAD33_DS_I_MSK	include/ssv6200_aux.h	1707;"	d
+PAD33_DS_MSK	include/ssv6200_aux.h	1706;"	d
+PAD33_DS_SFT	include/ssv6200_aux.h	1708;"	d
+PAD33_DS_SZ	include/ssv6200_aux.h	1710;"	d
+PAD33_IE_HI	include/ssv6200_aux.h	1714;"	d
+PAD33_IE_I_MSK	include/ssv6200_aux.h	1712;"	d
+PAD33_IE_MSK	include/ssv6200_aux.h	1711;"	d
+PAD33_IE_SFT	include/ssv6200_aux.h	1713;"	d
+PAD33_IE_SZ	include/ssv6200_aux.h	1715;"	d
+PAD33_OD_HI	include/ssv6200_aux.h	1724;"	d
+PAD33_OD_I_MSK	include/ssv6200_aux.h	1722;"	d
+PAD33_OD_MSK	include/ssv6200_aux.h	1721;"	d
+PAD33_OD_SFT	include/ssv6200_aux.h	1723;"	d
+PAD33_OD_SZ	include/ssv6200_aux.h	1725;"	d
+PAD33_OE_HI	include/ssv6200_aux.h	1699;"	d
+PAD33_OE_I_MSK	include/ssv6200_aux.h	1697;"	d
+PAD33_OE_MSK	include/ssv6200_aux.h	1696;"	d
+PAD33_OE_SFT	include/ssv6200_aux.h	1698;"	d
+PAD33_OE_SZ	include/ssv6200_aux.h	1700;"	d
+PAD33_PE_HI	include/ssv6200_aux.h	1704;"	d
+PAD33_PE_I_MSK	include/ssv6200_aux.h	1702;"	d
+PAD33_PE_MSK	include/ssv6200_aux.h	1701;"	d
+PAD33_PE_SFT	include/ssv6200_aux.h	1703;"	d
+PAD33_PE_SZ	include/ssv6200_aux.h	1705;"	d
+PAD33_SEL_I_HI	include/ssv6200_aux.h	1719;"	d
+PAD33_SEL_I_I_MSK	include/ssv6200_aux.h	1717;"	d
+PAD33_SEL_I_MSK	include/ssv6200_aux.h	1716;"	d
+PAD33_SEL_I_SFT	include/ssv6200_aux.h	1718;"	d
+PAD33_SEL_I_SZ	include/ssv6200_aux.h	1720;"	d
+PAD33_SEL_O_HI	include/ssv6200_aux.h	1729;"	d
+PAD33_SEL_O_I_MSK	include/ssv6200_aux.h	1727;"	d
+PAD33_SEL_O_MSK	include/ssv6200_aux.h	1726;"	d
+PAD33_SEL_O_SFT	include/ssv6200_aux.h	1728;"	d
+PAD33_SEL_O_SZ	include/ssv6200_aux.h	1730;"	d
+PAD34_DS_HI	include/ssv6200_aux.h	1749;"	d
+PAD34_DS_I_MSK	include/ssv6200_aux.h	1747;"	d
+PAD34_DS_MSK	include/ssv6200_aux.h	1746;"	d
+PAD34_DS_SFT	include/ssv6200_aux.h	1748;"	d
+PAD34_DS_SZ	include/ssv6200_aux.h	1750;"	d
+PAD34_IE_HI	include/ssv6200_aux.h	1754;"	d
+PAD34_IE_I_MSK	include/ssv6200_aux.h	1752;"	d
+PAD34_IE_MSK	include/ssv6200_aux.h	1751;"	d
+PAD34_IE_SFT	include/ssv6200_aux.h	1753;"	d
+PAD34_IE_SZ	include/ssv6200_aux.h	1755;"	d
+PAD34_OD_HI	include/ssv6200_aux.h	1764;"	d
+PAD34_OD_I_MSK	include/ssv6200_aux.h	1762;"	d
+PAD34_OD_MSK	include/ssv6200_aux.h	1761;"	d
+PAD34_OD_SFT	include/ssv6200_aux.h	1763;"	d
+PAD34_OD_SZ	include/ssv6200_aux.h	1765;"	d
+PAD34_OE_HI	include/ssv6200_aux.h	1739;"	d
+PAD34_OE_I_MSK	include/ssv6200_aux.h	1737;"	d
+PAD34_OE_MSK	include/ssv6200_aux.h	1736;"	d
+PAD34_OE_SFT	include/ssv6200_aux.h	1738;"	d
+PAD34_OE_SZ	include/ssv6200_aux.h	1740;"	d
+PAD34_PE_HI	include/ssv6200_aux.h	1744;"	d
+PAD34_PE_I_MSK	include/ssv6200_aux.h	1742;"	d
+PAD34_PE_MSK	include/ssv6200_aux.h	1741;"	d
+PAD34_PE_SFT	include/ssv6200_aux.h	1743;"	d
+PAD34_PE_SZ	include/ssv6200_aux.h	1745;"	d
+PAD34_SEL_I_HI	include/ssv6200_aux.h	1759;"	d
+PAD34_SEL_I_I_MSK	include/ssv6200_aux.h	1757;"	d
+PAD34_SEL_I_MSK	include/ssv6200_aux.h	1756;"	d
+PAD34_SEL_I_SFT	include/ssv6200_aux.h	1758;"	d
+PAD34_SEL_I_SZ	include/ssv6200_aux.h	1760;"	d
+PAD34_SEL_O_HI	include/ssv6200_aux.h	1769;"	d
+PAD34_SEL_O_I_MSK	include/ssv6200_aux.h	1767;"	d
+PAD34_SEL_O_MSK	include/ssv6200_aux.h	1766;"	d
+PAD34_SEL_O_SFT	include/ssv6200_aux.h	1768;"	d
+PAD34_SEL_O_SZ	include/ssv6200_aux.h	1770;"	d
+PAD42_DS_HI	include/ssv6200_aux.h	1789;"	d
+PAD42_DS_I_MSK	include/ssv6200_aux.h	1787;"	d
+PAD42_DS_MSK	include/ssv6200_aux.h	1786;"	d
+PAD42_DS_SFT	include/ssv6200_aux.h	1788;"	d
+PAD42_DS_SZ	include/ssv6200_aux.h	1790;"	d
+PAD42_IE_HI	include/ssv6200_aux.h	1794;"	d
+PAD42_IE_I_MSK	include/ssv6200_aux.h	1792;"	d
+PAD42_IE_MSK	include/ssv6200_aux.h	1791;"	d
+PAD42_IE_SFT	include/ssv6200_aux.h	1793;"	d
+PAD42_IE_SZ	include/ssv6200_aux.h	1795;"	d
+PAD42_OD_HI	include/ssv6200_aux.h	1804;"	d
+PAD42_OD_I_MSK	include/ssv6200_aux.h	1802;"	d
+PAD42_OD_MSK	include/ssv6200_aux.h	1801;"	d
+PAD42_OD_SFT	include/ssv6200_aux.h	1803;"	d
+PAD42_OD_SZ	include/ssv6200_aux.h	1805;"	d
+PAD42_OE_HI	include/ssv6200_aux.h	1779;"	d
+PAD42_OE_I_MSK	include/ssv6200_aux.h	1777;"	d
+PAD42_OE_MSK	include/ssv6200_aux.h	1776;"	d
+PAD42_OE_SFT	include/ssv6200_aux.h	1778;"	d
+PAD42_OE_SZ	include/ssv6200_aux.h	1780;"	d
+PAD42_PE_HI	include/ssv6200_aux.h	1784;"	d
+PAD42_PE_I_MSK	include/ssv6200_aux.h	1782;"	d
+PAD42_PE_MSK	include/ssv6200_aux.h	1781;"	d
+PAD42_PE_SFT	include/ssv6200_aux.h	1783;"	d
+PAD42_PE_SZ	include/ssv6200_aux.h	1785;"	d
+PAD42_SEL_I_HI	include/ssv6200_aux.h	1799;"	d
+PAD42_SEL_I_I_MSK	include/ssv6200_aux.h	1797;"	d
+PAD42_SEL_I_MSK	include/ssv6200_aux.h	1796;"	d
+PAD42_SEL_I_SFT	include/ssv6200_aux.h	1798;"	d
+PAD42_SEL_I_SZ	include/ssv6200_aux.h	1800;"	d
+PAD42_SEL_O_HI	include/ssv6200_aux.h	1809;"	d
+PAD42_SEL_O_I_MSK	include/ssv6200_aux.h	1807;"	d
+PAD42_SEL_O_MSK	include/ssv6200_aux.h	1806;"	d
+PAD42_SEL_O_SFT	include/ssv6200_aux.h	1808;"	d
+PAD42_SEL_O_SZ	include/ssv6200_aux.h	1810;"	d
+PAD43_DS_HI	include/ssv6200_aux.h	1829;"	d
+PAD43_DS_I_MSK	include/ssv6200_aux.h	1827;"	d
+PAD43_DS_MSK	include/ssv6200_aux.h	1826;"	d
+PAD43_DS_SFT	include/ssv6200_aux.h	1828;"	d
+PAD43_DS_SZ	include/ssv6200_aux.h	1830;"	d
+PAD43_IE_HI	include/ssv6200_aux.h	1834;"	d
+PAD43_IE_I_MSK	include/ssv6200_aux.h	1832;"	d
+PAD43_IE_MSK	include/ssv6200_aux.h	1831;"	d
+PAD43_IE_SFT	include/ssv6200_aux.h	1833;"	d
+PAD43_IE_SZ	include/ssv6200_aux.h	1835;"	d
+PAD43_OD_HI	include/ssv6200_aux.h	1844;"	d
+PAD43_OD_I_MSK	include/ssv6200_aux.h	1842;"	d
+PAD43_OD_MSK	include/ssv6200_aux.h	1841;"	d
+PAD43_OD_SFT	include/ssv6200_aux.h	1843;"	d
+PAD43_OD_SZ	include/ssv6200_aux.h	1845;"	d
+PAD43_OE_HI	include/ssv6200_aux.h	1819;"	d
+PAD43_OE_I_MSK	include/ssv6200_aux.h	1817;"	d
+PAD43_OE_MSK	include/ssv6200_aux.h	1816;"	d
+PAD43_OE_SFT	include/ssv6200_aux.h	1818;"	d
+PAD43_OE_SZ	include/ssv6200_aux.h	1820;"	d
+PAD43_PE_HI	include/ssv6200_aux.h	1824;"	d
+PAD43_PE_I_MSK	include/ssv6200_aux.h	1822;"	d
+PAD43_PE_MSK	include/ssv6200_aux.h	1821;"	d
+PAD43_PE_SFT	include/ssv6200_aux.h	1823;"	d
+PAD43_PE_SZ	include/ssv6200_aux.h	1825;"	d
+PAD43_SEL_I_HI	include/ssv6200_aux.h	1839;"	d
+PAD43_SEL_I_I_MSK	include/ssv6200_aux.h	1837;"	d
+PAD43_SEL_I_MSK	include/ssv6200_aux.h	1836;"	d
+PAD43_SEL_I_SFT	include/ssv6200_aux.h	1838;"	d
+PAD43_SEL_I_SZ	include/ssv6200_aux.h	1840;"	d
+PAD43_SEL_O_HI	include/ssv6200_aux.h	1849;"	d
+PAD43_SEL_O_I_MSK	include/ssv6200_aux.h	1847;"	d
+PAD43_SEL_O_MSK	include/ssv6200_aux.h	1846;"	d
+PAD43_SEL_O_SFT	include/ssv6200_aux.h	1848;"	d
+PAD43_SEL_O_SZ	include/ssv6200_aux.h	1850;"	d
+PAD44_DS_HI	include/ssv6200_aux.h	1869;"	d
+PAD44_DS_I_MSK	include/ssv6200_aux.h	1867;"	d
+PAD44_DS_MSK	include/ssv6200_aux.h	1866;"	d
+PAD44_DS_SFT	include/ssv6200_aux.h	1868;"	d
+PAD44_DS_SZ	include/ssv6200_aux.h	1870;"	d
+PAD44_IE_HI	include/ssv6200_aux.h	1874;"	d
+PAD44_IE_I_MSK	include/ssv6200_aux.h	1872;"	d
+PAD44_IE_MSK	include/ssv6200_aux.h	1871;"	d
+PAD44_IE_SFT	include/ssv6200_aux.h	1873;"	d
+PAD44_IE_SZ	include/ssv6200_aux.h	1875;"	d
+PAD44_OD_HI	include/ssv6200_aux.h	1884;"	d
+PAD44_OD_I_MSK	include/ssv6200_aux.h	1882;"	d
+PAD44_OD_MSK	include/ssv6200_aux.h	1881;"	d
+PAD44_OD_SFT	include/ssv6200_aux.h	1883;"	d
+PAD44_OD_SZ	include/ssv6200_aux.h	1885;"	d
+PAD44_OE_HI	include/ssv6200_aux.h	1859;"	d
+PAD44_OE_I_MSK	include/ssv6200_aux.h	1857;"	d
+PAD44_OE_MSK	include/ssv6200_aux.h	1856;"	d
+PAD44_OE_SFT	include/ssv6200_aux.h	1858;"	d
+PAD44_OE_SZ	include/ssv6200_aux.h	1860;"	d
+PAD44_PE_HI	include/ssv6200_aux.h	1864;"	d
+PAD44_PE_I_MSK	include/ssv6200_aux.h	1862;"	d
+PAD44_PE_MSK	include/ssv6200_aux.h	1861;"	d
+PAD44_PE_SFT	include/ssv6200_aux.h	1863;"	d
+PAD44_PE_SZ	include/ssv6200_aux.h	1865;"	d
+PAD44_SEL_I_HI	include/ssv6200_aux.h	1879;"	d
+PAD44_SEL_I_I_MSK	include/ssv6200_aux.h	1877;"	d
+PAD44_SEL_I_MSK	include/ssv6200_aux.h	1876;"	d
+PAD44_SEL_I_SFT	include/ssv6200_aux.h	1878;"	d
+PAD44_SEL_I_SZ	include/ssv6200_aux.h	1880;"	d
+PAD44_SEL_O_HI	include/ssv6200_aux.h	1889;"	d
+PAD44_SEL_O_I_MSK	include/ssv6200_aux.h	1887;"	d
+PAD44_SEL_O_MSK	include/ssv6200_aux.h	1886;"	d
+PAD44_SEL_O_SFT	include/ssv6200_aux.h	1888;"	d
+PAD44_SEL_O_SZ	include/ssv6200_aux.h	1890;"	d
+PAD45_DS_HI	include/ssv6200_aux.h	1909;"	d
+PAD45_DS_I_MSK	include/ssv6200_aux.h	1907;"	d
+PAD45_DS_MSK	include/ssv6200_aux.h	1906;"	d
+PAD45_DS_SFT	include/ssv6200_aux.h	1908;"	d
+PAD45_DS_SZ	include/ssv6200_aux.h	1910;"	d
+PAD45_IE_HI	include/ssv6200_aux.h	1914;"	d
+PAD45_IE_I_MSK	include/ssv6200_aux.h	1912;"	d
+PAD45_IE_MSK	include/ssv6200_aux.h	1911;"	d
+PAD45_IE_SFT	include/ssv6200_aux.h	1913;"	d
+PAD45_IE_SZ	include/ssv6200_aux.h	1915;"	d
+PAD45_OD_HI	include/ssv6200_aux.h	1924;"	d
+PAD45_OD_I_MSK	include/ssv6200_aux.h	1922;"	d
+PAD45_OD_MSK	include/ssv6200_aux.h	1921;"	d
+PAD45_OD_SFT	include/ssv6200_aux.h	1923;"	d
+PAD45_OD_SZ	include/ssv6200_aux.h	1925;"	d
+PAD45_OE_HI	include/ssv6200_aux.h	1899;"	d
+PAD45_OE_I_MSK	include/ssv6200_aux.h	1897;"	d
+PAD45_OE_MSK	include/ssv6200_aux.h	1896;"	d
+PAD45_OE_SFT	include/ssv6200_aux.h	1898;"	d
+PAD45_OE_SZ	include/ssv6200_aux.h	1900;"	d
+PAD45_PE_HI	include/ssv6200_aux.h	1904;"	d
+PAD45_PE_I_MSK	include/ssv6200_aux.h	1902;"	d
+PAD45_PE_MSK	include/ssv6200_aux.h	1901;"	d
+PAD45_PE_SFT	include/ssv6200_aux.h	1903;"	d
+PAD45_PE_SZ	include/ssv6200_aux.h	1905;"	d
+PAD45_SEL_I_HI	include/ssv6200_aux.h	1919;"	d
+PAD45_SEL_I_I_MSK	include/ssv6200_aux.h	1917;"	d
+PAD45_SEL_I_MSK	include/ssv6200_aux.h	1916;"	d
+PAD45_SEL_I_SFT	include/ssv6200_aux.h	1918;"	d
+PAD45_SEL_I_SZ	include/ssv6200_aux.h	1920;"	d
+PAD45_SEL_O_HI	include/ssv6200_aux.h	1929;"	d
+PAD45_SEL_O_I_MSK	include/ssv6200_aux.h	1927;"	d
+PAD45_SEL_O_MSK	include/ssv6200_aux.h	1926;"	d
+PAD45_SEL_O_SFT	include/ssv6200_aux.h	1928;"	d
+PAD45_SEL_O_SZ	include/ssv6200_aux.h	1930;"	d
+PAD46_DS_HI	include/ssv6200_aux.h	1949;"	d
+PAD46_DS_I_MSK	include/ssv6200_aux.h	1947;"	d
+PAD46_DS_MSK	include/ssv6200_aux.h	1946;"	d
+PAD46_DS_SFT	include/ssv6200_aux.h	1948;"	d
+PAD46_DS_SZ	include/ssv6200_aux.h	1950;"	d
+PAD46_IE_HI	include/ssv6200_aux.h	1954;"	d
+PAD46_IE_I_MSK	include/ssv6200_aux.h	1952;"	d
+PAD46_IE_MSK	include/ssv6200_aux.h	1951;"	d
+PAD46_IE_SFT	include/ssv6200_aux.h	1953;"	d
+PAD46_IE_SZ	include/ssv6200_aux.h	1955;"	d
+PAD46_OD_HI	include/ssv6200_aux.h	1964;"	d
+PAD46_OD_I_MSK	include/ssv6200_aux.h	1962;"	d
+PAD46_OD_MSK	include/ssv6200_aux.h	1961;"	d
+PAD46_OD_SFT	include/ssv6200_aux.h	1963;"	d
+PAD46_OD_SZ	include/ssv6200_aux.h	1965;"	d
+PAD46_OE_HI	include/ssv6200_aux.h	1939;"	d
+PAD46_OE_I_MSK	include/ssv6200_aux.h	1937;"	d
+PAD46_OE_MSK	include/ssv6200_aux.h	1936;"	d
+PAD46_OE_SFT	include/ssv6200_aux.h	1938;"	d
+PAD46_OE_SZ	include/ssv6200_aux.h	1940;"	d
+PAD46_PE_HI	include/ssv6200_aux.h	1944;"	d
+PAD46_PE_I_MSK	include/ssv6200_aux.h	1942;"	d
+PAD46_PE_MSK	include/ssv6200_aux.h	1941;"	d
+PAD46_PE_SFT	include/ssv6200_aux.h	1943;"	d
+PAD46_PE_SZ	include/ssv6200_aux.h	1945;"	d
+PAD46_SEL_I_HI	include/ssv6200_aux.h	1959;"	d
+PAD46_SEL_I_I_MSK	include/ssv6200_aux.h	1957;"	d
+PAD46_SEL_I_MSK	include/ssv6200_aux.h	1956;"	d
+PAD46_SEL_I_SFT	include/ssv6200_aux.h	1958;"	d
+PAD46_SEL_I_SZ	include/ssv6200_aux.h	1960;"	d
+PAD46_SEL_O_HI	include/ssv6200_aux.h	1969;"	d
+PAD46_SEL_O_I_MSK	include/ssv6200_aux.h	1967;"	d
+PAD46_SEL_O_MSK	include/ssv6200_aux.h	1966;"	d
+PAD46_SEL_O_SFT	include/ssv6200_aux.h	1968;"	d
+PAD46_SEL_O_SZ	include/ssv6200_aux.h	1970;"	d
+PAD47_DS_HI	include/ssv6200_aux.h	1989;"	d
+PAD47_DS_I_MSK	include/ssv6200_aux.h	1987;"	d
+PAD47_DS_MSK	include/ssv6200_aux.h	1986;"	d
+PAD47_DS_SFT	include/ssv6200_aux.h	1988;"	d
+PAD47_DS_SZ	include/ssv6200_aux.h	1990;"	d
+PAD47_OD_HI	include/ssv6200_aux.h	1999;"	d
+PAD47_OD_I_MSK	include/ssv6200_aux.h	1997;"	d
+PAD47_OD_MSK	include/ssv6200_aux.h	1996;"	d
+PAD47_OD_SFT	include/ssv6200_aux.h	1998;"	d
+PAD47_OD_SZ	include/ssv6200_aux.h	2000;"	d
+PAD47_OE_HI	include/ssv6200_aux.h	1979;"	d
+PAD47_OE_I_MSK	include/ssv6200_aux.h	1977;"	d
+PAD47_OE_MSK	include/ssv6200_aux.h	1976;"	d
+PAD47_OE_SFT	include/ssv6200_aux.h	1978;"	d
+PAD47_OE_SZ	include/ssv6200_aux.h	1980;"	d
+PAD47_PE_HI	include/ssv6200_aux.h	1984;"	d
+PAD47_PE_I_MSK	include/ssv6200_aux.h	1982;"	d
+PAD47_PE_MSK	include/ssv6200_aux.h	1981;"	d
+PAD47_PE_SFT	include/ssv6200_aux.h	1983;"	d
+PAD47_PE_SZ	include/ssv6200_aux.h	1985;"	d
+PAD47_SEL_I_HI	include/ssv6200_aux.h	1994;"	d
+PAD47_SEL_I_I_MSK	include/ssv6200_aux.h	1992;"	d
+PAD47_SEL_I_MSK	include/ssv6200_aux.h	1991;"	d
+PAD47_SEL_I_SFT	include/ssv6200_aux.h	1993;"	d
+PAD47_SEL_I_SZ	include/ssv6200_aux.h	1995;"	d
+PAD47_SEL_OE_HI	include/ssv6200_aux.h	2009;"	d
+PAD47_SEL_OE_I_MSK	include/ssv6200_aux.h	2007;"	d
+PAD47_SEL_OE_MSK	include/ssv6200_aux.h	2006;"	d
+PAD47_SEL_OE_SFT	include/ssv6200_aux.h	2008;"	d
+PAD47_SEL_OE_SZ	include/ssv6200_aux.h	2010;"	d
+PAD47_SEL_O_HI	include/ssv6200_aux.h	2004;"	d
+PAD47_SEL_O_I_MSK	include/ssv6200_aux.h	2002;"	d
+PAD47_SEL_O_MSK	include/ssv6200_aux.h	2001;"	d
+PAD47_SEL_O_SFT	include/ssv6200_aux.h	2003;"	d
+PAD47_SEL_O_SZ	include/ssv6200_aux.h	2005;"	d
+PAD48_DS_HI	include/ssv6200_aux.h	2029;"	d
+PAD48_DS_I_MSK	include/ssv6200_aux.h	2027;"	d
+PAD48_DS_MSK	include/ssv6200_aux.h	2026;"	d
+PAD48_DS_SFT	include/ssv6200_aux.h	2028;"	d
+PAD48_DS_SZ	include/ssv6200_aux.h	2030;"	d
+PAD48_IE_HI	include/ssv6200_aux.h	2034;"	d
+PAD48_IE_I_MSK	include/ssv6200_aux.h	2032;"	d
+PAD48_IE_MSK	include/ssv6200_aux.h	2031;"	d
+PAD48_IE_SFT	include/ssv6200_aux.h	2033;"	d
+PAD48_IE_SZ	include/ssv6200_aux.h	2035;"	d
+PAD48_OD_HI	include/ssv6200_aux.h	2044;"	d
+PAD48_OD_I_MSK	include/ssv6200_aux.h	2042;"	d
+PAD48_OD_MSK	include/ssv6200_aux.h	2041;"	d
+PAD48_OD_SFT	include/ssv6200_aux.h	2043;"	d
+PAD48_OD_SZ	include/ssv6200_aux.h	2045;"	d
+PAD48_OE_HI	include/ssv6200_aux.h	2019;"	d
+PAD48_OE_I_MSK	include/ssv6200_aux.h	2017;"	d
+PAD48_OE_MSK	include/ssv6200_aux.h	2016;"	d
+PAD48_OE_SFT	include/ssv6200_aux.h	2018;"	d
+PAD48_OE_SZ	include/ssv6200_aux.h	2020;"	d
+PAD48_PE_HI	include/ssv6200_aux.h	2024;"	d
+PAD48_PE_I_MSK	include/ssv6200_aux.h	2022;"	d
+PAD48_PE_MSK	include/ssv6200_aux.h	2021;"	d
+PAD48_PE_SEL_HI	include/ssv6200_aux.h	2049;"	d
+PAD48_PE_SEL_I_MSK	include/ssv6200_aux.h	2047;"	d
+PAD48_PE_SEL_MSK	include/ssv6200_aux.h	2046;"	d
+PAD48_PE_SEL_SFT	include/ssv6200_aux.h	2048;"	d
+PAD48_PE_SEL_SZ	include/ssv6200_aux.h	2050;"	d
+PAD48_PE_SFT	include/ssv6200_aux.h	2023;"	d
+PAD48_PE_SZ	include/ssv6200_aux.h	2025;"	d
+PAD48_SEL_I_HI	include/ssv6200_aux.h	2039;"	d
+PAD48_SEL_I_I_MSK	include/ssv6200_aux.h	2037;"	d
+PAD48_SEL_I_MSK	include/ssv6200_aux.h	2036;"	d
+PAD48_SEL_I_SFT	include/ssv6200_aux.h	2038;"	d
+PAD48_SEL_I_SZ	include/ssv6200_aux.h	2040;"	d
+PAD48_SEL_OE_HI	include/ssv6200_aux.h	2059;"	d
+PAD48_SEL_OE_I_MSK	include/ssv6200_aux.h	2057;"	d
+PAD48_SEL_OE_MSK	include/ssv6200_aux.h	2056;"	d
+PAD48_SEL_OE_SFT	include/ssv6200_aux.h	2058;"	d
+PAD48_SEL_OE_SZ	include/ssv6200_aux.h	2060;"	d
+PAD48_SEL_O_HI	include/ssv6200_aux.h	2054;"	d
+PAD48_SEL_O_I_MSK	include/ssv6200_aux.h	2052;"	d
+PAD48_SEL_O_MSK	include/ssv6200_aux.h	2051;"	d
+PAD48_SEL_O_SFT	include/ssv6200_aux.h	2053;"	d
+PAD48_SEL_O_SZ	include/ssv6200_aux.h	2055;"	d
+PAD49_DS_HI	include/ssv6200_aux.h	2079;"	d
+PAD49_DS_I_MSK	include/ssv6200_aux.h	2077;"	d
+PAD49_DS_MSK	include/ssv6200_aux.h	2076;"	d
+PAD49_DS_SFT	include/ssv6200_aux.h	2078;"	d
+PAD49_DS_SZ	include/ssv6200_aux.h	2080;"	d
+PAD49_IE_HI	include/ssv6200_aux.h	2084;"	d
+PAD49_IE_I_MSK	include/ssv6200_aux.h	2082;"	d
+PAD49_IE_MSK	include/ssv6200_aux.h	2081;"	d
+PAD49_IE_SFT	include/ssv6200_aux.h	2083;"	d
+PAD49_IE_SZ	include/ssv6200_aux.h	2085;"	d
+PAD49_OD_HI	include/ssv6200_aux.h	2094;"	d
+PAD49_OD_I_MSK	include/ssv6200_aux.h	2092;"	d
+PAD49_OD_MSK	include/ssv6200_aux.h	2091;"	d
+PAD49_OD_SFT	include/ssv6200_aux.h	2093;"	d
+PAD49_OD_SZ	include/ssv6200_aux.h	2095;"	d
+PAD49_OE_HI	include/ssv6200_aux.h	2069;"	d
+PAD49_OE_I_MSK	include/ssv6200_aux.h	2067;"	d
+PAD49_OE_MSK	include/ssv6200_aux.h	2066;"	d
+PAD49_OE_SFT	include/ssv6200_aux.h	2068;"	d
+PAD49_OE_SZ	include/ssv6200_aux.h	2070;"	d
+PAD49_PE_HI	include/ssv6200_aux.h	2074;"	d
+PAD49_PE_I_MSK	include/ssv6200_aux.h	2072;"	d
+PAD49_PE_MSK	include/ssv6200_aux.h	2071;"	d
+PAD49_PE_SFT	include/ssv6200_aux.h	2073;"	d
+PAD49_PE_SZ	include/ssv6200_aux.h	2075;"	d
+PAD49_SEL_I_HI	include/ssv6200_aux.h	2089;"	d
+PAD49_SEL_I_I_MSK	include/ssv6200_aux.h	2087;"	d
+PAD49_SEL_I_MSK	include/ssv6200_aux.h	2086;"	d
+PAD49_SEL_I_SFT	include/ssv6200_aux.h	2088;"	d
+PAD49_SEL_I_SZ	include/ssv6200_aux.h	2090;"	d
+PAD49_SEL_OE_HI	include/ssv6200_aux.h	2104;"	d
+PAD49_SEL_OE_I_MSK	include/ssv6200_aux.h	2102;"	d
+PAD49_SEL_OE_MSK	include/ssv6200_aux.h	2101;"	d
+PAD49_SEL_OE_SFT	include/ssv6200_aux.h	2103;"	d
+PAD49_SEL_OE_SZ	include/ssv6200_aux.h	2105;"	d
+PAD49_SEL_O_HI	include/ssv6200_aux.h	2099;"	d
+PAD49_SEL_O_I_MSK	include/ssv6200_aux.h	2097;"	d
+PAD49_SEL_O_MSK	include/ssv6200_aux.h	2096;"	d
+PAD49_SEL_O_SFT	include/ssv6200_aux.h	2098;"	d
+PAD49_SEL_O_SZ	include/ssv6200_aux.h	2100;"	d
+PAD50_DS_HI	include/ssv6200_aux.h	2124;"	d
+PAD50_DS_I_MSK	include/ssv6200_aux.h	2122;"	d
+PAD50_DS_MSK	include/ssv6200_aux.h	2121;"	d
+PAD50_DS_SFT	include/ssv6200_aux.h	2123;"	d
+PAD50_DS_SZ	include/ssv6200_aux.h	2125;"	d
+PAD50_IE_HI	include/ssv6200_aux.h	2129;"	d
+PAD50_IE_I_MSK	include/ssv6200_aux.h	2127;"	d
+PAD50_IE_MSK	include/ssv6200_aux.h	2126;"	d
+PAD50_IE_SFT	include/ssv6200_aux.h	2128;"	d
+PAD50_IE_SZ	include/ssv6200_aux.h	2130;"	d
+PAD50_OD_HI	include/ssv6200_aux.h	2139;"	d
+PAD50_OD_I_MSK	include/ssv6200_aux.h	2137;"	d
+PAD50_OD_MSK	include/ssv6200_aux.h	2136;"	d
+PAD50_OD_SFT	include/ssv6200_aux.h	2138;"	d
+PAD50_OD_SZ	include/ssv6200_aux.h	2140;"	d
+PAD50_OE_HI	include/ssv6200_aux.h	2114;"	d
+PAD50_OE_I_MSK	include/ssv6200_aux.h	2112;"	d
+PAD50_OE_MSK	include/ssv6200_aux.h	2111;"	d
+PAD50_OE_SFT	include/ssv6200_aux.h	2113;"	d
+PAD50_OE_SZ	include/ssv6200_aux.h	2115;"	d
+PAD50_PE_HI	include/ssv6200_aux.h	2119;"	d
+PAD50_PE_I_MSK	include/ssv6200_aux.h	2117;"	d
+PAD50_PE_MSK	include/ssv6200_aux.h	2116;"	d
+PAD50_PE_SFT	include/ssv6200_aux.h	2118;"	d
+PAD50_PE_SZ	include/ssv6200_aux.h	2120;"	d
+PAD50_SEL_I_HI	include/ssv6200_aux.h	2134;"	d
+PAD50_SEL_I_I_MSK	include/ssv6200_aux.h	2132;"	d
+PAD50_SEL_I_MSK	include/ssv6200_aux.h	2131;"	d
+PAD50_SEL_I_SFT	include/ssv6200_aux.h	2133;"	d
+PAD50_SEL_I_SZ	include/ssv6200_aux.h	2135;"	d
+PAD50_SEL_OE_HI	include/ssv6200_aux.h	2149;"	d
+PAD50_SEL_OE_I_MSK	include/ssv6200_aux.h	2147;"	d
+PAD50_SEL_OE_MSK	include/ssv6200_aux.h	2146;"	d
+PAD50_SEL_OE_SFT	include/ssv6200_aux.h	2148;"	d
+PAD50_SEL_OE_SZ	include/ssv6200_aux.h	2150;"	d
+PAD50_SEL_O_HI	include/ssv6200_aux.h	2144;"	d
+PAD50_SEL_O_I_MSK	include/ssv6200_aux.h	2142;"	d
+PAD50_SEL_O_MSK	include/ssv6200_aux.h	2141;"	d
+PAD50_SEL_O_SFT	include/ssv6200_aux.h	2143;"	d
+PAD50_SEL_O_SZ	include/ssv6200_aux.h	2145;"	d
+PAD51_DS_HI	include/ssv6200_aux.h	2169;"	d
+PAD51_DS_I_MSK	include/ssv6200_aux.h	2167;"	d
+PAD51_DS_MSK	include/ssv6200_aux.h	2166;"	d
+PAD51_DS_SFT	include/ssv6200_aux.h	2168;"	d
+PAD51_DS_SZ	include/ssv6200_aux.h	2170;"	d
+PAD51_IE_HI	include/ssv6200_aux.h	2174;"	d
+PAD51_IE_I_MSK	include/ssv6200_aux.h	2172;"	d
+PAD51_IE_MSK	include/ssv6200_aux.h	2171;"	d
+PAD51_IE_SFT	include/ssv6200_aux.h	2173;"	d
+PAD51_IE_SZ	include/ssv6200_aux.h	2175;"	d
+PAD51_OD_HI	include/ssv6200_aux.h	2184;"	d
+PAD51_OD_I_MSK	include/ssv6200_aux.h	2182;"	d
+PAD51_OD_MSK	include/ssv6200_aux.h	2181;"	d
+PAD51_OD_SFT	include/ssv6200_aux.h	2183;"	d
+PAD51_OD_SZ	include/ssv6200_aux.h	2185;"	d
+PAD51_OE_HI	include/ssv6200_aux.h	2159;"	d
+PAD51_OE_I_MSK	include/ssv6200_aux.h	2157;"	d
+PAD51_OE_MSK	include/ssv6200_aux.h	2156;"	d
+PAD51_OE_SFT	include/ssv6200_aux.h	2158;"	d
+PAD51_OE_SZ	include/ssv6200_aux.h	2160;"	d
+PAD51_PE_HI	include/ssv6200_aux.h	2164;"	d
+PAD51_PE_I_MSK	include/ssv6200_aux.h	2162;"	d
+PAD51_PE_MSK	include/ssv6200_aux.h	2161;"	d
+PAD51_PE_SFT	include/ssv6200_aux.h	2163;"	d
+PAD51_PE_SZ	include/ssv6200_aux.h	2165;"	d
+PAD51_SEL_I_HI	include/ssv6200_aux.h	2179;"	d
+PAD51_SEL_I_I_MSK	include/ssv6200_aux.h	2177;"	d
+PAD51_SEL_I_MSK	include/ssv6200_aux.h	2176;"	d
+PAD51_SEL_I_SFT	include/ssv6200_aux.h	2178;"	d
+PAD51_SEL_I_SZ	include/ssv6200_aux.h	2180;"	d
+PAD51_SEL_OE_HI	include/ssv6200_aux.h	2194;"	d
+PAD51_SEL_OE_I_MSK	include/ssv6200_aux.h	2192;"	d
+PAD51_SEL_OE_MSK	include/ssv6200_aux.h	2191;"	d
+PAD51_SEL_OE_SFT	include/ssv6200_aux.h	2193;"	d
+PAD51_SEL_OE_SZ	include/ssv6200_aux.h	2195;"	d
+PAD51_SEL_O_HI	include/ssv6200_aux.h	2189;"	d
+PAD51_SEL_O_I_MSK	include/ssv6200_aux.h	2187;"	d
+PAD51_SEL_O_MSK	include/ssv6200_aux.h	2186;"	d
+PAD51_SEL_O_SFT	include/ssv6200_aux.h	2188;"	d
+PAD51_SEL_O_SZ	include/ssv6200_aux.h	2190;"	d
+PAD52_DS_HI	include/ssv6200_aux.h	2214;"	d
+PAD52_DS_I_MSK	include/ssv6200_aux.h	2212;"	d
+PAD52_DS_MSK	include/ssv6200_aux.h	2211;"	d
+PAD52_DS_SFT	include/ssv6200_aux.h	2213;"	d
+PAD52_DS_SZ	include/ssv6200_aux.h	2215;"	d
+PAD52_OD_HI	include/ssv6200_aux.h	2224;"	d
+PAD52_OD_I_MSK	include/ssv6200_aux.h	2222;"	d
+PAD52_OD_MSK	include/ssv6200_aux.h	2221;"	d
+PAD52_OD_SFT	include/ssv6200_aux.h	2223;"	d
+PAD52_OD_SZ	include/ssv6200_aux.h	2225;"	d
+PAD52_OE_HI	include/ssv6200_aux.h	2204;"	d
+PAD52_OE_I_MSK	include/ssv6200_aux.h	2202;"	d
+PAD52_OE_MSK	include/ssv6200_aux.h	2201;"	d
+PAD52_OE_SFT	include/ssv6200_aux.h	2203;"	d
+PAD52_OE_SZ	include/ssv6200_aux.h	2205;"	d
+PAD52_PE_HI	include/ssv6200_aux.h	2209;"	d
+PAD52_PE_I_MSK	include/ssv6200_aux.h	2207;"	d
+PAD52_PE_MSK	include/ssv6200_aux.h	2206;"	d
+PAD52_PE_SFT	include/ssv6200_aux.h	2208;"	d
+PAD52_PE_SZ	include/ssv6200_aux.h	2210;"	d
+PAD52_SEL_I_HI	include/ssv6200_aux.h	2219;"	d
+PAD52_SEL_I_I_MSK	include/ssv6200_aux.h	2217;"	d
+PAD52_SEL_I_MSK	include/ssv6200_aux.h	2216;"	d
+PAD52_SEL_I_SFT	include/ssv6200_aux.h	2218;"	d
+PAD52_SEL_I_SZ	include/ssv6200_aux.h	2220;"	d
+PAD52_SEL_OE_HI	include/ssv6200_aux.h	2234;"	d
+PAD52_SEL_OE_I_MSK	include/ssv6200_aux.h	2232;"	d
+PAD52_SEL_OE_MSK	include/ssv6200_aux.h	2231;"	d
+PAD52_SEL_OE_SFT	include/ssv6200_aux.h	2233;"	d
+PAD52_SEL_OE_SZ	include/ssv6200_aux.h	2235;"	d
+PAD52_SEL_O_HI	include/ssv6200_aux.h	2229;"	d
+PAD52_SEL_O_I_MSK	include/ssv6200_aux.h	2227;"	d
+PAD52_SEL_O_MSK	include/ssv6200_aux.h	2226;"	d
+PAD52_SEL_O_SFT	include/ssv6200_aux.h	2228;"	d
+PAD52_SEL_O_SZ	include/ssv6200_aux.h	2230;"	d
+PAD53_DS_HI	include/ssv6200_aux.h	2254;"	d
+PAD53_DS_I_MSK	include/ssv6200_aux.h	2252;"	d
+PAD53_DS_MSK	include/ssv6200_aux.h	2251;"	d
+PAD53_DS_SFT	include/ssv6200_aux.h	2253;"	d
+PAD53_DS_SZ	include/ssv6200_aux.h	2255;"	d
+PAD53_IE_HI	include/ssv6200_aux.h	2259;"	d
+PAD53_IE_I_MSK	include/ssv6200_aux.h	2257;"	d
+PAD53_IE_MSK	include/ssv6200_aux.h	2256;"	d
+PAD53_IE_SFT	include/ssv6200_aux.h	2258;"	d
+PAD53_IE_SZ	include/ssv6200_aux.h	2260;"	d
+PAD53_OD_HI	include/ssv6200_aux.h	2269;"	d
+PAD53_OD_I_MSK	include/ssv6200_aux.h	2267;"	d
+PAD53_OD_MSK	include/ssv6200_aux.h	2266;"	d
+PAD53_OD_SFT	include/ssv6200_aux.h	2268;"	d
+PAD53_OD_SZ	include/ssv6200_aux.h	2270;"	d
+PAD53_OE_HI	include/ssv6200_aux.h	2244;"	d
+PAD53_OE_I_MSK	include/ssv6200_aux.h	2242;"	d
+PAD53_OE_MSK	include/ssv6200_aux.h	2241;"	d
+PAD53_OE_SFT	include/ssv6200_aux.h	2243;"	d
+PAD53_OE_SZ	include/ssv6200_aux.h	2245;"	d
+PAD53_PE_HI	include/ssv6200_aux.h	2249;"	d
+PAD53_PE_I_MSK	include/ssv6200_aux.h	2247;"	d
+PAD53_PE_MSK	include/ssv6200_aux.h	2246;"	d
+PAD53_PE_SFT	include/ssv6200_aux.h	2248;"	d
+PAD53_PE_SZ	include/ssv6200_aux.h	2250;"	d
+PAD53_SEL_I_HI	include/ssv6200_aux.h	2264;"	d
+PAD53_SEL_I_I_MSK	include/ssv6200_aux.h	2262;"	d
+PAD53_SEL_I_MSK	include/ssv6200_aux.h	2261;"	d
+PAD53_SEL_I_SFT	include/ssv6200_aux.h	2263;"	d
+PAD53_SEL_I_SZ	include/ssv6200_aux.h	2265;"	d
+PAD53_SEL_O_HI	include/ssv6200_aux.h	2274;"	d
+PAD53_SEL_O_I_MSK	include/ssv6200_aux.h	2272;"	d
+PAD53_SEL_O_MSK	include/ssv6200_aux.h	2271;"	d
+PAD53_SEL_O_SFT	include/ssv6200_aux.h	2273;"	d
+PAD53_SEL_O_SZ	include/ssv6200_aux.h	2275;"	d
+PAD54_DS_HI	include/ssv6200_aux.h	2294;"	d
+PAD54_DS_I_MSK	include/ssv6200_aux.h	2292;"	d
+PAD54_DS_MSK	include/ssv6200_aux.h	2291;"	d
+PAD54_DS_SFT	include/ssv6200_aux.h	2293;"	d
+PAD54_DS_SZ	include/ssv6200_aux.h	2295;"	d
+PAD54_OD_HI	include/ssv6200_aux.h	2299;"	d
+PAD54_OD_I_MSK	include/ssv6200_aux.h	2297;"	d
+PAD54_OD_MSK	include/ssv6200_aux.h	2296;"	d
+PAD54_OD_SFT	include/ssv6200_aux.h	2298;"	d
+PAD54_OD_SZ	include/ssv6200_aux.h	2300;"	d
+PAD54_OE_HI	include/ssv6200_aux.h	2284;"	d
+PAD54_OE_I_MSK	include/ssv6200_aux.h	2282;"	d
+PAD54_OE_MSK	include/ssv6200_aux.h	2281;"	d
+PAD54_OE_SFT	include/ssv6200_aux.h	2283;"	d
+PAD54_OE_SZ	include/ssv6200_aux.h	2285;"	d
+PAD54_PE_HI	include/ssv6200_aux.h	2289;"	d
+PAD54_PE_I_MSK	include/ssv6200_aux.h	2287;"	d
+PAD54_PE_MSK	include/ssv6200_aux.h	2286;"	d
+PAD54_PE_SFT	include/ssv6200_aux.h	2288;"	d
+PAD54_PE_SZ	include/ssv6200_aux.h	2290;"	d
+PAD54_SEL_O_HI	include/ssv6200_aux.h	2304;"	d
+PAD54_SEL_O_I_MSK	include/ssv6200_aux.h	2302;"	d
+PAD54_SEL_O_MSK	include/ssv6200_aux.h	2301;"	d
+PAD54_SEL_O_SFT	include/ssv6200_aux.h	2303;"	d
+PAD54_SEL_O_SZ	include/ssv6200_aux.h	2305;"	d
+PAD56_DS_HI	include/ssv6200_aux.h	2319;"	d
+PAD56_DS_I_MSK	include/ssv6200_aux.h	2317;"	d
+PAD56_DS_MSK	include/ssv6200_aux.h	2316;"	d
+PAD56_DS_SFT	include/ssv6200_aux.h	2318;"	d
+PAD56_DS_SZ	include/ssv6200_aux.h	2320;"	d
+PAD56_OD_HI	include/ssv6200_aux.h	2329;"	d
+PAD56_OD_I_MSK	include/ssv6200_aux.h	2327;"	d
+PAD56_OD_MSK	include/ssv6200_aux.h	2326;"	d
+PAD56_OD_SFT	include/ssv6200_aux.h	2328;"	d
+PAD56_OD_SZ	include/ssv6200_aux.h	2330;"	d
+PAD56_PE_HI	include/ssv6200_aux.h	2314;"	d
+PAD56_PE_I_MSK	include/ssv6200_aux.h	2312;"	d
+PAD56_PE_MSK	include/ssv6200_aux.h	2311;"	d
+PAD56_PE_SFT	include/ssv6200_aux.h	2313;"	d
+PAD56_PE_SZ	include/ssv6200_aux.h	2315;"	d
+PAD56_SEL_I_HI	include/ssv6200_aux.h	2324;"	d
+PAD56_SEL_I_I_MSK	include/ssv6200_aux.h	2322;"	d
+PAD56_SEL_I_MSK	include/ssv6200_aux.h	2321;"	d
+PAD56_SEL_I_SFT	include/ssv6200_aux.h	2323;"	d
+PAD56_SEL_I_SZ	include/ssv6200_aux.h	2325;"	d
+PAD57_DS_HI	include/ssv6200_aux.h	2349;"	d
+PAD57_DS_I_MSK	include/ssv6200_aux.h	2347;"	d
+PAD57_DS_MSK	include/ssv6200_aux.h	2346;"	d
+PAD57_DS_SFT	include/ssv6200_aux.h	2348;"	d
+PAD57_DS_SZ	include/ssv6200_aux.h	2350;"	d
+PAD57_IE_HI	include/ssv6200_aux.h	2354;"	d
+PAD57_IE_I_MSK	include/ssv6200_aux.h	2352;"	d
+PAD57_IE_MSK	include/ssv6200_aux.h	2351;"	d
+PAD57_IE_SFT	include/ssv6200_aux.h	2353;"	d
+PAD57_IE_SZ	include/ssv6200_aux.h	2355;"	d
+PAD57_OD_HI	include/ssv6200_aux.h	2364;"	d
+PAD57_OD_I_MSK	include/ssv6200_aux.h	2362;"	d
+PAD57_OD_MSK	include/ssv6200_aux.h	2361;"	d
+PAD57_OD_SFT	include/ssv6200_aux.h	2363;"	d
+PAD57_OD_SZ	include/ssv6200_aux.h	2365;"	d
+PAD57_OE_HI	include/ssv6200_aux.h	2339;"	d
+PAD57_OE_I_MSK	include/ssv6200_aux.h	2337;"	d
+PAD57_OE_MSK	include/ssv6200_aux.h	2336;"	d
+PAD57_OE_SFT	include/ssv6200_aux.h	2338;"	d
+PAD57_OE_SZ	include/ssv6200_aux.h	2340;"	d
+PAD57_PE_HI	include/ssv6200_aux.h	2344;"	d
+PAD57_PE_I_MSK	include/ssv6200_aux.h	2342;"	d
+PAD57_PE_MSK	include/ssv6200_aux.h	2341;"	d
+PAD57_PE_SFT	include/ssv6200_aux.h	2343;"	d
+PAD57_PE_SZ	include/ssv6200_aux.h	2345;"	d
+PAD57_SEL_I_HI	include/ssv6200_aux.h	2359;"	d
+PAD57_SEL_I_I_MSK	include/ssv6200_aux.h	2357;"	d
+PAD57_SEL_I_MSK	include/ssv6200_aux.h	2356;"	d
+PAD57_SEL_I_SFT	include/ssv6200_aux.h	2358;"	d
+PAD57_SEL_I_SZ	include/ssv6200_aux.h	2360;"	d
+PAD57_SEL_OE_HI	include/ssv6200_aux.h	2374;"	d
+PAD57_SEL_OE_I_MSK	include/ssv6200_aux.h	2372;"	d
+PAD57_SEL_OE_MSK	include/ssv6200_aux.h	2371;"	d
+PAD57_SEL_OE_SFT	include/ssv6200_aux.h	2373;"	d
+PAD57_SEL_OE_SZ	include/ssv6200_aux.h	2375;"	d
+PAD57_SEL_O_HI	include/ssv6200_aux.h	2369;"	d
+PAD57_SEL_O_I_MSK	include/ssv6200_aux.h	2367;"	d
+PAD57_SEL_O_MSK	include/ssv6200_aux.h	2366;"	d
+PAD57_SEL_O_SFT	include/ssv6200_aux.h	2368;"	d
+PAD57_SEL_O_SZ	include/ssv6200_aux.h	2370;"	d
+PAD58_DS_HI	include/ssv6200_aux.h	2394;"	d
+PAD58_DS_I_MSK	include/ssv6200_aux.h	2392;"	d
+PAD58_DS_MSK	include/ssv6200_aux.h	2391;"	d
+PAD58_DS_SFT	include/ssv6200_aux.h	2393;"	d
+PAD58_DS_SZ	include/ssv6200_aux.h	2395;"	d
+PAD58_IE_HI	include/ssv6200_aux.h	2399;"	d
+PAD58_IE_I_MSK	include/ssv6200_aux.h	2397;"	d
+PAD58_IE_MSK	include/ssv6200_aux.h	2396;"	d
+PAD58_IE_SFT	include/ssv6200_aux.h	2398;"	d
+PAD58_IE_SZ	include/ssv6200_aux.h	2400;"	d
+PAD58_OD_HI	include/ssv6200_aux.h	2409;"	d
+PAD58_OD_I_MSK	include/ssv6200_aux.h	2407;"	d
+PAD58_OD_MSK	include/ssv6200_aux.h	2406;"	d
+PAD58_OD_SFT	include/ssv6200_aux.h	2408;"	d
+PAD58_OD_SZ	include/ssv6200_aux.h	2410;"	d
+PAD58_OE_HI	include/ssv6200_aux.h	2384;"	d
+PAD58_OE_I_MSK	include/ssv6200_aux.h	2382;"	d
+PAD58_OE_MSK	include/ssv6200_aux.h	2381;"	d
+PAD58_OE_SFT	include/ssv6200_aux.h	2383;"	d
+PAD58_OE_SZ	include/ssv6200_aux.h	2385;"	d
+PAD58_PE_HI	include/ssv6200_aux.h	2389;"	d
+PAD58_PE_I_MSK	include/ssv6200_aux.h	2387;"	d
+PAD58_PE_MSK	include/ssv6200_aux.h	2386;"	d
+PAD58_PE_SFT	include/ssv6200_aux.h	2388;"	d
+PAD58_PE_SZ	include/ssv6200_aux.h	2390;"	d
+PAD58_SEL_I_HI	include/ssv6200_aux.h	2404;"	d
+PAD58_SEL_I_I_MSK	include/ssv6200_aux.h	2402;"	d
+PAD58_SEL_I_MSK	include/ssv6200_aux.h	2401;"	d
+PAD58_SEL_I_SFT	include/ssv6200_aux.h	2403;"	d
+PAD58_SEL_I_SZ	include/ssv6200_aux.h	2405;"	d
+PAD58_SEL_O_HI	include/ssv6200_aux.h	2414;"	d
+PAD58_SEL_O_I_MSK	include/ssv6200_aux.h	2412;"	d
+PAD58_SEL_O_MSK	include/ssv6200_aux.h	2411;"	d
+PAD58_SEL_O_SFT	include/ssv6200_aux.h	2413;"	d
+PAD58_SEL_O_SZ	include/ssv6200_aux.h	2415;"	d
+PAD59_DS_HI	include/ssv6200_aux.h	2434;"	d
+PAD59_DS_I_MSK	include/ssv6200_aux.h	2432;"	d
+PAD59_DS_MSK	include/ssv6200_aux.h	2431;"	d
+PAD59_DS_SFT	include/ssv6200_aux.h	2433;"	d
+PAD59_DS_SZ	include/ssv6200_aux.h	2435;"	d
+PAD59_IE_HI	include/ssv6200_aux.h	2439;"	d
+PAD59_IE_I_MSK	include/ssv6200_aux.h	2437;"	d
+PAD59_IE_MSK	include/ssv6200_aux.h	2436;"	d
+PAD59_IE_SFT	include/ssv6200_aux.h	2438;"	d
+PAD59_IE_SZ	include/ssv6200_aux.h	2440;"	d
+PAD59_OD_HI	include/ssv6200_aux.h	2449;"	d
+PAD59_OD_I_MSK	include/ssv6200_aux.h	2447;"	d
+PAD59_OD_MSK	include/ssv6200_aux.h	2446;"	d
+PAD59_OD_SFT	include/ssv6200_aux.h	2448;"	d
+PAD59_OD_SZ	include/ssv6200_aux.h	2450;"	d
+PAD59_OE_HI	include/ssv6200_aux.h	2424;"	d
+PAD59_OE_I_MSK	include/ssv6200_aux.h	2422;"	d
+PAD59_OE_MSK	include/ssv6200_aux.h	2421;"	d
+PAD59_OE_SFT	include/ssv6200_aux.h	2423;"	d
+PAD59_OE_SZ	include/ssv6200_aux.h	2425;"	d
+PAD59_PE_HI	include/ssv6200_aux.h	2429;"	d
+PAD59_PE_I_MSK	include/ssv6200_aux.h	2427;"	d
+PAD59_PE_MSK	include/ssv6200_aux.h	2426;"	d
+PAD59_PE_SFT	include/ssv6200_aux.h	2428;"	d
+PAD59_PE_SZ	include/ssv6200_aux.h	2430;"	d
+PAD59_SEL_I_HI	include/ssv6200_aux.h	2444;"	d
+PAD59_SEL_I_I_MSK	include/ssv6200_aux.h	2442;"	d
+PAD59_SEL_I_MSK	include/ssv6200_aux.h	2441;"	d
+PAD59_SEL_I_SFT	include/ssv6200_aux.h	2443;"	d
+PAD59_SEL_I_SZ	include/ssv6200_aux.h	2445;"	d
+PAD59_SEL_O_HI	include/ssv6200_aux.h	2454;"	d
+PAD59_SEL_O_I_MSK	include/ssv6200_aux.h	2452;"	d
+PAD59_SEL_O_MSK	include/ssv6200_aux.h	2451;"	d
+PAD59_SEL_O_SFT	include/ssv6200_aux.h	2453;"	d
+PAD59_SEL_O_SZ	include/ssv6200_aux.h	2455;"	d
+PAD60_DS_HI	include/ssv6200_aux.h	2474;"	d
+PAD60_DS_I_MSK	include/ssv6200_aux.h	2472;"	d
+PAD60_DS_MSK	include/ssv6200_aux.h	2471;"	d
+PAD60_DS_SFT	include/ssv6200_aux.h	2473;"	d
+PAD60_DS_SZ	include/ssv6200_aux.h	2475;"	d
+PAD60_IE_HI	include/ssv6200_aux.h	2479;"	d
+PAD60_IE_I_MSK	include/ssv6200_aux.h	2477;"	d
+PAD60_IE_MSK	include/ssv6200_aux.h	2476;"	d
+PAD60_IE_SFT	include/ssv6200_aux.h	2478;"	d
+PAD60_IE_SZ	include/ssv6200_aux.h	2480;"	d
+PAD60_OD_HI	include/ssv6200_aux.h	2489;"	d
+PAD60_OD_I_MSK	include/ssv6200_aux.h	2487;"	d
+PAD60_OD_MSK	include/ssv6200_aux.h	2486;"	d
+PAD60_OD_SFT	include/ssv6200_aux.h	2488;"	d
+PAD60_OD_SZ	include/ssv6200_aux.h	2490;"	d
+PAD60_OE_HI	include/ssv6200_aux.h	2464;"	d
+PAD60_OE_I_MSK	include/ssv6200_aux.h	2462;"	d
+PAD60_OE_MSK	include/ssv6200_aux.h	2461;"	d
+PAD60_OE_SFT	include/ssv6200_aux.h	2463;"	d
+PAD60_OE_SZ	include/ssv6200_aux.h	2465;"	d
+PAD60_PE_HI	include/ssv6200_aux.h	2469;"	d
+PAD60_PE_I_MSK	include/ssv6200_aux.h	2467;"	d
+PAD60_PE_MSK	include/ssv6200_aux.h	2466;"	d
+PAD60_PE_SFT	include/ssv6200_aux.h	2468;"	d
+PAD60_PE_SZ	include/ssv6200_aux.h	2470;"	d
+PAD60_SEL_I_HI	include/ssv6200_aux.h	2484;"	d
+PAD60_SEL_I_I_MSK	include/ssv6200_aux.h	2482;"	d
+PAD60_SEL_I_MSK	include/ssv6200_aux.h	2481;"	d
+PAD60_SEL_I_SFT	include/ssv6200_aux.h	2483;"	d
+PAD60_SEL_I_SZ	include/ssv6200_aux.h	2485;"	d
+PAD60_SEL_O_HI	include/ssv6200_aux.h	2494;"	d
+PAD60_SEL_O_I_MSK	include/ssv6200_aux.h	2492;"	d
+PAD60_SEL_O_MSK	include/ssv6200_aux.h	2491;"	d
+PAD60_SEL_O_SFT	include/ssv6200_aux.h	2493;"	d
+PAD60_SEL_O_SZ	include/ssv6200_aux.h	2495;"	d
+PAD61_DS_HI	include/ssv6200_aux.h	2514;"	d
+PAD61_DS_I_MSK	include/ssv6200_aux.h	2512;"	d
+PAD61_DS_MSK	include/ssv6200_aux.h	2511;"	d
+PAD61_DS_SFT	include/ssv6200_aux.h	2513;"	d
+PAD61_DS_SZ	include/ssv6200_aux.h	2515;"	d
+PAD61_IE_HI	include/ssv6200_aux.h	2519;"	d
+PAD61_IE_I_MSK	include/ssv6200_aux.h	2517;"	d
+PAD61_IE_MSK	include/ssv6200_aux.h	2516;"	d
+PAD61_IE_SFT	include/ssv6200_aux.h	2518;"	d
+PAD61_IE_SZ	include/ssv6200_aux.h	2520;"	d
+PAD61_OD_HI	include/ssv6200_aux.h	2529;"	d
+PAD61_OD_I_MSK	include/ssv6200_aux.h	2527;"	d
+PAD61_OD_MSK	include/ssv6200_aux.h	2526;"	d
+PAD61_OD_SFT	include/ssv6200_aux.h	2528;"	d
+PAD61_OD_SZ	include/ssv6200_aux.h	2530;"	d
+PAD61_OE_HI	include/ssv6200_aux.h	2504;"	d
+PAD61_OE_I_MSK	include/ssv6200_aux.h	2502;"	d
+PAD61_OE_MSK	include/ssv6200_aux.h	2501;"	d
+PAD61_OE_SFT	include/ssv6200_aux.h	2503;"	d
+PAD61_OE_SZ	include/ssv6200_aux.h	2505;"	d
+PAD61_PE_HI	include/ssv6200_aux.h	2509;"	d
+PAD61_PE_I_MSK	include/ssv6200_aux.h	2507;"	d
+PAD61_PE_MSK	include/ssv6200_aux.h	2506;"	d
+PAD61_PE_SFT	include/ssv6200_aux.h	2508;"	d
+PAD61_PE_SZ	include/ssv6200_aux.h	2510;"	d
+PAD61_SEL_I_HI	include/ssv6200_aux.h	2524;"	d
+PAD61_SEL_I_I_MSK	include/ssv6200_aux.h	2522;"	d
+PAD61_SEL_I_MSK	include/ssv6200_aux.h	2521;"	d
+PAD61_SEL_I_SFT	include/ssv6200_aux.h	2523;"	d
+PAD61_SEL_I_SZ	include/ssv6200_aux.h	2525;"	d
+PAD61_SEL_O_HI	include/ssv6200_aux.h	2534;"	d
+PAD61_SEL_O_I_MSK	include/ssv6200_aux.h	2532;"	d
+PAD61_SEL_O_MSK	include/ssv6200_aux.h	2531;"	d
+PAD61_SEL_O_SFT	include/ssv6200_aux.h	2533;"	d
+PAD61_SEL_O_SZ	include/ssv6200_aux.h	2535;"	d
+PAD62_DS_HI	include/ssv6200_aux.h	2554;"	d
+PAD62_DS_I_MSK	include/ssv6200_aux.h	2552;"	d
+PAD62_DS_MSK	include/ssv6200_aux.h	2551;"	d
+PAD62_DS_SFT	include/ssv6200_aux.h	2553;"	d
+PAD62_DS_SZ	include/ssv6200_aux.h	2555;"	d
+PAD62_IE_HI	include/ssv6200_aux.h	2559;"	d
+PAD62_IE_I_MSK	include/ssv6200_aux.h	2557;"	d
+PAD62_IE_MSK	include/ssv6200_aux.h	2556;"	d
+PAD62_IE_SFT	include/ssv6200_aux.h	2558;"	d
+PAD62_IE_SZ	include/ssv6200_aux.h	2560;"	d
+PAD62_OD_HI	include/ssv6200_aux.h	2569;"	d
+PAD62_OD_I_MSK	include/ssv6200_aux.h	2567;"	d
+PAD62_OD_MSK	include/ssv6200_aux.h	2566;"	d
+PAD62_OD_SFT	include/ssv6200_aux.h	2568;"	d
+PAD62_OD_SZ	include/ssv6200_aux.h	2570;"	d
+PAD62_OE_HI	include/ssv6200_aux.h	2544;"	d
+PAD62_OE_I_MSK	include/ssv6200_aux.h	2542;"	d
+PAD62_OE_MSK	include/ssv6200_aux.h	2541;"	d
+PAD62_OE_SFT	include/ssv6200_aux.h	2543;"	d
+PAD62_OE_SZ	include/ssv6200_aux.h	2545;"	d
+PAD62_PE_HI	include/ssv6200_aux.h	2549;"	d
+PAD62_PE_I_MSK	include/ssv6200_aux.h	2547;"	d
+PAD62_PE_MSK	include/ssv6200_aux.h	2546;"	d
+PAD62_PE_SFT	include/ssv6200_aux.h	2548;"	d
+PAD62_PE_SZ	include/ssv6200_aux.h	2550;"	d
+PAD62_SEL_I_HI	include/ssv6200_aux.h	2564;"	d
+PAD62_SEL_I_I_MSK	include/ssv6200_aux.h	2562;"	d
+PAD62_SEL_I_MSK	include/ssv6200_aux.h	2561;"	d
+PAD62_SEL_I_SFT	include/ssv6200_aux.h	2563;"	d
+PAD62_SEL_I_SZ	include/ssv6200_aux.h	2565;"	d
+PAD62_SEL_O_HI	include/ssv6200_aux.h	2574;"	d
+PAD62_SEL_O_I_MSK	include/ssv6200_aux.h	2572;"	d
+PAD62_SEL_O_MSK	include/ssv6200_aux.h	2571;"	d
+PAD62_SEL_O_SFT	include/ssv6200_aux.h	2573;"	d
+PAD62_SEL_O_SZ	include/ssv6200_aux.h	2575;"	d
+PAD64_DS_HI	include/ssv6200_aux.h	2594;"	d
+PAD64_DS_I_MSK	include/ssv6200_aux.h	2592;"	d
+PAD64_DS_MSK	include/ssv6200_aux.h	2591;"	d
+PAD64_DS_SFT	include/ssv6200_aux.h	2593;"	d
+PAD64_DS_SZ	include/ssv6200_aux.h	2595;"	d
+PAD64_IE_HI	include/ssv6200_aux.h	2599;"	d
+PAD64_IE_I_MSK	include/ssv6200_aux.h	2597;"	d
+PAD64_IE_MSK	include/ssv6200_aux.h	2596;"	d
+PAD64_IE_SFT	include/ssv6200_aux.h	2598;"	d
+PAD64_IE_SZ	include/ssv6200_aux.h	2600;"	d
+PAD64_OD_HI	include/ssv6200_aux.h	2609;"	d
+PAD64_OD_I_MSK	include/ssv6200_aux.h	2607;"	d
+PAD64_OD_MSK	include/ssv6200_aux.h	2606;"	d
+PAD64_OD_SFT	include/ssv6200_aux.h	2608;"	d
+PAD64_OD_SZ	include/ssv6200_aux.h	2610;"	d
+PAD64_OE_HI	include/ssv6200_aux.h	2584;"	d
+PAD64_OE_I_MSK	include/ssv6200_aux.h	2582;"	d
+PAD64_OE_MSK	include/ssv6200_aux.h	2581;"	d
+PAD64_OE_SFT	include/ssv6200_aux.h	2583;"	d
+PAD64_OE_SZ	include/ssv6200_aux.h	2585;"	d
+PAD64_PE_HI	include/ssv6200_aux.h	2589;"	d
+PAD64_PE_I_MSK	include/ssv6200_aux.h	2587;"	d
+PAD64_PE_MSK	include/ssv6200_aux.h	2586;"	d
+PAD64_PE_SFT	include/ssv6200_aux.h	2588;"	d
+PAD64_PE_SZ	include/ssv6200_aux.h	2590;"	d
+PAD64_SEL_I_HI	include/ssv6200_aux.h	2604;"	d
+PAD64_SEL_I_I_MSK	include/ssv6200_aux.h	2602;"	d
+PAD64_SEL_I_MSK	include/ssv6200_aux.h	2601;"	d
+PAD64_SEL_I_SFT	include/ssv6200_aux.h	2603;"	d
+PAD64_SEL_I_SZ	include/ssv6200_aux.h	2605;"	d
+PAD64_SEL_OE_HI	include/ssv6200_aux.h	2619;"	d
+PAD64_SEL_OE_I_MSK	include/ssv6200_aux.h	2617;"	d
+PAD64_SEL_OE_MSK	include/ssv6200_aux.h	2616;"	d
+PAD64_SEL_OE_SFT	include/ssv6200_aux.h	2618;"	d
+PAD64_SEL_OE_SZ	include/ssv6200_aux.h	2620;"	d
+PAD64_SEL_O_HI	include/ssv6200_aux.h	2614;"	d
+PAD64_SEL_O_I_MSK	include/ssv6200_aux.h	2612;"	d
+PAD64_SEL_O_MSK	include/ssv6200_aux.h	2611;"	d
+PAD64_SEL_O_SFT	include/ssv6200_aux.h	2613;"	d
+PAD64_SEL_O_SZ	include/ssv6200_aux.h	2615;"	d
+PAD65_DS_HI	include/ssv6200_aux.h	2639;"	d
+PAD65_DS_I_MSK	include/ssv6200_aux.h	2637;"	d
+PAD65_DS_MSK	include/ssv6200_aux.h	2636;"	d
+PAD65_DS_SFT	include/ssv6200_aux.h	2638;"	d
+PAD65_DS_SZ	include/ssv6200_aux.h	2640;"	d
+PAD65_IE_HI	include/ssv6200_aux.h	2644;"	d
+PAD65_IE_I_MSK	include/ssv6200_aux.h	2642;"	d
+PAD65_IE_MSK	include/ssv6200_aux.h	2641;"	d
+PAD65_IE_SFT	include/ssv6200_aux.h	2643;"	d
+PAD65_IE_SZ	include/ssv6200_aux.h	2645;"	d
+PAD65_OD_HI	include/ssv6200_aux.h	2654;"	d
+PAD65_OD_I_MSK	include/ssv6200_aux.h	2652;"	d
+PAD65_OD_MSK	include/ssv6200_aux.h	2651;"	d
+PAD65_OD_SFT	include/ssv6200_aux.h	2653;"	d
+PAD65_OD_SZ	include/ssv6200_aux.h	2655;"	d
+PAD65_OE_HI	include/ssv6200_aux.h	2629;"	d
+PAD65_OE_I_MSK	include/ssv6200_aux.h	2627;"	d
+PAD65_OE_MSK	include/ssv6200_aux.h	2626;"	d
+PAD65_OE_SFT	include/ssv6200_aux.h	2628;"	d
+PAD65_OE_SZ	include/ssv6200_aux.h	2630;"	d
+PAD65_PE_HI	include/ssv6200_aux.h	2634;"	d
+PAD65_PE_I_MSK	include/ssv6200_aux.h	2632;"	d
+PAD65_PE_MSK	include/ssv6200_aux.h	2631;"	d
+PAD65_PE_SFT	include/ssv6200_aux.h	2633;"	d
+PAD65_PE_SZ	include/ssv6200_aux.h	2635;"	d
+PAD65_SEL_I_HI	include/ssv6200_aux.h	2649;"	d
+PAD65_SEL_I_I_MSK	include/ssv6200_aux.h	2647;"	d
+PAD65_SEL_I_MSK	include/ssv6200_aux.h	2646;"	d
+PAD65_SEL_I_SFT	include/ssv6200_aux.h	2648;"	d
+PAD65_SEL_I_SZ	include/ssv6200_aux.h	2650;"	d
+PAD65_SEL_O_HI	include/ssv6200_aux.h	2659;"	d
+PAD65_SEL_O_I_MSK	include/ssv6200_aux.h	2657;"	d
+PAD65_SEL_O_MSK	include/ssv6200_aux.h	2656;"	d
+PAD65_SEL_O_SFT	include/ssv6200_aux.h	2658;"	d
+PAD65_SEL_O_SZ	include/ssv6200_aux.h	2660;"	d
+PAD66_DS_HI	include/ssv6200_aux.h	2679;"	d
+PAD66_DS_I_MSK	include/ssv6200_aux.h	2677;"	d
+PAD66_DS_MSK	include/ssv6200_aux.h	2676;"	d
+PAD66_DS_SFT	include/ssv6200_aux.h	2678;"	d
+PAD66_DS_SZ	include/ssv6200_aux.h	2680;"	d
+PAD66_IE_HI	include/ssv6200_aux.h	2684;"	d
+PAD66_IE_I_MSK	include/ssv6200_aux.h	2682;"	d
+PAD66_IE_MSK	include/ssv6200_aux.h	2681;"	d
+PAD66_IE_SFT	include/ssv6200_aux.h	2683;"	d
+PAD66_IE_SZ	include/ssv6200_aux.h	2685;"	d
+PAD66_OD_HI	include/ssv6200_aux.h	2694;"	d
+PAD66_OD_I_MSK	include/ssv6200_aux.h	2692;"	d
+PAD66_OD_MSK	include/ssv6200_aux.h	2691;"	d
+PAD66_OD_SFT	include/ssv6200_aux.h	2693;"	d
+PAD66_OD_SZ	include/ssv6200_aux.h	2695;"	d
+PAD66_OE_HI	include/ssv6200_aux.h	2669;"	d
+PAD66_OE_I_MSK	include/ssv6200_aux.h	2667;"	d
+PAD66_OE_MSK	include/ssv6200_aux.h	2666;"	d
+PAD66_OE_SFT	include/ssv6200_aux.h	2668;"	d
+PAD66_OE_SZ	include/ssv6200_aux.h	2670;"	d
+PAD66_PE_HI	include/ssv6200_aux.h	2674;"	d
+PAD66_PE_I_MSK	include/ssv6200_aux.h	2672;"	d
+PAD66_PE_MSK	include/ssv6200_aux.h	2671;"	d
+PAD66_PE_SFT	include/ssv6200_aux.h	2673;"	d
+PAD66_PE_SZ	include/ssv6200_aux.h	2675;"	d
+PAD66_SEL_I_HI	include/ssv6200_aux.h	2689;"	d
+PAD66_SEL_I_I_MSK	include/ssv6200_aux.h	2687;"	d
+PAD66_SEL_I_MSK	include/ssv6200_aux.h	2686;"	d
+PAD66_SEL_I_SFT	include/ssv6200_aux.h	2688;"	d
+PAD66_SEL_I_SZ	include/ssv6200_aux.h	2690;"	d
+PAD66_SEL_O_HI	include/ssv6200_aux.h	2699;"	d
+PAD66_SEL_O_I_MSK	include/ssv6200_aux.h	2697;"	d
+PAD66_SEL_O_MSK	include/ssv6200_aux.h	2696;"	d
+PAD66_SEL_O_SFT	include/ssv6200_aux.h	2698;"	d
+PAD66_SEL_O_SZ	include/ssv6200_aux.h	2700;"	d
+PAD67_DS_HI	include/ssv6200_aux.h	2754;"	d
+PAD67_DS_I_MSK	include/ssv6200_aux.h	2752;"	d
+PAD67_DS_MSK	include/ssv6200_aux.h	2751;"	d
+PAD67_DS_SFT	include/ssv6200_aux.h	2753;"	d
+PAD67_DS_SZ	include/ssv6200_aux.h	2755;"	d
+PAD67_IE_HI	include/ssv6200_aux.h	2759;"	d
+PAD67_IE_I_MSK	include/ssv6200_aux.h	2757;"	d
+PAD67_IE_MSK	include/ssv6200_aux.h	2756;"	d
+PAD67_IE_SFT	include/ssv6200_aux.h	2758;"	d
+PAD67_IE_SZ	include/ssv6200_aux.h	2760;"	d
+PAD67_OD_HI	include/ssv6200_aux.h	2769;"	d
+PAD67_OD_I_MSK	include/ssv6200_aux.h	2767;"	d
+PAD67_OD_MSK	include/ssv6200_aux.h	2766;"	d
+PAD67_OD_SFT	include/ssv6200_aux.h	2768;"	d
+PAD67_OD_SZ	include/ssv6200_aux.h	2770;"	d
+PAD67_OE_HI	include/ssv6200_aux.h	2744;"	d
+PAD67_OE_I_MSK	include/ssv6200_aux.h	2742;"	d
+PAD67_OE_MSK	include/ssv6200_aux.h	2741;"	d
+PAD67_OE_SFT	include/ssv6200_aux.h	2743;"	d
+PAD67_OE_SZ	include/ssv6200_aux.h	2745;"	d
+PAD67_PE_HI	include/ssv6200_aux.h	2749;"	d
+PAD67_PE_I_MSK	include/ssv6200_aux.h	2747;"	d
+PAD67_PE_MSK	include/ssv6200_aux.h	2746;"	d
+PAD67_PE_SFT	include/ssv6200_aux.h	2748;"	d
+PAD67_PE_SZ	include/ssv6200_aux.h	2750;"	d
+PAD67_SEL_I_HI	include/ssv6200_aux.h	2764;"	d
+PAD67_SEL_I_I_MSK	include/ssv6200_aux.h	2762;"	d
+PAD67_SEL_I_MSK	include/ssv6200_aux.h	2761;"	d
+PAD67_SEL_I_SFT	include/ssv6200_aux.h	2763;"	d
+PAD67_SEL_I_SZ	include/ssv6200_aux.h	2765;"	d
+PAD67_SEL_O_HI	include/ssv6200_aux.h	2774;"	d
+PAD67_SEL_O_I_MSK	include/ssv6200_aux.h	2772;"	d
+PAD67_SEL_O_MSK	include/ssv6200_aux.h	2771;"	d
+PAD67_SEL_O_SFT	include/ssv6200_aux.h	2773;"	d
+PAD67_SEL_O_SZ	include/ssv6200_aux.h	2775;"	d
+PAD68_DS_HI	include/ssv6200_aux.h	2719;"	d
+PAD68_DS_I_MSK	include/ssv6200_aux.h	2717;"	d
+PAD68_DS_MSK	include/ssv6200_aux.h	2716;"	d
+PAD68_DS_SFT	include/ssv6200_aux.h	2718;"	d
+PAD68_DS_SZ	include/ssv6200_aux.h	2720;"	d
+PAD68_IE_HI	include/ssv6200_aux.h	2724;"	d
+PAD68_IE_I_MSK	include/ssv6200_aux.h	2722;"	d
+PAD68_IE_MSK	include/ssv6200_aux.h	2721;"	d
+PAD68_IE_SFT	include/ssv6200_aux.h	2723;"	d
+PAD68_IE_SZ	include/ssv6200_aux.h	2725;"	d
+PAD68_OD_HI	include/ssv6200_aux.h	2729;"	d
+PAD68_OD_I_MSK	include/ssv6200_aux.h	2727;"	d
+PAD68_OD_MSK	include/ssv6200_aux.h	2726;"	d
+PAD68_OD_SFT	include/ssv6200_aux.h	2728;"	d
+PAD68_OD_SZ	include/ssv6200_aux.h	2730;"	d
+PAD68_OE_HI	include/ssv6200_aux.h	2709;"	d
+PAD68_OE_I_MSK	include/ssv6200_aux.h	2707;"	d
+PAD68_OE_MSK	include/ssv6200_aux.h	2706;"	d
+PAD68_OE_SFT	include/ssv6200_aux.h	2708;"	d
+PAD68_OE_SZ	include/ssv6200_aux.h	2710;"	d
+PAD68_PE_HI	include/ssv6200_aux.h	2714;"	d
+PAD68_PE_I_MSK	include/ssv6200_aux.h	2712;"	d
+PAD68_PE_MSK	include/ssv6200_aux.h	2711;"	d
+PAD68_PE_SFT	include/ssv6200_aux.h	2713;"	d
+PAD68_PE_SZ	include/ssv6200_aux.h	2715;"	d
+PAD68_SEL_O_HI	include/ssv6200_aux.h	2734;"	d
+PAD68_SEL_O_I_MSK	include/ssv6200_aux.h	2732;"	d
+PAD68_SEL_O_MSK	include/ssv6200_aux.h	2731;"	d
+PAD68_SEL_O_SFT	include/ssv6200_aux.h	2733;"	d
+PAD68_SEL_O_SZ	include/ssv6200_aux.h	2735;"	d
+PAD69_DS_HI	include/ssv6200_aux.h	2794;"	d
+PAD69_DS_I_MSK	include/ssv6200_aux.h	2792;"	d
+PAD69_DS_MSK	include/ssv6200_aux.h	2791;"	d
+PAD69_DS_SFT	include/ssv6200_aux.h	2793;"	d
+PAD69_DS_SZ	include/ssv6200_aux.h	2795;"	d
+PAD69_IE_HI	include/ssv6200_aux.h	2799;"	d
+PAD69_IE_I_MSK	include/ssv6200_aux.h	2797;"	d
+PAD69_IE_MSK	include/ssv6200_aux.h	2796;"	d
+PAD69_IE_SFT	include/ssv6200_aux.h	2798;"	d
+PAD69_IE_SZ	include/ssv6200_aux.h	2800;"	d
+PAD69_OD_HI	include/ssv6200_aux.h	2809;"	d
+PAD69_OD_I_MSK	include/ssv6200_aux.h	2807;"	d
+PAD69_OD_MSK	include/ssv6200_aux.h	2806;"	d
+PAD69_OD_SFT	include/ssv6200_aux.h	2808;"	d
+PAD69_OD_SZ	include/ssv6200_aux.h	2810;"	d
+PAD69_OE_HI	include/ssv6200_aux.h	2784;"	d
+PAD69_OE_I_MSK	include/ssv6200_aux.h	2782;"	d
+PAD69_OE_MSK	include/ssv6200_aux.h	2781;"	d
+PAD69_OE_SFT	include/ssv6200_aux.h	2783;"	d
+PAD69_OE_SZ	include/ssv6200_aux.h	2785;"	d
+PAD69_PE_HI	include/ssv6200_aux.h	2789;"	d
+PAD69_PE_I_MSK	include/ssv6200_aux.h	2787;"	d
+PAD69_PE_MSK	include/ssv6200_aux.h	2786;"	d
+PAD69_PE_SFT	include/ssv6200_aux.h	2788;"	d
+PAD69_PE_SZ	include/ssv6200_aux.h	2790;"	d
+PAD69_SEL_I_HI	include/ssv6200_aux.h	2804;"	d
+PAD69_SEL_I_I_MSK	include/ssv6200_aux.h	2802;"	d
+PAD69_SEL_I_MSK	include/ssv6200_aux.h	2801;"	d
+PAD69_SEL_I_SFT	include/ssv6200_aux.h	2803;"	d
+PAD69_SEL_I_SZ	include/ssv6200_aux.h	2805;"	d
+PAD69_SEL_O_HI	include/ssv6200_aux.h	2814;"	d
+PAD69_SEL_O_I_MSK	include/ssv6200_aux.h	2812;"	d
+PAD69_SEL_O_MSK	include/ssv6200_aux.h	2811;"	d
+PAD69_SEL_O_SFT	include/ssv6200_aux.h	2813;"	d
+PAD69_SEL_O_SZ	include/ssv6200_aux.h	2815;"	d
+PAD6_IE_HI	include/ssv6200_aux.h	869;"	d
+PAD6_IE_I_MSK	include/ssv6200_aux.h	867;"	d
+PAD6_IE_MSK	include/ssv6200_aux.h	866;"	d
+PAD6_IE_SFT	include/ssv6200_aux.h	868;"	d
+PAD6_IE_SZ	include/ssv6200_aux.h	870;"	d
+PAD6_OD_HI	include/ssv6200_aux.h	879;"	d
+PAD6_OD_I_MSK	include/ssv6200_aux.h	877;"	d
+PAD6_OD_MSK	include/ssv6200_aux.h	876;"	d
+PAD6_OD_SFT	include/ssv6200_aux.h	878;"	d
+PAD6_OD_SZ	include/ssv6200_aux.h	880;"	d
+PAD6_SEL_I_HI	include/ssv6200_aux.h	874;"	d
+PAD6_SEL_I_I_MSK	include/ssv6200_aux.h	872;"	d
+PAD6_SEL_I_MSK	include/ssv6200_aux.h	871;"	d
+PAD6_SEL_I_SFT	include/ssv6200_aux.h	873;"	d
+PAD6_SEL_I_SZ	include/ssv6200_aux.h	875;"	d
+PAD6_SEL_O_HI	include/ssv6200_aux.h	884;"	d
+PAD6_SEL_O_I_MSK	include/ssv6200_aux.h	882;"	d
+PAD6_SEL_O_MSK	include/ssv6200_aux.h	881;"	d
+PAD6_SEL_O_SFT	include/ssv6200_aux.h	883;"	d
+PAD6_SEL_O_SZ	include/ssv6200_aux.h	885;"	d
+PAD70_DS_HI	include/ssv6200_aux.h	2839;"	d
+PAD70_DS_I_MSK	include/ssv6200_aux.h	2837;"	d
+PAD70_DS_MSK	include/ssv6200_aux.h	2836;"	d
+PAD70_DS_SFT	include/ssv6200_aux.h	2838;"	d
+PAD70_DS_SZ	include/ssv6200_aux.h	2840;"	d
+PAD70_IE_HI	include/ssv6200_aux.h	2844;"	d
+PAD70_IE_I_MSK	include/ssv6200_aux.h	2842;"	d
+PAD70_IE_MSK	include/ssv6200_aux.h	2841;"	d
+PAD70_IE_SFT	include/ssv6200_aux.h	2843;"	d
+PAD70_IE_SZ	include/ssv6200_aux.h	2845;"	d
+PAD70_OD_HI	include/ssv6200_aux.h	2854;"	d
+PAD70_OD_I_MSK	include/ssv6200_aux.h	2852;"	d
+PAD70_OD_MSK	include/ssv6200_aux.h	2851;"	d
+PAD70_OD_SFT	include/ssv6200_aux.h	2853;"	d
+PAD70_OD_SZ	include/ssv6200_aux.h	2855;"	d
+PAD70_OE_HI	include/ssv6200_aux.h	2829;"	d
+PAD70_OE_I_MSK	include/ssv6200_aux.h	2827;"	d
+PAD70_OE_MSK	include/ssv6200_aux.h	2826;"	d
+PAD70_OE_SFT	include/ssv6200_aux.h	2828;"	d
+PAD70_OE_SZ	include/ssv6200_aux.h	2830;"	d
+PAD70_PE_HI	include/ssv6200_aux.h	2834;"	d
+PAD70_PE_I_MSK	include/ssv6200_aux.h	2832;"	d
+PAD70_PE_MSK	include/ssv6200_aux.h	2831;"	d
+PAD70_PE_SFT	include/ssv6200_aux.h	2833;"	d
+PAD70_PE_SZ	include/ssv6200_aux.h	2835;"	d
+PAD70_SEL_I_HI	include/ssv6200_aux.h	2849;"	d
+PAD70_SEL_I_I_MSK	include/ssv6200_aux.h	2847;"	d
+PAD70_SEL_I_MSK	include/ssv6200_aux.h	2846;"	d
+PAD70_SEL_I_SFT	include/ssv6200_aux.h	2848;"	d
+PAD70_SEL_I_SZ	include/ssv6200_aux.h	2850;"	d
+PAD70_SEL_O_HI	include/ssv6200_aux.h	2859;"	d
+PAD70_SEL_O_I_MSK	include/ssv6200_aux.h	2857;"	d
+PAD70_SEL_O_MSK	include/ssv6200_aux.h	2856;"	d
+PAD70_SEL_O_SFT	include/ssv6200_aux.h	2858;"	d
+PAD70_SEL_O_SZ	include/ssv6200_aux.h	2860;"	d
+PAD7_IE_HI	include/ssv6200_aux.h	904;"	d
+PAD7_IE_I_MSK	include/ssv6200_aux.h	902;"	d
+PAD7_IE_MSK	include/ssv6200_aux.h	901;"	d
+PAD7_IE_SFT	include/ssv6200_aux.h	903;"	d
+PAD7_IE_SZ	include/ssv6200_aux.h	905;"	d
+PAD7_OD_HI	include/ssv6200_aux.h	914;"	d
+PAD7_OD_I_MSK	include/ssv6200_aux.h	912;"	d
+PAD7_OD_MSK	include/ssv6200_aux.h	911;"	d
+PAD7_OD_SFT	include/ssv6200_aux.h	913;"	d
+PAD7_OD_SZ	include/ssv6200_aux.h	915;"	d
+PAD7_SEL_I_HI	include/ssv6200_aux.h	909;"	d
+PAD7_SEL_I_I_MSK	include/ssv6200_aux.h	907;"	d
+PAD7_SEL_I_MSK	include/ssv6200_aux.h	906;"	d
+PAD7_SEL_I_SFT	include/ssv6200_aux.h	908;"	d
+PAD7_SEL_I_SZ	include/ssv6200_aux.h	910;"	d
+PAD7_SEL_O_HI	include/ssv6200_aux.h	919;"	d
+PAD7_SEL_O_I_MSK	include/ssv6200_aux.h	917;"	d
+PAD7_SEL_O_MSK	include/ssv6200_aux.h	916;"	d
+PAD7_SEL_O_SFT	include/ssv6200_aux.h	918;"	d
+PAD7_SEL_O_SZ	include/ssv6200_aux.h	920;"	d
+PAD8_IE_HI	include/ssv6200_aux.h	939;"	d
+PAD8_IE_I_MSK	include/ssv6200_aux.h	937;"	d
+PAD8_IE_MSK	include/ssv6200_aux.h	936;"	d
+PAD8_IE_SFT	include/ssv6200_aux.h	938;"	d
+PAD8_IE_SZ	include/ssv6200_aux.h	940;"	d
+PAD8_OD_HI	include/ssv6200_aux.h	949;"	d
+PAD8_OD_I_MSK	include/ssv6200_aux.h	947;"	d
+PAD8_OD_MSK	include/ssv6200_aux.h	946;"	d
+PAD8_OD_SFT	include/ssv6200_aux.h	948;"	d
+PAD8_OD_SZ	include/ssv6200_aux.h	950;"	d
+PAD8_SEL_I_HI	include/ssv6200_aux.h	944;"	d
+PAD8_SEL_I_I_MSK	include/ssv6200_aux.h	942;"	d
+PAD8_SEL_I_MSK	include/ssv6200_aux.h	941;"	d
+PAD8_SEL_I_SFT	include/ssv6200_aux.h	943;"	d
+PAD8_SEL_I_SZ	include/ssv6200_aux.h	945;"	d
+PAD9_IE_HI	include/ssv6200_aux.h	969;"	d
+PAD9_IE_I_MSK	include/ssv6200_aux.h	967;"	d
+PAD9_IE_MSK	include/ssv6200_aux.h	966;"	d
+PAD9_IE_SFT	include/ssv6200_aux.h	968;"	d
+PAD9_IE_SZ	include/ssv6200_aux.h	970;"	d
+PAD9_OD_HI	include/ssv6200_aux.h	979;"	d
+PAD9_OD_I_MSK	include/ssv6200_aux.h	977;"	d
+PAD9_OD_MSK	include/ssv6200_aux.h	976;"	d
+PAD9_OD_SFT	include/ssv6200_aux.h	978;"	d
+PAD9_OD_SZ	include/ssv6200_aux.h	980;"	d
+PAD9_SEL_I_HI	include/ssv6200_aux.h	974;"	d
+PAD9_SEL_I_I_MSK	include/ssv6200_aux.h	972;"	d
+PAD9_SEL_I_MSK	include/ssv6200_aux.h	971;"	d
+PAD9_SEL_I_SFT	include/ssv6200_aux.h	973;"	d
+PAD9_SEL_I_SZ	include/ssv6200_aux.h	975;"	d
+PAD9_SEL_O_HI	include/ssv6200_aux.h	984;"	d
+PAD9_SEL_O_I_MSK	include/ssv6200_aux.h	982;"	d
+PAD9_SEL_O_MSK	include/ssv6200_aux.h	981;"	d
+PAD9_SEL_O_SFT	include/ssv6200_aux.h	983;"	d
+PAD9_SEL_O_SZ	include/ssv6200_aux.h	985;"	d
+PADPDBAND	smac/dev.h	567;"	d
+PADPDBAND	smac/hal/ssv6006c/turismo_common.h	174;"	d
+PAIR_SCRT_HI	include/ssv6200_aux.h	9199;"	d
+PAIR_SCRT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8959;"	d
+PAIR_SCRT_I_MSK	include/ssv6200_aux.h	9197;"	d
+PAIR_SCRT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8957;"	d
+PAIR_SCRT_MSK	include/ssv6200_aux.h	9196;"	d
+PAIR_SCRT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8956;"	d
+PAIR_SCRT_SFT	include/ssv6200_aux.h	9198;"	d
+PAIR_SCRT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8958;"	d
+PAIR_SCRT_SZ	include/ssv6200_aux.h	9200;"	d
+PAIR_SCRT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8960;"	d
+PAPDP_GAIN_SETTING	smac/hal/ssv6006c/turismoC_wifi_phy_reg.c	94;"	d	file:
+PAPDP_GAIN_SETTING	smac/hal/ssv6006c/turismo_common.h	215;"	d
+PAPDP_GAIN_SETTING_2G	smac/hal/ssv6006c/turismoC_wifi_phy_reg.c	96;"	d	file:
+PAPDP_GAIN_SETTING_2G	smac/hal/ssv6006c/turismo_common.h	217;"	d
+PAPDP_GAIN_SETTING_F2	smac/hal/ssv6006c/turismoC_wifi_phy_reg.c	95;"	d	file:
+PAPDP_GAIN_SETTING_F2	smac/hal/ssv6006c/turismo_common.h	216;"	d
+PARALLEL_DR_HI	include/ssv6200_aux.h	369;"	d
+PARALLEL_DR_I_MSK	include/ssv6200_aux.h	367;"	d
+PARALLEL_DR_MSK	include/ssv6200_aux.h	366;"	d
+PARALLEL_DR_SFT	include/ssv6200_aux.h	368;"	d
+PARALLEL_DR_SZ	include/ssv6200_aux.h	370;"	d
+PARA_ALC_RLS_HI	include/ssv6200_aux.h	17869;"	d
+PARA_ALC_RLS_I_MSK	include/ssv6200_aux.h	17867;"	d
+PARA_ALC_RLS_MSK	include/ssv6200_aux.h	17866;"	d
+PARA_ALC_RLS_SFT	include/ssv6200_aux.h	17868;"	d
+PARA_ALC_RLS_SZ	include/ssv6200_aux.h	17870;"	d
+PARITY_EN_HI	include/ssv6200_aux.h	4339;"	d
+PARITY_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3444;"	d
+PARITY_EN_I_MSK	include/ssv6200_aux.h	4337;"	d
+PARITY_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3442;"	d
+PARITY_EN_MSK	include/ssv6200_aux.h	4336;"	d
+PARITY_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3441;"	d
+PARITY_EN_SFT	include/ssv6200_aux.h	4338;"	d
+PARITY_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3443;"	d
+PARITY_EN_SZ	include/ssv6200_aux.h	4340;"	d
+PARITY_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3445;"	d
+PARITY_ERR_HI	include/ssv6200_aux.h	4399;"	d
+PARITY_ERR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3509;"	d
+PARITY_ERR_I_MSK	include/ssv6200_aux.h	4397;"	d
+PARITY_ERR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3507;"	d
+PARITY_ERR_MSK	include/ssv6200_aux.h	4396;"	d
+PARITY_ERR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3506;"	d
+PARITY_ERR_SFT	include/ssv6200_aux.h	4398;"	d
+PARITY_ERR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3508;"	d
+PARITY_ERR_SZ	include/ssv6200_aux.h	4400;"	d
+PARITY_ERR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3510;"	d
+PARITY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3664;"	d
+PARITY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3662;"	d
+PARITY_MACRO	smac/wapi_sms4.c	92;"	d	file:
+PARITY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3661;"	d
+PARITY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3663;"	d
+PARITY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3665;"	d
+PATCH00_ADDR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1799;"	d
+PATCH00_ADDR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1797;"	d
+PATCH00_ADDR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1796;"	d
+PATCH00_ADDR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1798;"	d
+PATCH00_ADDR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1800;"	d
+PATCH00_DATA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1804;"	d
+PATCH00_DATA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1802;"	d
+PATCH00_DATA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1801;"	d
+PATCH00_DATA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1803;"	d
+PATCH00_DATA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1805;"	d
+PATCH00_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1794;"	d
+PATCH00_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1792;"	d
+PATCH00_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1791;"	d
+PATCH00_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1793;"	d
+PATCH00_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1795;"	d
+PATCH01_ADDR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1814;"	d
+PATCH01_ADDR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1812;"	d
+PATCH01_ADDR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1811;"	d
+PATCH01_ADDR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1813;"	d
+PATCH01_ADDR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1815;"	d
+PATCH01_DATA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1819;"	d
+PATCH01_DATA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1817;"	d
+PATCH01_DATA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1816;"	d
+PATCH01_DATA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1818;"	d
+PATCH01_DATA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1820;"	d
+PATCH01_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1809;"	d
+PATCH01_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1807;"	d
+PATCH01_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1806;"	d
+PATCH01_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1808;"	d
+PATCH01_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1810;"	d
+PATCH02_ADDR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4889;"	d
+PATCH02_ADDR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4887;"	d
+PATCH02_ADDR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4886;"	d
+PATCH02_ADDR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4888;"	d
+PATCH02_ADDR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4890;"	d
+PATCH02_DATA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4894;"	d
+PATCH02_DATA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4892;"	d
+PATCH02_DATA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4891;"	d
+PATCH02_DATA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4893;"	d
+PATCH02_DATA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4895;"	d
+PATCH02_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4884;"	d
+PATCH02_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4882;"	d
+PATCH02_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4881;"	d
+PATCH02_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4883;"	d
+PATCH02_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4885;"	d
+PATCH03_ADDR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4904;"	d
+PATCH03_ADDR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4902;"	d
+PATCH03_ADDR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4901;"	d
+PATCH03_ADDR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4903;"	d
+PATCH03_ADDR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4905;"	d
+PATCH03_DATA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4909;"	d
+PATCH03_DATA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4907;"	d
+PATCH03_DATA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4906;"	d
+PATCH03_DATA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4908;"	d
+PATCH03_DATA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4910;"	d
+PATCH03_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4899;"	d
+PATCH03_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4897;"	d
+PATCH03_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4896;"	d
+PATCH03_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4898;"	d
+PATCH03_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4900;"	d
+PATCH04_ADDR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4919;"	d
+PATCH04_ADDR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4917;"	d
+PATCH04_ADDR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4916;"	d
+PATCH04_ADDR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4918;"	d
+PATCH04_ADDR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4920;"	d
+PATCH04_DATA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4924;"	d
+PATCH04_DATA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4922;"	d
+PATCH04_DATA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4921;"	d
+PATCH04_DATA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4923;"	d
+PATCH04_DATA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4925;"	d
+PATCH04_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4914;"	d
+PATCH04_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4912;"	d
+PATCH04_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4911;"	d
+PATCH04_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4913;"	d
+PATCH04_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4915;"	d
+PATCH05_ADDR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4934;"	d
+PATCH05_ADDR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4932;"	d
+PATCH05_ADDR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4931;"	d
+PATCH05_ADDR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4933;"	d
+PATCH05_ADDR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4935;"	d
+PATCH05_DATA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4939;"	d
+PATCH05_DATA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4937;"	d
+PATCH05_DATA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4936;"	d
+PATCH05_DATA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4938;"	d
+PATCH05_DATA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4940;"	d
+PATCH05_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4929;"	d
+PATCH05_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4927;"	d
+PATCH05_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4926;"	d
+PATCH05_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4928;"	d
+PATCH05_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4930;"	d
+PATCH06_ADDR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4949;"	d
+PATCH06_ADDR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4947;"	d
+PATCH06_ADDR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4946;"	d
+PATCH06_ADDR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4948;"	d
+PATCH06_ADDR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4950;"	d
+PATCH06_DATA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4954;"	d
+PATCH06_DATA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4952;"	d
+PATCH06_DATA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4951;"	d
+PATCH06_DATA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4953;"	d
+PATCH06_DATA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4955;"	d
+PATCH06_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4944;"	d
+PATCH06_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4942;"	d
+PATCH06_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4941;"	d
+PATCH06_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4943;"	d
+PATCH06_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4945;"	d
+PATCH07_ADDR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4964;"	d
+PATCH07_ADDR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4962;"	d
+PATCH07_ADDR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4961;"	d
+PATCH07_ADDR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4963;"	d
+PATCH07_ADDR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4965;"	d
+PATCH07_DATA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4969;"	d
+PATCH07_DATA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4967;"	d
+PATCH07_DATA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4966;"	d
+PATCH07_DATA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4968;"	d
+PATCH07_DATA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4970;"	d
+PATCH07_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4959;"	d
+PATCH07_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4957;"	d
+PATCH07_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4956;"	d
+PATCH07_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4958;"	d
+PATCH07_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4960;"	d
+PATCH08_ADDR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4979;"	d
+PATCH08_ADDR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4977;"	d
+PATCH08_ADDR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4976;"	d
+PATCH08_ADDR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4978;"	d
+PATCH08_ADDR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4980;"	d
+PATCH08_DATA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4984;"	d
+PATCH08_DATA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4982;"	d
+PATCH08_DATA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4981;"	d
+PATCH08_DATA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4983;"	d
+PATCH08_DATA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4985;"	d
+PATCH08_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4974;"	d
+PATCH08_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4972;"	d
+PATCH08_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4971;"	d
+PATCH08_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4973;"	d
+PATCH08_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4975;"	d
+PATCH09_ADDR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4994;"	d
+PATCH09_ADDR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4992;"	d
+PATCH09_ADDR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4991;"	d
+PATCH09_ADDR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4993;"	d
+PATCH09_ADDR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4995;"	d
+PATCH09_DATA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4999;"	d
+PATCH09_DATA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4997;"	d
+PATCH09_DATA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4996;"	d
+PATCH09_DATA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4998;"	d
+PATCH09_DATA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5000;"	d
+PATCH09_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4989;"	d
+PATCH09_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4987;"	d
+PATCH09_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4986;"	d
+PATCH09_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4988;"	d
+PATCH09_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4990;"	d
+PATCH10_ADDR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5009;"	d
+PATCH10_ADDR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5007;"	d
+PATCH10_ADDR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5006;"	d
+PATCH10_ADDR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5008;"	d
+PATCH10_ADDR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5010;"	d
+PATCH10_DATA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5014;"	d
+PATCH10_DATA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5012;"	d
+PATCH10_DATA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5011;"	d
+PATCH10_DATA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5013;"	d
+PATCH10_DATA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5015;"	d
+PATCH10_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5004;"	d
+PATCH10_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5002;"	d
+PATCH10_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5001;"	d
+PATCH10_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5003;"	d
+PATCH10_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5005;"	d
+PATCH11_ADDR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5024;"	d
+PATCH11_ADDR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5022;"	d
+PATCH11_ADDR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5021;"	d
+PATCH11_ADDR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5023;"	d
+PATCH11_ADDR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5025;"	d
+PATCH11_DATA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5029;"	d
+PATCH11_DATA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5027;"	d
+PATCH11_DATA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5026;"	d
+PATCH11_DATA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5028;"	d
+PATCH11_DATA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5030;"	d
+PATCH11_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5019;"	d
+PATCH11_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5017;"	d
+PATCH11_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5016;"	d
+PATCH11_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5018;"	d
+PATCH11_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5020;"	d
+PATCH12_ADDR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5039;"	d
+PATCH12_ADDR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5037;"	d
+PATCH12_ADDR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5036;"	d
+PATCH12_ADDR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5038;"	d
+PATCH12_ADDR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5040;"	d
+PATCH12_DATA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5044;"	d
+PATCH12_DATA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5042;"	d
+PATCH12_DATA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5041;"	d
+PATCH12_DATA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5043;"	d
+PATCH12_DATA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5045;"	d
+PATCH12_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5034;"	d
+PATCH12_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5032;"	d
+PATCH12_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5031;"	d
+PATCH12_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5033;"	d
+PATCH12_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5035;"	d
+PATCH13_ADDR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5054;"	d
+PATCH13_ADDR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5052;"	d
+PATCH13_ADDR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5051;"	d
+PATCH13_ADDR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5053;"	d
+PATCH13_ADDR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5055;"	d
+PATCH13_DATA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5059;"	d
+PATCH13_DATA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5057;"	d
+PATCH13_DATA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5056;"	d
+PATCH13_DATA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5058;"	d
+PATCH13_DATA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5060;"	d
+PATCH13_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5049;"	d
+PATCH13_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5047;"	d
+PATCH13_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5046;"	d
+PATCH13_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5048;"	d
+PATCH13_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5050;"	d
+PATCH14_ADDR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5069;"	d
+PATCH14_ADDR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5067;"	d
+PATCH14_ADDR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5066;"	d
+PATCH14_ADDR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5068;"	d
+PATCH14_ADDR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5070;"	d
+PATCH14_DATA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5074;"	d
+PATCH14_DATA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5072;"	d
+PATCH14_DATA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5071;"	d
+PATCH14_DATA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5073;"	d
+PATCH14_DATA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5075;"	d
+PATCH14_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5064;"	d
+PATCH14_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5062;"	d
+PATCH14_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5061;"	d
+PATCH14_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5063;"	d
+PATCH14_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5065;"	d
+PATCH15_ADDR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5084;"	d
+PATCH15_ADDR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5082;"	d
+PATCH15_ADDR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5081;"	d
+PATCH15_ADDR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5083;"	d
+PATCH15_ADDR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5085;"	d
+PATCH15_DATA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5089;"	d
+PATCH15_DATA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5087;"	d
+PATCH15_DATA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5086;"	d
+PATCH15_DATA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5088;"	d
+PATCH15_DATA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5090;"	d
+PATCH15_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5079;"	d
+PATCH15_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5077;"	d
+PATCH15_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5076;"	d
+PATCH15_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5078;"	d
+PATCH15_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5080;"	d
+PBUF_ADDR_SHIFT	smac/ap.c	42;"	d	file:
+PBUF_ADDR_SHIFT	smac/hal/ssv6006c/ssv6006_mac.h	30;"	d
+PBUF_BASE_ADDR	smac/ap.c	41;"	d	file:
+PBUF_BASE_ADDR	smac/hal/ssv6006c/ssv6006_mac.h	29;"	d
+PBUF_MapIDtoPkt	smac/ap.c	44;"	d	file:
+PBUF_MapIDtoPkt	smac/hal/ssv6006c/ssv6006_mac.h	32;"	d
+PBUF_MapPkttoID	smac/ap.c	43;"	d	file:
+PBUF_MapPkttoID	smac/hal/ssv6006c/ssv6006_mac.h	31;"	d
+PBUS_SWP_HI	include/ssv6200_aux.h	5729;"	d
+PBUS_SWP_I_MSK	include/ssv6200_aux.h	5727;"	d
+PBUS_SWP_MSK	include/ssv6200_aux.h	5726;"	d
+PBUS_SWP_SFT	include/ssv6200_aux.h	5728;"	d
+PBUS_SWP_SZ	include/ssv6200_aux.h	5730;"	d
+PB_OFFSET_HI	include/ssv6200_aux.h	9139;"	d
+PB_OFFSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8894;"	d
+PB_OFFSET_I_MSK	include/ssv6200_aux.h	9137;"	d
+PB_OFFSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8892;"	d
+PB_OFFSET_MSK	include/ssv6200_aux.h	9136;"	d
+PB_OFFSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8891;"	d
+PB_OFFSET_SFT	include/ssv6200_aux.h	9138;"	d
+PB_OFFSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8893;"	d
+PB_OFFSET_SZ	include/ssv6200_aux.h	9140;"	d
+PB_OFFSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8895;"	d
+PBuf_Type_E	include/ssv6xxx_common.h	/^} PBuf_Type_E;$/;"	t	typeref:enum:__PBuf_Type_E
+PDE_DATA	ssvdevice/ssvdevice.c	73;"	d	file:
+PEERPS_REJECT_ENABLE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5519;"	d
+PEERPS_REJECT_ENABLE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5517;"	d
+PEERPS_REJECT_ENABLE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5516;"	d
+PEERPS_REJECT_ENABLE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5518;"	d
+PEERPS_REJECT_ENABLE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5520;"	d
+PEER_HT_MODE0_HI	include/ssv6200_aux.h	8309;"	d
+PEER_HT_MODE0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8299;"	d
+PEER_HT_MODE0_I_MSK	include/ssv6200_aux.h	8307;"	d
+PEER_HT_MODE0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8297;"	d
+PEER_HT_MODE0_MSK	include/ssv6200_aux.h	8306;"	d
+PEER_HT_MODE0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8296;"	d
+PEER_HT_MODE0_SFT	include/ssv6200_aux.h	8308;"	d
+PEER_HT_MODE0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8298;"	d
+PEER_HT_MODE0_SZ	include/ssv6200_aux.h	8310;"	d
+PEER_HT_MODE0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8300;"	d
+PEER_HT_MODE1_HI	include/ssv6200_aux.h	8419;"	d
+PEER_HT_MODE1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8409;"	d
+PEER_HT_MODE1_I_MSK	include/ssv6200_aux.h	8417;"	d
+PEER_HT_MODE1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8407;"	d
+PEER_HT_MODE1_MSK	include/ssv6200_aux.h	8416;"	d
+PEER_HT_MODE1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8406;"	d
+PEER_HT_MODE1_SFT	include/ssv6200_aux.h	8418;"	d
+PEER_HT_MODE1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8408;"	d
+PEER_HT_MODE1_SZ	include/ssv6200_aux.h	8420;"	d
+PEER_HT_MODE1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8410;"	d
+PEER_HT_MODE2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9574;"	d
+PEER_HT_MODE2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9572;"	d
+PEER_HT_MODE2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9571;"	d
+PEER_HT_MODE2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9573;"	d
+PEER_HT_MODE2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9575;"	d
+PEER_HT_MODE3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9684;"	d
+PEER_HT_MODE3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9682;"	d
+PEER_HT_MODE3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9681;"	d
+PEER_HT_MODE3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9683;"	d
+PEER_HT_MODE3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9685;"	d
+PEER_HT_MODE4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9794;"	d
+PEER_HT_MODE4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9792;"	d
+PEER_HT_MODE4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9791;"	d
+PEER_HT_MODE4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9793;"	d
+PEER_HT_MODE4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9795;"	d
+PEER_HT_MODE5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9904;"	d
+PEER_HT_MODE5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9902;"	d
+PEER_HT_MODE5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9901;"	d
+PEER_HT_MODE5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9903;"	d
+PEER_HT_MODE5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9905;"	d
+PEER_HT_MODE6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10014;"	d
+PEER_HT_MODE6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10012;"	d
+PEER_HT_MODE6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10011;"	d
+PEER_HT_MODE6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10013;"	d
+PEER_HT_MODE6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10015;"	d
+PEER_HT_MODE7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10124;"	d
+PEER_HT_MODE7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10122;"	d
+PEER_HT_MODE7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10121;"	d
+PEER_HT_MODE7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10123;"	d
+PEER_HT_MODE7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10125;"	d
+PEER_MAC0_31_0_HI	include/ssv6200_aux.h	8314;"	d
+PEER_MAC0_31_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8304;"	d
+PEER_MAC0_31_0_I_MSK	include/ssv6200_aux.h	8312;"	d
+PEER_MAC0_31_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8302;"	d
+PEER_MAC0_31_0_MSK	include/ssv6200_aux.h	8311;"	d
+PEER_MAC0_31_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8301;"	d
+PEER_MAC0_31_0_SFT	include/ssv6200_aux.h	8313;"	d
+PEER_MAC0_31_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8303;"	d
+PEER_MAC0_31_0_SZ	include/ssv6200_aux.h	8315;"	d
+PEER_MAC0_31_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8305;"	d
+PEER_MAC0_47_32_HI	include/ssv6200_aux.h	8319;"	d
+PEER_MAC0_47_32_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8309;"	d
+PEER_MAC0_47_32_I_MSK	include/ssv6200_aux.h	8317;"	d
+PEER_MAC0_47_32_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8307;"	d
+PEER_MAC0_47_32_MSK	include/ssv6200_aux.h	8316;"	d
+PEER_MAC0_47_32_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8306;"	d
+PEER_MAC0_47_32_SFT	include/ssv6200_aux.h	8318;"	d
+PEER_MAC0_47_32_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8308;"	d
+PEER_MAC0_47_32_SZ	include/ssv6200_aux.h	8320;"	d
+PEER_MAC0_47_32_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8310;"	d
+PEER_MAC1_31_0_HI	include/ssv6200_aux.h	8424;"	d
+PEER_MAC1_31_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8414;"	d
+PEER_MAC1_31_0_I_MSK	include/ssv6200_aux.h	8422;"	d
+PEER_MAC1_31_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8412;"	d
+PEER_MAC1_31_0_MSK	include/ssv6200_aux.h	8421;"	d
+PEER_MAC1_31_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8411;"	d
+PEER_MAC1_31_0_SFT	include/ssv6200_aux.h	8423;"	d
+PEER_MAC1_31_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8413;"	d
+PEER_MAC1_31_0_SZ	include/ssv6200_aux.h	8425;"	d
+PEER_MAC1_31_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8415;"	d
+PEER_MAC1_47_32_HI	include/ssv6200_aux.h	8429;"	d
+PEER_MAC1_47_32_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8419;"	d
+PEER_MAC1_47_32_I_MSK	include/ssv6200_aux.h	8427;"	d
+PEER_MAC1_47_32_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8417;"	d
+PEER_MAC1_47_32_MSK	include/ssv6200_aux.h	8426;"	d
+PEER_MAC1_47_32_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8416;"	d
+PEER_MAC1_47_32_SFT	include/ssv6200_aux.h	8428;"	d
+PEER_MAC1_47_32_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8418;"	d
+PEER_MAC1_47_32_SZ	include/ssv6200_aux.h	8430;"	d
+PEER_MAC1_47_32_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8420;"	d
+PEER_MAC2_31_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9579;"	d
+PEER_MAC2_31_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9577;"	d
+PEER_MAC2_31_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9576;"	d
+PEER_MAC2_31_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9578;"	d
+PEER_MAC2_31_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9580;"	d
+PEER_MAC2_47_32_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9584;"	d
+PEER_MAC2_47_32_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9582;"	d
+PEER_MAC2_47_32_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9581;"	d
+PEER_MAC2_47_32_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9583;"	d
+PEER_MAC2_47_32_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9585;"	d
+PEER_MAC3_31_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9689;"	d
+PEER_MAC3_31_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9687;"	d
+PEER_MAC3_31_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9686;"	d
+PEER_MAC3_31_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9688;"	d
+PEER_MAC3_31_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9690;"	d
+PEER_MAC3_47_32_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9694;"	d
+PEER_MAC3_47_32_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9692;"	d
+PEER_MAC3_47_32_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9691;"	d
+PEER_MAC3_47_32_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9693;"	d
+PEER_MAC3_47_32_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9695;"	d
+PEER_MAC4_31_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9799;"	d
+PEER_MAC4_31_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9797;"	d
+PEER_MAC4_31_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9796;"	d
+PEER_MAC4_31_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9798;"	d
+PEER_MAC4_31_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9800;"	d
+PEER_MAC4_47_32_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9804;"	d
+PEER_MAC4_47_32_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9802;"	d
+PEER_MAC4_47_32_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9801;"	d
+PEER_MAC4_47_32_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9803;"	d
+PEER_MAC4_47_32_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9805;"	d
+PEER_MAC5_31_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9909;"	d
+PEER_MAC5_31_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9907;"	d
+PEER_MAC5_31_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9906;"	d
+PEER_MAC5_31_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9908;"	d
+PEER_MAC5_31_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9910;"	d
+PEER_MAC5_47_32_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9914;"	d
+PEER_MAC5_47_32_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9912;"	d
+PEER_MAC5_47_32_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9911;"	d
+PEER_MAC5_47_32_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9913;"	d
+PEER_MAC5_47_32_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9915;"	d
+PEER_MAC6_31_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10019;"	d
+PEER_MAC6_31_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10017;"	d
+PEER_MAC6_31_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10016;"	d
+PEER_MAC6_31_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10018;"	d
+PEER_MAC6_31_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10020;"	d
+PEER_MAC6_47_32_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10024;"	d
+PEER_MAC6_47_32_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10022;"	d
+PEER_MAC6_47_32_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10021;"	d
+PEER_MAC6_47_32_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10023;"	d
+PEER_MAC6_47_32_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10025;"	d
+PEER_MAC7_31_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10129;"	d
+PEER_MAC7_31_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10127;"	d
+PEER_MAC7_31_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10126;"	d
+PEER_MAC7_31_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10128;"	d
+PEER_MAC7_31_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10130;"	d
+PEER_MAC7_47_32_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10134;"	d
+PEER_MAC7_47_32_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10132;"	d
+PEER_MAC7_47_32_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10131;"	d
+PEER_MAC7_47_32_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10133;"	d
+PEER_MAC7_47_32_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10135;"	d
+PEER_OP_MODE0_HI	include/ssv6200_aux.h	8304;"	d
+PEER_OP_MODE0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8294;"	d
+PEER_OP_MODE0_I_MSK	include/ssv6200_aux.h	8302;"	d
+PEER_OP_MODE0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8292;"	d
+PEER_OP_MODE0_MSK	include/ssv6200_aux.h	8301;"	d
+PEER_OP_MODE0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8291;"	d
+PEER_OP_MODE0_SFT	include/ssv6200_aux.h	8303;"	d
+PEER_OP_MODE0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8293;"	d
+PEER_OP_MODE0_SZ	include/ssv6200_aux.h	8305;"	d
+PEER_OP_MODE0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8295;"	d
+PEER_OP_MODE1_HI	include/ssv6200_aux.h	8414;"	d
+PEER_OP_MODE1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8404;"	d
+PEER_OP_MODE1_I_MSK	include/ssv6200_aux.h	8412;"	d
+PEER_OP_MODE1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8402;"	d
+PEER_OP_MODE1_MSK	include/ssv6200_aux.h	8411;"	d
+PEER_OP_MODE1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8401;"	d
+PEER_OP_MODE1_SFT	include/ssv6200_aux.h	8413;"	d
+PEER_OP_MODE1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8403;"	d
+PEER_OP_MODE1_SZ	include/ssv6200_aux.h	8415;"	d
+PEER_OP_MODE1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8405;"	d
+PEER_OP_MODE2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9569;"	d
+PEER_OP_MODE2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9567;"	d
+PEER_OP_MODE2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9566;"	d
+PEER_OP_MODE2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9568;"	d
+PEER_OP_MODE2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9570;"	d
+PEER_OP_MODE3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9679;"	d
+PEER_OP_MODE3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9677;"	d
+PEER_OP_MODE3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9676;"	d
+PEER_OP_MODE3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9678;"	d
+PEER_OP_MODE3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9680;"	d
+PEER_OP_MODE4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9789;"	d
+PEER_OP_MODE4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9787;"	d
+PEER_OP_MODE4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9786;"	d
+PEER_OP_MODE4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9788;"	d
+PEER_OP_MODE4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9790;"	d
+PEER_OP_MODE5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9899;"	d
+PEER_OP_MODE5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9897;"	d
+PEER_OP_MODE5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9896;"	d
+PEER_OP_MODE5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9898;"	d
+PEER_OP_MODE5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9900;"	d
+PEER_OP_MODE6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10009;"	d
+PEER_OP_MODE6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10007;"	d
+PEER_OP_MODE6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10006;"	d
+PEER_OP_MODE6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10008;"	d
+PEER_OP_MODE6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10010;"	d
+PEER_OP_MODE7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10119;"	d
+PEER_OP_MODE7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10117;"	d
+PEER_OP_MODE7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10116;"	d
+PEER_OP_MODE7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10118;"	d
+PEER_OP_MODE7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10120;"	d
+PEER_QOS_EN0_HI	include/ssv6200_aux.h	8299;"	d
+PEER_QOS_EN0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8289;"	d
+PEER_QOS_EN0_I_MSK	include/ssv6200_aux.h	8297;"	d
+PEER_QOS_EN0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8287;"	d
+PEER_QOS_EN0_MSK	include/ssv6200_aux.h	8296;"	d
+PEER_QOS_EN0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8286;"	d
+PEER_QOS_EN0_SFT	include/ssv6200_aux.h	8298;"	d
+PEER_QOS_EN0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8288;"	d
+PEER_QOS_EN0_SZ	include/ssv6200_aux.h	8300;"	d
+PEER_QOS_EN0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8290;"	d
+PEER_QOS_EN1_HI	include/ssv6200_aux.h	8409;"	d
+PEER_QOS_EN1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8399;"	d
+PEER_QOS_EN1_I_MSK	include/ssv6200_aux.h	8407;"	d
+PEER_QOS_EN1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8397;"	d
+PEER_QOS_EN1_MSK	include/ssv6200_aux.h	8406;"	d
+PEER_QOS_EN1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8396;"	d
+PEER_QOS_EN1_SFT	include/ssv6200_aux.h	8408;"	d
+PEER_QOS_EN1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8398;"	d
+PEER_QOS_EN1_SZ	include/ssv6200_aux.h	8410;"	d
+PEER_QOS_EN1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8400;"	d
+PEER_QOS_EN2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9564;"	d
+PEER_QOS_EN2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9562;"	d
+PEER_QOS_EN2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9561;"	d
+PEER_QOS_EN2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9563;"	d
+PEER_QOS_EN2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9565;"	d
+PEER_QOS_EN3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9674;"	d
+PEER_QOS_EN3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9672;"	d
+PEER_QOS_EN3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9671;"	d
+PEER_QOS_EN3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9673;"	d
+PEER_QOS_EN3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9675;"	d
+PEER_QOS_EN4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9784;"	d
+PEER_QOS_EN4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9782;"	d
+PEER_QOS_EN4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9781;"	d
+PEER_QOS_EN4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9783;"	d
+PEER_QOS_EN4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9785;"	d
+PEER_QOS_EN5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9894;"	d
+PEER_QOS_EN5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9892;"	d
+PEER_QOS_EN5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9891;"	d
+PEER_QOS_EN5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9893;"	d
+PEER_QOS_EN5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9895;"	d
+PEER_QOS_EN6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10004;"	d
+PEER_QOS_EN6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10002;"	d
+PEER_QOS_EN6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10001;"	d
+PEER_QOS_EN6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10003;"	d
+PEER_QOS_EN6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10005;"	d
+PEER_QOS_EN7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10114;"	d
+PEER_QOS_EN7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10112;"	d
+PEER_QOS_EN7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10111;"	d
+PEER_QOS_EN7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10113;"	d
+PEER_QOS_EN7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10115;"	d
+PERI_GPI_1_0_HI	include/ssv6200_aux.h	4939;"	d
+PERI_GPI_1_0_I_MSK	include/ssv6200_aux.h	4937;"	d
+PERI_GPI_1_0_MSK	include/ssv6200_aux.h	4936;"	d
+PERI_GPI_1_0_SFT	include/ssv6200_aux.h	4938;"	d
+PERI_GPI_1_0_SZ	include/ssv6200_aux.h	4940;"	d
+PERI_GPI_2_HI	include/ssv6200_aux.h	4929;"	d
+PERI_GPI_2_I_MSK	include/ssv6200_aux.h	4927;"	d
+PERI_GPI_2_MSK	include/ssv6200_aux.h	4926;"	d
+PERI_GPI_2_SFT	include/ssv6200_aux.h	4928;"	d
+PERI_GPI_2_SZ	include/ssv6200_aux.h	4930;"	d
+PERI_GPI_SD_1_0_HI	include/ssv6200_aux.h	5284;"	d
+PERI_GPI_SD_1_0_I_MSK	include/ssv6200_aux.h	5282;"	d
+PERI_GPI_SD_1_0_MSK	include/ssv6200_aux.h	5281;"	d
+PERI_GPI_SD_1_0_SFT	include/ssv6200_aux.h	5283;"	d
+PERI_GPI_SD_1_0_SZ	include/ssv6200_aux.h	5285;"	d
+PERI_GPI_SD_2_HI	include/ssv6200_aux.h	5274;"	d
+PERI_GPI_SD_2_I_MSK	include/ssv6200_aux.h	5272;"	d
+PERI_GPI_SD_2_MSK	include/ssv6200_aux.h	5271;"	d
+PERI_GPI_SD_2_SFT	include/ssv6200_aux.h	5273;"	d
+PERI_GPI_SD_2_SZ	include/ssv6200_aux.h	5275;"	d
+PERI_MAC_ALL_RESET_HI	include/ssv6200_aux.h	3404;"	d
+PERI_MAC_ALL_RESET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2749;"	d
+PERI_MAC_ALL_RESET_I_MSK	include/ssv6200_aux.h	3402;"	d
+PERI_MAC_ALL_RESET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2747;"	d
+PERI_MAC_ALL_RESET_MSK	include/ssv6200_aux.h	3401;"	d
+PERI_MAC_ALL_RESET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2746;"	d
+PERI_MAC_ALL_RESET_SFT	include/ssv6200_aux.h	3403;"	d
+PERI_MAC_ALL_RESET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2748;"	d
+PERI_MAC_ALL_RESET_SZ	include/ssv6200_aux.h	3405;"	d
+PERI_MAC_ALL_RESET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2750;"	d
+PERI_RTC_HI	include/ssv6200_aux.h	4914;"	d
+PERI_RTC_I_MSK	include/ssv6200_aux.h	4912;"	d
+PERI_RTC_MSK	include/ssv6200_aux.h	4911;"	d
+PERI_RTC_SD_HI	include/ssv6200_aux.h	5259;"	d
+PERI_RTC_SD_I_MSK	include/ssv6200_aux.h	5257;"	d
+PERI_RTC_SD_MSK	include/ssv6200_aux.h	5256;"	d
+PERI_RTC_SD_SFT	include/ssv6200_aux.h	5258;"	d
+PERI_RTC_SD_SZ	include/ssv6200_aux.h	5260;"	d
+PERI_RTC_SFT	include/ssv6200_aux.h	4913;"	d
+PERI_RTC_SZ	include/ssv6200_aux.h	4915;"	d
+PG_TAG_127_96_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34629;"	d
+PG_TAG_127_96_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34627;"	d
+PG_TAG_127_96_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34626;"	d
+PG_TAG_127_96_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34628;"	d
+PG_TAG_127_96_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34630;"	d
+PG_TAG_159_128_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34634;"	d
+PG_TAG_159_128_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34632;"	d
+PG_TAG_159_128_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34631;"	d
+PG_TAG_159_128_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34633;"	d
+PG_TAG_159_128_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34635;"	d
+PG_TAG_191_160_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34639;"	d
+PG_TAG_191_160_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34637;"	d
+PG_TAG_191_160_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34636;"	d
+PG_TAG_191_160_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34638;"	d
+PG_TAG_191_160_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34640;"	d
+PG_TAG_223_192_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34644;"	d
+PG_TAG_223_192_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34642;"	d
+PG_TAG_223_192_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34641;"	d
+PG_TAG_223_192_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34643;"	d
+PG_TAG_223_192_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34645;"	d
+PG_TAG_255_224_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34649;"	d
+PG_TAG_255_224_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34647;"	d
+PG_TAG_255_224_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34646;"	d
+PG_TAG_255_224_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34648;"	d
+PG_TAG_255_224_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34650;"	d
+PG_TAG_31_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34614;"	d
+PG_TAG_31_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34612;"	d
+PG_TAG_31_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34611;"	d
+PG_TAG_31_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34613;"	d
+PG_TAG_31_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34615;"	d
+PG_TAG_63_32_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34619;"	d
+PG_TAG_63_32_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34617;"	d
+PG_TAG_63_32_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34616;"	d
+PG_TAG_63_32_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34618;"	d
+PG_TAG_63_32_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34620;"	d
+PG_TAG_95_64_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34624;"	d
+PG_TAG_95_64_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34622;"	d
+PG_TAG_95_64_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34621;"	d
+PG_TAG_95_64_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34623;"	d
+PG_TAG_95_64_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34625;"	d
+PHASE1_LOOP_COUNT	smac/sec_tkip.c	272;"	d	file:
+PHYTXSTART_NCYCLE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7359;"	d
+PHYTXSTART_NCYCLE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7357;"	d
+PHYTXSTART_NCYCLE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7356;"	d
+PHYTXSTART_NCYCLE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7358;"	d
+PHYTXSTART_NCYCLE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7360;"	d
+PHY_INFO_TBL1_SIZE	smac/drv_comm.h	18;"	d
+PHY_INFO_TBL2_SIZE	smac/drv_comm.h	19;"	d
+PHY_INFO_TBL3_SIZE	smac/drv_comm.h	20;"	d
+PHY_IQ_LOG_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1279;"	d
+PHY_IQ_LOG_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1277;"	d
+PHY_IQ_LOG_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1276;"	d
+PHY_IQ_LOG_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1278;"	d
+PHY_IQ_LOG_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1280;"	d
+PHY_MODE_HI	include/ssv6200_aux.h	6439;"	d
+PHY_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5684;"	d
+PHY_MODE_I_MSK	include/ssv6200_aux.h	6437;"	d
+PHY_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5682;"	d
+PHY_MODE_MSK	include/ssv6200_aux.h	6436;"	d
+PHY_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5681;"	d
+PHY_MODE_SFT	include/ssv6200_aux.h	6438;"	d
+PHY_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5683;"	d
+PHY_MODE_SZ	include/ssv6200_aux.h	6440;"	d
+PHY_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5685;"	d
+PHY_RATE_INFO_BANK_SIZE	include/ssv6200_reg.h	104;"	d
+PHY_RATE_INFO_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	125;"	d
+PHY_RATE_INFO_BASE	include/ssv6200_reg.h	55;"	d
+PHY_RATE_INFO_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	64;"	d
+PHY_SETTING_SIZE	include/ssv6xxx_common.h	234;"	d
+PIN_40_OR_56_ID_HI	include/ssv6200_aux.h	2894;"	d
+PIN_40_OR_56_ID_I_MSK	include/ssv6200_aux.h	2892;"	d
+PIN_40_OR_56_ID_MSK	include/ssv6200_aux.h	2891;"	d
+PIN_40_OR_56_ID_SFT	include/ssv6200_aux.h	2893;"	d
+PIN_40_OR_56_ID_SZ	include/ssv6200_aux.h	2895;"	d
+PKTBUF_FULL_HI	include/ssv6200_aux.h	17989;"	d
+PKTBUF_FULL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34604;"	d
+PKTBUF_FULL_I_MSK	include/ssv6200_aux.h	17987;"	d
+PKTBUF_FULL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34602;"	d
+PKTBUF_FULL_MSK	include/ssv6200_aux.h	17986;"	d
+PKTBUF_FULL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34601;"	d
+PKTBUF_FULL_SFT	include/ssv6200_aux.h	17988;"	d
+PKTBUF_FULL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34603;"	d
+PKTBUF_FULL_SZ	include/ssv6200_aux.h	17990;"	d
+PKTBUF_FULL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34605;"	d
+PKTID_ALT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33194;"	d
+PKTID_ALT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33192;"	d
+PKTID_ALT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33191;"	d
+PKTID_ALT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33193;"	d
+PKTID_ALT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33195;"	d
+PKTID_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32954;"	d
+PKTID_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32952;"	d
+PKTID_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32951;"	d
+PKTID_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32953;"	d
+PKTID_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32955;"	d
+PKT_CRYPT_ST_DEC_DONE	include/ssv6xxx_common.h	/^    PKT_CRYPT_ST_DEC_DONE,$/;"	e	enum:ssv_pkt_crypt_status
+PKT_CRYPT_ST_DEC_PRE	include/ssv6xxx_common.h	/^    PKT_CRYPT_ST_DEC_PRE,$/;"	e	enum:ssv_pkt_crypt_status
+PKT_CRYPT_ST_ENC_DONE	include/ssv6xxx_common.h	/^    PKT_CRYPT_ST_ENC_DONE,$/;"	e	enum:ssv_pkt_crypt_status
+PKT_CRYPT_ST_ENC_PRE	include/ssv6xxx_common.h	/^    PKT_CRYPT_ST_ENC_PRE,$/;"	e	enum:ssv_pkt_crypt_status
+PKT_CRYPT_ST_FAIL	include/ssv6xxx_common.h	/^    PKT_CRYPT_ST_FAIL,$/;"	e	enum:ssv_pkt_crypt_status
+PKT_CRYPT_ST_NOT_SUPPORT	include/ssv6xxx_common.h	/^    PKT_CRYPT_ST_NOT_SUPPORT$/;"	e	enum:ssv_pkt_crypt_status
+PKT_IDTBL_127_96_HI	include/ssv6200_aux.h	18059;"	d
+PKT_IDTBL_127_96_I_MSK	include/ssv6200_aux.h	18057;"	d
+PKT_IDTBL_127_96_MSK	include/ssv6200_aux.h	18056;"	d
+PKT_IDTBL_127_96_SFT	include/ssv6200_aux.h	18058;"	d
+PKT_IDTBL_127_96_SZ	include/ssv6200_aux.h	18060;"	d
+PKT_IDTBL_31_0_HI	include/ssv6200_aux.h	18044;"	d
+PKT_IDTBL_31_0_I_MSK	include/ssv6200_aux.h	18042;"	d
+PKT_IDTBL_31_0_MSK	include/ssv6200_aux.h	18041;"	d
+PKT_IDTBL_31_0_SFT	include/ssv6200_aux.h	18043;"	d
+PKT_IDTBL_31_0_SZ	include/ssv6200_aux.h	18045;"	d
+PKT_IDTBL_63_32_HI	include/ssv6200_aux.h	18049;"	d
+PKT_IDTBL_63_32_I_MSK	include/ssv6200_aux.h	18047;"	d
+PKT_IDTBL_63_32_MSK	include/ssv6200_aux.h	18046;"	d
+PKT_IDTBL_63_32_SFT	include/ssv6200_aux.h	18048;"	d
+PKT_IDTBL_63_32_SZ	include/ssv6200_aux.h	18050;"	d
+PKT_IDTBL_95_64_HI	include/ssv6200_aux.h	18054;"	d
+PKT_IDTBL_95_64_I_MSK	include/ssv6200_aux.h	18052;"	d
+PKT_IDTBL_95_64_MSK	include/ssv6200_aux.h	18051;"	d
+PKT_IDTBL_95_64_SFT	include/ssv6200_aux.h	18053;"	d
+PKT_IDTBL_95_64_SZ	include/ssv6200_aux.h	18055;"	d
+PKT_REQ_STATUS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34609;"	d
+PKT_REQ_STATUS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34607;"	d
+PKT_REQ_STATUS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34606;"	d
+PKT_REQ_STATUS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34608;"	d
+PKT_REQ_STATUS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34610;"	d
+PLF_SW_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1069;"	d
+PLF_SW_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1067;"	d
+PLF_SW_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1066;"	d
+PLF_SW_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1068;"	d
+PLF_SW_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1070;"	d
+PMUINT_WAKE_SEL_HI	include/ssv6200_aux.h	3004;"	d
+PMUINT_WAKE_SEL_I_MSK	include/ssv6200_aux.h	3002;"	d
+PMUINT_WAKE_SEL_MSK	include/ssv6200_aux.h	3001;"	d
+PMUINT_WAKE_SEL_SFT	include/ssv6200_aux.h	3003;"	d
+PMUINT_WAKE_SEL_SZ	include/ssv6200_aux.h	3005;"	d
+PMU_ENTER_SLEEP_MODE_HI	include/ssv6200_aux.h	5919;"	d
+PMU_ENTER_SLEEP_MODE_I_MSK	include/ssv6200_aux.h	5917;"	d
+PMU_ENTER_SLEEP_MODE_MSK	include/ssv6200_aux.h	5916;"	d
+PMU_ENTER_SLEEP_MODE_SFT	include/ssv6200_aux.h	5918;"	d
+PMU_ENTER_SLEEP_MODE_SZ	include/ssv6200_aux.h	5920;"	d
+PMU_WAKE_TRIG_EVENT_HI	include/ssv6200_aux.h	5909;"	d
+PMU_WAKE_TRIG_EVENT_I_MSK	include/ssv6200_aux.h	5907;"	d
+PMU_WAKE_TRIG_EVENT_MSK	include/ssv6200_aux.h	5906;"	d
+PMU_WAKE_TRIG_EVENT_SFT	include/ssv6200_aux.h	5908;"	d
+PMU_WAKE_TRIG_EVENT_SZ	include/ssv6200_aux.h	5910;"	d
+POSTMASK_TYPHOST_INT_MAP_02_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4339;"	d
+POSTMASK_TYPHOST_INT_MAP_02_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4337;"	d
+POSTMASK_TYPHOST_INT_MAP_02_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4336;"	d
+POSTMASK_TYPHOST_INT_MAP_02_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4338;"	d
+POSTMASK_TYPHOST_INT_MAP_02_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4340;"	d
+POSTMASK_TYPHOST_INT_MAP_15_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4354;"	d
+POSTMASK_TYPHOST_INT_MAP_15_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4352;"	d
+POSTMASK_TYPHOST_INT_MAP_15_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4351;"	d
+POSTMASK_TYPHOST_INT_MAP_15_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4353;"	d
+POSTMASK_TYPHOST_INT_MAP_15_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4355;"	d
+POSTMASK_TYPHOST_INT_MAP_31_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4369;"	d
+POSTMASK_TYPHOST_INT_MAP_31_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4367;"	d
+POSTMASK_TYPHOST_INT_MAP_31_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4366;"	d
+POSTMASK_TYPHOST_INT_MAP_31_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4368;"	d
+POSTMASK_TYPHOST_INT_MAP_31_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4370;"	d
+POSTMASK_TYPHOST_INT_MAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4384;"	d
+POSTMASK_TYPHOST_INT_MAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4382;"	d
+POSTMASK_TYPHOST_INT_MAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4381;"	d
+POSTMASK_TYPHOST_INT_MAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4383;"	d
+POSTMASK_TYPHOST_INT_MAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4385;"	d
+POSTMASK_TYPMCU_INT_MAP_02_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4404;"	d
+POSTMASK_TYPMCU_INT_MAP_02_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4402;"	d
+POSTMASK_TYPMCU_INT_MAP_02_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4401;"	d
+POSTMASK_TYPMCU_INT_MAP_02_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4403;"	d
+POSTMASK_TYPMCU_INT_MAP_02_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4405;"	d
+POSTMASK_TYPMCU_INT_MAP_15_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4419;"	d
+POSTMASK_TYPMCU_INT_MAP_15_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4417;"	d
+POSTMASK_TYPMCU_INT_MAP_15_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4416;"	d
+POSTMASK_TYPMCU_INT_MAP_15_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4418;"	d
+POSTMASK_TYPMCU_INT_MAP_15_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4420;"	d
+POSTMASK_TYPMCU_INT_MAP_31_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4434;"	d
+POSTMASK_TYPMCU_INT_MAP_31_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4432;"	d
+POSTMASK_TYPMCU_INT_MAP_31_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4431;"	d
+POSTMASK_TYPMCU_INT_MAP_31_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4433;"	d
+POSTMASK_TYPMCU_INT_MAP_31_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4435;"	d
+POSTMASK_TYPMCU_INT_MAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4449;"	d
+POSTMASK_TYPMCU_INT_MAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4447;"	d
+POSTMASK_TYPMCU_INT_MAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4446;"	d
+POSTMASK_TYPMCU_INT_MAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4448;"	d
+POSTMASK_TYPMCU_INT_MAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4450;"	d
+POST_PADPD	smac/hal/ssv6006c/turismo_common.h	3182;"	d
+PREDE_BT_TX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9174;"	d
+PREDE_BT_TX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9172;"	d
+PREDE_BT_TX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9171;"	d
+PREDE_BT_TX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9173;"	d
+PREDE_BT_TX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9175;"	d
+PREFETCH_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4059;"	d
+PREFETCH_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4057;"	d
+PREFETCH_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4056;"	d
+PREFETCH_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4058;"	d
+PREFETCH_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4060;"	d
+PRESCALER_USTIMER_HI	include/ssv6200_aux.h	549;"	d
+PRESCALER_USTIMER_I_MSK	include/ssv6200_aux.h	547;"	d
+PRESCALER_USTIMER_MSK	include/ssv6200_aux.h	546;"	d
+PRESCALER_USTIMER_SFT	include/ssv6200_aux.h	548;"	d
+PRESCALER_USTIMER_SZ	include/ssv6200_aux.h	550;"	d
+PRESCALER_US_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1774;"	d
+PRESCALER_US_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1772;"	d
+PRESCALER_US_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1771;"	d
+PRESCALER_US_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1773;"	d
+PRESCALER_US_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1775;"	d
+PRE_PADPD	smac/hal/ssv6006c/turismo_common.h	3102;"	d
+PRIHWID_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32979;"	d
+PRIHWID_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32977;"	d
+PRIHWID_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32976;"	d
+PRIHWID_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32978;"	d
+PRIHWID_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32980;"	d
+PRINT	smac/hal/ssv6006c/ssv6006_priv.h	28;"	d
+PRINT	smac/hal/ssv6006c/turismo_common.h	309;"	d
+PRINT_DEBUG	smac/sec_ccmp.c	32;"	d	file:
+PRINT_ERR	smac/hal/ssv6006c/ssv6006_priv.h	29;"	d
+PRINT_ERR	smac/hal/ssv6006c/turismo_common.h	313;"	d
+PRINT_INFO	smac/hal/ssv6006c/turismo_common.h	314;"	d
+PRIPKTID_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32974;"	d
+PRIPKTID_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32972;"	d
+PRIPKTID_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32971;"	d
+PRIPKTID_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32973;"	d
+PRIPKTID_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32975;"	d
+PRI_HW_PKTID_HI	include/ssv6200_aux.h	11419;"	d
+PRI_HW_PKTID_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32969;"	d
+PRI_HW_PKTID_I_MSK	include/ssv6200_aux.h	11417;"	d
+PRI_HW_PKTID_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32967;"	d
+PRI_HW_PKTID_MSK	include/ssv6200_aux.h	11416;"	d
+PRI_HW_PKTID_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32966;"	d
+PRI_HW_PKTID_SFT	include/ssv6200_aux.h	11418;"	d
+PRI_HW_PKTID_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32968;"	d
+PRI_HW_PKTID_SZ	include/ssv6200_aux.h	11420;"	d
+PRI_HW_PKTID_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32970;"	d
+PROC_DEVICETYPE_ENTRY	ssvdevice/ssv_cmd.h	20;"	d
+PROC_DIR_ENTRY	ssvdevice/ssv_cmd.h	19;"	d
+PROC_SI_ENTRY	ssvdevice/ssv_cmd.h	27;"	d
+PROC_SI_PASS_ENTRY	ssvdevice/ssv_cmd.h	29;"	d
+PROC_SI_SSID_ENTRY	ssvdevice/ssv_cmd.h	28;"	d
+PROC_SSV_CMD_ENTRY	ssvdevice/ssv_cmd.h	21;"	d
+PROC_SSV_DBG_ENTRY	ssvdevice/ssv_cmd.h	22;"	d
+PROC_SSV_FREQ_ENTRY	ssvdevice/ssv_cmd.h	23;"	d
+PROC_SSV_P2P_ENTRY	ssvdevice/ssv_cmd.h	24;"	d
+PRO_VER_HI	include/ssv6200_aux.h	6084;"	d
+PRO_VER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5134;"	d
+PRO_VER_I_MSK	include/ssv6200_aux.h	6082;"	d
+PRO_VER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5132;"	d
+PRO_VER_MSK	include/ssv6200_aux.h	6081;"	d
+PRO_VER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5131;"	d
+PRO_VER_SFT	include/ssv6200_aux.h	6083;"	d
+PRO_VER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5133;"	d
+PRO_VER_SZ	include/ssv6200_aux.h	6085;"	d
+PRO_VER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5135;"	d
+PSEUDO_HI	include/ssv6200_aux.h	6354;"	d
+PSEUDO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5599;"	d
+PSEUDO_I_MSK	include/ssv6200_aux.h	6352;"	d
+PSEUDO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5597;"	d
+PSEUDO_MSK	include/ssv6200_aux.h	6351;"	d
+PSEUDO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5596;"	d
+PSEUDO_SFT	include/ssv6200_aux.h	6353;"	d
+PSEUDO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5598;"	d
+PSEUDO_SZ	include/ssv6200_aux.h	6355;"	d
+PSEUDO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5600;"	d
+PS_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6489;"	d
+PS_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6487;"	d
+PS_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6486;"	d
+PS_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6488;"	d
+PS_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6490;"	d
+PWM_ALWAYSON_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2114;"	d
+PWM_ALWAYSON_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2112;"	d
+PWM_ALWAYSON_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2111;"	d
+PWM_ALWAYSON_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2113;"	d
+PWM_ALWAYSON_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2115;"	d
+PWM_ALWAYSON_1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2149;"	d
+PWM_ALWAYSON_1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2147;"	d
+PWM_ALWAYSON_1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2146;"	d
+PWM_ALWAYSON_1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2148;"	d
+PWM_ALWAYSON_1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2150;"	d
+PWM_ALWAYSON_2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2184;"	d
+PWM_ALWAYSON_2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2182;"	d
+PWM_ALWAYSON_2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2181;"	d
+PWM_ALWAYSON_2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2183;"	d
+PWM_ALWAYSON_2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2185;"	d
+PWM_ALWAYSON_3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2219;"	d
+PWM_ALWAYSON_3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2217;"	d
+PWM_ALWAYSON_3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2216;"	d
+PWM_ALWAYSON_3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2218;"	d
+PWM_ALWAYSON_3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2220;"	d
+PWM_ALWAYSON_4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2254;"	d
+PWM_ALWAYSON_4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2252;"	d
+PWM_ALWAYSON_4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2251;"	d
+PWM_ALWAYSON_4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2253;"	d
+PWM_ALWAYSON_4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2255;"	d
+PWM_ALWAYSON_A_HI	include/ssv6200_aux.h	494;"	d
+PWM_ALWAYSON_A_I_MSK	include/ssv6200_aux.h	492;"	d
+PWM_ALWAYSON_A_MSK	include/ssv6200_aux.h	491;"	d
+PWM_ALWAYSON_A_SFT	include/ssv6200_aux.h	493;"	d
+PWM_ALWAYSON_A_SZ	include/ssv6200_aux.h	495;"	d
+PWM_ALWAYSON_B_HI	include/ssv6200_aux.h	524;"	d
+PWM_ALWAYSON_B_I_MSK	include/ssv6200_aux.h	522;"	d
+PWM_ALWAYSON_B_MSK	include/ssv6200_aux.h	521;"	d
+PWM_ALWAYSON_B_SFT	include/ssv6200_aux.h	523;"	d
+PWM_ALWAYSON_B_SZ	include/ssv6200_aux.h	525;"	d
+PWM_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1249;"	d
+PWM_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1247;"	d
+PWM_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1246;"	d
+PWM_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1248;"	d
+PWM_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1250;"	d
+PWM_ENABLE_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2124;"	d
+PWM_ENABLE_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2122;"	d
+PWM_ENABLE_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2121;"	d
+PWM_ENABLE_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2123;"	d
+PWM_ENABLE_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2125;"	d
+PWM_ENABLE_1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2159;"	d
+PWM_ENABLE_1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2157;"	d
+PWM_ENABLE_1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2156;"	d
+PWM_ENABLE_1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2158;"	d
+PWM_ENABLE_1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2160;"	d
+PWM_ENABLE_2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2194;"	d
+PWM_ENABLE_2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2192;"	d
+PWM_ENABLE_2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2191;"	d
+PWM_ENABLE_2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2193;"	d
+PWM_ENABLE_2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2195;"	d
+PWM_ENABLE_3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2229;"	d
+PWM_ENABLE_3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2227;"	d
+PWM_ENABLE_3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2226;"	d
+PWM_ENABLE_3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2228;"	d
+PWM_ENABLE_3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2230;"	d
+PWM_ENABLE_4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2264;"	d
+PWM_ENABLE_4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2262;"	d
+PWM_ENABLE_4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2261;"	d
+PWM_ENABLE_4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2263;"	d
+PWM_ENABLE_4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2265;"	d
+PWM_ENABLE_A_HI	include/ssv6200_aux.h	504;"	d
+PWM_ENABLE_A_I_MSK	include/ssv6200_aux.h	502;"	d
+PWM_ENABLE_A_MSK	include/ssv6200_aux.h	501;"	d
+PWM_ENABLE_A_SFT	include/ssv6200_aux.h	503;"	d
+PWM_ENABLE_A_SZ	include/ssv6200_aux.h	505;"	d
+PWM_ENABLE_B_HI	include/ssv6200_aux.h	534;"	d
+PWM_ENABLE_B_I_MSK	include/ssv6200_aux.h	532;"	d
+PWM_ENABLE_B_MSK	include/ssv6200_aux.h	531;"	d
+PWM_ENABLE_B_SFT	include/ssv6200_aux.h	533;"	d
+PWM_ENABLE_B_SZ	include/ssv6200_aux.h	535;"	d
+PWM_INI_VALUE_N_A_HI	include/ssv6200_aux.h	484;"	d
+PWM_INI_VALUE_N_A_I_MSK	include/ssv6200_aux.h	482;"	d
+PWM_INI_VALUE_N_A_MSK	include/ssv6200_aux.h	481;"	d
+PWM_INI_VALUE_N_A_SFT	include/ssv6200_aux.h	483;"	d
+PWM_INI_VALUE_N_A_SZ	include/ssv6200_aux.h	485;"	d
+PWM_INI_VALUE_N_B_HI	include/ssv6200_aux.h	514;"	d
+PWM_INI_VALUE_N_B_I_MSK	include/ssv6200_aux.h	512;"	d
+PWM_INI_VALUE_N_B_MSK	include/ssv6200_aux.h	511;"	d
+PWM_INI_VALUE_N_B_SFT	include/ssv6200_aux.h	513;"	d
+PWM_INI_VALUE_N_B_SZ	include/ssv6200_aux.h	515;"	d
+PWM_INI_VALUE_PERIOD_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2129;"	d
+PWM_INI_VALUE_PERIOD_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2127;"	d
+PWM_INI_VALUE_PERIOD_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2126;"	d
+PWM_INI_VALUE_PERIOD_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2128;"	d
+PWM_INI_VALUE_PERIOD_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2130;"	d
+PWM_INI_VALUE_PERIOD_1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2164;"	d
+PWM_INI_VALUE_PERIOD_1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2162;"	d
+PWM_INI_VALUE_PERIOD_1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2161;"	d
+PWM_INI_VALUE_PERIOD_1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2163;"	d
+PWM_INI_VALUE_PERIOD_1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2165;"	d
+PWM_INI_VALUE_PERIOD_2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2199;"	d
+PWM_INI_VALUE_PERIOD_2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2197;"	d
+PWM_INI_VALUE_PERIOD_2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2196;"	d
+PWM_INI_VALUE_PERIOD_2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2198;"	d
+PWM_INI_VALUE_PERIOD_2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2200;"	d
+PWM_INI_VALUE_PERIOD_3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2234;"	d
+PWM_INI_VALUE_PERIOD_3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2232;"	d
+PWM_INI_VALUE_PERIOD_3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2231;"	d
+PWM_INI_VALUE_PERIOD_3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2233;"	d
+PWM_INI_VALUE_PERIOD_3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2235;"	d
+PWM_INI_VALUE_PERIOD_4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2269;"	d
+PWM_INI_VALUE_PERIOD_4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2267;"	d
+PWM_INI_VALUE_PERIOD_4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2266;"	d
+PWM_INI_VALUE_PERIOD_4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2268;"	d
+PWM_INI_VALUE_PERIOD_4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2270;"	d
+PWM_INI_VALUE_P_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2134;"	d
+PWM_INI_VALUE_P_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2132;"	d
+PWM_INI_VALUE_P_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2131;"	d
+PWM_INI_VALUE_P_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2133;"	d
+PWM_INI_VALUE_P_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2135;"	d
+PWM_INI_VALUE_P_1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2169;"	d
+PWM_INI_VALUE_P_1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2167;"	d
+PWM_INI_VALUE_P_1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2166;"	d
+PWM_INI_VALUE_P_1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2168;"	d
+PWM_INI_VALUE_P_1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2170;"	d
+PWM_INI_VALUE_P_2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2204;"	d
+PWM_INI_VALUE_P_2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2202;"	d
+PWM_INI_VALUE_P_2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2201;"	d
+PWM_INI_VALUE_P_2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2203;"	d
+PWM_INI_VALUE_P_2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2205;"	d
+PWM_INI_VALUE_P_3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2239;"	d
+PWM_INI_VALUE_P_3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2237;"	d
+PWM_INI_VALUE_P_3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2236;"	d
+PWM_INI_VALUE_P_3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2238;"	d
+PWM_INI_VALUE_P_3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2240;"	d
+PWM_INI_VALUE_P_4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2274;"	d
+PWM_INI_VALUE_P_4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2272;"	d
+PWM_INI_VALUE_P_4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2271;"	d
+PWM_INI_VALUE_P_4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2273;"	d
+PWM_INI_VALUE_P_4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2275;"	d
+PWM_INI_VALUE_P_A_HI	include/ssv6200_aux.h	479;"	d
+PWM_INI_VALUE_P_A_I_MSK	include/ssv6200_aux.h	477;"	d
+PWM_INI_VALUE_P_A_MSK	include/ssv6200_aux.h	476;"	d
+PWM_INI_VALUE_P_A_SFT	include/ssv6200_aux.h	478;"	d
+PWM_INI_VALUE_P_A_SZ	include/ssv6200_aux.h	480;"	d
+PWM_INI_VALUE_P_B_HI	include/ssv6200_aux.h	509;"	d
+PWM_INI_VALUE_P_B_I_MSK	include/ssv6200_aux.h	507;"	d
+PWM_INI_VALUE_P_B_MSK	include/ssv6200_aux.h	506;"	d
+PWM_INI_VALUE_P_B_SFT	include/ssv6200_aux.h	508;"	d
+PWM_INI_VALUE_P_B_SZ	include/ssv6200_aux.h	510;"	d
+PWM_INVERT_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2119;"	d
+PWM_INVERT_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2117;"	d
+PWM_INVERT_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2116;"	d
+PWM_INVERT_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2118;"	d
+PWM_INVERT_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2120;"	d
+PWM_INVERT_1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2154;"	d
+PWM_INVERT_1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2152;"	d
+PWM_INVERT_1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2151;"	d
+PWM_INVERT_1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2153;"	d
+PWM_INVERT_1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2155;"	d
+PWM_INVERT_2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2189;"	d
+PWM_INVERT_2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2187;"	d
+PWM_INVERT_2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2186;"	d
+PWM_INVERT_2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2188;"	d
+PWM_INVERT_2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2190;"	d
+PWM_INVERT_3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2224;"	d
+PWM_INVERT_3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2222;"	d
+PWM_INVERT_3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2221;"	d
+PWM_INVERT_3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2223;"	d
+PWM_INVERT_3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2225;"	d
+PWM_INVERT_4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2259;"	d
+PWM_INVERT_4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2257;"	d
+PWM_INVERT_4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2256;"	d
+PWM_INVERT_4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2258;"	d
+PWM_INVERT_4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2260;"	d
+PWM_INVERT_A_HI	include/ssv6200_aux.h	499;"	d
+PWM_INVERT_A_I_MSK	include/ssv6200_aux.h	497;"	d
+PWM_INVERT_A_MSK	include/ssv6200_aux.h	496;"	d
+PWM_INVERT_A_SFT	include/ssv6200_aux.h	498;"	d
+PWM_INVERT_A_SZ	include/ssv6200_aux.h	500;"	d
+PWM_INVERT_B_HI	include/ssv6200_aux.h	529;"	d
+PWM_INVERT_B_I_MSK	include/ssv6200_aux.h	527;"	d
+PWM_INVERT_B_MSK	include/ssv6200_aux.h	526;"	d
+PWM_INVERT_B_SFT	include/ssv6200_aux.h	528;"	d
+PWM_INVERT_B_SZ	include/ssv6200_aux.h	530;"	d
+PWM_POST_SCALER_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2104;"	d
+PWM_POST_SCALER_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2102;"	d
+PWM_POST_SCALER_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2101;"	d
+PWM_POST_SCALER_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2103;"	d
+PWM_POST_SCALER_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2105;"	d
+PWM_POST_SCALER_1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2139;"	d
+PWM_POST_SCALER_1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2137;"	d
+PWM_POST_SCALER_1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2136;"	d
+PWM_POST_SCALER_1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2138;"	d
+PWM_POST_SCALER_1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2140;"	d
+PWM_POST_SCALER_2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2174;"	d
+PWM_POST_SCALER_2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2172;"	d
+PWM_POST_SCALER_2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2171;"	d
+PWM_POST_SCALER_2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2173;"	d
+PWM_POST_SCALER_2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2175;"	d
+PWM_POST_SCALER_3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2209;"	d
+PWM_POST_SCALER_3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2207;"	d
+PWM_POST_SCALER_3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2206;"	d
+PWM_POST_SCALER_3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2208;"	d
+PWM_POST_SCALER_3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2210;"	d
+PWM_POST_SCALER_4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2244;"	d
+PWM_POST_SCALER_4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2242;"	d
+PWM_POST_SCALER_4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2241;"	d
+PWM_POST_SCALER_4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2243;"	d
+PWM_POST_SCALER_4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2245;"	d
+PWM_POST_SCALER_A_HI	include/ssv6200_aux.h	489;"	d
+PWM_POST_SCALER_A_I_MSK	include/ssv6200_aux.h	487;"	d
+PWM_POST_SCALER_A_MSK	include/ssv6200_aux.h	486;"	d
+PWM_POST_SCALER_A_SFT	include/ssv6200_aux.h	488;"	d
+PWM_POST_SCALER_A_SZ	include/ssv6200_aux.h	490;"	d
+PWM_POST_SCALER_B_HI	include/ssv6200_aux.h	519;"	d
+PWM_POST_SCALER_B_I_MSK	include/ssv6200_aux.h	517;"	d
+PWM_POST_SCALER_B_MSK	include/ssv6200_aux.h	516;"	d
+PWM_POST_SCALER_B_SFT	include/ssv6200_aux.h	518;"	d
+PWM_POST_SCALER_B_SZ	include/ssv6200_aux.h	520;"	d
+PWM_REG_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	94;"	d
+PWM_REG_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	33;"	d
+PWM_SETTING_UPDATE_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2109;"	d
+PWM_SETTING_UPDATE_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2107;"	d
+PWM_SETTING_UPDATE_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2106;"	d
+PWM_SETTING_UPDATE_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2108;"	d
+PWM_SETTING_UPDATE_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2110;"	d
+PWM_SETTING_UPDATE_1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2144;"	d
+PWM_SETTING_UPDATE_1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2142;"	d
+PWM_SETTING_UPDATE_1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2141;"	d
+PWM_SETTING_UPDATE_1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2143;"	d
+PWM_SETTING_UPDATE_1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2145;"	d
+PWM_SETTING_UPDATE_2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2179;"	d
+PWM_SETTING_UPDATE_2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2177;"	d
+PWM_SETTING_UPDATE_2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2176;"	d
+PWM_SETTING_UPDATE_2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2178;"	d
+PWM_SETTING_UPDATE_2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2180;"	d
+PWM_SETTING_UPDATE_3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2214;"	d
+PWM_SETTING_UPDATE_3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2212;"	d
+PWM_SETTING_UPDATE_3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2211;"	d
+PWM_SETTING_UPDATE_3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2213;"	d
+PWM_SETTING_UPDATE_3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2215;"	d
+PWM_SETTING_UPDATE_4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2249;"	d
+PWM_SETTING_UPDATE_4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2247;"	d
+PWM_SETTING_UPDATE_4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2246;"	d
+PWM_SETTING_UPDATE_4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2248;"	d
+PWM_SETTING_UPDATE_4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2250;"	d
+PWRSV_DISABLE	smac/dev.h	/^    PWRSV_DISABLE,$/;"	e	enum:PWRSV_STATUS
+PWRSV_ENABLE	smac/dev.h	/^    PWRSV_ENABLE,$/;"	e	enum:PWRSV_STATUS
+PWRSV_PREPARE	smac/dev.h	/^    PWRSV_PREPARE,$/;"	e	enum:PWRSV_STATUS
+PWRSV_STATUS	smac/dev.h	/^enum PWRSV_STATUS{$/;"	g
+Q0_PKT_CLS_MIB_EN_HI	include/ssv6200_aux.h	9364;"	d
+Q0_PKT_CLS_MIB_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9199;"	d
+Q0_PKT_CLS_MIB_EN_I_MSK	include/ssv6200_aux.h	9362;"	d
+Q0_PKT_CLS_MIB_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9197;"	d
+Q0_PKT_CLS_MIB_EN_MSK	include/ssv6200_aux.h	9361;"	d
+Q0_PKT_CLS_MIB_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9196;"	d
+Q0_PKT_CLS_MIB_EN_SFT	include/ssv6200_aux.h	9363;"	d
+Q0_PKT_CLS_MIB_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9198;"	d
+Q0_PKT_CLS_MIB_EN_SZ	include/ssv6200_aux.h	9365;"	d
+Q0_PKT_CLS_MIB_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9200;"	d
+Q0_PKT_CLS_ONGOING_HI	include/ssv6200_aux.h	9369;"	d
+Q0_PKT_CLS_ONGOING_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9204;"	d
+Q0_PKT_CLS_ONGOING_I_MSK	include/ssv6200_aux.h	9367;"	d
+Q0_PKT_CLS_ONGOING_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9202;"	d
+Q0_PKT_CLS_ONGOING_MSK	include/ssv6200_aux.h	9366;"	d
+Q0_PKT_CLS_ONGOING_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9201;"	d
+Q0_PKT_CLS_ONGOING_SFT	include/ssv6200_aux.h	9368;"	d
+Q0_PKT_CLS_ONGOING_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9203;"	d
+Q0_PKT_CLS_ONGOING_SZ	include/ssv6200_aux.h	9370;"	d
+Q0_PKT_CLS_ONGOING_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9205;"	d
+Q1_PKT_CLS_MIB_EN_HI	include/ssv6200_aux.h	9374;"	d
+Q1_PKT_CLS_MIB_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9209;"	d
+Q1_PKT_CLS_MIB_EN_I_MSK	include/ssv6200_aux.h	9372;"	d
+Q1_PKT_CLS_MIB_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9207;"	d
+Q1_PKT_CLS_MIB_EN_MSK	include/ssv6200_aux.h	9371;"	d
+Q1_PKT_CLS_MIB_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9206;"	d
+Q1_PKT_CLS_MIB_EN_SFT	include/ssv6200_aux.h	9373;"	d
+Q1_PKT_CLS_MIB_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9208;"	d
+Q1_PKT_CLS_MIB_EN_SZ	include/ssv6200_aux.h	9375;"	d
+Q1_PKT_CLS_MIB_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9210;"	d
+Q1_PKT_CLS_ONGOING_HI	include/ssv6200_aux.h	9379;"	d
+Q1_PKT_CLS_ONGOING_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9214;"	d
+Q1_PKT_CLS_ONGOING_I_MSK	include/ssv6200_aux.h	9377;"	d
+Q1_PKT_CLS_ONGOING_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9212;"	d
+Q1_PKT_CLS_ONGOING_MSK	include/ssv6200_aux.h	9376;"	d
+Q1_PKT_CLS_ONGOING_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9211;"	d
+Q1_PKT_CLS_ONGOING_SFT	include/ssv6200_aux.h	9378;"	d
+Q1_PKT_CLS_ONGOING_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9213;"	d
+Q1_PKT_CLS_ONGOING_SZ	include/ssv6200_aux.h	9380;"	d
+Q1_PKT_CLS_ONGOING_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9215;"	d
+Q2_PKT_CLS_MIB_EN_HI	include/ssv6200_aux.h	9384;"	d
+Q2_PKT_CLS_MIB_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9219;"	d
+Q2_PKT_CLS_MIB_EN_I_MSK	include/ssv6200_aux.h	9382;"	d
+Q2_PKT_CLS_MIB_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9217;"	d
+Q2_PKT_CLS_MIB_EN_MSK	include/ssv6200_aux.h	9381;"	d
+Q2_PKT_CLS_MIB_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9216;"	d
+Q2_PKT_CLS_MIB_EN_SFT	include/ssv6200_aux.h	9383;"	d
+Q2_PKT_CLS_MIB_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9218;"	d
+Q2_PKT_CLS_MIB_EN_SZ	include/ssv6200_aux.h	9385;"	d
+Q2_PKT_CLS_MIB_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9220;"	d
+Q2_PKT_CLS_ONGOING_HI	include/ssv6200_aux.h	9389;"	d
+Q2_PKT_CLS_ONGOING_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9224;"	d
+Q2_PKT_CLS_ONGOING_I_MSK	include/ssv6200_aux.h	9387;"	d
+Q2_PKT_CLS_ONGOING_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9222;"	d
+Q2_PKT_CLS_ONGOING_MSK	include/ssv6200_aux.h	9386;"	d
+Q2_PKT_CLS_ONGOING_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9221;"	d
+Q2_PKT_CLS_ONGOING_SFT	include/ssv6200_aux.h	9388;"	d
+Q2_PKT_CLS_ONGOING_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9223;"	d
+Q2_PKT_CLS_ONGOING_SZ	include/ssv6200_aux.h	9390;"	d
+Q2_PKT_CLS_ONGOING_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9225;"	d
+Q3_PKT_CLS_MIB_EN_HI	include/ssv6200_aux.h	9394;"	d
+Q3_PKT_CLS_MIB_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9229;"	d
+Q3_PKT_CLS_MIB_EN_I_MSK	include/ssv6200_aux.h	9392;"	d
+Q3_PKT_CLS_MIB_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9227;"	d
+Q3_PKT_CLS_MIB_EN_MSK	include/ssv6200_aux.h	9391;"	d
+Q3_PKT_CLS_MIB_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9226;"	d
+Q3_PKT_CLS_MIB_EN_SFT	include/ssv6200_aux.h	9393;"	d
+Q3_PKT_CLS_MIB_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9228;"	d
+Q3_PKT_CLS_MIB_EN_SZ	include/ssv6200_aux.h	9395;"	d
+Q3_PKT_CLS_MIB_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9230;"	d
+Q3_PKT_CLS_ONGOING_HI	include/ssv6200_aux.h	9399;"	d
+Q3_PKT_CLS_ONGOING_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9234;"	d
+Q3_PKT_CLS_ONGOING_I_MSK	include/ssv6200_aux.h	9397;"	d
+Q3_PKT_CLS_ONGOING_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9232;"	d
+Q3_PKT_CLS_ONGOING_MSK	include/ssv6200_aux.h	9396;"	d
+Q3_PKT_CLS_ONGOING_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9231;"	d
+Q3_PKT_CLS_ONGOING_SFT	include/ssv6200_aux.h	9398;"	d
+Q3_PKT_CLS_ONGOING_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9233;"	d
+Q3_PKT_CLS_ONGOING_SZ	include/ssv6200_aux.h	9400;"	d
+Q3_PKT_CLS_ONGOING_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9235;"	d
+QLERROR_BCAST_CALC_C	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	/^    QLERROR_BCAST_CALC_C = 9,$/;"	e	enum:fill80211relust
+QLERROR_BCAST_NOT_FRAME	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	/^    QLERROR_BCAST_NOT_FRAME = 8,$/;"	e	enum:fill80211relust
+QLERROR_BCAST_ONE_DATA	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	/^    QLERROR_BCAST_ONE_DATA = 10,$/;"	e	enum:fill80211relust
+QLERROR_DECRYPT_FAILED	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	/^ QLERROR_DECRYPT_FAILED = 4,$/;"	e	enum:fill80211relust
+QLERROR_HOP	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	/^ QLERROR_HOP = 1,$/;"	e	enum:fill80211relust
+QLERROR_HOP_NULL	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	/^ QLERROR_HOP_NULL = 6,$/;"	e	enum:wifisyncerror
+QLERROR_INIT_OTHER	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	/^ QLERROR_INIT_OTHER = 9,$/;"	e	enum:wifisyncerror
+QLERROR_INIT_SUCCESS	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	/^ QLERROR_INIT_SUCCESS = 0,$/;"	e	enum:wifisyncerror
+QLERROR_LOCK	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	/^ QLERROR_LOCK = 2,$/;"	e	enum:fill80211relust
+QLERROR_MCAST_NOT_FRAME	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	/^    QLERROR_MCAST_NOT_FRAME = 11,$/;"	e	enum:fill80211relust
+QLERROR_MCAST_ONE_DATA	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	/^    QLERROR_MCAST_ONE_DATA = 12,$/;"	e	enum:fill80211relust
+QLERROR_MEMORY_ALLOC	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	/^ QLERROR_MEMORY_ALLOC = 1,$/;"	e	enum:wifisyncerror
+QLERROR_NEED_INIT	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	/^ QLERROR_NEED_INIT = 5,$/;"	e	enum:fill80211relust
+QLERROR_NOTIFY_NULL	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	/^ QLERROR_NOTIFY_NULL = 2,$/;"	e	enum:wifisyncerror
+QLERROR_OPENSSL_LOAD_FAILED	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	/^ QLERROR_OPENSSL_LOAD_FAILED = 5,$/;"	e	enum:wifisyncerror
+QLERROR_OTHER	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	/^ QLERROR_OTHER = 3,$/;"	e	enum:fill80211relust
+QLERROR_PARAM_KEY	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	/^ QLERROR_PARAM_KEY = 3,$/;"	e	enum:wifisyncerror
+QLERROR_PARAM_KEY_LEN	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	/^ QLERROR_PARAM_KEY_LEN = 4,$/;"	e	enum:wifisyncerror
+QLERROR_START_FRAME	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	/^ QLERROR_START_FRAME = 7,$/;"	e	enum:fill80211relust
+QLERROR_SUCCESS	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	/^ QLERROR_SUCCESS = 0,$/;"	e	enum:fill80211relust
+QLERROR_SZIFNAME_INVALID	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	/^ QLERROR_SZIFNAME_INVALID = 7,$/;"	e	enum:wifisyncerror
+QLERROR_VERSION	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	/^ QLERROR_VERSION = 6,$/;"	e	enum:fill80211relust
+QLERROR_WIFICHIP_NOTSUPPORT	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	/^ QLERROR_WIFICHIP_NOTSUPPORT = 8,$/;"	e	enum:wifisyncerror
+QLMAX_IP_LEN	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	49;"	d
+QLMAX_PSWD_LEN	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	48;"	d
+QLMAX_SSID_LEN	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	47;"	d
+QOS_EN_HI	include/ssv6200_aux.h	9134;"	d
+QOS_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8889;"	d
+QOS_EN_I_MSK	include/ssv6200_aux.h	9132;"	d
+QOS_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8887;"	d
+QOS_EN_MSK	include/ssv6200_aux.h	9131;"	d
+QOS_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8886;"	d
+QOS_EN_SFT	include/ssv6200_aux.h	9133;"	d
+QOS_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8888;"	d
+QOS_EN_SZ	include/ssv6200_aux.h	9135;"	d
+QOS_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8890;"	d
+QUEUE_STATUS_BUF_SIZE	smac/ssv6xxx_debugfs.c	30;"	d	file:
+Q_DELAY_MS	ssvdevice/ssv_cmd.c	1509;"	d	file:
+Q_REQ_DUR_HI	include/ssv6200_aux.h	7789;"	d
+Q_REQ_DUR_I_MSK	include/ssv6200_aux.h	7787;"	d
+Q_REQ_DUR_MSK	include/ssv6200_aux.h	7786;"	d
+Q_REQ_DUR_SFT	include/ssv6200_aux.h	7788;"	d
+Q_REQ_DUR_SZ	include/ssv6200_aux.h	7790;"	d
+R5_RESPONSE_FLAG_HI	include/ssv6200_aux.h	3339;"	d
+R5_RESPONSE_FLAG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2659;"	d
+R5_RESPONSE_FLAG_I_MSK	include/ssv6200_aux.h	3337;"	d
+R5_RESPONSE_FLAG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2657;"	d
+R5_RESPONSE_FLAG_MSK	include/ssv6200_aux.h	3336;"	d
+R5_RESPONSE_FLAG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2656;"	d
+R5_RESPONSE_FLAG_SFT	include/ssv6200_aux.h	3338;"	d
+R5_RESPONSE_FLAG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2658;"	d
+R5_RESPONSE_FLAG_SZ	include/ssv6200_aux.h	3340;"	d
+R5_RESPONSE_FLAG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2660;"	d
+RANDOM_SEED1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9149;"	d
+RANDOM_SEED1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9147;"	d
+RANDOM_SEED1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9146;"	d
+RANDOM_SEED1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9148;"	d
+RANDOM_SEED1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9150;"	d
+RANDOM_SEED2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9144;"	d
+RANDOM_SEED2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9142;"	d
+RANDOM_SEED2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9141;"	d
+RANDOM_SEED2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9143;"	d
+RANDOM_SEED2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9145;"	d
+RANDOM_SEED3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9139;"	d
+RANDOM_SEED3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9137;"	d
+RANDOM_SEED3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9136;"	d
+RANDOM_SEED3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9138;"	d
+RANDOM_SEED3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9140;"	d
+RAND_EN_HI	include/ssv6200_aux.h	6379;"	d
+RAND_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5624;"	d
+RAND_EN_I_MSK	include/ssv6200_aux.h	6377;"	d
+RAND_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5622;"	d
+RAND_EN_MSK	include/ssv6200_aux.h	6376;"	d
+RAND_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5621;"	d
+RAND_EN_SFT	include/ssv6200_aux.h	6378;"	d
+RAND_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5623;"	d
+RAND_EN_SZ	include/ssv6200_aux.h	6380;"	d
+RAND_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5625;"	d
+RAND_NUM_HI	include/ssv6200_aux.h	6384;"	d
+RAND_NUM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5629;"	d
+RAND_NUM_I_MSK	include/ssv6200_aux.h	6382;"	d
+RAND_NUM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5627;"	d
+RAND_NUM_MSK	include/ssv6200_aux.h	6381;"	d
+RAND_NUM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5626;"	d
+RAND_NUM_SFT	include/ssv6200_aux.h	6383;"	d
+RAND_NUM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5628;"	d
+RAND_NUM_SZ	include/ssv6200_aux.h	6385;"	d
+RAND_NUM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5630;"	d
+RATE	smac/init.c	100;"	d	file:
+RATE_CONTROL_REALTIME_UPDATE	include/ssv_mod_conf.h	25;"	d
+RATE_RPT	include/ssv6xxx_common.h	71;"	d
+RATE_RPT	smac/hal/ssv6006c/ssv6006_common.h	57;"	d
+RATE_TABLE_SIZE	smac/ssv_rc_common.h	36;"	d
+RAW_TYPHOST_INT_MAP_02_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4334;"	d
+RAW_TYPHOST_INT_MAP_02_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4332;"	d
+RAW_TYPHOST_INT_MAP_02_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4331;"	d
+RAW_TYPHOST_INT_MAP_02_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4333;"	d
+RAW_TYPHOST_INT_MAP_02_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4335;"	d
+RAW_TYPHOST_INT_MAP_15_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4349;"	d
+RAW_TYPHOST_INT_MAP_15_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4347;"	d
+RAW_TYPHOST_INT_MAP_15_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4346;"	d
+RAW_TYPHOST_INT_MAP_15_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4348;"	d
+RAW_TYPHOST_INT_MAP_15_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4350;"	d
+RAW_TYPHOST_INT_MAP_31_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4364;"	d
+RAW_TYPHOST_INT_MAP_31_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4362;"	d
+RAW_TYPHOST_INT_MAP_31_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4361;"	d
+RAW_TYPHOST_INT_MAP_31_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4363;"	d
+RAW_TYPHOST_INT_MAP_31_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4365;"	d
+RAW_TYPHOST_INT_MAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4379;"	d
+RAW_TYPHOST_INT_MAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4377;"	d
+RAW_TYPHOST_INT_MAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4376;"	d
+RAW_TYPHOST_INT_MAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4378;"	d
+RAW_TYPHOST_INT_MAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4380;"	d
+RAW_TYPMCU_INT_MAP_02_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4399;"	d
+RAW_TYPMCU_INT_MAP_02_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4397;"	d
+RAW_TYPMCU_INT_MAP_02_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4396;"	d
+RAW_TYPMCU_INT_MAP_02_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4398;"	d
+RAW_TYPMCU_INT_MAP_02_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4400;"	d
+RAW_TYPMCU_INT_MAP_15_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4414;"	d
+RAW_TYPMCU_INT_MAP_15_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4412;"	d
+RAW_TYPMCU_INT_MAP_15_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4411;"	d
+RAW_TYPMCU_INT_MAP_15_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4413;"	d
+RAW_TYPMCU_INT_MAP_15_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4415;"	d
+RAW_TYPMCU_INT_MAP_31_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4429;"	d
+RAW_TYPMCU_INT_MAP_31_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4427;"	d
+RAW_TYPMCU_INT_MAP_31_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4426;"	d
+RAW_TYPMCU_INT_MAP_31_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4428;"	d
+RAW_TYPMCU_INT_MAP_31_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4430;"	d
+RAW_TYPMCU_INT_MAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4444;"	d
+RAW_TYPMCU_INT_MAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4442;"	d
+RAW_TYPMCU_INT_MAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4441;"	d
+RAW_TYPMCU_INT_MAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4443;"	d
+RAW_TYPMCU_INT_MAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4445;"	d
+RCAL_RDY_HI	include/ssv6200_aux.h	17554;"	d
+RCAL_RDY_I_MSK	include/ssv6200_aux.h	17552;"	d
+RCAL_RDY_MSK	include/ssv6200_aux.h	17551;"	d
+RCAL_RDY_SFT	include/ssv6200_aux.h	17553;"	d
+RCAL_RDY_SZ	include/ssv6200_aux.h	17555;"	d
+RC_FIRMWARE_REPORT_FLAG	include/ssv6xxx_common.h	19;"	d
+RC_FLAG_HT	smac/ssv_rc_common.h	25;"	d
+RC_FLAG_HT_GF	smac/ssv_rc_common.h	27;"	d
+RC_FLAG_HT_SGI	smac/ssv_rc_common.h	26;"	d
+RC_FLAG_INVALID	smac/ssv_rc_common.h	23;"	d
+RC_FLAG_LEGACY	smac/ssv_rc_common.h	24;"	d
+RC_FLAG_SHORT_PREAMBLE	smac/ssv_rc_common.h	28;"	d
+RC_PID_COEFF_D	smac/ssv_rc.h	28;"	d
+RC_PID_COEFF_I	smac/ssv_rc.h	27;"	d
+RC_PID_COEFF_P	smac/ssv_rc.h	26;"	d
+RC_PID_DO_ARITH_RIGHT_SHIFT	smac/ssv_rc.h	21;"	d
+RC_PID_INTERVAL	smac/ssv_rc.h	20;"	d
+RC_PID_NORM_OFFSET	smac/ssv_rc.h	23;"	d
+RC_PID_REPORT_INTERVAL	smac/ssv_rc.h	19;"	d
+RC_PID_SMOOTHING	smac/ssv_rc.h	25;"	d
+RC_PID_SMOOTHING_SHIFT	smac/ssv_rc.h	24;"	d
+RC_RETRY_PARAM_OFFSET	include/ssv6200_common.h	188;"	d
+RC_STA_CAP_GF	smac/ssv_rc_common.h	39;"	d
+RC_STA_CAP_HT	smac/ssv_rc_common.h	38;"	d
+RC_STA_CAP_SGI_20	smac/ssv_rc_common.h	40;"	d
+RC_STA_CAP_SHORT_PREAMBLE	smac/ssv_rc_common.h	41;"	d
+RC_STA_VALID	smac/ssv_rc_common.h	37;"	d
+RC_TYPE_B_ONLY	smac/ssv_rc_common.h	/^    RC_TYPE_B_ONLY=0,$/;"	e	enum:ssv_rc_rate_type
+RC_TYPE_HT_GF	smac/ssv_rc_common.h	/^    RC_TYPE_HT_GF,$/;"	e	enum:ssv_rc_rate_type
+RC_TYPE_HT_LGI_20	smac/ssv_rc_common.h	/^    RC_TYPE_HT_LGI_20,$/;"	e	enum:ssv_rc_rate_type
+RC_TYPE_HT_SGI_20	smac/ssv_rc_common.h	/^    RC_TYPE_HT_SGI_20,$/;"	e	enum:ssv_rc_rate_type
+RC_TYPE_LEGACY_GB	smac/ssv_rc_common.h	/^    RC_TYPE_LEGACY_GB,$/;"	e	enum:ssv_rc_rate_type
+RC_TYPE_LGI_20	smac/ssv_rc_common.h	/^    RC_TYPE_LGI_20,$/;"	e	enum:ssv_rc_rate_type
+RC_TYPE_MAX	smac/ssv_rc_common.h	/^    RC_TYPE_MAX,$/;"	e	enum:ssv_rc_rate_type
+RC_TYPE_SGI_20	smac/ssv_rc_common.h	/^    RC_TYPE_SGI_20,$/;"	e	enum:ssv_rc_rate_type
+RDATA_RDY_HI	include/ssv6200_aux.h	4004;"	d
+RDATA_RDY_I_MSK	include/ssv6200_aux.h	4002;"	d
+RDATA_RDY_MSK	include/ssv6200_aux.h	4001;"	d
+RDATA_RDY_SFT	include/ssv6200_aux.h	4003;"	d
+RDATA_RDY_SZ	include/ssv6200_aux.h	4005;"	d
+RDY_FOR_FW_DOWNLOAD_HI	include/ssv6200_aux.h	3144;"	d
+RDY_FOR_FW_DOWNLOAD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2614;"	d
+RDY_FOR_FW_DOWNLOAD_I_MSK	include/ssv6200_aux.h	3142;"	d
+RDY_FOR_FW_DOWNLOAD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2612;"	d
+RDY_FOR_FW_DOWNLOAD_MSK	include/ssv6200_aux.h	3141;"	d
+RDY_FOR_FW_DOWNLOAD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2611;"	d
+RDY_FOR_FW_DOWNLOAD_SFT	include/ssv6200_aux.h	3143;"	d
+RDY_FOR_FW_DOWNLOAD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2613;"	d
+RDY_FOR_FW_DOWNLOAD_SZ	include/ssv6200_aux.h	3145;"	d
+RDY_FOR_FW_DOWNLOAD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2615;"	d
+RDY_FOR_TX_RX_HI	include/ssv6200_aux.h	3139;"	d
+RDY_FOR_TX_RX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2609;"	d
+RDY_FOR_TX_RX_I_MSK	include/ssv6200_aux.h	3137;"	d
+RDY_FOR_TX_RX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2607;"	d
+RDY_FOR_TX_RX_MSK	include/ssv6200_aux.h	3136;"	d
+RDY_FOR_TX_RX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2606;"	d
+RDY_FOR_TX_RX_SFT	include/ssv6200_aux.h	3138;"	d
+RDY_FOR_TX_RX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2608;"	d
+RDY_FOR_TX_RX_SZ	include/ssv6200_aux.h	3140;"	d
+RDY_FOR_TX_RX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2610;"	d
+RD_ADDR_HI	include/ssv6200_aux.h	6409;"	d
+RD_ADDR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5654;"	d
+RD_ADDR_I_MSK	include/ssv6200_aux.h	6407;"	d
+RD_ADDR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5652;"	d
+RD_ADDR_MSK	include/ssv6200_aux.h	6406;"	d
+RD_ADDR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5651;"	d
+RD_ADDR_SFT	include/ssv6200_aux.h	6408;"	d
+RD_ADDR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5653;"	d
+RD_ADDR_SZ	include/ssv6200_aux.h	6410;"	d
+RD_ADDR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5655;"	d
+RD_DAT_CNT_CLR_HI	include/ssv6200_aux.h	4059;"	d
+RD_DAT_CNT_CLR_I_MSK	include/ssv6200_aux.h	4057;"	d
+RD_DAT_CNT_CLR_MSK	include/ssv6200_aux.h	4056;"	d
+RD_DAT_CNT_CLR_SFT	include/ssv6200_aux.h	4058;"	d
+RD_DAT_CNT_CLR_SZ	include/ssv6200_aux.h	4060;"	d
+RD_DAT_CNT_HI	include/ssv6200_aux.h	4039;"	d
+RD_DAT_CNT_I_MSK	include/ssv6200_aux.h	4037;"	d
+RD_DAT_CNT_MSK	include/ssv6200_aux.h	4036;"	d
+RD_DAT_CNT_SFT	include/ssv6200_aux.h	4038;"	d
+RD_DAT_CNT_SZ	include/ssv6200_aux.h	4040;"	d
+RD_ID_HI	include/ssv6200_aux.h	6414;"	d
+RD_ID_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5659;"	d
+RD_ID_I_MSK	include/ssv6200_aux.h	6412;"	d
+RD_ID_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5657;"	d
+RD_ID_MSK	include/ssv6200_aux.h	6411;"	d
+RD_ID_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5656;"	d
+RD_ID_SFT	include/ssv6200_aux.h	6413;"	d
+RD_ID_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5658;"	d
+RD_ID_SZ	include/ssv6200_aux.h	6415;"	d
+RD_ID_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5660;"	d
+RD_STS_CNT_CLR_HI	include/ssv6200_aux.h	4054;"	d
+RD_STS_CNT_CLR_I_MSK	include/ssv6200_aux.h	4052;"	d
+RD_STS_CNT_CLR_MSK	include/ssv6200_aux.h	4051;"	d
+RD_STS_CNT_CLR_SFT	include/ssv6200_aux.h	4053;"	d
+RD_STS_CNT_CLR_SZ	include/ssv6200_aux.h	4055;"	d
+RD_STS_CNT_HI	include/ssv6200_aux.h	4044;"	d
+RD_STS_CNT_I_MSK	include/ssv6200_aux.h	4042;"	d
+RD_STS_CNT_MSK	include/ssv6200_aux.h	4041;"	d
+RD_STS_CNT_SFT	include/ssv6200_aux.h	4043;"	d
+RD_STS_CNT_SZ	include/ssv6200_aux.h	4045;"	d
+READ_ADDRESS_HI	include/ssv6200_aux.h	3379;"	d
+READ_ADDRESS_I_MSK	include/ssv6200_aux.h	3377;"	d
+READ_ADDRESS_MSK	include/ssv6200_aux.h	3376;"	d
+READ_ADDRESS_SFT	include/ssv6200_aux.h	3378;"	d
+READ_ADDRESS_SZ	include/ssv6200_aux.h	3380;"	d
+READ_CHUNK	ssvdevice/ssvdevice.c	71;"	d	file:
+READ_DATA_HI	include/ssv6200_aux.h	3374;"	d
+READ_DATA_I_MSK	include/ssv6200_aux.h	3372;"	d
+READ_DATA_MSK	include/ssv6200_aux.h	3371;"	d
+READ_DATA_SFT	include/ssv6200_aux.h	3373;"	d
+READ_DATA_SZ	include/ssv6200_aux.h	3375;"	d
+REASON_TRAP0_HI	include/ssv6200_aux.h	9164;"	d
+REASON_TRAP0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8929;"	d
+REASON_TRAP0_I_MSK	include/ssv6200_aux.h	9162;"	d
+REASON_TRAP0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8927;"	d
+REASON_TRAP0_MSK	include/ssv6200_aux.h	9161;"	d
+REASON_TRAP0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8926;"	d
+REASON_TRAP0_SFT	include/ssv6200_aux.h	9163;"	d
+REASON_TRAP0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8928;"	d
+REASON_TRAP0_SZ	include/ssv6200_aux.h	9165;"	d
+REASON_TRAP0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8930;"	d
+REASON_TRAP1_HI	include/ssv6200_aux.h	9169;"	d
+REASON_TRAP1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8934;"	d
+REASON_TRAP1_I_MSK	include/ssv6200_aux.h	9167;"	d
+REASON_TRAP1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8932;"	d
+REASON_TRAP1_MSK	include/ssv6200_aux.h	9166;"	d
+REASON_TRAP1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8931;"	d
+REASON_TRAP1_SFT	include/ssv6200_aux.h	9168;"	d
+REASON_TRAP1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8933;"	d
+REASON_TRAP1_SZ	include/ssv6200_aux.h	9170;"	d
+REASON_TRAP1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8935;"	d
+REG32	smac/hal/ssv6006c/ssv6006_priv.h	20;"	d
+REG32_R	smac/hal/ssv6006c/ssv6006_priv_normal.h	18;"	d
+REG32_R	smac/hal/ssv6006c/ssv6006_priv_safe.h	18;"	d
+REG32_W	smac/hal/ssv6006c/ssv6006_priv.h	21;"	d
+REG_AHB_DEBUG_MX_HI	include/ssv6200_aux.h	334;"	d
+REG_AHB_DEBUG_MX_I_MSK	include/ssv6200_aux.h	332;"	d
+REG_AHB_DEBUG_MX_MSK	include/ssv6200_aux.h	331;"	d
+REG_AHB_DEBUG_MX_SFT	include/ssv6200_aux.h	333;"	d
+REG_AHB_DEBUG_MX_SZ	include/ssv6200_aux.h	335;"	d
+REG_CARD_FW_DL_STATUS	hwif/sdio/sdio_def.h	31;"	d
+REG_CARD_PKT_LEN_0	hwif/sdio/sdio_def.h	29;"	d
+REG_CARD_PKT_LEN_1	hwif/sdio/sdio_def.h	30;"	d
+REG_CARD_RCA_0	hwif/sdio/sdio_def.h	33;"	d
+REG_CARD_RCA_1	hwif/sdio/sdio_def.h	34;"	d
+REG_CARD_SELF_TEST	hwif/sdio/sdio_def.h	32;"	d
+REG_DATA_IO_PORT_0	hwif/sdio/sdio_def.h	21;"	d
+REG_DATA_IO_PORT_1	hwif/sdio/sdio_def.h	22;"	d
+REG_DATA_IO_PORT_2	hwif/sdio/sdio_def.h	23;"	d
+REG_Fn1_STATUS	hwif/sdio/sdio_def.h	27;"	d
+REG_INT_MASK	hwif/sdio/sdio_def.h	24;"	d
+REG_INT_STATUS	hwif/sdio/sdio_def.h	25;"	d
+REG_INT_TRIGGER	hwif/sdio/sdio_def.h	26;"	d
+REG_OUTPUT_TIMING_REG	hwif/sdio/sdio_def.h	37;"	d
+REG_PKT_R_NBRT_HI	include/ssv6200_aux.h	344;"	d
+REG_PKT_R_NBRT_I_MSK	include/ssv6200_aux.h	342;"	d
+REG_PKT_R_NBRT_MSK	include/ssv6200_aux.h	341;"	d
+REG_PKT_R_NBRT_SFT	include/ssv6200_aux.h	343;"	d
+REG_PKT_R_NBRT_SZ	include/ssv6200_aux.h	345;"	d
+REG_PKT_W_NBRT_HI	include/ssv6200_aux.h	339;"	d
+REG_PKT_W_NBRT_I_MSK	include/ssv6200_aux.h	337;"	d
+REG_PKT_W_NBRT_MSK	include/ssv6200_aux.h	336;"	d
+REG_PKT_W_NBRT_SFT	include/ssv6200_aux.h	338;"	d
+REG_PKT_W_NBRT_SZ	include/ssv6200_aux.h	340;"	d
+REG_PMU_WAKEUP	hwif/sdio/sdio_def.h	43;"	d
+REG_REG_IO_PORT_0	hwif/sdio/sdio_def.h	44;"	d
+REG_REG_IO_PORT_1	hwif/sdio/sdio_def.h	45;"	d
+REG_REG_IO_PORT_2	hwif/sdio/sdio_def.h	46;"	d
+REG_SDIO_DAT0_DELAY	hwif/sdio/sdio_def.h	42;"	d
+REG_SDIO_DAT1_DELAY	hwif/sdio/sdio_def.h	41;"	d
+REG_SDIO_DAT2_DELAY	hwif/sdio/sdio_def.h	40;"	d
+REG_SDIO_DAT3_DELAY	hwif/sdio/sdio_def.h	39;"	d
+REG_SDIO_FIFO_WR_THLD_0	hwif/sdio/sdio_def.h	35;"	d
+REG_SDIO_FIFO_WR_THLD_1	hwif/sdio/sdio_def.h	36;"	d
+REG_SDIO_TX_ALLOC_SHIFT	hwif/sdio/sdio_def.h	48;"	d
+REG_SDIO_TX_ALLOC_SIZE	hwif/sdio/sdio_def.h	47;"	d
+REG_SDIO_TX_ALLOC_STATE	hwif/sdio/sdio_def.h	49;"	d
+REG_SDIO_TX_INFORM_0	hwif/sdio/sdio_def.h	50;"	d
+REG_SDIO_TX_INFORM_1	hwif/sdio/sdio_def.h	51;"	d
+REG_SDIO_TX_INFORM_2	hwif/sdio/sdio_def.h	52;"	d
+REG_SD_READY_FLAG	hwif/sdio/sdio_def.h	28;"	d
+REMOVE_SPUR_PATCH	smac/hal/ssv6006c/turismo_common.h	3496;"	d
+REPORT_TX_STATUS_DIRECTLY	include/ssv_mod_conf.h	73;"	d
+REQ_LOCK_HI	include/ssv6200_aux.h	12544;"	d
+REQ_LOCK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34069;"	d
+REQ_LOCK_INT_EN_HI	include/ssv6200_aux.h	12569;"	d
+REQ_LOCK_INT_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34094;"	d
+REQ_LOCK_INT_EN_I_MSK	include/ssv6200_aux.h	12567;"	d
+REQ_LOCK_INT_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34092;"	d
+REQ_LOCK_INT_EN_MSK	include/ssv6200_aux.h	12566;"	d
+REQ_LOCK_INT_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34091;"	d
+REQ_LOCK_INT_EN_SFT	include/ssv6200_aux.h	12568;"	d
+REQ_LOCK_INT_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34093;"	d
+REQ_LOCK_INT_EN_SZ	include/ssv6200_aux.h	12570;"	d
+REQ_LOCK_INT_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34095;"	d
+REQ_LOCK_INT_HI	include/ssv6200_aux.h	12574;"	d
+REQ_LOCK_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34099;"	d
+REQ_LOCK_INT_I_MSK	include/ssv6200_aux.h	12572;"	d
+REQ_LOCK_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34097;"	d
+REQ_LOCK_INT_MSK	include/ssv6200_aux.h	12571;"	d
+REQ_LOCK_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34096;"	d
+REQ_LOCK_INT_SFT	include/ssv6200_aux.h	12573;"	d
+REQ_LOCK_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34098;"	d
+REQ_LOCK_INT_SZ	include/ssv6200_aux.h	12575;"	d
+REQ_LOCK_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34100;"	d
+REQ_LOCK_I_MSK	include/ssv6200_aux.h	12542;"	d
+REQ_LOCK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34067;"	d
+REQ_LOCK_MSK	include/ssv6200_aux.h	12541;"	d
+REQ_LOCK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34066;"	d
+REQ_LOCK_SFT	include/ssv6200_aux.h	12543;"	d
+REQ_LOCK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34068;"	d
+REQ_LOCK_SZ	include/ssv6200_aux.h	12545;"	d
+REQ_LOCK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34070;"	d
+REQ_NACK_CLR_HI	include/ssv6200_aux.h	17854;"	d
+REQ_NACK_CLR_I_MSK	include/ssv6200_aux.h	17852;"	d
+REQ_NACK_CLR_MSK	include/ssv6200_aux.h	17851;"	d
+REQ_NACK_CLR_SFT	include/ssv6200_aux.h	17853;"	d
+REQ_NACK_CLR_SZ	include/ssv6200_aux.h	17855;"	d
+REQ_PORNS_CHGEN_HI	include/ssv6200_aux.h	17874;"	d
+REQ_PORNS_CHGEN_I_MSK	include/ssv6200_aux.h	17872;"	d
+REQ_PORNS_CHGEN_MSK	include/ssv6200_aux.h	17871;"	d
+REQ_PORNS_CHGEN_SFT	include/ssv6200_aux.h	17873;"	d
+REQ_PORNS_CHGEN_SZ	include/ssv6200_aux.h	17875;"	d
+RESERVED	include/ssv6200_common.h	/^    u32 RESERVED[8];$/;"	m	struct:ssv6200_tx_desc	access:public
+RESET_N_CPUN10_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1259;"	d
+RESET_N_CPUN10_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1257;"	d
+RESET_N_CPUN10_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1256;"	d
+RESET_N_CPUN10_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1258;"	d
+RESET_N_CPUN10_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1260;"	d
+RESET_SMART_ICOMM	include/ssv6xxx_common.h	/^    RESET_SMART_ICOMM,$/;"	e	enum:ssv_smart_icomm_cmd
+RESET_SMART_ICOMM	smartlink/ssv_smartlink.h	/^    RESET_SMART_ICOMM,$/;"	e	enum:ssv_smart_icomm_cmd
+RESP_OUT_EDGE_HI	include/ssv6200_aux.h	3344;"	d
+RESP_OUT_EDGE_I_MSK	include/ssv6200_aux.h	3342;"	d
+RESP_OUT_EDGE_MSK	include/ssv6200_aux.h	3341;"	d
+RESP_OUT_EDGE_SFT	include/ssv6200_aux.h	3343;"	d
+RESP_OUT_EDGE_SZ	include/ssv6200_aux.h	3345;"	d
+RESULT	smartlink/qqlink-lib-mipsel/include/TXVoiceLink.h	/^enum RESULT$/;"	g
+RETRY_MAX	smac/dev.c	432;"	d	file:
+RF_BB_SW_RST_HI	include/ssv6200_aux.h	119;"	d
+RF_BB_SW_RST_I_MSK	include/ssv6200_aux.h	117;"	d
+RF_BB_SW_RST_MSK	include/ssv6200_aux.h	116;"	d
+RF_BB_SW_RST_SFT	include/ssv6200_aux.h	118;"	d
+RF_BB_SW_RST_SZ	include/ssv6200_aux.h	120;"	d
+RF_GEMINA	smac/hal/ssv6006c/ssv6006_mac.h	20;"	d
+RF_MODE_SHUTDOWN	smac/dev.h	39;"	d
+RF_MODE_STANDBY	smac/dev.h	40;"	d
+RF_MODE_TRX_EN	smac/dev.h	41;"	d
+RF_REG_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	130;"	d
+RF_REG_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	69;"	d
+RF_SETTING_SIZE	include/ssv6xxx_common.h	241;"	d
+RF_TURISMOA	smac/hal/ssv6006c/ssv6006_mac.h	21;"	d
+RG_11B_ACI_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30254;"	d
+RG_11B_ACI_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30252;"	d
+RG_11B_ACI_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30251;"	d
+RG_11B_ACI_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30253;"	d
+RG_11B_ACI_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30255;"	d
+RG_40M_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27164;"	d
+RG_40M_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27162;"	d
+RG_40M_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27161;"	d
+RG_40M_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27163;"	d
+RG_40M_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27165;"	d
+RG_5G_BYPASS_COARSE_FREQ_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32449;"	d
+RG_5G_BYPASS_COARSE_FREQ_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32447;"	d
+RG_5G_BYPASS_COARSE_FREQ_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32446;"	d
+RG_5G_BYPASS_COARSE_FREQ_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32448;"	d
+RG_5G_BYPASS_COARSE_FREQ_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32450;"	d
+RG_5G_CCFO_CNT_LMT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32444;"	d
+RG_5G_CCFO_CNT_LMT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32442;"	d
+RG_5G_CCFO_CNT_LMT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32441;"	d
+RG_5G_CCFO_CNT_LMT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32443;"	d
+RG_5G_CCFO_CNT_LMT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32445;"	d
+RG_5G_CCFO_GAIN_BY2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32454;"	d
+RG_5G_CCFO_GAIN_BY2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32452;"	d
+RG_5G_CCFO_GAIN_BY2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32451;"	d
+RG_5G_CCFO_GAIN_BY2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32453;"	d
+RG_5G_CCFO_GAIN_BY2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32455;"	d
+RG_5G_DC_RM_LEAKY_FACTOR_T1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30774;"	d
+RG_5G_DC_RM_LEAKY_FACTOR_T1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30772;"	d
+RG_5G_DC_RM_LEAKY_FACTOR_T1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30771;"	d
+RG_5G_DC_RM_LEAKY_FACTOR_T1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30773;"	d
+RG_5G_DC_RM_LEAKY_FACTOR_T1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30775;"	d
+RG_5G_DC_RM_LEAKY_FACTOR_T2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30769;"	d
+RG_5G_DC_RM_LEAKY_FACTOR_T2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30767;"	d
+RG_5G_DC_RM_LEAKY_FACTOR_T2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30766;"	d
+RG_5G_DC_RM_LEAKY_FACTOR_T2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30768;"	d
+RG_5G_DC_RM_LEAKY_FACTOR_T2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30770;"	d
+RG_5G_DC_RM_LEAKY_FACTOR_T3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30764;"	d
+RG_5G_DC_RM_LEAKY_FACTOR_T3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30762;"	d
+RG_5G_DC_RM_LEAKY_FACTOR_T3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30761;"	d
+RG_5G_DC_RM_LEAKY_FACTOR_T3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30763;"	d
+RG_5G_DC_RM_LEAKY_FACTOR_T3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30765;"	d
+RG_5G_EN_IREF_RX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25064;"	d
+RG_5G_EN_IREF_RX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25062;"	d
+RG_5G_EN_IREF_RX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25061;"	d
+RG_5G_EN_IREF_RX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25063;"	d
+RG_5G_EN_IREF_RX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25065;"	d
+RG_5G_EN_LDO_RX_FE_BYP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25019;"	d
+RG_5G_EN_LDO_RX_FE_BYP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25017;"	d
+RG_5G_EN_LDO_RX_FE_BYP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25016;"	d
+RG_5G_EN_LDO_RX_FE_BYP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25018;"	d
+RG_5G_EN_LDO_RX_FE_BYP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25020;"	d
+RG_5G_EN_LDO_RX_FE_FC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25069;"	d
+RG_5G_EN_LDO_RX_FE_FC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25067;"	d
+RG_5G_EN_LDO_RX_FE_FC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25066;"	d
+RG_5G_EN_LDO_RX_FE_FC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25068;"	d
+RG_5G_EN_LDO_RX_FE_FC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25070;"	d
+RG_5G_EN_LDO_RX_FE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25059;"	d
+RG_5G_EN_LDO_RX_FE_IQUP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25074;"	d
+RG_5G_EN_LDO_RX_FE_IQUP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25072;"	d
+RG_5G_EN_LDO_RX_FE_IQUP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25071;"	d
+RG_5G_EN_LDO_RX_FE_IQUP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25073;"	d
+RG_5G_EN_LDO_RX_FE_IQUP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25075;"	d
+RG_5G_EN_LDO_RX_FE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25057;"	d
+RG_5G_EN_LDO_RX_FE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25056;"	d
+RG_5G_EN_LDO_RX_FE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25058;"	d
+RG_5G_EN_LDO_RX_FE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25060;"	d
+RG_5G_EN_RX_DIV2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24904;"	d
+RG_5G_EN_RX_DIV2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24902;"	d
+RG_5G_EN_RX_DIV2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24901;"	d
+RG_5G_EN_RX_DIV2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24903;"	d
+RG_5G_EN_RX_DIV2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24905;"	d
+RG_5G_EN_RX_IQCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24994;"	d
+RG_5G_EN_RX_IQCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24992;"	d
+RG_5G_EN_RX_IQCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24991;"	d
+RG_5G_EN_RX_IQCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24993;"	d
+RG_5G_EN_RX_IQCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24995;"	d
+RG_5G_EN_RX_LNA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24884;"	d
+RG_5G_EN_RX_LNA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24882;"	d
+RG_5G_EN_RX_LNA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24881;"	d
+RG_5G_EN_RX_LNA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24883;"	d
+RG_5G_EN_RX_LNA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24885;"	d
+RG_5G_EN_RX_LOBUF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24914;"	d
+RG_5G_EN_RX_LOBUF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24912;"	d
+RG_5G_EN_RX_LOBUF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24911;"	d
+RG_5G_EN_RX_LOBUF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24913;"	d
+RG_5G_EN_RX_LOBUF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24915;"	d
+RG_5G_EN_RX_MIXER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24894;"	d
+RG_5G_EN_RX_MIXER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24892;"	d
+RG_5G_EN_RX_MIXER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24891;"	d
+RG_5G_EN_RX_MIXER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24893;"	d
+RG_5G_EN_RX_MIXER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24895;"	d
+RG_5G_EN_RX_TZ_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24924;"	d
+RG_5G_EN_RX_TZ_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24922;"	d
+RG_5G_EN_RX_TZ_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24921;"	d
+RG_5G_EN_RX_TZ_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24923;"	d
+RG_5G_EN_RX_TZ_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24925;"	d
+RG_5G_EN_TX_DIV2_BUF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24964;"	d
+RG_5G_EN_TX_DIV2_BUF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24962;"	d
+RG_5G_EN_TX_DIV2_BUF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24961;"	d
+RG_5G_EN_TX_DIV2_BUF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24963;"	d
+RG_5G_EN_TX_DIV2_BUF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24965;"	d
+RG_5G_EN_TX_DIV2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24954;"	d
+RG_5G_EN_TX_DIV2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24952;"	d
+RG_5G_EN_TX_DIV2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24951;"	d
+RG_5G_EN_TX_DIV2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24953;"	d
+RG_5G_EN_TX_DIV2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24955;"	d
+RG_5G_EN_TX_DPD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25004;"	d
+RG_5G_EN_TX_DPD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25002;"	d
+RG_5G_EN_TX_DPD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25001;"	d
+RG_5G_EN_TX_DPD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25003;"	d
+RG_5G_EN_TX_DPD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25005;"	d
+RG_5G_EN_TX_MOD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24944;"	d
+RG_5G_EN_TX_MOD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24942;"	d
+RG_5G_EN_TX_MOD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24941;"	d
+RG_5G_EN_TX_MOD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24943;"	d
+RG_5G_EN_TX_MOD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24945;"	d
+RG_5G_EN_TX_PA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24934;"	d
+RG_5G_EN_TX_PA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24932;"	d
+RG_5G_EN_TX_PA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24931;"	d
+RG_5G_EN_TX_PA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24933;"	d
+RG_5G_EN_TX_PA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24935;"	d
+RG_5G_EN_TX_SELF_MIXER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24984;"	d
+RG_5G_EN_TX_SELF_MIXER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24982;"	d
+RG_5G_EN_TX_SELF_MIXER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24981;"	d
+RG_5G_EN_TX_SELF_MIXER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24983;"	d
+RG_5G_EN_TX_SELF_MIXER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24985;"	d
+RG_5G_EN_TX_TRSW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24874;"	d
+RG_5G_EN_TX_TRSW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24872;"	d
+RG_5G_EN_TX_TRSW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24871;"	d
+RG_5G_EN_TX_TRSW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24873;"	d
+RG_5G_EN_TX_TRSW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24875;"	d
+RG_5G_EN_TX_TSSI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25009;"	d
+RG_5G_EN_TX_TSSI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25007;"	d
+RG_5G_EN_TX_TSSI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25006;"	d
+RG_5G_EN_TX_TSSI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25008;"	d
+RG_5G_EN_TX_TSSI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25010;"	d
+RG_5G_GM_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25104;"	d
+RG_5G_GM_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25102;"	d
+RG_5G_GM_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25101;"	d
+RG_5G_GM_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25103;"	d
+RG_5G_GM_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25105;"	d
+RG_5G_IDACAI_TZ0_COARSE0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26689;"	d
+RG_5G_IDACAI_TZ0_COARSE0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26687;"	d
+RG_5G_IDACAI_TZ0_COARSE0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26686;"	d
+RG_5G_IDACAI_TZ0_COARSE0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26688;"	d
+RG_5G_IDACAI_TZ0_COARSE0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26690;"	d
+RG_5G_IDACAI_TZ0_COARSE1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26679;"	d
+RG_5G_IDACAI_TZ0_COARSE1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26677;"	d
+RG_5G_IDACAI_TZ0_COARSE1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26676;"	d
+RG_5G_IDACAI_TZ0_COARSE1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26678;"	d
+RG_5G_IDACAI_TZ0_COARSE1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26680;"	d
+RG_5G_IDACAI_TZ0_COARSE2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26669;"	d
+RG_5G_IDACAI_TZ0_COARSE2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26667;"	d
+RG_5G_IDACAI_TZ0_COARSE2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26666;"	d
+RG_5G_IDACAI_TZ0_COARSE2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26668;"	d
+RG_5G_IDACAI_TZ0_COARSE2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26670;"	d
+RG_5G_IDACAI_TZ0_COARSE3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26659;"	d
+RG_5G_IDACAI_TZ0_COARSE3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26657;"	d
+RG_5G_IDACAI_TZ0_COARSE3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26656;"	d
+RG_5G_IDACAI_TZ0_COARSE3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26658;"	d
+RG_5G_IDACAI_TZ0_COARSE3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26660;"	d
+RG_5G_IDACAI_TZ0_COARSE4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26649;"	d
+RG_5G_IDACAI_TZ0_COARSE4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26647;"	d
+RG_5G_IDACAI_TZ0_COARSE4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26646;"	d
+RG_5G_IDACAI_TZ0_COARSE4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26648;"	d
+RG_5G_IDACAI_TZ0_COARSE4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26650;"	d
+RG_5G_IDACAI_TZ0_PGAG0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26479;"	d
+RG_5G_IDACAI_TZ0_PGAG0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26477;"	d
+RG_5G_IDACAI_TZ0_PGAG0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26476;"	d
+RG_5G_IDACAI_TZ0_PGAG0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26478;"	d
+RG_5G_IDACAI_TZ0_PGAG0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26480;"	d
+RG_5G_IDACAI_TZ0_PGAG10_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26379;"	d
+RG_5G_IDACAI_TZ0_PGAG10_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26377;"	d
+RG_5G_IDACAI_TZ0_PGAG10_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26376;"	d
+RG_5G_IDACAI_TZ0_PGAG10_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26378;"	d
+RG_5G_IDACAI_TZ0_PGAG10_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26380;"	d
+RG_5G_IDACAI_TZ0_PGAG11_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26369;"	d
+RG_5G_IDACAI_TZ0_PGAG11_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26367;"	d
+RG_5G_IDACAI_TZ0_PGAG11_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26366;"	d
+RG_5G_IDACAI_TZ0_PGAG11_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26368;"	d
+RG_5G_IDACAI_TZ0_PGAG11_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26370;"	d
+RG_5G_IDACAI_TZ0_PGAG12_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26359;"	d
+RG_5G_IDACAI_TZ0_PGAG12_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26357;"	d
+RG_5G_IDACAI_TZ0_PGAG12_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26356;"	d
+RG_5G_IDACAI_TZ0_PGAG12_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26358;"	d
+RG_5G_IDACAI_TZ0_PGAG12_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26360;"	d
+RG_5G_IDACAI_TZ0_PGAG13_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26349;"	d
+RG_5G_IDACAI_TZ0_PGAG13_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26347;"	d
+RG_5G_IDACAI_TZ0_PGAG13_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26346;"	d
+RG_5G_IDACAI_TZ0_PGAG13_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26348;"	d
+RG_5G_IDACAI_TZ0_PGAG13_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26350;"	d
+RG_5G_IDACAI_TZ0_PGAG14_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26339;"	d
+RG_5G_IDACAI_TZ0_PGAG14_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26337;"	d
+RG_5G_IDACAI_TZ0_PGAG14_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26336;"	d
+RG_5G_IDACAI_TZ0_PGAG14_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26338;"	d
+RG_5G_IDACAI_TZ0_PGAG14_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26340;"	d
+RG_5G_IDACAI_TZ0_PGAG15_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26329;"	d
+RG_5G_IDACAI_TZ0_PGAG15_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26327;"	d
+RG_5G_IDACAI_TZ0_PGAG15_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26326;"	d
+RG_5G_IDACAI_TZ0_PGAG15_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26328;"	d
+RG_5G_IDACAI_TZ0_PGAG15_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26330;"	d
+RG_5G_IDACAI_TZ0_PGAG1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26469;"	d
+RG_5G_IDACAI_TZ0_PGAG1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26467;"	d
+RG_5G_IDACAI_TZ0_PGAG1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26466;"	d
+RG_5G_IDACAI_TZ0_PGAG1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26468;"	d
+RG_5G_IDACAI_TZ0_PGAG1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26470;"	d
+RG_5G_IDACAI_TZ0_PGAG2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26459;"	d
+RG_5G_IDACAI_TZ0_PGAG2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26457;"	d
+RG_5G_IDACAI_TZ0_PGAG2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26456;"	d
+RG_5G_IDACAI_TZ0_PGAG2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26458;"	d
+RG_5G_IDACAI_TZ0_PGAG2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26460;"	d
+RG_5G_IDACAI_TZ0_PGAG3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26449;"	d
+RG_5G_IDACAI_TZ0_PGAG3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26447;"	d
+RG_5G_IDACAI_TZ0_PGAG3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26446;"	d
+RG_5G_IDACAI_TZ0_PGAG3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26448;"	d
+RG_5G_IDACAI_TZ0_PGAG3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26450;"	d
+RG_5G_IDACAI_TZ0_PGAG4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26439;"	d
+RG_5G_IDACAI_TZ0_PGAG4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26437;"	d
+RG_5G_IDACAI_TZ0_PGAG4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26436;"	d
+RG_5G_IDACAI_TZ0_PGAG4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26438;"	d
+RG_5G_IDACAI_TZ0_PGAG4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26440;"	d
+RG_5G_IDACAI_TZ0_PGAG5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26429;"	d
+RG_5G_IDACAI_TZ0_PGAG5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26427;"	d
+RG_5G_IDACAI_TZ0_PGAG5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26426;"	d
+RG_5G_IDACAI_TZ0_PGAG5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26428;"	d
+RG_5G_IDACAI_TZ0_PGAG5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26430;"	d
+RG_5G_IDACAI_TZ0_PGAG6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26419;"	d
+RG_5G_IDACAI_TZ0_PGAG6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26417;"	d
+RG_5G_IDACAI_TZ0_PGAG6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26416;"	d
+RG_5G_IDACAI_TZ0_PGAG6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26418;"	d
+RG_5G_IDACAI_TZ0_PGAG6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26420;"	d
+RG_5G_IDACAI_TZ0_PGAG7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26409;"	d
+RG_5G_IDACAI_TZ0_PGAG7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26407;"	d
+RG_5G_IDACAI_TZ0_PGAG7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26406;"	d
+RG_5G_IDACAI_TZ0_PGAG7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26408;"	d
+RG_5G_IDACAI_TZ0_PGAG7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26410;"	d
+RG_5G_IDACAI_TZ0_PGAG8_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26399;"	d
+RG_5G_IDACAI_TZ0_PGAG8_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26397;"	d
+RG_5G_IDACAI_TZ0_PGAG8_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26396;"	d
+RG_5G_IDACAI_TZ0_PGAG8_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26398;"	d
+RG_5G_IDACAI_TZ0_PGAG8_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26400;"	d
+RG_5G_IDACAI_TZ0_PGAG9_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26389;"	d
+RG_5G_IDACAI_TZ0_PGAG9_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26387;"	d
+RG_5G_IDACAI_TZ0_PGAG9_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26386;"	d
+RG_5G_IDACAI_TZ0_PGAG9_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26388;"	d
+RG_5G_IDACAI_TZ0_PGAG9_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26390;"	d
+RG_5G_IDACAI_TZ1_COARSE0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26739;"	d
+RG_5G_IDACAI_TZ1_COARSE0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26737;"	d
+RG_5G_IDACAI_TZ1_COARSE0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26736;"	d
+RG_5G_IDACAI_TZ1_COARSE0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26738;"	d
+RG_5G_IDACAI_TZ1_COARSE0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26740;"	d
+RG_5G_IDACAI_TZ1_COARSE1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26729;"	d
+RG_5G_IDACAI_TZ1_COARSE1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26727;"	d
+RG_5G_IDACAI_TZ1_COARSE1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26726;"	d
+RG_5G_IDACAI_TZ1_COARSE1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26728;"	d
+RG_5G_IDACAI_TZ1_COARSE1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26730;"	d
+RG_5G_IDACAI_TZ1_COARSE2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26719;"	d
+RG_5G_IDACAI_TZ1_COARSE2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26717;"	d
+RG_5G_IDACAI_TZ1_COARSE2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26716;"	d
+RG_5G_IDACAI_TZ1_COARSE2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26718;"	d
+RG_5G_IDACAI_TZ1_COARSE2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26720;"	d
+RG_5G_IDACAI_TZ1_COARSE3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26709;"	d
+RG_5G_IDACAI_TZ1_COARSE3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26707;"	d
+RG_5G_IDACAI_TZ1_COARSE3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26706;"	d
+RG_5G_IDACAI_TZ1_COARSE3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26708;"	d
+RG_5G_IDACAI_TZ1_COARSE3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26710;"	d
+RG_5G_IDACAI_TZ1_COARSE4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26699;"	d
+RG_5G_IDACAI_TZ1_COARSE4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26697;"	d
+RG_5G_IDACAI_TZ1_COARSE4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26696;"	d
+RG_5G_IDACAI_TZ1_COARSE4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26698;"	d
+RG_5G_IDACAI_TZ1_COARSE4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26700;"	d
+RG_5G_IDACAI_TZ1_PGAG0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26639;"	d
+RG_5G_IDACAI_TZ1_PGAG0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26637;"	d
+RG_5G_IDACAI_TZ1_PGAG0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26636;"	d
+RG_5G_IDACAI_TZ1_PGAG0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26638;"	d
+RG_5G_IDACAI_TZ1_PGAG0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26640;"	d
+RG_5G_IDACAI_TZ1_PGAG10_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26539;"	d
+RG_5G_IDACAI_TZ1_PGAG10_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26537;"	d
+RG_5G_IDACAI_TZ1_PGAG10_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26536;"	d
+RG_5G_IDACAI_TZ1_PGAG10_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26538;"	d
+RG_5G_IDACAI_TZ1_PGAG10_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26540;"	d
+RG_5G_IDACAI_TZ1_PGAG11_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26529;"	d
+RG_5G_IDACAI_TZ1_PGAG11_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26527;"	d
+RG_5G_IDACAI_TZ1_PGAG11_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26526;"	d
+RG_5G_IDACAI_TZ1_PGAG11_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26528;"	d
+RG_5G_IDACAI_TZ1_PGAG11_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26530;"	d
+RG_5G_IDACAI_TZ1_PGAG12_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26519;"	d
+RG_5G_IDACAI_TZ1_PGAG12_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26517;"	d
+RG_5G_IDACAI_TZ1_PGAG12_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26516;"	d
+RG_5G_IDACAI_TZ1_PGAG12_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26518;"	d
+RG_5G_IDACAI_TZ1_PGAG12_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26520;"	d
+RG_5G_IDACAI_TZ1_PGAG13_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26509;"	d
+RG_5G_IDACAI_TZ1_PGAG13_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26507;"	d
+RG_5G_IDACAI_TZ1_PGAG13_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26506;"	d
+RG_5G_IDACAI_TZ1_PGAG13_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26508;"	d
+RG_5G_IDACAI_TZ1_PGAG13_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26510;"	d
+RG_5G_IDACAI_TZ1_PGAG14_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26499;"	d
+RG_5G_IDACAI_TZ1_PGAG14_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26497;"	d
+RG_5G_IDACAI_TZ1_PGAG14_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26496;"	d
+RG_5G_IDACAI_TZ1_PGAG14_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26498;"	d
+RG_5G_IDACAI_TZ1_PGAG14_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26500;"	d
+RG_5G_IDACAI_TZ1_PGAG15_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26489;"	d
+RG_5G_IDACAI_TZ1_PGAG15_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26487;"	d
+RG_5G_IDACAI_TZ1_PGAG15_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26486;"	d
+RG_5G_IDACAI_TZ1_PGAG15_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26488;"	d
+RG_5G_IDACAI_TZ1_PGAG15_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26490;"	d
+RG_5G_IDACAI_TZ1_PGAG1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26629;"	d
+RG_5G_IDACAI_TZ1_PGAG1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26627;"	d
+RG_5G_IDACAI_TZ1_PGAG1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26626;"	d
+RG_5G_IDACAI_TZ1_PGAG1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26628;"	d
+RG_5G_IDACAI_TZ1_PGAG1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26630;"	d
+RG_5G_IDACAI_TZ1_PGAG2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26619;"	d
+RG_5G_IDACAI_TZ1_PGAG2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26617;"	d
+RG_5G_IDACAI_TZ1_PGAG2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26616;"	d
+RG_5G_IDACAI_TZ1_PGAG2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26618;"	d
+RG_5G_IDACAI_TZ1_PGAG2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26620;"	d
+RG_5G_IDACAI_TZ1_PGAG3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26609;"	d
+RG_5G_IDACAI_TZ1_PGAG3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26607;"	d
+RG_5G_IDACAI_TZ1_PGAG3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26606;"	d
+RG_5G_IDACAI_TZ1_PGAG3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26608;"	d
+RG_5G_IDACAI_TZ1_PGAG3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26610;"	d
+RG_5G_IDACAI_TZ1_PGAG4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26599;"	d
+RG_5G_IDACAI_TZ1_PGAG4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26597;"	d
+RG_5G_IDACAI_TZ1_PGAG4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26596;"	d
+RG_5G_IDACAI_TZ1_PGAG4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26598;"	d
+RG_5G_IDACAI_TZ1_PGAG4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26600;"	d
+RG_5G_IDACAI_TZ1_PGAG5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26589;"	d
+RG_5G_IDACAI_TZ1_PGAG5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26587;"	d
+RG_5G_IDACAI_TZ1_PGAG5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26586;"	d
+RG_5G_IDACAI_TZ1_PGAG5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26588;"	d
+RG_5G_IDACAI_TZ1_PGAG5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26590;"	d
+RG_5G_IDACAI_TZ1_PGAG6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26579;"	d
+RG_5G_IDACAI_TZ1_PGAG6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26577;"	d
+RG_5G_IDACAI_TZ1_PGAG6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26576;"	d
+RG_5G_IDACAI_TZ1_PGAG6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26578;"	d
+RG_5G_IDACAI_TZ1_PGAG6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26580;"	d
+RG_5G_IDACAI_TZ1_PGAG7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26569;"	d
+RG_5G_IDACAI_TZ1_PGAG7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26567;"	d
+RG_5G_IDACAI_TZ1_PGAG7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26566;"	d
+RG_5G_IDACAI_TZ1_PGAG7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26568;"	d
+RG_5G_IDACAI_TZ1_PGAG7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26570;"	d
+RG_5G_IDACAI_TZ1_PGAG8_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26559;"	d
+RG_5G_IDACAI_TZ1_PGAG8_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26557;"	d
+RG_5G_IDACAI_TZ1_PGAG8_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26556;"	d
+RG_5G_IDACAI_TZ1_PGAG8_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26558;"	d
+RG_5G_IDACAI_TZ1_PGAG8_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26560;"	d
+RG_5G_IDACAI_TZ1_PGAG9_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26549;"	d
+RG_5G_IDACAI_TZ1_PGAG9_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26547;"	d
+RG_5G_IDACAI_TZ1_PGAG9_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26546;"	d
+RG_5G_IDACAI_TZ1_PGAG9_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26548;"	d
+RG_5G_IDACAI_TZ1_PGAG9_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26550;"	d
+RG_5G_IDACAQ_TZ0_COARSE0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26694;"	d
+RG_5G_IDACAQ_TZ0_COARSE0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26692;"	d
+RG_5G_IDACAQ_TZ0_COARSE0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26691;"	d
+RG_5G_IDACAQ_TZ0_COARSE0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26693;"	d
+RG_5G_IDACAQ_TZ0_COARSE0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26695;"	d
+RG_5G_IDACAQ_TZ0_COARSE1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26684;"	d
+RG_5G_IDACAQ_TZ0_COARSE1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26682;"	d
+RG_5G_IDACAQ_TZ0_COARSE1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26681;"	d
+RG_5G_IDACAQ_TZ0_COARSE1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26683;"	d
+RG_5G_IDACAQ_TZ0_COARSE1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26685;"	d
+RG_5G_IDACAQ_TZ0_COARSE2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26674;"	d
+RG_5G_IDACAQ_TZ0_COARSE2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26672;"	d
+RG_5G_IDACAQ_TZ0_COARSE2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26671;"	d
+RG_5G_IDACAQ_TZ0_COARSE2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26673;"	d
+RG_5G_IDACAQ_TZ0_COARSE2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26675;"	d
+RG_5G_IDACAQ_TZ0_COARSE3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26664;"	d
+RG_5G_IDACAQ_TZ0_COARSE3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26662;"	d
+RG_5G_IDACAQ_TZ0_COARSE3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26661;"	d
+RG_5G_IDACAQ_TZ0_COARSE3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26663;"	d
+RG_5G_IDACAQ_TZ0_COARSE3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26665;"	d
+RG_5G_IDACAQ_TZ0_COARSE4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26654;"	d
+RG_5G_IDACAQ_TZ0_COARSE4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26652;"	d
+RG_5G_IDACAQ_TZ0_COARSE4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26651;"	d
+RG_5G_IDACAQ_TZ0_COARSE4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26653;"	d
+RG_5G_IDACAQ_TZ0_COARSE4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26655;"	d
+RG_5G_IDACAQ_TZ0_PGAG0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26484;"	d
+RG_5G_IDACAQ_TZ0_PGAG0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26482;"	d
+RG_5G_IDACAQ_TZ0_PGAG0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26481;"	d
+RG_5G_IDACAQ_TZ0_PGAG0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26483;"	d
+RG_5G_IDACAQ_TZ0_PGAG0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26485;"	d
+RG_5G_IDACAQ_TZ0_PGAG10_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26384;"	d
+RG_5G_IDACAQ_TZ0_PGAG10_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26382;"	d
+RG_5G_IDACAQ_TZ0_PGAG10_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26381;"	d
+RG_5G_IDACAQ_TZ0_PGAG10_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26383;"	d
+RG_5G_IDACAQ_TZ0_PGAG10_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26385;"	d
+RG_5G_IDACAQ_TZ0_PGAG11_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26374;"	d
+RG_5G_IDACAQ_TZ0_PGAG11_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26372;"	d
+RG_5G_IDACAQ_TZ0_PGAG11_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26371;"	d
+RG_5G_IDACAQ_TZ0_PGAG11_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26373;"	d
+RG_5G_IDACAQ_TZ0_PGAG11_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26375;"	d
+RG_5G_IDACAQ_TZ0_PGAG12_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26364;"	d
+RG_5G_IDACAQ_TZ0_PGAG12_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26362;"	d
+RG_5G_IDACAQ_TZ0_PGAG12_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26361;"	d
+RG_5G_IDACAQ_TZ0_PGAG12_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26363;"	d
+RG_5G_IDACAQ_TZ0_PGAG12_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26365;"	d
+RG_5G_IDACAQ_TZ0_PGAG13_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26354;"	d
+RG_5G_IDACAQ_TZ0_PGAG13_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26352;"	d
+RG_5G_IDACAQ_TZ0_PGAG13_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26351;"	d
+RG_5G_IDACAQ_TZ0_PGAG13_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26353;"	d
+RG_5G_IDACAQ_TZ0_PGAG13_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26355;"	d
+RG_5G_IDACAQ_TZ0_PGAG14_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26344;"	d
+RG_5G_IDACAQ_TZ0_PGAG14_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26342;"	d
+RG_5G_IDACAQ_TZ0_PGAG14_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26341;"	d
+RG_5G_IDACAQ_TZ0_PGAG14_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26343;"	d
+RG_5G_IDACAQ_TZ0_PGAG14_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26345;"	d
+RG_5G_IDACAQ_TZ0_PGAG15_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26334;"	d
+RG_5G_IDACAQ_TZ0_PGAG15_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26332;"	d
+RG_5G_IDACAQ_TZ0_PGAG15_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26331;"	d
+RG_5G_IDACAQ_TZ0_PGAG15_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26333;"	d
+RG_5G_IDACAQ_TZ0_PGAG15_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26335;"	d
+RG_5G_IDACAQ_TZ0_PGAG1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26474;"	d
+RG_5G_IDACAQ_TZ0_PGAG1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26472;"	d
+RG_5G_IDACAQ_TZ0_PGAG1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26471;"	d
+RG_5G_IDACAQ_TZ0_PGAG1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26473;"	d
+RG_5G_IDACAQ_TZ0_PGAG1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26475;"	d
+RG_5G_IDACAQ_TZ0_PGAG2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26464;"	d
+RG_5G_IDACAQ_TZ0_PGAG2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26462;"	d
+RG_5G_IDACAQ_TZ0_PGAG2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26461;"	d
+RG_5G_IDACAQ_TZ0_PGAG2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26463;"	d
+RG_5G_IDACAQ_TZ0_PGAG2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26465;"	d
+RG_5G_IDACAQ_TZ0_PGAG3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26454;"	d
+RG_5G_IDACAQ_TZ0_PGAG3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26452;"	d
+RG_5G_IDACAQ_TZ0_PGAG3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26451;"	d
+RG_5G_IDACAQ_TZ0_PGAG3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26453;"	d
+RG_5G_IDACAQ_TZ0_PGAG3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26455;"	d
+RG_5G_IDACAQ_TZ0_PGAG4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26444;"	d
+RG_5G_IDACAQ_TZ0_PGAG4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26442;"	d
+RG_5G_IDACAQ_TZ0_PGAG4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26441;"	d
+RG_5G_IDACAQ_TZ0_PGAG4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26443;"	d
+RG_5G_IDACAQ_TZ0_PGAG4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26445;"	d
+RG_5G_IDACAQ_TZ0_PGAG5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26434;"	d
+RG_5G_IDACAQ_TZ0_PGAG5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26432;"	d
+RG_5G_IDACAQ_TZ0_PGAG5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26431;"	d
+RG_5G_IDACAQ_TZ0_PGAG5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26433;"	d
+RG_5G_IDACAQ_TZ0_PGAG5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26435;"	d
+RG_5G_IDACAQ_TZ0_PGAG6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26424;"	d
+RG_5G_IDACAQ_TZ0_PGAG6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26422;"	d
+RG_5G_IDACAQ_TZ0_PGAG6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26421;"	d
+RG_5G_IDACAQ_TZ0_PGAG6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26423;"	d
+RG_5G_IDACAQ_TZ0_PGAG6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26425;"	d
+RG_5G_IDACAQ_TZ0_PGAG7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26414;"	d
+RG_5G_IDACAQ_TZ0_PGAG7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26412;"	d
+RG_5G_IDACAQ_TZ0_PGAG7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26411;"	d
+RG_5G_IDACAQ_TZ0_PGAG7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26413;"	d
+RG_5G_IDACAQ_TZ0_PGAG7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26415;"	d
+RG_5G_IDACAQ_TZ0_PGAG8_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26404;"	d
+RG_5G_IDACAQ_TZ0_PGAG8_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26402;"	d
+RG_5G_IDACAQ_TZ0_PGAG8_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26401;"	d
+RG_5G_IDACAQ_TZ0_PGAG8_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26403;"	d
+RG_5G_IDACAQ_TZ0_PGAG8_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26405;"	d
+RG_5G_IDACAQ_TZ0_PGAG9_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26394;"	d
+RG_5G_IDACAQ_TZ0_PGAG9_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26392;"	d
+RG_5G_IDACAQ_TZ0_PGAG9_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26391;"	d
+RG_5G_IDACAQ_TZ0_PGAG9_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26393;"	d
+RG_5G_IDACAQ_TZ0_PGAG9_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26395;"	d
+RG_5G_IDACAQ_TZ1_COARSE0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26744;"	d
+RG_5G_IDACAQ_TZ1_COARSE0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26742;"	d
+RG_5G_IDACAQ_TZ1_COARSE0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26741;"	d
+RG_5G_IDACAQ_TZ1_COARSE0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26743;"	d
+RG_5G_IDACAQ_TZ1_COARSE0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26745;"	d
+RG_5G_IDACAQ_TZ1_COARSE1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26734;"	d
+RG_5G_IDACAQ_TZ1_COARSE1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26732;"	d
+RG_5G_IDACAQ_TZ1_COARSE1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26731;"	d
+RG_5G_IDACAQ_TZ1_COARSE1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26733;"	d
+RG_5G_IDACAQ_TZ1_COARSE1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26735;"	d
+RG_5G_IDACAQ_TZ1_COARSE2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26724;"	d
+RG_5G_IDACAQ_TZ1_COARSE2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26722;"	d
+RG_5G_IDACAQ_TZ1_COARSE2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26721;"	d
+RG_5G_IDACAQ_TZ1_COARSE2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26723;"	d
+RG_5G_IDACAQ_TZ1_COARSE2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26725;"	d
+RG_5G_IDACAQ_TZ1_COARSE3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26714;"	d
+RG_5G_IDACAQ_TZ1_COARSE3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26712;"	d
+RG_5G_IDACAQ_TZ1_COARSE3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26711;"	d
+RG_5G_IDACAQ_TZ1_COARSE3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26713;"	d
+RG_5G_IDACAQ_TZ1_COARSE3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26715;"	d
+RG_5G_IDACAQ_TZ1_COARSE4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26704;"	d
+RG_5G_IDACAQ_TZ1_COARSE4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26702;"	d
+RG_5G_IDACAQ_TZ1_COARSE4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26701;"	d
+RG_5G_IDACAQ_TZ1_COARSE4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26703;"	d
+RG_5G_IDACAQ_TZ1_COARSE4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26705;"	d
+RG_5G_IDACAQ_TZ1_PGAG0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26644;"	d
+RG_5G_IDACAQ_TZ1_PGAG0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26642;"	d
+RG_5G_IDACAQ_TZ1_PGAG0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26641;"	d
+RG_5G_IDACAQ_TZ1_PGAG0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26643;"	d
+RG_5G_IDACAQ_TZ1_PGAG0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26645;"	d
+RG_5G_IDACAQ_TZ1_PGAG10_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26544;"	d
+RG_5G_IDACAQ_TZ1_PGAG10_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26542;"	d
+RG_5G_IDACAQ_TZ1_PGAG10_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26541;"	d
+RG_5G_IDACAQ_TZ1_PGAG10_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26543;"	d
+RG_5G_IDACAQ_TZ1_PGAG10_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26545;"	d
+RG_5G_IDACAQ_TZ1_PGAG11_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26534;"	d
+RG_5G_IDACAQ_TZ1_PGAG11_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26532;"	d
+RG_5G_IDACAQ_TZ1_PGAG11_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26531;"	d
+RG_5G_IDACAQ_TZ1_PGAG11_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26533;"	d
+RG_5G_IDACAQ_TZ1_PGAG11_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26535;"	d
+RG_5G_IDACAQ_TZ1_PGAG12_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26524;"	d
+RG_5G_IDACAQ_TZ1_PGAG12_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26522;"	d
+RG_5G_IDACAQ_TZ1_PGAG12_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26521;"	d
+RG_5G_IDACAQ_TZ1_PGAG12_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26523;"	d
+RG_5G_IDACAQ_TZ1_PGAG12_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26525;"	d
+RG_5G_IDACAQ_TZ1_PGAG13_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26514;"	d
+RG_5G_IDACAQ_TZ1_PGAG13_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26512;"	d
+RG_5G_IDACAQ_TZ1_PGAG13_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26511;"	d
+RG_5G_IDACAQ_TZ1_PGAG13_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26513;"	d
+RG_5G_IDACAQ_TZ1_PGAG13_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26515;"	d
+RG_5G_IDACAQ_TZ1_PGAG14_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26504;"	d
+RG_5G_IDACAQ_TZ1_PGAG14_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26502;"	d
+RG_5G_IDACAQ_TZ1_PGAG14_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26501;"	d
+RG_5G_IDACAQ_TZ1_PGAG14_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26503;"	d
+RG_5G_IDACAQ_TZ1_PGAG14_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26505;"	d
+RG_5G_IDACAQ_TZ1_PGAG15_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26494;"	d
+RG_5G_IDACAQ_TZ1_PGAG15_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26492;"	d
+RG_5G_IDACAQ_TZ1_PGAG15_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26491;"	d
+RG_5G_IDACAQ_TZ1_PGAG15_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26493;"	d
+RG_5G_IDACAQ_TZ1_PGAG15_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26495;"	d
+RG_5G_IDACAQ_TZ1_PGAG1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26634;"	d
+RG_5G_IDACAQ_TZ1_PGAG1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26632;"	d
+RG_5G_IDACAQ_TZ1_PGAG1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26631;"	d
+RG_5G_IDACAQ_TZ1_PGAG1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26633;"	d
+RG_5G_IDACAQ_TZ1_PGAG1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26635;"	d
+RG_5G_IDACAQ_TZ1_PGAG2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26624;"	d
+RG_5G_IDACAQ_TZ1_PGAG2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26622;"	d
+RG_5G_IDACAQ_TZ1_PGAG2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26621;"	d
+RG_5G_IDACAQ_TZ1_PGAG2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26623;"	d
+RG_5G_IDACAQ_TZ1_PGAG2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26625;"	d
+RG_5G_IDACAQ_TZ1_PGAG3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26614;"	d
+RG_5G_IDACAQ_TZ1_PGAG3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26612;"	d
+RG_5G_IDACAQ_TZ1_PGAG3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26611;"	d
+RG_5G_IDACAQ_TZ1_PGAG3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26613;"	d
+RG_5G_IDACAQ_TZ1_PGAG3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26615;"	d
+RG_5G_IDACAQ_TZ1_PGAG4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26604;"	d
+RG_5G_IDACAQ_TZ1_PGAG4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26602;"	d
+RG_5G_IDACAQ_TZ1_PGAG4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26601;"	d
+RG_5G_IDACAQ_TZ1_PGAG4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26603;"	d
+RG_5G_IDACAQ_TZ1_PGAG4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26605;"	d
+RG_5G_IDACAQ_TZ1_PGAG5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26594;"	d
+RG_5G_IDACAQ_TZ1_PGAG5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26592;"	d
+RG_5G_IDACAQ_TZ1_PGAG5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26591;"	d
+RG_5G_IDACAQ_TZ1_PGAG5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26593;"	d
+RG_5G_IDACAQ_TZ1_PGAG5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26595;"	d
+RG_5G_IDACAQ_TZ1_PGAG6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26584;"	d
+RG_5G_IDACAQ_TZ1_PGAG6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26582;"	d
+RG_5G_IDACAQ_TZ1_PGAG6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26581;"	d
+RG_5G_IDACAQ_TZ1_PGAG6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26583;"	d
+RG_5G_IDACAQ_TZ1_PGAG6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26585;"	d
+RG_5G_IDACAQ_TZ1_PGAG7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26574;"	d
+RG_5G_IDACAQ_TZ1_PGAG7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26572;"	d
+RG_5G_IDACAQ_TZ1_PGAG7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26571;"	d
+RG_5G_IDACAQ_TZ1_PGAG7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26573;"	d
+RG_5G_IDACAQ_TZ1_PGAG7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26575;"	d
+RG_5G_IDACAQ_TZ1_PGAG8_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26564;"	d
+RG_5G_IDACAQ_TZ1_PGAG8_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26562;"	d
+RG_5G_IDACAQ_TZ1_PGAG8_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26561;"	d
+RG_5G_IDACAQ_TZ1_PGAG8_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26563;"	d
+RG_5G_IDACAQ_TZ1_PGAG8_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26565;"	d
+RG_5G_IDACAQ_TZ1_PGAG9_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26554;"	d
+RG_5G_IDACAQ_TZ1_PGAG9_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26552;"	d
+RG_5G_IDACAQ_TZ1_PGAG9_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26551;"	d
+RG_5G_IDACAQ_TZ1_PGAG9_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26553;"	d
+RG_5G_IDACAQ_TZ1_PGAG9_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26555;"	d
+RG_5G_LDO_LEVEL_RX_FE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25014;"	d
+RG_5G_LDO_LEVEL_RX_FE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25012;"	d
+RG_5G_LDO_LEVEL_RX_FE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25011;"	d
+RG_5G_LDO_LEVEL_RX_FE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25013;"	d
+RG_5G_LDO_LEVEL_RX_FE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25015;"	d
+RG_5G_PABIAS_2X_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25229;"	d
+RG_5G_PABIAS_2X_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25227;"	d
+RG_5G_PABIAS_2X_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25226;"	d
+RG_5G_PABIAS_2X_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25228;"	d
+RG_5G_PABIAS_2X_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25230;"	d
+RG_5G_PABIAS_CTRL_F0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27024;"	d
+RG_5G_PABIAS_CTRL_F0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27022;"	d
+RG_5G_PABIAS_CTRL_F0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27021;"	d
+RG_5G_PABIAS_CTRL_F0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27023;"	d
+RG_5G_PABIAS_CTRL_F0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27025;"	d
+RG_5G_PABIAS_CTRL_F1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27049;"	d
+RG_5G_PABIAS_CTRL_F1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27047;"	d
+RG_5G_PABIAS_CTRL_F1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27046;"	d
+RG_5G_PABIAS_CTRL_F1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27048;"	d
+RG_5G_PABIAS_CTRL_F1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27050;"	d
+RG_5G_PABIAS_CTRL_F2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27074;"	d
+RG_5G_PABIAS_CTRL_F2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27072;"	d
+RG_5G_PABIAS_CTRL_F2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27071;"	d
+RG_5G_PABIAS_CTRL_F2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27073;"	d
+RG_5G_PABIAS_CTRL_F2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27075;"	d
+RG_5G_PABIAS_CTRL_F3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27099;"	d
+RG_5G_PABIAS_CTRL_F3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27097;"	d
+RG_5G_PABIAS_CTRL_F3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27096;"	d
+RG_5G_PABIAS_CTRL_F3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27098;"	d
+RG_5G_PABIAS_CTRL_F3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27100;"	d
+RG_5G_PABIAS_CTRL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25209;"	d
+RG_5G_PABIAS_CTRL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25207;"	d
+RG_5G_PABIAS_CTRL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25206;"	d
+RG_5G_PABIAS_CTRL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25208;"	d
+RG_5G_PABIAS_CTRL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25210;"	d
+RG_5G_PACELL_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25204;"	d
+RG_5G_PACELL_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25202;"	d
+RG_5G_PACELL_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25201;"	d
+RG_5G_PACELL_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25203;"	d
+RG_5G_PACELL_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25205;"	d
+RG_5G_PGAG_DPDCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26869;"	d
+RG_5G_PGAG_DPDCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26867;"	d
+RG_5G_PGAG_DPDCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26866;"	d
+RG_5G_PGAG_DPDCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26868;"	d
+RG_5G_PGAG_DPDCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26870;"	d
+RG_5G_PGAG_RCCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26844;"	d
+RG_5G_PGAG_RCCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26842;"	d
+RG_5G_PGAG_RCCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26841;"	d
+RG_5G_PGAG_RCCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26843;"	d
+RG_5G_PGAG_RCCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26845;"	d
+RG_5G_PGAG_RXIQCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26854;"	d
+RG_5G_PGAG_RXIQCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26852;"	d
+RG_5G_PGAG_RXIQCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26851;"	d
+RG_5G_PGAG_RXIQCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26853;"	d
+RG_5G_PGAG_RXIQCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26855;"	d
+RG_5G_PGAG_TXCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26834;"	d
+RG_5G_PGAG_TXCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26832;"	d
+RG_5G_PGAG_TXCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26831;"	d
+RG_5G_PGAG_TXCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26833;"	d
+RG_5G_PGAG_TXCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26835;"	d
+RG_5G_RFG_DPDCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26864;"	d
+RG_5G_RFG_DPDCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26862;"	d
+RG_5G_RFG_DPDCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26861;"	d
+RG_5G_RFG_DPDCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26863;"	d
+RG_5G_RFG_DPDCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26865;"	d
+RG_5G_RFG_RXIQCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26849;"	d
+RG_5G_RFG_RXIQCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26847;"	d
+RG_5G_RFG_RXIQCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26846;"	d
+RG_5G_RFG_RXIQCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26848;"	d
+RG_5G_RFG_RXIQCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26850;"	d
+RG_5G_RXRF_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26769;"	d
+RG_5G_RXRF_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26767;"	d
+RG_5G_RXRF_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26766;"	d
+RG_5G_RXRF_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26768;"	d
+RG_5G_RXRF_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26770;"	d
+RG_5G_RXRF_R2T_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26809;"	d
+RG_5G_RXRF_R2T_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26807;"	d
+RG_5G_RXRF_R2T_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26806;"	d
+RG_5G_RXRF_R2T_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26808;"	d
+RG_5G_RXRF_R2T_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26810;"	d
+RG_5G_RXRF_T2R_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26789;"	d
+RG_5G_RXRF_T2R_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26787;"	d
+RG_5G_RXRF_T2R_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26786;"	d
+RG_5G_RXRF_T2R_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26788;"	d
+RG_5G_RXRF_T2R_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26790;"	d
+RG_5G_RX_ADC_CLOAD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25174;"	d
+RG_5G_RX_ADC_CLOAD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25172;"	d
+RG_5G_RX_ADC_CLOAD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25171;"	d
+RG_5G_RX_ADC_CLOAD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25173;"	d
+RG_5G_RX_ADC_CLOAD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25175;"	d
+RG_5G_RX_ADC_ICMP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25164;"	d
+RG_5G_RX_ADC_ICMP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25162;"	d
+RG_5G_RX_ADC_ICMP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25161;"	d
+RG_5G_RX_ADC_ICMP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25163;"	d
+RG_5G_RX_ADC_ICMP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25165;"	d
+RG_5G_RX_ADC_PSW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25179;"	d
+RG_5G_RX_ADC_PSW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25177;"	d
+RG_5G_RX_ADC_PSW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25176;"	d
+RG_5G_RX_ADC_PSW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25178;"	d
+RG_5G_RX_ADC_PSW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25180;"	d
+RG_5G_RX_ADC_VCMI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25169;"	d
+RG_5G_RX_ADC_VCMI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25167;"	d
+RG_5G_RX_ADC_VCMI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25166;"	d
+RG_5G_RX_ADC_VCMI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25168;"	d
+RG_5G_RX_ADC_VCMI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25170;"	d
+RG_5G_RX_DCCAL_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26814;"	d
+RG_5G_RX_DCCAL_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26812;"	d
+RG_5G_RX_DCCAL_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26811;"	d
+RG_5G_RX_DCCAL_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26813;"	d
+RG_5G_RX_DCCAL_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26815;"	d
+RG_5G_RX_DIV2_BUF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25109;"	d
+RG_5G_RX_DIV2_BUF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25107;"	d
+RG_5G_RX_DIV2_BUF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25106;"	d
+RG_5G_RX_DIV2_BUF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25108;"	d
+RG_5G_RX_DIV2_BUF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25110;"	d
+RG_5G_RX_DIV2_CML_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25114;"	d
+RG_5G_RX_DIV2_CML_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25112;"	d
+RG_5G_RX_DIV2_CML_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25111;"	d
+RG_5G_RX_DIV2_CML_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25113;"	d
+RG_5G_RX_DIV2_CML_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25115;"	d
+RG_5G_RX_DIV2_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24899;"	d
+RG_5G_RX_DIV2_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24897;"	d
+RG_5G_RX_DIV2_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24896;"	d
+RG_5G_RX_DIV2_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24898;"	d
+RG_5G_RX_DIV2_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24900;"	d
+RG_5G_RX_DIV_CMLISEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25119;"	d
+RG_5G_RX_DIV_CMLISEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25117;"	d
+RG_5G_RX_DIV_CMLISEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25116;"	d
+RG_5G_RX_DIV_CMLISEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25118;"	d
+RG_5G_RX_DIV_CMLISEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25120;"	d
+RG_5G_RX_DIV_PREBUFS2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25124;"	d
+RG_5G_RX_DIV_PREBUFS2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25122;"	d
+RG_5G_RX_DIV_PREBUFS2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25121;"	d
+RG_5G_RX_DIV_PREBUFS2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25123;"	d
+RG_5G_RX_DIV_PREBUFS2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25125;"	d
+RG_5G_RX_HG_DIV2_CORE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25344;"	d
+RG_5G_RX_HG_DIV2_CORE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25342;"	d
+RG_5G_RX_HG_DIV2_CORE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25341;"	d
+RG_5G_RX_HG_DIV2_CORE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25343;"	d
+RG_5G_RX_HG_DIV2_CORE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25345;"	d
+RG_5G_RX_HG_LNAHGN_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25319;"	d
+RG_5G_RX_HG_LNAHGN_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25317;"	d
+RG_5G_RX_HG_LNAHGN_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25316;"	d
+RG_5G_RX_HG_LNAHGN_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25318;"	d
+RG_5G_RX_HG_LNAHGN_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25320;"	d
+RG_5G_RX_HG_LNAHGP_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25324;"	d
+RG_5G_RX_HG_LNAHGP_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25322;"	d
+RG_5G_RX_HG_LNAHGP_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25321;"	d
+RG_5G_RX_HG_LNAHGP_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25323;"	d
+RG_5G_RX_HG_LNAHGP_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25325;"	d
+RG_5G_RX_HG_LNALG_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25329;"	d
+RG_5G_RX_HG_LNALG_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25327;"	d
+RG_5G_RX_HG_LNALG_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25326;"	d
+RG_5G_RX_HG_LNALG_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25328;"	d
+RG_5G_RX_HG_LNALG_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25330;"	d
+RG_5G_RX_HG_LNA_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25309;"	d
+RG_5G_RX_HG_LNA_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25307;"	d
+RG_5G_RX_HG_LNA_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25306;"	d
+RG_5G_RX_HG_LNA_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25308;"	d
+RG_5G_RX_HG_LNA_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25310;"	d
+RG_5G_RX_HG_SQDC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25339;"	d
+RG_5G_RX_HG_SQDC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25337;"	d
+RG_5G_RX_HG_SQDC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25336;"	d
+RG_5G_RX_HG_SQDC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25338;"	d
+RG_5G_RX_HG_SQDC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25340;"	d
+RG_5G_RX_HG_TZI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25354;"	d
+RG_5G_RX_HG_TZI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25352;"	d
+RG_5G_RX_HG_TZI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25351;"	d
+RG_5G_RX_HG_TZI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25353;"	d
+RG_5G_RX_HG_TZI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25355;"	d
+RG_5G_RX_HG_TZ_CAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25334;"	d
+RG_5G_RX_HG_TZ_CAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25332;"	d
+RG_5G_RX_HG_TZ_CAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25331;"	d
+RG_5G_RX_HG_TZ_CAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25333;"	d
+RG_5G_RX_HG_TZ_CAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25335;"	d
+RG_5G_RX_HG_TZ_GC_BOOST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25349;"	d
+RG_5G_RX_HG_TZ_GC_BOOST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25347;"	d
+RG_5G_RX_HG_TZ_GC_BOOST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25346;"	d
+RG_5G_RX_HG_TZ_GC_BOOST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25348;"	d
+RG_5G_RX_HG_TZ_GC_BOOST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25350;"	d
+RG_5G_RX_HG_TZ_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25314;"	d
+RG_5G_RX_HG_TZ_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25312;"	d
+RG_5G_RX_HG_TZ_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25311;"	d
+RG_5G_RX_HG_TZ_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25313;"	d
+RG_5G_RX_HG_TZ_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25315;"	d
+RG_5G_RX_HG_TZ_VCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25359;"	d
+RG_5G_RX_HG_TZ_VCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25357;"	d
+RG_5G_RX_HG_TZ_VCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25356;"	d
+RG_5G_RX_HG_TZ_VCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25358;"	d
+RG_5G_RX_HG_TZ_VCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25360;"	d
+RG_5G_RX_IQCAL_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26829;"	d
+RG_5G_RX_IQCAL_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26827;"	d
+RG_5G_RX_IQCAL_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26826;"	d
+RG_5G_RX_IQCAL_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26828;"	d
+RG_5G_RX_IQCAL_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26830;"	d
+RG_5G_RX_IQCAL_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24989;"	d
+RG_5G_RX_IQCAL_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24987;"	d
+RG_5G_RX_IQCAL_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24986;"	d
+RG_5G_RX_IQCAL_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24988;"	d
+RG_5G_RX_IQCAL_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24990;"	d
+RG_5G_RX_LG_DIV2_CORE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25454;"	d
+RG_5G_RX_LG_DIV2_CORE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25452;"	d
+RG_5G_RX_LG_DIV2_CORE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25451;"	d
+RG_5G_RX_LG_DIV2_CORE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25453;"	d
+RG_5G_RX_LG_DIV2_CORE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25455;"	d
+RG_5G_RX_LG_LNAHGN_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25429;"	d
+RG_5G_RX_LG_LNAHGN_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25427;"	d
+RG_5G_RX_LG_LNAHGN_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25426;"	d
+RG_5G_RX_LG_LNAHGN_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25428;"	d
+RG_5G_RX_LG_LNAHGN_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25430;"	d
+RG_5G_RX_LG_LNAHGP_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25434;"	d
+RG_5G_RX_LG_LNAHGP_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25432;"	d
+RG_5G_RX_LG_LNAHGP_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25431;"	d
+RG_5G_RX_LG_LNAHGP_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25433;"	d
+RG_5G_RX_LG_LNAHGP_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25435;"	d
+RG_5G_RX_LG_LNALG_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25439;"	d
+RG_5G_RX_LG_LNALG_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25437;"	d
+RG_5G_RX_LG_LNALG_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25436;"	d
+RG_5G_RX_LG_LNALG_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25438;"	d
+RG_5G_RX_LG_LNALG_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25440;"	d
+RG_5G_RX_LG_LNA_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25419;"	d
+RG_5G_RX_LG_LNA_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25417;"	d
+RG_5G_RX_LG_LNA_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25416;"	d
+RG_5G_RX_LG_LNA_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25418;"	d
+RG_5G_RX_LG_LNA_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25420;"	d
+RG_5G_RX_LG_SQDC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25449;"	d
+RG_5G_RX_LG_SQDC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25447;"	d
+RG_5G_RX_LG_SQDC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25446;"	d
+RG_5G_RX_LG_SQDC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25448;"	d
+RG_5G_RX_LG_SQDC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25450;"	d
+RG_5G_RX_LG_TZI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25464;"	d
+RG_5G_RX_LG_TZI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25462;"	d
+RG_5G_RX_LG_TZI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25461;"	d
+RG_5G_RX_LG_TZI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25463;"	d
+RG_5G_RX_LG_TZI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25465;"	d
+RG_5G_RX_LG_TZ_CAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25444;"	d
+RG_5G_RX_LG_TZ_CAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25442;"	d
+RG_5G_RX_LG_TZ_CAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25441;"	d
+RG_5G_RX_LG_TZ_CAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25443;"	d
+RG_5G_RX_LG_TZ_CAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25445;"	d
+RG_5G_RX_LG_TZ_GC_BOOST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25459;"	d
+RG_5G_RX_LG_TZ_GC_BOOST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25457;"	d
+RG_5G_RX_LG_TZ_GC_BOOST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25456;"	d
+RG_5G_RX_LG_TZ_GC_BOOST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25458;"	d
+RG_5G_RX_LG_TZ_GC_BOOST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25460;"	d
+RG_5G_RX_LG_TZ_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25424;"	d
+RG_5G_RX_LG_TZ_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25422;"	d
+RG_5G_RX_LG_TZ_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25421;"	d
+RG_5G_RX_LG_TZ_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25423;"	d
+RG_5G_RX_LG_TZ_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25425;"	d
+RG_5G_RX_LG_TZ_VCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25469;"	d
+RG_5G_RX_LG_TZ_VCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25467;"	d
+RG_5G_RX_LG_TZ_VCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25466;"	d
+RG_5G_RX_LG_TZ_VCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25468;"	d
+RG_5G_RX_LG_TZ_VCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25470;"	d
+RG_5G_RX_LNA_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24879;"	d
+RG_5G_RX_LNA_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24877;"	d
+RG_5G_RX_LNA_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24876;"	d
+RG_5G_RX_LNA_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24878;"	d
+RG_5G_RX_LNA_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24880;"	d
+RG_5G_RX_LNA_SETTLE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25099;"	d
+RG_5G_RX_LNA_SETTLE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25097;"	d
+RG_5G_RX_LNA_SETTLE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25096;"	d
+RG_5G_RX_LNA_SETTLE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25098;"	d
+RG_5G_RX_LNA_SETTLE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25100;"	d
+RG_5G_RX_LNA_TRI_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25094;"	d
+RG_5G_RX_LNA_TRI_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25092;"	d
+RG_5G_RX_LNA_TRI_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25091;"	d
+RG_5G_RX_LNA_TRI_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25093;"	d
+RG_5G_RX_LNA_TRI_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25095;"	d
+RG_5G_RX_LOBUF_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24909;"	d
+RG_5G_RX_LOBUF_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24907;"	d
+RG_5G_RX_LOBUF_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24906;"	d
+RG_5G_RX_LOBUF_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24908;"	d
+RG_5G_RX_LOBUF_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24910;"	d
+RG_5G_RX_MG_DIV2_CORE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25399;"	d
+RG_5G_RX_MG_DIV2_CORE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25397;"	d
+RG_5G_RX_MG_DIV2_CORE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25396;"	d
+RG_5G_RX_MG_DIV2_CORE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25398;"	d
+RG_5G_RX_MG_DIV2_CORE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25400;"	d
+RG_5G_RX_MG_LNAHGN_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25374;"	d
+RG_5G_RX_MG_LNAHGN_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25372;"	d
+RG_5G_RX_MG_LNAHGN_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25371;"	d
+RG_5G_RX_MG_LNAHGN_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25373;"	d
+RG_5G_RX_MG_LNAHGN_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25375;"	d
+RG_5G_RX_MG_LNAHGP_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25379;"	d
+RG_5G_RX_MG_LNAHGP_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25377;"	d
+RG_5G_RX_MG_LNAHGP_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25376;"	d
+RG_5G_RX_MG_LNAHGP_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25378;"	d
+RG_5G_RX_MG_LNAHGP_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25380;"	d
+RG_5G_RX_MG_LNALG_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25384;"	d
+RG_5G_RX_MG_LNALG_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25382;"	d
+RG_5G_RX_MG_LNALG_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25381;"	d
+RG_5G_RX_MG_LNALG_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25383;"	d
+RG_5G_RX_MG_LNALG_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25385;"	d
+RG_5G_RX_MG_LNA_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25364;"	d
+RG_5G_RX_MG_LNA_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25362;"	d
+RG_5G_RX_MG_LNA_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25361;"	d
+RG_5G_RX_MG_LNA_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25363;"	d
+RG_5G_RX_MG_LNA_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25365;"	d
+RG_5G_RX_MG_SQDC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25394;"	d
+RG_5G_RX_MG_SQDC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25392;"	d
+RG_5G_RX_MG_SQDC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25391;"	d
+RG_5G_RX_MG_SQDC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25393;"	d
+RG_5G_RX_MG_SQDC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25395;"	d
+RG_5G_RX_MG_TZI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25409;"	d
+RG_5G_RX_MG_TZI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25407;"	d
+RG_5G_RX_MG_TZI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25406;"	d
+RG_5G_RX_MG_TZI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25408;"	d
+RG_5G_RX_MG_TZI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25410;"	d
+RG_5G_RX_MG_TZ_CAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25389;"	d
+RG_5G_RX_MG_TZ_CAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25387;"	d
+RG_5G_RX_MG_TZ_CAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25386;"	d
+RG_5G_RX_MG_TZ_CAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25388;"	d
+RG_5G_RX_MG_TZ_CAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25390;"	d
+RG_5G_RX_MG_TZ_GC_BOOST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25404;"	d
+RG_5G_RX_MG_TZ_GC_BOOST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25402;"	d
+RG_5G_RX_MG_TZ_GC_BOOST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25401;"	d
+RG_5G_RX_MG_TZ_GC_BOOST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25403;"	d
+RG_5G_RX_MG_TZ_GC_BOOST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25405;"	d
+RG_5G_RX_MG_TZ_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25369;"	d
+RG_5G_RX_MG_TZ_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25367;"	d
+RG_5G_RX_MG_TZ_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25366;"	d
+RG_5G_RX_MG_TZ_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25368;"	d
+RG_5G_RX_MG_TZ_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25370;"	d
+RG_5G_RX_MG_TZ_VCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25414;"	d
+RG_5G_RX_MG_TZ_VCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25412;"	d
+RG_5G_RX_MG_TZ_VCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25411;"	d
+RG_5G_RX_MG_TZ_VCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25413;"	d
+RG_5G_RX_MG_TZ_VCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25415;"	d
+RG_5G_RX_MIXER_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24889;"	d
+RG_5G_RX_MIXER_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24887;"	d
+RG_5G_RX_MIXER_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24886;"	d
+RG_5G_RX_MIXER_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24888;"	d
+RG_5G_RX_MIXER_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24890;"	d
+RG_5G_RX_SCA_LOAD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25089;"	d
+RG_5G_RX_SCA_LOAD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25087;"	d
+RG_5G_RX_SCA_LOAD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25086;"	d
+RG_5G_RX_SCA_LOAD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25088;"	d
+RG_5G_RX_SCA_LOAD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25090;"	d
+RG_5G_RX_SCA_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25079;"	d
+RG_5G_RX_SCA_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25077;"	d
+RG_5G_RX_SCA_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25076;"	d
+RG_5G_RX_SCA_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25078;"	d
+RG_5G_RX_SCA_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25080;"	d
+RG_5G_RX_SCA_MA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25084;"	d
+RG_5G_RX_SCA_MA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25082;"	d
+RG_5G_RX_SCA_MA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25081;"	d
+RG_5G_RX_SCA_MA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25083;"	d
+RG_5G_RX_SCA_MA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25085;"	d
+RG_5G_RX_TZ_CMZ_C_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25184;"	d
+RG_5G_RX_TZ_CMZ_C_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25182;"	d
+RG_5G_RX_TZ_CMZ_C_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25181;"	d
+RG_5G_RX_TZ_CMZ_C_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25183;"	d
+RG_5G_RX_TZ_CMZ_C_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25185;"	d
+RG_5G_RX_TZ_CMZ_R_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25189;"	d
+RG_5G_RX_TZ_CMZ_R_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25187;"	d
+RG_5G_RX_TZ_CMZ_R_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25186;"	d
+RG_5G_RX_TZ_CMZ_R_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25188;"	d
+RG_5G_RX_TZ_CMZ_R_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25190;"	d
+RG_5G_RX_TZ_COURSE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25129;"	d
+RG_5G_RX_TZ_COURSE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25127;"	d
+RG_5G_RX_TZ_COURSE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25126;"	d
+RG_5G_RX_TZ_COURSE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25128;"	d
+RG_5G_RX_TZ_COURSE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25130;"	d
+RG_5G_RX_TZ_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24919;"	d
+RG_5G_RX_TZ_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24917;"	d
+RG_5G_RX_TZ_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24916;"	d
+RG_5G_RX_TZ_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24918;"	d
+RG_5G_RX_TZ_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24920;"	d
+RG_5G_RX_TZ_OUT_TRISTATE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24974;"	d
+RG_5G_RX_TZ_OUT_TRISTATE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24972;"	d
+RG_5G_RX_TZ_OUT_TRISTATE_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24969;"	d
+RG_5G_RX_TZ_OUT_TRISTATE_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24967;"	d
+RG_5G_RX_TZ_OUT_TRISTATE_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24966;"	d
+RG_5G_RX_TZ_OUT_TRISTATE_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24968;"	d
+RG_5G_RX_TZ_OUT_TRISTATE_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24970;"	d
+RG_5G_RX_TZ_OUT_TRISTATE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24971;"	d
+RG_5G_RX_TZ_OUT_TRISTATE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24973;"	d
+RG_5G_RX_TZ_OUT_TRISTATE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24975;"	d
+RG_5G_RX_ULG_DIV2_CORE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25509;"	d
+RG_5G_RX_ULG_DIV2_CORE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25507;"	d
+RG_5G_RX_ULG_DIV2_CORE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25506;"	d
+RG_5G_RX_ULG_DIV2_CORE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25508;"	d
+RG_5G_RX_ULG_DIV2_CORE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25510;"	d
+RG_5G_RX_ULG_LNAHGN_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25484;"	d
+RG_5G_RX_ULG_LNAHGN_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25482;"	d
+RG_5G_RX_ULG_LNAHGN_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25481;"	d
+RG_5G_RX_ULG_LNAHGN_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25483;"	d
+RG_5G_RX_ULG_LNAHGN_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25485;"	d
+RG_5G_RX_ULG_LNAHGP_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25489;"	d
+RG_5G_RX_ULG_LNAHGP_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25487;"	d
+RG_5G_RX_ULG_LNAHGP_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25486;"	d
+RG_5G_RX_ULG_LNAHGP_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25488;"	d
+RG_5G_RX_ULG_LNAHGP_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25490;"	d
+RG_5G_RX_ULG_LNALG_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25494;"	d
+RG_5G_RX_ULG_LNALG_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25492;"	d
+RG_5G_RX_ULG_LNALG_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25491;"	d
+RG_5G_RX_ULG_LNALG_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25493;"	d
+RG_5G_RX_ULG_LNALG_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25495;"	d
+RG_5G_RX_ULG_LNA_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25474;"	d
+RG_5G_RX_ULG_LNA_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25472;"	d
+RG_5G_RX_ULG_LNA_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25471;"	d
+RG_5G_RX_ULG_LNA_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25473;"	d
+RG_5G_RX_ULG_LNA_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25475;"	d
+RG_5G_RX_ULG_SQDC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25504;"	d
+RG_5G_RX_ULG_SQDC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25502;"	d
+RG_5G_RX_ULG_SQDC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25501;"	d
+RG_5G_RX_ULG_SQDC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25503;"	d
+RG_5G_RX_ULG_SQDC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25505;"	d
+RG_5G_RX_ULG_TZI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25519;"	d
+RG_5G_RX_ULG_TZI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25517;"	d
+RG_5G_RX_ULG_TZI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25516;"	d
+RG_5G_RX_ULG_TZI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25518;"	d
+RG_5G_RX_ULG_TZI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25520;"	d
+RG_5G_RX_ULG_TZ_CAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25499;"	d
+RG_5G_RX_ULG_TZ_CAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25497;"	d
+RG_5G_RX_ULG_TZ_CAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25496;"	d
+RG_5G_RX_ULG_TZ_CAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25498;"	d
+RG_5G_RX_ULG_TZ_CAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25500;"	d
+RG_5G_RX_ULG_TZ_GC_BOOST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25514;"	d
+RG_5G_RX_ULG_TZ_GC_BOOST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25512;"	d
+RG_5G_RX_ULG_TZ_GC_BOOST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25511;"	d
+RG_5G_RX_ULG_TZ_GC_BOOST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25513;"	d
+RG_5G_RX_ULG_TZ_GC_BOOST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25515;"	d
+RG_5G_RX_ULG_TZ_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25479;"	d
+RG_5G_RX_ULG_TZ_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25477;"	d
+RG_5G_RX_ULG_TZ_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25476;"	d
+RG_5G_RX_ULG_TZ_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25478;"	d
+RG_5G_RX_ULG_TZ_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25480;"	d
+RG_5G_RX_ULG_TZ_VCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25524;"	d
+RG_5G_RX_ULG_TZ_VCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25522;"	d
+RG_5G_RX_ULG_TZ_VCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25521;"	d
+RG_5G_RX_ULG_TZ_VCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25523;"	d
+RG_5G_RX_ULG_TZ_VCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25525;"	d
+RG_5G_TXDAC_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26754;"	d
+RG_5G_TXDAC_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26752;"	d
+RG_5G_TXDAC_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26751;"	d
+RG_5G_TXDAC_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26753;"	d
+RG_5G_TXDAC_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26755;"	d
+RG_5G_TXDAC_R2T_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26794;"	d
+RG_5G_TXDAC_R2T_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26792;"	d
+RG_5G_TXDAC_R2T_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26791;"	d
+RG_5G_TXDAC_R2T_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26793;"	d
+RG_5G_TXDAC_R2T_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26795;"	d
+RG_5G_TXDAC_T2R_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26774;"	d
+RG_5G_TXDAC_T2R_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26772;"	d
+RG_5G_TXDAC_T2R_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26771;"	d
+RG_5G_TXDAC_T2R_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26773;"	d
+RG_5G_TXDAC_T2R_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26775;"	d
+RG_5G_TXLPF_BOOSTI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25559;"	d
+RG_5G_TXLPF_BOOSTI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25557;"	d
+RG_5G_TXLPF_BOOSTI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25556;"	d
+RG_5G_TXLPF_BOOSTI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25558;"	d
+RG_5G_TXLPF_BOOSTI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25560;"	d
+RG_5G_TXLPF_GMCELL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25279;"	d
+RG_5G_TXLPF_GMCELL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25277;"	d
+RG_5G_TXLPF_GMCELL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25276;"	d
+RG_5G_TXLPF_GMCELL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25278;"	d
+RG_5G_TXLPF_GMCELL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25280;"	d
+RG_5G_TXMOD_GMCELL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25274;"	d
+RG_5G_TXMOD_GMCELL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25272;"	d
+RG_5G_TXMOD_GMCELL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25271;"	d
+RG_5G_TXMOD_GMCELL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25273;"	d
+RG_5G_TXMOD_GMCELL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25275;"	d
+RG_5G_TXMOD_LOBIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25299;"	d
+RG_5G_TXMOD_LOBIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25297;"	d
+RG_5G_TXMOD_LOBIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25296;"	d
+RG_5G_TXMOD_LOBIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25298;"	d
+RG_5G_TXMOD_LOBIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25300;"	d
+RG_5G_TXMOD_PGABIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25304;"	d
+RG_5G_TXMOD_PGABIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25302;"	d
+RG_5G_TXMOD_PGABIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25301;"	d
+RG_5G_TXMOD_PGABIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25303;"	d
+RG_5G_TXMOD_PGABIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25305;"	d
+RG_5G_TXPAPGA_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25194;"	d
+RG_5G_TXPAPGA_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25192;"	d
+RG_5G_TXPAPGA_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25191;"	d
+RG_5G_TXPAPGA_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25193;"	d
+RG_5G_TXPAPGA_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25195;"	d
+RG_5G_TXPA_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26764;"	d
+RG_5G_TXPA_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26762;"	d
+RG_5G_TXPA_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26761;"	d
+RG_5G_TXPA_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26763;"	d
+RG_5G_TXPA_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26765;"	d
+RG_5G_TXPA_R2T_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26804;"	d
+RG_5G_TXPA_R2T_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26802;"	d
+RG_5G_TXPA_R2T_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26801;"	d
+RG_5G_TXPA_R2T_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26803;"	d
+RG_5G_TXPA_R2T_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26805;"	d
+RG_5G_TXPA_T2R_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26784;"	d
+RG_5G_TXPA_T2R_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26782;"	d
+RG_5G_TXPA_T2R_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26781;"	d
+RG_5G_TXPA_T2R_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26783;"	d
+RG_5G_TXPA_T2R_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26785;"	d
+RG_5G_TXPGA_CAPSW_F0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27019;"	d
+RG_5G_TXPGA_CAPSW_F0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27017;"	d
+RG_5G_TXPGA_CAPSW_F0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27016;"	d
+RG_5G_TXPGA_CAPSW_F0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27018;"	d
+RG_5G_TXPGA_CAPSW_F0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27020;"	d
+RG_5G_TXPGA_CAPSW_F1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27044;"	d
+RG_5G_TXPGA_CAPSW_F1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27042;"	d
+RG_5G_TXPGA_CAPSW_F1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27041;"	d
+RG_5G_TXPGA_CAPSW_F1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27043;"	d
+RG_5G_TXPGA_CAPSW_F1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27045;"	d
+RG_5G_TXPGA_CAPSW_F2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27069;"	d
+RG_5G_TXPGA_CAPSW_F2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27067;"	d
+RG_5G_TXPGA_CAPSW_F2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27066;"	d
+RG_5G_TXPGA_CAPSW_F2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27068;"	d
+RG_5G_TXPGA_CAPSW_F2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27070;"	d
+RG_5G_TXPGA_CAPSW_F3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27094;"	d
+RG_5G_TXPGA_CAPSW_F3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27092;"	d
+RG_5G_TXPGA_CAPSW_F3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27091;"	d
+RG_5G_TXPGA_CAPSW_F3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27093;"	d
+RG_5G_TXPGA_CAPSW_F3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27095;"	d
+RG_5G_TXPGA_CAPSW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25199;"	d
+RG_5G_TXPGA_CAPSW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25197;"	d
+RG_5G_TXPGA_CAPSW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25196;"	d
+RG_5G_TXPGA_CAPSW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25198;"	d
+RG_5G_TXPGA_CAPSW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25200;"	d
+RG_5G_TXPGA_MAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25264;"	d
+RG_5G_TXPGA_MAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25262;"	d
+RG_5G_TXPGA_MAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25261;"	d
+RG_5G_TXPGA_MAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25263;"	d
+RG_5G_TXPGA_MAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25265;"	d
+RG_5G_TXPGA_STEER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25269;"	d
+RG_5G_TXPGA_STEER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25267;"	d
+RG_5G_TXPGA_STEER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25266;"	d
+RG_5G_TXPGA_STEER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25268;"	d
+RG_5G_TXPGA_STEER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25270;"	d
+RG_5G_TXRF_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26759;"	d
+RG_5G_TXRF_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26757;"	d
+RG_5G_TXRF_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26756;"	d
+RG_5G_TXRF_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26758;"	d
+RG_5G_TXRF_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26760;"	d
+RG_5G_TXRF_R2T_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26799;"	d
+RG_5G_TXRF_R2T_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26797;"	d
+RG_5G_TXRF_R2T_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26796;"	d
+RG_5G_TXRF_R2T_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26798;"	d
+RG_5G_TXRF_R2T_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26800;"	d
+RG_5G_TXRF_T2R_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26779;"	d
+RG_5G_TXRF_T2R_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26777;"	d
+RG_5G_TXRF_T2R_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26776;"	d
+RG_5G_TXRF_T2R_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26778;"	d
+RG_5G_TXRF_T2R_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26780;"	d
+RG_5G_TX_ADDGMCELL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25294;"	d
+RG_5G_TX_ADDGMCELL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25292;"	d
+RG_5G_TX_ADDGMCELL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25291;"	d
+RG_5G_TX_ADDGMCELL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25293;"	d
+RG_5G_TX_ADDGMCELL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25295;"	d
+RG_5G_TX_BAND_F0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27864;"	d
+RG_5G_TX_BAND_F0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27862;"	d
+RG_5G_TX_BAND_F0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27861;"	d
+RG_5G_TX_BAND_F0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27863;"	d
+RG_5G_TX_BAND_F0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27865;"	d
+RG_5G_TX_BAND_F1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27859;"	d
+RG_5G_TX_BAND_F1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27857;"	d
+RG_5G_TX_BAND_F1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27856;"	d
+RG_5G_TX_BAND_F1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27858;"	d
+RG_5G_TX_BAND_F1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27860;"	d
+RG_5G_TX_BAND_F2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27869;"	d
+RG_5G_TX_BAND_F2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27867;"	d
+RG_5G_TX_BAND_F2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27866;"	d
+RG_5G_TX_BAND_F2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27868;"	d
+RG_5G_TX_BAND_F2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27870;"	d
+RG_5G_TX_DACI1ST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25529;"	d
+RG_5G_TX_DACI1ST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25527;"	d
+RG_5G_TX_DACI1ST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25526;"	d
+RG_5G_TX_DACI1ST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25528;"	d
+RG_5G_TX_DACI1ST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25530;"	d
+RG_5G_TX_DACLPF_ICOARSE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25534;"	d
+RG_5G_TX_DACLPF_ICOARSE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25532;"	d
+RG_5G_TX_DACLPF_ICOARSE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25531;"	d
+RG_5G_TX_DACLPF_ICOARSE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25533;"	d
+RG_5G_TX_DACLPF_ICOARSE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25535;"	d
+RG_5G_TX_DACLPF_IFINE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25539;"	d
+RG_5G_TX_DACLPF_IFINE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25537;"	d
+RG_5G_TX_DACLPF_IFINE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25536;"	d
+RG_5G_TX_DACLPF_IFINE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25538;"	d
+RG_5G_TX_DACLPF_IFINE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25540;"	d
+RG_5G_TX_DACLPF_VCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25544;"	d
+RG_5G_TX_DACLPF_VCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25542;"	d
+RG_5G_TX_DACLPF_VCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25541;"	d
+RG_5G_TX_DACLPF_VCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25543;"	d
+RG_5G_TX_DACLPF_VCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25545;"	d
+RG_5G_TX_DAC_CKEDGE_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25569;"	d
+RG_5G_TX_DAC_CKEDGE_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25567;"	d
+RG_5G_TX_DAC_CKEDGE_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25566;"	d
+RG_5G_TX_DAC_CKEDGE_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25568;"	d
+RG_5G_TX_DAC_CKEDGE_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25570;"	d
+RG_5G_TX_DAC_IATTN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25554;"	d
+RG_5G_TX_DAC_IATTN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25552;"	d
+RG_5G_TX_DAC_IATTN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25551;"	d
+RG_5G_TX_DAC_IATTN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25553;"	d
+RG_5G_TX_DAC_IATTN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25555;"	d
+RG_5G_TX_DAC_IBIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25549;"	d
+RG_5G_TX_DAC_IBIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25547;"	d
+RG_5G_TX_DAC_IBIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25546;"	d
+RG_5G_TX_DAC_IBIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25548;"	d
+RG_5G_TX_DAC_IBIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25550;"	d
+RG_5G_TX_DAC_IOFFSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25579;"	d
+RG_5G_TX_DAC_IOFFSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25577;"	d
+RG_5G_TX_DAC_IOFFSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25576;"	d
+RG_5G_TX_DAC_IOFFSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25578;"	d
+RG_5G_TX_DAC_IOFFSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25580;"	d
+RG_5G_TX_DAC_OS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25574;"	d
+RG_5G_TX_DAC_OS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25572;"	d
+RG_5G_TX_DAC_OS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25571;"	d
+RG_5G_TX_DAC_OS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25573;"	d
+RG_5G_TX_DAC_OS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25575;"	d
+RG_5G_TX_DAC_QOFFSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25584;"	d
+RG_5G_TX_DAC_QOFFSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25582;"	d
+RG_5G_TX_DAC_QOFFSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25581;"	d
+RG_5G_TX_DAC_QOFFSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25583;"	d
+RG_5G_TX_DAC_QOFFSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25585;"	d
+RG_5G_TX_DAC_RCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25564;"	d
+RG_5G_TX_DAC_RCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25562;"	d
+RG_5G_TX_DAC_RCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25561;"	d
+RG_5G_TX_DAC_RCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25563;"	d
+RG_5G_TX_DAC_RCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25565;"	d
+RG_5G_TX_DCCAL_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26819;"	d
+RG_5G_TX_DCCAL_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26817;"	d
+RG_5G_TX_DCCAL_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26816;"	d
+RG_5G_TX_DCCAL_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26818;"	d
+RG_5G_TX_DCCAL_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26820;"	d
+RG_5G_TX_DIV2_BUF_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24959;"	d
+RG_5G_TX_DIV2_BUF_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24957;"	d
+RG_5G_TX_DIV2_BUF_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24956;"	d
+RG_5G_TX_DIV2_BUF_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24958;"	d
+RG_5G_TX_DIV2_BUF_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24960;"	d
+RG_5G_TX_DIV2_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24949;"	d
+RG_5G_TX_DIV2_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24947;"	d
+RG_5G_TX_DIV2_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24946;"	d
+RG_5G_TX_DIV2_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24948;"	d
+RG_5G_TX_DIV2_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24950;"	d
+RG_5G_TX_DIV_CMLISEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25244;"	d
+RG_5G_TX_DIV_CMLISEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25242;"	d
+RG_5G_TX_DIV_CMLISEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25241;"	d
+RG_5G_TX_DIV_CMLISEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25243;"	d
+RG_5G_TX_DIV_CMLISEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25245;"	d
+RG_5G_TX_DIV_CMLVSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25249;"	d
+RG_5G_TX_DIV_CMLVSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25247;"	d
+RG_5G_TX_DIV_CMLVSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25246;"	d
+RG_5G_TX_DIV_CMLVSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25248;"	d
+RG_5G_TX_DIV_CMLVSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25250;"	d
+RG_5G_TX_DIV_PREBUFS2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25239;"	d
+RG_5G_TX_DIV_PREBUFS2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25237;"	d
+RG_5G_TX_DIV_PREBUFS2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25236;"	d
+RG_5G_TX_DIV_PREBUFS2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25238;"	d
+RG_5G_TX_DIV_PREBUFS2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25240;"	d
+RG_5G_TX_DIV_VSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25254;"	d
+RG_5G_TX_DIV_VSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25252;"	d
+RG_5G_TX_DIV_VSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25251;"	d
+RG_5G_TX_DIV_VSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25253;"	d
+RG_5G_TX_DIV_VSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25255;"	d
+RG_5G_TX_DPDGM_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25134;"	d
+RG_5G_TX_DPDGM_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25132;"	d
+RG_5G_TX_DPDGM_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25131;"	d
+RG_5G_TX_DPDGM_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25133;"	d
+RG_5G_TX_DPDGM_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25135;"	d
+RG_5G_TX_DPD_DIV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25139;"	d
+RG_5G_TX_DPD_DIV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25137;"	d
+RG_5G_TX_DPD_DIV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25136;"	d
+RG_5G_TX_DPD_DIV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25138;"	d
+RG_5G_TX_DPD_DIV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25140;"	d
+RG_5G_TX_DPD_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24999;"	d
+RG_5G_TX_DPD_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24997;"	d
+RG_5G_TX_DPD_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24996;"	d
+RG_5G_TX_DPD_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24998;"	d
+RG_5G_TX_DPD_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25000;"	d
+RG_5G_TX_GAIN_DPDCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26874;"	d
+RG_5G_TX_GAIN_DPDCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26872;"	d
+RG_5G_TX_GAIN_DPDCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26871;"	d
+RG_5G_TX_GAIN_DPDCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26873;"	d
+RG_5G_TX_GAIN_DPDCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26875;"	d
+RG_5G_TX_GAIN_F0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27139;"	d
+RG_5G_TX_GAIN_F0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27137;"	d
+RG_5G_TX_GAIN_F0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27136;"	d
+RG_5G_TX_GAIN_F0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27138;"	d
+RG_5G_TX_GAIN_F0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27140;"	d
+RG_5G_TX_GAIN_F1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27144;"	d
+RG_5G_TX_GAIN_F1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27142;"	d
+RG_5G_TX_GAIN_F1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27141;"	d
+RG_5G_TX_GAIN_F1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27143;"	d
+RG_5G_TX_GAIN_F1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27145;"	d
+RG_5G_TX_GAIN_F2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27149;"	d
+RG_5G_TX_GAIN_F2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27147;"	d
+RG_5G_TX_GAIN_F2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27146;"	d
+RG_5G_TX_GAIN_F2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27148;"	d
+RG_5G_TX_GAIN_F2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27150;"	d
+RG_5G_TX_GAIN_F3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27154;"	d
+RG_5G_TX_GAIN_F3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27152;"	d
+RG_5G_TX_GAIN_F3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27151;"	d
+RG_5G_TX_GAIN_F3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27153;"	d
+RG_5G_TX_GAIN_F3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27155;"	d
+RG_5G_TX_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25289;"	d
+RG_5G_TX_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25287;"	d
+RG_5G_TX_GAIN_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21584;"	d
+RG_5G_TX_GAIN_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21582;"	d
+RG_5G_TX_GAIN_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21581;"	d
+RG_5G_TX_GAIN_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21583;"	d
+RG_5G_TX_GAIN_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21585;"	d
+RG_5G_TX_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25286;"	d
+RG_5G_TX_GAIN_OFFSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25284;"	d
+RG_5G_TX_GAIN_OFFSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25282;"	d
+RG_5G_TX_GAIN_OFFSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25281;"	d
+RG_5G_TX_GAIN_OFFSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25283;"	d
+RG_5G_TX_GAIN_OFFSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25285;"	d
+RG_5G_TX_GAIN_RXIQCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26859;"	d
+RG_5G_TX_GAIN_RXIQCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26857;"	d
+RG_5G_TX_GAIN_RXIQCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26856;"	d
+RG_5G_TX_GAIN_RXIQCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26858;"	d
+RG_5G_TX_GAIN_RXIQCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26860;"	d
+RG_5G_TX_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25288;"	d
+RG_5G_TX_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25290;"	d
+RG_5G_TX_GAIN_TXCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26839;"	d
+RG_5G_TX_GAIN_TXCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26837;"	d
+RG_5G_TX_GAIN_TXCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26836;"	d
+RG_5G_TX_GAIN_TXCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26838;"	d
+RG_5G_TX_GAIN_TXCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26840;"	d
+RG_5G_TX_IQCAL_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26824;"	d
+RG_5G_TX_IQCAL_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26822;"	d
+RG_5G_TX_IQCAL_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26821;"	d
+RG_5G_TX_IQCAL_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26823;"	d
+RG_5G_TX_IQCAL_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26825;"	d
+RG_5G_TX_LOBUF_VSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25259;"	d
+RG_5G_TX_LOBUF_VSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25257;"	d
+RG_5G_TX_LOBUF_VSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25256;"	d
+RG_5G_TX_LOBUF_VSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25258;"	d
+RG_5G_TX_LOBUF_VSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25260;"	d
+RG_5G_TX_MOD_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24939;"	d
+RG_5G_TX_MOD_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24937;"	d
+RG_5G_TX_MOD_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24936;"	d
+RG_5G_TX_MOD_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24938;"	d
+RG_5G_TX_MOD_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24940;"	d
+RG_5G_TX_PA1_VCAS_F0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27029;"	d
+RG_5G_TX_PA1_VCAS_F0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27027;"	d
+RG_5G_TX_PA1_VCAS_F0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27026;"	d
+RG_5G_TX_PA1_VCAS_F0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27028;"	d
+RG_5G_TX_PA1_VCAS_F0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27030;"	d
+RG_5G_TX_PA1_VCAS_F1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27054;"	d
+RG_5G_TX_PA1_VCAS_F1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27052;"	d
+RG_5G_TX_PA1_VCAS_F1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27051;"	d
+RG_5G_TX_PA1_VCAS_F1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27053;"	d
+RG_5G_TX_PA1_VCAS_F1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27055;"	d
+RG_5G_TX_PA1_VCAS_F2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27079;"	d
+RG_5G_TX_PA1_VCAS_F2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27077;"	d
+RG_5G_TX_PA1_VCAS_F2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27076;"	d
+RG_5G_TX_PA1_VCAS_F2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27078;"	d
+RG_5G_TX_PA1_VCAS_F2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27080;"	d
+RG_5G_TX_PA1_VCAS_F3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27104;"	d
+RG_5G_TX_PA1_VCAS_F3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27102;"	d
+RG_5G_TX_PA1_VCAS_F3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27101;"	d
+RG_5G_TX_PA1_VCAS_F3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27103;"	d
+RG_5G_TX_PA1_VCAS_F3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27105;"	d
+RG_5G_TX_PA1_VCAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25219;"	d
+RG_5G_TX_PA1_VCAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25217;"	d
+RG_5G_TX_PA1_VCAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25216;"	d
+RG_5G_TX_PA1_VCAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25218;"	d
+RG_5G_TX_PA1_VCAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25220;"	d
+RG_5G_TX_PA2_VCAS_F0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27034;"	d
+RG_5G_TX_PA2_VCAS_F0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27032;"	d
+RG_5G_TX_PA2_VCAS_F0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27031;"	d
+RG_5G_TX_PA2_VCAS_F0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27033;"	d
+RG_5G_TX_PA2_VCAS_F0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27035;"	d
+RG_5G_TX_PA2_VCAS_F1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27059;"	d
+RG_5G_TX_PA2_VCAS_F1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27057;"	d
+RG_5G_TX_PA2_VCAS_F1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27056;"	d
+RG_5G_TX_PA2_VCAS_F1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27058;"	d
+RG_5G_TX_PA2_VCAS_F1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27060;"	d
+RG_5G_TX_PA2_VCAS_F2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27084;"	d
+RG_5G_TX_PA2_VCAS_F2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27082;"	d
+RG_5G_TX_PA2_VCAS_F2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27081;"	d
+RG_5G_TX_PA2_VCAS_F2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27083;"	d
+RG_5G_TX_PA2_VCAS_F2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27085;"	d
+RG_5G_TX_PA2_VCAS_F3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27109;"	d
+RG_5G_TX_PA2_VCAS_F3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27107;"	d
+RG_5G_TX_PA2_VCAS_F3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27106;"	d
+RG_5G_TX_PA2_VCAS_F3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27108;"	d
+RG_5G_TX_PA2_VCAS_F3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27110;"	d
+RG_5G_TX_PA2_VCAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25224;"	d
+RG_5G_TX_PA2_VCAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25222;"	d
+RG_5G_TX_PA2_VCAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25221;"	d
+RG_5G_TX_PA2_VCAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25223;"	d
+RG_5G_TX_PA2_VCAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25225;"	d
+RG_5G_TX_PA3_VCAS_F0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27039;"	d
+RG_5G_TX_PA3_VCAS_F0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27037;"	d
+RG_5G_TX_PA3_VCAS_F0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27036;"	d
+RG_5G_TX_PA3_VCAS_F0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27038;"	d
+RG_5G_TX_PA3_VCAS_F0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27040;"	d
+RG_5G_TX_PA3_VCAS_F1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27064;"	d
+RG_5G_TX_PA3_VCAS_F1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27062;"	d
+RG_5G_TX_PA3_VCAS_F1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27061;"	d
+RG_5G_TX_PA3_VCAS_F1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27063;"	d
+RG_5G_TX_PA3_VCAS_F1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27065;"	d
+RG_5G_TX_PA3_VCAS_F2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27089;"	d
+RG_5G_TX_PA3_VCAS_F2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27087;"	d
+RG_5G_TX_PA3_VCAS_F2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27086;"	d
+RG_5G_TX_PA3_VCAS_F2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27088;"	d
+RG_5G_TX_PA3_VCAS_F2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27090;"	d
+RG_5G_TX_PA3_VCAS_F3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27114;"	d
+RG_5G_TX_PA3_VCAS_F3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27112;"	d
+RG_5G_TX_PA3_VCAS_F3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27111;"	d
+RG_5G_TX_PA3_VCAS_F3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27113;"	d
+RG_5G_TX_PA3_VCAS_F3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27115;"	d
+RG_5G_TX_PA3_VCAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25234;"	d
+RG_5G_TX_PA3_VCAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25232;"	d
+RG_5G_TX_PA3_VCAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25231;"	d
+RG_5G_TX_PA3_VCAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25233;"	d
+RG_5G_TX_PA3_VCAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25235;"	d
+RG_5G_TX_PAFB_EN_F0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27119;"	d
+RG_5G_TX_PAFB_EN_F0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27117;"	d
+RG_5G_TX_PAFB_EN_F0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27116;"	d
+RG_5G_TX_PAFB_EN_F0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27118;"	d
+RG_5G_TX_PAFB_EN_F0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27120;"	d
+RG_5G_TX_PAFB_EN_F1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27124;"	d
+RG_5G_TX_PAFB_EN_F1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27122;"	d
+RG_5G_TX_PAFB_EN_F1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27121;"	d
+RG_5G_TX_PAFB_EN_F1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27123;"	d
+RG_5G_TX_PAFB_EN_F1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27125;"	d
+RG_5G_TX_PAFB_EN_F2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27129;"	d
+RG_5G_TX_PAFB_EN_F2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27127;"	d
+RG_5G_TX_PAFB_EN_F2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27126;"	d
+RG_5G_TX_PAFB_EN_F2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27128;"	d
+RG_5G_TX_PAFB_EN_F2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27130;"	d
+RG_5G_TX_PAFB_EN_F3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27134;"	d
+RG_5G_TX_PAFB_EN_F3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27132;"	d
+RG_5G_TX_PAFB_EN_F3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27131;"	d
+RG_5G_TX_PAFB_EN_F3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27133;"	d
+RG_5G_TX_PAFB_EN_F3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27135;"	d
+RG_5G_TX_PAFB_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25214;"	d
+RG_5G_TX_PAFB_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25212;"	d
+RG_5G_TX_PAFB_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25211;"	d
+RG_5G_TX_PAFB_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25213;"	d
+RG_5G_TX_PAFB_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25215;"	d
+RG_5G_TX_PA_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24929;"	d
+RG_5G_TX_PA_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24927;"	d
+RG_5G_TX_PA_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24926;"	d
+RG_5G_TX_PA_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24928;"	d
+RG_5G_TX_PA_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24930;"	d
+RG_5G_TX_SELF_MIXER_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24979;"	d
+RG_5G_TX_SELF_MIXER_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24977;"	d
+RG_5G_TX_SELF_MIXER_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24976;"	d
+RG_5G_TX_SELF_MIXER_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24978;"	d
+RG_5G_TX_SELF_MIXER_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24980;"	d
+RG_5G_TX_TRSW_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24869;"	d
+RG_5G_TX_TRSW_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24867;"	d
+RG_5G_TX_TRSW_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24866;"	d
+RG_5G_TX_TRSW_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24868;"	d
+RG_5G_TX_TRSW_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24870;"	d
+RG_5G_TX_TSSI_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25144;"	d
+RG_5G_TX_TSSI_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25142;"	d
+RG_5G_TX_TSSI_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25141;"	d
+RG_5G_TX_TSSI_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25143;"	d
+RG_5G_TX_TSSI_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25145;"	d
+RG_5G_TX_TSSI_DIV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25149;"	d
+RG_5G_TX_TSSI_DIV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25147;"	d
+RG_5G_TX_TSSI_DIV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25146;"	d
+RG_5G_TX_TSSI_DIV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25148;"	d
+RG_5G_TX_TSSI_DIV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25150;"	d
+RG_5G_TX_TSSI_TESTMODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25159;"	d
+RG_5G_TX_TSSI_TESTMODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25157;"	d
+RG_5G_TX_TSSI_TESTMODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25156;"	d
+RG_5G_TX_TSSI_TESTMODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25158;"	d
+RG_5G_TX_TSSI_TESTMODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25160;"	d
+RG_5G_TX_TSSI_TEST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25154;"	d
+RG_5G_TX_TSSI_TEST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25152;"	d
+RG_5G_TX_TSSI_TEST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25151;"	d
+RG_5G_TX_TSSI_TEST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25153;"	d
+RG_5G_TX_TSSI_TEST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25155;"	d
+RG_AAC5GB_PDSW_EN_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26269;"	d
+RG_AAC5GB_PDSW_EN_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26267;"	d
+RG_AAC5GB_PDSW_EN_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26266;"	d
+RG_AAC5GB_PDSW_EN_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26268;"	d
+RG_AAC5GB_PDSW_EN_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26270;"	d
+RG_AAC5GB_TAR_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26264;"	d
+RG_AAC5GB_TAR_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26262;"	d
+RG_AAC5GB_TAR_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26261;"	d
+RG_AAC5GB_TAR_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26263;"	d
+RG_AAC5GB_TAR_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26265;"	d
+RG_ACI_DAGC_DONE_CNT_LMT_11GN_HI	include/ssv6200_aux.h	13469;"	d
+RG_ACI_DAGC_DONE_CNT_LMT_11GN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30659;"	d
+RG_ACI_DAGC_DONE_CNT_LMT_11GN_I_MSK	include/ssv6200_aux.h	13467;"	d
+RG_ACI_DAGC_DONE_CNT_LMT_11GN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30657;"	d
+RG_ACI_DAGC_DONE_CNT_LMT_11GN_MSK	include/ssv6200_aux.h	13466;"	d
+RG_ACI_DAGC_DONE_CNT_LMT_11GN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30656;"	d
+RG_ACI_DAGC_DONE_CNT_LMT_11GN_SFT	include/ssv6200_aux.h	13468;"	d
+RG_ACI_DAGC_DONE_CNT_LMT_11GN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30658;"	d
+RG_ACI_DAGC_DONE_CNT_LMT_11GN_SZ	include/ssv6200_aux.h	13470;"	d
+RG_ACI_DAGC_DONE_CNT_LMT_11GN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30660;"	d
+RG_ACI_DAGC_LEAKY_FACTOR_11B_HI	include/ssv6200_aux.h	13434;"	d
+RG_ACI_DAGC_LEAKY_FACTOR_11B_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30614;"	d
+RG_ACI_DAGC_LEAKY_FACTOR_11B_I_MSK	include/ssv6200_aux.h	13432;"	d
+RG_ACI_DAGC_LEAKY_FACTOR_11B_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30612;"	d
+RG_ACI_DAGC_LEAKY_FACTOR_11B_MSK	include/ssv6200_aux.h	13431;"	d
+RG_ACI_DAGC_LEAKY_FACTOR_11B_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30611;"	d
+RG_ACI_DAGC_LEAKY_FACTOR_11B_SFT	include/ssv6200_aux.h	13433;"	d
+RG_ACI_DAGC_LEAKY_FACTOR_11B_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30613;"	d
+RG_ACI_DAGC_LEAKY_FACTOR_11B_SZ	include/ssv6200_aux.h	13435;"	d
+RG_ACI_DAGC_LEAKY_FACTOR_11B_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30615;"	d
+RG_ACI_DAGC_LEAKY_FACTOR_11GN_HI	include/ssv6200_aux.h	13464;"	d
+RG_ACI_DAGC_LEAKY_FACTOR_11GN_HT20_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30649;"	d
+RG_ACI_DAGC_LEAKY_FACTOR_11GN_HT20_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30647;"	d
+RG_ACI_DAGC_LEAKY_FACTOR_11GN_HT20_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30646;"	d
+RG_ACI_DAGC_LEAKY_FACTOR_11GN_HT20_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30648;"	d
+RG_ACI_DAGC_LEAKY_FACTOR_11GN_HT20_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30650;"	d
+RG_ACI_DAGC_LEAKY_FACTOR_11GN_HT40_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30999;"	d
+RG_ACI_DAGC_LEAKY_FACTOR_11GN_HT40_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30997;"	d
+RG_ACI_DAGC_LEAKY_FACTOR_11GN_HT40_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30996;"	d
+RG_ACI_DAGC_LEAKY_FACTOR_11GN_HT40_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30998;"	d
+RG_ACI_DAGC_LEAKY_FACTOR_11GN_HT40_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31000;"	d
+RG_ACI_DAGC_LEAKY_FACTOR_11GN_I_MSK	include/ssv6200_aux.h	13462;"	d
+RG_ACI_DAGC_LEAKY_FACTOR_11GN_MSK	include/ssv6200_aux.h	13461;"	d
+RG_ACI_DAGC_LEAKY_FACTOR_11GN_SFT	include/ssv6200_aux.h	13463;"	d
+RG_ACI_DAGC_LEAKY_FACTOR_11GN_SZ	include/ssv6200_aux.h	13465;"	d
+RG_ACI_DAGC_PWR_SEL_11B_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30619;"	d
+RG_ACI_DAGC_PWR_SEL_11B_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30617;"	d
+RG_ACI_DAGC_PWR_SEL_11B_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30616;"	d
+RG_ACI_DAGC_PWR_SEL_11B_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30618;"	d
+RG_ACI_DAGC_PWR_SEL_11B_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30620;"	d
+RG_ACI_DAGC_PWR_SEL_11GN_HT20_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30654;"	d
+RG_ACI_DAGC_PWR_SEL_11GN_HT20_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30652;"	d
+RG_ACI_DAGC_PWR_SEL_11GN_HT20_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30651;"	d
+RG_ACI_DAGC_PWR_SEL_11GN_HT20_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30653;"	d
+RG_ACI_DAGC_PWR_SEL_11GN_HT20_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30655;"	d
+RG_ACI_DAGC_PWR_SEL_11GN_HT40_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31004;"	d
+RG_ACI_DAGC_PWR_SEL_11GN_HT40_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31002;"	d
+RG_ACI_DAGC_PWR_SEL_11GN_HT40_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31001;"	d
+RG_ACI_DAGC_PWR_SEL_11GN_HT40_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31003;"	d
+RG_ACI_DAGC_PWR_SEL_11GN_HT40_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31005;"	d
+RG_ACI_DAGC_SET_VALUE_11B_HI	include/ssv6200_aux.h	13449;"	d
+RG_ACI_DAGC_SET_VALUE_11B_I_MSK	include/ssv6200_aux.h	13447;"	d
+RG_ACI_DAGC_SET_VALUE_11B_MSK	include/ssv6200_aux.h	13446;"	d
+RG_ACI_DAGC_SET_VALUE_11B_SFT	include/ssv6200_aux.h	13448;"	d
+RG_ACI_DAGC_SET_VALUE_11B_SZ	include/ssv6200_aux.h	13450;"	d
+RG_ACI_DAGC_SET_VALUE_11GN_HI	include/ssv6200_aux.h	13474;"	d
+RG_ACI_DAGC_SET_VALUE_11GN_I_MSK	include/ssv6200_aux.h	13472;"	d
+RG_ACI_DAGC_SET_VALUE_11GN_MSK	include/ssv6200_aux.h	13471;"	d
+RG_ACI_DAGC_SET_VALUE_11GN_SFT	include/ssv6200_aux.h	13473;"	d
+RG_ACI_DAGC_SET_VALUE_11GN_SZ	include/ssv6200_aux.h	13475;"	d
+RG_ACI_DAGC_TARGET_11B_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30624;"	d
+RG_ACI_DAGC_TARGET_11B_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30622;"	d
+RG_ACI_DAGC_TARGET_11B_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30621;"	d
+RG_ACI_DAGC_TARGET_11B_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30623;"	d
+RG_ACI_DAGC_TARGET_11B_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30625;"	d
+RG_ACI_DAGC_TARGET_11GN_HT20_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30664;"	d
+RG_ACI_DAGC_TARGET_11GN_HT20_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30662;"	d
+RG_ACI_DAGC_TARGET_11GN_HT20_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30661;"	d
+RG_ACI_DAGC_TARGET_11GN_HT20_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30663;"	d
+RG_ACI_DAGC_TARGET_11GN_HT20_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30665;"	d
+RG_ACI_DAGC_TARGET_11GN_HT40_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31009;"	d
+RG_ACI_DAGC_TARGET_11GN_HT40_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31007;"	d
+RG_ACI_DAGC_TARGET_11GN_HT40_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31006;"	d
+RG_ACI_DAGC_TARGET_11GN_HT40_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31008;"	d
+RG_ACI_DAGC_TARGET_11GN_HT40_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31010;"	d
+RG_ACI_GAIN_HI	include/ssv6200_aux.h	15684;"	d
+RG_ACI_GAIN_INI_11B_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30629;"	d
+RG_ACI_GAIN_INI_11B_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30627;"	d
+RG_ACI_GAIN_INI_11B_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30626;"	d
+RG_ACI_GAIN_INI_11B_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30628;"	d
+RG_ACI_GAIN_INI_11B_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30630;"	d
+RG_ACI_GAIN_INI_11GN_HT20_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31029;"	d
+RG_ACI_GAIN_INI_11GN_HT20_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31027;"	d
+RG_ACI_GAIN_INI_11GN_HT20_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31026;"	d
+RG_ACI_GAIN_INI_11GN_HT20_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31028;"	d
+RG_ACI_GAIN_INI_11GN_HT20_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31030;"	d
+RG_ACI_GAIN_INI_11GN_HT40_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31024;"	d
+RG_ACI_GAIN_INI_11GN_HT40_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31022;"	d
+RG_ACI_GAIN_INI_11GN_HT40_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31021;"	d
+RG_ACI_GAIN_INI_11GN_HT40_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31023;"	d
+RG_ACI_GAIN_INI_11GN_HT40_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31025;"	d
+RG_ACI_GAIN_INI_VAL_11GN_HI	include/ssv6200_aux.h	13479;"	d
+RG_ACI_GAIN_INI_VAL_11GN_I_MSK	include/ssv6200_aux.h	13477;"	d
+RG_ACI_GAIN_INI_VAL_11GN_MSK	include/ssv6200_aux.h	13476;"	d
+RG_ACI_GAIN_INI_VAL_11GN_SFT	include/ssv6200_aux.h	13478;"	d
+RG_ACI_GAIN_INI_VAL_11GN_SZ	include/ssv6200_aux.h	13480;"	d
+RG_ACI_GAIN_I_MSK	include/ssv6200_aux.h	15682;"	d
+RG_ACI_GAIN_MSK	include/ssv6200_aux.h	15681;"	d
+RG_ACI_GAIN_OW_11B_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30639;"	d
+RG_ACI_GAIN_OW_11B_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30637;"	d
+RG_ACI_GAIN_OW_11B_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30636;"	d
+RG_ACI_GAIN_OW_11B_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30638;"	d
+RG_ACI_GAIN_OW_11B_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30640;"	d
+RG_ACI_GAIN_OW_11GN_HI	include/ssv6200_aux.h	13489;"	d
+RG_ACI_GAIN_OW_11GN_HT20_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30674;"	d
+RG_ACI_GAIN_OW_11GN_HT20_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30672;"	d
+RG_ACI_GAIN_OW_11GN_HT20_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30671;"	d
+RG_ACI_GAIN_OW_11GN_HT20_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30673;"	d
+RG_ACI_GAIN_OW_11GN_HT20_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30675;"	d
+RG_ACI_GAIN_OW_11GN_HT40_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31019;"	d
+RG_ACI_GAIN_OW_11GN_HT40_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31017;"	d
+RG_ACI_GAIN_OW_11GN_HT40_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31016;"	d
+RG_ACI_GAIN_OW_11GN_HT40_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31018;"	d
+RG_ACI_GAIN_OW_11GN_HT40_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31020;"	d
+RG_ACI_GAIN_OW_11GN_I_MSK	include/ssv6200_aux.h	13487;"	d
+RG_ACI_GAIN_OW_11GN_MSK	include/ssv6200_aux.h	13486;"	d
+RG_ACI_GAIN_OW_11GN_SFT	include/ssv6200_aux.h	13488;"	d
+RG_ACI_GAIN_OW_11GN_SZ	include/ssv6200_aux.h	13490;"	d
+RG_ACI_GAIN_OW_VAL_11GN_HI	include/ssv6200_aux.h	13484;"	d
+RG_ACI_GAIN_OW_VAL_11GN_I_MSK	include/ssv6200_aux.h	13482;"	d
+RG_ACI_GAIN_OW_VAL_11GN_MSK	include/ssv6200_aux.h	13481;"	d
+RG_ACI_GAIN_OW_VAL_11GN_SFT	include/ssv6200_aux.h	13483;"	d
+RG_ACI_GAIN_OW_VAL_11GN_SZ	include/ssv6200_aux.h	13485;"	d
+RG_ACI_GAIN_SET_11B_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30634;"	d
+RG_ACI_GAIN_SET_11B_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30632;"	d
+RG_ACI_GAIN_SET_11B_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30631;"	d
+RG_ACI_GAIN_SET_11B_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30633;"	d
+RG_ACI_GAIN_SET_11B_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30635;"	d
+RG_ACI_GAIN_SET_11GN_HT20_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30669;"	d
+RG_ACI_GAIN_SET_11GN_HT20_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30667;"	d
+RG_ACI_GAIN_SET_11GN_HT20_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30666;"	d
+RG_ACI_GAIN_SET_11GN_HT20_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30668;"	d
+RG_ACI_GAIN_SET_11GN_HT20_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30670;"	d
+RG_ACI_GAIN_SET_11GN_HT40_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31014;"	d
+RG_ACI_GAIN_SET_11GN_HT40_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31012;"	d
+RG_ACI_GAIN_SET_11GN_HT40_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31011;"	d
+RG_ACI_GAIN_SET_11GN_HT40_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31013;"	d
+RG_ACI_GAIN_SET_11GN_HT40_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31015;"	d
+RG_ACI_GAIN_SFT	include/ssv6200_aux.h	15683;"	d
+RG_ACI_GAIN_SZ	include/ssv6200_aux.h	15685;"	d
+RG_ACI_POINT_CNT_LMT_11B_HI	include/ssv6200_aux.h	13429;"	d
+RG_ACI_POINT_CNT_LMT_11B_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30609;"	d
+RG_ACI_POINT_CNT_LMT_11B_I_MSK	include/ssv6200_aux.h	13427;"	d
+RG_ACI_POINT_CNT_LMT_11B_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30607;"	d
+RG_ACI_POINT_CNT_LMT_11B_MSK	include/ssv6200_aux.h	13426;"	d
+RG_ACI_POINT_CNT_LMT_11B_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30606;"	d
+RG_ACI_POINT_CNT_LMT_11B_SFT	include/ssv6200_aux.h	13428;"	d
+RG_ACI_POINT_CNT_LMT_11B_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30608;"	d
+RG_ACI_POINT_CNT_LMT_11B_SZ	include/ssv6200_aux.h	13430;"	d
+RG_ACI_POINT_CNT_LMT_11B_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30610;"	d
+RG_ACI_POINT_CNT_LMT_11GN_HI	include/ssv6200_aux.h	13459;"	d
+RG_ACI_POINT_CNT_LMT_11GN_HT20_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30644;"	d
+RG_ACI_POINT_CNT_LMT_11GN_HT20_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30642;"	d
+RG_ACI_POINT_CNT_LMT_11GN_HT20_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30641;"	d
+RG_ACI_POINT_CNT_LMT_11GN_HT20_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30643;"	d
+RG_ACI_POINT_CNT_LMT_11GN_HT20_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30645;"	d
+RG_ACI_POINT_CNT_LMT_11GN_HT40_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30994;"	d
+RG_ACI_POINT_CNT_LMT_11GN_HT40_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30992;"	d
+RG_ACI_POINT_CNT_LMT_11GN_HT40_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30991;"	d
+RG_ACI_POINT_CNT_LMT_11GN_HT40_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30993;"	d
+RG_ACI_POINT_CNT_LMT_11GN_HT40_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30995;"	d
+RG_ACI_POINT_CNT_LMT_11GN_I_MSK	include/ssv6200_aux.h	13457;"	d
+RG_ACI_POINT_CNT_LMT_11GN_MSK	include/ssv6200_aux.h	13456;"	d
+RG_ACI_POINT_CNT_LMT_11GN_SFT	include/ssv6200_aux.h	13458;"	d
+RG_ACI_POINT_CNT_LMT_11GN_SZ	include/ssv6200_aux.h	13460;"	d
+RG_ACS_INI_PM_ALL0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32459;"	d
+RG_ACS_INI_PM_ALL0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32457;"	d
+RG_ACS_INI_PM_ALL0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32456;"	d
+RG_ACS_INI_PM_ALL0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32458;"	d
+RG_ACS_INI_PM_ALL0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32460;"	d
+RG_ADC2LA_CLKPH_HI	include/ssv6200_aux.h	15724;"	d
+RG_ADC2LA_CLKPH_I_MSK	include/ssv6200_aux.h	15722;"	d
+RG_ADC2LA_CLKPH_MSK	include/ssv6200_aux.h	15721;"	d
+RG_ADC2LA_CLKPH_SFT	include/ssv6200_aux.h	15723;"	d
+RG_ADC2LA_CLKPH_SZ	include/ssv6200_aux.h	15725;"	d
+RG_ADC2LA_SEL_HI	include/ssv6200_aux.h	15719;"	d
+RG_ADC2LA_SEL_I_MSK	include/ssv6200_aux.h	15717;"	d
+RG_ADC2LA_SEL_MSK	include/ssv6200_aux.h	15716;"	d
+RG_ADC2LA_SEL_SFT	include/ssv6200_aux.h	15718;"	d
+RG_ADC2LA_SEL_SZ	include/ssv6200_aux.h	15720;"	d
+RG_ADC_CLKSEL_HI	include/ssv6200_aux.h	16759;"	d
+RG_ADC_CLKSEL_I_MSK	include/ssv6200_aux.h	16757;"	d
+RG_ADC_CLKSEL_MSK	include/ssv6200_aux.h	16756;"	d
+RG_ADC_CLKSEL_SFT	include/ssv6200_aux.h	16758;"	d
+RG_ADC_CLKSEL_SZ	include/ssv6200_aux.h	16760;"	d
+RG_ADC_DIBIAS_HI	include/ssv6200_aux.h	16764;"	d
+RG_ADC_DIBIAS_I_MSK	include/ssv6200_aux.h	16762;"	d
+RG_ADC_DIBIAS_MSK	include/ssv6200_aux.h	16761;"	d
+RG_ADC_DIBIAS_SFT	include/ssv6200_aux.h	16763;"	d
+RG_ADC_DIBIAS_SZ	include/ssv6200_aux.h	16765;"	d
+RG_ADC_DIVR_HI	include/ssv6200_aux.h	16769;"	d
+RG_ADC_DIVR_I_MSK	include/ssv6200_aux.h	16767;"	d
+RG_ADC_DIVR_MSK	include/ssv6200_aux.h	16766;"	d
+RG_ADC_DIVR_SFT	include/ssv6200_aux.h	16768;"	d
+RG_ADC_DIVR_SZ	include/ssv6200_aux.h	16770;"	d
+RG_ADC_DVCMI_HI	include/ssv6200_aux.h	16774;"	d
+RG_ADC_DVCMI_I_MSK	include/ssv6200_aux.h	16772;"	d
+RG_ADC_DVCMI_MSK	include/ssv6200_aux.h	16771;"	d
+RG_ADC_DVCMI_SFT	include/ssv6200_aux.h	16773;"	d
+RG_ADC_DVCMI_SZ	include/ssv6200_aux.h	16775;"	d
+RG_ADC_EDGE_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27214;"	d
+RG_ADC_EDGE_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27212;"	d
+RG_ADC_EDGE_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27211;"	d
+RG_ADC_EDGE_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27213;"	d
+RG_ADC_EDGE_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27215;"	d
+RG_ADC_SAMSEL_HI	include/ssv6200_aux.h	16779;"	d
+RG_ADC_SAMSEL_I_MSK	include/ssv6200_aux.h	16777;"	d
+RG_ADC_SAMSEL_MSK	include/ssv6200_aux.h	16776;"	d
+RG_ADC_SAMSEL_SFT	include/ssv6200_aux.h	16778;"	d
+RG_ADC_SAMSEL_SZ	include/ssv6200_aux.h	16780;"	d
+RG_ADC_STNBY_HI	include/ssv6200_aux.h	16784;"	d
+RG_ADC_STNBY_I_MSK	include/ssv6200_aux.h	16782;"	d
+RG_ADC_STNBY_MSK	include/ssv6200_aux.h	16781;"	d
+RG_ADC_STNBY_SFT	include/ssv6200_aux.h	16783;"	d
+RG_ADC_STNBY_SZ	include/ssv6200_aux.h	16785;"	d
+RG_ADC_TESTMODE_HI	include/ssv6200_aux.h	16789;"	d
+RG_ADC_TESTMODE_I_MSK	include/ssv6200_aux.h	16787;"	d
+RG_ADC_TESTMODE_MSK	include/ssv6200_aux.h	16786;"	d
+RG_ADC_TESTMODE_SFT	include/ssv6200_aux.h	16788;"	d
+RG_ADC_TESTMODE_SZ	include/ssv6200_aux.h	16790;"	d
+RG_ADC_TSEL_HI	include/ssv6200_aux.h	16794;"	d
+RG_ADC_TSEL_I_MSK	include/ssv6200_aux.h	16792;"	d
+RG_ADC_TSEL_MSK	include/ssv6200_aux.h	16791;"	d
+RG_ADC_TSEL_SFT	include/ssv6200_aux.h	16793;"	d
+RG_ADC_TSEL_SZ	include/ssv6200_aux.h	16795;"	d
+RG_ADC_VRSEL_HI	include/ssv6200_aux.h	16799;"	d
+RG_ADC_VRSEL_I_MSK	include/ssv6200_aux.h	16797;"	d
+RG_ADC_VRSEL_MSK	include/ssv6200_aux.h	16796;"	d
+RG_ADC_VRSEL_SFT	include/ssv6200_aux.h	16798;"	d
+RG_ADC_VRSEL_SZ	include/ssv6200_aux.h	16800;"	d
+RG_ADEDGE_SEL_HI	include/ssv6200_aux.h	12989;"	d
+RG_ADEDGE_SEL_I_MSK	include/ssv6200_aux.h	12987;"	d
+RG_ADEDGE_SEL_MSK	include/ssv6200_aux.h	12986;"	d
+RG_ADEDGE_SEL_SFT	include/ssv6200_aux.h	12988;"	d
+RG_ADEDGE_SEL_SZ	include/ssv6200_aux.h	12990;"	d
+RG_AGC_RELOCK_11B_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30889;"	d
+RG_AGC_RELOCK_11B_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30887;"	d
+RG_AGC_RELOCK_11B_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30886;"	d
+RG_AGC_RELOCK_11B_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30888;"	d
+RG_AGC_RELOCK_11B_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30890;"	d
+RG_AGC_RELOCK_11GN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30884;"	d
+RG_AGC_RELOCK_11GN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30882;"	d
+RG_AGC_RELOCK_11GN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30881;"	d
+RG_AGC_RELOCK_11GN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30883;"	d
+RG_AGC_RELOCK_11GN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30885;"	d
+RG_AGC_RELOCK_CNT_DIFFDB_TH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30899;"	d
+RG_AGC_RELOCK_CNT_DIFFDB_TH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30897;"	d
+RG_AGC_RELOCK_CNT_DIFFDB_TH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30896;"	d
+RG_AGC_RELOCK_CNT_DIFFDB_TH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30898;"	d
+RG_AGC_RELOCK_CNT_DIFFDB_TH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30900;"	d
+RG_AGC_RELOCK_CNT_TH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30869;"	d
+RG_AGC_RELOCK_CNT_TH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30867;"	d
+RG_AGC_RELOCK_CNT_TH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30866;"	d
+RG_AGC_RELOCK_CNT_TH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30868;"	d
+RG_AGC_RELOCK_CNT_TH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30870;"	d
+RG_AGC_RELOCK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30879;"	d
+RG_AGC_RELOCK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30877;"	d
+RG_AGC_RELOCK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30876;"	d
+RG_AGC_RELOCK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30878;"	d
+RG_AGC_RELOCK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30880;"	d
+RG_AGC_RELOCK_PWR_DIFFDB_TH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30894;"	d
+RG_AGC_RELOCK_PWR_DIFFDB_TH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30892;"	d
+RG_AGC_RELOCK_PWR_DIFFDB_TH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30891;"	d
+RG_AGC_RELOCK_PWR_DIFFDB_TH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30893;"	d
+RG_AGC_RELOCK_PWR_DIFFDB_TH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30895;"	d
+RG_AGC_RELOCK_PWR_TH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30864;"	d
+RG_AGC_RELOCK_PWR_TH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30862;"	d
+RG_AGC_RELOCK_PWR_TH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30861;"	d
+RG_AGC_RELOCK_PWR_TH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30863;"	d
+RG_AGC_RELOCK_PWR_TH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30865;"	d
+RG_AGC_RELOCK_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30874;"	d
+RG_AGC_RELOCK_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30872;"	d
+RG_AGC_RELOCK_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30871;"	d
+RG_AGC_RELOCK_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30873;"	d
+RG_AGC_RELOCK_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30875;"	d
+RG_AGC_THRESHOLD_HI	include/ssv6200_aux.h	13424;"	d
+RG_AGC_THRESHOLD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30604;"	d
+RG_AGC_THRESHOLD_I_MSK	include/ssv6200_aux.h	13422;"	d
+RG_AGC_THRESHOLD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30602;"	d
+RG_AGC_THRESHOLD_MSK	include/ssv6200_aux.h	13421;"	d
+RG_AGC_THRESHOLD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30601;"	d
+RG_AGC_THRESHOLD_SFT	include/ssv6200_aux.h	13423;"	d
+RG_AGC_THRESHOLD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30603;"	d
+RG_AGC_THRESHOLD_SZ	include/ssv6200_aux.h	13425;"	d
+RG_AGC_THRESHOLD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30605;"	d
+RG_AGGREGATE_HI	include/ssv6200_aux.h	13189;"	d
+RG_AGGREGATE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30379;"	d
+RG_AGGREGATE_I_MSK	include/ssv6200_aux.h	13187;"	d
+RG_AGGREGATE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30377;"	d
+RG_AGGREGATE_MSK	include/ssv6200_aux.h	13186;"	d
+RG_AGGREGATE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30376;"	d
+RG_AGGREGATE_SFT	include/ssv6200_aux.h	13188;"	d
+RG_AGGREGATE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30378;"	d
+RG_AGGREGATE_SZ	include/ssv6200_aux.h	13190;"	d
+RG_AGGREGATE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30380;"	d
+RG_ALPHA_COARSE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32809;"	d
+RG_ALPHA_COARSE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32807;"	d
+RG_ALPHA_COARSE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32806;"	d
+RG_ALPHA_COARSE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32808;"	d
+RG_ALPHA_COARSE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32810;"	d
+RG_ALPHA_FINE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32804;"	d
+RG_ALPHA_FINE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32802;"	d
+RG_ALPHA_FINE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32801;"	d
+RG_ALPHA_FINE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32803;"	d
+RG_ALPHA_FINE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32805;"	d
+RG_ALPHA_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27469;"	d
+RG_ALPHA_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27467;"	d
+RG_ALPHA_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27466;"	d
+RG_ALPHA_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27468;"	d
+RG_ALPHA_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27470;"	d
+RG_ANT_SW_0_HI	include/ssv6200_aux.h	13869;"	d
+RG_ANT_SW_0_I_MSK	include/ssv6200_aux.h	13867;"	d
+RG_ANT_SW_0_MSK	include/ssv6200_aux.h	13866;"	d
+RG_ANT_SW_0_SFT	include/ssv6200_aux.h	13868;"	d
+RG_ANT_SW_0_SZ	include/ssv6200_aux.h	13870;"	d
+RG_ANT_SW_1_HI	include/ssv6200_aux.h	13874;"	d
+RG_ANT_SW_1_I_MSK	include/ssv6200_aux.h	13872;"	d
+RG_ANT_SW_1_MSK	include/ssv6200_aux.h	13871;"	d
+RG_ANT_SW_1_SFT	include/ssv6200_aux.h	13873;"	d
+RG_ANT_SW_1_SZ	include/ssv6200_aux.h	13875;"	d
+RG_ATCOR16_CCA_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32569;"	d
+RG_ATCOR16_CCA_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32567;"	d
+RG_ATCOR16_CCA_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32566;"	d
+RG_ATCOR16_CCA_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32568;"	d
+RG_ATCOR16_CCA_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32570;"	d
+RG_ATCOR16_CNT_LMT1_HI	include/ssv6200_aux.h	14819;"	d
+RG_ATCOR16_CNT_LMT1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32059;"	d
+RG_ATCOR16_CNT_LMT1_I_MSK	include/ssv6200_aux.h	14817;"	d
+RG_ATCOR16_CNT_LMT1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32057;"	d
+RG_ATCOR16_CNT_LMT1_MSK	include/ssv6200_aux.h	14816;"	d
+RG_ATCOR16_CNT_LMT1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32056;"	d
+RG_ATCOR16_CNT_LMT1_SFT	include/ssv6200_aux.h	14818;"	d
+RG_ATCOR16_CNT_LMT1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32058;"	d
+RG_ATCOR16_CNT_LMT1_SZ	include/ssv6200_aux.h	14820;"	d
+RG_ATCOR16_CNT_LMT1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32060;"	d
+RG_ATCOR16_CNT_LMT2_HI	include/ssv6200_aux.h	14814;"	d
+RG_ATCOR16_CNT_LMT2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32054;"	d
+RG_ATCOR16_CNT_LMT2_I_MSK	include/ssv6200_aux.h	14812;"	d
+RG_ATCOR16_CNT_LMT2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32052;"	d
+RG_ATCOR16_CNT_LMT2_MSK	include/ssv6200_aux.h	14811;"	d
+RG_ATCOR16_CNT_LMT2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32051;"	d
+RG_ATCOR16_CNT_LMT2_SFT	include/ssv6200_aux.h	14813;"	d
+RG_ATCOR16_CNT_LMT2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32053;"	d
+RG_ATCOR16_CNT_LMT2_SZ	include/ssv6200_aux.h	14815;"	d
+RG_ATCOR16_CNT_LMT2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32055;"	d
+RG_ATCOR16_CNT_PLUS_LMT1_HI	include/ssv6200_aux.h	14939;"	d
+RG_ATCOR16_CNT_PLUS_LMT1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32179;"	d
+RG_ATCOR16_CNT_PLUS_LMT1_I_MSK	include/ssv6200_aux.h	14937;"	d
+RG_ATCOR16_CNT_PLUS_LMT1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32177;"	d
+RG_ATCOR16_CNT_PLUS_LMT1_MSK	include/ssv6200_aux.h	14936;"	d
+RG_ATCOR16_CNT_PLUS_LMT1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32176;"	d
+RG_ATCOR16_CNT_PLUS_LMT1_SFT	include/ssv6200_aux.h	14938;"	d
+RG_ATCOR16_CNT_PLUS_LMT1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32178;"	d
+RG_ATCOR16_CNT_PLUS_LMT1_SZ	include/ssv6200_aux.h	14940;"	d
+RG_ATCOR16_CNT_PLUS_LMT1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32180;"	d
+RG_ATCOR16_CNT_PLUS_LMT2_HI	include/ssv6200_aux.h	14934;"	d
+RG_ATCOR16_CNT_PLUS_LMT2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32174;"	d
+RG_ATCOR16_CNT_PLUS_LMT2_I_MSK	include/ssv6200_aux.h	14932;"	d
+RG_ATCOR16_CNT_PLUS_LMT2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32172;"	d
+RG_ATCOR16_CNT_PLUS_LMT2_MSK	include/ssv6200_aux.h	14931;"	d
+RG_ATCOR16_CNT_PLUS_LMT2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32171;"	d
+RG_ATCOR16_CNT_PLUS_LMT2_SFT	include/ssv6200_aux.h	14933;"	d
+RG_ATCOR16_CNT_PLUS_LMT2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32173;"	d
+RG_ATCOR16_CNT_PLUS_LMT2_SZ	include/ssv6200_aux.h	14935;"	d
+RG_ATCOR16_CNT_PLUS_LMT2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32175;"	d
+RG_ATCOR16_CNT_TH_HI	include/ssv6200_aux.h	14849;"	d
+RG_ATCOR16_CNT_TH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32089;"	d
+RG_ATCOR16_CNT_TH_I_MSK	include/ssv6200_aux.h	14847;"	d
+RG_ATCOR16_CNT_TH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32087;"	d
+RG_ATCOR16_CNT_TH_MSK	include/ssv6200_aux.h	14846;"	d
+RG_ATCOR16_CNT_TH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32086;"	d
+RG_ATCOR16_CNT_TH_SFT	include/ssv6200_aux.h	14848;"	d
+RG_ATCOR16_CNT_TH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32088;"	d
+RG_ATCOR16_CNT_TH_SZ	include/ssv6200_aux.h	14850;"	d
+RG_ATCOR16_CNT_TH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32090;"	d
+RG_ATCOR16_RATIO_CCD_HI	include/ssv6200_aux.h	14989;"	d
+RG_ATCOR16_RATIO_CCD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32409;"	d
+RG_ATCOR16_RATIO_CCD_I_MSK	include/ssv6200_aux.h	14987;"	d
+RG_ATCOR16_RATIO_CCD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32407;"	d
+RG_ATCOR16_RATIO_CCD_MSK	include/ssv6200_aux.h	14986;"	d
+RG_ATCOR16_RATIO_CCD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32406;"	d
+RG_ATCOR16_RATIO_CCD_SFT	include/ssv6200_aux.h	14988;"	d
+RG_ATCOR16_RATIO_CCD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32408;"	d
+RG_ATCOR16_RATIO_CCD_SZ	include/ssv6200_aux.h	14990;"	d
+RG_ATCOR16_RATIO_CCD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32410;"	d
+RG_ATCOR16_RATIO_SB_HI	include/ssv6200_aux.h	14824;"	d
+RG_ATCOR16_RATIO_SB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32064;"	d
+RG_ATCOR16_RATIO_SB_I_MSK	include/ssv6200_aux.h	14822;"	d
+RG_ATCOR16_RATIO_SB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32062;"	d
+RG_ATCOR16_RATIO_SB_MSK	include/ssv6200_aux.h	14821;"	d
+RG_ATCOR16_RATIO_SB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32061;"	d
+RG_ATCOR16_RATIO_SB_SFT	include/ssv6200_aux.h	14823;"	d
+RG_ATCOR16_RATIO_SB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32063;"	d
+RG_ATCOR16_RATIO_SB_SZ	include/ssv6200_aux.h	14825;"	d
+RG_ATCOR16_RATIO_SB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32065;"	d
+RG_ATCOR16_SHORT_CNT_LMT2_HI	include/ssv6200_aux.h	14999;"	d
+RG_ATCOR16_SHORT_CNT_LMT2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32419;"	d
+RG_ATCOR16_SHORT_CNT_LMT2_I_MSK	include/ssv6200_aux.h	14997;"	d
+RG_ATCOR16_SHORT_CNT_LMT2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32417;"	d
+RG_ATCOR16_SHORT_CNT_LMT2_MSK	include/ssv6200_aux.h	14996;"	d
+RG_ATCOR16_SHORT_CNT_LMT2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32416;"	d
+RG_ATCOR16_SHORT_CNT_LMT2_SFT	include/ssv6200_aux.h	14998;"	d
+RG_ATCOR16_SHORT_CNT_LMT2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32418;"	d
+RG_ATCOR16_SHORT_CNT_LMT2_SZ	include/ssv6200_aux.h	15000;"	d
+RG_ATCOR16_SHORT_CNT_LMT2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32420;"	d
+RG_ATCOR16_SHORT_CNT_LMT_HI	include/ssv6200_aux.h	14984;"	d
+RG_ATCOR16_SHORT_CNT_LMT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32404;"	d
+RG_ATCOR16_SHORT_CNT_LMT_I_MSK	include/ssv6200_aux.h	14982;"	d
+RG_ATCOR16_SHORT_CNT_LMT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32402;"	d
+RG_ATCOR16_SHORT_CNT_LMT_MSK	include/ssv6200_aux.h	14981;"	d
+RG_ATCOR16_SHORT_CNT_LMT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32401;"	d
+RG_ATCOR16_SHORT_CNT_LMT_SFT	include/ssv6200_aux.h	14983;"	d
+RG_ATCOR16_SHORT_CNT_LMT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32403;"	d
+RG_ATCOR16_SHORT_CNT_LMT_SZ	include/ssv6200_aux.h	14985;"	d
+RG_ATCOR16_SHORT_CNT_LMT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32405;"	d
+RG_ATCOR64_ACC_LMT_HI	include/ssv6200_aux.h	14994;"	d
+RG_ATCOR64_ACC_LMT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32414;"	d
+RG_ATCOR64_ACC_LMT_I_MSK	include/ssv6200_aux.h	14992;"	d
+RG_ATCOR64_ACC_LMT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32412;"	d
+RG_ATCOR64_ACC_LMT_MSK	include/ssv6200_aux.h	14991;"	d
+RG_ATCOR64_ACC_LMT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32411;"	d
+RG_ATCOR64_ACC_LMT_SFT	include/ssv6200_aux.h	14993;"	d
+RG_ATCOR64_ACC_LMT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32413;"	d
+RG_ATCOR64_ACC_LMT_SZ	include/ssv6200_aux.h	14995;"	d
+RG_ATCOR64_ACC_LMT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32415;"	d
+RG_ATCOR64_CNT_LMT_HI	include/ssv6200_aux.h	14809;"	d
+RG_ATCOR64_CNT_LMT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32049;"	d
+RG_ATCOR64_CNT_LMT_I_MSK	include/ssv6200_aux.h	14807;"	d
+RG_ATCOR64_CNT_LMT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32047;"	d
+RG_ATCOR64_CNT_LMT_MSK	include/ssv6200_aux.h	14806;"	d
+RG_ATCOR64_CNT_LMT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32046;"	d
+RG_ATCOR64_CNT_LMT_SFT	include/ssv6200_aux.h	14808;"	d
+RG_ATCOR64_CNT_LMT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32048;"	d
+RG_ATCOR64_CNT_LMT_SZ	include/ssv6200_aux.h	14810;"	d
+RG_ATCOR64_CNT_LMT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32050;"	d
+RG_ATCOR64_FREQ_START_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32559;"	d
+RG_ATCOR64_FREQ_START_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32557;"	d
+RG_ATCOR64_FREQ_START_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32556;"	d
+RG_ATCOR64_FREQ_START_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32558;"	d
+RG_ATCOR64_FREQ_START_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32560;"	d
+RG_AUDIO_ALPHA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27814;"	d
+RG_AUDIO_ALPHA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27812;"	d
+RG_AUDIO_ALPHA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27811;"	d
+RG_AUDIO_ALPHA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27813;"	d
+RG_AUDIO_ALPHA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27815;"	d
+RG_AUDIO_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31424;"	d
+RG_AUDIO_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31422;"	d
+RG_AUDIO_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31421;"	d
+RG_AUDIO_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31423;"	d
+RG_AUDIO_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31425;"	d
+RG_AUDIO_CLK_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31429;"	d
+RG_AUDIO_CLK_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31427;"	d
+RG_AUDIO_CLK_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31426;"	d
+RG_AUDIO_CLK_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31428;"	d
+RG_AUDIO_CLK_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31430;"	d
+RG_AUDIO_FIL_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27819;"	d
+RG_AUDIO_FIL_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27817;"	d
+RG_AUDIO_FIL_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27816;"	d
+RG_AUDIO_FIL_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27818;"	d
+RG_AUDIO_FIL_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27820;"	d
+RG_AUDIO_TYPE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27844;"	d
+RG_AUDIO_TYPE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27842;"	d
+RG_AUDIO_TYPE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27841;"	d
+RG_AUDIO_TYPE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27843;"	d
+RG_AUDIO_TYPE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27845;"	d
+RG_AUDIO_VOLUME_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27809;"	d
+RG_AUDIO_VOLUME_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27807;"	d
+RG_AUDIO_VOLUME_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27806;"	d
+RG_AUDIO_VOLUME_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27808;"	d
+RG_AUDIO_VOLUME_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27810;"	d
+RG_BB_11B_FALL_TIME_HI	include/ssv6200_aux.h	14304;"	d
+RG_BB_11B_FALL_TIME_I_MSK	include/ssv6200_aux.h	14302;"	d
+RG_BB_11B_FALL_TIME_MSK	include/ssv6200_aux.h	14301;"	d
+RG_BB_11B_FALL_TIME_SFT	include/ssv6200_aux.h	14303;"	d
+RG_BB_11B_FALL_TIME_SZ	include/ssv6200_aux.h	14305;"	d
+RG_BB_11B_RISE_TIME_HI	include/ssv6200_aux.h	14299;"	d
+RG_BB_11B_RISE_TIME_I_MSK	include/ssv6200_aux.h	14297;"	d
+RG_BB_11B_RISE_TIME_MSK	include/ssv6200_aux.h	14296;"	d
+RG_BB_11B_RISE_TIME_SFT	include/ssv6200_aux.h	14298;"	d
+RG_BB_11B_RISE_TIME_SZ	include/ssv6200_aux.h	14300;"	d
+RG_BB_11GN_FALL_TIME_HI	include/ssv6200_aux.h	14684;"	d
+RG_BB_11GN_FALL_TIME_I_MSK	include/ssv6200_aux.h	14682;"	d
+RG_BB_11GN_FALL_TIME_MSK	include/ssv6200_aux.h	14681;"	d
+RG_BB_11GN_FALL_TIME_SFT	include/ssv6200_aux.h	14683;"	d
+RG_BB_11GN_FALL_TIME_SZ	include/ssv6200_aux.h	14685;"	d
+RG_BB_11GN_RISE_TIME_HI	include/ssv6200_aux.h	14679;"	d
+RG_BB_11GN_RISE_TIME_I_MSK	include/ssv6200_aux.h	14677;"	d
+RG_BB_11GN_RISE_TIME_MSK	include/ssv6200_aux.h	14676;"	d
+RG_BB_11GN_RISE_TIME_SFT	include/ssv6200_aux.h	14678;"	d
+RG_BB_11GN_RISE_TIME_SZ	include/ssv6200_aux.h	14680;"	d
+RG_BB_CLK_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30259;"	d
+RG_BB_CLK_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30257;"	d
+RG_BB_CLK_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30256;"	d
+RG_BB_CLK_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30258;"	d
+RG_BB_CLK_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30260;"	d
+RG_BB_FALL_TIME_11B_TX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31484;"	d
+RG_BB_FALL_TIME_11B_TX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31482;"	d
+RG_BB_FALL_TIME_11B_TX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31481;"	d
+RG_BB_FALL_TIME_11B_TX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31483;"	d
+RG_BB_FALL_TIME_11B_TX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31485;"	d
+RG_BB_FALL_TIME_11GN_TX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31919;"	d
+RG_BB_FALL_TIME_11GN_TX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31917;"	d
+RG_BB_FALL_TIME_11GN_TX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31916;"	d
+RG_BB_FALL_TIME_11GN_TX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31918;"	d
+RG_BB_FALL_TIME_11GN_TX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31920;"	d
+RG_BB_RISE_TIME_11B_TX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31479;"	d
+RG_BB_RISE_TIME_11B_TX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31477;"	d
+RG_BB_RISE_TIME_11B_TX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31476;"	d
+RG_BB_RISE_TIME_11B_TX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31478;"	d
+RG_BB_RISE_TIME_11B_TX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31480;"	d
+RG_BB_RISE_TIME_11GN_TX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31914;"	d
+RG_BB_RISE_TIME_11GN_TX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31912;"	d
+RG_BB_RISE_TIME_11GN_TX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31911;"	d
+RG_BB_RISE_TIME_11GN_TX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31913;"	d
+RG_BB_RISE_TIME_11GN_TX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31915;"	d
+RG_BB_SCALE_BARKER_CCK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31129;"	d
+RG_BB_SCALE_BARKER_CCK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31127;"	d
+RG_BB_SCALE_BARKER_CCK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31126;"	d
+RG_BB_SCALE_BARKER_CCK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31128;"	d
+RG_BB_SCALE_BARKER_CCK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31130;"	d
+RG_BB_SCALE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30404;"	d
+RG_BB_SCALE_HT20_16QAM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31164;"	d
+RG_BB_SCALE_HT20_16QAM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31162;"	d
+RG_BB_SCALE_HT20_16QAM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31161;"	d
+RG_BB_SCALE_HT20_16QAM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31163;"	d
+RG_BB_SCALE_HT20_16QAM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31165;"	d
+RG_BB_SCALE_HT20_64QAM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31159;"	d
+RG_BB_SCALE_HT20_64QAM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31157;"	d
+RG_BB_SCALE_HT20_64QAM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31156;"	d
+RG_BB_SCALE_HT20_64QAM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31158;"	d
+RG_BB_SCALE_HT20_64QAM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31160;"	d
+RG_BB_SCALE_HT20_BPSK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31174;"	d
+RG_BB_SCALE_HT20_BPSK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31172;"	d
+RG_BB_SCALE_HT20_BPSK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31171;"	d
+RG_BB_SCALE_HT20_BPSK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31173;"	d
+RG_BB_SCALE_HT20_BPSK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31175;"	d
+RG_BB_SCALE_HT20_QPSK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31169;"	d
+RG_BB_SCALE_HT20_QPSK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31167;"	d
+RG_BB_SCALE_HT20_QPSK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31166;"	d
+RG_BB_SCALE_HT20_QPSK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31168;"	d
+RG_BB_SCALE_HT20_QPSK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31170;"	d
+RG_BB_SCALE_HT40_16QAM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31184;"	d
+RG_BB_SCALE_HT40_16QAM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31182;"	d
+RG_BB_SCALE_HT40_16QAM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31181;"	d
+RG_BB_SCALE_HT40_16QAM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31183;"	d
+RG_BB_SCALE_HT40_16QAM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31185;"	d
+RG_BB_SCALE_HT40_64QAM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31179;"	d
+RG_BB_SCALE_HT40_64QAM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31177;"	d
+RG_BB_SCALE_HT40_64QAM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31176;"	d
+RG_BB_SCALE_HT40_64QAM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31178;"	d
+RG_BB_SCALE_HT40_64QAM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31180;"	d
+RG_BB_SCALE_HT40_BPSK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31194;"	d
+RG_BB_SCALE_HT40_BPSK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31192;"	d
+RG_BB_SCALE_HT40_BPSK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31191;"	d
+RG_BB_SCALE_HT40_BPSK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31193;"	d
+RG_BB_SCALE_HT40_BPSK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31195;"	d
+RG_BB_SCALE_HT40_QPSK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31189;"	d
+RG_BB_SCALE_HT40_QPSK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31187;"	d
+RG_BB_SCALE_HT40_QPSK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31186;"	d
+RG_BB_SCALE_HT40_QPSK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31188;"	d
+RG_BB_SCALE_HT40_QPSK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31190;"	d
+RG_BB_SCALE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30402;"	d
+RG_BB_SCALE_LEGACY_16QAM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31144;"	d
+RG_BB_SCALE_LEGACY_16QAM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31142;"	d
+RG_BB_SCALE_LEGACY_16QAM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31141;"	d
+RG_BB_SCALE_LEGACY_16QAM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31143;"	d
+RG_BB_SCALE_LEGACY_16QAM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31145;"	d
+RG_BB_SCALE_LEGACY_64QAM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31139;"	d
+RG_BB_SCALE_LEGACY_64QAM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31137;"	d
+RG_BB_SCALE_LEGACY_64QAM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31136;"	d
+RG_BB_SCALE_LEGACY_64QAM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31138;"	d
+RG_BB_SCALE_LEGACY_64QAM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31140;"	d
+RG_BB_SCALE_LEGACY_BPSK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31154;"	d
+RG_BB_SCALE_LEGACY_BPSK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31152;"	d
+RG_BB_SCALE_LEGACY_BPSK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31151;"	d
+RG_BB_SCALE_LEGACY_BPSK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31153;"	d
+RG_BB_SCALE_LEGACY_BPSK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31155;"	d
+RG_BB_SCALE_LEGACY_QPSK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31149;"	d
+RG_BB_SCALE_LEGACY_QPSK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31147;"	d
+RG_BB_SCALE_LEGACY_QPSK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31146;"	d
+RG_BB_SCALE_LEGACY_QPSK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31148;"	d
+RG_BB_SCALE_LEGACY_QPSK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31150;"	d
+RG_BB_SCALE_MAN_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31134;"	d
+RG_BB_SCALE_MAN_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31132;"	d
+RG_BB_SCALE_MAN_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31131;"	d
+RG_BB_SCALE_MAN_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31133;"	d
+RG_BB_SCALE_MAN_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31135;"	d
+RG_BB_SCALE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30401;"	d
+RG_BB_SCALE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30403;"	d
+RG_BB_SCALE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30405;"	d
+RG_BB_SIG_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27274;"	d
+RG_BB_SIG_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27272;"	d
+RG_BB_SIG_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27271;"	d
+RG_BB_SIG_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27273;"	d
+RG_BB_SIG_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27275;"	d
+RG_BIST_EN_CCFO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32274;"	d
+RG_BIST_EN_CCFO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32272;"	d
+RG_BIST_EN_CCFO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32271;"	d
+RG_BIST_EN_CCFO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32273;"	d
+RG_BIST_EN_CCFO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32275;"	d
+RG_BIST_EN_RX_FFT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31394;"	d
+RG_BIST_EN_RX_FFT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31392;"	d
+RG_BIST_EN_RX_FFT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31391;"	d
+RG_BIST_EN_RX_FFT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31393;"	d
+RG_BIST_EN_RX_FFT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31395;"	d
+RG_BIST_EN_TX_FFT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31884;"	d
+RG_BIST_EN_TX_FFT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31882;"	d
+RG_BIST_EN_TX_FFT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31881;"	d
+RG_BIST_EN_TX_FFT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31883;"	d
+RG_BIST_EN_TX_FFT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31885;"	d
+RG_BIST_EN_VTB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32304;"	d
+RG_BIST_EN_VTB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32302;"	d
+RG_BIST_EN_VTB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32301;"	d
+RG_BIST_EN_VTB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32303;"	d
+RG_BIST_EN_VTB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32305;"	d
+RG_BIST_MODE_CCFO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32279;"	d
+RG_BIST_MODE_CCFO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32277;"	d
+RG_BIST_MODE_CCFO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32276;"	d
+RG_BIST_MODE_CCFO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32278;"	d
+RG_BIST_MODE_CCFO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32280;"	d
+RG_BIST_MODE_RX_FFT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31399;"	d
+RG_BIST_MODE_RX_FFT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31397;"	d
+RG_BIST_MODE_RX_FFT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31396;"	d
+RG_BIST_MODE_RX_FFT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31398;"	d
+RG_BIST_MODE_RX_FFT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31400;"	d
+RG_BIST_MODE_TX_FFT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31889;"	d
+RG_BIST_MODE_TX_FFT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31887;"	d
+RG_BIST_MODE_TX_FFT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31886;"	d
+RG_BIST_MODE_TX_FFT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31888;"	d
+RG_BIST_MODE_TX_FFT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31890;"	d
+RG_BIST_MODE_VTB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32309;"	d
+RG_BIST_MODE_VTB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32307;"	d
+RG_BIST_MODE_VTB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32306;"	d
+RG_BIST_MODE_VTB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32308;"	d
+RG_BIST_MODE_VTB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32310;"	d
+RG_BIT_REVERSE_HI	include/ssv6200_aux.h	14659;"	d
+RG_BIT_REVERSE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31859;"	d
+RG_BIT_REVERSE_I_MSK	include/ssv6200_aux.h	14657;"	d
+RG_BIT_REVERSE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31857;"	d
+RG_BIT_REVERSE_MSK	include/ssv6200_aux.h	14656;"	d
+RG_BIT_REVERSE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31856;"	d
+RG_BIT_REVERSE_SFT	include/ssv6200_aux.h	14658;"	d
+RG_BIT_REVERSE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31858;"	d
+RG_BIT_REVERSE_SZ	include/ssv6200_aux.h	14660;"	d
+RG_BIT_REVERSE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31860;"	d
+RG_BP_SMB_HI	include/ssv6200_aux.h	14284;"	d
+RG_BP_SMB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31489;"	d
+RG_BP_SMB_I_MSK	include/ssv6200_aux.h	14282;"	d
+RG_BP_SMB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31487;"	d
+RG_BP_SMB_MSK	include/ssv6200_aux.h	14281;"	d
+RG_BP_SMB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31486;"	d
+RG_BP_SMB_SFT	include/ssv6200_aux.h	14283;"	d
+RG_BP_SMB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31488;"	d
+RG_BP_SMB_SZ	include/ssv6200_aux.h	14285;"	d
+RG_BP_SMB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31490;"	d
+RG_BTRX_BTPASW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22364;"	d
+RG_BTRX_BTPASW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22362;"	d
+RG_BTRX_BTPASW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22361;"	d
+RG_BTRX_BTPASW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22363;"	d
+RG_BTRX_BTPASW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22365;"	d
+RG_BTTX_BTPASW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22369;"	d
+RG_BTTX_BTPASW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22367;"	d
+RG_BTTX_BTPASW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22366;"	d
+RG_BTTX_BTPASW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22368;"	d
+RG_BTTX_BTPASW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22370;"	d
+RG_BT_IDACAI_TZ0_PGAG0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24434;"	d
+RG_BT_IDACAI_TZ0_PGAG0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24432;"	d
+RG_BT_IDACAI_TZ0_PGAG0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24431;"	d
+RG_BT_IDACAI_TZ0_PGAG0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24433;"	d
+RG_BT_IDACAI_TZ0_PGAG0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24435;"	d
+RG_BT_IDACAI_TZ0_PGAG10_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24334;"	d
+RG_BT_IDACAI_TZ0_PGAG10_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24332;"	d
+RG_BT_IDACAI_TZ0_PGAG10_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24331;"	d
+RG_BT_IDACAI_TZ0_PGAG10_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24333;"	d
+RG_BT_IDACAI_TZ0_PGAG10_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24335;"	d
+RG_BT_IDACAI_TZ0_PGAG11_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24324;"	d
+RG_BT_IDACAI_TZ0_PGAG11_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24322;"	d
+RG_BT_IDACAI_TZ0_PGAG11_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24321;"	d
+RG_BT_IDACAI_TZ0_PGAG11_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24323;"	d
+RG_BT_IDACAI_TZ0_PGAG11_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24325;"	d
+RG_BT_IDACAI_TZ0_PGAG12_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24314;"	d
+RG_BT_IDACAI_TZ0_PGAG12_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24312;"	d
+RG_BT_IDACAI_TZ0_PGAG12_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24311;"	d
+RG_BT_IDACAI_TZ0_PGAG12_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24313;"	d
+RG_BT_IDACAI_TZ0_PGAG12_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24315;"	d
+RG_BT_IDACAI_TZ0_PGAG13_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24304;"	d
+RG_BT_IDACAI_TZ0_PGAG13_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24302;"	d
+RG_BT_IDACAI_TZ0_PGAG13_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24301;"	d
+RG_BT_IDACAI_TZ0_PGAG13_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24303;"	d
+RG_BT_IDACAI_TZ0_PGAG13_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24305;"	d
+RG_BT_IDACAI_TZ0_PGAG14_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24294;"	d
+RG_BT_IDACAI_TZ0_PGAG14_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24292;"	d
+RG_BT_IDACAI_TZ0_PGAG14_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24291;"	d
+RG_BT_IDACAI_TZ0_PGAG14_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24293;"	d
+RG_BT_IDACAI_TZ0_PGAG14_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24295;"	d
+RG_BT_IDACAI_TZ0_PGAG15_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24284;"	d
+RG_BT_IDACAI_TZ0_PGAG15_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24282;"	d
+RG_BT_IDACAI_TZ0_PGAG15_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24281;"	d
+RG_BT_IDACAI_TZ0_PGAG15_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24283;"	d
+RG_BT_IDACAI_TZ0_PGAG15_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24285;"	d
+RG_BT_IDACAI_TZ0_PGAG1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24424;"	d
+RG_BT_IDACAI_TZ0_PGAG1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24422;"	d
+RG_BT_IDACAI_TZ0_PGAG1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24421;"	d
+RG_BT_IDACAI_TZ0_PGAG1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24423;"	d
+RG_BT_IDACAI_TZ0_PGAG1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24425;"	d
+RG_BT_IDACAI_TZ0_PGAG2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24414;"	d
+RG_BT_IDACAI_TZ0_PGAG2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24412;"	d
+RG_BT_IDACAI_TZ0_PGAG2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24411;"	d
+RG_BT_IDACAI_TZ0_PGAG2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24413;"	d
+RG_BT_IDACAI_TZ0_PGAG2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24415;"	d
+RG_BT_IDACAI_TZ0_PGAG3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24404;"	d
+RG_BT_IDACAI_TZ0_PGAG3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24402;"	d
+RG_BT_IDACAI_TZ0_PGAG3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24401;"	d
+RG_BT_IDACAI_TZ0_PGAG3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24403;"	d
+RG_BT_IDACAI_TZ0_PGAG3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24405;"	d
+RG_BT_IDACAI_TZ0_PGAG4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24394;"	d
+RG_BT_IDACAI_TZ0_PGAG4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24392;"	d
+RG_BT_IDACAI_TZ0_PGAG4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24391;"	d
+RG_BT_IDACAI_TZ0_PGAG4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24393;"	d
+RG_BT_IDACAI_TZ0_PGAG4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24395;"	d
+RG_BT_IDACAI_TZ0_PGAG5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24384;"	d
+RG_BT_IDACAI_TZ0_PGAG5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24382;"	d
+RG_BT_IDACAI_TZ0_PGAG5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24381;"	d
+RG_BT_IDACAI_TZ0_PGAG5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24383;"	d
+RG_BT_IDACAI_TZ0_PGAG5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24385;"	d
+RG_BT_IDACAI_TZ0_PGAG6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24374;"	d
+RG_BT_IDACAI_TZ0_PGAG6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24372;"	d
+RG_BT_IDACAI_TZ0_PGAG6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24371;"	d
+RG_BT_IDACAI_TZ0_PGAG6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24373;"	d
+RG_BT_IDACAI_TZ0_PGAG6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24375;"	d
+RG_BT_IDACAI_TZ0_PGAG7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24364;"	d
+RG_BT_IDACAI_TZ0_PGAG7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24362;"	d
+RG_BT_IDACAI_TZ0_PGAG7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24361;"	d
+RG_BT_IDACAI_TZ0_PGAG7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24363;"	d
+RG_BT_IDACAI_TZ0_PGAG7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24365;"	d
+RG_BT_IDACAI_TZ0_PGAG8_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24354;"	d
+RG_BT_IDACAI_TZ0_PGAG8_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24352;"	d
+RG_BT_IDACAI_TZ0_PGAG8_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24351;"	d
+RG_BT_IDACAI_TZ0_PGAG8_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24353;"	d
+RG_BT_IDACAI_TZ0_PGAG8_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24355;"	d
+RG_BT_IDACAI_TZ0_PGAG9_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24344;"	d
+RG_BT_IDACAI_TZ0_PGAG9_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24342;"	d
+RG_BT_IDACAI_TZ0_PGAG9_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24341;"	d
+RG_BT_IDACAI_TZ0_PGAG9_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24343;"	d
+RG_BT_IDACAI_TZ0_PGAG9_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24345;"	d
+RG_BT_IDACAI_TZ1_PGAG0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24594;"	d
+RG_BT_IDACAI_TZ1_PGAG0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24592;"	d
+RG_BT_IDACAI_TZ1_PGAG0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24591;"	d
+RG_BT_IDACAI_TZ1_PGAG0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24593;"	d
+RG_BT_IDACAI_TZ1_PGAG0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24595;"	d
+RG_BT_IDACAI_TZ1_PGAG10_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24494;"	d
+RG_BT_IDACAI_TZ1_PGAG10_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24492;"	d
+RG_BT_IDACAI_TZ1_PGAG10_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24491;"	d
+RG_BT_IDACAI_TZ1_PGAG10_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24493;"	d
+RG_BT_IDACAI_TZ1_PGAG10_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24495;"	d
+RG_BT_IDACAI_TZ1_PGAG11_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24484;"	d
+RG_BT_IDACAI_TZ1_PGAG11_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24482;"	d
+RG_BT_IDACAI_TZ1_PGAG11_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24481;"	d
+RG_BT_IDACAI_TZ1_PGAG11_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24483;"	d
+RG_BT_IDACAI_TZ1_PGAG11_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24485;"	d
+RG_BT_IDACAI_TZ1_PGAG12_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24474;"	d
+RG_BT_IDACAI_TZ1_PGAG12_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24472;"	d
+RG_BT_IDACAI_TZ1_PGAG12_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24471;"	d
+RG_BT_IDACAI_TZ1_PGAG12_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24473;"	d
+RG_BT_IDACAI_TZ1_PGAG12_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24475;"	d
+RG_BT_IDACAI_TZ1_PGAG13_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24464;"	d
+RG_BT_IDACAI_TZ1_PGAG13_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24462;"	d
+RG_BT_IDACAI_TZ1_PGAG13_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24461;"	d
+RG_BT_IDACAI_TZ1_PGAG13_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24463;"	d
+RG_BT_IDACAI_TZ1_PGAG13_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24465;"	d
+RG_BT_IDACAI_TZ1_PGAG14_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24454;"	d
+RG_BT_IDACAI_TZ1_PGAG14_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24452;"	d
+RG_BT_IDACAI_TZ1_PGAG14_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24451;"	d
+RG_BT_IDACAI_TZ1_PGAG14_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24453;"	d
+RG_BT_IDACAI_TZ1_PGAG14_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24455;"	d
+RG_BT_IDACAI_TZ1_PGAG15_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24444;"	d
+RG_BT_IDACAI_TZ1_PGAG15_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24442;"	d
+RG_BT_IDACAI_TZ1_PGAG15_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24441;"	d
+RG_BT_IDACAI_TZ1_PGAG15_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24443;"	d
+RG_BT_IDACAI_TZ1_PGAG15_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24445;"	d
+RG_BT_IDACAI_TZ1_PGAG1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24584;"	d
+RG_BT_IDACAI_TZ1_PGAG1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24582;"	d
+RG_BT_IDACAI_TZ1_PGAG1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24581;"	d
+RG_BT_IDACAI_TZ1_PGAG1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24583;"	d
+RG_BT_IDACAI_TZ1_PGAG1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24585;"	d
+RG_BT_IDACAI_TZ1_PGAG2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24574;"	d
+RG_BT_IDACAI_TZ1_PGAG2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24572;"	d
+RG_BT_IDACAI_TZ1_PGAG2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24571;"	d
+RG_BT_IDACAI_TZ1_PGAG2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24573;"	d
+RG_BT_IDACAI_TZ1_PGAG2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24575;"	d
+RG_BT_IDACAI_TZ1_PGAG3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24564;"	d
+RG_BT_IDACAI_TZ1_PGAG3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24562;"	d
+RG_BT_IDACAI_TZ1_PGAG3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24561;"	d
+RG_BT_IDACAI_TZ1_PGAG3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24563;"	d
+RG_BT_IDACAI_TZ1_PGAG3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24565;"	d
+RG_BT_IDACAI_TZ1_PGAG4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24554;"	d
+RG_BT_IDACAI_TZ1_PGAG4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24552;"	d
+RG_BT_IDACAI_TZ1_PGAG4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24551;"	d
+RG_BT_IDACAI_TZ1_PGAG4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24553;"	d
+RG_BT_IDACAI_TZ1_PGAG4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24555;"	d
+RG_BT_IDACAI_TZ1_PGAG5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24544;"	d
+RG_BT_IDACAI_TZ1_PGAG5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24542;"	d
+RG_BT_IDACAI_TZ1_PGAG5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24541;"	d
+RG_BT_IDACAI_TZ1_PGAG5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24543;"	d
+RG_BT_IDACAI_TZ1_PGAG5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24545;"	d
+RG_BT_IDACAI_TZ1_PGAG6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24534;"	d
+RG_BT_IDACAI_TZ1_PGAG6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24532;"	d
+RG_BT_IDACAI_TZ1_PGAG6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24531;"	d
+RG_BT_IDACAI_TZ1_PGAG6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24533;"	d
+RG_BT_IDACAI_TZ1_PGAG6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24535;"	d
+RG_BT_IDACAI_TZ1_PGAG7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24524;"	d
+RG_BT_IDACAI_TZ1_PGAG7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24522;"	d
+RG_BT_IDACAI_TZ1_PGAG7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24521;"	d
+RG_BT_IDACAI_TZ1_PGAG7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24523;"	d
+RG_BT_IDACAI_TZ1_PGAG7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24525;"	d
+RG_BT_IDACAI_TZ1_PGAG8_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24514;"	d
+RG_BT_IDACAI_TZ1_PGAG8_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24512;"	d
+RG_BT_IDACAI_TZ1_PGAG8_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24511;"	d
+RG_BT_IDACAI_TZ1_PGAG8_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24513;"	d
+RG_BT_IDACAI_TZ1_PGAG8_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24515;"	d
+RG_BT_IDACAI_TZ1_PGAG9_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24504;"	d
+RG_BT_IDACAI_TZ1_PGAG9_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24502;"	d
+RG_BT_IDACAI_TZ1_PGAG9_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24501;"	d
+RG_BT_IDACAI_TZ1_PGAG9_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24503;"	d
+RG_BT_IDACAI_TZ1_PGAG9_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24505;"	d
+RG_BT_IDACAQ_TZ0_PGAG0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24439;"	d
+RG_BT_IDACAQ_TZ0_PGAG0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24437;"	d
+RG_BT_IDACAQ_TZ0_PGAG0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24436;"	d
+RG_BT_IDACAQ_TZ0_PGAG0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24438;"	d
+RG_BT_IDACAQ_TZ0_PGAG0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24440;"	d
+RG_BT_IDACAQ_TZ0_PGAG10_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24339;"	d
+RG_BT_IDACAQ_TZ0_PGAG10_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24337;"	d
+RG_BT_IDACAQ_TZ0_PGAG10_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24336;"	d
+RG_BT_IDACAQ_TZ0_PGAG10_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24338;"	d
+RG_BT_IDACAQ_TZ0_PGAG10_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24340;"	d
+RG_BT_IDACAQ_TZ0_PGAG11_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24329;"	d
+RG_BT_IDACAQ_TZ0_PGAG11_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24327;"	d
+RG_BT_IDACAQ_TZ0_PGAG11_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24326;"	d
+RG_BT_IDACAQ_TZ0_PGAG11_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24328;"	d
+RG_BT_IDACAQ_TZ0_PGAG11_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24330;"	d
+RG_BT_IDACAQ_TZ0_PGAG12_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24319;"	d
+RG_BT_IDACAQ_TZ0_PGAG12_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24317;"	d
+RG_BT_IDACAQ_TZ0_PGAG12_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24316;"	d
+RG_BT_IDACAQ_TZ0_PGAG12_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24318;"	d
+RG_BT_IDACAQ_TZ0_PGAG12_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24320;"	d
+RG_BT_IDACAQ_TZ0_PGAG13_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24309;"	d
+RG_BT_IDACAQ_TZ0_PGAG13_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24307;"	d
+RG_BT_IDACAQ_TZ0_PGAG13_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24306;"	d
+RG_BT_IDACAQ_TZ0_PGAG13_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24308;"	d
+RG_BT_IDACAQ_TZ0_PGAG13_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24310;"	d
+RG_BT_IDACAQ_TZ0_PGAG14_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24299;"	d
+RG_BT_IDACAQ_TZ0_PGAG14_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24297;"	d
+RG_BT_IDACAQ_TZ0_PGAG14_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24296;"	d
+RG_BT_IDACAQ_TZ0_PGAG14_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24298;"	d
+RG_BT_IDACAQ_TZ0_PGAG14_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24300;"	d
+RG_BT_IDACAQ_TZ0_PGAG15_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24289;"	d
+RG_BT_IDACAQ_TZ0_PGAG15_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24287;"	d
+RG_BT_IDACAQ_TZ0_PGAG15_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24286;"	d
+RG_BT_IDACAQ_TZ0_PGAG15_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24288;"	d
+RG_BT_IDACAQ_TZ0_PGAG15_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24290;"	d
+RG_BT_IDACAQ_TZ0_PGAG1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24429;"	d
+RG_BT_IDACAQ_TZ0_PGAG1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24427;"	d
+RG_BT_IDACAQ_TZ0_PGAG1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24426;"	d
+RG_BT_IDACAQ_TZ0_PGAG1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24428;"	d
+RG_BT_IDACAQ_TZ0_PGAG1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24430;"	d
+RG_BT_IDACAQ_TZ0_PGAG2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24419;"	d
+RG_BT_IDACAQ_TZ0_PGAG2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24417;"	d
+RG_BT_IDACAQ_TZ0_PGAG2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24416;"	d
+RG_BT_IDACAQ_TZ0_PGAG2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24418;"	d
+RG_BT_IDACAQ_TZ0_PGAG2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24420;"	d
+RG_BT_IDACAQ_TZ0_PGAG3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24409;"	d
+RG_BT_IDACAQ_TZ0_PGAG3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24407;"	d
+RG_BT_IDACAQ_TZ0_PGAG3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24406;"	d
+RG_BT_IDACAQ_TZ0_PGAG3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24408;"	d
+RG_BT_IDACAQ_TZ0_PGAG3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24410;"	d
+RG_BT_IDACAQ_TZ0_PGAG4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24399;"	d
+RG_BT_IDACAQ_TZ0_PGAG4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24397;"	d
+RG_BT_IDACAQ_TZ0_PGAG4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24396;"	d
+RG_BT_IDACAQ_TZ0_PGAG4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24398;"	d
+RG_BT_IDACAQ_TZ0_PGAG4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24400;"	d
+RG_BT_IDACAQ_TZ0_PGAG5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24389;"	d
+RG_BT_IDACAQ_TZ0_PGAG5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24387;"	d
+RG_BT_IDACAQ_TZ0_PGAG5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24386;"	d
+RG_BT_IDACAQ_TZ0_PGAG5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24388;"	d
+RG_BT_IDACAQ_TZ0_PGAG5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24390;"	d
+RG_BT_IDACAQ_TZ0_PGAG6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24379;"	d
+RG_BT_IDACAQ_TZ0_PGAG6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24377;"	d
+RG_BT_IDACAQ_TZ0_PGAG6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24376;"	d
+RG_BT_IDACAQ_TZ0_PGAG6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24378;"	d
+RG_BT_IDACAQ_TZ0_PGAG6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24380;"	d
+RG_BT_IDACAQ_TZ0_PGAG7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24369;"	d
+RG_BT_IDACAQ_TZ0_PGAG7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24367;"	d
+RG_BT_IDACAQ_TZ0_PGAG7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24366;"	d
+RG_BT_IDACAQ_TZ0_PGAG7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24368;"	d
+RG_BT_IDACAQ_TZ0_PGAG7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24370;"	d
+RG_BT_IDACAQ_TZ0_PGAG8_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24359;"	d
+RG_BT_IDACAQ_TZ0_PGAG8_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24357;"	d
+RG_BT_IDACAQ_TZ0_PGAG8_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24356;"	d
+RG_BT_IDACAQ_TZ0_PGAG8_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24358;"	d
+RG_BT_IDACAQ_TZ0_PGAG8_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24360;"	d
+RG_BT_IDACAQ_TZ0_PGAG9_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24349;"	d
+RG_BT_IDACAQ_TZ0_PGAG9_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24347;"	d
+RG_BT_IDACAQ_TZ0_PGAG9_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24346;"	d
+RG_BT_IDACAQ_TZ0_PGAG9_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24348;"	d
+RG_BT_IDACAQ_TZ0_PGAG9_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24350;"	d
+RG_BT_IDACAQ_TZ1_PGAG0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24599;"	d
+RG_BT_IDACAQ_TZ1_PGAG0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24597;"	d
+RG_BT_IDACAQ_TZ1_PGAG0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24596;"	d
+RG_BT_IDACAQ_TZ1_PGAG0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24598;"	d
+RG_BT_IDACAQ_TZ1_PGAG0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24600;"	d
+RG_BT_IDACAQ_TZ1_PGAG10_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24499;"	d
+RG_BT_IDACAQ_TZ1_PGAG10_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24497;"	d
+RG_BT_IDACAQ_TZ1_PGAG10_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24496;"	d
+RG_BT_IDACAQ_TZ1_PGAG10_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24498;"	d
+RG_BT_IDACAQ_TZ1_PGAG10_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24500;"	d
+RG_BT_IDACAQ_TZ1_PGAG11_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24489;"	d
+RG_BT_IDACAQ_TZ1_PGAG11_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24487;"	d
+RG_BT_IDACAQ_TZ1_PGAG11_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24486;"	d
+RG_BT_IDACAQ_TZ1_PGAG11_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24488;"	d
+RG_BT_IDACAQ_TZ1_PGAG11_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24490;"	d
+RG_BT_IDACAQ_TZ1_PGAG12_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24479;"	d
+RG_BT_IDACAQ_TZ1_PGAG12_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24477;"	d
+RG_BT_IDACAQ_TZ1_PGAG12_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24476;"	d
+RG_BT_IDACAQ_TZ1_PGAG12_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24478;"	d
+RG_BT_IDACAQ_TZ1_PGAG12_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24480;"	d
+RG_BT_IDACAQ_TZ1_PGAG13_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24469;"	d
+RG_BT_IDACAQ_TZ1_PGAG13_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24467;"	d
+RG_BT_IDACAQ_TZ1_PGAG13_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24466;"	d
+RG_BT_IDACAQ_TZ1_PGAG13_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24468;"	d
+RG_BT_IDACAQ_TZ1_PGAG13_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24470;"	d
+RG_BT_IDACAQ_TZ1_PGAG14_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24459;"	d
+RG_BT_IDACAQ_TZ1_PGAG14_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24457;"	d
+RG_BT_IDACAQ_TZ1_PGAG14_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24456;"	d
+RG_BT_IDACAQ_TZ1_PGAG14_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24458;"	d
+RG_BT_IDACAQ_TZ1_PGAG14_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24460;"	d
+RG_BT_IDACAQ_TZ1_PGAG15_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24449;"	d
+RG_BT_IDACAQ_TZ1_PGAG15_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24447;"	d
+RG_BT_IDACAQ_TZ1_PGAG15_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24446;"	d
+RG_BT_IDACAQ_TZ1_PGAG15_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24448;"	d
+RG_BT_IDACAQ_TZ1_PGAG15_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24450;"	d
+RG_BT_IDACAQ_TZ1_PGAG1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24589;"	d
+RG_BT_IDACAQ_TZ1_PGAG1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24587;"	d
+RG_BT_IDACAQ_TZ1_PGAG1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24586;"	d
+RG_BT_IDACAQ_TZ1_PGAG1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24588;"	d
+RG_BT_IDACAQ_TZ1_PGAG1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24590;"	d
+RG_BT_IDACAQ_TZ1_PGAG2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24579;"	d
+RG_BT_IDACAQ_TZ1_PGAG2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24577;"	d
+RG_BT_IDACAQ_TZ1_PGAG2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24576;"	d
+RG_BT_IDACAQ_TZ1_PGAG2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24578;"	d
+RG_BT_IDACAQ_TZ1_PGAG2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24580;"	d
+RG_BT_IDACAQ_TZ1_PGAG3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24569;"	d
+RG_BT_IDACAQ_TZ1_PGAG3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24567;"	d
+RG_BT_IDACAQ_TZ1_PGAG3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24566;"	d
+RG_BT_IDACAQ_TZ1_PGAG3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24568;"	d
+RG_BT_IDACAQ_TZ1_PGAG3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24570;"	d
+RG_BT_IDACAQ_TZ1_PGAG4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24559;"	d
+RG_BT_IDACAQ_TZ1_PGAG4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24557;"	d
+RG_BT_IDACAQ_TZ1_PGAG4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24556;"	d
+RG_BT_IDACAQ_TZ1_PGAG4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24558;"	d
+RG_BT_IDACAQ_TZ1_PGAG4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24560;"	d
+RG_BT_IDACAQ_TZ1_PGAG5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24549;"	d
+RG_BT_IDACAQ_TZ1_PGAG5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24547;"	d
+RG_BT_IDACAQ_TZ1_PGAG5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24546;"	d
+RG_BT_IDACAQ_TZ1_PGAG5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24548;"	d
+RG_BT_IDACAQ_TZ1_PGAG5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24550;"	d
+RG_BT_IDACAQ_TZ1_PGAG6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24539;"	d
+RG_BT_IDACAQ_TZ1_PGAG6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24537;"	d
+RG_BT_IDACAQ_TZ1_PGAG6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24536;"	d
+RG_BT_IDACAQ_TZ1_PGAG6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24538;"	d
+RG_BT_IDACAQ_TZ1_PGAG6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24540;"	d
+RG_BT_IDACAQ_TZ1_PGAG7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24529;"	d
+RG_BT_IDACAQ_TZ1_PGAG7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24527;"	d
+RG_BT_IDACAQ_TZ1_PGAG7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24526;"	d
+RG_BT_IDACAQ_TZ1_PGAG7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24528;"	d
+RG_BT_IDACAQ_TZ1_PGAG7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24530;"	d
+RG_BT_IDACAQ_TZ1_PGAG8_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24519;"	d
+RG_BT_IDACAQ_TZ1_PGAG8_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24517;"	d
+RG_BT_IDACAQ_TZ1_PGAG8_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24516;"	d
+RG_BT_IDACAQ_TZ1_PGAG8_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24518;"	d
+RG_BT_IDACAQ_TZ1_PGAG8_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24520;"	d
+RG_BT_IDACAQ_TZ1_PGAG9_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24509;"	d
+RG_BT_IDACAQ_TZ1_PGAG9_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24507;"	d
+RG_BT_IDACAQ_TZ1_PGAG9_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24506;"	d
+RG_BT_IDACAQ_TZ1_PGAG9_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24508;"	d
+RG_BT_IDACAQ_TZ1_PGAG9_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24510;"	d
+RG_BT_PABIAS_2X_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22374;"	d
+RG_BT_PABIAS_2X_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22372;"	d
+RG_BT_PABIAS_2X_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22371;"	d
+RG_BT_PABIAS_2X_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22373;"	d
+RG_BT_PABIAS_2X_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22375;"	d
+RG_BT_PABIAS_CTRL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22379;"	d
+RG_BT_PABIAS_CTRL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22377;"	d
+RG_BT_PABIAS_CTRL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22376;"	d
+RG_BT_PABIAS_CTRL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22378;"	d
+RG_BT_PABIAS_CTRL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22380;"	d
+RG_BT_RX_ABBCFIX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22179;"	d
+RG_BT_RX_ABBCFIX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22177;"	d
+RG_BT_RX_ABBCFIX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22176;"	d
+RG_BT_RX_ABBCFIX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22178;"	d
+RG_BT_RX_ABBCFIX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22180;"	d
+RG_BT_RX_ABBCTUNE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22149;"	d
+RG_BT_RX_ABBCTUNE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22147;"	d
+RG_BT_RX_ABBCTUNE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22146;"	d
+RG_BT_RX_ABBCTUNE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22148;"	d
+RG_BT_RX_ABBCTUNE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22150;"	d
+RG_BT_RX_ABB_BT_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22189;"	d
+RG_BT_RX_ABB_BT_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22187;"	d
+RG_BT_RX_ABB_BT_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22186;"	d
+RG_BT_RX_ABB_BT_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22188;"	d
+RG_BT_RX_ABB_BT_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22190;"	d
+RG_BT_RX_ABB_IDIV3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22194;"	d
+RG_BT_RX_ABB_IDIV3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22192;"	d
+RG_BT_RX_ABB_IDIV3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22191;"	d
+RG_BT_RX_ABB_IDIV3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22193;"	d
+RG_BT_RX_ABB_IDIV3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22195;"	d
+RG_BT_RX_ABB_N_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22184;"	d
+RG_BT_RX_ABB_N_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22182;"	d
+RG_BT_RX_ABB_N_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22181;"	d
+RG_BT_RX_ABB_N_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22183;"	d
+RG_BT_RX_ABB_N_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22185;"	d
+RG_BT_RX_ADC_CLOAD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22934;"	d
+RG_BT_RX_ADC_CLOAD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22932;"	d
+RG_BT_RX_ADC_CLOAD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22931;"	d
+RG_BT_RX_ADC_CLOAD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22933;"	d
+RG_BT_RX_ADC_CLOAD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22935;"	d
+RG_BT_RX_ADC_ICMP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22924;"	d
+RG_BT_RX_ADC_ICMP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22922;"	d
+RG_BT_RX_ADC_ICMP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22921;"	d
+RG_BT_RX_ADC_ICMP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22923;"	d
+RG_BT_RX_ADC_ICMP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22925;"	d
+RG_BT_RX_ADC_PSW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22939;"	d
+RG_BT_RX_ADC_PSW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22937;"	d
+RG_BT_RX_ADC_PSW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22936;"	d
+RG_BT_RX_ADC_PSW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22938;"	d
+RG_BT_RX_ADC_PSW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22940;"	d
+RG_BT_RX_ADC_VCMI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22929;"	d
+RG_BT_RX_ADC_VCMI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22927;"	d
+RG_BT_RX_ADC_VCMI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22926;"	d
+RG_BT_RX_ADC_VCMI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22928;"	d
+RG_BT_RX_ADC_VCMI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22930;"	d
+RG_BT_RX_DCCAL_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24679;"	d
+RG_BT_RX_DCCAL_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24677;"	d
+RG_BT_RX_DCCAL_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24676;"	d
+RG_BT_RX_DCCAL_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24678;"	d
+RG_BT_RX_DCCAL_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24680;"	d
+RG_BT_RX_EN_IDACA_COARSE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22199;"	d
+RG_BT_RX_EN_IDACA_COARSE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22197;"	d
+RG_BT_RX_EN_IDACA_COARSE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22196;"	d
+RG_BT_RX_EN_IDACA_COARSE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22198;"	d
+RG_BT_RX_EN_IDACA_COARSE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22200;"	d
+RG_BT_RX_EN_LOOPA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22204;"	d
+RG_BT_RX_EN_LOOPA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22202;"	d
+RG_BT_RX_EN_LOOPA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22201;"	d
+RG_BT_RX_EN_LOOPA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22203;"	d
+RG_BT_RX_EN_LOOPA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22205;"	d
+RG_BT_RX_FILTERI1ST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22164;"	d
+RG_BT_RX_FILTERI1ST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22162;"	d
+RG_BT_RX_FILTERI1ST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22161;"	d
+RG_BT_RX_FILTERI1ST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22163;"	d
+RG_BT_RX_FILTERI1ST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22165;"	d
+RG_BT_RX_FILTERI2ND_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22169;"	d
+RG_BT_RX_FILTERI2ND_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22167;"	d
+RG_BT_RX_FILTERI2ND_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22166;"	d
+RG_BT_RX_FILTERI2ND_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22168;"	d
+RG_BT_RX_FILTERI2ND_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22170;"	d
+RG_BT_RX_FILTERI3RD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22174;"	d
+RG_BT_RX_FILTERI3RD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22172;"	d
+RG_BT_RX_FILTERI3RD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22171;"	d
+RG_BT_RX_FILTERI3RD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22173;"	d
+RG_BT_RX_FILTERI3RD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22175;"	d
+RG_BT_RX_FILTERI_COARSE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22159;"	d
+RG_BT_RX_FILTERI_COARSE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22157;"	d
+RG_BT_RX_FILTERI_COARSE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22156;"	d
+RG_BT_RX_FILTERI_COARSE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22158;"	d
+RG_BT_RX_FILTERI_COARSE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22160;"	d
+RG_BT_RX_FILTERVCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22214;"	d
+RG_BT_RX_FILTERVCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22212;"	d
+RG_BT_RX_FILTERVCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22211;"	d
+RG_BT_RX_FILTERVCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22213;"	d
+RG_BT_RX_FILTERVCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22215;"	d
+RG_BT_RX_HG_DIV2_CORE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22694;"	d
+RG_BT_RX_HG_DIV2_CORE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22692;"	d
+RG_BT_RX_HG_DIV2_CORE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22691;"	d
+RG_BT_RX_HG_DIV2_CORE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22693;"	d
+RG_BT_RX_HG_DIV2_CORE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22695;"	d
+RG_BT_RX_HG_LNAHGN_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22669;"	d
+RG_BT_RX_HG_LNAHGN_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22667;"	d
+RG_BT_RX_HG_LNAHGN_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22666;"	d
+RG_BT_RX_HG_LNAHGN_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22668;"	d
+RG_BT_RX_HG_LNAHGN_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22670;"	d
+RG_BT_RX_HG_LNAHGP_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22674;"	d
+RG_BT_RX_HG_LNAHGP_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22672;"	d
+RG_BT_RX_HG_LNAHGP_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22671;"	d
+RG_BT_RX_HG_LNAHGP_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22673;"	d
+RG_BT_RX_HG_LNAHGP_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22675;"	d
+RG_BT_RX_HG_LNALG_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22679;"	d
+RG_BT_RX_HG_LNALG_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22677;"	d
+RG_BT_RX_HG_LNALG_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22676;"	d
+RG_BT_RX_HG_LNALG_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22678;"	d
+RG_BT_RX_HG_LNALG_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22680;"	d
+RG_BT_RX_HG_LNA_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22659;"	d
+RG_BT_RX_HG_LNA_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22657;"	d
+RG_BT_RX_HG_LNA_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22656;"	d
+RG_BT_RX_HG_LNA_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22658;"	d
+RG_BT_RX_HG_LNA_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22660;"	d
+RG_BT_RX_HG_LOBUF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22699;"	d
+RG_BT_RX_HG_LOBUF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22697;"	d
+RG_BT_RX_HG_LOBUF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22696;"	d
+RG_BT_RX_HG_LOBUF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22698;"	d
+RG_BT_RX_HG_LOBUF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22700;"	d
+RG_BT_RX_HG_TZI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22704;"	d
+RG_BT_RX_HG_TZI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22702;"	d
+RG_BT_RX_HG_TZI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22701;"	d
+RG_BT_RX_HG_TZI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22703;"	d
+RG_BT_RX_HG_TZI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22705;"	d
+RG_BT_RX_HG_TZ_CAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22684;"	d
+RG_BT_RX_HG_TZ_CAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22682;"	d
+RG_BT_RX_HG_TZ_CAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22681;"	d
+RG_BT_RX_HG_TZ_CAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22683;"	d
+RG_BT_RX_HG_TZ_CAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22685;"	d
+RG_BT_RX_HG_TZ_GC_BOOST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22689;"	d
+RG_BT_RX_HG_TZ_GC_BOOST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22687;"	d
+RG_BT_RX_HG_TZ_GC_BOOST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22686;"	d
+RG_BT_RX_HG_TZ_GC_BOOST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22688;"	d
+RG_BT_RX_HG_TZ_GC_BOOST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22690;"	d
+RG_BT_RX_HG_TZ_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22664;"	d
+RG_BT_RX_HG_TZ_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22662;"	d
+RG_BT_RX_HG_TZ_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22661;"	d
+RG_BT_RX_HG_TZ_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22663;"	d
+RG_BT_RX_HG_TZ_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22665;"	d
+RG_BT_RX_HG_TZ_VCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22709;"	d
+RG_BT_RX_HG_TZ_VCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22707;"	d
+RG_BT_RX_HG_TZ_VCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22706;"	d
+RG_BT_RX_HG_TZ_VCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22708;"	d
+RG_BT_RX_HG_TZ_VCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22710;"	d
+RG_BT_RX_LG_DIV2_CORE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22804;"	d
+RG_BT_RX_LG_DIV2_CORE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22802;"	d
+RG_BT_RX_LG_DIV2_CORE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22801;"	d
+RG_BT_RX_LG_DIV2_CORE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22803;"	d
+RG_BT_RX_LG_DIV2_CORE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22805;"	d
+RG_BT_RX_LG_LNAHGN_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22779;"	d
+RG_BT_RX_LG_LNAHGN_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22777;"	d
+RG_BT_RX_LG_LNAHGN_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22776;"	d
+RG_BT_RX_LG_LNAHGN_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22778;"	d
+RG_BT_RX_LG_LNAHGN_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22780;"	d
+RG_BT_RX_LG_LNAHGP_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22784;"	d
+RG_BT_RX_LG_LNAHGP_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22782;"	d
+RG_BT_RX_LG_LNAHGP_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22781;"	d
+RG_BT_RX_LG_LNAHGP_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22783;"	d
+RG_BT_RX_LG_LNAHGP_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22785;"	d
+RG_BT_RX_LG_LNALG_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22789;"	d
+RG_BT_RX_LG_LNALG_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22787;"	d
+RG_BT_RX_LG_LNALG_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22786;"	d
+RG_BT_RX_LG_LNALG_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22788;"	d
+RG_BT_RX_LG_LNALG_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22790;"	d
+RG_BT_RX_LG_LNA_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22769;"	d
+RG_BT_RX_LG_LNA_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22767;"	d
+RG_BT_RX_LG_LNA_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22766;"	d
+RG_BT_RX_LG_LNA_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22768;"	d
+RG_BT_RX_LG_LNA_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22770;"	d
+RG_BT_RX_LG_LOBUF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22809;"	d
+RG_BT_RX_LG_LOBUF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22807;"	d
+RG_BT_RX_LG_LOBUF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22806;"	d
+RG_BT_RX_LG_LOBUF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22808;"	d
+RG_BT_RX_LG_LOBUF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22810;"	d
+RG_BT_RX_LG_TZI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22814;"	d
+RG_BT_RX_LG_TZI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22812;"	d
+RG_BT_RX_LG_TZI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22811;"	d
+RG_BT_RX_LG_TZI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22813;"	d
+RG_BT_RX_LG_TZI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22815;"	d
+RG_BT_RX_LG_TZ_CAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22794;"	d
+RG_BT_RX_LG_TZ_CAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22792;"	d
+RG_BT_RX_LG_TZ_CAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22791;"	d
+RG_BT_RX_LG_TZ_CAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22793;"	d
+RG_BT_RX_LG_TZ_CAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22795;"	d
+RG_BT_RX_LG_TZ_GC_BOOST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22799;"	d
+RG_BT_RX_LG_TZ_GC_BOOST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22797;"	d
+RG_BT_RX_LG_TZ_GC_BOOST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22796;"	d
+RG_BT_RX_LG_TZ_GC_BOOST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22798;"	d
+RG_BT_RX_LG_TZ_GC_BOOST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22800;"	d
+RG_BT_RX_LG_TZ_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22774;"	d
+RG_BT_RX_LG_TZ_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22772;"	d
+RG_BT_RX_LG_TZ_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22771;"	d
+RG_BT_RX_LG_TZ_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22773;"	d
+RG_BT_RX_LG_TZ_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22775;"	d
+RG_BT_RX_LG_TZ_VCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22819;"	d
+RG_BT_RX_LG_TZ_VCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22817;"	d
+RG_BT_RX_LG_TZ_VCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22816;"	d
+RG_BT_RX_LG_TZ_VCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22818;"	d
+RG_BT_RX_LG_TZ_VCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22820;"	d
+RG_BT_RX_MG_DIV2_CORE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22749;"	d
+RG_BT_RX_MG_DIV2_CORE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22747;"	d
+RG_BT_RX_MG_DIV2_CORE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22746;"	d
+RG_BT_RX_MG_DIV2_CORE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22748;"	d
+RG_BT_RX_MG_DIV2_CORE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22750;"	d
+RG_BT_RX_MG_LNAHGN_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22724;"	d
+RG_BT_RX_MG_LNAHGN_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22722;"	d
+RG_BT_RX_MG_LNAHGN_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22721;"	d
+RG_BT_RX_MG_LNAHGN_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22723;"	d
+RG_BT_RX_MG_LNAHGN_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22725;"	d
+RG_BT_RX_MG_LNAHGP_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22729;"	d
+RG_BT_RX_MG_LNAHGP_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22727;"	d
+RG_BT_RX_MG_LNAHGP_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22726;"	d
+RG_BT_RX_MG_LNAHGP_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22728;"	d
+RG_BT_RX_MG_LNAHGP_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22730;"	d
+RG_BT_RX_MG_LNALG_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22734;"	d
+RG_BT_RX_MG_LNALG_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22732;"	d
+RG_BT_RX_MG_LNALG_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22731;"	d
+RG_BT_RX_MG_LNALG_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22733;"	d
+RG_BT_RX_MG_LNALG_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22735;"	d
+RG_BT_RX_MG_LNA_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22714;"	d
+RG_BT_RX_MG_LNA_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22712;"	d
+RG_BT_RX_MG_LNA_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22711;"	d
+RG_BT_RX_MG_LNA_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22713;"	d
+RG_BT_RX_MG_LNA_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22715;"	d
+RG_BT_RX_MG_LOBUF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22754;"	d
+RG_BT_RX_MG_LOBUF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22752;"	d
+RG_BT_RX_MG_LOBUF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22751;"	d
+RG_BT_RX_MG_LOBUF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22753;"	d
+RG_BT_RX_MG_LOBUF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22755;"	d
+RG_BT_RX_MG_TZI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22759;"	d
+RG_BT_RX_MG_TZI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22757;"	d
+RG_BT_RX_MG_TZI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22756;"	d
+RG_BT_RX_MG_TZI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22758;"	d
+RG_BT_RX_MG_TZI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22760;"	d
+RG_BT_RX_MG_TZ_CAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22739;"	d
+RG_BT_RX_MG_TZ_CAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22737;"	d
+RG_BT_RX_MG_TZ_CAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22736;"	d
+RG_BT_RX_MG_TZ_CAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22738;"	d
+RG_BT_RX_MG_TZ_CAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22740;"	d
+RG_BT_RX_MG_TZ_GC_BOOST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22744;"	d
+RG_BT_RX_MG_TZ_GC_BOOST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22742;"	d
+RG_BT_RX_MG_TZ_GC_BOOST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22741;"	d
+RG_BT_RX_MG_TZ_GC_BOOST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22743;"	d
+RG_BT_RX_MG_TZ_GC_BOOST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22745;"	d
+RG_BT_RX_MG_TZ_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22719;"	d
+RG_BT_RX_MG_TZ_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22717;"	d
+RG_BT_RX_MG_TZ_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22716;"	d
+RG_BT_RX_MG_TZ_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22718;"	d
+RG_BT_RX_MG_TZ_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22720;"	d
+RG_BT_RX_MG_TZ_VCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22764;"	d
+RG_BT_RX_MG_TZ_VCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22762;"	d
+RG_BT_RX_MG_TZ_VCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22761;"	d
+RG_BT_RX_MG_TZ_VCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22763;"	d
+RG_BT_RX_MG_TZ_VCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22765;"	d
+RG_BT_RX_OUTVCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22219;"	d
+RG_BT_RX_OUTVCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22217;"	d
+RG_BT_RX_OUTVCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22216;"	d
+RG_BT_RX_OUTVCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22218;"	d
+RG_BT_RX_OUTVCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22220;"	d
+RG_BT_RX_TZ_CMZ_C_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22154;"	d
+RG_BT_RX_TZ_CMZ_C_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22152;"	d
+RG_BT_RX_TZ_CMZ_C_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22151;"	d
+RG_BT_RX_TZ_CMZ_C_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22153;"	d
+RG_BT_RX_TZ_CMZ_C_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22155;"	d
+RG_BT_RX_TZ_CMZ_R_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22209;"	d
+RG_BT_RX_TZ_CMZ_R_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22207;"	d
+RG_BT_RX_TZ_CMZ_R_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22206;"	d
+RG_BT_RX_TZ_CMZ_R_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22208;"	d
+RG_BT_RX_TZ_CMZ_R_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22210;"	d
+RG_BT_RX_ULG_DIV2_CORE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22859;"	d
+RG_BT_RX_ULG_DIV2_CORE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22857;"	d
+RG_BT_RX_ULG_DIV2_CORE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22856;"	d
+RG_BT_RX_ULG_DIV2_CORE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22858;"	d
+RG_BT_RX_ULG_DIV2_CORE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22860;"	d
+RG_BT_RX_ULG_LNAHGN_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22834;"	d
+RG_BT_RX_ULG_LNAHGN_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22832;"	d
+RG_BT_RX_ULG_LNAHGN_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22831;"	d
+RG_BT_RX_ULG_LNAHGN_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22833;"	d
+RG_BT_RX_ULG_LNAHGN_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22835;"	d
+RG_BT_RX_ULG_LNAHGP_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22839;"	d
+RG_BT_RX_ULG_LNAHGP_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22837;"	d
+RG_BT_RX_ULG_LNAHGP_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22836;"	d
+RG_BT_RX_ULG_LNAHGP_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22838;"	d
+RG_BT_RX_ULG_LNAHGP_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22840;"	d
+RG_BT_RX_ULG_LNALG_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22844;"	d
+RG_BT_RX_ULG_LNALG_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22842;"	d
+RG_BT_RX_ULG_LNALG_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22841;"	d
+RG_BT_RX_ULG_LNALG_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22843;"	d
+RG_BT_RX_ULG_LNALG_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22845;"	d
+RG_BT_RX_ULG_LNA_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22824;"	d
+RG_BT_RX_ULG_LNA_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22822;"	d
+RG_BT_RX_ULG_LNA_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22821;"	d
+RG_BT_RX_ULG_LNA_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22823;"	d
+RG_BT_RX_ULG_LNA_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22825;"	d
+RG_BT_RX_ULG_LOBUF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22864;"	d
+RG_BT_RX_ULG_LOBUF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22862;"	d
+RG_BT_RX_ULG_LOBUF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22861;"	d
+RG_BT_RX_ULG_LOBUF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22863;"	d
+RG_BT_RX_ULG_LOBUF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22865;"	d
+RG_BT_RX_ULG_TZI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22869;"	d
+RG_BT_RX_ULG_TZI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22867;"	d
+RG_BT_RX_ULG_TZI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22866;"	d
+RG_BT_RX_ULG_TZI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22868;"	d
+RG_BT_RX_ULG_TZI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22870;"	d
+RG_BT_RX_ULG_TZ_CAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22849;"	d
+RG_BT_RX_ULG_TZ_CAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22847;"	d
+RG_BT_RX_ULG_TZ_CAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22846;"	d
+RG_BT_RX_ULG_TZ_CAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22848;"	d
+RG_BT_RX_ULG_TZ_CAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22850;"	d
+RG_BT_RX_ULG_TZ_GC_BOOST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22854;"	d
+RG_BT_RX_ULG_TZ_GC_BOOST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22852;"	d
+RG_BT_RX_ULG_TZ_GC_BOOST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22851;"	d
+RG_BT_RX_ULG_TZ_GC_BOOST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22853;"	d
+RG_BT_RX_ULG_TZ_GC_BOOST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22855;"	d
+RG_BT_RX_ULG_TZ_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22829;"	d
+RG_BT_RX_ULG_TZ_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22827;"	d
+RG_BT_RX_ULG_TZ_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22826;"	d
+RG_BT_RX_ULG_TZ_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22828;"	d
+RG_BT_RX_ULG_TZ_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22830;"	d
+RG_BT_RX_ULG_TZ_VCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22874;"	d
+RG_BT_RX_ULG_TZ_VCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22872;"	d
+RG_BT_RX_ULG_TZ_VCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22871;"	d
+RG_BT_RX_ULG_TZ_VCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22873;"	d
+RG_BT_RX_ULG_TZ_VCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22875;"	d
+RG_BT_TRX_IF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27174;"	d
+RG_BT_TRX_IF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27172;"	d
+RG_BT_TRX_IF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27171;"	d
+RG_BT_TRX_IF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27173;"	d
+RG_BT_TRX_IF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27175;"	d
+RG_BT_TXLPF_BOOSTI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23069;"	d
+RG_BT_TXLPF_BOOSTI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23067;"	d
+RG_BT_TXLPF_BOOSTI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23066;"	d
+RG_BT_TXLPF_BOOSTI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23068;"	d
+RG_BT_TXLPF_BOOSTI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23070;"	d
+RG_BT_TXMOD_GMCELL_FINE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22329;"	d
+RG_BT_TXMOD_GMCELL_FINE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22327;"	d
+RG_BT_TXMOD_GMCELL_FINE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22326;"	d
+RG_BT_TXMOD_GMCELL_FINE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22328;"	d
+RG_BT_TXMOD_GMCELL_FINE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22330;"	d
+RG_BT_TXPGA_CAPSW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22314;"	d
+RG_BT_TXPGA_CAPSW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22312;"	d
+RG_BT_TXPGA_CAPSW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22311;"	d
+RG_BT_TXPGA_CAPSW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22313;"	d
+RG_BT_TXPGA_CAPSW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22315;"	d
+RG_BT_TX_DACI1ST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23039;"	d
+RG_BT_TX_DACI1ST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23037;"	d
+RG_BT_TX_DACI1ST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23036;"	d
+RG_BT_TX_DACI1ST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23038;"	d
+RG_BT_TX_DACI1ST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23040;"	d
+RG_BT_TX_DACLPF_ICOARSE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23044;"	d
+RG_BT_TX_DACLPF_ICOARSE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23042;"	d
+RG_BT_TX_DACLPF_ICOARSE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23041;"	d
+RG_BT_TX_DACLPF_ICOARSE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23043;"	d
+RG_BT_TX_DACLPF_ICOARSE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23045;"	d
+RG_BT_TX_DACLPF_IFINE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23049;"	d
+RG_BT_TX_DACLPF_IFINE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23047;"	d
+RG_BT_TX_DACLPF_IFINE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23046;"	d
+RG_BT_TX_DACLPF_IFINE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23048;"	d
+RG_BT_TX_DACLPF_IFINE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23050;"	d
+RG_BT_TX_DACLPF_VCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23054;"	d
+RG_BT_TX_DACLPF_VCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23052;"	d
+RG_BT_TX_DACLPF_VCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23051;"	d
+RG_BT_TX_DACLPF_VCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23053;"	d
+RG_BT_TX_DACLPF_VCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23055;"	d
+RG_BT_TX_DAC_CKEDGE_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23079;"	d
+RG_BT_TX_DAC_CKEDGE_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23077;"	d
+RG_BT_TX_DAC_CKEDGE_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23076;"	d
+RG_BT_TX_DAC_CKEDGE_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23078;"	d
+RG_BT_TX_DAC_CKEDGE_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23080;"	d
+RG_BT_TX_DAC_IATTN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23064;"	d
+RG_BT_TX_DAC_IATTN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23062;"	d
+RG_BT_TX_DAC_IATTN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23061;"	d
+RG_BT_TX_DAC_IATTN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23063;"	d
+RG_BT_TX_DAC_IATTN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23065;"	d
+RG_BT_TX_DAC_IBIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23059;"	d
+RG_BT_TX_DAC_IBIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23057;"	d
+RG_BT_TX_DAC_IBIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23056;"	d
+RG_BT_TX_DAC_IBIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23058;"	d
+RG_BT_TX_DAC_IBIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23060;"	d
+RG_BT_TX_DAC_IOFFSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23089;"	d
+RG_BT_TX_DAC_IOFFSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23087;"	d
+RG_BT_TX_DAC_IOFFSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23086;"	d
+RG_BT_TX_DAC_IOFFSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23088;"	d
+RG_BT_TX_DAC_IOFFSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23090;"	d
+RG_BT_TX_DAC_OS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23084;"	d
+RG_BT_TX_DAC_OS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23082;"	d
+RG_BT_TX_DAC_OS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23081;"	d
+RG_BT_TX_DAC_OS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23083;"	d
+RG_BT_TX_DAC_OS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23085;"	d
+RG_BT_TX_DAC_QOFFSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23094;"	d
+RG_BT_TX_DAC_QOFFSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23092;"	d
+RG_BT_TX_DAC_QOFFSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23091;"	d
+RG_BT_TX_DAC_QOFFSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23093;"	d
+RG_BT_TX_DAC_QOFFSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23095;"	d
+RG_BT_TX_DAC_RCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23074;"	d
+RG_BT_TX_DAC_RCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23072;"	d
+RG_BT_TX_DAC_RCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23071;"	d
+RG_BT_TX_DAC_RCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23073;"	d
+RG_BT_TX_DAC_RCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23075;"	d
+RG_BT_TX_DIV_VSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22319;"	d
+RG_BT_TX_DIV_VSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22317;"	d
+RG_BT_TX_DIV_VSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22316;"	d
+RG_BT_TX_DIV_VSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22318;"	d
+RG_BT_TX_DIV_VSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22320;"	d
+RG_BT_TX_GAIN_OFFSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22414;"	d
+RG_BT_TX_GAIN_OFFSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22412;"	d
+RG_BT_TX_GAIN_OFFSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22411;"	d
+RG_BT_TX_GAIN_OFFSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22413;"	d
+RG_BT_TX_GAIN_OFFSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22415;"	d
+RG_BT_TX_LOBUF_VSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22324;"	d
+RG_BT_TX_LOBUF_VSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22322;"	d
+RG_BT_TX_LOBUF_VSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22321;"	d
+RG_BT_TX_LOBUF_VSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22323;"	d
+RG_BT_TX_LOBUF_VSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22325;"	d
+RG_BT_TX_PA_VCAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22384;"	d
+RG_BT_TX_PA_VCAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22382;"	d
+RG_BT_TX_PA_VCAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22381;"	d
+RG_BT_TX_PA_VCAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22383;"	d
+RG_BT_TX_PA_VCAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22385;"	d
+RG_BUCK_EN_PSM_HI	include/ssv6200_aux.h	5884;"	d
+RG_BUCK_EN_PSM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29634;"	d
+RG_BUCK_EN_PSM_I_MSK	include/ssv6200_aux.h	5882;"	d
+RG_BUCK_EN_PSM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29632;"	d
+RG_BUCK_EN_PSM_MSK	include/ssv6200_aux.h	5881;"	d
+RG_BUCK_EN_PSM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29631;"	d
+RG_BUCK_EN_PSM_SFT	include/ssv6200_aux.h	5883;"	d
+RG_BUCK_EN_PSM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29633;"	d
+RG_BUCK_EN_PSM_SZ	include/ssv6200_aux.h	5885;"	d
+RG_BUCK_EN_PSM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29635;"	d
+RG_BUCK_LEVEL_HI	include/ssv6200_aux.h	5854;"	d
+RG_BUCK_LEVEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29624;"	d
+RG_BUCK_LEVEL_I_MSK	include/ssv6200_aux.h	5852;"	d
+RG_BUCK_LEVEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29622;"	d
+RG_BUCK_LEVEL_MSK	include/ssv6200_aux.h	5851;"	d
+RG_BUCK_LEVEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29621;"	d
+RG_BUCK_LEVEL_SFT	include/ssv6200_aux.h	5853;"	d
+RG_BUCK_LEVEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29623;"	d
+RG_BUCK_LEVEL_SLP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30079;"	d
+RG_BUCK_LEVEL_SLP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30077;"	d
+RG_BUCK_LEVEL_SLP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30076;"	d
+RG_BUCK_LEVEL_SLP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30078;"	d
+RG_BUCK_LEVEL_SLP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30080;"	d
+RG_BUCK_LEVEL_SZ	include/ssv6200_aux.h	5855;"	d
+RG_BUCK_LEVEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29625;"	d
+RG_BUCK_PSM_VTH_HI	include/ssv6200_aux.h	5889;"	d
+RG_BUCK_PSM_VTH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29639;"	d
+RG_BUCK_PSM_VTH_I_MSK	include/ssv6200_aux.h	5887;"	d
+RG_BUCK_PSM_VTH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29637;"	d
+RG_BUCK_PSM_VTH_MSK	include/ssv6200_aux.h	5886;"	d
+RG_BUCK_PSM_VTH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29636;"	d
+RG_BUCK_PSM_VTH_SFT	include/ssv6200_aux.h	5888;"	d
+RG_BUCK_PSM_VTH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29638;"	d
+RG_BUCK_PSM_VTH_SZ	include/ssv6200_aux.h	5890;"	d
+RG_BUCK_PSM_VTH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29640;"	d
+RG_BUCK_RCZERO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29689;"	d
+RG_BUCK_RCZERO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29687;"	d
+RG_BUCK_RCZERO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29686;"	d
+RG_BUCK_RCZERO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29688;"	d
+RG_BUCK_RCZERO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29690;"	d
+RG_BUCK_SLOP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29694;"	d
+RG_BUCK_SLOP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29692;"	d
+RG_BUCK_SLOP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29691;"	d
+RG_BUCK_SLOP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29693;"	d
+RG_BUCK_SLOP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29695;"	d
+RG_BUCK_VREF_SEL_HI	include/ssv6200_aux.h	5859;"	d
+RG_BUCK_VREF_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29644;"	d
+RG_BUCK_VREF_SEL_I_MSK	include/ssv6200_aux.h	5857;"	d
+RG_BUCK_VREF_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29642;"	d
+RG_BUCK_VREF_SEL_MSK	include/ssv6200_aux.h	5856;"	d
+RG_BUCK_VREF_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29641;"	d
+RG_BUCK_VREF_SEL_SFT	include/ssv6200_aux.h	5858;"	d
+RG_BUCK_VREF_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29643;"	d
+RG_BUCK_VREF_SEL_SZ	include/ssv6200_aux.h	5860;"	d
+RG_BUCK_VREF_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29645;"	d
+RG_BW_HT40_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21629;"	d
+RG_BW_HT40_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21627;"	d
+RG_BW_HT40_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21626;"	d
+RG_BW_HT40_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21628;"	d
+RG_BW_HT40_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21630;"	d
+RG_BW_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21634;"	d
+RG_BW_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21632;"	d
+RG_BW_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21631;"	d
+RG_BW_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21633;"	d
+RG_BW_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21635;"	d
+RG_BYPASS_ACI_HI	include/ssv6200_aux.h	13014;"	d
+RG_BYPASS_ACI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30224;"	d
+RG_BYPASS_ACI_I_MSK	include/ssv6200_aux.h	13012;"	d
+RG_BYPASS_ACI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30222;"	d
+RG_BYPASS_ACI_MSK	include/ssv6200_aux.h	13011;"	d
+RG_BYPASS_ACI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30221;"	d
+RG_BYPASS_ACI_SFT	include/ssv6200_aux.h	13013;"	d
+RG_BYPASS_ACI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30223;"	d
+RG_BYPASS_ACI_SZ	include/ssv6200_aux.h	13015;"	d
+RG_BYPASS_ACI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30225;"	d
+RG_BYPASS_AGC_HI	include/ssv6200_aux.h	14344;"	d
+RG_BYPASS_AGC_I_MSK	include/ssv6200_aux.h	14342;"	d
+RG_BYPASS_AGC_MSK	include/ssv6200_aux.h	14341;"	d
+RG_BYPASS_AGC_SFT	include/ssv6200_aux.h	14343;"	d
+RG_BYPASS_AGC_SZ	include/ssv6200_aux.h	14345;"	d
+RG_BYPASS_AUDIO_LWDF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27834;"	d
+RG_BYPASS_AUDIO_LWDF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27832;"	d
+RG_BYPASS_AUDIO_LWDF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27831;"	d
+RG_BYPASS_AUDIO_LWDF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27833;"	d
+RG_BYPASS_AUDIO_LWDF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27835;"	d
+RG_BYPASS_COARSE_FREQ_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32429;"	d
+RG_BYPASS_COARSE_FREQ_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32427;"	d
+RG_BYPASS_COARSE_FREQ_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32426;"	d
+RG_BYPASS_COARSE_FREQ_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32428;"	d
+RG_BYPASS_COARSE_FREQ_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32430;"	d
+RG_BYPASS_CPE_MA_HI	include/ssv6200_aux.h	15019;"	d
+RG_BYPASS_CPE_MA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32509;"	d
+RG_BYPASS_CPE_MA_I_MSK	include/ssv6200_aux.h	15017;"	d
+RG_BYPASS_CPE_MA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32507;"	d
+RG_BYPASS_CPE_MA_MSK	include/ssv6200_aux.h	15016;"	d
+RG_BYPASS_CPE_MA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32506;"	d
+RG_BYPASS_CPE_MA_SFT	include/ssv6200_aux.h	15018;"	d
+RG_BYPASS_CPE_MA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32508;"	d
+RG_BYPASS_CPE_MA_SZ	include/ssv6200_aux.h	15020;"	d
+RG_BYPASS_CPE_MA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32510;"	d
+RG_BYPASS_DESCRAMBLER_HI	include/ssv6200_aux.h	14339;"	d
+RG_BYPASS_DESCRAMBLER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31529;"	d
+RG_BYPASS_DESCRAMBLER_I_MSK	include/ssv6200_aux.h	14337;"	d
+RG_BYPASS_DESCRAMBLER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31527;"	d
+RG_BYPASS_DESCRAMBLER_MSK	include/ssv6200_aux.h	14336;"	d
+RG_BYPASS_DESCRAMBLER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31526;"	d
+RG_BYPASS_DESCRAMBLER_SFT	include/ssv6200_aux.h	14338;"	d
+RG_BYPASS_DESCRAMBLER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31528;"	d
+RG_BYPASS_DESCRAMBLER_SZ	include/ssv6200_aux.h	14340;"	d
+RG_BYPASS_DESCRAMBLER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31530;"	d
+RG_CAL_INDEX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21614;"	d
+RG_CAL_INDEX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21612;"	d
+RG_CAL_INDEX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21611;"	d
+RG_CAL_INDEX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21613;"	d
+RG_CAL_INDEX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21615;"	d
+RG_CBW_20_40_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27304;"	d
+RG_CBW_20_40_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27302;"	d
+RG_CBW_20_40_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27301;"	d
+RG_CBW_20_40_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27303;"	d
+RG_CBW_20_40_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27305;"	d
+RG_CCA_BIT_CNT_LMT_RX_HI	include/ssv6200_aux.h	14349;"	d
+RG_CCA_BIT_CNT_LMT_RX_I_MSK	include/ssv6200_aux.h	14347;"	d
+RG_CCA_BIT_CNT_LMT_RX_MSK	include/ssv6200_aux.h	14346;"	d
+RG_CCA_BIT_CNT_LMT_RX_SFT	include/ssv6200_aux.h	14348;"	d
+RG_CCA_BIT_CNT_LMT_RX_SZ	include/ssv6200_aux.h	14350;"	d
+RG_CCA_BIT_CNT_TH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31534;"	d
+RG_CCA_BIT_CNT_TH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31532;"	d
+RG_CCA_BIT_CNT_TH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31531;"	d
+RG_CCA_BIT_CNT_TH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31533;"	d
+RG_CCA_BIT_CNT_TH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31535;"	d
+RG_CCA_POW_CNT_TH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32364;"	d
+RG_CCA_POW_CNT_TH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32362;"	d
+RG_CCA_POW_CNT_TH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32361;"	d
+RG_CCA_POW_CNT_TH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32363;"	d
+RG_CCA_POW_CNT_TH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32365;"	d
+RG_CCA_POW_SHORT_CNT_LMT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32369;"	d
+RG_CCA_POW_SHORT_CNT_LMT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32367;"	d
+RG_CCA_POW_SHORT_CNT_LMT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32366;"	d
+RG_CCA_POW_SHORT_CNT_LMT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32368;"	d
+RG_CCA_POW_SHORT_CNT_LMT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32370;"	d
+RG_CCA_POW_TH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32374;"	d
+RG_CCA_POW_TH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32372;"	d
+RG_CCA_POW_TH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32371;"	d
+RG_CCA_POW_TH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32373;"	d
+RG_CCA_POW_TH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32375;"	d
+RG_CCA_PWR_CNT_TH_HI	include/ssv6200_aux.h	14574;"	d
+RG_CCA_PWR_CNT_TH_I_MSK	include/ssv6200_aux.h	14572;"	d
+RG_CCA_PWR_CNT_TH_MSK	include/ssv6200_aux.h	14571;"	d
+RG_CCA_PWR_CNT_TH_SFT	include/ssv6200_aux.h	14573;"	d
+RG_CCA_PWR_CNT_TH_SZ	include/ssv6200_aux.h	14575;"	d
+RG_CCA_PWR_SEL_HI	include/ssv6200_aux.h	15339;"	d
+RG_CCA_PWR_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32729;"	d
+RG_CCA_PWR_SEL_I_MSK	include/ssv6200_aux.h	15337;"	d
+RG_CCA_PWR_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32727;"	d
+RG_CCA_PWR_SEL_MSK	include/ssv6200_aux.h	15336;"	d
+RG_CCA_PWR_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32726;"	d
+RG_CCA_PWR_SEL_SFT	include/ssv6200_aux.h	15338;"	d
+RG_CCA_PWR_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32728;"	d
+RG_CCA_PWR_SEL_SZ	include/ssv6200_aux.h	15340;"	d
+RG_CCA_PWR_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32730;"	d
+RG_CCA_PWR_TH_RX_HI	include/ssv6200_aux.h	14569;"	d
+RG_CCA_PWR_TH_RX_I_MSK	include/ssv6200_aux.h	14567;"	d
+RG_CCA_PWR_TH_RX_MSK	include/ssv6200_aux.h	14566;"	d
+RG_CCA_PWR_TH_RX_SFT	include/ssv6200_aux.h	14568;"	d
+RG_CCA_PWR_TH_RX_SZ	include/ssv6200_aux.h	14570;"	d
+RG_CCA_RE_CHK_BIT_CNT_TH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31519;"	d
+RG_CCA_RE_CHK_BIT_CNT_TH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31517;"	d
+RG_CCA_RE_CHK_BIT_CNT_TH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31516;"	d
+RG_CCA_RE_CHK_BIT_CNT_TH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31518;"	d
+RG_CCA_RE_CHK_BIT_CNT_TH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31520;"	d
+RG_CCA_SCALE_BF_HI	include/ssv6200_aux.h	14354;"	d
+RG_CCA_SCALE_BF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31539;"	d
+RG_CCA_SCALE_BF_I_MSK	include/ssv6200_aux.h	14352;"	d
+RG_CCA_SCALE_BF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31537;"	d
+RG_CCA_SCALE_BF_MSK	include/ssv6200_aux.h	14351;"	d
+RG_CCA_SCALE_BF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31536;"	d
+RG_CCA_SCALE_BF_SFT	include/ssv6200_aux.h	14353;"	d
+RG_CCA_SCALE_BF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31538;"	d
+RG_CCA_SCALE_BF_SZ	include/ssv6200_aux.h	14355;"	d
+RG_CCA_SCALE_BF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31540;"	d
+RG_CCA_XSCOR_AVGPWR_SEL_HI	include/ssv6200_aux.h	15349;"	d
+RG_CCA_XSCOR_AVGPWR_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32739;"	d
+RG_CCA_XSCOR_AVGPWR_SEL_I_MSK	include/ssv6200_aux.h	15347;"	d
+RG_CCA_XSCOR_AVGPWR_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32737;"	d
+RG_CCA_XSCOR_AVGPWR_SEL_MSK	include/ssv6200_aux.h	15346;"	d
+RG_CCA_XSCOR_AVGPWR_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32736;"	d
+RG_CCA_XSCOR_AVGPWR_SEL_SFT	include/ssv6200_aux.h	15348;"	d
+RG_CCA_XSCOR_AVGPWR_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32738;"	d
+RG_CCA_XSCOR_AVGPWR_SEL_SZ	include/ssv6200_aux.h	15350;"	d
+RG_CCA_XSCOR_AVGPWR_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32740;"	d
+RG_CCA_XSCOR_PWR_SEL_HI	include/ssv6200_aux.h	15344;"	d
+RG_CCA_XSCOR_PWR_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32734;"	d
+RG_CCA_XSCOR_PWR_SEL_I_MSK	include/ssv6200_aux.h	15342;"	d
+RG_CCA_XSCOR_PWR_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32732;"	d
+RG_CCA_XSCOR_PWR_SEL_MSK	include/ssv6200_aux.h	15341;"	d
+RG_CCA_XSCOR_PWR_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32731;"	d
+RG_CCA_XSCOR_PWR_SEL_SFT	include/ssv6200_aux.h	15343;"	d
+RG_CCA_XSCOR_PWR_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32733;"	d
+RG_CCA_XSCOR_PWR_SEL_SZ	include/ssv6200_aux.h	15345;"	d
+RG_CCA_XSCOR_PWR_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32735;"	d
+RG_CCFO_CNT_LMT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32424;"	d
+RG_CCFO_CNT_LMT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32422;"	d
+RG_CCFO_CNT_LMT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32421;"	d
+RG_CCFO_CNT_LMT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32423;"	d
+RG_CCFO_CNT_LMT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32425;"	d
+RG_CCFO_GAIN_BY2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32434;"	d
+RG_CCFO_GAIN_BY2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32432;"	d
+RG_CCFO_GAIN_BY2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32431;"	d
+RG_CCFO_GAIN_BY2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32433;"	d
+RG_CCFO_GAIN_BY2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32435;"	d
+RG_CCK_TR_KI_T2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31714;"	d
+RG_CCK_TR_KI_T2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31712;"	d
+RG_CCK_TR_KI_T2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31711;"	d
+RG_CCK_TR_KI_T2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31713;"	d
+RG_CCK_TR_KI_T2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31715;"	d
+RG_CCK_TR_KP_T2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31719;"	d
+RG_CCK_TR_KP_T2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31717;"	d
+RG_CCK_TR_KP_T2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31716;"	d
+RG_CCK_TR_KP_T2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31718;"	d
+RG_CCK_TR_KP_T2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31720;"	d
+RG_CE_BIT_CNT_LMT_HI	include/ssv6200_aux.h	14524;"	d
+RG_CE_BIT_CNT_LMT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31679;"	d
+RG_CE_BIT_CNT_LMT_I_MSK	include/ssv6200_aux.h	14522;"	d
+RG_CE_BIT_CNT_LMT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31677;"	d
+RG_CE_BIT_CNT_LMT_MSK	include/ssv6200_aux.h	14521;"	d
+RG_CE_BIT_CNT_LMT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31676;"	d
+RG_CE_BIT_CNT_LMT_SFT	include/ssv6200_aux.h	14523;"	d
+RG_CE_BIT_CNT_LMT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31678;"	d
+RG_CE_BIT_CNT_LMT_SZ	include/ssv6200_aux.h	14525;"	d
+RG_CE_BIT_CNT_LMT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31680;"	d
+RG_CE_BYPASS_TAP_HI	include/ssv6200_aux.h	14669;"	d
+RG_CE_BYPASS_TAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31869;"	d
+RG_CE_BYPASS_TAP_I_MSK	include/ssv6200_aux.h	14667;"	d
+RG_CE_BYPASS_TAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31867;"	d
+RG_CE_BYPASS_TAP_MSK	include/ssv6200_aux.h	14666;"	d
+RG_CE_BYPASS_TAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31866;"	d
+RG_CE_BYPASS_TAP_SFT	include/ssv6200_aux.h	14668;"	d
+RG_CE_BYPASS_TAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31868;"	d
+RG_CE_BYPASS_TAP_SZ	include/ssv6200_aux.h	14670;"	d
+RG_CE_BYPASS_TAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31870;"	d
+RG_CE_CH_MAIN_SET_HI	include/ssv6200_aux.h	14529;"	d
+RG_CE_CH_MAIN_SET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31684;"	d
+RG_CE_CH_MAIN_SET_I_MSK	include/ssv6200_aux.h	14527;"	d
+RG_CE_CH_MAIN_SET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31682;"	d
+RG_CE_CH_MAIN_SET_MSK	include/ssv6200_aux.h	14526;"	d
+RG_CE_CH_MAIN_SET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31681;"	d
+RG_CE_CH_MAIN_SET_SFT	include/ssv6200_aux.h	14528;"	d
+RG_CE_CH_MAIN_SET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31683;"	d
+RG_CE_CH_MAIN_SET_SZ	include/ssv6200_aux.h	14530;"	d
+RG_CE_CH_MAIN_SET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31685;"	d
+RG_CE_DLY_SEL_HI	include/ssv6200_aux.h	14419;"	d
+RG_CE_DLY_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31594;"	d
+RG_CE_DLY_SEL_I_MSK	include/ssv6200_aux.h	14417;"	d
+RG_CE_DLY_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31592;"	d
+RG_CE_DLY_SEL_MSK	include/ssv6200_aux.h	14416;"	d
+RG_CE_DLY_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31591;"	d
+RG_CE_DLY_SEL_SFT	include/ssv6200_aux.h	14418;"	d
+RG_CE_DLY_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31593;"	d
+RG_CE_DLY_SEL_SZ	include/ssv6200_aux.h	14420;"	d
+RG_CE_DLY_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31595;"	d
+RG_CE_MU_T1_HI	include/ssv6200_aux.h	14414;"	d
+RG_CE_MU_T1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31589;"	d
+RG_CE_MU_T1_I_MSK	include/ssv6200_aux.h	14412;"	d
+RG_CE_MU_T1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31587;"	d
+RG_CE_MU_T1_MSK	include/ssv6200_aux.h	14411;"	d
+RG_CE_MU_T1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31586;"	d
+RG_CE_MU_T1_SFT	include/ssv6200_aux.h	14413;"	d
+RG_CE_MU_T1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31588;"	d
+RG_CE_MU_T1_SZ	include/ssv6200_aux.h	14415;"	d
+RG_CE_MU_T1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31590;"	d
+RG_CE_MU_T2_HI	include/ssv6200_aux.h	14454;"	d
+RG_CE_MU_T2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31609;"	d
+RG_CE_MU_T2_I_MSK	include/ssv6200_aux.h	14452;"	d
+RG_CE_MU_T2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31607;"	d
+RG_CE_MU_T2_MSK	include/ssv6200_aux.h	14451;"	d
+RG_CE_MU_T2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31606;"	d
+RG_CE_MU_T2_SFT	include/ssv6200_aux.h	14453;"	d
+RG_CE_MU_T2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31608;"	d
+RG_CE_MU_T2_SZ	include/ssv6200_aux.h	14455;"	d
+RG_CE_MU_T2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31610;"	d
+RG_CE_MU_T3_HI	include/ssv6200_aux.h	14449;"	d
+RG_CE_MU_T3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31604;"	d
+RG_CE_MU_T3_I_MSK	include/ssv6200_aux.h	14447;"	d
+RG_CE_MU_T3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31602;"	d
+RG_CE_MU_T3_MSK	include/ssv6200_aux.h	14446;"	d
+RG_CE_MU_T3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31601;"	d
+RG_CE_MU_T3_SFT	include/ssv6200_aux.h	14448;"	d
+RG_CE_MU_T3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31603;"	d
+RG_CE_MU_T3_SZ	include/ssv6200_aux.h	14450;"	d
+RG_CE_MU_T3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31605;"	d
+RG_CE_MU_T4_HI	include/ssv6200_aux.h	14444;"	d
+RG_CE_MU_T4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31599;"	d
+RG_CE_MU_T4_I_MSK	include/ssv6200_aux.h	14442;"	d
+RG_CE_MU_T4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31597;"	d
+RG_CE_MU_T4_MSK	include/ssv6200_aux.h	14441;"	d
+RG_CE_MU_T4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31596;"	d
+RG_CE_MU_T4_SFT	include/ssv6200_aux.h	14443;"	d
+RG_CE_MU_T4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31598;"	d
+RG_CE_MU_T4_SZ	include/ssv6200_aux.h	14445;"	d
+RG_CE_MU_T4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31600;"	d
+RG_CE_MU_T5_HI	include/ssv6200_aux.h	14439;"	d
+RG_CE_MU_T5_I_MSK	include/ssv6200_aux.h	14437;"	d
+RG_CE_MU_T5_MSK	include/ssv6200_aux.h	14436;"	d
+RG_CE_MU_T5_SFT	include/ssv6200_aux.h	14438;"	d
+RG_CE_MU_T5_SZ	include/ssv6200_aux.h	14440;"	d
+RG_CE_MU_T6_HI	include/ssv6200_aux.h	14434;"	d
+RG_CE_MU_T6_I_MSK	include/ssv6200_aux.h	14432;"	d
+RG_CE_MU_T6_MSK	include/ssv6200_aux.h	14431;"	d
+RG_CE_MU_T6_SFT	include/ssv6200_aux.h	14433;"	d
+RG_CE_MU_T6_SZ	include/ssv6200_aux.h	14435;"	d
+RG_CE_MU_T7_HI	include/ssv6200_aux.h	14429;"	d
+RG_CE_MU_T7_I_MSK	include/ssv6200_aux.h	14427;"	d
+RG_CE_MU_T7_MSK	include/ssv6200_aux.h	14426;"	d
+RG_CE_MU_T7_SFT	include/ssv6200_aux.h	14428;"	d
+RG_CE_MU_T7_SZ	include/ssv6200_aux.h	14430;"	d
+RG_CE_MU_T8_HI	include/ssv6200_aux.h	14424;"	d
+RG_CE_MU_T8_I_MSK	include/ssv6200_aux.h	14422;"	d
+RG_CE_MU_T8_MSK	include/ssv6200_aux.h	14421;"	d
+RG_CE_MU_T8_SFT	include/ssv6200_aux.h	14423;"	d
+RG_CE_MU_T8_SZ	include/ssv6200_aux.h	14425;"	d
+RG_CE_T2_CNT_LMT_HI	include/ssv6200_aux.h	14409;"	d
+RG_CE_T2_CNT_LMT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31584;"	d
+RG_CE_T2_CNT_LMT_I_MSK	include/ssv6200_aux.h	14407;"	d
+RG_CE_T2_CNT_LMT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31582;"	d
+RG_CE_T2_CNT_LMT_MSK	include/ssv6200_aux.h	14406;"	d
+RG_CE_T2_CNT_LMT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31581;"	d
+RG_CE_T2_CNT_LMT_SFT	include/ssv6200_aux.h	14408;"	d
+RG_CE_T2_CNT_LMT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31583;"	d
+RG_CE_T2_CNT_LMT_SZ	include/ssv6200_aux.h	14410;"	d
+RG_CE_T2_CNT_LMT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31585;"	d
+RG_CE_T3_CNT_LMT_HI	include/ssv6200_aux.h	14404;"	d
+RG_CE_T3_CNT_LMT_I_MSK	include/ssv6200_aux.h	14402;"	d
+RG_CE_T3_CNT_LMT_MSK	include/ssv6200_aux.h	14401;"	d
+RG_CE_T3_CNT_LMT_SFT	include/ssv6200_aux.h	14403;"	d
+RG_CE_T3_CNT_LMT_SZ	include/ssv6200_aux.h	14405;"	d
+RG_CE_T4_CNT_LMT_HI	include/ssv6200_aux.h	14399;"	d
+RG_CE_T4_CNT_LMT_I_MSK	include/ssv6200_aux.h	14397;"	d
+RG_CE_T4_CNT_LMT_MSK	include/ssv6200_aux.h	14396;"	d
+RG_CE_T4_CNT_LMT_SFT	include/ssv6200_aux.h	14398;"	d
+RG_CE_T4_CNT_LMT_SZ	include/ssv6200_aux.h	14400;"	d
+RG_CFR_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28974;"	d
+RG_CFR_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28972;"	d
+RG_CFR_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28971;"	d
+RG_CFR_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28973;"	d
+RG_CFR_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28975;"	d
+RG_CFR_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28964;"	d
+RG_CFR_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28962;"	d
+RG_CFR_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28961;"	d
+RG_CFR_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28963;"	d
+RG_CFR_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28965;"	d
+RG_CFR_PEAK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28969;"	d
+RG_CFR_PEAK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28967;"	d
+RG_CFR_PEAK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28966;"	d
+RG_CFR_PEAK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28968;"	d
+RG_CFR_PEAK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28970;"	d
+RG_CHEST_DD_FACTOR_HI	include/ssv6200_aux.h	15049;"	d
+RG_CHEST_DD_FACTOR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32524;"	d
+RG_CHEST_DD_FACTOR_I_MSK	include/ssv6200_aux.h	15047;"	d
+RG_CHEST_DD_FACTOR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32522;"	d
+RG_CHEST_DD_FACTOR_MSK	include/ssv6200_aux.h	15046;"	d
+RG_CHEST_DD_FACTOR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32521;"	d
+RG_CHEST_DD_FACTOR_SFT	include/ssv6200_aux.h	15048;"	d
+RG_CHEST_DD_FACTOR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32523;"	d
+RG_CHEST_DD_FACTOR_SZ	include/ssv6200_aux.h	15050;"	d
+RG_CHEST_DD_FACTOR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32525;"	d
+RG_CHIP_CNT_SLICER_HI	include/ssv6200_aux.h	14394;"	d
+RG_CHIP_CNT_SLICER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31579;"	d
+RG_CHIP_CNT_SLICER_I_MSK	include/ssv6200_aux.h	14392;"	d
+RG_CHIP_CNT_SLICER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31577;"	d
+RG_CHIP_CNT_SLICER_MSK	include/ssv6200_aux.h	14391;"	d
+RG_CHIP_CNT_SLICER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31576;"	d
+RG_CHIP_CNT_SLICER_SFT	include/ssv6200_aux.h	14393;"	d
+RG_CHIP_CNT_SLICER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31578;"	d
+RG_CHIP_CNT_SLICER_SZ	include/ssv6200_aux.h	14395;"	d
+RG_CHIP_CNT_SLICER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31580;"	d
+RG_CHSMTH_COEF_HI	include/ssv6200_aux.h	15039;"	d
+RG_CHSMTH_COEF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32514;"	d
+RG_CHSMTH_COEF_I_MSK	include/ssv6200_aux.h	15037;"	d
+RG_CHSMTH_COEF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32512;"	d
+RG_CHSMTH_COEF_MSK	include/ssv6200_aux.h	15036;"	d
+RG_CHSMTH_COEF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32511;"	d
+RG_CHSMTH_COEF_SFT	include/ssv6200_aux.h	15038;"	d
+RG_CHSMTH_COEF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32513;"	d
+RG_CHSMTH_COEF_SZ	include/ssv6200_aux.h	15040;"	d
+RG_CHSMTH_COEF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32515;"	d
+RG_CHSMTH_EN_HI	include/ssv6200_aux.h	15044;"	d
+RG_CHSMTH_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32519;"	d
+RG_CHSMTH_EN_I_MSK	include/ssv6200_aux.h	15042;"	d
+RG_CHSMTH_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32517;"	d
+RG_CHSMTH_EN_MSK	include/ssv6200_aux.h	15041;"	d
+RG_CHSMTH_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32516;"	d
+RG_CHSMTH_EN_SFT	include/ssv6200_aux.h	15043;"	d
+RG_CHSMTH_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32518;"	d
+RG_CHSMTH_EN_SZ	include/ssv6200_aux.h	15045;"	d
+RG_CHSMTH_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32520;"	d
+RG_CH_BW_HI	include/ssv6200_aux.h	13144;"	d
+RG_CH_BW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30334;"	d
+RG_CH_BW_I_MSK	include/ssv6200_aux.h	13142;"	d
+RG_CH_BW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30332;"	d
+RG_CH_BW_MSK	include/ssv6200_aux.h	13141;"	d
+RG_CH_BW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30331;"	d
+RG_CH_BW_SFT	include/ssv6200_aux.h	13143;"	d
+RG_CH_BW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30333;"	d
+RG_CH_BW_SZ	include/ssv6200_aux.h	13145;"	d
+RG_CH_BW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30335;"	d
+RG_CH_UPDATE_HI	include/ssv6200_aux.h	15054;"	d
+RG_CH_UPDATE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32529;"	d
+RG_CH_UPDATE_I_MSK	include/ssv6200_aux.h	15052;"	d
+RG_CH_UPDATE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32527;"	d
+RG_CH_UPDATE_MSK	include/ssv6200_aux.h	15051;"	d
+RG_CH_UPDATE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32526;"	d
+RG_CH_UPDATE_SFT	include/ssv6200_aux.h	15053;"	d
+RG_CH_UPDATE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32528;"	d
+RG_CH_UPDATE_SZ	include/ssv6200_aux.h	15055;"	d
+RG_CH_UPDATE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32530;"	d
+RG_CLK_320M_INV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27294;"	d
+RG_CLK_320M_INV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27292;"	d
+RG_CLK_320M_INV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27291;"	d
+RG_CLK_320M_INV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27293;"	d
+RG_CLK_320M_INV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27295;"	d
+RG_CLK_RTC_SW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29839;"	d
+RG_CLK_RTC_SW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29837;"	d
+RG_CLK_RTC_SW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29836;"	d
+RG_CLK_RTC_SW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29838;"	d
+RG_CLK_RTC_SW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29840;"	d
+RG_CLK_SAR_SEL_HI	include/ssv6200_aux.h	16834;"	d
+RG_CLK_SAR_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22969;"	d
+RG_CLK_SAR_SEL_I_MSK	include/ssv6200_aux.h	16832;"	d
+RG_CLK_SAR_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22967;"	d
+RG_CLK_SAR_SEL_MSK	include/ssv6200_aux.h	16831;"	d
+RG_CLK_SAR_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22966;"	d
+RG_CLK_SAR_SEL_SFT	include/ssv6200_aux.h	16833;"	d
+RG_CLK_SAR_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22968;"	d
+RG_CLK_SAR_SEL_SZ	include/ssv6200_aux.h	16835;"	d
+RG_CLK_SAR_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22970;"	d
+RG_CLOCK_BF_MUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29564;"	d
+RG_CLOCK_BF_MUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29562;"	d
+RG_CLOCK_BF_MUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29561;"	d
+RG_CLOCK_BF_MUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29563;"	d
+RG_CLOCK_BF_MUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29565;"	d
+RG_CNT_CCA_LMT_HI	include/ssv6200_aux.h	14334;"	d
+RG_CNT_CCA_LMT_I_MSK	include/ssv6200_aux.h	14332;"	d
+RG_CNT_CCA_LMT_MSK	include/ssv6200_aux.h	14331;"	d
+RG_CNT_CCA_LMT_SFT	include/ssv6200_aux.h	14333;"	d
+RG_CNT_CCA_LMT_SZ	include/ssv6200_aux.h	14335;"	d
+RG_CNT_CCA_RE_CHK_LMT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31524;"	d
+RG_CNT_CCA_RE_CHK_LMT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31522;"	d
+RG_CNT_CCA_RE_CHK_LMT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31521;"	d
+RG_CNT_CCA_RE_CHK_LMT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31523;"	d
+RG_CNT_CCA_RE_CHK_LMT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31525;"	d
+RG_CONTINUOUS_DATA_11GN_HI	include/ssv6200_aux.h	14709;"	d
+RG_CONTINUOUS_DATA_11GN_I_MSK	include/ssv6200_aux.h	14707;"	d
+RG_CONTINUOUS_DATA_11GN_MSK	include/ssv6200_aux.h	14706;"	d
+RG_CONTINUOUS_DATA_11GN_SFT	include/ssv6200_aux.h	14708;"	d
+RG_CONTINUOUS_DATA_11GN_SZ	include/ssv6200_aux.h	14710;"	d
+RG_CONTINUOUS_DATA_HI	include/ssv6200_aux.h	13224;"	d
+RG_CONTINUOUS_DATA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30419;"	d
+RG_CONTINUOUS_DATA_I_MSK	include/ssv6200_aux.h	13222;"	d
+RG_CONTINUOUS_DATA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30417;"	d
+RG_CONTINUOUS_DATA_MSK	include/ssv6200_aux.h	13221;"	d
+RG_CONTINUOUS_DATA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30416;"	d
+RG_CONTINUOUS_DATA_SFT	include/ssv6200_aux.h	13223;"	d
+RG_CONTINUOUS_DATA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30418;"	d
+RG_CONTINUOUS_DATA_SZ	include/ssv6200_aux.h	13225;"	d
+RG_CONTINUOUS_DATA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30420;"	d
+RG_COR_SEL_HI	include/ssv6200_aux.h	15319;"	d
+RG_COR_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32719;"	d
+RG_COR_SEL_I_MSK	include/ssv6200_aux.h	15317;"	d
+RG_COR_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32717;"	d
+RG_COR_SEL_MSK	include/ssv6200_aux.h	15316;"	d
+RG_COR_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32716;"	d
+RG_COR_SEL_SFT	include/ssv6200_aux.h	15318;"	d
+RG_COR_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32718;"	d
+RG_COR_SEL_SZ	include/ssv6200_aux.h	15320;"	d
+RG_COR_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32720;"	d
+RG_CPE_SEL_16QAM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32494;"	d
+RG_CPE_SEL_16QAM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32492;"	d
+RG_CPE_SEL_16QAM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32491;"	d
+RG_CPE_SEL_16QAM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32493;"	d
+RG_CPE_SEL_16QAM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32495;"	d
+RG_CPE_SEL_64QAM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32489;"	d
+RG_CPE_SEL_64QAM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32487;"	d
+RG_CPE_SEL_64QAM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32486;"	d
+RG_CPE_SEL_64QAM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32488;"	d
+RG_CPE_SEL_64QAM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32490;"	d
+RG_CPE_SEL_BPSK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32504;"	d
+RG_CPE_SEL_BPSK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32502;"	d
+RG_CPE_SEL_BPSK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32501;"	d
+RG_CPE_SEL_BPSK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32503;"	d
+RG_CPE_SEL_BPSK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32505;"	d
+RG_CPE_SEL_QPSK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32499;"	d
+RG_CPE_SEL_QPSK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32497;"	d
+RG_CPE_SEL_QPSK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32496;"	d
+RG_CPE_SEL_QPSK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32498;"	d
+RG_CPE_SEL_QPSK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32500;"	d
+RG_CR_BIT_CNT_LMT_HI	include/ssv6200_aux.h	14539;"	d
+RG_CR_BIT_CNT_LMT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31694;"	d
+RG_CR_BIT_CNT_LMT_I_MSK	include/ssv6200_aux.h	14537;"	d
+RG_CR_BIT_CNT_LMT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31692;"	d
+RG_CR_BIT_CNT_LMT_MSK	include/ssv6200_aux.h	14536;"	d
+RG_CR_BIT_CNT_LMT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31691;"	d
+RG_CR_BIT_CNT_LMT_SFT	include/ssv6200_aux.h	14538;"	d
+RG_CR_BIT_CNT_LMT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31693;"	d
+RG_CR_BIT_CNT_LMT_SZ	include/ssv6200_aux.h	14540;"	d
+RG_CR_BIT_CNT_LMT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31695;"	d
+RG_CR_CNT_UPDATE_HI	include/ssv6200_aux.h	15009;"	d
+RG_CR_CNT_UPDATE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32479;"	d
+RG_CR_CNT_UPDATE_I_MSK	include/ssv6200_aux.h	15007;"	d
+RG_CR_CNT_UPDATE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32477;"	d
+RG_CR_CNT_UPDATE_MSK	include/ssv6200_aux.h	15006;"	d
+RG_CR_CNT_UPDATE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32476;"	d
+RG_CR_CNT_UPDATE_SFT	include/ssv6200_aux.h	15008;"	d
+RG_CR_CNT_UPDATE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32478;"	d
+RG_CR_CNT_UPDATE_SGI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32469;"	d
+RG_CR_CNT_UPDATE_SGI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32467;"	d
+RG_CR_CNT_UPDATE_SGI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32466;"	d
+RG_CR_CNT_UPDATE_SGI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32468;"	d
+RG_CR_CNT_UPDATE_SGI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32470;"	d
+RG_CR_CNT_UPDATE_SZ	include/ssv6200_aux.h	15010;"	d
+RG_CR_CNT_UPDATE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32480;"	d
+RG_CR_KI_T1_HI	include/ssv6200_aux.h	14384;"	d
+RG_CR_KI_T1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31569;"	d
+RG_CR_KI_T1_I_MSK	include/ssv6200_aux.h	14382;"	d
+RG_CR_KI_T1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31567;"	d
+RG_CR_KI_T1_MSK	include/ssv6200_aux.h	14381;"	d
+RG_CR_KI_T1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31566;"	d
+RG_CR_KI_T1_SFT	include/ssv6200_aux.h	14383;"	d
+RG_CR_KI_T1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31568;"	d
+RG_CR_KI_T1_SZ	include/ssv6200_aux.h	14385;"	d
+RG_CR_KI_T1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31570;"	d
+RG_CR_KP_T1_HI	include/ssv6200_aux.h	14389;"	d
+RG_CR_KP_T1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31574;"	d
+RG_CR_KP_T1_I_MSK	include/ssv6200_aux.h	14387;"	d
+RG_CR_KP_T1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31572;"	d
+RG_CR_KP_T1_MSK	include/ssv6200_aux.h	14386;"	d
+RG_CR_KP_T1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31571;"	d
+RG_CR_KP_T1_SFT	include/ssv6200_aux.h	14388;"	d
+RG_CR_KP_T1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31573;"	d
+RG_CR_KP_T1_SZ	include/ssv6200_aux.h	14390;"	d
+RG_CR_KP_T1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31575;"	d
+RG_CR_LPF_KI_GN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32034;"	d
+RG_CR_LPF_KI_GN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32032;"	d
+RG_CR_LPF_KI_GN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32031;"	d
+RG_CR_LPF_KI_GN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32033;"	d
+RG_CR_LPF_KI_GN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32035;"	d
+RG_CR_LPF_KI_G_HI	include/ssv6200_aux.h	14794;"	d
+RG_CR_LPF_KI_G_I_MSK	include/ssv6200_aux.h	14792;"	d
+RG_CR_LPF_KI_G_MSK	include/ssv6200_aux.h	14791;"	d
+RG_CR_LPF_KI_G_SFT	include/ssv6200_aux.h	14793;"	d
+RG_CR_LPF_KI_G_SZ	include/ssv6200_aux.h	14795;"	d
+RG_DACI1ST_HI	include/ssv6200_aux.h	16844;"	d
+RG_DACI1ST_I_MSK	include/ssv6200_aux.h	16842;"	d
+RG_DACI1ST_MSK	include/ssv6200_aux.h	16841;"	d
+RG_DACI1ST_SFT	include/ssv6200_aux.h	16843;"	d
+RG_DACI1ST_SZ	include/ssv6200_aux.h	16845;"	d
+RG_DAC_DBG_MODE_HI	include/ssv6200_aux.h	13249;"	d
+RG_DAC_DBG_MODE_I_MSK	include/ssv6200_aux.h	13247;"	d
+RG_DAC_DBG_MODE_MSK	include/ssv6200_aux.h	13246;"	d
+RG_DAC_DBG_MODE_SFT	include/ssv6200_aux.h	13248;"	d
+RG_DAC_DBG_MODE_SZ	include/ssv6200_aux.h	13250;"	d
+RG_DAC_DCEN_HI	include/ssv6200_aux.h	13279;"	d
+RG_DAC_DCEN_I_MSK	include/ssv6200_aux.h	13277;"	d
+RG_DAC_DCEN_MSK	include/ssv6200_aux.h	13276;"	d
+RG_DAC_DCEN_SFT	include/ssv6200_aux.h	13278;"	d
+RG_DAC_DCEN_SZ	include/ssv6200_aux.h	13280;"	d
+RG_DAC_DCI_HI	include/ssv6200_aux.h	13289;"	d
+RG_DAC_DCI_I_MSK	include/ssv6200_aux.h	13287;"	d
+RG_DAC_DCI_MSK	include/ssv6200_aux.h	13286;"	d
+RG_DAC_DCI_SFT	include/ssv6200_aux.h	13288;"	d
+RG_DAC_DCI_SZ	include/ssv6200_aux.h	13290;"	d
+RG_DAC_DCQ_HI	include/ssv6200_aux.h	13284;"	d
+RG_DAC_DCQ_I_MSK	include/ssv6200_aux.h	13282;"	d
+RG_DAC_DCQ_MSK	include/ssv6200_aux.h	13281;"	d
+RG_DAC_DCQ_SFT	include/ssv6200_aux.h	13283;"	d
+RG_DAC_DCQ_SZ	include/ssv6200_aux.h	13285;"	d
+RG_DAC_DC_I_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27314;"	d
+RG_DAC_DC_I_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27312;"	d
+RG_DAC_DC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27311;"	d
+RG_DAC_DC_I_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27313;"	d
+RG_DAC_DC_I_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27315;"	d
+RG_DAC_DC_Q_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27309;"	d
+RG_DAC_DC_Q_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27307;"	d
+RG_DAC_DC_Q_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27306;"	d
+RG_DAC_DC_Q_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27308;"	d
+RG_DAC_DC_Q_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27310;"	d
+RG_DAC_EN_MAN_HI	include/ssv6200_aux.h	13799;"	d
+RG_DAC_EN_MAN_I_MSK	include/ssv6200_aux.h	13797;"	d
+RG_DAC_EN_MAN_MSK	include/ssv6200_aux.h	13796;"	d
+RG_DAC_EN_MAN_SFT	include/ssv6200_aux.h	13798;"	d
+RG_DAC_EN_MAN_SZ	include/ssv6200_aux.h	13800;"	d
+RG_DAC_FALL_TIME_HI	include/ssv6200_aux.h	13859;"	d
+RG_DAC_FALL_TIME_I_MSK	include/ssv6200_aux.h	13857;"	d
+RG_DAC_FALL_TIME_MSK	include/ssv6200_aux.h	13856;"	d
+RG_DAC_FALL_TIME_SFT	include/ssv6200_aux.h	13858;"	d
+RG_DAC_FALL_TIME_SZ	include/ssv6200_aux.h	13860;"	d
+RG_DAC_I_SET_HI	include/ssv6200_aux.h	13794;"	d
+RG_DAC_I_SET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27329;"	d
+RG_DAC_I_SET_I_MSK	include/ssv6200_aux.h	13792;"	d
+RG_DAC_I_SET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27327;"	d
+RG_DAC_I_SET_MSK	include/ssv6200_aux.h	13791;"	d
+RG_DAC_I_SET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27326;"	d
+RG_DAC_I_SET_SFT	include/ssv6200_aux.h	13793;"	d
+RG_DAC_I_SET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27328;"	d
+RG_DAC_I_SET_SZ	include/ssv6200_aux.h	13795;"	d
+RG_DAC_I_SET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27330;"	d
+RG_DAC_LBK_EDGE_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30194;"	d
+RG_DAC_LBK_EDGE_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30192;"	d
+RG_DAC_LBK_EDGE_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30191;"	d
+RG_DAC_LBK_EDGE_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30193;"	d
+RG_DAC_LBK_EDGE_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30195;"	d
+RG_DAC_MAN_I_EN_HI	include/ssv6200_aux.h	13814;"	d
+RG_DAC_MAN_I_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27334;"	d
+RG_DAC_MAN_I_EN_I_MSK	include/ssv6200_aux.h	13812;"	d
+RG_DAC_MAN_I_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27332;"	d
+RG_DAC_MAN_I_EN_MSK	include/ssv6200_aux.h	13811;"	d
+RG_DAC_MAN_I_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27331;"	d
+RG_DAC_MAN_I_EN_SFT	include/ssv6200_aux.h	13813;"	d
+RG_DAC_MAN_I_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27333;"	d
+RG_DAC_MAN_I_EN_SZ	include/ssv6200_aux.h	13815;"	d
+RG_DAC_MAN_I_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27335;"	d
+RG_DAC_MAN_Q_EN_HI	include/ssv6200_aux.h	13809;"	d
+RG_DAC_MAN_Q_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27324;"	d
+RG_DAC_MAN_Q_EN_I_MSK	include/ssv6200_aux.h	13807;"	d
+RG_DAC_MAN_Q_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27322;"	d
+RG_DAC_MAN_Q_EN_MSK	include/ssv6200_aux.h	13806;"	d
+RG_DAC_MAN_Q_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27321;"	d
+RG_DAC_MAN_Q_EN_SFT	include/ssv6200_aux.h	13808;"	d
+RG_DAC_MAN_Q_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27323;"	d
+RG_DAC_MAN_Q_EN_SZ	include/ssv6200_aux.h	13810;"	d
+RG_DAC_MAN_Q_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27325;"	d
+RG_DAC_Q_SET_HI	include/ssv6200_aux.h	13789;"	d
+RG_DAC_Q_SET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27319;"	d
+RG_DAC_Q_SET_I_MSK	include/ssv6200_aux.h	13787;"	d
+RG_DAC_Q_SET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27317;"	d
+RG_DAC_Q_SET_MSK	include/ssv6200_aux.h	13786;"	d
+RG_DAC_Q_SET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27316;"	d
+RG_DAC_Q_SET_SFT	include/ssv6200_aux.h	13788;"	d
+RG_DAC_Q_SET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27318;"	d
+RG_DAC_Q_SET_SZ	include/ssv6200_aux.h	13790;"	d
+RG_DAC_Q_SET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27320;"	d
+RG_DAC_RISE_TIME_HI	include/ssv6200_aux.h	13839;"	d
+RG_DAC_RISE_TIME_I_MSK	include/ssv6200_aux.h	13837;"	d
+RG_DAC_RISE_TIME_MSK	include/ssv6200_aux.h	13836;"	d
+RG_DAC_RISE_TIME_SFT	include/ssv6200_aux.h	13838;"	d
+RG_DAC_RISE_TIME_SZ	include/ssv6200_aux.h	13840;"	d
+RG_DAC_SGN_SWAP_HI	include/ssv6200_aux.h	13254;"	d
+RG_DAC_SGN_SWAP_I_MSK	include/ssv6200_aux.h	13252;"	d
+RG_DAC_SGN_SWAP_MSK	include/ssv6200_aux.h	13251;"	d
+RG_DAC_SGN_SWAP_SFT	include/ssv6200_aux.h	13253;"	d
+RG_DAC_SGN_SWAP_SZ	include/ssv6200_aux.h	13255;"	d
+RG_DAGC_CNT_TH_HI	include/ssv6200_aux.h	15294;"	d
+RG_DAGC_CNT_TH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32689;"	d
+RG_DAGC_CNT_TH_I_MSK	include/ssv6200_aux.h	15292;"	d
+RG_DAGC_CNT_TH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32687;"	d
+RG_DAGC_CNT_TH_MSK	include/ssv6200_aux.h	15291;"	d
+RG_DAGC_CNT_TH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32686;"	d
+RG_DAGC_CNT_TH_SFT	include/ssv6200_aux.h	15293;"	d
+RG_DAGC_CNT_TH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32688;"	d
+RG_DAGC_CNT_TH_SZ	include/ssv6200_aux.h	15295;"	d
+RG_DAGC_CNT_TH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32690;"	d
+RG_DATA_SEL_HI	include/ssv6200_aux.h	13229;"	d
+RG_DATA_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30424;"	d
+RG_DATA_SEL_I_MSK	include/ssv6200_aux.h	13227;"	d
+RG_DATA_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30422;"	d
+RG_DATA_SEL_MSK	include/ssv6200_aux.h	13226;"	d
+RG_DATA_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30421;"	d
+RG_DATA_SEL_SFT	include/ssv6200_aux.h	13228;"	d
+RG_DATA_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30423;"	d
+RG_DATA_SEL_SZ	include/ssv6200_aux.h	13230;"	d
+RG_DATA_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30425;"	d
+RG_DBIST_MODE_16_HI	include/ssv6200_aux.h	13989;"	d
+RG_DBIST_MODE_16_I_MSK	include/ssv6200_aux.h	13987;"	d
+RG_DBIST_MODE_16_MSK	include/ssv6200_aux.h	13986;"	d
+RG_DBIST_MODE_16_SFT	include/ssv6200_aux.h	13988;"	d
+RG_DBIST_MODE_16_SZ	include/ssv6200_aux.h	13990;"	d
+RG_DBIST_MODE_64_HI	include/ssv6200_aux.h	15179;"	d
+RG_DBIST_MODE_64_I_MSK	include/ssv6200_aux.h	15177;"	d
+RG_DBIST_MODE_64_MSK	include/ssv6200_aux.h	15176;"	d
+RG_DBIST_MODE_64_SFT	include/ssv6200_aux.h	15178;"	d
+RG_DBIST_MODE_64_SZ	include/ssv6200_aux.h	15180;"	d
+RG_DBIST_MODE_80_HI	include/ssv6200_aux.h	15144;"	d
+RG_DBIST_MODE_80_I_MSK	include/ssv6200_aux.h	15142;"	d
+RG_DBIST_MODE_80_MSK	include/ssv6200_aux.h	15141;"	d
+RG_DBIST_MODE_80_SFT	include/ssv6200_aux.h	15143;"	d
+RG_DBIST_MODE_80_SZ	include/ssv6200_aux.h	15145;"	d
+RG_DCDC_CLK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29684;"	d
+RG_DCDC_CLK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29682;"	d
+RG_DCDC_CLK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29681;"	d
+RG_DCDC_CLK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29683;"	d
+RG_DCDC_CLK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29685;"	d
+RG_DCDC_MODE_HI	include/ssv6200_aux.h	5879;"	d
+RG_DCDC_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29614;"	d
+RG_DCDC_MODE_I_MSK	include/ssv6200_aux.h	5877;"	d
+RG_DCDC_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29612;"	d
+RG_DCDC_MODE_MSK	include/ssv6200_aux.h	5876;"	d
+RG_DCDC_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29611;"	d
+RG_DCDC_MODE_SFT	include/ssv6200_aux.h	5878;"	d
+RG_DCDC_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29613;"	d
+RG_DCDC_MODE_SLP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30069;"	d
+RG_DCDC_MODE_SLP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30067;"	d
+RG_DCDC_MODE_SLP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30066;"	d
+RG_DCDC_MODE_SLP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30068;"	d
+RG_DCDC_MODE_SLP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30070;"	d
+RG_DCDC_MODE_SZ	include/ssv6200_aux.h	5880;"	d
+RG_DCDC_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29615;"	d
+RG_DCDC_PULLLOW_CON_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29659;"	d
+RG_DCDC_PULLLOW_CON_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29657;"	d
+RG_DCDC_PULLLOW_CON_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29656;"	d
+RG_DCDC_PULLLOW_CON_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29658;"	d
+RG_DCDC_PULLLOW_CON_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29660;"	d
+RG_DCDC_RES2_CON_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29664;"	d
+RG_DCDC_RES2_CON_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29662;"	d
+RG_DCDC_RES2_CON_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29661;"	d
+RG_DCDC_RES2_CON_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29663;"	d
+RG_DCDC_RES2_CON_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29665;"	d
+RG_DCDC_RES_CON_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29669;"	d
+RG_DCDC_RES_CON_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29667;"	d
+RG_DCDC_RES_CON_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29666;"	d
+RG_DCDC_RES_CON_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29668;"	d
+RG_DCDC_RES_CON_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29670;"	d
+RG_DC_RM_BYP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30779;"	d
+RG_DC_RM_BYP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30777;"	d
+RG_DC_RM_BYP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30776;"	d
+RG_DC_RM_BYP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30778;"	d
+RG_DC_RM_BYP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30780;"	d
+RG_DC_RM_LEAKY_FACTOR_T1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30794;"	d
+RG_DC_RM_LEAKY_FACTOR_T1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30792;"	d
+RG_DC_RM_LEAKY_FACTOR_T1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30791;"	d
+RG_DC_RM_LEAKY_FACTOR_T1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30793;"	d
+RG_DC_RM_LEAKY_FACTOR_T1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30795;"	d
+RG_DC_RM_LEAKY_FACTOR_T2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30789;"	d
+RG_DC_RM_LEAKY_FACTOR_T2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30787;"	d
+RG_DC_RM_LEAKY_FACTOR_T2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30786;"	d
+RG_DC_RM_LEAKY_FACTOR_T2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30788;"	d
+RG_DC_RM_LEAKY_FACTOR_T2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30790;"	d
+RG_DC_RM_LEAKY_FACTOR_T3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30784;"	d
+RG_DC_RM_LEAKY_FACTOR_T3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30782;"	d
+RG_DC_RM_LEAKY_FACTOR_T3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30781;"	d
+RG_DC_RM_LEAKY_FACTOR_T3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30783;"	d
+RG_DC_RM_LEAKY_FACTOR_T3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30785;"	d
+RG_DEBUG_SEL_11B_RX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31879;"	d
+RG_DEBUG_SEL_11B_RX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31877;"	d
+RG_DEBUG_SEL_11B_RX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31876;"	d
+RG_DEBUG_SEL_11B_RX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31878;"	d
+RG_DEBUG_SEL_11B_RX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31880;"	d
+RG_DEBUG_SEL_11B_TX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31499;"	d
+RG_DEBUG_SEL_11B_TX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31497;"	d
+RG_DEBUG_SEL_11B_TX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31496;"	d
+RG_DEBUG_SEL_11B_TX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31498;"	d
+RG_DEBUG_SEL_11B_TX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31500;"	d
+RG_DEBUG_SEL_11GN_RX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32744;"	d
+RG_DEBUG_SEL_11GN_RX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32742;"	d
+RG_DEBUG_SEL_11GN_RX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32741;"	d
+RG_DEBUG_SEL_11GN_RX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32743;"	d
+RG_DEBUG_SEL_11GN_RX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32745;"	d
+RG_DEBUG_SEL_11GN_TX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31979;"	d
+RG_DEBUG_SEL_11GN_TX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31977;"	d
+RG_DEBUG_SEL_11GN_TX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31976;"	d
+RG_DEBUG_SEL_11GN_TX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31978;"	d
+RG_DEBUG_SEL_11GN_TX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31980;"	d
+RG_DEBUG_SEL_HI	include/ssv6200_aux.h	15354;"	d
+RG_DEBUG_SEL_I_MSK	include/ssv6200_aux.h	15352;"	d
+RG_DEBUG_SEL_MSK	include/ssv6200_aux.h	15351;"	d
+RG_DEBUG_SEL_SFT	include/ssv6200_aux.h	15353;"	d
+RG_DEBUG_SEL_SZ	include/ssv6200_aux.h	15355;"	d
+RG_DES_MAN_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30459;"	d
+RG_DES_MAN_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30457;"	d
+RG_DES_MAN_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30456;"	d
+RG_DES_MAN_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30458;"	d
+RG_DES_MAN_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30460;"	d
+RG_DES_RATE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30454;"	d
+RG_DES_RATE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30452;"	d
+RG_DES_RATE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30451;"	d
+RG_DES_RATE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30453;"	d
+RG_DES_RATE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30455;"	d
+RG_DES_SPD_HI	include/ssv6200_aux.h	14294;"	d
+RG_DES_SPD_I_MSK	include/ssv6200_aux.h	14292;"	d
+RG_DES_SPD_MSK	include/ssv6200_aux.h	14291;"	d
+RG_DES_SPD_SFT	include/ssv6200_aux.h	14293;"	d
+RG_DES_SPD_SZ	include/ssv6200_aux.h	14295;"	d
+RG_DICMP_HI	include/ssv6200_aux.h	16804;"	d
+RG_DICMP_I_MSK	include/ssv6200_aux.h	16802;"	d
+RG_DICMP_MSK	include/ssv6200_aux.h	16801;"	d
+RG_DICMP_SFT	include/ssv6200_aux.h	16803;"	d
+RG_DICMP_SZ	include/ssv6200_aux.h	16805;"	d
+RG_DIOP_HI	include/ssv6200_aux.h	16809;"	d
+RG_DIOP_I_MSK	include/ssv6200_aux.h	16807;"	d
+RG_DIOP_MSK	include/ssv6200_aux.h	16806;"	d
+RG_DIOP_SFT	include/ssv6200_aux.h	16808;"	d
+RG_DIOP_SZ	include/ssv6200_aux.h	16810;"	d
+RG_DIS_DAC_OFFSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27289;"	d
+RG_DIS_DAC_OFFSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27287;"	d
+RG_DIS_DAC_OFFSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27286;"	d
+RG_DIS_DAC_OFFSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27288;"	d
+RG_DIS_DAC_OFFSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27290;"	d
+RG_DLDO_BOOST_IQ_HI	include/ssv6200_aux.h	5849;"	d
+RG_DLDO_BOOST_IQ_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29629;"	d
+RG_DLDO_BOOST_IQ_I_MSK	include/ssv6200_aux.h	5847;"	d
+RG_DLDO_BOOST_IQ_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29627;"	d
+RG_DLDO_BOOST_IQ_MSK	include/ssv6200_aux.h	5846;"	d
+RG_DLDO_BOOST_IQ_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29626;"	d
+RG_DLDO_BOOST_IQ_SFT	include/ssv6200_aux.h	5848;"	d
+RG_DLDO_BOOST_IQ_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29628;"	d
+RG_DLDO_BOOST_IQ_SZ	include/ssv6200_aux.h	5850;"	d
+RG_DLDO_BOOST_IQ_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29630;"	d
+RG_DLDO_LEVEL_HI	include/ssv6200_aux.h	5844;"	d
+RG_DLDO_LEVEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29619;"	d
+RG_DLDO_LEVEL_I_MSK	include/ssv6200_aux.h	5842;"	d
+RG_DLDO_LEVEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29617;"	d
+RG_DLDO_LEVEL_MSK	include/ssv6200_aux.h	5841;"	d
+RG_DLDO_LEVEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29616;"	d
+RG_DLDO_LEVEL_SFT	include/ssv6200_aux.h	5843;"	d
+RG_DLDO_LEVEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29618;"	d
+RG_DLDO_LEVEL_SLP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30074;"	d
+RG_DLDO_LEVEL_SLP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30072;"	d
+RG_DLDO_LEVEL_SLP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30071;"	d
+RG_DLDO_LEVEL_SLP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30073;"	d
+RG_DLDO_LEVEL_SLP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30075;"	d
+RG_DLDO_LEVEL_SZ	include/ssv6200_aux.h	5845;"	d
+RG_DLDO_LEVEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29620;"	d
+RG_DO_NOT_CHECK_L_RATE_HI	include/ssv6200_aux.h	15069;"	d
+RG_DO_NOT_CHECK_L_RATE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32544;"	d
+RG_DO_NOT_CHECK_L_RATE_I_MSK	include/ssv6200_aux.h	15067;"	d
+RG_DO_NOT_CHECK_L_RATE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32542;"	d
+RG_DO_NOT_CHECK_L_RATE_MSK	include/ssv6200_aux.h	15066;"	d
+RG_DO_NOT_CHECK_L_RATE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32541;"	d
+RG_DO_NOT_CHECK_L_RATE_SFT	include/ssv6200_aux.h	15068;"	d
+RG_DO_NOT_CHECK_L_RATE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32543;"	d
+RG_DO_NOT_CHECK_L_RATE_SZ	include/ssv6200_aux.h	15070;"	d
+RG_DO_NOT_CHECK_L_RATE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32545;"	d
+RG_DPD_020_GAIN_HI	include/ssv6200_aux.h	15754;"	d
+RG_DPD_020_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29054;"	d
+RG_DPD_020_GAIN_I_MSK	include/ssv6200_aux.h	15752;"	d
+RG_DPD_020_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29052;"	d
+RG_DPD_020_GAIN_MSK	include/ssv6200_aux.h	15751;"	d
+RG_DPD_020_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29051;"	d
+RG_DPD_020_GAIN_SFT	include/ssv6200_aux.h	15753;"	d
+RG_DPD_020_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29053;"	d
+RG_DPD_020_GAIN_SZ	include/ssv6200_aux.h	15755;"	d
+RG_DPD_020_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29055;"	d
+RG_DPD_020_PH_HI	include/ssv6200_aux.h	15884;"	d
+RG_DPD_020_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29184;"	d
+RG_DPD_020_PH_I_MSK	include/ssv6200_aux.h	15882;"	d
+RG_DPD_020_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29182;"	d
+RG_DPD_020_PH_MSK	include/ssv6200_aux.h	15881;"	d
+RG_DPD_020_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29181;"	d
+RG_DPD_020_PH_SFT	include/ssv6200_aux.h	15883;"	d
+RG_DPD_020_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29183;"	d
+RG_DPD_020_PH_SZ	include/ssv6200_aux.h	15885;"	d
+RG_DPD_020_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29185;"	d
+RG_DPD_040_GAIN_HI	include/ssv6200_aux.h	15759;"	d
+RG_DPD_040_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29059;"	d
+RG_DPD_040_GAIN_I_MSK	include/ssv6200_aux.h	15757;"	d
+RG_DPD_040_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29057;"	d
+RG_DPD_040_GAIN_MSK	include/ssv6200_aux.h	15756;"	d
+RG_DPD_040_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29056;"	d
+RG_DPD_040_GAIN_SFT	include/ssv6200_aux.h	15758;"	d
+RG_DPD_040_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29058;"	d
+RG_DPD_040_GAIN_SZ	include/ssv6200_aux.h	15760;"	d
+RG_DPD_040_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29060;"	d
+RG_DPD_040_PH_HI	include/ssv6200_aux.h	15889;"	d
+RG_DPD_040_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29189;"	d
+RG_DPD_040_PH_I_MSK	include/ssv6200_aux.h	15887;"	d
+RG_DPD_040_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29187;"	d
+RG_DPD_040_PH_MSK	include/ssv6200_aux.h	15886;"	d
+RG_DPD_040_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29186;"	d
+RG_DPD_040_PH_SFT	include/ssv6200_aux.h	15888;"	d
+RG_DPD_040_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29188;"	d
+RG_DPD_040_PH_SZ	include/ssv6200_aux.h	15890;"	d
+RG_DPD_040_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29190;"	d
+RG_DPD_060_GAIN_HI	include/ssv6200_aux.h	15764;"	d
+RG_DPD_060_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29064;"	d
+RG_DPD_060_GAIN_I_MSK	include/ssv6200_aux.h	15762;"	d
+RG_DPD_060_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29062;"	d
+RG_DPD_060_GAIN_MSK	include/ssv6200_aux.h	15761;"	d
+RG_DPD_060_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29061;"	d
+RG_DPD_060_GAIN_SFT	include/ssv6200_aux.h	15763;"	d
+RG_DPD_060_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29063;"	d
+RG_DPD_060_GAIN_SZ	include/ssv6200_aux.h	15765;"	d
+RG_DPD_060_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29065;"	d
+RG_DPD_060_PH_HI	include/ssv6200_aux.h	15894;"	d
+RG_DPD_060_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29194;"	d
+RG_DPD_060_PH_I_MSK	include/ssv6200_aux.h	15892;"	d
+RG_DPD_060_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29192;"	d
+RG_DPD_060_PH_MSK	include/ssv6200_aux.h	15891;"	d
+RG_DPD_060_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29191;"	d
+RG_DPD_060_PH_SFT	include/ssv6200_aux.h	15893;"	d
+RG_DPD_060_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29193;"	d
+RG_DPD_060_PH_SZ	include/ssv6200_aux.h	15895;"	d
+RG_DPD_060_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29195;"	d
+RG_DPD_080_GAIN_HI	include/ssv6200_aux.h	15769;"	d
+RG_DPD_080_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29069;"	d
+RG_DPD_080_GAIN_I_MSK	include/ssv6200_aux.h	15767;"	d
+RG_DPD_080_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29067;"	d
+RG_DPD_080_GAIN_MSK	include/ssv6200_aux.h	15766;"	d
+RG_DPD_080_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29066;"	d
+RG_DPD_080_GAIN_SFT	include/ssv6200_aux.h	15768;"	d
+RG_DPD_080_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29068;"	d
+RG_DPD_080_GAIN_SZ	include/ssv6200_aux.h	15770;"	d
+RG_DPD_080_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29070;"	d
+RG_DPD_080_PH_HI	include/ssv6200_aux.h	15899;"	d
+RG_DPD_080_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29199;"	d
+RG_DPD_080_PH_I_MSK	include/ssv6200_aux.h	15897;"	d
+RG_DPD_080_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29197;"	d
+RG_DPD_080_PH_MSK	include/ssv6200_aux.h	15896;"	d
+RG_DPD_080_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29196;"	d
+RG_DPD_080_PH_SFT	include/ssv6200_aux.h	15898;"	d
+RG_DPD_080_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29198;"	d
+RG_DPD_080_PH_SZ	include/ssv6200_aux.h	15900;"	d
+RG_DPD_080_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29200;"	d
+RG_DPD_0A0_GAIN_HI	include/ssv6200_aux.h	15774;"	d
+RG_DPD_0A0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29074;"	d
+RG_DPD_0A0_GAIN_I_MSK	include/ssv6200_aux.h	15772;"	d
+RG_DPD_0A0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29072;"	d
+RG_DPD_0A0_GAIN_MSK	include/ssv6200_aux.h	15771;"	d
+RG_DPD_0A0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29071;"	d
+RG_DPD_0A0_GAIN_SFT	include/ssv6200_aux.h	15773;"	d
+RG_DPD_0A0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29073;"	d
+RG_DPD_0A0_GAIN_SZ	include/ssv6200_aux.h	15775;"	d
+RG_DPD_0A0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29075;"	d
+RG_DPD_0A0_PH_HI	include/ssv6200_aux.h	15904;"	d
+RG_DPD_0A0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29204;"	d
+RG_DPD_0A0_PH_I_MSK	include/ssv6200_aux.h	15902;"	d
+RG_DPD_0A0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29202;"	d
+RG_DPD_0A0_PH_MSK	include/ssv6200_aux.h	15901;"	d
+RG_DPD_0A0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29201;"	d
+RG_DPD_0A0_PH_SFT	include/ssv6200_aux.h	15903;"	d
+RG_DPD_0A0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29203;"	d
+RG_DPD_0A0_PH_SZ	include/ssv6200_aux.h	15905;"	d
+RG_DPD_0A0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29205;"	d
+RG_DPD_0C0_GAIN_HI	include/ssv6200_aux.h	15779;"	d
+RG_DPD_0C0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29079;"	d
+RG_DPD_0C0_GAIN_I_MSK	include/ssv6200_aux.h	15777;"	d
+RG_DPD_0C0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29077;"	d
+RG_DPD_0C0_GAIN_MSK	include/ssv6200_aux.h	15776;"	d
+RG_DPD_0C0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29076;"	d
+RG_DPD_0C0_GAIN_SFT	include/ssv6200_aux.h	15778;"	d
+RG_DPD_0C0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29078;"	d
+RG_DPD_0C0_GAIN_SZ	include/ssv6200_aux.h	15780;"	d
+RG_DPD_0C0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29080;"	d
+RG_DPD_0C0_PH_HI	include/ssv6200_aux.h	15909;"	d
+RG_DPD_0C0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29209;"	d
+RG_DPD_0C0_PH_I_MSK	include/ssv6200_aux.h	15907;"	d
+RG_DPD_0C0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29207;"	d
+RG_DPD_0C0_PH_MSK	include/ssv6200_aux.h	15906;"	d
+RG_DPD_0C0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29206;"	d
+RG_DPD_0C0_PH_SFT	include/ssv6200_aux.h	15908;"	d
+RG_DPD_0C0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29208;"	d
+RG_DPD_0C0_PH_SZ	include/ssv6200_aux.h	15910;"	d
+RG_DPD_0C0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29210;"	d
+RG_DPD_0D0_GAIN_HI	include/ssv6200_aux.h	15784;"	d
+RG_DPD_0D0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29084;"	d
+RG_DPD_0D0_GAIN_I_MSK	include/ssv6200_aux.h	15782;"	d
+RG_DPD_0D0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29082;"	d
+RG_DPD_0D0_GAIN_MSK	include/ssv6200_aux.h	15781;"	d
+RG_DPD_0D0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29081;"	d
+RG_DPD_0D0_GAIN_SFT	include/ssv6200_aux.h	15783;"	d
+RG_DPD_0D0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29083;"	d
+RG_DPD_0D0_GAIN_SZ	include/ssv6200_aux.h	15785;"	d
+RG_DPD_0D0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29085;"	d
+RG_DPD_0D0_PH_HI	include/ssv6200_aux.h	15914;"	d
+RG_DPD_0D0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29214;"	d
+RG_DPD_0D0_PH_I_MSK	include/ssv6200_aux.h	15912;"	d
+RG_DPD_0D0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29212;"	d
+RG_DPD_0D0_PH_MSK	include/ssv6200_aux.h	15911;"	d
+RG_DPD_0D0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29211;"	d
+RG_DPD_0D0_PH_SFT	include/ssv6200_aux.h	15913;"	d
+RG_DPD_0D0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29213;"	d
+RG_DPD_0D0_PH_SZ	include/ssv6200_aux.h	15915;"	d
+RG_DPD_0D0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29215;"	d
+RG_DPD_0E0_GAIN_HI	include/ssv6200_aux.h	15789;"	d
+RG_DPD_0E0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29089;"	d
+RG_DPD_0E0_GAIN_I_MSK	include/ssv6200_aux.h	15787;"	d
+RG_DPD_0E0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29087;"	d
+RG_DPD_0E0_GAIN_MSK	include/ssv6200_aux.h	15786;"	d
+RG_DPD_0E0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29086;"	d
+RG_DPD_0E0_GAIN_SFT	include/ssv6200_aux.h	15788;"	d
+RG_DPD_0E0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29088;"	d
+RG_DPD_0E0_GAIN_SZ	include/ssv6200_aux.h	15790;"	d
+RG_DPD_0E0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29090;"	d
+RG_DPD_0E0_PH_HI	include/ssv6200_aux.h	15919;"	d
+RG_DPD_0E0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29219;"	d
+RG_DPD_0E0_PH_I_MSK	include/ssv6200_aux.h	15917;"	d
+RG_DPD_0E0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29217;"	d
+RG_DPD_0E0_PH_MSK	include/ssv6200_aux.h	15916;"	d
+RG_DPD_0E0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29216;"	d
+RG_DPD_0E0_PH_SFT	include/ssv6200_aux.h	15918;"	d
+RG_DPD_0E0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29218;"	d
+RG_DPD_0E0_PH_SZ	include/ssv6200_aux.h	15920;"	d
+RG_DPD_0E0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29220;"	d
+RG_DPD_0F0_GAIN_HI	include/ssv6200_aux.h	15794;"	d
+RG_DPD_0F0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29094;"	d
+RG_DPD_0F0_GAIN_I_MSK	include/ssv6200_aux.h	15792;"	d
+RG_DPD_0F0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29092;"	d
+RG_DPD_0F0_GAIN_MSK	include/ssv6200_aux.h	15791;"	d
+RG_DPD_0F0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29091;"	d
+RG_DPD_0F0_GAIN_SFT	include/ssv6200_aux.h	15793;"	d
+RG_DPD_0F0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29093;"	d
+RG_DPD_0F0_GAIN_SZ	include/ssv6200_aux.h	15795;"	d
+RG_DPD_0F0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29095;"	d
+RG_DPD_0F0_PH_HI	include/ssv6200_aux.h	15924;"	d
+RG_DPD_0F0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29224;"	d
+RG_DPD_0F0_PH_I_MSK	include/ssv6200_aux.h	15922;"	d
+RG_DPD_0F0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29222;"	d
+RG_DPD_0F0_PH_MSK	include/ssv6200_aux.h	15921;"	d
+RG_DPD_0F0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29221;"	d
+RG_DPD_0F0_PH_SFT	include/ssv6200_aux.h	15923;"	d
+RG_DPD_0F0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29223;"	d
+RG_DPD_0F0_PH_SZ	include/ssv6200_aux.h	15925;"	d
+RG_DPD_0F0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29225;"	d
+RG_DPD_100_GAIN_HI	include/ssv6200_aux.h	15799;"	d
+RG_DPD_100_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29099;"	d
+RG_DPD_100_GAIN_I_MSK	include/ssv6200_aux.h	15797;"	d
+RG_DPD_100_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29097;"	d
+RG_DPD_100_GAIN_MSK	include/ssv6200_aux.h	15796;"	d
+RG_DPD_100_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29096;"	d
+RG_DPD_100_GAIN_SFT	include/ssv6200_aux.h	15798;"	d
+RG_DPD_100_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29098;"	d
+RG_DPD_100_GAIN_SZ	include/ssv6200_aux.h	15800;"	d
+RG_DPD_100_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29100;"	d
+RG_DPD_100_PH_HI	include/ssv6200_aux.h	15929;"	d
+RG_DPD_100_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29229;"	d
+RG_DPD_100_PH_I_MSK	include/ssv6200_aux.h	15927;"	d
+RG_DPD_100_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29227;"	d
+RG_DPD_100_PH_MSK	include/ssv6200_aux.h	15926;"	d
+RG_DPD_100_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29226;"	d
+RG_DPD_100_PH_SFT	include/ssv6200_aux.h	15928;"	d
+RG_DPD_100_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29228;"	d
+RG_DPD_100_PH_SZ	include/ssv6200_aux.h	15930;"	d
+RG_DPD_100_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29230;"	d
+RG_DPD_110_GAIN_HI	include/ssv6200_aux.h	15804;"	d
+RG_DPD_110_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29104;"	d
+RG_DPD_110_GAIN_I_MSK	include/ssv6200_aux.h	15802;"	d
+RG_DPD_110_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29102;"	d
+RG_DPD_110_GAIN_MSK	include/ssv6200_aux.h	15801;"	d
+RG_DPD_110_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29101;"	d
+RG_DPD_110_GAIN_SFT	include/ssv6200_aux.h	15803;"	d
+RG_DPD_110_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29103;"	d
+RG_DPD_110_GAIN_SZ	include/ssv6200_aux.h	15805;"	d
+RG_DPD_110_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29105;"	d
+RG_DPD_110_PH_HI	include/ssv6200_aux.h	15934;"	d
+RG_DPD_110_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29234;"	d
+RG_DPD_110_PH_I_MSK	include/ssv6200_aux.h	15932;"	d
+RG_DPD_110_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29232;"	d
+RG_DPD_110_PH_MSK	include/ssv6200_aux.h	15931;"	d
+RG_DPD_110_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29231;"	d
+RG_DPD_110_PH_SFT	include/ssv6200_aux.h	15933;"	d
+RG_DPD_110_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29233;"	d
+RG_DPD_110_PH_SZ	include/ssv6200_aux.h	15935;"	d
+RG_DPD_110_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29235;"	d
+RG_DPD_120_GAIN_HI	include/ssv6200_aux.h	15809;"	d
+RG_DPD_120_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29109;"	d
+RG_DPD_120_GAIN_I_MSK	include/ssv6200_aux.h	15807;"	d
+RG_DPD_120_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29107;"	d
+RG_DPD_120_GAIN_MSK	include/ssv6200_aux.h	15806;"	d
+RG_DPD_120_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29106;"	d
+RG_DPD_120_GAIN_SFT	include/ssv6200_aux.h	15808;"	d
+RG_DPD_120_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29108;"	d
+RG_DPD_120_GAIN_SZ	include/ssv6200_aux.h	15810;"	d
+RG_DPD_120_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29110;"	d
+RG_DPD_120_PH_HI	include/ssv6200_aux.h	15939;"	d
+RG_DPD_120_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29239;"	d
+RG_DPD_120_PH_I_MSK	include/ssv6200_aux.h	15937;"	d
+RG_DPD_120_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29237;"	d
+RG_DPD_120_PH_MSK	include/ssv6200_aux.h	15936;"	d
+RG_DPD_120_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29236;"	d
+RG_DPD_120_PH_SFT	include/ssv6200_aux.h	15938;"	d
+RG_DPD_120_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29238;"	d
+RG_DPD_120_PH_SZ	include/ssv6200_aux.h	15940;"	d
+RG_DPD_120_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29240;"	d
+RG_DPD_130_GAIN_HI	include/ssv6200_aux.h	15814;"	d
+RG_DPD_130_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29114;"	d
+RG_DPD_130_GAIN_I_MSK	include/ssv6200_aux.h	15812;"	d
+RG_DPD_130_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29112;"	d
+RG_DPD_130_GAIN_MSK	include/ssv6200_aux.h	15811;"	d
+RG_DPD_130_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29111;"	d
+RG_DPD_130_GAIN_SFT	include/ssv6200_aux.h	15813;"	d
+RG_DPD_130_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29113;"	d
+RG_DPD_130_GAIN_SZ	include/ssv6200_aux.h	15815;"	d
+RG_DPD_130_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29115;"	d
+RG_DPD_130_PH_HI	include/ssv6200_aux.h	15944;"	d
+RG_DPD_130_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29244;"	d
+RG_DPD_130_PH_I_MSK	include/ssv6200_aux.h	15942;"	d
+RG_DPD_130_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29242;"	d
+RG_DPD_130_PH_MSK	include/ssv6200_aux.h	15941;"	d
+RG_DPD_130_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29241;"	d
+RG_DPD_130_PH_SFT	include/ssv6200_aux.h	15943;"	d
+RG_DPD_130_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29243;"	d
+RG_DPD_130_PH_SZ	include/ssv6200_aux.h	15945;"	d
+RG_DPD_130_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29245;"	d
+RG_DPD_140_GAIN_HI	include/ssv6200_aux.h	15819;"	d
+RG_DPD_140_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29119;"	d
+RG_DPD_140_GAIN_I_MSK	include/ssv6200_aux.h	15817;"	d
+RG_DPD_140_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29117;"	d
+RG_DPD_140_GAIN_MSK	include/ssv6200_aux.h	15816;"	d
+RG_DPD_140_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29116;"	d
+RG_DPD_140_GAIN_SFT	include/ssv6200_aux.h	15818;"	d
+RG_DPD_140_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29118;"	d
+RG_DPD_140_GAIN_SZ	include/ssv6200_aux.h	15820;"	d
+RG_DPD_140_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29120;"	d
+RG_DPD_140_PH_HI	include/ssv6200_aux.h	15949;"	d
+RG_DPD_140_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29249;"	d
+RG_DPD_140_PH_I_MSK	include/ssv6200_aux.h	15947;"	d
+RG_DPD_140_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29247;"	d
+RG_DPD_140_PH_MSK	include/ssv6200_aux.h	15946;"	d
+RG_DPD_140_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29246;"	d
+RG_DPD_140_PH_SFT	include/ssv6200_aux.h	15948;"	d
+RG_DPD_140_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29248;"	d
+RG_DPD_140_PH_SZ	include/ssv6200_aux.h	15950;"	d
+RG_DPD_140_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29250;"	d
+RG_DPD_150_GAIN_HI	include/ssv6200_aux.h	15824;"	d
+RG_DPD_150_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29124;"	d
+RG_DPD_150_GAIN_I_MSK	include/ssv6200_aux.h	15822;"	d
+RG_DPD_150_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29122;"	d
+RG_DPD_150_GAIN_MSK	include/ssv6200_aux.h	15821;"	d
+RG_DPD_150_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29121;"	d
+RG_DPD_150_GAIN_SFT	include/ssv6200_aux.h	15823;"	d
+RG_DPD_150_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29123;"	d
+RG_DPD_150_GAIN_SZ	include/ssv6200_aux.h	15825;"	d
+RG_DPD_150_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29125;"	d
+RG_DPD_150_PH_HI	include/ssv6200_aux.h	15954;"	d
+RG_DPD_150_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29254;"	d
+RG_DPD_150_PH_I_MSK	include/ssv6200_aux.h	15952;"	d
+RG_DPD_150_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29252;"	d
+RG_DPD_150_PH_MSK	include/ssv6200_aux.h	15951;"	d
+RG_DPD_150_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29251;"	d
+RG_DPD_150_PH_SFT	include/ssv6200_aux.h	15953;"	d
+RG_DPD_150_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29253;"	d
+RG_DPD_150_PH_SZ	include/ssv6200_aux.h	15955;"	d
+RG_DPD_150_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29255;"	d
+RG_DPD_160_GAIN_HI	include/ssv6200_aux.h	15829;"	d
+RG_DPD_160_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29129;"	d
+RG_DPD_160_GAIN_I_MSK	include/ssv6200_aux.h	15827;"	d
+RG_DPD_160_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29127;"	d
+RG_DPD_160_GAIN_MSK	include/ssv6200_aux.h	15826;"	d
+RG_DPD_160_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29126;"	d
+RG_DPD_160_GAIN_SFT	include/ssv6200_aux.h	15828;"	d
+RG_DPD_160_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29128;"	d
+RG_DPD_160_GAIN_SZ	include/ssv6200_aux.h	15830;"	d
+RG_DPD_160_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29130;"	d
+RG_DPD_160_PH_HI	include/ssv6200_aux.h	15959;"	d
+RG_DPD_160_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29259;"	d
+RG_DPD_160_PH_I_MSK	include/ssv6200_aux.h	15957;"	d
+RG_DPD_160_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29257;"	d
+RG_DPD_160_PH_MSK	include/ssv6200_aux.h	15956;"	d
+RG_DPD_160_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29256;"	d
+RG_DPD_160_PH_SFT	include/ssv6200_aux.h	15958;"	d
+RG_DPD_160_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29258;"	d
+RG_DPD_160_PH_SZ	include/ssv6200_aux.h	15960;"	d
+RG_DPD_160_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29260;"	d
+RG_DPD_170_GAIN_HI	include/ssv6200_aux.h	15834;"	d
+RG_DPD_170_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29134;"	d
+RG_DPD_170_GAIN_I_MSK	include/ssv6200_aux.h	15832;"	d
+RG_DPD_170_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29132;"	d
+RG_DPD_170_GAIN_MSK	include/ssv6200_aux.h	15831;"	d
+RG_DPD_170_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29131;"	d
+RG_DPD_170_GAIN_SFT	include/ssv6200_aux.h	15833;"	d
+RG_DPD_170_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29133;"	d
+RG_DPD_170_GAIN_SZ	include/ssv6200_aux.h	15835;"	d
+RG_DPD_170_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29135;"	d
+RG_DPD_170_PH_HI	include/ssv6200_aux.h	15964;"	d
+RG_DPD_170_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29264;"	d
+RG_DPD_170_PH_I_MSK	include/ssv6200_aux.h	15962;"	d
+RG_DPD_170_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29262;"	d
+RG_DPD_170_PH_MSK	include/ssv6200_aux.h	15961;"	d
+RG_DPD_170_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29261;"	d
+RG_DPD_170_PH_SFT	include/ssv6200_aux.h	15963;"	d
+RG_DPD_170_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29263;"	d
+RG_DPD_170_PH_SZ	include/ssv6200_aux.h	15965;"	d
+RG_DPD_170_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29265;"	d
+RG_DPD_180_GAIN_HI	include/ssv6200_aux.h	15839;"	d
+RG_DPD_180_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29139;"	d
+RG_DPD_180_GAIN_I_MSK	include/ssv6200_aux.h	15837;"	d
+RG_DPD_180_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29137;"	d
+RG_DPD_180_GAIN_MSK	include/ssv6200_aux.h	15836;"	d
+RG_DPD_180_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29136;"	d
+RG_DPD_180_GAIN_SFT	include/ssv6200_aux.h	15838;"	d
+RG_DPD_180_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29138;"	d
+RG_DPD_180_GAIN_SZ	include/ssv6200_aux.h	15840;"	d
+RG_DPD_180_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29140;"	d
+RG_DPD_180_PH_HI	include/ssv6200_aux.h	15969;"	d
+RG_DPD_180_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29269;"	d
+RG_DPD_180_PH_I_MSK	include/ssv6200_aux.h	15967;"	d
+RG_DPD_180_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29267;"	d
+RG_DPD_180_PH_MSK	include/ssv6200_aux.h	15966;"	d
+RG_DPD_180_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29266;"	d
+RG_DPD_180_PH_SFT	include/ssv6200_aux.h	15968;"	d
+RG_DPD_180_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29268;"	d
+RG_DPD_180_PH_SZ	include/ssv6200_aux.h	15970;"	d
+RG_DPD_180_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29270;"	d
+RG_DPD_190_GAIN_HI	include/ssv6200_aux.h	15844;"	d
+RG_DPD_190_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29144;"	d
+RG_DPD_190_GAIN_I_MSK	include/ssv6200_aux.h	15842;"	d
+RG_DPD_190_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29142;"	d
+RG_DPD_190_GAIN_MSK	include/ssv6200_aux.h	15841;"	d
+RG_DPD_190_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29141;"	d
+RG_DPD_190_GAIN_SFT	include/ssv6200_aux.h	15843;"	d
+RG_DPD_190_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29143;"	d
+RG_DPD_190_GAIN_SZ	include/ssv6200_aux.h	15845;"	d
+RG_DPD_190_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29145;"	d
+RG_DPD_190_PH_HI	include/ssv6200_aux.h	15974;"	d
+RG_DPD_190_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29274;"	d
+RG_DPD_190_PH_I_MSK	include/ssv6200_aux.h	15972;"	d
+RG_DPD_190_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29272;"	d
+RG_DPD_190_PH_MSK	include/ssv6200_aux.h	15971;"	d
+RG_DPD_190_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29271;"	d
+RG_DPD_190_PH_SFT	include/ssv6200_aux.h	15973;"	d
+RG_DPD_190_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29273;"	d
+RG_DPD_190_PH_SZ	include/ssv6200_aux.h	15975;"	d
+RG_DPD_190_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29275;"	d
+RG_DPD_1A0_GAIN_HI	include/ssv6200_aux.h	15849;"	d
+RG_DPD_1A0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29149;"	d
+RG_DPD_1A0_GAIN_I_MSK	include/ssv6200_aux.h	15847;"	d
+RG_DPD_1A0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29147;"	d
+RG_DPD_1A0_GAIN_MSK	include/ssv6200_aux.h	15846;"	d
+RG_DPD_1A0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29146;"	d
+RG_DPD_1A0_GAIN_SFT	include/ssv6200_aux.h	15848;"	d
+RG_DPD_1A0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29148;"	d
+RG_DPD_1A0_GAIN_SZ	include/ssv6200_aux.h	15850;"	d
+RG_DPD_1A0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29150;"	d
+RG_DPD_1A0_PH_HI	include/ssv6200_aux.h	15979;"	d
+RG_DPD_1A0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29279;"	d
+RG_DPD_1A0_PH_I_MSK	include/ssv6200_aux.h	15977;"	d
+RG_DPD_1A0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29277;"	d
+RG_DPD_1A0_PH_MSK	include/ssv6200_aux.h	15976;"	d
+RG_DPD_1A0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29276;"	d
+RG_DPD_1A0_PH_SFT	include/ssv6200_aux.h	15978;"	d
+RG_DPD_1A0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29278;"	d
+RG_DPD_1A0_PH_SZ	include/ssv6200_aux.h	15980;"	d
+RG_DPD_1A0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29280;"	d
+RG_DPD_1B0_GAIN_HI	include/ssv6200_aux.h	15854;"	d
+RG_DPD_1B0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29154;"	d
+RG_DPD_1B0_GAIN_I_MSK	include/ssv6200_aux.h	15852;"	d
+RG_DPD_1B0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29152;"	d
+RG_DPD_1B0_GAIN_MSK	include/ssv6200_aux.h	15851;"	d
+RG_DPD_1B0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29151;"	d
+RG_DPD_1B0_GAIN_SFT	include/ssv6200_aux.h	15853;"	d
+RG_DPD_1B0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29153;"	d
+RG_DPD_1B0_GAIN_SZ	include/ssv6200_aux.h	15855;"	d
+RG_DPD_1B0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29155;"	d
+RG_DPD_1B0_PH_HI	include/ssv6200_aux.h	15984;"	d
+RG_DPD_1B0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29284;"	d
+RG_DPD_1B0_PH_I_MSK	include/ssv6200_aux.h	15982;"	d
+RG_DPD_1B0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29282;"	d
+RG_DPD_1B0_PH_MSK	include/ssv6200_aux.h	15981;"	d
+RG_DPD_1B0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29281;"	d
+RG_DPD_1B0_PH_SFT	include/ssv6200_aux.h	15983;"	d
+RG_DPD_1B0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29283;"	d
+RG_DPD_1B0_PH_SZ	include/ssv6200_aux.h	15985;"	d
+RG_DPD_1B0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29285;"	d
+RG_DPD_1C0_GAIN_HI	include/ssv6200_aux.h	15859;"	d
+RG_DPD_1C0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29159;"	d
+RG_DPD_1C0_GAIN_I_MSK	include/ssv6200_aux.h	15857;"	d
+RG_DPD_1C0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29157;"	d
+RG_DPD_1C0_GAIN_MSK	include/ssv6200_aux.h	15856;"	d
+RG_DPD_1C0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29156;"	d
+RG_DPD_1C0_GAIN_SFT	include/ssv6200_aux.h	15858;"	d
+RG_DPD_1C0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29158;"	d
+RG_DPD_1C0_GAIN_SZ	include/ssv6200_aux.h	15860;"	d
+RG_DPD_1C0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29160;"	d
+RG_DPD_1C0_PH_HI	include/ssv6200_aux.h	15989;"	d
+RG_DPD_1C0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29289;"	d
+RG_DPD_1C0_PH_I_MSK	include/ssv6200_aux.h	15987;"	d
+RG_DPD_1C0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29287;"	d
+RG_DPD_1C0_PH_MSK	include/ssv6200_aux.h	15986;"	d
+RG_DPD_1C0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29286;"	d
+RG_DPD_1C0_PH_SFT	include/ssv6200_aux.h	15988;"	d
+RG_DPD_1C0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29288;"	d
+RG_DPD_1C0_PH_SZ	include/ssv6200_aux.h	15990;"	d
+RG_DPD_1C0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29290;"	d
+RG_DPD_1D0_GAIN_HI	include/ssv6200_aux.h	15864;"	d
+RG_DPD_1D0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29164;"	d
+RG_DPD_1D0_GAIN_I_MSK	include/ssv6200_aux.h	15862;"	d
+RG_DPD_1D0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29162;"	d
+RG_DPD_1D0_GAIN_MSK	include/ssv6200_aux.h	15861;"	d
+RG_DPD_1D0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29161;"	d
+RG_DPD_1D0_GAIN_SFT	include/ssv6200_aux.h	15863;"	d
+RG_DPD_1D0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29163;"	d
+RG_DPD_1D0_GAIN_SZ	include/ssv6200_aux.h	15865;"	d
+RG_DPD_1D0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29165;"	d
+RG_DPD_1D0_PH_HI	include/ssv6200_aux.h	15994;"	d
+RG_DPD_1D0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29294;"	d
+RG_DPD_1D0_PH_I_MSK	include/ssv6200_aux.h	15992;"	d
+RG_DPD_1D0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29292;"	d
+RG_DPD_1D0_PH_MSK	include/ssv6200_aux.h	15991;"	d
+RG_DPD_1D0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29291;"	d
+RG_DPD_1D0_PH_SFT	include/ssv6200_aux.h	15993;"	d
+RG_DPD_1D0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29293;"	d
+RG_DPD_1D0_PH_SZ	include/ssv6200_aux.h	15995;"	d
+RG_DPD_1D0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29295;"	d
+RG_DPD_1E0_GAIN_HI	include/ssv6200_aux.h	15869;"	d
+RG_DPD_1E0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29169;"	d
+RG_DPD_1E0_GAIN_I_MSK	include/ssv6200_aux.h	15867;"	d
+RG_DPD_1E0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29167;"	d
+RG_DPD_1E0_GAIN_MSK	include/ssv6200_aux.h	15866;"	d
+RG_DPD_1E0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29166;"	d
+RG_DPD_1E0_GAIN_SFT	include/ssv6200_aux.h	15868;"	d
+RG_DPD_1E0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29168;"	d
+RG_DPD_1E0_GAIN_SZ	include/ssv6200_aux.h	15870;"	d
+RG_DPD_1E0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29170;"	d
+RG_DPD_1E0_PH_HI	include/ssv6200_aux.h	15999;"	d
+RG_DPD_1E0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29299;"	d
+RG_DPD_1E0_PH_I_MSK	include/ssv6200_aux.h	15997;"	d
+RG_DPD_1E0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29297;"	d
+RG_DPD_1E0_PH_MSK	include/ssv6200_aux.h	15996;"	d
+RG_DPD_1E0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29296;"	d
+RG_DPD_1E0_PH_SFT	include/ssv6200_aux.h	15998;"	d
+RG_DPD_1E0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29298;"	d
+RG_DPD_1E0_PH_SZ	include/ssv6200_aux.h	16000;"	d
+RG_DPD_1E0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29300;"	d
+RG_DPD_1F0_GAIN_HI	include/ssv6200_aux.h	15874;"	d
+RG_DPD_1F0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29174;"	d
+RG_DPD_1F0_GAIN_I_MSK	include/ssv6200_aux.h	15872;"	d
+RG_DPD_1F0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29172;"	d
+RG_DPD_1F0_GAIN_MSK	include/ssv6200_aux.h	15871;"	d
+RG_DPD_1F0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29171;"	d
+RG_DPD_1F0_GAIN_SFT	include/ssv6200_aux.h	15873;"	d
+RG_DPD_1F0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29173;"	d
+RG_DPD_1F0_GAIN_SZ	include/ssv6200_aux.h	15875;"	d
+RG_DPD_1F0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29175;"	d
+RG_DPD_1F0_PH_HI	include/ssv6200_aux.h	16004;"	d
+RG_DPD_1F0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29304;"	d
+RG_DPD_1F0_PH_I_MSK	include/ssv6200_aux.h	16002;"	d
+RG_DPD_1F0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29302;"	d
+RG_DPD_1F0_PH_MSK	include/ssv6200_aux.h	16001;"	d
+RG_DPD_1F0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29301;"	d
+RG_DPD_1F0_PH_SFT	include/ssv6200_aux.h	16003;"	d
+RG_DPD_1F0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29303;"	d
+RG_DPD_1F0_PH_SZ	include/ssv6200_aux.h	16005;"	d
+RG_DPD_1F0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29305;"	d
+RG_DPD_200_GAIN_HI	include/ssv6200_aux.h	15879;"	d
+RG_DPD_200_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29179;"	d
+RG_DPD_200_GAIN_I_MSK	include/ssv6200_aux.h	15877;"	d
+RG_DPD_200_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29177;"	d
+RG_DPD_200_GAIN_MSK	include/ssv6200_aux.h	15876;"	d
+RG_DPD_200_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29176;"	d
+RG_DPD_200_GAIN_SFT	include/ssv6200_aux.h	15878;"	d
+RG_DPD_200_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29178;"	d
+RG_DPD_200_GAIN_SZ	include/ssv6200_aux.h	15880;"	d
+RG_DPD_200_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29180;"	d
+RG_DPD_200_PH_HI	include/ssv6200_aux.h	16009;"	d
+RG_DPD_200_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29309;"	d
+RG_DPD_200_PH_I_MSK	include/ssv6200_aux.h	16007;"	d
+RG_DPD_200_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29307;"	d
+RG_DPD_200_PH_MSK	include/ssv6200_aux.h	16006;"	d
+RG_DPD_200_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29306;"	d
+RG_DPD_200_PH_SFT	include/ssv6200_aux.h	16008;"	d
+RG_DPD_200_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29308;"	d
+RG_DPD_200_PH_SZ	include/ssv6200_aux.h	16010;"	d
+RG_DPD_200_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29310;"	d
+RG_DPD_5100_020_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27874;"	d
+RG_DPD_5100_020_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27872;"	d
+RG_DPD_5100_020_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27871;"	d
+RG_DPD_5100_020_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27873;"	d
+RG_DPD_5100_020_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27875;"	d
+RG_DPD_5100_020_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28004;"	d
+RG_DPD_5100_020_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28002;"	d
+RG_DPD_5100_020_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28001;"	d
+RG_DPD_5100_020_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28003;"	d
+RG_DPD_5100_020_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28005;"	d
+RG_DPD_5100_040_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27879;"	d
+RG_DPD_5100_040_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27877;"	d
+RG_DPD_5100_040_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27876;"	d
+RG_DPD_5100_040_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27878;"	d
+RG_DPD_5100_040_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27880;"	d
+RG_DPD_5100_040_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28009;"	d
+RG_DPD_5100_040_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28007;"	d
+RG_DPD_5100_040_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28006;"	d
+RG_DPD_5100_040_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28008;"	d
+RG_DPD_5100_040_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28010;"	d
+RG_DPD_5100_060_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27884;"	d
+RG_DPD_5100_060_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27882;"	d
+RG_DPD_5100_060_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27881;"	d
+RG_DPD_5100_060_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27883;"	d
+RG_DPD_5100_060_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27885;"	d
+RG_DPD_5100_060_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28014;"	d
+RG_DPD_5100_060_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28012;"	d
+RG_DPD_5100_060_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28011;"	d
+RG_DPD_5100_060_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28013;"	d
+RG_DPD_5100_060_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28015;"	d
+RG_DPD_5100_080_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27889;"	d
+RG_DPD_5100_080_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27887;"	d
+RG_DPD_5100_080_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27886;"	d
+RG_DPD_5100_080_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27888;"	d
+RG_DPD_5100_080_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27890;"	d
+RG_DPD_5100_080_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28019;"	d
+RG_DPD_5100_080_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28017;"	d
+RG_DPD_5100_080_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28016;"	d
+RG_DPD_5100_080_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28018;"	d
+RG_DPD_5100_080_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28020;"	d
+RG_DPD_5100_0A0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27894;"	d
+RG_DPD_5100_0A0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27892;"	d
+RG_DPD_5100_0A0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27891;"	d
+RG_DPD_5100_0A0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27893;"	d
+RG_DPD_5100_0A0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27895;"	d
+RG_DPD_5100_0A0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28024;"	d
+RG_DPD_5100_0A0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28022;"	d
+RG_DPD_5100_0A0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28021;"	d
+RG_DPD_5100_0A0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28023;"	d
+RG_DPD_5100_0A0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28025;"	d
+RG_DPD_5100_0C0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27899;"	d
+RG_DPD_5100_0C0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27897;"	d
+RG_DPD_5100_0C0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27896;"	d
+RG_DPD_5100_0C0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27898;"	d
+RG_DPD_5100_0C0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27900;"	d
+RG_DPD_5100_0C0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28029;"	d
+RG_DPD_5100_0C0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28027;"	d
+RG_DPD_5100_0C0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28026;"	d
+RG_DPD_5100_0C0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28028;"	d
+RG_DPD_5100_0C0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28030;"	d
+RG_DPD_5100_0D0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27904;"	d
+RG_DPD_5100_0D0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27902;"	d
+RG_DPD_5100_0D0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27901;"	d
+RG_DPD_5100_0D0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27903;"	d
+RG_DPD_5100_0D0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27905;"	d
+RG_DPD_5100_0D0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28034;"	d
+RG_DPD_5100_0D0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28032;"	d
+RG_DPD_5100_0D0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28031;"	d
+RG_DPD_5100_0D0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28033;"	d
+RG_DPD_5100_0D0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28035;"	d
+RG_DPD_5100_0E0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27909;"	d
+RG_DPD_5100_0E0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27907;"	d
+RG_DPD_5100_0E0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27906;"	d
+RG_DPD_5100_0E0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27908;"	d
+RG_DPD_5100_0E0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27910;"	d
+RG_DPD_5100_0E0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28039;"	d
+RG_DPD_5100_0E0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28037;"	d
+RG_DPD_5100_0E0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28036;"	d
+RG_DPD_5100_0E0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28038;"	d
+RG_DPD_5100_0E0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28040;"	d
+RG_DPD_5100_0F0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27914;"	d
+RG_DPD_5100_0F0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27912;"	d
+RG_DPD_5100_0F0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27911;"	d
+RG_DPD_5100_0F0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27913;"	d
+RG_DPD_5100_0F0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27915;"	d
+RG_DPD_5100_0F0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28044;"	d
+RG_DPD_5100_0F0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28042;"	d
+RG_DPD_5100_0F0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28041;"	d
+RG_DPD_5100_0F0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28043;"	d
+RG_DPD_5100_0F0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28045;"	d
+RG_DPD_5100_100_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27919;"	d
+RG_DPD_5100_100_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27917;"	d
+RG_DPD_5100_100_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27916;"	d
+RG_DPD_5100_100_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27918;"	d
+RG_DPD_5100_100_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27920;"	d
+RG_DPD_5100_100_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28049;"	d
+RG_DPD_5100_100_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28047;"	d
+RG_DPD_5100_100_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28046;"	d
+RG_DPD_5100_100_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28048;"	d
+RG_DPD_5100_100_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28050;"	d
+RG_DPD_5100_110_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27924;"	d
+RG_DPD_5100_110_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27922;"	d
+RG_DPD_5100_110_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27921;"	d
+RG_DPD_5100_110_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27923;"	d
+RG_DPD_5100_110_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27925;"	d
+RG_DPD_5100_110_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28054;"	d
+RG_DPD_5100_110_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28052;"	d
+RG_DPD_5100_110_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28051;"	d
+RG_DPD_5100_110_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28053;"	d
+RG_DPD_5100_110_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28055;"	d
+RG_DPD_5100_120_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27929;"	d
+RG_DPD_5100_120_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27927;"	d
+RG_DPD_5100_120_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27926;"	d
+RG_DPD_5100_120_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27928;"	d
+RG_DPD_5100_120_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27930;"	d
+RG_DPD_5100_120_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28059;"	d
+RG_DPD_5100_120_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28057;"	d
+RG_DPD_5100_120_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28056;"	d
+RG_DPD_5100_120_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28058;"	d
+RG_DPD_5100_120_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28060;"	d
+RG_DPD_5100_130_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27934;"	d
+RG_DPD_5100_130_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27932;"	d
+RG_DPD_5100_130_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27931;"	d
+RG_DPD_5100_130_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27933;"	d
+RG_DPD_5100_130_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27935;"	d
+RG_DPD_5100_130_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28064;"	d
+RG_DPD_5100_130_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28062;"	d
+RG_DPD_5100_130_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28061;"	d
+RG_DPD_5100_130_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28063;"	d
+RG_DPD_5100_130_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28065;"	d
+RG_DPD_5100_140_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27939;"	d
+RG_DPD_5100_140_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27937;"	d
+RG_DPD_5100_140_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27936;"	d
+RG_DPD_5100_140_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27938;"	d
+RG_DPD_5100_140_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27940;"	d
+RG_DPD_5100_140_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28069;"	d
+RG_DPD_5100_140_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28067;"	d
+RG_DPD_5100_140_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28066;"	d
+RG_DPD_5100_140_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28068;"	d
+RG_DPD_5100_140_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28070;"	d
+RG_DPD_5100_150_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27944;"	d
+RG_DPD_5100_150_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27942;"	d
+RG_DPD_5100_150_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27941;"	d
+RG_DPD_5100_150_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27943;"	d
+RG_DPD_5100_150_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27945;"	d
+RG_DPD_5100_150_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28074;"	d
+RG_DPD_5100_150_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28072;"	d
+RG_DPD_5100_150_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28071;"	d
+RG_DPD_5100_150_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28073;"	d
+RG_DPD_5100_150_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28075;"	d
+RG_DPD_5100_160_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27949;"	d
+RG_DPD_5100_160_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27947;"	d
+RG_DPD_5100_160_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27946;"	d
+RG_DPD_5100_160_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27948;"	d
+RG_DPD_5100_160_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27950;"	d
+RG_DPD_5100_160_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28079;"	d
+RG_DPD_5100_160_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28077;"	d
+RG_DPD_5100_160_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28076;"	d
+RG_DPD_5100_160_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28078;"	d
+RG_DPD_5100_160_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28080;"	d
+RG_DPD_5100_170_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27954;"	d
+RG_DPD_5100_170_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27952;"	d
+RG_DPD_5100_170_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27951;"	d
+RG_DPD_5100_170_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27953;"	d
+RG_DPD_5100_170_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27955;"	d
+RG_DPD_5100_170_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28084;"	d
+RG_DPD_5100_170_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28082;"	d
+RG_DPD_5100_170_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28081;"	d
+RG_DPD_5100_170_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28083;"	d
+RG_DPD_5100_170_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28085;"	d
+RG_DPD_5100_180_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27959;"	d
+RG_DPD_5100_180_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27957;"	d
+RG_DPD_5100_180_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27956;"	d
+RG_DPD_5100_180_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27958;"	d
+RG_DPD_5100_180_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27960;"	d
+RG_DPD_5100_180_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28089;"	d
+RG_DPD_5100_180_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28087;"	d
+RG_DPD_5100_180_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28086;"	d
+RG_DPD_5100_180_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28088;"	d
+RG_DPD_5100_180_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28090;"	d
+RG_DPD_5100_190_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27964;"	d
+RG_DPD_5100_190_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27962;"	d
+RG_DPD_5100_190_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27961;"	d
+RG_DPD_5100_190_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27963;"	d
+RG_DPD_5100_190_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27965;"	d
+RG_DPD_5100_190_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28094;"	d
+RG_DPD_5100_190_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28092;"	d
+RG_DPD_5100_190_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28091;"	d
+RG_DPD_5100_190_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28093;"	d
+RG_DPD_5100_190_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28095;"	d
+RG_DPD_5100_1A0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27969;"	d
+RG_DPD_5100_1A0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27967;"	d
+RG_DPD_5100_1A0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27966;"	d
+RG_DPD_5100_1A0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27968;"	d
+RG_DPD_5100_1A0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27970;"	d
+RG_DPD_5100_1A0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28099;"	d
+RG_DPD_5100_1A0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28097;"	d
+RG_DPD_5100_1A0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28096;"	d
+RG_DPD_5100_1A0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28098;"	d
+RG_DPD_5100_1A0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28100;"	d
+RG_DPD_5100_1B0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27974;"	d
+RG_DPD_5100_1B0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27972;"	d
+RG_DPD_5100_1B0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27971;"	d
+RG_DPD_5100_1B0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27973;"	d
+RG_DPD_5100_1B0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27975;"	d
+RG_DPD_5100_1B0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28104;"	d
+RG_DPD_5100_1B0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28102;"	d
+RG_DPD_5100_1B0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28101;"	d
+RG_DPD_5100_1B0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28103;"	d
+RG_DPD_5100_1B0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28105;"	d
+RG_DPD_5100_1C0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27979;"	d
+RG_DPD_5100_1C0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27977;"	d
+RG_DPD_5100_1C0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27976;"	d
+RG_DPD_5100_1C0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27978;"	d
+RG_DPD_5100_1C0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27980;"	d
+RG_DPD_5100_1C0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28109;"	d
+RG_DPD_5100_1C0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28107;"	d
+RG_DPD_5100_1C0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28106;"	d
+RG_DPD_5100_1C0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28108;"	d
+RG_DPD_5100_1C0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28110;"	d
+RG_DPD_5100_1D0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27984;"	d
+RG_DPD_5100_1D0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27982;"	d
+RG_DPD_5100_1D0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27981;"	d
+RG_DPD_5100_1D0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27983;"	d
+RG_DPD_5100_1D0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27985;"	d
+RG_DPD_5100_1D0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28114;"	d
+RG_DPD_5100_1D0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28112;"	d
+RG_DPD_5100_1D0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28111;"	d
+RG_DPD_5100_1D0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28113;"	d
+RG_DPD_5100_1D0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28115;"	d
+RG_DPD_5100_1E0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27989;"	d
+RG_DPD_5100_1E0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27987;"	d
+RG_DPD_5100_1E0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27986;"	d
+RG_DPD_5100_1E0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27988;"	d
+RG_DPD_5100_1E0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27990;"	d
+RG_DPD_5100_1E0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28119;"	d
+RG_DPD_5100_1E0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28117;"	d
+RG_DPD_5100_1E0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28116;"	d
+RG_DPD_5100_1E0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28118;"	d
+RG_DPD_5100_1E0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28120;"	d
+RG_DPD_5100_1F0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27994;"	d
+RG_DPD_5100_1F0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27992;"	d
+RG_DPD_5100_1F0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27991;"	d
+RG_DPD_5100_1F0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27993;"	d
+RG_DPD_5100_1F0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27995;"	d
+RG_DPD_5100_1F0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28124;"	d
+RG_DPD_5100_1F0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28122;"	d
+RG_DPD_5100_1F0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28121;"	d
+RG_DPD_5100_1F0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28123;"	d
+RG_DPD_5100_1F0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28125;"	d
+RG_DPD_5100_200_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27999;"	d
+RG_DPD_5100_200_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27997;"	d
+RG_DPD_5100_200_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27996;"	d
+RG_DPD_5100_200_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27998;"	d
+RG_DPD_5100_200_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28000;"	d
+RG_DPD_5100_200_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28129;"	d
+RG_DPD_5100_200_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28127;"	d
+RG_DPD_5100_200_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28126;"	d
+RG_DPD_5100_200_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28128;"	d
+RG_DPD_5100_200_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28130;"	d
+RG_DPD_5500_020_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28134;"	d
+RG_DPD_5500_020_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28132;"	d
+RG_DPD_5500_020_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28131;"	d
+RG_DPD_5500_020_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28133;"	d
+RG_DPD_5500_020_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28135;"	d
+RG_DPD_5500_020_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28264;"	d
+RG_DPD_5500_020_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28262;"	d
+RG_DPD_5500_020_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28261;"	d
+RG_DPD_5500_020_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28263;"	d
+RG_DPD_5500_020_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28265;"	d
+RG_DPD_5500_040_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28139;"	d
+RG_DPD_5500_040_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28137;"	d
+RG_DPD_5500_040_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28136;"	d
+RG_DPD_5500_040_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28138;"	d
+RG_DPD_5500_040_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28140;"	d
+RG_DPD_5500_040_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28269;"	d
+RG_DPD_5500_040_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28267;"	d
+RG_DPD_5500_040_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28266;"	d
+RG_DPD_5500_040_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28268;"	d
+RG_DPD_5500_040_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28270;"	d
+RG_DPD_5500_060_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28144;"	d
+RG_DPD_5500_060_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28142;"	d
+RG_DPD_5500_060_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28141;"	d
+RG_DPD_5500_060_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28143;"	d
+RG_DPD_5500_060_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28145;"	d
+RG_DPD_5500_060_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28274;"	d
+RG_DPD_5500_060_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28272;"	d
+RG_DPD_5500_060_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28271;"	d
+RG_DPD_5500_060_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28273;"	d
+RG_DPD_5500_060_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28275;"	d
+RG_DPD_5500_080_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28149;"	d
+RG_DPD_5500_080_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28147;"	d
+RG_DPD_5500_080_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28146;"	d
+RG_DPD_5500_080_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28148;"	d
+RG_DPD_5500_080_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28150;"	d
+RG_DPD_5500_080_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28279;"	d
+RG_DPD_5500_080_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28277;"	d
+RG_DPD_5500_080_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28276;"	d
+RG_DPD_5500_080_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28278;"	d
+RG_DPD_5500_080_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28280;"	d
+RG_DPD_5500_0A0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28154;"	d
+RG_DPD_5500_0A0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28152;"	d
+RG_DPD_5500_0A0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28151;"	d
+RG_DPD_5500_0A0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28153;"	d
+RG_DPD_5500_0A0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28155;"	d
+RG_DPD_5500_0A0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28284;"	d
+RG_DPD_5500_0A0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28282;"	d
+RG_DPD_5500_0A0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28281;"	d
+RG_DPD_5500_0A0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28283;"	d
+RG_DPD_5500_0A0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28285;"	d
+RG_DPD_5500_0C0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28159;"	d
+RG_DPD_5500_0C0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28157;"	d
+RG_DPD_5500_0C0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28156;"	d
+RG_DPD_5500_0C0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28158;"	d
+RG_DPD_5500_0C0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28160;"	d
+RG_DPD_5500_0C0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28289;"	d
+RG_DPD_5500_0C0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28287;"	d
+RG_DPD_5500_0C0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28286;"	d
+RG_DPD_5500_0C0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28288;"	d
+RG_DPD_5500_0C0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28290;"	d
+RG_DPD_5500_0D0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28164;"	d
+RG_DPD_5500_0D0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28162;"	d
+RG_DPD_5500_0D0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28161;"	d
+RG_DPD_5500_0D0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28163;"	d
+RG_DPD_5500_0D0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28165;"	d
+RG_DPD_5500_0D0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28294;"	d
+RG_DPD_5500_0D0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28292;"	d
+RG_DPD_5500_0D0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28291;"	d
+RG_DPD_5500_0D0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28293;"	d
+RG_DPD_5500_0D0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28295;"	d
+RG_DPD_5500_0E0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28169;"	d
+RG_DPD_5500_0E0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28167;"	d
+RG_DPD_5500_0E0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28166;"	d
+RG_DPD_5500_0E0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28168;"	d
+RG_DPD_5500_0E0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28170;"	d
+RG_DPD_5500_0E0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28299;"	d
+RG_DPD_5500_0E0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28297;"	d
+RG_DPD_5500_0E0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28296;"	d
+RG_DPD_5500_0E0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28298;"	d
+RG_DPD_5500_0E0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28300;"	d
+RG_DPD_5500_0F0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28174;"	d
+RG_DPD_5500_0F0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28172;"	d
+RG_DPD_5500_0F0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28171;"	d
+RG_DPD_5500_0F0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28173;"	d
+RG_DPD_5500_0F0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28175;"	d
+RG_DPD_5500_0F0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28304;"	d
+RG_DPD_5500_0F0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28302;"	d
+RG_DPD_5500_0F0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28301;"	d
+RG_DPD_5500_0F0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28303;"	d
+RG_DPD_5500_0F0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28305;"	d
+RG_DPD_5500_100_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28179;"	d
+RG_DPD_5500_100_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28177;"	d
+RG_DPD_5500_100_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28176;"	d
+RG_DPD_5500_100_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28178;"	d
+RG_DPD_5500_100_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28180;"	d
+RG_DPD_5500_100_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28309;"	d
+RG_DPD_5500_100_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28307;"	d
+RG_DPD_5500_100_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28306;"	d
+RG_DPD_5500_100_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28308;"	d
+RG_DPD_5500_100_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28310;"	d
+RG_DPD_5500_110_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28184;"	d
+RG_DPD_5500_110_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28182;"	d
+RG_DPD_5500_110_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28181;"	d
+RG_DPD_5500_110_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28183;"	d
+RG_DPD_5500_110_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28185;"	d
+RG_DPD_5500_110_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28314;"	d
+RG_DPD_5500_110_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28312;"	d
+RG_DPD_5500_110_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28311;"	d
+RG_DPD_5500_110_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28313;"	d
+RG_DPD_5500_110_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28315;"	d
+RG_DPD_5500_120_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28189;"	d
+RG_DPD_5500_120_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28187;"	d
+RG_DPD_5500_120_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28186;"	d
+RG_DPD_5500_120_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28188;"	d
+RG_DPD_5500_120_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28190;"	d
+RG_DPD_5500_120_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28319;"	d
+RG_DPD_5500_120_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28317;"	d
+RG_DPD_5500_120_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28316;"	d
+RG_DPD_5500_120_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28318;"	d
+RG_DPD_5500_120_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28320;"	d
+RG_DPD_5500_130_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28194;"	d
+RG_DPD_5500_130_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28192;"	d
+RG_DPD_5500_130_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28191;"	d
+RG_DPD_5500_130_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28193;"	d
+RG_DPD_5500_130_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28195;"	d
+RG_DPD_5500_130_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28324;"	d
+RG_DPD_5500_130_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28322;"	d
+RG_DPD_5500_130_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28321;"	d
+RG_DPD_5500_130_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28323;"	d
+RG_DPD_5500_130_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28325;"	d
+RG_DPD_5500_140_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28199;"	d
+RG_DPD_5500_140_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28197;"	d
+RG_DPD_5500_140_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28196;"	d
+RG_DPD_5500_140_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28198;"	d
+RG_DPD_5500_140_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28200;"	d
+RG_DPD_5500_140_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28329;"	d
+RG_DPD_5500_140_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28327;"	d
+RG_DPD_5500_140_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28326;"	d
+RG_DPD_5500_140_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28328;"	d
+RG_DPD_5500_140_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28330;"	d
+RG_DPD_5500_150_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28204;"	d
+RG_DPD_5500_150_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28202;"	d
+RG_DPD_5500_150_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28201;"	d
+RG_DPD_5500_150_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28203;"	d
+RG_DPD_5500_150_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28205;"	d
+RG_DPD_5500_150_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28334;"	d
+RG_DPD_5500_150_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28332;"	d
+RG_DPD_5500_150_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28331;"	d
+RG_DPD_5500_150_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28333;"	d
+RG_DPD_5500_150_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28335;"	d
+RG_DPD_5500_160_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28209;"	d
+RG_DPD_5500_160_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28207;"	d
+RG_DPD_5500_160_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28206;"	d
+RG_DPD_5500_160_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28208;"	d
+RG_DPD_5500_160_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28210;"	d
+RG_DPD_5500_160_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28339;"	d
+RG_DPD_5500_160_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28337;"	d
+RG_DPD_5500_160_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28336;"	d
+RG_DPD_5500_160_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28338;"	d
+RG_DPD_5500_160_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28340;"	d
+RG_DPD_5500_170_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28214;"	d
+RG_DPD_5500_170_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28212;"	d
+RG_DPD_5500_170_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28211;"	d
+RG_DPD_5500_170_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28213;"	d
+RG_DPD_5500_170_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28215;"	d
+RG_DPD_5500_170_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28344;"	d
+RG_DPD_5500_170_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28342;"	d
+RG_DPD_5500_170_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28341;"	d
+RG_DPD_5500_170_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28343;"	d
+RG_DPD_5500_170_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28345;"	d
+RG_DPD_5500_180_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28219;"	d
+RG_DPD_5500_180_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28217;"	d
+RG_DPD_5500_180_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28216;"	d
+RG_DPD_5500_180_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28218;"	d
+RG_DPD_5500_180_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28220;"	d
+RG_DPD_5500_180_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28349;"	d
+RG_DPD_5500_180_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28347;"	d
+RG_DPD_5500_180_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28346;"	d
+RG_DPD_5500_180_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28348;"	d
+RG_DPD_5500_180_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28350;"	d
+RG_DPD_5500_190_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28224;"	d
+RG_DPD_5500_190_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28222;"	d
+RG_DPD_5500_190_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28221;"	d
+RG_DPD_5500_190_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28223;"	d
+RG_DPD_5500_190_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28225;"	d
+RG_DPD_5500_190_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28354;"	d
+RG_DPD_5500_190_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28352;"	d
+RG_DPD_5500_190_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28351;"	d
+RG_DPD_5500_190_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28353;"	d
+RG_DPD_5500_190_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28355;"	d
+RG_DPD_5500_1A0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28229;"	d
+RG_DPD_5500_1A0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28227;"	d
+RG_DPD_5500_1A0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28226;"	d
+RG_DPD_5500_1A0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28228;"	d
+RG_DPD_5500_1A0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28230;"	d
+RG_DPD_5500_1A0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28359;"	d
+RG_DPD_5500_1A0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28357;"	d
+RG_DPD_5500_1A0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28356;"	d
+RG_DPD_5500_1A0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28358;"	d
+RG_DPD_5500_1A0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28360;"	d
+RG_DPD_5500_1B0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28234;"	d
+RG_DPD_5500_1B0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28232;"	d
+RG_DPD_5500_1B0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28231;"	d
+RG_DPD_5500_1B0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28233;"	d
+RG_DPD_5500_1B0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28235;"	d
+RG_DPD_5500_1B0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28364;"	d
+RG_DPD_5500_1B0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28362;"	d
+RG_DPD_5500_1B0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28361;"	d
+RG_DPD_5500_1B0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28363;"	d
+RG_DPD_5500_1B0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28365;"	d
+RG_DPD_5500_1C0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28239;"	d
+RG_DPD_5500_1C0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28237;"	d
+RG_DPD_5500_1C0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28236;"	d
+RG_DPD_5500_1C0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28238;"	d
+RG_DPD_5500_1C0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28240;"	d
+RG_DPD_5500_1C0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28369;"	d
+RG_DPD_5500_1C0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28367;"	d
+RG_DPD_5500_1C0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28366;"	d
+RG_DPD_5500_1C0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28368;"	d
+RG_DPD_5500_1C0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28370;"	d
+RG_DPD_5500_1D0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28244;"	d
+RG_DPD_5500_1D0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28242;"	d
+RG_DPD_5500_1D0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28241;"	d
+RG_DPD_5500_1D0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28243;"	d
+RG_DPD_5500_1D0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28245;"	d
+RG_DPD_5500_1D0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28374;"	d
+RG_DPD_5500_1D0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28372;"	d
+RG_DPD_5500_1D0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28371;"	d
+RG_DPD_5500_1D0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28373;"	d
+RG_DPD_5500_1D0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28375;"	d
+RG_DPD_5500_1E0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28249;"	d
+RG_DPD_5500_1E0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28247;"	d
+RG_DPD_5500_1E0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28246;"	d
+RG_DPD_5500_1E0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28248;"	d
+RG_DPD_5500_1E0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28250;"	d
+RG_DPD_5500_1E0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28379;"	d
+RG_DPD_5500_1E0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28377;"	d
+RG_DPD_5500_1E0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28376;"	d
+RG_DPD_5500_1E0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28378;"	d
+RG_DPD_5500_1E0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28380;"	d
+RG_DPD_5500_1F0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28254;"	d
+RG_DPD_5500_1F0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28252;"	d
+RG_DPD_5500_1F0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28251;"	d
+RG_DPD_5500_1F0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28253;"	d
+RG_DPD_5500_1F0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28255;"	d
+RG_DPD_5500_1F0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28384;"	d
+RG_DPD_5500_1F0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28382;"	d
+RG_DPD_5500_1F0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28381;"	d
+RG_DPD_5500_1F0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28383;"	d
+RG_DPD_5500_1F0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28385;"	d
+RG_DPD_5500_200_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28259;"	d
+RG_DPD_5500_200_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28257;"	d
+RG_DPD_5500_200_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28256;"	d
+RG_DPD_5500_200_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28258;"	d
+RG_DPD_5500_200_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28260;"	d
+RG_DPD_5500_200_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28389;"	d
+RG_DPD_5500_200_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28387;"	d
+RG_DPD_5500_200_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28386;"	d
+RG_DPD_5500_200_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28388;"	d
+RG_DPD_5500_200_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28390;"	d
+RG_DPD_5700_020_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28394;"	d
+RG_DPD_5700_020_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28392;"	d
+RG_DPD_5700_020_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28391;"	d
+RG_DPD_5700_020_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28393;"	d
+RG_DPD_5700_020_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28395;"	d
+RG_DPD_5700_020_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28524;"	d
+RG_DPD_5700_020_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28522;"	d
+RG_DPD_5700_020_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28521;"	d
+RG_DPD_5700_020_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28523;"	d
+RG_DPD_5700_020_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28525;"	d
+RG_DPD_5700_040_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28399;"	d
+RG_DPD_5700_040_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28397;"	d
+RG_DPD_5700_040_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28396;"	d
+RG_DPD_5700_040_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28398;"	d
+RG_DPD_5700_040_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28400;"	d
+RG_DPD_5700_040_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28529;"	d
+RG_DPD_5700_040_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28527;"	d
+RG_DPD_5700_040_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28526;"	d
+RG_DPD_5700_040_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28528;"	d
+RG_DPD_5700_040_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28530;"	d
+RG_DPD_5700_060_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28404;"	d
+RG_DPD_5700_060_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28402;"	d
+RG_DPD_5700_060_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28401;"	d
+RG_DPD_5700_060_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28403;"	d
+RG_DPD_5700_060_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28405;"	d
+RG_DPD_5700_060_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28534;"	d
+RG_DPD_5700_060_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28532;"	d
+RG_DPD_5700_060_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28531;"	d
+RG_DPD_5700_060_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28533;"	d
+RG_DPD_5700_060_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28535;"	d
+RG_DPD_5700_080_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28409;"	d
+RG_DPD_5700_080_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28407;"	d
+RG_DPD_5700_080_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28406;"	d
+RG_DPD_5700_080_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28408;"	d
+RG_DPD_5700_080_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28410;"	d
+RG_DPD_5700_080_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28539;"	d
+RG_DPD_5700_080_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28537;"	d
+RG_DPD_5700_080_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28536;"	d
+RG_DPD_5700_080_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28538;"	d
+RG_DPD_5700_080_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28540;"	d
+RG_DPD_5700_0A0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28414;"	d
+RG_DPD_5700_0A0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28412;"	d
+RG_DPD_5700_0A0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28411;"	d
+RG_DPD_5700_0A0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28413;"	d
+RG_DPD_5700_0A0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28415;"	d
+RG_DPD_5700_0A0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28544;"	d
+RG_DPD_5700_0A0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28542;"	d
+RG_DPD_5700_0A0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28541;"	d
+RG_DPD_5700_0A0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28543;"	d
+RG_DPD_5700_0A0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28545;"	d
+RG_DPD_5700_0C0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28419;"	d
+RG_DPD_5700_0C0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28417;"	d
+RG_DPD_5700_0C0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28416;"	d
+RG_DPD_5700_0C0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28418;"	d
+RG_DPD_5700_0C0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28420;"	d
+RG_DPD_5700_0C0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28549;"	d
+RG_DPD_5700_0C0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28547;"	d
+RG_DPD_5700_0C0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28546;"	d
+RG_DPD_5700_0C0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28548;"	d
+RG_DPD_5700_0C0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28550;"	d
+RG_DPD_5700_0D0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28424;"	d
+RG_DPD_5700_0D0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28422;"	d
+RG_DPD_5700_0D0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28421;"	d
+RG_DPD_5700_0D0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28423;"	d
+RG_DPD_5700_0D0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28425;"	d
+RG_DPD_5700_0D0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28554;"	d
+RG_DPD_5700_0D0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28552;"	d
+RG_DPD_5700_0D0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28551;"	d
+RG_DPD_5700_0D0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28553;"	d
+RG_DPD_5700_0D0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28555;"	d
+RG_DPD_5700_0E0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28429;"	d
+RG_DPD_5700_0E0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28427;"	d
+RG_DPD_5700_0E0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28426;"	d
+RG_DPD_5700_0E0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28428;"	d
+RG_DPD_5700_0E0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28430;"	d
+RG_DPD_5700_0E0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28559;"	d
+RG_DPD_5700_0E0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28557;"	d
+RG_DPD_5700_0E0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28556;"	d
+RG_DPD_5700_0E0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28558;"	d
+RG_DPD_5700_0E0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28560;"	d
+RG_DPD_5700_0F0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28434;"	d
+RG_DPD_5700_0F0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28432;"	d
+RG_DPD_5700_0F0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28431;"	d
+RG_DPD_5700_0F0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28433;"	d
+RG_DPD_5700_0F0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28435;"	d
+RG_DPD_5700_0F0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28564;"	d
+RG_DPD_5700_0F0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28562;"	d
+RG_DPD_5700_0F0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28561;"	d
+RG_DPD_5700_0F0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28563;"	d
+RG_DPD_5700_0F0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28565;"	d
+RG_DPD_5700_100_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28439;"	d
+RG_DPD_5700_100_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28437;"	d
+RG_DPD_5700_100_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28436;"	d
+RG_DPD_5700_100_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28438;"	d
+RG_DPD_5700_100_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28440;"	d
+RG_DPD_5700_100_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28569;"	d
+RG_DPD_5700_100_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28567;"	d
+RG_DPD_5700_100_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28566;"	d
+RG_DPD_5700_100_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28568;"	d
+RG_DPD_5700_100_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28570;"	d
+RG_DPD_5700_110_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28444;"	d
+RG_DPD_5700_110_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28442;"	d
+RG_DPD_5700_110_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28441;"	d
+RG_DPD_5700_110_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28443;"	d
+RG_DPD_5700_110_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28445;"	d
+RG_DPD_5700_110_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28574;"	d
+RG_DPD_5700_110_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28572;"	d
+RG_DPD_5700_110_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28571;"	d
+RG_DPD_5700_110_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28573;"	d
+RG_DPD_5700_110_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28575;"	d
+RG_DPD_5700_120_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28449;"	d
+RG_DPD_5700_120_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28447;"	d
+RG_DPD_5700_120_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28446;"	d
+RG_DPD_5700_120_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28448;"	d
+RG_DPD_5700_120_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28450;"	d
+RG_DPD_5700_120_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28579;"	d
+RG_DPD_5700_120_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28577;"	d
+RG_DPD_5700_120_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28576;"	d
+RG_DPD_5700_120_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28578;"	d
+RG_DPD_5700_120_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28580;"	d
+RG_DPD_5700_130_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28454;"	d
+RG_DPD_5700_130_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28452;"	d
+RG_DPD_5700_130_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28451;"	d
+RG_DPD_5700_130_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28453;"	d
+RG_DPD_5700_130_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28455;"	d
+RG_DPD_5700_130_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28584;"	d
+RG_DPD_5700_130_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28582;"	d
+RG_DPD_5700_130_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28581;"	d
+RG_DPD_5700_130_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28583;"	d
+RG_DPD_5700_130_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28585;"	d
+RG_DPD_5700_140_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28459;"	d
+RG_DPD_5700_140_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28457;"	d
+RG_DPD_5700_140_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28456;"	d
+RG_DPD_5700_140_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28458;"	d
+RG_DPD_5700_140_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28460;"	d
+RG_DPD_5700_140_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28589;"	d
+RG_DPD_5700_140_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28587;"	d
+RG_DPD_5700_140_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28586;"	d
+RG_DPD_5700_140_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28588;"	d
+RG_DPD_5700_140_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28590;"	d
+RG_DPD_5700_150_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28464;"	d
+RG_DPD_5700_150_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28462;"	d
+RG_DPD_5700_150_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28461;"	d
+RG_DPD_5700_150_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28463;"	d
+RG_DPD_5700_150_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28465;"	d
+RG_DPD_5700_150_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28594;"	d
+RG_DPD_5700_150_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28592;"	d
+RG_DPD_5700_150_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28591;"	d
+RG_DPD_5700_150_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28593;"	d
+RG_DPD_5700_150_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28595;"	d
+RG_DPD_5700_160_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28469;"	d
+RG_DPD_5700_160_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28467;"	d
+RG_DPD_5700_160_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28466;"	d
+RG_DPD_5700_160_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28468;"	d
+RG_DPD_5700_160_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28470;"	d
+RG_DPD_5700_160_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28599;"	d
+RG_DPD_5700_160_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28597;"	d
+RG_DPD_5700_160_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28596;"	d
+RG_DPD_5700_160_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28598;"	d
+RG_DPD_5700_160_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28600;"	d
+RG_DPD_5700_170_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28474;"	d
+RG_DPD_5700_170_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28472;"	d
+RG_DPD_5700_170_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28471;"	d
+RG_DPD_5700_170_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28473;"	d
+RG_DPD_5700_170_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28475;"	d
+RG_DPD_5700_170_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28604;"	d
+RG_DPD_5700_170_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28602;"	d
+RG_DPD_5700_170_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28601;"	d
+RG_DPD_5700_170_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28603;"	d
+RG_DPD_5700_170_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28605;"	d
+RG_DPD_5700_180_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28479;"	d
+RG_DPD_5700_180_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28477;"	d
+RG_DPD_5700_180_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28476;"	d
+RG_DPD_5700_180_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28478;"	d
+RG_DPD_5700_180_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28480;"	d
+RG_DPD_5700_180_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28609;"	d
+RG_DPD_5700_180_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28607;"	d
+RG_DPD_5700_180_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28606;"	d
+RG_DPD_5700_180_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28608;"	d
+RG_DPD_5700_180_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28610;"	d
+RG_DPD_5700_190_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28484;"	d
+RG_DPD_5700_190_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28482;"	d
+RG_DPD_5700_190_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28481;"	d
+RG_DPD_5700_190_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28483;"	d
+RG_DPD_5700_190_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28485;"	d
+RG_DPD_5700_190_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28614;"	d
+RG_DPD_5700_190_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28612;"	d
+RG_DPD_5700_190_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28611;"	d
+RG_DPD_5700_190_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28613;"	d
+RG_DPD_5700_190_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28615;"	d
+RG_DPD_5700_1A0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28489;"	d
+RG_DPD_5700_1A0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28487;"	d
+RG_DPD_5700_1A0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28486;"	d
+RG_DPD_5700_1A0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28488;"	d
+RG_DPD_5700_1A0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28490;"	d
+RG_DPD_5700_1A0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28619;"	d
+RG_DPD_5700_1A0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28617;"	d
+RG_DPD_5700_1A0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28616;"	d
+RG_DPD_5700_1A0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28618;"	d
+RG_DPD_5700_1A0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28620;"	d
+RG_DPD_5700_1B0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28494;"	d
+RG_DPD_5700_1B0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28492;"	d
+RG_DPD_5700_1B0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28491;"	d
+RG_DPD_5700_1B0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28493;"	d
+RG_DPD_5700_1B0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28495;"	d
+RG_DPD_5700_1B0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28624;"	d
+RG_DPD_5700_1B0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28622;"	d
+RG_DPD_5700_1B0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28621;"	d
+RG_DPD_5700_1B0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28623;"	d
+RG_DPD_5700_1B0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28625;"	d
+RG_DPD_5700_1C0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28499;"	d
+RG_DPD_5700_1C0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28497;"	d
+RG_DPD_5700_1C0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28496;"	d
+RG_DPD_5700_1C0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28498;"	d
+RG_DPD_5700_1C0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28500;"	d
+RG_DPD_5700_1C0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28629;"	d
+RG_DPD_5700_1C0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28627;"	d
+RG_DPD_5700_1C0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28626;"	d
+RG_DPD_5700_1C0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28628;"	d
+RG_DPD_5700_1C0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28630;"	d
+RG_DPD_5700_1D0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28504;"	d
+RG_DPD_5700_1D0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28502;"	d
+RG_DPD_5700_1D0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28501;"	d
+RG_DPD_5700_1D0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28503;"	d
+RG_DPD_5700_1D0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28505;"	d
+RG_DPD_5700_1D0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28634;"	d
+RG_DPD_5700_1D0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28632;"	d
+RG_DPD_5700_1D0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28631;"	d
+RG_DPD_5700_1D0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28633;"	d
+RG_DPD_5700_1D0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28635;"	d
+RG_DPD_5700_1E0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28509;"	d
+RG_DPD_5700_1E0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28507;"	d
+RG_DPD_5700_1E0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28506;"	d
+RG_DPD_5700_1E0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28508;"	d
+RG_DPD_5700_1E0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28510;"	d
+RG_DPD_5700_1E0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28639;"	d
+RG_DPD_5700_1E0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28637;"	d
+RG_DPD_5700_1E0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28636;"	d
+RG_DPD_5700_1E0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28638;"	d
+RG_DPD_5700_1E0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28640;"	d
+RG_DPD_5700_1F0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28514;"	d
+RG_DPD_5700_1F0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28512;"	d
+RG_DPD_5700_1F0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28511;"	d
+RG_DPD_5700_1F0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28513;"	d
+RG_DPD_5700_1F0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28515;"	d
+RG_DPD_5700_1F0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28644;"	d
+RG_DPD_5700_1F0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28642;"	d
+RG_DPD_5700_1F0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28641;"	d
+RG_DPD_5700_1F0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28643;"	d
+RG_DPD_5700_1F0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28645;"	d
+RG_DPD_5700_200_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28519;"	d
+RG_DPD_5700_200_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28517;"	d
+RG_DPD_5700_200_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28516;"	d
+RG_DPD_5700_200_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28518;"	d
+RG_DPD_5700_200_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28520;"	d
+RG_DPD_5700_200_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28649;"	d
+RG_DPD_5700_200_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28647;"	d
+RG_DPD_5700_200_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28646;"	d
+RG_DPD_5700_200_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28648;"	d
+RG_DPD_5700_200_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28650;"	d
+RG_DPD_5900_020_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28654;"	d
+RG_DPD_5900_020_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28652;"	d
+RG_DPD_5900_020_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28651;"	d
+RG_DPD_5900_020_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28653;"	d
+RG_DPD_5900_020_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28655;"	d
+RG_DPD_5900_020_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28784;"	d
+RG_DPD_5900_020_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28782;"	d
+RG_DPD_5900_020_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28781;"	d
+RG_DPD_5900_020_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28783;"	d
+RG_DPD_5900_020_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28785;"	d
+RG_DPD_5900_040_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28659;"	d
+RG_DPD_5900_040_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28657;"	d
+RG_DPD_5900_040_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28656;"	d
+RG_DPD_5900_040_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28658;"	d
+RG_DPD_5900_040_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28660;"	d
+RG_DPD_5900_040_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28789;"	d
+RG_DPD_5900_040_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28787;"	d
+RG_DPD_5900_040_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28786;"	d
+RG_DPD_5900_040_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28788;"	d
+RG_DPD_5900_040_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28790;"	d
+RG_DPD_5900_060_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28664;"	d
+RG_DPD_5900_060_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28662;"	d
+RG_DPD_5900_060_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28661;"	d
+RG_DPD_5900_060_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28663;"	d
+RG_DPD_5900_060_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28665;"	d
+RG_DPD_5900_060_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28794;"	d
+RG_DPD_5900_060_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28792;"	d
+RG_DPD_5900_060_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28791;"	d
+RG_DPD_5900_060_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28793;"	d
+RG_DPD_5900_060_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28795;"	d
+RG_DPD_5900_080_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28669;"	d
+RG_DPD_5900_080_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28667;"	d
+RG_DPD_5900_080_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28666;"	d
+RG_DPD_5900_080_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28668;"	d
+RG_DPD_5900_080_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28670;"	d
+RG_DPD_5900_080_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28799;"	d
+RG_DPD_5900_080_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28797;"	d
+RG_DPD_5900_080_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28796;"	d
+RG_DPD_5900_080_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28798;"	d
+RG_DPD_5900_080_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28800;"	d
+RG_DPD_5900_0A0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28674;"	d
+RG_DPD_5900_0A0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28672;"	d
+RG_DPD_5900_0A0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28671;"	d
+RG_DPD_5900_0A0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28673;"	d
+RG_DPD_5900_0A0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28675;"	d
+RG_DPD_5900_0A0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28804;"	d
+RG_DPD_5900_0A0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28802;"	d
+RG_DPD_5900_0A0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28801;"	d
+RG_DPD_5900_0A0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28803;"	d
+RG_DPD_5900_0A0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28805;"	d
+RG_DPD_5900_0C0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28679;"	d
+RG_DPD_5900_0C0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28677;"	d
+RG_DPD_5900_0C0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28676;"	d
+RG_DPD_5900_0C0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28678;"	d
+RG_DPD_5900_0C0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28680;"	d
+RG_DPD_5900_0C0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28809;"	d
+RG_DPD_5900_0C0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28807;"	d
+RG_DPD_5900_0C0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28806;"	d
+RG_DPD_5900_0C0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28808;"	d
+RG_DPD_5900_0C0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28810;"	d
+RG_DPD_5900_0D0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28684;"	d
+RG_DPD_5900_0D0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28682;"	d
+RG_DPD_5900_0D0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28681;"	d
+RG_DPD_5900_0D0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28683;"	d
+RG_DPD_5900_0D0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28685;"	d
+RG_DPD_5900_0D0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28814;"	d
+RG_DPD_5900_0D0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28812;"	d
+RG_DPD_5900_0D0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28811;"	d
+RG_DPD_5900_0D0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28813;"	d
+RG_DPD_5900_0D0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28815;"	d
+RG_DPD_5900_0E0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28689;"	d
+RG_DPD_5900_0E0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28687;"	d
+RG_DPD_5900_0E0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28686;"	d
+RG_DPD_5900_0E0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28688;"	d
+RG_DPD_5900_0E0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28690;"	d
+RG_DPD_5900_0E0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28819;"	d
+RG_DPD_5900_0E0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28817;"	d
+RG_DPD_5900_0E0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28816;"	d
+RG_DPD_5900_0E0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28818;"	d
+RG_DPD_5900_0E0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28820;"	d
+RG_DPD_5900_0F0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28694;"	d
+RG_DPD_5900_0F0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28692;"	d
+RG_DPD_5900_0F0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28691;"	d
+RG_DPD_5900_0F0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28693;"	d
+RG_DPD_5900_0F0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28695;"	d
+RG_DPD_5900_0F0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28824;"	d
+RG_DPD_5900_0F0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28822;"	d
+RG_DPD_5900_0F0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28821;"	d
+RG_DPD_5900_0F0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28823;"	d
+RG_DPD_5900_0F0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28825;"	d
+RG_DPD_5900_100_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28699;"	d
+RG_DPD_5900_100_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28697;"	d
+RG_DPD_5900_100_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28696;"	d
+RG_DPD_5900_100_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28698;"	d
+RG_DPD_5900_100_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28700;"	d
+RG_DPD_5900_100_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28829;"	d
+RG_DPD_5900_100_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28827;"	d
+RG_DPD_5900_100_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28826;"	d
+RG_DPD_5900_100_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28828;"	d
+RG_DPD_5900_100_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28830;"	d
+RG_DPD_5900_110_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28704;"	d
+RG_DPD_5900_110_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28702;"	d
+RG_DPD_5900_110_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28701;"	d
+RG_DPD_5900_110_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28703;"	d
+RG_DPD_5900_110_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28705;"	d
+RG_DPD_5900_110_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28834;"	d
+RG_DPD_5900_110_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28832;"	d
+RG_DPD_5900_110_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28831;"	d
+RG_DPD_5900_110_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28833;"	d
+RG_DPD_5900_110_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28835;"	d
+RG_DPD_5900_120_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28709;"	d
+RG_DPD_5900_120_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28707;"	d
+RG_DPD_5900_120_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28706;"	d
+RG_DPD_5900_120_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28708;"	d
+RG_DPD_5900_120_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28710;"	d
+RG_DPD_5900_120_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28839;"	d
+RG_DPD_5900_120_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28837;"	d
+RG_DPD_5900_120_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28836;"	d
+RG_DPD_5900_120_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28838;"	d
+RG_DPD_5900_120_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28840;"	d
+RG_DPD_5900_130_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28714;"	d
+RG_DPD_5900_130_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28712;"	d
+RG_DPD_5900_130_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28711;"	d
+RG_DPD_5900_130_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28713;"	d
+RG_DPD_5900_130_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28715;"	d
+RG_DPD_5900_130_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28844;"	d
+RG_DPD_5900_130_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28842;"	d
+RG_DPD_5900_130_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28841;"	d
+RG_DPD_5900_130_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28843;"	d
+RG_DPD_5900_130_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28845;"	d
+RG_DPD_5900_140_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28719;"	d
+RG_DPD_5900_140_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28717;"	d
+RG_DPD_5900_140_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28716;"	d
+RG_DPD_5900_140_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28718;"	d
+RG_DPD_5900_140_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28720;"	d
+RG_DPD_5900_140_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28849;"	d
+RG_DPD_5900_140_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28847;"	d
+RG_DPD_5900_140_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28846;"	d
+RG_DPD_5900_140_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28848;"	d
+RG_DPD_5900_140_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28850;"	d
+RG_DPD_5900_150_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28724;"	d
+RG_DPD_5900_150_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28722;"	d
+RG_DPD_5900_150_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28721;"	d
+RG_DPD_5900_150_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28723;"	d
+RG_DPD_5900_150_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28725;"	d
+RG_DPD_5900_150_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28854;"	d
+RG_DPD_5900_150_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28852;"	d
+RG_DPD_5900_150_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28851;"	d
+RG_DPD_5900_150_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28853;"	d
+RG_DPD_5900_150_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28855;"	d
+RG_DPD_5900_160_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28729;"	d
+RG_DPD_5900_160_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28727;"	d
+RG_DPD_5900_160_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28726;"	d
+RG_DPD_5900_160_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28728;"	d
+RG_DPD_5900_160_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28730;"	d
+RG_DPD_5900_160_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28859;"	d
+RG_DPD_5900_160_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28857;"	d
+RG_DPD_5900_160_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28856;"	d
+RG_DPD_5900_160_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28858;"	d
+RG_DPD_5900_160_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28860;"	d
+RG_DPD_5900_170_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28734;"	d
+RG_DPD_5900_170_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28732;"	d
+RG_DPD_5900_170_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28731;"	d
+RG_DPD_5900_170_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28733;"	d
+RG_DPD_5900_170_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28735;"	d
+RG_DPD_5900_170_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28864;"	d
+RG_DPD_5900_170_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28862;"	d
+RG_DPD_5900_170_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28861;"	d
+RG_DPD_5900_170_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28863;"	d
+RG_DPD_5900_170_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28865;"	d
+RG_DPD_5900_180_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28739;"	d
+RG_DPD_5900_180_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28737;"	d
+RG_DPD_5900_180_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28736;"	d
+RG_DPD_5900_180_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28738;"	d
+RG_DPD_5900_180_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28740;"	d
+RG_DPD_5900_180_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28869;"	d
+RG_DPD_5900_180_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28867;"	d
+RG_DPD_5900_180_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28866;"	d
+RG_DPD_5900_180_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28868;"	d
+RG_DPD_5900_180_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28870;"	d
+RG_DPD_5900_190_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28744;"	d
+RG_DPD_5900_190_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28742;"	d
+RG_DPD_5900_190_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28741;"	d
+RG_DPD_5900_190_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28743;"	d
+RG_DPD_5900_190_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28745;"	d
+RG_DPD_5900_190_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28874;"	d
+RG_DPD_5900_190_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28872;"	d
+RG_DPD_5900_190_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28871;"	d
+RG_DPD_5900_190_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28873;"	d
+RG_DPD_5900_190_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28875;"	d
+RG_DPD_5900_1A0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28749;"	d
+RG_DPD_5900_1A0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28747;"	d
+RG_DPD_5900_1A0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28746;"	d
+RG_DPD_5900_1A0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28748;"	d
+RG_DPD_5900_1A0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28750;"	d
+RG_DPD_5900_1A0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28879;"	d
+RG_DPD_5900_1A0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28877;"	d
+RG_DPD_5900_1A0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28876;"	d
+RG_DPD_5900_1A0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28878;"	d
+RG_DPD_5900_1A0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28880;"	d
+RG_DPD_5900_1B0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28754;"	d
+RG_DPD_5900_1B0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28752;"	d
+RG_DPD_5900_1B0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28751;"	d
+RG_DPD_5900_1B0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28753;"	d
+RG_DPD_5900_1B0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28755;"	d
+RG_DPD_5900_1B0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28884;"	d
+RG_DPD_5900_1B0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28882;"	d
+RG_DPD_5900_1B0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28881;"	d
+RG_DPD_5900_1B0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28883;"	d
+RG_DPD_5900_1B0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28885;"	d
+RG_DPD_5900_1C0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28759;"	d
+RG_DPD_5900_1C0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28757;"	d
+RG_DPD_5900_1C0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28756;"	d
+RG_DPD_5900_1C0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28758;"	d
+RG_DPD_5900_1C0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28760;"	d
+RG_DPD_5900_1C0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28889;"	d
+RG_DPD_5900_1C0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28887;"	d
+RG_DPD_5900_1C0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28886;"	d
+RG_DPD_5900_1C0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28888;"	d
+RG_DPD_5900_1C0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28890;"	d
+RG_DPD_5900_1D0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28764;"	d
+RG_DPD_5900_1D0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28762;"	d
+RG_DPD_5900_1D0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28761;"	d
+RG_DPD_5900_1D0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28763;"	d
+RG_DPD_5900_1D0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28765;"	d
+RG_DPD_5900_1D0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28894;"	d
+RG_DPD_5900_1D0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28892;"	d
+RG_DPD_5900_1D0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28891;"	d
+RG_DPD_5900_1D0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28893;"	d
+RG_DPD_5900_1D0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28895;"	d
+RG_DPD_5900_1E0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28769;"	d
+RG_DPD_5900_1E0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28767;"	d
+RG_DPD_5900_1E0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28766;"	d
+RG_DPD_5900_1E0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28768;"	d
+RG_DPD_5900_1E0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28770;"	d
+RG_DPD_5900_1E0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28899;"	d
+RG_DPD_5900_1E0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28897;"	d
+RG_DPD_5900_1E0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28896;"	d
+RG_DPD_5900_1E0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28898;"	d
+RG_DPD_5900_1E0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28900;"	d
+RG_DPD_5900_1F0_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28774;"	d
+RG_DPD_5900_1F0_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28772;"	d
+RG_DPD_5900_1F0_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28771;"	d
+RG_DPD_5900_1F0_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28773;"	d
+RG_DPD_5900_1F0_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28775;"	d
+RG_DPD_5900_1F0_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28904;"	d
+RG_DPD_5900_1F0_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28902;"	d
+RG_DPD_5900_1F0_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28901;"	d
+RG_DPD_5900_1F0_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28903;"	d
+RG_DPD_5900_1F0_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28905;"	d
+RG_DPD_5900_200_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28779;"	d
+RG_DPD_5900_200_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28777;"	d
+RG_DPD_5900_200_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28776;"	d
+RG_DPD_5900_200_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28778;"	d
+RG_DPD_5900_200_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28780;"	d
+RG_DPD_5900_200_PH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28909;"	d
+RG_DPD_5900_200_PH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28907;"	d
+RG_DPD_5900_200_PH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28906;"	d
+RG_DPD_5900_200_PH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28908;"	d
+RG_DPD_5900_200_PH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28910;"	d
+RG_DPD_AM_EN_HI	include/ssv6200_aux.h	15739;"	d
+RG_DPD_AM_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29039;"	d
+RG_DPD_AM_EN_I_MSK	include/ssv6200_aux.h	15737;"	d
+RG_DPD_AM_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29037;"	d
+RG_DPD_AM_EN_MSK	include/ssv6200_aux.h	15736;"	d
+RG_DPD_AM_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29036;"	d
+RG_DPD_AM_EN_SFT	include/ssv6200_aux.h	15738;"	d
+RG_DPD_AM_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29038;"	d
+RG_DPD_AM_EN_SZ	include/ssv6200_aux.h	15740;"	d
+RG_DPD_AM_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29040;"	d
+RG_DPD_BB_SCALE_2500_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29334;"	d
+RG_DPD_BB_SCALE_2500_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29332;"	d
+RG_DPD_BB_SCALE_2500_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29331;"	d
+RG_DPD_BB_SCALE_2500_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29333;"	d
+RG_DPD_BB_SCALE_2500_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29335;"	d
+RG_DPD_BB_SCALE_5100_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29329;"	d
+RG_DPD_BB_SCALE_5100_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29327;"	d
+RG_DPD_BB_SCALE_5100_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29326;"	d
+RG_DPD_BB_SCALE_5100_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29328;"	d
+RG_DPD_BB_SCALE_5100_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29330;"	d
+RG_DPD_BB_SCALE_5500_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29324;"	d
+RG_DPD_BB_SCALE_5500_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29322;"	d
+RG_DPD_BB_SCALE_5500_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29321;"	d
+RG_DPD_BB_SCALE_5500_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29323;"	d
+RG_DPD_BB_SCALE_5500_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29325;"	d
+RG_DPD_BB_SCALE_5700_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29319;"	d
+RG_DPD_BB_SCALE_5700_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29317;"	d
+RG_DPD_BB_SCALE_5700_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29316;"	d
+RG_DPD_BB_SCALE_5700_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29318;"	d
+RG_DPD_BB_SCALE_5700_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29320;"	d
+RG_DPD_BB_SCALE_5900_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29314;"	d
+RG_DPD_BB_SCALE_5900_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29312;"	d
+RG_DPD_BB_SCALE_5900_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29311;"	d
+RG_DPD_BB_SCALE_5900_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29313;"	d
+RG_DPD_BB_SCALE_5900_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29315;"	d
+RG_DPD_GAIN_EST_EN_HI	include/ssv6200_aux.h	15579;"	d
+RG_DPD_GAIN_EST_EN_I_MSK	include/ssv6200_aux.h	15577;"	d
+RG_DPD_GAIN_EST_EN_MSK	include/ssv6200_aux.h	15576;"	d
+RG_DPD_GAIN_EST_EN_SFT	include/ssv6200_aux.h	15578;"	d
+RG_DPD_GAIN_EST_EN_SZ	include/ssv6200_aux.h	15580;"	d
+RG_DPD_GAIN_EST_X0_HI	include/ssv6200_aux.h	16029;"	d
+RG_DPD_GAIN_EST_X0_I_MSK	include/ssv6200_aux.h	16027;"	d
+RG_DPD_GAIN_EST_X0_MSK	include/ssv6200_aux.h	16026;"	d
+RG_DPD_GAIN_EST_X0_SFT	include/ssv6200_aux.h	16028;"	d
+RG_DPD_GAIN_EST_X0_SZ	include/ssv6200_aux.h	16030;"	d
+RG_DPD_GAIN_EST_Y0_HI	include/ssv6200_aux.h	16014;"	d
+RG_DPD_GAIN_EST_Y0_I_MSK	include/ssv6200_aux.h	16012;"	d
+RG_DPD_GAIN_EST_Y0_MSK	include/ssv6200_aux.h	16011;"	d
+RG_DPD_GAIN_EST_Y0_SFT	include/ssv6200_aux.h	16013;"	d
+RG_DPD_GAIN_EST_Y0_SZ	include/ssv6200_aux.h	16015;"	d
+RG_DPD_GAIN_EST_Y1_HI	include/ssv6200_aux.h	16019;"	d
+RG_DPD_GAIN_EST_Y1_I_MSK	include/ssv6200_aux.h	16017;"	d
+RG_DPD_GAIN_EST_Y1_MSK	include/ssv6200_aux.h	16016;"	d
+RG_DPD_GAIN_EST_Y1_SFT	include/ssv6200_aux.h	16018;"	d
+RG_DPD_GAIN_EST_Y1_SZ	include/ssv6200_aux.h	16020;"	d
+RG_DPD_LOOP_GAIN_HI	include/ssv6200_aux.h	16024;"	d
+RG_DPD_LOOP_GAIN_I_MSK	include/ssv6200_aux.h	16022;"	d
+RG_DPD_LOOP_GAIN_MSK	include/ssv6200_aux.h	16021;"	d
+RG_DPD_LOOP_GAIN_SFT	include/ssv6200_aux.h	16023;"	d
+RG_DPD_LOOP_GAIN_SZ	include/ssv6200_aux.h	16025;"	d
+RG_DPD_PM_AMSEL_HI	include/ssv6200_aux.h	15749;"	d
+RG_DPD_PM_AMSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29049;"	d
+RG_DPD_PM_AMSEL_I_MSK	include/ssv6200_aux.h	15747;"	d
+RG_DPD_PM_AMSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29047;"	d
+RG_DPD_PM_AMSEL_MSK	include/ssv6200_aux.h	15746;"	d
+RG_DPD_PM_AMSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29046;"	d
+RG_DPD_PM_AMSEL_SFT	include/ssv6200_aux.h	15748;"	d
+RG_DPD_PM_AMSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29048;"	d
+RG_DPD_PM_AMSEL_SZ	include/ssv6200_aux.h	15750;"	d
+RG_DPD_PM_AMSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29050;"	d
+RG_DPD_PM_EN_HI	include/ssv6200_aux.h	15744;"	d
+RG_DPD_PM_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29044;"	d
+RG_DPD_PM_EN_I_MSK	include/ssv6200_aux.h	15742;"	d
+RG_DPD_PM_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29042;"	d
+RG_DPD_PM_EN_MSK	include/ssv6200_aux.h	15741;"	d
+RG_DPD_PM_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29041;"	d
+RG_DPD_PM_EN_SFT	include/ssv6200_aux.h	15743;"	d
+RG_DPD_PM_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29043;"	d
+RG_DPD_PM_EN_SZ	include/ssv6200_aux.h	15745;"	d
+RG_DPD_PM_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29045;"	d
+RG_DPLL_CLK320BY2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27299;"	d
+RG_DPLL_CLK320BY2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27297;"	d
+RG_DPLL_CLK320BY2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27296;"	d
+RG_DPLL_CLK320BY2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27298;"	d
+RG_DPLL_CLK320BY2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27300;"	d
+RG_DPL_MOD_ORDER_HI	include/ssv6200_aux.h	16979;"	d
+RG_DPL_MOD_ORDER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29964;"	d
+RG_DPL_MOD_ORDER_I_MSK	include/ssv6200_aux.h	16977;"	d
+RG_DPL_MOD_ORDER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29962;"	d
+RG_DPL_MOD_ORDER_MSK	include/ssv6200_aux.h	16976;"	d
+RG_DPL_MOD_ORDER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29961;"	d
+RG_DPL_MOD_ORDER_SFT	include/ssv6200_aux.h	16978;"	d
+RG_DPL_MOD_ORDER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29963;"	d
+RG_DPL_MOD_ORDER_SZ	include/ssv6200_aux.h	16980;"	d
+RG_DPL_MOD_ORDER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29965;"	d
+RG_DPL_RFCTRL_CH_HI	include/ssv6200_aux.h	17614;"	d
+RG_DPL_RFCTRL_CH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30064;"	d
+RG_DPL_RFCTRL_CH_I_MSK	include/ssv6200_aux.h	17612;"	d
+RG_DPL_RFCTRL_CH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30062;"	d
+RG_DPL_RFCTRL_CH_MSK	include/ssv6200_aux.h	17611;"	d
+RG_DPL_RFCTRL_CH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30061;"	d
+RG_DPL_RFCTRL_CH_SFT	include/ssv6200_aux.h	17613;"	d
+RG_DPL_RFCTRL_CH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30063;"	d
+RG_DPL_RFCTRL_CH_SZ	include/ssv6200_aux.h	17615;"	d
+RG_DPL_RFCTRL_CH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30065;"	d
+RG_DPL_RFCTRL_F_HI	include/ssv6200_aux.h	17634;"	d
+RG_DPL_RFCTRL_F_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30059;"	d
+RG_DPL_RFCTRL_F_I_MSK	include/ssv6200_aux.h	17632;"	d
+RG_DPL_RFCTRL_F_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30057;"	d
+RG_DPL_RFCTRL_F_MSK	include/ssv6200_aux.h	17631;"	d
+RG_DPL_RFCTRL_F_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30056;"	d
+RG_DPL_RFCTRL_F_SFT	include/ssv6200_aux.h	17633;"	d
+RG_DPL_RFCTRL_F_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30058;"	d
+RG_DPL_RFCTRL_F_SZ	include/ssv6200_aux.h	17635;"	d
+RG_DPL_RFCTRL_F_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30060;"	d
+RG_DPL_SETTLING_TIMMER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29584;"	d
+RG_DPL_SETTLING_TIMMER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29582;"	d
+RG_DPL_SETTLING_TIMMER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29581;"	d
+RG_DPL_SETTLING_TIMMER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29583;"	d
+RG_DPL_SETTLING_TIMMER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29585;"	d
+RG_DP_ADC320_DIVBY2_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29949;"	d
+RG_DP_ADC320_DIVBY2_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29947;"	d
+RG_DP_ADC320_DIVBY2_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29946;"	d
+RG_DP_ADC320_DIVBY2_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29948;"	d
+RG_DP_ADC320_DIVBY2_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29950;"	d
+RG_DP_ADC320_DIVBY2_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29954;"	d
+RG_DP_ADC320_DIVBY2_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29952;"	d
+RG_DP_ADC320_DIVBY2_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29951;"	d
+RG_DP_ADC320_DIVBY2_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29953;"	d
+RG_DP_ADC320_DIVBY2_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29955;"	d
+RG_DP_AUTOMAP_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29869;"	d
+RG_DP_AUTOMAP_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29867;"	d
+RG_DP_AUTOMAP_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29866;"	d
+RG_DP_AUTOMAP_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29868;"	d
+RG_DP_AUTOMAP_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29870;"	d
+RG_DP_BBPLL_BP_HI	include/ssv6200_aux.h	17249;"	d
+RG_DP_BBPLL_BP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29929;"	d
+RG_DP_BBPLL_BP_I_MSK	include/ssv6200_aux.h	17247;"	d
+RG_DP_BBPLL_BP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29927;"	d
+RG_DP_BBPLL_BP_MSK	include/ssv6200_aux.h	17246;"	d
+RG_DP_BBPLL_BP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29926;"	d
+RG_DP_BBPLL_BP_SFT	include/ssv6200_aux.h	17248;"	d
+RG_DP_BBPLL_BP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29928;"	d
+RG_DP_BBPLL_BP_SZ	include/ssv6200_aux.h	17250;"	d
+RG_DP_BBPLL_BP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29930;"	d
+RG_DP_BBPLL_BS_HI	include/ssv6200_aux.h	17329;"	d
+RG_DP_BBPLL_BS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30049;"	d
+RG_DP_BBPLL_BS_I_MSK	include/ssv6200_aux.h	17327;"	d
+RG_DP_BBPLL_BS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30047;"	d
+RG_DP_BBPLL_BS_MSK	include/ssv6200_aux.h	17326;"	d
+RG_DP_BBPLL_BS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30046;"	d
+RG_DP_BBPLL_BS_SFT	include/ssv6200_aux.h	17328;"	d
+RG_DP_BBPLL_BS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30048;"	d
+RG_DP_BBPLL_BS_SZ	include/ssv6200_aux.h	17330;"	d
+RG_DP_BBPLL_BS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30050;"	d
+RG_DP_BBPLL_ICP_HI	include/ssv6200_aux.h	17254;"	d
+RG_DP_BBPLL_ICP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29994;"	d
+RG_DP_BBPLL_ICP_I_MSK	include/ssv6200_aux.h	17252;"	d
+RG_DP_BBPLL_ICP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29992;"	d
+RG_DP_BBPLL_ICP_MSK	include/ssv6200_aux.h	17251;"	d
+RG_DP_BBPLL_ICP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29991;"	d
+RG_DP_BBPLL_ICP_SFT	include/ssv6200_aux.h	17253;"	d
+RG_DP_BBPLL_ICP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29993;"	d
+RG_DP_BBPLL_ICP_SZ	include/ssv6200_aux.h	17255;"	d
+RG_DP_BBPLL_ICP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29995;"	d
+RG_DP_BBPLL_IDUAL_HI	include/ssv6200_aux.h	17259;"	d
+RG_DP_BBPLL_IDUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29999;"	d
+RG_DP_BBPLL_IDUAL_I_MSK	include/ssv6200_aux.h	17257;"	d
+RG_DP_BBPLL_IDUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29997;"	d
+RG_DP_BBPLL_IDUAL_MSK	include/ssv6200_aux.h	17256;"	d
+RG_DP_BBPLL_IDUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29996;"	d
+RG_DP_BBPLL_IDUAL_SFT	include/ssv6200_aux.h	17258;"	d
+RG_DP_BBPLL_IDUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29998;"	d
+RG_DP_BBPLL_IDUAL_SZ	include/ssv6200_aux.h	17260;"	d
+RG_DP_BBPLL_IDUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30000;"	d
+RG_DP_BBPLL_OD_TEST_HI	include/ssv6200_aux.h	17264;"	d
+RG_DP_BBPLL_OD_TEST_I_MSK	include/ssv6200_aux.h	17262;"	d
+RG_DP_BBPLL_OD_TEST_MSK	include/ssv6200_aux.h	17261;"	d
+RG_DP_BBPLL_OD_TEST_SFT	include/ssv6200_aux.h	17263;"	d
+RG_DP_BBPLL_OD_TEST_SZ	include/ssv6200_aux.h	17265;"	d
+RG_DP_BBPLL_PD_HI	include/ssv6200_aux.h	17269;"	d
+RG_DP_BBPLL_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29924;"	d
+RG_DP_BBPLL_PD_I_MSK	include/ssv6200_aux.h	17267;"	d
+RG_DP_BBPLL_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29922;"	d
+RG_DP_BBPLL_PD_MSK	include/ssv6200_aux.h	17266;"	d
+RG_DP_BBPLL_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29921;"	d
+RG_DP_BBPLL_PD_SFT	include/ssv6200_aux.h	17268;"	d
+RG_DP_BBPLL_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29923;"	d
+RG_DP_BBPLL_PD_SZ	include/ssv6200_aux.h	17270;"	d
+RG_DP_BBPLL_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29925;"	d
+RG_DP_BBPLL_PFD_DLY_HI	include/ssv6200_aux.h	17279;"	d
+RG_DP_BBPLL_PFD_DLY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30019;"	d
+RG_DP_BBPLL_PFD_DLY_I_MSK	include/ssv6200_aux.h	17277;"	d
+RG_DP_BBPLL_PFD_DLY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30017;"	d
+RG_DP_BBPLL_PFD_DLY_MSK	include/ssv6200_aux.h	17276;"	d
+RG_DP_BBPLL_PFD_DLY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30016;"	d
+RG_DP_BBPLL_PFD_DLY_SFT	include/ssv6200_aux.h	17278;"	d
+RG_DP_BBPLL_PFD_DLY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30018;"	d
+RG_DP_BBPLL_PFD_DLY_SZ	include/ssv6200_aux.h	17280;"	d
+RG_DP_BBPLL_PFD_DLY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30020;"	d
+RG_DP_BBPLL_SDM_EDGE_HI	include/ssv6200_aux.h	17294;"	d
+RG_DP_BBPLL_SDM_EDGE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30054;"	d
+RG_DP_BBPLL_SDM_EDGE_I_MSK	include/ssv6200_aux.h	17292;"	d
+RG_DP_BBPLL_SDM_EDGE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30052;"	d
+RG_DP_BBPLL_SDM_EDGE_MSK	include/ssv6200_aux.h	17291;"	d
+RG_DP_BBPLL_SDM_EDGE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30051;"	d
+RG_DP_BBPLL_SDM_EDGE_SFT	include/ssv6200_aux.h	17293;"	d
+RG_DP_BBPLL_SDM_EDGE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30053;"	d
+RG_DP_BBPLL_SDM_EDGE_SZ	include/ssv6200_aux.h	17295;"	d
+RG_DP_BBPLL_SDM_EDGE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30055;"	d
+RG_DP_BBPLL_TESTSEL_HI	include/ssv6200_aux.h	17274;"	d
+RG_DP_BBPLL_TESTSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29989;"	d
+RG_DP_BBPLL_TESTSEL_I_MSK	include/ssv6200_aux.h	17272;"	d
+RG_DP_BBPLL_TESTSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29987;"	d
+RG_DP_BBPLL_TESTSEL_MSK	include/ssv6200_aux.h	17271;"	d
+RG_DP_BBPLL_TESTSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29986;"	d
+RG_DP_BBPLL_TESTSEL_SFT	include/ssv6200_aux.h	17273;"	d
+RG_DP_BBPLL_TESTSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29988;"	d
+RG_DP_BBPLL_TESTSEL_SZ	include/ssv6200_aux.h	17275;"	d
+RG_DP_BBPLL_TESTSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29990;"	d
+RG_DP_CK320BY2_HI	include/ssv6200_aux.h	17239;"	d
+RG_DP_CK320BY2_I_MSK	include/ssv6200_aux.h	17237;"	d
+RG_DP_CK320BY2_MSK	include/ssv6200_aux.h	17236;"	d
+RG_DP_CK320BY2_SFT	include/ssv6200_aux.h	17238;"	d
+RG_DP_CK320BY2_SZ	include/ssv6200_aux.h	17240;"	d
+RG_DP_CP_IOSTPOL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30004;"	d
+RG_DP_CP_IOSTPOL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30002;"	d
+RG_DP_CP_IOSTPOL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30001;"	d
+RG_DP_CP_IOSTPOL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30003;"	d
+RG_DP_CP_IOSTPOL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30005;"	d
+RG_DP_CP_IOST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30009;"	d
+RG_DP_CP_IOST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30007;"	d
+RG_DP_CP_IOST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30006;"	d
+RG_DP_CP_IOST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30008;"	d
+RG_DP_CP_IOST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30010;"	d
+RG_DP_DAC320_DIVBY2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29944;"	d
+RG_DP_DAC320_DIVBY2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29942;"	d
+RG_DP_DAC320_DIVBY2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29941;"	d
+RG_DP_DAC320_DIVBY2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29943;"	d
+RG_DP_DAC320_DIVBY2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29945;"	d
+RG_DP_FODIV_HI	include/ssv6200_aux.h	17299;"	d
+RG_DP_FODIV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29974;"	d
+RG_DP_FODIV_I_MSK	include/ssv6200_aux.h	17297;"	d
+RG_DP_FODIV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29972;"	d
+RG_DP_FODIV_MSK	include/ssv6200_aux.h	17296;"	d
+RG_DP_FODIV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29971;"	d
+RG_DP_FODIV_SFT	include/ssv6200_aux.h	17298;"	d
+RG_DP_FODIV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29973;"	d
+RG_DP_FODIV_SZ	include/ssv6200_aux.h	17300;"	d
+RG_DP_FODIV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29975;"	d
+RG_DP_FREF_DOUB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29939;"	d
+RG_DP_FREF_DOUB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29937;"	d
+RG_DP_FREF_DOUB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29936;"	d
+RG_DP_FREF_DOUB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29938;"	d
+RG_DP_FREF_DOUB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29940;"	d
+RG_DP_LDO_LEVEL_HI	include/ssv6200_aux.h	16314;"	d
+RG_DP_LDO_LEVEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29859;"	d
+RG_DP_LDO_LEVEL_I_MSK	include/ssv6200_aux.h	16312;"	d
+RG_DP_LDO_LEVEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29857;"	d
+RG_DP_LDO_LEVEL_MSK	include/ssv6200_aux.h	16311;"	d
+RG_DP_LDO_LEVEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29856;"	d
+RG_DP_LDO_LEVEL_SFT	include/ssv6200_aux.h	16313;"	d
+RG_DP_LDO_LEVEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29858;"	d
+RG_DP_LDO_LEVEL_SZ	include/ssv6200_aux.h	16315;"	d
+RG_DP_LDO_LEVEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29860;"	d
+RG_DP_OD_TEST_HI	include/ssv6200_aux.h	17244;"	d
+RG_DP_OD_TEST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29984;"	d
+RG_DP_OD_TEST_I_MSK	include/ssv6200_aux.h	17242;"	d
+RG_DP_OD_TEST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29982;"	d
+RG_DP_OD_TEST_MSK	include/ssv6200_aux.h	17241;"	d
+RG_DP_OD_TEST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29981;"	d
+RG_DP_OD_TEST_SFT	include/ssv6200_aux.h	17243;"	d
+RG_DP_OD_TEST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29983;"	d
+RG_DP_OD_TEST_SZ	include/ssv6200_aux.h	17245;"	d
+RG_DP_OD_TEST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29985;"	d
+RG_DP_PFD_PFDSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30014;"	d
+RG_DP_PFD_PFDSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30012;"	d
+RG_DP_PFD_PFDSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30011;"	d
+RG_DP_PFD_PFDSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30013;"	d
+RG_DP_PFD_PFDSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30015;"	d
+RG_DP_REFDIV_HI	include/ssv6200_aux.h	17304;"	d
+RG_DP_REFDIV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29969;"	d
+RG_DP_REFDIV_I_MSK	include/ssv6200_aux.h	17302;"	d
+RG_DP_REFDIV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29967;"	d
+RG_DP_REFDIV_MSK	include/ssv6200_aux.h	17301;"	d
+RG_DP_REFDIV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29966;"	d
+RG_DP_REFDIV_SFT	include/ssv6200_aux.h	17303;"	d
+RG_DP_REFDIV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29968;"	d
+RG_DP_REFDIV_SZ	include/ssv6200_aux.h	17305;"	d
+RG_DP_REFDIV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29970;"	d
+RG_DP_RHP_HI	include/ssv6200_aux.h	17289;"	d
+RG_DP_RHP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30029;"	d
+RG_DP_RHP_I_MSK	include/ssv6200_aux.h	17287;"	d
+RG_DP_RHP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30027;"	d
+RG_DP_RHP_MSK	include/ssv6200_aux.h	17286;"	d
+RG_DP_RHP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30026;"	d
+RG_DP_RHP_SFT	include/ssv6200_aux.h	17288;"	d
+RG_DP_RHP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30028;"	d
+RG_DP_RHP_SZ	include/ssv6200_aux.h	17290;"	d
+RG_DP_RHP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30030;"	d
+RG_DP_RP_HI	include/ssv6200_aux.h	17284;"	d
+RG_DP_RP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30024;"	d
+RG_DP_RP_I_MSK	include/ssv6200_aux.h	17282;"	d
+RG_DP_RP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30022;"	d
+RG_DP_RP_MSK	include/ssv6200_aux.h	17281;"	d
+RG_DP_RP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30021;"	d
+RG_DP_RP_SFT	include/ssv6200_aux.h	17283;"	d
+RG_DP_RP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30023;"	d
+RG_DP_RP_SZ	include/ssv6200_aux.h	17285;"	d
+RG_DP_RP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30025;"	d
+RG_DP_VT_TH_HI_HI	include/ssv6200_aux.h	17229;"	d
+RG_DP_VT_TH_HI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30039;"	d
+RG_DP_VT_TH_HI_I_MSK	include/ssv6200_aux.h	17227;"	d
+RG_DP_VT_TH_HI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30037;"	d
+RG_DP_VT_TH_HI_MSK	include/ssv6200_aux.h	17226;"	d
+RG_DP_VT_TH_HI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30036;"	d
+RG_DP_VT_TH_HI_SFT	include/ssv6200_aux.h	17228;"	d
+RG_DP_VT_TH_HI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30038;"	d
+RG_DP_VT_TH_HI_SZ	include/ssv6200_aux.h	17230;"	d
+RG_DP_VT_TH_HI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30040;"	d
+RG_DP_VT_TH_LO_HI	include/ssv6200_aux.h	17234;"	d
+RG_DP_VT_TH_LO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30044;"	d
+RG_DP_VT_TH_LO_I_MSK	include/ssv6200_aux.h	17232;"	d
+RG_DP_VT_TH_LO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30042;"	d
+RG_DP_VT_TH_LO_MSK	include/ssv6200_aux.h	17231;"	d
+RG_DP_VT_TH_LO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30041;"	d
+RG_DP_VT_TH_LO_SFT	include/ssv6200_aux.h	17233;"	d
+RG_DP_VT_TH_LO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30043;"	d
+RG_DP_VT_TH_LO_SZ	include/ssv6200_aux.h	17235;"	d
+RG_DP_VT_TH_LO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30045;"	d
+RG_DP_XTAL_FREQ_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29919;"	d
+RG_DP_XTAL_FREQ_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29917;"	d
+RG_DP_XTAL_FREQ_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29916;"	d
+RG_DP_XTAL_FREQ_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29918;"	d
+RG_DP_XTAL_FREQ_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29920;"	d
+RG_EDCCA_AVG_T_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30834;"	d
+RG_EDCCA_AVG_T_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30832;"	d
+RG_EDCCA_AVG_T_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30831;"	d
+RG_EDCCA_AVG_T_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30833;"	d
+RG_EDCCA_AVG_T_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30835;"	d
+RG_EDCCA_STAT_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30839;"	d
+RG_EDCCA_STAT_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30837;"	d
+RG_EDCCA_STAT_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30836;"	d
+RG_EDCCA_STAT_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30838;"	d
+RG_EDCCA_STAT_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30840;"	d
+RG_EN_AAC5GB_MXPDSW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26279;"	d
+RG_EN_AAC5GB_MXPDSW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26277;"	d
+RG_EN_AAC5GB_MXPDSW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26276;"	d
+RG_EN_AAC5GB_MXPDSW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26278;"	d
+RG_EN_AAC5GB_MXPDSW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26280;"	d
+RG_EN_AAC5GB_RPPDSW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26284;"	d
+RG_EN_AAC5GB_RPPDSW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26282;"	d
+RG_EN_AAC5GB_RPPDSW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26281;"	d
+RG_EN_AAC5GB_RPPDSW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26283;"	d
+RG_EN_AAC5GB_RPPDSW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26285;"	d
+RG_EN_AAC5GB_VOPDSW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26274;"	d
+RG_EN_AAC5GB_VOPDSW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26272;"	d
+RG_EN_AAC5GB_VOPDSW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26271;"	d
+RG_EN_AAC5GB_VOPDSW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26273;"	d
+RG_EN_AAC5GB_VOPDSW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26275;"	d
+RG_EN_ADC_320M_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29874;"	d
+RG_EN_ADC_320M_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29872;"	d
+RG_EN_ADC_320M_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29871;"	d
+RG_EN_ADC_320M_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29873;"	d
+RG_EN_ADC_320M_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29875;"	d
+RG_EN_ADC_HI	include/ssv6200_aux.h	16154;"	d
+RG_EN_ADC_I_MSK	include/ssv6200_aux.h	16152;"	d
+RG_EN_ADC_MSK	include/ssv6200_aux.h	16151;"	d
+RG_EN_ADC_SFT	include/ssv6200_aux.h	16153;"	d
+RG_EN_ADC_SZ	include/ssv6200_aux.h	16155;"	d
+RG_EN_CLK_960MBY13_UART_HI	include/ssv6200_aux.h	16189;"	d
+RG_EN_CLK_960MBY13_UART_I_MSK	include/ssv6200_aux.h	16187;"	d
+RG_EN_CLK_960MBY13_UART_MSK	include/ssv6200_aux.h	16186;"	d
+RG_EN_CLK_960MBY13_UART_SFT	include/ssv6200_aux.h	16188;"	d
+RG_EN_CLK_960MBY13_UART_SZ	include/ssv6200_aux.h	16190;"	d
+RG_EN_DLDO_BYP_AUTO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30099;"	d
+RG_EN_DLDO_BYP_AUTO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30097;"	d
+RG_EN_DLDO_BYP_AUTO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30096;"	d
+RG_EN_DLDO_BYP_AUTO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30098;"	d
+RG_EN_DLDO_BYP_AUTO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30100;"	d
+RG_EN_DLDO_BYP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29494;"	d
+RG_EN_DLDO_BYP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29492;"	d
+RG_EN_DLDO_BYP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29491;"	d
+RG_EN_DLDO_BYP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29493;"	d
+RG_EN_DLDO_BYP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29495;"	d
+RG_EN_DLDO_HALF_IQ_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29499;"	d
+RG_EN_DLDO_HALF_IQ_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29497;"	d
+RG_EN_DLDO_HALF_IQ_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29496;"	d
+RG_EN_DLDO_HALF_IQ_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29498;"	d
+RG_EN_DLDO_HALF_IQ_SLP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30094;"	d
+RG_EN_DLDO_HALF_IQ_SLP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30092;"	d
+RG_EN_DLDO_HALF_IQ_SLP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30091;"	d
+RG_EN_DLDO_HALF_IQ_SLP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30093;"	d
+RG_EN_DLDO_HALF_IQ_SLP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30095;"	d
+RG_EN_DLDO_HALF_IQ_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29500;"	d
+RG_EN_DPL_MOD_HI	include/ssv6200_aux.h	16974;"	d
+RG_EN_DPL_MOD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29959;"	d
+RG_EN_DPL_MOD_I_MSK	include/ssv6200_aux.h	16972;"	d
+RG_EN_DPL_MOD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29957;"	d
+RG_EN_DPL_MOD_MSK	include/ssv6200_aux.h	16971;"	d
+RG_EN_DPL_MOD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29956;"	d
+RG_EN_DPL_MOD_SFT	include/ssv6200_aux.h	16973;"	d
+RG_EN_DPL_MOD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29958;"	d
+RG_EN_DPL_MOD_SZ	include/ssv6200_aux.h	16975;"	d
+RG_EN_DPL_MOD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29960;"	d
+RG_EN_DP_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29934;"	d
+RG_EN_DP_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29932;"	d
+RG_EN_DP_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29931;"	d
+RG_EN_DP_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29933;"	d
+RG_EN_DP_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29935;"	d
+RG_EN_DP_VT_MON_HI	include/ssv6200_aux.h	17224;"	d
+RG_EN_DP_VT_MON_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30034;"	d
+RG_EN_DP_VT_MON_I_MSK	include/ssv6200_aux.h	17222;"	d
+RG_EN_DP_VT_MON_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30032;"	d
+RG_EN_DP_VT_MON_MSK	include/ssv6200_aux.h	17221;"	d
+RG_EN_DP_VT_MON_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30031;"	d
+RG_EN_DP_VT_MON_SFT	include/ssv6200_aux.h	17223;"	d
+RG_EN_DP_VT_MON_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30033;"	d
+RG_EN_DP_VT_MON_SZ	include/ssv6200_aux.h	17225;"	d
+RG_EN_DP_VT_MON_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30035;"	d
+RG_EN_FDB_DCC_MUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29539;"	d
+RG_EN_FDB_DCC_MUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29537;"	d
+RG_EN_FDB_DCC_MUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29536;"	d
+RG_EN_FDB_DCC_MUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29538;"	d
+RG_EN_FDB_DCC_MUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29540;"	d
+RG_EN_FDB_DELAYC_MUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29544;"	d
+RG_EN_FDB_DELAYC_MUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29542;"	d
+RG_EN_FDB_DELAYC_MUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29541;"	d
+RG_EN_FDB_DELAYC_MUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29543;"	d
+RG_EN_FDB_DELAYC_MUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29545;"	d
+RG_EN_FDB_DELAYF_MUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29549;"	d
+RG_EN_FDB_DELAYF_MUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29547;"	d
+RG_EN_FDB_DELAYF_MUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29546;"	d
+RG_EN_FDB_DELAYF_MUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29548;"	d
+RG_EN_FDB_DELAYF_MUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29550;"	d
+RG_EN_FDB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29514;"	d
+RG_EN_FDB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29512;"	d
+RG_EN_FDB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29511;"	d
+RG_EN_FDB_PHASESWAP_MUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29554;"	d
+RG_EN_FDB_PHASESWAP_MUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29552;"	d
+RG_EN_FDB_PHASESWAP_MUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29551;"	d
+RG_EN_FDB_PHASESWAP_MUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29553;"	d
+RG_EN_FDB_PHASESWAP_MUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29555;"	d
+RG_EN_FDB_RECAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29604;"	d
+RG_EN_FDB_RECAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29602;"	d
+RG_EN_FDB_RECAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29601;"	d
+RG_EN_FDB_RECAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29603;"	d
+RG_EN_FDB_RECAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29605;"	d
+RG_EN_FDB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29513;"	d
+RG_EN_FDB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29515;"	d
+RG_EN_HSDIV_OBF_MX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25704;"	d
+RG_EN_HSDIV_OBF_MX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25702;"	d
+RG_EN_HSDIV_OBF_MX_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25699;"	d
+RG_EN_HSDIV_OBF_MX_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25697;"	d
+RG_EN_HSDIV_OBF_MX_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25696;"	d
+RG_EN_HSDIV_OBF_MX_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25698;"	d
+RG_EN_HSDIV_OBF_MX_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25700;"	d
+RG_EN_HSDIV_OBF_MX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25701;"	d
+RG_EN_HSDIV_OBF_MX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25703;"	d
+RG_EN_HSDIV_OBF_MX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25705;"	d
+RG_EN_HSDIV_OBF_SX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25694;"	d
+RG_EN_HSDIV_OBF_SX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25692;"	d
+RG_EN_HSDIV_OBF_SX_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25689;"	d
+RG_EN_HSDIV_OBF_SX_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25687;"	d
+RG_EN_HSDIV_OBF_SX_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25686;"	d
+RG_EN_HSDIV_OBF_SX_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25688;"	d
+RG_EN_HSDIV_OBF_SX_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25690;"	d
+RG_EN_HSDIV_OBF_SX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25691;"	d
+RG_EN_HSDIV_OBF_SX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25693;"	d
+RG_EN_HSDIV_OBF_SX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25695;"	d
+RG_EN_IOTADC_160M_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29879;"	d
+RG_EN_IOTADC_160M_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29877;"	d
+RG_EN_IOTADC_160M_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29876;"	d
+RG_EN_IOTADC_160M_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29878;"	d
+RG_EN_IOTADC_160M_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29880;"	d
+RG_EN_IOT_ADC_BUF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21794;"	d
+RG_EN_IOT_ADC_BUF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21792;"	d
+RG_EN_IOT_ADC_BUF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21791;"	d
+RG_EN_IOT_ADC_BUF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21793;"	d
+RG_EN_IOT_ADC_BUF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21795;"	d
+RG_EN_IOT_ADC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21799;"	d
+RG_EN_IOT_ADC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21797;"	d
+RG_EN_IOT_ADC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21796;"	d
+RG_EN_IOT_ADC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21798;"	d
+RG_EN_IOT_ADC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21800;"	d
+RG_EN_IQPAD_IOSW_HI	include/ssv6200_aux.h	16269;"	d
+RG_EN_IQPAD_IOSW_I_MSK	include/ssv6200_aux.h	16267;"	d
+RG_EN_IQPAD_IOSW_MSK	include/ssv6200_aux.h	16266;"	d
+RG_EN_IQPAD_IOSW_SFT	include/ssv6200_aux.h	16268;"	d
+RG_EN_IQPAD_IOSW_SZ	include/ssv6200_aux.h	16270;"	d
+RG_EN_IREF_RX_HI	include/ssv6200_aux.h	16249;"	d
+RG_EN_IREF_RX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21814;"	d
+RG_EN_IREF_RX_I_MSK	include/ssv6200_aux.h	16247;"	d
+RG_EN_IREF_RX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21812;"	d
+RG_EN_IREF_RX_MSK	include/ssv6200_aux.h	16246;"	d
+RG_EN_IREF_RX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21811;"	d
+RG_EN_IREF_RX_SFT	include/ssv6200_aux.h	16248;"	d
+RG_EN_IREF_RX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21813;"	d
+RG_EN_IREF_RX_SZ	include/ssv6200_aux.h	16250;"	d
+RG_EN_IREF_RX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21815;"	d
+RG_EN_LDO_5G_CP_BYP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25029;"	d
+RG_EN_LDO_5G_CP_BYP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25027;"	d
+RG_EN_LDO_5G_CP_BYP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25026;"	d
+RG_EN_LDO_5G_CP_BYP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25028;"	d
+RG_EN_LDO_5G_CP_BYP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25030;"	d
+RG_EN_LDO_5G_CP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25774;"	d
+RG_EN_LDO_5G_CP_IQUP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25814;"	d
+RG_EN_LDO_5G_CP_IQUP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25812;"	d
+RG_EN_LDO_5G_CP_IQUP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25811;"	d
+RG_EN_LDO_5G_CP_IQUP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25813;"	d
+RG_EN_LDO_5G_CP_IQUP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25815;"	d
+RG_EN_LDO_5G_CP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25772;"	d
+RG_EN_LDO_5G_CP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25771;"	d
+RG_EN_LDO_5G_CP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25773;"	d
+RG_EN_LDO_5G_CP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25775;"	d
+RG_EN_LDO_5G_DIV_BYP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25054;"	d
+RG_EN_LDO_5G_DIV_BYP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25052;"	d
+RG_EN_LDO_5G_DIV_BYP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25051;"	d
+RG_EN_LDO_5G_DIV_BYP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25053;"	d
+RG_EN_LDO_5G_DIV_BYP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25055;"	d
+RG_EN_LDO_5G_DIV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25779;"	d
+RG_EN_LDO_5G_DIV_IQUP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25819;"	d
+RG_EN_LDO_5G_DIV_IQUP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25817;"	d
+RG_EN_LDO_5G_DIV_IQUP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25816;"	d
+RG_EN_LDO_5G_DIV_IQUP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25818;"	d
+RG_EN_LDO_5G_DIV_IQUP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25820;"	d
+RG_EN_LDO_5G_DIV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25777;"	d
+RG_EN_LDO_5G_DIV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25776;"	d
+RG_EN_LDO_5G_DIV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25778;"	d
+RG_EN_LDO_5G_DIV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25780;"	d
+RG_EN_LDO_5G_LO_BYP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25039;"	d
+RG_EN_LDO_5G_LO_BYP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25037;"	d
+RG_EN_LDO_5G_LO_BYP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25036;"	d
+RG_EN_LDO_5G_LO_BYP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25038;"	d
+RG_EN_LDO_5G_LO_BYP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25040;"	d
+RG_EN_LDO_5G_LO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25784;"	d
+RG_EN_LDO_5G_LO_IQUP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25824;"	d
+RG_EN_LDO_5G_LO_IQUP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25822;"	d
+RG_EN_LDO_5G_LO_IQUP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25821;"	d
+RG_EN_LDO_5G_LO_IQUP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25823;"	d
+RG_EN_LDO_5G_LO_IQUP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25825;"	d
+RG_EN_LDO_5G_LO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25782;"	d
+RG_EN_LDO_5G_LO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25781;"	d
+RG_EN_LDO_5G_LO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25783;"	d
+RG_EN_LDO_5G_LO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25785;"	d
+RG_EN_LDO_5G_VCO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25789;"	d
+RG_EN_LDO_5G_VCO_IQUP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25829;"	d
+RG_EN_LDO_5G_VCO_IQUP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25827;"	d
+RG_EN_LDO_5G_VCO_IQUP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25826;"	d
+RG_EN_LDO_5G_VCO_IQUP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25828;"	d
+RG_EN_LDO_5G_VCO_IQUP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25830;"	d
+RG_EN_LDO_5G_VCO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25787;"	d
+RG_EN_LDO_5G_VCO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25786;"	d
+RG_EN_LDO_5G_VCO_PSW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25804;"	d
+RG_EN_LDO_5G_VCO_PSW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25802;"	d
+RG_EN_LDO_5G_VCO_PSW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25801;"	d
+RG_EN_LDO_5G_VCO_PSW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25803;"	d
+RG_EN_LDO_5G_VCO_PSW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25805;"	d
+RG_EN_LDO_5G_VCO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25788;"	d
+RG_EN_LDO_5G_VCO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25790;"	d
+RG_EN_LDO_5G_VCO_VDD33_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25809;"	d
+RG_EN_LDO_5G_VCO_VDD33_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25807;"	d
+RG_EN_LDO_5G_VCO_VDD33_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25806;"	d
+RG_EN_LDO_5G_VCO_VDD33_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25808;"	d
+RG_EN_LDO_5G_VCO_VDD33_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25810;"	d
+RG_EN_LDO_ABB_HI	include/ssv6200_aux.h	16229;"	d
+RG_EN_LDO_ABB_I_MSK	include/ssv6200_aux.h	16227;"	d
+RG_EN_LDO_ABB_MSK	include/ssv6200_aux.h	16226;"	d
+RG_EN_LDO_ABB_SFT	include/ssv6200_aux.h	16228;"	d
+RG_EN_LDO_ABB_SZ	include/ssv6200_aux.h	16230;"	d
+RG_EN_LDO_AFE_HI	include/ssv6200_aux.h	16234;"	d
+RG_EN_LDO_AFE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21809;"	d
+RG_EN_LDO_AFE_I_MSK	include/ssv6200_aux.h	16232;"	d
+RG_EN_LDO_AFE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21807;"	d
+RG_EN_LDO_AFE_MSK	include/ssv6200_aux.h	16231;"	d
+RG_EN_LDO_AFE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21806;"	d
+RG_EN_LDO_AFE_SFT	include/ssv6200_aux.h	16233;"	d
+RG_EN_LDO_AFE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21808;"	d
+RG_EN_LDO_AFE_SZ	include/ssv6200_aux.h	16235;"	d
+RG_EN_LDO_AFE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21810;"	d
+RG_EN_LDO_CP_BYP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21969;"	d
+RG_EN_LDO_CP_BYP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21967;"	d
+RG_EN_LDO_CP_BYP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21966;"	d
+RG_EN_LDO_CP_BYP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21968;"	d
+RG_EN_LDO_CP_BYP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21970;"	d
+RG_EN_LDO_CP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23239;"	d
+RG_EN_LDO_CP_IQUP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23269;"	d
+RG_EN_LDO_CP_IQUP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23267;"	d
+RG_EN_LDO_CP_IQUP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23266;"	d
+RG_EN_LDO_CP_IQUP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23268;"	d
+RG_EN_LDO_CP_IQUP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23270;"	d
+RG_EN_LDO_CP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23237;"	d
+RG_EN_LDO_CP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23236;"	d
+RG_EN_LDO_CP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23238;"	d
+RG_EN_LDO_CP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23240;"	d
+RG_EN_LDO_DIV_BYP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21994;"	d
+RG_EN_LDO_DIV_BYP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21992;"	d
+RG_EN_LDO_DIV_BYP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21991;"	d
+RG_EN_LDO_DIV_BYP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21993;"	d
+RG_EN_LDO_DIV_BYP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21995;"	d
+RG_EN_LDO_DIV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23244;"	d
+RG_EN_LDO_DIV_IQUP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23274;"	d
+RG_EN_LDO_DIV_IQUP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23272;"	d
+RG_EN_LDO_DIV_IQUP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23271;"	d
+RG_EN_LDO_DIV_IQUP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23273;"	d
+RG_EN_LDO_DIV_IQUP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23275;"	d
+RG_EN_LDO_DIV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23242;"	d
+RG_EN_LDO_DIV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23241;"	d
+RG_EN_LDO_DIV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23243;"	d
+RG_EN_LDO_DIV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23245;"	d
+RG_EN_LDO_DP_BYP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29864;"	d
+RG_EN_LDO_DP_BYP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29862;"	d
+RG_EN_LDO_DP_BYP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29861;"	d
+RG_EN_LDO_DP_BYP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29863;"	d
+RG_EN_LDO_DP_BYP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29865;"	d
+RG_EN_LDO_DP_IQUP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29979;"	d
+RG_EN_LDO_DP_IQUP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29977;"	d
+RG_EN_LDO_DP_IQUP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29976;"	d
+RG_EN_LDO_DP_IQUP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29978;"	d
+RG_EN_LDO_DP_IQUP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29980;"	d
+RG_EN_LDO_EFUSE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29654;"	d
+RG_EN_LDO_EFUSE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29652;"	d
+RG_EN_LDO_EFUSE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29651;"	d
+RG_EN_LDO_EFUSE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29653;"	d
+RG_EN_LDO_EFUSE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29655;"	d
+RG_EN_LDO_LO_BYP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21979;"	d
+RG_EN_LDO_LO_BYP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21977;"	d
+RG_EN_LDO_LO_BYP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21976;"	d
+RG_EN_LDO_LO_BYP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21978;"	d
+RG_EN_LDO_LO_BYP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21980;"	d
+RG_EN_LDO_LO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23249;"	d
+RG_EN_LDO_LO_IQUP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23279;"	d
+RG_EN_LDO_LO_IQUP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23277;"	d
+RG_EN_LDO_LO_IQUP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23276;"	d
+RG_EN_LDO_LO_IQUP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23278;"	d
+RG_EN_LDO_LO_IQUP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23280;"	d
+RG_EN_LDO_LO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23247;"	d
+RG_EN_LDO_LO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23246;"	d
+RG_EN_LDO_LO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23248;"	d
+RG_EN_LDO_LO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23250;"	d
+RG_EN_LDO_RX_AFE_BYP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21959;"	d
+RG_EN_LDO_RX_AFE_BYP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21957;"	d
+RG_EN_LDO_RX_AFE_BYP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21956;"	d
+RG_EN_LDO_RX_AFE_BYP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21958;"	d
+RG_EN_LDO_RX_AFE_BYP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21960;"	d
+RG_EN_LDO_RX_AFE_FC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21924;"	d
+RG_EN_LDO_RX_AFE_FC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21922;"	d
+RG_EN_LDO_RX_AFE_FC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21921;"	d
+RG_EN_LDO_RX_AFE_FC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21923;"	d
+RG_EN_LDO_RX_AFE_FC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21925;"	d
+RG_EN_LDO_RX_AFE_IQUP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21934;"	d
+RG_EN_LDO_RX_AFE_IQUP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21932;"	d
+RG_EN_LDO_RX_AFE_IQUP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21931;"	d
+RG_EN_LDO_RX_AFE_IQUP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21933;"	d
+RG_EN_LDO_RX_AFE_IQUP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21935;"	d
+RG_EN_LDO_RX_FE_BYP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21949;"	d
+RG_EN_LDO_RX_FE_BYP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21947;"	d
+RG_EN_LDO_RX_FE_BYP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21946;"	d
+RG_EN_LDO_RX_FE_BYP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21948;"	d
+RG_EN_LDO_RX_FE_BYP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21950;"	d
+RG_EN_LDO_RX_FE_FC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21919;"	d
+RG_EN_LDO_RX_FE_FC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21917;"	d
+RG_EN_LDO_RX_FE_FC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21916;"	d
+RG_EN_LDO_RX_FE_FC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21918;"	d
+RG_EN_LDO_RX_FE_FC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21920;"	d
+RG_EN_LDO_RX_FE_HI	include/ssv6200_aux.h	16224;"	d
+RG_EN_LDO_RX_FE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21804;"	d
+RG_EN_LDO_RX_FE_IQUP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21929;"	d
+RG_EN_LDO_RX_FE_IQUP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21927;"	d
+RG_EN_LDO_RX_FE_IQUP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21926;"	d
+RG_EN_LDO_RX_FE_IQUP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21928;"	d
+RG_EN_LDO_RX_FE_IQUP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21930;"	d
+RG_EN_LDO_RX_FE_I_MSK	include/ssv6200_aux.h	16222;"	d
+RG_EN_LDO_RX_FE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21802;"	d
+RG_EN_LDO_RX_FE_MSK	include/ssv6200_aux.h	16221;"	d
+RG_EN_LDO_RX_FE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21801;"	d
+RG_EN_LDO_RX_FE_SFT	include/ssv6200_aux.h	16223;"	d
+RG_EN_LDO_RX_FE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21803;"	d
+RG_EN_LDO_RX_FE_SZ	include/ssv6200_aux.h	16225;"	d
+RG_EN_LDO_RX_FE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21805;"	d
+RG_EN_LDO_VCO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23254;"	d
+RG_EN_LDO_VCO_IQUP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23284;"	d
+RG_EN_LDO_VCO_IQUP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23282;"	d
+RG_EN_LDO_VCO_IQUP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23281;"	d
+RG_EN_LDO_VCO_IQUP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23283;"	d
+RG_EN_LDO_VCO_IQUP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23285;"	d
+RG_EN_LDO_VCO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23252;"	d
+RG_EN_LDO_VCO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23251;"	d
+RG_EN_LDO_VCO_PSW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23259;"	d
+RG_EN_LDO_VCO_PSW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23257;"	d
+RG_EN_LDO_VCO_PSW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23256;"	d
+RG_EN_LDO_VCO_PSW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23258;"	d
+RG_EN_LDO_VCO_PSW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23260;"	d
+RG_EN_LDO_VCO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23253;"	d
+RG_EN_LDO_VCO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23255;"	d
+RG_EN_LDO_VCO_VDD33_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23264;"	d
+RG_EN_LDO_VCO_VDD33_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23262;"	d
+RG_EN_LDO_VCO_VDD33_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23261;"	d
+RG_EN_LDO_VCO_VDD33_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23263;"	d
+RG_EN_LDO_VCO_VDD33_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23265;"	d
+RG_EN_LDO_XO_BYP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29489;"	d
+RG_EN_LDO_XO_BYP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29487;"	d
+RG_EN_LDO_XO_BYP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29486;"	d
+RG_EN_LDO_XO_BYP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29488;"	d
+RG_EN_LDO_XO_BYP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29490;"	d
+RG_EN_LDO_XO_IQUP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29484;"	d
+RG_EN_LDO_XO_IQUP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29482;"	d
+RG_EN_LDO_XO_IQUP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29481;"	d
+RG_EN_LDO_XO_IQUP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29483;"	d
+RG_EN_LDO_XO_IQUP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29485;"	d
+RG_EN_MAC_120M_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29894;"	d
+RG_EN_MAC_120M_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29892;"	d
+RG_EN_MAC_120M_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29891;"	d
+RG_EN_MAC_120M_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29893;"	d
+RG_EN_MAC_120M_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29895;"	d
+RG_EN_MAC_160M_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29914;"	d
+RG_EN_MAC_160M_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29912;"	d
+RG_EN_MAC_160M_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29911;"	d
+RG_EN_MAC_160M_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29913;"	d
+RG_EN_MAC_160M_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29915;"	d
+RG_EN_MAC_80M_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29884;"	d
+RG_EN_MAC_80M_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29882;"	d
+RG_EN_MAC_80M_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29881;"	d
+RG_EN_MAC_80M_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29883;"	d
+RG_EN_MAC_80M_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29885;"	d
+RG_EN_MAC_96M_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29889;"	d
+RG_EN_MAC_96M_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29887;"	d
+RG_EN_MAC_96M_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29886;"	d
+RG_EN_MAC_96M_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29888;"	d
+RG_EN_MAC_96M_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29890;"	d
+RG_EN_MANUAL_HI	include/ssv6200_aux.h	16059;"	d
+RG_EN_MANUAL_I_MSK	include/ssv6200_aux.h	16057;"	d
+RG_EN_MANUAL_MSK	include/ssv6200_aux.h	16056;"	d
+RG_EN_MANUAL_SFT	include/ssv6200_aux.h	16058;"	d
+RG_EN_MANUAL_SZ	include/ssv6200_aux.h	16060;"	d
+RG_EN_PHY_160M_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29904;"	d
+RG_EN_PHY_160M_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29902;"	d
+RG_EN_PHY_160M_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29901;"	d
+RG_EN_PHY_160M_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29903;"	d
+RG_EN_PHY_160M_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29905;"	d
+RG_EN_PHY_320M_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29909;"	d
+RG_EN_PHY_320M_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29907;"	d
+RG_EN_PHY_320M_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29906;"	d
+RG_EN_PHY_320M_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29908;"	d
+RG_EN_PHY_320M_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29910;"	d
+RG_EN_PHY_80M_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29899;"	d
+RG_EN_PHY_80M_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29897;"	d
+RG_EN_PHY_80M_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29896;"	d
+RG_EN_PHY_80M_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29898;"	d
+RG_EN_PHY_80M_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29900;"	d
+RG_EN_RCAL_HI	include/ssv6200_aux.h	17474;"	d
+RG_EN_RCAL_I_MSK	include/ssv6200_aux.h	17472;"	d
+RG_EN_RCAL_MSK	include/ssv6200_aux.h	17471;"	d
+RG_EN_RCAL_SFT	include/ssv6200_aux.h	17473;"	d
+RG_EN_RCAL_SZ	include/ssv6200_aux.h	17475;"	d
+RG_EN_RTC_CAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29729;"	d
+RG_EN_RTC_CAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29727;"	d
+RG_EN_RTC_CAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29726;"	d
+RG_EN_RTC_CAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29728;"	d
+RG_EN_RTC_CAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29730;"	d
+RG_EN_RX_ADC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21719;"	d
+RG_EN_RX_ADC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21717;"	d
+RG_EN_RX_ADC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21716;"	d
+RG_EN_RX_ADC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21718;"	d
+RG_EN_RX_ADC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21720;"	d
+RG_EN_RX_DIV2_HI	include/ssv6200_aux.h	16124;"	d
+RG_EN_RX_DIV2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21679;"	d
+RG_EN_RX_DIV2_I_MSK	include/ssv6200_aux.h	16122;"	d
+RG_EN_RX_DIV2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21677;"	d
+RG_EN_RX_DIV2_MSK	include/ssv6200_aux.h	16121;"	d
+RG_EN_RX_DIV2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21676;"	d
+RG_EN_RX_DIV2_SFT	include/ssv6200_aux.h	16123;"	d
+RG_EN_RX_DIV2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21678;"	d
+RG_EN_RX_DIV2_SZ	include/ssv6200_aux.h	16125;"	d
+RG_EN_RX_DIV2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21680;"	d
+RG_EN_RX_FILTER_HI	include/ssv6200_aux.h	16139;"	d
+RG_EN_RX_FILTER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21709;"	d
+RG_EN_RX_FILTER_I_MSK	include/ssv6200_aux.h	16137;"	d
+RG_EN_RX_FILTER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21707;"	d
+RG_EN_RX_FILTER_MSK	include/ssv6200_aux.h	16136;"	d
+RG_EN_RX_FILTER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21706;"	d
+RG_EN_RX_FILTER_SFT	include/ssv6200_aux.h	16138;"	d
+RG_EN_RX_FILTER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21708;"	d
+RG_EN_RX_FILTER_SZ	include/ssv6200_aux.h	16140;"	d
+RG_EN_RX_FILTER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21710;"	d
+RG_EN_RX_HPF_HI	include/ssv6200_aux.h	16144;"	d
+RG_EN_RX_HPF_I_MSK	include/ssv6200_aux.h	16142;"	d
+RG_EN_RX_HPF_MSK	include/ssv6200_aux.h	16141;"	d
+RG_EN_RX_HPF_SFT	include/ssv6200_aux.h	16143;"	d
+RG_EN_RX_HPF_SZ	include/ssv6200_aux.h	16145;"	d
+RG_EN_RX_IQCAL_HI	include/ssv6200_aux.h	16204;"	d
+RG_EN_RX_IQCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21854;"	d
+RG_EN_RX_IQCAL_I_MSK	include/ssv6200_aux.h	16202;"	d
+RG_EN_RX_IQCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21852;"	d
+RG_EN_RX_IQCAL_MSK	include/ssv6200_aux.h	16201;"	d
+RG_EN_RX_IQCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21851;"	d
+RG_EN_RX_IQCAL_SFT	include/ssv6200_aux.h	16203;"	d
+RG_EN_RX_IQCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21853;"	d
+RG_EN_RX_IQCAL_SZ	include/ssv6200_aux.h	16205;"	d
+RG_EN_RX_IQCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21855;"	d
+RG_EN_RX_LNA_HI	include/ssv6200_aux.h	16114;"	d
+RG_EN_RX_LNA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21659;"	d
+RG_EN_RX_LNA_I_MSK	include/ssv6200_aux.h	16112;"	d
+RG_EN_RX_LNA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21657;"	d
+RG_EN_RX_LNA_MSK	include/ssv6200_aux.h	16111;"	d
+RG_EN_RX_LNA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21656;"	d
+RG_EN_RX_LNA_SFT	include/ssv6200_aux.h	16113;"	d
+RG_EN_RX_LNA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21658;"	d
+RG_EN_RX_LNA_SZ	include/ssv6200_aux.h	16115;"	d
+RG_EN_RX_LNA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21660;"	d
+RG_EN_RX_LOBF_HI	include/ssv6200_aux.h	16179;"	d
+RG_EN_RX_LOBF_I_MSK	include/ssv6200_aux.h	16177;"	d
+RG_EN_RX_LOBF_MSK	include/ssv6200_aux.h	16176;"	d
+RG_EN_RX_LOBF_SFT	include/ssv6200_aux.h	16178;"	d
+RG_EN_RX_LOBF_SZ	include/ssv6200_aux.h	16180;"	d
+RG_EN_RX_LOBUF_HI	include/ssv6200_aux.h	16129;"	d
+RG_EN_RX_LOBUF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21689;"	d
+RG_EN_RX_LOBUF_I_MSK	include/ssv6200_aux.h	16127;"	d
+RG_EN_RX_LOBUF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21687;"	d
+RG_EN_RX_LOBUF_MSK	include/ssv6200_aux.h	16126;"	d
+RG_EN_RX_LOBUF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21686;"	d
+RG_EN_RX_LOBUF_SFT	include/ssv6200_aux.h	16128;"	d
+RG_EN_RX_LOBUF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21688;"	d
+RG_EN_RX_LOBUF_SZ	include/ssv6200_aux.h	16130;"	d
+RG_EN_RX_LOBUF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21690;"	d
+RG_EN_RX_MIXER_HI	include/ssv6200_aux.h	16119;"	d
+RG_EN_RX_MIXER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21669;"	d
+RG_EN_RX_MIXER_I_MSK	include/ssv6200_aux.h	16117;"	d
+RG_EN_RX_MIXER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21667;"	d
+RG_EN_RX_MIXER_MSK	include/ssv6200_aux.h	16116;"	d
+RG_EN_RX_MIXER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21666;"	d
+RG_EN_RX_MIXER_SFT	include/ssv6200_aux.h	16118;"	d
+RG_EN_RX_MIXER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21668;"	d
+RG_EN_RX_MIXER_SZ	include/ssv6200_aux.h	16120;"	d
+RG_EN_RX_MIXER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21670;"	d
+RG_EN_RX_PADSW_HI	include/ssv6200_aux.h	16329;"	d
+RG_EN_RX_PADSW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21914;"	d
+RG_EN_RX_PADSW_I_MSK	include/ssv6200_aux.h	16327;"	d
+RG_EN_RX_PADSW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21912;"	d
+RG_EN_RX_PADSW_MSK	include/ssv6200_aux.h	16326;"	d
+RG_EN_RX_PADSW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21911;"	d
+RG_EN_RX_PADSW_SFT	include/ssv6200_aux.h	16328;"	d
+RG_EN_RX_PADSW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21913;"	d
+RG_EN_RX_PADSW_SZ	include/ssv6200_aux.h	16330;"	d
+RG_EN_RX_PADSW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21915;"	d
+RG_EN_RX_RSSI_HI	include/ssv6200_aux.h	16149;"	d
+RG_EN_RX_RSSI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21729;"	d
+RG_EN_RX_RSSI_I_MSK	include/ssv6200_aux.h	16147;"	d
+RG_EN_RX_RSSI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21727;"	d
+RG_EN_RX_RSSI_MSK	include/ssv6200_aux.h	16146;"	d
+RG_EN_RX_RSSI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21726;"	d
+RG_EN_RX_RSSI_SFT	include/ssv6200_aux.h	16148;"	d
+RG_EN_RX_RSSI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21728;"	d
+RG_EN_RX_RSSI_SZ	include/ssv6200_aux.h	16150;"	d
+RG_EN_RX_RSSI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21730;"	d
+RG_EN_RX_RSSI_TESTNODE_HI	include/ssv6200_aux.h	16459;"	d
+RG_EN_RX_RSSI_TESTNODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22279;"	d
+RG_EN_RX_RSSI_TESTNODE_I_MSK	include/ssv6200_aux.h	16457;"	d
+RG_EN_RX_RSSI_TESTNODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22277;"	d
+RG_EN_RX_RSSI_TESTNODE_MSK	include/ssv6200_aux.h	16456;"	d
+RG_EN_RX_RSSI_TESTNODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22276;"	d
+RG_EN_RX_RSSI_TESTNODE_SFT	include/ssv6200_aux.h	16458;"	d
+RG_EN_RX_RSSI_TESTNODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22278;"	d
+RG_EN_RX_RSSI_TESTNODE_SZ	include/ssv6200_aux.h	16460;"	d
+RG_EN_RX_RSSI_TESTNODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22280;"	d
+RG_EN_RX_TESTNODE_HI	include/ssv6200_aux.h	16334;"	d
+RG_EN_RX_TESTNODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21909;"	d
+RG_EN_RX_TESTNODE_I_MSK	include/ssv6200_aux.h	16332;"	d
+RG_EN_RX_TESTNODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21907;"	d
+RG_EN_RX_TESTNODE_MSK	include/ssv6200_aux.h	16331;"	d
+RG_EN_RX_TESTNODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21906;"	d
+RG_EN_RX_TESTNODE_SFT	include/ssv6200_aux.h	16333;"	d
+RG_EN_RX_TESTNODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21908;"	d
+RG_EN_RX_TESTNODE_SZ	include/ssv6200_aux.h	16335;"	d
+RG_EN_RX_TESTNODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21910;"	d
+RG_EN_RX_TZ_HI	include/ssv6200_aux.h	16134;"	d
+RG_EN_RX_TZ_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21699;"	d
+RG_EN_RX_TZ_I_MSK	include/ssv6200_aux.h	16132;"	d
+RG_EN_RX_TZ_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21697;"	d
+RG_EN_RX_TZ_MSK	include/ssv6200_aux.h	16131;"	d
+RG_EN_RX_TZ_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21696;"	d
+RG_EN_RX_TZ_SFT	include/ssv6200_aux.h	16133;"	d
+RG_EN_RX_TZ_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21698;"	d
+RG_EN_RX_TZ_SZ	include/ssv6200_aux.h	16135;"	d
+RG_EN_RX_TZ_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21700;"	d
+RG_EN_SARADC_HI	include/ssv6200_aux.h	16839;"	d
+RG_EN_SARADC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21874;"	d
+RG_EN_SARADC_I_MSK	include/ssv6200_aux.h	16837;"	d
+RG_EN_SARADC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21872;"	d
+RG_EN_SARADC_MSK	include/ssv6200_aux.h	16836;"	d
+RG_EN_SARADC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21871;"	d
+RG_EN_SARADC_SFT	include/ssv6200_aux.h	16838;"	d
+RG_EN_SARADC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21873;"	d
+RG_EN_SARADC_SZ	include/ssv6200_aux.h	16840;"	d
+RG_EN_SARADC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21875;"	d
+RG_EN_SAR_TEST_HI	include/ssv6200_aux.h	16819;"	d
+RG_EN_SAR_TEST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22954;"	d
+RG_EN_SAR_TEST_I_MSK	include/ssv6200_aux.h	16817;"	d
+RG_EN_SAR_TEST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22952;"	d
+RG_EN_SAR_TEST_MSK	include/ssv6200_aux.h	16816;"	d
+RG_EN_SAR_TEST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22951;"	d
+RG_EN_SAR_TEST_SFT	include/ssv6200_aux.h	16818;"	d
+RG_EN_SAR_TEST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22953;"	d
+RG_EN_SAR_TEST_SZ	include/ssv6200_aux.h	16820;"	d
+RG_EN_SAR_TEST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22955;"	d
+RG_EN_SRVC_HI	include/ssv6200_aux.h	14289;"	d
+RG_EN_SRVC_I_MSK	include/ssv6200_aux.h	14287;"	d
+RG_EN_SRVC_MSK	include/ssv6200_aux.h	14286;"	d
+RG_EN_SRVC_SFT	include/ssv6200_aux.h	14288;"	d
+RG_EN_SRVC_SZ	include/ssv6200_aux.h	14290;"	d
+RG_EN_SX5GB_CP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25634;"	d
+RG_EN_SX5GB_CP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25632;"	d
+RG_EN_SX5GB_CP_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25629;"	d
+RG_EN_SX5GB_CP_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25627;"	d
+RG_EN_SX5GB_CP_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25626;"	d
+RG_EN_SX5GB_CP_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25628;"	d
+RG_EN_SX5GB_CP_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25630;"	d
+RG_EN_SX5GB_CP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25631;"	d
+RG_EN_SX5GB_CP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25633;"	d
+RG_EN_SX5GB_CP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25635;"	d
+RG_EN_SX5GB_DITHER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26139;"	d
+RG_EN_SX5GB_DITHER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26137;"	d
+RG_EN_SX5GB_DITHER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26136;"	d
+RG_EN_SX5GB_DITHER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26138;"	d
+RG_EN_SX5GB_DITHER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26140;"	d
+RG_EN_SX5GB_DIV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25644;"	d
+RG_EN_SX5GB_DIV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25642;"	d
+RG_EN_SX5GB_DIV_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25639;"	d
+RG_EN_SX5GB_DIV_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25637;"	d
+RG_EN_SX5GB_DIV_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25636;"	d
+RG_EN_SX5GB_DIV_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25638;"	d
+RG_EN_SX5GB_DIV_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25640;"	d
+RG_EN_SX5GB_DIV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25641;"	d
+RG_EN_SX5GB_DIV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25643;"	d
+RG_EN_SX5GB_DIV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25645;"	d
+RG_EN_SX5GB_HSDIV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25684;"	d
+RG_EN_SX5GB_HSDIV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25682;"	d
+RG_EN_SX5GB_HSDIV_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25679;"	d
+RG_EN_SX5GB_HSDIV_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25677;"	d
+RG_EN_SX5GB_HSDIV_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25676;"	d
+RG_EN_SX5GB_HSDIV_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25678;"	d
+RG_EN_SX5GB_HSDIV_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25680;"	d
+RG_EN_SX5GB_HSDIV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25681;"	d
+RG_EN_SX5GB_HSDIV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25683;"	d
+RG_EN_SX5GB_HSDIV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25685;"	d
+RG_EN_SX5GB_LDO_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25769;"	d
+RG_EN_SX5GB_LDO_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25767;"	d
+RG_EN_SX5GB_LDO_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25766;"	d
+RG_EN_SX5GB_LDO_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25768;"	d
+RG_EN_SX5GB_LDO_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25770;"	d
+RG_EN_SX5GB_MOD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26134;"	d
+RG_EN_SX5GB_MOD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26132;"	d
+RG_EN_SX5GB_MOD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26131;"	d
+RG_EN_SX5GB_MOD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26133;"	d
+RG_EN_SX5GB_MOD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26135;"	d
+RG_EN_SX5GB_VCOMON_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26104;"	d
+RG_EN_SX5GB_VCOMON_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26102;"	d
+RG_EN_SX5GB_VCOMON_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26101;"	d
+RG_EN_SX5GB_VCOMON_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26103;"	d
+RG_EN_SX5GB_VCOMON_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26105;"	d
+RG_EN_SX5GB_VCO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25654;"	d
+RG_EN_SX5GB_VCO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25652;"	d
+RG_EN_SX5GB_VCO_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25649;"	d
+RG_EN_SX5GB_VCO_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25647;"	d
+RG_EN_SX5GB_VCO_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25646;"	d
+RG_EN_SX5GB_VCO_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25648;"	d
+RG_EN_SX5GB_VCO_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25650;"	d
+RG_EN_SX5GB_VCO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25651;"	d
+RG_EN_SX5GB_VCO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25653;"	d
+RG_EN_SX5GB_VCO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25655;"	d
+RG_EN_SXMIX_INBF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25799;"	d
+RG_EN_SXMIX_INBF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25797;"	d
+RG_EN_SXMIX_INBF_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25794;"	d
+RG_EN_SXMIX_INBF_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25792;"	d
+RG_EN_SXMIX_INBF_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25791;"	d
+RG_EN_SXMIX_INBF_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25793;"	d
+RG_EN_SXMIX_INBF_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25795;"	d
+RG_EN_SXMIX_INBF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25796;"	d
+RG_EN_SXMIX_INBF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25798;"	d
+RG_EN_SXMIX_INBF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25800;"	d
+RG_EN_SX_CHPLDO_HI	include/ssv6200_aux.h	16239;"	d
+RG_EN_SX_CHPLDO_I_MSK	include/ssv6200_aux.h	16237;"	d
+RG_EN_SX_CHPLDO_MSK	include/ssv6200_aux.h	16236;"	d
+RG_EN_SX_CHPLDO_SFT	include/ssv6200_aux.h	16238;"	d
+RG_EN_SX_CHPLDO_SZ	include/ssv6200_aux.h	16240;"	d
+RG_EN_SX_CHP_HI	include/ssv6200_aux.h	16924;"	d
+RG_EN_SX_CHP_I_MSK	include/ssv6200_aux.h	16922;"	d
+RG_EN_SX_CHP_MSK	include/ssv6200_aux.h	16921;"	d
+RG_EN_SX_CHP_SFT	include/ssv6200_aux.h	16923;"	d
+RG_EN_SX_CHP_SZ	include/ssv6200_aux.h	16925;"	d
+RG_EN_SX_CH_HI	include/ssv6200_aux.h	16919;"	d
+RG_EN_SX_CH_I_MSK	include/ssv6200_aux.h	16917;"	d
+RG_EN_SX_CH_MSK	include/ssv6200_aux.h	16916;"	d
+RG_EN_SX_CH_SFT	include/ssv6200_aux.h	16918;"	d
+RG_EN_SX_CH_SZ	include/ssv6200_aux.h	16920;"	d
+RG_EN_SX_CP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23114;"	d
+RG_EN_SX_CP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23112;"	d
+RG_EN_SX_CP_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23109;"	d
+RG_EN_SX_CP_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23107;"	d
+RG_EN_SX_CP_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23106;"	d
+RG_EN_SX_CP_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23108;"	d
+RG_EN_SX_CP_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23110;"	d
+RG_EN_SX_CP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23111;"	d
+RG_EN_SX_CP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23113;"	d
+RG_EN_SX_CP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23115;"	d
+RG_EN_SX_DITHER_HI	include/ssv6200_aux.h	16949;"	d
+RG_EN_SX_DITHER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23684;"	d
+RG_EN_SX_DITHER_I_MSK	include/ssv6200_aux.h	16947;"	d
+RG_EN_SX_DITHER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23682;"	d
+RG_EN_SX_DITHER_MSK	include/ssv6200_aux.h	16946;"	d
+RG_EN_SX_DITHER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23681;"	d
+RG_EN_SX_DITHER_SFT	include/ssv6200_aux.h	16948;"	d
+RG_EN_SX_DITHER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23683;"	d
+RG_EN_SX_DITHER_SZ	include/ssv6200_aux.h	16950;"	d
+RG_EN_SX_DITHER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23685;"	d
+RG_EN_SX_DIVCK_HI	include/ssv6200_aux.h	16929;"	d
+RG_EN_SX_DIVCK_I_MSK	include/ssv6200_aux.h	16927;"	d
+RG_EN_SX_DIVCK_MSK	include/ssv6200_aux.h	16926;"	d
+RG_EN_SX_DIVCK_SFT	include/ssv6200_aux.h	16928;"	d
+RG_EN_SX_DIVCK_SZ	include/ssv6200_aux.h	16930;"	d
+RG_EN_SX_DIV_HI	include/ssv6200_aux.h	16964;"	d
+RG_EN_SX_DIV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23124;"	d
+RG_EN_SX_DIV_I_MSK	include/ssv6200_aux.h	16962;"	d
+RG_EN_SX_DIV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23122;"	d
+RG_EN_SX_DIV_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23119;"	d
+RG_EN_SX_DIV_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23117;"	d
+RG_EN_SX_DIV_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23116;"	d
+RG_EN_SX_DIV_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23118;"	d
+RG_EN_SX_DIV_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23120;"	d
+RG_EN_SX_DIV_MSK	include/ssv6200_aux.h	16961;"	d
+RG_EN_SX_DIV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23121;"	d
+RG_EN_SX_DIV_SFT	include/ssv6200_aux.h	16963;"	d
+RG_EN_SX_DIV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23123;"	d
+RG_EN_SX_DIV_SZ	include/ssv6200_aux.h	16965;"	d
+RG_EN_SX_DIV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23125;"	d
+RG_EN_SX_HI	include/ssv6200_aux.h	16109;"	d
+RG_EN_SX_I_MSK	include/ssv6200_aux.h	16107;"	d
+RG_EN_SX_LCK_BIN_HI	include/ssv6200_aux.h	16259;"	d
+RG_EN_SX_LCK_BIN_I_MSK	include/ssv6200_aux.h	16257;"	d
+RG_EN_SX_LCK_BIN_MSK	include/ssv6200_aux.h	16256;"	d
+RG_EN_SX_LCK_BIN_SFT	include/ssv6200_aux.h	16258;"	d
+RG_EN_SX_LCK_BIN_SZ	include/ssv6200_aux.h	16260;"	d
+RG_EN_SX_LDO_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23234;"	d
+RG_EN_SX_LDO_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23232;"	d
+RG_EN_SX_LDO_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23231;"	d
+RG_EN_SX_LDO_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23233;"	d
+RG_EN_SX_LDO_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23235;"	d
+RG_EN_SX_LOBFLDO_HI	include/ssv6200_aux.h	16244;"	d
+RG_EN_SX_LOBFLDO_I_MSK	include/ssv6200_aux.h	16242;"	d
+RG_EN_SX_LOBFLDO_MSK	include/ssv6200_aux.h	16241;"	d
+RG_EN_SX_LOBFLDO_SFT	include/ssv6200_aux.h	16243;"	d
+RG_EN_SX_LOBFLDO_SZ	include/ssv6200_aux.h	16245;"	d
+RG_EN_SX_LPF_HI	include/ssv6200_aux.h	16969;"	d
+RG_EN_SX_LPF_I_MSK	include/ssv6200_aux.h	16967;"	d
+RG_EN_SX_LPF_MSK	include/ssv6200_aux.h	16966;"	d
+RG_EN_SX_LPF_SFT	include/ssv6200_aux.h	16968;"	d
+RG_EN_SX_LPF_SZ	include/ssv6200_aux.h	16970;"	d
+RG_EN_SX_MIX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25714;"	d
+RG_EN_SX_MIX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25712;"	d
+RG_EN_SX_MIX_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25709;"	d
+RG_EN_SX_MIX_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25707;"	d
+RG_EN_SX_MIX_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25706;"	d
+RG_EN_SX_MIX_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25708;"	d
+RG_EN_SX_MIX_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25710;"	d
+RG_EN_SX_MIX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25711;"	d
+RG_EN_SX_MIX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25713;"	d
+RG_EN_SX_MIX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25715;"	d
+RG_EN_SX_MOD_HI	include/ssv6200_aux.h	16944;"	d
+RG_EN_SX_MOD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23679;"	d
+RG_EN_SX_MOD_I_MSK	include/ssv6200_aux.h	16942;"	d
+RG_EN_SX_MOD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23677;"	d
+RG_EN_SX_MOD_MSK	include/ssv6200_aux.h	16941;"	d
+RG_EN_SX_MOD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23676;"	d
+RG_EN_SX_MOD_SFT	include/ssv6200_aux.h	16943;"	d
+RG_EN_SX_MOD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23678;"	d
+RG_EN_SX_MOD_SZ	include/ssv6200_aux.h	16945;"	d
+RG_EN_SX_MOD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23680;"	d
+RG_EN_SX_MSK	include/ssv6200_aux.h	16106;"	d
+RG_EN_SX_R3_HI	include/ssv6200_aux.h	16914;"	d
+RG_EN_SX_R3_I_MSK	include/ssv6200_aux.h	16912;"	d
+RG_EN_SX_R3_MSK	include/ssv6200_aux.h	16911;"	d
+RG_EN_SX_R3_SFT	include/ssv6200_aux.h	16913;"	d
+RG_EN_SX_R3_SZ	include/ssv6200_aux.h	16915;"	d
+RG_EN_SX_REP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25724;"	d
+RG_EN_SX_REP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25722;"	d
+RG_EN_SX_REP_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25719;"	d
+RG_EN_SX_REP_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25717;"	d
+RG_EN_SX_REP_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25716;"	d
+RG_EN_SX_REP_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25718;"	d
+RG_EN_SX_REP_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25720;"	d
+RG_EN_SX_REP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25721;"	d
+RG_EN_SX_REP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25723;"	d
+RG_EN_SX_REP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25725;"	d
+RG_EN_SX_SFT	include/ssv6200_aux.h	16108;"	d
+RG_EN_SX_SZ	include/ssv6200_aux.h	16110;"	d
+RG_EN_SX_VCOBF_HI	include/ssv6200_aux.h	16934;"	d
+RG_EN_SX_VCOBF_I_MSK	include/ssv6200_aux.h	16932;"	d
+RG_EN_SX_VCOBF_MSK	include/ssv6200_aux.h	16931;"	d
+RG_EN_SX_VCOBF_SFT	include/ssv6200_aux.h	16933;"	d
+RG_EN_SX_VCOBF_SZ	include/ssv6200_aux.h	16935;"	d
+RG_EN_SX_VCOMON_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23649;"	d
+RG_EN_SX_VCOMON_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23647;"	d
+RG_EN_SX_VCOMON_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23646;"	d
+RG_EN_SX_VCOMON_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23648;"	d
+RG_EN_SX_VCOMON_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23650;"	d
+RG_EN_SX_VCO_HI	include/ssv6200_aux.h	16939;"	d
+RG_EN_SX_VCO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23134;"	d
+RG_EN_SX_VCO_I_MSK	include/ssv6200_aux.h	16937;"	d
+RG_EN_SX_VCO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23132;"	d
+RG_EN_SX_VCO_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23129;"	d
+RG_EN_SX_VCO_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23127;"	d
+RG_EN_SX_VCO_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23126;"	d
+RG_EN_SX_VCO_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23128;"	d
+RG_EN_SX_VCO_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23130;"	d
+RG_EN_SX_VCO_MSK	include/ssv6200_aux.h	16936;"	d
+RG_EN_SX_VCO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23131;"	d
+RG_EN_SX_VCO_SFT	include/ssv6200_aux.h	16938;"	d
+RG_EN_SX_VCO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23133;"	d
+RG_EN_SX_VCO_SZ	include/ssv6200_aux.h	16940;"	d
+RG_EN_SX_VCO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23135;"	d
+RG_EN_SX_VT_MON_DG_HI	include/ssv6200_aux.h	16959;"	d
+RG_EN_SX_VT_MON_DG_I_MSK	include/ssv6200_aux.h	16957;"	d
+RG_EN_SX_VT_MON_DG_MSK	include/ssv6200_aux.h	16956;"	d
+RG_EN_SX_VT_MON_DG_SFT	include/ssv6200_aux.h	16958;"	d
+RG_EN_SX_VT_MON_DG_SZ	include/ssv6200_aux.h	16960;"	d
+RG_EN_SX_VT_MON_HI	include/ssv6200_aux.h	16954;"	d
+RG_EN_SX_VT_MON_I_MSK	include/ssv6200_aux.h	16952;"	d
+RG_EN_SX_VT_MON_MSK	include/ssv6200_aux.h	16951;"	d
+RG_EN_SX_VT_MON_SFT	include/ssv6200_aux.h	16953;"	d
+RG_EN_SX_VT_MON_SZ	include/ssv6200_aux.h	16955;"	d
+RG_EN_TESTPAD_IOSW_HI	include/ssv6200_aux.h	16274;"	d
+RG_EN_TESTPAD_IOSW_I_MSK	include/ssv6200_aux.h	16272;"	d
+RG_EN_TESTPAD_IOSW_MSK	include/ssv6200_aux.h	16271;"	d
+RG_EN_TESTPAD_IOSW_SFT	include/ssv6200_aux.h	16273;"	d
+RG_EN_TESTPAD_IOSW_SZ	include/ssv6200_aux.h	16275;"	d
+RG_EN_TRXBF_BYPASS_HI	include/ssv6200_aux.h	16279;"	d
+RG_EN_TRXBF_BYPASS_I_MSK	include/ssv6200_aux.h	16277;"	d
+RG_EN_TRXBF_BYPASS_MSK	include/ssv6200_aux.h	16276;"	d
+RG_EN_TRXBF_BYPASS_SFT	include/ssv6200_aux.h	16278;"	d
+RG_EN_TRXBF_BYPASS_SZ	include/ssv6200_aux.h	16280;"	d
+RG_EN_TX_BT_PA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21789;"	d
+RG_EN_TX_BT_PA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21787;"	d
+RG_EN_TX_BT_PA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21786;"	d
+RG_EN_TX_BT_PA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21788;"	d
+RG_EN_TX_BT_PA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21790;"	d
+RG_EN_TX_DAC_CAL_HI	include/ssv6200_aux.h	16209;"	d
+RG_EN_TX_DAC_CAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21824;"	d
+RG_EN_TX_DAC_CAL_I_MSK	include/ssv6200_aux.h	16207;"	d
+RG_EN_TX_DAC_CAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21822;"	d
+RG_EN_TX_DAC_CAL_MSK	include/ssv6200_aux.h	16206;"	d
+RG_EN_TX_DAC_CAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21821;"	d
+RG_EN_TX_DAC_CAL_SFT	include/ssv6200_aux.h	16208;"	d
+RG_EN_TX_DAC_CAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21823;"	d
+RG_EN_TX_DAC_CAL_SZ	include/ssv6200_aux.h	16210;"	d
+RG_EN_TX_DAC_CAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21825;"	d
+RG_EN_TX_DAC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21759;"	d
+RG_EN_TX_DAC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21757;"	d
+RG_EN_TX_DAC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21756;"	d
+RG_EN_TX_DAC_OUT_HI	include/ssv6200_aux.h	16219;"	d
+RG_EN_TX_DAC_OUT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21894;"	d
+RG_EN_TX_DAC_OUT_I_MSK	include/ssv6200_aux.h	16217;"	d
+RG_EN_TX_DAC_OUT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21892;"	d
+RG_EN_TX_DAC_OUT_MSK	include/ssv6200_aux.h	16216;"	d
+RG_EN_TX_DAC_OUT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21891;"	d
+RG_EN_TX_DAC_OUT_SFT	include/ssv6200_aux.h	16218;"	d
+RG_EN_TX_DAC_OUT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21893;"	d
+RG_EN_TX_DAC_OUT_SZ	include/ssv6200_aux.h	16220;"	d
+RG_EN_TX_DAC_OUT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21895;"	d
+RG_EN_TX_DAC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21758;"	d
+RG_EN_TX_DAC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21760;"	d
+RG_EN_TX_DAC_VOUT_HI	include/ssv6200_aux.h	16254;"	d
+RG_EN_TX_DAC_VOUT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21899;"	d
+RG_EN_TX_DAC_VOUT_I_MSK	include/ssv6200_aux.h	16252;"	d
+RG_EN_TX_DAC_VOUT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21897;"	d
+RG_EN_TX_DAC_VOUT_MSK	include/ssv6200_aux.h	16251;"	d
+RG_EN_TX_DAC_VOUT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21896;"	d
+RG_EN_TX_DAC_VOUT_SFT	include/ssv6200_aux.h	16253;"	d
+RG_EN_TX_DAC_VOUT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21898;"	d
+RG_EN_TX_DAC_VOUT_SZ	include/ssv6200_aux.h	16255;"	d
+RG_EN_TX_DAC_VOUT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21900;"	d
+RG_EN_TX_DIV2_BUF_HI	include/ssv6200_aux.h	16169;"	d
+RG_EN_TX_DIV2_BUF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21779;"	d
+RG_EN_TX_DIV2_BUF_I_MSK	include/ssv6200_aux.h	16167;"	d
+RG_EN_TX_DIV2_BUF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21777;"	d
+RG_EN_TX_DIV2_BUF_MSK	include/ssv6200_aux.h	16166;"	d
+RG_EN_TX_DIV2_BUF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21776;"	d
+RG_EN_TX_DIV2_BUF_SFT	include/ssv6200_aux.h	16168;"	d
+RG_EN_TX_DIV2_BUF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21778;"	d
+RG_EN_TX_DIV2_BUF_SZ	include/ssv6200_aux.h	16170;"	d
+RG_EN_TX_DIV2_BUF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21780;"	d
+RG_EN_TX_DIV2_HI	include/ssv6200_aux.h	16164;"	d
+RG_EN_TX_DIV2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21769;"	d
+RG_EN_TX_DIV2_I_MSK	include/ssv6200_aux.h	16162;"	d
+RG_EN_TX_DIV2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21767;"	d
+RG_EN_TX_DIV2_MSK	include/ssv6200_aux.h	16161;"	d
+RG_EN_TX_DIV2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21766;"	d
+RG_EN_TX_DIV2_SFT	include/ssv6200_aux.h	16163;"	d
+RG_EN_TX_DIV2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21768;"	d
+RG_EN_TX_DIV2_SZ	include/ssv6200_aux.h	16165;"	d
+RG_EN_TX_DIV2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21770;"	d
+RG_EN_TX_DPD_HI	include/ssv6200_aux.h	16194;"	d
+RG_EN_TX_DPD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21864;"	d
+RG_EN_TX_DPD_I_MSK	include/ssv6200_aux.h	16192;"	d
+RG_EN_TX_DPD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21862;"	d
+RG_EN_TX_DPD_MSK	include/ssv6200_aux.h	16191;"	d
+RG_EN_TX_DPD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21861;"	d
+RG_EN_TX_DPD_SFT	include/ssv6200_aux.h	16193;"	d
+RG_EN_TX_DPD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21863;"	d
+RG_EN_TX_DPD_SZ	include/ssv6200_aux.h	16195;"	d
+RG_EN_TX_DPD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21865;"	d
+RG_EN_TX_LOBF_HI	include/ssv6200_aux.h	16174;"	d
+RG_EN_TX_LOBF_I_MSK	include/ssv6200_aux.h	16172;"	d
+RG_EN_TX_LOBF_MSK	include/ssv6200_aux.h	16171;"	d
+RG_EN_TX_LOBF_SFT	include/ssv6200_aux.h	16173;"	d
+RG_EN_TX_LOBF_SZ	include/ssv6200_aux.h	16175;"	d
+RG_EN_TX_MOD_HI	include/ssv6200_aux.h	16159;"	d
+RG_EN_TX_MOD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21749;"	d
+RG_EN_TX_MOD_I_MSK	include/ssv6200_aux.h	16157;"	d
+RG_EN_TX_MOD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21747;"	d
+RG_EN_TX_MOD_MSK	include/ssv6200_aux.h	16156;"	d
+RG_EN_TX_MOD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21746;"	d
+RG_EN_TX_MOD_SFT	include/ssv6200_aux.h	16158;"	d
+RG_EN_TX_MOD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21748;"	d
+RG_EN_TX_MOD_SZ	include/ssv6200_aux.h	16160;"	d
+RG_EN_TX_MOD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21750;"	d
+RG_EN_TX_PA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21739;"	d
+RG_EN_TX_PA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21737;"	d
+RG_EN_TX_PA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21736;"	d
+RG_EN_TX_PA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21738;"	d
+RG_EN_TX_PA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21740;"	d
+RG_EN_TX_SELF_MIXER_HI	include/ssv6200_aux.h	16214;"	d
+RG_EN_TX_SELF_MIXER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21844;"	d
+RG_EN_TX_SELF_MIXER_I_MSK	include/ssv6200_aux.h	16212;"	d
+RG_EN_TX_SELF_MIXER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21842;"	d
+RG_EN_TX_SELF_MIXER_MSK	include/ssv6200_aux.h	16211;"	d
+RG_EN_TX_SELF_MIXER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21841;"	d
+RG_EN_TX_SELF_MIXER_SFT	include/ssv6200_aux.h	16213;"	d
+RG_EN_TX_SELF_MIXER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21843;"	d
+RG_EN_TX_SELF_MIXER_SZ	include/ssv6200_aux.h	16215;"	d
+RG_EN_TX_SELF_MIXER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21845;"	d
+RG_EN_TX_TRSW_HI	include/ssv6200_aux.h	16104;"	d
+RG_EN_TX_TRSW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21649;"	d
+RG_EN_TX_TRSW_I_MSK	include/ssv6200_aux.h	16102;"	d
+RG_EN_TX_TRSW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21647;"	d
+RG_EN_TX_TRSW_MSK	include/ssv6200_aux.h	16101;"	d
+RG_EN_TX_TRSW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21646;"	d
+RG_EN_TX_TRSW_SFT	include/ssv6200_aux.h	16103;"	d
+RG_EN_TX_TRSW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21648;"	d
+RG_EN_TX_TRSW_SZ	include/ssv6200_aux.h	16105;"	d
+RG_EN_TX_TRSW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21650;"	d
+RG_EN_TX_TSSI_HI	include/ssv6200_aux.h	16199;"	d
+RG_EN_TX_TSSI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21869;"	d
+RG_EN_TX_TSSI_I_MSK	include/ssv6200_aux.h	16197;"	d
+RG_EN_TX_TSSI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21867;"	d
+RG_EN_TX_TSSI_MSK	include/ssv6200_aux.h	16196;"	d
+RG_EN_TX_TSSI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21866;"	d
+RG_EN_TX_TSSI_SFT	include/ssv6200_aux.h	16198;"	d
+RG_EN_TX_TSSI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21868;"	d
+RG_EN_TX_TSSI_SZ	include/ssv6200_aux.h	16200;"	d
+RG_EN_TX_TSSI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21870;"	d
+RG_EN_TX_VTOI_2ND_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21879;"	d
+RG_EN_TX_VTOI_2ND_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21877;"	d
+RG_EN_TX_VTOI_2ND_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21876;"	d
+RG_EN_TX_VTOI_2ND_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21878;"	d
+RG_EN_TX_VTOI_2ND_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21880;"	d
+RG_EN_VCOBF_DIVCK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23204;"	d
+RG_EN_VCOBF_DIVCK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23202;"	d
+RG_EN_VCOBF_DIVCK_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23199;"	d
+RG_EN_VCOBF_DIVCK_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23197;"	d
+RG_EN_VCOBF_DIVCK_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23196;"	d
+RG_EN_VCOBF_DIVCK_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23198;"	d
+RG_EN_VCOBF_DIVCK_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23200;"	d
+RG_EN_VCOBF_DIVCK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23201;"	d
+RG_EN_VCOBF_DIVCK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23203;"	d
+RG_EN_VCOBF_DIVCK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23205;"	d
+RG_EN_VCOBF_RXMB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23184;"	d
+RG_EN_VCOBF_RXMB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23182;"	d
+RG_EN_VCOBF_RXMB_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23179;"	d
+RG_EN_VCOBF_RXMB_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23177;"	d
+RG_EN_VCOBF_RXMB_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23176;"	d
+RG_EN_VCOBF_RXMB_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23178;"	d
+RG_EN_VCOBF_RXMB_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23180;"	d
+RG_EN_VCOBF_RXMB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23181;"	d
+RG_EN_VCOBF_RXMB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23183;"	d
+RG_EN_VCOBF_RXMB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23185;"	d
+RG_EN_VCOBF_RXOB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23194;"	d
+RG_EN_VCOBF_RXOB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23192;"	d
+RG_EN_VCOBF_RXOB_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23189;"	d
+RG_EN_VCOBF_RXOB_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23187;"	d
+RG_EN_VCOBF_RXOB_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23186;"	d
+RG_EN_VCOBF_RXOB_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23188;"	d
+RG_EN_VCOBF_RXOB_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23190;"	d
+RG_EN_VCOBF_RXOB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23191;"	d
+RG_EN_VCOBF_RXOB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23193;"	d
+RG_EN_VCOBF_RXOB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23195;"	d
+RG_EN_VCOBF_TXMB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23164;"	d
+RG_EN_VCOBF_TXMB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23162;"	d
+RG_EN_VCOBF_TXMB_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23159;"	d
+RG_EN_VCOBF_TXMB_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23157;"	d
+RG_EN_VCOBF_TXMB_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23156;"	d
+RG_EN_VCOBF_TXMB_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23158;"	d
+RG_EN_VCOBF_TXMB_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23160;"	d
+RG_EN_VCOBF_TXMB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23161;"	d
+RG_EN_VCOBF_TXMB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23163;"	d
+RG_EN_VCOBF_TXMB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23165;"	d
+RG_EN_VCOBF_TXOB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23174;"	d
+RG_EN_VCOBF_TXOB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23172;"	d
+RG_EN_VCOBF_TXOB_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23169;"	d
+RG_EN_VCOBF_TXOB_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23167;"	d
+RG_EN_VCOBF_TXOB_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23166;"	d
+RG_EN_VCOBF_TXOB_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23168;"	d
+RG_EN_VCOBF_TXOB_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23170;"	d
+RG_EN_VCOBF_TXOB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23171;"	d
+RG_EN_VCOBF_TXOB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23173;"	d
+RG_EN_VCOBF_TXOB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23175;"	d
+RG_EN_XOTEST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29529;"	d
+RG_EN_XOTEST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29527;"	d
+RG_EN_XOTEST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29526;"	d
+RG_EN_XOTEST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29528;"	d
+RG_EN_XOTEST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29530;"	d
+RG_EQ_BYPASS_FBW_TAP_HI	include/ssv6200_aux.h	14674;"	d
+RG_EQ_BYPASS_FBW_TAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31874;"	d
+RG_EQ_BYPASS_FBW_TAP_I_MSK	include/ssv6200_aux.h	14672;"	d
+RG_EQ_BYPASS_FBW_TAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31872;"	d
+RG_EQ_BYPASS_FBW_TAP_MSK	include/ssv6200_aux.h	14671;"	d
+RG_EQ_BYPASS_FBW_TAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31871;"	d
+RG_EQ_BYPASS_FBW_TAP_SFT	include/ssv6200_aux.h	14673;"	d
+RG_EQ_BYPASS_FBW_TAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31873;"	d
+RG_EQ_BYPASS_FBW_TAP_SZ	include/ssv6200_aux.h	14675;"	d
+RG_EQ_BYPASS_FBW_TAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31875;"	d
+RG_EQ_KI_T1_HI	include/ssv6200_aux.h	14509;"	d
+RG_EQ_KI_T1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31664;"	d
+RG_EQ_KI_T1_I_MSK	include/ssv6200_aux.h	14507;"	d
+RG_EQ_KI_T1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31662;"	d
+RG_EQ_KI_T1_MSK	include/ssv6200_aux.h	14506;"	d
+RG_EQ_KI_T1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31661;"	d
+RG_EQ_KI_T1_SFT	include/ssv6200_aux.h	14508;"	d
+RG_EQ_KI_T1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31663;"	d
+RG_EQ_KI_T1_SZ	include/ssv6200_aux.h	14510;"	d
+RG_EQ_KI_T1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31665;"	d
+RG_EQ_KI_T2_HI	include/ssv6200_aux.h	14499;"	d
+RG_EQ_KI_T2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31654;"	d
+RG_EQ_KI_T2_I_MSK	include/ssv6200_aux.h	14497;"	d
+RG_EQ_KI_T2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31652;"	d
+RG_EQ_KI_T2_MSK	include/ssv6200_aux.h	14496;"	d
+RG_EQ_KI_T2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31651;"	d
+RG_EQ_KI_T2_SFT	include/ssv6200_aux.h	14498;"	d
+RG_EQ_KI_T2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31653;"	d
+RG_EQ_KI_T2_SZ	include/ssv6200_aux.h	14500;"	d
+RG_EQ_KI_T2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31655;"	d
+RG_EQ_KP_T1_HI	include/ssv6200_aux.h	14514;"	d
+RG_EQ_KP_T1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31669;"	d
+RG_EQ_KP_T1_I_MSK	include/ssv6200_aux.h	14512;"	d
+RG_EQ_KP_T1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31667;"	d
+RG_EQ_KP_T1_MSK	include/ssv6200_aux.h	14511;"	d
+RG_EQ_KP_T1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31666;"	d
+RG_EQ_KP_T1_SFT	include/ssv6200_aux.h	14513;"	d
+RG_EQ_KP_T1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31668;"	d
+RG_EQ_KP_T1_SZ	include/ssv6200_aux.h	14515;"	d
+RG_EQ_KP_T1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31670;"	d
+RG_EQ_KP_T2_HI	include/ssv6200_aux.h	14504;"	d
+RG_EQ_KP_T2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31659;"	d
+RG_EQ_KP_T2_I_MSK	include/ssv6200_aux.h	14502;"	d
+RG_EQ_KP_T2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31657;"	d
+RG_EQ_KP_T2_MSK	include/ssv6200_aux.h	14501;"	d
+RG_EQ_KP_T2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31656;"	d
+RG_EQ_KP_T2_SFT	include/ssv6200_aux.h	14503;"	d
+RG_EQ_KP_T2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31658;"	d
+RG_EQ_KP_T2_SZ	include/ssv6200_aux.h	14505;"	d
+RG_EQ_KP_T2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31660;"	d
+RG_EQ_MAIN_TAP_COEF_HI	include/ssv6200_aux.h	14554;"	d
+RG_EQ_MAIN_TAP_COEF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31709;"	d
+RG_EQ_MAIN_TAP_COEF_I_MSK	include/ssv6200_aux.h	14552;"	d
+RG_EQ_MAIN_TAP_COEF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31707;"	d
+RG_EQ_MAIN_TAP_COEF_MSK	include/ssv6200_aux.h	14551;"	d
+RG_EQ_MAIN_TAP_COEF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31706;"	d
+RG_EQ_MAIN_TAP_COEF_SFT	include/ssv6200_aux.h	14553;"	d
+RG_EQ_MAIN_TAP_COEF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31708;"	d
+RG_EQ_MAIN_TAP_COEF_SZ	include/ssv6200_aux.h	14555;"	d
+RG_EQ_MAIN_TAP_COEF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31710;"	d
+RG_EQ_MAIN_TAP_MAN_HI	include/ssv6200_aux.h	14549;"	d
+RG_EQ_MAIN_TAP_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31704;"	d
+RG_EQ_MAIN_TAP_MAN_I_MSK	include/ssv6200_aux.h	14547;"	d
+RG_EQ_MAIN_TAP_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31702;"	d
+RG_EQ_MAIN_TAP_MAN_MSK	include/ssv6200_aux.h	14546;"	d
+RG_EQ_MAIN_TAP_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31701;"	d
+RG_EQ_MAIN_TAP_MAN_SFT	include/ssv6200_aux.h	14548;"	d
+RG_EQ_MAIN_TAP_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31703;"	d
+RG_EQ_MAIN_TAP_MAN_SZ	include/ssv6200_aux.h	14550;"	d
+RG_EQ_MAIN_TAP_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31705;"	d
+RG_EQ_MU_FB_T1_HI	include/ssv6200_aux.h	14469;"	d
+RG_EQ_MU_FB_T1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31624;"	d
+RG_EQ_MU_FB_T1_I_MSK	include/ssv6200_aux.h	14467;"	d
+RG_EQ_MU_FB_T1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31622;"	d
+RG_EQ_MU_FB_T1_MSK	include/ssv6200_aux.h	14466;"	d
+RG_EQ_MU_FB_T1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31621;"	d
+RG_EQ_MU_FB_T1_SFT	include/ssv6200_aux.h	14468;"	d
+RG_EQ_MU_FB_T1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31623;"	d
+RG_EQ_MU_FB_T1_SZ	include/ssv6200_aux.h	14470;"	d
+RG_EQ_MU_FB_T1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31625;"	d
+RG_EQ_MU_FB_T2_HI	include/ssv6200_aux.h	14459;"	d
+RG_EQ_MU_FB_T2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31614;"	d
+RG_EQ_MU_FB_T2_I_MSK	include/ssv6200_aux.h	14457;"	d
+RG_EQ_MU_FB_T2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31612;"	d
+RG_EQ_MU_FB_T2_MSK	include/ssv6200_aux.h	14456;"	d
+RG_EQ_MU_FB_T2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31611;"	d
+RG_EQ_MU_FB_T2_SFT	include/ssv6200_aux.h	14458;"	d
+RG_EQ_MU_FB_T2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31613;"	d
+RG_EQ_MU_FB_T2_SZ	include/ssv6200_aux.h	14460;"	d
+RG_EQ_MU_FB_T2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31615;"	d
+RG_EQ_MU_FB_T3_HI	include/ssv6200_aux.h	14489;"	d
+RG_EQ_MU_FB_T3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31644;"	d
+RG_EQ_MU_FB_T3_I_MSK	include/ssv6200_aux.h	14487;"	d
+RG_EQ_MU_FB_T3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31642;"	d
+RG_EQ_MU_FB_T3_MSK	include/ssv6200_aux.h	14486;"	d
+RG_EQ_MU_FB_T3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31641;"	d
+RG_EQ_MU_FB_T3_SFT	include/ssv6200_aux.h	14488;"	d
+RG_EQ_MU_FB_T3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31643;"	d
+RG_EQ_MU_FB_T3_SZ	include/ssv6200_aux.h	14490;"	d
+RG_EQ_MU_FB_T3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31645;"	d
+RG_EQ_MU_FB_T4_HI	include/ssv6200_aux.h	14479;"	d
+RG_EQ_MU_FB_T4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31634;"	d
+RG_EQ_MU_FB_T4_I_MSK	include/ssv6200_aux.h	14477;"	d
+RG_EQ_MU_FB_T4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31632;"	d
+RG_EQ_MU_FB_T4_MSK	include/ssv6200_aux.h	14476;"	d
+RG_EQ_MU_FB_T4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31631;"	d
+RG_EQ_MU_FB_T4_SFT	include/ssv6200_aux.h	14478;"	d
+RG_EQ_MU_FB_T4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31633;"	d
+RG_EQ_MU_FB_T4_SZ	include/ssv6200_aux.h	14480;"	d
+RG_EQ_MU_FB_T4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31635;"	d
+RG_EQ_MU_FF_T1_HI	include/ssv6200_aux.h	14474;"	d
+RG_EQ_MU_FF_T1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31629;"	d
+RG_EQ_MU_FF_T1_I_MSK	include/ssv6200_aux.h	14472;"	d
+RG_EQ_MU_FF_T1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31627;"	d
+RG_EQ_MU_FF_T1_MSK	include/ssv6200_aux.h	14471;"	d
+RG_EQ_MU_FF_T1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31626;"	d
+RG_EQ_MU_FF_T1_SFT	include/ssv6200_aux.h	14473;"	d
+RG_EQ_MU_FF_T1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31628;"	d
+RG_EQ_MU_FF_T1_SZ	include/ssv6200_aux.h	14475;"	d
+RG_EQ_MU_FF_T1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31630;"	d
+RG_EQ_MU_FF_T2_HI	include/ssv6200_aux.h	14464;"	d
+RG_EQ_MU_FF_T2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31619;"	d
+RG_EQ_MU_FF_T2_I_MSK	include/ssv6200_aux.h	14462;"	d
+RG_EQ_MU_FF_T2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31617;"	d
+RG_EQ_MU_FF_T2_MSK	include/ssv6200_aux.h	14461;"	d
+RG_EQ_MU_FF_T2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31616;"	d
+RG_EQ_MU_FF_T2_SFT	include/ssv6200_aux.h	14463;"	d
+RG_EQ_MU_FF_T2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31618;"	d
+RG_EQ_MU_FF_T2_SZ	include/ssv6200_aux.h	14465;"	d
+RG_EQ_MU_FF_T2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31620;"	d
+RG_EQ_MU_FF_T3_HI	include/ssv6200_aux.h	14494;"	d
+RG_EQ_MU_FF_T3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31649;"	d
+RG_EQ_MU_FF_T3_I_MSK	include/ssv6200_aux.h	14492;"	d
+RG_EQ_MU_FF_T3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31647;"	d
+RG_EQ_MU_FF_T3_MSK	include/ssv6200_aux.h	14491;"	d
+RG_EQ_MU_FF_T3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31646;"	d
+RG_EQ_MU_FF_T3_SFT	include/ssv6200_aux.h	14493;"	d
+RG_EQ_MU_FF_T3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31648;"	d
+RG_EQ_MU_FF_T3_SZ	include/ssv6200_aux.h	14495;"	d
+RG_EQ_MU_FF_T3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31650;"	d
+RG_EQ_MU_FF_T4_HI	include/ssv6200_aux.h	14484;"	d
+RG_EQ_MU_FF_T4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31639;"	d
+RG_EQ_MU_FF_T4_I_MSK	include/ssv6200_aux.h	14482;"	d
+RG_EQ_MU_FF_T4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31637;"	d
+RG_EQ_MU_FF_T4_MSK	include/ssv6200_aux.h	14481;"	d
+RG_EQ_MU_FF_T4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31636;"	d
+RG_EQ_MU_FF_T4_SFT	include/ssv6200_aux.h	14483;"	d
+RG_EQ_MU_FF_T4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31638;"	d
+RG_EQ_MU_FF_T4_SZ	include/ssv6200_aux.h	14485;"	d
+RG_EQ_MU_FF_T4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31640;"	d
+RG_EQ_SHORT_GI_SHIFT_HI	include/ssv6200_aux.h	15029;"	d
+RG_EQ_SHORT_GI_SHIFT_I_MSK	include/ssv6200_aux.h	15027;"	d
+RG_EQ_SHORT_GI_SHIFT_MSK	include/ssv6200_aux.h	15026;"	d
+RG_EQ_SHORT_GI_SHIFT_SFT	include/ssv6200_aux.h	15028;"	d
+RG_EQ_SHORT_GI_SHIFT_SZ	include/ssv6200_aux.h	15030;"	d
+RG_ERASE_SC_NUM0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32224;"	d
+RG_ERASE_SC_NUM0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32222;"	d
+RG_ERASE_SC_NUM0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32221;"	d
+RG_ERASE_SC_NUM0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32223;"	d
+RG_ERASE_SC_NUM0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32225;"	d
+RG_ERASE_SC_NUM1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32214;"	d
+RG_ERASE_SC_NUM1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32212;"	d
+RG_ERASE_SC_NUM1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32211;"	d
+RG_ERASE_SC_NUM1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32213;"	d
+RG_ERASE_SC_NUM1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32215;"	d
+RG_ERASE_SC_NUM2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32204;"	d
+RG_ERASE_SC_NUM2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32202;"	d
+RG_ERASE_SC_NUM2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32201;"	d
+RG_ERASE_SC_NUM2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32203;"	d
+RG_ERASE_SC_NUM2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32205;"	d
+RG_ERASE_SC_NUM3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32194;"	d
+RG_ERASE_SC_NUM3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32192;"	d
+RG_ERASE_SC_NUM3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32191;"	d
+RG_ERASE_SC_NUM3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32193;"	d
+RG_ERASE_SC_NUM3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32195;"	d
+RG_ERASE_SC_NUM4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32264;"	d
+RG_ERASE_SC_NUM4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32262;"	d
+RG_ERASE_SC_NUM4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32261;"	d
+RG_ERASE_SC_NUM4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32263;"	d
+RG_ERASE_SC_NUM4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32265;"	d
+RG_ERASE_SC_NUM5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32254;"	d
+RG_ERASE_SC_NUM5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32252;"	d
+RG_ERASE_SC_NUM5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32251;"	d
+RG_ERASE_SC_NUM5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32253;"	d
+RG_ERASE_SC_NUM5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32255;"	d
+RG_ERASE_SC_NUM6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32244;"	d
+RG_ERASE_SC_NUM6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32242;"	d
+RG_ERASE_SC_NUM6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32241;"	d
+RG_ERASE_SC_NUM6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32243;"	d
+RG_ERASE_SC_NUM6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32245;"	d
+RG_ERASE_SC_NUM7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32234;"	d
+RG_ERASE_SC_NUM7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32232;"	d
+RG_ERASE_SC_NUM7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32231;"	d
+RG_ERASE_SC_NUM7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32233;"	d
+RG_ERASE_SC_NUM7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32235;"	d
+RG_FDB_BYPASS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29519;"	d
+RG_FDB_BYPASS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29517;"	d
+RG_FDB_BYPASS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29516;"	d
+RG_FDB_BYPASS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29518;"	d
+RG_FDB_BYPASS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29520;"	d
+RG_FDB_CDELAY_MUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29569;"	d
+RG_FDB_CDELAY_MUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29567;"	d
+RG_FDB_CDELAY_MUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29566;"	d
+RG_FDB_CDELAY_MUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29568;"	d
+RG_FDB_CDELAY_MUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29570;"	d
+RG_FDB_DUTY_LTH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29524;"	d
+RG_FDB_DUTY_LTH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29522;"	d
+RG_FDB_DUTY_LTH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29521;"	d
+RG_FDB_DUTY_LTH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29523;"	d
+RG_FDB_DUTY_LTH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29525;"	d
+RG_FDB_FDELAY_MUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29574;"	d
+RG_FDB_FDELAY_MUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29572;"	d
+RG_FDB_FDELAY_MUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29571;"	d
+RG_FDB_FDELAY_MUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29573;"	d
+RG_FDB_FDELAY_MUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29575;"	d
+RG_FDB_PHASESWAP_MUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29559;"	d
+RG_FDB_PHASESWAP_MUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29557;"	d
+RG_FDB_PHASESWAP_MUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29556;"	d
+RG_FDB_PHASESWAP_MUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29558;"	d
+RG_FDB_PHASESWAP_MUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29560;"	d
+RG_FDB_RDELAYF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29589;"	d
+RG_FDB_RDELAYF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29587;"	d
+RG_FDB_RDELAYF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29586;"	d
+RG_FDB_RDELAYF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29588;"	d
+RG_FDB_RDELAYF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29590;"	d
+RG_FDB_RDELAYS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29594;"	d
+RG_FDB_RDELAYS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29592;"	d
+RG_FDB_RDELAYS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29591;"	d
+RG_FDB_RDELAYS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29593;"	d
+RG_FDB_RDELAYS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29595;"	d
+RG_FDB_RECAL_TIMMER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29599;"	d
+RG_FDB_RECAL_TIMMER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29597;"	d
+RG_FDB_RECAL_TIMMER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29596;"	d
+RG_FDB_RECAL_TIMMER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29598;"	d
+RG_FDB_RECAL_TIMMER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29600;"	d
+RG_FEC_HI	include/ssv6200_aux.h	13199;"	d
+RG_FEC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30389;"	d
+RG_FEC_I_MSK	include/ssv6200_aux.h	13197;"	d
+RG_FEC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30387;"	d
+RG_FEC_MSK	include/ssv6200_aux.h	13196;"	d
+RG_FEC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30386;"	d
+RG_FEC_SFT	include/ssv6200_aux.h	13198;"	d
+RG_FEC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30388;"	d
+RG_FEC_SZ	include/ssv6200_aux.h	13200;"	d
+RG_FEC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30390;"	d
+RG_FFT_ENRG_FREQ_HI	include/ssv6200_aux.h	15704;"	d
+RG_FFT_ENRG_FREQ_I_MSK	include/ssv6200_aux.h	15702;"	d
+RG_FFT_ENRG_FREQ_MSK	include/ssv6200_aux.h	15701;"	d
+RG_FFT_ENRG_FREQ_SFT	include/ssv6200_aux.h	15703;"	d
+RG_FFT_ENRG_FREQ_SZ	include/ssv6200_aux.h	15705;"	d
+RG_FFT_EN_HI	include/ssv6200_aux.h	15689;"	d
+RG_FFT_EN_I_MSK	include/ssv6200_aux.h	15687;"	d
+RG_FFT_EN_MSK	include/ssv6200_aux.h	15686;"	d
+RG_FFT_EN_SFT	include/ssv6200_aux.h	15688;"	d
+RG_FFT_EN_SZ	include/ssv6200_aux.h	15690;"	d
+RG_FFT_IFFT_MODE_HI	include/ssv6200_aux.h	13244;"	d
+RG_FFT_IFFT_MODE_I_MSK	include/ssv6200_aux.h	13242;"	d
+RG_FFT_IFFT_MODE_MSK	include/ssv6200_aux.h	13241;"	d
+RG_FFT_IFFT_MODE_SFT	include/ssv6200_aux.h	13243;"	d
+RG_FFT_IFFT_MODE_SZ	include/ssv6200_aux.h	13245;"	d
+RG_FFT_MEM_CLK_EN_RX_HI	include/ssv6200_aux.h	13109;"	d
+RG_FFT_MEM_CLK_EN_RX_I_MSK	include/ssv6200_aux.h	13107;"	d
+RG_FFT_MEM_CLK_EN_RX_MSK	include/ssv6200_aux.h	13106;"	d
+RG_FFT_MEM_CLK_EN_RX_SFT	include/ssv6200_aux.h	13108;"	d
+RG_FFT_MEM_CLK_EN_RX_SZ	include/ssv6200_aux.h	13110;"	d
+RG_FFT_MEM_CLK_EN_TX_HI	include/ssv6200_aux.h	13114;"	d
+RG_FFT_MEM_CLK_EN_TX_I_MSK	include/ssv6200_aux.h	13112;"	d
+RG_FFT_MEM_CLK_EN_TX_MSK	include/ssv6200_aux.h	13111;"	d
+RG_FFT_MEM_CLK_EN_TX_SFT	include/ssv6200_aux.h	13113;"	d
+RG_FFT_MEM_CLK_EN_TX_SZ	include/ssv6200_aux.h	13115;"	d
+RG_FFT_MOD_HI	include/ssv6200_aux.h	15694;"	d
+RG_FFT_MOD_I_MSK	include/ssv6200_aux.h	15692;"	d
+RG_FFT_MOD_MSK	include/ssv6200_aux.h	15691;"	d
+RG_FFT_MOD_SFT	include/ssv6200_aux.h	15693;"	d
+RG_FFT_MOD_SZ	include/ssv6200_aux.h	15695;"	d
+RG_FFT_SCALE_104_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31944;"	d
+RG_FFT_SCALE_104_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31942;"	d
+RG_FFT_SCALE_104_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31941;"	d
+RG_FFT_SCALE_104_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31943;"	d
+RG_FFT_SCALE_104_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31945;"	d
+RG_FFT_SCALE_114_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31949;"	d
+RG_FFT_SCALE_114_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31947;"	d
+RG_FFT_SCALE_114_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31946;"	d
+RG_FFT_SCALE_114_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31948;"	d
+RG_FFT_SCALE_114_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31950;"	d
+RG_FFT_SCALE_52_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31954;"	d
+RG_FFT_SCALE_52_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31952;"	d
+RG_FFT_SCALE_52_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31951;"	d
+RG_FFT_SCALE_52_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31953;"	d
+RG_FFT_SCALE_52_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31955;"	d
+RG_FFT_SCALE_56_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31959;"	d
+RG_FFT_SCALE_56_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31957;"	d
+RG_FFT_SCALE_56_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31956;"	d
+RG_FFT_SCALE_56_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31958;"	d
+RG_FFT_SCALE_56_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31960;"	d
+RG_FFT_SCALE_HI	include/ssv6200_aux.h	15699;"	d
+RG_FFT_SCALE_I_MSK	include/ssv6200_aux.h	15697;"	d
+RG_FFT_SCALE_MSK	include/ssv6200_aux.h	15696;"	d
+RG_FFT_SCALE_SFT	include/ssv6200_aux.h	15698;"	d
+RG_FFT_SCALE_SZ	include/ssv6200_aux.h	15700;"	d
+RG_FFT_WDW_SHORT_SHIFT_HI	include/ssv6200_aux.h	15034;"	d
+RG_FFT_WDW_SHORT_SHIFT_I_MSK	include/ssv6200_aux.h	15032;"	d
+RG_FFT_WDW_SHORT_SHIFT_MSK	include/ssv6200_aux.h	15031;"	d
+RG_FFT_WDW_SHORT_SHIFT_SFT	include/ssv6200_aux.h	15033;"	d
+RG_FFT_WDW_SHORT_SHIFT_SZ	include/ssv6200_aux.h	15035;"	d
+RG_FILTER_AVERAGE_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27649;"	d
+RG_FILTER_AVERAGE_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27647;"	d
+RG_FILTER_AVERAGE_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27646;"	d
+RG_FILTER_AVERAGE_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27648;"	d
+RG_FILTER_AVERAGE_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27650;"	d
+RG_FMT_DET_GF_TH_HI	include/ssv6200_aux.h	15064;"	d
+RG_FMT_DET_GF_TH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32539;"	d
+RG_FMT_DET_GF_TH_I_MSK	include/ssv6200_aux.h	15062;"	d
+RG_FMT_DET_GF_TH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32537;"	d
+RG_FMT_DET_GF_TH_MSK	include/ssv6200_aux.h	15061;"	d
+RG_FMT_DET_GF_TH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32536;"	d
+RG_FMT_DET_GF_TH_SFT	include/ssv6200_aux.h	15063;"	d
+RG_FMT_DET_GF_TH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32538;"	d
+RG_FMT_DET_GF_TH_SZ	include/ssv6200_aux.h	15065;"	d
+RG_FMT_DET_GF_TH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32540;"	d
+RG_FMT_DET_LENGTH_TH_HI	include/ssv6200_aux.h	15074;"	d
+RG_FMT_DET_LENGTH_TH_I_MSK	include/ssv6200_aux.h	15072;"	d
+RG_FMT_DET_LENGTH_TH_MSK	include/ssv6200_aux.h	15071;"	d
+RG_FMT_DET_LENGTH_TH_SFT	include/ssv6200_aux.h	15073;"	d
+RG_FMT_DET_LENGTH_TH_SZ	include/ssv6200_aux.h	15075;"	d
+RG_FMT_DET_MM_TH_HI	include/ssv6200_aux.h	15059;"	d
+RG_FMT_DET_MM_TH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32534;"	d
+RG_FMT_DET_MM_TH_I_MSK	include/ssv6200_aux.h	15057;"	d
+RG_FMT_DET_MM_TH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32532;"	d
+RG_FMT_DET_MM_TH_MSK	include/ssv6200_aux.h	15056;"	d
+RG_FMT_DET_MM_TH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32531;"	d
+RG_FMT_DET_MM_TH_SFT	include/ssv6200_aux.h	15058;"	d
+RG_FMT_DET_MM_TH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32533;"	d
+RG_FMT_DET_MM_TH_SZ	include/ssv6200_aux.h	15060;"	d
+RG_FMT_DET_MM_TH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32535;"	d
+RG_FORCE_11B_EN_HI	include/ssv6200_aux.h	13104;"	d
+RG_FORCE_11B_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30309;"	d
+RG_FORCE_11B_EN_I_MSK	include/ssv6200_aux.h	13102;"	d
+RG_FORCE_11B_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30307;"	d
+RG_FORCE_11B_EN_MSK	include/ssv6200_aux.h	13101;"	d
+RG_FORCE_11B_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30306;"	d
+RG_FORCE_11B_EN_SFT	include/ssv6200_aux.h	13103;"	d
+RG_FORCE_11B_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30308;"	d
+RG_FORCE_11B_EN_SZ	include/ssv6200_aux.h	13105;"	d
+RG_FORCE_11B_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30310;"	d
+RG_FORCE_11GN_EN_HI	include/ssv6200_aux.h	13099;"	d
+RG_FORCE_11GN_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30304;"	d
+RG_FORCE_11GN_EN_I_MSK	include/ssv6200_aux.h	13097;"	d
+RG_FORCE_11GN_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30302;"	d
+RG_FORCE_11GN_EN_MSK	include/ssv6200_aux.h	13096;"	d
+RG_FORCE_11GN_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30301;"	d
+RG_FORCE_11GN_EN_SFT	include/ssv6200_aux.h	13098;"	d
+RG_FORCE_11GN_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30303;"	d
+RG_FORCE_11GN_EN_SZ	include/ssv6200_aux.h	13100;"	d
+RG_FORCE_11GN_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30305;"	d
+RG_FPGA_80M_PH_STP_HI	include/ssv6200_aux.h	15714;"	d
+RG_FPGA_80M_PH_STP_I_MSK	include/ssv6200_aux.h	15712;"	d
+RG_FPGA_80M_PH_STP_MSK	include/ssv6200_aux.h	15711;"	d
+RG_FPGA_80M_PH_STP_SFT	include/ssv6200_aux.h	15713;"	d
+RG_FPGA_80M_PH_STP_SZ	include/ssv6200_aux.h	15715;"	d
+RG_FPGA_80M_PH_UP_HI	include/ssv6200_aux.h	15709;"	d
+RG_FPGA_80M_PH_UP_I_MSK	include/ssv6200_aux.h	15707;"	d
+RG_FPGA_80M_PH_UP_MSK	include/ssv6200_aux.h	15706;"	d
+RG_FPGA_80M_PH_UP_SFT	include/ssv6200_aux.h	15708;"	d
+RG_FPGA_80M_PH_UP_SZ	include/ssv6200_aux.h	15710;"	d
+RG_FPGA_CLK_REF_40M_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29834;"	d
+RG_FPGA_CLK_REF_40M_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29832;"	d
+RG_FPGA_CLK_REF_40M_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29831;"	d
+RG_FPGA_CLK_REF_40M_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29833;"	d
+RG_FPGA_CLK_REF_40M_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29835;"	d
+RG_GEMINIA_40M_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13464;"	d
+RG_GEMINIA_40M_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13462;"	d
+RG_GEMINIA_40M_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13461;"	d
+RG_GEMINIA_40M_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13463;"	d
+RG_GEMINIA_40M_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13465;"	d
+RG_GEMINIA_ADC_EDGE_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13504;"	d
+RG_GEMINIA_ADC_EDGE_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13502;"	d
+RG_GEMINIA_ADC_EDGE_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13501;"	d
+RG_GEMINIA_ADC_EDGE_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13503;"	d
+RG_GEMINIA_ADC_EDGE_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13505;"	d
+RG_GEMINIA_ALPHA_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13684;"	d
+RG_GEMINIA_ALPHA_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13682;"	d
+RG_GEMINIA_ALPHA_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13681;"	d
+RG_GEMINIA_ALPHA_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13683;"	d
+RG_GEMINIA_ALPHA_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13685;"	d
+RG_GEMINIA_BT_CLK32K_CAL_DONE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14004;"	d
+RG_GEMINIA_BT_CLK32K_CAL_DONE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14002;"	d
+RG_GEMINIA_BT_CLK32K_CAL_DONE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14001;"	d
+RG_GEMINIA_BT_CLK32K_CAL_DONE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14003;"	d
+RG_GEMINIA_BT_CLK32K_CAL_DONE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14005;"	d
+RG_GEMINIA_BT_CLK_SW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13999;"	d
+RG_GEMINIA_BT_CLK_SW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13997;"	d
+RG_GEMINIA_BT_CLK_SW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13996;"	d
+RG_GEMINIA_BT_CLK_SW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13998;"	d
+RG_GEMINIA_BT_CLK_SW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14000;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13084;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13082;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13081;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13083;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13085;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG10_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12984;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG10_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12982;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG10_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12981;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG10_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12983;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG10_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12985;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG11_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12974;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG11_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12972;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG11_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12971;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG11_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12973;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG11_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12975;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG12_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12964;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG12_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12962;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG12_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12961;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG12_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12963;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG12_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12965;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG13_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12954;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG13_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12952;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG13_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12951;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG13_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12953;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG13_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12955;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG14_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12944;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG14_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12942;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG14_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12941;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG14_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12943;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG14_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12945;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG15_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12934;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG15_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12932;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG15_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12931;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG15_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12933;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG15_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12935;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13074;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13072;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13071;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13073;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13075;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13064;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13062;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13061;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13063;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13065;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13054;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13052;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13051;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13053;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13055;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13044;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13042;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13041;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13043;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13045;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13034;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13032;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13031;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13033;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13035;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13024;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13022;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13021;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13023;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13025;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13014;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13012;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13011;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13013;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13015;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG8_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13004;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG8_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13002;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG8_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13001;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG8_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13003;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG8_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13005;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG9_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12994;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG9_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12992;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG9_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12991;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG9_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12993;"	d
+RG_GEMINIA_BT_IDACAI_TZ0_PGAG9_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12995;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13244;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13242;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13241;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13243;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13245;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG10_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13144;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG10_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13142;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG10_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13141;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG10_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13143;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG10_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13145;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG11_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13134;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG11_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13132;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG11_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13131;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG11_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13133;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG11_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13135;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG12_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13124;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG12_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13122;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG12_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13121;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG12_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13123;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG12_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13125;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG13_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13114;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG13_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13112;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG13_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13111;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG13_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13113;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG13_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13115;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG14_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13104;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG14_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13102;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG14_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13101;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG14_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13103;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG14_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13105;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG15_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13094;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG15_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13092;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG15_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13091;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG15_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13093;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG15_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13095;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13234;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13232;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13231;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13233;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13235;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13224;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13222;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13221;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13223;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13225;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13214;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13212;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13211;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13213;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13215;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13204;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13202;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13201;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13203;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13205;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13194;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13192;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13191;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13193;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13195;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13184;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13182;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13181;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13183;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13185;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13174;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13172;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13171;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13173;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13175;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG8_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13164;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG8_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13162;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG8_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13161;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG8_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13163;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG8_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13165;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG9_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13154;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG9_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13152;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG9_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13151;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG9_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13153;"	d
+RG_GEMINIA_BT_IDACAI_TZ1_PGAG9_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13155;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13089;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13087;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13086;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13088;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13090;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG10_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12989;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG10_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12987;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG10_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12986;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG10_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12988;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG10_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12990;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG11_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12979;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG11_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12977;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG11_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12976;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG11_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12978;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG11_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12980;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG12_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12969;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG12_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12967;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG12_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12966;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG12_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12968;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG12_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12970;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG13_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12959;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG13_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12957;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG13_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12956;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG13_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12958;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG13_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12960;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG14_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12949;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG14_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12947;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG14_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12946;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG14_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12948;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG14_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12950;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG15_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12939;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG15_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12937;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG15_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12936;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG15_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12938;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG15_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12940;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13079;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13077;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13076;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13078;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13080;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13069;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13067;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13066;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13068;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13070;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13059;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13057;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13056;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13058;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13060;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13049;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13047;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13046;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13048;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13050;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13039;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13037;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13036;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13038;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13040;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13029;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13027;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13026;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13028;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13030;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13019;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13017;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13016;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13018;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13020;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG8_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13009;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG8_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13007;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG8_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13006;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG8_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13008;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG8_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13010;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG9_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12999;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG9_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12997;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG9_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12996;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG9_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12998;"	d
+RG_GEMINIA_BT_IDACAQ_TZ0_PGAG9_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13000;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13249;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13247;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13246;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13248;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13250;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG10_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13149;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG10_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13147;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG10_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13146;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG10_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13148;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG10_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13150;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG11_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13139;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG11_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13137;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG11_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13136;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG11_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13138;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG11_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13140;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG12_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13129;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG12_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13127;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG12_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13126;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG12_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13128;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG12_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13130;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG13_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13119;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG13_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13117;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG13_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13116;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG13_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13118;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG13_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13120;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG14_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13109;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG14_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13107;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG14_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13106;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG14_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13108;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG14_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13110;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG15_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13099;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG15_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13097;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG15_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13096;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG15_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13098;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG15_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13100;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13239;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13237;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13236;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13238;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13240;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13229;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13227;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13226;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13228;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13230;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13219;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13217;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13216;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13218;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13220;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13209;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13207;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13206;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13208;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13210;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13199;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13197;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13196;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13198;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13200;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13189;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13187;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13186;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13188;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13190;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13179;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13177;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13176;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13178;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13180;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG8_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13169;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG8_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13167;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG8_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13166;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG8_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13168;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG8_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13170;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG9_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13159;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG9_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13157;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG9_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13156;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG9_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13158;"	d
+RG_GEMINIA_BT_IDACAQ_TZ1_PGAG9_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13160;"	d
+RG_GEMINIA_BT_PABIAS_2X_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10904;"	d
+RG_GEMINIA_BT_PABIAS_2X_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10902;"	d
+RG_GEMINIA_BT_PABIAS_2X_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10901;"	d
+RG_GEMINIA_BT_PABIAS_2X_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10903;"	d
+RG_GEMINIA_BT_PABIAS_2X_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10905;"	d
+RG_GEMINIA_BT_PABIAS_CTRL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10909;"	d
+RG_GEMINIA_BT_PABIAS_CTRL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10907;"	d
+RG_GEMINIA_BT_PABIAS_CTRL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10906;"	d
+RG_GEMINIA_BT_PABIAS_CTRL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10908;"	d
+RG_GEMINIA_BT_PABIAS_CTRL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10910;"	d
+RG_GEMINIA_BT_PA_CAPSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10899;"	d
+RG_GEMINIA_BT_PA_CAPSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10897;"	d
+RG_GEMINIA_BT_PA_CAPSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10896;"	d
+RG_GEMINIA_BT_PA_CAPSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10898;"	d
+RG_GEMINIA_BT_PA_CAPSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10900;"	d
+RG_GEMINIA_BT_RX_ABBCFIX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10729;"	d
+RG_GEMINIA_BT_RX_ABBCFIX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10727;"	d
+RG_GEMINIA_BT_RX_ABBCFIX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10726;"	d
+RG_GEMINIA_BT_RX_ABBCFIX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10728;"	d
+RG_GEMINIA_BT_RX_ABBCFIX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10730;"	d
+RG_GEMINIA_BT_RX_ABBCTUNEI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10699;"	d
+RG_GEMINIA_BT_RX_ABBCTUNEI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10697;"	d
+RG_GEMINIA_BT_RX_ABBCTUNEI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10696;"	d
+RG_GEMINIA_BT_RX_ABBCTUNEI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10698;"	d
+RG_GEMINIA_BT_RX_ABBCTUNEI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10700;"	d
+RG_GEMINIA_BT_RX_ABBCTUNEQ_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10704;"	d
+RG_GEMINIA_BT_RX_ABBCTUNEQ_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10702;"	d
+RG_GEMINIA_BT_RX_ABBCTUNEQ_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10701;"	d
+RG_GEMINIA_BT_RX_ABBCTUNEQ_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10703;"	d
+RG_GEMINIA_BT_RX_ABBCTUNEQ_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10705;"	d
+RG_GEMINIA_BT_RX_ABB_BT_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10739;"	d
+RG_GEMINIA_BT_RX_ABB_BT_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10737;"	d
+RG_GEMINIA_BT_RX_ABB_BT_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10736;"	d
+RG_GEMINIA_BT_RX_ABB_BT_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10738;"	d
+RG_GEMINIA_BT_RX_ABB_BT_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10740;"	d
+RG_GEMINIA_BT_RX_ABB_IDIV3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10744;"	d
+RG_GEMINIA_BT_RX_ABB_IDIV3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10742;"	d
+RG_GEMINIA_BT_RX_ABB_IDIV3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10741;"	d
+RG_GEMINIA_BT_RX_ABB_IDIV3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10743;"	d
+RG_GEMINIA_BT_RX_ABB_IDIV3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10745;"	d
+RG_GEMINIA_BT_RX_ABB_N_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10734;"	d
+RG_GEMINIA_BT_RX_ABB_N_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10732;"	d
+RG_GEMINIA_BT_RX_ABB_N_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10731;"	d
+RG_GEMINIA_BT_RX_ABB_N_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10733;"	d
+RG_GEMINIA_BT_RX_ABB_N_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10735;"	d
+RG_GEMINIA_BT_RX_ADC_CLOAD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11459;"	d
+RG_GEMINIA_BT_RX_ADC_CLOAD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11457;"	d
+RG_GEMINIA_BT_RX_ADC_CLOAD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11456;"	d
+RG_GEMINIA_BT_RX_ADC_CLOAD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11458;"	d
+RG_GEMINIA_BT_RX_ADC_CLOAD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11460;"	d
+RG_GEMINIA_BT_RX_ADC_ICMP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11449;"	d
+RG_GEMINIA_BT_RX_ADC_ICMP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11447;"	d
+RG_GEMINIA_BT_RX_ADC_ICMP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11446;"	d
+RG_GEMINIA_BT_RX_ADC_ICMP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11448;"	d
+RG_GEMINIA_BT_RX_ADC_ICMP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11450;"	d
+RG_GEMINIA_BT_RX_ADC_VCMI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11454;"	d
+RG_GEMINIA_BT_RX_ADC_VCMI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11452;"	d
+RG_GEMINIA_BT_RX_ADC_VCMI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11451;"	d
+RG_GEMINIA_BT_RX_ADC_VCMI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11453;"	d
+RG_GEMINIA_BT_RX_ADC_VCMI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11455;"	d
+RG_GEMINIA_BT_RX_DCCAL_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13329;"	d
+RG_GEMINIA_BT_RX_DCCAL_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13327;"	d
+RG_GEMINIA_BT_RX_DCCAL_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13326;"	d
+RG_GEMINIA_BT_RX_DCCAL_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13328;"	d
+RG_GEMINIA_BT_RX_DCCAL_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13330;"	d
+RG_GEMINIA_BT_RX_EN_IDACA_COARSE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10749;"	d
+RG_GEMINIA_BT_RX_EN_IDACA_COARSE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10747;"	d
+RG_GEMINIA_BT_RX_EN_IDACA_COARSE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10746;"	d
+RG_GEMINIA_BT_RX_EN_IDACA_COARSE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10748;"	d
+RG_GEMINIA_BT_RX_EN_IDACA_COARSE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10750;"	d
+RG_GEMINIA_BT_RX_EN_LOOPA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10754;"	d
+RG_GEMINIA_BT_RX_EN_LOOPA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10752;"	d
+RG_GEMINIA_BT_RX_EN_LOOPA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10751;"	d
+RG_GEMINIA_BT_RX_EN_LOOPA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10753;"	d
+RG_GEMINIA_BT_RX_EN_LOOPA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10755;"	d
+RG_GEMINIA_BT_RX_FILTERI1ST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10714;"	d
+RG_GEMINIA_BT_RX_FILTERI1ST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10712;"	d
+RG_GEMINIA_BT_RX_FILTERI1ST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10711;"	d
+RG_GEMINIA_BT_RX_FILTERI1ST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10713;"	d
+RG_GEMINIA_BT_RX_FILTERI1ST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10715;"	d
+RG_GEMINIA_BT_RX_FILTERI2ND_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10719;"	d
+RG_GEMINIA_BT_RX_FILTERI2ND_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10717;"	d
+RG_GEMINIA_BT_RX_FILTERI2ND_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10716;"	d
+RG_GEMINIA_BT_RX_FILTERI2ND_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10718;"	d
+RG_GEMINIA_BT_RX_FILTERI2ND_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10720;"	d
+RG_GEMINIA_BT_RX_FILTERI3RD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10724;"	d
+RG_GEMINIA_BT_RX_FILTERI3RD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10722;"	d
+RG_GEMINIA_BT_RX_FILTERI3RD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10721;"	d
+RG_GEMINIA_BT_RX_FILTERI3RD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10723;"	d
+RG_GEMINIA_BT_RX_FILTERI3RD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10725;"	d
+RG_GEMINIA_BT_RX_FILTERI_COARSE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10709;"	d
+RG_GEMINIA_BT_RX_FILTERI_COARSE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10707;"	d
+RG_GEMINIA_BT_RX_FILTERI_COARSE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10706;"	d
+RG_GEMINIA_BT_RX_FILTERI_COARSE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10708;"	d
+RG_GEMINIA_BT_RX_FILTERI_COARSE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10710;"	d
+RG_GEMINIA_BT_RX_FILTERVCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10759;"	d
+RG_GEMINIA_BT_RX_FILTERVCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10757;"	d
+RG_GEMINIA_BT_RX_FILTERVCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10756;"	d
+RG_GEMINIA_BT_RX_FILTERVCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10758;"	d
+RG_GEMINIA_BT_RX_FILTERVCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10760;"	d
+RG_GEMINIA_BT_RX_HG_DIV2_CORE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11224;"	d
+RG_GEMINIA_BT_RX_HG_DIV2_CORE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11222;"	d
+RG_GEMINIA_BT_RX_HG_DIV2_CORE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11221;"	d
+RG_GEMINIA_BT_RX_HG_DIV2_CORE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11223;"	d
+RG_GEMINIA_BT_RX_HG_DIV2_CORE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11225;"	d
+RG_GEMINIA_BT_RX_HG_LNAHGN_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11199;"	d
+RG_GEMINIA_BT_RX_HG_LNAHGN_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11197;"	d
+RG_GEMINIA_BT_RX_HG_LNAHGN_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11196;"	d
+RG_GEMINIA_BT_RX_HG_LNAHGN_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11198;"	d
+RG_GEMINIA_BT_RX_HG_LNAHGN_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11200;"	d
+RG_GEMINIA_BT_RX_HG_LNAHGP_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11204;"	d
+RG_GEMINIA_BT_RX_HG_LNAHGP_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11202;"	d
+RG_GEMINIA_BT_RX_HG_LNAHGP_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11201;"	d
+RG_GEMINIA_BT_RX_HG_LNAHGP_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11203;"	d
+RG_GEMINIA_BT_RX_HG_LNAHGP_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11205;"	d
+RG_GEMINIA_BT_RX_HG_LNALG_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11209;"	d
+RG_GEMINIA_BT_RX_HG_LNALG_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11207;"	d
+RG_GEMINIA_BT_RX_HG_LNALG_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11206;"	d
+RG_GEMINIA_BT_RX_HG_LNALG_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11208;"	d
+RG_GEMINIA_BT_RX_HG_LNALG_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11210;"	d
+RG_GEMINIA_BT_RX_HG_LNA_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11189;"	d
+RG_GEMINIA_BT_RX_HG_LNA_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11187;"	d
+RG_GEMINIA_BT_RX_HG_LNA_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11186;"	d
+RG_GEMINIA_BT_RX_HG_LNA_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11188;"	d
+RG_GEMINIA_BT_RX_HG_LNA_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11190;"	d
+RG_GEMINIA_BT_RX_HG_LOBUF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11229;"	d
+RG_GEMINIA_BT_RX_HG_LOBUF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11227;"	d
+RG_GEMINIA_BT_RX_HG_LOBUF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11226;"	d
+RG_GEMINIA_BT_RX_HG_LOBUF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11228;"	d
+RG_GEMINIA_BT_RX_HG_LOBUF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11230;"	d
+RG_GEMINIA_BT_RX_HG_SQDC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11219;"	d
+RG_GEMINIA_BT_RX_HG_SQDC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11217;"	d
+RG_GEMINIA_BT_RX_HG_SQDC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11216;"	d
+RG_GEMINIA_BT_RX_HG_SQDC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11218;"	d
+RG_GEMINIA_BT_RX_HG_SQDC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11220;"	d
+RG_GEMINIA_BT_RX_HG_TZI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11234;"	d
+RG_GEMINIA_BT_RX_HG_TZI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11232;"	d
+RG_GEMINIA_BT_RX_HG_TZI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11231;"	d
+RG_GEMINIA_BT_RX_HG_TZI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11233;"	d
+RG_GEMINIA_BT_RX_HG_TZI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11235;"	d
+RG_GEMINIA_BT_RX_HG_TZ_CAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11214;"	d
+RG_GEMINIA_BT_RX_HG_TZ_CAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11212;"	d
+RG_GEMINIA_BT_RX_HG_TZ_CAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11211;"	d
+RG_GEMINIA_BT_RX_HG_TZ_CAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11213;"	d
+RG_GEMINIA_BT_RX_HG_TZ_CAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11215;"	d
+RG_GEMINIA_BT_RX_HG_TZ_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11194;"	d
+RG_GEMINIA_BT_RX_HG_TZ_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11192;"	d
+RG_GEMINIA_BT_RX_HG_TZ_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11191;"	d
+RG_GEMINIA_BT_RX_HG_TZ_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11193;"	d
+RG_GEMINIA_BT_RX_HG_TZ_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11195;"	d
+RG_GEMINIA_BT_RX_HG_TZ_VCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11239;"	d
+RG_GEMINIA_BT_RX_HG_TZ_VCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11237;"	d
+RG_GEMINIA_BT_RX_HG_TZ_VCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11236;"	d
+RG_GEMINIA_BT_RX_HG_TZ_VCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11238;"	d
+RG_GEMINIA_BT_RX_HG_TZ_VCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11240;"	d
+RG_GEMINIA_BT_RX_LG_DIV2_CORE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11334;"	d
+RG_GEMINIA_BT_RX_LG_DIV2_CORE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11332;"	d
+RG_GEMINIA_BT_RX_LG_DIV2_CORE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11331;"	d
+RG_GEMINIA_BT_RX_LG_DIV2_CORE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11333;"	d
+RG_GEMINIA_BT_RX_LG_DIV2_CORE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11335;"	d
+RG_GEMINIA_BT_RX_LG_LNAHGN_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11309;"	d
+RG_GEMINIA_BT_RX_LG_LNAHGN_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11307;"	d
+RG_GEMINIA_BT_RX_LG_LNAHGN_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11306;"	d
+RG_GEMINIA_BT_RX_LG_LNAHGN_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11308;"	d
+RG_GEMINIA_BT_RX_LG_LNAHGN_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11310;"	d
+RG_GEMINIA_BT_RX_LG_LNAHGP_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11314;"	d
+RG_GEMINIA_BT_RX_LG_LNAHGP_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11312;"	d
+RG_GEMINIA_BT_RX_LG_LNAHGP_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11311;"	d
+RG_GEMINIA_BT_RX_LG_LNAHGP_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11313;"	d
+RG_GEMINIA_BT_RX_LG_LNAHGP_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11315;"	d
+RG_GEMINIA_BT_RX_LG_LNALG_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11319;"	d
+RG_GEMINIA_BT_RX_LG_LNALG_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11317;"	d
+RG_GEMINIA_BT_RX_LG_LNALG_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11316;"	d
+RG_GEMINIA_BT_RX_LG_LNALG_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11318;"	d
+RG_GEMINIA_BT_RX_LG_LNALG_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11320;"	d
+RG_GEMINIA_BT_RX_LG_LNA_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11299;"	d
+RG_GEMINIA_BT_RX_LG_LNA_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11297;"	d
+RG_GEMINIA_BT_RX_LG_LNA_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11296;"	d
+RG_GEMINIA_BT_RX_LG_LNA_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11298;"	d
+RG_GEMINIA_BT_RX_LG_LNA_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11300;"	d
+RG_GEMINIA_BT_RX_LG_LOBUF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11339;"	d
+RG_GEMINIA_BT_RX_LG_LOBUF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11337;"	d
+RG_GEMINIA_BT_RX_LG_LOBUF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11336;"	d
+RG_GEMINIA_BT_RX_LG_LOBUF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11338;"	d
+RG_GEMINIA_BT_RX_LG_LOBUF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11340;"	d
+RG_GEMINIA_BT_RX_LG_SQDC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11329;"	d
+RG_GEMINIA_BT_RX_LG_SQDC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11327;"	d
+RG_GEMINIA_BT_RX_LG_SQDC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11326;"	d
+RG_GEMINIA_BT_RX_LG_SQDC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11328;"	d
+RG_GEMINIA_BT_RX_LG_SQDC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11330;"	d
+RG_GEMINIA_BT_RX_LG_TZI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11344;"	d
+RG_GEMINIA_BT_RX_LG_TZI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11342;"	d
+RG_GEMINIA_BT_RX_LG_TZI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11341;"	d
+RG_GEMINIA_BT_RX_LG_TZI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11343;"	d
+RG_GEMINIA_BT_RX_LG_TZI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11345;"	d
+RG_GEMINIA_BT_RX_LG_TZ_CAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11324;"	d
+RG_GEMINIA_BT_RX_LG_TZ_CAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11322;"	d
+RG_GEMINIA_BT_RX_LG_TZ_CAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11321;"	d
+RG_GEMINIA_BT_RX_LG_TZ_CAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11323;"	d
+RG_GEMINIA_BT_RX_LG_TZ_CAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11325;"	d
+RG_GEMINIA_BT_RX_LG_TZ_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11304;"	d
+RG_GEMINIA_BT_RX_LG_TZ_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11302;"	d
+RG_GEMINIA_BT_RX_LG_TZ_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11301;"	d
+RG_GEMINIA_BT_RX_LG_TZ_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11303;"	d
+RG_GEMINIA_BT_RX_LG_TZ_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11305;"	d
+RG_GEMINIA_BT_RX_LG_TZ_VCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11349;"	d
+RG_GEMINIA_BT_RX_LG_TZ_VCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11347;"	d
+RG_GEMINIA_BT_RX_LG_TZ_VCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11346;"	d
+RG_GEMINIA_BT_RX_LG_TZ_VCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11348;"	d
+RG_GEMINIA_BT_RX_LG_TZ_VCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11350;"	d
+RG_GEMINIA_BT_RX_MG_DIV2_CORE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11279;"	d
+RG_GEMINIA_BT_RX_MG_DIV2_CORE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11277;"	d
+RG_GEMINIA_BT_RX_MG_DIV2_CORE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11276;"	d
+RG_GEMINIA_BT_RX_MG_DIV2_CORE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11278;"	d
+RG_GEMINIA_BT_RX_MG_DIV2_CORE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11280;"	d
+RG_GEMINIA_BT_RX_MG_LNAHGN_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11254;"	d
+RG_GEMINIA_BT_RX_MG_LNAHGN_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11252;"	d
+RG_GEMINIA_BT_RX_MG_LNAHGN_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11251;"	d
+RG_GEMINIA_BT_RX_MG_LNAHGN_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11253;"	d
+RG_GEMINIA_BT_RX_MG_LNAHGN_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11255;"	d
+RG_GEMINIA_BT_RX_MG_LNAHGP_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11259;"	d
+RG_GEMINIA_BT_RX_MG_LNAHGP_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11257;"	d
+RG_GEMINIA_BT_RX_MG_LNAHGP_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11256;"	d
+RG_GEMINIA_BT_RX_MG_LNAHGP_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11258;"	d
+RG_GEMINIA_BT_RX_MG_LNAHGP_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11260;"	d
+RG_GEMINIA_BT_RX_MG_LNALG_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11264;"	d
+RG_GEMINIA_BT_RX_MG_LNALG_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11262;"	d
+RG_GEMINIA_BT_RX_MG_LNALG_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11261;"	d
+RG_GEMINIA_BT_RX_MG_LNALG_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11263;"	d
+RG_GEMINIA_BT_RX_MG_LNALG_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11265;"	d
+RG_GEMINIA_BT_RX_MG_LNA_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11244;"	d
+RG_GEMINIA_BT_RX_MG_LNA_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11242;"	d
+RG_GEMINIA_BT_RX_MG_LNA_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11241;"	d
+RG_GEMINIA_BT_RX_MG_LNA_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11243;"	d
+RG_GEMINIA_BT_RX_MG_LNA_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11245;"	d
+RG_GEMINIA_BT_RX_MG_LOBUF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11284;"	d
+RG_GEMINIA_BT_RX_MG_LOBUF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11282;"	d
+RG_GEMINIA_BT_RX_MG_LOBUF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11281;"	d
+RG_GEMINIA_BT_RX_MG_LOBUF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11283;"	d
+RG_GEMINIA_BT_RX_MG_LOBUF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11285;"	d
+RG_GEMINIA_BT_RX_MG_SQDC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11274;"	d
+RG_GEMINIA_BT_RX_MG_SQDC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11272;"	d
+RG_GEMINIA_BT_RX_MG_SQDC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11271;"	d
+RG_GEMINIA_BT_RX_MG_SQDC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11273;"	d
+RG_GEMINIA_BT_RX_MG_SQDC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11275;"	d
+RG_GEMINIA_BT_RX_MG_TZI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11289;"	d
+RG_GEMINIA_BT_RX_MG_TZI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11287;"	d
+RG_GEMINIA_BT_RX_MG_TZI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11286;"	d
+RG_GEMINIA_BT_RX_MG_TZI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11288;"	d
+RG_GEMINIA_BT_RX_MG_TZI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11290;"	d
+RG_GEMINIA_BT_RX_MG_TZ_CAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11269;"	d
+RG_GEMINIA_BT_RX_MG_TZ_CAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11267;"	d
+RG_GEMINIA_BT_RX_MG_TZ_CAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11266;"	d
+RG_GEMINIA_BT_RX_MG_TZ_CAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11268;"	d
+RG_GEMINIA_BT_RX_MG_TZ_CAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11270;"	d
+RG_GEMINIA_BT_RX_MG_TZ_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11249;"	d
+RG_GEMINIA_BT_RX_MG_TZ_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11247;"	d
+RG_GEMINIA_BT_RX_MG_TZ_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11246;"	d
+RG_GEMINIA_BT_RX_MG_TZ_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11248;"	d
+RG_GEMINIA_BT_RX_MG_TZ_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11250;"	d
+RG_GEMINIA_BT_RX_MG_TZ_VCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11294;"	d
+RG_GEMINIA_BT_RX_MG_TZ_VCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11292;"	d
+RG_GEMINIA_BT_RX_MG_TZ_VCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11291;"	d
+RG_GEMINIA_BT_RX_MG_TZ_VCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11293;"	d
+RG_GEMINIA_BT_RX_MG_TZ_VCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11295;"	d
+RG_GEMINIA_BT_RX_OUTVCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10764;"	d
+RG_GEMINIA_BT_RX_OUTVCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10762;"	d
+RG_GEMINIA_BT_RX_OUTVCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10761;"	d
+RG_GEMINIA_BT_RX_OUTVCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10763;"	d
+RG_GEMINIA_BT_RX_OUTVCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10765;"	d
+RG_GEMINIA_BT_RX_ULG_DIV2_CORE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11389;"	d
+RG_GEMINIA_BT_RX_ULG_DIV2_CORE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11387;"	d
+RG_GEMINIA_BT_RX_ULG_DIV2_CORE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11386;"	d
+RG_GEMINIA_BT_RX_ULG_DIV2_CORE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11388;"	d
+RG_GEMINIA_BT_RX_ULG_DIV2_CORE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11390;"	d
+RG_GEMINIA_BT_RX_ULG_LNAHGN_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11364;"	d
+RG_GEMINIA_BT_RX_ULG_LNAHGN_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11362;"	d
+RG_GEMINIA_BT_RX_ULG_LNAHGN_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11361;"	d
+RG_GEMINIA_BT_RX_ULG_LNAHGN_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11363;"	d
+RG_GEMINIA_BT_RX_ULG_LNAHGN_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11365;"	d
+RG_GEMINIA_BT_RX_ULG_LNAHGP_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11369;"	d
+RG_GEMINIA_BT_RX_ULG_LNAHGP_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11367;"	d
+RG_GEMINIA_BT_RX_ULG_LNAHGP_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11366;"	d
+RG_GEMINIA_BT_RX_ULG_LNAHGP_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11368;"	d
+RG_GEMINIA_BT_RX_ULG_LNAHGP_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11370;"	d
+RG_GEMINIA_BT_RX_ULG_LNALG_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11374;"	d
+RG_GEMINIA_BT_RX_ULG_LNALG_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11372;"	d
+RG_GEMINIA_BT_RX_ULG_LNALG_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11371;"	d
+RG_GEMINIA_BT_RX_ULG_LNALG_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11373;"	d
+RG_GEMINIA_BT_RX_ULG_LNALG_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11375;"	d
+RG_GEMINIA_BT_RX_ULG_LNA_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11354;"	d
+RG_GEMINIA_BT_RX_ULG_LNA_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11352;"	d
+RG_GEMINIA_BT_RX_ULG_LNA_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11351;"	d
+RG_GEMINIA_BT_RX_ULG_LNA_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11353;"	d
+RG_GEMINIA_BT_RX_ULG_LNA_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11355;"	d
+RG_GEMINIA_BT_RX_ULG_LOBUF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11394;"	d
+RG_GEMINIA_BT_RX_ULG_LOBUF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11392;"	d
+RG_GEMINIA_BT_RX_ULG_LOBUF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11391;"	d
+RG_GEMINIA_BT_RX_ULG_LOBUF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11393;"	d
+RG_GEMINIA_BT_RX_ULG_LOBUF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11395;"	d
+RG_GEMINIA_BT_RX_ULG_SQDC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11384;"	d
+RG_GEMINIA_BT_RX_ULG_SQDC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11382;"	d
+RG_GEMINIA_BT_RX_ULG_SQDC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11381;"	d
+RG_GEMINIA_BT_RX_ULG_SQDC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11383;"	d
+RG_GEMINIA_BT_RX_ULG_SQDC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11385;"	d
+RG_GEMINIA_BT_RX_ULG_TZI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11399;"	d
+RG_GEMINIA_BT_RX_ULG_TZI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11397;"	d
+RG_GEMINIA_BT_RX_ULG_TZI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11396;"	d
+RG_GEMINIA_BT_RX_ULG_TZI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11398;"	d
+RG_GEMINIA_BT_RX_ULG_TZI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11400;"	d
+RG_GEMINIA_BT_RX_ULG_TZ_CAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11379;"	d
+RG_GEMINIA_BT_RX_ULG_TZ_CAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11377;"	d
+RG_GEMINIA_BT_RX_ULG_TZ_CAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11376;"	d
+RG_GEMINIA_BT_RX_ULG_TZ_CAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11378;"	d
+RG_GEMINIA_BT_RX_ULG_TZ_CAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11380;"	d
+RG_GEMINIA_BT_RX_ULG_TZ_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11359;"	d
+RG_GEMINIA_BT_RX_ULG_TZ_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11357;"	d
+RG_GEMINIA_BT_RX_ULG_TZ_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11356;"	d
+RG_GEMINIA_BT_RX_ULG_TZ_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11358;"	d
+RG_GEMINIA_BT_RX_ULG_TZ_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11360;"	d
+RG_GEMINIA_BT_RX_ULG_TZ_VCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11404;"	d
+RG_GEMINIA_BT_RX_ULG_TZ_VCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11402;"	d
+RG_GEMINIA_BT_RX_ULG_TZ_VCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11401;"	d
+RG_GEMINIA_BT_RX_ULG_TZ_VCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11403;"	d
+RG_GEMINIA_BT_RX_ULG_TZ_VCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11405;"	d
+RG_GEMINIA_BT_TXLPF_BOOSTI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11584;"	d
+RG_GEMINIA_BT_TXLPF_BOOSTI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11582;"	d
+RG_GEMINIA_BT_TXLPF_BOOSTI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11581;"	d
+RG_GEMINIA_BT_TXLPF_BOOSTI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11583;"	d
+RG_GEMINIA_BT_TXLPF_BOOSTI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11585;"	d
+RG_GEMINIA_BT_TXPGA_CAPSW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10854;"	d
+RG_GEMINIA_BT_TXPGA_CAPSW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10852;"	d
+RG_GEMINIA_BT_TXPGA_CAPSW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10851;"	d
+RG_GEMINIA_BT_TXPGA_CAPSW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10853;"	d
+RG_GEMINIA_BT_TXPGA_CAPSW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10855;"	d
+RG_GEMINIA_BT_TX_DACI1ST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11554;"	d
+RG_GEMINIA_BT_TX_DACI1ST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11552;"	d
+RG_GEMINIA_BT_TX_DACI1ST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11551;"	d
+RG_GEMINIA_BT_TX_DACI1ST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11553;"	d
+RG_GEMINIA_BT_TX_DACI1ST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11555;"	d
+RG_GEMINIA_BT_TX_DACLPF_ICOARSE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11559;"	d
+RG_GEMINIA_BT_TX_DACLPF_ICOARSE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11557;"	d
+RG_GEMINIA_BT_TX_DACLPF_ICOARSE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11556;"	d
+RG_GEMINIA_BT_TX_DACLPF_ICOARSE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11558;"	d
+RG_GEMINIA_BT_TX_DACLPF_ICOARSE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11560;"	d
+RG_GEMINIA_BT_TX_DACLPF_IFINE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11564;"	d
+RG_GEMINIA_BT_TX_DACLPF_IFINE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11562;"	d
+RG_GEMINIA_BT_TX_DACLPF_IFINE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11561;"	d
+RG_GEMINIA_BT_TX_DACLPF_IFINE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11563;"	d
+RG_GEMINIA_BT_TX_DACLPF_IFINE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11565;"	d
+RG_GEMINIA_BT_TX_DACLPF_VCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11569;"	d
+RG_GEMINIA_BT_TX_DACLPF_VCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11567;"	d
+RG_GEMINIA_BT_TX_DACLPF_VCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11566;"	d
+RG_GEMINIA_BT_TX_DACLPF_VCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11568;"	d
+RG_GEMINIA_BT_TX_DACLPF_VCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11570;"	d
+RG_GEMINIA_BT_TX_DAC_CKEDGE_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11594;"	d
+RG_GEMINIA_BT_TX_DAC_CKEDGE_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11592;"	d
+RG_GEMINIA_BT_TX_DAC_CKEDGE_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11591;"	d
+RG_GEMINIA_BT_TX_DAC_CKEDGE_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11593;"	d
+RG_GEMINIA_BT_TX_DAC_CKEDGE_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11595;"	d
+RG_GEMINIA_BT_TX_DAC_IATTN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11579;"	d
+RG_GEMINIA_BT_TX_DAC_IATTN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11577;"	d
+RG_GEMINIA_BT_TX_DAC_IATTN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11576;"	d
+RG_GEMINIA_BT_TX_DAC_IATTN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11578;"	d
+RG_GEMINIA_BT_TX_DAC_IATTN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11580;"	d
+RG_GEMINIA_BT_TX_DAC_IBIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11574;"	d
+RG_GEMINIA_BT_TX_DAC_IBIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11572;"	d
+RG_GEMINIA_BT_TX_DAC_IBIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11571;"	d
+RG_GEMINIA_BT_TX_DAC_IBIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11573;"	d
+RG_GEMINIA_BT_TX_DAC_IBIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11575;"	d
+RG_GEMINIA_BT_TX_DAC_IOFFSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11604;"	d
+RG_GEMINIA_BT_TX_DAC_IOFFSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11602;"	d
+RG_GEMINIA_BT_TX_DAC_IOFFSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11601;"	d
+RG_GEMINIA_BT_TX_DAC_IOFFSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11603;"	d
+RG_GEMINIA_BT_TX_DAC_IOFFSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11605;"	d
+RG_GEMINIA_BT_TX_DAC_OS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11599;"	d
+RG_GEMINIA_BT_TX_DAC_OS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11597;"	d
+RG_GEMINIA_BT_TX_DAC_OS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11596;"	d
+RG_GEMINIA_BT_TX_DAC_OS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11598;"	d
+RG_GEMINIA_BT_TX_DAC_OS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11600;"	d
+RG_GEMINIA_BT_TX_DAC_QOFFSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11609;"	d
+RG_GEMINIA_BT_TX_DAC_QOFFSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11607;"	d
+RG_GEMINIA_BT_TX_DAC_QOFFSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11606;"	d
+RG_GEMINIA_BT_TX_DAC_QOFFSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11608;"	d
+RG_GEMINIA_BT_TX_DAC_QOFFSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11610;"	d
+RG_GEMINIA_BT_TX_DAC_RCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11589;"	d
+RG_GEMINIA_BT_TX_DAC_RCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11587;"	d
+RG_GEMINIA_BT_TX_DAC_RCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11586;"	d
+RG_GEMINIA_BT_TX_DAC_RCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11588;"	d
+RG_GEMINIA_BT_TX_DAC_RCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11590;"	d
+RG_GEMINIA_BT_TX_DIV_VSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10859;"	d
+RG_GEMINIA_BT_TX_DIV_VSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10857;"	d
+RG_GEMINIA_BT_TX_DIV_VSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10856;"	d
+RG_GEMINIA_BT_TX_DIV_VSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10858;"	d
+RG_GEMINIA_BT_TX_DIV_VSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10860;"	d
+RG_GEMINIA_BT_TX_GAIN_OFFSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10944;"	d
+RG_GEMINIA_BT_TX_GAIN_OFFSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10942;"	d
+RG_GEMINIA_BT_TX_GAIN_OFFSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10941;"	d
+RG_GEMINIA_BT_TX_GAIN_OFFSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10943;"	d
+RG_GEMINIA_BT_TX_GAIN_OFFSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10945;"	d
+RG_GEMINIA_BT_TX_LOBUF_VSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10864;"	d
+RG_GEMINIA_BT_TX_LOBUF_VSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10862;"	d
+RG_GEMINIA_BT_TX_LOBUF_VSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10861;"	d
+RG_GEMINIA_BT_TX_LOBUF_VSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10863;"	d
+RG_GEMINIA_BT_TX_LOBUF_VSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10865;"	d
+RG_GEMINIA_BT_TX_PA_VCAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10914;"	d
+RG_GEMINIA_BT_TX_PA_VCAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10912;"	d
+RG_GEMINIA_BT_TX_PA_VCAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10911;"	d
+RG_GEMINIA_BT_TX_PA_VCAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10913;"	d
+RG_GEMINIA_BT_TX_PA_VCAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10915;"	d
+RG_GEMINIA_BT_TX_VDDSW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10869;"	d
+RG_GEMINIA_BT_TX_VDDSW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10867;"	d
+RG_GEMINIA_BT_TX_VDDSW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10866;"	d
+RG_GEMINIA_BT_TX_VDDSW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10868;"	d
+RG_GEMINIA_BT_TX_VDDSW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10870;"	d
+RG_GEMINIA_BUCK_EN_PSM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13899;"	d
+RG_GEMINIA_BUCK_EN_PSM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13897;"	d
+RG_GEMINIA_BUCK_EN_PSM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13896;"	d
+RG_GEMINIA_BUCK_EN_PSM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13898;"	d
+RG_GEMINIA_BUCK_EN_PSM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13900;"	d
+RG_GEMINIA_BUCK_LEVEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13884;"	d
+RG_GEMINIA_BUCK_LEVEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13882;"	d
+RG_GEMINIA_BUCK_LEVEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13881;"	d
+RG_GEMINIA_BUCK_LEVEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13883;"	d
+RG_GEMINIA_BUCK_LEVEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13885;"	d
+RG_GEMINIA_BUCK_PSM_VTH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13904;"	d
+RG_GEMINIA_BUCK_PSM_VTH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13902;"	d
+RG_GEMINIA_BUCK_PSM_VTH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13901;"	d
+RG_GEMINIA_BUCK_PSM_VTH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13903;"	d
+RG_GEMINIA_BUCK_PSM_VTH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13905;"	d
+RG_GEMINIA_BUCK_VREF_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13909;"	d
+RG_GEMINIA_BUCK_VREF_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13907;"	d
+RG_GEMINIA_BUCK_VREF_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13906;"	d
+RG_GEMINIA_BUCK_VREF_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13908;"	d
+RG_GEMINIA_BUCK_VREF_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13910;"	d
+RG_GEMINIA_BW20_HB_COEF_00_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13619;"	d
+RG_GEMINIA_BW20_HB_COEF_00_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13617;"	d
+RG_GEMINIA_BW20_HB_COEF_00_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13616;"	d
+RG_GEMINIA_BW20_HB_COEF_00_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13618;"	d
+RG_GEMINIA_BW20_HB_COEF_00_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13620;"	d
+RG_GEMINIA_BW20_HB_COEF_01_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13614;"	d
+RG_GEMINIA_BW20_HB_COEF_01_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13612;"	d
+RG_GEMINIA_BW20_HB_COEF_01_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13611;"	d
+RG_GEMINIA_BW20_HB_COEF_01_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13613;"	d
+RG_GEMINIA_BW20_HB_COEF_01_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13615;"	d
+RG_GEMINIA_BW20_HB_COEF_02_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13629;"	d
+RG_GEMINIA_BW20_HB_COEF_02_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13627;"	d
+RG_GEMINIA_BW20_HB_COEF_02_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13626;"	d
+RG_GEMINIA_BW20_HB_COEF_02_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13628;"	d
+RG_GEMINIA_BW20_HB_COEF_02_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13630;"	d
+RG_GEMINIA_BW20_HB_COEF_03_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13624;"	d
+RG_GEMINIA_BW20_HB_COEF_03_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13622;"	d
+RG_GEMINIA_BW20_HB_COEF_03_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13621;"	d
+RG_GEMINIA_BW20_HB_COEF_03_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13623;"	d
+RG_GEMINIA_BW20_HB_COEF_03_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13625;"	d
+RG_GEMINIA_BW20_HB_COEF_04_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13639;"	d
+RG_GEMINIA_BW20_HB_COEF_04_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13637;"	d
+RG_GEMINIA_BW20_HB_COEF_04_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13636;"	d
+RG_GEMINIA_BW20_HB_COEF_04_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13638;"	d
+RG_GEMINIA_BW20_HB_COEF_04_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13640;"	d
+RG_GEMINIA_BW20_HB_COEF_05_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13634;"	d
+RG_GEMINIA_BW20_HB_COEF_05_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13632;"	d
+RG_GEMINIA_BW20_HB_COEF_05_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13631;"	d
+RG_GEMINIA_BW20_HB_COEF_05_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13633;"	d
+RG_GEMINIA_BW20_HB_COEF_05_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13635;"	d
+RG_GEMINIA_BW20_HB_COEF_06_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13649;"	d
+RG_GEMINIA_BW20_HB_COEF_06_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13647;"	d
+RG_GEMINIA_BW20_HB_COEF_06_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13646;"	d
+RG_GEMINIA_BW20_HB_COEF_06_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13648;"	d
+RG_GEMINIA_BW20_HB_COEF_06_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13650;"	d
+RG_GEMINIA_BW20_HB_COEF_07_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13644;"	d
+RG_GEMINIA_BW20_HB_COEF_07_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13642;"	d
+RG_GEMINIA_BW20_HB_COEF_07_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13641;"	d
+RG_GEMINIA_BW20_HB_COEF_07_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13643;"	d
+RG_GEMINIA_BW20_HB_COEF_07_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13645;"	d
+RG_GEMINIA_BW20_HB_COEF_08_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13659;"	d
+RG_GEMINIA_BW20_HB_COEF_08_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13657;"	d
+RG_GEMINIA_BW20_HB_COEF_08_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13656;"	d
+RG_GEMINIA_BW20_HB_COEF_08_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13658;"	d
+RG_GEMINIA_BW20_HB_COEF_08_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13660;"	d
+RG_GEMINIA_BW20_HB_COEF_09_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13654;"	d
+RG_GEMINIA_BW20_HB_COEF_09_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13652;"	d
+RG_GEMINIA_BW20_HB_COEF_09_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13651;"	d
+RG_GEMINIA_BW20_HB_COEF_09_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13653;"	d
+RG_GEMINIA_BW20_HB_COEF_09_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13655;"	d
+RG_GEMINIA_BW20_HB_COEF_10_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13669;"	d
+RG_GEMINIA_BW20_HB_COEF_10_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13667;"	d
+RG_GEMINIA_BW20_HB_COEF_10_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13666;"	d
+RG_GEMINIA_BW20_HB_COEF_10_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13668;"	d
+RG_GEMINIA_BW20_HB_COEF_10_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13670;"	d
+RG_GEMINIA_BW20_HB_COEF_11_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13664;"	d
+RG_GEMINIA_BW20_HB_COEF_11_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13662;"	d
+RG_GEMINIA_BW20_HB_COEF_11_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13661;"	d
+RG_GEMINIA_BW20_HB_COEF_11_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13663;"	d
+RG_GEMINIA_BW20_HB_COEF_11_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13665;"	d
+RG_GEMINIA_CAL_INDEX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10259;"	d
+RG_GEMINIA_CAL_INDEX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10257;"	d
+RG_GEMINIA_CAL_INDEX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10256;"	d
+RG_GEMINIA_CAL_INDEX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10258;"	d
+RG_GEMINIA_CAL_INDEX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10260;"	d
+RG_GEMINIA_CBW_20_40_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13579;"	d
+RG_GEMINIA_CBW_20_40_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13577;"	d
+RG_GEMINIA_CBW_20_40_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13576;"	d
+RG_GEMINIA_CBW_20_40_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13578;"	d
+RG_GEMINIA_CBW_20_40_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13580;"	d
+RG_GEMINIA_CLK_RTC_SW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14024;"	d
+RG_GEMINIA_CLK_RTC_SW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14022;"	d
+RG_GEMINIA_CLK_RTC_SW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14021;"	d
+RG_GEMINIA_CLK_RTC_SW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14023;"	d
+RG_GEMINIA_CLK_RTC_SW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14025;"	d
+RG_GEMINIA_CLK_SAR_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11484;"	d
+RG_GEMINIA_CLK_SAR_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11482;"	d
+RG_GEMINIA_CLK_SAR_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11481;"	d
+RG_GEMINIA_CLK_SAR_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11483;"	d
+RG_GEMINIA_CLK_SAR_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11485;"	d
+RG_GEMINIA_DAC_DC_I_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13589;"	d
+RG_GEMINIA_DAC_DC_I_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13587;"	d
+RG_GEMINIA_DAC_DC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13586;"	d
+RG_GEMINIA_DAC_DC_I_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13588;"	d
+RG_GEMINIA_DAC_DC_I_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13590;"	d
+RG_GEMINIA_DAC_DC_Q_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13584;"	d
+RG_GEMINIA_DAC_DC_Q_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13582;"	d
+RG_GEMINIA_DAC_DC_Q_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13581;"	d
+RG_GEMINIA_DAC_DC_Q_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13583;"	d
+RG_GEMINIA_DAC_DC_Q_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13585;"	d
+RG_GEMINIA_DAC_I_SET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13604;"	d
+RG_GEMINIA_DAC_I_SET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13602;"	d
+RG_GEMINIA_DAC_I_SET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13601;"	d
+RG_GEMINIA_DAC_I_SET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13603;"	d
+RG_GEMINIA_DAC_I_SET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13605;"	d
+RG_GEMINIA_DAC_MAN_I_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13609;"	d
+RG_GEMINIA_DAC_MAN_I_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13607;"	d
+RG_GEMINIA_DAC_MAN_I_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13606;"	d
+RG_GEMINIA_DAC_MAN_I_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13608;"	d
+RG_GEMINIA_DAC_MAN_I_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13610;"	d
+RG_GEMINIA_DAC_MAN_Q_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13599;"	d
+RG_GEMINIA_DAC_MAN_Q_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13597;"	d
+RG_GEMINIA_DAC_MAN_Q_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13596;"	d
+RG_GEMINIA_DAC_MAN_Q_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13598;"	d
+RG_GEMINIA_DAC_MAN_Q_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13600;"	d
+RG_GEMINIA_DAC_Q_SET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13594;"	d
+RG_GEMINIA_DAC_Q_SET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13592;"	d
+RG_GEMINIA_DAC_Q_SET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13591;"	d
+RG_GEMINIA_DAC_Q_SET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13593;"	d
+RG_GEMINIA_DAC_Q_SET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13595;"	d
+RG_GEMINIA_DCDC_CLK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13949;"	d
+RG_GEMINIA_DCDC_CLK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13947;"	d
+RG_GEMINIA_DCDC_CLK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13946;"	d
+RG_GEMINIA_DCDC_CLK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13948;"	d
+RG_GEMINIA_DCDC_CLK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13950;"	d
+RG_GEMINIA_DCDC_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13879;"	d
+RG_GEMINIA_DCDC_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13877;"	d
+RG_GEMINIA_DCDC_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13876;"	d
+RG_GEMINIA_DCDC_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13878;"	d
+RG_GEMINIA_DCDC_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13880;"	d
+RG_GEMINIA_DCDC_PULLLOW_CON_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13924;"	d
+RG_GEMINIA_DCDC_PULLLOW_CON_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13922;"	d
+RG_GEMINIA_DCDC_PULLLOW_CON_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13921;"	d
+RG_GEMINIA_DCDC_PULLLOW_CON_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13923;"	d
+RG_GEMINIA_DCDC_PULLLOW_CON_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13925;"	d
+RG_GEMINIA_DCDC_RES2_CON_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13929;"	d
+RG_GEMINIA_DCDC_RES2_CON_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13927;"	d
+RG_GEMINIA_DCDC_RES2_CON_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13926;"	d
+RG_GEMINIA_DCDC_RES2_CON_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13928;"	d
+RG_GEMINIA_DCDC_RES2_CON_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13930;"	d
+RG_GEMINIA_DCDC_RES_CON_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13934;"	d
+RG_GEMINIA_DCDC_RES_CON_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13932;"	d
+RG_GEMINIA_DCDC_RES_CON_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13931;"	d
+RG_GEMINIA_DCDC_RES_CON_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13933;"	d
+RG_GEMINIA_DCDC_RES_CON_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13935;"	d
+RG_GEMINIA_DIS_DAC_OFFSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13564;"	d
+RG_GEMINIA_DIS_DAC_OFFSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13562;"	d
+RG_GEMINIA_DIS_DAC_OFFSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13561;"	d
+RG_GEMINIA_DIS_DAC_OFFSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13563;"	d
+RG_GEMINIA_DIS_DAC_OFFSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13565;"	d
+RG_GEMINIA_DLDO_BOOST_IQ_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13894;"	d
+RG_GEMINIA_DLDO_BOOST_IQ_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13892;"	d
+RG_GEMINIA_DLDO_BOOST_IQ_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13891;"	d
+RG_GEMINIA_DLDO_BOOST_IQ_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13893;"	d
+RG_GEMINIA_DLDO_BOOST_IQ_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13895;"	d
+RG_GEMINIA_DLDO_LEVEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13889;"	d
+RG_GEMINIA_DLDO_LEVEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13887;"	d
+RG_GEMINIA_DLDO_LEVEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13886;"	d
+RG_GEMINIA_DLDO_LEVEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13888;"	d
+RG_GEMINIA_DLDO_LEVEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13890;"	d
+RG_GEMINIA_DPLL_CLK320BY2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13574;"	d
+RG_GEMINIA_DPLL_CLK320BY2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13572;"	d
+RG_GEMINIA_DPLL_CLK320BY2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13571;"	d
+RG_GEMINIA_DPLL_CLK320BY2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13573;"	d
+RG_GEMINIA_DPLL_CLK320BY2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13575;"	d
+RG_GEMINIA_DPL_MOD_ORDER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12404;"	d
+RG_GEMINIA_DPL_MOD_ORDER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12402;"	d
+RG_GEMINIA_DPL_MOD_ORDER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12401;"	d
+RG_GEMINIA_DPL_MOD_ORDER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12403;"	d
+RG_GEMINIA_DPL_MOD_ORDER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12405;"	d
+RG_GEMINIA_DPL_RFCTRL_CH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12509;"	d
+RG_GEMINIA_DPL_RFCTRL_CH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12507;"	d
+RG_GEMINIA_DPL_RFCTRL_CH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12506;"	d
+RG_GEMINIA_DPL_RFCTRL_CH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12508;"	d
+RG_GEMINIA_DPL_RFCTRL_CH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12510;"	d
+RG_GEMINIA_DPL_RFCTRL_F_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12504;"	d
+RG_GEMINIA_DPL_RFCTRL_F_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12502;"	d
+RG_GEMINIA_DPL_RFCTRL_F_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12501;"	d
+RG_GEMINIA_DPL_RFCTRL_F_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12503;"	d
+RG_GEMINIA_DPL_RFCTRL_F_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12505;"	d
+RG_GEMINIA_DPL_SETTLING_TIMMER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13849;"	d
+RG_GEMINIA_DPL_SETTLING_TIMMER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13847;"	d
+RG_GEMINIA_DPL_SETTLING_TIMMER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13846;"	d
+RG_GEMINIA_DPL_SETTLING_TIMMER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13848;"	d
+RG_GEMINIA_DPL_SETTLING_TIMMER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13850;"	d
+RG_GEMINIA_DP_ADC320_DIVBY2_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12389;"	d
+RG_GEMINIA_DP_ADC320_DIVBY2_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12387;"	d
+RG_GEMINIA_DP_ADC320_DIVBY2_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12386;"	d
+RG_GEMINIA_DP_ADC320_DIVBY2_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12388;"	d
+RG_GEMINIA_DP_ADC320_DIVBY2_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12390;"	d
+RG_GEMINIA_DP_ADC320_DIVBY2_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12394;"	d
+RG_GEMINIA_DP_ADC320_DIVBY2_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12392;"	d
+RG_GEMINIA_DP_ADC320_DIVBY2_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12391;"	d
+RG_GEMINIA_DP_ADC320_DIVBY2_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12393;"	d
+RG_GEMINIA_DP_ADC320_DIVBY2_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12395;"	d
+RG_GEMINIA_DP_BBPLL_BP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12369;"	d
+RG_GEMINIA_DP_BBPLL_BP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12367;"	d
+RG_GEMINIA_DP_BBPLL_BP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12366;"	d
+RG_GEMINIA_DP_BBPLL_BP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12368;"	d
+RG_GEMINIA_DP_BBPLL_BP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12370;"	d
+RG_GEMINIA_DP_BBPLL_BS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12494;"	d
+RG_GEMINIA_DP_BBPLL_BS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12492;"	d
+RG_GEMINIA_DP_BBPLL_BS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12491;"	d
+RG_GEMINIA_DP_BBPLL_BS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12493;"	d
+RG_GEMINIA_DP_BBPLL_BS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12495;"	d
+RG_GEMINIA_DP_BBPLL_ICP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12439;"	d
+RG_GEMINIA_DP_BBPLL_ICP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12437;"	d
+RG_GEMINIA_DP_BBPLL_ICP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12436;"	d
+RG_GEMINIA_DP_BBPLL_ICP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12438;"	d
+RG_GEMINIA_DP_BBPLL_ICP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12440;"	d
+RG_GEMINIA_DP_BBPLL_IDUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12444;"	d
+RG_GEMINIA_DP_BBPLL_IDUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12442;"	d
+RG_GEMINIA_DP_BBPLL_IDUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12441;"	d
+RG_GEMINIA_DP_BBPLL_IDUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12443;"	d
+RG_GEMINIA_DP_BBPLL_IDUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12445;"	d
+RG_GEMINIA_DP_BBPLL_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12364;"	d
+RG_GEMINIA_DP_BBPLL_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12362;"	d
+RG_GEMINIA_DP_BBPLL_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12361;"	d
+RG_GEMINIA_DP_BBPLL_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12363;"	d
+RG_GEMINIA_DP_BBPLL_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12365;"	d
+RG_GEMINIA_DP_BBPLL_PFD_DLY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12464;"	d
+RG_GEMINIA_DP_BBPLL_PFD_DLY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12462;"	d
+RG_GEMINIA_DP_BBPLL_PFD_DLY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12461;"	d
+RG_GEMINIA_DP_BBPLL_PFD_DLY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12463;"	d
+RG_GEMINIA_DP_BBPLL_PFD_DLY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12465;"	d
+RG_GEMINIA_DP_BBPLL_SDM_EDGE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12499;"	d
+RG_GEMINIA_DP_BBPLL_SDM_EDGE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12497;"	d
+RG_GEMINIA_DP_BBPLL_SDM_EDGE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12496;"	d
+RG_GEMINIA_DP_BBPLL_SDM_EDGE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12498;"	d
+RG_GEMINIA_DP_BBPLL_SDM_EDGE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12500;"	d
+RG_GEMINIA_DP_BBPLL_TESTSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12434;"	d
+RG_GEMINIA_DP_BBPLL_TESTSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12432;"	d
+RG_GEMINIA_DP_BBPLL_TESTSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12431;"	d
+RG_GEMINIA_DP_BBPLL_TESTSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12433;"	d
+RG_GEMINIA_DP_BBPLL_TESTSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12435;"	d
+RG_GEMINIA_DP_CP_IOSTPOL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12449;"	d
+RG_GEMINIA_DP_CP_IOSTPOL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12447;"	d
+RG_GEMINIA_DP_CP_IOSTPOL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12446;"	d
+RG_GEMINIA_DP_CP_IOSTPOL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12448;"	d
+RG_GEMINIA_DP_CP_IOSTPOL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12450;"	d
+RG_GEMINIA_DP_CP_IOST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12454;"	d
+RG_GEMINIA_DP_CP_IOST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12452;"	d
+RG_GEMINIA_DP_CP_IOST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12451;"	d
+RG_GEMINIA_DP_CP_IOST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12453;"	d
+RG_GEMINIA_DP_CP_IOST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12455;"	d
+RG_GEMINIA_DP_DAC320_DIVBY2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12384;"	d
+RG_GEMINIA_DP_DAC320_DIVBY2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12382;"	d
+RG_GEMINIA_DP_DAC320_DIVBY2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12381;"	d
+RG_GEMINIA_DP_DAC320_DIVBY2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12383;"	d
+RG_GEMINIA_DP_DAC320_DIVBY2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12385;"	d
+RG_GEMINIA_DP_FODIV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12414;"	d
+RG_GEMINIA_DP_FODIV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12412;"	d
+RG_GEMINIA_DP_FODIV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12411;"	d
+RG_GEMINIA_DP_FODIV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12413;"	d
+RG_GEMINIA_DP_FODIV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12415;"	d
+RG_GEMINIA_DP_FREF_DOUB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12379;"	d
+RG_GEMINIA_DP_FREF_DOUB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12377;"	d
+RG_GEMINIA_DP_FREF_DOUB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12376;"	d
+RG_GEMINIA_DP_FREF_DOUB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12378;"	d
+RG_GEMINIA_DP_FREF_DOUB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12380;"	d
+RG_GEMINIA_DP_LDO_LEVEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10614;"	d
+RG_GEMINIA_DP_LDO_LEVEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10612;"	d
+RG_GEMINIA_DP_LDO_LEVEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10611;"	d
+RG_GEMINIA_DP_LDO_LEVEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10613;"	d
+RG_GEMINIA_DP_LDO_LEVEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10615;"	d
+RG_GEMINIA_DP_OD_TEST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12429;"	d
+RG_GEMINIA_DP_OD_TEST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12427;"	d
+RG_GEMINIA_DP_OD_TEST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12426;"	d
+RG_GEMINIA_DP_OD_TEST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12428;"	d
+RG_GEMINIA_DP_OD_TEST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12430;"	d
+RG_GEMINIA_DP_PFD_PFDSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12459;"	d
+RG_GEMINIA_DP_PFD_PFDSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12457;"	d
+RG_GEMINIA_DP_PFD_PFDSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12456;"	d
+RG_GEMINIA_DP_PFD_PFDSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12458;"	d
+RG_GEMINIA_DP_PFD_PFDSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12460;"	d
+RG_GEMINIA_DP_REFDIV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12409;"	d
+RG_GEMINIA_DP_REFDIV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12407;"	d
+RG_GEMINIA_DP_REFDIV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12406;"	d
+RG_GEMINIA_DP_REFDIV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12408;"	d
+RG_GEMINIA_DP_REFDIV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12410;"	d
+RG_GEMINIA_DP_RHP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12474;"	d
+RG_GEMINIA_DP_RHP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12472;"	d
+RG_GEMINIA_DP_RHP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12471;"	d
+RG_GEMINIA_DP_RHP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12473;"	d
+RG_GEMINIA_DP_RHP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12475;"	d
+RG_GEMINIA_DP_RP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12469;"	d
+RG_GEMINIA_DP_RP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12467;"	d
+RG_GEMINIA_DP_RP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12466;"	d
+RG_GEMINIA_DP_RP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12468;"	d
+RG_GEMINIA_DP_RP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12470;"	d
+RG_GEMINIA_DP_VT_TH_HI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12484;"	d
+RG_GEMINIA_DP_VT_TH_HI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12482;"	d
+RG_GEMINIA_DP_VT_TH_HI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12481;"	d
+RG_GEMINIA_DP_VT_TH_HI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12483;"	d
+RG_GEMINIA_DP_VT_TH_HI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12485;"	d
+RG_GEMINIA_DP_VT_TH_LO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12489;"	d
+RG_GEMINIA_DP_VT_TH_LO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12487;"	d
+RG_GEMINIA_DP_VT_TH_LO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12486;"	d
+RG_GEMINIA_DP_VT_TH_LO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12488;"	d
+RG_GEMINIA_DP_VT_TH_LO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12490;"	d
+RG_GEMINIA_EN_DPL_MOD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12399;"	d
+RG_GEMINIA_EN_DPL_MOD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12397;"	d
+RG_GEMINIA_EN_DPL_MOD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12396;"	d
+RG_GEMINIA_EN_DPL_MOD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12398;"	d
+RG_GEMINIA_EN_DPL_MOD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12400;"	d
+RG_GEMINIA_EN_DP_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12374;"	d
+RG_GEMINIA_EN_DP_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12372;"	d
+RG_GEMINIA_EN_DP_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12371;"	d
+RG_GEMINIA_EN_DP_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12373;"	d
+RG_GEMINIA_EN_DP_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12375;"	d
+RG_GEMINIA_EN_DP_VT_MON_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12479;"	d
+RG_GEMINIA_EN_DP_VT_MON_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12477;"	d
+RG_GEMINIA_EN_DP_VT_MON_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12476;"	d
+RG_GEMINIA_EN_DP_VT_MON_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12478;"	d
+RG_GEMINIA_EN_DP_VT_MON_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12480;"	d
+RG_GEMINIA_EN_FDB_DCC_MUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13809;"	d
+RG_GEMINIA_EN_FDB_DCC_MUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13807;"	d
+RG_GEMINIA_EN_FDB_DCC_MUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13806;"	d
+RG_GEMINIA_EN_FDB_DCC_MUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13808;"	d
+RG_GEMINIA_EN_FDB_DCC_MUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13810;"	d
+RG_GEMINIA_EN_FDB_DELAYC_MUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13814;"	d
+RG_GEMINIA_EN_FDB_DELAYC_MUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13812;"	d
+RG_GEMINIA_EN_FDB_DELAYC_MUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13811;"	d
+RG_GEMINIA_EN_FDB_DELAYC_MUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13813;"	d
+RG_GEMINIA_EN_FDB_DELAYC_MUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13815;"	d
+RG_GEMINIA_EN_FDB_DELAYF_MUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13819;"	d
+RG_GEMINIA_EN_FDB_DELAYF_MUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13817;"	d
+RG_GEMINIA_EN_FDB_DELAYF_MUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13816;"	d
+RG_GEMINIA_EN_FDB_DELAYF_MUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13818;"	d
+RG_GEMINIA_EN_FDB_DELAYF_MUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13820;"	d
+RG_GEMINIA_EN_FDB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13789;"	d
+RG_GEMINIA_EN_FDB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13787;"	d
+RG_GEMINIA_EN_FDB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13786;"	d
+RG_GEMINIA_EN_FDB_PHASESWAP_MUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13824;"	d
+RG_GEMINIA_EN_FDB_PHASESWAP_MUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13822;"	d
+RG_GEMINIA_EN_FDB_PHASESWAP_MUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13821;"	d
+RG_GEMINIA_EN_FDB_PHASESWAP_MUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13823;"	d
+RG_GEMINIA_EN_FDB_PHASESWAP_MUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13825;"	d
+RG_GEMINIA_EN_FDB_RECAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13869;"	d
+RG_GEMINIA_EN_FDB_RECAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13867;"	d
+RG_GEMINIA_EN_FDB_RECAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13866;"	d
+RG_GEMINIA_EN_FDB_RECAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13868;"	d
+RG_GEMINIA_EN_FDB_RECAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13870;"	d
+RG_GEMINIA_EN_FDB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13788;"	d
+RG_GEMINIA_EN_FDB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13790;"	d
+RG_GEMINIA_EN_IREF_RX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10449;"	d
+RG_GEMINIA_EN_IREF_RX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10447;"	d
+RG_GEMINIA_EN_IREF_RX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10446;"	d
+RG_GEMINIA_EN_IREF_RX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10448;"	d
+RG_GEMINIA_EN_IREF_RX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10450;"	d
+RG_GEMINIA_EN_LDO_ABB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10434;"	d
+RG_GEMINIA_EN_LDO_ABB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10432;"	d
+RG_GEMINIA_EN_LDO_ABB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10431;"	d
+RG_GEMINIA_EN_LDO_ABB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10433;"	d
+RG_GEMINIA_EN_LDO_ABB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10435;"	d
+RG_GEMINIA_EN_LDO_ADC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10439;"	d
+RG_GEMINIA_EN_LDO_ADC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10437;"	d
+RG_GEMINIA_EN_LDO_ADC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10436;"	d
+RG_GEMINIA_EN_LDO_ADC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10438;"	d
+RG_GEMINIA_EN_LDO_ADC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10440;"	d
+RG_GEMINIA_EN_LDO_CP_BYP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11774;"	d
+RG_GEMINIA_EN_LDO_CP_BYP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11772;"	d
+RG_GEMINIA_EN_LDO_CP_BYP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11771;"	d
+RG_GEMINIA_EN_LDO_CP_BYP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11773;"	d
+RG_GEMINIA_EN_LDO_CP_BYP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11775;"	d
+RG_GEMINIA_EN_LDO_CP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11754;"	d
+RG_GEMINIA_EN_LDO_CP_IQUP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11799;"	d
+RG_GEMINIA_EN_LDO_CP_IQUP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11797;"	d
+RG_GEMINIA_EN_LDO_CP_IQUP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11796;"	d
+RG_GEMINIA_EN_LDO_CP_IQUP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11798;"	d
+RG_GEMINIA_EN_LDO_CP_IQUP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11800;"	d
+RG_GEMINIA_EN_LDO_CP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11752;"	d
+RG_GEMINIA_EN_LDO_CP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11751;"	d
+RG_GEMINIA_EN_LDO_CP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11753;"	d
+RG_GEMINIA_EN_LDO_CP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11755;"	d
+RG_GEMINIA_EN_LDO_DAC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10444;"	d
+RG_GEMINIA_EN_LDO_DAC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10442;"	d
+RG_GEMINIA_EN_LDO_DAC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10441;"	d
+RG_GEMINIA_EN_LDO_DAC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10443;"	d
+RG_GEMINIA_EN_LDO_DAC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10445;"	d
+RG_GEMINIA_EN_LDO_DIV_BYP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11779;"	d
+RG_GEMINIA_EN_LDO_DIV_BYP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11777;"	d
+RG_GEMINIA_EN_LDO_DIV_BYP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11776;"	d
+RG_GEMINIA_EN_LDO_DIV_BYP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11778;"	d
+RG_GEMINIA_EN_LDO_DIV_BYP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11780;"	d
+RG_GEMINIA_EN_LDO_DIV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11759;"	d
+RG_GEMINIA_EN_LDO_DIV_IQUP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11804;"	d
+RG_GEMINIA_EN_LDO_DIV_IQUP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11802;"	d
+RG_GEMINIA_EN_LDO_DIV_IQUP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11801;"	d
+RG_GEMINIA_EN_LDO_DIV_IQUP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11803;"	d
+RG_GEMINIA_EN_LDO_DIV_IQUP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11805;"	d
+RG_GEMINIA_EN_LDO_DIV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11757;"	d
+RG_GEMINIA_EN_LDO_DIV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11756;"	d
+RG_GEMINIA_EN_LDO_DIV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11758;"	d
+RG_GEMINIA_EN_LDO_DIV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11760;"	d
+RG_GEMINIA_EN_LDO_DP_BYP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12419;"	d
+RG_GEMINIA_EN_LDO_DP_BYP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12417;"	d
+RG_GEMINIA_EN_LDO_DP_BYP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12416;"	d
+RG_GEMINIA_EN_LDO_DP_BYP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12418;"	d
+RG_GEMINIA_EN_LDO_DP_BYP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12420;"	d
+RG_GEMINIA_EN_LDO_DP_IQUP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12424;"	d
+RG_GEMINIA_EN_LDO_DP_IQUP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12422;"	d
+RG_GEMINIA_EN_LDO_DP_IQUP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12421;"	d
+RG_GEMINIA_EN_LDO_DP_IQUP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12423;"	d
+RG_GEMINIA_EN_LDO_DP_IQUP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12425;"	d
+RG_GEMINIA_EN_LDO_EFUSE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13919;"	d
+RG_GEMINIA_EN_LDO_EFUSE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13917;"	d
+RG_GEMINIA_EN_LDO_EFUSE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13916;"	d
+RG_GEMINIA_EN_LDO_EFUSE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13918;"	d
+RG_GEMINIA_EN_LDO_EFUSE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13920;"	d
+RG_GEMINIA_EN_LDO_LO_BYP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11784;"	d
+RG_GEMINIA_EN_LDO_LO_BYP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11782;"	d
+RG_GEMINIA_EN_LDO_LO_BYP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11781;"	d
+RG_GEMINIA_EN_LDO_LO_BYP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11783;"	d
+RG_GEMINIA_EN_LDO_LO_BYP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11785;"	d
+RG_GEMINIA_EN_LDO_LO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11764;"	d
+RG_GEMINIA_EN_LDO_LO_IQUP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11809;"	d
+RG_GEMINIA_EN_LDO_LO_IQUP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11807;"	d
+RG_GEMINIA_EN_LDO_LO_IQUP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11806;"	d
+RG_GEMINIA_EN_LDO_LO_IQUP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11808;"	d
+RG_GEMINIA_EN_LDO_LO_IQUP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11810;"	d
+RG_GEMINIA_EN_LDO_LO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11762;"	d
+RG_GEMINIA_EN_LDO_LO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11761;"	d
+RG_GEMINIA_EN_LDO_LO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11763;"	d
+RG_GEMINIA_EN_LDO_LO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11765;"	d
+RG_GEMINIA_EN_LDO_RX_ADC_IQUP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10579;"	d
+RG_GEMINIA_EN_LDO_RX_ADC_IQUP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10577;"	d
+RG_GEMINIA_EN_LDO_RX_ADC_IQUP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10576;"	d
+RG_GEMINIA_EN_LDO_RX_ADC_IQUP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10578;"	d
+RG_GEMINIA_EN_LDO_RX_ADC_IQUP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10580;"	d
+RG_GEMINIA_EN_LDO_RX_FE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10429;"	d
+RG_GEMINIA_EN_LDO_RX_FE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10427;"	d
+RG_GEMINIA_EN_LDO_RX_FE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10426;"	d
+RG_GEMINIA_EN_LDO_RX_FE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10428;"	d
+RG_GEMINIA_EN_LDO_RX_FE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10430;"	d
+RG_GEMINIA_EN_LDO_VCO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11769;"	d
+RG_GEMINIA_EN_LDO_VCO_IQUP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11814;"	d
+RG_GEMINIA_EN_LDO_VCO_IQUP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11812;"	d
+RG_GEMINIA_EN_LDO_VCO_IQUP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11811;"	d
+RG_GEMINIA_EN_LDO_VCO_IQUP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11813;"	d
+RG_GEMINIA_EN_LDO_VCO_IQUP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11815;"	d
+RG_GEMINIA_EN_LDO_VCO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11767;"	d
+RG_GEMINIA_EN_LDO_VCO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11766;"	d
+RG_GEMINIA_EN_LDO_VCO_PSW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11789;"	d
+RG_GEMINIA_EN_LDO_VCO_PSW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11787;"	d
+RG_GEMINIA_EN_LDO_VCO_PSW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11786;"	d
+RG_GEMINIA_EN_LDO_VCO_PSW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11788;"	d
+RG_GEMINIA_EN_LDO_VCO_PSW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11790;"	d
+RG_GEMINIA_EN_LDO_VCO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11768;"	d
+RG_GEMINIA_EN_LDO_VCO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11770;"	d
+RG_GEMINIA_EN_LDO_VCO_VDD33_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11794;"	d
+RG_GEMINIA_EN_LDO_VCO_VDD33_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11792;"	d
+RG_GEMINIA_EN_LDO_VCO_VDD33_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11791;"	d
+RG_GEMINIA_EN_LDO_VCO_VDD33_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11793;"	d
+RG_GEMINIA_EN_LDO_VCO_VDD33_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11795;"	d
+RG_GEMINIA_EN_LDO_XO_BYP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13764;"	d
+RG_GEMINIA_EN_LDO_XO_BYP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13762;"	d
+RG_GEMINIA_EN_LDO_XO_BYP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13761;"	d
+RG_GEMINIA_EN_LDO_XO_BYP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13763;"	d
+RG_GEMINIA_EN_LDO_XO_BYP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13765;"	d
+RG_GEMINIA_EN_LDO_XO_IQUP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13769;"	d
+RG_GEMINIA_EN_LDO_XO_IQUP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13767;"	d
+RG_GEMINIA_EN_LDO_XO_IQUP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13766;"	d
+RG_GEMINIA_EN_LDO_XO_IQUP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13768;"	d
+RG_GEMINIA_EN_LDO_XO_IQUP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13770;"	d
+RG_GEMINIA_EN_RTC_CAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13984;"	d
+RG_GEMINIA_EN_RTC_CAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13982;"	d
+RG_GEMINIA_EN_RTC_CAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13981;"	d
+RG_GEMINIA_EN_RTC_CAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13983;"	d
+RG_GEMINIA_EN_RTC_CAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13985;"	d
+RG_GEMINIA_EN_RX_ADC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10354;"	d
+RG_GEMINIA_EN_RX_ADC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10352;"	d
+RG_GEMINIA_EN_RX_ADC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10351;"	d
+RG_GEMINIA_EN_RX_ADC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10353;"	d
+RG_GEMINIA_EN_RX_ADC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10355;"	d
+RG_GEMINIA_EN_RX_DIV2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10314;"	d
+RG_GEMINIA_EN_RX_DIV2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10312;"	d
+RG_GEMINIA_EN_RX_DIV2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10311;"	d
+RG_GEMINIA_EN_RX_DIV2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10313;"	d
+RG_GEMINIA_EN_RX_DIV2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10315;"	d
+RG_GEMINIA_EN_RX_FILTER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10344;"	d
+RG_GEMINIA_EN_RX_FILTER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10342;"	d
+RG_GEMINIA_EN_RX_FILTER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10341;"	d
+RG_GEMINIA_EN_RX_FILTER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10343;"	d
+RG_GEMINIA_EN_RX_FILTER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10345;"	d
+RG_GEMINIA_EN_RX_IQCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10489;"	d
+RG_GEMINIA_EN_RX_IQCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10487;"	d
+RG_GEMINIA_EN_RX_IQCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10486;"	d
+RG_GEMINIA_EN_RX_IQCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10488;"	d
+RG_GEMINIA_EN_RX_IQCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10490;"	d
+RG_GEMINIA_EN_RX_LNA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10294;"	d
+RG_GEMINIA_EN_RX_LNA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10292;"	d
+RG_GEMINIA_EN_RX_LNA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10291;"	d
+RG_GEMINIA_EN_RX_LNA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10293;"	d
+RG_GEMINIA_EN_RX_LNA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10295;"	d
+RG_GEMINIA_EN_RX_LOBUF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10324;"	d
+RG_GEMINIA_EN_RX_LOBUF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10322;"	d
+RG_GEMINIA_EN_RX_LOBUF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10321;"	d
+RG_GEMINIA_EN_RX_LOBUF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10323;"	d
+RG_GEMINIA_EN_RX_LOBUF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10325;"	d
+RG_GEMINIA_EN_RX_MIXER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10304;"	d
+RG_GEMINIA_EN_RX_MIXER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10302;"	d
+RG_GEMINIA_EN_RX_MIXER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10301;"	d
+RG_GEMINIA_EN_RX_MIXER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10303;"	d
+RG_GEMINIA_EN_RX_MIXER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10305;"	d
+RG_GEMINIA_EN_RX_PADSW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10554;"	d
+RG_GEMINIA_EN_RX_PADSW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10552;"	d
+RG_GEMINIA_EN_RX_PADSW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10551;"	d
+RG_GEMINIA_EN_RX_PADSW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10553;"	d
+RG_GEMINIA_EN_RX_PADSW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10555;"	d
+RG_GEMINIA_EN_RX_RSSI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10364;"	d
+RG_GEMINIA_EN_RX_RSSI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10362;"	d
+RG_GEMINIA_EN_RX_RSSI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10361;"	d
+RG_GEMINIA_EN_RX_RSSI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10363;"	d
+RG_GEMINIA_EN_RX_RSSI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10365;"	d
+RG_GEMINIA_EN_RX_RSSI_TESTNODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10819;"	d
+RG_GEMINIA_EN_RX_RSSI_TESTNODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10817;"	d
+RG_GEMINIA_EN_RX_RSSI_TESTNODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10816;"	d
+RG_GEMINIA_EN_RX_RSSI_TESTNODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10818;"	d
+RG_GEMINIA_EN_RX_RSSI_TESTNODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10820;"	d
+RG_GEMINIA_EN_RX_TESTNODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10549;"	d
+RG_GEMINIA_EN_RX_TESTNODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10547;"	d
+RG_GEMINIA_EN_RX_TESTNODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10546;"	d
+RG_GEMINIA_EN_RX_TESTNODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10548;"	d
+RG_GEMINIA_EN_RX_TESTNODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10550;"	d
+RG_GEMINIA_EN_RX_TZ_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10334;"	d
+RG_GEMINIA_EN_RX_TZ_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10332;"	d
+RG_GEMINIA_EN_RX_TZ_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10331;"	d
+RG_GEMINIA_EN_RX_TZ_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10333;"	d
+RG_GEMINIA_EN_RX_TZ_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10335;"	d
+RG_GEMINIA_EN_SARADC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10514;"	d
+RG_GEMINIA_EN_SARADC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10512;"	d
+RG_GEMINIA_EN_SARADC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10511;"	d
+RG_GEMINIA_EN_SARADC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10513;"	d
+RG_GEMINIA_EN_SARADC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10515;"	d
+RG_GEMINIA_EN_SAR_TEST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11469;"	d
+RG_GEMINIA_EN_SAR_TEST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11467;"	d
+RG_GEMINIA_EN_SAR_TEST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11466;"	d
+RG_GEMINIA_EN_SAR_TEST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11468;"	d
+RG_GEMINIA_EN_SAR_TEST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11470;"	d
+RG_GEMINIA_EN_SX_CP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11629;"	d
+RG_GEMINIA_EN_SX_CP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11627;"	d
+RG_GEMINIA_EN_SX_CP_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11624;"	d
+RG_GEMINIA_EN_SX_CP_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11622;"	d
+RG_GEMINIA_EN_SX_CP_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11621;"	d
+RG_GEMINIA_EN_SX_CP_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11623;"	d
+RG_GEMINIA_EN_SX_CP_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11625;"	d
+RG_GEMINIA_EN_SX_CP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11626;"	d
+RG_GEMINIA_EN_SX_CP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11628;"	d
+RG_GEMINIA_EN_SX_CP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11630;"	d
+RG_GEMINIA_EN_SX_DITHER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12199;"	d
+RG_GEMINIA_EN_SX_DITHER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12197;"	d
+RG_GEMINIA_EN_SX_DITHER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12196;"	d
+RG_GEMINIA_EN_SX_DITHER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12198;"	d
+RG_GEMINIA_EN_SX_DITHER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12200;"	d
+RG_GEMINIA_EN_SX_DIV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11639;"	d
+RG_GEMINIA_EN_SX_DIV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11637;"	d
+RG_GEMINIA_EN_SX_DIV_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11634;"	d
+RG_GEMINIA_EN_SX_DIV_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11632;"	d
+RG_GEMINIA_EN_SX_DIV_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11631;"	d
+RG_GEMINIA_EN_SX_DIV_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11633;"	d
+RG_GEMINIA_EN_SX_DIV_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11635;"	d
+RG_GEMINIA_EN_SX_DIV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11636;"	d
+RG_GEMINIA_EN_SX_DIV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11638;"	d
+RG_GEMINIA_EN_SX_DIV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11640;"	d
+RG_GEMINIA_EN_SX_LDO_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11749;"	d
+RG_GEMINIA_EN_SX_LDO_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11747;"	d
+RG_GEMINIA_EN_SX_LDO_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11746;"	d
+RG_GEMINIA_EN_SX_LDO_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11748;"	d
+RG_GEMINIA_EN_SX_LDO_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11750;"	d
+RG_GEMINIA_EN_SX_MOD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12194;"	d
+RG_GEMINIA_EN_SX_MOD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12192;"	d
+RG_GEMINIA_EN_SX_MOD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12191;"	d
+RG_GEMINIA_EN_SX_MOD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12193;"	d
+RG_GEMINIA_EN_SX_MOD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12195;"	d
+RG_GEMINIA_EN_SX_VCOMON_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12164;"	d
+RG_GEMINIA_EN_SX_VCOMON_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12162;"	d
+RG_GEMINIA_EN_SX_VCOMON_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12161;"	d
+RG_GEMINIA_EN_SX_VCOMON_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12163;"	d
+RG_GEMINIA_EN_SX_VCOMON_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12165;"	d
+RG_GEMINIA_EN_SX_VCO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11649;"	d
+RG_GEMINIA_EN_SX_VCO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11647;"	d
+RG_GEMINIA_EN_SX_VCO_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11644;"	d
+RG_GEMINIA_EN_SX_VCO_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11642;"	d
+RG_GEMINIA_EN_SX_VCO_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11641;"	d
+RG_GEMINIA_EN_SX_VCO_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11643;"	d
+RG_GEMINIA_EN_SX_VCO_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11645;"	d
+RG_GEMINIA_EN_SX_VCO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11646;"	d
+RG_GEMINIA_EN_SX_VCO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11648;"	d
+RG_GEMINIA_EN_SX_VCO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11650;"	d
+RG_GEMINIA_EN_TX_BT_PA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10424;"	d
+RG_GEMINIA_EN_TX_BT_PA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10422;"	d
+RG_GEMINIA_EN_TX_BT_PA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10421;"	d
+RG_GEMINIA_EN_TX_BT_PA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10423;"	d
+RG_GEMINIA_EN_TX_BT_PA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10425;"	d
+RG_GEMINIA_EN_TX_DAC_CAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10459;"	d
+RG_GEMINIA_EN_TX_DAC_CAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10457;"	d
+RG_GEMINIA_EN_TX_DAC_CAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10456;"	d
+RG_GEMINIA_EN_TX_DAC_CAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10458;"	d
+RG_GEMINIA_EN_TX_DAC_CAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10460;"	d
+RG_GEMINIA_EN_TX_DAC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10394;"	d
+RG_GEMINIA_EN_TX_DAC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10392;"	d
+RG_GEMINIA_EN_TX_DAC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10391;"	d
+RG_GEMINIA_EN_TX_DAC_OUT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10534;"	d
+RG_GEMINIA_EN_TX_DAC_OUT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10532;"	d
+RG_GEMINIA_EN_TX_DAC_OUT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10531;"	d
+RG_GEMINIA_EN_TX_DAC_OUT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10533;"	d
+RG_GEMINIA_EN_TX_DAC_OUT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10535;"	d
+RG_GEMINIA_EN_TX_DAC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10393;"	d
+RG_GEMINIA_EN_TX_DAC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10395;"	d
+RG_GEMINIA_EN_TX_DAC_VOUT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10539;"	d
+RG_GEMINIA_EN_TX_DAC_VOUT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10537;"	d
+RG_GEMINIA_EN_TX_DAC_VOUT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10536;"	d
+RG_GEMINIA_EN_TX_DAC_VOUT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10538;"	d
+RG_GEMINIA_EN_TX_DAC_VOUT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10540;"	d
+RG_GEMINIA_EN_TX_DIV2_BUF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10414;"	d
+RG_GEMINIA_EN_TX_DIV2_BUF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10412;"	d
+RG_GEMINIA_EN_TX_DIV2_BUF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10411;"	d
+RG_GEMINIA_EN_TX_DIV2_BUF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10413;"	d
+RG_GEMINIA_EN_TX_DIV2_BUF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10415;"	d
+RG_GEMINIA_EN_TX_DIV2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10404;"	d
+RG_GEMINIA_EN_TX_DIV2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10402;"	d
+RG_GEMINIA_EN_TX_DIV2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10401;"	d
+RG_GEMINIA_EN_TX_DIV2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10403;"	d
+RG_GEMINIA_EN_TX_DIV2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10405;"	d
+RG_GEMINIA_EN_TX_DPD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10499;"	d
+RG_GEMINIA_EN_TX_DPD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10497;"	d
+RG_GEMINIA_EN_TX_DPD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10496;"	d
+RG_GEMINIA_EN_TX_DPD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10498;"	d
+RG_GEMINIA_EN_TX_DPD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10500;"	d
+RG_GEMINIA_EN_TX_MOD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10384;"	d
+RG_GEMINIA_EN_TX_MOD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10382;"	d
+RG_GEMINIA_EN_TX_MOD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10381;"	d
+RG_GEMINIA_EN_TX_MOD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10383;"	d
+RG_GEMINIA_EN_TX_MOD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10385;"	d
+RG_GEMINIA_EN_TX_PA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10374;"	d
+RG_GEMINIA_EN_TX_PA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10372;"	d
+RG_GEMINIA_EN_TX_PA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10371;"	d
+RG_GEMINIA_EN_TX_PA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10373;"	d
+RG_GEMINIA_EN_TX_PA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10375;"	d
+RG_GEMINIA_EN_TX_SELF_MIXER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10479;"	d
+RG_GEMINIA_EN_TX_SELF_MIXER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10477;"	d
+RG_GEMINIA_EN_TX_SELF_MIXER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10476;"	d
+RG_GEMINIA_EN_TX_SELF_MIXER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10478;"	d
+RG_GEMINIA_EN_TX_SELF_MIXER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10480;"	d
+RG_GEMINIA_EN_TX_TRSW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10284;"	d
+RG_GEMINIA_EN_TX_TRSW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10282;"	d
+RG_GEMINIA_EN_TX_TRSW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10281;"	d
+RG_GEMINIA_EN_TX_TRSW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10283;"	d
+RG_GEMINIA_EN_TX_TRSW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10285;"	d
+RG_GEMINIA_EN_TX_TSSI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10509;"	d
+RG_GEMINIA_EN_TX_TSSI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10507;"	d
+RG_GEMINIA_EN_TX_TSSI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10506;"	d
+RG_GEMINIA_EN_TX_TSSI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10508;"	d
+RG_GEMINIA_EN_TX_TSSI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10510;"	d
+RG_GEMINIA_EN_TX_VTOI_2ND_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10519;"	d
+RG_GEMINIA_EN_TX_VTOI_2ND_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10517;"	d
+RG_GEMINIA_EN_TX_VTOI_2ND_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10516;"	d
+RG_GEMINIA_EN_TX_VTOI_2ND_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10518;"	d
+RG_GEMINIA_EN_TX_VTOI_2ND_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10520;"	d
+RG_GEMINIA_EN_VCOBF_DIVCK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11719;"	d
+RG_GEMINIA_EN_VCOBF_DIVCK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11717;"	d
+RG_GEMINIA_EN_VCOBF_DIVCK_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11714;"	d
+RG_GEMINIA_EN_VCOBF_DIVCK_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11712;"	d
+RG_GEMINIA_EN_VCOBF_DIVCK_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11711;"	d
+RG_GEMINIA_EN_VCOBF_DIVCK_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11713;"	d
+RG_GEMINIA_EN_VCOBF_DIVCK_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11715;"	d
+RG_GEMINIA_EN_VCOBF_DIVCK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11716;"	d
+RG_GEMINIA_EN_VCOBF_DIVCK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11718;"	d
+RG_GEMINIA_EN_VCOBF_DIVCK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11720;"	d
+RG_GEMINIA_EN_VCOBF_RXMB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11699;"	d
+RG_GEMINIA_EN_VCOBF_RXMB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11697;"	d
+RG_GEMINIA_EN_VCOBF_RXMB_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11694;"	d
+RG_GEMINIA_EN_VCOBF_RXMB_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11692;"	d
+RG_GEMINIA_EN_VCOBF_RXMB_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11691;"	d
+RG_GEMINIA_EN_VCOBF_RXMB_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11693;"	d
+RG_GEMINIA_EN_VCOBF_RXMB_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11695;"	d
+RG_GEMINIA_EN_VCOBF_RXMB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11696;"	d
+RG_GEMINIA_EN_VCOBF_RXMB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11698;"	d
+RG_GEMINIA_EN_VCOBF_RXMB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11700;"	d
+RG_GEMINIA_EN_VCOBF_RXOB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11709;"	d
+RG_GEMINIA_EN_VCOBF_RXOB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11707;"	d
+RG_GEMINIA_EN_VCOBF_RXOB_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11704;"	d
+RG_GEMINIA_EN_VCOBF_RXOB_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11702;"	d
+RG_GEMINIA_EN_VCOBF_RXOB_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11701;"	d
+RG_GEMINIA_EN_VCOBF_RXOB_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11703;"	d
+RG_GEMINIA_EN_VCOBF_RXOB_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11705;"	d
+RG_GEMINIA_EN_VCOBF_RXOB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11706;"	d
+RG_GEMINIA_EN_VCOBF_RXOB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11708;"	d
+RG_GEMINIA_EN_VCOBF_RXOB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11710;"	d
+RG_GEMINIA_EN_VCOBF_TXMB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11679;"	d
+RG_GEMINIA_EN_VCOBF_TXMB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11677;"	d
+RG_GEMINIA_EN_VCOBF_TXMB_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11674;"	d
+RG_GEMINIA_EN_VCOBF_TXMB_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11672;"	d
+RG_GEMINIA_EN_VCOBF_TXMB_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11671;"	d
+RG_GEMINIA_EN_VCOBF_TXMB_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11673;"	d
+RG_GEMINIA_EN_VCOBF_TXMB_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11675;"	d
+RG_GEMINIA_EN_VCOBF_TXMB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11676;"	d
+RG_GEMINIA_EN_VCOBF_TXMB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11678;"	d
+RG_GEMINIA_EN_VCOBF_TXMB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11680;"	d
+RG_GEMINIA_EN_VCOBF_TXOB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11689;"	d
+RG_GEMINIA_EN_VCOBF_TXOB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11687;"	d
+RG_GEMINIA_EN_VCOBF_TXOB_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11684;"	d
+RG_GEMINIA_EN_VCOBF_TXOB_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11682;"	d
+RG_GEMINIA_EN_VCOBF_TXOB_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11681;"	d
+RG_GEMINIA_EN_VCOBF_TXOB_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11683;"	d
+RG_GEMINIA_EN_VCOBF_TXOB_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11685;"	d
+RG_GEMINIA_EN_VCOBF_TXOB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11686;"	d
+RG_GEMINIA_EN_VCOBF_TXOB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11688;"	d
+RG_GEMINIA_EN_VCOBF_TXOB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11690;"	d
+RG_GEMINIA_EN_XOTEST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13804;"	d
+RG_GEMINIA_EN_XOTEST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13802;"	d
+RG_GEMINIA_EN_XOTEST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13801;"	d
+RG_GEMINIA_EN_XOTEST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13803;"	d
+RG_GEMINIA_EN_XOTEST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13805;"	d
+RG_GEMINIA_EXT_DAC_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13569;"	d
+RG_GEMINIA_EXT_DAC_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13567;"	d
+RG_GEMINIA_EXT_DAC_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13566;"	d
+RG_GEMINIA_EXT_DAC_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13568;"	d
+RG_GEMINIA_EXT_DAC_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13570;"	d
+RG_GEMINIA_EXT_MCU_PWRUP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14439;"	d
+RG_GEMINIA_EXT_MCU_PWRUP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14437;"	d
+RG_GEMINIA_EXT_MCU_PWRUP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14436;"	d
+RG_GEMINIA_EXT_MCU_PWRUP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14438;"	d
+RG_GEMINIA_EXT_MCU_PWRUP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14440;"	d
+RG_GEMINIA_FDB_BYPASS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13794;"	d
+RG_GEMINIA_FDB_BYPASS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13792;"	d
+RG_GEMINIA_FDB_BYPASS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13791;"	d
+RG_GEMINIA_FDB_BYPASS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13793;"	d
+RG_GEMINIA_FDB_BYPASS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13795;"	d
+RG_GEMINIA_FDB_CDELAY_MUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13834;"	d
+RG_GEMINIA_FDB_CDELAY_MUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13832;"	d
+RG_GEMINIA_FDB_CDELAY_MUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13831;"	d
+RG_GEMINIA_FDB_CDELAY_MUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13833;"	d
+RG_GEMINIA_FDB_CDELAY_MUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13835;"	d
+RG_GEMINIA_FDB_DUTY_LTH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13799;"	d
+RG_GEMINIA_FDB_DUTY_LTH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13797;"	d
+RG_GEMINIA_FDB_DUTY_LTH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13796;"	d
+RG_GEMINIA_FDB_DUTY_LTH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13798;"	d
+RG_GEMINIA_FDB_DUTY_LTH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13800;"	d
+RG_GEMINIA_FDB_FDELAY_MUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13839;"	d
+RG_GEMINIA_FDB_FDELAY_MUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13837;"	d
+RG_GEMINIA_FDB_FDELAY_MUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13836;"	d
+RG_GEMINIA_FDB_FDELAY_MUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13838;"	d
+RG_GEMINIA_FDB_FDELAY_MUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13840;"	d
+RG_GEMINIA_FDB_PHASESWAP_MUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13829;"	d
+RG_GEMINIA_FDB_PHASESWAP_MUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13827;"	d
+RG_GEMINIA_FDB_PHASESWAP_MUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13826;"	d
+RG_GEMINIA_FDB_PHASESWAP_MUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13828;"	d
+RG_GEMINIA_FDB_PHASESWAP_MUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13830;"	d
+RG_GEMINIA_FDB_RDELAYF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13854;"	d
+RG_GEMINIA_FDB_RDELAYF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13852;"	d
+RG_GEMINIA_FDB_RDELAYF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13851;"	d
+RG_GEMINIA_FDB_RDELAYF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13853;"	d
+RG_GEMINIA_FDB_RDELAYF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13855;"	d
+RG_GEMINIA_FDB_RDELAYS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13859;"	d
+RG_GEMINIA_FDB_RDELAYS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13857;"	d
+RG_GEMINIA_FDB_RDELAYS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13856;"	d
+RG_GEMINIA_FDB_RDELAYS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13858;"	d
+RG_GEMINIA_FDB_RDELAYS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13860;"	d
+RG_GEMINIA_FDB_RECAL_TIMMER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13864;"	d
+RG_GEMINIA_FDB_RECAL_TIMMER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13862;"	d
+RG_GEMINIA_FDB_RECAL_TIMMER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13861;"	d
+RG_GEMINIA_FDB_RECAL_TIMMER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13863;"	d
+RG_GEMINIA_FDB_RECAL_TIMMER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13865;"	d
+RG_GEMINIA_FPGA_CLK_REF_40M_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14164;"	d
+RG_GEMINIA_FPGA_CLK_REF_40M_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14162;"	d
+RG_GEMINIA_FPGA_CLK_REF_40M_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14161;"	d
+RG_GEMINIA_FPGA_CLK_REF_40M_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14163;"	d
+RG_GEMINIA_FPGA_CLK_REF_40M_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14165;"	d
+RG_GEMINIA_FPGA_CLK_REF_40M_OE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14174;"	d
+RG_GEMINIA_FPGA_CLK_REF_40M_OE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14172;"	d
+RG_GEMINIA_FPGA_CLK_REF_40M_OE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14171;"	d
+RG_GEMINIA_FPGA_CLK_REF_40M_OE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14173;"	d
+RG_GEMINIA_FPGA_CLK_REF_40M_OE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14175;"	d
+RG_GEMINIA_FPGA_CLK_REF_40M_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14169;"	d
+RG_GEMINIA_FPGA_CLK_REF_40M_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14167;"	d
+RG_GEMINIA_FPGA_CLK_REF_40M_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14166;"	d
+RG_GEMINIA_FPGA_CLK_REF_40M_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14168;"	d
+RG_GEMINIA_FPGA_CLK_REF_40M_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14170;"	d
+RG_GEMINIA_GPIO00_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14299;"	d
+RG_GEMINIA_GPIO00_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14297;"	d
+RG_GEMINIA_GPIO00_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14296;"	d
+RG_GEMINIA_GPIO00_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14298;"	d
+RG_GEMINIA_GPIO00_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14300;"	d
+RG_GEMINIA_GPIO00_OE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14309;"	d
+RG_GEMINIA_GPIO00_OE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14307;"	d
+RG_GEMINIA_GPIO00_OE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14306;"	d
+RG_GEMINIA_GPIO00_OE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14308;"	d
+RG_GEMINIA_GPIO00_OE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14310;"	d
+RG_GEMINIA_GPIO00_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14304;"	d
+RG_GEMINIA_GPIO00_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14302;"	d
+RG_GEMINIA_GPIO00_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14301;"	d
+RG_GEMINIA_GPIO00_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14303;"	d
+RG_GEMINIA_GPIO00_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14305;"	d
+RG_GEMINIA_GPIO01_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14314;"	d
+RG_GEMINIA_GPIO01_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14312;"	d
+RG_GEMINIA_GPIO01_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14311;"	d
+RG_GEMINIA_GPIO01_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14313;"	d
+RG_GEMINIA_GPIO01_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14315;"	d
+RG_GEMINIA_GPIO01_OE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14324;"	d
+RG_GEMINIA_GPIO01_OE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14322;"	d
+RG_GEMINIA_GPIO01_OE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14321;"	d
+RG_GEMINIA_GPIO01_OE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14323;"	d
+RG_GEMINIA_GPIO01_OE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14325;"	d
+RG_GEMINIA_GPIO01_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14319;"	d
+RG_GEMINIA_GPIO01_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14317;"	d
+RG_GEMINIA_GPIO01_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14316;"	d
+RG_GEMINIA_GPIO01_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14318;"	d
+RG_GEMINIA_GPIO01_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14320;"	d
+RG_GEMINIA_GPIO02_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14329;"	d
+RG_GEMINIA_GPIO02_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14327;"	d
+RG_GEMINIA_GPIO02_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14326;"	d
+RG_GEMINIA_GPIO02_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14328;"	d
+RG_GEMINIA_GPIO02_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14330;"	d
+RG_GEMINIA_GPIO02_OE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14339;"	d
+RG_GEMINIA_GPIO02_OE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14337;"	d
+RG_GEMINIA_GPIO02_OE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14336;"	d
+RG_GEMINIA_GPIO02_OE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14338;"	d
+RG_GEMINIA_GPIO02_OE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14340;"	d
+RG_GEMINIA_GPIO02_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14334;"	d
+RG_GEMINIA_GPIO02_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14332;"	d
+RG_GEMINIA_GPIO02_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14331;"	d
+RG_GEMINIA_GPIO02_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14333;"	d
+RG_GEMINIA_GPIO02_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14335;"	d
+RG_GEMINIA_GPIO03_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14344;"	d
+RG_GEMINIA_GPIO03_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14342;"	d
+RG_GEMINIA_GPIO03_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14341;"	d
+RG_GEMINIA_GPIO03_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14343;"	d
+RG_GEMINIA_GPIO03_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14345;"	d
+RG_GEMINIA_GPIO03_OE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14354;"	d
+RG_GEMINIA_GPIO03_OE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14352;"	d
+RG_GEMINIA_GPIO03_OE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14351;"	d
+RG_GEMINIA_GPIO03_OE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14353;"	d
+RG_GEMINIA_GPIO03_OE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14355;"	d
+RG_GEMINIA_GPIO03_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14349;"	d
+RG_GEMINIA_GPIO03_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14347;"	d
+RG_GEMINIA_GPIO03_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14346;"	d
+RG_GEMINIA_GPIO03_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14348;"	d
+RG_GEMINIA_GPIO03_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14350;"	d
+RG_GEMINIA_GPIO04_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14359;"	d
+RG_GEMINIA_GPIO04_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14357;"	d
+RG_GEMINIA_GPIO04_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14356;"	d
+RG_GEMINIA_GPIO04_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14358;"	d
+RG_GEMINIA_GPIO04_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14360;"	d
+RG_GEMINIA_GPIO04_OE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14369;"	d
+RG_GEMINIA_GPIO04_OE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14367;"	d
+RG_GEMINIA_GPIO04_OE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14366;"	d
+RG_GEMINIA_GPIO04_OE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14368;"	d
+RG_GEMINIA_GPIO04_OE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14370;"	d
+RG_GEMINIA_GPIO04_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14364;"	d
+RG_GEMINIA_GPIO04_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14362;"	d
+RG_GEMINIA_GPIO04_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14361;"	d
+RG_GEMINIA_GPIO04_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14363;"	d
+RG_GEMINIA_GPIO04_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14365;"	d
+RG_GEMINIA_GPIO05_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14374;"	d
+RG_GEMINIA_GPIO05_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14372;"	d
+RG_GEMINIA_GPIO05_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14371;"	d
+RG_GEMINIA_GPIO05_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14373;"	d
+RG_GEMINIA_GPIO05_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14375;"	d
+RG_GEMINIA_GPIO05_OE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14384;"	d
+RG_GEMINIA_GPIO05_OE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14382;"	d
+RG_GEMINIA_GPIO05_OE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14381;"	d
+RG_GEMINIA_GPIO05_OE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14383;"	d
+RG_GEMINIA_GPIO05_OE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14385;"	d
+RG_GEMINIA_GPIO05_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14379;"	d
+RG_GEMINIA_GPIO05_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14377;"	d
+RG_GEMINIA_GPIO05_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14376;"	d
+RG_GEMINIA_GPIO05_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14378;"	d
+RG_GEMINIA_GPIO05_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14380;"	d
+RG_GEMINIA_GPIO06_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14389;"	d
+RG_GEMINIA_GPIO06_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14387;"	d
+RG_GEMINIA_GPIO06_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14386;"	d
+RG_GEMINIA_GPIO06_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14388;"	d
+RG_GEMINIA_GPIO06_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14390;"	d
+RG_GEMINIA_GPIO06_OE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14399;"	d
+RG_GEMINIA_GPIO06_OE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14397;"	d
+RG_GEMINIA_GPIO06_OE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14396;"	d
+RG_GEMINIA_GPIO06_OE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14398;"	d
+RG_GEMINIA_GPIO06_OE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14400;"	d
+RG_GEMINIA_GPIO06_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14394;"	d
+RG_GEMINIA_GPIO06_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14392;"	d
+RG_GEMINIA_GPIO06_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14391;"	d
+RG_GEMINIA_GPIO06_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14393;"	d
+RG_GEMINIA_GPIO06_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14395;"	d
+RG_GEMINIA_GPIO07_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14404;"	d
+RG_GEMINIA_GPIO07_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14402;"	d
+RG_GEMINIA_GPIO07_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14401;"	d
+RG_GEMINIA_GPIO07_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14403;"	d
+RG_GEMINIA_GPIO07_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14405;"	d
+RG_GEMINIA_GPIO07_OE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14414;"	d
+RG_GEMINIA_GPIO07_OE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14412;"	d
+RG_GEMINIA_GPIO07_OE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14411;"	d
+RG_GEMINIA_GPIO07_OE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14413;"	d
+RG_GEMINIA_GPIO07_OE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14415;"	d
+RG_GEMINIA_GPIO07_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14409;"	d
+RG_GEMINIA_GPIO07_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14407;"	d
+RG_GEMINIA_GPIO07_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14406;"	d
+RG_GEMINIA_GPIO07_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14408;"	d
+RG_GEMINIA_GPIO07_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14410;"	d
+RG_GEMINIA_GPIO08_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14179;"	d
+RG_GEMINIA_GPIO08_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14177;"	d
+RG_GEMINIA_GPIO08_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14176;"	d
+RG_GEMINIA_GPIO08_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14178;"	d
+RG_GEMINIA_GPIO08_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14180;"	d
+RG_GEMINIA_GPIO08_OE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14189;"	d
+RG_GEMINIA_GPIO08_OE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14187;"	d
+RG_GEMINIA_GPIO08_OE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14186;"	d
+RG_GEMINIA_GPIO08_OE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14188;"	d
+RG_GEMINIA_GPIO08_OE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14190;"	d
+RG_GEMINIA_GPIO08_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14184;"	d
+RG_GEMINIA_GPIO08_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14182;"	d
+RG_GEMINIA_GPIO08_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14181;"	d
+RG_GEMINIA_GPIO08_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14183;"	d
+RG_GEMINIA_GPIO08_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14185;"	d
+RG_GEMINIA_GPIO09_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14194;"	d
+RG_GEMINIA_GPIO09_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14192;"	d
+RG_GEMINIA_GPIO09_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14191;"	d
+RG_GEMINIA_GPIO09_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14193;"	d
+RG_GEMINIA_GPIO09_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14195;"	d
+RG_GEMINIA_GPIO09_OE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14204;"	d
+RG_GEMINIA_GPIO09_OE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14202;"	d
+RG_GEMINIA_GPIO09_OE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14201;"	d
+RG_GEMINIA_GPIO09_OE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14203;"	d
+RG_GEMINIA_GPIO09_OE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14205;"	d
+RG_GEMINIA_GPIO09_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14199;"	d
+RG_GEMINIA_GPIO09_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14197;"	d
+RG_GEMINIA_GPIO09_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14196;"	d
+RG_GEMINIA_GPIO09_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14198;"	d
+RG_GEMINIA_GPIO09_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14200;"	d
+RG_GEMINIA_GPIO10_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14209;"	d
+RG_GEMINIA_GPIO10_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14207;"	d
+RG_GEMINIA_GPIO10_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14206;"	d
+RG_GEMINIA_GPIO10_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14208;"	d
+RG_GEMINIA_GPIO10_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14210;"	d
+RG_GEMINIA_GPIO10_OE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14219;"	d
+RG_GEMINIA_GPIO10_OE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14217;"	d
+RG_GEMINIA_GPIO10_OE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14216;"	d
+RG_GEMINIA_GPIO10_OE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14218;"	d
+RG_GEMINIA_GPIO10_OE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14220;"	d
+RG_GEMINIA_GPIO10_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14214;"	d
+RG_GEMINIA_GPIO10_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14212;"	d
+RG_GEMINIA_GPIO10_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14211;"	d
+RG_GEMINIA_GPIO10_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14213;"	d
+RG_GEMINIA_GPIO10_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14215;"	d
+RG_GEMINIA_GPIO11_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14224;"	d
+RG_GEMINIA_GPIO11_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14222;"	d
+RG_GEMINIA_GPIO11_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14221;"	d
+RG_GEMINIA_GPIO11_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14223;"	d
+RG_GEMINIA_GPIO11_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14225;"	d
+RG_GEMINIA_GPIO11_OE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14234;"	d
+RG_GEMINIA_GPIO11_OE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14232;"	d
+RG_GEMINIA_GPIO11_OE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14231;"	d
+RG_GEMINIA_GPIO11_OE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14233;"	d
+RG_GEMINIA_GPIO11_OE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14235;"	d
+RG_GEMINIA_GPIO11_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14229;"	d
+RG_GEMINIA_GPIO11_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14227;"	d
+RG_GEMINIA_GPIO11_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14226;"	d
+RG_GEMINIA_GPIO11_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14228;"	d
+RG_GEMINIA_GPIO11_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14230;"	d
+RG_GEMINIA_GPIO12_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14239;"	d
+RG_GEMINIA_GPIO12_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14237;"	d
+RG_GEMINIA_GPIO12_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14236;"	d
+RG_GEMINIA_GPIO12_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14238;"	d
+RG_GEMINIA_GPIO12_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14240;"	d
+RG_GEMINIA_GPIO12_OE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14249;"	d
+RG_GEMINIA_GPIO12_OE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14247;"	d
+RG_GEMINIA_GPIO12_OE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14246;"	d
+RG_GEMINIA_GPIO12_OE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14248;"	d
+RG_GEMINIA_GPIO12_OE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14250;"	d
+RG_GEMINIA_GPIO12_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14244;"	d
+RG_GEMINIA_GPIO12_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14242;"	d
+RG_GEMINIA_GPIO12_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14241;"	d
+RG_GEMINIA_GPIO12_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14243;"	d
+RG_GEMINIA_GPIO12_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14245;"	d
+RG_GEMINIA_GPIO13_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14254;"	d
+RG_GEMINIA_GPIO13_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14252;"	d
+RG_GEMINIA_GPIO13_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14251;"	d
+RG_GEMINIA_GPIO13_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14253;"	d
+RG_GEMINIA_GPIO13_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14255;"	d
+RG_GEMINIA_GPIO13_OE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14264;"	d
+RG_GEMINIA_GPIO13_OE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14262;"	d
+RG_GEMINIA_GPIO13_OE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14261;"	d
+RG_GEMINIA_GPIO13_OE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14263;"	d
+RG_GEMINIA_GPIO13_OE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14265;"	d
+RG_GEMINIA_GPIO13_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14259;"	d
+RG_GEMINIA_GPIO13_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14257;"	d
+RG_GEMINIA_GPIO13_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14256;"	d
+RG_GEMINIA_GPIO13_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14258;"	d
+RG_GEMINIA_GPIO13_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14260;"	d
+RG_GEMINIA_GPIO14_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14269;"	d
+RG_GEMINIA_GPIO14_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14267;"	d
+RG_GEMINIA_GPIO14_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14266;"	d
+RG_GEMINIA_GPIO14_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14268;"	d
+RG_GEMINIA_GPIO14_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14270;"	d
+RG_GEMINIA_GPIO14_OE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14279;"	d
+RG_GEMINIA_GPIO14_OE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14277;"	d
+RG_GEMINIA_GPIO14_OE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14276;"	d
+RG_GEMINIA_GPIO14_OE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14278;"	d
+RG_GEMINIA_GPIO14_OE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14280;"	d
+RG_GEMINIA_GPIO14_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14274;"	d
+RG_GEMINIA_GPIO14_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14272;"	d
+RG_GEMINIA_GPIO14_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14271;"	d
+RG_GEMINIA_GPIO14_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14273;"	d
+RG_GEMINIA_GPIO14_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14275;"	d
+RG_GEMINIA_GPIO15_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14284;"	d
+RG_GEMINIA_GPIO15_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14282;"	d
+RG_GEMINIA_GPIO15_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14281;"	d
+RG_GEMINIA_GPIO15_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14283;"	d
+RG_GEMINIA_GPIO15_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14285;"	d
+RG_GEMINIA_GPIO15_OE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14294;"	d
+RG_GEMINIA_GPIO15_OE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14292;"	d
+RG_GEMINIA_GPIO15_OE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14291;"	d
+RG_GEMINIA_GPIO15_OE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14293;"	d
+RG_GEMINIA_GPIO15_OE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14295;"	d
+RG_GEMINIA_GPIO15_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14289;"	d
+RG_GEMINIA_GPIO15_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14287;"	d
+RG_GEMINIA_GPIO15_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14286;"	d
+RG_GEMINIA_GPIO15_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14288;"	d
+RG_GEMINIA_GPIO15_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14290;"	d
+RG_GEMINIA_GPIO16_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14084;"	d
+RG_GEMINIA_GPIO16_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14082;"	d
+RG_GEMINIA_GPIO16_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14081;"	d
+RG_GEMINIA_GPIO16_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14083;"	d
+RG_GEMINIA_GPIO16_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14085;"	d
+RG_GEMINIA_GPIO16_OE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14094;"	d
+RG_GEMINIA_GPIO16_OE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14092;"	d
+RG_GEMINIA_GPIO16_OE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14091;"	d
+RG_GEMINIA_GPIO16_OE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14093;"	d
+RG_GEMINIA_GPIO16_OE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14095;"	d
+RG_GEMINIA_GPIO16_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14089;"	d
+RG_GEMINIA_GPIO16_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14087;"	d
+RG_GEMINIA_GPIO16_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14086;"	d
+RG_GEMINIA_GPIO16_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14088;"	d
+RG_GEMINIA_GPIO16_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14090;"	d
+RG_GEMINIA_GPIO17_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14099;"	d
+RG_GEMINIA_GPIO17_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14097;"	d
+RG_GEMINIA_GPIO17_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14096;"	d
+RG_GEMINIA_GPIO17_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14098;"	d
+RG_GEMINIA_GPIO17_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14100;"	d
+RG_GEMINIA_GPIO17_OE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14109;"	d
+RG_GEMINIA_GPIO17_OE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14107;"	d
+RG_GEMINIA_GPIO17_OE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14106;"	d
+RG_GEMINIA_GPIO17_OE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14108;"	d
+RG_GEMINIA_GPIO17_OE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14110;"	d
+RG_GEMINIA_GPIO17_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14104;"	d
+RG_GEMINIA_GPIO17_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14102;"	d
+RG_GEMINIA_GPIO17_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14101;"	d
+RG_GEMINIA_GPIO17_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14103;"	d
+RG_GEMINIA_GPIO17_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14105;"	d
+RG_GEMINIA_GPIO18_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14114;"	d
+RG_GEMINIA_GPIO18_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14112;"	d
+RG_GEMINIA_GPIO18_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14111;"	d
+RG_GEMINIA_GPIO18_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14113;"	d
+RG_GEMINIA_GPIO18_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14115;"	d
+RG_GEMINIA_GPIO18_OE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14124;"	d
+RG_GEMINIA_GPIO18_OE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14122;"	d
+RG_GEMINIA_GPIO18_OE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14121;"	d
+RG_GEMINIA_GPIO18_OE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14123;"	d
+RG_GEMINIA_GPIO18_OE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14125;"	d
+RG_GEMINIA_GPIO18_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14119;"	d
+RG_GEMINIA_GPIO18_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14117;"	d
+RG_GEMINIA_GPIO18_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14116;"	d
+RG_GEMINIA_GPIO18_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14118;"	d
+RG_GEMINIA_GPIO18_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14120;"	d
+RG_GEMINIA_GPIO19_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14129;"	d
+RG_GEMINIA_GPIO19_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14127;"	d
+RG_GEMINIA_GPIO19_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14126;"	d
+RG_GEMINIA_GPIO19_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14128;"	d
+RG_GEMINIA_GPIO19_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14130;"	d
+RG_GEMINIA_GPIO19_OE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14139;"	d
+RG_GEMINIA_GPIO19_OE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14137;"	d
+RG_GEMINIA_GPIO19_OE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14136;"	d
+RG_GEMINIA_GPIO19_OE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14138;"	d
+RG_GEMINIA_GPIO19_OE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14140;"	d
+RG_GEMINIA_GPIO19_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14134;"	d
+RG_GEMINIA_GPIO19_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14132;"	d
+RG_GEMINIA_GPIO19_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14131;"	d
+RG_GEMINIA_GPIO19_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14133;"	d
+RG_GEMINIA_GPIO19_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14135;"	d
+RG_GEMINIA_GPIO20_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14144;"	d
+RG_GEMINIA_GPIO20_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14142;"	d
+RG_GEMINIA_GPIO20_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14141;"	d
+RG_GEMINIA_GPIO20_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14143;"	d
+RG_GEMINIA_GPIO20_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14145;"	d
+RG_GEMINIA_GPIO20_OE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14154;"	d
+RG_GEMINIA_GPIO20_OE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14152;"	d
+RG_GEMINIA_GPIO20_OE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14151;"	d
+RG_GEMINIA_GPIO20_OE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14153;"	d
+RG_GEMINIA_GPIO20_OE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14155;"	d
+RG_GEMINIA_GPIO20_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14149;"	d
+RG_GEMINIA_GPIO20_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14147;"	d
+RG_GEMINIA_GPIO20_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14146;"	d
+RG_GEMINIA_GPIO20_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14148;"	d
+RG_GEMINIA_GPIO20_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14150;"	d
+RG_GEMINIA_HS_3WIRE_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10224;"	d
+RG_GEMINIA_HS_3WIRE_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10222;"	d
+RG_GEMINIA_HS_3WIRE_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10221;"	d
+RG_GEMINIA_HS_3WIRE_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10223;"	d
+RG_GEMINIA_HS_3WIRE_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10225;"	d
+RG_GEMINIA_HW_PINSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10219;"	d
+RG_GEMINIA_HW_PINSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10217;"	d
+RG_GEMINIA_HW_PINSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10216;"	d
+RG_GEMINIA_HW_PINSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10218;"	d
+RG_GEMINIA_HW_PINSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10220;"	d
+RG_GEMINIA_IDACAI_TZ0_COARSE0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12874;"	d
+RG_GEMINIA_IDACAI_TZ0_COARSE0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12872;"	d
+RG_GEMINIA_IDACAI_TZ0_COARSE0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12871;"	d
+RG_GEMINIA_IDACAI_TZ0_COARSE0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12873;"	d
+RG_GEMINIA_IDACAI_TZ0_COARSE0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12875;"	d
+RG_GEMINIA_IDACAI_TZ0_COARSE1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12864;"	d
+RG_GEMINIA_IDACAI_TZ0_COARSE1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12862;"	d
+RG_GEMINIA_IDACAI_TZ0_COARSE1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12861;"	d
+RG_GEMINIA_IDACAI_TZ0_COARSE1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12863;"	d
+RG_GEMINIA_IDACAI_TZ0_COARSE1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12865;"	d
+RG_GEMINIA_IDACAI_TZ0_COARSE2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12854;"	d
+RG_GEMINIA_IDACAI_TZ0_COARSE2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12852;"	d
+RG_GEMINIA_IDACAI_TZ0_COARSE2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12851;"	d
+RG_GEMINIA_IDACAI_TZ0_COARSE2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12853;"	d
+RG_GEMINIA_IDACAI_TZ0_COARSE2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12855;"	d
+RG_GEMINIA_IDACAI_TZ0_COARSE3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12844;"	d
+RG_GEMINIA_IDACAI_TZ0_COARSE3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12842;"	d
+RG_GEMINIA_IDACAI_TZ0_COARSE3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12841;"	d
+RG_GEMINIA_IDACAI_TZ0_COARSE3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12843;"	d
+RG_GEMINIA_IDACAI_TZ0_COARSE3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12845;"	d
+RG_GEMINIA_IDACAI_TZ0_COARSE4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12834;"	d
+RG_GEMINIA_IDACAI_TZ0_COARSE4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12832;"	d
+RG_GEMINIA_IDACAI_TZ0_COARSE4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12831;"	d
+RG_GEMINIA_IDACAI_TZ0_COARSE4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12833;"	d
+RG_GEMINIA_IDACAI_TZ0_COARSE4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12835;"	d
+RG_GEMINIA_IDACAI_TZ1_COARSE0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12924;"	d
+RG_GEMINIA_IDACAI_TZ1_COARSE0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12922;"	d
+RG_GEMINIA_IDACAI_TZ1_COARSE0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12921;"	d
+RG_GEMINIA_IDACAI_TZ1_COARSE0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12923;"	d
+RG_GEMINIA_IDACAI_TZ1_COARSE0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12925;"	d
+RG_GEMINIA_IDACAI_TZ1_COARSE1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12914;"	d
+RG_GEMINIA_IDACAI_TZ1_COARSE1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12912;"	d
+RG_GEMINIA_IDACAI_TZ1_COARSE1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12911;"	d
+RG_GEMINIA_IDACAI_TZ1_COARSE1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12913;"	d
+RG_GEMINIA_IDACAI_TZ1_COARSE1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12915;"	d
+RG_GEMINIA_IDACAI_TZ1_COARSE2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12904;"	d
+RG_GEMINIA_IDACAI_TZ1_COARSE2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12902;"	d
+RG_GEMINIA_IDACAI_TZ1_COARSE2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12901;"	d
+RG_GEMINIA_IDACAI_TZ1_COARSE2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12903;"	d
+RG_GEMINIA_IDACAI_TZ1_COARSE2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12905;"	d
+RG_GEMINIA_IDACAI_TZ1_COARSE3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12894;"	d
+RG_GEMINIA_IDACAI_TZ1_COARSE3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12892;"	d
+RG_GEMINIA_IDACAI_TZ1_COARSE3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12891;"	d
+RG_GEMINIA_IDACAI_TZ1_COARSE3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12893;"	d
+RG_GEMINIA_IDACAI_TZ1_COARSE3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12895;"	d
+RG_GEMINIA_IDACAI_TZ1_COARSE4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12884;"	d
+RG_GEMINIA_IDACAI_TZ1_COARSE4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12882;"	d
+RG_GEMINIA_IDACAI_TZ1_COARSE4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12881;"	d
+RG_GEMINIA_IDACAI_TZ1_COARSE4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12883;"	d
+RG_GEMINIA_IDACAI_TZ1_COARSE4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12885;"	d
+RG_GEMINIA_IDACAQ_TZ0_COARSE0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12879;"	d
+RG_GEMINIA_IDACAQ_TZ0_COARSE0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12877;"	d
+RG_GEMINIA_IDACAQ_TZ0_COARSE0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12876;"	d
+RG_GEMINIA_IDACAQ_TZ0_COARSE0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12878;"	d
+RG_GEMINIA_IDACAQ_TZ0_COARSE0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12880;"	d
+RG_GEMINIA_IDACAQ_TZ0_COARSE1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12869;"	d
+RG_GEMINIA_IDACAQ_TZ0_COARSE1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12867;"	d
+RG_GEMINIA_IDACAQ_TZ0_COARSE1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12866;"	d
+RG_GEMINIA_IDACAQ_TZ0_COARSE1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12868;"	d
+RG_GEMINIA_IDACAQ_TZ0_COARSE1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12870;"	d
+RG_GEMINIA_IDACAQ_TZ0_COARSE2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12859;"	d
+RG_GEMINIA_IDACAQ_TZ0_COARSE2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12857;"	d
+RG_GEMINIA_IDACAQ_TZ0_COARSE2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12856;"	d
+RG_GEMINIA_IDACAQ_TZ0_COARSE2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12858;"	d
+RG_GEMINIA_IDACAQ_TZ0_COARSE2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12860;"	d
+RG_GEMINIA_IDACAQ_TZ0_COARSE3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12849;"	d
+RG_GEMINIA_IDACAQ_TZ0_COARSE3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12847;"	d
+RG_GEMINIA_IDACAQ_TZ0_COARSE3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12846;"	d
+RG_GEMINIA_IDACAQ_TZ0_COARSE3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12848;"	d
+RG_GEMINIA_IDACAQ_TZ0_COARSE3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12850;"	d
+RG_GEMINIA_IDACAQ_TZ0_COARSE4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12839;"	d
+RG_GEMINIA_IDACAQ_TZ0_COARSE4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12837;"	d
+RG_GEMINIA_IDACAQ_TZ0_COARSE4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12836;"	d
+RG_GEMINIA_IDACAQ_TZ0_COARSE4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12838;"	d
+RG_GEMINIA_IDACAQ_TZ0_COARSE4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12840;"	d
+RG_GEMINIA_IDACAQ_TZ1_COARSE0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12929;"	d
+RG_GEMINIA_IDACAQ_TZ1_COARSE0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12927;"	d
+RG_GEMINIA_IDACAQ_TZ1_COARSE0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12926;"	d
+RG_GEMINIA_IDACAQ_TZ1_COARSE0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12928;"	d
+RG_GEMINIA_IDACAQ_TZ1_COARSE0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12930;"	d
+RG_GEMINIA_IDACAQ_TZ1_COARSE1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12919;"	d
+RG_GEMINIA_IDACAQ_TZ1_COARSE1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12917;"	d
+RG_GEMINIA_IDACAQ_TZ1_COARSE1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12916;"	d
+RG_GEMINIA_IDACAQ_TZ1_COARSE1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12918;"	d
+RG_GEMINIA_IDACAQ_TZ1_COARSE1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12920;"	d
+RG_GEMINIA_IDACAQ_TZ1_COARSE2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12909;"	d
+RG_GEMINIA_IDACAQ_TZ1_COARSE2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12907;"	d
+RG_GEMINIA_IDACAQ_TZ1_COARSE2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12906;"	d
+RG_GEMINIA_IDACAQ_TZ1_COARSE2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12908;"	d
+RG_GEMINIA_IDACAQ_TZ1_COARSE2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12910;"	d
+RG_GEMINIA_IDACAQ_TZ1_COARSE3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12899;"	d
+RG_GEMINIA_IDACAQ_TZ1_COARSE3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12897;"	d
+RG_GEMINIA_IDACAQ_TZ1_COARSE3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12896;"	d
+RG_GEMINIA_IDACAQ_TZ1_COARSE3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12898;"	d
+RG_GEMINIA_IDACAQ_TZ1_COARSE3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12900;"	d
+RG_GEMINIA_IDACAQ_TZ1_COARSE4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12889;"	d
+RG_GEMINIA_IDACAQ_TZ1_COARSE4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12887;"	d
+RG_GEMINIA_IDACAQ_TZ1_COARSE4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12886;"	d
+RG_GEMINIA_IDACAQ_TZ1_COARSE4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12888;"	d
+RG_GEMINIA_IDACAQ_TZ1_COARSE4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12890;"	d
+RG_GEMINIA_IQ_SWAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13519;"	d
+RG_GEMINIA_IQ_SWAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13517;"	d
+RG_GEMINIA_IQ_SWAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13516;"	d
+RG_GEMINIA_IQ_SWAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13518;"	d
+RG_GEMINIA_IQ_SWAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13520;"	d
+RG_GEMINIA_I_INV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13514;"	d
+RG_GEMINIA_I_INV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13512;"	d
+RG_GEMINIA_I_INV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13511;"	d
+RG_GEMINIA_I_INV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13513;"	d
+RG_GEMINIA_I_INV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13515;"	d
+RG_GEMINIA_LDO_CP_FC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11829;"	d
+RG_GEMINIA_LDO_CP_FC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11827;"	d
+RG_GEMINIA_LDO_CP_FC_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11824;"	d
+RG_GEMINIA_LDO_CP_FC_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11822;"	d
+RG_GEMINIA_LDO_CP_FC_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11821;"	d
+RG_GEMINIA_LDO_CP_FC_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11823;"	d
+RG_GEMINIA_LDO_CP_FC_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11825;"	d
+RG_GEMINIA_LDO_CP_FC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11826;"	d
+RG_GEMINIA_LDO_CP_FC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11828;"	d
+RG_GEMINIA_LDO_CP_FC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11830;"	d
+RG_GEMINIA_LDO_DIV_FC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11839;"	d
+RG_GEMINIA_LDO_DIV_FC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11837;"	d
+RG_GEMINIA_LDO_DIV_FC_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11834;"	d
+RG_GEMINIA_LDO_DIV_FC_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11832;"	d
+RG_GEMINIA_LDO_DIV_FC_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11831;"	d
+RG_GEMINIA_LDO_DIV_FC_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11833;"	d
+RG_GEMINIA_LDO_DIV_FC_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11835;"	d
+RG_GEMINIA_LDO_DIV_FC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11836;"	d
+RG_GEMINIA_LDO_DIV_FC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11838;"	d
+RG_GEMINIA_LDO_DIV_FC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11840;"	d
+RG_GEMINIA_LDO_LEVEL_ABB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10589;"	d
+RG_GEMINIA_LDO_LEVEL_ABB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10587;"	d
+RG_GEMINIA_LDO_LEVEL_ABB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10586;"	d
+RG_GEMINIA_LDO_LEVEL_ABB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10588;"	d
+RG_GEMINIA_LDO_LEVEL_ABB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10590;"	d
+RG_GEMINIA_LDO_LEVEL_ADC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10594;"	d
+RG_GEMINIA_LDO_LEVEL_ADC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10592;"	d
+RG_GEMINIA_LDO_LEVEL_ADC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10591;"	d
+RG_GEMINIA_LDO_LEVEL_ADC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10593;"	d
+RG_GEMINIA_LDO_LEVEL_ADC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10595;"	d
+RG_GEMINIA_LDO_LEVEL_DAC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10599;"	d
+RG_GEMINIA_LDO_LEVEL_DAC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10597;"	d
+RG_GEMINIA_LDO_LEVEL_DAC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10596;"	d
+RG_GEMINIA_LDO_LEVEL_DAC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10598;"	d
+RG_GEMINIA_LDO_LEVEL_DAC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10600;"	d
+RG_GEMINIA_LDO_LEVEL_EFUSE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13914;"	d
+RG_GEMINIA_LDO_LEVEL_EFUSE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13912;"	d
+RG_GEMINIA_LDO_LEVEL_EFUSE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13911;"	d
+RG_GEMINIA_LDO_LEVEL_EFUSE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13913;"	d
+RG_GEMINIA_LDO_LEVEL_EFUSE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13915;"	d
+RG_GEMINIA_LDO_LEVEL_RX_FE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10584;"	d
+RG_GEMINIA_LDO_LEVEL_RX_FE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10582;"	d
+RG_GEMINIA_LDO_LEVEL_RX_FE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10581;"	d
+RG_GEMINIA_LDO_LEVEL_RX_FE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10583;"	d
+RG_GEMINIA_LDO_LEVEL_RX_FE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10585;"	d
+RG_GEMINIA_LDO_LO_FC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11849;"	d
+RG_GEMINIA_LDO_LO_FC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11847;"	d
+RG_GEMINIA_LDO_LO_FC_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11844;"	d
+RG_GEMINIA_LDO_LO_FC_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11842;"	d
+RG_GEMINIA_LDO_LO_FC_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11841;"	d
+RG_GEMINIA_LDO_LO_FC_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11843;"	d
+RG_GEMINIA_LDO_LO_FC_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11845;"	d
+RG_GEMINIA_LDO_LO_FC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11846;"	d
+RG_GEMINIA_LDO_LO_FC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11848;"	d
+RG_GEMINIA_LDO_LO_FC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11850;"	d
+RG_GEMINIA_LDO_RX_ABB_EN_BYP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10564;"	d
+RG_GEMINIA_LDO_RX_ABB_EN_BYP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10562;"	d
+RG_GEMINIA_LDO_RX_ABB_EN_BYP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10561;"	d
+RG_GEMINIA_LDO_RX_ABB_EN_BYP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10563;"	d
+RG_GEMINIA_LDO_RX_ABB_EN_BYP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10565;"	d
+RG_GEMINIA_LDO_RX_ADC_EN_BYP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10569;"	d
+RG_GEMINIA_LDO_RX_ADC_EN_BYP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10567;"	d
+RG_GEMINIA_LDO_RX_ADC_EN_BYP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10566;"	d
+RG_GEMINIA_LDO_RX_ADC_EN_BYP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10568;"	d
+RG_GEMINIA_LDO_RX_ADC_EN_BYP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10570;"	d
+RG_GEMINIA_LDO_RX_FE_EN_BYP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10559;"	d
+RG_GEMINIA_LDO_RX_FE_EN_BYP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10557;"	d
+RG_GEMINIA_LDO_RX_FE_EN_BYP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10556;"	d
+RG_GEMINIA_LDO_RX_FE_EN_BYP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10558;"	d
+RG_GEMINIA_LDO_RX_FE_EN_BYP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10560;"	d
+RG_GEMINIA_LDO_TX_DAC_EN_BYP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10574;"	d
+RG_GEMINIA_LDO_TX_DAC_EN_BYP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10572;"	d
+RG_GEMINIA_LDO_TX_DAC_EN_BYP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10571;"	d
+RG_GEMINIA_LDO_TX_DAC_EN_BYP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10573;"	d
+RG_GEMINIA_LDO_TX_DAC_EN_BYP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10575;"	d
+RG_GEMINIA_LDO_VCO_FC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11859;"	d
+RG_GEMINIA_LDO_VCO_FC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11857;"	d
+RG_GEMINIA_LDO_VCO_FC_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11854;"	d
+RG_GEMINIA_LDO_VCO_FC_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11852;"	d
+RG_GEMINIA_LDO_VCO_FC_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11851;"	d
+RG_GEMINIA_LDO_VCO_FC_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11853;"	d
+RG_GEMINIA_LDO_VCO_FC_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11855;"	d
+RG_GEMINIA_LDO_VCO_FC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11856;"	d
+RG_GEMINIA_LDO_VCO_FC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11858;"	d
+RG_GEMINIA_LDO_VCO_FC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11860;"	d
+RG_GEMINIA_LDO_VCO_RCF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11864;"	d
+RG_GEMINIA_LDO_VCO_RCF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11862;"	d
+RG_GEMINIA_LDO_VCO_RCF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11861;"	d
+RG_GEMINIA_LDO_VCO_RCF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11863;"	d
+RG_GEMINIA_LDO_VCO_RCF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11865;"	d
+RG_GEMINIA_LOAD_RFTABLE_RDY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13874;"	d
+RG_GEMINIA_LOAD_RFTABLE_RDY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13872;"	d
+RG_GEMINIA_LOAD_RFTABLE_RDY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13871;"	d
+RG_GEMINIA_LOAD_RFTABLE_RDY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13873;"	d
+RG_GEMINIA_LOAD_RFTABLE_RDY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13875;"	d
+RG_GEMINIA_LO_UP_CH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13469;"	d
+RG_GEMINIA_LO_UP_CH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13467;"	d
+RG_GEMINIA_LO_UP_CH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13466;"	d
+RG_GEMINIA_LO_UP_CH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13468;"	d
+RG_GEMINIA_LO_UP_CH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13470;"	d
+RG_GEMINIA_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10254;"	d
+RG_GEMINIA_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10252;"	d
+RG_GEMINIA_MODE_LATCH_LMT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14434;"	d
+RG_GEMINIA_MODE_LATCH_LMT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14432;"	d
+RG_GEMINIA_MODE_LATCH_LMT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14431;"	d
+RG_GEMINIA_MODE_LATCH_LMT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14433;"	d
+RG_GEMINIA_MODE_LATCH_LMT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14435;"	d
+RG_GEMINIA_MODE_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10229;"	d
+RG_GEMINIA_MODE_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10227;"	d
+RG_GEMINIA_MODE_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10226;"	d
+RG_GEMINIA_MODE_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10228;"	d
+RG_GEMINIA_MODE_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10230;"	d
+RG_GEMINIA_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10251;"	d
+RG_GEMINIA_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10253;"	d
+RG_GEMINIA_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10255;"	d
+RG_GEMINIA_NFRAC_DELTA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13459;"	d
+RG_GEMINIA_NFRAC_DELTA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13457;"	d
+RG_GEMINIA_NFRAC_DELTA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13456;"	d
+RG_GEMINIA_NFRAC_DELTA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13458;"	d
+RG_GEMINIA_NFRAC_DELTA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13460;"	d
+RG_GEMINIA_PAD_MUX_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14429;"	d
+RG_GEMINIA_PAD_MUX_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14427;"	d
+RG_GEMINIA_PAD_MUX_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14426;"	d
+RG_GEMINIA_PAD_MUX_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14428;"	d
+RG_GEMINIA_PAD_MUX_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14430;"	d
+RG_GEMINIA_PGAG_DPDCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13389;"	d
+RG_GEMINIA_PGAG_DPDCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13387;"	d
+RG_GEMINIA_PGAG_DPDCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13386;"	d
+RG_GEMINIA_PGAG_DPDCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13388;"	d
+RG_GEMINIA_PGAG_DPDCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13390;"	d
+RG_GEMINIA_PGAG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10269;"	d
+RG_GEMINIA_PGAG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10267;"	d
+RG_GEMINIA_PGAG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10266;"	d
+RG_GEMINIA_PGAG_RCCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13354;"	d
+RG_GEMINIA_PGAG_RCCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13352;"	d
+RG_GEMINIA_PGAG_RCCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13351;"	d
+RG_GEMINIA_PGAG_RCCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13353;"	d
+RG_GEMINIA_PGAG_RCCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13355;"	d
+RG_GEMINIA_PGAG_RXIQCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13374;"	d
+RG_GEMINIA_PGAG_RXIQCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13372;"	d
+RG_GEMINIA_PGAG_RXIQCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13371;"	d
+RG_GEMINIA_PGAG_RXIQCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13373;"	d
+RG_GEMINIA_PGAG_RXIQCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13375;"	d
+RG_GEMINIA_PGAG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10268;"	d
+RG_GEMINIA_PGAG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10270;"	d
+RG_GEMINIA_PGAG_TXCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13359;"	d
+RG_GEMINIA_PGAG_TXCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13357;"	d
+RG_GEMINIA_PGAG_TXCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13356;"	d
+RG_GEMINIA_PGAG_TXCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13358;"	d
+RG_GEMINIA_PGAG_TXCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13360;"	d
+RG_GEMINIA_PHASE_17P5M_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13744;"	d
+RG_GEMINIA_PHASE_17P5M_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13742;"	d
+RG_GEMINIA_PHASE_17P5M_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13741;"	d
+RG_GEMINIA_PHASE_17P5M_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13743;"	d
+RG_GEMINIA_PHASE_17P5M_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13745;"	d
+RG_GEMINIA_PHASE_1M_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13759;"	d
+RG_GEMINIA_PHASE_1M_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13757;"	d
+RG_GEMINIA_PHASE_1M_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13756;"	d
+RG_GEMINIA_PHASE_1M_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13758;"	d
+RG_GEMINIA_PHASE_1M_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13760;"	d
+RG_GEMINIA_PHASE_2P5M_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13749;"	d
+RG_GEMINIA_PHASE_2P5M_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13747;"	d
+RG_GEMINIA_PHASE_2P5M_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13746;"	d
+RG_GEMINIA_PHASE_2P5M_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13748;"	d
+RG_GEMINIA_PHASE_2P5M_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13750;"	d
+RG_GEMINIA_PHASE_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13679;"	d
+RG_GEMINIA_PHASE_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13677;"	d
+RG_GEMINIA_PHASE_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13676;"	d
+RG_GEMINIA_PHASE_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13678;"	d
+RG_GEMINIA_PHASE_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13680;"	d
+RG_GEMINIA_PHASE_RXIQ_1M_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13754;"	d
+RG_GEMINIA_PHASE_RXIQ_1M_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13752;"	d
+RG_GEMINIA_PHASE_RXIQ_1M_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13751;"	d
+RG_GEMINIA_PHASE_RXIQ_1M_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13753;"	d
+RG_GEMINIA_PHASE_RXIQ_1M_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13755;"	d
+RG_GEMINIA_PHASE_STEP_VALUE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13674;"	d
+RG_GEMINIA_PHASE_STEP_VALUE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13672;"	d
+RG_GEMINIA_PHASE_STEP_VALUE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13671;"	d
+RG_GEMINIA_PHASE_STEP_VALUE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13673;"	d
+RG_GEMINIA_PHASE_STEP_VALUE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13675;"	d
+RG_GEMINIA_PMU_ENTER_SLEEP_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14014;"	d
+RG_GEMINIA_PMU_ENTER_SLEEP_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14012;"	d
+RG_GEMINIA_PMU_ENTER_SLEEP_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14011;"	d
+RG_GEMINIA_PMU_ENTER_SLEEP_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14013;"	d
+RG_GEMINIA_PMU_ENTER_SLEEP_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14015;"	d
+RG_GEMINIA_Q_INV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13509;"	d
+RG_GEMINIA_Q_INV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13507;"	d
+RG_GEMINIA_Q_INV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13506;"	d
+RG_GEMINIA_Q_INV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13508;"	d
+RG_GEMINIA_Q_INV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13510;"	d
+RG_GEMINIA_RAM_00_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14444;"	d
+RG_GEMINIA_RAM_00_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14442;"	d
+RG_GEMINIA_RAM_00_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14441;"	d
+RG_GEMINIA_RAM_00_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14443;"	d
+RG_GEMINIA_RAM_00_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14445;"	d
+RG_GEMINIA_RAM_01_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14449;"	d
+RG_GEMINIA_RAM_01_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14447;"	d
+RG_GEMINIA_RAM_01_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14446;"	d
+RG_GEMINIA_RAM_01_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14448;"	d
+RG_GEMINIA_RAM_01_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14450;"	d
+RG_GEMINIA_RAM_02_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14454;"	d
+RG_GEMINIA_RAM_02_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14452;"	d
+RG_GEMINIA_RAM_02_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14451;"	d
+RG_GEMINIA_RAM_02_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14453;"	d
+RG_GEMINIA_RAM_02_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14455;"	d
+RG_GEMINIA_RAM_03_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14459;"	d
+RG_GEMINIA_RAM_03_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14457;"	d
+RG_GEMINIA_RAM_03_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14456;"	d
+RG_GEMINIA_RAM_03_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14458;"	d
+RG_GEMINIA_RAM_03_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14460;"	d
+RG_GEMINIA_RAM_04_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14464;"	d
+RG_GEMINIA_RAM_04_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14462;"	d
+RG_GEMINIA_RAM_04_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14461;"	d
+RG_GEMINIA_RAM_04_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14463;"	d
+RG_GEMINIA_RAM_04_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14465;"	d
+RG_GEMINIA_RAM_05_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14469;"	d
+RG_GEMINIA_RAM_05_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14467;"	d
+RG_GEMINIA_RAM_05_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14466;"	d
+RG_GEMINIA_RAM_05_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14468;"	d
+RG_GEMINIA_RAM_05_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14470;"	d
+RG_GEMINIA_RAM_06_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14474;"	d
+RG_GEMINIA_RAM_06_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14472;"	d
+RG_GEMINIA_RAM_06_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14471;"	d
+RG_GEMINIA_RAM_06_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14473;"	d
+RG_GEMINIA_RAM_06_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14475;"	d
+RG_GEMINIA_RAM_07_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14479;"	d
+RG_GEMINIA_RAM_07_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14477;"	d
+RG_GEMINIA_RAM_07_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14476;"	d
+RG_GEMINIA_RAM_07_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14478;"	d
+RG_GEMINIA_RAM_07_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14480;"	d
+RG_GEMINIA_RAM_08_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14484;"	d
+RG_GEMINIA_RAM_08_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14482;"	d
+RG_GEMINIA_RAM_08_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14481;"	d
+RG_GEMINIA_RAM_08_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14483;"	d
+RG_GEMINIA_RAM_08_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14485;"	d
+RG_GEMINIA_RAM_09_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14489;"	d
+RG_GEMINIA_RAM_09_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14487;"	d
+RG_GEMINIA_RAM_09_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14486;"	d
+RG_GEMINIA_RAM_09_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14488;"	d
+RG_GEMINIA_RAM_09_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14490;"	d
+RG_GEMINIA_RAM_10_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14494;"	d
+RG_GEMINIA_RAM_10_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14492;"	d
+RG_GEMINIA_RAM_10_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14491;"	d
+RG_GEMINIA_RAM_10_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14493;"	d
+RG_GEMINIA_RAM_10_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14495;"	d
+RG_GEMINIA_RAM_11_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14499;"	d
+RG_GEMINIA_RAM_11_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14497;"	d
+RG_GEMINIA_RAM_11_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14496;"	d
+RG_GEMINIA_RAM_11_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14498;"	d
+RG_GEMINIA_RAM_11_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14500;"	d
+RG_GEMINIA_RAM_12_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14504;"	d
+RG_GEMINIA_RAM_12_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14502;"	d
+RG_GEMINIA_RAM_12_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14501;"	d
+RG_GEMINIA_RAM_12_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14503;"	d
+RG_GEMINIA_RAM_12_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14505;"	d
+RG_GEMINIA_RAM_13_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14509;"	d
+RG_GEMINIA_RAM_13_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14507;"	d
+RG_GEMINIA_RAM_13_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14506;"	d
+RG_GEMINIA_RAM_13_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14508;"	d
+RG_GEMINIA_RAM_13_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14510;"	d
+RG_GEMINIA_RAM_14_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14514;"	d
+RG_GEMINIA_RAM_14_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14512;"	d
+RG_GEMINIA_RAM_14_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14511;"	d
+RG_GEMINIA_RAM_14_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14513;"	d
+RG_GEMINIA_RAM_14_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14515;"	d
+RG_GEMINIA_RAM_15_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14519;"	d
+RG_GEMINIA_RAM_15_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14517;"	d
+RG_GEMINIA_RAM_15_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14516;"	d
+RG_GEMINIA_RAM_15_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14518;"	d
+RG_GEMINIA_RAM_15_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14520;"	d
+RG_GEMINIA_RAM_16_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14524;"	d
+RG_GEMINIA_RAM_16_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14522;"	d
+RG_GEMINIA_RAM_16_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14521;"	d
+RG_GEMINIA_RAM_16_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14523;"	d
+RG_GEMINIA_RAM_16_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14525;"	d
+RG_GEMINIA_RAM_17_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14529;"	d
+RG_GEMINIA_RAM_17_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14527;"	d
+RG_GEMINIA_RAM_17_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14526;"	d
+RG_GEMINIA_RAM_17_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14528;"	d
+RG_GEMINIA_RAM_17_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14530;"	d
+RG_GEMINIA_RAM_18_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14534;"	d
+RG_GEMINIA_RAM_18_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14532;"	d
+RG_GEMINIA_RAM_18_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14531;"	d
+RG_GEMINIA_RAM_18_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14533;"	d
+RG_GEMINIA_RAM_18_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14535;"	d
+RG_GEMINIA_RAM_19_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14539;"	d
+RG_GEMINIA_RAM_19_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14537;"	d
+RG_GEMINIA_RAM_19_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14536;"	d
+RG_GEMINIA_RAM_19_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14538;"	d
+RG_GEMINIA_RAM_19_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14540;"	d
+RG_GEMINIA_RAM_20_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14544;"	d
+RG_GEMINIA_RAM_20_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14542;"	d
+RG_GEMINIA_RAM_20_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14541;"	d
+RG_GEMINIA_RAM_20_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14543;"	d
+RG_GEMINIA_RAM_20_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14545;"	d
+RG_GEMINIA_RAM_21_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14549;"	d
+RG_GEMINIA_RAM_21_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14547;"	d
+RG_GEMINIA_RAM_21_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14546;"	d
+RG_GEMINIA_RAM_21_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14548;"	d
+RG_GEMINIA_RAM_21_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14550;"	d
+RG_GEMINIA_RAM_22_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14554;"	d
+RG_GEMINIA_RAM_22_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14552;"	d
+RG_GEMINIA_RAM_22_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14551;"	d
+RG_GEMINIA_RAM_22_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14553;"	d
+RG_GEMINIA_RAM_22_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14555;"	d
+RG_GEMINIA_RAM_23_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14559;"	d
+RG_GEMINIA_RAM_23_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14557;"	d
+RG_GEMINIA_RAM_23_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14556;"	d
+RG_GEMINIA_RAM_23_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14558;"	d
+RG_GEMINIA_RAM_23_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14560;"	d
+RG_GEMINIA_RAM_24_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14564;"	d
+RG_GEMINIA_RAM_24_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14562;"	d
+RG_GEMINIA_RAM_24_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14561;"	d
+RG_GEMINIA_RAM_24_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14563;"	d
+RG_GEMINIA_RAM_24_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14565;"	d
+RG_GEMINIA_RAM_25_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14569;"	d
+RG_GEMINIA_RAM_25_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14567;"	d
+RG_GEMINIA_RAM_25_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14566;"	d
+RG_GEMINIA_RAM_25_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14568;"	d
+RG_GEMINIA_RAM_25_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14570;"	d
+RG_GEMINIA_RAM_26_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14574;"	d
+RG_GEMINIA_RAM_26_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14572;"	d
+RG_GEMINIA_RAM_26_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14571;"	d
+RG_GEMINIA_RAM_26_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14573;"	d
+RG_GEMINIA_RAM_26_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14575;"	d
+RG_GEMINIA_RAM_27_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14579;"	d
+RG_GEMINIA_RAM_27_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14577;"	d
+RG_GEMINIA_RAM_27_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14576;"	d
+RG_GEMINIA_RAM_27_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14578;"	d
+RG_GEMINIA_RAM_27_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14580;"	d
+RG_GEMINIA_RAM_28_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14584;"	d
+RG_GEMINIA_RAM_28_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14582;"	d
+RG_GEMINIA_RAM_28_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14581;"	d
+RG_GEMINIA_RAM_28_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14583;"	d
+RG_GEMINIA_RAM_28_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14585;"	d
+RG_GEMINIA_RAM_29_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14589;"	d
+RG_GEMINIA_RAM_29_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14587;"	d
+RG_GEMINIA_RAM_29_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14586;"	d
+RG_GEMINIA_RAM_29_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14588;"	d
+RG_GEMINIA_RAM_29_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14590;"	d
+RG_GEMINIA_RAM_30_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14594;"	d
+RG_GEMINIA_RAM_30_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14592;"	d
+RG_GEMINIA_RAM_30_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14591;"	d
+RG_GEMINIA_RAM_30_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14593;"	d
+RG_GEMINIA_RAM_30_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14595;"	d
+RG_GEMINIA_RAM_31_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14599;"	d
+RG_GEMINIA_RAM_31_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14597;"	d
+RG_GEMINIA_RAM_31_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14596;"	d
+RG_GEMINIA_RAM_31_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14598;"	d
+RG_GEMINIA_RAM_31_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14600;"	d
+RG_GEMINIA_RCCAL_POLAR_INV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13709;"	d
+RG_GEMINIA_RCCAL_POLAR_INV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13707;"	d
+RG_GEMINIA_RCCAL_POLAR_INV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13706;"	d
+RG_GEMINIA_RCCAL_POLAR_INV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13708;"	d
+RG_GEMINIA_RCCAL_POLAR_INV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13710;"	d
+RG_GEMINIA_RFG_DPDCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13384;"	d
+RG_GEMINIA_RFG_DPDCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13382;"	d
+RG_GEMINIA_RFG_DPDCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13381;"	d
+RG_GEMINIA_RFG_DPDCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13383;"	d
+RG_GEMINIA_RFG_DPDCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13385;"	d
+RG_GEMINIA_RFG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10264;"	d
+RG_GEMINIA_RFG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10262;"	d
+RG_GEMINIA_RFG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10261;"	d
+RG_GEMINIA_RFG_RXIQCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13369;"	d
+RG_GEMINIA_RFG_RXIQCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13367;"	d
+RG_GEMINIA_RFG_RXIQCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13366;"	d
+RG_GEMINIA_RFG_RXIQCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13368;"	d
+RG_GEMINIA_RFG_RXIQCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13370;"	d
+RG_GEMINIA_RFG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10263;"	d
+RG_GEMINIA_RFG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10265;"	d
+RG_GEMINIA_RF_PHY_MODE_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14419;"	d
+RG_GEMINIA_RF_PHY_MODE_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14417;"	d
+RG_GEMINIA_RF_PHY_MODE_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14416;"	d
+RG_GEMINIA_RF_PHY_MODE_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14418;"	d
+RG_GEMINIA_RF_PHY_MODE_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14420;"	d
+RG_GEMINIA_RF_PHY_MODE_WIFI_MAC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14424;"	d
+RG_GEMINIA_RF_PHY_MODE_WIFI_MAC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14422;"	d
+RG_GEMINIA_RF_PHY_MODE_WIFI_MAC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14421;"	d
+RG_GEMINIA_RF_PHY_MODE_WIFI_MAC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14423;"	d
+RG_GEMINIA_RF_PHY_MODE_WIFI_MAC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14425;"	d
+RG_GEMINIA_RSSI_CLOCK_GATING_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10784;"	d
+RG_GEMINIA_RSSI_CLOCK_GATING_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10782;"	d
+RG_GEMINIA_RSSI_CLOCK_GATING_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10781;"	d
+RG_GEMINIA_RSSI_CLOCK_GATING_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10783;"	d
+RG_GEMINIA_RSSI_CLOCK_GATING_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10785;"	d
+RG_GEMINIA_RSSI_EDGE_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13499;"	d
+RG_GEMINIA_RSSI_EDGE_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13497;"	d
+RG_GEMINIA_RSSI_EDGE_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13496;"	d
+RG_GEMINIA_RSSI_EDGE_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13498;"	d
+RG_GEMINIA_RSSI_EDGE_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13500;"	d
+RG_GEMINIA_RTC_CAL_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13969;"	d
+RG_GEMINIA_RTC_CAL_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13967;"	d
+RG_GEMINIA_RTC_CAL_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13966;"	d
+RG_GEMINIA_RTC_CAL_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13968;"	d
+RG_GEMINIA_RTC_CAL_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13970;"	d
+RG_GEMINIA_RTC_CAL_TARGET_COUNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13959;"	d
+RG_GEMINIA_RTC_CAL_TARGET_COUNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13957;"	d
+RG_GEMINIA_RTC_CAL_TARGET_COUNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13956;"	d
+RG_GEMINIA_RTC_CAL_TARGET_COUNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13958;"	d
+RG_GEMINIA_RTC_CAL_TARGET_COUNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13960;"	d
+RG_GEMINIA_RTC_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14019;"	d
+RG_GEMINIA_RTC_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14017;"	d
+RG_GEMINIA_RTC_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14016;"	d
+RG_GEMINIA_RTC_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14018;"	d
+RG_GEMINIA_RTC_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14020;"	d
+RG_GEMINIA_RTC_INT_ALARM_MASK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14044;"	d
+RG_GEMINIA_RTC_INT_ALARM_MASK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14042;"	d
+RG_GEMINIA_RTC_INT_ALARM_MASK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14041;"	d
+RG_GEMINIA_RTC_INT_ALARM_MASK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14043;"	d
+RG_GEMINIA_RTC_INT_ALARM_MASK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14045;"	d
+RG_GEMINIA_RTC_INT_SEC_MASK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14039;"	d
+RG_GEMINIA_RTC_INT_SEC_MASK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14037;"	d
+RG_GEMINIA_RTC_INT_SEC_MASK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14036;"	d
+RG_GEMINIA_RTC_INT_SEC_MASK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14038;"	d
+RG_GEMINIA_RTC_INT_SEC_MASK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14040;"	d
+RG_GEMINIA_RTC_OFFSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13954;"	d
+RG_GEMINIA_RTC_OFFSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13952;"	d
+RG_GEMINIA_RTC_OFFSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13951;"	d
+RG_GEMINIA_RTC_OFFSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13953;"	d
+RG_GEMINIA_RTC_OFFSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13955;"	d
+RG_GEMINIA_RTC_OSC_RES_SW_MANUAL_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13979;"	d
+RG_GEMINIA_RTC_OSC_RES_SW_MANUAL_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13977;"	d
+RG_GEMINIA_RTC_OSC_RES_SW_MANUAL_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13976;"	d
+RG_GEMINIA_RTC_OSC_RES_SW_MANUAL_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13978;"	d
+RG_GEMINIA_RTC_OSC_RES_SW_MANUAL_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13980;"	d
+RG_GEMINIA_RTC_OSC_RES_SW_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13964;"	d
+RG_GEMINIA_RTC_OSC_RES_SW_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13962;"	d
+RG_GEMINIA_RTC_OSC_RES_SW_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13961;"	d
+RG_GEMINIA_RTC_OSC_RES_SW_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13963;"	d
+RG_GEMINIA_RTC_OSC_RES_SW_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13965;"	d
+RG_GEMINIA_RTC_RS1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13939;"	d
+RG_GEMINIA_RTC_RS1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13937;"	d
+RG_GEMINIA_RTC_RS1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13936;"	d
+RG_GEMINIA_RTC_RS1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13938;"	d
+RG_GEMINIA_RTC_RS1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13940;"	d
+RG_GEMINIA_RTC_RS2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13944;"	d
+RG_GEMINIA_RTC_RS2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13942;"	d
+RG_GEMINIA_RTC_RS2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13941;"	d
+RG_GEMINIA_RTC_RS2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13943;"	d
+RG_GEMINIA_RTC_RS2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13945;"	d
+RG_GEMINIA_RTC_SEC_ALARM_VALUE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14064;"	d
+RG_GEMINIA_RTC_SEC_ALARM_VALUE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14062;"	d
+RG_GEMINIA_RTC_SEC_ALARM_VALUE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14061;"	d
+RG_GEMINIA_RTC_SEC_ALARM_VALUE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14063;"	d
+RG_GEMINIA_RTC_SEC_ALARM_VALUE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14065;"	d
+RG_GEMINIA_RTC_SEC_START_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14059;"	d
+RG_GEMINIA_RTC_SEC_START_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14057;"	d
+RG_GEMINIA_RTC_SEC_START_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14056;"	d
+RG_GEMINIA_RTC_SEC_START_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14058;"	d
+RG_GEMINIA_RTC_SEC_START_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14060;"	d
+RG_GEMINIA_RXIQ_NOSHRK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13489;"	d
+RG_GEMINIA_RXIQ_NOSHRK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13487;"	d
+RG_GEMINIA_RXIQ_NOSHRK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13486;"	d
+RG_GEMINIA_RXIQ_NOSHRK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13488;"	d
+RG_GEMINIA_RXIQ_NOSHRK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13490;"	d
+RG_GEMINIA_RXRCCALQ_EN_BYP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10504;"	d
+RG_GEMINIA_RXRCCALQ_EN_BYP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10502;"	d
+RG_GEMINIA_RXRCCALQ_EN_BYP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10501;"	d
+RG_GEMINIA_RXRCCALQ_EN_BYP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10503;"	d
+RG_GEMINIA_RXRCCALQ_EN_BYP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10505;"	d
+RG_GEMINIA_RXRF_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13274;"	d
+RG_GEMINIA_RXRF_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13272;"	d
+RG_GEMINIA_RXRF_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13271;"	d
+RG_GEMINIA_RXRF_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13273;"	d
+RG_GEMINIA_RXRF_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13275;"	d
+RG_GEMINIA_RXRF_R2T_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13319;"	d
+RG_GEMINIA_RXRF_R2T_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13317;"	d
+RG_GEMINIA_RXRF_R2T_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13316;"	d
+RG_GEMINIA_RXRF_R2T_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13318;"	d
+RG_GEMINIA_RXRF_R2T_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13320;"	d
+RG_GEMINIA_RXRF_T2R_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13299;"	d
+RG_GEMINIA_RXRF_T2R_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13297;"	d
+RG_GEMINIA_RXRF_T2R_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13296;"	d
+RG_GEMINIA_RXRF_T2R_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13298;"	d
+RG_GEMINIA_RXRF_T2R_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13300;"	d
+RG_GEMINIA_RX_ABBOUT_TRI_STATE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10544;"	d
+RG_GEMINIA_RX_ABBOUT_TRI_STATE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10542;"	d
+RG_GEMINIA_RX_ABBOUT_TRI_STATE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10541;"	d
+RG_GEMINIA_RX_ABBOUT_TRI_STATE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10543;"	d
+RG_GEMINIA_RX_ABBOUT_TRI_STATE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10545;"	d
+RG_GEMINIA_RX_ADCRSSI_CLKSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10779;"	d
+RG_GEMINIA_RX_ADCRSSI_CLKSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10777;"	d
+RG_GEMINIA_RX_ADCRSSI_CLKSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10776;"	d
+RG_GEMINIA_RX_ADCRSSI_CLKSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10778;"	d
+RG_GEMINIA_RX_ADCRSSI_CLKSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10780;"	d
+RG_GEMINIA_RX_ADCRSSI_VCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10769;"	d
+RG_GEMINIA_RX_ADCRSSI_VCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10767;"	d
+RG_GEMINIA_RX_ADCRSSI_VCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10766;"	d
+RG_GEMINIA_RX_ADCRSSI_VCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10768;"	d
+RG_GEMINIA_RX_ADCRSSI_VCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10770;"	d
+RG_GEMINIA_RX_ADC_CLKSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11409;"	d
+RG_GEMINIA_RX_ADC_CLKSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11407;"	d
+RG_GEMINIA_RX_ADC_CLKSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11406;"	d
+RG_GEMINIA_RX_ADC_CLKSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11408;"	d
+RG_GEMINIA_RX_ADC_CLKSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11410;"	d
+RG_GEMINIA_RX_ADC_DNLEN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11414;"	d
+RG_GEMINIA_RX_ADC_DNLEN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11412;"	d
+RG_GEMINIA_RX_ADC_DNLEN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11411;"	d
+RG_GEMINIA_RX_ADC_DNLEN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11413;"	d
+RG_GEMINIA_RX_ADC_DNLEN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11415;"	d
+RG_GEMINIA_RX_ADC_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10349;"	d
+RG_GEMINIA_RX_ADC_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10347;"	d
+RG_GEMINIA_RX_ADC_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10346;"	d
+RG_GEMINIA_RX_ADC_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10348;"	d
+RG_GEMINIA_RX_ADC_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10350;"	d
+RG_GEMINIA_RX_ADC_METAEN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11419;"	d
+RG_GEMINIA_RX_ADC_METAEN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11417;"	d
+RG_GEMINIA_RX_ADC_METAEN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11416;"	d
+RG_GEMINIA_RX_ADC_METAEN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11418;"	d
+RG_GEMINIA_RX_ADC_METAEN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11420;"	d
+RG_GEMINIA_RX_ADC_TFLAG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11424;"	d
+RG_GEMINIA_RX_ADC_TFLAG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11422;"	d
+RG_GEMINIA_RX_ADC_TFLAG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11421;"	d
+RG_GEMINIA_RX_ADC_TFLAG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11423;"	d
+RG_GEMINIA_RX_ADC_TFLAG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11425;"	d
+RG_GEMINIA_RX_ADC_TSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11429;"	d
+RG_GEMINIA_RX_ADC_TSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11427;"	d
+RG_GEMINIA_RX_ADC_TSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11426;"	d
+RG_GEMINIA_RX_ADC_TSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11428;"	d
+RG_GEMINIA_RX_ADC_TSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11430;"	d
+RG_GEMINIA_RX_AGC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10249;"	d
+RG_GEMINIA_RX_AGC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10247;"	d
+RG_GEMINIA_RX_AGC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10246;"	d
+RG_GEMINIA_RX_AGC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10248;"	d
+RG_GEMINIA_RX_AGC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10250;"	d
+RG_GEMINIA_RX_DC_POLAR_INV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13704;"	d
+RG_GEMINIA_RX_DC_POLAR_INV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13702;"	d
+RG_GEMINIA_RX_DC_POLAR_INV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13701;"	d
+RG_GEMINIA_RX_DC_POLAR_INV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13703;"	d
+RG_GEMINIA_RX_DC_POLAR_INV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13705;"	d
+RG_GEMINIA_RX_DIV2_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10309;"	d
+RG_GEMINIA_RX_DIV2_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10307;"	d
+RG_GEMINIA_RX_DIV2_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10306;"	d
+RG_GEMINIA_RX_DIV2_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10308;"	d
+RG_GEMINIA_RX_DIV2_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10310;"	d
+RG_GEMINIA_RX_FILTER_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10339;"	d
+RG_GEMINIA_RX_FILTER_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10337;"	d
+RG_GEMINIA_RX_FILTER_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10336;"	d
+RG_GEMINIA_RX_FILTER_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10338;"	d
+RG_GEMINIA_RX_FILTER_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10340;"	d
+RG_GEMINIA_RX_GAIN_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10234;"	d
+RG_GEMINIA_RX_GAIN_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10232;"	d
+RG_GEMINIA_RX_GAIN_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10231;"	d
+RG_GEMINIA_RX_GAIN_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10233;"	d
+RG_GEMINIA_RX_GAIN_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10235;"	d
+RG_GEMINIA_RX_IQCAL_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13349;"	d
+RG_GEMINIA_RX_IQCAL_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13347;"	d
+RG_GEMINIA_RX_IQCAL_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13346;"	d
+RG_GEMINIA_RX_IQCAL_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13348;"	d
+RG_GEMINIA_RX_IQCAL_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13350;"	d
+RG_GEMINIA_RX_IQCAL_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10484;"	d
+RG_GEMINIA_RX_IQCAL_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10482;"	d
+RG_GEMINIA_RX_IQCAL_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10481;"	d
+RG_GEMINIA_RX_IQCAL_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10483;"	d
+RG_GEMINIA_RX_IQCAL_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10485;"	d
+RG_GEMINIA_RX_IQ_ALPHA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13474;"	d
+RG_GEMINIA_RX_IQ_ALPHA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13472;"	d
+RG_GEMINIA_RX_IQ_ALPHA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13471;"	d
+RG_GEMINIA_RX_IQ_ALPHA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13473;"	d
+RG_GEMINIA_RX_IQ_ALPHA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13475;"	d
+RG_GEMINIA_RX_IQ_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13484;"	d
+RG_GEMINIA_RX_IQ_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13482;"	d
+RG_GEMINIA_RX_IQ_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13481;"	d
+RG_GEMINIA_RX_IQ_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13483;"	d
+RG_GEMINIA_RX_IQ_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13485;"	d
+RG_GEMINIA_RX_IQ_THETA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13479;"	d
+RG_GEMINIA_RX_IQ_THETA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13477;"	d
+RG_GEMINIA_RX_IQ_THETA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13476;"	d
+RG_GEMINIA_RX_IQ_THETA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13478;"	d
+RG_GEMINIA_RX_IQ_THETA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13480;"	d
+RG_GEMINIA_RX_LNA_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10289;"	d
+RG_GEMINIA_RX_LNA_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10287;"	d
+RG_GEMINIA_RX_LNA_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10286;"	d
+RG_GEMINIA_RX_LNA_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10288;"	d
+RG_GEMINIA_RX_LNA_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10290;"	d
+RG_GEMINIA_RX_LNA_SETTLE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10829;"	d
+RG_GEMINIA_RX_LNA_SETTLE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10827;"	d
+RG_GEMINIA_RX_LNA_SETTLE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10826;"	d
+RG_GEMINIA_RX_LNA_SETTLE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10828;"	d
+RG_GEMINIA_RX_LNA_SETTLE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10830;"	d
+RG_GEMINIA_RX_LNA_TRI_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10824;"	d
+RG_GEMINIA_RX_LNA_TRI_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10822;"	d
+RG_GEMINIA_RX_LNA_TRI_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10821;"	d
+RG_GEMINIA_RX_LNA_TRI_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10823;"	d
+RG_GEMINIA_RX_LNA_TRI_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10825;"	d
+RG_GEMINIA_RX_LOBUF_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10319;"	d
+RG_GEMINIA_RX_LOBUF_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10317;"	d
+RG_GEMINIA_RX_LOBUF_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10316;"	d
+RG_GEMINIA_RX_LOBUF_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10318;"	d
+RG_GEMINIA_RX_LOBUF_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10320;"	d
+RG_GEMINIA_RX_MIXER_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10299;"	d
+RG_GEMINIA_RX_MIXER_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10297;"	d
+RG_GEMINIA_RX_MIXER_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10296;"	d
+RG_GEMINIA_RX_MIXER_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10298;"	d
+RG_GEMINIA_RX_MIXER_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10300;"	d
+RG_GEMINIA_RX_RCCAL_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13334;"	d
+RG_GEMINIA_RX_RCCAL_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13332;"	d
+RG_GEMINIA_RX_RCCAL_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13331;"	d
+RG_GEMINIA_RX_RCCAL_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13333;"	d
+RG_GEMINIA_RX_RCCAL_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13335;"	d
+RG_GEMINIA_RX_RCCAL_TARG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13699;"	d
+RG_GEMINIA_RX_RCCAL_TARG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13697;"	d
+RG_GEMINIA_RX_RCCAL_TARG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13696;"	d
+RG_GEMINIA_RX_RCCAL_TARG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13698;"	d
+RG_GEMINIA_RX_RCCAL_TARG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13700;"	d
+RG_GEMINIA_RX_REC_LPFCORNER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10774;"	d
+RG_GEMINIA_RX_REC_LPFCORNER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10772;"	d
+RG_GEMINIA_RX_REC_LPFCORNER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10771;"	d
+RG_GEMINIA_RX_REC_LPFCORNER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10773;"	d
+RG_GEMINIA_RX_REC_LPFCORNER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10775;"	d
+RG_GEMINIA_RX_RSSIADC_TH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13494;"	d
+RG_GEMINIA_RX_RSSIADC_TH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13492;"	d
+RG_GEMINIA_RX_RSSIADC_TH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13491;"	d
+RG_GEMINIA_RX_RSSIADC_TH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13493;"	d
+RG_GEMINIA_RX_RSSIADC_TH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13495;"	d
+RG_GEMINIA_RX_RSSI_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10359;"	d
+RG_GEMINIA_RX_RSSI_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10357;"	d
+RG_GEMINIA_RX_RSSI_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10356;"	d
+RG_GEMINIA_RX_RSSI_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10358;"	d
+RG_GEMINIA_RX_RSSI_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10360;"	d
+RG_GEMINIA_RX_TZ_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10329;"	d
+RG_GEMINIA_RX_TZ_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10327;"	d
+RG_GEMINIA_RX_TZ_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10326;"	d
+RG_GEMINIA_RX_TZ_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10328;"	d
+RG_GEMINIA_RX_TZ_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10330;"	d
+RG_GEMINIA_RX_TZ_OUT_TRISTATE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10469;"	d
+RG_GEMINIA_RX_TZ_OUT_TRISTATE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10467;"	d
+RG_GEMINIA_RX_TZ_OUT_TRISTATE_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10464;"	d
+RG_GEMINIA_RX_TZ_OUT_TRISTATE_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10462;"	d
+RG_GEMINIA_RX_TZ_OUT_TRISTATE_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10461;"	d
+RG_GEMINIA_RX_TZ_OUT_TRISTATE_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10463;"	d
+RG_GEMINIA_RX_TZ_OUT_TRISTATE_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10465;"	d
+RG_GEMINIA_RX_TZ_OUT_TRISTATE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10466;"	d
+RG_GEMINIA_RX_TZ_OUT_TRISTATE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10468;"	d
+RG_GEMINIA_RX_TZ_OUT_TRISTATE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10470;"	d
+RG_GEMINIA_SARADC_THERMAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11474;"	d
+RG_GEMINIA_SARADC_THERMAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11472;"	d
+RG_GEMINIA_SARADC_THERMAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11471;"	d
+RG_GEMINIA_SARADC_THERMAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11473;"	d
+RG_GEMINIA_SARADC_THERMAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11475;"	d
+RG_GEMINIA_SARADC_TSSI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11479;"	d
+RG_GEMINIA_SARADC_TSSI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11477;"	d
+RG_GEMINIA_SARADC_TSSI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11476;"	d
+RG_GEMINIA_SARADC_TSSI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11478;"	d
+RG_GEMINIA_SARADC_TSSI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11480;"	d
+RG_GEMINIA_SARADC_VRSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11464;"	d
+RG_GEMINIA_SARADC_VRSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11462;"	d
+RG_GEMINIA_SARADC_VRSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11461;"	d
+RG_GEMINIA_SARADC_VRSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11463;"	d
+RG_GEMINIA_SARADC_VRSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11465;"	d
+RG_GEMINIA_SEL_DPLL_CLK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13974;"	d
+RG_GEMINIA_SEL_DPLL_CLK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13972;"	d
+RG_GEMINIA_SEL_DPLL_CLK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13971;"	d
+RG_GEMINIA_SEL_DPLL_CLK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13973;"	d
+RG_GEMINIA_SEL_DPLL_CLK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13975;"	d
+RG_GEMINIA_SIGN_SWAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13524;"	d
+RG_GEMINIA_SIGN_SWAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13522;"	d
+RG_GEMINIA_SIGN_SWAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13521;"	d
+RG_GEMINIA_SIGN_SWAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13523;"	d
+RG_GEMINIA_SIGN_SWAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13525;"	d
+RG_GEMINIA_SLEEP_WAKE_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14009;"	d
+RG_GEMINIA_SLEEP_WAKE_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14007;"	d
+RG_GEMINIA_SLEEP_WAKE_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14006;"	d
+RG_GEMINIA_SLEEP_WAKE_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14008;"	d
+RG_GEMINIA_SLEEP_WAKE_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14010;"	d
+RG_GEMINIA_SPECTRUM_BW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13689;"	d
+RG_GEMINIA_SPECTRUM_BW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13687;"	d
+RG_GEMINIA_SPECTRUM_BW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13686;"	d
+RG_GEMINIA_SPECTRUM_BW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13688;"	d
+RG_GEMINIA_SPECTRUM_BW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13690;"	d
+RG_GEMINIA_SPECTRUM_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13694;"	d
+RG_GEMINIA_SPECTRUM_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13692;"	d
+RG_GEMINIA_SPECTRUM_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13691;"	d
+RG_GEMINIA_SPECTRUM_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13693;"	d
+RG_GEMINIA_SPECTRUM_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13695;"	d
+RG_GEMINIA_SPIS_MISO_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14159;"	d
+RG_GEMINIA_SPIS_MISO_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14157;"	d
+RG_GEMINIA_SPIS_MISO_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14156;"	d
+RG_GEMINIA_SPIS_MISO_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14158;"	d
+RG_GEMINIA_SPIS_MISO_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14160;"	d
+RG_GEMINIA_SX_AAC_DIS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11734;"	d
+RG_GEMINIA_SX_AAC_DIS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11732;"	d
+RG_GEMINIA_SX_AAC_DIS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11731;"	d
+RG_GEMINIA_SX_AAC_DIS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11733;"	d
+RG_GEMINIA_SX_AAC_DIS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11735;"	d
+RG_GEMINIA_SX_BTRX_SIDE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11899;"	d
+RG_GEMINIA_SX_BTRX_SIDE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11897;"	d
+RG_GEMINIA_SX_BTRX_SIDE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11896;"	d
+RG_GEMINIA_SX_BTRX_SIDE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11898;"	d
+RG_GEMINIA_SX_BTRX_SIDE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11900;"	d
+RG_GEMINIA_SX_CAL_INIT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11744;"	d
+RG_GEMINIA_SX_CAL_INIT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11742;"	d
+RG_GEMINIA_SX_CAL_INIT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11741;"	d
+RG_GEMINIA_SX_CAL_INIT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11743;"	d
+RG_GEMINIA_SX_CAL_INIT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11745;"	d
+RG_GEMINIA_SX_CHANNEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11909;"	d
+RG_GEMINIA_SX_CHANNEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11907;"	d
+RG_GEMINIA_SX_CHANNEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11906;"	d
+RG_GEMINIA_SX_CHANNEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11908;"	d
+RG_GEMINIA_SX_CHANNEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11910;"	d
+RG_GEMINIA_SX_CP_IOST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11949;"	d
+RG_GEMINIA_SX_CP_IOST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11947;"	d
+RG_GEMINIA_SX_CP_IOST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11946;"	d
+RG_GEMINIA_SX_CP_IOST_POL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11944;"	d
+RG_GEMINIA_SX_CP_IOST_POL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11942;"	d
+RG_GEMINIA_SX_CP_IOST_POL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11941;"	d
+RG_GEMINIA_SX_CP_IOST_POL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11943;"	d
+RG_GEMINIA_SX_CP_IOST_POL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11945;"	d
+RG_GEMINIA_SX_CP_IOST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11948;"	d
+RG_GEMINIA_SX_CP_IOST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11950;"	d
+RG_GEMINIA_SX_CP_ISEL50U_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11919;"	d
+RG_GEMINIA_SX_CP_ISEL50U_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11917;"	d
+RG_GEMINIA_SX_CP_ISEL50U_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11916;"	d
+RG_GEMINIA_SX_CP_ISEL50U_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11918;"	d
+RG_GEMINIA_SX_CP_ISEL50U_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11920;"	d
+RG_GEMINIA_SX_CP_ISEL50U_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11934;"	d
+RG_GEMINIA_SX_CP_ISEL50U_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11932;"	d
+RG_GEMINIA_SX_CP_ISEL50U_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11931;"	d
+RG_GEMINIA_SX_CP_ISEL50U_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11933;"	d
+RG_GEMINIA_SX_CP_ISEL50U_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11935;"	d
+RG_GEMINIA_SX_CP_ISEL_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11914;"	d
+RG_GEMINIA_SX_CP_ISEL_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11912;"	d
+RG_GEMINIA_SX_CP_ISEL_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11911;"	d
+RG_GEMINIA_SX_CP_ISEL_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11913;"	d
+RG_GEMINIA_SX_CP_ISEL_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11915;"	d
+RG_GEMINIA_SX_CP_ISEL_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11929;"	d
+RG_GEMINIA_SX_CP_ISEL_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11927;"	d
+RG_GEMINIA_SX_CP_ISEL_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11926;"	d
+RG_GEMINIA_SX_CP_ISEL_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11928;"	d
+RG_GEMINIA_SX_CP_ISEL_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11930;"	d
+RG_GEMINIA_SX_CP_KP_DOUB_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11924;"	d
+RG_GEMINIA_SX_CP_KP_DOUB_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11922;"	d
+RG_GEMINIA_SX_CP_KP_DOUB_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11921;"	d
+RG_GEMINIA_SX_CP_KP_DOUB_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11923;"	d
+RG_GEMINIA_SX_CP_KP_DOUB_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11925;"	d
+RG_GEMINIA_SX_CP_KP_DOUB_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11939;"	d
+RG_GEMINIA_SX_CP_KP_DOUB_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11937;"	d
+RG_GEMINIA_SX_CP_KP_DOUB_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11936;"	d
+RG_GEMINIA_SX_CP_KP_DOUB_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11938;"	d
+RG_GEMINIA_SX_CP_KP_DOUB_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11940;"	d
+RG_GEMINIA_SX_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13254;"	d
+RG_GEMINIA_SX_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13252;"	d
+RG_GEMINIA_SX_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13251;"	d
+RG_GEMINIA_SX_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13253;"	d
+RG_GEMINIA_SX_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13255;"	d
+RG_GEMINIA_SX_DITHER_WEIGHT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12209;"	d
+RG_GEMINIA_SX_DITHER_WEIGHT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12207;"	d
+RG_GEMINIA_SX_DITHER_WEIGHT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12206;"	d
+RG_GEMINIA_SX_DITHER_WEIGHT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12208;"	d
+RG_GEMINIA_SX_DITHER_WEIGHT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12210;"	d
+RG_GEMINIA_SX_DIV_DMYBUF_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12189;"	d
+RG_GEMINIA_SX_DIV_DMYBUF_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12187;"	d
+RG_GEMINIA_SX_DIV_DMYBUF_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12186;"	d
+RG_GEMINIA_SX_DIV_DMYBUF_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12188;"	d
+RG_GEMINIA_SX_DIV_DMYBUF_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12190;"	d
+RG_GEMINIA_SX_DIV_PREVDD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12169;"	d
+RG_GEMINIA_SX_DIV_PREVDD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12167;"	d
+RG_GEMINIA_SX_DIV_PREVDD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12166;"	d
+RG_GEMINIA_SX_DIV_PREVDD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12168;"	d
+RG_GEMINIA_SX_DIV_PREVDD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12170;"	d
+RG_GEMINIA_SX_DIV_PSCVDD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12174;"	d
+RG_GEMINIA_SX_DIV_PSCVDD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12172;"	d
+RG_GEMINIA_SX_DIV_PSCVDD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12171;"	d
+RG_GEMINIA_SX_DIV_PSCVDD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12173;"	d
+RG_GEMINIA_SX_DIV_PSCVDD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12175;"	d
+RG_GEMINIA_SX_DIV_RST_H_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12179;"	d
+RG_GEMINIA_SX_DIV_RST_H_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12177;"	d
+RG_GEMINIA_SX_DIV_RST_H_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12176;"	d
+RG_GEMINIA_SX_DIV_RST_H_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12178;"	d
+RG_GEMINIA_SX_DIV_RST_H_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12180;"	d
+RG_GEMINIA_SX_DIV_SDM_EDGE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12184;"	d
+RG_GEMINIA_SX_DIV_SDM_EDGE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12182;"	d
+RG_GEMINIA_SX_DIV_SDM_EDGE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12181;"	d
+RG_GEMINIA_SX_DIV_SDM_EDGE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12183;"	d
+RG_GEMINIA_SX_DIV_SDM_EDGE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12185;"	d
+RG_GEMINIA_SX_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11619;"	d
+RG_GEMINIA_SX_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11617;"	d
+RG_GEMINIA_SX_EN_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11614;"	d
+RG_GEMINIA_SX_EN_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11612;"	d
+RG_GEMINIA_SX_EN_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11611;"	d
+RG_GEMINIA_SX_EN_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11613;"	d
+RG_GEMINIA_SX_EN_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11615;"	d
+RG_GEMINIA_SX_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11616;"	d
+RG_GEMINIA_SX_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11618;"	d
+RG_GEMINIA_SX_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11620;"	d
+RG_GEMINIA_SX_FREF_DOUB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11894;"	d
+RG_GEMINIA_SX_FREF_DOUB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11892;"	d
+RG_GEMINIA_SX_FREF_DOUB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11891;"	d
+RG_GEMINIA_SX_FREF_DOUB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11893;"	d
+RG_GEMINIA_SX_FREF_DOUB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11895;"	d
+RG_GEMINIA_SX_LDO_CP_LEVEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10604;"	d
+RG_GEMINIA_SX_LDO_CP_LEVEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10602;"	d
+RG_GEMINIA_SX_LDO_CP_LEVEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10601;"	d
+RG_GEMINIA_SX_LDO_CP_LEVEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10603;"	d
+RG_GEMINIA_SX_LDO_CP_LEVEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10605;"	d
+RG_GEMINIA_SX_LDO_DIV_LEVEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10624;"	d
+RG_GEMINIA_SX_LDO_DIV_LEVEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10622;"	d
+RG_GEMINIA_SX_LDO_DIV_LEVEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10621;"	d
+RG_GEMINIA_SX_LDO_DIV_LEVEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10623;"	d
+RG_GEMINIA_SX_LDO_DIV_LEVEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10625;"	d
+RG_GEMINIA_SX_LDO_FCOFFT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11819;"	d
+RG_GEMINIA_SX_LDO_FCOFFT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11817;"	d
+RG_GEMINIA_SX_LDO_FCOFFT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11816;"	d
+RG_GEMINIA_SX_LDO_FCOFFT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11818;"	d
+RG_GEMINIA_SX_LDO_FCOFFT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11820;"	d
+RG_GEMINIA_SX_LDO_LO_LEVEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10609;"	d
+RG_GEMINIA_SX_LDO_LO_LEVEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10607;"	d
+RG_GEMINIA_SX_LDO_LO_LEVEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10606;"	d
+RG_GEMINIA_SX_LDO_LO_LEVEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10608;"	d
+RG_GEMINIA_SX_LDO_LO_LEVEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10610;"	d
+RG_GEMINIA_SX_LDO_VCO_LEVEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10619;"	d
+RG_GEMINIA_SX_LDO_VCO_LEVEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10617;"	d
+RG_GEMINIA_SX_LDO_VCO_LEVEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10616;"	d
+RG_GEMINIA_SX_LDO_VCO_LEVEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10618;"	d
+RG_GEMINIA_SX_LDO_VCO_LEVEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10620;"	d
+RG_GEMINIA_SX_LO_TIMES_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11904;"	d
+RG_GEMINIA_SX_LO_TIMES_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11902;"	d
+RG_GEMINIA_SX_LO_TIMES_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11901;"	d
+RG_GEMINIA_SX_LO_TIMES_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11903;"	d
+RG_GEMINIA_SX_LO_TIMES_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11905;"	d
+RG_GEMINIA_SX_LPF_C1_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11989;"	d
+RG_GEMINIA_SX_LPF_C1_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11987;"	d
+RG_GEMINIA_SX_LPF_C1_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11986;"	d
+RG_GEMINIA_SX_LPF_C1_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11988;"	d
+RG_GEMINIA_SX_LPF_C1_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11990;"	d
+RG_GEMINIA_SX_LPF_C1_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12014;"	d
+RG_GEMINIA_SX_LPF_C1_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12012;"	d
+RG_GEMINIA_SX_LPF_C1_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12011;"	d
+RG_GEMINIA_SX_LPF_C1_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12013;"	d
+RG_GEMINIA_SX_LPF_C1_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12015;"	d
+RG_GEMINIA_SX_LPF_C2_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11994;"	d
+RG_GEMINIA_SX_LPF_C2_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11992;"	d
+RG_GEMINIA_SX_LPF_C2_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11991;"	d
+RG_GEMINIA_SX_LPF_C2_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11993;"	d
+RG_GEMINIA_SX_LPF_C2_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11995;"	d
+RG_GEMINIA_SX_LPF_C2_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12019;"	d
+RG_GEMINIA_SX_LPF_C2_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12017;"	d
+RG_GEMINIA_SX_LPF_C2_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12016;"	d
+RG_GEMINIA_SX_LPF_C2_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12018;"	d
+RG_GEMINIA_SX_LPF_C2_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12020;"	d
+RG_GEMINIA_SX_LPF_C3_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11999;"	d
+RG_GEMINIA_SX_LPF_C3_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11997;"	d
+RG_GEMINIA_SX_LPF_C3_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11996;"	d
+RG_GEMINIA_SX_LPF_C3_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11998;"	d
+RG_GEMINIA_SX_LPF_C3_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12000;"	d
+RG_GEMINIA_SX_LPF_C3_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12024;"	d
+RG_GEMINIA_SX_LPF_C3_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12022;"	d
+RG_GEMINIA_SX_LPF_C3_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12021;"	d
+RG_GEMINIA_SX_LPF_C3_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12023;"	d
+RG_GEMINIA_SX_LPF_C3_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12025;"	d
+RG_GEMINIA_SX_LPF_R2_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12004;"	d
+RG_GEMINIA_SX_LPF_R2_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12002;"	d
+RG_GEMINIA_SX_LPF_R2_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12001;"	d
+RG_GEMINIA_SX_LPF_R2_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12003;"	d
+RG_GEMINIA_SX_LPF_R2_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12005;"	d
+RG_GEMINIA_SX_LPF_R2_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12029;"	d
+RG_GEMINIA_SX_LPF_R2_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12027;"	d
+RG_GEMINIA_SX_LPF_R2_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12026;"	d
+RG_GEMINIA_SX_LPF_R2_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12028;"	d
+RG_GEMINIA_SX_LPF_R2_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12030;"	d
+RG_GEMINIA_SX_LPF_R3_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12009;"	d
+RG_GEMINIA_SX_LPF_R3_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12007;"	d
+RG_GEMINIA_SX_LPF_R3_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12006;"	d
+RG_GEMINIA_SX_LPF_R3_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12008;"	d
+RG_GEMINIA_SX_LPF_R3_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12010;"	d
+RG_GEMINIA_SX_LPF_R3_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12034;"	d
+RG_GEMINIA_SX_LPF_R3_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12032;"	d
+RG_GEMINIA_SX_LPF_R3_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12031;"	d
+RG_GEMINIA_SX_LPF_R3_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12033;"	d
+RG_GEMINIA_SX_LPF_R3_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12035;"	d
+RG_GEMINIA_SX_LPF_VTUNE_TEST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12359;"	d
+RG_GEMINIA_SX_LPF_VTUNE_TEST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12357;"	d
+RG_GEMINIA_SX_LPF_VTUNE_TEST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12356;"	d
+RG_GEMINIA_SX_LPF_VTUNE_TEST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12358;"	d
+RG_GEMINIA_SX_LPF_VTUNE_TEST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12360;"	d
+RG_GEMINIA_SX_MOD_ORDER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12204;"	d
+RG_GEMINIA_SX_MOD_ORDER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12202;"	d
+RG_GEMINIA_SX_MOD_ORDER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12201;"	d
+RG_GEMINIA_SX_MOD_ORDER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12203;"	d
+RG_GEMINIA_SX_MOD_ORDER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12205;"	d
+RG_GEMINIA_SX_PFD_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11659;"	d
+RG_GEMINIA_SX_PFD_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11657;"	d
+RG_GEMINIA_SX_PFD_RST_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11654;"	d
+RG_GEMINIA_SX_PFD_RST_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11652;"	d
+RG_GEMINIA_SX_PFD_RST_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11651;"	d
+RG_GEMINIA_SX_PFD_RST_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11653;"	d
+RG_GEMINIA_SX_PFD_RST_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11655;"	d
+RG_GEMINIA_SX_PFD_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11656;"	d
+RG_GEMINIA_SX_PFD_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11658;"	d
+RG_GEMINIA_SX_PFD_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11660;"	d
+RG_GEMINIA_SX_PFD_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11954;"	d
+RG_GEMINIA_SX_PFD_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11952;"	d
+RG_GEMINIA_SX_PFD_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11951;"	d
+RG_GEMINIA_SX_PFD_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11953;"	d
+RG_GEMINIA_SX_PFD_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11955;"	d
+RG_GEMINIA_SX_PFD_SET1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11964;"	d
+RG_GEMINIA_SX_PFD_SET1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11962;"	d
+RG_GEMINIA_SX_PFD_SET1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11961;"	d
+RG_GEMINIA_SX_PFD_SET1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11963;"	d
+RG_GEMINIA_SX_PFD_SET1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11965;"	d
+RG_GEMINIA_SX_PFD_SET2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11969;"	d
+RG_GEMINIA_SX_PFD_SET2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11967;"	d
+RG_GEMINIA_SX_PFD_SET2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11966;"	d
+RG_GEMINIA_SX_PFD_SET2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11968;"	d
+RG_GEMINIA_SX_PFD_SET2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11970;"	d
+RG_GEMINIA_SX_PFD_SET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11959;"	d
+RG_GEMINIA_SX_PFD_SET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11957;"	d
+RG_GEMINIA_SX_PFD_SET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11956;"	d
+RG_GEMINIA_SX_PFD_SET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11958;"	d
+RG_GEMINIA_SX_PFD_SET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11960;"	d
+RG_GEMINIA_SX_PFD_TLSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11984;"	d
+RG_GEMINIA_SX_PFD_TLSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11982;"	d
+RG_GEMINIA_SX_PFD_TLSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11981;"	d
+RG_GEMINIA_SX_PFD_TLSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11983;"	d
+RG_GEMINIA_SX_PFD_TLSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11985;"	d
+RG_GEMINIA_SX_PFD_TRDN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11979;"	d
+RG_GEMINIA_SX_PFD_TRDN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11977;"	d
+RG_GEMINIA_SX_PFD_TRDN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11976;"	d
+RG_GEMINIA_SX_PFD_TRDN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11978;"	d
+RG_GEMINIA_SX_PFD_TRDN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11980;"	d
+RG_GEMINIA_SX_PFD_TRUP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11974;"	d
+RG_GEMINIA_SX_PFD_TRUP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11972;"	d
+RG_GEMINIA_SX_PFD_TRUP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11971;"	d
+RG_GEMINIA_SX_PFD_TRUP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11973;"	d
+RG_GEMINIA_SX_PFD_TRUP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11975;"	d
+RG_GEMINIA_SX_RFCH_MAP_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11884;"	d
+RG_GEMINIA_SX_RFCH_MAP_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11882;"	d
+RG_GEMINIA_SX_RFCH_MAP_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11881;"	d
+RG_GEMINIA_SX_RFCH_MAP_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11883;"	d
+RG_GEMINIA_SX_RFCH_MAP_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11885;"	d
+RG_GEMINIA_SX_RFCTRL_CH_10_8_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11879;"	d
+RG_GEMINIA_SX_RFCTRL_CH_10_8_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11877;"	d
+RG_GEMINIA_SX_RFCTRL_CH_10_8_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11876;"	d
+RG_GEMINIA_SX_RFCTRL_CH_10_8_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11878;"	d
+RG_GEMINIA_SX_RFCTRL_CH_10_8_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11880;"	d
+RG_GEMINIA_SX_RFCTRL_CH_7_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11874;"	d
+RG_GEMINIA_SX_RFCTRL_CH_7_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11872;"	d
+RG_GEMINIA_SX_RFCTRL_CH_7_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11871;"	d
+RG_GEMINIA_SX_RFCTRL_CH_7_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11873;"	d
+RG_GEMINIA_SX_RFCTRL_CH_7_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11875;"	d
+RG_GEMINIA_SX_RFCTRL_F_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11869;"	d
+RG_GEMINIA_SX_RFCTRL_F_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11867;"	d
+RG_GEMINIA_SX_RFCTRL_F_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11866;"	d
+RG_GEMINIA_SX_RFCTRL_F_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11868;"	d
+RG_GEMINIA_SX_RFCTRL_F_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11870;"	d
+RG_GEMINIA_SX_SBCAL_AW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11729;"	d
+RG_GEMINIA_SX_SBCAL_AW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11727;"	d
+RG_GEMINIA_SX_SBCAL_AW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11726;"	d
+RG_GEMINIA_SX_SBCAL_AW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11728;"	d
+RG_GEMINIA_SX_SBCAL_AW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11730;"	d
+RG_GEMINIA_SX_SBCAL_CT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12229;"	d
+RG_GEMINIA_SX_SBCAL_CT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12227;"	d
+RG_GEMINIA_SX_SBCAL_CT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12226;"	d
+RG_GEMINIA_SX_SBCAL_CT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12228;"	d
+RG_GEMINIA_SX_SBCAL_CT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12230;"	d
+RG_GEMINIA_SX_SBCAL_DIFFMIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12239;"	d
+RG_GEMINIA_SX_SBCAL_DIFFMIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12237;"	d
+RG_GEMINIA_SX_SBCAL_DIFFMIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12236;"	d
+RG_GEMINIA_SX_SBCAL_DIFFMIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12238;"	d
+RG_GEMINIA_SX_SBCAL_DIFFMIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12240;"	d
+RG_GEMINIA_SX_SBCAL_DIS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11724;"	d
+RG_GEMINIA_SX_SBCAL_DIS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11722;"	d
+RG_GEMINIA_SX_SBCAL_DIS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11721;"	d
+RG_GEMINIA_SX_SBCAL_DIS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11723;"	d
+RG_GEMINIA_SX_SBCAL_DIS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11725;"	d
+RG_GEMINIA_SX_SBCAL_NTARG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12249;"	d
+RG_GEMINIA_SX_SBCAL_NTARG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12247;"	d
+RG_GEMINIA_SX_SBCAL_NTARG_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12244;"	d
+RG_GEMINIA_SX_SBCAL_NTARG_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12242;"	d
+RG_GEMINIA_SX_SBCAL_NTARG_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12241;"	d
+RG_GEMINIA_SX_SBCAL_NTARG_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12243;"	d
+RG_GEMINIA_SX_SBCAL_NTARG_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12245;"	d
+RG_GEMINIA_SX_SBCAL_NTARG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12246;"	d
+RG_GEMINIA_SX_SBCAL_NTARG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12248;"	d
+RG_GEMINIA_SX_SBCAL_NTARG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12250;"	d
+RG_GEMINIA_SX_SBCAL_WT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12234;"	d
+RG_GEMINIA_SX_SBCAL_WT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12232;"	d
+RG_GEMINIA_SX_SBCAL_WT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12231;"	d
+RG_GEMINIA_SX_SBCAL_WT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12233;"	d
+RG_GEMINIA_SX_SBCAL_WT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12235;"	d
+RG_GEMINIA_SX_SUB_C0P5_DIS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12224;"	d
+RG_GEMINIA_SX_SUB_C0P5_DIS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12222;"	d
+RG_GEMINIA_SX_SUB_C0P5_DIS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12221;"	d
+RG_GEMINIA_SX_SUB_C0P5_DIS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12223;"	d
+RG_GEMINIA_SX_SUB_C0P5_DIS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12225;"	d
+RG_GEMINIA_SX_SUB_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12219;"	d
+RG_GEMINIA_SX_SUB_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12217;"	d
+RG_GEMINIA_SX_SUB_SEL_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12214;"	d
+RG_GEMINIA_SX_SUB_SEL_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12212;"	d
+RG_GEMINIA_SX_SUB_SEL_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12211;"	d
+RG_GEMINIA_SX_SUB_SEL_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12213;"	d
+RG_GEMINIA_SX_SUB_SEL_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12215;"	d
+RG_GEMINIA_SX_SUB_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12216;"	d
+RG_GEMINIA_SX_SUB_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12218;"	d
+RG_GEMINIA_SX_SUB_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12220;"	d
+RG_GEMINIA_SX_TTL_ACCUM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12334;"	d
+RG_GEMINIA_SX_TTL_ACCUM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12332;"	d
+RG_GEMINIA_SX_TTL_ACCUM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12331;"	d
+RG_GEMINIA_SX_TTL_ACCUM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12333;"	d
+RG_GEMINIA_SX_TTL_ACCUM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12335;"	d
+RG_GEMINIA_SX_TTL_CPT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12329;"	d
+RG_GEMINIA_SX_TTL_CPT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12327;"	d
+RG_GEMINIA_SX_TTL_CPT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12326;"	d
+RG_GEMINIA_SX_TTL_CPT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12328;"	d
+RG_GEMINIA_SX_TTL_CPT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12330;"	d
+RG_GEMINIA_SX_TTL_DIS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11739;"	d
+RG_GEMINIA_SX_TTL_DIS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11737;"	d
+RG_GEMINIA_SX_TTL_DIS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11736;"	d
+RG_GEMINIA_SX_TTL_DIS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11738;"	d
+RG_GEMINIA_SX_TTL_DIS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11740;"	d
+RG_GEMINIA_SX_TTL_FPT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12324;"	d
+RG_GEMINIA_SX_TTL_FPT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12322;"	d
+RG_GEMINIA_SX_TTL_FPT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12321;"	d
+RG_GEMINIA_SX_TTL_FPT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12323;"	d
+RG_GEMINIA_SX_TTL_FPT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12325;"	d
+RG_GEMINIA_SX_TTL_INIT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12319;"	d
+RG_GEMINIA_SX_TTL_INIT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12317;"	d
+RG_GEMINIA_SX_TTL_INIT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12316;"	d
+RG_GEMINIA_SX_TTL_INIT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12318;"	d
+RG_GEMINIA_SX_TTL_INIT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12320;"	d
+RG_GEMINIA_SX_TTL_SUB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12339;"	d
+RG_GEMINIA_SX_TTL_SUB_INV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12344;"	d
+RG_GEMINIA_SX_TTL_SUB_INV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12342;"	d
+RG_GEMINIA_SX_TTL_SUB_INV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12341;"	d
+RG_GEMINIA_SX_TTL_SUB_INV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12343;"	d
+RG_GEMINIA_SX_TTL_SUB_INV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12345;"	d
+RG_GEMINIA_SX_TTL_SUB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12337;"	d
+RG_GEMINIA_SX_TTL_SUB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12336;"	d
+RG_GEMINIA_SX_TTL_SUB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12338;"	d
+RG_GEMINIA_SX_TTL_SUB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12340;"	d
+RG_GEMINIA_SX_TTL_VH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12349;"	d
+RG_GEMINIA_SX_TTL_VH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12347;"	d
+RG_GEMINIA_SX_TTL_VH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12346;"	d
+RG_GEMINIA_SX_TTL_VH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12348;"	d
+RG_GEMINIA_SX_TTL_VH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12350;"	d
+RG_GEMINIA_SX_TTL_VL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12354;"	d
+RG_GEMINIA_SX_TTL_VL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12352;"	d
+RG_GEMINIA_SX_TTL_VL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12351;"	d
+RG_GEMINIA_SX_TTL_VL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12353;"	d
+RG_GEMINIA_SX_TTL_VL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12355;"	d
+RG_GEMINIA_SX_UOP_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11669;"	d
+RG_GEMINIA_SX_UOP_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11667;"	d
+RG_GEMINIA_SX_UOP_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11666;"	d
+RG_GEMINIA_SX_UOP_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11668;"	d
+RG_GEMINIA_SX_UOP_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11670;"	d
+RG_GEMINIA_SX_UOP_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11664;"	d
+RG_GEMINIA_SX_UOP_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11662;"	d
+RG_GEMINIA_SX_UOP_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11661;"	d
+RG_GEMINIA_SX_UOP_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11663;"	d
+RG_GEMINIA_SX_UOP_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11665;"	d
+RG_GEMINIA_SX_VCO_CS_AWH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12094;"	d
+RG_GEMINIA_SX_VCO_CS_AWH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12092;"	d
+RG_GEMINIA_SX_VCO_CS_AWH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12091;"	d
+RG_GEMINIA_SX_VCO_CS_AWH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12093;"	d
+RG_GEMINIA_SX_VCO_CS_AWH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12095;"	d
+RG_GEMINIA_SX_VCO_ISEL_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12044;"	d
+RG_GEMINIA_SX_VCO_ISEL_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12042;"	d
+RG_GEMINIA_SX_VCO_ISEL_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12041;"	d
+RG_GEMINIA_SX_VCO_ISEL_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12043;"	d
+RG_GEMINIA_SX_VCO_ISEL_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12045;"	d
+RG_GEMINIA_SX_VCO_ISEL_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12039;"	d
+RG_GEMINIA_SX_VCO_ISEL_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12037;"	d
+RG_GEMINIA_SX_VCO_ISEL_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12036;"	d
+RG_GEMINIA_SX_VCO_ISEL_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12038;"	d
+RG_GEMINIA_SX_VCO_ISEL_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12040;"	d
+RG_GEMINIA_SX_VCO_ISEL_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12064;"	d
+RG_GEMINIA_SX_VCO_ISEL_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12062;"	d
+RG_GEMINIA_SX_VCO_ISEL_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12061;"	d
+RG_GEMINIA_SX_VCO_ISEL_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12063;"	d
+RG_GEMINIA_SX_VCO_ISEL_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12065;"	d
+RG_GEMINIA_SX_VCO_KVDOUB_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12059;"	d
+RG_GEMINIA_SX_VCO_KVDOUB_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12057;"	d
+RG_GEMINIA_SX_VCO_KVDOUB_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12056;"	d
+RG_GEMINIA_SX_VCO_KVDOUB_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12058;"	d
+RG_GEMINIA_SX_VCO_KVDOUB_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12060;"	d
+RG_GEMINIA_SX_VCO_KVDOUB_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12079;"	d
+RG_GEMINIA_SX_VCO_KVDOUB_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12077;"	d
+RG_GEMINIA_SX_VCO_KVDOUB_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12076;"	d
+RG_GEMINIA_SX_VCO_KVDOUB_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12078;"	d
+RG_GEMINIA_SX_VCO_KVDOUB_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12080;"	d
+RG_GEMINIA_SX_VCO_LPM_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12049;"	d
+RG_GEMINIA_SX_VCO_LPM_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12047;"	d
+RG_GEMINIA_SX_VCO_LPM_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12046;"	d
+RG_GEMINIA_SX_VCO_LPM_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12048;"	d
+RG_GEMINIA_SX_VCO_LPM_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12050;"	d
+RG_GEMINIA_SX_VCO_LPM_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12069;"	d
+RG_GEMINIA_SX_VCO_LPM_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12067;"	d
+RG_GEMINIA_SX_VCO_LPM_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12066;"	d
+RG_GEMINIA_SX_VCO_LPM_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12068;"	d
+RG_GEMINIA_SX_VCO_LPM_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12070;"	d
+RG_GEMINIA_SX_VCO_RTAIL_SHIFT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12089;"	d
+RG_GEMINIA_SX_VCO_RTAIL_SHIFT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12087;"	d
+RG_GEMINIA_SX_VCO_RTAIL_SHIFT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12086;"	d
+RG_GEMINIA_SX_VCO_RTAIL_SHIFT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12088;"	d
+RG_GEMINIA_SX_VCO_RTAIL_SHIFT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12090;"	d
+RG_GEMINIA_SX_VCO_RXOB_AW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12149;"	d
+RG_GEMINIA_SX_VCO_RXOB_AW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12147;"	d
+RG_GEMINIA_SX_VCO_RXOB_AW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12146;"	d
+RG_GEMINIA_SX_VCO_RXOB_AW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12148;"	d
+RG_GEMINIA_SX_VCO_RXOB_AW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12150;"	d
+RG_GEMINIA_SX_VCO_TXOB_AW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12144;"	d
+RG_GEMINIA_SX_VCO_TXOB_AW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12142;"	d
+RG_GEMINIA_SX_VCO_TXOB_AW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12141;"	d
+RG_GEMINIA_SX_VCO_TXOB_AW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12143;"	d
+RG_GEMINIA_SX_VCO_TXOB_AW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12145;"	d
+RG_GEMINIA_SX_VCO_VARBSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12084;"	d
+RG_GEMINIA_SX_VCO_VARBSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12082;"	d
+RG_GEMINIA_SX_VCO_VARBSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12081;"	d
+RG_GEMINIA_SX_VCO_VARBSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12083;"	d
+RG_GEMINIA_SX_VCO_VARBSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12085;"	d
+RG_GEMINIA_SX_VCO_VCCBSEL_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12054;"	d
+RG_GEMINIA_SX_VCO_VCCBSEL_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12052;"	d
+RG_GEMINIA_SX_VCO_VCCBSEL_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12051;"	d
+RG_GEMINIA_SX_VCO_VCCBSEL_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12053;"	d
+RG_GEMINIA_SX_VCO_VCCBSEL_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12055;"	d
+RG_GEMINIA_SX_VCO_VCCBSEL_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12074;"	d
+RG_GEMINIA_SX_VCO_VCCBSEL_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12072;"	d
+RG_GEMINIA_SX_VCO_VCCBSEL_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12071;"	d
+RG_GEMINIA_SX_VCO_VCCBSEL_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12073;"	d
+RG_GEMINIA_SX_VCO_VCCBSEL_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12075;"	d
+RG_GEMINIA_SX_XTAL_FREQ_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11889;"	d
+RG_GEMINIA_SX_XTAL_FREQ_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11887;"	d
+RG_GEMINIA_SX_XTAL_FREQ_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11886;"	d
+RG_GEMINIA_SX_XTAL_FREQ_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11888;"	d
+RG_GEMINIA_SX_XTAL_FREQ_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11890;"	d
+RG_GEMINIA_TONE_SCALE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13554;"	d
+RG_GEMINIA_TONE_SCALE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13552;"	d
+RG_GEMINIA_TONE_SCALE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13551;"	d
+RG_GEMINIA_TONE_SCALE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13553;"	d
+RG_GEMINIA_TONE_SCALE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13555;"	d
+RG_GEMINIA_TXBTPA_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13279;"	d
+RG_GEMINIA_TXBTPA_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13277;"	d
+RG_GEMINIA_TXBTPA_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13276;"	d
+RG_GEMINIA_TXBTPA_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13278;"	d
+RG_GEMINIA_TXBTPA_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13280;"	d
+RG_GEMINIA_TXDAC_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13259;"	d
+RG_GEMINIA_TXDAC_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13257;"	d
+RG_GEMINIA_TXDAC_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13256;"	d
+RG_GEMINIA_TXDAC_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13258;"	d
+RG_GEMINIA_TXDAC_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13260;"	d
+RG_GEMINIA_TXDAC_R2T_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13304;"	d
+RG_GEMINIA_TXDAC_R2T_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13302;"	d
+RG_GEMINIA_TXDAC_R2T_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13301;"	d
+RG_GEMINIA_TXDAC_R2T_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13303;"	d
+RG_GEMINIA_TXDAC_R2T_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13305;"	d
+RG_GEMINIA_TXDAC_T2R_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13284;"	d
+RG_GEMINIA_TXDAC_T2R_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13282;"	d
+RG_GEMINIA_TXDAC_T2R_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13281;"	d
+RG_GEMINIA_TXDAC_T2R_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13283;"	d
+RG_GEMINIA_TXDAC_T2R_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13285;"	d
+RG_GEMINIA_TXGAIN_PHYCTRL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10244;"	d
+RG_GEMINIA_TXGAIN_PHYCTRL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10242;"	d
+RG_GEMINIA_TXGAIN_PHYCTRL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10241;"	d
+RG_GEMINIA_TXGAIN_PHYCTRL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10243;"	d
+RG_GEMINIA_TXGAIN_PHYCTRL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10245;"	d
+RG_GEMINIA_TXIQ_NOSHRK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13544;"	d
+RG_GEMINIA_TXIQ_NOSHRK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13542;"	d
+RG_GEMINIA_TXIQ_NOSHRK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13541;"	d
+RG_GEMINIA_TXIQ_NOSHRK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13543;"	d
+RG_GEMINIA_TXIQ_NOSHRK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13545;"	d
+RG_GEMINIA_TXLPF_BYPASS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10524;"	d
+RG_GEMINIA_TXLPF_BYPASS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10522;"	d
+RG_GEMINIA_TXLPF_BYPASS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10521;"	d
+RG_GEMINIA_TXLPF_BYPASS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10523;"	d
+RG_GEMINIA_TXLPF_BYPASS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10525;"	d
+RG_GEMINIA_TXLPF_GMCELL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10934;"	d
+RG_GEMINIA_TXLPF_GMCELL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10932;"	d
+RG_GEMINIA_TXLPF_GMCELL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10931;"	d
+RG_GEMINIA_TXLPF_GMCELL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10933;"	d
+RG_GEMINIA_TXLPF_GMCELL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10935;"	d
+RG_GEMINIA_TXMOD_GMCELL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10929;"	d
+RG_GEMINIA_TXMOD_GMCELL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10927;"	d
+RG_GEMINIA_TXMOD_GMCELL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10926;"	d
+RG_GEMINIA_TXMOD_GMCELL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10928;"	d
+RG_GEMINIA_TXMOD_GMCELL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10930;"	d
+RG_GEMINIA_TXPA_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13269;"	d
+RG_GEMINIA_TXPA_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13267;"	d
+RG_GEMINIA_TXPA_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13266;"	d
+RG_GEMINIA_TXPA_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13268;"	d
+RG_GEMINIA_TXPA_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13270;"	d
+RG_GEMINIA_TXPA_R2T_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13314;"	d
+RG_GEMINIA_TXPA_R2T_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13312;"	d
+RG_GEMINIA_TXPA_R2T_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13311;"	d
+RG_GEMINIA_TXPA_R2T_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13313;"	d
+RG_GEMINIA_TXPA_R2T_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13315;"	d
+RG_GEMINIA_TXPA_T2R_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13294;"	d
+RG_GEMINIA_TXPA_T2R_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13292;"	d
+RG_GEMINIA_TXPA_T2R_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13291;"	d
+RG_GEMINIA_TXPA_T2R_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13293;"	d
+RG_GEMINIA_TXPA_T2R_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13295;"	d
+RG_GEMINIA_TXPGA_MAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10919;"	d
+RG_GEMINIA_TXPGA_MAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10917;"	d
+RG_GEMINIA_TXPGA_MAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10916;"	d
+RG_GEMINIA_TXPGA_MAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10918;"	d
+RG_GEMINIA_TXPGA_MAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10920;"	d
+RG_GEMINIA_TXPGA_STEER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10924;"	d
+RG_GEMINIA_TXPGA_STEER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10922;"	d
+RG_GEMINIA_TXPGA_STEER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10921;"	d
+RG_GEMINIA_TXPGA_STEER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10923;"	d
+RG_GEMINIA_TXPGA_STEER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10925;"	d
+RG_GEMINIA_TXRF_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13264;"	d
+RG_GEMINIA_TXRF_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13262;"	d
+RG_GEMINIA_TXRF_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13261;"	d
+RG_GEMINIA_TXRF_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13263;"	d
+RG_GEMINIA_TXRF_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13265;"	d
+RG_GEMINIA_TXRF_R2T_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13309;"	d
+RG_GEMINIA_TXRF_R2T_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13307;"	d
+RG_GEMINIA_TXRF_R2T_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13306;"	d
+RG_GEMINIA_TXRF_R2T_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13308;"	d
+RG_GEMINIA_TXRF_R2T_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13310;"	d
+RG_GEMINIA_TXRF_T2R_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13289;"	d
+RG_GEMINIA_TXRF_T2R_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13287;"	d
+RG_GEMINIA_TXRF_T2R_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13286;"	d
+RG_GEMINIA_TXRF_T2R_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13288;"	d
+RG_GEMINIA_TXRF_T2R_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13290;"	d
+RG_GEMINIA_TX_BT_PA_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10419;"	d
+RG_GEMINIA_TX_BT_PA_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10417;"	d
+RG_GEMINIA_TX_BT_PA_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10416;"	d
+RG_GEMINIA_TX_BT_PA_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10418;"	d
+RG_GEMINIA_TX_BT_PA_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10420;"	d
+RG_GEMINIA_TX_DAC_CAL_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10454;"	d
+RG_GEMINIA_TX_DAC_CAL_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10452;"	d
+RG_GEMINIA_TX_DAC_CAL_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10451;"	d
+RG_GEMINIA_TX_DAC_CAL_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10453;"	d
+RG_GEMINIA_TX_DAC_CAL_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10455;"	d
+RG_GEMINIA_TX_DAC_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10389;"	d
+RG_GEMINIA_TX_DAC_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10387;"	d
+RG_GEMINIA_TX_DAC_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10386;"	d
+RG_GEMINIA_TX_DAC_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10388;"	d
+RG_GEMINIA_TX_DAC_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10390;"	d
+RG_GEMINIA_TX_DAC_TSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11549;"	d
+RG_GEMINIA_TX_DAC_TSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11547;"	d
+RG_GEMINIA_TX_DAC_TSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11546;"	d
+RG_GEMINIA_TX_DAC_TSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11548;"	d
+RG_GEMINIA_TX_DAC_TSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11550;"	d
+RG_GEMINIA_TX_DIV2_BUF_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10409;"	d
+RG_GEMINIA_TX_DIV2_BUF_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10407;"	d
+RG_GEMINIA_TX_DIV2_BUF_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10406;"	d
+RG_GEMINIA_TX_DIV2_BUF_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10408;"	d
+RG_GEMINIA_TX_DIV2_BUF_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10410;"	d
+RG_GEMINIA_TX_DIV2_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10399;"	d
+RG_GEMINIA_TX_DIV2_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10397;"	d
+RG_GEMINIA_TX_DIV2_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10396;"	d
+RG_GEMINIA_TX_DIV2_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10398;"	d
+RG_GEMINIA_TX_DIV2_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10400;"	d
+RG_GEMINIA_TX_DPDGM_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10789;"	d
+RG_GEMINIA_TX_DPDGM_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10787;"	d
+RG_GEMINIA_TX_DPDGM_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10786;"	d
+RG_GEMINIA_TX_DPDGM_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10788;"	d
+RG_GEMINIA_TX_DPDGM_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10790;"	d
+RG_GEMINIA_TX_DPD_DIV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10794;"	d
+RG_GEMINIA_TX_DPD_DIV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10792;"	d
+RG_GEMINIA_TX_DPD_DIV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10791;"	d
+RG_GEMINIA_TX_DPD_DIV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10793;"	d
+RG_GEMINIA_TX_DPD_DIV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10795;"	d
+RG_GEMINIA_TX_DPD_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10494;"	d
+RG_GEMINIA_TX_DPD_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10492;"	d
+RG_GEMINIA_TX_DPD_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10491;"	d
+RG_GEMINIA_TX_DPD_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10493;"	d
+RG_GEMINIA_TX_DPD_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10495;"	d
+RG_GEMINIA_TX_EN_VOLTAGE_IN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10529;"	d
+RG_GEMINIA_TX_EN_VOLTAGE_IN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10527;"	d
+RG_GEMINIA_TX_EN_VOLTAGE_IN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10526;"	d
+RG_GEMINIA_TX_EN_VOLTAGE_IN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10528;"	d
+RG_GEMINIA_TX_EN_VOLTAGE_IN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10530;"	d
+RG_GEMINIA_TX_FREQ_OFFSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13549;"	d
+RG_GEMINIA_TX_FREQ_OFFSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13547;"	d
+RG_GEMINIA_TX_FREQ_OFFSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13546;"	d
+RG_GEMINIA_TX_FREQ_OFFSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13548;"	d
+RG_GEMINIA_TX_FREQ_OFFSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13550;"	d
+RG_GEMINIA_TX_GAIN_DPDCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13394;"	d
+RG_GEMINIA_TX_GAIN_DPDCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13392;"	d
+RG_GEMINIA_TX_GAIN_DPDCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13391;"	d
+RG_GEMINIA_TX_GAIN_DPDCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13393;"	d
+RG_GEMINIA_TX_GAIN_DPDCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13395;"	d
+RG_GEMINIA_TX_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10274;"	d
+RG_GEMINIA_TX_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10272;"	d
+RG_GEMINIA_TX_GAIN_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10239;"	d
+RG_GEMINIA_TX_GAIN_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10237;"	d
+RG_GEMINIA_TX_GAIN_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10236;"	d
+RG_GEMINIA_TX_GAIN_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10238;"	d
+RG_GEMINIA_TX_GAIN_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10240;"	d
+RG_GEMINIA_TX_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10271;"	d
+RG_GEMINIA_TX_GAIN_RXIQCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13379;"	d
+RG_GEMINIA_TX_GAIN_RXIQCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13377;"	d
+RG_GEMINIA_TX_GAIN_RXIQCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13376;"	d
+RG_GEMINIA_TX_GAIN_RXIQCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13378;"	d
+RG_GEMINIA_TX_GAIN_RXIQCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13380;"	d
+RG_GEMINIA_TX_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10273;"	d
+RG_GEMINIA_TX_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10275;"	d
+RG_GEMINIA_TX_GAIN_TXCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13364;"	d
+RG_GEMINIA_TX_GAIN_TXCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13362;"	d
+RG_GEMINIA_TX_GAIN_TXCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13361;"	d
+RG_GEMINIA_TX_GAIN_TXCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13363;"	d
+RG_GEMINIA_TX_GAIN_TXCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13365;"	d
+RG_GEMINIA_TX_IQCAL_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13344;"	d
+RG_GEMINIA_TX_IQCAL_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13342;"	d
+RG_GEMINIA_TX_IQCAL_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13341;"	d
+RG_GEMINIA_TX_IQCAL_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13343;"	d
+RG_GEMINIA_TX_IQCAL_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13345;"	d
+RG_GEMINIA_TX_IQ_ALPHA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13529;"	d
+RG_GEMINIA_TX_IQ_ALPHA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13527;"	d
+RG_GEMINIA_TX_IQ_ALPHA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13526;"	d
+RG_GEMINIA_TX_IQ_ALPHA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13528;"	d
+RG_GEMINIA_TX_IQ_ALPHA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13530;"	d
+RG_GEMINIA_TX_IQ_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13539;"	d
+RG_GEMINIA_TX_IQ_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13537;"	d
+RG_GEMINIA_TX_IQ_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13536;"	d
+RG_GEMINIA_TX_IQ_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13538;"	d
+RG_GEMINIA_TX_IQ_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13540;"	d
+RG_GEMINIA_TX_IQ_THETA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13534;"	d
+RG_GEMINIA_TX_IQ_THETA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13532;"	d
+RG_GEMINIA_TX_IQ_THETA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13531;"	d
+RG_GEMINIA_TX_IQ_THETA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13533;"	d
+RG_GEMINIA_TX_IQ_THETA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13535;"	d
+RG_GEMINIA_TX_LOCAL_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13339;"	d
+RG_GEMINIA_TX_LOCAL_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13337;"	d
+RG_GEMINIA_TX_LOCAL_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13336;"	d
+RG_GEMINIA_TX_LOCAL_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13338;"	d
+RG_GEMINIA_TX_LOCAL_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13340;"	d
+RG_GEMINIA_TX_MOD_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10379;"	d
+RG_GEMINIA_TX_MOD_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10377;"	d
+RG_GEMINIA_TX_MOD_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10376;"	d
+RG_GEMINIA_TX_MOD_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10378;"	d
+RG_GEMINIA_TX_MOD_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10380;"	d
+RG_GEMINIA_TX_PA_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10369;"	d
+RG_GEMINIA_TX_PA_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10367;"	d
+RG_GEMINIA_TX_PA_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10366;"	d
+RG_GEMINIA_TX_PA_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10368;"	d
+RG_GEMINIA_TX_PA_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10370;"	d
+RG_GEMINIA_TX_SELF_MIXER_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10474;"	d
+RG_GEMINIA_TX_SELF_MIXER_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10472;"	d
+RG_GEMINIA_TX_SELF_MIXER_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10471;"	d
+RG_GEMINIA_TX_SELF_MIXER_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10473;"	d
+RG_GEMINIA_TX_SELF_MIXER_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10475;"	d
+RG_GEMINIA_TX_TRSW_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10279;"	d
+RG_GEMINIA_TX_TRSW_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10277;"	d
+RG_GEMINIA_TX_TRSW_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10276;"	d
+RG_GEMINIA_TX_TRSW_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10278;"	d
+RG_GEMINIA_TX_TRSW_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10280;"	d
+RG_GEMINIA_TX_TSSI_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10799;"	d
+RG_GEMINIA_TX_TSSI_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10797;"	d
+RG_GEMINIA_TX_TSSI_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10796;"	d
+RG_GEMINIA_TX_TSSI_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10798;"	d
+RG_GEMINIA_TX_TSSI_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10800;"	d
+RG_GEMINIA_TX_TSSI_DIV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10804;"	d
+RG_GEMINIA_TX_TSSI_DIV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10802;"	d
+RG_GEMINIA_TX_TSSI_DIV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10801;"	d
+RG_GEMINIA_TX_TSSI_DIV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10803;"	d
+RG_GEMINIA_TX_TSSI_DIV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10805;"	d
+RG_GEMINIA_TX_TSSI_TESTMODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10814;"	d
+RG_GEMINIA_TX_TSSI_TESTMODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10812;"	d
+RG_GEMINIA_TX_TSSI_TESTMODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10811;"	d
+RG_GEMINIA_TX_TSSI_TESTMODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10813;"	d
+RG_GEMINIA_TX_TSSI_TESTMODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10815;"	d
+RG_GEMINIA_TX_TSSI_TEST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10809;"	d
+RG_GEMINIA_TX_TSSI_TEST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10807;"	d
+RG_GEMINIA_TX_TSSI_TEST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10806;"	d
+RG_GEMINIA_TX_TSSI_TEST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10808;"	d
+RG_GEMINIA_TX_TSSI_TEST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10810;"	d
+RG_GEMINIA_TX_UP8X_MAN_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13559;"	d
+RG_GEMINIA_TX_UP8X_MAN_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13557;"	d
+RG_GEMINIA_TX_UP8X_MAN_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13556;"	d
+RG_GEMINIA_TX_UP8X_MAN_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13558;"	d
+RG_GEMINIA_TX_UP8X_MAN_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13560;"	d
+RG_GEMINIA_TX_VTOI_CURRENT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10949;"	d
+RG_GEMINIA_TX_VTOI_CURRENT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10947;"	d
+RG_GEMINIA_TX_VTOI_CURRENT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10946;"	d
+RG_GEMINIA_TX_VTOI_CURRENT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10948;"	d
+RG_GEMINIA_TX_VTOI_CURRENT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10950;"	d
+RG_GEMINIA_TX_VTOI_FS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10964;"	d
+RG_GEMINIA_TX_VTOI_FS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10962;"	d
+RG_GEMINIA_TX_VTOI_FS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10961;"	d
+RG_GEMINIA_TX_VTOI_FS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10963;"	d
+RG_GEMINIA_TX_VTOI_FS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10965;"	d
+RG_GEMINIA_TX_VTOI_GM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10954;"	d
+RG_GEMINIA_TX_VTOI_GM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10952;"	d
+RG_GEMINIA_TX_VTOI_GM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10951;"	d
+RG_GEMINIA_TX_VTOI_GM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10953;"	d
+RG_GEMINIA_TX_VTOI_GM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10955;"	d
+RG_GEMINIA_TX_VTOI_OPTION_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10959;"	d
+RG_GEMINIA_TX_VTOI_OPTION_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10957;"	d
+RG_GEMINIA_TX_VTOI_OPTION_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10956;"	d
+RG_GEMINIA_TX_VTOI_OPTION_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10958;"	d
+RG_GEMINIA_TX_VTOI_OPTION_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10960;"	d
+RG_GEMINIA_VOBF_CAPIMB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12159;"	d
+RG_GEMINIA_VOBF_CAPIMB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12157;"	d
+RG_GEMINIA_VOBF_CAPIMB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12156;"	d
+RG_GEMINIA_VOBF_CAPIMB_POL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12154;"	d
+RG_GEMINIA_VOBF_CAPIMB_POL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12152;"	d
+RG_GEMINIA_VOBF_CAPIMB_POL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12151;"	d
+RG_GEMINIA_VOBF_CAPIMB_POL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12153;"	d
+RG_GEMINIA_VOBF_CAPIMB_POL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12155;"	d
+RG_GEMINIA_VOBF_CAPIMB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12158;"	d
+RG_GEMINIA_VOBF_CAPIMB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12160;"	d
+RG_GEMINIA_VOBF_DIVBFSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12139;"	d
+RG_GEMINIA_VOBF_DIVBFSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12137;"	d
+RG_GEMINIA_VOBF_DIVBFSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12136;"	d
+RG_GEMINIA_VOBF_DIVBFSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12138;"	d
+RG_GEMINIA_VOBF_DIVBFSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12140;"	d
+RG_GEMINIA_VOBF_RXMBSEL_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12109;"	d
+RG_GEMINIA_VOBF_RXMBSEL_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12107;"	d
+RG_GEMINIA_VOBF_RXMBSEL_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12106;"	d
+RG_GEMINIA_VOBF_RXMBSEL_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12108;"	d
+RG_GEMINIA_VOBF_RXMBSEL_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12110;"	d
+RG_GEMINIA_VOBF_RXMBSEL_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12129;"	d
+RG_GEMINIA_VOBF_RXMBSEL_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12127;"	d
+RG_GEMINIA_VOBF_RXMBSEL_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12126;"	d
+RG_GEMINIA_VOBF_RXMBSEL_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12128;"	d
+RG_GEMINIA_VOBF_RXMBSEL_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12130;"	d
+RG_GEMINIA_VOBF_RXOBSEL_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12114;"	d
+RG_GEMINIA_VOBF_RXOBSEL_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12112;"	d
+RG_GEMINIA_VOBF_RXOBSEL_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12111;"	d
+RG_GEMINIA_VOBF_RXOBSEL_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12113;"	d
+RG_GEMINIA_VOBF_RXOBSEL_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12115;"	d
+RG_GEMINIA_VOBF_RXOBSEL_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12134;"	d
+RG_GEMINIA_VOBF_RXOBSEL_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12132;"	d
+RG_GEMINIA_VOBF_RXOBSEL_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12131;"	d
+RG_GEMINIA_VOBF_RXOBSEL_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12133;"	d
+RG_GEMINIA_VOBF_RXOBSEL_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12135;"	d
+RG_GEMINIA_VOBF_TXMBSEL_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12099;"	d
+RG_GEMINIA_VOBF_TXMBSEL_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12097;"	d
+RG_GEMINIA_VOBF_TXMBSEL_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12096;"	d
+RG_GEMINIA_VOBF_TXMBSEL_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12098;"	d
+RG_GEMINIA_VOBF_TXMBSEL_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12100;"	d
+RG_GEMINIA_VOBF_TXMBSEL_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12119;"	d
+RG_GEMINIA_VOBF_TXMBSEL_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12117;"	d
+RG_GEMINIA_VOBF_TXMBSEL_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12116;"	d
+RG_GEMINIA_VOBF_TXMBSEL_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12118;"	d
+RG_GEMINIA_VOBF_TXMBSEL_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12120;"	d
+RG_GEMINIA_VOBF_TXOBSEL_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12104;"	d
+RG_GEMINIA_VOBF_TXOBSEL_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12102;"	d
+RG_GEMINIA_VOBF_TXOBSEL_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12101;"	d
+RG_GEMINIA_VOBF_TXOBSEL_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12103;"	d
+RG_GEMINIA_VOBF_TXOBSEL_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12105;"	d
+RG_GEMINIA_VOBF_TXOBSEL_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12124;"	d
+RG_GEMINIA_VOBF_TXOBSEL_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12122;"	d
+RG_GEMINIA_VOBF_TXOBSEL_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12121;"	d
+RG_GEMINIA_VOBF_TXOBSEL_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12123;"	d
+RG_GEMINIA_VOBF_TXOBSEL_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12125;"	d
+RG_GEMINIA_VO_AAC_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12294;"	d
+RG_GEMINIA_VO_AAC_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12292;"	d
+RG_GEMINIA_VO_AAC_EN_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12289;"	d
+RG_GEMINIA_VO_AAC_EN_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12287;"	d
+RG_GEMINIA_VO_AAC_EN_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12286;"	d
+RG_GEMINIA_VO_AAC_EN_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12288;"	d
+RG_GEMINIA_VO_AAC_EN_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12290;"	d
+RG_GEMINIA_VO_AAC_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12291;"	d
+RG_GEMINIA_VO_AAC_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12293;"	d
+RG_GEMINIA_VO_AAC_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12295;"	d
+RG_GEMINIA_VO_AAC_EVA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12304;"	d
+RG_GEMINIA_VO_AAC_EVA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12302;"	d
+RG_GEMINIA_VO_AAC_EVA_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12299;"	d
+RG_GEMINIA_VO_AAC_EVA_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12297;"	d
+RG_GEMINIA_VO_AAC_EVA_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12296;"	d
+RG_GEMINIA_VO_AAC_EVA_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12298;"	d
+RG_GEMINIA_VO_AAC_EVA_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12300;"	d
+RG_GEMINIA_VO_AAC_EVA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12301;"	d
+RG_GEMINIA_VO_AAC_EVA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12303;"	d
+RG_GEMINIA_VO_AAC_EVA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12305;"	d
+RG_GEMINIA_VO_AAC_EVA_TS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12284;"	d
+RG_GEMINIA_VO_AAC_EVA_TS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12282;"	d
+RG_GEMINIA_VO_AAC_EVA_TS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12281;"	d
+RG_GEMINIA_VO_AAC_EVA_TS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12283;"	d
+RG_GEMINIA_VO_AAC_EVA_TS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12285;"	d
+RG_GEMINIA_VO_AAC_IMAX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12274;"	d
+RG_GEMINIA_VO_AAC_IMAX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12272;"	d
+RG_GEMINIA_VO_AAC_IMAX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12271;"	d
+RG_GEMINIA_VO_AAC_IMAX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12273;"	d
+RG_GEMINIA_VO_AAC_IMAX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12275;"	d
+RG_GEMINIA_VO_AAC_INIT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12279;"	d
+RG_GEMINIA_VO_AAC_INIT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12277;"	d
+RG_GEMINIA_VO_AAC_INIT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12276;"	d
+RG_GEMINIA_VO_AAC_INIT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12278;"	d
+RG_GEMINIA_VO_AAC_INIT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12280;"	d
+RG_GEMINIA_VO_AAC_IOST_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12259;"	d
+RG_GEMINIA_VO_AAC_IOST_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12257;"	d
+RG_GEMINIA_VO_AAC_IOST_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12256;"	d
+RG_GEMINIA_VO_AAC_IOST_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12258;"	d
+RG_GEMINIA_VO_AAC_IOST_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12260;"	d
+RG_GEMINIA_VO_AAC_IOST_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12269;"	d
+RG_GEMINIA_VO_AAC_IOST_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12267;"	d
+RG_GEMINIA_VO_AAC_IOST_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12266;"	d
+RG_GEMINIA_VO_AAC_IOST_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12268;"	d
+RG_GEMINIA_VO_AAC_IOST_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12270;"	d
+RG_GEMINIA_VO_AAC_TAR_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12254;"	d
+RG_GEMINIA_VO_AAC_TAR_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12252;"	d
+RG_GEMINIA_VO_AAC_TAR_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12251;"	d
+RG_GEMINIA_VO_AAC_TAR_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12253;"	d
+RG_GEMINIA_VO_AAC_TAR_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12255;"	d
+RG_GEMINIA_VO_AAC_TAR_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12264;"	d
+RG_GEMINIA_VO_AAC_TAR_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12262;"	d
+RG_GEMINIA_VO_AAC_TAR_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12261;"	d
+RG_GEMINIA_VO_AAC_TAR_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12263;"	d
+RG_GEMINIA_VO_AAC_TAR_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12265;"	d
+RG_GEMINIA_VO_AAC_TEST_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12309;"	d
+RG_GEMINIA_VO_AAC_TEST_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12307;"	d
+RG_GEMINIA_VO_AAC_TEST_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12306;"	d
+RG_GEMINIA_VO_AAC_TEST_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12308;"	d
+RG_GEMINIA_VO_AAC_TEST_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12310;"	d
+RG_GEMINIA_VO_AAC_TEST_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12314;"	d
+RG_GEMINIA_VO_AAC_TEST_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12312;"	d
+RG_GEMINIA_VO_AAC_TEST_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12311;"	d
+RG_GEMINIA_VO_AAC_TEST_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12313;"	d
+RG_GEMINIA_VO_AAC_TEST_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12315;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12664;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12662;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12661;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12663;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12665;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG10_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12564;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG10_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12562;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG10_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12561;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG10_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12563;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG10_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12565;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG11_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12554;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG11_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12552;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG11_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12551;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG11_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12553;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG11_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12555;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG12_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12544;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG12_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12542;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG12_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12541;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG12_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12543;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG12_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12545;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG13_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12534;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG13_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12532;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG13_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12531;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG13_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12533;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG13_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12535;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG14_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12524;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG14_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12522;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG14_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12521;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG14_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12523;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG14_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12525;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG15_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12514;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG15_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12512;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG15_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12511;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG15_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12513;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG15_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12515;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12654;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12652;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12651;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12653;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12655;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12644;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12642;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12641;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12643;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12645;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12634;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12632;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12631;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12633;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12635;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12624;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12622;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12621;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12623;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12625;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12614;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12612;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12611;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12613;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12615;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12604;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12602;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12601;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12603;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12605;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12594;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12592;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12591;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12593;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12595;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG8_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12584;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG8_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12582;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG8_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12581;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG8_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12583;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG8_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12585;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG9_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12574;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG9_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12572;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG9_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12571;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG9_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12573;"	d
+RG_GEMINIA_WF_IDACAI_TZ0_PGAG9_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12575;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12824;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12822;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12821;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12823;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12825;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG10_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12724;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG10_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12722;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG10_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12721;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG10_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12723;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG10_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12725;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG11_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12714;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG11_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12712;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG11_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12711;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG11_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12713;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG11_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12715;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG12_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12704;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG12_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12702;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG12_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12701;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG12_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12703;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG12_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12705;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG13_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12694;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG13_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12692;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG13_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12691;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG13_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12693;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG13_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12695;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG14_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12684;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG14_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12682;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG14_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12681;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG14_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12683;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG14_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12685;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG15_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12674;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG15_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12672;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG15_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12671;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG15_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12673;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG15_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12675;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12814;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12812;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12811;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12813;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12815;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12804;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12802;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12801;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12803;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12805;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12794;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12792;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12791;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12793;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12795;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12784;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12782;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12781;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12783;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12785;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12774;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12772;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12771;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12773;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12775;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12764;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12762;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12761;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12763;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12765;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12754;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12752;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12751;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12753;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12755;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG8_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12744;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG8_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12742;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG8_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12741;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG8_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12743;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG8_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12745;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG9_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12734;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG9_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12732;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG9_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12731;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG9_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12733;"	d
+RG_GEMINIA_WF_IDACAI_TZ1_PGAG9_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12735;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12669;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12667;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12666;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12668;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12670;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG10_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12569;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG10_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12567;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG10_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12566;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG10_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12568;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG10_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12570;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG11_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12559;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG11_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12557;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG11_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12556;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG11_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12558;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG11_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12560;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG12_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12549;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG12_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12547;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG12_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12546;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG12_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12548;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG12_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12550;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG13_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12539;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG13_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12537;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG13_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12536;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG13_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12538;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG13_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12540;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG14_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12529;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG14_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12527;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG14_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12526;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG14_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12528;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG14_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12530;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG15_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12519;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG15_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12517;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG15_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12516;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG15_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12518;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG15_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12520;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12659;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12657;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12656;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12658;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12660;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12649;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12647;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12646;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12648;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12650;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12639;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12637;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12636;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12638;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12640;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12629;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12627;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12626;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12628;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12630;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12619;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12617;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12616;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12618;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12620;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12609;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12607;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12606;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12608;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12610;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12599;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12597;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12596;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12598;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12600;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG8_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12589;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG8_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12587;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG8_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12586;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG8_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12588;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG8_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12590;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG9_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12579;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG9_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12577;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG9_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12576;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG9_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12578;"	d
+RG_GEMINIA_WF_IDACAQ_TZ0_PGAG9_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12580;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12829;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12827;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12826;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12828;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12830;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG10_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12729;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG10_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12727;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG10_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12726;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG10_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12728;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG10_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12730;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG11_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12719;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG11_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12717;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG11_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12716;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG11_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12718;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG11_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12720;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG12_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12709;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG12_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12707;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG12_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12706;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG12_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12708;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG12_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12710;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG13_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12699;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG13_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12697;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG13_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12696;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG13_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12698;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG13_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12700;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG14_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12689;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG14_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12687;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG14_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12686;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG14_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12688;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG14_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12690;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG15_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12679;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG15_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12677;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG15_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12676;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG15_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12678;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG15_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12680;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12819;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12817;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12816;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12818;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12820;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12809;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12807;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12806;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12808;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12810;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12799;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12797;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12796;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12798;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12800;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12789;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12787;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12786;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12788;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12790;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12779;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12777;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12776;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12778;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12780;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12769;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12767;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12766;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12768;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12770;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12759;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12757;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12756;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12758;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12760;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG8_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12749;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG8_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12747;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG8_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12746;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG8_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12748;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG8_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12750;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG9_HI	smac/hal/ssv6006c/ssv6006C_aux.h	12739;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG9_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12737;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG9_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	12736;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG9_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	12738;"	d
+RG_GEMINIA_WF_IDACAQ_TZ1_PGAG9_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	12740;"	d
+RG_GEMINIA_WF_PABIAS_CTRL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10879;"	d
+RG_GEMINIA_WF_PABIAS_CTRL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10877;"	d
+RG_GEMINIA_WF_PABIAS_CTRL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10876;"	d
+RG_GEMINIA_WF_PABIAS_CTRL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10878;"	d
+RG_GEMINIA_WF_PABIAS_CTRL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10880;"	d
+RG_GEMINIA_WF_PACELL_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10874;"	d
+RG_GEMINIA_WF_PACELL_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10872;"	d
+RG_GEMINIA_WF_PACELL_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10871;"	d
+RG_GEMINIA_WF_PACELL_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10873;"	d
+RG_GEMINIA_WF_PACELL_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10875;"	d
+RG_GEMINIA_WF_RX_ABBCFIX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10659;"	d
+RG_GEMINIA_WF_RX_ABBCFIX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10657;"	d
+RG_GEMINIA_WF_RX_ABBCFIX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10656;"	d
+RG_GEMINIA_WF_RX_ABBCFIX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10658;"	d
+RG_GEMINIA_WF_RX_ABBCFIX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10660;"	d
+RG_GEMINIA_WF_RX_ABBCTUNEI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10629;"	d
+RG_GEMINIA_WF_RX_ABBCTUNEI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10627;"	d
+RG_GEMINIA_WF_RX_ABBCTUNEI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10626;"	d
+RG_GEMINIA_WF_RX_ABBCTUNEI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10628;"	d
+RG_GEMINIA_WF_RX_ABBCTUNEI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10630;"	d
+RG_GEMINIA_WF_RX_ABBCTUNEQ_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10634;"	d
+RG_GEMINIA_WF_RX_ABBCTUNEQ_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10632;"	d
+RG_GEMINIA_WF_RX_ABBCTUNEQ_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10631;"	d
+RG_GEMINIA_WF_RX_ABBCTUNEQ_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10633;"	d
+RG_GEMINIA_WF_RX_ABBCTUNEQ_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10635;"	d
+RG_GEMINIA_WF_RX_ABB_BT_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10669;"	d
+RG_GEMINIA_WF_RX_ABB_BT_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10667;"	d
+RG_GEMINIA_WF_RX_ABB_BT_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10666;"	d
+RG_GEMINIA_WF_RX_ABB_BT_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10668;"	d
+RG_GEMINIA_WF_RX_ABB_BT_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10670;"	d
+RG_GEMINIA_WF_RX_ABB_IDIV3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10674;"	d
+RG_GEMINIA_WF_RX_ABB_IDIV3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10672;"	d
+RG_GEMINIA_WF_RX_ABB_IDIV3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10671;"	d
+RG_GEMINIA_WF_RX_ABB_IDIV3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10673;"	d
+RG_GEMINIA_WF_RX_ABB_IDIV3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10675;"	d
+RG_GEMINIA_WF_RX_ABB_N_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10664;"	d
+RG_GEMINIA_WF_RX_ABB_N_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10662;"	d
+RG_GEMINIA_WF_RX_ABB_N_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10661;"	d
+RG_GEMINIA_WF_RX_ABB_N_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10663;"	d
+RG_GEMINIA_WF_RX_ABB_N_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10665;"	d
+RG_GEMINIA_WF_RX_ADC_CLOAD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11444;"	d
+RG_GEMINIA_WF_RX_ADC_CLOAD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11442;"	d
+RG_GEMINIA_WF_RX_ADC_CLOAD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11441;"	d
+RG_GEMINIA_WF_RX_ADC_CLOAD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11443;"	d
+RG_GEMINIA_WF_RX_ADC_CLOAD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11445;"	d
+RG_GEMINIA_WF_RX_ADC_ICMP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11434;"	d
+RG_GEMINIA_WF_RX_ADC_ICMP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11432;"	d
+RG_GEMINIA_WF_RX_ADC_ICMP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11431;"	d
+RG_GEMINIA_WF_RX_ADC_ICMP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11433;"	d
+RG_GEMINIA_WF_RX_ADC_ICMP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11435;"	d
+RG_GEMINIA_WF_RX_ADC_VCMI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11439;"	d
+RG_GEMINIA_WF_RX_ADC_VCMI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11437;"	d
+RG_GEMINIA_WF_RX_ADC_VCMI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11436;"	d
+RG_GEMINIA_WF_RX_ADC_VCMI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11438;"	d
+RG_GEMINIA_WF_RX_ADC_VCMI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11440;"	d
+RG_GEMINIA_WF_RX_DCCAL_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13324;"	d
+RG_GEMINIA_WF_RX_DCCAL_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13322;"	d
+RG_GEMINIA_WF_RX_DCCAL_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13321;"	d
+RG_GEMINIA_WF_RX_DCCAL_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13323;"	d
+RG_GEMINIA_WF_RX_DCCAL_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13325;"	d
+RG_GEMINIA_WF_RX_EN_IDACA_COARSE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10679;"	d
+RG_GEMINIA_WF_RX_EN_IDACA_COARSE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10677;"	d
+RG_GEMINIA_WF_RX_EN_IDACA_COARSE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10676;"	d
+RG_GEMINIA_WF_RX_EN_IDACA_COARSE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10678;"	d
+RG_GEMINIA_WF_RX_EN_IDACA_COARSE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10680;"	d
+RG_GEMINIA_WF_RX_EN_LOOPA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10684;"	d
+RG_GEMINIA_WF_RX_EN_LOOPA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10682;"	d
+RG_GEMINIA_WF_RX_EN_LOOPA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10681;"	d
+RG_GEMINIA_WF_RX_EN_LOOPA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10683;"	d
+RG_GEMINIA_WF_RX_EN_LOOPA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10685;"	d
+RG_GEMINIA_WF_RX_FILTERI1ST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10644;"	d
+RG_GEMINIA_WF_RX_FILTERI1ST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10642;"	d
+RG_GEMINIA_WF_RX_FILTERI1ST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10641;"	d
+RG_GEMINIA_WF_RX_FILTERI1ST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10643;"	d
+RG_GEMINIA_WF_RX_FILTERI1ST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10645;"	d
+RG_GEMINIA_WF_RX_FILTERI2ND_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10649;"	d
+RG_GEMINIA_WF_RX_FILTERI2ND_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10647;"	d
+RG_GEMINIA_WF_RX_FILTERI2ND_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10646;"	d
+RG_GEMINIA_WF_RX_FILTERI2ND_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10648;"	d
+RG_GEMINIA_WF_RX_FILTERI2ND_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10650;"	d
+RG_GEMINIA_WF_RX_FILTERI3RD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10654;"	d
+RG_GEMINIA_WF_RX_FILTERI3RD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10652;"	d
+RG_GEMINIA_WF_RX_FILTERI3RD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10651;"	d
+RG_GEMINIA_WF_RX_FILTERI3RD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10653;"	d
+RG_GEMINIA_WF_RX_FILTERI3RD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10655;"	d
+RG_GEMINIA_WF_RX_FILTERI_COARSE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10639;"	d
+RG_GEMINIA_WF_RX_FILTERI_COARSE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10637;"	d
+RG_GEMINIA_WF_RX_FILTERI_COARSE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10636;"	d
+RG_GEMINIA_WF_RX_FILTERI_COARSE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10638;"	d
+RG_GEMINIA_WF_RX_FILTERI_COARSE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10640;"	d
+RG_GEMINIA_WF_RX_FILTERVCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10689;"	d
+RG_GEMINIA_WF_RX_FILTERVCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10687;"	d
+RG_GEMINIA_WF_RX_FILTERVCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10686;"	d
+RG_GEMINIA_WF_RX_FILTERVCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10688;"	d
+RG_GEMINIA_WF_RX_FILTERVCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10690;"	d
+RG_GEMINIA_WF_RX_HG_DIV2_CORE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11004;"	d
+RG_GEMINIA_WF_RX_HG_DIV2_CORE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11002;"	d
+RG_GEMINIA_WF_RX_HG_DIV2_CORE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11001;"	d
+RG_GEMINIA_WF_RX_HG_DIV2_CORE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11003;"	d
+RG_GEMINIA_WF_RX_HG_DIV2_CORE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11005;"	d
+RG_GEMINIA_WF_RX_HG_LNAHGN_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10979;"	d
+RG_GEMINIA_WF_RX_HG_LNAHGN_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10977;"	d
+RG_GEMINIA_WF_RX_HG_LNAHGN_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10976;"	d
+RG_GEMINIA_WF_RX_HG_LNAHGN_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10978;"	d
+RG_GEMINIA_WF_RX_HG_LNAHGN_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10980;"	d
+RG_GEMINIA_WF_RX_HG_LNAHGP_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10984;"	d
+RG_GEMINIA_WF_RX_HG_LNAHGP_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10982;"	d
+RG_GEMINIA_WF_RX_HG_LNAHGP_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10981;"	d
+RG_GEMINIA_WF_RX_HG_LNAHGP_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10983;"	d
+RG_GEMINIA_WF_RX_HG_LNAHGP_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10985;"	d
+RG_GEMINIA_WF_RX_HG_LNALG_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10989;"	d
+RG_GEMINIA_WF_RX_HG_LNALG_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10987;"	d
+RG_GEMINIA_WF_RX_HG_LNALG_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10986;"	d
+RG_GEMINIA_WF_RX_HG_LNALG_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10988;"	d
+RG_GEMINIA_WF_RX_HG_LNALG_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10990;"	d
+RG_GEMINIA_WF_RX_HG_LNA_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10969;"	d
+RG_GEMINIA_WF_RX_HG_LNA_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10967;"	d
+RG_GEMINIA_WF_RX_HG_LNA_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10966;"	d
+RG_GEMINIA_WF_RX_HG_LNA_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10968;"	d
+RG_GEMINIA_WF_RX_HG_LNA_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10970;"	d
+RG_GEMINIA_WF_RX_HG_LOBUF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11009;"	d
+RG_GEMINIA_WF_RX_HG_LOBUF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11007;"	d
+RG_GEMINIA_WF_RX_HG_LOBUF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11006;"	d
+RG_GEMINIA_WF_RX_HG_LOBUF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11008;"	d
+RG_GEMINIA_WF_RX_HG_LOBUF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11010;"	d
+RG_GEMINIA_WF_RX_HG_SQDC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10999;"	d
+RG_GEMINIA_WF_RX_HG_SQDC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10997;"	d
+RG_GEMINIA_WF_RX_HG_SQDC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10996;"	d
+RG_GEMINIA_WF_RX_HG_SQDC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10998;"	d
+RG_GEMINIA_WF_RX_HG_SQDC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11000;"	d
+RG_GEMINIA_WF_RX_HG_TZI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11014;"	d
+RG_GEMINIA_WF_RX_HG_TZI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11012;"	d
+RG_GEMINIA_WF_RX_HG_TZI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11011;"	d
+RG_GEMINIA_WF_RX_HG_TZI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11013;"	d
+RG_GEMINIA_WF_RX_HG_TZI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11015;"	d
+RG_GEMINIA_WF_RX_HG_TZ_CAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10994;"	d
+RG_GEMINIA_WF_RX_HG_TZ_CAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10992;"	d
+RG_GEMINIA_WF_RX_HG_TZ_CAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10991;"	d
+RG_GEMINIA_WF_RX_HG_TZ_CAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10993;"	d
+RG_GEMINIA_WF_RX_HG_TZ_CAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10995;"	d
+RG_GEMINIA_WF_RX_HG_TZ_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10974;"	d
+RG_GEMINIA_WF_RX_HG_TZ_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10972;"	d
+RG_GEMINIA_WF_RX_HG_TZ_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10971;"	d
+RG_GEMINIA_WF_RX_HG_TZ_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10973;"	d
+RG_GEMINIA_WF_RX_HG_TZ_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10975;"	d
+RG_GEMINIA_WF_RX_HG_TZ_VCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11019;"	d
+RG_GEMINIA_WF_RX_HG_TZ_VCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11017;"	d
+RG_GEMINIA_WF_RX_HG_TZ_VCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11016;"	d
+RG_GEMINIA_WF_RX_HG_TZ_VCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11018;"	d
+RG_GEMINIA_WF_RX_HG_TZ_VCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11020;"	d
+RG_GEMINIA_WF_RX_LG_DIV2_CORE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11114;"	d
+RG_GEMINIA_WF_RX_LG_DIV2_CORE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11112;"	d
+RG_GEMINIA_WF_RX_LG_DIV2_CORE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11111;"	d
+RG_GEMINIA_WF_RX_LG_DIV2_CORE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11113;"	d
+RG_GEMINIA_WF_RX_LG_DIV2_CORE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11115;"	d
+RG_GEMINIA_WF_RX_LG_LNAHGN_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11089;"	d
+RG_GEMINIA_WF_RX_LG_LNAHGN_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11087;"	d
+RG_GEMINIA_WF_RX_LG_LNAHGN_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11086;"	d
+RG_GEMINIA_WF_RX_LG_LNAHGN_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11088;"	d
+RG_GEMINIA_WF_RX_LG_LNAHGN_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11090;"	d
+RG_GEMINIA_WF_RX_LG_LNAHGP_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11094;"	d
+RG_GEMINIA_WF_RX_LG_LNAHGP_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11092;"	d
+RG_GEMINIA_WF_RX_LG_LNAHGP_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11091;"	d
+RG_GEMINIA_WF_RX_LG_LNAHGP_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11093;"	d
+RG_GEMINIA_WF_RX_LG_LNAHGP_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11095;"	d
+RG_GEMINIA_WF_RX_LG_LNALG_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11099;"	d
+RG_GEMINIA_WF_RX_LG_LNALG_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11097;"	d
+RG_GEMINIA_WF_RX_LG_LNALG_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11096;"	d
+RG_GEMINIA_WF_RX_LG_LNALG_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11098;"	d
+RG_GEMINIA_WF_RX_LG_LNALG_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11100;"	d
+RG_GEMINIA_WF_RX_LG_LNA_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11079;"	d
+RG_GEMINIA_WF_RX_LG_LNA_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11077;"	d
+RG_GEMINIA_WF_RX_LG_LNA_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11076;"	d
+RG_GEMINIA_WF_RX_LG_LNA_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11078;"	d
+RG_GEMINIA_WF_RX_LG_LNA_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11080;"	d
+RG_GEMINIA_WF_RX_LG_LOBUF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11119;"	d
+RG_GEMINIA_WF_RX_LG_LOBUF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11117;"	d
+RG_GEMINIA_WF_RX_LG_LOBUF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11116;"	d
+RG_GEMINIA_WF_RX_LG_LOBUF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11118;"	d
+RG_GEMINIA_WF_RX_LG_LOBUF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11120;"	d
+RG_GEMINIA_WF_RX_LG_SQDC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11109;"	d
+RG_GEMINIA_WF_RX_LG_SQDC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11107;"	d
+RG_GEMINIA_WF_RX_LG_SQDC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11106;"	d
+RG_GEMINIA_WF_RX_LG_SQDC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11108;"	d
+RG_GEMINIA_WF_RX_LG_SQDC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11110;"	d
+RG_GEMINIA_WF_RX_LG_TZI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11124;"	d
+RG_GEMINIA_WF_RX_LG_TZI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11122;"	d
+RG_GEMINIA_WF_RX_LG_TZI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11121;"	d
+RG_GEMINIA_WF_RX_LG_TZI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11123;"	d
+RG_GEMINIA_WF_RX_LG_TZI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11125;"	d
+RG_GEMINIA_WF_RX_LG_TZ_CAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11104;"	d
+RG_GEMINIA_WF_RX_LG_TZ_CAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11102;"	d
+RG_GEMINIA_WF_RX_LG_TZ_CAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11101;"	d
+RG_GEMINIA_WF_RX_LG_TZ_CAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11103;"	d
+RG_GEMINIA_WF_RX_LG_TZ_CAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11105;"	d
+RG_GEMINIA_WF_RX_LG_TZ_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11084;"	d
+RG_GEMINIA_WF_RX_LG_TZ_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11082;"	d
+RG_GEMINIA_WF_RX_LG_TZ_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11081;"	d
+RG_GEMINIA_WF_RX_LG_TZ_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11083;"	d
+RG_GEMINIA_WF_RX_LG_TZ_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11085;"	d
+RG_GEMINIA_WF_RX_LG_TZ_VCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11129;"	d
+RG_GEMINIA_WF_RX_LG_TZ_VCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11127;"	d
+RG_GEMINIA_WF_RX_LG_TZ_VCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11126;"	d
+RG_GEMINIA_WF_RX_LG_TZ_VCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11128;"	d
+RG_GEMINIA_WF_RX_LG_TZ_VCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11130;"	d
+RG_GEMINIA_WF_RX_MG_DIV2_CORE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11059;"	d
+RG_GEMINIA_WF_RX_MG_DIV2_CORE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11057;"	d
+RG_GEMINIA_WF_RX_MG_DIV2_CORE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11056;"	d
+RG_GEMINIA_WF_RX_MG_DIV2_CORE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11058;"	d
+RG_GEMINIA_WF_RX_MG_DIV2_CORE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11060;"	d
+RG_GEMINIA_WF_RX_MG_LNAHGN_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11034;"	d
+RG_GEMINIA_WF_RX_MG_LNAHGN_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11032;"	d
+RG_GEMINIA_WF_RX_MG_LNAHGN_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11031;"	d
+RG_GEMINIA_WF_RX_MG_LNAHGN_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11033;"	d
+RG_GEMINIA_WF_RX_MG_LNAHGN_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11035;"	d
+RG_GEMINIA_WF_RX_MG_LNAHGP_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11039;"	d
+RG_GEMINIA_WF_RX_MG_LNAHGP_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11037;"	d
+RG_GEMINIA_WF_RX_MG_LNAHGP_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11036;"	d
+RG_GEMINIA_WF_RX_MG_LNAHGP_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11038;"	d
+RG_GEMINIA_WF_RX_MG_LNAHGP_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11040;"	d
+RG_GEMINIA_WF_RX_MG_LNALG_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11044;"	d
+RG_GEMINIA_WF_RX_MG_LNALG_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11042;"	d
+RG_GEMINIA_WF_RX_MG_LNALG_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11041;"	d
+RG_GEMINIA_WF_RX_MG_LNALG_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11043;"	d
+RG_GEMINIA_WF_RX_MG_LNALG_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11045;"	d
+RG_GEMINIA_WF_RX_MG_LNA_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11024;"	d
+RG_GEMINIA_WF_RX_MG_LNA_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11022;"	d
+RG_GEMINIA_WF_RX_MG_LNA_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11021;"	d
+RG_GEMINIA_WF_RX_MG_LNA_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11023;"	d
+RG_GEMINIA_WF_RX_MG_LNA_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11025;"	d
+RG_GEMINIA_WF_RX_MG_LOBUF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11064;"	d
+RG_GEMINIA_WF_RX_MG_LOBUF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11062;"	d
+RG_GEMINIA_WF_RX_MG_LOBUF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11061;"	d
+RG_GEMINIA_WF_RX_MG_LOBUF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11063;"	d
+RG_GEMINIA_WF_RX_MG_LOBUF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11065;"	d
+RG_GEMINIA_WF_RX_MG_SQDC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11054;"	d
+RG_GEMINIA_WF_RX_MG_SQDC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11052;"	d
+RG_GEMINIA_WF_RX_MG_SQDC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11051;"	d
+RG_GEMINIA_WF_RX_MG_SQDC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11053;"	d
+RG_GEMINIA_WF_RX_MG_SQDC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11055;"	d
+RG_GEMINIA_WF_RX_MG_TZI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11069;"	d
+RG_GEMINIA_WF_RX_MG_TZI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11067;"	d
+RG_GEMINIA_WF_RX_MG_TZI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11066;"	d
+RG_GEMINIA_WF_RX_MG_TZI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11068;"	d
+RG_GEMINIA_WF_RX_MG_TZI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11070;"	d
+RG_GEMINIA_WF_RX_MG_TZ_CAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11049;"	d
+RG_GEMINIA_WF_RX_MG_TZ_CAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11047;"	d
+RG_GEMINIA_WF_RX_MG_TZ_CAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11046;"	d
+RG_GEMINIA_WF_RX_MG_TZ_CAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11048;"	d
+RG_GEMINIA_WF_RX_MG_TZ_CAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11050;"	d
+RG_GEMINIA_WF_RX_MG_TZ_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11029;"	d
+RG_GEMINIA_WF_RX_MG_TZ_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11027;"	d
+RG_GEMINIA_WF_RX_MG_TZ_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11026;"	d
+RG_GEMINIA_WF_RX_MG_TZ_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11028;"	d
+RG_GEMINIA_WF_RX_MG_TZ_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11030;"	d
+RG_GEMINIA_WF_RX_MG_TZ_VCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11074;"	d
+RG_GEMINIA_WF_RX_MG_TZ_VCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11072;"	d
+RG_GEMINIA_WF_RX_MG_TZ_VCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11071;"	d
+RG_GEMINIA_WF_RX_MG_TZ_VCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11073;"	d
+RG_GEMINIA_WF_RX_MG_TZ_VCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11075;"	d
+RG_GEMINIA_WF_RX_OUTVCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10694;"	d
+RG_GEMINIA_WF_RX_OUTVCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10692;"	d
+RG_GEMINIA_WF_RX_OUTVCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10691;"	d
+RG_GEMINIA_WF_RX_OUTVCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10693;"	d
+RG_GEMINIA_WF_RX_OUTVCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10695;"	d
+RG_GEMINIA_WF_RX_ULG_DIV2_CORE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11169;"	d
+RG_GEMINIA_WF_RX_ULG_DIV2_CORE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11167;"	d
+RG_GEMINIA_WF_RX_ULG_DIV2_CORE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11166;"	d
+RG_GEMINIA_WF_RX_ULG_DIV2_CORE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11168;"	d
+RG_GEMINIA_WF_RX_ULG_DIV2_CORE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11170;"	d
+RG_GEMINIA_WF_RX_ULG_LNAHGN_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11144;"	d
+RG_GEMINIA_WF_RX_ULG_LNAHGN_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11142;"	d
+RG_GEMINIA_WF_RX_ULG_LNAHGN_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11141;"	d
+RG_GEMINIA_WF_RX_ULG_LNAHGN_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11143;"	d
+RG_GEMINIA_WF_RX_ULG_LNAHGN_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11145;"	d
+RG_GEMINIA_WF_RX_ULG_LNAHGP_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11149;"	d
+RG_GEMINIA_WF_RX_ULG_LNAHGP_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11147;"	d
+RG_GEMINIA_WF_RX_ULG_LNAHGP_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11146;"	d
+RG_GEMINIA_WF_RX_ULG_LNAHGP_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11148;"	d
+RG_GEMINIA_WF_RX_ULG_LNAHGP_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11150;"	d
+RG_GEMINIA_WF_RX_ULG_LNALG_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11154;"	d
+RG_GEMINIA_WF_RX_ULG_LNALG_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11152;"	d
+RG_GEMINIA_WF_RX_ULG_LNALG_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11151;"	d
+RG_GEMINIA_WF_RX_ULG_LNALG_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11153;"	d
+RG_GEMINIA_WF_RX_ULG_LNALG_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11155;"	d
+RG_GEMINIA_WF_RX_ULG_LNA_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11134;"	d
+RG_GEMINIA_WF_RX_ULG_LNA_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11132;"	d
+RG_GEMINIA_WF_RX_ULG_LNA_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11131;"	d
+RG_GEMINIA_WF_RX_ULG_LNA_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11133;"	d
+RG_GEMINIA_WF_RX_ULG_LNA_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11135;"	d
+RG_GEMINIA_WF_RX_ULG_LOBUF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11174;"	d
+RG_GEMINIA_WF_RX_ULG_LOBUF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11172;"	d
+RG_GEMINIA_WF_RX_ULG_LOBUF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11171;"	d
+RG_GEMINIA_WF_RX_ULG_LOBUF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11173;"	d
+RG_GEMINIA_WF_RX_ULG_LOBUF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11175;"	d
+RG_GEMINIA_WF_RX_ULG_SQDC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11164;"	d
+RG_GEMINIA_WF_RX_ULG_SQDC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11162;"	d
+RG_GEMINIA_WF_RX_ULG_SQDC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11161;"	d
+RG_GEMINIA_WF_RX_ULG_SQDC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11163;"	d
+RG_GEMINIA_WF_RX_ULG_SQDC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11165;"	d
+RG_GEMINIA_WF_RX_ULG_TZI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11179;"	d
+RG_GEMINIA_WF_RX_ULG_TZI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11177;"	d
+RG_GEMINIA_WF_RX_ULG_TZI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11176;"	d
+RG_GEMINIA_WF_RX_ULG_TZI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11178;"	d
+RG_GEMINIA_WF_RX_ULG_TZI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11180;"	d
+RG_GEMINIA_WF_RX_ULG_TZ_CAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11159;"	d
+RG_GEMINIA_WF_RX_ULG_TZ_CAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11157;"	d
+RG_GEMINIA_WF_RX_ULG_TZ_CAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11156;"	d
+RG_GEMINIA_WF_RX_ULG_TZ_CAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11158;"	d
+RG_GEMINIA_WF_RX_ULG_TZ_CAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11160;"	d
+RG_GEMINIA_WF_RX_ULG_TZ_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11139;"	d
+RG_GEMINIA_WF_RX_ULG_TZ_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11137;"	d
+RG_GEMINIA_WF_RX_ULG_TZ_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11136;"	d
+RG_GEMINIA_WF_RX_ULG_TZ_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11138;"	d
+RG_GEMINIA_WF_RX_ULG_TZ_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11140;"	d
+RG_GEMINIA_WF_RX_ULG_TZ_VCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11184;"	d
+RG_GEMINIA_WF_RX_ULG_TZ_VCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11182;"	d
+RG_GEMINIA_WF_RX_ULG_TZ_VCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11181;"	d
+RG_GEMINIA_WF_RX_ULG_TZ_VCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11183;"	d
+RG_GEMINIA_WF_RX_ULG_TZ_VCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11185;"	d
+RG_GEMINIA_WF_TXLPF_BOOSTI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11519;"	d
+RG_GEMINIA_WF_TXLPF_BOOSTI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11517;"	d
+RG_GEMINIA_WF_TXLPF_BOOSTI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11516;"	d
+RG_GEMINIA_WF_TXLPF_BOOSTI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11518;"	d
+RG_GEMINIA_WF_TXLPF_BOOSTI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11520;"	d
+RG_GEMINIA_WF_TXPGA_CAPSW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10834;"	d
+RG_GEMINIA_WF_TXPGA_CAPSW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10832;"	d
+RG_GEMINIA_WF_TXPGA_CAPSW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10831;"	d
+RG_GEMINIA_WF_TXPGA_CAPSW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10833;"	d
+RG_GEMINIA_WF_TXPGA_CAPSW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10835;"	d
+RG_GEMINIA_WF_TX_DACI1ST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11489;"	d
+RG_GEMINIA_WF_TX_DACI1ST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11487;"	d
+RG_GEMINIA_WF_TX_DACI1ST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11486;"	d
+RG_GEMINIA_WF_TX_DACI1ST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11488;"	d
+RG_GEMINIA_WF_TX_DACI1ST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11490;"	d
+RG_GEMINIA_WF_TX_DACLPF_ICOARSE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11494;"	d
+RG_GEMINIA_WF_TX_DACLPF_ICOARSE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11492;"	d
+RG_GEMINIA_WF_TX_DACLPF_ICOARSE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11491;"	d
+RG_GEMINIA_WF_TX_DACLPF_ICOARSE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11493;"	d
+RG_GEMINIA_WF_TX_DACLPF_ICOARSE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11495;"	d
+RG_GEMINIA_WF_TX_DACLPF_IFINE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11499;"	d
+RG_GEMINIA_WF_TX_DACLPF_IFINE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11497;"	d
+RG_GEMINIA_WF_TX_DACLPF_IFINE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11496;"	d
+RG_GEMINIA_WF_TX_DACLPF_IFINE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11498;"	d
+RG_GEMINIA_WF_TX_DACLPF_IFINE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11500;"	d
+RG_GEMINIA_WF_TX_DACLPF_VCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11504;"	d
+RG_GEMINIA_WF_TX_DACLPF_VCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11502;"	d
+RG_GEMINIA_WF_TX_DACLPF_VCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11501;"	d
+RG_GEMINIA_WF_TX_DACLPF_VCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11503;"	d
+RG_GEMINIA_WF_TX_DACLPF_VCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11505;"	d
+RG_GEMINIA_WF_TX_DAC_CKEDGE_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11529;"	d
+RG_GEMINIA_WF_TX_DAC_CKEDGE_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11527;"	d
+RG_GEMINIA_WF_TX_DAC_CKEDGE_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11526;"	d
+RG_GEMINIA_WF_TX_DAC_CKEDGE_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11528;"	d
+RG_GEMINIA_WF_TX_DAC_CKEDGE_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11530;"	d
+RG_GEMINIA_WF_TX_DAC_IATTN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11514;"	d
+RG_GEMINIA_WF_TX_DAC_IATTN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11512;"	d
+RG_GEMINIA_WF_TX_DAC_IATTN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11511;"	d
+RG_GEMINIA_WF_TX_DAC_IATTN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11513;"	d
+RG_GEMINIA_WF_TX_DAC_IATTN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11515;"	d
+RG_GEMINIA_WF_TX_DAC_IBIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11509;"	d
+RG_GEMINIA_WF_TX_DAC_IBIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11507;"	d
+RG_GEMINIA_WF_TX_DAC_IBIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11506;"	d
+RG_GEMINIA_WF_TX_DAC_IBIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11508;"	d
+RG_GEMINIA_WF_TX_DAC_IBIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11510;"	d
+RG_GEMINIA_WF_TX_DAC_IOFFSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11539;"	d
+RG_GEMINIA_WF_TX_DAC_IOFFSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11537;"	d
+RG_GEMINIA_WF_TX_DAC_IOFFSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11536;"	d
+RG_GEMINIA_WF_TX_DAC_IOFFSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11538;"	d
+RG_GEMINIA_WF_TX_DAC_IOFFSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11540;"	d
+RG_GEMINIA_WF_TX_DAC_OS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11534;"	d
+RG_GEMINIA_WF_TX_DAC_OS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11532;"	d
+RG_GEMINIA_WF_TX_DAC_OS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11531;"	d
+RG_GEMINIA_WF_TX_DAC_OS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11533;"	d
+RG_GEMINIA_WF_TX_DAC_OS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11535;"	d
+RG_GEMINIA_WF_TX_DAC_QOFFSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11544;"	d
+RG_GEMINIA_WF_TX_DAC_QOFFSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11542;"	d
+RG_GEMINIA_WF_TX_DAC_QOFFSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11541;"	d
+RG_GEMINIA_WF_TX_DAC_QOFFSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11543;"	d
+RG_GEMINIA_WF_TX_DAC_QOFFSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11545;"	d
+RG_GEMINIA_WF_TX_DAC_RCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	11524;"	d
+RG_GEMINIA_WF_TX_DAC_RCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11522;"	d
+RG_GEMINIA_WF_TX_DAC_RCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	11521;"	d
+RG_GEMINIA_WF_TX_DAC_RCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	11523;"	d
+RG_GEMINIA_WF_TX_DAC_RCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	11525;"	d
+RG_GEMINIA_WF_TX_DIV_VSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10839;"	d
+RG_GEMINIA_WF_TX_DIV_VSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10837;"	d
+RG_GEMINIA_WF_TX_DIV_VSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10836;"	d
+RG_GEMINIA_WF_TX_DIV_VSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10838;"	d
+RG_GEMINIA_WF_TX_DIV_VSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10840;"	d
+RG_GEMINIA_WF_TX_GAIN_OFFSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10939;"	d
+RG_GEMINIA_WF_TX_GAIN_OFFSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10937;"	d
+RG_GEMINIA_WF_TX_GAIN_OFFSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10936;"	d
+RG_GEMINIA_WF_TX_GAIN_OFFSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10938;"	d
+RG_GEMINIA_WF_TX_GAIN_OFFSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10940;"	d
+RG_GEMINIA_WF_TX_LOBUF_VSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10844;"	d
+RG_GEMINIA_WF_TX_LOBUF_VSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10842;"	d
+RG_GEMINIA_WF_TX_LOBUF_VSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10841;"	d
+RG_GEMINIA_WF_TX_LOBUF_VSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10843;"	d
+RG_GEMINIA_WF_TX_LOBUF_VSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10845;"	d
+RG_GEMINIA_WF_TX_PA1_VCAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10884;"	d
+RG_GEMINIA_WF_TX_PA1_VCAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10882;"	d
+RG_GEMINIA_WF_TX_PA1_VCAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10881;"	d
+RG_GEMINIA_WF_TX_PA1_VCAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10883;"	d
+RG_GEMINIA_WF_TX_PA1_VCAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10885;"	d
+RG_GEMINIA_WF_TX_PA2_VCAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10889;"	d
+RG_GEMINIA_WF_TX_PA2_VCAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10887;"	d
+RG_GEMINIA_WF_TX_PA2_VCAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10886;"	d
+RG_GEMINIA_WF_TX_PA2_VCAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10888;"	d
+RG_GEMINIA_WF_TX_PA2_VCAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10890;"	d
+RG_GEMINIA_WF_TX_PA3_VCAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10894;"	d
+RG_GEMINIA_WF_TX_PA3_VCAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10892;"	d
+RG_GEMINIA_WF_TX_PA3_VCAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10891;"	d
+RG_GEMINIA_WF_TX_PA3_VCAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10893;"	d
+RG_GEMINIA_WF_TX_PA3_VCAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10895;"	d
+RG_GEMINIA_WF_TX_VDDSW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10849;"	d
+RG_GEMINIA_WF_TX_VDDSW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10847;"	d
+RG_GEMINIA_WF_TX_VDDSW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10846;"	d
+RG_GEMINIA_WF_TX_VDDSW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10848;"	d
+RG_GEMINIA_WF_TX_VDDSW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10850;"	d
+RG_GEMINIA_XO_CBANKI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13779;"	d
+RG_GEMINIA_XO_CBANKI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13777;"	d
+RG_GEMINIA_XO_CBANKI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13776;"	d
+RG_GEMINIA_XO_CBANKI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13778;"	d
+RG_GEMINIA_XO_CBANKI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13780;"	d
+RG_GEMINIA_XO_CBANKO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13784;"	d
+RG_GEMINIA_XO_CBANKO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13782;"	d
+RG_GEMINIA_XO_CBANKO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13781;"	d
+RG_GEMINIA_XO_CBANKO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13783;"	d
+RG_GEMINIA_XO_CBANKO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13785;"	d
+RG_GEMINIA_XO_LDO_LEVEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13774;"	d
+RG_GEMINIA_XO_LDO_LEVEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13772;"	d
+RG_GEMINIA_XO_LDO_LEVEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13771;"	d
+RG_GEMINIA_XO_LDO_LEVEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13773;"	d
+RG_GEMINIA_XO_LDO_LEVEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13775;"	d
+RG_GEMINIA_XO_TIMMER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13844;"	d
+RG_GEMINIA_XO_TIMMER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13842;"	d
+RG_GEMINIA_XO_TIMMER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13841;"	d
+RG_GEMINIA_XO_TIMMER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13843;"	d
+RG_GEMINIA_XO_TIMMER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13845;"	d
+RG_GP_DIV_EN_HI	include/ssv6200_aux.h	15574;"	d
+RG_GP_DIV_EN_I_MSK	include/ssv6200_aux.h	15572;"	d
+RG_GP_DIV_EN_MSK	include/ssv6200_aux.h	15571;"	d
+RG_GP_DIV_EN_SFT	include/ssv6200_aux.h	15573;"	d
+RG_GP_DIV_EN_SZ	include/ssv6200_aux.h	15575;"	d
+RG_HB_COEF0_HI	include/ssv6200_aux.h	14049;"	d
+RG_HB_COEF0_I_MSK	include/ssv6200_aux.h	14047;"	d
+RG_HB_COEF0_MSK	include/ssv6200_aux.h	14046;"	d
+RG_HB_COEF0_SFT	include/ssv6200_aux.h	14048;"	d
+RG_HB_COEF0_SZ	include/ssv6200_aux.h	14050;"	d
+RG_HB_COEF1_HI	include/ssv6200_aux.h	14054;"	d
+RG_HB_COEF1_I_MSK	include/ssv6200_aux.h	14052;"	d
+RG_HB_COEF1_MSK	include/ssv6200_aux.h	14051;"	d
+RG_HB_COEF1_SFT	include/ssv6200_aux.h	14053;"	d
+RG_HB_COEF1_SZ	include/ssv6200_aux.h	14055;"	d
+RG_HB_COEF2_HI	include/ssv6200_aux.h	14059;"	d
+RG_HB_COEF2_I_MSK	include/ssv6200_aux.h	14057;"	d
+RG_HB_COEF2_MSK	include/ssv6200_aux.h	14056;"	d
+RG_HB_COEF2_SFT	include/ssv6200_aux.h	14058;"	d
+RG_HB_COEF2_SZ	include/ssv6200_aux.h	14060;"	d
+RG_HB_COEF3_HI	include/ssv6200_aux.h	14064;"	d
+RG_HB_COEF3_I_MSK	include/ssv6200_aux.h	14062;"	d
+RG_HB_COEF3_MSK	include/ssv6200_aux.h	14061;"	d
+RG_HB_COEF3_SFT	include/ssv6200_aux.h	14063;"	d
+RG_HB_COEF3_SZ	include/ssv6200_aux.h	14065;"	d
+RG_HB_COEF4_HI	include/ssv6200_aux.h	14069;"	d
+RG_HB_COEF4_I_MSK	include/ssv6200_aux.h	14067;"	d
+RG_HB_COEF4_MSK	include/ssv6200_aux.h	14066;"	d
+RG_HB_COEF4_SFT	include/ssv6200_aux.h	14068;"	d
+RG_HB_COEF4_SZ	include/ssv6200_aux.h	14070;"	d
+RG_HG_PGA_SAT1_PGA_GAIN_HI	include/ssv6200_aux.h	13389;"	d
+RG_HG_PGA_SAT1_PGA_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30579;"	d
+RG_HG_PGA_SAT1_PGA_GAIN_I_MSK	include/ssv6200_aux.h	13387;"	d
+RG_HG_PGA_SAT1_PGA_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30577;"	d
+RG_HG_PGA_SAT1_PGA_GAIN_MSK	include/ssv6200_aux.h	13386;"	d
+RG_HG_PGA_SAT1_PGA_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30576;"	d
+RG_HG_PGA_SAT1_PGA_GAIN_SFT	include/ssv6200_aux.h	13388;"	d
+RG_HG_PGA_SAT1_PGA_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30578;"	d
+RG_HG_PGA_SAT1_PGA_GAIN_SZ	include/ssv6200_aux.h	13390;"	d
+RG_HG_PGA_SAT1_PGA_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30580;"	d
+RG_HG_PGA_SAT2_PGA_GAIN_HI	include/ssv6200_aux.h	13384;"	d
+RG_HG_PGA_SAT2_PGA_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30574;"	d
+RG_HG_PGA_SAT2_PGA_GAIN_I_MSK	include/ssv6200_aux.h	13382;"	d
+RG_HG_PGA_SAT2_PGA_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30572;"	d
+RG_HG_PGA_SAT2_PGA_GAIN_MSK	include/ssv6200_aux.h	13381;"	d
+RG_HG_PGA_SAT2_PGA_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30571;"	d
+RG_HG_PGA_SAT2_PGA_GAIN_SFT	include/ssv6200_aux.h	13383;"	d
+RG_HG_PGA_SAT2_PGA_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30573;"	d
+RG_HG_PGA_SAT2_PGA_GAIN_SZ	include/ssv6200_aux.h	13385;"	d
+RG_HG_PGA_SAT2_PGA_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30575;"	d
+RG_HG_RF_SAT_PGA_GAIN_HI	include/ssv6200_aux.h	13394;"	d
+RG_HG_RF_SAT_PGA_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30584;"	d
+RG_HG_RF_SAT_PGA_GAIN_I_MSK	include/ssv6200_aux.h	13392;"	d
+RG_HG_RF_SAT_PGA_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30582;"	d
+RG_HG_RF_SAT_PGA_GAIN_MSK	include/ssv6200_aux.h	13391;"	d
+RG_HG_RF_SAT_PGA_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30581;"	d
+RG_HG_RF_SAT_PGA_GAIN_SFT	include/ssv6200_aux.h	13393;"	d
+RG_HG_RF_SAT_PGA_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30583;"	d
+RG_HG_RF_SAT_PGA_GAIN_SZ	include/ssv6200_aux.h	13395;"	d
+RG_HG_RF_SAT_PGA_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30585;"	d
+RG_HPF1_FAST_SET_X_HI	include/ssv6200_aux.h	16699;"	d
+RG_HPF1_FAST_SET_X_I_MSK	include/ssv6200_aux.h	16697;"	d
+RG_HPF1_FAST_SET_X_MSK	include/ssv6200_aux.h	16696;"	d
+RG_HPF1_FAST_SET_X_SFT	include/ssv6200_aux.h	16698;"	d
+RG_HPF1_FAST_SET_X_SZ	include/ssv6200_aux.h	16700;"	d
+RG_HPF1_FAST_SET_Y_HI	include/ssv6200_aux.h	16704;"	d
+RG_HPF1_FAST_SET_Y_I_MSK	include/ssv6200_aux.h	16702;"	d
+RG_HPF1_FAST_SET_Y_MSK	include/ssv6200_aux.h	16701;"	d
+RG_HPF1_FAST_SET_Y_SFT	include/ssv6200_aux.h	16703;"	d
+RG_HPF1_FAST_SET_Y_SZ	include/ssv6200_aux.h	16705;"	d
+RG_HPF1_FAST_SET_Z_HI	include/ssv6200_aux.h	16709;"	d
+RG_HPF1_FAST_SET_Z_I_MSK	include/ssv6200_aux.h	16707;"	d
+RG_HPF1_FAST_SET_Z_MSK	include/ssv6200_aux.h	16706;"	d
+RG_HPF1_FAST_SET_Z_SFT	include/ssv6200_aux.h	16708;"	d
+RG_HPF1_FAST_SET_Z_SZ	include/ssv6200_aux.h	16710;"	d
+RG_HPF_T1A_HI	include/ssv6200_aux.h	16714;"	d
+RG_HPF_T1A_I_MSK	include/ssv6200_aux.h	16712;"	d
+RG_HPF_T1A_MSK	include/ssv6200_aux.h	16711;"	d
+RG_HPF_T1A_SFT	include/ssv6200_aux.h	16713;"	d
+RG_HPF_T1A_SZ	include/ssv6200_aux.h	16715;"	d
+RG_HPF_T1B_HI	include/ssv6200_aux.h	16719;"	d
+RG_HPF_T1B_I_MSK	include/ssv6200_aux.h	16717;"	d
+RG_HPF_T1B_MSK	include/ssv6200_aux.h	16716;"	d
+RG_HPF_T1B_SFT	include/ssv6200_aux.h	16718;"	d
+RG_HPF_T1B_SZ	include/ssv6200_aux.h	16720;"	d
+RG_HPF_T1C_HI	include/ssv6200_aux.h	16724;"	d
+RG_HPF_T1C_I_MSK	include/ssv6200_aux.h	16722;"	d
+RG_HPF_T1C_MSK	include/ssv6200_aux.h	16721;"	d
+RG_HPF_T1C_SFT	include/ssv6200_aux.h	16723;"	d
+RG_HPF_T1C_SZ	include/ssv6200_aux.h	16725;"	d
+RG_HS3W_COMM_DATA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27694;"	d
+RG_HS3W_COMM_DATA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27692;"	d
+RG_HS3W_COMM_DATA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27691;"	d
+RG_HS3W_COMM_DATA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27693;"	d
+RG_HS3W_COMM_DATA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27695;"	d
+RG_HS3W_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27689;"	d
+RG_HS3W_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27687;"	d
+RG_HS3W_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27686;"	d
+RG_HS3W_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27688;"	d
+RG_HS3W_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27690;"	d
+RG_HS3W_PGAGC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27669;"	d
+RG_HS3W_PGAGC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27667;"	d
+RG_HS3W_PGAGC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27666;"	d
+RG_HS3W_PGAGC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27668;"	d
+RG_HS3W_PGAGC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27670;"	d
+RG_HS3W_RFGC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27674;"	d
+RG_HS3W_RFGC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27672;"	d
+RG_HS3W_RFGC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27671;"	d
+RG_HS3W_RFGC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27673;"	d
+RG_HS3W_RFGC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27675;"	d
+RG_HS3W_RF_PHY_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27684;"	d
+RG_HS3W_RF_PHY_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27682;"	d
+RG_HS3W_RF_PHY_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27681;"	d
+RG_HS3W_RF_PHY_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27683;"	d
+RG_HS3W_RF_PHY_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27685;"	d
+RG_HS3W_RXAGC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27679;"	d
+RG_HS3W_RXAGC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27677;"	d
+RG_HS3W_RXAGC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27676;"	d
+RG_HS3W_RXAGC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27678;"	d
+RG_HS3W_RXAGC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27680;"	d
+RG_HS3W_START_SENT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27699;"	d
+RG_HS3W_START_SENT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27697;"	d
+RG_HS3W_START_SENT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27696;"	d
+RG_HS3W_START_SENT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27698;"	d
+RG_HS3W_START_SENT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27700;"	d
+RG_HS3W_SX_CHANNEL_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27714;"	d
+RG_HS3W_SX_CHANNEL_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27712;"	d
+RG_HS3W_SX_CHANNEL_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27711;"	d
+RG_HS3W_SX_CHANNEL_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27713;"	d
+RG_HS3W_SX_CHANNEL_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27715;"	d
+RG_HS3W_SX_RFCH_MAP_EN_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27709;"	d
+RG_HS3W_SX_RFCH_MAP_EN_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27707;"	d
+RG_HS3W_SX_RFCH_MAP_EN_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27706;"	d
+RG_HS3W_SX_RFCH_MAP_EN_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27708;"	d
+RG_HS3W_SX_RFCH_MAP_EN_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27710;"	d
+RG_HS3W_SX_RFCTRL_CH_INT_10_8_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27704;"	d
+RG_HS3W_SX_RFCTRL_CH_INT_10_8_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27702;"	d
+RG_HS3W_SX_RFCTRL_CH_INT_10_8_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27701;"	d
+RG_HS3W_SX_RFCTRL_CH_INT_10_8_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27703;"	d
+RG_HS3W_SX_RFCTRL_CH_INT_10_8_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27705;"	d
+RG_HS3W_SX_RFCTRL_CH_INT_7_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27724;"	d
+RG_HS3W_SX_RFCTRL_CH_INT_7_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27722;"	d
+RG_HS3W_SX_RFCTRL_CH_INT_7_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27721;"	d
+RG_HS3W_SX_RFCTRL_CH_INT_7_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27723;"	d
+RG_HS3W_SX_RFCTRL_CH_INT_7_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27725;"	d
+RG_HS3W_SX_RFCTRL_F_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27719;"	d
+RG_HS3W_SX_RFCTRL_F_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27717;"	d
+RG_HS3W_SX_RFCTRL_F_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27716;"	d
+RG_HS3W_SX_RFCTRL_F_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27718;"	d
+RG_HS3W_SX_RFCTRL_F_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27720;"	d
+RG_HS3W_TX_RF_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27664;"	d
+RG_HS3W_TX_RF_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27662;"	d
+RG_HS3W_TX_RF_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27661;"	d
+RG_HS3W_TX_RF_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27663;"	d
+RG_HS3W_TX_RF_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27665;"	d
+RG_HS5W_M_CAL_INDEX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29409;"	d
+RG_HS5W_M_CAL_INDEX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29407;"	d
+RG_HS5W_M_CAL_INDEX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29406;"	d
+RG_HS5W_M_CAL_INDEX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29408;"	d
+RG_HS5W_M_CAL_INDEX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29410;"	d
+RG_HS5W_M_CMD0_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29399;"	d
+RG_HS5W_M_CMD0_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29397;"	d
+RG_HS5W_M_CMD0_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29396;"	d
+RG_HS5W_M_CMD0_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29398;"	d
+RG_HS5W_M_CMD0_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29400;"	d
+RG_HS5W_M_CMD1_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29394;"	d
+RG_HS5W_M_CMD1_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29392;"	d
+RG_HS5W_M_CMD1_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29391;"	d
+RG_HS5W_M_CMD1_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29393;"	d
+RG_HS5W_M_CMD1_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29395;"	d
+RG_HS5W_M_CMD2_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29389;"	d
+RG_HS5W_M_CMD2_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29387;"	d
+RG_HS5W_M_CMD2_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29386;"	d
+RG_HS5W_M_CMD2_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29388;"	d
+RG_HS5W_M_CMD2_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29390;"	d
+RG_HS5W_M_CMD3_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29384;"	d
+RG_HS5W_M_CMD3_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29382;"	d
+RG_HS5W_M_CMD3_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29381;"	d
+RG_HS5W_M_CMD3_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29383;"	d
+RG_HS5W_M_CMD3_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29385;"	d
+RG_HS5W_M_CMD4_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29379;"	d
+RG_HS5W_M_CMD4_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29377;"	d
+RG_HS5W_M_CMD4_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29376;"	d
+RG_HS5W_M_CMD4_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29378;"	d
+RG_HS5W_M_CMD4_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29380;"	d
+RG_HS5W_M_CMD5_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29374;"	d
+RG_HS5W_M_CMD5_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29372;"	d
+RG_HS5W_M_CMD5_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29371;"	d
+RG_HS5W_M_CMD5_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29373;"	d
+RG_HS5W_M_CMD5_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29375;"	d
+RG_HS5W_M_CMD6_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29369;"	d
+RG_HS5W_M_CMD6_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29367;"	d
+RG_HS5W_M_CMD6_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29366;"	d
+RG_HS5W_M_CMD6_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29368;"	d
+RG_HS5W_M_CMD6_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29370;"	d
+RG_HS5W_M_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29364;"	d
+RG_HS5W_M_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29362;"	d
+RG_HS5W_M_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29361;"	d
+RG_HS5W_M_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29363;"	d
+RG_HS5W_M_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29365;"	d
+RG_HS5W_M_MD_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29359;"	d
+RG_HS5W_M_MD_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29357;"	d
+RG_HS5W_M_MD_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29356;"	d
+RG_HS5W_M_MD_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29358;"	d
+RG_HS5W_M_MD_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29360;"	d
+RG_HS5W_M_PGAGC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29414;"	d
+RG_HS5W_M_PGAGC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29412;"	d
+RG_HS5W_M_PGAGC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29411;"	d
+RG_HS5W_M_PGAGC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29413;"	d
+RG_HS5W_M_PGAGC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29415;"	d
+RG_HS5W_M_PHY_BW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29469;"	d
+RG_HS5W_M_PHY_BW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29467;"	d
+RG_HS5W_M_PHY_BW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29466;"	d
+RG_HS5W_M_PHY_BW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29468;"	d
+RG_HS5W_M_PHY_BW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29470;"	d
+RG_HS5W_M_RFGC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29419;"	d
+RG_HS5W_M_RFGC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29417;"	d
+RG_HS5W_M_RFGC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29416;"	d
+RG_HS5W_M_RFGC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29418;"	d
+RG_HS5W_M_RFGC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29420;"	d
+RG_HS5W_M_RF_PHY_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29404;"	d
+RG_HS5W_M_RF_PHY_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29402;"	d
+RG_HS5W_M_RF_PHY_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29401;"	d
+RG_HS5W_M_RF_PHY_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29403;"	d
+RG_HS5W_M_RF_PHY_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29405;"	d
+RG_HS5W_M_SX5GB_CHANNEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29464;"	d
+RG_HS5W_M_SX5GB_CHANNEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29462;"	d
+RG_HS5W_M_SX5GB_CHANNEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29461;"	d
+RG_HS5W_M_SX5GB_CHANNEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29463;"	d
+RG_HS5W_M_SX5GB_CHANNEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29465;"	d
+RG_HS5W_M_SX5GB_RFCH_MAP_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29454;"	d
+RG_HS5W_M_SX5GB_RFCH_MAP_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29452;"	d
+RG_HS5W_M_SX5GB_RFCH_MAP_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29451;"	d
+RG_HS5W_M_SX5GB_RFCH_MAP_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29453;"	d
+RG_HS5W_M_SX5GB_RFCH_MAP_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29455;"	d
+RG_HS5W_M_SX5GB_RFCTRL_CH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29434;"	d
+RG_HS5W_M_SX5GB_RFCTRL_CH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29432;"	d
+RG_HS5W_M_SX5GB_RFCTRL_CH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29431;"	d
+RG_HS5W_M_SX5GB_RFCTRL_CH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29433;"	d
+RG_HS5W_M_SX5GB_RFCTRL_CH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29435;"	d
+RG_HS5W_M_SX5GB_RFCTRL_F_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29449;"	d
+RG_HS5W_M_SX5GB_RFCTRL_F_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29447;"	d
+RG_HS5W_M_SX5GB_RFCTRL_F_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29446;"	d
+RG_HS5W_M_SX5GB_RFCTRL_F_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29448;"	d
+RG_HS5W_M_SX5GB_RFCTRL_F_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29450;"	d
+RG_HS5W_M_SX_CHANNEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29459;"	d
+RG_HS5W_M_SX_CHANNEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29457;"	d
+RG_HS5W_M_SX_CHANNEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29456;"	d
+RG_HS5W_M_SX_CHANNEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29458;"	d
+RG_HS5W_M_SX_CHANNEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29460;"	d
+RG_HS5W_M_SX_RFCH_MAP_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29444;"	d
+RG_HS5W_M_SX_RFCH_MAP_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29442;"	d
+RG_HS5W_M_SX_RFCH_MAP_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29441;"	d
+RG_HS5W_M_SX_RFCH_MAP_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29443;"	d
+RG_HS5W_M_SX_RFCH_MAP_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29445;"	d
+RG_HS5W_M_SX_RFCTRL_CH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29429;"	d
+RG_HS5W_M_SX_RFCTRL_CH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29427;"	d
+RG_HS5W_M_SX_RFCTRL_CH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29426;"	d
+RG_HS5W_M_SX_RFCTRL_CH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29428;"	d
+RG_HS5W_M_SX_RFCTRL_CH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29430;"	d
+RG_HS5W_M_SX_RFCTRL_F_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29439;"	d
+RG_HS5W_M_SX_RFCTRL_F_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29437;"	d
+RG_HS5W_M_SX_RFCTRL_F_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29436;"	d
+RG_HS5W_M_SX_RFCTRL_F_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29438;"	d
+RG_HS5W_M_SX_RFCTRL_F_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29440;"	d
+RG_HS5W_M_TXPWRLVL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29424;"	d
+RG_HS5W_M_TXPWRLVL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29422;"	d
+RG_HS5W_M_TXPWRLVL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29421;"	d
+RG_HS5W_M_TXPWRLVL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29423;"	d
+RG_HS5W_M_TXPWRLVL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29425;"	d
+RG_HSDIV_INBFSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26059;"	d
+RG_HSDIV_INBFSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26057;"	d
+RG_HSDIV_INBFSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26056;"	d
+RG_HSDIV_INBFSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26058;"	d
+RG_HSDIV_INBFSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26060;"	d
+RG_HSDIV_OBFMX_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26064;"	d
+RG_HSDIV_OBFMX_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26062;"	d
+RG_HSDIV_OBFMX_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26061;"	d
+RG_HSDIV_OBFMX_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26063;"	d
+RG_HSDIV_OBFMX_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26065;"	d
+RG_HSDIV_OBFSX_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26069;"	d
+RG_HSDIV_OBFSX_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26067;"	d
+RG_HSDIV_OBFSX_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26066;"	d
+RG_HSDIV_OBFSX_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26068;"	d
+RG_HSDIV_OBFSX_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26070;"	d
+RG_HSDIV_VRSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26074;"	d
+RG_HSDIV_VRSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26072;"	d
+RG_HSDIV_VRSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26071;"	d
+RG_HSDIV_VRSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26073;"	d
+RG_HSDIV_VRSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26075;"	d
+RG_HS_3WIRE_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21574;"	d
+RG_HS_3WIRE_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21572;"	d
+RG_HS_3WIRE_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21571;"	d
+RG_HS_3WIRE_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21573;"	d
+RG_HS_3WIRE_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21575;"	d
+RG_HT20_RX_FFT_SCALE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32079;"	d
+RG_HT20_RX_FFT_SCALE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32077;"	d
+RG_HT20_RX_FFT_SCALE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32076;"	d
+RG_HT20_RX_FFT_SCALE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32078;"	d
+RG_HT20_RX_FFT_SCALE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32080;"	d
+RG_HT20_SYM_BOUND_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32039;"	d
+RG_HT20_SYM_BOUND_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32037;"	d
+RG_HT20_SYM_BOUND_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32036;"	d
+RG_HT20_SYM_BOUND_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32038;"	d
+RG_HT20_SYM_BOUND_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32040;"	d
+RG_HT20_TR_LPF_KI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32019;"	d
+RG_HT20_TR_LPF_KI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32017;"	d
+RG_HT20_TR_LPF_KI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32016;"	d
+RG_HT20_TR_LPF_KI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32018;"	d
+RG_HT20_TR_LPF_KI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32020;"	d
+RG_HT20_TR_LPF_KP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32024;"	d
+RG_HT20_TR_LPF_KP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32022;"	d
+RG_HT20_TR_LPF_KP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32021;"	d
+RG_HT20_TR_LPF_KP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32023;"	d
+RG_HT20_TR_LPF_KP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32025;"	d
+RG_HT40_RX_FFT_SCALE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32189;"	d
+RG_HT40_RX_FFT_SCALE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32187;"	d
+RG_HT40_RX_FFT_SCALE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32186;"	d
+RG_HT40_RX_FFT_SCALE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32188;"	d
+RG_HT40_RX_FFT_SCALE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32190;"	d
+RG_HT40_SYM_BOUND_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32014;"	d
+RG_HT40_SYM_BOUND_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32012;"	d
+RG_HT40_SYM_BOUND_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32011;"	d
+RG_HT40_SYM_BOUND_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32013;"	d
+RG_HT40_SYM_BOUND_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32015;"	d
+RG_HT40_TR_LPF_KI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32004;"	d
+RG_HT40_TR_LPF_KI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32002;"	d
+RG_HT40_TR_LPF_KI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32001;"	d
+RG_HT40_TR_LPF_KI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32003;"	d
+RG_HT40_TR_LPF_KI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32005;"	d
+RG_HT40_TR_LPF_KP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32009;"	d
+RG_HT40_TR_LPF_KP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32007;"	d
+RG_HT40_TR_LPF_KP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32006;"	d
+RG_HT40_TR_LPF_KP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32008;"	d
+RG_HT40_TR_LPF_KP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32010;"	d
+RG_HTCARR52_FFT_SCALE_HI	include/ssv6200_aux.h	14689;"	d
+RG_HTCARR52_FFT_SCALE_I_MSK	include/ssv6200_aux.h	14687;"	d
+RG_HTCARR52_FFT_SCALE_MSK	include/ssv6200_aux.h	14686;"	d
+RG_HTCARR52_FFT_SCALE_SFT	include/ssv6200_aux.h	14688;"	d
+RG_HTCARR52_FFT_SCALE_SZ	include/ssv6200_aux.h	14690;"	d
+RG_HTCARR56_FFT_SCALE_HI	include/ssv6200_aux.h	14694;"	d
+RG_HTCARR56_FFT_SCALE_I_MSK	include/ssv6200_aux.h	14692;"	d
+RG_HTCARR56_FFT_SCALE_MSK	include/ssv6200_aux.h	14691;"	d
+RG_HTCARR56_FFT_SCALE_SFT	include/ssv6200_aux.h	14693;"	d
+RG_HTCARR56_FFT_SCALE_SZ	include/ssv6200_aux.h	14695;"	d
+RG_HT_LTF_SEL_EQ_HI	include/ssv6200_aux.h	15329;"	d
+RG_HT_LTF_SEL_EQ_I_MSK	include/ssv6200_aux.h	15327;"	d
+RG_HT_LTF_SEL_EQ_MSK	include/ssv6200_aux.h	15326;"	d
+RG_HT_LTF_SEL_EQ_SFT	include/ssv6200_aux.h	15328;"	d
+RG_HT_LTF_SEL_EQ_SZ	include/ssv6200_aux.h	15330;"	d
+RG_HT_LTF_SEL_PILOT_HI	include/ssv6200_aux.h	15334;"	d
+RG_HT_LTF_SEL_PILOT_I_MSK	include/ssv6200_aux.h	15332;"	d
+RG_HT_LTF_SEL_PILOT_MSK	include/ssv6200_aux.h	15331;"	d
+RG_HT_LTF_SEL_PILOT_SFT	include/ssv6200_aux.h	15333;"	d
+RG_HT_LTF_SEL_PILOT_SZ	include/ssv6200_aux.h	15335;"	d
+RG_HW_PINSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21569;"	d
+RG_HW_PINSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21567;"	d
+RG_HW_PINSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21566;"	d
+RG_HW_PINSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21568;"	d
+RG_HW_PINSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21570;"	d
+RG_HW_WAKE_XOSC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29534;"	d
+RG_HW_WAKE_XOSC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29532;"	d
+RG_HW_WAKE_XOSC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29531;"	d
+RG_HW_WAKE_XOSC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29533;"	d
+RG_HW_WAKE_XOSC_SLP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30104;"	d
+RG_HW_WAKE_XOSC_SLP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30102;"	d
+RG_HW_WAKE_XOSC_SLP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30101;"	d
+RG_HW_WAKE_XOSC_SLP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30103;"	d
+RG_HW_WAKE_XOSC_SLP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30105;"	d
+RG_HW_WAKE_XOSC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29535;"	d
+RG_IDACAI_PGAG0_HI	include/ssv6200_aux.h	17464;"	d
+RG_IDACAI_PGAG0_I_MSK	include/ssv6200_aux.h	17462;"	d
+RG_IDACAI_PGAG0_MSK	include/ssv6200_aux.h	17461;"	d
+RG_IDACAI_PGAG0_SFT	include/ssv6200_aux.h	17463;"	d
+RG_IDACAI_PGAG0_SZ	include/ssv6200_aux.h	17465;"	d
+RG_IDACAI_PGAG10_HI	include/ssv6200_aux.h	17364;"	d
+RG_IDACAI_PGAG10_I_MSK	include/ssv6200_aux.h	17362;"	d
+RG_IDACAI_PGAG10_MSK	include/ssv6200_aux.h	17361;"	d
+RG_IDACAI_PGAG10_SFT	include/ssv6200_aux.h	17363;"	d
+RG_IDACAI_PGAG10_SZ	include/ssv6200_aux.h	17365;"	d
+RG_IDACAI_PGAG11_HI	include/ssv6200_aux.h	17354;"	d
+RG_IDACAI_PGAG11_I_MSK	include/ssv6200_aux.h	17352;"	d
+RG_IDACAI_PGAG11_MSK	include/ssv6200_aux.h	17351;"	d
+RG_IDACAI_PGAG11_SFT	include/ssv6200_aux.h	17353;"	d
+RG_IDACAI_PGAG11_SZ	include/ssv6200_aux.h	17355;"	d
+RG_IDACAI_PGAG12_HI	include/ssv6200_aux.h	17344;"	d
+RG_IDACAI_PGAG12_I_MSK	include/ssv6200_aux.h	17342;"	d
+RG_IDACAI_PGAG12_MSK	include/ssv6200_aux.h	17341;"	d
+RG_IDACAI_PGAG12_SFT	include/ssv6200_aux.h	17343;"	d
+RG_IDACAI_PGAG12_SZ	include/ssv6200_aux.h	17345;"	d
+RG_IDACAI_PGAG13_HI	include/ssv6200_aux.h	17334;"	d
+RG_IDACAI_PGAG13_I_MSK	include/ssv6200_aux.h	17332;"	d
+RG_IDACAI_PGAG13_MSK	include/ssv6200_aux.h	17331;"	d
+RG_IDACAI_PGAG13_SFT	include/ssv6200_aux.h	17333;"	d
+RG_IDACAI_PGAG13_SZ	include/ssv6200_aux.h	17335;"	d
+RG_IDACAI_PGAG14_HI	include/ssv6200_aux.h	17319;"	d
+RG_IDACAI_PGAG14_I_MSK	include/ssv6200_aux.h	17317;"	d
+RG_IDACAI_PGAG14_MSK	include/ssv6200_aux.h	17316;"	d
+RG_IDACAI_PGAG14_SFT	include/ssv6200_aux.h	17318;"	d
+RG_IDACAI_PGAG14_SZ	include/ssv6200_aux.h	17320;"	d
+RG_IDACAI_PGAG15_HI	include/ssv6200_aux.h	17309;"	d
+RG_IDACAI_PGAG15_I_MSK	include/ssv6200_aux.h	17307;"	d
+RG_IDACAI_PGAG15_MSK	include/ssv6200_aux.h	17306;"	d
+RG_IDACAI_PGAG15_SFT	include/ssv6200_aux.h	17308;"	d
+RG_IDACAI_PGAG15_SZ	include/ssv6200_aux.h	17310;"	d
+RG_IDACAI_PGAG1_HI	include/ssv6200_aux.h	17454;"	d
+RG_IDACAI_PGAG1_I_MSK	include/ssv6200_aux.h	17452;"	d
+RG_IDACAI_PGAG1_MSK	include/ssv6200_aux.h	17451;"	d
+RG_IDACAI_PGAG1_SFT	include/ssv6200_aux.h	17453;"	d
+RG_IDACAI_PGAG1_SZ	include/ssv6200_aux.h	17455;"	d
+RG_IDACAI_PGAG2_HI	include/ssv6200_aux.h	17444;"	d
+RG_IDACAI_PGAG2_I_MSK	include/ssv6200_aux.h	17442;"	d
+RG_IDACAI_PGAG2_MSK	include/ssv6200_aux.h	17441;"	d
+RG_IDACAI_PGAG2_SFT	include/ssv6200_aux.h	17443;"	d
+RG_IDACAI_PGAG2_SZ	include/ssv6200_aux.h	17445;"	d
+RG_IDACAI_PGAG3_HI	include/ssv6200_aux.h	17434;"	d
+RG_IDACAI_PGAG3_I_MSK	include/ssv6200_aux.h	17432;"	d
+RG_IDACAI_PGAG3_MSK	include/ssv6200_aux.h	17431;"	d
+RG_IDACAI_PGAG3_SFT	include/ssv6200_aux.h	17433;"	d
+RG_IDACAI_PGAG3_SZ	include/ssv6200_aux.h	17435;"	d
+RG_IDACAI_PGAG4_HI	include/ssv6200_aux.h	17424;"	d
+RG_IDACAI_PGAG4_I_MSK	include/ssv6200_aux.h	17422;"	d
+RG_IDACAI_PGAG4_MSK	include/ssv6200_aux.h	17421;"	d
+RG_IDACAI_PGAG4_SFT	include/ssv6200_aux.h	17423;"	d
+RG_IDACAI_PGAG4_SZ	include/ssv6200_aux.h	17425;"	d
+RG_IDACAI_PGAG5_HI	include/ssv6200_aux.h	17414;"	d
+RG_IDACAI_PGAG5_I_MSK	include/ssv6200_aux.h	17412;"	d
+RG_IDACAI_PGAG5_MSK	include/ssv6200_aux.h	17411;"	d
+RG_IDACAI_PGAG5_SFT	include/ssv6200_aux.h	17413;"	d
+RG_IDACAI_PGAG5_SZ	include/ssv6200_aux.h	17415;"	d
+RG_IDACAI_PGAG6_HI	include/ssv6200_aux.h	17404;"	d
+RG_IDACAI_PGAG6_I_MSK	include/ssv6200_aux.h	17402;"	d
+RG_IDACAI_PGAG6_MSK	include/ssv6200_aux.h	17401;"	d
+RG_IDACAI_PGAG6_SFT	include/ssv6200_aux.h	17403;"	d
+RG_IDACAI_PGAG6_SZ	include/ssv6200_aux.h	17405;"	d
+RG_IDACAI_PGAG7_HI	include/ssv6200_aux.h	17394;"	d
+RG_IDACAI_PGAG7_I_MSK	include/ssv6200_aux.h	17392;"	d
+RG_IDACAI_PGAG7_MSK	include/ssv6200_aux.h	17391;"	d
+RG_IDACAI_PGAG7_SFT	include/ssv6200_aux.h	17393;"	d
+RG_IDACAI_PGAG7_SZ	include/ssv6200_aux.h	17395;"	d
+RG_IDACAI_PGAG8_HI	include/ssv6200_aux.h	17384;"	d
+RG_IDACAI_PGAG8_I_MSK	include/ssv6200_aux.h	17382;"	d
+RG_IDACAI_PGAG8_MSK	include/ssv6200_aux.h	17381;"	d
+RG_IDACAI_PGAG8_SFT	include/ssv6200_aux.h	17383;"	d
+RG_IDACAI_PGAG8_SZ	include/ssv6200_aux.h	17385;"	d
+RG_IDACAI_PGAG9_HI	include/ssv6200_aux.h	17374;"	d
+RG_IDACAI_PGAG9_I_MSK	include/ssv6200_aux.h	17372;"	d
+RG_IDACAI_PGAG9_MSK	include/ssv6200_aux.h	17371;"	d
+RG_IDACAI_PGAG9_SFT	include/ssv6200_aux.h	17373;"	d
+RG_IDACAI_PGAG9_SZ	include/ssv6200_aux.h	17375;"	d
+RG_IDACAI_TZ0_COARSE0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24224;"	d
+RG_IDACAI_TZ0_COARSE0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24222;"	d
+RG_IDACAI_TZ0_COARSE0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24221;"	d
+RG_IDACAI_TZ0_COARSE0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24223;"	d
+RG_IDACAI_TZ0_COARSE0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24225;"	d
+RG_IDACAI_TZ0_COARSE1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24214;"	d
+RG_IDACAI_TZ0_COARSE1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24212;"	d
+RG_IDACAI_TZ0_COARSE1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24211;"	d
+RG_IDACAI_TZ0_COARSE1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24213;"	d
+RG_IDACAI_TZ0_COARSE1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24215;"	d
+RG_IDACAI_TZ0_COARSE2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24204;"	d
+RG_IDACAI_TZ0_COARSE2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24202;"	d
+RG_IDACAI_TZ0_COARSE2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24201;"	d
+RG_IDACAI_TZ0_COARSE2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24203;"	d
+RG_IDACAI_TZ0_COARSE2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24205;"	d
+RG_IDACAI_TZ0_COARSE3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24194;"	d
+RG_IDACAI_TZ0_COARSE3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24192;"	d
+RG_IDACAI_TZ0_COARSE3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24191;"	d
+RG_IDACAI_TZ0_COARSE3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24193;"	d
+RG_IDACAI_TZ0_COARSE3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24195;"	d
+RG_IDACAI_TZ0_COARSE4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24184;"	d
+RG_IDACAI_TZ0_COARSE4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24182;"	d
+RG_IDACAI_TZ0_COARSE4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24181;"	d
+RG_IDACAI_TZ0_COARSE4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24183;"	d
+RG_IDACAI_TZ0_COARSE4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24185;"	d
+RG_IDACAI_TZ1_COARSE0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24274;"	d
+RG_IDACAI_TZ1_COARSE0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24272;"	d
+RG_IDACAI_TZ1_COARSE0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24271;"	d
+RG_IDACAI_TZ1_COARSE0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24273;"	d
+RG_IDACAI_TZ1_COARSE0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24275;"	d
+RG_IDACAI_TZ1_COARSE1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24264;"	d
+RG_IDACAI_TZ1_COARSE1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24262;"	d
+RG_IDACAI_TZ1_COARSE1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24261;"	d
+RG_IDACAI_TZ1_COARSE1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24263;"	d
+RG_IDACAI_TZ1_COARSE1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24265;"	d
+RG_IDACAI_TZ1_COARSE2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24254;"	d
+RG_IDACAI_TZ1_COARSE2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24252;"	d
+RG_IDACAI_TZ1_COARSE2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24251;"	d
+RG_IDACAI_TZ1_COARSE2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24253;"	d
+RG_IDACAI_TZ1_COARSE2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24255;"	d
+RG_IDACAI_TZ1_COARSE3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24244;"	d
+RG_IDACAI_TZ1_COARSE3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24242;"	d
+RG_IDACAI_TZ1_COARSE3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24241;"	d
+RG_IDACAI_TZ1_COARSE3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24243;"	d
+RG_IDACAI_TZ1_COARSE3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24245;"	d
+RG_IDACAI_TZ1_COARSE4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24234;"	d
+RG_IDACAI_TZ1_COARSE4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24232;"	d
+RG_IDACAI_TZ1_COARSE4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24231;"	d
+RG_IDACAI_TZ1_COARSE4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24233;"	d
+RG_IDACAI_TZ1_COARSE4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24235;"	d
+RG_IDACAQ_PGAG0_HI	include/ssv6200_aux.h	17469;"	d
+RG_IDACAQ_PGAG0_I_MSK	include/ssv6200_aux.h	17467;"	d
+RG_IDACAQ_PGAG0_MSK	include/ssv6200_aux.h	17466;"	d
+RG_IDACAQ_PGAG0_SFT	include/ssv6200_aux.h	17468;"	d
+RG_IDACAQ_PGAG0_SZ	include/ssv6200_aux.h	17470;"	d
+RG_IDACAQ_PGAG10_HI	include/ssv6200_aux.h	17369;"	d
+RG_IDACAQ_PGAG10_I_MSK	include/ssv6200_aux.h	17367;"	d
+RG_IDACAQ_PGAG10_MSK	include/ssv6200_aux.h	17366;"	d
+RG_IDACAQ_PGAG10_SFT	include/ssv6200_aux.h	17368;"	d
+RG_IDACAQ_PGAG10_SZ	include/ssv6200_aux.h	17370;"	d
+RG_IDACAQ_PGAG11_HI	include/ssv6200_aux.h	17359;"	d
+RG_IDACAQ_PGAG11_I_MSK	include/ssv6200_aux.h	17357;"	d
+RG_IDACAQ_PGAG11_MSK	include/ssv6200_aux.h	17356;"	d
+RG_IDACAQ_PGAG11_SFT	include/ssv6200_aux.h	17358;"	d
+RG_IDACAQ_PGAG11_SZ	include/ssv6200_aux.h	17360;"	d
+RG_IDACAQ_PGAG12_HI	include/ssv6200_aux.h	17349;"	d
+RG_IDACAQ_PGAG12_I_MSK	include/ssv6200_aux.h	17347;"	d
+RG_IDACAQ_PGAG12_MSK	include/ssv6200_aux.h	17346;"	d
+RG_IDACAQ_PGAG12_SFT	include/ssv6200_aux.h	17348;"	d
+RG_IDACAQ_PGAG12_SZ	include/ssv6200_aux.h	17350;"	d
+RG_IDACAQ_PGAG13_HI	include/ssv6200_aux.h	17339;"	d
+RG_IDACAQ_PGAG13_I_MSK	include/ssv6200_aux.h	17337;"	d
+RG_IDACAQ_PGAG13_MSK	include/ssv6200_aux.h	17336;"	d
+RG_IDACAQ_PGAG13_SFT	include/ssv6200_aux.h	17338;"	d
+RG_IDACAQ_PGAG13_SZ	include/ssv6200_aux.h	17340;"	d
+RG_IDACAQ_PGAG14_HI	include/ssv6200_aux.h	17324;"	d
+RG_IDACAQ_PGAG14_I_MSK	include/ssv6200_aux.h	17322;"	d
+RG_IDACAQ_PGAG14_MSK	include/ssv6200_aux.h	17321;"	d
+RG_IDACAQ_PGAG14_SFT	include/ssv6200_aux.h	17323;"	d
+RG_IDACAQ_PGAG14_SZ	include/ssv6200_aux.h	17325;"	d
+RG_IDACAQ_PGAG15_HI	include/ssv6200_aux.h	17314;"	d
+RG_IDACAQ_PGAG15_I_MSK	include/ssv6200_aux.h	17312;"	d
+RG_IDACAQ_PGAG15_MSK	include/ssv6200_aux.h	17311;"	d
+RG_IDACAQ_PGAG15_SFT	include/ssv6200_aux.h	17313;"	d
+RG_IDACAQ_PGAG15_SZ	include/ssv6200_aux.h	17315;"	d
+RG_IDACAQ_PGAG1_HI	include/ssv6200_aux.h	17459;"	d
+RG_IDACAQ_PGAG1_I_MSK	include/ssv6200_aux.h	17457;"	d
+RG_IDACAQ_PGAG1_MSK	include/ssv6200_aux.h	17456;"	d
+RG_IDACAQ_PGAG1_SFT	include/ssv6200_aux.h	17458;"	d
+RG_IDACAQ_PGAG1_SZ	include/ssv6200_aux.h	17460;"	d
+RG_IDACAQ_PGAG2_HI	include/ssv6200_aux.h	17449;"	d
+RG_IDACAQ_PGAG2_I_MSK	include/ssv6200_aux.h	17447;"	d
+RG_IDACAQ_PGAG2_MSK	include/ssv6200_aux.h	17446;"	d
+RG_IDACAQ_PGAG2_SFT	include/ssv6200_aux.h	17448;"	d
+RG_IDACAQ_PGAG2_SZ	include/ssv6200_aux.h	17450;"	d
+RG_IDACAQ_PGAG3_HI	include/ssv6200_aux.h	17439;"	d
+RG_IDACAQ_PGAG3_I_MSK	include/ssv6200_aux.h	17437;"	d
+RG_IDACAQ_PGAG3_MSK	include/ssv6200_aux.h	17436;"	d
+RG_IDACAQ_PGAG3_SFT	include/ssv6200_aux.h	17438;"	d
+RG_IDACAQ_PGAG3_SZ	include/ssv6200_aux.h	17440;"	d
+RG_IDACAQ_PGAG4_HI	include/ssv6200_aux.h	17429;"	d
+RG_IDACAQ_PGAG4_I_MSK	include/ssv6200_aux.h	17427;"	d
+RG_IDACAQ_PGAG4_MSK	include/ssv6200_aux.h	17426;"	d
+RG_IDACAQ_PGAG4_SFT	include/ssv6200_aux.h	17428;"	d
+RG_IDACAQ_PGAG4_SZ	include/ssv6200_aux.h	17430;"	d
+RG_IDACAQ_PGAG5_HI	include/ssv6200_aux.h	17419;"	d
+RG_IDACAQ_PGAG5_I_MSK	include/ssv6200_aux.h	17417;"	d
+RG_IDACAQ_PGAG5_MSK	include/ssv6200_aux.h	17416;"	d
+RG_IDACAQ_PGAG5_SFT	include/ssv6200_aux.h	17418;"	d
+RG_IDACAQ_PGAG5_SZ	include/ssv6200_aux.h	17420;"	d
+RG_IDACAQ_PGAG6_HI	include/ssv6200_aux.h	17409;"	d
+RG_IDACAQ_PGAG6_I_MSK	include/ssv6200_aux.h	17407;"	d
+RG_IDACAQ_PGAG6_MSK	include/ssv6200_aux.h	17406;"	d
+RG_IDACAQ_PGAG6_SFT	include/ssv6200_aux.h	17408;"	d
+RG_IDACAQ_PGAG6_SZ	include/ssv6200_aux.h	17410;"	d
+RG_IDACAQ_PGAG7_HI	include/ssv6200_aux.h	17399;"	d
+RG_IDACAQ_PGAG7_I_MSK	include/ssv6200_aux.h	17397;"	d
+RG_IDACAQ_PGAG7_MSK	include/ssv6200_aux.h	17396;"	d
+RG_IDACAQ_PGAG7_SFT	include/ssv6200_aux.h	17398;"	d
+RG_IDACAQ_PGAG7_SZ	include/ssv6200_aux.h	17400;"	d
+RG_IDACAQ_PGAG8_HI	include/ssv6200_aux.h	17389;"	d
+RG_IDACAQ_PGAG8_I_MSK	include/ssv6200_aux.h	17387;"	d
+RG_IDACAQ_PGAG8_MSK	include/ssv6200_aux.h	17386;"	d
+RG_IDACAQ_PGAG8_SFT	include/ssv6200_aux.h	17388;"	d
+RG_IDACAQ_PGAG8_SZ	include/ssv6200_aux.h	17390;"	d
+RG_IDACAQ_PGAG9_HI	include/ssv6200_aux.h	17379;"	d
+RG_IDACAQ_PGAG9_I_MSK	include/ssv6200_aux.h	17377;"	d
+RG_IDACAQ_PGAG9_MSK	include/ssv6200_aux.h	17376;"	d
+RG_IDACAQ_PGAG9_SFT	include/ssv6200_aux.h	17378;"	d
+RG_IDACAQ_PGAG9_SZ	include/ssv6200_aux.h	17380;"	d
+RG_IDACAQ_TZ0_COARSE0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24229;"	d
+RG_IDACAQ_TZ0_COARSE0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24227;"	d
+RG_IDACAQ_TZ0_COARSE0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24226;"	d
+RG_IDACAQ_TZ0_COARSE0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24228;"	d
+RG_IDACAQ_TZ0_COARSE0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24230;"	d
+RG_IDACAQ_TZ0_COARSE1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24219;"	d
+RG_IDACAQ_TZ0_COARSE1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24217;"	d
+RG_IDACAQ_TZ0_COARSE1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24216;"	d
+RG_IDACAQ_TZ0_COARSE1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24218;"	d
+RG_IDACAQ_TZ0_COARSE1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24220;"	d
+RG_IDACAQ_TZ0_COARSE2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24209;"	d
+RG_IDACAQ_TZ0_COARSE2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24207;"	d
+RG_IDACAQ_TZ0_COARSE2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24206;"	d
+RG_IDACAQ_TZ0_COARSE2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24208;"	d
+RG_IDACAQ_TZ0_COARSE2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24210;"	d
+RG_IDACAQ_TZ0_COARSE3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24199;"	d
+RG_IDACAQ_TZ0_COARSE3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24197;"	d
+RG_IDACAQ_TZ0_COARSE3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24196;"	d
+RG_IDACAQ_TZ0_COARSE3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24198;"	d
+RG_IDACAQ_TZ0_COARSE3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24200;"	d
+RG_IDACAQ_TZ0_COARSE4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24189;"	d
+RG_IDACAQ_TZ0_COARSE4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24187;"	d
+RG_IDACAQ_TZ0_COARSE4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24186;"	d
+RG_IDACAQ_TZ0_COARSE4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24188;"	d
+RG_IDACAQ_TZ0_COARSE4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24190;"	d
+RG_IDACAQ_TZ1_COARSE0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24279;"	d
+RG_IDACAQ_TZ1_COARSE0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24277;"	d
+RG_IDACAQ_TZ1_COARSE0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24276;"	d
+RG_IDACAQ_TZ1_COARSE0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24278;"	d
+RG_IDACAQ_TZ1_COARSE0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24280;"	d
+RG_IDACAQ_TZ1_COARSE1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24269;"	d
+RG_IDACAQ_TZ1_COARSE1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24267;"	d
+RG_IDACAQ_TZ1_COARSE1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24266;"	d
+RG_IDACAQ_TZ1_COARSE1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24268;"	d
+RG_IDACAQ_TZ1_COARSE1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24270;"	d
+RG_IDACAQ_TZ1_COARSE2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24259;"	d
+RG_IDACAQ_TZ1_COARSE2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24257;"	d
+RG_IDACAQ_TZ1_COARSE2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24256;"	d
+RG_IDACAQ_TZ1_COARSE2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24258;"	d
+RG_IDACAQ_TZ1_COARSE2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24260;"	d
+RG_IDACAQ_TZ1_COARSE3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24249;"	d
+RG_IDACAQ_TZ1_COARSE3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24247;"	d
+RG_IDACAQ_TZ1_COARSE3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24246;"	d
+RG_IDACAQ_TZ1_COARSE3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24248;"	d
+RG_IDACAQ_TZ1_COARSE3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24250;"	d
+RG_IDACAQ_TZ1_COARSE4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24239;"	d
+RG_IDACAQ_TZ1_COARSE4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24237;"	d
+RG_IDACAQ_TZ1_COARSE4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24236;"	d
+RG_IDACAQ_TZ1_COARSE4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24238;"	d
+RG_IDACAQ_TZ1_COARSE4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24240;"	d
+RG_IFS_TIME_EXT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30434;"	d
+RG_IFS_TIME_EXT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30432;"	d
+RG_IFS_TIME_EXT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30431;"	d
+RG_IFS_TIME_EXT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30433;"	d
+RG_IFS_TIME_EXT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30435;"	d
+RG_IFS_TIME_HI	include/ssv6200_aux.h	13219;"	d
+RG_IFS_TIME_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30414;"	d
+RG_IFS_TIME_I_MSK	include/ssv6200_aux.h	13217;"	d
+RG_IFS_TIME_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30412;"	d
+RG_IFS_TIME_MSK	include/ssv6200_aux.h	13216;"	d
+RG_IFS_TIME_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30411;"	d
+RG_IFS_TIME_SFT	include/ssv6200_aux.h	13218;"	d
+RG_IFS_TIME_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30413;"	d
+RG_IFS_TIME_SZ	include/ssv6200_aux.h	13220;"	d
+RG_IFS_TIME_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30415;"	d
+RG_INI_PHASE_HI	include/ssv6200_aux.h	15324;"	d
+RG_INI_PHASE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32724;"	d
+RG_INI_PHASE_I_MSK	include/ssv6200_aux.h	15322;"	d
+RG_INI_PHASE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32722;"	d
+RG_INI_PHASE_MSK	include/ssv6200_aux.h	15321;"	d
+RG_INI_PHASE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32721;"	d
+RG_INI_PHASE_SFT	include/ssv6200_aux.h	15323;"	d
+RG_INI_PHASE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32723;"	d
+RG_INI_PHASE_SZ	include/ssv6200_aux.h	15325;"	d
+RG_INI_PHASE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32725;"	d
+RG_INTG_MU_HI	include/ssv6200_aux.h	15529;"	d
+RG_INTG_MU_I_MSK	include/ssv6200_aux.h	15527;"	d
+RG_INTG_MU_MSK	include/ssv6200_aux.h	15526;"	d
+RG_INTG_MU_SFT	include/ssv6200_aux.h	15528;"	d
+RG_INTG_MU_SZ	include/ssv6200_aux.h	15530;"	d
+RG_INTG_PH_HI	include/ssv6200_aux.h	15519;"	d
+RG_INTG_PH_I_MSK	include/ssv6200_aux.h	15517;"	d
+RG_INTG_PH_MSK	include/ssv6200_aux.h	15516;"	d
+RG_INTG_PH_SFT	include/ssv6200_aux.h	15518;"	d
+RG_INTG_PH_SZ	include/ssv6200_aux.h	15520;"	d
+RG_INTG_PRD_HI	include/ssv6200_aux.h	15524;"	d
+RG_INTG_PRD_I_MSK	include/ssv6200_aux.h	15522;"	d
+RG_INTG_PRD_MSK	include/ssv6200_aux.h	15521;"	d
+RG_INTG_PRD_SFT	include/ssv6200_aux.h	15523;"	d
+RG_INTG_PRD_SZ	include/ssv6200_aux.h	15525;"	d
+RG_INTRUP_RX_11B_CLEAR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31759;"	d
+RG_INTRUP_RX_11B_CLEAR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31757;"	d
+RG_INTRUP_RX_11B_CLEAR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31756;"	d
+RG_INTRUP_RX_11B_CLEAR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31758;"	d
+RG_INTRUP_RX_11B_CLEAR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31760;"	d
+RG_INTRUP_RX_11B_MASK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31764;"	d
+RG_INTRUP_RX_11B_MASK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31762;"	d
+RG_INTRUP_RX_11B_MASK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31761;"	d
+RG_INTRUP_RX_11B_MASK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31763;"	d
+RG_INTRUP_RX_11B_MASK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31765;"	d
+RG_INTRUP_RX_11B_TRIG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31769;"	d
+RG_INTRUP_RX_11B_TRIG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31767;"	d
+RG_INTRUP_RX_11B_TRIG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31766;"	d
+RG_INTRUP_RX_11B_TRIG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31768;"	d
+RG_INTRUP_RX_11B_TRIG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31770;"	d
+RG_INTRUP_RX_11GN_CLEAR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32589;"	d
+RG_INTRUP_RX_11GN_CLEAR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32587;"	d
+RG_INTRUP_RX_11GN_CLEAR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32586;"	d
+RG_INTRUP_RX_11GN_CLEAR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32588;"	d
+RG_INTRUP_RX_11GN_CLEAR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32590;"	d
+RG_INTRUP_RX_11GN_MASK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32594;"	d
+RG_INTRUP_RX_11GN_MASK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32592;"	d
+RG_INTRUP_RX_11GN_MASK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32591;"	d
+RG_INTRUP_RX_11GN_MASK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32593;"	d
+RG_INTRUP_RX_11GN_MASK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32595;"	d
+RG_INTRUP_RX_11GN_TRIG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32599;"	d
+RG_INTRUP_RX_11GN_TRIG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32597;"	d
+RG_INTRUP_RX_11GN_TRIG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32596;"	d
+RG_INTRUP_RX_11GN_TRIG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32598;"	d
+RG_INTRUP_RX_11GN_TRIG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32600;"	d
+RG_INT_PMU_MASK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29774;"	d
+RG_INT_PMU_MASK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29772;"	d
+RG_INT_PMU_MASK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29771;"	d
+RG_INT_PMU_MASK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29773;"	d
+RG_INT_PMU_MASK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29775;"	d
+RG_IOT_ADC_CLKSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24754;"	d
+RG_IOT_ADC_CLKSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24752;"	d
+RG_IOT_ADC_CLKSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24751;"	d
+RG_IOT_ADC_CLKSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24753;"	d
+RG_IOT_ADC_CLKSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24755;"	d
+RG_IOT_ADC_CLK_DIV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24789;"	d
+RG_IOT_ADC_CLK_DIV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24787;"	d
+RG_IOT_ADC_CLK_DIV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24786;"	d
+RG_IOT_ADC_CLK_DIV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24788;"	d
+RG_IOT_ADC_CLK_DIV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24790;"	d
+RG_IOT_ADC_CLK_SH_DUTY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24794;"	d
+RG_IOT_ADC_CLK_SH_DUTY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24792;"	d
+RG_IOT_ADC_CLK_SH_DUTY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24791;"	d
+RG_IOT_ADC_CLK_SH_DUTY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24793;"	d
+RG_IOT_ADC_CLK_SH_DUTY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24795;"	d
+RG_IOT_ADC_CLOAD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24784;"	d
+RG_IOT_ADC_CLOAD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24782;"	d
+RG_IOT_ADC_CLOAD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24781;"	d
+RG_IOT_ADC_CLOAD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24783;"	d
+RG_IOT_ADC_CLOAD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24785;"	d
+RG_IOT_ADC_DNLEN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24759;"	d
+RG_IOT_ADC_DNLEN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24757;"	d
+RG_IOT_ADC_DNLEN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24756;"	d
+RG_IOT_ADC_DNLEN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24758;"	d
+RG_IOT_ADC_DNLEN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24760;"	d
+RG_IOT_ADC_EDGE_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27829;"	d
+RG_IOT_ADC_EDGE_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27827;"	d
+RG_IOT_ADC_EDGE_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27826;"	d
+RG_IOT_ADC_EDGE_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27828;"	d
+RG_IOT_ADC_EDGE_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27830;"	d
+RG_IOT_ADC_ICMP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24774;"	d
+RG_IOT_ADC_ICMP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24772;"	d
+RG_IOT_ADC_ICMP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24771;"	d
+RG_IOT_ADC_ICMP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24773;"	d
+RG_IOT_ADC_ICMP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24775;"	d
+RG_IOT_ADC_METAEN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24764;"	d
+RG_IOT_ADC_METAEN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24762;"	d
+RG_IOT_ADC_METAEN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24761;"	d
+RG_IOT_ADC_METAEN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24763;"	d
+RG_IOT_ADC_METAEN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24765;"	d
+RG_IOT_ADC_SIGN_SWAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27824;"	d
+RG_IOT_ADC_SIGN_SWAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27822;"	d
+RG_IOT_ADC_SIGN_SWAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27821;"	d
+RG_IOT_ADC_SIGN_SWAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27823;"	d
+RG_IOT_ADC_SIGN_SWAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27825;"	d
+RG_IOT_ADC_TFLAG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24769;"	d
+RG_IOT_ADC_TFLAG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24767;"	d
+RG_IOT_ADC_TFLAG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24766;"	d
+RG_IOT_ADC_TFLAG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24768;"	d
+RG_IOT_ADC_TFLAG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24770;"	d
+RG_IOT_ADC_VCMI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24779;"	d
+RG_IOT_ADC_VCMI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24777;"	d
+RG_IOT_ADC_VCMI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24776;"	d
+RG_IOT_ADC_VCMI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24778;"	d
+RG_IOT_ADC_VCMI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24780;"	d
+RG_IOT_ADC_VSEN_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24799;"	d
+RG_IOT_ADC_VSEN_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24797;"	d
+RG_IOT_ADC_VSEN_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24796;"	d
+RG_IOT_ADC_VSEN_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24798;"	d
+RG_IOT_ADC_VSEN_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24800;"	d
+RG_IQCAL_ALPHA_ESTM_EN_HI	include/ssv6200_aux.h	15554;"	d
+RG_IQCAL_ALPHA_ESTM_EN_I_MSK	include/ssv6200_aux.h	15552;"	d
+RG_IQCAL_ALPHA_ESTM_EN_MSK	include/ssv6200_aux.h	15551;"	d
+RG_IQCAL_ALPHA_ESTM_EN_SFT	include/ssv6200_aux.h	15553;"	d
+RG_IQCAL_ALPHA_ESTM_EN_SZ	include/ssv6200_aux.h	15555;"	d
+RG_IQCAL_BP_ACI_HI	include/ssv6200_aux.h	15734;"	d
+RG_IQCAL_BP_ACI_I_MSK	include/ssv6200_aux.h	15732;"	d
+RG_IQCAL_BP_ACI_MSK	include/ssv6200_aux.h	15731;"	d
+RG_IQCAL_BP_ACI_SFT	include/ssv6200_aux.h	15733;"	d
+RG_IQCAL_BP_ACI_SZ	include/ssv6200_aux.h	15735;"	d
+RG_IQCAL_DC_EN_HI	include/ssv6200_aux.h	15559;"	d
+RG_IQCAL_DC_EN_I_MSK	include/ssv6200_aux.h	15557;"	d
+RG_IQCAL_DC_EN_MSK	include/ssv6200_aux.h	15556;"	d
+RG_IQCAL_DC_EN_SFT	include/ssv6200_aux.h	15558;"	d
+RG_IQCAL_DC_EN_SZ	include/ssv6200_aux.h	15560;"	d
+RG_IQCAL_IQCOL_EN_HI	include/ssv6200_aux.h	15549;"	d
+RG_IQCAL_IQCOL_EN_I_MSK	include/ssv6200_aux.h	15547;"	d
+RG_IQCAL_IQCOL_EN_MSK	include/ssv6200_aux.h	15546;"	d
+RG_IQCAL_IQCOL_EN_SFT	include/ssv6200_aux.h	15548;"	d
+RG_IQCAL_IQCOL_EN_SZ	include/ssv6200_aux.h	15550;"	d
+RG_IQCAL_MULT_OP0_HI	include/ssv6200_aux.h	15584;"	d
+RG_IQCAL_MULT_OP0_I_MSK	include/ssv6200_aux.h	15582;"	d
+RG_IQCAL_MULT_OP0_MSK	include/ssv6200_aux.h	15581;"	d
+RG_IQCAL_MULT_OP0_SFT	include/ssv6200_aux.h	15583;"	d
+RG_IQCAL_MULT_OP0_SZ	include/ssv6200_aux.h	15585;"	d
+RG_IQCAL_MULT_OP1_HI	include/ssv6200_aux.h	15589;"	d
+RG_IQCAL_MULT_OP1_I_MSK	include/ssv6200_aux.h	15587;"	d
+RG_IQCAL_MULT_OP1_MSK	include/ssv6200_aux.h	15586;"	d
+RG_IQCAL_MULT_OP1_SFT	include/ssv6200_aux.h	15588;"	d
+RG_IQCAL_MULT_OP1_SZ	include/ssv6200_aux.h	15590;"	d
+RG_IQCAL_SPRM_EN_HI	include/ssv6200_aux.h	15539;"	d
+RG_IQCAL_SPRM_EN_I_MSK	include/ssv6200_aux.h	15537;"	d
+RG_IQCAL_SPRM_EN_MSK	include/ssv6200_aux.h	15536;"	d
+RG_IQCAL_SPRM_EN_SFT	include/ssv6200_aux.h	15538;"	d
+RG_IQCAL_SPRM_EN_SZ	include/ssv6200_aux.h	15540;"	d
+RG_IQCAL_SPRM_FREQ_HI	include/ssv6200_aux.h	15544;"	d
+RG_IQCAL_SPRM_FREQ_I_MSK	include/ssv6200_aux.h	15542;"	d
+RG_IQCAL_SPRM_FREQ_MSK	include/ssv6200_aux.h	15541;"	d
+RG_IQCAL_SPRM_FREQ_SFT	include/ssv6200_aux.h	15543;"	d
+RG_IQCAL_SPRM_FREQ_SZ	include/ssv6200_aux.h	15545;"	d
+RG_IQCAL_SPRM_SELQ_HI	include/ssv6200_aux.h	15534;"	d
+RG_IQCAL_SPRM_SELQ_I_MSK	include/ssv6200_aux.h	15532;"	d
+RG_IQCAL_SPRM_SELQ_MSK	include/ssv6200_aux.h	15531;"	d
+RG_IQCAL_SPRM_SELQ_SFT	include/ssv6200_aux.h	15533;"	d
+RG_IQCAL_SPRM_SELQ_SZ	include/ssv6200_aux.h	15535;"	d
+RG_IQC_FFT_EN_HI	include/ssv6200_aux.h	13804;"	d
+RG_IQC_FFT_EN_I_MSK	include/ssv6200_aux.h	13802;"	d
+RG_IQC_FFT_EN_MSK	include/ssv6200_aux.h	13801;"	d
+RG_IQC_FFT_EN_SFT	include/ssv6200_aux.h	13803;"	d
+RG_IQC_FFT_EN_SZ	include/ssv6200_aux.h	13805;"	d
+RG_IQ_DC_BYP_HI	include/ssv6200_aux.h	13269;"	d
+RG_IQ_DC_BYP_I_MSK	include/ssv6200_aux.h	13267;"	d
+RG_IQ_DC_BYP_MSK	include/ssv6200_aux.h	13266;"	d
+RG_IQ_DC_BYP_SFT	include/ssv6200_aux.h	13268;"	d
+RG_IQ_DC_BYP_SZ	include/ssv6200_aux.h	13270;"	d
+RG_IQ_DC_LEAKY_FACTOR_HI	include/ssv6200_aux.h	13274;"	d
+RG_IQ_DC_LEAKY_FACTOR_I_MSK	include/ssv6200_aux.h	13272;"	d
+RG_IQ_DC_LEAKY_FACTOR_MSK	include/ssv6200_aux.h	13271;"	d
+RG_IQ_DC_LEAKY_FACTOR_SFT	include/ssv6200_aux.h	13273;"	d
+RG_IQ_DC_LEAKY_FACTOR_SZ	include/ssv6200_aux.h	13275;"	d
+RG_IQ_SWAP_BB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30209;"	d
+RG_IQ_SWAP_BB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30207;"	d
+RG_IQ_SWAP_BB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30206;"	d
+RG_IQ_SWAP_BB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30208;"	d
+RG_IQ_SWAP_BB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30210;"	d
+RG_IQ_SWAP_HI	include/ssv6200_aux.h	12999;"	d
+RG_IQ_SWAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27229;"	d
+RG_IQ_SWAP_I_MSK	include/ssv6200_aux.h	12997;"	d
+RG_IQ_SWAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27227;"	d
+RG_IQ_SWAP_MSK	include/ssv6200_aux.h	12996;"	d
+RG_IQ_SWAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27226;"	d
+RG_IQ_SWAP_SFT	include/ssv6200_aux.h	12998;"	d
+RG_IQ_SWAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27228;"	d
+RG_IQ_SWAP_SZ	include/ssv6200_aux.h	13000;"	d
+RG_IQ_SWAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27230;"	d
+RG_I_INV_BB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30219;"	d
+RG_I_INV_BB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30217;"	d
+RG_I_INV_BB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30216;"	d
+RG_I_INV_BB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30218;"	d
+RG_I_INV_BB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30220;"	d
+RG_I_INV_HI	include/ssv6200_aux.h	13009;"	d
+RG_I_INV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27224;"	d
+RG_I_INV_I_MSK	include/ssv6200_aux.h	13007;"	d
+RG_I_INV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27222;"	d
+RG_I_INV_MSK	include/ssv6200_aux.h	13006;"	d
+RG_I_INV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27221;"	d
+RG_I_INV_SFT	include/ssv6200_aux.h	13008;"	d
+RG_I_INV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27223;"	d
+RG_I_INV_SZ	include/ssv6200_aux.h	13010;"	d
+RG_I_INV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27225;"	d
+RG_LBK_ANA_PATH_HI	include/ssv6200_aux.h	13019;"	d
+RG_LBK_ANA_PATH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30229;"	d
+RG_LBK_ANA_PATH_I_MSK	include/ssv6200_aux.h	13017;"	d
+RG_LBK_ANA_PATH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30227;"	d
+RG_LBK_ANA_PATH_MSK	include/ssv6200_aux.h	13016;"	d
+RG_LBK_ANA_PATH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30226;"	d
+RG_LBK_ANA_PATH_SFT	include/ssv6200_aux.h	13018;"	d
+RG_LBK_ANA_PATH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30228;"	d
+RG_LBK_ANA_PATH_SZ	include/ssv6200_aux.h	13020;"	d
+RG_LBK_ANA_PATH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30230;"	d
+RG_LBK_DIG_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30234;"	d
+RG_LBK_DIG_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30232;"	d
+RG_LBK_DIG_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30231;"	d
+RG_LBK_DIG_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30233;"	d
+RG_LBK_DIG_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30235;"	d
+RG_LDO_5G_CP_FC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25844;"	d
+RG_LDO_5G_CP_FC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25842;"	d
+RG_LDO_5G_CP_FC_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25839;"	d
+RG_LDO_5G_CP_FC_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25837;"	d
+RG_LDO_5G_CP_FC_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25836;"	d
+RG_LDO_5G_CP_FC_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25838;"	d
+RG_LDO_5G_CP_FC_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25840;"	d
+RG_LDO_5G_CP_FC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25841;"	d
+RG_LDO_5G_CP_FC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25843;"	d
+RG_LDO_5G_CP_FC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25845;"	d
+RG_LDO_5G_DIV_FC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25854;"	d
+RG_LDO_5G_DIV_FC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25852;"	d
+RG_LDO_5G_DIV_FC_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25849;"	d
+RG_LDO_5G_DIV_FC_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25847;"	d
+RG_LDO_5G_DIV_FC_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25846;"	d
+RG_LDO_5G_DIV_FC_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25848;"	d
+RG_LDO_5G_DIV_FC_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25850;"	d
+RG_LDO_5G_DIV_FC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25851;"	d
+RG_LDO_5G_DIV_FC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25853;"	d
+RG_LDO_5G_DIV_FC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25855;"	d
+RG_LDO_5G_LO_FC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25864;"	d
+RG_LDO_5G_LO_FC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25862;"	d
+RG_LDO_5G_LO_FC_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25859;"	d
+RG_LDO_5G_LO_FC_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25857;"	d
+RG_LDO_5G_LO_FC_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25856;"	d
+RG_LDO_5G_LO_FC_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25858;"	d
+RG_LDO_5G_LO_FC_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25860;"	d
+RG_LDO_5G_LO_FC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25861;"	d
+RG_LDO_5G_LO_FC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25863;"	d
+RG_LDO_5G_LO_FC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25865;"	d
+RG_LDO_5G_VCO_FC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25874;"	d
+RG_LDO_5G_VCO_FC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25872;"	d
+RG_LDO_5G_VCO_FC_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25869;"	d
+RG_LDO_5G_VCO_FC_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25867;"	d
+RG_LDO_5G_VCO_FC_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25866;"	d
+RG_LDO_5G_VCO_FC_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25868;"	d
+RG_LDO_5G_VCO_FC_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25870;"	d
+RG_LDO_5G_VCO_FC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25871;"	d
+RG_LDO_5G_VCO_FC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25873;"	d
+RG_LDO_5G_VCO_FC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25875;"	d
+RG_LDO_5G_VCO_RCF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25879;"	d
+RG_LDO_5G_VCO_RCF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25877;"	d
+RG_LDO_5G_VCO_RCF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25876;"	d
+RG_LDO_5G_VCO_RCF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25878;"	d
+RG_LDO_5G_VCO_RCF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25880;"	d
+RG_LDO_CP_FC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23299;"	d
+RG_LDO_CP_FC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23297;"	d
+RG_LDO_CP_FC_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23294;"	d
+RG_LDO_CP_FC_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23292;"	d
+RG_LDO_CP_FC_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23291;"	d
+RG_LDO_CP_FC_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23293;"	d
+RG_LDO_CP_FC_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23295;"	d
+RG_LDO_CP_FC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23296;"	d
+RG_LDO_CP_FC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23298;"	d
+RG_LDO_CP_FC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23300;"	d
+RG_LDO_DIV_FC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23309;"	d
+RG_LDO_DIV_FC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23307;"	d
+RG_LDO_DIV_FC_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23304;"	d
+RG_LDO_DIV_FC_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23302;"	d
+RG_LDO_DIV_FC_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23301;"	d
+RG_LDO_DIV_FC_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23303;"	d
+RG_LDO_DIV_FC_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23305;"	d
+RG_LDO_DIV_FC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23306;"	d
+RG_LDO_DIV_FC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23308;"	d
+RG_LDO_DIV_FC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23310;"	d
+RG_LDO_LEVEL_ABB_HI	include/ssv6200_aux.h	16289;"	d
+RG_LDO_LEVEL_ABB_I_MSK	include/ssv6200_aux.h	16287;"	d
+RG_LDO_LEVEL_ABB_MSK	include/ssv6200_aux.h	16286;"	d
+RG_LDO_LEVEL_ABB_SFT	include/ssv6200_aux.h	16288;"	d
+RG_LDO_LEVEL_ABB_SZ	include/ssv6200_aux.h	16290;"	d
+RG_LDO_LEVEL_AFE_HI	include/ssv6200_aux.h	16294;"	d
+RG_LDO_LEVEL_AFE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21954;"	d
+RG_LDO_LEVEL_AFE_I_MSK	include/ssv6200_aux.h	16292;"	d
+RG_LDO_LEVEL_AFE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21952;"	d
+RG_LDO_LEVEL_AFE_MSK	include/ssv6200_aux.h	16291;"	d
+RG_LDO_LEVEL_AFE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21951;"	d
+RG_LDO_LEVEL_AFE_SFT	include/ssv6200_aux.h	16293;"	d
+RG_LDO_LEVEL_AFE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21953;"	d
+RG_LDO_LEVEL_AFE_SZ	include/ssv6200_aux.h	16295;"	d
+RG_LDO_LEVEL_AFE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21955;"	d
+RG_LDO_LEVEL_EFUSE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29649;"	d
+RG_LDO_LEVEL_EFUSE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29647;"	d
+RG_LDO_LEVEL_EFUSE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29646;"	d
+RG_LDO_LEVEL_EFUSE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29648;"	d
+RG_LDO_LEVEL_EFUSE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29650;"	d
+RG_LDO_LEVEL_RX_FE_HI	include/ssv6200_aux.h	16284;"	d
+RG_LDO_LEVEL_RX_FE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21944;"	d
+RG_LDO_LEVEL_RX_FE_I_MSK	include/ssv6200_aux.h	16282;"	d
+RG_LDO_LEVEL_RX_FE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21942;"	d
+RG_LDO_LEVEL_RX_FE_MSK	include/ssv6200_aux.h	16281;"	d
+RG_LDO_LEVEL_RX_FE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21941;"	d
+RG_LDO_LEVEL_RX_FE_SFT	include/ssv6200_aux.h	16283;"	d
+RG_LDO_LEVEL_RX_FE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21943;"	d
+RG_LDO_LEVEL_RX_FE_SZ	include/ssv6200_aux.h	16285;"	d
+RG_LDO_LEVEL_RX_FE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21945;"	d
+RG_LDO_LO_FC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23319;"	d
+RG_LDO_LO_FC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23317;"	d
+RG_LDO_LO_FC_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23314;"	d
+RG_LDO_LO_FC_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23312;"	d
+RG_LDO_LO_FC_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23311;"	d
+RG_LDO_LO_FC_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23313;"	d
+RG_LDO_LO_FC_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23315;"	d
+RG_LDO_LO_FC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23316;"	d
+RG_LDO_LO_FC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23318;"	d
+RG_LDO_LO_FC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23320;"	d
+RG_LDO_VCO_FC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23329;"	d
+RG_LDO_VCO_FC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23327;"	d
+RG_LDO_VCO_FC_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23324;"	d
+RG_LDO_VCO_FC_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23322;"	d
+RG_LDO_VCO_FC_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23321;"	d
+RG_LDO_VCO_FC_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23323;"	d
+RG_LDO_VCO_FC_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23325;"	d
+RG_LDO_VCO_FC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23326;"	d
+RG_LDO_VCO_FC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23328;"	d
+RG_LDO_VCO_FC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23330;"	d
+RG_LDO_VCO_RCF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23334;"	d
+RG_LDO_VCO_RCF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23332;"	d
+RG_LDO_VCO_RCF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23331;"	d
+RG_LDO_VCO_RCF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23333;"	d
+RG_LDO_VCO_RCF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23335;"	d
+RG_LENGTH_HI	include/ssv6200_aux.h	13134;"	d
+RG_LENGTH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30324;"	d
+RG_LENGTH_I_MSK	include/ssv6200_aux.h	13132;"	d
+RG_LENGTH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30322;"	d
+RG_LENGTH_MSK	include/ssv6200_aux.h	13131;"	d
+RG_LENGTH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30321;"	d
+RG_LENGTH_SFT	include/ssv6200_aux.h	13133;"	d
+RG_LENGTH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30323;"	d
+RG_LENGTH_SZ	include/ssv6200_aux.h	13135;"	d
+RG_LENGTH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30325;"	d
+RG_LG_PGA_SAT_PGA_GAIN_HI	include/ssv6200_aux.h	13369;"	d
+RG_LG_PGA_SAT_PGA_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30559;"	d
+RG_LG_PGA_SAT_PGA_GAIN_I_MSK	include/ssv6200_aux.h	13367;"	d
+RG_LG_PGA_SAT_PGA_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30557;"	d
+RG_LG_PGA_SAT_PGA_GAIN_MSK	include/ssv6200_aux.h	13366;"	d
+RG_LG_PGA_SAT_PGA_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30556;"	d
+RG_LG_PGA_SAT_PGA_GAIN_SFT	include/ssv6200_aux.h	13368;"	d
+RG_LG_PGA_SAT_PGA_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30558;"	d
+RG_LG_PGA_SAT_PGA_GAIN_SZ	include/ssv6200_aux.h	13370;"	d
+RG_LG_PGA_SAT_PGA_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30560;"	d
+RG_LG_PGA_UND_PGA_GAIN_HI	include/ssv6200_aux.h	13364;"	d
+RG_LG_PGA_UND_PGA_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30554;"	d
+RG_LG_PGA_UND_PGA_GAIN_I_MSK	include/ssv6200_aux.h	13362;"	d
+RG_LG_PGA_UND_PGA_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30552;"	d
+RG_LG_PGA_UND_PGA_GAIN_MSK	include/ssv6200_aux.h	13361;"	d
+RG_LG_PGA_UND_PGA_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30551;"	d
+RG_LG_PGA_UND_PGA_GAIN_SFT	include/ssv6200_aux.h	13363;"	d
+RG_LG_PGA_UND_PGA_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30553;"	d
+RG_LG_PGA_UND_PGA_GAIN_SZ	include/ssv6200_aux.h	13365;"	d
+RG_LG_PGA_UND_PGA_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30555;"	d
+RG_LG_RF_SAT_PGA_GAIN_HI	include/ssv6200_aux.h	13374;"	d
+RG_LG_RF_SAT_PGA_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30564;"	d
+RG_LG_RF_SAT_PGA_GAIN_I_MSK	include/ssv6200_aux.h	13372;"	d
+RG_LG_RF_SAT_PGA_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30562;"	d
+RG_LG_RF_SAT_PGA_GAIN_MSK	include/ssv6200_aux.h	13371;"	d
+RG_LG_RF_SAT_PGA_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30561;"	d
+RG_LG_RF_SAT_PGA_GAIN_SFT	include/ssv6200_aux.h	13373;"	d
+RG_LG_RF_SAT_PGA_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30563;"	d
+RG_LG_RF_SAT_PGA_GAIN_SZ	include/ssv6200_aux.h	13375;"	d
+RG_LG_RF_SAT_PGA_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30565;"	d
+RG_LOAD_RFTABLE_RDY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29609;"	d
+RG_LOAD_RFTABLE_RDY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29607;"	d
+RG_LOAD_RFTABLE_RDY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29606;"	d
+RG_LOAD_RFTABLE_RDY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29608;"	d
+RG_LOAD_RFTABLE_RDY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29610;"	d
+RG_LO_UP_CH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27169;"	d
+RG_LO_UP_CH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27167;"	d
+RG_LO_UP_CH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27166;"	d
+RG_LO_UP_CH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27168;"	d
+RG_LO_UP_CH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27170;"	d
+RG_LPBK_RX_EN_HI	include/ssv6200_aux.h	8779;"	d
+RG_LPBK_RX_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8534;"	d
+RG_LPBK_RX_EN_I_MSK	include/ssv6200_aux.h	8777;"	d
+RG_LPBK_RX_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8532;"	d
+RG_LPBK_RX_EN_MSK	include/ssv6200_aux.h	8776;"	d
+RG_LPBK_RX_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8531;"	d
+RG_LPBK_RX_EN_SFT	include/ssv6200_aux.h	8778;"	d
+RG_LPBK_RX_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8533;"	d
+RG_LPBK_RX_EN_SZ	include/ssv6200_aux.h	8780;"	d
+RG_LPBK_RX_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8535;"	d
+RG_LPF4_00_HI	include/ssv6200_aux.h	14079;"	d
+RG_LPF4_00_I_MSK	include/ssv6200_aux.h	14077;"	d
+RG_LPF4_00_MSK	include/ssv6200_aux.h	14076;"	d
+RG_LPF4_00_SFT	include/ssv6200_aux.h	14078;"	d
+RG_LPF4_00_SZ	include/ssv6200_aux.h	14080;"	d
+RG_LPF4_01_HI	include/ssv6200_aux.h	14084;"	d
+RG_LPF4_01_I_MSK	include/ssv6200_aux.h	14082;"	d
+RG_LPF4_01_MSK	include/ssv6200_aux.h	14081;"	d
+RG_LPF4_01_SFT	include/ssv6200_aux.h	14083;"	d
+RG_LPF4_01_SZ	include/ssv6200_aux.h	14085;"	d
+RG_LPF4_02_HI	include/ssv6200_aux.h	14089;"	d
+RG_LPF4_02_I_MSK	include/ssv6200_aux.h	14087;"	d
+RG_LPF4_02_MSK	include/ssv6200_aux.h	14086;"	d
+RG_LPF4_02_SFT	include/ssv6200_aux.h	14088;"	d
+RG_LPF4_02_SZ	include/ssv6200_aux.h	14090;"	d
+RG_LPF4_03_HI	include/ssv6200_aux.h	14094;"	d
+RG_LPF4_03_I_MSK	include/ssv6200_aux.h	14092;"	d
+RG_LPF4_03_MSK	include/ssv6200_aux.h	14091;"	d
+RG_LPF4_03_SFT	include/ssv6200_aux.h	14093;"	d
+RG_LPF4_03_SZ	include/ssv6200_aux.h	14095;"	d
+RG_LPF4_04_HI	include/ssv6200_aux.h	14099;"	d
+RG_LPF4_04_I_MSK	include/ssv6200_aux.h	14097;"	d
+RG_LPF4_04_MSK	include/ssv6200_aux.h	14096;"	d
+RG_LPF4_04_SFT	include/ssv6200_aux.h	14098;"	d
+RG_LPF4_04_SZ	include/ssv6200_aux.h	14100;"	d
+RG_LPF4_05_HI	include/ssv6200_aux.h	14104;"	d
+RG_LPF4_05_I_MSK	include/ssv6200_aux.h	14102;"	d
+RG_LPF4_05_MSK	include/ssv6200_aux.h	14101;"	d
+RG_LPF4_05_SFT	include/ssv6200_aux.h	14103;"	d
+RG_LPF4_05_SZ	include/ssv6200_aux.h	14105;"	d
+RG_LPF4_06_HI	include/ssv6200_aux.h	14109;"	d
+RG_LPF4_06_I_MSK	include/ssv6200_aux.h	14107;"	d
+RG_LPF4_06_MSK	include/ssv6200_aux.h	14106;"	d
+RG_LPF4_06_SFT	include/ssv6200_aux.h	14108;"	d
+RG_LPF4_06_SZ	include/ssv6200_aux.h	14110;"	d
+RG_LPF4_07_HI	include/ssv6200_aux.h	14114;"	d
+RG_LPF4_07_I_MSK	include/ssv6200_aux.h	14112;"	d
+RG_LPF4_07_MSK	include/ssv6200_aux.h	14111;"	d
+RG_LPF4_07_SFT	include/ssv6200_aux.h	14113;"	d
+RG_LPF4_07_SZ	include/ssv6200_aux.h	14115;"	d
+RG_LPF4_08_HI	include/ssv6200_aux.h	14119;"	d
+RG_LPF4_08_I_MSK	include/ssv6200_aux.h	14117;"	d
+RG_LPF4_08_MSK	include/ssv6200_aux.h	14116;"	d
+RG_LPF4_08_SFT	include/ssv6200_aux.h	14118;"	d
+RG_LPF4_08_SZ	include/ssv6200_aux.h	14120;"	d
+RG_LPF4_09_HI	include/ssv6200_aux.h	14124;"	d
+RG_LPF4_09_I_MSK	include/ssv6200_aux.h	14122;"	d
+RG_LPF4_09_MSK	include/ssv6200_aux.h	14121;"	d
+RG_LPF4_09_SFT	include/ssv6200_aux.h	14123;"	d
+RG_LPF4_09_SZ	include/ssv6200_aux.h	14125;"	d
+RG_LPF4_10_HI	include/ssv6200_aux.h	14129;"	d
+RG_LPF4_10_I_MSK	include/ssv6200_aux.h	14127;"	d
+RG_LPF4_10_MSK	include/ssv6200_aux.h	14126;"	d
+RG_LPF4_10_SFT	include/ssv6200_aux.h	14128;"	d
+RG_LPF4_10_SZ	include/ssv6200_aux.h	14130;"	d
+RG_LPF4_11_HI	include/ssv6200_aux.h	14134;"	d
+RG_LPF4_11_I_MSK	include/ssv6200_aux.h	14132;"	d
+RG_LPF4_11_MSK	include/ssv6200_aux.h	14131;"	d
+RG_LPF4_11_SFT	include/ssv6200_aux.h	14133;"	d
+RG_LPF4_11_SZ	include/ssv6200_aux.h	14135;"	d
+RG_LPF4_12_HI	include/ssv6200_aux.h	14139;"	d
+RG_LPF4_12_I_MSK	include/ssv6200_aux.h	14137;"	d
+RG_LPF4_12_MSK	include/ssv6200_aux.h	14136;"	d
+RG_LPF4_12_SFT	include/ssv6200_aux.h	14138;"	d
+RG_LPF4_12_SZ	include/ssv6200_aux.h	14140;"	d
+RG_LPF4_13_HI	include/ssv6200_aux.h	14144;"	d
+RG_LPF4_13_I_MSK	include/ssv6200_aux.h	14142;"	d
+RG_LPF4_13_MSK	include/ssv6200_aux.h	14141;"	d
+RG_LPF4_13_SFT	include/ssv6200_aux.h	14143;"	d
+RG_LPF4_13_SZ	include/ssv6200_aux.h	14145;"	d
+RG_LPF4_14_HI	include/ssv6200_aux.h	14149;"	d
+RG_LPF4_14_I_MSK	include/ssv6200_aux.h	14147;"	d
+RG_LPF4_14_MSK	include/ssv6200_aux.h	14146;"	d
+RG_LPF4_14_SFT	include/ssv6200_aux.h	14148;"	d
+RG_LPF4_14_SZ	include/ssv6200_aux.h	14150;"	d
+RG_LPF4_15_HI	include/ssv6200_aux.h	14154;"	d
+RG_LPF4_15_I_MSK	include/ssv6200_aux.h	14152;"	d
+RG_LPF4_15_MSK	include/ssv6200_aux.h	14151;"	d
+RG_LPF4_15_SFT	include/ssv6200_aux.h	14153;"	d
+RG_LPF4_15_SZ	include/ssv6200_aux.h	14155;"	d
+RG_LPF4_16_HI	include/ssv6200_aux.h	14159;"	d
+RG_LPF4_16_I_MSK	include/ssv6200_aux.h	14157;"	d
+RG_LPF4_16_MSK	include/ssv6200_aux.h	14156;"	d
+RG_LPF4_16_SFT	include/ssv6200_aux.h	14158;"	d
+RG_LPF4_16_SZ	include/ssv6200_aux.h	14160;"	d
+RG_LPF4_17_HI	include/ssv6200_aux.h	14164;"	d
+RG_LPF4_17_I_MSK	include/ssv6200_aux.h	14162;"	d
+RG_LPF4_17_MSK	include/ssv6200_aux.h	14161;"	d
+RG_LPF4_17_SFT	include/ssv6200_aux.h	14163;"	d
+RG_LPF4_17_SZ	include/ssv6200_aux.h	14165;"	d
+RG_LPF4_18_HI	include/ssv6200_aux.h	14169;"	d
+RG_LPF4_18_I_MSK	include/ssv6200_aux.h	14167;"	d
+RG_LPF4_18_MSK	include/ssv6200_aux.h	14166;"	d
+RG_LPF4_18_SFT	include/ssv6200_aux.h	14168;"	d
+RG_LPF4_18_SZ	include/ssv6200_aux.h	14170;"	d
+RG_LPF4_19_HI	include/ssv6200_aux.h	14174;"	d
+RG_LPF4_19_I_MSK	include/ssv6200_aux.h	14172;"	d
+RG_LPF4_19_MSK	include/ssv6200_aux.h	14171;"	d
+RG_LPF4_19_SFT	include/ssv6200_aux.h	14173;"	d
+RG_LPF4_19_SZ	include/ssv6200_aux.h	14175;"	d
+RG_LPF4_20_HI	include/ssv6200_aux.h	14179;"	d
+RG_LPF4_20_I_MSK	include/ssv6200_aux.h	14177;"	d
+RG_LPF4_20_MSK	include/ssv6200_aux.h	14176;"	d
+RG_LPF4_20_SFT	include/ssv6200_aux.h	14178;"	d
+RG_LPF4_20_SZ	include/ssv6200_aux.h	14180;"	d
+RG_LPF4_21_HI	include/ssv6200_aux.h	14184;"	d
+RG_LPF4_21_I_MSK	include/ssv6200_aux.h	14182;"	d
+RG_LPF4_21_MSK	include/ssv6200_aux.h	14181;"	d
+RG_LPF4_21_SFT	include/ssv6200_aux.h	14183;"	d
+RG_LPF4_21_SZ	include/ssv6200_aux.h	14185;"	d
+RG_LPF4_22_HI	include/ssv6200_aux.h	14189;"	d
+RG_LPF4_22_I_MSK	include/ssv6200_aux.h	14187;"	d
+RG_LPF4_22_MSK	include/ssv6200_aux.h	14186;"	d
+RG_LPF4_22_SFT	include/ssv6200_aux.h	14188;"	d
+RG_LPF4_22_SZ	include/ssv6200_aux.h	14190;"	d
+RG_LPF4_23_HI	include/ssv6200_aux.h	14194;"	d
+RG_LPF4_23_I_MSK	include/ssv6200_aux.h	14192;"	d
+RG_LPF4_23_MSK	include/ssv6200_aux.h	14191;"	d
+RG_LPF4_23_SFT	include/ssv6200_aux.h	14193;"	d
+RG_LPF4_23_SZ	include/ssv6200_aux.h	14195;"	d
+RG_LPF4_24_HI	include/ssv6200_aux.h	14199;"	d
+RG_LPF4_24_I_MSK	include/ssv6200_aux.h	14197;"	d
+RG_LPF4_24_MSK	include/ssv6200_aux.h	14196;"	d
+RG_LPF4_24_SFT	include/ssv6200_aux.h	14198;"	d
+RG_LPF4_24_SZ	include/ssv6200_aux.h	14200;"	d
+RG_LPF4_25_HI	include/ssv6200_aux.h	14204;"	d
+RG_LPF4_25_I_MSK	include/ssv6200_aux.h	14202;"	d
+RG_LPF4_25_MSK	include/ssv6200_aux.h	14201;"	d
+RG_LPF4_25_SFT	include/ssv6200_aux.h	14203;"	d
+RG_LPF4_25_SZ	include/ssv6200_aux.h	14205;"	d
+RG_LPF4_26_HI	include/ssv6200_aux.h	14209;"	d
+RG_LPF4_26_I_MSK	include/ssv6200_aux.h	14207;"	d
+RG_LPF4_26_MSK	include/ssv6200_aux.h	14206;"	d
+RG_LPF4_26_SFT	include/ssv6200_aux.h	14208;"	d
+RG_LPF4_26_SZ	include/ssv6200_aux.h	14210;"	d
+RG_LPF4_27_HI	include/ssv6200_aux.h	14214;"	d
+RG_LPF4_27_I_MSK	include/ssv6200_aux.h	14212;"	d
+RG_LPF4_27_MSK	include/ssv6200_aux.h	14211;"	d
+RG_LPF4_27_SFT	include/ssv6200_aux.h	14213;"	d
+RG_LPF4_27_SZ	include/ssv6200_aux.h	14215;"	d
+RG_LPF4_28_HI	include/ssv6200_aux.h	14219;"	d
+RG_LPF4_28_I_MSK	include/ssv6200_aux.h	14217;"	d
+RG_LPF4_28_MSK	include/ssv6200_aux.h	14216;"	d
+RG_LPF4_28_SFT	include/ssv6200_aux.h	14218;"	d
+RG_LPF4_28_SZ	include/ssv6200_aux.h	14220;"	d
+RG_LPF4_29_HI	include/ssv6200_aux.h	14224;"	d
+RG_LPF4_29_I_MSK	include/ssv6200_aux.h	14222;"	d
+RG_LPF4_29_MSK	include/ssv6200_aux.h	14221;"	d
+RG_LPF4_29_SFT	include/ssv6200_aux.h	14223;"	d
+RG_LPF4_29_SZ	include/ssv6200_aux.h	14225;"	d
+RG_LPF4_30_HI	include/ssv6200_aux.h	14229;"	d
+RG_LPF4_30_I_MSK	include/ssv6200_aux.h	14227;"	d
+RG_LPF4_30_MSK	include/ssv6200_aux.h	14226;"	d
+RG_LPF4_30_SFT	include/ssv6200_aux.h	14228;"	d
+RG_LPF4_30_SZ	include/ssv6200_aux.h	14230;"	d
+RG_LPF4_31_HI	include/ssv6200_aux.h	14234;"	d
+RG_LPF4_31_I_MSK	include/ssv6200_aux.h	14232;"	d
+RG_LPF4_31_MSK	include/ssv6200_aux.h	14231;"	d
+RG_LPF4_31_SFT	include/ssv6200_aux.h	14233;"	d
+RG_LPF4_31_SZ	include/ssv6200_aux.h	14235;"	d
+RG_LPF4_32_HI	include/ssv6200_aux.h	14239;"	d
+RG_LPF4_32_I_MSK	include/ssv6200_aux.h	14237;"	d
+RG_LPF4_32_MSK	include/ssv6200_aux.h	14236;"	d
+RG_LPF4_32_SFT	include/ssv6200_aux.h	14238;"	d
+RG_LPF4_32_SZ	include/ssv6200_aux.h	14240;"	d
+RG_LPF4_33_HI	include/ssv6200_aux.h	14244;"	d
+RG_LPF4_33_I_MSK	include/ssv6200_aux.h	14242;"	d
+RG_LPF4_33_MSK	include/ssv6200_aux.h	14241;"	d
+RG_LPF4_33_SFT	include/ssv6200_aux.h	14243;"	d
+RG_LPF4_33_SZ	include/ssv6200_aux.h	14245;"	d
+RG_LPF4_34_HI	include/ssv6200_aux.h	14249;"	d
+RG_LPF4_34_I_MSK	include/ssv6200_aux.h	14247;"	d
+RG_LPF4_34_MSK	include/ssv6200_aux.h	14246;"	d
+RG_LPF4_34_SFT	include/ssv6200_aux.h	14248;"	d
+RG_LPF4_34_SZ	include/ssv6200_aux.h	14250;"	d
+RG_LPF4_35_HI	include/ssv6200_aux.h	14254;"	d
+RG_LPF4_35_I_MSK	include/ssv6200_aux.h	14252;"	d
+RG_LPF4_35_MSK	include/ssv6200_aux.h	14251;"	d
+RG_LPF4_35_SFT	include/ssv6200_aux.h	14253;"	d
+RG_LPF4_35_SZ	include/ssv6200_aux.h	14255;"	d
+RG_LPF4_36_HI	include/ssv6200_aux.h	14259;"	d
+RG_LPF4_36_I_MSK	include/ssv6200_aux.h	14257;"	d
+RG_LPF4_36_MSK	include/ssv6200_aux.h	14256;"	d
+RG_LPF4_36_SFT	include/ssv6200_aux.h	14258;"	d
+RG_LPF4_36_SZ	include/ssv6200_aux.h	14260;"	d
+RG_LPF4_37_HI	include/ssv6200_aux.h	14264;"	d
+RG_LPF4_37_I_MSK	include/ssv6200_aux.h	14262;"	d
+RG_LPF4_37_MSK	include/ssv6200_aux.h	14261;"	d
+RG_LPF4_37_SFT	include/ssv6200_aux.h	14263;"	d
+RG_LPF4_37_SZ	include/ssv6200_aux.h	14265;"	d
+RG_LPF4_38_HI	include/ssv6200_aux.h	14269;"	d
+RG_LPF4_38_I_MSK	include/ssv6200_aux.h	14267;"	d
+RG_LPF4_38_MSK	include/ssv6200_aux.h	14266;"	d
+RG_LPF4_38_SFT	include/ssv6200_aux.h	14268;"	d
+RG_LPF4_38_SZ	include/ssv6200_aux.h	14270;"	d
+RG_LPF4_39_HI	include/ssv6200_aux.h	14274;"	d
+RG_LPF4_39_I_MSK	include/ssv6200_aux.h	14272;"	d
+RG_LPF4_39_MSK	include/ssv6200_aux.h	14271;"	d
+RG_LPF4_39_SFT	include/ssv6200_aux.h	14273;"	d
+RG_LPF4_39_SZ	include/ssv6200_aux.h	14275;"	d
+RG_LPF4_40_HI	include/ssv6200_aux.h	14279;"	d
+RG_LPF4_40_I_MSK	include/ssv6200_aux.h	14277;"	d
+RG_LPF4_40_MSK	include/ssv6200_aux.h	14276;"	d
+RG_LPF4_40_SFT	include/ssv6200_aux.h	14278;"	d
+RG_LPF4_40_SZ	include/ssv6200_aux.h	14280;"	d
+RG_L_LENGTH_HI	include/ssv6200_aux.h	13164;"	d
+RG_L_LENGTH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30354;"	d
+RG_L_LENGTH_I_MSK	include/ssv6200_aux.h	13162;"	d
+RG_L_LENGTH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30352;"	d
+RG_L_LENGTH_MAX_HI	include/ssv6200_aux.h	15079;"	d
+RG_L_LENGTH_MAX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32564;"	d
+RG_L_LENGTH_MAX_I_MSK	include/ssv6200_aux.h	15077;"	d
+RG_L_LENGTH_MAX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32562;"	d
+RG_L_LENGTH_MAX_MSK	include/ssv6200_aux.h	15076;"	d
+RG_L_LENGTH_MAX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32561;"	d
+RG_L_LENGTH_MAX_SFT	include/ssv6200_aux.h	15078;"	d
+RG_L_LENGTH_MAX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32563;"	d
+RG_L_LENGTH_MAX_SZ	include/ssv6200_aux.h	15080;"	d
+RG_L_LENGTH_MAX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32565;"	d
+RG_L_LENGTH_MSK	include/ssv6200_aux.h	13161;"	d
+RG_L_LENGTH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30351;"	d
+RG_L_LENGTH_SFT	include/ssv6200_aux.h	13163;"	d
+RG_L_LENGTH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30353;"	d
+RG_L_LENGTH_SZ	include/ssv6200_aux.h	13165;"	d
+RG_L_LENGTH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30355;"	d
+RG_L_RATE_HI	include/ssv6200_aux.h	13169;"	d
+RG_L_RATE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30359;"	d
+RG_L_RATE_I_MSK	include/ssv6200_aux.h	13167;"	d
+RG_L_RATE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30357;"	d
+RG_L_RATE_MSK	include/ssv6200_aux.h	13166;"	d
+RG_L_RATE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30356;"	d
+RG_L_RATE_SFT	include/ssv6200_aux.h	13168;"	d
+RG_L_RATE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30358;"	d
+RG_L_RATE_SZ	include/ssv6200_aux.h	13170;"	d
+RG_L_RATE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30360;"	d
+RG_MAC_DES_SPACE_HI	include/ssv6200_aux.h	15089;"	d
+RG_MAC_DES_SPACE_I_MSK	include/ssv6200_aux.h	15087;"	d
+RG_MAC_DES_SPACE_MSK	include/ssv6200_aux.h	15086;"	d
+RG_MAC_DES_SPACE_SFT	include/ssv6200_aux.h	15088;"	d
+RG_MAC_DES_SPACE_SZ	include/ssv6200_aux.h	15090;"	d
+RG_MAC_LPBK_HI	include/ssv6200_aux.h	8764;"	d
+RG_MAC_LPBK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8519;"	d
+RG_MAC_LPBK_I_MSK	include/ssv6200_aux.h	8762;"	d
+RG_MAC_LPBK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8517;"	d
+RG_MAC_LPBK_MSK	include/ssv6200_aux.h	8761;"	d
+RG_MAC_LPBK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8516;"	d
+RG_MAC_LPBK_SFT	include/ssv6200_aux.h	8763;"	d
+RG_MAC_LPBK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8518;"	d
+RG_MAC_LPBK_SZ	include/ssv6200_aux.h	8765;"	d
+RG_MAC_LPBK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8520;"	d
+RG_MAC_M2M_HI	include/ssv6200_aux.h	8769;"	d
+RG_MAC_M2M_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8524;"	d
+RG_MAC_M2M_I_MSK	include/ssv6200_aux.h	8767;"	d
+RG_MAC_M2M_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8522;"	d
+RG_MAC_M2M_MSK	include/ssv6200_aux.h	8766;"	d
+RG_MAC_M2M_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8521;"	d
+RG_MAC_M2M_SFT	include/ssv6200_aux.h	8768;"	d
+RG_MAC_M2M_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8523;"	d
+RG_MAC_M2M_SZ	include/ssv6200_aux.h	8770;"	d
+RG_MAC_M2M_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8525;"	d
+RG_MAC_PKT_ADDR1_31_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31084;"	d
+RG_MAC_PKT_ADDR1_31_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31082;"	d
+RG_MAC_PKT_ADDR1_31_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31081;"	d
+RG_MAC_PKT_ADDR1_31_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31083;"	d
+RG_MAC_PKT_ADDR1_31_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31085;"	d
+RG_MAC_PKT_ADDR1_47_32_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31089;"	d
+RG_MAC_PKT_ADDR1_47_32_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31087;"	d
+RG_MAC_PKT_ADDR1_47_32_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31086;"	d
+RG_MAC_PKT_ADDR1_47_32_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31088;"	d
+RG_MAC_PKT_ADDR1_47_32_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31090;"	d
+RG_MAC_PKT_ADDR2_31_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31094;"	d
+RG_MAC_PKT_ADDR2_31_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31092;"	d
+RG_MAC_PKT_ADDR2_31_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31091;"	d
+RG_MAC_PKT_ADDR2_31_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31093;"	d
+RG_MAC_PKT_ADDR2_31_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31095;"	d
+RG_MAC_PKT_ADDR2_47_32_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31099;"	d
+RG_MAC_PKT_ADDR2_47_32_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31097;"	d
+RG_MAC_PKT_ADDR2_47_32_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31096;"	d
+RG_MAC_PKT_ADDR2_47_32_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31098;"	d
+RG_MAC_PKT_ADDR2_47_32_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31100;"	d
+RG_MAC_PKT_ADDR2_ON_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31059;"	d
+RG_MAC_PKT_ADDR2_ON_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31057;"	d
+RG_MAC_PKT_ADDR2_ON_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31056;"	d
+RG_MAC_PKT_ADDR2_ON_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31058;"	d
+RG_MAC_PKT_ADDR2_ON_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31060;"	d
+RG_MAC_PKT_ADDR3_31_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31104;"	d
+RG_MAC_PKT_ADDR3_31_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31102;"	d
+RG_MAC_PKT_ADDR3_31_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31101;"	d
+RG_MAC_PKT_ADDR3_31_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31103;"	d
+RG_MAC_PKT_ADDR3_31_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31105;"	d
+RG_MAC_PKT_ADDR3_47_32_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31109;"	d
+RG_MAC_PKT_ADDR3_47_32_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31107;"	d
+RG_MAC_PKT_ADDR3_47_32_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31106;"	d
+RG_MAC_PKT_ADDR3_47_32_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31108;"	d
+RG_MAC_PKT_ADDR3_47_32_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31110;"	d
+RG_MAC_PKT_ADDR3_ON_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31054;"	d
+RG_MAC_PKT_ADDR3_ON_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31052;"	d
+RG_MAC_PKT_ADDR3_ON_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31051;"	d
+RG_MAC_PKT_ADDR3_ON_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31053;"	d
+RG_MAC_PKT_ADDR3_ON_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31055;"	d
+RG_MAC_PKT_ADDR4_31_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31119;"	d
+RG_MAC_PKT_ADDR4_31_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31117;"	d
+RG_MAC_PKT_ADDR4_31_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31116;"	d
+RG_MAC_PKT_ADDR4_31_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31118;"	d
+RG_MAC_PKT_ADDR4_31_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31120;"	d
+RG_MAC_PKT_ADDR4_47_32_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31124;"	d
+RG_MAC_PKT_ADDR4_47_32_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31122;"	d
+RG_MAC_PKT_ADDR4_47_32_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31121;"	d
+RG_MAC_PKT_ADDR4_47_32_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31123;"	d
+RG_MAC_PKT_ADDR4_47_32_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31125;"	d
+RG_MAC_PKT_ADDR4_ON_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31044;"	d
+RG_MAC_PKT_ADDR4_ON_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31042;"	d
+RG_MAC_PKT_ADDR4_ON_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31041;"	d
+RG_MAC_PKT_ADDR4_ON_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31043;"	d
+RG_MAC_PKT_ADDR4_ON_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31045;"	d
+RG_MAC_PKT_AGGREGATE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31039;"	d
+RG_MAC_PKT_AGGREGATE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31037;"	d
+RG_MAC_PKT_AGGREGATE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31036;"	d
+RG_MAC_PKT_AGGREGATE_NUM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31064;"	d
+RG_MAC_PKT_AGGREGATE_NUM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31062;"	d
+RG_MAC_PKT_AGGREGATE_NUM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31061;"	d
+RG_MAC_PKT_AGGREGATE_NUM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31063;"	d
+RG_MAC_PKT_AGGREGATE_NUM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31065;"	d
+RG_MAC_PKT_AGGREGATE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31038;"	d
+RG_MAC_PKT_AGGREGATE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31040;"	d
+RG_MAC_PKT_DUR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31074;"	d
+RG_MAC_PKT_DUR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31072;"	d
+RG_MAC_PKT_DUR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31071;"	d
+RG_MAC_PKT_DUR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31073;"	d
+RG_MAC_PKT_DUR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31075;"	d
+RG_MAC_PKT_FC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31079;"	d
+RG_MAC_PKT_FC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31077;"	d
+RG_MAC_PKT_FC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31076;"	d
+RG_MAC_PKT_FC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31078;"	d
+RG_MAC_PKT_FC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31080;"	d
+RG_MAC_PKT_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31034;"	d
+RG_MAC_PKT_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31032;"	d
+RG_MAC_PKT_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31031;"	d
+RG_MAC_PKT_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31033;"	d
+RG_MAC_PKT_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31035;"	d
+RG_MAC_PKT_PLD_LENGTH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31069;"	d
+RG_MAC_PKT_PLD_LENGTH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31067;"	d
+RG_MAC_PKT_PLD_LENGTH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31066;"	d
+RG_MAC_PKT_PLD_LENGTH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31068;"	d
+RG_MAC_PKT_PLD_LENGTH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31070;"	d
+RG_MAC_PKT_SEQ_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31114;"	d
+RG_MAC_PKT_SEQ_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31112;"	d
+RG_MAC_PKT_SEQ_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31111;"	d
+RG_MAC_PKT_SEQ_ON_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31049;"	d
+RG_MAC_PKT_SEQ_ON_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31047;"	d
+RG_MAC_PKT_SEQ_ON_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31046;"	d
+RG_MAC_PKT_SEQ_ON_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31048;"	d
+RG_MAC_PKT_SEQ_ON_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31050;"	d
+RG_MAC_PKT_SEQ_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31113;"	d
+RG_MAC_PKT_SEQ_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31115;"	d
+RG_MA_DPTH_HI	include/ssv6200_aux.h	15514;"	d
+RG_MA_DPTH_I_MSK	include/ssv6200_aux.h	15512;"	d
+RG_MA_DPTH_MSK	include/ssv6200_aux.h	15511;"	d
+RG_MA_DPTH_SFT	include/ssv6200_aux.h	15513;"	d
+RG_MA_DPTH_SZ	include/ssv6200_aux.h	15515;"	d
+RG_MA_PGA_HIGH_TH_CNT_LMT_HI	include/ssv6200_aux.h	13419;"	d
+RG_MA_PGA_HIGH_TH_CNT_LMT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30599;"	d
+RG_MA_PGA_HIGH_TH_CNT_LMT_I_MSK	include/ssv6200_aux.h	13417;"	d
+RG_MA_PGA_HIGH_TH_CNT_LMT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30597;"	d
+RG_MA_PGA_HIGH_TH_CNT_LMT_MSK	include/ssv6200_aux.h	13416;"	d
+RG_MA_PGA_HIGH_TH_CNT_LMT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30596;"	d
+RG_MA_PGA_HIGH_TH_CNT_LMT_SFT	include/ssv6200_aux.h	13418;"	d
+RG_MA_PGA_HIGH_TH_CNT_LMT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30598;"	d
+RG_MA_PGA_HIGH_TH_CNT_LMT_SZ	include/ssv6200_aux.h	13420;"	d
+RG_MA_PGA_HIGH_TH_CNT_LMT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30600;"	d
+RG_MA_PGA_LOW_TH_CNT_LMT_HI	include/ssv6200_aux.h	13404;"	d
+RG_MA_PGA_LOW_TH_CNT_LMT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30594;"	d
+RG_MA_PGA_LOW_TH_CNT_LMT_I_MSK	include/ssv6200_aux.h	13402;"	d
+RG_MA_PGA_LOW_TH_CNT_LMT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30592;"	d
+RG_MA_PGA_LOW_TH_CNT_LMT_MSK	include/ssv6200_aux.h	13401;"	d
+RG_MA_PGA_LOW_TH_CNT_LMT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30591;"	d
+RG_MA_PGA_LOW_TH_CNT_LMT_SFT	include/ssv6200_aux.h	13403;"	d
+RG_MA_PGA_LOW_TH_CNT_LMT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30593;"	d
+RG_MA_PGA_LOW_TH_CNT_LMT_SZ	include/ssv6200_aux.h	13405;"	d
+RG_MA_PGA_LOW_TH_CNT_LMT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30595;"	d
+RG_MBRUN_16_HI	include/ssv6200_aux.h	13969;"	d
+RG_MBRUN_16_I_MSK	include/ssv6200_aux.h	13967;"	d
+RG_MBRUN_16_MSK	include/ssv6200_aux.h	13966;"	d
+RG_MBRUN_16_SFT	include/ssv6200_aux.h	13968;"	d
+RG_MBRUN_16_SZ	include/ssv6200_aux.h	13970;"	d
+RG_MBRUN_64_HI	include/ssv6200_aux.h	15159;"	d
+RG_MBRUN_64_I_MSK	include/ssv6200_aux.h	15157;"	d
+RG_MBRUN_64_MSK	include/ssv6200_aux.h	15156;"	d
+RG_MBRUN_64_SFT	include/ssv6200_aux.h	15158;"	d
+RG_MBRUN_64_SZ	include/ssv6200_aux.h	15160;"	d
+RG_MBRUN_80_HI	include/ssv6200_aux.h	15124;"	d
+RG_MBRUN_80_I_MSK	include/ssv6200_aux.h	15122;"	d
+RG_MBRUN_80_MSK	include/ssv6200_aux.h	15121;"	d
+RG_MBRUN_80_SFT	include/ssv6200_aux.h	15123;"	d
+RG_MBRUN_80_SZ	include/ssv6200_aux.h	15125;"	d
+RG_MG_PGA_JB_TH_HI	include/ssv6200_aux.h	13399;"	d
+RG_MG_PGA_JB_TH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30589;"	d
+RG_MG_PGA_JB_TH_I_MSK	include/ssv6200_aux.h	13397;"	d
+RG_MG_PGA_JB_TH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30587;"	d
+RG_MG_PGA_JB_TH_MSK	include/ssv6200_aux.h	13396;"	d
+RG_MG_PGA_JB_TH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30586;"	d
+RG_MG_PGA_JB_TH_SFT	include/ssv6200_aux.h	13398;"	d
+RG_MG_PGA_JB_TH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30588;"	d
+RG_MG_PGA_JB_TH_SZ	include/ssv6200_aux.h	13400;"	d
+RG_MG_PGA_JB_TH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30590;"	d
+RG_MG_RF_SAT_PGANOREF_PGA_GAIN_HI	include/ssv6200_aux.h	13379;"	d
+RG_MG_RF_SAT_PGANOREF_PGA_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30569;"	d
+RG_MG_RF_SAT_PGANOREF_PGA_GAIN_I_MSK	include/ssv6200_aux.h	13377;"	d
+RG_MG_RF_SAT_PGANOREF_PGA_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30567;"	d
+RG_MG_RF_SAT_PGANOREF_PGA_GAIN_MSK	include/ssv6200_aux.h	13376;"	d
+RG_MG_RF_SAT_PGANOREF_PGA_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30566;"	d
+RG_MG_RF_SAT_PGANOREF_PGA_GAIN_SFT	include/ssv6200_aux.h	13378;"	d
+RG_MG_RF_SAT_PGANOREF_PGA_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30568;"	d
+RG_MG_RF_SAT_PGANOREF_PGA_GAIN_SZ	include/ssv6200_aux.h	13380;"	d
+RG_MG_RF_SAT_PGANOREF_PGA_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30570;"	d
+RG_MODE_BY_HS_3WIRE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27729;"	d
+RG_MODE_BY_HS_3WIRE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27727;"	d
+RG_MODE_BY_HS_3WIRE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27726;"	d
+RG_MODE_BY_HS_3WIRE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27728;"	d
+RG_MODE_BY_HS_3WIRE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27730;"	d
+RG_MODE_BY_HWPIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27739;"	d
+RG_MODE_BY_HWPIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27737;"	d
+RG_MODE_BY_HWPIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27736;"	d
+RG_MODE_BY_HWPIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27738;"	d
+RG_MODE_BY_HWPIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27740;"	d
+RG_MODE_BY_PHY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27734;"	d
+RG_MODE_BY_PHY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27732;"	d
+RG_MODE_BY_PHY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27731;"	d
+RG_MODE_BY_PHY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27733;"	d
+RG_MODE_BY_PHY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27735;"	d
+RG_MODE_HI	include/ssv6200_aux.h	16099;"	d
+RG_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21609;"	d
+RG_MODE_I_MSK	include/ssv6200_aux.h	16097;"	d
+RG_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21607;"	d
+RG_MODE_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21579;"	d
+RG_MODE_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21577;"	d
+RG_MODE_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21576;"	d
+RG_MODE_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21578;"	d
+RG_MODE_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21580;"	d
+RG_MODE_MSK	include/ssv6200_aux.h	16096;"	d
+RG_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21606;"	d
+RG_MODE_REG_IN_16_HI	include/ssv6200_aux.h	13959;"	d
+RG_MODE_REG_IN_16_I_MSK	include/ssv6200_aux.h	13957;"	d
+RG_MODE_REG_IN_16_MSK	include/ssv6200_aux.h	13956;"	d
+RG_MODE_REG_IN_16_SFT	include/ssv6200_aux.h	13958;"	d
+RG_MODE_REG_IN_16_SZ	include/ssv6200_aux.h	13960;"	d
+RG_MODE_REG_IN_64_HI	include/ssv6200_aux.h	15149;"	d
+RG_MODE_REG_IN_64_I_MSK	include/ssv6200_aux.h	15147;"	d
+RG_MODE_REG_IN_64_MSK	include/ssv6200_aux.h	15146;"	d
+RG_MODE_REG_IN_64_SFT	include/ssv6200_aux.h	15148;"	d
+RG_MODE_REG_IN_64_SZ	include/ssv6200_aux.h	15150;"	d
+RG_MODE_REG_IN_80_HI	include/ssv6200_aux.h	15114;"	d
+RG_MODE_REG_IN_80_I_MSK	include/ssv6200_aux.h	15112;"	d
+RG_MODE_REG_IN_80_MSK	include/ssv6200_aux.h	15111;"	d
+RG_MODE_REG_IN_80_SFT	include/ssv6200_aux.h	15113;"	d
+RG_MODE_REG_IN_80_SZ	include/ssv6200_aux.h	15115;"	d
+RG_MODE_REG_SI_16_HI	include/ssv6200_aux.h	13979;"	d
+RG_MODE_REG_SI_16_I_MSK	include/ssv6200_aux.h	13977;"	d
+RG_MODE_REG_SI_16_MSK	include/ssv6200_aux.h	13976;"	d
+RG_MODE_REG_SI_16_SFT	include/ssv6200_aux.h	13978;"	d
+RG_MODE_REG_SI_16_SZ	include/ssv6200_aux.h	13980;"	d
+RG_MODE_REG_SI_64_HI	include/ssv6200_aux.h	15169;"	d
+RG_MODE_REG_SI_64_I_MSK	include/ssv6200_aux.h	15167;"	d
+RG_MODE_REG_SI_64_MSK	include/ssv6200_aux.h	15166;"	d
+RG_MODE_REG_SI_64_SFT	include/ssv6200_aux.h	15168;"	d
+RG_MODE_REG_SI_64_SZ	include/ssv6200_aux.h	15170;"	d
+RG_MODE_REG_SI_80_HI	include/ssv6200_aux.h	15134;"	d
+RG_MODE_REG_SI_80_I_MSK	include/ssv6200_aux.h	15132;"	d
+RG_MODE_REG_SI_80_MSK	include/ssv6200_aux.h	15131;"	d
+RG_MODE_REG_SI_80_SFT	include/ssv6200_aux.h	15133;"	d
+RG_MODE_REG_SI_80_SZ	include/ssv6200_aux.h	15135;"	d
+RG_MODE_SFT	include/ssv6200_aux.h	16098;"	d
+RG_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21608;"	d
+RG_MODE_SZ	include/ssv6200_aux.h	16100;"	d
+RG_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21610;"	d
+RG_MRX_EN_CNT_RST_N_HI	include/ssv6200_aux.h	13824;"	d
+RG_MRX_EN_CNT_RST_N_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30829;"	d
+RG_MRX_EN_CNT_RST_N_I_MSK	include/ssv6200_aux.h	13822;"	d
+RG_MRX_EN_CNT_RST_N_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30827;"	d
+RG_MRX_EN_CNT_RST_N_MSK	include/ssv6200_aux.h	13821;"	d
+RG_MRX_EN_CNT_RST_N_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30826;"	d
+RG_MRX_EN_CNT_RST_N_SFT	include/ssv6200_aux.h	13823;"	d
+RG_MRX_EN_CNT_RST_N_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30828;"	d
+RG_MRX_EN_CNT_RST_N_SZ	include/ssv6200_aux.h	13825;"	d
+RG_MRX_EN_CNT_RST_N_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30830;"	d
+RG_MRX_LEN_CNT_EN_0_HI	include/ssv6200_aux.h	13919;"	d
+RG_MRX_LEN_CNT_EN_0_I_MSK	include/ssv6200_aux.h	13917;"	d
+RG_MRX_LEN_CNT_EN_0_MSK	include/ssv6200_aux.h	13916;"	d
+RG_MRX_LEN_CNT_EN_0_SFT	include/ssv6200_aux.h	13918;"	d
+RG_MRX_LEN_CNT_EN_0_SZ	include/ssv6200_aux.h	13920;"	d
+RG_MRX_LEN_CNT_EN_1_HI	include/ssv6200_aux.h	13934;"	d
+RG_MRX_LEN_CNT_EN_1_I_MSK	include/ssv6200_aux.h	13932;"	d
+RG_MRX_LEN_CNT_EN_1_MSK	include/ssv6200_aux.h	13931;"	d
+RG_MRX_LEN_CNT_EN_1_SFT	include/ssv6200_aux.h	13933;"	d
+RG_MRX_LEN_CNT_EN_1_SZ	include/ssv6200_aux.h	13935;"	d
+RG_MRX_LEN_LOWER_TH_0_HI	include/ssv6200_aux.h	13909;"	d
+RG_MRX_LEN_LOWER_TH_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30924;"	d
+RG_MRX_LEN_LOWER_TH_0_I_MSK	include/ssv6200_aux.h	13907;"	d
+RG_MRX_LEN_LOWER_TH_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30922;"	d
+RG_MRX_LEN_LOWER_TH_0_MSK	include/ssv6200_aux.h	13906;"	d
+RG_MRX_LEN_LOWER_TH_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30921;"	d
+RG_MRX_LEN_LOWER_TH_0_SFT	include/ssv6200_aux.h	13908;"	d
+RG_MRX_LEN_LOWER_TH_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30923;"	d
+RG_MRX_LEN_LOWER_TH_0_SZ	include/ssv6200_aux.h	13910;"	d
+RG_MRX_LEN_LOWER_TH_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30925;"	d
+RG_MRX_LEN_LOWER_TH_1_HI	include/ssv6200_aux.h	13924;"	d
+RG_MRX_LEN_LOWER_TH_1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30934;"	d
+RG_MRX_LEN_LOWER_TH_1_I_MSK	include/ssv6200_aux.h	13922;"	d
+RG_MRX_LEN_LOWER_TH_1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30932;"	d
+RG_MRX_LEN_LOWER_TH_1_MSK	include/ssv6200_aux.h	13921;"	d
+RG_MRX_LEN_LOWER_TH_1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30931;"	d
+RG_MRX_LEN_LOWER_TH_1_SFT	include/ssv6200_aux.h	13923;"	d
+RG_MRX_LEN_LOWER_TH_1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30933;"	d
+RG_MRX_LEN_LOWER_TH_1_SZ	include/ssv6200_aux.h	13925;"	d
+RG_MRX_LEN_LOWER_TH_1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30935;"	d
+RG_MRX_LEN_UPPER_TH_0_HI	include/ssv6200_aux.h	13914;"	d
+RG_MRX_LEN_UPPER_TH_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30929;"	d
+RG_MRX_LEN_UPPER_TH_0_I_MSK	include/ssv6200_aux.h	13912;"	d
+RG_MRX_LEN_UPPER_TH_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30927;"	d
+RG_MRX_LEN_UPPER_TH_0_MSK	include/ssv6200_aux.h	13911;"	d
+RG_MRX_LEN_UPPER_TH_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30926;"	d
+RG_MRX_LEN_UPPER_TH_0_SFT	include/ssv6200_aux.h	13913;"	d
+RG_MRX_LEN_UPPER_TH_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30928;"	d
+RG_MRX_LEN_UPPER_TH_0_SZ	include/ssv6200_aux.h	13915;"	d
+RG_MRX_LEN_UPPER_TH_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30930;"	d
+RG_MRX_LEN_UPPER_TH_1_HI	include/ssv6200_aux.h	13929;"	d
+RG_MRX_LEN_UPPER_TH_1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30939;"	d
+RG_MRX_LEN_UPPER_TH_1_I_MSK	include/ssv6200_aux.h	13927;"	d
+RG_MRX_LEN_UPPER_TH_1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30937;"	d
+RG_MRX_LEN_UPPER_TH_1_MSK	include/ssv6200_aux.h	13926;"	d
+RG_MRX_LEN_UPPER_TH_1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30936;"	d
+RG_MRX_LEN_UPPER_TH_1_SFT	include/ssv6200_aux.h	13928;"	d
+RG_MRX_LEN_UPPER_TH_1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30938;"	d
+RG_MRX_LEN_UPPER_TH_1_SZ	include/ssv6200_aux.h	13930;"	d
+RG_MRX_LEN_UPPER_TH_1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30940;"	d
+RG_MRX_TYPE_0_HI	include/ssv6200_aux.h	14014;"	d
+RG_MRX_TYPE_0_I_MSK	include/ssv6200_aux.h	14012;"	d
+RG_MRX_TYPE_0_MSK	include/ssv6200_aux.h	14011;"	d
+RG_MRX_TYPE_0_SFT	include/ssv6200_aux.h	14013;"	d
+RG_MRX_TYPE_0_SZ	include/ssv6200_aux.h	14015;"	d
+RG_MRX_TYPE_1_HI	include/ssv6200_aux.h	14009;"	d
+RG_MRX_TYPE_1_I_MSK	include/ssv6200_aux.h	14007;"	d
+RG_MRX_TYPE_1_MSK	include/ssv6200_aux.h	14006;"	d
+RG_MRX_TYPE_1_SFT	include/ssv6200_aux.h	14008;"	d
+RG_MRX_TYPE_1_SZ	include/ssv6200_aux.h	14010;"	d
+RG_MRX_TYPE_CNT_LMT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30969;"	d
+RG_MRX_TYPE_CNT_LMT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30967;"	d
+RG_MRX_TYPE_CNT_LMT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30966;"	d
+RG_MRX_TYPE_CNT_LMT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30968;"	d
+RG_MRX_TYPE_CNT_LMT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30970;"	d
+RG_MRX_TYPE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30964;"	d
+RG_MRX_TYPE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30962;"	d
+RG_MRX_TYPE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30961;"	d
+RG_MRX_TYPE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30963;"	d
+RG_MRX_TYPE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30965;"	d
+RG_MTX_LEN_CNT_EN_0_HI	include/ssv6200_aux.h	13889;"	d
+RG_MTX_LEN_CNT_EN_0_I_MSK	include/ssv6200_aux.h	13887;"	d
+RG_MTX_LEN_CNT_EN_0_MSK	include/ssv6200_aux.h	13886;"	d
+RG_MTX_LEN_CNT_EN_0_SFT	include/ssv6200_aux.h	13888;"	d
+RG_MTX_LEN_CNT_EN_0_SZ	include/ssv6200_aux.h	13890;"	d
+RG_MTX_LEN_CNT_EN_1_HI	include/ssv6200_aux.h	13904;"	d
+RG_MTX_LEN_CNT_EN_1_I_MSK	include/ssv6200_aux.h	13902;"	d
+RG_MTX_LEN_CNT_EN_1_MSK	include/ssv6200_aux.h	13901;"	d
+RG_MTX_LEN_CNT_EN_1_SFT	include/ssv6200_aux.h	13903;"	d
+RG_MTX_LEN_CNT_EN_1_SZ	include/ssv6200_aux.h	13905;"	d
+RG_MTX_LEN_LOWER_TH_0_HI	include/ssv6200_aux.h	13879;"	d
+RG_MTX_LEN_LOWER_TH_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30904;"	d
+RG_MTX_LEN_LOWER_TH_0_I_MSK	include/ssv6200_aux.h	13877;"	d
+RG_MTX_LEN_LOWER_TH_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30902;"	d
+RG_MTX_LEN_LOWER_TH_0_MSK	include/ssv6200_aux.h	13876;"	d
+RG_MTX_LEN_LOWER_TH_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30901;"	d
+RG_MTX_LEN_LOWER_TH_0_SFT	include/ssv6200_aux.h	13878;"	d
+RG_MTX_LEN_LOWER_TH_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30903;"	d
+RG_MTX_LEN_LOWER_TH_0_SZ	include/ssv6200_aux.h	13880;"	d
+RG_MTX_LEN_LOWER_TH_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30905;"	d
+RG_MTX_LEN_LOWER_TH_1_HI	include/ssv6200_aux.h	13894;"	d
+RG_MTX_LEN_LOWER_TH_1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30914;"	d
+RG_MTX_LEN_LOWER_TH_1_I_MSK	include/ssv6200_aux.h	13892;"	d
+RG_MTX_LEN_LOWER_TH_1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30912;"	d
+RG_MTX_LEN_LOWER_TH_1_MSK	include/ssv6200_aux.h	13891;"	d
+RG_MTX_LEN_LOWER_TH_1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30911;"	d
+RG_MTX_LEN_LOWER_TH_1_SFT	include/ssv6200_aux.h	13893;"	d
+RG_MTX_LEN_LOWER_TH_1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30913;"	d
+RG_MTX_LEN_LOWER_TH_1_SZ	include/ssv6200_aux.h	13895;"	d
+RG_MTX_LEN_LOWER_TH_1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30915;"	d
+RG_MTX_LEN_UPPER_TH_0_HI	include/ssv6200_aux.h	13884;"	d
+RG_MTX_LEN_UPPER_TH_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30909;"	d
+RG_MTX_LEN_UPPER_TH_0_I_MSK	include/ssv6200_aux.h	13882;"	d
+RG_MTX_LEN_UPPER_TH_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30907;"	d
+RG_MTX_LEN_UPPER_TH_0_MSK	include/ssv6200_aux.h	13881;"	d
+RG_MTX_LEN_UPPER_TH_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30906;"	d
+RG_MTX_LEN_UPPER_TH_0_SFT	include/ssv6200_aux.h	13883;"	d
+RG_MTX_LEN_UPPER_TH_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30908;"	d
+RG_MTX_LEN_UPPER_TH_0_SZ	include/ssv6200_aux.h	13885;"	d
+RG_MTX_LEN_UPPER_TH_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30910;"	d
+RG_MTX_LEN_UPPER_TH_1_HI	include/ssv6200_aux.h	13899;"	d
+RG_MTX_LEN_UPPER_TH_1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30919;"	d
+RG_MTX_LEN_UPPER_TH_1_I_MSK	include/ssv6200_aux.h	13897;"	d
+RG_MTX_LEN_UPPER_TH_1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30917;"	d
+RG_MTX_LEN_UPPER_TH_1_MSK	include/ssv6200_aux.h	13896;"	d
+RG_MTX_LEN_UPPER_TH_1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30916;"	d
+RG_MTX_LEN_UPPER_TH_1_SFT	include/ssv6200_aux.h	13898;"	d
+RG_MTX_LEN_UPPER_TH_1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30918;"	d
+RG_MTX_LEN_UPPER_TH_1_SZ	include/ssv6200_aux.h	13900;"	d
+RG_MTX_LEN_UPPER_TH_1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30920;"	d
+RG_MTX_TYPE_0_HI	include/ssv6200_aux.h	14024;"	d
+RG_MTX_TYPE_0_I_MSK	include/ssv6200_aux.h	14022;"	d
+RG_MTX_TYPE_0_MSK	include/ssv6200_aux.h	14021;"	d
+RG_MTX_TYPE_0_SFT	include/ssv6200_aux.h	14023;"	d
+RG_MTX_TYPE_0_SZ	include/ssv6200_aux.h	14025;"	d
+RG_MTX_TYPE_1_HI	include/ssv6200_aux.h	14019;"	d
+RG_MTX_TYPE_1_I_MSK	include/ssv6200_aux.h	14017;"	d
+RG_MTX_TYPE_1_MSK	include/ssv6200_aux.h	14016;"	d
+RG_MTX_TYPE_1_SFT	include/ssv6200_aux.h	14018;"	d
+RG_MTX_TYPE_1_SZ	include/ssv6200_aux.h	14020;"	d
+RG_MTX_TYPE_CNT_LMT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30979;"	d
+RG_MTX_TYPE_CNT_LMT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30977;"	d
+RG_MTX_TYPE_CNT_LMT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30976;"	d
+RG_MTX_TYPE_CNT_LMT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30978;"	d
+RG_MTX_TYPE_CNT_LMT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30980;"	d
+RG_MTX_TYPE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30974;"	d
+RG_MTX_TYPE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30972;"	d
+RG_MTX_TYPE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30971;"	d
+RG_MTX_TYPE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30973;"	d
+RG_MTX_TYPE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30975;"	d
+RG_NEW_PILOT_AVG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32549;"	d
+RG_NEW_PILOT_AVG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32547;"	d
+RG_NEW_PILOT_AVG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32546;"	d
+RG_NEW_PILOT_AVG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32548;"	d
+RG_NEW_PILOT_AVG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32550;"	d
+RG_NEW_SB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32554;"	d
+RG_NEW_SB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32552;"	d
+RG_NEW_SB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32551;"	d
+RG_NEW_SB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32553;"	d
+RG_NEW_SB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32555;"	d
+RG_NFRAC_DELTA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27159;"	d
+RG_NFRAC_DELTA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27157;"	d
+RG_NFRAC_DELTA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27156;"	d
+RG_NFRAC_DELTA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27158;"	d
+RG_NFRAC_DELTA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27160;"	d
+RG_NORMSQUARE_LOW_SNR_4_HI	include/ssv6200_aux.h	14869;"	d
+RG_NORMSQUARE_LOW_SNR_4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32109;"	d
+RG_NORMSQUARE_LOW_SNR_4_I_MSK	include/ssv6200_aux.h	14867;"	d
+RG_NORMSQUARE_LOW_SNR_4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32107;"	d
+RG_NORMSQUARE_LOW_SNR_4_MSK	include/ssv6200_aux.h	14866;"	d
+RG_NORMSQUARE_LOW_SNR_4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32106;"	d
+RG_NORMSQUARE_LOW_SNR_4_SFT	include/ssv6200_aux.h	14868;"	d
+RG_NORMSQUARE_LOW_SNR_4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32108;"	d
+RG_NORMSQUARE_LOW_SNR_4_SZ	include/ssv6200_aux.h	14870;"	d
+RG_NORMSQUARE_LOW_SNR_4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32110;"	d
+RG_NORMSQUARE_LOW_SNR_5_HI	include/ssv6200_aux.h	14864;"	d
+RG_NORMSQUARE_LOW_SNR_5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32104;"	d
+RG_NORMSQUARE_LOW_SNR_5_I_MSK	include/ssv6200_aux.h	14862;"	d
+RG_NORMSQUARE_LOW_SNR_5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32102;"	d
+RG_NORMSQUARE_LOW_SNR_5_MSK	include/ssv6200_aux.h	14861;"	d
+RG_NORMSQUARE_LOW_SNR_5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32101;"	d
+RG_NORMSQUARE_LOW_SNR_5_SFT	include/ssv6200_aux.h	14863;"	d
+RG_NORMSQUARE_LOW_SNR_5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32103;"	d
+RG_NORMSQUARE_LOW_SNR_5_SZ	include/ssv6200_aux.h	14865;"	d
+RG_NORMSQUARE_LOW_SNR_5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32105;"	d
+RG_NORMSQUARE_LOW_SNR_6_HI	include/ssv6200_aux.h	14859;"	d
+RG_NORMSQUARE_LOW_SNR_6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32099;"	d
+RG_NORMSQUARE_LOW_SNR_6_I_MSK	include/ssv6200_aux.h	14857;"	d
+RG_NORMSQUARE_LOW_SNR_6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32097;"	d
+RG_NORMSQUARE_LOW_SNR_6_MSK	include/ssv6200_aux.h	14856;"	d
+RG_NORMSQUARE_LOW_SNR_6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32096;"	d
+RG_NORMSQUARE_LOW_SNR_6_SFT	include/ssv6200_aux.h	14858;"	d
+RG_NORMSQUARE_LOW_SNR_6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32098;"	d
+RG_NORMSQUARE_LOW_SNR_6_SZ	include/ssv6200_aux.h	14860;"	d
+RG_NORMSQUARE_LOW_SNR_6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32100;"	d
+RG_NORMSQUARE_LOW_SNR_7_HI	include/ssv6200_aux.h	14854;"	d
+RG_NORMSQUARE_LOW_SNR_7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32094;"	d
+RG_NORMSQUARE_LOW_SNR_7_I_MSK	include/ssv6200_aux.h	14852;"	d
+RG_NORMSQUARE_LOW_SNR_7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32092;"	d
+RG_NORMSQUARE_LOW_SNR_7_MSK	include/ssv6200_aux.h	14851;"	d
+RG_NORMSQUARE_LOW_SNR_7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32091;"	d
+RG_NORMSQUARE_LOW_SNR_7_SFT	include/ssv6200_aux.h	14853;"	d
+RG_NORMSQUARE_LOW_SNR_7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32093;"	d
+RG_NORMSQUARE_LOW_SNR_7_SZ	include/ssv6200_aux.h	14855;"	d
+RG_NORMSQUARE_LOW_SNR_7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32095;"	d
+RG_NORMSQUARE_LOW_SNR_8_HI	include/ssv6200_aux.h	14874;"	d
+RG_NORMSQUARE_LOW_SNR_8_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32114;"	d
+RG_NORMSQUARE_LOW_SNR_8_I_MSK	include/ssv6200_aux.h	14872;"	d
+RG_NORMSQUARE_LOW_SNR_8_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32112;"	d
+RG_NORMSQUARE_LOW_SNR_8_MSK	include/ssv6200_aux.h	14871;"	d
+RG_NORMSQUARE_LOW_SNR_8_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32111;"	d
+RG_NORMSQUARE_LOW_SNR_8_SFT	include/ssv6200_aux.h	14873;"	d
+RG_NORMSQUARE_LOW_SNR_8_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32113;"	d
+RG_NORMSQUARE_LOW_SNR_8_SZ	include/ssv6200_aux.h	14875;"	d
+RG_NORMSQUARE_LOW_SNR_8_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32115;"	d
+RG_NORMSQUARE_SNR_0_HI	include/ssv6200_aux.h	14894;"	d
+RG_NORMSQUARE_SNR_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32134;"	d
+RG_NORMSQUARE_SNR_0_I_MSK	include/ssv6200_aux.h	14892;"	d
+RG_NORMSQUARE_SNR_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32132;"	d
+RG_NORMSQUARE_SNR_0_MSK	include/ssv6200_aux.h	14891;"	d
+RG_NORMSQUARE_SNR_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32131;"	d
+RG_NORMSQUARE_SNR_0_SFT	include/ssv6200_aux.h	14893;"	d
+RG_NORMSQUARE_SNR_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32133;"	d
+RG_NORMSQUARE_SNR_0_SZ	include/ssv6200_aux.h	14895;"	d
+RG_NORMSQUARE_SNR_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32135;"	d
+RG_NORMSQUARE_SNR_1_HI	include/ssv6200_aux.h	14889;"	d
+RG_NORMSQUARE_SNR_1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32129;"	d
+RG_NORMSQUARE_SNR_1_I_MSK	include/ssv6200_aux.h	14887;"	d
+RG_NORMSQUARE_SNR_1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32127;"	d
+RG_NORMSQUARE_SNR_1_MSK	include/ssv6200_aux.h	14886;"	d
+RG_NORMSQUARE_SNR_1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32126;"	d
+RG_NORMSQUARE_SNR_1_SFT	include/ssv6200_aux.h	14888;"	d
+RG_NORMSQUARE_SNR_1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32128;"	d
+RG_NORMSQUARE_SNR_1_SZ	include/ssv6200_aux.h	14890;"	d
+RG_NORMSQUARE_SNR_1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32130;"	d
+RG_NORMSQUARE_SNR_2_HI	include/ssv6200_aux.h	14884;"	d
+RG_NORMSQUARE_SNR_2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32124;"	d
+RG_NORMSQUARE_SNR_2_I_MSK	include/ssv6200_aux.h	14882;"	d
+RG_NORMSQUARE_SNR_2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32122;"	d
+RG_NORMSQUARE_SNR_2_MSK	include/ssv6200_aux.h	14881;"	d
+RG_NORMSQUARE_SNR_2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32121;"	d
+RG_NORMSQUARE_SNR_2_SFT	include/ssv6200_aux.h	14883;"	d
+RG_NORMSQUARE_SNR_2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32123;"	d
+RG_NORMSQUARE_SNR_2_SZ	include/ssv6200_aux.h	14885;"	d
+RG_NORMSQUARE_SNR_2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32125;"	d
+RG_NORMSQUARE_SNR_3_HI	include/ssv6200_aux.h	14879;"	d
+RG_NORMSQUARE_SNR_3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32119;"	d
+RG_NORMSQUARE_SNR_3_I_MSK	include/ssv6200_aux.h	14877;"	d
+RG_NORMSQUARE_SNR_3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32117;"	d
+RG_NORMSQUARE_SNR_3_MSK	include/ssv6200_aux.h	14876;"	d
+RG_NORMSQUARE_SNR_3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32116;"	d
+RG_NORMSQUARE_SNR_3_SFT	include/ssv6200_aux.h	14878;"	d
+RG_NORMSQUARE_SNR_3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32118;"	d
+RG_NORMSQUARE_SNR_3_SZ	include/ssv6200_aux.h	14880;"	d
+RG_NORMSQUARE_SNR_3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32120;"	d
+RG_NORMSQUARE_SNR_4_HI	include/ssv6200_aux.h	14914;"	d
+RG_NORMSQUARE_SNR_4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32154;"	d
+RG_NORMSQUARE_SNR_4_I_MSK	include/ssv6200_aux.h	14912;"	d
+RG_NORMSQUARE_SNR_4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32152;"	d
+RG_NORMSQUARE_SNR_4_MSK	include/ssv6200_aux.h	14911;"	d
+RG_NORMSQUARE_SNR_4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32151;"	d
+RG_NORMSQUARE_SNR_4_SFT	include/ssv6200_aux.h	14913;"	d
+RG_NORMSQUARE_SNR_4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32153;"	d
+RG_NORMSQUARE_SNR_4_SZ	include/ssv6200_aux.h	14915;"	d
+RG_NORMSQUARE_SNR_4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32155;"	d
+RG_NORMSQUARE_SNR_5_HI	include/ssv6200_aux.h	14909;"	d
+RG_NORMSQUARE_SNR_5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32149;"	d
+RG_NORMSQUARE_SNR_5_I_MSK	include/ssv6200_aux.h	14907;"	d
+RG_NORMSQUARE_SNR_5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32147;"	d
+RG_NORMSQUARE_SNR_5_MSK	include/ssv6200_aux.h	14906;"	d
+RG_NORMSQUARE_SNR_5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32146;"	d
+RG_NORMSQUARE_SNR_5_SFT	include/ssv6200_aux.h	14908;"	d
+RG_NORMSQUARE_SNR_5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32148;"	d
+RG_NORMSQUARE_SNR_5_SZ	include/ssv6200_aux.h	14910;"	d
+RG_NORMSQUARE_SNR_5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32150;"	d
+RG_NORMSQUARE_SNR_6_HI	include/ssv6200_aux.h	14904;"	d
+RG_NORMSQUARE_SNR_6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32144;"	d
+RG_NORMSQUARE_SNR_6_I_MSK	include/ssv6200_aux.h	14902;"	d
+RG_NORMSQUARE_SNR_6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32142;"	d
+RG_NORMSQUARE_SNR_6_MSK	include/ssv6200_aux.h	14901;"	d
+RG_NORMSQUARE_SNR_6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32141;"	d
+RG_NORMSQUARE_SNR_6_SFT	include/ssv6200_aux.h	14903;"	d
+RG_NORMSQUARE_SNR_6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32143;"	d
+RG_NORMSQUARE_SNR_6_SZ	include/ssv6200_aux.h	14905;"	d
+RG_NORMSQUARE_SNR_6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32145;"	d
+RG_NORMSQUARE_SNR_7_HI	include/ssv6200_aux.h	14899;"	d
+RG_NORMSQUARE_SNR_7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32139;"	d
+RG_NORMSQUARE_SNR_7_I_MSK	include/ssv6200_aux.h	14897;"	d
+RG_NORMSQUARE_SNR_7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32137;"	d
+RG_NORMSQUARE_SNR_7_MSK	include/ssv6200_aux.h	14896;"	d
+RG_NORMSQUARE_SNR_7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32136;"	d
+RG_NORMSQUARE_SNR_7_SFT	include/ssv6200_aux.h	14898;"	d
+RG_NORMSQUARE_SNR_7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32138;"	d
+RG_NORMSQUARE_SNR_7_SZ	include/ssv6200_aux.h	14900;"	d
+RG_NORMSQUARE_SNR_7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32140;"	d
+RG_NORMSQUARE_SNR_8_HI	include/ssv6200_aux.h	14919;"	d
+RG_NORMSQUARE_SNR_8_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32159;"	d
+RG_NORMSQUARE_SNR_8_I_MSK	include/ssv6200_aux.h	14917;"	d
+RG_NORMSQUARE_SNR_8_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32157;"	d
+RG_NORMSQUARE_SNR_8_MSK	include/ssv6200_aux.h	14916;"	d
+RG_NORMSQUARE_SNR_8_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32156;"	d
+RG_NORMSQUARE_SNR_8_SFT	include/ssv6200_aux.h	14918;"	d
+RG_NORMSQUARE_SNR_8_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32158;"	d
+RG_NORMSQUARE_SNR_8_SZ	include/ssv6200_aux.h	14920;"	d
+RG_NORMSQUARE_SNR_8_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32160;"	d
+RG_NO_SOUND_HI	include/ssv6200_aux.h	13184;"	d
+RG_NO_SOUND_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30374;"	d
+RG_NO_SOUND_I_MSK	include/ssv6200_aux.h	13182;"	d
+RG_NO_SOUND_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30372;"	d
+RG_NO_SOUND_MSK	include/ssv6200_aux.h	13181;"	d
+RG_NO_SOUND_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30371;"	d
+RG_NO_SOUND_SFT	include/ssv6200_aux.h	13183;"	d
+RG_NO_SOUND_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30373;"	d
+RG_NO_SOUND_SZ	include/ssv6200_aux.h	13185;"	d
+RG_NO_SOUND_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30375;"	d
+RG_N_ESS_HI	include/ssv6200_aux.h	13204;"	d
+RG_N_ESS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30394;"	d
+RG_N_ESS_I_MSK	include/ssv6200_aux.h	13202;"	d
+RG_N_ESS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30392;"	d
+RG_N_ESS_MSK	include/ssv6200_aux.h	13201;"	d
+RG_N_ESS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30391;"	d
+RG_N_ESS_SFT	include/ssv6200_aux.h	13203;"	d
+RG_N_ESS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30393;"	d
+RG_N_ESS_SZ	include/ssv6200_aux.h	13205;"	d
+RG_N_ESS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30395;"	d
+RG_PABIAS_CTRL_HI	include/ssv6200_aux.h	16514;"	d
+RG_PABIAS_CTRL_I_MSK	include/ssv6200_aux.h	16512;"	d
+RG_PABIAS_CTRL_MSK	include/ssv6200_aux.h	16511;"	d
+RG_PABIAS_CTRL_SFT	include/ssv6200_aux.h	16513;"	d
+RG_PABIAS_CTRL_SZ	include/ssv6200_aux.h	16515;"	d
+RG_PACASCODE_CTRL_HI	include/ssv6200_aux.h	16574;"	d
+RG_PACASCODE_CTRL_I_MSK	include/ssv6200_aux.h	16572;"	d
+RG_PACASCODE_CTRL_MSK	include/ssv6200_aux.h	16571;"	d
+RG_PACASCODE_CTRL_SFT	include/ssv6200_aux.h	16573;"	d
+RG_PACASCODE_CTRL_SZ	include/ssv6200_aux.h	16575;"	d
+RG_PACELL_EN_HI	include/ssv6200_aux.h	16509;"	d
+RG_PACELL_EN_I_MSK	include/ssv6200_aux.h	16507;"	d
+RG_PACELL_EN_MSK	include/ssv6200_aux.h	16506;"	d
+RG_PACELL_EN_SFT	include/ssv6200_aux.h	16508;"	d
+RG_PACELL_EN_SZ	include/ssv6200_aux.h	16510;"	d
+RG_PACKET_STAT_EN_11B_HI	include/ssv6200_aux.h	14654;"	d
+RG_PACKET_STAT_EN_11B_I_MSK	include/ssv6200_aux.h	14652;"	d
+RG_PACKET_STAT_EN_11B_MSK	include/ssv6200_aux.h	14651;"	d
+RG_PACKET_STAT_EN_11B_RX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31854;"	d
+RG_PACKET_STAT_EN_11B_RX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31852;"	d
+RG_PACKET_STAT_EN_11B_RX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31851;"	d
+RG_PACKET_STAT_EN_11B_RX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31853;"	d
+RG_PACKET_STAT_EN_11B_RX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31855;"	d
+RG_PACKET_STAT_EN_11B_SFT	include/ssv6200_aux.h	14653;"	d
+RG_PACKET_STAT_EN_11B_SZ	include/ssv6200_aux.h	14655;"	d
+RG_PACKET_STAT_EN_11GN_HI	include/ssv6200_aux.h	15299;"	d
+RG_PACKET_STAT_EN_11GN_I_MSK	include/ssv6200_aux.h	15297;"	d
+RG_PACKET_STAT_EN_11GN_MSK	include/ssv6200_aux.h	15296;"	d
+RG_PACKET_STAT_EN_11GN_RX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32699;"	d
+RG_PACKET_STAT_EN_11GN_RX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32697;"	d
+RG_PACKET_STAT_EN_11GN_RX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32696;"	d
+RG_PACKET_STAT_EN_11GN_RX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32698;"	d
+RG_PACKET_STAT_EN_11GN_RX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32700;"	d
+RG_PACKET_STAT_EN_11GN_SFT	include/ssv6200_aux.h	15298;"	d
+RG_PACKET_STAT_EN_11GN_SZ	include/ssv6200_aux.h	15300;"	d
+RG_PACKET_STAT_EN_HI	include/ssv6200_aux.h	14699;"	d
+RG_PACKET_STAT_EN_I_MSK	include/ssv6200_aux.h	14697;"	d
+RG_PACKET_STAT_EN_MSK	include/ssv6200_aux.h	14696;"	d
+RG_PACKET_STAT_EN_SFT	include/ssv6200_aux.h	14698;"	d
+RG_PACKET_STAT_EN_SZ	include/ssv6200_aux.h	14700;"	d
+RG_PARALLEL_DR_16_HI	include/ssv6200_aux.h	13964;"	d
+RG_PARALLEL_DR_16_I_MSK	include/ssv6200_aux.h	13962;"	d
+RG_PARALLEL_DR_16_MSK	include/ssv6200_aux.h	13961;"	d
+RG_PARALLEL_DR_16_SFT	include/ssv6200_aux.h	13963;"	d
+RG_PARALLEL_DR_16_SZ	include/ssv6200_aux.h	13965;"	d
+RG_PARALLEL_DR_64_HI	include/ssv6200_aux.h	15154;"	d
+RG_PARALLEL_DR_64_I_MSK	include/ssv6200_aux.h	15152;"	d
+RG_PARALLEL_DR_64_MSK	include/ssv6200_aux.h	15151;"	d
+RG_PARALLEL_DR_64_SFT	include/ssv6200_aux.h	15153;"	d
+RG_PARALLEL_DR_64_SZ	include/ssv6200_aux.h	15155;"	d
+RG_PARALLEL_DR_80_HI	include/ssv6200_aux.h	15119;"	d
+RG_PARALLEL_DR_80_I_MSK	include/ssv6200_aux.h	15117;"	d
+RG_PARALLEL_DR_80_MSK	include/ssv6200_aux.h	15116;"	d
+RG_PARALLEL_DR_80_SFT	include/ssv6200_aux.h	15118;"	d
+RG_PARALLEL_DR_80_SZ	include/ssv6200_aux.h	15120;"	d
+RG_PA_FALL_TIME_HI	include/ssv6200_aux.h	13849;"	d
+RG_PA_FALL_TIME_I_MSK	include/ssv6200_aux.h	13847;"	d
+RG_PA_FALL_TIME_MSK	include/ssv6200_aux.h	13846;"	d
+RG_PA_FALL_TIME_SFT	include/ssv6200_aux.h	13848;"	d
+RG_PA_FALL_TIME_SZ	include/ssv6200_aux.h	13850;"	d
+RG_PA_RISE_TIME_HI	include/ssv6200_aux.h	13829;"	d
+RG_PA_RISE_TIME_I_MSK	include/ssv6200_aux.h	13827;"	d
+RG_PA_RISE_TIME_MSK	include/ssv6200_aux.h	13826;"	d
+RG_PA_RISE_TIME_SFT	include/ssv6200_aux.h	13828;"	d
+RG_PA_RISE_TIME_SZ	include/ssv6200_aux.h	13830;"	d
+RG_PDM_EDGE_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27839;"	d
+RG_PDM_EDGE_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27837;"	d
+RG_PDM_EDGE_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27836;"	d
+RG_PDM_EDGE_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27838;"	d
+RG_PDM_EDGE_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27840;"	d
+RG_PDM_HIGH_LEVEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27854;"	d
+RG_PDM_HIGH_LEVEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27852;"	d
+RG_PDM_HIGH_LEVEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27851;"	d
+RG_PDM_HIGH_LEVEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27853;"	d
+RG_PDM_HIGH_LEVEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27855;"	d
+RG_PDM_LOW_LEVEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27849;"	d
+RG_PDM_LOW_LEVEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27847;"	d
+RG_PDM_LOW_LEVEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27846;"	d
+RG_PDM_LOW_LEVEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27848;"	d
+RG_PDM_LOW_LEVEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27850;"	d
+RG_PEAK_IDX_CNT_SEL_HI	include/ssv6200_aux.h	14359;"	d
+RG_PEAK_IDX_CNT_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31544;"	d
+RG_PEAK_IDX_CNT_SEL_I_MSK	include/ssv6200_aux.h	14357;"	d
+RG_PEAK_IDX_CNT_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31542;"	d
+RG_PEAK_IDX_CNT_SEL_MSK	include/ssv6200_aux.h	14356;"	d
+RG_PEAK_IDX_CNT_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31541;"	d
+RG_PEAK_IDX_CNT_SEL_SFT	include/ssv6200_aux.h	14358;"	d
+RG_PEAK_IDX_CNT_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31543;"	d
+RG_PEAK_IDX_CNT_SEL_SZ	include/ssv6200_aux.h	14360;"	d
+RG_PEAK_IDX_CNT_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31545;"	d
+RG_PERIOD_MAX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32789;"	d
+RG_PERIOD_MAX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32787;"	d
+RG_PERIOD_MAX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32786;"	d
+RG_PERIOD_MAX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32788;"	d
+RG_PERIOD_MAX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32790;"	d
+RG_PERIOD_MIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32784;"	d
+RG_PERIOD_MIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32782;"	d
+RG_PERIOD_MIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32781;"	d
+RG_PERIOD_MIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32783;"	d
+RG_PERIOD_MIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32785;"	d
+RG_PGAGC_OW_HI	include/ssv6200_aux.h	13319;"	d
+RG_PGAGC_OW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30509;"	d
+RG_PGAGC_OW_I_MSK	include/ssv6200_aux.h	13317;"	d
+RG_PGAGC_OW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30507;"	d
+RG_PGAGC_OW_MSK	include/ssv6200_aux.h	13316;"	d
+RG_PGAGC_OW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30506;"	d
+RG_PGAGC_OW_SFT	include/ssv6200_aux.h	13318;"	d
+RG_PGAGC_OW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30508;"	d
+RG_PGAGC_OW_SZ	include/ssv6200_aux.h	13320;"	d
+RG_PGAGC_OW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30510;"	d
+RG_PGAGC_SET_HI	include/ssv6200_aux.h	13314;"	d
+RG_PGAGC_SET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30504;"	d
+RG_PGAGC_SET_I_MSK	include/ssv6200_aux.h	13312;"	d
+RG_PGAGC_SET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30502;"	d
+RG_PGAGC_SET_MSK	include/ssv6200_aux.h	13311;"	d
+RG_PGAGC_SET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30501;"	d
+RG_PGAGC_SET_SFT	include/ssv6200_aux.h	13313;"	d
+RG_PGAGC_SET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30503;"	d
+RG_PGAGC_SET_SZ	include/ssv6200_aux.h	13315;"	d
+RG_PGAGC_SET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30505;"	d
+RG_PGAG_DPDCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24744;"	d
+RG_PGAG_DPDCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24742;"	d
+RG_PGAG_DPDCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24741;"	d
+RG_PGAG_DPDCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24743;"	d
+RG_PGAG_DPDCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24745;"	d
+RG_PGAG_HI	include/ssv6200_aux.h	16094;"	d
+RG_PGAG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21624;"	d
+RG_PGAG_I_MSK	include/ssv6200_aux.h	16092;"	d
+RG_PGAG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21622;"	d
+RG_PGAG_MSK	include/ssv6200_aux.h	16091;"	d
+RG_PGAG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21621;"	d
+RG_PGAG_RCCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24709;"	d
+RG_PGAG_RCCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24707;"	d
+RG_PGAG_RCCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24706;"	d
+RG_PGAG_RCCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24708;"	d
+RG_PGAG_RCCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24710;"	d
+RG_PGAG_RXIQCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24729;"	d
+RG_PGAG_RXIQCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24727;"	d
+RG_PGAG_RXIQCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24726;"	d
+RG_PGAG_RXIQCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24728;"	d
+RG_PGAG_RXIQCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24730;"	d
+RG_PGAG_SFT	include/ssv6200_aux.h	16093;"	d
+RG_PGAG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21623;"	d
+RG_PGAG_SZ	include/ssv6200_aux.h	16095;"	d
+RG_PGAG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21625;"	d
+RG_PGAG_TXCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24714;"	d
+RG_PGAG_TXCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24712;"	d
+RG_PGAG_TXCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24711;"	d
+RG_PGAG_TXCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24713;"	d
+RG_PGAG_TXCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24715;"	d
+RG_PGA_REFDB_SAT_B_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30464;"	d
+RG_PGA_REFDB_SAT_B_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30462;"	d
+RG_PGA_REFDB_SAT_B_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30461;"	d
+RG_PGA_REFDB_SAT_B_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30463;"	d
+RG_PGA_REFDB_SAT_B_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30465;"	d
+RG_PGA_REFDB_SAT_GN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30484;"	d
+RG_PGA_REFDB_SAT_GN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30482;"	d
+RG_PGA_REFDB_SAT_GN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30481;"	d
+RG_PGA_REFDB_SAT_GN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30483;"	d
+RG_PGA_REFDB_SAT_GN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30485;"	d
+RG_PGA_REFDB_SAT_HI	include/ssv6200_aux.h	13294;"	d
+RG_PGA_REFDB_SAT_I_MSK	include/ssv6200_aux.h	13292;"	d
+RG_PGA_REFDB_SAT_MSK	include/ssv6200_aux.h	13291;"	d
+RG_PGA_REFDB_SAT_SFT	include/ssv6200_aux.h	13293;"	d
+RG_PGA_REFDB_SAT_SZ	include/ssv6200_aux.h	13295;"	d
+RG_PGA_REFDB_TOP_B_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30469;"	d
+RG_PGA_REFDB_TOP_B_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30467;"	d
+RG_PGA_REFDB_TOP_B_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30466;"	d
+RG_PGA_REFDB_TOP_B_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30468;"	d
+RG_PGA_REFDB_TOP_B_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30470;"	d
+RG_PGA_REFDB_TOP_GN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30489;"	d
+RG_PGA_REFDB_TOP_GN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30487;"	d
+RG_PGA_REFDB_TOP_GN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30486;"	d
+RG_PGA_REFDB_TOP_GN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30488;"	d
+RG_PGA_REFDB_TOP_GN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30490;"	d
+RG_PGA_REFDB_TOP_HI	include/ssv6200_aux.h	13299;"	d
+RG_PGA_REFDB_TOP_I_MSK	include/ssv6200_aux.h	13297;"	d
+RG_PGA_REFDB_TOP_MSK	include/ssv6200_aux.h	13296;"	d
+RG_PGA_REFDB_TOP_SFT	include/ssv6200_aux.h	13298;"	d
+RG_PGA_REFDB_TOP_SZ	include/ssv6200_aux.h	13300;"	d
+RG_PGA_REF_UND_B_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30474;"	d
+RG_PGA_REF_UND_B_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30472;"	d
+RG_PGA_REF_UND_B_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30471;"	d
+RG_PGA_REF_UND_B_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30473;"	d
+RG_PGA_REF_UND_B_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30475;"	d
+RG_PGA_REF_UND_GN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30494;"	d
+RG_PGA_REF_UND_GN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30492;"	d
+RG_PGA_REF_UND_GN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30491;"	d
+RG_PGA_REF_UND_GN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30493;"	d
+RG_PGA_REF_UND_GN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30495;"	d
+RG_PGA_REF_UND_HI	include/ssv6200_aux.h	13304;"	d
+RG_PGA_REF_UND_I_MSK	include/ssv6200_aux.h	13302;"	d
+RG_PGA_REF_UND_MSK	include/ssv6200_aux.h	13301;"	d
+RG_PGA_REF_UND_SFT	include/ssv6200_aux.h	13303;"	d
+RG_PGA_REF_UND_SZ	include/ssv6200_aux.h	13305;"	d
+RG_PHASE_17P5M_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27539;"	d
+RG_PHASE_17P5M_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27537;"	d
+RG_PHASE_17P5M_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27536;"	d
+RG_PHASE_17P5M_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27538;"	d
+RG_PHASE_17P5M_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27540;"	d
+RG_PHASE_1M_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27554;"	d
+RG_PHASE_1M_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27552;"	d
+RG_PHASE_1M_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27551;"	d
+RG_PHASE_1M_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27553;"	d
+RG_PHASE_1M_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27555;"	d
+RG_PHASE_2P5M_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27544;"	d
+RG_PHASE_2P5M_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27542;"	d
+RG_PHASE_2P5M_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27541;"	d
+RG_PHASE_2P5M_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27543;"	d
+RG_PHASE_2P5M_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27545;"	d
+RG_PHASE_35M_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27559;"	d
+RG_PHASE_35M_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27557;"	d
+RG_PHASE_35M_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27556;"	d
+RG_PHASE_35M_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27558;"	d
+RG_PHASE_35M_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27560;"	d
+RG_PHASE_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27464;"	d
+RG_PHASE_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27462;"	d
+RG_PHASE_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27461;"	d
+RG_PHASE_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27463;"	d
+RG_PHASE_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27465;"	d
+RG_PHASE_RND_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27654;"	d
+RG_PHASE_RND_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27652;"	d
+RG_PHASE_RND_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27651;"	d
+RG_PHASE_RND_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27653;"	d
+RG_PHASE_RND_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27655;"	d
+RG_PHASE_RXIQ_1M_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27549;"	d
+RG_PHASE_RXIQ_1M_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27547;"	d
+RG_PHASE_RXIQ_1M_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27546;"	d
+RG_PHASE_RXIQ_1M_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27548;"	d
+RG_PHASE_RXIQ_1M_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27550;"	d
+RG_PHASE_STEP_VALUE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27459;"	d
+RG_PHASE_STEP_VALUE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27457;"	d
+RG_PHASE_STEP_VALUE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27456;"	d
+RG_PHASE_STEP_VALUE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27458;"	d
+RG_PHASE_STEP_VALUE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27460;"	d
+RG_PHEST_EN_HI	include/ssv6200_aux.h	15569;"	d
+RG_PHEST_EN_I_MSK	include/ssv6200_aux.h	15567;"	d
+RG_PHEST_EN_MSK	include/ssv6200_aux.h	15566;"	d
+RG_PHEST_EN_SFT	include/ssv6200_aux.h	15568;"	d
+RG_PHEST_EN_SZ	include/ssv6200_aux.h	15570;"	d
+RG_PHEST_STBY_HI	include/ssv6200_aux.h	15564;"	d
+RG_PHEST_STBY_I_MSK	include/ssv6200_aux.h	15562;"	d
+RG_PHEST_STBY_MSK	include/ssv6200_aux.h	15561;"	d
+RG_PHEST_STBY_SFT	include/ssv6200_aux.h	15563;"	d
+RG_PHEST_STBY_SZ	include/ssv6200_aux.h	15565;"	d
+RG_PHY11BGN_MD_EN_HI	include/ssv6200_aux.h	13094;"	d
+RG_PHY11BGN_MD_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30299;"	d
+RG_PHY11BGN_MD_EN_I_MSK	include/ssv6200_aux.h	13092;"	d
+RG_PHY11BGN_MD_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30297;"	d
+RG_PHY11BGN_MD_EN_MSK	include/ssv6200_aux.h	13091;"	d
+RG_PHY11BGN_MD_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30296;"	d
+RG_PHY11BGN_MD_EN_SFT	include/ssv6200_aux.h	13093;"	d
+RG_PHY11BGN_MD_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30298;"	d
+RG_PHY11BGN_MD_EN_SZ	include/ssv6200_aux.h	13095;"	d
+RG_PHY11BGN_MD_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30300;"	d
+RG_PHY11B_MD_EN_HI	include/ssv6200_aux.h	13079;"	d
+RG_PHY11B_MD_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30284;"	d
+RG_PHY11B_MD_EN_I_MSK	include/ssv6200_aux.h	13077;"	d
+RG_PHY11B_MD_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30282;"	d
+RG_PHY11B_MD_EN_MSK	include/ssv6200_aux.h	13076;"	d
+RG_PHY11B_MD_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30281;"	d
+RG_PHY11B_MD_EN_SFT	include/ssv6200_aux.h	13078;"	d
+RG_PHY11B_MD_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30283;"	d
+RG_PHY11B_MD_EN_SZ	include/ssv6200_aux.h	13080;"	d
+RG_PHY11B_MD_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30285;"	d
+RG_PHY11GN_MD_EN_HI	include/ssv6200_aux.h	13074;"	d
+RG_PHY11GN_MD_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30279;"	d
+RG_PHY11GN_MD_EN_I_MSK	include/ssv6200_aux.h	13072;"	d
+RG_PHY11GN_MD_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30277;"	d
+RG_PHY11GN_MD_EN_MSK	include/ssv6200_aux.h	13071;"	d
+RG_PHY11GN_MD_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30276;"	d
+RG_PHY11GN_MD_EN_SFT	include/ssv6200_aux.h	13073;"	d
+RG_PHY11GN_MD_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30278;"	d
+RG_PHY11GN_MD_EN_SZ	include/ssv6200_aux.h	13075;"	d
+RG_PHY11GN_MD_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30280;"	d
+RG_PHYRXFIFO_MD_EN_HI	include/ssv6200_aux.h	13084;"	d
+RG_PHYRXFIFO_MD_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30289;"	d
+RG_PHYRXFIFO_MD_EN_I_MSK	include/ssv6200_aux.h	13082;"	d
+RG_PHYRXFIFO_MD_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30287;"	d
+RG_PHYRXFIFO_MD_EN_MSK	include/ssv6200_aux.h	13081;"	d
+RG_PHYRXFIFO_MD_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30286;"	d
+RG_PHYRXFIFO_MD_EN_SFT	include/ssv6200_aux.h	13083;"	d
+RG_PHYRXFIFO_MD_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30288;"	d
+RG_PHYRXFIFO_MD_EN_SZ	include/ssv6200_aux.h	13085;"	d
+RG_PHYRXFIFO_MD_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30290;"	d
+RG_PHYRX_MD_EN_HI	include/ssv6200_aux.h	13064;"	d
+RG_PHYRX_MD_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30269;"	d
+RG_PHYRX_MD_EN_I_MSK	include/ssv6200_aux.h	13062;"	d
+RG_PHYRX_MD_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30267;"	d
+RG_PHYRX_MD_EN_MSK	include/ssv6200_aux.h	13061;"	d
+RG_PHYRX_MD_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30266;"	d
+RG_PHYRX_MD_EN_SFT	include/ssv6200_aux.h	13063;"	d
+RG_PHYRX_MD_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30268;"	d
+RG_PHYRX_MD_EN_SZ	include/ssv6200_aux.h	13065;"	d
+RG_PHYRX_MD_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30270;"	d
+RG_PHYTXFIFO_MD_EN_HI	include/ssv6200_aux.h	13089;"	d
+RG_PHYTXFIFO_MD_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30294;"	d
+RG_PHYTXFIFO_MD_EN_I_MSK	include/ssv6200_aux.h	13087;"	d
+RG_PHYTXFIFO_MD_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30292;"	d
+RG_PHYTXFIFO_MD_EN_MSK	include/ssv6200_aux.h	13086;"	d
+RG_PHYTXFIFO_MD_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30291;"	d
+RG_PHYTXFIFO_MD_EN_SFT	include/ssv6200_aux.h	13088;"	d
+RG_PHYTXFIFO_MD_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30293;"	d
+RG_PHYTXFIFO_MD_EN_SZ	include/ssv6200_aux.h	13090;"	d
+RG_PHYTXFIFO_MD_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30295;"	d
+RG_PHYTX_MD_EN_HI	include/ssv6200_aux.h	13069;"	d
+RG_PHYTX_MD_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30274;"	d
+RG_PHYTX_MD_EN_I_MSK	include/ssv6200_aux.h	13067;"	d
+RG_PHYTX_MD_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30272;"	d
+RG_PHYTX_MD_EN_MSK	include/ssv6200_aux.h	13066;"	d
+RG_PHYTX_MD_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30271;"	d
+RG_PHYTX_MD_EN_SFT	include/ssv6200_aux.h	13068;"	d
+RG_PHYTX_MD_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30273;"	d
+RG_PHYTX_MD_EN_SZ	include/ssv6200_aux.h	13070;"	d
+RG_PHYTX_MD_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30275;"	d
+RG_PHY_IQ_TRIG_SEL_HI	include/ssv6200_aux.h	13119;"	d
+RG_PHY_IQ_TRIG_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30314;"	d
+RG_PHY_IQ_TRIG_SEL_I_MSK	include/ssv6200_aux.h	13117;"	d
+RG_PHY_IQ_TRIG_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30312;"	d
+RG_PHY_IQ_TRIG_SEL_MSK	include/ssv6200_aux.h	13116;"	d
+RG_PHY_IQ_TRIG_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30311;"	d
+RG_PHY_IQ_TRIG_SEL_SFT	include/ssv6200_aux.h	13118;"	d
+RG_PHY_IQ_TRIG_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30313;"	d
+RG_PHY_IQ_TRIG_SEL_SZ	include/ssv6200_aux.h	13120;"	d
+RG_PHY_IQ_TRIG_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30315;"	d
+RG_PHY_LPBK_HI	include/ssv6200_aux.h	8774;"	d
+RG_PHY_LPBK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8529;"	d
+RG_PHY_LPBK_I_MSK	include/ssv6200_aux.h	8772;"	d
+RG_PHY_LPBK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8527;"	d
+RG_PHY_LPBK_MSK	include/ssv6200_aux.h	8771;"	d
+RG_PHY_LPBK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8526;"	d
+RG_PHY_LPBK_SFT	include/ssv6200_aux.h	8773;"	d
+RG_PHY_LPBK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8528;"	d
+RG_PHY_LPBK_SZ	include/ssv6200_aux.h	8775;"	d
+RG_PHY_LPBK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8530;"	d
+RG_PHY_MD_EN_HI	include/ssv6200_aux.h	13059;"	d
+RG_PHY_MD_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30264;"	d
+RG_PHY_MD_EN_I_MSK	include/ssv6200_aux.h	13057;"	d
+RG_PHY_MD_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30262;"	d
+RG_PHY_MD_EN_MSK	include/ssv6200_aux.h	13056;"	d
+RG_PHY_MD_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30261;"	d
+RG_PHY_MD_EN_SFT	include/ssv6200_aux.h	13058;"	d
+RG_PHY_MD_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30263;"	d
+RG_PHY_MD_EN_SZ	include/ssv6200_aux.h	13060;"	d
+RG_PHY_MD_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30265;"	d
+RG_PHY_RST_N_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29844;"	d
+RG_PHY_RST_N_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29842;"	d
+RG_PHY_RST_N_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29841;"	d
+RG_PHY_RST_N_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29843;"	d
+RG_PHY_RST_N_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29845;"	d
+RG_PILOT_BNDRY_SHIFT_HI	include/ssv6200_aux.h	15024;"	d
+RG_PILOT_BNDRY_SHIFT_I_MSK	include/ssv6200_aux.h	15022;"	d
+RG_PILOT_BNDRY_SHIFT_MSK	include/ssv6200_aux.h	15021;"	d
+RG_PILOT_BNDRY_SHIFT_SFT	include/ssv6200_aux.h	15023;"	d
+RG_PILOT_BNDRY_SHIFT_SZ	include/ssv6200_aux.h	15025;"	d
+RG_PKT_MODE_HI	include/ssv6200_aux.h	13139;"	d
+RG_PKT_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30329;"	d
+RG_PKT_MODE_I_MSK	include/ssv6200_aux.h	13137;"	d
+RG_PKT_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30327;"	d
+RG_PKT_MODE_MSK	include/ssv6200_aux.h	13136;"	d
+RG_PKT_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30326;"	d
+RG_PKT_MODE_SFT	include/ssv6200_aux.h	13138;"	d
+RG_PKT_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30328;"	d
+RG_PKT_MODE_SZ	include/ssv6200_aux.h	13140;"	d
+RG_PKT_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30330;"	d
+RG_PMDLBK_HI	include/ssv6200_aux.h	12979;"	d
+RG_PMDLBK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30189;"	d
+RG_PMDLBK_I_MSK	include/ssv6200_aux.h	12977;"	d
+RG_PMDLBK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30187;"	d
+RG_PMDLBK_MSK	include/ssv6200_aux.h	12976;"	d
+RG_PMDLBK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30186;"	d
+RG_PMDLBK_SFT	include/ssv6200_aux.h	12978;"	d
+RG_PMDLBK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30188;"	d
+RG_PMDLBK_SZ	include/ssv6200_aux.h	12980;"	d
+RG_PMDLBK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30190;"	d
+RG_PMU_ENTER_SLEEP_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29764;"	d
+RG_PMU_ENTER_SLEEP_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29762;"	d
+RG_PMU_ENTER_SLEEP_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29761;"	d
+RG_PMU_ENTER_SLEEP_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29763;"	d
+RG_PMU_ENTER_SLEEP_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29765;"	d
+RG_POST_CLK_EN_HI	include/ssv6200_aux.h	15359;"	d
+RG_POST_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32749;"	d
+RG_POST_CLK_EN_I_MSK	include/ssv6200_aux.h	15357;"	d
+RG_POST_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32747;"	d
+RG_POST_CLK_EN_MSK	include/ssv6200_aux.h	15356;"	d
+RG_POST_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32746;"	d
+RG_POST_CLK_EN_SFT	include/ssv6200_aux.h	15358;"	d
+RG_POST_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32748;"	d
+RG_POST_CLK_EN_SZ	include/ssv6200_aux.h	15360;"	d
+RG_POST_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32750;"	d
+RG_POS_DES_11B_L_EXT_HI	include/ssv6200_aux.h	14324;"	d
+RG_POS_DES_11B_L_EXT_I_MSK	include/ssv6200_aux.h	14322;"	d
+RG_POS_DES_11B_L_EXT_MSK	include/ssv6200_aux.h	14321;"	d
+RG_POS_DES_11B_L_EXT_SFT	include/ssv6200_aux.h	14323;"	d
+RG_POS_DES_11B_L_EXT_SZ	include/ssv6200_aux.h	14325;"	d
+RG_POS_DES_11GN_L_EXT_HI	include/ssv6200_aux.h	14724;"	d
+RG_POS_DES_11GN_L_EXT_I_MSK	include/ssv6200_aux.h	14722;"	d
+RG_POS_DES_11GN_L_EXT_MSK	include/ssv6200_aux.h	14721;"	d
+RG_POS_DES_11GN_L_EXT_SFT	include/ssv6200_aux.h	14723;"	d
+RG_POS_DES_11GN_L_EXT_SZ	include/ssv6200_aux.h	14725;"	d
+RG_POS_DES_L_EXT_11B_RX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31509;"	d
+RG_POS_DES_L_EXT_11B_RX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31507;"	d
+RG_POS_DES_L_EXT_11B_RX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31506;"	d
+RG_POS_DES_L_EXT_11B_RX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31508;"	d
+RG_POS_DES_L_EXT_11B_RX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31510;"	d
+RG_POS_DES_L_EXT_11GN_RX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31989;"	d
+RG_POS_DES_L_EXT_11GN_RX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31987;"	d
+RG_POS_DES_L_EXT_11GN_RX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31986;"	d
+RG_POS_DES_L_EXT_11GN_RX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31988;"	d
+RG_POS_DES_L_EXT_11GN_RX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31990;"	d
+RG_POW16_CNT_TH_HI	include/ssv6200_aux.h	14959;"	d
+RG_POW16_CNT_TH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32379;"	d
+RG_POW16_CNT_TH_I_MSK	include/ssv6200_aux.h	14957;"	d
+RG_POW16_CNT_TH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32377;"	d
+RG_POW16_CNT_TH_MSK	include/ssv6200_aux.h	14956;"	d
+RG_POW16_CNT_TH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32376;"	d
+RG_POW16_CNT_TH_SFT	include/ssv6200_aux.h	14958;"	d
+RG_POW16_CNT_TH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32378;"	d
+RG_POW16_CNT_TH_SZ	include/ssv6200_aux.h	14960;"	d
+RG_POW16_CNT_TH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32380;"	d
+RG_POW16_SHORT_CNT_LMT_HI	include/ssv6200_aux.h	14964;"	d
+RG_POW16_SHORT_CNT_LMT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32384;"	d
+RG_POW16_SHORT_CNT_LMT_I_MSK	include/ssv6200_aux.h	14962;"	d
+RG_POW16_SHORT_CNT_LMT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32382;"	d
+RG_POW16_SHORT_CNT_LMT_MSK	include/ssv6200_aux.h	14961;"	d
+RG_POW16_SHORT_CNT_LMT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32381;"	d
+RG_POW16_SHORT_CNT_LMT_SFT	include/ssv6200_aux.h	14963;"	d
+RG_POW16_SHORT_CNT_LMT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32383;"	d
+RG_POW16_SHORT_CNT_LMT_SZ	include/ssv6200_aux.h	14965;"	d
+RG_POW16_SHORT_CNT_LMT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32385;"	d
+RG_POW16_TH_L_HI	include/ssv6200_aux.h	14969;"	d
+RG_POW16_TH_L_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32389;"	d
+RG_POW16_TH_L_I_MSK	include/ssv6200_aux.h	14967;"	d
+RG_POW16_TH_L_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32387;"	d
+RG_POW16_TH_L_MSK	include/ssv6200_aux.h	14966;"	d
+RG_POW16_TH_L_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32386;"	d
+RG_POW16_TH_L_SFT	include/ssv6200_aux.h	14968;"	d
+RG_POW16_TH_L_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32388;"	d
+RG_POW16_TH_L_SZ	include/ssv6200_aux.h	14970;"	d
+RG_POW16_TH_L_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32390;"	d
+RG_PRE_DC_AUTO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27644;"	d
+RG_PRE_DC_AUTO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27642;"	d
+RG_PRE_DC_AUTO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27641;"	d
+RG_PRE_DC_AUTO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27643;"	d
+RG_PRE_DC_AUTO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27645;"	d
+RG_PRE_DC_POLA_INV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27634;"	d
+RG_PRE_DC_POLA_INV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27632;"	d
+RG_PRE_DC_POLA_INV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27631;"	d
+RG_PRE_DC_POLA_INV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27633;"	d
+RG_PRE_DC_POLA_INV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27635;"	d
+RG_PRE_DES_11B_DLY_HI	include/ssv6200_aux.h	14329;"	d
+RG_PRE_DES_11B_DLY_I_MSK	include/ssv6200_aux.h	14327;"	d
+RG_PRE_DES_11B_DLY_MSK	include/ssv6200_aux.h	14326;"	d
+RG_PRE_DES_11B_DLY_SFT	include/ssv6200_aux.h	14328;"	d
+RG_PRE_DES_11B_DLY_SZ	include/ssv6200_aux.h	14330;"	d
+RG_PRE_DES_11GN_DLY_HI	include/ssv6200_aux.h	14729;"	d
+RG_PRE_DES_11GN_DLY_I_MSK	include/ssv6200_aux.h	14727;"	d
+RG_PRE_DES_11GN_DLY_MSK	include/ssv6200_aux.h	14726;"	d
+RG_PRE_DES_11GN_DLY_SFT	include/ssv6200_aux.h	14728;"	d
+RG_PRE_DES_11GN_DLY_SZ	include/ssv6200_aux.h	14730;"	d
+RG_PRE_DES_DLY_11B_RX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31514;"	d
+RG_PRE_DES_DLY_11B_RX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31512;"	d
+RG_PRE_DES_DLY_11B_RX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31511;"	d
+RG_PRE_DES_DLY_11B_RX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31513;"	d
+RG_PRE_DES_DLY_11B_RX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31515;"	d
+RG_PRE_DES_DLY_11GN_RX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31994;"	d
+RG_PRE_DES_DLY_11GN_RX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31992;"	d
+RG_PRE_DES_DLY_11GN_RX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31991;"	d
+RG_PRE_DES_DLY_11GN_RX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31993;"	d
+RG_PRE_DES_DLY_11GN_RX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31995;"	d
+RG_PRIMARY_CH_SIDE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30244;"	d
+RG_PRIMARY_CH_SIDE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30242;"	d
+RG_PRIMARY_CH_SIDE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30241;"	d
+RG_PRIMARY_CH_SIDE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30243;"	d
+RG_PRIMARY_CH_SIDE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30245;"	d
+RG_PRM_HI	include/ssv6200_aux.h	13149;"	d
+RG_PRM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30339;"	d
+RG_PRM_I_MSK	include/ssv6200_aux.h	13147;"	d
+RG_PRM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30337;"	d
+RG_PRM_MSK	include/ssv6200_aux.h	13146;"	d
+RG_PRM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30336;"	d
+RG_PRM_SFT	include/ssv6200_aux.h	13148;"	d
+RG_PRM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30338;"	d
+RG_PRM_SZ	include/ssv6200_aux.h	13150;"	d
+RG_PRM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30340;"	d
+RG_PROC_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27629;"	d
+RG_PROC_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27627;"	d
+RG_PROC_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27626;"	d
+RG_PROC_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27628;"	d
+RG_PROC_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27630;"	d
+RG_PSDU_TIME_OFFSET_11B_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31749;"	d
+RG_PSDU_TIME_OFFSET_11B_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31747;"	d
+RG_PSDU_TIME_OFFSET_11B_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31746;"	d
+RG_PSDU_TIME_OFFSET_11B_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31748;"	d
+RG_PSDU_TIME_OFFSET_11B_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31750;"	d
+RG_PSDU_TIME_OFFSET_GF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32574;"	d
+RG_PSDU_TIME_OFFSET_GF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32572;"	d
+RG_PSDU_TIME_OFFSET_GF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32571;"	d
+RG_PSDU_TIME_OFFSET_GF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32573;"	d
+RG_PSDU_TIME_OFFSET_GF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32575;"	d
+RG_PSDU_TIME_OFFSET_LEGACY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32584;"	d
+RG_PSDU_TIME_OFFSET_LEGACY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32582;"	d
+RG_PSDU_TIME_OFFSET_LEGACY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32581;"	d
+RG_PSDU_TIME_OFFSET_LEGACY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32583;"	d
+RG_PSDU_TIME_OFFSET_LEGACY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32585;"	d
+RG_PSDU_TIME_OFFSET_MF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32579;"	d
+RG_PSDU_TIME_OFFSET_MF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32577;"	d
+RG_PSDU_TIME_OFFSET_MF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32576;"	d
+RG_PSDU_TIME_OFFSET_MF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32578;"	d
+RG_PSDU_TIME_OFFSET_MF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32580;"	d
+RG_PULSE_NUMBER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32799;"	d
+RG_PULSE_NUMBER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32797;"	d
+RG_PULSE_NUMBER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32796;"	d
+RG_PULSE_NUMBER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32798;"	d
+RG_PULSE_NUMBER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32800;"	d
+RG_PWRON_DLY_TH_11B_HI	include/ssv6200_aux.h	14559;"	d
+RG_PWRON_DLY_TH_11B_I_MSK	include/ssv6200_aux.h	14557;"	d
+RG_PWRON_DLY_TH_11B_MSK	include/ssv6200_aux.h	14556;"	d
+RG_PWRON_DLY_TH_11B_RX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31724;"	d
+RG_PWRON_DLY_TH_11B_RX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31722;"	d
+RG_PWRON_DLY_TH_11B_RX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31721;"	d
+RG_PWRON_DLY_TH_11B_RX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31723;"	d
+RG_PWRON_DLY_TH_11B_RX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31725;"	d
+RG_PWRON_DLY_TH_11B_SFT	include/ssv6200_aux.h	14558;"	d
+RG_PWRON_DLY_TH_11B_SZ	include/ssv6200_aux.h	14560;"	d
+RG_PWRON_DLY_TH_11GN_HI	include/ssv6200_aux.h	14949;"	d
+RG_PWRON_DLY_TH_11GN_I_MSK	include/ssv6200_aux.h	14947;"	d
+RG_PWRON_DLY_TH_11GN_MSK	include/ssv6200_aux.h	14946;"	d
+RG_PWRON_DLY_TH_11GN_RX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32354;"	d
+RG_PWRON_DLY_TH_11GN_RX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32352;"	d
+RG_PWRON_DLY_TH_11GN_RX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32351;"	d
+RG_PWRON_DLY_TH_11GN_RX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32353;"	d
+RG_PWRON_DLY_TH_11GN_RX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32355;"	d
+RG_PWRON_DLY_TH_11GN_SFT	include/ssv6200_aux.h	14948;"	d
+RG_PWRON_DLY_TH_11GN_SZ	include/ssv6200_aux.h	14950;"	d
+RG_PWR_BIT_CNT_TH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31744;"	d
+RG_PWR_BIT_CNT_TH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31742;"	d
+RG_PWR_BIT_CNT_TH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31741;"	d
+RG_PWR_BIT_CNT_TH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31743;"	d
+RG_PWR_BIT_CNT_TH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31745;"	d
+RG_PWR_CNT_TH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31739;"	d
+RG_PWR_CNT_TH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31737;"	d
+RG_PWR_CNT_TH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31736;"	d
+RG_PWR_CNT_TH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31738;"	d
+RG_PWR_CNT_TH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31740;"	d
+RG_PWR_TH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31734;"	d
+RG_PWR_TH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31732;"	d
+RG_PWR_TH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31731;"	d
+RG_PWR_TH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31733;"	d
+RG_PWR_TH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31735;"	d
+RG_PW_CHIRP_MAX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32914;"	d
+RG_PW_CHIRP_MAX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32912;"	d
+RG_PW_CHIRP_MAX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32911;"	d
+RG_PW_CHIRP_MAX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32913;"	d
+RG_PW_CHIRP_MAX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32915;"	d
+RG_PW_CHIRP_MIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32909;"	d
+RG_PW_CHIRP_MIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32907;"	d
+RG_PW_CHIRP_MIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32906;"	d
+RG_PW_CHIRP_MIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32908;"	d
+RG_PW_CHIRP_MIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32910;"	d
+RG_PW_MAX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32779;"	d
+RG_PW_MAX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32777;"	d
+RG_PW_MAX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32776;"	d
+RG_PW_MAX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32778;"	d
+RG_PW_MAX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32780;"	d
+RG_PW_MIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32774;"	d
+RG_PW_MIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32772;"	d
+RG_PW_MIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32771;"	d
+RG_PW_MIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32773;"	d
+RG_PW_MIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32775;"	d
+RG_Q_INV_BB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30214;"	d
+RG_Q_INV_BB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30212;"	d
+RG_Q_INV_BB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30211;"	d
+RG_Q_INV_BB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30213;"	d
+RG_Q_INV_BB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30215;"	d
+RG_Q_INV_HI	include/ssv6200_aux.h	13004;"	d
+RG_Q_INV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27219;"	d
+RG_Q_INV_I_MSK	include/ssv6200_aux.h	13002;"	d
+RG_Q_INV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27217;"	d
+RG_Q_INV_MSK	include/ssv6200_aux.h	13001;"	d
+RG_Q_INV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27216;"	d
+RG_Q_INV_SFT	include/ssv6200_aux.h	13003;"	d
+RG_Q_INV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27218;"	d
+RG_Q_INV_SZ	include/ssv6200_aux.h	13005;"	d
+RG_Q_INV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27220;"	d
+RG_RADAR_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32814;"	d
+RG_RADAR_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32812;"	d
+RG_RADAR_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32811;"	d
+RG_RADAR_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32813;"	d
+RG_RADAR_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32815;"	d
+RG_RAM_00_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30109;"	d
+RG_RAM_00_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30107;"	d
+RG_RAM_00_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30106;"	d
+RG_RAM_00_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30108;"	d
+RG_RAM_00_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30110;"	d
+RG_RAM_01_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30114;"	d
+RG_RAM_01_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30112;"	d
+RG_RAM_01_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30111;"	d
+RG_RAM_01_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30113;"	d
+RG_RAM_01_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30115;"	d
+RG_RAM_02_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30119;"	d
+RG_RAM_02_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30117;"	d
+RG_RAM_02_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30116;"	d
+RG_RAM_02_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30118;"	d
+RG_RAM_02_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30120;"	d
+RG_RAM_03_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30124;"	d
+RG_RAM_03_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30122;"	d
+RG_RAM_03_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30121;"	d
+RG_RAM_03_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30123;"	d
+RG_RAM_03_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30125;"	d
+RG_RAM_04_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30129;"	d
+RG_RAM_04_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30127;"	d
+RG_RAM_04_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30126;"	d
+RG_RAM_04_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30128;"	d
+RG_RAM_04_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30130;"	d
+RG_RAM_05_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30134;"	d
+RG_RAM_05_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30132;"	d
+RG_RAM_05_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30131;"	d
+RG_RAM_05_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30133;"	d
+RG_RAM_05_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30135;"	d
+RG_RAM_06_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30139;"	d
+RG_RAM_06_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30137;"	d
+RG_RAM_06_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30136;"	d
+RG_RAM_06_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30138;"	d
+RG_RAM_06_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30140;"	d
+RG_RAM_07_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30144;"	d
+RG_RAM_07_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30142;"	d
+RG_RAM_07_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30141;"	d
+RG_RAM_07_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30143;"	d
+RG_RAM_07_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30145;"	d
+RG_RAM_08_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30149;"	d
+RG_RAM_08_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30147;"	d
+RG_RAM_08_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30146;"	d
+RG_RAM_08_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30148;"	d
+RG_RAM_08_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30150;"	d
+RG_RAM_09_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30154;"	d
+RG_RAM_09_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30152;"	d
+RG_RAM_09_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30151;"	d
+RG_RAM_09_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30153;"	d
+RG_RAM_09_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30155;"	d
+RG_RAM_10_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30159;"	d
+RG_RAM_10_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30157;"	d
+RG_RAM_10_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30156;"	d
+RG_RAM_10_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30158;"	d
+RG_RAM_10_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30160;"	d
+RG_RAM_11_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30164;"	d
+RG_RAM_11_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30162;"	d
+RG_RAM_11_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30161;"	d
+RG_RAM_11_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30163;"	d
+RG_RAM_11_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30165;"	d
+RG_RAM_12_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30169;"	d
+RG_RAM_12_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30167;"	d
+RG_RAM_12_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30166;"	d
+RG_RAM_12_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30168;"	d
+RG_RAM_12_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30170;"	d
+RG_RAM_13_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30174;"	d
+RG_RAM_13_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30172;"	d
+RG_RAM_13_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30171;"	d
+RG_RAM_13_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30173;"	d
+RG_RAM_13_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30175;"	d
+RG_RAM_14_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30179;"	d
+RG_RAM_14_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30177;"	d
+RG_RAM_14_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30176;"	d
+RG_RAM_14_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30178;"	d
+RG_RAM_14_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30180;"	d
+RG_RAM_15_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30184;"	d
+RG_RAM_15_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30182;"	d
+RG_RAM_15_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30181;"	d
+RG_RAM_15_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30183;"	d
+RG_RAM_15_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30185;"	d
+RG_RATE_HI	include/ssv6200_aux.h	13159;"	d
+RG_RATE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30349;"	d
+RG_RATE_I_MSK	include/ssv6200_aux.h	13157;"	d
+RG_RATE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30347;"	d
+RG_RATE_MCS_STAT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32694;"	d
+RG_RATE_MCS_STAT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32692;"	d
+RG_RATE_MCS_STAT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32691;"	d
+RG_RATE_MCS_STAT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32693;"	d
+RG_RATE_MCS_STAT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32695;"	d
+RG_RATE_MSK	include/ssv6200_aux.h	13156;"	d
+RG_RATE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30346;"	d
+RG_RATE_SFT	include/ssv6200_aux.h	13158;"	d
+RG_RATE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30348;"	d
+RG_RATE_STAT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31849;"	d
+RG_RATE_STAT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31847;"	d
+RG_RATE_STAT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31846;"	d
+RG_RATE_STAT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31848;"	d
+RG_RATE_STAT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31850;"	d
+RG_RATE_SZ	include/ssv6200_aux.h	13160;"	d
+RG_RATE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30350;"	d
+RG_RCAL_CODE_CWD_HI	include/ssv6200_aux.h	17494;"	d
+RG_RCAL_CODE_CWD_I_MSK	include/ssv6200_aux.h	17492;"	d
+RG_RCAL_CODE_CWD_MSK	include/ssv6200_aux.h	17491;"	d
+RG_RCAL_CODE_CWD_SFT	include/ssv6200_aux.h	17493;"	d
+RG_RCAL_CODE_CWD_SZ	include/ssv6200_aux.h	17495;"	d
+RG_RCAL_CODE_CWR_HI	include/ssv6200_aux.h	17489;"	d
+RG_RCAL_CODE_CWR_I_MSK	include/ssv6200_aux.h	17487;"	d
+RG_RCAL_CODE_CWR_MSK	include/ssv6200_aux.h	17486;"	d
+RG_RCAL_CODE_CWR_SFT	include/ssv6200_aux.h	17488;"	d
+RG_RCAL_CODE_CWR_SZ	include/ssv6200_aux.h	17490;"	d
+RG_RCAL_SPD_HI	include/ssv6200_aux.h	17479;"	d
+RG_RCAL_SPD_I_MSK	include/ssv6200_aux.h	17477;"	d
+RG_RCAL_SPD_MSK	include/ssv6200_aux.h	17476;"	d
+RG_RCAL_SPD_SFT	include/ssv6200_aux.h	17478;"	d
+RG_RCAL_SPD_SZ	include/ssv6200_aux.h	17480;"	d
+RG_RCAL_TMR_HI	include/ssv6200_aux.h	17484;"	d
+RG_RCAL_TMR_I_MSK	include/ssv6200_aux.h	17482;"	d
+RG_RCAL_TMR_MSK	include/ssv6200_aux.h	17481;"	d
+RG_RCAL_TMR_SFT	include/ssv6200_aux.h	17483;"	d
+RG_RCAL_TMR_SZ	include/ssv6200_aux.h	17485;"	d
+RG_RCCAL_DATA_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27659;"	d
+RG_RCCAL_DATA_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27657;"	d
+RG_RCCAL_DATA_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27656;"	d
+RG_RCCAL_DATA_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27658;"	d
+RG_RCCAL_DATA_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27660;"	d
+RG_RCCAL_POLAR_INV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27594;"	d
+RG_RCCAL_POLAR_INV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27592;"	d
+RG_RCCAL_POLAR_INV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27591;"	d
+RG_RCCAL_POLAR_INV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27593;"	d
+RG_RCCAL_POLAR_INV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27595;"	d
+RG_RDYACK_SEL_HI	include/ssv6200_aux.h	12984;"	d
+RG_RDYACK_SEL_I_MSK	include/ssv6200_aux.h	12982;"	d
+RG_RDYACK_SEL_MSK	include/ssv6200_aux.h	12981;"	d
+RG_RDYACK_SEL_SFT	include/ssv6200_aux.h	12983;"	d
+RG_RDYACK_SEL_SZ	include/ssv6200_aux.h	12985;"	d
+RG_REBOOT_HI	include/ssv6200_aux.h	139;"	d
+RG_REBOOT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1089;"	d
+RG_REBOOT_I_MSK	include/ssv6200_aux.h	137;"	d
+RG_REBOOT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1087;"	d
+RG_REBOOT_MSK	include/ssv6200_aux.h	136;"	d
+RG_REBOOT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1086;"	d
+RG_REBOOT_SFT	include/ssv6200_aux.h	138;"	d
+RG_REBOOT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1088;"	d
+RG_REBOOT_SZ	include/ssv6200_aux.h	140;"	d
+RG_REBOOT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1090;"	d
+RG_RESERVED_11B_RX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31754;"	d
+RG_RESERVED_11B_RX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31752;"	d
+RG_RESERVED_11B_RX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31751;"	d
+RG_RESERVED_11B_RX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31753;"	d
+RG_RESERVED_11B_RX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31755;"	d
+RG_RESERVED_11B_TX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31504;"	d
+RG_RESERVED_11B_TX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31502;"	d
+RG_RESERVED_11B_TX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31501;"	d
+RG_RESERVED_11B_TX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31503;"	d
+RG_RESERVED_11B_TX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31505;"	d
+RG_RESERVED_11GN_RX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31999;"	d
+RG_RESERVED_11GN_RX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31997;"	d
+RG_RESERVED_11GN_RX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31996;"	d
+RG_RESERVED_11GN_RX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31998;"	d
+RG_RESERVED_11GN_RX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32000;"	d
+RG_RESERVED_11GN_TX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31984;"	d
+RG_RESERVED_11GN_TX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31982;"	d
+RG_RESERVED_11GN_TX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31981;"	d
+RG_RESERVED_11GN_TX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31983;"	d
+RG_RESERVED_11GN_TX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31985;"	d
+RG_RESERVED_CMM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31474;"	d
+RG_RESERVED_CMM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31472;"	d
+RG_RESERVED_CMM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31471;"	d
+RG_RESERVED_CMM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31473;"	d
+RG_RESERVED_CMM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31475;"	d
+RG_RESERVED_DPD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29474;"	d
+RG_RESERVED_DPD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29472;"	d
+RG_RESERVED_DPD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29471;"	d
+RG_RESERVED_DPD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29473;"	d
+RG_RESERVED_DPD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29475;"	d
+RG_RFGC_OW_HI	include/ssv6200_aux.h	13329;"	d
+RG_RFGC_OW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30519;"	d
+RG_RFGC_OW_I_MSK	include/ssv6200_aux.h	13327;"	d
+RG_RFGC_OW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30517;"	d
+RG_RFGC_OW_MSK	include/ssv6200_aux.h	13326;"	d
+RG_RFGC_OW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30516;"	d
+RG_RFGC_OW_SFT	include/ssv6200_aux.h	13328;"	d
+RG_RFGC_OW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30518;"	d
+RG_RFGC_OW_SZ	include/ssv6200_aux.h	13330;"	d
+RG_RFGC_OW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30520;"	d
+RG_RFGC_SET_HI	include/ssv6200_aux.h	13324;"	d
+RG_RFGC_SET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30514;"	d
+RG_RFGC_SET_I_MSK	include/ssv6200_aux.h	13322;"	d
+RG_RFGC_SET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30512;"	d
+RG_RFGC_SET_MSK	include/ssv6200_aux.h	13321;"	d
+RG_RFGC_SET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30511;"	d
+RG_RFGC_SET_SFT	include/ssv6200_aux.h	13323;"	d
+RG_RFGC_SET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30513;"	d
+RG_RFGC_SET_SZ	include/ssv6200_aux.h	13325;"	d
+RG_RFGC_SET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30515;"	d
+RG_RFG_DPDCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24739;"	d
+RG_RFG_DPDCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24737;"	d
+RG_RFG_DPDCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24736;"	d
+RG_RFG_DPDCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24738;"	d
+RG_RFG_DPDCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24740;"	d
+RG_RFG_HI	include/ssv6200_aux.h	16089;"	d
+RG_RFG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21619;"	d
+RG_RFG_I_MSK	include/ssv6200_aux.h	16087;"	d
+RG_RFG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21617;"	d
+RG_RFG_MSK	include/ssv6200_aux.h	16086;"	d
+RG_RFG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21616;"	d
+RG_RFG_RXIQCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24724;"	d
+RG_RFG_RXIQCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24722;"	d
+RG_RFG_RXIQCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24721;"	d
+RG_RFG_RXIQCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24723;"	d
+RG_RFG_RXIQCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24725;"	d
+RG_RFG_SFT	include/ssv6200_aux.h	16088;"	d
+RG_RFG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21618;"	d
+RG_RFG_SZ	include/ssv6200_aux.h	16090;"	d
+RG_RFG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21620;"	d
+RG_RFTX_FALL_TIME_HI	include/ssv6200_aux.h	13854;"	d
+RG_RFTX_FALL_TIME_I_MSK	include/ssv6200_aux.h	13852;"	d
+RG_RFTX_FALL_TIME_MSK	include/ssv6200_aux.h	13851;"	d
+RG_RFTX_FALL_TIME_SFT	include/ssv6200_aux.h	13853;"	d
+RG_RFTX_FALL_TIME_SZ	include/ssv6200_aux.h	13855;"	d
+RG_RFTX_RISE_TIME_HI	include/ssv6200_aux.h	13834;"	d
+RG_RFTX_RISE_TIME_I_MSK	include/ssv6200_aux.h	13832;"	d
+RG_RFTX_RISE_TIME_MSK	include/ssv6200_aux.h	13831;"	d
+RG_RFTX_RISE_TIME_SFT	include/ssv6200_aux.h	13833;"	d
+RG_RFTX_RISE_TIME_SZ	include/ssv6200_aux.h	13835;"	d
+RG_RF_5G_BAND_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30239;"	d
+RG_RF_5G_BAND_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30237;"	d
+RG_RF_5G_BAND_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30236;"	d
+RG_RF_5G_BAND_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30238;"	d
+RG_RF_5G_BAND_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30240;"	d
+RG_RF_BB_CLK_SEL_HI	include/ssv6200_aux.h	13054;"	d
+RG_RF_BB_CLK_SEL_I_MSK	include/ssv6200_aux.h	13052;"	d
+RG_RF_BB_CLK_SEL_MSK	include/ssv6200_aux.h	13051;"	d
+RG_RF_BB_CLK_SEL_SFT	include/ssv6200_aux.h	13053;"	d
+RG_RF_BB_CLK_SEL_SZ	include/ssv6200_aux.h	13055;"	d
+RG_RF_D_REG_HI	include/ssv6200_aux.h	17654;"	d
+RG_RF_D_REG_I_MSK	include/ssv6200_aux.h	17652;"	d
+RG_RF_D_REG_MSK	include/ssv6200_aux.h	17651;"	d
+RG_RF_D_REG_SFT	include/ssv6200_aux.h	17653;"	d
+RG_RF_D_REG_SZ	include/ssv6200_aux.h	17655;"	d
+RG_RF_PWR_BARKER_CCK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31199;"	d
+RG_RF_PWR_BARKER_CCK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31197;"	d
+RG_RF_PWR_BARKER_CCK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31196;"	d
+RG_RF_PWR_BARKER_CCK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31198;"	d
+RG_RF_PWR_BARKER_CCK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31200;"	d
+RG_RF_PWR_HT20_16QAM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31234;"	d
+RG_RF_PWR_HT20_16QAM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31232;"	d
+RG_RF_PWR_HT20_16QAM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31231;"	d
+RG_RF_PWR_HT20_16QAM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31233;"	d
+RG_RF_PWR_HT20_16QAM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31235;"	d
+RG_RF_PWR_HT20_64QAM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31229;"	d
+RG_RF_PWR_HT20_64QAM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31227;"	d
+RG_RF_PWR_HT20_64QAM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31226;"	d
+RG_RF_PWR_HT20_64QAM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31228;"	d
+RG_RF_PWR_HT20_64QAM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31230;"	d
+RG_RF_PWR_HT20_BPSK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31244;"	d
+RG_RF_PWR_HT20_BPSK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31242;"	d
+RG_RF_PWR_HT20_BPSK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31241;"	d
+RG_RF_PWR_HT20_BPSK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31243;"	d
+RG_RF_PWR_HT20_BPSK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31245;"	d
+RG_RF_PWR_HT20_QPSK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31239;"	d
+RG_RF_PWR_HT20_QPSK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31237;"	d
+RG_RF_PWR_HT20_QPSK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31236;"	d
+RG_RF_PWR_HT20_QPSK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31238;"	d
+RG_RF_PWR_HT20_QPSK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31240;"	d
+RG_RF_PWR_HT40_16QAM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31254;"	d
+RG_RF_PWR_HT40_16QAM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31252;"	d
+RG_RF_PWR_HT40_16QAM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31251;"	d
+RG_RF_PWR_HT40_16QAM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31253;"	d
+RG_RF_PWR_HT40_16QAM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31255;"	d
+RG_RF_PWR_HT40_64QAM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31249;"	d
+RG_RF_PWR_HT40_64QAM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31247;"	d
+RG_RF_PWR_HT40_64QAM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31246;"	d
+RG_RF_PWR_HT40_64QAM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31248;"	d
+RG_RF_PWR_HT40_64QAM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31250;"	d
+RG_RF_PWR_HT40_BPSK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31264;"	d
+RG_RF_PWR_HT40_BPSK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31262;"	d
+RG_RF_PWR_HT40_BPSK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31261;"	d
+RG_RF_PWR_HT40_BPSK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31263;"	d
+RG_RF_PWR_HT40_BPSK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31265;"	d
+RG_RF_PWR_HT40_QPSK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31259;"	d
+RG_RF_PWR_HT40_QPSK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31257;"	d
+RG_RF_PWR_HT40_QPSK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31256;"	d
+RG_RF_PWR_HT40_QPSK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31258;"	d
+RG_RF_PWR_HT40_QPSK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31260;"	d
+RG_RF_PWR_LEGACY_16QAM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31214;"	d
+RG_RF_PWR_LEGACY_16QAM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31212;"	d
+RG_RF_PWR_LEGACY_16QAM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31211;"	d
+RG_RF_PWR_LEGACY_16QAM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31213;"	d
+RG_RF_PWR_LEGACY_16QAM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31215;"	d
+RG_RF_PWR_LEGACY_64QAM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31209;"	d
+RG_RF_PWR_LEGACY_64QAM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31207;"	d
+RG_RF_PWR_LEGACY_64QAM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31206;"	d
+RG_RF_PWR_LEGACY_64QAM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31208;"	d
+RG_RF_PWR_LEGACY_64QAM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31210;"	d
+RG_RF_PWR_LEGACY_BPSK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31224;"	d
+RG_RF_PWR_LEGACY_BPSK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31222;"	d
+RG_RF_PWR_LEGACY_BPSK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31221;"	d
+RG_RF_PWR_LEGACY_BPSK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31223;"	d
+RG_RF_PWR_LEGACY_BPSK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31225;"	d
+RG_RF_PWR_LEGACY_QPSK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31219;"	d
+RG_RF_PWR_LEGACY_QPSK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31217;"	d
+RG_RF_PWR_LEGACY_QPSK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31216;"	d
+RG_RF_PWR_LEGACY_QPSK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31218;"	d
+RG_RF_PWR_LEGACY_QPSK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31220;"	d
+RG_RF_PWR_MAN_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31204;"	d
+RG_RF_PWR_MAN_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31202;"	d
+RG_RF_PWR_MAN_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31201;"	d
+RG_RF_PWR_MAN_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31203;"	d
+RG_RF_PWR_MAN_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31205;"	d
+RG_RF_REF_SAT_B_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30479;"	d
+RG_RF_REF_SAT_B_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30477;"	d
+RG_RF_REF_SAT_B_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30476;"	d
+RG_RF_REF_SAT_B_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30478;"	d
+RG_RF_REF_SAT_B_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30480;"	d
+RG_RF_REF_SAT_GN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30499;"	d
+RG_RF_REF_SAT_GN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30497;"	d
+RG_RF_REF_SAT_GN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30496;"	d
+RG_RF_REF_SAT_GN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30498;"	d
+RG_RF_REF_SAT_GN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30500;"	d
+RG_RF_REF_SAT_HI	include/ssv6200_aux.h	13309;"	d
+RG_RF_REF_SAT_I_MSK	include/ssv6200_aux.h	13307;"	d
+RG_RF_REF_SAT_MSK	include/ssv6200_aux.h	13306;"	d
+RG_RF_REF_SAT_SFT	include/ssv6200_aux.h	13308;"	d
+RG_RF_REF_SAT_SZ	include/ssv6200_aux.h	13310;"	d
+RG_RIFS_EN_HI	include/ssv6200_aux.h	15309;"	d
+RG_RIFS_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32709;"	d
+RG_RIFS_EN_I_MSK	include/ssv6200_aux.h	15307;"	d
+RG_RIFS_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32707;"	d
+RG_RIFS_EN_MSK	include/ssv6200_aux.h	15306;"	d
+RG_RIFS_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32706;"	d
+RG_RIFS_EN_SFT	include/ssv6200_aux.h	15308;"	d
+RG_RIFS_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32708;"	d
+RG_RIFS_EN_SZ	include/ssv6200_aux.h	15310;"	d
+RG_RIFS_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32710;"	d
+RG_RSSIADC_RO_BIT_HI	include/ssv6200_aux.h	17619;"	d
+RG_RSSIADC_RO_BIT_I_MSK	include/ssv6200_aux.h	17617;"	d
+RG_RSSIADC_RO_BIT_MSK	include/ssv6200_aux.h	17616;"	d
+RG_RSSIADC_RO_BIT_SFT	include/ssv6200_aux.h	17618;"	d
+RG_RSSIADC_RO_BIT_SZ	include/ssv6200_aux.h	17620;"	d
+RG_RSSI_CLOCK_GATING_HI	include/ssv6200_aux.h	16479;"	d
+RG_RSSI_CLOCK_GATING_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22239;"	d
+RG_RSSI_CLOCK_GATING_I_MSK	include/ssv6200_aux.h	16477;"	d
+RG_RSSI_CLOCK_GATING_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22237;"	d
+RG_RSSI_CLOCK_GATING_MSK	include/ssv6200_aux.h	16476;"	d
+RG_RSSI_CLOCK_GATING_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22236;"	d
+RG_RSSI_CLOCK_GATING_SFT	include/ssv6200_aux.h	16478;"	d
+RG_RSSI_CLOCK_GATING_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22238;"	d
+RG_RSSI_CLOCK_GATING_SZ	include/ssv6200_aux.h	16480;"	d
+RG_RSSI_CLOCK_GATING_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22240;"	d
+RG_RSSI_EDGE_SEL_BB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30199;"	d
+RG_RSSI_EDGE_SEL_BB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30197;"	d
+RG_RSSI_EDGE_SEL_BB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30196;"	d
+RG_RSSI_EDGE_SEL_BB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30198;"	d
+RG_RSSI_EDGE_SEL_BB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30200;"	d
+RG_RSSI_EDGE_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27209;"	d
+RG_RSSI_EDGE_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27207;"	d
+RG_RSSI_EDGE_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27206;"	d
+RG_RSSI_EDGE_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27208;"	d
+RG_RSSI_EDGE_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27210;"	d
+RG_RSSI_INV_HI	include/ssv6200_aux.h	13774;"	d
+RG_RSSI_INV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30819;"	d
+RG_RSSI_INV_I_MSK	include/ssv6200_aux.h	13772;"	d
+RG_RSSI_INV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30817;"	d
+RG_RSSI_INV_MSK	include/ssv6200_aux.h	13771;"	d
+RG_RSSI_INV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30816;"	d
+RG_RSSI_INV_SFT	include/ssv6200_aux.h	13773;"	d
+RG_RSSI_INV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30818;"	d
+RG_RSSI_INV_SZ	include/ssv6200_aux.h	13775;"	d
+RG_RSSI_INV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30820;"	d
+RG_RSSI_OFFSET_HI	include/ssv6200_aux.h	13769;"	d
+RG_RSSI_OFFSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30814;"	d
+RG_RSSI_OFFSET_I_MSK	include/ssv6200_aux.h	13767;"	d
+RG_RSSI_OFFSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30812;"	d
+RG_RSSI_OFFSET_MSK	include/ssv6200_aux.h	13766;"	d
+RG_RSSI_OFFSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30811;"	d
+RG_RSSI_OFFSET_SFT	include/ssv6200_aux.h	13768;"	d
+RG_RSSI_OFFSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30813;"	d
+RG_RSSI_OFFSET_SZ	include/ssv6200_aux.h	13770;"	d
+RG_RSSI_OFFSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30815;"	d
+RG_RTC_CAL_MODE_HI	include/ssv6200_aux.h	16264;"	d
+RG_RTC_CAL_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29714;"	d
+RG_RTC_CAL_MODE_I_MSK	include/ssv6200_aux.h	16262;"	d
+RG_RTC_CAL_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29712;"	d
+RG_RTC_CAL_MODE_MSK	include/ssv6200_aux.h	16261;"	d
+RG_RTC_CAL_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29711;"	d
+RG_RTC_CAL_MODE_SFT	include/ssv6200_aux.h	16263;"	d
+RG_RTC_CAL_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29713;"	d
+RG_RTC_CAL_MODE_SZ	include/ssv6200_aux.h	16265;"	d
+RG_RTC_CAL_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29715;"	d
+RG_RTC_CAL_TARGET_COUNT_HI	include/ssv6200_aux.h	17649;"	d
+RG_RTC_CAL_TARGET_COUNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29704;"	d
+RG_RTC_CAL_TARGET_COUNT_I_MSK	include/ssv6200_aux.h	17647;"	d
+RG_RTC_CAL_TARGET_COUNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29702;"	d
+RG_RTC_CAL_TARGET_COUNT_MSK	include/ssv6200_aux.h	17646;"	d
+RG_RTC_CAL_TARGET_COUNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29701;"	d
+RG_RTC_CAL_TARGET_COUNT_SFT	include/ssv6200_aux.h	17648;"	d
+RG_RTC_CAL_TARGET_COUNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29703;"	d
+RG_RTC_CAL_TARGET_COUNT_SZ	include/ssv6200_aux.h	17650;"	d
+RG_RTC_CAL_TARGET_COUNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29705;"	d
+RG_RTC_DUMMIES_HI	include/ssv6200_aux.h	5924;"	d
+RG_RTC_DUMMIES_I_MSK	include/ssv6200_aux.h	5922;"	d
+RG_RTC_DUMMIES_MSK	include/ssv6200_aux.h	5921;"	d
+RG_RTC_DUMMIES_SFT	include/ssv6200_aux.h	5923;"	d
+RG_RTC_DUMMIES_SZ	include/ssv6200_aux.h	5925;"	d
+RG_RTC_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29789;"	d
+RG_RTC_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29787;"	d
+RG_RTC_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29786;"	d
+RG_RTC_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29788;"	d
+RG_RTC_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29790;"	d
+RG_RTC_INT_ALARM_MASK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29804;"	d
+RG_RTC_INT_ALARM_MASK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29802;"	d
+RG_RTC_INT_ALARM_MASK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29801;"	d
+RG_RTC_INT_ALARM_MASK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29803;"	d
+RG_RTC_INT_ALARM_MASK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29805;"	d
+RG_RTC_INT_SEC_MASK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29799;"	d
+RG_RTC_INT_SEC_MASK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29797;"	d
+RG_RTC_INT_SEC_MASK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29796;"	d
+RG_RTC_INT_SEC_MASK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29798;"	d
+RG_RTC_INT_SEC_MASK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29800;"	d
+RG_RTC_OFFSET_HI	include/ssv6200_aux.h	17644;"	d
+RG_RTC_OFFSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29699;"	d
+RG_RTC_OFFSET_I_MSK	include/ssv6200_aux.h	17642;"	d
+RG_RTC_OFFSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29697;"	d
+RG_RTC_OFFSET_MSK	include/ssv6200_aux.h	17641;"	d
+RG_RTC_OFFSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29696;"	d
+RG_RTC_OFFSET_SFT	include/ssv6200_aux.h	17643;"	d
+RG_RTC_OFFSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29698;"	d
+RG_RTC_OFFSET_SZ	include/ssv6200_aux.h	17645;"	d
+RG_RTC_OFFSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29700;"	d
+RG_RTC_OSC_RES_SW_HI	include/ssv6200_aux.h	5869;"	d
+RG_RTC_OSC_RES_SW_I_MSK	include/ssv6200_aux.h	5867;"	d
+RG_RTC_OSC_RES_SW_MANUAL_EN_HI	include/ssv6200_aux.h	5894;"	d
+RG_RTC_OSC_RES_SW_MANUAL_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29724;"	d
+RG_RTC_OSC_RES_SW_MANUAL_EN_I_MSK	include/ssv6200_aux.h	5892;"	d
+RG_RTC_OSC_RES_SW_MANUAL_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29722;"	d
+RG_RTC_OSC_RES_SW_MANUAL_EN_MSK	include/ssv6200_aux.h	5891;"	d
+RG_RTC_OSC_RES_SW_MANUAL_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29721;"	d
+RG_RTC_OSC_RES_SW_MANUAL_EN_SFT	include/ssv6200_aux.h	5893;"	d
+RG_RTC_OSC_RES_SW_MANUAL_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29723;"	d
+RG_RTC_OSC_RES_SW_MANUAL_EN_SZ	include/ssv6200_aux.h	5895;"	d
+RG_RTC_OSC_RES_SW_MANUAL_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29725;"	d
+RG_RTC_OSC_RES_SW_MANUAL_HI	include/ssv6200_aux.h	5864;"	d
+RG_RTC_OSC_RES_SW_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29709;"	d
+RG_RTC_OSC_RES_SW_MANUAL_I_MSK	include/ssv6200_aux.h	5862;"	d
+RG_RTC_OSC_RES_SW_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29707;"	d
+RG_RTC_OSC_RES_SW_MANUAL_MSK	include/ssv6200_aux.h	5861;"	d
+RG_RTC_OSC_RES_SW_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29706;"	d
+RG_RTC_OSC_RES_SW_MANUAL_SFT	include/ssv6200_aux.h	5863;"	d
+RG_RTC_OSC_RES_SW_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29708;"	d
+RG_RTC_OSC_RES_SW_MANUAL_SZ	include/ssv6200_aux.h	5865;"	d
+RG_RTC_OSC_RES_SW_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29710;"	d
+RG_RTC_OSC_RES_SW_MSK	include/ssv6200_aux.h	5866;"	d
+RG_RTC_OSC_RES_SW_SFT	include/ssv6200_aux.h	5868;"	d
+RG_RTC_OSC_RES_SW_SZ	include/ssv6200_aux.h	5870;"	d
+RG_RTC_RDY_DEGLITCH_TIMER_HI	include/ssv6200_aux.h	5899;"	d
+RG_RTC_RDY_DEGLITCH_TIMER_I_MSK	include/ssv6200_aux.h	5897;"	d
+RG_RTC_RDY_DEGLITCH_TIMER_MSK	include/ssv6200_aux.h	5896;"	d
+RG_RTC_RDY_DEGLITCH_TIMER_SFT	include/ssv6200_aux.h	5898;"	d
+RG_RTC_RDY_DEGLITCH_TIMER_SZ	include/ssv6200_aux.h	5900;"	d
+RG_RTC_RS1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29674;"	d
+RG_RTC_RS1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29672;"	d
+RG_RTC_RS1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29671;"	d
+RG_RTC_RS1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29673;"	d
+RG_RTC_RS1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29675;"	d
+RG_RTC_RS2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29679;"	d
+RG_RTC_RS2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29677;"	d
+RG_RTC_RS2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29676;"	d
+RG_RTC_RS2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29678;"	d
+RG_RTC_RS2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29680;"	d
+RG_RTC_SEC_ALARM_VALUE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29829;"	d
+RG_RTC_SEC_ALARM_VALUE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29827;"	d
+RG_RTC_SEC_ALARM_VALUE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29826;"	d
+RG_RTC_SEC_ALARM_VALUE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29828;"	d
+RG_RTC_SEC_ALARM_VALUE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29830;"	d
+RG_RTC_SEC_START_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29824;"	d
+RG_RTC_SEC_START_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29822;"	d
+RG_RTC_SEC_START_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29821;"	d
+RG_RTC_SEC_START_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29823;"	d
+RG_RTC_SEC_START_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29825;"	d
+RG_RXAGC_OW_HI	include/ssv6200_aux.h	13344;"	d
+RG_RXAGC_OW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30534;"	d
+RG_RXAGC_OW_I_MSK	include/ssv6200_aux.h	13342;"	d
+RG_RXAGC_OW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30532;"	d
+RG_RXAGC_OW_MSK	include/ssv6200_aux.h	13341;"	d
+RG_RXAGC_OW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30531;"	d
+RG_RXAGC_OW_SFT	include/ssv6200_aux.h	13343;"	d
+RG_RXAGC_OW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30533;"	d
+RG_RXAGC_OW_SZ	include/ssv6200_aux.h	13345;"	d
+RG_RXAGC_OW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30535;"	d
+RG_RXAGC_SET_HI	include/ssv6200_aux.h	13339;"	d
+RG_RXAGC_SET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30529;"	d
+RG_RXAGC_SET_I_MSK	include/ssv6200_aux.h	13337;"	d
+RG_RXAGC_SET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30527;"	d
+RG_RXAGC_SET_MSK	include/ssv6200_aux.h	13336;"	d
+RG_RXAGC_SET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30526;"	d
+RG_RXAGC_SET_SFT	include/ssv6200_aux.h	13338;"	d
+RG_RXAGC_SET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30528;"	d
+RG_RXAGC_SET_SZ	include/ssv6200_aux.h	13340;"	d
+RG_RXAGC_SET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30530;"	d
+RG_RXIQ_EMU_IDX_HI	include/ssv6200_aux.h	15729;"	d
+RG_RXIQ_EMU_IDX_I_MSK	include/ssv6200_aux.h	15727;"	d
+RG_RXIQ_EMU_IDX_MSK	include/ssv6200_aux.h	15726;"	d
+RG_RXIQ_EMU_IDX_SFT	include/ssv6200_aux.h	15728;"	d
+RG_RXIQ_EMU_IDX_SZ	include/ssv6200_aux.h	15730;"	d
+RG_RXIQ_NOSHRINK_HI	include/ssv6200_aux.h	15509;"	d
+RG_RXIQ_NOSHRINK_I_MSK	include/ssv6200_aux.h	15507;"	d
+RG_RXIQ_NOSHRINK_MSK	include/ssv6200_aux.h	15506;"	d
+RG_RXIQ_NOSHRINK_SFT	include/ssv6200_aux.h	15508;"	d
+RG_RXIQ_NOSHRINK_SZ	include/ssv6200_aux.h	15510;"	d
+RG_RXIQ_NOSHRK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27194;"	d
+RG_RXIQ_NOSHRK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27192;"	d
+RG_RXIQ_NOSHRK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27191;"	d
+RG_RXIQ_NOSHRK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27193;"	d
+RG_RXIQ_NOSHRK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27195;"	d
+RG_RXRF_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24624;"	d
+RG_RXRF_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24622;"	d
+RG_RXRF_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24621;"	d
+RG_RXRF_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24623;"	d
+RG_RXRF_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24625;"	d
+RG_RXRF_R2T_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24669;"	d
+RG_RXRF_R2T_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24667;"	d
+RG_RXRF_R2T_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24666;"	d
+RG_RXRF_R2T_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24668;"	d
+RG_RXRF_R2T_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24670;"	d
+RG_RXRF_T2R_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24649;"	d
+RG_RXRF_T2R_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24647;"	d
+RG_RXRF_T2R_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24646;"	d
+RG_RXRF_T2R_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24648;"	d
+RG_RXRF_T2R_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24650;"	d
+RG_RX_ABBCFIX_HI	include/ssv6200_aux.h	16339;"	d
+RG_RX_ABBCFIX_I_MSK	include/ssv6200_aux.h	16337;"	d
+RG_RX_ABBCFIX_MSK	include/ssv6200_aux.h	16336;"	d
+RG_RX_ABBCFIX_SFT	include/ssv6200_aux.h	16338;"	d
+RG_RX_ABBCFIX_SZ	include/ssv6200_aux.h	16340;"	d
+RG_RX_ABBCTUNE_HI	include/ssv6200_aux.h	16344;"	d
+RG_RX_ABBCTUNE_I_MSK	include/ssv6200_aux.h	16342;"	d
+RG_RX_ABBCTUNE_MSK	include/ssv6200_aux.h	16341;"	d
+RG_RX_ABBCTUNE_SFT	include/ssv6200_aux.h	16343;"	d
+RG_RX_ABBCTUNE_SZ	include/ssv6200_aux.h	16345;"	d
+RG_RX_ABBOUT_TRI_STATE_HI	include/ssv6200_aux.h	16349;"	d
+RG_RX_ABBOUT_TRI_STATE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21904;"	d
+RG_RX_ABBOUT_TRI_STATE_I_MSK	include/ssv6200_aux.h	16347;"	d
+RG_RX_ABBOUT_TRI_STATE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21902;"	d
+RG_RX_ABBOUT_TRI_STATE_MSK	include/ssv6200_aux.h	16346;"	d
+RG_RX_ABBOUT_TRI_STATE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21901;"	d
+RG_RX_ABBOUT_TRI_STATE_SFT	include/ssv6200_aux.h	16348;"	d
+RG_RX_ABBOUT_TRI_STATE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21903;"	d
+RG_RX_ABBOUT_TRI_STATE_SZ	include/ssv6200_aux.h	16350;"	d
+RG_RX_ABBOUT_TRI_STATE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21905;"	d
+RG_RX_ABB_N_MODE_HI	include/ssv6200_aux.h	16354;"	d
+RG_RX_ABB_N_MODE_I_MSK	include/ssv6200_aux.h	16352;"	d
+RG_RX_ABB_N_MODE_MSK	include/ssv6200_aux.h	16351;"	d
+RG_RX_ABB_N_MODE_SFT	include/ssv6200_aux.h	16353;"	d
+RG_RX_ABB_N_MODE_SZ	include/ssv6200_aux.h	16355;"	d
+RG_RX_ADCRSSI_CLKSEL_HI	include/ssv6200_aux.h	16464;"	d
+RG_RX_ADCRSSI_CLKSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22234;"	d
+RG_RX_ADCRSSI_CLKSEL_I_MSK	include/ssv6200_aux.h	16462;"	d
+RG_RX_ADCRSSI_CLKSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22232;"	d
+RG_RX_ADCRSSI_CLKSEL_MSK	include/ssv6200_aux.h	16461;"	d
+RG_RX_ADCRSSI_CLKSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22231;"	d
+RG_RX_ADCRSSI_CLKSEL_SFT	include/ssv6200_aux.h	16463;"	d
+RG_RX_ADCRSSI_CLKSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22233;"	d
+RG_RX_ADCRSSI_CLKSEL_SZ	include/ssv6200_aux.h	16465;"	d
+RG_RX_ADCRSSI_CLKSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22235;"	d
+RG_RX_ADCRSSI_VCM_HI	include/ssv6200_aux.h	16469;"	d
+RG_RX_ADCRSSI_VCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22224;"	d
+RG_RX_ADCRSSI_VCM_I_MSK	include/ssv6200_aux.h	16467;"	d
+RG_RX_ADCRSSI_VCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22222;"	d
+RG_RX_ADCRSSI_VCM_MSK	include/ssv6200_aux.h	16466;"	d
+RG_RX_ADCRSSI_VCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22221;"	d
+RG_RX_ADCRSSI_VCM_SFT	include/ssv6200_aux.h	16468;"	d
+RG_RX_ADCRSSI_VCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22223;"	d
+RG_RX_ADCRSSI_VCM_SZ	include/ssv6200_aux.h	16470;"	d
+RG_RX_ADCRSSI_VCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22225;"	d
+RG_RX_ADC_CLKSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22879;"	d
+RG_RX_ADC_CLKSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22877;"	d
+RG_RX_ADC_CLKSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22876;"	d
+RG_RX_ADC_CLKSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22878;"	d
+RG_RX_ADC_CLKSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22880;"	d
+RG_RX_ADC_DNLEN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22884;"	d
+RG_RX_ADC_DNLEN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22882;"	d
+RG_RX_ADC_DNLEN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22881;"	d
+RG_RX_ADC_DNLEN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22883;"	d
+RG_RX_ADC_DNLEN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22885;"	d
+RG_RX_ADC_I_RO_BIT_HI	include/ssv6200_aux.h	17624;"	d
+RG_RX_ADC_I_RO_BIT_I_MSK	include/ssv6200_aux.h	17622;"	d
+RG_RX_ADC_I_RO_BIT_MSK	include/ssv6200_aux.h	17621;"	d
+RG_RX_ADC_I_RO_BIT_SFT	include/ssv6200_aux.h	17623;"	d
+RG_RX_ADC_I_RO_BIT_SZ	include/ssv6200_aux.h	17625;"	d
+RG_RX_ADC_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21714;"	d
+RG_RX_ADC_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21712;"	d
+RG_RX_ADC_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21711;"	d
+RG_RX_ADC_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21713;"	d
+RG_RX_ADC_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21715;"	d
+RG_RX_ADC_METAEN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22889;"	d
+RG_RX_ADC_METAEN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22887;"	d
+RG_RX_ADC_METAEN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22886;"	d
+RG_RX_ADC_METAEN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22888;"	d
+RG_RX_ADC_METAEN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22890;"	d
+RG_RX_ADC_Q_RO_BIT_HI	include/ssv6200_aux.h	17629;"	d
+RG_RX_ADC_Q_RO_BIT_I_MSK	include/ssv6200_aux.h	17627;"	d
+RG_RX_ADC_Q_RO_BIT_MSK	include/ssv6200_aux.h	17626;"	d
+RG_RX_ADC_Q_RO_BIT_SFT	include/ssv6200_aux.h	17628;"	d
+RG_RX_ADC_Q_RO_BIT_SZ	include/ssv6200_aux.h	17630;"	d
+RG_RX_ADC_TFLAG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22894;"	d
+RG_RX_ADC_TFLAG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22892;"	d
+RG_RX_ADC_TFLAG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22891;"	d
+RG_RX_ADC_TFLAG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22893;"	d
+RG_RX_ADC_TFLAG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22895;"	d
+RG_RX_ADC_TSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22899;"	d
+RG_RX_ADC_TSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22897;"	d
+RG_RX_ADC_TSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22896;"	d
+RG_RX_ADC_TSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22898;"	d
+RG_RX_ADC_TSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22900;"	d
+RG_RX_AGC_HI	include/ssv6200_aux.h	16079;"	d
+RG_RX_AGC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21604;"	d
+RG_RX_AGC_I_MSK	include/ssv6200_aux.h	16077;"	d
+RG_RX_AGC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21602;"	d
+RG_RX_AGC_MSK	include/ssv6200_aux.h	16076;"	d
+RG_RX_AGC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21601;"	d
+RG_RX_AGC_SFT	include/ssv6200_aux.h	16078;"	d
+RG_RX_AGC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21603;"	d
+RG_RX_AGC_SZ	include/ssv6200_aux.h	16080;"	d
+RG_RX_AGC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21605;"	d
+RG_RX_BEACON_CRC_BYPASS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31304;"	d
+RG_RX_BEACON_CRC_BYPASS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31302;"	d
+RG_RX_BEACON_CRC_BYPASS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31301;"	d
+RG_RX_BEACON_CRC_BYPASS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31303;"	d
+RG_RX_BEACON_CRC_BYPASS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31305;"	d
+RG_RX_BEACON_INTERVAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31309;"	d
+RG_RX_BEACON_INTERVAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31307;"	d
+RG_RX_BEACON_INTERVAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31306;"	d
+RG_RX_BEACON_INTERVAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31308;"	d
+RG_RX_BEACON_INTERVAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31310;"	d
+RG_RX_BEACON_LOSS_CNT_LMT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31299;"	d
+RG_RX_BEACON_LOSS_CNT_LMT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31297;"	d
+RG_RX_BEACON_LOSS_CNT_LMT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31296;"	d
+RG_RX_BEACON_LOSS_CNT_LMT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31298;"	d
+RG_RX_BEACON_LOSS_CNT_LMT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31300;"	d
+RG_RX_BEACON_TU_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31289;"	d
+RG_RX_BEACON_TU_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31287;"	d
+RG_RX_BEACON_TU_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31286;"	d
+RG_RX_BEACON_TU_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31288;"	d
+RG_RX_BEACON_TU_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31290;"	d
+RG_RX_DC_POLAR_INV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27589;"	d
+RG_RX_DC_POLAR_INV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27587;"	d
+RG_RX_DC_POLAR_INV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27586;"	d
+RG_RX_DC_POLAR_INV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27588;"	d
+RG_RX_DC_POLAR_INV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27590;"	d
+RG_RX_DC_RESOLUTION_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27599;"	d
+RG_RX_DC_RESOLUTION_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27597;"	d
+RG_RX_DC_RESOLUTION_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27596;"	d
+RG_RX_DC_RESOLUTION_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27598;"	d
+RG_RX_DC_RESOLUTION_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27600;"	d
+RG_RX_DES_LEN_LO_HI	include/ssv6200_aux.h	13649;"	d
+RG_RX_DES_LEN_LO_I_MSK	include/ssv6200_aux.h	13647;"	d
+RG_RX_DES_LEN_LO_MSK	include/ssv6200_aux.h	13646;"	d
+RG_RX_DES_LEN_LO_SFT	include/ssv6200_aux.h	13648;"	d
+RG_RX_DES_LEN_LO_SZ	include/ssv6200_aux.h	13650;"	d
+RG_RX_DES_LEN_UP_HI	include/ssv6200_aux.h	13654;"	d
+RG_RX_DES_LEN_UP_I_MSK	include/ssv6200_aux.h	13652;"	d
+RG_RX_DES_LEN_UP_MSK	include/ssv6200_aux.h	13651;"	d
+RG_RX_DES_LEN_UP_SFT	include/ssv6200_aux.h	13653;"	d
+RG_RX_DES_LEN_UP_SZ	include/ssv6200_aux.h	13655;"	d
+RG_RX_DES_L_LEN_LO_HI	include/ssv6200_aux.h	13664;"	d
+RG_RX_DES_L_LEN_LO_I_MSK	include/ssv6200_aux.h	13662;"	d
+RG_RX_DES_L_LEN_LO_MSK	include/ssv6200_aux.h	13661;"	d
+RG_RX_DES_L_LEN_LO_SFT	include/ssv6200_aux.h	13663;"	d
+RG_RX_DES_L_LEN_LO_SZ	include/ssv6200_aux.h	13665;"	d
+RG_RX_DES_L_LEN_UP_COMB_HI	include/ssv6200_aux.h	13679;"	d
+RG_RX_DES_L_LEN_UP_COMB_I_MSK	include/ssv6200_aux.h	13677;"	d
+RG_RX_DES_L_LEN_UP_COMB_MSK	include/ssv6200_aux.h	13676;"	d
+RG_RX_DES_L_LEN_UP_COMB_SFT	include/ssv6200_aux.h	13678;"	d
+RG_RX_DES_L_LEN_UP_COMB_SZ	include/ssv6200_aux.h	13680;"	d
+RG_RX_DES_L_LEN_UP_HI	include/ssv6200_aux.h	13669;"	d
+RG_RX_DES_L_LEN_UP_I_MSK	include/ssv6200_aux.h	13667;"	d
+RG_RX_DES_L_LEN_UP_MSK	include/ssv6200_aux.h	13666;"	d
+RG_RX_DES_L_LEN_UP_SFT	include/ssv6200_aux.h	13668;"	d
+RG_RX_DES_L_LEN_UP_SZ	include/ssv6200_aux.h	13670;"	d
+RG_RX_DES_MODE_COMB_HI	include/ssv6200_aux.h	13694;"	d
+RG_RX_DES_MODE_COMB_I_MSK	include/ssv6200_aux.h	13692;"	d
+RG_RX_DES_MODE_COMB_MSK	include/ssv6200_aux.h	13691;"	d
+RG_RX_DES_MODE_COMB_SFT	include/ssv6200_aux.h	13693;"	d
+RG_RX_DES_MODE_COMB_SZ	include/ssv6200_aux.h	13695;"	d
+RG_RX_DES_MODE_HI	include/ssv6200_aux.h	13644;"	d
+RG_RX_DES_MODE_I_MSK	include/ssv6200_aux.h	13642;"	d
+RG_RX_DES_MODE_MSK	include/ssv6200_aux.h	13641;"	d
+RG_RX_DES_MODE_SFT	include/ssv6200_aux.h	13643;"	d
+RG_RX_DES_MODE_SZ	include/ssv6200_aux.h	13645;"	d
+RG_RX_DES_RATE_COMB_HI	include/ssv6200_aux.h	13689;"	d
+RG_RX_DES_RATE_COMB_I_MSK	include/ssv6200_aux.h	13687;"	d
+RG_RX_DES_RATE_COMB_MSK	include/ssv6200_aux.h	13686;"	d
+RG_RX_DES_RATE_COMB_SFT	include/ssv6200_aux.h	13688;"	d
+RG_RX_DES_RATE_COMB_SZ	include/ssv6200_aux.h	13690;"	d
+RG_RX_DES_RATE_HI	include/ssv6200_aux.h	13639;"	d
+RG_RX_DES_RATE_I_MSK	include/ssv6200_aux.h	13637;"	d
+RG_RX_DES_RATE_MSK	include/ssv6200_aux.h	13636;"	d
+RG_RX_DES_RATE_SFT	include/ssv6200_aux.h	13638;"	d
+RG_RX_DES_RATE_SZ	include/ssv6200_aux.h	13640;"	d
+RG_RX_DES_RCPI_GN_HI	include/ssv6200_aux.h	13759;"	d
+RG_RX_DES_RCPI_GN_I_MSK	include/ssv6200_aux.h	13757;"	d
+RG_RX_DES_RCPI_GN_MSK	include/ssv6200_aux.h	13756;"	d
+RG_RX_DES_RCPI_GN_SFT	include/ssv6200_aux.h	13758;"	d
+RG_RX_DES_RCPI_GN_SZ	include/ssv6200_aux.h	13760;"	d
+RG_RX_DES_RCPI_HI	include/ssv6200_aux.h	13704;"	d
+RG_RX_DES_RCPI_I_MSK	include/ssv6200_aux.h	13702;"	d
+RG_RX_DES_RCPI_MSK	include/ssv6200_aux.h	13701;"	d
+RG_RX_DES_RCPI_SFT	include/ssv6200_aux.h	13703;"	d
+RG_RX_DES_RCPI_SZ	include/ssv6200_aux.h	13705;"	d
+RG_RX_DES_SNR_GN_HI	include/ssv6200_aux.h	13754;"	d
+RG_RX_DES_SNR_GN_I_MSK	include/ssv6200_aux.h	13752;"	d
+RG_RX_DES_SNR_GN_MSK	include/ssv6200_aux.h	13751;"	d
+RG_RX_DES_SNR_GN_SFT	include/ssv6200_aux.h	13753;"	d
+RG_RX_DES_SNR_GN_SZ	include/ssv6200_aux.h	13755;"	d
+RG_RX_DES_SNR_HI	include/ssv6200_aux.h	13699;"	d
+RG_RX_DES_SNR_I_MSK	include/ssv6200_aux.h	13697;"	d
+RG_RX_DES_SNR_MSK	include/ssv6200_aux.h	13696;"	d
+RG_RX_DES_SNR_SFT	include/ssv6200_aux.h	13698;"	d
+RG_RX_DES_SNR_SZ	include/ssv6200_aux.h	13700;"	d
+RG_RX_DES_SRVC_LO_HI	include/ssv6200_aux.h	13709;"	d
+RG_RX_DES_SRVC_LO_I_MSK	include/ssv6200_aux.h	13707;"	d
+RG_RX_DES_SRVC_LO_MSK	include/ssv6200_aux.h	13706;"	d
+RG_RX_DES_SRVC_LO_SFT	include/ssv6200_aux.h	13708;"	d
+RG_RX_DES_SRVC_LO_SZ	include/ssv6200_aux.h	13710;"	d
+RG_RX_DES_SRVC_UP_HI	include/ssv6200_aux.h	13659;"	d
+RG_RX_DES_SRVC_UP_I_MSK	include/ssv6200_aux.h	13657;"	d
+RG_RX_DES_SRVC_UP_MSK	include/ssv6200_aux.h	13656;"	d
+RG_RX_DES_SRVC_UP_SFT	include/ssv6200_aux.h	13658;"	d
+RG_RX_DES_SRVC_UP_SZ	include/ssv6200_aux.h	13660;"	d
+RG_RX_DES_TYPE_COMB_HI	include/ssv6200_aux.h	13684;"	d
+RG_RX_DES_TYPE_COMB_I_MSK	include/ssv6200_aux.h	13682;"	d
+RG_RX_DES_TYPE_COMB_MSK	include/ssv6200_aux.h	13681;"	d
+RG_RX_DES_TYPE_COMB_SFT	include/ssv6200_aux.h	13683;"	d
+RG_RX_DES_TYPE_COMB_SZ	include/ssv6200_aux.h	13685;"	d
+RG_RX_DES_TYPE_HI	include/ssv6200_aux.h	13674;"	d
+RG_RX_DES_TYPE_I_MSK	include/ssv6200_aux.h	13672;"	d
+RG_RX_DES_TYPE_MSK	include/ssv6200_aux.h	13671;"	d
+RG_RX_DES_TYPE_SFT	include/ssv6200_aux.h	13673;"	d
+RG_RX_DES_TYPE_SZ	include/ssv6200_aux.h	13675;"	d
+RG_RX_DIV2_CORE_HI	include/ssv6200_aux.h	16534;"	d
+RG_RX_DIV2_CORE_I_MSK	include/ssv6200_aux.h	16532;"	d
+RG_RX_DIV2_CORE_MSK	include/ssv6200_aux.h	16531;"	d
+RG_RX_DIV2_CORE_SFT	include/ssv6200_aux.h	16533;"	d
+RG_RX_DIV2_CORE_SZ	include/ssv6200_aux.h	16535;"	d
+RG_RX_DIV2_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21674;"	d
+RG_RX_DIV2_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21672;"	d
+RG_RX_DIV2_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21671;"	d
+RG_RX_DIV2_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21673;"	d
+RG_RX_DIV2_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21675;"	d
+RG_RX_EN_LOOPA_HI	include/ssv6200_aux.h	16359;"	d
+RG_RX_EN_LOOPA_I_MSK	include/ssv6200_aux.h	16357;"	d
+RG_RX_EN_LOOPA_MSK	include/ssv6200_aux.h	16356;"	d
+RG_RX_EN_LOOPA_SFT	include/ssv6200_aux.h	16358;"	d
+RG_RX_EN_LOOPA_SZ	include/ssv6200_aux.h	16360;"	d
+RG_RX_FFT_SCALE_HI	include/ssv6200_aux.h	14839;"	d
+RG_RX_FFT_SCALE_I_MSK	include/ssv6200_aux.h	14837;"	d
+RG_RX_FFT_SCALE_MSK	include/ssv6200_aux.h	14836;"	d
+RG_RX_FFT_SCALE_SFT	include/ssv6200_aux.h	14838;"	d
+RG_RX_FFT_SCALE_SZ	include/ssv6200_aux.h	14840;"	d
+RG_RX_FIFO_FULL_CNT_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31374;"	d
+RG_RX_FIFO_FULL_CNT_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31372;"	d
+RG_RX_FIFO_FULL_CNT_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31371;"	d
+RG_RX_FIFO_FULL_CNT_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31373;"	d
+RG_RX_FIFO_FULL_CNT_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31375;"	d
+RG_RX_FILTERI1ST_HI	include/ssv6200_aux.h	16364;"	d
+RG_RX_FILTERI1ST_I_MSK	include/ssv6200_aux.h	16362;"	d
+RG_RX_FILTERI1ST_MSK	include/ssv6200_aux.h	16361;"	d
+RG_RX_FILTERI1ST_SFT	include/ssv6200_aux.h	16363;"	d
+RG_RX_FILTERI1ST_SZ	include/ssv6200_aux.h	16365;"	d
+RG_RX_FILTERI2ND_HI	include/ssv6200_aux.h	16369;"	d
+RG_RX_FILTERI2ND_I_MSK	include/ssv6200_aux.h	16367;"	d
+RG_RX_FILTERI2ND_MSK	include/ssv6200_aux.h	16366;"	d
+RG_RX_FILTERI2ND_SFT	include/ssv6200_aux.h	16368;"	d
+RG_RX_FILTERI2ND_SZ	include/ssv6200_aux.h	16370;"	d
+RG_RX_FILTERI3RD_HI	include/ssv6200_aux.h	16374;"	d
+RG_RX_FILTERI3RD_I_MSK	include/ssv6200_aux.h	16372;"	d
+RG_RX_FILTERI3RD_MSK	include/ssv6200_aux.h	16371;"	d
+RG_RX_FILTERI3RD_SFT	include/ssv6200_aux.h	16373;"	d
+RG_RX_FILTERI3RD_SZ	include/ssv6200_aux.h	16375;"	d
+RG_RX_FILTERI_COURSE_HI	include/ssv6200_aux.h	16379;"	d
+RG_RX_FILTERI_COURSE_I_MSK	include/ssv6200_aux.h	16377;"	d
+RG_RX_FILTERI_COURSE_MSK	include/ssv6200_aux.h	16376;"	d
+RG_RX_FILTERI_COURSE_SFT	include/ssv6200_aux.h	16378;"	d
+RG_RX_FILTERI_COURSE_SZ	include/ssv6200_aux.h	16380;"	d
+RG_RX_FILTERVCM_HI	include/ssv6200_aux.h	16384;"	d
+RG_RX_FILTERVCM_I_MSK	include/ssv6200_aux.h	16382;"	d
+RG_RX_FILTERVCM_MSK	include/ssv6200_aux.h	16381;"	d
+RG_RX_FILTERVCM_SFT	include/ssv6200_aux.h	16383;"	d
+RG_RX_FILTERVCM_SZ	include/ssv6200_aux.h	16385;"	d
+RG_RX_FILTER_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21704;"	d
+RG_RX_FILTER_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21702;"	d
+RG_RX_FILTER_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21701;"	d
+RG_RX_FILTER_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21703;"	d
+RG_RX_FILTER_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21705;"	d
+RG_RX_GAIN_MANUAL_HI	include/ssv6200_aux.h	16084;"	d
+RG_RX_GAIN_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21589;"	d
+RG_RX_GAIN_MANUAL_I_MSK	include/ssv6200_aux.h	16082;"	d
+RG_RX_GAIN_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21587;"	d
+RG_RX_GAIN_MANUAL_MSK	include/ssv6200_aux.h	16081;"	d
+RG_RX_GAIN_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21586;"	d
+RG_RX_GAIN_MANUAL_SFT	include/ssv6200_aux.h	16083;"	d
+RG_RX_GAIN_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21588;"	d
+RG_RX_GAIN_MANUAL_SZ	include/ssv6200_aux.h	16085;"	d
+RG_RX_GAIN_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21590;"	d
+RG_RX_HG_LNAHGN_BIAS_HI	include/ssv6200_aux.h	16584;"	d
+RG_RX_HG_LNAHGN_BIAS_I_MSK	include/ssv6200_aux.h	16582;"	d
+RG_RX_HG_LNAHGN_BIAS_MSK	include/ssv6200_aux.h	16581;"	d
+RG_RX_HG_LNAHGN_BIAS_SFT	include/ssv6200_aux.h	16583;"	d
+RG_RX_HG_LNAHGN_BIAS_SZ	include/ssv6200_aux.h	16585;"	d
+RG_RX_HG_LNAHGP_BIAS_HI	include/ssv6200_aux.h	16589;"	d
+RG_RX_HG_LNAHGP_BIAS_I_MSK	include/ssv6200_aux.h	16587;"	d
+RG_RX_HG_LNAHGP_BIAS_MSK	include/ssv6200_aux.h	16586;"	d
+RG_RX_HG_LNAHGP_BIAS_SFT	include/ssv6200_aux.h	16588;"	d
+RG_RX_HG_LNAHGP_BIAS_SZ	include/ssv6200_aux.h	16590;"	d
+RG_RX_HG_LNALG_BIAS_HI	include/ssv6200_aux.h	16594;"	d
+RG_RX_HG_LNALG_BIAS_I_MSK	include/ssv6200_aux.h	16592;"	d
+RG_RX_HG_LNALG_BIAS_MSK	include/ssv6200_aux.h	16591;"	d
+RG_RX_HG_LNALG_BIAS_SFT	include/ssv6200_aux.h	16593;"	d
+RG_RX_HG_LNALG_BIAS_SZ	include/ssv6200_aux.h	16595;"	d
+RG_RX_HG_LNA_GC_HI	include/ssv6200_aux.h	16579;"	d
+RG_RX_HG_LNA_GC_I_MSK	include/ssv6200_aux.h	16577;"	d
+RG_RX_HG_LNA_GC_MSK	include/ssv6200_aux.h	16576;"	d
+RG_RX_HG_LNA_GC_SFT	include/ssv6200_aux.h	16578;"	d
+RG_RX_HG_LNA_GC_SZ	include/ssv6200_aux.h	16580;"	d
+RG_RX_HG_TZ_CAP_HI	include/ssv6200_aux.h	16604;"	d
+RG_RX_HG_TZ_CAP_I_MSK	include/ssv6200_aux.h	16602;"	d
+RG_RX_HG_TZ_CAP_MSK	include/ssv6200_aux.h	16601;"	d
+RG_RX_HG_TZ_CAP_SFT	include/ssv6200_aux.h	16603;"	d
+RG_RX_HG_TZ_CAP_SZ	include/ssv6200_aux.h	16605;"	d
+RG_RX_HG_TZ_GC_HI	include/ssv6200_aux.h	16599;"	d
+RG_RX_HG_TZ_GC_I_MSK	include/ssv6200_aux.h	16597;"	d
+RG_RX_HG_TZ_GC_MSK	include/ssv6200_aux.h	16596;"	d
+RG_RX_HG_TZ_GC_SFT	include/ssv6200_aux.h	16598;"	d
+RG_RX_HG_TZ_GC_SZ	include/ssv6200_aux.h	16600;"	d
+RG_RX_HPF300K_HI	include/ssv6200_aux.h	16394;"	d
+RG_RX_HPF300K_I_MSK	include/ssv6200_aux.h	16392;"	d
+RG_RX_HPF300K_MSK	include/ssv6200_aux.h	16391;"	d
+RG_RX_HPF300K_SFT	include/ssv6200_aux.h	16393;"	d
+RG_RX_HPF300K_SZ	include/ssv6200_aux.h	16395;"	d
+RG_RX_HPF3M_HI	include/ssv6200_aux.h	16389;"	d
+RG_RX_HPF3M_I_MSK	include/ssv6200_aux.h	16387;"	d
+RG_RX_HPF3M_MSK	include/ssv6200_aux.h	16386;"	d
+RG_RX_HPF3M_SFT	include/ssv6200_aux.h	16388;"	d
+RG_RX_HPF3M_SZ	include/ssv6200_aux.h	16390;"	d
+RG_RX_HPFI_HI	include/ssv6200_aux.h	16399;"	d
+RG_RX_HPFI_I_MSK	include/ssv6200_aux.h	16397;"	d
+RG_RX_HPFI_MSK	include/ssv6200_aux.h	16396;"	d
+RG_RX_HPFI_SFT	include/ssv6200_aux.h	16398;"	d
+RG_RX_HPFI_SZ	include/ssv6200_aux.h	16400;"	d
+RG_RX_HPF_FINALCORNER_HI	include/ssv6200_aux.h	16404;"	d
+RG_RX_HPF_FINALCORNER_I_MSK	include/ssv6200_aux.h	16402;"	d
+RG_RX_HPF_FINALCORNER_MSK	include/ssv6200_aux.h	16401;"	d
+RG_RX_HPF_FINALCORNER_SFT	include/ssv6200_aux.h	16403;"	d
+RG_RX_HPF_FINALCORNER_SZ	include/ssv6200_aux.h	16405;"	d
+RG_RX_HPF_SETTLE1_C_HI	include/ssv6200_aux.h	16409;"	d
+RG_RX_HPF_SETTLE1_C_I_MSK	include/ssv6200_aux.h	16407;"	d
+RG_RX_HPF_SETTLE1_C_MSK	include/ssv6200_aux.h	16406;"	d
+RG_RX_HPF_SETTLE1_C_SFT	include/ssv6200_aux.h	16408;"	d
+RG_RX_HPF_SETTLE1_C_SZ	include/ssv6200_aux.h	16410;"	d
+RG_RX_HPF_SETTLE1_R_HI	include/ssv6200_aux.h	16414;"	d
+RG_RX_HPF_SETTLE1_R_I_MSK	include/ssv6200_aux.h	16412;"	d
+RG_RX_HPF_SETTLE1_R_MSK	include/ssv6200_aux.h	16411;"	d
+RG_RX_HPF_SETTLE1_R_SFT	include/ssv6200_aux.h	16413;"	d
+RG_RX_HPF_SETTLE1_R_SZ	include/ssv6200_aux.h	16415;"	d
+RG_RX_HPF_SETTLE2_C_HI	include/ssv6200_aux.h	16419;"	d
+RG_RX_HPF_SETTLE2_C_I_MSK	include/ssv6200_aux.h	16417;"	d
+RG_RX_HPF_SETTLE2_C_MSK	include/ssv6200_aux.h	16416;"	d
+RG_RX_HPF_SETTLE2_C_SFT	include/ssv6200_aux.h	16418;"	d
+RG_RX_HPF_SETTLE2_C_SZ	include/ssv6200_aux.h	16420;"	d
+RG_RX_HPF_SETTLE2_R_HI	include/ssv6200_aux.h	16424;"	d
+RG_RX_HPF_SETTLE2_R_I_MSK	include/ssv6200_aux.h	16422;"	d
+RG_RX_HPF_SETTLE2_R_MSK	include/ssv6200_aux.h	16421;"	d
+RG_RX_HPF_SETTLE2_R_SFT	include/ssv6200_aux.h	16423;"	d
+RG_RX_HPF_SETTLE2_R_SZ	include/ssv6200_aux.h	16425;"	d
+RG_RX_HPF_VCMCON2_HI	include/ssv6200_aux.h	16429;"	d
+RG_RX_HPF_VCMCON2_I_MSK	include/ssv6200_aux.h	16427;"	d
+RG_RX_HPF_VCMCON2_MSK	include/ssv6200_aux.h	16426;"	d
+RG_RX_HPF_VCMCON2_SFT	include/ssv6200_aux.h	16428;"	d
+RG_RX_HPF_VCMCON2_SZ	include/ssv6200_aux.h	16430;"	d
+RG_RX_HPF_VCMCON_HI	include/ssv6200_aux.h	16434;"	d
+RG_RX_HPF_VCMCON_I_MSK	include/ssv6200_aux.h	16432;"	d
+RG_RX_HPF_VCMCON_MSK	include/ssv6200_aux.h	16431;"	d
+RG_RX_HPF_VCMCON_SFT	include/ssv6200_aux.h	16433;"	d
+RG_RX_HPF_VCMCON_SZ	include/ssv6200_aux.h	16435;"	d
+RG_RX_IDACA_COARSE_PMOS_ON_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22244;"	d
+RG_RX_IDACA_COARSE_PMOS_ON_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22242;"	d
+RG_RX_IDACA_COARSE_PMOS_ON_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22241;"	d
+RG_RX_IDACA_COARSE_PMOS_ON_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22243;"	d
+RG_RX_IDACA_COARSE_PMOS_ON_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22245;"	d
+RG_RX_IQCAL_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24699;"	d
+RG_RX_IQCAL_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24697;"	d
+RG_RX_IQCAL_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24696;"	d
+RG_RX_IQCAL_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24698;"	d
+RG_RX_IQCAL_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24700;"	d
+RG_RX_IQCAL_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21849;"	d
+RG_RX_IQCAL_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21847;"	d
+RG_RX_IQCAL_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21846;"	d
+RG_RX_IQCAL_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21848;"	d
+RG_RX_IQCAL_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21850;"	d
+RG_RX_IQ_2500_ALPHA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27359;"	d
+RG_RX_IQ_2500_ALPHA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27357;"	d
+RG_RX_IQ_2500_ALPHA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27356;"	d
+RG_RX_IQ_2500_ALPHA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27358;"	d
+RG_RX_IQ_2500_ALPHA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27360;"	d
+RG_RX_IQ_2500_THETA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27364;"	d
+RG_RX_IQ_2500_THETA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27362;"	d
+RG_RX_IQ_2500_THETA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27361;"	d
+RG_RX_IQ_2500_THETA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27363;"	d
+RG_RX_IQ_2500_THETA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27365;"	d
+RG_RX_IQ_5100_ALPHA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27379;"	d
+RG_RX_IQ_5100_ALPHA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27377;"	d
+RG_RX_IQ_5100_ALPHA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27376;"	d
+RG_RX_IQ_5100_ALPHA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27378;"	d
+RG_RX_IQ_5100_ALPHA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27380;"	d
+RG_RX_IQ_5100_THETA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27384;"	d
+RG_RX_IQ_5100_THETA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27382;"	d
+RG_RX_IQ_5100_THETA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27381;"	d
+RG_RX_IQ_5100_THETA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27383;"	d
+RG_RX_IQ_5100_THETA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27385;"	d
+RG_RX_IQ_5500_ALPHA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27399;"	d
+RG_RX_IQ_5500_ALPHA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27397;"	d
+RG_RX_IQ_5500_ALPHA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27396;"	d
+RG_RX_IQ_5500_ALPHA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27398;"	d
+RG_RX_IQ_5500_ALPHA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27400;"	d
+RG_RX_IQ_5500_THETA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27404;"	d
+RG_RX_IQ_5500_THETA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27402;"	d
+RG_RX_IQ_5500_THETA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27401;"	d
+RG_RX_IQ_5500_THETA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27403;"	d
+RG_RX_IQ_5500_THETA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27405;"	d
+RG_RX_IQ_5700_ALPHA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27419;"	d
+RG_RX_IQ_5700_ALPHA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27417;"	d
+RG_RX_IQ_5700_ALPHA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27416;"	d
+RG_RX_IQ_5700_ALPHA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27418;"	d
+RG_RX_IQ_5700_ALPHA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27420;"	d
+RG_RX_IQ_5700_THETA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27424;"	d
+RG_RX_IQ_5700_THETA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27422;"	d
+RG_RX_IQ_5700_THETA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27421;"	d
+RG_RX_IQ_5700_THETA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27423;"	d
+RG_RX_IQ_5700_THETA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27425;"	d
+RG_RX_IQ_5900_ALPHA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27439;"	d
+RG_RX_IQ_5900_ALPHA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27437;"	d
+RG_RX_IQ_5900_ALPHA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27436;"	d
+RG_RX_IQ_5900_ALPHA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27438;"	d
+RG_RX_IQ_5900_ALPHA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27440;"	d
+RG_RX_IQ_5900_THETA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27444;"	d
+RG_RX_IQ_5900_THETA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27442;"	d
+RG_RX_IQ_5900_THETA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27441;"	d
+RG_RX_IQ_5900_THETA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27443;"	d
+RG_RX_IQ_5900_THETA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27445;"	d
+RG_RX_IQ_ALPHA_HI	include/ssv6200_aux.h	15504;"	d
+RG_RX_IQ_ALPHA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27179;"	d
+RG_RX_IQ_ALPHA_I_MSK	include/ssv6200_aux.h	15502;"	d
+RG_RX_IQ_ALPHA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27177;"	d
+RG_RX_IQ_ALPHA_MSK	include/ssv6200_aux.h	15501;"	d
+RG_RX_IQ_ALPHA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27176;"	d
+RG_RX_IQ_ALPHA_SFT	include/ssv6200_aux.h	15503;"	d
+RG_RX_IQ_ALPHA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27178;"	d
+RG_RX_IQ_ALPHA_SZ	include/ssv6200_aux.h	15505;"	d
+RG_RX_IQ_ALPHA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27180;"	d
+RG_RX_IQ_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27189;"	d
+RG_RX_IQ_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27187;"	d
+RG_RX_IQ_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27186;"	d
+RG_RX_IQ_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27188;"	d
+RG_RX_IQ_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27190;"	d
+RG_RX_IQ_SRC_HI	include/ssv6200_aux.h	15679;"	d
+RG_RX_IQ_SRC_I_MSK	include/ssv6200_aux.h	15677;"	d
+RG_RX_IQ_SRC_MSK	include/ssv6200_aux.h	15676;"	d
+RG_RX_IQ_SRC_SFT	include/ssv6200_aux.h	15678;"	d
+RG_RX_IQ_SRC_SZ	include/ssv6200_aux.h	15680;"	d
+RG_RX_IQ_SWP_HI	include/ssv6200_aux.h	15669;"	d
+RG_RX_IQ_SWP_I_MSK	include/ssv6200_aux.h	15667;"	d
+RG_RX_IQ_SWP_MSK	include/ssv6200_aux.h	15666;"	d
+RG_RX_IQ_SWP_SFT	include/ssv6200_aux.h	15668;"	d
+RG_RX_IQ_SWP_SZ	include/ssv6200_aux.h	15670;"	d
+RG_RX_IQ_THETA_HI	include/ssv6200_aux.h	15499;"	d
+RG_RX_IQ_THETA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27184;"	d
+RG_RX_IQ_THETA_I_MSK	include/ssv6200_aux.h	15497;"	d
+RG_RX_IQ_THETA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27182;"	d
+RG_RX_IQ_THETA_MSK	include/ssv6200_aux.h	15496;"	d
+RG_RX_IQ_THETA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27181;"	d
+RG_RX_IQ_THETA_SFT	include/ssv6200_aux.h	15498;"	d
+RG_RX_IQ_THETA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27183;"	d
+RG_RX_IQ_THETA_SZ	include/ssv6200_aux.h	15500;"	d
+RG_RX_IQ_THETA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27185;"	d
+RG_RX_I_OFFSET_HI	include/ssv6200_aux.h	15659;"	d
+RG_RX_I_OFFSET_I_MSK	include/ssv6200_aux.h	15657;"	d
+RG_RX_I_OFFSET_MSK	include/ssv6200_aux.h	15656;"	d
+RG_RX_I_OFFSET_SFT	include/ssv6200_aux.h	15658;"	d
+RG_RX_I_OFFSET_SZ	include/ssv6200_aux.h	15660;"	d
+RG_RX_I_SCALE_HI	include/ssv6200_aux.h	15649;"	d
+RG_RX_I_SCALE_I_MSK	include/ssv6200_aux.h	15647;"	d
+RG_RX_I_SCALE_MSK	include/ssv6200_aux.h	15646;"	d
+RG_RX_I_SCALE_SFT	include/ssv6200_aux.h	15648;"	d
+RG_RX_I_SCALE_SZ	include/ssv6200_aux.h	15650;"	d
+RG_RX_LG_LNAHGN_BIAS_HI	include/ssv6200_aux.h	16644;"	d
+RG_RX_LG_LNAHGN_BIAS_I_MSK	include/ssv6200_aux.h	16642;"	d
+RG_RX_LG_LNAHGN_BIAS_MSK	include/ssv6200_aux.h	16641;"	d
+RG_RX_LG_LNAHGN_BIAS_SFT	include/ssv6200_aux.h	16643;"	d
+RG_RX_LG_LNAHGN_BIAS_SZ	include/ssv6200_aux.h	16645;"	d
+RG_RX_LG_LNAHGP_BIAS_HI	include/ssv6200_aux.h	16649;"	d
+RG_RX_LG_LNAHGP_BIAS_I_MSK	include/ssv6200_aux.h	16647;"	d
+RG_RX_LG_LNAHGP_BIAS_MSK	include/ssv6200_aux.h	16646;"	d
+RG_RX_LG_LNAHGP_BIAS_SFT	include/ssv6200_aux.h	16648;"	d
+RG_RX_LG_LNAHGP_BIAS_SZ	include/ssv6200_aux.h	16650;"	d
+RG_RX_LG_LNALG_BIAS_HI	include/ssv6200_aux.h	16654;"	d
+RG_RX_LG_LNALG_BIAS_I_MSK	include/ssv6200_aux.h	16652;"	d
+RG_RX_LG_LNALG_BIAS_MSK	include/ssv6200_aux.h	16651;"	d
+RG_RX_LG_LNALG_BIAS_SFT	include/ssv6200_aux.h	16653;"	d
+RG_RX_LG_LNALG_BIAS_SZ	include/ssv6200_aux.h	16655;"	d
+RG_RX_LG_LNA_GC_HI	include/ssv6200_aux.h	16639;"	d
+RG_RX_LG_LNA_GC_I_MSK	include/ssv6200_aux.h	16637;"	d
+RG_RX_LG_LNA_GC_MSK	include/ssv6200_aux.h	16636;"	d
+RG_RX_LG_LNA_GC_SFT	include/ssv6200_aux.h	16638;"	d
+RG_RX_LG_LNA_GC_SZ	include/ssv6200_aux.h	16640;"	d
+RG_RX_LG_TZ_CAP_HI	include/ssv6200_aux.h	16664;"	d
+RG_RX_LG_TZ_CAP_I_MSK	include/ssv6200_aux.h	16662;"	d
+RG_RX_LG_TZ_CAP_MSK	include/ssv6200_aux.h	16661;"	d
+RG_RX_LG_TZ_CAP_SFT	include/ssv6200_aux.h	16663;"	d
+RG_RX_LG_TZ_CAP_SZ	include/ssv6200_aux.h	16665;"	d
+RG_RX_LG_TZ_GC_HI	include/ssv6200_aux.h	16659;"	d
+RG_RX_LG_TZ_GC_I_MSK	include/ssv6200_aux.h	16657;"	d
+RG_RX_LG_TZ_GC_MSK	include/ssv6200_aux.h	16656;"	d
+RG_RX_LG_TZ_GC_SFT	include/ssv6200_aux.h	16658;"	d
+RG_RX_LG_TZ_GC_SZ	include/ssv6200_aux.h	16660;"	d
+RG_RX_LNA_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21654;"	d
+RG_RX_LNA_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21652;"	d
+RG_RX_LNA_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21651;"	d
+RG_RX_LNA_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21653;"	d
+RG_RX_LNA_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21655;"	d
+RG_RX_LNA_SETTLE_HI	include/ssv6200_aux.h	16734;"	d
+RG_RX_LNA_SETTLE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22289;"	d
+RG_RX_LNA_SETTLE_I_MSK	include/ssv6200_aux.h	16732;"	d
+RG_RX_LNA_SETTLE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22287;"	d
+RG_RX_LNA_SETTLE_MSK	include/ssv6200_aux.h	16731;"	d
+RG_RX_LNA_SETTLE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22286;"	d
+RG_RX_LNA_SETTLE_SFT	include/ssv6200_aux.h	16733;"	d
+RG_RX_LNA_SETTLE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22288;"	d
+RG_RX_LNA_SETTLE_SZ	include/ssv6200_aux.h	16735;"	d
+RG_RX_LNA_SETTLE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22290;"	d
+RG_RX_LNA_TRI_SEL_HI	include/ssv6200_aux.h	16729;"	d
+RG_RX_LNA_TRI_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22284;"	d
+RG_RX_LNA_TRI_SEL_I_MSK	include/ssv6200_aux.h	16727;"	d
+RG_RX_LNA_TRI_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22282;"	d
+RG_RX_LNA_TRI_SEL_MSK	include/ssv6200_aux.h	16726;"	d
+RG_RX_LNA_TRI_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22281;"	d
+RG_RX_LNA_TRI_SEL_SFT	include/ssv6200_aux.h	16728;"	d
+RG_RX_LNA_TRI_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22283;"	d
+RG_RX_LNA_TRI_SEL_SZ	include/ssv6200_aux.h	16730;"	d
+RG_RX_LNA_TRI_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22285;"	d
+RG_RX_LOBUF_HI	include/ssv6200_aux.h	16539;"	d
+RG_RX_LOBUF_I_MSK	include/ssv6200_aux.h	16537;"	d
+RG_RX_LOBUF_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21684;"	d
+RG_RX_LOBUF_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21682;"	d
+RG_RX_LOBUF_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21681;"	d
+RG_RX_LOBUF_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21683;"	d
+RG_RX_LOBUF_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21685;"	d
+RG_RX_LOBUF_MSK	include/ssv6200_aux.h	16536;"	d
+RG_RX_LOBUF_SFT	include/ssv6200_aux.h	16538;"	d
+RG_RX_LOBUF_SZ	include/ssv6200_aux.h	16540;"	d
+RG_RX_MG_LNAHGN_BIAS_HI	include/ssv6200_aux.h	16614;"	d
+RG_RX_MG_LNAHGN_BIAS_I_MSK	include/ssv6200_aux.h	16612;"	d
+RG_RX_MG_LNAHGN_BIAS_MSK	include/ssv6200_aux.h	16611;"	d
+RG_RX_MG_LNAHGN_BIAS_SFT	include/ssv6200_aux.h	16613;"	d
+RG_RX_MG_LNAHGN_BIAS_SZ	include/ssv6200_aux.h	16615;"	d
+RG_RX_MG_LNAHGP_BIAS_HI	include/ssv6200_aux.h	16619;"	d
+RG_RX_MG_LNAHGP_BIAS_I_MSK	include/ssv6200_aux.h	16617;"	d
+RG_RX_MG_LNAHGP_BIAS_MSK	include/ssv6200_aux.h	16616;"	d
+RG_RX_MG_LNAHGP_BIAS_SFT	include/ssv6200_aux.h	16618;"	d
+RG_RX_MG_LNAHGP_BIAS_SZ	include/ssv6200_aux.h	16620;"	d
+RG_RX_MG_LNALG_BIAS_HI	include/ssv6200_aux.h	16624;"	d
+RG_RX_MG_LNALG_BIAS_I_MSK	include/ssv6200_aux.h	16622;"	d
+RG_RX_MG_LNALG_BIAS_MSK	include/ssv6200_aux.h	16621;"	d
+RG_RX_MG_LNALG_BIAS_SFT	include/ssv6200_aux.h	16623;"	d
+RG_RX_MG_LNALG_BIAS_SZ	include/ssv6200_aux.h	16625;"	d
+RG_RX_MG_LNA_GC_HI	include/ssv6200_aux.h	16609;"	d
+RG_RX_MG_LNA_GC_I_MSK	include/ssv6200_aux.h	16607;"	d
+RG_RX_MG_LNA_GC_MSK	include/ssv6200_aux.h	16606;"	d
+RG_RX_MG_LNA_GC_SFT	include/ssv6200_aux.h	16608;"	d
+RG_RX_MG_LNA_GC_SZ	include/ssv6200_aux.h	16610;"	d
+RG_RX_MG_TZ_CAP_HI	include/ssv6200_aux.h	16634;"	d
+RG_RX_MG_TZ_CAP_I_MSK	include/ssv6200_aux.h	16632;"	d
+RG_RX_MG_TZ_CAP_MSK	include/ssv6200_aux.h	16631;"	d
+RG_RX_MG_TZ_CAP_SFT	include/ssv6200_aux.h	16633;"	d
+RG_RX_MG_TZ_CAP_SZ	include/ssv6200_aux.h	16635;"	d
+RG_RX_MG_TZ_GC_HI	include/ssv6200_aux.h	16629;"	d
+RG_RX_MG_TZ_GC_I_MSK	include/ssv6200_aux.h	16627;"	d
+RG_RX_MG_TZ_GC_MSK	include/ssv6200_aux.h	16626;"	d
+RG_RX_MG_TZ_GC_SFT	include/ssv6200_aux.h	16628;"	d
+RG_RX_MG_TZ_GC_SZ	include/ssv6200_aux.h	16630;"	d
+RG_RX_MIXER_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21664;"	d
+RG_RX_MIXER_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21662;"	d
+RG_RX_MIXER_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21661;"	d
+RG_RX_MIXER_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21663;"	d
+RG_RX_MIXER_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21665;"	d
+RG_RX_MONITOR_ON_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31269;"	d
+RG_RX_MONITOR_ON_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31267;"	d
+RG_RX_MONITOR_ON_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31266;"	d
+RG_RX_MONITOR_ON_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31268;"	d
+RG_RX_MONITOR_ON_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31270;"	d
+RG_RX_N_RCCAL_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24704;"	d
+RG_RX_N_RCCAL_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24702;"	d
+RG_RX_N_RCCAL_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24701;"	d
+RG_RX_N_RCCAL_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24703;"	d
+RG_RX_N_RCCAL_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24705;"	d
+RG_RX_OUTVCM_HI	include/ssv6200_aux.h	16439;"	d
+RG_RX_OUTVCM_I_MSK	include/ssv6200_aux.h	16437;"	d
+RG_RX_OUTVCM_MSK	include/ssv6200_aux.h	16436;"	d
+RG_RX_OUTVCM_SFT	include/ssv6200_aux.h	16438;"	d
+RG_RX_OUTVCM_SZ	include/ssv6200_aux.h	16440;"	d
+RG_RX_PADPD_DATA_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28939;"	d
+RG_RX_PADPD_DATA_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28937;"	d
+RG_RX_PADPD_DATA_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28936;"	d
+RG_RX_PADPD_DATA_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28938;"	d
+RG_RX_PADPD_DATA_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28940;"	d
+RG_RX_PADPD_DC_RM_BYP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28984;"	d
+RG_RX_PADPD_DC_RM_BYP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28982;"	d
+RG_RX_PADPD_DC_RM_BYP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28981;"	d
+RG_RX_PADPD_DC_RM_BYP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28983;"	d
+RG_RX_PADPD_DC_RM_BYP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28985;"	d
+RG_RX_PADPD_DC_RM_LEAKY_FACTOR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28979;"	d
+RG_RX_PADPD_DC_RM_LEAKY_FACTOR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28977;"	d
+RG_RX_PADPD_DC_RM_LEAKY_FACTOR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28976;"	d
+RG_RX_PADPD_DC_RM_LEAKY_FACTOR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28978;"	d
+RG_RX_PADPD_DC_RM_LEAKY_FACTOR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28980;"	d
+RG_RX_PADPD_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28924;"	d
+RG_RX_PADPD_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28922;"	d
+RG_RX_PADPD_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28921;"	d
+RG_RX_PADPD_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28923;"	d
+RG_RX_PADPD_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28925;"	d
+RG_RX_PADPD_LATCH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28934;"	d
+RG_RX_PADPD_LATCH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28932;"	d
+RG_RX_PADPD_LATCH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28931;"	d
+RG_RX_PADPD_LATCH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28933;"	d
+RG_RX_PADPD_LATCH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28935;"	d
+RG_RX_PADPD_LEAKY_FACTOR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28929;"	d
+RG_RX_PADPD_LEAKY_FACTOR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28927;"	d
+RG_RX_PADPD_LEAKY_FACTOR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28926;"	d
+RG_RX_PADPD_LEAKY_FACTOR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28928;"	d
+RG_RX_PADPD_LEAKY_FACTOR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28930;"	d
+RG_RX_PADPD_RATE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28949;"	d
+RG_RX_PADPD_RATE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28947;"	d
+RG_RX_PADPD_RATE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28946;"	d
+RG_RX_PADPD_RATE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28948;"	d
+RG_RX_PADPD_RATE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28950;"	d
+RG_RX_PADPD_TONE_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28944;"	d
+RG_RX_PADPD_TONE_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28942;"	d
+RG_RX_PADPD_TONE_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28941;"	d
+RG_RX_PADPD_TONE_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28943;"	d
+RG_RX_PADPD_TONE_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28945;"	d
+RG_RX_PKT_ADDR1_31_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31319;"	d
+RG_RX_PKT_ADDR1_31_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31317;"	d
+RG_RX_PKT_ADDR1_31_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31316;"	d
+RG_RX_PKT_ADDR1_31_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31318;"	d
+RG_RX_PKT_ADDR1_31_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31320;"	d
+RG_RX_PKT_ADDR1_47_32_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31324;"	d
+RG_RX_PKT_ADDR1_47_32_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31322;"	d
+RG_RX_PKT_ADDR1_47_32_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31321;"	d
+RG_RX_PKT_ADDR1_47_32_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31323;"	d
+RG_RX_PKT_ADDR1_47_32_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31325;"	d
+RG_RX_PKT_ADDR1_ON_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31284;"	d
+RG_RX_PKT_ADDR1_ON_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31282;"	d
+RG_RX_PKT_ADDR1_ON_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31281;"	d
+RG_RX_PKT_ADDR1_ON_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31283;"	d
+RG_RX_PKT_ADDR1_ON_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31285;"	d
+RG_RX_PKT_ADDR2_31_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31329;"	d
+RG_RX_PKT_ADDR2_31_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31327;"	d
+RG_RX_PKT_ADDR2_31_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31326;"	d
+RG_RX_PKT_ADDR2_31_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31328;"	d
+RG_RX_PKT_ADDR2_31_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31330;"	d
+RG_RX_PKT_ADDR2_47_32_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31334;"	d
+RG_RX_PKT_ADDR2_47_32_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31332;"	d
+RG_RX_PKT_ADDR2_47_32_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31331;"	d
+RG_RX_PKT_ADDR2_47_32_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31333;"	d
+RG_RX_PKT_ADDR2_47_32_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31335;"	d
+RG_RX_PKT_ADDR2_ON_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31279;"	d
+RG_RX_PKT_ADDR2_ON_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31277;"	d
+RG_RX_PKT_ADDR2_ON_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31276;"	d
+RG_RX_PKT_ADDR2_ON_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31278;"	d
+RG_RX_PKT_ADDR2_ON_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31280;"	d
+RG_RX_PKT_ADDR3_31_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31339;"	d
+RG_RX_PKT_ADDR3_31_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31337;"	d
+RG_RX_PKT_ADDR3_31_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31336;"	d
+RG_RX_PKT_ADDR3_31_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31338;"	d
+RG_RX_PKT_ADDR3_31_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31340;"	d
+RG_RX_PKT_ADDR3_47_32_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31344;"	d
+RG_RX_PKT_ADDR3_47_32_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31342;"	d
+RG_RX_PKT_ADDR3_47_32_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31341;"	d
+RG_RX_PKT_ADDR3_47_32_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31343;"	d
+RG_RX_PKT_ADDR3_47_32_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31345;"	d
+RG_RX_PKT_ADDR3_ON_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31274;"	d
+RG_RX_PKT_ADDR3_ON_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31272;"	d
+RG_RX_PKT_ADDR3_ON_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31271;"	d
+RG_RX_PKT_ADDR3_ON_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31273;"	d
+RG_RX_PKT_ADDR3_ON_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31275;"	d
+RG_RX_PKT_FC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31314;"	d
+RG_RX_PKT_FC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31312;"	d
+RG_RX_PKT_FC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31311;"	d
+RG_RX_PKT_FC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31313;"	d
+RG_RX_PKT_FC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31315;"	d
+RG_RX_PKT_TIMER_LMT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31294;"	d
+RG_RX_PKT_TIMER_LMT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31292;"	d
+RG_RX_PKT_TIMER_LMT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31291;"	d
+RG_RX_PKT_TIMER_LMT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31293;"	d
+RG_RX_PKT_TIMER_LMT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31295;"	d
+RG_RX_PRE_DC_RESOLUTION_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27639;"	d
+RG_RX_PRE_DC_RESOLUTION_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27637;"	d
+RG_RX_PRE_DC_RESOLUTION_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27636;"	d
+RG_RX_PRE_DC_RESOLUTION_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27638;"	d
+RG_RX_PRE_DC_RESOLUTION_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27640;"	d
+RG_RX_Q_OFFSET_HI	include/ssv6200_aux.h	15664;"	d
+RG_RX_Q_OFFSET_I_MSK	include/ssv6200_aux.h	15662;"	d
+RG_RX_Q_OFFSET_MSK	include/ssv6200_aux.h	15661;"	d
+RG_RX_Q_OFFSET_SFT	include/ssv6200_aux.h	15663;"	d
+RG_RX_Q_OFFSET_SZ	include/ssv6200_aux.h	15665;"	d
+RG_RX_Q_SCALE_HI	include/ssv6200_aux.h	15654;"	d
+RG_RX_Q_SCALE_I_MSK	include/ssv6200_aux.h	15652;"	d
+RG_RX_Q_SCALE_MSK	include/ssv6200_aux.h	15651;"	d
+RG_RX_Q_SCALE_SFT	include/ssv6200_aux.h	15653;"	d
+RG_RX_Q_SCALE_SZ	include/ssv6200_aux.h	15655;"	d
+RG_RX_RCCAL_40M_TARG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27604;"	d
+RG_RX_RCCAL_40M_TARG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27602;"	d
+RG_RX_RCCAL_40M_TARG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27601;"	d
+RG_RX_RCCAL_40M_TARG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27603;"	d
+RG_RX_RCCAL_40M_TARG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27605;"	d
+RG_RX_RCCAL_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24684;"	d
+RG_RX_RCCAL_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24682;"	d
+RG_RX_RCCAL_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24681;"	d
+RG_RX_RCCAL_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24683;"	d
+RG_RX_RCCAL_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24685;"	d
+RG_RX_RCCAL_TARG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27584;"	d
+RG_RX_RCCAL_TARG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27582;"	d
+RG_RX_RCCAL_TARG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27581;"	d
+RG_RX_RCCAL_TARG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27583;"	d
+RG_RX_RCCAL_TARG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27585;"	d
+RG_RX_REC_LPFCORNER_HI	include/ssv6200_aux.h	16474;"	d
+RG_RX_REC_LPFCORNER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22229;"	d
+RG_RX_REC_LPFCORNER_I_MSK	include/ssv6200_aux.h	16472;"	d
+RG_RX_REC_LPFCORNER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22227;"	d
+RG_RX_REC_LPFCORNER_MSK	include/ssv6200_aux.h	16471;"	d
+RG_RX_REC_LPFCORNER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22226;"	d
+RG_RX_REC_LPFCORNER_SFT	include/ssv6200_aux.h	16473;"	d
+RG_RX_REC_LPFCORNER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22228;"	d
+RG_RX_REC_LPFCORNER_SZ	include/ssv6200_aux.h	16475;"	d
+RG_RX_REC_LPFCORNER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22230;"	d
+RG_RX_RSSIADC_TH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27199;"	d
+RG_RX_RSSIADC_TH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27197;"	d
+RG_RX_RSSIADC_TH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27196;"	d
+RG_RX_RSSIADC_TH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27198;"	d
+RG_RX_RSSIADC_TH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27200;"	d
+RG_RX_RSSI_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21724;"	d
+RG_RX_RSSI_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21722;"	d
+RG_RX_RSSI_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21721;"	d
+RG_RX_RSSI_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21723;"	d
+RG_RX_RSSI_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21725;"	d
+RG_RX_SCALOAD_STEP0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26984;"	d
+RG_RX_SCALOAD_STEP0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26982;"	d
+RG_RX_SCALOAD_STEP0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26981;"	d
+RG_RX_SCALOAD_STEP0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26983;"	d
+RG_RX_SCALOAD_STEP0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26985;"	d
+RG_RX_SCALOAD_STEP1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26989;"	d
+RG_RX_SCALOAD_STEP1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26987;"	d
+RG_RX_SCALOAD_STEP1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26986;"	d
+RG_RX_SCALOAD_STEP1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26988;"	d
+RG_RX_SCALOAD_STEP1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26990;"	d
+RG_RX_SCALOAD_STEP2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26994;"	d
+RG_RX_SCALOAD_STEP2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26992;"	d
+RG_RX_SCALOAD_STEP2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26991;"	d
+RG_RX_SCALOAD_STEP2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26993;"	d
+RG_RX_SCALOAD_STEP2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26995;"	d
+RG_RX_SCALOAD_STEP3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26999;"	d
+RG_RX_SCALOAD_STEP3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26997;"	d
+RG_RX_SCALOAD_STEP3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26996;"	d
+RG_RX_SCALOAD_STEP3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26998;"	d
+RG_RX_SCALOAD_STEP3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27000;"	d
+RG_RX_SCALOAD_STEP4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27004;"	d
+RG_RX_SCALOAD_STEP4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27002;"	d
+RG_RX_SCALOAD_STEP4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27001;"	d
+RG_RX_SCALOAD_STEP4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27003;"	d
+RG_RX_SCALOAD_STEP4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27005;"	d
+RG_RX_SCALOAD_STEP5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27009;"	d
+RG_RX_SCALOAD_STEP5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27007;"	d
+RG_RX_SCALOAD_STEP5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27006;"	d
+RG_RX_SCALOAD_STEP5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27008;"	d
+RG_RX_SCALOAD_STEP5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27010;"	d
+RG_RX_SCALOAD_STEP6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27014;"	d
+RG_RX_SCALOAD_STEP6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27012;"	d
+RG_RX_SCALOAD_STEP6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27011;"	d
+RG_RX_SCALOAD_STEP6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27013;"	d
+RG_RX_SCALOAD_STEP6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27015;"	d
+RG_RX_SCAMA_STEP0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26949;"	d
+RG_RX_SCAMA_STEP0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26947;"	d
+RG_RX_SCAMA_STEP0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26946;"	d
+RG_RX_SCAMA_STEP0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26948;"	d
+RG_RX_SCAMA_STEP0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26950;"	d
+RG_RX_SCAMA_STEP1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26954;"	d
+RG_RX_SCAMA_STEP1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26952;"	d
+RG_RX_SCAMA_STEP1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26951;"	d
+RG_RX_SCAMA_STEP1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26953;"	d
+RG_RX_SCAMA_STEP1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26955;"	d
+RG_RX_SCAMA_STEP2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26959;"	d
+RG_RX_SCAMA_STEP2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26957;"	d
+RG_RX_SCAMA_STEP2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26956;"	d
+RG_RX_SCAMA_STEP2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26958;"	d
+RG_RX_SCAMA_STEP2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26960;"	d
+RG_RX_SCAMA_STEP3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26964;"	d
+RG_RX_SCAMA_STEP3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26962;"	d
+RG_RX_SCAMA_STEP3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26961;"	d
+RG_RX_SCAMA_STEP3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26963;"	d
+RG_RX_SCAMA_STEP3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26965;"	d
+RG_RX_SCAMA_STEP4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26969;"	d
+RG_RX_SCAMA_STEP4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26967;"	d
+RG_RX_SCAMA_STEP4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26966;"	d
+RG_RX_SCAMA_STEP4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26968;"	d
+RG_RX_SCAMA_STEP4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26970;"	d
+RG_RX_SCAMA_STEP5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26974;"	d
+RG_RX_SCAMA_STEP5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26972;"	d
+RG_RX_SCAMA_STEP5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26971;"	d
+RG_RX_SCAMA_STEP5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26973;"	d
+RG_RX_SCAMA_STEP5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26975;"	d
+RG_RX_SCAMA_STEP6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26979;"	d
+RG_RX_SCAMA_STEP6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26977;"	d
+RG_RX_SCAMA_STEP6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26976;"	d
+RG_RX_SCAMA_STEP6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26978;"	d
+RG_RX_SCAMA_STEP6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26980;"	d
+RG_RX_SGN_IN_HI	include/ssv6200_aux.h	15674;"	d
+RG_RX_SGN_IN_I_MSK	include/ssv6200_aux.h	15672;"	d
+RG_RX_SGN_IN_MSK	include/ssv6200_aux.h	15671;"	d
+RG_RX_SGN_IN_SFT	include/ssv6200_aux.h	15673;"	d
+RG_RX_SGN_IN_SZ	include/ssv6200_aux.h	15675;"	d
+RG_RX_SQDC_HI	include/ssv6200_aux.h	16529;"	d
+RG_RX_SQDC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21939;"	d
+RG_RX_SQDC_I_MSK	include/ssv6200_aux.h	16527;"	d
+RG_RX_SQDC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21937;"	d
+RG_RX_SQDC_MSK	include/ssv6200_aux.h	16526;"	d
+RG_RX_SQDC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21936;"	d
+RG_RX_SQDC_SFT	include/ssv6200_aux.h	16528;"	d
+RG_RX_SQDC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21938;"	d
+RG_RX_SQDC_SZ	include/ssv6200_aux.h	16530;"	d
+RG_RX_SQDC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21940;"	d
+RG_RX_TZI_HI	include/ssv6200_aux.h	16444;"	d
+RG_RX_TZI_I_MSK	include/ssv6200_aux.h	16442;"	d
+RG_RX_TZI_MSK	include/ssv6200_aux.h	16441;"	d
+RG_RX_TZI_SFT	include/ssv6200_aux.h	16443;"	d
+RG_RX_TZI_SZ	include/ssv6200_aux.h	16445;"	d
+RG_RX_TZ_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21694;"	d
+RG_RX_TZ_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21692;"	d
+RG_RX_TZ_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21691;"	d
+RG_RX_TZ_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21693;"	d
+RG_RX_TZ_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21695;"	d
+RG_RX_TZ_OUT_TRISTATE_HI	include/ssv6200_aux.h	16449;"	d
+RG_RX_TZ_OUT_TRISTATE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21834;"	d
+RG_RX_TZ_OUT_TRISTATE_I_MSK	include/ssv6200_aux.h	16447;"	d
+RG_RX_TZ_OUT_TRISTATE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21832;"	d
+RG_RX_TZ_OUT_TRISTATE_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21829;"	d
+RG_RX_TZ_OUT_TRISTATE_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21827;"	d
+RG_RX_TZ_OUT_TRISTATE_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21826;"	d
+RG_RX_TZ_OUT_TRISTATE_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21828;"	d
+RG_RX_TZ_OUT_TRISTATE_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21830;"	d
+RG_RX_TZ_OUT_TRISTATE_MSK	include/ssv6200_aux.h	16446;"	d
+RG_RX_TZ_OUT_TRISTATE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21831;"	d
+RG_RX_TZ_OUT_TRISTATE_SFT	include/ssv6200_aux.h	16448;"	d
+RG_RX_TZ_OUT_TRISTATE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21833;"	d
+RG_RX_TZ_OUT_TRISTATE_SZ	include/ssv6200_aux.h	16450;"	d
+RG_RX_TZ_OUT_TRISTATE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21835;"	d
+RG_RX_TZ_VCM_HI	include/ssv6200_aux.h	16454;"	d
+RG_RX_TZ_VCM_I_MSK	include/ssv6200_aux.h	16452;"	d
+RG_RX_TZ_VCM_MSK	include/ssv6200_aux.h	16451;"	d
+RG_RX_TZ_VCM_SFT	include/ssv6200_aux.h	16453;"	d
+RG_RX_TZ_VCM_SZ	include/ssv6200_aux.h	16455;"	d
+RG_RX_ULG_LNAHGN_BIAS_HI	include/ssv6200_aux.h	16674;"	d
+RG_RX_ULG_LNAHGN_BIAS_I_MSK	include/ssv6200_aux.h	16672;"	d
+RG_RX_ULG_LNAHGN_BIAS_MSK	include/ssv6200_aux.h	16671;"	d
+RG_RX_ULG_LNAHGN_BIAS_SFT	include/ssv6200_aux.h	16673;"	d
+RG_RX_ULG_LNAHGN_BIAS_SZ	include/ssv6200_aux.h	16675;"	d
+RG_RX_ULG_LNAHGP_BIAS_HI	include/ssv6200_aux.h	16679;"	d
+RG_RX_ULG_LNAHGP_BIAS_I_MSK	include/ssv6200_aux.h	16677;"	d
+RG_RX_ULG_LNAHGP_BIAS_MSK	include/ssv6200_aux.h	16676;"	d
+RG_RX_ULG_LNAHGP_BIAS_SFT	include/ssv6200_aux.h	16678;"	d
+RG_RX_ULG_LNAHGP_BIAS_SZ	include/ssv6200_aux.h	16680;"	d
+RG_RX_ULG_LNALG_BIAS_HI	include/ssv6200_aux.h	16684;"	d
+RG_RX_ULG_LNALG_BIAS_I_MSK	include/ssv6200_aux.h	16682;"	d
+RG_RX_ULG_LNALG_BIAS_MSK	include/ssv6200_aux.h	16681;"	d
+RG_RX_ULG_LNALG_BIAS_SFT	include/ssv6200_aux.h	16683;"	d
+RG_RX_ULG_LNALG_BIAS_SZ	include/ssv6200_aux.h	16685;"	d
+RG_RX_ULG_LNA_GC_HI	include/ssv6200_aux.h	16669;"	d
+RG_RX_ULG_LNA_GC_I_MSK	include/ssv6200_aux.h	16667;"	d
+RG_RX_ULG_LNA_GC_MSK	include/ssv6200_aux.h	16666;"	d
+RG_RX_ULG_LNA_GC_SFT	include/ssv6200_aux.h	16668;"	d
+RG_RX_ULG_LNA_GC_SZ	include/ssv6200_aux.h	16670;"	d
+RG_RX_ULG_TZ_CAP_HI	include/ssv6200_aux.h	16694;"	d
+RG_RX_ULG_TZ_CAP_I_MSK	include/ssv6200_aux.h	16692;"	d
+RG_RX_ULG_TZ_CAP_MSK	include/ssv6200_aux.h	16691;"	d
+RG_RX_ULG_TZ_CAP_SFT	include/ssv6200_aux.h	16693;"	d
+RG_RX_ULG_TZ_CAP_SZ	include/ssv6200_aux.h	16695;"	d
+RG_RX_ULG_TZ_GC_HI	include/ssv6200_aux.h	16689;"	d
+RG_RX_ULG_TZ_GC_I_MSK	include/ssv6200_aux.h	16687;"	d
+RG_RX_ULG_TZ_GC_MSK	include/ssv6200_aux.h	16686;"	d
+RG_RX_ULG_TZ_GC_SFT	include/ssv6200_aux.h	16688;"	d
+RG_RX_ULG_TZ_GC_SZ	include/ssv6200_aux.h	16690;"	d
+RG_SARADC_5G_TSSI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22944;"	d
+RG_SARADC_5G_TSSI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22942;"	d
+RG_SARADC_5G_TSSI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22941;"	d
+RG_SARADC_5G_TSSI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22943;"	d
+RG_SARADC_5G_TSSI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22945;"	d
+RG_SARADC_BIT_HI	include/ssv6200_aux.h	17589;"	d
+RG_SARADC_BIT_I_MSK	include/ssv6200_aux.h	17587;"	d
+RG_SARADC_BIT_MSK	include/ssv6200_aux.h	17586;"	d
+RG_SARADC_BIT_SFT	include/ssv6200_aux.h	17588;"	d
+RG_SARADC_BIT_SZ	include/ssv6200_aux.h	17590;"	d
+RG_SARADC_THERMAL_HI	include/ssv6200_aux.h	16824;"	d
+RG_SARADC_THERMAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22959;"	d
+RG_SARADC_THERMAL_I_MSK	include/ssv6200_aux.h	16822;"	d
+RG_SARADC_THERMAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22957;"	d
+RG_SARADC_THERMAL_MSK	include/ssv6200_aux.h	16821;"	d
+RG_SARADC_THERMAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22956;"	d
+RG_SARADC_THERMAL_SFT	include/ssv6200_aux.h	16823;"	d
+RG_SARADC_THERMAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22958;"	d
+RG_SARADC_THERMAL_SZ	include/ssv6200_aux.h	16825;"	d
+RG_SARADC_THERMAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22960;"	d
+RG_SARADC_TSSI_HI	include/ssv6200_aux.h	16829;"	d
+RG_SARADC_TSSI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22964;"	d
+RG_SARADC_TSSI_I_MSK	include/ssv6200_aux.h	16827;"	d
+RG_SARADC_TSSI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22962;"	d
+RG_SARADC_TSSI_MSK	include/ssv6200_aux.h	16826;"	d
+RG_SARADC_TSSI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22961;"	d
+RG_SARADC_TSSI_SFT	include/ssv6200_aux.h	16828;"	d
+RG_SARADC_TSSI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22963;"	d
+RG_SARADC_TSSI_SZ	include/ssv6200_aux.h	16830;"	d
+RG_SARADC_TSSI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22965;"	d
+RG_SARADC_VRSEL_HI	include/ssv6200_aux.h	16814;"	d
+RG_SARADC_VRSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22949;"	d
+RG_SARADC_VRSEL_I_MSK	include/ssv6200_aux.h	16812;"	d
+RG_SARADC_VRSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22947;"	d
+RG_SARADC_VRSEL_MSK	include/ssv6200_aux.h	16811;"	d
+RG_SARADC_VRSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22946;"	d
+RG_SARADC_VRSEL_SFT	include/ssv6200_aux.h	16813;"	d
+RG_SARADC_VRSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22948;"	d
+RG_SARADC_VRSEL_SZ	include/ssv6200_aux.h	16815;"	d
+RG_SARADC_VRSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22950;"	d
+RG_SB_START_CNT_HI	include/ssv6200_aux.h	14954;"	d
+RG_SB_START_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32359;"	d
+RG_SB_START_CNT_I_MSK	include/ssv6200_aux.h	14952;"	d
+RG_SB_START_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32357;"	d
+RG_SB_START_CNT_MSK	include/ssv6200_aux.h	14951;"	d
+RG_SB_START_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32356;"	d
+RG_SB_START_CNT_SFT	include/ssv6200_aux.h	14953;"	d
+RG_SB_START_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32358;"	d
+RG_SB_START_CNT_SZ	include/ssv6200_aux.h	14955;"	d
+RG_SB_START_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32360;"	d
+RG_SCR_INIT_SEED_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31964;"	d
+RG_SCR_INIT_SEED_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31962;"	d
+RG_SCR_INIT_SEED_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31961;"	d
+RG_SCR_INIT_SEED_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31963;"	d
+RG_SCR_INIT_SEED_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31965;"	d
+RG_SCR_SEED_MANUANL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31969;"	d
+RG_SCR_SEED_MANUANL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31967;"	d
+RG_SCR_SEED_MANUANL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31966;"	d
+RG_SCR_SEED_MANUANL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31968;"	d
+RG_SCR_SEED_MANUANL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31970;"	d
+RG_SC_CTRL0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32229;"	d
+RG_SC_CTRL0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32227;"	d
+RG_SC_CTRL0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32226;"	d
+RG_SC_CTRL0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32228;"	d
+RG_SC_CTRL0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32230;"	d
+RG_SC_CTRL1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32219;"	d
+RG_SC_CTRL1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32217;"	d
+RG_SC_CTRL1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32216;"	d
+RG_SC_CTRL1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32218;"	d
+RG_SC_CTRL1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32220;"	d
+RG_SC_CTRL2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32209;"	d
+RG_SC_CTRL2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32207;"	d
+RG_SC_CTRL2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32206;"	d
+RG_SC_CTRL2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32208;"	d
+RG_SC_CTRL2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32210;"	d
+RG_SC_CTRL3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32199;"	d
+RG_SC_CTRL3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32197;"	d
+RG_SC_CTRL3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32196;"	d
+RG_SC_CTRL3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32198;"	d
+RG_SC_CTRL3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32200;"	d
+RG_SC_CTRL4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32269;"	d
+RG_SC_CTRL4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32267;"	d
+RG_SC_CTRL4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32266;"	d
+RG_SC_CTRL4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32268;"	d
+RG_SC_CTRL4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32270;"	d
+RG_SC_CTRL5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32259;"	d
+RG_SC_CTRL5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32257;"	d
+RG_SC_CTRL5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32256;"	d
+RG_SC_CTRL5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32258;"	d
+RG_SC_CTRL5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32260;"	d
+RG_SC_CTRL6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32249;"	d
+RG_SC_CTRL6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32247;"	d
+RG_SC_CTRL6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32246;"	d
+RG_SC_CTRL6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32248;"	d
+RG_SC_CTRL6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32250;"	d
+RG_SC_CTRL7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32239;"	d
+RG_SC_CTRL7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32237;"	d
+RG_SC_CTRL7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32236;"	d
+RG_SC_CTRL7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32238;"	d
+RG_SC_CTRL7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32240;"	d
+RG_SEC_CNT_VALUE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29784;"	d
+RG_SEC_CNT_VALUE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29782;"	d
+RG_SEC_CNT_VALUE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29781;"	d
+RG_SEC_CNT_VALUE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29783;"	d
+RG_SEC_CNT_VALUE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29785;"	d
+RG_SEL_DPLL_CLK_HI	include/ssv6200_aux.h	16184;"	d
+RG_SEL_DPLL_CLK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29719;"	d
+RG_SEL_DPLL_CLK_I_MSK	include/ssv6200_aux.h	16182;"	d
+RG_SEL_DPLL_CLK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29717;"	d
+RG_SEL_DPLL_CLK_MSK	include/ssv6200_aux.h	16181;"	d
+RG_SEL_DPLL_CLK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29716;"	d
+RG_SEL_DPLL_CLK_SFT	include/ssv6200_aux.h	16183;"	d
+RG_SEL_DPLL_CLK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29718;"	d
+RG_SEL_DPLL_CLK_SZ	include/ssv6200_aux.h	16185;"	d
+RG_SEL_DPLL_CLK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29720;"	d
+RG_SERVICE_HI	include/ssv6200_aux.h	13174;"	d
+RG_SERVICE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30364;"	d
+RG_SERVICE_I_MSK	include/ssv6200_aux.h	13172;"	d
+RG_SERVICE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30362;"	d
+RG_SERVICE_MSK	include/ssv6200_aux.h	13171;"	d
+RG_SERVICE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30361;"	d
+RG_SERVICE_SFT	include/ssv6200_aux.h	13173;"	d
+RG_SERVICE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30363;"	d
+RG_SERVICE_SZ	include/ssv6200_aux.h	13175;"	d
+RG_SERVICE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30365;"	d
+RG_SFD_BIT_CNT_LMT_HI	include/ssv6200_aux.h	14564;"	d
+RG_SFD_BIT_CNT_LMT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31729;"	d
+RG_SFD_BIT_CNT_LMT_I_MSK	include/ssv6200_aux.h	14562;"	d
+RG_SFD_BIT_CNT_LMT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31727;"	d
+RG_SFD_BIT_CNT_LMT_MSK	include/ssv6200_aux.h	14561;"	d
+RG_SFD_BIT_CNT_LMT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31726;"	d
+RG_SFD_BIT_CNT_LMT_SFT	include/ssv6200_aux.h	14563;"	d
+RG_SFD_BIT_CNT_LMT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31728;"	d
+RG_SFD_BIT_CNT_LMT_SZ	include/ssv6200_aux.h	14565;"	d
+RG_SFD_BIT_CNT_LMT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31730;"	d
+RG_SHIFT_DR_16_HI	include/ssv6200_aux.h	13974;"	d
+RG_SHIFT_DR_16_I_MSK	include/ssv6200_aux.h	13972;"	d
+RG_SHIFT_DR_16_MSK	include/ssv6200_aux.h	13971;"	d
+RG_SHIFT_DR_16_SFT	include/ssv6200_aux.h	13973;"	d
+RG_SHIFT_DR_16_SZ	include/ssv6200_aux.h	13975;"	d
+RG_SHIFT_DR_64_HI	include/ssv6200_aux.h	15164;"	d
+RG_SHIFT_DR_64_I_MSK	include/ssv6200_aux.h	15162;"	d
+RG_SHIFT_DR_64_MSK	include/ssv6200_aux.h	15161;"	d
+RG_SHIFT_DR_64_SFT	include/ssv6200_aux.h	15163;"	d
+RG_SHIFT_DR_64_SZ	include/ssv6200_aux.h	15165;"	d
+RG_SHIFT_DR_80_HI	include/ssv6200_aux.h	15129;"	d
+RG_SHIFT_DR_80_I_MSK	include/ssv6200_aux.h	15127;"	d
+RG_SHIFT_DR_80_MSK	include/ssv6200_aux.h	15126;"	d
+RG_SHIFT_DR_80_SFT	include/ssv6200_aux.h	15128;"	d
+RG_SHIFT_DR_80_SZ	include/ssv6200_aux.h	15130;"	d
+RG_SHORTGI_HI	include/ssv6200_aux.h	13154;"	d
+RG_SHORTGI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30344;"	d
+RG_SHORTGI_I_MSK	include/ssv6200_aux.h	13152;"	d
+RG_SHORTGI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30342;"	d
+RG_SHORTGI_MSK	include/ssv6200_aux.h	13151;"	d
+RG_SHORTGI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30341;"	d
+RG_SHORTGI_SFT	include/ssv6200_aux.h	13153;"	d
+RG_SHORTGI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30343;"	d
+RG_SHORTGI_SZ	include/ssv6200_aux.h	13155;"	d
+RG_SHORTGI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30345;"	d
+RG_SHORT_GI_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31929;"	d
+RG_SHORT_GI_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31927;"	d
+RG_SHORT_GI_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31926;"	d
+RG_SHORT_GI_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31928;"	d
+RG_SHORT_GI_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31930;"	d
+RG_SIGN_SWAP_BB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30204;"	d
+RG_SIGN_SWAP_BB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30202;"	d
+RG_SIGN_SWAP_BB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30201;"	d
+RG_SIGN_SWAP_BB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30203;"	d
+RG_SIGN_SWAP_BB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30205;"	d
+RG_SIGN_SWAP_HI	include/ssv6200_aux.h	12994;"	d
+RG_SIGN_SWAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27234;"	d
+RG_SIGN_SWAP_I_MSK	include/ssv6200_aux.h	12992;"	d
+RG_SIGN_SWAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27232;"	d
+RG_SIGN_SWAP_MSK	include/ssv6200_aux.h	12991;"	d
+RG_SIGN_SWAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27231;"	d
+RG_SIGN_SWAP_SFT	include/ssv6200_aux.h	12993;"	d
+RG_SIGN_SWAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27233;"	d
+RG_SIGN_SWAP_SZ	include/ssv6200_aux.h	12995;"	d
+RG_SIGN_SWAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27235;"	d
+RG_SIMULATION_MODE_16_HI	include/ssv6200_aux.h	13984;"	d
+RG_SIMULATION_MODE_16_I_MSK	include/ssv6200_aux.h	13982;"	d
+RG_SIMULATION_MODE_16_MSK	include/ssv6200_aux.h	13981;"	d
+RG_SIMULATION_MODE_16_SFT	include/ssv6200_aux.h	13983;"	d
+RG_SIMULATION_MODE_16_SZ	include/ssv6200_aux.h	13985;"	d
+RG_SIMULATION_MODE_64_HI	include/ssv6200_aux.h	15174;"	d
+RG_SIMULATION_MODE_64_I_MSK	include/ssv6200_aux.h	15172;"	d
+RG_SIMULATION_MODE_64_MSK	include/ssv6200_aux.h	15171;"	d
+RG_SIMULATION_MODE_64_SFT	include/ssv6200_aux.h	15173;"	d
+RG_SIMULATION_MODE_64_SZ	include/ssv6200_aux.h	15175;"	d
+RG_SIMULATION_MODE_80_HI	include/ssv6200_aux.h	15139;"	d
+RG_SIMULATION_MODE_80_I_MSK	include/ssv6200_aux.h	15137;"	d
+RG_SIMULATION_MODE_80_MSK	include/ssv6200_aux.h	15136;"	d
+RG_SIMULATION_MODE_80_SFT	include/ssv6200_aux.h	15138;"	d
+RG_SIMULATION_MODE_80_SZ	include/ssv6200_aux.h	15140;"	d
+RG_SLEEP_METHOD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29769;"	d
+RG_SLEEP_METHOD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29767;"	d
+RG_SLEEP_METHOD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29766;"	d
+RG_SLEEP_METHOD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29768;"	d
+RG_SLEEP_METHOD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29770;"	d
+RG_SLEEP_WAKE_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29779;"	d
+RG_SLEEP_WAKE_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29777;"	d
+RG_SLEEP_WAKE_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29776;"	d
+RG_SLEEP_WAKE_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29778;"	d
+RG_SLEEP_WAKE_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29780;"	d
+RG_SMB_DEF_HI	include/ssv6200_aux.h	14704;"	d
+RG_SMB_DEF_I_MSK	include/ssv6200_aux.h	14702;"	d
+RG_SMB_DEF_MSK	include/ssv6200_aux.h	14701;"	d
+RG_SMB_DEF_SFT	include/ssv6200_aux.h	14703;"	d
+RG_SMB_DEF_SZ	include/ssv6200_aux.h	14705;"	d
+RG_SMOOTHING_HI	include/ssv6200_aux.h	13179;"	d
+RG_SMOOTHING_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30369;"	d
+RG_SMOOTHING_I_MSK	include/ssv6200_aux.h	13177;"	d
+RG_SMOOTHING_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30367;"	d
+RG_SMOOTHING_MSK	include/ssv6200_aux.h	13176;"	d
+RG_SMOOTHING_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30366;"	d
+RG_SMOOTHING_SFT	include/ssv6200_aux.h	13178;"	d
+RG_SMOOTHING_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30368;"	d
+RG_SMOOTHING_SZ	include/ssv6200_aux.h	13180;"	d
+RG_SMOOTHING_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30370;"	d
+RG_SNR_TH_16QAM_HI	include/ssv6200_aux.h	14929;"	d
+RG_SNR_TH_16QAM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32169;"	d
+RG_SNR_TH_16QAM_I_MSK	include/ssv6200_aux.h	14927;"	d
+RG_SNR_TH_16QAM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32167;"	d
+RG_SNR_TH_16QAM_MSK	include/ssv6200_aux.h	14926;"	d
+RG_SNR_TH_16QAM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32166;"	d
+RG_SNR_TH_16QAM_SFT	include/ssv6200_aux.h	14928;"	d
+RG_SNR_TH_16QAM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32168;"	d
+RG_SNR_TH_16QAM_SZ	include/ssv6200_aux.h	14930;"	d
+RG_SNR_TH_16QAM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32170;"	d
+RG_SNR_TH_64QAM_HI	include/ssv6200_aux.h	14924;"	d
+RG_SNR_TH_64QAM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32164;"	d
+RG_SNR_TH_64QAM_I_MSK	include/ssv6200_aux.h	14922;"	d
+RG_SNR_TH_64QAM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32162;"	d
+RG_SNR_TH_64QAM_MSK	include/ssv6200_aux.h	14921;"	d
+RG_SNR_TH_64QAM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32161;"	d
+RG_SNR_TH_64QAM_SFT	include/ssv6200_aux.h	14923;"	d
+RG_SNR_TH_64QAM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32163;"	d
+RG_SNR_TH_64QAM_SZ	include/ssv6200_aux.h	14925;"	d
+RG_SNR_TH_64QAM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32165;"	d
+RG_SOFT_RST_N_11B_RX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31864;"	d
+RG_SOFT_RST_N_11B_RX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31862;"	d
+RG_SOFT_RST_N_11B_RX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31861;"	d
+RG_SOFT_RST_N_11B_RX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31863;"	d
+RG_SOFT_RST_N_11B_RX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31865;"	d
+RG_SOFT_RST_N_11GN_RX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32704;"	d
+RG_SOFT_RST_N_11GN_RX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32702;"	d
+RG_SOFT_RST_N_11GN_RX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32701;"	d
+RG_SOFT_RST_N_11GN_RX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32703;"	d
+RG_SOFT_RST_N_11GN_RX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32705;"	d
+RG_SPECTRUM_BW_HI	include/ssv6200_aux.h	13029;"	d
+RG_SPECTRUM_BW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27474;"	d
+RG_SPECTRUM_BW_I_MSK	include/ssv6200_aux.h	13027;"	d
+RG_SPECTRUM_BW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27472;"	d
+RG_SPECTRUM_BW_MSK	include/ssv6200_aux.h	13026;"	d
+RG_SPECTRUM_BW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27471;"	d
+RG_SPECTRUM_BW_SFT	include/ssv6200_aux.h	13028;"	d
+RG_SPECTRUM_BW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27473;"	d
+RG_SPECTRUM_BW_SZ	include/ssv6200_aux.h	13030;"	d
+RG_SPECTRUM_BW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27475;"	d
+RG_SPECTRUM_EN_HI	include/ssv6200_aux.h	13039;"	d
+RG_SPECTRUM_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27479;"	d
+RG_SPECTRUM_EN_I_MSK	include/ssv6200_aux.h	13037;"	d
+RG_SPECTRUM_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27477;"	d
+RG_SPECTRUM_EN_MSK	include/ssv6200_aux.h	13036;"	d
+RG_SPECTRUM_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27476;"	d
+RG_SPECTRUM_EN_SFT	include/ssv6200_aux.h	13038;"	d
+RG_SPECTRUM_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27478;"	d
+RG_SPECTRUM_EN_SZ	include/ssv6200_aux.h	13040;"	d
+RG_SPECTRUM_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27480;"	d
+RG_SPECTRUM_FREQ_HI	include/ssv6200_aux.h	13124;"	d
+RG_SPECTRUM_FREQ_I_MSK	include/ssv6200_aux.h	13122;"	d
+RG_SPECTRUM_FREQ_MANUAL_HI	include/ssv6200_aux.h	13034;"	d
+RG_SPECTRUM_FREQ_MANUAL_I_MSK	include/ssv6200_aux.h	13032;"	d
+RG_SPECTRUM_FREQ_MANUAL_MSK	include/ssv6200_aux.h	13031;"	d
+RG_SPECTRUM_FREQ_MANUAL_SFT	include/ssv6200_aux.h	13033;"	d
+RG_SPECTRUM_FREQ_MANUAL_SZ	include/ssv6200_aux.h	13035;"	d
+RG_SPECTRUM_FREQ_MSK	include/ssv6200_aux.h	13121;"	d
+RG_SPECTRUM_FREQ_SFT	include/ssv6200_aux.h	13123;"	d
+RG_SPECTRUM_FREQ_SZ	include/ssv6200_aux.h	13125;"	d
+RG_SPECTRUM_LEAKY_FACTOR_HI	include/ssv6200_aux.h	13024;"	d
+RG_SPECTRUM_LEAKY_FACTOR_I_MSK	include/ssv6200_aux.h	13022;"	d
+RG_SPECTRUM_LEAKY_FACTOR_MSK	include/ssv6200_aux.h	13021;"	d
+RG_SPECTRUM_LEAKY_FACTOR_SFT	include/ssv6200_aux.h	13023;"	d
+RG_SPECTRUM_LEAKY_FACTOR_SZ	include/ssv6200_aux.h	13025;"	d
+RG_SPECTRUM_LO_FIX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27614;"	d
+RG_SPECTRUM_LO_FIX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27612;"	d
+RG_SPECTRUM_LO_FIX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27611;"	d
+RG_SPECTRUM_LO_FIX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27613;"	d
+RG_SPECTRUM_LO_FIX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27615;"	d
+RG_SPECTRUM_PWR_UPDATE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27619;"	d
+RG_SPECTRUM_PWR_UPDATE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27617;"	d
+RG_SPECTRUM_PWR_UPDATE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27616;"	d
+RG_SPECTRUM_PWR_UPDATE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27618;"	d
+RG_SPECTRUM_PWR_UPDATE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27620;"	d
+RG_STBC_EN_HI	include/ssv6200_aux.h	15314;"	d
+RG_STBC_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32714;"	d
+RG_STBC_EN_I_MSK	include/ssv6200_aux.h	15312;"	d
+RG_STBC_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32712;"	d
+RG_STBC_EN_MSK	include/ssv6200_aux.h	15311;"	d
+RG_STBC_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32711;"	d
+RG_STBC_EN_SFT	include/ssv6200_aux.h	15313;"	d
+RG_STBC_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32713;"	d
+RG_STBC_EN_SZ	include/ssv6200_aux.h	15315;"	d
+RG_STBC_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32715;"	d
+RG_STBC_HI	include/ssv6200_aux.h	13194;"	d
+RG_STBC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30384;"	d
+RG_STBC_I_MSK	include/ssv6200_aux.h	13192;"	d
+RG_STBC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30382;"	d
+RG_STBC_MSK	include/ssv6200_aux.h	13191;"	d
+RG_STBC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30381;"	d
+RG_STBC_SFT	include/ssv6200_aux.h	13193;"	d
+RG_STBC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30383;"	d
+RG_STBC_SZ	include/ssv6200_aux.h	13195;"	d
+RG_STBC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30385;"	d
+RG_STF_SCALE_20_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31934;"	d
+RG_STF_SCALE_20_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31932;"	d
+RG_STF_SCALE_20_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31931;"	d
+RG_STF_SCALE_20_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31933;"	d
+RG_STF_SCALE_20_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31935;"	d
+RG_STF_SCALE_40_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31939;"	d
+RG_STF_SCALE_40_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31937;"	d
+RG_STF_SCALE_40_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31936;"	d
+RG_STF_SCALE_40_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31938;"	d
+RG_STF_SCALE_40_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31940;"	d
+RG_SUB_DC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27204;"	d
+RG_SUB_DC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27202;"	d
+RG_SUB_DC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27201;"	d
+RG_SUB_DC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27203;"	d
+RG_SUB_DC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27205;"	d
+RG_SW_FALL_TIME_HI	include/ssv6200_aux.h	13864;"	d
+RG_SW_FALL_TIME_I_MSK	include/ssv6200_aux.h	13862;"	d
+RG_SW_FALL_TIME_MSK	include/ssv6200_aux.h	13861;"	d
+RG_SW_FALL_TIME_SFT	include/ssv6200_aux.h	13863;"	d
+RG_SW_FALL_TIME_SZ	include/ssv6200_aux.h	13865;"	d
+RG_SW_RISE_TIME_HI	include/ssv6200_aux.h	13844;"	d
+RG_SW_RISE_TIME_I_MSK	include/ssv6200_aux.h	13842;"	d
+RG_SW_RISE_TIME_MSK	include/ssv6200_aux.h	13841;"	d
+RG_SW_RISE_TIME_SFT	include/ssv6200_aux.h	13843;"	d
+RG_SW_RISE_TIME_SZ	include/ssv6200_aux.h	13845;"	d
+RG_SX5GB_AAC_ACCUMH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26224;"	d
+RG_SX5GB_AAC_ACCUMH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26222;"	d
+RG_SX5GB_AAC_ACCUMH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26221;"	d
+RG_SX5GB_AAC_ACCUMH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26223;"	d
+RG_SX5GB_AAC_ACCUMH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26225;"	d
+RG_SX5GB_AAC_ACCUML_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26229;"	d
+RG_SX5GB_AAC_ACCUML_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26227;"	d
+RG_SX5GB_AAC_ACCUML_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26226;"	d
+RG_SX5GB_AAC_ACCUML_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26228;"	d
+RG_SX5GB_AAC_ACCUML_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26230;"	d
+RG_SX5GB_AAC_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26249;"	d
+RG_SX5GB_AAC_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26247;"	d
+RG_SX5GB_AAC_EN_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26244;"	d
+RG_SX5GB_AAC_EN_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26242;"	d
+RG_SX5GB_AAC_EN_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26241;"	d
+RG_SX5GB_AAC_EN_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26243;"	d
+RG_SX5GB_AAC_EN_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26245;"	d
+RG_SX5GB_AAC_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26246;"	d
+RG_SX5GB_AAC_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26248;"	d
+RG_SX5GB_AAC_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26250;"	d
+RG_SX5GB_AAC_EVA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26259;"	d
+RG_SX5GB_AAC_EVA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26257;"	d
+RG_SX5GB_AAC_EVA_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26254;"	d
+RG_SX5GB_AAC_EVA_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26252;"	d
+RG_SX5GB_AAC_EVA_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26251;"	d
+RG_SX5GB_AAC_EVA_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26253;"	d
+RG_SX5GB_AAC_EVA_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26255;"	d
+RG_SX5GB_AAC_EVA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26256;"	d
+RG_SX5GB_AAC_EVA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26258;"	d
+RG_SX5GB_AAC_EVA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26260;"	d
+RG_SX5GB_AAC_EVA_TS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26239;"	d
+RG_SX5GB_AAC_EVA_TS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26237;"	d
+RG_SX5GB_AAC_EVA_TS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26236;"	d
+RG_SX5GB_AAC_EVA_TS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26238;"	d
+RG_SX5GB_AAC_EVA_TS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26240;"	d
+RG_SX5GB_AAC_INIT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26234;"	d
+RG_SX5GB_AAC_INIT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26232;"	d
+RG_SX5GB_AAC_INIT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26231;"	d
+RG_SX5GB_AAC_INIT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26233;"	d
+RG_SX5GB_AAC_INIT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26235;"	d
+RG_SX5GB_AAC_TEST_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26289;"	d
+RG_SX5GB_AAC_TEST_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26287;"	d
+RG_SX5GB_AAC_TEST_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26286;"	d
+RG_SX5GB_AAC_TEST_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26288;"	d
+RG_SX5GB_AAC_TEST_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26290;"	d
+RG_SX5GB_AAC_TEST_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26294;"	d
+RG_SX5GB_AAC_TEST_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26292;"	d
+RG_SX5GB_AAC_TEST_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26291;"	d
+RG_SX5GB_AAC_TEST_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26293;"	d
+RG_SX5GB_AAC_TEST_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26295;"	d
+RG_SX5GB_CAL_INIT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25764;"	d
+RG_SX5GB_CAL_INIT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25762;"	d
+RG_SX5GB_CAL_INIT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25761;"	d
+RG_SX5GB_CAL_INIT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25763;"	d
+RG_SX5GB_CAL_INIT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25765;"	d
+RG_SX5GB_CHANNEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25614;"	d
+RG_SX5GB_CHANNEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25612;"	d
+RG_SX5GB_CHANNEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25611;"	d
+RG_SX5GB_CHANNEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25613;"	d
+RG_SX5GB_CHANNEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25615;"	d
+RG_SX5GB_CP_IOST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25904;"	d
+RG_SX5GB_CP_IOST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25902;"	d
+RG_SX5GB_CP_IOST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25901;"	d
+RG_SX5GB_CP_IOST_POL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25899;"	d
+RG_SX5GB_CP_IOST_POL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25897;"	d
+RG_SX5GB_CP_IOST_POL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25896;"	d
+RG_SX5GB_CP_IOST_POL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25898;"	d
+RG_SX5GB_CP_IOST_POL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25900;"	d
+RG_SX5GB_CP_IOST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25903;"	d
+RG_SX5GB_CP_IOST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25905;"	d
+RG_SX5GB_CP_ISEL50U_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25889;"	d
+RG_SX5GB_CP_ISEL50U_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25887;"	d
+RG_SX5GB_CP_ISEL50U_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25886;"	d
+RG_SX5GB_CP_ISEL50U_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25888;"	d
+RG_SX5GB_CP_ISEL50U_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25890;"	d
+RG_SX5GB_CP_ISEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25884;"	d
+RG_SX5GB_CP_ISEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25882;"	d
+RG_SX5GB_CP_ISEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25881;"	d
+RG_SX5GB_CP_ISEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25883;"	d
+RG_SX5GB_CP_ISEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25885;"	d
+RG_SX5GB_CP_KP_DOUB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25894;"	d
+RG_SX5GB_CP_KP_DOUB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25892;"	d
+RG_SX5GB_CP_KP_DOUB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25891;"	d
+RG_SX5GB_CP_KP_DOUB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25893;"	d
+RG_SX5GB_CP_KP_DOUB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25895;"	d
+RG_SX5GB_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26749;"	d
+RG_SX5GB_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26747;"	d
+RG_SX5GB_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26746;"	d
+RG_SX5GB_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26748;"	d
+RG_SX5GB_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26750;"	d
+RG_SX5GB_DITHER_WEIGHT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26149;"	d
+RG_SX5GB_DITHER_WEIGHT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26147;"	d
+RG_SX5GB_DITHER_WEIGHT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26146;"	d
+RG_SX5GB_DITHER_WEIGHT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26148;"	d
+RG_SX5GB_DITHER_WEIGHT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26150;"	d
+RG_SX5GB_DIV_DMYBUF_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26129;"	d
+RG_SX5GB_DIV_DMYBUF_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26127;"	d
+RG_SX5GB_DIV_DMYBUF_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26126;"	d
+RG_SX5GB_DIV_DMYBUF_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26128;"	d
+RG_SX5GB_DIV_DMYBUF_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26130;"	d
+RG_SX5GB_DIV_PREVDD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26109;"	d
+RG_SX5GB_DIV_PREVDD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26107;"	d
+RG_SX5GB_DIV_PREVDD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26106;"	d
+RG_SX5GB_DIV_PREVDD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26108;"	d
+RG_SX5GB_DIV_PREVDD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26110;"	d
+RG_SX5GB_DIV_PSCVDD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26114;"	d
+RG_SX5GB_DIV_PSCVDD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26112;"	d
+RG_SX5GB_DIV_PSCVDD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26111;"	d
+RG_SX5GB_DIV_PSCVDD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26113;"	d
+RG_SX5GB_DIV_PSCVDD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26115;"	d
+RG_SX5GB_DIV_RST_H_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26119;"	d
+RG_SX5GB_DIV_RST_H_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26117;"	d
+RG_SX5GB_DIV_RST_H_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26116;"	d
+RG_SX5GB_DIV_RST_H_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26118;"	d
+RG_SX5GB_DIV_RST_H_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26120;"	d
+RG_SX5GB_DIV_SDM_EDGE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26124;"	d
+RG_SX5GB_DIV_SDM_EDGE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26122;"	d
+RG_SX5GB_DIV_SDM_EDGE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26121;"	d
+RG_SX5GB_DIV_SDM_EDGE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26123;"	d
+RG_SX5GB_DIV_SDM_EDGE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26125;"	d
+RG_SX5GB_LDO_CP_LEVEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25024;"	d
+RG_SX5GB_LDO_CP_LEVEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25022;"	d
+RG_SX5GB_LDO_CP_LEVEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25021;"	d
+RG_SX5GB_LDO_CP_LEVEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25023;"	d
+RG_SX5GB_LDO_CP_LEVEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25025;"	d
+RG_SX5GB_LDO_DIV_LEVEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25049;"	d
+RG_SX5GB_LDO_DIV_LEVEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25047;"	d
+RG_SX5GB_LDO_DIV_LEVEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25046;"	d
+RG_SX5GB_LDO_DIV_LEVEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25048;"	d
+RG_SX5GB_LDO_DIV_LEVEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25050;"	d
+RG_SX5GB_LDO_FCOFFT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25834;"	d
+RG_SX5GB_LDO_FCOFFT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25832;"	d
+RG_SX5GB_LDO_FCOFFT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25831;"	d
+RG_SX5GB_LDO_FCOFFT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25833;"	d
+RG_SX5GB_LDO_FCOFFT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25835;"	d
+RG_SX5GB_LDO_LO_LEVEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25034;"	d
+RG_SX5GB_LDO_LO_LEVEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25032;"	d
+RG_SX5GB_LDO_LO_LEVEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25031;"	d
+RG_SX5GB_LDO_LO_LEVEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25033;"	d
+RG_SX5GB_LDO_LO_LEVEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25035;"	d
+RG_SX5GB_LDO_VCO_LEVEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25044;"	d
+RG_SX5GB_LDO_VCO_LEVEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25042;"	d
+RG_SX5GB_LDO_VCO_LEVEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25041;"	d
+RG_SX5GB_LDO_VCO_LEVEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25043;"	d
+RG_SX5GB_LDO_VCO_LEVEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25045;"	d
+RG_SX5GB_LO_TIMES_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25609;"	d
+RG_SX5GB_LO_TIMES_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25607;"	d
+RG_SX5GB_LO_TIMES_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25606;"	d
+RG_SX5GB_LO_TIMES_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25608;"	d
+RG_SX5GB_LO_TIMES_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25610;"	d
+RG_SX5GB_LPF_C1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25954;"	d
+RG_SX5GB_LPF_C1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25952;"	d
+RG_SX5GB_LPF_C1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25951;"	d
+RG_SX5GB_LPF_C1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25953;"	d
+RG_SX5GB_LPF_C1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25955;"	d
+RG_SX5GB_LPF_C2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25959;"	d
+RG_SX5GB_LPF_C2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25957;"	d
+RG_SX5GB_LPF_C2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25956;"	d
+RG_SX5GB_LPF_C2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25958;"	d
+RG_SX5GB_LPF_C2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25960;"	d
+RG_SX5GB_LPF_C3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25964;"	d
+RG_SX5GB_LPF_C3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25962;"	d
+RG_SX5GB_LPF_C3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25961;"	d
+RG_SX5GB_LPF_C3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25963;"	d
+RG_SX5GB_LPF_C3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25965;"	d
+RG_SX5GB_LPF_R2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25969;"	d
+RG_SX5GB_LPF_R2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25967;"	d
+RG_SX5GB_LPF_R2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25966;"	d
+RG_SX5GB_LPF_R2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25968;"	d
+RG_SX5GB_LPF_R2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25970;"	d
+RG_SX5GB_LPF_R3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25974;"	d
+RG_SX5GB_LPF_R3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25972;"	d
+RG_SX5GB_LPF_R3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25971;"	d
+RG_SX5GB_LPF_R3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25973;"	d
+RG_SX5GB_LPF_R3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25975;"	d
+RG_SX5GB_LPF_VTUNE_TEST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26019;"	d
+RG_SX5GB_LPF_VTUNE_TEST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26017;"	d
+RG_SX5GB_LPF_VTUNE_TEST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26016;"	d
+RG_SX5GB_LPF_VTUNE_TEST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26018;"	d
+RG_SX5GB_LPF_VTUNE_TEST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26020;"	d
+RG_SX5GB_MIXAAC_DIS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25749;"	d
+RG_SX5GB_MIXAAC_DIS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25747;"	d
+RG_SX5GB_MIXAAC_DIS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25746;"	d
+RG_SX5GB_MIXAAC_DIS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25748;"	d
+RG_SX5GB_MIXAAC_DIS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25750;"	d
+RG_SX5GB_MIXAAC_TAR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26299;"	d
+RG_SX5GB_MIXAAC_TAR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26297;"	d
+RG_SX5GB_MIXAAC_TAR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26296;"	d
+RG_SX5GB_MIXAAC_TAR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26298;"	d
+RG_SX5GB_MIXAAC_TAR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26300;"	d
+RG_SX5GB_MOD_ORDER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26144;"	d
+RG_SX5GB_MOD_ORDER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26142;"	d
+RG_SX5GB_MOD_ORDER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26141;"	d
+RG_SX5GB_MOD_ORDER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26143;"	d
+RG_SX5GB_MOD_ORDER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26145;"	d
+RG_SX5GB_PFD_DIV_EDGE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25949;"	d
+RG_SX5GB_PFD_DIV_EDGE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25947;"	d
+RG_SX5GB_PFD_DIV_EDGE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25946;"	d
+RG_SX5GB_PFD_DIV_EDGE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25948;"	d
+RG_SX5GB_PFD_DIV_EDGE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25950;"	d
+RG_SX5GB_PFD_REF_EDGE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25944;"	d
+RG_SX5GB_PFD_REF_EDGE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25942;"	d
+RG_SX5GB_PFD_REF_EDGE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25941;"	d
+RG_SX5GB_PFD_REF_EDGE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25943;"	d
+RG_SX5GB_PFD_REF_EDGE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25945;"	d
+RG_SX5GB_PFD_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25664;"	d
+RG_SX5GB_PFD_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25662;"	d
+RG_SX5GB_PFD_RST_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25659;"	d
+RG_SX5GB_PFD_RST_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25657;"	d
+RG_SX5GB_PFD_RST_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25656;"	d
+RG_SX5GB_PFD_RST_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25658;"	d
+RG_SX5GB_PFD_RST_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25660;"	d
+RG_SX5GB_PFD_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25661;"	d
+RG_SX5GB_PFD_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25663;"	d
+RG_SX5GB_PFD_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25665;"	d
+RG_SX5GB_PFD_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25909;"	d
+RG_SX5GB_PFD_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25907;"	d
+RG_SX5GB_PFD_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25906;"	d
+RG_SX5GB_PFD_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25908;"	d
+RG_SX5GB_PFD_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25910;"	d
+RG_SX5GB_PFD_SET1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25919;"	d
+RG_SX5GB_PFD_SET1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25917;"	d
+RG_SX5GB_PFD_SET1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25916;"	d
+RG_SX5GB_PFD_SET1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25918;"	d
+RG_SX5GB_PFD_SET1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25920;"	d
+RG_SX5GB_PFD_SET2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25924;"	d
+RG_SX5GB_PFD_SET2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25922;"	d
+RG_SX5GB_PFD_SET2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25921;"	d
+RG_SX5GB_PFD_SET2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25923;"	d
+RG_SX5GB_PFD_SET2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25925;"	d
+RG_SX5GB_PFD_SET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25914;"	d
+RG_SX5GB_PFD_SET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25912;"	d
+RG_SX5GB_PFD_SET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25911;"	d
+RG_SX5GB_PFD_SET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25913;"	d
+RG_SX5GB_PFD_SET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25915;"	d
+RG_SX5GB_PFD_TLSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25939;"	d
+RG_SX5GB_PFD_TLSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25937;"	d
+RG_SX5GB_PFD_TLSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25936;"	d
+RG_SX5GB_PFD_TLSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25938;"	d
+RG_SX5GB_PFD_TLSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25940;"	d
+RG_SX5GB_PFD_TRDN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25934;"	d
+RG_SX5GB_PFD_TRDN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25932;"	d
+RG_SX5GB_PFD_TRDN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25931;"	d
+RG_SX5GB_PFD_TRDN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25933;"	d
+RG_SX5GB_PFD_TRDN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25935;"	d
+RG_SX5GB_PFD_TRUP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25929;"	d
+RG_SX5GB_PFD_TRUP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25927;"	d
+RG_SX5GB_PFD_TRUP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25926;"	d
+RG_SX5GB_PFD_TRUP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25928;"	d
+RG_SX5GB_PFD_TRUP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25930;"	d
+RG_SX5GB_REPAAC_DIS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25754;"	d
+RG_SX5GB_REPAAC_DIS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25752;"	d
+RG_SX5GB_REPAAC_DIS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25751;"	d
+RG_SX5GB_REPAAC_DIS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25753;"	d
+RG_SX5GB_REPAAC_DIS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25755;"	d
+RG_SX5GB_REPAAC_TAR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26314;"	d
+RG_SX5GB_REPAAC_TAR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26312;"	d
+RG_SX5GB_REPAAC_TAR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26311;"	d
+RG_SX5GB_REPAAC_TAR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26313;"	d
+RG_SX5GB_REPAAC_TAR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26315;"	d
+RG_SX5GB_RFCH_MAP_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25604;"	d
+RG_SX5GB_RFCH_MAP_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25602;"	d
+RG_SX5GB_RFCH_MAP_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25601;"	d
+RG_SX5GB_RFCH_MAP_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25603;"	d
+RG_SX5GB_RFCH_MAP_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25605;"	d
+RG_SX5GB_RFCTRL_CH_10_8_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25599;"	d
+RG_SX5GB_RFCTRL_CH_10_8_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25597;"	d
+RG_SX5GB_RFCTRL_CH_10_8_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25596;"	d
+RG_SX5GB_RFCTRL_CH_10_8_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25598;"	d
+RG_SX5GB_RFCTRL_CH_10_8_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25600;"	d
+RG_SX5GB_RFCTRL_CH_7_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25594;"	d
+RG_SX5GB_RFCTRL_CH_7_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25592;"	d
+RG_SX5GB_RFCTRL_CH_7_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25591;"	d
+RG_SX5GB_RFCTRL_CH_7_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25593;"	d
+RG_SX5GB_RFCTRL_CH_7_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25595;"	d
+RG_SX5GB_RFCTRL_F_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25589;"	d
+RG_SX5GB_RFCTRL_F_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25587;"	d
+RG_SX5GB_RFCTRL_F_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25586;"	d
+RG_SX5GB_RFCTRL_F_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25588;"	d
+RG_SX5GB_RFCTRL_F_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25590;"	d
+RG_SX5GB_SBCAL_2ND_DIS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25734;"	d
+RG_SX5GB_SBCAL_2ND_DIS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25732;"	d
+RG_SX5GB_SBCAL_2ND_DIS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25731;"	d
+RG_SX5GB_SBCAL_2ND_DIS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25733;"	d
+RG_SX5GB_SBCAL_2ND_DIS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25735;"	d
+RG_SX5GB_SBCAL_AW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25739;"	d
+RG_SX5GB_SBCAL_AW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25737;"	d
+RG_SX5GB_SBCAL_AW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25736;"	d
+RG_SX5GB_SBCAL_AW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25738;"	d
+RG_SX5GB_SBCAL_AW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25740;"	d
+RG_SX5GB_SBCAL_CT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26184;"	d
+RG_SX5GB_SBCAL_CT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26182;"	d
+RG_SX5GB_SBCAL_CT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26181;"	d
+RG_SX5GB_SBCAL_CT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26183;"	d
+RG_SX5GB_SBCAL_CT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26185;"	d
+RG_SX5GB_SBCAL_DIFFMIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26194;"	d
+RG_SX5GB_SBCAL_DIFFMIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26192;"	d
+RG_SX5GB_SBCAL_DIFFMIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26191;"	d
+RG_SX5GB_SBCAL_DIFFMIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26193;"	d
+RG_SX5GB_SBCAL_DIFFMIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26195;"	d
+RG_SX5GB_SBCAL_DIS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25729;"	d
+RG_SX5GB_SBCAL_DIS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25727;"	d
+RG_SX5GB_SBCAL_DIS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25726;"	d
+RG_SX5GB_SBCAL_DIS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25728;"	d
+RG_SX5GB_SBCAL_DIS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25730;"	d
+RG_SX5GB_SBCAL_NTARG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26204;"	d
+RG_SX5GB_SBCAL_NTARG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26202;"	d
+RG_SX5GB_SBCAL_NTARG_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26199;"	d
+RG_SX5GB_SBCAL_NTARG_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26197;"	d
+RG_SX5GB_SBCAL_NTARG_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26196;"	d
+RG_SX5GB_SBCAL_NTARG_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26198;"	d
+RG_SX5GB_SBCAL_NTARG_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26200;"	d
+RG_SX5GB_SBCAL_NTARG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26201;"	d
+RG_SX5GB_SBCAL_NTARG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26203;"	d
+RG_SX5GB_SBCAL_NTARG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26205;"	d
+RG_SX5GB_SBCAL_WT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26189;"	d
+RG_SX5GB_SBCAL_WT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26187;"	d
+RG_SX5GB_SBCAL_WT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26186;"	d
+RG_SX5GB_SBCAL_WT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26188;"	d
+RG_SX5GB_SBCAL_WT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26190;"	d
+RG_SX5GB_SUB_C0P5_DIS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26179;"	d
+RG_SX5GB_SUB_C0P5_DIS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26177;"	d
+RG_SX5GB_SUB_C0P5_DIS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26176;"	d
+RG_SX5GB_SUB_C0P5_DIS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26178;"	d
+RG_SX5GB_SUB_C0P5_DIS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26180;"	d
+RG_SX5GB_SUB_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26174;"	d
+RG_SX5GB_SUB_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26172;"	d
+RG_SX5GB_SUB_SEL_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26169;"	d
+RG_SX5GB_SUB_SEL_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26167;"	d
+RG_SX5GB_SUB_SEL_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26166;"	d
+RG_SX5GB_SUB_SEL_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26168;"	d
+RG_SX5GB_SUB_SEL_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26170;"	d
+RG_SX5GB_SUB_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26171;"	d
+RG_SX5GB_SUB_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26173;"	d
+RG_SX5GB_SUB_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26175;"	d
+RG_SX5GB_TTL_ACCUM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25994;"	d
+RG_SX5GB_TTL_ACCUM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25992;"	d
+RG_SX5GB_TTL_ACCUM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25991;"	d
+RG_SX5GB_TTL_ACCUM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25993;"	d
+RG_SX5GB_TTL_ACCUM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25995;"	d
+RG_SX5GB_TTL_CPT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25989;"	d
+RG_SX5GB_TTL_CPT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25987;"	d
+RG_SX5GB_TTL_CPT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25986;"	d
+RG_SX5GB_TTL_CPT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25988;"	d
+RG_SX5GB_TTL_CPT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25990;"	d
+RG_SX5GB_TTL_DIS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25759;"	d
+RG_SX5GB_TTL_DIS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25757;"	d
+RG_SX5GB_TTL_DIS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25756;"	d
+RG_SX5GB_TTL_DIS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25758;"	d
+RG_SX5GB_TTL_DIS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25760;"	d
+RG_SX5GB_TTL_FPT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25984;"	d
+RG_SX5GB_TTL_FPT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25982;"	d
+RG_SX5GB_TTL_FPT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25981;"	d
+RG_SX5GB_TTL_FPT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25983;"	d
+RG_SX5GB_TTL_FPT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25985;"	d
+RG_SX5GB_TTL_INIT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25979;"	d
+RG_SX5GB_TTL_INIT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25977;"	d
+RG_SX5GB_TTL_INIT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25976;"	d
+RG_SX5GB_TTL_INIT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25978;"	d
+RG_SX5GB_TTL_INIT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25980;"	d
+RG_SX5GB_TTL_SUB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25999;"	d
+RG_SX5GB_TTL_SUB_INV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26004;"	d
+RG_SX5GB_TTL_SUB_INV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26002;"	d
+RG_SX5GB_TTL_SUB_INV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26001;"	d
+RG_SX5GB_TTL_SUB_INV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26003;"	d
+RG_SX5GB_TTL_SUB_INV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26005;"	d
+RG_SX5GB_TTL_SUB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25997;"	d
+RG_SX5GB_TTL_SUB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25996;"	d
+RG_SX5GB_TTL_SUB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25998;"	d
+RG_SX5GB_TTL_SUB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26000;"	d
+RG_SX5GB_TTL_VH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26009;"	d
+RG_SX5GB_TTL_VH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26007;"	d
+RG_SX5GB_TTL_VH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26006;"	d
+RG_SX5GB_TTL_VH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26008;"	d
+RG_SX5GB_TTL_VH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26010;"	d
+RG_SX5GB_TTL_VL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26014;"	d
+RG_SX5GB_TTL_VL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26012;"	d
+RG_SX5GB_TTL_VL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26011;"	d
+RG_SX5GB_TTL_VL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26013;"	d
+RG_SX5GB_TTL_VL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26015;"	d
+RG_SX5GB_UOP_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25674;"	d
+RG_SX5GB_UOP_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25672;"	d
+RG_SX5GB_UOP_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25671;"	d
+RG_SX5GB_UOP_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25673;"	d
+RG_SX5GB_UOP_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25675;"	d
+RG_SX5GB_UOP_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25669;"	d
+RG_SX5GB_UOP_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25667;"	d
+RG_SX5GB_UOP_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25666;"	d
+RG_SX5GB_UOP_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25668;"	d
+RG_SX5GB_UOP_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25670;"	d
+RG_SX5GB_VCO_CS_AWH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26054;"	d
+RG_SX5GB_VCO_CS_AWH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26052;"	d
+RG_SX5GB_VCO_CS_AWH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26051;"	d
+RG_SX5GB_VCO_CS_AWH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26053;"	d
+RG_SX5GB_VCO_CS_AWH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26055;"	d
+RG_SX5GB_VCO_ISEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26029;"	d
+RG_SX5GB_VCO_ISEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26027;"	d
+RG_SX5GB_VCO_ISEL_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26024;"	d
+RG_SX5GB_VCO_ISEL_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26022;"	d
+RG_SX5GB_VCO_ISEL_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26021;"	d
+RG_SX5GB_VCO_ISEL_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26023;"	d
+RG_SX5GB_VCO_ISEL_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26025;"	d
+RG_SX5GB_VCO_ISEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26026;"	d
+RG_SX5GB_VCO_ISEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26028;"	d
+RG_SX5GB_VCO_ISEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26030;"	d
+RG_SX5GB_VCO_KVDOUB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26039;"	d
+RG_SX5GB_VCO_KVDOUB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26037;"	d
+RG_SX5GB_VCO_KVDOUB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26036;"	d
+RG_SX5GB_VCO_KVDOUB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26038;"	d
+RG_SX5GB_VCO_KVDOUB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26040;"	d
+RG_SX5GB_VCO_RTAIL_SHIFT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26049;"	d
+RG_SX5GB_VCO_RTAIL_SHIFT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26047;"	d
+RG_SX5GB_VCO_RTAIL_SHIFT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26046;"	d
+RG_SX5GB_VCO_RTAIL_SHIFT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26048;"	d
+RG_SX5GB_VCO_RTAIL_SHIFT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26050;"	d
+RG_SX5GB_VCO_VARBSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26044;"	d
+RG_SX5GB_VCO_VARBSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26042;"	d
+RG_SX5GB_VCO_VARBSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26041;"	d
+RG_SX5GB_VCO_VARBSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26043;"	d
+RG_SX5GB_VCO_VARBSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26045;"	d
+RG_SX5GB_VCO_VCCBSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26034;"	d
+RG_SX5GB_VCO_VCCBSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26032;"	d
+RG_SX5GB_VCO_VCCBSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26031;"	d
+RG_SX5GB_VCO_VCCBSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26033;"	d
+RG_SX5GB_VCO_VCCBSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26035;"	d
+RG_SX5GB_VOAAC_DIS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25744;"	d
+RG_SX5GB_VOAAC_DIS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25742;"	d
+RG_SX5GB_VOAAC_DIS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25741;"	d
+RG_SX5GB_VOAAC_DIS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25743;"	d
+RG_SX5GB_VOAAC_DIS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25745;"	d
+RG_SX5GB_VOAAC_TAR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26209;"	d
+RG_SX5GB_VOAAC_TAR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26207;"	d
+RG_SX5GB_VOAAC_TAR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26206;"	d
+RG_SX5GB_VOAAC_TAR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26208;"	d
+RG_SX5GB_VOAAC_TAR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26210;"	d
+RG_SXMIX_GMBIAS_OP1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26159;"	d
+RG_SXMIX_GMBIAS_OP1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26157;"	d
+RG_SXMIX_GMBIAS_OP1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26156;"	d
+RG_SXMIX_GMBIAS_OP1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26158;"	d
+RG_SXMIX_GMBIAS_OP1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26160;"	d
+RG_SXMIX_GMSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26089;"	d
+RG_SXMIX_GMSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26087;"	d
+RG_SXMIX_GMSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26086;"	d
+RG_SXMIX_GMSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26088;"	d
+RG_SXMIX_GMSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26090;"	d
+RG_SXMIX_IBIAS_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26079;"	d
+RG_SXMIX_IBIAS_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26077;"	d
+RG_SXMIX_IBIAS_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26076;"	d
+RG_SXMIX_IBIAS_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26078;"	d
+RG_SXMIX_IBIAS_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26080;"	d
+RG_SXMIX_INBF_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26154;"	d
+RG_SXMIX_INBF_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26152;"	d
+RG_SXMIX_INBF_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26151;"	d
+RG_SXMIX_INBF_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26153;"	d
+RG_SXMIX_INBF_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26155;"	d
+RG_SXMIX_SCA_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26309;"	d
+RG_SXMIX_SCA_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26307;"	d
+RG_SXMIX_SCA_SEL_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26304;"	d
+RG_SXMIX_SCA_SEL_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26302;"	d
+RG_SXMIX_SCA_SEL_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26301;"	d
+RG_SXMIX_SCA_SEL_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26303;"	d
+RG_SXMIX_SCA_SEL_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26305;"	d
+RG_SXMIX_SCA_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26306;"	d
+RG_SXMIX_SCA_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26308;"	d
+RG_SXMIX_SCA_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26310;"	d
+RG_SXMIX_SWBIAS_OP1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26164;"	d
+RG_SXMIX_SWBIAS_OP1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26162;"	d
+RG_SXMIX_SWBIAS_OP1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26161;"	d
+RG_SXMIX_SWBIAS_OP1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26163;"	d
+RG_SXMIX_SWBIAS_OP1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26165;"	d
+RG_SXMIX_SWB_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26084;"	d
+RG_SXMIX_SWB_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26082;"	d
+RG_SXMIX_SWB_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26081;"	d
+RG_SXMIX_SWB_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26083;"	d
+RG_SXMIX_SWB_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26085;"	d
+RG_SXREP_CSSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26099;"	d
+RG_SXREP_CSSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26097;"	d
+RG_SXREP_CSSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26096;"	d
+RG_SXREP_CSSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26098;"	d
+RG_SXREP_CSSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26100;"	d
+RG_SXREP_SCA_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26324;"	d
+RG_SXREP_SCA_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26322;"	d
+RG_SXREP_SCA_SEL_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26319;"	d
+RG_SXREP_SCA_SEL_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26317;"	d
+RG_SXREP_SCA_SEL_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26316;"	d
+RG_SXREP_SCA_SEL_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26318;"	d
+RG_SXREP_SCA_SEL_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26320;"	d
+RG_SXREP_SCA_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26321;"	d
+RG_SXREP_SCA_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26323;"	d
+RG_SXREP_SCA_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26325;"	d
+RG_SXREP_SWB_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26094;"	d
+RG_SXREP_SWB_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26092;"	d
+RG_SXREP_SWB_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26091;"	d
+RG_SXREP_SWB_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26093;"	d
+RG_SXREP_SWB_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26095;"	d
+RG_SX_5GB_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25624;"	d
+RG_SX_5GB_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25622;"	d
+RG_SX_5GB_EN_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	25619;"	d
+RG_SX_5GB_EN_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25617;"	d
+RG_SX_5GB_EN_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25616;"	d
+RG_SX_5GB_EN_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25618;"	d
+RG_SX_5GB_EN_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25620;"	d
+RG_SX_5GB_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	25621;"	d
+RG_SX_5GB_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	25623;"	d
+RG_SX_5GB_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	25625;"	d
+RG_SX_AAC_DIS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23219;"	d
+RG_SX_AAC_DIS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23217;"	d
+RG_SX_AAC_DIS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23216;"	d
+RG_SX_AAC_DIS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23218;"	d
+RG_SX_AAC_DIS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23220;"	d
+RG_SX_BTRX_SIDE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23369;"	d
+RG_SX_BTRX_SIDE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23367;"	d
+RG_SX_BTRX_SIDE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23366;"	d
+RG_SX_BTRX_SIDE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23368;"	d
+RG_SX_BTRX_SIDE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23370;"	d
+RG_SX_CAL_INIT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23229;"	d
+RG_SX_CAL_INIT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23227;"	d
+RG_SX_CAL_INIT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23226;"	d
+RG_SX_CAL_INIT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23228;"	d
+RG_SX_CAL_INIT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23230;"	d
+RG_SX_CHANNEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23379;"	d
+RG_SX_CHANNEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23377;"	d
+RG_SX_CHANNEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23376;"	d
+RG_SX_CHANNEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23378;"	d
+RG_SX_CHANNEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23380;"	d
+RG_SX_CHP_IOST_HI	include/ssv6200_aux.h	17044;"	d
+RG_SX_CHP_IOST_I_MSK	include/ssv6200_aux.h	17042;"	d
+RG_SX_CHP_IOST_MSK	include/ssv6200_aux.h	17041;"	d
+RG_SX_CHP_IOST_POL_HI	include/ssv6200_aux.h	17039;"	d
+RG_SX_CHP_IOST_POL_I_MSK	include/ssv6200_aux.h	17037;"	d
+RG_SX_CHP_IOST_POL_MSK	include/ssv6200_aux.h	17036;"	d
+RG_SX_CHP_IOST_POL_SFT	include/ssv6200_aux.h	17038;"	d
+RG_SX_CHP_IOST_POL_SZ	include/ssv6200_aux.h	17040;"	d
+RG_SX_CHP_IOST_SFT	include/ssv6200_aux.h	17043;"	d
+RG_SX_CHP_IOST_SZ	include/ssv6200_aux.h	17045;"	d
+RG_SX_CP_IOST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23424;"	d
+RG_SX_CP_IOST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23422;"	d
+RG_SX_CP_IOST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23421;"	d
+RG_SX_CP_IOST_POL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23419;"	d
+RG_SX_CP_IOST_POL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23417;"	d
+RG_SX_CP_IOST_POL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23416;"	d
+RG_SX_CP_IOST_POL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23418;"	d
+RG_SX_CP_IOST_POL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23420;"	d
+RG_SX_CP_IOST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23423;"	d
+RG_SX_CP_IOST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23425;"	d
+RG_SX_CP_ISEL50U_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23394;"	d
+RG_SX_CP_ISEL50U_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23392;"	d
+RG_SX_CP_ISEL50U_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23391;"	d
+RG_SX_CP_ISEL50U_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23393;"	d
+RG_SX_CP_ISEL50U_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23395;"	d
+RG_SX_CP_ISEL50U_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23409;"	d
+RG_SX_CP_ISEL50U_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23407;"	d
+RG_SX_CP_ISEL50U_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23406;"	d
+RG_SX_CP_ISEL50U_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23408;"	d
+RG_SX_CP_ISEL50U_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23410;"	d
+RG_SX_CP_ISEL_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23389;"	d
+RG_SX_CP_ISEL_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23387;"	d
+RG_SX_CP_ISEL_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23386;"	d
+RG_SX_CP_ISEL_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23388;"	d
+RG_SX_CP_ISEL_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23390;"	d
+RG_SX_CP_ISEL_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23404;"	d
+RG_SX_CP_ISEL_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23402;"	d
+RG_SX_CP_ISEL_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23401;"	d
+RG_SX_CP_ISEL_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23403;"	d
+RG_SX_CP_ISEL_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23405;"	d
+RG_SX_CP_KP_DOUB_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23399;"	d
+RG_SX_CP_KP_DOUB_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23397;"	d
+RG_SX_CP_KP_DOUB_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23396;"	d
+RG_SX_CP_KP_DOUB_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23398;"	d
+RG_SX_CP_KP_DOUB_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23400;"	d
+RG_SX_CP_KP_DOUB_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23414;"	d
+RG_SX_CP_KP_DOUB_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23412;"	d
+RG_SX_CP_KP_DOUB_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23411;"	d
+RG_SX_CP_KP_DOUB_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23413;"	d
+RG_SX_CP_KP_DOUB_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23415;"	d
+RG_SX_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24604;"	d
+RG_SX_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24602;"	d
+RG_SX_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24601;"	d
+RG_SX_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24603;"	d
+RG_SX_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24605;"	d
+RG_SX_DITHER_WEIGHT_HI	include/ssv6200_aux.h	17134;"	d
+RG_SX_DITHER_WEIGHT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23694;"	d
+RG_SX_DITHER_WEIGHT_I_MSK	include/ssv6200_aux.h	17132;"	d
+RG_SX_DITHER_WEIGHT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23692;"	d
+RG_SX_DITHER_WEIGHT_MSK	include/ssv6200_aux.h	17131;"	d
+RG_SX_DITHER_WEIGHT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23691;"	d
+RG_SX_DITHER_WEIGHT_SFT	include/ssv6200_aux.h	17133;"	d
+RG_SX_DITHER_WEIGHT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23693;"	d
+RG_SX_DITHER_WEIGHT_SZ	include/ssv6200_aux.h	17135;"	d
+RG_SX_DITHER_WEIGHT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23695;"	d
+RG_SX_DIVBFSEL_HI	include/ssv6200_aux.h	17124;"	d
+RG_SX_DIVBFSEL_I_MSK	include/ssv6200_aux.h	17122;"	d
+RG_SX_DIVBFSEL_MSK	include/ssv6200_aux.h	17121;"	d
+RG_SX_DIVBFSEL_SFT	include/ssv6200_aux.h	17123;"	d
+RG_SX_DIVBFSEL_SZ	include/ssv6200_aux.h	17125;"	d
+RG_SX_DIV_DMYBUF_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23674;"	d
+RG_SX_DIV_DMYBUF_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23672;"	d
+RG_SX_DIV_DMYBUF_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23671;"	d
+RG_SX_DIV_DMYBUF_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23673;"	d
+RG_SX_DIV_DMYBUF_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23675;"	d
+RG_SX_DIV_PREVDD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23654;"	d
+RG_SX_DIV_PREVDD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23652;"	d
+RG_SX_DIV_PREVDD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23651;"	d
+RG_SX_DIV_PREVDD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23653;"	d
+RG_SX_DIV_PREVDD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23655;"	d
+RG_SX_DIV_PSCVDD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23659;"	d
+RG_SX_DIV_PSCVDD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23657;"	d
+RG_SX_DIV_PSCVDD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23656;"	d
+RG_SX_DIV_PSCVDD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23658;"	d
+RG_SX_DIV_PSCVDD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23660;"	d
+RG_SX_DIV_RST_H_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23664;"	d
+RG_SX_DIV_RST_H_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23662;"	d
+RG_SX_DIV_RST_H_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23661;"	d
+RG_SX_DIV_RST_H_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23663;"	d
+RG_SX_DIV_RST_H_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23665;"	d
+RG_SX_DIV_SDM_EDGE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23669;"	d
+RG_SX_DIV_SDM_EDGE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23667;"	d
+RG_SX_DIV_SDM_EDGE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23666;"	d
+RG_SX_DIV_SDM_EDGE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23668;"	d
+RG_SX_DIV_SDM_EDGE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23670;"	d
+RG_SX_DUMMMY_HI	include/ssv6200_aux.h	17549;"	d
+RG_SX_DUMMMY_I_MSK	include/ssv6200_aux.h	17547;"	d
+RG_SX_DUMMMY_MSK	include/ssv6200_aux.h	17546;"	d
+RG_SX_DUMMMY_SFT	include/ssv6200_aux.h	17548;"	d
+RG_SX_DUMMMY_SZ	include/ssv6200_aux.h	17550;"	d
+RG_SX_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23104;"	d
+RG_SX_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23102;"	d
+RG_SX_EN_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23099;"	d
+RG_SX_EN_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23097;"	d
+RG_SX_EN_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23096;"	d
+RG_SX_EN_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23098;"	d
+RG_SX_EN_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23100;"	d
+RG_SX_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23101;"	d
+RG_SX_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23103;"	d
+RG_SX_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23105;"	d
+RG_SX_FREF_DOUB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23364;"	d
+RG_SX_FREF_DOUB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23362;"	d
+RG_SX_FREF_DOUB_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23359;"	d
+RG_SX_FREF_DOUB_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23357;"	d
+RG_SX_FREF_DOUB_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23356;"	d
+RG_SX_FREF_DOUB_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23358;"	d
+RG_SX_FREF_DOUB_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23360;"	d
+RG_SX_FREF_DOUB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23361;"	d
+RG_SX_FREF_DOUB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23363;"	d
+RG_SX_FREF_DOUB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23365;"	d
+RG_SX_GNDR_SEL_HI	include/ssv6200_aux.h	17129;"	d
+RG_SX_GNDR_SEL_I_MSK	include/ssv6200_aux.h	17127;"	d
+RG_SX_GNDR_SEL_MSK	include/ssv6200_aux.h	17126;"	d
+RG_SX_GNDR_SEL_SFT	include/ssv6200_aux.h	17128;"	d
+RG_SX_GNDR_SEL_SZ	include/ssv6200_aux.h	17130;"	d
+RG_SX_LCKEN_HI	include/ssv6200_aux.h	17164;"	d
+RG_SX_LCKEN_I_MSK	include/ssv6200_aux.h	17162;"	d
+RG_SX_LCKEN_MSK	include/ssv6200_aux.h	17161;"	d
+RG_SX_LCKEN_SFT	include/ssv6200_aux.h	17163;"	d
+RG_SX_LCKEN_SZ	include/ssv6200_aux.h	17165;"	d
+RG_SX_LCK_BIN_OFFSET_HI	include/ssv6200_aux.h	17509;"	d
+RG_SX_LCK_BIN_OFFSET_I_MSK	include/ssv6200_aux.h	17507;"	d
+RG_SX_LCK_BIN_OFFSET_MSK	include/ssv6200_aux.h	17506;"	d
+RG_SX_LCK_BIN_OFFSET_SFT	include/ssv6200_aux.h	17508;"	d
+RG_SX_LCK_BIN_OFFSET_SZ	include/ssv6200_aux.h	17510;"	d
+RG_SX_LCK_BIN_PRECISION_HI	include/ssv6200_aux.h	17514;"	d
+RG_SX_LCK_BIN_PRECISION_I_MSK	include/ssv6200_aux.h	17512;"	d
+RG_SX_LCK_BIN_PRECISION_MSK	include/ssv6200_aux.h	17511;"	d
+RG_SX_LCK_BIN_PRECISION_SFT	include/ssv6200_aux.h	17513;"	d
+RG_SX_LCK_BIN_PRECISION_SZ	include/ssv6200_aux.h	17515;"	d
+RG_SX_LDO_CHP_LEVEL_HI	include/ssv6200_aux.h	16299;"	d
+RG_SX_LDO_CHP_LEVEL_I_MSK	include/ssv6200_aux.h	16297;"	d
+RG_SX_LDO_CHP_LEVEL_MSK	include/ssv6200_aux.h	16296;"	d
+RG_SX_LDO_CHP_LEVEL_SFT	include/ssv6200_aux.h	16298;"	d
+RG_SX_LDO_CHP_LEVEL_SZ	include/ssv6200_aux.h	16300;"	d
+RG_SX_LDO_CP_LEVEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21964;"	d
+RG_SX_LDO_CP_LEVEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21962;"	d
+RG_SX_LDO_CP_LEVEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21961;"	d
+RG_SX_LDO_CP_LEVEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21963;"	d
+RG_SX_LDO_CP_LEVEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21965;"	d
+RG_SX_LDO_DIV_LEVEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21989;"	d
+RG_SX_LDO_DIV_LEVEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21987;"	d
+RG_SX_LDO_DIV_LEVEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21986;"	d
+RG_SX_LDO_DIV_LEVEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21988;"	d
+RG_SX_LDO_DIV_LEVEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21990;"	d
+RG_SX_LDO_FCOFFT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23289;"	d
+RG_SX_LDO_FCOFFT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23287;"	d
+RG_SX_LDO_FCOFFT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23286;"	d
+RG_SX_LDO_FCOFFT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23288;"	d
+RG_SX_LDO_FCOFFT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23290;"	d
+RG_SX_LDO_LOBF_LEVEL_HI	include/ssv6200_aux.h	16304;"	d
+RG_SX_LDO_LOBF_LEVEL_I_MSK	include/ssv6200_aux.h	16302;"	d
+RG_SX_LDO_LOBF_LEVEL_MSK	include/ssv6200_aux.h	16301;"	d
+RG_SX_LDO_LOBF_LEVEL_SFT	include/ssv6200_aux.h	16303;"	d
+RG_SX_LDO_LOBF_LEVEL_SZ	include/ssv6200_aux.h	16305;"	d
+RG_SX_LDO_LO_LEVEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21974;"	d
+RG_SX_LDO_LO_LEVEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21972;"	d
+RG_SX_LDO_LO_LEVEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21971;"	d
+RG_SX_LDO_LO_LEVEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21973;"	d
+RG_SX_LDO_LO_LEVEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21975;"	d
+RG_SX_LDO_VCO_LEVEL_HI	include/ssv6200_aux.h	16319;"	d
+RG_SX_LDO_VCO_LEVEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21984;"	d
+RG_SX_LDO_VCO_LEVEL_I_MSK	include/ssv6200_aux.h	16317;"	d
+RG_SX_LDO_VCO_LEVEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21982;"	d
+RG_SX_LDO_VCO_LEVEL_MSK	include/ssv6200_aux.h	16316;"	d
+RG_SX_LDO_VCO_LEVEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21981;"	d
+RG_SX_LDO_VCO_LEVEL_SFT	include/ssv6200_aux.h	16318;"	d
+RG_SX_LDO_VCO_LEVEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21983;"	d
+RG_SX_LDO_VCO_LEVEL_SZ	include/ssv6200_aux.h	16320;"	d
+RG_SX_LDO_VCO_LEVEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21985;"	d
+RG_SX_LDO_XOSC_LEVEL_HI	include/ssv6200_aux.h	16309;"	d
+RG_SX_LDO_XOSC_LEVEL_I_MSK	include/ssv6200_aux.h	16307;"	d
+RG_SX_LDO_XOSC_LEVEL_MSK	include/ssv6200_aux.h	16306;"	d
+RG_SX_LDO_XOSC_LEVEL_SFT	include/ssv6200_aux.h	16308;"	d
+RG_SX_LDO_XOSC_LEVEL_SZ	include/ssv6200_aux.h	16310;"	d
+RG_SX_LOCK_EN_N_HI	include/ssv6200_aux.h	17519;"	d
+RG_SX_LOCK_EN_N_I_MSK	include/ssv6200_aux.h	17517;"	d
+RG_SX_LOCK_EN_N_MSK	include/ssv6200_aux.h	17516;"	d
+RG_SX_LOCK_EN_N_SFT	include/ssv6200_aux.h	17518;"	d
+RG_SX_LOCK_EN_N_SZ	include/ssv6200_aux.h	17520;"	d
+RG_SX_LOCK_MANUAL_HI	include/ssv6200_aux.h	17524;"	d
+RG_SX_LOCK_MANUAL_I_MSK	include/ssv6200_aux.h	17522;"	d
+RG_SX_LOCK_MANUAL_MSK	include/ssv6200_aux.h	17521;"	d
+RG_SX_LOCK_MANUAL_SFT	include/ssv6200_aux.h	17523;"	d
+RG_SX_LOCK_MANUAL_SZ	include/ssv6200_aux.h	17525;"	d
+RG_SX_LO_TIMES_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23374;"	d
+RG_SX_LO_TIMES_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23372;"	d
+RG_SX_LO_TIMES_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23371;"	d
+RG_SX_LO_TIMES_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23373;"	d
+RG_SX_LO_TIMES_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23375;"	d
+RG_SX_LPF_C1_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23474;"	d
+RG_SX_LPF_C1_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23472;"	d
+RG_SX_LPF_C1_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23471;"	d
+RG_SX_LPF_C1_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23473;"	d
+RG_SX_LPF_C1_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23475;"	d
+RG_SX_LPF_C1_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23499;"	d
+RG_SX_LPF_C1_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23497;"	d
+RG_SX_LPF_C1_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23496;"	d
+RG_SX_LPF_C1_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23498;"	d
+RG_SX_LPF_C1_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23500;"	d
+RG_SX_LPF_C2_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23479;"	d
+RG_SX_LPF_C2_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23477;"	d
+RG_SX_LPF_C2_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23476;"	d
+RG_SX_LPF_C2_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23478;"	d
+RG_SX_LPF_C2_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23480;"	d
+RG_SX_LPF_C2_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23504;"	d
+RG_SX_LPF_C2_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23502;"	d
+RG_SX_LPF_C2_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23501;"	d
+RG_SX_LPF_C2_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23503;"	d
+RG_SX_LPF_C2_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23505;"	d
+RG_SX_LPF_C3_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23484;"	d
+RG_SX_LPF_C3_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23482;"	d
+RG_SX_LPF_C3_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23481;"	d
+RG_SX_LPF_C3_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23483;"	d
+RG_SX_LPF_C3_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23485;"	d
+RG_SX_LPF_C3_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23509;"	d
+RG_SX_LPF_C3_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23507;"	d
+RG_SX_LPF_C3_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23506;"	d
+RG_SX_LPF_C3_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23508;"	d
+RG_SX_LPF_C3_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23510;"	d
+RG_SX_LPF_R2_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23489;"	d
+RG_SX_LPF_R2_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23487;"	d
+RG_SX_LPF_R2_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23486;"	d
+RG_SX_LPF_R2_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23488;"	d
+RG_SX_LPF_R2_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23490;"	d
+RG_SX_LPF_R2_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23514;"	d
+RG_SX_LPF_R2_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23512;"	d
+RG_SX_LPF_R2_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23511;"	d
+RG_SX_LPF_R2_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23513;"	d
+RG_SX_LPF_R2_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23515;"	d
+RG_SX_LPF_R3_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23494;"	d
+RG_SX_LPF_R3_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23492;"	d
+RG_SX_LPF_R3_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23491;"	d
+RG_SX_LPF_R3_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23493;"	d
+RG_SX_LPF_R3_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23495;"	d
+RG_SX_LPF_R3_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23519;"	d
+RG_SX_LPF_R3_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23517;"	d
+RG_SX_LPF_R3_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23516;"	d
+RG_SX_LPF_R3_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23518;"	d
+RG_SX_LPF_R3_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23520;"	d
+RG_SX_LPF_VTUNE_TEST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23844;"	d
+RG_SX_LPF_VTUNE_TEST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23842;"	d
+RG_SX_LPF_VTUNE_TEST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23841;"	d
+RG_SX_LPF_VTUNE_TEST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23843;"	d
+RG_SX_LPF_VTUNE_TEST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23845;"	d
+RG_SX_MOD_ORDER_HI	include/ssv6200_aux.h	17139;"	d
+RG_SX_MOD_ORDER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23689;"	d
+RG_SX_MOD_ORDER_I_MSK	include/ssv6200_aux.h	17137;"	d
+RG_SX_MOD_ORDER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23687;"	d
+RG_SX_MOD_ORDER_MSK	include/ssv6200_aux.h	17136;"	d
+RG_SX_MOD_ORDER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23686;"	d
+RG_SX_MOD_ORDER_SFT	include/ssv6200_aux.h	17138;"	d
+RG_SX_MOD_ORDER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23688;"	d
+RG_SX_MOD_ORDER_SZ	include/ssv6200_aux.h	17140;"	d
+RG_SX_MOD_ORDER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23690;"	d
+RG_SX_MUX_SEL_VTH_BINL_HI	include/ssv6200_aux.h	17539;"	d
+RG_SX_MUX_SEL_VTH_BINL_I_MSK	include/ssv6200_aux.h	17537;"	d
+RG_SX_MUX_SEL_VTH_BINL_MSK	include/ssv6200_aux.h	17536;"	d
+RG_SX_MUX_SEL_VTH_BINL_SFT	include/ssv6200_aux.h	17538;"	d
+RG_SX_MUX_SEL_VTH_BINL_SZ	include/ssv6200_aux.h	17540;"	d
+RG_SX_PFDSEL_HI	include/ssv6200_aux.h	17049;"	d
+RG_SX_PFDSEL_I_MSK	include/ssv6200_aux.h	17047;"	d
+RG_SX_PFDSEL_MSK	include/ssv6200_aux.h	17046;"	d
+RG_SX_PFDSEL_SFT	include/ssv6200_aux.h	17048;"	d
+RG_SX_PFDSEL_SZ	include/ssv6200_aux.h	17050;"	d
+RG_SX_PFD_DIV_EDGE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23454;"	d
+RG_SX_PFD_DIV_EDGE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23452;"	d
+RG_SX_PFD_DIV_EDGE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23451;"	d
+RG_SX_PFD_DIV_EDGE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23453;"	d
+RG_SX_PFD_DIV_EDGE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23455;"	d
+RG_SX_PFD_REF_EDGE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23449;"	d
+RG_SX_PFD_REF_EDGE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23447;"	d
+RG_SX_PFD_REF_EDGE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23446;"	d
+RG_SX_PFD_REF_EDGE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23448;"	d
+RG_SX_PFD_REF_EDGE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23450;"	d
+RG_SX_PFD_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23144;"	d
+RG_SX_PFD_RST_H_HI	include/ssv6200_aux.h	17074;"	d
+RG_SX_PFD_RST_H_I_MSK	include/ssv6200_aux.h	17072;"	d
+RG_SX_PFD_RST_H_MSK	include/ssv6200_aux.h	17071;"	d
+RG_SX_PFD_RST_H_SFT	include/ssv6200_aux.h	17073;"	d
+RG_SX_PFD_RST_H_SZ	include/ssv6200_aux.h	17075;"	d
+RG_SX_PFD_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23142;"	d
+RG_SX_PFD_RST_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23139;"	d
+RG_SX_PFD_RST_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23137;"	d
+RG_SX_PFD_RST_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23136;"	d
+RG_SX_PFD_RST_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23138;"	d
+RG_SX_PFD_RST_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23140;"	d
+RG_SX_PFD_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23141;"	d
+RG_SX_PFD_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23143;"	d
+RG_SX_PFD_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23145;"	d
+RG_SX_PFD_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23429;"	d
+RG_SX_PFD_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23427;"	d
+RG_SX_PFD_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23426;"	d
+RG_SX_PFD_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23428;"	d
+RG_SX_PFD_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23430;"	d
+RG_SX_PFD_SET1_HI	include/ssv6200_aux.h	17059;"	d
+RG_SX_PFD_SET1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23439;"	d
+RG_SX_PFD_SET1_I_MSK	include/ssv6200_aux.h	17057;"	d
+RG_SX_PFD_SET1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23437;"	d
+RG_SX_PFD_SET1_MSK	include/ssv6200_aux.h	17056;"	d
+RG_SX_PFD_SET1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23436;"	d
+RG_SX_PFD_SET1_SFT	include/ssv6200_aux.h	17058;"	d
+RG_SX_PFD_SET1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23438;"	d
+RG_SX_PFD_SET1_SZ	include/ssv6200_aux.h	17060;"	d
+RG_SX_PFD_SET1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23440;"	d
+RG_SX_PFD_SET2_HI	include/ssv6200_aux.h	17064;"	d
+RG_SX_PFD_SET2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23444;"	d
+RG_SX_PFD_SET2_I_MSK	include/ssv6200_aux.h	17062;"	d
+RG_SX_PFD_SET2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23442;"	d
+RG_SX_PFD_SET2_MSK	include/ssv6200_aux.h	17061;"	d
+RG_SX_PFD_SET2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23441;"	d
+RG_SX_PFD_SET2_SFT	include/ssv6200_aux.h	17063;"	d
+RG_SX_PFD_SET2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23443;"	d
+RG_SX_PFD_SET2_SZ	include/ssv6200_aux.h	17065;"	d
+RG_SX_PFD_SET2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23445;"	d
+RG_SX_PFD_SET_HI	include/ssv6200_aux.h	17054;"	d
+RG_SX_PFD_SET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23434;"	d
+RG_SX_PFD_SET_I_MSK	include/ssv6200_aux.h	17052;"	d
+RG_SX_PFD_SET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23432;"	d
+RG_SX_PFD_SET_MSK	include/ssv6200_aux.h	17051;"	d
+RG_SX_PFD_SET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23431;"	d
+RG_SX_PFD_SET_SFT	include/ssv6200_aux.h	17053;"	d
+RG_SX_PFD_SET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23433;"	d
+RG_SX_PFD_SET_SZ	include/ssv6200_aux.h	17055;"	d
+RG_SX_PFD_SET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23435;"	d
+RG_SX_PFD_TLSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23469;"	d
+RG_SX_PFD_TLSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23467;"	d
+RG_SX_PFD_TLSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23466;"	d
+RG_SX_PFD_TLSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23468;"	d
+RG_SX_PFD_TLSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23470;"	d
+RG_SX_PFD_TRDN_HI	include/ssv6200_aux.h	17084;"	d
+RG_SX_PFD_TRDN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23464;"	d
+RG_SX_PFD_TRDN_I_MSK	include/ssv6200_aux.h	17082;"	d
+RG_SX_PFD_TRDN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23462;"	d
+RG_SX_PFD_TRDN_MSK	include/ssv6200_aux.h	17081;"	d
+RG_SX_PFD_TRDN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23461;"	d
+RG_SX_PFD_TRDN_SFT	include/ssv6200_aux.h	17083;"	d
+RG_SX_PFD_TRDN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23463;"	d
+RG_SX_PFD_TRDN_SZ	include/ssv6200_aux.h	17085;"	d
+RG_SX_PFD_TRDN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23465;"	d
+RG_SX_PFD_TRSEL_HI	include/ssv6200_aux.h	17089;"	d
+RG_SX_PFD_TRSEL_I_MSK	include/ssv6200_aux.h	17087;"	d
+RG_SX_PFD_TRSEL_MSK	include/ssv6200_aux.h	17086;"	d
+RG_SX_PFD_TRSEL_SFT	include/ssv6200_aux.h	17088;"	d
+RG_SX_PFD_TRSEL_SZ	include/ssv6200_aux.h	17090;"	d
+RG_SX_PFD_TRUP_HI	include/ssv6200_aux.h	17079;"	d
+RG_SX_PFD_TRUP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23459;"	d
+RG_SX_PFD_TRUP_I_MSK	include/ssv6200_aux.h	17077;"	d
+RG_SX_PFD_TRUP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23457;"	d
+RG_SX_PFD_TRUP_MSK	include/ssv6200_aux.h	17076;"	d
+RG_SX_PFD_TRUP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23456;"	d
+RG_SX_PFD_TRUP_SFT	include/ssv6200_aux.h	17078;"	d
+RG_SX_PFD_TRUP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23458;"	d
+RG_SX_PFD_TRUP_SZ	include/ssv6200_aux.h	17080;"	d
+RG_SX_PFD_TRUP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23460;"	d
+RG_SX_PH_HI	include/ssv6200_aux.h	17179;"	d
+RG_SX_PH_I_MSK	include/ssv6200_aux.h	17177;"	d
+RG_SX_PH_MSK	include/ssv6200_aux.h	17176;"	d
+RG_SX_PH_SFT	include/ssv6200_aux.h	17178;"	d
+RG_SX_PH_SZ	include/ssv6200_aux.h	17180;"	d
+RG_SX_PL_HI	include/ssv6200_aux.h	17184;"	d
+RG_SX_PL_I_MSK	include/ssv6200_aux.h	17182;"	d
+RG_SX_PL_MSK	include/ssv6200_aux.h	17181;"	d
+RG_SX_PL_SFT	include/ssv6200_aux.h	17183;"	d
+RG_SX_PL_SZ	include/ssv6200_aux.h	17185;"	d
+RG_SX_PREVDD_HI	include/ssv6200_aux.h	17169;"	d
+RG_SX_PREVDD_I_MSK	include/ssv6200_aux.h	17167;"	d
+RG_SX_PREVDD_MSK	include/ssv6200_aux.h	17166;"	d
+RG_SX_PREVDD_SFT	include/ssv6200_aux.h	17168;"	d
+RG_SX_PREVDD_SZ	include/ssv6200_aux.h	17170;"	d
+RG_SX_PSCONTERVDD_HI	include/ssv6200_aux.h	17174;"	d
+RG_SX_PSCONTERVDD_I_MSK	include/ssv6200_aux.h	17172;"	d
+RG_SX_PSCONTERVDD_MSK	include/ssv6200_aux.h	17171;"	d
+RG_SX_PSCONTERVDD_SFT	include/ssv6200_aux.h	17173;"	d
+RG_SX_PSCONTERVDD_SZ	include/ssv6200_aux.h	17175;"	d
+RG_SX_REFBYTWO_HI	include/ssv6200_aux.h	17159;"	d
+RG_SX_REFBYTWO_I_MSK	include/ssv6200_aux.h	17157;"	d
+RG_SX_REFBYTWO_MSK	include/ssv6200_aux.h	17156;"	d
+RG_SX_REFBYTWO_SFT	include/ssv6200_aux.h	17158;"	d
+RG_SX_REFBYTWO_SZ	include/ssv6200_aux.h	17160;"	d
+RG_SX_RFCH_MAP_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23354;"	d
+RG_SX_RFCH_MAP_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23352;"	d
+RG_SX_RFCH_MAP_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23351;"	d
+RG_SX_RFCH_MAP_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23353;"	d
+RG_SX_RFCH_MAP_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23355;"	d
+RG_SX_RFCTRL_CH_10_8_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23349;"	d
+RG_SX_RFCTRL_CH_10_8_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23347;"	d
+RG_SX_RFCTRL_CH_10_8_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23346;"	d
+RG_SX_RFCTRL_CH_10_8_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23348;"	d
+RG_SX_RFCTRL_CH_10_8_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23350;"	d
+RG_SX_RFCTRL_CH_7_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23344;"	d
+RG_SX_RFCTRL_CH_7_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23342;"	d
+RG_SX_RFCTRL_CH_7_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23341;"	d
+RG_SX_RFCTRL_CH_7_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23343;"	d
+RG_SX_RFCTRL_CH_7_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23345;"	d
+RG_SX_RFCTRL_CH_HI	include/ssv6200_aux.h	16999;"	d
+RG_SX_RFCTRL_CH_I_MSK	include/ssv6200_aux.h	16997;"	d
+RG_SX_RFCTRL_CH_MSK	include/ssv6200_aux.h	16996;"	d
+RG_SX_RFCTRL_CH_SFT	include/ssv6200_aux.h	16998;"	d
+RG_SX_RFCTRL_CH_SZ	include/ssv6200_aux.h	17000;"	d
+RG_SX_RFCTRL_F_HI	include/ssv6200_aux.h	16984;"	d
+RG_SX_RFCTRL_F_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23339;"	d
+RG_SX_RFCTRL_F_I_MSK	include/ssv6200_aux.h	16982;"	d
+RG_SX_RFCTRL_F_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23337;"	d
+RG_SX_RFCTRL_F_MSK	include/ssv6200_aux.h	16981;"	d
+RG_SX_RFCTRL_F_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23336;"	d
+RG_SX_RFCTRL_F_SFT	include/ssv6200_aux.h	16983;"	d
+RG_SX_RFCTRL_F_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23338;"	d
+RG_SX_RFCTRL_F_SZ	include/ssv6200_aux.h	16985;"	d
+RG_SX_RFCTRL_F_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23340;"	d
+RG_SX_RST_H_DIV_HI	include/ssv6200_aux.h	17144;"	d
+RG_SX_RST_H_DIV_I_MSK	include/ssv6200_aux.h	17142;"	d
+RG_SX_RST_H_DIV_MSK	include/ssv6200_aux.h	17141;"	d
+RG_SX_RST_H_DIV_SFT	include/ssv6200_aux.h	17143;"	d
+RG_SX_RST_H_DIV_SZ	include/ssv6200_aux.h	17145;"	d
+RG_SX_RXBFSEL_HI	include/ssv6200_aux.h	17109;"	d
+RG_SX_RXBFSEL_I_MSK	include/ssv6200_aux.h	17107;"	d
+RG_SX_RXBFSEL_MSK	include/ssv6200_aux.h	17106;"	d
+RG_SX_RXBFSEL_SFT	include/ssv6200_aux.h	17108;"	d
+RG_SX_RXBFSEL_SZ	include/ssv6200_aux.h	17110;"	d
+RG_SX_SBCAL_AW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23214;"	d
+RG_SX_SBCAL_AW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23212;"	d
+RG_SX_SBCAL_AW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23211;"	d
+RG_SX_SBCAL_AW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23213;"	d
+RG_SX_SBCAL_AW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23215;"	d
+RG_SX_SBCAL_CT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23714;"	d
+RG_SX_SBCAL_CT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23712;"	d
+RG_SX_SBCAL_CT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23711;"	d
+RG_SX_SBCAL_CT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23713;"	d
+RG_SX_SBCAL_CT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23715;"	d
+RG_SX_SBCAL_DIFFMIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23724;"	d
+RG_SX_SBCAL_DIFFMIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23722;"	d
+RG_SX_SBCAL_DIFFMIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23721;"	d
+RG_SX_SBCAL_DIFFMIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23723;"	d
+RG_SX_SBCAL_DIFFMIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23725;"	d
+RG_SX_SBCAL_DIS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23209;"	d
+RG_SX_SBCAL_DIS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23207;"	d
+RG_SX_SBCAL_DIS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23206;"	d
+RG_SX_SBCAL_DIS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23208;"	d
+RG_SX_SBCAL_DIS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23210;"	d
+RG_SX_SBCAL_NTARG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23734;"	d
+RG_SX_SBCAL_NTARG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23732;"	d
+RG_SX_SBCAL_NTARG_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23729;"	d
+RG_SX_SBCAL_NTARG_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23727;"	d
+RG_SX_SBCAL_NTARG_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23726;"	d
+RG_SX_SBCAL_NTARG_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23728;"	d
+RG_SX_SBCAL_NTARG_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23730;"	d
+RG_SX_SBCAL_NTARG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23731;"	d
+RG_SX_SBCAL_NTARG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23733;"	d
+RG_SX_SBCAL_NTARG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23735;"	d
+RG_SX_SBCAL_WT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23719;"	d
+RG_SX_SBCAL_WT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23717;"	d
+RG_SX_SBCAL_WT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23716;"	d
+RG_SX_SBCAL_WT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23718;"	d
+RG_SX_SBCAL_WT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23720;"	d
+RG_SX_SDM_EDGE_HI	include/ssv6200_aux.h	17149;"	d
+RG_SX_SDM_EDGE_I_MSK	include/ssv6200_aux.h	17147;"	d
+RG_SX_SDM_EDGE_MSK	include/ssv6200_aux.h	17146;"	d
+RG_SX_SDM_EDGE_SFT	include/ssv6200_aux.h	17148;"	d
+RG_SX_SDM_EDGE_SZ	include/ssv6200_aux.h	17150;"	d
+RG_SX_SEL_C3_HI	include/ssv6200_aux.h	17004;"	d
+RG_SX_SEL_C3_I_MSK	include/ssv6200_aux.h	17002;"	d
+RG_SX_SEL_C3_MSK	include/ssv6200_aux.h	17001;"	d
+RG_SX_SEL_C3_SFT	include/ssv6200_aux.h	17003;"	d
+RG_SX_SEL_C3_SZ	include/ssv6200_aux.h	17005;"	d
+RG_SX_SEL_CHP_REGOP_HI	include/ssv6200_aux.h	17029;"	d
+RG_SX_SEL_CHP_REGOP_I_MSK	include/ssv6200_aux.h	17027;"	d
+RG_SX_SEL_CHP_REGOP_MSK	include/ssv6200_aux.h	17026;"	d
+RG_SX_SEL_CHP_REGOP_SFT	include/ssv6200_aux.h	17028;"	d
+RG_SX_SEL_CHP_REGOP_SZ	include/ssv6200_aux.h	17030;"	d
+RG_SX_SEL_CHP_UNIOP_HI	include/ssv6200_aux.h	17034;"	d
+RG_SX_SEL_CHP_UNIOP_I_MSK	include/ssv6200_aux.h	17032;"	d
+RG_SX_SEL_CHP_UNIOP_MSK	include/ssv6200_aux.h	17031;"	d
+RG_SX_SEL_CHP_UNIOP_SFT	include/ssv6200_aux.h	17033;"	d
+RG_SX_SEL_CHP_UNIOP_SZ	include/ssv6200_aux.h	17035;"	d
+RG_SX_SEL_CP_HI	include/ssv6200_aux.h	16989;"	d
+RG_SX_SEL_CP_I_MSK	include/ssv6200_aux.h	16987;"	d
+RG_SX_SEL_CP_MSK	include/ssv6200_aux.h	16986;"	d
+RG_SX_SEL_CP_SFT	include/ssv6200_aux.h	16988;"	d
+RG_SX_SEL_CP_SZ	include/ssv6200_aux.h	16990;"	d
+RG_SX_SEL_CS_HI	include/ssv6200_aux.h	16994;"	d
+RG_SX_SEL_CS_I_MSK	include/ssv6200_aux.h	16992;"	d
+RG_SX_SEL_CS_MSK	include/ssv6200_aux.h	16991;"	d
+RG_SX_SEL_CS_SFT	include/ssv6200_aux.h	16993;"	d
+RG_SX_SEL_CS_SZ	include/ssv6200_aux.h	16995;"	d
+RG_SX_SEL_ICHP_HI	include/ssv6200_aux.h	17019;"	d
+RG_SX_SEL_ICHP_I_MSK	include/ssv6200_aux.h	17017;"	d
+RG_SX_SEL_ICHP_MSK	include/ssv6200_aux.h	17016;"	d
+RG_SX_SEL_ICHP_SFT	include/ssv6200_aux.h	17018;"	d
+RG_SX_SEL_ICHP_SZ	include/ssv6200_aux.h	17020;"	d
+RG_SX_SEL_PCHP_HI	include/ssv6200_aux.h	17024;"	d
+RG_SX_SEL_PCHP_I_MSK	include/ssv6200_aux.h	17022;"	d
+RG_SX_SEL_PCHP_MSK	include/ssv6200_aux.h	17021;"	d
+RG_SX_SEL_PCHP_SFT	include/ssv6200_aux.h	17023;"	d
+RG_SX_SEL_PCHP_SZ	include/ssv6200_aux.h	17025;"	d
+RG_SX_SEL_R3_HI	include/ssv6200_aux.h	17014;"	d
+RG_SX_SEL_R3_I_MSK	include/ssv6200_aux.h	17012;"	d
+RG_SX_SEL_R3_MSK	include/ssv6200_aux.h	17011;"	d
+RG_SX_SEL_R3_SFT	include/ssv6200_aux.h	17013;"	d
+RG_SX_SEL_R3_SZ	include/ssv6200_aux.h	17015;"	d
+RG_SX_SEL_RS_HI	include/ssv6200_aux.h	17009;"	d
+RG_SX_SEL_RS_I_MSK	include/ssv6200_aux.h	17007;"	d
+RG_SX_SEL_RS_MSK	include/ssv6200_aux.h	17006;"	d
+RG_SX_SEL_RS_SFT	include/ssv6200_aux.h	17008;"	d
+RG_SX_SEL_RS_SZ	include/ssv6200_aux.h	17010;"	d
+RG_SX_SUB_C0P5_DIS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23709;"	d
+RG_SX_SUB_C0P5_DIS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23707;"	d
+RG_SX_SUB_C0P5_DIS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23706;"	d
+RG_SX_SUB_C0P5_DIS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23708;"	d
+RG_SX_SUB_C0P5_DIS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23710;"	d
+RG_SX_SUB_MANUAL_HI	include/ssv6200_aux.h	17529;"	d
+RG_SX_SUB_MANUAL_I_MSK	include/ssv6200_aux.h	17527;"	d
+RG_SX_SUB_MANUAL_MSK	include/ssv6200_aux.h	17526;"	d
+RG_SX_SUB_MANUAL_SFT	include/ssv6200_aux.h	17528;"	d
+RG_SX_SUB_MANUAL_SZ	include/ssv6200_aux.h	17530;"	d
+RG_SX_SUB_SEL_CWD_HI	include/ssv6200_aux.h	17504;"	d
+RG_SX_SUB_SEL_CWD_I_MSK	include/ssv6200_aux.h	17502;"	d
+RG_SX_SUB_SEL_CWD_MSK	include/ssv6200_aux.h	17501;"	d
+RG_SX_SUB_SEL_CWD_SFT	include/ssv6200_aux.h	17503;"	d
+RG_SX_SUB_SEL_CWD_SZ	include/ssv6200_aux.h	17505;"	d
+RG_SX_SUB_SEL_CWR_HI	include/ssv6200_aux.h	17499;"	d
+RG_SX_SUB_SEL_CWR_I_MSK	include/ssv6200_aux.h	17497;"	d
+RG_SX_SUB_SEL_CWR_MSK	include/ssv6200_aux.h	17496;"	d
+RG_SX_SUB_SEL_CWR_SFT	include/ssv6200_aux.h	17498;"	d
+RG_SX_SUB_SEL_CWR_SZ	include/ssv6200_aux.h	17500;"	d
+RG_SX_SUB_SEL_HI	include/ssv6200_aux.h	17534;"	d
+RG_SX_SUB_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23704;"	d
+RG_SX_SUB_SEL_I_MSK	include/ssv6200_aux.h	17532;"	d
+RG_SX_SUB_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23702;"	d
+RG_SX_SUB_SEL_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23699;"	d
+RG_SX_SUB_SEL_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23697;"	d
+RG_SX_SUB_SEL_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23696;"	d
+RG_SX_SUB_SEL_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23698;"	d
+RG_SX_SUB_SEL_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23700;"	d
+RG_SX_SUB_SEL_MSK	include/ssv6200_aux.h	17531;"	d
+RG_SX_SUB_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23701;"	d
+RG_SX_SUB_SEL_SFT	include/ssv6200_aux.h	17533;"	d
+RG_SX_SUB_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23703;"	d
+RG_SX_SUB_SEL_SZ	include/ssv6200_aux.h	17535;"	d
+RG_SX_SUB_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23705;"	d
+RG_SX_TARGET_CNT_HI	include/ssv6200_aux.h	17639;"	d
+RG_SX_TARGET_CNT_I_MSK	include/ssv6200_aux.h	17637;"	d
+RG_SX_TARGET_CNT_MSK	include/ssv6200_aux.h	17636;"	d
+RG_SX_TARGET_CNT_SFT	include/ssv6200_aux.h	17638;"	d
+RG_SX_TARGET_CNT_SZ	include/ssv6200_aux.h	17640;"	d
+RG_SX_TTL_ACCUM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23819;"	d
+RG_SX_TTL_ACCUM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23817;"	d
+RG_SX_TTL_ACCUM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23816;"	d
+RG_SX_TTL_ACCUM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23818;"	d
+RG_SX_TTL_ACCUM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23820;"	d
+RG_SX_TTL_CPT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23814;"	d
+RG_SX_TTL_CPT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23812;"	d
+RG_SX_TTL_CPT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23811;"	d
+RG_SX_TTL_CPT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23813;"	d
+RG_SX_TTL_CPT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23815;"	d
+RG_SX_TTL_DIS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23224;"	d
+RG_SX_TTL_DIS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23222;"	d
+RG_SX_TTL_DIS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23221;"	d
+RG_SX_TTL_DIS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23223;"	d
+RG_SX_TTL_DIS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23225;"	d
+RG_SX_TTL_FPT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23809;"	d
+RG_SX_TTL_FPT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23807;"	d
+RG_SX_TTL_FPT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23806;"	d
+RG_SX_TTL_FPT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23808;"	d
+RG_SX_TTL_FPT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23810;"	d
+RG_SX_TTL_INIT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23804;"	d
+RG_SX_TTL_INIT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23802;"	d
+RG_SX_TTL_INIT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23801;"	d
+RG_SX_TTL_INIT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23803;"	d
+RG_SX_TTL_INIT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23805;"	d
+RG_SX_TTL_SUB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23824;"	d
+RG_SX_TTL_SUB_INV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23829;"	d
+RG_SX_TTL_SUB_INV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23827;"	d
+RG_SX_TTL_SUB_INV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23826;"	d
+RG_SX_TTL_SUB_INV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23828;"	d
+RG_SX_TTL_SUB_INV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23830;"	d
+RG_SX_TTL_SUB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23822;"	d
+RG_SX_TTL_SUB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23821;"	d
+RG_SX_TTL_SUB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23823;"	d
+RG_SX_TTL_SUB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23825;"	d
+RG_SX_TTL_VH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23834;"	d
+RG_SX_TTL_VH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23832;"	d
+RG_SX_TTL_VH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23831;"	d
+RG_SX_TTL_VH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23833;"	d
+RG_SX_TTL_VH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23835;"	d
+RG_SX_TTL_VL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23839;"	d
+RG_SX_TTL_VL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23837;"	d
+RG_SX_TTL_VL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23836;"	d
+RG_SX_TTL_VL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23838;"	d
+RG_SX_TTL_VL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23840;"	d
+RG_SX_TXBFSEL_HI	include/ssv6200_aux.h	17114;"	d
+RG_SX_TXBFSEL_I_MSK	include/ssv6200_aux.h	17112;"	d
+RG_SX_TXBFSEL_MSK	include/ssv6200_aux.h	17111;"	d
+RG_SX_TXBFSEL_SFT	include/ssv6200_aux.h	17113;"	d
+RG_SX_TXBFSEL_SZ	include/ssv6200_aux.h	17115;"	d
+RG_SX_UOP_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23154;"	d
+RG_SX_UOP_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23152;"	d
+RG_SX_UOP_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23151;"	d
+RG_SX_UOP_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23153;"	d
+RG_SX_UOP_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23155;"	d
+RG_SX_UOP_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23149;"	d
+RG_SX_UOP_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23147;"	d
+RG_SX_UOP_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23146;"	d
+RG_SX_UOP_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23148;"	d
+RG_SX_UOP_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23150;"	d
+RG_SX_VBNCAS_SEL_HI	include/ssv6200_aux.h	17069;"	d
+RG_SX_VBNCAS_SEL_I_MSK	include/ssv6200_aux.h	17067;"	d
+RG_SX_VBNCAS_SEL_MSK	include/ssv6200_aux.h	17066;"	d
+RG_SX_VBNCAS_SEL_SFT	include/ssv6200_aux.h	17068;"	d
+RG_SX_VBNCAS_SEL_SZ	include/ssv6200_aux.h	17070;"	d
+RG_SX_VCOBA_R_HI	include/ssv6200_aux.h	17094;"	d
+RG_SX_VCOBA_R_I_MSK	include/ssv6200_aux.h	17092;"	d
+RG_SX_VCOBA_R_MSK	include/ssv6200_aux.h	17091;"	d
+RG_SX_VCOBA_R_SFT	include/ssv6200_aux.h	17093;"	d
+RG_SX_VCOBA_R_SZ	include/ssv6200_aux.h	17095;"	d
+RG_SX_VCOBFSEL_HI	include/ssv6200_aux.h	17119;"	d
+RG_SX_VCOBFSEL_I_MSK	include/ssv6200_aux.h	17117;"	d
+RG_SX_VCOBFSEL_MSK	include/ssv6200_aux.h	17116;"	d
+RG_SX_VCOBFSEL_SFT	include/ssv6200_aux.h	17118;"	d
+RG_SX_VCOBFSEL_SZ	include/ssv6200_aux.h	17120;"	d
+RG_SX_VCOCUSEL_HI	include/ssv6200_aux.h	17104;"	d
+RG_SX_VCOCUSEL_I_MSK	include/ssv6200_aux.h	17102;"	d
+RG_SX_VCOCUSEL_MSK	include/ssv6200_aux.h	17101;"	d
+RG_SX_VCOCUSEL_SFT	include/ssv6200_aux.h	17103;"	d
+RG_SX_VCOCUSEL_SZ	include/ssv6200_aux.h	17105;"	d
+RG_SX_VCORSEL_HI	include/ssv6200_aux.h	17099;"	d
+RG_SX_VCORSEL_I_MSK	include/ssv6200_aux.h	17097;"	d
+RG_SX_VCORSEL_MSK	include/ssv6200_aux.h	17096;"	d
+RG_SX_VCORSEL_SFT	include/ssv6200_aux.h	17098;"	d
+RG_SX_VCORSEL_SZ	include/ssv6200_aux.h	17100;"	d
+RG_SX_VCO_CS_AWH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23579;"	d
+RG_SX_VCO_CS_AWH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23577;"	d
+RG_SX_VCO_CS_AWH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23576;"	d
+RG_SX_VCO_CS_AWH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23578;"	d
+RG_SX_VCO_CS_AWH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23580;"	d
+RG_SX_VCO_ISEL_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23529;"	d
+RG_SX_VCO_ISEL_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23527;"	d
+RG_SX_VCO_ISEL_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23526;"	d
+RG_SX_VCO_ISEL_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23528;"	d
+RG_SX_VCO_ISEL_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23530;"	d
+RG_SX_VCO_ISEL_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23524;"	d
+RG_SX_VCO_ISEL_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23522;"	d
+RG_SX_VCO_ISEL_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23521;"	d
+RG_SX_VCO_ISEL_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23523;"	d
+RG_SX_VCO_ISEL_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23525;"	d
+RG_SX_VCO_ISEL_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23549;"	d
+RG_SX_VCO_ISEL_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23547;"	d
+RG_SX_VCO_ISEL_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23546;"	d
+RG_SX_VCO_ISEL_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23548;"	d
+RG_SX_VCO_ISEL_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23550;"	d
+RG_SX_VCO_KVDOUB_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23544;"	d
+RG_SX_VCO_KVDOUB_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23542;"	d
+RG_SX_VCO_KVDOUB_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23541;"	d
+RG_SX_VCO_KVDOUB_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23543;"	d
+RG_SX_VCO_KVDOUB_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23545;"	d
+RG_SX_VCO_KVDOUB_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23564;"	d
+RG_SX_VCO_KVDOUB_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23562;"	d
+RG_SX_VCO_KVDOUB_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23561;"	d
+RG_SX_VCO_KVDOUB_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23563;"	d
+RG_SX_VCO_KVDOUB_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23565;"	d
+RG_SX_VCO_LPM_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23534;"	d
+RG_SX_VCO_LPM_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23532;"	d
+RG_SX_VCO_LPM_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23531;"	d
+RG_SX_VCO_LPM_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23533;"	d
+RG_SX_VCO_LPM_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23535;"	d
+RG_SX_VCO_LPM_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23554;"	d
+RG_SX_VCO_LPM_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23552;"	d
+RG_SX_VCO_LPM_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23551;"	d
+RG_SX_VCO_LPM_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23553;"	d
+RG_SX_VCO_LPM_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23555;"	d
+RG_SX_VCO_RTAIL_SHIFT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23574;"	d
+RG_SX_VCO_RTAIL_SHIFT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23572;"	d
+RG_SX_VCO_RTAIL_SHIFT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23571;"	d
+RG_SX_VCO_RTAIL_SHIFT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23573;"	d
+RG_SX_VCO_RTAIL_SHIFT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23575;"	d
+RG_SX_VCO_RXOB_AW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23634;"	d
+RG_SX_VCO_RXOB_AW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23632;"	d
+RG_SX_VCO_RXOB_AW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23631;"	d
+RG_SX_VCO_RXOB_AW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23633;"	d
+RG_SX_VCO_RXOB_AW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23635;"	d
+RG_SX_VCO_TXOB_AW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23629;"	d
+RG_SX_VCO_TXOB_AW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23627;"	d
+RG_SX_VCO_TXOB_AW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23626;"	d
+RG_SX_VCO_TXOB_AW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23628;"	d
+RG_SX_VCO_TXOB_AW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23630;"	d
+RG_SX_VCO_VARBSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23569;"	d
+RG_SX_VCO_VARBSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23567;"	d
+RG_SX_VCO_VARBSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23566;"	d
+RG_SX_VCO_VARBSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23568;"	d
+RG_SX_VCO_VARBSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23570;"	d
+RG_SX_VCO_VCCBSEL_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23539;"	d
+RG_SX_VCO_VCCBSEL_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23537;"	d
+RG_SX_VCO_VCCBSEL_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23536;"	d
+RG_SX_VCO_VCCBSEL_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23538;"	d
+RG_SX_VCO_VCCBSEL_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23540;"	d
+RG_SX_VCO_VCCBSEL_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23559;"	d
+RG_SX_VCO_VCCBSEL_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23557;"	d
+RG_SX_VCO_VCCBSEL_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23556;"	d
+RG_SX_VCO_VCCBSEL_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23558;"	d
+RG_SX_VCO_VCCBSEL_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23560;"	d
+RG_SX_VT_MON_MODE_HI	include/ssv6200_aux.h	17199;"	d
+RG_SX_VT_MON_MODE_I_MSK	include/ssv6200_aux.h	17197;"	d
+RG_SX_VT_MON_MODE_MSK	include/ssv6200_aux.h	17196;"	d
+RG_SX_VT_MON_MODE_SFT	include/ssv6200_aux.h	17198;"	d
+RG_SX_VT_MON_MODE_SZ	include/ssv6200_aux.h	17200;"	d
+RG_SX_VT_MON_TMR_HI	include/ssv6200_aux.h	17219;"	d
+RG_SX_VT_MON_TMR_I_MSK	include/ssv6200_aux.h	17217;"	d
+RG_SX_VT_MON_TMR_MSK	include/ssv6200_aux.h	17216;"	d
+RG_SX_VT_MON_TMR_SFT	include/ssv6200_aux.h	17218;"	d
+RG_SX_VT_MON_TMR_SZ	include/ssv6200_aux.h	17220;"	d
+RG_SX_VT_SET_HI	include/ssv6200_aux.h	17214;"	d
+RG_SX_VT_SET_I_MSK	include/ssv6200_aux.h	17212;"	d
+RG_SX_VT_SET_MSK	include/ssv6200_aux.h	17211;"	d
+RG_SX_VT_SET_SFT	include/ssv6200_aux.h	17213;"	d
+RG_SX_VT_SET_SZ	include/ssv6200_aux.h	17215;"	d
+RG_SX_VT_TH_HI_HI	include/ssv6200_aux.h	17204;"	d
+RG_SX_VT_TH_HI_I_MSK	include/ssv6200_aux.h	17202;"	d
+RG_SX_VT_TH_HI_MSK	include/ssv6200_aux.h	17201;"	d
+RG_SX_VT_TH_HI_SFT	include/ssv6200_aux.h	17203;"	d
+RG_SX_VT_TH_HI_SZ	include/ssv6200_aux.h	17205;"	d
+RG_SX_VT_TH_LO_HI	include/ssv6200_aux.h	17209;"	d
+RG_SX_VT_TH_LO_I_MSK	include/ssv6200_aux.h	17207;"	d
+RG_SX_VT_TH_LO_MSK	include/ssv6200_aux.h	17206;"	d
+RG_SX_VT_TH_LO_SFT	include/ssv6200_aux.h	17208;"	d
+RG_SX_VT_TH_LO_SZ	include/ssv6200_aux.h	17210;"	d
+RG_SX_XO_GM_HI	include/ssv6200_aux.h	17154;"	d
+RG_SX_XO_GM_I_MSK	include/ssv6200_aux.h	17152;"	d
+RG_SX_XO_GM_MSK	include/ssv6200_aux.h	17151;"	d
+RG_SX_XO_GM_SFT	include/ssv6200_aux.h	17153;"	d
+RG_SX_XO_GM_SZ	include/ssv6200_aux.h	17155;"	d
+RG_SX_XTAL_FREQ_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23384;"	d
+RG_SX_XTAL_FREQ_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23382;"	d
+RG_SX_XTAL_FREQ_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23381;"	d
+RG_SX_XTAL_FREQ_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23383;"	d
+RG_SX_XTAL_FREQ_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23385;"	d
+RG_SYM_BOUND_CNT_HI	include/ssv6200_aux.h	14799;"	d
+RG_SYM_BOUND_CNT_I_MSK	include/ssv6200_aux.h	14797;"	d
+RG_SYM_BOUND_CNT_MSK	include/ssv6200_aux.h	14796;"	d
+RG_SYM_BOUND_CNT_SFT	include/ssv6200_aux.h	14798;"	d
+RG_SYM_BOUND_CNT_SZ	include/ssv6200_aux.h	14800;"	d
+RG_SYM_BOUND_METHOD_HI	include/ssv6200_aux.h	14944;"	d
+RG_SYM_BOUND_METHOD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32184;"	d
+RG_SYM_BOUND_METHOD_I_MSK	include/ssv6200_aux.h	14942;"	d
+RG_SYM_BOUND_METHOD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32182;"	d
+RG_SYM_BOUND_METHOD_MSK	include/ssv6200_aux.h	14941;"	d
+RG_SYM_BOUND_METHOD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32181;"	d
+RG_SYM_BOUND_METHOD_SFT	include/ssv6200_aux.h	14943;"	d
+RG_SYM_BOUND_METHOD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32183;"	d
+RG_SYM_BOUND_METHOD_SZ	include/ssv6200_aux.h	14945;"	d
+RG_SYM_BOUND_METHOD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32185;"	d
+RG_SYSTEM_BW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30249;"	d
+RG_SYSTEM_BW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30247;"	d
+RG_SYSTEM_BW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30246;"	d
+RG_SYSTEM_BW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30248;"	d
+RG_SYSTEM_BW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30250;"	d
+RG_TBUS_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30809;"	d
+RG_TBUS_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30807;"	d
+RG_TBUS_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30806;"	d
+RG_TBUS_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30808;"	d
+RG_TBUS_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30810;"	d
+RG_TC_BIT_CNT_LMT_HI	include/ssv6200_aux.h	14534;"	d
+RG_TC_BIT_CNT_LMT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31689;"	d
+RG_TC_BIT_CNT_LMT_I_MSK	include/ssv6200_aux.h	14532;"	d
+RG_TC_BIT_CNT_LMT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31687;"	d
+RG_TC_BIT_CNT_LMT_MSK	include/ssv6200_aux.h	14531;"	d
+RG_TC_BIT_CNT_LMT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31686;"	d
+RG_TC_BIT_CNT_LMT_SFT	include/ssv6200_aux.h	14533;"	d
+RG_TC_BIT_CNT_LMT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31688;"	d
+RG_TC_BIT_CNT_LMT_SZ	include/ssv6200_aux.h	14535;"	d
+RG_TC_BIT_CNT_LMT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31690;"	d
+RG_THH_ED_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32759;"	d
+RG_THH_ED_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32757;"	d
+RG_THH_ED_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32756;"	d
+RG_THH_ED_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32758;"	d
+RG_THH_ED_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32760;"	d
+RG_THH_RATIO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32769;"	d
+RG_THH_RATIO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32767;"	d
+RG_THH_RATIO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32766;"	d
+RG_THH_RATIO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32768;"	d
+RG_THH_RATIO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32770;"	d
+RG_THL_ED_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32754;"	d
+RG_THL_ED_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32752;"	d
+RG_THL_ED_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32751;"	d
+RG_THL_ED_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32753;"	d
+RG_THL_ED_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32755;"	d
+RG_THL_RATIO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32764;"	d
+RG_THL_RATIO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32762;"	d
+RG_THL_RATIO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32761;"	d
+RG_THL_RATIO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32763;"	d
+RG_THL_RATIO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32765;"	d
+RG_TIME_PERIOD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32794;"	d
+RG_TIME_PERIOD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32792;"	d
+RG_TIME_PERIOD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32791;"	d
+RG_TIME_PERIOD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32793;"	d
+RG_TIME_PERIOD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32795;"	d
+RG_TOLERANCE_PERIOD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32819;"	d
+RG_TOLERANCE_PERIOD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32817;"	d
+RG_TOLERANCE_PERIOD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32816;"	d
+RG_TOLERANCE_PERIOD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32818;"	d
+RG_TOLERANCE_PERIOD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32820;"	d
+RG_TOLERANCE_PW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32824;"	d
+RG_TOLERANCE_PW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32822;"	d
+RG_TOLERANCE_PW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32821;"	d
+RG_TOLERANCE_PW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32823;"	d
+RG_TOLERANCE_PW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32825;"	d
+RG_TONEGEN2_EN_HI	include/ssv6200_aux.h	15414;"	d
+RG_TONEGEN2_EN_I_MSK	include/ssv6200_aux.h	15412;"	d
+RG_TONEGEN2_EN_MSK	include/ssv6200_aux.h	15411;"	d
+RG_TONEGEN2_EN_SFT	include/ssv6200_aux.h	15413;"	d
+RG_TONEGEN2_EN_SZ	include/ssv6200_aux.h	15415;"	d
+RG_TONEGEN2_FREQ_HI	include/ssv6200_aux.h	15409;"	d
+RG_TONEGEN2_FREQ_I_MSK	include/ssv6200_aux.h	15407;"	d
+RG_TONEGEN2_FREQ_MSK	include/ssv6200_aux.h	15406;"	d
+RG_TONEGEN2_FREQ_SFT	include/ssv6200_aux.h	15408;"	d
+RG_TONEGEN2_FREQ_SZ	include/ssv6200_aux.h	15410;"	d
+RG_TONEGEN2_SCALE_HI	include/ssv6200_aux.h	15419;"	d
+RG_TONEGEN2_SCALE_I_MSK	include/ssv6200_aux.h	15417;"	d
+RG_TONEGEN2_SCALE_MSK	include/ssv6200_aux.h	15416;"	d
+RG_TONEGEN2_SCALE_SFT	include/ssv6200_aux.h	15418;"	d
+RG_TONEGEN2_SCALE_SZ	include/ssv6200_aux.h	15420;"	d
+RG_TONEGEN_EN_HI	include/ssv6200_aux.h	15399;"	d
+RG_TONEGEN_EN_I_MSK	include/ssv6200_aux.h	15397;"	d
+RG_TONEGEN_EN_MSK	include/ssv6200_aux.h	15396;"	d
+RG_TONEGEN_EN_SFT	include/ssv6200_aux.h	15398;"	d
+RG_TONEGEN_EN_SZ	include/ssv6200_aux.h	15400;"	d
+RG_TONEGEN_FREQ_HI	include/ssv6200_aux.h	15394;"	d
+RG_TONEGEN_FREQ_I_MSK	include/ssv6200_aux.h	15392;"	d
+RG_TONEGEN_FREQ_MSK	include/ssv6200_aux.h	15391;"	d
+RG_TONEGEN_FREQ_SFT	include/ssv6200_aux.h	15393;"	d
+RG_TONEGEN_FREQ_SZ	include/ssv6200_aux.h	15395;"	d
+RG_TONEGEN_INIT_PH_HI	include/ssv6200_aux.h	15404;"	d
+RG_TONEGEN_INIT_PH_I_MSK	include/ssv6200_aux.h	15402;"	d
+RG_TONEGEN_INIT_PH_MSK	include/ssv6200_aux.h	15401;"	d
+RG_TONEGEN_INIT_PH_SFT	include/ssv6200_aux.h	15403;"	d
+RG_TONEGEN_INIT_PH_SZ	include/ssv6200_aux.h	15405;"	d
+RG_TONE_1_RATE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28919;"	d
+RG_TONE_1_RATE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28917;"	d
+RG_TONE_1_RATE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28916;"	d
+RG_TONE_1_RATE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28918;"	d
+RG_TONE_1_RATE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28920;"	d
+RG_TONE_GEN_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27279;"	d
+RG_TONE_GEN_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27277;"	d
+RG_TONE_GEN_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27276;"	d
+RG_TONE_GEN_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27278;"	d
+RG_TONE_GEN_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27280;"	d
+RG_TONE_SCALE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27269;"	d
+RG_TONE_SCALE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27267;"	d
+RG_TONE_SCALE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27266;"	d
+RG_TONE_SCALE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27268;"	d
+RG_TONE_SCALE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27270;"	d
+RG_TONE_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28914;"	d
+RG_TONE_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28912;"	d
+RG_TONE_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28911;"	d
+RG_TONE_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28913;"	d
+RG_TONE_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28915;"	d
+RG_TRX_DUMMMY_HI	include/ssv6200_aux.h	17544;"	d
+RG_TRX_DUMMMY_I_MSK	include/ssv6200_aux.h	17542;"	d
+RG_TRX_DUMMMY_MSK	include/ssv6200_aux.h	17541;"	d
+RG_TRX_DUMMMY_SFT	include/ssv6200_aux.h	17543;"	d
+RG_TRX_DUMMMY_SZ	include/ssv6200_aux.h	17545;"	d
+RG_TR_BIT_CNT_LMT_HI	include/ssv6200_aux.h	14544;"	d
+RG_TR_BIT_CNT_LMT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31699;"	d
+RG_TR_BIT_CNT_LMT_I_MSK	include/ssv6200_aux.h	14542;"	d
+RG_TR_BIT_CNT_LMT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31697;"	d
+RG_TR_BIT_CNT_LMT_MSK	include/ssv6200_aux.h	14541;"	d
+RG_TR_BIT_CNT_LMT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31696;"	d
+RG_TR_BIT_CNT_LMT_SFT	include/ssv6200_aux.h	14543;"	d
+RG_TR_BIT_CNT_LMT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31698;"	d
+RG_TR_BIT_CNT_LMT_SZ	include/ssv6200_aux.h	14545;"	d
+RG_TR_BIT_CNT_LMT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31700;"	d
+RG_TR_CNT_T0_HI	include/ssv6200_aux.h	14759;"	d
+RG_TR_CNT_T0_I_MSK	include/ssv6200_aux.h	14757;"	d
+RG_TR_CNT_T0_MSK	include/ssv6200_aux.h	14756;"	d
+RG_TR_CNT_T0_SFT	include/ssv6200_aux.h	14758;"	d
+RG_TR_CNT_T0_SZ	include/ssv6200_aux.h	14760;"	d
+RG_TR_CNT_T1_HI	include/ssv6200_aux.h	14744;"	d
+RG_TR_CNT_T1_I_MSK	include/ssv6200_aux.h	14742;"	d
+RG_TR_CNT_T1_MSK	include/ssv6200_aux.h	14741;"	d
+RG_TR_CNT_T1_SFT	include/ssv6200_aux.h	14743;"	d
+RG_TR_CNT_T1_SZ	include/ssv6200_aux.h	14745;"	d
+RG_TR_CNT_T2_HI	include/ssv6200_aux.h	14774;"	d
+RG_TR_CNT_T2_I_MSK	include/ssv6200_aux.h	14772;"	d
+RG_TR_CNT_T2_MSK	include/ssv6200_aux.h	14771;"	d
+RG_TR_CNT_T2_SFT	include/ssv6200_aux.h	14773;"	d
+RG_TR_CNT_T2_SZ	include/ssv6200_aux.h	14775;"	d
+RG_TR_CNT_UPDATE_HI	include/ssv6200_aux.h	15014;"	d
+RG_TR_CNT_UPDATE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32484;"	d
+RG_TR_CNT_UPDATE_I_MSK	include/ssv6200_aux.h	15012;"	d
+RG_TR_CNT_UPDATE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32482;"	d
+RG_TR_CNT_UPDATE_MSK	include/ssv6200_aux.h	15011;"	d
+RG_TR_CNT_UPDATE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32481;"	d
+RG_TR_CNT_UPDATE_SFT	include/ssv6200_aux.h	15013;"	d
+RG_TR_CNT_UPDATE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32483;"	d
+RG_TR_CNT_UPDATE_SGI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32474;"	d
+RG_TR_CNT_UPDATE_SGI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32472;"	d
+RG_TR_CNT_UPDATE_SGI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32471;"	d
+RG_TR_CNT_UPDATE_SGI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32473;"	d
+RG_TR_CNT_UPDATE_SGI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32475;"	d
+RG_TR_CNT_UPDATE_SZ	include/ssv6200_aux.h	15015;"	d
+RG_TR_CNT_UPDATE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32485;"	d
+RG_TR_KI_T1_HI	include/ssv6200_aux.h	14374;"	d
+RG_TR_KI_T1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31559;"	d
+RG_TR_KI_T1_I_MSK	include/ssv6200_aux.h	14372;"	d
+RG_TR_KI_T1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31557;"	d
+RG_TR_KI_T1_MSK	include/ssv6200_aux.h	14371;"	d
+RG_TR_KI_T1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31556;"	d
+RG_TR_KI_T1_SFT	include/ssv6200_aux.h	14373;"	d
+RG_TR_KI_T1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31558;"	d
+RG_TR_KI_T1_SZ	include/ssv6200_aux.h	14375;"	d
+RG_TR_KI_T1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31560;"	d
+RG_TR_KI_T2_HI	include/ssv6200_aux.h	14364;"	d
+RG_TR_KI_T2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31549;"	d
+RG_TR_KI_T2_I_MSK	include/ssv6200_aux.h	14362;"	d
+RG_TR_KI_T2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31547;"	d
+RG_TR_KI_T2_MSK	include/ssv6200_aux.h	14361;"	d
+RG_TR_KI_T2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31546;"	d
+RG_TR_KI_T2_SFT	include/ssv6200_aux.h	14363;"	d
+RG_TR_KI_T2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31548;"	d
+RG_TR_KI_T2_SZ	include/ssv6200_aux.h	14365;"	d
+RG_TR_KI_T2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31550;"	d
+RG_TR_KP_T1_HI	include/ssv6200_aux.h	14379;"	d
+RG_TR_KP_T1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31564;"	d
+RG_TR_KP_T1_I_MSK	include/ssv6200_aux.h	14377;"	d
+RG_TR_KP_T1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31562;"	d
+RG_TR_KP_T1_MSK	include/ssv6200_aux.h	14376;"	d
+RG_TR_KP_T1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31561;"	d
+RG_TR_KP_T1_SFT	include/ssv6200_aux.h	14378;"	d
+RG_TR_KP_T1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31563;"	d
+RG_TR_KP_T1_SZ	include/ssv6200_aux.h	14380;"	d
+RG_TR_KP_T1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31565;"	d
+RG_TR_KP_T2_HI	include/ssv6200_aux.h	14369;"	d
+RG_TR_KP_T2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31554;"	d
+RG_TR_KP_T2_I_MSK	include/ssv6200_aux.h	14367;"	d
+RG_TR_KP_T2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31552;"	d
+RG_TR_KP_T2_MSK	include/ssv6200_aux.h	14366;"	d
+RG_TR_KP_T2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31551;"	d
+RG_TR_KP_T2_SFT	include/ssv6200_aux.h	14368;"	d
+RG_TR_KP_T2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31553;"	d
+RG_TR_KP_T2_SZ	include/ssv6200_aux.h	14370;"	d
+RG_TR_KP_T2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31555;"	d
+RG_TR_LPF_KI_G_HI	include/ssv6200_aux.h	14779;"	d
+RG_TR_LPF_KI_G_I_MSK	include/ssv6200_aux.h	14777;"	d
+RG_TR_LPF_KI_G_MSK	include/ssv6200_aux.h	14776;"	d
+RG_TR_LPF_KI_G_SFT	include/ssv6200_aux.h	14778;"	d
+RG_TR_LPF_KI_G_SZ	include/ssv6200_aux.h	14780;"	d
+RG_TR_LPF_KI_G_T0_HI	include/ssv6200_aux.h	14749;"	d
+RG_TR_LPF_KI_G_T0_I_MSK	include/ssv6200_aux.h	14747;"	d
+RG_TR_LPF_KI_G_T0_MSK	include/ssv6200_aux.h	14746;"	d
+RG_TR_LPF_KI_G_T0_SFT	include/ssv6200_aux.h	14748;"	d
+RG_TR_LPF_KI_G_T0_SZ	include/ssv6200_aux.h	14750;"	d
+RG_TR_LPF_KI_G_T1_HI	include/ssv6200_aux.h	14734;"	d
+RG_TR_LPF_KI_G_T1_I_MSK	include/ssv6200_aux.h	14732;"	d
+RG_TR_LPF_KI_G_T1_MSK	include/ssv6200_aux.h	14731;"	d
+RG_TR_LPF_KI_G_T1_SFT	include/ssv6200_aux.h	14733;"	d
+RG_TR_LPF_KI_G_T1_SZ	include/ssv6200_aux.h	14735;"	d
+RG_TR_LPF_KI_G_T2_HI	include/ssv6200_aux.h	14764;"	d
+RG_TR_LPF_KI_G_T2_I_MSK	include/ssv6200_aux.h	14762;"	d
+RG_TR_LPF_KI_G_T2_MSK	include/ssv6200_aux.h	14761;"	d
+RG_TR_LPF_KI_G_T2_SFT	include/ssv6200_aux.h	14763;"	d
+RG_TR_LPF_KI_G_T2_SZ	include/ssv6200_aux.h	14765;"	d
+RG_TR_LPF_KP_G_HI	include/ssv6200_aux.h	14784;"	d
+RG_TR_LPF_KP_G_I_MSK	include/ssv6200_aux.h	14782;"	d
+RG_TR_LPF_KP_G_MSK	include/ssv6200_aux.h	14781;"	d
+RG_TR_LPF_KP_G_SFT	include/ssv6200_aux.h	14783;"	d
+RG_TR_LPF_KP_G_SZ	include/ssv6200_aux.h	14785;"	d
+RG_TR_LPF_KP_G_T0_HI	include/ssv6200_aux.h	14754;"	d
+RG_TR_LPF_KP_G_T0_I_MSK	include/ssv6200_aux.h	14752;"	d
+RG_TR_LPF_KP_G_T0_MSK	include/ssv6200_aux.h	14751;"	d
+RG_TR_LPF_KP_G_T0_SFT	include/ssv6200_aux.h	14753;"	d
+RG_TR_LPF_KP_G_T0_SZ	include/ssv6200_aux.h	14755;"	d
+RG_TR_LPF_KP_G_T1_HI	include/ssv6200_aux.h	14739;"	d
+RG_TR_LPF_KP_G_T1_I_MSK	include/ssv6200_aux.h	14737;"	d
+RG_TR_LPF_KP_G_T1_MSK	include/ssv6200_aux.h	14736;"	d
+RG_TR_LPF_KP_G_T1_SFT	include/ssv6200_aux.h	14738;"	d
+RG_TR_LPF_KP_G_T1_SZ	include/ssv6200_aux.h	14740;"	d
+RG_TR_LPF_KP_G_T2_HI	include/ssv6200_aux.h	14769;"	d
+RG_TR_LPF_KP_G_T2_I_MSK	include/ssv6200_aux.h	14767;"	d
+RG_TR_LPF_KP_G_T2_MSK	include/ssv6200_aux.h	14766;"	d
+RG_TR_LPF_KP_G_T2_SFT	include/ssv6200_aux.h	14768;"	d
+RG_TR_LPF_KP_G_T2_SZ	include/ssv6200_aux.h	14770;"	d
+RG_TR_LPF_RATE_GN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32029;"	d
+RG_TR_LPF_RATE_GN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32027;"	d
+RG_TR_LPF_RATE_GN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32026;"	d
+RG_TR_LPF_RATE_GN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32028;"	d
+RG_TR_LPF_RATE_GN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32030;"	d
+RG_TR_LPF_RATE_G_HI	include/ssv6200_aux.h	14789;"	d
+RG_TR_LPF_RATE_G_I_MSK	include/ssv6200_aux.h	14787;"	d
+RG_TR_LPF_RATE_G_MSK	include/ssv6200_aux.h	14786;"	d
+RG_TR_LPF_RATE_G_SFT	include/ssv6200_aux.h	14788;"	d
+RG_TR_LPF_RATE_G_SZ	include/ssv6200_aux.h	14790;"	d
+RG_TR_LPF_RATE_HI	include/ssv6200_aux.h	14519;"	d
+RG_TR_LPF_RATE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31674;"	d
+RG_TR_LPF_RATE_I_MSK	include/ssv6200_aux.h	14517;"	d
+RG_TR_LPF_RATE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31672;"	d
+RG_TR_LPF_RATE_MSK	include/ssv6200_aux.h	14516;"	d
+RG_TR_LPF_RATE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31671;"	d
+RG_TR_LPF_RATE_SFT	include/ssv6200_aux.h	14518;"	d
+RG_TR_LPF_RATE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31673;"	d
+RG_TR_LPF_RATE_SZ	include/ssv6200_aux.h	14520;"	d
+RG_TR_LPF_RATE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31675;"	d
+RG_TR_LPF_STBC_GF_KI_G_HI	include/ssv6200_aux.h	15094;"	d
+RG_TR_LPF_STBC_GF_KI_G_I_MSK	include/ssv6200_aux.h	15092;"	d
+RG_TR_LPF_STBC_GF_KI_G_MSK	include/ssv6200_aux.h	15091;"	d
+RG_TR_LPF_STBC_GF_KI_G_SFT	include/ssv6200_aux.h	15093;"	d
+RG_TR_LPF_STBC_GF_KI_G_SZ	include/ssv6200_aux.h	15095;"	d
+RG_TR_LPF_STBC_GF_KP_G_HI	include/ssv6200_aux.h	15099;"	d
+RG_TR_LPF_STBC_GF_KP_G_I_MSK	include/ssv6200_aux.h	15097;"	d
+RG_TR_LPF_STBC_GF_KP_G_MSK	include/ssv6200_aux.h	15096;"	d
+RG_TR_LPF_STBC_GF_KP_G_SFT	include/ssv6200_aux.h	15098;"	d
+RG_TR_LPF_STBC_GF_KP_G_SZ	include/ssv6200_aux.h	15100;"	d
+RG_TR_LPF_STBC_MF_KI_G_HI	include/ssv6200_aux.h	15104;"	d
+RG_TR_LPF_STBC_MF_KI_G_I_MSK	include/ssv6200_aux.h	15102;"	d
+RG_TR_LPF_STBC_MF_KI_G_MSK	include/ssv6200_aux.h	15101;"	d
+RG_TR_LPF_STBC_MF_KI_G_SFT	include/ssv6200_aux.h	15103;"	d
+RG_TR_LPF_STBC_MF_KI_G_SZ	include/ssv6200_aux.h	15105;"	d
+RG_TR_LPF_STBC_MF_KP_G_HI	include/ssv6200_aux.h	15109;"	d
+RG_TR_LPF_STBC_MF_KP_G_I_MSK	include/ssv6200_aux.h	15107;"	d
+RG_TR_LPF_STBC_MF_KP_G_MSK	include/ssv6200_aux.h	15106;"	d
+RG_TR_LPF_STBC_MF_KP_G_SFT	include/ssv6200_aux.h	15108;"	d
+RG_TR_LPF_STBC_MF_KP_G_SZ	include/ssv6200_aux.h	15110;"	d
+RG_TST_ADC_ON_HI	include/ssv6200_aux.h	13779;"	d
+RG_TST_ADC_ON_I_MSK	include/ssv6200_aux.h	13777;"	d
+RG_TST_ADC_ON_MSK	include/ssv6200_aux.h	13776;"	d
+RG_TST_ADC_ON_SFT	include/ssv6200_aux.h	13778;"	d
+RG_TST_ADC_ON_SZ	include/ssv6200_aux.h	13780;"	d
+RG_TST_EXT_GAIN_HI	include/ssv6200_aux.h	13784;"	d
+RG_TST_EXT_GAIN_I_MSK	include/ssv6200_aux.h	13782;"	d
+RG_TST_EXT_GAIN_MSK	include/ssv6200_aux.h	13781;"	d
+RG_TST_EXT_GAIN_SFT	include/ssv6200_aux.h	13783;"	d
+RG_TST_EXT_GAIN_SZ	include/ssv6200_aux.h	13785;"	d
+RG_TST_TBUS_SEL_HI	include/ssv6200_aux.h	13764;"	d
+RG_TST_TBUS_SEL_I_MSK	include/ssv6200_aux.h	13762;"	d
+RG_TST_TBUS_SEL_MSK	include/ssv6200_aux.h	13761;"	d
+RG_TST_TBUS_SEL_SFT	include/ssv6200_aux.h	13763;"	d
+RG_TST_TBUS_SEL_SZ	include/ssv6200_aux.h	13765;"	d
+RG_TURISMO_TRX_40M_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20154;"	d
+RG_TURISMO_TRX_40M_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20152;"	d
+RG_TURISMO_TRX_40M_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20151;"	d
+RG_TURISMO_TRX_40M_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20153;"	d
+RG_TURISMO_TRX_40M_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20155;"	d
+RG_TURISMO_TRX_5G_EN_IREF_RX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18214;"	d
+RG_TURISMO_TRX_5G_EN_IREF_RX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18212;"	d
+RG_TURISMO_TRX_5G_EN_IREF_RX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18211;"	d
+RG_TURISMO_TRX_5G_EN_IREF_RX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18213;"	d
+RG_TURISMO_TRX_5G_EN_IREF_RX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18215;"	d
+RG_TURISMO_TRX_5G_EN_LDO_RX_FE_BYP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18169;"	d
+RG_TURISMO_TRX_5G_EN_LDO_RX_FE_BYP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18167;"	d
+RG_TURISMO_TRX_5G_EN_LDO_RX_FE_BYP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18166;"	d
+RG_TURISMO_TRX_5G_EN_LDO_RX_FE_BYP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18168;"	d
+RG_TURISMO_TRX_5G_EN_LDO_RX_FE_BYP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18170;"	d
+RG_TURISMO_TRX_5G_EN_LDO_RX_FE_FC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18219;"	d
+RG_TURISMO_TRX_5G_EN_LDO_RX_FE_FC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18217;"	d
+RG_TURISMO_TRX_5G_EN_LDO_RX_FE_FC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18216;"	d
+RG_TURISMO_TRX_5G_EN_LDO_RX_FE_FC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18218;"	d
+RG_TURISMO_TRX_5G_EN_LDO_RX_FE_FC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18220;"	d
+RG_TURISMO_TRX_5G_EN_LDO_RX_FE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18209;"	d
+RG_TURISMO_TRX_5G_EN_LDO_RX_FE_IQUP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18224;"	d
+RG_TURISMO_TRX_5G_EN_LDO_RX_FE_IQUP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18222;"	d
+RG_TURISMO_TRX_5G_EN_LDO_RX_FE_IQUP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18221;"	d
+RG_TURISMO_TRX_5G_EN_LDO_RX_FE_IQUP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18223;"	d
+RG_TURISMO_TRX_5G_EN_LDO_RX_FE_IQUP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18225;"	d
+RG_TURISMO_TRX_5G_EN_LDO_RX_FE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18207;"	d
+RG_TURISMO_TRX_5G_EN_LDO_RX_FE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18206;"	d
+RG_TURISMO_TRX_5G_EN_LDO_RX_FE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18208;"	d
+RG_TURISMO_TRX_5G_EN_LDO_RX_FE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18210;"	d
+RG_TURISMO_TRX_5G_EN_RX_DIV2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18054;"	d
+RG_TURISMO_TRX_5G_EN_RX_DIV2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18052;"	d
+RG_TURISMO_TRX_5G_EN_RX_DIV2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18051;"	d
+RG_TURISMO_TRX_5G_EN_RX_DIV2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18053;"	d
+RG_TURISMO_TRX_5G_EN_RX_DIV2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18055;"	d
+RG_TURISMO_TRX_5G_EN_RX_IQCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18144;"	d
+RG_TURISMO_TRX_5G_EN_RX_IQCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18142;"	d
+RG_TURISMO_TRX_5G_EN_RX_IQCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18141;"	d
+RG_TURISMO_TRX_5G_EN_RX_IQCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18143;"	d
+RG_TURISMO_TRX_5G_EN_RX_IQCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18145;"	d
+RG_TURISMO_TRX_5G_EN_RX_LNA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18034;"	d
+RG_TURISMO_TRX_5G_EN_RX_LNA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18032;"	d
+RG_TURISMO_TRX_5G_EN_RX_LNA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18031;"	d
+RG_TURISMO_TRX_5G_EN_RX_LNA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18033;"	d
+RG_TURISMO_TRX_5G_EN_RX_LNA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18035;"	d
+RG_TURISMO_TRX_5G_EN_RX_LOBUF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18064;"	d
+RG_TURISMO_TRX_5G_EN_RX_LOBUF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18062;"	d
+RG_TURISMO_TRX_5G_EN_RX_LOBUF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18061;"	d
+RG_TURISMO_TRX_5G_EN_RX_LOBUF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18063;"	d
+RG_TURISMO_TRX_5G_EN_RX_LOBUF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18065;"	d
+RG_TURISMO_TRX_5G_EN_RX_MIXER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18044;"	d
+RG_TURISMO_TRX_5G_EN_RX_MIXER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18042;"	d
+RG_TURISMO_TRX_5G_EN_RX_MIXER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18041;"	d
+RG_TURISMO_TRX_5G_EN_RX_MIXER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18043;"	d
+RG_TURISMO_TRX_5G_EN_RX_MIXER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18045;"	d
+RG_TURISMO_TRX_5G_EN_RX_TZ_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18074;"	d
+RG_TURISMO_TRX_5G_EN_RX_TZ_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18072;"	d
+RG_TURISMO_TRX_5G_EN_RX_TZ_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18071;"	d
+RG_TURISMO_TRX_5G_EN_RX_TZ_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18073;"	d
+RG_TURISMO_TRX_5G_EN_RX_TZ_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18075;"	d
+RG_TURISMO_TRX_5G_EN_TX_DIV2_BUF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18114;"	d
+RG_TURISMO_TRX_5G_EN_TX_DIV2_BUF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18112;"	d
+RG_TURISMO_TRX_5G_EN_TX_DIV2_BUF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18111;"	d
+RG_TURISMO_TRX_5G_EN_TX_DIV2_BUF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18113;"	d
+RG_TURISMO_TRX_5G_EN_TX_DIV2_BUF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18115;"	d
+RG_TURISMO_TRX_5G_EN_TX_DIV2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18104;"	d
+RG_TURISMO_TRX_5G_EN_TX_DIV2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18102;"	d
+RG_TURISMO_TRX_5G_EN_TX_DIV2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18101;"	d
+RG_TURISMO_TRX_5G_EN_TX_DIV2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18103;"	d
+RG_TURISMO_TRX_5G_EN_TX_DIV2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18105;"	d
+RG_TURISMO_TRX_5G_EN_TX_DPD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18154;"	d
+RG_TURISMO_TRX_5G_EN_TX_DPD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18152;"	d
+RG_TURISMO_TRX_5G_EN_TX_DPD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18151;"	d
+RG_TURISMO_TRX_5G_EN_TX_DPD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18153;"	d
+RG_TURISMO_TRX_5G_EN_TX_DPD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18155;"	d
+RG_TURISMO_TRX_5G_EN_TX_MOD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18094;"	d
+RG_TURISMO_TRX_5G_EN_TX_MOD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18092;"	d
+RG_TURISMO_TRX_5G_EN_TX_MOD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18091;"	d
+RG_TURISMO_TRX_5G_EN_TX_MOD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18093;"	d
+RG_TURISMO_TRX_5G_EN_TX_MOD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18095;"	d
+RG_TURISMO_TRX_5G_EN_TX_PA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18084;"	d
+RG_TURISMO_TRX_5G_EN_TX_PA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18082;"	d
+RG_TURISMO_TRX_5G_EN_TX_PA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18081;"	d
+RG_TURISMO_TRX_5G_EN_TX_PA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18083;"	d
+RG_TURISMO_TRX_5G_EN_TX_PA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18085;"	d
+RG_TURISMO_TRX_5G_EN_TX_SELF_MIXER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18134;"	d
+RG_TURISMO_TRX_5G_EN_TX_SELF_MIXER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18132;"	d
+RG_TURISMO_TRX_5G_EN_TX_SELF_MIXER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18131;"	d
+RG_TURISMO_TRX_5G_EN_TX_SELF_MIXER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18133;"	d
+RG_TURISMO_TRX_5G_EN_TX_SELF_MIXER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18135;"	d
+RG_TURISMO_TRX_5G_EN_TX_TRSW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18024;"	d
+RG_TURISMO_TRX_5G_EN_TX_TRSW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18022;"	d
+RG_TURISMO_TRX_5G_EN_TX_TRSW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18021;"	d
+RG_TURISMO_TRX_5G_EN_TX_TRSW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18023;"	d
+RG_TURISMO_TRX_5G_EN_TX_TRSW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18025;"	d
+RG_TURISMO_TRX_5G_EN_TX_TSSI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18159;"	d
+RG_TURISMO_TRX_5G_EN_TX_TSSI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18157;"	d
+RG_TURISMO_TRX_5G_EN_TX_TSSI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18156;"	d
+RG_TURISMO_TRX_5G_EN_TX_TSSI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18158;"	d
+RG_TURISMO_TRX_5G_EN_TX_TSSI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18160;"	d
+RG_TURISMO_TRX_5G_GM_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18259;"	d
+RG_TURISMO_TRX_5G_GM_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18257;"	d
+RG_TURISMO_TRX_5G_GM_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18256;"	d
+RG_TURISMO_TRX_5G_GM_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18258;"	d
+RG_TURISMO_TRX_5G_GM_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18260;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19784;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19782;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19781;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19783;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19785;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19774;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19772;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19771;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19773;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19775;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19764;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19762;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19761;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19763;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19765;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19754;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19752;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19751;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19753;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19755;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19744;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19742;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19741;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19743;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19745;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19574;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19572;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19571;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19573;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19575;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG10_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19474;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG10_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19472;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG10_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19471;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG10_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19473;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG10_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19475;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG11_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19464;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG11_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19462;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG11_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19461;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG11_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19463;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG11_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19465;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG12_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19454;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG12_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19452;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG12_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19451;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG12_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19453;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG12_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19455;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG13_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19444;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG13_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19442;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG13_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19441;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG13_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19443;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG13_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19445;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG14_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19434;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG14_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19432;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG14_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19431;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG14_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19433;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG14_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19435;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG15_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19424;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG15_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19422;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG15_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19421;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG15_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19423;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG15_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19425;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19564;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19562;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19561;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19563;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19565;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19554;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19552;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19551;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19553;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19555;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19544;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19542;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19541;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19543;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19545;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19534;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19532;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19531;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19533;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19535;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19524;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19522;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19521;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19523;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19525;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19514;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19512;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19511;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19513;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19515;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19504;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19502;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19501;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19503;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19505;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG8_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19494;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG8_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19492;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG8_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19491;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG8_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19493;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG8_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19495;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG9_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19484;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG9_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19482;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG9_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19481;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG9_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19483;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG9_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19485;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19834;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19832;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19831;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19833;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19835;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19824;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19822;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19821;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19823;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19825;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19814;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19812;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19811;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19813;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19815;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19804;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19802;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19801;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19803;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19805;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19794;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19792;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19791;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19793;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19795;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19734;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19732;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19731;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19733;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19735;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG10_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19634;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG10_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19632;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG10_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19631;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG10_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19633;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG10_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19635;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG11_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19624;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG11_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19622;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG11_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19621;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG11_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19623;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG11_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19625;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG12_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19614;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG12_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19612;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG12_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19611;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG12_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19613;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG12_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19615;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG13_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19604;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG13_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19602;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG13_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19601;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG13_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19603;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG13_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19605;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG14_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19594;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG14_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19592;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG14_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19591;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG14_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19593;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG14_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19595;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG15_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19584;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG15_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19582;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG15_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19581;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG15_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19583;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG15_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19585;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19724;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19722;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19721;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19723;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19725;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19714;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19712;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19711;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19713;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19715;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19704;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19702;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19701;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19703;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19705;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19694;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19692;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19691;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19693;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19695;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19684;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19682;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19681;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19683;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19685;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19674;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19672;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19671;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19673;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19675;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19664;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19662;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19661;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19663;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19665;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG8_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19654;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG8_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19652;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG8_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19651;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG8_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19653;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG8_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19655;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG9_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19644;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG9_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19642;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG9_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19641;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG9_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19643;"	d
+RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG9_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19645;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19789;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19787;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19786;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19788;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19790;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19779;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19777;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19776;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19778;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19780;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19769;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19767;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19766;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19768;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19770;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19759;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19757;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19756;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19758;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19760;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19749;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19747;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19746;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19748;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19750;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19579;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19577;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19576;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19578;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19580;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG10_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19479;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG10_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19477;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG10_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19476;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG10_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19478;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG10_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19480;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG11_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19469;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG11_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19467;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG11_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19466;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG11_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19468;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG11_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19470;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG12_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19459;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG12_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19457;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG12_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19456;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG12_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19458;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG12_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19460;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG13_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19449;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG13_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19447;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG13_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19446;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG13_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19448;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG13_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19450;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG14_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19439;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG14_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19437;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG14_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19436;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG14_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19438;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG14_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19440;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG15_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19429;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG15_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19427;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG15_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19426;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG15_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19428;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG15_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19430;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19569;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19567;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19566;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19568;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19570;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19559;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19557;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19556;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19558;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19560;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19549;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19547;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19546;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19548;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19550;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19539;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19537;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19536;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19538;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19540;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19529;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19527;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19526;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19528;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19530;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19519;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19517;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19516;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19518;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19520;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19509;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19507;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19506;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19508;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19510;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG8_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19499;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG8_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19497;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG8_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19496;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG8_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19498;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG8_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19500;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG9_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19489;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG9_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19487;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG9_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19486;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG9_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19488;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG9_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19490;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19839;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19837;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19836;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19838;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19840;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19829;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19827;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19826;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19828;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19830;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19819;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19817;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19816;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19818;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19820;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19809;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19807;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19806;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19808;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19810;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19799;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19797;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19796;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19798;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19800;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19739;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19737;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19736;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19738;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19740;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG10_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19639;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG10_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19637;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG10_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19636;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG10_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19638;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG10_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19640;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG11_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19629;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG11_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19627;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG11_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19626;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG11_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19628;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG11_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19630;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG12_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19619;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG12_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19617;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG12_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19616;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG12_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19618;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG12_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19620;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG13_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19609;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG13_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19607;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG13_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19606;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG13_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19608;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG13_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19610;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG14_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19599;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG14_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19597;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG14_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19596;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG14_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19598;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG14_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19600;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG15_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19589;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG15_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19587;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG15_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19586;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG15_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19588;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG15_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19590;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19729;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19727;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19726;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19728;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19730;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19719;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19717;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19716;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19718;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19720;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19709;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19707;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19706;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19708;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19710;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19699;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19697;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19696;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19698;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19700;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19689;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19687;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19686;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19688;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19690;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19679;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19677;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19676;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19678;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19680;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19669;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19667;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19666;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19668;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19670;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG8_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19659;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG8_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19657;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG8_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19656;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG8_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19658;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG8_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19660;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG9_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19649;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG9_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19647;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG9_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19646;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG9_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19648;"	d
+RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG9_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19650;"	d
+RG_TURISMO_TRX_5G_LDO_LEVEL_RX_FE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18164;"	d
+RG_TURISMO_TRX_5G_LDO_LEVEL_RX_FE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18162;"	d
+RG_TURISMO_TRX_5G_LDO_LEVEL_RX_FE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18161;"	d
+RG_TURISMO_TRX_5G_LDO_LEVEL_RX_FE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18163;"	d
+RG_TURISMO_TRX_5G_LDO_LEVEL_RX_FE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18165;"	d
+RG_TURISMO_TRX_5G_PABIAS_CTRL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18354;"	d
+RG_TURISMO_TRX_5G_PABIAS_CTRL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18352;"	d
+RG_TURISMO_TRX_5G_PABIAS_CTRL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18351;"	d
+RG_TURISMO_TRX_5G_PABIAS_CTRL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18353;"	d
+RG_TURISMO_TRX_5G_PABIAS_CTRL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18355;"	d
+RG_TURISMO_TRX_5G_PACELL_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18349;"	d
+RG_TURISMO_TRX_5G_PACELL_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18347;"	d
+RG_TURISMO_TRX_5G_PACELL_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18346;"	d
+RG_TURISMO_TRX_5G_PACELL_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18348;"	d
+RG_TURISMO_TRX_5G_PACELL_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18350;"	d
+RG_TURISMO_TRX_5G_PGAG_DPDCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19964;"	d
+RG_TURISMO_TRX_5G_PGAG_DPDCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19962;"	d
+RG_TURISMO_TRX_5G_PGAG_DPDCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19961;"	d
+RG_TURISMO_TRX_5G_PGAG_DPDCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19963;"	d
+RG_TURISMO_TRX_5G_PGAG_DPDCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19965;"	d
+RG_TURISMO_TRX_5G_PGAG_RCCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19939;"	d
+RG_TURISMO_TRX_5G_PGAG_RCCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19937;"	d
+RG_TURISMO_TRX_5G_PGAG_RCCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19936;"	d
+RG_TURISMO_TRX_5G_PGAG_RCCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19938;"	d
+RG_TURISMO_TRX_5G_PGAG_RCCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19940;"	d
+RG_TURISMO_TRX_5G_PGAG_RXIQCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19949;"	d
+RG_TURISMO_TRX_5G_PGAG_RXIQCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19947;"	d
+RG_TURISMO_TRX_5G_PGAG_RXIQCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19946;"	d
+RG_TURISMO_TRX_5G_PGAG_RXIQCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19948;"	d
+RG_TURISMO_TRX_5G_PGAG_RXIQCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19950;"	d
+RG_TURISMO_TRX_5G_PGAG_TXCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19929;"	d
+RG_TURISMO_TRX_5G_PGAG_TXCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19927;"	d
+RG_TURISMO_TRX_5G_PGAG_TXCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19926;"	d
+RG_TURISMO_TRX_5G_PGAG_TXCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19928;"	d
+RG_TURISMO_TRX_5G_PGAG_TXCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19930;"	d
+RG_TURISMO_TRX_5G_RFG_DPDCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19959;"	d
+RG_TURISMO_TRX_5G_RFG_DPDCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19957;"	d
+RG_TURISMO_TRX_5G_RFG_DPDCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19956;"	d
+RG_TURISMO_TRX_5G_RFG_DPDCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19958;"	d
+RG_TURISMO_TRX_5G_RFG_DPDCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19960;"	d
+RG_TURISMO_TRX_5G_RFG_RXIQCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19944;"	d
+RG_TURISMO_TRX_5G_RFG_RXIQCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19942;"	d
+RG_TURISMO_TRX_5G_RFG_RXIQCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19941;"	d
+RG_TURISMO_TRX_5G_RFG_RXIQCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19943;"	d
+RG_TURISMO_TRX_5G_RFG_RXIQCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19945;"	d
+RG_TURISMO_TRX_5G_RXRF_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19864;"	d
+RG_TURISMO_TRX_5G_RXRF_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19862;"	d
+RG_TURISMO_TRX_5G_RXRF_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19861;"	d
+RG_TURISMO_TRX_5G_RXRF_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19863;"	d
+RG_TURISMO_TRX_5G_RXRF_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19865;"	d
+RG_TURISMO_TRX_5G_RXRF_R2T_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19904;"	d
+RG_TURISMO_TRX_5G_RXRF_R2T_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19902;"	d
+RG_TURISMO_TRX_5G_RXRF_R2T_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19901;"	d
+RG_TURISMO_TRX_5G_RXRF_R2T_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19903;"	d
+RG_TURISMO_TRX_5G_RXRF_R2T_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19905;"	d
+RG_TURISMO_TRX_5G_RXRF_T2R_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19884;"	d
+RG_TURISMO_TRX_5G_RXRF_T2R_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19882;"	d
+RG_TURISMO_TRX_5G_RXRF_T2R_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19881;"	d
+RG_TURISMO_TRX_5G_RXRF_T2R_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19883;"	d
+RG_TURISMO_TRX_5G_RXRF_T2R_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19885;"	d
+RG_TURISMO_TRX_5G_RX_ADC_CLOAD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18329;"	d
+RG_TURISMO_TRX_5G_RX_ADC_CLOAD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18327;"	d
+RG_TURISMO_TRX_5G_RX_ADC_CLOAD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18326;"	d
+RG_TURISMO_TRX_5G_RX_ADC_CLOAD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18328;"	d
+RG_TURISMO_TRX_5G_RX_ADC_CLOAD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18330;"	d
+RG_TURISMO_TRX_5G_RX_ADC_ICMP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18319;"	d
+RG_TURISMO_TRX_5G_RX_ADC_ICMP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18317;"	d
+RG_TURISMO_TRX_5G_RX_ADC_ICMP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18316;"	d
+RG_TURISMO_TRX_5G_RX_ADC_ICMP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18318;"	d
+RG_TURISMO_TRX_5G_RX_ADC_ICMP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18320;"	d
+RG_TURISMO_TRX_5G_RX_ADC_VCMI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18324;"	d
+RG_TURISMO_TRX_5G_RX_ADC_VCMI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18322;"	d
+RG_TURISMO_TRX_5G_RX_ADC_VCMI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18321;"	d
+RG_TURISMO_TRX_5G_RX_ADC_VCMI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18323;"	d
+RG_TURISMO_TRX_5G_RX_ADC_VCMI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18325;"	d
+RG_TURISMO_TRX_5G_RX_DCCAL_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19909;"	d
+RG_TURISMO_TRX_5G_RX_DCCAL_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19907;"	d
+RG_TURISMO_TRX_5G_RX_DCCAL_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19906;"	d
+RG_TURISMO_TRX_5G_RX_DCCAL_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19908;"	d
+RG_TURISMO_TRX_5G_RX_DCCAL_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19910;"	d
+RG_TURISMO_TRX_5G_RX_DIV2_BUF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18264;"	d
+RG_TURISMO_TRX_5G_RX_DIV2_BUF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18262;"	d
+RG_TURISMO_TRX_5G_RX_DIV2_BUF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18261;"	d
+RG_TURISMO_TRX_5G_RX_DIV2_BUF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18263;"	d
+RG_TURISMO_TRX_5G_RX_DIV2_BUF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18265;"	d
+RG_TURISMO_TRX_5G_RX_DIV2_CML_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18269;"	d
+RG_TURISMO_TRX_5G_RX_DIV2_CML_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18267;"	d
+RG_TURISMO_TRX_5G_RX_DIV2_CML_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18266;"	d
+RG_TURISMO_TRX_5G_RX_DIV2_CML_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18268;"	d
+RG_TURISMO_TRX_5G_RX_DIV2_CML_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18270;"	d
+RG_TURISMO_TRX_5G_RX_DIV2_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18049;"	d
+RG_TURISMO_TRX_5G_RX_DIV2_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18047;"	d
+RG_TURISMO_TRX_5G_RX_DIV2_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18046;"	d
+RG_TURISMO_TRX_5G_RX_DIV2_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18048;"	d
+RG_TURISMO_TRX_5G_RX_DIV2_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18050;"	d
+RG_TURISMO_TRX_5G_RX_DIV_CMLISEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18274;"	d
+RG_TURISMO_TRX_5G_RX_DIV_CMLISEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18272;"	d
+RG_TURISMO_TRX_5G_RX_DIV_CMLISEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18271;"	d
+RG_TURISMO_TRX_5G_RX_DIV_CMLISEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18273;"	d
+RG_TURISMO_TRX_5G_RX_DIV_CMLISEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18275;"	d
+RG_TURISMO_TRX_5G_RX_DIV_PREBUFS2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18279;"	d
+RG_TURISMO_TRX_5G_RX_DIV_PREBUFS2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18277;"	d
+RG_TURISMO_TRX_5G_RX_DIV_PREBUFS2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18276;"	d
+RG_TURISMO_TRX_5G_RX_DIV_PREBUFS2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18278;"	d
+RG_TURISMO_TRX_5G_RX_DIV_PREBUFS2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18280;"	d
+RG_TURISMO_TRX_5G_RX_GM_IDB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18254;"	d
+RG_TURISMO_TRX_5G_RX_GM_IDB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18252;"	d
+RG_TURISMO_TRX_5G_RX_GM_IDB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18251;"	d
+RG_TURISMO_TRX_5G_RX_GM_IDB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18253;"	d
+RG_TURISMO_TRX_5G_RX_GM_IDB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18255;"	d
+RG_TURISMO_TRX_5G_RX_HG_DIV2_CORE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18464;"	d
+RG_TURISMO_TRX_5G_RX_HG_DIV2_CORE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18462;"	d
+RG_TURISMO_TRX_5G_RX_HG_DIV2_CORE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18461;"	d
+RG_TURISMO_TRX_5G_RX_HG_DIV2_CORE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18463;"	d
+RG_TURISMO_TRX_5G_RX_HG_DIV2_CORE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18465;"	d
+RG_TURISMO_TRX_5G_RX_HG_LNAHGN_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18439;"	d
+RG_TURISMO_TRX_5G_RX_HG_LNAHGN_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18437;"	d
+RG_TURISMO_TRX_5G_RX_HG_LNAHGN_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18436;"	d
+RG_TURISMO_TRX_5G_RX_HG_LNAHGN_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18438;"	d
+RG_TURISMO_TRX_5G_RX_HG_LNAHGN_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18440;"	d
+RG_TURISMO_TRX_5G_RX_HG_LNAHGP_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18444;"	d
+RG_TURISMO_TRX_5G_RX_HG_LNAHGP_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18442;"	d
+RG_TURISMO_TRX_5G_RX_HG_LNAHGP_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18441;"	d
+RG_TURISMO_TRX_5G_RX_HG_LNAHGP_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18443;"	d
+RG_TURISMO_TRX_5G_RX_HG_LNAHGP_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18445;"	d
+RG_TURISMO_TRX_5G_RX_HG_LNALG_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18449;"	d
+RG_TURISMO_TRX_5G_RX_HG_LNALG_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18447;"	d
+RG_TURISMO_TRX_5G_RX_HG_LNALG_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18446;"	d
+RG_TURISMO_TRX_5G_RX_HG_LNALG_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18448;"	d
+RG_TURISMO_TRX_5G_RX_HG_LNALG_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18450;"	d
+RG_TURISMO_TRX_5G_RX_HG_LNA_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18429;"	d
+RG_TURISMO_TRX_5G_RX_HG_LNA_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18427;"	d
+RG_TURISMO_TRX_5G_RX_HG_LNA_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18426;"	d
+RG_TURISMO_TRX_5G_RX_HG_LNA_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18428;"	d
+RG_TURISMO_TRX_5G_RX_HG_LNA_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18430;"	d
+RG_TURISMO_TRX_5G_RX_HG_SQDC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18459;"	d
+RG_TURISMO_TRX_5G_RX_HG_SQDC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18457;"	d
+RG_TURISMO_TRX_5G_RX_HG_SQDC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18456;"	d
+RG_TURISMO_TRX_5G_RX_HG_SQDC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18458;"	d
+RG_TURISMO_TRX_5G_RX_HG_SQDC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18460;"	d
+RG_TURISMO_TRX_5G_RX_HG_TZI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18474;"	d
+RG_TURISMO_TRX_5G_RX_HG_TZI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18472;"	d
+RG_TURISMO_TRX_5G_RX_HG_TZI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18471;"	d
+RG_TURISMO_TRX_5G_RX_HG_TZI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18473;"	d
+RG_TURISMO_TRX_5G_RX_HG_TZI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18475;"	d
+RG_TURISMO_TRX_5G_RX_HG_TZ_CAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18454;"	d
+RG_TURISMO_TRX_5G_RX_HG_TZ_CAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18452;"	d
+RG_TURISMO_TRX_5G_RX_HG_TZ_CAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18451;"	d
+RG_TURISMO_TRX_5G_RX_HG_TZ_CAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18453;"	d
+RG_TURISMO_TRX_5G_RX_HG_TZ_CAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18455;"	d
+RG_TURISMO_TRX_5G_RX_HG_TZ_GC_BOOST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18469;"	d
+RG_TURISMO_TRX_5G_RX_HG_TZ_GC_BOOST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18467;"	d
+RG_TURISMO_TRX_5G_RX_HG_TZ_GC_BOOST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18466;"	d
+RG_TURISMO_TRX_5G_RX_HG_TZ_GC_BOOST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18468;"	d
+RG_TURISMO_TRX_5G_RX_HG_TZ_GC_BOOST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18470;"	d
+RG_TURISMO_TRX_5G_RX_HG_TZ_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18434;"	d
+RG_TURISMO_TRX_5G_RX_HG_TZ_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18432;"	d
+RG_TURISMO_TRX_5G_RX_HG_TZ_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18431;"	d
+RG_TURISMO_TRX_5G_RX_HG_TZ_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18433;"	d
+RG_TURISMO_TRX_5G_RX_HG_TZ_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18435;"	d
+RG_TURISMO_TRX_5G_RX_HG_TZ_VCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18479;"	d
+RG_TURISMO_TRX_5G_RX_HG_TZ_VCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18477;"	d
+RG_TURISMO_TRX_5G_RX_HG_TZ_VCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18476;"	d
+RG_TURISMO_TRX_5G_RX_HG_TZ_VCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18478;"	d
+RG_TURISMO_TRX_5G_RX_HG_TZ_VCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18480;"	d
+RG_TURISMO_TRX_5G_RX_IQCAL_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19924;"	d
+RG_TURISMO_TRX_5G_RX_IQCAL_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19922;"	d
+RG_TURISMO_TRX_5G_RX_IQCAL_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19921;"	d
+RG_TURISMO_TRX_5G_RX_IQCAL_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19923;"	d
+RG_TURISMO_TRX_5G_RX_IQCAL_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19925;"	d
+RG_TURISMO_TRX_5G_RX_IQCAL_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18139;"	d
+RG_TURISMO_TRX_5G_RX_IQCAL_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18137;"	d
+RG_TURISMO_TRX_5G_RX_IQCAL_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18136;"	d
+RG_TURISMO_TRX_5G_RX_IQCAL_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18138;"	d
+RG_TURISMO_TRX_5G_RX_IQCAL_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18140;"	d
+RG_TURISMO_TRX_5G_RX_LG_DIV2_CORE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18574;"	d
+RG_TURISMO_TRX_5G_RX_LG_DIV2_CORE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18572;"	d
+RG_TURISMO_TRX_5G_RX_LG_DIV2_CORE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18571;"	d
+RG_TURISMO_TRX_5G_RX_LG_DIV2_CORE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18573;"	d
+RG_TURISMO_TRX_5G_RX_LG_DIV2_CORE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18575;"	d
+RG_TURISMO_TRX_5G_RX_LG_LNAHGN_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18549;"	d
+RG_TURISMO_TRX_5G_RX_LG_LNAHGN_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18547;"	d
+RG_TURISMO_TRX_5G_RX_LG_LNAHGN_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18546;"	d
+RG_TURISMO_TRX_5G_RX_LG_LNAHGN_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18548;"	d
+RG_TURISMO_TRX_5G_RX_LG_LNAHGN_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18550;"	d
+RG_TURISMO_TRX_5G_RX_LG_LNAHGP_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18554;"	d
+RG_TURISMO_TRX_5G_RX_LG_LNAHGP_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18552;"	d
+RG_TURISMO_TRX_5G_RX_LG_LNAHGP_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18551;"	d
+RG_TURISMO_TRX_5G_RX_LG_LNAHGP_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18553;"	d
+RG_TURISMO_TRX_5G_RX_LG_LNAHGP_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18555;"	d
+RG_TURISMO_TRX_5G_RX_LG_LNALG_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18559;"	d
+RG_TURISMO_TRX_5G_RX_LG_LNALG_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18557;"	d
+RG_TURISMO_TRX_5G_RX_LG_LNALG_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18556;"	d
+RG_TURISMO_TRX_5G_RX_LG_LNALG_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18558;"	d
+RG_TURISMO_TRX_5G_RX_LG_LNALG_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18560;"	d
+RG_TURISMO_TRX_5G_RX_LG_LNA_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18539;"	d
+RG_TURISMO_TRX_5G_RX_LG_LNA_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18537;"	d
+RG_TURISMO_TRX_5G_RX_LG_LNA_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18536;"	d
+RG_TURISMO_TRX_5G_RX_LG_LNA_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18538;"	d
+RG_TURISMO_TRX_5G_RX_LG_LNA_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18540;"	d
+RG_TURISMO_TRX_5G_RX_LG_SQDC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18569;"	d
+RG_TURISMO_TRX_5G_RX_LG_SQDC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18567;"	d
+RG_TURISMO_TRX_5G_RX_LG_SQDC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18566;"	d
+RG_TURISMO_TRX_5G_RX_LG_SQDC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18568;"	d
+RG_TURISMO_TRX_5G_RX_LG_SQDC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18570;"	d
+RG_TURISMO_TRX_5G_RX_LG_TZI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18584;"	d
+RG_TURISMO_TRX_5G_RX_LG_TZI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18582;"	d
+RG_TURISMO_TRX_5G_RX_LG_TZI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18581;"	d
+RG_TURISMO_TRX_5G_RX_LG_TZI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18583;"	d
+RG_TURISMO_TRX_5G_RX_LG_TZI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18585;"	d
+RG_TURISMO_TRX_5G_RX_LG_TZ_CAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18564;"	d
+RG_TURISMO_TRX_5G_RX_LG_TZ_CAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18562;"	d
+RG_TURISMO_TRX_5G_RX_LG_TZ_CAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18561;"	d
+RG_TURISMO_TRX_5G_RX_LG_TZ_CAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18563;"	d
+RG_TURISMO_TRX_5G_RX_LG_TZ_CAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18565;"	d
+RG_TURISMO_TRX_5G_RX_LG_TZ_GC_BOOST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18579;"	d
+RG_TURISMO_TRX_5G_RX_LG_TZ_GC_BOOST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18577;"	d
+RG_TURISMO_TRX_5G_RX_LG_TZ_GC_BOOST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18576;"	d
+RG_TURISMO_TRX_5G_RX_LG_TZ_GC_BOOST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18578;"	d
+RG_TURISMO_TRX_5G_RX_LG_TZ_GC_BOOST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18580;"	d
+RG_TURISMO_TRX_5G_RX_LG_TZ_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18544;"	d
+RG_TURISMO_TRX_5G_RX_LG_TZ_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18542;"	d
+RG_TURISMO_TRX_5G_RX_LG_TZ_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18541;"	d
+RG_TURISMO_TRX_5G_RX_LG_TZ_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18543;"	d
+RG_TURISMO_TRX_5G_RX_LG_TZ_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18545;"	d
+RG_TURISMO_TRX_5G_RX_LG_TZ_VCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18589;"	d
+RG_TURISMO_TRX_5G_RX_LG_TZ_VCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18587;"	d
+RG_TURISMO_TRX_5G_RX_LG_TZ_VCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18586;"	d
+RG_TURISMO_TRX_5G_RX_LG_TZ_VCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18588;"	d
+RG_TURISMO_TRX_5G_RX_LG_TZ_VCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18590;"	d
+RG_TURISMO_TRX_5G_RX_LNA_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18029;"	d
+RG_TURISMO_TRX_5G_RX_LNA_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18027;"	d
+RG_TURISMO_TRX_5G_RX_LNA_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18026;"	d
+RG_TURISMO_TRX_5G_RX_LNA_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18028;"	d
+RG_TURISMO_TRX_5G_RX_LNA_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18030;"	d
+RG_TURISMO_TRX_5G_RX_LNA_SETTLE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18249;"	d
+RG_TURISMO_TRX_5G_RX_LNA_SETTLE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18247;"	d
+RG_TURISMO_TRX_5G_RX_LNA_SETTLE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18246;"	d
+RG_TURISMO_TRX_5G_RX_LNA_SETTLE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18248;"	d
+RG_TURISMO_TRX_5G_RX_LNA_SETTLE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18250;"	d
+RG_TURISMO_TRX_5G_RX_LNA_TRI_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18244;"	d
+RG_TURISMO_TRX_5G_RX_LNA_TRI_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18242;"	d
+RG_TURISMO_TRX_5G_RX_LNA_TRI_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18241;"	d
+RG_TURISMO_TRX_5G_RX_LNA_TRI_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18243;"	d
+RG_TURISMO_TRX_5G_RX_LNA_TRI_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18245;"	d
+RG_TURISMO_TRX_5G_RX_LOBUF_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18059;"	d
+RG_TURISMO_TRX_5G_RX_LOBUF_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18057;"	d
+RG_TURISMO_TRX_5G_RX_LOBUF_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18056;"	d
+RG_TURISMO_TRX_5G_RX_LOBUF_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18058;"	d
+RG_TURISMO_TRX_5G_RX_LOBUF_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18060;"	d
+RG_TURISMO_TRX_5G_RX_MG_DIV2_CORE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18519;"	d
+RG_TURISMO_TRX_5G_RX_MG_DIV2_CORE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18517;"	d
+RG_TURISMO_TRX_5G_RX_MG_DIV2_CORE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18516;"	d
+RG_TURISMO_TRX_5G_RX_MG_DIV2_CORE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18518;"	d
+RG_TURISMO_TRX_5G_RX_MG_DIV2_CORE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18520;"	d
+RG_TURISMO_TRX_5G_RX_MG_LNAHGN_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18494;"	d
+RG_TURISMO_TRX_5G_RX_MG_LNAHGN_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18492;"	d
+RG_TURISMO_TRX_5G_RX_MG_LNAHGN_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18491;"	d
+RG_TURISMO_TRX_5G_RX_MG_LNAHGN_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18493;"	d
+RG_TURISMO_TRX_5G_RX_MG_LNAHGN_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18495;"	d
+RG_TURISMO_TRX_5G_RX_MG_LNAHGP_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18499;"	d
+RG_TURISMO_TRX_5G_RX_MG_LNAHGP_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18497;"	d
+RG_TURISMO_TRX_5G_RX_MG_LNAHGP_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18496;"	d
+RG_TURISMO_TRX_5G_RX_MG_LNAHGP_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18498;"	d
+RG_TURISMO_TRX_5G_RX_MG_LNAHGP_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18500;"	d
+RG_TURISMO_TRX_5G_RX_MG_LNALG_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18504;"	d
+RG_TURISMO_TRX_5G_RX_MG_LNALG_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18502;"	d
+RG_TURISMO_TRX_5G_RX_MG_LNALG_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18501;"	d
+RG_TURISMO_TRX_5G_RX_MG_LNALG_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18503;"	d
+RG_TURISMO_TRX_5G_RX_MG_LNALG_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18505;"	d
+RG_TURISMO_TRX_5G_RX_MG_LNA_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18484;"	d
+RG_TURISMO_TRX_5G_RX_MG_LNA_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18482;"	d
+RG_TURISMO_TRX_5G_RX_MG_LNA_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18481;"	d
+RG_TURISMO_TRX_5G_RX_MG_LNA_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18483;"	d
+RG_TURISMO_TRX_5G_RX_MG_LNA_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18485;"	d
+RG_TURISMO_TRX_5G_RX_MG_SQDC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18514;"	d
+RG_TURISMO_TRX_5G_RX_MG_SQDC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18512;"	d
+RG_TURISMO_TRX_5G_RX_MG_SQDC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18511;"	d
+RG_TURISMO_TRX_5G_RX_MG_SQDC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18513;"	d
+RG_TURISMO_TRX_5G_RX_MG_SQDC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18515;"	d
+RG_TURISMO_TRX_5G_RX_MG_TZI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18529;"	d
+RG_TURISMO_TRX_5G_RX_MG_TZI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18527;"	d
+RG_TURISMO_TRX_5G_RX_MG_TZI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18526;"	d
+RG_TURISMO_TRX_5G_RX_MG_TZI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18528;"	d
+RG_TURISMO_TRX_5G_RX_MG_TZI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18530;"	d
+RG_TURISMO_TRX_5G_RX_MG_TZ_CAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18509;"	d
+RG_TURISMO_TRX_5G_RX_MG_TZ_CAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18507;"	d
+RG_TURISMO_TRX_5G_RX_MG_TZ_CAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18506;"	d
+RG_TURISMO_TRX_5G_RX_MG_TZ_CAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18508;"	d
+RG_TURISMO_TRX_5G_RX_MG_TZ_CAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18510;"	d
+RG_TURISMO_TRX_5G_RX_MG_TZ_GC_BOOST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18524;"	d
+RG_TURISMO_TRX_5G_RX_MG_TZ_GC_BOOST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18522;"	d
+RG_TURISMO_TRX_5G_RX_MG_TZ_GC_BOOST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18521;"	d
+RG_TURISMO_TRX_5G_RX_MG_TZ_GC_BOOST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18523;"	d
+RG_TURISMO_TRX_5G_RX_MG_TZ_GC_BOOST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18525;"	d
+RG_TURISMO_TRX_5G_RX_MG_TZ_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18489;"	d
+RG_TURISMO_TRX_5G_RX_MG_TZ_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18487;"	d
+RG_TURISMO_TRX_5G_RX_MG_TZ_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18486;"	d
+RG_TURISMO_TRX_5G_RX_MG_TZ_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18488;"	d
+RG_TURISMO_TRX_5G_RX_MG_TZ_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18490;"	d
+RG_TURISMO_TRX_5G_RX_MG_TZ_VCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18534;"	d
+RG_TURISMO_TRX_5G_RX_MG_TZ_VCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18532;"	d
+RG_TURISMO_TRX_5G_RX_MG_TZ_VCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18531;"	d
+RG_TURISMO_TRX_5G_RX_MG_TZ_VCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18533;"	d
+RG_TURISMO_TRX_5G_RX_MG_TZ_VCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18535;"	d
+RG_TURISMO_TRX_5G_RX_MIXER_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18039;"	d
+RG_TURISMO_TRX_5G_RX_MIXER_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18037;"	d
+RG_TURISMO_TRX_5G_RX_MIXER_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18036;"	d
+RG_TURISMO_TRX_5G_RX_MIXER_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18038;"	d
+RG_TURISMO_TRX_5G_RX_MIXER_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18040;"	d
+RG_TURISMO_TRX_5G_RX_SCA_LOAD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18239;"	d
+RG_TURISMO_TRX_5G_RX_SCA_LOAD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18237;"	d
+RG_TURISMO_TRX_5G_RX_SCA_LOAD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18236;"	d
+RG_TURISMO_TRX_5G_RX_SCA_LOAD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18238;"	d
+RG_TURISMO_TRX_5G_RX_SCA_LOAD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18240;"	d
+RG_TURISMO_TRX_5G_RX_SCA_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18229;"	d
+RG_TURISMO_TRX_5G_RX_SCA_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18227;"	d
+RG_TURISMO_TRX_5G_RX_SCA_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18226;"	d
+RG_TURISMO_TRX_5G_RX_SCA_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18228;"	d
+RG_TURISMO_TRX_5G_RX_SCA_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18230;"	d
+RG_TURISMO_TRX_5G_RX_SCA_MA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18234;"	d
+RG_TURISMO_TRX_5G_RX_SCA_MA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18232;"	d
+RG_TURISMO_TRX_5G_RX_SCA_MA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18231;"	d
+RG_TURISMO_TRX_5G_RX_SCA_MA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18233;"	d
+RG_TURISMO_TRX_5G_RX_SCA_MA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18235;"	d
+RG_TURISMO_TRX_5G_RX_TZ_COURSE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18284;"	d
+RG_TURISMO_TRX_5G_RX_TZ_COURSE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18282;"	d
+RG_TURISMO_TRX_5G_RX_TZ_COURSE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18281;"	d
+RG_TURISMO_TRX_5G_RX_TZ_COURSE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18283;"	d
+RG_TURISMO_TRX_5G_RX_TZ_COURSE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18285;"	d
+RG_TURISMO_TRX_5G_RX_TZ_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18069;"	d
+RG_TURISMO_TRX_5G_RX_TZ_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18067;"	d
+RG_TURISMO_TRX_5G_RX_TZ_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18066;"	d
+RG_TURISMO_TRX_5G_RX_TZ_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18068;"	d
+RG_TURISMO_TRX_5G_RX_TZ_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18070;"	d
+RG_TURISMO_TRX_5G_RX_TZ_OUT_TRISTATE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18124;"	d
+RG_TURISMO_TRX_5G_RX_TZ_OUT_TRISTATE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18122;"	d
+RG_TURISMO_TRX_5G_RX_TZ_OUT_TRISTATE_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18119;"	d
+RG_TURISMO_TRX_5G_RX_TZ_OUT_TRISTATE_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18117;"	d
+RG_TURISMO_TRX_5G_RX_TZ_OUT_TRISTATE_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18116;"	d
+RG_TURISMO_TRX_5G_RX_TZ_OUT_TRISTATE_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18118;"	d
+RG_TURISMO_TRX_5G_RX_TZ_OUT_TRISTATE_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18120;"	d
+RG_TURISMO_TRX_5G_RX_TZ_OUT_TRISTATE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18121;"	d
+RG_TURISMO_TRX_5G_RX_TZ_OUT_TRISTATE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18123;"	d
+RG_TURISMO_TRX_5G_RX_TZ_OUT_TRISTATE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18125;"	d
+RG_TURISMO_TRX_5G_RX_ULG_DIV2_CORE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18629;"	d
+RG_TURISMO_TRX_5G_RX_ULG_DIV2_CORE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18627;"	d
+RG_TURISMO_TRX_5G_RX_ULG_DIV2_CORE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18626;"	d
+RG_TURISMO_TRX_5G_RX_ULG_DIV2_CORE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18628;"	d
+RG_TURISMO_TRX_5G_RX_ULG_DIV2_CORE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18630;"	d
+RG_TURISMO_TRX_5G_RX_ULG_LNAHGN_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18604;"	d
+RG_TURISMO_TRX_5G_RX_ULG_LNAHGN_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18602;"	d
+RG_TURISMO_TRX_5G_RX_ULG_LNAHGN_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18601;"	d
+RG_TURISMO_TRX_5G_RX_ULG_LNAHGN_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18603;"	d
+RG_TURISMO_TRX_5G_RX_ULG_LNAHGN_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18605;"	d
+RG_TURISMO_TRX_5G_RX_ULG_LNAHGP_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18609;"	d
+RG_TURISMO_TRX_5G_RX_ULG_LNAHGP_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18607;"	d
+RG_TURISMO_TRX_5G_RX_ULG_LNAHGP_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18606;"	d
+RG_TURISMO_TRX_5G_RX_ULG_LNAHGP_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18608;"	d
+RG_TURISMO_TRX_5G_RX_ULG_LNAHGP_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18610;"	d
+RG_TURISMO_TRX_5G_RX_ULG_LNALG_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18614;"	d
+RG_TURISMO_TRX_5G_RX_ULG_LNALG_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18612;"	d
+RG_TURISMO_TRX_5G_RX_ULG_LNALG_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18611;"	d
+RG_TURISMO_TRX_5G_RX_ULG_LNALG_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18613;"	d
+RG_TURISMO_TRX_5G_RX_ULG_LNALG_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18615;"	d
+RG_TURISMO_TRX_5G_RX_ULG_LNA_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18594;"	d
+RG_TURISMO_TRX_5G_RX_ULG_LNA_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18592;"	d
+RG_TURISMO_TRX_5G_RX_ULG_LNA_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18591;"	d
+RG_TURISMO_TRX_5G_RX_ULG_LNA_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18593;"	d
+RG_TURISMO_TRX_5G_RX_ULG_LNA_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18595;"	d
+RG_TURISMO_TRX_5G_RX_ULG_SQDC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18624;"	d
+RG_TURISMO_TRX_5G_RX_ULG_SQDC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18622;"	d
+RG_TURISMO_TRX_5G_RX_ULG_SQDC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18621;"	d
+RG_TURISMO_TRX_5G_RX_ULG_SQDC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18623;"	d
+RG_TURISMO_TRX_5G_RX_ULG_SQDC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18625;"	d
+RG_TURISMO_TRX_5G_RX_ULG_TZI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18639;"	d
+RG_TURISMO_TRX_5G_RX_ULG_TZI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18637;"	d
+RG_TURISMO_TRX_5G_RX_ULG_TZI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18636;"	d
+RG_TURISMO_TRX_5G_RX_ULG_TZI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18638;"	d
+RG_TURISMO_TRX_5G_RX_ULG_TZI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18640;"	d
+RG_TURISMO_TRX_5G_RX_ULG_TZ_CAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18619;"	d
+RG_TURISMO_TRX_5G_RX_ULG_TZ_CAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18617;"	d
+RG_TURISMO_TRX_5G_RX_ULG_TZ_CAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18616;"	d
+RG_TURISMO_TRX_5G_RX_ULG_TZ_CAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18618;"	d
+RG_TURISMO_TRX_5G_RX_ULG_TZ_CAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18620;"	d
+RG_TURISMO_TRX_5G_RX_ULG_TZ_GC_BOOST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18634;"	d
+RG_TURISMO_TRX_5G_RX_ULG_TZ_GC_BOOST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18632;"	d
+RG_TURISMO_TRX_5G_RX_ULG_TZ_GC_BOOST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18631;"	d
+RG_TURISMO_TRX_5G_RX_ULG_TZ_GC_BOOST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18633;"	d
+RG_TURISMO_TRX_5G_RX_ULG_TZ_GC_BOOST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18635;"	d
+RG_TURISMO_TRX_5G_RX_ULG_TZ_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18599;"	d
+RG_TURISMO_TRX_5G_RX_ULG_TZ_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18597;"	d
+RG_TURISMO_TRX_5G_RX_ULG_TZ_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18596;"	d
+RG_TURISMO_TRX_5G_RX_ULG_TZ_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18598;"	d
+RG_TURISMO_TRX_5G_RX_ULG_TZ_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18600;"	d
+RG_TURISMO_TRX_5G_RX_ULG_TZ_VCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18644;"	d
+RG_TURISMO_TRX_5G_RX_ULG_TZ_VCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18642;"	d
+RG_TURISMO_TRX_5G_RX_ULG_TZ_VCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18641;"	d
+RG_TURISMO_TRX_5G_RX_ULG_TZ_VCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18643;"	d
+RG_TURISMO_TRX_5G_RX_ULG_TZ_VCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18645;"	d
+RG_TURISMO_TRX_5G_TXDAC_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19849;"	d
+RG_TURISMO_TRX_5G_TXDAC_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19847;"	d
+RG_TURISMO_TRX_5G_TXDAC_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19846;"	d
+RG_TURISMO_TRX_5G_TXDAC_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19848;"	d
+RG_TURISMO_TRX_5G_TXDAC_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19850;"	d
+RG_TURISMO_TRX_5G_TXDAC_R2T_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19889;"	d
+RG_TURISMO_TRX_5G_TXDAC_R2T_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19887;"	d
+RG_TURISMO_TRX_5G_TXDAC_R2T_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19886;"	d
+RG_TURISMO_TRX_5G_TXDAC_R2T_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19888;"	d
+RG_TURISMO_TRX_5G_TXDAC_R2T_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19890;"	d
+RG_TURISMO_TRX_5G_TXDAC_T2R_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19869;"	d
+RG_TURISMO_TRX_5G_TXDAC_T2R_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19867;"	d
+RG_TURISMO_TRX_5G_TXDAC_T2R_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19866;"	d
+RG_TURISMO_TRX_5G_TXDAC_T2R_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19868;"	d
+RG_TURISMO_TRX_5G_TXDAC_T2R_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19870;"	d
+RG_TURISMO_TRX_5G_TXLPF_BOOSTI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18679;"	d
+RG_TURISMO_TRX_5G_TXLPF_BOOSTI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18677;"	d
+RG_TURISMO_TRX_5G_TXLPF_BOOSTI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18676;"	d
+RG_TURISMO_TRX_5G_TXLPF_BOOSTI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18678;"	d
+RG_TURISMO_TRX_5G_TXLPF_BOOSTI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18680;"	d
+RG_TURISMO_TRX_5G_TXMOD_GMCELL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18414;"	d
+RG_TURISMO_TRX_5G_TXMOD_GMCELL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18412;"	d
+RG_TURISMO_TRX_5G_TXMOD_GMCELL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18411;"	d
+RG_TURISMO_TRX_5G_TXMOD_GMCELL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18413;"	d
+RG_TURISMO_TRX_5G_TXMOD_GMCELL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18415;"	d
+RG_TURISMO_TRX_5G_TXPA_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19859;"	d
+RG_TURISMO_TRX_5G_TXPA_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19857;"	d
+RG_TURISMO_TRX_5G_TXPA_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19856;"	d
+RG_TURISMO_TRX_5G_TXPA_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19858;"	d
+RG_TURISMO_TRX_5G_TXPA_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19860;"	d
+RG_TURISMO_TRX_5G_TXPA_R2T_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19899;"	d
+RG_TURISMO_TRX_5G_TXPA_R2T_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19897;"	d
+RG_TURISMO_TRX_5G_TXPA_R2T_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19896;"	d
+RG_TURISMO_TRX_5G_TXPA_R2T_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19898;"	d
+RG_TURISMO_TRX_5G_TXPA_R2T_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19900;"	d
+RG_TURISMO_TRX_5G_TXPA_T2R_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19879;"	d
+RG_TURISMO_TRX_5G_TXPA_T2R_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19877;"	d
+RG_TURISMO_TRX_5G_TXPA_T2R_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19876;"	d
+RG_TURISMO_TRX_5G_TXPA_T2R_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19878;"	d
+RG_TURISMO_TRX_5G_TXPA_T2R_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19880;"	d
+RG_TURISMO_TRX_5G_TXPGA_CAPSW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18339;"	d
+RG_TURISMO_TRX_5G_TXPGA_CAPSW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18337;"	d
+RG_TURISMO_TRX_5G_TXPGA_CAPSW_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18334;"	d
+RG_TURISMO_TRX_5G_TXPGA_CAPSW_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18332;"	d
+RG_TURISMO_TRX_5G_TXPGA_CAPSW_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18331;"	d
+RG_TURISMO_TRX_5G_TXPGA_CAPSW_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18333;"	d
+RG_TURISMO_TRX_5G_TXPGA_CAPSW_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18335;"	d
+RG_TURISMO_TRX_5G_TXPGA_CAPSW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18336;"	d
+RG_TURISMO_TRX_5G_TXPGA_CAPSW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18338;"	d
+RG_TURISMO_TRX_5G_TXPGA_CAPSW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18340;"	d
+RG_TURISMO_TRX_5G_TXPGA_MAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18404;"	d
+RG_TURISMO_TRX_5G_TXPGA_MAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18402;"	d
+RG_TURISMO_TRX_5G_TXPGA_MAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18401;"	d
+RG_TURISMO_TRX_5G_TXPGA_MAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18403;"	d
+RG_TURISMO_TRX_5G_TXPGA_MAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18405;"	d
+RG_TURISMO_TRX_5G_TXPGA_STEER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18409;"	d
+RG_TURISMO_TRX_5G_TXPGA_STEER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18407;"	d
+RG_TURISMO_TRX_5G_TXPGA_STEER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18406;"	d
+RG_TURISMO_TRX_5G_TXPGA_STEER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18408;"	d
+RG_TURISMO_TRX_5G_TXPGA_STEER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18410;"	d
+RG_TURISMO_TRX_5G_TXRF_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19854;"	d
+RG_TURISMO_TRX_5G_TXRF_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19852;"	d
+RG_TURISMO_TRX_5G_TXRF_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19851;"	d
+RG_TURISMO_TRX_5G_TXRF_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19853;"	d
+RG_TURISMO_TRX_5G_TXRF_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19855;"	d
+RG_TURISMO_TRX_5G_TXRF_R2T_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19894;"	d
+RG_TURISMO_TRX_5G_TXRF_R2T_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19892;"	d
+RG_TURISMO_TRX_5G_TXRF_R2T_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19891;"	d
+RG_TURISMO_TRX_5G_TXRF_R2T_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19893;"	d
+RG_TURISMO_TRX_5G_TXRF_R2T_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19895;"	d
+RG_TURISMO_TRX_5G_TXRF_T2R_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19874;"	d
+RG_TURISMO_TRX_5G_TXRF_T2R_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19872;"	d
+RG_TURISMO_TRX_5G_TXRF_T2R_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19871;"	d
+RG_TURISMO_TRX_5G_TXRF_T2R_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19873;"	d
+RG_TURISMO_TRX_5G_TXRF_T2R_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19875;"	d
+RG_TURISMO_TRX_5G_TX_ADDGMCELL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18344;"	d
+RG_TURISMO_TRX_5G_TX_ADDGMCELL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18342;"	d
+RG_TURISMO_TRX_5G_TX_ADDGMCELL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18341;"	d
+RG_TURISMO_TRX_5G_TX_ADDGMCELL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18343;"	d
+RG_TURISMO_TRX_5G_TX_ADDGMCELL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18345;"	d
+RG_TURISMO_TRX_5G_TX_DACI1ST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18649;"	d
+RG_TURISMO_TRX_5G_TX_DACI1ST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18647;"	d
+RG_TURISMO_TRX_5G_TX_DACI1ST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18646;"	d
+RG_TURISMO_TRX_5G_TX_DACI1ST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18648;"	d
+RG_TURISMO_TRX_5G_TX_DACI1ST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18650;"	d
+RG_TURISMO_TRX_5G_TX_DACLPF_ICOARSE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18654;"	d
+RG_TURISMO_TRX_5G_TX_DACLPF_ICOARSE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18652;"	d
+RG_TURISMO_TRX_5G_TX_DACLPF_ICOARSE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18651;"	d
+RG_TURISMO_TRX_5G_TX_DACLPF_ICOARSE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18653;"	d
+RG_TURISMO_TRX_5G_TX_DACLPF_ICOARSE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18655;"	d
+RG_TURISMO_TRX_5G_TX_DACLPF_IFINE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18659;"	d
+RG_TURISMO_TRX_5G_TX_DACLPF_IFINE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18657;"	d
+RG_TURISMO_TRX_5G_TX_DACLPF_IFINE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18656;"	d
+RG_TURISMO_TRX_5G_TX_DACLPF_IFINE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18658;"	d
+RG_TURISMO_TRX_5G_TX_DACLPF_IFINE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18660;"	d
+RG_TURISMO_TRX_5G_TX_DACLPF_VCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18664;"	d
+RG_TURISMO_TRX_5G_TX_DACLPF_VCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18662;"	d
+RG_TURISMO_TRX_5G_TX_DACLPF_VCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18661;"	d
+RG_TURISMO_TRX_5G_TX_DACLPF_VCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18663;"	d
+RG_TURISMO_TRX_5G_TX_DACLPF_VCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18665;"	d
+RG_TURISMO_TRX_5G_TX_DAC_CKEDGE_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18689;"	d
+RG_TURISMO_TRX_5G_TX_DAC_CKEDGE_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18687;"	d
+RG_TURISMO_TRX_5G_TX_DAC_CKEDGE_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18686;"	d
+RG_TURISMO_TRX_5G_TX_DAC_CKEDGE_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18688;"	d
+RG_TURISMO_TRX_5G_TX_DAC_CKEDGE_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18690;"	d
+RG_TURISMO_TRX_5G_TX_DAC_IATTN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18674;"	d
+RG_TURISMO_TRX_5G_TX_DAC_IATTN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18672;"	d
+RG_TURISMO_TRX_5G_TX_DAC_IATTN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18671;"	d
+RG_TURISMO_TRX_5G_TX_DAC_IATTN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18673;"	d
+RG_TURISMO_TRX_5G_TX_DAC_IATTN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18675;"	d
+RG_TURISMO_TRX_5G_TX_DAC_IBIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18669;"	d
+RG_TURISMO_TRX_5G_TX_DAC_IBIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18667;"	d
+RG_TURISMO_TRX_5G_TX_DAC_IBIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18666;"	d
+RG_TURISMO_TRX_5G_TX_DAC_IBIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18668;"	d
+RG_TURISMO_TRX_5G_TX_DAC_IBIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18670;"	d
+RG_TURISMO_TRX_5G_TX_DAC_IOFFSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18699;"	d
+RG_TURISMO_TRX_5G_TX_DAC_IOFFSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18697;"	d
+RG_TURISMO_TRX_5G_TX_DAC_IOFFSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18696;"	d
+RG_TURISMO_TRX_5G_TX_DAC_IOFFSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18698;"	d
+RG_TURISMO_TRX_5G_TX_DAC_IOFFSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18700;"	d
+RG_TURISMO_TRX_5G_TX_DAC_OS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18694;"	d
+RG_TURISMO_TRX_5G_TX_DAC_OS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18692;"	d
+RG_TURISMO_TRX_5G_TX_DAC_OS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18691;"	d
+RG_TURISMO_TRX_5G_TX_DAC_OS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18693;"	d
+RG_TURISMO_TRX_5G_TX_DAC_OS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18695;"	d
+RG_TURISMO_TRX_5G_TX_DAC_QOFFSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18704;"	d
+RG_TURISMO_TRX_5G_TX_DAC_QOFFSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18702;"	d
+RG_TURISMO_TRX_5G_TX_DAC_QOFFSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18701;"	d
+RG_TURISMO_TRX_5G_TX_DAC_QOFFSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18703;"	d
+RG_TURISMO_TRX_5G_TX_DAC_QOFFSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18705;"	d
+RG_TURISMO_TRX_5G_TX_DAC_RCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18684;"	d
+RG_TURISMO_TRX_5G_TX_DAC_RCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18682;"	d
+RG_TURISMO_TRX_5G_TX_DAC_RCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18681;"	d
+RG_TURISMO_TRX_5G_TX_DAC_RCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18683;"	d
+RG_TURISMO_TRX_5G_TX_DAC_RCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18685;"	d
+RG_TURISMO_TRX_5G_TX_DCCAL_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19914;"	d
+RG_TURISMO_TRX_5G_TX_DCCAL_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19912;"	d
+RG_TURISMO_TRX_5G_TX_DCCAL_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19911;"	d
+RG_TURISMO_TRX_5G_TX_DCCAL_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19913;"	d
+RG_TURISMO_TRX_5G_TX_DCCAL_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19915;"	d
+RG_TURISMO_TRX_5G_TX_DIV2_BUF_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18109;"	d
+RG_TURISMO_TRX_5G_TX_DIV2_BUF_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18107;"	d
+RG_TURISMO_TRX_5G_TX_DIV2_BUF_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18106;"	d
+RG_TURISMO_TRX_5G_TX_DIV2_BUF_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18108;"	d
+RG_TURISMO_TRX_5G_TX_DIV2_BUF_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18110;"	d
+RG_TURISMO_TRX_5G_TX_DIV2_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18099;"	d
+RG_TURISMO_TRX_5G_TX_DIV2_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18097;"	d
+RG_TURISMO_TRX_5G_TX_DIV2_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18096;"	d
+RG_TURISMO_TRX_5G_TX_DIV2_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18098;"	d
+RG_TURISMO_TRX_5G_TX_DIV2_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18100;"	d
+RG_TURISMO_TRX_5G_TX_DIV_CMLISEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18384;"	d
+RG_TURISMO_TRX_5G_TX_DIV_CMLISEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18382;"	d
+RG_TURISMO_TRX_5G_TX_DIV_CMLISEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18381;"	d
+RG_TURISMO_TRX_5G_TX_DIV_CMLISEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18383;"	d
+RG_TURISMO_TRX_5G_TX_DIV_CMLISEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18385;"	d
+RG_TURISMO_TRX_5G_TX_DIV_CMLVSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18389;"	d
+RG_TURISMO_TRX_5G_TX_DIV_CMLVSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18387;"	d
+RG_TURISMO_TRX_5G_TX_DIV_CMLVSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18386;"	d
+RG_TURISMO_TRX_5G_TX_DIV_CMLVSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18388;"	d
+RG_TURISMO_TRX_5G_TX_DIV_CMLVSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18390;"	d
+RG_TURISMO_TRX_5G_TX_DIV_PREBUFS2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18379;"	d
+RG_TURISMO_TRX_5G_TX_DIV_PREBUFS2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18377;"	d
+RG_TURISMO_TRX_5G_TX_DIV_PREBUFS2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18376;"	d
+RG_TURISMO_TRX_5G_TX_DIV_PREBUFS2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18378;"	d
+RG_TURISMO_TRX_5G_TX_DIV_PREBUFS2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18380;"	d
+RG_TURISMO_TRX_5G_TX_DIV_VSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18394;"	d
+RG_TURISMO_TRX_5G_TX_DIV_VSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18392;"	d
+RG_TURISMO_TRX_5G_TX_DIV_VSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18391;"	d
+RG_TURISMO_TRX_5G_TX_DIV_VSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18393;"	d
+RG_TURISMO_TRX_5G_TX_DIV_VSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18395;"	d
+RG_TURISMO_TRX_5G_TX_DPDGM_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18289;"	d
+RG_TURISMO_TRX_5G_TX_DPDGM_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18287;"	d
+RG_TURISMO_TRX_5G_TX_DPDGM_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18286;"	d
+RG_TURISMO_TRX_5G_TX_DPDGM_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18288;"	d
+RG_TURISMO_TRX_5G_TX_DPDGM_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18290;"	d
+RG_TURISMO_TRX_5G_TX_DPD_DIV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18294;"	d
+RG_TURISMO_TRX_5G_TX_DPD_DIV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18292;"	d
+RG_TURISMO_TRX_5G_TX_DPD_DIV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18291;"	d
+RG_TURISMO_TRX_5G_TX_DPD_DIV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18293;"	d
+RG_TURISMO_TRX_5G_TX_DPD_DIV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18295;"	d
+RG_TURISMO_TRX_5G_TX_DPD_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18149;"	d
+RG_TURISMO_TRX_5G_TX_DPD_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18147;"	d
+RG_TURISMO_TRX_5G_TX_DPD_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18146;"	d
+RG_TURISMO_TRX_5G_TX_DPD_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18148;"	d
+RG_TURISMO_TRX_5G_TX_DPD_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18150;"	d
+RG_TURISMO_TRX_5G_TX_GAIN_DPDCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19969;"	d
+RG_TURISMO_TRX_5G_TX_GAIN_DPDCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19967;"	d
+RG_TURISMO_TRX_5G_TX_GAIN_DPDCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19966;"	d
+RG_TURISMO_TRX_5G_TX_GAIN_DPDCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19968;"	d
+RG_TURISMO_TRX_5G_TX_GAIN_DPDCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19970;"	d
+RG_TURISMO_TRX_5G_TX_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18424;"	d
+RG_TURISMO_TRX_5G_TX_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18422;"	d
+RG_TURISMO_TRX_5G_TX_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18421;"	d
+RG_TURISMO_TRX_5G_TX_GAIN_OFFSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18419;"	d
+RG_TURISMO_TRX_5G_TX_GAIN_OFFSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18417;"	d
+RG_TURISMO_TRX_5G_TX_GAIN_OFFSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18416;"	d
+RG_TURISMO_TRX_5G_TX_GAIN_OFFSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18418;"	d
+RG_TURISMO_TRX_5G_TX_GAIN_OFFSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18420;"	d
+RG_TURISMO_TRX_5G_TX_GAIN_RXIQCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19954;"	d
+RG_TURISMO_TRX_5G_TX_GAIN_RXIQCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19952;"	d
+RG_TURISMO_TRX_5G_TX_GAIN_RXIQCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19951;"	d
+RG_TURISMO_TRX_5G_TX_GAIN_RXIQCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19953;"	d
+RG_TURISMO_TRX_5G_TX_GAIN_RXIQCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19955;"	d
+RG_TURISMO_TRX_5G_TX_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18423;"	d
+RG_TURISMO_TRX_5G_TX_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18425;"	d
+RG_TURISMO_TRX_5G_TX_GAIN_TXCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19934;"	d
+RG_TURISMO_TRX_5G_TX_GAIN_TXCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19932;"	d
+RG_TURISMO_TRX_5G_TX_GAIN_TXCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19931;"	d
+RG_TURISMO_TRX_5G_TX_GAIN_TXCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19933;"	d
+RG_TURISMO_TRX_5G_TX_GAIN_TXCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19935;"	d
+RG_TURISMO_TRX_5G_TX_IQCAL_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19919;"	d
+RG_TURISMO_TRX_5G_TX_IQCAL_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19917;"	d
+RG_TURISMO_TRX_5G_TX_IQCAL_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19916;"	d
+RG_TURISMO_TRX_5G_TX_IQCAL_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19918;"	d
+RG_TURISMO_TRX_5G_TX_IQCAL_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19920;"	d
+RG_TURISMO_TRX_5G_TX_LOBUF_VSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18399;"	d
+RG_TURISMO_TRX_5G_TX_LOBUF_VSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18397;"	d
+RG_TURISMO_TRX_5G_TX_LOBUF_VSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18396;"	d
+RG_TURISMO_TRX_5G_TX_LOBUF_VSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18398;"	d
+RG_TURISMO_TRX_5G_TX_LOBUF_VSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18400;"	d
+RG_TURISMO_TRX_5G_TX_MOD_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18089;"	d
+RG_TURISMO_TRX_5G_TX_MOD_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18087;"	d
+RG_TURISMO_TRX_5G_TX_MOD_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18086;"	d
+RG_TURISMO_TRX_5G_TX_MOD_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18088;"	d
+RG_TURISMO_TRX_5G_TX_MOD_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18090;"	d
+RG_TURISMO_TRX_5G_TX_PA1_VCAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18364;"	d
+RG_TURISMO_TRX_5G_TX_PA1_VCAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18362;"	d
+RG_TURISMO_TRX_5G_TX_PA1_VCAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18361;"	d
+RG_TURISMO_TRX_5G_TX_PA1_VCAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18363;"	d
+RG_TURISMO_TRX_5G_TX_PA1_VCAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18365;"	d
+RG_TURISMO_TRX_5G_TX_PA2_VCAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18369;"	d
+RG_TURISMO_TRX_5G_TX_PA2_VCAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18367;"	d
+RG_TURISMO_TRX_5G_TX_PA2_VCAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18366;"	d
+RG_TURISMO_TRX_5G_TX_PA2_VCAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18368;"	d
+RG_TURISMO_TRX_5G_TX_PA2_VCAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18370;"	d
+RG_TURISMO_TRX_5G_TX_PA3_VCAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18374;"	d
+RG_TURISMO_TRX_5G_TX_PA3_VCAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18372;"	d
+RG_TURISMO_TRX_5G_TX_PA3_VCAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18371;"	d
+RG_TURISMO_TRX_5G_TX_PA3_VCAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18373;"	d
+RG_TURISMO_TRX_5G_TX_PA3_VCAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18375;"	d
+RG_TURISMO_TRX_5G_TX_PAFB_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18359;"	d
+RG_TURISMO_TRX_5G_TX_PAFB_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18357;"	d
+RG_TURISMO_TRX_5G_TX_PAFB_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18356;"	d
+RG_TURISMO_TRX_5G_TX_PAFB_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18358;"	d
+RG_TURISMO_TRX_5G_TX_PAFB_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18360;"	d
+RG_TURISMO_TRX_5G_TX_PA_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18079;"	d
+RG_TURISMO_TRX_5G_TX_PA_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18077;"	d
+RG_TURISMO_TRX_5G_TX_PA_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18076;"	d
+RG_TURISMO_TRX_5G_TX_PA_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18078;"	d
+RG_TURISMO_TRX_5G_TX_PA_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18080;"	d
+RG_TURISMO_TRX_5G_TX_SELF_MIXER_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18129;"	d
+RG_TURISMO_TRX_5G_TX_SELF_MIXER_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18127;"	d
+RG_TURISMO_TRX_5G_TX_SELF_MIXER_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18126;"	d
+RG_TURISMO_TRX_5G_TX_SELF_MIXER_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18128;"	d
+RG_TURISMO_TRX_5G_TX_SELF_MIXER_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18130;"	d
+RG_TURISMO_TRX_5G_TX_TRSW_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18019;"	d
+RG_TURISMO_TRX_5G_TX_TRSW_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18017;"	d
+RG_TURISMO_TRX_5G_TX_TRSW_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18016;"	d
+RG_TURISMO_TRX_5G_TX_TRSW_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18018;"	d
+RG_TURISMO_TRX_5G_TX_TRSW_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18020;"	d
+RG_TURISMO_TRX_5G_TX_TSSI_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18299;"	d
+RG_TURISMO_TRX_5G_TX_TSSI_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18297;"	d
+RG_TURISMO_TRX_5G_TX_TSSI_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18296;"	d
+RG_TURISMO_TRX_5G_TX_TSSI_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18298;"	d
+RG_TURISMO_TRX_5G_TX_TSSI_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18300;"	d
+RG_TURISMO_TRX_5G_TX_TSSI_DIV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18304;"	d
+RG_TURISMO_TRX_5G_TX_TSSI_DIV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18302;"	d
+RG_TURISMO_TRX_5G_TX_TSSI_DIV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18301;"	d
+RG_TURISMO_TRX_5G_TX_TSSI_DIV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18303;"	d
+RG_TURISMO_TRX_5G_TX_TSSI_DIV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18305;"	d
+RG_TURISMO_TRX_5G_TX_TSSI_TESTMODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18314;"	d
+RG_TURISMO_TRX_5G_TX_TSSI_TESTMODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18312;"	d
+RG_TURISMO_TRX_5G_TX_TSSI_TESTMODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18311;"	d
+RG_TURISMO_TRX_5G_TX_TSSI_TESTMODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18313;"	d
+RG_TURISMO_TRX_5G_TX_TSSI_TESTMODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18315;"	d
+RG_TURISMO_TRX_5G_TX_TSSI_TEST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18309;"	d
+RG_TURISMO_TRX_5G_TX_TSSI_TEST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18307;"	d
+RG_TURISMO_TRX_5G_TX_TSSI_TEST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18306;"	d
+RG_TURISMO_TRX_5G_TX_TSSI_TEST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18308;"	d
+RG_TURISMO_TRX_5G_TX_TSSI_TEST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18310;"	d
+RG_TURISMO_TRX_AAC5GB_PDSW_EN_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19364;"	d
+RG_TURISMO_TRX_AAC5GB_PDSW_EN_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19362;"	d
+RG_TURISMO_TRX_AAC5GB_PDSW_EN_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19361;"	d
+RG_TURISMO_TRX_AAC5GB_PDSW_EN_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19363;"	d
+RG_TURISMO_TRX_AAC5GB_PDSW_EN_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19365;"	d
+RG_TURISMO_TRX_AAC5GB_TAR_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19359;"	d
+RG_TURISMO_TRX_AAC5GB_TAR_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19357;"	d
+RG_TURISMO_TRX_AAC5GB_TAR_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19356;"	d
+RG_TURISMO_TRX_AAC5GB_TAR_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19358;"	d
+RG_TURISMO_TRX_AAC5GB_TAR_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19360;"	d
+RG_TURISMO_TRX_ADC_EDGE_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20209;"	d
+RG_TURISMO_TRX_ADC_EDGE_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20207;"	d
+RG_TURISMO_TRX_ADC_EDGE_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20206;"	d
+RG_TURISMO_TRX_ADC_EDGE_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20208;"	d
+RG_TURISMO_TRX_ADC_EDGE_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20210;"	d
+RG_TURISMO_TRX_ALPHA_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20404;"	d
+RG_TURISMO_TRX_ALPHA_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20402;"	d
+RG_TURISMO_TRX_ALPHA_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20401;"	d
+RG_TURISMO_TRX_ALPHA_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20403;"	d
+RG_TURISMO_TRX_ALPHA_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20405;"	d
+RG_TURISMO_TRX_BB_SIG_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20269;"	d
+RG_TURISMO_TRX_BB_SIG_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20267;"	d
+RG_TURISMO_TRX_BB_SIG_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20266;"	d
+RG_TURISMO_TRX_BB_SIG_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20268;"	d
+RG_TURISMO_TRX_BB_SIG_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20270;"	d
+RG_TURISMO_TRX_BT_CLK32K_CAL_DONE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21039;"	d
+RG_TURISMO_TRX_BT_CLK32K_CAL_DONE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21037;"	d
+RG_TURISMO_TRX_BT_CLK32K_CAL_DONE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21036;"	d
+RG_TURISMO_TRX_BT_CLK32K_CAL_DONE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21038;"	d
+RG_TURISMO_TRX_BT_CLK32K_CAL_DONE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21040;"	d
+RG_TURISMO_TRX_BT_CLK_SW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21034;"	d
+RG_TURISMO_TRX_BT_CLK_SW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21032;"	d
+RG_TURISMO_TRX_BT_CLK_SW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21031;"	d
+RG_TURISMO_TRX_BT_CLK_SW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21033;"	d
+RG_TURISMO_TRX_BT_CLK_SW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21035;"	d
+RG_TURISMO_TRX_BT_EN_TX_PA_VIN33_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15354;"	d
+RG_TURISMO_TRX_BT_EN_TX_PA_VIN33_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15352;"	d
+RG_TURISMO_TRX_BT_EN_TX_PA_VIN33_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15351;"	d
+RG_TURISMO_TRX_BT_EN_TX_PA_VIN33_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15353;"	d
+RG_TURISMO_TRX_BT_EN_TX_PA_VIN33_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15355;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17589;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17587;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17586;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17588;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17590;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG10_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17489;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG10_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17487;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG10_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17486;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG10_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17488;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG10_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17490;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG11_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17479;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG11_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17477;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG11_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17476;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG11_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17478;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG11_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17480;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG12_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17469;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG12_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17467;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG12_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17466;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG12_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17468;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG12_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17470;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG13_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17459;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG13_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17457;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG13_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17456;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG13_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17458;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG13_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17460;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG14_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17449;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG14_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17447;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG14_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17446;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG14_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17448;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG14_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17450;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG15_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17439;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG15_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17437;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG15_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17436;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG15_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17438;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG15_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17440;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17579;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17577;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17576;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17578;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17580;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17569;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17567;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17566;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17568;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17570;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17559;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17557;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17556;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17558;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17560;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17549;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17547;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17546;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17548;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17550;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17539;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17537;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17536;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17538;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17540;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17529;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17527;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17526;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17528;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17530;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17519;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17517;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17516;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17518;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17520;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG8_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17509;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG8_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17507;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG8_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17506;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG8_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17508;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG8_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17510;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG9_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17499;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG9_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17497;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG9_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17496;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG9_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17498;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG9_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17500;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17749;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17747;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17746;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17748;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17750;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG10_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17649;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG10_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17647;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG10_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17646;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG10_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17648;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG10_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17650;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG11_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17639;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG11_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17637;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG11_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17636;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG11_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17638;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG11_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17640;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG12_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17629;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG12_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17627;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG12_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17626;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG12_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17628;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG12_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17630;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG13_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17619;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG13_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17617;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG13_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17616;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG13_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17618;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG13_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17620;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG14_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17609;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG14_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17607;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG14_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17606;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG14_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17608;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG14_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17610;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG15_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17599;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG15_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17597;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG15_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17596;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG15_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17598;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG15_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17600;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17739;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17737;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17736;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17738;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17740;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17729;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17727;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17726;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17728;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17730;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17719;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17717;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17716;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17718;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17720;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17709;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17707;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17706;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17708;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17710;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17699;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17697;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17696;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17698;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17700;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17689;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17687;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17686;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17688;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17690;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17679;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17677;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17676;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17678;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17680;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG8_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17669;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG8_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17667;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG8_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17666;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG8_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17668;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG8_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17670;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG9_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17659;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG9_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17657;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG9_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17656;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG9_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17658;"	d
+RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG9_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17660;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17594;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17592;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17591;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17593;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17595;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG10_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17494;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG10_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17492;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG10_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17491;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG10_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17493;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG10_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17495;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG11_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17484;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG11_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17482;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG11_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17481;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG11_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17483;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG11_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17485;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG12_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17474;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG12_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17472;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG12_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17471;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG12_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17473;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG12_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17475;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG13_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17464;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG13_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17462;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG13_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17461;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG13_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17463;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG13_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17465;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG14_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17454;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG14_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17452;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG14_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17451;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG14_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17453;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG14_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17455;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG15_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17444;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG15_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17442;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG15_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17441;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG15_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17443;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG15_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17445;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17584;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17582;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17581;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17583;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17585;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17574;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17572;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17571;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17573;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17575;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17564;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17562;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17561;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17563;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17565;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17554;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17552;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17551;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17553;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17555;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17544;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17542;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17541;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17543;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17545;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17534;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17532;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17531;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17533;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17535;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17524;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17522;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17521;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17523;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17525;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG8_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17514;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG8_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17512;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG8_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17511;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG8_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17513;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG8_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17515;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG9_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17504;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG9_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17502;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG9_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17501;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG9_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17503;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG9_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17505;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17754;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17752;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17751;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17753;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17755;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG10_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17654;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG10_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17652;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG10_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17651;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG10_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17653;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG10_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17655;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG11_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17644;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG11_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17642;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG11_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17641;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG11_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17643;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG11_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17645;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG12_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17634;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG12_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17632;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG12_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17631;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG12_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17633;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG12_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17635;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG13_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17624;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG13_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17622;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG13_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17621;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG13_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17623;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG13_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17625;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG14_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17614;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG14_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17612;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG14_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17611;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG14_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17613;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG14_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17615;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG15_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17604;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG15_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17602;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG15_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17601;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG15_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17603;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG15_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17605;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17744;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17742;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17741;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17743;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17745;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17734;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17732;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17731;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17733;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17735;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17724;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17722;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17721;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17723;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17725;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17714;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17712;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17711;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17713;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17715;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17704;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17702;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17701;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17703;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17705;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17694;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17692;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17691;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17693;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17695;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17684;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17682;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17681;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17683;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17685;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG8_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17674;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG8_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17672;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG8_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17671;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG8_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17673;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG8_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17675;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG9_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17664;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG9_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17662;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG9_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17661;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG9_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17663;"	d
+RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG9_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17665;"	d
+RG_TURISMO_TRX_BT_PABIAS_2X_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15409;"	d
+RG_TURISMO_TRX_BT_PABIAS_2X_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15407;"	d
+RG_TURISMO_TRX_BT_PABIAS_2X_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15406;"	d
+RG_TURISMO_TRX_BT_PABIAS_2X_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15408;"	d
+RG_TURISMO_TRX_BT_PABIAS_2X_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15410;"	d
+RG_TURISMO_TRX_BT_PABIAS_CTRL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15414;"	d
+RG_TURISMO_TRX_BT_PABIAS_CTRL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15412;"	d
+RG_TURISMO_TRX_BT_PABIAS_CTRL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15411;"	d
+RG_TURISMO_TRX_BT_PABIAS_CTRL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15413;"	d
+RG_TURISMO_TRX_BT_PABIAS_CTRL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15415;"	d
+RG_TURISMO_TRX_BT_RX_ABBCFIX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15199;"	d
+RG_TURISMO_TRX_BT_RX_ABBCFIX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15197;"	d
+RG_TURISMO_TRX_BT_RX_ABBCFIX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15196;"	d
+RG_TURISMO_TRX_BT_RX_ABBCFIX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15198;"	d
+RG_TURISMO_TRX_BT_RX_ABBCFIX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15200;"	d
+RG_TURISMO_TRX_BT_RX_ABBCTUNE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15174;"	d
+RG_TURISMO_TRX_BT_RX_ABBCTUNE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15172;"	d
+RG_TURISMO_TRX_BT_RX_ABBCTUNE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15171;"	d
+RG_TURISMO_TRX_BT_RX_ABBCTUNE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15173;"	d
+RG_TURISMO_TRX_BT_RX_ABBCTUNE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15175;"	d
+RG_TURISMO_TRX_BT_RX_ABB_BT_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15209;"	d
+RG_TURISMO_TRX_BT_RX_ABB_BT_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15207;"	d
+RG_TURISMO_TRX_BT_RX_ABB_BT_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15206;"	d
+RG_TURISMO_TRX_BT_RX_ABB_BT_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15208;"	d
+RG_TURISMO_TRX_BT_RX_ABB_BT_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15210;"	d
+RG_TURISMO_TRX_BT_RX_ABB_IDIV3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15214;"	d
+RG_TURISMO_TRX_BT_RX_ABB_IDIV3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15212;"	d
+RG_TURISMO_TRX_BT_RX_ABB_IDIV3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15211;"	d
+RG_TURISMO_TRX_BT_RX_ABB_IDIV3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15213;"	d
+RG_TURISMO_TRX_BT_RX_ABB_IDIV3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15215;"	d
+RG_TURISMO_TRX_BT_RX_ABB_N_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15204;"	d
+RG_TURISMO_TRX_BT_RX_ABB_N_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15202;"	d
+RG_TURISMO_TRX_BT_RX_ABB_N_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15201;"	d
+RG_TURISMO_TRX_BT_RX_ABB_N_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15203;"	d
+RG_TURISMO_TRX_BT_RX_ABB_N_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15205;"	d
+RG_TURISMO_TRX_BT_RX_ADC_CLOAD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15969;"	d
+RG_TURISMO_TRX_BT_RX_ADC_CLOAD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15967;"	d
+RG_TURISMO_TRX_BT_RX_ADC_CLOAD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15966;"	d
+RG_TURISMO_TRX_BT_RX_ADC_CLOAD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15968;"	d
+RG_TURISMO_TRX_BT_RX_ADC_CLOAD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15970;"	d
+RG_TURISMO_TRX_BT_RX_ADC_ICMP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15959;"	d
+RG_TURISMO_TRX_BT_RX_ADC_ICMP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15957;"	d
+RG_TURISMO_TRX_BT_RX_ADC_ICMP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15956;"	d
+RG_TURISMO_TRX_BT_RX_ADC_ICMP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15958;"	d
+RG_TURISMO_TRX_BT_RX_ADC_ICMP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15960;"	d
+RG_TURISMO_TRX_BT_RX_ADC_VCMI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15964;"	d
+RG_TURISMO_TRX_BT_RX_ADC_VCMI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15962;"	d
+RG_TURISMO_TRX_BT_RX_ADC_VCMI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15961;"	d
+RG_TURISMO_TRX_BT_RX_ADC_VCMI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15963;"	d
+RG_TURISMO_TRX_BT_RX_ADC_VCMI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15965;"	d
+RG_TURISMO_TRX_BT_RX_DCCAL_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17834;"	d
+RG_TURISMO_TRX_BT_RX_DCCAL_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17832;"	d
+RG_TURISMO_TRX_BT_RX_DCCAL_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17831;"	d
+RG_TURISMO_TRX_BT_RX_DCCAL_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17833;"	d
+RG_TURISMO_TRX_BT_RX_DCCAL_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17835;"	d
+RG_TURISMO_TRX_BT_RX_EN_IDACA_COARSE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15219;"	d
+RG_TURISMO_TRX_BT_RX_EN_IDACA_COARSE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15217;"	d
+RG_TURISMO_TRX_BT_RX_EN_IDACA_COARSE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15216;"	d
+RG_TURISMO_TRX_BT_RX_EN_IDACA_COARSE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15218;"	d
+RG_TURISMO_TRX_BT_RX_EN_IDACA_COARSE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15220;"	d
+RG_TURISMO_TRX_BT_RX_EN_LOOPA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15224;"	d
+RG_TURISMO_TRX_BT_RX_EN_LOOPA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15222;"	d
+RG_TURISMO_TRX_BT_RX_EN_LOOPA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15221;"	d
+RG_TURISMO_TRX_BT_RX_EN_LOOPA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15223;"	d
+RG_TURISMO_TRX_BT_RX_EN_LOOPA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15225;"	d
+RG_TURISMO_TRX_BT_RX_FILTERI1ST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15184;"	d
+RG_TURISMO_TRX_BT_RX_FILTERI1ST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15182;"	d
+RG_TURISMO_TRX_BT_RX_FILTERI1ST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15181;"	d
+RG_TURISMO_TRX_BT_RX_FILTERI1ST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15183;"	d
+RG_TURISMO_TRX_BT_RX_FILTERI1ST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15185;"	d
+RG_TURISMO_TRX_BT_RX_FILTERI2ND_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15189;"	d
+RG_TURISMO_TRX_BT_RX_FILTERI2ND_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15187;"	d
+RG_TURISMO_TRX_BT_RX_FILTERI2ND_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15186;"	d
+RG_TURISMO_TRX_BT_RX_FILTERI2ND_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15188;"	d
+RG_TURISMO_TRX_BT_RX_FILTERI2ND_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15190;"	d
+RG_TURISMO_TRX_BT_RX_FILTERI3RD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15194;"	d
+RG_TURISMO_TRX_BT_RX_FILTERI3RD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15192;"	d
+RG_TURISMO_TRX_BT_RX_FILTERI3RD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15191;"	d
+RG_TURISMO_TRX_BT_RX_FILTERI3RD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15193;"	d
+RG_TURISMO_TRX_BT_RX_FILTERI3RD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15195;"	d
+RG_TURISMO_TRX_BT_RX_FILTERI_COARSE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15179;"	d
+RG_TURISMO_TRX_BT_RX_FILTERI_COARSE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15177;"	d
+RG_TURISMO_TRX_BT_RX_FILTERI_COARSE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15176;"	d
+RG_TURISMO_TRX_BT_RX_FILTERI_COARSE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15178;"	d
+RG_TURISMO_TRX_BT_RX_FILTERI_COARSE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15180;"	d
+RG_TURISMO_TRX_BT_RX_FILTERVCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15229;"	d
+RG_TURISMO_TRX_BT_RX_FILTERVCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15227;"	d
+RG_TURISMO_TRX_BT_RX_FILTERVCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15226;"	d
+RG_TURISMO_TRX_BT_RX_FILTERVCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15228;"	d
+RG_TURISMO_TRX_BT_RX_FILTERVCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15230;"	d
+RG_TURISMO_TRX_BT_RX_HG_DIV2_CORE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15734;"	d
+RG_TURISMO_TRX_BT_RX_HG_DIV2_CORE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15732;"	d
+RG_TURISMO_TRX_BT_RX_HG_DIV2_CORE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15731;"	d
+RG_TURISMO_TRX_BT_RX_HG_DIV2_CORE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15733;"	d
+RG_TURISMO_TRX_BT_RX_HG_DIV2_CORE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15735;"	d
+RG_TURISMO_TRX_BT_RX_HG_LNAHGN_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15709;"	d
+RG_TURISMO_TRX_BT_RX_HG_LNAHGN_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15707;"	d
+RG_TURISMO_TRX_BT_RX_HG_LNAHGN_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15706;"	d
+RG_TURISMO_TRX_BT_RX_HG_LNAHGN_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15708;"	d
+RG_TURISMO_TRX_BT_RX_HG_LNAHGN_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15710;"	d
+RG_TURISMO_TRX_BT_RX_HG_LNAHGP_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15714;"	d
+RG_TURISMO_TRX_BT_RX_HG_LNAHGP_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15712;"	d
+RG_TURISMO_TRX_BT_RX_HG_LNAHGP_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15711;"	d
+RG_TURISMO_TRX_BT_RX_HG_LNAHGP_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15713;"	d
+RG_TURISMO_TRX_BT_RX_HG_LNAHGP_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15715;"	d
+RG_TURISMO_TRX_BT_RX_HG_LNALG_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15719;"	d
+RG_TURISMO_TRX_BT_RX_HG_LNALG_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15717;"	d
+RG_TURISMO_TRX_BT_RX_HG_LNALG_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15716;"	d
+RG_TURISMO_TRX_BT_RX_HG_LNALG_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15718;"	d
+RG_TURISMO_TRX_BT_RX_HG_LNALG_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15720;"	d
+RG_TURISMO_TRX_BT_RX_HG_LNA_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15699;"	d
+RG_TURISMO_TRX_BT_RX_HG_LNA_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15697;"	d
+RG_TURISMO_TRX_BT_RX_HG_LNA_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15696;"	d
+RG_TURISMO_TRX_BT_RX_HG_LNA_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15698;"	d
+RG_TURISMO_TRX_BT_RX_HG_LNA_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15700;"	d
+RG_TURISMO_TRX_BT_RX_HG_LOBUF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15739;"	d
+RG_TURISMO_TRX_BT_RX_HG_LOBUF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15737;"	d
+RG_TURISMO_TRX_BT_RX_HG_LOBUF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15736;"	d
+RG_TURISMO_TRX_BT_RX_HG_LOBUF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15738;"	d
+RG_TURISMO_TRX_BT_RX_HG_LOBUF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15740;"	d
+RG_TURISMO_TRX_BT_RX_HG_TZI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15744;"	d
+RG_TURISMO_TRX_BT_RX_HG_TZI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15742;"	d
+RG_TURISMO_TRX_BT_RX_HG_TZI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15741;"	d
+RG_TURISMO_TRX_BT_RX_HG_TZI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15743;"	d
+RG_TURISMO_TRX_BT_RX_HG_TZI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15745;"	d
+RG_TURISMO_TRX_BT_RX_HG_TZ_CAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15724;"	d
+RG_TURISMO_TRX_BT_RX_HG_TZ_CAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15722;"	d
+RG_TURISMO_TRX_BT_RX_HG_TZ_CAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15721;"	d
+RG_TURISMO_TRX_BT_RX_HG_TZ_CAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15723;"	d
+RG_TURISMO_TRX_BT_RX_HG_TZ_CAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15725;"	d
+RG_TURISMO_TRX_BT_RX_HG_TZ_GC_BOOST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15729;"	d
+RG_TURISMO_TRX_BT_RX_HG_TZ_GC_BOOST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15727;"	d
+RG_TURISMO_TRX_BT_RX_HG_TZ_GC_BOOST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15726;"	d
+RG_TURISMO_TRX_BT_RX_HG_TZ_GC_BOOST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15728;"	d
+RG_TURISMO_TRX_BT_RX_HG_TZ_GC_BOOST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15730;"	d
+RG_TURISMO_TRX_BT_RX_HG_TZ_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15704;"	d
+RG_TURISMO_TRX_BT_RX_HG_TZ_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15702;"	d
+RG_TURISMO_TRX_BT_RX_HG_TZ_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15701;"	d
+RG_TURISMO_TRX_BT_RX_HG_TZ_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15703;"	d
+RG_TURISMO_TRX_BT_RX_HG_TZ_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15705;"	d
+RG_TURISMO_TRX_BT_RX_HG_TZ_VCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15749;"	d
+RG_TURISMO_TRX_BT_RX_HG_TZ_VCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15747;"	d
+RG_TURISMO_TRX_BT_RX_HG_TZ_VCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15746;"	d
+RG_TURISMO_TRX_BT_RX_HG_TZ_VCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15748;"	d
+RG_TURISMO_TRX_BT_RX_HG_TZ_VCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15750;"	d
+RG_TURISMO_TRX_BT_RX_LG_DIV2_CORE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15844;"	d
+RG_TURISMO_TRX_BT_RX_LG_DIV2_CORE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15842;"	d
+RG_TURISMO_TRX_BT_RX_LG_DIV2_CORE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15841;"	d
+RG_TURISMO_TRX_BT_RX_LG_DIV2_CORE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15843;"	d
+RG_TURISMO_TRX_BT_RX_LG_DIV2_CORE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15845;"	d
+RG_TURISMO_TRX_BT_RX_LG_LNAHGN_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15819;"	d
+RG_TURISMO_TRX_BT_RX_LG_LNAHGN_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15817;"	d
+RG_TURISMO_TRX_BT_RX_LG_LNAHGN_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15816;"	d
+RG_TURISMO_TRX_BT_RX_LG_LNAHGN_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15818;"	d
+RG_TURISMO_TRX_BT_RX_LG_LNAHGN_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15820;"	d
+RG_TURISMO_TRX_BT_RX_LG_LNAHGP_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15824;"	d
+RG_TURISMO_TRX_BT_RX_LG_LNAHGP_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15822;"	d
+RG_TURISMO_TRX_BT_RX_LG_LNAHGP_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15821;"	d
+RG_TURISMO_TRX_BT_RX_LG_LNAHGP_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15823;"	d
+RG_TURISMO_TRX_BT_RX_LG_LNAHGP_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15825;"	d
+RG_TURISMO_TRX_BT_RX_LG_LNALG_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15829;"	d
+RG_TURISMO_TRX_BT_RX_LG_LNALG_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15827;"	d
+RG_TURISMO_TRX_BT_RX_LG_LNALG_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15826;"	d
+RG_TURISMO_TRX_BT_RX_LG_LNALG_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15828;"	d
+RG_TURISMO_TRX_BT_RX_LG_LNALG_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15830;"	d
+RG_TURISMO_TRX_BT_RX_LG_LNA_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15809;"	d
+RG_TURISMO_TRX_BT_RX_LG_LNA_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15807;"	d
+RG_TURISMO_TRX_BT_RX_LG_LNA_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15806;"	d
+RG_TURISMO_TRX_BT_RX_LG_LNA_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15808;"	d
+RG_TURISMO_TRX_BT_RX_LG_LNA_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15810;"	d
+RG_TURISMO_TRX_BT_RX_LG_LOBUF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15849;"	d
+RG_TURISMO_TRX_BT_RX_LG_LOBUF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15847;"	d
+RG_TURISMO_TRX_BT_RX_LG_LOBUF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15846;"	d
+RG_TURISMO_TRX_BT_RX_LG_LOBUF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15848;"	d
+RG_TURISMO_TRX_BT_RX_LG_LOBUF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15850;"	d
+RG_TURISMO_TRX_BT_RX_LG_TZI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15854;"	d
+RG_TURISMO_TRX_BT_RX_LG_TZI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15852;"	d
+RG_TURISMO_TRX_BT_RX_LG_TZI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15851;"	d
+RG_TURISMO_TRX_BT_RX_LG_TZI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15853;"	d
+RG_TURISMO_TRX_BT_RX_LG_TZI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15855;"	d
+RG_TURISMO_TRX_BT_RX_LG_TZ_CAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15834;"	d
+RG_TURISMO_TRX_BT_RX_LG_TZ_CAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15832;"	d
+RG_TURISMO_TRX_BT_RX_LG_TZ_CAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15831;"	d
+RG_TURISMO_TRX_BT_RX_LG_TZ_CAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15833;"	d
+RG_TURISMO_TRX_BT_RX_LG_TZ_CAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15835;"	d
+RG_TURISMO_TRX_BT_RX_LG_TZ_GC_BOOST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15839;"	d
+RG_TURISMO_TRX_BT_RX_LG_TZ_GC_BOOST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15837;"	d
+RG_TURISMO_TRX_BT_RX_LG_TZ_GC_BOOST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15836;"	d
+RG_TURISMO_TRX_BT_RX_LG_TZ_GC_BOOST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15838;"	d
+RG_TURISMO_TRX_BT_RX_LG_TZ_GC_BOOST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15840;"	d
+RG_TURISMO_TRX_BT_RX_LG_TZ_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15814;"	d
+RG_TURISMO_TRX_BT_RX_LG_TZ_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15812;"	d
+RG_TURISMO_TRX_BT_RX_LG_TZ_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15811;"	d
+RG_TURISMO_TRX_BT_RX_LG_TZ_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15813;"	d
+RG_TURISMO_TRX_BT_RX_LG_TZ_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15815;"	d
+RG_TURISMO_TRX_BT_RX_LG_TZ_VCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15859;"	d
+RG_TURISMO_TRX_BT_RX_LG_TZ_VCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15857;"	d
+RG_TURISMO_TRX_BT_RX_LG_TZ_VCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15856;"	d
+RG_TURISMO_TRX_BT_RX_LG_TZ_VCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15858;"	d
+RG_TURISMO_TRX_BT_RX_LG_TZ_VCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15860;"	d
+RG_TURISMO_TRX_BT_RX_MG_DIV2_CORE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15789;"	d
+RG_TURISMO_TRX_BT_RX_MG_DIV2_CORE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15787;"	d
+RG_TURISMO_TRX_BT_RX_MG_DIV2_CORE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15786;"	d
+RG_TURISMO_TRX_BT_RX_MG_DIV2_CORE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15788;"	d
+RG_TURISMO_TRX_BT_RX_MG_DIV2_CORE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15790;"	d
+RG_TURISMO_TRX_BT_RX_MG_LNAHGN_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15764;"	d
+RG_TURISMO_TRX_BT_RX_MG_LNAHGN_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15762;"	d
+RG_TURISMO_TRX_BT_RX_MG_LNAHGN_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15761;"	d
+RG_TURISMO_TRX_BT_RX_MG_LNAHGN_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15763;"	d
+RG_TURISMO_TRX_BT_RX_MG_LNAHGN_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15765;"	d
+RG_TURISMO_TRX_BT_RX_MG_LNAHGP_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15769;"	d
+RG_TURISMO_TRX_BT_RX_MG_LNAHGP_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15767;"	d
+RG_TURISMO_TRX_BT_RX_MG_LNAHGP_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15766;"	d
+RG_TURISMO_TRX_BT_RX_MG_LNAHGP_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15768;"	d
+RG_TURISMO_TRX_BT_RX_MG_LNAHGP_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15770;"	d
+RG_TURISMO_TRX_BT_RX_MG_LNALG_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15774;"	d
+RG_TURISMO_TRX_BT_RX_MG_LNALG_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15772;"	d
+RG_TURISMO_TRX_BT_RX_MG_LNALG_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15771;"	d
+RG_TURISMO_TRX_BT_RX_MG_LNALG_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15773;"	d
+RG_TURISMO_TRX_BT_RX_MG_LNALG_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15775;"	d
+RG_TURISMO_TRX_BT_RX_MG_LNA_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15754;"	d
+RG_TURISMO_TRX_BT_RX_MG_LNA_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15752;"	d
+RG_TURISMO_TRX_BT_RX_MG_LNA_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15751;"	d
+RG_TURISMO_TRX_BT_RX_MG_LNA_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15753;"	d
+RG_TURISMO_TRX_BT_RX_MG_LNA_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15755;"	d
+RG_TURISMO_TRX_BT_RX_MG_LOBUF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15794;"	d
+RG_TURISMO_TRX_BT_RX_MG_LOBUF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15792;"	d
+RG_TURISMO_TRX_BT_RX_MG_LOBUF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15791;"	d
+RG_TURISMO_TRX_BT_RX_MG_LOBUF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15793;"	d
+RG_TURISMO_TRX_BT_RX_MG_LOBUF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15795;"	d
+RG_TURISMO_TRX_BT_RX_MG_TZI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15799;"	d
+RG_TURISMO_TRX_BT_RX_MG_TZI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15797;"	d
+RG_TURISMO_TRX_BT_RX_MG_TZI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15796;"	d
+RG_TURISMO_TRX_BT_RX_MG_TZI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15798;"	d
+RG_TURISMO_TRX_BT_RX_MG_TZI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15800;"	d
+RG_TURISMO_TRX_BT_RX_MG_TZ_CAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15779;"	d
+RG_TURISMO_TRX_BT_RX_MG_TZ_CAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15777;"	d
+RG_TURISMO_TRX_BT_RX_MG_TZ_CAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15776;"	d
+RG_TURISMO_TRX_BT_RX_MG_TZ_CAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15778;"	d
+RG_TURISMO_TRX_BT_RX_MG_TZ_CAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15780;"	d
+RG_TURISMO_TRX_BT_RX_MG_TZ_GC_BOOST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15784;"	d
+RG_TURISMO_TRX_BT_RX_MG_TZ_GC_BOOST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15782;"	d
+RG_TURISMO_TRX_BT_RX_MG_TZ_GC_BOOST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15781;"	d
+RG_TURISMO_TRX_BT_RX_MG_TZ_GC_BOOST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15783;"	d
+RG_TURISMO_TRX_BT_RX_MG_TZ_GC_BOOST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15785;"	d
+RG_TURISMO_TRX_BT_RX_MG_TZ_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15759;"	d
+RG_TURISMO_TRX_BT_RX_MG_TZ_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15757;"	d
+RG_TURISMO_TRX_BT_RX_MG_TZ_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15756;"	d
+RG_TURISMO_TRX_BT_RX_MG_TZ_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15758;"	d
+RG_TURISMO_TRX_BT_RX_MG_TZ_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15760;"	d
+RG_TURISMO_TRX_BT_RX_MG_TZ_VCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15804;"	d
+RG_TURISMO_TRX_BT_RX_MG_TZ_VCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15802;"	d
+RG_TURISMO_TRX_BT_RX_MG_TZ_VCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15801;"	d
+RG_TURISMO_TRX_BT_RX_MG_TZ_VCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15803;"	d
+RG_TURISMO_TRX_BT_RX_MG_TZ_VCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15805;"	d
+RG_TURISMO_TRX_BT_RX_OUTVCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15234;"	d
+RG_TURISMO_TRX_BT_RX_OUTVCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15232;"	d
+RG_TURISMO_TRX_BT_RX_OUTVCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15231;"	d
+RG_TURISMO_TRX_BT_RX_OUTVCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15233;"	d
+RG_TURISMO_TRX_BT_RX_OUTVCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15235;"	d
+RG_TURISMO_TRX_BT_RX_ULG_DIV2_CORE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15899;"	d
+RG_TURISMO_TRX_BT_RX_ULG_DIV2_CORE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15897;"	d
+RG_TURISMO_TRX_BT_RX_ULG_DIV2_CORE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15896;"	d
+RG_TURISMO_TRX_BT_RX_ULG_DIV2_CORE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15898;"	d
+RG_TURISMO_TRX_BT_RX_ULG_DIV2_CORE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15900;"	d
+RG_TURISMO_TRX_BT_RX_ULG_LNAHGN_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15874;"	d
+RG_TURISMO_TRX_BT_RX_ULG_LNAHGN_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15872;"	d
+RG_TURISMO_TRX_BT_RX_ULG_LNAHGN_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15871;"	d
+RG_TURISMO_TRX_BT_RX_ULG_LNAHGN_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15873;"	d
+RG_TURISMO_TRX_BT_RX_ULG_LNAHGN_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15875;"	d
+RG_TURISMO_TRX_BT_RX_ULG_LNAHGP_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15879;"	d
+RG_TURISMO_TRX_BT_RX_ULG_LNAHGP_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15877;"	d
+RG_TURISMO_TRX_BT_RX_ULG_LNAHGP_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15876;"	d
+RG_TURISMO_TRX_BT_RX_ULG_LNAHGP_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15878;"	d
+RG_TURISMO_TRX_BT_RX_ULG_LNAHGP_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15880;"	d
+RG_TURISMO_TRX_BT_RX_ULG_LNALG_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15884;"	d
+RG_TURISMO_TRX_BT_RX_ULG_LNALG_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15882;"	d
+RG_TURISMO_TRX_BT_RX_ULG_LNALG_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15881;"	d
+RG_TURISMO_TRX_BT_RX_ULG_LNALG_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15883;"	d
+RG_TURISMO_TRX_BT_RX_ULG_LNALG_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15885;"	d
+RG_TURISMO_TRX_BT_RX_ULG_LNA_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15864;"	d
+RG_TURISMO_TRX_BT_RX_ULG_LNA_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15862;"	d
+RG_TURISMO_TRX_BT_RX_ULG_LNA_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15861;"	d
+RG_TURISMO_TRX_BT_RX_ULG_LNA_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15863;"	d
+RG_TURISMO_TRX_BT_RX_ULG_LNA_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15865;"	d
+RG_TURISMO_TRX_BT_RX_ULG_LOBUF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15904;"	d
+RG_TURISMO_TRX_BT_RX_ULG_LOBUF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15902;"	d
+RG_TURISMO_TRX_BT_RX_ULG_LOBUF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15901;"	d
+RG_TURISMO_TRX_BT_RX_ULG_LOBUF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15903;"	d
+RG_TURISMO_TRX_BT_RX_ULG_LOBUF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15905;"	d
+RG_TURISMO_TRX_BT_RX_ULG_TZI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15909;"	d
+RG_TURISMO_TRX_BT_RX_ULG_TZI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15907;"	d
+RG_TURISMO_TRX_BT_RX_ULG_TZI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15906;"	d
+RG_TURISMO_TRX_BT_RX_ULG_TZI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15908;"	d
+RG_TURISMO_TRX_BT_RX_ULG_TZI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15910;"	d
+RG_TURISMO_TRX_BT_RX_ULG_TZ_CAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15889;"	d
+RG_TURISMO_TRX_BT_RX_ULG_TZ_CAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15887;"	d
+RG_TURISMO_TRX_BT_RX_ULG_TZ_CAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15886;"	d
+RG_TURISMO_TRX_BT_RX_ULG_TZ_CAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15888;"	d
+RG_TURISMO_TRX_BT_RX_ULG_TZ_CAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15890;"	d
+RG_TURISMO_TRX_BT_RX_ULG_TZ_GC_BOOST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15894;"	d
+RG_TURISMO_TRX_BT_RX_ULG_TZ_GC_BOOST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15892;"	d
+RG_TURISMO_TRX_BT_RX_ULG_TZ_GC_BOOST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15891;"	d
+RG_TURISMO_TRX_BT_RX_ULG_TZ_GC_BOOST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15893;"	d
+RG_TURISMO_TRX_BT_RX_ULG_TZ_GC_BOOST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15895;"	d
+RG_TURISMO_TRX_BT_RX_ULG_TZ_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15869;"	d
+RG_TURISMO_TRX_BT_RX_ULG_TZ_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15867;"	d
+RG_TURISMO_TRX_BT_RX_ULG_TZ_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15866;"	d
+RG_TURISMO_TRX_BT_RX_ULG_TZ_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15868;"	d
+RG_TURISMO_TRX_BT_RX_ULG_TZ_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15870;"	d
+RG_TURISMO_TRX_BT_RX_ULG_TZ_VCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15914;"	d
+RG_TURISMO_TRX_BT_RX_ULG_TZ_VCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15912;"	d
+RG_TURISMO_TRX_BT_RX_ULG_TZ_VCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15911;"	d
+RG_TURISMO_TRX_BT_RX_ULG_TZ_VCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15913;"	d
+RG_TURISMO_TRX_BT_RX_ULG_TZ_VCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15915;"	d
+RG_TURISMO_TRX_BT_TRX_IF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20164;"	d
+RG_TURISMO_TRX_BT_TRX_IF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20162;"	d
+RG_TURISMO_TRX_BT_TRX_IF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20161;"	d
+RG_TURISMO_TRX_BT_TRX_IF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20163;"	d
+RG_TURISMO_TRX_BT_TRX_IF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20165;"	d
+RG_TURISMO_TRX_BT_TXLPF_BOOSTI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16099;"	d
+RG_TURISMO_TRX_BT_TXLPF_BOOSTI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16097;"	d
+RG_TURISMO_TRX_BT_TXLPF_BOOSTI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16096;"	d
+RG_TURISMO_TRX_BT_TXLPF_BOOSTI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16098;"	d
+RG_TURISMO_TRX_BT_TXLPF_BOOSTI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16100;"	d
+RG_TURISMO_TRX_BT_TXPGA_CAPSW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15334;"	d
+RG_TURISMO_TRX_BT_TXPGA_CAPSW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15332;"	d
+RG_TURISMO_TRX_BT_TXPGA_CAPSW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15331;"	d
+RG_TURISMO_TRX_BT_TXPGA_CAPSW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15333;"	d
+RG_TURISMO_TRX_BT_TXPGA_CAPSW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15335;"	d
+RG_TURISMO_TRX_BT_TX_BTPASW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15349;"	d
+RG_TURISMO_TRX_BT_TX_BTPASW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15347;"	d
+RG_TURISMO_TRX_BT_TX_BTPASW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15346;"	d
+RG_TURISMO_TRX_BT_TX_BTPASW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15348;"	d
+RG_TURISMO_TRX_BT_TX_BTPASW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15350;"	d
+RG_TURISMO_TRX_BT_TX_DACI1ST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16069;"	d
+RG_TURISMO_TRX_BT_TX_DACI1ST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16067;"	d
+RG_TURISMO_TRX_BT_TX_DACI1ST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16066;"	d
+RG_TURISMO_TRX_BT_TX_DACI1ST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16068;"	d
+RG_TURISMO_TRX_BT_TX_DACI1ST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16070;"	d
+RG_TURISMO_TRX_BT_TX_DACLPF_ICOARSE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16074;"	d
+RG_TURISMO_TRX_BT_TX_DACLPF_ICOARSE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16072;"	d
+RG_TURISMO_TRX_BT_TX_DACLPF_ICOARSE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16071;"	d
+RG_TURISMO_TRX_BT_TX_DACLPF_ICOARSE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16073;"	d
+RG_TURISMO_TRX_BT_TX_DACLPF_ICOARSE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16075;"	d
+RG_TURISMO_TRX_BT_TX_DACLPF_IFINE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16079;"	d
+RG_TURISMO_TRX_BT_TX_DACLPF_IFINE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16077;"	d
+RG_TURISMO_TRX_BT_TX_DACLPF_IFINE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16076;"	d
+RG_TURISMO_TRX_BT_TX_DACLPF_IFINE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16078;"	d
+RG_TURISMO_TRX_BT_TX_DACLPF_IFINE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16080;"	d
+RG_TURISMO_TRX_BT_TX_DACLPF_VCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16084;"	d
+RG_TURISMO_TRX_BT_TX_DACLPF_VCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16082;"	d
+RG_TURISMO_TRX_BT_TX_DACLPF_VCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16081;"	d
+RG_TURISMO_TRX_BT_TX_DACLPF_VCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16083;"	d
+RG_TURISMO_TRX_BT_TX_DACLPF_VCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16085;"	d
+RG_TURISMO_TRX_BT_TX_DAC_CKEDGE_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16109;"	d
+RG_TURISMO_TRX_BT_TX_DAC_CKEDGE_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16107;"	d
+RG_TURISMO_TRX_BT_TX_DAC_CKEDGE_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16106;"	d
+RG_TURISMO_TRX_BT_TX_DAC_CKEDGE_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16108;"	d
+RG_TURISMO_TRX_BT_TX_DAC_CKEDGE_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16110;"	d
+RG_TURISMO_TRX_BT_TX_DAC_IATTN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16094;"	d
+RG_TURISMO_TRX_BT_TX_DAC_IATTN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16092;"	d
+RG_TURISMO_TRX_BT_TX_DAC_IATTN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16091;"	d
+RG_TURISMO_TRX_BT_TX_DAC_IATTN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16093;"	d
+RG_TURISMO_TRX_BT_TX_DAC_IATTN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16095;"	d
+RG_TURISMO_TRX_BT_TX_DAC_IBIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16089;"	d
+RG_TURISMO_TRX_BT_TX_DAC_IBIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16087;"	d
+RG_TURISMO_TRX_BT_TX_DAC_IBIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16086;"	d
+RG_TURISMO_TRX_BT_TX_DAC_IBIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16088;"	d
+RG_TURISMO_TRX_BT_TX_DAC_IBIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16090;"	d
+RG_TURISMO_TRX_BT_TX_DAC_IOFFSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16119;"	d
+RG_TURISMO_TRX_BT_TX_DAC_IOFFSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16117;"	d
+RG_TURISMO_TRX_BT_TX_DAC_IOFFSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16116;"	d
+RG_TURISMO_TRX_BT_TX_DAC_IOFFSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16118;"	d
+RG_TURISMO_TRX_BT_TX_DAC_IOFFSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16120;"	d
+RG_TURISMO_TRX_BT_TX_DAC_OS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16114;"	d
+RG_TURISMO_TRX_BT_TX_DAC_OS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16112;"	d
+RG_TURISMO_TRX_BT_TX_DAC_OS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16111;"	d
+RG_TURISMO_TRX_BT_TX_DAC_OS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16113;"	d
+RG_TURISMO_TRX_BT_TX_DAC_OS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16115;"	d
+RG_TURISMO_TRX_BT_TX_DAC_QOFFSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16124;"	d
+RG_TURISMO_TRX_BT_TX_DAC_QOFFSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16122;"	d
+RG_TURISMO_TRX_BT_TX_DAC_QOFFSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16121;"	d
+RG_TURISMO_TRX_BT_TX_DAC_QOFFSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16123;"	d
+RG_TURISMO_TRX_BT_TX_DAC_QOFFSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16125;"	d
+RG_TURISMO_TRX_BT_TX_DAC_RCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16104;"	d
+RG_TURISMO_TRX_BT_TX_DAC_RCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16102;"	d
+RG_TURISMO_TRX_BT_TX_DAC_RCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16101;"	d
+RG_TURISMO_TRX_BT_TX_DAC_RCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16103;"	d
+RG_TURISMO_TRX_BT_TX_DAC_RCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16105;"	d
+RG_TURISMO_TRX_BT_TX_DIV_VSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15339;"	d
+RG_TURISMO_TRX_BT_TX_DIV_VSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15337;"	d
+RG_TURISMO_TRX_BT_TX_DIV_VSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15336;"	d
+RG_TURISMO_TRX_BT_TX_DIV_VSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15338;"	d
+RG_TURISMO_TRX_BT_TX_DIV_VSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15340;"	d
+RG_TURISMO_TRX_BT_TX_GAIN_OFFSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15454;"	d
+RG_TURISMO_TRX_BT_TX_GAIN_OFFSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15452;"	d
+RG_TURISMO_TRX_BT_TX_GAIN_OFFSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15451;"	d
+RG_TURISMO_TRX_BT_TX_GAIN_OFFSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15453;"	d
+RG_TURISMO_TRX_BT_TX_GAIN_OFFSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15455;"	d
+RG_TURISMO_TRX_BT_TX_LOBUF_VSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15344;"	d
+RG_TURISMO_TRX_BT_TX_LOBUF_VSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15342;"	d
+RG_TURISMO_TRX_BT_TX_LOBUF_VSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15341;"	d
+RG_TURISMO_TRX_BT_TX_LOBUF_VSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15343;"	d
+RG_TURISMO_TRX_BT_TX_LOBUF_VSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15345;"	d
+RG_TURISMO_TRX_BT_TX_MOD_CS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15424;"	d
+RG_TURISMO_TRX_BT_TX_MOD_CS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15422;"	d
+RG_TURISMO_TRX_BT_TX_MOD_CS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15421;"	d
+RG_TURISMO_TRX_BT_TX_MOD_CS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15423;"	d
+RG_TURISMO_TRX_BT_TX_MOD_CS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15425;"	d
+RG_TURISMO_TRX_BT_TX_PA_VCAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15419;"	d
+RG_TURISMO_TRX_BT_TX_PA_VCAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15417;"	d
+RG_TURISMO_TRX_BT_TX_PA_VCAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15416;"	d
+RG_TURISMO_TRX_BT_TX_PA_VCAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15418;"	d
+RG_TURISMO_TRX_BT_TX_PA_VCAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15420;"	d
+RG_TURISMO_TRX_BUCK_EN_PSM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20809;"	d
+RG_TURISMO_TRX_BUCK_EN_PSM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20807;"	d
+RG_TURISMO_TRX_BUCK_EN_PSM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20806;"	d
+RG_TURISMO_TRX_BUCK_EN_PSM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20808;"	d
+RG_TURISMO_TRX_BUCK_EN_PSM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20810;"	d
+RG_TURISMO_TRX_BUCK_LEVEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20799;"	d
+RG_TURISMO_TRX_BUCK_LEVEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20797;"	d
+RG_TURISMO_TRX_BUCK_LEVEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20796;"	d
+RG_TURISMO_TRX_BUCK_LEVEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20798;"	d
+RG_TURISMO_TRX_BUCK_LEVEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20800;"	d
+RG_TURISMO_TRX_BUCK_PSM_VTH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20814;"	d
+RG_TURISMO_TRX_BUCK_PSM_VTH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20812;"	d
+RG_TURISMO_TRX_BUCK_PSM_VTH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20811;"	d
+RG_TURISMO_TRX_BUCK_PSM_VTH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20813;"	d
+RG_TURISMO_TRX_BUCK_PSM_VTH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20815;"	d
+RG_TURISMO_TRX_BUCK_RCZERO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20864;"	d
+RG_TURISMO_TRX_BUCK_RCZERO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20862;"	d
+RG_TURISMO_TRX_BUCK_RCZERO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20861;"	d
+RG_TURISMO_TRX_BUCK_RCZERO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20863;"	d
+RG_TURISMO_TRX_BUCK_RCZERO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20865;"	d
+RG_TURISMO_TRX_BUCK_SLOP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20869;"	d
+RG_TURISMO_TRX_BUCK_SLOP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20867;"	d
+RG_TURISMO_TRX_BUCK_SLOP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20866;"	d
+RG_TURISMO_TRX_BUCK_SLOP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20868;"	d
+RG_TURISMO_TRX_BUCK_SLOP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20870;"	d
+RG_TURISMO_TRX_BUCK_VREF_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20819;"	d
+RG_TURISMO_TRX_BUCK_VREF_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20817;"	d
+RG_TURISMO_TRX_BUCK_VREF_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20816;"	d
+RG_TURISMO_TRX_BUCK_VREF_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20818;"	d
+RG_TURISMO_TRX_BUCK_VREF_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20820;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_00_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20339;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_00_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20337;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_00_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20336;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_00_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20338;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_00_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20340;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_01_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20334;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_01_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20332;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_01_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20331;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_01_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20333;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_01_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20335;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_02_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20349;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_02_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20347;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_02_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20346;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_02_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20348;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_02_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20350;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_03_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20344;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_03_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20342;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_03_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20341;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_03_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20343;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_03_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20345;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_04_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20359;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_04_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20357;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_04_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20356;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_04_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20358;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_04_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20360;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_05_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20354;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_05_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20352;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_05_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20351;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_05_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20353;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_05_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20355;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_06_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20369;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_06_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20367;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_06_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20366;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_06_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20368;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_06_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20370;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_07_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20364;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_07_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20362;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_07_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20361;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_07_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20363;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_07_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20365;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_08_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20379;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_08_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20377;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_08_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20376;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_08_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20378;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_08_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20380;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_09_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20374;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_09_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20372;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_09_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20371;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_09_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20373;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_09_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20375;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_10_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20389;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_10_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20387;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_10_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20386;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_10_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20388;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_10_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20390;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_11_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20384;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_11_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20382;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_11_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20381;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_11_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20383;"	d
+RG_TURISMO_TRX_BW20_HB_COEF_11_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20385;"	d
+RG_TURISMO_TRX_BW_HT40_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14659;"	d
+RG_TURISMO_TRX_BW_HT40_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14657;"	d
+RG_TURISMO_TRX_BW_HT40_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14656;"	d
+RG_TURISMO_TRX_BW_HT40_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14658;"	d
+RG_TURISMO_TRX_BW_HT40_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14660;"	d
+RG_TURISMO_TRX_BW_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14664;"	d
+RG_TURISMO_TRX_BW_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14662;"	d
+RG_TURISMO_TRX_BW_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14661;"	d
+RG_TURISMO_TRX_BW_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14663;"	d
+RG_TURISMO_TRX_BW_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14665;"	d
+RG_TURISMO_TRX_CAL_INDEX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14644;"	d
+RG_TURISMO_TRX_CAL_INDEX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14642;"	d
+RG_TURISMO_TRX_CAL_INDEX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14641;"	d
+RG_TURISMO_TRX_CAL_INDEX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14643;"	d
+RG_TURISMO_TRX_CAL_INDEX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14645;"	d
+RG_TURISMO_TRX_CBW_20_40_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20299;"	d
+RG_TURISMO_TRX_CBW_20_40_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20297;"	d
+RG_TURISMO_TRX_CBW_20_40_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20296;"	d
+RG_TURISMO_TRX_CBW_20_40_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20298;"	d
+RG_TURISMO_TRX_CBW_20_40_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20300;"	d
+RG_TURISMO_TRX_CLK_320M_INV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20289;"	d
+RG_TURISMO_TRX_CLK_320M_INV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20287;"	d
+RG_TURISMO_TRX_CLK_320M_INV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20286;"	d
+RG_TURISMO_TRX_CLK_320M_INV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20288;"	d
+RG_TURISMO_TRX_CLK_320M_INV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20290;"	d
+RG_TURISMO_TRX_CLK_MON_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21399;"	d
+RG_TURISMO_TRX_CLK_MON_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21397;"	d
+RG_TURISMO_TRX_CLK_MON_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21396;"	d
+RG_TURISMO_TRX_CLK_MON_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21398;"	d
+RG_TURISMO_TRX_CLK_MON_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21400;"	d
+RG_TURISMO_TRX_CLK_RTC_SW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21014;"	d
+RG_TURISMO_TRX_CLK_RTC_SW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21012;"	d
+RG_TURISMO_TRX_CLK_RTC_SW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21011;"	d
+RG_TURISMO_TRX_CLK_RTC_SW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21013;"	d
+RG_TURISMO_TRX_CLK_RTC_SW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21015;"	d
+RG_TURISMO_TRX_CLK_SAR_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15999;"	d
+RG_TURISMO_TRX_CLK_SAR_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15997;"	d
+RG_TURISMO_TRX_CLK_SAR_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15996;"	d
+RG_TURISMO_TRX_CLK_SAR_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15998;"	d
+RG_TURISMO_TRX_CLK_SAR_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16000;"	d
+RG_TURISMO_TRX_DAC_DC_I_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20309;"	d
+RG_TURISMO_TRX_DAC_DC_I_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20307;"	d
+RG_TURISMO_TRX_DAC_DC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20306;"	d
+RG_TURISMO_TRX_DAC_DC_I_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20308;"	d
+RG_TURISMO_TRX_DAC_DC_I_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20310;"	d
+RG_TURISMO_TRX_DAC_DC_Q_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20304;"	d
+RG_TURISMO_TRX_DAC_DC_Q_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20302;"	d
+RG_TURISMO_TRX_DAC_DC_Q_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20301;"	d
+RG_TURISMO_TRX_DAC_DC_Q_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20303;"	d
+RG_TURISMO_TRX_DAC_DC_Q_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20305;"	d
+RG_TURISMO_TRX_DAC_I_SET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20324;"	d
+RG_TURISMO_TRX_DAC_I_SET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20322;"	d
+RG_TURISMO_TRX_DAC_I_SET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20321;"	d
+RG_TURISMO_TRX_DAC_I_SET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20323;"	d
+RG_TURISMO_TRX_DAC_I_SET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20325;"	d
+RG_TURISMO_TRX_DAC_MAN_I_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20329;"	d
+RG_TURISMO_TRX_DAC_MAN_I_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20327;"	d
+RG_TURISMO_TRX_DAC_MAN_I_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20326;"	d
+RG_TURISMO_TRX_DAC_MAN_I_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20328;"	d
+RG_TURISMO_TRX_DAC_MAN_I_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20330;"	d
+RG_TURISMO_TRX_DAC_MAN_Q_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20319;"	d
+RG_TURISMO_TRX_DAC_MAN_Q_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20317;"	d
+RG_TURISMO_TRX_DAC_MAN_Q_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20316;"	d
+RG_TURISMO_TRX_DAC_MAN_Q_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20318;"	d
+RG_TURISMO_TRX_DAC_MAN_Q_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20320;"	d
+RG_TURISMO_TRX_DAC_Q_SET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20314;"	d
+RG_TURISMO_TRX_DAC_Q_SET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20312;"	d
+RG_TURISMO_TRX_DAC_Q_SET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20311;"	d
+RG_TURISMO_TRX_DAC_Q_SET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20313;"	d
+RG_TURISMO_TRX_DAC_Q_SET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20315;"	d
+RG_TURISMO_TRX_DCDC_CLK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20859;"	d
+RG_TURISMO_TRX_DCDC_CLK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20857;"	d
+RG_TURISMO_TRX_DCDC_CLK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20856;"	d
+RG_TURISMO_TRX_DCDC_CLK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20858;"	d
+RG_TURISMO_TRX_DCDC_CLK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20860;"	d
+RG_TURISMO_TRX_DCDC_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20789;"	d
+RG_TURISMO_TRX_DCDC_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20787;"	d
+RG_TURISMO_TRX_DCDC_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20786;"	d
+RG_TURISMO_TRX_DCDC_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20788;"	d
+RG_TURISMO_TRX_DCDC_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20790;"	d
+RG_TURISMO_TRX_DCDC_PULLLOW_CON_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20834;"	d
+RG_TURISMO_TRX_DCDC_PULLLOW_CON_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20832;"	d
+RG_TURISMO_TRX_DCDC_PULLLOW_CON_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20831;"	d
+RG_TURISMO_TRX_DCDC_PULLLOW_CON_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20833;"	d
+RG_TURISMO_TRX_DCDC_PULLLOW_CON_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20835;"	d
+RG_TURISMO_TRX_DCDC_RES2_CON_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20839;"	d
+RG_TURISMO_TRX_DCDC_RES2_CON_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20837;"	d
+RG_TURISMO_TRX_DCDC_RES2_CON_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20836;"	d
+RG_TURISMO_TRX_DCDC_RES2_CON_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20838;"	d
+RG_TURISMO_TRX_DCDC_RES2_CON_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20840;"	d
+RG_TURISMO_TRX_DCDC_RES_CON_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20844;"	d
+RG_TURISMO_TRX_DCDC_RES_CON_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20842;"	d
+RG_TURISMO_TRX_DCDC_RES_CON_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20841;"	d
+RG_TURISMO_TRX_DCDC_RES_CON_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20843;"	d
+RG_TURISMO_TRX_DCDC_RES_CON_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20845;"	d
+RG_TURISMO_TRX_DIS_DAC_OFFSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20284;"	d
+RG_TURISMO_TRX_DIS_DAC_OFFSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20282;"	d
+RG_TURISMO_TRX_DIS_DAC_OFFSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20281;"	d
+RG_TURISMO_TRX_DIS_DAC_OFFSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20283;"	d
+RG_TURISMO_TRX_DIS_DAC_OFFSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20285;"	d
+RG_TURISMO_TRX_DLDO_BOOST_IQ_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20804;"	d
+RG_TURISMO_TRX_DLDO_BOOST_IQ_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20802;"	d
+RG_TURISMO_TRX_DLDO_BOOST_IQ_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20801;"	d
+RG_TURISMO_TRX_DLDO_BOOST_IQ_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20803;"	d
+RG_TURISMO_TRX_DLDO_BOOST_IQ_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20805;"	d
+RG_TURISMO_TRX_DLDO_LEVEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20794;"	d
+RG_TURISMO_TRX_DLDO_LEVEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20792;"	d
+RG_TURISMO_TRX_DLDO_LEVEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20791;"	d
+RG_TURISMO_TRX_DLDO_LEVEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20793;"	d
+RG_TURISMO_TRX_DLDO_LEVEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20795;"	d
+RG_TURISMO_TRX_DPLL_CLK320BY2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20294;"	d
+RG_TURISMO_TRX_DPLL_CLK320BY2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20292;"	d
+RG_TURISMO_TRX_DPLL_CLK320BY2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20291;"	d
+RG_TURISMO_TRX_DPLL_CLK320BY2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20293;"	d
+RG_TURISMO_TRX_DPLL_CLK320BY2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20295;"	d
+RG_TURISMO_TRX_DPL_MOD_ORDER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16914;"	d
+RG_TURISMO_TRX_DPL_MOD_ORDER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16912;"	d
+RG_TURISMO_TRX_DPL_MOD_ORDER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16911;"	d
+RG_TURISMO_TRX_DPL_MOD_ORDER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16913;"	d
+RG_TURISMO_TRX_DPL_MOD_ORDER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16915;"	d
+RG_TURISMO_TRX_DPL_RFCTRL_CH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17014;"	d
+RG_TURISMO_TRX_DPL_RFCTRL_CH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17012;"	d
+RG_TURISMO_TRX_DPL_RFCTRL_CH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17011;"	d
+RG_TURISMO_TRX_DPL_RFCTRL_CH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17013;"	d
+RG_TURISMO_TRX_DPL_RFCTRL_CH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17015;"	d
+RG_TURISMO_TRX_DPL_RFCTRL_F_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17009;"	d
+RG_TURISMO_TRX_DPL_RFCTRL_F_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17007;"	d
+RG_TURISMO_TRX_DPL_RFCTRL_F_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17006;"	d
+RG_TURISMO_TRX_DPL_RFCTRL_F_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17008;"	d
+RG_TURISMO_TRX_DPL_RFCTRL_F_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17010;"	d
+RG_TURISMO_TRX_DPL_SETTLING_TIMMER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20759;"	d
+RG_TURISMO_TRX_DPL_SETTLING_TIMMER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20757;"	d
+RG_TURISMO_TRX_DPL_SETTLING_TIMMER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20756;"	d
+RG_TURISMO_TRX_DPL_SETTLING_TIMMER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20758;"	d
+RG_TURISMO_TRX_DPL_SETTLING_TIMMER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20760;"	d
+RG_TURISMO_TRX_DP_ADC320_DIVBY2_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16899;"	d
+RG_TURISMO_TRX_DP_ADC320_DIVBY2_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16897;"	d
+RG_TURISMO_TRX_DP_ADC320_DIVBY2_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16896;"	d
+RG_TURISMO_TRX_DP_ADC320_DIVBY2_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16898;"	d
+RG_TURISMO_TRX_DP_ADC320_DIVBY2_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16900;"	d
+RG_TURISMO_TRX_DP_ADC320_DIVBY2_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16904;"	d
+RG_TURISMO_TRX_DP_ADC320_DIVBY2_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16902;"	d
+RG_TURISMO_TRX_DP_ADC320_DIVBY2_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16901;"	d
+RG_TURISMO_TRX_DP_ADC320_DIVBY2_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16903;"	d
+RG_TURISMO_TRX_DP_ADC320_DIVBY2_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16905;"	d
+RG_TURISMO_TRX_DP_BBPLL_BP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16879;"	d
+RG_TURISMO_TRX_DP_BBPLL_BP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16877;"	d
+RG_TURISMO_TRX_DP_BBPLL_BP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16876;"	d
+RG_TURISMO_TRX_DP_BBPLL_BP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16878;"	d
+RG_TURISMO_TRX_DP_BBPLL_BP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16880;"	d
+RG_TURISMO_TRX_DP_BBPLL_BS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16999;"	d
+RG_TURISMO_TRX_DP_BBPLL_BS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16997;"	d
+RG_TURISMO_TRX_DP_BBPLL_BS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16996;"	d
+RG_TURISMO_TRX_DP_BBPLL_BS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16998;"	d
+RG_TURISMO_TRX_DP_BBPLL_BS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17000;"	d
+RG_TURISMO_TRX_DP_BBPLL_ICP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16944;"	d
+RG_TURISMO_TRX_DP_BBPLL_ICP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16942;"	d
+RG_TURISMO_TRX_DP_BBPLL_ICP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16941;"	d
+RG_TURISMO_TRX_DP_BBPLL_ICP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16943;"	d
+RG_TURISMO_TRX_DP_BBPLL_ICP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16945;"	d
+RG_TURISMO_TRX_DP_BBPLL_IDUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16949;"	d
+RG_TURISMO_TRX_DP_BBPLL_IDUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16947;"	d
+RG_TURISMO_TRX_DP_BBPLL_IDUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16946;"	d
+RG_TURISMO_TRX_DP_BBPLL_IDUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16948;"	d
+RG_TURISMO_TRX_DP_BBPLL_IDUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16950;"	d
+RG_TURISMO_TRX_DP_BBPLL_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16874;"	d
+RG_TURISMO_TRX_DP_BBPLL_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16872;"	d
+RG_TURISMO_TRX_DP_BBPLL_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16871;"	d
+RG_TURISMO_TRX_DP_BBPLL_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16873;"	d
+RG_TURISMO_TRX_DP_BBPLL_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16875;"	d
+RG_TURISMO_TRX_DP_BBPLL_PFD_DLY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16969;"	d
+RG_TURISMO_TRX_DP_BBPLL_PFD_DLY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16967;"	d
+RG_TURISMO_TRX_DP_BBPLL_PFD_DLY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16966;"	d
+RG_TURISMO_TRX_DP_BBPLL_PFD_DLY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16968;"	d
+RG_TURISMO_TRX_DP_BBPLL_PFD_DLY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16970;"	d
+RG_TURISMO_TRX_DP_BBPLL_SDM_EDGE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17004;"	d
+RG_TURISMO_TRX_DP_BBPLL_SDM_EDGE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17002;"	d
+RG_TURISMO_TRX_DP_BBPLL_SDM_EDGE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17001;"	d
+RG_TURISMO_TRX_DP_BBPLL_SDM_EDGE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17003;"	d
+RG_TURISMO_TRX_DP_BBPLL_SDM_EDGE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17005;"	d
+RG_TURISMO_TRX_DP_BBPLL_TESTSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16939;"	d
+RG_TURISMO_TRX_DP_BBPLL_TESTSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16937;"	d
+RG_TURISMO_TRX_DP_BBPLL_TESTSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16936;"	d
+RG_TURISMO_TRX_DP_BBPLL_TESTSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16938;"	d
+RG_TURISMO_TRX_DP_BBPLL_TESTSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16940;"	d
+RG_TURISMO_TRX_DP_CP_IOSTPOL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16954;"	d
+RG_TURISMO_TRX_DP_CP_IOSTPOL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16952;"	d
+RG_TURISMO_TRX_DP_CP_IOSTPOL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16951;"	d
+RG_TURISMO_TRX_DP_CP_IOSTPOL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16953;"	d
+RG_TURISMO_TRX_DP_CP_IOSTPOL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16955;"	d
+RG_TURISMO_TRX_DP_CP_IOST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16959;"	d
+RG_TURISMO_TRX_DP_CP_IOST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16957;"	d
+RG_TURISMO_TRX_DP_CP_IOST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16956;"	d
+RG_TURISMO_TRX_DP_CP_IOST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16958;"	d
+RG_TURISMO_TRX_DP_CP_IOST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16960;"	d
+RG_TURISMO_TRX_DP_DAC320_DIVBY2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16894;"	d
+RG_TURISMO_TRX_DP_DAC320_DIVBY2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16892;"	d
+RG_TURISMO_TRX_DP_DAC320_DIVBY2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16891;"	d
+RG_TURISMO_TRX_DP_DAC320_DIVBY2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16893;"	d
+RG_TURISMO_TRX_DP_DAC320_DIVBY2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16895;"	d
+RG_TURISMO_TRX_DP_FODIV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16924;"	d
+RG_TURISMO_TRX_DP_FODIV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16922;"	d
+RG_TURISMO_TRX_DP_FODIV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16921;"	d
+RG_TURISMO_TRX_DP_FODIV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16923;"	d
+RG_TURISMO_TRX_DP_FODIV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16925;"	d
+RG_TURISMO_TRX_DP_FREF_DOUB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16889;"	d
+RG_TURISMO_TRX_DP_FREF_DOUB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16887;"	d
+RG_TURISMO_TRX_DP_FREF_DOUB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16886;"	d
+RG_TURISMO_TRX_DP_FREF_DOUB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16888;"	d
+RG_TURISMO_TRX_DP_FREF_DOUB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16890;"	d
+RG_TURISMO_TRX_DP_LDO_LEVEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14999;"	d
+RG_TURISMO_TRX_DP_LDO_LEVEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14997;"	d
+RG_TURISMO_TRX_DP_LDO_LEVEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14996;"	d
+RG_TURISMO_TRX_DP_LDO_LEVEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14998;"	d
+RG_TURISMO_TRX_DP_LDO_LEVEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15000;"	d
+RG_TURISMO_TRX_DP_OD_TEST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16934;"	d
+RG_TURISMO_TRX_DP_OD_TEST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16932;"	d
+RG_TURISMO_TRX_DP_OD_TEST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16931;"	d
+RG_TURISMO_TRX_DP_OD_TEST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16933;"	d
+RG_TURISMO_TRX_DP_OD_TEST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16935;"	d
+RG_TURISMO_TRX_DP_PFD_PFDSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16964;"	d
+RG_TURISMO_TRX_DP_PFD_PFDSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16962;"	d
+RG_TURISMO_TRX_DP_PFD_PFDSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16961;"	d
+RG_TURISMO_TRX_DP_PFD_PFDSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16963;"	d
+RG_TURISMO_TRX_DP_PFD_PFDSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16965;"	d
+RG_TURISMO_TRX_DP_REFDIV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16919;"	d
+RG_TURISMO_TRX_DP_REFDIV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16917;"	d
+RG_TURISMO_TRX_DP_REFDIV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16916;"	d
+RG_TURISMO_TRX_DP_REFDIV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16918;"	d
+RG_TURISMO_TRX_DP_REFDIV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16920;"	d
+RG_TURISMO_TRX_DP_RHP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16979;"	d
+RG_TURISMO_TRX_DP_RHP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16977;"	d
+RG_TURISMO_TRX_DP_RHP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16976;"	d
+RG_TURISMO_TRX_DP_RHP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16978;"	d
+RG_TURISMO_TRX_DP_RHP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16980;"	d
+RG_TURISMO_TRX_DP_RP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16974;"	d
+RG_TURISMO_TRX_DP_RP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16972;"	d
+RG_TURISMO_TRX_DP_RP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16971;"	d
+RG_TURISMO_TRX_DP_RP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16973;"	d
+RG_TURISMO_TRX_DP_RP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16975;"	d
+RG_TURISMO_TRX_DP_VT_TH_HI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16989;"	d
+RG_TURISMO_TRX_DP_VT_TH_HI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16987;"	d
+RG_TURISMO_TRX_DP_VT_TH_HI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16986;"	d
+RG_TURISMO_TRX_DP_VT_TH_HI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16988;"	d
+RG_TURISMO_TRX_DP_VT_TH_HI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16990;"	d
+RG_TURISMO_TRX_DP_VT_TH_LO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16994;"	d
+RG_TURISMO_TRX_DP_VT_TH_LO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16992;"	d
+RG_TURISMO_TRX_DP_VT_TH_LO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16991;"	d
+RG_TURISMO_TRX_DP_VT_TH_LO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16993;"	d
+RG_TURISMO_TRX_DP_VT_TH_LO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16995;"	d
+RG_TURISMO_TRX_EN_AAC5GB_MXPDSW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19374;"	d
+RG_TURISMO_TRX_EN_AAC5GB_MXPDSW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19372;"	d
+RG_TURISMO_TRX_EN_AAC5GB_MXPDSW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19371;"	d
+RG_TURISMO_TRX_EN_AAC5GB_MXPDSW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19373;"	d
+RG_TURISMO_TRX_EN_AAC5GB_MXPDSW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19375;"	d
+RG_TURISMO_TRX_EN_AAC5GB_RPPDSW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19379;"	d
+RG_TURISMO_TRX_EN_AAC5GB_RPPDSW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19377;"	d
+RG_TURISMO_TRX_EN_AAC5GB_RPPDSW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19376;"	d
+RG_TURISMO_TRX_EN_AAC5GB_RPPDSW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19378;"	d
+RG_TURISMO_TRX_EN_AAC5GB_RPPDSW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19380;"	d
+RG_TURISMO_TRX_EN_AAC5GB_VOPDSW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19369;"	d
+RG_TURISMO_TRX_EN_AAC5GB_VOPDSW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19367;"	d
+RG_TURISMO_TRX_EN_AAC5GB_VOPDSW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19366;"	d
+RG_TURISMO_TRX_EN_AAC5GB_VOPDSW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19368;"	d
+RG_TURISMO_TRX_EN_AAC5GB_VOPDSW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19370;"	d
+RG_TURISMO_TRX_EN_DLDO_BYP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20684;"	d
+RG_TURISMO_TRX_EN_DLDO_BYP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20682;"	d
+RG_TURISMO_TRX_EN_DLDO_BYP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20681;"	d
+RG_TURISMO_TRX_EN_DLDO_BYP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20683;"	d
+RG_TURISMO_TRX_EN_DLDO_BYP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20685;"	d
+RG_TURISMO_TRX_EN_DPL_MOD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16909;"	d
+RG_TURISMO_TRX_EN_DPL_MOD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16907;"	d
+RG_TURISMO_TRX_EN_DPL_MOD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16906;"	d
+RG_TURISMO_TRX_EN_DPL_MOD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16908;"	d
+RG_TURISMO_TRX_EN_DPL_MOD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16910;"	d
+RG_TURISMO_TRX_EN_DP_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16884;"	d
+RG_TURISMO_TRX_EN_DP_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16882;"	d
+RG_TURISMO_TRX_EN_DP_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16881;"	d
+RG_TURISMO_TRX_EN_DP_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16883;"	d
+RG_TURISMO_TRX_EN_DP_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16885;"	d
+RG_TURISMO_TRX_EN_DP_VT_MON_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16984;"	d
+RG_TURISMO_TRX_EN_DP_VT_MON_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16982;"	d
+RG_TURISMO_TRX_EN_DP_VT_MON_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16981;"	d
+RG_TURISMO_TRX_EN_DP_VT_MON_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16983;"	d
+RG_TURISMO_TRX_EN_DP_VT_MON_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16985;"	d
+RG_TURISMO_TRX_EN_FDB_DCC_MUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20719;"	d
+RG_TURISMO_TRX_EN_FDB_DCC_MUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20717;"	d
+RG_TURISMO_TRX_EN_FDB_DCC_MUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20716;"	d
+RG_TURISMO_TRX_EN_FDB_DCC_MUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20718;"	d
+RG_TURISMO_TRX_EN_FDB_DCC_MUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20720;"	d
+RG_TURISMO_TRX_EN_FDB_DELAYC_MUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20724;"	d
+RG_TURISMO_TRX_EN_FDB_DELAYC_MUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20722;"	d
+RG_TURISMO_TRX_EN_FDB_DELAYC_MUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20721;"	d
+RG_TURISMO_TRX_EN_FDB_DELAYC_MUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20723;"	d
+RG_TURISMO_TRX_EN_FDB_DELAYC_MUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20725;"	d
+RG_TURISMO_TRX_EN_FDB_DELAYF_MUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20729;"	d
+RG_TURISMO_TRX_EN_FDB_DELAYF_MUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20727;"	d
+RG_TURISMO_TRX_EN_FDB_DELAYF_MUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20726;"	d
+RG_TURISMO_TRX_EN_FDB_DELAYF_MUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20728;"	d
+RG_TURISMO_TRX_EN_FDB_DELAYF_MUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20730;"	d
+RG_TURISMO_TRX_EN_FDB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20699;"	d
+RG_TURISMO_TRX_EN_FDB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20697;"	d
+RG_TURISMO_TRX_EN_FDB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20696;"	d
+RG_TURISMO_TRX_EN_FDB_PHASESWAP_MUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20734;"	d
+RG_TURISMO_TRX_EN_FDB_PHASESWAP_MUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20732;"	d
+RG_TURISMO_TRX_EN_FDB_PHASESWAP_MUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20731;"	d
+RG_TURISMO_TRX_EN_FDB_PHASESWAP_MUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20733;"	d
+RG_TURISMO_TRX_EN_FDB_PHASESWAP_MUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20735;"	d
+RG_TURISMO_TRX_EN_FDB_RECAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20779;"	d
+RG_TURISMO_TRX_EN_FDB_RECAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20777;"	d
+RG_TURISMO_TRX_EN_FDB_RECAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20776;"	d
+RG_TURISMO_TRX_EN_FDB_RECAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20778;"	d
+RG_TURISMO_TRX_EN_FDB_RECAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20780;"	d
+RG_TURISMO_TRX_EN_FDB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20698;"	d
+RG_TURISMO_TRX_EN_FDB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20700;"	d
+RG_TURISMO_TRX_EN_HSDIV_OBF_MX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18824;"	d
+RG_TURISMO_TRX_EN_HSDIV_OBF_MX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18822;"	d
+RG_TURISMO_TRX_EN_HSDIV_OBF_MX_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18819;"	d
+RG_TURISMO_TRX_EN_HSDIV_OBF_MX_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18817;"	d
+RG_TURISMO_TRX_EN_HSDIV_OBF_MX_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18816;"	d
+RG_TURISMO_TRX_EN_HSDIV_OBF_MX_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18818;"	d
+RG_TURISMO_TRX_EN_HSDIV_OBF_MX_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18820;"	d
+RG_TURISMO_TRX_EN_HSDIV_OBF_MX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18821;"	d
+RG_TURISMO_TRX_EN_HSDIV_OBF_MX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18823;"	d
+RG_TURISMO_TRX_EN_HSDIV_OBF_MX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18825;"	d
+RG_TURISMO_TRX_EN_HSDIV_OBF_SX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18814;"	d
+RG_TURISMO_TRX_EN_HSDIV_OBF_SX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18812;"	d
+RG_TURISMO_TRX_EN_HSDIV_OBF_SX_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18809;"	d
+RG_TURISMO_TRX_EN_HSDIV_OBF_SX_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18807;"	d
+RG_TURISMO_TRX_EN_HSDIV_OBF_SX_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18806;"	d
+RG_TURISMO_TRX_EN_HSDIV_OBF_SX_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18808;"	d
+RG_TURISMO_TRX_EN_HSDIV_OBF_SX_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18810;"	d
+RG_TURISMO_TRX_EN_HSDIV_OBF_SX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18811;"	d
+RG_TURISMO_TRX_EN_HSDIV_OBF_SX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18813;"	d
+RG_TURISMO_TRX_EN_HSDIV_OBF_SX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18815;"	d
+RG_TURISMO_TRX_EN_IOT_ADC_BUF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14824;"	d
+RG_TURISMO_TRX_EN_IOT_ADC_BUF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14822;"	d
+RG_TURISMO_TRX_EN_IOT_ADC_BUF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14821;"	d
+RG_TURISMO_TRX_EN_IOT_ADC_BUF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14823;"	d
+RG_TURISMO_TRX_EN_IOT_ADC_BUF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14825;"	d
+RG_TURISMO_TRX_EN_IOT_ADC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14829;"	d
+RG_TURISMO_TRX_EN_IOT_ADC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14827;"	d
+RG_TURISMO_TRX_EN_IOT_ADC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14826;"	d
+RG_TURISMO_TRX_EN_IOT_ADC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14828;"	d
+RG_TURISMO_TRX_EN_IOT_ADC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14830;"	d
+RG_TURISMO_TRX_EN_IREF_RX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14844;"	d
+RG_TURISMO_TRX_EN_IREF_RX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14842;"	d
+RG_TURISMO_TRX_EN_IREF_RX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14841;"	d
+RG_TURISMO_TRX_EN_IREF_RX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14843;"	d
+RG_TURISMO_TRX_EN_IREF_RX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14845;"	d
+RG_TURISMO_TRX_EN_LDO_5G_CP_BYP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18179;"	d
+RG_TURISMO_TRX_EN_LDO_5G_CP_BYP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18177;"	d
+RG_TURISMO_TRX_EN_LDO_5G_CP_BYP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18176;"	d
+RG_TURISMO_TRX_EN_LDO_5G_CP_BYP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18178;"	d
+RG_TURISMO_TRX_EN_LDO_5G_CP_BYP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18180;"	d
+RG_TURISMO_TRX_EN_LDO_5G_CP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18894;"	d
+RG_TURISMO_TRX_EN_LDO_5G_CP_IQUP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18924;"	d
+RG_TURISMO_TRX_EN_LDO_5G_CP_IQUP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18922;"	d
+RG_TURISMO_TRX_EN_LDO_5G_CP_IQUP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18921;"	d
+RG_TURISMO_TRX_EN_LDO_5G_CP_IQUP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18923;"	d
+RG_TURISMO_TRX_EN_LDO_5G_CP_IQUP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18925;"	d
+RG_TURISMO_TRX_EN_LDO_5G_CP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18892;"	d
+RG_TURISMO_TRX_EN_LDO_5G_CP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18891;"	d
+RG_TURISMO_TRX_EN_LDO_5G_CP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18893;"	d
+RG_TURISMO_TRX_EN_LDO_5G_CP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18895;"	d
+RG_TURISMO_TRX_EN_LDO_5G_DIV_BYP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18204;"	d
+RG_TURISMO_TRX_EN_LDO_5G_DIV_BYP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18202;"	d
+RG_TURISMO_TRX_EN_LDO_5G_DIV_BYP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18201;"	d
+RG_TURISMO_TRX_EN_LDO_5G_DIV_BYP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18203;"	d
+RG_TURISMO_TRX_EN_LDO_5G_DIV_BYP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18205;"	d
+RG_TURISMO_TRX_EN_LDO_5G_DIV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18899;"	d
+RG_TURISMO_TRX_EN_LDO_5G_DIV_IQUP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18929;"	d
+RG_TURISMO_TRX_EN_LDO_5G_DIV_IQUP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18927;"	d
+RG_TURISMO_TRX_EN_LDO_5G_DIV_IQUP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18926;"	d
+RG_TURISMO_TRX_EN_LDO_5G_DIV_IQUP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18928;"	d
+RG_TURISMO_TRX_EN_LDO_5G_DIV_IQUP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18930;"	d
+RG_TURISMO_TRX_EN_LDO_5G_DIV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18897;"	d
+RG_TURISMO_TRX_EN_LDO_5G_DIV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18896;"	d
+RG_TURISMO_TRX_EN_LDO_5G_DIV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18898;"	d
+RG_TURISMO_TRX_EN_LDO_5G_DIV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18900;"	d
+RG_TURISMO_TRX_EN_LDO_5G_LO_BYP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18189;"	d
+RG_TURISMO_TRX_EN_LDO_5G_LO_BYP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18187;"	d
+RG_TURISMO_TRX_EN_LDO_5G_LO_BYP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18186;"	d
+RG_TURISMO_TRX_EN_LDO_5G_LO_BYP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18188;"	d
+RG_TURISMO_TRX_EN_LDO_5G_LO_BYP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18190;"	d
+RG_TURISMO_TRX_EN_LDO_5G_LO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18904;"	d
+RG_TURISMO_TRX_EN_LDO_5G_LO_IQUP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18934;"	d
+RG_TURISMO_TRX_EN_LDO_5G_LO_IQUP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18932;"	d
+RG_TURISMO_TRX_EN_LDO_5G_LO_IQUP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18931;"	d
+RG_TURISMO_TRX_EN_LDO_5G_LO_IQUP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18933;"	d
+RG_TURISMO_TRX_EN_LDO_5G_LO_IQUP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18935;"	d
+RG_TURISMO_TRX_EN_LDO_5G_LO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18902;"	d
+RG_TURISMO_TRX_EN_LDO_5G_LO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18901;"	d
+RG_TURISMO_TRX_EN_LDO_5G_LO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18903;"	d
+RG_TURISMO_TRX_EN_LDO_5G_LO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18905;"	d
+RG_TURISMO_TRX_EN_LDO_5G_VCO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18909;"	d
+RG_TURISMO_TRX_EN_LDO_5G_VCO_IQUP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18939;"	d
+RG_TURISMO_TRX_EN_LDO_5G_VCO_IQUP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18937;"	d
+RG_TURISMO_TRX_EN_LDO_5G_VCO_IQUP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18936;"	d
+RG_TURISMO_TRX_EN_LDO_5G_VCO_IQUP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18938;"	d
+RG_TURISMO_TRX_EN_LDO_5G_VCO_IQUP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18940;"	d
+RG_TURISMO_TRX_EN_LDO_5G_VCO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18907;"	d
+RG_TURISMO_TRX_EN_LDO_5G_VCO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18906;"	d
+RG_TURISMO_TRX_EN_LDO_5G_VCO_PSW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18914;"	d
+RG_TURISMO_TRX_EN_LDO_5G_VCO_PSW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18912;"	d
+RG_TURISMO_TRX_EN_LDO_5G_VCO_PSW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18911;"	d
+RG_TURISMO_TRX_EN_LDO_5G_VCO_PSW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18913;"	d
+RG_TURISMO_TRX_EN_LDO_5G_VCO_PSW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18915;"	d
+RG_TURISMO_TRX_EN_LDO_5G_VCO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18908;"	d
+RG_TURISMO_TRX_EN_LDO_5G_VCO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18910;"	d
+RG_TURISMO_TRX_EN_LDO_5G_VCO_VDD33_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18919;"	d
+RG_TURISMO_TRX_EN_LDO_5G_VCO_VDD33_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18917;"	d
+RG_TURISMO_TRX_EN_LDO_5G_VCO_VDD33_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18916;"	d
+RG_TURISMO_TRX_EN_LDO_5G_VCO_VDD33_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18918;"	d
+RG_TURISMO_TRX_EN_LDO_5G_VCO_VDD33_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18920;"	d
+RG_TURISMO_TRX_EN_LDO_AFE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14839;"	d
+RG_TURISMO_TRX_EN_LDO_AFE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14837;"	d
+RG_TURISMO_TRX_EN_LDO_AFE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14836;"	d
+RG_TURISMO_TRX_EN_LDO_AFE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14838;"	d
+RG_TURISMO_TRX_EN_LDO_AFE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14840;"	d
+RG_TURISMO_TRX_EN_LDO_CP_BYP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15014;"	d
+RG_TURISMO_TRX_EN_LDO_CP_BYP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15012;"	d
+RG_TURISMO_TRX_EN_LDO_CP_BYP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15011;"	d
+RG_TURISMO_TRX_EN_LDO_CP_BYP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15013;"	d
+RG_TURISMO_TRX_EN_LDO_CP_BYP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15015;"	d
+RG_TURISMO_TRX_EN_LDO_CP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16269;"	d
+RG_TURISMO_TRX_EN_LDO_CP_IQUP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16299;"	d
+RG_TURISMO_TRX_EN_LDO_CP_IQUP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16297;"	d
+RG_TURISMO_TRX_EN_LDO_CP_IQUP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16296;"	d
+RG_TURISMO_TRX_EN_LDO_CP_IQUP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16298;"	d
+RG_TURISMO_TRX_EN_LDO_CP_IQUP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16300;"	d
+RG_TURISMO_TRX_EN_LDO_CP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16267;"	d
+RG_TURISMO_TRX_EN_LDO_CP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16266;"	d
+RG_TURISMO_TRX_EN_LDO_CP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16268;"	d
+RG_TURISMO_TRX_EN_LDO_CP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16270;"	d
+RG_TURISMO_TRX_EN_LDO_DIV_BYP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15039;"	d
+RG_TURISMO_TRX_EN_LDO_DIV_BYP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15037;"	d
+RG_TURISMO_TRX_EN_LDO_DIV_BYP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15036;"	d
+RG_TURISMO_TRX_EN_LDO_DIV_BYP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15038;"	d
+RG_TURISMO_TRX_EN_LDO_DIV_BYP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15040;"	d
+RG_TURISMO_TRX_EN_LDO_DIV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16274;"	d
+RG_TURISMO_TRX_EN_LDO_DIV_IQUP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16304;"	d
+RG_TURISMO_TRX_EN_LDO_DIV_IQUP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16302;"	d
+RG_TURISMO_TRX_EN_LDO_DIV_IQUP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16301;"	d
+RG_TURISMO_TRX_EN_LDO_DIV_IQUP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16303;"	d
+RG_TURISMO_TRX_EN_LDO_DIV_IQUP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16305;"	d
+RG_TURISMO_TRX_EN_LDO_DIV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16272;"	d
+RG_TURISMO_TRX_EN_LDO_DIV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16271;"	d
+RG_TURISMO_TRX_EN_LDO_DIV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16273;"	d
+RG_TURISMO_TRX_EN_LDO_DIV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16275;"	d
+RG_TURISMO_TRX_EN_LDO_DP_BYP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15004;"	d
+RG_TURISMO_TRX_EN_LDO_DP_BYP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15002;"	d
+RG_TURISMO_TRX_EN_LDO_DP_BYP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15001;"	d
+RG_TURISMO_TRX_EN_LDO_DP_BYP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15003;"	d
+RG_TURISMO_TRX_EN_LDO_DP_BYP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15005;"	d
+RG_TURISMO_TRX_EN_LDO_DP_IQUP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16929;"	d
+RG_TURISMO_TRX_EN_LDO_DP_IQUP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16927;"	d
+RG_TURISMO_TRX_EN_LDO_DP_IQUP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16926;"	d
+RG_TURISMO_TRX_EN_LDO_DP_IQUP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16928;"	d
+RG_TURISMO_TRX_EN_LDO_DP_IQUP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16930;"	d
+RG_TURISMO_TRX_EN_LDO_EFUSE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20829;"	d
+RG_TURISMO_TRX_EN_LDO_EFUSE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20827;"	d
+RG_TURISMO_TRX_EN_LDO_EFUSE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20826;"	d
+RG_TURISMO_TRX_EN_LDO_EFUSE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20828;"	d
+RG_TURISMO_TRX_EN_LDO_EFUSE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20830;"	d
+RG_TURISMO_TRX_EN_LDO_LO_BYP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15024;"	d
+RG_TURISMO_TRX_EN_LDO_LO_BYP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15022;"	d
+RG_TURISMO_TRX_EN_LDO_LO_BYP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15021;"	d
+RG_TURISMO_TRX_EN_LDO_LO_BYP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15023;"	d
+RG_TURISMO_TRX_EN_LDO_LO_BYP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15025;"	d
+RG_TURISMO_TRX_EN_LDO_LO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16279;"	d
+RG_TURISMO_TRX_EN_LDO_LO_IQUP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16309;"	d
+RG_TURISMO_TRX_EN_LDO_LO_IQUP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16307;"	d
+RG_TURISMO_TRX_EN_LDO_LO_IQUP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16306;"	d
+RG_TURISMO_TRX_EN_LDO_LO_IQUP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16308;"	d
+RG_TURISMO_TRX_EN_LDO_LO_IQUP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16310;"	d
+RG_TURISMO_TRX_EN_LDO_LO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16277;"	d
+RG_TURISMO_TRX_EN_LDO_LO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16276;"	d
+RG_TURISMO_TRX_EN_LDO_LO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16278;"	d
+RG_TURISMO_TRX_EN_LDO_LO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16280;"	d
+RG_TURISMO_TRX_EN_LDO_RX_AFE_BYP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14989;"	d
+RG_TURISMO_TRX_EN_LDO_RX_AFE_BYP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14987;"	d
+RG_TURISMO_TRX_EN_LDO_RX_AFE_BYP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14986;"	d
+RG_TURISMO_TRX_EN_LDO_RX_AFE_BYP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14988;"	d
+RG_TURISMO_TRX_EN_LDO_RX_AFE_BYP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14990;"	d
+RG_TURISMO_TRX_EN_LDO_RX_AFE_FC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14954;"	d
+RG_TURISMO_TRX_EN_LDO_RX_AFE_FC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14952;"	d
+RG_TURISMO_TRX_EN_LDO_RX_AFE_FC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14951;"	d
+RG_TURISMO_TRX_EN_LDO_RX_AFE_FC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14953;"	d
+RG_TURISMO_TRX_EN_LDO_RX_AFE_FC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14955;"	d
+RG_TURISMO_TRX_EN_LDO_RX_AFE_IQUP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14964;"	d
+RG_TURISMO_TRX_EN_LDO_RX_AFE_IQUP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14962;"	d
+RG_TURISMO_TRX_EN_LDO_RX_AFE_IQUP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14961;"	d
+RG_TURISMO_TRX_EN_LDO_RX_AFE_IQUP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14963;"	d
+RG_TURISMO_TRX_EN_LDO_RX_AFE_IQUP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14965;"	d
+RG_TURISMO_TRX_EN_LDO_RX_FE_BYP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14979;"	d
+RG_TURISMO_TRX_EN_LDO_RX_FE_BYP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14977;"	d
+RG_TURISMO_TRX_EN_LDO_RX_FE_BYP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14976;"	d
+RG_TURISMO_TRX_EN_LDO_RX_FE_BYP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14978;"	d
+RG_TURISMO_TRX_EN_LDO_RX_FE_BYP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14980;"	d
+RG_TURISMO_TRX_EN_LDO_RX_FE_FC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14949;"	d
+RG_TURISMO_TRX_EN_LDO_RX_FE_FC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14947;"	d
+RG_TURISMO_TRX_EN_LDO_RX_FE_FC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14946;"	d
+RG_TURISMO_TRX_EN_LDO_RX_FE_FC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14948;"	d
+RG_TURISMO_TRX_EN_LDO_RX_FE_FC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14950;"	d
+RG_TURISMO_TRX_EN_LDO_RX_FE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14834;"	d
+RG_TURISMO_TRX_EN_LDO_RX_FE_IQUP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14959;"	d
+RG_TURISMO_TRX_EN_LDO_RX_FE_IQUP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14957;"	d
+RG_TURISMO_TRX_EN_LDO_RX_FE_IQUP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14956;"	d
+RG_TURISMO_TRX_EN_LDO_RX_FE_IQUP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14958;"	d
+RG_TURISMO_TRX_EN_LDO_RX_FE_IQUP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14960;"	d
+RG_TURISMO_TRX_EN_LDO_RX_FE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14832;"	d
+RG_TURISMO_TRX_EN_LDO_RX_FE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14831;"	d
+RG_TURISMO_TRX_EN_LDO_RX_FE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14833;"	d
+RG_TURISMO_TRX_EN_LDO_RX_FE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14835;"	d
+RG_TURISMO_TRX_EN_LDO_TX_PA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15364;"	d
+RG_TURISMO_TRX_EN_LDO_TX_PA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15362;"	d
+RG_TURISMO_TRX_EN_LDO_TX_PA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15361;"	d
+RG_TURISMO_TRX_EN_LDO_TX_PA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15363;"	d
+RG_TURISMO_TRX_EN_LDO_TX_PA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15365;"	d
+RG_TURISMO_TRX_EN_LDO_VCO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16284;"	d
+RG_TURISMO_TRX_EN_LDO_VCO_IQUP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16314;"	d
+RG_TURISMO_TRX_EN_LDO_VCO_IQUP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16312;"	d
+RG_TURISMO_TRX_EN_LDO_VCO_IQUP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16311;"	d
+RG_TURISMO_TRX_EN_LDO_VCO_IQUP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16313;"	d
+RG_TURISMO_TRX_EN_LDO_VCO_IQUP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16315;"	d
+RG_TURISMO_TRX_EN_LDO_VCO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16282;"	d
+RG_TURISMO_TRX_EN_LDO_VCO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16281;"	d
+RG_TURISMO_TRX_EN_LDO_VCO_PSW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16289;"	d
+RG_TURISMO_TRX_EN_LDO_VCO_PSW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16287;"	d
+RG_TURISMO_TRX_EN_LDO_VCO_PSW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16286;"	d
+RG_TURISMO_TRX_EN_LDO_VCO_PSW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16288;"	d
+RG_TURISMO_TRX_EN_LDO_VCO_PSW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16290;"	d
+RG_TURISMO_TRX_EN_LDO_VCO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16283;"	d
+RG_TURISMO_TRX_EN_LDO_VCO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16285;"	d
+RG_TURISMO_TRX_EN_LDO_VCO_VDD33_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16294;"	d
+RG_TURISMO_TRX_EN_LDO_VCO_VDD33_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16292;"	d
+RG_TURISMO_TRX_EN_LDO_VCO_VDD33_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16291;"	d
+RG_TURISMO_TRX_EN_LDO_VCO_VDD33_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16293;"	d
+RG_TURISMO_TRX_EN_LDO_VCO_VDD33_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16295;"	d
+RG_TURISMO_TRX_EN_LDO_XO_BYP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20679;"	d
+RG_TURISMO_TRX_EN_LDO_XO_BYP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20677;"	d
+RG_TURISMO_TRX_EN_LDO_XO_BYP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20676;"	d
+RG_TURISMO_TRX_EN_LDO_XO_BYP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20678;"	d
+RG_TURISMO_TRX_EN_LDO_XO_BYP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20680;"	d
+RG_TURISMO_TRX_EN_LDO_XO_IQUP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20674;"	d
+RG_TURISMO_TRX_EN_LDO_XO_IQUP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20672;"	d
+RG_TURISMO_TRX_EN_LDO_XO_IQUP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20671;"	d
+RG_TURISMO_TRX_EN_LDO_XO_IQUP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20673;"	d
+RG_TURISMO_TRX_EN_LDO_XO_IQUP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20675;"	d
+RG_TURISMO_TRX_EN_RTC_CAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20904;"	d
+RG_TURISMO_TRX_EN_RTC_CAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20902;"	d
+RG_TURISMO_TRX_EN_RTC_CAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20901;"	d
+RG_TURISMO_TRX_EN_RTC_CAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20903;"	d
+RG_TURISMO_TRX_EN_RTC_CAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20905;"	d
+RG_TURISMO_TRX_EN_RX_ADC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14749;"	d
+RG_TURISMO_TRX_EN_RX_ADC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14747;"	d
+RG_TURISMO_TRX_EN_RX_ADC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14746;"	d
+RG_TURISMO_TRX_EN_RX_ADC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14748;"	d
+RG_TURISMO_TRX_EN_RX_ADC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14750;"	d
+RG_TURISMO_TRX_EN_RX_DIV2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14709;"	d
+RG_TURISMO_TRX_EN_RX_DIV2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14707;"	d
+RG_TURISMO_TRX_EN_RX_DIV2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14706;"	d
+RG_TURISMO_TRX_EN_RX_DIV2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14708;"	d
+RG_TURISMO_TRX_EN_RX_DIV2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14710;"	d
+RG_TURISMO_TRX_EN_RX_FILTER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14739;"	d
+RG_TURISMO_TRX_EN_RX_FILTER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14737;"	d
+RG_TURISMO_TRX_EN_RX_FILTER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14736;"	d
+RG_TURISMO_TRX_EN_RX_FILTER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14738;"	d
+RG_TURISMO_TRX_EN_RX_FILTER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14740;"	d
+RG_TURISMO_TRX_EN_RX_IQCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14884;"	d
+RG_TURISMO_TRX_EN_RX_IQCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14882;"	d
+RG_TURISMO_TRX_EN_RX_IQCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14881;"	d
+RG_TURISMO_TRX_EN_RX_IQCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14883;"	d
+RG_TURISMO_TRX_EN_RX_IQCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14885;"	d
+RG_TURISMO_TRX_EN_RX_LNA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14689;"	d
+RG_TURISMO_TRX_EN_RX_LNA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14687;"	d
+RG_TURISMO_TRX_EN_RX_LNA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14686;"	d
+RG_TURISMO_TRX_EN_RX_LNA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14688;"	d
+RG_TURISMO_TRX_EN_RX_LNA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14690;"	d
+RG_TURISMO_TRX_EN_RX_LOBUF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14719;"	d
+RG_TURISMO_TRX_EN_RX_LOBUF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14717;"	d
+RG_TURISMO_TRX_EN_RX_LOBUF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14716;"	d
+RG_TURISMO_TRX_EN_RX_LOBUF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14718;"	d
+RG_TURISMO_TRX_EN_RX_LOBUF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14720;"	d
+RG_TURISMO_TRX_EN_RX_MIXER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14699;"	d
+RG_TURISMO_TRX_EN_RX_MIXER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14697;"	d
+RG_TURISMO_TRX_EN_RX_MIXER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14696;"	d
+RG_TURISMO_TRX_EN_RX_MIXER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14698;"	d
+RG_TURISMO_TRX_EN_RX_MIXER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14700;"	d
+RG_TURISMO_TRX_EN_RX_PADSW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14944;"	d
+RG_TURISMO_TRX_EN_RX_PADSW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14942;"	d
+RG_TURISMO_TRX_EN_RX_PADSW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14941;"	d
+RG_TURISMO_TRX_EN_RX_PADSW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14943;"	d
+RG_TURISMO_TRX_EN_RX_PADSW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14945;"	d
+RG_TURISMO_TRX_EN_RX_RSSI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14759;"	d
+RG_TURISMO_TRX_EN_RX_RSSI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14757;"	d
+RG_TURISMO_TRX_EN_RX_RSSI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14756;"	d
+RG_TURISMO_TRX_EN_RX_RSSI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14758;"	d
+RG_TURISMO_TRX_EN_RX_RSSI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14760;"	d
+RG_TURISMO_TRX_EN_RX_RSSI_TESTNODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15294;"	d
+RG_TURISMO_TRX_EN_RX_RSSI_TESTNODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15292;"	d
+RG_TURISMO_TRX_EN_RX_RSSI_TESTNODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15291;"	d
+RG_TURISMO_TRX_EN_RX_RSSI_TESTNODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15293;"	d
+RG_TURISMO_TRX_EN_RX_RSSI_TESTNODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15295;"	d
+RG_TURISMO_TRX_EN_RX_TESTNODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14939;"	d
+RG_TURISMO_TRX_EN_RX_TESTNODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14937;"	d
+RG_TURISMO_TRX_EN_RX_TESTNODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14936;"	d
+RG_TURISMO_TRX_EN_RX_TESTNODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14938;"	d
+RG_TURISMO_TRX_EN_RX_TESTNODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14940;"	d
+RG_TURISMO_TRX_EN_RX_TZ_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14729;"	d
+RG_TURISMO_TRX_EN_RX_TZ_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14727;"	d
+RG_TURISMO_TRX_EN_RX_TZ_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14726;"	d
+RG_TURISMO_TRX_EN_RX_TZ_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14728;"	d
+RG_TURISMO_TRX_EN_RX_TZ_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14730;"	d
+RG_TURISMO_TRX_EN_SARADC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14904;"	d
+RG_TURISMO_TRX_EN_SARADC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14902;"	d
+RG_TURISMO_TRX_EN_SARADC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14901;"	d
+RG_TURISMO_TRX_EN_SARADC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14903;"	d
+RG_TURISMO_TRX_EN_SARADC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14905;"	d
+RG_TURISMO_TRX_EN_SAR_TEST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15984;"	d
+RG_TURISMO_TRX_EN_SAR_TEST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15982;"	d
+RG_TURISMO_TRX_EN_SAR_TEST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15981;"	d
+RG_TURISMO_TRX_EN_SAR_TEST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15983;"	d
+RG_TURISMO_TRX_EN_SAR_TEST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15985;"	d
+RG_TURISMO_TRX_EN_SX5GB_CP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18754;"	d
+RG_TURISMO_TRX_EN_SX5GB_CP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18752;"	d
+RG_TURISMO_TRX_EN_SX5GB_CP_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18749;"	d
+RG_TURISMO_TRX_EN_SX5GB_CP_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18747;"	d
+RG_TURISMO_TRX_EN_SX5GB_CP_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18746;"	d
+RG_TURISMO_TRX_EN_SX5GB_CP_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18748;"	d
+RG_TURISMO_TRX_EN_SX5GB_CP_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18750;"	d
+RG_TURISMO_TRX_EN_SX5GB_CP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18751;"	d
+RG_TURISMO_TRX_EN_SX5GB_CP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18753;"	d
+RG_TURISMO_TRX_EN_SX5GB_CP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18755;"	d
+RG_TURISMO_TRX_EN_SX5GB_DITHER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19249;"	d
+RG_TURISMO_TRX_EN_SX5GB_DITHER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19247;"	d
+RG_TURISMO_TRX_EN_SX5GB_DITHER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19246;"	d
+RG_TURISMO_TRX_EN_SX5GB_DITHER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19248;"	d
+RG_TURISMO_TRX_EN_SX5GB_DITHER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19250;"	d
+RG_TURISMO_TRX_EN_SX5GB_DIV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18764;"	d
+RG_TURISMO_TRX_EN_SX5GB_DIV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18762;"	d
+RG_TURISMO_TRX_EN_SX5GB_DIV_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18759;"	d
+RG_TURISMO_TRX_EN_SX5GB_DIV_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18757;"	d
+RG_TURISMO_TRX_EN_SX5GB_DIV_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18756;"	d
+RG_TURISMO_TRX_EN_SX5GB_DIV_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18758;"	d
+RG_TURISMO_TRX_EN_SX5GB_DIV_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18760;"	d
+RG_TURISMO_TRX_EN_SX5GB_DIV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18761;"	d
+RG_TURISMO_TRX_EN_SX5GB_DIV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18763;"	d
+RG_TURISMO_TRX_EN_SX5GB_DIV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18765;"	d
+RG_TURISMO_TRX_EN_SX5GB_HSDIV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18804;"	d
+RG_TURISMO_TRX_EN_SX5GB_HSDIV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18802;"	d
+RG_TURISMO_TRX_EN_SX5GB_HSDIV_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18799;"	d
+RG_TURISMO_TRX_EN_SX5GB_HSDIV_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18797;"	d
+RG_TURISMO_TRX_EN_SX5GB_HSDIV_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18796;"	d
+RG_TURISMO_TRX_EN_SX5GB_HSDIV_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18798;"	d
+RG_TURISMO_TRX_EN_SX5GB_HSDIV_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18800;"	d
+RG_TURISMO_TRX_EN_SX5GB_HSDIV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18801;"	d
+RG_TURISMO_TRX_EN_SX5GB_HSDIV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18803;"	d
+RG_TURISMO_TRX_EN_SX5GB_HSDIV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18805;"	d
+RG_TURISMO_TRX_EN_SX5GB_LDO_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18889;"	d
+RG_TURISMO_TRX_EN_SX5GB_LDO_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18887;"	d
+RG_TURISMO_TRX_EN_SX5GB_LDO_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18886;"	d
+RG_TURISMO_TRX_EN_SX5GB_LDO_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18888;"	d
+RG_TURISMO_TRX_EN_SX5GB_LDO_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18890;"	d
+RG_TURISMO_TRX_EN_SX5GB_MOD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19244;"	d
+RG_TURISMO_TRX_EN_SX5GB_MOD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19242;"	d
+RG_TURISMO_TRX_EN_SX5GB_MOD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19241;"	d
+RG_TURISMO_TRX_EN_SX5GB_MOD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19243;"	d
+RG_TURISMO_TRX_EN_SX5GB_MOD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19245;"	d
+RG_TURISMO_TRX_EN_SX5GB_VCOMON_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19214;"	d
+RG_TURISMO_TRX_EN_SX5GB_VCOMON_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19212;"	d
+RG_TURISMO_TRX_EN_SX5GB_VCOMON_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19211;"	d
+RG_TURISMO_TRX_EN_SX5GB_VCOMON_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19213;"	d
+RG_TURISMO_TRX_EN_SX5GB_VCOMON_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19215;"	d
+RG_TURISMO_TRX_EN_SX5GB_VCO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18774;"	d
+RG_TURISMO_TRX_EN_SX5GB_VCO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18772;"	d
+RG_TURISMO_TRX_EN_SX5GB_VCO_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18769;"	d
+RG_TURISMO_TRX_EN_SX5GB_VCO_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18767;"	d
+RG_TURISMO_TRX_EN_SX5GB_VCO_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18766;"	d
+RG_TURISMO_TRX_EN_SX5GB_VCO_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18768;"	d
+RG_TURISMO_TRX_EN_SX5GB_VCO_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18770;"	d
+RG_TURISMO_TRX_EN_SX5GB_VCO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18771;"	d
+RG_TURISMO_TRX_EN_SX5GB_VCO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18773;"	d
+RG_TURISMO_TRX_EN_SX5GB_VCO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18775;"	d
+RG_TURISMO_TRX_EN_SX_CP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16144;"	d
+RG_TURISMO_TRX_EN_SX_CP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16142;"	d
+RG_TURISMO_TRX_EN_SX_CP_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16139;"	d
+RG_TURISMO_TRX_EN_SX_CP_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16137;"	d
+RG_TURISMO_TRX_EN_SX_CP_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16136;"	d
+RG_TURISMO_TRX_EN_SX_CP_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16138;"	d
+RG_TURISMO_TRX_EN_SX_CP_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16140;"	d
+RG_TURISMO_TRX_EN_SX_CP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16141;"	d
+RG_TURISMO_TRX_EN_SX_CP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16143;"	d
+RG_TURISMO_TRX_EN_SX_CP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16145;"	d
+RG_TURISMO_TRX_EN_SX_DITHER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16709;"	d
+RG_TURISMO_TRX_EN_SX_DITHER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16707;"	d
+RG_TURISMO_TRX_EN_SX_DITHER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16706;"	d
+RG_TURISMO_TRX_EN_SX_DITHER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16708;"	d
+RG_TURISMO_TRX_EN_SX_DITHER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16710;"	d
+RG_TURISMO_TRX_EN_SX_DIV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16154;"	d
+RG_TURISMO_TRX_EN_SX_DIV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16152;"	d
+RG_TURISMO_TRX_EN_SX_DIV_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16149;"	d
+RG_TURISMO_TRX_EN_SX_DIV_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16147;"	d
+RG_TURISMO_TRX_EN_SX_DIV_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16146;"	d
+RG_TURISMO_TRX_EN_SX_DIV_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16148;"	d
+RG_TURISMO_TRX_EN_SX_DIV_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16150;"	d
+RG_TURISMO_TRX_EN_SX_DIV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16151;"	d
+RG_TURISMO_TRX_EN_SX_DIV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16153;"	d
+RG_TURISMO_TRX_EN_SX_DIV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16155;"	d
+RG_TURISMO_TRX_EN_SX_LDO_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16264;"	d
+RG_TURISMO_TRX_EN_SX_LDO_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16262;"	d
+RG_TURISMO_TRX_EN_SX_LDO_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16261;"	d
+RG_TURISMO_TRX_EN_SX_LDO_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16263;"	d
+RG_TURISMO_TRX_EN_SX_LDO_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16265;"	d
+RG_TURISMO_TRX_EN_SX_MIX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18834;"	d
+RG_TURISMO_TRX_EN_SX_MIX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18832;"	d
+RG_TURISMO_TRX_EN_SX_MIX_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18829;"	d
+RG_TURISMO_TRX_EN_SX_MIX_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18827;"	d
+RG_TURISMO_TRX_EN_SX_MIX_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18826;"	d
+RG_TURISMO_TRX_EN_SX_MIX_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18828;"	d
+RG_TURISMO_TRX_EN_SX_MIX_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18830;"	d
+RG_TURISMO_TRX_EN_SX_MIX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18831;"	d
+RG_TURISMO_TRX_EN_SX_MIX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18833;"	d
+RG_TURISMO_TRX_EN_SX_MIX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18835;"	d
+RG_TURISMO_TRX_EN_SX_MOD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16704;"	d
+RG_TURISMO_TRX_EN_SX_MOD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16702;"	d
+RG_TURISMO_TRX_EN_SX_MOD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16701;"	d
+RG_TURISMO_TRX_EN_SX_MOD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16703;"	d
+RG_TURISMO_TRX_EN_SX_MOD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16705;"	d
+RG_TURISMO_TRX_EN_SX_REP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18844;"	d
+RG_TURISMO_TRX_EN_SX_REP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18842;"	d
+RG_TURISMO_TRX_EN_SX_REP_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18839;"	d
+RG_TURISMO_TRX_EN_SX_REP_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18837;"	d
+RG_TURISMO_TRX_EN_SX_REP_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18836;"	d
+RG_TURISMO_TRX_EN_SX_REP_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18838;"	d
+RG_TURISMO_TRX_EN_SX_REP_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18840;"	d
+RG_TURISMO_TRX_EN_SX_REP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18841;"	d
+RG_TURISMO_TRX_EN_SX_REP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18843;"	d
+RG_TURISMO_TRX_EN_SX_REP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18845;"	d
+RG_TURISMO_TRX_EN_SX_VCOMON_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16674;"	d
+RG_TURISMO_TRX_EN_SX_VCOMON_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16672;"	d
+RG_TURISMO_TRX_EN_SX_VCOMON_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16671;"	d
+RG_TURISMO_TRX_EN_SX_VCOMON_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16673;"	d
+RG_TURISMO_TRX_EN_SX_VCOMON_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16675;"	d
+RG_TURISMO_TRX_EN_SX_VCO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16164;"	d
+RG_TURISMO_TRX_EN_SX_VCO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16162;"	d
+RG_TURISMO_TRX_EN_SX_VCO_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16159;"	d
+RG_TURISMO_TRX_EN_SX_VCO_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16157;"	d
+RG_TURISMO_TRX_EN_SX_VCO_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16156;"	d
+RG_TURISMO_TRX_EN_SX_VCO_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16158;"	d
+RG_TURISMO_TRX_EN_SX_VCO_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16160;"	d
+RG_TURISMO_TRX_EN_SX_VCO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16161;"	d
+RG_TURISMO_TRX_EN_SX_VCO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16163;"	d
+RG_TURISMO_TRX_EN_SX_VCO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16165;"	d
+RG_TURISMO_TRX_EN_TX_BT_PA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14819;"	d
+RG_TURISMO_TRX_EN_TX_BT_PA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14817;"	d
+RG_TURISMO_TRX_EN_TX_BT_PA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14816;"	d
+RG_TURISMO_TRX_EN_TX_BT_PA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14818;"	d
+RG_TURISMO_TRX_EN_TX_BT_PA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14820;"	d
+RG_TURISMO_TRX_EN_TX_DAC_CAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14854;"	d
+RG_TURISMO_TRX_EN_TX_DAC_CAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14852;"	d
+RG_TURISMO_TRX_EN_TX_DAC_CAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14851;"	d
+RG_TURISMO_TRX_EN_TX_DAC_CAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14853;"	d
+RG_TURISMO_TRX_EN_TX_DAC_CAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14855;"	d
+RG_TURISMO_TRX_EN_TX_DAC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14789;"	d
+RG_TURISMO_TRX_EN_TX_DAC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14787;"	d
+RG_TURISMO_TRX_EN_TX_DAC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14786;"	d
+RG_TURISMO_TRX_EN_TX_DAC_OUT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14924;"	d
+RG_TURISMO_TRX_EN_TX_DAC_OUT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14922;"	d
+RG_TURISMO_TRX_EN_TX_DAC_OUT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14921;"	d
+RG_TURISMO_TRX_EN_TX_DAC_OUT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14923;"	d
+RG_TURISMO_TRX_EN_TX_DAC_OUT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14925;"	d
+RG_TURISMO_TRX_EN_TX_DAC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14788;"	d
+RG_TURISMO_TRX_EN_TX_DAC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14790;"	d
+RG_TURISMO_TRX_EN_TX_DAC_VOUT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14929;"	d
+RG_TURISMO_TRX_EN_TX_DAC_VOUT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14927;"	d
+RG_TURISMO_TRX_EN_TX_DAC_VOUT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14926;"	d
+RG_TURISMO_TRX_EN_TX_DAC_VOUT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14928;"	d
+RG_TURISMO_TRX_EN_TX_DAC_VOUT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14930;"	d
+RG_TURISMO_TRX_EN_TX_DIV2_BUF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14809;"	d
+RG_TURISMO_TRX_EN_TX_DIV2_BUF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14807;"	d
+RG_TURISMO_TRX_EN_TX_DIV2_BUF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14806;"	d
+RG_TURISMO_TRX_EN_TX_DIV2_BUF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14808;"	d
+RG_TURISMO_TRX_EN_TX_DIV2_BUF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14810;"	d
+RG_TURISMO_TRX_EN_TX_DIV2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14799;"	d
+RG_TURISMO_TRX_EN_TX_DIV2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14797;"	d
+RG_TURISMO_TRX_EN_TX_DIV2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14796;"	d
+RG_TURISMO_TRX_EN_TX_DIV2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14798;"	d
+RG_TURISMO_TRX_EN_TX_DIV2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14800;"	d
+RG_TURISMO_TRX_EN_TX_DPD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14894;"	d
+RG_TURISMO_TRX_EN_TX_DPD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14892;"	d
+RG_TURISMO_TRX_EN_TX_DPD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14891;"	d
+RG_TURISMO_TRX_EN_TX_DPD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14893;"	d
+RG_TURISMO_TRX_EN_TX_DPD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14895;"	d
+RG_TURISMO_TRX_EN_TX_MOD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14779;"	d
+RG_TURISMO_TRX_EN_TX_MOD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14777;"	d
+RG_TURISMO_TRX_EN_TX_MOD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14776;"	d
+RG_TURISMO_TRX_EN_TX_MOD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14778;"	d
+RG_TURISMO_TRX_EN_TX_MOD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14780;"	d
+RG_TURISMO_TRX_EN_TX_PA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14769;"	d
+RG_TURISMO_TRX_EN_TX_PA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14767;"	d
+RG_TURISMO_TRX_EN_TX_PA_LDO_FC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15369;"	d
+RG_TURISMO_TRX_EN_TX_PA_LDO_FC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15367;"	d
+RG_TURISMO_TRX_EN_TX_PA_LDO_FC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15366;"	d
+RG_TURISMO_TRX_EN_TX_PA_LDO_FC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15368;"	d
+RG_TURISMO_TRX_EN_TX_PA_LDO_FC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15370;"	d
+RG_TURISMO_TRX_EN_TX_PA_LDO_IQUP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15374;"	d
+RG_TURISMO_TRX_EN_TX_PA_LDO_IQUP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15372;"	d
+RG_TURISMO_TRX_EN_TX_PA_LDO_IQUP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15371;"	d
+RG_TURISMO_TRX_EN_TX_PA_LDO_IQUP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15373;"	d
+RG_TURISMO_TRX_EN_TX_PA_LDO_IQUP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15375;"	d
+RG_TURISMO_TRX_EN_TX_PA_LDO_VTH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15379;"	d
+RG_TURISMO_TRX_EN_TX_PA_LDO_VTH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15377;"	d
+RG_TURISMO_TRX_EN_TX_PA_LDO_VTH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15376;"	d
+RG_TURISMO_TRX_EN_TX_PA_LDO_VTH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15378;"	d
+RG_TURISMO_TRX_EN_TX_PA_LDO_VTH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15380;"	d
+RG_TURISMO_TRX_EN_TX_PA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14766;"	d
+RG_TURISMO_TRX_EN_TX_PA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14768;"	d
+RG_TURISMO_TRX_EN_TX_PA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14770;"	d
+RG_TURISMO_TRX_EN_TX_SELF_MIXER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14874;"	d
+RG_TURISMO_TRX_EN_TX_SELF_MIXER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14872;"	d
+RG_TURISMO_TRX_EN_TX_SELF_MIXER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14871;"	d
+RG_TURISMO_TRX_EN_TX_SELF_MIXER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14873;"	d
+RG_TURISMO_TRX_EN_TX_SELF_MIXER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14875;"	d
+RG_TURISMO_TRX_EN_TX_TRSW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14679;"	d
+RG_TURISMO_TRX_EN_TX_TRSW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14677;"	d
+RG_TURISMO_TRX_EN_TX_TRSW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14676;"	d
+RG_TURISMO_TRX_EN_TX_TRSW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14678;"	d
+RG_TURISMO_TRX_EN_TX_TRSW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14680;"	d
+RG_TURISMO_TRX_EN_TX_TSSI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14899;"	d
+RG_TURISMO_TRX_EN_TX_TSSI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14897;"	d
+RG_TURISMO_TRX_EN_TX_TSSI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14896;"	d
+RG_TURISMO_TRX_EN_TX_TSSI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14898;"	d
+RG_TURISMO_TRX_EN_TX_TSSI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14900;"	d
+RG_TURISMO_TRX_EN_TX_VTOI_2ND_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14909;"	d
+RG_TURISMO_TRX_EN_TX_VTOI_2ND_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14907;"	d
+RG_TURISMO_TRX_EN_TX_VTOI_2ND_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14906;"	d
+RG_TURISMO_TRX_EN_TX_VTOI_2ND_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14908;"	d
+RG_TURISMO_TRX_EN_TX_VTOI_2ND_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14910;"	d
+RG_TURISMO_TRX_EN_VCOBF_DIVCK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16234;"	d
+RG_TURISMO_TRX_EN_VCOBF_DIVCK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16232;"	d
+RG_TURISMO_TRX_EN_VCOBF_DIVCK_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16229;"	d
+RG_TURISMO_TRX_EN_VCOBF_DIVCK_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16227;"	d
+RG_TURISMO_TRX_EN_VCOBF_DIVCK_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16226;"	d
+RG_TURISMO_TRX_EN_VCOBF_DIVCK_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16228;"	d
+RG_TURISMO_TRX_EN_VCOBF_DIVCK_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16230;"	d
+RG_TURISMO_TRX_EN_VCOBF_DIVCK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16231;"	d
+RG_TURISMO_TRX_EN_VCOBF_DIVCK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16233;"	d
+RG_TURISMO_TRX_EN_VCOBF_DIVCK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16235;"	d
+RG_TURISMO_TRX_EN_VCOBF_RXMB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16214;"	d
+RG_TURISMO_TRX_EN_VCOBF_RXMB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16212;"	d
+RG_TURISMO_TRX_EN_VCOBF_RXMB_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16209;"	d
+RG_TURISMO_TRX_EN_VCOBF_RXMB_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16207;"	d
+RG_TURISMO_TRX_EN_VCOBF_RXMB_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16206;"	d
+RG_TURISMO_TRX_EN_VCOBF_RXMB_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16208;"	d
+RG_TURISMO_TRX_EN_VCOBF_RXMB_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16210;"	d
+RG_TURISMO_TRX_EN_VCOBF_RXMB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16211;"	d
+RG_TURISMO_TRX_EN_VCOBF_RXMB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16213;"	d
+RG_TURISMO_TRX_EN_VCOBF_RXMB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16215;"	d
+RG_TURISMO_TRX_EN_VCOBF_RXOB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16224;"	d
+RG_TURISMO_TRX_EN_VCOBF_RXOB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16222;"	d
+RG_TURISMO_TRX_EN_VCOBF_RXOB_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16219;"	d
+RG_TURISMO_TRX_EN_VCOBF_RXOB_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16217;"	d
+RG_TURISMO_TRX_EN_VCOBF_RXOB_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16216;"	d
+RG_TURISMO_TRX_EN_VCOBF_RXOB_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16218;"	d
+RG_TURISMO_TRX_EN_VCOBF_RXOB_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16220;"	d
+RG_TURISMO_TRX_EN_VCOBF_RXOB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16221;"	d
+RG_TURISMO_TRX_EN_VCOBF_RXOB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16223;"	d
+RG_TURISMO_TRX_EN_VCOBF_RXOB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16225;"	d
+RG_TURISMO_TRX_EN_VCOBF_TXMB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16194;"	d
+RG_TURISMO_TRX_EN_VCOBF_TXMB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16192;"	d
+RG_TURISMO_TRX_EN_VCOBF_TXMB_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16189;"	d
+RG_TURISMO_TRX_EN_VCOBF_TXMB_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16187;"	d
+RG_TURISMO_TRX_EN_VCOBF_TXMB_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16186;"	d
+RG_TURISMO_TRX_EN_VCOBF_TXMB_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16188;"	d
+RG_TURISMO_TRX_EN_VCOBF_TXMB_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16190;"	d
+RG_TURISMO_TRX_EN_VCOBF_TXMB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16191;"	d
+RG_TURISMO_TRX_EN_VCOBF_TXMB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16193;"	d
+RG_TURISMO_TRX_EN_VCOBF_TXMB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16195;"	d
+RG_TURISMO_TRX_EN_VCOBF_TXOB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16204;"	d
+RG_TURISMO_TRX_EN_VCOBF_TXOB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16202;"	d
+RG_TURISMO_TRX_EN_VCOBF_TXOB_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16199;"	d
+RG_TURISMO_TRX_EN_VCOBF_TXOB_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16197;"	d
+RG_TURISMO_TRX_EN_VCOBF_TXOB_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16196;"	d
+RG_TURISMO_TRX_EN_VCOBF_TXOB_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16198;"	d
+RG_TURISMO_TRX_EN_VCOBF_TXOB_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16200;"	d
+RG_TURISMO_TRX_EN_VCOBF_TXOB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16201;"	d
+RG_TURISMO_TRX_EN_VCOBF_TXOB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16203;"	d
+RG_TURISMO_TRX_EN_VCOBF_TXOB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16205;"	d
+RG_TURISMO_TRX_EN_XOTEST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20714;"	d
+RG_TURISMO_TRX_EN_XOTEST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20712;"	d
+RG_TURISMO_TRX_EN_XOTEST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20711;"	d
+RG_TURISMO_TRX_EN_XOTEST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20713;"	d
+RG_TURISMO_TRX_EN_XOTEST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20715;"	d
+RG_TURISMO_TRX_EXT_MCU_PWRUP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21404;"	d
+RG_TURISMO_TRX_EXT_MCU_PWRUP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21402;"	d
+RG_TURISMO_TRX_EXT_MCU_PWRUP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21401;"	d
+RG_TURISMO_TRX_EXT_MCU_PWRUP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21403;"	d
+RG_TURISMO_TRX_EXT_MCU_PWRUP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21405;"	d
+RG_TURISMO_TRX_FDB_BYPASS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20704;"	d
+RG_TURISMO_TRX_FDB_BYPASS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20702;"	d
+RG_TURISMO_TRX_FDB_BYPASS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20701;"	d
+RG_TURISMO_TRX_FDB_BYPASS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20703;"	d
+RG_TURISMO_TRX_FDB_BYPASS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20705;"	d
+RG_TURISMO_TRX_FDB_CDELAY_MUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20744;"	d
+RG_TURISMO_TRX_FDB_CDELAY_MUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20742;"	d
+RG_TURISMO_TRX_FDB_CDELAY_MUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20741;"	d
+RG_TURISMO_TRX_FDB_CDELAY_MUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20743;"	d
+RG_TURISMO_TRX_FDB_CDELAY_MUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20745;"	d
+RG_TURISMO_TRX_FDB_DUTY_LTH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20709;"	d
+RG_TURISMO_TRX_FDB_DUTY_LTH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20707;"	d
+RG_TURISMO_TRX_FDB_DUTY_LTH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20706;"	d
+RG_TURISMO_TRX_FDB_DUTY_LTH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20708;"	d
+RG_TURISMO_TRX_FDB_DUTY_LTH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20710;"	d
+RG_TURISMO_TRX_FDB_FDELAY_MUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20749;"	d
+RG_TURISMO_TRX_FDB_FDELAY_MUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20747;"	d
+RG_TURISMO_TRX_FDB_FDELAY_MUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20746;"	d
+RG_TURISMO_TRX_FDB_FDELAY_MUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20748;"	d
+RG_TURISMO_TRX_FDB_FDELAY_MUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20750;"	d
+RG_TURISMO_TRX_FDB_PHASESWAP_MUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20739;"	d
+RG_TURISMO_TRX_FDB_PHASESWAP_MUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20737;"	d
+RG_TURISMO_TRX_FDB_PHASESWAP_MUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20736;"	d
+RG_TURISMO_TRX_FDB_PHASESWAP_MUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20738;"	d
+RG_TURISMO_TRX_FDB_PHASESWAP_MUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20740;"	d
+RG_TURISMO_TRX_FDB_RDELAYF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20764;"	d
+RG_TURISMO_TRX_FDB_RDELAYF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20762;"	d
+RG_TURISMO_TRX_FDB_RDELAYF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20761;"	d
+RG_TURISMO_TRX_FDB_RDELAYF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20763;"	d
+RG_TURISMO_TRX_FDB_RDELAYF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20765;"	d
+RG_TURISMO_TRX_FDB_RDELAYS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20769;"	d
+RG_TURISMO_TRX_FDB_RDELAYS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20767;"	d
+RG_TURISMO_TRX_FDB_RDELAYS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20766;"	d
+RG_TURISMO_TRX_FDB_RDELAYS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20768;"	d
+RG_TURISMO_TRX_FDB_RDELAYS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20770;"	d
+RG_TURISMO_TRX_FDB_RECAL_TIMMER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20774;"	d
+RG_TURISMO_TRX_FDB_RECAL_TIMMER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20772;"	d
+RG_TURISMO_TRX_FDB_RECAL_TIMMER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20771;"	d
+RG_TURISMO_TRX_FDB_RECAL_TIMMER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20773;"	d
+RG_TURISMO_TRX_FDB_RECAL_TIMMER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20775;"	d
+RG_TURISMO_TRX_FPGA_CLK_REF_40M_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21124;"	d
+RG_TURISMO_TRX_FPGA_CLK_REF_40M_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21122;"	d
+RG_TURISMO_TRX_FPGA_CLK_REF_40M_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21121;"	d
+RG_TURISMO_TRX_FPGA_CLK_REF_40M_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21123;"	d
+RG_TURISMO_TRX_FPGA_CLK_REF_40M_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21125;"	d
+RG_TURISMO_TRX_FPGA_CLK_REF_40M_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21009;"	d
+RG_TURISMO_TRX_FPGA_CLK_REF_40M_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21007;"	d
+RG_TURISMO_TRX_FPGA_CLK_REF_40M_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21006;"	d
+RG_TURISMO_TRX_FPGA_CLK_REF_40M_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21008;"	d
+RG_TURISMO_TRX_FPGA_CLK_REF_40M_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21010;"	d
+RG_TURISMO_TRX_FPGA_CLK_REF_40M_OE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21134;"	d
+RG_TURISMO_TRX_FPGA_CLK_REF_40M_OE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21132;"	d
+RG_TURISMO_TRX_FPGA_CLK_REF_40M_OE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21131;"	d
+RG_TURISMO_TRX_FPGA_CLK_REF_40M_OE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21133;"	d
+RG_TURISMO_TRX_FPGA_CLK_REF_40M_OE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21135;"	d
+RG_TURISMO_TRX_FPGA_CLK_REF_40M_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21129;"	d
+RG_TURISMO_TRX_FPGA_CLK_REF_40M_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21127;"	d
+RG_TURISMO_TRX_FPGA_CLK_REF_40M_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21126;"	d
+RG_TURISMO_TRX_FPGA_CLK_REF_40M_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21128;"	d
+RG_TURISMO_TRX_FPGA_CLK_REF_40M_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21130;"	d
+RG_TURISMO_TRX_GPIO00_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21259;"	d
+RG_TURISMO_TRX_GPIO00_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21257;"	d
+RG_TURISMO_TRX_GPIO00_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21256;"	d
+RG_TURISMO_TRX_GPIO00_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21258;"	d
+RG_TURISMO_TRX_GPIO00_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21260;"	d
+RG_TURISMO_TRX_GPIO00_OE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21269;"	d
+RG_TURISMO_TRX_GPIO00_OE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21267;"	d
+RG_TURISMO_TRX_GPIO00_OE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21266;"	d
+RG_TURISMO_TRX_GPIO00_OE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21268;"	d
+RG_TURISMO_TRX_GPIO00_OE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21270;"	d
+RG_TURISMO_TRX_GPIO00_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21264;"	d
+RG_TURISMO_TRX_GPIO00_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21262;"	d
+RG_TURISMO_TRX_GPIO00_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21261;"	d
+RG_TURISMO_TRX_GPIO00_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21263;"	d
+RG_TURISMO_TRX_GPIO00_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21265;"	d
+RG_TURISMO_TRX_GPIO01_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21274;"	d
+RG_TURISMO_TRX_GPIO01_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21272;"	d
+RG_TURISMO_TRX_GPIO01_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21271;"	d
+RG_TURISMO_TRX_GPIO01_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21273;"	d
+RG_TURISMO_TRX_GPIO01_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21275;"	d
+RG_TURISMO_TRX_GPIO01_OE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21284;"	d
+RG_TURISMO_TRX_GPIO01_OE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21282;"	d
+RG_TURISMO_TRX_GPIO01_OE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21281;"	d
+RG_TURISMO_TRX_GPIO01_OE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21283;"	d
+RG_TURISMO_TRX_GPIO01_OE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21285;"	d
+RG_TURISMO_TRX_GPIO01_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21279;"	d
+RG_TURISMO_TRX_GPIO01_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21277;"	d
+RG_TURISMO_TRX_GPIO01_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21276;"	d
+RG_TURISMO_TRX_GPIO01_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21278;"	d
+RG_TURISMO_TRX_GPIO01_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21280;"	d
+RG_TURISMO_TRX_GPIO02_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21289;"	d
+RG_TURISMO_TRX_GPIO02_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21287;"	d
+RG_TURISMO_TRX_GPIO02_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21286;"	d
+RG_TURISMO_TRX_GPIO02_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21288;"	d
+RG_TURISMO_TRX_GPIO02_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21290;"	d
+RG_TURISMO_TRX_GPIO02_OE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21299;"	d
+RG_TURISMO_TRX_GPIO02_OE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21297;"	d
+RG_TURISMO_TRX_GPIO02_OE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21296;"	d
+RG_TURISMO_TRX_GPIO02_OE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21298;"	d
+RG_TURISMO_TRX_GPIO02_OE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21300;"	d
+RG_TURISMO_TRX_GPIO02_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21294;"	d
+RG_TURISMO_TRX_GPIO02_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21292;"	d
+RG_TURISMO_TRX_GPIO02_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21291;"	d
+RG_TURISMO_TRX_GPIO02_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21293;"	d
+RG_TURISMO_TRX_GPIO02_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21295;"	d
+RG_TURISMO_TRX_GPIO03_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21304;"	d
+RG_TURISMO_TRX_GPIO03_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21302;"	d
+RG_TURISMO_TRX_GPIO03_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21301;"	d
+RG_TURISMO_TRX_GPIO03_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21303;"	d
+RG_TURISMO_TRX_GPIO03_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21305;"	d
+RG_TURISMO_TRX_GPIO03_OE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21314;"	d
+RG_TURISMO_TRX_GPIO03_OE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21312;"	d
+RG_TURISMO_TRX_GPIO03_OE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21311;"	d
+RG_TURISMO_TRX_GPIO03_OE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21313;"	d
+RG_TURISMO_TRX_GPIO03_OE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21315;"	d
+RG_TURISMO_TRX_GPIO03_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21309;"	d
+RG_TURISMO_TRX_GPIO03_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21307;"	d
+RG_TURISMO_TRX_GPIO03_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21306;"	d
+RG_TURISMO_TRX_GPIO03_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21308;"	d
+RG_TURISMO_TRX_GPIO03_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21310;"	d
+RG_TURISMO_TRX_GPIO04_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21319;"	d
+RG_TURISMO_TRX_GPIO04_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21317;"	d
+RG_TURISMO_TRX_GPIO04_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21316;"	d
+RG_TURISMO_TRX_GPIO04_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21318;"	d
+RG_TURISMO_TRX_GPIO04_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21320;"	d
+RG_TURISMO_TRX_GPIO04_OE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21329;"	d
+RG_TURISMO_TRX_GPIO04_OE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21327;"	d
+RG_TURISMO_TRX_GPIO04_OE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21326;"	d
+RG_TURISMO_TRX_GPIO04_OE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21328;"	d
+RG_TURISMO_TRX_GPIO04_OE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21330;"	d
+RG_TURISMO_TRX_GPIO04_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21324;"	d
+RG_TURISMO_TRX_GPIO04_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21322;"	d
+RG_TURISMO_TRX_GPIO04_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21321;"	d
+RG_TURISMO_TRX_GPIO04_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21323;"	d
+RG_TURISMO_TRX_GPIO04_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21325;"	d
+RG_TURISMO_TRX_GPIO05_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21334;"	d
+RG_TURISMO_TRX_GPIO05_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21332;"	d
+RG_TURISMO_TRX_GPIO05_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21331;"	d
+RG_TURISMO_TRX_GPIO05_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21333;"	d
+RG_TURISMO_TRX_GPIO05_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21335;"	d
+RG_TURISMO_TRX_GPIO05_OE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21344;"	d
+RG_TURISMO_TRX_GPIO05_OE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21342;"	d
+RG_TURISMO_TRX_GPIO05_OE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21341;"	d
+RG_TURISMO_TRX_GPIO05_OE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21343;"	d
+RG_TURISMO_TRX_GPIO05_OE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21345;"	d
+RG_TURISMO_TRX_GPIO05_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21339;"	d
+RG_TURISMO_TRX_GPIO05_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21337;"	d
+RG_TURISMO_TRX_GPIO05_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21336;"	d
+RG_TURISMO_TRX_GPIO05_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21338;"	d
+RG_TURISMO_TRX_GPIO05_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21340;"	d
+RG_TURISMO_TRX_GPIO06_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21349;"	d
+RG_TURISMO_TRX_GPIO06_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21347;"	d
+RG_TURISMO_TRX_GPIO06_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21346;"	d
+RG_TURISMO_TRX_GPIO06_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21348;"	d
+RG_TURISMO_TRX_GPIO06_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21350;"	d
+RG_TURISMO_TRX_GPIO06_OE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21359;"	d
+RG_TURISMO_TRX_GPIO06_OE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21357;"	d
+RG_TURISMO_TRX_GPIO06_OE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21356;"	d
+RG_TURISMO_TRX_GPIO06_OE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21358;"	d
+RG_TURISMO_TRX_GPIO06_OE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21360;"	d
+RG_TURISMO_TRX_GPIO06_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21354;"	d
+RG_TURISMO_TRX_GPIO06_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21352;"	d
+RG_TURISMO_TRX_GPIO06_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21351;"	d
+RG_TURISMO_TRX_GPIO06_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21353;"	d
+RG_TURISMO_TRX_GPIO06_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21355;"	d
+RG_TURISMO_TRX_GPIO07_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21364;"	d
+RG_TURISMO_TRX_GPIO07_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21362;"	d
+RG_TURISMO_TRX_GPIO07_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21361;"	d
+RG_TURISMO_TRX_GPIO07_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21363;"	d
+RG_TURISMO_TRX_GPIO07_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21365;"	d
+RG_TURISMO_TRX_GPIO07_OE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21374;"	d
+RG_TURISMO_TRX_GPIO07_OE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21372;"	d
+RG_TURISMO_TRX_GPIO07_OE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21371;"	d
+RG_TURISMO_TRX_GPIO07_OE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21373;"	d
+RG_TURISMO_TRX_GPIO07_OE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21375;"	d
+RG_TURISMO_TRX_GPIO07_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21369;"	d
+RG_TURISMO_TRX_GPIO07_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21367;"	d
+RG_TURISMO_TRX_GPIO07_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21366;"	d
+RG_TURISMO_TRX_GPIO07_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21368;"	d
+RG_TURISMO_TRX_GPIO07_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21370;"	d
+RG_TURISMO_TRX_GPIO08_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21139;"	d
+RG_TURISMO_TRX_GPIO08_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21137;"	d
+RG_TURISMO_TRX_GPIO08_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21136;"	d
+RG_TURISMO_TRX_GPIO08_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21138;"	d
+RG_TURISMO_TRX_GPIO08_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21140;"	d
+RG_TURISMO_TRX_GPIO08_OE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21149;"	d
+RG_TURISMO_TRX_GPIO08_OE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21147;"	d
+RG_TURISMO_TRX_GPIO08_OE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21146;"	d
+RG_TURISMO_TRX_GPIO08_OE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21148;"	d
+RG_TURISMO_TRX_GPIO08_OE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21150;"	d
+RG_TURISMO_TRX_GPIO08_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21144;"	d
+RG_TURISMO_TRX_GPIO08_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21142;"	d
+RG_TURISMO_TRX_GPIO08_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21141;"	d
+RG_TURISMO_TRX_GPIO08_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21143;"	d
+RG_TURISMO_TRX_GPIO08_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21145;"	d
+RG_TURISMO_TRX_GPIO09_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21154;"	d
+RG_TURISMO_TRX_GPIO09_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21152;"	d
+RG_TURISMO_TRX_GPIO09_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21151;"	d
+RG_TURISMO_TRX_GPIO09_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21153;"	d
+RG_TURISMO_TRX_GPIO09_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21155;"	d
+RG_TURISMO_TRX_GPIO09_OE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21164;"	d
+RG_TURISMO_TRX_GPIO09_OE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21162;"	d
+RG_TURISMO_TRX_GPIO09_OE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21161;"	d
+RG_TURISMO_TRX_GPIO09_OE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21163;"	d
+RG_TURISMO_TRX_GPIO09_OE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21165;"	d
+RG_TURISMO_TRX_GPIO09_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21159;"	d
+RG_TURISMO_TRX_GPIO09_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21157;"	d
+RG_TURISMO_TRX_GPIO09_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21156;"	d
+RG_TURISMO_TRX_GPIO09_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21158;"	d
+RG_TURISMO_TRX_GPIO09_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21160;"	d
+RG_TURISMO_TRX_GPIO10_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21169;"	d
+RG_TURISMO_TRX_GPIO10_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21167;"	d
+RG_TURISMO_TRX_GPIO10_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21166;"	d
+RG_TURISMO_TRX_GPIO10_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21168;"	d
+RG_TURISMO_TRX_GPIO10_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21170;"	d
+RG_TURISMO_TRX_GPIO10_OE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21179;"	d
+RG_TURISMO_TRX_GPIO10_OE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21177;"	d
+RG_TURISMO_TRX_GPIO10_OE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21176;"	d
+RG_TURISMO_TRX_GPIO10_OE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21178;"	d
+RG_TURISMO_TRX_GPIO10_OE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21180;"	d
+RG_TURISMO_TRX_GPIO10_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21174;"	d
+RG_TURISMO_TRX_GPIO10_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21172;"	d
+RG_TURISMO_TRX_GPIO10_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21171;"	d
+RG_TURISMO_TRX_GPIO10_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21173;"	d
+RG_TURISMO_TRX_GPIO10_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21175;"	d
+RG_TURISMO_TRX_GPIO11_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21184;"	d
+RG_TURISMO_TRX_GPIO11_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21182;"	d
+RG_TURISMO_TRX_GPIO11_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21181;"	d
+RG_TURISMO_TRX_GPIO11_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21183;"	d
+RG_TURISMO_TRX_GPIO11_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21185;"	d
+RG_TURISMO_TRX_GPIO11_OE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21194;"	d
+RG_TURISMO_TRX_GPIO11_OE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21192;"	d
+RG_TURISMO_TRX_GPIO11_OE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21191;"	d
+RG_TURISMO_TRX_GPIO11_OE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21193;"	d
+RG_TURISMO_TRX_GPIO11_OE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21195;"	d
+RG_TURISMO_TRX_GPIO11_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21189;"	d
+RG_TURISMO_TRX_GPIO11_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21187;"	d
+RG_TURISMO_TRX_GPIO11_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21186;"	d
+RG_TURISMO_TRX_GPIO11_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21188;"	d
+RG_TURISMO_TRX_GPIO11_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21190;"	d
+RG_TURISMO_TRX_GPIO12_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21199;"	d
+RG_TURISMO_TRX_GPIO12_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21197;"	d
+RG_TURISMO_TRX_GPIO12_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21196;"	d
+RG_TURISMO_TRX_GPIO12_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21198;"	d
+RG_TURISMO_TRX_GPIO12_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21200;"	d
+RG_TURISMO_TRX_GPIO12_OE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21209;"	d
+RG_TURISMO_TRX_GPIO12_OE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21207;"	d
+RG_TURISMO_TRX_GPIO12_OE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21206;"	d
+RG_TURISMO_TRX_GPIO12_OE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21208;"	d
+RG_TURISMO_TRX_GPIO12_OE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21210;"	d
+RG_TURISMO_TRX_GPIO12_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21204;"	d
+RG_TURISMO_TRX_GPIO12_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21202;"	d
+RG_TURISMO_TRX_GPIO12_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21201;"	d
+RG_TURISMO_TRX_GPIO12_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21203;"	d
+RG_TURISMO_TRX_GPIO12_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21205;"	d
+RG_TURISMO_TRX_GPIO13_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21214;"	d
+RG_TURISMO_TRX_GPIO13_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21212;"	d
+RG_TURISMO_TRX_GPIO13_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21211;"	d
+RG_TURISMO_TRX_GPIO13_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21213;"	d
+RG_TURISMO_TRX_GPIO13_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21215;"	d
+RG_TURISMO_TRX_GPIO13_OE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21224;"	d
+RG_TURISMO_TRX_GPIO13_OE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21222;"	d
+RG_TURISMO_TRX_GPIO13_OE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21221;"	d
+RG_TURISMO_TRX_GPIO13_OE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21223;"	d
+RG_TURISMO_TRX_GPIO13_OE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21225;"	d
+RG_TURISMO_TRX_GPIO13_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21219;"	d
+RG_TURISMO_TRX_GPIO13_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21217;"	d
+RG_TURISMO_TRX_GPIO13_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21216;"	d
+RG_TURISMO_TRX_GPIO13_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21218;"	d
+RG_TURISMO_TRX_GPIO13_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21220;"	d
+RG_TURISMO_TRX_GPIO14_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21229;"	d
+RG_TURISMO_TRX_GPIO14_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21227;"	d
+RG_TURISMO_TRX_GPIO14_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21226;"	d
+RG_TURISMO_TRX_GPIO14_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21228;"	d
+RG_TURISMO_TRX_GPIO14_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21230;"	d
+RG_TURISMO_TRX_GPIO14_OE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21239;"	d
+RG_TURISMO_TRX_GPIO14_OE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21237;"	d
+RG_TURISMO_TRX_GPIO14_OE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21236;"	d
+RG_TURISMO_TRX_GPIO14_OE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21238;"	d
+RG_TURISMO_TRX_GPIO14_OE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21240;"	d
+RG_TURISMO_TRX_GPIO14_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21234;"	d
+RG_TURISMO_TRX_GPIO14_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21232;"	d
+RG_TURISMO_TRX_GPIO14_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21231;"	d
+RG_TURISMO_TRX_GPIO14_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21233;"	d
+RG_TURISMO_TRX_GPIO14_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21235;"	d
+RG_TURISMO_TRX_GPIO15_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21244;"	d
+RG_TURISMO_TRX_GPIO15_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21242;"	d
+RG_TURISMO_TRX_GPIO15_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21241;"	d
+RG_TURISMO_TRX_GPIO15_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21243;"	d
+RG_TURISMO_TRX_GPIO15_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21245;"	d
+RG_TURISMO_TRX_GPIO15_OE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21254;"	d
+RG_TURISMO_TRX_GPIO15_OE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21252;"	d
+RG_TURISMO_TRX_GPIO15_OE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21251;"	d
+RG_TURISMO_TRX_GPIO15_OE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21253;"	d
+RG_TURISMO_TRX_GPIO15_OE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21255;"	d
+RG_TURISMO_TRX_GPIO15_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21249;"	d
+RG_TURISMO_TRX_GPIO15_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21247;"	d
+RG_TURISMO_TRX_GPIO15_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21246;"	d
+RG_TURISMO_TRX_GPIO15_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21248;"	d
+RG_TURISMO_TRX_GPIO15_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21250;"	d
+RG_TURISMO_TRX_GPIO16_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21044;"	d
+RG_TURISMO_TRX_GPIO16_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21042;"	d
+RG_TURISMO_TRX_GPIO16_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21041;"	d
+RG_TURISMO_TRX_GPIO16_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21043;"	d
+RG_TURISMO_TRX_GPIO16_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21045;"	d
+RG_TURISMO_TRX_GPIO16_OE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21054;"	d
+RG_TURISMO_TRX_GPIO16_OE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21052;"	d
+RG_TURISMO_TRX_GPIO16_OE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21051;"	d
+RG_TURISMO_TRX_GPIO16_OE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21053;"	d
+RG_TURISMO_TRX_GPIO16_OE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21055;"	d
+RG_TURISMO_TRX_GPIO16_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21049;"	d
+RG_TURISMO_TRX_GPIO16_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21047;"	d
+RG_TURISMO_TRX_GPIO16_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21046;"	d
+RG_TURISMO_TRX_GPIO16_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21048;"	d
+RG_TURISMO_TRX_GPIO16_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21050;"	d
+RG_TURISMO_TRX_GPIO17_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21059;"	d
+RG_TURISMO_TRX_GPIO17_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21057;"	d
+RG_TURISMO_TRX_GPIO17_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21056;"	d
+RG_TURISMO_TRX_GPIO17_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21058;"	d
+RG_TURISMO_TRX_GPIO17_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21060;"	d
+RG_TURISMO_TRX_GPIO17_OE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21069;"	d
+RG_TURISMO_TRX_GPIO17_OE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21067;"	d
+RG_TURISMO_TRX_GPIO17_OE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21066;"	d
+RG_TURISMO_TRX_GPIO17_OE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21068;"	d
+RG_TURISMO_TRX_GPIO17_OE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21070;"	d
+RG_TURISMO_TRX_GPIO17_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21064;"	d
+RG_TURISMO_TRX_GPIO17_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21062;"	d
+RG_TURISMO_TRX_GPIO17_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21061;"	d
+RG_TURISMO_TRX_GPIO17_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21063;"	d
+RG_TURISMO_TRX_GPIO17_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21065;"	d
+RG_TURISMO_TRX_GPIO18_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21074;"	d
+RG_TURISMO_TRX_GPIO18_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21072;"	d
+RG_TURISMO_TRX_GPIO18_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21071;"	d
+RG_TURISMO_TRX_GPIO18_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21073;"	d
+RG_TURISMO_TRX_GPIO18_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21075;"	d
+RG_TURISMO_TRX_GPIO18_OE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21084;"	d
+RG_TURISMO_TRX_GPIO18_OE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21082;"	d
+RG_TURISMO_TRX_GPIO18_OE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21081;"	d
+RG_TURISMO_TRX_GPIO18_OE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21083;"	d
+RG_TURISMO_TRX_GPIO18_OE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21085;"	d
+RG_TURISMO_TRX_GPIO18_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21079;"	d
+RG_TURISMO_TRX_GPIO18_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21077;"	d
+RG_TURISMO_TRX_GPIO18_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21076;"	d
+RG_TURISMO_TRX_GPIO18_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21078;"	d
+RG_TURISMO_TRX_GPIO18_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21080;"	d
+RG_TURISMO_TRX_GPIO19_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21089;"	d
+RG_TURISMO_TRX_GPIO19_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21087;"	d
+RG_TURISMO_TRX_GPIO19_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21086;"	d
+RG_TURISMO_TRX_GPIO19_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21088;"	d
+RG_TURISMO_TRX_GPIO19_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21090;"	d
+RG_TURISMO_TRX_GPIO19_OE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21099;"	d
+RG_TURISMO_TRX_GPIO19_OE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21097;"	d
+RG_TURISMO_TRX_GPIO19_OE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21096;"	d
+RG_TURISMO_TRX_GPIO19_OE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21098;"	d
+RG_TURISMO_TRX_GPIO19_OE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21100;"	d
+RG_TURISMO_TRX_GPIO19_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21094;"	d
+RG_TURISMO_TRX_GPIO19_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21092;"	d
+RG_TURISMO_TRX_GPIO19_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21091;"	d
+RG_TURISMO_TRX_GPIO19_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21093;"	d
+RG_TURISMO_TRX_GPIO19_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21095;"	d
+RG_TURISMO_TRX_GPIO20_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21104;"	d
+RG_TURISMO_TRX_GPIO20_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21102;"	d
+RG_TURISMO_TRX_GPIO20_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21101;"	d
+RG_TURISMO_TRX_GPIO20_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21103;"	d
+RG_TURISMO_TRX_GPIO20_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21105;"	d
+RG_TURISMO_TRX_GPIO20_OE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21114;"	d
+RG_TURISMO_TRX_GPIO20_OE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21112;"	d
+RG_TURISMO_TRX_GPIO20_OE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21111;"	d
+RG_TURISMO_TRX_GPIO20_OE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21113;"	d
+RG_TURISMO_TRX_GPIO20_OE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21115;"	d
+RG_TURISMO_TRX_GPIO20_PD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21109;"	d
+RG_TURISMO_TRX_GPIO20_PD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21107;"	d
+RG_TURISMO_TRX_GPIO20_PD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21106;"	d
+RG_TURISMO_TRX_GPIO20_PD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21108;"	d
+RG_TURISMO_TRX_GPIO20_PD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21110;"	d
+RG_TURISMO_TRX_HS3W_COMM_DATA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20619;"	d
+RG_TURISMO_TRX_HS3W_COMM_DATA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20617;"	d
+RG_TURISMO_TRX_HS3W_COMM_DATA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20616;"	d
+RG_TURISMO_TRX_HS3W_COMM_DATA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20618;"	d
+RG_TURISMO_TRX_HS3W_COMM_DATA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20620;"	d
+RG_TURISMO_TRX_HS3W_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20614;"	d
+RG_TURISMO_TRX_HS3W_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20612;"	d
+RG_TURISMO_TRX_HS3W_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20611;"	d
+RG_TURISMO_TRX_HS3W_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20613;"	d
+RG_TURISMO_TRX_HS3W_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20615;"	d
+RG_TURISMO_TRX_HS3W_PGAGC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20594;"	d
+RG_TURISMO_TRX_HS3W_PGAGC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20592;"	d
+RG_TURISMO_TRX_HS3W_PGAGC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20591;"	d
+RG_TURISMO_TRX_HS3W_PGAGC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20593;"	d
+RG_TURISMO_TRX_HS3W_PGAGC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20595;"	d
+RG_TURISMO_TRX_HS3W_RFGC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20599;"	d
+RG_TURISMO_TRX_HS3W_RFGC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20597;"	d
+RG_TURISMO_TRX_HS3W_RFGC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20596;"	d
+RG_TURISMO_TRX_HS3W_RFGC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20598;"	d
+RG_TURISMO_TRX_HS3W_RFGC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20600;"	d
+RG_TURISMO_TRX_HS3W_RF_PHY_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20609;"	d
+RG_TURISMO_TRX_HS3W_RF_PHY_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20607;"	d
+RG_TURISMO_TRX_HS3W_RF_PHY_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20606;"	d
+RG_TURISMO_TRX_HS3W_RF_PHY_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20608;"	d
+RG_TURISMO_TRX_HS3W_RF_PHY_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20610;"	d
+RG_TURISMO_TRX_HS3W_RXAGC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20604;"	d
+RG_TURISMO_TRX_HS3W_RXAGC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20602;"	d
+RG_TURISMO_TRX_HS3W_RXAGC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20601;"	d
+RG_TURISMO_TRX_HS3W_RXAGC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20603;"	d
+RG_TURISMO_TRX_HS3W_RXAGC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20605;"	d
+RG_TURISMO_TRX_HS3W_START_SENT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20624;"	d
+RG_TURISMO_TRX_HS3W_START_SENT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20622;"	d
+RG_TURISMO_TRX_HS3W_START_SENT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20621;"	d
+RG_TURISMO_TRX_HS3W_START_SENT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20623;"	d
+RG_TURISMO_TRX_HS3W_START_SENT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20625;"	d
+RG_TURISMO_TRX_HS3W_SX_CHANNEL_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20639;"	d
+RG_TURISMO_TRX_HS3W_SX_CHANNEL_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20637;"	d
+RG_TURISMO_TRX_HS3W_SX_CHANNEL_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20636;"	d
+RG_TURISMO_TRX_HS3W_SX_CHANNEL_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20638;"	d
+RG_TURISMO_TRX_HS3W_SX_CHANNEL_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20640;"	d
+RG_TURISMO_TRX_HS3W_SX_RFCH_MAP_EN_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20634;"	d
+RG_TURISMO_TRX_HS3W_SX_RFCH_MAP_EN_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20632;"	d
+RG_TURISMO_TRX_HS3W_SX_RFCH_MAP_EN_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20631;"	d
+RG_TURISMO_TRX_HS3W_SX_RFCH_MAP_EN_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20633;"	d
+RG_TURISMO_TRX_HS3W_SX_RFCH_MAP_EN_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20635;"	d
+RG_TURISMO_TRX_HS3W_SX_RFCTRL_CH_INT_10_8_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20629;"	d
+RG_TURISMO_TRX_HS3W_SX_RFCTRL_CH_INT_10_8_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20627;"	d
+RG_TURISMO_TRX_HS3W_SX_RFCTRL_CH_INT_10_8_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20626;"	d
+RG_TURISMO_TRX_HS3W_SX_RFCTRL_CH_INT_10_8_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20628;"	d
+RG_TURISMO_TRX_HS3W_SX_RFCTRL_CH_INT_10_8_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20630;"	d
+RG_TURISMO_TRX_HS3W_SX_RFCTRL_CH_INT_7_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20649;"	d
+RG_TURISMO_TRX_HS3W_SX_RFCTRL_CH_INT_7_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20647;"	d
+RG_TURISMO_TRX_HS3W_SX_RFCTRL_CH_INT_7_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20646;"	d
+RG_TURISMO_TRX_HS3W_SX_RFCTRL_CH_INT_7_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20648;"	d
+RG_TURISMO_TRX_HS3W_SX_RFCTRL_CH_INT_7_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20650;"	d
+RG_TURISMO_TRX_HS3W_SX_RFCTRL_F_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20644;"	d
+RG_TURISMO_TRX_HS3W_SX_RFCTRL_F_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20642;"	d
+RG_TURISMO_TRX_HS3W_SX_RFCTRL_F_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20641;"	d
+RG_TURISMO_TRX_HS3W_SX_RFCTRL_F_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20643;"	d
+RG_TURISMO_TRX_HS3W_SX_RFCTRL_F_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20645;"	d
+RG_TURISMO_TRX_HS3W_TX_RF_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20589;"	d
+RG_TURISMO_TRX_HS3W_TX_RF_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20587;"	d
+RG_TURISMO_TRX_HS3W_TX_RF_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20586;"	d
+RG_TURISMO_TRX_HS3W_TX_RF_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20588;"	d
+RG_TURISMO_TRX_HS3W_TX_RF_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20590;"	d
+RG_TURISMO_TRX_HSDIV_INBFSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19169;"	d
+RG_TURISMO_TRX_HSDIV_INBFSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19167;"	d
+RG_TURISMO_TRX_HSDIV_INBFSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19166;"	d
+RG_TURISMO_TRX_HSDIV_INBFSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19168;"	d
+RG_TURISMO_TRX_HSDIV_INBFSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19170;"	d
+RG_TURISMO_TRX_HSDIV_OBFMX_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19174;"	d
+RG_TURISMO_TRX_HSDIV_OBFMX_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19172;"	d
+RG_TURISMO_TRX_HSDIV_OBFMX_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19171;"	d
+RG_TURISMO_TRX_HSDIV_OBFMX_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19173;"	d
+RG_TURISMO_TRX_HSDIV_OBFMX_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19175;"	d
+RG_TURISMO_TRX_HSDIV_OBFSX_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19179;"	d
+RG_TURISMO_TRX_HSDIV_OBFSX_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19177;"	d
+RG_TURISMO_TRX_HSDIV_OBFSX_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19176;"	d
+RG_TURISMO_TRX_HSDIV_OBFSX_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19178;"	d
+RG_TURISMO_TRX_HSDIV_OBFSX_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19180;"	d
+RG_TURISMO_TRX_HSDIV_VRSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19184;"	d
+RG_TURISMO_TRX_HSDIV_VRSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19182;"	d
+RG_TURISMO_TRX_HSDIV_VRSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19181;"	d
+RG_TURISMO_TRX_HSDIV_VRSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19183;"	d
+RG_TURISMO_TRX_HSDIV_VRSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19185;"	d
+RG_TURISMO_TRX_HS_3WIRE_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14609;"	d
+RG_TURISMO_TRX_HS_3WIRE_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14607;"	d
+RG_TURISMO_TRX_HS_3WIRE_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14606;"	d
+RG_TURISMO_TRX_HS_3WIRE_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14608;"	d
+RG_TURISMO_TRX_HS_3WIRE_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14610;"	d
+RG_TURISMO_TRX_HW_PINSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14604;"	d
+RG_TURISMO_TRX_HW_PINSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14602;"	d
+RG_TURISMO_TRX_HW_PINSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14601;"	d
+RG_TURISMO_TRX_HW_PINSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14603;"	d
+RG_TURISMO_TRX_HW_PINSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14605;"	d
+RG_TURISMO_TRX_IDACAI_TZ0_COARSE0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17379;"	d
+RG_TURISMO_TRX_IDACAI_TZ0_COARSE0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17377;"	d
+RG_TURISMO_TRX_IDACAI_TZ0_COARSE0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17376;"	d
+RG_TURISMO_TRX_IDACAI_TZ0_COARSE0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17378;"	d
+RG_TURISMO_TRX_IDACAI_TZ0_COARSE0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17380;"	d
+RG_TURISMO_TRX_IDACAI_TZ0_COARSE1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17369;"	d
+RG_TURISMO_TRX_IDACAI_TZ0_COARSE1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17367;"	d
+RG_TURISMO_TRX_IDACAI_TZ0_COARSE1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17366;"	d
+RG_TURISMO_TRX_IDACAI_TZ0_COARSE1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17368;"	d
+RG_TURISMO_TRX_IDACAI_TZ0_COARSE1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17370;"	d
+RG_TURISMO_TRX_IDACAI_TZ0_COARSE2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17359;"	d
+RG_TURISMO_TRX_IDACAI_TZ0_COARSE2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17357;"	d
+RG_TURISMO_TRX_IDACAI_TZ0_COARSE2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17356;"	d
+RG_TURISMO_TRX_IDACAI_TZ0_COARSE2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17358;"	d
+RG_TURISMO_TRX_IDACAI_TZ0_COARSE2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17360;"	d
+RG_TURISMO_TRX_IDACAI_TZ0_COARSE3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17349;"	d
+RG_TURISMO_TRX_IDACAI_TZ0_COARSE3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17347;"	d
+RG_TURISMO_TRX_IDACAI_TZ0_COARSE3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17346;"	d
+RG_TURISMO_TRX_IDACAI_TZ0_COARSE3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17348;"	d
+RG_TURISMO_TRX_IDACAI_TZ0_COARSE3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17350;"	d
+RG_TURISMO_TRX_IDACAI_TZ0_COARSE4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17339;"	d
+RG_TURISMO_TRX_IDACAI_TZ0_COARSE4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17337;"	d
+RG_TURISMO_TRX_IDACAI_TZ0_COARSE4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17336;"	d
+RG_TURISMO_TRX_IDACAI_TZ0_COARSE4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17338;"	d
+RG_TURISMO_TRX_IDACAI_TZ0_COARSE4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17340;"	d
+RG_TURISMO_TRX_IDACAI_TZ1_COARSE0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17429;"	d
+RG_TURISMO_TRX_IDACAI_TZ1_COARSE0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17427;"	d
+RG_TURISMO_TRX_IDACAI_TZ1_COARSE0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17426;"	d
+RG_TURISMO_TRX_IDACAI_TZ1_COARSE0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17428;"	d
+RG_TURISMO_TRX_IDACAI_TZ1_COARSE0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17430;"	d
+RG_TURISMO_TRX_IDACAI_TZ1_COARSE1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17419;"	d
+RG_TURISMO_TRX_IDACAI_TZ1_COARSE1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17417;"	d
+RG_TURISMO_TRX_IDACAI_TZ1_COARSE1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17416;"	d
+RG_TURISMO_TRX_IDACAI_TZ1_COARSE1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17418;"	d
+RG_TURISMO_TRX_IDACAI_TZ1_COARSE1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17420;"	d
+RG_TURISMO_TRX_IDACAI_TZ1_COARSE2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17409;"	d
+RG_TURISMO_TRX_IDACAI_TZ1_COARSE2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17407;"	d
+RG_TURISMO_TRX_IDACAI_TZ1_COARSE2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17406;"	d
+RG_TURISMO_TRX_IDACAI_TZ1_COARSE2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17408;"	d
+RG_TURISMO_TRX_IDACAI_TZ1_COARSE2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17410;"	d
+RG_TURISMO_TRX_IDACAI_TZ1_COARSE3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17399;"	d
+RG_TURISMO_TRX_IDACAI_TZ1_COARSE3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17397;"	d
+RG_TURISMO_TRX_IDACAI_TZ1_COARSE3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17396;"	d
+RG_TURISMO_TRX_IDACAI_TZ1_COARSE3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17398;"	d
+RG_TURISMO_TRX_IDACAI_TZ1_COARSE3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17400;"	d
+RG_TURISMO_TRX_IDACAI_TZ1_COARSE4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17389;"	d
+RG_TURISMO_TRX_IDACAI_TZ1_COARSE4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17387;"	d
+RG_TURISMO_TRX_IDACAI_TZ1_COARSE4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17386;"	d
+RG_TURISMO_TRX_IDACAI_TZ1_COARSE4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17388;"	d
+RG_TURISMO_TRX_IDACAI_TZ1_COARSE4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17390;"	d
+RG_TURISMO_TRX_IDACAQ_TZ0_COARSE0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17384;"	d
+RG_TURISMO_TRX_IDACAQ_TZ0_COARSE0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17382;"	d
+RG_TURISMO_TRX_IDACAQ_TZ0_COARSE0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17381;"	d
+RG_TURISMO_TRX_IDACAQ_TZ0_COARSE0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17383;"	d
+RG_TURISMO_TRX_IDACAQ_TZ0_COARSE0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17385;"	d
+RG_TURISMO_TRX_IDACAQ_TZ0_COARSE1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17374;"	d
+RG_TURISMO_TRX_IDACAQ_TZ0_COARSE1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17372;"	d
+RG_TURISMO_TRX_IDACAQ_TZ0_COARSE1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17371;"	d
+RG_TURISMO_TRX_IDACAQ_TZ0_COARSE1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17373;"	d
+RG_TURISMO_TRX_IDACAQ_TZ0_COARSE1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17375;"	d
+RG_TURISMO_TRX_IDACAQ_TZ0_COARSE2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17364;"	d
+RG_TURISMO_TRX_IDACAQ_TZ0_COARSE2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17362;"	d
+RG_TURISMO_TRX_IDACAQ_TZ0_COARSE2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17361;"	d
+RG_TURISMO_TRX_IDACAQ_TZ0_COARSE2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17363;"	d
+RG_TURISMO_TRX_IDACAQ_TZ0_COARSE2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17365;"	d
+RG_TURISMO_TRX_IDACAQ_TZ0_COARSE3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17354;"	d
+RG_TURISMO_TRX_IDACAQ_TZ0_COARSE3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17352;"	d
+RG_TURISMO_TRX_IDACAQ_TZ0_COARSE3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17351;"	d
+RG_TURISMO_TRX_IDACAQ_TZ0_COARSE3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17353;"	d
+RG_TURISMO_TRX_IDACAQ_TZ0_COARSE3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17355;"	d
+RG_TURISMO_TRX_IDACAQ_TZ0_COARSE4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17344;"	d
+RG_TURISMO_TRX_IDACAQ_TZ0_COARSE4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17342;"	d
+RG_TURISMO_TRX_IDACAQ_TZ0_COARSE4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17341;"	d
+RG_TURISMO_TRX_IDACAQ_TZ0_COARSE4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17343;"	d
+RG_TURISMO_TRX_IDACAQ_TZ0_COARSE4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17345;"	d
+RG_TURISMO_TRX_IDACAQ_TZ1_COARSE0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17434;"	d
+RG_TURISMO_TRX_IDACAQ_TZ1_COARSE0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17432;"	d
+RG_TURISMO_TRX_IDACAQ_TZ1_COARSE0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17431;"	d
+RG_TURISMO_TRX_IDACAQ_TZ1_COARSE0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17433;"	d
+RG_TURISMO_TRX_IDACAQ_TZ1_COARSE0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17435;"	d
+RG_TURISMO_TRX_IDACAQ_TZ1_COARSE1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17424;"	d
+RG_TURISMO_TRX_IDACAQ_TZ1_COARSE1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17422;"	d
+RG_TURISMO_TRX_IDACAQ_TZ1_COARSE1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17421;"	d
+RG_TURISMO_TRX_IDACAQ_TZ1_COARSE1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17423;"	d
+RG_TURISMO_TRX_IDACAQ_TZ1_COARSE1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17425;"	d
+RG_TURISMO_TRX_IDACAQ_TZ1_COARSE2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17414;"	d
+RG_TURISMO_TRX_IDACAQ_TZ1_COARSE2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17412;"	d
+RG_TURISMO_TRX_IDACAQ_TZ1_COARSE2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17411;"	d
+RG_TURISMO_TRX_IDACAQ_TZ1_COARSE2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17413;"	d
+RG_TURISMO_TRX_IDACAQ_TZ1_COARSE2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17415;"	d
+RG_TURISMO_TRX_IDACAQ_TZ1_COARSE3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17404;"	d
+RG_TURISMO_TRX_IDACAQ_TZ1_COARSE3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17402;"	d
+RG_TURISMO_TRX_IDACAQ_TZ1_COARSE3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17401;"	d
+RG_TURISMO_TRX_IDACAQ_TZ1_COARSE3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17403;"	d
+RG_TURISMO_TRX_IDACAQ_TZ1_COARSE3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17405;"	d
+RG_TURISMO_TRX_IDACAQ_TZ1_COARSE4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17394;"	d
+RG_TURISMO_TRX_IDACAQ_TZ1_COARSE4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17392;"	d
+RG_TURISMO_TRX_IDACAQ_TZ1_COARSE4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17391;"	d
+RG_TURISMO_TRX_IDACAQ_TZ1_COARSE4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17393;"	d
+RG_TURISMO_TRX_IDACAQ_TZ1_COARSE4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17395;"	d
+RG_TURISMO_TRX_INT_PMU_MASK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20949;"	d
+RG_TURISMO_TRX_INT_PMU_MASK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20947;"	d
+RG_TURISMO_TRX_INT_PMU_MASK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20946;"	d
+RG_TURISMO_TRX_INT_PMU_MASK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20948;"	d
+RG_TURISMO_TRX_INT_PMU_MASK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20950;"	d
+RG_TURISMO_TRX_IOT_ADC_CLKSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17909;"	d
+RG_TURISMO_TRX_IOT_ADC_CLKSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17907;"	d
+RG_TURISMO_TRX_IOT_ADC_CLKSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17906;"	d
+RG_TURISMO_TRX_IOT_ADC_CLKSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17908;"	d
+RG_TURISMO_TRX_IOT_ADC_CLKSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17910;"	d
+RG_TURISMO_TRX_IOT_ADC_CLK_DIV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17944;"	d
+RG_TURISMO_TRX_IOT_ADC_CLK_DIV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17942;"	d
+RG_TURISMO_TRX_IOT_ADC_CLK_DIV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17941;"	d
+RG_TURISMO_TRX_IOT_ADC_CLK_DIV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17943;"	d
+RG_TURISMO_TRX_IOT_ADC_CLK_DIV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17945;"	d
+RG_TURISMO_TRX_IOT_ADC_CLK_SH_DUTY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17949;"	d
+RG_TURISMO_TRX_IOT_ADC_CLK_SH_DUTY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17947;"	d
+RG_TURISMO_TRX_IOT_ADC_CLK_SH_DUTY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17946;"	d
+RG_TURISMO_TRX_IOT_ADC_CLK_SH_DUTY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17948;"	d
+RG_TURISMO_TRX_IOT_ADC_CLK_SH_DUTY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17950;"	d
+RG_TURISMO_TRX_IOT_ADC_CLOAD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17939;"	d
+RG_TURISMO_TRX_IOT_ADC_CLOAD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17937;"	d
+RG_TURISMO_TRX_IOT_ADC_CLOAD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17936;"	d
+RG_TURISMO_TRX_IOT_ADC_CLOAD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17938;"	d
+RG_TURISMO_TRX_IOT_ADC_CLOAD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17940;"	d
+RG_TURISMO_TRX_IOT_ADC_DNLEN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17914;"	d
+RG_TURISMO_TRX_IOT_ADC_DNLEN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17912;"	d
+RG_TURISMO_TRX_IOT_ADC_DNLEN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17911;"	d
+RG_TURISMO_TRX_IOT_ADC_DNLEN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17913;"	d
+RG_TURISMO_TRX_IOT_ADC_DNLEN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17915;"	d
+RG_TURISMO_TRX_IOT_ADC_EDGE_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20199;"	d
+RG_TURISMO_TRX_IOT_ADC_EDGE_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20197;"	d
+RG_TURISMO_TRX_IOT_ADC_EDGE_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20196;"	d
+RG_TURISMO_TRX_IOT_ADC_EDGE_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20198;"	d
+RG_TURISMO_TRX_IOT_ADC_EDGE_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20200;"	d
+RG_TURISMO_TRX_IOT_ADC_ICMP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17929;"	d
+RG_TURISMO_TRX_IOT_ADC_ICMP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17927;"	d
+RG_TURISMO_TRX_IOT_ADC_ICMP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17926;"	d
+RG_TURISMO_TRX_IOT_ADC_ICMP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17928;"	d
+RG_TURISMO_TRX_IOT_ADC_ICMP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17930;"	d
+RG_TURISMO_TRX_IOT_ADC_METAEN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17919;"	d
+RG_TURISMO_TRX_IOT_ADC_METAEN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17917;"	d
+RG_TURISMO_TRX_IOT_ADC_METAEN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17916;"	d
+RG_TURISMO_TRX_IOT_ADC_METAEN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17918;"	d
+RG_TURISMO_TRX_IOT_ADC_METAEN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17920;"	d
+RG_TURISMO_TRX_IOT_ADC_TFLAG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17924;"	d
+RG_TURISMO_TRX_IOT_ADC_TFLAG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17922;"	d
+RG_TURISMO_TRX_IOT_ADC_TFLAG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17921;"	d
+RG_TURISMO_TRX_IOT_ADC_TFLAG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17923;"	d
+RG_TURISMO_TRX_IOT_ADC_TFLAG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17925;"	d
+RG_TURISMO_TRX_IOT_ADC_VCMI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17934;"	d
+RG_TURISMO_TRX_IOT_ADC_VCMI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17932;"	d
+RG_TURISMO_TRX_IOT_ADC_VCMI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17931;"	d
+RG_TURISMO_TRX_IOT_ADC_VCMI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17933;"	d
+RG_TURISMO_TRX_IOT_ADC_VCMI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17935;"	d
+RG_TURISMO_TRX_IQ_SWAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20224;"	d
+RG_TURISMO_TRX_IQ_SWAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20222;"	d
+RG_TURISMO_TRX_IQ_SWAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20221;"	d
+RG_TURISMO_TRX_IQ_SWAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20223;"	d
+RG_TURISMO_TRX_IQ_SWAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20225;"	d
+RG_TURISMO_TRX_I_INV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20219;"	d
+RG_TURISMO_TRX_I_INV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20217;"	d
+RG_TURISMO_TRX_I_INV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20216;"	d
+RG_TURISMO_TRX_I_INV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20218;"	d
+RG_TURISMO_TRX_I_INV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20220;"	d
+RG_TURISMO_TRX_LDO_5G_CP_FC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18954;"	d
+RG_TURISMO_TRX_LDO_5G_CP_FC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18952;"	d
+RG_TURISMO_TRX_LDO_5G_CP_FC_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18949;"	d
+RG_TURISMO_TRX_LDO_5G_CP_FC_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18947;"	d
+RG_TURISMO_TRX_LDO_5G_CP_FC_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18946;"	d
+RG_TURISMO_TRX_LDO_5G_CP_FC_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18948;"	d
+RG_TURISMO_TRX_LDO_5G_CP_FC_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18950;"	d
+RG_TURISMO_TRX_LDO_5G_CP_FC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18951;"	d
+RG_TURISMO_TRX_LDO_5G_CP_FC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18953;"	d
+RG_TURISMO_TRX_LDO_5G_CP_FC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18955;"	d
+RG_TURISMO_TRX_LDO_5G_DIV_FC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18964;"	d
+RG_TURISMO_TRX_LDO_5G_DIV_FC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18962;"	d
+RG_TURISMO_TRX_LDO_5G_DIV_FC_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18959;"	d
+RG_TURISMO_TRX_LDO_5G_DIV_FC_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18957;"	d
+RG_TURISMO_TRX_LDO_5G_DIV_FC_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18956;"	d
+RG_TURISMO_TRX_LDO_5G_DIV_FC_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18958;"	d
+RG_TURISMO_TRX_LDO_5G_DIV_FC_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18960;"	d
+RG_TURISMO_TRX_LDO_5G_DIV_FC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18961;"	d
+RG_TURISMO_TRX_LDO_5G_DIV_FC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18963;"	d
+RG_TURISMO_TRX_LDO_5G_DIV_FC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18965;"	d
+RG_TURISMO_TRX_LDO_5G_LO_FC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18974;"	d
+RG_TURISMO_TRX_LDO_5G_LO_FC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18972;"	d
+RG_TURISMO_TRX_LDO_5G_LO_FC_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18969;"	d
+RG_TURISMO_TRX_LDO_5G_LO_FC_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18967;"	d
+RG_TURISMO_TRX_LDO_5G_LO_FC_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18966;"	d
+RG_TURISMO_TRX_LDO_5G_LO_FC_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18968;"	d
+RG_TURISMO_TRX_LDO_5G_LO_FC_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18970;"	d
+RG_TURISMO_TRX_LDO_5G_LO_FC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18971;"	d
+RG_TURISMO_TRX_LDO_5G_LO_FC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18973;"	d
+RG_TURISMO_TRX_LDO_5G_LO_FC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18975;"	d
+RG_TURISMO_TRX_LDO_5G_VCO_FC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18984;"	d
+RG_TURISMO_TRX_LDO_5G_VCO_FC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18982;"	d
+RG_TURISMO_TRX_LDO_5G_VCO_FC_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18979;"	d
+RG_TURISMO_TRX_LDO_5G_VCO_FC_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18977;"	d
+RG_TURISMO_TRX_LDO_5G_VCO_FC_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18976;"	d
+RG_TURISMO_TRX_LDO_5G_VCO_FC_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18978;"	d
+RG_TURISMO_TRX_LDO_5G_VCO_FC_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18980;"	d
+RG_TURISMO_TRX_LDO_5G_VCO_FC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18981;"	d
+RG_TURISMO_TRX_LDO_5G_VCO_FC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18983;"	d
+RG_TURISMO_TRX_LDO_5G_VCO_FC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18985;"	d
+RG_TURISMO_TRX_LDO_5G_VCO_RCF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18989;"	d
+RG_TURISMO_TRX_LDO_5G_VCO_RCF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18987;"	d
+RG_TURISMO_TRX_LDO_5G_VCO_RCF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18986;"	d
+RG_TURISMO_TRX_LDO_5G_VCO_RCF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18988;"	d
+RG_TURISMO_TRX_LDO_5G_VCO_RCF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18990;"	d
+RG_TURISMO_TRX_LDO_CP_FC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16329;"	d
+RG_TURISMO_TRX_LDO_CP_FC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16327;"	d
+RG_TURISMO_TRX_LDO_CP_FC_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16324;"	d
+RG_TURISMO_TRX_LDO_CP_FC_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16322;"	d
+RG_TURISMO_TRX_LDO_CP_FC_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16321;"	d
+RG_TURISMO_TRX_LDO_CP_FC_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16323;"	d
+RG_TURISMO_TRX_LDO_CP_FC_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16325;"	d
+RG_TURISMO_TRX_LDO_CP_FC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16326;"	d
+RG_TURISMO_TRX_LDO_CP_FC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16328;"	d
+RG_TURISMO_TRX_LDO_CP_FC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16330;"	d
+RG_TURISMO_TRX_LDO_DIV_FC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16339;"	d
+RG_TURISMO_TRX_LDO_DIV_FC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16337;"	d
+RG_TURISMO_TRX_LDO_DIV_FC_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16334;"	d
+RG_TURISMO_TRX_LDO_DIV_FC_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16332;"	d
+RG_TURISMO_TRX_LDO_DIV_FC_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16331;"	d
+RG_TURISMO_TRX_LDO_DIV_FC_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16333;"	d
+RG_TURISMO_TRX_LDO_DIV_FC_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16335;"	d
+RG_TURISMO_TRX_LDO_DIV_FC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16336;"	d
+RG_TURISMO_TRX_LDO_DIV_FC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16338;"	d
+RG_TURISMO_TRX_LDO_DIV_FC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16340;"	d
+RG_TURISMO_TRX_LDO_LEVEL_AFE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14984;"	d
+RG_TURISMO_TRX_LDO_LEVEL_AFE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14982;"	d
+RG_TURISMO_TRX_LDO_LEVEL_AFE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14981;"	d
+RG_TURISMO_TRX_LDO_LEVEL_AFE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14983;"	d
+RG_TURISMO_TRX_LDO_LEVEL_AFE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14985;"	d
+RG_TURISMO_TRX_LDO_LEVEL_EFUSE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20824;"	d
+RG_TURISMO_TRX_LDO_LEVEL_EFUSE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20822;"	d
+RG_TURISMO_TRX_LDO_LEVEL_EFUSE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20821;"	d
+RG_TURISMO_TRX_LDO_LEVEL_EFUSE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20823;"	d
+RG_TURISMO_TRX_LDO_LEVEL_EFUSE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20825;"	d
+RG_TURISMO_TRX_LDO_LEVEL_RX_FE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14974;"	d
+RG_TURISMO_TRX_LDO_LEVEL_RX_FE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14972;"	d
+RG_TURISMO_TRX_LDO_LEVEL_RX_FE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14971;"	d
+RG_TURISMO_TRX_LDO_LEVEL_RX_FE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14973;"	d
+RG_TURISMO_TRX_LDO_LEVEL_RX_FE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14975;"	d
+RG_TURISMO_TRX_LDO_LO_FC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16349;"	d
+RG_TURISMO_TRX_LDO_LO_FC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16347;"	d
+RG_TURISMO_TRX_LDO_LO_FC_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16344;"	d
+RG_TURISMO_TRX_LDO_LO_FC_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16342;"	d
+RG_TURISMO_TRX_LDO_LO_FC_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16341;"	d
+RG_TURISMO_TRX_LDO_LO_FC_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16343;"	d
+RG_TURISMO_TRX_LDO_LO_FC_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16345;"	d
+RG_TURISMO_TRX_LDO_LO_FC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16346;"	d
+RG_TURISMO_TRX_LDO_LO_FC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16348;"	d
+RG_TURISMO_TRX_LDO_LO_FC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16350;"	d
+RG_TURISMO_TRX_LDO_VCO_FC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16359;"	d
+RG_TURISMO_TRX_LDO_VCO_FC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16357;"	d
+RG_TURISMO_TRX_LDO_VCO_FC_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16354;"	d
+RG_TURISMO_TRX_LDO_VCO_FC_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16352;"	d
+RG_TURISMO_TRX_LDO_VCO_FC_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16351;"	d
+RG_TURISMO_TRX_LDO_VCO_FC_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16353;"	d
+RG_TURISMO_TRX_LDO_VCO_FC_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16355;"	d
+RG_TURISMO_TRX_LDO_VCO_FC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16356;"	d
+RG_TURISMO_TRX_LDO_VCO_FC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16358;"	d
+RG_TURISMO_TRX_LDO_VCO_FC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16360;"	d
+RG_TURISMO_TRX_LDO_VCO_RCF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16364;"	d
+RG_TURISMO_TRX_LDO_VCO_RCF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16362;"	d
+RG_TURISMO_TRX_LDO_VCO_RCF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16361;"	d
+RG_TURISMO_TRX_LDO_VCO_RCF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16363;"	d
+RG_TURISMO_TRX_LDO_VCO_RCF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16365;"	d
+RG_TURISMO_TRX_LOAD_RFTABLE_RDY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20784;"	d
+RG_TURISMO_TRX_LOAD_RFTABLE_RDY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20782;"	d
+RG_TURISMO_TRX_LOAD_RFTABLE_RDY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20781;"	d
+RG_TURISMO_TRX_LOAD_RFTABLE_RDY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20783;"	d
+RG_TURISMO_TRX_LOAD_RFTABLE_RDY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20785;"	d
+RG_TURISMO_TRX_LO_UP_CH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20159;"	d
+RG_TURISMO_TRX_LO_UP_CH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20157;"	d
+RG_TURISMO_TRX_LO_UP_CH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20156;"	d
+RG_TURISMO_TRX_LO_UP_CH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20158;"	d
+RG_TURISMO_TRX_LO_UP_CH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20160;"	d
+RG_TURISMO_TRX_MODE_BY_HS_3WIRE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20654;"	d
+RG_TURISMO_TRX_MODE_BY_HS_3WIRE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20652;"	d
+RG_TURISMO_TRX_MODE_BY_HS_3WIRE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20651;"	d
+RG_TURISMO_TRX_MODE_BY_HS_3WIRE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20653;"	d
+RG_TURISMO_TRX_MODE_BY_HS_3WIRE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20655;"	d
+RG_TURISMO_TRX_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14639;"	d
+RG_TURISMO_TRX_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14637;"	d
+RG_TURISMO_TRX_MODE_LATCH_LMT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21394;"	d
+RG_TURISMO_TRX_MODE_LATCH_LMT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21392;"	d
+RG_TURISMO_TRX_MODE_LATCH_LMT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21391;"	d
+RG_TURISMO_TRX_MODE_LATCH_LMT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21393;"	d
+RG_TURISMO_TRX_MODE_LATCH_LMT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21395;"	d
+RG_TURISMO_TRX_MODE_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14614;"	d
+RG_TURISMO_TRX_MODE_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14612;"	d
+RG_TURISMO_TRX_MODE_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14611;"	d
+RG_TURISMO_TRX_MODE_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14613;"	d
+RG_TURISMO_TRX_MODE_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14615;"	d
+RG_TURISMO_TRX_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14636;"	d
+RG_TURISMO_TRX_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14638;"	d
+RG_TURISMO_TRX_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14640;"	d
+RG_TURISMO_TRX_NFRAC_DELTA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20149;"	d
+RG_TURISMO_TRX_NFRAC_DELTA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20147;"	d
+RG_TURISMO_TRX_NFRAC_DELTA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20146;"	d
+RG_TURISMO_TRX_NFRAC_DELTA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20148;"	d
+RG_TURISMO_TRX_NFRAC_DELTA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20150;"	d
+RG_TURISMO_TRX_PAD_MUX_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21389;"	d
+RG_TURISMO_TRX_PAD_MUX_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21387;"	d
+RG_TURISMO_TRX_PAD_MUX_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21386;"	d
+RG_TURISMO_TRX_PAD_MUX_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21388;"	d
+RG_TURISMO_TRX_PAD_MUX_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21390;"	d
+RG_TURISMO_TRX_PGAG_DPDCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17899;"	d
+RG_TURISMO_TRX_PGAG_DPDCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17897;"	d
+RG_TURISMO_TRX_PGAG_DPDCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17896;"	d
+RG_TURISMO_TRX_PGAG_DPDCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17898;"	d
+RG_TURISMO_TRX_PGAG_DPDCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17900;"	d
+RG_TURISMO_TRX_PGAG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14654;"	d
+RG_TURISMO_TRX_PGAG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14652;"	d
+RG_TURISMO_TRX_PGAG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14651;"	d
+RG_TURISMO_TRX_PGAG_RCCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17864;"	d
+RG_TURISMO_TRX_PGAG_RCCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17862;"	d
+RG_TURISMO_TRX_PGAG_RCCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17861;"	d
+RG_TURISMO_TRX_PGAG_RCCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17863;"	d
+RG_TURISMO_TRX_PGAG_RCCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17865;"	d
+RG_TURISMO_TRX_PGAG_RXIQCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17884;"	d
+RG_TURISMO_TRX_PGAG_RXIQCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17882;"	d
+RG_TURISMO_TRX_PGAG_RXIQCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17881;"	d
+RG_TURISMO_TRX_PGAG_RXIQCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17883;"	d
+RG_TURISMO_TRX_PGAG_RXIQCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17885;"	d
+RG_TURISMO_TRX_PGAG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14653;"	d
+RG_TURISMO_TRX_PGAG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14655;"	d
+RG_TURISMO_TRX_PGAG_TXCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17869;"	d
+RG_TURISMO_TRX_PGAG_TXCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17867;"	d
+RG_TURISMO_TRX_PGAG_TXCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17866;"	d
+RG_TURISMO_TRX_PGAG_TXCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17868;"	d
+RG_TURISMO_TRX_PGAG_TXCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17870;"	d
+RG_TURISMO_TRX_PHASE_17P5M_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20474;"	d
+RG_TURISMO_TRX_PHASE_17P5M_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20472;"	d
+RG_TURISMO_TRX_PHASE_17P5M_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20471;"	d
+RG_TURISMO_TRX_PHASE_17P5M_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20473;"	d
+RG_TURISMO_TRX_PHASE_17P5M_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20475;"	d
+RG_TURISMO_TRX_PHASE_1M_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20489;"	d
+RG_TURISMO_TRX_PHASE_1M_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20487;"	d
+RG_TURISMO_TRX_PHASE_1M_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20486;"	d
+RG_TURISMO_TRX_PHASE_1M_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20488;"	d
+RG_TURISMO_TRX_PHASE_1M_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20490;"	d
+RG_TURISMO_TRX_PHASE_2P5M_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20479;"	d
+RG_TURISMO_TRX_PHASE_2P5M_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20477;"	d
+RG_TURISMO_TRX_PHASE_2P5M_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20476;"	d
+RG_TURISMO_TRX_PHASE_2P5M_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20478;"	d
+RG_TURISMO_TRX_PHASE_2P5M_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20480;"	d
+RG_TURISMO_TRX_PHASE_35M_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20499;"	d
+RG_TURISMO_TRX_PHASE_35M_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20497;"	d
+RG_TURISMO_TRX_PHASE_35M_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20496;"	d
+RG_TURISMO_TRX_PHASE_35M_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20498;"	d
+RG_TURISMO_TRX_PHASE_35M_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20500;"	d
+RG_TURISMO_TRX_PHASE_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20399;"	d
+RG_TURISMO_TRX_PHASE_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20397;"	d
+RG_TURISMO_TRX_PHASE_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20396;"	d
+RG_TURISMO_TRX_PHASE_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20398;"	d
+RG_TURISMO_TRX_PHASE_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20400;"	d
+RG_TURISMO_TRX_PHASE_PADPD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20494;"	d
+RG_TURISMO_TRX_PHASE_PADPD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20492;"	d
+RG_TURISMO_TRX_PHASE_PADPD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20491;"	d
+RG_TURISMO_TRX_PHASE_PADPD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20493;"	d
+RG_TURISMO_TRX_PHASE_PADPD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20495;"	d
+RG_TURISMO_TRX_PHASE_RXIQ_1M_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20484;"	d
+RG_TURISMO_TRX_PHASE_RXIQ_1M_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20482;"	d
+RG_TURISMO_TRX_PHASE_RXIQ_1M_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20481;"	d
+RG_TURISMO_TRX_PHASE_RXIQ_1M_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20483;"	d
+RG_TURISMO_TRX_PHASE_RXIQ_1M_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20485;"	d
+RG_TURISMO_TRX_PHASE_STEP_VALUE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20394;"	d
+RG_TURISMO_TRX_PHASE_STEP_VALUE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20392;"	d
+RG_TURISMO_TRX_PHASE_STEP_VALUE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20391;"	d
+RG_TURISMO_TRX_PHASE_STEP_VALUE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20393;"	d
+RG_TURISMO_TRX_PHASE_STEP_VALUE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20395;"	d
+RG_TURISMO_TRX_PHY_RST_N_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21019;"	d
+RG_TURISMO_TRX_PHY_RST_N_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21017;"	d
+RG_TURISMO_TRX_PHY_RST_N_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21016;"	d
+RG_TURISMO_TRX_PHY_RST_N_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21018;"	d
+RG_TURISMO_TRX_PHY_RST_N_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21020;"	d
+RG_TURISMO_TRX_PMU_ENTER_SLEEP_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20939;"	d
+RG_TURISMO_TRX_PMU_ENTER_SLEEP_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20937;"	d
+RG_TURISMO_TRX_PMU_ENTER_SLEEP_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20936;"	d
+RG_TURISMO_TRX_PMU_ENTER_SLEEP_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20938;"	d
+RG_TURISMO_TRX_PMU_ENTER_SLEEP_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20940;"	d
+RG_TURISMO_TRX_PRE_DC_AUTO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20584;"	d
+RG_TURISMO_TRX_PRE_DC_AUTO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20582;"	d
+RG_TURISMO_TRX_PRE_DC_AUTO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20581;"	d
+RG_TURISMO_TRX_PRE_DC_AUTO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20583;"	d
+RG_TURISMO_TRX_PRE_DC_AUTO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20585;"	d
+RG_TURISMO_TRX_PRE_DC_POLA_INV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20574;"	d
+RG_TURISMO_TRX_PRE_DC_POLA_INV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20572;"	d
+RG_TURISMO_TRX_PRE_DC_POLA_INV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20571;"	d
+RG_TURISMO_TRX_PRE_DC_POLA_INV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20573;"	d
+RG_TURISMO_TRX_PRE_DC_POLA_INV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20575;"	d
+RG_TURISMO_TRX_PROC_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20569;"	d
+RG_TURISMO_TRX_PROC_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20567;"	d
+RG_TURISMO_TRX_PROC_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20566;"	d
+RG_TURISMO_TRX_PROC_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20568;"	d
+RG_TURISMO_TRX_PROC_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20570;"	d
+RG_TURISMO_TRX_Q_INV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20214;"	d
+RG_TURISMO_TRX_Q_INV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20212;"	d
+RG_TURISMO_TRX_Q_INV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20211;"	d
+RG_TURISMO_TRX_Q_INV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20213;"	d
+RG_TURISMO_TRX_Q_INV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20215;"	d
+RG_TURISMO_TRX_RAM_00_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21409;"	d
+RG_TURISMO_TRX_RAM_00_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21407;"	d
+RG_TURISMO_TRX_RAM_00_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21406;"	d
+RG_TURISMO_TRX_RAM_00_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21408;"	d
+RG_TURISMO_TRX_RAM_00_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21410;"	d
+RG_TURISMO_TRX_RAM_01_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21414;"	d
+RG_TURISMO_TRX_RAM_01_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21412;"	d
+RG_TURISMO_TRX_RAM_01_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21411;"	d
+RG_TURISMO_TRX_RAM_01_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21413;"	d
+RG_TURISMO_TRX_RAM_01_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21415;"	d
+RG_TURISMO_TRX_RAM_02_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21419;"	d
+RG_TURISMO_TRX_RAM_02_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21417;"	d
+RG_TURISMO_TRX_RAM_02_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21416;"	d
+RG_TURISMO_TRX_RAM_02_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21418;"	d
+RG_TURISMO_TRX_RAM_02_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21420;"	d
+RG_TURISMO_TRX_RAM_03_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21424;"	d
+RG_TURISMO_TRX_RAM_03_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21422;"	d
+RG_TURISMO_TRX_RAM_03_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21421;"	d
+RG_TURISMO_TRX_RAM_03_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21423;"	d
+RG_TURISMO_TRX_RAM_03_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21425;"	d
+RG_TURISMO_TRX_RAM_04_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21429;"	d
+RG_TURISMO_TRX_RAM_04_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21427;"	d
+RG_TURISMO_TRX_RAM_04_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21426;"	d
+RG_TURISMO_TRX_RAM_04_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21428;"	d
+RG_TURISMO_TRX_RAM_04_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21430;"	d
+RG_TURISMO_TRX_RAM_05_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21434;"	d
+RG_TURISMO_TRX_RAM_05_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21432;"	d
+RG_TURISMO_TRX_RAM_05_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21431;"	d
+RG_TURISMO_TRX_RAM_05_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21433;"	d
+RG_TURISMO_TRX_RAM_05_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21435;"	d
+RG_TURISMO_TRX_RAM_06_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21439;"	d
+RG_TURISMO_TRX_RAM_06_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21437;"	d
+RG_TURISMO_TRX_RAM_06_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21436;"	d
+RG_TURISMO_TRX_RAM_06_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21438;"	d
+RG_TURISMO_TRX_RAM_06_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21440;"	d
+RG_TURISMO_TRX_RAM_07_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21444;"	d
+RG_TURISMO_TRX_RAM_07_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21442;"	d
+RG_TURISMO_TRX_RAM_07_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21441;"	d
+RG_TURISMO_TRX_RAM_07_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21443;"	d
+RG_TURISMO_TRX_RAM_07_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21445;"	d
+RG_TURISMO_TRX_RAM_08_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21449;"	d
+RG_TURISMO_TRX_RAM_08_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21447;"	d
+RG_TURISMO_TRX_RAM_08_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21446;"	d
+RG_TURISMO_TRX_RAM_08_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21448;"	d
+RG_TURISMO_TRX_RAM_08_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21450;"	d
+RG_TURISMO_TRX_RAM_09_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21454;"	d
+RG_TURISMO_TRX_RAM_09_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21452;"	d
+RG_TURISMO_TRX_RAM_09_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21451;"	d
+RG_TURISMO_TRX_RAM_09_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21453;"	d
+RG_TURISMO_TRX_RAM_09_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21455;"	d
+RG_TURISMO_TRX_RAM_10_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21459;"	d
+RG_TURISMO_TRX_RAM_10_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21457;"	d
+RG_TURISMO_TRX_RAM_10_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21456;"	d
+RG_TURISMO_TRX_RAM_10_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21458;"	d
+RG_TURISMO_TRX_RAM_10_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21460;"	d
+RG_TURISMO_TRX_RAM_11_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21464;"	d
+RG_TURISMO_TRX_RAM_11_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21462;"	d
+RG_TURISMO_TRX_RAM_11_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21461;"	d
+RG_TURISMO_TRX_RAM_11_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21463;"	d
+RG_TURISMO_TRX_RAM_11_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21465;"	d
+RG_TURISMO_TRX_RAM_12_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21469;"	d
+RG_TURISMO_TRX_RAM_12_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21467;"	d
+RG_TURISMO_TRX_RAM_12_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21466;"	d
+RG_TURISMO_TRX_RAM_12_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21468;"	d
+RG_TURISMO_TRX_RAM_12_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21470;"	d
+RG_TURISMO_TRX_RAM_13_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21474;"	d
+RG_TURISMO_TRX_RAM_13_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21472;"	d
+RG_TURISMO_TRX_RAM_13_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21471;"	d
+RG_TURISMO_TRX_RAM_13_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21473;"	d
+RG_TURISMO_TRX_RAM_13_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21475;"	d
+RG_TURISMO_TRX_RAM_14_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21479;"	d
+RG_TURISMO_TRX_RAM_14_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21477;"	d
+RG_TURISMO_TRX_RAM_14_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21476;"	d
+RG_TURISMO_TRX_RAM_14_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21478;"	d
+RG_TURISMO_TRX_RAM_14_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21480;"	d
+RG_TURISMO_TRX_RAM_15_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21484;"	d
+RG_TURISMO_TRX_RAM_15_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21482;"	d
+RG_TURISMO_TRX_RAM_15_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21481;"	d
+RG_TURISMO_TRX_RAM_15_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21483;"	d
+RG_TURISMO_TRX_RAM_15_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21485;"	d
+RG_TURISMO_TRX_RAM_16_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21489;"	d
+RG_TURISMO_TRX_RAM_16_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21487;"	d
+RG_TURISMO_TRX_RAM_16_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21486;"	d
+RG_TURISMO_TRX_RAM_16_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21488;"	d
+RG_TURISMO_TRX_RAM_16_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21490;"	d
+RG_TURISMO_TRX_RAM_17_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21494;"	d
+RG_TURISMO_TRX_RAM_17_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21492;"	d
+RG_TURISMO_TRX_RAM_17_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21491;"	d
+RG_TURISMO_TRX_RAM_17_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21493;"	d
+RG_TURISMO_TRX_RAM_17_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21495;"	d
+RG_TURISMO_TRX_RAM_18_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21499;"	d
+RG_TURISMO_TRX_RAM_18_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21497;"	d
+RG_TURISMO_TRX_RAM_18_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21496;"	d
+RG_TURISMO_TRX_RAM_18_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21498;"	d
+RG_TURISMO_TRX_RAM_18_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21500;"	d
+RG_TURISMO_TRX_RAM_19_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21504;"	d
+RG_TURISMO_TRX_RAM_19_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21502;"	d
+RG_TURISMO_TRX_RAM_19_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21501;"	d
+RG_TURISMO_TRX_RAM_19_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21503;"	d
+RG_TURISMO_TRX_RAM_19_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21505;"	d
+RG_TURISMO_TRX_RAM_20_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21509;"	d
+RG_TURISMO_TRX_RAM_20_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21507;"	d
+RG_TURISMO_TRX_RAM_20_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21506;"	d
+RG_TURISMO_TRX_RAM_20_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21508;"	d
+RG_TURISMO_TRX_RAM_20_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21510;"	d
+RG_TURISMO_TRX_RAM_21_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21514;"	d
+RG_TURISMO_TRX_RAM_21_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21512;"	d
+RG_TURISMO_TRX_RAM_21_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21511;"	d
+RG_TURISMO_TRX_RAM_21_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21513;"	d
+RG_TURISMO_TRX_RAM_21_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21515;"	d
+RG_TURISMO_TRX_RAM_22_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21519;"	d
+RG_TURISMO_TRX_RAM_22_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21517;"	d
+RG_TURISMO_TRX_RAM_22_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21516;"	d
+RG_TURISMO_TRX_RAM_22_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21518;"	d
+RG_TURISMO_TRX_RAM_22_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21520;"	d
+RG_TURISMO_TRX_RAM_23_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21524;"	d
+RG_TURISMO_TRX_RAM_23_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21522;"	d
+RG_TURISMO_TRX_RAM_23_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21521;"	d
+RG_TURISMO_TRX_RAM_23_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21523;"	d
+RG_TURISMO_TRX_RAM_23_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21525;"	d
+RG_TURISMO_TRX_RAM_24_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21529;"	d
+RG_TURISMO_TRX_RAM_24_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21527;"	d
+RG_TURISMO_TRX_RAM_24_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21526;"	d
+RG_TURISMO_TRX_RAM_24_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21528;"	d
+RG_TURISMO_TRX_RAM_24_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21530;"	d
+RG_TURISMO_TRX_RAM_25_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21534;"	d
+RG_TURISMO_TRX_RAM_25_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21532;"	d
+RG_TURISMO_TRX_RAM_25_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21531;"	d
+RG_TURISMO_TRX_RAM_25_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21533;"	d
+RG_TURISMO_TRX_RAM_25_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21535;"	d
+RG_TURISMO_TRX_RAM_26_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21539;"	d
+RG_TURISMO_TRX_RAM_26_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21537;"	d
+RG_TURISMO_TRX_RAM_26_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21536;"	d
+RG_TURISMO_TRX_RAM_26_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21538;"	d
+RG_TURISMO_TRX_RAM_26_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21540;"	d
+RG_TURISMO_TRX_RAM_27_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21544;"	d
+RG_TURISMO_TRX_RAM_27_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21542;"	d
+RG_TURISMO_TRX_RAM_27_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21541;"	d
+RG_TURISMO_TRX_RAM_27_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21543;"	d
+RG_TURISMO_TRX_RAM_27_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21545;"	d
+RG_TURISMO_TRX_RAM_28_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21549;"	d
+RG_TURISMO_TRX_RAM_28_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21547;"	d
+RG_TURISMO_TRX_RAM_28_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21546;"	d
+RG_TURISMO_TRX_RAM_28_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21548;"	d
+RG_TURISMO_TRX_RAM_28_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21550;"	d
+RG_TURISMO_TRX_RAM_29_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21554;"	d
+RG_TURISMO_TRX_RAM_29_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21552;"	d
+RG_TURISMO_TRX_RAM_29_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21551;"	d
+RG_TURISMO_TRX_RAM_29_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21553;"	d
+RG_TURISMO_TRX_RAM_29_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21555;"	d
+RG_TURISMO_TRX_RAM_30_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21559;"	d
+RG_TURISMO_TRX_RAM_30_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21557;"	d
+RG_TURISMO_TRX_RAM_30_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21556;"	d
+RG_TURISMO_TRX_RAM_30_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21558;"	d
+RG_TURISMO_TRX_RAM_30_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21560;"	d
+RG_TURISMO_TRX_RAM_31_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21564;"	d
+RG_TURISMO_TRX_RAM_31_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21562;"	d
+RG_TURISMO_TRX_RAM_31_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21561;"	d
+RG_TURISMO_TRX_RAM_31_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21563;"	d
+RG_TURISMO_TRX_RAM_31_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21565;"	d
+RG_TURISMO_TRX_RCCAL_POLAR_INV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20534;"	d
+RG_TURISMO_TRX_RCCAL_POLAR_INV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20532;"	d
+RG_TURISMO_TRX_RCCAL_POLAR_INV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20531;"	d
+RG_TURISMO_TRX_RCCAL_POLAR_INV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20533;"	d
+RG_TURISMO_TRX_RCCAL_POLAR_INV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20535;"	d
+RG_TURISMO_TRX_RFG_DPDCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17894;"	d
+RG_TURISMO_TRX_RFG_DPDCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17892;"	d
+RG_TURISMO_TRX_RFG_DPDCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17891;"	d
+RG_TURISMO_TRX_RFG_DPDCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17893;"	d
+RG_TURISMO_TRX_RFG_DPDCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17895;"	d
+RG_TURISMO_TRX_RFG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14649;"	d
+RG_TURISMO_TRX_RFG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14647;"	d
+RG_TURISMO_TRX_RFG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14646;"	d
+RG_TURISMO_TRX_RFG_RXIQCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17879;"	d
+RG_TURISMO_TRX_RFG_RXIQCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17877;"	d
+RG_TURISMO_TRX_RFG_RXIQCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17876;"	d
+RG_TURISMO_TRX_RFG_RXIQCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17878;"	d
+RG_TURISMO_TRX_RFG_RXIQCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17880;"	d
+RG_TURISMO_TRX_RFG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14648;"	d
+RG_TURISMO_TRX_RFG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14650;"	d
+RG_TURISMO_TRX_RF_PHY_MODE_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21379;"	d
+RG_TURISMO_TRX_RF_PHY_MODE_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21377;"	d
+RG_TURISMO_TRX_RF_PHY_MODE_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21376;"	d
+RG_TURISMO_TRX_RF_PHY_MODE_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21378;"	d
+RG_TURISMO_TRX_RF_PHY_MODE_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21380;"	d
+RG_TURISMO_TRX_RF_PHY_MODE_WIFI_MAC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21384;"	d
+RG_TURISMO_TRX_RF_PHY_MODE_WIFI_MAC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21382;"	d
+RG_TURISMO_TRX_RF_PHY_MODE_WIFI_MAC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21381;"	d
+RG_TURISMO_TRX_RF_PHY_MODE_WIFI_MAC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21383;"	d
+RG_TURISMO_TRX_RF_PHY_MODE_WIFI_MAC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21385;"	d
+RG_TURISMO_TRX_RSSI_CLOCK_GATING_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15254;"	d
+RG_TURISMO_TRX_RSSI_CLOCK_GATING_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15252;"	d
+RG_TURISMO_TRX_RSSI_CLOCK_GATING_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15251;"	d
+RG_TURISMO_TRX_RSSI_CLOCK_GATING_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15253;"	d
+RG_TURISMO_TRX_RSSI_CLOCK_GATING_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15255;"	d
+RG_TURISMO_TRX_RSSI_EDGE_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20204;"	d
+RG_TURISMO_TRX_RSSI_EDGE_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20202;"	d
+RG_TURISMO_TRX_RSSI_EDGE_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20201;"	d
+RG_TURISMO_TRX_RSSI_EDGE_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20203;"	d
+RG_TURISMO_TRX_RSSI_EDGE_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20205;"	d
+RG_TURISMO_TRX_RTC_CAL_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20889;"	d
+RG_TURISMO_TRX_RTC_CAL_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20887;"	d
+RG_TURISMO_TRX_RTC_CAL_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20886;"	d
+RG_TURISMO_TRX_RTC_CAL_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20888;"	d
+RG_TURISMO_TRX_RTC_CAL_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20890;"	d
+RG_TURISMO_TRX_RTC_CAL_TARGET_COUNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20879;"	d
+RG_TURISMO_TRX_RTC_CAL_TARGET_COUNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20877;"	d
+RG_TURISMO_TRX_RTC_CAL_TARGET_COUNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20876;"	d
+RG_TURISMO_TRX_RTC_CAL_TARGET_COUNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20878;"	d
+RG_TURISMO_TRX_RTC_CAL_TARGET_COUNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20880;"	d
+RG_TURISMO_TRX_RTC_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20964;"	d
+RG_TURISMO_TRX_RTC_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20962;"	d
+RG_TURISMO_TRX_RTC_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20961;"	d
+RG_TURISMO_TRX_RTC_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20963;"	d
+RG_TURISMO_TRX_RTC_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20965;"	d
+RG_TURISMO_TRX_RTC_INT_ALARM_MASK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20979;"	d
+RG_TURISMO_TRX_RTC_INT_ALARM_MASK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20977;"	d
+RG_TURISMO_TRX_RTC_INT_ALARM_MASK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20976;"	d
+RG_TURISMO_TRX_RTC_INT_ALARM_MASK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20978;"	d
+RG_TURISMO_TRX_RTC_INT_ALARM_MASK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20980;"	d
+RG_TURISMO_TRX_RTC_INT_SEC_MASK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20974;"	d
+RG_TURISMO_TRX_RTC_INT_SEC_MASK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20972;"	d
+RG_TURISMO_TRX_RTC_INT_SEC_MASK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20971;"	d
+RG_TURISMO_TRX_RTC_INT_SEC_MASK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20973;"	d
+RG_TURISMO_TRX_RTC_INT_SEC_MASK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20975;"	d
+RG_TURISMO_TRX_RTC_OFFSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20874;"	d
+RG_TURISMO_TRX_RTC_OFFSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20872;"	d
+RG_TURISMO_TRX_RTC_OFFSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20871;"	d
+RG_TURISMO_TRX_RTC_OFFSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20873;"	d
+RG_TURISMO_TRX_RTC_OFFSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20875;"	d
+RG_TURISMO_TRX_RTC_OSC_RES_SW_MANUAL_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20899;"	d
+RG_TURISMO_TRX_RTC_OSC_RES_SW_MANUAL_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20897;"	d
+RG_TURISMO_TRX_RTC_OSC_RES_SW_MANUAL_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20896;"	d
+RG_TURISMO_TRX_RTC_OSC_RES_SW_MANUAL_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20898;"	d
+RG_TURISMO_TRX_RTC_OSC_RES_SW_MANUAL_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20900;"	d
+RG_TURISMO_TRX_RTC_OSC_RES_SW_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20884;"	d
+RG_TURISMO_TRX_RTC_OSC_RES_SW_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20882;"	d
+RG_TURISMO_TRX_RTC_OSC_RES_SW_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20881;"	d
+RG_TURISMO_TRX_RTC_OSC_RES_SW_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20883;"	d
+RG_TURISMO_TRX_RTC_OSC_RES_SW_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20885;"	d
+RG_TURISMO_TRX_RTC_RS1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20849;"	d
+RG_TURISMO_TRX_RTC_RS1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20847;"	d
+RG_TURISMO_TRX_RTC_RS1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20846;"	d
+RG_TURISMO_TRX_RTC_RS1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20848;"	d
+RG_TURISMO_TRX_RTC_RS1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20850;"	d
+RG_TURISMO_TRX_RTC_RS2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20854;"	d
+RG_TURISMO_TRX_RTC_RS2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20852;"	d
+RG_TURISMO_TRX_RTC_RS2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20851;"	d
+RG_TURISMO_TRX_RTC_RS2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20853;"	d
+RG_TURISMO_TRX_RTC_RS2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20855;"	d
+RG_TURISMO_TRX_RTC_SEC_ALARM_VALUE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21004;"	d
+RG_TURISMO_TRX_RTC_SEC_ALARM_VALUE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21002;"	d
+RG_TURISMO_TRX_RTC_SEC_ALARM_VALUE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21001;"	d
+RG_TURISMO_TRX_RTC_SEC_ALARM_VALUE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21003;"	d
+RG_TURISMO_TRX_RTC_SEC_ALARM_VALUE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21005;"	d
+RG_TURISMO_TRX_RTC_SEC_START_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20999;"	d
+RG_TURISMO_TRX_RTC_SEC_START_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20997;"	d
+RG_TURISMO_TRX_RTC_SEC_START_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20996;"	d
+RG_TURISMO_TRX_RTC_SEC_START_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20998;"	d
+RG_TURISMO_TRX_RTC_SEC_START_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21000;"	d
+RG_TURISMO_TRX_RXIQ_NOSHRK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20184;"	d
+RG_TURISMO_TRX_RXIQ_NOSHRK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20182;"	d
+RG_TURISMO_TRX_RXIQ_NOSHRK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20181;"	d
+RG_TURISMO_TRX_RXIQ_NOSHRK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20183;"	d
+RG_TURISMO_TRX_RXIQ_NOSHRK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20185;"	d
+RG_TURISMO_TRX_RXRF_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17779;"	d
+RG_TURISMO_TRX_RXRF_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17777;"	d
+RG_TURISMO_TRX_RXRF_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17776;"	d
+RG_TURISMO_TRX_RXRF_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17778;"	d
+RG_TURISMO_TRX_RXRF_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17780;"	d
+RG_TURISMO_TRX_RXRF_R2T_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17824;"	d
+RG_TURISMO_TRX_RXRF_R2T_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17822;"	d
+RG_TURISMO_TRX_RXRF_R2T_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17821;"	d
+RG_TURISMO_TRX_RXRF_R2T_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17823;"	d
+RG_TURISMO_TRX_RXRF_R2T_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17825;"	d
+RG_TURISMO_TRX_RXRF_T2R_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17804;"	d
+RG_TURISMO_TRX_RXRF_T2R_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17802;"	d
+RG_TURISMO_TRX_RXRF_T2R_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17801;"	d
+RG_TURISMO_TRX_RXRF_T2R_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17803;"	d
+RG_TURISMO_TRX_RXRF_T2R_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17805;"	d
+RG_TURISMO_TRX_RX_ABBOUT_TRI_STATE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14934;"	d
+RG_TURISMO_TRX_RX_ABBOUT_TRI_STATE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14932;"	d
+RG_TURISMO_TRX_RX_ABBOUT_TRI_STATE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14931;"	d
+RG_TURISMO_TRX_RX_ABBOUT_TRI_STATE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14933;"	d
+RG_TURISMO_TRX_RX_ABBOUT_TRI_STATE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14935;"	d
+RG_TURISMO_TRX_RX_ADCRSSI_CLKSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15249;"	d
+RG_TURISMO_TRX_RX_ADCRSSI_CLKSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15247;"	d
+RG_TURISMO_TRX_RX_ADCRSSI_CLKSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15246;"	d
+RG_TURISMO_TRX_RX_ADCRSSI_CLKSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15248;"	d
+RG_TURISMO_TRX_RX_ADCRSSI_CLKSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15250;"	d
+RG_TURISMO_TRX_RX_ADCRSSI_VCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15239;"	d
+RG_TURISMO_TRX_RX_ADCRSSI_VCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15237;"	d
+RG_TURISMO_TRX_RX_ADCRSSI_VCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15236;"	d
+RG_TURISMO_TRX_RX_ADCRSSI_VCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15238;"	d
+RG_TURISMO_TRX_RX_ADCRSSI_VCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15240;"	d
+RG_TURISMO_TRX_RX_ADC_CLKSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15919;"	d
+RG_TURISMO_TRX_RX_ADC_CLKSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15917;"	d
+RG_TURISMO_TRX_RX_ADC_CLKSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15916;"	d
+RG_TURISMO_TRX_RX_ADC_CLKSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15918;"	d
+RG_TURISMO_TRX_RX_ADC_CLKSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15920;"	d
+RG_TURISMO_TRX_RX_ADC_DNLEN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15924;"	d
+RG_TURISMO_TRX_RX_ADC_DNLEN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15922;"	d
+RG_TURISMO_TRX_RX_ADC_DNLEN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15921;"	d
+RG_TURISMO_TRX_RX_ADC_DNLEN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15923;"	d
+RG_TURISMO_TRX_RX_ADC_DNLEN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15925;"	d
+RG_TURISMO_TRX_RX_ADC_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14744;"	d
+RG_TURISMO_TRX_RX_ADC_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14742;"	d
+RG_TURISMO_TRX_RX_ADC_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14741;"	d
+RG_TURISMO_TRX_RX_ADC_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14743;"	d
+RG_TURISMO_TRX_RX_ADC_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14745;"	d
+RG_TURISMO_TRX_RX_ADC_METAEN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15929;"	d
+RG_TURISMO_TRX_RX_ADC_METAEN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15927;"	d
+RG_TURISMO_TRX_RX_ADC_METAEN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15926;"	d
+RG_TURISMO_TRX_RX_ADC_METAEN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15928;"	d
+RG_TURISMO_TRX_RX_ADC_METAEN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15930;"	d
+RG_TURISMO_TRX_RX_ADC_TFLAG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15934;"	d
+RG_TURISMO_TRX_RX_ADC_TFLAG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15932;"	d
+RG_TURISMO_TRX_RX_ADC_TFLAG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15931;"	d
+RG_TURISMO_TRX_RX_ADC_TFLAG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15933;"	d
+RG_TURISMO_TRX_RX_ADC_TFLAG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15935;"	d
+RG_TURISMO_TRX_RX_ADC_TSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15939;"	d
+RG_TURISMO_TRX_RX_ADC_TSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15937;"	d
+RG_TURISMO_TRX_RX_ADC_TSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15936;"	d
+RG_TURISMO_TRX_RX_ADC_TSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15938;"	d
+RG_TURISMO_TRX_RX_ADC_TSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15940;"	d
+RG_TURISMO_TRX_RX_AGC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14634;"	d
+RG_TURISMO_TRX_RX_AGC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14632;"	d
+RG_TURISMO_TRX_RX_AGC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14631;"	d
+RG_TURISMO_TRX_RX_AGC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14633;"	d
+RG_TURISMO_TRX_RX_AGC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14635;"	d
+RG_TURISMO_TRX_RX_DC_POLAR_INV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20529;"	d
+RG_TURISMO_TRX_RX_DC_POLAR_INV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20527;"	d
+RG_TURISMO_TRX_RX_DC_POLAR_INV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20526;"	d
+RG_TURISMO_TRX_RX_DC_POLAR_INV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20528;"	d
+RG_TURISMO_TRX_RX_DC_POLAR_INV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20530;"	d
+RG_TURISMO_TRX_RX_DC_RESOLUTION_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20539;"	d
+RG_TURISMO_TRX_RX_DC_RESOLUTION_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20537;"	d
+RG_TURISMO_TRX_RX_DC_RESOLUTION_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20536;"	d
+RG_TURISMO_TRX_RX_DC_RESOLUTION_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20538;"	d
+RG_TURISMO_TRX_RX_DC_RESOLUTION_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20540;"	d
+RG_TURISMO_TRX_RX_DIV2_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14704;"	d
+RG_TURISMO_TRX_RX_DIV2_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14702;"	d
+RG_TURISMO_TRX_RX_DIV2_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14701;"	d
+RG_TURISMO_TRX_RX_DIV2_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14703;"	d
+RG_TURISMO_TRX_RX_DIV2_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14705;"	d
+RG_TURISMO_TRX_RX_FILTER_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14734;"	d
+RG_TURISMO_TRX_RX_FILTER_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14732;"	d
+RG_TURISMO_TRX_RX_FILTER_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14731;"	d
+RG_TURISMO_TRX_RX_FILTER_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14733;"	d
+RG_TURISMO_TRX_RX_FILTER_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14735;"	d
+RG_TURISMO_TRX_RX_GAIN_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14619;"	d
+RG_TURISMO_TRX_RX_GAIN_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14617;"	d
+RG_TURISMO_TRX_RX_GAIN_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14616;"	d
+RG_TURISMO_TRX_RX_GAIN_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14618;"	d
+RG_TURISMO_TRX_RX_GAIN_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14620;"	d
+RG_TURISMO_TRX_RX_IDACA_COARSE_PMOS_ON_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15259;"	d
+RG_TURISMO_TRX_RX_IDACA_COARSE_PMOS_ON_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15257;"	d
+RG_TURISMO_TRX_RX_IDACA_COARSE_PMOS_ON_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15256;"	d
+RG_TURISMO_TRX_RX_IDACA_COARSE_PMOS_ON_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15258;"	d
+RG_TURISMO_TRX_RX_IDACA_COARSE_PMOS_ON_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15260;"	d
+RG_TURISMO_TRX_RX_IQCAL_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17854;"	d
+RG_TURISMO_TRX_RX_IQCAL_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17852;"	d
+RG_TURISMO_TRX_RX_IQCAL_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17851;"	d
+RG_TURISMO_TRX_RX_IQCAL_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17853;"	d
+RG_TURISMO_TRX_RX_IQCAL_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17855;"	d
+RG_TURISMO_TRX_RX_IQCAL_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14879;"	d
+RG_TURISMO_TRX_RX_IQCAL_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14877;"	d
+RG_TURISMO_TRX_RX_IQCAL_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14876;"	d
+RG_TURISMO_TRX_RX_IQCAL_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14878;"	d
+RG_TURISMO_TRX_RX_IQCAL_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14880;"	d
+RG_TURISMO_TRX_RX_IQ_ALPHA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20169;"	d
+RG_TURISMO_TRX_RX_IQ_ALPHA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20167;"	d
+RG_TURISMO_TRX_RX_IQ_ALPHA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20166;"	d
+RG_TURISMO_TRX_RX_IQ_ALPHA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20168;"	d
+RG_TURISMO_TRX_RX_IQ_ALPHA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20170;"	d
+RG_TURISMO_TRX_RX_IQ_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20179;"	d
+RG_TURISMO_TRX_RX_IQ_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20177;"	d
+RG_TURISMO_TRX_RX_IQ_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20176;"	d
+RG_TURISMO_TRX_RX_IQ_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20178;"	d
+RG_TURISMO_TRX_RX_IQ_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20180;"	d
+RG_TURISMO_TRX_RX_IQ_THETA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20174;"	d
+RG_TURISMO_TRX_RX_IQ_THETA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20172;"	d
+RG_TURISMO_TRX_RX_IQ_THETA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20171;"	d
+RG_TURISMO_TRX_RX_IQ_THETA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20173;"	d
+RG_TURISMO_TRX_RX_IQ_THETA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20175;"	d
+RG_TURISMO_TRX_RX_LNA_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14684;"	d
+RG_TURISMO_TRX_RX_LNA_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14682;"	d
+RG_TURISMO_TRX_RX_LNA_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14681;"	d
+RG_TURISMO_TRX_RX_LNA_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14683;"	d
+RG_TURISMO_TRX_RX_LNA_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14685;"	d
+RG_TURISMO_TRX_RX_LNA_SETTLE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15304;"	d
+RG_TURISMO_TRX_RX_LNA_SETTLE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15302;"	d
+RG_TURISMO_TRX_RX_LNA_SETTLE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15301;"	d
+RG_TURISMO_TRX_RX_LNA_SETTLE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15303;"	d
+RG_TURISMO_TRX_RX_LNA_SETTLE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15305;"	d
+RG_TURISMO_TRX_RX_LNA_TRI_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15299;"	d
+RG_TURISMO_TRX_RX_LNA_TRI_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15297;"	d
+RG_TURISMO_TRX_RX_LNA_TRI_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15296;"	d
+RG_TURISMO_TRX_RX_LNA_TRI_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15298;"	d
+RG_TURISMO_TRX_RX_LNA_TRI_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15300;"	d
+RG_TURISMO_TRX_RX_LOBUF_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14714;"	d
+RG_TURISMO_TRX_RX_LOBUF_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14712;"	d
+RG_TURISMO_TRX_RX_LOBUF_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14711;"	d
+RG_TURISMO_TRX_RX_LOBUF_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14713;"	d
+RG_TURISMO_TRX_RX_LOBUF_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14715;"	d
+RG_TURISMO_TRX_RX_MIXER_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14694;"	d
+RG_TURISMO_TRX_RX_MIXER_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14692;"	d
+RG_TURISMO_TRX_RX_MIXER_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14691;"	d
+RG_TURISMO_TRX_RX_MIXER_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14693;"	d
+RG_TURISMO_TRX_RX_MIXER_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14695;"	d
+RG_TURISMO_TRX_RX_N_RCCAL_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17859;"	d
+RG_TURISMO_TRX_RX_N_RCCAL_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17857;"	d
+RG_TURISMO_TRX_RX_N_RCCAL_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17856;"	d
+RG_TURISMO_TRX_RX_N_RCCAL_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17858;"	d
+RG_TURISMO_TRX_RX_N_RCCAL_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17860;"	d
+RG_TURISMO_TRX_RX_PRE_DC_RESOLUTION_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20579;"	d
+RG_TURISMO_TRX_RX_PRE_DC_RESOLUTION_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20577;"	d
+RG_TURISMO_TRX_RX_PRE_DC_RESOLUTION_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20576;"	d
+RG_TURISMO_TRX_RX_PRE_DC_RESOLUTION_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20578;"	d
+RG_TURISMO_TRX_RX_PRE_DC_RESOLUTION_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20580;"	d
+RG_TURISMO_TRX_RX_RCCAL_40M_TARG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20544;"	d
+RG_TURISMO_TRX_RX_RCCAL_40M_TARG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20542;"	d
+RG_TURISMO_TRX_RX_RCCAL_40M_TARG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20541;"	d
+RG_TURISMO_TRX_RX_RCCAL_40M_TARG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20543;"	d
+RG_TURISMO_TRX_RX_RCCAL_40M_TARG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20545;"	d
+RG_TURISMO_TRX_RX_RCCAL_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17839;"	d
+RG_TURISMO_TRX_RX_RCCAL_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17837;"	d
+RG_TURISMO_TRX_RX_RCCAL_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17836;"	d
+RG_TURISMO_TRX_RX_RCCAL_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17838;"	d
+RG_TURISMO_TRX_RX_RCCAL_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17840;"	d
+RG_TURISMO_TRX_RX_RCCAL_TARG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20524;"	d
+RG_TURISMO_TRX_RX_RCCAL_TARG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20522;"	d
+RG_TURISMO_TRX_RX_RCCAL_TARG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20521;"	d
+RG_TURISMO_TRX_RX_RCCAL_TARG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20523;"	d
+RG_TURISMO_TRX_RX_RCCAL_TARG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20525;"	d
+RG_TURISMO_TRX_RX_REC_LPFCORNER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15244;"	d
+RG_TURISMO_TRX_RX_REC_LPFCORNER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15242;"	d
+RG_TURISMO_TRX_RX_REC_LPFCORNER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15241;"	d
+RG_TURISMO_TRX_RX_REC_LPFCORNER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15243;"	d
+RG_TURISMO_TRX_RX_REC_LPFCORNER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15245;"	d
+RG_TURISMO_TRX_RX_RSSIADC_TH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20189;"	d
+RG_TURISMO_TRX_RX_RSSIADC_TH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20187;"	d
+RG_TURISMO_TRX_RX_RSSIADC_TH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20186;"	d
+RG_TURISMO_TRX_RX_RSSIADC_TH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20188;"	d
+RG_TURISMO_TRX_RX_RSSIADC_TH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20190;"	d
+RG_TURISMO_TRX_RX_RSSI_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14754;"	d
+RG_TURISMO_TRX_RX_RSSI_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14752;"	d
+RG_TURISMO_TRX_RX_RSSI_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14751;"	d
+RG_TURISMO_TRX_RX_RSSI_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14753;"	d
+RG_TURISMO_TRX_RX_RSSI_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14755;"	d
+RG_TURISMO_TRX_RX_SCALOAD_STEP0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20079;"	d
+RG_TURISMO_TRX_RX_SCALOAD_STEP0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20077;"	d
+RG_TURISMO_TRX_RX_SCALOAD_STEP0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20076;"	d
+RG_TURISMO_TRX_RX_SCALOAD_STEP0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20078;"	d
+RG_TURISMO_TRX_RX_SCALOAD_STEP0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20080;"	d
+RG_TURISMO_TRX_RX_SCALOAD_STEP1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20084;"	d
+RG_TURISMO_TRX_RX_SCALOAD_STEP1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20082;"	d
+RG_TURISMO_TRX_RX_SCALOAD_STEP1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20081;"	d
+RG_TURISMO_TRX_RX_SCALOAD_STEP1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20083;"	d
+RG_TURISMO_TRX_RX_SCALOAD_STEP1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20085;"	d
+RG_TURISMO_TRX_RX_SCALOAD_STEP2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20089;"	d
+RG_TURISMO_TRX_RX_SCALOAD_STEP2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20087;"	d
+RG_TURISMO_TRX_RX_SCALOAD_STEP2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20086;"	d
+RG_TURISMO_TRX_RX_SCALOAD_STEP2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20088;"	d
+RG_TURISMO_TRX_RX_SCALOAD_STEP2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20090;"	d
+RG_TURISMO_TRX_RX_SCALOAD_STEP3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20094;"	d
+RG_TURISMO_TRX_RX_SCALOAD_STEP3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20092;"	d
+RG_TURISMO_TRX_RX_SCALOAD_STEP3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20091;"	d
+RG_TURISMO_TRX_RX_SCALOAD_STEP3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20093;"	d
+RG_TURISMO_TRX_RX_SCALOAD_STEP3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20095;"	d
+RG_TURISMO_TRX_RX_SCALOAD_STEP4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20099;"	d
+RG_TURISMO_TRX_RX_SCALOAD_STEP4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20097;"	d
+RG_TURISMO_TRX_RX_SCALOAD_STEP4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20096;"	d
+RG_TURISMO_TRX_RX_SCALOAD_STEP4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20098;"	d
+RG_TURISMO_TRX_RX_SCALOAD_STEP4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20100;"	d
+RG_TURISMO_TRX_RX_SCALOAD_STEP5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20104;"	d
+RG_TURISMO_TRX_RX_SCALOAD_STEP5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20102;"	d
+RG_TURISMO_TRX_RX_SCALOAD_STEP5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20101;"	d
+RG_TURISMO_TRX_RX_SCALOAD_STEP5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20103;"	d
+RG_TURISMO_TRX_RX_SCALOAD_STEP5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20105;"	d
+RG_TURISMO_TRX_RX_SCALOAD_STEP6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20109;"	d
+RG_TURISMO_TRX_RX_SCALOAD_STEP6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20107;"	d
+RG_TURISMO_TRX_RX_SCALOAD_STEP6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20106;"	d
+RG_TURISMO_TRX_RX_SCALOAD_STEP6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20108;"	d
+RG_TURISMO_TRX_RX_SCALOAD_STEP6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20110;"	d
+RG_TURISMO_TRX_RX_SCAMA_STEP0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20044;"	d
+RG_TURISMO_TRX_RX_SCAMA_STEP0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20042;"	d
+RG_TURISMO_TRX_RX_SCAMA_STEP0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20041;"	d
+RG_TURISMO_TRX_RX_SCAMA_STEP0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20043;"	d
+RG_TURISMO_TRX_RX_SCAMA_STEP0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20045;"	d
+RG_TURISMO_TRX_RX_SCAMA_STEP1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20049;"	d
+RG_TURISMO_TRX_RX_SCAMA_STEP1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20047;"	d
+RG_TURISMO_TRX_RX_SCAMA_STEP1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20046;"	d
+RG_TURISMO_TRX_RX_SCAMA_STEP1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20048;"	d
+RG_TURISMO_TRX_RX_SCAMA_STEP1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20050;"	d
+RG_TURISMO_TRX_RX_SCAMA_STEP2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20054;"	d
+RG_TURISMO_TRX_RX_SCAMA_STEP2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20052;"	d
+RG_TURISMO_TRX_RX_SCAMA_STEP2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20051;"	d
+RG_TURISMO_TRX_RX_SCAMA_STEP2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20053;"	d
+RG_TURISMO_TRX_RX_SCAMA_STEP2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20055;"	d
+RG_TURISMO_TRX_RX_SCAMA_STEP3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20059;"	d
+RG_TURISMO_TRX_RX_SCAMA_STEP3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20057;"	d
+RG_TURISMO_TRX_RX_SCAMA_STEP3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20056;"	d
+RG_TURISMO_TRX_RX_SCAMA_STEP3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20058;"	d
+RG_TURISMO_TRX_RX_SCAMA_STEP3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20060;"	d
+RG_TURISMO_TRX_RX_SCAMA_STEP4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20064;"	d
+RG_TURISMO_TRX_RX_SCAMA_STEP4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20062;"	d
+RG_TURISMO_TRX_RX_SCAMA_STEP4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20061;"	d
+RG_TURISMO_TRX_RX_SCAMA_STEP4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20063;"	d
+RG_TURISMO_TRX_RX_SCAMA_STEP4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20065;"	d
+RG_TURISMO_TRX_RX_SCAMA_STEP5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20069;"	d
+RG_TURISMO_TRX_RX_SCAMA_STEP5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20067;"	d
+RG_TURISMO_TRX_RX_SCAMA_STEP5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20066;"	d
+RG_TURISMO_TRX_RX_SCAMA_STEP5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20068;"	d
+RG_TURISMO_TRX_RX_SCAMA_STEP5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20070;"	d
+RG_TURISMO_TRX_RX_SCAMA_STEP6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20074;"	d
+RG_TURISMO_TRX_RX_SCAMA_STEP6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20072;"	d
+RG_TURISMO_TRX_RX_SCAMA_STEP6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20071;"	d
+RG_TURISMO_TRX_RX_SCAMA_STEP6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20073;"	d
+RG_TURISMO_TRX_RX_SCAMA_STEP6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20075;"	d
+RG_TURISMO_TRX_RX_SQDC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14969;"	d
+RG_TURISMO_TRX_RX_SQDC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14967;"	d
+RG_TURISMO_TRX_RX_SQDC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14966;"	d
+RG_TURISMO_TRX_RX_SQDC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14968;"	d
+RG_TURISMO_TRX_RX_SQDC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14970;"	d
+RG_TURISMO_TRX_RX_TZ_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14724;"	d
+RG_TURISMO_TRX_RX_TZ_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14722;"	d
+RG_TURISMO_TRX_RX_TZ_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14721;"	d
+RG_TURISMO_TRX_RX_TZ_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14723;"	d
+RG_TURISMO_TRX_RX_TZ_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14725;"	d
+RG_TURISMO_TRX_RX_TZ_OUT_TRISTATE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14864;"	d
+RG_TURISMO_TRX_RX_TZ_OUT_TRISTATE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14862;"	d
+RG_TURISMO_TRX_RX_TZ_OUT_TRISTATE_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14859;"	d
+RG_TURISMO_TRX_RX_TZ_OUT_TRISTATE_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14857;"	d
+RG_TURISMO_TRX_RX_TZ_OUT_TRISTATE_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14856;"	d
+RG_TURISMO_TRX_RX_TZ_OUT_TRISTATE_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14858;"	d
+RG_TURISMO_TRX_RX_TZ_OUT_TRISTATE_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14860;"	d
+RG_TURISMO_TRX_RX_TZ_OUT_TRISTATE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14861;"	d
+RG_TURISMO_TRX_RX_TZ_OUT_TRISTATE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14863;"	d
+RG_TURISMO_TRX_RX_TZ_OUT_TRISTATE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14865;"	d
+RG_TURISMO_TRX_SARADC_5G_TSSI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15974;"	d
+RG_TURISMO_TRX_SARADC_5G_TSSI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15972;"	d
+RG_TURISMO_TRX_SARADC_5G_TSSI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15971;"	d
+RG_TURISMO_TRX_SARADC_5G_TSSI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15973;"	d
+RG_TURISMO_TRX_SARADC_5G_TSSI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15975;"	d
+RG_TURISMO_TRX_SARADC_THERMAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15989;"	d
+RG_TURISMO_TRX_SARADC_THERMAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15987;"	d
+RG_TURISMO_TRX_SARADC_THERMAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15986;"	d
+RG_TURISMO_TRX_SARADC_THERMAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15988;"	d
+RG_TURISMO_TRX_SARADC_THERMAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15990;"	d
+RG_TURISMO_TRX_SARADC_TSSI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15994;"	d
+RG_TURISMO_TRX_SARADC_TSSI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15992;"	d
+RG_TURISMO_TRX_SARADC_TSSI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15991;"	d
+RG_TURISMO_TRX_SARADC_TSSI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15993;"	d
+RG_TURISMO_TRX_SARADC_TSSI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15995;"	d
+RG_TURISMO_TRX_SARADC_VRSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15979;"	d
+RG_TURISMO_TRX_SARADC_VRSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15977;"	d
+RG_TURISMO_TRX_SARADC_VRSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15976;"	d
+RG_TURISMO_TRX_SARADC_VRSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15978;"	d
+RG_TURISMO_TRX_SARADC_VRSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15980;"	d
+RG_TURISMO_TRX_SEC_CNT_VALUE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20959;"	d
+RG_TURISMO_TRX_SEC_CNT_VALUE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20957;"	d
+RG_TURISMO_TRX_SEC_CNT_VALUE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20956;"	d
+RG_TURISMO_TRX_SEC_CNT_VALUE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20958;"	d
+RG_TURISMO_TRX_SEC_CNT_VALUE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20960;"	d
+RG_TURISMO_TRX_SEL_DPLL_CLK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20894;"	d
+RG_TURISMO_TRX_SEL_DPLL_CLK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20892;"	d
+RG_TURISMO_TRX_SEL_DPLL_CLK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20891;"	d
+RG_TURISMO_TRX_SEL_DPLL_CLK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20893;"	d
+RG_TURISMO_TRX_SEL_DPLL_CLK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20895;"	d
+RG_TURISMO_TRX_SIGN_SWAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20229;"	d
+RG_TURISMO_TRX_SIGN_SWAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20227;"	d
+RG_TURISMO_TRX_SIGN_SWAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20226;"	d
+RG_TURISMO_TRX_SIGN_SWAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20228;"	d
+RG_TURISMO_TRX_SIGN_SWAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20230;"	d
+RG_TURISMO_TRX_SLEEP_METHOD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20944;"	d
+RG_TURISMO_TRX_SLEEP_METHOD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20942;"	d
+RG_TURISMO_TRX_SLEEP_METHOD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20941;"	d
+RG_TURISMO_TRX_SLEEP_METHOD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20943;"	d
+RG_TURISMO_TRX_SLEEP_METHOD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20945;"	d
+RG_TURISMO_TRX_SLEEP_WAKE_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20954;"	d
+RG_TURISMO_TRX_SLEEP_WAKE_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20952;"	d
+RG_TURISMO_TRX_SLEEP_WAKE_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20951;"	d
+RG_TURISMO_TRX_SLEEP_WAKE_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20953;"	d
+RG_TURISMO_TRX_SLEEP_WAKE_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20955;"	d
+RG_TURISMO_TRX_SPECTRUM_BW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20409;"	d
+RG_TURISMO_TRX_SPECTRUM_BW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20407;"	d
+RG_TURISMO_TRX_SPECTRUM_BW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20406;"	d
+RG_TURISMO_TRX_SPECTRUM_BW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20408;"	d
+RG_TURISMO_TRX_SPECTRUM_BW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20410;"	d
+RG_TURISMO_TRX_SPECTRUM_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20414;"	d
+RG_TURISMO_TRX_SPECTRUM_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20412;"	d
+RG_TURISMO_TRX_SPECTRUM_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20411;"	d
+RG_TURISMO_TRX_SPECTRUM_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20413;"	d
+RG_TURISMO_TRX_SPECTRUM_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20415;"	d
+RG_TURISMO_TRX_SPECTRUM_LO_FIX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20554;"	d
+RG_TURISMO_TRX_SPECTRUM_LO_FIX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20552;"	d
+RG_TURISMO_TRX_SPECTRUM_LO_FIX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20551;"	d
+RG_TURISMO_TRX_SPECTRUM_LO_FIX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20553;"	d
+RG_TURISMO_TRX_SPECTRUM_LO_FIX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20555;"	d
+RG_TURISMO_TRX_SPECTRUM_PWR_UPDATE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20559;"	d
+RG_TURISMO_TRX_SPECTRUM_PWR_UPDATE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20557;"	d
+RG_TURISMO_TRX_SPECTRUM_PWR_UPDATE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20556;"	d
+RG_TURISMO_TRX_SPECTRUM_PWR_UPDATE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20558;"	d
+RG_TURISMO_TRX_SPECTRUM_PWR_UPDATE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20560;"	d
+RG_TURISMO_TRX_SPIS_MISO_DS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21119;"	d
+RG_TURISMO_TRX_SPIS_MISO_DS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21117;"	d
+RG_TURISMO_TRX_SPIS_MISO_DS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21116;"	d
+RG_TURISMO_TRX_SPIS_MISO_DS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21118;"	d
+RG_TURISMO_TRX_SPIS_MISO_DS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21120;"	d
+RG_TURISMO_TRX_SUB_DC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20194;"	d
+RG_TURISMO_TRX_SUB_DC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20192;"	d
+RG_TURISMO_TRX_SUB_DC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20191;"	d
+RG_TURISMO_TRX_SUB_DC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20193;"	d
+RG_TURISMO_TRX_SUB_DC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20195;"	d
+RG_TURISMO_TRX_SX5GB_AAC_ACCUMH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19319;"	d
+RG_TURISMO_TRX_SX5GB_AAC_ACCUMH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19317;"	d
+RG_TURISMO_TRX_SX5GB_AAC_ACCUMH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19316;"	d
+RG_TURISMO_TRX_SX5GB_AAC_ACCUMH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19318;"	d
+RG_TURISMO_TRX_SX5GB_AAC_ACCUMH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19320;"	d
+RG_TURISMO_TRX_SX5GB_AAC_ACCUML_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19324;"	d
+RG_TURISMO_TRX_SX5GB_AAC_ACCUML_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19322;"	d
+RG_TURISMO_TRX_SX5GB_AAC_ACCUML_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19321;"	d
+RG_TURISMO_TRX_SX5GB_AAC_ACCUML_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19323;"	d
+RG_TURISMO_TRX_SX5GB_AAC_ACCUML_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19325;"	d
+RG_TURISMO_TRX_SX5GB_AAC_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19344;"	d
+RG_TURISMO_TRX_SX5GB_AAC_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19342;"	d
+RG_TURISMO_TRX_SX5GB_AAC_EN_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19339;"	d
+RG_TURISMO_TRX_SX5GB_AAC_EN_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19337;"	d
+RG_TURISMO_TRX_SX5GB_AAC_EN_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19336;"	d
+RG_TURISMO_TRX_SX5GB_AAC_EN_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19338;"	d
+RG_TURISMO_TRX_SX5GB_AAC_EN_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19340;"	d
+RG_TURISMO_TRX_SX5GB_AAC_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19341;"	d
+RG_TURISMO_TRX_SX5GB_AAC_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19343;"	d
+RG_TURISMO_TRX_SX5GB_AAC_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19345;"	d
+RG_TURISMO_TRX_SX5GB_AAC_EVA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19354;"	d
+RG_TURISMO_TRX_SX5GB_AAC_EVA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19352;"	d
+RG_TURISMO_TRX_SX5GB_AAC_EVA_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19349;"	d
+RG_TURISMO_TRX_SX5GB_AAC_EVA_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19347;"	d
+RG_TURISMO_TRX_SX5GB_AAC_EVA_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19346;"	d
+RG_TURISMO_TRX_SX5GB_AAC_EVA_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19348;"	d
+RG_TURISMO_TRX_SX5GB_AAC_EVA_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19350;"	d
+RG_TURISMO_TRX_SX5GB_AAC_EVA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19351;"	d
+RG_TURISMO_TRX_SX5GB_AAC_EVA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19353;"	d
+RG_TURISMO_TRX_SX5GB_AAC_EVA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19355;"	d
+RG_TURISMO_TRX_SX5GB_AAC_EVA_TS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19334;"	d
+RG_TURISMO_TRX_SX5GB_AAC_EVA_TS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19332;"	d
+RG_TURISMO_TRX_SX5GB_AAC_EVA_TS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19331;"	d
+RG_TURISMO_TRX_SX5GB_AAC_EVA_TS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19333;"	d
+RG_TURISMO_TRX_SX5GB_AAC_EVA_TS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19335;"	d
+RG_TURISMO_TRX_SX5GB_AAC_INIT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19329;"	d
+RG_TURISMO_TRX_SX5GB_AAC_INIT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19327;"	d
+RG_TURISMO_TRX_SX5GB_AAC_INIT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19326;"	d
+RG_TURISMO_TRX_SX5GB_AAC_INIT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19328;"	d
+RG_TURISMO_TRX_SX5GB_AAC_INIT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19330;"	d
+RG_TURISMO_TRX_SX5GB_AAC_TEST_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19384;"	d
+RG_TURISMO_TRX_SX5GB_AAC_TEST_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19382;"	d
+RG_TURISMO_TRX_SX5GB_AAC_TEST_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19381;"	d
+RG_TURISMO_TRX_SX5GB_AAC_TEST_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19383;"	d
+RG_TURISMO_TRX_SX5GB_AAC_TEST_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19385;"	d
+RG_TURISMO_TRX_SX5GB_AAC_TEST_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19389;"	d
+RG_TURISMO_TRX_SX5GB_AAC_TEST_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19387;"	d
+RG_TURISMO_TRX_SX5GB_AAC_TEST_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19386;"	d
+RG_TURISMO_TRX_SX5GB_AAC_TEST_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19388;"	d
+RG_TURISMO_TRX_SX5GB_AAC_TEST_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19390;"	d
+RG_TURISMO_TRX_SX5GB_CAL_INIT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18884;"	d
+RG_TURISMO_TRX_SX5GB_CAL_INIT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18882;"	d
+RG_TURISMO_TRX_SX5GB_CAL_INIT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18881;"	d
+RG_TURISMO_TRX_SX5GB_CAL_INIT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18883;"	d
+RG_TURISMO_TRX_SX5GB_CAL_INIT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18885;"	d
+RG_TURISMO_TRX_SX5GB_CHANNEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18734;"	d
+RG_TURISMO_TRX_SX5GB_CHANNEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18732;"	d
+RG_TURISMO_TRX_SX5GB_CHANNEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18731;"	d
+RG_TURISMO_TRX_SX5GB_CHANNEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18733;"	d
+RG_TURISMO_TRX_SX5GB_CHANNEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18735;"	d
+RG_TURISMO_TRX_SX5GB_CP_IOST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19014;"	d
+RG_TURISMO_TRX_SX5GB_CP_IOST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19012;"	d
+RG_TURISMO_TRX_SX5GB_CP_IOST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19011;"	d
+RG_TURISMO_TRX_SX5GB_CP_IOST_POL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19009;"	d
+RG_TURISMO_TRX_SX5GB_CP_IOST_POL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19007;"	d
+RG_TURISMO_TRX_SX5GB_CP_IOST_POL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19006;"	d
+RG_TURISMO_TRX_SX5GB_CP_IOST_POL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19008;"	d
+RG_TURISMO_TRX_SX5GB_CP_IOST_POL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19010;"	d
+RG_TURISMO_TRX_SX5GB_CP_IOST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19013;"	d
+RG_TURISMO_TRX_SX5GB_CP_IOST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19015;"	d
+RG_TURISMO_TRX_SX5GB_CP_ISEL50U_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18999;"	d
+RG_TURISMO_TRX_SX5GB_CP_ISEL50U_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18997;"	d
+RG_TURISMO_TRX_SX5GB_CP_ISEL50U_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18996;"	d
+RG_TURISMO_TRX_SX5GB_CP_ISEL50U_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18998;"	d
+RG_TURISMO_TRX_SX5GB_CP_ISEL50U_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19000;"	d
+RG_TURISMO_TRX_SX5GB_CP_ISEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18994;"	d
+RG_TURISMO_TRX_SX5GB_CP_ISEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18992;"	d
+RG_TURISMO_TRX_SX5GB_CP_ISEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18991;"	d
+RG_TURISMO_TRX_SX5GB_CP_ISEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18993;"	d
+RG_TURISMO_TRX_SX5GB_CP_ISEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18995;"	d
+RG_TURISMO_TRX_SX5GB_CP_KP_DOUB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19004;"	d
+RG_TURISMO_TRX_SX5GB_CP_KP_DOUB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19002;"	d
+RG_TURISMO_TRX_SX5GB_CP_KP_DOUB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19001;"	d
+RG_TURISMO_TRX_SX5GB_CP_KP_DOUB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19003;"	d
+RG_TURISMO_TRX_SX5GB_CP_KP_DOUB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19005;"	d
+RG_TURISMO_TRX_SX5GB_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19844;"	d
+RG_TURISMO_TRX_SX5GB_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19842;"	d
+RG_TURISMO_TRX_SX5GB_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19841;"	d
+RG_TURISMO_TRX_SX5GB_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19843;"	d
+RG_TURISMO_TRX_SX5GB_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19845;"	d
+RG_TURISMO_TRX_SX5GB_DITHER_WEIGHT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19259;"	d
+RG_TURISMO_TRX_SX5GB_DITHER_WEIGHT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19257;"	d
+RG_TURISMO_TRX_SX5GB_DITHER_WEIGHT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19256;"	d
+RG_TURISMO_TRX_SX5GB_DITHER_WEIGHT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19258;"	d
+RG_TURISMO_TRX_SX5GB_DITHER_WEIGHT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19260;"	d
+RG_TURISMO_TRX_SX5GB_DIV_DMYBUF_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19239;"	d
+RG_TURISMO_TRX_SX5GB_DIV_DMYBUF_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19237;"	d
+RG_TURISMO_TRX_SX5GB_DIV_DMYBUF_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19236;"	d
+RG_TURISMO_TRX_SX5GB_DIV_DMYBUF_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19238;"	d
+RG_TURISMO_TRX_SX5GB_DIV_DMYBUF_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19240;"	d
+RG_TURISMO_TRX_SX5GB_DIV_PREVDD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19219;"	d
+RG_TURISMO_TRX_SX5GB_DIV_PREVDD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19217;"	d
+RG_TURISMO_TRX_SX5GB_DIV_PREVDD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19216;"	d
+RG_TURISMO_TRX_SX5GB_DIV_PREVDD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19218;"	d
+RG_TURISMO_TRX_SX5GB_DIV_PREVDD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19220;"	d
+RG_TURISMO_TRX_SX5GB_DIV_PSCVDD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19224;"	d
+RG_TURISMO_TRX_SX5GB_DIV_PSCVDD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19222;"	d
+RG_TURISMO_TRX_SX5GB_DIV_PSCVDD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19221;"	d
+RG_TURISMO_TRX_SX5GB_DIV_PSCVDD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19223;"	d
+RG_TURISMO_TRX_SX5GB_DIV_PSCVDD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19225;"	d
+RG_TURISMO_TRX_SX5GB_DIV_RST_H_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19229;"	d
+RG_TURISMO_TRX_SX5GB_DIV_RST_H_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19227;"	d
+RG_TURISMO_TRX_SX5GB_DIV_RST_H_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19226;"	d
+RG_TURISMO_TRX_SX5GB_DIV_RST_H_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19228;"	d
+RG_TURISMO_TRX_SX5GB_DIV_RST_H_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19230;"	d
+RG_TURISMO_TRX_SX5GB_DIV_SDM_EDGE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19234;"	d
+RG_TURISMO_TRX_SX5GB_DIV_SDM_EDGE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19232;"	d
+RG_TURISMO_TRX_SX5GB_DIV_SDM_EDGE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19231;"	d
+RG_TURISMO_TRX_SX5GB_DIV_SDM_EDGE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19233;"	d
+RG_TURISMO_TRX_SX5GB_DIV_SDM_EDGE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19235;"	d
+RG_TURISMO_TRX_SX5GB_LDO_CP_LEVEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18174;"	d
+RG_TURISMO_TRX_SX5GB_LDO_CP_LEVEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18172;"	d
+RG_TURISMO_TRX_SX5GB_LDO_CP_LEVEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18171;"	d
+RG_TURISMO_TRX_SX5GB_LDO_CP_LEVEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18173;"	d
+RG_TURISMO_TRX_SX5GB_LDO_CP_LEVEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18175;"	d
+RG_TURISMO_TRX_SX5GB_LDO_DIV_LEVEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18199;"	d
+RG_TURISMO_TRX_SX5GB_LDO_DIV_LEVEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18197;"	d
+RG_TURISMO_TRX_SX5GB_LDO_DIV_LEVEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18196;"	d
+RG_TURISMO_TRX_SX5GB_LDO_DIV_LEVEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18198;"	d
+RG_TURISMO_TRX_SX5GB_LDO_DIV_LEVEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18200;"	d
+RG_TURISMO_TRX_SX5GB_LDO_FCOFFT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18944;"	d
+RG_TURISMO_TRX_SX5GB_LDO_FCOFFT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18942;"	d
+RG_TURISMO_TRX_SX5GB_LDO_FCOFFT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18941;"	d
+RG_TURISMO_TRX_SX5GB_LDO_FCOFFT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18943;"	d
+RG_TURISMO_TRX_SX5GB_LDO_FCOFFT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18945;"	d
+RG_TURISMO_TRX_SX5GB_LDO_LO_LEVEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18184;"	d
+RG_TURISMO_TRX_SX5GB_LDO_LO_LEVEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18182;"	d
+RG_TURISMO_TRX_SX5GB_LDO_LO_LEVEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18181;"	d
+RG_TURISMO_TRX_SX5GB_LDO_LO_LEVEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18183;"	d
+RG_TURISMO_TRX_SX5GB_LDO_LO_LEVEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18185;"	d
+RG_TURISMO_TRX_SX5GB_LDO_VCO_LEVEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18194;"	d
+RG_TURISMO_TRX_SX5GB_LDO_VCO_LEVEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18192;"	d
+RG_TURISMO_TRX_SX5GB_LDO_VCO_LEVEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18191;"	d
+RG_TURISMO_TRX_SX5GB_LDO_VCO_LEVEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18193;"	d
+RG_TURISMO_TRX_SX5GB_LDO_VCO_LEVEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18195;"	d
+RG_TURISMO_TRX_SX5GB_LO_TIMES_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18729;"	d
+RG_TURISMO_TRX_SX5GB_LO_TIMES_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18727;"	d
+RG_TURISMO_TRX_SX5GB_LO_TIMES_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18726;"	d
+RG_TURISMO_TRX_SX5GB_LO_TIMES_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18728;"	d
+RG_TURISMO_TRX_SX5GB_LO_TIMES_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18730;"	d
+RG_TURISMO_TRX_SX5GB_LPF_C1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19064;"	d
+RG_TURISMO_TRX_SX5GB_LPF_C1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19062;"	d
+RG_TURISMO_TRX_SX5GB_LPF_C1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19061;"	d
+RG_TURISMO_TRX_SX5GB_LPF_C1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19063;"	d
+RG_TURISMO_TRX_SX5GB_LPF_C1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19065;"	d
+RG_TURISMO_TRX_SX5GB_LPF_C2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19069;"	d
+RG_TURISMO_TRX_SX5GB_LPF_C2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19067;"	d
+RG_TURISMO_TRX_SX5GB_LPF_C2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19066;"	d
+RG_TURISMO_TRX_SX5GB_LPF_C2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19068;"	d
+RG_TURISMO_TRX_SX5GB_LPF_C2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19070;"	d
+RG_TURISMO_TRX_SX5GB_LPF_C3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19074;"	d
+RG_TURISMO_TRX_SX5GB_LPF_C3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19072;"	d
+RG_TURISMO_TRX_SX5GB_LPF_C3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19071;"	d
+RG_TURISMO_TRX_SX5GB_LPF_C3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19073;"	d
+RG_TURISMO_TRX_SX5GB_LPF_C3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19075;"	d
+RG_TURISMO_TRX_SX5GB_LPF_R2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19079;"	d
+RG_TURISMO_TRX_SX5GB_LPF_R2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19077;"	d
+RG_TURISMO_TRX_SX5GB_LPF_R2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19076;"	d
+RG_TURISMO_TRX_SX5GB_LPF_R2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19078;"	d
+RG_TURISMO_TRX_SX5GB_LPF_R2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19080;"	d
+RG_TURISMO_TRX_SX5GB_LPF_R3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19084;"	d
+RG_TURISMO_TRX_SX5GB_LPF_R3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19082;"	d
+RG_TURISMO_TRX_SX5GB_LPF_R3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19081;"	d
+RG_TURISMO_TRX_SX5GB_LPF_R3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19083;"	d
+RG_TURISMO_TRX_SX5GB_LPF_R3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19085;"	d
+RG_TURISMO_TRX_SX5GB_LPF_VTUNE_TEST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19129;"	d
+RG_TURISMO_TRX_SX5GB_LPF_VTUNE_TEST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19127;"	d
+RG_TURISMO_TRX_SX5GB_LPF_VTUNE_TEST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19126;"	d
+RG_TURISMO_TRX_SX5GB_LPF_VTUNE_TEST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19128;"	d
+RG_TURISMO_TRX_SX5GB_LPF_VTUNE_TEST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19130;"	d
+RG_TURISMO_TRX_SX5GB_MIXAAC_DIS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18869;"	d
+RG_TURISMO_TRX_SX5GB_MIXAAC_DIS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18867;"	d
+RG_TURISMO_TRX_SX5GB_MIXAAC_DIS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18866;"	d
+RG_TURISMO_TRX_SX5GB_MIXAAC_DIS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18868;"	d
+RG_TURISMO_TRX_SX5GB_MIXAAC_DIS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18870;"	d
+RG_TURISMO_TRX_SX5GB_MIXAAC_TAR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19394;"	d
+RG_TURISMO_TRX_SX5GB_MIXAAC_TAR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19392;"	d
+RG_TURISMO_TRX_SX5GB_MIXAAC_TAR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19391;"	d
+RG_TURISMO_TRX_SX5GB_MIXAAC_TAR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19393;"	d
+RG_TURISMO_TRX_SX5GB_MIXAAC_TAR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19395;"	d
+RG_TURISMO_TRX_SX5GB_MOD_ORDER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19254;"	d
+RG_TURISMO_TRX_SX5GB_MOD_ORDER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19252;"	d
+RG_TURISMO_TRX_SX5GB_MOD_ORDER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19251;"	d
+RG_TURISMO_TRX_SX5GB_MOD_ORDER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19253;"	d
+RG_TURISMO_TRX_SX5GB_MOD_ORDER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19255;"	d
+RG_TURISMO_TRX_SX5GB_PFD_DIV_EDGE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19059;"	d
+RG_TURISMO_TRX_SX5GB_PFD_DIV_EDGE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19057;"	d
+RG_TURISMO_TRX_SX5GB_PFD_DIV_EDGE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19056;"	d
+RG_TURISMO_TRX_SX5GB_PFD_DIV_EDGE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19058;"	d
+RG_TURISMO_TRX_SX5GB_PFD_DIV_EDGE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19060;"	d
+RG_TURISMO_TRX_SX5GB_PFD_REF_EDGE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19054;"	d
+RG_TURISMO_TRX_SX5GB_PFD_REF_EDGE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19052;"	d
+RG_TURISMO_TRX_SX5GB_PFD_REF_EDGE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19051;"	d
+RG_TURISMO_TRX_SX5GB_PFD_REF_EDGE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19053;"	d
+RG_TURISMO_TRX_SX5GB_PFD_REF_EDGE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19055;"	d
+RG_TURISMO_TRX_SX5GB_PFD_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18784;"	d
+RG_TURISMO_TRX_SX5GB_PFD_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18782;"	d
+RG_TURISMO_TRX_SX5GB_PFD_RST_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18779;"	d
+RG_TURISMO_TRX_SX5GB_PFD_RST_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18777;"	d
+RG_TURISMO_TRX_SX5GB_PFD_RST_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18776;"	d
+RG_TURISMO_TRX_SX5GB_PFD_RST_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18778;"	d
+RG_TURISMO_TRX_SX5GB_PFD_RST_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18780;"	d
+RG_TURISMO_TRX_SX5GB_PFD_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18781;"	d
+RG_TURISMO_TRX_SX5GB_PFD_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18783;"	d
+RG_TURISMO_TRX_SX5GB_PFD_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18785;"	d
+RG_TURISMO_TRX_SX5GB_PFD_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19019;"	d
+RG_TURISMO_TRX_SX5GB_PFD_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19017;"	d
+RG_TURISMO_TRX_SX5GB_PFD_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19016;"	d
+RG_TURISMO_TRX_SX5GB_PFD_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19018;"	d
+RG_TURISMO_TRX_SX5GB_PFD_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19020;"	d
+RG_TURISMO_TRX_SX5GB_PFD_SET1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19029;"	d
+RG_TURISMO_TRX_SX5GB_PFD_SET1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19027;"	d
+RG_TURISMO_TRX_SX5GB_PFD_SET1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19026;"	d
+RG_TURISMO_TRX_SX5GB_PFD_SET1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19028;"	d
+RG_TURISMO_TRX_SX5GB_PFD_SET1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19030;"	d
+RG_TURISMO_TRX_SX5GB_PFD_SET2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19034;"	d
+RG_TURISMO_TRX_SX5GB_PFD_SET2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19032;"	d
+RG_TURISMO_TRX_SX5GB_PFD_SET2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19031;"	d
+RG_TURISMO_TRX_SX5GB_PFD_SET2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19033;"	d
+RG_TURISMO_TRX_SX5GB_PFD_SET2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19035;"	d
+RG_TURISMO_TRX_SX5GB_PFD_SET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19024;"	d
+RG_TURISMO_TRX_SX5GB_PFD_SET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19022;"	d
+RG_TURISMO_TRX_SX5GB_PFD_SET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19021;"	d
+RG_TURISMO_TRX_SX5GB_PFD_SET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19023;"	d
+RG_TURISMO_TRX_SX5GB_PFD_SET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19025;"	d
+RG_TURISMO_TRX_SX5GB_PFD_TLSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19049;"	d
+RG_TURISMO_TRX_SX5GB_PFD_TLSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19047;"	d
+RG_TURISMO_TRX_SX5GB_PFD_TLSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19046;"	d
+RG_TURISMO_TRX_SX5GB_PFD_TLSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19048;"	d
+RG_TURISMO_TRX_SX5GB_PFD_TLSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19050;"	d
+RG_TURISMO_TRX_SX5GB_PFD_TRDN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19044;"	d
+RG_TURISMO_TRX_SX5GB_PFD_TRDN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19042;"	d
+RG_TURISMO_TRX_SX5GB_PFD_TRDN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19041;"	d
+RG_TURISMO_TRX_SX5GB_PFD_TRDN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19043;"	d
+RG_TURISMO_TRX_SX5GB_PFD_TRDN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19045;"	d
+RG_TURISMO_TRX_SX5GB_PFD_TRUP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19039;"	d
+RG_TURISMO_TRX_SX5GB_PFD_TRUP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19037;"	d
+RG_TURISMO_TRX_SX5GB_PFD_TRUP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19036;"	d
+RG_TURISMO_TRX_SX5GB_PFD_TRUP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19038;"	d
+RG_TURISMO_TRX_SX5GB_PFD_TRUP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19040;"	d
+RG_TURISMO_TRX_SX5GB_REPAAC_DIS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18874;"	d
+RG_TURISMO_TRX_SX5GB_REPAAC_DIS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18872;"	d
+RG_TURISMO_TRX_SX5GB_REPAAC_DIS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18871;"	d
+RG_TURISMO_TRX_SX5GB_REPAAC_DIS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18873;"	d
+RG_TURISMO_TRX_SX5GB_REPAAC_DIS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18875;"	d
+RG_TURISMO_TRX_SX5GB_REPAAC_TAR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19409;"	d
+RG_TURISMO_TRX_SX5GB_REPAAC_TAR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19407;"	d
+RG_TURISMO_TRX_SX5GB_REPAAC_TAR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19406;"	d
+RG_TURISMO_TRX_SX5GB_REPAAC_TAR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19408;"	d
+RG_TURISMO_TRX_SX5GB_REPAAC_TAR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19410;"	d
+RG_TURISMO_TRX_SX5GB_RFCH_MAP_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18724;"	d
+RG_TURISMO_TRX_SX5GB_RFCH_MAP_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18722;"	d
+RG_TURISMO_TRX_SX5GB_RFCH_MAP_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18721;"	d
+RG_TURISMO_TRX_SX5GB_RFCH_MAP_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18723;"	d
+RG_TURISMO_TRX_SX5GB_RFCH_MAP_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18725;"	d
+RG_TURISMO_TRX_SX5GB_RFCTRL_CH_10_8_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18719;"	d
+RG_TURISMO_TRX_SX5GB_RFCTRL_CH_10_8_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18717;"	d
+RG_TURISMO_TRX_SX5GB_RFCTRL_CH_10_8_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18716;"	d
+RG_TURISMO_TRX_SX5GB_RFCTRL_CH_10_8_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18718;"	d
+RG_TURISMO_TRX_SX5GB_RFCTRL_CH_10_8_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18720;"	d
+RG_TURISMO_TRX_SX5GB_RFCTRL_CH_7_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18714;"	d
+RG_TURISMO_TRX_SX5GB_RFCTRL_CH_7_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18712;"	d
+RG_TURISMO_TRX_SX5GB_RFCTRL_CH_7_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18711;"	d
+RG_TURISMO_TRX_SX5GB_RFCTRL_CH_7_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18713;"	d
+RG_TURISMO_TRX_SX5GB_RFCTRL_CH_7_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18715;"	d
+RG_TURISMO_TRX_SX5GB_RFCTRL_F_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18709;"	d
+RG_TURISMO_TRX_SX5GB_RFCTRL_F_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18707;"	d
+RG_TURISMO_TRX_SX5GB_RFCTRL_F_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18706;"	d
+RG_TURISMO_TRX_SX5GB_RFCTRL_F_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18708;"	d
+RG_TURISMO_TRX_SX5GB_RFCTRL_F_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18710;"	d
+RG_TURISMO_TRX_SX5GB_SBCAL_2ND_DIS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18854;"	d
+RG_TURISMO_TRX_SX5GB_SBCAL_2ND_DIS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18852;"	d
+RG_TURISMO_TRX_SX5GB_SBCAL_2ND_DIS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18851;"	d
+RG_TURISMO_TRX_SX5GB_SBCAL_2ND_DIS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18853;"	d
+RG_TURISMO_TRX_SX5GB_SBCAL_2ND_DIS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18855;"	d
+RG_TURISMO_TRX_SX5GB_SBCAL_AW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18859;"	d
+RG_TURISMO_TRX_SX5GB_SBCAL_AW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18857;"	d
+RG_TURISMO_TRX_SX5GB_SBCAL_AW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18856;"	d
+RG_TURISMO_TRX_SX5GB_SBCAL_AW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18858;"	d
+RG_TURISMO_TRX_SX5GB_SBCAL_AW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18860;"	d
+RG_TURISMO_TRX_SX5GB_SBCAL_CT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19279;"	d
+RG_TURISMO_TRX_SX5GB_SBCAL_CT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19277;"	d
+RG_TURISMO_TRX_SX5GB_SBCAL_CT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19276;"	d
+RG_TURISMO_TRX_SX5GB_SBCAL_CT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19278;"	d
+RG_TURISMO_TRX_SX5GB_SBCAL_CT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19280;"	d
+RG_TURISMO_TRX_SX5GB_SBCAL_DIFFMIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19289;"	d
+RG_TURISMO_TRX_SX5GB_SBCAL_DIFFMIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19287;"	d
+RG_TURISMO_TRX_SX5GB_SBCAL_DIFFMIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19286;"	d
+RG_TURISMO_TRX_SX5GB_SBCAL_DIFFMIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19288;"	d
+RG_TURISMO_TRX_SX5GB_SBCAL_DIFFMIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19290;"	d
+RG_TURISMO_TRX_SX5GB_SBCAL_DIS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18849;"	d
+RG_TURISMO_TRX_SX5GB_SBCAL_DIS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18847;"	d
+RG_TURISMO_TRX_SX5GB_SBCAL_DIS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18846;"	d
+RG_TURISMO_TRX_SX5GB_SBCAL_DIS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18848;"	d
+RG_TURISMO_TRX_SX5GB_SBCAL_DIS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18850;"	d
+RG_TURISMO_TRX_SX5GB_SBCAL_NTARG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19299;"	d
+RG_TURISMO_TRX_SX5GB_SBCAL_NTARG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19297;"	d
+RG_TURISMO_TRX_SX5GB_SBCAL_NTARG_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19294;"	d
+RG_TURISMO_TRX_SX5GB_SBCAL_NTARG_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19292;"	d
+RG_TURISMO_TRX_SX5GB_SBCAL_NTARG_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19291;"	d
+RG_TURISMO_TRX_SX5GB_SBCAL_NTARG_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19293;"	d
+RG_TURISMO_TRX_SX5GB_SBCAL_NTARG_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19295;"	d
+RG_TURISMO_TRX_SX5GB_SBCAL_NTARG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19296;"	d
+RG_TURISMO_TRX_SX5GB_SBCAL_NTARG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19298;"	d
+RG_TURISMO_TRX_SX5GB_SBCAL_NTARG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19300;"	d
+RG_TURISMO_TRX_SX5GB_SBCAL_WT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19284;"	d
+RG_TURISMO_TRX_SX5GB_SBCAL_WT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19282;"	d
+RG_TURISMO_TRX_SX5GB_SBCAL_WT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19281;"	d
+RG_TURISMO_TRX_SX5GB_SBCAL_WT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19283;"	d
+RG_TURISMO_TRX_SX5GB_SBCAL_WT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19285;"	d
+RG_TURISMO_TRX_SX5GB_SUB_C0P5_DIS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19274;"	d
+RG_TURISMO_TRX_SX5GB_SUB_C0P5_DIS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19272;"	d
+RG_TURISMO_TRX_SX5GB_SUB_C0P5_DIS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19271;"	d
+RG_TURISMO_TRX_SX5GB_SUB_C0P5_DIS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19273;"	d
+RG_TURISMO_TRX_SX5GB_SUB_C0P5_DIS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19275;"	d
+RG_TURISMO_TRX_SX5GB_SUB_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19269;"	d
+RG_TURISMO_TRX_SX5GB_SUB_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19267;"	d
+RG_TURISMO_TRX_SX5GB_SUB_SEL_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19264;"	d
+RG_TURISMO_TRX_SX5GB_SUB_SEL_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19262;"	d
+RG_TURISMO_TRX_SX5GB_SUB_SEL_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19261;"	d
+RG_TURISMO_TRX_SX5GB_SUB_SEL_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19263;"	d
+RG_TURISMO_TRX_SX5GB_SUB_SEL_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19265;"	d
+RG_TURISMO_TRX_SX5GB_SUB_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19266;"	d
+RG_TURISMO_TRX_SX5GB_SUB_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19268;"	d
+RG_TURISMO_TRX_SX5GB_SUB_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19270;"	d
+RG_TURISMO_TRX_SX5GB_TTL_ACCUM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19104;"	d
+RG_TURISMO_TRX_SX5GB_TTL_ACCUM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19102;"	d
+RG_TURISMO_TRX_SX5GB_TTL_ACCUM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19101;"	d
+RG_TURISMO_TRX_SX5GB_TTL_ACCUM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19103;"	d
+RG_TURISMO_TRX_SX5GB_TTL_ACCUM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19105;"	d
+RG_TURISMO_TRX_SX5GB_TTL_CPT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19099;"	d
+RG_TURISMO_TRX_SX5GB_TTL_CPT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19097;"	d
+RG_TURISMO_TRX_SX5GB_TTL_CPT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19096;"	d
+RG_TURISMO_TRX_SX5GB_TTL_CPT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19098;"	d
+RG_TURISMO_TRX_SX5GB_TTL_CPT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19100;"	d
+RG_TURISMO_TRX_SX5GB_TTL_DIS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18879;"	d
+RG_TURISMO_TRX_SX5GB_TTL_DIS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18877;"	d
+RG_TURISMO_TRX_SX5GB_TTL_DIS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18876;"	d
+RG_TURISMO_TRX_SX5GB_TTL_DIS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18878;"	d
+RG_TURISMO_TRX_SX5GB_TTL_DIS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18880;"	d
+RG_TURISMO_TRX_SX5GB_TTL_FPT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19094;"	d
+RG_TURISMO_TRX_SX5GB_TTL_FPT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19092;"	d
+RG_TURISMO_TRX_SX5GB_TTL_FPT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19091;"	d
+RG_TURISMO_TRX_SX5GB_TTL_FPT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19093;"	d
+RG_TURISMO_TRX_SX5GB_TTL_FPT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19095;"	d
+RG_TURISMO_TRX_SX5GB_TTL_INIT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19089;"	d
+RG_TURISMO_TRX_SX5GB_TTL_INIT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19087;"	d
+RG_TURISMO_TRX_SX5GB_TTL_INIT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19086;"	d
+RG_TURISMO_TRX_SX5GB_TTL_INIT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19088;"	d
+RG_TURISMO_TRX_SX5GB_TTL_INIT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19090;"	d
+RG_TURISMO_TRX_SX5GB_TTL_SUB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19109;"	d
+RG_TURISMO_TRX_SX5GB_TTL_SUB_INV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19114;"	d
+RG_TURISMO_TRX_SX5GB_TTL_SUB_INV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19112;"	d
+RG_TURISMO_TRX_SX5GB_TTL_SUB_INV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19111;"	d
+RG_TURISMO_TRX_SX5GB_TTL_SUB_INV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19113;"	d
+RG_TURISMO_TRX_SX5GB_TTL_SUB_INV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19115;"	d
+RG_TURISMO_TRX_SX5GB_TTL_SUB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19107;"	d
+RG_TURISMO_TRX_SX5GB_TTL_SUB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19106;"	d
+RG_TURISMO_TRX_SX5GB_TTL_SUB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19108;"	d
+RG_TURISMO_TRX_SX5GB_TTL_SUB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19110;"	d
+RG_TURISMO_TRX_SX5GB_TTL_VH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19119;"	d
+RG_TURISMO_TRX_SX5GB_TTL_VH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19117;"	d
+RG_TURISMO_TRX_SX5GB_TTL_VH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19116;"	d
+RG_TURISMO_TRX_SX5GB_TTL_VH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19118;"	d
+RG_TURISMO_TRX_SX5GB_TTL_VH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19120;"	d
+RG_TURISMO_TRX_SX5GB_TTL_VL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19124;"	d
+RG_TURISMO_TRX_SX5GB_TTL_VL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19122;"	d
+RG_TURISMO_TRX_SX5GB_TTL_VL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19121;"	d
+RG_TURISMO_TRX_SX5GB_TTL_VL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19123;"	d
+RG_TURISMO_TRX_SX5GB_TTL_VL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19125;"	d
+RG_TURISMO_TRX_SX5GB_UOP_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18794;"	d
+RG_TURISMO_TRX_SX5GB_UOP_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18792;"	d
+RG_TURISMO_TRX_SX5GB_UOP_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18791;"	d
+RG_TURISMO_TRX_SX5GB_UOP_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18793;"	d
+RG_TURISMO_TRX_SX5GB_UOP_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18795;"	d
+RG_TURISMO_TRX_SX5GB_UOP_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18789;"	d
+RG_TURISMO_TRX_SX5GB_UOP_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18787;"	d
+RG_TURISMO_TRX_SX5GB_UOP_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18786;"	d
+RG_TURISMO_TRX_SX5GB_UOP_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18788;"	d
+RG_TURISMO_TRX_SX5GB_UOP_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18790;"	d
+RG_TURISMO_TRX_SX5GB_VCO_CS_AWH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19164;"	d
+RG_TURISMO_TRX_SX5GB_VCO_CS_AWH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19162;"	d
+RG_TURISMO_TRX_SX5GB_VCO_CS_AWH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19161;"	d
+RG_TURISMO_TRX_SX5GB_VCO_CS_AWH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19163;"	d
+RG_TURISMO_TRX_SX5GB_VCO_CS_AWH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19165;"	d
+RG_TURISMO_TRX_SX5GB_VCO_ISEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19139;"	d
+RG_TURISMO_TRX_SX5GB_VCO_ISEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19137;"	d
+RG_TURISMO_TRX_SX5GB_VCO_ISEL_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19134;"	d
+RG_TURISMO_TRX_SX5GB_VCO_ISEL_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19132;"	d
+RG_TURISMO_TRX_SX5GB_VCO_ISEL_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19131;"	d
+RG_TURISMO_TRX_SX5GB_VCO_ISEL_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19133;"	d
+RG_TURISMO_TRX_SX5GB_VCO_ISEL_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19135;"	d
+RG_TURISMO_TRX_SX5GB_VCO_ISEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19136;"	d
+RG_TURISMO_TRX_SX5GB_VCO_ISEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19138;"	d
+RG_TURISMO_TRX_SX5GB_VCO_ISEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19140;"	d
+RG_TURISMO_TRX_SX5GB_VCO_KVDOUB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19149;"	d
+RG_TURISMO_TRX_SX5GB_VCO_KVDOUB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19147;"	d
+RG_TURISMO_TRX_SX5GB_VCO_KVDOUB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19146;"	d
+RG_TURISMO_TRX_SX5GB_VCO_KVDOUB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19148;"	d
+RG_TURISMO_TRX_SX5GB_VCO_KVDOUB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19150;"	d
+RG_TURISMO_TRX_SX5GB_VCO_RTAIL_SHIFT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19159;"	d
+RG_TURISMO_TRX_SX5GB_VCO_RTAIL_SHIFT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19157;"	d
+RG_TURISMO_TRX_SX5GB_VCO_RTAIL_SHIFT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19156;"	d
+RG_TURISMO_TRX_SX5GB_VCO_RTAIL_SHIFT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19158;"	d
+RG_TURISMO_TRX_SX5GB_VCO_RTAIL_SHIFT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19160;"	d
+RG_TURISMO_TRX_SX5GB_VCO_VARBSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19154;"	d
+RG_TURISMO_TRX_SX5GB_VCO_VARBSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19152;"	d
+RG_TURISMO_TRX_SX5GB_VCO_VARBSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19151;"	d
+RG_TURISMO_TRX_SX5GB_VCO_VARBSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19153;"	d
+RG_TURISMO_TRX_SX5GB_VCO_VARBSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19155;"	d
+RG_TURISMO_TRX_SX5GB_VCO_VCCBSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19144;"	d
+RG_TURISMO_TRX_SX5GB_VCO_VCCBSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19142;"	d
+RG_TURISMO_TRX_SX5GB_VCO_VCCBSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19141;"	d
+RG_TURISMO_TRX_SX5GB_VCO_VCCBSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19143;"	d
+RG_TURISMO_TRX_SX5GB_VCO_VCCBSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19145;"	d
+RG_TURISMO_TRX_SX5GB_VOAAC_DIS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18864;"	d
+RG_TURISMO_TRX_SX5GB_VOAAC_DIS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18862;"	d
+RG_TURISMO_TRX_SX5GB_VOAAC_DIS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18861;"	d
+RG_TURISMO_TRX_SX5GB_VOAAC_DIS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18863;"	d
+RG_TURISMO_TRX_SX5GB_VOAAC_DIS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18865;"	d
+RG_TURISMO_TRX_SX5GB_VOAAC_TAR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19304;"	d
+RG_TURISMO_TRX_SX5GB_VOAAC_TAR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19302;"	d
+RG_TURISMO_TRX_SX5GB_VOAAC_TAR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19301;"	d
+RG_TURISMO_TRX_SX5GB_VOAAC_TAR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19303;"	d
+RG_TURISMO_TRX_SX5GB_VOAAC_TAR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19305;"	d
+RG_TURISMO_TRX_SXMIX_GMSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19199;"	d
+RG_TURISMO_TRX_SXMIX_GMSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19197;"	d
+RG_TURISMO_TRX_SXMIX_GMSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19196;"	d
+RG_TURISMO_TRX_SXMIX_GMSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19198;"	d
+RG_TURISMO_TRX_SXMIX_GMSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19200;"	d
+RG_TURISMO_TRX_SXMIX_IBIAS_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19189;"	d
+RG_TURISMO_TRX_SXMIX_IBIAS_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19187;"	d
+RG_TURISMO_TRX_SXMIX_IBIAS_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19186;"	d
+RG_TURISMO_TRX_SXMIX_IBIAS_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19188;"	d
+RG_TURISMO_TRX_SXMIX_IBIAS_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19190;"	d
+RG_TURISMO_TRX_SXMIX_SCA_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19404;"	d
+RG_TURISMO_TRX_SXMIX_SCA_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19402;"	d
+RG_TURISMO_TRX_SXMIX_SCA_SEL_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19399;"	d
+RG_TURISMO_TRX_SXMIX_SCA_SEL_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19397;"	d
+RG_TURISMO_TRX_SXMIX_SCA_SEL_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19396;"	d
+RG_TURISMO_TRX_SXMIX_SCA_SEL_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19398;"	d
+RG_TURISMO_TRX_SXMIX_SCA_SEL_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19400;"	d
+RG_TURISMO_TRX_SXMIX_SCA_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19401;"	d
+RG_TURISMO_TRX_SXMIX_SCA_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19403;"	d
+RG_TURISMO_TRX_SXMIX_SCA_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19405;"	d
+RG_TURISMO_TRX_SXMIX_SWB_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19194;"	d
+RG_TURISMO_TRX_SXMIX_SWB_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19192;"	d
+RG_TURISMO_TRX_SXMIX_SWB_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19191;"	d
+RG_TURISMO_TRX_SXMIX_SWB_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19193;"	d
+RG_TURISMO_TRX_SXMIX_SWB_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19195;"	d
+RG_TURISMO_TRX_SXREP_CSSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19209;"	d
+RG_TURISMO_TRX_SXREP_CSSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19207;"	d
+RG_TURISMO_TRX_SXREP_CSSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19206;"	d
+RG_TURISMO_TRX_SXREP_CSSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19208;"	d
+RG_TURISMO_TRX_SXREP_CSSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19210;"	d
+RG_TURISMO_TRX_SXREP_SCA_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19419;"	d
+RG_TURISMO_TRX_SXREP_SCA_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19417;"	d
+RG_TURISMO_TRX_SXREP_SCA_SEL_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19414;"	d
+RG_TURISMO_TRX_SXREP_SCA_SEL_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19412;"	d
+RG_TURISMO_TRX_SXREP_SCA_SEL_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19411;"	d
+RG_TURISMO_TRX_SXREP_SCA_SEL_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19413;"	d
+RG_TURISMO_TRX_SXREP_SCA_SEL_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19415;"	d
+RG_TURISMO_TRX_SXREP_SCA_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19416;"	d
+RG_TURISMO_TRX_SXREP_SCA_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19418;"	d
+RG_TURISMO_TRX_SXREP_SCA_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19420;"	d
+RG_TURISMO_TRX_SXREP_SWB_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19204;"	d
+RG_TURISMO_TRX_SXREP_SWB_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19202;"	d
+RG_TURISMO_TRX_SXREP_SWB_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19201;"	d
+RG_TURISMO_TRX_SXREP_SWB_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19203;"	d
+RG_TURISMO_TRX_SXREP_SWB_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19205;"	d
+RG_TURISMO_TRX_SX_5GB_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18744;"	d
+RG_TURISMO_TRX_SX_5GB_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18742;"	d
+RG_TURISMO_TRX_SX_5GB_EN_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	18739;"	d
+RG_TURISMO_TRX_SX_5GB_EN_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18737;"	d
+RG_TURISMO_TRX_SX_5GB_EN_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18736;"	d
+RG_TURISMO_TRX_SX_5GB_EN_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18738;"	d
+RG_TURISMO_TRX_SX_5GB_EN_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18740;"	d
+RG_TURISMO_TRX_SX_5GB_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	18741;"	d
+RG_TURISMO_TRX_SX_5GB_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	18743;"	d
+RG_TURISMO_TRX_SX_5GB_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	18745;"	d
+RG_TURISMO_TRX_SX_AAC_DIS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16249;"	d
+RG_TURISMO_TRX_SX_AAC_DIS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16247;"	d
+RG_TURISMO_TRX_SX_AAC_DIS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16246;"	d
+RG_TURISMO_TRX_SX_AAC_DIS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16248;"	d
+RG_TURISMO_TRX_SX_AAC_DIS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16250;"	d
+RG_TURISMO_TRX_SX_BTRX_SIDE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16399;"	d
+RG_TURISMO_TRX_SX_BTRX_SIDE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16397;"	d
+RG_TURISMO_TRX_SX_BTRX_SIDE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16396;"	d
+RG_TURISMO_TRX_SX_BTRX_SIDE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16398;"	d
+RG_TURISMO_TRX_SX_BTRX_SIDE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16400;"	d
+RG_TURISMO_TRX_SX_CAL_INIT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16259;"	d
+RG_TURISMO_TRX_SX_CAL_INIT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16257;"	d
+RG_TURISMO_TRX_SX_CAL_INIT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16256;"	d
+RG_TURISMO_TRX_SX_CAL_INIT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16258;"	d
+RG_TURISMO_TRX_SX_CAL_INIT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16260;"	d
+RG_TURISMO_TRX_SX_CHANNEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16409;"	d
+RG_TURISMO_TRX_SX_CHANNEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16407;"	d
+RG_TURISMO_TRX_SX_CHANNEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16406;"	d
+RG_TURISMO_TRX_SX_CHANNEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16408;"	d
+RG_TURISMO_TRX_SX_CHANNEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16410;"	d
+RG_TURISMO_TRX_SX_CP_IOST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16449;"	d
+RG_TURISMO_TRX_SX_CP_IOST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16447;"	d
+RG_TURISMO_TRX_SX_CP_IOST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16446;"	d
+RG_TURISMO_TRX_SX_CP_IOST_POL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16444;"	d
+RG_TURISMO_TRX_SX_CP_IOST_POL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16442;"	d
+RG_TURISMO_TRX_SX_CP_IOST_POL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16441;"	d
+RG_TURISMO_TRX_SX_CP_IOST_POL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16443;"	d
+RG_TURISMO_TRX_SX_CP_IOST_POL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16445;"	d
+RG_TURISMO_TRX_SX_CP_IOST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16448;"	d
+RG_TURISMO_TRX_SX_CP_IOST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16450;"	d
+RG_TURISMO_TRX_SX_CP_ISEL50U_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16419;"	d
+RG_TURISMO_TRX_SX_CP_ISEL50U_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16417;"	d
+RG_TURISMO_TRX_SX_CP_ISEL50U_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16416;"	d
+RG_TURISMO_TRX_SX_CP_ISEL50U_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16418;"	d
+RG_TURISMO_TRX_SX_CP_ISEL50U_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16420;"	d
+RG_TURISMO_TRX_SX_CP_ISEL50U_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16434;"	d
+RG_TURISMO_TRX_SX_CP_ISEL50U_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16432;"	d
+RG_TURISMO_TRX_SX_CP_ISEL50U_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16431;"	d
+RG_TURISMO_TRX_SX_CP_ISEL50U_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16433;"	d
+RG_TURISMO_TRX_SX_CP_ISEL50U_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16435;"	d
+RG_TURISMO_TRX_SX_CP_ISEL_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16414;"	d
+RG_TURISMO_TRX_SX_CP_ISEL_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16412;"	d
+RG_TURISMO_TRX_SX_CP_ISEL_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16411;"	d
+RG_TURISMO_TRX_SX_CP_ISEL_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16413;"	d
+RG_TURISMO_TRX_SX_CP_ISEL_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16415;"	d
+RG_TURISMO_TRX_SX_CP_ISEL_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16429;"	d
+RG_TURISMO_TRX_SX_CP_ISEL_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16427;"	d
+RG_TURISMO_TRX_SX_CP_ISEL_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16426;"	d
+RG_TURISMO_TRX_SX_CP_ISEL_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16428;"	d
+RG_TURISMO_TRX_SX_CP_ISEL_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16430;"	d
+RG_TURISMO_TRX_SX_CP_KP_DOUB_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16424;"	d
+RG_TURISMO_TRX_SX_CP_KP_DOUB_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16422;"	d
+RG_TURISMO_TRX_SX_CP_KP_DOUB_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16421;"	d
+RG_TURISMO_TRX_SX_CP_KP_DOUB_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16423;"	d
+RG_TURISMO_TRX_SX_CP_KP_DOUB_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16425;"	d
+RG_TURISMO_TRX_SX_CP_KP_DOUB_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16439;"	d
+RG_TURISMO_TRX_SX_CP_KP_DOUB_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16437;"	d
+RG_TURISMO_TRX_SX_CP_KP_DOUB_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16436;"	d
+RG_TURISMO_TRX_SX_CP_KP_DOUB_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16438;"	d
+RG_TURISMO_TRX_SX_CP_KP_DOUB_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16440;"	d
+RG_TURISMO_TRX_SX_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17759;"	d
+RG_TURISMO_TRX_SX_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17757;"	d
+RG_TURISMO_TRX_SX_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17756;"	d
+RG_TURISMO_TRX_SX_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17758;"	d
+RG_TURISMO_TRX_SX_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17760;"	d
+RG_TURISMO_TRX_SX_DITHER_WEIGHT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16719;"	d
+RG_TURISMO_TRX_SX_DITHER_WEIGHT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16717;"	d
+RG_TURISMO_TRX_SX_DITHER_WEIGHT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16716;"	d
+RG_TURISMO_TRX_SX_DITHER_WEIGHT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16718;"	d
+RG_TURISMO_TRX_SX_DITHER_WEIGHT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16720;"	d
+RG_TURISMO_TRX_SX_DIV_DMYBUF_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16699;"	d
+RG_TURISMO_TRX_SX_DIV_DMYBUF_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16697;"	d
+RG_TURISMO_TRX_SX_DIV_DMYBUF_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16696;"	d
+RG_TURISMO_TRX_SX_DIV_DMYBUF_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16698;"	d
+RG_TURISMO_TRX_SX_DIV_DMYBUF_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16700;"	d
+RG_TURISMO_TRX_SX_DIV_PREVDD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16679;"	d
+RG_TURISMO_TRX_SX_DIV_PREVDD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16677;"	d
+RG_TURISMO_TRX_SX_DIV_PREVDD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16676;"	d
+RG_TURISMO_TRX_SX_DIV_PREVDD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16678;"	d
+RG_TURISMO_TRX_SX_DIV_PREVDD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16680;"	d
+RG_TURISMO_TRX_SX_DIV_PSCVDD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16684;"	d
+RG_TURISMO_TRX_SX_DIV_PSCVDD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16682;"	d
+RG_TURISMO_TRX_SX_DIV_PSCVDD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16681;"	d
+RG_TURISMO_TRX_SX_DIV_PSCVDD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16683;"	d
+RG_TURISMO_TRX_SX_DIV_PSCVDD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16685;"	d
+RG_TURISMO_TRX_SX_DIV_RST_H_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16689;"	d
+RG_TURISMO_TRX_SX_DIV_RST_H_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16687;"	d
+RG_TURISMO_TRX_SX_DIV_RST_H_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16686;"	d
+RG_TURISMO_TRX_SX_DIV_RST_H_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16688;"	d
+RG_TURISMO_TRX_SX_DIV_RST_H_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16690;"	d
+RG_TURISMO_TRX_SX_DIV_SDM_EDGE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16694;"	d
+RG_TURISMO_TRX_SX_DIV_SDM_EDGE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16692;"	d
+RG_TURISMO_TRX_SX_DIV_SDM_EDGE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16691;"	d
+RG_TURISMO_TRX_SX_DIV_SDM_EDGE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16693;"	d
+RG_TURISMO_TRX_SX_DIV_SDM_EDGE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16695;"	d
+RG_TURISMO_TRX_SX_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16134;"	d
+RG_TURISMO_TRX_SX_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16132;"	d
+RG_TURISMO_TRX_SX_EN_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16129;"	d
+RG_TURISMO_TRX_SX_EN_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16127;"	d
+RG_TURISMO_TRX_SX_EN_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16126;"	d
+RG_TURISMO_TRX_SX_EN_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16128;"	d
+RG_TURISMO_TRX_SX_EN_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16130;"	d
+RG_TURISMO_TRX_SX_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16131;"	d
+RG_TURISMO_TRX_SX_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16133;"	d
+RG_TURISMO_TRX_SX_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16135;"	d
+RG_TURISMO_TRX_SX_FREF_DOUB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16394;"	d
+RG_TURISMO_TRX_SX_FREF_DOUB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16392;"	d
+RG_TURISMO_TRX_SX_FREF_DOUB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16391;"	d
+RG_TURISMO_TRX_SX_FREF_DOUB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16393;"	d
+RG_TURISMO_TRX_SX_FREF_DOUB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16395;"	d
+RG_TURISMO_TRX_SX_LDO_CP_LEVEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15009;"	d
+RG_TURISMO_TRX_SX_LDO_CP_LEVEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15007;"	d
+RG_TURISMO_TRX_SX_LDO_CP_LEVEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15006;"	d
+RG_TURISMO_TRX_SX_LDO_CP_LEVEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15008;"	d
+RG_TURISMO_TRX_SX_LDO_CP_LEVEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15010;"	d
+RG_TURISMO_TRX_SX_LDO_DIV_LEVEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15034;"	d
+RG_TURISMO_TRX_SX_LDO_DIV_LEVEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15032;"	d
+RG_TURISMO_TRX_SX_LDO_DIV_LEVEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15031;"	d
+RG_TURISMO_TRX_SX_LDO_DIV_LEVEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15033;"	d
+RG_TURISMO_TRX_SX_LDO_DIV_LEVEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15035;"	d
+RG_TURISMO_TRX_SX_LDO_FCOFFT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16319;"	d
+RG_TURISMO_TRX_SX_LDO_FCOFFT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16317;"	d
+RG_TURISMO_TRX_SX_LDO_FCOFFT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16316;"	d
+RG_TURISMO_TRX_SX_LDO_FCOFFT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16318;"	d
+RG_TURISMO_TRX_SX_LDO_FCOFFT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16320;"	d
+RG_TURISMO_TRX_SX_LDO_LO_LEVEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15019;"	d
+RG_TURISMO_TRX_SX_LDO_LO_LEVEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15017;"	d
+RG_TURISMO_TRX_SX_LDO_LO_LEVEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15016;"	d
+RG_TURISMO_TRX_SX_LDO_LO_LEVEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15018;"	d
+RG_TURISMO_TRX_SX_LDO_LO_LEVEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15020;"	d
+RG_TURISMO_TRX_SX_LDO_VCO_LEVEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15029;"	d
+RG_TURISMO_TRX_SX_LDO_VCO_LEVEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15027;"	d
+RG_TURISMO_TRX_SX_LDO_VCO_LEVEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15026;"	d
+RG_TURISMO_TRX_SX_LDO_VCO_LEVEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15028;"	d
+RG_TURISMO_TRX_SX_LDO_VCO_LEVEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15030;"	d
+RG_TURISMO_TRX_SX_LO_TIMES_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16404;"	d
+RG_TURISMO_TRX_SX_LO_TIMES_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16402;"	d
+RG_TURISMO_TRX_SX_LO_TIMES_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16401;"	d
+RG_TURISMO_TRX_SX_LO_TIMES_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16403;"	d
+RG_TURISMO_TRX_SX_LO_TIMES_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16405;"	d
+RG_TURISMO_TRX_SX_LPF_C1_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16499;"	d
+RG_TURISMO_TRX_SX_LPF_C1_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16497;"	d
+RG_TURISMO_TRX_SX_LPF_C1_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16496;"	d
+RG_TURISMO_TRX_SX_LPF_C1_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16498;"	d
+RG_TURISMO_TRX_SX_LPF_C1_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16500;"	d
+RG_TURISMO_TRX_SX_LPF_C1_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16524;"	d
+RG_TURISMO_TRX_SX_LPF_C1_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16522;"	d
+RG_TURISMO_TRX_SX_LPF_C1_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16521;"	d
+RG_TURISMO_TRX_SX_LPF_C1_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16523;"	d
+RG_TURISMO_TRX_SX_LPF_C1_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16525;"	d
+RG_TURISMO_TRX_SX_LPF_C2_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16504;"	d
+RG_TURISMO_TRX_SX_LPF_C2_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16502;"	d
+RG_TURISMO_TRX_SX_LPF_C2_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16501;"	d
+RG_TURISMO_TRX_SX_LPF_C2_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16503;"	d
+RG_TURISMO_TRX_SX_LPF_C2_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16505;"	d
+RG_TURISMO_TRX_SX_LPF_C2_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16529;"	d
+RG_TURISMO_TRX_SX_LPF_C2_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16527;"	d
+RG_TURISMO_TRX_SX_LPF_C2_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16526;"	d
+RG_TURISMO_TRX_SX_LPF_C2_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16528;"	d
+RG_TURISMO_TRX_SX_LPF_C2_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16530;"	d
+RG_TURISMO_TRX_SX_LPF_C3_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16509;"	d
+RG_TURISMO_TRX_SX_LPF_C3_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16507;"	d
+RG_TURISMO_TRX_SX_LPF_C3_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16506;"	d
+RG_TURISMO_TRX_SX_LPF_C3_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16508;"	d
+RG_TURISMO_TRX_SX_LPF_C3_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16510;"	d
+RG_TURISMO_TRX_SX_LPF_C3_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16534;"	d
+RG_TURISMO_TRX_SX_LPF_C3_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16532;"	d
+RG_TURISMO_TRX_SX_LPF_C3_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16531;"	d
+RG_TURISMO_TRX_SX_LPF_C3_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16533;"	d
+RG_TURISMO_TRX_SX_LPF_C3_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16535;"	d
+RG_TURISMO_TRX_SX_LPF_R2_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16514;"	d
+RG_TURISMO_TRX_SX_LPF_R2_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16512;"	d
+RG_TURISMO_TRX_SX_LPF_R2_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16511;"	d
+RG_TURISMO_TRX_SX_LPF_R2_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16513;"	d
+RG_TURISMO_TRX_SX_LPF_R2_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16515;"	d
+RG_TURISMO_TRX_SX_LPF_R2_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16539;"	d
+RG_TURISMO_TRX_SX_LPF_R2_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16537;"	d
+RG_TURISMO_TRX_SX_LPF_R2_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16536;"	d
+RG_TURISMO_TRX_SX_LPF_R2_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16538;"	d
+RG_TURISMO_TRX_SX_LPF_R2_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16540;"	d
+RG_TURISMO_TRX_SX_LPF_R3_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16519;"	d
+RG_TURISMO_TRX_SX_LPF_R3_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16517;"	d
+RG_TURISMO_TRX_SX_LPF_R3_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16516;"	d
+RG_TURISMO_TRX_SX_LPF_R3_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16518;"	d
+RG_TURISMO_TRX_SX_LPF_R3_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16520;"	d
+RG_TURISMO_TRX_SX_LPF_R3_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16544;"	d
+RG_TURISMO_TRX_SX_LPF_R3_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16542;"	d
+RG_TURISMO_TRX_SX_LPF_R3_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16541;"	d
+RG_TURISMO_TRX_SX_LPF_R3_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16543;"	d
+RG_TURISMO_TRX_SX_LPF_R3_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16545;"	d
+RG_TURISMO_TRX_SX_LPF_VTUNE_TEST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16869;"	d
+RG_TURISMO_TRX_SX_LPF_VTUNE_TEST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16867;"	d
+RG_TURISMO_TRX_SX_LPF_VTUNE_TEST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16866;"	d
+RG_TURISMO_TRX_SX_LPF_VTUNE_TEST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16868;"	d
+RG_TURISMO_TRX_SX_LPF_VTUNE_TEST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16870;"	d
+RG_TURISMO_TRX_SX_MOD_ORDER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16714;"	d
+RG_TURISMO_TRX_SX_MOD_ORDER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16712;"	d
+RG_TURISMO_TRX_SX_MOD_ORDER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16711;"	d
+RG_TURISMO_TRX_SX_MOD_ORDER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16713;"	d
+RG_TURISMO_TRX_SX_MOD_ORDER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16715;"	d
+RG_TURISMO_TRX_SX_PFD_DIV_EDGE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16479;"	d
+RG_TURISMO_TRX_SX_PFD_DIV_EDGE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16477;"	d
+RG_TURISMO_TRX_SX_PFD_DIV_EDGE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16476;"	d
+RG_TURISMO_TRX_SX_PFD_DIV_EDGE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16478;"	d
+RG_TURISMO_TRX_SX_PFD_DIV_EDGE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16480;"	d
+RG_TURISMO_TRX_SX_PFD_REF_EDGE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16474;"	d
+RG_TURISMO_TRX_SX_PFD_REF_EDGE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16472;"	d
+RG_TURISMO_TRX_SX_PFD_REF_EDGE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16471;"	d
+RG_TURISMO_TRX_SX_PFD_REF_EDGE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16473;"	d
+RG_TURISMO_TRX_SX_PFD_REF_EDGE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16475;"	d
+RG_TURISMO_TRX_SX_PFD_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16174;"	d
+RG_TURISMO_TRX_SX_PFD_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16172;"	d
+RG_TURISMO_TRX_SX_PFD_RST_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16169;"	d
+RG_TURISMO_TRX_SX_PFD_RST_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16167;"	d
+RG_TURISMO_TRX_SX_PFD_RST_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16166;"	d
+RG_TURISMO_TRX_SX_PFD_RST_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16168;"	d
+RG_TURISMO_TRX_SX_PFD_RST_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16170;"	d
+RG_TURISMO_TRX_SX_PFD_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16171;"	d
+RG_TURISMO_TRX_SX_PFD_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16173;"	d
+RG_TURISMO_TRX_SX_PFD_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16175;"	d
+RG_TURISMO_TRX_SX_PFD_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16454;"	d
+RG_TURISMO_TRX_SX_PFD_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16452;"	d
+RG_TURISMO_TRX_SX_PFD_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16451;"	d
+RG_TURISMO_TRX_SX_PFD_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16453;"	d
+RG_TURISMO_TRX_SX_PFD_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16455;"	d
+RG_TURISMO_TRX_SX_PFD_SET1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16464;"	d
+RG_TURISMO_TRX_SX_PFD_SET1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16462;"	d
+RG_TURISMO_TRX_SX_PFD_SET1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16461;"	d
+RG_TURISMO_TRX_SX_PFD_SET1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16463;"	d
+RG_TURISMO_TRX_SX_PFD_SET1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16465;"	d
+RG_TURISMO_TRX_SX_PFD_SET2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16469;"	d
+RG_TURISMO_TRX_SX_PFD_SET2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16467;"	d
+RG_TURISMO_TRX_SX_PFD_SET2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16466;"	d
+RG_TURISMO_TRX_SX_PFD_SET2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16468;"	d
+RG_TURISMO_TRX_SX_PFD_SET2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16470;"	d
+RG_TURISMO_TRX_SX_PFD_SET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16459;"	d
+RG_TURISMO_TRX_SX_PFD_SET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16457;"	d
+RG_TURISMO_TRX_SX_PFD_SET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16456;"	d
+RG_TURISMO_TRX_SX_PFD_SET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16458;"	d
+RG_TURISMO_TRX_SX_PFD_SET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16460;"	d
+RG_TURISMO_TRX_SX_PFD_TLSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16494;"	d
+RG_TURISMO_TRX_SX_PFD_TLSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16492;"	d
+RG_TURISMO_TRX_SX_PFD_TLSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16491;"	d
+RG_TURISMO_TRX_SX_PFD_TLSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16493;"	d
+RG_TURISMO_TRX_SX_PFD_TLSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16495;"	d
+RG_TURISMO_TRX_SX_PFD_TRDN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16489;"	d
+RG_TURISMO_TRX_SX_PFD_TRDN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16487;"	d
+RG_TURISMO_TRX_SX_PFD_TRDN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16486;"	d
+RG_TURISMO_TRX_SX_PFD_TRDN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16488;"	d
+RG_TURISMO_TRX_SX_PFD_TRDN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16490;"	d
+RG_TURISMO_TRX_SX_PFD_TRUP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16484;"	d
+RG_TURISMO_TRX_SX_PFD_TRUP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16482;"	d
+RG_TURISMO_TRX_SX_PFD_TRUP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16481;"	d
+RG_TURISMO_TRX_SX_PFD_TRUP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16483;"	d
+RG_TURISMO_TRX_SX_PFD_TRUP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16485;"	d
+RG_TURISMO_TRX_SX_RFCH_MAP_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16384;"	d
+RG_TURISMO_TRX_SX_RFCH_MAP_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16382;"	d
+RG_TURISMO_TRX_SX_RFCH_MAP_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16381;"	d
+RG_TURISMO_TRX_SX_RFCH_MAP_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16383;"	d
+RG_TURISMO_TRX_SX_RFCH_MAP_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16385;"	d
+RG_TURISMO_TRX_SX_RFCTRL_CH_10_8_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16379;"	d
+RG_TURISMO_TRX_SX_RFCTRL_CH_10_8_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16377;"	d
+RG_TURISMO_TRX_SX_RFCTRL_CH_10_8_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16376;"	d
+RG_TURISMO_TRX_SX_RFCTRL_CH_10_8_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16378;"	d
+RG_TURISMO_TRX_SX_RFCTRL_CH_10_8_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16380;"	d
+RG_TURISMO_TRX_SX_RFCTRL_CH_7_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16374;"	d
+RG_TURISMO_TRX_SX_RFCTRL_CH_7_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16372;"	d
+RG_TURISMO_TRX_SX_RFCTRL_CH_7_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16371;"	d
+RG_TURISMO_TRX_SX_RFCTRL_CH_7_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16373;"	d
+RG_TURISMO_TRX_SX_RFCTRL_CH_7_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16375;"	d
+RG_TURISMO_TRX_SX_RFCTRL_F_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16369;"	d
+RG_TURISMO_TRX_SX_RFCTRL_F_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16367;"	d
+RG_TURISMO_TRX_SX_RFCTRL_F_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16366;"	d
+RG_TURISMO_TRX_SX_RFCTRL_F_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16368;"	d
+RG_TURISMO_TRX_SX_RFCTRL_F_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16370;"	d
+RG_TURISMO_TRX_SX_SBCAL_AW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16244;"	d
+RG_TURISMO_TRX_SX_SBCAL_AW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16242;"	d
+RG_TURISMO_TRX_SX_SBCAL_AW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16241;"	d
+RG_TURISMO_TRX_SX_SBCAL_AW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16243;"	d
+RG_TURISMO_TRX_SX_SBCAL_AW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16245;"	d
+RG_TURISMO_TRX_SX_SBCAL_CT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16739;"	d
+RG_TURISMO_TRX_SX_SBCAL_CT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16737;"	d
+RG_TURISMO_TRX_SX_SBCAL_CT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16736;"	d
+RG_TURISMO_TRX_SX_SBCAL_CT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16738;"	d
+RG_TURISMO_TRX_SX_SBCAL_CT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16740;"	d
+RG_TURISMO_TRX_SX_SBCAL_DIFFMIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16749;"	d
+RG_TURISMO_TRX_SX_SBCAL_DIFFMIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16747;"	d
+RG_TURISMO_TRX_SX_SBCAL_DIFFMIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16746;"	d
+RG_TURISMO_TRX_SX_SBCAL_DIFFMIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16748;"	d
+RG_TURISMO_TRX_SX_SBCAL_DIFFMIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16750;"	d
+RG_TURISMO_TRX_SX_SBCAL_DIS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16239;"	d
+RG_TURISMO_TRX_SX_SBCAL_DIS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16237;"	d
+RG_TURISMO_TRX_SX_SBCAL_DIS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16236;"	d
+RG_TURISMO_TRX_SX_SBCAL_DIS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16238;"	d
+RG_TURISMO_TRX_SX_SBCAL_DIS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16240;"	d
+RG_TURISMO_TRX_SX_SBCAL_NTARG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16759;"	d
+RG_TURISMO_TRX_SX_SBCAL_NTARG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16757;"	d
+RG_TURISMO_TRX_SX_SBCAL_NTARG_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16754;"	d
+RG_TURISMO_TRX_SX_SBCAL_NTARG_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16752;"	d
+RG_TURISMO_TRX_SX_SBCAL_NTARG_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16751;"	d
+RG_TURISMO_TRX_SX_SBCAL_NTARG_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16753;"	d
+RG_TURISMO_TRX_SX_SBCAL_NTARG_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16755;"	d
+RG_TURISMO_TRX_SX_SBCAL_NTARG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16756;"	d
+RG_TURISMO_TRX_SX_SBCAL_NTARG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16758;"	d
+RG_TURISMO_TRX_SX_SBCAL_NTARG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16760;"	d
+RG_TURISMO_TRX_SX_SBCAL_WT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16744;"	d
+RG_TURISMO_TRX_SX_SBCAL_WT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16742;"	d
+RG_TURISMO_TRX_SX_SBCAL_WT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16741;"	d
+RG_TURISMO_TRX_SX_SBCAL_WT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16743;"	d
+RG_TURISMO_TRX_SX_SBCAL_WT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16745;"	d
+RG_TURISMO_TRX_SX_SUB_C0P5_DIS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16734;"	d
+RG_TURISMO_TRX_SX_SUB_C0P5_DIS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16732;"	d
+RG_TURISMO_TRX_SX_SUB_C0P5_DIS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16731;"	d
+RG_TURISMO_TRX_SX_SUB_C0P5_DIS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16733;"	d
+RG_TURISMO_TRX_SX_SUB_C0P5_DIS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16735;"	d
+RG_TURISMO_TRX_SX_SUB_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16729;"	d
+RG_TURISMO_TRX_SX_SUB_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16727;"	d
+RG_TURISMO_TRX_SX_SUB_SEL_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16724;"	d
+RG_TURISMO_TRX_SX_SUB_SEL_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16722;"	d
+RG_TURISMO_TRX_SX_SUB_SEL_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16721;"	d
+RG_TURISMO_TRX_SX_SUB_SEL_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16723;"	d
+RG_TURISMO_TRX_SX_SUB_SEL_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16725;"	d
+RG_TURISMO_TRX_SX_SUB_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16726;"	d
+RG_TURISMO_TRX_SX_SUB_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16728;"	d
+RG_TURISMO_TRX_SX_SUB_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16730;"	d
+RG_TURISMO_TRX_SX_TTL_ACCUM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16844;"	d
+RG_TURISMO_TRX_SX_TTL_ACCUM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16842;"	d
+RG_TURISMO_TRX_SX_TTL_ACCUM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16841;"	d
+RG_TURISMO_TRX_SX_TTL_ACCUM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16843;"	d
+RG_TURISMO_TRX_SX_TTL_ACCUM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16845;"	d
+RG_TURISMO_TRX_SX_TTL_CPT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16839;"	d
+RG_TURISMO_TRX_SX_TTL_CPT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16837;"	d
+RG_TURISMO_TRX_SX_TTL_CPT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16836;"	d
+RG_TURISMO_TRX_SX_TTL_CPT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16838;"	d
+RG_TURISMO_TRX_SX_TTL_CPT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16840;"	d
+RG_TURISMO_TRX_SX_TTL_DIS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16254;"	d
+RG_TURISMO_TRX_SX_TTL_DIS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16252;"	d
+RG_TURISMO_TRX_SX_TTL_DIS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16251;"	d
+RG_TURISMO_TRX_SX_TTL_DIS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16253;"	d
+RG_TURISMO_TRX_SX_TTL_DIS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16255;"	d
+RG_TURISMO_TRX_SX_TTL_FPT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16834;"	d
+RG_TURISMO_TRX_SX_TTL_FPT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16832;"	d
+RG_TURISMO_TRX_SX_TTL_FPT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16831;"	d
+RG_TURISMO_TRX_SX_TTL_FPT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16833;"	d
+RG_TURISMO_TRX_SX_TTL_FPT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16835;"	d
+RG_TURISMO_TRX_SX_TTL_INIT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16829;"	d
+RG_TURISMO_TRX_SX_TTL_INIT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16827;"	d
+RG_TURISMO_TRX_SX_TTL_INIT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16826;"	d
+RG_TURISMO_TRX_SX_TTL_INIT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16828;"	d
+RG_TURISMO_TRX_SX_TTL_INIT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16830;"	d
+RG_TURISMO_TRX_SX_TTL_SUB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16849;"	d
+RG_TURISMO_TRX_SX_TTL_SUB_INV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16854;"	d
+RG_TURISMO_TRX_SX_TTL_SUB_INV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16852;"	d
+RG_TURISMO_TRX_SX_TTL_SUB_INV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16851;"	d
+RG_TURISMO_TRX_SX_TTL_SUB_INV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16853;"	d
+RG_TURISMO_TRX_SX_TTL_SUB_INV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16855;"	d
+RG_TURISMO_TRX_SX_TTL_SUB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16847;"	d
+RG_TURISMO_TRX_SX_TTL_SUB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16846;"	d
+RG_TURISMO_TRX_SX_TTL_SUB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16848;"	d
+RG_TURISMO_TRX_SX_TTL_SUB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16850;"	d
+RG_TURISMO_TRX_SX_TTL_VH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16859;"	d
+RG_TURISMO_TRX_SX_TTL_VH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16857;"	d
+RG_TURISMO_TRX_SX_TTL_VH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16856;"	d
+RG_TURISMO_TRX_SX_TTL_VH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16858;"	d
+RG_TURISMO_TRX_SX_TTL_VH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16860;"	d
+RG_TURISMO_TRX_SX_TTL_VL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16864;"	d
+RG_TURISMO_TRX_SX_TTL_VL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16862;"	d
+RG_TURISMO_TRX_SX_TTL_VL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16861;"	d
+RG_TURISMO_TRX_SX_TTL_VL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16863;"	d
+RG_TURISMO_TRX_SX_TTL_VL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16865;"	d
+RG_TURISMO_TRX_SX_UOP_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16184;"	d
+RG_TURISMO_TRX_SX_UOP_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16182;"	d
+RG_TURISMO_TRX_SX_UOP_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16181;"	d
+RG_TURISMO_TRX_SX_UOP_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16183;"	d
+RG_TURISMO_TRX_SX_UOP_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16185;"	d
+RG_TURISMO_TRX_SX_UOP_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16179;"	d
+RG_TURISMO_TRX_SX_UOP_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16177;"	d
+RG_TURISMO_TRX_SX_UOP_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16176;"	d
+RG_TURISMO_TRX_SX_UOP_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16178;"	d
+RG_TURISMO_TRX_SX_UOP_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16180;"	d
+RG_TURISMO_TRX_SX_VCO_CS_AWH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16604;"	d
+RG_TURISMO_TRX_SX_VCO_CS_AWH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16602;"	d
+RG_TURISMO_TRX_SX_VCO_CS_AWH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16601;"	d
+RG_TURISMO_TRX_SX_VCO_CS_AWH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16603;"	d
+RG_TURISMO_TRX_SX_VCO_CS_AWH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16605;"	d
+RG_TURISMO_TRX_SX_VCO_ISEL_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16554;"	d
+RG_TURISMO_TRX_SX_VCO_ISEL_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16552;"	d
+RG_TURISMO_TRX_SX_VCO_ISEL_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16551;"	d
+RG_TURISMO_TRX_SX_VCO_ISEL_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16553;"	d
+RG_TURISMO_TRX_SX_VCO_ISEL_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16555;"	d
+RG_TURISMO_TRX_SX_VCO_ISEL_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16549;"	d
+RG_TURISMO_TRX_SX_VCO_ISEL_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16547;"	d
+RG_TURISMO_TRX_SX_VCO_ISEL_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16546;"	d
+RG_TURISMO_TRX_SX_VCO_ISEL_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16548;"	d
+RG_TURISMO_TRX_SX_VCO_ISEL_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16550;"	d
+RG_TURISMO_TRX_SX_VCO_ISEL_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16574;"	d
+RG_TURISMO_TRX_SX_VCO_ISEL_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16572;"	d
+RG_TURISMO_TRX_SX_VCO_ISEL_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16571;"	d
+RG_TURISMO_TRX_SX_VCO_ISEL_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16573;"	d
+RG_TURISMO_TRX_SX_VCO_ISEL_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16575;"	d
+RG_TURISMO_TRX_SX_VCO_KVDOUB_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16569;"	d
+RG_TURISMO_TRX_SX_VCO_KVDOUB_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16567;"	d
+RG_TURISMO_TRX_SX_VCO_KVDOUB_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16566;"	d
+RG_TURISMO_TRX_SX_VCO_KVDOUB_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16568;"	d
+RG_TURISMO_TRX_SX_VCO_KVDOUB_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16570;"	d
+RG_TURISMO_TRX_SX_VCO_KVDOUB_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16589;"	d
+RG_TURISMO_TRX_SX_VCO_KVDOUB_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16587;"	d
+RG_TURISMO_TRX_SX_VCO_KVDOUB_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16586;"	d
+RG_TURISMO_TRX_SX_VCO_KVDOUB_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16588;"	d
+RG_TURISMO_TRX_SX_VCO_KVDOUB_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16590;"	d
+RG_TURISMO_TRX_SX_VCO_LPM_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16559;"	d
+RG_TURISMO_TRX_SX_VCO_LPM_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16557;"	d
+RG_TURISMO_TRX_SX_VCO_LPM_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16556;"	d
+RG_TURISMO_TRX_SX_VCO_LPM_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16558;"	d
+RG_TURISMO_TRX_SX_VCO_LPM_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16560;"	d
+RG_TURISMO_TRX_SX_VCO_LPM_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16579;"	d
+RG_TURISMO_TRX_SX_VCO_LPM_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16577;"	d
+RG_TURISMO_TRX_SX_VCO_LPM_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16576;"	d
+RG_TURISMO_TRX_SX_VCO_LPM_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16578;"	d
+RG_TURISMO_TRX_SX_VCO_LPM_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16580;"	d
+RG_TURISMO_TRX_SX_VCO_RTAIL_SHIFT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16599;"	d
+RG_TURISMO_TRX_SX_VCO_RTAIL_SHIFT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16597;"	d
+RG_TURISMO_TRX_SX_VCO_RTAIL_SHIFT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16596;"	d
+RG_TURISMO_TRX_SX_VCO_RTAIL_SHIFT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16598;"	d
+RG_TURISMO_TRX_SX_VCO_RTAIL_SHIFT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16600;"	d
+RG_TURISMO_TRX_SX_VCO_RXOB_AW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16659;"	d
+RG_TURISMO_TRX_SX_VCO_RXOB_AW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16657;"	d
+RG_TURISMO_TRX_SX_VCO_RXOB_AW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16656;"	d
+RG_TURISMO_TRX_SX_VCO_RXOB_AW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16658;"	d
+RG_TURISMO_TRX_SX_VCO_RXOB_AW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16660;"	d
+RG_TURISMO_TRX_SX_VCO_TXOB_AW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16654;"	d
+RG_TURISMO_TRX_SX_VCO_TXOB_AW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16652;"	d
+RG_TURISMO_TRX_SX_VCO_TXOB_AW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16651;"	d
+RG_TURISMO_TRX_SX_VCO_TXOB_AW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16653;"	d
+RG_TURISMO_TRX_SX_VCO_TXOB_AW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16655;"	d
+RG_TURISMO_TRX_SX_VCO_VARBSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16594;"	d
+RG_TURISMO_TRX_SX_VCO_VARBSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16592;"	d
+RG_TURISMO_TRX_SX_VCO_VARBSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16591;"	d
+RG_TURISMO_TRX_SX_VCO_VARBSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16593;"	d
+RG_TURISMO_TRX_SX_VCO_VARBSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16595;"	d
+RG_TURISMO_TRX_SX_VCO_VCCBSEL_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16564;"	d
+RG_TURISMO_TRX_SX_VCO_VCCBSEL_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16562;"	d
+RG_TURISMO_TRX_SX_VCO_VCCBSEL_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16561;"	d
+RG_TURISMO_TRX_SX_VCO_VCCBSEL_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16563;"	d
+RG_TURISMO_TRX_SX_VCO_VCCBSEL_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16565;"	d
+RG_TURISMO_TRX_SX_VCO_VCCBSEL_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16584;"	d
+RG_TURISMO_TRX_SX_VCO_VCCBSEL_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16582;"	d
+RG_TURISMO_TRX_SX_VCO_VCCBSEL_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16581;"	d
+RG_TURISMO_TRX_SX_VCO_VCCBSEL_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16583;"	d
+RG_TURISMO_TRX_SX_VCO_VCCBSEL_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16585;"	d
+RG_TURISMO_TRX_SX_XTAL_FREQ_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16389;"	d
+RG_TURISMO_TRX_SX_XTAL_FREQ_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16387;"	d
+RG_TURISMO_TRX_SX_XTAL_FREQ_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16386;"	d
+RG_TURISMO_TRX_SX_XTAL_FREQ_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16388;"	d
+RG_TURISMO_TRX_SX_XTAL_FREQ_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16390;"	d
+RG_TURISMO_TRX_TONE_GEN_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20274;"	d
+RG_TURISMO_TRX_TONE_GEN_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20272;"	d
+RG_TURISMO_TRX_TONE_GEN_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20271;"	d
+RG_TURISMO_TRX_TONE_GEN_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20273;"	d
+RG_TURISMO_TRX_TONE_GEN_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20275;"	d
+RG_TURISMO_TRX_TONE_SCALE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20264;"	d
+RG_TURISMO_TRX_TONE_SCALE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20262;"	d
+RG_TURISMO_TRX_TONE_SCALE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20261;"	d
+RG_TURISMO_TRX_TONE_SCALE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20263;"	d
+RG_TURISMO_TRX_TONE_SCALE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20265;"	d
+RG_TURISMO_TRX_TXBTPA_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17784;"	d
+RG_TURISMO_TRX_TXBTPA_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17782;"	d
+RG_TURISMO_TRX_TXBTPA_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17781;"	d
+RG_TURISMO_TRX_TXBTPA_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17783;"	d
+RG_TURISMO_TRX_TXBTPA_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17785;"	d
+RG_TURISMO_TRX_TXDAC_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17764;"	d
+RG_TURISMO_TRX_TXDAC_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17762;"	d
+RG_TURISMO_TRX_TXDAC_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17761;"	d
+RG_TURISMO_TRX_TXDAC_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17763;"	d
+RG_TURISMO_TRX_TXDAC_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17765;"	d
+RG_TURISMO_TRX_TXDAC_R2T_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17809;"	d
+RG_TURISMO_TRX_TXDAC_R2T_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17807;"	d
+RG_TURISMO_TRX_TXDAC_R2T_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17806;"	d
+RG_TURISMO_TRX_TXDAC_R2T_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17808;"	d
+RG_TURISMO_TRX_TXDAC_R2T_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17810;"	d
+RG_TURISMO_TRX_TXDAC_T2R_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17789;"	d
+RG_TURISMO_TRX_TXDAC_T2R_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17787;"	d
+RG_TURISMO_TRX_TXDAC_T2R_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17786;"	d
+RG_TURISMO_TRX_TXDAC_T2R_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17788;"	d
+RG_TURISMO_TRX_TXDAC_T2R_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17790;"	d
+RG_TURISMO_TRX_TXGAIN_PHYCTRL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14629;"	d
+RG_TURISMO_TRX_TXGAIN_PHYCTRL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14627;"	d
+RG_TURISMO_TRX_TXGAIN_PHYCTRL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14626;"	d
+RG_TURISMO_TRX_TXGAIN_PHYCTRL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14628;"	d
+RG_TURISMO_TRX_TXGAIN_PHYCTRL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14630;"	d
+RG_TURISMO_TRX_TXIQ_NOSHRK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20249;"	d
+RG_TURISMO_TRX_TXIQ_NOSHRK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20247;"	d
+RG_TURISMO_TRX_TXIQ_NOSHRK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20246;"	d
+RG_TURISMO_TRX_TXIQ_NOSHRK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20248;"	d
+RG_TURISMO_TRX_TXIQ_NOSHRK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20250;"	d
+RG_TURISMO_TRX_TXLPF_BYPASS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14914;"	d
+RG_TURISMO_TRX_TXLPF_BYPASS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14912;"	d
+RG_TURISMO_TRX_TXLPF_BYPASS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14911;"	d
+RG_TURISMO_TRX_TXLPF_BYPASS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14913;"	d
+RG_TURISMO_TRX_TXLPF_BYPASS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14915;"	d
+RG_TURISMO_TRX_TXLPF_GMCELL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15444;"	d
+RG_TURISMO_TRX_TXLPF_GMCELL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15442;"	d
+RG_TURISMO_TRX_TXLPF_GMCELL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15441;"	d
+RG_TURISMO_TRX_TXLPF_GMCELL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15443;"	d
+RG_TURISMO_TRX_TXLPF_GMCELL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15445;"	d
+RG_TURISMO_TRX_TXMOD_GMCELL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15439;"	d
+RG_TURISMO_TRX_TXMOD_GMCELL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15437;"	d
+RG_TURISMO_TRX_TXMOD_GMCELL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15436;"	d
+RG_TURISMO_TRX_TXMOD_GMCELL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15438;"	d
+RG_TURISMO_TRX_TXMOD_GMCELL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15440;"	d
+RG_TURISMO_TRX_TXPA_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17774;"	d
+RG_TURISMO_TRX_TXPA_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17772;"	d
+RG_TURISMO_TRX_TXPA_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17771;"	d
+RG_TURISMO_TRX_TXPA_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17773;"	d
+RG_TURISMO_TRX_TXPA_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17775;"	d
+RG_TURISMO_TRX_TXPA_R2T_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17819;"	d
+RG_TURISMO_TRX_TXPA_R2T_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17817;"	d
+RG_TURISMO_TRX_TXPA_R2T_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17816;"	d
+RG_TURISMO_TRX_TXPA_R2T_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17818;"	d
+RG_TURISMO_TRX_TXPA_R2T_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17820;"	d
+RG_TURISMO_TRX_TXPA_T2R_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17799;"	d
+RG_TURISMO_TRX_TXPA_T2R_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17797;"	d
+RG_TURISMO_TRX_TXPA_T2R_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17796;"	d
+RG_TURISMO_TRX_TXPA_T2R_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17798;"	d
+RG_TURISMO_TRX_TXPA_T2R_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17800;"	d
+RG_TURISMO_TRX_TXPGA_MAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15429;"	d
+RG_TURISMO_TRX_TXPGA_MAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15427;"	d
+RG_TURISMO_TRX_TXPGA_MAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15426;"	d
+RG_TURISMO_TRX_TXPGA_MAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15428;"	d
+RG_TURISMO_TRX_TXPGA_MAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15430;"	d
+RG_TURISMO_TRX_TXPGA_STEER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15434;"	d
+RG_TURISMO_TRX_TXPGA_STEER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15432;"	d
+RG_TURISMO_TRX_TXPGA_STEER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15431;"	d
+RG_TURISMO_TRX_TXPGA_STEER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15433;"	d
+RG_TURISMO_TRX_TXPGA_STEER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15435;"	d
+RG_TURISMO_TRX_TXRF_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17769;"	d
+RG_TURISMO_TRX_TXRF_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17767;"	d
+RG_TURISMO_TRX_TXRF_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17766;"	d
+RG_TURISMO_TRX_TXRF_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17768;"	d
+RG_TURISMO_TRX_TXRF_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17770;"	d
+RG_TURISMO_TRX_TXRF_R2T_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17814;"	d
+RG_TURISMO_TRX_TXRF_R2T_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17812;"	d
+RG_TURISMO_TRX_TXRF_R2T_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17811;"	d
+RG_TURISMO_TRX_TXRF_R2T_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17813;"	d
+RG_TURISMO_TRX_TXRF_R2T_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17815;"	d
+RG_TURISMO_TRX_TXRF_T2R_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17794;"	d
+RG_TURISMO_TRX_TXRF_T2R_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17792;"	d
+RG_TURISMO_TRX_TXRF_T2R_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17791;"	d
+RG_TURISMO_TRX_TXRF_T2R_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17793;"	d
+RG_TURISMO_TRX_TXRF_T2R_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17795;"	d
+RG_TURISMO_TRX_TX_BT_PA_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14814;"	d
+RG_TURISMO_TRX_TX_BT_PA_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14812;"	d
+RG_TURISMO_TRX_TX_BT_PA_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14811;"	d
+RG_TURISMO_TRX_TX_BT_PA_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14813;"	d
+RG_TURISMO_TRX_TX_BT_PA_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14815;"	d
+RG_TURISMO_TRX_TX_CAPSW_STEP0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20114;"	d
+RG_TURISMO_TRX_TX_CAPSW_STEP0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20112;"	d
+RG_TURISMO_TRX_TX_CAPSW_STEP0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20111;"	d
+RG_TURISMO_TRX_TX_CAPSW_STEP0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20113;"	d
+RG_TURISMO_TRX_TX_CAPSW_STEP0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20115;"	d
+RG_TURISMO_TRX_TX_CAPSW_STEP1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20119;"	d
+RG_TURISMO_TRX_TX_CAPSW_STEP1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20117;"	d
+RG_TURISMO_TRX_TX_CAPSW_STEP1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20116;"	d
+RG_TURISMO_TRX_TX_CAPSW_STEP1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20118;"	d
+RG_TURISMO_TRX_TX_CAPSW_STEP1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20120;"	d
+RG_TURISMO_TRX_TX_CAPSW_STEP2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20124;"	d
+RG_TURISMO_TRX_TX_CAPSW_STEP2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20122;"	d
+RG_TURISMO_TRX_TX_CAPSW_STEP2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20121;"	d
+RG_TURISMO_TRX_TX_CAPSW_STEP2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20123;"	d
+RG_TURISMO_TRX_TX_CAPSW_STEP2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20125;"	d
+RG_TURISMO_TRX_TX_CAPSW_STEP3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20129;"	d
+RG_TURISMO_TRX_TX_CAPSW_STEP3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20127;"	d
+RG_TURISMO_TRX_TX_CAPSW_STEP3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20126;"	d
+RG_TURISMO_TRX_TX_CAPSW_STEP3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20128;"	d
+RG_TURISMO_TRX_TX_CAPSW_STEP3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20130;"	d
+RG_TURISMO_TRX_TX_CAPSW_STEP4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20134;"	d
+RG_TURISMO_TRX_TX_CAPSW_STEP4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20132;"	d
+RG_TURISMO_TRX_TX_CAPSW_STEP4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20131;"	d
+RG_TURISMO_TRX_TX_CAPSW_STEP4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20133;"	d
+RG_TURISMO_TRX_TX_CAPSW_STEP4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20135;"	d
+RG_TURISMO_TRX_TX_CAPSW_STEP5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20139;"	d
+RG_TURISMO_TRX_TX_CAPSW_STEP5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20137;"	d
+RG_TURISMO_TRX_TX_CAPSW_STEP5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20136;"	d
+RG_TURISMO_TRX_TX_CAPSW_STEP5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20138;"	d
+RG_TURISMO_TRX_TX_CAPSW_STEP5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20140;"	d
+RG_TURISMO_TRX_TX_CAPSW_STEP6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20144;"	d
+RG_TURISMO_TRX_TX_CAPSW_STEP6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20142;"	d
+RG_TURISMO_TRX_TX_CAPSW_STEP6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20141;"	d
+RG_TURISMO_TRX_TX_CAPSW_STEP6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20143;"	d
+RG_TURISMO_TRX_TX_CAPSW_STEP6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20145;"	d
+RG_TURISMO_TRX_TX_DAC_CAL_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14849;"	d
+RG_TURISMO_TRX_TX_DAC_CAL_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14847;"	d
+RG_TURISMO_TRX_TX_DAC_CAL_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14846;"	d
+RG_TURISMO_TRX_TX_DAC_CAL_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14848;"	d
+RG_TURISMO_TRX_TX_DAC_CAL_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14850;"	d
+RG_TURISMO_TRX_TX_DAC_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14784;"	d
+RG_TURISMO_TRX_TX_DAC_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14782;"	d
+RG_TURISMO_TRX_TX_DAC_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14781;"	d
+RG_TURISMO_TRX_TX_DAC_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14783;"	d
+RG_TURISMO_TRX_TX_DAC_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14785;"	d
+RG_TURISMO_TRX_TX_DAC_TSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16064;"	d
+RG_TURISMO_TRX_TX_DAC_TSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16062;"	d
+RG_TURISMO_TRX_TX_DAC_TSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16061;"	d
+RG_TURISMO_TRX_TX_DAC_TSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16063;"	d
+RG_TURISMO_TRX_TX_DAC_TSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16065;"	d
+RG_TURISMO_TRX_TX_DCCAL_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17844;"	d
+RG_TURISMO_TRX_TX_DCCAL_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17842;"	d
+RG_TURISMO_TRX_TX_DCCAL_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17841;"	d
+RG_TURISMO_TRX_TX_DCCAL_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17843;"	d
+RG_TURISMO_TRX_TX_DCCAL_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17845;"	d
+RG_TURISMO_TRX_TX_DIV2_BUF_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14804;"	d
+RG_TURISMO_TRX_TX_DIV2_BUF_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14802;"	d
+RG_TURISMO_TRX_TX_DIV2_BUF_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14801;"	d
+RG_TURISMO_TRX_TX_DIV2_BUF_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14803;"	d
+RG_TURISMO_TRX_TX_DIV2_BUF_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14805;"	d
+RG_TURISMO_TRX_TX_DIV2_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14794;"	d
+RG_TURISMO_TRX_TX_DIV2_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14792;"	d
+RG_TURISMO_TRX_TX_DIV2_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14791;"	d
+RG_TURISMO_TRX_TX_DIV2_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14793;"	d
+RG_TURISMO_TRX_TX_DIV2_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14795;"	d
+RG_TURISMO_TRX_TX_DPDGM_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15264;"	d
+RG_TURISMO_TRX_TX_DPDGM_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15262;"	d
+RG_TURISMO_TRX_TX_DPDGM_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15261;"	d
+RG_TURISMO_TRX_TX_DPDGM_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15263;"	d
+RG_TURISMO_TRX_TX_DPDGM_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15265;"	d
+RG_TURISMO_TRX_TX_DPD_DIV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15269;"	d
+RG_TURISMO_TRX_TX_DPD_DIV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15267;"	d
+RG_TURISMO_TRX_TX_DPD_DIV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15266;"	d
+RG_TURISMO_TRX_TX_DPD_DIV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15268;"	d
+RG_TURISMO_TRX_TX_DPD_DIV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15270;"	d
+RG_TURISMO_TRX_TX_DPD_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14889;"	d
+RG_TURISMO_TRX_TX_DPD_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14887;"	d
+RG_TURISMO_TRX_TX_DPD_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14886;"	d
+RG_TURISMO_TRX_TX_DPD_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14888;"	d
+RG_TURISMO_TRX_TX_DPD_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14890;"	d
+RG_TURISMO_TRX_TX_EN_VOLTAGE_IN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14919;"	d
+RG_TURISMO_TRX_TX_EN_VOLTAGE_IN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14917;"	d
+RG_TURISMO_TRX_TX_EN_VOLTAGE_IN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14916;"	d
+RG_TURISMO_TRX_TX_EN_VOLTAGE_IN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14918;"	d
+RG_TURISMO_TRX_TX_EN_VOLTAGE_IN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14920;"	d
+RG_TURISMO_TRX_TX_FREQ_OFFSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20259;"	d
+RG_TURISMO_TRX_TX_FREQ_OFFSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20257;"	d
+RG_TURISMO_TRX_TX_FREQ_OFFSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20256;"	d
+RG_TURISMO_TRX_TX_FREQ_OFFSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20258;"	d
+RG_TURISMO_TRX_TX_FREQ_OFFSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20260;"	d
+RG_TURISMO_TRX_TX_GAIN_DPDCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17904;"	d
+RG_TURISMO_TRX_TX_GAIN_DPDCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17902;"	d
+RG_TURISMO_TRX_TX_GAIN_DPDCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17901;"	d
+RG_TURISMO_TRX_TX_GAIN_DPDCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17903;"	d
+RG_TURISMO_TRX_TX_GAIN_DPDCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17905;"	d
+RG_TURISMO_TRX_TX_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14669;"	d
+RG_TURISMO_TRX_TX_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14667;"	d
+RG_TURISMO_TRX_TX_GAIN_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14624;"	d
+RG_TURISMO_TRX_TX_GAIN_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14622;"	d
+RG_TURISMO_TRX_TX_GAIN_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14621;"	d
+RG_TURISMO_TRX_TX_GAIN_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14623;"	d
+RG_TURISMO_TRX_TX_GAIN_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14625;"	d
+RG_TURISMO_TRX_TX_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14666;"	d
+RG_TURISMO_TRX_TX_GAIN_RXIQCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17889;"	d
+RG_TURISMO_TRX_TX_GAIN_RXIQCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17887;"	d
+RG_TURISMO_TRX_TX_GAIN_RXIQCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17886;"	d
+RG_TURISMO_TRX_TX_GAIN_RXIQCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17888;"	d
+RG_TURISMO_TRX_TX_GAIN_RXIQCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17890;"	d
+RG_TURISMO_TRX_TX_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14668;"	d
+RG_TURISMO_TRX_TX_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14670;"	d
+RG_TURISMO_TRX_TX_GAIN_TXCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17874;"	d
+RG_TURISMO_TRX_TX_GAIN_TXCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17872;"	d
+RG_TURISMO_TRX_TX_GAIN_TXCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17871;"	d
+RG_TURISMO_TRX_TX_GAIN_TXCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17873;"	d
+RG_TURISMO_TRX_TX_GAIN_TXCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17875;"	d
+RG_TURISMO_TRX_TX_IQCAL_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17849;"	d
+RG_TURISMO_TRX_TX_IQCAL_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17847;"	d
+RG_TURISMO_TRX_TX_IQCAL_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17846;"	d
+RG_TURISMO_TRX_TX_IQCAL_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17848;"	d
+RG_TURISMO_TRX_TX_IQCAL_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17850;"	d
+RG_TURISMO_TRX_TX_IQCAL_TIME_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20254;"	d
+RG_TURISMO_TRX_TX_IQCAL_TIME_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20252;"	d
+RG_TURISMO_TRX_TX_IQCAL_TIME_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20251;"	d
+RG_TURISMO_TRX_TX_IQCAL_TIME_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20253;"	d
+RG_TURISMO_TRX_TX_IQCAL_TIME_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20255;"	d
+RG_TURISMO_TRX_TX_IQ_ALPHA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20234;"	d
+RG_TURISMO_TRX_TX_IQ_ALPHA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20232;"	d
+RG_TURISMO_TRX_TX_IQ_ALPHA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20231;"	d
+RG_TURISMO_TRX_TX_IQ_ALPHA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20233;"	d
+RG_TURISMO_TRX_TX_IQ_ALPHA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20235;"	d
+RG_TURISMO_TRX_TX_IQ_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20244;"	d
+RG_TURISMO_TRX_TX_IQ_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20242;"	d
+RG_TURISMO_TRX_TX_IQ_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20241;"	d
+RG_TURISMO_TRX_TX_IQ_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20243;"	d
+RG_TURISMO_TRX_TX_IQ_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20245;"	d
+RG_TURISMO_TRX_TX_IQ_THETA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20239;"	d
+RG_TURISMO_TRX_TX_IQ_THETA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20237;"	d
+RG_TURISMO_TRX_TX_IQ_THETA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20236;"	d
+RG_TURISMO_TRX_TX_IQ_THETA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20238;"	d
+RG_TURISMO_TRX_TX_IQ_THETA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20240;"	d
+RG_TURISMO_TRX_TX_MOD_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14774;"	d
+RG_TURISMO_TRX_TX_MOD_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14772;"	d
+RG_TURISMO_TRX_TX_MOD_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14771;"	d
+RG_TURISMO_TRX_TX_MOD_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14773;"	d
+RG_TURISMO_TRX_TX_MOD_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14775;"	d
+RG_TURISMO_TRX_TX_PA_LDO_LEVEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14994;"	d
+RG_TURISMO_TRX_TX_PA_LDO_LEVEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14992;"	d
+RG_TURISMO_TRX_TX_PA_LDO_LEVEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14991;"	d
+RG_TURISMO_TRX_TX_PA_LDO_LEVEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14993;"	d
+RG_TURISMO_TRX_TX_PA_LDO_LEVEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14995;"	d
+RG_TURISMO_TRX_TX_PA_LDO_SEL_RES_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15359;"	d
+RG_TURISMO_TRX_TX_PA_LDO_SEL_RES_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15357;"	d
+RG_TURISMO_TRX_TX_PA_LDO_SEL_RES_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15356;"	d
+RG_TURISMO_TRX_TX_PA_LDO_SEL_RES_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15358;"	d
+RG_TURISMO_TRX_TX_PA_LDO_SEL_RES_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15360;"	d
+RG_TURISMO_TRX_TX_PA_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14764;"	d
+RG_TURISMO_TRX_TX_PA_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14762;"	d
+RG_TURISMO_TRX_TX_PA_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14761;"	d
+RG_TURISMO_TRX_TX_PA_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14763;"	d
+RG_TURISMO_TRX_TX_PA_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14765;"	d
+RG_TURISMO_TRX_TX_SELF_MIXER_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14869;"	d
+RG_TURISMO_TRX_TX_SELF_MIXER_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14867;"	d
+RG_TURISMO_TRX_TX_SELF_MIXER_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14866;"	d
+RG_TURISMO_TRX_TX_SELF_MIXER_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14868;"	d
+RG_TURISMO_TRX_TX_SELF_MIXER_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14870;"	d
+RG_TURISMO_TRX_TX_TRSW_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14674;"	d
+RG_TURISMO_TRX_TX_TRSW_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14672;"	d
+RG_TURISMO_TRX_TX_TRSW_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14671;"	d
+RG_TURISMO_TRX_TX_TRSW_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14673;"	d
+RG_TURISMO_TRX_TX_TRSW_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14675;"	d
+RG_TURISMO_TRX_TX_TSSI_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15274;"	d
+RG_TURISMO_TRX_TX_TSSI_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15272;"	d
+RG_TURISMO_TRX_TX_TSSI_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15271;"	d
+RG_TURISMO_TRX_TX_TSSI_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15273;"	d
+RG_TURISMO_TRX_TX_TSSI_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15275;"	d
+RG_TURISMO_TRX_TX_TSSI_DIV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15279;"	d
+RG_TURISMO_TRX_TX_TSSI_DIV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15277;"	d
+RG_TURISMO_TRX_TX_TSSI_DIV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15276;"	d
+RG_TURISMO_TRX_TX_TSSI_DIV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15278;"	d
+RG_TURISMO_TRX_TX_TSSI_DIV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15280;"	d
+RG_TURISMO_TRX_TX_TSSI_TESTMODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15289;"	d
+RG_TURISMO_TRX_TX_TSSI_TESTMODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15287;"	d
+RG_TURISMO_TRX_TX_TSSI_TESTMODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15286;"	d
+RG_TURISMO_TRX_TX_TSSI_TESTMODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15288;"	d
+RG_TURISMO_TRX_TX_TSSI_TESTMODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15290;"	d
+RG_TURISMO_TRX_TX_TSSI_TEST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15284;"	d
+RG_TURISMO_TRX_TX_TSSI_TEST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15282;"	d
+RG_TURISMO_TRX_TX_TSSI_TEST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15281;"	d
+RG_TURISMO_TRX_TX_TSSI_TEST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15283;"	d
+RG_TURISMO_TRX_TX_TSSI_TEST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15285;"	d
+RG_TURISMO_TRX_TX_UP8X_MAN_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20279;"	d
+RG_TURISMO_TRX_TX_UP8X_MAN_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20277;"	d
+RG_TURISMO_TRX_TX_UP8X_MAN_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20276;"	d
+RG_TURISMO_TRX_TX_UP8X_MAN_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20278;"	d
+RG_TURISMO_TRX_TX_UP8X_MAN_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20280;"	d
+RG_TURISMO_TRX_TX_VTOI_CURRENT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15459;"	d
+RG_TURISMO_TRX_TX_VTOI_CURRENT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15457;"	d
+RG_TURISMO_TRX_TX_VTOI_CURRENT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15456;"	d
+RG_TURISMO_TRX_TX_VTOI_CURRENT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15458;"	d
+RG_TURISMO_TRX_TX_VTOI_CURRENT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15460;"	d
+RG_TURISMO_TRX_TX_VTOI_FS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15474;"	d
+RG_TURISMO_TRX_TX_VTOI_FS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15472;"	d
+RG_TURISMO_TRX_TX_VTOI_FS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15471;"	d
+RG_TURISMO_TRX_TX_VTOI_FS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15473;"	d
+RG_TURISMO_TRX_TX_VTOI_FS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15475;"	d
+RG_TURISMO_TRX_TX_VTOI_GM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15464;"	d
+RG_TURISMO_TRX_TX_VTOI_GM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15462;"	d
+RG_TURISMO_TRX_TX_VTOI_GM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15461;"	d
+RG_TURISMO_TRX_TX_VTOI_GM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15463;"	d
+RG_TURISMO_TRX_TX_VTOI_GM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15465;"	d
+RG_TURISMO_TRX_TX_VTOI_OPTION_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15469;"	d
+RG_TURISMO_TRX_TX_VTOI_OPTION_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15467;"	d
+RG_TURISMO_TRX_TX_VTOI_OPTION_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15466;"	d
+RG_TURISMO_TRX_TX_VTOI_OPTION_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15468;"	d
+RG_TURISMO_TRX_TX_VTOI_OPTION_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15470;"	d
+RG_TURISMO_TRX_VO5GB_AAC_IMAX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19314;"	d
+RG_TURISMO_TRX_VO5GB_AAC_IMAX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19312;"	d
+RG_TURISMO_TRX_VO5GB_AAC_IMAX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19311;"	d
+RG_TURISMO_TRX_VO5GB_AAC_IMAX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19313;"	d
+RG_TURISMO_TRX_VO5GB_AAC_IMAX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19315;"	d
+RG_TURISMO_TRX_VO5GB_AAC_IOST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	19309;"	d
+RG_TURISMO_TRX_VO5GB_AAC_IOST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19307;"	d
+RG_TURISMO_TRX_VO5GB_AAC_IOST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	19306;"	d
+RG_TURISMO_TRX_VO5GB_AAC_IOST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	19308;"	d
+RG_TURISMO_TRX_VO5GB_AAC_IOST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	19310;"	d
+RG_TURISMO_TRX_VOBF_CAPIMB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16669;"	d
+RG_TURISMO_TRX_VOBF_CAPIMB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16667;"	d
+RG_TURISMO_TRX_VOBF_CAPIMB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16666;"	d
+RG_TURISMO_TRX_VOBF_CAPIMB_POL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16664;"	d
+RG_TURISMO_TRX_VOBF_CAPIMB_POL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16662;"	d
+RG_TURISMO_TRX_VOBF_CAPIMB_POL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16661;"	d
+RG_TURISMO_TRX_VOBF_CAPIMB_POL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16663;"	d
+RG_TURISMO_TRX_VOBF_CAPIMB_POL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16665;"	d
+RG_TURISMO_TRX_VOBF_CAPIMB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16668;"	d
+RG_TURISMO_TRX_VOBF_CAPIMB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16670;"	d
+RG_TURISMO_TRX_VOBF_DIVBFSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16649;"	d
+RG_TURISMO_TRX_VOBF_DIVBFSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16647;"	d
+RG_TURISMO_TRX_VOBF_DIVBFSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16646;"	d
+RG_TURISMO_TRX_VOBF_DIVBFSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16648;"	d
+RG_TURISMO_TRX_VOBF_DIVBFSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16650;"	d
+RG_TURISMO_TRX_VOBF_RXMBSEL_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16619;"	d
+RG_TURISMO_TRX_VOBF_RXMBSEL_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16617;"	d
+RG_TURISMO_TRX_VOBF_RXMBSEL_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16616;"	d
+RG_TURISMO_TRX_VOBF_RXMBSEL_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16618;"	d
+RG_TURISMO_TRX_VOBF_RXMBSEL_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16620;"	d
+RG_TURISMO_TRX_VOBF_RXMBSEL_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16639;"	d
+RG_TURISMO_TRX_VOBF_RXMBSEL_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16637;"	d
+RG_TURISMO_TRX_VOBF_RXMBSEL_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16636;"	d
+RG_TURISMO_TRX_VOBF_RXMBSEL_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16638;"	d
+RG_TURISMO_TRX_VOBF_RXMBSEL_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16640;"	d
+RG_TURISMO_TRX_VOBF_RXOBSEL_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16624;"	d
+RG_TURISMO_TRX_VOBF_RXOBSEL_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16622;"	d
+RG_TURISMO_TRX_VOBF_RXOBSEL_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16621;"	d
+RG_TURISMO_TRX_VOBF_RXOBSEL_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16623;"	d
+RG_TURISMO_TRX_VOBF_RXOBSEL_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16625;"	d
+RG_TURISMO_TRX_VOBF_RXOBSEL_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16644;"	d
+RG_TURISMO_TRX_VOBF_RXOBSEL_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16642;"	d
+RG_TURISMO_TRX_VOBF_RXOBSEL_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16641;"	d
+RG_TURISMO_TRX_VOBF_RXOBSEL_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16643;"	d
+RG_TURISMO_TRX_VOBF_RXOBSEL_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16645;"	d
+RG_TURISMO_TRX_VOBF_TXMBSEL_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16609;"	d
+RG_TURISMO_TRX_VOBF_TXMBSEL_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16607;"	d
+RG_TURISMO_TRX_VOBF_TXMBSEL_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16606;"	d
+RG_TURISMO_TRX_VOBF_TXMBSEL_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16608;"	d
+RG_TURISMO_TRX_VOBF_TXMBSEL_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16610;"	d
+RG_TURISMO_TRX_VOBF_TXMBSEL_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16629;"	d
+RG_TURISMO_TRX_VOBF_TXMBSEL_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16627;"	d
+RG_TURISMO_TRX_VOBF_TXMBSEL_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16626;"	d
+RG_TURISMO_TRX_VOBF_TXMBSEL_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16628;"	d
+RG_TURISMO_TRX_VOBF_TXMBSEL_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16630;"	d
+RG_TURISMO_TRX_VOBF_TXOBSEL_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16614;"	d
+RG_TURISMO_TRX_VOBF_TXOBSEL_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16612;"	d
+RG_TURISMO_TRX_VOBF_TXOBSEL_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16611;"	d
+RG_TURISMO_TRX_VOBF_TXOBSEL_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16613;"	d
+RG_TURISMO_TRX_VOBF_TXOBSEL_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16615;"	d
+RG_TURISMO_TRX_VOBF_TXOBSEL_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16634;"	d
+RG_TURISMO_TRX_VOBF_TXOBSEL_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16632;"	d
+RG_TURISMO_TRX_VOBF_TXOBSEL_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16631;"	d
+RG_TURISMO_TRX_VOBF_TXOBSEL_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16633;"	d
+RG_TURISMO_TRX_VOBF_TXOBSEL_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16635;"	d
+RG_TURISMO_TRX_VO_AAC_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16804;"	d
+RG_TURISMO_TRX_VO_AAC_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16802;"	d
+RG_TURISMO_TRX_VO_AAC_EN_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16799;"	d
+RG_TURISMO_TRX_VO_AAC_EN_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16797;"	d
+RG_TURISMO_TRX_VO_AAC_EN_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16796;"	d
+RG_TURISMO_TRX_VO_AAC_EN_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16798;"	d
+RG_TURISMO_TRX_VO_AAC_EN_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16800;"	d
+RG_TURISMO_TRX_VO_AAC_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16801;"	d
+RG_TURISMO_TRX_VO_AAC_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16803;"	d
+RG_TURISMO_TRX_VO_AAC_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16805;"	d
+RG_TURISMO_TRX_VO_AAC_EVA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16814;"	d
+RG_TURISMO_TRX_VO_AAC_EVA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16812;"	d
+RG_TURISMO_TRX_VO_AAC_EVA_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16809;"	d
+RG_TURISMO_TRX_VO_AAC_EVA_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16807;"	d
+RG_TURISMO_TRX_VO_AAC_EVA_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16806;"	d
+RG_TURISMO_TRX_VO_AAC_EVA_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16808;"	d
+RG_TURISMO_TRX_VO_AAC_EVA_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16810;"	d
+RG_TURISMO_TRX_VO_AAC_EVA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16811;"	d
+RG_TURISMO_TRX_VO_AAC_EVA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16813;"	d
+RG_TURISMO_TRX_VO_AAC_EVA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16815;"	d
+RG_TURISMO_TRX_VO_AAC_EVA_TS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16794;"	d
+RG_TURISMO_TRX_VO_AAC_EVA_TS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16792;"	d
+RG_TURISMO_TRX_VO_AAC_EVA_TS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16791;"	d
+RG_TURISMO_TRX_VO_AAC_EVA_TS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16793;"	d
+RG_TURISMO_TRX_VO_AAC_EVA_TS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16795;"	d
+RG_TURISMO_TRX_VO_AAC_IMAX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16784;"	d
+RG_TURISMO_TRX_VO_AAC_IMAX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16782;"	d
+RG_TURISMO_TRX_VO_AAC_IMAX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16781;"	d
+RG_TURISMO_TRX_VO_AAC_IMAX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16783;"	d
+RG_TURISMO_TRX_VO_AAC_IMAX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16785;"	d
+RG_TURISMO_TRX_VO_AAC_INIT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16789;"	d
+RG_TURISMO_TRX_VO_AAC_INIT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16787;"	d
+RG_TURISMO_TRX_VO_AAC_INIT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16786;"	d
+RG_TURISMO_TRX_VO_AAC_INIT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16788;"	d
+RG_TURISMO_TRX_VO_AAC_INIT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16790;"	d
+RG_TURISMO_TRX_VO_AAC_IOST_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16769;"	d
+RG_TURISMO_TRX_VO_AAC_IOST_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16767;"	d
+RG_TURISMO_TRX_VO_AAC_IOST_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16766;"	d
+RG_TURISMO_TRX_VO_AAC_IOST_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16768;"	d
+RG_TURISMO_TRX_VO_AAC_IOST_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16770;"	d
+RG_TURISMO_TRX_VO_AAC_IOST_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16779;"	d
+RG_TURISMO_TRX_VO_AAC_IOST_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16777;"	d
+RG_TURISMO_TRX_VO_AAC_IOST_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16776;"	d
+RG_TURISMO_TRX_VO_AAC_IOST_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16778;"	d
+RG_TURISMO_TRX_VO_AAC_IOST_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16780;"	d
+RG_TURISMO_TRX_VO_AAC_TAR_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16764;"	d
+RG_TURISMO_TRX_VO_AAC_TAR_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16762;"	d
+RG_TURISMO_TRX_VO_AAC_TAR_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16761;"	d
+RG_TURISMO_TRX_VO_AAC_TAR_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16763;"	d
+RG_TURISMO_TRX_VO_AAC_TAR_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16765;"	d
+RG_TURISMO_TRX_VO_AAC_TAR_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16774;"	d
+RG_TURISMO_TRX_VO_AAC_TAR_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16772;"	d
+RG_TURISMO_TRX_VO_AAC_TAR_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16771;"	d
+RG_TURISMO_TRX_VO_AAC_TAR_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16773;"	d
+RG_TURISMO_TRX_VO_AAC_TAR_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16775;"	d
+RG_TURISMO_TRX_VO_AAC_TEST_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16819;"	d
+RG_TURISMO_TRX_VO_AAC_TEST_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16817;"	d
+RG_TURISMO_TRX_VO_AAC_TEST_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16816;"	d
+RG_TURISMO_TRX_VO_AAC_TEST_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16818;"	d
+RG_TURISMO_TRX_VO_AAC_TEST_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16820;"	d
+RG_TURISMO_TRX_VO_AAC_TEST_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16824;"	d
+RG_TURISMO_TRX_VO_AAC_TEST_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16822;"	d
+RG_TURISMO_TRX_VO_AAC_TEST_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16821;"	d
+RG_TURISMO_TRX_VO_AAC_TEST_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16823;"	d
+RG_TURISMO_TRX_VO_AAC_TEST_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16825;"	d
+RG_TURISMO_TRX_WF_EN_TX_PA_VIN33_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15329;"	d
+RG_TURISMO_TRX_WF_EN_TX_PA_VIN33_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15327;"	d
+RG_TURISMO_TRX_WF_EN_TX_PA_VIN33_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15326;"	d
+RG_TURISMO_TRX_WF_EN_TX_PA_VIN33_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15328;"	d
+RG_TURISMO_TRX_WF_EN_TX_PA_VIN33_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15330;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17169;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17167;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17166;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17168;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17170;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG10_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17069;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG10_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17067;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG10_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17066;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG10_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17068;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG10_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17070;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG11_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17059;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG11_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17057;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG11_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17056;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG11_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17058;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG11_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17060;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG12_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17049;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG12_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17047;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG12_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17046;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG12_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17048;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG12_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17050;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG13_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17039;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG13_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17037;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG13_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17036;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG13_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17038;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG13_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17040;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG14_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17029;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG14_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17027;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG14_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17026;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG14_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17028;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG14_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17030;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG15_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17019;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG15_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17017;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG15_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17016;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG15_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17018;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG15_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17020;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17159;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17157;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17156;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17158;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17160;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17149;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17147;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17146;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17148;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17150;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17139;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17137;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17136;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17138;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17140;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17129;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17127;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17126;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17128;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17130;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17119;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17117;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17116;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17118;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17120;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17109;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17107;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17106;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17108;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17110;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17099;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17097;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17096;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17098;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17100;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG8_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17089;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG8_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17087;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG8_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17086;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG8_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17088;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG8_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17090;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG9_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17079;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG9_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17077;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG9_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17076;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG9_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17078;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG9_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17080;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17329;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17327;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17326;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17328;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17330;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG10_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17229;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG10_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17227;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG10_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17226;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG10_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17228;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG10_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17230;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG11_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17219;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG11_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17217;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG11_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17216;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG11_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17218;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG11_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17220;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG12_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17209;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG12_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17207;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG12_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17206;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG12_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17208;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG12_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17210;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG13_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17199;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG13_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17197;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG13_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17196;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG13_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17198;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG13_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17200;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG14_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17189;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG14_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17187;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG14_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17186;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG14_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17188;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG14_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17190;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG15_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17179;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG15_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17177;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG15_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17176;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG15_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17178;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG15_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17180;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17319;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17317;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17316;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17318;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17320;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17309;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17307;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17306;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17308;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17310;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17299;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17297;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17296;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17298;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17300;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17289;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17287;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17286;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17288;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17290;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17279;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17277;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17276;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17278;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17280;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17269;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17267;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17266;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17268;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17270;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17259;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17257;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17256;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17258;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17260;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG8_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17249;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG8_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17247;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG8_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17246;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG8_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17248;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG8_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17250;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG9_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17239;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG9_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17237;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG9_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17236;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG9_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17238;"	d
+RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG9_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17240;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17174;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17172;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17171;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17173;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17175;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG10_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17074;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG10_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17072;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG10_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17071;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG10_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17073;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG10_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17075;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG11_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17064;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG11_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17062;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG11_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17061;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG11_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17063;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG11_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17065;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG12_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17054;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG12_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17052;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG12_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17051;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG12_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17053;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG12_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17055;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG13_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17044;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG13_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17042;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG13_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17041;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG13_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17043;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG13_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17045;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG14_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17034;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG14_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17032;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG14_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17031;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG14_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17033;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG14_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17035;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG15_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17024;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG15_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17022;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG15_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17021;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG15_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17023;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG15_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17025;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17164;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17162;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17161;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17163;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17165;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17154;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17152;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17151;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17153;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17155;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17144;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17142;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17141;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17143;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17145;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17134;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17132;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17131;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17133;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17135;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17124;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17122;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17121;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17123;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17125;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17114;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17112;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17111;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17113;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17115;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17104;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17102;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17101;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17103;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17105;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG8_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17094;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG8_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17092;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG8_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17091;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG8_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17093;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG8_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17095;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG9_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17084;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG9_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17082;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG9_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17081;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG9_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17083;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG9_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17085;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17334;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17332;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17331;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17333;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17335;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG10_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17234;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG10_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17232;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG10_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17231;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG10_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17233;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG10_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17235;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG11_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17224;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG11_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17222;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG11_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17221;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG11_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17223;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG11_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17225;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG12_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17214;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG12_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17212;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG12_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17211;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG12_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17213;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG12_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17215;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG13_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17204;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG13_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17202;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG13_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17201;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG13_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17203;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG13_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17205;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG14_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17194;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG14_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17192;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG14_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17191;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG14_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17193;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG14_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17195;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG15_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17184;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG15_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17182;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG15_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17181;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG15_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17183;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG15_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17185;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17324;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17322;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17321;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17323;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17325;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17314;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17312;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17311;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17313;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17315;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17304;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17302;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17301;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17303;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17305;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17294;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17292;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17291;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17293;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17295;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17284;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17282;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17281;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17283;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17285;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17274;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17272;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17271;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17273;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17275;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17264;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17262;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17261;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17263;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17265;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG8_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17254;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG8_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17252;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG8_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17251;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG8_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17253;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG8_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17255;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG9_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17244;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG9_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17242;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG9_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17241;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG9_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17243;"	d
+RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG9_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17245;"	d
+RG_TURISMO_TRX_WF_N_RX_ABBCFIX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15134;"	d
+RG_TURISMO_TRX_WF_N_RX_ABBCFIX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15132;"	d
+RG_TURISMO_TRX_WF_N_RX_ABBCFIX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15131;"	d
+RG_TURISMO_TRX_WF_N_RX_ABBCFIX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15133;"	d
+RG_TURISMO_TRX_WF_N_RX_ABBCFIX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15135;"	d
+RG_TURISMO_TRX_WF_N_RX_ABBCTUNE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15109;"	d
+RG_TURISMO_TRX_WF_N_RX_ABBCTUNE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15107;"	d
+RG_TURISMO_TRX_WF_N_RX_ABBCTUNE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15106;"	d
+RG_TURISMO_TRX_WF_N_RX_ABBCTUNE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15108;"	d
+RG_TURISMO_TRX_WF_N_RX_ABBCTUNE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15110;"	d
+RG_TURISMO_TRX_WF_N_RX_ABB_BT_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15144;"	d
+RG_TURISMO_TRX_WF_N_RX_ABB_BT_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15142;"	d
+RG_TURISMO_TRX_WF_N_RX_ABB_BT_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15141;"	d
+RG_TURISMO_TRX_WF_N_RX_ABB_BT_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15143;"	d
+RG_TURISMO_TRX_WF_N_RX_ABB_BT_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15145;"	d
+RG_TURISMO_TRX_WF_N_RX_ABB_IDIV3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15149;"	d
+RG_TURISMO_TRX_WF_N_RX_ABB_IDIV3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15147;"	d
+RG_TURISMO_TRX_WF_N_RX_ABB_IDIV3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15146;"	d
+RG_TURISMO_TRX_WF_N_RX_ABB_IDIV3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15148;"	d
+RG_TURISMO_TRX_WF_N_RX_ABB_IDIV3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15150;"	d
+RG_TURISMO_TRX_WF_N_RX_ABB_N_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15139;"	d
+RG_TURISMO_TRX_WF_N_RX_ABB_N_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15137;"	d
+RG_TURISMO_TRX_WF_N_RX_ABB_N_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15136;"	d
+RG_TURISMO_TRX_WF_N_RX_ABB_N_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15138;"	d
+RG_TURISMO_TRX_WF_N_RX_ABB_N_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15140;"	d
+RG_TURISMO_TRX_WF_N_RX_EN_IDACA_COARSE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15154;"	d
+RG_TURISMO_TRX_WF_N_RX_EN_IDACA_COARSE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15152;"	d
+RG_TURISMO_TRX_WF_N_RX_EN_IDACA_COARSE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15151;"	d
+RG_TURISMO_TRX_WF_N_RX_EN_IDACA_COARSE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15153;"	d
+RG_TURISMO_TRX_WF_N_RX_EN_IDACA_COARSE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15155;"	d
+RG_TURISMO_TRX_WF_N_RX_EN_LOOPA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15159;"	d
+RG_TURISMO_TRX_WF_N_RX_EN_LOOPA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15157;"	d
+RG_TURISMO_TRX_WF_N_RX_EN_LOOPA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15156;"	d
+RG_TURISMO_TRX_WF_N_RX_EN_LOOPA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15158;"	d
+RG_TURISMO_TRX_WF_N_RX_EN_LOOPA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15160;"	d
+RG_TURISMO_TRX_WF_N_RX_FILTERI1ST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15119;"	d
+RG_TURISMO_TRX_WF_N_RX_FILTERI1ST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15117;"	d
+RG_TURISMO_TRX_WF_N_RX_FILTERI1ST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15116;"	d
+RG_TURISMO_TRX_WF_N_RX_FILTERI1ST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15118;"	d
+RG_TURISMO_TRX_WF_N_RX_FILTERI1ST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15120;"	d
+RG_TURISMO_TRX_WF_N_RX_FILTERI2ND_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15124;"	d
+RG_TURISMO_TRX_WF_N_RX_FILTERI2ND_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15122;"	d
+RG_TURISMO_TRX_WF_N_RX_FILTERI2ND_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15121;"	d
+RG_TURISMO_TRX_WF_N_RX_FILTERI2ND_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15123;"	d
+RG_TURISMO_TRX_WF_N_RX_FILTERI2ND_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15125;"	d
+RG_TURISMO_TRX_WF_N_RX_FILTERI3RD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15129;"	d
+RG_TURISMO_TRX_WF_N_RX_FILTERI3RD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15127;"	d
+RG_TURISMO_TRX_WF_N_RX_FILTERI3RD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15126;"	d
+RG_TURISMO_TRX_WF_N_RX_FILTERI3RD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15128;"	d
+RG_TURISMO_TRX_WF_N_RX_FILTERI3RD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15130;"	d
+RG_TURISMO_TRX_WF_N_RX_FILTERI_COARSE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15114;"	d
+RG_TURISMO_TRX_WF_N_RX_FILTERI_COARSE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15112;"	d
+RG_TURISMO_TRX_WF_N_RX_FILTERI_COARSE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15111;"	d
+RG_TURISMO_TRX_WF_N_RX_FILTERI_COARSE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15113;"	d
+RG_TURISMO_TRX_WF_N_RX_FILTERI_COARSE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15115;"	d
+RG_TURISMO_TRX_WF_N_RX_FILTERVCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15164;"	d
+RG_TURISMO_TRX_WF_N_RX_FILTERVCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15162;"	d
+RG_TURISMO_TRX_WF_N_RX_FILTERVCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15161;"	d
+RG_TURISMO_TRX_WF_N_RX_FILTERVCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15163;"	d
+RG_TURISMO_TRX_WF_N_RX_FILTERVCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15165;"	d
+RG_TURISMO_TRX_WF_N_RX_OUTVCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15169;"	d
+RG_TURISMO_TRX_WF_N_RX_OUTVCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15167;"	d
+RG_TURISMO_TRX_WF_N_RX_OUTVCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15166;"	d
+RG_TURISMO_TRX_WF_N_RX_OUTVCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15168;"	d
+RG_TURISMO_TRX_WF_N_RX_OUTVCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15170;"	d
+RG_TURISMO_TRX_WF_PABIAS_CTRL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15389;"	d
+RG_TURISMO_TRX_WF_PABIAS_CTRL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15387;"	d
+RG_TURISMO_TRX_WF_PABIAS_CTRL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15386;"	d
+RG_TURISMO_TRX_WF_PABIAS_CTRL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15388;"	d
+RG_TURISMO_TRX_WF_PABIAS_CTRL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15390;"	d
+RG_TURISMO_TRX_WF_PACELL_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15384;"	d
+RG_TURISMO_TRX_WF_PACELL_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15382;"	d
+RG_TURISMO_TRX_WF_PACELL_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15381;"	d
+RG_TURISMO_TRX_WF_PACELL_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15383;"	d
+RG_TURISMO_TRX_WF_PACELL_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15385;"	d
+RG_TURISMO_TRX_WF_RX_ABBCFIX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15069;"	d
+RG_TURISMO_TRX_WF_RX_ABBCFIX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15067;"	d
+RG_TURISMO_TRX_WF_RX_ABBCFIX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15066;"	d
+RG_TURISMO_TRX_WF_RX_ABBCFIX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15068;"	d
+RG_TURISMO_TRX_WF_RX_ABBCFIX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15070;"	d
+RG_TURISMO_TRX_WF_RX_ABBCTUNE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15044;"	d
+RG_TURISMO_TRX_WF_RX_ABBCTUNE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15042;"	d
+RG_TURISMO_TRX_WF_RX_ABBCTUNE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15041;"	d
+RG_TURISMO_TRX_WF_RX_ABBCTUNE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15043;"	d
+RG_TURISMO_TRX_WF_RX_ABBCTUNE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15045;"	d
+RG_TURISMO_TRX_WF_RX_ABB_BT_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15079;"	d
+RG_TURISMO_TRX_WF_RX_ABB_BT_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15077;"	d
+RG_TURISMO_TRX_WF_RX_ABB_BT_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15076;"	d
+RG_TURISMO_TRX_WF_RX_ABB_BT_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15078;"	d
+RG_TURISMO_TRX_WF_RX_ABB_BT_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15080;"	d
+RG_TURISMO_TRX_WF_RX_ABB_IDIV3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15084;"	d
+RG_TURISMO_TRX_WF_RX_ABB_IDIV3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15082;"	d
+RG_TURISMO_TRX_WF_RX_ABB_IDIV3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15081;"	d
+RG_TURISMO_TRX_WF_RX_ABB_IDIV3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15083;"	d
+RG_TURISMO_TRX_WF_RX_ABB_IDIV3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15085;"	d
+RG_TURISMO_TRX_WF_RX_ABB_N_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15074;"	d
+RG_TURISMO_TRX_WF_RX_ABB_N_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15072;"	d
+RG_TURISMO_TRX_WF_RX_ABB_N_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15071;"	d
+RG_TURISMO_TRX_WF_RX_ABB_N_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15073;"	d
+RG_TURISMO_TRX_WF_RX_ABB_N_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15075;"	d
+RG_TURISMO_TRX_WF_RX_ADC_CLOAD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15954;"	d
+RG_TURISMO_TRX_WF_RX_ADC_CLOAD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15952;"	d
+RG_TURISMO_TRX_WF_RX_ADC_CLOAD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15951;"	d
+RG_TURISMO_TRX_WF_RX_ADC_CLOAD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15953;"	d
+RG_TURISMO_TRX_WF_RX_ADC_CLOAD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15955;"	d
+RG_TURISMO_TRX_WF_RX_ADC_ICMP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15944;"	d
+RG_TURISMO_TRX_WF_RX_ADC_ICMP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15942;"	d
+RG_TURISMO_TRX_WF_RX_ADC_ICMP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15941;"	d
+RG_TURISMO_TRX_WF_RX_ADC_ICMP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15943;"	d
+RG_TURISMO_TRX_WF_RX_ADC_ICMP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15945;"	d
+RG_TURISMO_TRX_WF_RX_ADC_VCMI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15949;"	d
+RG_TURISMO_TRX_WF_RX_ADC_VCMI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15947;"	d
+RG_TURISMO_TRX_WF_RX_ADC_VCMI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15946;"	d
+RG_TURISMO_TRX_WF_RX_ADC_VCMI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15948;"	d
+RG_TURISMO_TRX_WF_RX_ADC_VCMI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15950;"	d
+RG_TURISMO_TRX_WF_RX_DCCAL_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17829;"	d
+RG_TURISMO_TRX_WF_RX_DCCAL_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17827;"	d
+RG_TURISMO_TRX_WF_RX_DCCAL_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17826;"	d
+RG_TURISMO_TRX_WF_RX_DCCAL_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17828;"	d
+RG_TURISMO_TRX_WF_RX_DCCAL_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17830;"	d
+RG_TURISMO_TRX_WF_RX_EN_IDACA_COARSE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15089;"	d
+RG_TURISMO_TRX_WF_RX_EN_IDACA_COARSE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15087;"	d
+RG_TURISMO_TRX_WF_RX_EN_IDACA_COARSE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15086;"	d
+RG_TURISMO_TRX_WF_RX_EN_IDACA_COARSE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15088;"	d
+RG_TURISMO_TRX_WF_RX_EN_IDACA_COARSE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15090;"	d
+RG_TURISMO_TRX_WF_RX_EN_LOOPA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15094;"	d
+RG_TURISMO_TRX_WF_RX_EN_LOOPA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15092;"	d
+RG_TURISMO_TRX_WF_RX_EN_LOOPA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15091;"	d
+RG_TURISMO_TRX_WF_RX_EN_LOOPA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15093;"	d
+RG_TURISMO_TRX_WF_RX_EN_LOOPA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15095;"	d
+RG_TURISMO_TRX_WF_RX_FILTERI1ST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15054;"	d
+RG_TURISMO_TRX_WF_RX_FILTERI1ST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15052;"	d
+RG_TURISMO_TRX_WF_RX_FILTERI1ST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15051;"	d
+RG_TURISMO_TRX_WF_RX_FILTERI1ST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15053;"	d
+RG_TURISMO_TRX_WF_RX_FILTERI1ST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15055;"	d
+RG_TURISMO_TRX_WF_RX_FILTERI2ND_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15059;"	d
+RG_TURISMO_TRX_WF_RX_FILTERI2ND_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15057;"	d
+RG_TURISMO_TRX_WF_RX_FILTERI2ND_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15056;"	d
+RG_TURISMO_TRX_WF_RX_FILTERI2ND_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15058;"	d
+RG_TURISMO_TRX_WF_RX_FILTERI2ND_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15060;"	d
+RG_TURISMO_TRX_WF_RX_FILTERI3RD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15064;"	d
+RG_TURISMO_TRX_WF_RX_FILTERI3RD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15062;"	d
+RG_TURISMO_TRX_WF_RX_FILTERI3RD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15061;"	d
+RG_TURISMO_TRX_WF_RX_FILTERI3RD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15063;"	d
+RG_TURISMO_TRX_WF_RX_FILTERI3RD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15065;"	d
+RG_TURISMO_TRX_WF_RX_FILTERI_COARSE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15049;"	d
+RG_TURISMO_TRX_WF_RX_FILTERI_COARSE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15047;"	d
+RG_TURISMO_TRX_WF_RX_FILTERI_COARSE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15046;"	d
+RG_TURISMO_TRX_WF_RX_FILTERI_COARSE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15048;"	d
+RG_TURISMO_TRX_WF_RX_FILTERI_COARSE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15050;"	d
+RG_TURISMO_TRX_WF_RX_FILTERVCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15099;"	d
+RG_TURISMO_TRX_WF_RX_FILTERVCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15097;"	d
+RG_TURISMO_TRX_WF_RX_FILTERVCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15096;"	d
+RG_TURISMO_TRX_WF_RX_FILTERVCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15098;"	d
+RG_TURISMO_TRX_WF_RX_FILTERVCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15100;"	d
+RG_TURISMO_TRX_WF_RX_HG_DIV2_CORE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15514;"	d
+RG_TURISMO_TRX_WF_RX_HG_DIV2_CORE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15512;"	d
+RG_TURISMO_TRX_WF_RX_HG_DIV2_CORE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15511;"	d
+RG_TURISMO_TRX_WF_RX_HG_DIV2_CORE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15513;"	d
+RG_TURISMO_TRX_WF_RX_HG_DIV2_CORE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15515;"	d
+RG_TURISMO_TRX_WF_RX_HG_LNAHGN_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15489;"	d
+RG_TURISMO_TRX_WF_RX_HG_LNAHGN_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15487;"	d
+RG_TURISMO_TRX_WF_RX_HG_LNAHGN_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15486;"	d
+RG_TURISMO_TRX_WF_RX_HG_LNAHGN_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15488;"	d
+RG_TURISMO_TRX_WF_RX_HG_LNAHGN_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15490;"	d
+RG_TURISMO_TRX_WF_RX_HG_LNAHGP_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15494;"	d
+RG_TURISMO_TRX_WF_RX_HG_LNAHGP_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15492;"	d
+RG_TURISMO_TRX_WF_RX_HG_LNAHGP_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15491;"	d
+RG_TURISMO_TRX_WF_RX_HG_LNAHGP_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15493;"	d
+RG_TURISMO_TRX_WF_RX_HG_LNAHGP_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15495;"	d
+RG_TURISMO_TRX_WF_RX_HG_LNALG_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15499;"	d
+RG_TURISMO_TRX_WF_RX_HG_LNALG_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15497;"	d
+RG_TURISMO_TRX_WF_RX_HG_LNALG_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15496;"	d
+RG_TURISMO_TRX_WF_RX_HG_LNALG_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15498;"	d
+RG_TURISMO_TRX_WF_RX_HG_LNALG_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15500;"	d
+RG_TURISMO_TRX_WF_RX_HG_LNA_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15479;"	d
+RG_TURISMO_TRX_WF_RX_HG_LNA_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15477;"	d
+RG_TURISMO_TRX_WF_RX_HG_LNA_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15476;"	d
+RG_TURISMO_TRX_WF_RX_HG_LNA_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15478;"	d
+RG_TURISMO_TRX_WF_RX_HG_LNA_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15480;"	d
+RG_TURISMO_TRX_WF_RX_HG_LOBUF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15519;"	d
+RG_TURISMO_TRX_WF_RX_HG_LOBUF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15517;"	d
+RG_TURISMO_TRX_WF_RX_HG_LOBUF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15516;"	d
+RG_TURISMO_TRX_WF_RX_HG_LOBUF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15518;"	d
+RG_TURISMO_TRX_WF_RX_HG_LOBUF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15520;"	d
+RG_TURISMO_TRX_WF_RX_HG_TZI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15524;"	d
+RG_TURISMO_TRX_WF_RX_HG_TZI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15522;"	d
+RG_TURISMO_TRX_WF_RX_HG_TZI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15521;"	d
+RG_TURISMO_TRX_WF_RX_HG_TZI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15523;"	d
+RG_TURISMO_TRX_WF_RX_HG_TZI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15525;"	d
+RG_TURISMO_TRX_WF_RX_HG_TZ_CAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15504;"	d
+RG_TURISMO_TRX_WF_RX_HG_TZ_CAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15502;"	d
+RG_TURISMO_TRX_WF_RX_HG_TZ_CAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15501;"	d
+RG_TURISMO_TRX_WF_RX_HG_TZ_CAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15503;"	d
+RG_TURISMO_TRX_WF_RX_HG_TZ_CAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15505;"	d
+RG_TURISMO_TRX_WF_RX_HG_TZ_GC_BOOST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15509;"	d
+RG_TURISMO_TRX_WF_RX_HG_TZ_GC_BOOST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15507;"	d
+RG_TURISMO_TRX_WF_RX_HG_TZ_GC_BOOST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15506;"	d
+RG_TURISMO_TRX_WF_RX_HG_TZ_GC_BOOST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15508;"	d
+RG_TURISMO_TRX_WF_RX_HG_TZ_GC_BOOST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15510;"	d
+RG_TURISMO_TRX_WF_RX_HG_TZ_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15484;"	d
+RG_TURISMO_TRX_WF_RX_HG_TZ_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15482;"	d
+RG_TURISMO_TRX_WF_RX_HG_TZ_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15481;"	d
+RG_TURISMO_TRX_WF_RX_HG_TZ_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15483;"	d
+RG_TURISMO_TRX_WF_RX_HG_TZ_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15485;"	d
+RG_TURISMO_TRX_WF_RX_HG_TZ_VCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15529;"	d
+RG_TURISMO_TRX_WF_RX_HG_TZ_VCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15527;"	d
+RG_TURISMO_TRX_WF_RX_HG_TZ_VCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15526;"	d
+RG_TURISMO_TRX_WF_RX_HG_TZ_VCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15528;"	d
+RG_TURISMO_TRX_WF_RX_HG_TZ_VCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15530;"	d
+RG_TURISMO_TRX_WF_RX_LG_DIV2_CORE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15624;"	d
+RG_TURISMO_TRX_WF_RX_LG_DIV2_CORE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15622;"	d
+RG_TURISMO_TRX_WF_RX_LG_DIV2_CORE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15621;"	d
+RG_TURISMO_TRX_WF_RX_LG_DIV2_CORE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15623;"	d
+RG_TURISMO_TRX_WF_RX_LG_DIV2_CORE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15625;"	d
+RG_TURISMO_TRX_WF_RX_LG_LNAHGN_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15599;"	d
+RG_TURISMO_TRX_WF_RX_LG_LNAHGN_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15597;"	d
+RG_TURISMO_TRX_WF_RX_LG_LNAHGN_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15596;"	d
+RG_TURISMO_TRX_WF_RX_LG_LNAHGN_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15598;"	d
+RG_TURISMO_TRX_WF_RX_LG_LNAHGN_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15600;"	d
+RG_TURISMO_TRX_WF_RX_LG_LNAHGP_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15604;"	d
+RG_TURISMO_TRX_WF_RX_LG_LNAHGP_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15602;"	d
+RG_TURISMO_TRX_WF_RX_LG_LNAHGP_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15601;"	d
+RG_TURISMO_TRX_WF_RX_LG_LNAHGP_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15603;"	d
+RG_TURISMO_TRX_WF_RX_LG_LNAHGP_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15605;"	d
+RG_TURISMO_TRX_WF_RX_LG_LNALG_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15609;"	d
+RG_TURISMO_TRX_WF_RX_LG_LNALG_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15607;"	d
+RG_TURISMO_TRX_WF_RX_LG_LNALG_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15606;"	d
+RG_TURISMO_TRX_WF_RX_LG_LNALG_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15608;"	d
+RG_TURISMO_TRX_WF_RX_LG_LNALG_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15610;"	d
+RG_TURISMO_TRX_WF_RX_LG_LNA_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15589;"	d
+RG_TURISMO_TRX_WF_RX_LG_LNA_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15587;"	d
+RG_TURISMO_TRX_WF_RX_LG_LNA_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15586;"	d
+RG_TURISMO_TRX_WF_RX_LG_LNA_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15588;"	d
+RG_TURISMO_TRX_WF_RX_LG_LNA_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15590;"	d
+RG_TURISMO_TRX_WF_RX_LG_LOBUF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15629;"	d
+RG_TURISMO_TRX_WF_RX_LG_LOBUF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15627;"	d
+RG_TURISMO_TRX_WF_RX_LG_LOBUF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15626;"	d
+RG_TURISMO_TRX_WF_RX_LG_LOBUF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15628;"	d
+RG_TURISMO_TRX_WF_RX_LG_LOBUF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15630;"	d
+RG_TURISMO_TRX_WF_RX_LG_TZI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15634;"	d
+RG_TURISMO_TRX_WF_RX_LG_TZI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15632;"	d
+RG_TURISMO_TRX_WF_RX_LG_TZI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15631;"	d
+RG_TURISMO_TRX_WF_RX_LG_TZI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15633;"	d
+RG_TURISMO_TRX_WF_RX_LG_TZI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15635;"	d
+RG_TURISMO_TRX_WF_RX_LG_TZ_CAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15614;"	d
+RG_TURISMO_TRX_WF_RX_LG_TZ_CAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15612;"	d
+RG_TURISMO_TRX_WF_RX_LG_TZ_CAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15611;"	d
+RG_TURISMO_TRX_WF_RX_LG_TZ_CAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15613;"	d
+RG_TURISMO_TRX_WF_RX_LG_TZ_CAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15615;"	d
+RG_TURISMO_TRX_WF_RX_LG_TZ_GC_BOOST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15619;"	d
+RG_TURISMO_TRX_WF_RX_LG_TZ_GC_BOOST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15617;"	d
+RG_TURISMO_TRX_WF_RX_LG_TZ_GC_BOOST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15616;"	d
+RG_TURISMO_TRX_WF_RX_LG_TZ_GC_BOOST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15618;"	d
+RG_TURISMO_TRX_WF_RX_LG_TZ_GC_BOOST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15620;"	d
+RG_TURISMO_TRX_WF_RX_LG_TZ_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15594;"	d
+RG_TURISMO_TRX_WF_RX_LG_TZ_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15592;"	d
+RG_TURISMO_TRX_WF_RX_LG_TZ_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15591;"	d
+RG_TURISMO_TRX_WF_RX_LG_TZ_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15593;"	d
+RG_TURISMO_TRX_WF_RX_LG_TZ_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15595;"	d
+RG_TURISMO_TRX_WF_RX_LG_TZ_VCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15639;"	d
+RG_TURISMO_TRX_WF_RX_LG_TZ_VCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15637;"	d
+RG_TURISMO_TRX_WF_RX_LG_TZ_VCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15636;"	d
+RG_TURISMO_TRX_WF_RX_LG_TZ_VCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15638;"	d
+RG_TURISMO_TRX_WF_RX_LG_TZ_VCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15640;"	d
+RG_TURISMO_TRX_WF_RX_MG_DIV2_CORE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15569;"	d
+RG_TURISMO_TRX_WF_RX_MG_DIV2_CORE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15567;"	d
+RG_TURISMO_TRX_WF_RX_MG_DIV2_CORE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15566;"	d
+RG_TURISMO_TRX_WF_RX_MG_DIV2_CORE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15568;"	d
+RG_TURISMO_TRX_WF_RX_MG_DIV2_CORE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15570;"	d
+RG_TURISMO_TRX_WF_RX_MG_LNAHGN_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15544;"	d
+RG_TURISMO_TRX_WF_RX_MG_LNAHGN_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15542;"	d
+RG_TURISMO_TRX_WF_RX_MG_LNAHGN_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15541;"	d
+RG_TURISMO_TRX_WF_RX_MG_LNAHGN_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15543;"	d
+RG_TURISMO_TRX_WF_RX_MG_LNAHGN_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15545;"	d
+RG_TURISMO_TRX_WF_RX_MG_LNAHGP_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15549;"	d
+RG_TURISMO_TRX_WF_RX_MG_LNAHGP_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15547;"	d
+RG_TURISMO_TRX_WF_RX_MG_LNAHGP_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15546;"	d
+RG_TURISMO_TRX_WF_RX_MG_LNAHGP_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15548;"	d
+RG_TURISMO_TRX_WF_RX_MG_LNAHGP_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15550;"	d
+RG_TURISMO_TRX_WF_RX_MG_LNALG_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15554;"	d
+RG_TURISMO_TRX_WF_RX_MG_LNALG_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15552;"	d
+RG_TURISMO_TRX_WF_RX_MG_LNALG_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15551;"	d
+RG_TURISMO_TRX_WF_RX_MG_LNALG_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15553;"	d
+RG_TURISMO_TRX_WF_RX_MG_LNALG_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15555;"	d
+RG_TURISMO_TRX_WF_RX_MG_LNA_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15534;"	d
+RG_TURISMO_TRX_WF_RX_MG_LNA_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15532;"	d
+RG_TURISMO_TRX_WF_RX_MG_LNA_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15531;"	d
+RG_TURISMO_TRX_WF_RX_MG_LNA_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15533;"	d
+RG_TURISMO_TRX_WF_RX_MG_LNA_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15535;"	d
+RG_TURISMO_TRX_WF_RX_MG_LOBUF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15574;"	d
+RG_TURISMO_TRX_WF_RX_MG_LOBUF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15572;"	d
+RG_TURISMO_TRX_WF_RX_MG_LOBUF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15571;"	d
+RG_TURISMO_TRX_WF_RX_MG_LOBUF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15573;"	d
+RG_TURISMO_TRX_WF_RX_MG_LOBUF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15575;"	d
+RG_TURISMO_TRX_WF_RX_MG_TZI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15579;"	d
+RG_TURISMO_TRX_WF_RX_MG_TZI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15577;"	d
+RG_TURISMO_TRX_WF_RX_MG_TZI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15576;"	d
+RG_TURISMO_TRX_WF_RX_MG_TZI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15578;"	d
+RG_TURISMO_TRX_WF_RX_MG_TZI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15580;"	d
+RG_TURISMO_TRX_WF_RX_MG_TZ_CAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15559;"	d
+RG_TURISMO_TRX_WF_RX_MG_TZ_CAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15557;"	d
+RG_TURISMO_TRX_WF_RX_MG_TZ_CAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15556;"	d
+RG_TURISMO_TRX_WF_RX_MG_TZ_CAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15558;"	d
+RG_TURISMO_TRX_WF_RX_MG_TZ_CAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15560;"	d
+RG_TURISMO_TRX_WF_RX_MG_TZ_GC_BOOST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15564;"	d
+RG_TURISMO_TRX_WF_RX_MG_TZ_GC_BOOST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15562;"	d
+RG_TURISMO_TRX_WF_RX_MG_TZ_GC_BOOST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15561;"	d
+RG_TURISMO_TRX_WF_RX_MG_TZ_GC_BOOST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15563;"	d
+RG_TURISMO_TRX_WF_RX_MG_TZ_GC_BOOST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15565;"	d
+RG_TURISMO_TRX_WF_RX_MG_TZ_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15539;"	d
+RG_TURISMO_TRX_WF_RX_MG_TZ_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15537;"	d
+RG_TURISMO_TRX_WF_RX_MG_TZ_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15536;"	d
+RG_TURISMO_TRX_WF_RX_MG_TZ_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15538;"	d
+RG_TURISMO_TRX_WF_RX_MG_TZ_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15540;"	d
+RG_TURISMO_TRX_WF_RX_MG_TZ_VCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15584;"	d
+RG_TURISMO_TRX_WF_RX_MG_TZ_VCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15582;"	d
+RG_TURISMO_TRX_WF_RX_MG_TZ_VCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15581;"	d
+RG_TURISMO_TRX_WF_RX_MG_TZ_VCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15583;"	d
+RG_TURISMO_TRX_WF_RX_MG_TZ_VCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15585;"	d
+RG_TURISMO_TRX_WF_RX_OUTVCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15104;"	d
+RG_TURISMO_TRX_WF_RX_OUTVCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15102;"	d
+RG_TURISMO_TRX_WF_RX_OUTVCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15101;"	d
+RG_TURISMO_TRX_WF_RX_OUTVCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15103;"	d
+RG_TURISMO_TRX_WF_RX_OUTVCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15105;"	d
+RG_TURISMO_TRX_WF_RX_ULG_DIV2_CORE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15679;"	d
+RG_TURISMO_TRX_WF_RX_ULG_DIV2_CORE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15677;"	d
+RG_TURISMO_TRX_WF_RX_ULG_DIV2_CORE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15676;"	d
+RG_TURISMO_TRX_WF_RX_ULG_DIV2_CORE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15678;"	d
+RG_TURISMO_TRX_WF_RX_ULG_DIV2_CORE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15680;"	d
+RG_TURISMO_TRX_WF_RX_ULG_LNAHGN_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15654;"	d
+RG_TURISMO_TRX_WF_RX_ULG_LNAHGN_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15652;"	d
+RG_TURISMO_TRX_WF_RX_ULG_LNAHGN_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15651;"	d
+RG_TURISMO_TRX_WF_RX_ULG_LNAHGN_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15653;"	d
+RG_TURISMO_TRX_WF_RX_ULG_LNAHGN_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15655;"	d
+RG_TURISMO_TRX_WF_RX_ULG_LNAHGP_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15659;"	d
+RG_TURISMO_TRX_WF_RX_ULG_LNAHGP_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15657;"	d
+RG_TURISMO_TRX_WF_RX_ULG_LNAHGP_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15656;"	d
+RG_TURISMO_TRX_WF_RX_ULG_LNAHGP_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15658;"	d
+RG_TURISMO_TRX_WF_RX_ULG_LNAHGP_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15660;"	d
+RG_TURISMO_TRX_WF_RX_ULG_LNALG_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15664;"	d
+RG_TURISMO_TRX_WF_RX_ULG_LNALG_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15662;"	d
+RG_TURISMO_TRX_WF_RX_ULG_LNALG_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15661;"	d
+RG_TURISMO_TRX_WF_RX_ULG_LNALG_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15663;"	d
+RG_TURISMO_TRX_WF_RX_ULG_LNALG_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15665;"	d
+RG_TURISMO_TRX_WF_RX_ULG_LNA_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15644;"	d
+RG_TURISMO_TRX_WF_RX_ULG_LNA_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15642;"	d
+RG_TURISMO_TRX_WF_RX_ULG_LNA_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15641;"	d
+RG_TURISMO_TRX_WF_RX_ULG_LNA_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15643;"	d
+RG_TURISMO_TRX_WF_RX_ULG_LNA_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15645;"	d
+RG_TURISMO_TRX_WF_RX_ULG_LOBUF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15684;"	d
+RG_TURISMO_TRX_WF_RX_ULG_LOBUF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15682;"	d
+RG_TURISMO_TRX_WF_RX_ULG_LOBUF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15681;"	d
+RG_TURISMO_TRX_WF_RX_ULG_LOBUF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15683;"	d
+RG_TURISMO_TRX_WF_RX_ULG_LOBUF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15685;"	d
+RG_TURISMO_TRX_WF_RX_ULG_TZI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15689;"	d
+RG_TURISMO_TRX_WF_RX_ULG_TZI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15687;"	d
+RG_TURISMO_TRX_WF_RX_ULG_TZI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15686;"	d
+RG_TURISMO_TRX_WF_RX_ULG_TZI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15688;"	d
+RG_TURISMO_TRX_WF_RX_ULG_TZI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15690;"	d
+RG_TURISMO_TRX_WF_RX_ULG_TZ_CAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15669;"	d
+RG_TURISMO_TRX_WF_RX_ULG_TZ_CAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15667;"	d
+RG_TURISMO_TRX_WF_RX_ULG_TZ_CAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15666;"	d
+RG_TURISMO_TRX_WF_RX_ULG_TZ_CAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15668;"	d
+RG_TURISMO_TRX_WF_RX_ULG_TZ_CAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15670;"	d
+RG_TURISMO_TRX_WF_RX_ULG_TZ_GC_BOOST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15674;"	d
+RG_TURISMO_TRX_WF_RX_ULG_TZ_GC_BOOST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15672;"	d
+RG_TURISMO_TRX_WF_RX_ULG_TZ_GC_BOOST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15671;"	d
+RG_TURISMO_TRX_WF_RX_ULG_TZ_GC_BOOST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15673;"	d
+RG_TURISMO_TRX_WF_RX_ULG_TZ_GC_BOOST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15675;"	d
+RG_TURISMO_TRX_WF_RX_ULG_TZ_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15649;"	d
+RG_TURISMO_TRX_WF_RX_ULG_TZ_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15647;"	d
+RG_TURISMO_TRX_WF_RX_ULG_TZ_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15646;"	d
+RG_TURISMO_TRX_WF_RX_ULG_TZ_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15648;"	d
+RG_TURISMO_TRX_WF_RX_ULG_TZ_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15650;"	d
+RG_TURISMO_TRX_WF_RX_ULG_TZ_VCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15694;"	d
+RG_TURISMO_TRX_WF_RX_ULG_TZ_VCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15692;"	d
+RG_TURISMO_TRX_WF_RX_ULG_TZ_VCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15691;"	d
+RG_TURISMO_TRX_WF_RX_ULG_TZ_VCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15693;"	d
+RG_TURISMO_TRX_WF_RX_ULG_TZ_VCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15695;"	d
+RG_TURISMO_TRX_WF_TXLPF_BOOSTI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16034;"	d
+RG_TURISMO_TRX_WF_TXLPF_BOOSTI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16032;"	d
+RG_TURISMO_TRX_WF_TXLPF_BOOSTI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16031;"	d
+RG_TURISMO_TRX_WF_TXLPF_BOOSTI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16033;"	d
+RG_TURISMO_TRX_WF_TXLPF_BOOSTI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16035;"	d
+RG_TURISMO_TRX_WF_TXPGA_CAPSW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15309;"	d
+RG_TURISMO_TRX_WF_TXPGA_CAPSW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15307;"	d
+RG_TURISMO_TRX_WF_TXPGA_CAPSW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15306;"	d
+RG_TURISMO_TRX_WF_TXPGA_CAPSW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15308;"	d
+RG_TURISMO_TRX_WF_TXPGA_CAPSW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15310;"	d
+RG_TURISMO_TRX_WF_TX_BTPASW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15324;"	d
+RG_TURISMO_TRX_WF_TX_BTPASW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15322;"	d
+RG_TURISMO_TRX_WF_TX_BTPASW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15321;"	d
+RG_TURISMO_TRX_WF_TX_BTPASW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15323;"	d
+RG_TURISMO_TRX_WF_TX_BTPASW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15325;"	d
+RG_TURISMO_TRX_WF_TX_DACI1ST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16004;"	d
+RG_TURISMO_TRX_WF_TX_DACI1ST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16002;"	d
+RG_TURISMO_TRX_WF_TX_DACI1ST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16001;"	d
+RG_TURISMO_TRX_WF_TX_DACI1ST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16003;"	d
+RG_TURISMO_TRX_WF_TX_DACI1ST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16005;"	d
+RG_TURISMO_TRX_WF_TX_DACLPF_ICOARSE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16009;"	d
+RG_TURISMO_TRX_WF_TX_DACLPF_ICOARSE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16007;"	d
+RG_TURISMO_TRX_WF_TX_DACLPF_ICOARSE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16006;"	d
+RG_TURISMO_TRX_WF_TX_DACLPF_ICOARSE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16008;"	d
+RG_TURISMO_TRX_WF_TX_DACLPF_ICOARSE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16010;"	d
+RG_TURISMO_TRX_WF_TX_DACLPF_IFINE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16014;"	d
+RG_TURISMO_TRX_WF_TX_DACLPF_IFINE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16012;"	d
+RG_TURISMO_TRX_WF_TX_DACLPF_IFINE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16011;"	d
+RG_TURISMO_TRX_WF_TX_DACLPF_IFINE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16013;"	d
+RG_TURISMO_TRX_WF_TX_DACLPF_IFINE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16015;"	d
+RG_TURISMO_TRX_WF_TX_DACLPF_VCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16019;"	d
+RG_TURISMO_TRX_WF_TX_DACLPF_VCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16017;"	d
+RG_TURISMO_TRX_WF_TX_DACLPF_VCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16016;"	d
+RG_TURISMO_TRX_WF_TX_DACLPF_VCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16018;"	d
+RG_TURISMO_TRX_WF_TX_DACLPF_VCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16020;"	d
+RG_TURISMO_TRX_WF_TX_DAC_CKEDGE_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16044;"	d
+RG_TURISMO_TRX_WF_TX_DAC_CKEDGE_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16042;"	d
+RG_TURISMO_TRX_WF_TX_DAC_CKEDGE_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16041;"	d
+RG_TURISMO_TRX_WF_TX_DAC_CKEDGE_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16043;"	d
+RG_TURISMO_TRX_WF_TX_DAC_CKEDGE_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16045;"	d
+RG_TURISMO_TRX_WF_TX_DAC_IATTN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16029;"	d
+RG_TURISMO_TRX_WF_TX_DAC_IATTN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16027;"	d
+RG_TURISMO_TRX_WF_TX_DAC_IATTN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16026;"	d
+RG_TURISMO_TRX_WF_TX_DAC_IATTN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16028;"	d
+RG_TURISMO_TRX_WF_TX_DAC_IATTN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16030;"	d
+RG_TURISMO_TRX_WF_TX_DAC_IBIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16024;"	d
+RG_TURISMO_TRX_WF_TX_DAC_IBIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16022;"	d
+RG_TURISMO_TRX_WF_TX_DAC_IBIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16021;"	d
+RG_TURISMO_TRX_WF_TX_DAC_IBIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16023;"	d
+RG_TURISMO_TRX_WF_TX_DAC_IBIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16025;"	d
+RG_TURISMO_TRX_WF_TX_DAC_IOFFSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16054;"	d
+RG_TURISMO_TRX_WF_TX_DAC_IOFFSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16052;"	d
+RG_TURISMO_TRX_WF_TX_DAC_IOFFSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16051;"	d
+RG_TURISMO_TRX_WF_TX_DAC_IOFFSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16053;"	d
+RG_TURISMO_TRX_WF_TX_DAC_IOFFSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16055;"	d
+RG_TURISMO_TRX_WF_TX_DAC_OS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16049;"	d
+RG_TURISMO_TRX_WF_TX_DAC_OS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16047;"	d
+RG_TURISMO_TRX_WF_TX_DAC_OS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16046;"	d
+RG_TURISMO_TRX_WF_TX_DAC_OS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16048;"	d
+RG_TURISMO_TRX_WF_TX_DAC_OS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16050;"	d
+RG_TURISMO_TRX_WF_TX_DAC_QOFFSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16059;"	d
+RG_TURISMO_TRX_WF_TX_DAC_QOFFSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16057;"	d
+RG_TURISMO_TRX_WF_TX_DAC_QOFFSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16056;"	d
+RG_TURISMO_TRX_WF_TX_DAC_QOFFSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16058;"	d
+RG_TURISMO_TRX_WF_TX_DAC_QOFFSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16060;"	d
+RG_TURISMO_TRX_WF_TX_DAC_RCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	16039;"	d
+RG_TURISMO_TRX_WF_TX_DAC_RCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16037;"	d
+RG_TURISMO_TRX_WF_TX_DAC_RCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	16036;"	d
+RG_TURISMO_TRX_WF_TX_DAC_RCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	16038;"	d
+RG_TURISMO_TRX_WF_TX_DAC_RCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	16040;"	d
+RG_TURISMO_TRX_WF_TX_DIV_VSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15314;"	d
+RG_TURISMO_TRX_WF_TX_DIV_VSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15312;"	d
+RG_TURISMO_TRX_WF_TX_DIV_VSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15311;"	d
+RG_TURISMO_TRX_WF_TX_DIV_VSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15313;"	d
+RG_TURISMO_TRX_WF_TX_DIV_VSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15315;"	d
+RG_TURISMO_TRX_WF_TX_GAIN_OFFSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15449;"	d
+RG_TURISMO_TRX_WF_TX_GAIN_OFFSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15447;"	d
+RG_TURISMO_TRX_WF_TX_GAIN_OFFSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15446;"	d
+RG_TURISMO_TRX_WF_TX_GAIN_OFFSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15448;"	d
+RG_TURISMO_TRX_WF_TX_GAIN_OFFSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15450;"	d
+RG_TURISMO_TRX_WF_TX_LOBUF_VSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15319;"	d
+RG_TURISMO_TRX_WF_TX_LOBUF_VSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15317;"	d
+RG_TURISMO_TRX_WF_TX_LOBUF_VSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15316;"	d
+RG_TURISMO_TRX_WF_TX_LOBUF_VSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15318;"	d
+RG_TURISMO_TRX_WF_TX_LOBUF_VSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15320;"	d
+RG_TURISMO_TRX_WF_TX_PA1_VCAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15394;"	d
+RG_TURISMO_TRX_WF_TX_PA1_VCAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15392;"	d
+RG_TURISMO_TRX_WF_TX_PA1_VCAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15391;"	d
+RG_TURISMO_TRX_WF_TX_PA1_VCAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15393;"	d
+RG_TURISMO_TRX_WF_TX_PA1_VCAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15395;"	d
+RG_TURISMO_TRX_WF_TX_PA2_VCAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15399;"	d
+RG_TURISMO_TRX_WF_TX_PA2_VCAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15397;"	d
+RG_TURISMO_TRX_WF_TX_PA2_VCAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15396;"	d
+RG_TURISMO_TRX_WF_TX_PA2_VCAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15398;"	d
+RG_TURISMO_TRX_WF_TX_PA2_VCAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15400;"	d
+RG_TURISMO_TRX_WF_TX_PA3_VCAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	15404;"	d
+RG_TURISMO_TRX_WF_TX_PA3_VCAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15402;"	d
+RG_TURISMO_TRX_WF_TX_PA3_VCAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	15401;"	d
+RG_TURISMO_TRX_WF_TX_PA3_VCAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	15403;"	d
+RG_TURISMO_TRX_WF_TX_PA3_VCAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	15405;"	d
+RG_TURISMO_TRX_XO_CBANKI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20689;"	d
+RG_TURISMO_TRX_XO_CBANKI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20687;"	d
+RG_TURISMO_TRX_XO_CBANKI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20686;"	d
+RG_TURISMO_TRX_XO_CBANKI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20688;"	d
+RG_TURISMO_TRX_XO_CBANKI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20690;"	d
+RG_TURISMO_TRX_XO_CBANKO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20694;"	d
+RG_TURISMO_TRX_XO_CBANKO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20692;"	d
+RG_TURISMO_TRX_XO_CBANKO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20691;"	d
+RG_TURISMO_TRX_XO_CBANKO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20693;"	d
+RG_TURISMO_TRX_XO_CBANKO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20695;"	d
+RG_TURISMO_TRX_XO_LDO_LEVEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20669;"	d
+RG_TURISMO_TRX_XO_LDO_LEVEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20667;"	d
+RG_TURISMO_TRX_XO_LDO_LEVEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20666;"	d
+RG_TURISMO_TRX_XO_LDO_LEVEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20668;"	d
+RG_TURISMO_TRX_XO_LDO_LEVEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20670;"	d
+RG_TURISMO_TRX_XO_TIMMER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20754;"	d
+RG_TURISMO_TRX_XO_TIMMER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20752;"	d
+RG_TURISMO_TRX_XO_TIMMER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20751;"	d
+RG_TURISMO_TRX_XO_TIMMER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20753;"	d
+RG_TURISMO_TRX_XO_TIMMER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20755;"	d
+RG_TXBTPA_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24629;"	d
+RG_TXBTPA_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24627;"	d
+RG_TXBTPA_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24626;"	d
+RG_TXBTPA_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24628;"	d
+RG_TXBTPA_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24630;"	d
+RG_TXDAC_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24609;"	d
+RG_TXDAC_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24607;"	d
+RG_TXDAC_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24606;"	d
+RG_TXDAC_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24608;"	d
+RG_TXDAC_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24610;"	d
+RG_TXDAC_R2T_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24654;"	d
+RG_TXDAC_R2T_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24652;"	d
+RG_TXDAC_R2T_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24651;"	d
+RG_TXDAC_R2T_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24653;"	d
+RG_TXDAC_R2T_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24655;"	d
+RG_TXDAC_T2R_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24634;"	d
+RG_TXDAC_T2R_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24632;"	d
+RG_TXDAC_T2R_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24631;"	d
+RG_TXDAC_T2R_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24633;"	d
+RG_TXDAC_T2R_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24635;"	d
+RG_TXD_SEL_HI	include/ssv6200_aux.h	13259;"	d
+RG_TXD_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30444;"	d
+RG_TXD_SEL_I_MSK	include/ssv6200_aux.h	13257;"	d
+RG_TXD_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30442;"	d
+RG_TXD_SEL_MSK	include/ssv6200_aux.h	13256;"	d
+RG_TXD_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30441;"	d
+RG_TXD_SEL_SFT	include/ssv6200_aux.h	13258;"	d
+RG_TXD_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30443;"	d
+RG_TXD_SEL_SZ	include/ssv6200_aux.h	13260;"	d
+RG_TXD_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30445;"	d
+RG_TXGAIN_MANUAL_HI	include/ssv6200_aux.h	16749;"	d
+RG_TXGAIN_MANUAL_I_MSK	include/ssv6200_aux.h	16747;"	d
+RG_TXGAIN_MANUAL_MSK	include/ssv6200_aux.h	16746;"	d
+RG_TXGAIN_MANUAL_SFT	include/ssv6200_aux.h	16748;"	d
+RG_TXGAIN_MANUAL_SZ	include/ssv6200_aux.h	16750;"	d
+RG_TXGAIN_PHYCTRL_HI	include/ssv6200_aux.h	16739;"	d
+RG_TXGAIN_PHYCTRL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21599;"	d
+RG_TXGAIN_PHYCTRL_I_MSK	include/ssv6200_aux.h	16737;"	d
+RG_TXGAIN_PHYCTRL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21597;"	d
+RG_TXGAIN_PHYCTRL_MSK	include/ssv6200_aux.h	16736;"	d
+RG_TXGAIN_PHYCTRL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21596;"	d
+RG_TXGAIN_PHYCTRL_SFT	include/ssv6200_aux.h	16738;"	d
+RG_TXGAIN_PHYCTRL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21598;"	d
+RG_TXGAIN_PHYCTRL_SZ	include/ssv6200_aux.h	16740;"	d
+RG_TXGAIN_PHYCTRL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21600;"	d
+RG_TXIQ_CLP_THD_I_HI	include/ssv6200_aux.h	15424;"	d
+RG_TXIQ_CLP_THD_I_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28989;"	d
+RG_TXIQ_CLP_THD_I_I_MSK	include/ssv6200_aux.h	15422;"	d
+RG_TXIQ_CLP_THD_I_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28987;"	d
+RG_TXIQ_CLP_THD_I_MSK	include/ssv6200_aux.h	15421;"	d
+RG_TXIQ_CLP_THD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28986;"	d
+RG_TXIQ_CLP_THD_I_SFT	include/ssv6200_aux.h	15423;"	d
+RG_TXIQ_CLP_THD_I_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28988;"	d
+RG_TXIQ_CLP_THD_I_SZ	include/ssv6200_aux.h	15425;"	d
+RG_TXIQ_CLP_THD_I_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28990;"	d
+RG_TXIQ_CLP_THD_Q_HI	include/ssv6200_aux.h	15429;"	d
+RG_TXIQ_CLP_THD_Q_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28994;"	d
+RG_TXIQ_CLP_THD_Q_I_MSK	include/ssv6200_aux.h	15427;"	d
+RG_TXIQ_CLP_THD_Q_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28992;"	d
+RG_TXIQ_CLP_THD_Q_MSK	include/ssv6200_aux.h	15426;"	d
+RG_TXIQ_CLP_THD_Q_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28991;"	d
+RG_TXIQ_CLP_THD_Q_SFT	include/ssv6200_aux.h	15428;"	d
+RG_TXIQ_CLP_THD_Q_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28993;"	d
+RG_TXIQ_CLP_THD_Q_SZ	include/ssv6200_aux.h	15430;"	d
+RG_TXIQ_CLP_THD_Q_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28995;"	d
+RG_TXIQ_EMU_IDX_HI	include/ssv6200_aux.h	15454;"	d
+RG_TXIQ_EMU_IDX_I_MSK	include/ssv6200_aux.h	15452;"	d
+RG_TXIQ_EMU_IDX_MSK	include/ssv6200_aux.h	15451;"	d
+RG_TXIQ_EMU_IDX_SFT	include/ssv6200_aux.h	15453;"	d
+RG_TXIQ_EMU_IDX_SZ	include/ssv6200_aux.h	15455;"	d
+RG_TXIQ_NOSHRINK_HI	include/ssv6200_aux.h	15484;"	d
+RG_TXIQ_NOSHRINK_I_MSK	include/ssv6200_aux.h	15482;"	d
+RG_TXIQ_NOSHRINK_MSK	include/ssv6200_aux.h	15481;"	d
+RG_TXIQ_NOSHRINK_SFT	include/ssv6200_aux.h	15483;"	d
+RG_TXIQ_NOSHRINK_SZ	include/ssv6200_aux.h	15485;"	d
+RG_TXIQ_NOSHRK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27254;"	d
+RG_TXIQ_NOSHRK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27252;"	d
+RG_TXIQ_NOSHRK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27251;"	d
+RG_TXIQ_NOSHRK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27253;"	d
+RG_TXIQ_NOSHRK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27255;"	d
+RG_TXLPF_BOOSTI_HI	include/ssv6200_aux.h	16899;"	d
+RG_TXLPF_BOOSTI_I_MSK	include/ssv6200_aux.h	16897;"	d
+RG_TXLPF_BOOSTI_MSK	include/ssv6200_aux.h	16896;"	d
+RG_TXLPF_BOOSTI_SFT	include/ssv6200_aux.h	16898;"	d
+RG_TXLPF_BOOSTI_SZ	include/ssv6200_aux.h	16900;"	d
+RG_TXLPF_BYPASS_HI	include/ssv6200_aux.h	16894;"	d
+RG_TXLPF_BYPASS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21884;"	d
+RG_TXLPF_BYPASS_I_MSK	include/ssv6200_aux.h	16892;"	d
+RG_TXLPF_BYPASS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21882;"	d
+RG_TXLPF_BYPASS_MSK	include/ssv6200_aux.h	16891;"	d
+RG_TXLPF_BYPASS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21881;"	d
+RG_TXLPF_BYPASS_SFT	include/ssv6200_aux.h	16893;"	d
+RG_TXLPF_BYPASS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21883;"	d
+RG_TXLPF_BYPASS_SZ	include/ssv6200_aux.h	16895;"	d
+RG_TXLPF_BYPASS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21885;"	d
+RG_TXLPF_GMCELL_HI	include/ssv6200_aux.h	16504;"	d
+RG_TXLPF_GMCELL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22404;"	d
+RG_TXLPF_GMCELL_I_MSK	include/ssv6200_aux.h	16502;"	d
+RG_TXLPF_GMCELL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22402;"	d
+RG_TXLPF_GMCELL_MSK	include/ssv6200_aux.h	16501;"	d
+RG_TXLPF_GMCELL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22401;"	d
+RG_TXLPF_GMCELL_SFT	include/ssv6200_aux.h	16503;"	d
+RG_TXLPF_GMCELL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22403;"	d
+RG_TXLPF_GMCELL_SZ	include/ssv6200_aux.h	16505;"	d
+RG_TXLPF_GMCELL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22405;"	d
+RG_TXMOD_GMCELL_HI	include/ssv6200_aux.h	16499;"	d
+RG_TXMOD_GMCELL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22399;"	d
+RG_TXMOD_GMCELL_I_MSK	include/ssv6200_aux.h	16497;"	d
+RG_TXMOD_GMCELL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22397;"	d
+RG_TXMOD_GMCELL_MSK	include/ssv6200_aux.h	16496;"	d
+RG_TXMOD_GMCELL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22396;"	d
+RG_TXMOD_GMCELL_SFT	include/ssv6200_aux.h	16498;"	d
+RG_TXMOD_GMCELL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22398;"	d
+RG_TXMOD_GMCELL_SZ	include/ssv6200_aux.h	16500;"	d
+RG_TXMOD_GMCELL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22400;"	d
+RG_TXPA_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24619;"	d
+RG_TXPA_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24617;"	d
+RG_TXPA_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24616;"	d
+RG_TXPA_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24618;"	d
+RG_TXPA_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24620;"	d
+RG_TXPA_R2T_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24664;"	d
+RG_TXPA_R2T_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24662;"	d
+RG_TXPA_R2T_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24661;"	d
+RG_TXPA_R2T_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24663;"	d
+RG_TXPA_R2T_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24665;"	d
+RG_TXPA_T2R_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24644;"	d
+RG_TXPA_T2R_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24642;"	d
+RG_TXPA_T2R_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24641;"	d
+RG_TXPA_T2R_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24643;"	d
+RG_TXPA_T2R_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24645;"	d
+RG_TXPGA_CAPSW_HI	include/ssv6200_aux.h	16484;"	d
+RG_TXPGA_CAPSW_I_MSK	include/ssv6200_aux.h	16482;"	d
+RG_TXPGA_CAPSW_MSK	include/ssv6200_aux.h	16481;"	d
+RG_TXPGA_CAPSW_SFT	include/ssv6200_aux.h	16483;"	d
+RG_TXPGA_CAPSW_SZ	include/ssv6200_aux.h	16485;"	d
+RG_TXPGA_MAIN_HI	include/ssv6200_aux.h	16489;"	d
+RG_TXPGA_MAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22389;"	d
+RG_TXPGA_MAIN_I_MSK	include/ssv6200_aux.h	16487;"	d
+RG_TXPGA_MAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22387;"	d
+RG_TXPGA_MAIN_MSK	include/ssv6200_aux.h	16486;"	d
+RG_TXPGA_MAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22386;"	d
+RG_TXPGA_MAIN_SFT	include/ssv6200_aux.h	16488;"	d
+RG_TXPGA_MAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22388;"	d
+RG_TXPGA_MAIN_SZ	include/ssv6200_aux.h	16490;"	d
+RG_TXPGA_MAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22390;"	d
+RG_TXPGA_STEER_HI	include/ssv6200_aux.h	16494;"	d
+RG_TXPGA_STEER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22394;"	d
+RG_TXPGA_STEER_I_MSK	include/ssv6200_aux.h	16492;"	d
+RG_TXPGA_STEER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22392;"	d
+RG_TXPGA_STEER_MSK	include/ssv6200_aux.h	16491;"	d
+RG_TXPGA_STEER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22391;"	d
+RG_TXPGA_STEER_SFT	include/ssv6200_aux.h	16493;"	d
+RG_TXPGA_STEER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22393;"	d
+RG_TXPGA_STEER_SZ	include/ssv6200_aux.h	16495;"	d
+RG_TXPGA_STEER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22395;"	d
+RG_TXPWRLVL_HI	include/ssv6200_aux.h	13209;"	d
+RG_TXPWRLVL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30399;"	d
+RG_TXPWRLVL_I_MSK	include/ssv6200_aux.h	13207;"	d
+RG_TXPWRLVL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30397;"	d
+RG_TXPWRLVL_MSK	include/ssv6200_aux.h	13206;"	d
+RG_TXPWRLVL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30396;"	d
+RG_TXPWRLVL_SEL_HI	include/ssv6200_aux.h	13049;"	d
+RG_TXPWRLVL_SEL_I_MSK	include/ssv6200_aux.h	13047;"	d
+RG_TXPWRLVL_SEL_MSK	include/ssv6200_aux.h	13046;"	d
+RG_TXPWRLVL_SEL_SFT	include/ssv6200_aux.h	13048;"	d
+RG_TXPWRLVL_SEL_SZ	include/ssv6200_aux.h	13050;"	d
+RG_TXPWRLVL_SET_HI	include/ssv6200_aux.h	13044;"	d
+RG_TXPWRLVL_SET_I_MSK	include/ssv6200_aux.h	13042;"	d
+RG_TXPWRLVL_SET_MSK	include/ssv6200_aux.h	13041;"	d
+RG_TXPWRLVL_SET_SFT	include/ssv6200_aux.h	13043;"	d
+RG_TXPWRLVL_SET_SZ	include/ssv6200_aux.h	13045;"	d
+RG_TXPWRLVL_SFT	include/ssv6200_aux.h	13208;"	d
+RG_TXPWRLVL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30398;"	d
+RG_TXPWRLVL_SZ	include/ssv6200_aux.h	13210;"	d
+RG_TXPWRLVL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30400;"	d
+RG_TXRF_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24614;"	d
+RG_TXRF_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24612;"	d
+RG_TXRF_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24611;"	d
+RG_TXRF_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24613;"	d
+RG_TXRF_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24615;"	d
+RG_TXRF_R2T_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24659;"	d
+RG_TXRF_R2T_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24657;"	d
+RG_TXRF_R2T_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24656;"	d
+RG_TXRF_R2T_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24658;"	d
+RG_TXRF_R2T_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24660;"	d
+RG_TXRF_T2R_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24639;"	d
+RG_TXRF_T2R_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24637;"	d
+RG_TXRF_T2R_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24636;"	d
+RG_TXRF_T2R_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24638;"	d
+RG_TXRF_T2R_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24640;"	d
+RG_TX_BB_SCALE_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29009;"	d
+RG_TX_BB_SCALE_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29007;"	d
+RG_TX_BB_SCALE_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29006;"	d
+RG_TX_BB_SCALE_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29008;"	d
+RG_TX_BB_SCALE_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29010;"	d
+RG_TX_BT_PA_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21784;"	d
+RG_TX_BT_PA_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21782;"	d
+RG_TX_BT_PA_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21781;"	d
+RG_TX_BT_PA_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21783;"	d
+RG_TX_BT_PA_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21785;"	d
+RG_TX_CLK_OUTER_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31924;"	d
+RG_TX_CLK_OUTER_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31922;"	d
+RG_TX_CLK_OUTER_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31921;"	d
+RG_TX_CLK_OUTER_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31923;"	d
+RG_TX_CLK_OUTER_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31925;"	d
+RG_TX_CNT_TARGET_HI	include/ssv6200_aux.h	13239;"	d
+RG_TX_CNT_TARGET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30439;"	d
+RG_TX_CNT_TARGET_I_MSK	include/ssv6200_aux.h	13237;"	d
+RG_TX_CNT_TARGET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30437;"	d
+RG_TX_CNT_TARGET_MSK	include/ssv6200_aux.h	13236;"	d
+RG_TX_CNT_TARGET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30436;"	d
+RG_TX_CNT_TARGET_SFT	include/ssv6200_aux.h	13238;"	d
+RG_TX_CNT_TARGET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30438;"	d
+RG_TX_CNT_TARGET_SZ	include/ssv6200_aux.h	13240;"	d
+RG_TX_CNT_TARGET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30440;"	d
+RG_TX_DACLPF_ICOURSE_HI	include/ssv6200_aux.h	16849;"	d
+RG_TX_DACLPF_ICOURSE_I_MSK	include/ssv6200_aux.h	16847;"	d
+RG_TX_DACLPF_ICOURSE_MSK	include/ssv6200_aux.h	16846;"	d
+RG_TX_DACLPF_ICOURSE_SFT	include/ssv6200_aux.h	16848;"	d
+RG_TX_DACLPF_ICOURSE_SZ	include/ssv6200_aux.h	16850;"	d
+RG_TX_DACLPF_IFINE_HI	include/ssv6200_aux.h	16854;"	d
+RG_TX_DACLPF_IFINE_I_MSK	include/ssv6200_aux.h	16852;"	d
+RG_TX_DACLPF_IFINE_MSK	include/ssv6200_aux.h	16851;"	d
+RG_TX_DACLPF_IFINE_SFT	include/ssv6200_aux.h	16853;"	d
+RG_TX_DACLPF_IFINE_SZ	include/ssv6200_aux.h	16855;"	d
+RG_TX_DACLPF_VCM_HI	include/ssv6200_aux.h	16859;"	d
+RG_TX_DACLPF_VCM_I_MSK	include/ssv6200_aux.h	16857;"	d
+RG_TX_DACLPF_VCM_MSK	include/ssv6200_aux.h	16856;"	d
+RG_TX_DACLPF_VCM_SFT	include/ssv6200_aux.h	16858;"	d
+RG_TX_DACLPF_VCM_SZ	include/ssv6200_aux.h	16860;"	d
+RG_TX_DAC_CAL_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21819;"	d
+RG_TX_DAC_CAL_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21817;"	d
+RG_TX_DAC_CAL_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21816;"	d
+RG_TX_DAC_CAL_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21818;"	d
+RG_TX_DAC_CAL_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21820;"	d
+RG_TX_DAC_CKEDGE_SEL_HI	include/ssv6200_aux.h	16864;"	d
+RG_TX_DAC_CKEDGE_SEL_I_MSK	include/ssv6200_aux.h	16862;"	d
+RG_TX_DAC_CKEDGE_SEL_MSK	include/ssv6200_aux.h	16861;"	d
+RG_TX_DAC_CKEDGE_SEL_SFT	include/ssv6200_aux.h	16863;"	d
+RG_TX_DAC_CKEDGE_SEL_SZ	include/ssv6200_aux.h	16865;"	d
+RG_TX_DAC_EN_HI	include/ssv6200_aux.h	16074;"	d
+RG_TX_DAC_EN_I_MSK	include/ssv6200_aux.h	16072;"	d
+RG_TX_DAC_EN_MSK	include/ssv6200_aux.h	16071;"	d
+RG_TX_DAC_EN_SFT	include/ssv6200_aux.h	16073;"	d
+RG_TX_DAC_EN_SZ	include/ssv6200_aux.h	16075;"	d
+RG_TX_DAC_IBIAS_HI	include/ssv6200_aux.h	16869;"	d
+RG_TX_DAC_IBIAS_I_MSK	include/ssv6200_aux.h	16867;"	d
+RG_TX_DAC_IBIAS_MSK	include/ssv6200_aux.h	16866;"	d
+RG_TX_DAC_IBIAS_SFT	include/ssv6200_aux.h	16868;"	d
+RG_TX_DAC_IBIAS_SZ	include/ssv6200_aux.h	16870;"	d
+RG_TX_DAC_IOFFSET_HI	include/ssv6200_aux.h	16904;"	d
+RG_TX_DAC_IOFFSET_I_MSK	include/ssv6200_aux.h	16902;"	d
+RG_TX_DAC_IOFFSET_MSK	include/ssv6200_aux.h	16901;"	d
+RG_TX_DAC_IOFFSET_SFT	include/ssv6200_aux.h	16903;"	d
+RG_TX_DAC_IOFFSET_SZ	include/ssv6200_aux.h	16905;"	d
+RG_TX_DAC_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21754;"	d
+RG_TX_DAC_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21752;"	d
+RG_TX_DAC_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21751;"	d
+RG_TX_DAC_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21753;"	d
+RG_TX_DAC_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21755;"	d
+RG_TX_DAC_OS_HI	include/ssv6200_aux.h	16874;"	d
+RG_TX_DAC_OS_I_MSK	include/ssv6200_aux.h	16872;"	d
+RG_TX_DAC_OS_MSK	include/ssv6200_aux.h	16871;"	d
+RG_TX_DAC_OS_SFT	include/ssv6200_aux.h	16873;"	d
+RG_TX_DAC_OS_SZ	include/ssv6200_aux.h	16875;"	d
+RG_TX_DAC_QOFFSET_HI	include/ssv6200_aux.h	16909;"	d
+RG_TX_DAC_QOFFSET_I_MSK	include/ssv6200_aux.h	16907;"	d
+RG_TX_DAC_QOFFSET_MSK	include/ssv6200_aux.h	16906;"	d
+RG_TX_DAC_QOFFSET_SFT	include/ssv6200_aux.h	16908;"	d
+RG_TX_DAC_QOFFSET_SZ	include/ssv6200_aux.h	16910;"	d
+RG_TX_DAC_RCAL_HI	include/ssv6200_aux.h	16879;"	d
+RG_TX_DAC_RCAL_I_MSK	include/ssv6200_aux.h	16877;"	d
+RG_TX_DAC_RCAL_MSK	include/ssv6200_aux.h	16876;"	d
+RG_TX_DAC_RCAL_SFT	include/ssv6200_aux.h	16878;"	d
+RG_TX_DAC_RCAL_SZ	include/ssv6200_aux.h	16880;"	d
+RG_TX_DAC_TSEL_HI	include/ssv6200_aux.h	16884;"	d
+RG_TX_DAC_TSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23034;"	d
+RG_TX_DAC_TSEL_I_MSK	include/ssv6200_aux.h	16882;"	d
+RG_TX_DAC_TSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23032;"	d
+RG_TX_DAC_TSEL_MSK	include/ssv6200_aux.h	16881;"	d
+RG_TX_DAC_TSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23031;"	d
+RG_TX_DAC_TSEL_SFT	include/ssv6200_aux.h	16883;"	d
+RG_TX_DAC_TSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23033;"	d
+RG_TX_DAC_TSEL_SZ	include/ssv6200_aux.h	16885;"	d
+RG_TX_DAC_TSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23035;"	d
+RG_TX_DCCAL_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24689;"	d
+RG_TX_DCCAL_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24687;"	d
+RG_TX_DCCAL_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24686;"	d
+RG_TX_DCCAL_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24688;"	d
+RG_TX_DCCAL_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24690;"	d
+RG_TX_DES_ACK_PRD_HI	include/ssv6200_aux.h	13749;"	d
+RG_TX_DES_ACK_PRD_I_MSK	include/ssv6200_aux.h	13747;"	d
+RG_TX_DES_ACK_PRD_MSK	include/ssv6200_aux.h	13746;"	d
+RG_TX_DES_ACK_PRD_SFT	include/ssv6200_aux.h	13748;"	d
+RG_TX_DES_ACK_PRD_SZ	include/ssv6200_aux.h	13750;"	d
+RG_TX_DES_ACK_WIDTH_HI	include/ssv6200_aux.h	13744;"	d
+RG_TX_DES_ACK_WIDTH_I_MSK	include/ssv6200_aux.h	13742;"	d
+RG_TX_DES_ACK_WIDTH_MSK	include/ssv6200_aux.h	13741;"	d
+RG_TX_DES_ACK_WIDTH_SFT	include/ssv6200_aux.h	13743;"	d
+RG_TX_DES_ACK_WIDTH_SZ	include/ssv6200_aux.h	13745;"	d
+RG_TX_DES_EXCP_CLR_HI	include/ssv6200_aux.h	13739;"	d
+RG_TX_DES_EXCP_CLR_I_MSK	include/ssv6200_aux.h	13737;"	d
+RG_TX_DES_EXCP_CLR_MSK	include/ssv6200_aux.h	13736;"	d
+RG_TX_DES_EXCP_CLR_SFT	include/ssv6200_aux.h	13738;"	d
+RG_TX_DES_EXCP_CLR_SZ	include/ssv6200_aux.h	13740;"	d
+RG_TX_DES_EXCP_MODE_DEFAULT_HI	include/ssv6200_aux.h	13734;"	d
+RG_TX_DES_EXCP_MODE_DEFAULT_I_MSK	include/ssv6200_aux.h	13732;"	d
+RG_TX_DES_EXCP_MODE_DEFAULT_MSK	include/ssv6200_aux.h	13731;"	d
+RG_TX_DES_EXCP_MODE_DEFAULT_SFT	include/ssv6200_aux.h	13733;"	d
+RG_TX_DES_EXCP_MODE_DEFAULT_SZ	include/ssv6200_aux.h	13735;"	d
+RG_TX_DES_EXCP_RATE_DEFAULT_HI	include/ssv6200_aux.h	13729;"	d
+RG_TX_DES_EXCP_RATE_DEFAULT_I_MSK	include/ssv6200_aux.h	13727;"	d
+RG_TX_DES_EXCP_RATE_DEFAULT_MSK	include/ssv6200_aux.h	13726;"	d
+RG_TX_DES_EXCP_RATE_DEFAULT_SFT	include/ssv6200_aux.h	13728;"	d
+RG_TX_DES_EXCP_RATE_DEFAULT_SZ	include/ssv6200_aux.h	13730;"	d
+RG_TX_DES_LEN_LO_HI	include/ssv6200_aux.h	13579;"	d
+RG_TX_DES_LEN_LO_I_MSK	include/ssv6200_aux.h	13577;"	d
+RG_TX_DES_LEN_LO_MSK	include/ssv6200_aux.h	13576;"	d
+RG_TX_DES_LEN_LO_SFT	include/ssv6200_aux.h	13578;"	d
+RG_TX_DES_LEN_LO_SZ	include/ssv6200_aux.h	13580;"	d
+RG_TX_DES_LEN_UP_HI	include/ssv6200_aux.h	13584;"	d
+RG_TX_DES_LEN_UP_I_MSK	include/ssv6200_aux.h	13582;"	d
+RG_TX_DES_LEN_UP_MSK	include/ssv6200_aux.h	13581;"	d
+RG_TX_DES_LEN_UP_SFT	include/ssv6200_aux.h	13583;"	d
+RG_TX_DES_LEN_UP_SZ	include/ssv6200_aux.h	13585;"	d
+RG_TX_DES_L_LEN_LO_HI	include/ssv6200_aux.h	13594;"	d
+RG_TX_DES_L_LEN_LO_I_MSK	include/ssv6200_aux.h	13592;"	d
+RG_TX_DES_L_LEN_LO_MSK	include/ssv6200_aux.h	13591;"	d
+RG_TX_DES_L_LEN_LO_SFT	include/ssv6200_aux.h	13593;"	d
+RG_TX_DES_L_LEN_LO_SZ	include/ssv6200_aux.h	13595;"	d
+RG_TX_DES_L_LEN_UP_COMB_HI	include/ssv6200_aux.h	13609;"	d
+RG_TX_DES_L_LEN_UP_COMB_I_MSK	include/ssv6200_aux.h	13607;"	d
+RG_TX_DES_L_LEN_UP_COMB_MSK	include/ssv6200_aux.h	13606;"	d
+RG_TX_DES_L_LEN_UP_COMB_SFT	include/ssv6200_aux.h	13608;"	d
+RG_TX_DES_L_LEN_UP_COMB_SZ	include/ssv6200_aux.h	13610;"	d
+RG_TX_DES_L_LEN_UP_HI	include/ssv6200_aux.h	13599;"	d
+RG_TX_DES_L_LEN_UP_I_MSK	include/ssv6200_aux.h	13597;"	d
+RG_TX_DES_L_LEN_UP_MSK	include/ssv6200_aux.h	13596;"	d
+RG_TX_DES_L_LEN_UP_SFT	include/ssv6200_aux.h	13598;"	d
+RG_TX_DES_L_LEN_UP_SZ	include/ssv6200_aux.h	13600;"	d
+RG_TX_DES_MODE_COMB_HI	include/ssv6200_aux.h	13624;"	d
+RG_TX_DES_MODE_COMB_I_MSK	include/ssv6200_aux.h	13622;"	d
+RG_TX_DES_MODE_COMB_MSK	include/ssv6200_aux.h	13621;"	d
+RG_TX_DES_MODE_COMB_SFT	include/ssv6200_aux.h	13623;"	d
+RG_TX_DES_MODE_COMB_SZ	include/ssv6200_aux.h	13625;"	d
+RG_TX_DES_MODE_HI	include/ssv6200_aux.h	13574;"	d
+RG_TX_DES_MODE_I_MSK	include/ssv6200_aux.h	13572;"	d
+RG_TX_DES_MODE_MSK	include/ssv6200_aux.h	13571;"	d
+RG_TX_DES_MODE_SFT	include/ssv6200_aux.h	13573;"	d
+RG_TX_DES_MODE_SZ	include/ssv6200_aux.h	13575;"	d
+RG_TX_DES_PWRLVL_HI	include/ssv6200_aux.h	13629;"	d
+RG_TX_DES_PWRLVL_I_MSK	include/ssv6200_aux.h	13627;"	d
+RG_TX_DES_PWRLVL_MSK	include/ssv6200_aux.h	13626;"	d
+RG_TX_DES_PWRLVL_SFT	include/ssv6200_aux.h	13628;"	d
+RG_TX_DES_PWRLVL_SZ	include/ssv6200_aux.h	13630;"	d
+RG_TX_DES_RATE_COMB_HI	include/ssv6200_aux.h	13619;"	d
+RG_TX_DES_RATE_COMB_I_MSK	include/ssv6200_aux.h	13617;"	d
+RG_TX_DES_RATE_COMB_MSK	include/ssv6200_aux.h	13616;"	d
+RG_TX_DES_RATE_COMB_SFT	include/ssv6200_aux.h	13618;"	d
+RG_TX_DES_RATE_COMB_SZ	include/ssv6200_aux.h	13620;"	d
+RG_TX_DES_RATE_HI	include/ssv6200_aux.h	13569;"	d
+RG_TX_DES_RATE_I_MSK	include/ssv6200_aux.h	13567;"	d
+RG_TX_DES_RATE_MSK	include/ssv6200_aux.h	13566;"	d
+RG_TX_DES_RATE_SFT	include/ssv6200_aux.h	13568;"	d
+RG_TX_DES_RATE_SZ	include/ssv6200_aux.h	13570;"	d
+RG_TX_DES_SRVC_LO_HI	include/ssv6200_aux.h	13634;"	d
+RG_TX_DES_SRVC_LO_I_MSK	include/ssv6200_aux.h	13632;"	d
+RG_TX_DES_SRVC_LO_MSK	include/ssv6200_aux.h	13631;"	d
+RG_TX_DES_SRVC_LO_SFT	include/ssv6200_aux.h	13633;"	d
+RG_TX_DES_SRVC_LO_SZ	include/ssv6200_aux.h	13635;"	d
+RG_TX_DES_SRVC_UP_HI	include/ssv6200_aux.h	13589;"	d
+RG_TX_DES_SRVC_UP_I_MSK	include/ssv6200_aux.h	13587;"	d
+RG_TX_DES_SRVC_UP_MSK	include/ssv6200_aux.h	13586;"	d
+RG_TX_DES_SRVC_UP_SFT	include/ssv6200_aux.h	13588;"	d
+RG_TX_DES_SRVC_UP_SZ	include/ssv6200_aux.h	13590;"	d
+RG_TX_DES_TYPE_COMB_HI	include/ssv6200_aux.h	13614;"	d
+RG_TX_DES_TYPE_COMB_I_MSK	include/ssv6200_aux.h	13612;"	d
+RG_TX_DES_TYPE_COMB_MSK	include/ssv6200_aux.h	13611;"	d
+RG_TX_DES_TYPE_COMB_SFT	include/ssv6200_aux.h	13613;"	d
+RG_TX_DES_TYPE_COMB_SZ	include/ssv6200_aux.h	13615;"	d
+RG_TX_DES_TYPE_HI	include/ssv6200_aux.h	13604;"	d
+RG_TX_DES_TYPE_I_MSK	include/ssv6200_aux.h	13602;"	d
+RG_TX_DES_TYPE_MSK	include/ssv6200_aux.h	13601;"	d
+RG_TX_DES_TYPE_SFT	include/ssv6200_aux.h	13603;"	d
+RG_TX_DES_TYPE_SZ	include/ssv6200_aux.h	13605;"	d
+RG_TX_DIV2_BUF_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21774;"	d
+RG_TX_DIV2_BUF_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21772;"	d
+RG_TX_DIV2_BUF_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21771;"	d
+RG_TX_DIV2_BUF_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21773;"	d
+RG_TX_DIV2_BUF_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21775;"	d
+RG_TX_DIV2_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21764;"	d
+RG_TX_DIV2_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21762;"	d
+RG_TX_DIV2_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21761;"	d
+RG_TX_DIV2_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21763;"	d
+RG_TX_DIV2_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21765;"	d
+RG_TX_DIV_VSET_HI	include/ssv6200_aux.h	16519;"	d
+RG_TX_DIV_VSET_I_MSK	include/ssv6200_aux.h	16517;"	d
+RG_TX_DIV_VSET_MSK	include/ssv6200_aux.h	16516;"	d
+RG_TX_DIV_VSET_SFT	include/ssv6200_aux.h	16518;"	d
+RG_TX_DIV_VSET_SZ	include/ssv6200_aux.h	16520;"	d
+RG_TX_DPDGM_BIAS_HI	include/ssv6200_aux.h	16544;"	d
+RG_TX_DPDGM_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22249;"	d
+RG_TX_DPDGM_BIAS_I_MSK	include/ssv6200_aux.h	16542;"	d
+RG_TX_DPDGM_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22247;"	d
+RG_TX_DPDGM_BIAS_MSK	include/ssv6200_aux.h	16541;"	d
+RG_TX_DPDGM_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22246;"	d
+RG_TX_DPDGM_BIAS_SFT	include/ssv6200_aux.h	16543;"	d
+RG_TX_DPDGM_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22248;"	d
+RG_TX_DPDGM_BIAS_SZ	include/ssv6200_aux.h	16545;"	d
+RG_TX_DPDGM_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22250;"	d
+RG_TX_DPD_DIV_HI	include/ssv6200_aux.h	16549;"	d
+RG_TX_DPD_DIV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22254;"	d
+RG_TX_DPD_DIV_I_MSK	include/ssv6200_aux.h	16547;"	d
+RG_TX_DPD_DIV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22252;"	d
+RG_TX_DPD_DIV_MSK	include/ssv6200_aux.h	16546;"	d
+RG_TX_DPD_DIV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22251;"	d
+RG_TX_DPD_DIV_SFT	include/ssv6200_aux.h	16548;"	d
+RG_TX_DPD_DIV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22253;"	d
+RG_TX_DPD_DIV_SZ	include/ssv6200_aux.h	16550;"	d
+RG_TX_DPD_DIV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22255;"	d
+RG_TX_DPD_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21859;"	d
+RG_TX_DPD_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21857;"	d
+RG_TX_DPD_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21856;"	d
+RG_TX_DPD_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21858;"	d
+RG_TX_DPD_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21860;"	d
+RG_TX_D_HI	include/ssv6200_aux.h	13234;"	d
+RG_TX_D_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30429;"	d
+RG_TX_D_I_MSK	include/ssv6200_aux.h	13232;"	d
+RG_TX_D_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30427;"	d
+RG_TX_D_MSK	include/ssv6200_aux.h	13231;"	d
+RG_TX_D_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30426;"	d
+RG_TX_D_SFT	include/ssv6200_aux.h	13233;"	d
+RG_TX_D_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30428;"	d
+RG_TX_D_SZ	include/ssv6200_aux.h	13235;"	d
+RG_TX_D_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30430;"	d
+RG_TX_EN_HI	include/ssv6200_aux.h	16064;"	d
+RG_TX_EN_I_MSK	include/ssv6200_aux.h	16062;"	d
+RG_TX_EN_MSK	include/ssv6200_aux.h	16061;"	d
+RG_TX_EN_SFT	include/ssv6200_aux.h	16063;"	d
+RG_TX_EN_SZ	include/ssv6200_aux.h	16065;"	d
+RG_TX_EN_VOLTAGE_IN_HI	include/ssv6200_aux.h	16889;"	d
+RG_TX_EN_VOLTAGE_IN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21889;"	d
+RG_TX_EN_VOLTAGE_IN_I_MSK	include/ssv6200_aux.h	16887;"	d
+RG_TX_EN_VOLTAGE_IN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21887;"	d
+RG_TX_EN_VOLTAGE_IN_MSK	include/ssv6200_aux.h	16886;"	d
+RG_TX_EN_VOLTAGE_IN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21886;"	d
+RG_TX_EN_VOLTAGE_IN_SFT	include/ssv6200_aux.h	16888;"	d
+RG_TX_EN_VOLTAGE_IN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21888;"	d
+RG_TX_EN_VOLTAGE_IN_SZ	include/ssv6200_aux.h	16890;"	d
+RG_TX_EN_VOLTAGE_IN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21890;"	d
+RG_TX_FIFO_EMPTY_CNT_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31379;"	d
+RG_TX_FIFO_EMPTY_CNT_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31377;"	d
+RG_TX_FIFO_EMPTY_CNT_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31376;"	d
+RG_TX_FIFO_EMPTY_CNT_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31378;"	d
+RG_TX_FIFO_EMPTY_CNT_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31380;"	d
+RG_TX_FREQ_OFFSET_DES_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30449;"	d
+RG_TX_FREQ_OFFSET_DES_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30447;"	d
+RG_TX_FREQ_OFFSET_DES_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30446;"	d
+RG_TX_FREQ_OFFSET_DES_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30448;"	d
+RG_TX_FREQ_OFFSET_DES_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30450;"	d
+RG_TX_FREQ_OFFSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27264;"	d
+RG_TX_FREQ_OFFSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27262;"	d
+RG_TX_FREQ_OFFSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27261;"	d
+RG_TX_FREQ_OFFSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27263;"	d
+RG_TX_FREQ_OFFSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27265;"	d
+RG_TX_GAIN_DPDCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24749;"	d
+RG_TX_GAIN_DPDCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24747;"	d
+RG_TX_GAIN_DPDCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24746;"	d
+RG_TX_GAIN_DPDCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24748;"	d
+RG_TX_GAIN_DPDCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24750;"	d
+RG_TX_GAIN_HI	include/ssv6200_aux.h	16744;"	d
+RG_TX_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21639;"	d
+RG_TX_GAIN_I_MSK	include/ssv6200_aux.h	16742;"	d
+RG_TX_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21637;"	d
+RG_TX_GAIN_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21594;"	d
+RG_TX_GAIN_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21592;"	d
+RG_TX_GAIN_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21591;"	d
+RG_TX_GAIN_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21593;"	d
+RG_TX_GAIN_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21595;"	d
+RG_TX_GAIN_MSK	include/ssv6200_aux.h	16741;"	d
+RG_TX_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21636;"	d
+RG_TX_GAIN_OFFSET_HI	include/ssv6200_aux.h	16754;"	d
+RG_TX_GAIN_OFFSET_I_MSK	include/ssv6200_aux.h	16752;"	d
+RG_TX_GAIN_OFFSET_MSK	include/ssv6200_aux.h	16751;"	d
+RG_TX_GAIN_OFFSET_SFT	include/ssv6200_aux.h	16753;"	d
+RG_TX_GAIN_OFFSET_SZ	include/ssv6200_aux.h	16755;"	d
+RG_TX_GAIN_RXIQCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24734;"	d
+RG_TX_GAIN_RXIQCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24732;"	d
+RG_TX_GAIN_RXIQCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24731;"	d
+RG_TX_GAIN_RXIQCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24733;"	d
+RG_TX_GAIN_RXIQCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24735;"	d
+RG_TX_GAIN_SFT	include/ssv6200_aux.h	16743;"	d
+RG_TX_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21638;"	d
+RG_TX_GAIN_SZ	include/ssv6200_aux.h	16745;"	d
+RG_TX_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21640;"	d
+RG_TX_GAIN_TXCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24719;"	d
+RG_TX_GAIN_TXCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24717;"	d
+RG_TX_GAIN_TXCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24716;"	d
+RG_TX_GAIN_TXCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24718;"	d
+RG_TX_GAIN_TXCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24720;"	d
+RG_TX_IQCAL_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24694;"	d
+RG_TX_IQCAL_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24692;"	d
+RG_TX_IQCAL_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24691;"	d
+RG_TX_IQCAL_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24693;"	d
+RG_TX_IQCAL_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24695;"	d
+RG_TX_IQCAL_TIME_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27259;"	d
+RG_TX_IQCAL_TIME_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27257;"	d
+RG_TX_IQCAL_TIME_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27256;"	d
+RG_TX_IQCAL_TIME_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27258;"	d
+RG_TX_IQCAL_TIME_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27260;"	d
+RG_TX_IQ_2500_ALPHA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27369;"	d
+RG_TX_IQ_2500_ALPHA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27367;"	d
+RG_TX_IQ_2500_ALPHA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27366;"	d
+RG_TX_IQ_2500_ALPHA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27368;"	d
+RG_TX_IQ_2500_ALPHA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27370;"	d
+RG_TX_IQ_2500_THETA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27374;"	d
+RG_TX_IQ_2500_THETA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27372;"	d
+RG_TX_IQ_2500_THETA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27371;"	d
+RG_TX_IQ_2500_THETA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27373;"	d
+RG_TX_IQ_2500_THETA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27375;"	d
+RG_TX_IQ_5100_ALPHA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27389;"	d
+RG_TX_IQ_5100_ALPHA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27387;"	d
+RG_TX_IQ_5100_ALPHA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27386;"	d
+RG_TX_IQ_5100_ALPHA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27388;"	d
+RG_TX_IQ_5100_ALPHA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27390;"	d
+RG_TX_IQ_5100_THETA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27394;"	d
+RG_TX_IQ_5100_THETA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27392;"	d
+RG_TX_IQ_5100_THETA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27391;"	d
+RG_TX_IQ_5100_THETA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27393;"	d
+RG_TX_IQ_5100_THETA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27395;"	d
+RG_TX_IQ_5500_ALPHA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27409;"	d
+RG_TX_IQ_5500_ALPHA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27407;"	d
+RG_TX_IQ_5500_ALPHA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27406;"	d
+RG_TX_IQ_5500_ALPHA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27408;"	d
+RG_TX_IQ_5500_ALPHA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27410;"	d
+RG_TX_IQ_5500_THETA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27414;"	d
+RG_TX_IQ_5500_THETA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27412;"	d
+RG_TX_IQ_5500_THETA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27411;"	d
+RG_TX_IQ_5500_THETA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27413;"	d
+RG_TX_IQ_5500_THETA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27415;"	d
+RG_TX_IQ_5700_ALPHA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27429;"	d
+RG_TX_IQ_5700_ALPHA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27427;"	d
+RG_TX_IQ_5700_ALPHA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27426;"	d
+RG_TX_IQ_5700_ALPHA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27428;"	d
+RG_TX_IQ_5700_ALPHA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27430;"	d
+RG_TX_IQ_5700_THETA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27434;"	d
+RG_TX_IQ_5700_THETA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27432;"	d
+RG_TX_IQ_5700_THETA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27431;"	d
+RG_TX_IQ_5700_THETA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27433;"	d
+RG_TX_IQ_5700_THETA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27435;"	d
+RG_TX_IQ_5900_ALPHA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27449;"	d
+RG_TX_IQ_5900_ALPHA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27447;"	d
+RG_TX_IQ_5900_ALPHA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27446;"	d
+RG_TX_IQ_5900_ALPHA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27448;"	d
+RG_TX_IQ_5900_ALPHA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27450;"	d
+RG_TX_IQ_5900_THETA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27454;"	d
+RG_TX_IQ_5900_THETA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27452;"	d
+RG_TX_IQ_5900_THETA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27451;"	d
+RG_TX_IQ_5900_THETA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27453;"	d
+RG_TX_IQ_5900_THETA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27455;"	d
+RG_TX_IQ_ALPHA_HI	include/ssv6200_aux.h	15479;"	d
+RG_TX_IQ_ALPHA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27239;"	d
+RG_TX_IQ_ALPHA_I_MSK	include/ssv6200_aux.h	15477;"	d
+RG_TX_IQ_ALPHA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27237;"	d
+RG_TX_IQ_ALPHA_MSK	include/ssv6200_aux.h	15476;"	d
+RG_TX_IQ_ALPHA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27236;"	d
+RG_TX_IQ_ALPHA_SFT	include/ssv6200_aux.h	15478;"	d
+RG_TX_IQ_ALPHA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27238;"	d
+RG_TX_IQ_ALPHA_SZ	include/ssv6200_aux.h	15480;"	d
+RG_TX_IQ_ALPHA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27240;"	d
+RG_TX_IQ_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27249;"	d
+RG_TX_IQ_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27247;"	d
+RG_TX_IQ_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27246;"	d
+RG_TX_IQ_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27248;"	d
+RG_TX_IQ_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27250;"	d
+RG_TX_IQ_SRC_HI	include/ssv6200_aux.h	15459;"	d
+RG_TX_IQ_SRC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29014;"	d
+RG_TX_IQ_SRC_I_MSK	include/ssv6200_aux.h	15457;"	d
+RG_TX_IQ_SRC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29012;"	d
+RG_TX_IQ_SRC_MSK	include/ssv6200_aux.h	15456;"	d
+RG_TX_IQ_SRC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29011;"	d
+RG_TX_IQ_SRC_SFT	include/ssv6200_aux.h	15458;"	d
+RG_TX_IQ_SRC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29013;"	d
+RG_TX_IQ_SRC_SZ	include/ssv6200_aux.h	15460;"	d
+RG_TX_IQ_SRC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29015;"	d
+RG_TX_IQ_SWP_HI	include/ssv6200_aux.h	15444;"	d
+RG_TX_IQ_SWP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29004;"	d
+RG_TX_IQ_SWP_I_MSK	include/ssv6200_aux.h	15442;"	d
+RG_TX_IQ_SWP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29002;"	d
+RG_TX_IQ_SWP_MSK	include/ssv6200_aux.h	15441;"	d
+RG_TX_IQ_SWP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29001;"	d
+RG_TX_IQ_SWP_SFT	include/ssv6200_aux.h	15443;"	d
+RG_TX_IQ_SWP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29003;"	d
+RG_TX_IQ_SWP_SZ	include/ssv6200_aux.h	15445;"	d
+RG_TX_IQ_SWP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29005;"	d
+RG_TX_IQ_THETA_HI	include/ssv6200_aux.h	15474;"	d
+RG_TX_IQ_THETA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27244;"	d
+RG_TX_IQ_THETA_I_MSK	include/ssv6200_aux.h	15472;"	d
+RG_TX_IQ_THETA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27242;"	d
+RG_TX_IQ_THETA_MSK	include/ssv6200_aux.h	15471;"	d
+RG_TX_IQ_THETA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27241;"	d
+RG_TX_IQ_THETA_SFT	include/ssv6200_aux.h	15473;"	d
+RG_TX_IQ_THETA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27243;"	d
+RG_TX_IQ_THETA_SZ	include/ssv6200_aux.h	15475;"	d
+RG_TX_IQ_THETA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27245;"	d
+RG_TX_I_DC_HI	include/ssv6200_aux.h	15464;"	d
+RG_TX_I_DC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29019;"	d
+RG_TX_I_DC_I_MSK	include/ssv6200_aux.h	15462;"	d
+RG_TX_I_DC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29017;"	d
+RG_TX_I_DC_MSK	include/ssv6200_aux.h	15461;"	d
+RG_TX_I_DC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29016;"	d
+RG_TX_I_DC_SFT	include/ssv6200_aux.h	15463;"	d
+RG_TX_I_DC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29018;"	d
+RG_TX_I_DC_SZ	include/ssv6200_aux.h	15465;"	d
+RG_TX_I_DC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29020;"	d
+RG_TX_I_OFFSET_HI	include/ssv6200_aux.h	15489;"	d
+RG_TX_I_OFFSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29029;"	d
+RG_TX_I_OFFSET_I_MSK	include/ssv6200_aux.h	15487;"	d
+RG_TX_I_OFFSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29027;"	d
+RG_TX_I_OFFSET_MSK	include/ssv6200_aux.h	15486;"	d
+RG_TX_I_OFFSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29026;"	d
+RG_TX_I_OFFSET_SFT	include/ssv6200_aux.h	15488;"	d
+RG_TX_I_OFFSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29028;"	d
+RG_TX_I_OFFSET_SZ	include/ssv6200_aux.h	15490;"	d
+RG_TX_I_OFFSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29030;"	d
+RG_TX_I_SCALE_HI	include/ssv6200_aux.h	15434;"	d
+RG_TX_I_SCALE_I_MSK	include/ssv6200_aux.h	15432;"	d
+RG_TX_I_SCALE_MSK	include/ssv6200_aux.h	15431;"	d
+RG_TX_I_SCALE_SFT	include/ssv6200_aux.h	15433;"	d
+RG_TX_I_SCALE_SZ	include/ssv6200_aux.h	15435;"	d
+RG_TX_LDO_TX_LEVEL_HI	include/ssv6200_aux.h	16324;"	d
+RG_TX_LDO_TX_LEVEL_I_MSK	include/ssv6200_aux.h	16322;"	d
+RG_TX_LDO_TX_LEVEL_MSK	include/ssv6200_aux.h	16321;"	d
+RG_TX_LDO_TX_LEVEL_SFT	include/ssv6200_aux.h	16323;"	d
+RG_TX_LDO_TX_LEVEL_SZ	include/ssv6200_aux.h	16325;"	d
+RG_TX_LOBUF_VSET_HI	include/ssv6200_aux.h	16524;"	d
+RG_TX_LOBUF_VSET_I_MSK	include/ssv6200_aux.h	16522;"	d
+RG_TX_LOBUF_VSET_MSK	include/ssv6200_aux.h	16521;"	d
+RG_TX_LOBUF_VSET_SFT	include/ssv6200_aux.h	16523;"	d
+RG_TX_LOBUF_VSET_SZ	include/ssv6200_aux.h	16525;"	d
+RG_TX_MOD_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21744;"	d
+RG_TX_MOD_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21742;"	d
+RG_TX_MOD_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21741;"	d
+RG_TX_MOD_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21743;"	d
+RG_TX_MOD_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21745;"	d
+RG_TX_PA_EN_HI	include/ssv6200_aux.h	16069;"	d
+RG_TX_PA_EN_I_MSK	include/ssv6200_aux.h	16067;"	d
+RG_TX_PA_EN_MSK	include/ssv6200_aux.h	16066;"	d
+RG_TX_PA_EN_SFT	include/ssv6200_aux.h	16068;"	d
+RG_TX_PA_EN_SZ	include/ssv6200_aux.h	16070;"	d
+RG_TX_PA_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21734;"	d
+RG_TX_PA_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21732;"	d
+RG_TX_PA_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21731;"	d
+RG_TX_PA_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21733;"	d
+RG_TX_PA_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21735;"	d
+RG_TX_Q_DC_HI	include/ssv6200_aux.h	15469;"	d
+RG_TX_Q_DC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29024;"	d
+RG_TX_Q_DC_I_MSK	include/ssv6200_aux.h	15467;"	d
+RG_TX_Q_DC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29022;"	d
+RG_TX_Q_DC_MSK	include/ssv6200_aux.h	15466;"	d
+RG_TX_Q_DC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29021;"	d
+RG_TX_Q_DC_SFT	include/ssv6200_aux.h	15468;"	d
+RG_TX_Q_DC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29023;"	d
+RG_TX_Q_DC_SZ	include/ssv6200_aux.h	15470;"	d
+RG_TX_Q_DC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29025;"	d
+RG_TX_Q_OFFSET_HI	include/ssv6200_aux.h	15494;"	d
+RG_TX_Q_OFFSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29034;"	d
+RG_TX_Q_OFFSET_I_MSK	include/ssv6200_aux.h	15492;"	d
+RG_TX_Q_OFFSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29032;"	d
+RG_TX_Q_OFFSET_MSK	include/ssv6200_aux.h	15491;"	d
+RG_TX_Q_OFFSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29031;"	d
+RG_TX_Q_OFFSET_SFT	include/ssv6200_aux.h	15493;"	d
+RG_TX_Q_OFFSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29033;"	d
+RG_TX_Q_OFFSET_SZ	include/ssv6200_aux.h	15495;"	d
+RG_TX_Q_OFFSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29035;"	d
+RG_TX_Q_SCALE_HI	include/ssv6200_aux.h	15439;"	d
+RG_TX_Q_SCALE_I_MSK	include/ssv6200_aux.h	15437;"	d
+RG_TX_Q_SCALE_MSK	include/ssv6200_aux.h	15436;"	d
+RG_TX_Q_SCALE_SFT	include/ssv6200_aux.h	15438;"	d
+RG_TX_Q_SCALE_SZ	include/ssv6200_aux.h	15440;"	d
+RG_TX_SCALE_11B_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29339;"	d
+RG_TX_SCALE_11B_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29337;"	d
+RG_TX_SCALE_11B_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29336;"	d
+RG_TX_SCALE_11B_P0D5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29344;"	d
+RG_TX_SCALE_11B_P0D5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29342;"	d
+RG_TX_SCALE_11B_P0D5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29341;"	d
+RG_TX_SCALE_11B_P0D5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29343;"	d
+RG_TX_SCALE_11B_P0D5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29345;"	d
+RG_TX_SCALE_11B_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29338;"	d
+RG_TX_SCALE_11B_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29340;"	d
+RG_TX_SCALE_11G_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29349;"	d
+RG_TX_SCALE_11G_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29347;"	d
+RG_TX_SCALE_11G_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29346;"	d
+RG_TX_SCALE_11G_P0D5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29354;"	d
+RG_TX_SCALE_11G_P0D5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29352;"	d
+RG_TX_SCALE_11G_P0D5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29351;"	d
+RG_TX_SCALE_11G_P0D5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29353;"	d
+RG_TX_SCALE_11G_P0D5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29355;"	d
+RG_TX_SCALE_11G_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29348;"	d
+RG_TX_SCALE_11G_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29350;"	d
+RG_TX_SCALE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28999;"	d
+RG_TX_SCALE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28997;"	d
+RG_TX_SCALE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28996;"	d
+RG_TX_SCALE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28998;"	d
+RG_TX_SCALE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29000;"	d
+RG_TX_SELF_MIXER_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21839;"	d
+RG_TX_SELF_MIXER_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21837;"	d
+RG_TX_SELF_MIXER_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21836;"	d
+RG_TX_SELF_MIXER_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21838;"	d
+RG_TX_SELF_MIXER_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21840;"	d
+RG_TX_SGN_OUT_HI	include/ssv6200_aux.h	15449;"	d
+RG_TX_SGN_OUT_I_MSK	include/ssv6200_aux.h	15447;"	d
+RG_TX_SGN_OUT_MSK	include/ssv6200_aux.h	15446;"	d
+RG_TX_SGN_OUT_SFT	include/ssv6200_aux.h	15448;"	d
+RG_TX_SGN_OUT_SZ	include/ssv6200_aux.h	15450;"	d
+RG_TX_START_HI	include/ssv6200_aux.h	13214;"	d
+RG_TX_START_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30409;"	d
+RG_TX_START_I_MSK	include/ssv6200_aux.h	13212;"	d
+RG_TX_START_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30407;"	d
+RG_TX_START_MSK	include/ssv6200_aux.h	13211;"	d
+RG_TX_START_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30406;"	d
+RG_TX_START_SFT	include/ssv6200_aux.h	13213;"	d
+RG_TX_START_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30408;"	d
+RG_TX_START_SZ	include/ssv6200_aux.h	13215;"	d
+RG_TX_START_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30410;"	d
+RG_TX_TIME_EXT_HI	include/ssv6200_aux.h	15084;"	d
+RG_TX_TIME_EXT_I_MSK	include/ssv6200_aux.h	15082;"	d
+RG_TX_TIME_EXT_MSK	include/ssv6200_aux.h	15081;"	d
+RG_TX_TIME_EXT_SFT	include/ssv6200_aux.h	15083;"	d
+RG_TX_TIME_EXT_SZ	include/ssv6200_aux.h	15085;"	d
+RG_TX_TRSW_MANUAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21644;"	d
+RG_TX_TRSW_MANUAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21642;"	d
+RG_TX_TRSW_MANUAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21641;"	d
+RG_TX_TRSW_MANUAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21643;"	d
+RG_TX_TRSW_MANUAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21645;"	d
+RG_TX_TSSI_BIAS_HI	include/ssv6200_aux.h	16554;"	d
+RG_TX_TSSI_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22259;"	d
+RG_TX_TSSI_BIAS_I_MSK	include/ssv6200_aux.h	16552;"	d
+RG_TX_TSSI_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22257;"	d
+RG_TX_TSSI_BIAS_MSK	include/ssv6200_aux.h	16551;"	d
+RG_TX_TSSI_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22256;"	d
+RG_TX_TSSI_BIAS_SFT	include/ssv6200_aux.h	16553;"	d
+RG_TX_TSSI_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22258;"	d
+RG_TX_TSSI_BIAS_SZ	include/ssv6200_aux.h	16555;"	d
+RG_TX_TSSI_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22260;"	d
+RG_TX_TSSI_DIV_HI	include/ssv6200_aux.h	16559;"	d
+RG_TX_TSSI_DIV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22264;"	d
+RG_TX_TSSI_DIV_I_MSK	include/ssv6200_aux.h	16557;"	d
+RG_TX_TSSI_DIV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22262;"	d
+RG_TX_TSSI_DIV_MSK	include/ssv6200_aux.h	16556;"	d
+RG_TX_TSSI_DIV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22261;"	d
+RG_TX_TSSI_DIV_SFT	include/ssv6200_aux.h	16558;"	d
+RG_TX_TSSI_DIV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22263;"	d
+RG_TX_TSSI_DIV_SZ	include/ssv6200_aux.h	16560;"	d
+RG_TX_TSSI_DIV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22265;"	d
+RG_TX_TSSI_TESTMODE_HI	include/ssv6200_aux.h	16564;"	d
+RG_TX_TSSI_TESTMODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22274;"	d
+RG_TX_TSSI_TESTMODE_I_MSK	include/ssv6200_aux.h	16562;"	d
+RG_TX_TSSI_TESTMODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22272;"	d
+RG_TX_TSSI_TESTMODE_MSK	include/ssv6200_aux.h	16561;"	d
+RG_TX_TSSI_TESTMODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22271;"	d
+RG_TX_TSSI_TESTMODE_SFT	include/ssv6200_aux.h	16563;"	d
+RG_TX_TSSI_TESTMODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22273;"	d
+RG_TX_TSSI_TESTMODE_SZ	include/ssv6200_aux.h	16565;"	d
+RG_TX_TSSI_TESTMODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22275;"	d
+RG_TX_TSSI_TEST_HI	include/ssv6200_aux.h	16569;"	d
+RG_TX_TSSI_TEST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22269;"	d
+RG_TX_TSSI_TEST_I_MSK	include/ssv6200_aux.h	16567;"	d
+RG_TX_TSSI_TEST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22267;"	d
+RG_TX_TSSI_TEST_MSK	include/ssv6200_aux.h	16566;"	d
+RG_TX_TSSI_TEST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22266;"	d
+RG_TX_TSSI_TEST_SFT	include/ssv6200_aux.h	16568;"	d
+RG_TX_TSSI_TEST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22268;"	d
+RG_TX_TSSI_TEST_SZ	include/ssv6200_aux.h	16570;"	d
+RG_TX_TSSI_TEST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22270;"	d
+RG_TX_UP8X_MAN_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27284;"	d
+RG_TX_UP8X_MAN_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27282;"	d
+RG_TX_UP8X_MAN_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27281;"	d
+RG_TX_UP8X_MAN_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27283;"	d
+RG_TX_UP8X_MAN_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27285;"	d
+RG_TX_VTOI_CURRENT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22419;"	d
+RG_TX_VTOI_CURRENT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22417;"	d
+RG_TX_VTOI_CURRENT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22416;"	d
+RG_TX_VTOI_CURRENT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22418;"	d
+RG_TX_VTOI_CURRENT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22420;"	d
+RG_TX_VTOI_FS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22434;"	d
+RG_TX_VTOI_FS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22432;"	d
+RG_TX_VTOI_FS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22431;"	d
+RG_TX_VTOI_FS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22433;"	d
+RG_TX_VTOI_FS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22435;"	d
+RG_TX_VTOI_GM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22424;"	d
+RG_TX_VTOI_GM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22422;"	d
+RG_TX_VTOI_GM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22421;"	d
+RG_TX_VTOI_GM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22423;"	d
+RG_TX_VTOI_GM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22425;"	d
+RG_TX_VTOI_OPTION_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22429;"	d
+RG_TX_VTOI_OPTION_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22427;"	d
+RG_TX_VTOI_OPTION_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22426;"	d
+RG_TX_VTOI_OPTION_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22428;"	d
+RG_TX_VTOI_OPTION_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22430;"	d
+RG_ULG_PGA_SAT_PGA_GAIN_HI	include/ssv6200_aux.h	13359;"	d
+RG_ULG_PGA_SAT_PGA_GAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30549;"	d
+RG_ULG_PGA_SAT_PGA_GAIN_I_MSK	include/ssv6200_aux.h	13357;"	d
+RG_ULG_PGA_SAT_PGA_GAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30547;"	d
+RG_ULG_PGA_SAT_PGA_GAIN_MSK	include/ssv6200_aux.h	13356;"	d
+RG_ULG_PGA_SAT_PGA_GAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30546;"	d
+RG_ULG_PGA_SAT_PGA_GAIN_SFT	include/ssv6200_aux.h	13358;"	d
+RG_ULG_PGA_SAT_PGA_GAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30548;"	d
+RG_ULG_PGA_SAT_PGA_GAIN_SZ	include/ssv6200_aux.h	13360;"	d
+RG_ULG_PGA_SAT_PGA_GAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30550;"	d
+RG_UP8X_HI	include/ssv6200_aux.h	13264;"	d
+RG_UP8X_I_MSK	include/ssv6200_aux.h	13262;"	d
+RG_UP8X_MSK	include/ssv6200_aux.h	13261;"	d
+RG_UP8X_SFT	include/ssv6200_aux.h	13263;"	d
+RG_UP8X_SZ	include/ssv6200_aux.h	13265;"	d
+RG_VITERBI_AB_SWAP_HI	include/ssv6200_aux.h	14844;"	d
+RG_VITERBI_AB_SWAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32084;"	d
+RG_VITERBI_AB_SWAP_I_MSK	include/ssv6200_aux.h	14842;"	d
+RG_VITERBI_AB_SWAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32082;"	d
+RG_VITERBI_AB_SWAP_MSK	include/ssv6200_aux.h	14841;"	d
+RG_VITERBI_AB_SWAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32081;"	d
+RG_VITERBI_AB_SWAP_SFT	include/ssv6200_aux.h	14843;"	d
+RG_VITERBI_AB_SWAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32083;"	d
+RG_VITERBI_AB_SWAP_SZ	include/ssv6200_aux.h	14845;"	d
+RG_VITERBI_AB_SWAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32085;"	d
+RG_VITERBI_TB_BITS_HI	include/ssv6200_aux.h	15004;"	d
+RG_VITERBI_TB_BITS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32464;"	d
+RG_VITERBI_TB_BITS_I_MSK	include/ssv6200_aux.h	15002;"	d
+RG_VITERBI_TB_BITS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32462;"	d
+RG_VITERBI_TB_BITS_MSK	include/ssv6200_aux.h	15001;"	d
+RG_VITERBI_TB_BITS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32461;"	d
+RG_VITERBI_TB_BITS_SFT	include/ssv6200_aux.h	15003;"	d
+RG_VITERBI_TB_BITS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32463;"	d
+RG_VITERBI_TB_BITS_SZ	include/ssv6200_aux.h	15005;"	d
+RG_VITERBI_TB_BITS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32465;"	d
+RG_VO5GB_AAC_IMAX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26219;"	d
+RG_VO5GB_AAC_IMAX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26217;"	d
+RG_VO5GB_AAC_IMAX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26216;"	d
+RG_VO5GB_AAC_IMAX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26218;"	d
+RG_VO5GB_AAC_IMAX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26220;"	d
+RG_VO5GB_AAC_IOST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	26214;"	d
+RG_VO5GB_AAC_IOST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26212;"	d
+RG_VO5GB_AAC_IOST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	26211;"	d
+RG_VO5GB_AAC_IOST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	26213;"	d
+RG_VO5GB_AAC_IOST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	26215;"	d
+RG_VOBF_CAPIMB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23644;"	d
+RG_VOBF_CAPIMB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23642;"	d
+RG_VOBF_CAPIMB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23641;"	d
+RG_VOBF_CAPIMB_POL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23639;"	d
+RG_VOBF_CAPIMB_POL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23637;"	d
+RG_VOBF_CAPIMB_POL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23636;"	d
+RG_VOBF_CAPIMB_POL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23638;"	d
+RG_VOBF_CAPIMB_POL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23640;"	d
+RG_VOBF_CAPIMB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23643;"	d
+RG_VOBF_CAPIMB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23645;"	d
+RG_VOBF_DIVBFSEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23624;"	d
+RG_VOBF_DIVBFSEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23622;"	d
+RG_VOBF_DIVBFSEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23621;"	d
+RG_VOBF_DIVBFSEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23623;"	d
+RG_VOBF_DIVBFSEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23625;"	d
+RG_VOBF_RXMBSEL_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23594;"	d
+RG_VOBF_RXMBSEL_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23592;"	d
+RG_VOBF_RXMBSEL_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23591;"	d
+RG_VOBF_RXMBSEL_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23593;"	d
+RG_VOBF_RXMBSEL_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23595;"	d
+RG_VOBF_RXMBSEL_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23614;"	d
+RG_VOBF_RXMBSEL_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23612;"	d
+RG_VOBF_RXMBSEL_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23611;"	d
+RG_VOBF_RXMBSEL_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23613;"	d
+RG_VOBF_RXMBSEL_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23615;"	d
+RG_VOBF_RXOBSEL_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23599;"	d
+RG_VOBF_RXOBSEL_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23597;"	d
+RG_VOBF_RXOBSEL_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23596;"	d
+RG_VOBF_RXOBSEL_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23598;"	d
+RG_VOBF_RXOBSEL_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23600;"	d
+RG_VOBF_RXOBSEL_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23619;"	d
+RG_VOBF_RXOBSEL_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23617;"	d
+RG_VOBF_RXOBSEL_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23616;"	d
+RG_VOBF_RXOBSEL_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23618;"	d
+RG_VOBF_RXOBSEL_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23620;"	d
+RG_VOBF_TXMBSEL_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23584;"	d
+RG_VOBF_TXMBSEL_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23582;"	d
+RG_VOBF_TXMBSEL_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23581;"	d
+RG_VOBF_TXMBSEL_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23583;"	d
+RG_VOBF_TXMBSEL_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23585;"	d
+RG_VOBF_TXMBSEL_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23604;"	d
+RG_VOBF_TXMBSEL_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23602;"	d
+RG_VOBF_TXMBSEL_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23601;"	d
+RG_VOBF_TXMBSEL_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23603;"	d
+RG_VOBF_TXMBSEL_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23605;"	d
+RG_VOBF_TXOBSEL_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23589;"	d
+RG_VOBF_TXOBSEL_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23587;"	d
+RG_VOBF_TXOBSEL_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23586;"	d
+RG_VOBF_TXOBSEL_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23588;"	d
+RG_VOBF_TXOBSEL_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23590;"	d
+RG_VOBF_TXOBSEL_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23609;"	d
+RG_VOBF_TXOBSEL_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23607;"	d
+RG_VOBF_TXOBSEL_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23606;"	d
+RG_VOBF_TXOBSEL_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23608;"	d
+RG_VOBF_TXOBSEL_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23610;"	d
+RG_VO_AAC_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23779;"	d
+RG_VO_AAC_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23777;"	d
+RG_VO_AAC_EN_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23774;"	d
+RG_VO_AAC_EN_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23772;"	d
+RG_VO_AAC_EN_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23771;"	d
+RG_VO_AAC_EN_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23773;"	d
+RG_VO_AAC_EN_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23775;"	d
+RG_VO_AAC_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23776;"	d
+RG_VO_AAC_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23778;"	d
+RG_VO_AAC_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23780;"	d
+RG_VO_AAC_EVA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23789;"	d
+RG_VO_AAC_EVA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23787;"	d
+RG_VO_AAC_EVA_MAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23784;"	d
+RG_VO_AAC_EVA_MAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23782;"	d
+RG_VO_AAC_EVA_MAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23781;"	d
+RG_VO_AAC_EVA_MAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23783;"	d
+RG_VO_AAC_EVA_MAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23785;"	d
+RG_VO_AAC_EVA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23786;"	d
+RG_VO_AAC_EVA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23788;"	d
+RG_VO_AAC_EVA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23790;"	d
+RG_VO_AAC_EVA_TS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23769;"	d
+RG_VO_AAC_EVA_TS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23767;"	d
+RG_VO_AAC_EVA_TS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23766;"	d
+RG_VO_AAC_EVA_TS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23768;"	d
+RG_VO_AAC_EVA_TS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23770;"	d
+RG_VO_AAC_IMAX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23759;"	d
+RG_VO_AAC_IMAX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23757;"	d
+RG_VO_AAC_IMAX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23756;"	d
+RG_VO_AAC_IMAX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23758;"	d
+RG_VO_AAC_IMAX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23760;"	d
+RG_VO_AAC_INIT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23764;"	d
+RG_VO_AAC_INIT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23762;"	d
+RG_VO_AAC_INIT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23761;"	d
+RG_VO_AAC_INIT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23763;"	d
+RG_VO_AAC_INIT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23765;"	d
+RG_VO_AAC_IOST_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23744;"	d
+RG_VO_AAC_IOST_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23742;"	d
+RG_VO_AAC_IOST_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23741;"	d
+RG_VO_AAC_IOST_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23743;"	d
+RG_VO_AAC_IOST_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23745;"	d
+RG_VO_AAC_IOST_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23754;"	d
+RG_VO_AAC_IOST_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23752;"	d
+RG_VO_AAC_IOST_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23751;"	d
+RG_VO_AAC_IOST_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23753;"	d
+RG_VO_AAC_IOST_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23755;"	d
+RG_VO_AAC_TAR_BT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23739;"	d
+RG_VO_AAC_TAR_BT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23737;"	d
+RG_VO_AAC_TAR_BT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23736;"	d
+RG_VO_AAC_TAR_BT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23738;"	d
+RG_VO_AAC_TAR_BT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23740;"	d
+RG_VO_AAC_TAR_WF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23749;"	d
+RG_VO_AAC_TAR_WF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23747;"	d
+RG_VO_AAC_TAR_WF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23746;"	d
+RG_VO_AAC_TAR_WF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23748;"	d
+RG_VO_AAC_TAR_WF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23750;"	d
+RG_VO_AAC_TEST_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23794;"	d
+RG_VO_AAC_TEST_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23792;"	d
+RG_VO_AAC_TEST_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23791;"	d
+RG_VO_AAC_TEST_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23793;"	d
+RG_VO_AAC_TEST_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23795;"	d
+RG_VO_AAC_TEST_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23799;"	d
+RG_VO_AAC_TEST_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23797;"	d
+RG_VO_AAC_TEST_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23796;"	d
+RG_VO_AAC_TEST_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23798;"	d
+RG_VO_AAC_TEST_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23800;"	d
+RG_WAIT_T_FINAL_HI	include/ssv6200_aux.h	13349;"	d
+RG_WAIT_T_FINAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30539;"	d
+RG_WAIT_T_FINAL_I_MSK	include/ssv6200_aux.h	13347;"	d
+RG_WAIT_T_FINAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30537;"	d
+RG_WAIT_T_FINAL_MSK	include/ssv6200_aux.h	13346;"	d
+RG_WAIT_T_FINAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30536;"	d
+RG_WAIT_T_FINAL_SFT	include/ssv6200_aux.h	13348;"	d
+RG_WAIT_T_FINAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30538;"	d
+RG_WAIT_T_FINAL_SZ	include/ssv6200_aux.h	13350;"	d
+RG_WAIT_T_FINAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30540;"	d
+RG_WAIT_T_HI	include/ssv6200_aux.h	13354;"	d
+RG_WAIT_T_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30544;"	d
+RG_WAIT_T_I_MSK	include/ssv6200_aux.h	13352;"	d
+RG_WAIT_T_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30542;"	d
+RG_WAIT_T_MSK	include/ssv6200_aux.h	13351;"	d
+RG_WAIT_T_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30541;"	d
+RG_WAIT_T_RXAGC_HI	include/ssv6200_aux.h	13334;"	d
+RG_WAIT_T_RXAGC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30524;"	d
+RG_WAIT_T_RXAGC_I_MSK	include/ssv6200_aux.h	13332;"	d
+RG_WAIT_T_RXAGC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30522;"	d
+RG_WAIT_T_RXAGC_MSK	include/ssv6200_aux.h	13331;"	d
+RG_WAIT_T_RXAGC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30521;"	d
+RG_WAIT_T_RXAGC_SFT	include/ssv6200_aux.h	13333;"	d
+RG_WAIT_T_RXAGC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30523;"	d
+RG_WAIT_T_RXAGC_SZ	include/ssv6200_aux.h	13335;"	d
+RG_WAIT_T_RXAGC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30525;"	d
+RG_WAIT_T_SFT	include/ssv6200_aux.h	13353;"	d
+RG_WAIT_T_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30543;"	d
+RG_WAIT_T_SZ	include/ssv6200_aux.h	13355;"	d
+RG_WAIT_T_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30545;"	d
+RG_WF_BTPASW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22359;"	d
+RG_WF_BTPASW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22357;"	d
+RG_WF_BTPASW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22356;"	d
+RG_WF_BTPASW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22358;"	d
+RG_WF_BTPASW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22360;"	d
+RG_WF_IDACAI_TZ0_PGAG0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24014;"	d
+RG_WF_IDACAI_TZ0_PGAG0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24012;"	d
+RG_WF_IDACAI_TZ0_PGAG0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24011;"	d
+RG_WF_IDACAI_TZ0_PGAG0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24013;"	d
+RG_WF_IDACAI_TZ0_PGAG0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24015;"	d
+RG_WF_IDACAI_TZ0_PGAG10_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23914;"	d
+RG_WF_IDACAI_TZ0_PGAG10_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23912;"	d
+RG_WF_IDACAI_TZ0_PGAG10_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23911;"	d
+RG_WF_IDACAI_TZ0_PGAG10_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23913;"	d
+RG_WF_IDACAI_TZ0_PGAG10_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23915;"	d
+RG_WF_IDACAI_TZ0_PGAG11_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23904;"	d
+RG_WF_IDACAI_TZ0_PGAG11_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23902;"	d
+RG_WF_IDACAI_TZ0_PGAG11_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23901;"	d
+RG_WF_IDACAI_TZ0_PGAG11_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23903;"	d
+RG_WF_IDACAI_TZ0_PGAG11_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23905;"	d
+RG_WF_IDACAI_TZ0_PGAG12_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23894;"	d
+RG_WF_IDACAI_TZ0_PGAG12_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23892;"	d
+RG_WF_IDACAI_TZ0_PGAG12_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23891;"	d
+RG_WF_IDACAI_TZ0_PGAG12_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23893;"	d
+RG_WF_IDACAI_TZ0_PGAG12_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23895;"	d
+RG_WF_IDACAI_TZ0_PGAG13_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23884;"	d
+RG_WF_IDACAI_TZ0_PGAG13_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23882;"	d
+RG_WF_IDACAI_TZ0_PGAG13_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23881;"	d
+RG_WF_IDACAI_TZ0_PGAG13_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23883;"	d
+RG_WF_IDACAI_TZ0_PGAG13_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23885;"	d
+RG_WF_IDACAI_TZ0_PGAG14_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23874;"	d
+RG_WF_IDACAI_TZ0_PGAG14_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23872;"	d
+RG_WF_IDACAI_TZ0_PGAG14_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23871;"	d
+RG_WF_IDACAI_TZ0_PGAG14_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23873;"	d
+RG_WF_IDACAI_TZ0_PGAG14_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23875;"	d
+RG_WF_IDACAI_TZ0_PGAG15_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23864;"	d
+RG_WF_IDACAI_TZ0_PGAG15_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23862;"	d
+RG_WF_IDACAI_TZ0_PGAG15_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23861;"	d
+RG_WF_IDACAI_TZ0_PGAG15_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23863;"	d
+RG_WF_IDACAI_TZ0_PGAG15_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23865;"	d
+RG_WF_IDACAI_TZ0_PGAG1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24004;"	d
+RG_WF_IDACAI_TZ0_PGAG1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24002;"	d
+RG_WF_IDACAI_TZ0_PGAG1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24001;"	d
+RG_WF_IDACAI_TZ0_PGAG1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24003;"	d
+RG_WF_IDACAI_TZ0_PGAG1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24005;"	d
+RG_WF_IDACAI_TZ0_PGAG2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23994;"	d
+RG_WF_IDACAI_TZ0_PGAG2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23992;"	d
+RG_WF_IDACAI_TZ0_PGAG2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23991;"	d
+RG_WF_IDACAI_TZ0_PGAG2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23993;"	d
+RG_WF_IDACAI_TZ0_PGAG2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23995;"	d
+RG_WF_IDACAI_TZ0_PGAG3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23984;"	d
+RG_WF_IDACAI_TZ0_PGAG3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23982;"	d
+RG_WF_IDACAI_TZ0_PGAG3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23981;"	d
+RG_WF_IDACAI_TZ0_PGAG3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23983;"	d
+RG_WF_IDACAI_TZ0_PGAG3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23985;"	d
+RG_WF_IDACAI_TZ0_PGAG4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23974;"	d
+RG_WF_IDACAI_TZ0_PGAG4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23972;"	d
+RG_WF_IDACAI_TZ0_PGAG4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23971;"	d
+RG_WF_IDACAI_TZ0_PGAG4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23973;"	d
+RG_WF_IDACAI_TZ0_PGAG4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23975;"	d
+RG_WF_IDACAI_TZ0_PGAG5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23964;"	d
+RG_WF_IDACAI_TZ0_PGAG5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23962;"	d
+RG_WF_IDACAI_TZ0_PGAG5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23961;"	d
+RG_WF_IDACAI_TZ0_PGAG5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23963;"	d
+RG_WF_IDACAI_TZ0_PGAG5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23965;"	d
+RG_WF_IDACAI_TZ0_PGAG6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23954;"	d
+RG_WF_IDACAI_TZ0_PGAG6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23952;"	d
+RG_WF_IDACAI_TZ0_PGAG6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23951;"	d
+RG_WF_IDACAI_TZ0_PGAG6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23953;"	d
+RG_WF_IDACAI_TZ0_PGAG6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23955;"	d
+RG_WF_IDACAI_TZ0_PGAG7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23944;"	d
+RG_WF_IDACAI_TZ0_PGAG7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23942;"	d
+RG_WF_IDACAI_TZ0_PGAG7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23941;"	d
+RG_WF_IDACAI_TZ0_PGAG7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23943;"	d
+RG_WF_IDACAI_TZ0_PGAG7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23945;"	d
+RG_WF_IDACAI_TZ0_PGAG8_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23934;"	d
+RG_WF_IDACAI_TZ0_PGAG8_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23932;"	d
+RG_WF_IDACAI_TZ0_PGAG8_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23931;"	d
+RG_WF_IDACAI_TZ0_PGAG8_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23933;"	d
+RG_WF_IDACAI_TZ0_PGAG8_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23935;"	d
+RG_WF_IDACAI_TZ0_PGAG9_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23924;"	d
+RG_WF_IDACAI_TZ0_PGAG9_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23922;"	d
+RG_WF_IDACAI_TZ0_PGAG9_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23921;"	d
+RG_WF_IDACAI_TZ0_PGAG9_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23923;"	d
+RG_WF_IDACAI_TZ0_PGAG9_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23925;"	d
+RG_WF_IDACAI_TZ1_PGAG0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24174;"	d
+RG_WF_IDACAI_TZ1_PGAG0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24172;"	d
+RG_WF_IDACAI_TZ1_PGAG0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24171;"	d
+RG_WF_IDACAI_TZ1_PGAG0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24173;"	d
+RG_WF_IDACAI_TZ1_PGAG0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24175;"	d
+RG_WF_IDACAI_TZ1_PGAG10_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24074;"	d
+RG_WF_IDACAI_TZ1_PGAG10_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24072;"	d
+RG_WF_IDACAI_TZ1_PGAG10_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24071;"	d
+RG_WF_IDACAI_TZ1_PGAG10_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24073;"	d
+RG_WF_IDACAI_TZ1_PGAG10_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24075;"	d
+RG_WF_IDACAI_TZ1_PGAG11_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24064;"	d
+RG_WF_IDACAI_TZ1_PGAG11_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24062;"	d
+RG_WF_IDACAI_TZ1_PGAG11_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24061;"	d
+RG_WF_IDACAI_TZ1_PGAG11_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24063;"	d
+RG_WF_IDACAI_TZ1_PGAG11_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24065;"	d
+RG_WF_IDACAI_TZ1_PGAG12_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24054;"	d
+RG_WF_IDACAI_TZ1_PGAG12_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24052;"	d
+RG_WF_IDACAI_TZ1_PGAG12_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24051;"	d
+RG_WF_IDACAI_TZ1_PGAG12_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24053;"	d
+RG_WF_IDACAI_TZ1_PGAG12_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24055;"	d
+RG_WF_IDACAI_TZ1_PGAG13_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24044;"	d
+RG_WF_IDACAI_TZ1_PGAG13_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24042;"	d
+RG_WF_IDACAI_TZ1_PGAG13_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24041;"	d
+RG_WF_IDACAI_TZ1_PGAG13_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24043;"	d
+RG_WF_IDACAI_TZ1_PGAG13_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24045;"	d
+RG_WF_IDACAI_TZ1_PGAG14_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24034;"	d
+RG_WF_IDACAI_TZ1_PGAG14_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24032;"	d
+RG_WF_IDACAI_TZ1_PGAG14_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24031;"	d
+RG_WF_IDACAI_TZ1_PGAG14_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24033;"	d
+RG_WF_IDACAI_TZ1_PGAG14_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24035;"	d
+RG_WF_IDACAI_TZ1_PGAG15_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24024;"	d
+RG_WF_IDACAI_TZ1_PGAG15_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24022;"	d
+RG_WF_IDACAI_TZ1_PGAG15_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24021;"	d
+RG_WF_IDACAI_TZ1_PGAG15_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24023;"	d
+RG_WF_IDACAI_TZ1_PGAG15_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24025;"	d
+RG_WF_IDACAI_TZ1_PGAG1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24164;"	d
+RG_WF_IDACAI_TZ1_PGAG1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24162;"	d
+RG_WF_IDACAI_TZ1_PGAG1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24161;"	d
+RG_WF_IDACAI_TZ1_PGAG1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24163;"	d
+RG_WF_IDACAI_TZ1_PGAG1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24165;"	d
+RG_WF_IDACAI_TZ1_PGAG2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24154;"	d
+RG_WF_IDACAI_TZ1_PGAG2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24152;"	d
+RG_WF_IDACAI_TZ1_PGAG2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24151;"	d
+RG_WF_IDACAI_TZ1_PGAG2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24153;"	d
+RG_WF_IDACAI_TZ1_PGAG2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24155;"	d
+RG_WF_IDACAI_TZ1_PGAG3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24144;"	d
+RG_WF_IDACAI_TZ1_PGAG3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24142;"	d
+RG_WF_IDACAI_TZ1_PGAG3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24141;"	d
+RG_WF_IDACAI_TZ1_PGAG3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24143;"	d
+RG_WF_IDACAI_TZ1_PGAG3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24145;"	d
+RG_WF_IDACAI_TZ1_PGAG4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24134;"	d
+RG_WF_IDACAI_TZ1_PGAG4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24132;"	d
+RG_WF_IDACAI_TZ1_PGAG4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24131;"	d
+RG_WF_IDACAI_TZ1_PGAG4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24133;"	d
+RG_WF_IDACAI_TZ1_PGAG4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24135;"	d
+RG_WF_IDACAI_TZ1_PGAG5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24124;"	d
+RG_WF_IDACAI_TZ1_PGAG5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24122;"	d
+RG_WF_IDACAI_TZ1_PGAG5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24121;"	d
+RG_WF_IDACAI_TZ1_PGAG5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24123;"	d
+RG_WF_IDACAI_TZ1_PGAG5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24125;"	d
+RG_WF_IDACAI_TZ1_PGAG6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24114;"	d
+RG_WF_IDACAI_TZ1_PGAG6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24112;"	d
+RG_WF_IDACAI_TZ1_PGAG6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24111;"	d
+RG_WF_IDACAI_TZ1_PGAG6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24113;"	d
+RG_WF_IDACAI_TZ1_PGAG6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24115;"	d
+RG_WF_IDACAI_TZ1_PGAG7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24104;"	d
+RG_WF_IDACAI_TZ1_PGAG7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24102;"	d
+RG_WF_IDACAI_TZ1_PGAG7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24101;"	d
+RG_WF_IDACAI_TZ1_PGAG7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24103;"	d
+RG_WF_IDACAI_TZ1_PGAG7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24105;"	d
+RG_WF_IDACAI_TZ1_PGAG8_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24094;"	d
+RG_WF_IDACAI_TZ1_PGAG8_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24092;"	d
+RG_WF_IDACAI_TZ1_PGAG8_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24091;"	d
+RG_WF_IDACAI_TZ1_PGAG8_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24093;"	d
+RG_WF_IDACAI_TZ1_PGAG8_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24095;"	d
+RG_WF_IDACAI_TZ1_PGAG9_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24084;"	d
+RG_WF_IDACAI_TZ1_PGAG9_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24082;"	d
+RG_WF_IDACAI_TZ1_PGAG9_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24081;"	d
+RG_WF_IDACAI_TZ1_PGAG9_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24083;"	d
+RG_WF_IDACAI_TZ1_PGAG9_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24085;"	d
+RG_WF_IDACAQ_TZ0_PGAG0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24019;"	d
+RG_WF_IDACAQ_TZ0_PGAG0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24017;"	d
+RG_WF_IDACAQ_TZ0_PGAG0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24016;"	d
+RG_WF_IDACAQ_TZ0_PGAG0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24018;"	d
+RG_WF_IDACAQ_TZ0_PGAG0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24020;"	d
+RG_WF_IDACAQ_TZ0_PGAG10_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23919;"	d
+RG_WF_IDACAQ_TZ0_PGAG10_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23917;"	d
+RG_WF_IDACAQ_TZ0_PGAG10_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23916;"	d
+RG_WF_IDACAQ_TZ0_PGAG10_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23918;"	d
+RG_WF_IDACAQ_TZ0_PGAG10_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23920;"	d
+RG_WF_IDACAQ_TZ0_PGAG11_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23909;"	d
+RG_WF_IDACAQ_TZ0_PGAG11_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23907;"	d
+RG_WF_IDACAQ_TZ0_PGAG11_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23906;"	d
+RG_WF_IDACAQ_TZ0_PGAG11_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23908;"	d
+RG_WF_IDACAQ_TZ0_PGAG11_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23910;"	d
+RG_WF_IDACAQ_TZ0_PGAG12_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23899;"	d
+RG_WF_IDACAQ_TZ0_PGAG12_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23897;"	d
+RG_WF_IDACAQ_TZ0_PGAG12_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23896;"	d
+RG_WF_IDACAQ_TZ0_PGAG12_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23898;"	d
+RG_WF_IDACAQ_TZ0_PGAG12_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23900;"	d
+RG_WF_IDACAQ_TZ0_PGAG13_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23889;"	d
+RG_WF_IDACAQ_TZ0_PGAG13_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23887;"	d
+RG_WF_IDACAQ_TZ0_PGAG13_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23886;"	d
+RG_WF_IDACAQ_TZ0_PGAG13_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23888;"	d
+RG_WF_IDACAQ_TZ0_PGAG13_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23890;"	d
+RG_WF_IDACAQ_TZ0_PGAG14_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23879;"	d
+RG_WF_IDACAQ_TZ0_PGAG14_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23877;"	d
+RG_WF_IDACAQ_TZ0_PGAG14_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23876;"	d
+RG_WF_IDACAQ_TZ0_PGAG14_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23878;"	d
+RG_WF_IDACAQ_TZ0_PGAG14_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23880;"	d
+RG_WF_IDACAQ_TZ0_PGAG15_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23869;"	d
+RG_WF_IDACAQ_TZ0_PGAG15_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23867;"	d
+RG_WF_IDACAQ_TZ0_PGAG15_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23866;"	d
+RG_WF_IDACAQ_TZ0_PGAG15_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23868;"	d
+RG_WF_IDACAQ_TZ0_PGAG15_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23870;"	d
+RG_WF_IDACAQ_TZ0_PGAG1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24009;"	d
+RG_WF_IDACAQ_TZ0_PGAG1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24007;"	d
+RG_WF_IDACAQ_TZ0_PGAG1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24006;"	d
+RG_WF_IDACAQ_TZ0_PGAG1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24008;"	d
+RG_WF_IDACAQ_TZ0_PGAG1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24010;"	d
+RG_WF_IDACAQ_TZ0_PGAG2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23999;"	d
+RG_WF_IDACAQ_TZ0_PGAG2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23997;"	d
+RG_WF_IDACAQ_TZ0_PGAG2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23996;"	d
+RG_WF_IDACAQ_TZ0_PGAG2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23998;"	d
+RG_WF_IDACAQ_TZ0_PGAG2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24000;"	d
+RG_WF_IDACAQ_TZ0_PGAG3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23989;"	d
+RG_WF_IDACAQ_TZ0_PGAG3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23987;"	d
+RG_WF_IDACAQ_TZ0_PGAG3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23986;"	d
+RG_WF_IDACAQ_TZ0_PGAG3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23988;"	d
+RG_WF_IDACAQ_TZ0_PGAG3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23990;"	d
+RG_WF_IDACAQ_TZ0_PGAG4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23979;"	d
+RG_WF_IDACAQ_TZ0_PGAG4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23977;"	d
+RG_WF_IDACAQ_TZ0_PGAG4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23976;"	d
+RG_WF_IDACAQ_TZ0_PGAG4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23978;"	d
+RG_WF_IDACAQ_TZ0_PGAG4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23980;"	d
+RG_WF_IDACAQ_TZ0_PGAG5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23969;"	d
+RG_WF_IDACAQ_TZ0_PGAG5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23967;"	d
+RG_WF_IDACAQ_TZ0_PGAG5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23966;"	d
+RG_WF_IDACAQ_TZ0_PGAG5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23968;"	d
+RG_WF_IDACAQ_TZ0_PGAG5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23970;"	d
+RG_WF_IDACAQ_TZ0_PGAG6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23959;"	d
+RG_WF_IDACAQ_TZ0_PGAG6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23957;"	d
+RG_WF_IDACAQ_TZ0_PGAG6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23956;"	d
+RG_WF_IDACAQ_TZ0_PGAG6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23958;"	d
+RG_WF_IDACAQ_TZ0_PGAG6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23960;"	d
+RG_WF_IDACAQ_TZ0_PGAG7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23949;"	d
+RG_WF_IDACAQ_TZ0_PGAG7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23947;"	d
+RG_WF_IDACAQ_TZ0_PGAG7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23946;"	d
+RG_WF_IDACAQ_TZ0_PGAG7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23948;"	d
+RG_WF_IDACAQ_TZ0_PGAG7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23950;"	d
+RG_WF_IDACAQ_TZ0_PGAG8_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23939;"	d
+RG_WF_IDACAQ_TZ0_PGAG8_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23937;"	d
+RG_WF_IDACAQ_TZ0_PGAG8_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23936;"	d
+RG_WF_IDACAQ_TZ0_PGAG8_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23938;"	d
+RG_WF_IDACAQ_TZ0_PGAG8_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23940;"	d
+RG_WF_IDACAQ_TZ0_PGAG9_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23929;"	d
+RG_WF_IDACAQ_TZ0_PGAG9_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23927;"	d
+RG_WF_IDACAQ_TZ0_PGAG9_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23926;"	d
+RG_WF_IDACAQ_TZ0_PGAG9_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23928;"	d
+RG_WF_IDACAQ_TZ0_PGAG9_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23930;"	d
+RG_WF_IDACAQ_TZ1_PGAG0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24179;"	d
+RG_WF_IDACAQ_TZ1_PGAG0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24177;"	d
+RG_WF_IDACAQ_TZ1_PGAG0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24176;"	d
+RG_WF_IDACAQ_TZ1_PGAG0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24178;"	d
+RG_WF_IDACAQ_TZ1_PGAG0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24180;"	d
+RG_WF_IDACAQ_TZ1_PGAG10_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24079;"	d
+RG_WF_IDACAQ_TZ1_PGAG10_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24077;"	d
+RG_WF_IDACAQ_TZ1_PGAG10_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24076;"	d
+RG_WF_IDACAQ_TZ1_PGAG10_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24078;"	d
+RG_WF_IDACAQ_TZ1_PGAG10_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24080;"	d
+RG_WF_IDACAQ_TZ1_PGAG11_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24069;"	d
+RG_WF_IDACAQ_TZ1_PGAG11_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24067;"	d
+RG_WF_IDACAQ_TZ1_PGAG11_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24066;"	d
+RG_WF_IDACAQ_TZ1_PGAG11_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24068;"	d
+RG_WF_IDACAQ_TZ1_PGAG11_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24070;"	d
+RG_WF_IDACAQ_TZ1_PGAG12_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24059;"	d
+RG_WF_IDACAQ_TZ1_PGAG12_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24057;"	d
+RG_WF_IDACAQ_TZ1_PGAG12_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24056;"	d
+RG_WF_IDACAQ_TZ1_PGAG12_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24058;"	d
+RG_WF_IDACAQ_TZ1_PGAG12_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24060;"	d
+RG_WF_IDACAQ_TZ1_PGAG13_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24049;"	d
+RG_WF_IDACAQ_TZ1_PGAG13_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24047;"	d
+RG_WF_IDACAQ_TZ1_PGAG13_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24046;"	d
+RG_WF_IDACAQ_TZ1_PGAG13_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24048;"	d
+RG_WF_IDACAQ_TZ1_PGAG13_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24050;"	d
+RG_WF_IDACAQ_TZ1_PGAG14_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24039;"	d
+RG_WF_IDACAQ_TZ1_PGAG14_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24037;"	d
+RG_WF_IDACAQ_TZ1_PGAG14_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24036;"	d
+RG_WF_IDACAQ_TZ1_PGAG14_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24038;"	d
+RG_WF_IDACAQ_TZ1_PGAG14_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24040;"	d
+RG_WF_IDACAQ_TZ1_PGAG15_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24029;"	d
+RG_WF_IDACAQ_TZ1_PGAG15_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24027;"	d
+RG_WF_IDACAQ_TZ1_PGAG15_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24026;"	d
+RG_WF_IDACAQ_TZ1_PGAG15_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24028;"	d
+RG_WF_IDACAQ_TZ1_PGAG15_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24030;"	d
+RG_WF_IDACAQ_TZ1_PGAG1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24169;"	d
+RG_WF_IDACAQ_TZ1_PGAG1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24167;"	d
+RG_WF_IDACAQ_TZ1_PGAG1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24166;"	d
+RG_WF_IDACAQ_TZ1_PGAG1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24168;"	d
+RG_WF_IDACAQ_TZ1_PGAG1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24170;"	d
+RG_WF_IDACAQ_TZ1_PGAG2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24159;"	d
+RG_WF_IDACAQ_TZ1_PGAG2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24157;"	d
+RG_WF_IDACAQ_TZ1_PGAG2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24156;"	d
+RG_WF_IDACAQ_TZ1_PGAG2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24158;"	d
+RG_WF_IDACAQ_TZ1_PGAG2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24160;"	d
+RG_WF_IDACAQ_TZ1_PGAG3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24149;"	d
+RG_WF_IDACAQ_TZ1_PGAG3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24147;"	d
+RG_WF_IDACAQ_TZ1_PGAG3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24146;"	d
+RG_WF_IDACAQ_TZ1_PGAG3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24148;"	d
+RG_WF_IDACAQ_TZ1_PGAG3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24150;"	d
+RG_WF_IDACAQ_TZ1_PGAG4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24139;"	d
+RG_WF_IDACAQ_TZ1_PGAG4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24137;"	d
+RG_WF_IDACAQ_TZ1_PGAG4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24136;"	d
+RG_WF_IDACAQ_TZ1_PGAG4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24138;"	d
+RG_WF_IDACAQ_TZ1_PGAG4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24140;"	d
+RG_WF_IDACAQ_TZ1_PGAG5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24129;"	d
+RG_WF_IDACAQ_TZ1_PGAG5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24127;"	d
+RG_WF_IDACAQ_TZ1_PGAG5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24126;"	d
+RG_WF_IDACAQ_TZ1_PGAG5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24128;"	d
+RG_WF_IDACAQ_TZ1_PGAG5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24130;"	d
+RG_WF_IDACAQ_TZ1_PGAG6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24119;"	d
+RG_WF_IDACAQ_TZ1_PGAG6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24117;"	d
+RG_WF_IDACAQ_TZ1_PGAG6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24116;"	d
+RG_WF_IDACAQ_TZ1_PGAG6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24118;"	d
+RG_WF_IDACAQ_TZ1_PGAG6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24120;"	d
+RG_WF_IDACAQ_TZ1_PGAG7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24109;"	d
+RG_WF_IDACAQ_TZ1_PGAG7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24107;"	d
+RG_WF_IDACAQ_TZ1_PGAG7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24106;"	d
+RG_WF_IDACAQ_TZ1_PGAG7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24108;"	d
+RG_WF_IDACAQ_TZ1_PGAG7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24110;"	d
+RG_WF_IDACAQ_TZ1_PGAG8_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24099;"	d
+RG_WF_IDACAQ_TZ1_PGAG8_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24097;"	d
+RG_WF_IDACAQ_TZ1_PGAG8_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24096;"	d
+RG_WF_IDACAQ_TZ1_PGAG8_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24098;"	d
+RG_WF_IDACAQ_TZ1_PGAG8_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24100;"	d
+RG_WF_IDACAQ_TZ1_PGAG9_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24089;"	d
+RG_WF_IDACAQ_TZ1_PGAG9_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24087;"	d
+RG_WF_IDACAQ_TZ1_PGAG9_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24086;"	d
+RG_WF_IDACAQ_TZ1_PGAG9_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24088;"	d
+RG_WF_IDACAQ_TZ1_PGAG9_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24090;"	d
+RG_WF_N_RX_ABBCFIX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22104;"	d
+RG_WF_N_RX_ABBCFIX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22102;"	d
+RG_WF_N_RX_ABBCFIX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22101;"	d
+RG_WF_N_RX_ABBCFIX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22103;"	d
+RG_WF_N_RX_ABBCFIX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22105;"	d
+RG_WF_N_RX_ABBCTUNE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22074;"	d
+RG_WF_N_RX_ABBCTUNE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22072;"	d
+RG_WF_N_RX_ABBCTUNE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22071;"	d
+RG_WF_N_RX_ABBCTUNE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22073;"	d
+RG_WF_N_RX_ABBCTUNE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22075;"	d
+RG_WF_N_RX_ABBCTUNE_TUNE_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27354;"	d
+RG_WF_N_RX_ABBCTUNE_TUNE_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27352;"	d
+RG_WF_N_RX_ABBCTUNE_TUNE_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27351;"	d
+RG_WF_N_RX_ABBCTUNE_TUNE_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27353;"	d
+RG_WF_N_RX_ABBCTUNE_TUNE_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27355;"	d
+RG_WF_N_RX_ABBCTUNE_TUNE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27349;"	d
+RG_WF_N_RX_ABBCTUNE_TUNE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27347;"	d
+RG_WF_N_RX_ABBCTUNE_TUNE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27346;"	d
+RG_WF_N_RX_ABBCTUNE_TUNE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27348;"	d
+RG_WF_N_RX_ABBCTUNE_TUNE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27350;"	d
+RG_WF_N_RX_ABB_BT_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22114;"	d
+RG_WF_N_RX_ABB_BT_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22112;"	d
+RG_WF_N_RX_ABB_BT_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22111;"	d
+RG_WF_N_RX_ABB_BT_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22113;"	d
+RG_WF_N_RX_ABB_BT_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22115;"	d
+RG_WF_N_RX_ABB_IDIV3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22119;"	d
+RG_WF_N_RX_ABB_IDIV3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22117;"	d
+RG_WF_N_RX_ABB_IDIV3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22116;"	d
+RG_WF_N_RX_ABB_IDIV3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22118;"	d
+RG_WF_N_RX_ABB_IDIV3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22120;"	d
+RG_WF_N_RX_ABB_N_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22109;"	d
+RG_WF_N_RX_ABB_N_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22107;"	d
+RG_WF_N_RX_ABB_N_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22106;"	d
+RG_WF_N_RX_ABB_N_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22108;"	d
+RG_WF_N_RX_ABB_N_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22110;"	d
+RG_WF_N_RX_EN_IDACA_COARSE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22124;"	d
+RG_WF_N_RX_EN_IDACA_COARSE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22122;"	d
+RG_WF_N_RX_EN_IDACA_COARSE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22121;"	d
+RG_WF_N_RX_EN_IDACA_COARSE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22123;"	d
+RG_WF_N_RX_EN_IDACA_COARSE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22125;"	d
+RG_WF_N_RX_EN_LOOPA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22129;"	d
+RG_WF_N_RX_EN_LOOPA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22127;"	d
+RG_WF_N_RX_EN_LOOPA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22126;"	d
+RG_WF_N_RX_EN_LOOPA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22128;"	d
+RG_WF_N_RX_EN_LOOPA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22130;"	d
+RG_WF_N_RX_FILTERI1ST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22089;"	d
+RG_WF_N_RX_FILTERI1ST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22087;"	d
+RG_WF_N_RX_FILTERI1ST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22086;"	d
+RG_WF_N_RX_FILTERI1ST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22088;"	d
+RG_WF_N_RX_FILTERI1ST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22090;"	d
+RG_WF_N_RX_FILTERI2ND_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22094;"	d
+RG_WF_N_RX_FILTERI2ND_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22092;"	d
+RG_WF_N_RX_FILTERI2ND_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22091;"	d
+RG_WF_N_RX_FILTERI2ND_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22093;"	d
+RG_WF_N_RX_FILTERI2ND_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22095;"	d
+RG_WF_N_RX_FILTERI3RD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22099;"	d
+RG_WF_N_RX_FILTERI3RD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22097;"	d
+RG_WF_N_RX_FILTERI3RD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22096;"	d
+RG_WF_N_RX_FILTERI3RD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22098;"	d
+RG_WF_N_RX_FILTERI3RD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22100;"	d
+RG_WF_N_RX_FILTERI_COARSE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22084;"	d
+RG_WF_N_RX_FILTERI_COARSE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22082;"	d
+RG_WF_N_RX_FILTERI_COARSE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22081;"	d
+RG_WF_N_RX_FILTERI_COARSE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22083;"	d
+RG_WF_N_RX_FILTERI_COARSE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22085;"	d
+RG_WF_N_RX_FILTERVCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22139;"	d
+RG_WF_N_RX_FILTERVCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22137;"	d
+RG_WF_N_RX_FILTERVCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22136;"	d
+RG_WF_N_RX_FILTERVCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22138;"	d
+RG_WF_N_RX_FILTERVCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22140;"	d
+RG_WF_N_RX_OUTVCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22144;"	d
+RG_WF_N_RX_OUTVCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22142;"	d
+RG_WF_N_RX_OUTVCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22141;"	d
+RG_WF_N_RX_OUTVCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22143;"	d
+RG_WF_N_RX_OUTVCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22145;"	d
+RG_WF_N_RX_TZ_CMZ_C_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22079;"	d
+RG_WF_N_RX_TZ_CMZ_C_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22077;"	d
+RG_WF_N_RX_TZ_CMZ_C_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22076;"	d
+RG_WF_N_RX_TZ_CMZ_C_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22078;"	d
+RG_WF_N_RX_TZ_CMZ_C_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22080;"	d
+RG_WF_N_RX_TZ_CMZ_R_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22134;"	d
+RG_WF_N_RX_TZ_CMZ_R_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22132;"	d
+RG_WF_N_RX_TZ_CMZ_R_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22131;"	d
+RG_WF_N_RX_TZ_CMZ_R_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22133;"	d
+RG_WF_N_RX_TZ_CMZ_R_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22135;"	d
+RG_WF_PABIAS_CTRL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22339;"	d
+RG_WF_PABIAS_CTRL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22337;"	d
+RG_WF_PABIAS_CTRL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22336;"	d
+RG_WF_PABIAS_CTRL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22338;"	d
+RG_WF_PABIAS_CTRL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22340;"	d
+RG_WF_PACELL_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22334;"	d
+RG_WF_PACELL_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22332;"	d
+RG_WF_PACELL_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22331;"	d
+RG_WF_PACELL_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22333;"	d
+RG_WF_PACELL_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22335;"	d
+RG_WF_RX_ABBCFIX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22029;"	d
+RG_WF_RX_ABBCFIX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22027;"	d
+RG_WF_RX_ABBCFIX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22026;"	d
+RG_WF_RX_ABBCFIX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22028;"	d
+RG_WF_RX_ABBCFIX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22030;"	d
+RG_WF_RX_ABBCTUNE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21999;"	d
+RG_WF_RX_ABBCTUNE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21997;"	d
+RG_WF_RX_ABBCTUNE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21996;"	d
+RG_WF_RX_ABBCTUNE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21998;"	d
+RG_WF_RX_ABBCTUNE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22000;"	d
+RG_WF_RX_ABBCTUNE_TUNE_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27344;"	d
+RG_WF_RX_ABBCTUNE_TUNE_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27342;"	d
+RG_WF_RX_ABBCTUNE_TUNE_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27341;"	d
+RG_WF_RX_ABBCTUNE_TUNE_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27343;"	d
+RG_WF_RX_ABBCTUNE_TUNE_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27345;"	d
+RG_WF_RX_ABBCTUNE_TUNE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27339;"	d
+RG_WF_RX_ABBCTUNE_TUNE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27337;"	d
+RG_WF_RX_ABBCTUNE_TUNE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27336;"	d
+RG_WF_RX_ABBCTUNE_TUNE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27338;"	d
+RG_WF_RX_ABBCTUNE_TUNE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27340;"	d
+RG_WF_RX_ABB_BT_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22039;"	d
+RG_WF_RX_ABB_BT_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22037;"	d
+RG_WF_RX_ABB_BT_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22036;"	d
+RG_WF_RX_ABB_BT_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22038;"	d
+RG_WF_RX_ABB_BT_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22040;"	d
+RG_WF_RX_ABB_IDIV3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22044;"	d
+RG_WF_RX_ABB_IDIV3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22042;"	d
+RG_WF_RX_ABB_IDIV3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22041;"	d
+RG_WF_RX_ABB_IDIV3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22043;"	d
+RG_WF_RX_ABB_IDIV3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22045;"	d
+RG_WF_RX_ABB_N_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22034;"	d
+RG_WF_RX_ABB_N_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22032;"	d
+RG_WF_RX_ABB_N_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22031;"	d
+RG_WF_RX_ABB_N_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22033;"	d
+RG_WF_RX_ABB_N_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22035;"	d
+RG_WF_RX_ADC_CLOAD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22914;"	d
+RG_WF_RX_ADC_CLOAD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22912;"	d
+RG_WF_RX_ADC_CLOAD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22911;"	d
+RG_WF_RX_ADC_CLOAD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22913;"	d
+RG_WF_RX_ADC_CLOAD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22915;"	d
+RG_WF_RX_ADC_ICMP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22904;"	d
+RG_WF_RX_ADC_ICMP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22902;"	d
+RG_WF_RX_ADC_ICMP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22901;"	d
+RG_WF_RX_ADC_ICMP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22903;"	d
+RG_WF_RX_ADC_ICMP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22905;"	d
+RG_WF_RX_ADC_PSW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22919;"	d
+RG_WF_RX_ADC_PSW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22917;"	d
+RG_WF_RX_ADC_PSW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22916;"	d
+RG_WF_RX_ADC_PSW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22918;"	d
+RG_WF_RX_ADC_PSW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22920;"	d
+RG_WF_RX_ADC_VCMI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22909;"	d
+RG_WF_RX_ADC_VCMI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22907;"	d
+RG_WF_RX_ADC_VCMI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22906;"	d
+RG_WF_RX_ADC_VCMI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22908;"	d
+RG_WF_RX_ADC_VCMI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22910;"	d
+RG_WF_RX_DCCAL_DELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24674;"	d
+RG_WF_RX_DCCAL_DELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24672;"	d
+RG_WF_RX_DCCAL_DELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24671;"	d
+RG_WF_RX_DCCAL_DELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24673;"	d
+RG_WF_RX_DCCAL_DELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24675;"	d
+RG_WF_RX_EN_IDACA_COARSE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22049;"	d
+RG_WF_RX_EN_IDACA_COARSE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22047;"	d
+RG_WF_RX_EN_IDACA_COARSE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22046;"	d
+RG_WF_RX_EN_IDACA_COARSE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22048;"	d
+RG_WF_RX_EN_IDACA_COARSE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22050;"	d
+RG_WF_RX_EN_LOOPA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22054;"	d
+RG_WF_RX_EN_LOOPA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22052;"	d
+RG_WF_RX_EN_LOOPA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22051;"	d
+RG_WF_RX_EN_LOOPA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22053;"	d
+RG_WF_RX_EN_LOOPA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22055;"	d
+RG_WF_RX_FILTERI1ST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22014;"	d
+RG_WF_RX_FILTERI1ST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22012;"	d
+RG_WF_RX_FILTERI1ST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22011;"	d
+RG_WF_RX_FILTERI1ST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22013;"	d
+RG_WF_RX_FILTERI1ST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22015;"	d
+RG_WF_RX_FILTERI2ND_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22019;"	d
+RG_WF_RX_FILTERI2ND_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22017;"	d
+RG_WF_RX_FILTERI2ND_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22016;"	d
+RG_WF_RX_FILTERI2ND_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22018;"	d
+RG_WF_RX_FILTERI2ND_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22020;"	d
+RG_WF_RX_FILTERI3RD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22024;"	d
+RG_WF_RX_FILTERI3RD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22022;"	d
+RG_WF_RX_FILTERI3RD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22021;"	d
+RG_WF_RX_FILTERI3RD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22023;"	d
+RG_WF_RX_FILTERI3RD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22025;"	d
+RG_WF_RX_FILTERI_COARSE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22009;"	d
+RG_WF_RX_FILTERI_COARSE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22007;"	d
+RG_WF_RX_FILTERI_COARSE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22006;"	d
+RG_WF_RX_FILTERI_COARSE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22008;"	d
+RG_WF_RX_FILTERI_COARSE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22010;"	d
+RG_WF_RX_FILTERVCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22064;"	d
+RG_WF_RX_FILTERVCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22062;"	d
+RG_WF_RX_FILTERVCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22061;"	d
+RG_WF_RX_FILTERVCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22063;"	d
+RG_WF_RX_FILTERVCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22065;"	d
+RG_WF_RX_HG_DIV2_CORE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22474;"	d
+RG_WF_RX_HG_DIV2_CORE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22472;"	d
+RG_WF_RX_HG_DIV2_CORE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22471;"	d
+RG_WF_RX_HG_DIV2_CORE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22473;"	d
+RG_WF_RX_HG_DIV2_CORE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22475;"	d
+RG_WF_RX_HG_LNAHGN_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22449;"	d
+RG_WF_RX_HG_LNAHGN_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22447;"	d
+RG_WF_RX_HG_LNAHGN_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22446;"	d
+RG_WF_RX_HG_LNAHGN_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22448;"	d
+RG_WF_RX_HG_LNAHGN_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22450;"	d
+RG_WF_RX_HG_LNAHGP_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22454;"	d
+RG_WF_RX_HG_LNAHGP_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22452;"	d
+RG_WF_RX_HG_LNAHGP_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22451;"	d
+RG_WF_RX_HG_LNAHGP_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22453;"	d
+RG_WF_RX_HG_LNAHGP_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22455;"	d
+RG_WF_RX_HG_LNALG_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22459;"	d
+RG_WF_RX_HG_LNALG_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22457;"	d
+RG_WF_RX_HG_LNALG_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22456;"	d
+RG_WF_RX_HG_LNALG_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22458;"	d
+RG_WF_RX_HG_LNALG_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22460;"	d
+RG_WF_RX_HG_LNA_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22439;"	d
+RG_WF_RX_HG_LNA_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22437;"	d
+RG_WF_RX_HG_LNA_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22436;"	d
+RG_WF_RX_HG_LNA_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22438;"	d
+RG_WF_RX_HG_LNA_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22440;"	d
+RG_WF_RX_HG_LOBUF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22479;"	d
+RG_WF_RX_HG_LOBUF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22477;"	d
+RG_WF_RX_HG_LOBUF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22476;"	d
+RG_WF_RX_HG_LOBUF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22478;"	d
+RG_WF_RX_HG_LOBUF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22480;"	d
+RG_WF_RX_HG_TZI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22484;"	d
+RG_WF_RX_HG_TZI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22482;"	d
+RG_WF_RX_HG_TZI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22481;"	d
+RG_WF_RX_HG_TZI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22483;"	d
+RG_WF_RX_HG_TZI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22485;"	d
+RG_WF_RX_HG_TZ_CAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22464;"	d
+RG_WF_RX_HG_TZ_CAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22462;"	d
+RG_WF_RX_HG_TZ_CAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22461;"	d
+RG_WF_RX_HG_TZ_CAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22463;"	d
+RG_WF_RX_HG_TZ_CAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22465;"	d
+RG_WF_RX_HG_TZ_GC_BOOST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22469;"	d
+RG_WF_RX_HG_TZ_GC_BOOST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22467;"	d
+RG_WF_RX_HG_TZ_GC_BOOST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22466;"	d
+RG_WF_RX_HG_TZ_GC_BOOST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22468;"	d
+RG_WF_RX_HG_TZ_GC_BOOST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22470;"	d
+RG_WF_RX_HG_TZ_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22444;"	d
+RG_WF_RX_HG_TZ_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22442;"	d
+RG_WF_RX_HG_TZ_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22441;"	d
+RG_WF_RX_HG_TZ_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22443;"	d
+RG_WF_RX_HG_TZ_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22445;"	d
+RG_WF_RX_HG_TZ_VCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22489;"	d
+RG_WF_RX_HG_TZ_VCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22487;"	d
+RG_WF_RX_HG_TZ_VCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22486;"	d
+RG_WF_RX_HG_TZ_VCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22488;"	d
+RG_WF_RX_HG_TZ_VCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22490;"	d
+RG_WF_RX_LG_DIV2_CORE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22584;"	d
+RG_WF_RX_LG_DIV2_CORE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22582;"	d
+RG_WF_RX_LG_DIV2_CORE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22581;"	d
+RG_WF_RX_LG_DIV2_CORE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22583;"	d
+RG_WF_RX_LG_DIV2_CORE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22585;"	d
+RG_WF_RX_LG_LNAHGN_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22559;"	d
+RG_WF_RX_LG_LNAHGN_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22557;"	d
+RG_WF_RX_LG_LNAHGN_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22556;"	d
+RG_WF_RX_LG_LNAHGN_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22558;"	d
+RG_WF_RX_LG_LNAHGN_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22560;"	d
+RG_WF_RX_LG_LNAHGP_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22564;"	d
+RG_WF_RX_LG_LNAHGP_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22562;"	d
+RG_WF_RX_LG_LNAHGP_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22561;"	d
+RG_WF_RX_LG_LNAHGP_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22563;"	d
+RG_WF_RX_LG_LNAHGP_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22565;"	d
+RG_WF_RX_LG_LNALG_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22569;"	d
+RG_WF_RX_LG_LNALG_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22567;"	d
+RG_WF_RX_LG_LNALG_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22566;"	d
+RG_WF_RX_LG_LNALG_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22568;"	d
+RG_WF_RX_LG_LNALG_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22570;"	d
+RG_WF_RX_LG_LNA_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22549;"	d
+RG_WF_RX_LG_LNA_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22547;"	d
+RG_WF_RX_LG_LNA_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22546;"	d
+RG_WF_RX_LG_LNA_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22548;"	d
+RG_WF_RX_LG_LNA_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22550;"	d
+RG_WF_RX_LG_LOBUF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22589;"	d
+RG_WF_RX_LG_LOBUF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22587;"	d
+RG_WF_RX_LG_LOBUF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22586;"	d
+RG_WF_RX_LG_LOBUF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22588;"	d
+RG_WF_RX_LG_LOBUF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22590;"	d
+RG_WF_RX_LG_TZI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22594;"	d
+RG_WF_RX_LG_TZI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22592;"	d
+RG_WF_RX_LG_TZI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22591;"	d
+RG_WF_RX_LG_TZI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22593;"	d
+RG_WF_RX_LG_TZI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22595;"	d
+RG_WF_RX_LG_TZ_CAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22574;"	d
+RG_WF_RX_LG_TZ_CAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22572;"	d
+RG_WF_RX_LG_TZ_CAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22571;"	d
+RG_WF_RX_LG_TZ_CAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22573;"	d
+RG_WF_RX_LG_TZ_CAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22575;"	d
+RG_WF_RX_LG_TZ_GC_BOOST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22579;"	d
+RG_WF_RX_LG_TZ_GC_BOOST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22577;"	d
+RG_WF_RX_LG_TZ_GC_BOOST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22576;"	d
+RG_WF_RX_LG_TZ_GC_BOOST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22578;"	d
+RG_WF_RX_LG_TZ_GC_BOOST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22580;"	d
+RG_WF_RX_LG_TZ_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22554;"	d
+RG_WF_RX_LG_TZ_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22552;"	d
+RG_WF_RX_LG_TZ_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22551;"	d
+RG_WF_RX_LG_TZ_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22553;"	d
+RG_WF_RX_LG_TZ_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22555;"	d
+RG_WF_RX_LG_TZ_VCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22599;"	d
+RG_WF_RX_LG_TZ_VCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22597;"	d
+RG_WF_RX_LG_TZ_VCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22596;"	d
+RG_WF_RX_LG_TZ_VCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22598;"	d
+RG_WF_RX_LG_TZ_VCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22600;"	d
+RG_WF_RX_MG_DIV2_CORE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22529;"	d
+RG_WF_RX_MG_DIV2_CORE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22527;"	d
+RG_WF_RX_MG_DIV2_CORE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22526;"	d
+RG_WF_RX_MG_DIV2_CORE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22528;"	d
+RG_WF_RX_MG_DIV2_CORE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22530;"	d
+RG_WF_RX_MG_LNAHGN_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22504;"	d
+RG_WF_RX_MG_LNAHGN_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22502;"	d
+RG_WF_RX_MG_LNAHGN_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22501;"	d
+RG_WF_RX_MG_LNAHGN_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22503;"	d
+RG_WF_RX_MG_LNAHGN_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22505;"	d
+RG_WF_RX_MG_LNAHGP_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22509;"	d
+RG_WF_RX_MG_LNAHGP_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22507;"	d
+RG_WF_RX_MG_LNAHGP_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22506;"	d
+RG_WF_RX_MG_LNAHGP_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22508;"	d
+RG_WF_RX_MG_LNAHGP_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22510;"	d
+RG_WF_RX_MG_LNALG_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22514;"	d
+RG_WF_RX_MG_LNALG_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22512;"	d
+RG_WF_RX_MG_LNALG_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22511;"	d
+RG_WF_RX_MG_LNALG_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22513;"	d
+RG_WF_RX_MG_LNALG_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22515;"	d
+RG_WF_RX_MG_LNA_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22494;"	d
+RG_WF_RX_MG_LNA_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22492;"	d
+RG_WF_RX_MG_LNA_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22491;"	d
+RG_WF_RX_MG_LNA_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22493;"	d
+RG_WF_RX_MG_LNA_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22495;"	d
+RG_WF_RX_MG_LOBUF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22534;"	d
+RG_WF_RX_MG_LOBUF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22532;"	d
+RG_WF_RX_MG_LOBUF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22531;"	d
+RG_WF_RX_MG_LOBUF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22533;"	d
+RG_WF_RX_MG_LOBUF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22535;"	d
+RG_WF_RX_MG_TZI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22539;"	d
+RG_WF_RX_MG_TZI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22537;"	d
+RG_WF_RX_MG_TZI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22536;"	d
+RG_WF_RX_MG_TZI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22538;"	d
+RG_WF_RX_MG_TZI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22540;"	d
+RG_WF_RX_MG_TZ_CAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22519;"	d
+RG_WF_RX_MG_TZ_CAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22517;"	d
+RG_WF_RX_MG_TZ_CAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22516;"	d
+RG_WF_RX_MG_TZ_CAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22518;"	d
+RG_WF_RX_MG_TZ_CAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22520;"	d
+RG_WF_RX_MG_TZ_GC_BOOST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22524;"	d
+RG_WF_RX_MG_TZ_GC_BOOST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22522;"	d
+RG_WF_RX_MG_TZ_GC_BOOST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22521;"	d
+RG_WF_RX_MG_TZ_GC_BOOST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22523;"	d
+RG_WF_RX_MG_TZ_GC_BOOST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22525;"	d
+RG_WF_RX_MG_TZ_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22499;"	d
+RG_WF_RX_MG_TZ_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22497;"	d
+RG_WF_RX_MG_TZ_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22496;"	d
+RG_WF_RX_MG_TZ_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22498;"	d
+RG_WF_RX_MG_TZ_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22500;"	d
+RG_WF_RX_MG_TZ_VCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22544;"	d
+RG_WF_RX_MG_TZ_VCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22542;"	d
+RG_WF_RX_MG_TZ_VCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22541;"	d
+RG_WF_RX_MG_TZ_VCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22543;"	d
+RG_WF_RX_MG_TZ_VCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22545;"	d
+RG_WF_RX_OUTVCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22069;"	d
+RG_WF_RX_OUTVCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22067;"	d
+RG_WF_RX_OUTVCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22066;"	d
+RG_WF_RX_OUTVCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22068;"	d
+RG_WF_RX_OUTVCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22070;"	d
+RG_WF_RX_TZ_CMZ_C_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22004;"	d
+RG_WF_RX_TZ_CMZ_C_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22002;"	d
+RG_WF_RX_TZ_CMZ_C_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22001;"	d
+RG_WF_RX_TZ_CMZ_C_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22003;"	d
+RG_WF_RX_TZ_CMZ_C_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22005;"	d
+RG_WF_RX_TZ_CMZ_R_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22059;"	d
+RG_WF_RX_TZ_CMZ_R_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22057;"	d
+RG_WF_RX_TZ_CMZ_R_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22056;"	d
+RG_WF_RX_TZ_CMZ_R_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22058;"	d
+RG_WF_RX_TZ_CMZ_R_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22060;"	d
+RG_WF_RX_ULG_DIV2_CORE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22639;"	d
+RG_WF_RX_ULG_DIV2_CORE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22637;"	d
+RG_WF_RX_ULG_DIV2_CORE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22636;"	d
+RG_WF_RX_ULG_DIV2_CORE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22638;"	d
+RG_WF_RX_ULG_DIV2_CORE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22640;"	d
+RG_WF_RX_ULG_LNAHGN_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22614;"	d
+RG_WF_RX_ULG_LNAHGN_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22612;"	d
+RG_WF_RX_ULG_LNAHGN_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22611;"	d
+RG_WF_RX_ULG_LNAHGN_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22613;"	d
+RG_WF_RX_ULG_LNAHGN_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22615;"	d
+RG_WF_RX_ULG_LNAHGP_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22619;"	d
+RG_WF_RX_ULG_LNAHGP_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22617;"	d
+RG_WF_RX_ULG_LNAHGP_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22616;"	d
+RG_WF_RX_ULG_LNAHGP_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22618;"	d
+RG_WF_RX_ULG_LNAHGP_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22620;"	d
+RG_WF_RX_ULG_LNALG_BIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22624;"	d
+RG_WF_RX_ULG_LNALG_BIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22622;"	d
+RG_WF_RX_ULG_LNALG_BIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22621;"	d
+RG_WF_RX_ULG_LNALG_BIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22623;"	d
+RG_WF_RX_ULG_LNALG_BIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22625;"	d
+RG_WF_RX_ULG_LNA_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22604;"	d
+RG_WF_RX_ULG_LNA_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22602;"	d
+RG_WF_RX_ULG_LNA_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22601;"	d
+RG_WF_RX_ULG_LNA_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22603;"	d
+RG_WF_RX_ULG_LNA_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22605;"	d
+RG_WF_RX_ULG_LOBUF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22644;"	d
+RG_WF_RX_ULG_LOBUF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22642;"	d
+RG_WF_RX_ULG_LOBUF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22641;"	d
+RG_WF_RX_ULG_LOBUF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22643;"	d
+RG_WF_RX_ULG_LOBUF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22645;"	d
+RG_WF_RX_ULG_TZI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22649;"	d
+RG_WF_RX_ULG_TZI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22647;"	d
+RG_WF_RX_ULG_TZI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22646;"	d
+RG_WF_RX_ULG_TZI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22648;"	d
+RG_WF_RX_ULG_TZI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22650;"	d
+RG_WF_RX_ULG_TZ_CAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22629;"	d
+RG_WF_RX_ULG_TZ_CAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22627;"	d
+RG_WF_RX_ULG_TZ_CAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22626;"	d
+RG_WF_RX_ULG_TZ_CAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22628;"	d
+RG_WF_RX_ULG_TZ_CAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22630;"	d
+RG_WF_RX_ULG_TZ_GC_BOOST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22634;"	d
+RG_WF_RX_ULG_TZ_GC_BOOST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22632;"	d
+RG_WF_RX_ULG_TZ_GC_BOOST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22631;"	d
+RG_WF_RX_ULG_TZ_GC_BOOST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22633;"	d
+RG_WF_RX_ULG_TZ_GC_BOOST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22635;"	d
+RG_WF_RX_ULG_TZ_GC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22609;"	d
+RG_WF_RX_ULG_TZ_GC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22607;"	d
+RG_WF_RX_ULG_TZ_GC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22606;"	d
+RG_WF_RX_ULG_TZ_GC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22608;"	d
+RG_WF_RX_ULG_TZ_GC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22610;"	d
+RG_WF_RX_ULG_TZ_VCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22654;"	d
+RG_WF_RX_ULG_TZ_VCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22652;"	d
+RG_WF_RX_ULG_TZ_VCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22651;"	d
+RG_WF_RX_ULG_TZ_VCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22653;"	d
+RG_WF_RX_ULG_TZ_VCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22655;"	d
+RG_WF_TXLPF_BOOSTI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23004;"	d
+RG_WF_TXLPF_BOOSTI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23002;"	d
+RG_WF_TXLPF_BOOSTI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23001;"	d
+RG_WF_TXLPF_BOOSTI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23003;"	d
+RG_WF_TXLPF_BOOSTI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23005;"	d
+RG_WF_TXMOD_GMCELL_FINE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22309;"	d
+RG_WF_TXMOD_GMCELL_FINE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22307;"	d
+RG_WF_TXMOD_GMCELL_FINE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22306;"	d
+RG_WF_TXMOD_GMCELL_FINE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22308;"	d
+RG_WF_TXMOD_GMCELL_FINE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22310;"	d
+RG_WF_TXPGA_CAPSW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22294;"	d
+RG_WF_TXPGA_CAPSW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22292;"	d
+RG_WF_TXPGA_CAPSW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22291;"	d
+RG_WF_TXPGA_CAPSW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22293;"	d
+RG_WF_TXPGA_CAPSW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22295;"	d
+RG_WF_TX_DACI1ST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22974;"	d
+RG_WF_TX_DACI1ST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22972;"	d
+RG_WF_TX_DACI1ST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22971;"	d
+RG_WF_TX_DACI1ST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22973;"	d
+RG_WF_TX_DACI1ST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22975;"	d
+RG_WF_TX_DACLPF_ICOARSE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22979;"	d
+RG_WF_TX_DACLPF_ICOARSE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22977;"	d
+RG_WF_TX_DACLPF_ICOARSE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22976;"	d
+RG_WF_TX_DACLPF_ICOARSE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22978;"	d
+RG_WF_TX_DACLPF_ICOARSE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22980;"	d
+RG_WF_TX_DACLPF_IFINE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22984;"	d
+RG_WF_TX_DACLPF_IFINE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22982;"	d
+RG_WF_TX_DACLPF_IFINE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22981;"	d
+RG_WF_TX_DACLPF_IFINE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22983;"	d
+RG_WF_TX_DACLPF_IFINE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22985;"	d
+RG_WF_TX_DACLPF_VCM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22989;"	d
+RG_WF_TX_DACLPF_VCM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22987;"	d
+RG_WF_TX_DACLPF_VCM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22986;"	d
+RG_WF_TX_DACLPF_VCM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22988;"	d
+RG_WF_TX_DACLPF_VCM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22990;"	d
+RG_WF_TX_DAC_CKEDGE_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23014;"	d
+RG_WF_TX_DAC_CKEDGE_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23012;"	d
+RG_WF_TX_DAC_CKEDGE_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23011;"	d
+RG_WF_TX_DAC_CKEDGE_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23013;"	d
+RG_WF_TX_DAC_CKEDGE_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23015;"	d
+RG_WF_TX_DAC_IATTN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22999;"	d
+RG_WF_TX_DAC_IATTN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22997;"	d
+RG_WF_TX_DAC_IATTN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22996;"	d
+RG_WF_TX_DAC_IATTN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22998;"	d
+RG_WF_TX_DAC_IATTN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23000;"	d
+RG_WF_TX_DAC_IBIAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22994;"	d
+RG_WF_TX_DAC_IBIAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22992;"	d
+RG_WF_TX_DAC_IBIAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22991;"	d
+RG_WF_TX_DAC_IBIAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22993;"	d
+RG_WF_TX_DAC_IBIAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22995;"	d
+RG_WF_TX_DAC_IOFFSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23024;"	d
+RG_WF_TX_DAC_IOFFSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23022;"	d
+RG_WF_TX_DAC_IOFFSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23021;"	d
+RG_WF_TX_DAC_IOFFSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23023;"	d
+RG_WF_TX_DAC_IOFFSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23025;"	d
+RG_WF_TX_DAC_OS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23019;"	d
+RG_WF_TX_DAC_OS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23017;"	d
+RG_WF_TX_DAC_OS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23016;"	d
+RG_WF_TX_DAC_OS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23018;"	d
+RG_WF_TX_DAC_OS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23020;"	d
+RG_WF_TX_DAC_QOFFSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23029;"	d
+RG_WF_TX_DAC_QOFFSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23027;"	d
+RG_WF_TX_DAC_QOFFSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23026;"	d
+RG_WF_TX_DAC_QOFFSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23028;"	d
+RG_WF_TX_DAC_QOFFSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23030;"	d
+RG_WF_TX_DAC_RCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	23009;"	d
+RG_WF_TX_DAC_RCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23007;"	d
+RG_WF_TX_DAC_RCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	23006;"	d
+RG_WF_TX_DAC_RCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	23008;"	d
+RG_WF_TX_DAC_RCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	23010;"	d
+RG_WF_TX_DIV_VSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22299;"	d
+RG_WF_TX_DIV_VSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22297;"	d
+RG_WF_TX_DIV_VSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22296;"	d
+RG_WF_TX_DIV_VSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22298;"	d
+RG_WF_TX_DIV_VSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22300;"	d
+RG_WF_TX_GAIN_OFFSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22409;"	d
+RG_WF_TX_GAIN_OFFSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22407;"	d
+RG_WF_TX_GAIN_OFFSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22406;"	d
+RG_WF_TX_GAIN_OFFSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22408;"	d
+RG_WF_TX_GAIN_OFFSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22410;"	d
+RG_WF_TX_LOBUF_VSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22304;"	d
+RG_WF_TX_LOBUF_VSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22302;"	d
+RG_WF_TX_LOBUF_VSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22301;"	d
+RG_WF_TX_LOBUF_VSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22303;"	d
+RG_WF_TX_LOBUF_VSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22305;"	d
+RG_WF_TX_PA1_VCAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22344;"	d
+RG_WF_TX_PA1_VCAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22342;"	d
+RG_WF_TX_PA1_VCAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22341;"	d
+RG_WF_TX_PA1_VCAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22343;"	d
+RG_WF_TX_PA1_VCAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22345;"	d
+RG_WF_TX_PA2_VCAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22349;"	d
+RG_WF_TX_PA2_VCAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22347;"	d
+RG_WF_TX_PA2_VCAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22346;"	d
+RG_WF_TX_PA2_VCAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22348;"	d
+RG_WF_TX_PA2_VCAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22350;"	d
+RG_WF_TX_PA3_VCAS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	22354;"	d
+RG_WF_TX_PA3_VCAS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22352;"	d
+RG_WF_TX_PA3_VCAS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	22351;"	d
+RG_WF_TX_PA3_VCAS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	22353;"	d
+RG_WF_TX_PA3_VCAS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	22355;"	d
+RG_WR_ACI_GAIN_INI_SEL_11B_HI	include/ssv6200_aux.h	13439;"	d
+RG_WR_ACI_GAIN_INI_SEL_11B_I_MSK	include/ssv6200_aux.h	13437;"	d
+RG_WR_ACI_GAIN_INI_SEL_11B_MSK	include/ssv6200_aux.h	13436;"	d
+RG_WR_ACI_GAIN_INI_SEL_11B_SFT	include/ssv6200_aux.h	13438;"	d
+RG_WR_ACI_GAIN_INI_SEL_11B_SZ	include/ssv6200_aux.h	13440;"	d
+RG_WR_ACI_GAIN_OW_11B_HI	include/ssv6200_aux.h	13454;"	d
+RG_WR_ACI_GAIN_OW_11B_I_MSK	include/ssv6200_aux.h	13452;"	d
+RG_WR_ACI_GAIN_OW_11B_MSK	include/ssv6200_aux.h	13451;"	d
+RG_WR_ACI_GAIN_OW_11B_SFT	include/ssv6200_aux.h	13453;"	d
+RG_WR_ACI_GAIN_OW_11B_SZ	include/ssv6200_aux.h	13455;"	d
+RG_WR_ACI_GAIN_SEL_11B_HI	include/ssv6200_aux.h	13444;"	d
+RG_WR_ACI_GAIN_SEL_11B_I_MSK	include/ssv6200_aux.h	13442;"	d
+RG_WR_ACI_GAIN_SEL_11B_MSK	include/ssv6200_aux.h	13441;"	d
+RG_WR_ACI_GAIN_SEL_11B_SFT	include/ssv6200_aux.h	13443;"	d
+RG_WR_ACI_GAIN_SEL_11B_SZ	include/ssv6200_aux.h	13445;"	d
+RG_WR_RFGC_INIT_EN_HI	include/ssv6200_aux.h	13414;"	d
+RG_WR_RFGC_INIT_EN_I_MSK	include/ssv6200_aux.h	13412;"	d
+RG_WR_RFGC_INIT_EN_MSK	include/ssv6200_aux.h	13411;"	d
+RG_WR_RFGC_INIT_EN_SFT	include/ssv6200_aux.h	13413;"	d
+RG_WR_RFGC_INIT_EN_SZ	include/ssv6200_aux.h	13415;"	d
+RG_WR_RFGC_INIT_SET_HI	include/ssv6200_aux.h	13409;"	d
+RG_WR_RFGC_INIT_SET_I_MSK	include/ssv6200_aux.h	13407;"	d
+RG_WR_RFGC_INIT_SET_MSK	include/ssv6200_aux.h	13406;"	d
+RG_WR_RFGC_INIT_SET_SFT	include/ssv6200_aux.h	13408;"	d
+RG_WR_RFGC_INIT_SET_SZ	include/ssv6200_aux.h	13410;"	d
+RG_WR_TX_EN_CNT_RST_N_HI	include/ssv6200_aux.h	14309;"	d
+RG_WR_TX_EN_CNT_RST_N_I_MSK	include/ssv6200_aux.h	14307;"	d
+RG_WR_TX_EN_CNT_RST_N_MSK	include/ssv6200_aux.h	14306;"	d
+RG_WR_TX_EN_CNT_RST_N_SFT	include/ssv6200_aux.h	14308;"	d
+RG_WR_TX_EN_CNT_RST_N_SZ	include/ssv6200_aux.h	14310;"	d
+RG_XOSC_CBANK_XI_HI	include/ssv6200_aux.h	17194;"	d
+RG_XOSC_CBANK_XI_I_MSK	include/ssv6200_aux.h	17192;"	d
+RG_XOSC_CBANK_XI_MSK	include/ssv6200_aux.h	17191;"	d
+RG_XOSC_CBANK_XI_SFT	include/ssv6200_aux.h	17193;"	d
+RG_XOSC_CBANK_XI_SZ	include/ssv6200_aux.h	17195;"	d
+RG_XOSC_CBANK_XO_HI	include/ssv6200_aux.h	17189;"	d
+RG_XOSC_CBANK_XO_I_MSK	include/ssv6200_aux.h	17187;"	d
+RG_XOSC_CBANK_XO_MSK	include/ssv6200_aux.h	17186;"	d
+RG_XOSC_CBANK_XO_SFT	include/ssv6200_aux.h	17188;"	d
+RG_XOSC_CBANK_XO_SZ	include/ssv6200_aux.h	17190;"	d
+RG_XO_CBANKI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29504;"	d
+RG_XO_CBANKI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29502;"	d
+RG_XO_CBANKI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29501;"	d
+RG_XO_CBANKI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29503;"	d
+RG_XO_CBANKI_SLP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30084;"	d
+RG_XO_CBANKI_SLP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30082;"	d
+RG_XO_CBANKI_SLP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30081;"	d
+RG_XO_CBANKI_SLP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30083;"	d
+RG_XO_CBANKI_SLP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30085;"	d
+RG_XO_CBANKI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29505;"	d
+RG_XO_CBANKO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29509;"	d
+RG_XO_CBANKO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29507;"	d
+RG_XO_CBANKO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29506;"	d
+RG_XO_CBANKO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29508;"	d
+RG_XO_CBANKO_SLP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30089;"	d
+RG_XO_CBANKO_SLP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30087;"	d
+RG_XO_CBANKO_SLP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30086;"	d
+RG_XO_CBANKO_SLP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30088;"	d
+RG_XO_CBANKO_SLP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30090;"	d
+RG_XO_CBANKO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29510;"	d
+RG_XO_LDO_LEVEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29479;"	d
+RG_XO_LDO_LEVEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29477;"	d
+RG_XO_LDO_LEVEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29476;"	d
+RG_XO_LDO_LEVEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29478;"	d
+RG_XO_LDO_LEVEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29480;"	d
+RG_XO_TIMMER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29579;"	d
+RG_XO_TIMMER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29577;"	d
+RG_XO_TIMMER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29576;"	d
+RG_XO_TIMMER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29578;"	d
+RG_XO_TIMMER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29580;"	d
+RG_XSCOR16_RATIO_HI	include/ssv6200_aux.h	14979;"	d
+RG_XSCOR16_RATIO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32399;"	d
+RG_XSCOR16_RATIO_I_MSK	include/ssv6200_aux.h	14977;"	d
+RG_XSCOR16_RATIO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32397;"	d
+RG_XSCOR16_RATIO_MSK	include/ssv6200_aux.h	14976;"	d
+RG_XSCOR16_RATIO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32396;"	d
+RG_XSCOR16_RATIO_SFT	include/ssv6200_aux.h	14978;"	d
+RG_XSCOR16_RATIO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32398;"	d
+RG_XSCOR16_RATIO_SZ	include/ssv6200_aux.h	14980;"	d
+RG_XSCOR16_RATIO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32400;"	d
+RG_XSCOR16_SHORT_CNT_LMT_HI	include/ssv6200_aux.h	14974;"	d
+RG_XSCOR16_SHORT_CNT_LMT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32394;"	d
+RG_XSCOR16_SHORT_CNT_LMT_I_MSK	include/ssv6200_aux.h	14972;"	d
+RG_XSCOR16_SHORT_CNT_LMT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32392;"	d
+RG_XSCOR16_SHORT_CNT_LMT_MSK	include/ssv6200_aux.h	14971;"	d
+RG_XSCOR16_SHORT_CNT_LMT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32391;"	d
+RG_XSCOR16_SHORT_CNT_LMT_SFT	include/ssv6200_aux.h	14973;"	d
+RG_XSCOR16_SHORT_CNT_LMT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32393;"	d
+RG_XSCOR16_SHORT_CNT_LMT_SZ	include/ssv6200_aux.h	14975;"	d
+RG_XSCOR16_SHORT_CNT_LMT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32395;"	d
+RG_XSCOR32_RATIO_HI	include/ssv6200_aux.h	14804;"	d
+RG_XSCOR32_RATIO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32044;"	d
+RG_XSCOR32_RATIO_I_MSK	include/ssv6200_aux.h	14802;"	d
+RG_XSCOR32_RATIO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32042;"	d
+RG_XSCOR32_RATIO_MSK	include/ssv6200_aux.h	14801;"	d
+RG_XSCOR32_RATIO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32041;"	d
+RG_XSCOR32_RATIO_SFT	include/ssv6200_aux.h	14803;"	d
+RG_XSCOR32_RATIO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32043;"	d
+RG_XSCOR32_RATIO_SZ	include/ssv6200_aux.h	14805;"	d
+RG_XSCOR32_RATIO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32045;"	d
+RG_XSCOR64_CNT_LMT1_HI	include/ssv6200_aux.h	14834;"	d
+RG_XSCOR64_CNT_LMT1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32074;"	d
+RG_XSCOR64_CNT_LMT1_I_MSK	include/ssv6200_aux.h	14832;"	d
+RG_XSCOR64_CNT_LMT1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32072;"	d
+RG_XSCOR64_CNT_LMT1_MSK	include/ssv6200_aux.h	14831;"	d
+RG_XSCOR64_CNT_LMT1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32071;"	d
+RG_XSCOR64_CNT_LMT1_SFT	include/ssv6200_aux.h	14833;"	d
+RG_XSCOR64_CNT_LMT1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32073;"	d
+RG_XSCOR64_CNT_LMT1_SZ	include/ssv6200_aux.h	14835;"	d
+RG_XSCOR64_CNT_LMT1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32075;"	d
+RG_XSCOR64_CNT_LMT2_HI	include/ssv6200_aux.h	14829;"	d
+RG_XSCOR64_CNT_LMT2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32069;"	d
+RG_XSCOR64_CNT_LMT2_I_MSK	include/ssv6200_aux.h	14827;"	d
+RG_XSCOR64_CNT_LMT2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32067;"	d
+RG_XSCOR64_CNT_LMT2_MSK	include/ssv6200_aux.h	14826;"	d
+RG_XSCOR64_CNT_LMT2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32066;"	d
+RG_XSCOR64_CNT_LMT2_SFT	include/ssv6200_aux.h	14828;"	d
+RG_XSCOR64_CNT_LMT2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32068;"	d
+RG_XSCOR64_CNT_LMT2_SZ	include/ssv6200_aux.h	14830;"	d
+RG_XSCOR64_CNT_LMT2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32070;"	d
+RG_XSCOR64_RATIO_SB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32439;"	d
+RG_XSCOR64_RATIO_SB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32437;"	d
+RG_XSCOR64_RATIO_SB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32436;"	d
+RG_XSCOR64_RATIO_SB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32438;"	d
+RG_XSCOR64_RATIO_SB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32440;"	d
+RIP_A_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3679;"	d
+RIP_A_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3677;"	d
+RIP_A_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3676;"	d
+RIP_A_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3678;"	d
+RIP_A_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3680;"	d
+RI_HI	include/ssv6200_aux.h	4459;"	d
+RI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3569;"	d
+RI_I_MSK	include/ssv6200_aux.h	4457;"	d
+RI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3567;"	d
+RI_MSK	include/ssv6200_aux.h	4456;"	d
+RI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3566;"	d
+RI_SFT	include/ssv6200_aux.h	4458;"	d
+RI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3568;"	d
+RI_SZ	include/ssv6200_aux.h	4460;"	d
+RI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3570;"	d
+RK_LEN	smac/wapi_sms4.c	29;"	d	file:
+RLS_ABT_ID_HI	include/ssv6200_aux.h	17889;"	d
+RLS_ABT_ID_I_MSK	include/ssv6200_aux.h	17887;"	d
+RLS_ABT_ID_MSK	include/ssv6200_aux.h	17886;"	d
+RLS_ABT_ID_SFT	include/ssv6200_aux.h	17888;"	d
+RLS_ABT_ID_SZ	include/ssv6200_aux.h	17890;"	d
+RLS_ABT_INT_HI	include/ssv6200_aux.h	17894;"	d
+RLS_ABT_INT_I_MSK	include/ssv6200_aux.h	17892;"	d
+RLS_ABT_INT_MSK	include/ssv6200_aux.h	17891;"	d
+RLS_ABT_INT_SFT	include/ssv6200_aux.h	17893;"	d
+RLS_ABT_INT_SZ	include/ssv6200_aux.h	17895;"	d
+RLS_BUSY_HI	include/ssv6200_aux.h	11434;"	d
+RLS_BUSY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33004;"	d
+RLS_BUSY_I_MSK	include/ssv6200_aux.h	11432;"	d
+RLS_BUSY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33002;"	d
+RLS_BUSY_MSK	include/ssv6200_aux.h	11431;"	d
+RLS_BUSY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33001;"	d
+RLS_BUSY_SFT	include/ssv6200_aux.h	11433;"	d
+RLS_BUSY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33003;"	d
+RLS_BUSY_SZ	include/ssv6200_aux.h	11435;"	d
+RLS_BUSY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33005;"	d
+RLS_COUNT_CLR_HI	include/ssv6200_aux.h	11439;"	d
+RLS_COUNT_CLR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33009;"	d
+RLS_COUNT_CLR_I_MSK	include/ssv6200_aux.h	11437;"	d
+RLS_COUNT_CLR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33007;"	d
+RLS_COUNT_CLR_MSK	include/ssv6200_aux.h	11436;"	d
+RLS_COUNT_CLR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33006;"	d
+RLS_COUNT_CLR_SFT	include/ssv6200_aux.h	11438;"	d
+RLS_COUNT_CLR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33008;"	d
+RLS_COUNT_CLR_SZ	include/ssv6200_aux.h	11440;"	d
+RLS_COUNT_CLR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33010;"	d
+RLS_COUNT_HI	include/ssv6200_aux.h	11449;"	d
+RLS_COUNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33019;"	d
+RLS_COUNT_I_MSK	include/ssv6200_aux.h	11447;"	d
+RLS_COUNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33017;"	d
+RLS_COUNT_MSK	include/ssv6200_aux.h	11446;"	d
+RLS_COUNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33016;"	d
+RLS_COUNT_SFT	include/ssv6200_aux.h	11448;"	d
+RLS_COUNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33018;"	d
+RLS_COUNT_SZ	include/ssv6200_aux.h	11450;"	d
+RLS_COUNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33020;"	d
+RLS_ERR_CLR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34544;"	d
+RLS_ERR_CLR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34542;"	d
+RLS_ERR_CLR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34541;"	d
+RLS_ERR_CLR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34543;"	d
+RLS_ERR_CLR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34545;"	d
+RLS_ERR_HI	include/ssv6200_aux.h	17919;"	d
+RLS_ERR_ID_HI	include/ssv6200_aux.h	17939;"	d
+RLS_ERR_ID_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34564;"	d
+RLS_ERR_ID_I_MSK	include/ssv6200_aux.h	17937;"	d
+RLS_ERR_ID_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34562;"	d
+RLS_ERR_ID_MSK	include/ssv6200_aux.h	17936;"	d
+RLS_ERR_ID_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34561;"	d
+RLS_ERR_ID_SFT	include/ssv6200_aux.h	17938;"	d
+RLS_ERR_ID_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34563;"	d
+RLS_ERR_ID_SZ	include/ssv6200_aux.h	17940;"	d
+RLS_ERR_ID_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34565;"	d
+RLS_ERR_I_MSK	include/ssv6200_aux.h	17917;"	d
+RLS_ERR_MSK	include/ssv6200_aux.h	17916;"	d
+RLS_ERR_SFT	include/ssv6200_aux.h	17918;"	d
+RLS_ERR_STS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34534;"	d
+RLS_ERR_STS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34532;"	d
+RLS_ERR_STS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34531;"	d
+RLS_ERR_STS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34533;"	d
+RLS_ERR_STS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34535;"	d
+RLS_ERR_SZ	include/ssv6200_aux.h	17920;"	d
+RL_STATE_HI	include/ssv6200_aux.h	17929;"	d
+RL_STATE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34554;"	d
+RL_STATE_I_MSK	include/ssv6200_aux.h	17927;"	d
+RL_STATE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34552;"	d
+RL_STATE_MSK	include/ssv6200_aux.h	17926;"	d
+RL_STATE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34551;"	d
+RL_STATE_SFT	include/ssv6200_aux.h	17928;"	d
+RL_STATE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34553;"	d
+RL_STATE_SZ	include/ssv6200_aux.h	17930;"	d
+RL_STATE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34555;"	d
+ROMCRC32_GOLDEN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2454;"	d
+ROMCRC32_GOLDEN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2452;"	d
+ROMCRC32_GOLDEN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2451;"	d
+ROMCRC32_GOLDEN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2453;"	d
+ROMCRC32_GOLDEN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2455;"	d
+ROMCRC32_RESULT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2459;"	d
+ROMCRC32_RESULT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2457;"	d
+ROMCRC32_RESULT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2456;"	d
+ROMCRC32_RESULT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2458;"	d
+ROMCRC32_RESULT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2460;"	d
+ROM_END_INDEX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2449;"	d
+ROM_END_INDEX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2447;"	d
+ROM_END_INDEX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2446;"	d
+ROM_END_INDEX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2448;"	d
+ROM_END_INDEX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2450;"	d
+ROM_READ_PROT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1359;"	d
+ROM_READ_PROT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1357;"	d
+ROM_READ_PROT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1356;"	d
+ROM_READ_PROT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1358;"	d
+ROM_READ_PROT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1360;"	d
+ROM_START_INDEX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2444;"	d
+ROM_START_INDEX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2442;"	d
+ROM_START_INDEX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2441;"	d
+ROM_START_INDEX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2443;"	d
+ROM_START_INDEX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2445;"	d
+ROP_A_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3674;"	d
+ROP_A_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3672;"	d
+ROP_A_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3671;"	d
+ROP_A_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3673;"	d
+ROP_A_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3675;"	d
+RO_11B_CCA_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31819;"	d
+RO_11B_CCA_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31817;"	d
+RO_11B_CCA_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31816;"	d
+RO_11B_CCA_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31818;"	d
+RO_11B_CCA_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31820;"	d
+RO_11B_CRC_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31794;"	d
+RO_11B_CRC_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31792;"	d
+RO_11B_CRC_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31791;"	d
+RO_11B_CRC_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31793;"	d
+RO_11B_CRC_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31795;"	d
+RO_11B_CRC_CORRECT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31844;"	d
+RO_11B_CRC_CORRECT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31842;"	d
+RO_11B_CRC_CORRECT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31841;"	d
+RO_11B_CRC_CORRECT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31843;"	d
+RO_11B_CRC_CORRECT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31845;"	d
+RO_11B_FREQ_OS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31779;"	d
+RO_11B_FREQ_OS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31777;"	d
+RO_11B_FREQ_OS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31776;"	d
+RO_11B_FREQ_OS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31778;"	d
+RO_11B_FREQ_OS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31780;"	d
+RO_11B_LENGTH_FIELD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31824;"	d
+RO_11B_LENGTH_FIELD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31822;"	d
+RO_11B_LENGTH_FIELD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31821;"	d
+RO_11B_LENGTH_FIELD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31823;"	d
+RO_11B_LENGTH_FIELD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31825;"	d
+RO_11B_PACKET_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31814;"	d
+RO_11B_PACKET_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31812;"	d
+RO_11B_PACKET_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31811;"	d
+RO_11B_PACKET_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31813;"	d
+RO_11B_PACKET_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31815;"	d
+RO_11B_PACKET_ERR_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31804;"	d
+RO_11B_PACKET_ERR_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31802;"	d
+RO_11B_PACKET_ERR_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31801;"	d
+RO_11B_PACKET_ERR_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31803;"	d
+RO_11B_PACKET_ERR_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31805;"	d
+RO_11B_PACKET_ERR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31809;"	d
+RO_11B_PACKET_ERR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31807;"	d
+RO_11B_PACKET_ERR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31806;"	d
+RO_11B_PACKET_ERR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31808;"	d
+RO_11B_PACKET_ERR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31810;"	d
+RO_11B_RCPI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31789;"	d
+RO_11B_RCPI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31787;"	d
+RO_11B_RCPI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31786;"	d
+RO_11B_RCPI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31788;"	d
+RO_11B_RCPI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31790;"	d
+RO_11B_SERVICE_FIELD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31839;"	d
+RO_11B_SERVICE_FIELD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31837;"	d
+RO_11B_SERVICE_FIELD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31836;"	d
+RO_11B_SERVICE_FIELD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31838;"	d
+RO_11B_SERVICE_FIELD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31840;"	d
+RO_11B_SFD_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31799;"	d
+RO_11B_SFD_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31797;"	d
+RO_11B_SFD_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31796;"	d
+RO_11B_SFD_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31798;"	d
+RO_11B_SFD_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31800;"	d
+RO_11B_SFD_FIELD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31829;"	d
+RO_11B_SFD_FIELD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31827;"	d
+RO_11B_SFD_FIELD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31826;"	d
+RO_11B_SFD_FIELD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31828;"	d
+RO_11B_SFD_FIELD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31830;"	d
+RO_11B_SIGNAL_FIELD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31834;"	d
+RO_11B_SIGNAL_FIELD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31832;"	d
+RO_11B_SIGNAL_FIELD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31831;"	d
+RO_11B_SIGNAL_FIELD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31833;"	d
+RO_11B_SIGNAL_FIELD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31835;"	d
+RO_11B_SNR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31784;"	d
+RO_11B_SNR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31782;"	d
+RO_11B_SNR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31781;"	d
+RO_11B_SNR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31783;"	d
+RO_11B_SNR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31785;"	d
+RO_11GN_CCA_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32669;"	d
+RO_11GN_CCA_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32667;"	d
+RO_11GN_CCA_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32666;"	d
+RO_11GN_CCA_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32668;"	d
+RO_11GN_CCA_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32670;"	d
+RO_11GN_FREQ_OS_LTS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32639;"	d
+RO_11GN_FREQ_OS_LTS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32637;"	d
+RO_11GN_FREQ_OS_LTS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32636;"	d
+RO_11GN_FREQ_OS_LTS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32638;"	d
+RO_11GN_FREQ_OS_LTS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32640;"	d
+RO_11GN_HT_SIGNAL_FIELD_23_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32649;"	d
+RO_11GN_HT_SIGNAL_FIELD_23_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32647;"	d
+RO_11GN_HT_SIGNAL_FIELD_23_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32646;"	d
+RO_11GN_HT_SIGNAL_FIELD_23_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32648;"	d
+RO_11GN_HT_SIGNAL_FIELD_23_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32650;"	d
+RO_11GN_HT_SIGNAL_FIELD_47_24_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32644;"	d
+RO_11GN_HT_SIGNAL_FIELD_47_24_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32642;"	d
+RO_11GN_HT_SIGNAL_FIELD_47_24_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32641;"	d
+RO_11GN_HT_SIGNAL_FIELD_47_24_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32643;"	d
+RO_11GN_HT_SIGNAL_FIELD_47_24_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32645;"	d
+RO_11GN_L_SIGNAL_FIELD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32674;"	d
+RO_11GN_L_SIGNAL_FIELD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32672;"	d
+RO_11GN_L_SIGNAL_FIELD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32671;"	d
+RO_11GN_L_SIGNAL_FIELD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32673;"	d
+RO_11GN_L_SIGNAL_FIELD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32675;"	d
+RO_11GN_NOISE_PWR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32624;"	d
+RO_11GN_NOISE_PWR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32622;"	d
+RO_11GN_NOISE_PWR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32621;"	d
+RO_11GN_NOISE_PWR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32623;"	d
+RO_11GN_NOISE_PWR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32625;"	d
+RO_11GN_PACKET_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32664;"	d
+RO_11GN_PACKET_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32662;"	d
+RO_11GN_PACKET_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32661;"	d
+RO_11GN_PACKET_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32663;"	d
+RO_11GN_PACKET_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32665;"	d
+RO_11GN_PACKET_ERR_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32654;"	d
+RO_11GN_PACKET_ERR_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32652;"	d
+RO_11GN_PACKET_ERR_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32651;"	d
+RO_11GN_PACKET_ERR_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32653;"	d
+RO_11GN_PACKET_ERR_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32655;"	d
+RO_11GN_RCPI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32629;"	d
+RO_11GN_RCPI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32627;"	d
+RO_11GN_RCPI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32626;"	d
+RO_11GN_RCPI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32628;"	d
+RO_11GN_RCPI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32630;"	d
+RO_11GN_SERVICE_FIELD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32659;"	d
+RO_11GN_SERVICE_FIELD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32657;"	d
+RO_11GN_SERVICE_FIELD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32656;"	d
+RO_11GN_SERVICE_FIELD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32658;"	d
+RO_11GN_SERVICE_FIELD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32660;"	d
+RO_11GN_SIGNAL_PWR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32634;"	d
+RO_11GN_SIGNAL_PWR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32632;"	d
+RO_11GN_SIGNAL_PWR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32631;"	d
+RO_11GN_SIGNAL_PWR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32633;"	d
+RO_11GN_SIGNAL_PWR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32635;"	d
+RO_11GN_SNR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32619;"	d
+RO_11GN_SNR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32617;"	d
+RO_11GN_SNR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32616;"	d
+RO_11GN_SNR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32618;"	d
+RO_11GN_SNR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32620;"	d
+RO_2ND_ED_STATE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30699;"	d
+RO_2ND_ED_STATE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30697;"	d
+RO_2ND_ED_STATE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30696;"	d
+RO_2ND_ED_STATE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30698;"	d
+RO_2ND_ED_STATE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30700;"	d
+RO_5G_DCCAL_DONE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27529;"	d
+RO_5G_DCCAL_DONE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27527;"	d
+RO_5G_DCCAL_DONE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27526;"	d
+RO_5G_DCCAL_DONE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27528;"	d
+RO_5G_DCCAL_DONE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27530;"	d
+RO_5G_RXIQ_DONE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27524;"	d
+RO_5G_RXIQ_DONE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27522;"	d
+RO_5G_RXIQ_DONE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27521;"	d
+RO_5G_RXIQ_DONE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27523;"	d
+RO_5G_RXIQ_DONE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27525;"	d
+RO_5G_TXDC_DONE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27514;"	d
+RO_5G_TXDC_DONE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27512;"	d
+RO_5G_TXDC_DONE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27511;"	d
+RO_5G_TXDC_DONE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27513;"	d
+RO_5G_TXDC_DONE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27515;"	d
+RO_5G_TXIQ_DONE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27519;"	d
+RO_5G_TXIQ_DONE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27517;"	d
+RO_5G_TXIQ_DONE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27516;"	d
+RO_5G_TXIQ_DONE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27518;"	d
+RO_5G_TXIQ_DONE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27520;"	d
+RO_ABBPGA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27764;"	d
+RO_ABBPGA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27762;"	d
+RO_ABBPGA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27761;"	d
+RO_ABBPGA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27763;"	d
+RO_ABBPGA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27765;"	d
+RO_ACT_MASK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6779;"	d
+RO_ACT_MASK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6777;"	d
+RO_ACT_MASK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6776;"	d
+RO_ACT_MASK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6778;"	d
+RO_ACT_MASK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6780;"	d
+RO_AD_VBAT_OK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29854;"	d
+RO_AD_VBAT_OK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29852;"	d
+RO_AD_VBAT_OK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29851;"	d
+RO_AD_VBAT_OK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29853;"	d
+RO_AD_VBAT_OK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29855;"	d
+RO_AGC_START_80M_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31449;"	d
+RO_AGC_START_80M_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31447;"	d
+RO_AGC_START_80M_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31446;"	d
+RO_AGC_START_80M_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31448;"	d
+RO_AGC_START_80M_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31450;"	d
+RO_AMPDU_PACKET_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32679;"	d
+RO_AMPDU_PACKET_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32677;"	d
+RO_AMPDU_PACKET_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32676;"	d
+RO_AMPDU_PACKET_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32678;"	d
+RO_AMPDU_PACKET_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32680;"	d
+RO_AMPDU_PACKET_ERR_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32684;"	d
+RO_AMPDU_PACKET_ERR_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32682;"	d
+RO_AMPDU_PACKET_ERR_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32681;"	d
+RO_AMPDU_PACKET_ERR_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32683;"	d
+RO_AMPDU_PACKET_ERR_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32685;"	d
+RO_AMP_O_HI	include/ssv6200_aux.h	15644;"	d
+RO_AMP_O_I_MSK	include/ssv6200_aux.h	15642;"	d
+RO_AMP_O_MSK	include/ssv6200_aux.h	15641;"	d
+RO_AMP_O_SFT	include/ssv6200_aux.h	15643;"	d
+RO_AMP_O_SZ	include/ssv6200_aux.h	15645;"	d
+RO_BIST_DONE_CCFO_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32294;"	d
+RO_BIST_DONE_CCFO_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32292;"	d
+RO_BIST_DONE_CCFO_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32291;"	d
+RO_BIST_DONE_CCFO_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32293;"	d
+RO_BIST_DONE_CCFO_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32295;"	d
+RO_BIST_DONE_CCFO_1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32284;"	d
+RO_BIST_DONE_CCFO_1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32282;"	d
+RO_BIST_DONE_CCFO_1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32281;"	d
+RO_BIST_DONE_CCFO_1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32283;"	d
+RO_BIST_DONE_CCFO_1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32285;"	d
+RO_BIST_DONE_RX_FFT_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31414;"	d
+RO_BIST_DONE_RX_FFT_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31412;"	d
+RO_BIST_DONE_RX_FFT_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31411;"	d
+RO_BIST_DONE_RX_FFT_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31413;"	d
+RO_BIST_DONE_RX_FFT_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31415;"	d
+RO_BIST_DONE_RX_FFT_1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31404;"	d
+RO_BIST_DONE_RX_FFT_1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31402;"	d
+RO_BIST_DONE_RX_FFT_1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31401;"	d
+RO_BIST_DONE_RX_FFT_1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31403;"	d
+RO_BIST_DONE_RX_FFT_1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31405;"	d
+RO_BIST_DONE_TX_FFT_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31904;"	d
+RO_BIST_DONE_TX_FFT_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31902;"	d
+RO_BIST_DONE_TX_FFT_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31901;"	d
+RO_BIST_DONE_TX_FFT_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31903;"	d
+RO_BIST_DONE_TX_FFT_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31905;"	d
+RO_BIST_DONE_TX_FFT_1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31894;"	d
+RO_BIST_DONE_TX_FFT_1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31892;"	d
+RO_BIST_DONE_TX_FFT_1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31891;"	d
+RO_BIST_DONE_TX_FFT_1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31893;"	d
+RO_BIST_DONE_TX_FFT_1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31895;"	d
+RO_BIST_DONE_VTB_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32344;"	d
+RO_BIST_DONE_VTB_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32342;"	d
+RO_BIST_DONE_VTB_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32341;"	d
+RO_BIST_DONE_VTB_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32343;"	d
+RO_BIST_DONE_VTB_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32345;"	d
+RO_BIST_DONE_VTB_1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32334;"	d
+RO_BIST_DONE_VTB_1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32332;"	d
+RO_BIST_DONE_VTB_1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32331;"	d
+RO_BIST_DONE_VTB_1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32333;"	d
+RO_BIST_DONE_VTB_1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32335;"	d
+RO_BIST_DONE_VTB_2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32324;"	d
+RO_BIST_DONE_VTB_2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32322;"	d
+RO_BIST_DONE_VTB_2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32321;"	d
+RO_BIST_DONE_VTB_2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32323;"	d
+RO_BIST_DONE_VTB_2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32325;"	d
+RO_BIST_DONE_VTB_3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32314;"	d
+RO_BIST_DONE_VTB_3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32312;"	d
+RO_BIST_DONE_VTB_3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32311;"	d
+RO_BIST_DONE_VTB_3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32313;"	d
+RO_BIST_DONE_VTB_3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32315;"	d
+RO_BIST_FAIL_CCFO_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32299;"	d
+RO_BIST_FAIL_CCFO_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32297;"	d
+RO_BIST_FAIL_CCFO_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32296;"	d
+RO_BIST_FAIL_CCFO_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32298;"	d
+RO_BIST_FAIL_CCFO_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32300;"	d
+RO_BIST_FAIL_CCFO_1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32289;"	d
+RO_BIST_FAIL_CCFO_1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32287;"	d
+RO_BIST_FAIL_CCFO_1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32286;"	d
+RO_BIST_FAIL_CCFO_1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32288;"	d
+RO_BIST_FAIL_CCFO_1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32290;"	d
+RO_BIST_FAIL_RX_FFT_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31419;"	d
+RO_BIST_FAIL_RX_FFT_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31417;"	d
+RO_BIST_FAIL_RX_FFT_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31416;"	d
+RO_BIST_FAIL_RX_FFT_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31418;"	d
+RO_BIST_FAIL_RX_FFT_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31420;"	d
+RO_BIST_FAIL_RX_FFT_1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31409;"	d
+RO_BIST_FAIL_RX_FFT_1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31407;"	d
+RO_BIST_FAIL_RX_FFT_1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31406;"	d
+RO_BIST_FAIL_RX_FFT_1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31408;"	d
+RO_BIST_FAIL_RX_FFT_1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31410;"	d
+RO_BIST_FAIL_TX_FFT_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31909;"	d
+RO_BIST_FAIL_TX_FFT_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31907;"	d
+RO_BIST_FAIL_TX_FFT_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31906;"	d
+RO_BIST_FAIL_TX_FFT_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31908;"	d
+RO_BIST_FAIL_TX_FFT_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31910;"	d
+RO_BIST_FAIL_TX_FFT_1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31899;"	d
+RO_BIST_FAIL_TX_FFT_1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31897;"	d
+RO_BIST_FAIL_TX_FFT_1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31896;"	d
+RO_BIST_FAIL_TX_FFT_1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31898;"	d
+RO_BIST_FAIL_TX_FFT_1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31900;"	d
+RO_BIST_FAIL_VTB_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32349;"	d
+RO_BIST_FAIL_VTB_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32347;"	d
+RO_BIST_FAIL_VTB_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32346;"	d
+RO_BIST_FAIL_VTB_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32348;"	d
+RO_BIST_FAIL_VTB_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32350;"	d
+RO_BIST_FAIL_VTB_1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32339;"	d
+RO_BIST_FAIL_VTB_1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32337;"	d
+RO_BIST_FAIL_VTB_1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32336;"	d
+RO_BIST_FAIL_VTB_1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32338;"	d
+RO_BIST_FAIL_VTB_1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32340;"	d
+RO_BIST_FAIL_VTB_2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32329;"	d
+RO_BIST_FAIL_VTB_2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32327;"	d
+RO_BIST_FAIL_VTB_2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32326;"	d
+RO_BIST_FAIL_VTB_2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32328;"	d
+RO_BIST_FAIL_VTB_2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32330;"	d
+RO_BIST_FAIL_VTB_3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32319;"	d
+RO_BIST_FAIL_VTB_3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32317;"	d
+RO_BIST_FAIL_VTB_3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32316;"	d
+RO_BIST_FAIL_VTB_3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32318;"	d
+RO_BIST_FAIL_VTB_3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32320;"	d
+RO_BT_DCCAL_DONE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27489;"	d
+RO_BT_DCCAL_DONE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27487;"	d
+RO_BT_DCCAL_DONE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27486;"	d
+RO_BT_DCCAL_DONE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27488;"	d
+RO_BT_DCCAL_DONE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27490;"	d
+RO_CAND_MASK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6784;"	d
+RO_CAND_MASK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6782;"	d
+RO_CAND_MASK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6781;"	d
+RO_CAND_MASK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6783;"	d
+RO_CAND_MASK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6785;"	d
+RO_CCA_PWR_MA_11B_HI	include/ssv6200_aux.h	13504;"	d
+RO_CCA_PWR_MA_11B_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30689;"	d
+RO_CCA_PWR_MA_11B_I_MSK	include/ssv6200_aux.h	13502;"	d
+RO_CCA_PWR_MA_11B_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30687;"	d
+RO_CCA_PWR_MA_11B_MSK	include/ssv6200_aux.h	13501;"	d
+RO_CCA_PWR_MA_11B_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30686;"	d
+RO_CCA_PWR_MA_11B_SFT	include/ssv6200_aux.h	13503;"	d
+RO_CCA_PWR_MA_11B_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30688;"	d
+RO_CCA_PWR_MA_11B_SZ	include/ssv6200_aux.h	13505;"	d
+RO_CCA_PWR_MA_11B_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30690;"	d
+RO_CCA_PWR_MA_11GN_HI	include/ssv6200_aux.h	13494;"	d
+RO_CCA_PWR_MA_11GN_HT20_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30684;"	d
+RO_CCA_PWR_MA_11GN_HT20_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30682;"	d
+RO_CCA_PWR_MA_11GN_HT20_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30681;"	d
+RO_CCA_PWR_MA_11GN_HT20_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30683;"	d
+RO_CCA_PWR_MA_11GN_HT20_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30685;"	d
+RO_CCA_PWR_MA_11GN_HT40_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30679;"	d
+RO_CCA_PWR_MA_11GN_HT40_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30677;"	d
+RO_CCA_PWR_MA_11GN_HT40_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30676;"	d
+RO_CCA_PWR_MA_11GN_HT40_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30678;"	d
+RO_CCA_PWR_MA_11GN_HT40_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30680;"	d
+RO_CCA_PWR_MA_11GN_I_MSK	include/ssv6200_aux.h	13492;"	d
+RO_CCA_PWR_MA_11GN_MSK	include/ssv6200_aux.h	13491;"	d
+RO_CCA_PWR_MA_11GN_SFT	include/ssv6200_aux.h	13493;"	d
+RO_CCA_PWR_MA_11GN_SZ	include/ssv6200_aux.h	13495;"	d
+RO_CSTATE_AGC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31444;"	d
+RO_CSTATE_AGC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31442;"	d
+RO_CSTATE_AGC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31441;"	d
+RO_CSTATE_AGC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31443;"	d
+RO_CSTATE_AGC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31445;"	d
+RO_CSTATE_PKT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31434;"	d
+RO_CSTATE_PKT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31432;"	d
+RO_CSTATE_PKT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31431;"	d
+RO_CSTATE_PKT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31433;"	d
+RO_CSTATE_PKT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31435;"	d
+RO_CSTATE_RX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31454;"	d
+RO_CSTATE_RX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31452;"	d
+RO_CSTATE_RX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31451;"	d
+RO_CSTATE_RX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31453;"	d
+RO_CSTATE_RX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31455;"	d
+RO_CSTATE_TX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31464;"	d
+RO_CSTATE_TX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31462;"	d
+RO_CSTATE_TX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31461;"	d
+RO_CSTATE_TX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31463;"	d
+RO_CSTATE_TX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31465;"	d
+RO_DA_RX_AGC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27774;"	d
+RO_DA_RX_AGC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27772;"	d
+RO_DA_RX_AGC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27771;"	d
+RO_DA_RX_AGC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27773;"	d
+RO_DA_RX_AGC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27775;"	d
+RO_DC_CAL_I_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27804;"	d
+RO_DC_CAL_I_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27802;"	d
+RO_DC_CAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27801;"	d
+RO_DC_CAL_I_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27803;"	d
+RO_DC_CAL_I_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27805;"	d
+RO_DC_CAL_Q_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27799;"	d
+RO_DC_CAL_Q_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27797;"	d
+RO_DC_CAL_Q_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27796;"	d
+RO_DC_CAL_Q_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27798;"	d
+RO_DC_CAL_Q_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27800;"	d
+RO_DPD_GAIN_HI	include/ssv6200_aux.h	16034;"	d
+RO_DPD_GAIN_I_MSK	include/ssv6200_aux.h	16032;"	d
+RO_DPD_GAIN_MSK	include/ssv6200_aux.h	16031;"	d
+RO_DPD_GAIN_SFT	include/ssv6200_aux.h	16033;"	d
+RO_DPD_GAIN_SZ	include/ssv6200_aux.h	16035;"	d
+RO_EDCCA_PRIMARY_PRD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30844;"	d
+RO_EDCCA_PRIMARY_PRD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30842;"	d
+RO_EDCCA_PRIMARY_PRD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30841;"	d
+RO_EDCCA_PRIMARY_PRD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30843;"	d
+RO_EDCCA_PRIMARY_PRD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30845;"	d
+RO_EDCCA_SECONDARY_PRD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30854;"	d
+RO_EDCCA_SECONDARY_PRD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30852;"	d
+RO_EDCCA_SECONDARY_PRD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30851;"	d
+RO_EDCCA_SECONDARY_PRD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30853;"	d
+RO_EDCCA_SECONDARY_PRD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30855;"	d
+RO_ED_STATE_HI	include/ssv6200_aux.h	13499;"	d
+RO_ED_STATE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30694;"	d
+RO_ED_STATE_I_MSK	include/ssv6200_aux.h	13497;"	d
+RO_ED_STATE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30692;"	d
+RO_ED_STATE_MSK	include/ssv6200_aux.h	13496;"	d
+RO_ED_STATE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30691;"	d
+RO_ED_STATE_SFT	include/ssv6200_aux.h	13498;"	d
+RO_ED_STATE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30693;"	d
+RO_ED_STATE_SZ	include/ssv6200_aux.h	13500;"	d
+RO_ED_STATE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30695;"	d
+RO_FDB_CDELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29734;"	d
+RO_FDB_CDELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29732;"	d
+RO_FDB_CDELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29731;"	d
+RO_FDB_CDELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29733;"	d
+RO_FDB_CDELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29735;"	d
+RO_FDB_FDELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29739;"	d
+RO_FDB_FDELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29737;"	d
+RO_FDB_FDELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29736;"	d
+RO_FDB_FDELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29738;"	d
+RO_FDB_FDELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29740;"	d
+RO_FDB_PHASESWAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29744;"	d
+RO_FDB_PHASESWAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29742;"	d
+RO_FDB_PHASESWAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29741;"	d
+RO_FDB_PHASESWAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29743;"	d
+RO_FDB_PHASESWAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29745;"	d
+RO_FFT_ENRG_RDY_HI	include/ssv6200_aux.h	15624;"	d
+RO_FFT_ENRG_RDY_I_MSK	include/ssv6200_aux.h	15622;"	d
+RO_FFT_ENRG_RDY_MSK	include/ssv6200_aux.h	15621;"	d
+RO_FFT_ENRG_RDY_SFT	include/ssv6200_aux.h	15623;"	d
+RO_FFT_ENRG_RDY_SZ	include/ssv6200_aux.h	15625;"	d
+RO_FREQ_OS_LTS_HI	include/ssv6200_aux.h	15239;"	d
+RO_FREQ_OS_LTS_I_MSK	include/ssv6200_aux.h	15237;"	d
+RO_FREQ_OS_LTS_MSK	include/ssv6200_aux.h	15236;"	d
+RO_FREQ_OS_LTS_SFT	include/ssv6200_aux.h	15238;"	d
+RO_FREQ_OS_LTS_SZ	include/ssv6200_aux.h	15240;"	d
+RO_FSM_MTXDMA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6799;"	d
+RO_FSM_MTXDMA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6797;"	d
+RO_FSM_MTXDMA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6796;"	d
+RO_FSM_MTXDMA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6798;"	d
+RO_FSM_MTXDMA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6800;"	d
+RO_FSM_MTXHALT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6794;"	d
+RO_FSM_MTXHALT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6792;"	d
+RO_FSM_MTXHALT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6791;"	d
+RO_FSM_MTXHALT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6793;"	d
+RO_FSM_MTXHALT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6795;"	d
+RO_FSM_MTXPHYTX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6804;"	d
+RO_FSM_MTXPHYTX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6802;"	d
+RO_FSM_MTXPHYTX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6801;"	d
+RO_FSM_MTXPHYTX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6803;"	d
+RO_FSM_MTXPHYTX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6805;"	d
+RO_FSM_MTXPTC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6774;"	d
+RO_FSM_MTXPTC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6772;"	d
+RO_FSM_MTXPTC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6771;"	d
+RO_FSM_MTXPTC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6773;"	d
+RO_FSM_MTXPTC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6775;"	d
+RO_GAIN_EST_RDY_HI	include/ssv6200_aux.h	15639;"	d
+RO_GAIN_EST_RDY_I_MSK	include/ssv6200_aux.h	15637;"	d
+RO_GAIN_EST_RDY_MSK	include/ssv6200_aux.h	15636;"	d
+RO_GAIN_EST_RDY_SFT	include/ssv6200_aux.h	15638;"	d
+RO_GAIN_EST_RDY_SZ	include/ssv6200_aux.h	15640;"	d
+RO_GAIN_TX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27759;"	d
+RO_GAIN_TX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27757;"	d
+RO_GAIN_TX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27756;"	d
+RO_GAIN_TX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27758;"	d
+RO_GAIN_TX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27760;"	d
+RO_GEMINIA_BT_DCCAL_DONE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13719;"	d
+RO_GEMINIA_BT_DCCAL_DONE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13717;"	d
+RO_GEMINIA_BT_DCCAL_DONE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13716;"	d
+RO_GEMINIA_BT_DCCAL_DONE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13718;"	d
+RO_GEMINIA_BT_DCCAL_DONE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13720;"	d
+RO_GEMINIA_FDB_CDELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14069;"	d
+RO_GEMINIA_FDB_CDELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14067;"	d
+RO_GEMINIA_FDB_CDELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14066;"	d
+RO_GEMINIA_FDB_CDELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14068;"	d
+RO_GEMINIA_FDB_CDELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14070;"	d
+RO_GEMINIA_FDB_FDELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14074;"	d
+RO_GEMINIA_FDB_FDELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14072;"	d
+RO_GEMINIA_FDB_FDELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14071;"	d
+RO_GEMINIA_FDB_FDELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14073;"	d
+RO_GEMINIA_FDB_FDELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14075;"	d
+RO_GEMINIA_FDB_PHASESWAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14079;"	d
+RO_GEMINIA_FDB_PHASESWAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14077;"	d
+RO_GEMINIA_FDB_PHASESWAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14076;"	d
+RO_GEMINIA_FDB_PHASESWAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14078;"	d
+RO_GEMINIA_FDB_PHASESWAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14080;"	d
+RO_GEMINIA_PMU_WAKE_TRIG_EVENT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14029;"	d
+RO_GEMINIA_PMU_WAKE_TRIG_EVENT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14027;"	d
+RO_GEMINIA_PMU_WAKE_TRIG_EVENT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14026;"	d
+RO_GEMINIA_PMU_WAKE_TRIG_EVENT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14028;"	d
+RO_GEMINIA_PMU_WAKE_TRIG_EVENT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14030;"	d
+RO_GEMINIA_RCCAL_DONE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13724;"	d
+RO_GEMINIA_RCCAL_DONE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13722;"	d
+RO_GEMINIA_RCCAL_DONE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13721;"	d
+RO_GEMINIA_RCCAL_DONE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13723;"	d
+RO_GEMINIA_RCCAL_DONE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13725;"	d
+RO_GEMINIA_RTC_INT_ALARM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14054;"	d
+RO_GEMINIA_RTC_INT_ALARM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14052;"	d
+RO_GEMINIA_RTC_INT_ALARM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14051;"	d
+RO_GEMINIA_RTC_INT_ALARM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14053;"	d
+RO_GEMINIA_RTC_INT_ALARM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14055;"	d
+RO_GEMINIA_RTC_INT_SEC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14049;"	d
+RO_GEMINIA_RTC_INT_SEC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14047;"	d
+RO_GEMINIA_RTC_INT_SEC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14046;"	d
+RO_GEMINIA_RTC_INT_SEC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14048;"	d
+RO_GEMINIA_RTC_INT_SEC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14050;"	d
+RO_GEMINIA_RTC_OSC_CAL_RES_RDY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13994;"	d
+RO_GEMINIA_RTC_OSC_CAL_RES_RDY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13992;"	d
+RO_GEMINIA_RTC_OSC_CAL_RES_RDY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13991;"	d
+RO_GEMINIA_RTC_OSC_CAL_RES_RDY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13993;"	d
+RO_GEMINIA_RTC_OSC_CAL_RES_RDY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13995;"	d
+RO_GEMINIA_RTC_OSC_RES_SW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13989;"	d
+RO_GEMINIA_RTC_OSC_RES_SW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13987;"	d
+RO_GEMINIA_RTC_OSC_RES_SW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13986;"	d
+RO_GEMINIA_RTC_OSC_RES_SW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13988;"	d
+RO_GEMINIA_RTC_OSC_RES_SW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13990;"	d
+RO_GEMINIA_RTC_TICK_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	14034;"	d
+RO_GEMINIA_RTC_TICK_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14032;"	d
+RO_GEMINIA_RTC_TICK_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	14031;"	d
+RO_GEMINIA_RTC_TICK_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	14033;"	d
+RO_GEMINIA_RTC_TICK_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	14035;"	d
+RO_GEMINIA_RXIQ_DONE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13739;"	d
+RO_GEMINIA_RXIQ_DONE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13737;"	d
+RO_GEMINIA_RXIQ_DONE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13736;"	d
+RO_GEMINIA_RXIQ_DONE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13738;"	d
+RO_GEMINIA_RXIQ_DONE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13740;"	d
+RO_GEMINIA_TXDC_DONE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13729;"	d
+RO_GEMINIA_TXDC_DONE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13727;"	d
+RO_GEMINIA_TXDC_DONE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13726;"	d
+RO_GEMINIA_TXDC_DONE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13728;"	d
+RO_GEMINIA_TXDC_DONE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13730;"	d
+RO_GEMINIA_TXIQ_DONE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13734;"	d
+RO_GEMINIA_TXIQ_DONE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13732;"	d
+RO_GEMINIA_TXIQ_DONE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13731;"	d
+RO_GEMINIA_TXIQ_DONE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13733;"	d
+RO_GEMINIA_TXIQ_DONE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13735;"	d
+RO_GEMINIA_WF_DCCAL_DONE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	13714;"	d
+RO_GEMINIA_WF_DCCAL_DONE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13712;"	d
+RO_GEMINIA_WF_DCCAL_DONE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	13711;"	d
+RO_GEMINIA_WF_DCCAL_DONE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	13713;"	d
+RO_GEMINIA_WF_DCCAL_DONE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	13715;"	d
+RO_GP_DIV_RDY_HI	include/ssv6200_aux.h	15634;"	d
+RO_GP_DIV_RDY_I_MSK	include/ssv6200_aux.h	15632;"	d
+RO_GP_DIV_RDY_MSK	include/ssv6200_aux.h	15631;"	d
+RO_GP_DIV_RDY_SFT	include/ssv6200_aux.h	15633;"	d
+RO_GP_DIV_RDY_SZ	include/ssv6200_aux.h	15635;"	d
+RO_HS3W_SX_CHANNEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27749;"	d
+RO_HS3W_SX_CHANNEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27747;"	d
+RO_HS3W_SX_CHANNEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27746;"	d
+RO_HS3W_SX_CHANNEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27748;"	d
+RO_HS3W_SX_CHANNEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27750;"	d
+RO_HS3W_SX_RFCH_MAP_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27754;"	d
+RO_HS3W_SX_RFCH_MAP_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27752;"	d
+RO_HS3W_SX_RFCH_MAP_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27751;"	d
+RO_HS3W_SX_RFCH_MAP_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27753;"	d
+RO_HS3W_SX_RFCH_MAP_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27755;"	d
+RO_HS3W_SX_RFCTRL_CH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27779;"	d
+RO_HS3W_SX_RFCTRL_CH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27777;"	d
+RO_HS3W_SX_RFCTRL_CH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27776;"	d
+RO_HS3W_SX_RFCTRL_CH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27778;"	d
+RO_HS3W_SX_RFCTRL_CH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27780;"	d
+RO_HS3W_SX_RFCTRL_F_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27784;"	d
+RO_HS3W_SX_RFCTRL_F_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27782;"	d
+RO_HS3W_SX_RFCTRL_F_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27781;"	d
+RO_HS3W_SX_RFCTRL_F_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27783;"	d
+RO_HS3W_SX_RFCTRL_F_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27785;"	d
+RO_HT_MCS_40M_HI	include/ssv6200_aux.h	15284;"	d
+RO_HT_MCS_40M_I_MSK	include/ssv6200_aux.h	15282;"	d
+RO_HT_MCS_40M_MSK	include/ssv6200_aux.h	15281;"	d
+RO_HT_MCS_40M_SFT	include/ssv6200_aux.h	15283;"	d
+RO_HT_MCS_40M_SZ	include/ssv6200_aux.h	15285;"	d
+RO_IFSAIR1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7189;"	d
+RO_IFSAIR1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7187;"	d
+RO_IFSAIR1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7186;"	d
+RO_IFSAIR1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7188;"	d
+RO_IFSAIR1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7190;"	d
+RO_IFSAIR2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7194;"	d
+RO_IFSAIR2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7192;"	d
+RO_IFSAIR2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7191;"	d
+RO_IFSAIR2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7193;"	d
+RO_IFSAIR2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7195;"	d
+RO_IFSST0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7424;"	d
+RO_IFSST0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7422;"	d
+RO_IFSST0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7421;"	d
+RO_IFSST0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7423;"	d
+RO_IFSST0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7425;"	d
+RO_IFSST1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7429;"	d
+RO_IFSST1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7427;"	d
+RO_IFSST1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7426;"	d
+RO_IFSST1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7428;"	d
+RO_IFSST1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7430;"	d
+RO_IFSST2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7434;"	d
+RO_IFSST2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7432;"	d
+RO_IFSST2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7431;"	d
+RO_IFSST2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7433;"	d
+RO_IFSST2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7435;"	d
+RO_IFSST3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7439;"	d
+RO_IFSST3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7437;"	d
+RO_IFSST3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7436;"	d
+RO_IFSST3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7438;"	d
+RO_IFSST3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7440;"	d
+RO_INTRP_RX_BEACON_LOSS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31359;"	d
+RO_INTRP_RX_BEACON_LOSS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31357;"	d
+RO_INTRP_RX_BEACON_LOSS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31356;"	d
+RO_INTRP_RX_BEACON_LOSS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31358;"	d
+RO_INTRP_RX_BEACON_LOSS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31360;"	d
+RO_INTRP_RX_LOSS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31349;"	d
+RO_INTRP_RX_LOSS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31347;"	d
+RO_INTRP_RX_LOSS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31346;"	d
+RO_INTRP_RX_LOSS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31348;"	d
+RO_INTRP_RX_LOSS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31350;"	d
+RO_INTRUP_RX_11B_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31774;"	d
+RO_INTRUP_RX_11B_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31772;"	d
+RO_INTRUP_RX_11B_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31771;"	d
+RO_INTRUP_RX_11B_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31773;"	d
+RO_INTRUP_RX_11B_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31775;"	d
+RO_INTRUP_RX_11GN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32604;"	d
+RO_INTRUP_RX_11GN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32602;"	d
+RO_INTRUP_RX_11GN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32601;"	d
+RO_INTRUP_RX_11GN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32603;"	d
+RO_INTRUP_RX_11GN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32605;"	d
+RO_IQCAL_ALPHA_ESTM_RDY_HI	include/ssv6200_aux.h	15609;"	d
+RO_IQCAL_ALPHA_ESTM_RDY_I_MSK	include/ssv6200_aux.h	15607;"	d
+RO_IQCAL_ALPHA_ESTM_RDY_MSK	include/ssv6200_aux.h	15606;"	d
+RO_IQCAL_ALPHA_ESTM_RDY_SFT	include/ssv6200_aux.h	15608;"	d
+RO_IQCAL_ALPHA_ESTM_RDY_SZ	include/ssv6200_aux.h	15610;"	d
+RO_IQCAL_DC_RDY_HI	include/ssv6200_aux.h	15614;"	d
+RO_IQCAL_DC_RDY_I_MSK	include/ssv6200_aux.h	15612;"	d
+RO_IQCAL_DC_RDY_MSK	include/ssv6200_aux.h	15611;"	d
+RO_IQCAL_DC_RDY_SFT	include/ssv6200_aux.h	15613;"	d
+RO_IQCAL_DC_RDY_SZ	include/ssv6200_aux.h	15615;"	d
+RO_IQCAL_IQCOL_RDY_HI	include/ssv6200_aux.h	15604;"	d
+RO_IQCAL_IQCOL_RDY_I_MSK	include/ssv6200_aux.h	15602;"	d
+RO_IQCAL_IQCOL_RDY_MSK	include/ssv6200_aux.h	15601;"	d
+RO_IQCAL_IQCOL_RDY_SFT	include/ssv6200_aux.h	15603;"	d
+RO_IQCAL_IQCOL_RDY_SZ	include/ssv6200_aux.h	15605;"	d
+RO_IQCAL_MULT_RDY_HI	include/ssv6200_aux.h	15619;"	d
+RO_IQCAL_MULT_RDY_I_MSK	include/ssv6200_aux.h	15617;"	d
+RO_IQCAL_MULT_RDY_MSK	include/ssv6200_aux.h	15616;"	d
+RO_IQCAL_MULT_RDY_SFT	include/ssv6200_aux.h	15618;"	d
+RO_IQCAL_MULT_RDY_SZ	include/ssv6200_aux.h	15620;"	d
+RO_IQCAL_O_HI	include/ssv6200_aux.h	15594;"	d
+RO_IQCAL_O_I_MSK	include/ssv6200_aux.h	15592;"	d
+RO_IQCAL_O_MSK	include/ssv6200_aux.h	15591;"	d
+RO_IQCAL_O_SFT	include/ssv6200_aux.h	15593;"	d
+RO_IQCAL_O_SZ	include/ssv6200_aux.h	15595;"	d
+RO_IQCAL_SPRM_RDY_HI	include/ssv6200_aux.h	15599;"	d
+RO_IQCAL_SPRM_RDY_I_MSK	include/ssv6200_aux.h	15597;"	d
+RO_IQCAL_SPRM_RDY_MSK	include/ssv6200_aux.h	15596;"	d
+RO_IQCAL_SPRM_RDY_SFT	include/ssv6200_aux.h	15598;"	d
+RO_IQCAL_SPRM_RDY_SZ	include/ssv6200_aux.h	15600;"	d
+RO_I_DC_OUT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30804;"	d
+RO_I_DC_OUT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30802;"	d
+RO_I_DC_OUT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30801;"	d
+RO_I_DC_OUT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30803;"	d
+RO_I_DC_OUT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30805;"	d
+RO_L_RATE_40M_HI	include/ssv6200_aux.h	15289;"	d
+RO_L_RATE_40M_I_MSK	include/ssv6200_aux.h	15287;"	d
+RO_L_RATE_40M_MSK	include/ssv6200_aux.h	15286;"	d
+RO_L_RATE_40M_SFT	include/ssv6200_aux.h	15288;"	d
+RO_L_RATE_40M_SZ	include/ssv6200_aux.h	15290;"	d
+RO_MAC_PHY_TRX_EN_SYNC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31469;"	d
+RO_MAC_PHY_TRX_EN_SYNC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31467;"	d
+RO_MAC_PHY_TRX_EN_SYNC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31466;"	d
+RO_MAC_PHY_TRX_EN_SYNC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31468;"	d
+RO_MAC_PHY_TRX_EN_SYNC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31470;"	d
+RO_MAC_TX_FIFO_WEMPTY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7389;"	d
+RO_MAC_TX_FIFO_WEMPTY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7387;"	d
+RO_MAC_TX_FIFO_WEMPTY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7386;"	d
+RO_MAC_TX_FIFO_WEMPTY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7388;"	d
+RO_MAC_TX_FIFO_WEMPTY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7390;"	d
+RO_MAC_TX_FIFO_WFULL_MX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7384;"	d
+RO_MAC_TX_FIFO_WFULL_MX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7382;"	d
+RO_MAC_TX_FIFO_WFULL_MX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7381;"	d
+RO_MAC_TX_FIFO_WFULL_MX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7383;"	d
+RO_MAC_TX_FIFO_WFULL_MX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7385;"	d
+RO_MAC_TX_FIFO_WINC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7379;"	d
+RO_MAC_TX_FIFO_WINC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7377;"	d
+RO_MAC_TX_FIFO_WINC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7376;"	d
+RO_MAC_TX_FIFO_WINC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7378;"	d
+RO_MAC_TX_FIFO_WINC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7380;"	d
+RO_MODE_REG_OUT_16_HI	include/ssv6200_aux.h	13994;"	d
+RO_MODE_REG_OUT_16_I_MSK	include/ssv6200_aux.h	13992;"	d
+RO_MODE_REG_OUT_16_MSK	include/ssv6200_aux.h	13991;"	d
+RO_MODE_REG_OUT_16_SFT	include/ssv6200_aux.h	13993;"	d
+RO_MODE_REG_OUT_16_SZ	include/ssv6200_aux.h	13995;"	d
+RO_MODE_REG_OUT_64_HI	include/ssv6200_aux.h	15199;"	d
+RO_MODE_REG_OUT_64_I_MSK	include/ssv6200_aux.h	15197;"	d
+RO_MODE_REG_OUT_64_MSK	include/ssv6200_aux.h	15196;"	d
+RO_MODE_REG_OUT_64_SFT	include/ssv6200_aux.h	15198;"	d
+RO_MODE_REG_OUT_64_SZ	include/ssv6200_aux.h	15200;"	d
+RO_MODE_REG_OUT_80_HI	include/ssv6200_aux.h	15184;"	d
+RO_MODE_REG_OUT_80_I_MSK	include/ssv6200_aux.h	15182;"	d
+RO_MODE_REG_OUT_80_MSK	include/ssv6200_aux.h	15181;"	d
+RO_MODE_REG_OUT_80_SFT	include/ssv6200_aux.h	15183;"	d
+RO_MODE_REG_OUT_80_SZ	include/ssv6200_aux.h	15185;"	d
+RO_MODE_REG_SO_16_HI	include/ssv6200_aux.h	13999;"	d
+RO_MODE_REG_SO_16_I_MSK	include/ssv6200_aux.h	13997;"	d
+RO_MODE_REG_SO_16_MSK	include/ssv6200_aux.h	13996;"	d
+RO_MODE_REG_SO_16_SFT	include/ssv6200_aux.h	13998;"	d
+RO_MODE_REG_SO_16_SZ	include/ssv6200_aux.h	14000;"	d
+RO_MODE_REG_SO_64_HI	include/ssv6200_aux.h	15204;"	d
+RO_MODE_REG_SO_64_I_MSK	include/ssv6200_aux.h	15202;"	d
+RO_MODE_REG_SO_64_MSK	include/ssv6200_aux.h	15201;"	d
+RO_MODE_REG_SO_64_SFT	include/ssv6200_aux.h	15203;"	d
+RO_MODE_REG_SO_64_SZ	include/ssv6200_aux.h	15205;"	d
+RO_MODE_REG_SO_80_HI	include/ssv6200_aux.h	15189;"	d
+RO_MODE_REG_SO_80_I_MSK	include/ssv6200_aux.h	15187;"	d
+RO_MODE_REG_SO_80_MSK	include/ssv6200_aux.h	15186;"	d
+RO_MODE_REG_SO_80_SFT	include/ssv6200_aux.h	15188;"	d
+RO_MODE_REG_SO_80_SZ	include/ssv6200_aux.h	15190;"	d
+RO_MONITOR_BUS_16_HI	include/ssv6200_aux.h	14004;"	d
+RO_MONITOR_BUS_16_I_MSK	include/ssv6200_aux.h	14002;"	d
+RO_MONITOR_BUS_16_MSK	include/ssv6200_aux.h	14001;"	d
+RO_MONITOR_BUS_16_SFT	include/ssv6200_aux.h	14003;"	d
+RO_MONITOR_BUS_16_SZ	include/ssv6200_aux.h	14005;"	d
+RO_MONITOR_BUS_64_HI	include/ssv6200_aux.h	15209;"	d
+RO_MONITOR_BUS_64_I_MSK	include/ssv6200_aux.h	15207;"	d
+RO_MONITOR_BUS_64_MSK	include/ssv6200_aux.h	15206;"	d
+RO_MONITOR_BUS_64_SFT	include/ssv6200_aux.h	15208;"	d
+RO_MONITOR_BUS_64_SZ	include/ssv6200_aux.h	15210;"	d
+RO_MONITOR_BUS_80_HI	include/ssv6200_aux.h	15194;"	d
+RO_MONITOR_BUS_80_I_MSK	include/ssv6200_aux.h	15192;"	d
+RO_MONITOR_BUS_80_MSK	include/ssv6200_aux.h	15191;"	d
+RO_MONITOR_BUS_80_SFT	include/ssv6200_aux.h	15193;"	d
+RO_MONITOR_BUS_80_SZ	include/ssv6200_aux.h	15195;"	d
+RO_MRX_EN_CNT_HI	include/ssv6200_aux.h	13819;"	d
+RO_MRX_EN_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30824;"	d
+RO_MRX_EN_CNT_I_MSK	include/ssv6200_aux.h	13817;"	d
+RO_MRX_EN_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30822;"	d
+RO_MRX_EN_CNT_MSK	include/ssv6200_aux.h	13816;"	d
+RO_MRX_EN_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30821;"	d
+RO_MRX_EN_CNT_SFT	include/ssv6200_aux.h	13818;"	d
+RO_MRX_EN_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30823;"	d
+RO_MRX_EN_CNT_SZ	include/ssv6200_aux.h	13820;"	d
+RO_MRX_EN_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30825;"	d
+RO_MRX_LEN_CNT_0_HI	include/ssv6200_aux.h	13954;"	d
+RO_MRX_LEN_CNT_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30959;"	d
+RO_MRX_LEN_CNT_0_I_MSK	include/ssv6200_aux.h	13952;"	d
+RO_MRX_LEN_CNT_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30957;"	d
+RO_MRX_LEN_CNT_0_MSK	include/ssv6200_aux.h	13951;"	d
+RO_MRX_LEN_CNT_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30956;"	d
+RO_MRX_LEN_CNT_0_SFT	include/ssv6200_aux.h	13953;"	d
+RO_MRX_LEN_CNT_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30958;"	d
+RO_MRX_LEN_CNT_0_SZ	include/ssv6200_aux.h	13955;"	d
+RO_MRX_LEN_CNT_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30960;"	d
+RO_MRX_LEN_CNT_1_HI	include/ssv6200_aux.h	13949;"	d
+RO_MRX_LEN_CNT_1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30954;"	d
+RO_MRX_LEN_CNT_1_I_MSK	include/ssv6200_aux.h	13947;"	d
+RO_MRX_LEN_CNT_1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30952;"	d
+RO_MRX_LEN_CNT_1_MSK	include/ssv6200_aux.h	13946;"	d
+RO_MRX_LEN_CNT_1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30951;"	d
+RO_MRX_LEN_CNT_1_SFT	include/ssv6200_aux.h	13948;"	d
+RO_MRX_LEN_CNT_1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30953;"	d
+RO_MRX_LEN_CNT_1_SZ	include/ssv6200_aux.h	13950;"	d
+RO_MRX_LEN_CNT_1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30955;"	d
+RO_MRX_RX_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31439;"	d
+RO_MRX_RX_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31437;"	d
+RO_MRX_RX_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31436;"	d
+RO_MRX_RX_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31438;"	d
+RO_MRX_RX_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31440;"	d
+RO_MRX_TYPE_CNT_0_HI	include/ssv6200_aux.h	14044;"	d
+RO_MRX_TYPE_CNT_0_I_MSK	include/ssv6200_aux.h	14042;"	d
+RO_MRX_TYPE_CNT_0_MSK	include/ssv6200_aux.h	14041;"	d
+RO_MRX_TYPE_CNT_0_SFT	include/ssv6200_aux.h	14043;"	d
+RO_MRX_TYPE_CNT_0_SZ	include/ssv6200_aux.h	14045;"	d
+RO_MRX_TYPE_CNT_1_HI	include/ssv6200_aux.h	14039;"	d
+RO_MRX_TYPE_CNT_1_I_MSK	include/ssv6200_aux.h	14037;"	d
+RO_MRX_TYPE_CNT_1_MSK	include/ssv6200_aux.h	14036;"	d
+RO_MRX_TYPE_CNT_1_SFT	include/ssv6200_aux.h	14038;"	d
+RO_MRX_TYPE_CNT_1_SZ	include/ssv6200_aux.h	14040;"	d
+RO_MRX_TYPE_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30984;"	d
+RO_MRX_TYPE_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30982;"	d
+RO_MRX_TYPE_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30981;"	d
+RO_MRX_TYPE_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30983;"	d
+RO_MRX_TYPE_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30985;"	d
+RO_MTXDMA_CMD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6809;"	d
+RO_MTXDMA_CMD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6807;"	d
+RO_MTXDMA_CMD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6806;"	d
+RO_MTXDMA_CMD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6808;"	d
+RO_MTXDMA_CMD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6810;"	d
+RO_MTX_BASE1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7449;"	d
+RO_MTX_BASE1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7447;"	d
+RO_MTX_BASE1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7446;"	d
+RO_MTX_BASE1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7448;"	d
+RO_MTX_BASE1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7450;"	d
+RO_MTX_BASE2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7454;"	d
+RO_MTX_BASE2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7452;"	d
+RO_MTX_BASE2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7451;"	d
+RO_MTX_BASE2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7453;"	d
+RO_MTX_BASE2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7455;"	d
+RO_MTX_BASE3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7459;"	d
+RO_MTX_BASE3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7457;"	d
+RO_MTX_BASE3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7456;"	d
+RO_MTX_BASE3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7458;"	d
+RO_MTX_BASE3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7460;"	d
+RO_MTX_LEN_CNT_0_HI	include/ssv6200_aux.h	13944;"	d
+RO_MTX_LEN_CNT_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30949;"	d
+RO_MTX_LEN_CNT_0_I_MSK	include/ssv6200_aux.h	13942;"	d
+RO_MTX_LEN_CNT_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30947;"	d
+RO_MTX_LEN_CNT_0_MSK	include/ssv6200_aux.h	13941;"	d
+RO_MTX_LEN_CNT_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30946;"	d
+RO_MTX_LEN_CNT_0_SFT	include/ssv6200_aux.h	13943;"	d
+RO_MTX_LEN_CNT_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30948;"	d
+RO_MTX_LEN_CNT_0_SZ	include/ssv6200_aux.h	13945;"	d
+RO_MTX_LEN_CNT_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30950;"	d
+RO_MTX_LEN_CNT_1_HI	include/ssv6200_aux.h	13939;"	d
+RO_MTX_LEN_CNT_1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30944;"	d
+RO_MTX_LEN_CNT_1_I_MSK	include/ssv6200_aux.h	13937;"	d
+RO_MTX_LEN_CNT_1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30942;"	d
+RO_MTX_LEN_CNT_1_MSK	include/ssv6200_aux.h	13936;"	d
+RO_MTX_LEN_CNT_1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30941;"	d
+RO_MTX_LEN_CNT_1_SFT	include/ssv6200_aux.h	13938;"	d
+RO_MTX_LEN_CNT_1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30943;"	d
+RO_MTX_LEN_CNT_1_SZ	include/ssv6200_aux.h	13940;"	d
+RO_MTX_LEN_CNT_1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30945;"	d
+RO_MTX_TX_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7374;"	d
+RO_MTX_TX_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7372;"	d
+RO_MTX_TX_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7371;"	d
+RO_MTX_TX_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7373;"	d
+RO_MTX_TX_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7375;"	d
+RO_MTX_TYPE_CNT_0_HI	include/ssv6200_aux.h	14034;"	d
+RO_MTX_TYPE_CNT_0_I_MSK	include/ssv6200_aux.h	14032;"	d
+RO_MTX_TYPE_CNT_0_MSK	include/ssv6200_aux.h	14031;"	d
+RO_MTX_TYPE_CNT_0_SFT	include/ssv6200_aux.h	14033;"	d
+RO_MTX_TYPE_CNT_0_SZ	include/ssv6200_aux.h	14035;"	d
+RO_MTX_TYPE_CNT_1_HI	include/ssv6200_aux.h	14029;"	d
+RO_MTX_TYPE_CNT_1_I_MSK	include/ssv6200_aux.h	14027;"	d
+RO_MTX_TYPE_CNT_1_MSK	include/ssv6200_aux.h	14026;"	d
+RO_MTX_TYPE_CNT_1_SFT	include/ssv6200_aux.h	14028;"	d
+RO_MTX_TYPE_CNT_1_SZ	include/ssv6200_aux.h	14030;"	d
+RO_MTX_TYPE_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30989;"	d
+RO_MTX_TYPE_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30987;"	d
+RO_MTX_TYPE_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30986;"	d
+RO_MTX_TYPE_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30988;"	d
+RO_MTX_TYPE_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30990;"	d
+RO_PACKET_ERR_CNT_HI	include/ssv6200_aux.h	14719;"	d
+RO_PACKET_ERR_CNT_I_MSK	include/ssv6200_aux.h	14717;"	d
+RO_PACKET_ERR_CNT_MSK	include/ssv6200_aux.h	14716;"	d
+RO_PACKET_ERR_CNT_SFT	include/ssv6200_aux.h	14718;"	d
+RO_PACKET_ERR_CNT_SZ	include/ssv6200_aux.h	14720;"	d
+RO_PERIOD_ARRAY_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32879;"	d
+RO_PERIOD_ARRAY_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32877;"	d
+RO_PERIOD_ARRAY_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32876;"	d
+RO_PERIOD_ARRAY_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32878;"	d
+RO_PERIOD_ARRAY_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32880;"	d
+RO_PERIOD_ARRAY_1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32884;"	d
+RO_PERIOD_ARRAY_1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32882;"	d
+RO_PERIOD_ARRAY_1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32881;"	d
+RO_PERIOD_ARRAY_1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32883;"	d
+RO_PERIOD_ARRAY_1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32885;"	d
+RO_PERIOD_ARRAY_2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32889;"	d
+RO_PERIOD_ARRAY_2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32887;"	d
+RO_PERIOD_ARRAY_2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32886;"	d
+RO_PERIOD_ARRAY_2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32888;"	d
+RO_PERIOD_ARRAY_2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32890;"	d
+RO_PERIOD_ARRAY_3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32894;"	d
+RO_PERIOD_ARRAY_3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32892;"	d
+RO_PERIOD_ARRAY_3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32891;"	d
+RO_PERIOD_ARRAY_3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32893;"	d
+RO_PERIOD_ARRAY_3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32895;"	d
+RO_PERIOD_ARRAY_4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32899;"	d
+RO_PERIOD_ARRAY_4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32897;"	d
+RO_PERIOD_ARRAY_4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32896;"	d
+RO_PERIOD_ARRAY_4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32898;"	d
+RO_PERIOD_ARRAY_4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32900;"	d
+RO_PERIOD_ARRAY_5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32904;"	d
+RO_PERIOD_ARRAY_5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32902;"	d
+RO_PERIOD_ARRAY_5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32901;"	d
+RO_PERIOD_ARRAY_5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32903;"	d
+RO_PERIOD_ARRAY_5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32905;"	d
+RO_PGAGC_FF1_HI	include/ssv6200_aux.h	13519;"	d
+RO_PGAGC_FF1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30714;"	d
+RO_PGAGC_FF1_I_MSK	include/ssv6200_aux.h	13517;"	d
+RO_PGAGC_FF1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30712;"	d
+RO_PGAGC_FF1_MSK	include/ssv6200_aux.h	13516;"	d
+RO_PGAGC_FF1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30711;"	d
+RO_PGAGC_FF1_SFT	include/ssv6200_aux.h	13518;"	d
+RO_PGAGC_FF1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30713;"	d
+RO_PGAGC_FF1_SZ	include/ssv6200_aux.h	13520;"	d
+RO_PGAGC_FF1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30715;"	d
+RO_PGAGC_FF2_HI	include/ssv6200_aux.h	13539;"	d
+RO_PGAGC_FF2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30734;"	d
+RO_PGAGC_FF2_I_MSK	include/ssv6200_aux.h	13537;"	d
+RO_PGAGC_FF2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30732;"	d
+RO_PGAGC_FF2_MSK	include/ssv6200_aux.h	13536;"	d
+RO_PGAGC_FF2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30731;"	d
+RO_PGAGC_FF2_SFT	include/ssv6200_aux.h	13538;"	d
+RO_PGAGC_FF2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30733;"	d
+RO_PGAGC_FF2_SZ	include/ssv6200_aux.h	13540;"	d
+RO_PGAGC_FF2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30735;"	d
+RO_PGAGC_FF3_HI	include/ssv6200_aux.h	13559;"	d
+RO_PGAGC_FF3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30754;"	d
+RO_PGAGC_FF3_I_MSK	include/ssv6200_aux.h	13557;"	d
+RO_PGAGC_FF3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30752;"	d
+RO_PGAGC_FF3_MSK	include/ssv6200_aux.h	13556;"	d
+RO_PGAGC_FF3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30751;"	d
+RO_PGAGC_FF3_SFT	include/ssv6200_aux.h	13558;"	d
+RO_PGAGC_FF3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30753;"	d
+RO_PGAGC_FF3_SZ	include/ssv6200_aux.h	13560;"	d
+RO_PGAGC_FF3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30755;"	d
+RO_PGA_PWR_FF1_HI	include/ssv6200_aux.h	13509;"	d
+RO_PGA_PWR_FF1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30704;"	d
+RO_PGA_PWR_FF1_I_MSK	include/ssv6200_aux.h	13507;"	d
+RO_PGA_PWR_FF1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30702;"	d
+RO_PGA_PWR_FF1_MSK	include/ssv6200_aux.h	13506;"	d
+RO_PGA_PWR_FF1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30701;"	d
+RO_PGA_PWR_FF1_SFT	include/ssv6200_aux.h	13508;"	d
+RO_PGA_PWR_FF1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30703;"	d
+RO_PGA_PWR_FF1_SZ	include/ssv6200_aux.h	13510;"	d
+RO_PGA_PWR_FF1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30705;"	d
+RO_PGA_PWR_FF2_HI	include/ssv6200_aux.h	13529;"	d
+RO_PGA_PWR_FF2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30724;"	d
+RO_PGA_PWR_FF2_I_MSK	include/ssv6200_aux.h	13527;"	d
+RO_PGA_PWR_FF2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30722;"	d
+RO_PGA_PWR_FF2_MSK	include/ssv6200_aux.h	13526;"	d
+RO_PGA_PWR_FF2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30721;"	d
+RO_PGA_PWR_FF2_SFT	include/ssv6200_aux.h	13528;"	d
+RO_PGA_PWR_FF2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30723;"	d
+RO_PGA_PWR_FF2_SZ	include/ssv6200_aux.h	13530;"	d
+RO_PGA_PWR_FF2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30725;"	d
+RO_PGA_PWR_FF3_HI	include/ssv6200_aux.h	13549;"	d
+RO_PGA_PWR_FF3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30744;"	d
+RO_PGA_PWR_FF3_I_MSK	include/ssv6200_aux.h	13547;"	d
+RO_PGA_PWR_FF3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30742;"	d
+RO_PGA_PWR_FF3_MSK	include/ssv6200_aux.h	13546;"	d
+RO_PGA_PWR_FF3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30741;"	d
+RO_PGA_PWR_FF3_SFT	include/ssv6200_aux.h	13548;"	d
+RO_PGA_PWR_FF3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30743;"	d
+RO_PGA_PWR_FF3_SZ	include/ssv6200_aux.h	13550;"	d
+RO_PGA_PWR_FF3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30745;"	d
+RO_PHEST_RDY_HI	include/ssv6200_aux.h	15629;"	d
+RO_PHEST_RDY_I_MSK	include/ssv6200_aux.h	15627;"	d
+RO_PHEST_RDY_MSK	include/ssv6200_aux.h	15626;"	d
+RO_PHEST_RDY_SFT	include/ssv6200_aux.h	15628;"	d
+RO_PHEST_RDY_SZ	include/ssv6200_aux.h	15630;"	d
+RO_PHYTXIP_TIMEOUT_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7174;"	d
+RO_PHYTXIP_TIMEOUT_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7172;"	d
+RO_PHYTXIP_TIMEOUT_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7171;"	d
+RO_PHYTXIP_TIMEOUT_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7173;"	d
+RO_PHYTXIP_TIMEOUT_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7175;"	d
+RO_PMU_STATE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29849;"	d
+RO_PMU_STATE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29847;"	d
+RO_PMU_STATE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29846;"	d
+RO_PMU_STATE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29848;"	d
+RO_PMU_STATE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29850;"	d
+RO_PMU_WAKE_TRIG_EVENT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29809;"	d
+RO_PMU_WAKE_TRIG_EVENT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29807;"	d
+RO_PMU_WAKE_TRIG_EVENT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29806;"	d
+RO_PMU_WAKE_TRIG_EVENT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29808;"	d
+RO_PMU_WAKE_TRIG_EVENT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29810;"	d
+RO_PRE_DC_DONE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27534;"	d
+RO_PRE_DC_DONE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27532;"	d
+RO_PRE_DC_DONE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27531;"	d
+RO_PRE_DC_DONE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27533;"	d
+RO_PRE_DC_DONE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27535;"	d
+RO_PRIMARY_EDCCA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30849;"	d
+RO_PRIMARY_EDCCA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30847;"	d
+RO_PRIMARY_EDCCA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30846;"	d
+RO_PRIMARY_EDCCA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30848;"	d
+RO_PRIMARY_EDCCA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30850;"	d
+RO_PTC_SCHEDULE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6769;"	d
+RO_PTC_SCHEDULE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6767;"	d
+RO_PTC_SCHEDULE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6766;"	d
+RO_PTC_SCHEDULE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6768;"	d
+RO_PTC_SCHEDULE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6770;"	d
+RO_PW_ARRAY_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32849;"	d
+RO_PW_ARRAY_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32847;"	d
+RO_PW_ARRAY_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32846;"	d
+RO_PW_ARRAY_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32848;"	d
+RO_PW_ARRAY_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32850;"	d
+RO_PW_ARRAY_1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32854;"	d
+RO_PW_ARRAY_1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32852;"	d
+RO_PW_ARRAY_1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32851;"	d
+RO_PW_ARRAY_1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32853;"	d
+RO_PW_ARRAY_1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32855;"	d
+RO_PW_ARRAY_2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32859;"	d
+RO_PW_ARRAY_2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32857;"	d
+RO_PW_ARRAY_2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32856;"	d
+RO_PW_ARRAY_2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32858;"	d
+RO_PW_ARRAY_2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32860;"	d
+RO_PW_ARRAY_3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32864;"	d
+RO_PW_ARRAY_3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32862;"	d
+RO_PW_ARRAY_3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32861;"	d
+RO_PW_ARRAY_3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32863;"	d
+RO_PW_ARRAY_3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32865;"	d
+RO_PW_ARRAY_4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32869;"	d
+RO_PW_ARRAY_4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32867;"	d
+RO_PW_ARRAY_4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32866;"	d
+RO_PW_ARRAY_4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32868;"	d
+RO_PW_ARRAY_4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32870;"	d
+RO_PW_ARRAY_5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32874;"	d
+RO_PW_ARRAY_5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32872;"	d
+RO_PW_ARRAY_5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32871;"	d
+RO_PW_ARRAY_5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32873;"	d
+RO_PW_ARRAY_5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32875;"	d
+RO_PW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32844;"	d
+RO_PW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32842;"	d
+RO_PW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32841;"	d
+RO_PW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32843;"	d
+RO_PW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32845;"	d
+RO_Q_DC_OUT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30799;"	d
+RO_Q_DC_OUT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30797;"	d
+RO_Q_DC_OUT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30796;"	d
+RO_Q_DC_OUT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30798;"	d
+RO_Q_DC_OUT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30800;"	d
+RO_RADAR_DET_NUM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32829;"	d
+RO_RADAR_DET_NUM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32827;"	d
+RO_RADAR_DET_NUM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32826;"	d
+RO_RADAR_DET_NUM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32828;"	d
+RO_RADAR_DET_NUM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32830;"	d
+RO_RADAR_DET_OUT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32834;"	d
+RO_RADAR_DET_OUT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32832;"	d
+RO_RADAR_DET_OUT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32831;"	d
+RO_RADAR_DET_OUT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32833;"	d
+RO_RADAR_DET_OUT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32835;"	d
+RO_RADAR_VALID_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32839;"	d
+RO_RADAR_VALID_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32837;"	d
+RO_RADAR_VALID_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32836;"	d
+RO_RADAR_VALID_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32838;"	d
+RO_RADAR_VALID_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32840;"	d
+RO_RCCAL_DONE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27494;"	d
+RO_RCCAL_DONE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27492;"	d
+RO_RCCAL_DONE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27491;"	d
+RO_RCCAL_DONE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27493;"	d
+RO_RCCAL_DONE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27495;"	d
+RO_REFREG_KHZ_OUT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27789;"	d
+RO_REFREG_KHZ_OUT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27787;"	d
+RO_REFREG_KHZ_OUT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27786;"	d
+RO_REFREG_KHZ_OUT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27788;"	d
+RO_REFREG_KHZ_OUT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27790;"	d
+RO_RFGC_FF1_HI	include/ssv6200_aux.h	13524;"	d
+RO_RFGC_FF1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30719;"	d
+RO_RFGC_FF1_I_MSK	include/ssv6200_aux.h	13522;"	d
+RO_RFGC_FF1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30717;"	d
+RO_RFGC_FF1_MSK	include/ssv6200_aux.h	13521;"	d
+RO_RFGC_FF1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30716;"	d
+RO_RFGC_FF1_SFT	include/ssv6200_aux.h	13523;"	d
+RO_RFGC_FF1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30718;"	d
+RO_RFGC_FF1_SZ	include/ssv6200_aux.h	13525;"	d
+RO_RFGC_FF1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30720;"	d
+RO_RFGC_FF2_HI	include/ssv6200_aux.h	13544;"	d
+RO_RFGC_FF2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30739;"	d
+RO_RFGC_FF2_I_MSK	include/ssv6200_aux.h	13542;"	d
+RO_RFGC_FF2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30737;"	d
+RO_RFGC_FF2_MSK	include/ssv6200_aux.h	13541;"	d
+RO_RFGC_FF2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30736;"	d
+RO_RFGC_FF2_SFT	include/ssv6200_aux.h	13543;"	d
+RO_RFGC_FF2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30738;"	d
+RO_RFGC_FF2_SZ	include/ssv6200_aux.h	13545;"	d
+RO_RFGC_FF2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30740;"	d
+RO_RFGC_FF3_HI	include/ssv6200_aux.h	13564;"	d
+RO_RFGC_FF3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30759;"	d
+RO_RFGC_FF3_I_MSK	include/ssv6200_aux.h	13562;"	d
+RO_RFGC_FF3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30757;"	d
+RO_RFGC_FF3_MSK	include/ssv6200_aux.h	13561;"	d
+RO_RFGC_FF3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30756;"	d
+RO_RFGC_FF3_SFT	include/ssv6200_aux.h	13563;"	d
+RO_RFGC_FF3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30758;"	d
+RO_RFGC_FF3_SZ	include/ssv6200_aux.h	13565;"	d
+RO_RFGC_FF3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30760;"	d
+RO_RFPGA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27769;"	d
+RO_RFPGA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27767;"	d
+RO_RFPGA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27766;"	d
+RO_RFPGA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27768;"	d
+RO_RFPGA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27770;"	d
+RO_RF_CH_FREQ_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27794;"	d
+RO_RF_CH_FREQ_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27792;"	d
+RO_RF_CH_FREQ_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27791;"	d
+RO_RF_CH_FREQ_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27793;"	d
+RO_RF_CH_FREQ_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27795;"	d
+RO_RF_PHY_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27744;"	d
+RO_RF_PHY_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27742;"	d
+RO_RF_PHY_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27741;"	d
+RO_RF_PHY_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27743;"	d
+RO_RF_PHY_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27745;"	d
+RO_RF_PWR_FF1_HI	include/ssv6200_aux.h	13514;"	d
+RO_RF_PWR_FF1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30709;"	d
+RO_RF_PWR_FF1_I_MSK	include/ssv6200_aux.h	13512;"	d
+RO_RF_PWR_FF1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30707;"	d
+RO_RF_PWR_FF1_MSK	include/ssv6200_aux.h	13511;"	d
+RO_RF_PWR_FF1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30706;"	d
+RO_RF_PWR_FF1_SFT	include/ssv6200_aux.h	13513;"	d
+RO_RF_PWR_FF1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30708;"	d
+RO_RF_PWR_FF1_SZ	include/ssv6200_aux.h	13515;"	d
+RO_RF_PWR_FF1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30710;"	d
+RO_RF_PWR_FF2_HI	include/ssv6200_aux.h	13534;"	d
+RO_RF_PWR_FF2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30729;"	d
+RO_RF_PWR_FF2_I_MSK	include/ssv6200_aux.h	13532;"	d
+RO_RF_PWR_FF2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30727;"	d
+RO_RF_PWR_FF2_MSK	include/ssv6200_aux.h	13531;"	d
+RO_RF_PWR_FF2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30726;"	d
+RO_RF_PWR_FF2_SFT	include/ssv6200_aux.h	13533;"	d
+RO_RF_PWR_FF2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30728;"	d
+RO_RF_PWR_FF2_SZ	include/ssv6200_aux.h	13535;"	d
+RO_RF_PWR_FF2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30730;"	d
+RO_RF_PWR_FF3_HI	include/ssv6200_aux.h	13554;"	d
+RO_RF_PWR_FF3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30749;"	d
+RO_RF_PWR_FF3_I_MSK	include/ssv6200_aux.h	13552;"	d
+RO_RF_PWR_FF3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30747;"	d
+RO_RF_PWR_FF3_MSK	include/ssv6200_aux.h	13551;"	d
+RO_RF_PWR_FF3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30746;"	d
+RO_RF_PWR_FF3_SFT	include/ssv6200_aux.h	13553;"	d
+RO_RF_PWR_FF3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30748;"	d
+RO_RF_PWR_FF3_SZ	include/ssv6200_aux.h	13555;"	d
+RO_RF_PWR_FF3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30750;"	d
+RO_RTC_INT_ALARM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29819;"	d
+RO_RTC_INT_ALARM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29817;"	d
+RO_RTC_INT_ALARM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29816;"	d
+RO_RTC_INT_ALARM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29818;"	d
+RO_RTC_INT_ALARM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29820;"	d
+RO_RTC_INT_SEC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29814;"	d
+RO_RTC_INT_SEC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29812;"	d
+RO_RTC_INT_SEC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29811;"	d
+RO_RTC_INT_SEC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29813;"	d
+RO_RTC_INT_SEC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29815;"	d
+RO_RTC_OSC_CAL_RES_RDY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29754;"	d
+RO_RTC_OSC_CAL_RES_RDY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29752;"	d
+RO_RTC_OSC_CAL_RES_RDY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29751;"	d
+RO_RTC_OSC_CAL_RES_RDY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29753;"	d
+RO_RTC_OSC_CAL_RES_RDY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29755;"	d
+RO_RTC_OSC_RES_SW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29759;"	d
+RO_RTC_OSC_RES_SW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29757;"	d
+RO_RTC_OSC_RES_SW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29756;"	d
+RO_RTC_OSC_RES_SW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29758;"	d
+RO_RTC_OSC_RES_SW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29760;"	d
+RO_RTC_TICK_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29794;"	d
+RO_RTC_TICK_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29792;"	d
+RO_RTC_TICK_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29791;"	d
+RO_RTC_TICK_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29793;"	d
+RO_RTC_TICK_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29795;"	d
+RO_RXIQ_DONE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27509;"	d
+RO_RXIQ_DONE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27507;"	d
+RO_RXIQ_DONE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27506;"	d
+RO_RXIQ_DONE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27508;"	d
+RO_RXIQ_DONE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27510;"	d
+RO_RX_AMP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28959;"	d
+RO_RX_AMP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28957;"	d
+RO_RX_AMP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28956;"	d
+RO_RX_AMP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28958;"	d
+RO_RX_AMP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28960;"	d
+RO_RX_BEACON_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31369;"	d
+RO_RX_BEACON_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31367;"	d
+RO_RX_BEACON_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31366;"	d
+RO_RX_BEACON_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31368;"	d
+RO_RX_BEACON_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31370;"	d
+RO_RX_BEACON_LOSS_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31364;"	d
+RO_RX_BEACON_LOSS_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31362;"	d
+RO_RX_BEACON_LOSS_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31361;"	d
+RO_RX_BEACON_LOSS_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31363;"	d
+RO_RX_BEACON_LOSS_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31365;"	d
+RO_RX_FIFO_FULL_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31384;"	d
+RO_RX_FIFO_FULL_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31382;"	d
+RO_RX_FIFO_FULL_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31381;"	d
+RO_RX_FIFO_FULL_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31383;"	d
+RO_RX_FIFO_FULL_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31385;"	d
+RO_RX_IQ_ALPHA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27569;"	d
+RO_RX_IQ_ALPHA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27567;"	d
+RO_RX_IQ_ALPHA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27566;"	d
+RO_RX_IQ_ALPHA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27568;"	d
+RO_RX_IQ_ALPHA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27570;"	d
+RO_RX_IQ_THETA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27564;"	d
+RO_RX_IQ_THETA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27562;"	d
+RO_RX_IQ_THETA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27561;"	d
+RO_RX_IQ_THETA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27563;"	d
+RO_RX_IQ_THETA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27565;"	d
+RO_RX_PHI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	28954;"	d
+RO_RX_PHI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28952;"	d
+RO_RX_PHI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	28951;"	d
+RO_RX_PHI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	28953;"	d
+RO_RX_PHI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	28955;"	d
+RO_RX_PKT_TIMER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31354;"	d
+RO_RX_PKT_TIMER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31352;"	d
+RO_RX_PKT_TIMER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31351;"	d
+RO_RX_PKT_TIMER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31353;"	d
+RO_RX_PKT_TIMER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31355;"	d
+RO_SECONDARY_EDCCA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30859;"	d
+RO_SECONDARY_EDCCA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30857;"	d
+RO_SECONDARY_EDCCA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30856;"	d
+RO_SECONDARY_EDCCA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30858;"	d
+RO_SECONDARY_EDCCA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30860;"	d
+RO_SPECTRUM_DATA_HI	include/ssv6200_aux.h	15214;"	d
+RO_SPECTRUM_DATA_I_MSK	include/ssv6200_aux.h	15212;"	d
+RO_SPECTRUM_DATA_MSK	include/ssv6200_aux.h	15211;"	d
+RO_SPECTRUM_DATA_SFT	include/ssv6200_aux.h	15213;"	d
+RO_SPECTRUM_DATA_SZ	include/ssv6200_aux.h	15215;"	d
+RO_SPECTRUM_IQ_PWR_31_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27624;"	d
+RO_SPECTRUM_IQ_PWR_31_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27622;"	d
+RO_SPECTRUM_IQ_PWR_31_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27621;"	d
+RO_SPECTRUM_IQ_PWR_31_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27623;"	d
+RO_SPECTRUM_IQ_PWR_31_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27625;"	d
+RO_SPECTRUM_IQ_PWR_39_32_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27609;"	d
+RO_SPECTRUM_IQ_PWR_39_32_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27607;"	d
+RO_SPECTRUM_IQ_PWR_39_32_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27606;"	d
+RO_SPECTRUM_IQ_PWR_39_32_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27608;"	d
+RO_SPECTRUM_IQ_PWR_39_32_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27610;"	d
+RO_STBC_PACKET_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32609;"	d
+RO_STBC_PACKET_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32607;"	d
+RO_STBC_PACKET_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32606;"	d
+RO_STBC_PACKET_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32608;"	d
+RO_STBC_PACKET_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32610;"	d
+RO_STBC_PACKET_ERR_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	32614;"	d
+RO_STBC_PACKET_ERR_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32612;"	d
+RO_STBC_PACKET_ERR_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	32611;"	d
+RO_STBC_PACKET_ERR_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	32613;"	d
+RO_STBC_PACKET_ERR_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	32615;"	d
+RO_TBUS_O_HI	include/ssv6200_aux.h	14074;"	d
+RO_TBUS_O_I_MSK	include/ssv6200_aux.h	14072;"	d
+RO_TBUS_O_MSK	include/ssv6200_aux.h	14071;"	d
+RO_TBUS_O_SFT	include/ssv6200_aux.h	14073;"	d
+RO_TBUS_O_SZ	include/ssv6200_aux.h	14075;"	d
+RO_TURISMO_TRX_5G_DCCAL_DONE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20464;"	d
+RO_TURISMO_TRX_5G_DCCAL_DONE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20462;"	d
+RO_TURISMO_TRX_5G_DCCAL_DONE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20461;"	d
+RO_TURISMO_TRX_5G_DCCAL_DONE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20463;"	d
+RO_TURISMO_TRX_5G_DCCAL_DONE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20465;"	d
+RO_TURISMO_TRX_5G_RXIQ_DONE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20459;"	d
+RO_TURISMO_TRX_5G_RXIQ_DONE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20457;"	d
+RO_TURISMO_TRX_5G_RXIQ_DONE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20456;"	d
+RO_TURISMO_TRX_5G_RXIQ_DONE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20458;"	d
+RO_TURISMO_TRX_5G_RXIQ_DONE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20460;"	d
+RO_TURISMO_TRX_5G_TXDC_DONE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20449;"	d
+RO_TURISMO_TRX_5G_TXDC_DONE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20447;"	d
+RO_TURISMO_TRX_5G_TXDC_DONE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20446;"	d
+RO_TURISMO_TRX_5G_TXDC_DONE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20448;"	d
+RO_TURISMO_TRX_5G_TXDC_DONE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20450;"	d
+RO_TURISMO_TRX_5G_TXIQ_DONE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20454;"	d
+RO_TURISMO_TRX_5G_TXIQ_DONE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20452;"	d
+RO_TURISMO_TRX_5G_TXIQ_DONE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20451;"	d
+RO_TURISMO_TRX_5G_TXIQ_DONE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20453;"	d
+RO_TURISMO_TRX_5G_TXIQ_DONE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20455;"	d
+RO_TURISMO_TRX_AD_VBAT_OK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21029;"	d
+RO_TURISMO_TRX_AD_VBAT_OK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21027;"	d
+RO_TURISMO_TRX_AD_VBAT_OK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21026;"	d
+RO_TURISMO_TRX_AD_VBAT_OK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21028;"	d
+RO_TURISMO_TRX_AD_VBAT_OK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21030;"	d
+RO_TURISMO_TRX_BT_DCCAL_DONE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20424;"	d
+RO_TURISMO_TRX_BT_DCCAL_DONE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20422;"	d
+RO_TURISMO_TRX_BT_DCCAL_DONE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20421;"	d
+RO_TURISMO_TRX_BT_DCCAL_DONE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20423;"	d
+RO_TURISMO_TRX_BT_DCCAL_DONE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20425;"	d
+RO_TURISMO_TRX_DC_CAL_I_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20664;"	d
+RO_TURISMO_TRX_DC_CAL_I_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20662;"	d
+RO_TURISMO_TRX_DC_CAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20661;"	d
+RO_TURISMO_TRX_DC_CAL_I_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20663;"	d
+RO_TURISMO_TRX_DC_CAL_I_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20665;"	d
+RO_TURISMO_TRX_DC_CAL_Q_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20659;"	d
+RO_TURISMO_TRX_DC_CAL_Q_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20657;"	d
+RO_TURISMO_TRX_DC_CAL_Q_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20656;"	d
+RO_TURISMO_TRX_DC_CAL_Q_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20658;"	d
+RO_TURISMO_TRX_DC_CAL_Q_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20660;"	d
+RO_TURISMO_TRX_FDB_CDELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20909;"	d
+RO_TURISMO_TRX_FDB_CDELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20907;"	d
+RO_TURISMO_TRX_FDB_CDELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20906;"	d
+RO_TURISMO_TRX_FDB_CDELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20908;"	d
+RO_TURISMO_TRX_FDB_CDELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20910;"	d
+RO_TURISMO_TRX_FDB_FDELAY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20914;"	d
+RO_TURISMO_TRX_FDB_FDELAY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20912;"	d
+RO_TURISMO_TRX_FDB_FDELAY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20911;"	d
+RO_TURISMO_TRX_FDB_FDELAY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20913;"	d
+RO_TURISMO_TRX_FDB_FDELAY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20915;"	d
+RO_TURISMO_TRX_FDB_PHASESWAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20919;"	d
+RO_TURISMO_TRX_FDB_PHASESWAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20917;"	d
+RO_TURISMO_TRX_FDB_PHASESWAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20916;"	d
+RO_TURISMO_TRX_FDB_PHASESWAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20918;"	d
+RO_TURISMO_TRX_FDB_PHASESWAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20920;"	d
+RO_TURISMO_TRX_PMU_STATE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	21024;"	d
+RO_TURISMO_TRX_PMU_STATE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21022;"	d
+RO_TURISMO_TRX_PMU_STATE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	21021;"	d
+RO_TURISMO_TRX_PMU_STATE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	21023;"	d
+RO_TURISMO_TRX_PMU_STATE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	21025;"	d
+RO_TURISMO_TRX_PMU_WAKE_TRIG_EVENT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20984;"	d
+RO_TURISMO_TRX_PMU_WAKE_TRIG_EVENT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20982;"	d
+RO_TURISMO_TRX_PMU_WAKE_TRIG_EVENT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20981;"	d
+RO_TURISMO_TRX_PMU_WAKE_TRIG_EVENT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20983;"	d
+RO_TURISMO_TRX_PMU_WAKE_TRIG_EVENT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20985;"	d
+RO_TURISMO_TRX_PRE_DC_DONE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20469;"	d
+RO_TURISMO_TRX_PRE_DC_DONE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20467;"	d
+RO_TURISMO_TRX_PRE_DC_DONE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20466;"	d
+RO_TURISMO_TRX_PRE_DC_DONE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20468;"	d
+RO_TURISMO_TRX_PRE_DC_DONE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20470;"	d
+RO_TURISMO_TRX_RCCAL_DONE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20429;"	d
+RO_TURISMO_TRX_RCCAL_DONE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20427;"	d
+RO_TURISMO_TRX_RCCAL_DONE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20426;"	d
+RO_TURISMO_TRX_RCCAL_DONE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20428;"	d
+RO_TURISMO_TRX_RCCAL_DONE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20430;"	d
+RO_TURISMO_TRX_RTC_INT_ALARM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20994;"	d
+RO_TURISMO_TRX_RTC_INT_ALARM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20992;"	d
+RO_TURISMO_TRX_RTC_INT_ALARM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20991;"	d
+RO_TURISMO_TRX_RTC_INT_ALARM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20993;"	d
+RO_TURISMO_TRX_RTC_INT_ALARM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20995;"	d
+RO_TURISMO_TRX_RTC_INT_SEC_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20989;"	d
+RO_TURISMO_TRX_RTC_INT_SEC_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20987;"	d
+RO_TURISMO_TRX_RTC_INT_SEC_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20986;"	d
+RO_TURISMO_TRX_RTC_INT_SEC_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20988;"	d
+RO_TURISMO_TRX_RTC_INT_SEC_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20990;"	d
+RO_TURISMO_TRX_RTC_OSC_CAL_RES_RDY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20929;"	d
+RO_TURISMO_TRX_RTC_OSC_CAL_RES_RDY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20927;"	d
+RO_TURISMO_TRX_RTC_OSC_CAL_RES_RDY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20926;"	d
+RO_TURISMO_TRX_RTC_OSC_CAL_RES_RDY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20928;"	d
+RO_TURISMO_TRX_RTC_OSC_CAL_RES_RDY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20930;"	d
+RO_TURISMO_TRX_RTC_OSC_RES_SW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20934;"	d
+RO_TURISMO_TRX_RTC_OSC_RES_SW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20932;"	d
+RO_TURISMO_TRX_RTC_OSC_RES_SW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20931;"	d
+RO_TURISMO_TRX_RTC_OSC_RES_SW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20933;"	d
+RO_TURISMO_TRX_RTC_OSC_RES_SW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20935;"	d
+RO_TURISMO_TRX_RTC_TICK_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20969;"	d
+RO_TURISMO_TRX_RTC_TICK_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20967;"	d
+RO_TURISMO_TRX_RTC_TICK_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20966;"	d
+RO_TURISMO_TRX_RTC_TICK_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20968;"	d
+RO_TURISMO_TRX_RTC_TICK_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20970;"	d
+RO_TURISMO_TRX_RXIQ_DONE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20444;"	d
+RO_TURISMO_TRX_RXIQ_DONE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20442;"	d
+RO_TURISMO_TRX_RXIQ_DONE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20441;"	d
+RO_TURISMO_TRX_RXIQ_DONE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20443;"	d
+RO_TURISMO_TRX_RXIQ_DONE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20445;"	d
+RO_TURISMO_TRX_RX_IQ_ALPHA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20509;"	d
+RO_TURISMO_TRX_RX_IQ_ALPHA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20507;"	d
+RO_TURISMO_TRX_RX_IQ_ALPHA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20506;"	d
+RO_TURISMO_TRX_RX_IQ_ALPHA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20508;"	d
+RO_TURISMO_TRX_RX_IQ_ALPHA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20510;"	d
+RO_TURISMO_TRX_RX_IQ_THETA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20504;"	d
+RO_TURISMO_TRX_RX_IQ_THETA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20502;"	d
+RO_TURISMO_TRX_RX_IQ_THETA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20501;"	d
+RO_TURISMO_TRX_RX_IQ_THETA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20503;"	d
+RO_TURISMO_TRX_RX_IQ_THETA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20505;"	d
+RO_TURISMO_TRX_SPECTRUM_IQ_PWR_31_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20564;"	d
+RO_TURISMO_TRX_SPECTRUM_IQ_PWR_31_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20562;"	d
+RO_TURISMO_TRX_SPECTRUM_IQ_PWR_31_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20561;"	d
+RO_TURISMO_TRX_SPECTRUM_IQ_PWR_31_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20563;"	d
+RO_TURISMO_TRX_SPECTRUM_IQ_PWR_31_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20565;"	d
+RO_TURISMO_TRX_SPECTRUM_IQ_PWR_39_32_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20549;"	d
+RO_TURISMO_TRX_SPECTRUM_IQ_PWR_39_32_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20547;"	d
+RO_TURISMO_TRX_SPECTRUM_IQ_PWR_39_32_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20546;"	d
+RO_TURISMO_TRX_SPECTRUM_IQ_PWR_39_32_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20548;"	d
+RO_TURISMO_TRX_SPECTRUM_IQ_PWR_39_32_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20550;"	d
+RO_TURISMO_TRX_TXDC_DONE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20434;"	d
+RO_TURISMO_TRX_TXDC_DONE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20432;"	d
+RO_TURISMO_TRX_TXDC_DONE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20431;"	d
+RO_TURISMO_TRX_TXDC_DONE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20433;"	d
+RO_TURISMO_TRX_TXDC_DONE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20435;"	d
+RO_TURISMO_TRX_TXIQ_DONE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20439;"	d
+RO_TURISMO_TRX_TXIQ_DONE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20437;"	d
+RO_TURISMO_TRX_TXIQ_DONE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20436;"	d
+RO_TURISMO_TRX_TXIQ_DONE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20438;"	d
+RO_TURISMO_TRX_TXIQ_DONE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20440;"	d
+RO_TURISMO_TRX_TX_IQ_ALPHA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20519;"	d
+RO_TURISMO_TRX_TX_IQ_ALPHA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20517;"	d
+RO_TURISMO_TRX_TX_IQ_ALPHA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20516;"	d
+RO_TURISMO_TRX_TX_IQ_ALPHA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20518;"	d
+RO_TURISMO_TRX_TX_IQ_ALPHA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20520;"	d
+RO_TURISMO_TRX_TX_IQ_THETA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20514;"	d
+RO_TURISMO_TRX_TX_IQ_THETA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20512;"	d
+RO_TURISMO_TRX_TX_IQ_THETA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20511;"	d
+RO_TURISMO_TRX_TX_IQ_THETA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20513;"	d
+RO_TURISMO_TRX_TX_IQ_THETA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20515;"	d
+RO_TURISMO_TRX_WF_DCCAL_DONE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20419;"	d
+RO_TURISMO_TRX_WF_DCCAL_DONE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20417;"	d
+RO_TURISMO_TRX_WF_DCCAL_DONE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20416;"	d
+RO_TURISMO_TRX_WF_DCCAL_DONE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20418;"	d
+RO_TURISMO_TRX_WF_DCCAL_DONE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20420;"	d
+RO_TURISMO_TRX_XO_RDY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	20924;"	d
+RO_TURISMO_TRX_XO_RDY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20922;"	d
+RO_TURISMO_TRX_XO_RDY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	20921;"	d
+RO_TURISMO_TRX_XO_RDY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	20923;"	d
+RO_TURISMO_TRX_XO_RDY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	20925;"	d
+RO_TXDC_DONE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27499;"	d
+RO_TXDC_DONE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27497;"	d
+RO_TXDC_DONE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27496;"	d
+RO_TXDC_DONE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27498;"	d
+RO_TXDC_DONE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27500;"	d
+RO_TXIQ_DONE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27504;"	d
+RO_TXIQ_DONE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27502;"	d
+RO_TXIQ_DONE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27501;"	d
+RO_TXIQ_DONE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27503;"	d
+RO_TXIQ_DONE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27505;"	d
+RO_TXOP_INTERVAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6814;"	d
+RO_TXOP_INTERVAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6812;"	d
+RO_TXOP_INTERVAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6811;"	d
+RO_TXOP_INTERVAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6813;"	d
+RO_TXOP_INTERVAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6815;"	d
+RO_TX_CNT_HI	include/ssv6200_aux.h	14319;"	d
+RO_TX_CNT_I_MSK	include/ssv6200_aux.h	14317;"	d
+RO_TX_CNT_MSK	include/ssv6200_aux.h	14316;"	d
+RO_TX_CNT_R_11B_TX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31494;"	d
+RO_TX_CNT_R_11B_TX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31492;"	d
+RO_TX_CNT_R_11B_TX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31491;"	d
+RO_TX_CNT_R_11B_TX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31493;"	d
+RO_TX_CNT_R_11B_TX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31495;"	d
+RO_TX_CNT_R_11GN_TX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31974;"	d
+RO_TX_CNT_R_11GN_TX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31972;"	d
+RO_TX_CNT_R_11GN_TX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31971;"	d
+RO_TX_CNT_R_11GN_TX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31973;"	d
+RO_TX_CNT_R_11GN_TX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31975;"	d
+RO_TX_CNT_R_HI	include/ssv6200_aux.h	14714;"	d
+RO_TX_CNT_R_I_MSK	include/ssv6200_aux.h	14712;"	d
+RO_TX_CNT_R_MSK	include/ssv6200_aux.h	14711;"	d
+RO_TX_CNT_R_SFT	include/ssv6200_aux.h	14713;"	d
+RO_TX_CNT_R_SZ	include/ssv6200_aux.h	14715;"	d
+RO_TX_CNT_SFT	include/ssv6200_aux.h	14318;"	d
+RO_TX_CNT_SZ	include/ssv6200_aux.h	14320;"	d
+RO_TX_DES_EXCP_CH_BW_CNT_HI	include/ssv6200_aux.h	13719;"	d
+RO_TX_DES_EXCP_CH_BW_CNT_I_MSK	include/ssv6200_aux.h	13717;"	d
+RO_TX_DES_EXCP_CH_BW_CNT_MSK	include/ssv6200_aux.h	13716;"	d
+RO_TX_DES_EXCP_CH_BW_CNT_SFT	include/ssv6200_aux.h	13718;"	d
+RO_TX_DES_EXCP_CH_BW_CNT_SZ	include/ssv6200_aux.h	13720;"	d
+RO_TX_DES_EXCP_MODE_CNT_HI	include/ssv6200_aux.h	13724;"	d
+RO_TX_DES_EXCP_MODE_CNT_I_MSK	include/ssv6200_aux.h	13722;"	d
+RO_TX_DES_EXCP_MODE_CNT_MSK	include/ssv6200_aux.h	13721;"	d
+RO_TX_DES_EXCP_MODE_CNT_SFT	include/ssv6200_aux.h	13723;"	d
+RO_TX_DES_EXCP_MODE_CNT_SZ	include/ssv6200_aux.h	13725;"	d
+RO_TX_DES_EXCP_RATE_CNT_HI	include/ssv6200_aux.h	13714;"	d
+RO_TX_DES_EXCP_RATE_CNT_I_MSK	include/ssv6200_aux.h	13712;"	d
+RO_TX_DES_EXCP_RATE_CNT_MSK	include/ssv6200_aux.h	13711;"	d
+RO_TX_DES_EXCP_RATE_CNT_SFT	include/ssv6200_aux.h	13713;"	d
+RO_TX_DES_EXCP_RATE_CNT_SZ	include/ssv6200_aux.h	13715;"	d
+RO_TX_EN_CNT_HI	include/ssv6200_aux.h	14314;"	d
+RO_TX_EN_CNT_I_MSK	include/ssv6200_aux.h	14312;"	d
+RO_TX_EN_CNT_MSK	include/ssv6200_aux.h	14311;"	d
+RO_TX_EN_CNT_SFT	include/ssv6200_aux.h	14313;"	d
+RO_TX_EN_CNT_SZ	include/ssv6200_aux.h	14315;"	d
+RO_TX_FIFO_EMPTY_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31389;"	d
+RO_TX_FIFO_EMPTY_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31387;"	d
+RO_TX_FIFO_EMPTY_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31386;"	d
+RO_TX_FIFO_EMPTY_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31388;"	d
+RO_TX_FIFO_EMPTY_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31390;"	d
+RO_TX_IP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	31459;"	d
+RO_TX_IP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31457;"	d
+RO_TX_IP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	31456;"	d
+RO_TX_IP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	31458;"	d
+RO_TX_IP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	31460;"	d
+RO_TX_IQ_ALPHA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27579;"	d
+RO_TX_IQ_ALPHA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27577;"	d
+RO_TX_IQ_ALPHA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27576;"	d
+RO_TX_IQ_ALPHA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27578;"	d
+RO_TX_IQ_ALPHA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27580;"	d
+RO_TX_IQ_THETA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27574;"	d
+RO_TX_IQ_THETA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27572;"	d
+RO_TX_IQ_THETA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27571;"	d
+RO_TX_IQ_THETA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27573;"	d
+RO_TX_IQ_THETA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27575;"	d
+RO_WAIT_RESPONSE_PHASE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6789;"	d
+RO_WAIT_RESPONSE_PHASE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6787;"	d
+RO_WAIT_RESPONSE_PHASE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6786;"	d
+RO_WAIT_RESPONSE_PHASE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6788;"	d
+RO_WAIT_RESPONSE_PHASE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6790;"	d
+RO_WF_DCCAL_DONE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	27484;"	d
+RO_WF_DCCAL_DONE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27482;"	d
+RO_WF_DCCAL_DONE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	27481;"	d
+RO_WF_DCCAL_DONE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	27483;"	d
+RO_WF_DCCAL_DONE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	27485;"	d
+RO_XO_RDY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	29749;"	d
+RO_XO_RDY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29747;"	d
+RO_XO_RDY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	29746;"	d
+RO_XO_RDY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	29748;"	d
+RO_XO_RDY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	29750;"	d
+RSSI_DECIMAL_POINT_SHIFT	smac/dev.h	197;"	d
+RSSI_SMOOTHING_SHIFT	smac/dev.h	196;"	d
+RSVD	include/ssv6200_common.h	/^u32 RSVD:16;$/;"	m	struct:ssv6200_rxphy_info_padding	access:public
+RSVD	include/ssv6xxx_common.h	/^    u32 RSVD:10;$/;"	m	struct:fw_rc_retry_params	access:public
+RSVD0	include/ssv6xxx_common.h	/^    u32 RSVD0 :5;$/;"	m	struct:cfg_host_event	access:public
+RSVD0	include/ssv6xxx_common.h	/^    u32 RSVD0:15;$/;"	m	struct:hci_rx_aggr_info	access:public
+RSVD0	include/ssv6xxx_common.h	/^    u32 RSVD0:5;$/;"	m	struct:cfg_host_cmd	access:public
+RSVD0	smac/hal/ssv6006c/ssv6006_mac.h	/^    u32 RSVD0:8;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+RSVD1	include/ssv6xxx_common.h	/^    u32 RSVD1:4;$/;"	m	struct:hci_rx_aggr_info	access:public
+RSVD1	smac/hal/ssv6006c/ssv6006_mac.h	/^    u16 RSVD1;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+RSVD10	smac/hal/ssv6006c/ssv6006_mac.h	/^    u32 RSVD10;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+RSVD11	smac/hal/ssv6006c/ssv6006_mac.h	/^    u32 RSVD11;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+RSVD2	smac/hal/ssv6006c/ssv6006_mac.h	/^    u16 RSVD2;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+RSVD3	smac/hal/ssv6006c/ssv6006_mac.h	/^    u32 RSVD3;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+RSVD4	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 RSVD4;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+RSVD5	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 RSVD5;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+RSVD6	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 RSVD6;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+RSVD7	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 RSVD7;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+RSVD8	smac/hal/ssv6006c/ssv6006_mac.h	/^    u16 RSVD8;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+RSVD9	smac/hal/ssv6006c/ssv6006_mac.h	/^    u32 RSVD9;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+RSVD_0	include/ssv6200_common.h	/^    u32 RSVD_0:2;$/;"	m	struct:ssv6200_rx_desc	access:public
+RSVD_0	include/ssv6200_common.h	/^    u32 RSVD_0:3;$/;"	m	struct:ssv6200_tx_desc	access:public
+RSVD_1	include/ssv6200_common.h	/^    u32 RSVD_1:1;$/;"	m	struct:ssv6200_rx_desc	access:public
+RSVD_1	include/ssv6200_common.h	/^    u32 RSVD_1:3;$/;"	m	struct:ssv6200_tx_desc	access:public
+RSVD_2	include/ssv6200_common.h	/^    u32 RSVD_2:1;$/;"	m	struct:ssv6200_tx_desc	access:public
+RSVD_3	include/ssv6200_common.h	/^    u32 RSVD_3:14;$/;"	m	struct:ssv6200_tx_desc	access:public
+RSVD_3	include/ssv6200_common.h	/^    u32 RSVD_3:3;$/;"	m	struct:ssv6200_rx_desc	access:public
+RSVD_4	include/ssv6200_common.h	/^    u32 RSVD_4:7;$/;"	m	struct:ssv6200_tx_desc	access:public
+RTC_CAL_ENA_HI	include/ssv6200_aux.h	5904;"	d
+RTC_CAL_ENA_I_MSK	include/ssv6200_aux.h	5902;"	d
+RTC_CAL_ENA_MSK	include/ssv6200_aux.h	5901;"	d
+RTC_CAL_ENA_SFT	include/ssv6200_aux.h	5903;"	d
+RTC_CAL_ENA_SZ	include/ssv6200_aux.h	5905;"	d
+RTC_CAL_RDY_HI	include/ssv6200_aux.h	17584;"	d
+RTC_CAL_RDY_I_MSK	include/ssv6200_aux.h	17582;"	d
+RTC_CAL_RDY_MSK	include/ssv6200_aux.h	17581;"	d
+RTC_CAL_RDY_SFT	include/ssv6200_aux.h	17583;"	d
+RTC_CAL_RDY_SZ	include/ssv6200_aux.h	17585;"	d
+RTC_EN_HI	include/ssv6200_aux.h	5929;"	d
+RTC_EN_I_MSK	include/ssv6200_aux.h	5927;"	d
+RTC_EN_MSK	include/ssv6200_aux.h	5926;"	d
+RTC_EN_SFT	include/ssv6200_aux.h	5928;"	d
+RTC_EN_SZ	include/ssv6200_aux.h	5930;"	d
+RTC_INT_ALARM_HI	include/ssv6200_aux.h	5959;"	d
+RTC_INT_ALARM_I_MSK	include/ssv6200_aux.h	5957;"	d
+RTC_INT_ALARM_MASK_HI	include/ssv6200_aux.h	5949;"	d
+RTC_INT_ALARM_MASK_I_MSK	include/ssv6200_aux.h	5947;"	d
+RTC_INT_ALARM_MASK_MSK	include/ssv6200_aux.h	5946;"	d
+RTC_INT_ALARM_MASK_SFT	include/ssv6200_aux.h	5948;"	d
+RTC_INT_ALARM_MASK_SZ	include/ssv6200_aux.h	5950;"	d
+RTC_INT_ALARM_MSK	include/ssv6200_aux.h	5956;"	d
+RTC_INT_ALARM_SFT	include/ssv6200_aux.h	5958;"	d
+RTC_INT_ALARM_SZ	include/ssv6200_aux.h	5960;"	d
+RTC_INT_SEC_HI	include/ssv6200_aux.h	5954;"	d
+RTC_INT_SEC_I_MSK	include/ssv6200_aux.h	5952;"	d
+RTC_INT_SEC_MASK_HI	include/ssv6200_aux.h	5944;"	d
+RTC_INT_SEC_MASK_I_MSK	include/ssv6200_aux.h	5942;"	d
+RTC_INT_SEC_MASK_MSK	include/ssv6200_aux.h	5941;"	d
+RTC_INT_SEC_MASK_SFT	include/ssv6200_aux.h	5943;"	d
+RTC_INT_SEC_MASK_SZ	include/ssv6200_aux.h	5945;"	d
+RTC_INT_SEC_MSK	include/ssv6200_aux.h	5951;"	d
+RTC_INT_SEC_SFT	include/ssv6200_aux.h	5953;"	d
+RTC_INT_SEC_SZ	include/ssv6200_aux.h	5955;"	d
+RTC_MISC_REG_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	107;"	d
+RTC_MISC_REG_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	46;"	d
+RTC_OSC_CAL_RES_RDY_HI	include/ssv6200_aux.h	5874;"	d
+RTC_OSC_CAL_RES_RDY_I_MSK	include/ssv6200_aux.h	5872;"	d
+RTC_OSC_CAL_RES_RDY_MSK	include/ssv6200_aux.h	5871;"	d
+RTC_OSC_CAL_RES_RDY_SFT	include/ssv6200_aux.h	5873;"	d
+RTC_OSC_CAL_RES_RDY_SZ	include/ssv6200_aux.h	5875;"	d
+RTC_RAM_BANK_SIZE	include/ssv6200_reg.h	89;"	d
+RTC_RAM_BASE	include/ssv6200_reg.h	40;"	d
+RTC_SEC_ALARM_VALUE_HI	include/ssv6200_aux.h	5974;"	d
+RTC_SEC_ALARM_VALUE_I_MSK	include/ssv6200_aux.h	5972;"	d
+RTC_SEC_ALARM_VALUE_MSK	include/ssv6200_aux.h	5971;"	d
+RTC_SEC_ALARM_VALUE_SFT	include/ssv6200_aux.h	5973;"	d
+RTC_SEC_ALARM_VALUE_SZ	include/ssv6200_aux.h	5975;"	d
+RTC_SEC_CNT_HI	include/ssv6200_aux.h	5969;"	d
+RTC_SEC_CNT_I_MSK	include/ssv6200_aux.h	5967;"	d
+RTC_SEC_CNT_MSK	include/ssv6200_aux.h	5966;"	d
+RTC_SEC_CNT_SFT	include/ssv6200_aux.h	5968;"	d
+RTC_SEC_CNT_SZ	include/ssv6200_aux.h	5970;"	d
+RTC_SEC_START_CNT_HI	include/ssv6200_aux.h	5964;"	d
+RTC_SEC_START_CNT_I_MSK	include/ssv6200_aux.h	5962;"	d
+RTC_SEC_START_CNT_MSK	include/ssv6200_aux.h	5961;"	d
+RTC_SEC_START_CNT_SFT	include/ssv6200_aux.h	5963;"	d
+RTC_SEC_START_CNT_SZ	include/ssv6200_aux.h	5965;"	d
+RTC_SRC_HI	include/ssv6200_aux.h	5934;"	d
+RTC_SRC_I_MSK	include/ssv6200_aux.h	5932;"	d
+RTC_SRC_MSK	include/ssv6200_aux.h	5931;"	d
+RTC_SRC_SFT	include/ssv6200_aux.h	5933;"	d
+RTC_SRC_SZ	include/ssv6200_aux.h	5935;"	d
+RTC_TICK_CNT_HI	include/ssv6200_aux.h	5939;"	d
+RTC_TICK_CNT_I_MSK	include/ssv6200_aux.h	5937;"	d
+RTC_TICK_CNT_MSK	include/ssv6200_aux.h	5936;"	d
+RTC_TICK_CNT_SFT	include/ssv6200_aux.h	5938;"	d
+RTC_TICK_CNT_SZ	include/ssv6200_aux.h	5940;"	d
+RTC_TIMER_WAKE_PMU_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1779;"	d
+RTC_TIMER_WAKE_PMU_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1777;"	d
+RTC_TIMER_WAKE_PMU_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1776;"	d
+RTC_TIMER_WAKE_PMU_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1778;"	d
+RTC_TIMER_WAKE_PMU_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1780;"	d
+RTHR_H_HI	include/ssv6200_aux.h	4479;"	d
+RTHR_H_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3589;"	d
+RTHR_H_I_MSK	include/ssv6200_aux.h	4477;"	d
+RTHR_H_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3587;"	d
+RTHR_H_MSK	include/ssv6200_aux.h	4476;"	d
+RTHR_H_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3586;"	d
+RTHR_H_SFT	include/ssv6200_aux.h	4478;"	d
+RTHR_H_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3588;"	d
+RTHR_H_SZ	include/ssv6200_aux.h	4480;"	d
+RTHR_H_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3590;"	d
+RTHR_L_HI	include/ssv6200_aux.h	4474;"	d
+RTHR_L_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3584;"	d
+RTHR_L_I_MSK	include/ssv6200_aux.h	4472;"	d
+RTHR_L_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3582;"	d
+RTHR_L_MSK	include/ssv6200_aux.h	4471;"	d
+RTHR_L_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3581;"	d
+RTHR_L_SFT	include/ssv6200_aux.h	4473;"	d
+RTHR_L_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3583;"	d
+RTHR_L_SZ	include/ssv6200_aux.h	4475;"	d
+RTHR_L_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3585;"	d
+RTN_COUNT_CLR_HI	include/ssv6200_aux.h	11444;"	d
+RTN_COUNT_CLR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33014;"	d
+RTN_COUNT_CLR_I_MSK	include/ssv6200_aux.h	11442;"	d
+RTN_COUNT_CLR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33012;"	d
+RTN_COUNT_CLR_MSK	include/ssv6200_aux.h	11441;"	d
+RTN_COUNT_CLR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33011;"	d
+RTN_COUNT_CLR_SFT	include/ssv6200_aux.h	11443;"	d
+RTN_COUNT_CLR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33013;"	d
+RTN_COUNT_CLR_SZ	include/ssv6200_aux.h	11445;"	d
+RTN_COUNT_CLR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33015;"	d
+RTN_COUNT_HI	include/ssv6200_aux.h	11454;"	d
+RTN_COUNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33024;"	d
+RTN_COUNT_I_MSK	include/ssv6200_aux.h	11452;"	d
+RTN_COUNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33022;"	d
+RTN_COUNT_MSK	include/ssv6200_aux.h	11451;"	d
+RTN_COUNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33021;"	d
+RTN_COUNT_SFT	include/ssv6200_aux.h	11453;"	d
+RTN_COUNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33023;"	d
+RTN_COUNT_SZ	include/ssv6200_aux.h	11455;"	d
+RTN_COUNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33025;"	d
+RTS_CTS_PROTECT	smac/dev.h	281;"	d
+RTS_HI	include/ssv6200_aux.h	4369;"	d
+RTS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3474;"	d
+RTS_I_MSK	include/ssv6200_aux.h	4367;"	d
+RTS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3472;"	d
+RTS_LEN	smac/dev.h	160;"	d
+RTS_MSK	include/ssv6200_aux.h	4366;"	d
+RTS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3471;"	d
+RTS_SFT	include/ssv6200_aux.h	4368;"	d
+RTS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3473;"	d
+RTS_SZ	include/ssv6200_aux.h	4370;"	d
+RTS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3475;"	d
+RW_BUF_CLR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4179;"	d
+RW_BUF_CLR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4177;"	d
+RW_BUF_CLR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4176;"	d
+RW_BUF_CLR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4178;"	d
+RW_BUF_CLR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4180;"	d
+RXBUFLENGTH	bridge/sdiobridge.c	40;"	d	file:
+RXBUFLENGTH	hci_wrapper/ssv_huw.c	31;"	d	file:
+RXBUFSIZE	bridge/sdiobridge.c	41;"	d	file:
+RXBUFSIZE	hci_wrapper/ssv_huw.c	32;"	d	file:
+RXFIFO_RST_HI	include/ssv6200_aux.h	4299;"	d
+RXFIFO_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3404;"	d
+RXFIFO_RST_I_MSK	include/ssv6200_aux.h	4297;"	d
+RXFIFO_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3402;"	d
+RXFIFO_RST_MSK	include/ssv6200_aux.h	4296;"	d
+RXFIFO_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3401;"	d
+RXFIFO_RST_SFT	include/ssv6200_aux.h	4298;"	d
+RXFIFO_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3403;"	d
+RXFIFO_RST_SZ	include/ssv6200_aux.h	4300;"	d
+RXFIFO_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3405;"	d
+RXFIFO_TRGLVL_HI	include/ssv6200_aux.h	4324;"	d
+RXFIFO_TRGLVL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3429;"	d
+RXFIFO_TRGLVL_I_MSK	include/ssv6200_aux.h	4322;"	d
+RXFIFO_TRGLVL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3427;"	d
+RXFIFO_TRGLVL_MSK	include/ssv6200_aux.h	4321;"	d
+RXFIFO_TRGLVL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3426;"	d
+RXFIFO_TRGLVL_SFT	include/ssv6200_aux.h	4323;"	d
+RXFIFO_TRGLVL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3428;"	d
+RXFIFO_TRGLVL_SZ	include/ssv6200_aux.h	4325;"	d
+RXFIFO_TRGLVL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3430;"	d
+RXFULLFLAG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	904;"	d
+RXFULLFLAG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	902;"	d
+RXFULLFLAG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	901;"	d
+RXFULLFLAG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	903;"	d
+RXFULLFLAG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	905;"	d
+RXID_ALC_CNT_FAIL_HI	include/ssv6200_aux.h	9714;"	d
+RXID_ALC_CNT_FAIL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9549;"	d
+RXID_ALC_CNT_FAIL_I_MSK	include/ssv6200_aux.h	9712;"	d
+RXID_ALC_CNT_FAIL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9547;"	d
+RXID_ALC_CNT_FAIL_MSK	include/ssv6200_aux.h	9711;"	d
+RXID_ALC_CNT_FAIL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9546;"	d
+RXID_ALC_CNT_FAIL_SFT	include/ssv6200_aux.h	9713;"	d
+RXID_ALC_CNT_FAIL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9548;"	d
+RXID_ALC_CNT_FAIL_SZ	include/ssv6200_aux.h	9715;"	d
+RXID_ALC_CNT_FAIL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9550;"	d
+RXID_ALC_LEN_FAIL_HI	include/ssv6200_aux.h	9719;"	d
+RXID_ALC_LEN_FAIL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9554;"	d
+RXID_ALC_LEN_FAIL_I_MSK	include/ssv6200_aux.h	9717;"	d
+RXID_ALC_LEN_FAIL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9552;"	d
+RXID_ALC_LEN_FAIL_MSK	include/ssv6200_aux.h	9716;"	d
+RXID_ALC_LEN_FAIL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9551;"	d
+RXID_ALC_LEN_FAIL_SFT	include/ssv6200_aux.h	9718;"	d
+RXID_ALC_LEN_FAIL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9553;"	d
+RXID_ALC_LEN_FAIL_SZ	include/ssv6200_aux.h	9720;"	d
+RXID_ALC_LEN_FAIL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9555;"	d
+RXNOTEMPTYFLAG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	899;"	d
+RXNOTEMPTYFLAG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	897;"	d
+RXNOTEMPTYFLAG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	896;"	d
+RXNOTEMPTYFLAG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	898;"	d
+RXNOTEMPTYFLAG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	900;"	d
+RXPB_OFFSET	include/ssv6200_common.h	51;"	d
+RXPB_OFFSET	include/ssv6xxx_common.h	61;"	d
+RXTRAP_ETHTYPE0_HI	include/ssv6200_aux.h	6209;"	d
+RXTRAP_ETHTYPE0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5344;"	d
+RXTRAP_ETHTYPE0_I_MSK	include/ssv6200_aux.h	6207;"	d
+RXTRAP_ETHTYPE0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5342;"	d
+RXTRAP_ETHTYPE0_MSK	include/ssv6200_aux.h	6206;"	d
+RXTRAP_ETHTYPE0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5341;"	d
+RXTRAP_ETHTYPE0_SFT	include/ssv6200_aux.h	6208;"	d
+RXTRAP_ETHTYPE0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5343;"	d
+RXTRAP_ETHTYPE0_SZ	include/ssv6200_aux.h	6210;"	d
+RXTRAP_ETHTYPE0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5345;"	d
+RXTRAP_ETHTYPE1_HI	include/ssv6200_aux.h	6204;"	d
+RXTRAP_ETHTYPE1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5339;"	d
+RXTRAP_ETHTYPE1_I_MSK	include/ssv6200_aux.h	6202;"	d
+RXTRAP_ETHTYPE1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5337;"	d
+RXTRAP_ETHTYPE1_MSK	include/ssv6200_aux.h	6201;"	d
+RXTRAP_ETHTYPE1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5336;"	d
+RXTRAP_ETHTYPE1_SFT	include/ssv6200_aux.h	6203;"	d
+RXTRAP_ETHTYPE1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5338;"	d
+RXTRAP_ETHTYPE1_SZ	include/ssv6200_aux.h	6205;"	d
+RXTRAP_ETHTYPE1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5340;"	d
+RX_11B_CCA_IN_SCAN	smac/dev.c	4487;"	d	file:
+RX_11B_CCA_IN_SCAN	smac/dev.c	4680;"	d	file:
+RX_2_HOST_HI	include/ssv6200_aux.h	6059;"	d
+RX_2_HOST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5109;"	d
+RX_2_HOST_I_MSK	include/ssv6200_aux.h	6057;"	d
+RX_2_HOST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5107;"	d
+RX_2_HOST_MSK	include/ssv6200_aux.h	6056;"	d
+RX_2_HOST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5106;"	d
+RX_2_HOST_SFT	include/ssv6200_aux.h	6058;"	d
+RX_2_HOST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5108;"	d
+RX_2_HOST_SZ	include/ssv6200_aux.h	6060;"	d
+RX_2_HOST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5110;"	d
+RX_ACCU_LEN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5209;"	d
+RX_ACCU_LEN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5207;"	d
+RX_ACCU_LEN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5206;"	d
+RX_ACCU_LEN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5208;"	d
+RX_ACCU_LEN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5210;"	d
+RX_AGG_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5564;"	d
+RX_AGG_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5562;"	d
+RX_AGG_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5561;"	d
+RX_AGG_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5563;"	d
+RX_AGG_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5565;"	d
+RX_AGG_METHOD_3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5569;"	d
+RX_AGG_METHOD_3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5567;"	d
+RX_AGG_METHOD_3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5566;"	d
+RX_AGG_METHOD_3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5568;"	d
+RX_AGG_METHOD_3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5570;"	d
+RX_AGG_TIMER_RELOAD_VALUE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5574;"	d
+RX_AGG_TIMER_RELOAD_VALUE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5572;"	d
+RX_AGG_TIMER_RELOAD_VALUE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5571;"	d
+RX_AGG_TIMER_RELOAD_VALUE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5573;"	d
+RX_AGG_TIMER_RELOAD_VALUE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5575;"	d
+RX_BUF	include/ssv6xxx_common.h	/^    RX_BUF = 2$/;"	e	enum:__PBuf_Type_E
+RX_BURSTREAD_MODE	include/ssv6xxx_common.h	29;"	d
+RX_BURSTREAD_SZ_FROM_CMD	include/ssv6xxx_common.h	30;"	d
+RX_BURSTREAD_SZ_MAX_FRAME	include/ssv6xxx_common.h	31;"	d
+RX_BURSTREAD_SZ_MAX_FRAME_DMG	include/ssv6xxx_common.h	32;"	d
+RX_CIPHER_HCI	smac/dev.h	115;"	d
+RX_CIPHER_MIC_HCI	smac/dev.h	118;"	d
+RX_CPU_HCI	smac/dev.h	116;"	d
+RX_CS_DUR_HI	include/ssv6200_aux.h	7779;"	d
+RX_CS_DUR_I_MSK	include/ssv6200_aux.h	7777;"	d
+RX_CS_DUR_MSK	include/ssv6200_aux.h	7776;"	d
+RX_CS_DUR_SFT	include/ssv6200_aux.h	7778;"	d
+RX_CS_DUR_SZ	include/ssv6200_aux.h	7780;"	d
+RX_CTRL_FLOW	smac/dev.h	/^    RX_CTRL_FLOW,$/;"	e	enum:ssv_rx_flow
+RX_DATA_FLOW	smac/dev.h	/^    RX_DATA_FLOW,$/;"	e	enum:ssv_rx_flow
+RX_DEBUG_HCI_EXP_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5544;"	d
+RX_DEBUG_HCI_EXP_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5542;"	d
+RX_DEBUG_HCI_EXP_0_LENGHT_LIMIT_MAX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5559;"	d
+RX_DEBUG_HCI_EXP_0_LENGHT_LIMIT_MAX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5557;"	d
+RX_DEBUG_HCI_EXP_0_LENGHT_LIMIT_MAX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5556;"	d
+RX_DEBUG_HCI_EXP_0_LENGHT_LIMIT_MAX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5558;"	d
+RX_DEBUG_HCI_EXP_0_LENGHT_LIMIT_MAX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5560;"	d
+RX_DEBUG_HCI_EXP_0_LENGHT_LIMIT_MIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5554;"	d
+RX_DEBUG_HCI_EXP_0_LENGHT_LIMIT_MIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5552;"	d
+RX_DEBUG_HCI_EXP_0_LENGHT_LIMIT_MIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5551;"	d
+RX_DEBUG_HCI_EXP_0_LENGHT_LIMIT_MIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5553;"	d
+RX_DEBUG_HCI_EXP_0_LENGHT_LIMIT_MIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5555;"	d
+RX_DEBUG_HCI_EXP_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5541;"	d
+RX_DEBUG_HCI_EXP_0_RND_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5549;"	d
+RX_DEBUG_HCI_EXP_0_RND_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5547;"	d
+RX_DEBUG_HCI_EXP_0_RND_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5546;"	d
+RX_DEBUG_HCI_EXP_0_RND_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5548;"	d
+RX_DEBUG_HCI_EXP_0_RND_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5550;"	d
+RX_DEBUG_HCI_EXP_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5543;"	d
+RX_DEBUG_HCI_EXP_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5545;"	d
+RX_EN_DUR_HI	include/ssv6200_aux.h	7774;"	d
+RX_EN_DUR_I_MSK	include/ssv6200_aux.h	7772;"	d
+RX_EN_DUR_MSK	include/ssv6200_aux.h	7771;"	d
+RX_EN_DUR_SFT	include/ssv6200_aux.h	7773;"	d
+RX_EN_DUR_SZ	include/ssv6200_aux.h	7775;"	d
+RX_ETHER_TRAP_EN_HI	include/ssv6200_aux.h	6104;"	d
+RX_ETHER_TRAP_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5154;"	d
+RX_ETHER_TRAP_EN_I_MSK	include/ssv6200_aux.h	6102;"	d
+RX_ETHER_TRAP_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5152;"	d
+RX_ETHER_TRAP_EN_MSK	include/ssv6200_aux.h	6101;"	d
+RX_ETHER_TRAP_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5151;"	d
+RX_ETHER_TRAP_EN_SFT	include/ssv6200_aux.h	6103;"	d
+RX_ETHER_TRAP_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5153;"	d
+RX_ETHER_TRAP_EN_SZ	include/ssv6200_aux.h	6105;"	d
+RX_ETHER_TRAP_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5155;"	d
+RX_FIFO_FAIL_HI	include/ssv6200_aux.h	3974;"	d
+RX_FIFO_FAIL_I_MSK	include/ssv6200_aux.h	3972;"	d
+RX_FIFO_FAIL_MSK	include/ssv6200_aux.h	3971;"	d
+RX_FIFO_FAIL_SFT	include/ssv6200_aux.h	3973;"	d
+RX_FIFO_FAIL_SZ	include/ssv6200_aux.h	3975;"	d
+RX_FIFO_RESIDUE_HI	include/ssv6200_aux.h	4109;"	d
+RX_FIFO_RESIDUE_I_MSK	include/ssv6200_aux.h	4107;"	d
+RX_FIFO_RESIDUE_MSK	include/ssv6200_aux.h	4106;"	d
+RX_FIFO_RESIDUE_SFT	include/ssv6200_aux.h	4108;"	d
+RX_FIFO_RESIDUE_SZ	include/ssv6200_aux.h	4110;"	d
+RX_FIFO_TO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3629;"	d
+RX_FIFO_TO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3627;"	d
+RX_FIFO_TO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3626;"	d
+RX_FIFO_TO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3628;"	d
+RX_FIFO_TO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3630;"	d
+RX_FLOW_CTRL_HI	include/ssv6200_aux.h	7114;"	d
+RX_FLOW_CTRL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6289;"	d
+RX_FLOW_CTRL_I_MSK	include/ssv6200_aux.h	7112;"	d
+RX_FLOW_CTRL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6287;"	d
+RX_FLOW_CTRL_MSK	include/ssv6200_aux.h	7111;"	d
+RX_FLOW_CTRL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6286;"	d
+RX_FLOW_CTRL_SFT	include/ssv6200_aux.h	7113;"	d
+RX_FLOW_CTRL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6288;"	d
+RX_FLOW_CTRL_SZ	include/ssv6200_aux.h	7115;"	d
+RX_FLOW_CTRL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6290;"	d
+RX_FLOW_DATA_HI	include/ssv6200_aux.h	7104;"	d
+RX_FLOW_DATA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6279;"	d
+RX_FLOW_DATA_I_MSK	include/ssv6200_aux.h	7102;"	d
+RX_FLOW_DATA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6277;"	d
+RX_FLOW_DATA_MSK	include/ssv6200_aux.h	7101;"	d
+RX_FLOW_DATA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6276;"	d
+RX_FLOW_DATA_SFT	include/ssv6200_aux.h	7103;"	d
+RX_FLOW_DATA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6278;"	d
+RX_FLOW_DATA_SZ	include/ssv6200_aux.h	7105;"	d
+RX_FLOW_DATA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6280;"	d
+RX_FLOW_MNG_HI	include/ssv6200_aux.h	7109;"	d
+RX_FLOW_MNG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6284;"	d
+RX_FLOW_MNG_I_MSK	include/ssv6200_aux.h	7107;"	d
+RX_FLOW_MNG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6282;"	d
+RX_FLOW_MNG_MSK	include/ssv6200_aux.h	7106;"	d
+RX_FLOW_MNG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6281;"	d
+RX_FLOW_MNG_SFT	include/ssv6200_aux.h	7108;"	d
+RX_FLOW_MNG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6283;"	d
+RX_FLOW_MNG_SZ	include/ssv6200_aux.h	7110;"	d
+RX_FLOW_MNG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6285;"	d
+RX_GET_TX_QUEUE_EN_HI	include/ssv6200_aux.h	6114;"	d
+RX_GET_TX_QUEUE_EN_I_MSK	include/ssv6200_aux.h	6112;"	d
+RX_GET_TX_QUEUE_EN_MSK	include/ssv6200_aux.h	6111;"	d
+RX_GET_TX_QUEUE_EN_SFT	include/ssv6200_aux.h	6113;"	d
+RX_GET_TX_QUEUE_EN_SZ	include/ssv6200_aux.h	6115;"	d
+RX_HCI	smac/dev.h	114;"	d
+RX_HOST_FAIL_HI	include/ssv6200_aux.h	3979;"	d
+RX_HOST_FAIL_I_MSK	include/ssv6200_aux.h	3977;"	d
+RX_HOST_FAIL_MSK	include/ssv6200_aux.h	3976;"	d
+RX_HOST_FAIL_SFT	include/ssv6200_aux.h	3978;"	d
+RX_HOST_FAIL_SZ	include/ssv6200_aux.h	3980;"	d
+RX_HW_AGG_MODE	include/ssv6xxx_common.h	27;"	d
+RX_HW_AGG_MODE_METH3	include/ssv6xxx_common.h	28;"	d
+RX_IDLE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3599;"	d
+RX_IDLE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3597;"	d
+RX_IDLE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3596;"	d
+RX_IDLE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3598;"	d
+RX_IDLE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3600;"	d
+RX_ID_ALC_LEN_HI	include/ssv6200_aux.h	12759;"	d
+RX_ID_ALC_LEN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34284;"	d
+RX_ID_ALC_LEN_I_MSK	include/ssv6200_aux.h	12757;"	d
+RX_ID_ALC_LEN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34282;"	d
+RX_ID_ALC_LEN_MSK	include/ssv6200_aux.h	12756;"	d
+RX_ID_ALC_LEN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34281;"	d
+RX_ID_ALC_LEN_SFT	include/ssv6200_aux.h	12758;"	d
+RX_ID_ALC_LEN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34283;"	d
+RX_ID_ALC_LEN_SZ	include/ssv6200_aux.h	12760;"	d
+RX_ID_ALC_LEN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34285;"	d
+RX_ID_COUNT_HI	include/ssv6200_aux.h	12639;"	d
+RX_ID_COUNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34164;"	d
+RX_ID_COUNT_I_MSK	include/ssv6200_aux.h	12637;"	d
+RX_ID_COUNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34162;"	d
+RX_ID_COUNT_MSK	include/ssv6200_aux.h	12636;"	d
+RX_ID_COUNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34161;"	d
+RX_ID_COUNT_SFT	include/ssv6200_aux.h	12638;"	d
+RX_ID_COUNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34163;"	d
+RX_ID_COUNT_SZ	include/ssv6200_aux.h	12640;"	d
+RX_ID_COUNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34165;"	d
+RX_ID_IFO_LEN_HI	include/ssv6200_aux.h	12944;"	d
+RX_ID_IFO_LEN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34479;"	d
+RX_ID_IFO_LEN_I_MSK	include/ssv6200_aux.h	12942;"	d
+RX_ID_IFO_LEN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34477;"	d
+RX_ID_IFO_LEN_MSK	include/ssv6200_aux.h	12941;"	d
+RX_ID_IFO_LEN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34476;"	d
+RX_ID_IFO_LEN_SFT	include/ssv6200_aux.h	12943;"	d
+RX_ID_IFO_LEN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34478;"	d
+RX_ID_IFO_LEN_SZ	include/ssv6200_aux.h	12945;"	d
+RX_ID_IFO_LEN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34480;"	d
+RX_ID_LEN_THOLD_HI	include/ssv6200_aux.h	5019;"	d
+RX_ID_LEN_THOLD_INT_HI	include/ssv6200_aux.h	12729;"	d
+RX_ID_LEN_THOLD_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34254;"	d
+RX_ID_LEN_THOLD_INT_I_MSK	include/ssv6200_aux.h	12727;"	d
+RX_ID_LEN_THOLD_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34252;"	d
+RX_ID_LEN_THOLD_INT_MSK	include/ssv6200_aux.h	12726;"	d
+RX_ID_LEN_THOLD_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34251;"	d
+RX_ID_LEN_THOLD_INT_SFT	include/ssv6200_aux.h	12728;"	d
+RX_ID_LEN_THOLD_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34253;"	d
+RX_ID_LEN_THOLD_INT_SZ	include/ssv6200_aux.h	12730;"	d
+RX_ID_LEN_THOLD_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34255;"	d
+RX_ID_LEN_THOLD_I_MSK	include/ssv6200_aux.h	5017;"	d
+RX_ID_LEN_THOLD_MSK	include/ssv6200_aux.h	5016;"	d
+RX_ID_LEN_THOLD_SD_HI	include/ssv6200_aux.h	5364;"	d
+RX_ID_LEN_THOLD_SD_I_MSK	include/ssv6200_aux.h	5362;"	d
+RX_ID_LEN_THOLD_SD_MSK	include/ssv6200_aux.h	5361;"	d
+RX_ID_LEN_THOLD_SD_SFT	include/ssv6200_aux.h	5363;"	d
+RX_ID_LEN_THOLD_SD_SZ	include/ssv6200_aux.h	5365;"	d
+RX_ID_LEN_THOLD_SFT	include/ssv6200_aux.h	5018;"	d
+RX_ID_LEN_THOLD_SZ	include/ssv6200_aux.h	5020;"	d
+RX_ID_TB0_HI	include/ssv6200_aux.h	12689;"	d
+RX_ID_TB0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34214;"	d
+RX_ID_TB0_I_MSK	include/ssv6200_aux.h	12687;"	d
+RX_ID_TB0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34212;"	d
+RX_ID_TB0_MSK	include/ssv6200_aux.h	12686;"	d
+RX_ID_TB0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34211;"	d
+RX_ID_TB0_SFT	include/ssv6200_aux.h	12688;"	d
+RX_ID_TB0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34213;"	d
+RX_ID_TB0_SZ	include/ssv6200_aux.h	12690;"	d
+RX_ID_TB0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34215;"	d
+RX_ID_TB1_HI	include/ssv6200_aux.h	12694;"	d
+RX_ID_TB1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34219;"	d
+RX_ID_TB1_I_MSK	include/ssv6200_aux.h	12692;"	d
+RX_ID_TB1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34217;"	d
+RX_ID_TB1_MSK	include/ssv6200_aux.h	12691;"	d
+RX_ID_TB1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34216;"	d
+RX_ID_TB1_SFT	include/ssv6200_aux.h	12693;"	d
+RX_ID_TB1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34218;"	d
+RX_ID_TB1_SZ	include/ssv6200_aux.h	12695;"	d
+RX_ID_TB1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34220;"	d
+RX_ID_TB2_HI	include/ssv6200_aux.h	12874;"	d
+RX_ID_TB2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34399;"	d
+RX_ID_TB2_I_MSK	include/ssv6200_aux.h	12872;"	d
+RX_ID_TB2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34397;"	d
+RX_ID_TB2_MSK	include/ssv6200_aux.h	12871;"	d
+RX_ID_TB2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34396;"	d
+RX_ID_TB2_SFT	include/ssv6200_aux.h	12873;"	d
+RX_ID_TB2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34398;"	d
+RX_ID_TB2_SZ	include/ssv6200_aux.h	12875;"	d
+RX_ID_TB2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34400;"	d
+RX_ID_TB3_HI	include/ssv6200_aux.h	12879;"	d
+RX_ID_TB3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34404;"	d
+RX_ID_TB3_I_MSK	include/ssv6200_aux.h	12877;"	d
+RX_ID_TB3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34402;"	d
+RX_ID_TB3_MSK	include/ssv6200_aux.h	12876;"	d
+RX_ID_TB3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34401;"	d
+RX_ID_TB3_SFT	include/ssv6200_aux.h	12878;"	d
+RX_ID_TB3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34403;"	d
+RX_ID_TB3_SZ	include/ssv6200_aux.h	12880;"	d
+RX_ID_TB3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34405;"	d
+RX_ID_THOLD_HI	include/ssv6200_aux.h	12649;"	d
+RX_ID_THOLD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34174;"	d
+RX_ID_THOLD_I_MSK	include/ssv6200_aux.h	12647;"	d
+RX_ID_THOLD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34172;"	d
+RX_ID_THOLD_MSK	include/ssv6200_aux.h	12646;"	d
+RX_ID_THOLD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34171;"	d
+RX_ID_THOLD_SFT	include/ssv6200_aux.h	12648;"	d
+RX_ID_THOLD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34173;"	d
+RX_ID_THOLD_SZ	include/ssv6200_aux.h	12650;"	d
+RX_ID_THOLD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34175;"	d
+RX_INFO_SIZE_HI	include/ssv6200_aux.h	6174;"	d
+RX_INFO_SIZE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5269;"	d
+RX_INFO_SIZE_I_MSK	include/ssv6200_aux.h	6172;"	d
+RX_INFO_SIZE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5267;"	d
+RX_INFO_SIZE_MSK	include/ssv6200_aux.h	6171;"	d
+RX_INFO_SIZE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5266;"	d
+RX_INFO_SIZE_SFT	include/ssv6200_aux.h	6173;"	d
+RX_INFO_SIZE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5268;"	d
+RX_INFO_SIZE_SZ	include/ssv6200_aux.h	6175;"	d
+RX_INFO_SIZE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5270;"	d
+RX_INT1_HI	include/ssv6200_aux.h	3219;"	d
+RX_INT1_I_MSK	include/ssv6200_aux.h	3217;"	d
+RX_INT1_MSK	include/ssv6200_aux.h	3216;"	d
+RX_INT1_SFT	include/ssv6200_aux.h	3218;"	d
+RX_INT1_SZ	include/ssv6200_aux.h	3220;"	d
+RX_INT3_HI	include/ssv6200_aux.h	3634;"	d
+RX_INT3_I_MSK	include/ssv6200_aux.h	3632;"	d
+RX_INT3_MSK	include/ssv6200_aux.h	3631;"	d
+RX_INT3_SFT	include/ssv6200_aux.h	3633;"	d
+RX_INT3_SZ	include/ssv6200_aux.h	3635;"	d
+RX_INT_CH_HI	include/ssv6200_aux.h	12659;"	d
+RX_INT_CH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34184;"	d
+RX_INT_CH_I_MSK	include/ssv6200_aux.h	12657;"	d
+RX_INT_CH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34182;"	d
+RX_INT_CH_MSK	include/ssv6200_aux.h	12656;"	d
+RX_INT_CH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34181;"	d
+RX_INT_CH_SFT	include/ssv6200_aux.h	12658;"	d
+RX_INT_CH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34183;"	d
+RX_INT_CH_SZ	include/ssv6200_aux.h	12660;"	d
+RX_INT_CH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34185;"	d
+RX_INT_HI	include/ssv6200_aux.h	3079;"	d
+RX_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2549;"	d
+RX_INT_I_MSK	include/ssv6200_aux.h	3077;"	d
+RX_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2547;"	d
+RX_INT_MSK	include/ssv6200_aux.h	3076;"	d
+RX_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2546;"	d
+RX_INT_SFT	include/ssv6200_aux.h	3078;"	d
+RX_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2548;"	d
+RX_INT_SZ	include/ssv6200_aux.h	3080;"	d
+RX_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2550;"	d
+RX_INT_TIMEOUT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5234;"	d
+RX_INT_TIMEOUT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5232;"	d
+RX_INT_TIMEOUT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5231;"	d
+RX_INT_TIMEOUT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5233;"	d
+RX_INT_TIMEOUT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5235;"	d
+RX_LAST_PHY_SIZE_HI	include/ssv6200_aux.h	6179;"	d
+RX_LAST_PHY_SIZE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5274;"	d
+RX_LAST_PHY_SIZE_I_MSK	include/ssv6200_aux.h	6177;"	d
+RX_LAST_PHY_SIZE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5272;"	d
+RX_LAST_PHY_SIZE_MSK	include/ssv6200_aux.h	6176;"	d
+RX_LAST_PHY_SIZE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5271;"	d
+RX_LAST_PHY_SIZE_SFT	include/ssv6200_aux.h	6178;"	d
+RX_LAST_PHY_SIZE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5273;"	d
+RX_LAST_PHY_SIZE_SZ	include/ssv6200_aux.h	6180;"	d
+RX_LAST_PHY_SIZE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5275;"	d
+RX_LEN_HI	include/ssv6200_aux.h	4019;"	d
+RX_LEN_I_MSK	include/ssv6200_aux.h	4017;"	d
+RX_LEN_MSK	include/ssv6200_aux.h	4016;"	d
+RX_LEN_SFT	include/ssv6200_aux.h	4018;"	d
+RX_LEN_SZ	include/ssv6200_aux.h	4020;"	d
+RX_LINESTS_IE_HI	include/ssv6200_aux.h	4274;"	d
+RX_LINESTS_IE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3379;"	d
+RX_LINESTS_IE_I_MSK	include/ssv6200_aux.h	4272;"	d
+RX_LINESTS_IE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3377;"	d
+RX_LINESTS_IE_MSK	include/ssv6200_aux.h	4271;"	d
+RX_LINESTS_IE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3376;"	d
+RX_LINESTS_IE_SFT	include/ssv6200_aux.h	4273;"	d
+RX_LINESTS_IE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3378;"	d
+RX_LINESTS_IE_SZ	include/ssv6200_aux.h	4275;"	d
+RX_LINESTS_IE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3380;"	d
+RX_MGMT_FLOW	smac/dev.h	/^    RX_MGMT_FLOW,$/;"	e	enum:ssv_rx_flow
+RX_MOUNT_HI	include/ssv6200_aux.h	17979;"	d
+RX_MOUNT_I_MSK	include/ssv6200_aux.h	17977;"	d
+RX_MOUNT_MSK	include/ssv6200_aux.h	17976;"	d
+RX_MOUNT_SFT	include/ssv6200_aux.h	17978;"	d
+RX_MOUNT_SZ	include/ssv6200_aux.h	17980;"	d
+RX_NORMAL_MODE	include/ssv6xxx_common.h	26;"	d
+RX_NULL_TRAP_EN_HI	include/ssv6200_aux.h	6109;"	d
+RX_NULL_TRAP_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5159;"	d
+RX_NULL_TRAP_EN_I_MSK	include/ssv6200_aux.h	6107;"	d
+RX_NULL_TRAP_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5157;"	d
+RX_NULL_TRAP_EN_MSK	include/ssv6200_aux.h	6106;"	d
+RX_NULL_TRAP_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5156;"	d
+RX_NULL_TRAP_EN_SFT	include/ssv6200_aux.h	6108;"	d
+RX_NULL_TRAP_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5158;"	d
+RX_NULL_TRAP_EN_SZ	include/ssv6200_aux.h	6110;"	d
+RX_NULL_TRAP_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5160;"	d
+RX_PACKET_LENGTH2_HI	include/ssv6200_aux.h	3214;"	d
+RX_PACKET_LENGTH2_I_MSK	include/ssv6200_aux.h	3212;"	d
+RX_PACKET_LENGTH2_MSK	include/ssv6200_aux.h	3211;"	d
+RX_PACKET_LENGTH2_SFT	include/ssv6200_aux.h	3213;"	d
+RX_PACKET_LENGTH2_SZ	include/ssv6200_aux.h	3215;"	d
+RX_PACKET_LENGTH3_HI	include/ssv6200_aux.h	3629;"	d
+RX_PACKET_LENGTH3_I_MSK	include/ssv6200_aux.h	3627;"	d
+RX_PACKET_LENGTH3_MSK	include/ssv6200_aux.h	3626;"	d
+RX_PACKET_LENGTH3_SFT	include/ssv6200_aux.h	3628;"	d
+RX_PACKET_LENGTH3_SZ	include/ssv6200_aux.h	3630;"	d
+RX_PACKET_LENGTH_HI	include/ssv6200_aux.h	3174;"	d
+RX_PACKET_LENGTH_I_MSK	include/ssv6200_aux.h	3172;"	d
+RX_PACKET_LENGTH_MSK	include/ssv6200_aux.h	3171;"	d
+RX_PACKET_LENGTH_SFT	include/ssv6200_aux.h	3173;"	d
+RX_PACKET_LENGTH_SZ	include/ssv6200_aux.h	3175;"	d
+RX_PER_RD_LEN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5289;"	d
+RX_PER_RD_LEN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5287;"	d
+RX_PER_RD_LEN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5286;"	d
+RX_PER_RD_LEN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5288;"	d
+RX_PER_RD_LEN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5290;"	d
+RX_PHY_11B_SOFT_RST_N_HI	include/ssv6200_aux.h	14664;"	d
+RX_PHY_11B_SOFT_RST_N_I_MSK	include/ssv6200_aux.h	14662;"	d
+RX_PHY_11B_SOFT_RST_N_MSK	include/ssv6200_aux.h	14661;"	d
+RX_PHY_11B_SOFT_RST_N_SFT	include/ssv6200_aux.h	14663;"	d
+RX_PHY_11B_SOFT_RST_N_SZ	include/ssv6200_aux.h	14665;"	d
+RX_PHY_11GN_SOFT_RST_N_HI	include/ssv6200_aux.h	15304;"	d
+RX_PHY_11GN_SOFT_RST_N_I_MSK	include/ssv6200_aux.h	15302;"	d
+RX_PHY_11GN_SOFT_RST_N_MSK	include/ssv6200_aux.h	15301;"	d
+RX_PHY_11GN_SOFT_RST_N_SFT	include/ssv6200_aux.h	15303;"	d
+RX_PHY_11GN_SOFT_RST_N_SZ	include/ssv6200_aux.h	15305;"	d
+RX_PKT_COUNTER_HI	include/ssv6200_aux.h	6219;"	d
+RX_PKT_COUNTER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5489;"	d
+RX_PKT_COUNTER_I_MSK	include/ssv6200_aux.h	6217;"	d
+RX_PKT_COUNTER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5487;"	d
+RX_PKT_COUNTER_MSK	include/ssv6200_aux.h	6216;"	d
+RX_PKT_COUNTER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5486;"	d
+RX_PKT_COUNTER_SFT	include/ssv6200_aux.h	6218;"	d
+RX_PKT_COUNTER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5488;"	d
+RX_PKT_COUNTER_SZ	include/ssv6200_aux.h	6220;"	d
+RX_PKT_COUNTER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5490;"	d
+RX_PKT_DROP_COUNTER_HI	include/ssv6200_aux.h	6239;"	d
+RX_PKT_DROP_COUNTER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5469;"	d
+RX_PKT_DROP_COUNTER_I_MSK	include/ssv6200_aux.h	6237;"	d
+RX_PKT_DROP_COUNTER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5467;"	d
+RX_PKT_DROP_COUNTER_MSK	include/ssv6200_aux.h	6236;"	d
+RX_PKT_DROP_COUNTER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5466;"	d
+RX_PKT_DROP_COUNTER_SFT	include/ssv6200_aux.h	6238;"	d
+RX_PKT_DROP_COUNTER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5468;"	d
+RX_PKT_DROP_COUNTER_SZ	include/ssv6200_aux.h	6240;"	d
+RX_PKT_DROP_COUNTER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5470;"	d
+RX_PKT_TRAP_COUNTER_HI	include/ssv6200_aux.h	6249;"	d
+RX_PKT_TRAP_COUNTER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5459;"	d
+RX_PKT_TRAP_COUNTER_I_MSK	include/ssv6200_aux.h	6247;"	d
+RX_PKT_TRAP_COUNTER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5457;"	d
+RX_PKT_TRAP_COUNTER_MSK	include/ssv6200_aux.h	6246;"	d
+RX_PKT_TRAP_COUNTER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5456;"	d
+RX_PKT_TRAP_COUNTER_SFT	include/ssv6200_aux.h	6248;"	d
+RX_PKT_TRAP_COUNTER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5458;"	d
+RX_PKT_TRAP_COUNTER_SZ	include/ssv6200_aux.h	6250;"	d
+RX_PKT_TRAP_COUNTER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5460;"	d
+RX_QUOTA_HI	include/ssv6200_aux.h	3929;"	d
+RX_QUOTA_I_MSK	include/ssv6200_aux.h	3927;"	d
+RX_QUOTA_MSK	include/ssv6200_aux.h	3926;"	d
+RX_QUOTA_SFT	include/ssv6200_aux.h	3928;"	d
+RX_QUOTA_SZ	include/ssv6200_aux.h	3930;"	d
+RX_RDY_HI	include/ssv6200_aux.h	4114;"	d
+RX_RDY_I_MSK	include/ssv6200_aux.h	4112;"	d
+RX_RDY_MSK	include/ssv6200_aux.h	4111;"	d
+RX_RDY_SFT	include/ssv6200_aux.h	4113;"	d
+RX_RDY_SZ	include/ssv6200_aux.h	4115;"	d
+RX_RECIEVED_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3624;"	d
+RX_RECIEVED_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3622;"	d
+RX_RECIEVED_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3621;"	d
+RX_RECIEVED_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3623;"	d
+RX_RECIEVED_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3625;"	d
+RX_TRAP_HW_ID_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5539;"	d
+RX_TRAP_HW_ID_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5537;"	d
+RX_TRAP_HW_ID_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5536;"	d
+RX_TRAP_HW_ID_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5538;"	d
+RX_TRAP_HW_ID_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5540;"	d
+RX_TRASH	smac/dev.h	117;"	d
+R_BOOTSTRAP_SAMPLE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1319;"	d
+R_BOOTSTRAP_SAMPLE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1317;"	d
+R_BOOTSTRAP_SAMPLE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1316;"	d
+R_BOOTSTRAP_SAMPLE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1318;"	d
+R_BOOTSTRAP_SAMPLE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1320;"	d
+RotR1	smac/sec_tkip.c	/^static inline u16 RotR1(u16 val)$/;"	f	file:	signature:(u16 val)
+RxResult	include/ssv6200_common.h	/^    u32 RxResult:8;$/;"	m	struct:ssv6200_rx_desc	access:public
+RxResult	smac/hal/ssv6006c/turismo_common.h	/^    u32 RxResult:8;$/;"	m	struct:ssv6006_rx_desc	access:public
+SAME_ID_ALLOC_MD_HI	include/ssv6200_aux.h	17674;"	d
+SAME_ID_ALLOC_MD_I_MSK	include/ssv6200_aux.h	17672;"	d
+SAME_ID_ALLOC_MD_MSK	include/ssv6200_aux.h	17671;"	d
+SAME_ID_ALLOC_MD_SFT	include/ssv6200_aux.h	17673;"	d
+SAME_ID_ALLOC_MD_SZ	include/ssv6200_aux.h	17675;"	d
+SAMPLE_COLUMNS	smac/ssv_ht_rc.c	26;"	d	file:
+SAMPLE_COLUMNS	smac/ssv_rc_minstrel.c	25;"	d	file:
+SAMPLE_COLUMNS	smac/ssv_rc_minstrel_ht.c	30;"	d	file:
+SAMPLE_COUNT	smac/ssv_ht_rc.c	22;"	d	file:
+SAMPLE_TBL	smac/ssv_rc_minstrel.c	26;"	d	file:
+SAR_ADC_FSM_RDY_HI	include/ssv6200_aux.h	17594;"	d
+SAR_ADC_FSM_RDY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	24824;"	d
+SAR_ADC_FSM_RDY_I_MSK	include/ssv6200_aux.h	17592;"	d
+SAR_ADC_FSM_RDY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24822;"	d
+SAR_ADC_FSM_RDY_MSK	include/ssv6200_aux.h	17591;"	d
+SAR_ADC_FSM_RDY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	24821;"	d
+SAR_ADC_FSM_RDY_SFT	include/ssv6200_aux.h	17593;"	d
+SAR_ADC_FSM_RDY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	24823;"	d
+SAR_ADC_FSM_RDY_SZ	include/ssv6200_aux.h	17595;"	d
+SAR_ADC_FSM_RDY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	24825;"	d
+SBUS_DMAC_BLOCK0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	319;"	d
+SBUS_DMAC_BLOCK0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	317;"	d
+SBUS_DMAC_BLOCK0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	316;"	d
+SBUS_DMAC_BLOCK0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	318;"	d
+SBUS_DMAC_BLOCK0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	320;"	d
+SBUS_DMAC_BLOCK1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	404;"	d
+SBUS_DMAC_BLOCK1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	402;"	d
+SBUS_DMAC_BLOCK1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	401;"	d
+SBUS_DMAC_BLOCK1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	403;"	d
+SBUS_DMAC_BLOCK1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	405;"	d
+SBUS_DMAC_CH0_CLR_ERR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	479;"	d
+SBUS_DMAC_CH0_CLR_ERR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	477;"	d
+SBUS_DMAC_CH0_CLR_ERR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	476;"	d
+SBUS_DMAC_CH0_CLR_ERR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	478;"	d
+SBUS_DMAC_CH0_CLR_ERR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	480;"	d
+SBUS_DMAC_CH0_CLR_TR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	469;"	d
+SBUS_DMAC_CH0_CLR_TR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	467;"	d
+SBUS_DMAC_CH0_CLR_TR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	466;"	d
+SBUS_DMAC_CH0_CLR_TR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	468;"	d
+SBUS_DMAC_CH0_CLR_TR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	470;"	d
+SBUS_DMAC_CH0_PRIOR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	324;"	d
+SBUS_DMAC_CH0_PRIOR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	322;"	d
+SBUS_DMAC_CH0_PRIOR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	321;"	d
+SBUS_DMAC_CH0_PRIOR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	323;"	d
+SBUS_DMAC_CH0_PRIOR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	325;"	d
+SBUS_DMAC_CH1_CLR_ERR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	484;"	d
+SBUS_DMAC_CH1_CLR_ERR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	482;"	d
+SBUS_DMAC_CH1_CLR_ERR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	481;"	d
+SBUS_DMAC_CH1_CLR_ERR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	483;"	d
+SBUS_DMAC_CH1_CLR_ERR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	485;"	d
+SBUS_DMAC_CH1_CLR_TR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	474;"	d
+SBUS_DMAC_CH1_CLR_TR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	472;"	d
+SBUS_DMAC_CH1_CLR_TR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	471;"	d
+SBUS_DMAC_CH1_CLR_TR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	473;"	d
+SBUS_DMAC_CH1_CLR_TR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	475;"	d
+SBUS_DMAC_CH1_PRIOR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	409;"	d
+SBUS_DMAC_CH1_PRIOR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	407;"	d
+SBUS_DMAC_CH1_PRIOR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	406;"	d
+SBUS_DMAC_CH1_PRIOR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	408;"	d
+SBUS_DMAC_CH1_PRIOR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	410;"	d
+SBUS_DMAC_CH_DEMASK_ERR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	464;"	d
+SBUS_DMAC_CH_DEMASK_ERR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	462;"	d
+SBUS_DMAC_CH_DEMASK_ERR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	461;"	d
+SBUS_DMAC_CH_DEMASK_ERR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	463;"	d
+SBUS_DMAC_CH_DEMASK_ERR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	465;"	d
+SBUS_DMAC_CH_DEMASK_TR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	459;"	d
+SBUS_DMAC_CH_DEMASK_TR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	457;"	d
+SBUS_DMAC_CH_DEMASK_TR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	456;"	d
+SBUS_DMAC_CH_DEMASK_TR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	458;"	d
+SBUS_DMAC_CH_DEMASK_TR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	460;"	d
+SBUS_DMAC_CH_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	514;"	d
+SBUS_DMAC_CH_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	512;"	d
+SBUS_DMAC_CH_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	511;"	d
+SBUS_DMAC_CH_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	513;"	d
+SBUS_DMAC_CH_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	515;"	d
+SBUS_DMAC_CH_ERR_TR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	444;"	d
+SBUS_DMAC_CH_ERR_TR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	442;"	d
+SBUS_DMAC_CH_ERR_TR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	441;"	d
+SBUS_DMAC_CH_ERR_TR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	443;"	d
+SBUS_DMAC_CH_ERR_TR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	445;"	d
+SBUS_DMAC_CH_RAW_TR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	439;"	d
+SBUS_DMAC_CH_RAW_TR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	437;"	d
+SBUS_DMAC_CH_RAW_TR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	436;"	d
+SBUS_DMAC_CH_RAW_TR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	438;"	d
+SBUS_DMAC_CH_RAW_TR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	440;"	d
+SBUS_DMAC_CH_STATUSERR_TR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	454;"	d
+SBUS_DMAC_CH_STATUSERR_TR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	452;"	d
+SBUS_DMAC_CH_STATUSERR_TR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	451;"	d
+SBUS_DMAC_CH_STATUSERR_TR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	453;"	d
+SBUS_DMAC_CH_STATUSERR_TR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	455;"	d
+SBUS_DMAC_CH_STATUSTR_TR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	449;"	d
+SBUS_DMAC_CH_STATUSTR_TR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	447;"	d
+SBUS_DMAC_CH_STATUSTR_TR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	446;"	d
+SBUS_DMAC_CH_STATUSTR_TR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	448;"	d
+SBUS_DMAC_CH_STATUSTR_TR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	450;"	d
+SBUS_DMAC_DAR0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	274;"	d
+SBUS_DMAC_DAR0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	272;"	d
+SBUS_DMAC_DAR0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	271;"	d
+SBUS_DMAC_DAR0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	273;"	d
+SBUS_DMAC_DAR0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	275;"	d
+SBUS_DMAC_DAR1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	359;"	d
+SBUS_DMAC_DAR1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	357;"	d
+SBUS_DMAC_DAR1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	356;"	d
+SBUS_DMAC_DAR1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	358;"	d
+SBUS_DMAC_DAR1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	360;"	d
+SBUS_DMAC_DINC0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	294;"	d
+SBUS_DMAC_DINC0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	292;"	d
+SBUS_DMAC_DINC0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	291;"	d
+SBUS_DMAC_DINC0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	293;"	d
+SBUS_DMAC_DINC0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	295;"	d
+SBUS_DMAC_DINC1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	379;"	d
+SBUS_DMAC_DINC1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	377;"	d
+SBUS_DMAC_DINC1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	376;"	d
+SBUS_DMAC_DINC1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	378;"	d
+SBUS_DMAC_DINC1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	380;"	d
+SBUS_DMAC_DISEN_SHS_DST_REQ_HI	smac/hal/ssv6006c/ssv6006C_aux.h	494;"	d
+SBUS_DMAC_DISEN_SHS_DST_REQ_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	492;"	d
+SBUS_DMAC_DISEN_SHS_DST_REQ_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	491;"	d
+SBUS_DMAC_DISEN_SHS_DST_REQ_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	493;"	d
+SBUS_DMAC_DISEN_SHS_DST_REQ_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	495;"	d
+SBUS_DMAC_DISEN_SHS_DST_SREQ_HI	smac/hal/ssv6006c/ssv6006C_aux.h	504;"	d
+SBUS_DMAC_DISEN_SHS_DST_SREQ_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	502;"	d
+SBUS_DMAC_DISEN_SHS_DST_SREQ_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	501;"	d
+SBUS_DMAC_DISEN_SHS_DST_SREQ_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	503;"	d
+SBUS_DMAC_DISEN_SHS_DST_SREQ_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	505;"	d
+SBUS_DMAC_DISEN_SHS_SRC_REQ_HI	smac/hal/ssv6006c/ssv6006C_aux.h	489;"	d
+SBUS_DMAC_DISEN_SHS_SRC_REQ_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	487;"	d
+SBUS_DMAC_DISEN_SHS_SRC_REQ_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	486;"	d
+SBUS_DMAC_DISEN_SHS_SRC_REQ_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	488;"	d
+SBUS_DMAC_DISEN_SHS_SRC_REQ_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	490;"	d
+SBUS_DMAC_DISEN_SHS_SRC_SREQ_HI	smac/hal/ssv6006c/ssv6006C_aux.h	499;"	d
+SBUS_DMAC_DISEN_SHS_SRC_SREQ_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	497;"	d
+SBUS_DMAC_DISEN_SHS_SRC_SREQ_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	496;"	d
+SBUS_DMAC_DISEN_SHS_SRC_SREQ_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	498;"	d
+SBUS_DMAC_DISEN_SHS_SRC_SREQ_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	500;"	d
+SBUS_DMAC_DST_HS_BUS_SEL0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	349;"	d
+SBUS_DMAC_DST_HS_BUS_SEL0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	347;"	d
+SBUS_DMAC_DST_HS_BUS_SEL0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	346;"	d
+SBUS_DMAC_DST_HS_BUS_SEL0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	348;"	d
+SBUS_DMAC_DST_HS_BUS_SEL0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	350;"	d
+SBUS_DMAC_DST_HS_BUS_SEL1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	434;"	d
+SBUS_DMAC_DST_HS_BUS_SEL1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	432;"	d
+SBUS_DMAC_DST_HS_BUS_SEL1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	431;"	d
+SBUS_DMAC_DST_HS_BUS_SEL1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	433;"	d
+SBUS_DMAC_DST_HS_BUS_SEL1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	435;"	d
+SBUS_DMAC_DST_MSIZE0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	304;"	d
+SBUS_DMAC_DST_MSIZE0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	302;"	d
+SBUS_DMAC_DST_MSIZE0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	301;"	d
+SBUS_DMAC_DST_MSIZE0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	303;"	d
+SBUS_DMAC_DST_MSIZE0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	305;"	d
+SBUS_DMAC_DST_MSIZE1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	389;"	d
+SBUS_DMAC_DST_MSIZE1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	387;"	d
+SBUS_DMAC_DST_MSIZE1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	386;"	d
+SBUS_DMAC_DST_MSIZE1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	388;"	d
+SBUS_DMAC_DST_MSIZE1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	390;"	d
+SBUS_DMAC_DST_TR_WIDTH0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	284;"	d
+SBUS_DMAC_DST_TR_WIDTH0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	282;"	d
+SBUS_DMAC_DST_TR_WIDTH0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	281;"	d
+SBUS_DMAC_DST_TR_WIDTH0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	283;"	d
+SBUS_DMAC_DST_TR_WIDTH0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	285;"	d
+SBUS_DMAC_DST_TR_WIDTH1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	369;"	d
+SBUS_DMAC_DST_TR_WIDTH1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	367;"	d
+SBUS_DMAC_DST_TR_WIDTH1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	366;"	d
+SBUS_DMAC_DST_TR_WIDTH1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	368;"	d
+SBUS_DMAC_DST_TR_WIDTH1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	370;"	d
+SBUS_DMAC_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	509;"	d
+SBUS_DMAC_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	507;"	d
+SBUS_DMAC_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	506;"	d
+SBUS_DMAC_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	508;"	d
+SBUS_DMAC_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	510;"	d
+SBUS_DMAC_FC_MODE0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	314;"	d
+SBUS_DMAC_FC_MODE0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	312;"	d
+SBUS_DMAC_FC_MODE0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	311;"	d
+SBUS_DMAC_FC_MODE0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	313;"	d
+SBUS_DMAC_FC_MODE0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	315;"	d
+SBUS_DMAC_FC_MODE1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	399;"	d
+SBUS_DMAC_FC_MODE1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	397;"	d
+SBUS_DMAC_FC_MODE1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	396;"	d
+SBUS_DMAC_FC_MODE1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	398;"	d
+SBUS_DMAC_FC_MODE1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	400;"	d
+SBUS_DMAC_HS_SEL_DST0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	329;"	d
+SBUS_DMAC_HS_SEL_DST0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	327;"	d
+SBUS_DMAC_HS_SEL_DST0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	326;"	d
+SBUS_DMAC_HS_SEL_DST0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	328;"	d
+SBUS_DMAC_HS_SEL_DST0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	330;"	d
+SBUS_DMAC_HS_SEL_DST1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	414;"	d
+SBUS_DMAC_HS_SEL_DST1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	412;"	d
+SBUS_DMAC_HS_SEL_DST1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	411;"	d
+SBUS_DMAC_HS_SEL_DST1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	413;"	d
+SBUS_DMAC_HS_SEL_DST1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	415;"	d
+SBUS_DMAC_HS_SEL_SRC0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	334;"	d
+SBUS_DMAC_HS_SEL_SRC0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	332;"	d
+SBUS_DMAC_HS_SEL_SRC0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	331;"	d
+SBUS_DMAC_HS_SEL_SRC0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	333;"	d
+SBUS_DMAC_HS_SEL_SRC0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	335;"	d
+SBUS_DMAC_HS_SEL_SRC1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	419;"	d
+SBUS_DMAC_HS_SEL_SRC1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	417;"	d
+SBUS_DMAC_HS_SEL_SRC1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	416;"	d
+SBUS_DMAC_HS_SEL_SRC1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	418;"	d
+SBUS_DMAC_HS_SEL_SRC1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	420;"	d
+SBUS_DMAC_INTR_EN0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	279;"	d
+SBUS_DMAC_INTR_EN0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	277;"	d
+SBUS_DMAC_INTR_EN0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	276;"	d
+SBUS_DMAC_INTR_EN0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	278;"	d
+SBUS_DMAC_INTR_EN0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	280;"	d
+SBUS_DMAC_INTR_EN1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	364;"	d
+SBUS_DMAC_INTR_EN1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	362;"	d
+SBUS_DMAC_INTR_EN1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	361;"	d
+SBUS_DMAC_INTR_EN1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	363;"	d
+SBUS_DMAC_INTR_EN1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	365;"	d
+SBUS_DMAC_MAX_BURST_LEN0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	339;"	d
+SBUS_DMAC_MAX_BURST_LEN0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	337;"	d
+SBUS_DMAC_MAX_BURST_LEN0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	336;"	d
+SBUS_DMAC_MAX_BURST_LEN0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	338;"	d
+SBUS_DMAC_MAX_BURST_LEN0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	340;"	d
+SBUS_DMAC_MAX_BURST_LEN1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	424;"	d
+SBUS_DMAC_MAX_BURST_LEN1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	422;"	d
+SBUS_DMAC_MAX_BURST_LEN1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	421;"	d
+SBUS_DMAC_MAX_BURST_LEN1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	423;"	d
+SBUS_DMAC_MAX_BURST_LEN1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	425;"	d
+SBUS_DMAC_REG_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	78;"	d
+SBUS_DMAC_REG_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	17;"	d
+SBUS_DMAC_SAR0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	269;"	d
+SBUS_DMAC_SAR0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	267;"	d
+SBUS_DMAC_SAR0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	266;"	d
+SBUS_DMAC_SAR0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	268;"	d
+SBUS_DMAC_SAR0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	270;"	d
+SBUS_DMAC_SAR1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	354;"	d
+SBUS_DMAC_SAR1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	352;"	d
+SBUS_DMAC_SAR1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	351;"	d
+SBUS_DMAC_SAR1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	353;"	d
+SBUS_DMAC_SAR1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	355;"	d
+SBUS_DMAC_SINC0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	299;"	d
+SBUS_DMAC_SINC0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	297;"	d
+SBUS_DMAC_SINC0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	296;"	d
+SBUS_DMAC_SINC0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	298;"	d
+SBUS_DMAC_SINC0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	300;"	d
+SBUS_DMAC_SINC1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	384;"	d
+SBUS_DMAC_SINC1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	382;"	d
+SBUS_DMAC_SINC1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	381;"	d
+SBUS_DMAC_SINC1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	383;"	d
+SBUS_DMAC_SINC1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	385;"	d
+SBUS_DMAC_SRC_HS_BUS_SEL0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	344;"	d
+SBUS_DMAC_SRC_HS_BUS_SEL0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	342;"	d
+SBUS_DMAC_SRC_HS_BUS_SEL0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	341;"	d
+SBUS_DMAC_SRC_HS_BUS_SEL0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	343;"	d
+SBUS_DMAC_SRC_HS_BUS_SEL0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	345;"	d
+SBUS_DMAC_SRC_HS_BUS_SEL1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	429;"	d
+SBUS_DMAC_SRC_HS_BUS_SEL1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	427;"	d
+SBUS_DMAC_SRC_HS_BUS_SEL1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	426;"	d
+SBUS_DMAC_SRC_HS_BUS_SEL1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	428;"	d
+SBUS_DMAC_SRC_HS_BUS_SEL1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	430;"	d
+SBUS_DMAC_SRC_MSIZE0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	309;"	d
+SBUS_DMAC_SRC_MSIZE0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	307;"	d
+SBUS_DMAC_SRC_MSIZE0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	306;"	d
+SBUS_DMAC_SRC_MSIZE0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	308;"	d
+SBUS_DMAC_SRC_MSIZE0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	310;"	d
+SBUS_DMAC_SRC_MSIZE1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	394;"	d
+SBUS_DMAC_SRC_MSIZE1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	392;"	d
+SBUS_DMAC_SRC_MSIZE1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	391;"	d
+SBUS_DMAC_SRC_MSIZE1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	393;"	d
+SBUS_DMAC_SRC_MSIZE1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	395;"	d
+SBUS_DMAC_SRC_TR_WIDTH0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	289;"	d
+SBUS_DMAC_SRC_TR_WIDTH0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	287;"	d
+SBUS_DMAC_SRC_TR_WIDTH0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	286;"	d
+SBUS_DMAC_SRC_TR_WIDTH0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	288;"	d
+SBUS_DMAC_SRC_TR_WIDTH0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	290;"	d
+SBUS_DMAC_SRC_TR_WIDTH1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	374;"	d
+SBUS_DMAC_SRC_TR_WIDTH1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	372;"	d
+SBUS_DMAC_SRC_TR_WIDTH1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	371;"	d
+SBUS_DMAC_SRC_TR_WIDTH1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	373;"	d
+SBUS_DMAC_SRC_TR_WIDTH1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	375;"	d
+SCL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3114;"	d
+SCL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3112;"	d
+SCL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3111;"	d
+SCL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3113;"	d
+SCL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3115;"	d
+SCOREBOAD_SIZE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6479;"	d
+SCOREBOAD_SIZE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6477;"	d
+SCOREBOAD_SIZE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6476;"	d
+SCOREBOAD_SIZE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6478;"	d
+SCOREBOAD_SIZE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6480;"	d
+SCRT_CCMP_CERR_HI	include/ssv6200_aux.h	9689;"	d
+SCRT_CCMP_CERR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9524;"	d
+SCRT_CCMP_CERR_I_MSK	include/ssv6200_aux.h	9687;"	d
+SCRT_CCMP_CERR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9522;"	d
+SCRT_CCMP_CERR_MSK	include/ssv6200_aux.h	9686;"	d
+SCRT_CCMP_CERR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9521;"	d
+SCRT_CCMP_CERR_SFT	include/ssv6200_aux.h	9688;"	d
+SCRT_CCMP_CERR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9523;"	d
+SCRT_CCMP_CERR_SZ	include/ssv6200_aux.h	9690;"	d
+SCRT_CCMP_CERR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9525;"	d
+SCRT_CCMP_RPLY_HI	include/ssv6200_aux.h	9684;"	d
+SCRT_CCMP_RPLY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9519;"	d
+SCRT_CCMP_RPLY_I_MSK	include/ssv6200_aux.h	9682;"	d
+SCRT_CCMP_RPLY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9517;"	d
+SCRT_CCMP_RPLY_MSK	include/ssv6200_aux.h	9681;"	d
+SCRT_CCMP_RPLY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9516;"	d
+SCRT_CCMP_RPLY_SFT	include/ssv6200_aux.h	9683;"	d
+SCRT_CCMP_RPLY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9518;"	d
+SCRT_CCMP_RPLY_SZ	include/ssv6200_aux.h	9685;"	d
+SCRT_CCMP_RPLY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9520;"	d
+SCRT_CLK_EN_HI	include/ssv6200_aux.h	9029;"	d
+SCRT_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8784;"	d
+SCRT_CLK_EN_I_MSK	include/ssv6200_aux.h	9027;"	d
+SCRT_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8782;"	d
+SCRT_CLK_EN_MSK	include/ssv6200_aux.h	9026;"	d
+SCRT_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8781;"	d
+SCRT_CLK_EN_SFT	include/ssv6200_aux.h	9028;"	d
+SCRT_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8783;"	d
+SCRT_CLK_EN_SZ	include/ssv6200_aux.h	9030;"	d
+SCRT_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8785;"	d
+SCRT_CSR_CLK_EN_HI	include/ssv6200_aux.h	9109;"	d
+SCRT_CSR_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8864;"	d
+SCRT_CSR_CLK_EN_I_MSK	include/ssv6200_aux.h	9107;"	d
+SCRT_CSR_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8862;"	d
+SCRT_CSR_CLK_EN_MSK	include/ssv6200_aux.h	9106;"	d
+SCRT_CSR_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8861;"	d
+SCRT_CSR_CLK_EN_SFT	include/ssv6200_aux.h	9108;"	d
+SCRT_CSR_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8863;"	d
+SCRT_CSR_CLK_EN_SZ	include/ssv6200_aux.h	9110;"	d
+SCRT_CSR_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8865;"	d
+SCRT_CSR_RST_HI	include/ssv6200_aux.h	8969;"	d
+SCRT_CSR_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8724;"	d
+SCRT_CSR_RST_I_MSK	include/ssv6200_aux.h	8967;"	d
+SCRT_CSR_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8722;"	d
+SCRT_CSR_RST_MSK	include/ssv6200_aux.h	8966;"	d
+SCRT_CSR_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8721;"	d
+SCRT_CSR_RST_SFT	include/ssv6200_aux.h	8968;"	d
+SCRT_CSR_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8723;"	d
+SCRT_CSR_RST_SZ	include/ssv6200_aux.h	8970;"	d
+SCRT_CSR_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8725;"	d
+SCRT_ENG_CLK_EN_HI	include/ssv6200_aux.h	9084;"	d
+SCRT_ENG_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8839;"	d
+SCRT_ENG_CLK_EN_I_MSK	include/ssv6200_aux.h	9082;"	d
+SCRT_ENG_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8837;"	d
+SCRT_ENG_CLK_EN_MSK	include/ssv6200_aux.h	9081;"	d
+SCRT_ENG_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8836;"	d
+SCRT_ENG_CLK_EN_SFT	include/ssv6200_aux.h	9083;"	d
+SCRT_ENG_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8838;"	d
+SCRT_ENG_CLK_EN_SZ	include/ssv6200_aux.h	9085;"	d
+SCRT_ENG_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8840;"	d
+SCRT_ENG_RST_HI	include/ssv6200_aux.h	8909;"	d
+SCRT_ENG_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8664;"	d
+SCRT_ENG_RST_I_MSK	include/ssv6200_aux.h	8907;"	d
+SCRT_ENG_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8662;"	d
+SCRT_ENG_RST_MSK	include/ssv6200_aux.h	8906;"	d
+SCRT_ENG_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8661;"	d
+SCRT_ENG_RST_SFT	include/ssv6200_aux.h	8908;"	d
+SCRT_ENG_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8663;"	d
+SCRT_ENG_RST_SZ	include/ssv6200_aux.h	8910;"	d
+SCRT_ENG_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8665;"	d
+SCRT_INT_1_HI	include/ssv6200_aux.h	4944;"	d
+SCRT_INT_1_I_MSK	include/ssv6200_aux.h	4942;"	d
+SCRT_INT_1_MSK	include/ssv6200_aux.h	4941;"	d
+SCRT_INT_1_SD_HI	include/ssv6200_aux.h	5289;"	d
+SCRT_INT_1_SD_I_MSK	include/ssv6200_aux.h	5287;"	d
+SCRT_INT_1_SD_MSK	include/ssv6200_aux.h	5286;"	d
+SCRT_INT_1_SD_SFT	include/ssv6200_aux.h	5288;"	d
+SCRT_INT_1_SD_SZ	include/ssv6200_aux.h	5290;"	d
+SCRT_INT_1_SFT	include/ssv6200_aux.h	4943;"	d
+SCRT_INT_1_SZ	include/ssv6200_aux.h	4945;"	d
+SCRT_PKT_CLS_MIB_EN_HI	include/ssv6200_aux.h	9404;"	d
+SCRT_PKT_CLS_MIB_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9239;"	d
+SCRT_PKT_CLS_MIB_EN_I_MSK	include/ssv6200_aux.h	9402;"	d
+SCRT_PKT_CLS_MIB_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9237;"	d
+SCRT_PKT_CLS_MIB_EN_MSK	include/ssv6200_aux.h	9401;"	d
+SCRT_PKT_CLS_MIB_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9236;"	d
+SCRT_PKT_CLS_MIB_EN_SFT	include/ssv6200_aux.h	9403;"	d
+SCRT_PKT_CLS_MIB_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9238;"	d
+SCRT_PKT_CLS_MIB_EN_SZ	include/ssv6200_aux.h	9405;"	d
+SCRT_PKT_CLS_MIB_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9240;"	d
+SCRT_PKT_CLS_ONGOING_HI	include/ssv6200_aux.h	9409;"	d
+SCRT_PKT_CLS_ONGOING_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9244;"	d
+SCRT_PKT_CLS_ONGOING_I_MSK	include/ssv6200_aux.h	9407;"	d
+SCRT_PKT_CLS_ONGOING_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9242;"	d
+SCRT_PKT_CLS_ONGOING_MSK	include/ssv6200_aux.h	9406;"	d
+SCRT_PKT_CLS_ONGOING_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9241;"	d
+SCRT_PKT_CLS_ONGOING_SFT	include/ssv6200_aux.h	9408;"	d
+SCRT_PKT_CLS_ONGOING_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9243;"	d
+SCRT_PKT_CLS_ONGOING_SZ	include/ssv6200_aux.h	9410;"	d
+SCRT_PKT_CLS_ONGOING_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9245;"	d
+SCRT_PKT_ID_HI	include/ssv6200_aux.h	9209;"	d
+SCRT_PKT_ID_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8969;"	d
+SCRT_PKT_ID_I_MSK	include/ssv6200_aux.h	9207;"	d
+SCRT_PKT_ID_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8967;"	d
+SCRT_PKT_ID_MSK	include/ssv6200_aux.h	9206;"	d
+SCRT_PKT_ID_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8966;"	d
+SCRT_PKT_ID_SFT	include/ssv6200_aux.h	9208;"	d
+SCRT_PKT_ID_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8968;"	d
+SCRT_PKT_ID_SZ	include/ssv6200_aux.h	9210;"	d
+SCRT_PKT_ID_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8970;"	d
+SCRT_RPLY_IGNORE_HI	include/ssv6200_aux.h	9214;"	d
+SCRT_RPLY_IGNORE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8974;"	d
+SCRT_RPLY_IGNORE_I_MSK	include/ssv6200_aux.h	9212;"	d
+SCRT_RPLY_IGNORE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8972;"	d
+SCRT_RPLY_IGNORE_MSK	include/ssv6200_aux.h	9211;"	d
+SCRT_RPLY_IGNORE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8971;"	d
+SCRT_RPLY_IGNORE_SFT	include/ssv6200_aux.h	9213;"	d
+SCRT_RPLY_IGNORE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8973;"	d
+SCRT_RPLY_IGNORE_SZ	include/ssv6200_aux.h	9215;"	d
+SCRT_RPLY_IGNORE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8975;"	d
+SCRT_STATE_HI	include/ssv6200_aux.h	9184;"	d
+SCRT_STATE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8979;"	d
+SCRT_STATE_I_MSK	include/ssv6200_aux.h	9182;"	d
+SCRT_STATE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8977;"	d
+SCRT_STATE_MSK	include/ssv6200_aux.h	9181;"	d
+SCRT_STATE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8976;"	d
+SCRT_STATE_SFT	include/ssv6200_aux.h	9183;"	d
+SCRT_STATE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8978;"	d
+SCRT_STATE_SZ	include/ssv6200_aux.h	9185;"	d
+SCRT_STATE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8980;"	d
+SCRT_SW_RST_HI	include/ssv6200_aux.h	8854;"	d
+SCRT_SW_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8609;"	d
+SCRT_SW_RST_I_MSK	include/ssv6200_aux.h	8852;"	d
+SCRT_SW_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8607;"	d
+SCRT_SW_RST_MSK	include/ssv6200_aux.h	8851;"	d
+SCRT_SW_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8606;"	d
+SCRT_SW_RST_SFT	include/ssv6200_aux.h	8853;"	d
+SCRT_SW_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8608;"	d
+SCRT_SW_RST_SZ	include/ssv6200_aux.h	8855;"	d
+SCRT_SW_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8610;"	d
+SCRT_TKIP_CERR_HI	include/ssv6200_aux.h	9669;"	d
+SCRT_TKIP_CERR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9504;"	d
+SCRT_TKIP_CERR_I_MSK	include/ssv6200_aux.h	9667;"	d
+SCRT_TKIP_CERR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9502;"	d
+SCRT_TKIP_CERR_MSK	include/ssv6200_aux.h	9666;"	d
+SCRT_TKIP_CERR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9501;"	d
+SCRT_TKIP_CERR_SFT	include/ssv6200_aux.h	9668;"	d
+SCRT_TKIP_CERR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9503;"	d
+SCRT_TKIP_CERR_SZ	include/ssv6200_aux.h	9670;"	d
+SCRT_TKIP_CERR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9505;"	d
+SCRT_TKIP_MIC_ERR_HI	include/ssv6200_aux.h	9674;"	d
+SCRT_TKIP_MIC_ERR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9509;"	d
+SCRT_TKIP_MIC_ERR_I_MSK	include/ssv6200_aux.h	9672;"	d
+SCRT_TKIP_MIC_ERR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9507;"	d
+SCRT_TKIP_MIC_ERR_MSK	include/ssv6200_aux.h	9671;"	d
+SCRT_TKIP_MIC_ERR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9506;"	d
+SCRT_TKIP_MIC_ERR_SFT	include/ssv6200_aux.h	9673;"	d
+SCRT_TKIP_MIC_ERR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9508;"	d
+SCRT_TKIP_MIC_ERR_SZ	include/ssv6200_aux.h	9675;"	d
+SCRT_TKIP_MIC_ERR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9510;"	d
+SCRT_TKIP_RPLY_HI	include/ssv6200_aux.h	9679;"	d
+SCRT_TKIP_RPLY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9514;"	d
+SCRT_TKIP_RPLY_I_MSK	include/ssv6200_aux.h	9677;"	d
+SCRT_TKIP_RPLY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9512;"	d
+SCRT_TKIP_RPLY_MSK	include/ssv6200_aux.h	9676;"	d
+SCRT_TKIP_RPLY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9511;"	d
+SCRT_TKIP_RPLY_SFT	include/ssv6200_aux.h	9678;"	d
+SCRT_TKIP_RPLY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9513;"	d
+SCRT_TKIP_RPLY_SZ	include/ssv6200_aux.h	9680;"	d
+SCRT_TKIP_RPLY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9515;"	d
+SC_OP_BLOCK_CNTL	smac/dev.h	794;"	d
+SC_OP_CHAN_FIXED	smac/dev.h	795;"	d
+SC_OP_CTS_PROT	smac/dev.h	792;"	d
+SC_OP_DEV_READY	smac/dev.h	787;"	d
+SC_OP_DIRECTLY_ACK	smac/dev.h	793;"	d
+SC_OP_FIXED_RATE	smac/dev.h	790;"	d
+SC_OP_HW_RESET	smac/dev.h	788;"	d
+SC_OP_OFFCHAN	smac/dev.h	789;"	d
+SC_OP_SHORT_PREAMBLE	smac/dev.h	791;"	d
+SDA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3119;"	d
+SDA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3117;"	d
+SDA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3116;"	d
+SDA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3118;"	d
+SDA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3120;"	d
+SDIO_ALL_RESET_HI	include/ssv6200_aux.h	3399;"	d
+SDIO_ALL_RESET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2744;"	d
+SDIO_ALL_RESET_I_MSK	include/ssv6200_aux.h	3397;"	d
+SDIO_ALL_RESET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2742;"	d
+SDIO_ALL_RESET_MSK	include/ssv6200_aux.h	3396;"	d
+SDIO_ALL_RESET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2741;"	d
+SDIO_ALL_RESET_SFT	include/ssv6200_aux.h	3398;"	d
+SDIO_ALL_RESET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2743;"	d
+SDIO_ALL_RESET_SZ	include/ssv6200_aux.h	3400;"	d
+SDIO_ALL_RESET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2745;"	d
+SDIO_ALL_RESE_ACTIVE_HI	include/ssv6200_aux.h	3209;"	d
+SDIO_ALL_RESE_ACTIVE_I_MSK	include/ssv6200_aux.h	3207;"	d
+SDIO_ALL_RESE_ACTIVE_MSK	include/ssv6200_aux.h	3206;"	d
+SDIO_ALL_RESE_ACTIVE_SFT	include/ssv6200_aux.h	3208;"	d
+SDIO_ALL_RESE_ACTIVE_SZ	include/ssv6200_aux.h	3210;"	d
+SDIO_BUSY_LONG_CNT_HI	include/ssv6200_aux.h	3329;"	d
+SDIO_BUSY_LONG_CNT_I_MSK	include/ssv6200_aux.h	3327;"	d
+SDIO_BUSY_LONG_CNT_MSK	include/ssv6200_aux.h	3326;"	d
+SDIO_BUSY_LONG_CNT_SFT	include/ssv6200_aux.h	3328;"	d
+SDIO_BUSY_LONG_CNT_SZ	include/ssv6200_aux.h	3330;"	d
+SDIO_BUS_STATE_REG_HI	include/ssv6200_aux.h	3324;"	d
+SDIO_BUS_STATE_REG_I_MSK	include/ssv6200_aux.h	3322;"	d
+SDIO_BUS_STATE_REG_MSK	include/ssv6200_aux.h	3321;"	d
+SDIO_BUS_STATE_REG_SFT	include/ssv6200_aux.h	3323;"	d
+SDIO_BUS_STATE_REG_SZ	include/ssv6200_aux.h	3325;"	d
+SDIO_BYTE_MODE_BATCH_SIZE_REG_HI	include/ssv6200_aux.h	3304;"	d
+SDIO_BYTE_MODE_BATCH_SIZE_REG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2649;"	d
+SDIO_BYTE_MODE_BATCH_SIZE_REG_I_MSK	include/ssv6200_aux.h	3302;"	d
+SDIO_BYTE_MODE_BATCH_SIZE_REG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2647;"	d
+SDIO_BYTE_MODE_BATCH_SIZE_REG_MSK	include/ssv6200_aux.h	3301;"	d
+SDIO_BYTE_MODE_BATCH_SIZE_REG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2646;"	d
+SDIO_BYTE_MODE_BATCH_SIZE_REG_SFT	include/ssv6200_aux.h	3303;"	d
+SDIO_BYTE_MODE_BATCH_SIZE_REG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2648;"	d
+SDIO_BYTE_MODE_BATCH_SIZE_REG_SZ	include/ssv6200_aux.h	3305;"	d
+SDIO_BYTE_MODE_BATCH_SIZE_REG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2650;"	d
+SDIO_CARD_STATUS_REG_HI	include/ssv6200_aux.h	3334;"	d
+SDIO_CARD_STATUS_REG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2654;"	d
+SDIO_CARD_STATUS_REG_I_MSK	include/ssv6200_aux.h	3332;"	d
+SDIO_CARD_STATUS_REG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2652;"	d
+SDIO_CARD_STATUS_REG_MSK	include/ssv6200_aux.h	3331;"	d
+SDIO_CARD_STATUS_REG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2651;"	d
+SDIO_CARD_STATUS_REG_SFT	include/ssv6200_aux.h	3333;"	d
+SDIO_CARD_STATUS_REG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2653;"	d
+SDIO_CARD_STATUS_REG_SZ	include/ssv6200_aux.h	3335;"	d
+SDIO_CARD_STATUS_REG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2655;"	d
+SDIO_CLK_EN_HI	include/ssv6200_aux.h	204;"	d
+SDIO_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1154;"	d
+SDIO_CLK_EN_I_MSK	include/ssv6200_aux.h	202;"	d
+SDIO_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1152;"	d
+SDIO_CLK_EN_MSK	include/ssv6200_aux.h	201;"	d
+SDIO_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1151;"	d
+SDIO_CLK_EN_SFT	include/ssv6200_aux.h	203;"	d
+SDIO_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1153;"	d
+SDIO_CLK_EN_SZ	include/ssv6200_aux.h	205;"	d
+SDIO_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1155;"	d
+SDIO_CMD52_06H_RESET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1684;"	d
+SDIO_CMD52_06H_RESET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1682;"	d
+SDIO_CMD52_06H_RESET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1681;"	d
+SDIO_CMD52_06H_RESET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1683;"	d
+SDIO_CMD52_06H_RESET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1685;"	d
+SDIO_COMMAND_BUFFER_LEN	hwif/sdio/sdio_def.h	98;"	d
+SDIO_CRC16_ERROR_CNT_HI	include/ssv6200_aux.h	3439;"	d
+SDIO_CRC16_ERROR_CNT_I_MSK	include/ssv6200_aux.h	3437;"	d
+SDIO_CRC16_ERROR_CNT_MSK	include/ssv6200_aux.h	3436;"	d
+SDIO_CRC16_ERROR_CNT_SFT	include/ssv6200_aux.h	3438;"	d
+SDIO_CRC16_ERROR_CNT_SZ	include/ssv6200_aux.h	3440;"	d
+SDIO_CRC7_ERROR_CNT_HI	include/ssv6200_aux.h	3434;"	d
+SDIO_CRC7_ERROR_CNT_I_MSK	include/ssv6200_aux.h	3432;"	d
+SDIO_CRC7_ERROR_CNT_MSK	include/ssv6200_aux.h	3431;"	d
+SDIO_CRC7_ERROR_CNT_SFT	include/ssv6200_aux.h	3433;"	d
+SDIO_CRC7_ERROR_CNT_SZ	include/ssv6200_aux.h	3435;"	d
+SDIO_DEF_BLOCK_MODE_THRD	hwif/sdio/sdio_def.h	70;"	d
+SDIO_DEF_BLOCK_SIZE	hwif/sdio/sdio_def.h	65;"	d
+SDIO_DEF_FORCE_BLOCK_MODE	hwif/sdio/sdio_def.h	74;"	d
+SDIO_DEF_OUTPUT_TIMING	hwif/sdio/sdio_def.h	69;"	d
+SDIO_DELAY_LEVEL_0	hwif/sdio/sdio_def.h	113;"	d
+SDIO_DELAY_LEVEL_1	hwif/sdio/sdio_def.h	114;"	d
+SDIO_DELAY_LEVEL_2	hwif/sdio/sdio_def.h	115;"	d
+SDIO_DELAY_LEVEL_3	hwif/sdio/sdio_def.h	116;"	d
+SDIO_DELAY_LEVEL_OFF	hwif/sdio/sdio_def.h	112;"	d
+SDIO_DMA_BUFFER_LEN	hwif/sdio/sdio_def.h	95;"	d
+SDIO_FIFO_EMPTY_CNT_HI	include/ssv6200_aux.h	3424;"	d
+SDIO_FIFO_EMPTY_CNT_I_MSK	include/ssv6200_aux.h	3422;"	d
+SDIO_FIFO_EMPTY_CNT_MSK	include/ssv6200_aux.h	3421;"	d
+SDIO_FIFO_EMPTY_CNT_SFT	include/ssv6200_aux.h	3423;"	d
+SDIO_FIFO_EMPTY_CNT_SZ	include/ssv6200_aux.h	3425;"	d
+SDIO_FIFO_FULL_CNT_HI	include/ssv6200_aux.h	3429;"	d
+SDIO_FIFO_FULL_CNT_I_MSK	include/ssv6200_aux.h	3427;"	d
+SDIO_FIFO_FULL_CNT_MSK	include/ssv6200_aux.h	3426;"	d
+SDIO_FIFO_FULL_CNT_SFT	include/ssv6200_aux.h	3428;"	d
+SDIO_FIFO_FULL_CNT_SZ	include/ssv6200_aux.h	3430;"	d
+SDIO_FIFO_RD_PTR_REG_HI	include/ssv6200_aux.h	3469;"	d
+SDIO_FIFO_RD_PTR_REG_I_MSK	include/ssv6200_aux.h	3467;"	d
+SDIO_FIFO_RD_PTR_REG_MSK	include/ssv6200_aux.h	3466;"	d
+SDIO_FIFO_RD_PTR_REG_SFT	include/ssv6200_aux.h	3468;"	d
+SDIO_FIFO_RD_PTR_REG_SZ	include/ssv6200_aux.h	3470;"	d
+SDIO_FIFO_WR_LIMIT_REG_HI	include/ssv6200_aux.h	3274;"	d
+SDIO_FIFO_WR_LIMIT_REG_I_MSK	include/ssv6200_aux.h	3272;"	d
+SDIO_FIFO_WR_LIMIT_REG_MSK	include/ssv6200_aux.h	3271;"	d
+SDIO_FIFO_WR_LIMIT_REG_SFT	include/ssv6200_aux.h	3273;"	d
+SDIO_FIFO_WR_LIMIT_REG_SZ	include/ssv6200_aux.h	3275;"	d
+SDIO_FIFO_WR_PTR_REG_HI	include/ssv6200_aux.h	3464;"	d
+SDIO_FIFO_WR_PTR_REG_I_MSK	include/ssv6200_aux.h	3462;"	d
+SDIO_FIFO_WR_PTR_REG_MSK	include/ssv6200_aux.h	3461;"	d
+SDIO_FIFO_WR_PTR_REG_SFT	include/ssv6200_aux.h	3463;"	d
+SDIO_FIFO_WR_PTR_REG_SZ	include/ssv6200_aux.h	3465;"	d
+SDIO_FIFO_WR_THLD_REG_HI	include/ssv6200_aux.h	3269;"	d
+SDIO_FIFO_WR_THLD_REG_I_MSK	include/ssv6200_aux.h	3267;"	d
+SDIO_FIFO_WR_THLD_REG_MSK	include/ssv6200_aux.h	3266;"	d
+SDIO_FIFO_WR_THLD_REG_SFT	include/ssv6200_aux.h	3268;"	d
+SDIO_FIFO_WR_THLD_REG_SZ	include/ssv6200_aux.h	3270;"	d
+SDIO_ID	platforms/a33-generic-wlan.c	62;"	d	file:
+SDIO_ID	platforms/h3-generic-wlan.c	53;"	d	file:
+SDIO_ID	platforms/h8-generic-wlan.c	53;"	d	file:
+SDIO_ID	platforms/t10-generic-wlan.c	52;"	d	file:
+SDIO_ID	platforms/x1000-generic-wlan.c	52;"	d	file:
+SDIO_INPUT_DELAY_LEVEL_MSK	hwif/sdio/sdio_def.h	106;"	d
+SDIO_INPUT_DELAY_LEVEL_SFT	hwif/sdio/sdio_def.h	107;"	d
+SDIO_INPUT_DELAY_MSK	hwif/sdio/sdio_def.h	104;"	d
+SDIO_INPUT_DELAY_SFT	hwif/sdio/sdio_def.h	105;"	d
+SDIO_LAST_CMD_ARG_REG_HI	include/ssv6200_aux.h	3319;"	d
+SDIO_LAST_CMD_ARG_REG_I_MSK	include/ssv6200_aux.h	3317;"	d
+SDIO_LAST_CMD_ARG_REG_MSK	include/ssv6200_aux.h	3316;"	d
+SDIO_LAST_CMD_ARG_REG_SFT	include/ssv6200_aux.h	3318;"	d
+SDIO_LAST_CMD_ARG_REG_SZ	include/ssv6200_aux.h	3320;"	d
+SDIO_LAST_CMD_CRC_REG_HI	include/ssv6200_aux.h	3314;"	d
+SDIO_LAST_CMD_CRC_REG_I_MSK	include/ssv6200_aux.h	3312;"	d
+SDIO_LAST_CMD_CRC_REG_MSK	include/ssv6200_aux.h	3311;"	d
+SDIO_LAST_CMD_CRC_REG_SFT	include/ssv6200_aux.h	3313;"	d
+SDIO_LAST_CMD_CRC_REG_SZ	include/ssv6200_aux.h	3315;"	d
+SDIO_LAST_CMD_INDEX_REG_HI	include/ssv6200_aux.h	3309;"	d
+SDIO_LAST_CMD_INDEX_REG_I_MSK	include/ssv6200_aux.h	3307;"	d
+SDIO_LAST_CMD_INDEX_REG_MSK	include/ssv6200_aux.h	3306;"	d
+SDIO_LAST_CMD_INDEX_REG_SFT	include/ssv6200_aux.h	3308;"	d
+SDIO_LAST_CMD_INDEX_REG_SZ	include/ssv6200_aux.h	3310;"	d
+SDIO_LOOP_BACK_TEST_HI	include/ssv6200_aux.h	3189;"	d
+SDIO_LOOP_BACK_TEST_I_MSK	include/ssv6200_aux.h	3187;"	d
+SDIO_LOOP_BACK_TEST_MSK	include/ssv6200_aux.h	3186;"	d
+SDIO_LOOP_BACK_TEST_SFT	include/ssv6200_aux.h	3188;"	d
+SDIO_LOOP_BACK_TEST_SZ	include/ssv6200_aux.h	3190;"	d
+SDIO_OUTPUT_DELAY_LEVEL_MSK	hwif/sdio/sdio_def.h	110;"	d
+SDIO_OUTPUT_DELAY_LEVEL_SFT	hwif/sdio/sdio_def.h	111;"	d
+SDIO_OUTPUT_DELAY_MSK	hwif/sdio/sdio_def.h	108;"	d
+SDIO_OUTPUT_DELAY_SFT	hwif/sdio/sdio_def.h	109;"	d
+SDIO_PARTIAL_RESET_ACTIVE_HI	include/ssv6200_aux.h	3204;"	d
+SDIO_PARTIAL_RESET_ACTIVE_I_MSK	include/ssv6200_aux.h	3202;"	d
+SDIO_PARTIAL_RESET_ACTIVE_MSK	include/ssv6200_aux.h	3201;"	d
+SDIO_PARTIAL_RESET_ACTIVE_SFT	include/ssv6200_aux.h	3203;"	d
+SDIO_PARTIAL_RESET_ACTIVE_SZ	include/ssv6200_aux.h	3205;"	d
+SDIO_PARTIAL_RESET_HI	include/ssv6200_aux.h	3394;"	d
+SDIO_PARTIAL_RESET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2739;"	d
+SDIO_PARTIAL_RESET_I_MSK	include/ssv6200_aux.h	3392;"	d
+SDIO_PARTIAL_RESET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2737;"	d
+SDIO_PARTIAL_RESET_MSK	include/ssv6200_aux.h	3391;"	d
+SDIO_PARTIAL_RESET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2736;"	d
+SDIO_PARTIAL_RESET_SFT	include/ssv6200_aux.h	3393;"	d
+SDIO_PARTIAL_RESET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2738;"	d
+SDIO_PARTIAL_RESET_SZ	include/ssv6200_aux.h	3395;"	d
+SDIO_PARTIAL_RESET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2740;"	d
+SDIO_RD_BLOCK_CNT_HI	include/ssv6200_aux.h	3444;"	d
+SDIO_RD_BLOCK_CNT_I_MSK	include/ssv6200_aux.h	3442;"	d
+SDIO_RD_BLOCK_CNT_MSK	include/ssv6200_aux.h	3441;"	d
+SDIO_RD_BLOCK_CNT_SFT	include/ssv6200_aux.h	3443;"	d
+SDIO_RD_BLOCK_CNT_SZ	include/ssv6200_aux.h	3445;"	d
+SDIO_READ	hwif/sdio/sdio_def.h	87;"	d
+SDIO_READY_FLAG_BUSY	hwif/sdio/sdio_def.h	117;"	d
+SDIO_READY_FLAG_BUSY_DELAY	hwif/sdio/sdio_def.h	120;"	d
+SDIO_READY_FLAG_BUSY_THRESHOLD	hwif/sdio/sdio_def.h	119;"	d
+SDIO_READY_FLAG_IDLE	hwif/sdio/sdio_def.h	118;"	d
+SDIO_READ_DATA_CTRL_HI	include/ssv6200_aux.h	3474;"	d
+SDIO_READ_DATA_CTRL_I_MSK	include/ssv6200_aux.h	3472;"	d
+SDIO_READ_DATA_CTRL_MSK	include/ssv6200_aux.h	3471;"	d
+SDIO_READ_DATA_CTRL_SFT	include/ssv6200_aux.h	3473;"	d
+SDIO_READ_DATA_CTRL_SZ	include/ssv6200_aux.h	3475;"	d
+SDIO_RX_DATA_BATCH_SIZE_REG_HI	include/ssv6200_aux.h	3289;"	d
+SDIO_RX_DATA_BATCH_SIZE_REG_I_MSK	include/ssv6200_aux.h	3287;"	d
+SDIO_RX_DATA_BATCH_SIZE_REG_MSK	include/ssv6200_aux.h	3286;"	d
+SDIO_RX_DATA_BATCH_SIZE_REG_SFT	include/ssv6200_aux.h	3288;"	d
+SDIO_RX_DATA_BATCH_SIZE_REG_SZ	include/ssv6200_aux.h	3290;"	d
+SDIO_SW_RST_HI	include/ssv6200_aux.h	34;"	d
+SDIO_SW_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	989;"	d
+SDIO_SW_RST_I_MSK	include/ssv6200_aux.h	32;"	d
+SDIO_SW_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	987;"	d
+SDIO_SW_RST_MSK	include/ssv6200_aux.h	31;"	d
+SDIO_SW_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	986;"	d
+SDIO_SW_RST_SFT	include/ssv6200_aux.h	33;"	d
+SDIO_SW_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	988;"	d
+SDIO_SW_RST_SZ	include/ssv6200_aux.h	35;"	d
+SDIO_SW_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	990;"	d
+SDIO_SYS_INT_HI	include/ssv6200_aux.h	4119;"	d
+SDIO_SYS_INT_I_MSK	include/ssv6200_aux.h	4117;"	d
+SDIO_SYS_INT_MSK	include/ssv6200_aux.h	4116;"	d
+SDIO_SYS_INT_SFT	include/ssv6200_aux.h	4118;"	d
+SDIO_SYS_INT_SZ	include/ssv6200_aux.h	4120;"	d
+SDIO_THLD_FOR_CMD53RD_REG_HI	include/ssv6200_aux.h	3284;"	d
+SDIO_THLD_FOR_CMD53RD_REG_I_MSK	include/ssv6200_aux.h	3282;"	d
+SDIO_THLD_FOR_CMD53RD_REG_MSK	include/ssv6200_aux.h	3281;"	d
+SDIO_THLD_FOR_CMD53RD_REG_SFT	include/ssv6200_aux.h	3283;"	d
+SDIO_THLD_FOR_CMD53RD_REG_SZ	include/ssv6200_aux.h	3285;"	d
+SDIO_TO_MCU_INFO_HI	include/ssv6200_aux.h	3389;"	d
+SDIO_TO_MCU_INFO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2734;"	d
+SDIO_TO_MCU_INFO_I_MSK	include/ssv6200_aux.h	3387;"	d
+SDIO_TO_MCU_INFO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2732;"	d
+SDIO_TO_MCU_INFO_MSK	include/ssv6200_aux.h	3386;"	d
+SDIO_TO_MCU_INFO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2731;"	d
+SDIO_TO_MCU_INFO_SFT	include/ssv6200_aux.h	3388;"	d
+SDIO_TO_MCU_INFO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2733;"	d
+SDIO_TO_MCU_INFO_SZ	include/ssv6200_aux.h	3390;"	d
+SDIO_TO_MCU_INFO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2735;"	d
+SDIO_TRANS_CNT_HI	include/ssv6200_aux.h	6319;"	d
+SDIO_TRANS_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5439;"	d
+SDIO_TRANS_CNT_I_MSK	include/ssv6200_aux.h	6317;"	d
+SDIO_TRANS_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5437;"	d
+SDIO_TRANS_CNT_MSK	include/ssv6200_aux.h	6316;"	d
+SDIO_TRANS_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5436;"	d
+SDIO_TRANS_CNT_SFT	include/ssv6200_aux.h	6318;"	d
+SDIO_TRANS_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5438;"	d
+SDIO_TRANS_CNT_SZ	include/ssv6200_aux.h	6320;"	d
+SDIO_TRANS_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5440;"	d
+SDIO_TRX_DATA_SEQUENCE_HI	include/ssv6200_aux.h	3154;"	d
+SDIO_TRX_DATA_SEQUENCE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2624;"	d
+SDIO_TRX_DATA_SEQUENCE_I_MSK	include/ssv6200_aux.h	3152;"	d
+SDIO_TRX_DATA_SEQUENCE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2622;"	d
+SDIO_TRX_DATA_SEQUENCE_MSK	include/ssv6200_aux.h	3151;"	d
+SDIO_TRX_DATA_SEQUENCE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2621;"	d
+SDIO_TRX_DATA_SEQUENCE_SFT	include/ssv6200_aux.h	3153;"	d
+SDIO_TRX_DATA_SEQUENCE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2623;"	d
+SDIO_TRX_DATA_SEQUENCE_SZ	include/ssv6200_aux.h	3155;"	d
+SDIO_TRX_DATA_SEQUENCE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2625;"	d
+SDIO_TX_ALLOC_STATE_HI	include/ssv6200_aux.h	3489;"	d
+SDIO_TX_ALLOC_STATE_I_MSK	include/ssv6200_aux.h	3487;"	d
+SDIO_TX_ALLOC_STATE_MSK	include/ssv6200_aux.h	3486;"	d
+SDIO_TX_ALLOC_STATE_SFT	include/ssv6200_aux.h	3488;"	d
+SDIO_TX_ALLOC_STATE_SZ	include/ssv6200_aux.h	3490;"	d
+SDIO_TX_DATA_BATCH_SIZE_REG_HI	include/ssv6200_aux.h	3279;"	d
+SDIO_TX_DATA_BATCH_SIZE_REG_I_MSK	include/ssv6200_aux.h	3277;"	d
+SDIO_TX_DATA_BATCH_SIZE_REG_MSK	include/ssv6200_aux.h	3276;"	d
+SDIO_TX_DATA_BATCH_SIZE_REG_SFT	include/ssv6200_aux.h	3278;"	d
+SDIO_TX_DATA_BATCH_SIZE_REG_SZ	include/ssv6200_aux.h	3280;"	d
+SDIO_TX_INVALID_CNT_31_0_HI	include/ssv6200_aux.h	6324;"	d
+SDIO_TX_INVALID_CNT_31_0_I_MSK	include/ssv6200_aux.h	6322;"	d
+SDIO_TX_INVALID_CNT_31_0_MSK	include/ssv6200_aux.h	6321;"	d
+SDIO_TX_INVALID_CNT_31_0_SFT	include/ssv6200_aux.h	6323;"	d
+SDIO_TX_INVALID_CNT_31_0_SZ	include/ssv6200_aux.h	6325;"	d
+SDIO_TX_INVALID_CNT_47_32_HI	include/ssv6200_aux.h	6329;"	d
+SDIO_TX_INVALID_CNT_47_32_I_MSK	include/ssv6200_aux.h	6327;"	d
+SDIO_TX_INVALID_CNT_47_32_MSK	include/ssv6200_aux.h	6326;"	d
+SDIO_TX_INVALID_CNT_47_32_SFT	include/ssv6200_aux.h	6328;"	d
+SDIO_TX_INVALID_CNT_47_32_SZ	include/ssv6200_aux.h	6330;"	d
+SDIO_TX_INVALID_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5424;"	d
+SDIO_TX_INVALID_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5422;"	d
+SDIO_TX_INVALID_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5421;"	d
+SDIO_TX_INVALID_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5423;"	d
+SDIO_TX_INVALID_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5425;"	d
+SDIO_WRITE	hwif/sdio/sdio_def.h	88;"	d
+SDIO_WR_BLOCK_CNT_HI	include/ssv6200_aux.h	3449;"	d
+SDIO_WR_BLOCK_CNT_I_MSK	include/ssv6200_aux.h	3447;"	d
+SDIO_WR_BLOCK_CNT_MSK	include/ssv6200_aux.h	3446;"	d
+SDIO_WR_BLOCK_CNT_SFT	include/ssv6200_aux.h	3448;"	d
+SDIO_WR_BLOCK_CNT_SZ	include/ssv6200_aux.h	3450;"	d
+SDK_API	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	18;"	d
+SD_CMD_IN_DLY_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2679;"	d
+SD_CMD_IN_DLY_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2677;"	d
+SD_CMD_IN_DLY_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2676;"	d
+SD_CMD_IN_DLY_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2678;"	d
+SD_CMD_IN_DLY_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2680;"	d
+SD_CMD_OUT_DLY_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2684;"	d
+SD_CMD_OUT_DLY_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2682;"	d
+SD_CMD_OUT_DLY_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2681;"	d
+SD_CMD_OUT_DLY_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2683;"	d
+SD_CMD_OUT_DLY_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2685;"	d
+SD_DAT_0_IN_DLY_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2719;"	d
+SD_DAT_0_IN_DLY_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2717;"	d
+SD_DAT_0_IN_DLY_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2716;"	d
+SD_DAT_0_IN_DLY_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2718;"	d
+SD_DAT_0_IN_DLY_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2720;"	d
+SD_DAT_0_OUT_DLY_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2724;"	d
+SD_DAT_0_OUT_DLY_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2722;"	d
+SD_DAT_0_OUT_DLY_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2721;"	d
+SD_DAT_0_OUT_DLY_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2723;"	d
+SD_DAT_0_OUT_DLY_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2725;"	d
+SD_DAT_1_IN_DLY_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2709;"	d
+SD_DAT_1_IN_DLY_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2707;"	d
+SD_DAT_1_IN_DLY_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2706;"	d
+SD_DAT_1_IN_DLY_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2708;"	d
+SD_DAT_1_IN_DLY_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2710;"	d
+SD_DAT_1_OUT_DLY_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2714;"	d
+SD_DAT_1_OUT_DLY_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2712;"	d
+SD_DAT_1_OUT_DLY_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2711;"	d
+SD_DAT_1_OUT_DLY_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2713;"	d
+SD_DAT_1_OUT_DLY_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2715;"	d
+SD_DAT_2_IN_DLY_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2699;"	d
+SD_DAT_2_IN_DLY_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2697;"	d
+SD_DAT_2_IN_DLY_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2696;"	d
+SD_DAT_2_IN_DLY_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2698;"	d
+SD_DAT_2_IN_DLY_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2700;"	d
+SD_DAT_2_OUT_DLY_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2704;"	d
+SD_DAT_2_OUT_DLY_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2702;"	d
+SD_DAT_2_OUT_DLY_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2701;"	d
+SD_DAT_2_OUT_DLY_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2703;"	d
+SD_DAT_2_OUT_DLY_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2705;"	d
+SD_DAT_3_IN_DLY_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2689;"	d
+SD_DAT_3_IN_DLY_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2687;"	d
+SD_DAT_3_IN_DLY_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2686;"	d
+SD_DAT_3_IN_DLY_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2688;"	d
+SD_DAT_3_IN_DLY_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2690;"	d
+SD_DAT_3_OUT_DLY_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2694;"	d
+SD_DAT_3_OUT_DLY_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2692;"	d
+SD_DAT_3_OUT_DLY_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2691;"	d
+SD_DAT_3_OUT_DLY_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2693;"	d
+SD_DAT_3_OUT_DLY_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2695;"	d
+SD_HOST_INIT_HI	include/ssv6200_aux.h	609;"	d
+SD_HOST_INIT_I_MSK	include/ssv6200_aux.h	607;"	d
+SD_HOST_INIT_MSK	include/ssv6200_aux.h	606;"	d
+SD_HOST_INIT_SFT	include/ssv6200_aux.h	608;"	d
+SD_HOST_INIT_SZ	include/ssv6200_aux.h	610;"	d
+SD_MASK_TOP_HI	include/ssv6200_aux.h	5094;"	d
+SD_MASK_TOP_I_MSK	include/ssv6200_aux.h	5092;"	d
+SD_MASK_TOP_MSK	include/ssv6200_aux.h	5091;"	d
+SD_MASK_TOP_SFT	include/ssv6200_aux.h	5093;"	d
+SD_MASK_TOP_SZ	include/ssv6200_aux.h	5095;"	d
+SD_REG_BANK_SIZE	include/ssv6200_reg.h	78;"	d
+SD_REG_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	97;"	d
+SD_REG_BASE	hwif/sdio/sdio_def.h	20;"	d
+SD_REG_BASE	include/ssv6200_reg.h	29;"	d
+SD_REG_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	36;"	d
+SD_RX_LEN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5204;"	d
+SD_RX_LEN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5202;"	d
+SD_RX_LEN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5201;"	d
+SD_RX_LEN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5203;"	d
+SD_RX_LEN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5205;"	d
+SD_SSDR104_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2859;"	d
+SD_SSDR104_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2857;"	d
+SD_SSDR104_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2856;"	d
+SD_SSDR104_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2858;"	d
+SD_SSDR104_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2860;"	d
+SD_SSDR50_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2854;"	d
+SD_SSDR50_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2852;"	d
+SD_SSDR50_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2851;"	d
+SD_SSDR50_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2853;"	d
+SD_SSDR50_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2855;"	d
+SECURITY_KEY_LEN	smac/drv_comm.h	26;"	d
+SEC_CFG_BIN_NAME	smac/hal/ssv6006c/ssv6006_mac.h	112;"	d
+SEC_H	smac/sec.h	17;"	d
+SEL_BTCX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2379;"	d
+SEL_BTCX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2377;"	d
+SEL_BTCX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2376;"	d
+SEL_BTCX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2378;"	d
+SEL_BTCX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2380;"	d
+SEL_DEBUG_II_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2404;"	d
+SEL_DEBUG_II_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2402;"	d
+SEL_DEBUG_II_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2401;"	d
+SEL_DEBUG_II_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2403;"	d
+SEL_DEBUG_II_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2405;"	d
+SEL_DEBUG_I_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2399;"	d
+SEL_DEBUG_I_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2397;"	d
+SEL_DEBUG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2396;"	d
+SEL_DEBUG_I_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2398;"	d
+SEL_DEBUG_I_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2400;"	d
+SEL_FLASH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2384;"	d
+SEL_FLASH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2382;"	d
+SEL_FLASH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2381;"	d
+SEL_FLASH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2383;"	d
+SEL_FLASH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2385;"	d
+SEL_GPO_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2439;"	d
+SEL_GPO_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2437;"	d
+SEL_GPO_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2436;"	d
+SEL_GPO_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2438;"	d
+SEL_GPO_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2440;"	d
+SEL_I2C_MST_II_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2359;"	d
+SEL_I2C_MST_II_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2357;"	d
+SEL_I2C_MST_II_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2356;"	d
+SEL_I2C_MST_II_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2358;"	d
+SEL_I2C_MST_II_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2360;"	d
+SEL_I2C_MST_I_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2364;"	d
+SEL_I2C_MST_I_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2362;"	d
+SEL_I2C_MST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2361;"	d
+SEL_I2C_MST_I_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2363;"	d
+SEL_I2C_MST_I_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2365;"	d
+SEL_I2C_SLV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2354;"	d
+SEL_I2C_SLV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2352;"	d
+SEL_I2C_SLV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2351;"	d
+SEL_I2C_SLV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2353;"	d
+SEL_I2C_SLV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2355;"	d
+SEL_I2STRX_II_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2334;"	d
+SEL_I2STRX_II_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2332;"	d
+SEL_I2STRX_II_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2331;"	d
+SEL_I2STRX_II_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2333;"	d
+SEL_I2STRX_II_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2335;"	d
+SEL_I2STRX_I_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2339;"	d
+SEL_I2STRX_I_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2337;"	d
+SEL_I2STRX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2336;"	d
+SEL_I2STRX_I_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2338;"	d
+SEL_I2STRX_I_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2340;"	d
+SEL_MEM_BIST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2409;"	d
+SEL_MEM_BIST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2407;"	d
+SEL_MEM_BIST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2406;"	d
+SEL_MEM_BIST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2408;"	d
+SEL_MEM_BIST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2410;"	d
+SEL_PWM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2394;"	d
+SEL_PWM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2392;"	d
+SEL_PWM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2391;"	d
+SEL_PWM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2393;"	d
+SEL_PWM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2395;"	d
+SEL_RF_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2389;"	d
+SEL_RF_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2387;"	d
+SEL_RF_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2386;"	d
+SEL_RF_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2388;"	d
+SEL_RF_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2390;"	d
+SEL_SPI_MST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2349;"	d
+SEL_SPI_MST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2347;"	d
+SEL_SPI_MST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2346;"	d
+SEL_SPI_MST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2348;"	d
+SEL_SPI_MST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2350;"	d
+SEL_SPI_SLV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2344;"	d
+SEL_SPI_SLV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2342;"	d
+SEL_SPI_SLV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2341;"	d
+SEL_SPI_SLV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2343;"	d
+SEL_SPI_SLV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2345;"	d
+SEL_UART0_II_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2369;"	d
+SEL_UART0_II_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2367;"	d
+SEL_UART0_II_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2366;"	d
+SEL_UART0_II_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2368;"	d
+SEL_UART0_II_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2370;"	d
+SEL_UART0_I_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2374;"	d
+SEL_UART0_I_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2372;"	d
+SEL_UART0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2371;"	d
+SEL_UART0_I_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2373;"	d
+SEL_UART0_I_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2375;"	d
+SEL_USB_BIST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2414;"	d
+SEL_USB_BIST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2412;"	d
+SEL_USB_BIST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2411;"	d
+SEL_USB_BIST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2413;"	d
+SEL_USB_BIST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2415;"	d
+SEL_USB_IDDQ_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2424;"	d
+SEL_USB_IDDQ_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2422;"	d
+SEL_USB_IDDQ_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2421;"	d
+SEL_USB_IDDQ_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2423;"	d
+SEL_USB_IDDQ_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2425;"	d
+SEL_USB_TEST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2419;"	d
+SEL_USB_TEST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2417;"	d
+SEL_USB_TEST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2416;"	d
+SEL_USB_TEST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2418;"	d
+SEL_USB_TEST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2420;"	d
+SEQ_CTRL_HI	include/ssv6200_aux.h	6159;"	d
+SEQ_CTRL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5244;"	d
+SEQ_CTRL_I_MSK	include/ssv6200_aux.h	6157;"	d
+SEQ_CTRL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5242;"	d
+SEQ_CTRL_MSK	include/ssv6200_aux.h	6156;"	d
+SEQ_CTRL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5241;"	d
+SEQ_CTRL_SFT	include/ssv6200_aux.h	6158;"	d
+SEQ_CTRL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5243;"	d
+SEQ_CTRL_SZ	include/ssv6200_aux.h	6160;"	d
+SEQ_CTRL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5245;"	d
+SET_ABT_SW_RST_N	include/ssv6200_reg.h	8447;"	d
+SET_ACC_RD_LEN	include/ssv6200_reg.h	8473;"	d
+SET_ACC_WR_LEN	include/ssv6200_reg.h	8472;"	d
+SET_ACK_GEN_DUR	include/ssv6200_reg.h	6347;"	d
+SET_ACK_GEN_DUR	smac/hal/ssv6006c/ssv6006C_reg.h	10351;"	d
+SET_ACK_GEN_EN	include/ssv6200_reg.h	6345;"	d
+SET_ACK_GEN_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10349;"	d
+SET_ACK_GEN_INFO	include/ssv6200_reg.h	6348;"	d
+SET_ACK_GEN_INFO	smac/hal/ssv6006c/ssv6006C_reg.h	10352;"	d
+SET_ACK_GEN_RA_31_0	include/ssv6200_reg.h	6349;"	d
+SET_ACK_GEN_RA_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	10353;"	d
+SET_ACK_GEN_RA_47_32	include/ssv6200_reg.h	6350;"	d
+SET_ACK_GEN_RA_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	10354;"	d
+SET_ADDR1A_SEL	include/ssv6200_reg.h	6371;"	d
+SET_ADDR1A_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	10360;"	d
+SET_ADDR1B_SEL	include/ssv6200_reg.h	6374;"	d
+SET_ADDR1B_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	10363;"	d
+SET_ADDR2A_SEL	include/ssv6200_reg.h	6372;"	d
+SET_ADDR2A_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	10361;"	d
+SET_ADDR2B_SEL	include/ssv6200_reg.h	6375;"	d
+SET_ADDR2B_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	10364;"	d
+SET_ADDR3A_SEL	include/ssv6200_reg.h	6373;"	d
+SET_ADDR3A_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	10362;"	d
+SET_ADDR3B_SEL	include/ssv6200_reg.h	6376;"	d
+SET_ADDR3B_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	10365;"	d
+SET_ADDR3C_SEL	include/ssv6200_reg.h	6377;"	d
+SET_ADDR3C_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	10366;"	d
+SET_ADD_LEN	include/ssv6200_reg.h	6172;"	d
+SET_ADD_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	10190;"	d
+SET_AD_CIRCUIT_VERSION	include/ssv6200_reg.h	8423;"	d
+SET_AD_DP_VT_MON_Q	include/ssv6200_reg.h	8419;"	d
+SET_AD_SX_VT_MON_Q	include/ssv6200_reg.h	8418;"	d
+SET_AHB2PKT_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9321;"	d
+SET_AHB_BRIDGE_RESET	include/ssv6200_reg.h	5586;"	d
+SET_AHB_BRIDGE_RESET	smac/hal/ssv6006c/ssv6006C_reg.h	9624;"	d
+SET_AHB_ERR_RST	include/ssv6200_reg.h	4969;"	d
+SET_AHB_FEN_ADDR	include/ssv6200_reg.h	4994;"	d
+SET_AHB_HANG2	include/ssv6200_reg.h	5606;"	d
+SET_AHB_HANG4	include/ssv6200_reg.h	5553;"	d
+SET_AHB_ILL_ADDR	include/ssv6200_reg.h	4993;"	d
+SET_AHB_STATUS	include/ssv6200_reg.h	4976;"	d
+SET_AHB_SW_RST	include/ssv6200_reg.h	4968;"	d
+SET_ALC_ABT_CLR	smac/hal/ssv6006c/ssv6006C_reg.h	15947;"	d
+SET_ALC_ABT_ID	include/ssv6200_reg.h	8479;"	d
+SET_ALC_ABT_ID	smac/hal/ssv6006c/ssv6006C_reg.h	15945;"	d
+SET_ALC_ABT_INT	include/ssv6200_reg.h	8480;"	d
+SET_ALC_ABT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	15946;"	d
+SET_ALC_BUSY	include/ssv6200_reg.h	7421;"	d
+SET_ALC_BUSY	smac/hal/ssv6006c/ssv6006C_reg.h	15865;"	d
+SET_ALC_ERR	include/ssv6200_reg.h	8486;"	d
+SET_ALC_ERR_CLR	smac/hal/ssv6006c/ssv6006C_reg.h	15950;"	d
+SET_ALC_ERR_ID	include/ssv6200_reg.h	8490;"	d
+SET_ALC_ERR_ID	smac/hal/ssv6006c/ssv6006C_reg.h	15954;"	d
+SET_ALC_ERR_STS	smac/hal/ssv6006c/ssv6006C_reg.h	15948;"	d
+SET_ALC_FAIL	include/ssv6200_reg.h	7420;"	d
+SET_ALC_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	15864;"	d
+SET_ALC_INT_ID	include/ssv6200_reg.h	7426;"	d
+SET_ALC_INT_ID	smac/hal/ssv6006c/ssv6006C_reg.h	15870;"	d
+SET_ALC_LENG	include/ssv6200_reg.h	7397;"	d
+SET_ALC_LENG	smac/hal/ssv6006c/ssv6006C_reg.h	15841;"	d
+SET_ALC_NOCHG_ID	include/ssv6200_reg.h	8528;"	d
+SET_ALC_NOCHG_INT	include/ssv6200_reg.h	8529;"	d
+SET_ALC_TIMEOUT	include/ssv6200_reg.h	7427;"	d
+SET_ALC_TIMEOUT	smac/hal/ssv6006c/ssv6006C_reg.h	15871;"	d
+SET_ALC_TIMEOUT_INT	include/ssv6200_reg.h	7429;"	d
+SET_ALC_TIMEOUT_INT	smac/hal/ssv6006c/ssv6006C_reg.h	15873;"	d
+SET_ALC_TIMEOUT_INT_EN	include/ssv6200_reg.h	7428;"	d
+SET_ALC_TIMEOUT_INT_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15872;"	d
+SET_ALLOCATESTATUS	include/ssv6200_reg.h	5610;"	d
+SET_ALLOCATE_STATUS	include/ssv6200_reg.h	5550;"	d
+SET_ALLOCATE_STATUS2	include/ssv6200_reg.h	5602;"	d
+SET_ALLOW_SD_RESET	include/ssv6200_reg.h	5026;"	d
+SET_ALLOW_SD_SPI_RESET	smac/hal/ssv6006c/ssv6006C_reg.h	9406;"	d
+SET_ALL_ID_ALC_LEN	include/ssv6200_reg.h	7453;"	d
+SET_ALL_ID_ALC_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	15897;"	d
+SET_ALL_ID_LEN_THOLD	include/ssv6200_reg.h	5909;"	d
+SET_ALL_ID_LEN_THOLD_INT	include/ssv6200_reg.h	7447;"	d
+SET_ALL_ID_LEN_THOLD_INT	smac/hal/ssv6006c/ssv6006C_reg.h	15891;"	d
+SET_ALL_ID_LEN_THOLD_SD	include/ssv6200_reg.h	5978;"	d
+SET_ALL_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	9287;"	d
+SET_ALR_ABT_NOCHG_INT_IRQ	include/ssv6200_reg.h	5915;"	d
+SET_ALR_ABT_NOCHG_INT_IRQ_SD	include/ssv6200_reg.h	5984;"	d
+SET_ALR_SW_RST_N	include/ssv6200_reg.h	8444;"	d
+SET_AL_STATE	include/ssv6200_reg.h	8488;"	d
+SET_AL_STATE	smac/hal/ssv6006c/ssv6006C_reg.h	15952;"	d
+SET_AMPDU_CLK_EN	include/ssv6200_reg.h	6705;"	d
+SET_AMPDU_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10801;"	d
+SET_AMPDU_CSR_CLK_EN	include/ssv6200_reg.h	6724;"	d
+SET_AMPDU_CSR_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10820;"	d
+SET_AMPDU_CSR_RST	include/ssv6200_reg.h	6696;"	d
+SET_AMPDU_CSR_RST	smac/hal/ssv6006c/ssv6006C_reg.h	10792;"	d
+SET_AMPDU_ENG_CLK_EN	include/ssv6200_reg.h	6717;"	d
+SET_AMPDU_ENG_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10813;"	d
+SET_AMPDU_ENG_RST	include/ssv6200_reg.h	6682;"	d
+SET_AMPDU_ENG_RST	smac/hal/ssv6006c/ssv6006C_reg.h	10778;"	d
+SET_AMPDU_SIG	include/ssv6200_reg.h	6380;"	d
+SET_AMPDU_SIG	smac/hal/ssv6006c/ssv6006C_reg.h	10380;"	d
+SET_AMPDU_SNIFFER	include/ssv6200_reg.h	6735;"	d
+SET_AMPDU_SNIFFER	smac/hal/ssv6006c/ssv6006C_reg.h	10831;"	d
+SET_AMPDU_SW_RST	include/ssv6200_reg.h	6670;"	d
+SET_AMPDU_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	10766;"	d
+SET_ASIC_TAG	include/ssv6200_reg.h	6662;"	d
+SET_AUTO_CSN	smac/hal/ssv6006c/ssv6006C_reg.h	10273;"	d
+SET_AUTO_REMAIN	smac/hal/ssv6006c/ssv6006C_reg.h	10882;"	d
+SET_AUTO_SEQNO	include/ssv6200_reg.h	6116;"	d
+SET_AUTO_SEQNO	smac/hal/ssv6006c/ssv6006C_reg.h	10095;"	d
+SET_AVA_TAG	include/ssv6200_reg.h	8500;"	d
+SET_AVA_TAG	smac/hal/ssv6006c/ssv6006C_reg.h	15962;"	d
+SET_BACKUP_PG_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	10131;"	d
+SET_BACK_DLY	include/ssv6200_reg.h	5696;"	d
+SET_BACK_DLY	smac/hal/ssv6006c/ssv6006C_reg.h	9688;"	d
+SET_BA_AGRE_EN	include/ssv6200_reg.h	6337;"	d
+SET_BA_AGRE_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10341;"	d
+SET_BA_CTRL	include/ssv6200_reg.h	6335;"	d
+SET_BA_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	10339;"	d
+SET_BA_DBG_EN	include/ssv6200_reg.h	6336;"	d
+SET_BA_DBG_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10340;"	d
+SET_BA_GEN_EN	include/ssv6200_reg.h	6346;"	d
+SET_BA_GEN_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10350;"	d
+SET_BA_HW_ID	smac/hal/ssv6006c/ssv6006C_reg.h	10375;"	d
+SET_BA_H_QUEUE_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10372;"	d
+SET_BA_SB0	include/ssv6200_reg.h	6342;"	d
+SET_BA_SB0	smac/hal/ssv6006c/ssv6006C_reg.h	10346;"	d
+SET_BA_SB1	include/ssv6200_reg.h	6343;"	d
+SET_BA_SB1	smac/hal/ssv6006c/ssv6006C_reg.h	10347;"	d
+SET_BA_ST_SEQ	include/ssv6200_reg.h	6341;"	d
+SET_BA_ST_SEQ	smac/hal/ssv6006c/ssv6006C_reg.h	10345;"	d
+SET_BA_TA_31_0	include/ssv6200_reg.h	6338;"	d
+SET_BA_TA_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	10342;"	d
+SET_BA_TA_47_32	include/ssv6200_reg.h	6339;"	d
+SET_BA_TA_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	10343;"	d
+SET_BA_TID	include/ssv6200_reg.h	6340;"	d
+SET_BA_TID	smac/hal/ssv6006c/ssv6006C_reg.h	10344;"	d
+SET_BCAST_RATEUNKNOW	include/ssv6200_reg.h	6648;"	d
+SET_BEACON_TIMEOUT	include/ssv6200_reg.h	6762;"	d
+SET_BEACON_TIMEOUT	smac/hal/ssv6006c/ssv6006C_reg.h	10865;"	d
+SET_BEACON_TIMEOUT_EN	include/ssv6200_reg.h	6753;"	d
+SET_BEACON_TIMEOUT_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10856;"	d
+SET_BIST_CLK_EN	include/ssv6200_reg.h	4961;"	d
+SET_BIT	smac/ap.c	38;"	d	file:
+SET_BIT1_RD_CMD	smac/hal/ssv6006c/ssv6006C_reg.h	9890;"	d
+SET_BIT1_WR_CMD	smac/hal/ssv6006c/ssv6006C_reg.h	9889;"	d
+SET_BIT2_RD_CMD	smac/hal/ssv6006c/ssv6006C_reg.h	9891;"	d
+SET_BIT4_RD_CMD	smac/hal/ssv6006c/ssv6006C_reg.h	9892;"	d
+SET_BIT4_WR_CMD	smac/hal/ssv6006c/ssv6006C_reg.h	9893;"	d
+SET_BIT_MODE1	include/ssv6200_reg.h	6050;"	d
+SET_BIT_MODE2	include/ssv6200_reg.h	6051;"	d
+SET_BIT_MODE4	include/ssv6200_reg.h	6052;"	d
+SET_BLOCK_TXQ	smac/hal/ssv6006c/ssv6006C_reg.h	10437;"	d
+SET_BOOT_ADDR	include/ssv6200_reg.h	6034;"	d
+SET_BOOT_CHECK_SUM	include/ssv6200_reg.h	6053;"	d
+SET_BRDC_DIV	include/ssv6200_reg.h	5797;"	d
+SET_BRDC_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	9788;"	d
+SET_BREAK	smac/hal/ssv6006c/ssv6006C_reg.h	9804;"	d
+SET_BREAK_HI	include/ssv6200_aux.h	4354;"	d
+SET_BREAK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3459;"	d
+SET_BREAK_INT	include/ssv6200_reg.h	5785;"	d
+SET_BREAK_INT	smac/hal/ssv6006c/ssv6006C_reg.h	9776;"	d
+SET_BREAK_I_MSK	include/ssv6200_aux.h	4352;"	d
+SET_BREAK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3457;"	d
+SET_BREAK_MSK	include/ssv6200_aux.h	4351;"	d
+SET_BREAK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3456;"	d
+SET_BREAK_SFT	include/ssv6200_aux.h	4353;"	d
+SET_BREAK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3458;"	d
+SET_BREAK_SZ	include/ssv6200_aux.h	4355;"	d
+SET_BREAK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3460;"	d
+SET_BRST_MODE	include/ssv6200_reg.h	5693;"	d
+SET_BSS	include/ssv6200_reg.h	5650;"	d
+SET_BSS	smac/hal/ssv6006c/ssv6006C_reg.h	9646;"	d
+SET_BSSID1_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	10845;"	d
+SET_BSSID1_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	10846;"	d
+SET_BSSID_31_0	include/ssv6200_reg.h	6738;"	d
+SET_BSSID_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	10836;"	d
+SET_BSSID_47_32	include/ssv6200_reg.h	6739;"	d
+SET_BSSID_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	10837;"	d
+SET_BTCX_CLK_EN	include/ssv6200_reg.h	4951;"	d
+SET_BTCX_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9310;"	d
+SET_BTCX_CSR_CLK_EN	include/ssv6200_reg.h	4963;"	d
+SET_BTCX_CSR_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9334;"	d
+SET_BTCX_INTR	smac/hal/ssv6006c/ssv6006C_reg.h	10881;"	d
+SET_BTCX_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	10880;"	d
+SET_BTCX_SW_RST	include/ssv6200_reg.h	4917;"	d
+SET_BTCX_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	9277;"	d
+SET_BT_BUSY	smac/hal/ssv6006c/ssv6006C_reg.h	10531;"	d
+SET_BT_BUSY_MANUAL_EN	include/ssv6200_reg.h	6770;"	d
+SET_BT_BUSY_MANUAL_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10873;"	d
+SET_BT_BUSY_SET	include/ssv6200_reg.h	6771;"	d
+SET_BT_BUSY_SET	smac/hal/ssv6006c/ssv6006C_reg.h	10874;"	d
+SET_BT_PRI_SMP_TIME	include/ssv6200_reg.h	6760;"	d
+SET_BT_PRI_SMP_TIME	smac/hal/ssv6006c/ssv6006C_reg.h	10863;"	d
+SET_BT_STA_SMP_TIME	include/ssv6200_reg.h	6761;"	d
+SET_BT_STA_SMP_TIME	smac/hal/ssv6006c/ssv6006C_reg.h	10864;"	d
+SET_BT_SW_O_C	include/ssv6200_reg.h	5101;"	d
+SET_BT_SW_O_OE	include/ssv6200_reg.h	5095;"	d
+SET_BT_SW_O_PE	include/ssv6200_reg.h	5096;"	d
+SET_BT_SW_POL	include/ssv6200_reg.h	6759;"	d
+SET_BT_SW_POL	smac/hal/ssv6006c/ssv6006C_reg.h	10862;"	d
+SET_BT_TRX_SMP_TIME	smac/hal/ssv6006c/ssv6006C_reg.h	10879;"	d
+SET_BT_TXBAR_MANUAL_EN	include/ssv6200_reg.h	6768;"	d
+SET_BT_TXBAR_MANUAL_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10871;"	d
+SET_BT_TXBAR_SET	include/ssv6200_reg.h	6769;"	d
+SET_BT_TXBAR_SET	smac/hal/ssv6006c/ssv6006C_reg.h	10872;"	d
+SET_BYPASSS_TX_PARSER_ENCAP	include/ssv6200_reg.h	6117;"	d
+SET_BYPASS_TX_PARSER_ENCAP	smac/hal/ssv6006c/ssv6006C_reg.h	10096;"	d
+SET_B_CCA_CNT	include/ssv6200_reg.h	7827;"	d
+SET_B_FREQ_OS	include/ssv6200_reg.h	7819;"	d
+SET_B_LENGTH_FIELD	include/ssv6200_reg.h	7828;"	d
+SET_B_PACKET_CNT	include/ssv6200_reg.h	7826;"	d
+SET_B_PACKET_ERR_CNT	include/ssv6200_reg.h	7824;"	d
+SET_B_RCPI	include/ssv6200_reg.h	7821;"	d
+SET_B_SERVICE_FIELD	include/ssv6200_reg.h	7831;"	d
+SET_B_SNR	include/ssv6200_reg.h	7820;"	d
+SET_CALCULATE	include/ssv6200_reg.h	6175;"	d
+SET_CALCULATE	smac/hal/ssv6006c/ssv6006C_reg.h	10193;"	d
+SET_CARD_FW_DL_STATUS	include/ssv6200_reg.h	5539;"	d
+SET_CARD_RCA_REG	include/ssv6200_reg.h	5556;"	d
+SET_CARD_RCA_REG	smac/hal/ssv6006c/ssv6006C_reg.h	9601;"	d
+SET_CBR_AD_DP_VT_MON_Q	include/ssv6200_reg.h	7147;"	d
+SET_CBR_AD_SX_VT_MON_Q	include/ssv6200_reg.h	7146;"	d
+SET_CBR_CH_RDY	include/ssv6200_reg.h	7144;"	d
+SET_CBR_DATA_OUT_SEL	include/ssv6200_reg.h	7177;"	d
+SET_CBR_DA_DP_BBPLL_BS	include/ssv6200_reg.h	7150;"	d
+SET_CBR_DA_LCK_RDY	include/ssv6200_reg.h	7141;"	d
+SET_CBR_DA_R_CAL_CODE	include/ssv6200_reg.h	7148;"	d
+SET_CBR_DA_R_CODE_LUT	include/ssv6200_reg.h	7145;"	d
+SET_CBR_DA_SX_SUB_SEL	include/ssv6200_reg.h	7149;"	d
+SET_CBR_DBG_EN	include/ssv6200_reg.h	7173;"	d
+SET_CBR_DBG_SEL	include/ssv6200_reg.h	7172;"	d
+SET_CBR_DP_VT_MON_RDY	include/ssv6200_reg.h	7143;"	d
+SET_CBR_FREQ_SEL	include/ssv6200_reg.h	7179;"	d
+SET_CBR_IDEAL_IQ_EN	include/ssv6200_reg.h	7176;"	d
+SET_CBR_IFS_TIME	include/ssv6200_reg.h	7153;"	d
+SET_CBR_INTP_SEL	include/ssv6200_reg.h	7168;"	d
+SET_CBR_IQ_SCALE	include/ssv6200_reg.h	7180;"	d
+SET_CBR_IQ_SWP	include/ssv6200_reg.h	7169;"	d
+SET_CBR_LENGTH_TARGET	include/ssv6200_reg.h	7154;"	d
+SET_CBR_PLCP_BYTE_LENGTH	include/ssv6200_reg.h	7159;"	d
+SET_CBR_PLCP_PSDU_DATA_MEM	include/ssv6200_reg.h	7157;"	d
+SET_CBR_PLCP_PSDU_PREAMBLE_SHORT	include/ssv6200_reg.h	7158;"	d
+SET_CBR_PLCP_PSDU_RATE	include/ssv6200_reg.h	7160;"	d
+SET_CBR_RCAL_RDY	include/ssv6200_reg.h	7140;"	d
+SET_CBR_RG_ADC_CLKSEL	include/ssv6200_reg.h	6979;"	d
+SET_CBR_RG_ADC_DIBIAS	include/ssv6200_reg.h	6980;"	d
+SET_CBR_RG_ADC_DIVR	include/ssv6200_reg.h	6981;"	d
+SET_CBR_RG_ADC_DVCMI	include/ssv6200_reg.h	6982;"	d
+SET_CBR_RG_ADC_SAMSEL	include/ssv6200_reg.h	6983;"	d
+SET_CBR_RG_ADC_STNBY	include/ssv6200_reg.h	6984;"	d
+SET_CBR_RG_ADC_TESTMODE	include/ssv6200_reg.h	6985;"	d
+SET_CBR_RG_ADC_TSEL	include/ssv6200_reg.h	6986;"	d
+SET_CBR_RG_ADC_VRSEL	include/ssv6200_reg.h	6987;"	d
+SET_CBR_RG_BUCK_LEVEL	include/ssv6200_reg.h	6896;"	d
+SET_CBR_RG_DACI1ST	include/ssv6200_reg.h	6990;"	d
+SET_CBR_RG_DCDC_MODE	include/ssv6200_reg.h	6886;"	d
+SET_CBR_RG_DICMP	include/ssv6200_reg.h	6988;"	d
+SET_CBR_RG_DIOP	include/ssv6200_reg.h	6989;"	d
+SET_CBR_RG_DIS_DA_OFFSET	include/ssv6200_reg.h	7171;"	d
+SET_CBR_RG_DP_BBPLL_BP	include/ssv6200_reg.h	7084;"	d
+SET_CBR_RG_DP_BBPLL_BS_CWD	include/ssv6200_reg.h	7139;"	d
+SET_CBR_RG_DP_BBPLL_BS_CWR	include/ssv6200_reg.h	7138;"	d
+SET_CBR_RG_DP_BBPLL_ICP	include/ssv6200_reg.h	7085;"	d
+SET_CBR_RG_DP_BBPLL_IDUAL	include/ssv6200_reg.h	7086;"	d
+SET_CBR_RG_DP_BBPLL_OD_TEST	include/ssv6200_reg.h	7087;"	d
+SET_CBR_RG_DP_BBPLL_PD	include/ssv6200_reg.h	7088;"	d
+SET_CBR_RG_DP_BBPLL_PFD_DLY	include/ssv6200_reg.h	7090;"	d
+SET_CBR_RG_DP_BBPLL_TESTSEL	include/ssv6200_reg.h	7089;"	d
+SET_CBR_RG_DP_CK320BY2	include/ssv6200_reg.h	7081;"	d
+SET_CBR_RG_DP_DCP	include/ssv6200_reg.h	7094;"	d
+SET_CBR_RG_DP_DCS	include/ssv6200_reg.h	7095;"	d
+SET_CBR_RG_DP_DR3	include/ssv6200_reg.h	7093;"	d
+SET_CBR_RG_DP_FBDIV	include/ssv6200_reg.h	7096;"	d
+SET_CBR_RG_DP_FODIV	include/ssv6200_reg.h	7097;"	d
+SET_CBR_RG_DP_LDO_LEVEL	include/ssv6200_reg.h	6893;"	d
+SET_CBR_RG_DP_OD_TEST	include/ssv6200_reg.h	7083;"	d
+SET_CBR_RG_DP_REFDIV	include/ssv6200_reg.h	7098;"	d
+SET_CBR_RG_DP_RHP	include/ssv6200_reg.h	7092;"	d
+SET_CBR_RG_DP_RP	include/ssv6200_reg.h	7091;"	d
+SET_CBR_RG_DP_VT_MON_TMR	include/ssv6200_reg.h	7080;"	d
+SET_CBR_RG_DP_VT_TH_HI	include/ssv6200_reg.h	7078;"	d
+SET_CBR_RG_DP_VT_TH_LO	include/ssv6200_reg.h	7079;"	d
+SET_CBR_RG_EN_ADC	include/ssv6200_reg.h	6867;"	d
+SET_CBR_RG_EN_DP_VT_MON	include/ssv6200_reg.h	7077;"	d
+SET_CBR_RG_EN_EXT_DA	include/ssv6200_reg.h	7170;"	d
+SET_CBR_RG_EN_IREF_RX	include/ssv6200_reg.h	6885;"	d
+SET_CBR_RG_EN_LDO_ABB	include/ssv6200_reg.h	6881;"	d
+SET_CBR_RG_EN_LDO_AFE	include/ssv6200_reg.h	6882;"	d
+SET_CBR_RG_EN_LDO_RX_FE	include/ssv6200_reg.h	6880;"	d
+SET_CBR_RG_EN_MANUAL	include/ssv6200_reg.h	6848;"	d
+SET_CBR_RG_EN_RCAL	include/ssv6200_reg.h	7131;"	d
+SET_CBR_RG_EN_RX_DIV2	include/ssv6200_reg.h	6861;"	d
+SET_CBR_RG_EN_RX_FILTER	include/ssv6200_reg.h	6864;"	d
+SET_CBR_RG_EN_RX_HPF	include/ssv6200_reg.h	6865;"	d
+SET_CBR_RG_EN_RX_IQCAL	include/ssv6200_reg.h	6876;"	d
+SET_CBR_RG_EN_RX_LNA	include/ssv6200_reg.h	6859;"	d
+SET_CBR_RG_EN_RX_LOBF	include/ssv6200_reg.h	6872;"	d
+SET_CBR_RG_EN_RX_LOBUF	include/ssv6200_reg.h	6862;"	d
+SET_CBR_RG_EN_RX_MIXER	include/ssv6200_reg.h	6860;"	d
+SET_CBR_RG_EN_RX_PADSW	include/ssv6200_reg.h	6897;"	d
+SET_CBR_RG_EN_RX_RSSI	include/ssv6200_reg.h	6866;"	d
+SET_CBR_RG_EN_RX_RSSI_TESTNODE	include/ssv6200_reg.h	6923;"	d
+SET_CBR_RG_EN_RX_TESTNODE	include/ssv6200_reg.h	6898;"	d
+SET_CBR_RG_EN_RX_TZ	include/ssv6200_reg.h	6863;"	d
+SET_CBR_RG_EN_SX	include/ssv6200_reg.h	6858;"	d
+SET_CBR_RG_EN_SX_CH	include/ssv6200_reg.h	7003;"	d
+SET_CBR_RG_EN_SX_CHP	include/ssv6200_reg.h	7004;"	d
+SET_CBR_RG_EN_SX_CHPLDO	include/ssv6200_reg.h	6883;"	d
+SET_CBR_RG_EN_SX_DELCAL	include/ssv6200_reg.h	7011;"	d
+SET_CBR_RG_EN_SX_DITHER	include/ssv6200_reg.h	7010;"	d
+SET_CBR_RG_EN_SX_DIV	include/ssv6200_reg.h	7015;"	d
+SET_CBR_RG_EN_SX_DIVCK	include/ssv6200_reg.h	7005;"	d
+SET_CBR_RG_EN_SX_LCK	include/ssv6200_reg.h	7009;"	d
+SET_CBR_RG_EN_SX_LOBFLDO	include/ssv6200_reg.h	6884;"	d
+SET_CBR_RG_EN_SX_LPF	include/ssv6200_reg.h	7016;"	d
+SET_CBR_RG_EN_SX_MOD	include/ssv6200_reg.h	7008;"	d
+SET_CBR_RG_EN_SX_PC_BYPASS	include/ssv6200_reg.h	7012;"	d
+SET_CBR_RG_EN_SX_R3	include/ssv6200_reg.h	7002;"	d
+SET_CBR_RG_EN_SX_VCO	include/ssv6200_reg.h	7007;"	d
+SET_CBR_RG_EN_SX_VCOBF	include/ssv6200_reg.h	7006;"	d
+SET_CBR_RG_EN_SX_VT_MON	include/ssv6200_reg.h	7013;"	d
+SET_CBR_RG_EN_SX_VT_MON_DG	include/ssv6200_reg.h	7014;"	d
+SET_CBR_RG_EN_TX_DAC_CAL	include/ssv6200_reg.h	6877;"	d
+SET_CBR_RG_EN_TX_DAC_OUT	include/ssv6200_reg.h	6879;"	d
+SET_CBR_RG_EN_TX_DIV2	include/ssv6200_reg.h	6869;"	d
+SET_CBR_RG_EN_TX_DIV2_BUF	include/ssv6200_reg.h	6870;"	d
+SET_CBR_RG_EN_TX_DPD	include/ssv6200_reg.h	6874;"	d
+SET_CBR_RG_EN_TX_LOBF	include/ssv6200_reg.h	6871;"	d
+SET_CBR_RG_EN_TX_MOD	include/ssv6200_reg.h	6868;"	d
+SET_CBR_RG_EN_TX_SELF_MIXER	include/ssv6200_reg.h	6878;"	d
+SET_CBR_RG_EN_TX_TRSW	include/ssv6200_reg.h	6857;"	d
+SET_CBR_RG_EN_TX_TSSI	include/ssv6200_reg.h	6875;"	d
+SET_CBR_RG_HPF1_FAST_SET_X	include/ssv6200_reg.h	6971;"	d
+SET_CBR_RG_HPF1_FAST_SET_Y	include/ssv6200_reg.h	6972;"	d
+SET_CBR_RG_HPF1_FAST_SET_Z	include/ssv6200_reg.h	6973;"	d
+SET_CBR_RG_HPF_T1A	include/ssv6200_reg.h	6974;"	d
+SET_CBR_RG_HPF_T1B	include/ssv6200_reg.h	6975;"	d
+SET_CBR_RG_HPF_T1C	include/ssv6200_reg.h	6976;"	d
+SET_CBR_RG_IDACAI_PGAG0	include/ssv6200_reg.h	7129;"	d
+SET_CBR_RG_IDACAI_PGAG1	include/ssv6200_reg.h	7127;"	d
+SET_CBR_RG_IDACAI_PGAG10	include/ssv6200_reg.h	7109;"	d
+SET_CBR_RG_IDACAI_PGAG11	include/ssv6200_reg.h	7107;"	d
+SET_CBR_RG_IDACAI_PGAG12	include/ssv6200_reg.h	7105;"	d
+SET_CBR_RG_IDACAI_PGAG13	include/ssv6200_reg.h	7103;"	d
+SET_CBR_RG_IDACAI_PGAG14	include/ssv6200_reg.h	7101;"	d
+SET_CBR_RG_IDACAI_PGAG15	include/ssv6200_reg.h	7099;"	d
+SET_CBR_RG_IDACAI_PGAG2	include/ssv6200_reg.h	7125;"	d
+SET_CBR_RG_IDACAI_PGAG3	include/ssv6200_reg.h	7123;"	d
+SET_CBR_RG_IDACAI_PGAG4	include/ssv6200_reg.h	7121;"	d
+SET_CBR_RG_IDACAI_PGAG5	include/ssv6200_reg.h	7119;"	d
+SET_CBR_RG_IDACAI_PGAG6	include/ssv6200_reg.h	7117;"	d
+SET_CBR_RG_IDACAI_PGAG7	include/ssv6200_reg.h	7115;"	d
+SET_CBR_RG_IDACAI_PGAG8	include/ssv6200_reg.h	7113;"	d
+SET_CBR_RG_IDACAI_PGAG9	include/ssv6200_reg.h	7111;"	d
+SET_CBR_RG_IDACAQ_PGAG0	include/ssv6200_reg.h	7130;"	d
+SET_CBR_RG_IDACAQ_PGAG1	include/ssv6200_reg.h	7128;"	d
+SET_CBR_RG_IDACAQ_PGAG10	include/ssv6200_reg.h	7110;"	d
+SET_CBR_RG_IDACAQ_PGAG11	include/ssv6200_reg.h	7108;"	d
+SET_CBR_RG_IDACAQ_PGAG12	include/ssv6200_reg.h	7106;"	d
+SET_CBR_RG_IDACAQ_PGAG13	include/ssv6200_reg.h	7104;"	d
+SET_CBR_RG_IDACAQ_PGAG14	include/ssv6200_reg.h	7102;"	d
+SET_CBR_RG_IDACAQ_PGAG15	include/ssv6200_reg.h	7100;"	d
+SET_CBR_RG_IDACAQ_PGAG2	include/ssv6200_reg.h	7126;"	d
+SET_CBR_RG_IDACAQ_PGAG3	include/ssv6200_reg.h	7124;"	d
+SET_CBR_RG_IDACAQ_PGAG4	include/ssv6200_reg.h	7122;"	d
+SET_CBR_RG_IDACAQ_PGAG5	include/ssv6200_reg.h	7120;"	d
+SET_CBR_RG_IDACAQ_PGAG6	include/ssv6200_reg.h	7118;"	d
+SET_CBR_RG_IDACAQ_PGAG7	include/ssv6200_reg.h	7116;"	d
+SET_CBR_RG_IDACAQ_PGAG8	include/ssv6200_reg.h	7114;"	d
+SET_CBR_RG_IDACAQ_PGAG9	include/ssv6200_reg.h	7112;"	d
+SET_CBR_RG_IDEAL_CYCLE	include/ssv6200_reg.h	7076;"	d
+SET_CBR_RG_I_PAD_PD	include/ssv6200_reg.h	7163;"	d
+SET_CBR_RG_LDO_LEVEL_ABB	include/ssv6200_reg.h	6888;"	d
+SET_CBR_RG_LDO_LEVEL_AFE	include/ssv6200_reg.h	6889;"	d
+SET_CBR_RG_LDO_LEVEL_RX_FE	include/ssv6200_reg.h	6887;"	d
+SET_CBR_RG_MODE	include/ssv6200_reg.h	6856;"	d
+SET_CBR_RG_O_PAD_PD	include/ssv6200_reg.h	7162;"	d
+SET_CBR_RG_PABIAS_AB	include/ssv6200_reg.h	6935;"	d
+SET_CBR_RG_PABIAS_CTRL	include/ssv6200_reg.h	6934;"	d
+SET_CBR_RG_PACELL_EN	include/ssv6200_reg.h	6933;"	d
+SET_CBR_RG_PAD_DS	include/ssv6200_reg.h	7165;"	d
+SET_CBR_RG_PAD_DS_CLK	include/ssv6200_reg.h	7167;"	d
+SET_CBR_RG_PGAG	include/ssv6200_reg.h	6855;"	d
+SET_CBR_RG_PKT_GEN_TX_CNT	include/ssv6200_reg.h	7174;"	d
+SET_CBR_RG_RCAL_CODE_CWD	include/ssv6200_reg.h	7135;"	d
+SET_CBR_RG_RCAL_CODE_CWR	include/ssv6200_reg.h	7134;"	d
+SET_CBR_RG_RCAL_SPD	include/ssv6200_reg.h	7132;"	d
+SET_CBR_RG_RCAL_TMR	include/ssv6200_reg.h	7133;"	d
+SET_CBR_RG_RFG	include/ssv6200_reg.h	6854;"	d
+SET_CBR_RG_RSSI_CLOCK_GATING	include/ssv6200_reg.h	6927;"	d
+SET_CBR_RG_RX_ABBCFIX	include/ssv6200_reg.h	6899;"	d
+SET_CBR_RG_RX_ABBCTUNE	include/ssv6200_reg.h	6900;"	d
+SET_CBR_RG_RX_ABBOUT_TRI_STATE	include/ssv6200_reg.h	6901;"	d
+SET_CBR_RG_RX_ABB_N_MODE	include/ssv6200_reg.h	6902;"	d
+SET_CBR_RG_RX_ADCRSSI_CLKSEL	include/ssv6200_reg.h	6924;"	d
+SET_CBR_RG_RX_ADCRSSI_VCM	include/ssv6200_reg.h	6925;"	d
+SET_CBR_RG_RX_AGC	include/ssv6200_reg.h	6852;"	d
+SET_CBR_RG_RX_DIV2_CORE	include/ssv6200_reg.h	6939;"	d
+SET_CBR_RG_RX_EN_LOOPA	include/ssv6200_reg.h	6903;"	d
+SET_CBR_RG_RX_FILTERI1ST	include/ssv6200_reg.h	6904;"	d
+SET_CBR_RG_RX_FILTERI2ND	include/ssv6200_reg.h	6905;"	d
+SET_CBR_RG_RX_FILTERI3RD	include/ssv6200_reg.h	6906;"	d
+SET_CBR_RG_RX_FILTERI_COURSE	include/ssv6200_reg.h	6907;"	d
+SET_CBR_RG_RX_FILTERVCM	include/ssv6200_reg.h	6908;"	d
+SET_CBR_RG_RX_GAIN_MANUAL	include/ssv6200_reg.h	6853;"	d
+SET_CBR_RG_RX_HG_LNAHGN_BIAS	include/ssv6200_reg.h	6948;"	d
+SET_CBR_RG_RX_HG_LNAHGP_BIAS	include/ssv6200_reg.h	6949;"	d
+SET_CBR_RG_RX_HG_LNALG_BIAS	include/ssv6200_reg.h	6950;"	d
+SET_CBR_RG_RX_HG_LNA_GC	include/ssv6200_reg.h	6947;"	d
+SET_CBR_RG_RX_HG_TZ_CAP	include/ssv6200_reg.h	6952;"	d
+SET_CBR_RG_RX_HG_TZ_GC	include/ssv6200_reg.h	6951;"	d
+SET_CBR_RG_RX_HPF300K	include/ssv6200_reg.h	6910;"	d
+SET_CBR_RG_RX_HPF3M	include/ssv6200_reg.h	6909;"	d
+SET_CBR_RG_RX_HPFI	include/ssv6200_reg.h	6911;"	d
+SET_CBR_RG_RX_HPF_FINALCORNER	include/ssv6200_reg.h	6912;"	d
+SET_CBR_RG_RX_HPF_SETTLE1_C	include/ssv6200_reg.h	6913;"	d
+SET_CBR_RG_RX_HPF_SETTLE1_R	include/ssv6200_reg.h	6914;"	d
+SET_CBR_RG_RX_HPF_SETTLE2_C	include/ssv6200_reg.h	6915;"	d
+SET_CBR_RG_RX_HPF_SETTLE2_R	include/ssv6200_reg.h	6916;"	d
+SET_CBR_RG_RX_HPF_VCMCON	include/ssv6200_reg.h	6918;"	d
+SET_CBR_RG_RX_HPF_VCMCON2	include/ssv6200_reg.h	6917;"	d
+SET_CBR_RG_RX_LG_LNAHGN_BIAS	include/ssv6200_reg.h	6960;"	d
+SET_CBR_RG_RX_LG_LNAHGP_BIAS	include/ssv6200_reg.h	6961;"	d
+SET_CBR_RG_RX_LG_LNALG_BIAS	include/ssv6200_reg.h	6962;"	d
+SET_CBR_RG_RX_LG_LNA_GC	include/ssv6200_reg.h	6959;"	d
+SET_CBR_RG_RX_LG_TZ_CAP	include/ssv6200_reg.h	6964;"	d
+SET_CBR_RG_RX_LG_TZ_GC	include/ssv6200_reg.h	6963;"	d
+SET_CBR_RG_RX_LNA_SETTLE	include/ssv6200_reg.h	6978;"	d
+SET_CBR_RG_RX_LNA_TRI_SEL	include/ssv6200_reg.h	6977;"	d
+SET_CBR_RG_RX_LOBUF	include/ssv6200_reg.h	6940;"	d
+SET_CBR_RG_RX_MG_LNAHGN_BIAS	include/ssv6200_reg.h	6954;"	d
+SET_CBR_RG_RX_MG_LNAHGP_BIAS	include/ssv6200_reg.h	6955;"	d
+SET_CBR_RG_RX_MG_LNALG_BIAS	include/ssv6200_reg.h	6956;"	d
+SET_CBR_RG_RX_MG_LNA_GC	include/ssv6200_reg.h	6953;"	d
+SET_CBR_RG_RX_MG_TZ_CAP	include/ssv6200_reg.h	6958;"	d
+SET_CBR_RG_RX_MG_TZ_GC	include/ssv6200_reg.h	6957;"	d
+SET_CBR_RG_RX_OUTVCM	include/ssv6200_reg.h	6919;"	d
+SET_CBR_RG_RX_REC_LPFCORNER	include/ssv6200_reg.h	6926;"	d
+SET_CBR_RG_RX_SQDC	include/ssv6200_reg.h	6938;"	d
+SET_CBR_RG_RX_TZI	include/ssv6200_reg.h	6920;"	d
+SET_CBR_RG_RX_TZ_OUT_TRISTATE	include/ssv6200_reg.h	6921;"	d
+SET_CBR_RG_RX_TZ_VCM	include/ssv6200_reg.h	6922;"	d
+SET_CBR_RG_RX_ULG_LNAHGN_BIAS	include/ssv6200_reg.h	6966;"	d
+SET_CBR_RG_RX_ULG_LNAHGP_BIAS	include/ssv6200_reg.h	6967;"	d
+SET_CBR_RG_RX_ULG_LNALG_BIAS	include/ssv6200_reg.h	6968;"	d
+SET_CBR_RG_RX_ULG_LNA_GC	include/ssv6200_reg.h	6965;"	d
+SET_CBR_RG_RX_ULG_TZ_CAP	include/ssv6200_reg.h	6970;"	d
+SET_CBR_RG_RX_ULG_TZ_GC	include/ssv6200_reg.h	6969;"	d
+SET_CBR_RG_SDM_PASS	include/ssv6200_reg.h	7052;"	d
+SET_CBR_RG_SEL_DPLL_CLK	include/ssv6200_reg.h	6873;"	d
+SET_CBR_RG_SX_CHP_IOST	include/ssv6200_reg.h	7029;"	d
+SET_CBR_RG_SX_CHP_IOST_POL	include/ssv6200_reg.h	7028;"	d
+SET_CBR_RG_SX_CV_CURVE_SEL	include/ssv6200_reg.h	7064;"	d
+SET_CBR_RG_SX_DELCTRL	include/ssv6200_reg.h	7082;"	d
+SET_CBR_RG_SX_DITHER_WEIGHT	include/ssv6200_reg.h	7047;"	d
+SET_CBR_RG_SX_DIVBFSEL	include/ssv6200_reg.h	7045;"	d
+SET_CBR_RG_SX_GNDR_SEL	include/ssv6200_reg.h	7046;"	d
+SET_CBR_RG_SX_LCKEN	include/ssv6200_reg.h	7059;"	d
+SET_CBR_RG_SX_LDO_CHP_LEVEL	include/ssv6200_reg.h	6890;"	d
+SET_CBR_RG_SX_LDO_LOBF_LEVEL	include/ssv6200_reg.h	6891;"	d
+SET_CBR_RG_SX_LDO_VCO_LEVEL	include/ssv6200_reg.h	6894;"	d
+SET_CBR_RG_SX_LDO_XOSC_LEVEL	include/ssv6200_reg.h	6892;"	d
+SET_CBR_RG_SX_MODDB	include/ssv6200_reg.h	7063;"	d
+SET_CBR_RG_SX_MOD_ERRCMP	include/ssv6200_reg.h	7048;"	d
+SET_CBR_RG_SX_MOD_ERR_DELAY	include/ssv6200_reg.h	7062;"	d
+SET_CBR_RG_SX_MOD_ORDER	include/ssv6200_reg.h	7049;"	d
+SET_CBR_RG_SX_PFDSEL	include/ssv6200_reg.h	7030;"	d
+SET_CBR_RG_SX_PFD_RST_H	include/ssv6200_reg.h	7035;"	d
+SET_CBR_RG_SX_PFD_SET	include/ssv6200_reg.h	7031;"	d
+SET_CBR_RG_SX_PFD_SET1	include/ssv6200_reg.h	7032;"	d
+SET_CBR_RG_SX_PFD_SET2	include/ssv6200_reg.h	7033;"	d
+SET_CBR_RG_SX_PFD_TRDN	include/ssv6200_reg.h	7037;"	d
+SET_CBR_RG_SX_PFD_TRSEL	include/ssv6200_reg.h	7038;"	d
+SET_CBR_RG_SX_PFD_TRUP	include/ssv6200_reg.h	7036;"	d
+SET_CBR_RG_SX_PH	include/ssv6200_reg.h	7069;"	d
+SET_CBR_RG_SX_PL	include/ssv6200_reg.h	7070;"	d
+SET_CBR_RG_SX_PREVDD	include/ssv6200_reg.h	7060;"	d
+SET_CBR_RG_SX_PSCONTERVDD	include/ssv6200_reg.h	7061;"	d
+SET_CBR_RG_SX_REFBYTWO	include/ssv6200_reg.h	7056;"	d
+SET_CBR_RG_SX_REF_CYCLE	include/ssv6200_reg.h	7066;"	d
+SET_CBR_RG_SX_RFCTRL_CH	include/ssv6200_reg.h	7020;"	d
+SET_CBR_RG_SX_RFCTRL_F	include/ssv6200_reg.h	7017;"	d
+SET_CBR_RG_SX_RST_H_DIV	include/ssv6200_reg.h	7053;"	d
+SET_CBR_RG_SX_RXBFSEL	include/ssv6200_reg.h	7042;"	d
+SET_CBR_RG_SX_SDMLUT_INV	include/ssv6200_reg.h	7058;"	d
+SET_CBR_RG_SX_SDM_D1	include/ssv6200_reg.h	7050;"	d
+SET_CBR_RG_SX_SDM_D2	include/ssv6200_reg.h	7051;"	d
+SET_CBR_RG_SX_SDM_EDGE	include/ssv6200_reg.h	7054;"	d
+SET_CBR_RG_SX_SEL_C3	include/ssv6200_reg.h	7021;"	d
+SET_CBR_RG_SX_SEL_CHP_REGOP	include/ssv6200_reg.h	7026;"	d
+SET_CBR_RG_SX_SEL_CHP_UNIOP	include/ssv6200_reg.h	7027;"	d
+SET_CBR_RG_SX_SEL_CP	include/ssv6200_reg.h	7018;"	d
+SET_CBR_RG_SX_SEL_CS	include/ssv6200_reg.h	7019;"	d
+SET_CBR_RG_SX_SEL_DELAY	include/ssv6200_reg.h	7065;"	d
+SET_CBR_RG_SX_SEL_ICHP	include/ssv6200_reg.h	7024;"	d
+SET_CBR_RG_SX_SEL_PCHP	include/ssv6200_reg.h	7025;"	d
+SET_CBR_RG_SX_SEL_R3	include/ssv6200_reg.h	7023;"	d
+SET_CBR_RG_SX_SEL_RS	include/ssv6200_reg.h	7022;"	d
+SET_CBR_RG_SX_SUB_SEL_CWD	include/ssv6200_reg.h	7137;"	d
+SET_CBR_RG_SX_SUB_SEL_CWR	include/ssv6200_reg.h	7136;"	d
+SET_CBR_RG_SX_TXBFSEL	include/ssv6200_reg.h	7043;"	d
+SET_CBR_RG_SX_VBNCAS_SEL	include/ssv6200_reg.h	7034;"	d
+SET_CBR_RG_SX_VCOBA_R	include/ssv6200_reg.h	7039;"	d
+SET_CBR_RG_SX_VCOBFSEL	include/ssv6200_reg.h	7044;"	d
+SET_CBR_RG_SX_VCOBY16	include/ssv6200_reg.h	7067;"	d
+SET_CBR_RG_SX_VCOBY32	include/ssv6200_reg.h	7068;"	d
+SET_CBR_RG_SX_VCOCUSEL	include/ssv6200_reg.h	7041;"	d
+SET_CBR_RG_SX_VCORSEL	include/ssv6200_reg.h	7040;"	d
+SET_CBR_RG_SX_VT_MON_MODE	include/ssv6200_reg.h	7071;"	d
+SET_CBR_RG_SX_VT_MON_TMR	include/ssv6200_reg.h	7075;"	d
+SET_CBR_RG_SX_VT_SET	include/ssv6200_reg.h	7074;"	d
+SET_CBR_RG_SX_VT_TH_HI	include/ssv6200_reg.h	7072;"	d
+SET_CBR_RG_SX_VT_TH_LO	include/ssv6200_reg.h	7073;"	d
+SET_CBR_RG_SX_XO_GM	include/ssv6200_reg.h	7055;"	d
+SET_CBR_RG_SX_XO_SWCAP	include/ssv6200_reg.h	7057;"	d
+SET_CBR_RG_TXLPF_BOOSTI	include/ssv6200_reg.h	7001;"	d
+SET_CBR_RG_TXLPF_BYPASS	include/ssv6200_reg.h	7000;"	d
+SET_CBR_RG_TXLPF_GMCELL	include/ssv6200_reg.h	6932;"	d
+SET_CBR_RG_TXMOD_GMCELL	include/ssv6200_reg.h	6931;"	d
+SET_CBR_RG_TXPGA_CAPSW	include/ssv6200_reg.h	6928;"	d
+SET_CBR_RG_TXPGA_MAIN	include/ssv6200_reg.h	6929;"	d
+SET_CBR_RG_TXPGA_STEER	include/ssv6200_reg.h	6930;"	d
+SET_CBR_RG_TX_DACLPF_ICOURSE	include/ssv6200_reg.h	6991;"	d
+SET_CBR_RG_TX_DACLPF_IFINE	include/ssv6200_reg.h	6992;"	d
+SET_CBR_RG_TX_DACLPF_VCM	include/ssv6200_reg.h	6993;"	d
+SET_CBR_RG_TX_DAC_CKEDGE_SEL	include/ssv6200_reg.h	6994;"	d
+SET_CBR_RG_TX_DAC_EN	include/ssv6200_reg.h	6851;"	d
+SET_CBR_RG_TX_DAC_IBIAS	include/ssv6200_reg.h	6995;"	d
+SET_CBR_RG_TX_DAC_OS	include/ssv6200_reg.h	6996;"	d
+SET_CBR_RG_TX_DAC_RCAL	include/ssv6200_reg.h	6997;"	d
+SET_CBR_RG_TX_DAC_TSEL	include/ssv6200_reg.h	6998;"	d
+SET_CBR_RG_TX_DIV_VSET	include/ssv6200_reg.h	6936;"	d
+SET_CBR_RG_TX_DPDGM_BIAS	include/ssv6200_reg.h	6941;"	d
+SET_CBR_RG_TX_DPD_DIV	include/ssv6200_reg.h	6942;"	d
+SET_CBR_RG_TX_EN	include/ssv6200_reg.h	6849;"	d
+SET_CBR_RG_TX_EN_VOLTAGE_IN	include/ssv6200_reg.h	6999;"	d
+SET_CBR_RG_TX_LDO_TX_LEVEL	include/ssv6200_reg.h	6895;"	d
+SET_CBR_RG_TX_LOBUF_VSET	include/ssv6200_reg.h	6937;"	d
+SET_CBR_RG_TX_PA_EN	include/ssv6200_reg.h	6850;"	d
+SET_CBR_RG_TX_TSSI_BIAS	include/ssv6200_reg.h	6943;"	d
+SET_CBR_RG_TX_TSSI_DIV	include/ssv6200_reg.h	6944;"	d
+SET_CBR_RG_TX_TSSI_TEST	include/ssv6200_reg.h	6946;"	d
+SET_CBR_RG_TX_TSSI_TESTMODE	include/ssv6200_reg.h	6945;"	d
+SET_CBR_SEL_ADCKP_INV	include/ssv6200_reg.h	7164;"	d
+SET_CBR_SEL_ADCKP_MUX	include/ssv6200_reg.h	7166;"	d
+SET_CBR_TAIL_TIME	include/ssv6200_reg.h	7161;"	d
+SET_CBR_TC_CNT_TARGET	include/ssv6200_reg.h	7156;"	d
+SET_CBR_TP_SEL	include/ssv6200_reg.h	7175;"	d
+SET_CBR_TWO_TONE_EN	include/ssv6200_reg.h	7178;"	d
+SET_CBR_TX_CNT_RST	include/ssv6200_reg.h	7152;"	d
+SET_CBR_TX_CNT_TARGET	include/ssv6200_reg.h	7155;"	d
+SET_CBR_TX_EN	include/ssv6200_reg.h	7151;"	d
+SET_CBR_VT_MON_RDY	include/ssv6200_reg.h	7142;"	d
+SET_CCCR_00H_REG	include/ssv6200_reg.h	5633;"	d
+SET_CCCR_00H_REG	smac/hal/ssv6006c/ssv6006C_reg.h	9627;"	d
+SET_CCCR_02H_REG	include/ssv6200_reg.h	5634;"	d
+SET_CCCR_02H_REG	smac/hal/ssv6006c/ssv6006C_reg.h	9628;"	d
+SET_CCCR_03H_REG	include/ssv6200_reg.h	5635;"	d
+SET_CCCR_03H_REG	smac/hal/ssv6006c/ssv6006C_reg.h	9629;"	d
+SET_CCCR_04H_REG	include/ssv6200_reg.h	5636;"	d
+SET_CCCR_04H_REG	smac/hal/ssv6006c/ssv6006C_reg.h	9630;"	d
+SET_CCCR_05H_REG	include/ssv6200_reg.h	5637;"	d
+SET_CCCR_05H_REG	smac/hal/ssv6006c/ssv6006C_reg.h	9631;"	d
+SET_CCCR_06H_REG	include/ssv6200_reg.h	5638;"	d
+SET_CCCR_06H_REG	smac/hal/ssv6006c/ssv6006C_reg.h	9632;"	d
+SET_CCCR_07H_REG	include/ssv6200_reg.h	5639;"	d
+SET_CCCR_07H_REG	smac/hal/ssv6006c/ssv6006C_reg.h	9633;"	d
+SET_CCMP_H_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	10832;"	d
+SET_CD	include/ssv6200_reg.h	5796;"	d
+SET_CD	smac/hal/ssv6006c/ssv6006C_reg.h	9787;"	d
+SET_CH0_DYN_PRI	include/ssv6200_reg.h	7398;"	d
+SET_CH0_DYN_PRI	smac/hal/ssv6006c/ssv6006C_reg.h	15842;"	d
+SET_CH0_FFO_FULL	include/ssv6200_reg.h	7320;"	d
+SET_CH0_FFO_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	15777;"	d
+SET_CH0_FULL	include/ssv6200_reg.h	7188;"	d
+SET_CH0_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	15641;"	d
+SET_CH0_FULL_ALT	smac/hal/ssv6006c/ssv6006C_reg.h	15666;"	d
+SET_CH0_INT_ADDR	include/ssv6200_reg.h	7186;"	d
+SET_CH0_INT_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	15639;"	d
+SET_CH0_LOWTHOLD	include/ssv6200_reg.h	7353;"	d
+SET_CH0_LOWTHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	15810;"	d
+SET_CH0_LOWTHOLD_INT	include/ssv6200_reg.h	7336;"	d
+SET_CH0_LOWTHOLD_INT	smac/hal/ssv6006c/ssv6006C_reg.h	15793;"	d
+SET_CH0_NVLD	include/ssv6200_reg.h	7422;"	d
+SET_CH0_NVLD	smac/hal/ssv6006c/ssv6006C_reg.h	15866;"	d
+SET_CH0_QUEUE_FLUSH	include/ssv6200_reg.h	7288;"	d
+SET_CH0_REQ_LOCK	include/ssv6200_reg.h	7413;"	d
+SET_CH0_REQ_LOCK	smac/hal/ssv6006c/ssv6006C_reg.h	15857;"	d
+SET_CH0_STA_PRI	include/ssv6200_reg.h	7400;"	d
+SET_CH0_STA_PRI	smac/hal/ssv6006c/ssv6006C_reg.h	15844;"	d
+SET_CH0_WRFF_FLUSH	include/ssv6200_reg.h	7373;"	d
+SET_CH10_FFO_FULL	include/ssv6200_reg.h	7330;"	d
+SET_CH10_FFO_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	15787;"	d
+SET_CH10_FULL	include/ssv6200_reg.h	7220;"	d
+SET_CH10_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	15676;"	d
+SET_CH10_HALT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	15709;"	d
+SET_CH10_LOWTHOLD	include/ssv6200_reg.h	7363;"	d
+SET_CH10_LOWTHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	15820;"	d
+SET_CH10_LOWTHOLD_INT	include/ssv6200_reg.h	7346;"	d
+SET_CH10_LOWTHOLD_INT	smac/hal/ssv6006c/ssv6006C_reg.h	15803;"	d
+SET_CH10_QUEUE_FLUSH	include/ssv6200_reg.h	7298;"	d
+SET_CH10_WRFF_FLUSH	include/ssv6200_reg.h	7383;"	d
+SET_CH11_FFO_FULL	include/ssv6200_reg.h	7331;"	d
+SET_CH11_FFO_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	15788;"	d
+SET_CH11_FULL	include/ssv6200_reg.h	7221;"	d
+SET_CH11_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	15677;"	d
+SET_CH11_HALT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	15710;"	d
+SET_CH11_LOWTHOLD	include/ssv6200_reg.h	7364;"	d
+SET_CH11_LOWTHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	15821;"	d
+SET_CH11_LOWTHOLD_INT	include/ssv6200_reg.h	7347;"	d
+SET_CH11_LOWTHOLD_INT	smac/hal/ssv6006c/ssv6006C_reg.h	15804;"	d
+SET_CH11_QUEUE_FLUSH	include/ssv6200_reg.h	7299;"	d
+SET_CH11_WRFF_FLUSH	include/ssv6200_reg.h	7384;"	d
+SET_CH12_FFO_FULL	include/ssv6200_reg.h	7332;"	d
+SET_CH12_FFO_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	15789;"	d
+SET_CH12_FULL	include/ssv6200_reg.h	7222;"	d
+SET_CH12_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	15678;"	d
+SET_CH12_HALT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	15711;"	d
+SET_CH12_LOWTHOLD	include/ssv6200_reg.h	7365;"	d
+SET_CH12_LOWTHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	15822;"	d
+SET_CH12_LOWTHOLD_INT	include/ssv6200_reg.h	7348;"	d
+SET_CH12_LOWTHOLD_INT	smac/hal/ssv6006c/ssv6006C_reg.h	15805;"	d
+SET_CH12_QUEUE_FLUSH	include/ssv6200_reg.h	7300;"	d
+SET_CH12_WRFF_FLUSH	include/ssv6200_reg.h	7385;"	d
+SET_CH13_FFO_FULL	include/ssv6200_reg.h	7333;"	d
+SET_CH13_FFO_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	15790;"	d
+SET_CH13_FULL	include/ssv6200_reg.h	7223;"	d
+SET_CH13_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	15679;"	d
+SET_CH13_HALT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	15712;"	d
+SET_CH13_LOWTHOLD	include/ssv6200_reg.h	7366;"	d
+SET_CH13_LOWTHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	15823;"	d
+SET_CH13_LOWTHOLD_INT	include/ssv6200_reg.h	7349;"	d
+SET_CH13_LOWTHOLD_INT	smac/hal/ssv6006c/ssv6006C_reg.h	15806;"	d
+SET_CH13_QUEUE_FLUSH	include/ssv6200_reg.h	7301;"	d
+SET_CH13_WRFF_FLUSH	include/ssv6200_reg.h	7386;"	d
+SET_CH14_FFO_FULL	include/ssv6200_reg.h	7334;"	d
+SET_CH14_FFO_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	15791;"	d
+SET_CH14_FULL	include/ssv6200_reg.h	7224;"	d
+SET_CH14_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	15680;"	d
+SET_CH14_HALT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	15713;"	d
+SET_CH14_LOWTHOLD	include/ssv6200_reg.h	7367;"	d
+SET_CH14_LOWTHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	15824;"	d
+SET_CH14_LOWTHOLD_INT	include/ssv6200_reg.h	7350;"	d
+SET_CH14_LOWTHOLD_INT	smac/hal/ssv6006c/ssv6006C_reg.h	15807;"	d
+SET_CH14_QUEUE_FLUSH	include/ssv6200_reg.h	7302;"	d
+SET_CH14_WRFF_FLUSH	include/ssv6200_reg.h	7387;"	d
+SET_CH15_FFO_FULL	include/ssv6200_reg.h	7335;"	d
+SET_CH15_FFO_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	15792;"	d
+SET_CH15_FULL	include/ssv6200_reg.h	7225;"	d
+SET_CH15_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	15681;"	d
+SET_CH15_LOWTHOLD	include/ssv6200_reg.h	7368;"	d
+SET_CH15_LOWTHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	15825;"	d
+SET_CH15_LOWTHOLD_INT	include/ssv6200_reg.h	7351;"	d
+SET_CH15_LOWTHOLD_INT	smac/hal/ssv6006c/ssv6006C_reg.h	15808;"	d
+SET_CH15_QUEUE_FLUSH	include/ssv6200_reg.h	7303;"	d
+SET_CH1_FFO_FULL	include/ssv6200_reg.h	7321;"	d
+SET_CH1_FFO_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	15778;"	d
+SET_CH1_FULL	include/ssv6200_reg.h	7211;"	d
+SET_CH1_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	15667;"	d
+SET_CH1_HALT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	15701;"	d
+SET_CH1_LOWTHOLD	include/ssv6200_reg.h	7354;"	d
+SET_CH1_LOWTHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	15811;"	d
+SET_CH1_LOWTHOLD_INT	include/ssv6200_reg.h	7337;"	d
+SET_CH1_LOWTHOLD_INT	smac/hal/ssv6006c/ssv6006C_reg.h	15794;"	d
+SET_CH1_NVLD	include/ssv6200_reg.h	7423;"	d
+SET_CH1_NVLD	smac/hal/ssv6006c/ssv6006C_reg.h	15867;"	d
+SET_CH1_PRI	include/ssv6200_reg.h	6653;"	d
+SET_CH1_PRI	smac/hal/ssv6006c/ssv6006C_reg.h	10749;"	d
+SET_CH1_QUEUE_FLUSH	include/ssv6200_reg.h	7289;"	d
+SET_CH1_REQ_LOCK	include/ssv6200_reg.h	7414;"	d
+SET_CH1_REQ_LOCK	smac/hal/ssv6006c/ssv6006C_reg.h	15858;"	d
+SET_CH1_STA_PRI	include/ssv6200_reg.h	7401;"	d
+SET_CH1_STA_PRI	smac/hal/ssv6006c/ssv6006C_reg.h	15845;"	d
+SET_CH1_WRFF_FLUSH	include/ssv6200_reg.h	7374;"	d
+SET_CH2_FFO_FULL	include/ssv6200_reg.h	7322;"	d
+SET_CH2_FFO_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	15779;"	d
+SET_CH2_FULL	include/ssv6200_reg.h	7212;"	d
+SET_CH2_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	15643;"	d
+SET_CH2_FULL_ALT	smac/hal/ssv6006c/ssv6006C_reg.h	15668;"	d
+SET_CH2_INT_ADDR_ALT	smac/hal/ssv6006c/ssv6006C_reg.h	15683;"	d
+SET_CH2_LOWTHOLD	include/ssv6200_reg.h	7355;"	d
+SET_CH2_LOWTHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	15812;"	d
+SET_CH2_LOWTHOLD_INT	include/ssv6200_reg.h	7338;"	d
+SET_CH2_LOWTHOLD_INT	smac/hal/ssv6006c/ssv6006C_reg.h	15795;"	d
+SET_CH2_NVLD	include/ssv6200_reg.h	7424;"	d
+SET_CH2_NVLD	smac/hal/ssv6006c/ssv6006C_reg.h	15868;"	d
+SET_CH2_PRI	include/ssv6200_reg.h	6654;"	d
+SET_CH2_PRI	smac/hal/ssv6006c/ssv6006C_reg.h	10750;"	d
+SET_CH2_QUEUE_FLUSH	include/ssv6200_reg.h	7290;"	d
+SET_CH2_REQ_LOCK	include/ssv6200_reg.h	7415;"	d
+SET_CH2_REQ_LOCK	smac/hal/ssv6006c/ssv6006C_reg.h	15859;"	d
+SET_CH2_STA_PRI	include/ssv6200_reg.h	7402;"	d
+SET_CH2_STA_PRI	smac/hal/ssv6006c/ssv6006C_reg.h	15846;"	d
+SET_CH2_WRFF_FLUSH	include/ssv6200_reg.h	7375;"	d
+SET_CH3_FFO_FULL	include/ssv6200_reg.h	7323;"	d
+SET_CH3_FFO_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	15780;"	d
+SET_CH3_FULL	include/ssv6200_reg.h	7213;"	d
+SET_CH3_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	15669;"	d
+SET_CH3_HALT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	15702;"	d
+SET_CH3_LOWTHOLD	include/ssv6200_reg.h	7356;"	d
+SET_CH3_LOWTHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	15813;"	d
+SET_CH3_LOWTHOLD_INT	include/ssv6200_reg.h	7339;"	d
+SET_CH3_LOWTHOLD_INT	smac/hal/ssv6006c/ssv6006C_reg.h	15796;"	d
+SET_CH3_NVLD	include/ssv6200_reg.h	7425;"	d
+SET_CH3_NVLD	smac/hal/ssv6006c/ssv6006C_reg.h	15869;"	d
+SET_CH3_PRI	include/ssv6200_reg.h	6655;"	d
+SET_CH3_PRI	smac/hal/ssv6006c/ssv6006C_reg.h	10751;"	d
+SET_CH3_QUEUE_FLUSH	include/ssv6200_reg.h	7291;"	d
+SET_CH3_REQ_LOCK	include/ssv6200_reg.h	7416;"	d
+SET_CH3_REQ_LOCK	smac/hal/ssv6006c/ssv6006C_reg.h	15860;"	d
+SET_CH3_STA_PRI	include/ssv6200_reg.h	7403;"	d
+SET_CH3_STA_PRI	smac/hal/ssv6006c/ssv6006C_reg.h	15847;"	d
+SET_CH3_WRFF_FLUSH	include/ssv6200_reg.h	7376;"	d
+SET_CH4_FFO_FULL	include/ssv6200_reg.h	7324;"	d
+SET_CH4_FFO_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	15781;"	d
+SET_CH4_FULL	include/ssv6200_reg.h	7214;"	d
+SET_CH4_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	15670;"	d
+SET_CH4_HALT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	15703;"	d
+SET_CH4_LOWTHOLD	include/ssv6200_reg.h	7357;"	d
+SET_CH4_LOWTHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	15814;"	d
+SET_CH4_LOWTHOLD_INT	include/ssv6200_reg.h	7340;"	d
+SET_CH4_LOWTHOLD_INT	smac/hal/ssv6006c/ssv6006C_reg.h	15797;"	d
+SET_CH4_QUEUE_FLUSH	include/ssv6200_reg.h	7292;"	d
+SET_CH4_WRFF_FLUSH	include/ssv6200_reg.h	7377;"	d
+SET_CH5_FFO_FULL	include/ssv6200_reg.h	7325;"	d
+SET_CH5_FFO_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	15782;"	d
+SET_CH5_FULL	include/ssv6200_reg.h	7215;"	d
+SET_CH5_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	15671;"	d
+SET_CH5_HALT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	15704;"	d
+SET_CH5_LOWTHOLD	include/ssv6200_reg.h	7358;"	d
+SET_CH5_LOWTHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	15815;"	d
+SET_CH5_LOWTHOLD_INT	include/ssv6200_reg.h	7341;"	d
+SET_CH5_LOWTHOLD_INT	smac/hal/ssv6006c/ssv6006C_reg.h	15798;"	d
+SET_CH5_QUEUE_FLUSH	include/ssv6200_reg.h	7293;"	d
+SET_CH5_WRFF_FLUSH	include/ssv6200_reg.h	7378;"	d
+SET_CH6_FFO_FULL	include/ssv6200_reg.h	7326;"	d
+SET_CH6_FFO_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	15783;"	d
+SET_CH6_FULL	include/ssv6200_reg.h	7216;"	d
+SET_CH6_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	15672;"	d
+SET_CH6_HALT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	15705;"	d
+SET_CH6_LOWTHOLD	include/ssv6200_reg.h	7359;"	d
+SET_CH6_LOWTHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	15816;"	d
+SET_CH6_LOWTHOLD_INT	include/ssv6200_reg.h	7342;"	d
+SET_CH6_LOWTHOLD_INT	smac/hal/ssv6006c/ssv6006C_reg.h	15799;"	d
+SET_CH6_QUEUE_FLUSH	include/ssv6200_reg.h	7294;"	d
+SET_CH6_WRFF_FLUSH	include/ssv6200_reg.h	7379;"	d
+SET_CH7_FFO_FULL	include/ssv6200_reg.h	7327;"	d
+SET_CH7_FFO_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	15784;"	d
+SET_CH7_FULL	include/ssv6200_reg.h	7217;"	d
+SET_CH7_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	15673;"	d
+SET_CH7_HALT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	15706;"	d
+SET_CH7_LOWTHOLD	include/ssv6200_reg.h	7360;"	d
+SET_CH7_LOWTHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	15817;"	d
+SET_CH7_LOWTHOLD_INT	include/ssv6200_reg.h	7343;"	d
+SET_CH7_LOWTHOLD_INT	smac/hal/ssv6006c/ssv6006C_reg.h	15800;"	d
+SET_CH7_QUEUE_FLUSH	include/ssv6200_reg.h	7295;"	d
+SET_CH7_WRFF_FLUSH	include/ssv6200_reg.h	7380;"	d
+SET_CH8_FFO_FULL	include/ssv6200_reg.h	7328;"	d
+SET_CH8_FFO_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	15785;"	d
+SET_CH8_FULL	include/ssv6200_reg.h	7218;"	d
+SET_CH8_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	15674;"	d
+SET_CH8_HALT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	15707;"	d
+SET_CH8_LOWTHOLD	include/ssv6200_reg.h	7361;"	d
+SET_CH8_LOWTHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	15818;"	d
+SET_CH8_LOWTHOLD_INT	include/ssv6200_reg.h	7344;"	d
+SET_CH8_LOWTHOLD_INT	smac/hal/ssv6006c/ssv6006C_reg.h	15801;"	d
+SET_CH8_QUEUE_FLUSH	include/ssv6200_reg.h	7296;"	d
+SET_CH8_WRFF_FLUSH	include/ssv6200_reg.h	7381;"	d
+SET_CH9_FFO_FULL	include/ssv6200_reg.h	7329;"	d
+SET_CH9_FFO_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	15786;"	d
+SET_CH9_FULL	include/ssv6200_reg.h	7219;"	d
+SET_CH9_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	15675;"	d
+SET_CH9_HALT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	15708;"	d
+SET_CH9_LOWTHOLD	include/ssv6200_reg.h	7362;"	d
+SET_CH9_LOWTHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	15819;"	d
+SET_CH9_LOWTHOLD_INT	include/ssv6200_reg.h	7345;"	d
+SET_CH9_LOWTHOLD_INT	smac/hal/ssv6006c/ssv6006C_reg.h	15802;"	d
+SET_CH9_QUEUE_FLUSH	include/ssv6200_reg.h	7297;"	d
+SET_CH9_WRFF_FLUSH	include/ssv6200_reg.h	7382;"	d
+SET_CHECK_SUM	include/ssv6200_reg.h	6178;"	d
+SET_CHECK_SUM	smac/hal/ssv6006c/ssv6006C_reg.h	10196;"	d
+SET_CHECK_SUM_FAIL	include/ssv6200_reg.h	6035;"	d
+SET_CHECK_SUM_TAG	include/ssv6200_reg.h	6054;"	d
+SET_CHIP_DATE_00HHMMSS	smac/hal/ssv6006c/ssv6006C_reg.h	9392;"	d
+SET_CHIP_DATE_YYYYMMDD	smac/hal/ssv6006c/ssv6006C_reg.h	9391;"	d
+SET_CHIP_GITSHA_127_96	smac/hal/ssv6006c/ssv6006C_reg.h	9396;"	d
+SET_CHIP_GITSHA_159_128	smac/hal/ssv6006c/ssv6006C_reg.h	9397;"	d
+SET_CHIP_GITSHA_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	9393;"	d
+SET_CHIP_GITSHA_63_32	smac/hal/ssv6006c/ssv6006C_reg.h	9394;"	d
+SET_CHIP_GITSHA_95_64	smac/hal/ssv6006c/ssv6006C_reg.h	9395;"	d
+SET_CHIP_ID_127_96	include/ssv6200_reg.h	4938;"	d
+SET_CHIP_ID_127_96	smac/hal/ssv6006c/ssv6006C_reg.h	9297;"	d
+SET_CHIP_ID_31_0	include/ssv6200_reg.h	4935;"	d
+SET_CHIP_ID_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	9294;"	d
+SET_CHIP_ID_63_32	include/ssv6200_reg.h	4936;"	d
+SET_CHIP_ID_63_32	smac/hal/ssv6006c/ssv6006C_reg.h	9295;"	d
+SET_CHIP_ID_95_64	include/ssv6200_reg.h	4937;"	d
+SET_CHIP_ID_95_64	smac/hal/ssv6006c/ssv6006C_reg.h	9296;"	d
+SET_CHIP_INFO_FPGA_TAG	smac/hal/ssv6006c/ssv6006C_reg.h	9401;"	d
+SET_CHIP_INFO_ID_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	9387;"	d
+SET_CHIP_INFO_ID_63_32	smac/hal/ssv6006c/ssv6006C_reg.h	9388;"	d
+SET_CHIP_TYPE	smac/hal/ssv6006c/ssv6006C_reg.h	9390;"	d
+SET_CHIP_VER	smac/hal/ssv6006c/ssv6006C_reg.h	9389;"	d
+SET_CH_ARB_EN	include/ssv6200_reg.h	7456;"	d
+SET_CH_ARB_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15900;"	d
+SET_CH_PRI1	include/ssv6200_reg.h	7457;"	d
+SET_CH_PRI1	smac/hal/ssv6006c/ssv6006C_reg.h	15901;"	d
+SET_CH_PRI2	include/ssv6200_reg.h	7458;"	d
+SET_CH_PRI2	smac/hal/ssv6006c/ssv6006C_reg.h	15902;"	d
+SET_CH_PRI3	include/ssv6200_reg.h	7459;"	d
+SET_CH_PRI3	smac/hal/ssv6006c/ssv6006C_reg.h	15903;"	d
+SET_CH_PRI4	include/ssv6200_reg.h	7460;"	d
+SET_CH_PRI4	smac/hal/ssv6006c/ssv6006C_reg.h	15904;"	d
+SET_CH_STA0_DUR	include/ssv6200_reg.h	6462;"	d
+SET_CH_STA1_DUR	include/ssv6200_reg.h	6473;"	d
+SET_CH_STA2_DUR	include/ssv6200_reg.h	6474;"	d
+SET_CH_STA3_DUR	include/ssv6200_reg.h	6480;"	d
+SET_CH_STA4_DUR	include/ssv6200_reg.h	6481;"	d
+SET_CH_ST_FSM	include/ssv6200_reg.h	6445;"	d
+SET_CK_SEL_1_0	include/ssv6200_reg.h	4939;"	d
+SET_CK_SEL_2	include/ssv6200_reg.h	4940;"	d
+SET_CLK_DIGI_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	9298;"	d
+SET_CLK_EN_160M_PHY	smac/hal/ssv6006c/ssv6006C_reg.h	9333;"	d
+SET_CLK_EN_CPUN10	smac/hal/ssv6006c/ssv6006C_reg.h	9383;"	d
+SET_CLK_EN_MBIST	smac/hal/ssv6006c/ssv6006C_reg.h	9335;"	d
+SET_CLK_EN_PHYRF40M	smac/hal/ssv6006c/ssv6006C_reg.h	9331;"	d
+SET_CLK_EN_PHYRF80M	smac/hal/ssv6006c/ssv6006C_reg.h	9332;"	d
+SET_CLK_EN_USB_CTRLUTMI	smac/hal/ssv6006c/ssv6006C_reg.h	9327;"	d
+SET_CLK_EN_USB_PHY30M	smac/hal/ssv6006c/ssv6006C_reg.h	9326;"	d
+SET_CLK_FBUS_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	9353;"	d
+SET_CLK_USB_PHY30M_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	9299;"	d
+SET_CLK_WIDTH	include/ssv6200_reg.h	5694;"	d
+SET_CLK_WIDTH	smac/hal/ssv6006c/ssv6006C_reg.h	9686;"	d
+SET_CLR	include/ssv6200_reg.h	6190;"	d
+SET_CLR	smac/hal/ssv6006c/ssv6006C_reg.h	10208;"	d
+SET_CMD52_ABORT_ACTIVE	include/ssv6200_reg.h	5542;"	d
+SET_CMD52_ABORT_RESPONSE	include/ssv6200_reg.h	5537;"	d
+SET_CMD52_ABORT_RESPONSE	smac/hal/ssv6006c/ssv6006C_reg.h	9600;"	d
+SET_CMD52_RD_ABORT_CNT	include/ssv6200_reg.h	5594;"	d
+SET_CMD52_RESET_ACTIVE	include/ssv6200_reg.h	5543;"	d
+SET_CMD52_WR_ABORT_CNT	include/ssv6200_reg.h	5595;"	d
+SET_CMD_ADDR	include/ssv6200_reg.h	6056;"	d
+SET_CMD_LEN	include/ssv6200_reg.h	6055;"	d
+SET_CMD_LEN_SPIMAS	smac/hal/ssv6006c/ssv6006C_reg.h	10278;"	d
+SET_CMD_LOG_PART1	include/ssv6200_reg.h	5626;"	d
+SET_CMD_LOG_PART2	include/ssv6200_reg.h	5627;"	d
+SET_COEXIST_EN	include/ssv6200_reg.h	6747;"	d
+SET_COEXIST_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10850;"	d
+SET_COMMAND_COUNTER	include/ssv6200_reg.h	5625;"	d
+SET_COMMON_CIS_PONTER	include/ssv6200_reg.h	5648;"	d
+SET_COMMON_CIS_PONTER	smac/hal/ssv6006c/ssv6006C_reg.h	9642;"	d
+SET_CONDI_NUM	include/ssv6200_reg.h	5690;"	d
+SET_CONTINUE_R_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9886;"	d
+SET_CORRECT_RATE_REP_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	10174;"	d
+SET_CO_PROC_CLK_EN	include/ssv6200_reg.h	6701;"	d
+SET_CO_PROC_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10797;"	d
+SET_CO_PROC_CSR_CLK_EN	include/ssv6200_reg.h	6722;"	d
+SET_CO_PROC_CSR_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10818;"	d
+SET_CO_PROC_CSR_RST	include/ssv6200_reg.h	6687;"	d
+SET_CO_PROC_CSR_RST	smac/hal/ssv6006c/ssv6006C_reg.h	10783;"	d
+SET_CO_PROC_ENG_CLK_EN	include/ssv6200_reg.h	6713;"	d
+SET_CO_PROC_ENG_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10809;"	d
+SET_CO_PROC_ENG_RST	include/ssv6200_reg.h	6676;"	d
+SET_CO_PROC_ENG_RST	smac/hal/ssv6006c/ssv6006C_reg.h	10772;"	d
+SET_CO_PROC_SW_RST	include/ssv6200_reg.h	6664;"	d
+SET_CO_PROC_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	10759;"	d
+SET_CPHA	smac/hal/ssv6006c/ssv6006C_reg.h	10269;"	d
+SET_CPOL	smac/hal/ssv6006c/ssv6006C_reg.h	10268;"	d
+SET_CPU_ID_TB0	include/ssv6200_reg.h	7183;"	d
+SET_CPU_ID_TB0	smac/hal/ssv6006c/ssv6006C_reg.h	15636;"	d
+SET_CPU_ID_TB1	include/ssv6200_reg.h	7184;"	d
+SET_CPU_ID_TB1	smac/hal/ssv6006c/ssv6006C_reg.h	15637;"	d
+SET_CPU_ID_TB2	include/ssv6200_reg.h	7388;"	d
+SET_CPU_ID_TB2	smac/hal/ssv6006c/ssv6006C_reg.h	15833;"	d
+SET_CPU_ID_TB3	include/ssv6200_reg.h	7389;"	d
+SET_CPU_ID_TB3	smac/hal/ssv6006c/ssv6006C_reg.h	15834;"	d
+SET_CPU_INT	include/ssv6200_reg.h	7182;"	d
+SET_CPU_INT	smac/hal/ssv6006c/ssv6006C_reg.h	15635;"	d
+SET_CPU_INT_ALT	smac/hal/ssv6006c/ssv6006C_reg.h	15633;"	d
+SET_CPU_POR0	include/ssv6200_reg.h	8456;"	d
+SET_CPU_POR1	include/ssv6200_reg.h	8457;"	d
+SET_CPU_POR2	include/ssv6200_reg.h	8458;"	d
+SET_CPU_POR3	include/ssv6200_reg.h	8459;"	d
+SET_CPU_POR4	include/ssv6200_reg.h	8460;"	d
+SET_CPU_POR5	include/ssv6200_reg.h	8461;"	d
+SET_CPU_POR6	include/ssv6200_reg.h	8462;"	d
+SET_CPU_POR7	include/ssv6200_reg.h	8463;"	d
+SET_CPU_POR8	include/ssv6200_reg.h	8464;"	d
+SET_CPU_POR9	include/ssv6200_reg.h	8465;"	d
+SET_CPU_PORA	include/ssv6200_reg.h	8466;"	d
+SET_CPU_PORB	include/ssv6200_reg.h	8467;"	d
+SET_CPU_PORC	include/ssv6200_reg.h	8468;"	d
+SET_CPU_PORD	include/ssv6200_reg.h	8469;"	d
+SET_CPU_PORE	include/ssv6200_reg.h	8470;"	d
+SET_CPU_PORF	include/ssv6200_reg.h	8471;"	d
+SET_CPU_QUE_POP	include/ssv6200_reg.h	7181;"	d
+SET_CPU_QUE_POP	smac/hal/ssv6006c/ssv6006C_reg.h	15634;"	d
+SET_CPU_QUE_POP_ALT	smac/hal/ssv6006c/ssv6006C_reg.h	15632;"	d
+SET_CRC_CNT	include/ssv6200_reg.h	7822;"	d
+SET_CRC_CORRECT	include/ssv6200_reg.h	7832;"	d
+SET_CRYSTAL_OUT_REQ_SEL	include/ssv6200_reg.h	5492;"	d
+SET_CSASUPPORT	include/ssv6200_reg.h	5652;"	d
+SET_CSASUPPORT	smac/hal/ssv6006c/ssv6006C_reg.h	9648;"	d
+SET_CSN_DLY	smac/hal/ssv6006c/ssv6006C_reg.h	9877;"	d
+SET_CSN_INTER	include/ssv6200_reg.h	5695;"	d
+SET_CSN_INTER	smac/hal/ssv6006c/ssv6006C_reg.h	9687;"	d
+SET_CSPOL	smac/hal/ssv6006c/ssv6006C_reg.h	10270;"	d
+SET_CSR_PHY_INFO	include/ssv6200_reg.h	6379;"	d
+SET_CSR_PHY_INFO	smac/hal/ssv6006c/ssv6006C_reg.h	10379;"	d
+SET_CSTATE	include/ssv6200_reg.h	7952;"	d
+SET_CS_ADDER_EN	include/ssv6200_reg.h	6173;"	d
+SET_CS_ADDER_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10191;"	d
+SET_CS_PKT_ID	include/ssv6200_reg.h	6171;"	d
+SET_CS_PKT_ID	smac/hal/ssv6006c/ssv6006C_reg.h	10189;"	d
+SET_CS_START_ADDR	include/ssv6200_reg.h	6170;"	d
+SET_CS_START_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	10188;"	d
+SET_CTS	include/ssv6200_reg.h	5793;"	d
+SET_CTS	smac/hal/ssv6006c/ssv6006C_reg.h	9784;"	d
+SET_CTYPE_RATE_RPT	smac/hal/ssv6006c/ssv6006C_reg.h	10476;"	d
+SET_D2_DMA_ADR_DST	include/ssv6200_reg.h	6100;"	d
+SET_D2_DMA_ADR_DST	smac/hal/ssv6006c/ssv6006C_reg.h	9925;"	d
+SET_D2_DMA_ADR_SRC	include/ssv6200_reg.h	6099;"	d
+SET_D2_DMA_ADR_SRC	smac/hal/ssv6006c/ssv6006C_reg.h	9924;"	d
+SET_D2_DMA_BADR_EN	include/ssv6200_reg.h	6107;"	d
+SET_D2_DMA_BADR_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9932;"	d
+SET_D2_DMA_CONST	include/ssv6200_reg.h	6112;"	d
+SET_D2_DMA_CONST	smac/hal/ssv6006c/ssv6006C_reg.h	9937;"	d
+SET_D2_DMA_DST_INC	include/ssv6200_reg.h	6104;"	d
+SET_D2_DMA_DST_INC	smac/hal/ssv6006c/ssv6006C_reg.h	9929;"	d
+SET_D2_DMA_DST_SIZE	include/ssv6200_reg.h	6103;"	d
+SET_D2_DMA_DST_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	9928;"	d
+SET_D2_DMA_FAST_FILL	include/ssv6200_reg.h	6105;"	d
+SET_D2_DMA_FAST_FILL	smac/hal/ssv6006c/ssv6006C_reg.h	9930;"	d
+SET_D2_DMA_FINISH	include/ssv6200_reg.h	6111;"	d
+SET_D2_DMA_FINISH	smac/hal/ssv6006c/ssv6006C_reg.h	9936;"	d
+SET_D2_DMA_INT_MASK	include/ssv6200_reg.h	6109;"	d
+SET_D2_DMA_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	9934;"	d
+SET_D2_DMA_LEN	include/ssv6200_reg.h	6108;"	d
+SET_D2_DMA_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	9933;"	d
+SET_D2_DMA_SDIO_KICK	include/ssv6200_reg.h	6106;"	d
+SET_D2_DMA_SDIO_KICK	smac/hal/ssv6006c/ssv6006C_reg.h	9931;"	d
+SET_D2_DMA_SRC_INC	include/ssv6200_reg.h	6102;"	d
+SET_D2_DMA_SRC_INC	smac/hal/ssv6006c/ssv6006C_reg.h	9927;"	d
+SET_D2_DMA_SRC_SIZE	include/ssv6200_reg.h	6101;"	d
+SET_D2_DMA_SRC_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	9926;"	d
+SET_D2_DMA_STS	include/ssv6200_reg.h	6110;"	d
+SET_D2_DMA_STS	smac/hal/ssv6006c/ssv6006C_reg.h	9935;"	d
+SET_DATA_FRAMES	smac/hal/ssv6006c/ssv6006C_reg.h	9243;"	d
+SET_DATA_RATE	include/ssv6200_reg.h	6194;"	d
+SET_DATA_RATE	smac/hal/ssv6006c/ssv6006C_reg.h	10212;"	d
+SET_DATA_RDY	include/ssv6200_reg.h	5781;"	d
+SET_DATA_RDY	smac/hal/ssv6006c/ssv6006C_reg.h	9772;"	d
+SET_DATA_RDY_IE	include/ssv6200_reg.h	5756;"	d
+SET_DATA_RDY_IE	smac/hal/ssv6006c/ssv6006C_reg.h	9746;"	d
+SET_DATA_SPI_RESET	smac/hal/ssv6006c/ssv6006C_reg.h	9410;"	d
+SET_DATA_SPI_WAKEUP	smac/hal/ssv6006c/ssv6006C_reg.h	9404;"	d
+SET_DATA_UART_W2B_EN	include/ssv6200_reg.h	4992;"	d
+SET_DAT_BRDC_DIV	include/ssv6200_reg.h	5844;"	d
+SET_DAT_BREAK_INT	include/ssv6200_reg.h	5832;"	d
+SET_DAT_CD	include/ssv6200_reg.h	5843;"	d
+SET_DAT_CTS	include/ssv6200_reg.h	5840;"	d
+SET_DAT_DATA_RDY	include/ssv6200_reg.h	5828;"	d
+SET_DAT_DATA_RDY_IE	include/ssv6200_reg.h	5803;"	d
+SET_DAT_DELTA_CD	include/ssv6200_reg.h	5839;"	d
+SET_DAT_DELTA_CTS	include/ssv6200_reg.h	5836;"	d
+SET_DAT_DELTA_DSR	include/ssv6200_reg.h	5837;"	d
+SET_DAT_DLAB	include/ssv6200_reg.h	5822;"	d
+SET_DAT_DMA_MODE	include/ssv6200_reg.h	5812;"	d
+SET_DAT_DMA_RXEND_IE	include/ssv6200_reg.h	5807;"	d
+SET_DAT_DMA_TXEND_IE	include/ssv6200_reg.h	5808;"	d
+SET_DAT_DSR	include/ssv6200_reg.h	5841;"	d
+SET_DAT_DTR	include/ssv6200_reg.h	5823;"	d
+SET_DAT_EN_AUTO_CTS	include/ssv6200_reg.h	5814;"	d
+SET_DAT_EN_AUTO_RTS	include/ssv6200_reg.h	5813;"	d
+SET_DAT_EVEN_PARITY	include/ssv6200_reg.h	5819;"	d
+SET_DAT_FIFODATA_ERR	include/ssv6200_reg.h	5835;"	d
+SET_DAT_FIFOS_ENABLED	include/ssv6200_reg.h	5848;"	d
+SET_DAT_FIFO_EN	include/ssv6200_reg.h	5809;"	d
+SET_DAT_FORCE_PARITY	include/ssv6200_reg.h	5820;"	d
+SET_DAT_FRAMING_ERR	include/ssv6200_reg.h	5831;"	d
+SET_DAT_INT_IDCODE	include/ssv6200_reg.h	5847;"	d
+SET_DAT_LOOP_BACK	include/ssv6200_reg.h	5827;"	d
+SET_DAT_MDM_STS_IE	include/ssv6200_reg.h	5806;"	d
+SET_DAT_MODE_OFF	include/ssv6200_reg.h	5723;"	d
+SET_DAT_OUT_1	include/ssv6200_reg.h	5825;"	d
+SET_DAT_OUT_2	include/ssv6200_reg.h	5826;"	d
+SET_DAT_OUT_EDGE	include/ssv6200_reg.h	5573;"	d
+SET_DAT_OVERRUN_ERR	include/ssv6200_reg.h	5829;"	d
+SET_DAT_PARITY_EN	include/ssv6200_reg.h	5818;"	d
+SET_DAT_PARITY_ERR	include/ssv6200_reg.h	5830;"	d
+SET_DAT_RI	include/ssv6200_reg.h	5842;"	d
+SET_DAT_RTHR_H	include/ssv6200_reg.h	5846;"	d
+SET_DAT_RTHR_L	include/ssv6200_reg.h	5845;"	d
+SET_DAT_RTS	include/ssv6200_reg.h	5824;"	d
+SET_DAT_RXFIFO_RST	include/ssv6200_reg.h	5810;"	d
+SET_DAT_RXFIFO_TRGLVL	include/ssv6200_reg.h	5815;"	d
+SET_DAT_RX_LINESTS_IE	include/ssv6200_reg.h	5805;"	d
+SET_DAT_SET_BREAK	include/ssv6200_reg.h	5821;"	d
+SET_DAT_STOP_BIT	include/ssv6200_reg.h	5817;"	d
+SET_DAT_THR_EMPTY	include/ssv6200_reg.h	5833;"	d
+SET_DAT_THR_EMPTY_IE	include/ssv6200_reg.h	5804;"	d
+SET_DAT_TRAILEDGE_RI	include/ssv6200_reg.h	5838;"	d
+SET_DAT_TXFIFO_RST	include/ssv6200_reg.h	5811;"	d
+SET_DAT_TX_EMPTY	include/ssv6200_reg.h	5834;"	d
+SET_DAT_UART_DATA	include/ssv6200_reg.h	5802;"	d
+SET_DAT_UART_MULTI_IRQ	include/ssv6200_reg.h	5914;"	d
+SET_DAT_UART_MULTI_IRQ_SD	include/ssv6200_reg.h	5983;"	d
+SET_DAT_UART_NCTS_SEL	include/ssv6200_reg.h	5497;"	d
+SET_DAT_UART_RXD_SEL_0	include/ssv6200_reg.h	5507;"	d
+SET_DAT_UART_RXD_SEL_1	include/ssv6200_reg.h	5508;"	d
+SET_DAT_UART_RX_TIMEOUT	include/ssv6200_reg.h	5913;"	d
+SET_DAT_UART_RX_TIMEOUT_SD	include/ssv6200_reg.h	5982;"	d
+SET_DAT_UART_SW_RST	include/ssv6200_reg.h	4929;"	d
+SET_DAT_UART_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	9288;"	d
+SET_DAT_WORD_LEN	include/ssv6200_reg.h	5816;"	d
+SET_DA_R_CAL_CODE	include/ssv6200_reg.h	8424;"	d
+SET_DA_R_CODE_LUT	include/ssv6200_reg.h	8417;"	d
+SET_DA_SX_SUB_SEL	include/ssv6200_reg.h	8425;"	d
+SET_DBG_ADDR_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10122;"	d
+SET_DBG_ADDR_FENCE	smac/hal/ssv6006c/ssv6006C_reg.h	10123;"	d
+SET_DBG_ALC_LOG_EN	include/ssv6200_reg.h	7249;"	d
+SET_DBG_ALC_LOG_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15719;"	d
+SET_DBG_AMPDU_FAIL	include/ssv6200_reg.h	6845;"	d
+SET_DBG_AMPDU_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	10957;"	d
+SET_DBG_AMPDU_PASS	include/ssv6200_reg.h	6844;"	d
+SET_DBG_AMPDU_PASS	smac/hal/ssv6006c/ssv6006C_reg.h	10956;"	d
+SET_DBG_BACK_DLY	include/ssv6200_reg.h	5994;"	d
+SET_DBG_BA_SEQ	include/ssv6200_reg.h	6297;"	d
+SET_DBG_BA_SEQ	smac/hal/ssv6006c/ssv6006C_reg.h	10301;"	d
+SET_DBG_BA_TYPE	include/ssv6200_reg.h	6296;"	d
+SET_DBG_BA_TYPE	smac/hal/ssv6006c/ssv6006C_reg.h	10300;"	d
+SET_DBG_BRST_MODE	include/ssv6200_reg.h	5991;"	d
+SET_DBG_CFRM_BUSY	include/ssv6200_reg.h	6454;"	d
+SET_DBG_CLK_WIDTH	include/ssv6200_reg.h	5992;"	d
+SET_DBG_CONDI_NUM	include/ssv6200_reg.h	5988;"	d
+SET_DBG_CSN_INTER	include/ssv6200_reg.h	5993;"	d
+SET_DBG_DAT_MODE_OFF	include/ssv6200_reg.h	6021;"	d
+SET_DBG_DMA_RDY	include/ssv6200_reg.h	6452;"	d
+SET_DBG_EDCA0_LOWTHOLD_INT	include/ssv6200_reg.h	6026;"	d
+SET_DBG_EDCA1_LOWTHOLD_INT	include/ssv6200_reg.h	6027;"	d
+SET_DBG_EDCA2_LOWTHOLD_INT	include/ssv6200_reg.h	6028;"	d
+SET_DBG_EDCA3_LOWTHOLD_INT	include/ssv6200_reg.h	6029;"	d
+SET_DBG_FF_FULL	include/ssv6200_reg.h	6329;"	d
+SET_DBG_FF_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	10333;"	d
+SET_DBG_FF_FULL_CLR	include/ssv6200_reg.h	6330;"	d
+SET_DBG_FF_FULL_CLR	smac/hal/ssv6006c/ssv6006C_reg.h	10334;"	d
+SET_DBG_FRONT_DLY	include/ssv6200_reg.h	5995;"	d
+SET_DBG_HOST_PATH	include/ssv6200_reg.h	5989;"	d
+SET_DBG_HWID0_RD_EN	include/ssv6200_reg.h	7271;"	d
+SET_DBG_HWID0_RD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15741;"	d
+SET_DBG_HWID0_WR_EN	include/ssv6200_reg.h	7255;"	d
+SET_DBG_HWID0_WR_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15725;"	d
+SET_DBG_HWID10_RD_EN	include/ssv6200_reg.h	7281;"	d
+SET_DBG_HWID10_RD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15751;"	d
+SET_DBG_HWID10_WR_EN	include/ssv6200_reg.h	7265;"	d
+SET_DBG_HWID10_WR_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15735;"	d
+SET_DBG_HWID11_RD_EN	include/ssv6200_reg.h	7282;"	d
+SET_DBG_HWID11_RD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15752;"	d
+SET_DBG_HWID11_WR_EN	include/ssv6200_reg.h	7266;"	d
+SET_DBG_HWID11_WR_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15736;"	d
+SET_DBG_HWID12_RD_EN	include/ssv6200_reg.h	7283;"	d
+SET_DBG_HWID12_RD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15753;"	d
+SET_DBG_HWID12_WR_EN	include/ssv6200_reg.h	7267;"	d
+SET_DBG_HWID12_WR_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15737;"	d
+SET_DBG_HWID13_RD_EN	include/ssv6200_reg.h	7284;"	d
+SET_DBG_HWID13_RD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15754;"	d
+SET_DBG_HWID13_WR_EN	include/ssv6200_reg.h	7268;"	d
+SET_DBG_HWID13_WR_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15738;"	d
+SET_DBG_HWID14_RD_EN	include/ssv6200_reg.h	7285;"	d
+SET_DBG_HWID14_RD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15755;"	d
+SET_DBG_HWID14_WR_EN	include/ssv6200_reg.h	7269;"	d
+SET_DBG_HWID14_WR_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15739;"	d
+SET_DBG_HWID15_RD_EN	include/ssv6200_reg.h	7286;"	d
+SET_DBG_HWID15_RD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15756;"	d
+SET_DBG_HWID15_WR_EN	include/ssv6200_reg.h	7270;"	d
+SET_DBG_HWID15_WR_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15740;"	d
+SET_DBG_HWID1_RD_EN	include/ssv6200_reg.h	7272;"	d
+SET_DBG_HWID1_RD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15742;"	d
+SET_DBG_HWID1_WR_EN	include/ssv6200_reg.h	7256;"	d
+SET_DBG_HWID1_WR_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15726;"	d
+SET_DBG_HWID2_RD_EN	include/ssv6200_reg.h	7273;"	d
+SET_DBG_HWID2_RD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15743;"	d
+SET_DBG_HWID2_WR_EN	include/ssv6200_reg.h	7257;"	d
+SET_DBG_HWID2_WR_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15727;"	d
+SET_DBG_HWID3_RD_EN	include/ssv6200_reg.h	7274;"	d
+SET_DBG_HWID3_RD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15744;"	d
+SET_DBG_HWID3_WR_EN	include/ssv6200_reg.h	7258;"	d
+SET_DBG_HWID3_WR_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15728;"	d
+SET_DBG_HWID4_RD_EN	include/ssv6200_reg.h	7275;"	d
+SET_DBG_HWID4_RD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15745;"	d
+SET_DBG_HWID4_WR_EN	include/ssv6200_reg.h	7259;"	d
+SET_DBG_HWID4_WR_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15729;"	d
+SET_DBG_HWID5_RD_EN	include/ssv6200_reg.h	7276;"	d
+SET_DBG_HWID5_RD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15746;"	d
+SET_DBG_HWID5_WR_EN	include/ssv6200_reg.h	7260;"	d
+SET_DBG_HWID5_WR_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15730;"	d
+SET_DBG_HWID6_RD_EN	include/ssv6200_reg.h	7277;"	d
+SET_DBG_HWID6_RD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15747;"	d
+SET_DBG_HWID6_WR_EN	include/ssv6200_reg.h	7261;"	d
+SET_DBG_HWID6_WR_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15731;"	d
+SET_DBG_HWID7_RD_EN	include/ssv6200_reg.h	7278;"	d
+SET_DBG_HWID7_RD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15748;"	d
+SET_DBG_HWID7_WR_EN	include/ssv6200_reg.h	7262;"	d
+SET_DBG_HWID7_WR_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15732;"	d
+SET_DBG_HWID8_RD_EN	include/ssv6200_reg.h	7279;"	d
+SET_DBG_HWID8_RD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15749;"	d
+SET_DBG_HWID8_WR_EN	include/ssv6200_reg.h	7263;"	d
+SET_DBG_HWID8_WR_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15733;"	d
+SET_DBG_HWID9_RD_EN	include/ssv6200_reg.h	7280;"	d
+SET_DBG_HWID9_RD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15750;"	d
+SET_DBG_HWID9_WR_EN	include/ssv6200_reg.h	7264;"	d
+SET_DBG_HWID9_WR_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15734;"	d
+SET_DBG_JUDGE_CNT	include/ssv6200_reg.h	6011;"	d
+SET_DBG_JUDGE_CNT_CLR	include/ssv6200_reg.h	6014;"	d
+SET_DBG_LEN_ALC_FAIL	include/ssv6200_reg.h	6843;"	d
+SET_DBG_LEN_ALC_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	10955;"	d
+SET_DBG_LEN_CRC_FAIL	include/ssv6200_reg.h	6842;"	d
+SET_DBG_LEN_CRC_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	10954;"	d
+SET_DBG_MB_FULL	include/ssv6200_reg.h	6333;"	d
+SET_DBG_MB_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	10337;"	d
+SET_DBG_MB_FULL_CLR	include/ssv6200_reg.h	6334;"	d
+SET_DBG_MB_FULL_CLR	smac/hal/ssv6006c/ssv6006C_reg.h	10338;"	d
+SET_DBG_MODE	include/ssv6200_reg.h	6456;"	d
+SET_DBG_MTX_IGNORE_NAV	smac/hal/ssv6006c/ssv6006C_reg.h	10485;"	d
+SET_DBG_PHYTXIP_TIMEOUT_RECOVERY	smac/hal/ssv6006c/ssv6006C_reg.h	10484;"	d
+SET_DBG_PHYTX_PROCEED	smac/hal/ssv6006c/ssv6006C_reg.h	10440;"	d
+SET_DBG_PRTC_PRD	include/ssv6200_reg.h	6451;"	d
+SET_DBG_Q0_ACK_FAIL	include/ssv6200_reg.h	6824;"	d
+SET_DBG_Q0_ACK_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	10936;"	d
+SET_DBG_Q0_ACK_SUCC	include/ssv6200_reg.h	6823;"	d
+SET_DBG_Q0_ACK_SUCC	smac/hal/ssv6006c/ssv6006C_reg.h	10935;"	d
+SET_DBG_Q0_FAIL	include/ssv6200_reg.h	6822;"	d
+SET_DBG_Q0_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	10934;"	d
+SET_DBG_Q0_SUCC	include/ssv6200_reg.h	6821;"	d
+SET_DBG_Q0_SUCC	smac/hal/ssv6006c/ssv6006C_reg.h	10933;"	d
+SET_DBG_Q1_ACK_FAIL	include/ssv6200_reg.h	6828;"	d
+SET_DBG_Q1_ACK_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	10940;"	d
+SET_DBG_Q1_ACK_SUCC	include/ssv6200_reg.h	6827;"	d
+SET_DBG_Q1_ACK_SUCC	smac/hal/ssv6006c/ssv6006C_reg.h	10939;"	d
+SET_DBG_Q1_FAIL	include/ssv6200_reg.h	6826;"	d
+SET_DBG_Q1_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	10938;"	d
+SET_DBG_Q1_SUCC	include/ssv6200_reg.h	6825;"	d
+SET_DBG_Q1_SUCC	smac/hal/ssv6006c/ssv6006C_reg.h	10937;"	d
+SET_DBG_Q2_ACK_FAIL	include/ssv6200_reg.h	6832;"	d
+SET_DBG_Q2_ACK_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	10944;"	d
+SET_DBG_Q2_ACK_SUCC	include/ssv6200_reg.h	6831;"	d
+SET_DBG_Q2_ACK_SUCC	smac/hal/ssv6006c/ssv6006C_reg.h	10943;"	d
+SET_DBG_Q2_FAIL	include/ssv6200_reg.h	6830;"	d
+SET_DBG_Q2_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	10942;"	d
+SET_DBG_Q2_SUCC	include/ssv6200_reg.h	6829;"	d
+SET_DBG_Q2_SUCC	smac/hal/ssv6006c/ssv6006C_reg.h	10941;"	d
+SET_DBG_Q3_ACK_FAIL	include/ssv6200_reg.h	6836;"	d
+SET_DBG_Q3_ACK_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	10948;"	d
+SET_DBG_Q3_ACK_SUCC	include/ssv6200_reg.h	6835;"	d
+SET_DBG_Q3_ACK_SUCC	smac/hal/ssv6006c/ssv6006C_reg.h	10947;"	d
+SET_DBG_Q3_FAIL	include/ssv6200_reg.h	6834;"	d
+SET_DBG_Q3_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	10946;"	d
+SET_DBG_Q3_SUCC	include/ssv6200_reg.h	6833;"	d
+SET_DBG_Q3_SUCC	smac/hal/ssv6006c/ssv6006C_reg.h	10945;"	d
+SET_DBG_RDATA_RDY	include/ssv6200_reg.h	6002;"	d
+SET_DBG_RD_DAT_CNT	include/ssv6200_reg.h	6009;"	d
+SET_DBG_RD_DAT_CNT_CLR	include/ssv6200_reg.h	6013;"	d
+SET_DBG_RD_STS_CNT	include/ssv6200_reg.h	6010;"	d
+SET_DBG_RD_STS_CNT_CLR	include/ssv6200_reg.h	6012;"	d
+SET_DBG_RST	include/ssv6200_reg.h	6455;"	d
+SET_DBG_RX_FIFO_FAIL	include/ssv6200_reg.h	5996;"	d
+SET_DBG_RX_FIFO_RESIDUE	include/ssv6200_reg.h	6023;"	d
+SET_DBG_RX_HOST_FAIL	include/ssv6200_reg.h	5997;"	d
+SET_DBG_RX_LEN	include/ssv6200_reg.h	6005;"	d
+SET_DBG_RX_QUOTA	include/ssv6200_reg.h	5987;"	d
+SET_DBG_RX_RDY	include/ssv6200_reg.h	6024;"	d
+SET_DBG_SDIO_SYS_INT	include/ssv6200_reg.h	6025;"	d
+SET_DBG_SPI_ALLOC_STATUS	include/ssv6200_reg.h	6003;"	d
+SET_DBG_SPI_CLK_EN_INT	include/ssv6200_reg.h	6032;"	d
+SET_DBG_SPI_DBG_WR_FIFO_FULL	include/ssv6200_reg.h	6004;"	d
+SET_DBG_SPI_DOUBLE_ALLOC	include/ssv6200_reg.h	6000;"	d
+SET_DBG_SPI_FN1	include/ssv6200_reg.h	6031;"	d
+SET_DBG_SPI_HOST_MASK	include/ssv6200_reg.h	6033;"	d
+SET_DBG_SPI_HOST_TX_ALLOC_PKBUF	include/ssv6200_reg.h	6007;"	d
+SET_DBG_SPI_MODE	include/ssv6200_reg.h	5986;"	d
+SET_DBG_SPI_TX_ALLOC_SIZE	include/ssv6200_reg.h	6008;"	d
+SET_DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS	include/ssv6200_reg.h	6006;"	d
+SET_DBG_SPI_TX_NO_ALLOC	include/ssv6200_reg.h	6001;"	d
+SET_DBG_TX_DISCARD_CNT	include/ssv6200_reg.h	6016;"	d
+SET_DBG_TX_DISCARD_CNT_CLR	include/ssv6200_reg.h	6018;"	d
+SET_DBG_TX_DONE_CNT	include/ssv6200_reg.h	6015;"	d
+SET_DBG_TX_DONE_CNT_CLR	include/ssv6200_reg.h	6019;"	d
+SET_DBG_TX_FIFO_FAIL	include/ssv6200_reg.h	5998;"	d
+SET_DBG_TX_FIFO_RESIDUE	include/ssv6200_reg.h	6022;"	d
+SET_DBG_TX_HOST_FAIL	include/ssv6200_reg.h	5999;"	d
+SET_DBG_TX_LIMIT_INT_IN	include/ssv6200_reg.h	6030;"	d
+SET_DBG_TX_SEG	include/ssv6200_reg.h	5990;"	d
+SET_DBG_TX_SET_CNT	include/ssv6200_reg.h	6017;"	d
+SET_DBG_TX_SET_CNT_CLR	include/ssv6200_reg.h	6020;"	d
+SET_DBG_TYPE	include/ssv6200_reg.h	7247;"	d
+SET_DBG_TYPE	smac/hal/ssv6006c/ssv6006C_reg.h	15717;"	d
+SET_DBG_WAIT_RSP	include/ssv6200_reg.h	6453;"	d
+SET_DBG_WFF_FULL	include/ssv6200_reg.h	6331;"	d
+SET_DBG_WFF_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	10335;"	d
+SET_DBG_WFF_FULL_CLR	include/ssv6200_reg.h	6332;"	d
+SET_DBG_WFF_FULL_CLR	smac/hal/ssv6006c/ssv6006C_reg.h	10336;"	d
+SET_DBG_WRITE_TO_FINISH_SIM	smac/hal/ssv6006c/ssv6006C_reg.h	9403;"	d
+SET_DBIST_MODE	include/ssv6200_reg.h	4982;"	d
+SET_DB_AD_ADC_I_OUT	smac/hal/ssv6006c/ssv6006C_reg.h	14009;"	d
+SET_DB_AD_ADC_Q_OUT	smac/hal/ssv6006c/ssv6006C_reg.h	14010;"	d
+SET_DB_AD_DP_VT_MON_Q	smac/hal/ssv6006c/ssv6006C_reg.h	14018;"	d
+SET_DB_AD_IOT_ADC_OUT	smac/hal/ssv6006c/ssv6006C_reg.h	14019;"	d
+SET_DB_AD_RX_RSSIADC	smac/hal/ssv6006c/ssv6006C_reg.h	14011;"	d
+SET_DB_AD_SX5GB_AAC_COMPOUT	smac/hal/ssv6006c/ssv6006C_reg.h	14430;"	d
+SET_DB_DA_SARADC_BIT	smac/hal/ssv6006c/ssv6006C_reg.h	14012;"	d
+SET_DB_DA_SX5GB_SUB_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	14424;"	d
+SET_DB_DA_SX5GB_VCO_ISEL	smac/hal/ssv6006c/ssv6006C_reg.h	14425;"	d
+SET_DB_DA_SXMIX_GMSEL	smac/hal/ssv6006c/ssv6006C_reg.h	14427;"	d
+SET_DB_DA_SXMIX_SCA_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	14426;"	d
+SET_DB_DA_SXREP_CSSEL	smac/hal/ssv6006c/ssv6006C_reg.h	14429;"	d
+SET_DB_DA_SXREP_SCA_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	14428;"	d
+SET_DB_DA_SX_SUB_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	14014;"	d
+SET_DB_DA_SX_VCO_ISEL	smac/hal/ssv6006c/ssv6006C_reg.h	14015;"	d
+SET_DB_GEMINIA_AD_ADC_I_OUT	smac/hal/ssv6006c/ssv6006C_reg.h	11728;"	d
+SET_DB_GEMINIA_AD_ADC_Q_OUT	smac/hal/ssv6006c/ssv6006C_reg.h	11729;"	d
+SET_DB_GEMINIA_AD_DP_VT_MON_Q	smac/hal/ssv6006c/ssv6006C_reg.h	11737;"	d
+SET_DB_GEMINIA_AD_RX_RSSIADC	smac/hal/ssv6006c/ssv6006C_reg.h	11730;"	d
+SET_DB_GEMINIA_DA_SARADC_BIT	smac/hal/ssv6006c/ssv6006C_reg.h	11731;"	d
+SET_DB_GEMINIA_DA_SX_SUB_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	11733;"	d
+SET_DB_GEMINIA_DA_SX_VCO_ISEL	smac/hal/ssv6006c/ssv6006C_reg.h	11734;"	d
+SET_DB_GEMINIA_SX_SBCAL_NCOUNT	smac/hal/ssv6006c/ssv6006C_reg.h	11738;"	d
+SET_DB_GEMINIA_SX_SBCAL_NTARGET	smac/hal/ssv6006c/ssv6006C_reg.h	11739;"	d
+SET_DB_GEMINIA_SX_TTL_VT_DET	smac/hal/ssv6006c/ssv6006C_reg.h	11736;"	d
+SET_DB_GEMINIA_VO_AAC_COMPOUT	smac/hal/ssv6006c/ssv6006C_reg.h	11735;"	d
+SET_DB_SX5GB_SBCAL_NCOUNT	smac/hal/ssv6006c/ssv6006C_reg.h	14436;"	d
+SET_DB_SX5GB_SBCAL_NTARGET	smac/hal/ssv6006c/ssv6006C_reg.h	14437;"	d
+SET_DB_SX5GB_TTL_VT_DET	smac/hal/ssv6006c/ssv6006C_reg.h	14431;"	d
+SET_DB_SXMIX_SCA_SEL_A1	smac/hal/ssv6006c/ssv6006C_reg.h	14432;"	d
+SET_DB_SXMIX_SCA_SEL_A2	smac/hal/ssv6006c/ssv6006C_reg.h	14433;"	d
+SET_DB_SXREP_SCA_SEL_B1	smac/hal/ssv6006c/ssv6006C_reg.h	14434;"	d
+SET_DB_SXREP_SCA_SEL_B2	smac/hal/ssv6006c/ssv6006C_reg.h	14435;"	d
+SET_DB_SX_SBCAL_NCOUNT	smac/hal/ssv6006c/ssv6006C_reg.h	14020;"	d
+SET_DB_SX_SBCAL_NTARGET	smac/hal/ssv6006c/ssv6006C_reg.h	14021;"	d
+SET_DB_SX_TTL_VT_DET	smac/hal/ssv6006c/ssv6006C_reg.h	14017;"	d
+SET_DB_TURISMO_TRX_AD_ADC_I_OUT	smac/hal/ssv6006c/ssv6006C_reg.h	12639;"	d
+SET_DB_TURISMO_TRX_AD_ADC_Q_OUT	smac/hal/ssv6006c/ssv6006C_reg.h	12640;"	d
+SET_DB_TURISMO_TRX_AD_DP_VT_MON_Q	smac/hal/ssv6006c/ssv6006C_reg.h	12648;"	d
+SET_DB_TURISMO_TRX_AD_IOT_ADC_OUT	smac/hal/ssv6006c/ssv6006C_reg.h	12649;"	d
+SET_DB_TURISMO_TRX_AD_RX_RSSIADC	smac/hal/ssv6006c/ssv6006C_reg.h	12641;"	d
+SET_DB_TURISMO_TRX_AD_SX5GB_AAC_COMPOUT	smac/hal/ssv6006c/ssv6006C_reg.h	13049;"	d
+SET_DB_TURISMO_TRX_DA_SARADC_BIT	smac/hal/ssv6006c/ssv6006C_reg.h	12642;"	d
+SET_DB_TURISMO_TRX_DA_SX5GB_SUB_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	13043;"	d
+SET_DB_TURISMO_TRX_DA_SX5GB_VCO_ISEL	smac/hal/ssv6006c/ssv6006C_reg.h	13044;"	d
+SET_DB_TURISMO_TRX_DA_SXMIX_GMSEL	smac/hal/ssv6006c/ssv6006C_reg.h	13046;"	d
+SET_DB_TURISMO_TRX_DA_SXMIX_SCA_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	13045;"	d
+SET_DB_TURISMO_TRX_DA_SXREP_CSSEL	smac/hal/ssv6006c/ssv6006C_reg.h	13048;"	d
+SET_DB_TURISMO_TRX_DA_SXREP_SCA_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	13047;"	d
+SET_DB_TURISMO_TRX_DA_SX_SUB_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	12644;"	d
+SET_DB_TURISMO_TRX_DA_SX_VCO_ISEL	smac/hal/ssv6006c/ssv6006C_reg.h	12645;"	d
+SET_DB_TURISMO_TRX_SX5GB_SBCAL_NCOUNT	smac/hal/ssv6006c/ssv6006C_reg.h	13055;"	d
+SET_DB_TURISMO_TRX_SX5GB_SBCAL_NTARGET	smac/hal/ssv6006c/ssv6006C_reg.h	13056;"	d
+SET_DB_TURISMO_TRX_SX5GB_TTL_VT_DET	smac/hal/ssv6006c/ssv6006C_reg.h	13050;"	d
+SET_DB_TURISMO_TRX_SXMIX_SCA_SEL_A1	smac/hal/ssv6006c/ssv6006C_reg.h	13051;"	d
+SET_DB_TURISMO_TRX_SXMIX_SCA_SEL_A2	smac/hal/ssv6006c/ssv6006C_reg.h	13052;"	d
+SET_DB_TURISMO_TRX_SXREP_SCA_SEL_B1	smac/hal/ssv6006c/ssv6006C_reg.h	13053;"	d
+SET_DB_TURISMO_TRX_SXREP_SCA_SEL_B2	smac/hal/ssv6006c/ssv6006C_reg.h	13054;"	d
+SET_DB_TURISMO_TRX_SX_SBCAL_NCOUNT	smac/hal/ssv6006c/ssv6006C_reg.h	12650;"	d
+SET_DB_TURISMO_TRX_SX_SBCAL_NTARGET	smac/hal/ssv6006c/ssv6006C_reg.h	12651;"	d
+SET_DB_TURISMO_TRX_SX_TTL_VT_DET	smac/hal/ssv6006c/ssv6006C_reg.h	12647;"	d
+SET_DB_TURISMO_TRX_VO_AAC_COMPOUT	smac/hal/ssv6006c/ssv6006C_reg.h	12646;"	d
+SET_DB_VO_AAC_COMPOUT	smac/hal/ssv6006c/ssv6006C_reg.h	14016;"	d
+SET_DEBUG_CTL	include/ssv6200_reg.h	8483;"	d
+SET_DEBUG_H16	include/ssv6200_reg.h	8484;"	d
+SET_DEBUG_OUT	include/ssv6200_reg.h	8485;"	d
+SET_DEBUG_SEL	include/ssv6200_reg.h	7833;"	d
+SET_DEC_DIN_MSB	include/ssv6200_reg.h	6245;"	d
+SET_DEC_DOUT_MSB	include/ssv6200_reg.h	6244;"	d
+SET_DEC_TBL	smac/dev_tbl.h	36;"	d
+SET_DELTA_CD	include/ssv6200_reg.h	5792;"	d
+SET_DELTA_CD	smac/hal/ssv6006c/ssv6006C_reg.h	9783;"	d
+SET_DELTA_CTS	include/ssv6200_reg.h	5789;"	d
+SET_DELTA_CTS	smac/hal/ssv6006c/ssv6006C_reg.h	9780;"	d
+SET_DELTA_DSR	include/ssv6200_reg.h	5790;"	d
+SET_DELTA_DSR	smac/hal/ssv6006c/ssv6006C_reg.h	9781;"	d
+SET_DE_RTS	smac/hal/ssv6006c/ssv6006C_reg.h	9771;"	d
+SET_DIGI_TOP_POR_MASK	include/ssv6200_reg.h	6086;"	d
+SET_DIRECT_INT_MUX_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	9607;"	d
+SET_DIRECT_MODE	include/ssv6200_reg.h	8435;"	d
+SET_DIS_DEMAND	include/ssv6200_reg.h	8437;"	d
+SET_DLAB	include/ssv6200_reg.h	5775;"	d
+SET_DLAB	smac/hal/ssv6006c/ssv6006C_reg.h	9765;"	d
+SET_DMA_ADR_DST	include/ssv6200_reg.h	6058;"	d
+SET_DMA_ADR_DST	smac/hal/ssv6006c/ssv6006C_reg.h	9911;"	d
+SET_DMA_ADR_SRC	include/ssv6200_reg.h	6057;"	d
+SET_DMA_ADR_SRC	smac/hal/ssv6006c/ssv6006C_reg.h	9910;"	d
+SET_DMA_BADR_EN	include/ssv6200_reg.h	6065;"	d
+SET_DMA_BADR_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9918;"	d
+SET_DMA_BUSY	include/ssv6200_reg.h	6041;"	d
+SET_DMA_CLK_EN	include/ssv6200_reg.h	4947;"	d
+SET_DMA_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9306;"	d
+SET_DMA_CONST	include/ssv6200_reg.h	6070;"	d
+SET_DMA_CONST	smac/hal/ssv6006c/ssv6006C_reg.h	9923;"	d
+SET_DMA_DST_INC	include/ssv6200_reg.h	6062;"	d
+SET_DMA_DST_INC	smac/hal/ssv6006c/ssv6006C_reg.h	9915;"	d
+SET_DMA_DST_SIZE	include/ssv6200_reg.h	6061;"	d
+SET_DMA_DST_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	9914;"	d
+SET_DMA_EN	include/ssv6200_reg.h	6040;"	d
+SET_DMA_FAST_FILL	include/ssv6200_reg.h	6063;"	d
+SET_DMA_FAST_FILL	smac/hal/ssv6006c/ssv6006C_reg.h	9916;"	d
+SET_DMA_FINISH	include/ssv6200_reg.h	6069;"	d
+SET_DMA_FINISH	smac/hal/ssv6006c/ssv6006C_reg.h	9922;"	d
+SET_DMA_INT_MASK	include/ssv6200_reg.h	6067;"	d
+SET_DMA_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	9920;"	d
+SET_DMA_LEN	include/ssv6200_reg.h	6066;"	d
+SET_DMA_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	9919;"	d
+SET_DMA_MODE	include/ssv6200_reg.h	5765;"	d
+SET_DMA_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	9755;"	d
+SET_DMA_RXEND_IE	include/ssv6200_reg.h	5760;"	d
+SET_DMA_SDIO_KICK	include/ssv6200_reg.h	6064;"	d
+SET_DMA_SDIO_KICK	smac/hal/ssv6006c/ssv6006C_reg.h	9917;"	d
+SET_DMA_SRC_INC	include/ssv6200_reg.h	6060;"	d
+SET_DMA_SRC_INC	smac/hal/ssv6006c/ssv6006C_reg.h	9913;"	d
+SET_DMA_SRC_SIZE	include/ssv6200_reg.h	6059;"	d
+SET_DMA_SRC_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	9912;"	d
+SET_DMA_STS	include/ssv6200_reg.h	6068;"	d
+SET_DMA_STS	smac/hal/ssv6006c/ssv6006C_reg.h	9921;"	d
+SET_DMA_SW_RST	include/ssv6200_reg.h	4913;"	d
+SET_DMA_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	9273;"	d
+SET_DMA_TXEND_IE	include/ssv6200_reg.h	5761;"	d
+SET_DMN_FLAG	include/ssv6200_reg.h	8493;"	d
+SET_DMN_FLAG_CLR	include/ssv6200_reg.h	8442;"	d
+SET_DMN_IDTBL_127_96	include/ssv6200_reg.h	8519;"	d
+SET_DMN_IDTBL_31_0	include/ssv6200_reg.h	8516;"	d
+SET_DMN_IDTBL_63_32	include/ssv6200_reg.h	8517;"	d
+SET_DMN_IDTBL_95_64	include/ssv6200_reg.h	8518;"	d
+SET_DMN_MCU_ADDR	include/ssv6200_reg.h	8507;"	d
+SET_DMN_MCU_FLAG	include/ssv6200_reg.h	8503;"	d
+SET_DMN_MCU_ID	include/ssv6200_reg.h	8506;"	d
+SET_DMN_MCU_INT	include/ssv6200_reg.h	5910;"	d
+SET_DMN_MCU_INT_SD	include/ssv6200_reg.h	5979;"	d
+SET_DMN_MCU_PORT	include/ssv6200_reg.h	8505;"	d
+SET_DMN_MCU_WR	include/ssv6200_reg.h	8504;"	d
+SET_DMN_NHIT_ADDR	include/ssv6200_reg.h	8497;"	d
+SET_DMN_NHIT_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	15961;"	d
+SET_DMN_NHIT_ID	include/ssv6200_reg.h	8496;"	d
+SET_DMN_NHIT_ID	smac/hal/ssv6006c/ssv6006C_reg.h	15960;"	d
+SET_DMN_NOHIT_CLR	smac/hal/ssv6006c/ssv6006C_reg.h	15957;"	d
+SET_DMN_NOHIT_FLAG	include/ssv6200_reg.h	8492;"	d
+SET_DMN_NOHIT_INT	include/ssv6200_reg.h	5903;"	d
+SET_DMN_NOHIT_INT_SD	include/ssv6200_reg.h	5972;"	d
+SET_DMN_NOHIT_MCU	include/ssv6200_reg.h	8502;"	d
+SET_DMN_NOHIT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	15956;"	d
+SET_DMN_PORT	include/ssv6200_reg.h	8495;"	d
+SET_DMN_PORT	smac/hal/ssv6006c/ssv6006C_reg.h	15959;"	d
+SET_DMN_R_PASS	include/ssv6200_reg.h	8476;"	d
+SET_DMN_WR	include/ssv6200_reg.h	8494;"	d
+SET_DMN_WR	smac/hal/ssv6006c/ssv6006C_reg.h	15958;"	d
+SET_DOT11RTSTHRESHOLD	include/ssv6200_reg.h	6133;"	d
+SET_DOT11RTSTHRESHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	10116;"	d
+SET_DOUBLE_ALLOCATE_ERROR	include/ssv6200_reg.h	5604;"	d
+SET_DOUBLE_ALLOC_ERR	smac/hal/ssv6006c/ssv6006C_reg.h	10136;"	d
+SET_DOUBLE_RLS_ID	include/ssv6200_reg.h	7445;"	d
+SET_DOUBLE_RLS_ID	smac/hal/ssv6006c/ssv6006C_reg.h	15889;"	d
+SET_DOUBLE_RLS_INT_EN	include/ssv6200_reg.h	7443;"	d
+SET_DOUBLE_RLS_INT_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15887;"	d
+SET_DPLL_CKT_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	13819;"	d
+SET_DPLL_FB_DIVISION__REGISTERS	smac/hal/ssv6006c/ssv6006C_reg.h	13820;"	d
+SET_DPLL_TOP_REGISTER	smac/hal/ssv6006c/ssv6006C_reg.h	13818;"	d
+SET_DSR	include/ssv6200_reg.h	5794;"	d
+SET_DSR	smac/hal/ssv6006c/ssv6006C_reg.h	9785;"	d
+SET_DTR	include/ssv6200_reg.h	5776;"	d
+SET_DTR	smac/hal/ssv6006c/ssv6006C_reg.h	9766;"	d
+SET_DUAL_ANT_EN	include/ssv6200_reg.h	6755;"	d
+SET_DUAL_ANT_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10858;"	d
+SET_DUMY_DLY	smac/hal/ssv6006c/ssv6006C_reg.h	9879;"	d
+SET_DUP_FLT	include/ssv6200_reg.h	6733;"	d
+SET_DUP_FLT	smac/hal/ssv6006c/ssv6006C_reg.h	10829;"	d
+SET_DURATION	include/ssv6200_reg.h	6197;"	d
+SET_DURATION	smac/hal/ssv6006c/ssv6006C_reg.h	10215;"	d
+SET_EARLY_SAMPLE	smac/hal/ssv6006c/ssv6006C_reg.h	10276;"	d
+SET_EDCA0_FFO_CNT	include/ssv6200_reg.h	7470;"	d
+SET_EDCA0_FFO_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15914;"	d
+SET_EDCA0_LOWTHOLD_INT	include/ssv6200_reg.h	5728;"	d
+SET_EDCA0_LOW_THR_INT_MASK	include/ssv6200_reg.h	5514;"	d
+SET_EDCA0_LOW_THR_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	9577;"	d
+SET_EDCA0_LOW_THR_INT_STS	include/ssv6200_reg.h	5522;"	d
+SET_EDCA0_LOW_THR_INT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	9585;"	d
+SET_EDCA0_UPTHOLD_INT	include/ssv6200_reg.h	5614;"	d
+SET_EDCA1_FFO_CNT2	include/ssv6200_reg.h	7485;"	d
+SET_EDCA1_FFO_CNT2	smac/hal/ssv6006c/ssv6006C_reg.h	15930;"	d
+SET_EDCA1_FFO_CNT_3_0	include/ssv6200_reg.h	7471;"	d
+SET_EDCA1_FFO_CNT_3_0	smac/hal/ssv6006c/ssv6006C_reg.h	15915;"	d
+SET_EDCA1_LOWTHOLD_INT	include/ssv6200_reg.h	5729;"	d
+SET_EDCA1_LOW_THR_INT_MASK	include/ssv6200_reg.h	5515;"	d
+SET_EDCA1_LOW_THR_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	9578;"	d
+SET_EDCA1_LOW_THR_INT_STS	include/ssv6200_reg.h	5523;"	d
+SET_EDCA1_LOW_THR_INT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	9586;"	d
+SET_EDCA1_UPTHOLD_INT	include/ssv6200_reg.h	5615;"	d
+SET_EDCA2_FFO_CNT	include/ssv6200_reg.h	7472;"	d
+SET_EDCA2_FFO_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15916;"	d
+SET_EDCA2_FFO_CNT2	include/ssv6200_reg.h	7489;"	d
+SET_EDCA2_FFO_CNT2	smac/hal/ssv6006c/ssv6006C_reg.h	15935;"	d
+SET_EDCA2_LOWTHOLD_INT	include/ssv6200_reg.h	5730;"	d
+SET_EDCA2_LOW_THR_INT_MASK	include/ssv6200_reg.h	5516;"	d
+SET_EDCA2_LOW_THR_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	9579;"	d
+SET_EDCA2_LOW_THR_INT_STS	include/ssv6200_reg.h	5524;"	d
+SET_EDCA2_LOW_THR_INT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	9587;"	d
+SET_EDCA2_UPTHOLD_INT	include/ssv6200_reg.h	5616;"	d
+SET_EDCA3_FFO_CNT	include/ssv6200_reg.h	7473;"	d
+SET_EDCA3_FFO_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15917;"	d
+SET_EDCA3_FFO_CNT2	include/ssv6200_reg.h	7490;"	d
+SET_EDCA3_FFO_CNT2	smac/hal/ssv6006c/ssv6006C_reg.h	15936;"	d
+SET_EDCA3_LOWTHOLD_INT	include/ssv6200_reg.h	5731;"	d
+SET_EDCA3_LOW_THR_INT_MASK	include/ssv6200_reg.h	5517;"	d
+SET_EDCA3_LOW_THR_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	9580;"	d
+SET_EDCA3_LOW_THR_INT_STS	include/ssv6200_reg.h	5525;"	d
+SET_EDCA3_LOW_THR_INT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	9588;"	d
+SET_EDCA3_UPTHOLD_INT	include/ssv6200_reg.h	5617;"	d
+SET_EDCA4_FFO_CNT	include/ssv6200_reg.h	7482;"	d
+SET_EDCA4_FFO_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15926;"	d
+SET_EDCA4_FFO_CNT2	include/ssv6200_reg.h	7486;"	d
+SET_EDCA4_FFO_CNT2	smac/hal/ssv6006c/ssv6006C_reg.h	15931;"	d
+SET_EDCA4_LOW_THR_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	9575;"	d
+SET_EDCA4_LOW_THR_INT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	9583;"	d
+SET_EDCA5_FFO_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15927;"	d
+SET_EDCA5_FFO_CNT2	smac/hal/ssv6006c/ssv6006C_reg.h	15932;"	d
+SET_EDLM_SRAM_ERRCK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9363;"	d
+SET_EDLM_SRAM_ERR_INT	smac/hal/ssv6006c/ssv6006C_reg.h	9368;"	d
+SET_EFS_BYTE_0	smac/hal/ssv6006c/ssv6006C_reg.h	10231;"	d
+SET_EFS_BYTE_1	smac/hal/ssv6006c/ssv6006C_reg.h	10232;"	d
+SET_EFS_BYTE_10	smac/hal/ssv6006c/ssv6006C_reg.h	10241;"	d
+SET_EFS_BYTE_11	smac/hal/ssv6006c/ssv6006C_reg.h	10242;"	d
+SET_EFS_BYTE_12	smac/hal/ssv6006c/ssv6006C_reg.h	10243;"	d
+SET_EFS_BYTE_13	smac/hal/ssv6006c/ssv6006C_reg.h	10244;"	d
+SET_EFS_BYTE_14	smac/hal/ssv6006c/ssv6006C_reg.h	10245;"	d
+SET_EFS_BYTE_15	smac/hal/ssv6006c/ssv6006C_reg.h	10246;"	d
+SET_EFS_BYTE_16	smac/hal/ssv6006c/ssv6006C_reg.h	10247;"	d
+SET_EFS_BYTE_17	smac/hal/ssv6006c/ssv6006C_reg.h	10248;"	d
+SET_EFS_BYTE_18	smac/hal/ssv6006c/ssv6006C_reg.h	10249;"	d
+SET_EFS_BYTE_19	smac/hal/ssv6006c/ssv6006C_reg.h	10250;"	d
+SET_EFS_BYTE_2	smac/hal/ssv6006c/ssv6006C_reg.h	10233;"	d
+SET_EFS_BYTE_20	smac/hal/ssv6006c/ssv6006C_reg.h	10251;"	d
+SET_EFS_BYTE_21	smac/hal/ssv6006c/ssv6006C_reg.h	10252;"	d
+SET_EFS_BYTE_22	smac/hal/ssv6006c/ssv6006C_reg.h	10253;"	d
+SET_EFS_BYTE_23	smac/hal/ssv6006c/ssv6006C_reg.h	10254;"	d
+SET_EFS_BYTE_24	smac/hal/ssv6006c/ssv6006C_reg.h	10255;"	d
+SET_EFS_BYTE_25	smac/hal/ssv6006c/ssv6006C_reg.h	10256;"	d
+SET_EFS_BYTE_26	smac/hal/ssv6006c/ssv6006C_reg.h	10257;"	d
+SET_EFS_BYTE_27	smac/hal/ssv6006c/ssv6006C_reg.h	10258;"	d
+SET_EFS_BYTE_28	smac/hal/ssv6006c/ssv6006C_reg.h	10259;"	d
+SET_EFS_BYTE_29	smac/hal/ssv6006c/ssv6006C_reg.h	10260;"	d
+SET_EFS_BYTE_3	smac/hal/ssv6006c/ssv6006C_reg.h	10234;"	d
+SET_EFS_BYTE_30	smac/hal/ssv6006c/ssv6006C_reg.h	10261;"	d
+SET_EFS_BYTE_31	smac/hal/ssv6006c/ssv6006C_reg.h	10262;"	d
+SET_EFS_BYTE_4	smac/hal/ssv6006c/ssv6006C_reg.h	10235;"	d
+SET_EFS_BYTE_5	smac/hal/ssv6006c/ssv6006C_reg.h	10236;"	d
+SET_EFS_BYTE_6	smac/hal/ssv6006c/ssv6006C_reg.h	10237;"	d
+SET_EFS_BYTE_7	smac/hal/ssv6006c/ssv6006C_reg.h	10238;"	d
+SET_EFS_BYTE_8	smac/hal/ssv6006c/ssv6006C_reg.h	10239;"	d
+SET_EFS_BYTE_9	smac/hal/ssv6006c/ssv6006C_reg.h	10240;"	d
+SET_EFS_CLKFREQ	include/ssv6200_reg.h	6202;"	d
+SET_EFS_CLKFREQ	smac/hal/ssv6006c/ssv6006C_reg.h	10220;"	d
+SET_EFS_CLKFREQ_RD	include/ssv6200_reg.h	6204;"	d
+SET_EFS_CLKFREQ_RD	smac/hal/ssv6006c/ssv6006C_reg.h	10222;"	d
+SET_EFS_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9311;"	d
+SET_EFS_LDO_OFF	include/ssv6200_reg.h	6207;"	d
+SET_EFS_LDO_OFF	smac/hal/ssv6006c/ssv6006C_reg.h	10225;"	d
+SET_EFS_LDO_ON	include/ssv6200_reg.h	6206;"	d
+SET_EFS_LDO_ON	smac/hal/ssv6006c/ssv6006C_reg.h	10224;"	d
+SET_EFS_PRE_RD	include/ssv6200_reg.h	6205;"	d
+SET_EFS_PRE_RD	smac/hal/ssv6006c/ssv6006C_reg.h	10223;"	d
+SET_EFS_PROGRESS_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	10227;"	d
+SET_EFS_RDATA_0	include/ssv6200_reg.h	6208;"	d
+SET_EFS_RDATA_1	include/ssv6200_reg.h	6210;"	d
+SET_EFS_RDATA_2	include/ssv6200_reg.h	6212;"	d
+SET_EFS_RDATA_3	include/ssv6200_reg.h	6214;"	d
+SET_EFS_RDATA_4	include/ssv6200_reg.h	6216;"	d
+SET_EFS_RDATA_5	include/ssv6200_reg.h	6218;"	d
+SET_EFS_RDATA_6	include/ssv6200_reg.h	6220;"	d
+SET_EFS_RDATA_7	include/ssv6200_reg.h	6222;"	d
+SET_EFS_RD_FLAG	smac/hal/ssv6006c/ssv6006C_reg.h	10226;"	d
+SET_EFS_RD_KICK	smac/hal/ssv6006c/ssv6006C_reg.h	10229;"	d
+SET_EFS_SPI_RBUSY	include/ssv6200_reg.h	6232;"	d
+SET_EFS_SPI_RD0_EN	include/ssv6200_reg.h	6224;"	d
+SET_EFS_SPI_RD1_EN	include/ssv6200_reg.h	6225;"	d
+SET_EFS_SPI_RD2_EN	include/ssv6200_reg.h	6226;"	d
+SET_EFS_SPI_RD3_EN	include/ssv6200_reg.h	6227;"	d
+SET_EFS_SPI_RD4_EN	include/ssv6200_reg.h	6228;"	d
+SET_EFS_SPI_RD5_EN	include/ssv6200_reg.h	6229;"	d
+SET_EFS_SPI_RD6_EN	include/ssv6200_reg.h	6230;"	d
+SET_EFS_SPI_RD7_EN	include/ssv6200_reg.h	6231;"	d
+SET_EFS_SPI_RDATA_0	include/ssv6200_reg.h	6233;"	d
+SET_EFS_SPI_RDATA_1	include/ssv6200_reg.h	6234;"	d
+SET_EFS_SPI_RDATA_2	include/ssv6200_reg.h	6235;"	d
+SET_EFS_SPI_RDATA_3	include/ssv6200_reg.h	6236;"	d
+SET_EFS_SPI_RDATA_4	include/ssv6200_reg.h	6237;"	d
+SET_EFS_SPI_RDATA_5	include/ssv6200_reg.h	6238;"	d
+SET_EFS_SPI_RDATA_6	include/ssv6200_reg.h	6239;"	d
+SET_EFS_SPI_RDATA_7	include/ssv6200_reg.h	6240;"	d
+SET_EFS_VDDQ_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10230;"	d
+SET_EFS_VDDQ_EN_LOW_ACTIVE	smac/hal/ssv6006c/ssv6006C_reg.h	10221;"	d
+SET_EFS_WDATA_0	include/ssv6200_reg.h	6209;"	d
+SET_EFS_WDATA_1	include/ssv6200_reg.h	6211;"	d
+SET_EFS_WDATA_2	include/ssv6200_reg.h	6213;"	d
+SET_EFS_WDATA_3	include/ssv6200_reg.h	6215;"	d
+SET_EFS_WDATA_4	include/ssv6200_reg.h	6217;"	d
+SET_EFS_WDATA_5	include/ssv6200_reg.h	6219;"	d
+SET_EFS_WDATA_6	include/ssv6200_reg.h	6221;"	d
+SET_EFS_WDATA_7	include/ssv6200_reg.h	6223;"	d
+SET_EFS_WR_KICK	smac/hal/ssv6006c/ssv6006C_reg.h	10228;"	d
+SET_EIFS_IN_SLOT	smac/hal/ssv6006c/ssv6006C_reg.h	10513;"	d
+SET_EILM_ROM_ERRCK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9364;"	d
+SET_EILM_ROM_ERR_INT	smac/hal/ssv6006c/ssv6006C_reg.h	9369;"	d
+SET_EILM_SRAM_ERRCK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9365;"	d
+SET_EILM_SRAM_ERR_INT	smac/hal/ssv6006c/ssv6006C_reg.h	9370;"	d
+SET_ENABLECSA	include/ssv6200_reg.h	5653;"	d
+SET_ENABLECSA	smac/hal/ssv6006c/ssv6006C_reg.h	9649;"	d
+SET_ENABLE_BLOCK_GAP_INTERRUPT	include/ssv6200_reg.h	5645;"	d
+SET_ENABLE_BLOCK_GAP_INTERRUPT	smac/hal/ssv6006c/ssv6006C_reg.h	9639;"	d
+SET_ENC_DIN_MSB	include/ssv6200_reg.h	6247;"	d
+SET_ENC_DOUT_MSB	include/ssv6200_reg.h	6246;"	d
+SET_ENDIAN	smac/hal/ssv6006c/ssv6006C_reg.h	10275;"	d
+SET_END_BYTE_VALUE	include/ssv6200_reg.h	5563;"	d
+SET_END_BYTE_VALUE2	include/ssv6200_reg.h	5628;"	d
+SET_EN_AUTO_CTS	include/ssv6200_reg.h	5767;"	d
+SET_EN_AUTO_CTS	smac/hal/ssv6006c/ssv6006C_reg.h	9757;"	d
+SET_EN_AUTO_RTS	include/ssv6200_reg.h	5766;"	d
+SET_EN_AUTO_RTS	smac/hal/ssv6006c/ssv6006C_reg.h	9756;"	d
+SET_EN_STAT_FINISH_INT	smac/hal/ssv6006c/ssv6006C_reg.h	10458;"	d
+SET_EN_UNEXPECT_WSID	smac/hal/ssv6006c/ssv6006C_reg.h	10457;"	d
+SET_EOSP_HW_ID	smac/hal/ssv6006c/ssv6006C_reg.h	10374;"	d
+SET_EOSP_H_QUEUE_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10373;"	d
+SET_ERP_PROTECT	include/ssv6200_reg.h	6119;"	d
+SET_ERP_PROTECT	smac/hal/ssv6006c/ssv6006C_reg.h	10098;"	d
+SET_ERR_FLAG_CLR	smac/hal/ssv6006c/ssv6006C_reg.h	9909;"	d
+SET_ERR_SW_RST_N	include/ssv6200_reg.h	8443;"	d
+SET_EVEN_PARITY	include/ssv6200_reg.h	5772;"	d
+SET_EVEN_PARITY	smac/hal/ssv6006c/ssv6006C_reg.h	9762;"	d
+SET_EXT_32K_SEL	include/ssv6200_reg.h	5501;"	d
+SET_EXT_MAC_MODE	include/ssv6200_reg.h	6660;"	d
+SET_EXT_MAC_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	10756;"	d
+SET_EXT_PHY_MODE	include/ssv6200_reg.h	6661;"	d
+SET_EXT_PHY_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	10757;"	d
+SET_F0_CIS_CONTENT_REG_127_96	include/ssv6200_reg.h	5659;"	d
+SET_F0_CIS_CONTENT_REG_127_96	smac/hal/ssv6006c/ssv6006C_reg.h	9655;"	d
+SET_F0_CIS_CONTENT_REG_159_128	include/ssv6200_reg.h	5660;"	d
+SET_F0_CIS_CONTENT_REG_159_128	smac/hal/ssv6006c/ssv6006C_reg.h	9656;"	d
+SET_F0_CIS_CONTENT_REG_191_160	include/ssv6200_reg.h	5661;"	d
+SET_F0_CIS_CONTENT_REG_191_160	smac/hal/ssv6006c/ssv6006C_reg.h	9657;"	d
+SET_F0_CIS_CONTENT_REG_223_192	include/ssv6200_reg.h	5662;"	d
+SET_F0_CIS_CONTENT_REG_223_192	smac/hal/ssv6006c/ssv6006C_reg.h	9658;"	d
+SET_F0_CIS_CONTENT_REG_255_224	include/ssv6200_reg.h	5663;"	d
+SET_F0_CIS_CONTENT_REG_255_224	smac/hal/ssv6006c/ssv6006C_reg.h	9659;"	d
+SET_F0_CIS_CONTENT_REG_287_256	include/ssv6200_reg.h	5664;"	d
+SET_F0_CIS_CONTENT_REG_287_256	smac/hal/ssv6006c/ssv6006C_reg.h	9660;"	d
+SET_F0_CIS_CONTENT_REG_319_288	include/ssv6200_reg.h	5665;"	d
+SET_F0_CIS_CONTENT_REG_319_288	smac/hal/ssv6006c/ssv6006C_reg.h	9661;"	d
+SET_F0_CIS_CONTENT_REG_31_0	include/ssv6200_reg.h	5656;"	d
+SET_F0_CIS_CONTENT_REG_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	9652;"	d
+SET_F0_CIS_CONTENT_REG_351_320	include/ssv6200_reg.h	5666;"	d
+SET_F0_CIS_CONTENT_REG_351_320	smac/hal/ssv6006c/ssv6006C_reg.h	9662;"	d
+SET_F0_CIS_CONTENT_REG_383_352	include/ssv6200_reg.h	5667;"	d
+SET_F0_CIS_CONTENT_REG_383_352	smac/hal/ssv6006c/ssv6006C_reg.h	9663;"	d
+SET_F0_CIS_CONTENT_REG_415_384	include/ssv6200_reg.h	5668;"	d
+SET_F0_CIS_CONTENT_REG_415_384	smac/hal/ssv6006c/ssv6006C_reg.h	9664;"	d
+SET_F0_CIS_CONTENT_REG_447_416	include/ssv6200_reg.h	5669;"	d
+SET_F0_CIS_CONTENT_REG_447_416	smac/hal/ssv6006c/ssv6006C_reg.h	9665;"	d
+SET_F0_CIS_CONTENT_REG_479_448	include/ssv6200_reg.h	5670;"	d
+SET_F0_CIS_CONTENT_REG_479_448	smac/hal/ssv6006c/ssv6006C_reg.h	9666;"	d
+SET_F0_CIS_CONTENT_REG_511_480	include/ssv6200_reg.h	5671;"	d
+SET_F0_CIS_CONTENT_REG_511_480	smac/hal/ssv6006c/ssv6006C_reg.h	9667;"	d
+SET_F0_CIS_CONTENT_REG_63_32	include/ssv6200_reg.h	5657;"	d
+SET_F0_CIS_CONTENT_REG_63_32	smac/hal/ssv6006c/ssv6006C_reg.h	9653;"	d
+SET_F0_CIS_CONTENT_REG_95_64	include/ssv6200_reg.h	5658;"	d
+SET_F0_CIS_CONTENT_REG_95_64	smac/hal/ssv6006c/ssv6006C_reg.h	9654;"	d
+SET_F1_BLOCK_SIZE_0_REG	include/ssv6200_reg.h	5623;"	d
+SET_F1_CIS_CONTENT_REG_127_96	include/ssv6200_reg.h	5675;"	d
+SET_F1_CIS_CONTENT_REG_127_96	smac/hal/ssv6006c/ssv6006C_reg.h	9671;"	d
+SET_F1_CIS_CONTENT_REG_159_128	include/ssv6200_reg.h	5676;"	d
+SET_F1_CIS_CONTENT_REG_159_128	smac/hal/ssv6006c/ssv6006C_reg.h	9672;"	d
+SET_F1_CIS_CONTENT_REG_191_160	include/ssv6200_reg.h	5677;"	d
+SET_F1_CIS_CONTENT_REG_191_160	smac/hal/ssv6006c/ssv6006C_reg.h	9673;"	d
+SET_F1_CIS_CONTENT_REG_223_192	include/ssv6200_reg.h	5678;"	d
+SET_F1_CIS_CONTENT_REG_223_192	smac/hal/ssv6006c/ssv6006C_reg.h	9674;"	d
+SET_F1_CIS_CONTENT_REG_255_224	include/ssv6200_reg.h	5679;"	d
+SET_F1_CIS_CONTENT_REG_255_224	smac/hal/ssv6006c/ssv6006C_reg.h	9675;"	d
+SET_F1_CIS_CONTENT_REG_287_256	include/ssv6200_reg.h	5680;"	d
+SET_F1_CIS_CONTENT_REG_287_256	smac/hal/ssv6006c/ssv6006C_reg.h	9676;"	d
+SET_F1_CIS_CONTENT_REG_319_288	include/ssv6200_reg.h	5681;"	d
+SET_F1_CIS_CONTENT_REG_319_288	smac/hal/ssv6006c/ssv6006C_reg.h	9677;"	d
+SET_F1_CIS_CONTENT_REG_31_0	include/ssv6200_reg.h	5672;"	d
+SET_F1_CIS_CONTENT_REG_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	9668;"	d
+SET_F1_CIS_CONTENT_REG_351_320	include/ssv6200_reg.h	5682;"	d
+SET_F1_CIS_CONTENT_REG_351_320	smac/hal/ssv6006c/ssv6006C_reg.h	9678;"	d
+SET_F1_CIS_CONTENT_REG_383_352	include/ssv6200_reg.h	5683;"	d
+SET_F1_CIS_CONTENT_REG_383_352	smac/hal/ssv6006c/ssv6006C_reg.h	9679;"	d
+SET_F1_CIS_CONTENT_REG_415_384	include/ssv6200_reg.h	5684;"	d
+SET_F1_CIS_CONTENT_REG_415_384	smac/hal/ssv6006c/ssv6006C_reg.h	9680;"	d
+SET_F1_CIS_CONTENT_REG_447_416	include/ssv6200_reg.h	5685;"	d
+SET_F1_CIS_CONTENT_REG_447_416	smac/hal/ssv6006c/ssv6006C_reg.h	9681;"	d
+SET_F1_CIS_CONTENT_REG_479_448	include/ssv6200_reg.h	5686;"	d
+SET_F1_CIS_CONTENT_REG_479_448	smac/hal/ssv6006c/ssv6006C_reg.h	9682;"	d
+SET_F1_CIS_CONTENT_REG_511_480	include/ssv6200_reg.h	5687;"	d
+SET_F1_CIS_CONTENT_REG_511_480	smac/hal/ssv6006c/ssv6006C_reg.h	9683;"	d
+SET_F1_CIS_CONTENT_REG_63_32	include/ssv6200_reg.h	5673;"	d
+SET_F1_CIS_CONTENT_REG_63_32	smac/hal/ssv6006c/ssv6006C_reg.h	9669;"	d
+SET_F1_CIS_CONTENT_REG_95_64	include/ssv6200_reg.h	5674;"	d
+SET_F1_CIS_CONTENT_REG_95_64	smac/hal/ssv6006c/ssv6006C_reg.h	9670;"	d
+SET_FAST_CLK	smac/hal/ssv6006c/ssv6006C_reg.h	10272;"	d
+SET_FBR_100H_REG	include/ssv6200_reg.h	5651;"	d
+SET_FBR_100H_REG	smac/hal/ssv6006c/ssv6006C_reg.h	9647;"	d
+SET_FBR_101H_REG	include/ssv6200_reg.h	5654;"	d
+SET_FBR_101H_REG	smac/hal/ssv6006c/ssv6006C_reg.h	9650;"	d
+SET_FBR_109H_REG	include/ssv6200_reg.h	5655;"	d
+SET_FBR_109H_REG	smac/hal/ssv6006c/ssv6006C_reg.h	9651;"	d
+SET_FBUS_DMAC_BLOCK0	smac/hal/ssv6006c/ssv6006C_reg.h	9086;"	d
+SET_FBUS_DMAC_BLOCK1	smac/hal/ssv6006c/ssv6006C_reg.h	9103;"	d
+SET_FBUS_DMAC_CH0_CLR_ERR	smac/hal/ssv6006c/ssv6006C_reg.h	9118;"	d
+SET_FBUS_DMAC_CH0_CLR_TR	smac/hal/ssv6006c/ssv6006C_reg.h	9116;"	d
+SET_FBUS_DMAC_CH0_PRIOR	smac/hal/ssv6006c/ssv6006C_reg.h	9087;"	d
+SET_FBUS_DMAC_CH1_CLR_ERR	smac/hal/ssv6006c/ssv6006C_reg.h	9119;"	d
+SET_FBUS_DMAC_CH1_CLR_TR	smac/hal/ssv6006c/ssv6006C_reg.h	9117;"	d
+SET_FBUS_DMAC_CH1_PRIOR	smac/hal/ssv6006c/ssv6006C_reg.h	9104;"	d
+SET_FBUS_DMAC_CH_DEMASK_ERR	smac/hal/ssv6006c/ssv6006C_reg.h	9115;"	d
+SET_FBUS_DMAC_CH_DEMASK_TR	smac/hal/ssv6006c/ssv6006C_reg.h	9114;"	d
+SET_FBUS_DMAC_CH_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9125;"	d
+SET_FBUS_DMAC_CH_ERR_TR	smac/hal/ssv6006c/ssv6006C_reg.h	9111;"	d
+SET_FBUS_DMAC_CH_RAW_TR	smac/hal/ssv6006c/ssv6006C_reg.h	9110;"	d
+SET_FBUS_DMAC_CH_STATUSERR_TR	smac/hal/ssv6006c/ssv6006C_reg.h	9113;"	d
+SET_FBUS_DMAC_CH_STATUSTR_TR	smac/hal/ssv6006c/ssv6006C_reg.h	9112;"	d
+SET_FBUS_DMAC_DAR0	smac/hal/ssv6006c/ssv6006C_reg.h	9077;"	d
+SET_FBUS_DMAC_DAR1	smac/hal/ssv6006c/ssv6006C_reg.h	9094;"	d
+SET_FBUS_DMAC_DINC0	smac/hal/ssv6006c/ssv6006C_reg.h	9081;"	d
+SET_FBUS_DMAC_DINC1	smac/hal/ssv6006c/ssv6006C_reg.h	9098;"	d
+SET_FBUS_DMAC_DISEN_SHS_DST_REQ	smac/hal/ssv6006c/ssv6006C_reg.h	9121;"	d
+SET_FBUS_DMAC_DISEN_SHS_DST_SREQ	smac/hal/ssv6006c/ssv6006C_reg.h	9123;"	d
+SET_FBUS_DMAC_DISEN_SHS_SRC_REQ	smac/hal/ssv6006c/ssv6006C_reg.h	9120;"	d
+SET_FBUS_DMAC_DISEN_SHS_SRC_SREQ	smac/hal/ssv6006c/ssv6006C_reg.h	9122;"	d
+SET_FBUS_DMAC_DST_HS_BUS_SEL0	smac/hal/ssv6006c/ssv6006C_reg.h	9092;"	d
+SET_FBUS_DMAC_DST_HS_BUS_SEL1	smac/hal/ssv6006c/ssv6006C_reg.h	9109;"	d
+SET_FBUS_DMAC_DST_MSIZE0	smac/hal/ssv6006c/ssv6006C_reg.h	9083;"	d
+SET_FBUS_DMAC_DST_MSIZE1	smac/hal/ssv6006c/ssv6006C_reg.h	9100;"	d
+SET_FBUS_DMAC_DST_TR_WIDTH0	smac/hal/ssv6006c/ssv6006C_reg.h	9079;"	d
+SET_FBUS_DMAC_DST_TR_WIDTH1	smac/hal/ssv6006c/ssv6006C_reg.h	9096;"	d
+SET_FBUS_DMAC_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9124;"	d
+SET_FBUS_DMAC_FC_MODE0	smac/hal/ssv6006c/ssv6006C_reg.h	9085;"	d
+SET_FBUS_DMAC_FC_MODE1	smac/hal/ssv6006c/ssv6006C_reg.h	9102;"	d
+SET_FBUS_DMAC_HS_SEL_DST0	smac/hal/ssv6006c/ssv6006C_reg.h	9088;"	d
+SET_FBUS_DMAC_HS_SEL_DST1	smac/hal/ssv6006c/ssv6006C_reg.h	9105;"	d
+SET_FBUS_DMAC_HS_SEL_SRC0	smac/hal/ssv6006c/ssv6006C_reg.h	9089;"	d
+SET_FBUS_DMAC_HS_SEL_SRC1	smac/hal/ssv6006c/ssv6006C_reg.h	9106;"	d
+SET_FBUS_DMAC_INTR_EN0	smac/hal/ssv6006c/ssv6006C_reg.h	9078;"	d
+SET_FBUS_DMAC_INTR_EN1	smac/hal/ssv6006c/ssv6006C_reg.h	9095;"	d
+SET_FBUS_DMAC_MAX_BURST_LEN0	smac/hal/ssv6006c/ssv6006C_reg.h	9090;"	d
+SET_FBUS_DMAC_MAX_BURST_LEN1	smac/hal/ssv6006c/ssv6006C_reg.h	9107;"	d
+SET_FBUS_DMAC_SAR0	smac/hal/ssv6006c/ssv6006C_reg.h	9076;"	d
+SET_FBUS_DMAC_SAR1	smac/hal/ssv6006c/ssv6006C_reg.h	9093;"	d
+SET_FBUS_DMAC_SINC0	smac/hal/ssv6006c/ssv6006C_reg.h	9082;"	d
+SET_FBUS_DMAC_SINC1	smac/hal/ssv6006c/ssv6006C_reg.h	9099;"	d
+SET_FBUS_DMAC_SRC_HS_BUS_SEL0	smac/hal/ssv6006c/ssv6006C_reg.h	9091;"	d
+SET_FBUS_DMAC_SRC_HS_BUS_SEL1	smac/hal/ssv6006c/ssv6006C_reg.h	9108;"	d
+SET_FBUS_DMAC_SRC_MSIZE0	smac/hal/ssv6006c/ssv6006C_reg.h	9084;"	d
+SET_FBUS_DMAC_SRC_MSIZE1	smac/hal/ssv6006c/ssv6006C_reg.h	9101;"	d
+SET_FBUS_DMAC_SRC_TR_WIDTH0	smac/hal/ssv6006c/ssv6006C_reg.h	9080;"	d
+SET_FBUS_DMAC_SRC_TR_WIDTH1	smac/hal/ssv6006c/ssv6006C_reg.h	9097;"	d
+SET_FBUS_SRAM_ERRCK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9366;"	d
+SET_FBUS_SRAM_ERR_INT	smac/hal/ssv6006c/ssv6006C_reg.h	9371;"	d
+SET_FENCE_HIT_ADR	smac/hal/ssv6006c/ssv6006C_reg.h	9362;"	d
+SET_FENCE_HIT_CLR	include/ssv6200_reg.h	4996;"	d
+SET_FENCE_HIT_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9367;"	d
+SET_FENCE_HIT_INT	include/ssv6200_reg.h	4998;"	d
+SET_FENCE_HIT_INT	smac/hal/ssv6006c/ssv6006C_reg.h	9372;"	d
+SET_FF0_CNT	include/ssv6200_reg.h	7195;"	d
+SET_FF0_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15650;"	d
+SET_FF0_EMPTY	include/ssv6200_reg.h	7189;"	d
+SET_FF0_EMPTY	smac/hal/ssv6006c/ssv6006C_reg.h	15642;"	d
+SET_FF10_CNT	include/ssv6200_reg.h	7203;"	d
+SET_FF10_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15658;"	d
+SET_FF11_CNT	include/ssv6200_reg.h	7204;"	d
+SET_FF11_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15659;"	d
+SET_FF12_CNT	include/ssv6200_reg.h	7205;"	d
+SET_FF12_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15660;"	d
+SET_FF13_CNT	include/ssv6200_reg.h	7206;"	d
+SET_FF13_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15661;"	d
+SET_FF14_CNT	include/ssv6200_reg.h	7207;"	d
+SET_FF14_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15662;"	d
+SET_FF15_CNT	include/ssv6200_reg.h	7208;"	d
+SET_FF15_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15663;"	d
+SET_FF1_CNT	include/ssv6200_reg.h	7196;"	d
+SET_FF1_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15651;"	d
+SET_FF2_CNT	include/ssv6200_reg.h	7210;"	d
+SET_FF2_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15665;"	d
+SET_FF2_EMPTY	smac/hal/ssv6006c/ssv6006C_reg.h	15644;"	d
+SET_FF3_CNT	include/ssv6200_reg.h	7197;"	d
+SET_FF3_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15652;"	d
+SET_FF4_CNT	include/ssv6200_reg.h	7209;"	d
+SET_FF4_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15664;"	d
+SET_FF5_CNT	include/ssv6200_reg.h	7198;"	d
+SET_FF5_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15653;"	d
+SET_FF6_CNT	include/ssv6200_reg.h	7199;"	d
+SET_FF6_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15654;"	d
+SET_FF7_CNT	include/ssv6200_reg.h	7200;"	d
+SET_FF7_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15655;"	d
+SET_FF8_CNT	include/ssv6200_reg.h	7201;"	d
+SET_FF8_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15656;"	d
+SET_FF9_CNT	include/ssv6200_reg.h	7202;"	d
+SET_FF9_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15657;"	d
+SET_FFO0_CNT	include/ssv6200_reg.h	7304;"	d
+SET_FFO0_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15761;"	d
+SET_FFO10_CNT	include/ssv6200_reg.h	7314;"	d
+SET_FFO10_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15771;"	d
+SET_FFO11_CNT	include/ssv6200_reg.h	7315;"	d
+SET_FFO11_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15772;"	d
+SET_FFO12_CNT	include/ssv6200_reg.h	7316;"	d
+SET_FFO12_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15773;"	d
+SET_FFO13_CNT	include/ssv6200_reg.h	7317;"	d
+SET_FFO13_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15774;"	d
+SET_FFO14_CNT	include/ssv6200_reg.h	7318;"	d
+SET_FFO14_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15775;"	d
+SET_FFO15_CNT	include/ssv6200_reg.h	7319;"	d
+SET_FFO15_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15776;"	d
+SET_FFO1_CNT	include/ssv6200_reg.h	7305;"	d
+SET_FFO1_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15762;"	d
+SET_FFO2_CNT	include/ssv6200_reg.h	7306;"	d
+SET_FFO2_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15763;"	d
+SET_FFO3_CNT	include/ssv6200_reg.h	7307;"	d
+SET_FFO3_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15764;"	d
+SET_FFO4_CNT	include/ssv6200_reg.h	7308;"	d
+SET_FFO4_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15765;"	d
+SET_FFO5_CNT	include/ssv6200_reg.h	7309;"	d
+SET_FFO5_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15766;"	d
+SET_FFO6_CNT	include/ssv6200_reg.h	7310;"	d
+SET_FFO6_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15767;"	d
+SET_FFO7_CNT	include/ssv6200_reg.h	7311;"	d
+SET_FFO7_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15768;"	d
+SET_FFO8_CNT	include/ssv6200_reg.h	7312;"	d
+SET_FFO8_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15769;"	d
+SET_FFO9_CNT	include/ssv6200_reg.h	7313;"	d
+SET_FFO9_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15770;"	d
+SET_FIFODATA_ERR	include/ssv6200_reg.h	5788;"	d
+SET_FIFODATA_ERR	smac/hal/ssv6006c/ssv6006C_reg.h	9779;"	d
+SET_FIFOS_ENABLED	include/ssv6200_reg.h	5801;"	d
+SET_FIFOS_ENABLED	smac/hal/ssv6006c/ssv6006C_reg.h	9794;"	d
+SET_FIFO_EN	include/ssv6200_reg.h	5762;"	d
+SET_FIFO_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9752;"	d
+SET_FIQ_RAW	include/ssv6200_reg.h	5884;"	d
+SET_FIQ_STATUS	include/ssv6200_reg.h	5882;"	d
+SET_FLASH_ADDR	include/ssv6200_reg.h	6037;"	d
+SET_FLASH_BACK_DLY	include/ssv6200_reg.h	6045;"	d
+SET_FLASH_BACK_DLY	smac/hal/ssv6006c/ssv6006C_reg.h	9876;"	d
+SET_FLASH_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9302;"	d
+SET_FLASH_CLK_WIDTH	include/ssv6200_reg.h	6046;"	d
+SET_FLASH_CMD_CLR	include/ssv6200_reg.h	6038;"	d
+SET_FLASH_DMA_CLR	include/ssv6200_reg.h	6039;"	d
+SET_FLASH_DMA_LEN	include/ssv6200_reg.h	6043;"	d
+SET_FLASH_FRONT_DLY	include/ssv6200_reg.h	6044;"	d
+SET_FLASH_FRONT_DLY	smac/hal/ssv6006c/ssv6006C_reg.h	9875;"	d
+SET_FLS_CLK_IN_DLY_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	9894;"	d
+SET_FLS_CLK_OUT_DLY_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	9895;"	d
+SET_FLS_MISO_IN_DLY_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	9898;"	d
+SET_FLS_MISO_OUT_DLY_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	9899;"	d
+SET_FLS_MOSI_IN_DLY_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	9896;"	d
+SET_FLS_MOSI_OUT_DLY_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	9897;"	d
+SET_FLS_NC_IN_DLY_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	9902;"	d
+SET_FLS_NC_OUT_DLY_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	9903;"	d
+SET_FLS_REMAP	include/ssv6200_reg.h	6048;"	d
+SET_FLS_WP_IN_DLY_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	9900;"	d
+SET_FLS_WP_OUT_DLY_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	9901;"	d
+SET_FN1_DMA_RD_START_ADDR_REG	smac/hal/ssv6006c/ssv6006C_reg.h	9626;"	d
+SET_FN1_DMA_START_ADDR_REG	include/ssv6200_reg.h	5580;"	d
+SET_FN1_DMA_START_ADDR_REG	smac/hal/ssv6006c/ssv6006C_reg.h	9618;"	d
+SET_FORCE_GET_RK	include/ssv6200_reg.h	6242;"	d
+SET_FORCE_PARITY	include/ssv6200_reg.h	5773;"	d
+SET_FORCE_PARITY	smac/hal/ssv6006c/ssv6006C_reg.h	9763;"	d
+SET_FPGA_TO_GEMINIA_ADC_EDGE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	15975;"	d
+SET_FPGA_TO_GEMINIA_DAC_EDGE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	15974;"	d
+SET_FPGA_TO_GEMINIA_DAC_SIGN_SWAP	smac/hal/ssv6006c/ssv6006C_reg.h	15973;"	d
+SET_FRAME_LEN	include/ssv6200_reg.h	6196;"	d
+SET_FRAME_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	10214;"	d
+SET_FRAMING	smac/hal/ssv6006c/ssv6006C_reg.h	9803;"	d
+SET_FRAMING_ERR	include/ssv6200_reg.h	5784;"	d
+SET_FRAMING_ERR	smac/hal/ssv6006c/ssv6006C_reg.h	9775;"	d
+SET_FRM_CTRL	include/ssv6200_reg.h	6378;"	d
+SET_FRM_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	10367;"	d
+SET_FRONT_DLY	include/ssv6200_reg.h	5697;"	d
+SET_FRONT_DLY	smac/hal/ssv6006c/ssv6006C_reg.h	9689;"	d
+SET_FSM_SYSCTRL	smac/hal/ssv6006c/ssv6006C_reg.h	9356;"	d
+SET_FW_EVENT	smac/hal/ssv6006c/ssv6006C_reg.h	9385;"	d
+SET_G0_PKT_CLS_MIB_EN	include/ssv6200_reg.h	6772;"	d
+SET_G0_PKT_CLS_MIB_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10884;"	d
+SET_G0_PKT_CLS_ONGOING	include/ssv6200_reg.h	6773;"	d
+SET_G0_PKT_CLS_ONGOING	smac/hal/ssv6006c/ssv6006C_reg.h	10885;"	d
+SET_G1_PKT_CLS_MIB_EN	include/ssv6200_reg.h	6774;"	d
+SET_G1_PKT_CLS_MIB_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10886;"	d
+SET_G1_PKT_CLS_ONGOING	include/ssv6200_reg.h	6775;"	d
+SET_G1_PKT_CLS_ONGOING	smac/hal/ssv6006c/ssv6006C_reg.h	10887;"	d
+SET_GEMINIA_SAR_ADC_FSM_RDY	smac/hal/ssv6006c/ssv6006C_reg.h	11732;"	d
+SET_GET_RK	include/ssv6200_reg.h	6241;"	d
+SET_GN_CCA_CNT	include/ssv6200_reg.h	7957;"	d
+SET_GN_LENGTH_FIELD	include/ssv6200_reg.h	7958;"	d
+SET_GN_NOISE_PWR	include/ssv6200_reg.h	7948;"	d
+SET_GN_PACKET_CNT	include/ssv6200_reg.h	7956;"	d
+SET_GN_PACKET_ERR_CNT	include/ssv6200_reg.h	7955;"	d
+SET_GN_RCPI	include/ssv6200_reg.h	7949;"	d
+SET_GN_SERVICE_FIELD	include/ssv6200_reg.h	7959;"	d
+SET_GN_SIGNAL_PWR	include/ssv6200_reg.h	7950;"	d
+SET_GN_SNR	include/ssv6200_reg.h	7947;"	d
+SET_GPIO_10_ID	include/ssv6200_reg.h	5316;"	d
+SET_GPIO_11_ID	include/ssv6200_reg.h	5325;"	d
+SET_GPIO_12_ID	include/ssv6200_reg.h	5334;"	d
+SET_GPIO_13_ID	include/ssv6200_reg.h	5343;"	d
+SET_GPIO_14_ID	include/ssv6200_reg.h	5351;"	d
+SET_GPIO_15_IP_ID	include/ssv6200_reg.h	5428;"	d
+SET_GPIO_17_QP_ID	include/ssv6200_reg.h	5444;"	d
+SET_GPIO_19_ID	include/ssv6200_reg.h	5451;"	d
+SET_GPIO_1_ID	include/ssv6200_reg.h	5193;"	d
+SET_GPIO_20_ID	include/ssv6200_reg.h	5468;"	d
+SET_GPIO_21_ID	include/ssv6200_reg.h	5476;"	d
+SET_GPIO_2_ID	include/ssv6200_reg.h	5201;"	d
+SET_GPIO_3_ID	include/ssv6200_reg.h	5210;"	d
+SET_GPIO_9_ID	include/ssv6200_reg.h	5306;"	d
+SET_GPIO_CLK_EN	include/ssv6200_reg.h	4952;"	d
+SET_GPIO_INT_TRIGGER_OPTION	include/ssv6200_reg.h	5535;"	d
+SET_GPIO_INT_TRIGGER_OPTION	smac/hal/ssv6006c/ssv6006C_reg.h	9598;"	d
+SET_GPIO_LOG_STOP_SEL	include/ssv6200_reg.h	5498;"	d
+SET_GPIO_STOP_EN	include/ssv6200_reg.h	7392;"	d
+SET_GPIO_STOP_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9347;"	d
+SET_GPIO_STOP_POL	include/ssv6200_reg.h	7393;"	d
+SET_GPIO_STOP_POL	smac/hal/ssv6006c/ssv6006C_reg.h	9346;"	d
+SET_GPIO_STOP_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	9345;"	d
+SET_GPIO_SW_RST	include/ssv6200_reg.h	4918;"	d
+SET_GPIO_TEST_1_ID	include/ssv6200_reg.h	5157;"	d
+SET_GPIO_TEST_2_ID	include/ssv6200_reg.h	5166;"	d
+SET_GPIO_TEST_3_ID	include/ssv6200_reg.h	5175;"	d
+SET_GPIO_TEST_4_ID	include/ssv6200_reg.h	5183;"	d
+SET_GPIO_TEST_5_ID	include/ssv6200_reg.h	5218;"	d
+SET_GPIO_TEST_7_IN_ID	include/ssv6200_reg.h	5436;"	d
+SET_GPIO_TEST_8_QN_ID	include/ssv6200_reg.h	5459;"	d
+SET_GPO_INT_POL	smac/hal/ssv6006c/ssv6006C_reg.h	10010;"	d
+SET_GRP_SCRT	include/ssv6200_reg.h	6744;"	d
+SET_GRP_SCRT	smac/hal/ssv6006c/ssv6006C_reg.h	10841;"	d
+SET_GRP_WSID	smac/hal/ssv6006c/ssv6006C_reg.h	10359;"	d
+SET_GURAN_USE_CTRL	include/ssv6200_reg.h	6752;"	d
+SET_GURAN_USE_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	10855;"	d
+SET_GURAN_USE_EN	include/ssv6200_reg.h	6751;"	d
+SET_GURAN_USE_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10854;"	d
+SET_HALT_CH0	include/ssv6200_reg.h	7226;"	d
+SET_HALT_CH1	include/ssv6200_reg.h	7227;"	d
+SET_HALT_CH1	smac/hal/ssv6006c/ssv6006C_reg.h	15684;"	d
+SET_HALT_CH10	include/ssv6200_reg.h	7236;"	d
+SET_HALT_CH10	smac/hal/ssv6006c/ssv6006C_reg.h	15692;"	d
+SET_HALT_CH11	include/ssv6200_reg.h	7237;"	d
+SET_HALT_CH11	smac/hal/ssv6006c/ssv6006C_reg.h	15693;"	d
+SET_HALT_CH12	include/ssv6200_reg.h	7238;"	d
+SET_HALT_CH12	smac/hal/ssv6006c/ssv6006C_reg.h	15694;"	d
+SET_HALT_CH13	include/ssv6200_reg.h	7239;"	d
+SET_HALT_CH13	smac/hal/ssv6006c/ssv6006C_reg.h	15695;"	d
+SET_HALT_CH14	include/ssv6200_reg.h	7240;"	d
+SET_HALT_CH14	smac/hal/ssv6006c/ssv6006C_reg.h	15696;"	d
+SET_HALT_CH15	include/ssv6200_reg.h	7241;"	d
+SET_HALT_CH2	include/ssv6200_reg.h	7228;"	d
+SET_HALT_CH3	include/ssv6200_reg.h	7229;"	d
+SET_HALT_CH3	smac/hal/ssv6006c/ssv6006C_reg.h	15685;"	d
+SET_HALT_CH4	include/ssv6200_reg.h	7230;"	d
+SET_HALT_CH4	smac/hal/ssv6006c/ssv6006C_reg.h	15686;"	d
+SET_HALT_CH5	include/ssv6200_reg.h	7231;"	d
+SET_HALT_CH5	smac/hal/ssv6006c/ssv6006C_reg.h	15687;"	d
+SET_HALT_CH6	include/ssv6200_reg.h	7232;"	d
+SET_HALT_CH6	smac/hal/ssv6006c/ssv6006C_reg.h	15688;"	d
+SET_HALT_CH7	include/ssv6200_reg.h	7233;"	d
+SET_HALT_CH7	smac/hal/ssv6006c/ssv6006C_reg.h	15689;"	d
+SET_HALT_CH8	include/ssv6200_reg.h	7234;"	d
+SET_HALT_CH8	smac/hal/ssv6006c/ssv6006C_reg.h	15690;"	d
+SET_HALT_CH9	include/ssv6200_reg.h	7235;"	d
+SET_HALT_CH9	smac/hal/ssv6006c/ssv6006C_reg.h	15691;"	d
+SET_HAS_MANUAL_BUF	smac/hal/ssv6006c/ssv6006C_reg.h	10135;"	d
+SET_HBURST_LOCK	include/ssv6200_reg.h	5012;"	d
+SET_HBURST_LOCK	smac/hal/ssv6006c/ssv6006C_reg.h	9361;"	d
+SET_HBUSREQ_LOCK	include/ssv6200_reg.h	5011;"	d
+SET_HBUSREQ_LOCK	smac/hal/ssv6006c/ssv6006C_reg.h	9360;"	d
+SET_HCI_BULK_IN_HOST_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	10150;"	d
+SET_HCI_BULK_IN_TIME_OUT	smac/hal/ssv6006c/ssv6006C_reg.h	10151;"	d
+SET_HCI_CLK_EN	include/ssv6200_reg.h	6700;"	d
+SET_HCI_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10796;"	d
+SET_HCI_ENG_CLK_EN	include/ssv6200_reg.h	6712;"	d
+SET_HCI_ENG_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10808;"	d
+SET_HCI_INPUT_FF_CNT	include/ssv6200_reg.h	5551;"	d
+SET_HCI_INPUT_FF_CNT2	include/ssv6200_reg.h	5622;"	d
+SET_HCI_INPUT_QUEUE_FULL	include/ssv6200_reg.h	5609;"	d
+SET_HCI_INQ_SEL	include/ssv6200_reg.h	6127;"	d
+SET_HCI_INT_1	include/ssv6200_reg.h	5899;"	d
+SET_HCI_INT_1_SD	include/ssv6200_reg.h	5968;"	d
+SET_HCI_IN_QUE_EMPTY	include/ssv6200_reg.h	5554;"	d
+SET_HCI_IN_QUE_EMPTY2	include/ssv6200_reg.h	5612;"	d
+SET_HCI_MB_MAX_CNT	include/ssv6200_reg.h	6163;"	d
+SET_HCI_MB_MAX_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	10158;"	d
+SET_HCI_MONITOR_REG0	smac/hal/ssv6006c/ssv6006C_reg.h	10152;"	d
+SET_HCI_MONITOR_REG1	include/ssv6200_reg.h	6159;"	d
+SET_HCI_MONITOR_REG2	include/ssv6200_reg.h	6160;"	d
+SET_HCI_MONITOR_REG2	smac/hal/ssv6006c/ssv6006C_reg.h	10153;"	d
+SET_HCI_MONITOR_REG3	smac/hal/ssv6006c/ssv6006C_reg.h	10154;"	d
+SET_HCI_MONITOR_REG4	smac/hal/ssv6006c/ssv6006C_reg.h	10155;"	d
+SET_HCI_MONITOR_REG5	smac/hal/ssv6006c/ssv6006C_reg.h	10156;"	d
+SET_HCI_OUTPUT_FF_CNT	include/ssv6200_reg.h	5552;"	d
+SET_HCI_OUTPUT_FF_CNT2	include/ssv6200_reg.h	5621;"	d
+SET_HCI_OUTPUT_FF_CNT_0	include/ssv6200_reg.h	5620;"	d
+SET_HCI_PENDING_RX_MPDU_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	10145;"	d
+SET_HCI_PROC_CNT	include/ssv6200_reg.h	6166;"	d
+SET_HCI_PROC_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	10159;"	d
+SET_HCI_RX_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10107;"	d
+SET_HCI_RX_FORM_0	smac/hal/ssv6006c/ssv6006C_reg.h	10109;"	d
+SET_HCI_RX_FORM_1	smac/hal/ssv6006c/ssv6006C_reg.h	10108;"	d
+SET_HCI_RX_HALT	smac/hal/ssv6006c/ssv6006C_reg.h	10146;"	d
+SET_HCI_RX_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	10115;"	d
+SET_HCI_RX_MPDU_DEQUE	smac/hal/ssv6006c/ssv6006C_reg.h	10149;"	d
+SET_HCI_STATE_MONITOR	include/ssv6200_reg.h	6156;"	d
+SET_HCI_ST_TIMEOUT_MONITOR	include/ssv6200_reg.h	6157;"	d
+SET_HCI_SW_RST	include/ssv6200_reg.h	6663;"	d
+SET_HCI_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	10758;"	d
+SET_HCI_TRX_FINISH	include/ssv6200_reg.h	5549;"	d
+SET_HCI_TRX_FINISH2	include/ssv6200_reg.h	5607;"	d
+SET_HCI_TRX_FINISH3	include/ssv6200_reg.h	5611;"	d
+SET_HCI_TX_AGG_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10106;"	d
+SET_HCI_TX_ALLOC_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	10162;"	d
+SET_HCI_TX_ALLOC_CNT_31_0	include/ssv6200_reg.h	6164;"	d
+SET_HCI_TX_ALLOC_CNT_47_32	include/ssv6200_reg.h	6165;"	d
+SET_HCI_TX_ALLOC_TIME	smac/hal/ssv6006c/ssv6006C_reg.h	10163;"	d
+SET_HCI_TX_ALLOC_TIME_31_0	include/ssv6200_reg.h	6161;"	d
+SET_HCI_TX_ALLOC_TIME_47_32	include/ssv6200_reg.h	6162;"	d
+SET_HDR_STRIP	include/ssv6200_reg.h	6118;"	d
+SET_HDR_STRIP	smac/hal/ssv6006c/ssv6006C_reg.h	10097;"	d
+SET_HIF_LOOP_BACK	smac/hal/ssv6006c/ssv6006C_reg.h	10147;"	d
+SET_HOST_CMD_COUNTER	include/ssv6200_reg.h	6148;"	d
+SET_HOST_CMD_COUNTER	smac/hal/ssv6006c/ssv6006C_reg.h	10169;"	d
+SET_HOST_EVENT	smac/hal/ssv6006c/ssv6006C_reg.h	9386;"	d
+SET_HOST_EVENT_COUNTER	include/ssv6200_reg.h	6149;"	d
+SET_HOST_EVENT_COUNTER	smac/hal/ssv6006c/ssv6006C_reg.h	10168;"	d
+SET_HOST_PATH	include/ssv6200_reg.h	5691;"	d
+SET_HOST_RX_FAIL_COUNTER	include/ssv6200_reg.h	6155;"	d
+SET_HOST_RX_FAIL_COUNTER	smac/hal/ssv6006c/ssv6006C_reg.h	10172;"	d
+SET_HOST_TRIGGERED_RX_INT	include/ssv6200_reg.h	5527;"	d
+SET_HOST_TRIGGERED_RX_INT	smac/hal/ssv6006c/ssv6006C_reg.h	9590;"	d
+SET_HOST_TRIGGERED_TX_INT	include/ssv6200_reg.h	5528;"	d
+SET_HOST_TRIGGERED_TX_INT	smac/hal/ssv6006c/ssv6006C_reg.h	9591;"	d
+SET_HOST_TX_FAIL_COUNTER	include/ssv6200_reg.h	6154;"	d
+SET_HOST_TX_FAIL_COUNTER	smac/hal/ssv6006c/ssv6006C_reg.h	10173;"	d
+SET_HOST_WAKE_WIFI	smac/hal/ssv6006c/ssv6006C_reg.h	9425;"	d
+SET_HOST_WAKE_WIFI_POL	smac/hal/ssv6006c/ssv6006C_reg.h	9426;"	d
+SET_HSUART_ACTS	smac/hal/ssv6006c/ssv6006C_reg.h	9836;"	d
+SET_HSUART_ARTS	smac/hal/ssv6006c/ssv6006C_reg.h	9835;"	d
+SET_HSUART_BI	smac/hal/ssv6006c/ssv6006C_reg.h	9841;"	d
+SET_HSUART_CTS	smac/hal/ssv6006c/ssv6006C_reg.h	9849;"	d
+SET_HSUART_DCR	smac/hal/ssv6006c/ssv6006C_reg.h	9852;"	d
+SET_HSUART_DCTS	smac/hal/ssv6006c/ssv6006C_reg.h	9845;"	d
+SET_HSUART_DDCD	smac/hal/ssv6006c/ssv6006C_reg.h	9848;"	d
+SET_HSUART_DDSR	smac/hal/ssv6006c/ssv6006C_reg.h	9846;"	d
+SET_HSUART_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	9862;"	d
+SET_HSUART_DLAB	smac/hal/ssv6006c/ssv6006C_reg.h	9829;"	d
+SET_HSUART_DMA	smac/hal/ssv6006c/ssv6006C_reg.h	9822;"	d
+SET_HSUART_DMA_RX_END_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	9866;"	d
+SET_HSUART_DMA_RX_RPT	smac/hal/ssv6006c/ssv6006C_reg.h	9868;"	d
+SET_HSUART_DMA_RX_STR_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	9865;"	d
+SET_HSUART_DMA_RX_WPT	smac/hal/ssv6006c/ssv6006C_reg.h	9867;"	d
+SET_HSUART_DMA_TX_END_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	9870;"	d
+SET_HSUART_DMA_TX_RPT	smac/hal/ssv6006c/ssv6006C_reg.h	9872;"	d
+SET_HSUART_DMA_TX_STR_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	9869;"	d
+SET_HSUART_DMA_TX_WPT	smac/hal/ssv6006c/ssv6006C_reg.h	9871;"	d
+SET_HSUART_DR	smac/hal/ssv6006c/ssv6006C_reg.h	9837;"	d
+SET_HSUART_DSR	smac/hal/ssv6006c/ssv6006C_reg.h	9850;"	d
+SET_HSUART_DTS	smac/hal/ssv6006c/ssv6006C_reg.h	9830;"	d
+SET_HSUART_ENABCTXTHR	smac/hal/ssv6006c/ssv6006C_reg.h	9816;"	d
+SET_HSUART_ENABDMARXEND	smac/hal/ssv6006c/ssv6006C_reg.h	9817;"	d
+SET_HSUART_ENABDMATXEND	smac/hal/ssv6006c/ssv6006C_reg.h	9818;"	d
+SET_HSUART_ENABLNSTAT	smac/hal/ssv6006c/ssv6006C_reg.h	9814;"	d
+SET_HSUART_ENABMDSTAT	smac/hal/ssv6006c/ssv6006C_reg.h	9815;"	d
+SET_HSUART_ENABRXBUFF	smac/hal/ssv6006c/ssv6006C_reg.h	9812;"	d
+SET_HSUART_ENABTXBUFF	smac/hal/ssv6006c/ssv6006C_reg.h	9813;"	d
+SET_HSUART_ERF	smac/hal/ssv6006c/ssv6006C_reg.h	9844;"	d
+SET_HSUART_FE	smac/hal/ssv6006c/ssv6006C_reg.h	9840;"	d
+SET_HSUART_FIFOE	smac/hal/ssv6006c/ssv6006C_reg.h	9819;"	d
+SET_HSUART_FRAC	smac/hal/ssv6006c/ssv6006C_reg.h	9863;"	d
+SET_HSUART_IFIFOE1	smac/hal/ssv6006c/ssv6006C_reg.h	9861;"	d
+SET_HSUART_IFOFOE0	smac/hal/ssv6006c/ssv6006C_reg.h	9860;"	d
+SET_HSUART_IIR	smac/hal/ssv6006c/ssv6006C_reg.h	9858;"	d
+SET_HSUART_INT	smac/hal/ssv6006c/ssv6006C_reg.h	9864;"	d
+SET_HSUART_LOOP1	smac/hal/ssv6006c/ssv6006C_reg.h	9834;"	d
+SET_HSUART_OE	smac/hal/ssv6006c/ssv6006C_reg.h	9838;"	d
+SET_HSUART_OUT1	smac/hal/ssv6006c/ssv6006C_reg.h	9832;"	d
+SET_HSUART_OUT2	smac/hal/ssv6006c/ssv6006C_reg.h	9833;"	d
+SET_HSUART_PE	smac/hal/ssv6006c/ssv6006C_reg.h	9839;"	d
+SET_HSUART_PEN	smac/hal/ssv6006c/ssv6006C_reg.h	9826;"	d
+SET_HSUART_RI	smac/hal/ssv6006c/ssv6006C_reg.h	9851;"	d
+SET_HSUART_RTS	smac/hal/ssv6006c/ssv6006C_reg.h	9831;"	d
+SET_HSUART_RTS_AUTO_TH_H	smac/hal/ssv6006c/ssv6006C_reg.h	9855;"	d
+SET_HSUART_RTS_AUTO_TH_L	smac/hal/ssv6006c/ssv6006C_reg.h	9854;"	d
+SET_HSUART_RXD	smac/hal/ssv6006c/ssv6006C_reg.h	9811;"	d
+SET_HSUART_RX_FIFO_RST	smac/hal/ssv6006c/ssv6006C_reg.h	9820;"	d
+SET_HSUART_RX_TRIG_LV	smac/hal/ssv6006c/ssv6006C_reg.h	9823;"	d
+SET_HSUART_SB	smac/hal/ssv6006c/ssv6006C_reg.h	9828;"	d
+SET_HSUART_SCR	smac/hal/ssv6006c/ssv6006C_reg.h	9853;"	d
+SET_HSUART_SP_EPS	smac/hal/ssv6006c/ssv6006C_reg.h	9827;"	d
+SET_HSUART_STB	smac/hal/ssv6006c/ssv6006C_reg.h	9825;"	d
+SET_HSUART_TERI	smac/hal/ssv6006c/ssv6006C_reg.h	9847;"	d
+SET_HSUART_THRE	smac/hal/ssv6006c/ssv6006C_reg.h	9842;"	d
+SET_HSUART_TSRE	smac/hal/ssv6006c/ssv6006C_reg.h	9843;"	d
+SET_HSUART_TXDMA_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	9859;"	d
+SET_HSUART_TX_FIFO_RST	smac/hal/ssv6006c/ssv6006C_reg.h	9821;"	d
+SET_HSUART_TX_THR_H	smac/hal/ssv6006c/ssv6006C_reg.h	9857;"	d
+SET_HSUART_TX_THR_L	smac/hal/ssv6006c/ssv6006C_reg.h	9856;"	d
+SET_HSUART_WLS	smac/hal/ssv6006c/ssv6006C_reg.h	9824;"	d
+SET_HS_ACCESS_MD	include/ssv6200_reg.h	8439;"	d
+SET_HS_CHANNEL	include/ssv6200_reg.h	8453;"	d
+SET_HS_DATA	include/ssv6200_reg.h	8455;"	d
+SET_HS_FLAG	include/ssv6200_reg.h	8451;"	d
+SET_HS_ID	include/ssv6200_reg.h	8452;"	d
+SET_HS_PAGE	include/ssv6200_reg.h	8454;"	d
+SET_HS_WR	include/ssv6200_reg.h	8450;"	d
+SET_HT20_G_RESP_RATE	smac/hal/ssv6006c/turismo_common.h	2937;"	d
+SET_HT40_G_RESP_RATE	smac/hal/ssv6006c/turismo_common.h	2948;"	d
+SET_HT_MODE	include/ssv6200_reg.h	6729;"	d
+SET_HT_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	10825;"	d
+SET_HW_PKTID	include/ssv6200_reg.h	7185;"	d
+SET_HW_PKTID	smac/hal/ssv6006c/ssv6006C_reg.h	15638;"	d
+SET_HW_PKTID_ALT	smac/hal/ssv6006c/ssv6006C_reg.h	15682;"	d
+SET_I2CMST_DISABLE_SLAVE	smac/hal/ssv6006c/ssv6006C_reg.h	9209;"	d
+SET_I2CMST_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9238;"	d
+SET_I2CMST_ENABLE_MASTER	smac/hal/ssv6006c/ssv6006C_reg.h	9206;"	d
+SET_I2CMST_RESTART_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9208;"	d
+SET_I2CMST_RXDONE_INT	smac/hal/ssv6006c/ssv6006C_reg.h	9223;"	d
+SET_I2CMST_RXDONE_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	9229;"	d
+SET_I2CMST_RXDONE_INT_STAR	smac/hal/ssv6006c/ssv6006C_reg.h	9235;"	d
+SET_I2CMST_RXF_INT	smac/hal/ssv6006c/ssv6006C_reg.h	9220;"	d
+SET_I2CMST_RXF_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	9226;"	d
+SET_I2CMST_RXF_INT_STAR	smac/hal/ssv6006c/ssv6006C_reg.h	9232;"	d
+SET_I2CMST_RXO_INT	smac/hal/ssv6006c/ssv6006C_reg.h	9219;"	d
+SET_I2CMST_RXO_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	9225;"	d
+SET_I2CMST_RXO_INT_STAR	smac/hal/ssv6006c/ssv6006C_reg.h	9231;"	d
+SET_I2CMST_RXU_INT	smac/hal/ssv6006c/ssv6006C_reg.h	9218;"	d
+SET_I2CMST_RXU_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	9224;"	d
+SET_I2CMST_RXU_INT_STAR	smac/hal/ssv6006c/ssv6006C_reg.h	9230;"	d
+SET_I2CMST_RX_1STBRDYR	smac/hal/ssv6006c/ssv6006C_reg.h	9215;"	d
+SET_I2CMST_RX_FIFO_TH	smac/hal/ssv6006c/ssv6006C_reg.h	9236;"	d
+SET_I2CMST_SCLK_H_WIDTH	smac/hal/ssv6006c/ssv6006C_reg.h	9216;"	d
+SET_I2CMST_SCLK_L_WIDTH	smac/hal/ssv6006c/ssv6006C_reg.h	9217;"	d
+SET_I2CMST_SPEED	smac/hal/ssv6006c/ssv6006C_reg.h	9207;"	d
+SET_I2CMST_TAR	smac/hal/ssv6006c/ssv6006C_reg.h	9210;"	d
+SET_I2CMST_TRX_CMDW	smac/hal/ssv6006c/ssv6006C_reg.h	9212;"	d
+SET_I2CMST_TRX_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	9211;"	d
+SET_I2CMST_TRX_RESTARTW	smac/hal/ssv6006c/ssv6006C_reg.h	9214;"	d
+SET_I2CMST_TRX_STOPW	smac/hal/ssv6006c/ssv6006C_reg.h	9213;"	d
+SET_I2CMST_TXE_INT	smac/hal/ssv6006c/ssv6006C_reg.h	9222;"	d
+SET_I2CMST_TXE_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	9228;"	d
+SET_I2CMST_TXE_INT_STAR	smac/hal/ssv6006c/ssv6006C_reg.h	9234;"	d
+SET_I2CMST_TXO_INT	smac/hal/ssv6006c/ssv6006C_reg.h	9221;"	d
+SET_I2CMST_TXO_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	9227;"	d
+SET_I2CMST_TXO_INT_STAR	smac/hal/ssv6006c/ssv6006C_reg.h	9233;"	d
+SET_I2CMST_TX_FIFO_TH	smac/hal/ssv6006c/ssv6006C_reg.h	9237;"	d
+SET_I2CM_DEV_A	include/ssv6200_reg.h	5744;"	d
+SET_I2CM_DEV_A	smac/hal/ssv6006c/ssv6006C_reg.h	9733;"	d
+SET_I2CM_DEV_A10B	include/ssv6200_reg.h	5745;"	d
+SET_I2CM_DEV_A10B	smac/hal/ssv6006c/ssv6006C_reg.h	9734;"	d
+SET_I2CM_IDLE	include/ssv6200_reg.h	5738;"	d
+SET_I2CM_IDLE	smac/hal/ssv6006c/ssv6006C_reg.h	9727;"	d
+SET_I2CM_INT_MISMATCH	include/ssv6200_reg.h	5739;"	d
+SET_I2CM_INT_MISMATCH	smac/hal/ssv6006c/ssv6006C_reg.h	9728;"	d
+SET_I2CM_INT_RDATA_NEED	include/ssv6200_reg.h	5743;"	d
+SET_I2CM_INT_RDATA_NEED	smac/hal/ssv6006c/ssv6006C_reg.h	9732;"	d
+SET_I2CM_INT_RDONE	include/ssv6200_reg.h	5737;"	d
+SET_I2CM_INT_RDONE	smac/hal/ssv6006c/ssv6006C_reg.h	9726;"	d
+SET_I2CM_INT_WDATA_NEED	include/ssv6200_reg.h	5742;"	d
+SET_I2CM_INT_WDATA_NEED	smac/hal/ssv6006c/ssv6006C_reg.h	9731;"	d
+SET_I2CM_INT_WDONE	include/ssv6200_reg.h	5736;"	d
+SET_I2CM_INT_WDONE	smac/hal/ssv6006c/ssv6006C_reg.h	9725;"	d
+SET_I2CM_LEN	include/ssv6200_reg.h	5747;"	d
+SET_I2CM_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	9736;"	d
+SET_I2CM_MANUAL_MODE	include/ssv6200_reg.h	5741;"	d
+SET_I2CM_MANUAL_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	9730;"	d
+SET_I2CM_PSCL	include/ssv6200_reg.h	5740;"	d
+SET_I2CM_PSCL	smac/hal/ssv6006c/ssv6006C_reg.h	9729;"	d
+SET_I2CM_RDAT	include/ssv6200_reg.h	5751;"	d
+SET_I2CM_RDAT	smac/hal/ssv6006c/ssv6006C_reg.h	9740;"	d
+SET_I2CM_REPEAT_START	include/ssv6200_reg.h	5754;"	d
+SET_I2CM_REPEAT_START	smac/hal/ssv6006c/ssv6006C_reg.h	9743;"	d
+SET_I2CM_RX	include/ssv6200_reg.h	5746;"	d
+SET_I2CM_RX	smac/hal/ssv6006c/ssv6006C_reg.h	9735;"	d
+SET_I2CM_R_GET	include/ssv6200_reg.h	5749;"	d
+SET_I2CM_R_GET	smac/hal/ssv6006c/ssv6006C_reg.h	9738;"	d
+SET_I2CM_SCL_ID_SEL	include/ssv6200_reg.h	5505;"	d
+SET_I2CM_SDA_ID_SEL	include/ssv6200_reg.h	5491;"	d
+SET_I2CM_SR_LEN	include/ssv6200_reg.h	5752;"	d
+SET_I2CM_SR_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	9741;"	d
+SET_I2CM_SR_RX	include/ssv6200_reg.h	5753;"	d
+SET_I2CM_SR_RX	smac/hal/ssv6006c/ssv6006C_reg.h	9742;"	d
+SET_I2CM_STA_STO_PSCL	smac/hal/ssv6006c/ssv6006C_reg.h	9744;"	d
+SET_I2CM_T_LEFT	include/ssv6200_reg.h	5748;"	d
+SET_I2CM_T_LEFT	smac/hal/ssv6006c/ssv6006C_reg.h	9737;"	d
+SET_I2CM_WDAT	include/ssv6200_reg.h	5750;"	d
+SET_I2CM_WDAT	smac/hal/ssv6006c/ssv6006C_reg.h	9739;"	d
+SET_I2CS_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	9566;"	d
+SET_I2CS_ADDR_DC	smac/hal/ssv6006c/ssv6006C_reg.h	9565;"	d
+SET_I2CS_DATA_CONFIG	smac/hal/ssv6006c/ssv6006C_reg.h	9571;"	d
+SET_I2CS_HOLD_BUS_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9572;"	d
+SET_I2CS_IDLE	smac/hal/ssv6006c/ssv6006C_reg.h	9568;"	d
+SET_I2CS_INT	smac/hal/ssv6006c/ssv6006C_reg.h	9567;"	d
+SET_I2CS_STATE	smac/hal/ssv6006c/ssv6006C_reg.h	9570;"	d
+SET_I2CS_TIME_OUT_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	9569;"	d
+SET_I2C_MST_CLK_EN	include/ssv6200_reg.h	4962;"	d
+SET_I2C_MST_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9323;"	d
+SET_I2C_MST_SW_RST	include/ssv6200_reg.h	4930;"	d
+SET_I2C_MST_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	9289;"	d
+SET_I2C_SLV_CLK_EN	include/ssv6200_reg.h	4949;"	d
+SET_I2C_SLV_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9308;"	d
+SET_I2C_SLV_SW_RST	include/ssv6200_reg.h	4915;"	d
+SET_I2C_SLV_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	9275;"	d
+SET_I2SMAS_CLK_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	9357;"	d
+SET_I2S_ENABLE	smac/hal/ssv6006c/ssv6006C_reg.h	9176;"	d
+SET_I2S_INTR_RXDA	smac/hal/ssv6006c/ssv6006C_reg.h	9190;"	d
+SET_I2S_INTR_RXFA_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	9194;"	d
+SET_I2S_INTR_RXFE	smac/hal/ssv6006c/ssv6006C_reg.h	9192;"	d
+SET_I2S_INTR_RXFO	smac/hal/ssv6006c/ssv6006C_reg.h	9191;"	d
+SET_I2S_INTR_RXFO_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	9195;"	d
+SET_I2S_INTR_TXFE_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	9196;"	d
+SET_I2S_INTR_TXFO	smac/hal/ssv6006c/ssv6006C_reg.h	9193;"	d
+SET_I2S_INTR_TXFO_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	9197;"	d
+SET_I2S_L_TRX_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	9184;"	d
+SET_I2S_MASTER	smac/hal/ssv6006c/ssv6006C_reg.h	9359;"	d
+SET_I2S_MCLK_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	9358;"	d
+SET_I2S_PCLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9330;"	d
+SET_I2S_RAW_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	9558;"	d
+SET_I2S_RST_RXFIFO	smac/hal/ssv6006c/ssv6006C_reg.h	9182;"	d
+SET_I2S_RST_TXFIFO	smac/hal/ssv6006c/ssv6006C_reg.h	9183;"	d
+SET_I2S_RXFO	smac/hal/ssv6006c/ssv6006C_reg.h	9198;"	d
+SET_I2S_RX_CH_ENABLE	smac/hal/ssv6006c/ssv6006C_reg.h	9186;"	d
+SET_I2S_RX_DMA	smac/hal/ssv6006c/ssv6006C_reg.h	9204;"	d
+SET_I2S_RX_ENABLE	smac/hal/ssv6006c/ssv6006C_reg.h	9177;"	d
+SET_I2S_RX_FIFO_FLUSH	smac/hal/ssv6006c/ssv6006C_reg.h	9202;"	d
+SET_I2S_RX_FIFO_TH	smac/hal/ssv6006c/ssv6006C_reg.h	9200;"	d
+SET_I2S_RX_WD_RES	smac/hal/ssv6006c/ssv6006C_reg.h	9188;"	d
+SET_I2S_R_TRX_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	9185;"	d
+SET_I2S_SCLK_GATE	smac/hal/ssv6006c/ssv6006C_reg.h	9180;"	d
+SET_I2S_SCLK_SOURCE_ENABLE	smac/hal/ssv6006c/ssv6006C_reg.h	9179;"	d
+SET_I2S_TXFO	smac/hal/ssv6006c/ssv6006C_reg.h	9199;"	d
+SET_I2S_TX_CH_ENABLE	smac/hal/ssv6006c/ssv6006C_reg.h	9187;"	d
+SET_I2S_TX_DMA	smac/hal/ssv6006c/ssv6006C_reg.h	9205;"	d
+SET_I2S_TX_ENABLE	smac/hal/ssv6006c/ssv6006C_reg.h	9178;"	d
+SET_I2S_TX_FIFO_FLUSH	smac/hal/ssv6006c/ssv6006C_reg.h	9203;"	d
+SET_I2S_TX_FIFO_TH	smac/hal/ssv6006c/ssv6006C_reg.h	9201;"	d
+SET_I2S_TX_WD_RES	smac/hal/ssv6006c/ssv6006C_reg.h	9189;"	d
+SET_I2S_WS_LENGTH	smac/hal/ssv6006c/ssv6006C_reg.h	9181;"	d
+SET_IC_TAG_31_0	include/ssv6200_reg.h	6651;"	d
+SET_IC_TAG_63_32	include/ssv6200_reg.h	6652;"	d
+SET_IDX_EXTEND	smac/hal/ssv6006c/ssv6006C_reg.h	10376;"	d
+SET_ID_DOUBLE_RLS	include/ssv6200_reg.h	5906;"	d
+SET_ID_DOUBLE_RLS_INT	include/ssv6200_reg.h	7444;"	d
+SET_ID_DOUBLE_RLS_INT	smac/hal/ssv6006c/ssv6006C_reg.h	15888;"	d
+SET_ID_DOUBLE_RLS_SD	include/ssv6200_reg.h	5975;"	d
+SET_ID_EXCEPT_FLG	include/ssv6200_reg.h	7409;"	d
+SET_ID_EXCEPT_FLG	smac/hal/ssv6006c/ssv6006C_reg.h	15853;"	d
+SET_ID_EXCEPT_FLG_CLR	include/ssv6200_reg.h	7408;"	d
+SET_ID_EXCEPT_FLG_CLR	smac/hal/ssv6006c/ssv6006C_reg.h	15852;"	d
+SET_ID_FULL	include/ssv6200_reg.h	7410;"	d
+SET_ID_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	15854;"	d
+SET_ID_IN_USE	include/ssv6200_reg.h	6353;"	d
+SET_ID_IN_USE	smac/hal/ssv6006c/ssv6006C_reg.h	10357;"	d
+SET_ID_LEN_THOLD	include/ssv6200_reg.h	7452;"	d
+SET_ID_LEN_THOLD	smac/hal/ssv6006c/ssv6006C_reg.h	15896;"	d
+SET_ID_LEN_THOLD_INT_EN	include/ssv6200_reg.h	7446;"	d
+SET_ID_LEN_THOLD_INT_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15890;"	d
+SET_ID_MNG_BUSY	include/ssv6200_reg.h	7411;"	d
+SET_ID_MNG_BUSY	smac/hal/ssv6006c/ssv6006C_reg.h	15855;"	d
+SET_ID_MNG_CLK_EN	include/ssv6200_reg.h	6707;"	d
+SET_ID_MNG_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10803;"	d
+SET_ID_MNG_CSR_CLK_EN	include/ssv6200_reg.h	6726;"	d
+SET_ID_MNG_CSR_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10822;"	d
+SET_ID_MNG_CSR_RST	include/ssv6200_reg.h	6698;"	d
+SET_ID_MNG_CSR_RST	smac/hal/ssv6006c/ssv6006C_reg.h	10794;"	d
+SET_ID_MNG_ENG_CLK_EN	include/ssv6200_reg.h	6718;"	d
+SET_ID_MNG_ENG_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10814;"	d
+SET_ID_MNG_ENG_RST	include/ssv6200_reg.h	6683;"	d
+SET_ID_MNG_ENG_RST	smac/hal/ssv6006c/ssv6006C_reg.h	10779;"	d
+SET_ID_MNG_ERR_HALT_EN	include/ssv6200_reg.h	7407;"	d
+SET_ID_MNG_ERR_HALT_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15851;"	d
+SET_ID_MNG_HALT	include/ssv6200_reg.h	7406;"	d
+SET_ID_MNG_HALT	smac/hal/ssv6006c/ssv6006C_reg.h	15850;"	d
+SET_ID_MNG_INT_1	include/ssv6200_reg.h	5895;"	d
+SET_ID_MNG_INT_1_SD	include/ssv6200_reg.h	5964;"	d
+SET_ID_MNG_INT_2	include/ssv6200_reg.h	5902;"	d
+SET_ID_MNG_INT_2_SD	include/ssv6200_reg.h	5971;"	d
+SET_ID_MNG_SW_RST	include/ssv6200_reg.h	6672;"	d
+SET_ID_MNG_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	10768;"	d
+SET_ID_PAGE_MAX_SIZE	include/ssv6200_reg.h	7463;"	d
+SET_ID_PAGE_MAX_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	15907;"	d
+SET_ID_RX_LEN_THOLD	include/ssv6200_reg.h	7451;"	d
+SET_ID_RX_LEN_THOLD	smac/hal/ssv6006c/ssv6006C_reg.h	15895;"	d
+SET_ID_TB0	include/ssv6200_reg.h	7404;"	d
+SET_ID_TB0	smac/hal/ssv6006c/ssv6006C_reg.h	15848;"	d
+SET_ID_TB1	include/ssv6200_reg.h	7405;"	d
+SET_ID_TB1	smac/hal/ssv6006c/ssv6006C_reg.h	15849;"	d
+SET_ID_TB2	include/ssv6200_reg.h	7474;"	d
+SET_ID_TB2	smac/hal/ssv6006c/ssv6006C_reg.h	15918;"	d
+SET_ID_TB3	include/ssv6200_reg.h	7475;"	d
+SET_ID_TB3	smac/hal/ssv6006c/ssv6006C_reg.h	15919;"	d
+SET_ID_THOLD_INT_EN	include/ssv6200_reg.h	7438;"	d
+SET_ID_THOLD_INT_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15882;"	d
+SET_ID_THOLD_RX	include/ssv6200_reg.h	5904;"	d
+SET_ID_THOLD_RX_INT	include/ssv6200_reg.h	7434;"	d
+SET_ID_THOLD_RX_INT	smac/hal/ssv6006c/ssv6006C_reg.h	15878;"	d
+SET_ID_THOLD_RX_SD	include/ssv6200_reg.h	5973;"	d
+SET_ID_THOLD_TX	include/ssv6200_reg.h	5905;"	d
+SET_ID_THOLD_TX_INT	include/ssv6200_reg.h	7436;"	d
+SET_ID_THOLD_TX_INT	smac/hal/ssv6006c/ssv6006C_reg.h	15880;"	d
+SET_ID_THOLD_TX_SD	include/ssv6200_reg.h	5974;"	d
+SET_ID_TX_LEN_THOLD	include/ssv6200_reg.h	7450;"	d
+SET_ID_TX_LEN_THOLD	smac/hal/ssv6006c/ssv6006C_reg.h	15894;"	d
+SET_ILLEGAL_CMD_RESP_OPTION	include/ssv6200_reg.h	5533;"	d
+SET_ILLEGAL_CMD_RESP_OPTION	smac/hal/ssv6006c/ssv6006C_reg.h	9596;"	d
+SET_ILL_ADDR_CLR	include/ssv6200_reg.h	4995;"	d
+SET_ILL_ADDR_INT	include/ssv6200_reg.h	4997;"	d
+SET_ILM160KB_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9430;"	d
+SET_INDICATOR	smac/hal/ssv6006c/ssv6006C_reg.h	9878;"	d
+SET_INFO0	include/ssv6200_reg.h	6606;"	d
+SET_INFO1	include/ssv6200_reg.h	6607;"	d
+SET_INFO10	include/ssv6200_reg.h	6616;"	d
+SET_INFO11	include/ssv6200_reg.h	6617;"	d
+SET_INFO12	include/ssv6200_reg.h	6618;"	d
+SET_INFO13	include/ssv6200_reg.h	6619;"	d
+SET_INFO14	include/ssv6200_reg.h	6620;"	d
+SET_INFO15	include/ssv6200_reg.h	6621;"	d
+SET_INFO16	include/ssv6200_reg.h	6622;"	d
+SET_INFO17	include/ssv6200_reg.h	6623;"	d
+SET_INFO18	include/ssv6200_reg.h	6624;"	d
+SET_INFO19	include/ssv6200_reg.h	6625;"	d
+SET_INFO2	include/ssv6200_reg.h	6608;"	d
+SET_INFO20	include/ssv6200_reg.h	6626;"	d
+SET_INFO21	include/ssv6200_reg.h	6627;"	d
+SET_INFO22	include/ssv6200_reg.h	6628;"	d
+SET_INFO23	include/ssv6200_reg.h	6629;"	d
+SET_INFO24	include/ssv6200_reg.h	6630;"	d
+SET_INFO25	include/ssv6200_reg.h	6631;"	d
+SET_INFO26	include/ssv6200_reg.h	6632;"	d
+SET_INFO27	include/ssv6200_reg.h	6633;"	d
+SET_INFO28	include/ssv6200_reg.h	6634;"	d
+SET_INFO29	include/ssv6200_reg.h	6635;"	d
+SET_INFO3	include/ssv6200_reg.h	6609;"	d
+SET_INFO30	include/ssv6200_reg.h	6636;"	d
+SET_INFO31	include/ssv6200_reg.h	6637;"	d
+SET_INFO32	include/ssv6200_reg.h	6638;"	d
+SET_INFO33	include/ssv6200_reg.h	6639;"	d
+SET_INFO34	include/ssv6200_reg.h	6640;"	d
+SET_INFO35	include/ssv6200_reg.h	6641;"	d
+SET_INFO36	include/ssv6200_reg.h	6642;"	d
+SET_INFO37	include/ssv6200_reg.h	6643;"	d
+SET_INFO38	include/ssv6200_reg.h	6644;"	d
+SET_INFO4	include/ssv6200_reg.h	6610;"	d
+SET_INFO5	include/ssv6200_reg.h	6611;"	d
+SET_INFO6	include/ssv6200_reg.h	6612;"	d
+SET_INFO7	include/ssv6200_reg.h	6613;"	d
+SET_INFO8	include/ssv6200_reg.h	6614;"	d
+SET_INFO9	include/ssv6200_reg.h	6615;"	d
+SET_INFO_DEF_RATE	include/ssv6200_reg.h	6646;"	d
+SET_INFO_IDX_TBL_ADDR	include/ssv6200_reg.h	6649;"	d
+SET_INFO_LEN_TBL_ADDR	include/ssv6200_reg.h	6650;"	d
+SET_INFO_MASK	include/ssv6200_reg.h	6645;"	d
+SET_INFO_MRX_OFFSET	include/ssv6200_reg.h	6647;"	d
+SET_INS_BUF_CLR	smac/hal/ssv6006c/ssv6006C_reg.h	9907;"	d
+SET_INS_END_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	9906;"	d
+SET_INS_START_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	9905;"	d
+SET_INTR_GPI00_CFG	include/ssv6200_reg.h	5918;"	d
+SET_INTR_GPI01_CFG	include/ssv6200_reg.h	5919;"	d
+SET_INTR_PERI_RAW	include/ssv6200_reg.h	5917;"	d
+SET_INTR_RX	include/ssv6200_reg.h	5608;"	d
+SET_INT_ALC_TIMEOUT	smac/hal/ssv6006c/ssv6006C_reg.h	10015;"	d
+SET_INT_ALL_ID_LEN_THOLD	smac/hal/ssv6006c/ssv6006C_reg.h	10023;"	d
+SET_INT_BROWNOUT_LOWBATTERY	smac/hal/ssv6006c/ssv6006C_reg.h	10091;"	d
+SET_INT_CO_DMA	smac/hal/ssv6006c/ssv6006C_reg.h	10048;"	d
+SET_INT_CPU	smac/hal/ssv6006c/ssv6006C_reg.h	10037;"	d
+SET_INT_CPU_ALT	smac/hal/ssv6006c/ssv6006C_reg.h	10036;"	d
+SET_INT_CTL_CLK_EN	include/ssv6200_reg.h	4950;"	d
+SET_INT_CTL_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9309;"	d
+SET_INT_CTL_SW_RST	include/ssv6200_reg.h	4916;"	d
+SET_INT_CTL_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	9276;"	d
+SET_INT_DMAC_INT_COMBINED	smac/hal/ssv6006c/ssv6006C_reg.h	10034;"	d
+SET_INT_EDCA0_LOWTHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	10026;"	d
+SET_INT_EDCA1_LOWTHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	10027;"	d
+SET_INT_EDCA2_LOWTHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	10028;"	d
+SET_INT_EDCA3_LOWTHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	10029;"	d
+SET_INT_FBUSDMAC_INT_COMBINED	smac/hal/ssv6006c/ssv6006C_reg.h	10033;"	d
+SET_INT_FLASH_DMA_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	10032;"	d
+SET_INT_GPI_MODE_00	smac/hal/ssv6006c/ssv6006C_reg.h	9987;"	d
+SET_INT_GPI_MODE_01	smac/hal/ssv6006c/ssv6006C_reg.h	9988;"	d
+SET_INT_GPI_MODE_02	smac/hal/ssv6006c/ssv6006C_reg.h	9989;"	d
+SET_INT_GPI_MODE_03	smac/hal/ssv6006c/ssv6006C_reg.h	9990;"	d
+SET_INT_GPI_MODE_04	smac/hal/ssv6006c/ssv6006C_reg.h	9991;"	d
+SET_INT_GPI_MODE_05	smac/hal/ssv6006c/ssv6006C_reg.h	9992;"	d
+SET_INT_GPI_MODE_06	smac/hal/ssv6006c/ssv6006C_reg.h	9993;"	d
+SET_INT_GPI_MODE_07	smac/hal/ssv6006c/ssv6006C_reg.h	9994;"	d
+SET_INT_GPI_MODE_08	smac/hal/ssv6006c/ssv6006C_reg.h	9995;"	d
+SET_INT_GPI_MODE_09	smac/hal/ssv6006c/ssv6006C_reg.h	9996;"	d
+SET_INT_GPI_MODE_10	smac/hal/ssv6006c/ssv6006C_reg.h	9997;"	d
+SET_INT_GPI_MODE_11	smac/hal/ssv6006c/ssv6006C_reg.h	9998;"	d
+SET_INT_GPI_MODE_12	smac/hal/ssv6006c/ssv6006C_reg.h	9999;"	d
+SET_INT_GPI_MODE_13	smac/hal/ssv6006c/ssv6006C_reg.h	10000;"	d
+SET_INT_GPI_MODE_14	smac/hal/ssv6006c/ssv6006C_reg.h	10001;"	d
+SET_INT_GPI_MODE_15	smac/hal/ssv6006c/ssv6006C_reg.h	10002;"	d
+SET_INT_GPI_MODE_16	smac/hal/ssv6006c/ssv6006C_reg.h	10003;"	d
+SET_INT_GPI_MODE_17	smac/hal/ssv6006c/ssv6006C_reg.h	10004;"	d
+SET_INT_GPI_MODE_18	smac/hal/ssv6006c/ssv6006C_reg.h	10005;"	d
+SET_INT_GPI_MODE_19	smac/hal/ssv6006c/ssv6006C_reg.h	10006;"	d
+SET_INT_GPI_MODE_20	smac/hal/ssv6006c/ssv6006C_reg.h	10007;"	d
+SET_INT_GPI_MODE_21	smac/hal/ssv6006c/ssv6006C_reg.h	10008;"	d
+SET_INT_GPI_MODE_22	smac/hal/ssv6006c/ssv6006C_reg.h	10009;"	d
+SET_INT_GPI_SUB_00	smac/hal/ssv6006c/ssv6006C_reg.h	9964;"	d
+SET_INT_GPI_SUB_01	smac/hal/ssv6006c/ssv6006C_reg.h	9965;"	d
+SET_INT_GPI_SUB_02	smac/hal/ssv6006c/ssv6006C_reg.h	9966;"	d
+SET_INT_GPI_SUB_03	smac/hal/ssv6006c/ssv6006C_reg.h	9967;"	d
+SET_INT_GPI_SUB_04	smac/hal/ssv6006c/ssv6006C_reg.h	9968;"	d
+SET_INT_GPI_SUB_05	smac/hal/ssv6006c/ssv6006C_reg.h	9969;"	d
+SET_INT_GPI_SUB_06	smac/hal/ssv6006c/ssv6006C_reg.h	9970;"	d
+SET_INT_GPI_SUB_07	smac/hal/ssv6006c/ssv6006C_reg.h	9971;"	d
+SET_INT_GPI_SUB_08	smac/hal/ssv6006c/ssv6006C_reg.h	9972;"	d
+SET_INT_GPI_SUB_09	smac/hal/ssv6006c/ssv6006C_reg.h	9973;"	d
+SET_INT_GPI_SUB_10	smac/hal/ssv6006c/ssv6006C_reg.h	9974;"	d
+SET_INT_GPI_SUB_11	smac/hal/ssv6006c/ssv6006C_reg.h	9975;"	d
+SET_INT_GPI_SUB_12	smac/hal/ssv6006c/ssv6006C_reg.h	9976;"	d
+SET_INT_GPI_SUB_13	smac/hal/ssv6006c/ssv6006C_reg.h	9977;"	d
+SET_INT_GPI_SUB_14	smac/hal/ssv6006c/ssv6006C_reg.h	9978;"	d
+SET_INT_GPI_SUB_15	smac/hal/ssv6006c/ssv6006C_reg.h	9979;"	d
+SET_INT_GPI_SUB_16	smac/hal/ssv6006c/ssv6006C_reg.h	9980;"	d
+SET_INT_GPI_SUB_17	smac/hal/ssv6006c/ssv6006C_reg.h	9981;"	d
+SET_INT_GPI_SUB_18	smac/hal/ssv6006c/ssv6006C_reg.h	9982;"	d
+SET_INT_GPI_SUB_19	smac/hal/ssv6006c/ssv6006C_reg.h	9983;"	d
+SET_INT_GPI_SUB_20	smac/hal/ssv6006c/ssv6006C_reg.h	9984;"	d
+SET_INT_GPI_SUB_21	smac/hal/ssv6006c/ssv6006C_reg.h	9985;"	d
+SET_INT_GPI_SUB_22	smac/hal/ssv6006c/ssv6006C_reg.h	9986;"	d
+SET_INT_HCI	smac/hal/ssv6006c/ssv6006C_reg.h	10047;"	d
+SET_INT_I2CMST	smac/hal/ssv6006c/ssv6006C_reg.h	10046;"	d
+SET_INT_I2S	smac/hal/ssv6006c/ssv6006C_reg.h	10035;"	d
+SET_INT_IDCODE	include/ssv6200_reg.h	5800;"	d
+SET_INT_IDCODE	smac/hal/ssv6006c/ssv6006C_reg.h	9791;"	d
+SET_INT_ID_DOUBLE_RLS	smac/hal/ssv6006c/ssv6006C_reg.h	10020;"	d
+SET_INT_ID_THOLD_RX	smac/hal/ssv6006c/ssv6006C_reg.h	10018;"	d
+SET_INT_ID_THOLD_TX	smac/hal/ssv6006c/ssv6006C_reg.h	10019;"	d
+SET_INT_IPC_RAW	smac/hal/ssv6006c/ssv6006C_reg.h	10011;"	d
+SET_INT_MB_LOWTHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	10025;"	d
+SET_INT_MODE	include/ssv6200_reg.h	5850;"	d
+SET_INT_MS_TIMER_0	smac/hal/ssv6006c/ssv6006C_reg.h	10042;"	d
+SET_INT_MS_TIMER_1	smac/hal/ssv6006c/ssv6006C_reg.h	10043;"	d
+SET_INT_MS_TIMER_2	smac/hal/ssv6006c/ssv6006C_reg.h	10044;"	d
+SET_INT_MS_TIMER_3	smac/hal/ssv6006c/ssv6006C_reg.h	10045;"	d
+SET_INT_PERI_MASK	include/ssv6200_reg.h	5885;"	d
+SET_INT_PERI_MASK_SD	include/ssv6200_reg.h	5954;"	d
+SET_INT_REQ_LOCK	smac/hal/ssv6006c/ssv6006C_reg.h	10016;"	d
+SET_INT_RX_ID_LEN_THOLD	smac/hal/ssv6006c/ssv6006C_reg.h	10021;"	d
+SET_INT_SDIO_WAKE	smac/hal/ssv6006c/ssv6006C_reg.h	10030;"	d
+SET_INT_SPI_M_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	10031;"	d
+SET_INT_THROUGH_PIN	include/ssv6200_reg.h	5575;"	d
+SET_INT_THROUGH_PIN	smac/hal/ssv6006c/ssv6006C_reg.h	9606;"	d
+SET_INT_TRASH_CAN	smac/hal/ssv6006c/ssv6006C_reg.h	10024;"	d
+SET_INT_TX_ID_LEN_THOLD	smac/hal/ssv6006c/ssv6006C_reg.h	10022;"	d
+SET_INT_TX_LIMIT	smac/hal/ssv6006c/ssv6006C_reg.h	10017;"	d
+SET_INT_UART_DATA_RX_TOUT	smac/hal/ssv6006c/ssv6006C_reg.h	10014;"	d
+SET_INT_UART_DBG_RX_TOUT	smac/hal/ssv6006c/ssv6006C_reg.h	10013;"	d
+SET_INT_US_TIMER_0	smac/hal/ssv6006c/ssv6006C_reg.h	10038;"	d
+SET_INT_US_TIMER_1	smac/hal/ssv6006c/ssv6006C_reg.h	10039;"	d
+SET_INT_US_TIMER_2	smac/hal/ssv6006c/ssv6006C_reg.h	10040;"	d
+SET_INT_US_TIMER_3	smac/hal/ssv6006c/ssv6006C_reg.h	10041;"	d
+SET_INT_WIFI_PHY	smac/hal/ssv6006c/ssv6006C_reg.h	10012;"	d
+SET_INV_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	10271;"	d
+SET_IN_FIFO_FLUSH_ID	smac/hal/ssv6006c/ssv6006C_reg.h	15830;"	d
+SET_IN_FIFO_FLUSH_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	15831;"	d
+SET_IN_FIFO_FLUSH_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	15832;"	d
+SET_IO_DS	smac/hal/ssv6006c/ssv6006C_reg.h	9538;"	d
+SET_IO_PDE	smac/hal/ssv6006c/ssv6006C_reg.h	9537;"	d
+SET_IO_PI	smac/hal/ssv6006c/ssv6006C_reg.h	9533;"	d
+SET_IO_PIE	smac/hal/ssv6006c/ssv6006C_reg.h	9534;"	d
+SET_IO_PO	smac/hal/ssv6006c/ssv6006C_reg.h	9532;"	d
+SET_IO_POEN	smac/hal/ssv6006c/ssv6006C_reg.h	9535;"	d
+SET_IO_PORT_REG	include/ssv6200_reg.h	5510;"	d
+SET_IO_PORT_REG	smac/hal/ssv6006c/ssv6006C_reg.h	9573;"	d
+SET_IO_PUE	smac/hal/ssv6006c/ssv6006C_reg.h	9536;"	d
+SET_IO_REG_PORT_REG	include/ssv6200_reg.h	5587;"	d
+SET_IQCAL_RF_PGAG	include/ssv6200_reg.h	7980;"	d
+SET_IQCAL_RF_RFG	include/ssv6200_reg.h	7981;"	d
+SET_IQCAL_RF_RX_AGC	include/ssv6200_reg.h	7979;"	d
+SET_IQCAL_RF_TX_DAC_EN	include/ssv6200_reg.h	7978;"	d
+SET_IQCAL_RF_TX_EN	include/ssv6200_reg.h	7976;"	d
+SET_IQCAL_RF_TX_PA_EN	include/ssv6200_reg.h	7977;"	d
+SET_IQ_LOG_EN	include/ssv6200_reg.h	7390;"	d
+SET_IQ_LOG_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15835;"	d
+SET_IQ_LOG_LEN	include/ssv6200_reg.h	7395;"	d
+SET_IQ_LOG_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	15838;"	d
+SET_IQ_LOG_STOP_MODE	include/ssv6200_reg.h	7391;"	d
+SET_IQ_LOG_STOP_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	15836;"	d
+SET_IQ_LOG_ST_ADR	smac/hal/ssv6006c/ssv6006C_reg.h	15839;"	d
+SET_IQ_LOG_TAIL_ADR	include/ssv6200_reg.h	7396;"	d
+SET_IQ_LOG_TAIL_ADR	smac/hal/ssv6006c/ssv6006C_reg.h	15840;"	d
+SET_IQ_LOG_TIMER	include/ssv6200_reg.h	7394;"	d
+SET_IQ_LOG_TIMER	smac/hal/ssv6006c/ssv6006C_reg.h	15837;"	d
+SET_IQ_SRAM_SEL_0	include/ssv6200_reg.h	4973;"	d
+SET_IQ_SRAM_SEL_1	include/ssv6200_reg.h	4974;"	d
+SET_IQ_SRAM_SEL_2	include/ssv6200_reg.h	4975;"	d
+SET_IRQ_BEACON	include/ssv6200_reg.h	5855;"	d
+SET_IRQ_BEACON_DONE	include/ssv6200_reg.h	5854;"	d
+SET_IRQ_BEACON_DONE_SD	include/ssv6200_reg.h	5926;"	d
+SET_IRQ_BEACON_DTIM	include/ssv6200_reg.h	5862;"	d
+SET_IRQ_BEACON_DTIM_SD	include/ssv6200_reg.h	5934;"	d
+SET_IRQ_BEACON_SD	include/ssv6200_reg.h	5927;"	d
+SET_IRQ_CO_DMA	include/ssv6200_reg.h	5880;"	d
+SET_IRQ_CO_DMA_SD	include/ssv6200_reg.h	5952;"	d
+SET_IRQ_DAT_UART_RX	include/ssv6200_reg.h	5912;"	d
+SET_IRQ_DAT_UART_RX_SD	include/ssv6200_reg.h	5981;"	d
+SET_IRQ_DAT_UART_TX	include/ssv6200_reg.h	5911;"	d
+SET_IRQ_DAT_UART_TX_SD	include/ssv6200_reg.h	5980;"	d
+SET_IRQ_DMA0	include/ssv6200_reg.h	5879;"	d
+SET_IRQ_DMA0_SD	include/ssv6200_reg.h	5951;"	d
+SET_IRQ_EDCA0_LOWTHOLD_INT	include/ssv6200_reg.h	5863;"	d
+SET_IRQ_EDCA0_LOWTHOLD_INT_SD	include/ssv6200_reg.h	5935;"	d
+SET_IRQ_EDCA0_TX_DONE	include/ssv6200_reg.h	5857;"	d
+SET_IRQ_EDCA0_TX_DONE_SD	include/ssv6200_reg.h	5929;"	d
+SET_IRQ_EDCA1_LOWTHOLD_INT	include/ssv6200_reg.h	5864;"	d
+SET_IRQ_EDCA1_LOWTHOLD_INT_SD	include/ssv6200_reg.h	5936;"	d
+SET_IRQ_EDCA1_TX_DONE	include/ssv6200_reg.h	5858;"	d
+SET_IRQ_EDCA1_TX_DONE_SD	include/ssv6200_reg.h	5930;"	d
+SET_IRQ_EDCA2_LOWTHOLD_INT	include/ssv6200_reg.h	5865;"	d
+SET_IRQ_EDCA2_LOWTHOLD_INT_SD	include/ssv6200_reg.h	5937;"	d
+SET_IRQ_EDCA2_TX_DONE	include/ssv6200_reg.h	5859;"	d
+SET_IRQ_EDCA2_TX_DONE_SD	include/ssv6200_reg.h	5931;"	d
+SET_IRQ_EDCA3_LOWTHOLD_INT	include/ssv6200_reg.h	5866;"	d
+SET_IRQ_EDCA3_LOWTHOLD_INT_SD	include/ssv6200_reg.h	5938;"	d
+SET_IRQ_EDCA3_TX_DONE	include/ssv6200_reg.h	5860;"	d
+SET_IRQ_EDCA3_TX_DONE_SD	include/ssv6200_reg.h	5932;"	d
+SET_IRQ_EDCA4_TX_DONE	include/ssv6200_reg.h	5861;"	d
+SET_IRQ_EDCA4_TX_DONE_SD	include/ssv6200_reg.h	5933;"	d
+SET_IRQ_FENCE_HIT_INT	include/ssv6200_reg.h	5867;"	d
+SET_IRQ_FENCE_HIT_INT_SD	include/ssv6200_reg.h	5939;"	d
+SET_IRQ_ILL_ADDR_INT	include/ssv6200_reg.h	5868;"	d
+SET_IRQ_ILL_ADDR_INT_SD	include/ssv6200_reg.h	5940;"	d
+SET_IRQ_MBOX	include/ssv6200_reg.h	5869;"	d
+SET_IRQ_MBOX_SD	include/ssv6200_reg.h	5941;"	d
+SET_IRQ_MS_TIMER0	include/ssv6200_reg.h	5874;"	d
+SET_IRQ_MS_TIMER0_SD	include/ssv6200_reg.h	5946;"	d
+SET_IRQ_MS_TIMER1	include/ssv6200_reg.h	5875;"	d
+SET_IRQ_MS_TIMER1_SD	include/ssv6200_reg.h	5947;"	d
+SET_IRQ_MS_TIMER2	include/ssv6200_reg.h	5876;"	d
+SET_IRQ_MS_TIMER2_SD	include/ssv6200_reg.h	5948;"	d
+SET_IRQ_MS_TIMER3	include/ssv6200_reg.h	5877;"	d
+SET_IRQ_MS_TIMER3_SD	include/ssv6200_reg.h	5949;"	d
+SET_IRQ_PERI_GROUP	include/ssv6200_reg.h	5881;"	d
+SET_IRQ_PERI_GROUP_SD	include/ssv6200_reg.h	5953;"	d
+SET_IRQ_PHY_0	include/ssv6200_reg.h	5851;"	d
+SET_IRQ_PHY_0_SD	include/ssv6200_reg.h	5923;"	d
+SET_IRQ_PHY_1	include/ssv6200_reg.h	5852;"	d
+SET_IRQ_PHY_1_SD	include/ssv6200_reg.h	5924;"	d
+SET_IRQ_PRE_BEACON	include/ssv6200_reg.h	5856;"	d
+SET_IRQ_PRE_BEACON_SD	include/ssv6200_reg.h	5928;"	d
+SET_IRQ_RAW	include/ssv6200_reg.h	5883;"	d
+SET_IRQ_SDIO	include/ssv6200_reg.h	5853;"	d
+SET_IRQ_SDIO_SD	include/ssv6200_reg.h	5925;"	d
+SET_IRQ_SPI_IPC	include/ssv6200_reg.h	5890;"	d
+SET_IRQ_SPI_IPC_SD	include/ssv6200_reg.h	5959;"	d
+SET_IRQ_TX_LIMIT_INT	include/ssv6200_reg.h	5878;"	d
+SET_IRQ_TX_LIMIT_INT_SD	include/ssv6200_reg.h	5950;"	d
+SET_IRQ_UART0_RX	include/ssv6200_reg.h	5888;"	d
+SET_IRQ_UART0_RX_SD	include/ssv6200_reg.h	5957;"	d
+SET_IRQ_UART0_TX	include/ssv6200_reg.h	5887;"	d
+SET_IRQ_UART0_TX_SD	include/ssv6200_reg.h	5956;"	d
+SET_IRQ_US_TIMER0	include/ssv6200_reg.h	5870;"	d
+SET_IRQ_US_TIMER0_SD	include/ssv6200_reg.h	5942;"	d
+SET_IRQ_US_TIMER1	include/ssv6200_reg.h	5871;"	d
+SET_IRQ_US_TIMER1_SD	include/ssv6200_reg.h	5943;"	d
+SET_IRQ_US_TIMER2	include/ssv6200_reg.h	5872;"	d
+SET_IRQ_US_TIMER2_SD	include/ssv6200_reg.h	5944;"	d
+SET_IRQ_US_TIMER3	include/ssv6200_reg.h	5873;"	d
+SET_IRQ_US_TIMER3_SD	include/ssv6200_reg.h	5945;"	d
+SET_JTAG_TCK_ID	include/ssv6200_reg.h	5365;"	d
+SET_JTAG_TDI_ID	include/ssv6200_reg.h	5370;"	d
+SET_JTAG_TDO_ID	include/ssv6200_reg.h	5379;"	d
+SET_JTAG_TMS_ID	include/ssv6200_reg.h	5359;"	d
+SET_JUDGE_CNT	include/ssv6200_reg.h	5713;"	d
+SET_JUDGE_CNT_CLR	include/ssv6200_reg.h	5716;"	d
+SET_KEY_DIN_MSB	include/ssv6200_reg.h	6248;"	d
+SET_L4_LEN	include/ssv6200_reg.h	6176;"	d
+SET_L4_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	10194;"	d
+SET_L4_PROTOL	include/ssv6200_reg.h	6177;"	d
+SET_L4_PROTOL	smac/hal/ssv6006c/ssv6006C_reg.h	10195;"	d
+SET_LCK_BIN_RDY	include/ssv6200_reg.h	8415;"	d
+SET_LEN	include/ssv6200_reg.h	6189;"	d
+SET_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	10207;"	d
+SET_LEN_FLT	include/ssv6200_reg.h	6382;"	d
+SET_LEN_FLT	smac/hal/ssv6006c/ssv6006C_reg.h	10382;"	d
+SET_LOOP_BACK	include/ssv6200_reg.h	5780;"	d
+SET_LOOP_BACK	smac/hal/ssv6006c/ssv6006C_reg.h	9770;"	d
+SET_LOWBATTERY_SAMPLE_MIN_COUNT	smac/hal/ssv6006c/ssv6006C_reg.h	10092;"	d
+SET_LOW_ACTIVE	include/ssv6200_reg.h	6203;"	d
+SET_LOW_SPEED_CARD	include/ssv6200_reg.h	5646;"	d
+SET_LOW_SPEED_CARD	smac/hal/ssv6006c/ssv6006C_reg.h	9640;"	d
+SET_LOW_SPEED_CARD_4BIT	include/ssv6200_reg.h	5647;"	d
+SET_LOW_SPEED_CARD_4BIT	smac/hal/ssv6006c/ssv6006C_reg.h	9641;"	d
+SET_LUT_SEL_V2	smac/hal/ssv6006c/ssv6006C_reg.h	10833;"	d
+SET_MAC_ALL_RESET	include/ssv6200_reg.h	5585;"	d
+SET_MAC_ALL_RESET	smac/hal/ssv6006c/ssv6006C_reg.h	9623;"	d
+SET_MAC_CLK_80M	smac/hal/ssv6006c/ssv6006C_reg.h	10522;"	d
+SET_MAC_CLK_EN	include/ssv6200_reg.h	4942;"	d
+SET_MAC_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9301;"	d
+SET_MAC_SW_RST	include/ssv6200_reg.h	4908;"	d
+SET_MAC_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	9268;"	d
+SET_MAC_TX_PEER_PS_LOCK_AUTOLOCK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10472;"	d
+SET_MAC_TX_PEER_PS_LOCK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10471;"	d
+SET_MAC_TX_PS_LOCK	smac/hal/ssv6006c/ssv6006C_reg.h	10473;"	d
+SET_MAC_TX_PS_LOCK_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	10474;"	d
+SET_MAC_TX_PS_UNLOCK	smac/hal/ssv6006c/ssv6006C_reg.h	10470;"	d
+SET_MANUAL_ALLOC_ID	smac/hal/ssv6006c/ssv6006C_reg.h	10134;"	d
+SET_MANUAL_DS	smac/hal/ssv6006c/ssv6006C_reg.h	9531;"	d
+SET_MANUAL_HCI_ALLOC_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10132;"	d
+SET_MANUAL_HCI_ALLOC_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	10133;"	d
+SET_MANUAL_IO	smac/hal/ssv6006c/ssv6006C_reg.h	9528;"	d
+SET_MANUAL_MODE_BUSY	smac/hal/ssv6006c/ssv6006C_reg.h	9883;"	d
+SET_MANUAL_PD	smac/hal/ssv6006c/ssv6006C_reg.h	9530;"	d
+SET_MANUAL_PU	smac/hal/ssv6006c/ssv6006C_reg.h	9529;"	d
+SET_MANUAL_R_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	9874;"	d
+SET_MANUAL_R_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	9888;"	d
+SET_MANUAL_T_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	9873;"	d
+SET_MANUAL_T_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	9887;"	d
+SET_MASK_ABNORMAL_CRC	smac/hal/ssv6006c/ssv6006C_reg.h	10369;"	d
+SET_MASK_RX_INT	include/ssv6200_reg.h	5511;"	d
+SET_MASK_RX_INT	smac/hal/ssv6006c/ssv6006C_reg.h	9574;"	d
+SET_MASK_SOC_SYSTEM_INT	include/ssv6200_reg.h	5513;"	d
+SET_MASK_SOC_SYSTEM_INT	smac/hal/ssv6006c/ssv6006C_reg.h	9576;"	d
+SET_MASK_TOP	include/ssv6200_reg.h	5849;"	d
+SET_MASK_TX_INT	include/ssv6200_reg.h	5512;"	d
+SET_MASK_TYPHOST_INT_MAP	smac/hal/ssv6006c/ssv6006C_reg.h	9947;"	d
+SET_MASK_TYPHOST_INT_MAP_02	smac/hal/ssv6006c/ssv6006C_reg.h	9938;"	d
+SET_MASK_TYPHOST_INT_MAP_15	smac/hal/ssv6006c/ssv6006C_reg.h	9941;"	d
+SET_MASK_TYPHOST_INT_MAP_31	smac/hal/ssv6006c/ssv6006C_reg.h	9944;"	d
+SET_MASK_TYPMCU_INT_MAP	smac/hal/ssv6006c/ssv6006C_reg.h	9960;"	d
+SET_MASK_TYPMCU_INT_MAP_02	smac/hal/ssv6006c/ssv6006C_reg.h	9951;"	d
+SET_MASK_TYPMCU_INT_MAP_15	smac/hal/ssv6006c/ssv6006C_reg.h	9954;"	d
+SET_MASK_TYPMCU_INT_MAP_31	smac/hal/ssv6006c/ssv6006C_reg.h	9957;"	d
+SET_MAX_ALL_ALC_ID_CNT	include/ssv6200_reg.h	7493;"	d
+SET_MAX_ALL_ALC_ID_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15939;"	d
+SET_MAX_ALL_ID_ALC_LEN	include/ssv6200_reg.h	7496;"	d
+SET_MAX_ALL_ID_ALC_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	15942;"	d
+SET_MAX_RX_ALC_ID_CNT	include/ssv6200_reg.h	7495;"	d
+SET_MAX_RX_ALC_ID_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15941;"	d
+SET_MAX_RX_ID_ALC_LEN	include/ssv6200_reg.h	7498;"	d
+SET_MAX_RX_ID_ALC_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	15944;"	d
+SET_MAX_TX_ALC_ID_CNT	include/ssv6200_reg.h	7494;"	d
+SET_MAX_TX_ALC_ID_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15940;"	d
+SET_MAX_TX_ID_ALC_LEN	include/ssv6200_reg.h	7497;"	d
+SET_MAX_TX_ID_ALC_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	15943;"	d
+SET_MBOX_CLK_EN	include/ssv6200_reg.h	6708;"	d
+SET_MBOX_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10804;"	d
+SET_MBOX_CSR_CLK_EN	include/ssv6200_reg.h	6727;"	d
+SET_MBOX_CSR_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10823;"	d
+SET_MBOX_CSR_RST	include/ssv6200_reg.h	6699;"	d
+SET_MBOX_CSR_RST	smac/hal/ssv6006c/ssv6006C_reg.h	10795;"	d
+SET_MBOX_ENG_CLK_EN	include/ssv6200_reg.h	6719;"	d
+SET_MBOX_ENG_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10815;"	d
+SET_MBOX_ENG_RST	include/ssv6200_reg.h	6684;"	d
+SET_MBOX_ENG_RST	smac/hal/ssv6006c/ssv6006C_reg.h	10780;"	d
+SET_MBOX_INT_1	include/ssv6200_reg.h	5896;"	d
+SET_MBOX_INT_1_SD	include/ssv6200_reg.h	5965;"	d
+SET_MBOX_INT_2	include/ssv6200_reg.h	5897;"	d
+SET_MBOX_INT_2_SD	include/ssv6200_reg.h	5966;"	d
+SET_MBOX_INT_3	include/ssv6200_reg.h	5898;"	d
+SET_MBOX_INT_3_SD	include/ssv6200_reg.h	5967;"	d
+SET_MBOX_SW_RST	include/ssv6200_reg.h	6673;"	d
+SET_MBOX_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	10769;"	d
+SET_MBRUN	include/ssv6200_reg.h	4978;"	d
+SET_MB_DBG_CFG_ADDR	include/ssv6200_reg.h	7254;"	d
+SET_MB_DBG_CFG_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	15724;"	d
+SET_MB_DBG_CLR	include/ssv6200_reg.h	7248;"	d
+SET_MB_DBG_CLR	smac/hal/ssv6006c/ssv6006C_reg.h	15718;"	d
+SET_MB_DBG_COUNTER_EN	include/ssv6200_reg.h	7250;"	d
+SET_MB_DBG_COUNTER_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15720;"	d
+SET_MB_DBG_EN	include/ssv6200_reg.h	7251;"	d
+SET_MB_DBG_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15721;"	d
+SET_MB_DBG_LENGTH	include/ssv6200_reg.h	7253;"	d
+SET_MB_DBG_LENGTH	smac/hal/ssv6006c/ssv6006C_reg.h	15723;"	d
+SET_MB_DBG_RECORD_CNT	include/ssv6200_reg.h	7252;"	d
+SET_MB_DBG_RECORD_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15722;"	d
+SET_MB_DBG_TIME_STEP	include/ssv6200_reg.h	7246;"	d
+SET_MB_DBG_TIME_STEP	smac/hal/ssv6006c/ssv6006C_reg.h	15716;"	d
+SET_MB_ERR_AUTO_HALT_EN	include/ssv6200_reg.h	7243;"	d
+SET_MB_ERR_AUTO_HALT_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15699;"	d
+SET_MB_EXCEPT_CASE	include/ssv6200_reg.h	7245;"	d
+SET_MB_EXCEPT_CASE	smac/hal/ssv6006c/ssv6006C_reg.h	15715;"	d
+SET_MB_EXCEPT_CLR	include/ssv6200_reg.h	7244;"	d
+SET_MB_EXCEPT_CLR	smac/hal/ssv6006c/ssv6006C_reg.h	15700;"	d
+SET_MB_IDTBL_127_96	include/ssv6200_reg.h	8511;"	d
+SET_MB_IDTBL_31_0	include/ssv6200_reg.h	8508;"	d
+SET_MB_IDTBL_63_32	include/ssv6200_reg.h	8509;"	d
+SET_MB_IDTBL_95_64	include/ssv6200_reg.h	8510;"	d
+SET_MB_LOW_THOLD_EN	include/ssv6200_reg.h	7352;"	d
+SET_MB_LOW_THOLD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15809;"	d
+SET_MB_OUT_QUEUE_EN	include/ssv6200_reg.h	7287;"	d
+SET_MB_OUT_QUEUE_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15757;"	d
+SET_MB_REQ_DUR	include/ssv6200_reg.h	6457;"	d
+SET_MCH_SW_RST_N	include/ssv6200_reg.h	8445;"	d
+SET_MCS	include/ssv6200_reg.h	6195;"	d
+SET_MCS	smac/hal/ssv6006c/ssv6006C_reg.h	10213;"	d
+SET_MCU_ALC_READY	include/ssv6200_reg.h	7419;"	d
+SET_MCU_ALC_READY	smac/hal/ssv6006c/ssv6006C_reg.h	15863;"	d
+SET_MCU_CLK_EN	include/ssv6200_reg.h	4943;"	d
+SET_MCU_DBG_DATA	include/ssv6200_reg.h	4967;"	d
+SET_MCU_DBG_SEL	include/ssv6200_reg.h	4964;"	d
+SET_MCU_ENABLE	include/ssv6200_reg.h	4907;"	d
+SET_MCU_ENABLE	smac/hal/ssv6006c/ssv6006C_reg.h	9267;"	d
+SET_MCU_PKTID	include/ssv6200_reg.h	7399;"	d
+SET_MCU_PKTID	smac/hal/ssv6006c/ssv6006C_reg.h	15843;"	d
+SET_MCU_STOP_ANYTIME	include/ssv6200_reg.h	4966;"	d
+SET_MCU_STOP_NOGRANT	include/ssv6200_reg.h	4965;"	d
+SET_MCU_SW_RST	include/ssv6200_reg.h	4909;"	d
+SET_MCU_TO_SDIO_INFO	smac/hal/ssv6006c/ssv6006C_reg.h	9625;"	d
+SET_MCU_TO_SDIO_INFO_MASK	include/ssv6200_reg.h	5574;"	d
+SET_MCU_TO_SDIO_INFO_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	9605;"	d
+SET_MCU_WDOG_ENA	include/ssv6200_reg.h	5071;"	d
+SET_MCU_WDOG_ENA	smac/hal/ssv6006c/ssv6006C_reg.h	9488;"	d
+SET_MCU_WDT_INT_CNT_OFS	smac/hal/ssv6006c/ssv6006C_reg.h	9486;"	d
+SET_MCU_WDT_STATUS	include/ssv6200_reg.h	5070;"	d
+SET_MCU_WDT_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	9487;"	d
+SET_MCU_WDT_TIME_CNT	include/ssv6200_reg.h	5069;"	d
+SET_MCU_WDT_TIME_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	9485;"	d
+SET_MDM_STS_IE	include/ssv6200_reg.h	5759;"	d
+SET_MDM_STS_IE	smac/hal/ssv6006c/ssv6006C_reg.h	9749;"	d
+SET_MEM_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	9880;"	d
+SET_MIB_AMPDU	include/ssv6200_reg.h	6381;"	d
+SET_MIB_AMPDU	smac/hal/ssv6006c/ssv6006C_reg.h	10381;"	d
+SET_MIB_CLK_EN	include/ssv6200_reg.h	6711;"	d
+SET_MIB_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10807;"	d
+SET_MIB_DELIMITER	include/ssv6200_reg.h	6383;"	d
+SET_MIB_DELIMITER	smac/hal/ssv6006c/ssv6006C_reg.h	10383;"	d
+SET_MIB_LEN_FAIL	include/ssv6200_reg.h	6351;"	d
+SET_MIB_LEN_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	10355;"	d
+SET_MIC_CLK_EN	include/ssv6200_reg.h	6710;"	d
+SET_MIC_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10806;"	d
+SET_MIC_ENG_CLK_EN	include/ssv6200_reg.h	6721;"	d
+SET_MIC_ENG_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10817;"	d
+SET_MIC_ENG_RST	include/ssv6200_reg.h	6686;"	d
+SET_MIC_ENG_RST	smac/hal/ssv6006c/ssv6006C_reg.h	10782;"	d
+SET_MIC_SW_RST	include/ssv6200_reg.h	6675;"	d
+SET_MIC_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	10771;"	d
+SET_MISC_PKT_CLS_MIB_EN	include/ssv6200_reg.h	6786;"	d
+SET_MISC_PKT_CLS_MIB_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10898;"	d
+SET_MISC_PKT_CLS_ONGOING	include/ssv6200_reg.h	6787;"	d
+SET_MISC_PKT_CLS_ONGOING	smac/hal/ssv6006c/ssv6006C_reg.h	10899;"	d
+SET_MMU_ALC_ERR	include/ssv6200_reg.h	5893;"	d
+SET_MMU_ALC_ERR_SD	include/ssv6200_reg.h	5962;"	d
+SET_MMU_CLK_EN	include/ssv6200_reg.h	6706;"	d
+SET_MMU_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10802;"	d
+SET_MMU_RLS_ERR	include/ssv6200_reg.h	5894;"	d
+SET_MMU_RLS_ERR_SD	include/ssv6200_reg.h	5963;"	d
+SET_MMU_SHARE_MCU	include/ssv6200_reg.h	8449;"	d
+SET_MMU_SW_RST	include/ssv6200_reg.h	6671;"	d
+SET_MMU_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	10767;"	d
+SET_MMU_VER	include/ssv6200_reg.h	8448;"	d
+SET_MODEN_INT	smac/hal/ssv6006c/ssv6006C_reg.h	9806;"	d
+SET_MODE_REG_IN	include/ssv6200_reg.h	4983;"	d
+SET_MODE_REG_IN_MMU	include/ssv6200_reg.h	5014;"	d
+SET_MODE_REG_OUT_MCU	include/ssv6200_reg.h	4984;"	d
+SET_MODE_REG_OUT_MMU	include/ssv6200_reg.h	5015;"	d
+SET_MODE_REG_SI	include/ssv6200_reg.h	4980;"	d
+SET_MODE_REG_SO_MCU	include/ssv6200_reg.h	4985;"	d
+SET_MODE_REG_SO_MMU	include/ssv6200_reg.h	5016;"	d
+SET_MONITOR_BUS_MCU_31_0	include/ssv6200_reg.h	4986;"	d
+SET_MONITOR_BUS_MCU_33_32	include/ssv6200_reg.h	4987;"	d
+SET_MONITOR_BUS_MMU	include/ssv6200_reg.h	5017;"	d
+SET_MP_MRX_RX_EN_SEL	include/ssv6200_reg.h	5506;"	d
+SET_MP_PHY2RX_DATA__0_SEL	include/ssv6200_reg.h	5483;"	d
+SET_MP_PHY2RX_DATA__1_SEL	include/ssv6200_reg.h	5484;"	d
+SET_MP_PHY2RX_DATA__2_SEL	include/ssv6200_reg.h	5489;"	d
+SET_MP_PHY2RX_DATA__3_SEL	include/ssv6200_reg.h	5494;"	d
+SET_MP_PHY2RX_DATA__4_SEL	include/ssv6200_reg.h	5490;"	d
+SET_MP_PHY2RX_DATA__5_SEL	include/ssv6200_reg.h	5493;"	d
+SET_MP_PHY2RX_DATA__6_SEL	include/ssv6200_reg.h	5496;"	d
+SET_MP_PHY2RX_DATA__7_SEL	include/ssv6200_reg.h	5502;"	d
+SET_MP_PHY_RX_WRST_N_SEL	include/ssv6200_reg.h	5500;"	d
+SET_MP_RX_FF_WPTR__0_SEL	include/ssv6200_reg.h	5488;"	d
+SET_MP_RX_FF_WPTR__1_SEL	include/ssv6200_reg.h	5487;"	d
+SET_MP_RX_FF_WPTR__2_SEL	include/ssv6200_reg.h	5486;"	d
+SET_MP_TX_FF_RPTR__0_SEL	include/ssv6200_reg.h	5499;"	d
+SET_MP_TX_FF_RPTR__1_SEL	include/ssv6200_reg.h	5485;"	d
+SET_MP_TX_FF_RPTR__2_SEL	include/ssv6200_reg.h	5503;"	d
+SET_MRX_ACK_NTF	include/ssv6200_reg.h	6812;"	d
+SET_MRX_ACK_NTF	smac/hal/ssv6006c/ssv6006C_reg.h	10924;"	d
+SET_MRX_ALC_FAIL	include/ssv6200_reg.h	6808;"	d
+SET_MRX_ALC_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	10920;"	d
+SET_MRX_BAR_NTF	include/ssv6200_reg.h	6817;"	d
+SET_MRX_BAR_NTF	smac/hal/ssv6006c/ssv6006C_reg.h	10929;"	d
+SET_MRX_BA_NTF	include/ssv6200_reg.h	6813;"	d
+SET_MRX_BA_NTF	smac/hal/ssv6006c/ssv6006C_reg.h	10925;"	d
+SET_MRX_CCA	include/ssv6200_reg.h	6443;"	d
+SET_MRX_CLK_EN	include/ssv6200_reg.h	6704;"	d
+SET_MRX_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10800;"	d
+SET_MRX_CSR_CLK_EN	include/ssv6200_reg.h	6723;"	d
+SET_MRX_CSR_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10819;"	d
+SET_MRX_CSR_NTF	include/ssv6200_reg.h	6820;"	d
+SET_MRX_CSR_NTF	smac/hal/ssv6006c/ssv6006C_reg.h	10932;"	d
+SET_MRX_CSR_RST	include/ssv6200_reg.h	6695;"	d
+SET_MRX_CSR_RST	smac/hal/ssv6006c/ssv6006C_reg.h	10791;"	d
+SET_MRX_CTS_NTF	include/ssv6200_reg.h	6811;"	d
+SET_MRX_CTS_NTF	smac/hal/ssv6006c/ssv6006C_reg.h	10923;"	d
+SET_MRX_DATA_NTF	include/ssv6200_reg.h	6814;"	d
+SET_MRX_DATA_NTF	smac/hal/ssv6006c/ssv6006C_reg.h	10926;"	d
+SET_MRX_DAT_CRC_NTF	include/ssv6200_reg.h	6816;"	d
+SET_MRX_DAT_CRC_NTF	smac/hal/ssv6006c/ssv6006C_reg.h	10928;"	d
+SET_MRX_DAT_NTF	include/ssv6200_reg.h	6809;"	d
+SET_MRX_DAT_NTF	smac/hal/ssv6006c/ssv6006C_reg.h	10921;"	d
+SET_MRX_DUP	include/ssv6200_reg.h	6802;"	d
+SET_MRX_DUP	smac/hal/ssv6006c/ssv6006C_reg.h	10914;"	d
+SET_MRX_ENG_CLK_EN	include/ssv6200_reg.h	6716;"	d
+SET_MRX_ENG_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10812;"	d
+SET_MRX_ENG_RST	include/ssv6200_reg.h	6681;"	d
+SET_MRX_ENG_RST	smac/hal/ssv6006c/ssv6006C_reg.h	10777;"	d
+SET_MRX_ERR	include/ssv6200_reg.h	6354;"	d
+SET_MRX_ERR	smac/hal/ssv6006c/ssv6006C_reg.h	10358;"	d
+SET_MRX_FCS_ERR	include/ssv6200_reg.h	6805;"	d
+SET_MRX_FCS_ERR	smac/hal/ssv6006c/ssv6006C_reg.h	10917;"	d
+SET_MRX_FCS_SUC	include/ssv6200_reg.h	6806;"	d
+SET_MRX_FCS_SUC	smac/hal/ssv6006c/ssv6006C_reg.h	10918;"	d
+SET_MRX_FLT_EN0	include/ssv6200_reg.h	6314;"	d
+SET_MRX_FLT_EN0	smac/hal/ssv6006c/ssv6006C_reg.h	10318;"	d
+SET_MRX_FLT_EN1	include/ssv6200_reg.h	6315;"	d
+SET_MRX_FLT_EN1	smac/hal/ssv6006c/ssv6006C_reg.h	10319;"	d
+SET_MRX_FLT_EN10	smac/hal/ssv6006c/ssv6006C_reg.h	10378;"	d
+SET_MRX_FLT_EN2	include/ssv6200_reg.h	6316;"	d
+SET_MRX_FLT_EN2	smac/hal/ssv6006c/ssv6006C_reg.h	10320;"	d
+SET_MRX_FLT_EN3	include/ssv6200_reg.h	6317;"	d
+SET_MRX_FLT_EN3	smac/hal/ssv6006c/ssv6006C_reg.h	10321;"	d
+SET_MRX_FLT_EN4	include/ssv6200_reg.h	6318;"	d
+SET_MRX_FLT_EN4	smac/hal/ssv6006c/ssv6006C_reg.h	10322;"	d
+SET_MRX_FLT_EN5	include/ssv6200_reg.h	6319;"	d
+SET_MRX_FLT_EN5	smac/hal/ssv6006c/ssv6006C_reg.h	10323;"	d
+SET_MRX_FLT_EN6	include/ssv6200_reg.h	6320;"	d
+SET_MRX_FLT_EN6	smac/hal/ssv6006c/ssv6006C_reg.h	10324;"	d
+SET_MRX_FLT_EN7	include/ssv6200_reg.h	6321;"	d
+SET_MRX_FLT_EN7	smac/hal/ssv6006c/ssv6006C_reg.h	10325;"	d
+SET_MRX_FLT_EN8	include/ssv6200_reg.h	6322;"	d
+SET_MRX_FLT_EN8	smac/hal/ssv6006c/ssv6006C_reg.h	10326;"	d
+SET_MRX_FLT_EN9	smac/hal/ssv6006c/ssv6006C_reg.h	10377;"	d
+SET_MRX_FLT_TB0	include/ssv6200_reg.h	6298;"	d
+SET_MRX_FLT_TB0	smac/hal/ssv6006c/ssv6006C_reg.h	10302;"	d
+SET_MRX_FLT_TB1	include/ssv6200_reg.h	6299;"	d
+SET_MRX_FLT_TB1	smac/hal/ssv6006c/ssv6006C_reg.h	10303;"	d
+SET_MRX_FLT_TB10	include/ssv6200_reg.h	6308;"	d
+SET_MRX_FLT_TB10	smac/hal/ssv6006c/ssv6006C_reg.h	10312;"	d
+SET_MRX_FLT_TB11	include/ssv6200_reg.h	6309;"	d
+SET_MRX_FLT_TB11	smac/hal/ssv6006c/ssv6006C_reg.h	10313;"	d
+SET_MRX_FLT_TB12	include/ssv6200_reg.h	6310;"	d
+SET_MRX_FLT_TB12	smac/hal/ssv6006c/ssv6006C_reg.h	10314;"	d
+SET_MRX_FLT_TB13	include/ssv6200_reg.h	6311;"	d
+SET_MRX_FLT_TB13	smac/hal/ssv6006c/ssv6006C_reg.h	10315;"	d
+SET_MRX_FLT_TB14	include/ssv6200_reg.h	6312;"	d
+SET_MRX_FLT_TB14	smac/hal/ssv6006c/ssv6006C_reg.h	10316;"	d
+SET_MRX_FLT_TB15	include/ssv6200_reg.h	6313;"	d
+SET_MRX_FLT_TB15	smac/hal/ssv6006c/ssv6006C_reg.h	10317;"	d
+SET_MRX_FLT_TB2	include/ssv6200_reg.h	6300;"	d
+SET_MRX_FLT_TB2	smac/hal/ssv6006c/ssv6006C_reg.h	10304;"	d
+SET_MRX_FLT_TB3	include/ssv6200_reg.h	6301;"	d
+SET_MRX_FLT_TB3	smac/hal/ssv6006c/ssv6006C_reg.h	10305;"	d
+SET_MRX_FLT_TB4	include/ssv6200_reg.h	6302;"	d
+SET_MRX_FLT_TB4	smac/hal/ssv6006c/ssv6006C_reg.h	10306;"	d
+SET_MRX_FLT_TB5	include/ssv6200_reg.h	6303;"	d
+SET_MRX_FLT_TB5	smac/hal/ssv6006c/ssv6006C_reg.h	10307;"	d
+SET_MRX_FLT_TB6	include/ssv6200_reg.h	6304;"	d
+SET_MRX_FLT_TB6	smac/hal/ssv6006c/ssv6006C_reg.h	10308;"	d
+SET_MRX_FLT_TB7	include/ssv6200_reg.h	6305;"	d
+SET_MRX_FLT_TB7	smac/hal/ssv6006c/ssv6006C_reg.h	10309;"	d
+SET_MRX_FLT_TB8	include/ssv6200_reg.h	6306;"	d
+SET_MRX_FLT_TB8	smac/hal/ssv6006c/ssv6006C_reg.h	10310;"	d
+SET_MRX_FLT_TB9	include/ssv6200_reg.h	6307;"	d
+SET_MRX_FLT_TB9	smac/hal/ssv6006c/ssv6006C_reg.h	10311;"	d
+SET_MRX_FRG	include/ssv6200_reg.h	6803;"	d
+SET_MRX_FRG	smac/hal/ssv6006c/ssv6006C_reg.h	10915;"	d
+SET_MRX_GRP	include/ssv6200_reg.h	6804;"	d
+SET_MRX_GRP	smac/hal/ssv6006c/ssv6006C_reg.h	10916;"	d
+SET_MRX_LEN_FLT	include/ssv6200_reg.h	6323;"	d
+SET_MRX_LEN_FLT	smac/hal/ssv6006c/ssv6006C_reg.h	10327;"	d
+SET_MRX_MB_MISS	include/ssv6200_reg.h	6818;"	d
+SET_MRX_MB_MISS	smac/hal/ssv6006c/ssv6006C_reg.h	10930;"	d
+SET_MRX_MCAST_CTRL_0	include/ssv6200_reg.h	6279;"	d
+SET_MRX_MCAST_CTRL_0	smac/hal/ssv6006c/ssv6006C_reg.h	10283;"	d
+SET_MRX_MCAST_CTRL_1	include/ssv6200_reg.h	6284;"	d
+SET_MRX_MCAST_CTRL_1	smac/hal/ssv6006c/ssv6006C_reg.h	10288;"	d
+SET_MRX_MCAST_CTRL_2	include/ssv6200_reg.h	6289;"	d
+SET_MRX_MCAST_CTRL_2	smac/hal/ssv6006c/ssv6006C_reg.h	10293;"	d
+SET_MRX_MCAST_CTRL_3	include/ssv6200_reg.h	6294;"	d
+SET_MRX_MCAST_CTRL_3	smac/hal/ssv6006c/ssv6006C_reg.h	10298;"	d
+SET_MRX_MCAST_MASK0_31_0	include/ssv6200_reg.h	6277;"	d
+SET_MRX_MCAST_MASK0_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	10281;"	d
+SET_MRX_MCAST_MASK0_47_32	include/ssv6200_reg.h	6278;"	d
+SET_MRX_MCAST_MASK0_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	10282;"	d
+SET_MRX_MCAST_MASK1_31_0	include/ssv6200_reg.h	6282;"	d
+SET_MRX_MCAST_MASK1_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	10286;"	d
+SET_MRX_MCAST_MASK1_47_32	include/ssv6200_reg.h	6283;"	d
+SET_MRX_MCAST_MASK1_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	10287;"	d
+SET_MRX_MCAST_MASK2_31_0	include/ssv6200_reg.h	6287;"	d
+SET_MRX_MCAST_MASK2_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	10291;"	d
+SET_MRX_MCAST_MASK2_47_32	include/ssv6200_reg.h	6288;"	d
+SET_MRX_MCAST_MASK2_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	10292;"	d
+SET_MRX_MCAST_MASK3_31_0	include/ssv6200_reg.h	6292;"	d
+SET_MRX_MCAST_MASK3_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	10296;"	d
+SET_MRX_MCAST_MASK3_47_32	include/ssv6200_reg.h	6293;"	d
+SET_MRX_MCAST_MASK3_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	10297;"	d
+SET_MRX_MCAST_TB0_31_0	include/ssv6200_reg.h	6275;"	d
+SET_MRX_MCAST_TB0_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	10279;"	d
+SET_MRX_MCAST_TB0_47_32	include/ssv6200_reg.h	6276;"	d
+SET_MRX_MCAST_TB0_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	10280;"	d
+SET_MRX_MCAST_TB1_31_0	include/ssv6200_reg.h	6280;"	d
+SET_MRX_MCAST_TB1_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	10284;"	d
+SET_MRX_MCAST_TB1_47_32	include/ssv6200_reg.h	6281;"	d
+SET_MRX_MCAST_TB1_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	10285;"	d
+SET_MRX_MCAST_TB2_31_0	include/ssv6200_reg.h	6285;"	d
+SET_MRX_MCAST_TB2_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	10289;"	d
+SET_MRX_MCAST_TB2_47_32	include/ssv6200_reg.h	6286;"	d
+SET_MRX_MCAST_TB2_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	10290;"	d
+SET_MRX_MCAST_TB3_31_0	include/ssv6200_reg.h	6290;"	d
+SET_MRX_MCAST_TB3_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	10294;"	d
+SET_MRX_MCAST_TB3_47_32	include/ssv6200_reg.h	6291;"	d
+SET_MRX_MCAST_TB3_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	10295;"	d
+SET_MRX_MISS	include/ssv6200_reg.h	6807;"	d
+SET_MRX_MISS	smac/hal/ssv6006c/ssv6006C_reg.h	10919;"	d
+SET_MRX_MNG_NTF	include/ssv6200_reg.h	6815;"	d
+SET_MRX_MNG_NTF	smac/hal/ssv6006c/ssv6006C_reg.h	10927;"	d
+SET_MRX_NIDLE_MISS	include/ssv6200_reg.h	6819;"	d
+SET_MRX_NIDLE_MISS	smac/hal/ssv6006c/ssv6006C_reg.h	10931;"	d
+SET_MRX_PHY_INFO	include/ssv6200_reg.h	6295;"	d
+SET_MRX_PHY_INFO	smac/hal/ssv6006c/ssv6006C_reg.h	10299;"	d
+SET_MRX_RTS_NTF	include/ssv6200_reg.h	6810;"	d
+SET_MRX_RTS_NTF	smac/hal/ssv6006c/ssv6006C_reg.h	10922;"	d
+SET_MRX_RX_EN	include/ssv6200_reg.h	6450;"	d
+SET_MRX_STP_EN	include/ssv6200_reg.h	6327;"	d
+SET_MRX_STP_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10331;"	d
+SET_MRX_STP_OFST	include/ssv6200_reg.h	6328;"	d
+SET_MRX_STP_OFST	smac/hal/ssv6006c/ssv6006C_reg.h	10332;"	d
+SET_MRX_SW_RST	include/ssv6200_reg.h	6669;"	d
+SET_MRX_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	10765;"	d
+SET_MRX_WD	include/ssv6200_reg.h	6344;"	d
+SET_MRX_WD	smac/hal/ssv6006c/ssv6006C_reg.h	10348;"	d
+SET_MS0TMR_CLK_EN	include/ssv6200_reg.h	4957;"	d
+SET_MS0TMR_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9316;"	d
+SET_MS0TMR_SW_RST	include/ssv6200_reg.h	4923;"	d
+SET_MS0TMR_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	9282;"	d
+SET_MS1TMR_CLK_EN	include/ssv6200_reg.h	4958;"	d
+SET_MS1TMR_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9317;"	d
+SET_MS1TMR_SW_RST	include/ssv6200_reg.h	4924;"	d
+SET_MS1TMR_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	9283;"	d
+SET_MS2TMR_CLK_EN	include/ssv6200_reg.h	4959;"	d
+SET_MS2TMR_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9318;"	d
+SET_MS2TMR_SW_RST	include/ssv6200_reg.h	4925;"	d
+SET_MS2TMR_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	9284;"	d
+SET_MS3TMR_CLK_EN	include/ssv6200_reg.h	4960;"	d
+SET_MS3TMR_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9319;"	d
+SET_MS3TMR_SW_RST	include/ssv6200_reg.h	4926;"	d
+SET_MS3TMR_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	9285;"	d
+SET_MTX_ACK_DUR0	include/ssv6200_reg.h	6409;"	d
+SET_MTX_ACK_FAIL	include/ssv6200_reg.h	6798;"	d
+SET_MTX_ACK_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	10910;"	d
+SET_MTX_ACK_TX	include/ssv6200_reg.h	6800;"	d
+SET_MTX_ACK_TX	smac/hal/ssv6006c/ssv6006C_reg.h	10912;"	d
+SET_MTX_AMPDU_CRC8_AUTO	smac/hal/ssv6006c/ssv6006C_reg.h	10410;"	d
+SET_MTX_AMPDU_CRC_AUTO	include/ssv6200_reg.h	6406;"	d
+SET_MTX_AMPDU_SET_DIF	include/ssv6200_reg.h	6418;"	d
+SET_MTX_AUTO_BCN_ONGOING	include/ssv6200_reg.h	6432;"	d
+SET_MTX_AUTO_BCN_ONGOING	smac/hal/ssv6006c/ssv6006C_reg.h	10506;"	d
+SET_MTX_AUTO_FLUSH_Q4	include/ssv6200_reg.h	6429;"	d
+SET_MTX_BCN_AUTO_SEQ_NO	smac/hal/ssv6006c/ssv6006C_reg.h	10503;"	d
+SET_MTX_BCN_CFG_VLD	include/ssv6200_reg.h	6431;"	d
+SET_MTX_BCN_CFG_VLD	smac/hal/ssv6006c/ssv6006C_reg.h	10505;"	d
+SET_MTX_BCN_ENG_RST	include/ssv6200_reg.h	6680;"	d
+SET_MTX_BCN_ENG_RST	smac/hal/ssv6006c/ssv6006C_reg.h	10776;"	d
+SET_MTX_BCN_PERIOD	include/ssv6200_reg.h	6434;"	d
+SET_MTX_BCN_PERIOD	smac/hal/ssv6006c/ssv6006C_reg.h	10508;"	d
+SET_MTX_BCN_PKTID_CH_LOCK	include/ssv6200_reg.h	6430;"	d
+SET_MTX_BCN_PKTID_CH_LOCK	smac/hal/ssv6006c/ssv6006C_reg.h	10504;"	d
+SET_MTX_BCN_PKT_ID0	include/ssv6200_reg.h	6438;"	d
+SET_MTX_BCN_PKT_ID0	smac/hal/ssv6006c/ssv6006C_reg.h	10488;"	d
+SET_MTX_BCN_PKT_ID1	include/ssv6200_reg.h	6440;"	d
+SET_MTX_BCN_PKT_ID1	smac/hal/ssv6006c/ssv6006C_reg.h	10489;"	d
+SET_MTX_BCN_SW_RST	include/ssv6200_reg.h	6668;"	d
+SET_MTX_BCN_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	10764;"	d
+SET_MTX_BCN_TIMER	include/ssv6200_reg.h	6433;"	d
+SET_MTX_BCN_TIMER	smac/hal/ssv6006c/ssv6006C_reg.h	10507;"	d
+SET_MTX_BCN_TIMER_EN	include/ssv6200_reg.h	6424;"	d
+SET_MTX_BCN_TIMER_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10498;"	d
+SET_MTX_BCN_TSF_L	include/ssv6200_reg.h	6436;"	d
+SET_MTX_BCN_TSF_L	smac/hal/ssv6006c/ssv6006C_reg.h	10509;"	d
+SET_MTX_BCN_TSF_U	include/ssv6200_reg.h	6437;"	d
+SET_MTX_BCN_TSF_U	smac/hal/ssv6006c/ssv6006C_reg.h	10510;"	d
+SET_MTX_BLOCKTX_IGNORE_BT_BUSY	smac/hal/ssv6006c/ssv6006C_reg.h	10411;"	d
+SET_MTX_BLOCKTX_IGNORE_TOMAC_CCA_CS	smac/hal/ssv6006c/ssv6006C_reg.h	10415;"	d
+SET_MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_PRIMARY	smac/hal/ssv6006c/ssv6006C_reg.h	10417;"	d
+SET_MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_SECONDARY	smac/hal/ssv6006c/ssv6006C_reg.h	10416;"	d
+SET_MTX_BLOCKTX_IGNORE_TOMAC_RX_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10414;"	d
+SET_MTX_BLOCKTX_IGNORE_TOMAC_TX_IP	smac/hal/ssv6006c/ssv6006C_reg.h	10413;"	d
+SET_MTX_CCA	include/ssv6200_reg.h	6442;"	d
+SET_MTX_CHST_ENG_RST	include/ssv6200_reg.h	6679;"	d
+SET_MTX_CHST_ENG_RST	smac/hal/ssv6006c/ssv6006C_reg.h	10775;"	d
+SET_MTX_CHST_SW_RST	include/ssv6200_reg.h	6667;"	d
+SET_MTX_CHST_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	10763;"	d
+SET_MTX_CTS_SET_DIF	include/ssv6200_reg.h	6417;"	d
+SET_MTX_CTS_TX	include/ssv6200_reg.h	6801;"	d
+SET_MTX_CTS_TX	smac/hal/ssv6006c/ssv6006C_reg.h	10913;"	d
+SET_MTX_DBGOPT_FORCE_DO_RTS_CTS_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	10479;"	d
+SET_MTX_DBGOPT_FORCE_DO_RTS_CTS_MODE_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10482;"	d
+SET_MTX_DBGOPT_FORCE_TXCTRL_RATE	smac/hal/ssv6006c/ssv6006C_reg.h	10478;"	d
+SET_MTX_DBGOPT_FORCE_TXCTRL_RATE_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10481;"	d
+SET_MTX_DBGOPT_FORCE_TXMAJOR_RATE	smac/hal/ssv6006c/ssv6006C_reg.h	10477;"	d
+SET_MTX_DBGOPT_FORCE_TXMAJOR_RATE_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10480;"	d
+SET_MTX_DBG_PHYRX_IFS_DELTATIME	smac/hal/ssv6006c/ssv6006C_reg.h	10532;"	d
+SET_MTX_DMA_FSM	include/ssv6200_reg.h	6444;"	d
+SET_MTX_DMA_REQ	include/ssv6200_reg.h	6447;"	d
+SET_MTX_DTIM_CNT_AUTO_FILL	smac/hal/ssv6006c/ssv6006C_reg.h	10500;"	d
+SET_MTX_DTIM_NUM	include/ssv6200_reg.h	6435;"	d
+SET_MTX_DTIM_NUM	smac/hal/ssv6006c/ssv6006C_reg.h	10492;"	d
+SET_MTX_DTIM_OFST0	include/ssv6200_reg.h	6439;"	d
+SET_MTX_DTIM_OFST0	smac/hal/ssv6006c/ssv6006C_reg.h	10490;"	d
+SET_MTX_DTIM_OFST1	include/ssv6200_reg.h	6441;"	d
+SET_MTX_DTIM_OFST1	smac/hal/ssv6006c/ssv6006C_reg.h	10491;"	d
+SET_MTX_DUR_BURST_SIFS	include/ssv6200_reg.h	6466;"	d
+SET_MTX_DUR_BURST_SIFS_G	include/ssv6200_reg.h	6470;"	d
+SET_MTX_DUR_RSP_EIFS	include/ssv6200_reg.h	6468;"	d
+SET_MTX_DUR_RSP_EIFS_G	include/ssv6200_reg.h	6472;"	d
+SET_MTX_DUR_RSP_SIFS	include/ssv6200_reg.h	6465;"	d
+SET_MTX_DUR_RSP_SIFS_G	include/ssv6200_reg.h	6469;"	d
+SET_MTX_DUR_RSP_TOUT_B	include/ssv6200_reg.h	6463;"	d
+SET_MTX_DUR_RSP_TOUT_G	include/ssv6200_reg.h	6464;"	d
+SET_MTX_DUR_SLOT	include/ssv6200_reg.h	6467;"	d
+SET_MTX_DUR_SLOT_G	include/ssv6200_reg.h	6471;"	d
+SET_MTX_EDCCA_TOUT	include/ssv6200_reg.h	6419;"	d
+SET_MTX_EN_INT_BCN	include/ssv6200_reg.h	6422;"	d
+SET_MTX_EN_INT_BCN	smac/hal/ssv6006c/ssv6006C_reg.h	10496;"	d
+SET_MTX_EN_INT_DTIM	include/ssv6200_reg.h	6423;"	d
+SET_MTX_EN_INT_DTIM	smac/hal/ssv6006c/ssv6006C_reg.h	10497;"	d
+SET_MTX_EN_INT_Q0_Q_EMPTY	include/ssv6200_reg.h	6394;"	d
+SET_MTX_EN_INT_Q0_Q_EMPTY	smac/hal/ssv6006c/ssv6006C_reg.h	10396;"	d
+SET_MTX_EN_INT_Q0_TXOP_RUNOUT	include/ssv6200_reg.h	6395;"	d
+SET_MTX_EN_INT_Q0_TXOP_RUNOUT	smac/hal/ssv6006c/ssv6006C_reg.h	10397;"	d
+SET_MTX_EN_INT_Q1_Q_EMPTY	include/ssv6200_reg.h	6396;"	d
+SET_MTX_EN_INT_Q1_Q_EMPTY	smac/hal/ssv6006c/ssv6006C_reg.h	10398;"	d
+SET_MTX_EN_INT_Q1_TXOP_RUNOUT	include/ssv6200_reg.h	6397;"	d
+SET_MTX_EN_INT_Q1_TXOP_RUNOUT	smac/hal/ssv6006c/ssv6006C_reg.h	10399;"	d
+SET_MTX_EN_INT_Q2_Q_EMPTY	include/ssv6200_reg.h	6398;"	d
+SET_MTX_EN_INT_Q2_Q_EMPTY	smac/hal/ssv6006c/ssv6006C_reg.h	10400;"	d
+SET_MTX_EN_INT_Q2_TXOP_RUNOUT	include/ssv6200_reg.h	6399;"	d
+SET_MTX_EN_INT_Q2_TXOP_RUNOUT	smac/hal/ssv6006c/ssv6006C_reg.h	10401;"	d
+SET_MTX_EN_INT_Q3_Q_EMPTY	include/ssv6200_reg.h	6400;"	d
+SET_MTX_EN_INT_Q3_Q_EMPTY	smac/hal/ssv6006c/ssv6006C_reg.h	10402;"	d
+SET_MTX_EN_INT_Q3_TXOP_RUNOUT	include/ssv6200_reg.h	6401;"	d
+SET_MTX_EN_INT_Q3_TXOP_RUNOUT	smac/hal/ssv6006c/ssv6006C_reg.h	10403;"	d
+SET_MTX_EN_INT_Q4_Q_EMPTY	include/ssv6200_reg.h	6402;"	d
+SET_MTX_EN_INT_Q4_Q_EMPTY	smac/hal/ssv6006c/ssv6006C_reg.h	10404;"	d
+SET_MTX_EN_INT_Q4_TXOP_RUNOUT	include/ssv6200_reg.h	6403;"	d
+SET_MTX_EN_INT_Q4_TXOP_RUNOUT	smac/hal/ssv6006c/ssv6006C_reg.h	10405;"	d
+SET_MTX_EN_INT_Q5_Q_EMPTY	smac/hal/ssv6006c/ssv6006C_reg.h	10406;"	d
+SET_MTX_EN_INT_Q5_TXOP_RUNOUT	smac/hal/ssv6006c/ssv6006C_reg.h	10407;"	d
+SET_MTX_FAIL	include/ssv6200_reg.h	6793;"	d
+SET_MTX_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	10905;"	d
+SET_MTX_FAST_RSP_MODE	include/ssv6200_reg.h	6407;"	d
+SET_MTX_FORCE_BKF_RXEN0	include/ssv6200_reg.h	6413;"	d
+SET_MTX_FORCE_CS_IDLE	include/ssv6200_reg.h	6412;"	d
+SET_MTX_FORCE_DMA_RXEN0	include/ssv6200_reg.h	6414;"	d
+SET_MTX_FORCE_RXEN0	include/ssv6200_reg.h	6415;"	d
+SET_MTX_FRM	include/ssv6200_reg.h	6799;"	d
+SET_MTX_FRM	smac/hal/ssv6006c/ssv6006C_reg.h	10911;"	d
+SET_MTX_GNT_LOCK	include/ssv6200_reg.h	6446;"	d
+SET_MTX_GRP	include/ssv6200_reg.h	6792;"	d
+SET_MTX_GRP	smac/hal/ssv6006c/ssv6006C_reg.h	10904;"	d
+SET_MTX_HALT_IGNORE_RXREQ_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10439;"	d
+SET_MTX_HALT_IGNORE_TXREQ_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10438;"	d
+SET_MTX_HALT_MNG_UNTIL_DTIM	include/ssv6200_reg.h	6427;"	d
+SET_MTX_HALT_MODE0	smac/hal/ssv6006c/ssv6006C_reg.h	10436;"	d
+SET_MTX_HALT_Q_MB	include/ssv6200_reg.h	6416;"	d
+SET_MTX_HALT_Q_MB	smac/hal/ssv6006c/ssv6006C_reg.h	10418;"	d
+SET_MTX_IGNORE_PHYRX_IFS_DELTATIME	smac/hal/ssv6006c/ssv6006C_reg.h	10419;"	d
+SET_MTX_INT_BCN	include/ssv6200_reg.h	6420;"	d
+SET_MTX_INT_BCN	smac/hal/ssv6006c/ssv6006C_reg.h	10495;"	d
+SET_MTX_INT_DTIM	include/ssv6200_reg.h	6421;"	d
+SET_MTX_INT_DTIM	smac/hal/ssv6006c/ssv6006C_reg.h	10494;"	d
+SET_MTX_INT_DTIM_NUM	include/ssv6200_reg.h	6428;"	d
+SET_MTX_INT_DTIM_NUM	smac/hal/ssv6006c/ssv6006C_reg.h	10493;"	d
+SET_MTX_INT_Q0_Q_EMPTY	include/ssv6200_reg.h	6384;"	d
+SET_MTX_INT_Q0_Q_EMPTY	smac/hal/ssv6006c/ssv6006C_reg.h	10384;"	d
+SET_MTX_INT_Q0_TXOP_RUNOUT	include/ssv6200_reg.h	6385;"	d
+SET_MTX_INT_Q0_TXOP_RUNOUT	smac/hal/ssv6006c/ssv6006C_reg.h	10385;"	d
+SET_MTX_INT_Q1_Q_EMPTY	include/ssv6200_reg.h	6386;"	d
+SET_MTX_INT_Q1_Q_EMPTY	smac/hal/ssv6006c/ssv6006C_reg.h	10386;"	d
+SET_MTX_INT_Q1_TXOP_RUNOUT	include/ssv6200_reg.h	6387;"	d
+SET_MTX_INT_Q1_TXOP_RUNOUT	smac/hal/ssv6006c/ssv6006C_reg.h	10387;"	d
+SET_MTX_INT_Q2_Q_EMPTY	include/ssv6200_reg.h	6388;"	d
+SET_MTX_INT_Q2_Q_EMPTY	smac/hal/ssv6006c/ssv6006C_reg.h	10388;"	d
+SET_MTX_INT_Q2_TXOP_RUNOUT	include/ssv6200_reg.h	6389;"	d
+SET_MTX_INT_Q2_TXOP_RUNOUT	smac/hal/ssv6006c/ssv6006C_reg.h	10389;"	d
+SET_MTX_INT_Q3_Q_EMPTY	include/ssv6200_reg.h	6390;"	d
+SET_MTX_INT_Q3_Q_EMPTY	smac/hal/ssv6006c/ssv6006C_reg.h	10390;"	d
+SET_MTX_INT_Q3_TXOP_RUNOUT	include/ssv6200_reg.h	6391;"	d
+SET_MTX_INT_Q3_TXOP_RUNOUT	smac/hal/ssv6006c/ssv6006C_reg.h	10391;"	d
+SET_MTX_INT_Q4_Q_EMPTY	include/ssv6200_reg.h	6392;"	d
+SET_MTX_INT_Q4_Q_EMPTY	smac/hal/ssv6006c/ssv6006C_reg.h	10392;"	d
+SET_MTX_INT_Q4_TXOP_RUNOUT	include/ssv6200_reg.h	6393;"	d
+SET_MTX_INT_Q4_TXOP_RUNOUT	smac/hal/ssv6006c/ssv6006C_reg.h	10393;"	d
+SET_MTX_INT_Q5_Q_EMPTY	smac/hal/ssv6006c/ssv6006C_reg.h	10394;"	d
+SET_MTX_INT_Q5_TXOP_RUNOUT	smac/hal/ssv6006c/ssv6006C_reg.h	10395;"	d
+SET_MTX_M2M_SLOW_PRD	include/ssv6200_reg.h	6405;"	d
+SET_MTX_M2M_SLOW_PRD	smac/hal/ssv6006c/ssv6006C_reg.h	10409;"	d
+SET_MTX_MIB_CNT0	include/ssv6200_reg.h	6476;"	d
+SET_MTX_MIB_CNT0	smac/hal/ssv6006c/ssv6006C_reg.h	10441;"	d
+SET_MTX_MIB_CNT1	include/ssv6200_reg.h	6478;"	d
+SET_MTX_MIB_CNT1	smac/hal/ssv6006c/ssv6006C_reg.h	10443;"	d
+SET_MTX_MIB_CNT2	smac/hal/ssv6006c/ssv6006C_reg.h	10445;"	d
+SET_MTX_MIB_CNT3	smac/hal/ssv6006c/ssv6006C_reg.h	10447;"	d
+SET_MTX_MIB_CNT4	smac/hal/ssv6006c/ssv6006C_reg.h	10449;"	d
+SET_MTX_MIB_CNT5	smac/hal/ssv6006c/ssv6006C_reg.h	10451;"	d
+SET_MTX_MIB_CNT6	smac/hal/ssv6006c/ssv6006C_reg.h	10453;"	d
+SET_MTX_MIB_CNT7	smac/hal/ssv6006c/ssv6006C_reg.h	10455;"	d
+SET_MTX_MIB_EN0	include/ssv6200_reg.h	6477;"	d
+SET_MTX_MIB_EN0	smac/hal/ssv6006c/ssv6006C_reg.h	10442;"	d
+SET_MTX_MIB_EN1	include/ssv6200_reg.h	6479;"	d
+SET_MTX_MIB_EN1	smac/hal/ssv6006c/ssv6006C_reg.h	10444;"	d
+SET_MTX_MIB_EN2	smac/hal/ssv6006c/ssv6006C_reg.h	10446;"	d
+SET_MTX_MIB_EN3	smac/hal/ssv6006c/ssv6006C_reg.h	10448;"	d
+SET_MTX_MIB_EN4	smac/hal/ssv6006c/ssv6006C_reg.h	10450;"	d
+SET_MTX_MIB_EN5	smac/hal/ssv6006c/ssv6006C_reg.h	10452;"	d
+SET_MTX_MIB_EN6	smac/hal/ssv6006c/ssv6006C_reg.h	10454;"	d
+SET_MTX_MIB_EN7	smac/hal/ssv6006c/ssv6006C_reg.h	10456;"	d
+SET_MTX_MISC_CLK_EN	include/ssv6200_reg.h	6702;"	d
+SET_MTX_MISC_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10798;"	d
+SET_MTX_MISC_CSR_RST	include/ssv6200_reg.h	6688;"	d
+SET_MTX_MISC_CSR_RST	smac/hal/ssv6006c/ssv6006C_reg.h	10784;"	d
+SET_MTX_MISC_ENG_CLK_EN	include/ssv6200_reg.h	6714;"	d
+SET_MTX_MISC_ENG_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10810;"	d
+SET_MTX_MISC_ENG_RST	include/ssv6200_reg.h	6677;"	d
+SET_MTX_MISC_ENG_RST	smac/hal/ssv6006c/ssv6006C_reg.h	10773;"	d
+SET_MTX_MISC_SW_RST	include/ssv6200_reg.h	6665;"	d
+SET_MTX_MISC_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	10761;"	d
+SET_MTX_MNG_UPTHOLD_INT	include/ssv6200_reg.h	5613;"	d
+SET_MTX_MTX2PHY_SLOW	include/ssv6200_reg.h	6404;"	d
+SET_MTX_MTX2PHY_SLOW	smac/hal/ssv6006c/ssv6006C_reg.h	10408;"	d
+SET_MTX_MULTI_RETRY	include/ssv6200_reg.h	6795;"	d
+SET_MTX_MULTI_RETRY	smac/hal/ssv6006c/ssv6006C_reg.h	10907;"	d
+SET_MTX_NAV	include/ssv6200_reg.h	6475;"	d
+SET_MTX_NAV	smac/hal/ssv6006c/ssv6006C_reg.h	10537;"	d
+SET_MTX_QUE0_CSR_RST	include/ssv6200_reg.h	6689;"	d
+SET_MTX_QUE0_CSR_RST	smac/hal/ssv6006c/ssv6006C_reg.h	10785;"	d
+SET_MTX_QUE1_CSR_RST	include/ssv6200_reg.h	6690;"	d
+SET_MTX_QUE1_CSR_RST	smac/hal/ssv6006c/ssv6006C_reg.h	10786;"	d
+SET_MTX_QUE2_CSR_RST	include/ssv6200_reg.h	6691;"	d
+SET_MTX_QUE2_CSR_RST	smac/hal/ssv6006c/ssv6006C_reg.h	10787;"	d
+SET_MTX_QUE3_CSR_RST	include/ssv6200_reg.h	6692;"	d
+SET_MTX_QUE3_CSR_RST	smac/hal/ssv6006c/ssv6006C_reg.h	10788;"	d
+SET_MTX_QUE4_CSR_RST	include/ssv6200_reg.h	6693;"	d
+SET_MTX_QUE4_CSR_RST	smac/hal/ssv6006c/ssv6006C_reg.h	10789;"	d
+SET_MTX_QUE5_CSR_RST	include/ssv6200_reg.h	6694;"	d
+SET_MTX_QUE5_CSR_RST	smac/hal/ssv6006c/ssv6006C_reg.h	10790;"	d
+SET_MTX_QUE_CLK_EN	include/ssv6200_reg.h	6703;"	d
+SET_MTX_QUE_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10799;"	d
+SET_MTX_QUE_ENG_CLK_EN	include/ssv6200_reg.h	6715;"	d
+SET_MTX_QUE_ENG_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10811;"	d
+SET_MTX_QUE_ENG_RST	include/ssv6200_reg.h	6678;"	d
+SET_MTX_QUE_ENG_RST	smac/hal/ssv6006c/ssv6006C_reg.h	10774;"	d
+SET_MTX_QUE_SW_RST	include/ssv6200_reg.h	6666;"	d
+SET_MTX_QUE_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	10762;"	d
+SET_MTX_Q_REQ	include/ssv6200_reg.h	6448;"	d
+SET_MTX_RATERPT_HWID	smac/hal/ssv6006c/ssv6006C_reg.h	10475;"	d
+SET_MTX_RAW_DATA_MODE	include/ssv6200_reg.h	6408;"	d
+SET_MTX_RAW_DATA_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	10412;"	d
+SET_MTX_RESPFRM_INFO_00	smac/hal/ssv6006c/ssv6006C_reg.h	10666;"	d
+SET_MTX_RESPFRM_INFO_01	smac/hal/ssv6006c/ssv6006C_reg.h	10667;"	d
+SET_MTX_RESPFRM_INFO_02	smac/hal/ssv6006c/ssv6006C_reg.h	10668;"	d
+SET_MTX_RESPFRM_INFO_03	smac/hal/ssv6006c/ssv6006C_reg.h	10669;"	d
+SET_MTX_RESPFRM_INFO_11	smac/hal/ssv6006c/ssv6006C_reg.h	10670;"	d
+SET_MTX_RESPFRM_INFO_12	smac/hal/ssv6006c/ssv6006C_reg.h	10671;"	d
+SET_MTX_RESPFRM_INFO_13	smac/hal/ssv6006c/ssv6006C_reg.h	10672;"	d
+SET_MTX_RESPFRM_INFO_90_B0	smac/hal/ssv6006c/ssv6006C_reg.h	10673;"	d
+SET_MTX_RESPFRM_INFO_91_B1	smac/hal/ssv6006c/ssv6006C_reg.h	10674;"	d
+SET_MTX_RESPFRM_INFO_92_B2	smac/hal/ssv6006c/ssv6006C_reg.h	10675;"	d
+SET_MTX_RESPFRM_INFO_93_B3	smac/hal/ssv6006c/ssv6006C_reg.h	10676;"	d
+SET_MTX_RESPFRM_INFO_94_B4	smac/hal/ssv6006c/ssv6006C_reg.h	10677;"	d
+SET_MTX_RESPFRM_INFO_95_B5	smac/hal/ssv6006c/ssv6006C_reg.h	10678;"	d
+SET_MTX_RESPFRM_INFO_96_B6	smac/hal/ssv6006c/ssv6006C_reg.h	10679;"	d
+SET_MTX_RESPFRM_INFO_97_B7	smac/hal/ssv6006c/ssv6006C_reg.h	10680;"	d
+SET_MTX_RESPFRM_INFO_C0	smac/hal/ssv6006c/ssv6006C_reg.h	10681;"	d
+SET_MTX_RESPFRM_INFO_C1	smac/hal/ssv6006c/ssv6006C_reg.h	10682;"	d
+SET_MTX_RESPFRM_INFO_C2	smac/hal/ssv6006c/ssv6006C_reg.h	10683;"	d
+SET_MTX_RESPFRM_INFO_C3	smac/hal/ssv6006c/ssv6006C_reg.h	10684;"	d
+SET_MTX_RESPFRM_INFO_C4	smac/hal/ssv6006c/ssv6006C_reg.h	10685;"	d
+SET_MTX_RESPFRM_INFO_C5	smac/hal/ssv6006c/ssv6006C_reg.h	10686;"	d
+SET_MTX_RESPFRM_INFO_C6	smac/hal/ssv6006c/ssv6006C_reg.h	10687;"	d
+SET_MTX_RESPFRM_INFO_C7	smac/hal/ssv6006c/ssv6006C_reg.h	10688;"	d
+SET_MTX_RESPFRM_INFO_D0	smac/hal/ssv6006c/ssv6006C_reg.h	10689;"	d
+SET_MTX_RESPFRM_INFO_D1	smac/hal/ssv6006c/ssv6006C_reg.h	10690;"	d
+SET_MTX_RESPFRM_INFO_D2	smac/hal/ssv6006c/ssv6006C_reg.h	10691;"	d
+SET_MTX_RESPFRM_INFO_D3	smac/hal/ssv6006c/ssv6006C_reg.h	10692;"	d
+SET_MTX_RESPFRM_INFO_D4	smac/hal/ssv6006c/ssv6006C_reg.h	10693;"	d
+SET_MTX_RESPFRM_INFO_D5	smac/hal/ssv6006c/ssv6006C_reg.h	10694;"	d
+SET_MTX_RESPFRM_INFO_D6	smac/hal/ssv6006c/ssv6006C_reg.h	10695;"	d
+SET_MTX_RESPFRM_INFO_D7	smac/hal/ssv6006c/ssv6006C_reg.h	10696;"	d
+SET_MTX_RESPFRM_INFO_D8	smac/hal/ssv6006c/ssv6006C_reg.h	10697;"	d
+SET_MTX_RESPFRM_INFO_D9	smac/hal/ssv6006c/ssv6006C_reg.h	10698;"	d
+SET_MTX_RESPFRM_INFO_DA	smac/hal/ssv6006c/ssv6006C_reg.h	10699;"	d
+SET_MTX_RESPFRM_INFO_DB	smac/hal/ssv6006c/ssv6006C_reg.h	10700;"	d
+SET_MTX_RESPFRM_INFO_DC	smac/hal/ssv6006c/ssv6006C_reg.h	10701;"	d
+SET_MTX_RESPFRM_INFO_DD	smac/hal/ssv6006c/ssv6006C_reg.h	10702;"	d
+SET_MTX_RESPFRM_INFO_DE	smac/hal/ssv6006c/ssv6006C_reg.h	10703;"	d
+SET_MTX_RESPFRM_INFO_DF	smac/hal/ssv6006c/ssv6006C_reg.h	10704;"	d
+SET_MTX_RESPFRM_INFO_EXCEPTION	smac/hal/ssv6006c/ssv6006C_reg.h	10665;"	d
+SET_MTX_RESPFRM_RATE_00	smac/hal/ssv6006c/ssv6006C_reg.h	10626;"	d
+SET_MTX_RESPFRM_RATE_01	smac/hal/ssv6006c/ssv6006C_reg.h	10627;"	d
+SET_MTX_RESPFRM_RATE_02	smac/hal/ssv6006c/ssv6006C_reg.h	10628;"	d
+SET_MTX_RESPFRM_RATE_03	smac/hal/ssv6006c/ssv6006C_reg.h	10629;"	d
+SET_MTX_RESPFRM_RATE_11	smac/hal/ssv6006c/ssv6006C_reg.h	10630;"	d
+SET_MTX_RESPFRM_RATE_12	smac/hal/ssv6006c/ssv6006C_reg.h	10631;"	d
+SET_MTX_RESPFRM_RATE_13	smac/hal/ssv6006c/ssv6006C_reg.h	10632;"	d
+SET_MTX_RESPFRM_RATE_90_B0	smac/hal/ssv6006c/ssv6006C_reg.h	10633;"	d
+SET_MTX_RESPFRM_RATE_91_B1	smac/hal/ssv6006c/ssv6006C_reg.h	10634;"	d
+SET_MTX_RESPFRM_RATE_92_B2	smac/hal/ssv6006c/ssv6006C_reg.h	10635;"	d
+SET_MTX_RESPFRM_RATE_93_B3	smac/hal/ssv6006c/ssv6006C_reg.h	10636;"	d
+SET_MTX_RESPFRM_RATE_94_B4	smac/hal/ssv6006c/ssv6006C_reg.h	10637;"	d
+SET_MTX_RESPFRM_RATE_95_B5	smac/hal/ssv6006c/ssv6006C_reg.h	10638;"	d
+SET_MTX_RESPFRM_RATE_96_B6	smac/hal/ssv6006c/ssv6006C_reg.h	10639;"	d
+SET_MTX_RESPFRM_RATE_97_B7	smac/hal/ssv6006c/ssv6006C_reg.h	10640;"	d
+SET_MTX_RESPFRM_RATE_C0_E0	smac/hal/ssv6006c/ssv6006C_reg.h	10641;"	d
+SET_MTX_RESPFRM_RATE_C1_E1	smac/hal/ssv6006c/ssv6006C_reg.h	10642;"	d
+SET_MTX_RESPFRM_RATE_C2_E2	smac/hal/ssv6006c/ssv6006C_reg.h	10643;"	d
+SET_MTX_RESPFRM_RATE_C3_E3	smac/hal/ssv6006c/ssv6006C_reg.h	10644;"	d
+SET_MTX_RESPFRM_RATE_C4_E4	smac/hal/ssv6006c/ssv6006C_reg.h	10645;"	d
+SET_MTX_RESPFRM_RATE_C5_E5	smac/hal/ssv6006c/ssv6006C_reg.h	10646;"	d
+SET_MTX_RESPFRM_RATE_C6_E6	smac/hal/ssv6006c/ssv6006C_reg.h	10647;"	d
+SET_MTX_RESPFRM_RATE_C7_E7	smac/hal/ssv6006c/ssv6006C_reg.h	10648;"	d
+SET_MTX_RESPFRM_RATE_D0_F0	smac/hal/ssv6006c/ssv6006C_reg.h	10649;"	d
+SET_MTX_RESPFRM_RATE_D1_F1	smac/hal/ssv6006c/ssv6006C_reg.h	10650;"	d
+SET_MTX_RESPFRM_RATE_D2_F2	smac/hal/ssv6006c/ssv6006C_reg.h	10651;"	d
+SET_MTX_RESPFRM_RATE_D3_F3	smac/hal/ssv6006c/ssv6006C_reg.h	10652;"	d
+SET_MTX_RESPFRM_RATE_D4_F4	smac/hal/ssv6006c/ssv6006C_reg.h	10653;"	d
+SET_MTX_RESPFRM_RATE_D5_F5	smac/hal/ssv6006c/ssv6006C_reg.h	10654;"	d
+SET_MTX_RESPFRM_RATE_D6_F6	smac/hal/ssv6006c/ssv6006C_reg.h	10655;"	d
+SET_MTX_RESPFRM_RATE_D7_F7	smac/hal/ssv6006c/ssv6006C_reg.h	10656;"	d
+SET_MTX_RESPFRM_RATE_D8_F8	smac/hal/ssv6006c/ssv6006C_reg.h	10657;"	d
+SET_MTX_RESPFRM_RATE_D9_F9	smac/hal/ssv6006c/ssv6006C_reg.h	10658;"	d
+SET_MTX_RESPFRM_RATE_DA_FA	smac/hal/ssv6006c/ssv6006C_reg.h	10659;"	d
+SET_MTX_RESPFRM_RATE_DB_FB	smac/hal/ssv6006c/ssv6006C_reg.h	10660;"	d
+SET_MTX_RESPFRM_RATE_DC_FC	smac/hal/ssv6006c/ssv6006C_reg.h	10661;"	d
+SET_MTX_RESPFRM_RATE_DD_FD	smac/hal/ssv6006c/ssv6006C_reg.h	10662;"	d
+SET_MTX_RESPFRM_RATE_DE_FE	smac/hal/ssv6006c/ssv6006C_reg.h	10663;"	d
+SET_MTX_RESPFRM_RATE_DF_FF	smac/hal/ssv6006c/ssv6006C_reg.h	10664;"	d
+SET_MTX_RESPFRM_RATE_EXCEPTION	smac/hal/ssv6006c/ssv6006C_reg.h	10625;"	d
+SET_MTX_RETRY	include/ssv6200_reg.h	6794;"	d
+SET_MTX_RETRY	smac/hal/ssv6006c/ssv6006C_reg.h	10906;"	d
+SET_MTX_RTS_FAIL	include/ssv6200_reg.h	6797;"	d
+SET_MTX_RTS_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	10909;"	d
+SET_MTX_RTS_SUCC	include/ssv6200_reg.h	6796;"	d
+SET_MTX_RTS_SUCC	smac/hal/ssv6006c/ssv6006C_reg.h	10908;"	d
+SET_MTX_SELFSTA_PS	smac/hal/ssv6006c/ssv6006C_reg.h	10420;"	d
+SET_MTX_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	10760;"	d
+SET_MTX_TIME_STAMP_AUTO_FILL	include/ssv6200_reg.h	6425;"	d
+SET_MTX_TIME_STAMP_AUTO_FILL	smac/hal/ssv6006c/ssv6006C_reg.h	10499;"	d
+SET_MTX_TSF_AUTO_BCN	include/ssv6200_reg.h	6410;"	d
+SET_MTX_TSF_AUTO_MISC	include/ssv6200_reg.h	6411;"	d
+SET_MTX_TSF_TIMER_EN	include/ssv6200_reg.h	6426;"	d
+SET_MTX_TSF_TIMER_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10501;"	d
+SET_MTX_TX_EN	include/ssv6200_reg.h	6449;"	d
+SET_MTX_WSID0_FRM	include/ssv6200_reg.h	6789;"	d
+SET_MTX_WSID0_FRM	smac/hal/ssv6006c/ssv6006C_reg.h	10901;"	d
+SET_MTX_WSID0_RETRY	include/ssv6200_reg.h	6790;"	d
+SET_MTX_WSID0_RETRY	smac/hal/ssv6006c/ssv6006C_reg.h	10902;"	d
+SET_MTX_WSID0_SUCC	include/ssv6200_reg.h	6788;"	d
+SET_MTX_WSID0_SUCC	smac/hal/ssv6006c/ssv6006C_reg.h	10900;"	d
+SET_MTX_WSID0_TOTAL	include/ssv6200_reg.h	6791;"	d
+SET_MTX_WSID0_TOTAL	smac/hal/ssv6006c/ssv6006C_reg.h	10903;"	d
+SET_MULTI_AMPDU_W_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10371;"	d
+SET_MUL_ANS0	include/ssv6200_reg.h	6183;"	d
+SET_MUL_ANS0	smac/hal/ssv6006c/ssv6006C_reg.h	10201;"	d
+SET_MUL_ANS1	include/ssv6200_reg.h	6184;"	d
+SET_MUL_ANS1	smac/hal/ssv6006c/ssv6006C_reg.h	10202;"	d
+SET_MUL_OP1	include/ssv6200_reg.h	6181;"	d
+SET_MUL_OP1	smac/hal/ssv6006c/ssv6006C_reg.h	10199;"	d
+SET_MUL_OP2	include/ssv6200_reg.h	6182;"	d
+SET_MUL_OP2	smac/hal/ssv6006c/ssv6006C_reg.h	10200;"	d
+SET_N10CFG_DEFAULT_IVB	smac/hal/ssv6006c/ssv6006C_reg.h	9398;"	d
+SET_N10_CORE_CURRENT_PC	smac/hal/ssv6006c/ssv6006C_reg.h	9337;"	d
+SET_N10_CORE_DEBUG_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	9340;"	d
+SET_N10_CORE_STANDBY_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	9339;"	d
+SET_N10_STANDBY	smac/hal/ssv6006c/ssv6006C_reg.h	9341;"	d
+SET_N10_STANDBY_REQ	smac/hal/ssv6006c/ssv6006C_reg.h	9338;"	d
+SET_N10_WAKEUP_OK	smac/hal/ssv6006c/ssv6006C_reg.h	9342;"	d
+SET_N10_WARM_RESET_N	smac/hal/ssv6006c/ssv6006C_reg.h	9384;"	d
+SET_NACK_FLAG_BUS	include/ssv6200_reg.h	8475;"	d
+SET_NAVCS_PHYCS_FALL_OFFSET_STEP	smac/hal/ssv6006c/ssv6006C_reg.h	10518;"	d
+SET_NEQ_MB_FLAG	include/ssv6200_reg.h	8531;"	d
+SET_NEQ_MB_ID_127_96	include/ssv6200_reg.h	8523;"	d
+SET_NEQ_MB_ID_31_0	include/ssv6200_reg.h	8520;"	d
+SET_NEQ_MB_ID_63_32	include/ssv6200_reg.h	8521;"	d
+SET_NEQ_MB_ID_95_64	include/ssv6200_reg.h	8522;"	d
+SET_NEQ_PKT_FLAG	include/ssv6200_reg.h	8530;"	d
+SET_NEQ_PKT_ID_127_96	include/ssv6200_reg.h	8527;"	d
+SET_NEQ_PKT_ID_31_0	include/ssv6200_reg.h	8524;"	d
+SET_NEQ_PKT_ID_63_32	include/ssv6200_reg.h	8525;"	d
+SET_NEQ_PKT_ID_95_64	include/ssv6200_reg.h	8526;"	d
+SET_NOHIT_RPASS_MD	include/ssv6200_reg.h	8441;"	d
+SET_NORMAL_ISO_ON1	smac/hal/ssv6006c/ssv6006C_reg.h	9419;"	d
+SET_NORMAL_ISO_ON2	smac/hal/ssv6006c/ssv6006C_reg.h	9420;"	d
+SET_NORMAL_ISO_ON3	smac/hal/ssv6006c/ssv6006C_reg.h	9421;"	d
+SET_NORMAL_PWR_ON1	smac/hal/ssv6006c/ssv6006C_reg.h	9413;"	d
+SET_NORMAL_PWR_ON2	smac/hal/ssv6006c/ssv6006C_reg.h	9414;"	d
+SET_NORMAL_PWR_ON3	smac/hal/ssv6006c/ssv6006C_reg.h	9415;"	d
+SET_NO_ALLOCATE_SEND_ERROR	include/ssv6200_reg.h	5603;"	d
+SET_NO_ALLOC_ERR	smac/hal/ssv6006c/ssv6006C_reg.h	10137;"	d
+SET_NO_PKT_BUF_REDUCTION	smac/hal/ssv6006c/ssv6006C_reg.h	10421;"	d
+SET_NO_REDUCE_PKT_PEERPS_AMPDUV1P2	smac/hal/ssv6006c/ssv6006C_reg.h	10424;"	d
+SET_NO_REDUCE_PKT_PEERPS_AMPDUV1P3	smac/hal/ssv6006c/ssv6006C_reg.h	10425;"	d
+SET_NO_REDUCE_PKT_PEERPS_MPDU	smac/hal/ssv6006c/ssv6006C_reg.h	10423;"	d
+SET_NO_REDUCE_TXALLFAIL_PKT	smac/hal/ssv6006c/ssv6006C_reg.h	10422;"	d
+SET_OP_MODE	include/ssv6200_reg.h	6728;"	d
+SET_OP_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	10824;"	d
+SET_OP_MODE1	smac/hal/ssv6006c/ssv6006C_reg.h	10849;"	d
+SET_OUT_1	include/ssv6200_reg.h	5778;"	d
+SET_OUT_1	smac/hal/ssv6006c/ssv6006C_reg.h	9768;"	d
+SET_OUT_2	include/ssv6200_reg.h	5779;"	d
+SET_OUT_2	smac/hal/ssv6006c/ssv6006C_reg.h	9769;"	d
+SET_OUT_QUEUE_FLUSH_ID	smac/hal/ssv6006c/ssv6006C_reg.h	15758;"	d
+SET_OUT_QUEUE_FLUSH_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	15759;"	d
+SET_OUT_QUEUE_FLUSH_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	15760;"	d
+SET_OVERRUN	smac/hal/ssv6006c/ssv6006C_reg.h	9802;"	d
+SET_OVERRUN_ERR	include/ssv6200_reg.h	5782;"	d
+SET_OVERRUN_ERR	smac/hal/ssv6006c/ssv6006C_reg.h	9773;"	d
+SET_PACKET_ERR	include/ssv6200_reg.h	7825;"	d
+SET_PAD11_IE	include/ssv6200_reg.h	5104;"	d
+SET_PAD11_OD	include/ssv6200_reg.h	5106;"	d
+SET_PAD11_SEL_I	include/ssv6200_reg.h	5105;"	d
+SET_PAD11_SEL_O	include/ssv6200_reg.h	5107;"	d
+SET_PAD15_DS	include/ssv6200_reg.h	5111;"	d
+SET_PAD15_IE	include/ssv6200_reg.h	5112;"	d
+SET_PAD15_OD	include/ssv6200_reg.h	5114;"	d
+SET_PAD15_OE	include/ssv6200_reg.h	5109;"	d
+SET_PAD15_PE	include/ssv6200_reg.h	5110;"	d
+SET_PAD15_SEL_I	include/ssv6200_reg.h	5113;"	d
+SET_PAD15_SEL_O	include/ssv6200_reg.h	5115;"	d
+SET_PAD16_DS	include/ssv6200_reg.h	5119;"	d
+SET_PAD16_IE	include/ssv6200_reg.h	5120;"	d
+SET_PAD16_OD	include/ssv6200_reg.h	5122;"	d
+SET_PAD16_OE	include/ssv6200_reg.h	5117;"	d
+SET_PAD16_PE	include/ssv6200_reg.h	5118;"	d
+SET_PAD16_SEL_I	include/ssv6200_reg.h	5121;"	d
+SET_PAD16_SEL_O	include/ssv6200_reg.h	5123;"	d
+SET_PAD17_DS	include/ssv6200_reg.h	5127;"	d
+SET_PAD17_IE	include/ssv6200_reg.h	5128;"	d
+SET_PAD17_OD	include/ssv6200_reg.h	5130;"	d
+SET_PAD17_OE	include/ssv6200_reg.h	5125;"	d
+SET_PAD17_PE	include/ssv6200_reg.h	5126;"	d
+SET_PAD17_SEL_I	include/ssv6200_reg.h	5129;"	d
+SET_PAD17_SEL_O	include/ssv6200_reg.h	5131;"	d
+SET_PAD18_DS	include/ssv6200_reg.h	5135;"	d
+SET_PAD18_IE	include/ssv6200_reg.h	5136;"	d
+SET_PAD18_OD	include/ssv6200_reg.h	5138;"	d
+SET_PAD18_OE	include/ssv6200_reg.h	5133;"	d
+SET_PAD18_PE	include/ssv6200_reg.h	5134;"	d
+SET_PAD18_SEL_I	include/ssv6200_reg.h	5137;"	d
+SET_PAD18_SEL_O	include/ssv6200_reg.h	5139;"	d
+SET_PAD19_DS	include/ssv6200_reg.h	5143;"	d
+SET_PAD19_IE	include/ssv6200_reg.h	5144;"	d
+SET_PAD19_OD	include/ssv6200_reg.h	5146;"	d
+SET_PAD19_OE	include/ssv6200_reg.h	5141;"	d
+SET_PAD19_PE	include/ssv6200_reg.h	5142;"	d
+SET_PAD19_SEL_I	include/ssv6200_reg.h	5145;"	d
+SET_PAD19_SEL_O	include/ssv6200_reg.h	5147;"	d
+SET_PAD20_DS	include/ssv6200_reg.h	5151;"	d
+SET_PAD20_IE	include/ssv6200_reg.h	5152;"	d
+SET_PAD20_OD	include/ssv6200_reg.h	5154;"	d
+SET_PAD20_OE	include/ssv6200_reg.h	5149;"	d
+SET_PAD20_PE	include/ssv6200_reg.h	5150;"	d
+SET_PAD20_SEL_I	include/ssv6200_reg.h	5153;"	d
+SET_PAD20_SEL_O	include/ssv6200_reg.h	5155;"	d
+SET_PAD21_DS	include/ssv6200_reg.h	5160;"	d
+SET_PAD21_IE	include/ssv6200_reg.h	5161;"	d
+SET_PAD21_OD	include/ssv6200_reg.h	5163;"	d
+SET_PAD21_OE	include/ssv6200_reg.h	5158;"	d
+SET_PAD21_PE	include/ssv6200_reg.h	5159;"	d
+SET_PAD21_SEL_I	include/ssv6200_reg.h	5162;"	d
+SET_PAD21_SEL_O	include/ssv6200_reg.h	5164;"	d
+SET_PAD22_DS	include/ssv6200_reg.h	5169;"	d
+SET_PAD22_IE	include/ssv6200_reg.h	5170;"	d
+SET_PAD22_OD	include/ssv6200_reg.h	5172;"	d
+SET_PAD22_OE	include/ssv6200_reg.h	5167;"	d
+SET_PAD22_PE	include/ssv6200_reg.h	5168;"	d
+SET_PAD22_SEL_I	include/ssv6200_reg.h	5171;"	d
+SET_PAD22_SEL_O	include/ssv6200_reg.h	5173;"	d
+SET_PAD22_SEL_OE	include/ssv6200_reg.h	5174;"	d
+SET_PAD231_DS	include/ssv6200_reg.h	5479;"	d
+SET_PAD231_IE	include/ssv6200_reg.h	5480;"	d
+SET_PAD231_OD	include/ssv6200_reg.h	5481;"	d
+SET_PAD231_OE	include/ssv6200_reg.h	5477;"	d
+SET_PAD231_PE	include/ssv6200_reg.h	5478;"	d
+SET_PAD24_DS	include/ssv6200_reg.h	5178;"	d
+SET_PAD24_IE	include/ssv6200_reg.h	5179;"	d
+SET_PAD24_OD	include/ssv6200_reg.h	5181;"	d
+SET_PAD24_OE	include/ssv6200_reg.h	5176;"	d
+SET_PAD24_PE	include/ssv6200_reg.h	5177;"	d
+SET_PAD24_SEL_I	include/ssv6200_reg.h	5180;"	d
+SET_PAD24_SEL_O	include/ssv6200_reg.h	5182;"	d
+SET_PAD25_DS	include/ssv6200_reg.h	5186;"	d
+SET_PAD25_IE	include/ssv6200_reg.h	5187;"	d
+SET_PAD25_OD	include/ssv6200_reg.h	5189;"	d
+SET_PAD25_OE	include/ssv6200_reg.h	5184;"	d
+SET_PAD25_PE	include/ssv6200_reg.h	5185;"	d
+SET_PAD25_SEL_I	include/ssv6200_reg.h	5188;"	d
+SET_PAD25_SEL_O	include/ssv6200_reg.h	5190;"	d
+SET_PAD25_SEL_OE	include/ssv6200_reg.h	5191;"	d
+SET_PAD27_DS	include/ssv6200_reg.h	5196;"	d
+SET_PAD27_IE	include/ssv6200_reg.h	5197;"	d
+SET_PAD27_OD	include/ssv6200_reg.h	5199;"	d
+SET_PAD27_OE	include/ssv6200_reg.h	5194;"	d
+SET_PAD27_PE	include/ssv6200_reg.h	5195;"	d
+SET_PAD27_SEL_I	include/ssv6200_reg.h	5198;"	d
+SET_PAD27_SEL_O	include/ssv6200_reg.h	5200;"	d
+SET_PAD28_DS	include/ssv6200_reg.h	5204;"	d
+SET_PAD28_IE	include/ssv6200_reg.h	5205;"	d
+SET_PAD28_OD	include/ssv6200_reg.h	5207;"	d
+SET_PAD28_OE	include/ssv6200_reg.h	5202;"	d
+SET_PAD28_PE	include/ssv6200_reg.h	5203;"	d
+SET_PAD28_SEL_I	include/ssv6200_reg.h	5206;"	d
+SET_PAD28_SEL_O	include/ssv6200_reg.h	5208;"	d
+SET_PAD28_SEL_OE	include/ssv6200_reg.h	5209;"	d
+SET_PAD29_DS	include/ssv6200_reg.h	5213;"	d
+SET_PAD29_IE	include/ssv6200_reg.h	5214;"	d
+SET_PAD29_OD	include/ssv6200_reg.h	5216;"	d
+SET_PAD29_OE	include/ssv6200_reg.h	5211;"	d
+SET_PAD29_PE	include/ssv6200_reg.h	5212;"	d
+SET_PAD29_SEL_I	include/ssv6200_reg.h	5215;"	d
+SET_PAD29_SEL_O	include/ssv6200_reg.h	5217;"	d
+SET_PAD30_DS	include/ssv6200_reg.h	5221;"	d
+SET_PAD30_IE	include/ssv6200_reg.h	5222;"	d
+SET_PAD30_OD	include/ssv6200_reg.h	5224;"	d
+SET_PAD30_OE	include/ssv6200_reg.h	5219;"	d
+SET_PAD30_PE	include/ssv6200_reg.h	5220;"	d
+SET_PAD30_SEL_I	include/ssv6200_reg.h	5223;"	d
+SET_PAD30_SEL_O	include/ssv6200_reg.h	5225;"	d
+SET_PAD31_DS	include/ssv6200_reg.h	5229;"	d
+SET_PAD31_IE	include/ssv6200_reg.h	5230;"	d
+SET_PAD31_OD	include/ssv6200_reg.h	5232;"	d
+SET_PAD31_OE	include/ssv6200_reg.h	5227;"	d
+SET_PAD31_PE	include/ssv6200_reg.h	5228;"	d
+SET_PAD31_SEL_I	include/ssv6200_reg.h	5231;"	d
+SET_PAD31_SEL_O	include/ssv6200_reg.h	5233;"	d
+SET_PAD32_DS	include/ssv6200_reg.h	5237;"	d
+SET_PAD32_IE	include/ssv6200_reg.h	5238;"	d
+SET_PAD32_OD	include/ssv6200_reg.h	5240;"	d
+SET_PAD32_OE	include/ssv6200_reg.h	5235;"	d
+SET_PAD32_PE	include/ssv6200_reg.h	5236;"	d
+SET_PAD32_SEL_I	include/ssv6200_reg.h	5239;"	d
+SET_PAD32_SEL_O	include/ssv6200_reg.h	5241;"	d
+SET_PAD33_DS	include/ssv6200_reg.h	5245;"	d
+SET_PAD33_IE	include/ssv6200_reg.h	5246;"	d
+SET_PAD33_OD	include/ssv6200_reg.h	5248;"	d
+SET_PAD33_OE	include/ssv6200_reg.h	5243;"	d
+SET_PAD33_PE	include/ssv6200_reg.h	5244;"	d
+SET_PAD33_SEL_I	include/ssv6200_reg.h	5247;"	d
+SET_PAD33_SEL_O	include/ssv6200_reg.h	5249;"	d
+SET_PAD34_DS	include/ssv6200_reg.h	5253;"	d
+SET_PAD34_IE	include/ssv6200_reg.h	5254;"	d
+SET_PAD34_OD	include/ssv6200_reg.h	5256;"	d
+SET_PAD34_OE	include/ssv6200_reg.h	5251;"	d
+SET_PAD34_PE	include/ssv6200_reg.h	5252;"	d
+SET_PAD34_SEL_I	include/ssv6200_reg.h	5255;"	d
+SET_PAD34_SEL_O	include/ssv6200_reg.h	5257;"	d
+SET_PAD42_DS	include/ssv6200_reg.h	5261;"	d
+SET_PAD42_IE	include/ssv6200_reg.h	5262;"	d
+SET_PAD42_OD	include/ssv6200_reg.h	5264;"	d
+SET_PAD42_OE	include/ssv6200_reg.h	5259;"	d
+SET_PAD42_PE	include/ssv6200_reg.h	5260;"	d
+SET_PAD42_SEL_I	include/ssv6200_reg.h	5263;"	d
+SET_PAD42_SEL_O	include/ssv6200_reg.h	5265;"	d
+SET_PAD43_DS	include/ssv6200_reg.h	5269;"	d
+SET_PAD43_IE	include/ssv6200_reg.h	5270;"	d
+SET_PAD43_OD	include/ssv6200_reg.h	5272;"	d
+SET_PAD43_OE	include/ssv6200_reg.h	5267;"	d
+SET_PAD43_PE	include/ssv6200_reg.h	5268;"	d
+SET_PAD43_SEL_I	include/ssv6200_reg.h	5271;"	d
+SET_PAD43_SEL_O	include/ssv6200_reg.h	5273;"	d
+SET_PAD44_DS	include/ssv6200_reg.h	5277;"	d
+SET_PAD44_IE	include/ssv6200_reg.h	5278;"	d
+SET_PAD44_OD	include/ssv6200_reg.h	5280;"	d
+SET_PAD44_OE	include/ssv6200_reg.h	5275;"	d
+SET_PAD44_PE	include/ssv6200_reg.h	5276;"	d
+SET_PAD44_SEL_I	include/ssv6200_reg.h	5279;"	d
+SET_PAD44_SEL_O	include/ssv6200_reg.h	5281;"	d
+SET_PAD45_DS	include/ssv6200_reg.h	5285;"	d
+SET_PAD45_IE	include/ssv6200_reg.h	5286;"	d
+SET_PAD45_OD	include/ssv6200_reg.h	5288;"	d
+SET_PAD45_OE	include/ssv6200_reg.h	5283;"	d
+SET_PAD45_PE	include/ssv6200_reg.h	5284;"	d
+SET_PAD45_SEL_I	include/ssv6200_reg.h	5287;"	d
+SET_PAD45_SEL_O	include/ssv6200_reg.h	5289;"	d
+SET_PAD46_DS	include/ssv6200_reg.h	5293;"	d
+SET_PAD46_IE	include/ssv6200_reg.h	5294;"	d
+SET_PAD46_OD	include/ssv6200_reg.h	5296;"	d
+SET_PAD46_OE	include/ssv6200_reg.h	5291;"	d
+SET_PAD46_PE	include/ssv6200_reg.h	5292;"	d
+SET_PAD46_SEL_I	include/ssv6200_reg.h	5295;"	d
+SET_PAD46_SEL_O	include/ssv6200_reg.h	5297;"	d
+SET_PAD47_DS	include/ssv6200_reg.h	5301;"	d
+SET_PAD47_OD	include/ssv6200_reg.h	5303;"	d
+SET_PAD47_OE	include/ssv6200_reg.h	5299;"	d
+SET_PAD47_PE	include/ssv6200_reg.h	5300;"	d
+SET_PAD47_SEL_I	include/ssv6200_reg.h	5302;"	d
+SET_PAD47_SEL_O	include/ssv6200_reg.h	5304;"	d
+SET_PAD47_SEL_OE	include/ssv6200_reg.h	5305;"	d
+SET_PAD48_DS	include/ssv6200_reg.h	5309;"	d
+SET_PAD48_IE	include/ssv6200_reg.h	5310;"	d
+SET_PAD48_OD	include/ssv6200_reg.h	5312;"	d
+SET_PAD48_OE	include/ssv6200_reg.h	5307;"	d
+SET_PAD48_PE	include/ssv6200_reg.h	5308;"	d
+SET_PAD48_PE_SEL	include/ssv6200_reg.h	5313;"	d
+SET_PAD48_SEL_I	include/ssv6200_reg.h	5311;"	d
+SET_PAD48_SEL_O	include/ssv6200_reg.h	5314;"	d
+SET_PAD48_SEL_OE	include/ssv6200_reg.h	5315;"	d
+SET_PAD49_DS	include/ssv6200_reg.h	5319;"	d
+SET_PAD49_IE	include/ssv6200_reg.h	5320;"	d
+SET_PAD49_OD	include/ssv6200_reg.h	5322;"	d
+SET_PAD49_OE	include/ssv6200_reg.h	5317;"	d
+SET_PAD49_PE	include/ssv6200_reg.h	5318;"	d
+SET_PAD49_SEL_I	include/ssv6200_reg.h	5321;"	d
+SET_PAD49_SEL_O	include/ssv6200_reg.h	5323;"	d
+SET_PAD49_SEL_OE	include/ssv6200_reg.h	5324;"	d
+SET_PAD50_DS	include/ssv6200_reg.h	5328;"	d
+SET_PAD50_IE	include/ssv6200_reg.h	5329;"	d
+SET_PAD50_OD	include/ssv6200_reg.h	5331;"	d
+SET_PAD50_OE	include/ssv6200_reg.h	5326;"	d
+SET_PAD50_PE	include/ssv6200_reg.h	5327;"	d
+SET_PAD50_SEL_I	include/ssv6200_reg.h	5330;"	d
+SET_PAD50_SEL_O	include/ssv6200_reg.h	5332;"	d
+SET_PAD50_SEL_OE	include/ssv6200_reg.h	5333;"	d
+SET_PAD51_DS	include/ssv6200_reg.h	5337;"	d
+SET_PAD51_IE	include/ssv6200_reg.h	5338;"	d
+SET_PAD51_OD	include/ssv6200_reg.h	5340;"	d
+SET_PAD51_OE	include/ssv6200_reg.h	5335;"	d
+SET_PAD51_PE	include/ssv6200_reg.h	5336;"	d
+SET_PAD51_SEL_I	include/ssv6200_reg.h	5339;"	d
+SET_PAD51_SEL_O	include/ssv6200_reg.h	5341;"	d
+SET_PAD51_SEL_OE	include/ssv6200_reg.h	5342;"	d
+SET_PAD52_DS	include/ssv6200_reg.h	5346;"	d
+SET_PAD52_OD	include/ssv6200_reg.h	5348;"	d
+SET_PAD52_OE	include/ssv6200_reg.h	5344;"	d
+SET_PAD52_PE	include/ssv6200_reg.h	5345;"	d
+SET_PAD52_SEL_I	include/ssv6200_reg.h	5347;"	d
+SET_PAD52_SEL_O	include/ssv6200_reg.h	5349;"	d
+SET_PAD52_SEL_OE	include/ssv6200_reg.h	5350;"	d
+SET_PAD53_DS	include/ssv6200_reg.h	5354;"	d
+SET_PAD53_IE	include/ssv6200_reg.h	5355;"	d
+SET_PAD53_OD	include/ssv6200_reg.h	5357;"	d
+SET_PAD53_OE	include/ssv6200_reg.h	5352;"	d
+SET_PAD53_PE	include/ssv6200_reg.h	5353;"	d
+SET_PAD53_SEL_I	include/ssv6200_reg.h	5356;"	d
+SET_PAD53_SEL_O	include/ssv6200_reg.h	5358;"	d
+SET_PAD54_DS	include/ssv6200_reg.h	5362;"	d
+SET_PAD54_OD	include/ssv6200_reg.h	5363;"	d
+SET_PAD54_OE	include/ssv6200_reg.h	5360;"	d
+SET_PAD54_PE	include/ssv6200_reg.h	5361;"	d
+SET_PAD54_SEL_O	include/ssv6200_reg.h	5364;"	d
+SET_PAD56_DS	include/ssv6200_reg.h	5367;"	d
+SET_PAD56_OD	include/ssv6200_reg.h	5369;"	d
+SET_PAD56_PE	include/ssv6200_reg.h	5366;"	d
+SET_PAD56_SEL_I	include/ssv6200_reg.h	5368;"	d
+SET_PAD57_DS	include/ssv6200_reg.h	5373;"	d
+SET_PAD57_IE	include/ssv6200_reg.h	5374;"	d
+SET_PAD57_OD	include/ssv6200_reg.h	5376;"	d
+SET_PAD57_OE	include/ssv6200_reg.h	5371;"	d
+SET_PAD57_PE	include/ssv6200_reg.h	5372;"	d
+SET_PAD57_SEL_I	include/ssv6200_reg.h	5375;"	d
+SET_PAD57_SEL_O	include/ssv6200_reg.h	5377;"	d
+SET_PAD57_SEL_OE	include/ssv6200_reg.h	5378;"	d
+SET_PAD58_DS	include/ssv6200_reg.h	5382;"	d
+SET_PAD58_IE	include/ssv6200_reg.h	5383;"	d
+SET_PAD58_OD	include/ssv6200_reg.h	5385;"	d
+SET_PAD58_OE	include/ssv6200_reg.h	5380;"	d
+SET_PAD58_PE	include/ssv6200_reg.h	5381;"	d
+SET_PAD58_SEL_I	include/ssv6200_reg.h	5384;"	d
+SET_PAD58_SEL_O	include/ssv6200_reg.h	5386;"	d
+SET_PAD59_DS	include/ssv6200_reg.h	5390;"	d
+SET_PAD59_IE	include/ssv6200_reg.h	5391;"	d
+SET_PAD59_OD	include/ssv6200_reg.h	5393;"	d
+SET_PAD59_OE	include/ssv6200_reg.h	5388;"	d
+SET_PAD59_PE	include/ssv6200_reg.h	5389;"	d
+SET_PAD59_SEL_I	include/ssv6200_reg.h	5392;"	d
+SET_PAD59_SEL_O	include/ssv6200_reg.h	5394;"	d
+SET_PAD60_DS	include/ssv6200_reg.h	5398;"	d
+SET_PAD60_IE	include/ssv6200_reg.h	5399;"	d
+SET_PAD60_OD	include/ssv6200_reg.h	5401;"	d
+SET_PAD60_OE	include/ssv6200_reg.h	5396;"	d
+SET_PAD60_PE	include/ssv6200_reg.h	5397;"	d
+SET_PAD60_SEL_I	include/ssv6200_reg.h	5400;"	d
+SET_PAD60_SEL_O	include/ssv6200_reg.h	5402;"	d
+SET_PAD61_DS	include/ssv6200_reg.h	5406;"	d
+SET_PAD61_IE	include/ssv6200_reg.h	5407;"	d
+SET_PAD61_OD	include/ssv6200_reg.h	5409;"	d
+SET_PAD61_OE	include/ssv6200_reg.h	5404;"	d
+SET_PAD61_PE	include/ssv6200_reg.h	5405;"	d
+SET_PAD61_SEL_I	include/ssv6200_reg.h	5408;"	d
+SET_PAD61_SEL_O	include/ssv6200_reg.h	5410;"	d
+SET_PAD62_DS	include/ssv6200_reg.h	5414;"	d
+SET_PAD62_IE	include/ssv6200_reg.h	5415;"	d
+SET_PAD62_OD	include/ssv6200_reg.h	5417;"	d
+SET_PAD62_OE	include/ssv6200_reg.h	5412;"	d
+SET_PAD62_PE	include/ssv6200_reg.h	5413;"	d
+SET_PAD62_SEL_I	include/ssv6200_reg.h	5416;"	d
+SET_PAD62_SEL_O	include/ssv6200_reg.h	5418;"	d
+SET_PAD64_DS	include/ssv6200_reg.h	5422;"	d
+SET_PAD64_IE	include/ssv6200_reg.h	5423;"	d
+SET_PAD64_OD	include/ssv6200_reg.h	5425;"	d
+SET_PAD64_OE	include/ssv6200_reg.h	5420;"	d
+SET_PAD64_PE	include/ssv6200_reg.h	5421;"	d
+SET_PAD64_SEL_I	include/ssv6200_reg.h	5424;"	d
+SET_PAD64_SEL_O	include/ssv6200_reg.h	5426;"	d
+SET_PAD64_SEL_OE	include/ssv6200_reg.h	5427;"	d
+SET_PAD65_DS	include/ssv6200_reg.h	5431;"	d
+SET_PAD65_IE	include/ssv6200_reg.h	5432;"	d
+SET_PAD65_OD	include/ssv6200_reg.h	5434;"	d
+SET_PAD65_OE	include/ssv6200_reg.h	5429;"	d
+SET_PAD65_PE	include/ssv6200_reg.h	5430;"	d
+SET_PAD65_SEL_I	include/ssv6200_reg.h	5433;"	d
+SET_PAD65_SEL_O	include/ssv6200_reg.h	5435;"	d
+SET_PAD66_DS	include/ssv6200_reg.h	5439;"	d
+SET_PAD66_IE	include/ssv6200_reg.h	5440;"	d
+SET_PAD66_OD	include/ssv6200_reg.h	5442;"	d
+SET_PAD66_OE	include/ssv6200_reg.h	5437;"	d
+SET_PAD66_PE	include/ssv6200_reg.h	5438;"	d
+SET_PAD66_SEL_I	include/ssv6200_reg.h	5441;"	d
+SET_PAD66_SEL_O	include/ssv6200_reg.h	5443;"	d
+SET_PAD67_DS	include/ssv6200_reg.h	5454;"	d
+SET_PAD67_IE	include/ssv6200_reg.h	5455;"	d
+SET_PAD67_OD	include/ssv6200_reg.h	5457;"	d
+SET_PAD67_OE	include/ssv6200_reg.h	5452;"	d
+SET_PAD67_PE	include/ssv6200_reg.h	5453;"	d
+SET_PAD67_SEL_I	include/ssv6200_reg.h	5456;"	d
+SET_PAD67_SEL_O	include/ssv6200_reg.h	5458;"	d
+SET_PAD68_DS	include/ssv6200_reg.h	5447;"	d
+SET_PAD68_IE	include/ssv6200_reg.h	5448;"	d
+SET_PAD68_OD	include/ssv6200_reg.h	5449;"	d
+SET_PAD68_OE	include/ssv6200_reg.h	5445;"	d
+SET_PAD68_PE	include/ssv6200_reg.h	5446;"	d
+SET_PAD68_SEL_O	include/ssv6200_reg.h	5450;"	d
+SET_PAD69_DS	include/ssv6200_reg.h	5462;"	d
+SET_PAD69_IE	include/ssv6200_reg.h	5463;"	d
+SET_PAD69_OD	include/ssv6200_reg.h	5465;"	d
+SET_PAD69_OE	include/ssv6200_reg.h	5460;"	d
+SET_PAD69_PE	include/ssv6200_reg.h	5461;"	d
+SET_PAD69_SEL_I	include/ssv6200_reg.h	5464;"	d
+SET_PAD69_SEL_O	include/ssv6200_reg.h	5466;"	d
+SET_PAD6_IE	include/ssv6200_reg.h	5077;"	d
+SET_PAD6_OD	include/ssv6200_reg.h	5079;"	d
+SET_PAD6_SEL_I	include/ssv6200_reg.h	5078;"	d
+SET_PAD6_SEL_O	include/ssv6200_reg.h	5080;"	d
+SET_PAD70_DS	include/ssv6200_reg.h	5471;"	d
+SET_PAD70_IE	include/ssv6200_reg.h	5472;"	d
+SET_PAD70_OD	include/ssv6200_reg.h	5474;"	d
+SET_PAD70_OE	include/ssv6200_reg.h	5469;"	d
+SET_PAD70_PE	include/ssv6200_reg.h	5470;"	d
+SET_PAD70_SEL_I	include/ssv6200_reg.h	5473;"	d
+SET_PAD70_SEL_O	include/ssv6200_reg.h	5475;"	d
+SET_PAD7_IE	include/ssv6200_reg.h	5084;"	d
+SET_PAD7_OD	include/ssv6200_reg.h	5086;"	d
+SET_PAD7_SEL_I	include/ssv6200_reg.h	5085;"	d
+SET_PAD7_SEL_O	include/ssv6200_reg.h	5087;"	d
+SET_PAD8_IE	include/ssv6200_reg.h	5091;"	d
+SET_PAD8_OD	include/ssv6200_reg.h	5093;"	d
+SET_PAD8_SEL_I	include/ssv6200_reg.h	5092;"	d
+SET_PAD9_IE	include/ssv6200_reg.h	5097;"	d
+SET_PAD9_OD	include/ssv6200_reg.h	5099;"	d
+SET_PAD9_SEL_I	include/ssv6200_reg.h	5098;"	d
+SET_PAD9_SEL_O	include/ssv6200_reg.h	5100;"	d
+SET_PAIR_SCRT	include/ssv6200_reg.h	6743;"	d
+SET_PAIR_SCRT	smac/hal/ssv6006c/ssv6006C_reg.h	10840;"	d
+SET_PARALLEL_DR	include/ssv6200_reg.h	4977;"	d
+SET_PARA_ALC_RLS	include/ssv6200_reg.h	8477;"	d
+SET_PARITY	smac/hal/ssv6006c/ssv6006C_reg.h	9805;"	d
+SET_PARITY_EN	include/ssv6200_reg.h	5771;"	d
+SET_PARITY_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9761;"	d
+SET_PARITY_ERR	include/ssv6200_reg.h	5783;"	d
+SET_PARITY_ERR	smac/hal/ssv6006c/ssv6006C_reg.h	9774;"	d
+SET_PATCH00_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	9432;"	d
+SET_PATCH00_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	9433;"	d
+SET_PATCH00_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9431;"	d
+SET_PATCH01_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	9435;"	d
+SET_PATCH01_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	9436;"	d
+SET_PATCH01_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9434;"	d
+SET_PATCH02_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	10050;"	d
+SET_PATCH02_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	10051;"	d
+SET_PATCH02_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10049;"	d
+SET_PATCH03_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	10053;"	d
+SET_PATCH03_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	10054;"	d
+SET_PATCH03_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10052;"	d
+SET_PATCH04_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	10056;"	d
+SET_PATCH04_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	10057;"	d
+SET_PATCH04_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10055;"	d
+SET_PATCH05_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	10059;"	d
+SET_PATCH05_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	10060;"	d
+SET_PATCH05_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10058;"	d
+SET_PATCH06_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	10062;"	d
+SET_PATCH06_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	10063;"	d
+SET_PATCH06_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10061;"	d
+SET_PATCH07_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	10065;"	d
+SET_PATCH07_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	10066;"	d
+SET_PATCH07_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10064;"	d
+SET_PATCH08_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	10068;"	d
+SET_PATCH08_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	10069;"	d
+SET_PATCH08_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10067;"	d
+SET_PATCH09_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	10071;"	d
+SET_PATCH09_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	10072;"	d
+SET_PATCH09_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10070;"	d
+SET_PATCH10_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	10074;"	d
+SET_PATCH10_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	10075;"	d
+SET_PATCH10_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10073;"	d
+SET_PATCH11_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	10077;"	d
+SET_PATCH11_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	10078;"	d
+SET_PATCH11_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10076;"	d
+SET_PATCH12_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	10080;"	d
+SET_PATCH12_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	10081;"	d
+SET_PATCH12_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10079;"	d
+SET_PATCH13_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	10083;"	d
+SET_PATCH13_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	10084;"	d
+SET_PATCH13_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10082;"	d
+SET_PATCH14_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	10086;"	d
+SET_PATCH14_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	10087;"	d
+SET_PATCH14_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10085;"	d
+SET_PATCH15_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	10089;"	d
+SET_PATCH15_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	10090;"	d
+SET_PATCH15_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10088;"	d
+SET_PBUS_SWP	include/ssv6200_reg.h	6049;"	d
+SET_PB_OFFSET	include/ssv6200_reg.h	6731;"	d
+SET_PB_OFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	10827;"	d
+SET_PEERPS_REJECT_ENABLE	smac/hal/ssv6006c/ssv6006C_reg.h	10176;"	d
+SET_PEER_HT_MODE0	include/ssv6200_reg.h	6565;"	d
+SET_PEER_HT_MODE0	smac/hal/ssv6006c/ssv6006C_reg.h	10708;"	d
+SET_PEER_HT_MODE1	include/ssv6200_reg.h	6587;"	d
+SET_PEER_HT_MODE1	smac/hal/ssv6006c/ssv6006C_reg.h	10730;"	d
+SET_PEER_HT_MODE2	smac/hal/ssv6006c/ssv6006C_reg.h	10963;"	d
+SET_PEER_HT_MODE3	smac/hal/ssv6006c/ssv6006C_reg.h	10985;"	d
+SET_PEER_HT_MODE4	smac/hal/ssv6006c/ssv6006C_reg.h	11007;"	d
+SET_PEER_HT_MODE5	smac/hal/ssv6006c/ssv6006C_reg.h	11029;"	d
+SET_PEER_HT_MODE6	smac/hal/ssv6006c/ssv6006C_reg.h	11051;"	d
+SET_PEER_HT_MODE7	smac/hal/ssv6006c/ssv6006C_reg.h	11073;"	d
+SET_PEER_MAC0_31_0	include/ssv6200_reg.h	6566;"	d
+SET_PEER_MAC0_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	10709;"	d
+SET_PEER_MAC0_47_32	include/ssv6200_reg.h	6567;"	d
+SET_PEER_MAC0_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	10710;"	d
+SET_PEER_MAC1_31_0	include/ssv6200_reg.h	6588;"	d
+SET_PEER_MAC1_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	10731;"	d
+SET_PEER_MAC1_47_32	include/ssv6200_reg.h	6589;"	d
+SET_PEER_MAC1_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	10732;"	d
+SET_PEER_MAC2_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	10964;"	d
+SET_PEER_MAC2_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	10965;"	d
+SET_PEER_MAC3_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	10986;"	d
+SET_PEER_MAC3_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	10987;"	d
+SET_PEER_MAC4_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	11008;"	d
+SET_PEER_MAC4_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	11009;"	d
+SET_PEER_MAC5_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	11030;"	d
+SET_PEER_MAC5_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	11031;"	d
+SET_PEER_MAC6_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	11052;"	d
+SET_PEER_MAC6_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	11053;"	d
+SET_PEER_MAC7_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	11074;"	d
+SET_PEER_MAC7_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	11075;"	d
+SET_PEER_OP_MODE0	include/ssv6200_reg.h	6564;"	d
+SET_PEER_OP_MODE0	smac/hal/ssv6006c/ssv6006C_reg.h	10707;"	d
+SET_PEER_OP_MODE1	include/ssv6200_reg.h	6586;"	d
+SET_PEER_OP_MODE1	smac/hal/ssv6006c/ssv6006C_reg.h	10729;"	d
+SET_PEER_OP_MODE2	smac/hal/ssv6006c/ssv6006C_reg.h	10962;"	d
+SET_PEER_OP_MODE3	smac/hal/ssv6006c/ssv6006C_reg.h	10984;"	d
+SET_PEER_OP_MODE4	smac/hal/ssv6006c/ssv6006C_reg.h	11006;"	d
+SET_PEER_OP_MODE5	smac/hal/ssv6006c/ssv6006C_reg.h	11028;"	d
+SET_PEER_OP_MODE6	smac/hal/ssv6006c/ssv6006C_reg.h	11050;"	d
+SET_PEER_OP_MODE7	smac/hal/ssv6006c/ssv6006C_reg.h	11072;"	d
+SET_PEER_QOS_EN0	include/ssv6200_reg.h	6563;"	d
+SET_PEER_QOS_EN0	smac/hal/ssv6006c/ssv6006C_reg.h	10706;"	d
+SET_PEER_QOS_EN1	include/ssv6200_reg.h	6585;"	d
+SET_PEER_QOS_EN1	smac/hal/ssv6006c/ssv6006C_reg.h	10728;"	d
+SET_PEER_QOS_EN2	smac/hal/ssv6006c/ssv6006C_reg.h	10961;"	d
+SET_PEER_QOS_EN3	smac/hal/ssv6006c/ssv6006C_reg.h	10983;"	d
+SET_PEER_QOS_EN4	smac/hal/ssv6006c/ssv6006C_reg.h	11005;"	d
+SET_PEER_QOS_EN5	smac/hal/ssv6006c/ssv6006C_reg.h	11027;"	d
+SET_PEER_QOS_EN6	smac/hal/ssv6006c/ssv6006C_reg.h	11049;"	d
+SET_PEER_QOS_EN7	smac/hal/ssv6006c/ssv6006C_reg.h	11071;"	d
+SET_PERI_GPI_1_0	include/ssv6200_reg.h	5891;"	d
+SET_PERI_GPI_2	include/ssv6200_reg.h	5889;"	d
+SET_PERI_GPI_SD_1_0	include/ssv6200_reg.h	5960;"	d
+SET_PERI_GPI_SD_2	include/ssv6200_reg.h	5958;"	d
+SET_PERI_MAC_ALL_RESET	include/ssv6200_reg.h	5584;"	d
+SET_PERI_MAC_ALL_RESET	smac/hal/ssv6006c/ssv6006C_reg.h	9622;"	d
+SET_PERI_RTC	include/ssv6200_reg.h	5886;"	d
+SET_PERI_RTC_SD	include/ssv6200_reg.h	5955;"	d
+SET_PG_TAG_127_96	smac/hal/ssv6006c/ssv6006C_reg.h	15968;"	d
+SET_PG_TAG_159_128	smac/hal/ssv6006c/ssv6006C_reg.h	15969;"	d
+SET_PG_TAG_191_160	smac/hal/ssv6006c/ssv6006C_reg.h	15970;"	d
+SET_PG_TAG_223_192	smac/hal/ssv6006c/ssv6006C_reg.h	15971;"	d
+SET_PG_TAG_255_224	smac/hal/ssv6006c/ssv6006C_reg.h	15972;"	d
+SET_PG_TAG_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	15965;"	d
+SET_PG_TAG_63_32	smac/hal/ssv6006c/ssv6006C_reg.h	15966;"	d
+SET_PG_TAG_95_64	smac/hal/ssv6006c/ssv6006C_reg.h	15967;"	d
+SET_PHYTXSTART_NCYCLE	smac/hal/ssv6006c/ssv6006C_reg.h	10520;"	d
+SET_PHY_INFO	smac/dev_tbl.h	165;"	d
+SET_PHY_IQ_LOG_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9328;"	d
+SET_PHY_L_LENGTH	smac/dev_tbl.h	171;"	d
+SET_PHY_MODE	include/ssv6200_reg.h	6191;"	d
+SET_PHY_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	10209;"	d
+SET_PIN_40_OR_56_ID	include/ssv6200_reg.h	5482;"	d
+SET_PKTBUF_FULL	include/ssv6200_reg.h	8501;"	d
+SET_PKTBUF_FULL	smac/hal/ssv6006c/ssv6006C_reg.h	15963;"	d
+SET_PKT_IDTBL_127_96	include/ssv6200_reg.h	8515;"	d
+SET_PKT_IDTBL_31_0	include/ssv6200_reg.h	8512;"	d
+SET_PKT_IDTBL_63_32	include/ssv6200_reg.h	8513;"	d
+SET_PKT_IDTBL_95_64	include/ssv6200_reg.h	8514;"	d
+SET_PKT_REQ_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	15964;"	d
+SET_PLF_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	9286;"	d
+SET_PMUINT_WAKE_SEL	include/ssv6200_reg.h	5504;"	d
+SET_PMU_ENTER_SLEEP_MODE	include/ssv6200_reg.h	6087;"	d
+SET_PMU_WAKE_TRIG_EVENT	include/ssv6200_reg.h	6085;"	d
+SET_POSTMASK_TYPHOST_INT_MAP	smac/hal/ssv6006c/ssv6006C_reg.h	9949;"	d
+SET_POSTMASK_TYPHOST_INT_MAP_02	smac/hal/ssv6006c/ssv6006C_reg.h	9940;"	d
+SET_POSTMASK_TYPHOST_INT_MAP_15	smac/hal/ssv6006c/ssv6006C_reg.h	9943;"	d
+SET_POSTMASK_TYPHOST_INT_MAP_31	smac/hal/ssv6006c/ssv6006C_reg.h	9946;"	d
+SET_POSTMASK_TYPMCU_INT_MAP	smac/hal/ssv6006c/ssv6006C_reg.h	9962;"	d
+SET_POSTMASK_TYPMCU_INT_MAP_02	smac/hal/ssv6006c/ssv6006C_reg.h	9953;"	d
+SET_POSTMASK_TYPMCU_INT_MAP_15	smac/hal/ssv6006c/ssv6006C_reg.h	9956;"	d
+SET_POSTMASK_TYPMCU_INT_MAP_31	smac/hal/ssv6006c/ssv6006C_reg.h	9959;"	d
+SET_PREDE_BT_TX	smac/hal/ssv6006c/ssv6006C_reg.h	10883;"	d
+SET_PREFETCH_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9884;"	d
+SET_PRESCALER_US	smac/hal/ssv6006c/ssv6006C_reg.h	9427;"	d
+SET_PRESCALER_USTIMER	include/ssv6200_reg.h	5013;"	d
+SET_PRI_HW_PKTID	include/ssv6200_reg.h	7187;"	d
+SET_PRI_HW_PKTID	smac/hal/ssv6006c/ssv6006C_reg.h	15640;"	d
+SET_PRO_VER	include/ssv6200_reg.h	6120;"	d
+SET_PRO_VER	smac/hal/ssv6006c/ssv6006C_reg.h	10099;"	d
+SET_PSEUDO	include/ssv6200_reg.h	6174;"	d
+SET_PSEUDO	smac/hal/ssv6006c/ssv6006C_reg.h	10192;"	d
+SET_PS_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10370;"	d
+SET_PWM_ALWAYSON_0	smac/hal/ssv6006c/ssv6006C_reg.h	9495;"	d
+SET_PWM_ALWAYSON_1	smac/hal/ssv6006c/ssv6006C_reg.h	9502;"	d
+SET_PWM_ALWAYSON_2	smac/hal/ssv6006c/ssv6006C_reg.h	9509;"	d
+SET_PWM_ALWAYSON_3	smac/hal/ssv6006c/ssv6006C_reg.h	9516;"	d
+SET_PWM_ALWAYSON_4	smac/hal/ssv6006c/ssv6006C_reg.h	9523;"	d
+SET_PWM_ALWAYSON_A	include/ssv6200_reg.h	5002;"	d
+SET_PWM_ALWAYSON_B	include/ssv6200_reg.h	5008;"	d
+SET_PWM_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9322;"	d
+SET_PWM_ENABLE_0	smac/hal/ssv6006c/ssv6006C_reg.h	9497;"	d
+SET_PWM_ENABLE_1	smac/hal/ssv6006c/ssv6006C_reg.h	9504;"	d
+SET_PWM_ENABLE_2	smac/hal/ssv6006c/ssv6006C_reg.h	9511;"	d
+SET_PWM_ENABLE_3	smac/hal/ssv6006c/ssv6006C_reg.h	9518;"	d
+SET_PWM_ENABLE_4	smac/hal/ssv6006c/ssv6006C_reg.h	9525;"	d
+SET_PWM_ENABLE_A	include/ssv6200_reg.h	5004;"	d
+SET_PWM_ENABLE_B	include/ssv6200_reg.h	5010;"	d
+SET_PWM_INI_VALUE_N_A	include/ssv6200_reg.h	5000;"	d
+SET_PWM_INI_VALUE_N_B	include/ssv6200_reg.h	5006;"	d
+SET_PWM_INI_VALUE_PERIOD_0	smac/hal/ssv6006c/ssv6006C_reg.h	9498;"	d
+SET_PWM_INI_VALUE_PERIOD_1	smac/hal/ssv6006c/ssv6006C_reg.h	9505;"	d
+SET_PWM_INI_VALUE_PERIOD_2	smac/hal/ssv6006c/ssv6006C_reg.h	9512;"	d
+SET_PWM_INI_VALUE_PERIOD_3	smac/hal/ssv6006c/ssv6006C_reg.h	9519;"	d
+SET_PWM_INI_VALUE_PERIOD_4	smac/hal/ssv6006c/ssv6006C_reg.h	9526;"	d
+SET_PWM_INI_VALUE_P_0	smac/hal/ssv6006c/ssv6006C_reg.h	9499;"	d
+SET_PWM_INI_VALUE_P_1	smac/hal/ssv6006c/ssv6006C_reg.h	9506;"	d
+SET_PWM_INI_VALUE_P_2	smac/hal/ssv6006c/ssv6006C_reg.h	9513;"	d
+SET_PWM_INI_VALUE_P_3	smac/hal/ssv6006c/ssv6006C_reg.h	9520;"	d
+SET_PWM_INI_VALUE_P_4	smac/hal/ssv6006c/ssv6006C_reg.h	9527;"	d
+SET_PWM_INI_VALUE_P_A	include/ssv6200_reg.h	4999;"	d
+SET_PWM_INI_VALUE_P_B	include/ssv6200_reg.h	5005;"	d
+SET_PWM_INVERT_0	smac/hal/ssv6006c/ssv6006C_reg.h	9496;"	d
+SET_PWM_INVERT_1	smac/hal/ssv6006c/ssv6006C_reg.h	9503;"	d
+SET_PWM_INVERT_2	smac/hal/ssv6006c/ssv6006C_reg.h	9510;"	d
+SET_PWM_INVERT_3	smac/hal/ssv6006c/ssv6006C_reg.h	9517;"	d
+SET_PWM_INVERT_4	smac/hal/ssv6006c/ssv6006C_reg.h	9524;"	d
+SET_PWM_INVERT_A	include/ssv6200_reg.h	5003;"	d
+SET_PWM_INVERT_B	include/ssv6200_reg.h	5009;"	d
+SET_PWM_POST_SCALER_0	smac/hal/ssv6006c/ssv6006C_reg.h	9493;"	d
+SET_PWM_POST_SCALER_1	smac/hal/ssv6006c/ssv6006C_reg.h	9500;"	d
+SET_PWM_POST_SCALER_2	smac/hal/ssv6006c/ssv6006C_reg.h	9507;"	d
+SET_PWM_POST_SCALER_3	smac/hal/ssv6006c/ssv6006C_reg.h	9514;"	d
+SET_PWM_POST_SCALER_4	smac/hal/ssv6006c/ssv6006C_reg.h	9521;"	d
+SET_PWM_POST_SCALER_A	include/ssv6200_reg.h	5001;"	d
+SET_PWM_POST_SCALER_B	include/ssv6200_reg.h	5007;"	d
+SET_PWM_SETTING_UPDATE_0	smac/hal/ssv6006c/ssv6006C_reg.h	9494;"	d
+SET_PWM_SETTING_UPDATE_1	smac/hal/ssv6006c/ssv6006C_reg.h	9501;"	d
+SET_PWM_SETTING_UPDATE_2	smac/hal/ssv6006c/ssv6006C_reg.h	9508;"	d
+SET_PWM_SETTING_UPDATE_3	smac/hal/ssv6006c/ssv6006C_reg.h	9515;"	d
+SET_PWM_SETTING_UPDATE_4	smac/hal/ssv6006c/ssv6006C_reg.h	9522;"	d
+SET_Q0_PKT_CLS_MIB_EN	include/ssv6200_reg.h	6776;"	d
+SET_Q0_PKT_CLS_MIB_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10888;"	d
+SET_Q0_PKT_CLS_ONGOING	include/ssv6200_reg.h	6777;"	d
+SET_Q0_PKT_CLS_ONGOING	smac/hal/ssv6006c/ssv6006C_reg.h	10889;"	d
+SET_Q1_PKT_CLS_MIB_EN	include/ssv6200_reg.h	6778;"	d
+SET_Q1_PKT_CLS_MIB_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10890;"	d
+SET_Q1_PKT_CLS_ONGOING	include/ssv6200_reg.h	6779;"	d
+SET_Q1_PKT_CLS_ONGOING	smac/hal/ssv6006c/ssv6006C_reg.h	10891;"	d
+SET_Q2_PKT_CLS_MIB_EN	include/ssv6200_reg.h	6780;"	d
+SET_Q2_PKT_CLS_MIB_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10892;"	d
+SET_Q2_PKT_CLS_ONGOING	include/ssv6200_reg.h	6781;"	d
+SET_Q2_PKT_CLS_ONGOING	smac/hal/ssv6006c/ssv6006C_reg.h	10893;"	d
+SET_Q3_PKT_CLS_MIB_EN	include/ssv6200_reg.h	6782;"	d
+SET_Q3_PKT_CLS_MIB_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10894;"	d
+SET_Q3_PKT_CLS_ONGOING	include/ssv6200_reg.h	6783;"	d
+SET_Q3_PKT_CLS_ONGOING	smac/hal/ssv6006c/ssv6006C_reg.h	10895;"	d
+SET_QOS_EN	include/ssv6200_reg.h	6730;"	d
+SET_QOS_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10826;"	d
+SET_Q_REQ_DUR	include/ssv6200_reg.h	6461;"	d
+SET_R5_RESPONSE_FLAG	include/ssv6200_reg.h	5571;"	d
+SET_R5_RESPONSE_FLAG	smac/hal/ssv6006c/ssv6006C_reg.h	9604;"	d
+SET_RANDOM_SEED1	smac/hal/ssv6006c/ssv6006C_reg.h	10878;"	d
+SET_RANDOM_SEED2	smac/hal/ssv6006c/ssv6006C_reg.h	10877;"	d
+SET_RANDOM_SEED3	smac/hal/ssv6006c/ssv6006C_reg.h	10876;"	d
+SET_RAND_EN	include/ssv6200_reg.h	6179;"	d
+SET_RAND_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10197;"	d
+SET_RAND_NUM	include/ssv6200_reg.h	6180;"	d
+SET_RAND_NUM	smac/hal/ssv6006c/ssv6006C_reg.h	10198;"	d
+SET_RAW_TYPHOST_INT_MAP	smac/hal/ssv6006c/ssv6006C_reg.h	9948;"	d
+SET_RAW_TYPHOST_INT_MAP_02	smac/hal/ssv6006c/ssv6006C_reg.h	9939;"	d
+SET_RAW_TYPHOST_INT_MAP_15	smac/hal/ssv6006c/ssv6006C_reg.h	9942;"	d
+SET_RAW_TYPHOST_INT_MAP_31	smac/hal/ssv6006c/ssv6006C_reg.h	9945;"	d
+SET_RAW_TYPMCU_INT_MAP	smac/hal/ssv6006c/ssv6006C_reg.h	9961;"	d
+SET_RAW_TYPMCU_INT_MAP_02	smac/hal/ssv6006c/ssv6006C_reg.h	9952;"	d
+SET_RAW_TYPMCU_INT_MAP_15	smac/hal/ssv6006c/ssv6006C_reg.h	9955;"	d
+SET_RAW_TYPMCU_INT_MAP_31	smac/hal/ssv6006c/ssv6006C_reg.h	9958;"	d
+SET_RCAL_RDY	include/ssv6200_reg.h	8414;"	d
+SET_RDATA_RDY	include/ssv6200_reg.h	5704;"	d
+SET_RDY_FOR_FW_DOWNLOAD	include/ssv6200_reg.h	5532;"	d
+SET_RDY_FOR_FW_DOWNLOAD	smac/hal/ssv6006c/ssv6006C_reg.h	9595;"	d
+SET_RDY_FOR_TX_RX	include/ssv6200_reg.h	5531;"	d
+SET_RDY_FOR_TX_RX	smac/hal/ssv6006c/ssv6006C_reg.h	9594;"	d
+SET_RD_ADDR	include/ssv6200_reg.h	6185;"	d
+SET_RD_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	10203;"	d
+SET_RD_DAT_CNT	include/ssv6200_reg.h	5711;"	d
+SET_RD_DAT_CNT_CLR	include/ssv6200_reg.h	5715;"	d
+SET_RD_ID	include/ssv6200_reg.h	6186;"	d
+SET_RD_ID	smac/hal/ssv6006c/ssv6006C_reg.h	10204;"	d
+SET_RD_STS_CNT	include/ssv6200_reg.h	5712;"	d
+SET_RD_STS_CNT_CLR	include/ssv6200_reg.h	5714;"	d
+SET_READ_ADDRESS	include/ssv6200_reg.h	5579;"	d
+SET_READ_DATA	include/ssv6200_reg.h	5578;"	d
+SET_REASON_TRAP0	include/ssv6200_reg.h	6736;"	d
+SET_REASON_TRAP0	smac/hal/ssv6006c/ssv6006C_reg.h	10834;"	d
+SET_REASON_TRAP1	include/ssv6200_reg.h	6737;"	d
+SET_REASON_TRAP1	smac/hal/ssv6006c/ssv6006C_reg.h	10835;"	d
+SET_REG	smac/hal/ssv6006c/ssv6006C_reg.h	9074;"	d
+SET_REG_AHB_DEBUG_MX	include/ssv6200_reg.h	4970;"	d
+SET_REG_PKT_R_NBRT	include/ssv6200_reg.h	4972;"	d
+SET_REG_PKT_W_NBRT	include/ssv6200_reg.h	4971;"	d
+SET_REQ_LOCK	include/ssv6200_reg.h	7412;"	d
+SET_REQ_LOCK	smac/hal/ssv6006c/ssv6006C_reg.h	15856;"	d
+SET_REQ_LOCK_INT	include/ssv6200_reg.h	7418;"	d
+SET_REQ_LOCK_INT	smac/hal/ssv6006c/ssv6006C_reg.h	15862;"	d
+SET_REQ_LOCK_INT_EN	include/ssv6200_reg.h	7417;"	d
+SET_REQ_LOCK_INT_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15861;"	d
+SET_REQ_NACK_CLR	include/ssv6200_reg.h	8474;"	d
+SET_REQ_PORNS_CHGEN	include/ssv6200_reg.h	8478;"	d
+SET_RESET_N_CPUN10	smac/hal/ssv6006c/ssv6006C_reg.h	9324;"	d
+SET_RESP_OUT_EDGE	include/ssv6200_reg.h	5572;"	d
+SET_RF_BB_SW_RST	include/ssv6200_reg.h	4927;"	d
+SET_RG_11B_ACI_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	15099;"	d
+SET_RG_40M_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	14481;"	d
+SET_RG_5G_BYPASS_COARSE_FREQ	smac/hal/ssv6006c/ssv6006C_reg.h	15538;"	d
+SET_RG_5G_CCFO_CNT_LMT	smac/hal/ssv6006c/ssv6006C_reg.h	15537;"	d
+SET_RG_5G_CCFO_GAIN_BY2	smac/hal/ssv6006c/ssv6006C_reg.h	15539;"	d
+SET_RG_5G_DC_RM_LEAKY_FACTOR_T1	smac/hal/ssv6006c/ssv6006C_reg.h	15203;"	d
+SET_RG_5G_DC_RM_LEAKY_FACTOR_T2	smac/hal/ssv6006c/ssv6006C_reg.h	15202;"	d
+SET_RG_5G_DC_RM_LEAKY_FACTOR_T3	smac/hal/ssv6006c/ssv6006C_reg.h	15201;"	d
+SET_RG_5G_EN_IREF_RX	smac/hal/ssv6006c/ssv6006C_reg.h	14061;"	d
+SET_RG_5G_EN_LDO_RX_FE	smac/hal/ssv6006c/ssv6006C_reg.h	14060;"	d
+SET_RG_5G_EN_LDO_RX_FE_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	14052;"	d
+SET_RG_5G_EN_LDO_RX_FE_FC	smac/hal/ssv6006c/ssv6006C_reg.h	14062;"	d
+SET_RG_5G_EN_LDO_RX_FE_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	14063;"	d
+SET_RG_5G_EN_RX_DIV2	smac/hal/ssv6006c/ssv6006C_reg.h	14029;"	d
+SET_RG_5G_EN_RX_IQCAL	smac/hal/ssv6006c/ssv6006C_reg.h	14047;"	d
+SET_RG_5G_EN_RX_LNA	smac/hal/ssv6006c/ssv6006C_reg.h	14025;"	d
+SET_RG_5G_EN_RX_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	14031;"	d
+SET_RG_5G_EN_RX_MIXER	smac/hal/ssv6006c/ssv6006C_reg.h	14027;"	d
+SET_RG_5G_EN_RX_TZ	smac/hal/ssv6006c/ssv6006C_reg.h	14033;"	d
+SET_RG_5G_EN_TX_DIV2	smac/hal/ssv6006c/ssv6006C_reg.h	14039;"	d
+SET_RG_5G_EN_TX_DIV2_BUF	smac/hal/ssv6006c/ssv6006C_reg.h	14041;"	d
+SET_RG_5G_EN_TX_DPD	smac/hal/ssv6006c/ssv6006C_reg.h	14049;"	d
+SET_RG_5G_EN_TX_MOD	smac/hal/ssv6006c/ssv6006C_reg.h	14037;"	d
+SET_RG_5G_EN_TX_PA	smac/hal/ssv6006c/ssv6006C_reg.h	14035;"	d
+SET_RG_5G_EN_TX_SELF_MIXER	smac/hal/ssv6006c/ssv6006C_reg.h	14045;"	d
+SET_RG_5G_EN_TX_TRSW	smac/hal/ssv6006c/ssv6006C_reg.h	14023;"	d
+SET_RG_5G_EN_TX_TSSI	smac/hal/ssv6006c/ssv6006C_reg.h	14050;"	d
+SET_RG_5G_GM_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	14069;"	d
+SET_RG_5G_IDACAI_TZ0_COARSE0	smac/hal/ssv6006c/ssv6006C_reg.h	14386;"	d
+SET_RG_5G_IDACAI_TZ0_COARSE1	smac/hal/ssv6006c/ssv6006C_reg.h	14384;"	d
+SET_RG_5G_IDACAI_TZ0_COARSE2	smac/hal/ssv6006c/ssv6006C_reg.h	14382;"	d
+SET_RG_5G_IDACAI_TZ0_COARSE3	smac/hal/ssv6006c/ssv6006C_reg.h	14380;"	d
+SET_RG_5G_IDACAI_TZ0_COARSE4	smac/hal/ssv6006c/ssv6006C_reg.h	14378;"	d
+SET_RG_5G_IDACAI_TZ0_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	14344;"	d
+SET_RG_5G_IDACAI_TZ0_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	14342;"	d
+SET_RG_5G_IDACAI_TZ0_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	14324;"	d
+SET_RG_5G_IDACAI_TZ0_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	14322;"	d
+SET_RG_5G_IDACAI_TZ0_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	14320;"	d
+SET_RG_5G_IDACAI_TZ0_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	14318;"	d
+SET_RG_5G_IDACAI_TZ0_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	14316;"	d
+SET_RG_5G_IDACAI_TZ0_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	14314;"	d
+SET_RG_5G_IDACAI_TZ0_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	14340;"	d
+SET_RG_5G_IDACAI_TZ0_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	14338;"	d
+SET_RG_5G_IDACAI_TZ0_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	14336;"	d
+SET_RG_5G_IDACAI_TZ0_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	14334;"	d
+SET_RG_5G_IDACAI_TZ0_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	14332;"	d
+SET_RG_5G_IDACAI_TZ0_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	14330;"	d
+SET_RG_5G_IDACAI_TZ0_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	14328;"	d
+SET_RG_5G_IDACAI_TZ0_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	14326;"	d
+SET_RG_5G_IDACAI_TZ1_COARSE0	smac/hal/ssv6006c/ssv6006C_reg.h	14396;"	d
+SET_RG_5G_IDACAI_TZ1_COARSE1	smac/hal/ssv6006c/ssv6006C_reg.h	14394;"	d
+SET_RG_5G_IDACAI_TZ1_COARSE2	smac/hal/ssv6006c/ssv6006C_reg.h	14392;"	d
+SET_RG_5G_IDACAI_TZ1_COARSE3	smac/hal/ssv6006c/ssv6006C_reg.h	14390;"	d
+SET_RG_5G_IDACAI_TZ1_COARSE4	smac/hal/ssv6006c/ssv6006C_reg.h	14388;"	d
+SET_RG_5G_IDACAI_TZ1_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	14376;"	d
+SET_RG_5G_IDACAI_TZ1_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	14374;"	d
+SET_RG_5G_IDACAI_TZ1_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	14356;"	d
+SET_RG_5G_IDACAI_TZ1_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	14354;"	d
+SET_RG_5G_IDACAI_TZ1_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	14352;"	d
+SET_RG_5G_IDACAI_TZ1_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	14350;"	d
+SET_RG_5G_IDACAI_TZ1_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	14348;"	d
+SET_RG_5G_IDACAI_TZ1_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	14346;"	d
+SET_RG_5G_IDACAI_TZ1_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	14372;"	d
+SET_RG_5G_IDACAI_TZ1_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	14370;"	d
+SET_RG_5G_IDACAI_TZ1_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	14368;"	d
+SET_RG_5G_IDACAI_TZ1_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	14366;"	d
+SET_RG_5G_IDACAI_TZ1_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	14364;"	d
+SET_RG_5G_IDACAI_TZ1_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	14362;"	d
+SET_RG_5G_IDACAI_TZ1_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	14360;"	d
+SET_RG_5G_IDACAI_TZ1_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	14358;"	d
+SET_RG_5G_IDACAQ_TZ0_COARSE0	smac/hal/ssv6006c/ssv6006C_reg.h	14387;"	d
+SET_RG_5G_IDACAQ_TZ0_COARSE1	smac/hal/ssv6006c/ssv6006C_reg.h	14385;"	d
+SET_RG_5G_IDACAQ_TZ0_COARSE2	smac/hal/ssv6006c/ssv6006C_reg.h	14383;"	d
+SET_RG_5G_IDACAQ_TZ0_COARSE3	smac/hal/ssv6006c/ssv6006C_reg.h	14381;"	d
+SET_RG_5G_IDACAQ_TZ0_COARSE4	smac/hal/ssv6006c/ssv6006C_reg.h	14379;"	d
+SET_RG_5G_IDACAQ_TZ0_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	14345;"	d
+SET_RG_5G_IDACAQ_TZ0_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	14343;"	d
+SET_RG_5G_IDACAQ_TZ0_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	14325;"	d
+SET_RG_5G_IDACAQ_TZ0_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	14323;"	d
+SET_RG_5G_IDACAQ_TZ0_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	14321;"	d
+SET_RG_5G_IDACAQ_TZ0_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	14319;"	d
+SET_RG_5G_IDACAQ_TZ0_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	14317;"	d
+SET_RG_5G_IDACAQ_TZ0_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	14315;"	d
+SET_RG_5G_IDACAQ_TZ0_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	14341;"	d
+SET_RG_5G_IDACAQ_TZ0_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	14339;"	d
+SET_RG_5G_IDACAQ_TZ0_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	14337;"	d
+SET_RG_5G_IDACAQ_TZ0_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	14335;"	d
+SET_RG_5G_IDACAQ_TZ0_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	14333;"	d
+SET_RG_5G_IDACAQ_TZ0_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	14331;"	d
+SET_RG_5G_IDACAQ_TZ0_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	14329;"	d
+SET_RG_5G_IDACAQ_TZ0_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	14327;"	d
+SET_RG_5G_IDACAQ_TZ1_COARSE0	smac/hal/ssv6006c/ssv6006C_reg.h	14397;"	d
+SET_RG_5G_IDACAQ_TZ1_COARSE1	smac/hal/ssv6006c/ssv6006C_reg.h	14395;"	d
+SET_RG_5G_IDACAQ_TZ1_COARSE2	smac/hal/ssv6006c/ssv6006C_reg.h	14393;"	d
+SET_RG_5G_IDACAQ_TZ1_COARSE3	smac/hal/ssv6006c/ssv6006C_reg.h	14391;"	d
+SET_RG_5G_IDACAQ_TZ1_COARSE4	smac/hal/ssv6006c/ssv6006C_reg.h	14389;"	d
+SET_RG_5G_IDACAQ_TZ1_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	14377;"	d
+SET_RG_5G_IDACAQ_TZ1_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	14375;"	d
+SET_RG_5G_IDACAQ_TZ1_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	14357;"	d
+SET_RG_5G_IDACAQ_TZ1_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	14355;"	d
+SET_RG_5G_IDACAQ_TZ1_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	14353;"	d
+SET_RG_5G_IDACAQ_TZ1_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	14351;"	d
+SET_RG_5G_IDACAQ_TZ1_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	14349;"	d
+SET_RG_5G_IDACAQ_TZ1_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	14347;"	d
+SET_RG_5G_IDACAQ_TZ1_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	14373;"	d
+SET_RG_5G_IDACAQ_TZ1_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	14371;"	d
+SET_RG_5G_IDACAQ_TZ1_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	14369;"	d
+SET_RG_5G_IDACAQ_TZ1_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	14367;"	d
+SET_RG_5G_IDACAQ_TZ1_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	14365;"	d
+SET_RG_5G_IDACAQ_TZ1_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	14363;"	d
+SET_RG_5G_IDACAQ_TZ1_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	14361;"	d
+SET_RG_5G_IDACAQ_TZ1_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	14359;"	d
+SET_RG_5G_LDO_LEVEL_RX_FE	smac/hal/ssv6006c/ssv6006C_reg.h	14051;"	d
+SET_RG_5G_PABIAS_2X	smac/hal/ssv6006c/ssv6006C_reg.h	14094;"	d
+SET_RG_5G_PABIAS_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	14090;"	d
+SET_RG_5G_PABIAS_CTRL_F0	smac/hal/ssv6006c/ssv6006C_reg.h	14453;"	d
+SET_RG_5G_PABIAS_CTRL_F1	smac/hal/ssv6006c/ssv6006C_reg.h	14458;"	d
+SET_RG_5G_PABIAS_CTRL_F2	smac/hal/ssv6006c/ssv6006C_reg.h	14463;"	d
+SET_RG_5G_PABIAS_CTRL_F3	smac/hal/ssv6006c/ssv6006C_reg.h	14468;"	d
+SET_RG_5G_PACELL_EN	smac/hal/ssv6006c/ssv6006C_reg.h	14089;"	d
+SET_RG_5G_PGAG_DPDCAL	smac/hal/ssv6006c/ssv6006C_reg.h	14422;"	d
+SET_RG_5G_PGAG_RCCAL	smac/hal/ssv6006c/ssv6006C_reg.h	14417;"	d
+SET_RG_5G_PGAG_RXIQCAL	smac/hal/ssv6006c/ssv6006C_reg.h	14419;"	d
+SET_RG_5G_PGAG_TXCAL	smac/hal/ssv6006c/ssv6006C_reg.h	14415;"	d
+SET_RG_5G_RFG_DPDCAL	smac/hal/ssv6006c/ssv6006C_reg.h	14421;"	d
+SET_RG_5G_RFG_RXIQCAL	smac/hal/ssv6006c/ssv6006C_reg.h	14418;"	d
+SET_RG_5G_RXRF_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	14402;"	d
+SET_RG_5G_RXRF_R2T_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	14410;"	d
+SET_RG_5G_RXRF_T2R_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	14406;"	d
+SET_RG_5G_RX_ADC_CLOAD	smac/hal/ssv6006c/ssv6006C_reg.h	14083;"	d
+SET_RG_5G_RX_ADC_ICMP	smac/hal/ssv6006c/ssv6006C_reg.h	14081;"	d
+SET_RG_5G_RX_ADC_PSW	smac/hal/ssv6006c/ssv6006C_reg.h	14084;"	d
+SET_RG_5G_RX_ADC_VCMI	smac/hal/ssv6006c/ssv6006C_reg.h	14082;"	d
+SET_RG_5G_RX_DCCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	14411;"	d
+SET_RG_5G_RX_DIV2_BUF	smac/hal/ssv6006c/ssv6006C_reg.h	14070;"	d
+SET_RG_5G_RX_DIV2_CML	smac/hal/ssv6006c/ssv6006C_reg.h	14071;"	d
+SET_RG_5G_RX_DIV2_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	14028;"	d
+SET_RG_5G_RX_DIV_CMLISEL	smac/hal/ssv6006c/ssv6006C_reg.h	14072;"	d
+SET_RG_5G_RX_DIV_PREBUFS2	smac/hal/ssv6006c/ssv6006C_reg.h	14073;"	d
+SET_RG_5G_RX_HG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	14117;"	d
+SET_RG_5G_RX_HG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	14112;"	d
+SET_RG_5G_RX_HG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	14113;"	d
+SET_RG_5G_RX_HG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	14114;"	d
+SET_RG_5G_RX_HG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	14110;"	d
+SET_RG_5G_RX_HG_SQDC	smac/hal/ssv6006c/ssv6006C_reg.h	14116;"	d
+SET_RG_5G_RX_HG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	14119;"	d
+SET_RG_5G_RX_HG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	14115;"	d
+SET_RG_5G_RX_HG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	14111;"	d
+SET_RG_5G_RX_HG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	14118;"	d
+SET_RG_5G_RX_HG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	14120;"	d
+SET_RG_5G_RX_IQCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	14414;"	d
+SET_RG_5G_RX_IQCAL_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	14046;"	d
+SET_RG_5G_RX_LG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	14139;"	d
+SET_RG_5G_RX_LG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	14134;"	d
+SET_RG_5G_RX_LG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	14135;"	d
+SET_RG_5G_RX_LG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	14136;"	d
+SET_RG_5G_RX_LG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	14132;"	d
+SET_RG_5G_RX_LG_SQDC	smac/hal/ssv6006c/ssv6006C_reg.h	14138;"	d
+SET_RG_5G_RX_LG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	14141;"	d
+SET_RG_5G_RX_LG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	14137;"	d
+SET_RG_5G_RX_LG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	14133;"	d
+SET_RG_5G_RX_LG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	14140;"	d
+SET_RG_5G_RX_LG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	14142;"	d
+SET_RG_5G_RX_LNA_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	14024;"	d
+SET_RG_5G_RX_LNA_SETTLE	smac/hal/ssv6006c/ssv6006C_reg.h	14068;"	d
+SET_RG_5G_RX_LNA_TRI_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	14067;"	d
+SET_RG_5G_RX_LOBUF_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	14030;"	d
+SET_RG_5G_RX_MG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	14128;"	d
+SET_RG_5G_RX_MG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	14123;"	d
+SET_RG_5G_RX_MG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	14124;"	d
+SET_RG_5G_RX_MG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	14125;"	d
+SET_RG_5G_RX_MG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	14121;"	d
+SET_RG_5G_RX_MG_SQDC	smac/hal/ssv6006c/ssv6006C_reg.h	14127;"	d
+SET_RG_5G_RX_MG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	14130;"	d
+SET_RG_5G_RX_MG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	14126;"	d
+SET_RG_5G_RX_MG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	14122;"	d
+SET_RG_5G_RX_MG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	14129;"	d
+SET_RG_5G_RX_MG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	14131;"	d
+SET_RG_5G_RX_MIXER_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	14026;"	d
+SET_RG_5G_RX_SCA_LOAD	smac/hal/ssv6006c/ssv6006C_reg.h	14066;"	d
+SET_RG_5G_RX_SCA_MA	smac/hal/ssv6006c/ssv6006C_reg.h	14065;"	d
+SET_RG_5G_RX_SCA_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	14064;"	d
+SET_RG_5G_RX_TZ_CMZ_C	smac/hal/ssv6006c/ssv6006C_reg.h	14085;"	d
+SET_RG_5G_RX_TZ_CMZ_R	smac/hal/ssv6006c/ssv6006C_reg.h	14086;"	d
+SET_RG_5G_RX_TZ_COURSE	smac/hal/ssv6006c/ssv6006C_reg.h	14074;"	d
+SET_RG_5G_RX_TZ_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	14032;"	d
+SET_RG_5G_RX_TZ_OUT_TRISTATE	smac/hal/ssv6006c/ssv6006C_reg.h	14043;"	d
+SET_RG_5G_RX_TZ_OUT_TRISTATE_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	14042;"	d
+SET_RG_5G_RX_ULG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	14150;"	d
+SET_RG_5G_RX_ULG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	14145;"	d
+SET_RG_5G_RX_ULG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	14146;"	d
+SET_RG_5G_RX_ULG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	14147;"	d
+SET_RG_5G_RX_ULG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	14143;"	d
+SET_RG_5G_RX_ULG_SQDC	smac/hal/ssv6006c/ssv6006C_reg.h	14149;"	d
+SET_RG_5G_RX_ULG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	14152;"	d
+SET_RG_5G_RX_ULG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	14148;"	d
+SET_RG_5G_RX_ULG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	14144;"	d
+SET_RG_5G_RX_ULG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	14151;"	d
+SET_RG_5G_RX_ULG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	14153;"	d
+SET_RG_5G_TXDAC_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	14399;"	d
+SET_RG_5G_TXDAC_R2T_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	14407;"	d
+SET_RG_5G_TXDAC_T2R_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	14403;"	d
+SET_RG_5G_TXLPF_BOOSTI	smac/hal/ssv6006c/ssv6006C_reg.h	14160;"	d
+SET_RG_5G_TXLPF_GMCELL	smac/hal/ssv6006c/ssv6006C_reg.h	14104;"	d
+SET_RG_5G_TXMOD_GMCELL	smac/hal/ssv6006c/ssv6006C_reg.h	14103;"	d
+SET_RG_5G_TXMOD_LOBIAS	smac/hal/ssv6006c/ssv6006C_reg.h	14108;"	d
+SET_RG_5G_TXMOD_PGABIAS	smac/hal/ssv6006c/ssv6006C_reg.h	14109;"	d
+SET_RG_5G_TXPAPGA_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	14087;"	d
+SET_RG_5G_TXPA_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	14401;"	d
+SET_RG_5G_TXPA_R2T_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	14409;"	d
+SET_RG_5G_TXPA_T2R_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	14405;"	d
+SET_RG_5G_TXPGA_CAPSW	smac/hal/ssv6006c/ssv6006C_reg.h	14088;"	d
+SET_RG_5G_TXPGA_CAPSW_F0	smac/hal/ssv6006c/ssv6006C_reg.h	14452;"	d
+SET_RG_5G_TXPGA_CAPSW_F1	smac/hal/ssv6006c/ssv6006C_reg.h	14457;"	d
+SET_RG_5G_TXPGA_CAPSW_F2	smac/hal/ssv6006c/ssv6006C_reg.h	14462;"	d
+SET_RG_5G_TXPGA_CAPSW_F3	smac/hal/ssv6006c/ssv6006C_reg.h	14467;"	d
+SET_RG_5G_TXPGA_MAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14101;"	d
+SET_RG_5G_TXPGA_STEER	smac/hal/ssv6006c/ssv6006C_reg.h	14102;"	d
+SET_RG_5G_TXRF_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	14400;"	d
+SET_RG_5G_TXRF_R2T_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	14408;"	d
+SET_RG_5G_TXRF_T2R_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	14404;"	d
+SET_RG_5G_TX_ADDGMCELL	smac/hal/ssv6006c/ssv6006C_reg.h	14107;"	d
+SET_RG_5G_TX_BAND_F0	smac/hal/ssv6006c/ssv6006C_reg.h	14621;"	d
+SET_RG_5G_TX_BAND_F1	smac/hal/ssv6006c/ssv6006C_reg.h	14620;"	d
+SET_RG_5G_TX_BAND_F2	smac/hal/ssv6006c/ssv6006C_reg.h	14622;"	d
+SET_RG_5G_TX_DACI1ST	smac/hal/ssv6006c/ssv6006C_reg.h	14154;"	d
+SET_RG_5G_TX_DACLPF_ICOARSE	smac/hal/ssv6006c/ssv6006C_reg.h	14155;"	d
+SET_RG_5G_TX_DACLPF_IFINE	smac/hal/ssv6006c/ssv6006C_reg.h	14156;"	d
+SET_RG_5G_TX_DACLPF_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	14157;"	d
+SET_RG_5G_TX_DAC_CKEDGE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	14162;"	d
+SET_RG_5G_TX_DAC_IATTN	smac/hal/ssv6006c/ssv6006C_reg.h	14159;"	d
+SET_RG_5G_TX_DAC_IBIAS	smac/hal/ssv6006c/ssv6006C_reg.h	14158;"	d
+SET_RG_5G_TX_DAC_IOFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	14164;"	d
+SET_RG_5G_TX_DAC_OS	smac/hal/ssv6006c/ssv6006C_reg.h	14163;"	d
+SET_RG_5G_TX_DAC_QOFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	14165;"	d
+SET_RG_5G_TX_DAC_RCAL	smac/hal/ssv6006c/ssv6006C_reg.h	14161;"	d
+SET_RG_5G_TX_DCCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	14412;"	d
+SET_RG_5G_TX_DIV2_BUF_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	14040;"	d
+SET_RG_5G_TX_DIV2_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	14038;"	d
+SET_RG_5G_TX_DIV_CMLISEL	smac/hal/ssv6006c/ssv6006C_reg.h	14097;"	d
+SET_RG_5G_TX_DIV_CMLVSEL	smac/hal/ssv6006c/ssv6006C_reg.h	14098;"	d
+SET_RG_5G_TX_DIV_PREBUFS2	smac/hal/ssv6006c/ssv6006C_reg.h	14096;"	d
+SET_RG_5G_TX_DIV_VSET	smac/hal/ssv6006c/ssv6006C_reg.h	14099;"	d
+SET_RG_5G_TX_DPDGM_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	14075;"	d
+SET_RG_5G_TX_DPD_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	14076;"	d
+SET_RG_5G_TX_DPD_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	14048;"	d
+SET_RG_5G_TX_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14106;"	d
+SET_RG_5G_TX_GAIN_DPDCAL	smac/hal/ssv6006c/ssv6006C_reg.h	14423;"	d
+SET_RG_5G_TX_GAIN_F0	smac/hal/ssv6006c/ssv6006C_reg.h	14476;"	d
+SET_RG_5G_TX_GAIN_F1	smac/hal/ssv6006c/ssv6006C_reg.h	14477;"	d
+SET_RG_5G_TX_GAIN_F2	smac/hal/ssv6006c/ssv6006C_reg.h	14478;"	d
+SET_RG_5G_TX_GAIN_F3	smac/hal/ssv6006c/ssv6006C_reg.h	14479;"	d
+SET_RG_5G_TX_GAIN_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	13365;"	d
+SET_RG_5G_TX_GAIN_OFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	14105;"	d
+SET_RG_5G_TX_GAIN_RXIQCAL	smac/hal/ssv6006c/ssv6006C_reg.h	14420;"	d
+SET_RG_5G_TX_GAIN_TXCAL	smac/hal/ssv6006c/ssv6006C_reg.h	14416;"	d
+SET_RG_5G_TX_IQCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	14413;"	d
+SET_RG_5G_TX_LOBUF_VSET	smac/hal/ssv6006c/ssv6006C_reg.h	14100;"	d
+SET_RG_5G_TX_MOD_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	14036;"	d
+SET_RG_5G_TX_PA1_VCAS	smac/hal/ssv6006c/ssv6006C_reg.h	14092;"	d
+SET_RG_5G_TX_PA1_VCAS_F0	smac/hal/ssv6006c/ssv6006C_reg.h	14454;"	d
+SET_RG_5G_TX_PA1_VCAS_F1	smac/hal/ssv6006c/ssv6006C_reg.h	14459;"	d
+SET_RG_5G_TX_PA1_VCAS_F2	smac/hal/ssv6006c/ssv6006C_reg.h	14464;"	d
+SET_RG_5G_TX_PA1_VCAS_F3	smac/hal/ssv6006c/ssv6006C_reg.h	14469;"	d
+SET_RG_5G_TX_PA2_VCAS	smac/hal/ssv6006c/ssv6006C_reg.h	14093;"	d
+SET_RG_5G_TX_PA2_VCAS_F0	smac/hal/ssv6006c/ssv6006C_reg.h	14455;"	d
+SET_RG_5G_TX_PA2_VCAS_F1	smac/hal/ssv6006c/ssv6006C_reg.h	14460;"	d
+SET_RG_5G_TX_PA2_VCAS_F2	smac/hal/ssv6006c/ssv6006C_reg.h	14465;"	d
+SET_RG_5G_TX_PA2_VCAS_F3	smac/hal/ssv6006c/ssv6006C_reg.h	14470;"	d
+SET_RG_5G_TX_PA3_VCAS	smac/hal/ssv6006c/ssv6006C_reg.h	14095;"	d
+SET_RG_5G_TX_PA3_VCAS_F0	smac/hal/ssv6006c/ssv6006C_reg.h	14456;"	d
+SET_RG_5G_TX_PA3_VCAS_F1	smac/hal/ssv6006c/ssv6006C_reg.h	14461;"	d
+SET_RG_5G_TX_PA3_VCAS_F2	smac/hal/ssv6006c/ssv6006C_reg.h	14466;"	d
+SET_RG_5G_TX_PA3_VCAS_F3	smac/hal/ssv6006c/ssv6006C_reg.h	14471;"	d
+SET_RG_5G_TX_PAFB_EN	smac/hal/ssv6006c/ssv6006C_reg.h	14091;"	d
+SET_RG_5G_TX_PAFB_EN_F0	smac/hal/ssv6006c/ssv6006C_reg.h	14472;"	d
+SET_RG_5G_TX_PAFB_EN_F1	smac/hal/ssv6006c/ssv6006C_reg.h	14473;"	d
+SET_RG_5G_TX_PAFB_EN_F2	smac/hal/ssv6006c/ssv6006C_reg.h	14474;"	d
+SET_RG_5G_TX_PAFB_EN_F3	smac/hal/ssv6006c/ssv6006C_reg.h	14475;"	d
+SET_RG_5G_TX_PA_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	14034;"	d
+SET_RG_5G_TX_SELF_MIXER_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	14044;"	d
+SET_RG_5G_TX_TRSW_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	14022;"	d
+SET_RG_5G_TX_TSSI_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	14077;"	d
+SET_RG_5G_TX_TSSI_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	14078;"	d
+SET_RG_5G_TX_TSSI_TEST	smac/hal/ssv6006c/ssv6006C_reg.h	14079;"	d
+SET_RG_5G_TX_TSSI_TESTMODE	smac/hal/ssv6006c/ssv6006C_reg.h	14080;"	d
+SET_RG_AAC5GB_PDSW_EN_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	14302;"	d
+SET_RG_AAC5GB_TAR_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	14301;"	d
+SET_RG_ACI_DAGC_DONE_CNT_LMT_11GN	include/ssv6200_reg.h	7597;"	d
+SET_RG_ACI_DAGC_DONE_CNT_LMT_11GN	smac/hal/ssv6006c/ssv6006C_reg.h	15180;"	d
+SET_RG_ACI_DAGC_LEAKY_FACTOR_11B	include/ssv6200_reg.h	7590;"	d
+SET_RG_ACI_DAGC_LEAKY_FACTOR_11B	smac/hal/ssv6006c/ssv6006C_reg.h	15171;"	d
+SET_RG_ACI_DAGC_LEAKY_FACTOR_11GN	include/ssv6200_reg.h	7596;"	d
+SET_RG_ACI_DAGC_LEAKY_FACTOR_11GN_HT20	smac/hal/ssv6006c/ssv6006C_reg.h	15178;"	d
+SET_RG_ACI_DAGC_LEAKY_FACTOR_11GN_HT40	smac/hal/ssv6006c/ssv6006C_reg.h	15248;"	d
+SET_RG_ACI_DAGC_PWR_SEL_11B	smac/hal/ssv6006c/ssv6006C_reg.h	15172;"	d
+SET_RG_ACI_DAGC_PWR_SEL_11GN_HT20	smac/hal/ssv6006c/ssv6006C_reg.h	15179;"	d
+SET_RG_ACI_DAGC_PWR_SEL_11GN_HT40	smac/hal/ssv6006c/ssv6006C_reg.h	15249;"	d
+SET_RG_ACI_DAGC_SET_VALUE_11B	include/ssv6200_reg.h	7593;"	d
+SET_RG_ACI_DAGC_SET_VALUE_11GN	include/ssv6200_reg.h	7598;"	d
+SET_RG_ACI_DAGC_TARGET_11B	smac/hal/ssv6006c/ssv6006C_reg.h	15173;"	d
+SET_RG_ACI_DAGC_TARGET_11GN_HT20	smac/hal/ssv6006c/ssv6006C_reg.h	15181;"	d
+SET_RG_ACI_DAGC_TARGET_11GN_HT40	smac/hal/ssv6006c/ssv6006C_reg.h	15250;"	d
+SET_RG_ACI_GAIN	include/ssv6200_reg.h	8040;"	d
+SET_RG_ACI_GAIN_INI_11B	smac/hal/ssv6006c/ssv6006C_reg.h	15174;"	d
+SET_RG_ACI_GAIN_INI_11GN_HT20	smac/hal/ssv6006c/ssv6006C_reg.h	15254;"	d
+SET_RG_ACI_GAIN_INI_11GN_HT40	smac/hal/ssv6006c/ssv6006C_reg.h	15253;"	d
+SET_RG_ACI_GAIN_INI_VAL_11GN	include/ssv6200_reg.h	7599;"	d
+SET_RG_ACI_GAIN_OW_11B	smac/hal/ssv6006c/ssv6006C_reg.h	15176;"	d
+SET_RG_ACI_GAIN_OW_11GN	include/ssv6200_reg.h	7601;"	d
+SET_RG_ACI_GAIN_OW_11GN_HT20	smac/hal/ssv6006c/ssv6006C_reg.h	15183;"	d
+SET_RG_ACI_GAIN_OW_11GN_HT40	smac/hal/ssv6006c/ssv6006C_reg.h	15252;"	d
+SET_RG_ACI_GAIN_OW_VAL_11GN	include/ssv6200_reg.h	7600;"	d
+SET_RG_ACI_GAIN_SET_11B	smac/hal/ssv6006c/ssv6006C_reg.h	15175;"	d
+SET_RG_ACI_GAIN_SET_11GN_HT20	smac/hal/ssv6006c/ssv6006C_reg.h	15182;"	d
+SET_RG_ACI_GAIN_SET_11GN_HT40	smac/hal/ssv6006c/ssv6006C_reg.h	15251;"	d
+SET_RG_ACI_POINT_CNT_LMT_11B	include/ssv6200_reg.h	7589;"	d
+SET_RG_ACI_POINT_CNT_LMT_11B	smac/hal/ssv6006c/ssv6006C_reg.h	15170;"	d
+SET_RG_ACI_POINT_CNT_LMT_11GN	include/ssv6200_reg.h	7595;"	d
+SET_RG_ACI_POINT_CNT_LMT_11GN_HT20	smac/hal/ssv6006c/ssv6006C_reg.h	15177;"	d
+SET_RG_ACI_POINT_CNT_LMT_11GN_HT40	smac/hal/ssv6006c/ssv6006C_reg.h	15247;"	d
+SET_RG_ACS_INI_PM_ALL0	smac/hal/ssv6006c/ssv6006C_reg.h	15540;"	d
+SET_RG_ADC2LA_CLKPH	include/ssv6200_reg.h	8048;"	d
+SET_RG_ADC2LA_SEL	include/ssv6200_reg.h	8047;"	d
+SET_RG_ADC_CLKSEL	include/ssv6200_reg.h	8255;"	d
+SET_RG_ADC_DIBIAS	include/ssv6200_reg.h	8256;"	d
+SET_RG_ADC_DIVR	include/ssv6200_reg.h	8257;"	d
+SET_RG_ADC_DVCMI	include/ssv6200_reg.h	8258;"	d
+SET_RG_ADC_EDGE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	14491;"	d
+SET_RG_ADC_SAMSEL	include/ssv6200_reg.h	8259;"	d
+SET_RG_ADC_STNBY	include/ssv6200_reg.h	8260;"	d
+SET_RG_ADC_TESTMODE	include/ssv6200_reg.h	8261;"	d
+SET_RG_ADC_TSEL	include/ssv6200_reg.h	8262;"	d
+SET_RG_ADC_VRSEL	include/ssv6200_reg.h	8263;"	d
+SET_RG_ADEDGE_SEL	include/ssv6200_reg.h	7501;"	d
+SET_RG_AGC_RELOCK_11B	smac/hal/ssv6006c/ssv6006C_reg.h	15226;"	d
+SET_RG_AGC_RELOCK_11GN	smac/hal/ssv6006c/ssv6006C_reg.h	15225;"	d
+SET_RG_AGC_RELOCK_CNT_DIFFDB_TH	smac/hal/ssv6006c/ssv6006C_reg.h	15228;"	d
+SET_RG_AGC_RELOCK_CNT_TH	smac/hal/ssv6006c/ssv6006C_reg.h	15222;"	d
+SET_RG_AGC_RELOCK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15224;"	d
+SET_RG_AGC_RELOCK_PWR_DIFFDB_TH	smac/hal/ssv6006c/ssv6006C_reg.h	15227;"	d
+SET_RG_AGC_RELOCK_PWR_TH	smac/hal/ssv6006c/ssv6006C_reg.h	15221;"	d
+SET_RG_AGC_RELOCK_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	15223;"	d
+SET_RG_AGC_THRESHOLD	include/ssv6200_reg.h	7588;"	d
+SET_RG_AGC_THRESHOLD	smac/hal/ssv6006c/ssv6006C_reg.h	15169;"	d
+SET_RG_AGGREGATE	include/ssv6200_reg.h	7541;"	d
+SET_RG_AGGREGATE	smac/hal/ssv6006c/ssv6006C_reg.h	15124;"	d
+SET_RG_ALPHA_COARSE	smac/hal/ssv6006c/ssv6006C_reg.h	15610;"	d
+SET_RG_ALPHA_FINE	smac/hal/ssv6006c/ssv6006C_reg.h	15609;"	d
+SET_RG_ALPHA_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	14542;"	d
+SET_RG_ANT_SW_0	include/ssv6200_reg.h	7677;"	d
+SET_RG_ANT_SW_1	include/ssv6200_reg.h	7678;"	d
+SET_RG_ATCOR16_CCA_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	15562;"	d
+SET_RG_ATCOR16_CNT_LMT1	include/ssv6200_reg.h	7867;"	d
+SET_RG_ATCOR16_CNT_LMT1	smac/hal/ssv6006c/ssv6006C_reg.h	15460;"	d
+SET_RG_ATCOR16_CNT_LMT2	include/ssv6200_reg.h	7866;"	d
+SET_RG_ATCOR16_CNT_LMT2	smac/hal/ssv6006c/ssv6006C_reg.h	15459;"	d
+SET_RG_ATCOR16_CNT_PLUS_LMT1	include/ssv6200_reg.h	7891;"	d
+SET_RG_ATCOR16_CNT_PLUS_LMT1	smac/hal/ssv6006c/ssv6006C_reg.h	15484;"	d
+SET_RG_ATCOR16_CNT_PLUS_LMT2	include/ssv6200_reg.h	7890;"	d
+SET_RG_ATCOR16_CNT_PLUS_LMT2	smac/hal/ssv6006c/ssv6006C_reg.h	15483;"	d
+SET_RG_ATCOR16_CNT_TH	include/ssv6200_reg.h	7873;"	d
+SET_RG_ATCOR16_CNT_TH	smac/hal/ssv6006c/ssv6006C_reg.h	15466;"	d
+SET_RG_ATCOR16_RATIO_CCD	include/ssv6200_reg.h	7901;"	d
+SET_RG_ATCOR16_RATIO_CCD	smac/hal/ssv6006c/ssv6006C_reg.h	15530;"	d
+SET_RG_ATCOR16_RATIO_SB	include/ssv6200_reg.h	7868;"	d
+SET_RG_ATCOR16_RATIO_SB	smac/hal/ssv6006c/ssv6006C_reg.h	15461;"	d
+SET_RG_ATCOR16_SHORT_CNT_LMT	include/ssv6200_reg.h	7900;"	d
+SET_RG_ATCOR16_SHORT_CNT_LMT	smac/hal/ssv6006c/ssv6006C_reg.h	15529;"	d
+SET_RG_ATCOR16_SHORT_CNT_LMT2	include/ssv6200_reg.h	7903;"	d
+SET_RG_ATCOR16_SHORT_CNT_LMT2	smac/hal/ssv6006c/ssv6006C_reg.h	15532;"	d
+SET_RG_ATCOR64_ACC_LMT	include/ssv6200_reg.h	7902;"	d
+SET_RG_ATCOR64_ACC_LMT	smac/hal/ssv6006c/ssv6006C_reg.h	15531;"	d
+SET_RG_ATCOR64_CNT_LMT	include/ssv6200_reg.h	7865;"	d
+SET_RG_ATCOR64_CNT_LMT	smac/hal/ssv6006c/ssv6006C_reg.h	15458;"	d
+SET_RG_ATCOR64_FREQ_START	smac/hal/ssv6006c/ssv6006C_reg.h	15560;"	d
+SET_RG_AUDIO_ALPHA	smac/hal/ssv6006c/ssv6006C_reg.h	14611;"	d
+SET_RG_AUDIO_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15333;"	d
+SET_RG_AUDIO_CLK_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	15334;"	d
+SET_RG_AUDIO_FIL_EN	smac/hal/ssv6006c/ssv6006C_reg.h	14612;"	d
+SET_RG_AUDIO_TYPE	smac/hal/ssv6006c/ssv6006C_reg.h	14617;"	d
+SET_RG_AUDIO_VOLUME	smac/hal/ssv6006c/ssv6006C_reg.h	14610;"	d
+SET_RG_BB_11B_FALL_TIME	include/ssv6200_reg.h	7764;"	d
+SET_RG_BB_11B_RISE_TIME	include/ssv6200_reg.h	7763;"	d
+SET_RG_BB_11GN_FALL_TIME	include/ssv6200_reg.h	7840;"	d
+SET_RG_BB_11GN_RISE_TIME	include/ssv6200_reg.h	7839;"	d
+SET_RG_BB_CLK_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	15100;"	d
+SET_RG_BB_FALL_TIME_11B_TX	smac/hal/ssv6006c/ssv6006C_reg.h	15345;"	d
+SET_RG_BB_FALL_TIME_11GN_TX	smac/hal/ssv6006c/ssv6006C_reg.h	15432;"	d
+SET_RG_BB_RISE_TIME_11B_TX	smac/hal/ssv6006c/ssv6006C_reg.h	15344;"	d
+SET_RG_BB_RISE_TIME_11GN_TX	smac/hal/ssv6006c/ssv6006C_reg.h	15431;"	d
+SET_RG_BB_SCALE	smac/hal/ssv6006c/ssv6006C_reg.h	15129;"	d
+SET_RG_BB_SCALE_BARKER_CCK	smac/hal/ssv6006c/ssv6006C_reg.h	15274;"	d
+SET_RG_BB_SCALE_HT20_16QAM	smac/hal/ssv6006c/ssv6006C_reg.h	15281;"	d
+SET_RG_BB_SCALE_HT20_64QAM	smac/hal/ssv6006c/ssv6006C_reg.h	15280;"	d
+SET_RG_BB_SCALE_HT20_BPSK	smac/hal/ssv6006c/ssv6006C_reg.h	15283;"	d
+SET_RG_BB_SCALE_HT20_QPSK	smac/hal/ssv6006c/ssv6006C_reg.h	15282;"	d
+SET_RG_BB_SCALE_HT40_16QAM	smac/hal/ssv6006c/ssv6006C_reg.h	15285;"	d
+SET_RG_BB_SCALE_HT40_64QAM	smac/hal/ssv6006c/ssv6006C_reg.h	15284;"	d
+SET_RG_BB_SCALE_HT40_BPSK	smac/hal/ssv6006c/ssv6006C_reg.h	15287;"	d
+SET_RG_BB_SCALE_HT40_QPSK	smac/hal/ssv6006c/ssv6006C_reg.h	15286;"	d
+SET_RG_BB_SCALE_LEGACY_16QAM	smac/hal/ssv6006c/ssv6006C_reg.h	15277;"	d
+SET_RG_BB_SCALE_LEGACY_64QAM	smac/hal/ssv6006c/ssv6006C_reg.h	15276;"	d
+SET_RG_BB_SCALE_LEGACY_BPSK	smac/hal/ssv6006c/ssv6006C_reg.h	15279;"	d
+SET_RG_BB_SCALE_LEGACY_QPSK	smac/hal/ssv6006c/ssv6006C_reg.h	15278;"	d
+SET_RG_BB_SCALE_MAN_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15275;"	d
+SET_RG_BB_SIG_EN	smac/hal/ssv6006c/ssv6006C_reg.h	14503;"	d
+SET_RG_BIST_EN_CCFO	smac/hal/ssv6006c/ssv6006C_reg.h	15503;"	d
+SET_RG_BIST_EN_RX_FFT	smac/hal/ssv6006c/ssv6006C_reg.h	15327;"	d
+SET_RG_BIST_EN_TX_FFT	smac/hal/ssv6006c/ssv6006C_reg.h	15425;"	d
+SET_RG_BIST_EN_VTB	smac/hal/ssv6006c/ssv6006C_reg.h	15509;"	d
+SET_RG_BIST_MODE_CCFO	smac/hal/ssv6006c/ssv6006C_reg.h	15504;"	d
+SET_RG_BIST_MODE_RX_FFT	smac/hal/ssv6006c/ssv6006C_reg.h	15328;"	d
+SET_RG_BIST_MODE_TX_FFT	smac/hal/ssv6006c/ssv6006C_reg.h	15426;"	d
+SET_RG_BIST_MODE_VTB	smac/hal/ssv6006c/ssv6006C_reg.h	15510;"	d
+SET_RG_BIT_REVERSE	include/ssv6200_reg.h	7835;"	d
+SET_RG_BIT_REVERSE	smac/hal/ssv6006c/ssv6006C_reg.h	15420;"	d
+SET_RG_BP_SMB	include/ssv6200_reg.h	7760;"	d
+SET_RG_BP_SMB	smac/hal/ssv6006c/ssv6006C_reg.h	15346;"	d
+SET_RG_BTRX_BTPASW	smac/hal/ssv6006c/ssv6006C_reg.h	13521;"	d
+SET_RG_BTTX_BTPASW	smac/hal/ssv6006c/ssv6006C_reg.h	13522;"	d
+SET_RG_BT_IDACAI_TZ0_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	13935;"	d
+SET_RG_BT_IDACAI_TZ0_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	13933;"	d
+SET_RG_BT_IDACAI_TZ0_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	13915;"	d
+SET_RG_BT_IDACAI_TZ0_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	13913;"	d
+SET_RG_BT_IDACAI_TZ0_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	13911;"	d
+SET_RG_BT_IDACAI_TZ0_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	13909;"	d
+SET_RG_BT_IDACAI_TZ0_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	13907;"	d
+SET_RG_BT_IDACAI_TZ0_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	13905;"	d
+SET_RG_BT_IDACAI_TZ0_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	13931;"	d
+SET_RG_BT_IDACAI_TZ0_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	13929;"	d
+SET_RG_BT_IDACAI_TZ0_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	13927;"	d
+SET_RG_BT_IDACAI_TZ0_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	13925;"	d
+SET_RG_BT_IDACAI_TZ0_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	13923;"	d
+SET_RG_BT_IDACAI_TZ0_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	13921;"	d
+SET_RG_BT_IDACAI_TZ0_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	13919;"	d
+SET_RG_BT_IDACAI_TZ0_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	13917;"	d
+SET_RG_BT_IDACAI_TZ1_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	13967;"	d
+SET_RG_BT_IDACAI_TZ1_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	13965;"	d
+SET_RG_BT_IDACAI_TZ1_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	13947;"	d
+SET_RG_BT_IDACAI_TZ1_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	13945;"	d
+SET_RG_BT_IDACAI_TZ1_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	13943;"	d
+SET_RG_BT_IDACAI_TZ1_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	13941;"	d
+SET_RG_BT_IDACAI_TZ1_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	13939;"	d
+SET_RG_BT_IDACAI_TZ1_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	13937;"	d
+SET_RG_BT_IDACAI_TZ1_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	13963;"	d
+SET_RG_BT_IDACAI_TZ1_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	13961;"	d
+SET_RG_BT_IDACAI_TZ1_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	13959;"	d
+SET_RG_BT_IDACAI_TZ1_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	13957;"	d
+SET_RG_BT_IDACAI_TZ1_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	13955;"	d
+SET_RG_BT_IDACAI_TZ1_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	13953;"	d
+SET_RG_BT_IDACAI_TZ1_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	13951;"	d
+SET_RG_BT_IDACAI_TZ1_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	13949;"	d
+SET_RG_BT_IDACAQ_TZ0_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	13936;"	d
+SET_RG_BT_IDACAQ_TZ0_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	13934;"	d
+SET_RG_BT_IDACAQ_TZ0_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	13916;"	d
+SET_RG_BT_IDACAQ_TZ0_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	13914;"	d
+SET_RG_BT_IDACAQ_TZ0_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	13912;"	d
+SET_RG_BT_IDACAQ_TZ0_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	13910;"	d
+SET_RG_BT_IDACAQ_TZ0_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	13908;"	d
+SET_RG_BT_IDACAQ_TZ0_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	13906;"	d
+SET_RG_BT_IDACAQ_TZ0_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	13932;"	d
+SET_RG_BT_IDACAQ_TZ0_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	13930;"	d
+SET_RG_BT_IDACAQ_TZ0_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	13928;"	d
+SET_RG_BT_IDACAQ_TZ0_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	13926;"	d
+SET_RG_BT_IDACAQ_TZ0_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	13924;"	d
+SET_RG_BT_IDACAQ_TZ0_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	13922;"	d
+SET_RG_BT_IDACAQ_TZ0_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	13920;"	d
+SET_RG_BT_IDACAQ_TZ0_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	13918;"	d
+SET_RG_BT_IDACAQ_TZ1_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	13968;"	d
+SET_RG_BT_IDACAQ_TZ1_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	13966;"	d
+SET_RG_BT_IDACAQ_TZ1_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	13948;"	d
+SET_RG_BT_IDACAQ_TZ1_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	13946;"	d
+SET_RG_BT_IDACAQ_TZ1_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	13944;"	d
+SET_RG_BT_IDACAQ_TZ1_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	13942;"	d
+SET_RG_BT_IDACAQ_TZ1_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	13940;"	d
+SET_RG_BT_IDACAQ_TZ1_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	13938;"	d
+SET_RG_BT_IDACAQ_TZ1_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	13964;"	d
+SET_RG_BT_IDACAQ_TZ1_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	13962;"	d
+SET_RG_BT_IDACAQ_TZ1_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	13960;"	d
+SET_RG_BT_IDACAQ_TZ1_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	13958;"	d
+SET_RG_BT_IDACAQ_TZ1_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	13956;"	d
+SET_RG_BT_IDACAQ_TZ1_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	13954;"	d
+SET_RG_BT_IDACAQ_TZ1_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	13952;"	d
+SET_RG_BT_IDACAQ_TZ1_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	13950;"	d
+SET_RG_BT_PABIAS_2X	smac/hal/ssv6006c/ssv6006C_reg.h	13523;"	d
+SET_RG_BT_PABIAS_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	13524;"	d
+SET_RG_BT_RX_ABBCFIX	smac/hal/ssv6006c/ssv6006C_reg.h	13484;"	d
+SET_RG_BT_RX_ABBCTUNE	smac/hal/ssv6006c/ssv6006C_reg.h	13478;"	d
+SET_RG_BT_RX_ABB_BT_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	13486;"	d
+SET_RG_BT_RX_ABB_IDIV3	smac/hal/ssv6006c/ssv6006C_reg.h	13487;"	d
+SET_RG_BT_RX_ABB_N_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	13485;"	d
+SET_RG_BT_RX_ADC_CLOAD	smac/hal/ssv6006c/ssv6006C_reg.h	13635;"	d
+SET_RG_BT_RX_ADC_ICMP	smac/hal/ssv6006c/ssv6006C_reg.h	13633;"	d
+SET_RG_BT_RX_ADC_PSW	smac/hal/ssv6006c/ssv6006C_reg.h	13636;"	d
+SET_RG_BT_RX_ADC_VCMI	smac/hal/ssv6006c/ssv6006C_reg.h	13634;"	d
+SET_RG_BT_RX_DCCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	13984;"	d
+SET_RG_BT_RX_EN_IDACA_COARSE	smac/hal/ssv6006c/ssv6006C_reg.h	13488;"	d
+SET_RG_BT_RX_EN_LOOPA	smac/hal/ssv6006c/ssv6006C_reg.h	13489;"	d
+SET_RG_BT_RX_FILTERI1ST	smac/hal/ssv6006c/ssv6006C_reg.h	13481;"	d
+SET_RG_BT_RX_FILTERI2ND	smac/hal/ssv6006c/ssv6006C_reg.h	13482;"	d
+SET_RG_BT_RX_FILTERI3RD	smac/hal/ssv6006c/ssv6006C_reg.h	13483;"	d
+SET_RG_BT_RX_FILTERI_COARSE	smac/hal/ssv6006c/ssv6006C_reg.h	13480;"	d
+SET_RG_BT_RX_FILTERVCM	smac/hal/ssv6006c/ssv6006C_reg.h	13491;"	d
+SET_RG_BT_RX_HG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	13587;"	d
+SET_RG_BT_RX_HG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	13582;"	d
+SET_RG_BT_RX_HG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	13583;"	d
+SET_RG_BT_RX_HG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	13584;"	d
+SET_RG_BT_RX_HG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	13580;"	d
+SET_RG_BT_RX_HG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	13588;"	d
+SET_RG_BT_RX_HG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	13589;"	d
+SET_RG_BT_RX_HG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	13585;"	d
+SET_RG_BT_RX_HG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	13581;"	d
+SET_RG_BT_RX_HG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	13586;"	d
+SET_RG_BT_RX_HG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	13590;"	d
+SET_RG_BT_RX_LG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	13609;"	d
+SET_RG_BT_RX_LG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	13604;"	d
+SET_RG_BT_RX_LG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	13605;"	d
+SET_RG_BT_RX_LG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	13606;"	d
+SET_RG_BT_RX_LG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	13602;"	d
+SET_RG_BT_RX_LG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	13610;"	d
+SET_RG_BT_RX_LG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	13611;"	d
+SET_RG_BT_RX_LG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	13607;"	d
+SET_RG_BT_RX_LG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	13603;"	d
+SET_RG_BT_RX_LG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	13608;"	d
+SET_RG_BT_RX_LG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	13612;"	d
+SET_RG_BT_RX_MG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	13598;"	d
+SET_RG_BT_RX_MG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	13593;"	d
+SET_RG_BT_RX_MG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	13594;"	d
+SET_RG_BT_RX_MG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	13595;"	d
+SET_RG_BT_RX_MG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	13591;"	d
+SET_RG_BT_RX_MG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	13599;"	d
+SET_RG_BT_RX_MG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	13600;"	d
+SET_RG_BT_RX_MG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	13596;"	d
+SET_RG_BT_RX_MG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	13592;"	d
+SET_RG_BT_RX_MG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	13597;"	d
+SET_RG_BT_RX_MG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	13601;"	d
+SET_RG_BT_RX_OUTVCM	smac/hal/ssv6006c/ssv6006C_reg.h	13492;"	d
+SET_RG_BT_RX_TZ_CMZ_C	smac/hal/ssv6006c/ssv6006C_reg.h	13479;"	d
+SET_RG_BT_RX_TZ_CMZ_R	smac/hal/ssv6006c/ssv6006C_reg.h	13490;"	d
+SET_RG_BT_RX_ULG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	13620;"	d
+SET_RG_BT_RX_ULG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	13615;"	d
+SET_RG_BT_RX_ULG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	13616;"	d
+SET_RG_BT_RX_ULG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	13617;"	d
+SET_RG_BT_RX_ULG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	13613;"	d
+SET_RG_BT_RX_ULG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	13621;"	d
+SET_RG_BT_RX_ULG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	13622;"	d
+SET_RG_BT_RX_ULG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	13618;"	d
+SET_RG_BT_RX_ULG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	13614;"	d
+SET_RG_BT_RX_ULG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	13619;"	d
+SET_RG_BT_RX_ULG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	13623;"	d
+SET_RG_BT_TRX_IF	smac/hal/ssv6006c/ssv6006C_reg.h	14483;"	d
+SET_RG_BT_TXLPF_BOOSTI	smac/hal/ssv6006c/ssv6006C_reg.h	13662;"	d
+SET_RG_BT_TXMOD_GMCELL_FINE	smac/hal/ssv6006c/ssv6006C_reg.h	13514;"	d
+SET_RG_BT_TXPGA_CAPSW	smac/hal/ssv6006c/ssv6006C_reg.h	13511;"	d
+SET_RG_BT_TX_DACI1ST	smac/hal/ssv6006c/ssv6006C_reg.h	13656;"	d
+SET_RG_BT_TX_DACLPF_ICOARSE	smac/hal/ssv6006c/ssv6006C_reg.h	13657;"	d
+SET_RG_BT_TX_DACLPF_IFINE	smac/hal/ssv6006c/ssv6006C_reg.h	13658;"	d
+SET_RG_BT_TX_DACLPF_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	13659;"	d
+SET_RG_BT_TX_DAC_CKEDGE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	13664;"	d
+SET_RG_BT_TX_DAC_IATTN	smac/hal/ssv6006c/ssv6006C_reg.h	13661;"	d
+SET_RG_BT_TX_DAC_IBIAS	smac/hal/ssv6006c/ssv6006C_reg.h	13660;"	d
+SET_RG_BT_TX_DAC_IOFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	13666;"	d
+SET_RG_BT_TX_DAC_OS	smac/hal/ssv6006c/ssv6006C_reg.h	13665;"	d
+SET_RG_BT_TX_DAC_QOFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	13667;"	d
+SET_RG_BT_TX_DAC_RCAL	smac/hal/ssv6006c/ssv6006C_reg.h	13663;"	d
+SET_RG_BT_TX_DIV_VSET	smac/hal/ssv6006c/ssv6006C_reg.h	13512;"	d
+SET_RG_BT_TX_GAIN_OFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	13531;"	d
+SET_RG_BT_TX_LOBUF_VSET	smac/hal/ssv6006c/ssv6006C_reg.h	13513;"	d
+SET_RG_BT_TX_PA_VCAS	smac/hal/ssv6006c/ssv6006C_reg.h	13525;"	d
+SET_RG_BUCK_EN_PSM	include/ssv6200_reg.h	6080;"	d
+SET_RG_BUCK_EN_PSM	smac/hal/ssv6006c/ssv6006C_reg.h	14975;"	d
+SET_RG_BUCK_LEVEL	include/ssv6200_reg.h	6074;"	d
+SET_RG_BUCK_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	14973;"	d
+SET_RG_BUCK_LEVEL_SLP	smac/hal/ssv6006c/ssv6006C_reg.h	15064;"	d
+SET_RG_BUCK_PSM_VTH	include/ssv6200_reg.h	6081;"	d
+SET_RG_BUCK_PSM_VTH	smac/hal/ssv6006c/ssv6006C_reg.h	14976;"	d
+SET_RG_BUCK_RCZERO	smac/hal/ssv6006c/ssv6006C_reg.h	14986;"	d
+SET_RG_BUCK_SLOP	smac/hal/ssv6006c/ssv6006C_reg.h	14987;"	d
+SET_RG_BUCK_VREF_SEL	include/ssv6200_reg.h	6075;"	d
+SET_RG_BUCK_VREF_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	14977;"	d
+SET_RG_BW_HT40	smac/hal/ssv6006c/ssv6006C_reg.h	13374;"	d
+SET_RG_BW_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	13375;"	d
+SET_RG_BYPASS_ACI	include/ssv6200_reg.h	7506;"	d
+SET_RG_BYPASS_ACI	smac/hal/ssv6006c/ssv6006C_reg.h	15093;"	d
+SET_RG_BYPASS_AGC	include/ssv6200_reg.h	7772;"	d
+SET_RG_BYPASS_AUDIO_LWDF	smac/hal/ssv6006c/ssv6006C_reg.h	14615;"	d
+SET_RG_BYPASS_COARSE_FREQ	smac/hal/ssv6006c/ssv6006C_reg.h	15534;"	d
+SET_RG_BYPASS_CPE_MA	include/ssv6200_reg.h	7907;"	d
+SET_RG_BYPASS_CPE_MA	smac/hal/ssv6006c/ssv6006C_reg.h	15550;"	d
+SET_RG_BYPASS_DESCRAMBLER	include/ssv6200_reg.h	7771;"	d
+SET_RG_BYPASS_DESCRAMBLER	smac/hal/ssv6006c/ssv6006C_reg.h	15354;"	d
+SET_RG_CAL_INDEX	smac/hal/ssv6006c/ssv6006C_reg.h	13371;"	d
+SET_RG_CBW_20_40	smac/hal/ssv6006c/ssv6006C_reg.h	14509;"	d
+SET_RG_CCA_BIT_CNT_LMT_RX	include/ssv6200_reg.h	7773;"	d
+SET_RG_CCA_BIT_CNT_TH	smac/hal/ssv6006c/ssv6006C_reg.h	15355;"	d
+SET_RG_CCA_POW_CNT_TH	smac/hal/ssv6006c/ssv6006C_reg.h	15521;"	d
+SET_RG_CCA_POW_SHORT_CNT_LMT	smac/hal/ssv6006c/ssv6006C_reg.h	15522;"	d
+SET_RG_CCA_POW_TH	smac/hal/ssv6006c/ssv6006C_reg.h	15523;"	d
+SET_RG_CCA_PWR_CNT_TH	include/ssv6200_reg.h	7818;"	d
+SET_RG_CCA_PWR_SEL	include/ssv6200_reg.h	7971;"	d
+SET_RG_CCA_PWR_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	15594;"	d
+SET_RG_CCA_PWR_TH_RX	include/ssv6200_reg.h	7817;"	d
+SET_RG_CCA_RE_CHK_BIT_CNT_TH	smac/hal/ssv6006c/ssv6006C_reg.h	15352;"	d
+SET_RG_CCA_SCALE_BF	include/ssv6200_reg.h	7774;"	d
+SET_RG_CCA_SCALE_BF	smac/hal/ssv6006c/ssv6006C_reg.h	15356;"	d
+SET_RG_CCA_XSCOR_AVGPWR_SEL	include/ssv6200_reg.h	7973;"	d
+SET_RG_CCA_XSCOR_AVGPWR_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	15596;"	d
+SET_RG_CCA_XSCOR_PWR_SEL	include/ssv6200_reg.h	7972;"	d
+SET_RG_CCA_XSCOR_PWR_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	15595;"	d
+SET_RG_CCFO_CNT_LMT	smac/hal/ssv6006c/ssv6006C_reg.h	15533;"	d
+SET_RG_CCFO_GAIN_BY2	smac/hal/ssv6006c/ssv6006C_reg.h	15535;"	d
+SET_RG_CCK_TR_KI_T2	smac/hal/ssv6006c/ssv6006C_reg.h	15391;"	d
+SET_RG_CCK_TR_KP_T2	smac/hal/ssv6006c/ssv6006C_reg.h	15392;"	d
+SET_RG_CE_BIT_CNT_LMT	include/ssv6200_reg.h	7808;"	d
+SET_RG_CE_BIT_CNT_LMT	smac/hal/ssv6006c/ssv6006C_reg.h	15384;"	d
+SET_RG_CE_BYPASS_TAP	include/ssv6200_reg.h	7837;"	d
+SET_RG_CE_BYPASS_TAP	smac/hal/ssv6006c/ssv6006C_reg.h	15422;"	d
+SET_RG_CE_CH_MAIN_SET	include/ssv6200_reg.h	7809;"	d
+SET_RG_CE_CH_MAIN_SET	smac/hal/ssv6006c/ssv6006C_reg.h	15385;"	d
+SET_RG_CE_DLY_SEL	include/ssv6200_reg.h	7787;"	d
+SET_RG_CE_DLY_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	15367;"	d
+SET_RG_CE_MU_T1	include/ssv6200_reg.h	7786;"	d
+SET_RG_CE_MU_T1	smac/hal/ssv6006c/ssv6006C_reg.h	15366;"	d
+SET_RG_CE_MU_T2	include/ssv6200_reg.h	7794;"	d
+SET_RG_CE_MU_T2	smac/hal/ssv6006c/ssv6006C_reg.h	15370;"	d
+SET_RG_CE_MU_T3	include/ssv6200_reg.h	7793;"	d
+SET_RG_CE_MU_T3	smac/hal/ssv6006c/ssv6006C_reg.h	15369;"	d
+SET_RG_CE_MU_T4	include/ssv6200_reg.h	7792;"	d
+SET_RG_CE_MU_T4	smac/hal/ssv6006c/ssv6006C_reg.h	15368;"	d
+SET_RG_CE_MU_T5	include/ssv6200_reg.h	7791;"	d
+SET_RG_CE_MU_T6	include/ssv6200_reg.h	7790;"	d
+SET_RG_CE_MU_T7	include/ssv6200_reg.h	7789;"	d
+SET_RG_CE_MU_T8	include/ssv6200_reg.h	7788;"	d
+SET_RG_CE_T2_CNT_LMT	include/ssv6200_reg.h	7785;"	d
+SET_RG_CE_T2_CNT_LMT	smac/hal/ssv6006c/ssv6006C_reg.h	15365;"	d
+SET_RG_CE_T3_CNT_LMT	include/ssv6200_reg.h	7784;"	d
+SET_RG_CE_T4_CNT_LMT	include/ssv6200_reg.h	7783;"	d
+SET_RG_CFR_EN	smac/hal/ssv6006c/ssv6006C_reg.h	14843;"	d
+SET_RG_CFR_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14841;"	d
+SET_RG_CFR_PEAK	smac/hal/ssv6006c/ssv6006C_reg.h	14842;"	d
+SET_RG_CHEST_DD_FACTOR	include/ssv6200_reg.h	7913;"	d
+SET_RG_CHEST_DD_FACTOR	smac/hal/ssv6006c/ssv6006C_reg.h	15553;"	d
+SET_RG_CHIP_CNT_SLICER	include/ssv6200_reg.h	7782;"	d
+SET_RG_CHIP_CNT_SLICER	smac/hal/ssv6006c/ssv6006C_reg.h	15364;"	d
+SET_RG_CHSMTH_COEF	include/ssv6200_reg.h	7911;"	d
+SET_RG_CHSMTH_COEF	smac/hal/ssv6006c/ssv6006C_reg.h	15551;"	d
+SET_RG_CHSMTH_EN	include/ssv6200_reg.h	7912;"	d
+SET_RG_CHSMTH_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15552;"	d
+SET_RG_CH_BW	include/ssv6200_reg.h	7532;"	d
+SET_RG_CH_BW	smac/hal/ssv6006c/ssv6006C_reg.h	15115;"	d
+SET_RG_CH_UPDATE	include/ssv6200_reg.h	7914;"	d
+SET_RG_CH_UPDATE	smac/hal/ssv6006c/ssv6006C_reg.h	15554;"	d
+SET_RG_CLK_320M_INV	smac/hal/ssv6006c/ssv6006C_reg.h	14507;"	d
+SET_RG_CLK_RTC_SW	smac/hal/ssv6006c/ssv6006C_reg.h	15016;"	d
+SET_RG_CLK_SAR_SEL	include/ssv6200_reg.h	8270;"	d
+SET_RG_CLK_SAR_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	13642;"	d
+SET_RG_CLOCK_BF_MUAL	smac/hal/ssv6006c/ssv6006C_reg.h	14961;"	d
+SET_RG_CNT_CCA_LMT	include/ssv6200_reg.h	7770;"	d
+SET_RG_CNT_CCA_RE_CHK_LMT	smac/hal/ssv6006c/ssv6006C_reg.h	15353;"	d
+SET_RG_CONTINUOUS_DATA	include/ssv6200_reg.h	7548;"	d
+SET_RG_CONTINUOUS_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	15132;"	d
+SET_RG_CONTINUOUS_DATA_11GN	include/ssv6200_reg.h	7845;"	d
+SET_RG_COR_SEL	include/ssv6200_reg.h	7967;"	d
+SET_RG_COR_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	15592;"	d
+SET_RG_CPE_SEL_16QAM	smac/hal/ssv6006c/ssv6006C_reg.h	15547;"	d
+SET_RG_CPE_SEL_64QAM	smac/hal/ssv6006c/ssv6006C_reg.h	15546;"	d
+SET_RG_CPE_SEL_BPSK	smac/hal/ssv6006c/ssv6006C_reg.h	15549;"	d
+SET_RG_CPE_SEL_QPSK	smac/hal/ssv6006c/ssv6006C_reg.h	15548;"	d
+SET_RG_CR_BIT_CNT_LMT	include/ssv6200_reg.h	7811;"	d
+SET_RG_CR_BIT_CNT_LMT	smac/hal/ssv6006c/ssv6006C_reg.h	15387;"	d
+SET_RG_CR_CNT_UPDATE	include/ssv6200_reg.h	7905;"	d
+SET_RG_CR_CNT_UPDATE	smac/hal/ssv6006c/ssv6006C_reg.h	15544;"	d
+SET_RG_CR_CNT_UPDATE_SGI	smac/hal/ssv6006c/ssv6006C_reg.h	15542;"	d
+SET_RG_CR_KI_T1	include/ssv6200_reg.h	7780;"	d
+SET_RG_CR_KI_T1	smac/hal/ssv6006c/ssv6006C_reg.h	15362;"	d
+SET_RG_CR_KP_T1	include/ssv6200_reg.h	7781;"	d
+SET_RG_CR_KP_T1	smac/hal/ssv6006c/ssv6006C_reg.h	15363;"	d
+SET_RG_CR_LPF_KI_G	include/ssv6200_reg.h	7862;"	d
+SET_RG_CR_LPF_KI_GN	smac/hal/ssv6006c/ssv6006C_reg.h	15455;"	d
+SET_RG_DACI1ST	include/ssv6200_reg.h	8272;"	d
+SET_RG_DAC_DBG_MODE	include/ssv6200_reg.h	7553;"	d
+SET_RG_DAC_DCEN	include/ssv6200_reg.h	7559;"	d
+SET_RG_DAC_DCI	include/ssv6200_reg.h	7561;"	d
+SET_RG_DAC_DCQ	include/ssv6200_reg.h	7560;"	d
+SET_RG_DAC_DC_I	smac/hal/ssv6006c/ssv6006C_reg.h	14511;"	d
+SET_RG_DAC_DC_Q	smac/hal/ssv6006c/ssv6006C_reg.h	14510;"	d
+SET_RG_DAC_EN_MAN	include/ssv6200_reg.h	7663;"	d
+SET_RG_DAC_FALL_TIME	include/ssv6200_reg.h	7675;"	d
+SET_RG_DAC_I_SET	include/ssv6200_reg.h	7662;"	d
+SET_RG_DAC_I_SET	smac/hal/ssv6006c/ssv6006C_reg.h	14514;"	d
+SET_RG_DAC_LBK_EDGE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	15087;"	d
+SET_RG_DAC_MAN_I_EN	include/ssv6200_reg.h	7666;"	d
+SET_RG_DAC_MAN_I_EN	smac/hal/ssv6006c/ssv6006C_reg.h	14515;"	d
+SET_RG_DAC_MAN_Q_EN	include/ssv6200_reg.h	7665;"	d
+SET_RG_DAC_MAN_Q_EN	smac/hal/ssv6006c/ssv6006C_reg.h	14513;"	d
+SET_RG_DAC_Q_SET	include/ssv6200_reg.h	7661;"	d
+SET_RG_DAC_Q_SET	smac/hal/ssv6006c/ssv6006C_reg.h	14512;"	d
+SET_RG_DAC_RISE_TIME	include/ssv6200_reg.h	7671;"	d
+SET_RG_DAC_SGN_SWAP	include/ssv6200_reg.h	7554;"	d
+SET_RG_DAGC_CNT_TH	include/ssv6200_reg.h	7962;"	d
+SET_RG_DAGC_CNT_TH	smac/hal/ssv6006c/ssv6006C_reg.h	15586;"	d
+SET_RG_DATA_SEL	include/ssv6200_reg.h	7549;"	d
+SET_RG_DATA_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	15133;"	d
+SET_RG_DBIST_MODE_16	include/ssv6200_reg.h	7701;"	d
+SET_RG_DBIST_MODE_64	include/ssv6200_reg.h	7939;"	d
+SET_RG_DBIST_MODE_80	include/ssv6200_reg.h	7932;"	d
+SET_RG_DCDC_CLK	smac/hal/ssv6006c/ssv6006C_reg.h	14985;"	d
+SET_RG_DCDC_MODE	include/ssv6200_reg.h	6079;"	d
+SET_RG_DCDC_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	14971;"	d
+SET_RG_DCDC_MODE_SLP	smac/hal/ssv6006c/ssv6006C_reg.h	15062;"	d
+SET_RG_DCDC_PULLLOW_CON	smac/hal/ssv6006c/ssv6006C_reg.h	14980;"	d
+SET_RG_DCDC_RES2_CON	smac/hal/ssv6006c/ssv6006C_reg.h	14981;"	d
+SET_RG_DCDC_RES_CON	smac/hal/ssv6006c/ssv6006C_reg.h	14982;"	d
+SET_RG_DC_RM_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	15204;"	d
+SET_RG_DC_RM_LEAKY_FACTOR_T1	smac/hal/ssv6006c/ssv6006C_reg.h	15207;"	d
+SET_RG_DC_RM_LEAKY_FACTOR_T2	smac/hal/ssv6006c/ssv6006C_reg.h	15206;"	d
+SET_RG_DC_RM_LEAKY_FACTOR_T3	smac/hal/ssv6006c/ssv6006C_reg.h	15205;"	d
+SET_RG_DEBUG_SEL	include/ssv6200_reg.h	7974;"	d
+SET_RG_DEBUG_SEL_11B_RX	smac/hal/ssv6006c/ssv6006C_reg.h	15424;"	d
+SET_RG_DEBUG_SEL_11B_TX	smac/hal/ssv6006c/ssv6006C_reg.h	15348;"	d
+SET_RG_DEBUG_SEL_11GN_RX	smac/hal/ssv6006c/ssv6006C_reg.h	15597;"	d
+SET_RG_DEBUG_SEL_11GN_TX	smac/hal/ssv6006c/ssv6006C_reg.h	15444;"	d
+SET_RG_DES_MAN_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15140;"	d
+SET_RG_DES_RATE	smac/hal/ssv6006c/ssv6006C_reg.h	15139;"	d
+SET_RG_DES_SPD	include/ssv6200_reg.h	7762;"	d
+SET_RG_DICMP	include/ssv6200_reg.h	8264;"	d
+SET_RG_DIOP	include/ssv6200_reg.h	8265;"	d
+SET_RG_DIS_DAC_OFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	14506;"	d
+SET_RG_DLDO_BOOST_IQ	include/ssv6200_reg.h	6073;"	d
+SET_RG_DLDO_BOOST_IQ	smac/hal/ssv6006c/ssv6006C_reg.h	14974;"	d
+SET_RG_DLDO_LEVEL	include/ssv6200_reg.h	6072;"	d
+SET_RG_DLDO_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	14972;"	d
+SET_RG_DLDO_LEVEL_SLP	smac/hal/ssv6006c/ssv6006C_reg.h	15063;"	d
+SET_RG_DO_NOT_CHECK_L_RATE	include/ssv6200_reg.h	7917;"	d
+SET_RG_DO_NOT_CHECK_L_RATE	smac/hal/ssv6006c/ssv6006C_reg.h	15557;"	d
+SET_RG_DPD_020_GAIN	include/ssv6200_reg.h	8054;"	d
+SET_RG_DPD_020_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14859;"	d
+SET_RG_DPD_020_PH	include/ssv6200_reg.h	8080;"	d
+SET_RG_DPD_020_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14885;"	d
+SET_RG_DPD_040_GAIN	include/ssv6200_reg.h	8055;"	d
+SET_RG_DPD_040_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14860;"	d
+SET_RG_DPD_040_PH	include/ssv6200_reg.h	8081;"	d
+SET_RG_DPD_040_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14886;"	d
+SET_RG_DPD_060_GAIN	include/ssv6200_reg.h	8056;"	d
+SET_RG_DPD_060_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14861;"	d
+SET_RG_DPD_060_PH	include/ssv6200_reg.h	8082;"	d
+SET_RG_DPD_060_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14887;"	d
+SET_RG_DPD_080_GAIN	include/ssv6200_reg.h	8057;"	d
+SET_RG_DPD_080_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14862;"	d
+SET_RG_DPD_080_PH	include/ssv6200_reg.h	8083;"	d
+SET_RG_DPD_080_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14888;"	d
+SET_RG_DPD_0A0_GAIN	include/ssv6200_reg.h	8058;"	d
+SET_RG_DPD_0A0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14863;"	d
+SET_RG_DPD_0A0_PH	include/ssv6200_reg.h	8084;"	d
+SET_RG_DPD_0A0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14889;"	d
+SET_RG_DPD_0C0_GAIN	include/ssv6200_reg.h	8059;"	d
+SET_RG_DPD_0C0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14864;"	d
+SET_RG_DPD_0C0_PH	include/ssv6200_reg.h	8085;"	d
+SET_RG_DPD_0C0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14890;"	d
+SET_RG_DPD_0D0_GAIN	include/ssv6200_reg.h	8060;"	d
+SET_RG_DPD_0D0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14865;"	d
+SET_RG_DPD_0D0_PH	include/ssv6200_reg.h	8086;"	d
+SET_RG_DPD_0D0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14891;"	d
+SET_RG_DPD_0E0_GAIN	include/ssv6200_reg.h	8061;"	d
+SET_RG_DPD_0E0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14866;"	d
+SET_RG_DPD_0E0_PH	include/ssv6200_reg.h	8087;"	d
+SET_RG_DPD_0E0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14892;"	d
+SET_RG_DPD_0F0_GAIN	include/ssv6200_reg.h	8062;"	d
+SET_RG_DPD_0F0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14867;"	d
+SET_RG_DPD_0F0_PH	include/ssv6200_reg.h	8088;"	d
+SET_RG_DPD_0F0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14893;"	d
+SET_RG_DPD_100_GAIN	include/ssv6200_reg.h	8063;"	d
+SET_RG_DPD_100_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14868;"	d
+SET_RG_DPD_100_PH	include/ssv6200_reg.h	8089;"	d
+SET_RG_DPD_100_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14894;"	d
+SET_RG_DPD_110_GAIN	include/ssv6200_reg.h	8064;"	d
+SET_RG_DPD_110_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14869;"	d
+SET_RG_DPD_110_PH	include/ssv6200_reg.h	8090;"	d
+SET_RG_DPD_110_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14895;"	d
+SET_RG_DPD_120_GAIN	include/ssv6200_reg.h	8065;"	d
+SET_RG_DPD_120_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14870;"	d
+SET_RG_DPD_120_PH	include/ssv6200_reg.h	8091;"	d
+SET_RG_DPD_120_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14896;"	d
+SET_RG_DPD_130_GAIN	include/ssv6200_reg.h	8066;"	d
+SET_RG_DPD_130_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14871;"	d
+SET_RG_DPD_130_PH	include/ssv6200_reg.h	8092;"	d
+SET_RG_DPD_130_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14897;"	d
+SET_RG_DPD_140_GAIN	include/ssv6200_reg.h	8067;"	d
+SET_RG_DPD_140_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14872;"	d
+SET_RG_DPD_140_PH	include/ssv6200_reg.h	8093;"	d
+SET_RG_DPD_140_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14898;"	d
+SET_RG_DPD_150_GAIN	include/ssv6200_reg.h	8068;"	d
+SET_RG_DPD_150_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14873;"	d
+SET_RG_DPD_150_PH	include/ssv6200_reg.h	8094;"	d
+SET_RG_DPD_150_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14899;"	d
+SET_RG_DPD_160_GAIN	include/ssv6200_reg.h	8069;"	d
+SET_RG_DPD_160_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14874;"	d
+SET_RG_DPD_160_PH	include/ssv6200_reg.h	8095;"	d
+SET_RG_DPD_160_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14900;"	d
+SET_RG_DPD_170_GAIN	include/ssv6200_reg.h	8070;"	d
+SET_RG_DPD_170_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14875;"	d
+SET_RG_DPD_170_PH	include/ssv6200_reg.h	8096;"	d
+SET_RG_DPD_170_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14901;"	d
+SET_RG_DPD_180_GAIN	include/ssv6200_reg.h	8071;"	d
+SET_RG_DPD_180_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14876;"	d
+SET_RG_DPD_180_PH	include/ssv6200_reg.h	8097;"	d
+SET_RG_DPD_180_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14902;"	d
+SET_RG_DPD_190_GAIN	include/ssv6200_reg.h	8072;"	d
+SET_RG_DPD_190_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14877;"	d
+SET_RG_DPD_190_PH	include/ssv6200_reg.h	8098;"	d
+SET_RG_DPD_190_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14903;"	d
+SET_RG_DPD_1A0_GAIN	include/ssv6200_reg.h	8073;"	d
+SET_RG_DPD_1A0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14878;"	d
+SET_RG_DPD_1A0_PH	include/ssv6200_reg.h	8099;"	d
+SET_RG_DPD_1A0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14904;"	d
+SET_RG_DPD_1B0_GAIN	include/ssv6200_reg.h	8074;"	d
+SET_RG_DPD_1B0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14879;"	d
+SET_RG_DPD_1B0_PH	include/ssv6200_reg.h	8100;"	d
+SET_RG_DPD_1B0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14905;"	d
+SET_RG_DPD_1C0_GAIN	include/ssv6200_reg.h	8075;"	d
+SET_RG_DPD_1C0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14880;"	d
+SET_RG_DPD_1C0_PH	include/ssv6200_reg.h	8101;"	d
+SET_RG_DPD_1C0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14906;"	d
+SET_RG_DPD_1D0_GAIN	include/ssv6200_reg.h	8076;"	d
+SET_RG_DPD_1D0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14881;"	d
+SET_RG_DPD_1D0_PH	include/ssv6200_reg.h	8102;"	d
+SET_RG_DPD_1D0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14907;"	d
+SET_RG_DPD_1E0_GAIN	include/ssv6200_reg.h	8077;"	d
+SET_RG_DPD_1E0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14882;"	d
+SET_RG_DPD_1E0_PH	include/ssv6200_reg.h	8103;"	d
+SET_RG_DPD_1E0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14908;"	d
+SET_RG_DPD_1F0_GAIN	include/ssv6200_reg.h	8078;"	d
+SET_RG_DPD_1F0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14883;"	d
+SET_RG_DPD_1F0_PH	include/ssv6200_reg.h	8104;"	d
+SET_RG_DPD_1F0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14909;"	d
+SET_RG_DPD_200_GAIN	include/ssv6200_reg.h	8079;"	d
+SET_RG_DPD_200_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14884;"	d
+SET_RG_DPD_200_PH	include/ssv6200_reg.h	8105;"	d
+SET_RG_DPD_200_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14910;"	d
+SET_RG_DPD_5100_020_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14623;"	d
+SET_RG_DPD_5100_020_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14649;"	d
+SET_RG_DPD_5100_040_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14624;"	d
+SET_RG_DPD_5100_040_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14650;"	d
+SET_RG_DPD_5100_060_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14625;"	d
+SET_RG_DPD_5100_060_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14651;"	d
+SET_RG_DPD_5100_080_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14626;"	d
+SET_RG_DPD_5100_080_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14652;"	d
+SET_RG_DPD_5100_0A0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14627;"	d
+SET_RG_DPD_5100_0A0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14653;"	d
+SET_RG_DPD_5100_0C0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14628;"	d
+SET_RG_DPD_5100_0C0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14654;"	d
+SET_RG_DPD_5100_0D0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14629;"	d
+SET_RG_DPD_5100_0D0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14655;"	d
+SET_RG_DPD_5100_0E0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14630;"	d
+SET_RG_DPD_5100_0E0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14656;"	d
+SET_RG_DPD_5100_0F0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14631;"	d
+SET_RG_DPD_5100_0F0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14657;"	d
+SET_RG_DPD_5100_100_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14632;"	d
+SET_RG_DPD_5100_100_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14658;"	d
+SET_RG_DPD_5100_110_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14633;"	d
+SET_RG_DPD_5100_110_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14659;"	d
+SET_RG_DPD_5100_120_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14634;"	d
+SET_RG_DPD_5100_120_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14660;"	d
+SET_RG_DPD_5100_130_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14635;"	d
+SET_RG_DPD_5100_130_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14661;"	d
+SET_RG_DPD_5100_140_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14636;"	d
+SET_RG_DPD_5100_140_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14662;"	d
+SET_RG_DPD_5100_150_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14637;"	d
+SET_RG_DPD_5100_150_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14663;"	d
+SET_RG_DPD_5100_160_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14638;"	d
+SET_RG_DPD_5100_160_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14664;"	d
+SET_RG_DPD_5100_170_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14639;"	d
+SET_RG_DPD_5100_170_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14665;"	d
+SET_RG_DPD_5100_180_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14640;"	d
+SET_RG_DPD_5100_180_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14666;"	d
+SET_RG_DPD_5100_190_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14641;"	d
+SET_RG_DPD_5100_190_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14667;"	d
+SET_RG_DPD_5100_1A0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14642;"	d
+SET_RG_DPD_5100_1A0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14668;"	d
+SET_RG_DPD_5100_1B0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14643;"	d
+SET_RG_DPD_5100_1B0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14669;"	d
+SET_RG_DPD_5100_1C0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14644;"	d
+SET_RG_DPD_5100_1C0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14670;"	d
+SET_RG_DPD_5100_1D0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14645;"	d
+SET_RG_DPD_5100_1D0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14671;"	d
+SET_RG_DPD_5100_1E0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14646;"	d
+SET_RG_DPD_5100_1E0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14672;"	d
+SET_RG_DPD_5100_1F0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14647;"	d
+SET_RG_DPD_5100_1F0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14673;"	d
+SET_RG_DPD_5100_200_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14648;"	d
+SET_RG_DPD_5100_200_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14674;"	d
+SET_RG_DPD_5500_020_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14675;"	d
+SET_RG_DPD_5500_020_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14701;"	d
+SET_RG_DPD_5500_040_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14676;"	d
+SET_RG_DPD_5500_040_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14702;"	d
+SET_RG_DPD_5500_060_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14677;"	d
+SET_RG_DPD_5500_060_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14703;"	d
+SET_RG_DPD_5500_080_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14678;"	d
+SET_RG_DPD_5500_080_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14704;"	d
+SET_RG_DPD_5500_0A0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14679;"	d
+SET_RG_DPD_5500_0A0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14705;"	d
+SET_RG_DPD_5500_0C0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14680;"	d
+SET_RG_DPD_5500_0C0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14706;"	d
+SET_RG_DPD_5500_0D0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14681;"	d
+SET_RG_DPD_5500_0D0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14707;"	d
+SET_RG_DPD_5500_0E0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14682;"	d
+SET_RG_DPD_5500_0E0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14708;"	d
+SET_RG_DPD_5500_0F0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14683;"	d
+SET_RG_DPD_5500_0F0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14709;"	d
+SET_RG_DPD_5500_100_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14684;"	d
+SET_RG_DPD_5500_100_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14710;"	d
+SET_RG_DPD_5500_110_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14685;"	d
+SET_RG_DPD_5500_110_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14711;"	d
+SET_RG_DPD_5500_120_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14686;"	d
+SET_RG_DPD_5500_120_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14712;"	d
+SET_RG_DPD_5500_130_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14687;"	d
+SET_RG_DPD_5500_130_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14713;"	d
+SET_RG_DPD_5500_140_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14688;"	d
+SET_RG_DPD_5500_140_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14714;"	d
+SET_RG_DPD_5500_150_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14689;"	d
+SET_RG_DPD_5500_150_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14715;"	d
+SET_RG_DPD_5500_160_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14690;"	d
+SET_RG_DPD_5500_160_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14716;"	d
+SET_RG_DPD_5500_170_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14691;"	d
+SET_RG_DPD_5500_170_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14717;"	d
+SET_RG_DPD_5500_180_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14692;"	d
+SET_RG_DPD_5500_180_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14718;"	d
+SET_RG_DPD_5500_190_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14693;"	d
+SET_RG_DPD_5500_190_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14719;"	d
+SET_RG_DPD_5500_1A0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14694;"	d
+SET_RG_DPD_5500_1A0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14720;"	d
+SET_RG_DPD_5500_1B0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14695;"	d
+SET_RG_DPD_5500_1B0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14721;"	d
+SET_RG_DPD_5500_1C0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14696;"	d
+SET_RG_DPD_5500_1C0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14722;"	d
+SET_RG_DPD_5500_1D0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14697;"	d
+SET_RG_DPD_5500_1D0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14723;"	d
+SET_RG_DPD_5500_1E0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14698;"	d
+SET_RG_DPD_5500_1E0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14724;"	d
+SET_RG_DPD_5500_1F0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14699;"	d
+SET_RG_DPD_5500_1F0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14725;"	d
+SET_RG_DPD_5500_200_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14700;"	d
+SET_RG_DPD_5500_200_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14726;"	d
+SET_RG_DPD_5700_020_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14727;"	d
+SET_RG_DPD_5700_020_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14753;"	d
+SET_RG_DPD_5700_040_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14728;"	d
+SET_RG_DPD_5700_040_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14754;"	d
+SET_RG_DPD_5700_060_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14729;"	d
+SET_RG_DPD_5700_060_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14755;"	d
+SET_RG_DPD_5700_080_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14730;"	d
+SET_RG_DPD_5700_080_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14756;"	d
+SET_RG_DPD_5700_0A0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14731;"	d
+SET_RG_DPD_5700_0A0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14757;"	d
+SET_RG_DPD_5700_0C0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14732;"	d
+SET_RG_DPD_5700_0C0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14758;"	d
+SET_RG_DPD_5700_0D0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14733;"	d
+SET_RG_DPD_5700_0D0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14759;"	d
+SET_RG_DPD_5700_0E0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14734;"	d
+SET_RG_DPD_5700_0E0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14760;"	d
+SET_RG_DPD_5700_0F0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14735;"	d
+SET_RG_DPD_5700_0F0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14761;"	d
+SET_RG_DPD_5700_100_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14736;"	d
+SET_RG_DPD_5700_100_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14762;"	d
+SET_RG_DPD_5700_110_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14737;"	d
+SET_RG_DPD_5700_110_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14763;"	d
+SET_RG_DPD_5700_120_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14738;"	d
+SET_RG_DPD_5700_120_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14764;"	d
+SET_RG_DPD_5700_130_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14739;"	d
+SET_RG_DPD_5700_130_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14765;"	d
+SET_RG_DPD_5700_140_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14740;"	d
+SET_RG_DPD_5700_140_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14766;"	d
+SET_RG_DPD_5700_150_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14741;"	d
+SET_RG_DPD_5700_150_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14767;"	d
+SET_RG_DPD_5700_160_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14742;"	d
+SET_RG_DPD_5700_160_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14768;"	d
+SET_RG_DPD_5700_170_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14743;"	d
+SET_RG_DPD_5700_170_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14769;"	d
+SET_RG_DPD_5700_180_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14744;"	d
+SET_RG_DPD_5700_180_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14770;"	d
+SET_RG_DPD_5700_190_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14745;"	d
+SET_RG_DPD_5700_190_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14771;"	d
+SET_RG_DPD_5700_1A0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14746;"	d
+SET_RG_DPD_5700_1A0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14772;"	d
+SET_RG_DPD_5700_1B0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14747;"	d
+SET_RG_DPD_5700_1B0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14773;"	d
+SET_RG_DPD_5700_1C0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14748;"	d
+SET_RG_DPD_5700_1C0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14774;"	d
+SET_RG_DPD_5700_1D0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14749;"	d
+SET_RG_DPD_5700_1D0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14775;"	d
+SET_RG_DPD_5700_1E0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14750;"	d
+SET_RG_DPD_5700_1E0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14776;"	d
+SET_RG_DPD_5700_1F0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14751;"	d
+SET_RG_DPD_5700_1F0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14777;"	d
+SET_RG_DPD_5700_200_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14752;"	d
+SET_RG_DPD_5700_200_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14778;"	d
+SET_RG_DPD_5900_020_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14779;"	d
+SET_RG_DPD_5900_020_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14805;"	d
+SET_RG_DPD_5900_040_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14780;"	d
+SET_RG_DPD_5900_040_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14806;"	d
+SET_RG_DPD_5900_060_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14781;"	d
+SET_RG_DPD_5900_060_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14807;"	d
+SET_RG_DPD_5900_080_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14782;"	d
+SET_RG_DPD_5900_080_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14808;"	d
+SET_RG_DPD_5900_0A0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14783;"	d
+SET_RG_DPD_5900_0A0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14809;"	d
+SET_RG_DPD_5900_0C0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14784;"	d
+SET_RG_DPD_5900_0C0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14810;"	d
+SET_RG_DPD_5900_0D0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14785;"	d
+SET_RG_DPD_5900_0D0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14811;"	d
+SET_RG_DPD_5900_0E0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14786;"	d
+SET_RG_DPD_5900_0E0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14812;"	d
+SET_RG_DPD_5900_0F0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14787;"	d
+SET_RG_DPD_5900_0F0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14813;"	d
+SET_RG_DPD_5900_100_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14788;"	d
+SET_RG_DPD_5900_100_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14814;"	d
+SET_RG_DPD_5900_110_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14789;"	d
+SET_RG_DPD_5900_110_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14815;"	d
+SET_RG_DPD_5900_120_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14790;"	d
+SET_RG_DPD_5900_120_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14816;"	d
+SET_RG_DPD_5900_130_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14791;"	d
+SET_RG_DPD_5900_130_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14817;"	d
+SET_RG_DPD_5900_140_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14792;"	d
+SET_RG_DPD_5900_140_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14818;"	d
+SET_RG_DPD_5900_150_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14793;"	d
+SET_RG_DPD_5900_150_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14819;"	d
+SET_RG_DPD_5900_160_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14794;"	d
+SET_RG_DPD_5900_160_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14820;"	d
+SET_RG_DPD_5900_170_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14795;"	d
+SET_RG_DPD_5900_170_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14821;"	d
+SET_RG_DPD_5900_180_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14796;"	d
+SET_RG_DPD_5900_180_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14822;"	d
+SET_RG_DPD_5900_190_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14797;"	d
+SET_RG_DPD_5900_190_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14823;"	d
+SET_RG_DPD_5900_1A0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14798;"	d
+SET_RG_DPD_5900_1A0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14824;"	d
+SET_RG_DPD_5900_1B0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14799;"	d
+SET_RG_DPD_5900_1B0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14825;"	d
+SET_RG_DPD_5900_1C0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14800;"	d
+SET_RG_DPD_5900_1C0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14826;"	d
+SET_RG_DPD_5900_1D0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14801;"	d
+SET_RG_DPD_5900_1D0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14827;"	d
+SET_RG_DPD_5900_1E0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14802;"	d
+SET_RG_DPD_5900_1E0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14828;"	d
+SET_RG_DPD_5900_1F0_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14803;"	d
+SET_RG_DPD_5900_1F0_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14829;"	d
+SET_RG_DPD_5900_200_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14804;"	d
+SET_RG_DPD_5900_200_PH	smac/hal/ssv6006c/ssv6006C_reg.h	14830;"	d
+SET_RG_DPD_AM_EN	include/ssv6200_reg.h	8051;"	d
+SET_RG_DPD_AM_EN	smac/hal/ssv6006c/ssv6006C_reg.h	14856;"	d
+SET_RG_DPD_BB_SCALE_2500	smac/hal/ssv6006c/ssv6006C_reg.h	14915;"	d
+SET_RG_DPD_BB_SCALE_5100	smac/hal/ssv6006c/ssv6006C_reg.h	14914;"	d
+SET_RG_DPD_BB_SCALE_5500	smac/hal/ssv6006c/ssv6006C_reg.h	14913;"	d
+SET_RG_DPD_BB_SCALE_5700	smac/hal/ssv6006c/ssv6006C_reg.h	14912;"	d
+SET_RG_DPD_BB_SCALE_5900	smac/hal/ssv6006c/ssv6006C_reg.h	14911;"	d
+SET_RG_DPD_GAIN_EST_EN	include/ssv6200_reg.h	8019;"	d
+SET_RG_DPD_GAIN_EST_X0	include/ssv6200_reg.h	8109;"	d
+SET_RG_DPD_GAIN_EST_Y0	include/ssv6200_reg.h	8106;"	d
+SET_RG_DPD_GAIN_EST_Y1	include/ssv6200_reg.h	8107;"	d
+SET_RG_DPD_LOOP_GAIN	include/ssv6200_reg.h	8108;"	d
+SET_RG_DPD_PM_AMSEL	include/ssv6200_reg.h	8053;"	d
+SET_RG_DPD_PM_AMSEL	smac/hal/ssv6006c/ssv6006C_reg.h	14858;"	d
+SET_RG_DPD_PM_EN	include/ssv6200_reg.h	8052;"	d
+SET_RG_DPD_PM_EN	smac/hal/ssv6006c/ssv6006C_reg.h	14857;"	d
+SET_RG_DPLL_CLK320BY2	smac/hal/ssv6006c/ssv6006C_reg.h	14508;"	d
+SET_RG_DPL_MOD_ORDER	include/ssv6200_reg.h	8299;"	d
+SET_RG_DPL_MOD_ORDER	smac/hal/ssv6006c/ssv6006C_reg.h	15041;"	d
+SET_RG_DPL_RFCTRL_CH	include/ssv6200_reg.h	8426;"	d
+SET_RG_DPL_RFCTRL_CH	smac/hal/ssv6006c/ssv6006C_reg.h	15061;"	d
+SET_RG_DPL_RFCTRL_F	include/ssv6200_reg.h	8430;"	d
+SET_RG_DPL_RFCTRL_F	smac/hal/ssv6006c/ssv6006C_reg.h	15060;"	d
+SET_RG_DPL_SETTLING_TIMMER	smac/hal/ssv6006c/ssv6006C_reg.h	14965;"	d
+SET_RG_DP_ADC320_DIVBY2_BT	smac/hal/ssv6006c/ssv6006C_reg.h	15038;"	d
+SET_RG_DP_ADC320_DIVBY2_WF	smac/hal/ssv6006c/ssv6006C_reg.h	15039;"	d
+SET_RG_DP_AUTOMAP_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15022;"	d
+SET_RG_DP_BBPLL_BP	include/ssv6200_reg.h	8353;"	d
+SET_RG_DP_BBPLL_BP	smac/hal/ssv6006c/ssv6006C_reg.h	15034;"	d
+SET_RG_DP_BBPLL_BS	include/ssv6200_reg.h	8369;"	d
+SET_RG_DP_BBPLL_BS	smac/hal/ssv6006c/ssv6006C_reg.h	15058;"	d
+SET_RG_DP_BBPLL_ICP	include/ssv6200_reg.h	8354;"	d
+SET_RG_DP_BBPLL_ICP	smac/hal/ssv6006c/ssv6006C_reg.h	15047;"	d
+SET_RG_DP_BBPLL_IDUAL	include/ssv6200_reg.h	8355;"	d
+SET_RG_DP_BBPLL_IDUAL	smac/hal/ssv6006c/ssv6006C_reg.h	15048;"	d
+SET_RG_DP_BBPLL_OD_TEST	include/ssv6200_reg.h	8356;"	d
+SET_RG_DP_BBPLL_PD	include/ssv6200_reg.h	8357;"	d
+SET_RG_DP_BBPLL_PD	smac/hal/ssv6006c/ssv6006C_reg.h	15033;"	d
+SET_RG_DP_BBPLL_PFD_DLY	include/ssv6200_reg.h	8359;"	d
+SET_RG_DP_BBPLL_PFD_DLY	smac/hal/ssv6006c/ssv6006C_reg.h	15052;"	d
+SET_RG_DP_BBPLL_SDM_EDGE	include/ssv6200_reg.h	8362;"	d
+SET_RG_DP_BBPLL_SDM_EDGE	smac/hal/ssv6006c/ssv6006C_reg.h	15059;"	d
+SET_RG_DP_BBPLL_TESTSEL	include/ssv6200_reg.h	8358;"	d
+SET_RG_DP_BBPLL_TESTSEL	smac/hal/ssv6006c/ssv6006C_reg.h	15046;"	d
+SET_RG_DP_CK320BY2	include/ssv6200_reg.h	8351;"	d
+SET_RG_DP_CP_IOST	smac/hal/ssv6006c/ssv6006C_reg.h	15050;"	d
+SET_RG_DP_CP_IOSTPOL	smac/hal/ssv6006c/ssv6006C_reg.h	15049;"	d
+SET_RG_DP_DAC320_DIVBY2	smac/hal/ssv6006c/ssv6006C_reg.h	15037;"	d
+SET_RG_DP_FODIV	include/ssv6200_reg.h	8363;"	d
+SET_RG_DP_FODIV	smac/hal/ssv6006c/ssv6006C_reg.h	15043;"	d
+SET_RG_DP_FREF_DOUB	smac/hal/ssv6006c/ssv6006C_reg.h	15036;"	d
+SET_RG_DP_LDO_LEVEL	include/ssv6200_reg.h	8166;"	d
+SET_RG_DP_LDO_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	15020;"	d
+SET_RG_DP_OD_TEST	include/ssv6200_reg.h	8352;"	d
+SET_RG_DP_OD_TEST	smac/hal/ssv6006c/ssv6006C_reg.h	15045;"	d
+SET_RG_DP_PFD_PFDSEL	smac/hal/ssv6006c/ssv6006C_reg.h	15051;"	d
+SET_RG_DP_REFDIV	include/ssv6200_reg.h	8364;"	d
+SET_RG_DP_REFDIV	smac/hal/ssv6006c/ssv6006C_reg.h	15042;"	d
+SET_RG_DP_RHP	include/ssv6200_reg.h	8361;"	d
+SET_RG_DP_RHP	smac/hal/ssv6006c/ssv6006C_reg.h	15054;"	d
+SET_RG_DP_RP	include/ssv6200_reg.h	8360;"	d
+SET_RG_DP_RP	smac/hal/ssv6006c/ssv6006C_reg.h	15053;"	d
+SET_RG_DP_VT_TH_HI	include/ssv6200_reg.h	8349;"	d
+SET_RG_DP_VT_TH_HI	smac/hal/ssv6006c/ssv6006C_reg.h	15056;"	d
+SET_RG_DP_VT_TH_LO	include/ssv6200_reg.h	8350;"	d
+SET_RG_DP_VT_TH_LO	smac/hal/ssv6006c/ssv6006C_reg.h	15057;"	d
+SET_RG_DP_XTAL_FREQ	smac/hal/ssv6006c/ssv6006C_reg.h	15032;"	d
+SET_RG_EDCCA_AVG_T	smac/hal/ssv6006c/ssv6006C_reg.h	15215;"	d
+SET_RG_EDCCA_STAT_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15216;"	d
+SET_RG_EN_AAC5GB_MXPDSW	smac/hal/ssv6006c/ssv6006C_reg.h	14304;"	d
+SET_RG_EN_AAC5GB_RPPDSW	smac/hal/ssv6006c/ssv6006C_reg.h	14305;"	d
+SET_RG_EN_AAC5GB_VOPDSW	smac/hal/ssv6006c/ssv6006C_reg.h	14303;"	d
+SET_RG_EN_ADC	include/ssv6200_reg.h	8134;"	d
+SET_RG_EN_ADC_320M	smac/hal/ssv6006c/ssv6006C_reg.h	15023;"	d
+SET_RG_EN_CLK_960MBY13_UART	include/ssv6200_reg.h	8141;"	d
+SET_RG_EN_DLDO_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	14947;"	d
+SET_RG_EN_DLDO_BYP_AUTO	smac/hal/ssv6006c/ssv6006C_reg.h	15068;"	d
+SET_RG_EN_DLDO_HALF_IQ	smac/hal/ssv6006c/ssv6006C_reg.h	14948;"	d
+SET_RG_EN_DLDO_HALF_IQ_SLP	smac/hal/ssv6006c/ssv6006C_reg.h	15067;"	d
+SET_RG_EN_DPL_MOD	include/ssv6200_reg.h	8298;"	d
+SET_RG_EN_DPL_MOD	smac/hal/ssv6006c/ssv6006C_reg.h	15040;"	d
+SET_RG_EN_DP_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	15035;"	d
+SET_RG_EN_DP_VT_MON	include/ssv6200_reg.h	8348;"	d
+SET_RG_EN_DP_VT_MON	smac/hal/ssv6006c/ssv6006C_reg.h	15055;"	d
+SET_RG_EN_FDB	smac/hal/ssv6006c/ssv6006C_reg.h	14951;"	d
+SET_RG_EN_FDB_DCC_MUAL	smac/hal/ssv6006c/ssv6006C_reg.h	14956;"	d
+SET_RG_EN_FDB_DELAYC_MUAL	smac/hal/ssv6006c/ssv6006C_reg.h	14957;"	d
+SET_RG_EN_FDB_DELAYF_MUAL	smac/hal/ssv6006c/ssv6006C_reg.h	14958;"	d
+SET_RG_EN_FDB_PHASESWAP_MUAL	smac/hal/ssv6006c/ssv6006C_reg.h	14959;"	d
+SET_RG_EN_FDB_RECAL	smac/hal/ssv6006c/ssv6006C_reg.h	14969;"	d
+SET_RG_EN_HSDIV_OBF_MX	smac/hal/ssv6006c/ssv6006C_reg.h	14189;"	d
+SET_RG_EN_HSDIV_OBF_MX_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	14188;"	d
+SET_RG_EN_HSDIV_OBF_SX	smac/hal/ssv6006c/ssv6006C_reg.h	14187;"	d
+SET_RG_EN_HSDIV_OBF_SX_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	14186;"	d
+SET_RG_EN_IOTADC_160M	smac/hal/ssv6006c/ssv6006C_reg.h	15024;"	d
+SET_RG_EN_IOT_ADC	smac/hal/ssv6006c/ssv6006C_reg.h	13408;"	d
+SET_RG_EN_IOT_ADC_BUF	smac/hal/ssv6006c/ssv6006C_reg.h	13407;"	d
+SET_RG_EN_IQPAD_IOSW	include/ssv6200_reg.h	8157;"	d
+SET_RG_EN_IREF_RX	include/ssv6200_reg.h	8153;"	d
+SET_RG_EN_IREF_RX	smac/hal/ssv6006c/ssv6006C_reg.h	13411;"	d
+SET_RG_EN_LDO_5G_CP	smac/hal/ssv6006c/ssv6006C_reg.h	14203;"	d
+SET_RG_EN_LDO_5G_CP_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	14054;"	d
+SET_RG_EN_LDO_5G_CP_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	14211;"	d
+SET_RG_EN_LDO_5G_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	14204;"	d
+SET_RG_EN_LDO_5G_DIV_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	14059;"	d
+SET_RG_EN_LDO_5G_DIV_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	14212;"	d
+SET_RG_EN_LDO_5G_LO	smac/hal/ssv6006c/ssv6006C_reg.h	14205;"	d
+SET_RG_EN_LDO_5G_LO_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	14056;"	d
+SET_RG_EN_LDO_5G_LO_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	14213;"	d
+SET_RG_EN_LDO_5G_VCO	smac/hal/ssv6006c/ssv6006C_reg.h	14206;"	d
+SET_RG_EN_LDO_5G_VCO_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	14214;"	d
+SET_RG_EN_LDO_5G_VCO_PSW	smac/hal/ssv6006c/ssv6006C_reg.h	14209;"	d
+SET_RG_EN_LDO_5G_VCO_VDD33	smac/hal/ssv6006c/ssv6006C_reg.h	14210;"	d
+SET_RG_EN_LDO_ABB	include/ssv6200_reg.h	8149;"	d
+SET_RG_EN_LDO_AFE	include/ssv6200_reg.h	8150;"	d
+SET_RG_EN_LDO_AFE	smac/hal/ssv6006c/ssv6006C_reg.h	13410;"	d
+SET_RG_EN_LDO_CP	smac/hal/ssv6006c/ssv6006C_reg.h	13696;"	d
+SET_RG_EN_LDO_CP_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	13442;"	d
+SET_RG_EN_LDO_CP_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	13702;"	d
+SET_RG_EN_LDO_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	13697;"	d
+SET_RG_EN_LDO_DIV_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	13447;"	d
+SET_RG_EN_LDO_DIV_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	13703;"	d
+SET_RG_EN_LDO_DP_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	15021;"	d
+SET_RG_EN_LDO_DP_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	15044;"	d
+SET_RG_EN_LDO_EFUSE	smac/hal/ssv6006c/ssv6006C_reg.h	14979;"	d
+SET_RG_EN_LDO_LO	smac/hal/ssv6006c/ssv6006C_reg.h	13698;"	d
+SET_RG_EN_LDO_LO_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	13444;"	d
+SET_RG_EN_LDO_LO_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	13704;"	d
+SET_RG_EN_LDO_RX_AFE_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	13440;"	d
+SET_RG_EN_LDO_RX_AFE_FC	smac/hal/ssv6006c/ssv6006C_reg.h	13433;"	d
+SET_RG_EN_LDO_RX_AFE_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	13435;"	d
+SET_RG_EN_LDO_RX_FE	include/ssv6200_reg.h	8148;"	d
+SET_RG_EN_LDO_RX_FE	smac/hal/ssv6006c/ssv6006C_reg.h	13409;"	d
+SET_RG_EN_LDO_RX_FE_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	13438;"	d
+SET_RG_EN_LDO_RX_FE_FC	smac/hal/ssv6006c/ssv6006C_reg.h	13432;"	d
+SET_RG_EN_LDO_RX_FE_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	13434;"	d
+SET_RG_EN_LDO_VCO	smac/hal/ssv6006c/ssv6006C_reg.h	13699;"	d
+SET_RG_EN_LDO_VCO_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	13705;"	d
+SET_RG_EN_LDO_VCO_PSW	smac/hal/ssv6006c/ssv6006C_reg.h	13700;"	d
+SET_RG_EN_LDO_VCO_VDD33	smac/hal/ssv6006c/ssv6006C_reg.h	13701;"	d
+SET_RG_EN_LDO_XO_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	14946;"	d
+SET_RG_EN_LDO_XO_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	14945;"	d
+SET_RG_EN_MAC_120M	smac/hal/ssv6006c/ssv6006C_reg.h	15027;"	d
+SET_RG_EN_MAC_160M	smac/hal/ssv6006c/ssv6006C_reg.h	15031;"	d
+SET_RG_EN_MAC_80M	smac/hal/ssv6006c/ssv6006C_reg.h	15025;"	d
+SET_RG_EN_MAC_96M	smac/hal/ssv6006c/ssv6006C_reg.h	15026;"	d
+SET_RG_EN_MANUAL	include/ssv6200_reg.h	8115;"	d
+SET_RG_EN_PHY_160M	smac/hal/ssv6006c/ssv6006C_reg.h	15029;"	d
+SET_RG_EN_PHY_320M	smac/hal/ssv6006c/ssv6006C_reg.h	15030;"	d
+SET_RG_EN_PHY_80M	smac/hal/ssv6006c/ssv6006C_reg.h	15028;"	d
+SET_RG_EN_RCAL	include/ssv6200_reg.h	8398;"	d
+SET_RG_EN_RTC_CAL	smac/hal/ssv6006c/ssv6006C_reg.h	14994;"	d
+SET_RG_EN_RX_ADC	smac/hal/ssv6006c/ssv6006C_reg.h	13392;"	d
+SET_RG_EN_RX_DIV2	include/ssv6200_reg.h	8128;"	d
+SET_RG_EN_RX_DIV2	smac/hal/ssv6006c/ssv6006C_reg.h	13384;"	d
+SET_RG_EN_RX_FILTER	include/ssv6200_reg.h	8131;"	d
+SET_RG_EN_RX_FILTER	smac/hal/ssv6006c/ssv6006C_reg.h	13390;"	d
+SET_RG_EN_RX_HPF	include/ssv6200_reg.h	8132;"	d
+SET_RG_EN_RX_IQCAL	include/ssv6200_reg.h	8144;"	d
+SET_RG_EN_RX_IQCAL	smac/hal/ssv6006c/ssv6006C_reg.h	13419;"	d
+SET_RG_EN_RX_LNA	include/ssv6200_reg.h	8126;"	d
+SET_RG_EN_RX_LNA	smac/hal/ssv6006c/ssv6006C_reg.h	13380;"	d
+SET_RG_EN_RX_LOBF	include/ssv6200_reg.h	8139;"	d
+SET_RG_EN_RX_LOBUF	include/ssv6200_reg.h	8129;"	d
+SET_RG_EN_RX_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	13386;"	d
+SET_RG_EN_RX_MIXER	include/ssv6200_reg.h	8127;"	d
+SET_RG_EN_RX_MIXER	smac/hal/ssv6006c/ssv6006C_reg.h	13382;"	d
+SET_RG_EN_RX_PADSW	include/ssv6200_reg.h	8169;"	d
+SET_RG_EN_RX_PADSW	smac/hal/ssv6006c/ssv6006C_reg.h	13431;"	d
+SET_RG_EN_RX_RSSI	include/ssv6200_reg.h	8133;"	d
+SET_RG_EN_RX_RSSI	smac/hal/ssv6006c/ssv6006C_reg.h	13394;"	d
+SET_RG_EN_RX_RSSI_TESTNODE	include/ssv6200_reg.h	8195;"	d
+SET_RG_EN_RX_RSSI_TESTNODE	smac/hal/ssv6006c/ssv6006C_reg.h	13504;"	d
+SET_RG_EN_RX_TESTNODE	include/ssv6200_reg.h	8170;"	d
+SET_RG_EN_RX_TESTNODE	smac/hal/ssv6006c/ssv6006C_reg.h	13430;"	d
+SET_RG_EN_RX_TZ	include/ssv6200_reg.h	8130;"	d
+SET_RG_EN_RX_TZ	smac/hal/ssv6006c/ssv6006C_reg.h	13388;"	d
+SET_RG_EN_SARADC	include/ssv6200_reg.h	8271;"	d
+SET_RG_EN_SARADC	smac/hal/ssv6006c/ssv6006C_reg.h	13423;"	d
+SET_RG_EN_SAR_TEST	include/ssv6200_reg.h	8267;"	d
+SET_RG_EN_SAR_TEST	smac/hal/ssv6006c/ssv6006C_reg.h	13639;"	d
+SET_RG_EN_SRVC	include/ssv6200_reg.h	7761;"	d
+SET_RG_EN_SX	include/ssv6200_reg.h	8125;"	d
+SET_RG_EN_SX5GB_CP	smac/hal/ssv6006c/ssv6006C_reg.h	14175;"	d
+SET_RG_EN_SX5GB_CP_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	14174;"	d
+SET_RG_EN_SX5GB_DITHER	smac/hal/ssv6006c/ssv6006C_reg.h	14276;"	d
+SET_RG_EN_SX5GB_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	14177;"	d
+SET_RG_EN_SX5GB_DIV_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	14176;"	d
+SET_RG_EN_SX5GB_HSDIV	smac/hal/ssv6006c/ssv6006C_reg.h	14185;"	d
+SET_RG_EN_SX5GB_HSDIV_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	14184;"	d
+SET_RG_EN_SX5GB_LDO_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	14202;"	d
+SET_RG_EN_SX5GB_MOD	smac/hal/ssv6006c/ssv6006C_reg.h	14275;"	d
+SET_RG_EN_SX5GB_VCO	smac/hal/ssv6006c/ssv6006C_reg.h	14179;"	d
+SET_RG_EN_SX5GB_VCOMON	smac/hal/ssv6006c/ssv6006C_reg.h	14269;"	d
+SET_RG_EN_SX5GB_VCO_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	14178;"	d
+SET_RG_EN_SXMIX_INBF	smac/hal/ssv6006c/ssv6006C_reg.h	14208;"	d
+SET_RG_EN_SXMIX_INBF_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	14207;"	d
+SET_RG_EN_SX_CH	include/ssv6200_reg.h	8287;"	d
+SET_RG_EN_SX_CHP	include/ssv6200_reg.h	8288;"	d
+SET_RG_EN_SX_CHPLDO	include/ssv6200_reg.h	8151;"	d
+SET_RG_EN_SX_CP	smac/hal/ssv6006c/ssv6006C_reg.h	13671;"	d
+SET_RG_EN_SX_CP_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	13670;"	d
+SET_RG_EN_SX_DITHER	include/ssv6200_reg.h	8293;"	d
+SET_RG_EN_SX_DITHER	smac/hal/ssv6006c/ssv6006C_reg.h	13785;"	d
+SET_RG_EN_SX_DIV	include/ssv6200_reg.h	8296;"	d
+SET_RG_EN_SX_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	13673;"	d
+SET_RG_EN_SX_DIVCK	include/ssv6200_reg.h	8289;"	d
+SET_RG_EN_SX_DIV_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	13672;"	d
+SET_RG_EN_SX_LCK_BIN	include/ssv6200_reg.h	8155;"	d
+SET_RG_EN_SX_LDO_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	13695;"	d
+SET_RG_EN_SX_LOBFLDO	include/ssv6200_reg.h	8152;"	d
+SET_RG_EN_SX_LPF	include/ssv6200_reg.h	8297;"	d
+SET_RG_EN_SX_MIX	smac/hal/ssv6006c/ssv6006C_reg.h	14191;"	d
+SET_RG_EN_SX_MIX_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	14190;"	d
+SET_RG_EN_SX_MOD	include/ssv6200_reg.h	8292;"	d
+SET_RG_EN_SX_MOD	smac/hal/ssv6006c/ssv6006C_reg.h	13784;"	d
+SET_RG_EN_SX_R3	include/ssv6200_reg.h	8286;"	d
+SET_RG_EN_SX_REP	smac/hal/ssv6006c/ssv6006C_reg.h	14193;"	d
+SET_RG_EN_SX_REP_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	14192;"	d
+SET_RG_EN_SX_VCO	include/ssv6200_reg.h	8291;"	d
+SET_RG_EN_SX_VCO	smac/hal/ssv6006c/ssv6006C_reg.h	13675;"	d
+SET_RG_EN_SX_VCOBF	include/ssv6200_reg.h	8290;"	d
+SET_RG_EN_SX_VCOMON	smac/hal/ssv6006c/ssv6006C_reg.h	13778;"	d
+SET_RG_EN_SX_VCO_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	13674;"	d
+SET_RG_EN_SX_VT_MON	include/ssv6200_reg.h	8294;"	d
+SET_RG_EN_SX_VT_MON_DG	include/ssv6200_reg.h	8295;"	d
+SET_RG_EN_TESTPAD_IOSW	include/ssv6200_reg.h	8158;"	d
+SET_RG_EN_TRXBF_BYPASS	include/ssv6200_reg.h	8159;"	d
+SET_RG_EN_TX_BT_PA	smac/hal/ssv6006c/ssv6006C_reg.h	13406;"	d
+SET_RG_EN_TX_DAC	smac/hal/ssv6006c/ssv6006C_reg.h	13400;"	d
+SET_RG_EN_TX_DAC_CAL	include/ssv6200_reg.h	8145;"	d
+SET_RG_EN_TX_DAC_CAL	smac/hal/ssv6006c/ssv6006C_reg.h	13413;"	d
+SET_RG_EN_TX_DAC_OUT	include/ssv6200_reg.h	8147;"	d
+SET_RG_EN_TX_DAC_OUT	smac/hal/ssv6006c/ssv6006C_reg.h	13427;"	d
+SET_RG_EN_TX_DAC_VOUT	include/ssv6200_reg.h	8154;"	d
+SET_RG_EN_TX_DAC_VOUT	smac/hal/ssv6006c/ssv6006C_reg.h	13428;"	d
+SET_RG_EN_TX_DIV2	include/ssv6200_reg.h	8136;"	d
+SET_RG_EN_TX_DIV2	smac/hal/ssv6006c/ssv6006C_reg.h	13402;"	d
+SET_RG_EN_TX_DIV2_BUF	include/ssv6200_reg.h	8137;"	d
+SET_RG_EN_TX_DIV2_BUF	smac/hal/ssv6006c/ssv6006C_reg.h	13404;"	d
+SET_RG_EN_TX_DPD	include/ssv6200_reg.h	8142;"	d
+SET_RG_EN_TX_DPD	smac/hal/ssv6006c/ssv6006C_reg.h	13421;"	d
+SET_RG_EN_TX_LOBF	include/ssv6200_reg.h	8138;"	d
+SET_RG_EN_TX_MOD	include/ssv6200_reg.h	8135;"	d
+SET_RG_EN_TX_MOD	smac/hal/ssv6006c/ssv6006C_reg.h	13398;"	d
+SET_RG_EN_TX_PA	smac/hal/ssv6006c/ssv6006C_reg.h	13396;"	d
+SET_RG_EN_TX_SELF_MIXER	include/ssv6200_reg.h	8146;"	d
+SET_RG_EN_TX_SELF_MIXER	smac/hal/ssv6006c/ssv6006C_reg.h	13417;"	d
+SET_RG_EN_TX_TRSW	include/ssv6200_reg.h	8124;"	d
+SET_RG_EN_TX_TRSW	smac/hal/ssv6006c/ssv6006C_reg.h	13378;"	d
+SET_RG_EN_TX_TSSI	include/ssv6200_reg.h	8143;"	d
+SET_RG_EN_TX_TSSI	smac/hal/ssv6006c/ssv6006C_reg.h	13422;"	d
+SET_RG_EN_TX_VTOI_2ND	smac/hal/ssv6006c/ssv6006C_reg.h	13424;"	d
+SET_RG_EN_VCOBF_DIVCK	smac/hal/ssv6006c/ssv6006C_reg.h	13689;"	d
+SET_RG_EN_VCOBF_DIVCK_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	13688;"	d
+SET_RG_EN_VCOBF_RXMB	smac/hal/ssv6006c/ssv6006C_reg.h	13685;"	d
+SET_RG_EN_VCOBF_RXMB_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	13684;"	d
+SET_RG_EN_VCOBF_RXOB	smac/hal/ssv6006c/ssv6006C_reg.h	13687;"	d
+SET_RG_EN_VCOBF_RXOB_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	13686;"	d
+SET_RG_EN_VCOBF_TXMB	smac/hal/ssv6006c/ssv6006C_reg.h	13681;"	d
+SET_RG_EN_VCOBF_TXMB_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	13680;"	d
+SET_RG_EN_VCOBF_TXOB	smac/hal/ssv6006c/ssv6006C_reg.h	13683;"	d
+SET_RG_EN_VCOBF_TXOB_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	13682;"	d
+SET_RG_EN_XOTEST	smac/hal/ssv6006c/ssv6006C_reg.h	14954;"	d
+SET_RG_EQ_BYPASS_FBW_TAP	include/ssv6200_reg.h	7838;"	d
+SET_RG_EQ_BYPASS_FBW_TAP	smac/hal/ssv6006c/ssv6006C_reg.h	15423;"	d
+SET_RG_EQ_KI_T1	include/ssv6200_reg.h	7805;"	d
+SET_RG_EQ_KI_T1	smac/hal/ssv6006c/ssv6006C_reg.h	15381;"	d
+SET_RG_EQ_KI_T2	include/ssv6200_reg.h	7803;"	d
+SET_RG_EQ_KI_T2	smac/hal/ssv6006c/ssv6006C_reg.h	15379;"	d
+SET_RG_EQ_KP_T1	include/ssv6200_reg.h	7806;"	d
+SET_RG_EQ_KP_T1	smac/hal/ssv6006c/ssv6006C_reg.h	15382;"	d
+SET_RG_EQ_KP_T2	include/ssv6200_reg.h	7804;"	d
+SET_RG_EQ_KP_T2	smac/hal/ssv6006c/ssv6006C_reg.h	15380;"	d
+SET_RG_EQ_MAIN_TAP_COEF	include/ssv6200_reg.h	7814;"	d
+SET_RG_EQ_MAIN_TAP_COEF	smac/hal/ssv6006c/ssv6006C_reg.h	15390;"	d
+SET_RG_EQ_MAIN_TAP_MAN	include/ssv6200_reg.h	7813;"	d
+SET_RG_EQ_MAIN_TAP_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	15389;"	d
+SET_RG_EQ_MU_FB_T1	include/ssv6200_reg.h	7797;"	d
+SET_RG_EQ_MU_FB_T1	smac/hal/ssv6006c/ssv6006C_reg.h	15373;"	d
+SET_RG_EQ_MU_FB_T2	include/ssv6200_reg.h	7795;"	d
+SET_RG_EQ_MU_FB_T2	smac/hal/ssv6006c/ssv6006C_reg.h	15371;"	d
+SET_RG_EQ_MU_FB_T3	include/ssv6200_reg.h	7801;"	d
+SET_RG_EQ_MU_FB_T3	smac/hal/ssv6006c/ssv6006C_reg.h	15377;"	d
+SET_RG_EQ_MU_FB_T4	include/ssv6200_reg.h	7799;"	d
+SET_RG_EQ_MU_FB_T4	smac/hal/ssv6006c/ssv6006C_reg.h	15375;"	d
+SET_RG_EQ_MU_FF_T1	include/ssv6200_reg.h	7798;"	d
+SET_RG_EQ_MU_FF_T1	smac/hal/ssv6006c/ssv6006C_reg.h	15374;"	d
+SET_RG_EQ_MU_FF_T2	include/ssv6200_reg.h	7796;"	d
+SET_RG_EQ_MU_FF_T2	smac/hal/ssv6006c/ssv6006C_reg.h	15372;"	d
+SET_RG_EQ_MU_FF_T3	include/ssv6200_reg.h	7802;"	d
+SET_RG_EQ_MU_FF_T3	smac/hal/ssv6006c/ssv6006C_reg.h	15378;"	d
+SET_RG_EQ_MU_FF_T4	include/ssv6200_reg.h	7800;"	d
+SET_RG_EQ_MU_FF_T4	smac/hal/ssv6006c/ssv6006C_reg.h	15376;"	d
+SET_RG_EQ_SHORT_GI_SHIFT	include/ssv6200_reg.h	7909;"	d
+SET_RG_ERASE_SC_NUM0	smac/hal/ssv6006c/ssv6006C_reg.h	15493;"	d
+SET_RG_ERASE_SC_NUM1	smac/hal/ssv6006c/ssv6006C_reg.h	15491;"	d
+SET_RG_ERASE_SC_NUM2	smac/hal/ssv6006c/ssv6006C_reg.h	15489;"	d
+SET_RG_ERASE_SC_NUM3	smac/hal/ssv6006c/ssv6006C_reg.h	15487;"	d
+SET_RG_ERASE_SC_NUM4	smac/hal/ssv6006c/ssv6006C_reg.h	15501;"	d
+SET_RG_ERASE_SC_NUM5	smac/hal/ssv6006c/ssv6006C_reg.h	15499;"	d
+SET_RG_ERASE_SC_NUM6	smac/hal/ssv6006c/ssv6006C_reg.h	15497;"	d
+SET_RG_ERASE_SC_NUM7	smac/hal/ssv6006c/ssv6006C_reg.h	15495;"	d
+SET_RG_FDB_BYPASS	smac/hal/ssv6006c/ssv6006C_reg.h	14952;"	d
+SET_RG_FDB_CDELAY_MUAL	smac/hal/ssv6006c/ssv6006C_reg.h	14962;"	d
+SET_RG_FDB_DUTY_LTH	smac/hal/ssv6006c/ssv6006C_reg.h	14953;"	d
+SET_RG_FDB_FDELAY_MUAL	smac/hal/ssv6006c/ssv6006C_reg.h	14963;"	d
+SET_RG_FDB_PHASESWAP_MUAL	smac/hal/ssv6006c/ssv6006C_reg.h	14960;"	d
+SET_RG_FDB_RDELAYF	smac/hal/ssv6006c/ssv6006C_reg.h	14966;"	d
+SET_RG_FDB_RDELAYS	smac/hal/ssv6006c/ssv6006C_reg.h	14967;"	d
+SET_RG_FDB_RECAL_TIMMER	smac/hal/ssv6006c/ssv6006C_reg.h	14968;"	d
+SET_RG_FEC	include/ssv6200_reg.h	7543;"	d
+SET_RG_FEC	smac/hal/ssv6006c/ssv6006C_reg.h	15126;"	d
+SET_RG_FFT_EN	include/ssv6200_reg.h	8041;"	d
+SET_RG_FFT_ENRG_FREQ	include/ssv6200_reg.h	8044;"	d
+SET_RG_FFT_IFFT_MODE	include/ssv6200_reg.h	7552;"	d
+SET_RG_FFT_MEM_CLK_EN_RX	include/ssv6200_reg.h	7525;"	d
+SET_RG_FFT_MEM_CLK_EN_TX	include/ssv6200_reg.h	7526;"	d
+SET_RG_FFT_MOD	include/ssv6200_reg.h	8042;"	d
+SET_RG_FFT_SCALE	include/ssv6200_reg.h	8043;"	d
+SET_RG_FFT_SCALE_104	smac/hal/ssv6006c/ssv6006C_reg.h	15437;"	d
+SET_RG_FFT_SCALE_114	smac/hal/ssv6006c/ssv6006C_reg.h	15438;"	d
+SET_RG_FFT_SCALE_52	smac/hal/ssv6006c/ssv6006C_reg.h	15439;"	d
+SET_RG_FFT_SCALE_56	smac/hal/ssv6006c/ssv6006C_reg.h	15440;"	d
+SET_RG_FFT_WDW_SHORT_SHIFT	include/ssv6200_reg.h	7910;"	d
+SET_RG_FILTER_AVERAGE_EN	smac/hal/ssv6006c/ssv6006C_reg.h	14578;"	d
+SET_RG_FMT_DET_GF_TH	include/ssv6200_reg.h	7916;"	d
+SET_RG_FMT_DET_GF_TH	smac/hal/ssv6006c/ssv6006C_reg.h	15556;"	d
+SET_RG_FMT_DET_LENGTH_TH	include/ssv6200_reg.h	7918;"	d
+SET_RG_FMT_DET_MM_TH	include/ssv6200_reg.h	7915;"	d
+SET_RG_FMT_DET_MM_TH	smac/hal/ssv6006c/ssv6006C_reg.h	15555;"	d
+SET_RG_FORCE_11B_EN	include/ssv6200_reg.h	7524;"	d
+SET_RG_FORCE_11B_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15110;"	d
+SET_RG_FORCE_11GN_EN	include/ssv6200_reg.h	7523;"	d
+SET_RG_FORCE_11GN_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15109;"	d
+SET_RG_FPGA_80M_PH_STP	include/ssv6200_reg.h	8046;"	d
+SET_RG_FPGA_80M_PH_UP	include/ssv6200_reg.h	8045;"	d
+SET_RG_FPGA_CLK_REF_40M_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15015;"	d
+SET_RG_GEMINIA_40M_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	11741;"	d
+SET_RG_GEMINIA_ADC_EDGE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	11749;"	d
+SET_RG_GEMINIA_ALPHA_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	11785;"	d
+SET_RG_GEMINIA_BT_CLK32K_CAL_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	11849;"	d
+SET_RG_GEMINIA_BT_CLK_SW	smac/hal/ssv6006c/ssv6006C_reg.h	11848;"	d
+SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	11665;"	d
+SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	11663;"	d
+SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	11645;"	d
+SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	11643;"	d
+SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	11641;"	d
+SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	11639;"	d
+SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	11637;"	d
+SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	11635;"	d
+SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	11661;"	d
+SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	11659;"	d
+SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	11657;"	d
+SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	11655;"	d
+SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	11653;"	d
+SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	11651;"	d
+SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	11649;"	d
+SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	11647;"	d
+SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	11697;"	d
+SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	11695;"	d
+SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	11677;"	d
+SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	11675;"	d
+SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	11673;"	d
+SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	11671;"	d
+SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	11669;"	d
+SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	11667;"	d
+SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	11693;"	d
+SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	11691;"	d
+SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	11689;"	d
+SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	11687;"	d
+SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	11685;"	d
+SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	11683;"	d
+SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	11681;"	d
+SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	11679;"	d
+SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	11666;"	d
+SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	11664;"	d
+SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	11646;"	d
+SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	11644;"	d
+SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	11642;"	d
+SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	11640;"	d
+SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	11638;"	d
+SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	11636;"	d
+SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	11662;"	d
+SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	11660;"	d
+SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	11658;"	d
+SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	11656;"	d
+SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	11654;"	d
+SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	11652;"	d
+SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	11650;"	d
+SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	11648;"	d
+SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	11698;"	d
+SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	11696;"	d
+SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	11678;"	d
+SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	11676;"	d
+SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	11674;"	d
+SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	11672;"	d
+SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	11670;"	d
+SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	11668;"	d
+SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	11694;"	d
+SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	11692;"	d
+SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	11690;"	d
+SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	11688;"	d
+SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	11686;"	d
+SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	11684;"	d
+SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	11682;"	d
+SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	11680;"	d
+SET_RG_GEMINIA_BT_PABIAS_2X	smac/hal/ssv6006c/ssv6006C_reg.h	11229;"	d
+SET_RG_GEMINIA_BT_PABIAS_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	11230;"	d
+SET_RG_GEMINIA_BT_PA_CAPSEL	smac/hal/ssv6006c/ssv6006C_reg.h	11228;"	d
+SET_RG_GEMINIA_BT_RX_ABBCFIX	smac/hal/ssv6006c/ssv6006C_reg.h	11194;"	d
+SET_RG_GEMINIA_BT_RX_ABBCTUNEI	smac/hal/ssv6006c/ssv6006C_reg.h	11188;"	d
+SET_RG_GEMINIA_BT_RX_ABBCTUNEQ	smac/hal/ssv6006c/ssv6006C_reg.h	11189;"	d
+SET_RG_GEMINIA_BT_RX_ABB_BT_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	11196;"	d
+SET_RG_GEMINIA_BT_RX_ABB_IDIV3	smac/hal/ssv6006c/ssv6006C_reg.h	11197;"	d
+SET_RG_GEMINIA_BT_RX_ABB_N_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	11195;"	d
+SET_RG_GEMINIA_BT_RX_ADC_CLOAD	smac/hal/ssv6006c/ssv6006C_reg.h	11340;"	d
+SET_RG_GEMINIA_BT_RX_ADC_ICMP	smac/hal/ssv6006c/ssv6006C_reg.h	11338;"	d
+SET_RG_GEMINIA_BT_RX_ADC_VCMI	smac/hal/ssv6006c/ssv6006C_reg.h	11339;"	d
+SET_RG_GEMINIA_BT_RX_DCCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	11714;"	d
+SET_RG_GEMINIA_BT_RX_EN_IDACA_COARSE	smac/hal/ssv6006c/ssv6006C_reg.h	11198;"	d
+SET_RG_GEMINIA_BT_RX_EN_LOOPA	smac/hal/ssv6006c/ssv6006C_reg.h	11199;"	d
+SET_RG_GEMINIA_BT_RX_FILTERI1ST	smac/hal/ssv6006c/ssv6006C_reg.h	11191;"	d
+SET_RG_GEMINIA_BT_RX_FILTERI2ND	smac/hal/ssv6006c/ssv6006C_reg.h	11192;"	d
+SET_RG_GEMINIA_BT_RX_FILTERI3RD	smac/hal/ssv6006c/ssv6006C_reg.h	11193;"	d
+SET_RG_GEMINIA_BT_RX_FILTERI_COARSE	smac/hal/ssv6006c/ssv6006C_reg.h	11190;"	d
+SET_RG_GEMINIA_BT_RX_FILTERVCM	smac/hal/ssv6006c/ssv6006C_reg.h	11200;"	d
+SET_RG_GEMINIA_BT_RX_HG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	11293;"	d
+SET_RG_GEMINIA_BT_RX_HG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	11288;"	d
+SET_RG_GEMINIA_BT_RX_HG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	11289;"	d
+SET_RG_GEMINIA_BT_RX_HG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	11290;"	d
+SET_RG_GEMINIA_BT_RX_HG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	11286;"	d
+SET_RG_GEMINIA_BT_RX_HG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	11294;"	d
+SET_RG_GEMINIA_BT_RX_HG_SQDC	smac/hal/ssv6006c/ssv6006C_reg.h	11292;"	d
+SET_RG_GEMINIA_BT_RX_HG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	11295;"	d
+SET_RG_GEMINIA_BT_RX_HG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	11291;"	d
+SET_RG_GEMINIA_BT_RX_HG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	11287;"	d
+SET_RG_GEMINIA_BT_RX_HG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	11296;"	d
+SET_RG_GEMINIA_BT_RX_LG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	11315;"	d
+SET_RG_GEMINIA_BT_RX_LG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	11310;"	d
+SET_RG_GEMINIA_BT_RX_LG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	11311;"	d
+SET_RG_GEMINIA_BT_RX_LG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	11312;"	d
+SET_RG_GEMINIA_BT_RX_LG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	11308;"	d
+SET_RG_GEMINIA_BT_RX_LG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	11316;"	d
+SET_RG_GEMINIA_BT_RX_LG_SQDC	smac/hal/ssv6006c/ssv6006C_reg.h	11314;"	d
+SET_RG_GEMINIA_BT_RX_LG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	11317;"	d
+SET_RG_GEMINIA_BT_RX_LG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	11313;"	d
+SET_RG_GEMINIA_BT_RX_LG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	11309;"	d
+SET_RG_GEMINIA_BT_RX_LG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	11318;"	d
+SET_RG_GEMINIA_BT_RX_MG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	11304;"	d
+SET_RG_GEMINIA_BT_RX_MG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	11299;"	d
+SET_RG_GEMINIA_BT_RX_MG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	11300;"	d
+SET_RG_GEMINIA_BT_RX_MG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	11301;"	d
+SET_RG_GEMINIA_BT_RX_MG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	11297;"	d
+SET_RG_GEMINIA_BT_RX_MG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	11305;"	d
+SET_RG_GEMINIA_BT_RX_MG_SQDC	smac/hal/ssv6006c/ssv6006C_reg.h	11303;"	d
+SET_RG_GEMINIA_BT_RX_MG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	11306;"	d
+SET_RG_GEMINIA_BT_RX_MG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	11302;"	d
+SET_RG_GEMINIA_BT_RX_MG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	11298;"	d
+SET_RG_GEMINIA_BT_RX_MG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	11307;"	d
+SET_RG_GEMINIA_BT_RX_OUTVCM	smac/hal/ssv6006c/ssv6006C_reg.h	11201;"	d
+SET_RG_GEMINIA_BT_RX_ULG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	11326;"	d
+SET_RG_GEMINIA_BT_RX_ULG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	11321;"	d
+SET_RG_GEMINIA_BT_RX_ULG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	11322;"	d
+SET_RG_GEMINIA_BT_RX_ULG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	11323;"	d
+SET_RG_GEMINIA_BT_RX_ULG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	11319;"	d
+SET_RG_GEMINIA_BT_RX_ULG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	11327;"	d
+SET_RG_GEMINIA_BT_RX_ULG_SQDC	smac/hal/ssv6006c/ssv6006C_reg.h	11325;"	d
+SET_RG_GEMINIA_BT_RX_ULG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	11328;"	d
+SET_RG_GEMINIA_BT_RX_ULG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	11324;"	d
+SET_RG_GEMINIA_BT_RX_ULG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	11320;"	d
+SET_RG_GEMINIA_BT_RX_ULG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	11329;"	d
+SET_RG_GEMINIA_BT_TXLPF_BOOSTI	smac/hal/ssv6006c/ssv6006C_reg.h	11365;"	d
+SET_RG_GEMINIA_BT_TXPGA_CAPSW	smac/hal/ssv6006c/ssv6006C_reg.h	11219;"	d
+SET_RG_GEMINIA_BT_TX_DACI1ST	smac/hal/ssv6006c/ssv6006C_reg.h	11359;"	d
+SET_RG_GEMINIA_BT_TX_DACLPF_ICOARSE	smac/hal/ssv6006c/ssv6006C_reg.h	11360;"	d
+SET_RG_GEMINIA_BT_TX_DACLPF_IFINE	smac/hal/ssv6006c/ssv6006C_reg.h	11361;"	d
+SET_RG_GEMINIA_BT_TX_DACLPF_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	11362;"	d
+SET_RG_GEMINIA_BT_TX_DAC_CKEDGE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	11367;"	d
+SET_RG_GEMINIA_BT_TX_DAC_IATTN	smac/hal/ssv6006c/ssv6006C_reg.h	11364;"	d
+SET_RG_GEMINIA_BT_TX_DAC_IBIAS	smac/hal/ssv6006c/ssv6006C_reg.h	11363;"	d
+SET_RG_GEMINIA_BT_TX_DAC_IOFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	11369;"	d
+SET_RG_GEMINIA_BT_TX_DAC_OS	smac/hal/ssv6006c/ssv6006C_reg.h	11368;"	d
+SET_RG_GEMINIA_BT_TX_DAC_QOFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	11370;"	d
+SET_RG_GEMINIA_BT_TX_DAC_RCAL	smac/hal/ssv6006c/ssv6006C_reg.h	11366;"	d
+SET_RG_GEMINIA_BT_TX_DIV_VSET	smac/hal/ssv6006c/ssv6006C_reg.h	11220;"	d
+SET_RG_GEMINIA_BT_TX_GAIN_OFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	11237;"	d
+SET_RG_GEMINIA_BT_TX_LOBUF_VSET	smac/hal/ssv6006c/ssv6006C_reg.h	11221;"	d
+SET_RG_GEMINIA_BT_TX_PA_VCAS	smac/hal/ssv6006c/ssv6006C_reg.h	11231;"	d
+SET_RG_GEMINIA_BT_TX_VDDSW	smac/hal/ssv6006c/ssv6006C_reg.h	11222;"	d
+SET_RG_GEMINIA_BUCK_EN_PSM	smac/hal/ssv6006c/ssv6006C_reg.h	11828;"	d
+SET_RG_GEMINIA_BUCK_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	11825;"	d
+SET_RG_GEMINIA_BUCK_PSM_VTH	smac/hal/ssv6006c/ssv6006C_reg.h	11829;"	d
+SET_RG_GEMINIA_BUCK_VREF_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	11830;"	d
+SET_RG_GEMINIA_BW20_HB_COEF_00	smac/hal/ssv6006c/ssv6006C_reg.h	11772;"	d
+SET_RG_GEMINIA_BW20_HB_COEF_01	smac/hal/ssv6006c/ssv6006C_reg.h	11771;"	d
+SET_RG_GEMINIA_BW20_HB_COEF_02	smac/hal/ssv6006c/ssv6006C_reg.h	11774;"	d
+SET_RG_GEMINIA_BW20_HB_COEF_03	smac/hal/ssv6006c/ssv6006C_reg.h	11773;"	d
+SET_RG_GEMINIA_BW20_HB_COEF_04	smac/hal/ssv6006c/ssv6006C_reg.h	11776;"	d
+SET_RG_GEMINIA_BW20_HB_COEF_05	smac/hal/ssv6006c/ssv6006C_reg.h	11775;"	d
+SET_RG_GEMINIA_BW20_HB_COEF_06	smac/hal/ssv6006c/ssv6006C_reg.h	11778;"	d
+SET_RG_GEMINIA_BW20_HB_COEF_07	smac/hal/ssv6006c/ssv6006C_reg.h	11777;"	d
+SET_RG_GEMINIA_BW20_HB_COEF_08	smac/hal/ssv6006c/ssv6006C_reg.h	11780;"	d
+SET_RG_GEMINIA_BW20_HB_COEF_09	smac/hal/ssv6006c/ssv6006C_reg.h	11779;"	d
+SET_RG_GEMINIA_BW20_HB_COEF_10	smac/hal/ssv6006c/ssv6006C_reg.h	11782;"	d
+SET_RG_GEMINIA_BW20_HB_COEF_11	smac/hal/ssv6006c/ssv6006C_reg.h	11781;"	d
+SET_RG_GEMINIA_CAL_INDEX	smac/hal/ssv6006c/ssv6006C_reg.h	11100;"	d
+SET_RG_GEMINIA_CBW_20_40	smac/hal/ssv6006c/ssv6006C_reg.h	11764;"	d
+SET_RG_GEMINIA_CLK_RTC_SW	smac/hal/ssv6006c/ssv6006C_reg.h	11853;"	d
+SET_RG_GEMINIA_CLK_SAR_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	11345;"	d
+SET_RG_GEMINIA_DAC_DC_I	smac/hal/ssv6006c/ssv6006C_reg.h	11766;"	d
+SET_RG_GEMINIA_DAC_DC_Q	smac/hal/ssv6006c/ssv6006C_reg.h	11765;"	d
+SET_RG_GEMINIA_DAC_I_SET	smac/hal/ssv6006c/ssv6006C_reg.h	11769;"	d
+SET_RG_GEMINIA_DAC_MAN_I_EN	smac/hal/ssv6006c/ssv6006C_reg.h	11770;"	d
+SET_RG_GEMINIA_DAC_MAN_Q_EN	smac/hal/ssv6006c/ssv6006C_reg.h	11768;"	d
+SET_RG_GEMINIA_DAC_Q_SET	smac/hal/ssv6006c/ssv6006C_reg.h	11767;"	d
+SET_RG_GEMINIA_DCDC_CLK	smac/hal/ssv6006c/ssv6006C_reg.h	11838;"	d
+SET_RG_GEMINIA_DCDC_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	11824;"	d
+SET_RG_GEMINIA_DCDC_PULLLOW_CON	smac/hal/ssv6006c/ssv6006C_reg.h	11833;"	d
+SET_RG_GEMINIA_DCDC_RES2_CON	smac/hal/ssv6006c/ssv6006C_reg.h	11834;"	d
+SET_RG_GEMINIA_DCDC_RES_CON	smac/hal/ssv6006c/ssv6006C_reg.h	11835;"	d
+SET_RG_GEMINIA_DIS_DAC_OFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	11761;"	d
+SET_RG_GEMINIA_DLDO_BOOST_IQ	smac/hal/ssv6006c/ssv6006C_reg.h	11827;"	d
+SET_RG_GEMINIA_DLDO_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	11826;"	d
+SET_RG_GEMINIA_DPLL_CLK320BY2	smac/hal/ssv6006c/ssv6006C_reg.h	11763;"	d
+SET_RG_GEMINIA_DPL_MOD_ORDER	smac/hal/ssv6006c/ssv6006C_reg.h	11529;"	d
+SET_RG_GEMINIA_DPL_RFCTRL_CH	smac/hal/ssv6006c/ssv6006C_reg.h	11550;"	d
+SET_RG_GEMINIA_DPL_RFCTRL_F	smac/hal/ssv6006c/ssv6006C_reg.h	11549;"	d
+SET_RG_GEMINIA_DPL_SETTLING_TIMMER	smac/hal/ssv6006c/ssv6006C_reg.h	11818;"	d
+SET_RG_GEMINIA_DP_ADC320_DIVBY2_BT	smac/hal/ssv6006c/ssv6006C_reg.h	11526;"	d
+SET_RG_GEMINIA_DP_ADC320_DIVBY2_WF	smac/hal/ssv6006c/ssv6006C_reg.h	11527;"	d
+SET_RG_GEMINIA_DP_BBPLL_BP	smac/hal/ssv6006c/ssv6006C_reg.h	11522;"	d
+SET_RG_GEMINIA_DP_BBPLL_BS	smac/hal/ssv6006c/ssv6006C_reg.h	11547;"	d
+SET_RG_GEMINIA_DP_BBPLL_ICP	smac/hal/ssv6006c/ssv6006C_reg.h	11536;"	d
+SET_RG_GEMINIA_DP_BBPLL_IDUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11537;"	d
+SET_RG_GEMINIA_DP_BBPLL_PD	smac/hal/ssv6006c/ssv6006C_reg.h	11521;"	d
+SET_RG_GEMINIA_DP_BBPLL_PFD_DLY	smac/hal/ssv6006c/ssv6006C_reg.h	11541;"	d
+SET_RG_GEMINIA_DP_BBPLL_SDM_EDGE	smac/hal/ssv6006c/ssv6006C_reg.h	11548;"	d
+SET_RG_GEMINIA_DP_BBPLL_TESTSEL	smac/hal/ssv6006c/ssv6006C_reg.h	11535;"	d
+SET_RG_GEMINIA_DP_CP_IOST	smac/hal/ssv6006c/ssv6006C_reg.h	11539;"	d
+SET_RG_GEMINIA_DP_CP_IOSTPOL	smac/hal/ssv6006c/ssv6006C_reg.h	11538;"	d
+SET_RG_GEMINIA_DP_DAC320_DIVBY2	smac/hal/ssv6006c/ssv6006C_reg.h	11525;"	d
+SET_RG_GEMINIA_DP_FODIV	smac/hal/ssv6006c/ssv6006C_reg.h	11531;"	d
+SET_RG_GEMINIA_DP_FREF_DOUB	smac/hal/ssv6006c/ssv6006C_reg.h	11524;"	d
+SET_RG_GEMINIA_DP_LDO_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	11171;"	d
+SET_RG_GEMINIA_DP_OD_TEST	smac/hal/ssv6006c/ssv6006C_reg.h	11534;"	d
+SET_RG_GEMINIA_DP_PFD_PFDSEL	smac/hal/ssv6006c/ssv6006C_reg.h	11540;"	d
+SET_RG_GEMINIA_DP_REFDIV	smac/hal/ssv6006c/ssv6006C_reg.h	11530;"	d
+SET_RG_GEMINIA_DP_RHP	smac/hal/ssv6006c/ssv6006C_reg.h	11543;"	d
+SET_RG_GEMINIA_DP_RP	smac/hal/ssv6006c/ssv6006C_reg.h	11542;"	d
+SET_RG_GEMINIA_DP_VT_TH_HI	smac/hal/ssv6006c/ssv6006C_reg.h	11545;"	d
+SET_RG_GEMINIA_DP_VT_TH_LO	smac/hal/ssv6006c/ssv6006C_reg.h	11546;"	d
+SET_RG_GEMINIA_EN_DPL_MOD	smac/hal/ssv6006c/ssv6006C_reg.h	11528;"	d
+SET_RG_GEMINIA_EN_DP_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11523;"	d
+SET_RG_GEMINIA_EN_DP_VT_MON	smac/hal/ssv6006c/ssv6006C_reg.h	11544;"	d
+SET_RG_GEMINIA_EN_FDB	smac/hal/ssv6006c/ssv6006C_reg.h	11806;"	d
+SET_RG_GEMINIA_EN_FDB_DCC_MUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11810;"	d
+SET_RG_GEMINIA_EN_FDB_DELAYC_MUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11811;"	d
+SET_RG_GEMINIA_EN_FDB_DELAYF_MUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11812;"	d
+SET_RG_GEMINIA_EN_FDB_PHASESWAP_MUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11813;"	d
+SET_RG_GEMINIA_EN_FDB_RECAL	smac/hal/ssv6006c/ssv6006C_reg.h	11822;"	d
+SET_RG_GEMINIA_EN_IREF_RX	smac/hal/ssv6006c/ssv6006C_reg.h	11138;"	d
+SET_RG_GEMINIA_EN_LDO_ABB	smac/hal/ssv6006c/ssv6006C_reg.h	11135;"	d
+SET_RG_GEMINIA_EN_LDO_ADC	smac/hal/ssv6006c/ssv6006C_reg.h	11136;"	d
+SET_RG_GEMINIA_EN_LDO_CP	smac/hal/ssv6006c/ssv6006C_reg.h	11399;"	d
+SET_RG_GEMINIA_EN_LDO_CP_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	11403;"	d
+SET_RG_GEMINIA_EN_LDO_CP_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	11408;"	d
+SET_RG_GEMINIA_EN_LDO_DAC	smac/hal/ssv6006c/ssv6006C_reg.h	11137;"	d
+SET_RG_GEMINIA_EN_LDO_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	11400;"	d
+SET_RG_GEMINIA_EN_LDO_DIV_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	11404;"	d
+SET_RG_GEMINIA_EN_LDO_DIV_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	11409;"	d
+SET_RG_GEMINIA_EN_LDO_DP_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	11532;"	d
+SET_RG_GEMINIA_EN_LDO_DP_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	11533;"	d
+SET_RG_GEMINIA_EN_LDO_EFUSE	smac/hal/ssv6006c/ssv6006C_reg.h	11832;"	d
+SET_RG_GEMINIA_EN_LDO_LO	smac/hal/ssv6006c/ssv6006C_reg.h	11401;"	d
+SET_RG_GEMINIA_EN_LDO_LO_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	11405;"	d
+SET_RG_GEMINIA_EN_LDO_LO_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	11410;"	d
+SET_RG_GEMINIA_EN_LDO_RX_ADC_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	11164;"	d
+SET_RG_GEMINIA_EN_LDO_RX_FE	smac/hal/ssv6006c/ssv6006C_reg.h	11134;"	d
+SET_RG_GEMINIA_EN_LDO_VCO	smac/hal/ssv6006c/ssv6006C_reg.h	11402;"	d
+SET_RG_GEMINIA_EN_LDO_VCO_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	11411;"	d
+SET_RG_GEMINIA_EN_LDO_VCO_PSW	smac/hal/ssv6006c/ssv6006C_reg.h	11406;"	d
+SET_RG_GEMINIA_EN_LDO_VCO_VDD33	smac/hal/ssv6006c/ssv6006C_reg.h	11407;"	d
+SET_RG_GEMINIA_EN_LDO_XO_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	11801;"	d
+SET_RG_GEMINIA_EN_LDO_XO_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	11802;"	d
+SET_RG_GEMINIA_EN_RTC_CAL	smac/hal/ssv6006c/ssv6006C_reg.h	11845;"	d
+SET_RG_GEMINIA_EN_RX_ADC	smac/hal/ssv6006c/ssv6006C_reg.h	11119;"	d
+SET_RG_GEMINIA_EN_RX_DIV2	smac/hal/ssv6006c/ssv6006C_reg.h	11111;"	d
+SET_RG_GEMINIA_EN_RX_FILTER	smac/hal/ssv6006c/ssv6006C_reg.h	11117;"	d
+SET_RG_GEMINIA_EN_RX_IQCAL	smac/hal/ssv6006c/ssv6006C_reg.h	11146;"	d
+SET_RG_GEMINIA_EN_RX_LNA	smac/hal/ssv6006c/ssv6006C_reg.h	11107;"	d
+SET_RG_GEMINIA_EN_RX_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	11113;"	d
+SET_RG_GEMINIA_EN_RX_MIXER	smac/hal/ssv6006c/ssv6006C_reg.h	11109;"	d
+SET_RG_GEMINIA_EN_RX_PADSW	smac/hal/ssv6006c/ssv6006C_reg.h	11159;"	d
+SET_RG_GEMINIA_EN_RX_RSSI	smac/hal/ssv6006c/ssv6006C_reg.h	11121;"	d
+SET_RG_GEMINIA_EN_RX_RSSI_TESTNODE	smac/hal/ssv6006c/ssv6006C_reg.h	11212;"	d
+SET_RG_GEMINIA_EN_RX_TESTNODE	smac/hal/ssv6006c/ssv6006C_reg.h	11158;"	d
+SET_RG_GEMINIA_EN_RX_TZ	smac/hal/ssv6006c/ssv6006C_reg.h	11115;"	d
+SET_RG_GEMINIA_EN_SARADC	smac/hal/ssv6006c/ssv6006C_reg.h	11151;"	d
+SET_RG_GEMINIA_EN_SAR_TEST	smac/hal/ssv6006c/ssv6006C_reg.h	11342;"	d
+SET_RG_GEMINIA_EN_SX_CP	smac/hal/ssv6006c/ssv6006C_reg.h	11374;"	d
+SET_RG_GEMINIA_EN_SX_CP_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	11373;"	d
+SET_RG_GEMINIA_EN_SX_DITHER	smac/hal/ssv6006c/ssv6006C_reg.h	11488;"	d
+SET_RG_GEMINIA_EN_SX_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	11376;"	d
+SET_RG_GEMINIA_EN_SX_DIV_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	11375;"	d
+SET_RG_GEMINIA_EN_SX_LDO_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	11398;"	d
+SET_RG_GEMINIA_EN_SX_MOD	smac/hal/ssv6006c/ssv6006C_reg.h	11487;"	d
+SET_RG_GEMINIA_EN_SX_VCO	smac/hal/ssv6006c/ssv6006C_reg.h	11378;"	d
+SET_RG_GEMINIA_EN_SX_VCOMON	smac/hal/ssv6006c/ssv6006C_reg.h	11481;"	d
+SET_RG_GEMINIA_EN_SX_VCO_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	11377;"	d
+SET_RG_GEMINIA_EN_TX_BT_PA	smac/hal/ssv6006c/ssv6006C_reg.h	11133;"	d
+SET_RG_GEMINIA_EN_TX_DAC	smac/hal/ssv6006c/ssv6006C_reg.h	11127;"	d
+SET_RG_GEMINIA_EN_TX_DAC_CAL	smac/hal/ssv6006c/ssv6006C_reg.h	11140;"	d
+SET_RG_GEMINIA_EN_TX_DAC_OUT	smac/hal/ssv6006c/ssv6006C_reg.h	11155;"	d
+SET_RG_GEMINIA_EN_TX_DAC_VOUT	smac/hal/ssv6006c/ssv6006C_reg.h	11156;"	d
+SET_RG_GEMINIA_EN_TX_DIV2	smac/hal/ssv6006c/ssv6006C_reg.h	11129;"	d
+SET_RG_GEMINIA_EN_TX_DIV2_BUF	smac/hal/ssv6006c/ssv6006C_reg.h	11131;"	d
+SET_RG_GEMINIA_EN_TX_DPD	smac/hal/ssv6006c/ssv6006C_reg.h	11148;"	d
+SET_RG_GEMINIA_EN_TX_MOD	smac/hal/ssv6006c/ssv6006C_reg.h	11125;"	d
+SET_RG_GEMINIA_EN_TX_PA	smac/hal/ssv6006c/ssv6006C_reg.h	11123;"	d
+SET_RG_GEMINIA_EN_TX_SELF_MIXER	smac/hal/ssv6006c/ssv6006C_reg.h	11144;"	d
+SET_RG_GEMINIA_EN_TX_TRSW	smac/hal/ssv6006c/ssv6006C_reg.h	11105;"	d
+SET_RG_GEMINIA_EN_TX_TSSI	smac/hal/ssv6006c/ssv6006C_reg.h	11150;"	d
+SET_RG_GEMINIA_EN_TX_VTOI_2ND	smac/hal/ssv6006c/ssv6006C_reg.h	11152;"	d
+SET_RG_GEMINIA_EN_VCOBF_DIVCK	smac/hal/ssv6006c/ssv6006C_reg.h	11392;"	d
+SET_RG_GEMINIA_EN_VCOBF_DIVCK_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	11391;"	d
+SET_RG_GEMINIA_EN_VCOBF_RXMB	smac/hal/ssv6006c/ssv6006C_reg.h	11388;"	d
+SET_RG_GEMINIA_EN_VCOBF_RXMB_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	11387;"	d
+SET_RG_GEMINIA_EN_VCOBF_RXOB	smac/hal/ssv6006c/ssv6006C_reg.h	11390;"	d
+SET_RG_GEMINIA_EN_VCOBF_RXOB_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	11389;"	d
+SET_RG_GEMINIA_EN_VCOBF_TXMB	smac/hal/ssv6006c/ssv6006C_reg.h	11384;"	d
+SET_RG_GEMINIA_EN_VCOBF_TXMB_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	11383;"	d
+SET_RG_GEMINIA_EN_VCOBF_TXOB	smac/hal/ssv6006c/ssv6006C_reg.h	11386;"	d
+SET_RG_GEMINIA_EN_VCOBF_TXOB_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	11385;"	d
+SET_RG_GEMINIA_EN_XOTEST	smac/hal/ssv6006c/ssv6006C_reg.h	11809;"	d
+SET_RG_GEMINIA_EXT_DAC_EN	smac/hal/ssv6006c/ssv6006C_reg.h	11762;"	d
+SET_RG_GEMINIA_EXT_MCU_PWRUP	smac/hal/ssv6006c/ssv6006C_reg.h	11936;"	d
+SET_RG_GEMINIA_FDB_BYPASS	smac/hal/ssv6006c/ssv6006C_reg.h	11807;"	d
+SET_RG_GEMINIA_FDB_CDELAY_MUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11815;"	d
+SET_RG_GEMINIA_FDB_DUTY_LTH	smac/hal/ssv6006c/ssv6006C_reg.h	11808;"	d
+SET_RG_GEMINIA_FDB_FDELAY_MUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11816;"	d
+SET_RG_GEMINIA_FDB_PHASESWAP_MUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11814;"	d
+SET_RG_GEMINIA_FDB_RDELAYF	smac/hal/ssv6006c/ssv6006C_reg.h	11819;"	d
+SET_RG_GEMINIA_FDB_RDELAYS	smac/hal/ssv6006c/ssv6006C_reg.h	11820;"	d
+SET_RG_GEMINIA_FDB_RECAL_TIMMER	smac/hal/ssv6006c/ssv6006C_reg.h	11821;"	d
+SET_RG_GEMINIA_FPGA_CLK_REF_40M_DS	smac/hal/ssv6006c/ssv6006C_reg.h	11881;"	d
+SET_RG_GEMINIA_FPGA_CLK_REF_40M_OE	smac/hal/ssv6006c/ssv6006C_reg.h	11883;"	d
+SET_RG_GEMINIA_FPGA_CLK_REF_40M_PD	smac/hal/ssv6006c/ssv6006C_reg.h	11882;"	d
+SET_RG_GEMINIA_GPIO00_DS	smac/hal/ssv6006c/ssv6006C_reg.h	11908;"	d
+SET_RG_GEMINIA_GPIO00_OE	smac/hal/ssv6006c/ssv6006C_reg.h	11910;"	d
+SET_RG_GEMINIA_GPIO00_PD	smac/hal/ssv6006c/ssv6006C_reg.h	11909;"	d
+SET_RG_GEMINIA_GPIO01_DS	smac/hal/ssv6006c/ssv6006C_reg.h	11911;"	d
+SET_RG_GEMINIA_GPIO01_OE	smac/hal/ssv6006c/ssv6006C_reg.h	11913;"	d
+SET_RG_GEMINIA_GPIO01_PD	smac/hal/ssv6006c/ssv6006C_reg.h	11912;"	d
+SET_RG_GEMINIA_GPIO02_DS	smac/hal/ssv6006c/ssv6006C_reg.h	11914;"	d
+SET_RG_GEMINIA_GPIO02_OE	smac/hal/ssv6006c/ssv6006C_reg.h	11916;"	d
+SET_RG_GEMINIA_GPIO02_PD	smac/hal/ssv6006c/ssv6006C_reg.h	11915;"	d
+SET_RG_GEMINIA_GPIO03_DS	smac/hal/ssv6006c/ssv6006C_reg.h	11917;"	d
+SET_RG_GEMINIA_GPIO03_OE	smac/hal/ssv6006c/ssv6006C_reg.h	11919;"	d
+SET_RG_GEMINIA_GPIO03_PD	smac/hal/ssv6006c/ssv6006C_reg.h	11918;"	d
+SET_RG_GEMINIA_GPIO04_DS	smac/hal/ssv6006c/ssv6006C_reg.h	11920;"	d
+SET_RG_GEMINIA_GPIO04_OE	smac/hal/ssv6006c/ssv6006C_reg.h	11922;"	d
+SET_RG_GEMINIA_GPIO04_PD	smac/hal/ssv6006c/ssv6006C_reg.h	11921;"	d
+SET_RG_GEMINIA_GPIO05_DS	smac/hal/ssv6006c/ssv6006C_reg.h	11923;"	d
+SET_RG_GEMINIA_GPIO05_OE	smac/hal/ssv6006c/ssv6006C_reg.h	11925;"	d
+SET_RG_GEMINIA_GPIO05_PD	smac/hal/ssv6006c/ssv6006C_reg.h	11924;"	d
+SET_RG_GEMINIA_GPIO06_DS	smac/hal/ssv6006c/ssv6006C_reg.h	11926;"	d
+SET_RG_GEMINIA_GPIO06_OE	smac/hal/ssv6006c/ssv6006C_reg.h	11928;"	d
+SET_RG_GEMINIA_GPIO06_PD	smac/hal/ssv6006c/ssv6006C_reg.h	11927;"	d
+SET_RG_GEMINIA_GPIO07_DS	smac/hal/ssv6006c/ssv6006C_reg.h	11929;"	d
+SET_RG_GEMINIA_GPIO07_OE	smac/hal/ssv6006c/ssv6006C_reg.h	11931;"	d
+SET_RG_GEMINIA_GPIO07_PD	smac/hal/ssv6006c/ssv6006C_reg.h	11930;"	d
+SET_RG_GEMINIA_GPIO08_DS	smac/hal/ssv6006c/ssv6006C_reg.h	11884;"	d
+SET_RG_GEMINIA_GPIO08_OE	smac/hal/ssv6006c/ssv6006C_reg.h	11886;"	d
+SET_RG_GEMINIA_GPIO08_PD	smac/hal/ssv6006c/ssv6006C_reg.h	11885;"	d
+SET_RG_GEMINIA_GPIO09_DS	smac/hal/ssv6006c/ssv6006C_reg.h	11887;"	d
+SET_RG_GEMINIA_GPIO09_OE	smac/hal/ssv6006c/ssv6006C_reg.h	11889;"	d
+SET_RG_GEMINIA_GPIO09_PD	smac/hal/ssv6006c/ssv6006C_reg.h	11888;"	d
+SET_RG_GEMINIA_GPIO10_DS	smac/hal/ssv6006c/ssv6006C_reg.h	11890;"	d
+SET_RG_GEMINIA_GPIO10_OE	smac/hal/ssv6006c/ssv6006C_reg.h	11892;"	d
+SET_RG_GEMINIA_GPIO10_PD	smac/hal/ssv6006c/ssv6006C_reg.h	11891;"	d
+SET_RG_GEMINIA_GPIO11_DS	smac/hal/ssv6006c/ssv6006C_reg.h	11893;"	d
+SET_RG_GEMINIA_GPIO11_OE	smac/hal/ssv6006c/ssv6006C_reg.h	11895;"	d
+SET_RG_GEMINIA_GPIO11_PD	smac/hal/ssv6006c/ssv6006C_reg.h	11894;"	d
+SET_RG_GEMINIA_GPIO12_DS	smac/hal/ssv6006c/ssv6006C_reg.h	11896;"	d
+SET_RG_GEMINIA_GPIO12_OE	smac/hal/ssv6006c/ssv6006C_reg.h	11898;"	d
+SET_RG_GEMINIA_GPIO12_PD	smac/hal/ssv6006c/ssv6006C_reg.h	11897;"	d
+SET_RG_GEMINIA_GPIO13_DS	smac/hal/ssv6006c/ssv6006C_reg.h	11899;"	d
+SET_RG_GEMINIA_GPIO13_OE	smac/hal/ssv6006c/ssv6006C_reg.h	11901;"	d
+SET_RG_GEMINIA_GPIO13_PD	smac/hal/ssv6006c/ssv6006C_reg.h	11900;"	d
+SET_RG_GEMINIA_GPIO14_DS	smac/hal/ssv6006c/ssv6006C_reg.h	11902;"	d
+SET_RG_GEMINIA_GPIO14_OE	smac/hal/ssv6006c/ssv6006C_reg.h	11904;"	d
+SET_RG_GEMINIA_GPIO14_PD	smac/hal/ssv6006c/ssv6006C_reg.h	11903;"	d
+SET_RG_GEMINIA_GPIO15_DS	smac/hal/ssv6006c/ssv6006C_reg.h	11905;"	d
+SET_RG_GEMINIA_GPIO15_OE	smac/hal/ssv6006c/ssv6006C_reg.h	11907;"	d
+SET_RG_GEMINIA_GPIO15_PD	smac/hal/ssv6006c/ssv6006C_reg.h	11906;"	d
+SET_RG_GEMINIA_GPIO16_DS	smac/hal/ssv6006c/ssv6006C_reg.h	11865;"	d
+SET_RG_GEMINIA_GPIO16_OE	smac/hal/ssv6006c/ssv6006C_reg.h	11867;"	d
+SET_RG_GEMINIA_GPIO16_PD	smac/hal/ssv6006c/ssv6006C_reg.h	11866;"	d
+SET_RG_GEMINIA_GPIO17_DS	smac/hal/ssv6006c/ssv6006C_reg.h	11868;"	d
+SET_RG_GEMINIA_GPIO17_OE	smac/hal/ssv6006c/ssv6006C_reg.h	11870;"	d
+SET_RG_GEMINIA_GPIO17_PD	smac/hal/ssv6006c/ssv6006C_reg.h	11869;"	d
+SET_RG_GEMINIA_GPIO18_DS	smac/hal/ssv6006c/ssv6006C_reg.h	11871;"	d
+SET_RG_GEMINIA_GPIO18_OE	smac/hal/ssv6006c/ssv6006C_reg.h	11873;"	d
+SET_RG_GEMINIA_GPIO18_PD	smac/hal/ssv6006c/ssv6006C_reg.h	11872;"	d
+SET_RG_GEMINIA_GPIO19_DS	smac/hal/ssv6006c/ssv6006C_reg.h	11874;"	d
+SET_RG_GEMINIA_GPIO19_OE	smac/hal/ssv6006c/ssv6006C_reg.h	11876;"	d
+SET_RG_GEMINIA_GPIO19_PD	smac/hal/ssv6006c/ssv6006C_reg.h	11875;"	d
+SET_RG_GEMINIA_GPIO20_DS	smac/hal/ssv6006c/ssv6006C_reg.h	11877;"	d
+SET_RG_GEMINIA_GPIO20_OE	smac/hal/ssv6006c/ssv6006C_reg.h	11879;"	d
+SET_RG_GEMINIA_GPIO20_PD	smac/hal/ssv6006c/ssv6006C_reg.h	11878;"	d
+SET_RG_GEMINIA_HS_3WIRE_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11093;"	d
+SET_RG_GEMINIA_HW_PINSEL	smac/hal/ssv6006c/ssv6006C_reg.h	11092;"	d
+SET_RG_GEMINIA_IDACAI_TZ0_COARSE0	smac/hal/ssv6006c/ssv6006C_reg.h	11623;"	d
+SET_RG_GEMINIA_IDACAI_TZ0_COARSE1	smac/hal/ssv6006c/ssv6006C_reg.h	11621;"	d
+SET_RG_GEMINIA_IDACAI_TZ0_COARSE2	smac/hal/ssv6006c/ssv6006C_reg.h	11619;"	d
+SET_RG_GEMINIA_IDACAI_TZ0_COARSE3	smac/hal/ssv6006c/ssv6006C_reg.h	11617;"	d
+SET_RG_GEMINIA_IDACAI_TZ0_COARSE4	smac/hal/ssv6006c/ssv6006C_reg.h	11615;"	d
+SET_RG_GEMINIA_IDACAI_TZ1_COARSE0	smac/hal/ssv6006c/ssv6006C_reg.h	11633;"	d
+SET_RG_GEMINIA_IDACAI_TZ1_COARSE1	smac/hal/ssv6006c/ssv6006C_reg.h	11631;"	d
+SET_RG_GEMINIA_IDACAI_TZ1_COARSE2	smac/hal/ssv6006c/ssv6006C_reg.h	11629;"	d
+SET_RG_GEMINIA_IDACAI_TZ1_COARSE3	smac/hal/ssv6006c/ssv6006C_reg.h	11627;"	d
+SET_RG_GEMINIA_IDACAI_TZ1_COARSE4	smac/hal/ssv6006c/ssv6006C_reg.h	11625;"	d
+SET_RG_GEMINIA_IDACAQ_TZ0_COARSE0	smac/hal/ssv6006c/ssv6006C_reg.h	11624;"	d
+SET_RG_GEMINIA_IDACAQ_TZ0_COARSE1	smac/hal/ssv6006c/ssv6006C_reg.h	11622;"	d
+SET_RG_GEMINIA_IDACAQ_TZ0_COARSE2	smac/hal/ssv6006c/ssv6006C_reg.h	11620;"	d
+SET_RG_GEMINIA_IDACAQ_TZ0_COARSE3	smac/hal/ssv6006c/ssv6006C_reg.h	11618;"	d
+SET_RG_GEMINIA_IDACAQ_TZ0_COARSE4	smac/hal/ssv6006c/ssv6006C_reg.h	11616;"	d
+SET_RG_GEMINIA_IDACAQ_TZ1_COARSE0	smac/hal/ssv6006c/ssv6006C_reg.h	11634;"	d
+SET_RG_GEMINIA_IDACAQ_TZ1_COARSE1	smac/hal/ssv6006c/ssv6006C_reg.h	11632;"	d
+SET_RG_GEMINIA_IDACAQ_TZ1_COARSE2	smac/hal/ssv6006c/ssv6006C_reg.h	11630;"	d
+SET_RG_GEMINIA_IDACAQ_TZ1_COARSE3	smac/hal/ssv6006c/ssv6006C_reg.h	11628;"	d
+SET_RG_GEMINIA_IDACAQ_TZ1_COARSE4	smac/hal/ssv6006c/ssv6006C_reg.h	11626;"	d
+SET_RG_GEMINIA_IQ_SWAP	smac/hal/ssv6006c/ssv6006C_reg.h	11752;"	d
+SET_RG_GEMINIA_I_INV	smac/hal/ssv6006c/ssv6006C_reg.h	11751;"	d
+SET_RG_GEMINIA_LDO_CP_FC	smac/hal/ssv6006c/ssv6006C_reg.h	11414;"	d
+SET_RG_GEMINIA_LDO_CP_FC_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	11413;"	d
+SET_RG_GEMINIA_LDO_DIV_FC	smac/hal/ssv6006c/ssv6006C_reg.h	11416;"	d
+SET_RG_GEMINIA_LDO_DIV_FC_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	11415;"	d
+SET_RG_GEMINIA_LDO_LEVEL_ABB	smac/hal/ssv6006c/ssv6006C_reg.h	11166;"	d
+SET_RG_GEMINIA_LDO_LEVEL_ADC	smac/hal/ssv6006c/ssv6006C_reg.h	11167;"	d
+SET_RG_GEMINIA_LDO_LEVEL_DAC	smac/hal/ssv6006c/ssv6006C_reg.h	11168;"	d
+SET_RG_GEMINIA_LDO_LEVEL_EFUSE	smac/hal/ssv6006c/ssv6006C_reg.h	11831;"	d
+SET_RG_GEMINIA_LDO_LEVEL_RX_FE	smac/hal/ssv6006c/ssv6006C_reg.h	11165;"	d
+SET_RG_GEMINIA_LDO_LO_FC	smac/hal/ssv6006c/ssv6006C_reg.h	11418;"	d
+SET_RG_GEMINIA_LDO_LO_FC_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	11417;"	d
+SET_RG_GEMINIA_LDO_RX_ABB_EN_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	11161;"	d
+SET_RG_GEMINIA_LDO_RX_ADC_EN_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	11162;"	d
+SET_RG_GEMINIA_LDO_RX_FE_EN_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	11160;"	d
+SET_RG_GEMINIA_LDO_TX_DAC_EN_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	11163;"	d
+SET_RG_GEMINIA_LDO_VCO_FC	smac/hal/ssv6006c/ssv6006C_reg.h	11420;"	d
+SET_RG_GEMINIA_LDO_VCO_FC_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	11419;"	d
+SET_RG_GEMINIA_LDO_VCO_RCF	smac/hal/ssv6006c/ssv6006C_reg.h	11421;"	d
+SET_RG_GEMINIA_LOAD_RFTABLE_RDY	smac/hal/ssv6006c/ssv6006C_reg.h	11823;"	d
+SET_RG_GEMINIA_LO_UP_CH	smac/hal/ssv6006c/ssv6006C_reg.h	11742;"	d
+SET_RG_GEMINIA_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	11099;"	d
+SET_RG_GEMINIA_MODE_LATCH_LMT	smac/hal/ssv6006c/ssv6006C_reg.h	11935;"	d
+SET_RG_GEMINIA_MODE_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11094;"	d
+SET_RG_GEMINIA_NFRAC_DELTA	smac/hal/ssv6006c/ssv6006C_reg.h	11740;"	d
+SET_RG_GEMINIA_PAD_MUX_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	11934;"	d
+SET_RG_GEMINIA_PGAG	smac/hal/ssv6006c/ssv6006C_reg.h	11102;"	d
+SET_RG_GEMINIA_PGAG_DPDCAL	smac/hal/ssv6006c/ssv6006C_reg.h	11726;"	d
+SET_RG_GEMINIA_PGAG_RCCAL	smac/hal/ssv6006c/ssv6006C_reg.h	11719;"	d
+SET_RG_GEMINIA_PGAG_RXIQCAL	smac/hal/ssv6006c/ssv6006C_reg.h	11723;"	d
+SET_RG_GEMINIA_PGAG_TXCAL	smac/hal/ssv6006c/ssv6006C_reg.h	11720;"	d
+SET_RG_GEMINIA_PHASE_17P5M	smac/hal/ssv6006c/ssv6006C_reg.h	11797;"	d
+SET_RG_GEMINIA_PHASE_1M	smac/hal/ssv6006c/ssv6006C_reg.h	11800;"	d
+SET_RG_GEMINIA_PHASE_2P5M	smac/hal/ssv6006c/ssv6006C_reg.h	11798;"	d
+SET_RG_GEMINIA_PHASE_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11784;"	d
+SET_RG_GEMINIA_PHASE_RXIQ_1M	smac/hal/ssv6006c/ssv6006C_reg.h	11799;"	d
+SET_RG_GEMINIA_PHASE_STEP_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	11783;"	d
+SET_RG_GEMINIA_PMU_ENTER_SLEEP_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	11851;"	d
+SET_RG_GEMINIA_Q_INV	smac/hal/ssv6006c/ssv6006C_reg.h	11750;"	d
+SET_RG_GEMINIA_RAM_00	smac/hal/ssv6006c/ssv6006C_reg.h	11937;"	d
+SET_RG_GEMINIA_RAM_01	smac/hal/ssv6006c/ssv6006C_reg.h	11938;"	d
+SET_RG_GEMINIA_RAM_02	smac/hal/ssv6006c/ssv6006C_reg.h	11939;"	d
+SET_RG_GEMINIA_RAM_03	smac/hal/ssv6006c/ssv6006C_reg.h	11940;"	d
+SET_RG_GEMINIA_RAM_04	smac/hal/ssv6006c/ssv6006C_reg.h	11941;"	d
+SET_RG_GEMINIA_RAM_05	smac/hal/ssv6006c/ssv6006C_reg.h	11942;"	d
+SET_RG_GEMINIA_RAM_06	smac/hal/ssv6006c/ssv6006C_reg.h	11943;"	d
+SET_RG_GEMINIA_RAM_07	smac/hal/ssv6006c/ssv6006C_reg.h	11944;"	d
+SET_RG_GEMINIA_RAM_08	smac/hal/ssv6006c/ssv6006C_reg.h	11945;"	d
+SET_RG_GEMINIA_RAM_09	smac/hal/ssv6006c/ssv6006C_reg.h	11946;"	d
+SET_RG_GEMINIA_RAM_10	smac/hal/ssv6006c/ssv6006C_reg.h	11947;"	d
+SET_RG_GEMINIA_RAM_11	smac/hal/ssv6006c/ssv6006C_reg.h	11948;"	d
+SET_RG_GEMINIA_RAM_12	smac/hal/ssv6006c/ssv6006C_reg.h	11949;"	d
+SET_RG_GEMINIA_RAM_13	smac/hal/ssv6006c/ssv6006C_reg.h	11950;"	d
+SET_RG_GEMINIA_RAM_14	smac/hal/ssv6006c/ssv6006C_reg.h	11951;"	d
+SET_RG_GEMINIA_RAM_15	smac/hal/ssv6006c/ssv6006C_reg.h	11952;"	d
+SET_RG_GEMINIA_RAM_16	smac/hal/ssv6006c/ssv6006C_reg.h	11953;"	d
+SET_RG_GEMINIA_RAM_17	smac/hal/ssv6006c/ssv6006C_reg.h	11954;"	d
+SET_RG_GEMINIA_RAM_18	smac/hal/ssv6006c/ssv6006C_reg.h	11955;"	d
+SET_RG_GEMINIA_RAM_19	smac/hal/ssv6006c/ssv6006C_reg.h	11956;"	d
+SET_RG_GEMINIA_RAM_20	smac/hal/ssv6006c/ssv6006C_reg.h	11957;"	d
+SET_RG_GEMINIA_RAM_21	smac/hal/ssv6006c/ssv6006C_reg.h	11958;"	d
+SET_RG_GEMINIA_RAM_22	smac/hal/ssv6006c/ssv6006C_reg.h	11959;"	d
+SET_RG_GEMINIA_RAM_23	smac/hal/ssv6006c/ssv6006C_reg.h	11960;"	d
+SET_RG_GEMINIA_RAM_24	smac/hal/ssv6006c/ssv6006C_reg.h	11961;"	d
+SET_RG_GEMINIA_RAM_25	smac/hal/ssv6006c/ssv6006C_reg.h	11962;"	d
+SET_RG_GEMINIA_RAM_26	smac/hal/ssv6006c/ssv6006C_reg.h	11963;"	d
+SET_RG_GEMINIA_RAM_27	smac/hal/ssv6006c/ssv6006C_reg.h	11964;"	d
+SET_RG_GEMINIA_RAM_28	smac/hal/ssv6006c/ssv6006C_reg.h	11965;"	d
+SET_RG_GEMINIA_RAM_29	smac/hal/ssv6006c/ssv6006C_reg.h	11966;"	d
+SET_RG_GEMINIA_RAM_30	smac/hal/ssv6006c/ssv6006C_reg.h	11967;"	d
+SET_RG_GEMINIA_RAM_31	smac/hal/ssv6006c/ssv6006C_reg.h	11968;"	d
+SET_RG_GEMINIA_RCCAL_POLAR_INV	smac/hal/ssv6006c/ssv6006C_reg.h	11790;"	d
+SET_RG_GEMINIA_RFG	smac/hal/ssv6006c/ssv6006C_reg.h	11101;"	d
+SET_RG_GEMINIA_RFG_DPDCAL	smac/hal/ssv6006c/ssv6006C_reg.h	11725;"	d
+SET_RG_GEMINIA_RFG_RXIQCAL	smac/hal/ssv6006c/ssv6006C_reg.h	11722;"	d
+SET_RG_GEMINIA_RF_PHY_MODE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	11932;"	d
+SET_RG_GEMINIA_RF_PHY_MODE_WIFI_MAC	smac/hal/ssv6006c/ssv6006C_reg.h	11933;"	d
+SET_RG_GEMINIA_RSSI_CLOCK_GATING	smac/hal/ssv6006c/ssv6006C_reg.h	11205;"	d
+SET_RG_GEMINIA_RSSI_EDGE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	11748;"	d
+SET_RG_GEMINIA_RTC_CAL_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	11842;"	d
+SET_RG_GEMINIA_RTC_CAL_TARGET_COUNT	smac/hal/ssv6006c/ssv6006C_reg.h	11840;"	d
+SET_RG_GEMINIA_RTC_EN	smac/hal/ssv6006c/ssv6006C_reg.h	11852;"	d
+SET_RG_GEMINIA_RTC_INT_ALARM_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	11857;"	d
+SET_RG_GEMINIA_RTC_INT_SEC_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	11856;"	d
+SET_RG_GEMINIA_RTC_OFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	11839;"	d
+SET_RG_GEMINIA_RTC_OSC_RES_SW_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11841;"	d
+SET_RG_GEMINIA_RTC_OSC_RES_SW_MANUAL_EN	smac/hal/ssv6006c/ssv6006C_reg.h	11844;"	d
+SET_RG_GEMINIA_RTC_RS1	smac/hal/ssv6006c/ssv6006C_reg.h	11836;"	d
+SET_RG_GEMINIA_RTC_RS2	smac/hal/ssv6006c/ssv6006C_reg.h	11837;"	d
+SET_RG_GEMINIA_RTC_SEC_ALARM_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	11861;"	d
+SET_RG_GEMINIA_RTC_SEC_START_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	11860;"	d
+SET_RG_GEMINIA_RXIQ_NOSHRK	smac/hal/ssv6006c/ssv6006C_reg.h	11746;"	d
+SET_RG_GEMINIA_RXRCCALQ_EN_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	11149;"	d
+SET_RG_GEMINIA_RXRF_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	11703;"	d
+SET_RG_GEMINIA_RXRF_R2T_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	11712;"	d
+SET_RG_GEMINIA_RXRF_T2R_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	11708;"	d
+SET_RG_GEMINIA_RX_ABBOUT_TRI_STATE	smac/hal/ssv6006c/ssv6006C_reg.h	11157;"	d
+SET_RG_GEMINIA_RX_ADCRSSI_CLKSEL	smac/hal/ssv6006c/ssv6006C_reg.h	11204;"	d
+SET_RG_GEMINIA_RX_ADCRSSI_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	11202;"	d
+SET_RG_GEMINIA_RX_ADC_CLKSEL	smac/hal/ssv6006c/ssv6006C_reg.h	11330;"	d
+SET_RG_GEMINIA_RX_ADC_DNLEN	smac/hal/ssv6006c/ssv6006C_reg.h	11331;"	d
+SET_RG_GEMINIA_RX_ADC_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11118;"	d
+SET_RG_GEMINIA_RX_ADC_METAEN	smac/hal/ssv6006c/ssv6006C_reg.h	11332;"	d
+SET_RG_GEMINIA_RX_ADC_TFLAG	smac/hal/ssv6006c/ssv6006C_reg.h	11333;"	d
+SET_RG_GEMINIA_RX_ADC_TSEL	smac/hal/ssv6006c/ssv6006C_reg.h	11334;"	d
+SET_RG_GEMINIA_RX_AGC	smac/hal/ssv6006c/ssv6006C_reg.h	11098;"	d
+SET_RG_GEMINIA_RX_DC_POLAR_INV	smac/hal/ssv6006c/ssv6006C_reg.h	11789;"	d
+SET_RG_GEMINIA_RX_DIV2_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11110;"	d
+SET_RG_GEMINIA_RX_FILTER_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11116;"	d
+SET_RG_GEMINIA_RX_GAIN_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11095;"	d
+SET_RG_GEMINIA_RX_IQCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	11718;"	d
+SET_RG_GEMINIA_RX_IQCAL_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11145;"	d
+SET_RG_GEMINIA_RX_IQ_ALPHA	smac/hal/ssv6006c/ssv6006C_reg.h	11743;"	d
+SET_RG_GEMINIA_RX_IQ_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11745;"	d
+SET_RG_GEMINIA_RX_IQ_THETA	smac/hal/ssv6006c/ssv6006C_reg.h	11744;"	d
+SET_RG_GEMINIA_RX_LNA_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11106;"	d
+SET_RG_GEMINIA_RX_LNA_SETTLE	smac/hal/ssv6006c/ssv6006C_reg.h	11214;"	d
+SET_RG_GEMINIA_RX_LNA_TRI_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	11213;"	d
+SET_RG_GEMINIA_RX_LOBUF_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11112;"	d
+SET_RG_GEMINIA_RX_MIXER_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11108;"	d
+SET_RG_GEMINIA_RX_RCCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	11715;"	d
+SET_RG_GEMINIA_RX_RCCAL_TARG	smac/hal/ssv6006c/ssv6006C_reg.h	11788;"	d
+SET_RG_GEMINIA_RX_REC_LPFCORNER	smac/hal/ssv6006c/ssv6006C_reg.h	11203;"	d
+SET_RG_GEMINIA_RX_RSSIADC_TH	smac/hal/ssv6006c/ssv6006C_reg.h	11747;"	d
+SET_RG_GEMINIA_RX_RSSI_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11120;"	d
+SET_RG_GEMINIA_RX_TZ_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11114;"	d
+SET_RG_GEMINIA_RX_TZ_OUT_TRISTATE	smac/hal/ssv6006c/ssv6006C_reg.h	11142;"	d
+SET_RG_GEMINIA_RX_TZ_OUT_TRISTATE_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11141;"	d
+SET_RG_GEMINIA_SARADC_THERMAL	smac/hal/ssv6006c/ssv6006C_reg.h	11343;"	d
+SET_RG_GEMINIA_SARADC_TSSI	smac/hal/ssv6006c/ssv6006C_reg.h	11344;"	d
+SET_RG_GEMINIA_SARADC_VRSEL	smac/hal/ssv6006c/ssv6006C_reg.h	11341;"	d
+SET_RG_GEMINIA_SEL_DPLL_CLK	smac/hal/ssv6006c/ssv6006C_reg.h	11843;"	d
+SET_RG_GEMINIA_SIGN_SWAP	smac/hal/ssv6006c/ssv6006C_reg.h	11753;"	d
+SET_RG_GEMINIA_SLEEP_WAKE_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	11850;"	d
+SET_RG_GEMINIA_SPECTRUM_BW	smac/hal/ssv6006c/ssv6006C_reg.h	11786;"	d
+SET_RG_GEMINIA_SPECTRUM_EN	smac/hal/ssv6006c/ssv6006C_reg.h	11787;"	d
+SET_RG_GEMINIA_SPIS_MISO_DS	smac/hal/ssv6006c/ssv6006C_reg.h	11880;"	d
+SET_RG_GEMINIA_SX_AAC_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	11395;"	d
+SET_RG_GEMINIA_SX_BTRX_SIDE	smac/hal/ssv6006c/ssv6006C_reg.h	11428;"	d
+SET_RG_GEMINIA_SX_CAL_INIT	smac/hal/ssv6006c/ssv6006C_reg.h	11397;"	d
+SET_RG_GEMINIA_SX_CHANNEL	smac/hal/ssv6006c/ssv6006C_reg.h	11430;"	d
+SET_RG_GEMINIA_SX_CP_IOST	smac/hal/ssv6006c/ssv6006C_reg.h	11438;"	d
+SET_RG_GEMINIA_SX_CP_IOST_POL	smac/hal/ssv6006c/ssv6006C_reg.h	11437;"	d
+SET_RG_GEMINIA_SX_CP_ISEL50U_BT	smac/hal/ssv6006c/ssv6006C_reg.h	11432;"	d
+SET_RG_GEMINIA_SX_CP_ISEL50U_WF	smac/hal/ssv6006c/ssv6006C_reg.h	11435;"	d
+SET_RG_GEMINIA_SX_CP_ISEL_BT	smac/hal/ssv6006c/ssv6006C_reg.h	11431;"	d
+SET_RG_GEMINIA_SX_CP_ISEL_WF	smac/hal/ssv6006c/ssv6006C_reg.h	11434;"	d
+SET_RG_GEMINIA_SX_CP_KP_DOUB_BT	smac/hal/ssv6006c/ssv6006C_reg.h	11433;"	d
+SET_RG_GEMINIA_SX_CP_KP_DOUB_WF	smac/hal/ssv6006c/ssv6006C_reg.h	11436;"	d
+SET_RG_GEMINIA_SX_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	11699;"	d
+SET_RG_GEMINIA_SX_DITHER_WEIGHT	smac/hal/ssv6006c/ssv6006C_reg.h	11490;"	d
+SET_RG_GEMINIA_SX_DIV_DMYBUF_EN	smac/hal/ssv6006c/ssv6006C_reg.h	11486;"	d
+SET_RG_GEMINIA_SX_DIV_PREVDD	smac/hal/ssv6006c/ssv6006C_reg.h	11482;"	d
+SET_RG_GEMINIA_SX_DIV_PSCVDD	smac/hal/ssv6006c/ssv6006C_reg.h	11483;"	d
+SET_RG_GEMINIA_SX_DIV_RST_H	smac/hal/ssv6006c/ssv6006C_reg.h	11484;"	d
+SET_RG_GEMINIA_SX_DIV_SDM_EDGE	smac/hal/ssv6006c/ssv6006C_reg.h	11485;"	d
+SET_RG_GEMINIA_SX_EN	smac/hal/ssv6006c/ssv6006C_reg.h	11372;"	d
+SET_RG_GEMINIA_SX_EN_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	11371;"	d
+SET_RG_GEMINIA_SX_FREF_DOUB	smac/hal/ssv6006c/ssv6006C_reg.h	11427;"	d
+SET_RG_GEMINIA_SX_LDO_CP_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	11169;"	d
+SET_RG_GEMINIA_SX_LDO_DIV_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	11173;"	d
+SET_RG_GEMINIA_SX_LDO_FCOFFT	smac/hal/ssv6006c/ssv6006C_reg.h	11412;"	d
+SET_RG_GEMINIA_SX_LDO_LO_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	11170;"	d
+SET_RG_GEMINIA_SX_LDO_VCO_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	11172;"	d
+SET_RG_GEMINIA_SX_LO_TIMES	smac/hal/ssv6006c/ssv6006C_reg.h	11429;"	d
+SET_RG_GEMINIA_SX_LPF_C1_BT	smac/hal/ssv6006c/ssv6006C_reg.h	11446;"	d
+SET_RG_GEMINIA_SX_LPF_C1_WF	smac/hal/ssv6006c/ssv6006C_reg.h	11451;"	d
+SET_RG_GEMINIA_SX_LPF_C2_BT	smac/hal/ssv6006c/ssv6006C_reg.h	11447;"	d
+SET_RG_GEMINIA_SX_LPF_C2_WF	smac/hal/ssv6006c/ssv6006C_reg.h	11452;"	d
+SET_RG_GEMINIA_SX_LPF_C3_BT	smac/hal/ssv6006c/ssv6006C_reg.h	11448;"	d
+SET_RG_GEMINIA_SX_LPF_C3_WF	smac/hal/ssv6006c/ssv6006C_reg.h	11453;"	d
+SET_RG_GEMINIA_SX_LPF_R2_BT	smac/hal/ssv6006c/ssv6006C_reg.h	11449;"	d
+SET_RG_GEMINIA_SX_LPF_R2_WF	smac/hal/ssv6006c/ssv6006C_reg.h	11454;"	d
+SET_RG_GEMINIA_SX_LPF_R3_BT	smac/hal/ssv6006c/ssv6006C_reg.h	11450;"	d
+SET_RG_GEMINIA_SX_LPF_R3_WF	smac/hal/ssv6006c/ssv6006C_reg.h	11455;"	d
+SET_RG_GEMINIA_SX_LPF_VTUNE_TEST	smac/hal/ssv6006c/ssv6006C_reg.h	11520;"	d
+SET_RG_GEMINIA_SX_MOD_ORDER	smac/hal/ssv6006c/ssv6006C_reg.h	11489;"	d
+SET_RG_GEMINIA_SX_PFD_RST	smac/hal/ssv6006c/ssv6006C_reg.h	11380;"	d
+SET_RG_GEMINIA_SX_PFD_RST_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	11379;"	d
+SET_RG_GEMINIA_SX_PFD_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	11439;"	d
+SET_RG_GEMINIA_SX_PFD_SET	smac/hal/ssv6006c/ssv6006C_reg.h	11440;"	d
+SET_RG_GEMINIA_SX_PFD_SET1	smac/hal/ssv6006c/ssv6006C_reg.h	11441;"	d
+SET_RG_GEMINIA_SX_PFD_SET2	smac/hal/ssv6006c/ssv6006C_reg.h	11442;"	d
+SET_RG_GEMINIA_SX_PFD_TLSEL	smac/hal/ssv6006c/ssv6006C_reg.h	11445;"	d
+SET_RG_GEMINIA_SX_PFD_TRDN	smac/hal/ssv6006c/ssv6006C_reg.h	11444;"	d
+SET_RG_GEMINIA_SX_PFD_TRUP	smac/hal/ssv6006c/ssv6006C_reg.h	11443;"	d
+SET_RG_GEMINIA_SX_RFCH_MAP_EN	smac/hal/ssv6006c/ssv6006C_reg.h	11425;"	d
+SET_RG_GEMINIA_SX_RFCTRL_CH_10_8	smac/hal/ssv6006c/ssv6006C_reg.h	11424;"	d
+SET_RG_GEMINIA_SX_RFCTRL_CH_7_0	smac/hal/ssv6006c/ssv6006C_reg.h	11423;"	d
+SET_RG_GEMINIA_SX_RFCTRL_F	smac/hal/ssv6006c/ssv6006C_reg.h	11422;"	d
+SET_RG_GEMINIA_SX_SBCAL_AW	smac/hal/ssv6006c/ssv6006C_reg.h	11394;"	d
+SET_RG_GEMINIA_SX_SBCAL_CT	smac/hal/ssv6006c/ssv6006C_reg.h	11494;"	d
+SET_RG_GEMINIA_SX_SBCAL_DIFFMIN	smac/hal/ssv6006c/ssv6006C_reg.h	11496;"	d
+SET_RG_GEMINIA_SX_SBCAL_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	11393;"	d
+SET_RG_GEMINIA_SX_SBCAL_NTARG	smac/hal/ssv6006c/ssv6006C_reg.h	11498;"	d
+SET_RG_GEMINIA_SX_SBCAL_NTARG_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	11497;"	d
+SET_RG_GEMINIA_SX_SBCAL_WT	smac/hal/ssv6006c/ssv6006C_reg.h	11495;"	d
+SET_RG_GEMINIA_SX_SUB_C0P5_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	11493;"	d
+SET_RG_GEMINIA_SX_SUB_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	11492;"	d
+SET_RG_GEMINIA_SX_SUB_SEL_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	11491;"	d
+SET_RG_GEMINIA_SX_TTL_ACCUM	smac/hal/ssv6006c/ssv6006C_reg.h	11515;"	d
+SET_RG_GEMINIA_SX_TTL_CPT	smac/hal/ssv6006c/ssv6006C_reg.h	11514;"	d
+SET_RG_GEMINIA_SX_TTL_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	11396;"	d
+SET_RG_GEMINIA_SX_TTL_FPT	smac/hal/ssv6006c/ssv6006C_reg.h	11513;"	d
+SET_RG_GEMINIA_SX_TTL_INIT	smac/hal/ssv6006c/ssv6006C_reg.h	11512;"	d
+SET_RG_GEMINIA_SX_TTL_SUB	smac/hal/ssv6006c/ssv6006C_reg.h	11516;"	d
+SET_RG_GEMINIA_SX_TTL_SUB_INV	smac/hal/ssv6006c/ssv6006C_reg.h	11517;"	d
+SET_RG_GEMINIA_SX_TTL_VH	smac/hal/ssv6006c/ssv6006C_reg.h	11518;"	d
+SET_RG_GEMINIA_SX_TTL_VL	smac/hal/ssv6006c/ssv6006C_reg.h	11519;"	d
+SET_RG_GEMINIA_SX_UOP_EN	smac/hal/ssv6006c/ssv6006C_reg.h	11382;"	d
+SET_RG_GEMINIA_SX_UOP_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	11381;"	d
+SET_RG_GEMINIA_SX_VCO_CS_AWH	smac/hal/ssv6006c/ssv6006C_reg.h	11467;"	d
+SET_RG_GEMINIA_SX_VCO_ISEL_BT	smac/hal/ssv6006c/ssv6006C_reg.h	11457;"	d
+SET_RG_GEMINIA_SX_VCO_ISEL_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	11456;"	d
+SET_RG_GEMINIA_SX_VCO_ISEL_WF	smac/hal/ssv6006c/ssv6006C_reg.h	11461;"	d
+SET_RG_GEMINIA_SX_VCO_KVDOUB_BT	smac/hal/ssv6006c/ssv6006C_reg.h	11460;"	d
+SET_RG_GEMINIA_SX_VCO_KVDOUB_WF	smac/hal/ssv6006c/ssv6006C_reg.h	11464;"	d
+SET_RG_GEMINIA_SX_VCO_LPM_BT	smac/hal/ssv6006c/ssv6006C_reg.h	11458;"	d
+SET_RG_GEMINIA_SX_VCO_LPM_WF	smac/hal/ssv6006c/ssv6006C_reg.h	11462;"	d
+SET_RG_GEMINIA_SX_VCO_RTAIL_SHIFT	smac/hal/ssv6006c/ssv6006C_reg.h	11466;"	d
+SET_RG_GEMINIA_SX_VCO_RXOB_AW	smac/hal/ssv6006c/ssv6006C_reg.h	11478;"	d
+SET_RG_GEMINIA_SX_VCO_TXOB_AW	smac/hal/ssv6006c/ssv6006C_reg.h	11477;"	d
+SET_RG_GEMINIA_SX_VCO_VARBSEL	smac/hal/ssv6006c/ssv6006C_reg.h	11465;"	d
+SET_RG_GEMINIA_SX_VCO_VCCBSEL_BT	smac/hal/ssv6006c/ssv6006C_reg.h	11459;"	d
+SET_RG_GEMINIA_SX_VCO_VCCBSEL_WF	smac/hal/ssv6006c/ssv6006C_reg.h	11463;"	d
+SET_RG_GEMINIA_SX_XTAL_FREQ	smac/hal/ssv6006c/ssv6006C_reg.h	11426;"	d
+SET_RG_GEMINIA_TONE_SCALE	smac/hal/ssv6006c/ssv6006C_reg.h	11759;"	d
+SET_RG_GEMINIA_TXBTPA_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	11704;"	d
+SET_RG_GEMINIA_TXDAC_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	11700;"	d
+SET_RG_GEMINIA_TXDAC_R2T_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	11709;"	d
+SET_RG_GEMINIA_TXDAC_T2R_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	11705;"	d
+SET_RG_GEMINIA_TXGAIN_PHYCTRL	smac/hal/ssv6006c/ssv6006C_reg.h	11097;"	d
+SET_RG_GEMINIA_TXIQ_NOSHRK	smac/hal/ssv6006c/ssv6006C_reg.h	11757;"	d
+SET_RG_GEMINIA_TXLPF_BYPASS	smac/hal/ssv6006c/ssv6006C_reg.h	11153;"	d
+SET_RG_GEMINIA_TXLPF_GMCELL	smac/hal/ssv6006c/ssv6006C_reg.h	11235;"	d
+SET_RG_GEMINIA_TXMOD_GMCELL	smac/hal/ssv6006c/ssv6006C_reg.h	11234;"	d
+SET_RG_GEMINIA_TXPA_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	11702;"	d
+SET_RG_GEMINIA_TXPA_R2T_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	11711;"	d
+SET_RG_GEMINIA_TXPA_T2R_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	11707;"	d
+SET_RG_GEMINIA_TXPGA_MAIN	smac/hal/ssv6006c/ssv6006C_reg.h	11232;"	d
+SET_RG_GEMINIA_TXPGA_STEER	smac/hal/ssv6006c/ssv6006C_reg.h	11233;"	d
+SET_RG_GEMINIA_TXRF_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	11701;"	d
+SET_RG_GEMINIA_TXRF_R2T_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	11710;"	d
+SET_RG_GEMINIA_TXRF_T2R_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	11706;"	d
+SET_RG_GEMINIA_TX_BT_PA_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11132;"	d
+SET_RG_GEMINIA_TX_DAC_CAL_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11139;"	d
+SET_RG_GEMINIA_TX_DAC_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11126;"	d
+SET_RG_GEMINIA_TX_DAC_TSEL	smac/hal/ssv6006c/ssv6006C_reg.h	11358;"	d
+SET_RG_GEMINIA_TX_DIV2_BUF_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11130;"	d
+SET_RG_GEMINIA_TX_DIV2_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11128;"	d
+SET_RG_GEMINIA_TX_DPDGM_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	11206;"	d
+SET_RG_GEMINIA_TX_DPD_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	11207;"	d
+SET_RG_GEMINIA_TX_DPD_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11147;"	d
+SET_RG_GEMINIA_TX_EN_VOLTAGE_IN	smac/hal/ssv6006c/ssv6006C_reg.h	11154;"	d
+SET_RG_GEMINIA_TX_FREQ_OFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	11758;"	d
+SET_RG_GEMINIA_TX_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	11103;"	d
+SET_RG_GEMINIA_TX_GAIN_DPDCAL	smac/hal/ssv6006c/ssv6006C_reg.h	11727;"	d
+SET_RG_GEMINIA_TX_GAIN_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11096;"	d
+SET_RG_GEMINIA_TX_GAIN_RXIQCAL	smac/hal/ssv6006c/ssv6006C_reg.h	11724;"	d
+SET_RG_GEMINIA_TX_GAIN_TXCAL	smac/hal/ssv6006c/ssv6006C_reg.h	11721;"	d
+SET_RG_GEMINIA_TX_IQCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	11717;"	d
+SET_RG_GEMINIA_TX_IQ_ALPHA	smac/hal/ssv6006c/ssv6006C_reg.h	11754;"	d
+SET_RG_GEMINIA_TX_IQ_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11756;"	d
+SET_RG_GEMINIA_TX_IQ_THETA	smac/hal/ssv6006c/ssv6006C_reg.h	11755;"	d
+SET_RG_GEMINIA_TX_LOCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	11716;"	d
+SET_RG_GEMINIA_TX_MOD_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11124;"	d
+SET_RG_GEMINIA_TX_PA_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11122;"	d
+SET_RG_GEMINIA_TX_SELF_MIXER_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11143;"	d
+SET_RG_GEMINIA_TX_TRSW_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11104;"	d
+SET_RG_GEMINIA_TX_TSSI_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	11208;"	d
+SET_RG_GEMINIA_TX_TSSI_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	11209;"	d
+SET_RG_GEMINIA_TX_TSSI_TEST	smac/hal/ssv6006c/ssv6006C_reg.h	11210;"	d
+SET_RG_GEMINIA_TX_TSSI_TESTMODE	smac/hal/ssv6006c/ssv6006C_reg.h	11211;"	d
+SET_RG_GEMINIA_TX_UP8X_MAN_EN	smac/hal/ssv6006c/ssv6006C_reg.h	11760;"	d
+SET_RG_GEMINIA_TX_VTOI_CURRENT	smac/hal/ssv6006c/ssv6006C_reg.h	11238;"	d
+SET_RG_GEMINIA_TX_VTOI_FS	smac/hal/ssv6006c/ssv6006C_reg.h	11241;"	d
+SET_RG_GEMINIA_TX_VTOI_GM	smac/hal/ssv6006c/ssv6006C_reg.h	11239;"	d
+SET_RG_GEMINIA_TX_VTOI_OPTION	smac/hal/ssv6006c/ssv6006C_reg.h	11240;"	d
+SET_RG_GEMINIA_VOBF_CAPIMB	smac/hal/ssv6006c/ssv6006C_reg.h	11480;"	d
+SET_RG_GEMINIA_VOBF_CAPIMB_POL	smac/hal/ssv6006c/ssv6006C_reg.h	11479;"	d
+SET_RG_GEMINIA_VOBF_DIVBFSEL	smac/hal/ssv6006c/ssv6006C_reg.h	11476;"	d
+SET_RG_GEMINIA_VOBF_RXMBSEL_BT	smac/hal/ssv6006c/ssv6006C_reg.h	11470;"	d
+SET_RG_GEMINIA_VOBF_RXMBSEL_WF	smac/hal/ssv6006c/ssv6006C_reg.h	11474;"	d
+SET_RG_GEMINIA_VOBF_RXOBSEL_BT	smac/hal/ssv6006c/ssv6006C_reg.h	11471;"	d
+SET_RG_GEMINIA_VOBF_RXOBSEL_WF	smac/hal/ssv6006c/ssv6006C_reg.h	11475;"	d
+SET_RG_GEMINIA_VOBF_TXMBSEL_BT	smac/hal/ssv6006c/ssv6006C_reg.h	11468;"	d
+SET_RG_GEMINIA_VOBF_TXMBSEL_WF	smac/hal/ssv6006c/ssv6006C_reg.h	11472;"	d
+SET_RG_GEMINIA_VOBF_TXOBSEL_BT	smac/hal/ssv6006c/ssv6006C_reg.h	11469;"	d
+SET_RG_GEMINIA_VOBF_TXOBSEL_WF	smac/hal/ssv6006c/ssv6006C_reg.h	11473;"	d
+SET_RG_GEMINIA_VO_AAC_EN	smac/hal/ssv6006c/ssv6006C_reg.h	11507;"	d
+SET_RG_GEMINIA_VO_AAC_EN_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	11506;"	d
+SET_RG_GEMINIA_VO_AAC_EVA	smac/hal/ssv6006c/ssv6006C_reg.h	11509;"	d
+SET_RG_GEMINIA_VO_AAC_EVA_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	11508;"	d
+SET_RG_GEMINIA_VO_AAC_EVA_TS	smac/hal/ssv6006c/ssv6006C_reg.h	11505;"	d
+SET_RG_GEMINIA_VO_AAC_IMAX	smac/hal/ssv6006c/ssv6006C_reg.h	11503;"	d
+SET_RG_GEMINIA_VO_AAC_INIT	smac/hal/ssv6006c/ssv6006C_reg.h	11504;"	d
+SET_RG_GEMINIA_VO_AAC_IOST_BT	smac/hal/ssv6006c/ssv6006C_reg.h	11500;"	d
+SET_RG_GEMINIA_VO_AAC_IOST_WF	smac/hal/ssv6006c/ssv6006C_reg.h	11502;"	d
+SET_RG_GEMINIA_VO_AAC_TAR_BT	smac/hal/ssv6006c/ssv6006C_reg.h	11499;"	d
+SET_RG_GEMINIA_VO_AAC_TAR_WF	smac/hal/ssv6006c/ssv6006C_reg.h	11501;"	d
+SET_RG_GEMINIA_VO_AAC_TEST_EN	smac/hal/ssv6006c/ssv6006C_reg.h	11510;"	d
+SET_RG_GEMINIA_VO_AAC_TEST_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	11511;"	d
+SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	11581;"	d
+SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	11579;"	d
+SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	11561;"	d
+SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	11559;"	d
+SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	11557;"	d
+SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	11555;"	d
+SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	11553;"	d
+SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	11551;"	d
+SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	11577;"	d
+SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	11575;"	d
+SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	11573;"	d
+SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	11571;"	d
+SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	11569;"	d
+SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	11567;"	d
+SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	11565;"	d
+SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	11563;"	d
+SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	11613;"	d
+SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	11611;"	d
+SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	11593;"	d
+SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	11591;"	d
+SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	11589;"	d
+SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	11587;"	d
+SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	11585;"	d
+SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	11583;"	d
+SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	11609;"	d
+SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	11607;"	d
+SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	11605;"	d
+SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	11603;"	d
+SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	11601;"	d
+SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	11599;"	d
+SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	11597;"	d
+SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	11595;"	d
+SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	11582;"	d
+SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	11580;"	d
+SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	11562;"	d
+SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	11560;"	d
+SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	11558;"	d
+SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	11556;"	d
+SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	11554;"	d
+SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	11552;"	d
+SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	11578;"	d
+SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	11576;"	d
+SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	11574;"	d
+SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	11572;"	d
+SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	11570;"	d
+SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	11568;"	d
+SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	11566;"	d
+SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	11564;"	d
+SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	11614;"	d
+SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	11612;"	d
+SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	11594;"	d
+SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	11592;"	d
+SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	11590;"	d
+SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	11588;"	d
+SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	11586;"	d
+SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	11584;"	d
+SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	11610;"	d
+SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	11608;"	d
+SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	11606;"	d
+SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	11604;"	d
+SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	11602;"	d
+SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	11600;"	d
+SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	11598;"	d
+SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	11596;"	d
+SET_RG_GEMINIA_WF_PABIAS_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	11224;"	d
+SET_RG_GEMINIA_WF_PACELL_EN	smac/hal/ssv6006c/ssv6006C_reg.h	11223;"	d
+SET_RG_GEMINIA_WF_RX_ABBCFIX	smac/hal/ssv6006c/ssv6006C_reg.h	11180;"	d
+SET_RG_GEMINIA_WF_RX_ABBCTUNEI	smac/hal/ssv6006c/ssv6006C_reg.h	11174;"	d
+SET_RG_GEMINIA_WF_RX_ABBCTUNEQ	smac/hal/ssv6006c/ssv6006C_reg.h	11175;"	d
+SET_RG_GEMINIA_WF_RX_ABB_BT_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	11182;"	d
+SET_RG_GEMINIA_WF_RX_ABB_IDIV3	smac/hal/ssv6006c/ssv6006C_reg.h	11183;"	d
+SET_RG_GEMINIA_WF_RX_ABB_N_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	11181;"	d
+SET_RG_GEMINIA_WF_RX_ADC_CLOAD	smac/hal/ssv6006c/ssv6006C_reg.h	11337;"	d
+SET_RG_GEMINIA_WF_RX_ADC_ICMP	smac/hal/ssv6006c/ssv6006C_reg.h	11335;"	d
+SET_RG_GEMINIA_WF_RX_ADC_VCMI	smac/hal/ssv6006c/ssv6006C_reg.h	11336;"	d
+SET_RG_GEMINIA_WF_RX_DCCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	11713;"	d
+SET_RG_GEMINIA_WF_RX_EN_IDACA_COARSE	smac/hal/ssv6006c/ssv6006C_reg.h	11184;"	d
+SET_RG_GEMINIA_WF_RX_EN_LOOPA	smac/hal/ssv6006c/ssv6006C_reg.h	11185;"	d
+SET_RG_GEMINIA_WF_RX_FILTERI1ST	smac/hal/ssv6006c/ssv6006C_reg.h	11177;"	d
+SET_RG_GEMINIA_WF_RX_FILTERI2ND	smac/hal/ssv6006c/ssv6006C_reg.h	11178;"	d
+SET_RG_GEMINIA_WF_RX_FILTERI3RD	smac/hal/ssv6006c/ssv6006C_reg.h	11179;"	d
+SET_RG_GEMINIA_WF_RX_FILTERI_COARSE	smac/hal/ssv6006c/ssv6006C_reg.h	11176;"	d
+SET_RG_GEMINIA_WF_RX_FILTERVCM	smac/hal/ssv6006c/ssv6006C_reg.h	11186;"	d
+SET_RG_GEMINIA_WF_RX_HG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	11249;"	d
+SET_RG_GEMINIA_WF_RX_HG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	11244;"	d
+SET_RG_GEMINIA_WF_RX_HG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	11245;"	d
+SET_RG_GEMINIA_WF_RX_HG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	11246;"	d
+SET_RG_GEMINIA_WF_RX_HG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	11242;"	d
+SET_RG_GEMINIA_WF_RX_HG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	11250;"	d
+SET_RG_GEMINIA_WF_RX_HG_SQDC	smac/hal/ssv6006c/ssv6006C_reg.h	11248;"	d
+SET_RG_GEMINIA_WF_RX_HG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	11251;"	d
+SET_RG_GEMINIA_WF_RX_HG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	11247;"	d
+SET_RG_GEMINIA_WF_RX_HG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	11243;"	d
+SET_RG_GEMINIA_WF_RX_HG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	11252;"	d
+SET_RG_GEMINIA_WF_RX_LG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	11271;"	d
+SET_RG_GEMINIA_WF_RX_LG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	11266;"	d
+SET_RG_GEMINIA_WF_RX_LG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	11267;"	d
+SET_RG_GEMINIA_WF_RX_LG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	11268;"	d
+SET_RG_GEMINIA_WF_RX_LG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	11264;"	d
+SET_RG_GEMINIA_WF_RX_LG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	11272;"	d
+SET_RG_GEMINIA_WF_RX_LG_SQDC	smac/hal/ssv6006c/ssv6006C_reg.h	11270;"	d
+SET_RG_GEMINIA_WF_RX_LG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	11273;"	d
+SET_RG_GEMINIA_WF_RX_LG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	11269;"	d
+SET_RG_GEMINIA_WF_RX_LG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	11265;"	d
+SET_RG_GEMINIA_WF_RX_LG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	11274;"	d
+SET_RG_GEMINIA_WF_RX_MG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	11260;"	d
+SET_RG_GEMINIA_WF_RX_MG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	11255;"	d
+SET_RG_GEMINIA_WF_RX_MG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	11256;"	d
+SET_RG_GEMINIA_WF_RX_MG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	11257;"	d
+SET_RG_GEMINIA_WF_RX_MG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	11253;"	d
+SET_RG_GEMINIA_WF_RX_MG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	11261;"	d
+SET_RG_GEMINIA_WF_RX_MG_SQDC	smac/hal/ssv6006c/ssv6006C_reg.h	11259;"	d
+SET_RG_GEMINIA_WF_RX_MG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	11262;"	d
+SET_RG_GEMINIA_WF_RX_MG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	11258;"	d
+SET_RG_GEMINIA_WF_RX_MG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	11254;"	d
+SET_RG_GEMINIA_WF_RX_MG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	11263;"	d
+SET_RG_GEMINIA_WF_RX_OUTVCM	smac/hal/ssv6006c/ssv6006C_reg.h	11187;"	d
+SET_RG_GEMINIA_WF_RX_ULG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	11282;"	d
+SET_RG_GEMINIA_WF_RX_ULG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	11277;"	d
+SET_RG_GEMINIA_WF_RX_ULG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	11278;"	d
+SET_RG_GEMINIA_WF_RX_ULG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	11279;"	d
+SET_RG_GEMINIA_WF_RX_ULG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	11275;"	d
+SET_RG_GEMINIA_WF_RX_ULG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	11283;"	d
+SET_RG_GEMINIA_WF_RX_ULG_SQDC	smac/hal/ssv6006c/ssv6006C_reg.h	11281;"	d
+SET_RG_GEMINIA_WF_RX_ULG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	11284;"	d
+SET_RG_GEMINIA_WF_RX_ULG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	11280;"	d
+SET_RG_GEMINIA_WF_RX_ULG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	11276;"	d
+SET_RG_GEMINIA_WF_RX_ULG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	11285;"	d
+SET_RG_GEMINIA_WF_TXLPF_BOOSTI	smac/hal/ssv6006c/ssv6006C_reg.h	11352;"	d
+SET_RG_GEMINIA_WF_TXPGA_CAPSW	smac/hal/ssv6006c/ssv6006C_reg.h	11215;"	d
+SET_RG_GEMINIA_WF_TX_DACI1ST	smac/hal/ssv6006c/ssv6006C_reg.h	11346;"	d
+SET_RG_GEMINIA_WF_TX_DACLPF_ICOARSE	smac/hal/ssv6006c/ssv6006C_reg.h	11347;"	d
+SET_RG_GEMINIA_WF_TX_DACLPF_IFINE	smac/hal/ssv6006c/ssv6006C_reg.h	11348;"	d
+SET_RG_GEMINIA_WF_TX_DACLPF_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	11349;"	d
+SET_RG_GEMINIA_WF_TX_DAC_CKEDGE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	11354;"	d
+SET_RG_GEMINIA_WF_TX_DAC_IATTN	smac/hal/ssv6006c/ssv6006C_reg.h	11351;"	d
+SET_RG_GEMINIA_WF_TX_DAC_IBIAS	smac/hal/ssv6006c/ssv6006C_reg.h	11350;"	d
+SET_RG_GEMINIA_WF_TX_DAC_IOFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	11356;"	d
+SET_RG_GEMINIA_WF_TX_DAC_OS	smac/hal/ssv6006c/ssv6006C_reg.h	11355;"	d
+SET_RG_GEMINIA_WF_TX_DAC_QOFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	11357;"	d
+SET_RG_GEMINIA_WF_TX_DAC_RCAL	smac/hal/ssv6006c/ssv6006C_reg.h	11353;"	d
+SET_RG_GEMINIA_WF_TX_DIV_VSET	smac/hal/ssv6006c/ssv6006C_reg.h	11216;"	d
+SET_RG_GEMINIA_WF_TX_GAIN_OFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	11236;"	d
+SET_RG_GEMINIA_WF_TX_LOBUF_VSET	smac/hal/ssv6006c/ssv6006C_reg.h	11217;"	d
+SET_RG_GEMINIA_WF_TX_PA1_VCAS	smac/hal/ssv6006c/ssv6006C_reg.h	11225;"	d
+SET_RG_GEMINIA_WF_TX_PA2_VCAS	smac/hal/ssv6006c/ssv6006C_reg.h	11226;"	d
+SET_RG_GEMINIA_WF_TX_PA3_VCAS	smac/hal/ssv6006c/ssv6006C_reg.h	11227;"	d
+SET_RG_GEMINIA_WF_TX_VDDSW	smac/hal/ssv6006c/ssv6006C_reg.h	11218;"	d
+SET_RG_GEMINIA_XO_CBANKI	smac/hal/ssv6006c/ssv6006C_reg.h	11804;"	d
+SET_RG_GEMINIA_XO_CBANKO	smac/hal/ssv6006c/ssv6006C_reg.h	11805;"	d
+SET_RG_GEMINIA_XO_LDO_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	11803;"	d
+SET_RG_GEMINIA_XO_TIMMER	smac/hal/ssv6006c/ssv6006C_reg.h	11817;"	d
+SET_RG_GP_DIV_EN	include/ssv6200_reg.h	8018;"	d
+SET_RG_HB_COEF0	include/ssv6200_reg.h	7713;"	d
+SET_RG_HB_COEF1	include/ssv6200_reg.h	7714;"	d
+SET_RG_HB_COEF2	include/ssv6200_reg.h	7715;"	d
+SET_RG_HB_COEF3	include/ssv6200_reg.h	7716;"	d
+SET_RG_HB_COEF4	include/ssv6200_reg.h	7717;"	d
+SET_RG_HG_PGA_SAT1_PGA_GAIN	include/ssv6200_reg.h	7581;"	d
+SET_RG_HG_PGA_SAT1_PGA_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	15164;"	d
+SET_RG_HG_PGA_SAT2_PGA_GAIN	include/ssv6200_reg.h	7580;"	d
+SET_RG_HG_PGA_SAT2_PGA_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	15163;"	d
+SET_RG_HG_RF_SAT_PGA_GAIN	include/ssv6200_reg.h	7582;"	d
+SET_RG_HG_RF_SAT_PGA_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	15165;"	d
+SET_RG_HPF1_FAST_SET_X	include/ssv6200_reg.h	8243;"	d
+SET_RG_HPF1_FAST_SET_Y	include/ssv6200_reg.h	8244;"	d
+SET_RG_HPF1_FAST_SET_Z	include/ssv6200_reg.h	8245;"	d
+SET_RG_HPF_T1A	include/ssv6200_reg.h	8246;"	d
+SET_RG_HPF_T1B	include/ssv6200_reg.h	8247;"	d
+SET_RG_HPF_T1C	include/ssv6200_reg.h	8248;"	d
+SET_RG_HS3W_COMM_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	14587;"	d
+SET_RG_HS3W_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	14586;"	d
+SET_RG_HS3W_PGAGC	smac/hal/ssv6006c/ssv6006C_reg.h	14582;"	d
+SET_RG_HS3W_RFGC	smac/hal/ssv6006c/ssv6006C_reg.h	14583;"	d
+SET_RG_HS3W_RF_PHY_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	14585;"	d
+SET_RG_HS3W_RXAGC	smac/hal/ssv6006c/ssv6006C_reg.h	14584;"	d
+SET_RG_HS3W_START_SENT	smac/hal/ssv6006c/ssv6006C_reg.h	14588;"	d
+SET_RG_HS3W_SX_CHANNEL_INT	smac/hal/ssv6006c/ssv6006C_reg.h	14591;"	d
+SET_RG_HS3W_SX_RFCH_MAP_EN_INT	smac/hal/ssv6006c/ssv6006C_reg.h	14590;"	d
+SET_RG_HS3W_SX_RFCTRL_CH_INT_10_8	smac/hal/ssv6006c/ssv6006C_reg.h	14589;"	d
+SET_RG_HS3W_SX_RFCTRL_CH_INT_7_0	smac/hal/ssv6006c/ssv6006C_reg.h	14593;"	d
+SET_RG_HS3W_SX_RFCTRL_F_INT	smac/hal/ssv6006c/ssv6006C_reg.h	14592;"	d
+SET_RG_HS3W_TX_RF_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	14581;"	d
+SET_RG_HS5W_M_CAL_INDEX	smac/hal/ssv6006c/ssv6006C_reg.h	14930;"	d
+SET_RG_HS5W_M_CMD0_EN	smac/hal/ssv6006c/ssv6006C_reg.h	14928;"	d
+SET_RG_HS5W_M_CMD1_EN	smac/hal/ssv6006c/ssv6006C_reg.h	14927;"	d
+SET_RG_HS5W_M_CMD2_EN	smac/hal/ssv6006c/ssv6006C_reg.h	14926;"	d
+SET_RG_HS5W_M_CMD3_EN	smac/hal/ssv6006c/ssv6006C_reg.h	14925;"	d
+SET_RG_HS5W_M_CMD4_EN	smac/hal/ssv6006c/ssv6006C_reg.h	14924;"	d
+SET_RG_HS5W_M_CMD5_EN	smac/hal/ssv6006c/ssv6006C_reg.h	14923;"	d
+SET_RG_HS5W_M_CMD6_EN	smac/hal/ssv6006c/ssv6006C_reg.h	14922;"	d
+SET_RG_HS5W_M_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	14921;"	d
+SET_RG_HS5W_M_MD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	14920;"	d
+SET_RG_HS5W_M_PGAGC	smac/hal/ssv6006c/ssv6006C_reg.h	14931;"	d
+SET_RG_HS5W_M_PHY_BW	smac/hal/ssv6006c/ssv6006C_reg.h	14942;"	d
+SET_RG_HS5W_M_RFGC	smac/hal/ssv6006c/ssv6006C_reg.h	14932;"	d
+SET_RG_HS5W_M_RF_PHY_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	14929;"	d
+SET_RG_HS5W_M_SX5GB_CHANNEL	smac/hal/ssv6006c/ssv6006C_reg.h	14941;"	d
+SET_RG_HS5W_M_SX5GB_RFCH_MAP_EN	smac/hal/ssv6006c/ssv6006C_reg.h	14939;"	d
+SET_RG_HS5W_M_SX5GB_RFCTRL_CH	smac/hal/ssv6006c/ssv6006C_reg.h	14935;"	d
+SET_RG_HS5W_M_SX5GB_RFCTRL_F	smac/hal/ssv6006c/ssv6006C_reg.h	14938;"	d
+SET_RG_HS5W_M_SX_CHANNEL	smac/hal/ssv6006c/ssv6006C_reg.h	14940;"	d
+SET_RG_HS5W_M_SX_RFCH_MAP_EN	smac/hal/ssv6006c/ssv6006C_reg.h	14937;"	d
+SET_RG_HS5W_M_SX_RFCTRL_CH	smac/hal/ssv6006c/ssv6006C_reg.h	14934;"	d
+SET_RG_HS5W_M_SX_RFCTRL_F	smac/hal/ssv6006c/ssv6006C_reg.h	14936;"	d
+SET_RG_HS5W_M_TXPWRLVL	smac/hal/ssv6006c/ssv6006C_reg.h	14933;"	d
+SET_RG_HSDIV_INBFSEL	smac/hal/ssv6006c/ssv6006C_reg.h	14260;"	d
+SET_RG_HSDIV_OBFMX_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	14261;"	d
+SET_RG_HSDIV_OBFSX_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	14262;"	d
+SET_RG_HSDIV_VRSEL	smac/hal/ssv6006c/ssv6006C_reg.h	14263;"	d
+SET_RG_HS_3WIRE_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	13363;"	d
+SET_RG_HT20_RX_FFT_SCALE	smac/hal/ssv6006c/ssv6006C_reg.h	15464;"	d
+SET_RG_HT20_SYM_BOUND_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15456;"	d
+SET_RG_HT20_TR_LPF_KI	smac/hal/ssv6006c/ssv6006C_reg.h	15452;"	d
+SET_RG_HT20_TR_LPF_KP	smac/hal/ssv6006c/ssv6006C_reg.h	15453;"	d
+SET_RG_HT40_RX_FFT_SCALE	smac/hal/ssv6006c/ssv6006C_reg.h	15486;"	d
+SET_RG_HT40_SYM_BOUND_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15451;"	d
+SET_RG_HT40_TR_LPF_KI	smac/hal/ssv6006c/ssv6006C_reg.h	15449;"	d
+SET_RG_HT40_TR_LPF_KP	smac/hal/ssv6006c/ssv6006C_reg.h	15450;"	d
+SET_RG_HTCARR52_FFT_SCALE	include/ssv6200_reg.h	7841;"	d
+SET_RG_HTCARR56_FFT_SCALE	include/ssv6200_reg.h	7842;"	d
+SET_RG_HT_LTF_SEL_EQ	include/ssv6200_reg.h	7969;"	d
+SET_RG_HT_LTF_SEL_PILOT	include/ssv6200_reg.h	7970;"	d
+SET_RG_HW_PINSEL	smac/hal/ssv6006c/ssv6006C_reg.h	13362;"	d
+SET_RG_HW_WAKE_XOSC	smac/hal/ssv6006c/ssv6006C_reg.h	14955;"	d
+SET_RG_HW_WAKE_XOSC_SLP	smac/hal/ssv6006c/ssv6006C_reg.h	15069;"	d
+SET_RG_IDACAI_PGAG0	include/ssv6200_reg.h	8396;"	d
+SET_RG_IDACAI_PGAG1	include/ssv6200_reg.h	8394;"	d
+SET_RG_IDACAI_PGAG10	include/ssv6200_reg.h	8376;"	d
+SET_RG_IDACAI_PGAG11	include/ssv6200_reg.h	8374;"	d
+SET_RG_IDACAI_PGAG12	include/ssv6200_reg.h	8372;"	d
+SET_RG_IDACAI_PGAG13	include/ssv6200_reg.h	8370;"	d
+SET_RG_IDACAI_PGAG14	include/ssv6200_reg.h	8367;"	d
+SET_RG_IDACAI_PGAG15	include/ssv6200_reg.h	8365;"	d
+SET_RG_IDACAI_PGAG2	include/ssv6200_reg.h	8392;"	d
+SET_RG_IDACAI_PGAG3	include/ssv6200_reg.h	8390;"	d
+SET_RG_IDACAI_PGAG4	include/ssv6200_reg.h	8388;"	d
+SET_RG_IDACAI_PGAG5	include/ssv6200_reg.h	8386;"	d
+SET_RG_IDACAI_PGAG6	include/ssv6200_reg.h	8384;"	d
+SET_RG_IDACAI_PGAG7	include/ssv6200_reg.h	8382;"	d
+SET_RG_IDACAI_PGAG8	include/ssv6200_reg.h	8380;"	d
+SET_RG_IDACAI_PGAG9	include/ssv6200_reg.h	8378;"	d
+SET_RG_IDACAI_TZ0_COARSE0	smac/hal/ssv6006c/ssv6006C_reg.h	13893;"	d
+SET_RG_IDACAI_TZ0_COARSE1	smac/hal/ssv6006c/ssv6006C_reg.h	13891;"	d
+SET_RG_IDACAI_TZ0_COARSE2	smac/hal/ssv6006c/ssv6006C_reg.h	13889;"	d
+SET_RG_IDACAI_TZ0_COARSE3	smac/hal/ssv6006c/ssv6006C_reg.h	13887;"	d
+SET_RG_IDACAI_TZ0_COARSE4	smac/hal/ssv6006c/ssv6006C_reg.h	13885;"	d
+SET_RG_IDACAI_TZ1_COARSE0	smac/hal/ssv6006c/ssv6006C_reg.h	13903;"	d
+SET_RG_IDACAI_TZ1_COARSE1	smac/hal/ssv6006c/ssv6006C_reg.h	13901;"	d
+SET_RG_IDACAI_TZ1_COARSE2	smac/hal/ssv6006c/ssv6006C_reg.h	13899;"	d
+SET_RG_IDACAI_TZ1_COARSE3	smac/hal/ssv6006c/ssv6006C_reg.h	13897;"	d
+SET_RG_IDACAI_TZ1_COARSE4	smac/hal/ssv6006c/ssv6006C_reg.h	13895;"	d
+SET_RG_IDACAQ_PGAG0	include/ssv6200_reg.h	8397;"	d
+SET_RG_IDACAQ_PGAG1	include/ssv6200_reg.h	8395;"	d
+SET_RG_IDACAQ_PGAG10	include/ssv6200_reg.h	8377;"	d
+SET_RG_IDACAQ_PGAG11	include/ssv6200_reg.h	8375;"	d
+SET_RG_IDACAQ_PGAG12	include/ssv6200_reg.h	8373;"	d
+SET_RG_IDACAQ_PGAG13	include/ssv6200_reg.h	8371;"	d
+SET_RG_IDACAQ_PGAG14	include/ssv6200_reg.h	8368;"	d
+SET_RG_IDACAQ_PGAG15	include/ssv6200_reg.h	8366;"	d
+SET_RG_IDACAQ_PGAG2	include/ssv6200_reg.h	8393;"	d
+SET_RG_IDACAQ_PGAG3	include/ssv6200_reg.h	8391;"	d
+SET_RG_IDACAQ_PGAG4	include/ssv6200_reg.h	8389;"	d
+SET_RG_IDACAQ_PGAG5	include/ssv6200_reg.h	8387;"	d
+SET_RG_IDACAQ_PGAG6	include/ssv6200_reg.h	8385;"	d
+SET_RG_IDACAQ_PGAG7	include/ssv6200_reg.h	8383;"	d
+SET_RG_IDACAQ_PGAG8	include/ssv6200_reg.h	8381;"	d
+SET_RG_IDACAQ_PGAG9	include/ssv6200_reg.h	8379;"	d
+SET_RG_IDACAQ_TZ0_COARSE0	smac/hal/ssv6006c/ssv6006C_reg.h	13894;"	d
+SET_RG_IDACAQ_TZ0_COARSE1	smac/hal/ssv6006c/ssv6006C_reg.h	13892;"	d
+SET_RG_IDACAQ_TZ0_COARSE2	smac/hal/ssv6006c/ssv6006C_reg.h	13890;"	d
+SET_RG_IDACAQ_TZ0_COARSE3	smac/hal/ssv6006c/ssv6006C_reg.h	13888;"	d
+SET_RG_IDACAQ_TZ0_COARSE4	smac/hal/ssv6006c/ssv6006C_reg.h	13886;"	d
+SET_RG_IDACAQ_TZ1_COARSE0	smac/hal/ssv6006c/ssv6006C_reg.h	13904;"	d
+SET_RG_IDACAQ_TZ1_COARSE1	smac/hal/ssv6006c/ssv6006C_reg.h	13902;"	d
+SET_RG_IDACAQ_TZ1_COARSE2	smac/hal/ssv6006c/ssv6006C_reg.h	13900;"	d
+SET_RG_IDACAQ_TZ1_COARSE3	smac/hal/ssv6006c/ssv6006C_reg.h	13898;"	d
+SET_RG_IDACAQ_TZ1_COARSE4	smac/hal/ssv6006c/ssv6006C_reg.h	13896;"	d
+SET_RG_IFS_TIME	include/ssv6200_reg.h	7547;"	d
+SET_RG_IFS_TIME	smac/hal/ssv6006c/ssv6006C_reg.h	15131;"	d
+SET_RG_IFS_TIME_EXT	smac/hal/ssv6006c/ssv6006C_reg.h	15135;"	d
+SET_RG_INI_PHASE	include/ssv6200_reg.h	7968;"	d
+SET_RG_INI_PHASE	smac/hal/ssv6006c/ssv6006C_reg.h	15593;"	d
+SET_RG_INTG_MU	include/ssv6200_reg.h	8009;"	d
+SET_RG_INTG_PH	include/ssv6200_reg.h	8007;"	d
+SET_RG_INTG_PRD	include/ssv6200_reg.h	8008;"	d
+SET_RG_INTRUP_RX_11B_CLEAR	smac/hal/ssv6006c/ssv6006C_reg.h	15400;"	d
+SET_RG_INTRUP_RX_11B_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	15401;"	d
+SET_RG_INTRUP_RX_11B_TRIG	smac/hal/ssv6006c/ssv6006C_reg.h	15402;"	d
+SET_RG_INTRUP_RX_11GN_CLEAR	smac/hal/ssv6006c/ssv6006C_reg.h	15566;"	d
+SET_RG_INTRUP_RX_11GN_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	15567;"	d
+SET_RG_INTRUP_RX_11GN_TRIG	smac/hal/ssv6006c/ssv6006C_reg.h	15568;"	d
+SET_RG_INT_PMU_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	15003;"	d
+SET_RG_IOT_ADC_CLKSEL	smac/hal/ssv6006c/ssv6006C_reg.h	13999;"	d
+SET_RG_IOT_ADC_CLK_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	14006;"	d
+SET_RG_IOT_ADC_CLK_SH_DUTY	smac/hal/ssv6006c/ssv6006C_reg.h	14007;"	d
+SET_RG_IOT_ADC_CLOAD	smac/hal/ssv6006c/ssv6006C_reg.h	14005;"	d
+SET_RG_IOT_ADC_DNLEN	smac/hal/ssv6006c/ssv6006C_reg.h	14000;"	d
+SET_RG_IOT_ADC_EDGE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	14614;"	d
+SET_RG_IOT_ADC_ICMP	smac/hal/ssv6006c/ssv6006C_reg.h	14003;"	d
+SET_RG_IOT_ADC_METAEN	smac/hal/ssv6006c/ssv6006C_reg.h	14001;"	d
+SET_RG_IOT_ADC_SIGN_SWAP	smac/hal/ssv6006c/ssv6006C_reg.h	14613;"	d
+SET_RG_IOT_ADC_TFLAG	smac/hal/ssv6006c/ssv6006C_reg.h	14002;"	d
+SET_RG_IOT_ADC_VCMI	smac/hal/ssv6006c/ssv6006C_reg.h	14004;"	d
+SET_RG_IOT_ADC_VSEN_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	14008;"	d
+SET_RG_IQCAL_ALPHA_ESTM_EN	include/ssv6200_reg.h	8014;"	d
+SET_RG_IQCAL_BP_ACI	include/ssv6200_reg.h	8050;"	d
+SET_RG_IQCAL_DC_EN	include/ssv6200_reg.h	8015;"	d
+SET_RG_IQCAL_IQCOL_EN	include/ssv6200_reg.h	8013;"	d
+SET_RG_IQCAL_MULT_OP0	include/ssv6200_reg.h	8020;"	d
+SET_RG_IQCAL_MULT_OP1	include/ssv6200_reg.h	8021;"	d
+SET_RG_IQCAL_SPRM_EN	include/ssv6200_reg.h	8011;"	d
+SET_RG_IQCAL_SPRM_FREQ	include/ssv6200_reg.h	8012;"	d
+SET_RG_IQCAL_SPRM_SELQ	include/ssv6200_reg.h	8010;"	d
+SET_RG_IQC_FFT_EN	include/ssv6200_reg.h	7664;"	d
+SET_RG_IQ_DC_BYP	include/ssv6200_reg.h	7557;"	d
+SET_RG_IQ_DC_LEAKY_FACTOR	include/ssv6200_reg.h	7558;"	d
+SET_RG_IQ_SWAP	include/ssv6200_reg.h	7503;"	d
+SET_RG_IQ_SWAP	smac/hal/ssv6006c/ssv6006C_reg.h	14494;"	d
+SET_RG_IQ_SWAP_BB	smac/hal/ssv6006c/ssv6006C_reg.h	15090;"	d
+SET_RG_I_INV	include/ssv6200_reg.h	7505;"	d
+SET_RG_I_INV	smac/hal/ssv6006c/ssv6006C_reg.h	14493;"	d
+SET_RG_I_INV_BB	smac/hal/ssv6006c/ssv6006C_reg.h	15092;"	d
+SET_RG_LBK_ANA_PATH	include/ssv6200_reg.h	7507;"	d
+SET_RG_LBK_ANA_PATH	smac/hal/ssv6006c/ssv6006C_reg.h	15094;"	d
+SET_RG_LBK_DIG_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	15095;"	d
+SET_RG_LDO_5G_CP_FC	smac/hal/ssv6006c/ssv6006C_reg.h	14217;"	d
+SET_RG_LDO_5G_CP_FC_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	14216;"	d
+SET_RG_LDO_5G_DIV_FC	smac/hal/ssv6006c/ssv6006C_reg.h	14219;"	d
+SET_RG_LDO_5G_DIV_FC_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	14218;"	d
+SET_RG_LDO_5G_LO_FC	smac/hal/ssv6006c/ssv6006C_reg.h	14221;"	d
+SET_RG_LDO_5G_LO_FC_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	14220;"	d
+SET_RG_LDO_5G_VCO_FC	smac/hal/ssv6006c/ssv6006C_reg.h	14223;"	d
+SET_RG_LDO_5G_VCO_FC_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	14222;"	d
+SET_RG_LDO_5G_VCO_RCF	smac/hal/ssv6006c/ssv6006C_reg.h	14224;"	d
+SET_RG_LDO_CP_FC	smac/hal/ssv6006c/ssv6006C_reg.h	13708;"	d
+SET_RG_LDO_CP_FC_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	13707;"	d
+SET_RG_LDO_DIV_FC	smac/hal/ssv6006c/ssv6006C_reg.h	13710;"	d
+SET_RG_LDO_DIV_FC_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	13709;"	d
+SET_RG_LDO_LEVEL_ABB	include/ssv6200_reg.h	8161;"	d
+SET_RG_LDO_LEVEL_AFE	include/ssv6200_reg.h	8162;"	d
+SET_RG_LDO_LEVEL_AFE	smac/hal/ssv6006c/ssv6006C_reg.h	13439;"	d
+SET_RG_LDO_LEVEL_EFUSE	smac/hal/ssv6006c/ssv6006C_reg.h	14978;"	d
+SET_RG_LDO_LEVEL_RX_FE	include/ssv6200_reg.h	8160;"	d
+SET_RG_LDO_LEVEL_RX_FE	smac/hal/ssv6006c/ssv6006C_reg.h	13437;"	d
+SET_RG_LDO_LO_FC	smac/hal/ssv6006c/ssv6006C_reg.h	13712;"	d
+SET_RG_LDO_LO_FC_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	13711;"	d
+SET_RG_LDO_VCO_FC	smac/hal/ssv6006c/ssv6006C_reg.h	13714;"	d
+SET_RG_LDO_VCO_FC_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	13713;"	d
+SET_RG_LDO_VCO_RCF	smac/hal/ssv6006c/ssv6006C_reg.h	13715;"	d
+SET_RG_LENGTH	include/ssv6200_reg.h	7530;"	d
+SET_RG_LENGTH	smac/hal/ssv6006c/ssv6006C_reg.h	15113;"	d
+SET_RG_LG_PGA_SAT_PGA_GAIN	include/ssv6200_reg.h	7577;"	d
+SET_RG_LG_PGA_SAT_PGA_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	15160;"	d
+SET_RG_LG_PGA_UND_PGA_GAIN	include/ssv6200_reg.h	7576;"	d
+SET_RG_LG_PGA_UND_PGA_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	15159;"	d
+SET_RG_LG_RF_SAT_PGA_GAIN	include/ssv6200_reg.h	7578;"	d
+SET_RG_LG_RF_SAT_PGA_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	15161;"	d
+SET_RG_LOAD_RFTABLE_RDY	smac/hal/ssv6006c/ssv6006C_reg.h	14970;"	d
+SET_RG_LO_UP_CH	smac/hal/ssv6006c/ssv6006C_reg.h	14482;"	d
+SET_RG_LPBK_RX_EN	include/ssv6200_reg.h	6659;"	d
+SET_RG_LPBK_RX_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10755;"	d
+SET_RG_LPF4_00	include/ssv6200_reg.h	7719;"	d
+SET_RG_LPF4_01	include/ssv6200_reg.h	7720;"	d
+SET_RG_LPF4_02	include/ssv6200_reg.h	7721;"	d
+SET_RG_LPF4_03	include/ssv6200_reg.h	7722;"	d
+SET_RG_LPF4_04	include/ssv6200_reg.h	7723;"	d
+SET_RG_LPF4_05	include/ssv6200_reg.h	7724;"	d
+SET_RG_LPF4_06	include/ssv6200_reg.h	7725;"	d
+SET_RG_LPF4_07	include/ssv6200_reg.h	7726;"	d
+SET_RG_LPF4_08	include/ssv6200_reg.h	7727;"	d
+SET_RG_LPF4_09	include/ssv6200_reg.h	7728;"	d
+SET_RG_LPF4_10	include/ssv6200_reg.h	7729;"	d
+SET_RG_LPF4_11	include/ssv6200_reg.h	7730;"	d
+SET_RG_LPF4_12	include/ssv6200_reg.h	7731;"	d
+SET_RG_LPF4_13	include/ssv6200_reg.h	7732;"	d
+SET_RG_LPF4_14	include/ssv6200_reg.h	7733;"	d
+SET_RG_LPF4_15	include/ssv6200_reg.h	7734;"	d
+SET_RG_LPF4_16	include/ssv6200_reg.h	7735;"	d
+SET_RG_LPF4_17	include/ssv6200_reg.h	7736;"	d
+SET_RG_LPF4_18	include/ssv6200_reg.h	7737;"	d
+SET_RG_LPF4_19	include/ssv6200_reg.h	7738;"	d
+SET_RG_LPF4_20	include/ssv6200_reg.h	7739;"	d
+SET_RG_LPF4_21	include/ssv6200_reg.h	7740;"	d
+SET_RG_LPF4_22	include/ssv6200_reg.h	7741;"	d
+SET_RG_LPF4_23	include/ssv6200_reg.h	7742;"	d
+SET_RG_LPF4_24	include/ssv6200_reg.h	7743;"	d
+SET_RG_LPF4_25	include/ssv6200_reg.h	7744;"	d
+SET_RG_LPF4_26	include/ssv6200_reg.h	7745;"	d
+SET_RG_LPF4_27	include/ssv6200_reg.h	7746;"	d
+SET_RG_LPF4_28	include/ssv6200_reg.h	7747;"	d
+SET_RG_LPF4_29	include/ssv6200_reg.h	7748;"	d
+SET_RG_LPF4_30	include/ssv6200_reg.h	7749;"	d
+SET_RG_LPF4_31	include/ssv6200_reg.h	7750;"	d
+SET_RG_LPF4_32	include/ssv6200_reg.h	7751;"	d
+SET_RG_LPF4_33	include/ssv6200_reg.h	7752;"	d
+SET_RG_LPF4_34	include/ssv6200_reg.h	7753;"	d
+SET_RG_LPF4_35	include/ssv6200_reg.h	7754;"	d
+SET_RG_LPF4_36	include/ssv6200_reg.h	7755;"	d
+SET_RG_LPF4_37	include/ssv6200_reg.h	7756;"	d
+SET_RG_LPF4_38	include/ssv6200_reg.h	7757;"	d
+SET_RG_LPF4_39	include/ssv6200_reg.h	7758;"	d
+SET_RG_LPF4_40	include/ssv6200_reg.h	7759;"	d
+SET_RG_L_LENGTH	include/ssv6200_reg.h	7536;"	d
+SET_RG_L_LENGTH	smac/hal/ssv6006c/ssv6006C_reg.h	15119;"	d
+SET_RG_L_LENGTH_MAX	include/ssv6200_reg.h	7919;"	d
+SET_RG_L_LENGTH_MAX	smac/hal/ssv6006c/ssv6006C_reg.h	15561;"	d
+SET_RG_L_RATE	include/ssv6200_reg.h	7537;"	d
+SET_RG_L_RATE	smac/hal/ssv6006c/ssv6006C_reg.h	15120;"	d
+SET_RG_MAC_DES_SPACE	include/ssv6200_reg.h	7921;"	d
+SET_RG_MAC_LPBK	include/ssv6200_reg.h	6656;"	d
+SET_RG_MAC_LPBK	smac/hal/ssv6006c/ssv6006C_reg.h	10752;"	d
+SET_RG_MAC_M2M	include/ssv6200_reg.h	6657;"	d
+SET_RG_MAC_M2M	smac/hal/ssv6006c/ssv6006C_reg.h	10753;"	d
+SET_RG_MAC_PKT_ADDR1_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	15265;"	d
+SET_RG_MAC_PKT_ADDR1_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	15266;"	d
+SET_RG_MAC_PKT_ADDR2_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	15267;"	d
+SET_RG_MAC_PKT_ADDR2_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	15268;"	d
+SET_RG_MAC_PKT_ADDR2_ON	smac/hal/ssv6006c/ssv6006C_reg.h	15260;"	d
+SET_RG_MAC_PKT_ADDR3_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	15269;"	d
+SET_RG_MAC_PKT_ADDR3_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	15270;"	d
+SET_RG_MAC_PKT_ADDR3_ON	smac/hal/ssv6006c/ssv6006C_reg.h	15259;"	d
+SET_RG_MAC_PKT_ADDR4_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	15272;"	d
+SET_RG_MAC_PKT_ADDR4_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	15273;"	d
+SET_RG_MAC_PKT_ADDR4_ON	smac/hal/ssv6006c/ssv6006C_reg.h	15257;"	d
+SET_RG_MAC_PKT_AGGREGATE	smac/hal/ssv6006c/ssv6006C_reg.h	15256;"	d
+SET_RG_MAC_PKT_AGGREGATE_NUM	smac/hal/ssv6006c/ssv6006C_reg.h	15261;"	d
+SET_RG_MAC_PKT_DUR	smac/hal/ssv6006c/ssv6006C_reg.h	15263;"	d
+SET_RG_MAC_PKT_FC	smac/hal/ssv6006c/ssv6006C_reg.h	15264;"	d
+SET_RG_MAC_PKT_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	15255;"	d
+SET_RG_MAC_PKT_PLD_LENGTH	smac/hal/ssv6006c/ssv6006C_reg.h	15262;"	d
+SET_RG_MAC_PKT_SEQ	smac/hal/ssv6006c/ssv6006C_reg.h	15271;"	d
+SET_RG_MAC_PKT_SEQ_ON	smac/hal/ssv6006c/ssv6006C_reg.h	15258;"	d
+SET_RG_MA_DPTH	include/ssv6200_reg.h	8006;"	d
+SET_RG_MA_PGA_HIGH_TH_CNT_LMT	include/ssv6200_reg.h	7587;"	d
+SET_RG_MA_PGA_HIGH_TH_CNT_LMT	smac/hal/ssv6006c/ssv6006C_reg.h	15168;"	d
+SET_RG_MA_PGA_LOW_TH_CNT_LMT	include/ssv6200_reg.h	7584;"	d
+SET_RG_MA_PGA_LOW_TH_CNT_LMT	smac/hal/ssv6006c/ssv6006C_reg.h	15167;"	d
+SET_RG_MBRUN_16	include/ssv6200_reg.h	7697;"	d
+SET_RG_MBRUN_64	include/ssv6200_reg.h	7935;"	d
+SET_RG_MBRUN_80	include/ssv6200_reg.h	7928;"	d
+SET_RG_MG_PGA_JB_TH	include/ssv6200_reg.h	7583;"	d
+SET_RG_MG_PGA_JB_TH	smac/hal/ssv6006c/ssv6006C_reg.h	15166;"	d
+SET_RG_MG_RF_SAT_PGANOREF_PGA_GAIN	include/ssv6200_reg.h	7579;"	d
+SET_RG_MG_RF_SAT_PGANOREF_PGA_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	15162;"	d
+SET_RG_MODE	include/ssv6200_reg.h	8123;"	d
+SET_RG_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	13370;"	d
+SET_RG_MODE_BY_HS_3WIRE	smac/hal/ssv6006c/ssv6006C_reg.h	14594;"	d
+SET_RG_MODE_BY_HWPIN	smac/hal/ssv6006c/ssv6006C_reg.h	14596;"	d
+SET_RG_MODE_BY_PHY	smac/hal/ssv6006c/ssv6006C_reg.h	14595;"	d
+SET_RG_MODE_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	13364;"	d
+SET_RG_MODE_REG_IN_16	include/ssv6200_reg.h	7695;"	d
+SET_RG_MODE_REG_IN_64	include/ssv6200_reg.h	7933;"	d
+SET_RG_MODE_REG_IN_80	include/ssv6200_reg.h	7926;"	d
+SET_RG_MODE_REG_SI_16	include/ssv6200_reg.h	7699;"	d
+SET_RG_MODE_REG_SI_64	include/ssv6200_reg.h	7937;"	d
+SET_RG_MODE_REG_SI_80	include/ssv6200_reg.h	7930;"	d
+SET_RG_MRX_EN_CNT_RST_N	include/ssv6200_reg.h	7668;"	d
+SET_RG_MRX_EN_CNT_RST_N	smac/hal/ssv6006c/ssv6006C_reg.h	15214;"	d
+SET_RG_MRX_LEN_CNT_EN_0	include/ssv6200_reg.h	7687;"	d
+SET_RG_MRX_LEN_CNT_EN_1	include/ssv6200_reg.h	7690;"	d
+SET_RG_MRX_LEN_LOWER_TH_0	include/ssv6200_reg.h	7685;"	d
+SET_RG_MRX_LEN_LOWER_TH_0	smac/hal/ssv6006c/ssv6006C_reg.h	15233;"	d
+SET_RG_MRX_LEN_LOWER_TH_1	include/ssv6200_reg.h	7688;"	d
+SET_RG_MRX_LEN_LOWER_TH_1	smac/hal/ssv6006c/ssv6006C_reg.h	15235;"	d
+SET_RG_MRX_LEN_UPPER_TH_0	include/ssv6200_reg.h	7686;"	d
+SET_RG_MRX_LEN_UPPER_TH_0	smac/hal/ssv6006c/ssv6006C_reg.h	15234;"	d
+SET_RG_MRX_LEN_UPPER_TH_1	include/ssv6200_reg.h	7689;"	d
+SET_RG_MRX_LEN_UPPER_TH_1	smac/hal/ssv6006c/ssv6006C_reg.h	15236;"	d
+SET_RG_MRX_TYPE	smac/hal/ssv6006c/ssv6006C_reg.h	15241;"	d
+SET_RG_MRX_TYPE_0	include/ssv6200_reg.h	7706;"	d
+SET_RG_MRX_TYPE_1	include/ssv6200_reg.h	7705;"	d
+SET_RG_MRX_TYPE_CNT_LMT	smac/hal/ssv6006c/ssv6006C_reg.h	15242;"	d
+SET_RG_MTX_LEN_CNT_EN_0	include/ssv6200_reg.h	7681;"	d
+SET_RG_MTX_LEN_CNT_EN_1	include/ssv6200_reg.h	7684;"	d
+SET_RG_MTX_LEN_LOWER_TH_0	include/ssv6200_reg.h	7679;"	d
+SET_RG_MTX_LEN_LOWER_TH_0	smac/hal/ssv6006c/ssv6006C_reg.h	15229;"	d
+SET_RG_MTX_LEN_LOWER_TH_1	include/ssv6200_reg.h	7682;"	d
+SET_RG_MTX_LEN_LOWER_TH_1	smac/hal/ssv6006c/ssv6006C_reg.h	15231;"	d
+SET_RG_MTX_LEN_UPPER_TH_0	include/ssv6200_reg.h	7680;"	d
+SET_RG_MTX_LEN_UPPER_TH_0	smac/hal/ssv6006c/ssv6006C_reg.h	15230;"	d
+SET_RG_MTX_LEN_UPPER_TH_1	include/ssv6200_reg.h	7683;"	d
+SET_RG_MTX_LEN_UPPER_TH_1	smac/hal/ssv6006c/ssv6006C_reg.h	15232;"	d
+SET_RG_MTX_TYPE	smac/hal/ssv6006c/ssv6006C_reg.h	15243;"	d
+SET_RG_MTX_TYPE_0	include/ssv6200_reg.h	7708;"	d
+SET_RG_MTX_TYPE_1	include/ssv6200_reg.h	7707;"	d
+SET_RG_MTX_TYPE_CNT_LMT	smac/hal/ssv6006c/ssv6006C_reg.h	15244;"	d
+SET_RG_NEW_PILOT_AVG	smac/hal/ssv6006c/ssv6006C_reg.h	15558;"	d
+SET_RG_NEW_SB	smac/hal/ssv6006c/ssv6006C_reg.h	15559;"	d
+SET_RG_NFRAC_DELTA	smac/hal/ssv6006c/ssv6006C_reg.h	14480;"	d
+SET_RG_NORMSQUARE_LOW_SNR_4	include/ssv6200_reg.h	7877;"	d
+SET_RG_NORMSQUARE_LOW_SNR_4	smac/hal/ssv6006c/ssv6006C_reg.h	15470;"	d
+SET_RG_NORMSQUARE_LOW_SNR_5	include/ssv6200_reg.h	7876;"	d
+SET_RG_NORMSQUARE_LOW_SNR_5	smac/hal/ssv6006c/ssv6006C_reg.h	15469;"	d
+SET_RG_NORMSQUARE_LOW_SNR_6	include/ssv6200_reg.h	7875;"	d
+SET_RG_NORMSQUARE_LOW_SNR_6	smac/hal/ssv6006c/ssv6006C_reg.h	15468;"	d
+SET_RG_NORMSQUARE_LOW_SNR_7	include/ssv6200_reg.h	7874;"	d
+SET_RG_NORMSQUARE_LOW_SNR_7	smac/hal/ssv6006c/ssv6006C_reg.h	15467;"	d
+SET_RG_NORMSQUARE_LOW_SNR_8	include/ssv6200_reg.h	7878;"	d
+SET_RG_NORMSQUARE_LOW_SNR_8	smac/hal/ssv6006c/ssv6006C_reg.h	15471;"	d
+SET_RG_NORMSQUARE_SNR_0	include/ssv6200_reg.h	7882;"	d
+SET_RG_NORMSQUARE_SNR_0	smac/hal/ssv6006c/ssv6006C_reg.h	15475;"	d
+SET_RG_NORMSQUARE_SNR_1	include/ssv6200_reg.h	7881;"	d
+SET_RG_NORMSQUARE_SNR_1	smac/hal/ssv6006c/ssv6006C_reg.h	15474;"	d
+SET_RG_NORMSQUARE_SNR_2	include/ssv6200_reg.h	7880;"	d
+SET_RG_NORMSQUARE_SNR_2	smac/hal/ssv6006c/ssv6006C_reg.h	15473;"	d
+SET_RG_NORMSQUARE_SNR_3	include/ssv6200_reg.h	7879;"	d
+SET_RG_NORMSQUARE_SNR_3	smac/hal/ssv6006c/ssv6006C_reg.h	15472;"	d
+SET_RG_NORMSQUARE_SNR_4	include/ssv6200_reg.h	7886;"	d
+SET_RG_NORMSQUARE_SNR_4	smac/hal/ssv6006c/ssv6006C_reg.h	15479;"	d
+SET_RG_NORMSQUARE_SNR_5	include/ssv6200_reg.h	7885;"	d
+SET_RG_NORMSQUARE_SNR_5	smac/hal/ssv6006c/ssv6006C_reg.h	15478;"	d
+SET_RG_NORMSQUARE_SNR_6	include/ssv6200_reg.h	7884;"	d
+SET_RG_NORMSQUARE_SNR_6	smac/hal/ssv6006c/ssv6006C_reg.h	15477;"	d
+SET_RG_NORMSQUARE_SNR_7	include/ssv6200_reg.h	7883;"	d
+SET_RG_NORMSQUARE_SNR_7	smac/hal/ssv6006c/ssv6006C_reg.h	15476;"	d
+SET_RG_NORMSQUARE_SNR_8	include/ssv6200_reg.h	7887;"	d
+SET_RG_NORMSQUARE_SNR_8	smac/hal/ssv6006c/ssv6006C_reg.h	15480;"	d
+SET_RG_NO_SOUND	include/ssv6200_reg.h	7540;"	d
+SET_RG_NO_SOUND	smac/hal/ssv6006c/ssv6006C_reg.h	15123;"	d
+SET_RG_N_ESS	include/ssv6200_reg.h	7544;"	d
+SET_RG_N_ESS	smac/hal/ssv6006c/ssv6006C_reg.h	15127;"	d
+SET_RG_PABIAS_CTRL	include/ssv6200_reg.h	8206;"	d
+SET_RG_PACASCODE_CTRL	include/ssv6200_reg.h	8218;"	d
+SET_RG_PACELL_EN	include/ssv6200_reg.h	8205;"	d
+SET_RG_PACKET_STAT_EN	include/ssv6200_reg.h	7843;"	d
+SET_RG_PACKET_STAT_EN_11B	include/ssv6200_reg.h	7834;"	d
+SET_RG_PACKET_STAT_EN_11B_RX	smac/hal/ssv6006c/ssv6006C_reg.h	15419;"	d
+SET_RG_PACKET_STAT_EN_11GN	include/ssv6200_reg.h	7963;"	d
+SET_RG_PACKET_STAT_EN_11GN_RX	smac/hal/ssv6006c/ssv6006C_reg.h	15588;"	d
+SET_RG_PARALLEL_DR_16	include/ssv6200_reg.h	7696;"	d
+SET_RG_PARALLEL_DR_64	include/ssv6200_reg.h	7934;"	d
+SET_RG_PARALLEL_DR_80	include/ssv6200_reg.h	7927;"	d
+SET_RG_PA_FALL_TIME	include/ssv6200_reg.h	7673;"	d
+SET_RG_PA_RISE_TIME	include/ssv6200_reg.h	7669;"	d
+SET_RG_PDM_EDGE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	14616;"	d
+SET_RG_PDM_HIGH_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	14619;"	d
+SET_RG_PDM_LOW_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	14618;"	d
+SET_RG_PEAK_IDX_CNT_SEL	include/ssv6200_reg.h	7775;"	d
+SET_RG_PEAK_IDX_CNT_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	15357;"	d
+SET_RG_PERIOD_MAX	smac/hal/ssv6006c/ssv6006C_reg.h	15606;"	d
+SET_RG_PERIOD_MIN	smac/hal/ssv6006c/ssv6006C_reg.h	15605;"	d
+SET_RG_PGAG	include/ssv6200_reg.h	8122;"	d
+SET_RG_PGAG	smac/hal/ssv6006c/ssv6006C_reg.h	13373;"	d
+SET_RG_PGAGC_OW	include/ssv6200_reg.h	7567;"	d
+SET_RG_PGAGC_OW	smac/hal/ssv6006c/ssv6006C_reg.h	15150;"	d
+SET_RG_PGAGC_SET	include/ssv6200_reg.h	7566;"	d
+SET_RG_PGAGC_SET	smac/hal/ssv6006c/ssv6006C_reg.h	15149;"	d
+SET_RG_PGAG_DPDCAL	smac/hal/ssv6006c/ssv6006C_reg.h	13997;"	d
+SET_RG_PGAG_RCCAL	smac/hal/ssv6006c/ssv6006C_reg.h	13990;"	d
+SET_RG_PGAG_RXIQCAL	smac/hal/ssv6006c/ssv6006C_reg.h	13994;"	d
+SET_RG_PGAG_TXCAL	smac/hal/ssv6006c/ssv6006C_reg.h	13991;"	d
+SET_RG_PGA_REFDB_SAT	include/ssv6200_reg.h	7562;"	d
+SET_RG_PGA_REFDB_SAT_B	smac/hal/ssv6006c/ssv6006C_reg.h	15141;"	d
+SET_RG_PGA_REFDB_SAT_GN	smac/hal/ssv6006c/ssv6006C_reg.h	15145;"	d
+SET_RG_PGA_REFDB_TOP	include/ssv6200_reg.h	7563;"	d
+SET_RG_PGA_REFDB_TOP_B	smac/hal/ssv6006c/ssv6006C_reg.h	15142;"	d
+SET_RG_PGA_REFDB_TOP_GN	smac/hal/ssv6006c/ssv6006C_reg.h	15146;"	d
+SET_RG_PGA_REF_UND	include/ssv6200_reg.h	7564;"	d
+SET_RG_PGA_REF_UND_B	smac/hal/ssv6006c/ssv6006C_reg.h	15143;"	d
+SET_RG_PGA_REF_UND_GN	smac/hal/ssv6006c/ssv6006C_reg.h	15147;"	d
+SET_RG_PHASE_17P5M	smac/hal/ssv6006c/ssv6006C_reg.h	14556;"	d
+SET_RG_PHASE_1M	smac/hal/ssv6006c/ssv6006C_reg.h	14559;"	d
+SET_RG_PHASE_2P5M	smac/hal/ssv6006c/ssv6006C_reg.h	14557;"	d
+SET_RG_PHASE_35M	smac/hal/ssv6006c/ssv6006C_reg.h	14560;"	d
+SET_RG_PHASE_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	14541;"	d
+SET_RG_PHASE_RND_EN	smac/hal/ssv6006c/ssv6006C_reg.h	14579;"	d
+SET_RG_PHASE_RXIQ_1M	smac/hal/ssv6006c/ssv6006C_reg.h	14558;"	d
+SET_RG_PHASE_STEP_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	14540;"	d
+SET_RG_PHEST_EN	include/ssv6200_reg.h	8017;"	d
+SET_RG_PHEST_STBY	include/ssv6200_reg.h	8016;"	d
+SET_RG_PHY11BGN_MD_EN	include/ssv6200_reg.h	7522;"	d
+SET_RG_PHY11BGN_MD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15108;"	d
+SET_RG_PHY11B_MD_EN	include/ssv6200_reg.h	7519;"	d
+SET_RG_PHY11B_MD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15105;"	d
+SET_RG_PHY11GN_MD_EN	include/ssv6200_reg.h	7518;"	d
+SET_RG_PHY11GN_MD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15104;"	d
+SET_RG_PHYRXFIFO_MD_EN	include/ssv6200_reg.h	7520;"	d
+SET_RG_PHYRXFIFO_MD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15106;"	d
+SET_RG_PHYRX_MD_EN	include/ssv6200_reg.h	7516;"	d
+SET_RG_PHYRX_MD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15102;"	d
+SET_RG_PHYTXFIFO_MD_EN	include/ssv6200_reg.h	7521;"	d
+SET_RG_PHYTXFIFO_MD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15107;"	d
+SET_RG_PHYTX_MD_EN	include/ssv6200_reg.h	7517;"	d
+SET_RG_PHYTX_MD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15103;"	d
+SET_RG_PHY_IQ_TRIG_SEL	include/ssv6200_reg.h	7527;"	d
+SET_RG_PHY_IQ_TRIG_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	15111;"	d
+SET_RG_PHY_LPBK	include/ssv6200_reg.h	6658;"	d
+SET_RG_PHY_LPBK	smac/hal/ssv6006c/ssv6006C_reg.h	10754;"	d
+SET_RG_PHY_MD_EN	include/ssv6200_reg.h	7515;"	d
+SET_RG_PHY_MD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15101;"	d
+SET_RG_PHY_RST_N	smac/hal/ssv6006c/ssv6006C_reg.h	15017;"	d
+SET_RG_PILOT_BNDRY_SHIFT	include/ssv6200_reg.h	7908;"	d
+SET_RG_PKT_MODE	include/ssv6200_reg.h	7531;"	d
+SET_RG_PKT_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	15114;"	d
+SET_RG_PMDLBK	include/ssv6200_reg.h	7499;"	d
+SET_RG_PMDLBK	smac/hal/ssv6006c/ssv6006C_reg.h	15086;"	d
+SET_RG_PMU_ENTER_SLEEP_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	15001;"	d
+SET_RG_POST_CLK_EN	include/ssv6200_reg.h	7975;"	d
+SET_RG_POST_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15598;"	d
+SET_RG_POS_DES_11B_L_EXT	include/ssv6200_reg.h	7768;"	d
+SET_RG_POS_DES_11GN_L_EXT	include/ssv6200_reg.h	7848;"	d
+SET_RG_POS_DES_L_EXT_11B_RX	smac/hal/ssv6006c/ssv6006C_reg.h	15350;"	d
+SET_RG_POS_DES_L_EXT_11GN_RX	smac/hal/ssv6006c/ssv6006C_reg.h	15446;"	d
+SET_RG_POW16_CNT_TH	include/ssv6200_reg.h	7895;"	d
+SET_RG_POW16_CNT_TH	smac/hal/ssv6006c/ssv6006C_reg.h	15524;"	d
+SET_RG_POW16_SHORT_CNT_LMT	include/ssv6200_reg.h	7896;"	d
+SET_RG_POW16_SHORT_CNT_LMT	smac/hal/ssv6006c/ssv6006C_reg.h	15525;"	d
+SET_RG_POW16_TH_L	include/ssv6200_reg.h	7897;"	d
+SET_RG_POW16_TH_L	smac/hal/ssv6006c/ssv6006C_reg.h	15526;"	d
+SET_RG_PRE_DC_AUTO	smac/hal/ssv6006c/ssv6006C_reg.h	14577;"	d
+SET_RG_PRE_DC_POLA_INV	smac/hal/ssv6006c/ssv6006C_reg.h	14575;"	d
+SET_RG_PRE_DES_11B_DLY	include/ssv6200_reg.h	7769;"	d
+SET_RG_PRE_DES_11GN_DLY	include/ssv6200_reg.h	7849;"	d
+SET_RG_PRE_DES_DLY_11B_RX	smac/hal/ssv6006c/ssv6006C_reg.h	15351;"	d
+SET_RG_PRE_DES_DLY_11GN_RX	smac/hal/ssv6006c/ssv6006C_reg.h	15447;"	d
+SET_RG_PRIMARY_CH_SIDE	smac/hal/ssv6006c/ssv6006C_reg.h	15097;"	d
+SET_RG_PRM	include/ssv6200_reg.h	7533;"	d
+SET_RG_PRM	smac/hal/ssv6006c/ssv6006C_reg.h	15116;"	d
+SET_RG_PROC_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	14574;"	d
+SET_RG_PSDU_TIME_OFFSET_11B	smac/hal/ssv6006c/ssv6006C_reg.h	15398;"	d
+SET_RG_PSDU_TIME_OFFSET_GF	smac/hal/ssv6006c/ssv6006C_reg.h	15563;"	d
+SET_RG_PSDU_TIME_OFFSET_LEGACY	smac/hal/ssv6006c/ssv6006C_reg.h	15565;"	d
+SET_RG_PSDU_TIME_OFFSET_MF	smac/hal/ssv6006c/ssv6006C_reg.h	15564;"	d
+SET_RG_PULSE_NUMBER	smac/hal/ssv6006c/ssv6006C_reg.h	15608;"	d
+SET_RG_PWRON_DLY_TH_11B	include/ssv6200_reg.h	7815;"	d
+SET_RG_PWRON_DLY_TH_11B_RX	smac/hal/ssv6006c/ssv6006C_reg.h	15393;"	d
+SET_RG_PWRON_DLY_TH_11GN	include/ssv6200_reg.h	7893;"	d
+SET_RG_PWRON_DLY_TH_11GN_RX	smac/hal/ssv6006c/ssv6006C_reg.h	15519;"	d
+SET_RG_PWR_BIT_CNT_TH	smac/hal/ssv6006c/ssv6006C_reg.h	15397;"	d
+SET_RG_PWR_CNT_TH	smac/hal/ssv6006c/ssv6006C_reg.h	15396;"	d
+SET_RG_PWR_TH	smac/hal/ssv6006c/ssv6006C_reg.h	15395;"	d
+SET_RG_PW_CHIRP_MAX	smac/hal/ssv6006c/ssv6006C_reg.h	15631;"	d
+SET_RG_PW_CHIRP_MIN	smac/hal/ssv6006c/ssv6006C_reg.h	15630;"	d
+SET_RG_PW_MAX	smac/hal/ssv6006c/ssv6006C_reg.h	15604;"	d
+SET_RG_PW_MIN	smac/hal/ssv6006c/ssv6006C_reg.h	15603;"	d
+SET_RG_Q_INV	include/ssv6200_reg.h	7504;"	d
+SET_RG_Q_INV	smac/hal/ssv6006c/ssv6006C_reg.h	14492;"	d
+SET_RG_Q_INV_BB	smac/hal/ssv6006c/ssv6006C_reg.h	15091;"	d
+SET_RG_RADAR_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15611;"	d
+SET_RG_RAM_00	smac/hal/ssv6006c/ssv6006C_reg.h	15070;"	d
+SET_RG_RAM_01	smac/hal/ssv6006c/ssv6006C_reg.h	15071;"	d
+SET_RG_RAM_02	smac/hal/ssv6006c/ssv6006C_reg.h	15072;"	d
+SET_RG_RAM_03	smac/hal/ssv6006c/ssv6006C_reg.h	15073;"	d
+SET_RG_RAM_04	smac/hal/ssv6006c/ssv6006C_reg.h	15074;"	d
+SET_RG_RAM_05	smac/hal/ssv6006c/ssv6006C_reg.h	15075;"	d
+SET_RG_RAM_06	smac/hal/ssv6006c/ssv6006C_reg.h	15076;"	d
+SET_RG_RAM_07	smac/hal/ssv6006c/ssv6006C_reg.h	15077;"	d
+SET_RG_RAM_08	smac/hal/ssv6006c/ssv6006C_reg.h	15078;"	d
+SET_RG_RAM_09	smac/hal/ssv6006c/ssv6006C_reg.h	15079;"	d
+SET_RG_RAM_10	smac/hal/ssv6006c/ssv6006C_reg.h	15080;"	d
+SET_RG_RAM_11	smac/hal/ssv6006c/ssv6006C_reg.h	15081;"	d
+SET_RG_RAM_12	smac/hal/ssv6006c/ssv6006C_reg.h	15082;"	d
+SET_RG_RAM_13	smac/hal/ssv6006c/ssv6006C_reg.h	15083;"	d
+SET_RG_RAM_14	smac/hal/ssv6006c/ssv6006C_reg.h	15084;"	d
+SET_RG_RAM_15	smac/hal/ssv6006c/ssv6006C_reg.h	15085;"	d
+SET_RG_RATE	include/ssv6200_reg.h	7535;"	d
+SET_RG_RATE	smac/hal/ssv6006c/ssv6006C_reg.h	15118;"	d
+SET_RG_RATE_MCS_STAT	smac/hal/ssv6006c/ssv6006C_reg.h	15587;"	d
+SET_RG_RATE_STAT	smac/hal/ssv6006c/ssv6006C_reg.h	15418;"	d
+SET_RG_RCAL_CODE_CWD	include/ssv6200_reg.h	8402;"	d
+SET_RG_RCAL_CODE_CWR	include/ssv6200_reg.h	8401;"	d
+SET_RG_RCAL_SPD	include/ssv6200_reg.h	8399;"	d
+SET_RG_RCAL_TMR	include/ssv6200_reg.h	8400;"	d
+SET_RG_RCCAL_DATA_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	14580;"	d
+SET_RG_RCCAL_POLAR_INV	smac/hal/ssv6006c/ssv6006C_reg.h	14567;"	d
+SET_RG_RDYACK_SEL	include/ssv6200_reg.h	7500;"	d
+SET_RG_REBOOT	include/ssv6200_reg.h	4931;"	d
+SET_RG_REBOOT	smac/hal/ssv6006c/ssv6006C_reg.h	9290;"	d
+SET_RG_RESERVED_11B_RX	smac/hal/ssv6006c/ssv6006C_reg.h	15399;"	d
+SET_RG_RESERVED_11B_TX	smac/hal/ssv6006c/ssv6006C_reg.h	15349;"	d
+SET_RG_RESERVED_11GN_RX	smac/hal/ssv6006c/ssv6006C_reg.h	15448;"	d
+SET_RG_RESERVED_11GN_TX	smac/hal/ssv6006c/ssv6006C_reg.h	15445;"	d
+SET_RG_RESERVED_CMM	smac/hal/ssv6006c/ssv6006C_reg.h	15343;"	d
+SET_RG_RESERVED_DPD	smac/hal/ssv6006c/ssv6006C_reg.h	14943;"	d
+SET_RG_RFG	include/ssv6200_reg.h	8121;"	d
+SET_RG_RFG	smac/hal/ssv6006c/ssv6006C_reg.h	13372;"	d
+SET_RG_RFGC_OW	include/ssv6200_reg.h	7569;"	d
+SET_RG_RFGC_OW	smac/hal/ssv6006c/ssv6006C_reg.h	15152;"	d
+SET_RG_RFGC_SET	include/ssv6200_reg.h	7568;"	d
+SET_RG_RFGC_SET	smac/hal/ssv6006c/ssv6006C_reg.h	15151;"	d
+SET_RG_RFG_DPDCAL	smac/hal/ssv6006c/ssv6006C_reg.h	13996;"	d
+SET_RG_RFG_RXIQCAL	smac/hal/ssv6006c/ssv6006C_reg.h	13993;"	d
+SET_RG_RFTX_FALL_TIME	include/ssv6200_reg.h	7674;"	d
+SET_RG_RFTX_RISE_TIME	include/ssv6200_reg.h	7670;"	d
+SET_RG_RF_5G_BAND	smac/hal/ssv6006c/ssv6006C_reg.h	15096;"	d
+SET_RG_RF_BB_CLK_SEL	include/ssv6200_reg.h	7514;"	d
+SET_RG_RF_D_REG	include/ssv6200_reg.h	8434;"	d
+SET_RG_RF_PWR_BARKER_CCK	smac/hal/ssv6006c/ssv6006C_reg.h	15288;"	d
+SET_RG_RF_PWR_HT20_16QAM	smac/hal/ssv6006c/ssv6006C_reg.h	15295;"	d
+SET_RG_RF_PWR_HT20_64QAM	smac/hal/ssv6006c/ssv6006C_reg.h	15294;"	d
+SET_RG_RF_PWR_HT20_BPSK	smac/hal/ssv6006c/ssv6006C_reg.h	15297;"	d
+SET_RG_RF_PWR_HT20_QPSK	smac/hal/ssv6006c/ssv6006C_reg.h	15296;"	d
+SET_RG_RF_PWR_HT40_16QAM	smac/hal/ssv6006c/ssv6006C_reg.h	15299;"	d
+SET_RG_RF_PWR_HT40_64QAM	smac/hal/ssv6006c/ssv6006C_reg.h	15298;"	d
+SET_RG_RF_PWR_HT40_BPSK	smac/hal/ssv6006c/ssv6006C_reg.h	15301;"	d
+SET_RG_RF_PWR_HT40_QPSK	smac/hal/ssv6006c/ssv6006C_reg.h	15300;"	d
+SET_RG_RF_PWR_LEGACY_16QAM	smac/hal/ssv6006c/ssv6006C_reg.h	15291;"	d
+SET_RG_RF_PWR_LEGACY_64QAM	smac/hal/ssv6006c/ssv6006C_reg.h	15290;"	d
+SET_RG_RF_PWR_LEGACY_BPSK	smac/hal/ssv6006c/ssv6006C_reg.h	15293;"	d
+SET_RG_RF_PWR_LEGACY_QPSK	smac/hal/ssv6006c/ssv6006C_reg.h	15292;"	d
+SET_RG_RF_PWR_MAN_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15289;"	d
+SET_RG_RF_REF_SAT	include/ssv6200_reg.h	7565;"	d
+SET_RG_RF_REF_SAT_B	smac/hal/ssv6006c/ssv6006C_reg.h	15144;"	d
+SET_RG_RF_REF_SAT_GN	smac/hal/ssv6006c/ssv6006C_reg.h	15148;"	d
+SET_RG_RIFS_EN	include/ssv6200_reg.h	7965;"	d
+SET_RG_RIFS_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15590;"	d
+SET_RG_RSSIADC_RO_BIT	include/ssv6200_reg.h	8427;"	d
+SET_RG_RSSI_CLOCK_GATING	include/ssv6200_reg.h	8199;"	d
+SET_RG_RSSI_CLOCK_GATING	smac/hal/ssv6006c/ssv6006C_reg.h	13496;"	d
+SET_RG_RSSI_EDGE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	14490;"	d
+SET_RG_RSSI_EDGE_SEL_BB	smac/hal/ssv6006c/ssv6006C_reg.h	15088;"	d
+SET_RG_RSSI_INV	include/ssv6200_reg.h	7658;"	d
+SET_RG_RSSI_INV	smac/hal/ssv6006c/ssv6006C_reg.h	15212;"	d
+SET_RG_RSSI_OFFSET	include/ssv6200_reg.h	7657;"	d
+SET_RG_RSSI_OFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	15211;"	d
+SET_RG_RTC_CAL_MODE	include/ssv6200_reg.h	8156;"	d
+SET_RG_RTC_CAL_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	14991;"	d
+SET_RG_RTC_CAL_TARGET_COUNT	include/ssv6200_reg.h	8433;"	d
+SET_RG_RTC_CAL_TARGET_COUNT	smac/hal/ssv6006c/ssv6006C_reg.h	14989;"	d
+SET_RG_RTC_DUMMIES	include/ssv6200_reg.h	6088;"	d
+SET_RG_RTC_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15006;"	d
+SET_RG_RTC_INT_ALARM_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	15009;"	d
+SET_RG_RTC_INT_SEC_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	15008;"	d
+SET_RG_RTC_OFFSET	include/ssv6200_reg.h	8432;"	d
+SET_RG_RTC_OFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	14988;"	d
+SET_RG_RTC_OSC_RES_SW	include/ssv6200_reg.h	6077;"	d
+SET_RG_RTC_OSC_RES_SW_MANUAL	include/ssv6200_reg.h	6076;"	d
+SET_RG_RTC_OSC_RES_SW_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	14990;"	d
+SET_RG_RTC_OSC_RES_SW_MANUAL_EN	include/ssv6200_reg.h	6082;"	d
+SET_RG_RTC_OSC_RES_SW_MANUAL_EN	smac/hal/ssv6006c/ssv6006C_reg.h	14993;"	d
+SET_RG_RTC_RDY_DEGLITCH_TIMER	include/ssv6200_reg.h	6083;"	d
+SET_RG_RTC_RS1	smac/hal/ssv6006c/ssv6006C_reg.h	14983;"	d
+SET_RG_RTC_RS2	smac/hal/ssv6006c/ssv6006C_reg.h	14984;"	d
+SET_RG_RTC_SEC_ALARM_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	15014;"	d
+SET_RG_RTC_SEC_START_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15013;"	d
+SET_RG_RXAGC_OW	include/ssv6200_reg.h	7572;"	d
+SET_RG_RXAGC_OW	smac/hal/ssv6006c/ssv6006C_reg.h	15155;"	d
+SET_RG_RXAGC_SET	include/ssv6200_reg.h	7571;"	d
+SET_RG_RXAGC_SET	smac/hal/ssv6006c/ssv6006C_reg.h	15154;"	d
+SET_RG_RXIQ_EMU_IDX	include/ssv6200_reg.h	8049;"	d
+SET_RG_RXIQ_NOSHRINK	include/ssv6200_reg.h	8005;"	d
+SET_RG_RXIQ_NOSHRK	smac/hal/ssv6006c/ssv6006C_reg.h	14487;"	d
+SET_RG_RXRF_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	13973;"	d
+SET_RG_RXRF_R2T_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	13982;"	d
+SET_RG_RXRF_T2R_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	13978;"	d
+SET_RG_RX_ABBCFIX	include/ssv6200_reg.h	8171;"	d
+SET_RG_RX_ABBCTUNE	include/ssv6200_reg.h	8172;"	d
+SET_RG_RX_ABBOUT_TRI_STATE	include/ssv6200_reg.h	8173;"	d
+SET_RG_RX_ABBOUT_TRI_STATE	smac/hal/ssv6006c/ssv6006C_reg.h	13429;"	d
+SET_RG_RX_ABB_N_MODE	include/ssv6200_reg.h	8174;"	d
+SET_RG_RX_ADCRSSI_CLKSEL	include/ssv6200_reg.h	8196;"	d
+SET_RG_RX_ADCRSSI_CLKSEL	smac/hal/ssv6006c/ssv6006C_reg.h	13495;"	d
+SET_RG_RX_ADCRSSI_VCM	include/ssv6200_reg.h	8197;"	d
+SET_RG_RX_ADCRSSI_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	13493;"	d
+SET_RG_RX_ADC_CLKSEL	smac/hal/ssv6006c/ssv6006C_reg.h	13624;"	d
+SET_RG_RX_ADC_DNLEN	smac/hal/ssv6006c/ssv6006C_reg.h	13625;"	d
+SET_RG_RX_ADC_I_RO_BIT	include/ssv6200_reg.h	8428;"	d
+SET_RG_RX_ADC_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	13391;"	d
+SET_RG_RX_ADC_METAEN	smac/hal/ssv6006c/ssv6006C_reg.h	13626;"	d
+SET_RG_RX_ADC_Q_RO_BIT	include/ssv6200_reg.h	8429;"	d
+SET_RG_RX_ADC_TFLAG	smac/hal/ssv6006c/ssv6006C_reg.h	13627;"	d
+SET_RG_RX_ADC_TSEL	smac/hal/ssv6006c/ssv6006C_reg.h	13628;"	d
+SET_RG_RX_AGC	include/ssv6200_reg.h	8119;"	d
+SET_RG_RX_AGC	smac/hal/ssv6006c/ssv6006C_reg.h	13369;"	d
+SET_RG_RX_BEACON_CRC_BYPASS	smac/hal/ssv6006c/ssv6006C_reg.h	15309;"	d
+SET_RG_RX_BEACON_INTERVAL	smac/hal/ssv6006c/ssv6006C_reg.h	15310;"	d
+SET_RG_RX_BEACON_LOSS_CNT_LMT	smac/hal/ssv6006c/ssv6006C_reg.h	15308;"	d
+SET_RG_RX_BEACON_TU	smac/hal/ssv6006c/ssv6006C_reg.h	15306;"	d
+SET_RG_RX_DC_POLAR_INV	smac/hal/ssv6006c/ssv6006C_reg.h	14566;"	d
+SET_RG_RX_DC_RESOLUTION	smac/hal/ssv6006c/ssv6006C_reg.h	14568;"	d
+SET_RG_RX_DES_LEN_LO	include/ssv6200_reg.h	7633;"	d
+SET_RG_RX_DES_LEN_UP	include/ssv6200_reg.h	7634;"	d
+SET_RG_RX_DES_L_LEN_LO	include/ssv6200_reg.h	7636;"	d
+SET_RG_RX_DES_L_LEN_UP	include/ssv6200_reg.h	7637;"	d
+SET_RG_RX_DES_L_LEN_UP_COMB	include/ssv6200_reg.h	7639;"	d
+SET_RG_RX_DES_MODE	include/ssv6200_reg.h	7632;"	d
+SET_RG_RX_DES_MODE_COMB	include/ssv6200_reg.h	7642;"	d
+SET_RG_RX_DES_RATE	include/ssv6200_reg.h	7631;"	d
+SET_RG_RX_DES_RATE_COMB	include/ssv6200_reg.h	7641;"	d
+SET_RG_RX_DES_RCPI	include/ssv6200_reg.h	7644;"	d
+SET_RG_RX_DES_RCPI_GN	include/ssv6200_reg.h	7655;"	d
+SET_RG_RX_DES_SNR	include/ssv6200_reg.h	7643;"	d
+SET_RG_RX_DES_SNR_GN	include/ssv6200_reg.h	7654;"	d
+SET_RG_RX_DES_SRVC_LO	include/ssv6200_reg.h	7645;"	d
+SET_RG_RX_DES_SRVC_UP	include/ssv6200_reg.h	7635;"	d
+SET_RG_RX_DES_TYPE	include/ssv6200_reg.h	7638;"	d
+SET_RG_RX_DES_TYPE_COMB	include/ssv6200_reg.h	7640;"	d
+SET_RG_RX_DIV2_CORE	include/ssv6200_reg.h	8210;"	d
+SET_RG_RX_DIV2_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	13383;"	d
+SET_RG_RX_EN_LOOPA	include/ssv6200_reg.h	8175;"	d
+SET_RG_RX_FFT_SCALE	include/ssv6200_reg.h	7871;"	d
+SET_RG_RX_FIFO_FULL_CNT_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15323;"	d
+SET_RG_RX_FILTERI1ST	include/ssv6200_reg.h	8176;"	d
+SET_RG_RX_FILTERI2ND	include/ssv6200_reg.h	8177;"	d
+SET_RG_RX_FILTERI3RD	include/ssv6200_reg.h	8178;"	d
+SET_RG_RX_FILTERI_COURSE	include/ssv6200_reg.h	8179;"	d
+SET_RG_RX_FILTERVCM	include/ssv6200_reg.h	8180;"	d
+SET_RG_RX_FILTER_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	13389;"	d
+SET_RG_RX_GAIN_MANUAL	include/ssv6200_reg.h	8120;"	d
+SET_RG_RX_GAIN_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	13366;"	d
+SET_RG_RX_HG_LNAHGN_BIAS	include/ssv6200_reg.h	8220;"	d
+SET_RG_RX_HG_LNAHGP_BIAS	include/ssv6200_reg.h	8221;"	d
+SET_RG_RX_HG_LNALG_BIAS	include/ssv6200_reg.h	8222;"	d
+SET_RG_RX_HG_LNA_GC	include/ssv6200_reg.h	8219;"	d
+SET_RG_RX_HG_TZ_CAP	include/ssv6200_reg.h	8224;"	d
+SET_RG_RX_HG_TZ_GC	include/ssv6200_reg.h	8223;"	d
+SET_RG_RX_HPF300K	include/ssv6200_reg.h	8182;"	d
+SET_RG_RX_HPF3M	include/ssv6200_reg.h	8181;"	d
+SET_RG_RX_HPFI	include/ssv6200_reg.h	8183;"	d
+SET_RG_RX_HPF_FINALCORNER	include/ssv6200_reg.h	8184;"	d
+SET_RG_RX_HPF_SETTLE1_C	include/ssv6200_reg.h	8185;"	d
+SET_RG_RX_HPF_SETTLE1_R	include/ssv6200_reg.h	8186;"	d
+SET_RG_RX_HPF_SETTLE2_C	include/ssv6200_reg.h	8187;"	d
+SET_RG_RX_HPF_SETTLE2_R	include/ssv6200_reg.h	8188;"	d
+SET_RG_RX_HPF_VCMCON	include/ssv6200_reg.h	8190;"	d
+SET_RG_RX_HPF_VCMCON2	include/ssv6200_reg.h	8189;"	d
+SET_RG_RX_IDACA_COARSE_PMOS_ON	smac/hal/ssv6006c/ssv6006C_reg.h	13497;"	d
+SET_RG_RX_IQCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	13988;"	d
+SET_RG_RX_IQCAL_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	13418;"	d
+SET_RG_RX_IQ_2500_ALPHA	smac/hal/ssv6006c/ssv6006C_reg.h	14520;"	d
+SET_RG_RX_IQ_2500_THETA	smac/hal/ssv6006c/ssv6006C_reg.h	14521;"	d
+SET_RG_RX_IQ_5100_ALPHA	smac/hal/ssv6006c/ssv6006C_reg.h	14524;"	d
+SET_RG_RX_IQ_5100_THETA	smac/hal/ssv6006c/ssv6006C_reg.h	14525;"	d
+SET_RG_RX_IQ_5500_ALPHA	smac/hal/ssv6006c/ssv6006C_reg.h	14528;"	d
+SET_RG_RX_IQ_5500_THETA	smac/hal/ssv6006c/ssv6006C_reg.h	14529;"	d
+SET_RG_RX_IQ_5700_ALPHA	smac/hal/ssv6006c/ssv6006C_reg.h	14532;"	d
+SET_RG_RX_IQ_5700_THETA	smac/hal/ssv6006c/ssv6006C_reg.h	14533;"	d
+SET_RG_RX_IQ_5900_ALPHA	smac/hal/ssv6006c/ssv6006C_reg.h	14536;"	d
+SET_RG_RX_IQ_5900_THETA	smac/hal/ssv6006c/ssv6006C_reg.h	14537;"	d
+SET_RG_RX_IQ_ALPHA	include/ssv6200_reg.h	8004;"	d
+SET_RG_RX_IQ_ALPHA	smac/hal/ssv6006c/ssv6006C_reg.h	14484;"	d
+SET_RG_RX_IQ_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	14486;"	d
+SET_RG_RX_IQ_SRC	include/ssv6200_reg.h	8039;"	d
+SET_RG_RX_IQ_SWP	include/ssv6200_reg.h	8037;"	d
+SET_RG_RX_IQ_THETA	include/ssv6200_reg.h	8003;"	d
+SET_RG_RX_IQ_THETA	smac/hal/ssv6006c/ssv6006C_reg.h	14485;"	d
+SET_RG_RX_I_OFFSET	include/ssv6200_reg.h	8035;"	d
+SET_RG_RX_I_SCALE	include/ssv6200_reg.h	8033;"	d
+SET_RG_RX_LG_LNAHGN_BIAS	include/ssv6200_reg.h	8232;"	d
+SET_RG_RX_LG_LNAHGP_BIAS	include/ssv6200_reg.h	8233;"	d
+SET_RG_RX_LG_LNALG_BIAS	include/ssv6200_reg.h	8234;"	d
+SET_RG_RX_LG_LNA_GC	include/ssv6200_reg.h	8231;"	d
+SET_RG_RX_LG_TZ_CAP	include/ssv6200_reg.h	8236;"	d
+SET_RG_RX_LG_TZ_GC	include/ssv6200_reg.h	8235;"	d
+SET_RG_RX_LNA_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	13379;"	d
+SET_RG_RX_LNA_SETTLE	include/ssv6200_reg.h	8250;"	d
+SET_RG_RX_LNA_SETTLE	smac/hal/ssv6006c/ssv6006C_reg.h	13506;"	d
+SET_RG_RX_LNA_TRI_SEL	include/ssv6200_reg.h	8249;"	d
+SET_RG_RX_LNA_TRI_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	13505;"	d
+SET_RG_RX_LOBUF	include/ssv6200_reg.h	8211;"	d
+SET_RG_RX_LOBUF_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	13385;"	d
+SET_RG_RX_MG_LNAHGN_BIAS	include/ssv6200_reg.h	8226;"	d
+SET_RG_RX_MG_LNAHGP_BIAS	include/ssv6200_reg.h	8227;"	d
+SET_RG_RX_MG_LNALG_BIAS	include/ssv6200_reg.h	8228;"	d
+SET_RG_RX_MG_LNA_GC	include/ssv6200_reg.h	8225;"	d
+SET_RG_RX_MG_TZ_CAP	include/ssv6200_reg.h	8230;"	d
+SET_RG_RX_MG_TZ_GC	include/ssv6200_reg.h	8229;"	d
+SET_RG_RX_MIXER_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	13381;"	d
+SET_RG_RX_MONITOR_ON	smac/hal/ssv6006c/ssv6006C_reg.h	15302;"	d
+SET_RG_RX_N_RCCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	13989;"	d
+SET_RG_RX_OUTVCM	include/ssv6200_reg.h	8191;"	d
+SET_RG_RX_PADPD_DATA_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	14836;"	d
+SET_RG_RX_PADPD_DC_RM_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	14845;"	d
+SET_RG_RX_PADPD_DC_RM_LEAKY_FACTOR	smac/hal/ssv6006c/ssv6006C_reg.h	14844;"	d
+SET_RG_RX_PADPD_EN	smac/hal/ssv6006c/ssv6006C_reg.h	14833;"	d
+SET_RG_RX_PADPD_LATCH	smac/hal/ssv6006c/ssv6006C_reg.h	14835;"	d
+SET_RG_RX_PADPD_LEAKY_FACTOR	smac/hal/ssv6006c/ssv6006C_reg.h	14834;"	d
+SET_RG_RX_PADPD_RATE	smac/hal/ssv6006c/ssv6006C_reg.h	14838;"	d
+SET_RG_RX_PADPD_TONE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	14837;"	d
+SET_RG_RX_PKT_ADDR1_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	15312;"	d
+SET_RG_RX_PKT_ADDR1_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	15313;"	d
+SET_RG_RX_PKT_ADDR1_ON	smac/hal/ssv6006c/ssv6006C_reg.h	15305;"	d
+SET_RG_RX_PKT_ADDR2_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	15314;"	d
+SET_RG_RX_PKT_ADDR2_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	15315;"	d
+SET_RG_RX_PKT_ADDR2_ON	smac/hal/ssv6006c/ssv6006C_reg.h	15304;"	d
+SET_RG_RX_PKT_ADDR3_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	15316;"	d
+SET_RG_RX_PKT_ADDR3_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	15317;"	d
+SET_RG_RX_PKT_ADDR3_ON	smac/hal/ssv6006c/ssv6006C_reg.h	15303;"	d
+SET_RG_RX_PKT_FC	smac/hal/ssv6006c/ssv6006C_reg.h	15311;"	d
+SET_RG_RX_PKT_TIMER_LMT	smac/hal/ssv6006c/ssv6006C_reg.h	15307;"	d
+SET_RG_RX_PRE_DC_RESOLUTION	smac/hal/ssv6006c/ssv6006C_reg.h	14576;"	d
+SET_RG_RX_Q_OFFSET	include/ssv6200_reg.h	8036;"	d
+SET_RG_RX_Q_SCALE	include/ssv6200_reg.h	8034;"	d
+SET_RG_RX_RCCAL_40M_TARG	smac/hal/ssv6006c/ssv6006C_reg.h	14569;"	d
+SET_RG_RX_RCCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	13985;"	d
+SET_RG_RX_RCCAL_TARG	smac/hal/ssv6006c/ssv6006C_reg.h	14565;"	d
+SET_RG_RX_REC_LPFCORNER	include/ssv6200_reg.h	8198;"	d
+SET_RG_RX_REC_LPFCORNER	smac/hal/ssv6006c/ssv6006C_reg.h	13494;"	d
+SET_RG_RX_RSSIADC_TH	smac/hal/ssv6006c/ssv6006C_reg.h	14488;"	d
+SET_RG_RX_RSSI_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	13393;"	d
+SET_RG_RX_SCALOAD_STEP0	smac/hal/ssv6006c/ssv6006C_reg.h	14445;"	d
+SET_RG_RX_SCALOAD_STEP1	smac/hal/ssv6006c/ssv6006C_reg.h	14446;"	d
+SET_RG_RX_SCALOAD_STEP2	smac/hal/ssv6006c/ssv6006C_reg.h	14447;"	d
+SET_RG_RX_SCALOAD_STEP3	smac/hal/ssv6006c/ssv6006C_reg.h	14448;"	d
+SET_RG_RX_SCALOAD_STEP4	smac/hal/ssv6006c/ssv6006C_reg.h	14449;"	d
+SET_RG_RX_SCALOAD_STEP5	smac/hal/ssv6006c/ssv6006C_reg.h	14450;"	d
+SET_RG_RX_SCALOAD_STEP6	smac/hal/ssv6006c/ssv6006C_reg.h	14451;"	d
+SET_RG_RX_SCAMA_STEP0	smac/hal/ssv6006c/ssv6006C_reg.h	14438;"	d
+SET_RG_RX_SCAMA_STEP1	smac/hal/ssv6006c/ssv6006C_reg.h	14439;"	d
+SET_RG_RX_SCAMA_STEP2	smac/hal/ssv6006c/ssv6006C_reg.h	14440;"	d
+SET_RG_RX_SCAMA_STEP3	smac/hal/ssv6006c/ssv6006C_reg.h	14441;"	d
+SET_RG_RX_SCAMA_STEP4	smac/hal/ssv6006c/ssv6006C_reg.h	14442;"	d
+SET_RG_RX_SCAMA_STEP5	smac/hal/ssv6006c/ssv6006C_reg.h	14443;"	d
+SET_RG_RX_SCAMA_STEP6	smac/hal/ssv6006c/ssv6006C_reg.h	14444;"	d
+SET_RG_RX_SGN_IN	include/ssv6200_reg.h	8038;"	d
+SET_RG_RX_SQDC	include/ssv6200_reg.h	8209;"	d
+SET_RG_RX_SQDC	smac/hal/ssv6006c/ssv6006C_reg.h	13436;"	d
+SET_RG_RX_TZI	include/ssv6200_reg.h	8192;"	d
+SET_RG_RX_TZ_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	13387;"	d
+SET_RG_RX_TZ_OUT_TRISTATE	include/ssv6200_reg.h	8193;"	d
+SET_RG_RX_TZ_OUT_TRISTATE	smac/hal/ssv6006c/ssv6006C_reg.h	13415;"	d
+SET_RG_RX_TZ_OUT_TRISTATE_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	13414;"	d
+SET_RG_RX_TZ_VCM	include/ssv6200_reg.h	8194;"	d
+SET_RG_RX_ULG_LNAHGN_BIAS	include/ssv6200_reg.h	8238;"	d
+SET_RG_RX_ULG_LNAHGP_BIAS	include/ssv6200_reg.h	8239;"	d
+SET_RG_RX_ULG_LNALG_BIAS	include/ssv6200_reg.h	8240;"	d
+SET_RG_RX_ULG_LNA_GC	include/ssv6200_reg.h	8237;"	d
+SET_RG_RX_ULG_TZ_CAP	include/ssv6200_reg.h	8242;"	d
+SET_RG_RX_ULG_TZ_GC	include/ssv6200_reg.h	8241;"	d
+SET_RG_SARADC_5G_TSSI	smac/hal/ssv6006c/ssv6006C_reg.h	13637;"	d
+SET_RG_SARADC_BIT	include/ssv6200_reg.h	8421;"	d
+SET_RG_SARADC_THERMAL	include/ssv6200_reg.h	8268;"	d
+SET_RG_SARADC_THERMAL	smac/hal/ssv6006c/ssv6006C_reg.h	13640;"	d
+SET_RG_SARADC_TSSI	include/ssv6200_reg.h	8269;"	d
+SET_RG_SARADC_TSSI	smac/hal/ssv6006c/ssv6006C_reg.h	13641;"	d
+SET_RG_SARADC_VRSEL	include/ssv6200_reg.h	8266;"	d
+SET_RG_SARADC_VRSEL	smac/hal/ssv6006c/ssv6006C_reg.h	13638;"	d
+SET_RG_SB_START_CNT	include/ssv6200_reg.h	7894;"	d
+SET_RG_SB_START_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15520;"	d
+SET_RG_SCR_INIT_SEED	smac/hal/ssv6006c/ssv6006C_reg.h	15441;"	d
+SET_RG_SCR_SEED_MANUANL	smac/hal/ssv6006c/ssv6006C_reg.h	15442;"	d
+SET_RG_SC_CTRL0	smac/hal/ssv6006c/ssv6006C_reg.h	15494;"	d
+SET_RG_SC_CTRL1	smac/hal/ssv6006c/ssv6006C_reg.h	15492;"	d
+SET_RG_SC_CTRL2	smac/hal/ssv6006c/ssv6006C_reg.h	15490;"	d
+SET_RG_SC_CTRL3	smac/hal/ssv6006c/ssv6006C_reg.h	15488;"	d
+SET_RG_SC_CTRL4	smac/hal/ssv6006c/ssv6006C_reg.h	15502;"	d
+SET_RG_SC_CTRL5	smac/hal/ssv6006c/ssv6006C_reg.h	15500;"	d
+SET_RG_SC_CTRL6	smac/hal/ssv6006c/ssv6006C_reg.h	15498;"	d
+SET_RG_SC_CTRL7	smac/hal/ssv6006c/ssv6006C_reg.h	15496;"	d
+SET_RG_SEC_CNT_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	15005;"	d
+SET_RG_SEL_DPLL_CLK	include/ssv6200_reg.h	8140;"	d
+SET_RG_SEL_DPLL_CLK	smac/hal/ssv6006c/ssv6006C_reg.h	14992;"	d
+SET_RG_SERVICE	include/ssv6200_reg.h	7538;"	d
+SET_RG_SERVICE	smac/hal/ssv6006c/ssv6006C_reg.h	15121;"	d
+SET_RG_SFD_BIT_CNT_LMT	include/ssv6200_reg.h	7816;"	d
+SET_RG_SFD_BIT_CNT_LMT	smac/hal/ssv6006c/ssv6006C_reg.h	15394;"	d
+SET_RG_SHIFT_DR_16	include/ssv6200_reg.h	7698;"	d
+SET_RG_SHIFT_DR_64	include/ssv6200_reg.h	7936;"	d
+SET_RG_SHIFT_DR_80	include/ssv6200_reg.h	7929;"	d
+SET_RG_SHORTGI	include/ssv6200_reg.h	7534;"	d
+SET_RG_SHORTGI	smac/hal/ssv6006c/ssv6006C_reg.h	15117;"	d
+SET_RG_SHORT_GI_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15434;"	d
+SET_RG_SIGN_SWAP	include/ssv6200_reg.h	7502;"	d
+SET_RG_SIGN_SWAP	smac/hal/ssv6006c/ssv6006C_reg.h	14495;"	d
+SET_RG_SIGN_SWAP_BB	smac/hal/ssv6006c/ssv6006C_reg.h	15089;"	d
+SET_RG_SIMULATION_MODE_16	include/ssv6200_reg.h	7700;"	d
+SET_RG_SIMULATION_MODE_64	include/ssv6200_reg.h	7938;"	d
+SET_RG_SIMULATION_MODE_80	include/ssv6200_reg.h	7931;"	d
+SET_RG_SLEEP_METHOD	smac/hal/ssv6006c/ssv6006C_reg.h	15002;"	d
+SET_RG_SLEEP_WAKE_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15004;"	d
+SET_RG_SMB_DEF	include/ssv6200_reg.h	7844;"	d
+SET_RG_SMOOTHING	include/ssv6200_reg.h	7539;"	d
+SET_RG_SMOOTHING	smac/hal/ssv6006c/ssv6006C_reg.h	15122;"	d
+SET_RG_SNR_TH_16QAM	include/ssv6200_reg.h	7889;"	d
+SET_RG_SNR_TH_16QAM	smac/hal/ssv6006c/ssv6006C_reg.h	15482;"	d
+SET_RG_SNR_TH_64QAM	include/ssv6200_reg.h	7888;"	d
+SET_RG_SNR_TH_64QAM	smac/hal/ssv6006c/ssv6006C_reg.h	15481;"	d
+SET_RG_SOFT_RST_N_11B_RX	smac/hal/ssv6006c/ssv6006C_reg.h	15421;"	d
+SET_RG_SOFT_RST_N_11GN_RX	smac/hal/ssv6006c/ssv6006C_reg.h	15589;"	d
+SET_RG_SPECTRUM_BW	include/ssv6200_reg.h	7509;"	d
+SET_RG_SPECTRUM_BW	smac/hal/ssv6006c/ssv6006C_reg.h	14543;"	d
+SET_RG_SPECTRUM_EN	include/ssv6200_reg.h	7511;"	d
+SET_RG_SPECTRUM_EN	smac/hal/ssv6006c/ssv6006C_reg.h	14544;"	d
+SET_RG_SPECTRUM_FREQ	include/ssv6200_reg.h	7528;"	d
+SET_RG_SPECTRUM_FREQ_MANUAL	include/ssv6200_reg.h	7510;"	d
+SET_RG_SPECTRUM_LEAKY_FACTOR	include/ssv6200_reg.h	7508;"	d
+SET_RG_SPECTRUM_LO_FIX	smac/hal/ssv6006c/ssv6006C_reg.h	14571;"	d
+SET_RG_SPECTRUM_PWR_UPDATE	smac/hal/ssv6006c/ssv6006C_reg.h	14572;"	d
+SET_RG_STBC	include/ssv6200_reg.h	7542;"	d
+SET_RG_STBC	smac/hal/ssv6006c/ssv6006C_reg.h	15125;"	d
+SET_RG_STBC_EN	include/ssv6200_reg.h	7966;"	d
+SET_RG_STBC_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15591;"	d
+SET_RG_STF_SCALE_20	smac/hal/ssv6006c/ssv6006C_reg.h	15435;"	d
+SET_RG_STF_SCALE_40	smac/hal/ssv6006c/ssv6006C_reg.h	15436;"	d
+SET_RG_SUB_DC	smac/hal/ssv6006c/ssv6006C_reg.h	14489;"	d
+SET_RG_SW_FALL_TIME	include/ssv6200_reg.h	7676;"	d
+SET_RG_SW_RISE_TIME	include/ssv6200_reg.h	7672;"	d
+SET_RG_SX5GB_AAC_ACCUMH	smac/hal/ssv6006c/ssv6006C_reg.h	14293;"	d
+SET_RG_SX5GB_AAC_ACCUML	smac/hal/ssv6006c/ssv6006C_reg.h	14294;"	d
+SET_RG_SX5GB_AAC_EN	smac/hal/ssv6006c/ssv6006C_reg.h	14298;"	d
+SET_RG_SX5GB_AAC_EN_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	14297;"	d
+SET_RG_SX5GB_AAC_EVA	smac/hal/ssv6006c/ssv6006C_reg.h	14300;"	d
+SET_RG_SX5GB_AAC_EVA_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	14299;"	d
+SET_RG_SX5GB_AAC_EVA_TS	smac/hal/ssv6006c/ssv6006C_reg.h	14296;"	d
+SET_RG_SX5GB_AAC_INIT	smac/hal/ssv6006c/ssv6006C_reg.h	14295;"	d
+SET_RG_SX5GB_AAC_TEST_EN	smac/hal/ssv6006c/ssv6006C_reg.h	14306;"	d
+SET_RG_SX5GB_AAC_TEST_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	14307;"	d
+SET_RG_SX5GB_CAL_INIT	smac/hal/ssv6006c/ssv6006C_reg.h	14201;"	d
+SET_RG_SX5GB_CHANNEL	smac/hal/ssv6006c/ssv6006C_reg.h	14171;"	d
+SET_RG_SX5GB_CP_IOST	smac/hal/ssv6006c/ssv6006C_reg.h	14229;"	d
+SET_RG_SX5GB_CP_IOST_POL	smac/hal/ssv6006c/ssv6006C_reg.h	14228;"	d
+SET_RG_SX5GB_CP_ISEL	smac/hal/ssv6006c/ssv6006C_reg.h	14225;"	d
+SET_RG_SX5GB_CP_ISEL50U	smac/hal/ssv6006c/ssv6006C_reg.h	14226;"	d
+SET_RG_SX5GB_CP_KP_DOUB	smac/hal/ssv6006c/ssv6006C_reg.h	14227;"	d
+SET_RG_SX5GB_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	14398;"	d
+SET_RG_SX5GB_DITHER_WEIGHT	smac/hal/ssv6006c/ssv6006C_reg.h	14278;"	d
+SET_RG_SX5GB_DIV_DMYBUF_EN	smac/hal/ssv6006c/ssv6006C_reg.h	14274;"	d
+SET_RG_SX5GB_DIV_PREVDD	smac/hal/ssv6006c/ssv6006C_reg.h	14270;"	d
+SET_RG_SX5GB_DIV_PSCVDD	smac/hal/ssv6006c/ssv6006C_reg.h	14271;"	d
+SET_RG_SX5GB_DIV_RST_H	smac/hal/ssv6006c/ssv6006C_reg.h	14272;"	d
+SET_RG_SX5GB_DIV_SDM_EDGE	smac/hal/ssv6006c/ssv6006C_reg.h	14273;"	d
+SET_RG_SX5GB_LDO_CP_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	14053;"	d
+SET_RG_SX5GB_LDO_DIV_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	14058;"	d
+SET_RG_SX5GB_LDO_FCOFFT	smac/hal/ssv6006c/ssv6006C_reg.h	14215;"	d
+SET_RG_SX5GB_LDO_LO_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	14055;"	d
+SET_RG_SX5GB_LDO_VCO_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	14057;"	d
+SET_RG_SX5GB_LO_TIMES	smac/hal/ssv6006c/ssv6006C_reg.h	14170;"	d
+SET_RG_SX5GB_LPF_C1	smac/hal/ssv6006c/ssv6006C_reg.h	14239;"	d
+SET_RG_SX5GB_LPF_C2	smac/hal/ssv6006c/ssv6006C_reg.h	14240;"	d
+SET_RG_SX5GB_LPF_C3	smac/hal/ssv6006c/ssv6006C_reg.h	14241;"	d
+SET_RG_SX5GB_LPF_R2	smac/hal/ssv6006c/ssv6006C_reg.h	14242;"	d
+SET_RG_SX5GB_LPF_R3	smac/hal/ssv6006c/ssv6006C_reg.h	14243;"	d
+SET_RG_SX5GB_LPF_VTUNE_TEST	smac/hal/ssv6006c/ssv6006C_reg.h	14252;"	d
+SET_RG_SX5GB_MIXAAC_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	14198;"	d
+SET_RG_SX5GB_MIXAAC_TAR	smac/hal/ssv6006c/ssv6006C_reg.h	14308;"	d
+SET_RG_SX5GB_MOD_ORDER	smac/hal/ssv6006c/ssv6006C_reg.h	14277;"	d
+SET_RG_SX5GB_PFD_DIV_EDGE	smac/hal/ssv6006c/ssv6006C_reg.h	14238;"	d
+SET_RG_SX5GB_PFD_REF_EDGE	smac/hal/ssv6006c/ssv6006C_reg.h	14237;"	d
+SET_RG_SX5GB_PFD_RST	smac/hal/ssv6006c/ssv6006C_reg.h	14181;"	d
+SET_RG_SX5GB_PFD_RST_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	14180;"	d
+SET_RG_SX5GB_PFD_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	14230;"	d
+SET_RG_SX5GB_PFD_SET	smac/hal/ssv6006c/ssv6006C_reg.h	14231;"	d
+SET_RG_SX5GB_PFD_SET1	smac/hal/ssv6006c/ssv6006C_reg.h	14232;"	d
+SET_RG_SX5GB_PFD_SET2	smac/hal/ssv6006c/ssv6006C_reg.h	14233;"	d
+SET_RG_SX5GB_PFD_TLSEL	smac/hal/ssv6006c/ssv6006C_reg.h	14236;"	d
+SET_RG_SX5GB_PFD_TRDN	smac/hal/ssv6006c/ssv6006C_reg.h	14235;"	d
+SET_RG_SX5GB_PFD_TRUP	smac/hal/ssv6006c/ssv6006C_reg.h	14234;"	d
+SET_RG_SX5GB_REPAAC_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	14199;"	d
+SET_RG_SX5GB_REPAAC_TAR	smac/hal/ssv6006c/ssv6006C_reg.h	14311;"	d
+SET_RG_SX5GB_RFCH_MAP_EN	smac/hal/ssv6006c/ssv6006C_reg.h	14169;"	d
+SET_RG_SX5GB_RFCTRL_CH_10_8	smac/hal/ssv6006c/ssv6006C_reg.h	14168;"	d
+SET_RG_SX5GB_RFCTRL_CH_7_0	smac/hal/ssv6006c/ssv6006C_reg.h	14167;"	d
+SET_RG_SX5GB_RFCTRL_F	smac/hal/ssv6006c/ssv6006C_reg.h	14166;"	d
+SET_RG_SX5GB_SBCAL_2ND_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	14195;"	d
+SET_RG_SX5GB_SBCAL_AW	smac/hal/ssv6006c/ssv6006C_reg.h	14196;"	d
+SET_RG_SX5GB_SBCAL_CT	smac/hal/ssv6006c/ssv6006C_reg.h	14285;"	d
+SET_RG_SX5GB_SBCAL_DIFFMIN	smac/hal/ssv6006c/ssv6006C_reg.h	14287;"	d
+SET_RG_SX5GB_SBCAL_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	14194;"	d
+SET_RG_SX5GB_SBCAL_NTARG	smac/hal/ssv6006c/ssv6006C_reg.h	14289;"	d
+SET_RG_SX5GB_SBCAL_NTARG_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	14288;"	d
+SET_RG_SX5GB_SBCAL_WT	smac/hal/ssv6006c/ssv6006C_reg.h	14286;"	d
+SET_RG_SX5GB_SUB_C0P5_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	14284;"	d
+SET_RG_SX5GB_SUB_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	14283;"	d
+SET_RG_SX5GB_SUB_SEL_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	14282;"	d
+SET_RG_SX5GB_TTL_ACCUM	smac/hal/ssv6006c/ssv6006C_reg.h	14247;"	d
+SET_RG_SX5GB_TTL_CPT	smac/hal/ssv6006c/ssv6006C_reg.h	14246;"	d
+SET_RG_SX5GB_TTL_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	14200;"	d
+SET_RG_SX5GB_TTL_FPT	smac/hal/ssv6006c/ssv6006C_reg.h	14245;"	d
+SET_RG_SX5GB_TTL_INIT	smac/hal/ssv6006c/ssv6006C_reg.h	14244;"	d
+SET_RG_SX5GB_TTL_SUB	smac/hal/ssv6006c/ssv6006C_reg.h	14248;"	d
+SET_RG_SX5GB_TTL_SUB_INV	smac/hal/ssv6006c/ssv6006C_reg.h	14249;"	d
+SET_RG_SX5GB_TTL_VH	smac/hal/ssv6006c/ssv6006C_reg.h	14250;"	d
+SET_RG_SX5GB_TTL_VL	smac/hal/ssv6006c/ssv6006C_reg.h	14251;"	d
+SET_RG_SX5GB_UOP_EN	smac/hal/ssv6006c/ssv6006C_reg.h	14183;"	d
+SET_RG_SX5GB_UOP_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	14182;"	d
+SET_RG_SX5GB_VCO_CS_AWH	smac/hal/ssv6006c/ssv6006C_reg.h	14259;"	d
+SET_RG_SX5GB_VCO_ISEL	smac/hal/ssv6006c/ssv6006C_reg.h	14254;"	d
+SET_RG_SX5GB_VCO_ISEL_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	14253;"	d
+SET_RG_SX5GB_VCO_KVDOUB	smac/hal/ssv6006c/ssv6006C_reg.h	14256;"	d
+SET_RG_SX5GB_VCO_RTAIL_SHIFT	smac/hal/ssv6006c/ssv6006C_reg.h	14258;"	d
+SET_RG_SX5GB_VCO_VARBSEL	smac/hal/ssv6006c/ssv6006C_reg.h	14257;"	d
+SET_RG_SX5GB_VCO_VCCBSEL	smac/hal/ssv6006c/ssv6006C_reg.h	14255;"	d
+SET_RG_SX5GB_VOAAC_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	14197;"	d
+SET_RG_SX5GB_VOAAC_TAR	smac/hal/ssv6006c/ssv6006C_reg.h	14290;"	d
+SET_RG_SXMIX_GMBIAS_OP1	smac/hal/ssv6006c/ssv6006C_reg.h	14280;"	d
+SET_RG_SXMIX_GMSEL	smac/hal/ssv6006c/ssv6006C_reg.h	14266;"	d
+SET_RG_SXMIX_IBIAS_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	14264;"	d
+SET_RG_SXMIX_INBF_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	14279;"	d
+SET_RG_SXMIX_SCA_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	14310;"	d
+SET_RG_SXMIX_SCA_SEL_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	14309;"	d
+SET_RG_SXMIX_SWBIAS_OP1	smac/hal/ssv6006c/ssv6006C_reg.h	14281;"	d
+SET_RG_SXMIX_SWB_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	14265;"	d
+SET_RG_SXREP_CSSEL	smac/hal/ssv6006c/ssv6006C_reg.h	14268;"	d
+SET_RG_SXREP_SCA_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	14313;"	d
+SET_RG_SXREP_SCA_SEL_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	14312;"	d
+SET_RG_SXREP_SWB_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	14267;"	d
+SET_RG_SX_5GB_EN	smac/hal/ssv6006c/ssv6006C_reg.h	14173;"	d
+SET_RG_SX_5GB_EN_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	14172;"	d
+SET_RG_SX_AAC_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	13692;"	d
+SET_RG_SX_BTRX_SIDE	smac/hal/ssv6006c/ssv6006C_reg.h	13722;"	d
+SET_RG_SX_CAL_INIT	smac/hal/ssv6006c/ssv6006C_reg.h	13694;"	d
+SET_RG_SX_CHANNEL	smac/hal/ssv6006c/ssv6006C_reg.h	13724;"	d
+SET_RG_SX_CHP_IOST	include/ssv6200_reg.h	8312;"	d
+SET_RG_SX_CHP_IOST_POL	include/ssv6200_reg.h	8311;"	d
+SET_RG_SX_CP_IOST	smac/hal/ssv6006c/ssv6006C_reg.h	13733;"	d
+SET_RG_SX_CP_IOST_POL	smac/hal/ssv6006c/ssv6006C_reg.h	13732;"	d
+SET_RG_SX_CP_ISEL50U_BT	smac/hal/ssv6006c/ssv6006C_reg.h	13727;"	d
+SET_RG_SX_CP_ISEL50U_WF	smac/hal/ssv6006c/ssv6006C_reg.h	13730;"	d
+SET_RG_SX_CP_ISEL_BT	smac/hal/ssv6006c/ssv6006C_reg.h	13726;"	d
+SET_RG_SX_CP_ISEL_WF	smac/hal/ssv6006c/ssv6006C_reg.h	13729;"	d
+SET_RG_SX_CP_KP_DOUB_BT	smac/hal/ssv6006c/ssv6006C_reg.h	13728;"	d
+SET_RG_SX_CP_KP_DOUB_WF	smac/hal/ssv6006c/ssv6006C_reg.h	13731;"	d
+SET_RG_SX_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	13969;"	d
+SET_RG_SX_DITHER_WEIGHT	include/ssv6200_reg.h	8330;"	d
+SET_RG_SX_DITHER_WEIGHT	smac/hal/ssv6006c/ssv6006C_reg.h	13787;"	d
+SET_RG_SX_DIVBFSEL	include/ssv6200_reg.h	8328;"	d
+SET_RG_SX_DIV_DMYBUF_EN	smac/hal/ssv6006c/ssv6006C_reg.h	13783;"	d
+SET_RG_SX_DIV_PREVDD	smac/hal/ssv6006c/ssv6006C_reg.h	13779;"	d
+SET_RG_SX_DIV_PSCVDD	smac/hal/ssv6006c/ssv6006C_reg.h	13780;"	d
+SET_RG_SX_DIV_RST_H	smac/hal/ssv6006c/ssv6006C_reg.h	13781;"	d
+SET_RG_SX_DIV_SDM_EDGE	smac/hal/ssv6006c/ssv6006C_reg.h	13782;"	d
+SET_RG_SX_DUMMMY	include/ssv6200_reg.h	8413;"	d
+SET_RG_SX_EN	smac/hal/ssv6006c/ssv6006C_reg.h	13669;"	d
+SET_RG_SX_EN_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	13668;"	d
+SET_RG_SX_FREF_DOUB	smac/hal/ssv6006c/ssv6006C_reg.h	13721;"	d
+SET_RG_SX_FREF_DOUB_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	13720;"	d
+SET_RG_SX_GNDR_SEL	include/ssv6200_reg.h	8329;"	d
+SET_RG_SX_LCKEN	include/ssv6200_reg.h	8336;"	d
+SET_RG_SX_LCK_BIN_OFFSET	include/ssv6200_reg.h	8405;"	d
+SET_RG_SX_LCK_BIN_PRECISION	include/ssv6200_reg.h	8406;"	d
+SET_RG_SX_LDO_CHP_LEVEL	include/ssv6200_reg.h	8163;"	d
+SET_RG_SX_LDO_CP_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	13441;"	d
+SET_RG_SX_LDO_DIV_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	13446;"	d
+SET_RG_SX_LDO_FCOFFT	smac/hal/ssv6006c/ssv6006C_reg.h	13706;"	d
+SET_RG_SX_LDO_LOBF_LEVEL	include/ssv6200_reg.h	8164;"	d
+SET_RG_SX_LDO_LO_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	13443;"	d
+SET_RG_SX_LDO_VCO_LEVEL	include/ssv6200_reg.h	8167;"	d
+SET_RG_SX_LDO_VCO_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	13445;"	d
+SET_RG_SX_LDO_XOSC_LEVEL	include/ssv6200_reg.h	8165;"	d
+SET_RG_SX_LOCK_EN_N	include/ssv6200_reg.h	8407;"	d
+SET_RG_SX_LOCK_MANUAL	include/ssv6200_reg.h	8408;"	d
+SET_RG_SX_LO_TIMES	smac/hal/ssv6006c/ssv6006C_reg.h	13723;"	d
+SET_RG_SX_LPF_C1_BT	smac/hal/ssv6006c/ssv6006C_reg.h	13743;"	d
+SET_RG_SX_LPF_C1_WF	smac/hal/ssv6006c/ssv6006C_reg.h	13748;"	d
+SET_RG_SX_LPF_C2_BT	smac/hal/ssv6006c/ssv6006C_reg.h	13744;"	d
+SET_RG_SX_LPF_C2_WF	smac/hal/ssv6006c/ssv6006C_reg.h	13749;"	d
+SET_RG_SX_LPF_C3_BT	smac/hal/ssv6006c/ssv6006C_reg.h	13745;"	d
+SET_RG_SX_LPF_C3_WF	smac/hal/ssv6006c/ssv6006C_reg.h	13750;"	d
+SET_RG_SX_LPF_R2_BT	smac/hal/ssv6006c/ssv6006C_reg.h	13746;"	d
+SET_RG_SX_LPF_R2_WF	smac/hal/ssv6006c/ssv6006C_reg.h	13751;"	d
+SET_RG_SX_LPF_R3_BT	smac/hal/ssv6006c/ssv6006C_reg.h	13747;"	d
+SET_RG_SX_LPF_R3_WF	smac/hal/ssv6006c/ssv6006C_reg.h	13752;"	d
+SET_RG_SX_LPF_VTUNE_TEST	smac/hal/ssv6006c/ssv6006C_reg.h	13817;"	d
+SET_RG_SX_MOD_ORDER	include/ssv6200_reg.h	8331;"	d
+SET_RG_SX_MOD_ORDER	smac/hal/ssv6006c/ssv6006C_reg.h	13786;"	d
+SET_RG_SX_MUX_SEL_VTH_BINL	include/ssv6200_reg.h	8411;"	d
+SET_RG_SX_PFDSEL	include/ssv6200_reg.h	8313;"	d
+SET_RG_SX_PFD_DIV_EDGE	smac/hal/ssv6006c/ssv6006C_reg.h	13739;"	d
+SET_RG_SX_PFD_REF_EDGE	smac/hal/ssv6006c/ssv6006C_reg.h	13738;"	d
+SET_RG_SX_PFD_RST	smac/hal/ssv6006c/ssv6006C_reg.h	13677;"	d
+SET_RG_SX_PFD_RST_H	include/ssv6200_reg.h	8318;"	d
+SET_RG_SX_PFD_RST_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	13676;"	d
+SET_RG_SX_PFD_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	13734;"	d
+SET_RG_SX_PFD_SET	include/ssv6200_reg.h	8314;"	d
+SET_RG_SX_PFD_SET	smac/hal/ssv6006c/ssv6006C_reg.h	13735;"	d
+SET_RG_SX_PFD_SET1	include/ssv6200_reg.h	8315;"	d
+SET_RG_SX_PFD_SET1	smac/hal/ssv6006c/ssv6006C_reg.h	13736;"	d
+SET_RG_SX_PFD_SET2	include/ssv6200_reg.h	8316;"	d
+SET_RG_SX_PFD_SET2	smac/hal/ssv6006c/ssv6006C_reg.h	13737;"	d
+SET_RG_SX_PFD_TLSEL	smac/hal/ssv6006c/ssv6006C_reg.h	13742;"	d
+SET_RG_SX_PFD_TRDN	include/ssv6200_reg.h	8320;"	d
+SET_RG_SX_PFD_TRDN	smac/hal/ssv6006c/ssv6006C_reg.h	13741;"	d
+SET_RG_SX_PFD_TRSEL	include/ssv6200_reg.h	8321;"	d
+SET_RG_SX_PFD_TRUP	include/ssv6200_reg.h	8319;"	d
+SET_RG_SX_PFD_TRUP	smac/hal/ssv6006c/ssv6006C_reg.h	13740;"	d
+SET_RG_SX_PH	include/ssv6200_reg.h	8339;"	d
+SET_RG_SX_PL	include/ssv6200_reg.h	8340;"	d
+SET_RG_SX_PREVDD	include/ssv6200_reg.h	8337;"	d
+SET_RG_SX_PSCONTERVDD	include/ssv6200_reg.h	8338;"	d
+SET_RG_SX_REFBYTWO	include/ssv6200_reg.h	8335;"	d
+SET_RG_SX_RFCH_MAP_EN	smac/hal/ssv6006c/ssv6006C_reg.h	13719;"	d
+SET_RG_SX_RFCTRL_CH	include/ssv6200_reg.h	8303;"	d
+SET_RG_SX_RFCTRL_CH_10_8	smac/hal/ssv6006c/ssv6006C_reg.h	13718;"	d
+SET_RG_SX_RFCTRL_CH_7_0	smac/hal/ssv6006c/ssv6006C_reg.h	13717;"	d
+SET_RG_SX_RFCTRL_F	include/ssv6200_reg.h	8300;"	d
+SET_RG_SX_RFCTRL_F	smac/hal/ssv6006c/ssv6006C_reg.h	13716;"	d
+SET_RG_SX_RST_H_DIV	include/ssv6200_reg.h	8332;"	d
+SET_RG_SX_RXBFSEL	include/ssv6200_reg.h	8325;"	d
+SET_RG_SX_SBCAL_AW	smac/hal/ssv6006c/ssv6006C_reg.h	13691;"	d
+SET_RG_SX_SBCAL_CT	smac/hal/ssv6006c/ssv6006C_reg.h	13791;"	d
+SET_RG_SX_SBCAL_DIFFMIN	smac/hal/ssv6006c/ssv6006C_reg.h	13793;"	d
+SET_RG_SX_SBCAL_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	13690;"	d
+SET_RG_SX_SBCAL_NTARG	smac/hal/ssv6006c/ssv6006C_reg.h	13795;"	d
+SET_RG_SX_SBCAL_NTARG_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	13794;"	d
+SET_RG_SX_SBCAL_WT	smac/hal/ssv6006c/ssv6006C_reg.h	13792;"	d
+SET_RG_SX_SDM_EDGE	include/ssv6200_reg.h	8333;"	d
+SET_RG_SX_SEL_C3	include/ssv6200_reg.h	8304;"	d
+SET_RG_SX_SEL_CHP_REGOP	include/ssv6200_reg.h	8309;"	d
+SET_RG_SX_SEL_CHP_UNIOP	include/ssv6200_reg.h	8310;"	d
+SET_RG_SX_SEL_CP	include/ssv6200_reg.h	8301;"	d
+SET_RG_SX_SEL_CS	include/ssv6200_reg.h	8302;"	d
+SET_RG_SX_SEL_ICHP	include/ssv6200_reg.h	8307;"	d
+SET_RG_SX_SEL_PCHP	include/ssv6200_reg.h	8308;"	d
+SET_RG_SX_SEL_R3	include/ssv6200_reg.h	8306;"	d
+SET_RG_SX_SEL_RS	include/ssv6200_reg.h	8305;"	d
+SET_RG_SX_SUB_C0P5_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	13790;"	d
+SET_RG_SX_SUB_MANUAL	include/ssv6200_reg.h	8409;"	d
+SET_RG_SX_SUB_SEL	include/ssv6200_reg.h	8410;"	d
+SET_RG_SX_SUB_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	13789;"	d
+SET_RG_SX_SUB_SEL_CWD	include/ssv6200_reg.h	8404;"	d
+SET_RG_SX_SUB_SEL_CWR	include/ssv6200_reg.h	8403;"	d
+SET_RG_SX_SUB_SEL_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	13788;"	d
+SET_RG_SX_TARGET_CNT	include/ssv6200_reg.h	8431;"	d
+SET_RG_SX_TTL_ACCUM	smac/hal/ssv6006c/ssv6006C_reg.h	13812;"	d
+SET_RG_SX_TTL_CPT	smac/hal/ssv6006c/ssv6006C_reg.h	13811;"	d
+SET_RG_SX_TTL_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	13693;"	d
+SET_RG_SX_TTL_FPT	smac/hal/ssv6006c/ssv6006C_reg.h	13810;"	d
+SET_RG_SX_TTL_INIT	smac/hal/ssv6006c/ssv6006C_reg.h	13809;"	d
+SET_RG_SX_TTL_SUB	smac/hal/ssv6006c/ssv6006C_reg.h	13813;"	d
+SET_RG_SX_TTL_SUB_INV	smac/hal/ssv6006c/ssv6006C_reg.h	13814;"	d
+SET_RG_SX_TTL_VH	smac/hal/ssv6006c/ssv6006C_reg.h	13815;"	d
+SET_RG_SX_TTL_VL	smac/hal/ssv6006c/ssv6006C_reg.h	13816;"	d
+SET_RG_SX_TXBFSEL	include/ssv6200_reg.h	8326;"	d
+SET_RG_SX_UOP_EN	smac/hal/ssv6006c/ssv6006C_reg.h	13679;"	d
+SET_RG_SX_UOP_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	13678;"	d
+SET_RG_SX_VBNCAS_SEL	include/ssv6200_reg.h	8317;"	d
+SET_RG_SX_VCOBA_R	include/ssv6200_reg.h	8322;"	d
+SET_RG_SX_VCOBFSEL	include/ssv6200_reg.h	8327;"	d
+SET_RG_SX_VCOCUSEL	include/ssv6200_reg.h	8324;"	d
+SET_RG_SX_VCORSEL	include/ssv6200_reg.h	8323;"	d
+SET_RG_SX_VCO_CS_AWH	smac/hal/ssv6006c/ssv6006C_reg.h	13764;"	d
+SET_RG_SX_VCO_ISEL_BT	smac/hal/ssv6006c/ssv6006C_reg.h	13754;"	d
+SET_RG_SX_VCO_ISEL_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	13753;"	d
+SET_RG_SX_VCO_ISEL_WF	smac/hal/ssv6006c/ssv6006C_reg.h	13758;"	d
+SET_RG_SX_VCO_KVDOUB_BT	smac/hal/ssv6006c/ssv6006C_reg.h	13757;"	d
+SET_RG_SX_VCO_KVDOUB_WF	smac/hal/ssv6006c/ssv6006C_reg.h	13761;"	d
+SET_RG_SX_VCO_LPM_BT	smac/hal/ssv6006c/ssv6006C_reg.h	13755;"	d
+SET_RG_SX_VCO_LPM_WF	smac/hal/ssv6006c/ssv6006C_reg.h	13759;"	d
+SET_RG_SX_VCO_RTAIL_SHIFT	smac/hal/ssv6006c/ssv6006C_reg.h	13763;"	d
+SET_RG_SX_VCO_RXOB_AW	smac/hal/ssv6006c/ssv6006C_reg.h	13775;"	d
+SET_RG_SX_VCO_TXOB_AW	smac/hal/ssv6006c/ssv6006C_reg.h	13774;"	d
+SET_RG_SX_VCO_VARBSEL	smac/hal/ssv6006c/ssv6006C_reg.h	13762;"	d
+SET_RG_SX_VCO_VCCBSEL_BT	smac/hal/ssv6006c/ssv6006C_reg.h	13756;"	d
+SET_RG_SX_VCO_VCCBSEL_WF	smac/hal/ssv6006c/ssv6006C_reg.h	13760;"	d
+SET_RG_SX_VT_MON_MODE	include/ssv6200_reg.h	8343;"	d
+SET_RG_SX_VT_MON_TMR	include/ssv6200_reg.h	8347;"	d
+SET_RG_SX_VT_SET	include/ssv6200_reg.h	8346;"	d
+SET_RG_SX_VT_TH_HI	include/ssv6200_reg.h	8344;"	d
+SET_RG_SX_VT_TH_LO	include/ssv6200_reg.h	8345;"	d
+SET_RG_SX_XO_GM	include/ssv6200_reg.h	8334;"	d
+SET_RG_SX_XTAL_FREQ	smac/hal/ssv6006c/ssv6006C_reg.h	13725;"	d
+SET_RG_SYM_BOUND_CNT	include/ssv6200_reg.h	7863;"	d
+SET_RG_SYM_BOUND_METHOD	include/ssv6200_reg.h	7892;"	d
+SET_RG_SYM_BOUND_METHOD	smac/hal/ssv6006c/ssv6006C_reg.h	15485;"	d
+SET_RG_SYSTEM_BW	smac/hal/ssv6006c/ssv6006C_reg.h	15098;"	d
+SET_RG_TBUS_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	15210;"	d
+SET_RG_TC_BIT_CNT_LMT	include/ssv6200_reg.h	7810;"	d
+SET_RG_TC_BIT_CNT_LMT	smac/hal/ssv6006c/ssv6006C_reg.h	15386;"	d
+SET_RG_THH_ED	smac/hal/ssv6006c/ssv6006C_reg.h	15600;"	d
+SET_RG_THH_RATIO	smac/hal/ssv6006c/ssv6006C_reg.h	15602;"	d
+SET_RG_THL_ED	smac/hal/ssv6006c/ssv6006C_reg.h	15599;"	d
+SET_RG_THL_RATIO	smac/hal/ssv6006c/ssv6006C_reg.h	15601;"	d
+SET_RG_TIME_PERIOD	smac/hal/ssv6006c/ssv6006C_reg.h	15607;"	d
+SET_RG_TOLERANCE_PERIOD	smac/hal/ssv6006c/ssv6006C_reg.h	15612;"	d
+SET_RG_TOLERANCE_PW	smac/hal/ssv6006c/ssv6006C_reg.h	15613;"	d
+SET_RG_TONEGEN2_EN	include/ssv6200_reg.h	7986;"	d
+SET_RG_TONEGEN2_FREQ	include/ssv6200_reg.h	7985;"	d
+SET_RG_TONEGEN2_SCALE	include/ssv6200_reg.h	7987;"	d
+SET_RG_TONEGEN_EN	include/ssv6200_reg.h	7983;"	d
+SET_RG_TONEGEN_FREQ	include/ssv6200_reg.h	7982;"	d
+SET_RG_TONEGEN_INIT_PH	include/ssv6200_reg.h	7984;"	d
+SET_RG_TONE_1_RATE	smac/hal/ssv6006c/ssv6006C_reg.h	14832;"	d
+SET_RG_TONE_GEN_EN	smac/hal/ssv6006c/ssv6006C_reg.h	14504;"	d
+SET_RG_TONE_SCALE	smac/hal/ssv6006c/ssv6006C_reg.h	14502;"	d
+SET_RG_TONE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	14831;"	d
+SET_RG_TRX_DUMMMY	include/ssv6200_reg.h	8412;"	d
+SET_RG_TR_BIT_CNT_LMT	include/ssv6200_reg.h	7812;"	d
+SET_RG_TR_BIT_CNT_LMT	smac/hal/ssv6006c/ssv6006C_reg.h	15388;"	d
+SET_RG_TR_CNT_T0	include/ssv6200_reg.h	7855;"	d
+SET_RG_TR_CNT_T1	include/ssv6200_reg.h	7852;"	d
+SET_RG_TR_CNT_T2	include/ssv6200_reg.h	7858;"	d
+SET_RG_TR_CNT_UPDATE	include/ssv6200_reg.h	7906;"	d
+SET_RG_TR_CNT_UPDATE	smac/hal/ssv6006c/ssv6006C_reg.h	15545;"	d
+SET_RG_TR_CNT_UPDATE_SGI	smac/hal/ssv6006c/ssv6006C_reg.h	15543;"	d
+SET_RG_TR_KI_T1	include/ssv6200_reg.h	7778;"	d
+SET_RG_TR_KI_T1	smac/hal/ssv6006c/ssv6006C_reg.h	15360;"	d
+SET_RG_TR_KI_T2	include/ssv6200_reg.h	7776;"	d
+SET_RG_TR_KI_T2	smac/hal/ssv6006c/ssv6006C_reg.h	15358;"	d
+SET_RG_TR_KP_T1	include/ssv6200_reg.h	7779;"	d
+SET_RG_TR_KP_T1	smac/hal/ssv6006c/ssv6006C_reg.h	15361;"	d
+SET_RG_TR_KP_T2	include/ssv6200_reg.h	7777;"	d
+SET_RG_TR_KP_T2	smac/hal/ssv6006c/ssv6006C_reg.h	15359;"	d
+SET_RG_TR_LPF_KI_G	include/ssv6200_reg.h	7859;"	d
+SET_RG_TR_LPF_KI_G_T0	include/ssv6200_reg.h	7853;"	d
+SET_RG_TR_LPF_KI_G_T1	include/ssv6200_reg.h	7850;"	d
+SET_RG_TR_LPF_KI_G_T2	include/ssv6200_reg.h	7856;"	d
+SET_RG_TR_LPF_KP_G	include/ssv6200_reg.h	7860;"	d
+SET_RG_TR_LPF_KP_G_T0	include/ssv6200_reg.h	7854;"	d
+SET_RG_TR_LPF_KP_G_T1	include/ssv6200_reg.h	7851;"	d
+SET_RG_TR_LPF_KP_G_T2	include/ssv6200_reg.h	7857;"	d
+SET_RG_TR_LPF_RATE	include/ssv6200_reg.h	7807;"	d
+SET_RG_TR_LPF_RATE	smac/hal/ssv6006c/ssv6006C_reg.h	15383;"	d
+SET_RG_TR_LPF_RATE_G	include/ssv6200_reg.h	7861;"	d
+SET_RG_TR_LPF_RATE_GN	smac/hal/ssv6006c/ssv6006C_reg.h	15454;"	d
+SET_RG_TR_LPF_STBC_GF_KI_G	include/ssv6200_reg.h	7922;"	d
+SET_RG_TR_LPF_STBC_GF_KP_G	include/ssv6200_reg.h	7923;"	d
+SET_RG_TR_LPF_STBC_MF_KI_G	include/ssv6200_reg.h	7924;"	d
+SET_RG_TR_LPF_STBC_MF_KP_G	include/ssv6200_reg.h	7925;"	d
+SET_RG_TST_ADC_ON	include/ssv6200_reg.h	7659;"	d
+SET_RG_TST_EXT_GAIN	include/ssv6200_reg.h	7660;"	d
+SET_RG_TST_TBUS_SEL	include/ssv6200_reg.h	7656;"	d
+SET_RG_TURISMO_TRX_40M_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	13079;"	d
+SET_RG_TURISMO_TRX_5G_EN_IREF_RX	smac/hal/ssv6006c/ssv6006C_reg.h	12691;"	d
+SET_RG_TURISMO_TRX_5G_EN_LDO_RX_FE	smac/hal/ssv6006c/ssv6006C_reg.h	12690;"	d
+SET_RG_TURISMO_TRX_5G_EN_LDO_RX_FE_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	12682;"	d
+SET_RG_TURISMO_TRX_5G_EN_LDO_RX_FE_FC	smac/hal/ssv6006c/ssv6006C_reg.h	12692;"	d
+SET_RG_TURISMO_TRX_5G_EN_LDO_RX_FE_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	12693;"	d
+SET_RG_TURISMO_TRX_5G_EN_RX_DIV2	smac/hal/ssv6006c/ssv6006C_reg.h	12659;"	d
+SET_RG_TURISMO_TRX_5G_EN_RX_IQCAL	smac/hal/ssv6006c/ssv6006C_reg.h	12677;"	d
+SET_RG_TURISMO_TRX_5G_EN_RX_LNA	smac/hal/ssv6006c/ssv6006C_reg.h	12655;"	d
+SET_RG_TURISMO_TRX_5G_EN_RX_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	12661;"	d
+SET_RG_TURISMO_TRX_5G_EN_RX_MIXER	smac/hal/ssv6006c/ssv6006C_reg.h	12657;"	d
+SET_RG_TURISMO_TRX_5G_EN_RX_TZ	smac/hal/ssv6006c/ssv6006C_reg.h	12663;"	d
+SET_RG_TURISMO_TRX_5G_EN_TX_DIV2	smac/hal/ssv6006c/ssv6006C_reg.h	12669;"	d
+SET_RG_TURISMO_TRX_5G_EN_TX_DIV2_BUF	smac/hal/ssv6006c/ssv6006C_reg.h	12671;"	d
+SET_RG_TURISMO_TRX_5G_EN_TX_DPD	smac/hal/ssv6006c/ssv6006C_reg.h	12679;"	d
+SET_RG_TURISMO_TRX_5G_EN_TX_MOD	smac/hal/ssv6006c/ssv6006C_reg.h	12667;"	d
+SET_RG_TURISMO_TRX_5G_EN_TX_PA	smac/hal/ssv6006c/ssv6006C_reg.h	12665;"	d
+SET_RG_TURISMO_TRX_5G_EN_TX_SELF_MIXER	smac/hal/ssv6006c/ssv6006C_reg.h	12675;"	d
+SET_RG_TURISMO_TRX_5G_EN_TX_TRSW	smac/hal/ssv6006c/ssv6006C_reg.h	12653;"	d
+SET_RG_TURISMO_TRX_5G_EN_TX_TSSI	smac/hal/ssv6006c/ssv6006C_reg.h	12680;"	d
+SET_RG_TURISMO_TRX_5G_GM_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	12700;"	d
+SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE0	smac/hal/ssv6006c/ssv6006C_reg.h	13005;"	d
+SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE1	smac/hal/ssv6006c/ssv6006C_reg.h	13003;"	d
+SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE2	smac/hal/ssv6006c/ssv6006C_reg.h	13001;"	d
+SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE3	smac/hal/ssv6006c/ssv6006C_reg.h	12999;"	d
+SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE4	smac/hal/ssv6006c/ssv6006C_reg.h	12997;"	d
+SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	12963;"	d
+SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	12961;"	d
+SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	12943;"	d
+SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	12941;"	d
+SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	12939;"	d
+SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	12937;"	d
+SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	12935;"	d
+SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	12933;"	d
+SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	12959;"	d
+SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	12957;"	d
+SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	12955;"	d
+SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	12953;"	d
+SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	12951;"	d
+SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	12949;"	d
+SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	12947;"	d
+SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	12945;"	d
+SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE0	smac/hal/ssv6006c/ssv6006C_reg.h	13015;"	d
+SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE1	smac/hal/ssv6006c/ssv6006C_reg.h	13013;"	d
+SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE2	smac/hal/ssv6006c/ssv6006C_reg.h	13011;"	d
+SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE3	smac/hal/ssv6006c/ssv6006C_reg.h	13009;"	d
+SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE4	smac/hal/ssv6006c/ssv6006C_reg.h	13007;"	d
+SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	12995;"	d
+SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	12993;"	d
+SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	12975;"	d
+SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	12973;"	d
+SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	12971;"	d
+SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	12969;"	d
+SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	12967;"	d
+SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	12965;"	d
+SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	12991;"	d
+SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	12989;"	d
+SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	12987;"	d
+SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	12985;"	d
+SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	12983;"	d
+SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	12981;"	d
+SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	12979;"	d
+SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	12977;"	d
+SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE0	smac/hal/ssv6006c/ssv6006C_reg.h	13006;"	d
+SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE1	smac/hal/ssv6006c/ssv6006C_reg.h	13004;"	d
+SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE2	smac/hal/ssv6006c/ssv6006C_reg.h	13002;"	d
+SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE3	smac/hal/ssv6006c/ssv6006C_reg.h	13000;"	d
+SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE4	smac/hal/ssv6006c/ssv6006C_reg.h	12998;"	d
+SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	12964;"	d
+SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	12962;"	d
+SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	12944;"	d
+SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	12942;"	d
+SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	12940;"	d
+SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	12938;"	d
+SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	12936;"	d
+SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	12934;"	d
+SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	12960;"	d
+SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	12958;"	d
+SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	12956;"	d
+SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	12954;"	d
+SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	12952;"	d
+SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	12950;"	d
+SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	12948;"	d
+SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	12946;"	d
+SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE0	smac/hal/ssv6006c/ssv6006C_reg.h	13016;"	d
+SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE1	smac/hal/ssv6006c/ssv6006C_reg.h	13014;"	d
+SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE2	smac/hal/ssv6006c/ssv6006C_reg.h	13012;"	d
+SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE3	smac/hal/ssv6006c/ssv6006C_reg.h	13010;"	d
+SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE4	smac/hal/ssv6006c/ssv6006C_reg.h	13008;"	d
+SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	12996;"	d
+SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	12994;"	d
+SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	12976;"	d
+SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	12974;"	d
+SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	12972;"	d
+SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	12970;"	d
+SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	12968;"	d
+SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	12966;"	d
+SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	12992;"	d
+SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	12990;"	d
+SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	12988;"	d
+SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	12986;"	d
+SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	12984;"	d
+SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	12982;"	d
+SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	12980;"	d
+SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	12978;"	d
+SET_RG_TURISMO_TRX_5G_LDO_LEVEL_RX_FE	smac/hal/ssv6006c/ssv6006C_reg.h	12681;"	d
+SET_RG_TURISMO_TRX_5G_PABIAS_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	12719;"	d
+SET_RG_TURISMO_TRX_5G_PACELL_EN	smac/hal/ssv6006c/ssv6006C_reg.h	12718;"	d
+SET_RG_TURISMO_TRX_5G_PGAG_DPDCAL	smac/hal/ssv6006c/ssv6006C_reg.h	13041;"	d
+SET_RG_TURISMO_TRX_5G_PGAG_RCCAL	smac/hal/ssv6006c/ssv6006C_reg.h	13036;"	d
+SET_RG_TURISMO_TRX_5G_PGAG_RXIQCAL	smac/hal/ssv6006c/ssv6006C_reg.h	13038;"	d
+SET_RG_TURISMO_TRX_5G_PGAG_TXCAL	smac/hal/ssv6006c/ssv6006C_reg.h	13034;"	d
+SET_RG_TURISMO_TRX_5G_RFG_DPDCAL	smac/hal/ssv6006c/ssv6006C_reg.h	13040;"	d
+SET_RG_TURISMO_TRX_5G_RFG_RXIQCAL	smac/hal/ssv6006c/ssv6006C_reg.h	13037;"	d
+SET_RG_TURISMO_TRX_5G_RXRF_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	13021;"	d
+SET_RG_TURISMO_TRX_5G_RXRF_R2T_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	13029;"	d
+SET_RG_TURISMO_TRX_5G_RXRF_T2R_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	13025;"	d
+SET_RG_TURISMO_TRX_5G_RX_ADC_CLOAD	smac/hal/ssv6006c/ssv6006C_reg.h	12714;"	d
+SET_RG_TURISMO_TRX_5G_RX_ADC_ICMP	smac/hal/ssv6006c/ssv6006C_reg.h	12712;"	d
+SET_RG_TURISMO_TRX_5G_RX_ADC_VCMI	smac/hal/ssv6006c/ssv6006C_reg.h	12713;"	d
+SET_RG_TURISMO_TRX_5G_RX_DCCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	13030;"	d
+SET_RG_TURISMO_TRX_5G_RX_DIV2_BUF	smac/hal/ssv6006c/ssv6006C_reg.h	12701;"	d
+SET_RG_TURISMO_TRX_5G_RX_DIV2_CML	smac/hal/ssv6006c/ssv6006C_reg.h	12702;"	d
+SET_RG_TURISMO_TRX_5G_RX_DIV2_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	12658;"	d
+SET_RG_TURISMO_TRX_5G_RX_DIV_CMLISEL	smac/hal/ssv6006c/ssv6006C_reg.h	12703;"	d
+SET_RG_TURISMO_TRX_5G_RX_DIV_PREBUFS2	smac/hal/ssv6006c/ssv6006C_reg.h	12704;"	d
+SET_RG_TURISMO_TRX_5G_RX_GM_IDB	smac/hal/ssv6006c/ssv6006C_reg.h	12699;"	d
+SET_RG_TURISMO_TRX_5G_RX_HG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	12741;"	d
+SET_RG_TURISMO_TRX_5G_RX_HG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	12736;"	d
+SET_RG_TURISMO_TRX_5G_RX_HG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	12737;"	d
+SET_RG_TURISMO_TRX_5G_RX_HG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	12738;"	d
+SET_RG_TURISMO_TRX_5G_RX_HG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	12734;"	d
+SET_RG_TURISMO_TRX_5G_RX_HG_SQDC	smac/hal/ssv6006c/ssv6006C_reg.h	12740;"	d
+SET_RG_TURISMO_TRX_5G_RX_HG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	12743;"	d
+SET_RG_TURISMO_TRX_5G_RX_HG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	12739;"	d
+SET_RG_TURISMO_TRX_5G_RX_HG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	12735;"	d
+SET_RG_TURISMO_TRX_5G_RX_HG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	12742;"	d
+SET_RG_TURISMO_TRX_5G_RX_HG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	12744;"	d
+SET_RG_TURISMO_TRX_5G_RX_IQCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	13033;"	d
+SET_RG_TURISMO_TRX_5G_RX_IQCAL_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	12676;"	d
+SET_RG_TURISMO_TRX_5G_RX_LG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	12763;"	d
+SET_RG_TURISMO_TRX_5G_RX_LG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	12758;"	d
+SET_RG_TURISMO_TRX_5G_RX_LG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	12759;"	d
+SET_RG_TURISMO_TRX_5G_RX_LG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	12760;"	d
+SET_RG_TURISMO_TRX_5G_RX_LG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	12756;"	d
+SET_RG_TURISMO_TRX_5G_RX_LG_SQDC	smac/hal/ssv6006c/ssv6006C_reg.h	12762;"	d
+SET_RG_TURISMO_TRX_5G_RX_LG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	12765;"	d
+SET_RG_TURISMO_TRX_5G_RX_LG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	12761;"	d
+SET_RG_TURISMO_TRX_5G_RX_LG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	12757;"	d
+SET_RG_TURISMO_TRX_5G_RX_LG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	12764;"	d
+SET_RG_TURISMO_TRX_5G_RX_LG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	12766;"	d
+SET_RG_TURISMO_TRX_5G_RX_LNA_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	12654;"	d
+SET_RG_TURISMO_TRX_5G_RX_LNA_SETTLE	smac/hal/ssv6006c/ssv6006C_reg.h	12698;"	d
+SET_RG_TURISMO_TRX_5G_RX_LNA_TRI_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	12697;"	d
+SET_RG_TURISMO_TRX_5G_RX_LOBUF_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	12660;"	d
+SET_RG_TURISMO_TRX_5G_RX_MG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	12752;"	d
+SET_RG_TURISMO_TRX_5G_RX_MG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	12747;"	d
+SET_RG_TURISMO_TRX_5G_RX_MG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	12748;"	d
+SET_RG_TURISMO_TRX_5G_RX_MG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	12749;"	d
+SET_RG_TURISMO_TRX_5G_RX_MG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	12745;"	d
+SET_RG_TURISMO_TRX_5G_RX_MG_SQDC	smac/hal/ssv6006c/ssv6006C_reg.h	12751;"	d
+SET_RG_TURISMO_TRX_5G_RX_MG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	12754;"	d
+SET_RG_TURISMO_TRX_5G_RX_MG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	12750;"	d
+SET_RG_TURISMO_TRX_5G_RX_MG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	12746;"	d
+SET_RG_TURISMO_TRX_5G_RX_MG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	12753;"	d
+SET_RG_TURISMO_TRX_5G_RX_MG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	12755;"	d
+SET_RG_TURISMO_TRX_5G_RX_MIXER_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	12656;"	d
+SET_RG_TURISMO_TRX_5G_RX_SCA_LOAD	smac/hal/ssv6006c/ssv6006C_reg.h	12696;"	d
+SET_RG_TURISMO_TRX_5G_RX_SCA_MA	smac/hal/ssv6006c/ssv6006C_reg.h	12695;"	d
+SET_RG_TURISMO_TRX_5G_RX_SCA_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	12694;"	d
+SET_RG_TURISMO_TRX_5G_RX_TZ_COURSE	smac/hal/ssv6006c/ssv6006C_reg.h	12705;"	d
+SET_RG_TURISMO_TRX_5G_RX_TZ_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	12662;"	d
+SET_RG_TURISMO_TRX_5G_RX_TZ_OUT_TRISTATE	smac/hal/ssv6006c/ssv6006C_reg.h	12673;"	d
+SET_RG_TURISMO_TRX_5G_RX_TZ_OUT_TRISTATE_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	12672;"	d
+SET_RG_TURISMO_TRX_5G_RX_ULG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	12774;"	d
+SET_RG_TURISMO_TRX_5G_RX_ULG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	12769;"	d
+SET_RG_TURISMO_TRX_5G_RX_ULG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	12770;"	d
+SET_RG_TURISMO_TRX_5G_RX_ULG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	12771;"	d
+SET_RG_TURISMO_TRX_5G_RX_ULG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	12767;"	d
+SET_RG_TURISMO_TRX_5G_RX_ULG_SQDC	smac/hal/ssv6006c/ssv6006C_reg.h	12773;"	d
+SET_RG_TURISMO_TRX_5G_RX_ULG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	12776;"	d
+SET_RG_TURISMO_TRX_5G_RX_ULG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	12772;"	d
+SET_RG_TURISMO_TRX_5G_RX_ULG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	12768;"	d
+SET_RG_TURISMO_TRX_5G_RX_ULG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	12775;"	d
+SET_RG_TURISMO_TRX_5G_RX_ULG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	12777;"	d
+SET_RG_TURISMO_TRX_5G_TXDAC_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	13018;"	d
+SET_RG_TURISMO_TRX_5G_TXDAC_R2T_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	13026;"	d
+SET_RG_TURISMO_TRX_5G_TXDAC_T2R_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	13022;"	d
+SET_RG_TURISMO_TRX_5G_TXLPF_BOOSTI	smac/hal/ssv6006c/ssv6006C_reg.h	12784;"	d
+SET_RG_TURISMO_TRX_5G_TXMOD_GMCELL	smac/hal/ssv6006c/ssv6006C_reg.h	12731;"	d
+SET_RG_TURISMO_TRX_5G_TXPA_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	13020;"	d
+SET_RG_TURISMO_TRX_5G_TXPA_R2T_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	13028;"	d
+SET_RG_TURISMO_TRX_5G_TXPA_T2R_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	13024;"	d
+SET_RG_TURISMO_TRX_5G_TXPGA_CAPSW	smac/hal/ssv6006c/ssv6006C_reg.h	12716;"	d
+SET_RG_TURISMO_TRX_5G_TXPGA_CAPSW_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	12715;"	d
+SET_RG_TURISMO_TRX_5G_TXPGA_MAIN	smac/hal/ssv6006c/ssv6006C_reg.h	12729;"	d
+SET_RG_TURISMO_TRX_5G_TXPGA_STEER	smac/hal/ssv6006c/ssv6006C_reg.h	12730;"	d
+SET_RG_TURISMO_TRX_5G_TXRF_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	13019;"	d
+SET_RG_TURISMO_TRX_5G_TXRF_R2T_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	13027;"	d
+SET_RG_TURISMO_TRX_5G_TXRF_T2R_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	13023;"	d
+SET_RG_TURISMO_TRX_5G_TX_ADDGMCELL	smac/hal/ssv6006c/ssv6006C_reg.h	12717;"	d
+SET_RG_TURISMO_TRX_5G_TX_DACI1ST	smac/hal/ssv6006c/ssv6006C_reg.h	12778;"	d
+SET_RG_TURISMO_TRX_5G_TX_DACLPF_ICOARSE	smac/hal/ssv6006c/ssv6006C_reg.h	12779;"	d
+SET_RG_TURISMO_TRX_5G_TX_DACLPF_IFINE	smac/hal/ssv6006c/ssv6006C_reg.h	12780;"	d
+SET_RG_TURISMO_TRX_5G_TX_DACLPF_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	12781;"	d
+SET_RG_TURISMO_TRX_5G_TX_DAC_CKEDGE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	12786;"	d
+SET_RG_TURISMO_TRX_5G_TX_DAC_IATTN	smac/hal/ssv6006c/ssv6006C_reg.h	12783;"	d
+SET_RG_TURISMO_TRX_5G_TX_DAC_IBIAS	smac/hal/ssv6006c/ssv6006C_reg.h	12782;"	d
+SET_RG_TURISMO_TRX_5G_TX_DAC_IOFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	12788;"	d
+SET_RG_TURISMO_TRX_5G_TX_DAC_OS	smac/hal/ssv6006c/ssv6006C_reg.h	12787;"	d
+SET_RG_TURISMO_TRX_5G_TX_DAC_QOFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	12789;"	d
+SET_RG_TURISMO_TRX_5G_TX_DAC_RCAL	smac/hal/ssv6006c/ssv6006C_reg.h	12785;"	d
+SET_RG_TURISMO_TRX_5G_TX_DCCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	13031;"	d
+SET_RG_TURISMO_TRX_5G_TX_DIV2_BUF_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	12670;"	d
+SET_RG_TURISMO_TRX_5G_TX_DIV2_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	12668;"	d
+SET_RG_TURISMO_TRX_5G_TX_DIV_CMLISEL	smac/hal/ssv6006c/ssv6006C_reg.h	12725;"	d
+SET_RG_TURISMO_TRX_5G_TX_DIV_CMLVSEL	smac/hal/ssv6006c/ssv6006C_reg.h	12726;"	d
+SET_RG_TURISMO_TRX_5G_TX_DIV_PREBUFS2	smac/hal/ssv6006c/ssv6006C_reg.h	12724;"	d
+SET_RG_TURISMO_TRX_5G_TX_DIV_VSET	smac/hal/ssv6006c/ssv6006C_reg.h	12727;"	d
+SET_RG_TURISMO_TRX_5G_TX_DPDGM_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	12706;"	d
+SET_RG_TURISMO_TRX_5G_TX_DPD_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	12707;"	d
+SET_RG_TURISMO_TRX_5G_TX_DPD_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	12678;"	d
+SET_RG_TURISMO_TRX_5G_TX_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	12733;"	d
+SET_RG_TURISMO_TRX_5G_TX_GAIN_DPDCAL	smac/hal/ssv6006c/ssv6006C_reg.h	13042;"	d
+SET_RG_TURISMO_TRX_5G_TX_GAIN_OFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	12732;"	d
+SET_RG_TURISMO_TRX_5G_TX_GAIN_RXIQCAL	smac/hal/ssv6006c/ssv6006C_reg.h	13039;"	d
+SET_RG_TURISMO_TRX_5G_TX_GAIN_TXCAL	smac/hal/ssv6006c/ssv6006C_reg.h	13035;"	d
+SET_RG_TURISMO_TRX_5G_TX_IQCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	13032;"	d
+SET_RG_TURISMO_TRX_5G_TX_LOBUF_VSET	smac/hal/ssv6006c/ssv6006C_reg.h	12728;"	d
+SET_RG_TURISMO_TRX_5G_TX_MOD_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	12666;"	d
+SET_RG_TURISMO_TRX_5G_TX_PA1_VCAS	smac/hal/ssv6006c/ssv6006C_reg.h	12721;"	d
+SET_RG_TURISMO_TRX_5G_TX_PA2_VCAS	smac/hal/ssv6006c/ssv6006C_reg.h	12722;"	d
+SET_RG_TURISMO_TRX_5G_TX_PA3_VCAS	smac/hal/ssv6006c/ssv6006C_reg.h	12723;"	d
+SET_RG_TURISMO_TRX_5G_TX_PAFB_EN	smac/hal/ssv6006c/ssv6006C_reg.h	12720;"	d
+SET_RG_TURISMO_TRX_5G_TX_PA_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	12664;"	d
+SET_RG_TURISMO_TRX_5G_TX_SELF_MIXER_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	12674;"	d
+SET_RG_TURISMO_TRX_5G_TX_TRSW_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	12652;"	d
+SET_RG_TURISMO_TRX_5G_TX_TSSI_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	12708;"	d
+SET_RG_TURISMO_TRX_5G_TX_TSSI_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	12709;"	d
+SET_RG_TURISMO_TRX_5G_TX_TSSI_TEST	smac/hal/ssv6006c/ssv6006C_reg.h	12710;"	d
+SET_RG_TURISMO_TRX_5G_TX_TSSI_TESTMODE	smac/hal/ssv6006c/ssv6006C_reg.h	12711;"	d
+SET_RG_TURISMO_TRX_AAC5GB_PDSW_EN_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	12921;"	d
+SET_RG_TURISMO_TRX_AAC5GB_TAR_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	12920;"	d
+SET_RG_TURISMO_TRX_ADC_EDGE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	13090;"	d
+SET_RG_TURISMO_TRX_ALPHA_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	13129;"	d
+SET_RG_TURISMO_TRX_BB_SIG_EN	smac/hal/ssv6006c/ssv6006C_reg.h	13102;"	d
+SET_RG_TURISMO_TRX_BT_CLK32K_CAL_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	13256;"	d
+SET_RG_TURISMO_TRX_BT_CLK_SW	smac/hal/ssv6006c/ssv6006C_reg.h	13255;"	d
+SET_RG_TURISMO_TRX_BT_EN_TX_PA_VIN33	smac/hal/ssv6006c/ssv6006C_reg.h	12119;"	d
+SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	12566;"	d
+SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	12564;"	d
+SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	12546;"	d
+SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	12544;"	d
+SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	12542;"	d
+SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	12540;"	d
+SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	12538;"	d
+SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	12536;"	d
+SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	12562;"	d
+SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	12560;"	d
+SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	12558;"	d
+SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	12556;"	d
+SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	12554;"	d
+SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	12552;"	d
+SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	12550;"	d
+SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	12548;"	d
+SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	12598;"	d
+SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	12596;"	d
+SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	12578;"	d
+SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	12576;"	d
+SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	12574;"	d
+SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	12572;"	d
+SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	12570;"	d
+SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	12568;"	d
+SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	12594;"	d
+SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	12592;"	d
+SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	12590;"	d
+SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	12588;"	d
+SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	12586;"	d
+SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	12584;"	d
+SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	12582;"	d
+SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	12580;"	d
+SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	12567;"	d
+SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	12565;"	d
+SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	12547;"	d
+SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	12545;"	d
+SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	12543;"	d
+SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	12541;"	d
+SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	12539;"	d
+SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	12537;"	d
+SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	12563;"	d
+SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	12561;"	d
+SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	12559;"	d
+SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	12557;"	d
+SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	12555;"	d
+SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	12553;"	d
+SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	12551;"	d
+SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	12549;"	d
+SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	12599;"	d
+SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	12597;"	d
+SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	12579;"	d
+SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	12577;"	d
+SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	12575;"	d
+SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	12573;"	d
+SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	12571;"	d
+SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	12569;"	d
+SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	12595;"	d
+SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	12593;"	d
+SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	12591;"	d
+SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	12589;"	d
+SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	12587;"	d
+SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	12585;"	d
+SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	12583;"	d
+SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	12581;"	d
+SET_RG_TURISMO_TRX_BT_PABIAS_2X	smac/hal/ssv6006c/ssv6006C_reg.h	12130;"	d
+SET_RG_TURISMO_TRX_BT_PABIAS_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	12131;"	d
+SET_RG_TURISMO_TRX_BT_RX_ABBCFIX	smac/hal/ssv6006c/ssv6006C_reg.h	12088;"	d
+SET_RG_TURISMO_TRX_BT_RX_ABBCTUNE	smac/hal/ssv6006c/ssv6006C_reg.h	12083;"	d
+SET_RG_TURISMO_TRX_BT_RX_ABB_BT_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	12090;"	d
+SET_RG_TURISMO_TRX_BT_RX_ABB_IDIV3	smac/hal/ssv6006c/ssv6006C_reg.h	12091;"	d
+SET_RG_TURISMO_TRX_BT_RX_ABB_N_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	12089;"	d
+SET_RG_TURISMO_TRX_BT_RX_ADC_CLOAD	smac/hal/ssv6006c/ssv6006C_reg.h	12242;"	d
+SET_RG_TURISMO_TRX_BT_RX_ADC_ICMP	smac/hal/ssv6006c/ssv6006C_reg.h	12240;"	d
+SET_RG_TURISMO_TRX_BT_RX_ADC_VCMI	smac/hal/ssv6006c/ssv6006C_reg.h	12241;"	d
+SET_RG_TURISMO_TRX_BT_RX_DCCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	12615;"	d
+SET_RG_TURISMO_TRX_BT_RX_EN_IDACA_COARSE	smac/hal/ssv6006c/ssv6006C_reg.h	12092;"	d
+SET_RG_TURISMO_TRX_BT_RX_EN_LOOPA	smac/hal/ssv6006c/ssv6006C_reg.h	12093;"	d
+SET_RG_TURISMO_TRX_BT_RX_FILTERI1ST	smac/hal/ssv6006c/ssv6006C_reg.h	12085;"	d
+SET_RG_TURISMO_TRX_BT_RX_FILTERI2ND	smac/hal/ssv6006c/ssv6006C_reg.h	12086;"	d
+SET_RG_TURISMO_TRX_BT_RX_FILTERI3RD	smac/hal/ssv6006c/ssv6006C_reg.h	12087;"	d
+SET_RG_TURISMO_TRX_BT_RX_FILTERI_COARSE	smac/hal/ssv6006c/ssv6006C_reg.h	12084;"	d
+SET_RG_TURISMO_TRX_BT_RX_FILTERVCM	smac/hal/ssv6006c/ssv6006C_reg.h	12094;"	d
+SET_RG_TURISMO_TRX_BT_RX_HG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	12195;"	d
+SET_RG_TURISMO_TRX_BT_RX_HG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	12190;"	d
+SET_RG_TURISMO_TRX_BT_RX_HG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	12191;"	d
+SET_RG_TURISMO_TRX_BT_RX_HG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	12192;"	d
+SET_RG_TURISMO_TRX_BT_RX_HG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	12188;"	d
+SET_RG_TURISMO_TRX_BT_RX_HG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	12196;"	d
+SET_RG_TURISMO_TRX_BT_RX_HG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	12197;"	d
+SET_RG_TURISMO_TRX_BT_RX_HG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	12193;"	d
+SET_RG_TURISMO_TRX_BT_RX_HG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	12189;"	d
+SET_RG_TURISMO_TRX_BT_RX_HG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	12194;"	d
+SET_RG_TURISMO_TRX_BT_RX_HG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	12198;"	d
+SET_RG_TURISMO_TRX_BT_RX_LG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	12217;"	d
+SET_RG_TURISMO_TRX_BT_RX_LG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	12212;"	d
+SET_RG_TURISMO_TRX_BT_RX_LG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	12213;"	d
+SET_RG_TURISMO_TRX_BT_RX_LG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	12214;"	d
+SET_RG_TURISMO_TRX_BT_RX_LG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	12210;"	d
+SET_RG_TURISMO_TRX_BT_RX_LG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	12218;"	d
+SET_RG_TURISMO_TRX_BT_RX_LG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	12219;"	d
+SET_RG_TURISMO_TRX_BT_RX_LG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	12215;"	d
+SET_RG_TURISMO_TRX_BT_RX_LG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	12211;"	d
+SET_RG_TURISMO_TRX_BT_RX_LG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	12216;"	d
+SET_RG_TURISMO_TRX_BT_RX_LG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	12220;"	d
+SET_RG_TURISMO_TRX_BT_RX_MG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	12206;"	d
+SET_RG_TURISMO_TRX_BT_RX_MG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	12201;"	d
+SET_RG_TURISMO_TRX_BT_RX_MG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	12202;"	d
+SET_RG_TURISMO_TRX_BT_RX_MG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	12203;"	d
+SET_RG_TURISMO_TRX_BT_RX_MG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	12199;"	d
+SET_RG_TURISMO_TRX_BT_RX_MG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	12207;"	d
+SET_RG_TURISMO_TRX_BT_RX_MG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	12208;"	d
+SET_RG_TURISMO_TRX_BT_RX_MG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	12204;"	d
+SET_RG_TURISMO_TRX_BT_RX_MG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	12200;"	d
+SET_RG_TURISMO_TRX_BT_RX_MG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	12205;"	d
+SET_RG_TURISMO_TRX_BT_RX_MG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	12209;"	d
+SET_RG_TURISMO_TRX_BT_RX_OUTVCM	smac/hal/ssv6006c/ssv6006C_reg.h	12095;"	d
+SET_RG_TURISMO_TRX_BT_RX_ULG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	12228;"	d
+SET_RG_TURISMO_TRX_BT_RX_ULG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	12223;"	d
+SET_RG_TURISMO_TRX_BT_RX_ULG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	12224;"	d
+SET_RG_TURISMO_TRX_BT_RX_ULG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	12225;"	d
+SET_RG_TURISMO_TRX_BT_RX_ULG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	12221;"	d
+SET_RG_TURISMO_TRX_BT_RX_ULG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	12229;"	d
+SET_RG_TURISMO_TRX_BT_RX_ULG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	12230;"	d
+SET_RG_TURISMO_TRX_BT_RX_ULG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	12226;"	d
+SET_RG_TURISMO_TRX_BT_RX_ULG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	12222;"	d
+SET_RG_TURISMO_TRX_BT_RX_ULG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	12227;"	d
+SET_RG_TURISMO_TRX_BT_RX_ULG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	12231;"	d
+SET_RG_TURISMO_TRX_BT_TRX_IF	smac/hal/ssv6006c/ssv6006C_reg.h	13081;"	d
+SET_RG_TURISMO_TRX_BT_TXLPF_BOOSTI	smac/hal/ssv6006c/ssv6006C_reg.h	12268;"	d
+SET_RG_TURISMO_TRX_BT_TXPGA_CAPSW	smac/hal/ssv6006c/ssv6006C_reg.h	12115;"	d
+SET_RG_TURISMO_TRX_BT_TX_BTPASW	smac/hal/ssv6006c/ssv6006C_reg.h	12118;"	d
+SET_RG_TURISMO_TRX_BT_TX_DACI1ST	smac/hal/ssv6006c/ssv6006C_reg.h	12262;"	d
+SET_RG_TURISMO_TRX_BT_TX_DACLPF_ICOARSE	smac/hal/ssv6006c/ssv6006C_reg.h	12263;"	d
+SET_RG_TURISMO_TRX_BT_TX_DACLPF_IFINE	smac/hal/ssv6006c/ssv6006C_reg.h	12264;"	d
+SET_RG_TURISMO_TRX_BT_TX_DACLPF_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	12265;"	d
+SET_RG_TURISMO_TRX_BT_TX_DAC_CKEDGE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	12270;"	d
+SET_RG_TURISMO_TRX_BT_TX_DAC_IATTN	smac/hal/ssv6006c/ssv6006C_reg.h	12267;"	d
+SET_RG_TURISMO_TRX_BT_TX_DAC_IBIAS	smac/hal/ssv6006c/ssv6006C_reg.h	12266;"	d
+SET_RG_TURISMO_TRX_BT_TX_DAC_IOFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	12272;"	d
+SET_RG_TURISMO_TRX_BT_TX_DAC_OS	smac/hal/ssv6006c/ssv6006C_reg.h	12271;"	d
+SET_RG_TURISMO_TRX_BT_TX_DAC_QOFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	12273;"	d
+SET_RG_TURISMO_TRX_BT_TX_DAC_RCAL	smac/hal/ssv6006c/ssv6006C_reg.h	12269;"	d
+SET_RG_TURISMO_TRX_BT_TX_DIV_VSET	smac/hal/ssv6006c/ssv6006C_reg.h	12116;"	d
+SET_RG_TURISMO_TRX_BT_TX_GAIN_OFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	12139;"	d
+SET_RG_TURISMO_TRX_BT_TX_LOBUF_VSET	smac/hal/ssv6006c/ssv6006C_reg.h	12117;"	d
+SET_RG_TURISMO_TRX_BT_TX_MOD_CS	smac/hal/ssv6006c/ssv6006C_reg.h	12133;"	d
+SET_RG_TURISMO_TRX_BT_TX_PA_VCAS	smac/hal/ssv6006c/ssv6006C_reg.h	12132;"	d
+SET_RG_TURISMO_TRX_BUCK_EN_PSM	smac/hal/ssv6006c/ssv6006C_reg.h	13210;"	d
+SET_RG_TURISMO_TRX_BUCK_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	13208;"	d
+SET_RG_TURISMO_TRX_BUCK_PSM_VTH	smac/hal/ssv6006c/ssv6006C_reg.h	13211;"	d
+SET_RG_TURISMO_TRX_BUCK_RCZERO	smac/hal/ssv6006c/ssv6006C_reg.h	13221;"	d
+SET_RG_TURISMO_TRX_BUCK_SLOP	smac/hal/ssv6006c/ssv6006C_reg.h	13222;"	d
+SET_RG_TURISMO_TRX_BUCK_VREF_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	13212;"	d
+SET_RG_TURISMO_TRX_BW20_HB_COEF_00	smac/hal/ssv6006c/ssv6006C_reg.h	13116;"	d
+SET_RG_TURISMO_TRX_BW20_HB_COEF_01	smac/hal/ssv6006c/ssv6006C_reg.h	13115;"	d
+SET_RG_TURISMO_TRX_BW20_HB_COEF_02	smac/hal/ssv6006c/ssv6006C_reg.h	13118;"	d
+SET_RG_TURISMO_TRX_BW20_HB_COEF_03	smac/hal/ssv6006c/ssv6006C_reg.h	13117;"	d
+SET_RG_TURISMO_TRX_BW20_HB_COEF_04	smac/hal/ssv6006c/ssv6006C_reg.h	13120;"	d
+SET_RG_TURISMO_TRX_BW20_HB_COEF_05	smac/hal/ssv6006c/ssv6006C_reg.h	13119;"	d
+SET_RG_TURISMO_TRX_BW20_HB_COEF_06	smac/hal/ssv6006c/ssv6006C_reg.h	13122;"	d
+SET_RG_TURISMO_TRX_BW20_HB_COEF_07	smac/hal/ssv6006c/ssv6006C_reg.h	13121;"	d
+SET_RG_TURISMO_TRX_BW20_HB_COEF_08	smac/hal/ssv6006c/ssv6006C_reg.h	13124;"	d
+SET_RG_TURISMO_TRX_BW20_HB_COEF_09	smac/hal/ssv6006c/ssv6006C_reg.h	13123;"	d
+SET_RG_TURISMO_TRX_BW20_HB_COEF_10	smac/hal/ssv6006c/ssv6006C_reg.h	13126;"	d
+SET_RG_TURISMO_TRX_BW20_HB_COEF_11	smac/hal/ssv6006c/ssv6006C_reg.h	13125;"	d
+SET_RG_TURISMO_TRX_BW_HT40	smac/hal/ssv6006c/ssv6006C_reg.h	11980;"	d
+SET_RG_TURISMO_TRX_BW_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11981;"	d
+SET_RG_TURISMO_TRX_CAL_INDEX	smac/hal/ssv6006c/ssv6006C_reg.h	11977;"	d
+SET_RG_TURISMO_TRX_CBW_20_40	smac/hal/ssv6006c/ssv6006C_reg.h	13108;"	d
+SET_RG_TURISMO_TRX_CLK_320M_INV	smac/hal/ssv6006c/ssv6006C_reg.h	13106;"	d
+SET_RG_TURISMO_TRX_CLK_MON_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	13328;"	d
+SET_RG_TURISMO_TRX_CLK_RTC_SW	smac/hal/ssv6006c/ssv6006C_reg.h	13251;"	d
+SET_RG_TURISMO_TRX_CLK_SAR_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	12248;"	d
+SET_RG_TURISMO_TRX_DAC_DC_I	smac/hal/ssv6006c/ssv6006C_reg.h	13110;"	d
+SET_RG_TURISMO_TRX_DAC_DC_Q	smac/hal/ssv6006c/ssv6006C_reg.h	13109;"	d
+SET_RG_TURISMO_TRX_DAC_I_SET	smac/hal/ssv6006c/ssv6006C_reg.h	13113;"	d
+SET_RG_TURISMO_TRX_DAC_MAN_I_EN	smac/hal/ssv6006c/ssv6006C_reg.h	13114;"	d
+SET_RG_TURISMO_TRX_DAC_MAN_Q_EN	smac/hal/ssv6006c/ssv6006C_reg.h	13112;"	d
+SET_RG_TURISMO_TRX_DAC_Q_SET	smac/hal/ssv6006c/ssv6006C_reg.h	13111;"	d
+SET_RG_TURISMO_TRX_DCDC_CLK	smac/hal/ssv6006c/ssv6006C_reg.h	13220;"	d
+SET_RG_TURISMO_TRX_DCDC_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	13206;"	d
+SET_RG_TURISMO_TRX_DCDC_PULLLOW_CON	smac/hal/ssv6006c/ssv6006C_reg.h	13215;"	d
+SET_RG_TURISMO_TRX_DCDC_RES2_CON	smac/hal/ssv6006c/ssv6006C_reg.h	13216;"	d
+SET_RG_TURISMO_TRX_DCDC_RES_CON	smac/hal/ssv6006c/ssv6006C_reg.h	13217;"	d
+SET_RG_TURISMO_TRX_DIS_DAC_OFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	13105;"	d
+SET_RG_TURISMO_TRX_DLDO_BOOST_IQ	smac/hal/ssv6006c/ssv6006C_reg.h	13209;"	d
+SET_RG_TURISMO_TRX_DLDO_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	13207;"	d
+SET_RG_TURISMO_TRX_DPLL_CLK320BY2	smac/hal/ssv6006c/ssv6006C_reg.h	13107;"	d
+SET_RG_TURISMO_TRX_DPL_MOD_ORDER	smac/hal/ssv6006c/ssv6006C_reg.h	12431;"	d
+SET_RG_TURISMO_TRX_DPL_RFCTRL_CH	smac/hal/ssv6006c/ssv6006C_reg.h	12451;"	d
+SET_RG_TURISMO_TRX_DPL_RFCTRL_F	smac/hal/ssv6006c/ssv6006C_reg.h	12450;"	d
+SET_RG_TURISMO_TRX_DPL_SETTLING_TIMMER	smac/hal/ssv6006c/ssv6006C_reg.h	13200;"	d
+SET_RG_TURISMO_TRX_DP_ADC320_DIVBY2_BT	smac/hal/ssv6006c/ssv6006C_reg.h	12428;"	d
+SET_RG_TURISMO_TRX_DP_ADC320_DIVBY2_WF	smac/hal/ssv6006c/ssv6006C_reg.h	12429;"	d
+SET_RG_TURISMO_TRX_DP_BBPLL_BP	smac/hal/ssv6006c/ssv6006C_reg.h	12424;"	d
+SET_RG_TURISMO_TRX_DP_BBPLL_BS	smac/hal/ssv6006c/ssv6006C_reg.h	12448;"	d
+SET_RG_TURISMO_TRX_DP_BBPLL_ICP	smac/hal/ssv6006c/ssv6006C_reg.h	12437;"	d
+SET_RG_TURISMO_TRX_DP_BBPLL_IDUAL	smac/hal/ssv6006c/ssv6006C_reg.h	12438;"	d
+SET_RG_TURISMO_TRX_DP_BBPLL_PD	smac/hal/ssv6006c/ssv6006C_reg.h	12423;"	d
+SET_RG_TURISMO_TRX_DP_BBPLL_PFD_DLY	smac/hal/ssv6006c/ssv6006C_reg.h	12442;"	d
+SET_RG_TURISMO_TRX_DP_BBPLL_SDM_EDGE	smac/hal/ssv6006c/ssv6006C_reg.h	12449;"	d
+SET_RG_TURISMO_TRX_DP_BBPLL_TESTSEL	smac/hal/ssv6006c/ssv6006C_reg.h	12436;"	d
+SET_RG_TURISMO_TRX_DP_CP_IOST	smac/hal/ssv6006c/ssv6006C_reg.h	12440;"	d
+SET_RG_TURISMO_TRX_DP_CP_IOSTPOL	smac/hal/ssv6006c/ssv6006C_reg.h	12439;"	d
+SET_RG_TURISMO_TRX_DP_DAC320_DIVBY2	smac/hal/ssv6006c/ssv6006C_reg.h	12427;"	d
+SET_RG_TURISMO_TRX_DP_FODIV	smac/hal/ssv6006c/ssv6006C_reg.h	12433;"	d
+SET_RG_TURISMO_TRX_DP_FREF_DOUB	smac/hal/ssv6006c/ssv6006C_reg.h	12426;"	d
+SET_RG_TURISMO_TRX_DP_LDO_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	12048;"	d
+SET_RG_TURISMO_TRX_DP_OD_TEST	smac/hal/ssv6006c/ssv6006C_reg.h	12435;"	d
+SET_RG_TURISMO_TRX_DP_PFD_PFDSEL	smac/hal/ssv6006c/ssv6006C_reg.h	12441;"	d
+SET_RG_TURISMO_TRX_DP_REFDIV	smac/hal/ssv6006c/ssv6006C_reg.h	12432;"	d
+SET_RG_TURISMO_TRX_DP_RHP	smac/hal/ssv6006c/ssv6006C_reg.h	12444;"	d
+SET_RG_TURISMO_TRX_DP_RP	smac/hal/ssv6006c/ssv6006C_reg.h	12443;"	d
+SET_RG_TURISMO_TRX_DP_VT_TH_HI	smac/hal/ssv6006c/ssv6006C_reg.h	12446;"	d
+SET_RG_TURISMO_TRX_DP_VT_TH_LO	smac/hal/ssv6006c/ssv6006C_reg.h	12447;"	d
+SET_RG_TURISMO_TRX_EN_AAC5GB_MXPDSW	smac/hal/ssv6006c/ssv6006C_reg.h	12923;"	d
+SET_RG_TURISMO_TRX_EN_AAC5GB_RPPDSW	smac/hal/ssv6006c/ssv6006C_reg.h	12924;"	d
+SET_RG_TURISMO_TRX_EN_AAC5GB_VOPDSW	smac/hal/ssv6006c/ssv6006C_reg.h	12922;"	d
+SET_RG_TURISMO_TRX_EN_DLDO_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	13185;"	d
+SET_RG_TURISMO_TRX_EN_DPL_MOD	smac/hal/ssv6006c/ssv6006C_reg.h	12430;"	d
+SET_RG_TURISMO_TRX_EN_DP_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	12425;"	d
+SET_RG_TURISMO_TRX_EN_DP_VT_MON	smac/hal/ssv6006c/ssv6006C_reg.h	12445;"	d
+SET_RG_TURISMO_TRX_EN_FDB	smac/hal/ssv6006c/ssv6006C_reg.h	13188;"	d
+SET_RG_TURISMO_TRX_EN_FDB_DCC_MUAL	smac/hal/ssv6006c/ssv6006C_reg.h	13192;"	d
+SET_RG_TURISMO_TRX_EN_FDB_DELAYC_MUAL	smac/hal/ssv6006c/ssv6006C_reg.h	13193;"	d
+SET_RG_TURISMO_TRX_EN_FDB_DELAYF_MUAL	smac/hal/ssv6006c/ssv6006C_reg.h	13194;"	d
+SET_RG_TURISMO_TRX_EN_FDB_PHASESWAP_MUAL	smac/hal/ssv6006c/ssv6006C_reg.h	13195;"	d
+SET_RG_TURISMO_TRX_EN_FDB_RECAL	smac/hal/ssv6006c/ssv6006C_reg.h	13204;"	d
+SET_RG_TURISMO_TRX_EN_HSDIV_OBF_MX	smac/hal/ssv6006c/ssv6006C_reg.h	12813;"	d
+SET_RG_TURISMO_TRX_EN_HSDIV_OBF_MX_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	12812;"	d
+SET_RG_TURISMO_TRX_EN_HSDIV_OBF_SX	smac/hal/ssv6006c/ssv6006C_reg.h	12811;"	d
+SET_RG_TURISMO_TRX_EN_HSDIV_OBF_SX_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	12810;"	d
+SET_RG_TURISMO_TRX_EN_IOT_ADC	smac/hal/ssv6006c/ssv6006C_reg.h	12014;"	d
+SET_RG_TURISMO_TRX_EN_IOT_ADC_BUF	smac/hal/ssv6006c/ssv6006C_reg.h	12013;"	d
+SET_RG_TURISMO_TRX_EN_IREF_RX	smac/hal/ssv6006c/ssv6006C_reg.h	12017;"	d
+SET_RG_TURISMO_TRX_EN_LDO_5G_CP	smac/hal/ssv6006c/ssv6006C_reg.h	12827;"	d
+SET_RG_TURISMO_TRX_EN_LDO_5G_CP_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	12684;"	d
+SET_RG_TURISMO_TRX_EN_LDO_5G_CP_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	12833;"	d
+SET_RG_TURISMO_TRX_EN_LDO_5G_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	12828;"	d
+SET_RG_TURISMO_TRX_EN_LDO_5G_DIV_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	12689;"	d
+SET_RG_TURISMO_TRX_EN_LDO_5G_DIV_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	12834;"	d
+SET_RG_TURISMO_TRX_EN_LDO_5G_LO	smac/hal/ssv6006c/ssv6006C_reg.h	12829;"	d
+SET_RG_TURISMO_TRX_EN_LDO_5G_LO_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	12686;"	d
+SET_RG_TURISMO_TRX_EN_LDO_5G_LO_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	12835;"	d
+SET_RG_TURISMO_TRX_EN_LDO_5G_VCO	smac/hal/ssv6006c/ssv6006C_reg.h	12830;"	d
+SET_RG_TURISMO_TRX_EN_LDO_5G_VCO_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	12836;"	d
+SET_RG_TURISMO_TRX_EN_LDO_5G_VCO_PSW	smac/hal/ssv6006c/ssv6006C_reg.h	12831;"	d
+SET_RG_TURISMO_TRX_EN_LDO_5G_VCO_VDD33	smac/hal/ssv6006c/ssv6006C_reg.h	12832;"	d
+SET_RG_TURISMO_TRX_EN_LDO_AFE	smac/hal/ssv6006c/ssv6006C_reg.h	12016;"	d
+SET_RG_TURISMO_TRX_EN_LDO_CP	smac/hal/ssv6006c/ssv6006C_reg.h	12302;"	d
+SET_RG_TURISMO_TRX_EN_LDO_CP_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	12051;"	d
+SET_RG_TURISMO_TRX_EN_LDO_CP_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	12308;"	d
+SET_RG_TURISMO_TRX_EN_LDO_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	12303;"	d
+SET_RG_TURISMO_TRX_EN_LDO_DIV_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	12056;"	d
+SET_RG_TURISMO_TRX_EN_LDO_DIV_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	12309;"	d
+SET_RG_TURISMO_TRX_EN_LDO_DP_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	12049;"	d
+SET_RG_TURISMO_TRX_EN_LDO_DP_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	12434;"	d
+SET_RG_TURISMO_TRX_EN_LDO_EFUSE	smac/hal/ssv6006c/ssv6006C_reg.h	13214;"	d
+SET_RG_TURISMO_TRX_EN_LDO_LO	smac/hal/ssv6006c/ssv6006C_reg.h	12304;"	d
+SET_RG_TURISMO_TRX_EN_LDO_LO_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	12053;"	d
+SET_RG_TURISMO_TRX_EN_LDO_LO_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	12310;"	d
+SET_RG_TURISMO_TRX_EN_LDO_RX_AFE_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	12046;"	d
+SET_RG_TURISMO_TRX_EN_LDO_RX_AFE_FC	smac/hal/ssv6006c/ssv6006C_reg.h	12039;"	d
+SET_RG_TURISMO_TRX_EN_LDO_RX_AFE_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	12041;"	d
+SET_RG_TURISMO_TRX_EN_LDO_RX_FE	smac/hal/ssv6006c/ssv6006C_reg.h	12015;"	d
+SET_RG_TURISMO_TRX_EN_LDO_RX_FE_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	12044;"	d
+SET_RG_TURISMO_TRX_EN_LDO_RX_FE_FC	smac/hal/ssv6006c/ssv6006C_reg.h	12038;"	d
+SET_RG_TURISMO_TRX_EN_LDO_RX_FE_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	12040;"	d
+SET_RG_TURISMO_TRX_EN_LDO_TX_PA	smac/hal/ssv6006c/ssv6006C_reg.h	12121;"	d
+SET_RG_TURISMO_TRX_EN_LDO_VCO	smac/hal/ssv6006c/ssv6006C_reg.h	12305;"	d
+SET_RG_TURISMO_TRX_EN_LDO_VCO_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	12311;"	d
+SET_RG_TURISMO_TRX_EN_LDO_VCO_PSW	smac/hal/ssv6006c/ssv6006C_reg.h	12306;"	d
+SET_RG_TURISMO_TRX_EN_LDO_VCO_VDD33	smac/hal/ssv6006c/ssv6006C_reg.h	12307;"	d
+SET_RG_TURISMO_TRX_EN_LDO_XO_BYP	smac/hal/ssv6006c/ssv6006C_reg.h	13184;"	d
+SET_RG_TURISMO_TRX_EN_LDO_XO_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	13183;"	d
+SET_RG_TURISMO_TRX_EN_RTC_CAL	smac/hal/ssv6006c/ssv6006C_reg.h	13229;"	d
+SET_RG_TURISMO_TRX_EN_RX_ADC	smac/hal/ssv6006c/ssv6006C_reg.h	11998;"	d
+SET_RG_TURISMO_TRX_EN_RX_DIV2	smac/hal/ssv6006c/ssv6006C_reg.h	11990;"	d
+SET_RG_TURISMO_TRX_EN_RX_FILTER	smac/hal/ssv6006c/ssv6006C_reg.h	11996;"	d
+SET_RG_TURISMO_TRX_EN_RX_IQCAL	smac/hal/ssv6006c/ssv6006C_reg.h	12025;"	d
+SET_RG_TURISMO_TRX_EN_RX_LNA	smac/hal/ssv6006c/ssv6006C_reg.h	11986;"	d
+SET_RG_TURISMO_TRX_EN_RX_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	11992;"	d
+SET_RG_TURISMO_TRX_EN_RX_MIXER	smac/hal/ssv6006c/ssv6006C_reg.h	11988;"	d
+SET_RG_TURISMO_TRX_EN_RX_PADSW	smac/hal/ssv6006c/ssv6006C_reg.h	12037;"	d
+SET_RG_TURISMO_TRX_EN_RX_RSSI	smac/hal/ssv6006c/ssv6006C_reg.h	12000;"	d
+SET_RG_TURISMO_TRX_EN_RX_RSSI_TESTNODE	smac/hal/ssv6006c/ssv6006C_reg.h	12107;"	d
+SET_RG_TURISMO_TRX_EN_RX_TESTNODE	smac/hal/ssv6006c/ssv6006C_reg.h	12036;"	d
+SET_RG_TURISMO_TRX_EN_RX_TZ	smac/hal/ssv6006c/ssv6006C_reg.h	11994;"	d
+SET_RG_TURISMO_TRX_EN_SARADC	smac/hal/ssv6006c/ssv6006C_reg.h	12029;"	d
+SET_RG_TURISMO_TRX_EN_SAR_TEST	smac/hal/ssv6006c/ssv6006C_reg.h	12245;"	d
+SET_RG_TURISMO_TRX_EN_SX5GB_CP	smac/hal/ssv6006c/ssv6006C_reg.h	12799;"	d
+SET_RG_TURISMO_TRX_EN_SX5GB_CP_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	12798;"	d
+SET_RG_TURISMO_TRX_EN_SX5GB_DITHER	smac/hal/ssv6006c/ssv6006C_reg.h	12898;"	d
+SET_RG_TURISMO_TRX_EN_SX5GB_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	12801;"	d
+SET_RG_TURISMO_TRX_EN_SX5GB_DIV_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	12800;"	d
+SET_RG_TURISMO_TRX_EN_SX5GB_HSDIV	smac/hal/ssv6006c/ssv6006C_reg.h	12809;"	d
+SET_RG_TURISMO_TRX_EN_SX5GB_HSDIV_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	12808;"	d
+SET_RG_TURISMO_TRX_EN_SX5GB_LDO_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	12826;"	d
+SET_RG_TURISMO_TRX_EN_SX5GB_MOD	smac/hal/ssv6006c/ssv6006C_reg.h	12897;"	d
+SET_RG_TURISMO_TRX_EN_SX5GB_VCO	smac/hal/ssv6006c/ssv6006C_reg.h	12803;"	d
+SET_RG_TURISMO_TRX_EN_SX5GB_VCOMON	smac/hal/ssv6006c/ssv6006C_reg.h	12891;"	d
+SET_RG_TURISMO_TRX_EN_SX5GB_VCO_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	12802;"	d
+SET_RG_TURISMO_TRX_EN_SX_CP	smac/hal/ssv6006c/ssv6006C_reg.h	12277;"	d
+SET_RG_TURISMO_TRX_EN_SX_CP_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	12276;"	d
+SET_RG_TURISMO_TRX_EN_SX_DITHER	smac/hal/ssv6006c/ssv6006C_reg.h	12390;"	d
+SET_RG_TURISMO_TRX_EN_SX_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	12279;"	d
+SET_RG_TURISMO_TRX_EN_SX_DIV_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	12278;"	d
+SET_RG_TURISMO_TRX_EN_SX_LDO_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	12301;"	d
+SET_RG_TURISMO_TRX_EN_SX_MIX	smac/hal/ssv6006c/ssv6006C_reg.h	12815;"	d
+SET_RG_TURISMO_TRX_EN_SX_MIX_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	12814;"	d
+SET_RG_TURISMO_TRX_EN_SX_MOD	smac/hal/ssv6006c/ssv6006C_reg.h	12389;"	d
+SET_RG_TURISMO_TRX_EN_SX_REP	smac/hal/ssv6006c/ssv6006C_reg.h	12817;"	d
+SET_RG_TURISMO_TRX_EN_SX_REP_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	12816;"	d
+SET_RG_TURISMO_TRX_EN_SX_VCO	smac/hal/ssv6006c/ssv6006C_reg.h	12281;"	d
+SET_RG_TURISMO_TRX_EN_SX_VCOMON	smac/hal/ssv6006c/ssv6006C_reg.h	12383;"	d
+SET_RG_TURISMO_TRX_EN_SX_VCO_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	12280;"	d
+SET_RG_TURISMO_TRX_EN_TX_BT_PA	smac/hal/ssv6006c/ssv6006C_reg.h	12012;"	d
+SET_RG_TURISMO_TRX_EN_TX_DAC	smac/hal/ssv6006c/ssv6006C_reg.h	12006;"	d
+SET_RG_TURISMO_TRX_EN_TX_DAC_CAL	smac/hal/ssv6006c/ssv6006C_reg.h	12019;"	d
+SET_RG_TURISMO_TRX_EN_TX_DAC_OUT	smac/hal/ssv6006c/ssv6006C_reg.h	12033;"	d
+SET_RG_TURISMO_TRX_EN_TX_DAC_VOUT	smac/hal/ssv6006c/ssv6006C_reg.h	12034;"	d
+SET_RG_TURISMO_TRX_EN_TX_DIV2	smac/hal/ssv6006c/ssv6006C_reg.h	12008;"	d
+SET_RG_TURISMO_TRX_EN_TX_DIV2_BUF	smac/hal/ssv6006c/ssv6006C_reg.h	12010;"	d
+SET_RG_TURISMO_TRX_EN_TX_DPD	smac/hal/ssv6006c/ssv6006C_reg.h	12027;"	d
+SET_RG_TURISMO_TRX_EN_TX_MOD	smac/hal/ssv6006c/ssv6006C_reg.h	12004;"	d
+SET_RG_TURISMO_TRX_EN_TX_PA	smac/hal/ssv6006c/ssv6006C_reg.h	12002;"	d
+SET_RG_TURISMO_TRX_EN_TX_PA_LDO_FC	smac/hal/ssv6006c/ssv6006C_reg.h	12122;"	d
+SET_RG_TURISMO_TRX_EN_TX_PA_LDO_IQUP	smac/hal/ssv6006c/ssv6006C_reg.h	12123;"	d
+SET_RG_TURISMO_TRX_EN_TX_PA_LDO_VTH	smac/hal/ssv6006c/ssv6006C_reg.h	12124;"	d
+SET_RG_TURISMO_TRX_EN_TX_SELF_MIXER	smac/hal/ssv6006c/ssv6006C_reg.h	12023;"	d
+SET_RG_TURISMO_TRX_EN_TX_TRSW	smac/hal/ssv6006c/ssv6006C_reg.h	11984;"	d
+SET_RG_TURISMO_TRX_EN_TX_TSSI	smac/hal/ssv6006c/ssv6006C_reg.h	12028;"	d
+SET_RG_TURISMO_TRX_EN_TX_VTOI_2ND	smac/hal/ssv6006c/ssv6006C_reg.h	12030;"	d
+SET_RG_TURISMO_TRX_EN_VCOBF_DIVCK	smac/hal/ssv6006c/ssv6006C_reg.h	12295;"	d
+SET_RG_TURISMO_TRX_EN_VCOBF_DIVCK_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	12294;"	d
+SET_RG_TURISMO_TRX_EN_VCOBF_RXMB	smac/hal/ssv6006c/ssv6006C_reg.h	12291;"	d
+SET_RG_TURISMO_TRX_EN_VCOBF_RXMB_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	12290;"	d
+SET_RG_TURISMO_TRX_EN_VCOBF_RXOB	smac/hal/ssv6006c/ssv6006C_reg.h	12293;"	d
+SET_RG_TURISMO_TRX_EN_VCOBF_RXOB_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	12292;"	d
+SET_RG_TURISMO_TRX_EN_VCOBF_TXMB	smac/hal/ssv6006c/ssv6006C_reg.h	12287;"	d
+SET_RG_TURISMO_TRX_EN_VCOBF_TXMB_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	12286;"	d
+SET_RG_TURISMO_TRX_EN_VCOBF_TXOB	smac/hal/ssv6006c/ssv6006C_reg.h	12289;"	d
+SET_RG_TURISMO_TRX_EN_VCOBF_TXOB_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	12288;"	d
+SET_RG_TURISMO_TRX_EN_XOTEST	smac/hal/ssv6006c/ssv6006C_reg.h	13191;"	d
+SET_RG_TURISMO_TRX_EXT_MCU_PWRUP	smac/hal/ssv6006c/ssv6006C_reg.h	13329;"	d
+SET_RG_TURISMO_TRX_FDB_BYPASS	smac/hal/ssv6006c/ssv6006C_reg.h	13189;"	d
+SET_RG_TURISMO_TRX_FDB_CDELAY_MUAL	smac/hal/ssv6006c/ssv6006C_reg.h	13197;"	d
+SET_RG_TURISMO_TRX_FDB_DUTY_LTH	smac/hal/ssv6006c/ssv6006C_reg.h	13190;"	d
+SET_RG_TURISMO_TRX_FDB_FDELAY_MUAL	smac/hal/ssv6006c/ssv6006C_reg.h	13198;"	d
+SET_RG_TURISMO_TRX_FDB_PHASESWAP_MUAL	smac/hal/ssv6006c/ssv6006C_reg.h	13196;"	d
+SET_RG_TURISMO_TRX_FDB_RDELAYF	smac/hal/ssv6006c/ssv6006C_reg.h	13201;"	d
+SET_RG_TURISMO_TRX_FDB_RDELAYS	smac/hal/ssv6006c/ssv6006C_reg.h	13202;"	d
+SET_RG_TURISMO_TRX_FDB_RECAL_TIMMER	smac/hal/ssv6006c/ssv6006C_reg.h	13203;"	d
+SET_RG_TURISMO_TRX_FPGA_CLK_REF_40M_DS	smac/hal/ssv6006c/ssv6006C_reg.h	13273;"	d
+SET_RG_TURISMO_TRX_FPGA_CLK_REF_40M_EN	smac/hal/ssv6006c/ssv6006C_reg.h	13250;"	d
+SET_RG_TURISMO_TRX_FPGA_CLK_REF_40M_OE	smac/hal/ssv6006c/ssv6006C_reg.h	13275;"	d
+SET_RG_TURISMO_TRX_FPGA_CLK_REF_40M_PD	smac/hal/ssv6006c/ssv6006C_reg.h	13274;"	d
+SET_RG_TURISMO_TRX_GPIO00_DS	smac/hal/ssv6006c/ssv6006C_reg.h	13300;"	d
+SET_RG_TURISMO_TRX_GPIO00_OE	smac/hal/ssv6006c/ssv6006C_reg.h	13302;"	d
+SET_RG_TURISMO_TRX_GPIO00_PD	smac/hal/ssv6006c/ssv6006C_reg.h	13301;"	d
+SET_RG_TURISMO_TRX_GPIO01_DS	smac/hal/ssv6006c/ssv6006C_reg.h	13303;"	d
+SET_RG_TURISMO_TRX_GPIO01_OE	smac/hal/ssv6006c/ssv6006C_reg.h	13305;"	d
+SET_RG_TURISMO_TRX_GPIO01_PD	smac/hal/ssv6006c/ssv6006C_reg.h	13304;"	d
+SET_RG_TURISMO_TRX_GPIO02_DS	smac/hal/ssv6006c/ssv6006C_reg.h	13306;"	d
+SET_RG_TURISMO_TRX_GPIO02_OE	smac/hal/ssv6006c/ssv6006C_reg.h	13308;"	d
+SET_RG_TURISMO_TRX_GPIO02_PD	smac/hal/ssv6006c/ssv6006C_reg.h	13307;"	d
+SET_RG_TURISMO_TRX_GPIO03_DS	smac/hal/ssv6006c/ssv6006C_reg.h	13309;"	d
+SET_RG_TURISMO_TRX_GPIO03_OE	smac/hal/ssv6006c/ssv6006C_reg.h	13311;"	d
+SET_RG_TURISMO_TRX_GPIO03_PD	smac/hal/ssv6006c/ssv6006C_reg.h	13310;"	d
+SET_RG_TURISMO_TRX_GPIO04_DS	smac/hal/ssv6006c/ssv6006C_reg.h	13312;"	d
+SET_RG_TURISMO_TRX_GPIO04_OE	smac/hal/ssv6006c/ssv6006C_reg.h	13314;"	d
+SET_RG_TURISMO_TRX_GPIO04_PD	smac/hal/ssv6006c/ssv6006C_reg.h	13313;"	d
+SET_RG_TURISMO_TRX_GPIO05_DS	smac/hal/ssv6006c/ssv6006C_reg.h	13315;"	d
+SET_RG_TURISMO_TRX_GPIO05_OE	smac/hal/ssv6006c/ssv6006C_reg.h	13317;"	d
+SET_RG_TURISMO_TRX_GPIO05_PD	smac/hal/ssv6006c/ssv6006C_reg.h	13316;"	d
+SET_RG_TURISMO_TRX_GPIO06_DS	smac/hal/ssv6006c/ssv6006C_reg.h	13318;"	d
+SET_RG_TURISMO_TRX_GPIO06_OE	smac/hal/ssv6006c/ssv6006C_reg.h	13320;"	d
+SET_RG_TURISMO_TRX_GPIO06_PD	smac/hal/ssv6006c/ssv6006C_reg.h	13319;"	d
+SET_RG_TURISMO_TRX_GPIO07_DS	smac/hal/ssv6006c/ssv6006C_reg.h	13321;"	d
+SET_RG_TURISMO_TRX_GPIO07_OE	smac/hal/ssv6006c/ssv6006C_reg.h	13323;"	d
+SET_RG_TURISMO_TRX_GPIO07_PD	smac/hal/ssv6006c/ssv6006C_reg.h	13322;"	d
+SET_RG_TURISMO_TRX_GPIO08_DS	smac/hal/ssv6006c/ssv6006C_reg.h	13276;"	d
+SET_RG_TURISMO_TRX_GPIO08_OE	smac/hal/ssv6006c/ssv6006C_reg.h	13278;"	d
+SET_RG_TURISMO_TRX_GPIO08_PD	smac/hal/ssv6006c/ssv6006C_reg.h	13277;"	d
+SET_RG_TURISMO_TRX_GPIO09_DS	smac/hal/ssv6006c/ssv6006C_reg.h	13279;"	d
+SET_RG_TURISMO_TRX_GPIO09_OE	smac/hal/ssv6006c/ssv6006C_reg.h	13281;"	d
+SET_RG_TURISMO_TRX_GPIO09_PD	smac/hal/ssv6006c/ssv6006C_reg.h	13280;"	d
+SET_RG_TURISMO_TRX_GPIO10_DS	smac/hal/ssv6006c/ssv6006C_reg.h	13282;"	d
+SET_RG_TURISMO_TRX_GPIO10_OE	smac/hal/ssv6006c/ssv6006C_reg.h	13284;"	d
+SET_RG_TURISMO_TRX_GPIO10_PD	smac/hal/ssv6006c/ssv6006C_reg.h	13283;"	d
+SET_RG_TURISMO_TRX_GPIO11_DS	smac/hal/ssv6006c/ssv6006C_reg.h	13285;"	d
+SET_RG_TURISMO_TRX_GPIO11_OE	smac/hal/ssv6006c/ssv6006C_reg.h	13287;"	d
+SET_RG_TURISMO_TRX_GPIO11_PD	smac/hal/ssv6006c/ssv6006C_reg.h	13286;"	d
+SET_RG_TURISMO_TRX_GPIO12_DS	smac/hal/ssv6006c/ssv6006C_reg.h	13288;"	d
+SET_RG_TURISMO_TRX_GPIO12_OE	smac/hal/ssv6006c/ssv6006C_reg.h	13290;"	d
+SET_RG_TURISMO_TRX_GPIO12_PD	smac/hal/ssv6006c/ssv6006C_reg.h	13289;"	d
+SET_RG_TURISMO_TRX_GPIO13_DS	smac/hal/ssv6006c/ssv6006C_reg.h	13291;"	d
+SET_RG_TURISMO_TRX_GPIO13_OE	smac/hal/ssv6006c/ssv6006C_reg.h	13293;"	d
+SET_RG_TURISMO_TRX_GPIO13_PD	smac/hal/ssv6006c/ssv6006C_reg.h	13292;"	d
+SET_RG_TURISMO_TRX_GPIO14_DS	smac/hal/ssv6006c/ssv6006C_reg.h	13294;"	d
+SET_RG_TURISMO_TRX_GPIO14_OE	smac/hal/ssv6006c/ssv6006C_reg.h	13296;"	d
+SET_RG_TURISMO_TRX_GPIO14_PD	smac/hal/ssv6006c/ssv6006C_reg.h	13295;"	d
+SET_RG_TURISMO_TRX_GPIO15_DS	smac/hal/ssv6006c/ssv6006C_reg.h	13297;"	d
+SET_RG_TURISMO_TRX_GPIO15_OE	smac/hal/ssv6006c/ssv6006C_reg.h	13299;"	d
+SET_RG_TURISMO_TRX_GPIO15_PD	smac/hal/ssv6006c/ssv6006C_reg.h	13298;"	d
+SET_RG_TURISMO_TRX_GPIO16_DS	smac/hal/ssv6006c/ssv6006C_reg.h	13257;"	d
+SET_RG_TURISMO_TRX_GPIO16_OE	smac/hal/ssv6006c/ssv6006C_reg.h	13259;"	d
+SET_RG_TURISMO_TRX_GPIO16_PD	smac/hal/ssv6006c/ssv6006C_reg.h	13258;"	d
+SET_RG_TURISMO_TRX_GPIO17_DS	smac/hal/ssv6006c/ssv6006C_reg.h	13260;"	d
+SET_RG_TURISMO_TRX_GPIO17_OE	smac/hal/ssv6006c/ssv6006C_reg.h	13262;"	d
+SET_RG_TURISMO_TRX_GPIO17_PD	smac/hal/ssv6006c/ssv6006C_reg.h	13261;"	d
+SET_RG_TURISMO_TRX_GPIO18_DS	smac/hal/ssv6006c/ssv6006C_reg.h	13263;"	d
+SET_RG_TURISMO_TRX_GPIO18_OE	smac/hal/ssv6006c/ssv6006C_reg.h	13265;"	d
+SET_RG_TURISMO_TRX_GPIO18_PD	smac/hal/ssv6006c/ssv6006C_reg.h	13264;"	d
+SET_RG_TURISMO_TRX_GPIO19_DS	smac/hal/ssv6006c/ssv6006C_reg.h	13266;"	d
+SET_RG_TURISMO_TRX_GPIO19_OE	smac/hal/ssv6006c/ssv6006C_reg.h	13268;"	d
+SET_RG_TURISMO_TRX_GPIO19_PD	smac/hal/ssv6006c/ssv6006C_reg.h	13267;"	d
+SET_RG_TURISMO_TRX_GPIO20_DS	smac/hal/ssv6006c/ssv6006C_reg.h	13269;"	d
+SET_RG_TURISMO_TRX_GPIO20_OE	smac/hal/ssv6006c/ssv6006C_reg.h	13271;"	d
+SET_RG_TURISMO_TRX_GPIO20_PD	smac/hal/ssv6006c/ssv6006C_reg.h	13270;"	d
+SET_RG_TURISMO_TRX_HS3W_COMM_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	13172;"	d
+SET_RG_TURISMO_TRX_HS3W_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	13171;"	d
+SET_RG_TURISMO_TRX_HS3W_PGAGC	smac/hal/ssv6006c/ssv6006C_reg.h	13167;"	d
+SET_RG_TURISMO_TRX_HS3W_RFGC	smac/hal/ssv6006c/ssv6006C_reg.h	13168;"	d
+SET_RG_TURISMO_TRX_HS3W_RF_PHY_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	13170;"	d
+SET_RG_TURISMO_TRX_HS3W_RXAGC	smac/hal/ssv6006c/ssv6006C_reg.h	13169;"	d
+SET_RG_TURISMO_TRX_HS3W_START_SENT	smac/hal/ssv6006c/ssv6006C_reg.h	13173;"	d
+SET_RG_TURISMO_TRX_HS3W_SX_CHANNEL_INT	smac/hal/ssv6006c/ssv6006C_reg.h	13176;"	d
+SET_RG_TURISMO_TRX_HS3W_SX_RFCH_MAP_EN_INT	smac/hal/ssv6006c/ssv6006C_reg.h	13175;"	d
+SET_RG_TURISMO_TRX_HS3W_SX_RFCTRL_CH_INT_10_8	smac/hal/ssv6006c/ssv6006C_reg.h	13174;"	d
+SET_RG_TURISMO_TRX_HS3W_SX_RFCTRL_CH_INT_7_0	smac/hal/ssv6006c/ssv6006C_reg.h	13178;"	d
+SET_RG_TURISMO_TRX_HS3W_SX_RFCTRL_F_INT	smac/hal/ssv6006c/ssv6006C_reg.h	13177;"	d
+SET_RG_TURISMO_TRX_HS3W_TX_RF_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	13166;"	d
+SET_RG_TURISMO_TRX_HSDIV_INBFSEL	smac/hal/ssv6006c/ssv6006C_reg.h	12882;"	d
+SET_RG_TURISMO_TRX_HSDIV_OBFMX_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	12883;"	d
+SET_RG_TURISMO_TRX_HSDIV_OBFSX_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	12884;"	d
+SET_RG_TURISMO_TRX_HSDIV_VRSEL	smac/hal/ssv6006c/ssv6006C_reg.h	12885;"	d
+SET_RG_TURISMO_TRX_HS_3WIRE_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11970;"	d
+SET_RG_TURISMO_TRX_HW_PINSEL	smac/hal/ssv6006c/ssv6006C_reg.h	11969;"	d
+SET_RG_TURISMO_TRX_IDACAI_TZ0_COARSE0	smac/hal/ssv6006c/ssv6006C_reg.h	12524;"	d
+SET_RG_TURISMO_TRX_IDACAI_TZ0_COARSE1	smac/hal/ssv6006c/ssv6006C_reg.h	12522;"	d
+SET_RG_TURISMO_TRX_IDACAI_TZ0_COARSE2	smac/hal/ssv6006c/ssv6006C_reg.h	12520;"	d
+SET_RG_TURISMO_TRX_IDACAI_TZ0_COARSE3	smac/hal/ssv6006c/ssv6006C_reg.h	12518;"	d
+SET_RG_TURISMO_TRX_IDACAI_TZ0_COARSE4	smac/hal/ssv6006c/ssv6006C_reg.h	12516;"	d
+SET_RG_TURISMO_TRX_IDACAI_TZ1_COARSE0	smac/hal/ssv6006c/ssv6006C_reg.h	12534;"	d
+SET_RG_TURISMO_TRX_IDACAI_TZ1_COARSE1	smac/hal/ssv6006c/ssv6006C_reg.h	12532;"	d
+SET_RG_TURISMO_TRX_IDACAI_TZ1_COARSE2	smac/hal/ssv6006c/ssv6006C_reg.h	12530;"	d
+SET_RG_TURISMO_TRX_IDACAI_TZ1_COARSE3	smac/hal/ssv6006c/ssv6006C_reg.h	12528;"	d
+SET_RG_TURISMO_TRX_IDACAI_TZ1_COARSE4	smac/hal/ssv6006c/ssv6006C_reg.h	12526;"	d
+SET_RG_TURISMO_TRX_IDACAQ_TZ0_COARSE0	smac/hal/ssv6006c/ssv6006C_reg.h	12525;"	d
+SET_RG_TURISMO_TRX_IDACAQ_TZ0_COARSE1	smac/hal/ssv6006c/ssv6006C_reg.h	12523;"	d
+SET_RG_TURISMO_TRX_IDACAQ_TZ0_COARSE2	smac/hal/ssv6006c/ssv6006C_reg.h	12521;"	d
+SET_RG_TURISMO_TRX_IDACAQ_TZ0_COARSE3	smac/hal/ssv6006c/ssv6006C_reg.h	12519;"	d
+SET_RG_TURISMO_TRX_IDACAQ_TZ0_COARSE4	smac/hal/ssv6006c/ssv6006C_reg.h	12517;"	d
+SET_RG_TURISMO_TRX_IDACAQ_TZ1_COARSE0	smac/hal/ssv6006c/ssv6006C_reg.h	12535;"	d
+SET_RG_TURISMO_TRX_IDACAQ_TZ1_COARSE1	smac/hal/ssv6006c/ssv6006C_reg.h	12533;"	d
+SET_RG_TURISMO_TRX_IDACAQ_TZ1_COARSE2	smac/hal/ssv6006c/ssv6006C_reg.h	12531;"	d
+SET_RG_TURISMO_TRX_IDACAQ_TZ1_COARSE3	smac/hal/ssv6006c/ssv6006C_reg.h	12529;"	d
+SET_RG_TURISMO_TRX_IDACAQ_TZ1_COARSE4	smac/hal/ssv6006c/ssv6006C_reg.h	12527;"	d
+SET_RG_TURISMO_TRX_INT_PMU_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	13238;"	d
+SET_RG_TURISMO_TRX_IOT_ADC_CLKSEL	smac/hal/ssv6006c/ssv6006C_reg.h	12630;"	d
+SET_RG_TURISMO_TRX_IOT_ADC_CLK_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	12637;"	d
+SET_RG_TURISMO_TRX_IOT_ADC_CLK_SH_DUTY	smac/hal/ssv6006c/ssv6006C_reg.h	12638;"	d
+SET_RG_TURISMO_TRX_IOT_ADC_CLOAD	smac/hal/ssv6006c/ssv6006C_reg.h	12636;"	d
+SET_RG_TURISMO_TRX_IOT_ADC_DNLEN	smac/hal/ssv6006c/ssv6006C_reg.h	12631;"	d
+SET_RG_TURISMO_TRX_IOT_ADC_EDGE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	13088;"	d
+SET_RG_TURISMO_TRX_IOT_ADC_ICMP	smac/hal/ssv6006c/ssv6006C_reg.h	12634;"	d
+SET_RG_TURISMO_TRX_IOT_ADC_METAEN	smac/hal/ssv6006c/ssv6006C_reg.h	12632;"	d
+SET_RG_TURISMO_TRX_IOT_ADC_TFLAG	smac/hal/ssv6006c/ssv6006C_reg.h	12633;"	d
+SET_RG_TURISMO_TRX_IOT_ADC_VCMI	smac/hal/ssv6006c/ssv6006C_reg.h	12635;"	d
+SET_RG_TURISMO_TRX_IQ_SWAP	smac/hal/ssv6006c/ssv6006C_reg.h	13093;"	d
+SET_RG_TURISMO_TRX_I_INV	smac/hal/ssv6006c/ssv6006C_reg.h	13092;"	d
+SET_RG_TURISMO_TRX_LDO_5G_CP_FC	smac/hal/ssv6006c/ssv6006C_reg.h	12839;"	d
+SET_RG_TURISMO_TRX_LDO_5G_CP_FC_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	12838;"	d
+SET_RG_TURISMO_TRX_LDO_5G_DIV_FC	smac/hal/ssv6006c/ssv6006C_reg.h	12841;"	d
+SET_RG_TURISMO_TRX_LDO_5G_DIV_FC_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	12840;"	d
+SET_RG_TURISMO_TRX_LDO_5G_LO_FC	smac/hal/ssv6006c/ssv6006C_reg.h	12843;"	d
+SET_RG_TURISMO_TRX_LDO_5G_LO_FC_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	12842;"	d
+SET_RG_TURISMO_TRX_LDO_5G_VCO_FC	smac/hal/ssv6006c/ssv6006C_reg.h	12845;"	d
+SET_RG_TURISMO_TRX_LDO_5G_VCO_FC_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	12844;"	d
+SET_RG_TURISMO_TRX_LDO_5G_VCO_RCF	smac/hal/ssv6006c/ssv6006C_reg.h	12846;"	d
+SET_RG_TURISMO_TRX_LDO_CP_FC	smac/hal/ssv6006c/ssv6006C_reg.h	12314;"	d
+SET_RG_TURISMO_TRX_LDO_CP_FC_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	12313;"	d
+SET_RG_TURISMO_TRX_LDO_DIV_FC	smac/hal/ssv6006c/ssv6006C_reg.h	12316;"	d
+SET_RG_TURISMO_TRX_LDO_DIV_FC_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	12315;"	d
+SET_RG_TURISMO_TRX_LDO_LEVEL_AFE	smac/hal/ssv6006c/ssv6006C_reg.h	12045;"	d
+SET_RG_TURISMO_TRX_LDO_LEVEL_EFUSE	smac/hal/ssv6006c/ssv6006C_reg.h	13213;"	d
+SET_RG_TURISMO_TRX_LDO_LEVEL_RX_FE	smac/hal/ssv6006c/ssv6006C_reg.h	12043;"	d
+SET_RG_TURISMO_TRX_LDO_LO_FC	smac/hal/ssv6006c/ssv6006C_reg.h	12318;"	d
+SET_RG_TURISMO_TRX_LDO_LO_FC_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	12317;"	d
+SET_RG_TURISMO_TRX_LDO_VCO_FC	smac/hal/ssv6006c/ssv6006C_reg.h	12320;"	d
+SET_RG_TURISMO_TRX_LDO_VCO_FC_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	12319;"	d
+SET_RG_TURISMO_TRX_LDO_VCO_RCF	smac/hal/ssv6006c/ssv6006C_reg.h	12321;"	d
+SET_RG_TURISMO_TRX_LOAD_RFTABLE_RDY	smac/hal/ssv6006c/ssv6006C_reg.h	13205;"	d
+SET_RG_TURISMO_TRX_LO_UP_CH	smac/hal/ssv6006c/ssv6006C_reg.h	13080;"	d
+SET_RG_TURISMO_TRX_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	11976;"	d
+SET_RG_TURISMO_TRX_MODE_BY_HS_3WIRE	smac/hal/ssv6006c/ssv6006C_reg.h	13179;"	d
+SET_RG_TURISMO_TRX_MODE_LATCH_LMT	smac/hal/ssv6006c/ssv6006C_reg.h	13327;"	d
+SET_RG_TURISMO_TRX_MODE_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11971;"	d
+SET_RG_TURISMO_TRX_NFRAC_DELTA	smac/hal/ssv6006c/ssv6006C_reg.h	13078;"	d
+SET_RG_TURISMO_TRX_PAD_MUX_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	13326;"	d
+SET_RG_TURISMO_TRX_PGAG	smac/hal/ssv6006c/ssv6006C_reg.h	11979;"	d
+SET_RG_TURISMO_TRX_PGAG_DPDCAL	smac/hal/ssv6006c/ssv6006C_reg.h	12628;"	d
+SET_RG_TURISMO_TRX_PGAG_RCCAL	smac/hal/ssv6006c/ssv6006C_reg.h	12621;"	d
+SET_RG_TURISMO_TRX_PGAG_RXIQCAL	smac/hal/ssv6006c/ssv6006C_reg.h	12625;"	d
+SET_RG_TURISMO_TRX_PGAG_TXCAL	smac/hal/ssv6006c/ssv6006C_reg.h	12622;"	d
+SET_RG_TURISMO_TRX_PHASE_17P5M	smac/hal/ssv6006c/ssv6006C_reg.h	13143;"	d
+SET_RG_TURISMO_TRX_PHASE_1M	smac/hal/ssv6006c/ssv6006C_reg.h	13146;"	d
+SET_RG_TURISMO_TRX_PHASE_2P5M	smac/hal/ssv6006c/ssv6006C_reg.h	13144;"	d
+SET_RG_TURISMO_TRX_PHASE_35M	smac/hal/ssv6006c/ssv6006C_reg.h	13148;"	d
+SET_RG_TURISMO_TRX_PHASE_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	13128;"	d
+SET_RG_TURISMO_TRX_PHASE_PADPD	smac/hal/ssv6006c/ssv6006C_reg.h	13147;"	d
+SET_RG_TURISMO_TRX_PHASE_RXIQ_1M	smac/hal/ssv6006c/ssv6006C_reg.h	13145;"	d
+SET_RG_TURISMO_TRX_PHASE_STEP_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	13127;"	d
+SET_RG_TURISMO_TRX_PHY_RST_N	smac/hal/ssv6006c/ssv6006C_reg.h	13252;"	d
+SET_RG_TURISMO_TRX_PMU_ENTER_SLEEP_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	13236;"	d
+SET_RG_TURISMO_TRX_PRE_DC_AUTO	smac/hal/ssv6006c/ssv6006C_reg.h	13165;"	d
+SET_RG_TURISMO_TRX_PRE_DC_POLA_INV	smac/hal/ssv6006c/ssv6006C_reg.h	13163;"	d
+SET_RG_TURISMO_TRX_PROC_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	13162;"	d
+SET_RG_TURISMO_TRX_Q_INV	smac/hal/ssv6006c/ssv6006C_reg.h	13091;"	d
+SET_RG_TURISMO_TRX_RAM_00	smac/hal/ssv6006c/ssv6006C_reg.h	13330;"	d
+SET_RG_TURISMO_TRX_RAM_01	smac/hal/ssv6006c/ssv6006C_reg.h	13331;"	d
+SET_RG_TURISMO_TRX_RAM_02	smac/hal/ssv6006c/ssv6006C_reg.h	13332;"	d
+SET_RG_TURISMO_TRX_RAM_03	smac/hal/ssv6006c/ssv6006C_reg.h	13333;"	d
+SET_RG_TURISMO_TRX_RAM_04	smac/hal/ssv6006c/ssv6006C_reg.h	13334;"	d
+SET_RG_TURISMO_TRX_RAM_05	smac/hal/ssv6006c/ssv6006C_reg.h	13335;"	d
+SET_RG_TURISMO_TRX_RAM_06	smac/hal/ssv6006c/ssv6006C_reg.h	13336;"	d
+SET_RG_TURISMO_TRX_RAM_07	smac/hal/ssv6006c/ssv6006C_reg.h	13337;"	d
+SET_RG_TURISMO_TRX_RAM_08	smac/hal/ssv6006c/ssv6006C_reg.h	13338;"	d
+SET_RG_TURISMO_TRX_RAM_09	smac/hal/ssv6006c/ssv6006C_reg.h	13339;"	d
+SET_RG_TURISMO_TRX_RAM_10	smac/hal/ssv6006c/ssv6006C_reg.h	13340;"	d
+SET_RG_TURISMO_TRX_RAM_11	smac/hal/ssv6006c/ssv6006C_reg.h	13341;"	d
+SET_RG_TURISMO_TRX_RAM_12	smac/hal/ssv6006c/ssv6006C_reg.h	13342;"	d
+SET_RG_TURISMO_TRX_RAM_13	smac/hal/ssv6006c/ssv6006C_reg.h	13343;"	d
+SET_RG_TURISMO_TRX_RAM_14	smac/hal/ssv6006c/ssv6006C_reg.h	13344;"	d
+SET_RG_TURISMO_TRX_RAM_15	smac/hal/ssv6006c/ssv6006C_reg.h	13345;"	d
+SET_RG_TURISMO_TRX_RAM_16	smac/hal/ssv6006c/ssv6006C_reg.h	13346;"	d
+SET_RG_TURISMO_TRX_RAM_17	smac/hal/ssv6006c/ssv6006C_reg.h	13347;"	d
+SET_RG_TURISMO_TRX_RAM_18	smac/hal/ssv6006c/ssv6006C_reg.h	13348;"	d
+SET_RG_TURISMO_TRX_RAM_19	smac/hal/ssv6006c/ssv6006C_reg.h	13349;"	d
+SET_RG_TURISMO_TRX_RAM_20	smac/hal/ssv6006c/ssv6006C_reg.h	13350;"	d
+SET_RG_TURISMO_TRX_RAM_21	smac/hal/ssv6006c/ssv6006C_reg.h	13351;"	d
+SET_RG_TURISMO_TRX_RAM_22	smac/hal/ssv6006c/ssv6006C_reg.h	13352;"	d
+SET_RG_TURISMO_TRX_RAM_23	smac/hal/ssv6006c/ssv6006C_reg.h	13353;"	d
+SET_RG_TURISMO_TRX_RAM_24	smac/hal/ssv6006c/ssv6006C_reg.h	13354;"	d
+SET_RG_TURISMO_TRX_RAM_25	smac/hal/ssv6006c/ssv6006C_reg.h	13355;"	d
+SET_RG_TURISMO_TRX_RAM_26	smac/hal/ssv6006c/ssv6006C_reg.h	13356;"	d
+SET_RG_TURISMO_TRX_RAM_27	smac/hal/ssv6006c/ssv6006C_reg.h	13357;"	d
+SET_RG_TURISMO_TRX_RAM_28	smac/hal/ssv6006c/ssv6006C_reg.h	13358;"	d
+SET_RG_TURISMO_TRX_RAM_29	smac/hal/ssv6006c/ssv6006C_reg.h	13359;"	d
+SET_RG_TURISMO_TRX_RAM_30	smac/hal/ssv6006c/ssv6006C_reg.h	13360;"	d
+SET_RG_TURISMO_TRX_RAM_31	smac/hal/ssv6006c/ssv6006C_reg.h	13361;"	d
+SET_RG_TURISMO_TRX_RCCAL_POLAR_INV	smac/hal/ssv6006c/ssv6006C_reg.h	13155;"	d
+SET_RG_TURISMO_TRX_RFG	smac/hal/ssv6006c/ssv6006C_reg.h	11978;"	d
+SET_RG_TURISMO_TRX_RFG_DPDCAL	smac/hal/ssv6006c/ssv6006C_reg.h	12627;"	d
+SET_RG_TURISMO_TRX_RFG_RXIQCAL	smac/hal/ssv6006c/ssv6006C_reg.h	12624;"	d
+SET_RG_TURISMO_TRX_RF_PHY_MODE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	13324;"	d
+SET_RG_TURISMO_TRX_RF_PHY_MODE_WIFI_MAC	smac/hal/ssv6006c/ssv6006C_reg.h	13325;"	d
+SET_RG_TURISMO_TRX_RSSI_CLOCK_GATING	smac/hal/ssv6006c/ssv6006C_reg.h	12099;"	d
+SET_RG_TURISMO_TRX_RSSI_EDGE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	13089;"	d
+SET_RG_TURISMO_TRX_RTC_CAL_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	13226;"	d
+SET_RG_TURISMO_TRX_RTC_CAL_TARGET_COUNT	smac/hal/ssv6006c/ssv6006C_reg.h	13224;"	d
+SET_RG_TURISMO_TRX_RTC_EN	smac/hal/ssv6006c/ssv6006C_reg.h	13241;"	d
+SET_RG_TURISMO_TRX_RTC_INT_ALARM_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	13244;"	d
+SET_RG_TURISMO_TRX_RTC_INT_SEC_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	13243;"	d
+SET_RG_TURISMO_TRX_RTC_OFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	13223;"	d
+SET_RG_TURISMO_TRX_RTC_OSC_RES_SW_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	13225;"	d
+SET_RG_TURISMO_TRX_RTC_OSC_RES_SW_MANUAL_EN	smac/hal/ssv6006c/ssv6006C_reg.h	13228;"	d
+SET_RG_TURISMO_TRX_RTC_RS1	smac/hal/ssv6006c/ssv6006C_reg.h	13218;"	d
+SET_RG_TURISMO_TRX_RTC_RS2	smac/hal/ssv6006c/ssv6006C_reg.h	13219;"	d
+SET_RG_TURISMO_TRX_RTC_SEC_ALARM_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	13249;"	d
+SET_RG_TURISMO_TRX_RTC_SEC_START_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	13248;"	d
+SET_RG_TURISMO_TRX_RXIQ_NOSHRK	smac/hal/ssv6006c/ssv6006C_reg.h	13085;"	d
+SET_RG_TURISMO_TRX_RXRF_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	12604;"	d
+SET_RG_TURISMO_TRX_RXRF_R2T_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	12613;"	d
+SET_RG_TURISMO_TRX_RXRF_T2R_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	12609;"	d
+SET_RG_TURISMO_TRX_RX_ABBOUT_TRI_STATE	smac/hal/ssv6006c/ssv6006C_reg.h	12035;"	d
+SET_RG_TURISMO_TRX_RX_ADCRSSI_CLKSEL	smac/hal/ssv6006c/ssv6006C_reg.h	12098;"	d
+SET_RG_TURISMO_TRX_RX_ADCRSSI_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	12096;"	d
+SET_RG_TURISMO_TRX_RX_ADC_CLKSEL	smac/hal/ssv6006c/ssv6006C_reg.h	12232;"	d
+SET_RG_TURISMO_TRX_RX_ADC_DNLEN	smac/hal/ssv6006c/ssv6006C_reg.h	12233;"	d
+SET_RG_TURISMO_TRX_RX_ADC_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11997;"	d
+SET_RG_TURISMO_TRX_RX_ADC_METAEN	smac/hal/ssv6006c/ssv6006C_reg.h	12234;"	d
+SET_RG_TURISMO_TRX_RX_ADC_TFLAG	smac/hal/ssv6006c/ssv6006C_reg.h	12235;"	d
+SET_RG_TURISMO_TRX_RX_ADC_TSEL	smac/hal/ssv6006c/ssv6006C_reg.h	12236;"	d
+SET_RG_TURISMO_TRX_RX_AGC	smac/hal/ssv6006c/ssv6006C_reg.h	11975;"	d
+SET_RG_TURISMO_TRX_RX_DC_POLAR_INV	smac/hal/ssv6006c/ssv6006C_reg.h	13154;"	d
+SET_RG_TURISMO_TRX_RX_DC_RESOLUTION	smac/hal/ssv6006c/ssv6006C_reg.h	13156;"	d
+SET_RG_TURISMO_TRX_RX_DIV2_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11989;"	d
+SET_RG_TURISMO_TRX_RX_FILTER_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11995;"	d
+SET_RG_TURISMO_TRX_RX_GAIN_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11972;"	d
+SET_RG_TURISMO_TRX_RX_IDACA_COARSE_PMOS_ON	smac/hal/ssv6006c/ssv6006C_reg.h	12100;"	d
+SET_RG_TURISMO_TRX_RX_IQCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	12619;"	d
+SET_RG_TURISMO_TRX_RX_IQCAL_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	12024;"	d
+SET_RG_TURISMO_TRX_RX_IQ_ALPHA	smac/hal/ssv6006c/ssv6006C_reg.h	13082;"	d
+SET_RG_TURISMO_TRX_RX_IQ_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	13084;"	d
+SET_RG_TURISMO_TRX_RX_IQ_THETA	smac/hal/ssv6006c/ssv6006C_reg.h	13083;"	d
+SET_RG_TURISMO_TRX_RX_LNA_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11985;"	d
+SET_RG_TURISMO_TRX_RX_LNA_SETTLE	smac/hal/ssv6006c/ssv6006C_reg.h	12109;"	d
+SET_RG_TURISMO_TRX_RX_LNA_TRI_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	12108;"	d
+SET_RG_TURISMO_TRX_RX_LOBUF_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11991;"	d
+SET_RG_TURISMO_TRX_RX_MIXER_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11987;"	d
+SET_RG_TURISMO_TRX_RX_N_RCCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	12620;"	d
+SET_RG_TURISMO_TRX_RX_PRE_DC_RESOLUTION	smac/hal/ssv6006c/ssv6006C_reg.h	13164;"	d
+SET_RG_TURISMO_TRX_RX_RCCAL_40M_TARG	smac/hal/ssv6006c/ssv6006C_reg.h	13157;"	d
+SET_RG_TURISMO_TRX_RX_RCCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	12616;"	d
+SET_RG_TURISMO_TRX_RX_RCCAL_TARG	smac/hal/ssv6006c/ssv6006C_reg.h	13153;"	d
+SET_RG_TURISMO_TRX_RX_REC_LPFCORNER	smac/hal/ssv6006c/ssv6006C_reg.h	12097;"	d
+SET_RG_TURISMO_TRX_RX_RSSIADC_TH	smac/hal/ssv6006c/ssv6006C_reg.h	13086;"	d
+SET_RG_TURISMO_TRX_RX_RSSI_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11999;"	d
+SET_RG_TURISMO_TRX_RX_SCALOAD_STEP0	smac/hal/ssv6006c/ssv6006C_reg.h	13064;"	d
+SET_RG_TURISMO_TRX_RX_SCALOAD_STEP1	smac/hal/ssv6006c/ssv6006C_reg.h	13065;"	d
+SET_RG_TURISMO_TRX_RX_SCALOAD_STEP2	smac/hal/ssv6006c/ssv6006C_reg.h	13066;"	d
+SET_RG_TURISMO_TRX_RX_SCALOAD_STEP3	smac/hal/ssv6006c/ssv6006C_reg.h	13067;"	d
+SET_RG_TURISMO_TRX_RX_SCALOAD_STEP4	smac/hal/ssv6006c/ssv6006C_reg.h	13068;"	d
+SET_RG_TURISMO_TRX_RX_SCALOAD_STEP5	smac/hal/ssv6006c/ssv6006C_reg.h	13069;"	d
+SET_RG_TURISMO_TRX_RX_SCALOAD_STEP6	smac/hal/ssv6006c/ssv6006C_reg.h	13070;"	d
+SET_RG_TURISMO_TRX_RX_SCAMA_STEP0	smac/hal/ssv6006c/ssv6006C_reg.h	13057;"	d
+SET_RG_TURISMO_TRX_RX_SCAMA_STEP1	smac/hal/ssv6006c/ssv6006C_reg.h	13058;"	d
+SET_RG_TURISMO_TRX_RX_SCAMA_STEP2	smac/hal/ssv6006c/ssv6006C_reg.h	13059;"	d
+SET_RG_TURISMO_TRX_RX_SCAMA_STEP3	smac/hal/ssv6006c/ssv6006C_reg.h	13060;"	d
+SET_RG_TURISMO_TRX_RX_SCAMA_STEP4	smac/hal/ssv6006c/ssv6006C_reg.h	13061;"	d
+SET_RG_TURISMO_TRX_RX_SCAMA_STEP5	smac/hal/ssv6006c/ssv6006C_reg.h	13062;"	d
+SET_RG_TURISMO_TRX_RX_SCAMA_STEP6	smac/hal/ssv6006c/ssv6006C_reg.h	13063;"	d
+SET_RG_TURISMO_TRX_RX_SQDC	smac/hal/ssv6006c/ssv6006C_reg.h	12042;"	d
+SET_RG_TURISMO_TRX_RX_TZ_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11993;"	d
+SET_RG_TURISMO_TRX_RX_TZ_OUT_TRISTATE	smac/hal/ssv6006c/ssv6006C_reg.h	12021;"	d
+SET_RG_TURISMO_TRX_RX_TZ_OUT_TRISTATE_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	12020;"	d
+SET_RG_TURISMO_TRX_SARADC_5G_TSSI	smac/hal/ssv6006c/ssv6006C_reg.h	12243;"	d
+SET_RG_TURISMO_TRX_SARADC_THERMAL	smac/hal/ssv6006c/ssv6006C_reg.h	12246;"	d
+SET_RG_TURISMO_TRX_SARADC_TSSI	smac/hal/ssv6006c/ssv6006C_reg.h	12247;"	d
+SET_RG_TURISMO_TRX_SARADC_VRSEL	smac/hal/ssv6006c/ssv6006C_reg.h	12244;"	d
+SET_RG_TURISMO_TRX_SEC_CNT_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	13240;"	d
+SET_RG_TURISMO_TRX_SEL_DPLL_CLK	smac/hal/ssv6006c/ssv6006C_reg.h	13227;"	d
+SET_RG_TURISMO_TRX_SIGN_SWAP	smac/hal/ssv6006c/ssv6006C_reg.h	13094;"	d
+SET_RG_TURISMO_TRX_SLEEP_METHOD	smac/hal/ssv6006c/ssv6006C_reg.h	13237;"	d
+SET_RG_TURISMO_TRX_SLEEP_WAKE_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	13239;"	d
+SET_RG_TURISMO_TRX_SPECTRUM_BW	smac/hal/ssv6006c/ssv6006C_reg.h	13130;"	d
+SET_RG_TURISMO_TRX_SPECTRUM_EN	smac/hal/ssv6006c/ssv6006C_reg.h	13131;"	d
+SET_RG_TURISMO_TRX_SPECTRUM_LO_FIX	smac/hal/ssv6006c/ssv6006C_reg.h	13159;"	d
+SET_RG_TURISMO_TRX_SPECTRUM_PWR_UPDATE	smac/hal/ssv6006c/ssv6006C_reg.h	13160;"	d
+SET_RG_TURISMO_TRX_SPIS_MISO_DS	smac/hal/ssv6006c/ssv6006C_reg.h	13272;"	d
+SET_RG_TURISMO_TRX_SUB_DC	smac/hal/ssv6006c/ssv6006C_reg.h	13087;"	d
+SET_RG_TURISMO_TRX_SX5GB_AAC_ACCUMH	smac/hal/ssv6006c/ssv6006C_reg.h	12912;"	d
+SET_RG_TURISMO_TRX_SX5GB_AAC_ACCUML	smac/hal/ssv6006c/ssv6006C_reg.h	12913;"	d
+SET_RG_TURISMO_TRX_SX5GB_AAC_EN	smac/hal/ssv6006c/ssv6006C_reg.h	12917;"	d
+SET_RG_TURISMO_TRX_SX5GB_AAC_EN_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	12916;"	d
+SET_RG_TURISMO_TRX_SX5GB_AAC_EVA	smac/hal/ssv6006c/ssv6006C_reg.h	12919;"	d
+SET_RG_TURISMO_TRX_SX5GB_AAC_EVA_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	12918;"	d
+SET_RG_TURISMO_TRX_SX5GB_AAC_EVA_TS	smac/hal/ssv6006c/ssv6006C_reg.h	12915;"	d
+SET_RG_TURISMO_TRX_SX5GB_AAC_INIT	smac/hal/ssv6006c/ssv6006C_reg.h	12914;"	d
+SET_RG_TURISMO_TRX_SX5GB_AAC_TEST_EN	smac/hal/ssv6006c/ssv6006C_reg.h	12925;"	d
+SET_RG_TURISMO_TRX_SX5GB_AAC_TEST_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	12926;"	d
+SET_RG_TURISMO_TRX_SX5GB_CAL_INIT	smac/hal/ssv6006c/ssv6006C_reg.h	12825;"	d
+SET_RG_TURISMO_TRX_SX5GB_CHANNEL	smac/hal/ssv6006c/ssv6006C_reg.h	12795;"	d
+SET_RG_TURISMO_TRX_SX5GB_CP_IOST	smac/hal/ssv6006c/ssv6006C_reg.h	12851;"	d
+SET_RG_TURISMO_TRX_SX5GB_CP_IOST_POL	smac/hal/ssv6006c/ssv6006C_reg.h	12850;"	d
+SET_RG_TURISMO_TRX_SX5GB_CP_ISEL	smac/hal/ssv6006c/ssv6006C_reg.h	12847;"	d
+SET_RG_TURISMO_TRX_SX5GB_CP_ISEL50U	smac/hal/ssv6006c/ssv6006C_reg.h	12848;"	d
+SET_RG_TURISMO_TRX_SX5GB_CP_KP_DOUB	smac/hal/ssv6006c/ssv6006C_reg.h	12849;"	d
+SET_RG_TURISMO_TRX_SX5GB_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	13017;"	d
+SET_RG_TURISMO_TRX_SX5GB_DITHER_WEIGHT	smac/hal/ssv6006c/ssv6006C_reg.h	12900;"	d
+SET_RG_TURISMO_TRX_SX5GB_DIV_DMYBUF_EN	smac/hal/ssv6006c/ssv6006C_reg.h	12896;"	d
+SET_RG_TURISMO_TRX_SX5GB_DIV_PREVDD	smac/hal/ssv6006c/ssv6006C_reg.h	12892;"	d
+SET_RG_TURISMO_TRX_SX5GB_DIV_PSCVDD	smac/hal/ssv6006c/ssv6006C_reg.h	12893;"	d
+SET_RG_TURISMO_TRX_SX5GB_DIV_RST_H	smac/hal/ssv6006c/ssv6006C_reg.h	12894;"	d
+SET_RG_TURISMO_TRX_SX5GB_DIV_SDM_EDGE	smac/hal/ssv6006c/ssv6006C_reg.h	12895;"	d
+SET_RG_TURISMO_TRX_SX5GB_LDO_CP_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	12683;"	d
+SET_RG_TURISMO_TRX_SX5GB_LDO_DIV_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	12688;"	d
+SET_RG_TURISMO_TRX_SX5GB_LDO_FCOFFT	smac/hal/ssv6006c/ssv6006C_reg.h	12837;"	d
+SET_RG_TURISMO_TRX_SX5GB_LDO_LO_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	12685;"	d
+SET_RG_TURISMO_TRX_SX5GB_LDO_VCO_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	12687;"	d
+SET_RG_TURISMO_TRX_SX5GB_LO_TIMES	smac/hal/ssv6006c/ssv6006C_reg.h	12794;"	d
+SET_RG_TURISMO_TRX_SX5GB_LPF_C1	smac/hal/ssv6006c/ssv6006C_reg.h	12861;"	d
+SET_RG_TURISMO_TRX_SX5GB_LPF_C2	smac/hal/ssv6006c/ssv6006C_reg.h	12862;"	d
+SET_RG_TURISMO_TRX_SX5GB_LPF_C3	smac/hal/ssv6006c/ssv6006C_reg.h	12863;"	d
+SET_RG_TURISMO_TRX_SX5GB_LPF_R2	smac/hal/ssv6006c/ssv6006C_reg.h	12864;"	d
+SET_RG_TURISMO_TRX_SX5GB_LPF_R3	smac/hal/ssv6006c/ssv6006C_reg.h	12865;"	d
+SET_RG_TURISMO_TRX_SX5GB_LPF_VTUNE_TEST	smac/hal/ssv6006c/ssv6006C_reg.h	12874;"	d
+SET_RG_TURISMO_TRX_SX5GB_MIXAAC_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	12822;"	d
+SET_RG_TURISMO_TRX_SX5GB_MIXAAC_TAR	smac/hal/ssv6006c/ssv6006C_reg.h	12927;"	d
+SET_RG_TURISMO_TRX_SX5GB_MOD_ORDER	smac/hal/ssv6006c/ssv6006C_reg.h	12899;"	d
+SET_RG_TURISMO_TRX_SX5GB_PFD_DIV_EDGE	smac/hal/ssv6006c/ssv6006C_reg.h	12860;"	d
+SET_RG_TURISMO_TRX_SX5GB_PFD_REF_EDGE	smac/hal/ssv6006c/ssv6006C_reg.h	12859;"	d
+SET_RG_TURISMO_TRX_SX5GB_PFD_RST	smac/hal/ssv6006c/ssv6006C_reg.h	12805;"	d
+SET_RG_TURISMO_TRX_SX5GB_PFD_RST_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	12804;"	d
+SET_RG_TURISMO_TRX_SX5GB_PFD_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	12852;"	d
+SET_RG_TURISMO_TRX_SX5GB_PFD_SET	smac/hal/ssv6006c/ssv6006C_reg.h	12853;"	d
+SET_RG_TURISMO_TRX_SX5GB_PFD_SET1	smac/hal/ssv6006c/ssv6006C_reg.h	12854;"	d
+SET_RG_TURISMO_TRX_SX5GB_PFD_SET2	smac/hal/ssv6006c/ssv6006C_reg.h	12855;"	d
+SET_RG_TURISMO_TRX_SX5GB_PFD_TLSEL	smac/hal/ssv6006c/ssv6006C_reg.h	12858;"	d
+SET_RG_TURISMO_TRX_SX5GB_PFD_TRDN	smac/hal/ssv6006c/ssv6006C_reg.h	12857;"	d
+SET_RG_TURISMO_TRX_SX5GB_PFD_TRUP	smac/hal/ssv6006c/ssv6006C_reg.h	12856;"	d
+SET_RG_TURISMO_TRX_SX5GB_REPAAC_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	12823;"	d
+SET_RG_TURISMO_TRX_SX5GB_REPAAC_TAR	smac/hal/ssv6006c/ssv6006C_reg.h	12930;"	d
+SET_RG_TURISMO_TRX_SX5GB_RFCH_MAP_EN	smac/hal/ssv6006c/ssv6006C_reg.h	12793;"	d
+SET_RG_TURISMO_TRX_SX5GB_RFCTRL_CH_10_8	smac/hal/ssv6006c/ssv6006C_reg.h	12792;"	d
+SET_RG_TURISMO_TRX_SX5GB_RFCTRL_CH_7_0	smac/hal/ssv6006c/ssv6006C_reg.h	12791;"	d
+SET_RG_TURISMO_TRX_SX5GB_RFCTRL_F	smac/hal/ssv6006c/ssv6006C_reg.h	12790;"	d
+SET_RG_TURISMO_TRX_SX5GB_SBCAL_2ND_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	12819;"	d
+SET_RG_TURISMO_TRX_SX5GB_SBCAL_AW	smac/hal/ssv6006c/ssv6006C_reg.h	12820;"	d
+SET_RG_TURISMO_TRX_SX5GB_SBCAL_CT	smac/hal/ssv6006c/ssv6006C_reg.h	12904;"	d
+SET_RG_TURISMO_TRX_SX5GB_SBCAL_DIFFMIN	smac/hal/ssv6006c/ssv6006C_reg.h	12906;"	d
+SET_RG_TURISMO_TRX_SX5GB_SBCAL_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	12818;"	d
+SET_RG_TURISMO_TRX_SX5GB_SBCAL_NTARG	smac/hal/ssv6006c/ssv6006C_reg.h	12908;"	d
+SET_RG_TURISMO_TRX_SX5GB_SBCAL_NTARG_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	12907;"	d
+SET_RG_TURISMO_TRX_SX5GB_SBCAL_WT	smac/hal/ssv6006c/ssv6006C_reg.h	12905;"	d
+SET_RG_TURISMO_TRX_SX5GB_SUB_C0P5_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	12903;"	d
+SET_RG_TURISMO_TRX_SX5GB_SUB_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	12902;"	d
+SET_RG_TURISMO_TRX_SX5GB_SUB_SEL_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	12901;"	d
+SET_RG_TURISMO_TRX_SX5GB_TTL_ACCUM	smac/hal/ssv6006c/ssv6006C_reg.h	12869;"	d
+SET_RG_TURISMO_TRX_SX5GB_TTL_CPT	smac/hal/ssv6006c/ssv6006C_reg.h	12868;"	d
+SET_RG_TURISMO_TRX_SX5GB_TTL_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	12824;"	d
+SET_RG_TURISMO_TRX_SX5GB_TTL_FPT	smac/hal/ssv6006c/ssv6006C_reg.h	12867;"	d
+SET_RG_TURISMO_TRX_SX5GB_TTL_INIT	smac/hal/ssv6006c/ssv6006C_reg.h	12866;"	d
+SET_RG_TURISMO_TRX_SX5GB_TTL_SUB	smac/hal/ssv6006c/ssv6006C_reg.h	12870;"	d
+SET_RG_TURISMO_TRX_SX5GB_TTL_SUB_INV	smac/hal/ssv6006c/ssv6006C_reg.h	12871;"	d
+SET_RG_TURISMO_TRX_SX5GB_TTL_VH	smac/hal/ssv6006c/ssv6006C_reg.h	12872;"	d
+SET_RG_TURISMO_TRX_SX5GB_TTL_VL	smac/hal/ssv6006c/ssv6006C_reg.h	12873;"	d
+SET_RG_TURISMO_TRX_SX5GB_UOP_EN	smac/hal/ssv6006c/ssv6006C_reg.h	12807;"	d
+SET_RG_TURISMO_TRX_SX5GB_UOP_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	12806;"	d
+SET_RG_TURISMO_TRX_SX5GB_VCO_CS_AWH	smac/hal/ssv6006c/ssv6006C_reg.h	12881;"	d
+SET_RG_TURISMO_TRX_SX5GB_VCO_ISEL	smac/hal/ssv6006c/ssv6006C_reg.h	12876;"	d
+SET_RG_TURISMO_TRX_SX5GB_VCO_ISEL_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	12875;"	d
+SET_RG_TURISMO_TRX_SX5GB_VCO_KVDOUB	smac/hal/ssv6006c/ssv6006C_reg.h	12878;"	d
+SET_RG_TURISMO_TRX_SX5GB_VCO_RTAIL_SHIFT	smac/hal/ssv6006c/ssv6006C_reg.h	12880;"	d
+SET_RG_TURISMO_TRX_SX5GB_VCO_VARBSEL	smac/hal/ssv6006c/ssv6006C_reg.h	12879;"	d
+SET_RG_TURISMO_TRX_SX5GB_VCO_VCCBSEL	smac/hal/ssv6006c/ssv6006C_reg.h	12877;"	d
+SET_RG_TURISMO_TRX_SX5GB_VOAAC_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	12821;"	d
+SET_RG_TURISMO_TRX_SX5GB_VOAAC_TAR	smac/hal/ssv6006c/ssv6006C_reg.h	12909;"	d
+SET_RG_TURISMO_TRX_SXMIX_GMSEL	smac/hal/ssv6006c/ssv6006C_reg.h	12888;"	d
+SET_RG_TURISMO_TRX_SXMIX_IBIAS_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	12886;"	d
+SET_RG_TURISMO_TRX_SXMIX_SCA_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	12929;"	d
+SET_RG_TURISMO_TRX_SXMIX_SCA_SEL_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	12928;"	d
+SET_RG_TURISMO_TRX_SXMIX_SWB_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	12887;"	d
+SET_RG_TURISMO_TRX_SXREP_CSSEL	smac/hal/ssv6006c/ssv6006C_reg.h	12890;"	d
+SET_RG_TURISMO_TRX_SXREP_SCA_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	12932;"	d
+SET_RG_TURISMO_TRX_SXREP_SCA_SEL_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	12931;"	d
+SET_RG_TURISMO_TRX_SXREP_SWB_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	12889;"	d
+SET_RG_TURISMO_TRX_SX_5GB_EN	smac/hal/ssv6006c/ssv6006C_reg.h	12797;"	d
+SET_RG_TURISMO_TRX_SX_5GB_EN_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	12796;"	d
+SET_RG_TURISMO_TRX_SX_AAC_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	12298;"	d
+SET_RG_TURISMO_TRX_SX_BTRX_SIDE	smac/hal/ssv6006c/ssv6006C_reg.h	12328;"	d
+SET_RG_TURISMO_TRX_SX_CAL_INIT	smac/hal/ssv6006c/ssv6006C_reg.h	12300;"	d
+SET_RG_TURISMO_TRX_SX_CHANNEL	smac/hal/ssv6006c/ssv6006C_reg.h	12330;"	d
+SET_RG_TURISMO_TRX_SX_CP_IOST	smac/hal/ssv6006c/ssv6006C_reg.h	12338;"	d
+SET_RG_TURISMO_TRX_SX_CP_IOST_POL	smac/hal/ssv6006c/ssv6006C_reg.h	12337;"	d
+SET_RG_TURISMO_TRX_SX_CP_ISEL50U_BT	smac/hal/ssv6006c/ssv6006C_reg.h	12332;"	d
+SET_RG_TURISMO_TRX_SX_CP_ISEL50U_WF	smac/hal/ssv6006c/ssv6006C_reg.h	12335;"	d
+SET_RG_TURISMO_TRX_SX_CP_ISEL_BT	smac/hal/ssv6006c/ssv6006C_reg.h	12331;"	d
+SET_RG_TURISMO_TRX_SX_CP_ISEL_WF	smac/hal/ssv6006c/ssv6006C_reg.h	12334;"	d
+SET_RG_TURISMO_TRX_SX_CP_KP_DOUB_BT	smac/hal/ssv6006c/ssv6006C_reg.h	12333;"	d
+SET_RG_TURISMO_TRX_SX_CP_KP_DOUB_WF	smac/hal/ssv6006c/ssv6006C_reg.h	12336;"	d
+SET_RG_TURISMO_TRX_SX_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	12600;"	d
+SET_RG_TURISMO_TRX_SX_DITHER_WEIGHT	smac/hal/ssv6006c/ssv6006C_reg.h	12392;"	d
+SET_RG_TURISMO_TRX_SX_DIV_DMYBUF_EN	smac/hal/ssv6006c/ssv6006C_reg.h	12388;"	d
+SET_RG_TURISMO_TRX_SX_DIV_PREVDD	smac/hal/ssv6006c/ssv6006C_reg.h	12384;"	d
+SET_RG_TURISMO_TRX_SX_DIV_PSCVDD	smac/hal/ssv6006c/ssv6006C_reg.h	12385;"	d
+SET_RG_TURISMO_TRX_SX_DIV_RST_H	smac/hal/ssv6006c/ssv6006C_reg.h	12386;"	d
+SET_RG_TURISMO_TRX_SX_DIV_SDM_EDGE	smac/hal/ssv6006c/ssv6006C_reg.h	12387;"	d
+SET_RG_TURISMO_TRX_SX_EN	smac/hal/ssv6006c/ssv6006C_reg.h	12275;"	d
+SET_RG_TURISMO_TRX_SX_EN_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	12274;"	d
+SET_RG_TURISMO_TRX_SX_FREF_DOUB	smac/hal/ssv6006c/ssv6006C_reg.h	12327;"	d
+SET_RG_TURISMO_TRX_SX_LDO_CP_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	12050;"	d
+SET_RG_TURISMO_TRX_SX_LDO_DIV_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	12055;"	d
+SET_RG_TURISMO_TRX_SX_LDO_FCOFFT	smac/hal/ssv6006c/ssv6006C_reg.h	12312;"	d
+SET_RG_TURISMO_TRX_SX_LDO_LO_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	12052;"	d
+SET_RG_TURISMO_TRX_SX_LDO_VCO_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	12054;"	d
+SET_RG_TURISMO_TRX_SX_LO_TIMES	smac/hal/ssv6006c/ssv6006C_reg.h	12329;"	d
+SET_RG_TURISMO_TRX_SX_LPF_C1_BT	smac/hal/ssv6006c/ssv6006C_reg.h	12348;"	d
+SET_RG_TURISMO_TRX_SX_LPF_C1_WF	smac/hal/ssv6006c/ssv6006C_reg.h	12353;"	d
+SET_RG_TURISMO_TRX_SX_LPF_C2_BT	smac/hal/ssv6006c/ssv6006C_reg.h	12349;"	d
+SET_RG_TURISMO_TRX_SX_LPF_C2_WF	smac/hal/ssv6006c/ssv6006C_reg.h	12354;"	d
+SET_RG_TURISMO_TRX_SX_LPF_C3_BT	smac/hal/ssv6006c/ssv6006C_reg.h	12350;"	d
+SET_RG_TURISMO_TRX_SX_LPF_C3_WF	smac/hal/ssv6006c/ssv6006C_reg.h	12355;"	d
+SET_RG_TURISMO_TRX_SX_LPF_R2_BT	smac/hal/ssv6006c/ssv6006C_reg.h	12351;"	d
+SET_RG_TURISMO_TRX_SX_LPF_R2_WF	smac/hal/ssv6006c/ssv6006C_reg.h	12356;"	d
+SET_RG_TURISMO_TRX_SX_LPF_R3_BT	smac/hal/ssv6006c/ssv6006C_reg.h	12352;"	d
+SET_RG_TURISMO_TRX_SX_LPF_R3_WF	smac/hal/ssv6006c/ssv6006C_reg.h	12357;"	d
+SET_RG_TURISMO_TRX_SX_LPF_VTUNE_TEST	smac/hal/ssv6006c/ssv6006C_reg.h	12422;"	d
+SET_RG_TURISMO_TRX_SX_MOD_ORDER	smac/hal/ssv6006c/ssv6006C_reg.h	12391;"	d
+SET_RG_TURISMO_TRX_SX_PFD_DIV_EDGE	smac/hal/ssv6006c/ssv6006C_reg.h	12344;"	d
+SET_RG_TURISMO_TRX_SX_PFD_REF_EDGE	smac/hal/ssv6006c/ssv6006C_reg.h	12343;"	d
+SET_RG_TURISMO_TRX_SX_PFD_RST	smac/hal/ssv6006c/ssv6006C_reg.h	12283;"	d
+SET_RG_TURISMO_TRX_SX_PFD_RST_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	12282;"	d
+SET_RG_TURISMO_TRX_SX_PFD_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	12339;"	d
+SET_RG_TURISMO_TRX_SX_PFD_SET	smac/hal/ssv6006c/ssv6006C_reg.h	12340;"	d
+SET_RG_TURISMO_TRX_SX_PFD_SET1	smac/hal/ssv6006c/ssv6006C_reg.h	12341;"	d
+SET_RG_TURISMO_TRX_SX_PFD_SET2	smac/hal/ssv6006c/ssv6006C_reg.h	12342;"	d
+SET_RG_TURISMO_TRX_SX_PFD_TLSEL	smac/hal/ssv6006c/ssv6006C_reg.h	12347;"	d
+SET_RG_TURISMO_TRX_SX_PFD_TRDN	smac/hal/ssv6006c/ssv6006C_reg.h	12346;"	d
+SET_RG_TURISMO_TRX_SX_PFD_TRUP	smac/hal/ssv6006c/ssv6006C_reg.h	12345;"	d
+SET_RG_TURISMO_TRX_SX_RFCH_MAP_EN	smac/hal/ssv6006c/ssv6006C_reg.h	12325;"	d
+SET_RG_TURISMO_TRX_SX_RFCTRL_CH_10_8	smac/hal/ssv6006c/ssv6006C_reg.h	12324;"	d
+SET_RG_TURISMO_TRX_SX_RFCTRL_CH_7_0	smac/hal/ssv6006c/ssv6006C_reg.h	12323;"	d
+SET_RG_TURISMO_TRX_SX_RFCTRL_F	smac/hal/ssv6006c/ssv6006C_reg.h	12322;"	d
+SET_RG_TURISMO_TRX_SX_SBCAL_AW	smac/hal/ssv6006c/ssv6006C_reg.h	12297;"	d
+SET_RG_TURISMO_TRX_SX_SBCAL_CT	smac/hal/ssv6006c/ssv6006C_reg.h	12396;"	d
+SET_RG_TURISMO_TRX_SX_SBCAL_DIFFMIN	smac/hal/ssv6006c/ssv6006C_reg.h	12398;"	d
+SET_RG_TURISMO_TRX_SX_SBCAL_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	12296;"	d
+SET_RG_TURISMO_TRX_SX_SBCAL_NTARG	smac/hal/ssv6006c/ssv6006C_reg.h	12400;"	d
+SET_RG_TURISMO_TRX_SX_SBCAL_NTARG_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	12399;"	d
+SET_RG_TURISMO_TRX_SX_SBCAL_WT	smac/hal/ssv6006c/ssv6006C_reg.h	12397;"	d
+SET_RG_TURISMO_TRX_SX_SUB_C0P5_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	12395;"	d
+SET_RG_TURISMO_TRX_SX_SUB_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	12394;"	d
+SET_RG_TURISMO_TRX_SX_SUB_SEL_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	12393;"	d
+SET_RG_TURISMO_TRX_SX_TTL_ACCUM	smac/hal/ssv6006c/ssv6006C_reg.h	12417;"	d
+SET_RG_TURISMO_TRX_SX_TTL_CPT	smac/hal/ssv6006c/ssv6006C_reg.h	12416;"	d
+SET_RG_TURISMO_TRX_SX_TTL_DIS	smac/hal/ssv6006c/ssv6006C_reg.h	12299;"	d
+SET_RG_TURISMO_TRX_SX_TTL_FPT	smac/hal/ssv6006c/ssv6006C_reg.h	12415;"	d
+SET_RG_TURISMO_TRX_SX_TTL_INIT	smac/hal/ssv6006c/ssv6006C_reg.h	12414;"	d
+SET_RG_TURISMO_TRX_SX_TTL_SUB	smac/hal/ssv6006c/ssv6006C_reg.h	12418;"	d
+SET_RG_TURISMO_TRX_SX_TTL_SUB_INV	smac/hal/ssv6006c/ssv6006C_reg.h	12419;"	d
+SET_RG_TURISMO_TRX_SX_TTL_VH	smac/hal/ssv6006c/ssv6006C_reg.h	12420;"	d
+SET_RG_TURISMO_TRX_SX_TTL_VL	smac/hal/ssv6006c/ssv6006C_reg.h	12421;"	d
+SET_RG_TURISMO_TRX_SX_UOP_EN	smac/hal/ssv6006c/ssv6006C_reg.h	12285;"	d
+SET_RG_TURISMO_TRX_SX_UOP_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	12284;"	d
+SET_RG_TURISMO_TRX_SX_VCO_CS_AWH	smac/hal/ssv6006c/ssv6006C_reg.h	12369;"	d
+SET_RG_TURISMO_TRX_SX_VCO_ISEL_BT	smac/hal/ssv6006c/ssv6006C_reg.h	12359;"	d
+SET_RG_TURISMO_TRX_SX_VCO_ISEL_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	12358;"	d
+SET_RG_TURISMO_TRX_SX_VCO_ISEL_WF	smac/hal/ssv6006c/ssv6006C_reg.h	12363;"	d
+SET_RG_TURISMO_TRX_SX_VCO_KVDOUB_BT	smac/hal/ssv6006c/ssv6006C_reg.h	12362;"	d
+SET_RG_TURISMO_TRX_SX_VCO_KVDOUB_WF	smac/hal/ssv6006c/ssv6006C_reg.h	12366;"	d
+SET_RG_TURISMO_TRX_SX_VCO_LPM_BT	smac/hal/ssv6006c/ssv6006C_reg.h	12360;"	d
+SET_RG_TURISMO_TRX_SX_VCO_LPM_WF	smac/hal/ssv6006c/ssv6006C_reg.h	12364;"	d
+SET_RG_TURISMO_TRX_SX_VCO_RTAIL_SHIFT	smac/hal/ssv6006c/ssv6006C_reg.h	12368;"	d
+SET_RG_TURISMO_TRX_SX_VCO_RXOB_AW	smac/hal/ssv6006c/ssv6006C_reg.h	12380;"	d
+SET_RG_TURISMO_TRX_SX_VCO_TXOB_AW	smac/hal/ssv6006c/ssv6006C_reg.h	12379;"	d
+SET_RG_TURISMO_TRX_SX_VCO_VARBSEL	smac/hal/ssv6006c/ssv6006C_reg.h	12367;"	d
+SET_RG_TURISMO_TRX_SX_VCO_VCCBSEL_BT	smac/hal/ssv6006c/ssv6006C_reg.h	12361;"	d
+SET_RG_TURISMO_TRX_SX_VCO_VCCBSEL_WF	smac/hal/ssv6006c/ssv6006C_reg.h	12365;"	d
+SET_RG_TURISMO_TRX_SX_XTAL_FREQ	smac/hal/ssv6006c/ssv6006C_reg.h	12326;"	d
+SET_RG_TURISMO_TRX_TONE_GEN_EN	smac/hal/ssv6006c/ssv6006C_reg.h	13103;"	d
+SET_RG_TURISMO_TRX_TONE_SCALE	smac/hal/ssv6006c/ssv6006C_reg.h	13101;"	d
+SET_RG_TURISMO_TRX_TXBTPA_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	12605;"	d
+SET_RG_TURISMO_TRX_TXDAC_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	12601;"	d
+SET_RG_TURISMO_TRX_TXDAC_R2T_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	12610;"	d
+SET_RG_TURISMO_TRX_TXDAC_T2R_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	12606;"	d
+SET_RG_TURISMO_TRX_TXGAIN_PHYCTRL	smac/hal/ssv6006c/ssv6006C_reg.h	11974;"	d
+SET_RG_TURISMO_TRX_TXIQ_NOSHRK	smac/hal/ssv6006c/ssv6006C_reg.h	13098;"	d
+SET_RG_TURISMO_TRX_TXLPF_BYPASS	smac/hal/ssv6006c/ssv6006C_reg.h	12031;"	d
+SET_RG_TURISMO_TRX_TXLPF_GMCELL	smac/hal/ssv6006c/ssv6006C_reg.h	12137;"	d
+SET_RG_TURISMO_TRX_TXMOD_GMCELL	smac/hal/ssv6006c/ssv6006C_reg.h	12136;"	d
+SET_RG_TURISMO_TRX_TXPA_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	12603;"	d
+SET_RG_TURISMO_TRX_TXPA_R2T_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	12612;"	d
+SET_RG_TURISMO_TRX_TXPA_T2R_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	12608;"	d
+SET_RG_TURISMO_TRX_TXPGA_MAIN	smac/hal/ssv6006c/ssv6006C_reg.h	12134;"	d
+SET_RG_TURISMO_TRX_TXPGA_STEER	smac/hal/ssv6006c/ssv6006C_reg.h	12135;"	d
+SET_RG_TURISMO_TRX_TXRF_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	12602;"	d
+SET_RG_TURISMO_TRX_TXRF_R2T_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	12611;"	d
+SET_RG_TURISMO_TRX_TXRF_T2R_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	12607;"	d
+SET_RG_TURISMO_TRX_TX_BT_PA_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	12011;"	d
+SET_RG_TURISMO_TRX_TX_CAPSW_STEP0	smac/hal/ssv6006c/ssv6006C_reg.h	13071;"	d
+SET_RG_TURISMO_TRX_TX_CAPSW_STEP1	smac/hal/ssv6006c/ssv6006C_reg.h	13072;"	d
+SET_RG_TURISMO_TRX_TX_CAPSW_STEP2	smac/hal/ssv6006c/ssv6006C_reg.h	13073;"	d
+SET_RG_TURISMO_TRX_TX_CAPSW_STEP3	smac/hal/ssv6006c/ssv6006C_reg.h	13074;"	d
+SET_RG_TURISMO_TRX_TX_CAPSW_STEP4	smac/hal/ssv6006c/ssv6006C_reg.h	13075;"	d
+SET_RG_TURISMO_TRX_TX_CAPSW_STEP5	smac/hal/ssv6006c/ssv6006C_reg.h	13076;"	d
+SET_RG_TURISMO_TRX_TX_CAPSW_STEP6	smac/hal/ssv6006c/ssv6006C_reg.h	13077;"	d
+SET_RG_TURISMO_TRX_TX_DAC_CAL_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	12018;"	d
+SET_RG_TURISMO_TRX_TX_DAC_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	12005;"	d
+SET_RG_TURISMO_TRX_TX_DAC_TSEL	smac/hal/ssv6006c/ssv6006C_reg.h	12261;"	d
+SET_RG_TURISMO_TRX_TX_DCCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	12617;"	d
+SET_RG_TURISMO_TRX_TX_DIV2_BUF_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	12009;"	d
+SET_RG_TURISMO_TRX_TX_DIV2_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	12007;"	d
+SET_RG_TURISMO_TRX_TX_DPDGM_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	12101;"	d
+SET_RG_TURISMO_TRX_TX_DPD_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	12102;"	d
+SET_RG_TURISMO_TRX_TX_DPD_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	12026;"	d
+SET_RG_TURISMO_TRX_TX_EN_VOLTAGE_IN	smac/hal/ssv6006c/ssv6006C_reg.h	12032;"	d
+SET_RG_TURISMO_TRX_TX_FREQ_OFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	13100;"	d
+SET_RG_TURISMO_TRX_TX_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	11982;"	d
+SET_RG_TURISMO_TRX_TX_GAIN_DPDCAL	smac/hal/ssv6006c/ssv6006C_reg.h	12629;"	d
+SET_RG_TURISMO_TRX_TX_GAIN_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11973;"	d
+SET_RG_TURISMO_TRX_TX_GAIN_RXIQCAL	smac/hal/ssv6006c/ssv6006C_reg.h	12626;"	d
+SET_RG_TURISMO_TRX_TX_GAIN_TXCAL	smac/hal/ssv6006c/ssv6006C_reg.h	12623;"	d
+SET_RG_TURISMO_TRX_TX_IQCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	12618;"	d
+SET_RG_TURISMO_TRX_TX_IQCAL_TIME	smac/hal/ssv6006c/ssv6006C_reg.h	13099;"	d
+SET_RG_TURISMO_TRX_TX_IQ_ALPHA	smac/hal/ssv6006c/ssv6006C_reg.h	13095;"	d
+SET_RG_TURISMO_TRX_TX_IQ_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	13097;"	d
+SET_RG_TURISMO_TRX_TX_IQ_THETA	smac/hal/ssv6006c/ssv6006C_reg.h	13096;"	d
+SET_RG_TURISMO_TRX_TX_MOD_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	12003;"	d
+SET_RG_TURISMO_TRX_TX_PA_LDO_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	12047;"	d
+SET_RG_TURISMO_TRX_TX_PA_LDO_SEL_RES	smac/hal/ssv6006c/ssv6006C_reg.h	12120;"	d
+SET_RG_TURISMO_TRX_TX_PA_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	12001;"	d
+SET_RG_TURISMO_TRX_TX_SELF_MIXER_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	12022;"	d
+SET_RG_TURISMO_TRX_TX_TRSW_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	11983;"	d
+SET_RG_TURISMO_TRX_TX_TSSI_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	12103;"	d
+SET_RG_TURISMO_TRX_TX_TSSI_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	12104;"	d
+SET_RG_TURISMO_TRX_TX_TSSI_TEST	smac/hal/ssv6006c/ssv6006C_reg.h	12105;"	d
+SET_RG_TURISMO_TRX_TX_TSSI_TESTMODE	smac/hal/ssv6006c/ssv6006C_reg.h	12106;"	d
+SET_RG_TURISMO_TRX_TX_UP8X_MAN_EN	smac/hal/ssv6006c/ssv6006C_reg.h	13104;"	d
+SET_RG_TURISMO_TRX_TX_VTOI_CURRENT	smac/hal/ssv6006c/ssv6006C_reg.h	12140;"	d
+SET_RG_TURISMO_TRX_TX_VTOI_FS	smac/hal/ssv6006c/ssv6006C_reg.h	12143;"	d
+SET_RG_TURISMO_TRX_TX_VTOI_GM	smac/hal/ssv6006c/ssv6006C_reg.h	12141;"	d
+SET_RG_TURISMO_TRX_TX_VTOI_OPTION	smac/hal/ssv6006c/ssv6006C_reg.h	12142;"	d
+SET_RG_TURISMO_TRX_VO5GB_AAC_IMAX	smac/hal/ssv6006c/ssv6006C_reg.h	12911;"	d
+SET_RG_TURISMO_TRX_VO5GB_AAC_IOST	smac/hal/ssv6006c/ssv6006C_reg.h	12910;"	d
+SET_RG_TURISMO_TRX_VOBF_CAPIMB	smac/hal/ssv6006c/ssv6006C_reg.h	12382;"	d
+SET_RG_TURISMO_TRX_VOBF_CAPIMB_POL	smac/hal/ssv6006c/ssv6006C_reg.h	12381;"	d
+SET_RG_TURISMO_TRX_VOBF_DIVBFSEL	smac/hal/ssv6006c/ssv6006C_reg.h	12378;"	d
+SET_RG_TURISMO_TRX_VOBF_RXMBSEL_BT	smac/hal/ssv6006c/ssv6006C_reg.h	12372;"	d
+SET_RG_TURISMO_TRX_VOBF_RXMBSEL_WF	smac/hal/ssv6006c/ssv6006C_reg.h	12376;"	d
+SET_RG_TURISMO_TRX_VOBF_RXOBSEL_BT	smac/hal/ssv6006c/ssv6006C_reg.h	12373;"	d
+SET_RG_TURISMO_TRX_VOBF_RXOBSEL_WF	smac/hal/ssv6006c/ssv6006C_reg.h	12377;"	d
+SET_RG_TURISMO_TRX_VOBF_TXMBSEL_BT	smac/hal/ssv6006c/ssv6006C_reg.h	12370;"	d
+SET_RG_TURISMO_TRX_VOBF_TXMBSEL_WF	smac/hal/ssv6006c/ssv6006C_reg.h	12374;"	d
+SET_RG_TURISMO_TRX_VOBF_TXOBSEL_BT	smac/hal/ssv6006c/ssv6006C_reg.h	12371;"	d
+SET_RG_TURISMO_TRX_VOBF_TXOBSEL_WF	smac/hal/ssv6006c/ssv6006C_reg.h	12375;"	d
+SET_RG_TURISMO_TRX_VO_AAC_EN	smac/hal/ssv6006c/ssv6006C_reg.h	12409;"	d
+SET_RG_TURISMO_TRX_VO_AAC_EN_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	12408;"	d
+SET_RG_TURISMO_TRX_VO_AAC_EVA	smac/hal/ssv6006c/ssv6006C_reg.h	12411;"	d
+SET_RG_TURISMO_TRX_VO_AAC_EVA_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	12410;"	d
+SET_RG_TURISMO_TRX_VO_AAC_EVA_TS	smac/hal/ssv6006c/ssv6006C_reg.h	12407;"	d
+SET_RG_TURISMO_TRX_VO_AAC_IMAX	smac/hal/ssv6006c/ssv6006C_reg.h	12405;"	d
+SET_RG_TURISMO_TRX_VO_AAC_INIT	smac/hal/ssv6006c/ssv6006C_reg.h	12406;"	d
+SET_RG_TURISMO_TRX_VO_AAC_IOST_BT	smac/hal/ssv6006c/ssv6006C_reg.h	12402;"	d
+SET_RG_TURISMO_TRX_VO_AAC_IOST_WF	smac/hal/ssv6006c/ssv6006C_reg.h	12404;"	d
+SET_RG_TURISMO_TRX_VO_AAC_TAR_BT	smac/hal/ssv6006c/ssv6006C_reg.h	12401;"	d
+SET_RG_TURISMO_TRX_VO_AAC_TAR_WF	smac/hal/ssv6006c/ssv6006C_reg.h	12403;"	d
+SET_RG_TURISMO_TRX_VO_AAC_TEST_EN	smac/hal/ssv6006c/ssv6006C_reg.h	12412;"	d
+SET_RG_TURISMO_TRX_VO_AAC_TEST_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	12413;"	d
+SET_RG_TURISMO_TRX_WF_EN_TX_PA_VIN33	smac/hal/ssv6006c/ssv6006C_reg.h	12114;"	d
+SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	12482;"	d
+SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	12480;"	d
+SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	12462;"	d
+SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	12460;"	d
+SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	12458;"	d
+SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	12456;"	d
+SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	12454;"	d
+SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	12452;"	d
+SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	12478;"	d
+SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	12476;"	d
+SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	12474;"	d
+SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	12472;"	d
+SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	12470;"	d
+SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	12468;"	d
+SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	12466;"	d
+SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	12464;"	d
+SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	12514;"	d
+SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	12512;"	d
+SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	12494;"	d
+SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	12492;"	d
+SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	12490;"	d
+SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	12488;"	d
+SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	12486;"	d
+SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	12484;"	d
+SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	12510;"	d
+SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	12508;"	d
+SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	12506;"	d
+SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	12504;"	d
+SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	12502;"	d
+SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	12500;"	d
+SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	12498;"	d
+SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	12496;"	d
+SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	12483;"	d
+SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	12481;"	d
+SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	12463;"	d
+SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	12461;"	d
+SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	12459;"	d
+SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	12457;"	d
+SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	12455;"	d
+SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	12453;"	d
+SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	12479;"	d
+SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	12477;"	d
+SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	12475;"	d
+SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	12473;"	d
+SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	12471;"	d
+SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	12469;"	d
+SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	12467;"	d
+SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	12465;"	d
+SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	12515;"	d
+SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	12513;"	d
+SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	12495;"	d
+SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	12493;"	d
+SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	12491;"	d
+SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	12489;"	d
+SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	12487;"	d
+SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	12485;"	d
+SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	12511;"	d
+SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	12509;"	d
+SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	12507;"	d
+SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	12505;"	d
+SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	12503;"	d
+SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	12501;"	d
+SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	12499;"	d
+SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	12497;"	d
+SET_RG_TURISMO_TRX_WF_N_RX_ABBCFIX	smac/hal/ssv6006c/ssv6006C_reg.h	12075;"	d
+SET_RG_TURISMO_TRX_WF_N_RX_ABBCTUNE	smac/hal/ssv6006c/ssv6006C_reg.h	12070;"	d
+SET_RG_TURISMO_TRX_WF_N_RX_ABB_BT_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	12077;"	d
+SET_RG_TURISMO_TRX_WF_N_RX_ABB_IDIV3	smac/hal/ssv6006c/ssv6006C_reg.h	12078;"	d
+SET_RG_TURISMO_TRX_WF_N_RX_ABB_N_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	12076;"	d
+SET_RG_TURISMO_TRX_WF_N_RX_EN_IDACA_COARSE	smac/hal/ssv6006c/ssv6006C_reg.h	12079;"	d
+SET_RG_TURISMO_TRX_WF_N_RX_EN_LOOPA	smac/hal/ssv6006c/ssv6006C_reg.h	12080;"	d
+SET_RG_TURISMO_TRX_WF_N_RX_FILTERI1ST	smac/hal/ssv6006c/ssv6006C_reg.h	12072;"	d
+SET_RG_TURISMO_TRX_WF_N_RX_FILTERI2ND	smac/hal/ssv6006c/ssv6006C_reg.h	12073;"	d
+SET_RG_TURISMO_TRX_WF_N_RX_FILTERI3RD	smac/hal/ssv6006c/ssv6006C_reg.h	12074;"	d
+SET_RG_TURISMO_TRX_WF_N_RX_FILTERI_COARSE	smac/hal/ssv6006c/ssv6006C_reg.h	12071;"	d
+SET_RG_TURISMO_TRX_WF_N_RX_FILTERVCM	smac/hal/ssv6006c/ssv6006C_reg.h	12081;"	d
+SET_RG_TURISMO_TRX_WF_N_RX_OUTVCM	smac/hal/ssv6006c/ssv6006C_reg.h	12082;"	d
+SET_RG_TURISMO_TRX_WF_PABIAS_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	12126;"	d
+SET_RG_TURISMO_TRX_WF_PACELL_EN	smac/hal/ssv6006c/ssv6006C_reg.h	12125;"	d
+SET_RG_TURISMO_TRX_WF_RX_ABBCFIX	smac/hal/ssv6006c/ssv6006C_reg.h	12062;"	d
+SET_RG_TURISMO_TRX_WF_RX_ABBCTUNE	smac/hal/ssv6006c/ssv6006C_reg.h	12057;"	d
+SET_RG_TURISMO_TRX_WF_RX_ABB_BT_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	12064;"	d
+SET_RG_TURISMO_TRX_WF_RX_ABB_IDIV3	smac/hal/ssv6006c/ssv6006C_reg.h	12065;"	d
+SET_RG_TURISMO_TRX_WF_RX_ABB_N_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	12063;"	d
+SET_RG_TURISMO_TRX_WF_RX_ADC_CLOAD	smac/hal/ssv6006c/ssv6006C_reg.h	12239;"	d
+SET_RG_TURISMO_TRX_WF_RX_ADC_ICMP	smac/hal/ssv6006c/ssv6006C_reg.h	12237;"	d
+SET_RG_TURISMO_TRX_WF_RX_ADC_VCMI	smac/hal/ssv6006c/ssv6006C_reg.h	12238;"	d
+SET_RG_TURISMO_TRX_WF_RX_DCCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	12614;"	d
+SET_RG_TURISMO_TRX_WF_RX_EN_IDACA_COARSE	smac/hal/ssv6006c/ssv6006C_reg.h	12066;"	d
+SET_RG_TURISMO_TRX_WF_RX_EN_LOOPA	smac/hal/ssv6006c/ssv6006C_reg.h	12067;"	d
+SET_RG_TURISMO_TRX_WF_RX_FILTERI1ST	smac/hal/ssv6006c/ssv6006C_reg.h	12059;"	d
+SET_RG_TURISMO_TRX_WF_RX_FILTERI2ND	smac/hal/ssv6006c/ssv6006C_reg.h	12060;"	d
+SET_RG_TURISMO_TRX_WF_RX_FILTERI3RD	smac/hal/ssv6006c/ssv6006C_reg.h	12061;"	d
+SET_RG_TURISMO_TRX_WF_RX_FILTERI_COARSE	smac/hal/ssv6006c/ssv6006C_reg.h	12058;"	d
+SET_RG_TURISMO_TRX_WF_RX_FILTERVCM	smac/hal/ssv6006c/ssv6006C_reg.h	12068;"	d
+SET_RG_TURISMO_TRX_WF_RX_HG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	12151;"	d
+SET_RG_TURISMO_TRX_WF_RX_HG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	12146;"	d
+SET_RG_TURISMO_TRX_WF_RX_HG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	12147;"	d
+SET_RG_TURISMO_TRX_WF_RX_HG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	12148;"	d
+SET_RG_TURISMO_TRX_WF_RX_HG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	12144;"	d
+SET_RG_TURISMO_TRX_WF_RX_HG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	12152;"	d
+SET_RG_TURISMO_TRX_WF_RX_HG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	12153;"	d
+SET_RG_TURISMO_TRX_WF_RX_HG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	12149;"	d
+SET_RG_TURISMO_TRX_WF_RX_HG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	12145;"	d
+SET_RG_TURISMO_TRX_WF_RX_HG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	12150;"	d
+SET_RG_TURISMO_TRX_WF_RX_HG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	12154;"	d
+SET_RG_TURISMO_TRX_WF_RX_LG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	12173;"	d
+SET_RG_TURISMO_TRX_WF_RX_LG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	12168;"	d
+SET_RG_TURISMO_TRX_WF_RX_LG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	12169;"	d
+SET_RG_TURISMO_TRX_WF_RX_LG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	12170;"	d
+SET_RG_TURISMO_TRX_WF_RX_LG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	12166;"	d
+SET_RG_TURISMO_TRX_WF_RX_LG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	12174;"	d
+SET_RG_TURISMO_TRX_WF_RX_LG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	12175;"	d
+SET_RG_TURISMO_TRX_WF_RX_LG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	12171;"	d
+SET_RG_TURISMO_TRX_WF_RX_LG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	12167;"	d
+SET_RG_TURISMO_TRX_WF_RX_LG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	12172;"	d
+SET_RG_TURISMO_TRX_WF_RX_LG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	12176;"	d
+SET_RG_TURISMO_TRX_WF_RX_MG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	12162;"	d
+SET_RG_TURISMO_TRX_WF_RX_MG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	12157;"	d
+SET_RG_TURISMO_TRX_WF_RX_MG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	12158;"	d
+SET_RG_TURISMO_TRX_WF_RX_MG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	12159;"	d
+SET_RG_TURISMO_TRX_WF_RX_MG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	12155;"	d
+SET_RG_TURISMO_TRX_WF_RX_MG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	12163;"	d
+SET_RG_TURISMO_TRX_WF_RX_MG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	12164;"	d
+SET_RG_TURISMO_TRX_WF_RX_MG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	12160;"	d
+SET_RG_TURISMO_TRX_WF_RX_MG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	12156;"	d
+SET_RG_TURISMO_TRX_WF_RX_MG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	12161;"	d
+SET_RG_TURISMO_TRX_WF_RX_MG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	12165;"	d
+SET_RG_TURISMO_TRX_WF_RX_OUTVCM	smac/hal/ssv6006c/ssv6006C_reg.h	12069;"	d
+SET_RG_TURISMO_TRX_WF_RX_ULG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	12184;"	d
+SET_RG_TURISMO_TRX_WF_RX_ULG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	12179;"	d
+SET_RG_TURISMO_TRX_WF_RX_ULG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	12180;"	d
+SET_RG_TURISMO_TRX_WF_RX_ULG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	12181;"	d
+SET_RG_TURISMO_TRX_WF_RX_ULG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	12177;"	d
+SET_RG_TURISMO_TRX_WF_RX_ULG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	12185;"	d
+SET_RG_TURISMO_TRX_WF_RX_ULG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	12186;"	d
+SET_RG_TURISMO_TRX_WF_RX_ULG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	12182;"	d
+SET_RG_TURISMO_TRX_WF_RX_ULG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	12178;"	d
+SET_RG_TURISMO_TRX_WF_RX_ULG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	12183;"	d
+SET_RG_TURISMO_TRX_WF_RX_ULG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	12187;"	d
+SET_RG_TURISMO_TRX_WF_TXLPF_BOOSTI	smac/hal/ssv6006c/ssv6006C_reg.h	12255;"	d
+SET_RG_TURISMO_TRX_WF_TXPGA_CAPSW	smac/hal/ssv6006c/ssv6006C_reg.h	12110;"	d
+SET_RG_TURISMO_TRX_WF_TX_BTPASW	smac/hal/ssv6006c/ssv6006C_reg.h	12113;"	d
+SET_RG_TURISMO_TRX_WF_TX_DACI1ST	smac/hal/ssv6006c/ssv6006C_reg.h	12249;"	d
+SET_RG_TURISMO_TRX_WF_TX_DACLPF_ICOARSE	smac/hal/ssv6006c/ssv6006C_reg.h	12250;"	d
+SET_RG_TURISMO_TRX_WF_TX_DACLPF_IFINE	smac/hal/ssv6006c/ssv6006C_reg.h	12251;"	d
+SET_RG_TURISMO_TRX_WF_TX_DACLPF_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	12252;"	d
+SET_RG_TURISMO_TRX_WF_TX_DAC_CKEDGE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	12257;"	d
+SET_RG_TURISMO_TRX_WF_TX_DAC_IATTN	smac/hal/ssv6006c/ssv6006C_reg.h	12254;"	d
+SET_RG_TURISMO_TRX_WF_TX_DAC_IBIAS	smac/hal/ssv6006c/ssv6006C_reg.h	12253;"	d
+SET_RG_TURISMO_TRX_WF_TX_DAC_IOFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	12259;"	d
+SET_RG_TURISMO_TRX_WF_TX_DAC_OS	smac/hal/ssv6006c/ssv6006C_reg.h	12258;"	d
+SET_RG_TURISMO_TRX_WF_TX_DAC_QOFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	12260;"	d
+SET_RG_TURISMO_TRX_WF_TX_DAC_RCAL	smac/hal/ssv6006c/ssv6006C_reg.h	12256;"	d
+SET_RG_TURISMO_TRX_WF_TX_DIV_VSET	smac/hal/ssv6006c/ssv6006C_reg.h	12111;"	d
+SET_RG_TURISMO_TRX_WF_TX_GAIN_OFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	12138;"	d
+SET_RG_TURISMO_TRX_WF_TX_LOBUF_VSET	smac/hal/ssv6006c/ssv6006C_reg.h	12112;"	d
+SET_RG_TURISMO_TRX_WF_TX_PA1_VCAS	smac/hal/ssv6006c/ssv6006C_reg.h	12127;"	d
+SET_RG_TURISMO_TRX_WF_TX_PA2_VCAS	smac/hal/ssv6006c/ssv6006C_reg.h	12128;"	d
+SET_RG_TURISMO_TRX_WF_TX_PA3_VCAS	smac/hal/ssv6006c/ssv6006C_reg.h	12129;"	d
+SET_RG_TURISMO_TRX_XO_CBANKI	smac/hal/ssv6006c/ssv6006C_reg.h	13186;"	d
+SET_RG_TURISMO_TRX_XO_CBANKO	smac/hal/ssv6006c/ssv6006C_reg.h	13187;"	d
+SET_RG_TURISMO_TRX_XO_LDO_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	13182;"	d
+SET_RG_TURISMO_TRX_XO_TIMMER	smac/hal/ssv6006c/ssv6006C_reg.h	13199;"	d
+SET_RG_TXBTPA_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	13974;"	d
+SET_RG_TXDAC_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	13970;"	d
+SET_RG_TXDAC_R2T_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	13979;"	d
+SET_RG_TXDAC_T2R_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	13975;"	d
+SET_RG_TXD_SEL	include/ssv6200_reg.h	7555;"	d
+SET_RG_TXD_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	15137;"	d
+SET_RG_TXGAIN_MANUAL	include/ssv6200_reg.h	8253;"	d
+SET_RG_TXGAIN_PHYCTRL	include/ssv6200_reg.h	8251;"	d
+SET_RG_TXGAIN_PHYCTRL	smac/hal/ssv6006c/ssv6006C_reg.h	13368;"	d
+SET_RG_TXIQ_CLP_THD_I	include/ssv6200_reg.h	7988;"	d
+SET_RG_TXIQ_CLP_THD_I	smac/hal/ssv6006c/ssv6006C_reg.h	14846;"	d
+SET_RG_TXIQ_CLP_THD_Q	include/ssv6200_reg.h	7989;"	d
+SET_RG_TXIQ_CLP_THD_Q	smac/hal/ssv6006c/ssv6006C_reg.h	14847;"	d
+SET_RG_TXIQ_EMU_IDX	include/ssv6200_reg.h	7994;"	d
+SET_RG_TXIQ_NOSHRINK	include/ssv6200_reg.h	8000;"	d
+SET_RG_TXIQ_NOSHRK	smac/hal/ssv6006c/ssv6006C_reg.h	14499;"	d
+SET_RG_TXLPF_BOOSTI	include/ssv6200_reg.h	8283;"	d
+SET_RG_TXLPF_BYPASS	include/ssv6200_reg.h	8282;"	d
+SET_RG_TXLPF_BYPASS	smac/hal/ssv6006c/ssv6006C_reg.h	13425;"	d
+SET_RG_TXLPF_GMCELL	include/ssv6200_reg.h	8204;"	d
+SET_RG_TXLPF_GMCELL	smac/hal/ssv6006c/ssv6006C_reg.h	13529;"	d
+SET_RG_TXMOD_GMCELL	include/ssv6200_reg.h	8203;"	d
+SET_RG_TXMOD_GMCELL	smac/hal/ssv6006c/ssv6006C_reg.h	13528;"	d
+SET_RG_TXPA_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	13972;"	d
+SET_RG_TXPA_R2T_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	13981;"	d
+SET_RG_TXPA_T2R_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	13977;"	d
+SET_RG_TXPGA_CAPSW	include/ssv6200_reg.h	8200;"	d
+SET_RG_TXPGA_MAIN	include/ssv6200_reg.h	8201;"	d
+SET_RG_TXPGA_MAIN	smac/hal/ssv6006c/ssv6006C_reg.h	13526;"	d
+SET_RG_TXPGA_STEER	include/ssv6200_reg.h	8202;"	d
+SET_RG_TXPGA_STEER	smac/hal/ssv6006c/ssv6006C_reg.h	13527;"	d
+SET_RG_TXPWRLVL	include/ssv6200_reg.h	7545;"	d
+SET_RG_TXPWRLVL	smac/hal/ssv6006c/ssv6006C_reg.h	15128;"	d
+SET_RG_TXPWRLVL_SEL	include/ssv6200_reg.h	7513;"	d
+SET_RG_TXPWRLVL_SET	include/ssv6200_reg.h	7512;"	d
+SET_RG_TXRF_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	13971;"	d
+SET_RG_TXRF_R2T_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	13980;"	d
+SET_RG_TXRF_T2R_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	13976;"	d
+SET_RG_TX_BB_SCALE_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	14850;"	d
+SET_RG_TX_BT_PA_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	13405;"	d
+SET_RG_TX_CLK_OUTER_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15433;"	d
+SET_RG_TX_CNT_TARGET	include/ssv6200_reg.h	7551;"	d
+SET_RG_TX_CNT_TARGET	smac/hal/ssv6006c/ssv6006C_reg.h	15136;"	d
+SET_RG_TX_D	include/ssv6200_reg.h	7550;"	d
+SET_RG_TX_D	smac/hal/ssv6006c/ssv6006C_reg.h	15134;"	d
+SET_RG_TX_DACLPF_ICOURSE	include/ssv6200_reg.h	8273;"	d
+SET_RG_TX_DACLPF_IFINE	include/ssv6200_reg.h	8274;"	d
+SET_RG_TX_DACLPF_VCM	include/ssv6200_reg.h	8275;"	d
+SET_RG_TX_DAC_CAL_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	13412;"	d
+SET_RG_TX_DAC_CKEDGE_SEL	include/ssv6200_reg.h	8276;"	d
+SET_RG_TX_DAC_EN	include/ssv6200_reg.h	8118;"	d
+SET_RG_TX_DAC_IBIAS	include/ssv6200_reg.h	8277;"	d
+SET_RG_TX_DAC_IOFFSET	include/ssv6200_reg.h	8284;"	d
+SET_RG_TX_DAC_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	13399;"	d
+SET_RG_TX_DAC_OS	include/ssv6200_reg.h	8278;"	d
+SET_RG_TX_DAC_QOFFSET	include/ssv6200_reg.h	8285;"	d
+SET_RG_TX_DAC_RCAL	include/ssv6200_reg.h	8279;"	d
+SET_RG_TX_DAC_TSEL	include/ssv6200_reg.h	8280;"	d
+SET_RG_TX_DAC_TSEL	smac/hal/ssv6006c/ssv6006C_reg.h	13655;"	d
+SET_RG_TX_DCCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	13986;"	d
+SET_RG_TX_DES_ACK_PRD	include/ssv6200_reg.h	7653;"	d
+SET_RG_TX_DES_ACK_WIDTH	include/ssv6200_reg.h	7652;"	d
+SET_RG_TX_DES_EXCP_CLR	include/ssv6200_reg.h	7651;"	d
+SET_RG_TX_DES_EXCP_MODE_DEFAULT	include/ssv6200_reg.h	7650;"	d
+SET_RG_TX_DES_EXCP_RATE_DEFAULT	include/ssv6200_reg.h	7649;"	d
+SET_RG_TX_DES_LEN_LO	include/ssv6200_reg.h	7619;"	d
+SET_RG_TX_DES_LEN_UP	include/ssv6200_reg.h	7620;"	d
+SET_RG_TX_DES_L_LEN_LO	include/ssv6200_reg.h	7622;"	d
+SET_RG_TX_DES_L_LEN_UP	include/ssv6200_reg.h	7623;"	d
+SET_RG_TX_DES_L_LEN_UP_COMB	include/ssv6200_reg.h	7625;"	d
+SET_RG_TX_DES_MODE	include/ssv6200_reg.h	7618;"	d
+SET_RG_TX_DES_MODE_COMB	include/ssv6200_reg.h	7628;"	d
+SET_RG_TX_DES_PWRLVL	include/ssv6200_reg.h	7629;"	d
+SET_RG_TX_DES_RATE	include/ssv6200_reg.h	7617;"	d
+SET_RG_TX_DES_RATE_COMB	include/ssv6200_reg.h	7627;"	d
+SET_RG_TX_DES_SRVC_LO	include/ssv6200_reg.h	7630;"	d
+SET_RG_TX_DES_SRVC_UP	include/ssv6200_reg.h	7621;"	d
+SET_RG_TX_DES_TYPE	include/ssv6200_reg.h	7624;"	d
+SET_RG_TX_DES_TYPE_COMB	include/ssv6200_reg.h	7626;"	d
+SET_RG_TX_DIV2_BUF_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	13403;"	d
+SET_RG_TX_DIV2_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	13401;"	d
+SET_RG_TX_DIV_VSET	include/ssv6200_reg.h	8207;"	d
+SET_RG_TX_DPDGM_BIAS	include/ssv6200_reg.h	8212;"	d
+SET_RG_TX_DPDGM_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	13498;"	d
+SET_RG_TX_DPD_DIV	include/ssv6200_reg.h	8213;"	d
+SET_RG_TX_DPD_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	13499;"	d
+SET_RG_TX_DPD_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	13420;"	d
+SET_RG_TX_EN	include/ssv6200_reg.h	8116;"	d
+SET_RG_TX_EN_VOLTAGE_IN	include/ssv6200_reg.h	8281;"	d
+SET_RG_TX_EN_VOLTAGE_IN	smac/hal/ssv6006c/ssv6006C_reg.h	13426;"	d
+SET_RG_TX_FIFO_EMPTY_CNT_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15324;"	d
+SET_RG_TX_FREQ_OFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	14501;"	d
+SET_RG_TX_FREQ_OFFSET_DES	smac/hal/ssv6006c/ssv6006C_reg.h	15138;"	d
+SET_RG_TX_GAIN	include/ssv6200_reg.h	8252;"	d
+SET_RG_TX_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	13376;"	d
+SET_RG_TX_GAIN_DPDCAL	smac/hal/ssv6006c/ssv6006C_reg.h	13998;"	d
+SET_RG_TX_GAIN_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	13367;"	d
+SET_RG_TX_GAIN_OFFSET	include/ssv6200_reg.h	8254;"	d
+SET_RG_TX_GAIN_RXIQCAL	smac/hal/ssv6006c/ssv6006C_reg.h	13995;"	d
+SET_RG_TX_GAIN_TXCAL	smac/hal/ssv6006c/ssv6006C_reg.h	13992;"	d
+SET_RG_TX_IQCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	13987;"	d
+SET_RG_TX_IQCAL_TIME	smac/hal/ssv6006c/ssv6006C_reg.h	14500;"	d
+SET_RG_TX_IQ_2500_ALPHA	smac/hal/ssv6006c/ssv6006C_reg.h	14522;"	d
+SET_RG_TX_IQ_2500_THETA	smac/hal/ssv6006c/ssv6006C_reg.h	14523;"	d
+SET_RG_TX_IQ_5100_ALPHA	smac/hal/ssv6006c/ssv6006C_reg.h	14526;"	d
+SET_RG_TX_IQ_5100_THETA	smac/hal/ssv6006c/ssv6006C_reg.h	14527;"	d
+SET_RG_TX_IQ_5500_ALPHA	smac/hal/ssv6006c/ssv6006C_reg.h	14530;"	d
+SET_RG_TX_IQ_5500_THETA	smac/hal/ssv6006c/ssv6006C_reg.h	14531;"	d
+SET_RG_TX_IQ_5700_ALPHA	smac/hal/ssv6006c/ssv6006C_reg.h	14534;"	d
+SET_RG_TX_IQ_5700_THETA	smac/hal/ssv6006c/ssv6006C_reg.h	14535;"	d
+SET_RG_TX_IQ_5900_ALPHA	smac/hal/ssv6006c/ssv6006C_reg.h	14538;"	d
+SET_RG_TX_IQ_5900_THETA	smac/hal/ssv6006c/ssv6006C_reg.h	14539;"	d
+SET_RG_TX_IQ_ALPHA	include/ssv6200_reg.h	7999;"	d
+SET_RG_TX_IQ_ALPHA	smac/hal/ssv6006c/ssv6006C_reg.h	14496;"	d
+SET_RG_TX_IQ_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	14498;"	d
+SET_RG_TX_IQ_SRC	include/ssv6200_reg.h	7995;"	d
+SET_RG_TX_IQ_SRC	smac/hal/ssv6006c/ssv6006C_reg.h	14851;"	d
+SET_RG_TX_IQ_SWP	include/ssv6200_reg.h	7992;"	d
+SET_RG_TX_IQ_SWP	smac/hal/ssv6006c/ssv6006C_reg.h	14849;"	d
+SET_RG_TX_IQ_THETA	include/ssv6200_reg.h	7998;"	d
+SET_RG_TX_IQ_THETA	smac/hal/ssv6006c/ssv6006C_reg.h	14497;"	d
+SET_RG_TX_I_DC	include/ssv6200_reg.h	7996;"	d
+SET_RG_TX_I_DC	smac/hal/ssv6006c/ssv6006C_reg.h	14852;"	d
+SET_RG_TX_I_OFFSET	include/ssv6200_reg.h	8001;"	d
+SET_RG_TX_I_OFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	14854;"	d
+SET_RG_TX_I_SCALE	include/ssv6200_reg.h	7990;"	d
+SET_RG_TX_LDO_TX_LEVEL	include/ssv6200_reg.h	8168;"	d
+SET_RG_TX_LOBUF_VSET	include/ssv6200_reg.h	8208;"	d
+SET_RG_TX_MOD_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	13397;"	d
+SET_RG_TX_PA_EN	include/ssv6200_reg.h	8117;"	d
+SET_RG_TX_PA_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	13395;"	d
+SET_RG_TX_Q_DC	include/ssv6200_reg.h	7997;"	d
+SET_RG_TX_Q_DC	smac/hal/ssv6006c/ssv6006C_reg.h	14853;"	d
+SET_RG_TX_Q_OFFSET	include/ssv6200_reg.h	8002;"	d
+SET_RG_TX_Q_OFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	14855;"	d
+SET_RG_TX_Q_SCALE	include/ssv6200_reg.h	7991;"	d
+SET_RG_TX_SCALE	smac/hal/ssv6006c/ssv6006C_reg.h	14848;"	d
+SET_RG_TX_SCALE_11B	smac/hal/ssv6006c/ssv6006C_reg.h	14916;"	d
+SET_RG_TX_SCALE_11B_P0D5	smac/hal/ssv6006c/ssv6006C_reg.h	14917;"	d
+SET_RG_TX_SCALE_11G	smac/hal/ssv6006c/ssv6006C_reg.h	14918;"	d
+SET_RG_TX_SCALE_11G_P0D5	smac/hal/ssv6006c/ssv6006C_reg.h	14919;"	d
+SET_RG_TX_SELF_MIXER_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	13416;"	d
+SET_RG_TX_SGN_OUT	include/ssv6200_reg.h	7993;"	d
+SET_RG_TX_START	include/ssv6200_reg.h	7546;"	d
+SET_RG_TX_START	smac/hal/ssv6006c/ssv6006C_reg.h	15130;"	d
+SET_RG_TX_TIME_EXT	include/ssv6200_reg.h	7920;"	d
+SET_RG_TX_TRSW_MANUAL	smac/hal/ssv6006c/ssv6006C_reg.h	13377;"	d
+SET_RG_TX_TSSI_BIAS	include/ssv6200_reg.h	8214;"	d
+SET_RG_TX_TSSI_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	13500;"	d
+SET_RG_TX_TSSI_DIV	include/ssv6200_reg.h	8215;"	d
+SET_RG_TX_TSSI_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	13501;"	d
+SET_RG_TX_TSSI_TEST	include/ssv6200_reg.h	8217;"	d
+SET_RG_TX_TSSI_TEST	smac/hal/ssv6006c/ssv6006C_reg.h	13502;"	d
+SET_RG_TX_TSSI_TESTMODE	include/ssv6200_reg.h	8216;"	d
+SET_RG_TX_TSSI_TESTMODE	smac/hal/ssv6006c/ssv6006C_reg.h	13503;"	d
+SET_RG_TX_UP8X_MAN_EN	smac/hal/ssv6006c/ssv6006C_reg.h	14505;"	d
+SET_RG_TX_VTOI_CURRENT	smac/hal/ssv6006c/ssv6006C_reg.h	13532;"	d
+SET_RG_TX_VTOI_FS	smac/hal/ssv6006c/ssv6006C_reg.h	13535;"	d
+SET_RG_TX_VTOI_GM	smac/hal/ssv6006c/ssv6006C_reg.h	13533;"	d
+SET_RG_TX_VTOI_OPTION	smac/hal/ssv6006c/ssv6006C_reg.h	13534;"	d
+SET_RG_ULG_PGA_SAT_PGA_GAIN	include/ssv6200_reg.h	7575;"	d
+SET_RG_ULG_PGA_SAT_PGA_GAIN	smac/hal/ssv6006c/ssv6006C_reg.h	15158;"	d
+SET_RG_UP8X	include/ssv6200_reg.h	7556;"	d
+SET_RG_VITERBI_AB_SWAP	include/ssv6200_reg.h	7872;"	d
+SET_RG_VITERBI_AB_SWAP	smac/hal/ssv6006c/ssv6006C_reg.h	15465;"	d
+SET_RG_VITERBI_TB_BITS	include/ssv6200_reg.h	7904;"	d
+SET_RG_VITERBI_TB_BITS	smac/hal/ssv6006c/ssv6006C_reg.h	15541;"	d
+SET_RG_VO5GB_AAC_IMAX	smac/hal/ssv6006c/ssv6006C_reg.h	14292;"	d
+SET_RG_VO5GB_AAC_IOST	smac/hal/ssv6006c/ssv6006C_reg.h	14291;"	d
+SET_RG_VOBF_CAPIMB	smac/hal/ssv6006c/ssv6006C_reg.h	13777;"	d
+SET_RG_VOBF_CAPIMB_POL	smac/hal/ssv6006c/ssv6006C_reg.h	13776;"	d
+SET_RG_VOBF_DIVBFSEL	smac/hal/ssv6006c/ssv6006C_reg.h	13773;"	d
+SET_RG_VOBF_RXMBSEL_BT	smac/hal/ssv6006c/ssv6006C_reg.h	13767;"	d
+SET_RG_VOBF_RXMBSEL_WF	smac/hal/ssv6006c/ssv6006C_reg.h	13771;"	d
+SET_RG_VOBF_RXOBSEL_BT	smac/hal/ssv6006c/ssv6006C_reg.h	13768;"	d
+SET_RG_VOBF_RXOBSEL_WF	smac/hal/ssv6006c/ssv6006C_reg.h	13772;"	d
+SET_RG_VOBF_TXMBSEL_BT	smac/hal/ssv6006c/ssv6006C_reg.h	13765;"	d
+SET_RG_VOBF_TXMBSEL_WF	smac/hal/ssv6006c/ssv6006C_reg.h	13769;"	d
+SET_RG_VOBF_TXOBSEL_BT	smac/hal/ssv6006c/ssv6006C_reg.h	13766;"	d
+SET_RG_VOBF_TXOBSEL_WF	smac/hal/ssv6006c/ssv6006C_reg.h	13770;"	d
+SET_RG_VO_AAC_EN	smac/hal/ssv6006c/ssv6006C_reg.h	13804;"	d
+SET_RG_VO_AAC_EN_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	13803;"	d
+SET_RG_VO_AAC_EVA	smac/hal/ssv6006c/ssv6006C_reg.h	13806;"	d
+SET_RG_VO_AAC_EVA_MAN	smac/hal/ssv6006c/ssv6006C_reg.h	13805;"	d
+SET_RG_VO_AAC_EVA_TS	smac/hal/ssv6006c/ssv6006C_reg.h	13802;"	d
+SET_RG_VO_AAC_IMAX	smac/hal/ssv6006c/ssv6006C_reg.h	13800;"	d
+SET_RG_VO_AAC_INIT	smac/hal/ssv6006c/ssv6006C_reg.h	13801;"	d
+SET_RG_VO_AAC_IOST_BT	smac/hal/ssv6006c/ssv6006C_reg.h	13797;"	d
+SET_RG_VO_AAC_IOST_WF	smac/hal/ssv6006c/ssv6006C_reg.h	13799;"	d
+SET_RG_VO_AAC_TAR_BT	smac/hal/ssv6006c/ssv6006C_reg.h	13796;"	d
+SET_RG_VO_AAC_TAR_WF	smac/hal/ssv6006c/ssv6006C_reg.h	13798;"	d
+SET_RG_VO_AAC_TEST_EN	smac/hal/ssv6006c/ssv6006C_reg.h	13807;"	d
+SET_RG_VO_AAC_TEST_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	13808;"	d
+SET_RG_WAIT_T	include/ssv6200_reg.h	7574;"	d
+SET_RG_WAIT_T	smac/hal/ssv6006c/ssv6006C_reg.h	15157;"	d
+SET_RG_WAIT_T_FINAL	include/ssv6200_reg.h	7573;"	d
+SET_RG_WAIT_T_FINAL	smac/hal/ssv6006c/ssv6006C_reg.h	15156;"	d
+SET_RG_WAIT_T_RXAGC	include/ssv6200_reg.h	7570;"	d
+SET_RG_WAIT_T_RXAGC	smac/hal/ssv6006c/ssv6006C_reg.h	15153;"	d
+SET_RG_WF_BTPASW	smac/hal/ssv6006c/ssv6006C_reg.h	13520;"	d
+SET_RG_WF_IDACAI_TZ0_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	13851;"	d
+SET_RG_WF_IDACAI_TZ0_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	13849;"	d
+SET_RG_WF_IDACAI_TZ0_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	13831;"	d
+SET_RG_WF_IDACAI_TZ0_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	13829;"	d
+SET_RG_WF_IDACAI_TZ0_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	13827;"	d
+SET_RG_WF_IDACAI_TZ0_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	13825;"	d
+SET_RG_WF_IDACAI_TZ0_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	13823;"	d
+SET_RG_WF_IDACAI_TZ0_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	13821;"	d
+SET_RG_WF_IDACAI_TZ0_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	13847;"	d
+SET_RG_WF_IDACAI_TZ0_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	13845;"	d
+SET_RG_WF_IDACAI_TZ0_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	13843;"	d
+SET_RG_WF_IDACAI_TZ0_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	13841;"	d
+SET_RG_WF_IDACAI_TZ0_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	13839;"	d
+SET_RG_WF_IDACAI_TZ0_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	13837;"	d
+SET_RG_WF_IDACAI_TZ0_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	13835;"	d
+SET_RG_WF_IDACAI_TZ0_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	13833;"	d
+SET_RG_WF_IDACAI_TZ1_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	13883;"	d
+SET_RG_WF_IDACAI_TZ1_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	13881;"	d
+SET_RG_WF_IDACAI_TZ1_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	13863;"	d
+SET_RG_WF_IDACAI_TZ1_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	13861;"	d
+SET_RG_WF_IDACAI_TZ1_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	13859;"	d
+SET_RG_WF_IDACAI_TZ1_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	13857;"	d
+SET_RG_WF_IDACAI_TZ1_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	13855;"	d
+SET_RG_WF_IDACAI_TZ1_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	13853;"	d
+SET_RG_WF_IDACAI_TZ1_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	13879;"	d
+SET_RG_WF_IDACAI_TZ1_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	13877;"	d
+SET_RG_WF_IDACAI_TZ1_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	13875;"	d
+SET_RG_WF_IDACAI_TZ1_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	13873;"	d
+SET_RG_WF_IDACAI_TZ1_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	13871;"	d
+SET_RG_WF_IDACAI_TZ1_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	13869;"	d
+SET_RG_WF_IDACAI_TZ1_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	13867;"	d
+SET_RG_WF_IDACAI_TZ1_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	13865;"	d
+SET_RG_WF_IDACAQ_TZ0_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	13852;"	d
+SET_RG_WF_IDACAQ_TZ0_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	13850;"	d
+SET_RG_WF_IDACAQ_TZ0_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	13832;"	d
+SET_RG_WF_IDACAQ_TZ0_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	13830;"	d
+SET_RG_WF_IDACAQ_TZ0_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	13828;"	d
+SET_RG_WF_IDACAQ_TZ0_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	13826;"	d
+SET_RG_WF_IDACAQ_TZ0_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	13824;"	d
+SET_RG_WF_IDACAQ_TZ0_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	13822;"	d
+SET_RG_WF_IDACAQ_TZ0_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	13848;"	d
+SET_RG_WF_IDACAQ_TZ0_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	13846;"	d
+SET_RG_WF_IDACAQ_TZ0_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	13844;"	d
+SET_RG_WF_IDACAQ_TZ0_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	13842;"	d
+SET_RG_WF_IDACAQ_TZ0_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	13840;"	d
+SET_RG_WF_IDACAQ_TZ0_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	13838;"	d
+SET_RG_WF_IDACAQ_TZ0_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	13836;"	d
+SET_RG_WF_IDACAQ_TZ0_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	13834;"	d
+SET_RG_WF_IDACAQ_TZ1_PGAG0	smac/hal/ssv6006c/ssv6006C_reg.h	13884;"	d
+SET_RG_WF_IDACAQ_TZ1_PGAG1	smac/hal/ssv6006c/ssv6006C_reg.h	13882;"	d
+SET_RG_WF_IDACAQ_TZ1_PGAG10	smac/hal/ssv6006c/ssv6006C_reg.h	13864;"	d
+SET_RG_WF_IDACAQ_TZ1_PGAG11	smac/hal/ssv6006c/ssv6006C_reg.h	13862;"	d
+SET_RG_WF_IDACAQ_TZ1_PGAG12	smac/hal/ssv6006c/ssv6006C_reg.h	13860;"	d
+SET_RG_WF_IDACAQ_TZ1_PGAG13	smac/hal/ssv6006c/ssv6006C_reg.h	13858;"	d
+SET_RG_WF_IDACAQ_TZ1_PGAG14	smac/hal/ssv6006c/ssv6006C_reg.h	13856;"	d
+SET_RG_WF_IDACAQ_TZ1_PGAG15	smac/hal/ssv6006c/ssv6006C_reg.h	13854;"	d
+SET_RG_WF_IDACAQ_TZ1_PGAG2	smac/hal/ssv6006c/ssv6006C_reg.h	13880;"	d
+SET_RG_WF_IDACAQ_TZ1_PGAG3	smac/hal/ssv6006c/ssv6006C_reg.h	13878;"	d
+SET_RG_WF_IDACAQ_TZ1_PGAG4	smac/hal/ssv6006c/ssv6006C_reg.h	13876;"	d
+SET_RG_WF_IDACAQ_TZ1_PGAG5	smac/hal/ssv6006c/ssv6006C_reg.h	13874;"	d
+SET_RG_WF_IDACAQ_TZ1_PGAG6	smac/hal/ssv6006c/ssv6006C_reg.h	13872;"	d
+SET_RG_WF_IDACAQ_TZ1_PGAG7	smac/hal/ssv6006c/ssv6006C_reg.h	13870;"	d
+SET_RG_WF_IDACAQ_TZ1_PGAG8	smac/hal/ssv6006c/ssv6006C_reg.h	13868;"	d
+SET_RG_WF_IDACAQ_TZ1_PGAG9	smac/hal/ssv6006c/ssv6006C_reg.h	13866;"	d
+SET_RG_WF_N_RX_ABBCFIX	smac/hal/ssv6006c/ssv6006C_reg.h	13469;"	d
+SET_RG_WF_N_RX_ABBCTUNE	smac/hal/ssv6006c/ssv6006C_reg.h	13463;"	d
+SET_RG_WF_N_RX_ABBCTUNE_TUNE	smac/hal/ssv6006c/ssv6006C_reg.h	14518;"	d
+SET_RG_WF_N_RX_ABBCTUNE_TUNE_EN	smac/hal/ssv6006c/ssv6006C_reg.h	14519;"	d
+SET_RG_WF_N_RX_ABB_BT_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	13471;"	d
+SET_RG_WF_N_RX_ABB_IDIV3	smac/hal/ssv6006c/ssv6006C_reg.h	13472;"	d
+SET_RG_WF_N_RX_ABB_N_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	13470;"	d
+SET_RG_WF_N_RX_EN_IDACA_COARSE	smac/hal/ssv6006c/ssv6006C_reg.h	13473;"	d
+SET_RG_WF_N_RX_EN_LOOPA	smac/hal/ssv6006c/ssv6006C_reg.h	13474;"	d
+SET_RG_WF_N_RX_FILTERI1ST	smac/hal/ssv6006c/ssv6006C_reg.h	13466;"	d
+SET_RG_WF_N_RX_FILTERI2ND	smac/hal/ssv6006c/ssv6006C_reg.h	13467;"	d
+SET_RG_WF_N_RX_FILTERI3RD	smac/hal/ssv6006c/ssv6006C_reg.h	13468;"	d
+SET_RG_WF_N_RX_FILTERI_COARSE	smac/hal/ssv6006c/ssv6006C_reg.h	13465;"	d
+SET_RG_WF_N_RX_FILTERVCM	smac/hal/ssv6006c/ssv6006C_reg.h	13476;"	d
+SET_RG_WF_N_RX_OUTVCM	smac/hal/ssv6006c/ssv6006C_reg.h	13477;"	d
+SET_RG_WF_N_RX_TZ_CMZ_C	smac/hal/ssv6006c/ssv6006C_reg.h	13464;"	d
+SET_RG_WF_N_RX_TZ_CMZ_R	smac/hal/ssv6006c/ssv6006C_reg.h	13475;"	d
+SET_RG_WF_PABIAS_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	13516;"	d
+SET_RG_WF_PACELL_EN	smac/hal/ssv6006c/ssv6006C_reg.h	13515;"	d
+SET_RG_WF_RX_ABBCFIX	smac/hal/ssv6006c/ssv6006C_reg.h	13454;"	d
+SET_RG_WF_RX_ABBCTUNE	smac/hal/ssv6006c/ssv6006C_reg.h	13448;"	d
+SET_RG_WF_RX_ABBCTUNE_TUNE	smac/hal/ssv6006c/ssv6006C_reg.h	14516;"	d
+SET_RG_WF_RX_ABBCTUNE_TUNE_EN	smac/hal/ssv6006c/ssv6006C_reg.h	14517;"	d
+SET_RG_WF_RX_ABB_BT_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	13456;"	d
+SET_RG_WF_RX_ABB_IDIV3	smac/hal/ssv6006c/ssv6006C_reg.h	13457;"	d
+SET_RG_WF_RX_ABB_N_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	13455;"	d
+SET_RG_WF_RX_ADC_CLOAD	smac/hal/ssv6006c/ssv6006C_reg.h	13631;"	d
+SET_RG_WF_RX_ADC_ICMP	smac/hal/ssv6006c/ssv6006C_reg.h	13629;"	d
+SET_RG_WF_RX_ADC_PSW	smac/hal/ssv6006c/ssv6006C_reg.h	13632;"	d
+SET_RG_WF_RX_ADC_VCMI	smac/hal/ssv6006c/ssv6006C_reg.h	13630;"	d
+SET_RG_WF_RX_DCCAL_DELAY	smac/hal/ssv6006c/ssv6006C_reg.h	13983;"	d
+SET_RG_WF_RX_EN_IDACA_COARSE	smac/hal/ssv6006c/ssv6006C_reg.h	13458;"	d
+SET_RG_WF_RX_EN_LOOPA	smac/hal/ssv6006c/ssv6006C_reg.h	13459;"	d
+SET_RG_WF_RX_FILTERI1ST	smac/hal/ssv6006c/ssv6006C_reg.h	13451;"	d
+SET_RG_WF_RX_FILTERI2ND	smac/hal/ssv6006c/ssv6006C_reg.h	13452;"	d
+SET_RG_WF_RX_FILTERI3RD	smac/hal/ssv6006c/ssv6006C_reg.h	13453;"	d
+SET_RG_WF_RX_FILTERI_COARSE	smac/hal/ssv6006c/ssv6006C_reg.h	13450;"	d
+SET_RG_WF_RX_FILTERVCM	smac/hal/ssv6006c/ssv6006C_reg.h	13461;"	d
+SET_RG_WF_RX_HG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	13543;"	d
+SET_RG_WF_RX_HG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	13538;"	d
+SET_RG_WF_RX_HG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	13539;"	d
+SET_RG_WF_RX_HG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	13540;"	d
+SET_RG_WF_RX_HG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	13536;"	d
+SET_RG_WF_RX_HG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	13544;"	d
+SET_RG_WF_RX_HG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	13545;"	d
+SET_RG_WF_RX_HG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	13541;"	d
+SET_RG_WF_RX_HG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	13537;"	d
+SET_RG_WF_RX_HG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	13542;"	d
+SET_RG_WF_RX_HG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	13546;"	d
+SET_RG_WF_RX_LG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	13565;"	d
+SET_RG_WF_RX_LG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	13560;"	d
+SET_RG_WF_RX_LG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	13561;"	d
+SET_RG_WF_RX_LG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	13562;"	d
+SET_RG_WF_RX_LG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	13558;"	d
+SET_RG_WF_RX_LG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	13566;"	d
+SET_RG_WF_RX_LG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	13567;"	d
+SET_RG_WF_RX_LG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	13563;"	d
+SET_RG_WF_RX_LG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	13559;"	d
+SET_RG_WF_RX_LG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	13564;"	d
+SET_RG_WF_RX_LG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	13568;"	d
+SET_RG_WF_RX_MG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	13554;"	d
+SET_RG_WF_RX_MG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	13549;"	d
+SET_RG_WF_RX_MG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	13550;"	d
+SET_RG_WF_RX_MG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	13551;"	d
+SET_RG_WF_RX_MG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	13547;"	d
+SET_RG_WF_RX_MG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	13555;"	d
+SET_RG_WF_RX_MG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	13556;"	d
+SET_RG_WF_RX_MG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	13552;"	d
+SET_RG_WF_RX_MG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	13548;"	d
+SET_RG_WF_RX_MG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	13553;"	d
+SET_RG_WF_RX_MG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	13557;"	d
+SET_RG_WF_RX_OUTVCM	smac/hal/ssv6006c/ssv6006C_reg.h	13462;"	d
+SET_RG_WF_RX_TZ_CMZ_C	smac/hal/ssv6006c/ssv6006C_reg.h	13449;"	d
+SET_RG_WF_RX_TZ_CMZ_R	smac/hal/ssv6006c/ssv6006C_reg.h	13460;"	d
+SET_RG_WF_RX_ULG_DIV2_CORE	smac/hal/ssv6006c/ssv6006C_reg.h	13576;"	d
+SET_RG_WF_RX_ULG_LNAHGN_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	13571;"	d
+SET_RG_WF_RX_ULG_LNAHGP_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	13572;"	d
+SET_RG_WF_RX_ULG_LNALG_BIAS	smac/hal/ssv6006c/ssv6006C_reg.h	13573;"	d
+SET_RG_WF_RX_ULG_LNA_GC	smac/hal/ssv6006c/ssv6006C_reg.h	13569;"	d
+SET_RG_WF_RX_ULG_LOBUF	smac/hal/ssv6006c/ssv6006C_reg.h	13577;"	d
+SET_RG_WF_RX_ULG_TZI	smac/hal/ssv6006c/ssv6006C_reg.h	13578;"	d
+SET_RG_WF_RX_ULG_TZ_CAP	smac/hal/ssv6006c/ssv6006C_reg.h	13574;"	d
+SET_RG_WF_RX_ULG_TZ_GC	smac/hal/ssv6006c/ssv6006C_reg.h	13570;"	d
+SET_RG_WF_RX_ULG_TZ_GC_BOOST	smac/hal/ssv6006c/ssv6006C_reg.h	13575;"	d
+SET_RG_WF_RX_ULG_TZ_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	13579;"	d
+SET_RG_WF_TXLPF_BOOSTI	smac/hal/ssv6006c/ssv6006C_reg.h	13649;"	d
+SET_RG_WF_TXMOD_GMCELL_FINE	smac/hal/ssv6006c/ssv6006C_reg.h	13510;"	d
+SET_RG_WF_TXPGA_CAPSW	smac/hal/ssv6006c/ssv6006C_reg.h	13507;"	d
+SET_RG_WF_TX_DACI1ST	smac/hal/ssv6006c/ssv6006C_reg.h	13643;"	d
+SET_RG_WF_TX_DACLPF_ICOARSE	smac/hal/ssv6006c/ssv6006C_reg.h	13644;"	d
+SET_RG_WF_TX_DACLPF_IFINE	smac/hal/ssv6006c/ssv6006C_reg.h	13645;"	d
+SET_RG_WF_TX_DACLPF_VCM	smac/hal/ssv6006c/ssv6006C_reg.h	13646;"	d
+SET_RG_WF_TX_DAC_CKEDGE_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	13651;"	d
+SET_RG_WF_TX_DAC_IATTN	smac/hal/ssv6006c/ssv6006C_reg.h	13648;"	d
+SET_RG_WF_TX_DAC_IBIAS	smac/hal/ssv6006c/ssv6006C_reg.h	13647;"	d
+SET_RG_WF_TX_DAC_IOFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	13653;"	d
+SET_RG_WF_TX_DAC_OS	smac/hal/ssv6006c/ssv6006C_reg.h	13652;"	d
+SET_RG_WF_TX_DAC_QOFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	13654;"	d
+SET_RG_WF_TX_DAC_RCAL	smac/hal/ssv6006c/ssv6006C_reg.h	13650;"	d
+SET_RG_WF_TX_DIV_VSET	smac/hal/ssv6006c/ssv6006C_reg.h	13508;"	d
+SET_RG_WF_TX_GAIN_OFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	13530;"	d
+SET_RG_WF_TX_LOBUF_VSET	smac/hal/ssv6006c/ssv6006C_reg.h	13509;"	d
+SET_RG_WF_TX_PA1_VCAS	smac/hal/ssv6006c/ssv6006C_reg.h	13517;"	d
+SET_RG_WF_TX_PA2_VCAS	smac/hal/ssv6006c/ssv6006C_reg.h	13518;"	d
+SET_RG_WF_TX_PA3_VCAS	smac/hal/ssv6006c/ssv6006C_reg.h	13519;"	d
+SET_RG_WR_ACI_GAIN_INI_SEL_11B	include/ssv6200_reg.h	7591;"	d
+SET_RG_WR_ACI_GAIN_OW_11B	include/ssv6200_reg.h	7594;"	d
+SET_RG_WR_ACI_GAIN_SEL_11B	include/ssv6200_reg.h	7592;"	d
+SET_RG_WR_RFGC_INIT_EN	include/ssv6200_reg.h	7586;"	d
+SET_RG_WR_RFGC_INIT_SET	include/ssv6200_reg.h	7585;"	d
+SET_RG_WR_TX_EN_CNT_RST_N	include/ssv6200_reg.h	7765;"	d
+SET_RG_XOSC_CBANK_XI	include/ssv6200_reg.h	8342;"	d
+SET_RG_XOSC_CBANK_XO	include/ssv6200_reg.h	8341;"	d
+SET_RG_XO_CBANKI	smac/hal/ssv6006c/ssv6006C_reg.h	14949;"	d
+SET_RG_XO_CBANKI_SLP	smac/hal/ssv6006c/ssv6006C_reg.h	15065;"	d
+SET_RG_XO_CBANKO	smac/hal/ssv6006c/ssv6006C_reg.h	14950;"	d
+SET_RG_XO_CBANKO_SLP	smac/hal/ssv6006c/ssv6006C_reg.h	15066;"	d
+SET_RG_XO_LDO_LEVEL	smac/hal/ssv6006c/ssv6006C_reg.h	14944;"	d
+SET_RG_XO_TIMMER	smac/hal/ssv6006c/ssv6006C_reg.h	14964;"	d
+SET_RG_XSCOR16_RATIO	include/ssv6200_reg.h	7899;"	d
+SET_RG_XSCOR16_RATIO	smac/hal/ssv6006c/ssv6006C_reg.h	15528;"	d
+SET_RG_XSCOR16_SHORT_CNT_LMT	include/ssv6200_reg.h	7898;"	d
+SET_RG_XSCOR16_SHORT_CNT_LMT	smac/hal/ssv6006c/ssv6006C_reg.h	15527;"	d
+SET_RG_XSCOR32_RATIO	include/ssv6200_reg.h	7864;"	d
+SET_RG_XSCOR32_RATIO	smac/hal/ssv6006c/ssv6006C_reg.h	15457;"	d
+SET_RG_XSCOR64_CNT_LMT1	include/ssv6200_reg.h	7870;"	d
+SET_RG_XSCOR64_CNT_LMT1	smac/hal/ssv6006c/ssv6006C_reg.h	15463;"	d
+SET_RG_XSCOR64_CNT_LMT2	include/ssv6200_reg.h	7869;"	d
+SET_RG_XSCOR64_CNT_LMT2	smac/hal/ssv6006c/ssv6006C_reg.h	15462;"	d
+SET_RG_XSCOR64_RATIO_SB	smac/hal/ssv6006c/ssv6006C_reg.h	15536;"	d
+SET_RI	include/ssv6200_reg.h	5795;"	d
+SET_RI	smac/hal/ssv6006c/ssv6006C_reg.h	9786;"	d
+SET_RIP_A	smac/hal/ssv6006c/ssv6006C_reg.h	9808;"	d
+SET_RLS_ABT_ID	include/ssv6200_reg.h	8481;"	d
+SET_RLS_ABT_INT	include/ssv6200_reg.h	8482;"	d
+SET_RLS_BUSY	include/ssv6200_reg.h	7190;"	d
+SET_RLS_BUSY	smac/hal/ssv6006c/ssv6006C_reg.h	15645;"	d
+SET_RLS_COUNT	include/ssv6200_reg.h	7193;"	d
+SET_RLS_COUNT	smac/hal/ssv6006c/ssv6006C_reg.h	15648;"	d
+SET_RLS_COUNT_CLR	include/ssv6200_reg.h	7191;"	d
+SET_RLS_COUNT_CLR	smac/hal/ssv6006c/ssv6006C_reg.h	15646;"	d
+SET_RLS_ERR	include/ssv6200_reg.h	8487;"	d
+SET_RLS_ERR_CLR	smac/hal/ssv6006c/ssv6006C_reg.h	15951;"	d
+SET_RLS_ERR_ID	include/ssv6200_reg.h	8491;"	d
+SET_RLS_ERR_ID	smac/hal/ssv6006c/ssv6006C_reg.h	15955;"	d
+SET_RLS_ERR_STS	smac/hal/ssv6006c/ssv6006C_reg.h	15949;"	d
+SET_RL_STATE	include/ssv6200_reg.h	8489;"	d
+SET_RL_STATE	smac/hal/ssv6006c/ssv6006C_reg.h	15953;"	d
+SET_ROMCRC32_GOLDEN	smac/hal/ssv6006c/ssv6006C_reg.h	9563;"	d
+SET_ROMCRC32_RESULT	smac/hal/ssv6006c/ssv6006C_reg.h	9564;"	d
+SET_ROM_END_INDEX	smac/hal/ssv6006c/ssv6006C_reg.h	9562;"	d
+SET_ROM_READ_PROT	smac/hal/ssv6006c/ssv6006C_reg.h	9344;"	d
+SET_ROM_START_INDEX	smac/hal/ssv6006c/ssv6006C_reg.h	9561;"	d
+SET_ROP_A	smac/hal/ssv6006c/ssv6006C_reg.h	9807;"	d
+SET_RO_11B_CCA_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15412;"	d
+SET_RO_11B_CRC_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15407;"	d
+SET_RO_11B_CRC_CORRECT	smac/hal/ssv6006c/ssv6006C_reg.h	15417;"	d
+SET_RO_11B_FREQ_OS	smac/hal/ssv6006c/ssv6006C_reg.h	15404;"	d
+SET_RO_11B_LENGTH_FIELD	smac/hal/ssv6006c/ssv6006C_reg.h	15413;"	d
+SET_RO_11B_PACKET_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15411;"	d
+SET_RO_11B_PACKET_ERR	smac/hal/ssv6006c/ssv6006C_reg.h	15410;"	d
+SET_RO_11B_PACKET_ERR_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15409;"	d
+SET_RO_11B_RCPI	smac/hal/ssv6006c/ssv6006C_reg.h	15406;"	d
+SET_RO_11B_SERVICE_FIELD	smac/hal/ssv6006c/ssv6006C_reg.h	15416;"	d
+SET_RO_11B_SFD_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15408;"	d
+SET_RO_11B_SFD_FIELD	smac/hal/ssv6006c/ssv6006C_reg.h	15414;"	d
+SET_RO_11B_SIGNAL_FIELD	smac/hal/ssv6006c/ssv6006C_reg.h	15415;"	d
+SET_RO_11B_SNR	smac/hal/ssv6006c/ssv6006C_reg.h	15405;"	d
+SET_RO_11GN_CCA_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15582;"	d
+SET_RO_11GN_FREQ_OS_LTS	smac/hal/ssv6006c/ssv6006C_reg.h	15576;"	d
+SET_RO_11GN_HT_SIGNAL_FIELD_23_0	smac/hal/ssv6006c/ssv6006C_reg.h	15578;"	d
+SET_RO_11GN_HT_SIGNAL_FIELD_47_24	smac/hal/ssv6006c/ssv6006C_reg.h	15577;"	d
+SET_RO_11GN_L_SIGNAL_FIELD	smac/hal/ssv6006c/ssv6006C_reg.h	15583;"	d
+SET_RO_11GN_NOISE_PWR	smac/hal/ssv6006c/ssv6006C_reg.h	15573;"	d
+SET_RO_11GN_PACKET_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15581;"	d
+SET_RO_11GN_PACKET_ERR_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15579;"	d
+SET_RO_11GN_RCPI	smac/hal/ssv6006c/ssv6006C_reg.h	15574;"	d
+SET_RO_11GN_SERVICE_FIELD	smac/hal/ssv6006c/ssv6006C_reg.h	15580;"	d
+SET_RO_11GN_SIGNAL_PWR	smac/hal/ssv6006c/ssv6006C_reg.h	15575;"	d
+SET_RO_11GN_SNR	smac/hal/ssv6006c/ssv6006C_reg.h	15572;"	d
+SET_RO_2ND_ED_STATE	smac/hal/ssv6006c/ssv6006C_reg.h	15188;"	d
+SET_RO_5G_DCCAL_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	14554;"	d
+SET_RO_5G_RXIQ_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	14553;"	d
+SET_RO_5G_TXDC_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	14551;"	d
+SET_RO_5G_TXIQ_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	14552;"	d
+SET_RO_ABBPGA	smac/hal/ssv6006c/ssv6006C_reg.h	14601;"	d
+SET_RO_ACT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	10428;"	d
+SET_RO_AD_VBAT_OK	smac/hal/ssv6006c/ssv6006C_reg.h	15019;"	d
+SET_RO_AGC_START_80M	smac/hal/ssv6006c/ssv6006C_reg.h	15338;"	d
+SET_RO_AMPDU_PACKET_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15584;"	d
+SET_RO_AMPDU_PACKET_ERR_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15585;"	d
+SET_RO_AMP_O	include/ssv6200_reg.h	8032;"	d
+SET_RO_BIST_DONE_CCFO_0	smac/hal/ssv6006c/ssv6006C_reg.h	15507;"	d
+SET_RO_BIST_DONE_CCFO_1	smac/hal/ssv6006c/ssv6006C_reg.h	15505;"	d
+SET_RO_BIST_DONE_RX_FFT_0	smac/hal/ssv6006c/ssv6006C_reg.h	15331;"	d
+SET_RO_BIST_DONE_RX_FFT_1	smac/hal/ssv6006c/ssv6006C_reg.h	15329;"	d
+SET_RO_BIST_DONE_TX_FFT_0	smac/hal/ssv6006c/ssv6006C_reg.h	15429;"	d
+SET_RO_BIST_DONE_TX_FFT_1	smac/hal/ssv6006c/ssv6006C_reg.h	15427;"	d
+SET_RO_BIST_DONE_VTB_0	smac/hal/ssv6006c/ssv6006C_reg.h	15517;"	d
+SET_RO_BIST_DONE_VTB_1	smac/hal/ssv6006c/ssv6006C_reg.h	15515;"	d
+SET_RO_BIST_DONE_VTB_2	smac/hal/ssv6006c/ssv6006C_reg.h	15513;"	d
+SET_RO_BIST_DONE_VTB_3	smac/hal/ssv6006c/ssv6006C_reg.h	15511;"	d
+SET_RO_BIST_FAIL_CCFO_0	smac/hal/ssv6006c/ssv6006C_reg.h	15508;"	d
+SET_RO_BIST_FAIL_CCFO_1	smac/hal/ssv6006c/ssv6006C_reg.h	15506;"	d
+SET_RO_BIST_FAIL_RX_FFT_0	smac/hal/ssv6006c/ssv6006C_reg.h	15332;"	d
+SET_RO_BIST_FAIL_RX_FFT_1	smac/hal/ssv6006c/ssv6006C_reg.h	15330;"	d
+SET_RO_BIST_FAIL_TX_FFT_0	smac/hal/ssv6006c/ssv6006C_reg.h	15430;"	d
+SET_RO_BIST_FAIL_TX_FFT_1	smac/hal/ssv6006c/ssv6006C_reg.h	15428;"	d
+SET_RO_BIST_FAIL_VTB_0	smac/hal/ssv6006c/ssv6006C_reg.h	15518;"	d
+SET_RO_BIST_FAIL_VTB_1	smac/hal/ssv6006c/ssv6006C_reg.h	15516;"	d
+SET_RO_BIST_FAIL_VTB_2	smac/hal/ssv6006c/ssv6006C_reg.h	15514;"	d
+SET_RO_BIST_FAIL_VTB_3	smac/hal/ssv6006c/ssv6006C_reg.h	15512;"	d
+SET_RO_BT_DCCAL_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	14546;"	d
+SET_RO_CAND_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	10429;"	d
+SET_RO_CCA_PWR_MA_11B	include/ssv6200_reg.h	7604;"	d
+SET_RO_CCA_PWR_MA_11B	smac/hal/ssv6006c/ssv6006C_reg.h	15186;"	d
+SET_RO_CCA_PWR_MA_11GN	include/ssv6200_reg.h	7602;"	d
+SET_RO_CCA_PWR_MA_11GN_HT20	smac/hal/ssv6006c/ssv6006C_reg.h	15185;"	d
+SET_RO_CCA_PWR_MA_11GN_HT40	smac/hal/ssv6006c/ssv6006C_reg.h	15184;"	d
+SET_RO_CSTATE_AGC	smac/hal/ssv6006c/ssv6006C_reg.h	15337;"	d
+SET_RO_CSTATE_PKT	smac/hal/ssv6006c/ssv6006C_reg.h	15335;"	d
+SET_RO_CSTATE_RX	smac/hal/ssv6006c/ssv6006C_reg.h	15339;"	d
+SET_RO_CSTATE_TX	smac/hal/ssv6006c/ssv6006C_reg.h	15341;"	d
+SET_RO_DA_RX_AGC	smac/hal/ssv6006c/ssv6006C_reg.h	14603;"	d
+SET_RO_DC_CAL_I	smac/hal/ssv6006c/ssv6006C_reg.h	14609;"	d
+SET_RO_DC_CAL_Q	smac/hal/ssv6006c/ssv6006C_reg.h	14608;"	d
+SET_RO_DPD_GAIN	include/ssv6200_reg.h	8110;"	d
+SET_RO_EDCCA_PRIMARY_PRD	smac/hal/ssv6006c/ssv6006C_reg.h	15217;"	d
+SET_RO_EDCCA_SECONDARY_PRD	smac/hal/ssv6006c/ssv6006C_reg.h	15219;"	d
+SET_RO_ED_STATE	include/ssv6200_reg.h	7603;"	d
+SET_RO_ED_STATE	smac/hal/ssv6006c/ssv6006C_reg.h	15187;"	d
+SET_RO_FDB_CDELAY	smac/hal/ssv6006c/ssv6006C_reg.h	14995;"	d
+SET_RO_FDB_FDELAY	smac/hal/ssv6006c/ssv6006C_reg.h	14996;"	d
+SET_RO_FDB_PHASESWAP	smac/hal/ssv6006c/ssv6006C_reg.h	14997;"	d
+SET_RO_FFT_ENRG_RDY	include/ssv6200_reg.h	8028;"	d
+SET_RO_FREQ_OS_LTS	include/ssv6200_reg.h	7951;"	d
+SET_RO_FSM_MTXDMA	smac/hal/ssv6006c/ssv6006C_reg.h	10432;"	d
+SET_RO_FSM_MTXHALT	smac/hal/ssv6006c/ssv6006C_reg.h	10431;"	d
+SET_RO_FSM_MTXPHYTX	smac/hal/ssv6006c/ssv6006C_reg.h	10433;"	d
+SET_RO_FSM_MTXPTC	smac/hal/ssv6006c/ssv6006C_reg.h	10427;"	d
+SET_RO_GAIN_EST_RDY	include/ssv6200_reg.h	8031;"	d
+SET_RO_GAIN_TX	smac/hal/ssv6006c/ssv6006C_reg.h	14600;"	d
+SET_RO_GEMINIA_BT_DCCAL_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	11792;"	d
+SET_RO_GEMINIA_FDB_CDELAY	smac/hal/ssv6006c/ssv6006C_reg.h	11862;"	d
+SET_RO_GEMINIA_FDB_FDELAY	smac/hal/ssv6006c/ssv6006C_reg.h	11863;"	d
+SET_RO_GEMINIA_FDB_PHASESWAP	smac/hal/ssv6006c/ssv6006C_reg.h	11864;"	d
+SET_RO_GEMINIA_PMU_WAKE_TRIG_EVENT	smac/hal/ssv6006c/ssv6006C_reg.h	11854;"	d
+SET_RO_GEMINIA_RCCAL_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	11793;"	d
+SET_RO_GEMINIA_RTC_INT_ALARM	smac/hal/ssv6006c/ssv6006C_reg.h	11859;"	d
+SET_RO_GEMINIA_RTC_INT_SEC	smac/hal/ssv6006c/ssv6006C_reg.h	11858;"	d
+SET_RO_GEMINIA_RTC_OSC_CAL_RES_RDY	smac/hal/ssv6006c/ssv6006C_reg.h	11847;"	d
+SET_RO_GEMINIA_RTC_OSC_RES_SW	smac/hal/ssv6006c/ssv6006C_reg.h	11846;"	d
+SET_RO_GEMINIA_RTC_TICK_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	11855;"	d
+SET_RO_GEMINIA_RXIQ_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	11796;"	d
+SET_RO_GEMINIA_TXDC_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	11794;"	d
+SET_RO_GEMINIA_TXIQ_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	11795;"	d
+SET_RO_GEMINIA_WF_DCCAL_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	11791;"	d
+SET_RO_GP_DIV_RDY	include/ssv6200_reg.h	8030;"	d
+SET_RO_HS3W_SX_CHANNEL	smac/hal/ssv6006c/ssv6006C_reg.h	14598;"	d
+SET_RO_HS3W_SX_RFCH_MAP_EN	smac/hal/ssv6006c/ssv6006C_reg.h	14599;"	d
+SET_RO_HS3W_SX_RFCTRL_CH	smac/hal/ssv6006c/ssv6006C_reg.h	14604;"	d
+SET_RO_HS3W_SX_RFCTRL_F	smac/hal/ssv6006c/ssv6006C_reg.h	14605;"	d
+SET_RO_HT_MCS_40M	include/ssv6200_reg.h	7960;"	d
+SET_RO_IFSAIR1	smac/hal/ssv6006c/ssv6006C_reg.h	10486;"	d
+SET_RO_IFSAIR2	smac/hal/ssv6006c/ssv6006C_reg.h	10487;"	d
+SET_RO_IFSST0	smac/hal/ssv6006c/ssv6006C_reg.h	10533;"	d
+SET_RO_IFSST1	smac/hal/ssv6006c/ssv6006C_reg.h	10534;"	d
+SET_RO_IFSST2	smac/hal/ssv6006c/ssv6006C_reg.h	10535;"	d
+SET_RO_IFSST3	smac/hal/ssv6006c/ssv6006C_reg.h	10536;"	d
+SET_RO_INTRP_RX_BEACON_LOSS	smac/hal/ssv6006c/ssv6006C_reg.h	15320;"	d
+SET_RO_INTRP_RX_LOSS	smac/hal/ssv6006c/ssv6006C_reg.h	15318;"	d
+SET_RO_INTRUP_RX_11B	smac/hal/ssv6006c/ssv6006C_reg.h	15403;"	d
+SET_RO_INTRUP_RX_11GN	smac/hal/ssv6006c/ssv6006C_reg.h	15569;"	d
+SET_RO_IQCAL_ALPHA_ESTM_RDY	include/ssv6200_reg.h	8025;"	d
+SET_RO_IQCAL_DC_RDY	include/ssv6200_reg.h	8026;"	d
+SET_RO_IQCAL_IQCOL_RDY	include/ssv6200_reg.h	8024;"	d
+SET_RO_IQCAL_MULT_RDY	include/ssv6200_reg.h	8027;"	d
+SET_RO_IQCAL_O	include/ssv6200_reg.h	8022;"	d
+SET_RO_IQCAL_SPRM_RDY	include/ssv6200_reg.h	8023;"	d
+SET_RO_I_DC_OUT	smac/hal/ssv6006c/ssv6006C_reg.h	15209;"	d
+SET_RO_L_RATE_40M	include/ssv6200_reg.h	7961;"	d
+SET_RO_MAC_PHY_TRX_EN_SYNC	smac/hal/ssv6006c/ssv6006C_reg.h	15342;"	d
+SET_RO_MAC_TX_FIFO_WEMPTY	smac/hal/ssv6006c/ssv6006C_reg.h	10526;"	d
+SET_RO_MAC_TX_FIFO_WFULL_MX	smac/hal/ssv6006c/ssv6006C_reg.h	10525;"	d
+SET_RO_MAC_TX_FIFO_WINC	smac/hal/ssv6006c/ssv6006C_reg.h	10524;"	d
+SET_RO_MODE_REG_OUT_16	include/ssv6200_reg.h	7702;"	d
+SET_RO_MODE_REG_OUT_64	include/ssv6200_reg.h	7943;"	d
+SET_RO_MODE_REG_OUT_80	include/ssv6200_reg.h	7940;"	d
+SET_RO_MODE_REG_SO_16	include/ssv6200_reg.h	7703;"	d
+SET_RO_MODE_REG_SO_64	include/ssv6200_reg.h	7944;"	d
+SET_RO_MODE_REG_SO_80	include/ssv6200_reg.h	7941;"	d
+SET_RO_MONITOR_BUS_16	include/ssv6200_reg.h	7704;"	d
+SET_RO_MONITOR_BUS_64	include/ssv6200_reg.h	7945;"	d
+SET_RO_MONITOR_BUS_80	include/ssv6200_reg.h	7942;"	d
+SET_RO_MRX_EN_CNT	include/ssv6200_reg.h	7667;"	d
+SET_RO_MRX_EN_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15213;"	d
+SET_RO_MRX_LEN_CNT_0	include/ssv6200_reg.h	7694;"	d
+SET_RO_MRX_LEN_CNT_0	smac/hal/ssv6006c/ssv6006C_reg.h	15240;"	d
+SET_RO_MRX_LEN_CNT_1	include/ssv6200_reg.h	7693;"	d
+SET_RO_MRX_LEN_CNT_1	smac/hal/ssv6006c/ssv6006C_reg.h	15239;"	d
+SET_RO_MRX_RX_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15336;"	d
+SET_RO_MRX_TYPE_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15245;"	d
+SET_RO_MRX_TYPE_CNT_0	include/ssv6200_reg.h	7712;"	d
+SET_RO_MRX_TYPE_CNT_1	include/ssv6200_reg.h	7711;"	d
+SET_RO_MTXDMA_CMD	smac/hal/ssv6006c/ssv6006C_reg.h	10434;"	d
+SET_RO_MTX_BASE1	smac/hal/ssv6006c/ssv6006C_reg.h	10538;"	d
+SET_RO_MTX_BASE2	smac/hal/ssv6006c/ssv6006C_reg.h	10539;"	d
+SET_RO_MTX_BASE3	smac/hal/ssv6006c/ssv6006C_reg.h	10540;"	d
+SET_RO_MTX_LEN_CNT_0	include/ssv6200_reg.h	7692;"	d
+SET_RO_MTX_LEN_CNT_0	smac/hal/ssv6006c/ssv6006C_reg.h	15238;"	d
+SET_RO_MTX_LEN_CNT_1	include/ssv6200_reg.h	7691;"	d
+SET_RO_MTX_LEN_CNT_1	smac/hal/ssv6006c/ssv6006C_reg.h	15237;"	d
+SET_RO_MTX_TX_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10523;"	d
+SET_RO_MTX_TYPE_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15246;"	d
+SET_RO_MTX_TYPE_CNT_0	include/ssv6200_reg.h	7710;"	d
+SET_RO_MTX_TYPE_CNT_1	include/ssv6200_reg.h	7709;"	d
+SET_RO_PACKET_ERR_CNT	include/ssv6200_reg.h	7847;"	d
+SET_RO_PERIOD_ARRAY_0	smac/hal/ssv6006c/ssv6006C_reg.h	15624;"	d
+SET_RO_PERIOD_ARRAY_1	smac/hal/ssv6006c/ssv6006C_reg.h	15625;"	d
+SET_RO_PERIOD_ARRAY_2	smac/hal/ssv6006c/ssv6006C_reg.h	15626;"	d
+SET_RO_PERIOD_ARRAY_3	smac/hal/ssv6006c/ssv6006C_reg.h	15627;"	d
+SET_RO_PERIOD_ARRAY_4	smac/hal/ssv6006c/ssv6006C_reg.h	15628;"	d
+SET_RO_PERIOD_ARRAY_5	smac/hal/ssv6006c/ssv6006C_reg.h	15629;"	d
+SET_RO_PGAGC_FF1	include/ssv6200_reg.h	7607;"	d
+SET_RO_PGAGC_FF1	smac/hal/ssv6006c/ssv6006C_reg.h	15191;"	d
+SET_RO_PGAGC_FF2	include/ssv6200_reg.h	7611;"	d
+SET_RO_PGAGC_FF2	smac/hal/ssv6006c/ssv6006C_reg.h	15195;"	d
+SET_RO_PGAGC_FF3	include/ssv6200_reg.h	7615;"	d
+SET_RO_PGAGC_FF3	smac/hal/ssv6006c/ssv6006C_reg.h	15199;"	d
+SET_RO_PGA_PWR_FF1	include/ssv6200_reg.h	7605;"	d
+SET_RO_PGA_PWR_FF1	smac/hal/ssv6006c/ssv6006C_reg.h	15189;"	d
+SET_RO_PGA_PWR_FF2	include/ssv6200_reg.h	7609;"	d
+SET_RO_PGA_PWR_FF2	smac/hal/ssv6006c/ssv6006C_reg.h	15193;"	d
+SET_RO_PGA_PWR_FF3	include/ssv6200_reg.h	7613;"	d
+SET_RO_PGA_PWR_FF3	smac/hal/ssv6006c/ssv6006C_reg.h	15197;"	d
+SET_RO_PHEST_RDY	include/ssv6200_reg.h	8029;"	d
+SET_RO_PHYTXIP_TIMEOUT_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	10483;"	d
+SET_RO_PMU_STATE	smac/hal/ssv6006c/ssv6006C_reg.h	15018;"	d
+SET_RO_PMU_WAKE_TRIG_EVENT	smac/hal/ssv6006c/ssv6006C_reg.h	15010;"	d
+SET_RO_PRE_DC_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	14555;"	d
+SET_RO_PRIMARY_EDCCA	smac/hal/ssv6006c/ssv6006C_reg.h	15218;"	d
+SET_RO_PTC_SCHEDULE	smac/hal/ssv6006c/ssv6006C_reg.h	10426;"	d
+SET_RO_PW	smac/hal/ssv6006c/ssv6006C_reg.h	15617;"	d
+SET_RO_PW_ARRAY_0	smac/hal/ssv6006c/ssv6006C_reg.h	15618;"	d
+SET_RO_PW_ARRAY_1	smac/hal/ssv6006c/ssv6006C_reg.h	15619;"	d
+SET_RO_PW_ARRAY_2	smac/hal/ssv6006c/ssv6006C_reg.h	15620;"	d
+SET_RO_PW_ARRAY_3	smac/hal/ssv6006c/ssv6006C_reg.h	15621;"	d
+SET_RO_PW_ARRAY_4	smac/hal/ssv6006c/ssv6006C_reg.h	15622;"	d
+SET_RO_PW_ARRAY_5	smac/hal/ssv6006c/ssv6006C_reg.h	15623;"	d
+SET_RO_Q_DC_OUT	smac/hal/ssv6006c/ssv6006C_reg.h	15208;"	d
+SET_RO_RADAR_DET_NUM	smac/hal/ssv6006c/ssv6006C_reg.h	15614;"	d
+SET_RO_RADAR_DET_OUT	smac/hal/ssv6006c/ssv6006C_reg.h	15615;"	d
+SET_RO_RADAR_VALID	smac/hal/ssv6006c/ssv6006C_reg.h	15616;"	d
+SET_RO_RCCAL_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	14547;"	d
+SET_RO_REFREG_KHZ_OUT	smac/hal/ssv6006c/ssv6006C_reg.h	14606;"	d
+SET_RO_RFGC_FF1	include/ssv6200_reg.h	7608;"	d
+SET_RO_RFGC_FF1	smac/hal/ssv6006c/ssv6006C_reg.h	15192;"	d
+SET_RO_RFGC_FF2	include/ssv6200_reg.h	7612;"	d
+SET_RO_RFGC_FF2	smac/hal/ssv6006c/ssv6006C_reg.h	15196;"	d
+SET_RO_RFGC_FF3	include/ssv6200_reg.h	7616;"	d
+SET_RO_RFGC_FF3	smac/hal/ssv6006c/ssv6006C_reg.h	15200;"	d
+SET_RO_RFPGA	smac/hal/ssv6006c/ssv6006C_reg.h	14602;"	d
+SET_RO_RF_CH_FREQ	smac/hal/ssv6006c/ssv6006C_reg.h	14607;"	d
+SET_RO_RF_PHY_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	14597;"	d
+SET_RO_RF_PWR_FF1	include/ssv6200_reg.h	7606;"	d
+SET_RO_RF_PWR_FF1	smac/hal/ssv6006c/ssv6006C_reg.h	15190;"	d
+SET_RO_RF_PWR_FF2	include/ssv6200_reg.h	7610;"	d
+SET_RO_RF_PWR_FF2	smac/hal/ssv6006c/ssv6006C_reg.h	15194;"	d
+SET_RO_RF_PWR_FF3	include/ssv6200_reg.h	7614;"	d
+SET_RO_RF_PWR_FF3	smac/hal/ssv6006c/ssv6006C_reg.h	15198;"	d
+SET_RO_RTC_INT_ALARM	smac/hal/ssv6006c/ssv6006C_reg.h	15012;"	d
+SET_RO_RTC_INT_SEC	smac/hal/ssv6006c/ssv6006C_reg.h	15011;"	d
+SET_RO_RTC_OSC_CAL_RES_RDY	smac/hal/ssv6006c/ssv6006C_reg.h	14999;"	d
+SET_RO_RTC_OSC_RES_SW	smac/hal/ssv6006c/ssv6006C_reg.h	15000;"	d
+SET_RO_RTC_TICK_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15007;"	d
+SET_RO_RXIQ_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	14550;"	d
+SET_RO_RX_AMP	smac/hal/ssv6006c/ssv6006C_reg.h	14840;"	d
+SET_RO_RX_BEACON_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15322;"	d
+SET_RO_RX_BEACON_LOSS_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15321;"	d
+SET_RO_RX_FIFO_FULL_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15325;"	d
+SET_RO_RX_IQ_ALPHA	smac/hal/ssv6006c/ssv6006C_reg.h	14562;"	d
+SET_RO_RX_IQ_THETA	smac/hal/ssv6006c/ssv6006C_reg.h	14561;"	d
+SET_RO_RX_PHI	smac/hal/ssv6006c/ssv6006C_reg.h	14839;"	d
+SET_RO_RX_PKT_TIMER	smac/hal/ssv6006c/ssv6006C_reg.h	15319;"	d
+SET_RO_SECONDARY_EDCCA	smac/hal/ssv6006c/ssv6006C_reg.h	15220;"	d
+SET_RO_SPECTRUM_DATA	include/ssv6200_reg.h	7946;"	d
+SET_RO_SPECTRUM_IQ_PWR_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	14573;"	d
+SET_RO_SPECTRUM_IQ_PWR_39_32	smac/hal/ssv6006c/ssv6006C_reg.h	14570;"	d
+SET_RO_STBC_PACKET_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15570;"	d
+SET_RO_STBC_PACKET_ERR_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15571;"	d
+SET_RO_TBUS_O	include/ssv6200_reg.h	7718;"	d
+SET_RO_TURISMO_TRX_5G_DCCAL_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	13141;"	d
+SET_RO_TURISMO_TRX_5G_RXIQ_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	13140;"	d
+SET_RO_TURISMO_TRX_5G_TXDC_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	13138;"	d
+SET_RO_TURISMO_TRX_5G_TXIQ_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	13139;"	d
+SET_RO_TURISMO_TRX_AD_VBAT_OK	smac/hal/ssv6006c/ssv6006C_reg.h	13254;"	d
+SET_RO_TURISMO_TRX_BT_DCCAL_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	13133;"	d
+SET_RO_TURISMO_TRX_DC_CAL_I	smac/hal/ssv6006c/ssv6006C_reg.h	13181;"	d
+SET_RO_TURISMO_TRX_DC_CAL_Q	smac/hal/ssv6006c/ssv6006C_reg.h	13180;"	d
+SET_RO_TURISMO_TRX_FDB_CDELAY	smac/hal/ssv6006c/ssv6006C_reg.h	13230;"	d
+SET_RO_TURISMO_TRX_FDB_FDELAY	smac/hal/ssv6006c/ssv6006C_reg.h	13231;"	d
+SET_RO_TURISMO_TRX_FDB_PHASESWAP	smac/hal/ssv6006c/ssv6006C_reg.h	13232;"	d
+SET_RO_TURISMO_TRX_PMU_STATE	smac/hal/ssv6006c/ssv6006C_reg.h	13253;"	d
+SET_RO_TURISMO_TRX_PMU_WAKE_TRIG_EVENT	smac/hal/ssv6006c/ssv6006C_reg.h	13245;"	d
+SET_RO_TURISMO_TRX_PRE_DC_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	13142;"	d
+SET_RO_TURISMO_TRX_RCCAL_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	13134;"	d
+SET_RO_TURISMO_TRX_RTC_INT_ALARM	smac/hal/ssv6006c/ssv6006C_reg.h	13247;"	d
+SET_RO_TURISMO_TRX_RTC_INT_SEC	smac/hal/ssv6006c/ssv6006C_reg.h	13246;"	d
+SET_RO_TURISMO_TRX_RTC_OSC_CAL_RES_RDY	smac/hal/ssv6006c/ssv6006C_reg.h	13234;"	d
+SET_RO_TURISMO_TRX_RTC_OSC_RES_SW	smac/hal/ssv6006c/ssv6006C_reg.h	13235;"	d
+SET_RO_TURISMO_TRX_RTC_TICK_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	13242;"	d
+SET_RO_TURISMO_TRX_RXIQ_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	13137;"	d
+SET_RO_TURISMO_TRX_RX_IQ_ALPHA	smac/hal/ssv6006c/ssv6006C_reg.h	13150;"	d
+SET_RO_TURISMO_TRX_RX_IQ_THETA	smac/hal/ssv6006c/ssv6006C_reg.h	13149;"	d
+SET_RO_TURISMO_TRX_SPECTRUM_IQ_PWR_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	13161;"	d
+SET_RO_TURISMO_TRX_SPECTRUM_IQ_PWR_39_32	smac/hal/ssv6006c/ssv6006C_reg.h	13158;"	d
+SET_RO_TURISMO_TRX_TXDC_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	13135;"	d
+SET_RO_TURISMO_TRX_TXIQ_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	13136;"	d
+SET_RO_TURISMO_TRX_TX_IQ_ALPHA	smac/hal/ssv6006c/ssv6006C_reg.h	13152;"	d
+SET_RO_TURISMO_TRX_TX_IQ_THETA	smac/hal/ssv6006c/ssv6006C_reg.h	13151;"	d
+SET_RO_TURISMO_TRX_WF_DCCAL_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	13132;"	d
+SET_RO_TURISMO_TRX_XO_RDY	smac/hal/ssv6006c/ssv6006C_reg.h	13233;"	d
+SET_RO_TXDC_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	14548;"	d
+SET_RO_TXIQ_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	14549;"	d
+SET_RO_TXOP_INTERVAL	smac/hal/ssv6006c/ssv6006C_reg.h	10435;"	d
+SET_RO_TX_CNT	include/ssv6200_reg.h	7767;"	d
+SET_RO_TX_CNT_R	include/ssv6200_reg.h	7846;"	d
+SET_RO_TX_CNT_R_11B_TX	smac/hal/ssv6006c/ssv6006C_reg.h	15347;"	d
+SET_RO_TX_CNT_R_11GN_TX	smac/hal/ssv6006c/ssv6006C_reg.h	15443;"	d
+SET_RO_TX_DES_EXCP_CH_BW_CNT	include/ssv6200_reg.h	7647;"	d
+SET_RO_TX_DES_EXCP_MODE_CNT	include/ssv6200_reg.h	7648;"	d
+SET_RO_TX_DES_EXCP_RATE_CNT	include/ssv6200_reg.h	7646;"	d
+SET_RO_TX_EN_CNT	include/ssv6200_reg.h	7766;"	d
+SET_RO_TX_FIFO_EMPTY_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	15326;"	d
+SET_RO_TX_IP	smac/hal/ssv6006c/ssv6006C_reg.h	15340;"	d
+SET_RO_TX_IQ_ALPHA	smac/hal/ssv6006c/ssv6006C_reg.h	14564;"	d
+SET_RO_TX_IQ_THETA	smac/hal/ssv6006c/ssv6006C_reg.h	14563;"	d
+SET_RO_WAIT_RESPONSE_PHASE	smac/hal/ssv6006c/ssv6006C_reg.h	10430;"	d
+SET_RO_WF_DCCAL_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	14545;"	d
+SET_RO_XO_RDY	smac/hal/ssv6006c/ssv6006C_reg.h	14998;"	d
+SET_RTC_CAL_ENA	include/ssv6200_reg.h	6084;"	d
+SET_RTC_CAL_RDY	include/ssv6200_reg.h	8420;"	d
+SET_RTC_EN	include/ssv6200_reg.h	6089;"	d
+SET_RTC_INT_ALARM	include/ssv6200_reg.h	6095;"	d
+SET_RTC_INT_ALARM_MASK	include/ssv6200_reg.h	6093;"	d
+SET_RTC_INT_SEC	include/ssv6200_reg.h	6094;"	d
+SET_RTC_INT_SEC_MASK	include/ssv6200_reg.h	6092;"	d
+SET_RTC_OSC_CAL_RES_RDY	include/ssv6200_reg.h	6078;"	d
+SET_RTC_SEC_ALARM_VALUE	include/ssv6200_reg.h	6098;"	d
+SET_RTC_SEC_CNT	include/ssv6200_reg.h	6097;"	d
+SET_RTC_SEC_START_CNT	include/ssv6200_reg.h	6096;"	d
+SET_RTC_SRC	include/ssv6200_reg.h	6090;"	d
+SET_RTC_TICK_CNT	include/ssv6200_reg.h	6091;"	d
+SET_RTC_TIMER_WAKE_PMU_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9428;"	d
+SET_RTHR_H	include/ssv6200_reg.h	5799;"	d
+SET_RTHR_H	smac/hal/ssv6006c/ssv6006C_reg.h	9790;"	d
+SET_RTHR_L	include/ssv6200_reg.h	5798;"	d
+SET_RTHR_L	smac/hal/ssv6006c/ssv6006C_reg.h	9789;"	d
+SET_RTN_COUNT	include/ssv6200_reg.h	7194;"	d
+SET_RTN_COUNT	smac/hal/ssv6006c/ssv6006C_reg.h	15649;"	d
+SET_RTN_COUNT_CLR	include/ssv6200_reg.h	7192;"	d
+SET_RTN_COUNT_CLR	smac/hal/ssv6006c/ssv6006C_reg.h	15647;"	d
+SET_RTS	include/ssv6200_reg.h	5777;"	d
+SET_RTS	smac/hal/ssv6006c/ssv6006C_reg.h	9767;"	d
+SET_RW_BUF_CLR	smac/hal/ssv6006c/ssv6006C_reg.h	9908;"	d
+SET_RXFIFO_RST	include/ssv6200_reg.h	5763;"	d
+SET_RXFIFO_RST	smac/hal/ssv6006c/ssv6006C_reg.h	9753;"	d
+SET_RXFIFO_TRGLVL	include/ssv6200_reg.h	5768;"	d
+SET_RXFIFO_TRGLVL	smac/hal/ssv6006c/ssv6006C_reg.h	9758;"	d
+SET_RXFULLFLAG	smac/hal/ssv6006c/ssv6006C_reg.h	9253;"	d
+SET_RXID_ALC_CNT_FAIL	include/ssv6200_reg.h	6846;"	d
+SET_RXID_ALC_CNT_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	10958;"	d
+SET_RXID_ALC_LEN_FAIL	include/ssv6200_reg.h	6847;"	d
+SET_RXID_ALC_LEN_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	10959;"	d
+SET_RXNOTEMPTYFLAG	smac/hal/ssv6006c/ssv6006C_reg.h	9252;"	d
+SET_RXTRAP_ETHTYPE0	include/ssv6200_reg.h	6145;"	d
+SET_RXTRAP_ETHTYPE0	smac/hal/ssv6006c/ssv6006C_reg.h	10141;"	d
+SET_RXTRAP_ETHTYPE1	include/ssv6200_reg.h	6144;"	d
+SET_RXTRAP_ETHTYPE1	smac/hal/ssv6006c/ssv6006C_reg.h	10140;"	d
+SET_RX_2_HOST	include/ssv6200_reg.h	6115;"	d
+SET_RX_2_HOST	smac/hal/ssv6006c/ssv6006C_reg.h	10094;"	d
+SET_RX_ACCU_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	10114;"	d
+SET_RX_AGG_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	10185;"	d
+SET_RX_AGG_METHOD_3	smac/hal/ssv6006c/ssv6006C_reg.h	10186;"	d
+SET_RX_AGG_TIMER_RELOAD_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	10187;"	d
+SET_RX_CS_DUR	include/ssv6200_reg.h	6459;"	d
+SET_RX_DEBUG_HCI_EXP_0	smac/hal/ssv6006c/ssv6006C_reg.h	10181;"	d
+SET_RX_DEBUG_HCI_EXP_0_LENGHT_LIMIT_MAX	smac/hal/ssv6006c/ssv6006C_reg.h	10184;"	d
+SET_RX_DEBUG_HCI_EXP_0_LENGHT_LIMIT_MIN	smac/hal/ssv6006c/ssv6006C_reg.h	10183;"	d
+SET_RX_DEBUG_HCI_EXP_0_RND_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	10182;"	d
+SET_RX_EN_DUR	include/ssv6200_reg.h	6458;"	d
+SET_RX_ETHER_TRAP_EN	include/ssv6200_reg.h	6124;"	d
+SET_RX_ETHER_TRAP_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10103;"	d
+SET_RX_FIFO_FAIL	include/ssv6200_reg.h	5698;"	d
+SET_RX_FIFO_RESIDUE	include/ssv6200_reg.h	5725;"	d
+SET_RX_FIFO_TO	smac/hal/ssv6006c/ssv6006C_reg.h	9798;"	d
+SET_RX_FLOW_CTRL	include/ssv6200_reg.h	6326;"	d
+SET_RX_FLOW_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	10330;"	d
+SET_RX_FLOW_DATA	include/ssv6200_reg.h	6324;"	d
+SET_RX_FLOW_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	10328;"	d
+SET_RX_FLOW_MNG	include/ssv6200_reg.h	6325;"	d
+SET_RX_FLOW_MNG	smac/hal/ssv6006c/ssv6006C_reg.h	10329;"	d
+SET_RX_GET_TX_QUEUE_EN	include/ssv6200_reg.h	6126;"	d
+SET_RX_HOST_FAIL	include/ssv6200_reg.h	5699;"	d
+SET_RX_IDLE	smac/hal/ssv6006c/ssv6006C_reg.h	9792;"	d
+SET_RX_ID_ALC_LEN	include/ssv6200_reg.h	7455;"	d
+SET_RX_ID_ALC_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	15899;"	d
+SET_RX_ID_COUNT	include/ssv6200_reg.h	7431;"	d
+SET_RX_ID_COUNT	smac/hal/ssv6006c/ssv6006C_reg.h	15875;"	d
+SET_RX_ID_IFO_LEN	include/ssv6200_reg.h	7492;"	d
+SET_RX_ID_IFO_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	15938;"	d
+SET_RX_ID_LEN_THOLD	include/ssv6200_reg.h	5907;"	d
+SET_RX_ID_LEN_THOLD_INT	include/ssv6200_reg.h	7449;"	d
+SET_RX_ID_LEN_THOLD_INT	smac/hal/ssv6006c/ssv6006C_reg.h	15893;"	d
+SET_RX_ID_LEN_THOLD_SD	include/ssv6200_reg.h	5976;"	d
+SET_RX_ID_TB0	include/ssv6200_reg.h	7441;"	d
+SET_RX_ID_TB0	smac/hal/ssv6006c/ssv6006C_reg.h	15885;"	d
+SET_RX_ID_TB1	include/ssv6200_reg.h	7442;"	d
+SET_RX_ID_TB1	smac/hal/ssv6006c/ssv6006C_reg.h	15886;"	d
+SET_RX_ID_TB2	include/ssv6200_reg.h	7478;"	d
+SET_RX_ID_TB2	smac/hal/ssv6006c/ssv6006C_reg.h	15922;"	d
+SET_RX_ID_TB3	include/ssv6200_reg.h	7479;"	d
+SET_RX_ID_TB3	smac/hal/ssv6006c/ssv6006C_reg.h	15923;"	d
+SET_RX_ID_THOLD	include/ssv6200_reg.h	7433;"	d
+SET_RX_ID_THOLD	smac/hal/ssv6006c/ssv6006C_reg.h	15877;"	d
+SET_RX_INFO_SIZE	include/ssv6200_reg.h	6138;"	d
+SET_RX_INFO_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	10126;"	d
+SET_RX_INT	include/ssv6200_reg.h	5519;"	d
+SET_RX_INT	smac/hal/ssv6006c/ssv6006C_reg.h	9582;"	d
+SET_RX_INT1	include/ssv6200_reg.h	5547;"	d
+SET_RX_INT3	include/ssv6200_reg.h	5630;"	d
+SET_RX_INT_CH	include/ssv6200_reg.h	7435;"	d
+SET_RX_INT_CH	smac/hal/ssv6006c/ssv6006C_reg.h	15879;"	d
+SET_RX_INT_TIMEOUT	smac/hal/ssv6006c/ssv6006C_reg.h	10119;"	d
+SET_RX_LAST_PHY_SIZE	include/ssv6200_reg.h	6139;"	d
+SET_RX_LAST_PHY_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	10127;"	d
+SET_RX_LEN	include/ssv6200_reg.h	5707;"	d
+SET_RX_LINESTS_IE	include/ssv6200_reg.h	5758;"	d
+SET_RX_LINESTS_IE	smac/hal/ssv6006c/ssv6006C_reg.h	9748;"	d
+SET_RX_MOUNT	include/ssv6200_reg.h	8499;"	d
+SET_RX_NULL_TRAP_EN	include/ssv6200_reg.h	6125;"	d
+SET_RX_NULL_TRAP_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10104;"	d
+SET_RX_PACKET_LENGTH	include/ssv6200_reg.h	5538;"	d
+SET_RX_PACKET_LENGTH2	include/ssv6200_reg.h	5546;"	d
+SET_RX_PACKET_LENGTH3	include/ssv6200_reg.h	5629;"	d
+SET_RX_PER_RD_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	10130;"	d
+SET_RX_PHY_11B_SOFT_RST_N	include/ssv6200_reg.h	7836;"	d
+SET_RX_PHY_11GN_SOFT_RST_N	include/ssv6200_reg.h	7964;"	d
+SET_RX_PKT_COUNTER	include/ssv6200_reg.h	6147;"	d
+SET_RX_PKT_COUNTER	smac/hal/ssv6006c/ssv6006C_reg.h	10170;"	d
+SET_RX_PKT_DROP_COUNTER	include/ssv6200_reg.h	6151;"	d
+SET_RX_PKT_DROP_COUNTER	smac/hal/ssv6006c/ssv6006C_reg.h	10166;"	d
+SET_RX_PKT_TRAP_COUNTER	include/ssv6200_reg.h	6153;"	d
+SET_RX_PKT_TRAP_COUNTER	smac/hal/ssv6006c/ssv6006C_reg.h	10164;"	d
+SET_RX_QUOTA	include/ssv6200_reg.h	5689;"	d
+SET_RX_RDY	include/ssv6200_reg.h	5726;"	d
+SET_RX_RECIEVED	smac/hal/ssv6006c/ssv6006C_reg.h	9797;"	d
+SET_RX_TRAP_HW_ID	smac/hal/ssv6006c/ssv6006C_reg.h	10180;"	d
+SET_R_BOOTSTRAP_SAMPLE	smac/hal/ssv6006c/ssv6006C_reg.h	9336;"	d
+SET_SAME_ID_ALLOC_MD	include/ssv6200_reg.h	8438;"	d
+SET_SAR_ADC_FSM_RDY	include/ssv6200_reg.h	8422;"	d
+SET_SAR_ADC_FSM_RDY	smac/hal/ssv6006c/ssv6006C_reg.h	14013;"	d
+SET_SBUS_DMAC_BLOCK0	smac/hal/ssv6006c/ssv6006C_reg.h	9136;"	d
+SET_SBUS_DMAC_BLOCK1	smac/hal/ssv6006c/ssv6006C_reg.h	9153;"	d
+SET_SBUS_DMAC_CH0_CLR_ERR	smac/hal/ssv6006c/ssv6006C_reg.h	9168;"	d
+SET_SBUS_DMAC_CH0_CLR_TR	smac/hal/ssv6006c/ssv6006C_reg.h	9166;"	d
+SET_SBUS_DMAC_CH0_PRIOR	smac/hal/ssv6006c/ssv6006C_reg.h	9137;"	d
+SET_SBUS_DMAC_CH1_CLR_ERR	smac/hal/ssv6006c/ssv6006C_reg.h	9169;"	d
+SET_SBUS_DMAC_CH1_CLR_TR	smac/hal/ssv6006c/ssv6006C_reg.h	9167;"	d
+SET_SBUS_DMAC_CH1_PRIOR	smac/hal/ssv6006c/ssv6006C_reg.h	9154;"	d
+SET_SBUS_DMAC_CH_DEMASK_ERR	smac/hal/ssv6006c/ssv6006C_reg.h	9165;"	d
+SET_SBUS_DMAC_CH_DEMASK_TR	smac/hal/ssv6006c/ssv6006C_reg.h	9164;"	d
+SET_SBUS_DMAC_CH_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9175;"	d
+SET_SBUS_DMAC_CH_ERR_TR	smac/hal/ssv6006c/ssv6006C_reg.h	9161;"	d
+SET_SBUS_DMAC_CH_RAW_TR	smac/hal/ssv6006c/ssv6006C_reg.h	9160;"	d
+SET_SBUS_DMAC_CH_STATUSERR_TR	smac/hal/ssv6006c/ssv6006C_reg.h	9163;"	d
+SET_SBUS_DMAC_CH_STATUSTR_TR	smac/hal/ssv6006c/ssv6006C_reg.h	9162;"	d
+SET_SBUS_DMAC_DAR0	smac/hal/ssv6006c/ssv6006C_reg.h	9127;"	d
+SET_SBUS_DMAC_DAR1	smac/hal/ssv6006c/ssv6006C_reg.h	9144;"	d
+SET_SBUS_DMAC_DINC0	smac/hal/ssv6006c/ssv6006C_reg.h	9131;"	d
+SET_SBUS_DMAC_DINC1	smac/hal/ssv6006c/ssv6006C_reg.h	9148;"	d
+SET_SBUS_DMAC_DISEN_SHS_DST_REQ	smac/hal/ssv6006c/ssv6006C_reg.h	9171;"	d
+SET_SBUS_DMAC_DISEN_SHS_DST_SREQ	smac/hal/ssv6006c/ssv6006C_reg.h	9173;"	d
+SET_SBUS_DMAC_DISEN_SHS_SRC_REQ	smac/hal/ssv6006c/ssv6006C_reg.h	9170;"	d
+SET_SBUS_DMAC_DISEN_SHS_SRC_SREQ	smac/hal/ssv6006c/ssv6006C_reg.h	9172;"	d
+SET_SBUS_DMAC_DST_HS_BUS_SEL0	smac/hal/ssv6006c/ssv6006C_reg.h	9142;"	d
+SET_SBUS_DMAC_DST_HS_BUS_SEL1	smac/hal/ssv6006c/ssv6006C_reg.h	9159;"	d
+SET_SBUS_DMAC_DST_MSIZE0	smac/hal/ssv6006c/ssv6006C_reg.h	9133;"	d
+SET_SBUS_DMAC_DST_MSIZE1	smac/hal/ssv6006c/ssv6006C_reg.h	9150;"	d
+SET_SBUS_DMAC_DST_TR_WIDTH0	smac/hal/ssv6006c/ssv6006C_reg.h	9129;"	d
+SET_SBUS_DMAC_DST_TR_WIDTH1	smac/hal/ssv6006c/ssv6006C_reg.h	9146;"	d
+SET_SBUS_DMAC_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9174;"	d
+SET_SBUS_DMAC_FC_MODE0	smac/hal/ssv6006c/ssv6006C_reg.h	9135;"	d
+SET_SBUS_DMAC_FC_MODE1	smac/hal/ssv6006c/ssv6006C_reg.h	9152;"	d
+SET_SBUS_DMAC_HS_SEL_DST0	smac/hal/ssv6006c/ssv6006C_reg.h	9138;"	d
+SET_SBUS_DMAC_HS_SEL_DST1	smac/hal/ssv6006c/ssv6006C_reg.h	9155;"	d
+SET_SBUS_DMAC_HS_SEL_SRC0	smac/hal/ssv6006c/ssv6006C_reg.h	9139;"	d
+SET_SBUS_DMAC_HS_SEL_SRC1	smac/hal/ssv6006c/ssv6006C_reg.h	9156;"	d
+SET_SBUS_DMAC_INTR_EN0	smac/hal/ssv6006c/ssv6006C_reg.h	9128;"	d
+SET_SBUS_DMAC_INTR_EN1	smac/hal/ssv6006c/ssv6006C_reg.h	9145;"	d
+SET_SBUS_DMAC_MAX_BURST_LEN0	smac/hal/ssv6006c/ssv6006C_reg.h	9140;"	d
+SET_SBUS_DMAC_MAX_BURST_LEN1	smac/hal/ssv6006c/ssv6006C_reg.h	9157;"	d
+SET_SBUS_DMAC_SAR0	smac/hal/ssv6006c/ssv6006C_reg.h	9126;"	d
+SET_SBUS_DMAC_SAR1	smac/hal/ssv6006c/ssv6006C_reg.h	9143;"	d
+SET_SBUS_DMAC_SINC0	smac/hal/ssv6006c/ssv6006C_reg.h	9132;"	d
+SET_SBUS_DMAC_SINC1	smac/hal/ssv6006c/ssv6006C_reg.h	9149;"	d
+SET_SBUS_DMAC_SRC_HS_BUS_SEL0	smac/hal/ssv6006c/ssv6006C_reg.h	9141;"	d
+SET_SBUS_DMAC_SRC_HS_BUS_SEL1	smac/hal/ssv6006c/ssv6006C_reg.h	9158;"	d
+SET_SBUS_DMAC_SRC_MSIZE0	smac/hal/ssv6006c/ssv6006C_reg.h	9134;"	d
+SET_SBUS_DMAC_SRC_MSIZE1	smac/hal/ssv6006c/ssv6006C_reg.h	9151;"	d
+SET_SBUS_DMAC_SRC_TR_WIDTH0	smac/hal/ssv6006c/ssv6006C_reg.h	9130;"	d
+SET_SBUS_DMAC_SRC_TR_WIDTH1	smac/hal/ssv6006c/ssv6006C_reg.h	9147;"	d
+SET_SCL	smac/hal/ssv6006c/ssv6006C_reg.h	9695;"	d
+SET_SCOREBOAD_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	10368;"	d
+SET_SCRT_CCMP_CERR	include/ssv6200_reg.h	6841;"	d
+SET_SCRT_CCMP_CERR	smac/hal/ssv6006c/ssv6006C_reg.h	10953;"	d
+SET_SCRT_CCMP_RPLY	include/ssv6200_reg.h	6840;"	d
+SET_SCRT_CCMP_RPLY	smac/hal/ssv6006c/ssv6006C_reg.h	10952;"	d
+SET_SCRT_CLK_EN	include/ssv6200_reg.h	6709;"	d
+SET_SCRT_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10805;"	d
+SET_SCRT_CSR_CLK_EN	include/ssv6200_reg.h	6725;"	d
+SET_SCRT_CSR_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10821;"	d
+SET_SCRT_CSR_RST	include/ssv6200_reg.h	6697;"	d
+SET_SCRT_CSR_RST	smac/hal/ssv6006c/ssv6006C_reg.h	10793;"	d
+SET_SCRT_ENG_CLK_EN	include/ssv6200_reg.h	6720;"	d
+SET_SCRT_ENG_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10816;"	d
+SET_SCRT_ENG_RST	include/ssv6200_reg.h	6685;"	d
+SET_SCRT_ENG_RST	smac/hal/ssv6006c/ssv6006C_reg.h	10781;"	d
+SET_SCRT_INT_1	include/ssv6200_reg.h	5892;"	d
+SET_SCRT_INT_1_SD	include/ssv6200_reg.h	5961;"	d
+SET_SCRT_PKT_CLS_MIB_EN	include/ssv6200_reg.h	6784;"	d
+SET_SCRT_PKT_CLS_MIB_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10896;"	d
+SET_SCRT_PKT_CLS_ONGOING	include/ssv6200_reg.h	6785;"	d
+SET_SCRT_PKT_CLS_ONGOING	smac/hal/ssv6006c/ssv6006C_reg.h	10897;"	d
+SET_SCRT_PKT_ID	include/ssv6200_reg.h	6745;"	d
+SET_SCRT_PKT_ID	smac/hal/ssv6006c/ssv6006C_reg.h	10842;"	d
+SET_SCRT_RPLY_IGNORE	include/ssv6200_reg.h	6746;"	d
+SET_SCRT_RPLY_IGNORE	smac/hal/ssv6006c/ssv6006C_reg.h	10843;"	d
+SET_SCRT_STATE	include/ssv6200_reg.h	6740;"	d
+SET_SCRT_STATE	smac/hal/ssv6006c/ssv6006C_reg.h	10844;"	d
+SET_SCRT_SW_RST	include/ssv6200_reg.h	6674;"	d
+SET_SCRT_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	10770;"	d
+SET_SCRT_TKIP_CERR	include/ssv6200_reg.h	6837;"	d
+SET_SCRT_TKIP_CERR	smac/hal/ssv6006c/ssv6006C_reg.h	10949;"	d
+SET_SCRT_TKIP_MIC_ERR	include/ssv6200_reg.h	6838;"	d
+SET_SCRT_TKIP_MIC_ERR	smac/hal/ssv6006c/ssv6006C_reg.h	10950;"	d
+SET_SCRT_TKIP_RPLY	include/ssv6200_reg.h	6839;"	d
+SET_SCRT_TKIP_RPLY	smac/hal/ssv6006c/ssv6006C_reg.h	10951;"	d
+SET_SDA	smac/hal/ssv6006c/ssv6006C_reg.h	9696;"	d
+SET_SDIO_ALL_RESET	include/ssv6200_reg.h	5583;"	d
+SET_SDIO_ALL_RESET	smac/hal/ssv6006c/ssv6006C_reg.h	9621;"	d
+SET_SDIO_ALL_RESE_ACTIVE	include/ssv6200_reg.h	5545;"	d
+SET_SDIO_BUSY_LONG_CNT	include/ssv6200_reg.h	5569;"	d
+SET_SDIO_BUS_STATE_REG	include/ssv6200_reg.h	5568;"	d
+SET_SDIO_BYTE_MODE_BATCH_SIZE_REG	include/ssv6200_reg.h	5564;"	d
+SET_SDIO_BYTE_MODE_BATCH_SIZE_REG	smac/hal/ssv6006c/ssv6006C_reg.h	9602;"	d
+SET_SDIO_CARD_STATUS_REG	include/ssv6200_reg.h	5570;"	d
+SET_SDIO_CARD_STATUS_REG	smac/hal/ssv6006c/ssv6006C_reg.h	9603;"	d
+SET_SDIO_CLK_EN	include/ssv6200_reg.h	4944;"	d
+SET_SDIO_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9303;"	d
+SET_SDIO_CMD52_06H_RESET	smac/hal/ssv6006c/ssv6006C_reg.h	9409;"	d
+SET_SDIO_CRC16_ERROR_CNT	include/ssv6200_reg.h	5591;"	d
+SET_SDIO_CRC7_ERROR_CNT	include/ssv6200_reg.h	5590;"	d
+SET_SDIO_FIFO_EMPTY_CNT	include/ssv6200_reg.h	5588;"	d
+SET_SDIO_FIFO_FULL_CNT	include/ssv6200_reg.h	5589;"	d
+SET_SDIO_FIFO_RD_PTR_REG	include/ssv6200_reg.h	5597;"	d
+SET_SDIO_FIFO_WR_LIMIT_REG	include/ssv6200_reg.h	5558;"	d
+SET_SDIO_FIFO_WR_PTR_REG	include/ssv6200_reg.h	5596;"	d
+SET_SDIO_FIFO_WR_THLD_REG	include/ssv6200_reg.h	5557;"	d
+SET_SDIO_LAST_CMD_ARG_REG	include/ssv6200_reg.h	5567;"	d
+SET_SDIO_LAST_CMD_CRC_REG	include/ssv6200_reg.h	5566;"	d
+SET_SDIO_LAST_CMD_INDEX_REG	include/ssv6200_reg.h	5565;"	d
+SET_SDIO_LOOP_BACK_TEST	include/ssv6200_reg.h	5541;"	d
+SET_SDIO_PARTIAL_RESET	include/ssv6200_reg.h	5582;"	d
+SET_SDIO_PARTIAL_RESET	smac/hal/ssv6006c/ssv6006C_reg.h	9620;"	d
+SET_SDIO_PARTIAL_RESET_ACTIVE	include/ssv6200_reg.h	5544;"	d
+SET_SDIO_RD_BLOCK_CNT	include/ssv6200_reg.h	5592;"	d
+SET_SDIO_READ_DATA_CTRL	include/ssv6200_reg.h	5598;"	d
+SET_SDIO_RX_DATA_BATCH_SIZE_REG	include/ssv6200_reg.h	5561;"	d
+SET_SDIO_SW_RST	include/ssv6200_reg.h	4910;"	d
+SET_SDIO_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	9270;"	d
+SET_SDIO_SYS_INT	include/ssv6200_reg.h	5727;"	d
+SET_SDIO_THLD_FOR_CMD53RD_REG	include/ssv6200_reg.h	5560;"	d
+SET_SDIO_TO_MCU_INFO	include/ssv6200_reg.h	5581;"	d
+SET_SDIO_TO_MCU_INFO	smac/hal/ssv6006c/ssv6006C_reg.h	9619;"	d
+SET_SDIO_TRANS_CNT	include/ssv6200_reg.h	6167;"	d
+SET_SDIO_TRANS_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	10160;"	d
+SET_SDIO_TRX_DATA_SEQUENCE	include/ssv6200_reg.h	5534;"	d
+SET_SDIO_TRX_DATA_SEQUENCE	smac/hal/ssv6006c/ssv6006C_reg.h	9597;"	d
+SET_SDIO_TX_ALLOC_STATE	include/ssv6200_reg.h	5601;"	d
+SET_SDIO_TX_DATA_BATCH_SIZE_REG	include/ssv6200_reg.h	5559;"	d
+SET_SDIO_TX_INVALID_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	10157;"	d
+SET_SDIO_TX_INVALID_CNT_31_0	include/ssv6200_reg.h	6168;"	d
+SET_SDIO_TX_INVALID_CNT_47_32	include/ssv6200_reg.h	6169;"	d
+SET_SDIO_WR_BLOCK_CNT	include/ssv6200_reg.h	5593;"	d
+SET_SD_CMD_IN_DLY_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	9608;"	d
+SET_SD_CMD_OUT_DLY_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	9609;"	d
+SET_SD_DAT_0_IN_DLY_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	9616;"	d
+SET_SD_DAT_0_OUT_DLY_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	9617;"	d
+SET_SD_DAT_1_IN_DLY_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	9614;"	d
+SET_SD_DAT_1_OUT_DLY_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	9615;"	d
+SET_SD_DAT_2_IN_DLY_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	9612;"	d
+SET_SD_DAT_2_OUT_DLY_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	9613;"	d
+SET_SD_DAT_3_IN_DLY_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	9610;"	d
+SET_SD_DAT_3_OUT_DLY_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	9611;"	d
+SET_SD_HOST_INIT	include/ssv6200_reg.h	5025;"	d
+SET_SD_MASK_TOP	include/ssv6200_reg.h	5922;"	d
+SET_SD_RX_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	10113;"	d
+SET_SD_SSDR104	smac/hal/ssv6006c/ssv6006C_reg.h	9644;"	d
+SET_SD_SSDR50	smac/hal/ssv6006c/ssv6006C_reg.h	9643;"	d
+SET_SEL_BTCX	smac/hal/ssv6006c/ssv6006C_reg.h	9548;"	d
+SET_SEL_DEBUG_I	smac/hal/ssv6006c/ssv6006C_reg.h	9552;"	d
+SET_SEL_DEBUG_II	smac/hal/ssv6006c/ssv6006C_reg.h	9553;"	d
+SET_SEL_FLASH	smac/hal/ssv6006c/ssv6006C_reg.h	9549;"	d
+SET_SEL_GPO_INT	smac/hal/ssv6006c/ssv6006C_reg.h	9560;"	d
+SET_SEL_I2C_MST_I	smac/hal/ssv6006c/ssv6006C_reg.h	9545;"	d
+SET_SEL_I2C_MST_II	smac/hal/ssv6006c/ssv6006C_reg.h	9544;"	d
+SET_SEL_I2C_SLV	smac/hal/ssv6006c/ssv6006C_reg.h	9543;"	d
+SET_SEL_I2STRX_I	smac/hal/ssv6006c/ssv6006C_reg.h	9540;"	d
+SET_SEL_I2STRX_II	smac/hal/ssv6006c/ssv6006C_reg.h	9539;"	d
+SET_SEL_MEM_BIST	smac/hal/ssv6006c/ssv6006C_reg.h	9554;"	d
+SET_SEL_PWM	smac/hal/ssv6006c/ssv6006C_reg.h	9551;"	d
+SET_SEL_RF	smac/hal/ssv6006c/ssv6006C_reg.h	9550;"	d
+SET_SEL_SPI_MST	smac/hal/ssv6006c/ssv6006C_reg.h	9542;"	d
+SET_SEL_SPI_SLV	smac/hal/ssv6006c/ssv6006C_reg.h	9541;"	d
+SET_SEL_UART0_I	smac/hal/ssv6006c/ssv6006C_reg.h	9547;"	d
+SET_SEL_UART0_II	smac/hal/ssv6006c/ssv6006C_reg.h	9546;"	d
+SET_SEL_USB_BIST	smac/hal/ssv6006c/ssv6006C_reg.h	9555;"	d
+SET_SEL_USB_IDDQ	smac/hal/ssv6006c/ssv6006C_reg.h	9557;"	d
+SET_SEL_USB_TEST	smac/hal/ssv6006c/ssv6006C_reg.h	9556;"	d
+SET_SEQ_CTRL	include/ssv6200_reg.h	6135;"	d
+SET_SEQ_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	10121;"	d
+SET_SET_BREAK	include/ssv6200_reg.h	5774;"	d
+SET_SET_BREAK	smac/hal/ssv6006c/ssv6006C_reg.h	9764;"	d
+SET_SFD_CNT	include/ssv6200_reg.h	7823;"	d
+SET_SFD_FIELD	include/ssv6200_reg.h	7829;"	d
+SET_SHA_BUSY	include/ssv6200_reg.h	6200;"	d
+SET_SHA_BUSY	smac/hal/ssv6006c/ssv6006C_reg.h	10218;"	d
+SET_SHA_DST_ADDR	include/ssv6200_reg.h	6198;"	d
+SET_SHA_DST_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	10216;"	d
+SET_SHA_ENDIAN	include/ssv6200_reg.h	6201;"	d
+SET_SHA_ENDIAN	smac/hal/ssv6006c/ssv6006C_reg.h	10219;"	d
+SET_SHA_SRC_ADDR	include/ssv6200_reg.h	6199;"	d
+SET_SHA_SRC_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	10217;"	d
+SET_SHIFT_DR	include/ssv6200_reg.h	4979;"	d
+SET_SHORT_TO_20_ID	include/ssv6200_reg.h	5148;"	d
+SET_SHRT_GI	include/ssv6200_reg.h	6193;"	d
+SET_SHRT_GI	smac/hal/ssv6006c/ssv6006C_reg.h	10211;"	d
+SET_SHRT_PREAM	include/ssv6200_reg.h	6192;"	d
+SET_SHRT_PREAM	smac/hal/ssv6006c/ssv6006C_reg.h	10210;"	d
+SET_SIFS	smac/hal/ssv6006c/ssv6006C_reg.h	10517;"	d
+SET_SIGEXT	smac/hal/ssv6006c/ssv6006C_reg.h	10521;"	d
+SET_SIGNAL_FIELD	include/ssv6200_reg.h	7830;"	d
+SET_SIGNAL_FIELD0	include/ssv6200_reg.h	7953;"	d
+SET_SIGNAL_FIELD1	include/ssv6200_reg.h	7954;"	d
+SET_SIMULATION_MODE	include/ssv6200_reg.h	4981;"	d
+SET_SLEEP_WAKE_CNT	include/ssv6200_reg.h	6071;"	d
+SET_SLOTTIME	smac/hal/ssv6006c/ssv6006C_reg.h	10516;"	d
+SET_SMS4_BUSY	include/ssv6200_reg.h	6253;"	d
+SET_SMS4_CBC_EN	include/ssv6200_reg.h	6249;"	d
+SET_SMS4_CFB_EN	include/ssv6200_reg.h	6250;"	d
+SET_SMS4_DATAIN_0	include/ssv6200_reg.h	6255;"	d
+SET_SMS4_DATAIN_1	include/ssv6200_reg.h	6256;"	d
+SET_SMS4_DATAIN_2	include/ssv6200_reg.h	6257;"	d
+SET_SMS4_DATAIN_3	include/ssv6200_reg.h	6258;"	d
+SET_SMS4_DATAOUT_0	include/ssv6200_reg.h	6259;"	d
+SET_SMS4_DATAOUT_1	include/ssv6200_reg.h	6260;"	d
+SET_SMS4_DATAOUT_2	include/ssv6200_reg.h	6261;"	d
+SET_SMS4_DATAOUT_3	include/ssv6200_reg.h	6262;"	d
+SET_SMS4_DESCRY_EN	include/ssv6200_reg.h	6243;"	d
+SET_SMS4_DONE	include/ssv6200_reg.h	6254;"	d
+SET_SMS4_KEY_0	include/ssv6200_reg.h	6263;"	d
+SET_SMS4_KEY_1	include/ssv6200_reg.h	6264;"	d
+SET_SMS4_KEY_2	include/ssv6200_reg.h	6265;"	d
+SET_SMS4_KEY_3	include/ssv6200_reg.h	6266;"	d
+SET_SMS4_MODE_IV0	include/ssv6200_reg.h	6267;"	d
+SET_SMS4_MODE_IV1	include/ssv6200_reg.h	6268;"	d
+SET_SMS4_MODE_IV2	include/ssv6200_reg.h	6269;"	d
+SET_SMS4_MODE_IV3	include/ssv6200_reg.h	6270;"	d
+SET_SMS4_OFB_EN	include/ssv6200_reg.h	6251;"	d
+SET_SMS4_OFB_ENC0	include/ssv6200_reg.h	6271;"	d
+SET_SMS4_OFB_ENC1	include/ssv6200_reg.h	6272;"	d
+SET_SMS4_OFB_ENC2	include/ssv6200_reg.h	6273;"	d
+SET_SMS4_OFB_ENC3	include/ssv6200_reg.h	6274;"	d
+SET_SMS4_START_TRIG	include/ssv6200_reg.h	6252;"	d
+SET_SNIFFER_MODE	include/ssv6200_reg.h	6732;"	d
+SET_SNIFFER_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	10828;"	d
+SET_SOC_SYSTEM_INT_STATUS	include/ssv6200_reg.h	5521;"	d
+SET_SOC_SYSTEM_INT_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	9584;"	d
+SET_SOC_TRIGGER_RX_INT	include/ssv6200_reg.h	5529;"	d
+SET_SOC_TRIGGER_RX_INT	smac/hal/ssv6006c/ssv6006C_reg.h	9592;"	d
+SET_SOC_TRIGGER_TX_INT	include/ssv6200_reg.h	5530;"	d
+SET_SOC_TRIGGER_TX_INT	smac/hal/ssv6006c/ssv6006C_reg.h	9593;"	d
+SET_SPARE_MEM	smac/hal/ssv6006c/ssv6006C_reg.h	9684;"	d
+SET_SPIMAS_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9329;"	d
+SET_SPIMST_CEN_ENABLE	smac/hal/ssv6006c/ssv6006C_reg.h	9245;"	d
+SET_SPIMST_CPHA	smac/hal/ssv6006c/ssv6006C_reg.h	9240;"	d
+SET_SPIMST_CPOL	smac/hal/ssv6006c/ssv6006C_reg.h	9241;"	d
+SET_SPIMST_DATA_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	9239;"	d
+SET_SPIMST_ENABLE	smac/hal/ssv6006c/ssv6006C_reg.h	9244;"	d
+SET_SPIMST_RXFIFO_TH	smac/hal/ssv6006c/ssv6006C_reg.h	9248;"	d
+SET_SPIMST_RXF_INT	smac/hal/ssv6006c/ssv6006C_reg.h	9264;"	d
+SET_SPIMST_RXF_INT_UNMASK	smac/hal/ssv6006c/ssv6006C_reg.h	9259;"	d
+SET_SPIMST_RXO_INT	smac/hal/ssv6006c/ssv6006C_reg.h	9263;"	d
+SET_SPIMST_RXO_INT_UNMASK	smac/hal/ssv6006c/ssv6006C_reg.h	9258;"	d
+SET_SPIMST_RXU_INT	smac/hal/ssv6006c/ssv6006C_reg.h	9262;"	d
+SET_SPIMST_RXU_INT_UNMASK	smac/hal/ssv6006c/ssv6006C_reg.h	9257;"	d
+SET_SPIMST_RX_SAMPLE_DLY	smac/hal/ssv6006c/ssv6006C_reg.h	9266;"	d
+SET_SPIMST_SCLK_RATE	smac/hal/ssv6006c/ssv6006C_reg.h	9246;"	d
+SET_SPIMST_TRX_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	9265;"	d
+SET_SPIMST_TXE_INT	smac/hal/ssv6006c/ssv6006C_reg.h	9260;"	d
+SET_SPIMST_TXE_INT_UNMASK	smac/hal/ssv6006c/ssv6006C_reg.h	9255;"	d
+SET_SPIMST_TXFIFO_TH	smac/hal/ssv6006c/ssv6006C_reg.h	9247;"	d
+SET_SPIMST_TXO_INT	smac/hal/ssv6006c/ssv6006C_reg.h	9261;"	d
+SET_SPIMST_TXO_INT_UNMASK	smac/hal/ssv6006c/ssv6006C_reg.h	9256;"	d
+SET_SPI_ALLOC_STATUS	include/ssv6200_reg.h	5705;"	d
+SET_SPI_BUSY	include/ssv6200_reg.h	6047;"	d
+SET_SPI_BUSY	smac/hal/ssv6006c/ssv6006C_reg.h	9881;"	d
+SET_SPI_CLK_DIV	smac/hal/ssv6006c/ssv6006C_reg.h	10265;"	d
+SET_SPI_CLK_EN_INT	include/ssv6200_reg.h	5734;"	d
+SET_SPI_CLR	smac/hal/ssv6006c/ssv6006C_reg.h	10267;"	d
+SET_SPI_CSN	smac/hal/ssv6006c/ssv6006C_reg.h	10277;"	d
+SET_SPI_DBG_WR_FIFO_FULL	include/ssv6200_reg.h	5706;"	d
+SET_SPI_DI_SEL	include/ssv6200_reg.h	5509;"	d
+SET_SPI_DOUBLE_ALLOC	include/ssv6200_reg.h	5702;"	d
+SET_SPI_FLASH_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	9882;"	d
+SET_SPI_FN1	include/ssv6200_reg.h	5733;"	d
+SET_SPI_F_MISO_CLK_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	9904;"	d
+SET_SPI_HOST_MASK	include/ssv6200_reg.h	5735;"	d
+SET_SPI_HOST_TX_ALLOC_PKBUF	include/ssv6200_reg.h	5709;"	d
+SET_SPI_IPC_ADDR	include/ssv6200_reg.h	5921;"	d
+SET_SPI_MASTER_BUSY	smac/hal/ssv6006c/ssv6006C_reg.h	10266;"	d
+SET_SPI_MODE	include/ssv6200_reg.h	5688;"	d
+SET_SPI_MST2CBRA_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9320;"	d
+SET_SPI_M_BACK_DLY	smac/hal/ssv6006c/ssv6006C_reg.h	10264;"	d
+SET_SPI_M_FRONT_DLY	smac/hal/ssv6006c/ssv6006C_reg.h	10263;"	d
+SET_SPI_RAW_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	9559;"	d
+SET_SPI_SLV_CLK_EN	include/ssv6200_reg.h	4945;"	d
+SET_SPI_SLV_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9304;"	d
+SET_SPI_SLV_SW_RST	include/ssv6200_reg.h	4911;"	d
+SET_SPI_SLV_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	9271;"	d
+SET_SPI_TX_ALLOC_SIZE	include/ssv6200_reg.h	5710;"	d
+SET_SPI_TX_ALLOC_SIZE_SHIFT_BITS	include/ssv6200_reg.h	5708;"	d
+SET_SPI_TX_NO_ALLOC	include/ssv6200_reg.h	5703;"	d
+SET_SRAM_ACCESS_MD	include/ssv6200_reg.h	8440;"	d
+SET_SRAM_ADDR	include/ssv6200_reg.h	6042;"	d
+SET_SRAM_TAG_0	include/ssv6200_reg.h	8532;"	d
+SET_SRAM_TAG_1	include/ssv6200_reg.h	8533;"	d
+SET_SRAM_TAG_10	include/ssv6200_reg.h	8542;"	d
+SET_SRAM_TAG_11	include/ssv6200_reg.h	8543;"	d
+SET_SRAM_TAG_12	include/ssv6200_reg.h	8544;"	d
+SET_SRAM_TAG_13	include/ssv6200_reg.h	8545;"	d
+SET_SRAM_TAG_14	include/ssv6200_reg.h	8546;"	d
+SET_SRAM_TAG_15	include/ssv6200_reg.h	8547;"	d
+SET_SRAM_TAG_2	include/ssv6200_reg.h	8534;"	d
+SET_SRAM_TAG_3	include/ssv6200_reg.h	8535;"	d
+SET_SRAM_TAG_4	include/ssv6200_reg.h	8536;"	d
+SET_SRAM_TAG_5	include/ssv6200_reg.h	8537;"	d
+SET_SRAM_TAG_6	include/ssv6200_reg.h	8538;"	d
+SET_SRAM_TAG_7	include/ssv6200_reg.h	8539;"	d
+SET_SRAM_TAG_8	include/ssv6200_reg.h	8540;"	d
+SET_SRAM_TAG_9	include/ssv6200_reg.h	8541;"	d
+SET_START_BYTE_VALUE	include/ssv6200_reg.h	5562;"	d
+SET_START_BYTE_VALUE2	include/ssv6200_reg.h	5624;"	d
+SET_STAT_CLR	smac/hal/ssv6006c/ssv6006C_reg.h	10468;"	d
+SET_STAT_CLR_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	10469;"	d
+SET_STAT_ENABLE	smac/hal/ssv6006c/ssv6006C_reg.h	10465;"	d
+SET_STAT_EN_MB	smac/hal/ssv6006c/ssv6006C_reg.h	10459;"	d
+SET_STAT_FINISH	smac/hal/ssv6006c/ssv6006C_reg.h	10462;"	d
+SET_STAT_FREEZE	smac/hal/ssv6006c/ssv6006C_reg.h	10467;"	d
+SET_STAT_FSM	smac/hal/ssv6006c/ssv6006C_reg.h	10464;"	d
+SET_STAT_MB_TARGET	smac/hal/ssv6006c/ssv6006C_reg.h	10460;"	d
+SET_STAT_PKT_ID	smac/hal/ssv6006c/ssv6006C_reg.h	10463;"	d
+SET_STAT_UNEXPECT_WSID	smac/hal/ssv6006c/ssv6006C_reg.h	10461;"	d
+SET_STAT_WSID	smac/hal/ssv6006c/ssv6006C_reg.h	10466;"	d
+SET_STA_MAC1_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	10847;"	d
+SET_STA_MAC1_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	10848;"	d
+SET_STA_MAC_31_0	include/ssv6200_reg.h	6741;"	d
+SET_STA_MAC_31_0	smac/hal/ssv6006c/ssv6006C_reg.h	10838;"	d
+SET_STA_MAC_47_32	include/ssv6200_reg.h	6742;"	d
+SET_STA_MAC_47_32	smac/hal/ssv6006c/ssv6006C_reg.h	10839;"	d
+SET_STOP_BIT	include/ssv6200_reg.h	5770;"	d
+SET_STOP_BIT	smac/hal/ssv6006c/ssv6006C_reg.h	9760;"	d
+SET_STOP_MBOX	include/ssv6200_reg.h	7242;"	d
+SET_STOP_MBOX_IN	smac/hal/ssv6006c/ssv6006C_reg.h	15698;"	d
+SET_STOP_MBOX_OUT	smac/hal/ssv6006c/ssv6006C_reg.h	15697;"	d
+SET_STOP_MBOX_OUT_SUCCESS	smac/hal/ssv6006c/ssv6006C_reg.h	15714;"	d
+SET_STRAP0	include/ssv6200_reg.h	5156;"	d
+SET_STRAP1	include/ssv6200_reg.h	5192;"	d
+SET_STRAP2	include/ssv6200_reg.h	5467;"	d
+SET_STRAP3	include/ssv6200_reg.h	5165;"	d
+SET_SUMMARY_TYPHOST_INT_MAP	smac/hal/ssv6006c/ssv6006C_reg.h	9950;"	d
+SET_SUMMARY_TYPMCU_INT_MAP	smac/hal/ssv6006c/ssv6006C_reg.h	9963;"	d
+SET_SUPPORT_BLOCK_GAP_INTERRUPT	include/ssv6200_reg.h	5644;"	d
+SET_SUPPORT_BLOCK_GAP_INTERRUPT	smac/hal/ssv6006c/ssv6006C_reg.h	9638;"	d
+SET_SUPPORT_BUS_CONTROL	include/ssv6200_reg.h	5643;"	d
+SET_SUPPORT_BUS_CONTROL	smac/hal/ssv6006c/ssv6006C_reg.h	9637;"	d
+SET_SUPPORT_DIRECT_COMMAND_SDIO	include/ssv6200_reg.h	5640;"	d
+SET_SUPPORT_DIRECT_COMMAND_SDIO	smac/hal/ssv6006c/ssv6006C_reg.h	9634;"	d
+SET_SUPPORT_HIGH_SPEED	include/ssv6200_reg.h	5649;"	d
+SET_SUPPORT_HIGH_SPEED	smac/hal/ssv6006c/ssv6006C_reg.h	9645;"	d
+SET_SUPPORT_MULTIPLE_BLOCK_TRANSFER	include/ssv6200_reg.h	5641;"	d
+SET_SUPPORT_MULTIPLE_BLOCK_TRANSFER	smac/hal/ssv6006c/ssv6006C_reg.h	9635;"	d
+SET_SUPPORT_READ_WAIT	include/ssv6200_reg.h	5642;"	d
+SET_SUPPORT_READ_WAIT	smac/hal/ssv6006c/ssv6006C_reg.h	9636;"	d
+SET_SUSPEND_PWR_ON1	smac/hal/ssv6006c/ssv6006C_reg.h	9416;"	d
+SET_SUSPEND_PWR_ON2	smac/hal/ssv6006c/ssv6006C_reg.h	9417;"	d
+SET_SUSPEND_PWR_ON3	smac/hal/ssv6006c/ssv6006C_reg.h	9418;"	d
+SET_SVN_VERSION	include/ssv6200_reg.h	7529;"	d
+SET_SVN_VERSION	smac/hal/ssv6006c/ssv6006C_reg.h	15112;"	d
+SET_SWITCH_2WIRE_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10875;"	d
+SET_SW_BT_TRX	include/ssv6200_reg.h	6767;"	d
+SET_SW_BT_TRX	smac/hal/ssv6006c/ssv6006C_reg.h	10870;"	d
+SET_SW_MANUAL_EN	include/ssv6200_reg.h	6764;"	d
+SET_SW_MANUAL_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10867;"	d
+SET_SW_WL_RX	include/ssv6200_reg.h	6766;"	d
+SET_SW_WL_RX	smac/hal/ssv6006c/ssv6006C_reg.h	10869;"	d
+SET_SW_WL_TX	include/ssv6200_reg.h	6765;"	d
+SET_SW_WL_TX	smac/hal/ssv6006c/ssv6006C_reg.h	10868;"	d
+SET_SYSCTRL_CMD	smac/hal/ssv6006c/ssv6006C_reg.h	9352;"	d
+SET_SYSTEM_INT	include/ssv6200_reg.h	5555;"	d
+SET_SYS_ALL_RST	include/ssv6200_reg.h	4928;"	d
+SET_SYS_CLK_EN	include/ssv6200_reg.h	4941;"	d
+SET_SYS_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9300;"	d
+SET_SYS_CLOCK_STATE	smac/hal/ssv6006c/ssv6006C_reg.h	9343;"	d
+SET_SYS_DPLL_ON	smac/hal/ssv6006c/ssv6006C_reg.h	9355;"	d
+SET_SYS_N10_IVB_VAL	smac/hal/ssv6006c/ssv6006C_reg.h	9399;"	d
+SET_SYS_PMU_MODE_TRAN_INT	smac/hal/ssv6006c/ssv6006C_reg.h	9402;"	d
+SET_SYS_RST_INT	include/ssv6200_reg.h	5920;"	d
+SET_SYS_WDOG_ENA	include/ssv6200_reg.h	5074;"	d
+SET_SYS_WDOG_ENA	smac/hal/ssv6006c/ssv6006C_reg.h	9492;"	d
+SET_SYS_WDT_INT_CNT_OFS	smac/hal/ssv6006c/ssv6006C_reg.h	9490;"	d
+SET_SYS_WDT_STATUS	include/ssv6200_reg.h	5073;"	d
+SET_SYS_WDT_STATUS	smac/hal/ssv6006c/ssv6006C_reg.h	9491;"	d
+SET_SYS_WDT_TIME_CNT	include/ssv6200_reg.h	5072;"	d
+SET_SYS_WDT_TIME_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	9489;"	d
+SET_SYS_XOSC_ON	smac/hal/ssv6006c/ssv6006C_reg.h	9354;"	d
+SET_TAG_INTERLEAVE_MD	include/ssv6200_reg.h	8436;"	d
+SET_TAG_SW_RST_N	include/ssv6200_reg.h	8446;"	d
+SET_TBLNEQ_MNGPKT_INT_IRQ	include/ssv6200_reg.h	5916;"	d
+SET_TBLNEQ_MNGPKT_INT_IRQ_SD	include/ssv6200_reg.h	5985;"	d
+SET_TB_ADR_SEL	include/ssv6200_reg.h	4988;"	d
+SET_TB_ADR_SEL	smac/hal/ssv6006c/ssv6006C_reg.h	9348;"	d
+SET_TB_CS	include/ssv6200_reg.h	4989;"	d
+SET_TB_CS	smac/hal/ssv6006c/ssv6006C_reg.h	9349;"	d
+SET_TB_RDATA	include/ssv6200_reg.h	4990;"	d
+SET_TB_RDATA	smac/hal/ssv6006c/ssv6006C_reg.h	9350;"	d
+SET_TEST_10_ID	include/ssv6200_reg.h	5258;"	d
+SET_TEST_11_ID	include/ssv6200_reg.h	5266;"	d
+SET_TEST_12_ID	include/ssv6200_reg.h	5274;"	d
+SET_TEST_13_ID	include/ssv6200_reg.h	5282;"	d
+SET_TEST_14_ID	include/ssv6200_reg.h	5290;"	d
+SET_TEST_15_ID	include/ssv6200_reg.h	5298;"	d
+SET_TEST_16_ID	include/ssv6200_reg.h	5387;"	d
+SET_TEST_17_ID	include/ssv6200_reg.h	5395;"	d
+SET_TEST_18_ID	include/ssv6200_reg.h	5403;"	d
+SET_TEST_19_ID	include/ssv6200_reg.h	5411;"	d
+SET_TEST_1_ID	include/ssv6200_reg.h	5116;"	d
+SET_TEST_20_ID	include/ssv6200_reg.h	5419;"	d
+SET_TEST_2_ID	include/ssv6200_reg.h	5124;"	d
+SET_TEST_3_ID	include/ssv6200_reg.h	5132;"	d
+SET_TEST_4_ID	include/ssv6200_reg.h	5140;"	d
+SET_TEST_6_ID	include/ssv6200_reg.h	5226;"	d
+SET_TEST_7_ID	include/ssv6200_reg.h	5234;"	d
+SET_TEST_8_ID	include/ssv6200_reg.h	5242;"	d
+SET_TEST_9_ID	include/ssv6200_reg.h	5250;"	d
+SET_TEST_MODE0	include/ssv6200_reg.h	5018;"	d
+SET_TEST_MODE0	smac/hal/ssv6006c/ssv6006C_reg.h	9377;"	d
+SET_TEST_MODE1	include/ssv6200_reg.h	5019;"	d
+SET_TEST_MODE1	smac/hal/ssv6006c/ssv6006C_reg.h	9378;"	d
+SET_TEST_MODE2	include/ssv6200_reg.h	5020;"	d
+SET_TEST_MODE2	smac/hal/ssv6006c/ssv6006C_reg.h	9379;"	d
+SET_TEST_MODE3	include/ssv6200_reg.h	5021;"	d
+SET_TEST_MODE3	smac/hal/ssv6006c/ssv6006C_reg.h	9380;"	d
+SET_TEST_MODE4	include/ssv6200_reg.h	5022;"	d
+SET_TEST_MODE4	smac/hal/ssv6006c/ssv6006C_reg.h	9381;"	d
+SET_TEST_MODE_ALL	include/ssv6200_reg.h	5023;"	d
+SET_TEST_MODE_ALL	smac/hal/ssv6006c/ssv6006C_reg.h	9382;"	d
+SET_THREE_WIRE	smac/hal/ssv6006c/ssv6006C_reg.h	10274;"	d
+SET_THR_EMPTY	include/ssv6200_reg.h	5786;"	d
+SET_THR_EMPTY	smac/hal/ssv6006c/ssv6006C_reg.h	9777;"	d
+SET_THR_EMPTY_IE	include/ssv6200_reg.h	5757;"	d
+SET_THR_EMPTY_IE	smac/hal/ssv6006c/ssv6006C_reg.h	9747;"	d
+SET_TIP_A	smac/hal/ssv6006c/ssv6006C_reg.h	9810;"	d
+SET_TM0_PRESCALER_USTIMER_LOCAL	smac/hal/ssv6006c/ssv6006C_reg.h	9466;"	d
+SET_TM0_TM_CUR_VALUE	include/ssv6200_reg.h	5053;"	d
+SET_TM0_TM_CUR_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	9465;"	d
+SET_TM0_TM_INIT_VALUE	include/ssv6200_reg.h	5049;"	d
+SET_TM0_TM_INIT_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	9461;"	d
+SET_TM0_TM_INT_MASK	include/ssv6200_reg.h	5052;"	d
+SET_TM0_TM_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	9464;"	d
+SET_TM0_TM_INT_STS_DONE	include/ssv6200_reg.h	5051;"	d
+SET_TM0_TM_INT_STS_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	9463;"	d
+SET_TM0_TM_MODE	include/ssv6200_reg.h	5050;"	d
+SET_TM0_TM_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	9462;"	d
+SET_TM1_PRESCALER_USTIMER_LOCAL	smac/hal/ssv6006c/ssv6006C_reg.h	9472;"	d
+SET_TM1_TM_CUR_VALUE	include/ssv6200_reg.h	5058;"	d
+SET_TM1_TM_CUR_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	9471;"	d
+SET_TM1_TM_INIT_VALUE	include/ssv6200_reg.h	5054;"	d
+SET_TM1_TM_INIT_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	9467;"	d
+SET_TM1_TM_INT_MASK	include/ssv6200_reg.h	5057;"	d
+SET_TM1_TM_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	9470;"	d
+SET_TM1_TM_INT_STS_DONE	include/ssv6200_reg.h	5056;"	d
+SET_TM1_TM_INT_STS_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	9469;"	d
+SET_TM1_TM_MODE	include/ssv6200_reg.h	5055;"	d
+SET_TM1_TM_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	9468;"	d
+SET_TM2_PRESCALER_USTIMER_LOCAL	smac/hal/ssv6006c/ssv6006C_reg.h	9478;"	d
+SET_TM2_TM_CUR_VALUE	include/ssv6200_reg.h	5063;"	d
+SET_TM2_TM_CUR_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	9477;"	d
+SET_TM2_TM_INIT_VALUE	include/ssv6200_reg.h	5059;"	d
+SET_TM2_TM_INIT_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	9473;"	d
+SET_TM2_TM_INT_MASK	include/ssv6200_reg.h	5062;"	d
+SET_TM2_TM_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	9476;"	d
+SET_TM2_TM_INT_STS_DONE	include/ssv6200_reg.h	5061;"	d
+SET_TM2_TM_INT_STS_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	9475;"	d
+SET_TM2_TM_MODE	include/ssv6200_reg.h	5060;"	d
+SET_TM2_TM_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	9474;"	d
+SET_TM3_PRESCALER_USTIMER_LOCAL	smac/hal/ssv6006c/ssv6006C_reg.h	9484;"	d
+SET_TM3_TM_CUR_VALUE	include/ssv6200_reg.h	5068;"	d
+SET_TM3_TM_CUR_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	9483;"	d
+SET_TM3_TM_INIT_VALUE	include/ssv6200_reg.h	5064;"	d
+SET_TM3_TM_INIT_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	9479;"	d
+SET_TM3_TM_INT_MASK	include/ssv6200_reg.h	5067;"	d
+SET_TM3_TM_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	9482;"	d
+SET_TM3_TM_INT_STS_DONE	include/ssv6200_reg.h	5066;"	d
+SET_TM3_TM_INT_STS_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	9481;"	d
+SET_TM3_TM_MODE	include/ssv6200_reg.h	5065;"	d
+SET_TM3_TM_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	9480;"	d
+SET_TOMAC_CS_CCA_MX	smac/hal/ssv6006c/ssv6006C_reg.h	10530;"	d
+SET_TOMAC_ED_CCA_PRIMARY_MX	smac/hal/ssv6006c/ssv6006C_reg.h	10528;"	d
+SET_TOMAC_ED_CCA_SECONDARY_MX	smac/hal/ssv6006c/ssv6006C_reg.h	10529;"	d
+SET_TOMAC_TX_IP	smac/hal/ssv6006c/ssv6006C_reg.h	10527;"	d
+SET_TOP_A	smac/hal/ssv6006c/ssv6006C_reg.h	9809;"	d
+SET_TOP_ON1_RST_N	smac/hal/ssv6006c/ssv6006C_reg.h	9422;"	d
+SET_TOP_ON2_RST_N	smac/hal/ssv6006c/ssv6006C_reg.h	9423;"	d
+SET_TOP_ON3_RST_N	smac/hal/ssv6006c/ssv6006C_reg.h	9424;"	d
+SET_TOP_SW_PWR_ON1_OUTPUT_PWR_ON1_1_0_0	smac/hal/ssv6006c/ssv6006C_reg.h	9373;"	d
+SET_TOP_SW_PWR_ON2_OUTPUT_PWR_ON2_1_0_0	smac/hal/ssv6006c/ssv6006C_reg.h	9374;"	d
+SET_TOP_SW_PWR_ON3_OUTPUT_PWR_ON3_1_0_0	smac/hal/ssv6006c/ssv6006C_reg.h	9375;"	d
+SET_TOUT_AGN	smac/hal/ssv6006c/ssv6006C_reg.h	10512;"	d
+SET_TOUT_B	smac/hal/ssv6006c/ssv6006C_reg.h	10511;"	d
+SET_TRAILEDGE_RI	include/ssv6200_reg.h	5791;"	d
+SET_TRAILEDGE_RI	smac/hal/ssv6006c/ssv6006C_reg.h	9782;"	d
+SET_TRANS_FULL_PKT_AMPDU1P2	smac/hal/ssv6006c/ssv6006C_reg.h	10177;"	d
+SET_TRAP_BOOT_FLS	include/ssv6200_reg.h	4934;"	d
+SET_TRAP_BOOT_FLS	smac/hal/ssv6006c/ssv6006C_reg.h	9293;"	d
+SET_TRAP_HW_ID	include/ssv6200_reg.h	6352;"	d
+SET_TRAP_HW_ID	smac/hal/ssv6006c/ssv6006C_reg.h	10356;"	d
+SET_TRAP_IMG_FLS	include/ssv6200_reg.h	4932;"	d
+SET_TRAP_IMG_FLS	smac/hal/ssv6006c/ssv6006C_reg.h	9291;"	d
+SET_TRAP_REBOOT	include/ssv6200_reg.h	4933;"	d
+SET_TRAP_REBOOT	smac/hal/ssv6006c/ssv6006C_reg.h	9292;"	d
+SET_TRAP_UNKNOWN_TYPE	include/ssv6200_reg.h	6113;"	d
+SET_TRASH_CAN_INT	include/ssv6200_reg.h	7370;"	d
+SET_TRASH_CAN_INT	smac/hal/ssv6006c/ssv6006C_reg.h	15827;"	d
+SET_TRASH_INT_ID	include/ssv6200_reg.h	7371;"	d
+SET_TRASH_INT_ID	smac/hal/ssv6006c/ssv6006C_reg.h	15828;"	d
+SET_TRASH_TIMEOUT	include/ssv6200_reg.h	7372;"	d
+SET_TRASH_TIMEOUT	smac/hal/ssv6006c/ssv6006C_reg.h	15829;"	d
+SET_TRASH_TIMEOUT_EN	include/ssv6200_reg.h	7369;"	d
+SET_TRASH_TIMEOUT_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15826;"	d
+SET_TRIGGER_FUNCTION_SETTING	include/ssv6200_reg.h	5536;"	d
+SET_TRIGGER_FUNCTION_SETTING	smac/hal/ssv6006c/ssv6006C_reg.h	9599;"	d
+SET_TRSW_PHY_POL	include/ssv6200_reg.h	6756;"	d
+SET_TRSW_PHY_POL	smac/hal/ssv6006c/ssv6006C_reg.h	10859;"	d
+SET_TRXBUSYFLAG	smac/hal/ssv6006c/ssv6006C_reg.h	9249;"	d
+SET_TRX_DEBUG_CNT_ENA	include/ssv6200_reg.h	6128;"	d
+SET_TRX_DEBUG_CNT_ENA	smac/hal/ssv6006c/ssv6006C_reg.h	10105;"	d
+SET_TRX_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	9242;"	d
+SET_TTHR_H	smac/hal/ssv6006c/ssv6006C_reg.h	9796;"	d
+SET_TTHR_L	smac/hal/ssv6006c/ssv6006C_reg.h	9795;"	d
+SET_TU0_PRESCALER_USTIMER_LOCAL	smac/hal/ssv6006c/ssv6006C_reg.h	9442;"	d
+SET_TU0_TM_CUR_VALUE	include/ssv6200_reg.h	5033;"	d
+SET_TU0_TM_CUR_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	9441;"	d
+SET_TU0_TM_INIT_VALUE	include/ssv6200_reg.h	5029;"	d
+SET_TU0_TM_INIT_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	9437;"	d
+SET_TU0_TM_INT_MASK	include/ssv6200_reg.h	5032;"	d
+SET_TU0_TM_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	9440;"	d
+SET_TU0_TM_INT_STS_DONE	include/ssv6200_reg.h	5031;"	d
+SET_TU0_TM_INT_STS_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	9439;"	d
+SET_TU0_TM_MODE	include/ssv6200_reg.h	5030;"	d
+SET_TU0_TM_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	9438;"	d
+SET_TU1_PRESCALER_USTIMER_LOCAL	smac/hal/ssv6006c/ssv6006C_reg.h	9448;"	d
+SET_TU1_TM_CUR_VALUE	include/ssv6200_reg.h	5038;"	d
+SET_TU1_TM_CUR_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	9447;"	d
+SET_TU1_TM_INIT_VALUE	include/ssv6200_reg.h	5034;"	d
+SET_TU1_TM_INIT_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	9443;"	d
+SET_TU1_TM_INT_MASK	include/ssv6200_reg.h	5037;"	d
+SET_TU1_TM_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	9446;"	d
+SET_TU1_TM_INT_STS_DONE	include/ssv6200_reg.h	5036;"	d
+SET_TU1_TM_INT_STS_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	9445;"	d
+SET_TU1_TM_MODE	include/ssv6200_reg.h	5035;"	d
+SET_TU1_TM_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	9444;"	d
+SET_TU2_PRESCALER_USTIMER_LOCAL	smac/hal/ssv6006c/ssv6006C_reg.h	9454;"	d
+SET_TU2_TM_CUR_VALUE	include/ssv6200_reg.h	5043;"	d
+SET_TU2_TM_CUR_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	9453;"	d
+SET_TU2_TM_INIT_VALUE	include/ssv6200_reg.h	5039;"	d
+SET_TU2_TM_INIT_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	9449;"	d
+SET_TU2_TM_INT_MASK	include/ssv6200_reg.h	5042;"	d
+SET_TU2_TM_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	9452;"	d
+SET_TU2_TM_INT_STS_DONE	include/ssv6200_reg.h	5041;"	d
+SET_TU2_TM_INT_STS_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	9451;"	d
+SET_TU2_TM_MODE	include/ssv6200_reg.h	5040;"	d
+SET_TU2_TM_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	9450;"	d
+SET_TU3_PRESCALER_USTIMER_LOCAL	smac/hal/ssv6006c/ssv6006C_reg.h	9460;"	d
+SET_TU3_TM_CUR_VALUE	include/ssv6200_reg.h	5048;"	d
+SET_TU3_TM_CUR_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	9459;"	d
+SET_TU3_TM_INIT_VALUE	include/ssv6200_reg.h	5044;"	d
+SET_TU3_TM_INIT_VALUE	smac/hal/ssv6006c/ssv6006C_reg.h	9455;"	d
+SET_TU3_TM_INT_MASK	include/ssv6200_reg.h	5047;"	d
+SET_TU3_TM_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	9458;"	d
+SET_TU3_TM_INT_STS_DONE	include/ssv6200_reg.h	5046;"	d
+SET_TU3_TM_INT_STS_DONE	smac/hal/ssv6006c/ssv6006C_reg.h	9457;"	d
+SET_TU3_TM_MODE	include/ssv6200_reg.h	5045;"	d
+SET_TU3_TM_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	9456;"	d
+SET_TURISMO_TRX_SAR_ADC_FSM_RDY	smac/hal/ssv6006c/ssv6006C_reg.h	12643;"	d
+SET_TWI_DELAY_ACK	smac/hal/ssv6006c/ssv6006C_reg.h	9724;"	d
+SET_TWI_DEV_A10B	smac/hal/ssv6006c/ssv6006C_reg.h	9718;"	d
+SET_TWI_DEV_A_10B	smac/hal/ssv6006c/ssv6006C_reg.h	9693;"	d
+SET_TWI_INT_HOLD_BUS	smac/hal/ssv6006c/ssv6006C_reg.h	9708;"	d
+SET_TWI_INT_HOLD_BUS_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9702;"	d
+SET_TWI_INT_HOLD_BUS_ST	smac/hal/ssv6006c/ssv6006C_reg.h	9714;"	d
+SET_TWI_INT_MISMATCH	smac/hal/ssv6006c/ssv6006C_reg.h	9706;"	d
+SET_TWI_INT_MISMATCH_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9700;"	d
+SET_TWI_INT_MISMATCH_ST	smac/hal/ssv6006c/ssv6006C_reg.h	9712;"	d
+SET_TWI_INT_RXD_STALL	smac/hal/ssv6006c/ssv6006C_reg.h	9704;"	d
+SET_TWI_INT_RXD_STALL_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9698;"	d
+SET_TWI_INT_RXD_STALL_ST	smac/hal/ssv6006c/ssv6006C_reg.h	9710;"	d
+SET_TWI_INT_TRANS_FAIL	smac/hal/ssv6006c/ssv6006C_reg.h	9707;"	d
+SET_TWI_INT_TRANS_FAIL_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9701;"	d
+SET_TWI_INT_TRANS_FAIL_ST	smac/hal/ssv6006c/ssv6006C_reg.h	9713;"	d
+SET_TWI_INT_TRANS_FINISH	smac/hal/ssv6006c/ssv6006C_reg.h	9705;"	d
+SET_TWI_INT_TRANS_FINISH_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9699;"	d
+SET_TWI_INT_TRANS_FINISH_ST	smac/hal/ssv6006c/ssv6006C_reg.h	9711;"	d
+SET_TWI_INT_TXD_STALL	smac/hal/ssv6006c/ssv6006C_reg.h	9703;"	d
+SET_TWI_INT_TXD_STALL_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9697;"	d
+SET_TWI_INT_TXD_STALL_ST	smac/hal/ssv6006c/ssv6006C_reg.h	9709;"	d
+SET_TWI_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	9694;"	d
+SET_TWI_PSCL	smac/hal/ssv6006c/ssv6006C_reg.h	9721;"	d
+SET_TWI_RX	smac/hal/ssv6006c/ssv6006C_reg.h	9717;"	d
+SET_TWI_RXD_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	9720;"	d
+SET_TWI_START_TRIG	smac/hal/ssv6006c/ssv6006C_reg.h	9690;"	d
+SET_TWI_STATUS_RECORD_0	smac/hal/ssv6006c/ssv6006C_reg.h	9715;"	d
+SET_TWI_STATUS_RECORD_1	smac/hal/ssv6006c/ssv6006C_reg.h	9716;"	d
+SET_TWI_STA_STO_PSCL	smac/hal/ssv6006c/ssv6006C_reg.h	9722;"	d
+SET_TWI_STOP_TRIG	smac/hal/ssv6006c/ssv6006C_reg.h	9691;"	d
+SET_TWI_TRANS_CONTINUE	smac/hal/ssv6006c/ssv6006C_reg.h	9692;"	d
+SET_TWI_TRANS_PSDA	smac/hal/ssv6006c/ssv6006C_reg.h	9723;"	d
+SET_TWI_TXD_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	9719;"	d
+SET_TXEMPTYFLAG	smac/hal/ssv6006c/ssv6006C_reg.h	9251;"	d
+SET_TXERRORFLAG	smac/hal/ssv6006c/ssv6006C_reg.h	9254;"	d
+SET_TXFIFO_RST	include/ssv6200_reg.h	5764;"	d
+SET_TXFIFO_RST	smac/hal/ssv6006c/ssv6006C_reg.h	9754;"	d
+SET_TXF_ID	include/ssv6200_reg.h	6134;"	d
+SET_TXF_ID	smac/hal/ssv6006c/ssv6006C_reg.h	10120;"	d
+SET_TXNOTFULLFLAG	smac/hal/ssv6006c/ssv6006C_reg.h	9250;"	d
+SET_TXQ0_MTX_Q_AIFSN	include/ssv6200_reg.h	6488;"	d
+SET_TXQ0_MTX_Q_AIFSN	smac/hal/ssv6006c/ssv6006C_reg.h	10544;"	d
+SET_TXQ0_MTX_Q_BKF_CNT	include/ssv6200_reg.h	6492;"	d
+SET_TXQ0_MTX_Q_BKF_CNT_FIX	smac/hal/ssv6006c/ssv6006C_reg.h	10548;"	d
+SET_TXQ0_MTX_Q_BKF_CNT_FIXED	include/ssv6200_reg.h	6483;"	d
+SET_TXQ0_MTX_Q_ECWMAX	include/ssv6200_reg.h	6490;"	d
+SET_TXQ0_MTX_Q_ECWMAX	smac/hal/ssv6006c/ssv6006C_reg.h	10546;"	d
+SET_TXQ0_MTX_Q_ECWMIN	include/ssv6200_reg.h	6489;"	d
+SET_TXQ0_MTX_Q_ECWMIN	smac/hal/ssv6006c/ssv6006C_reg.h	10545;"	d
+SET_TXQ0_MTX_Q_ID_MAP_L	include/ssv6200_reg.h	6495;"	d
+SET_TXQ0_MTX_Q_LRC_LIMIT	include/ssv6200_reg.h	6494;"	d
+SET_TXQ0_MTX_Q_MB_NO_RLS	include/ssv6200_reg.h	6485;"	d
+SET_TXQ0_MTX_Q_MB_NO_RLS	smac/hal/ssv6006c/ssv6006C_reg.h	10542;"	d
+SET_TXQ0_MTX_Q_PRE_LD	include/ssv6200_reg.h	6482;"	d
+SET_TXQ0_MTX_Q_RND_MODE	include/ssv6200_reg.h	6487;"	d
+SET_TXQ0_MTX_Q_RND_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	10541;"	d
+SET_TXQ0_MTX_Q_SRC_LIMIT	include/ssv6200_reg.h	6493;"	d
+SET_TXQ0_MTX_Q_TXOP_CH_THD	include/ssv6200_reg.h	6496;"	d
+SET_TXQ0_MTX_Q_TXOP_FRC_BUR	include/ssv6200_reg.h	6486;"	d
+SET_TXQ0_MTX_Q_TXOP_LIMIT	include/ssv6200_reg.h	6491;"	d
+SET_TXQ0_MTX_Q_TXOP_LIMIT	smac/hal/ssv6006c/ssv6006C_reg.h	10547;"	d
+SET_TXQ0_MTX_Q_TXOP_OV_THD	include/ssv6200_reg.h	6497;"	d
+SET_TXQ0_MTX_Q_TXOP_SUB_FRM_TIME	include/ssv6200_reg.h	6484;"	d
+SET_TXQ0_Q_NULLDATAFRAME_GEN_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10543;"	d
+SET_TXQ0_RO_AIFS_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	10552;"	d
+SET_TXQ0_RO_BKF_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	10553;"	d
+SET_TXQ0_RO_FSM_TXQ	smac/hal/ssv6006c/ssv6006C_reg.h	10549;"	d
+SET_TXQ0_RO_PKTID	smac/hal/ssv6006c/ssv6006C_reg.h	10554;"	d
+SET_TXQ0_RO_RATESET_IDX	smac/hal/ssv6006c/ssv6006C_reg.h	10551;"	d
+SET_TXQ0_RO_TRY_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	10550;"	d
+SET_TXQ1_MTX_Q_AIFSN	include/ssv6200_reg.h	6504;"	d
+SET_TXQ1_MTX_Q_AIFSN	smac/hal/ssv6006c/ssv6006C_reg.h	10558;"	d
+SET_TXQ1_MTX_Q_BKF_CNT	include/ssv6200_reg.h	6508;"	d
+SET_TXQ1_MTX_Q_BKF_CNT_FIX	smac/hal/ssv6006c/ssv6006C_reg.h	10562;"	d
+SET_TXQ1_MTX_Q_BKF_CNT_FIXED	include/ssv6200_reg.h	6499;"	d
+SET_TXQ1_MTX_Q_ECWMAX	include/ssv6200_reg.h	6506;"	d
+SET_TXQ1_MTX_Q_ECWMAX	smac/hal/ssv6006c/ssv6006C_reg.h	10560;"	d
+SET_TXQ1_MTX_Q_ECWMIN	include/ssv6200_reg.h	6505;"	d
+SET_TXQ1_MTX_Q_ECWMIN	smac/hal/ssv6006c/ssv6006C_reg.h	10559;"	d
+SET_TXQ1_MTX_Q_ID_MAP_L	include/ssv6200_reg.h	6511;"	d
+SET_TXQ1_MTX_Q_LRC_LIMIT	include/ssv6200_reg.h	6510;"	d
+SET_TXQ1_MTX_Q_MB_NO_RLS	include/ssv6200_reg.h	6501;"	d
+SET_TXQ1_MTX_Q_MB_NO_RLS	smac/hal/ssv6006c/ssv6006C_reg.h	10556;"	d
+SET_TXQ1_MTX_Q_PRE_LD	include/ssv6200_reg.h	6498;"	d
+SET_TXQ1_MTX_Q_RND_MODE	include/ssv6200_reg.h	6503;"	d
+SET_TXQ1_MTX_Q_RND_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	10555;"	d
+SET_TXQ1_MTX_Q_SRC_LIMIT	include/ssv6200_reg.h	6509;"	d
+SET_TXQ1_MTX_Q_TXOP_CH_THD	include/ssv6200_reg.h	6512;"	d
+SET_TXQ1_MTX_Q_TXOP_FRC_BUR	include/ssv6200_reg.h	6502;"	d
+SET_TXQ1_MTX_Q_TXOP_LIMIT	include/ssv6200_reg.h	6507;"	d
+SET_TXQ1_MTX_Q_TXOP_LIMIT	smac/hal/ssv6006c/ssv6006C_reg.h	10561;"	d
+SET_TXQ1_MTX_Q_TXOP_OV_THD	include/ssv6200_reg.h	6513;"	d
+SET_TXQ1_MTX_Q_TXOP_SUB_FRM_TIME	include/ssv6200_reg.h	6500;"	d
+SET_TXQ1_Q_NULLDATAFRAME_GEN_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10557;"	d
+SET_TXQ1_RO_AIFS_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	10566;"	d
+SET_TXQ1_RO_BKF_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	10567;"	d
+SET_TXQ1_RO_FSM_TXQ	smac/hal/ssv6006c/ssv6006C_reg.h	10563;"	d
+SET_TXQ1_RO_PKTID	smac/hal/ssv6006c/ssv6006C_reg.h	10568;"	d
+SET_TXQ1_RO_RATESET_IDX	smac/hal/ssv6006c/ssv6006C_reg.h	10565;"	d
+SET_TXQ1_RO_TRY_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	10564;"	d
+SET_TXQ2_MTX_Q_AIFSN	include/ssv6200_reg.h	6520;"	d
+SET_TXQ2_MTX_Q_AIFSN	smac/hal/ssv6006c/ssv6006C_reg.h	10572;"	d
+SET_TXQ2_MTX_Q_BKF_CNT	include/ssv6200_reg.h	6524;"	d
+SET_TXQ2_MTX_Q_BKF_CNT_FIX	smac/hal/ssv6006c/ssv6006C_reg.h	10576;"	d
+SET_TXQ2_MTX_Q_BKF_CNT_FIXED	include/ssv6200_reg.h	6515;"	d
+SET_TXQ2_MTX_Q_ECWMAX	include/ssv6200_reg.h	6522;"	d
+SET_TXQ2_MTX_Q_ECWMAX	smac/hal/ssv6006c/ssv6006C_reg.h	10574;"	d
+SET_TXQ2_MTX_Q_ECWMIN	include/ssv6200_reg.h	6521;"	d
+SET_TXQ2_MTX_Q_ECWMIN	smac/hal/ssv6006c/ssv6006C_reg.h	10573;"	d
+SET_TXQ2_MTX_Q_ID_MAP_L	include/ssv6200_reg.h	6527;"	d
+SET_TXQ2_MTX_Q_LRC_LIMIT	include/ssv6200_reg.h	6526;"	d
+SET_TXQ2_MTX_Q_MB_NO_RLS	include/ssv6200_reg.h	6517;"	d
+SET_TXQ2_MTX_Q_MB_NO_RLS	smac/hal/ssv6006c/ssv6006C_reg.h	10570;"	d
+SET_TXQ2_MTX_Q_PRE_LD	include/ssv6200_reg.h	6514;"	d
+SET_TXQ2_MTX_Q_RND_MODE	include/ssv6200_reg.h	6519;"	d
+SET_TXQ2_MTX_Q_RND_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	10569;"	d
+SET_TXQ2_MTX_Q_SRC_LIMIT	include/ssv6200_reg.h	6525;"	d
+SET_TXQ2_MTX_Q_TXOP_CH_THD	include/ssv6200_reg.h	6528;"	d
+SET_TXQ2_MTX_Q_TXOP_FRC_BUR	include/ssv6200_reg.h	6518;"	d
+SET_TXQ2_MTX_Q_TXOP_LIMIT	include/ssv6200_reg.h	6523;"	d
+SET_TXQ2_MTX_Q_TXOP_LIMIT	smac/hal/ssv6006c/ssv6006C_reg.h	10575;"	d
+SET_TXQ2_MTX_Q_TXOP_OV_THD	include/ssv6200_reg.h	6529;"	d
+SET_TXQ2_MTX_Q_TXOP_SUB_FRM_TIME	include/ssv6200_reg.h	6516;"	d
+SET_TXQ2_Q_NULLDATAFRAME_GEN_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10571;"	d
+SET_TXQ2_RO_AIFS_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	10580;"	d
+SET_TXQ2_RO_BKF_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	10581;"	d
+SET_TXQ2_RO_FSM_TXQ	smac/hal/ssv6006c/ssv6006C_reg.h	10577;"	d
+SET_TXQ2_RO_PKTID	smac/hal/ssv6006c/ssv6006C_reg.h	10582;"	d
+SET_TXQ2_RO_RATESET_IDX	smac/hal/ssv6006c/ssv6006C_reg.h	10579;"	d
+SET_TXQ2_RO_TRY_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	10578;"	d
+SET_TXQ3_MTX_Q_AIFSN	include/ssv6200_reg.h	6536;"	d
+SET_TXQ3_MTX_Q_AIFSN	smac/hal/ssv6006c/ssv6006C_reg.h	10586;"	d
+SET_TXQ3_MTX_Q_BKF_CNT	include/ssv6200_reg.h	6540;"	d
+SET_TXQ3_MTX_Q_BKF_CNT_FIX	smac/hal/ssv6006c/ssv6006C_reg.h	10590;"	d
+SET_TXQ3_MTX_Q_BKF_CNT_FIXED	include/ssv6200_reg.h	6531;"	d
+SET_TXQ3_MTX_Q_ECWMAX	include/ssv6200_reg.h	6538;"	d
+SET_TXQ3_MTX_Q_ECWMAX	smac/hal/ssv6006c/ssv6006C_reg.h	10588;"	d
+SET_TXQ3_MTX_Q_ECWMIN	include/ssv6200_reg.h	6537;"	d
+SET_TXQ3_MTX_Q_ECWMIN	smac/hal/ssv6006c/ssv6006C_reg.h	10587;"	d
+SET_TXQ3_MTX_Q_ID_MAP_L	include/ssv6200_reg.h	6543;"	d
+SET_TXQ3_MTX_Q_LRC_LIMIT	include/ssv6200_reg.h	6542;"	d
+SET_TXQ3_MTX_Q_MB_NO_RLS	include/ssv6200_reg.h	6533;"	d
+SET_TXQ3_MTX_Q_MB_NO_RLS	smac/hal/ssv6006c/ssv6006C_reg.h	10584;"	d
+SET_TXQ3_MTX_Q_PRE_LD	include/ssv6200_reg.h	6530;"	d
+SET_TXQ3_MTX_Q_RND_MODE	include/ssv6200_reg.h	6535;"	d
+SET_TXQ3_MTX_Q_RND_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	10583;"	d
+SET_TXQ3_MTX_Q_SRC_LIMIT	include/ssv6200_reg.h	6541;"	d
+SET_TXQ3_MTX_Q_TXOP_CH_THD	include/ssv6200_reg.h	6544;"	d
+SET_TXQ3_MTX_Q_TXOP_FRC_BUR	include/ssv6200_reg.h	6534;"	d
+SET_TXQ3_MTX_Q_TXOP_LIMIT	include/ssv6200_reg.h	6539;"	d
+SET_TXQ3_MTX_Q_TXOP_LIMIT	smac/hal/ssv6006c/ssv6006C_reg.h	10589;"	d
+SET_TXQ3_MTX_Q_TXOP_OV_THD	include/ssv6200_reg.h	6545;"	d
+SET_TXQ3_MTX_Q_TXOP_SUB_FRM_TIME	include/ssv6200_reg.h	6532;"	d
+SET_TXQ3_Q_NULLDATAFRAME_GEN_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10585;"	d
+SET_TXQ3_RO_AIFS_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	10594;"	d
+SET_TXQ3_RO_BKF_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	10595;"	d
+SET_TXQ3_RO_FSM_TXQ	smac/hal/ssv6006c/ssv6006C_reg.h	10591;"	d
+SET_TXQ3_RO_PKTID	smac/hal/ssv6006c/ssv6006C_reg.h	10596;"	d
+SET_TXQ3_RO_RATESET_IDX	smac/hal/ssv6006c/ssv6006C_reg.h	10593;"	d
+SET_TXQ3_RO_TRY_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	10592;"	d
+SET_TXQ4_MTX_Q_AIFSN	include/ssv6200_reg.h	6552;"	d
+SET_TXQ4_MTX_Q_AIFSN	smac/hal/ssv6006c/ssv6006C_reg.h	10600;"	d
+SET_TXQ4_MTX_Q_BKF_CNT	include/ssv6200_reg.h	6556;"	d
+SET_TXQ4_MTX_Q_BKF_CNT_FIX	smac/hal/ssv6006c/ssv6006C_reg.h	10604;"	d
+SET_TXQ4_MTX_Q_BKF_CNT_FIXED	include/ssv6200_reg.h	6547;"	d
+SET_TXQ4_MTX_Q_ECWMAX	include/ssv6200_reg.h	6554;"	d
+SET_TXQ4_MTX_Q_ECWMAX	smac/hal/ssv6006c/ssv6006C_reg.h	10602;"	d
+SET_TXQ4_MTX_Q_ECWMIN	include/ssv6200_reg.h	6553;"	d
+SET_TXQ4_MTX_Q_ECWMIN	smac/hal/ssv6006c/ssv6006C_reg.h	10601;"	d
+SET_TXQ4_MTX_Q_ID_MAP_L	include/ssv6200_reg.h	6559;"	d
+SET_TXQ4_MTX_Q_LRC_LIMIT	include/ssv6200_reg.h	6558;"	d
+SET_TXQ4_MTX_Q_MB_NO_RLS	include/ssv6200_reg.h	6549;"	d
+SET_TXQ4_MTX_Q_MB_NO_RLS	smac/hal/ssv6006c/ssv6006C_reg.h	10598;"	d
+SET_TXQ4_MTX_Q_PRE_LD	include/ssv6200_reg.h	6546;"	d
+SET_TXQ4_MTX_Q_RND_MODE	include/ssv6200_reg.h	6551;"	d
+SET_TXQ4_MTX_Q_RND_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	10597;"	d
+SET_TXQ4_MTX_Q_SRC_LIMIT	include/ssv6200_reg.h	6557;"	d
+SET_TXQ4_MTX_Q_TXOP_CH_THD	include/ssv6200_reg.h	6560;"	d
+SET_TXQ4_MTX_Q_TXOP_FRC_BUR	include/ssv6200_reg.h	6550;"	d
+SET_TXQ4_MTX_Q_TXOP_LIMIT	include/ssv6200_reg.h	6555;"	d
+SET_TXQ4_MTX_Q_TXOP_LIMIT	smac/hal/ssv6006c/ssv6006C_reg.h	10603;"	d
+SET_TXQ4_MTX_Q_TXOP_OV_THD	include/ssv6200_reg.h	6561;"	d
+SET_TXQ4_MTX_Q_TXOP_SUB_FRM_TIME	include/ssv6200_reg.h	6548;"	d
+SET_TXQ4_Q_NULLDATAFRAME_GEN_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10599;"	d
+SET_TXQ4_RO_AIFS_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	10608;"	d
+SET_TXQ4_RO_BKF_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	10609;"	d
+SET_TXQ4_RO_FSM_TXQ	smac/hal/ssv6006c/ssv6006C_reg.h	10605;"	d
+SET_TXQ4_RO_PKTID	smac/hal/ssv6006c/ssv6006C_reg.h	10610;"	d
+SET_TXQ4_RO_RATESET_IDX	smac/hal/ssv6006c/ssv6006C_reg.h	10607;"	d
+SET_TXQ4_RO_TRY_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	10606;"	d
+SET_TXQ5_DTIM_BEACON_BURST_MNG	smac/hal/ssv6006c/ssv6006C_reg.h	10502;"	d
+SET_TXQ5_MTX_Q_AIFSN	smac/hal/ssv6006c/ssv6006C_reg.h	10614;"	d
+SET_TXQ5_MTX_Q_BKF_CNT_FIX	smac/hal/ssv6006c/ssv6006C_reg.h	10618;"	d
+SET_TXQ5_MTX_Q_ECWMAX	smac/hal/ssv6006c/ssv6006C_reg.h	10616;"	d
+SET_TXQ5_MTX_Q_ECWMIN	smac/hal/ssv6006c/ssv6006C_reg.h	10615;"	d
+SET_TXQ5_MTX_Q_MB_NO_RLS	smac/hal/ssv6006c/ssv6006C_reg.h	10612;"	d
+SET_TXQ5_MTX_Q_RND_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	10611;"	d
+SET_TXQ5_MTX_Q_TXOP_LIMIT	smac/hal/ssv6006c/ssv6006C_reg.h	10617;"	d
+SET_TXQ5_Q_NULLDATAFRAME_GEN_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10613;"	d
+SET_TXQ5_RO_AIFS_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	10622;"	d
+SET_TXQ5_RO_BKF_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	10623;"	d
+SET_TXQ5_RO_FSM_TXQ	smac/hal/ssv6006c/ssv6006C_reg.h	10619;"	d
+SET_TXQ5_RO_PKTID	smac/hal/ssv6006c/ssv6006C_reg.h	10624;"	d
+SET_TXQ5_RO_RATESET_IDX	smac/hal/ssv6006c/ssv6006C_reg.h	10621;"	d
+SET_TXQ5_RO_TRY_CNT	smac/hal/ssv6006c/ssv6006C_reg.h	10620;"	d
+SET_TXQ_ID0	include/ssv6200_reg.h	6121;"	d
+SET_TXQ_ID0	smac/hal/ssv6006c/ssv6006C_reg.h	10100;"	d
+SET_TXQ_ID1	include/ssv6200_reg.h	6122;"	d
+SET_TXQ_ID1	smac/hal/ssv6006c/ssv6006C_reg.h	10101;"	d
+SET_TXSIFS_SUB_MAX	smac/hal/ssv6006c/ssv6006C_reg.h	10515;"	d
+SET_TXSIFS_SUB_MIN	smac/hal/ssv6006c/ssv6006C_reg.h	10514;"	d
+SET_TXTRAP_ETHTYPE0	include/ssv6200_reg.h	6143;"	d
+SET_TXTRAP_ETHTYPE0	smac/hal/ssv6006c/ssv6006C_reg.h	10139;"	d
+SET_TXTRAP_ETHTYPE1	include/ssv6200_reg.h	6142;"	d
+SET_TXTRAP_ETHTYPE1	smac/hal/ssv6006c/ssv6006C_reg.h	10138;"	d
+SET_TX_ACK_POLICY_0_0	include/ssv6200_reg.h	6568;"	d
+SET_TX_ACK_POLICY_0_0	smac/hal/ssv6006c/ssv6006C_reg.h	10711;"	d
+SET_TX_ACK_POLICY_0_1	include/ssv6200_reg.h	6570;"	d
+SET_TX_ACK_POLICY_0_1	smac/hal/ssv6006c/ssv6006C_reg.h	10713;"	d
+SET_TX_ACK_POLICY_0_2	include/ssv6200_reg.h	6572;"	d
+SET_TX_ACK_POLICY_0_2	smac/hal/ssv6006c/ssv6006C_reg.h	10715;"	d
+SET_TX_ACK_POLICY_0_3	include/ssv6200_reg.h	6574;"	d
+SET_TX_ACK_POLICY_0_3	smac/hal/ssv6006c/ssv6006C_reg.h	10717;"	d
+SET_TX_ACK_POLICY_0_4	include/ssv6200_reg.h	6576;"	d
+SET_TX_ACK_POLICY_0_4	smac/hal/ssv6006c/ssv6006C_reg.h	10719;"	d
+SET_TX_ACK_POLICY_0_5	include/ssv6200_reg.h	6578;"	d
+SET_TX_ACK_POLICY_0_5	smac/hal/ssv6006c/ssv6006C_reg.h	10721;"	d
+SET_TX_ACK_POLICY_0_6	include/ssv6200_reg.h	6580;"	d
+SET_TX_ACK_POLICY_0_6	smac/hal/ssv6006c/ssv6006C_reg.h	10723;"	d
+SET_TX_ACK_POLICY_0_7	include/ssv6200_reg.h	6582;"	d
+SET_TX_ACK_POLICY_0_7	smac/hal/ssv6006c/ssv6006C_reg.h	10725;"	d
+SET_TX_ACK_POLICY_1_0	include/ssv6200_reg.h	6590;"	d
+SET_TX_ACK_POLICY_1_0	smac/hal/ssv6006c/ssv6006C_reg.h	10733;"	d
+SET_TX_ACK_POLICY_1_1	include/ssv6200_reg.h	6592;"	d
+SET_TX_ACK_POLICY_1_1	smac/hal/ssv6006c/ssv6006C_reg.h	10735;"	d
+SET_TX_ACK_POLICY_1_2	include/ssv6200_reg.h	6594;"	d
+SET_TX_ACK_POLICY_1_2	smac/hal/ssv6006c/ssv6006C_reg.h	10737;"	d
+SET_TX_ACK_POLICY_1_3	include/ssv6200_reg.h	6596;"	d
+SET_TX_ACK_POLICY_1_3	smac/hal/ssv6006c/ssv6006C_reg.h	10739;"	d
+SET_TX_ACK_POLICY_1_4	include/ssv6200_reg.h	6598;"	d
+SET_TX_ACK_POLICY_1_4	smac/hal/ssv6006c/ssv6006C_reg.h	10741;"	d
+SET_TX_ACK_POLICY_1_5	include/ssv6200_reg.h	6600;"	d
+SET_TX_ACK_POLICY_1_5	smac/hal/ssv6006c/ssv6006C_reg.h	10743;"	d
+SET_TX_ACK_POLICY_1_6	include/ssv6200_reg.h	6602;"	d
+SET_TX_ACK_POLICY_1_6	smac/hal/ssv6006c/ssv6006C_reg.h	10745;"	d
+SET_TX_ACK_POLICY_1_7	include/ssv6200_reg.h	6604;"	d
+SET_TX_ACK_POLICY_1_7	smac/hal/ssv6006c/ssv6006C_reg.h	10747;"	d
+SET_TX_ACK_POLICY_2_0	smac/hal/ssv6006c/ssv6006C_reg.h	10966;"	d
+SET_TX_ACK_POLICY_2_1	smac/hal/ssv6006c/ssv6006C_reg.h	10968;"	d
+SET_TX_ACK_POLICY_2_2	smac/hal/ssv6006c/ssv6006C_reg.h	10970;"	d
+SET_TX_ACK_POLICY_2_3	smac/hal/ssv6006c/ssv6006C_reg.h	10972;"	d
+SET_TX_ACK_POLICY_2_4	smac/hal/ssv6006c/ssv6006C_reg.h	10974;"	d
+SET_TX_ACK_POLICY_2_5	smac/hal/ssv6006c/ssv6006C_reg.h	10976;"	d
+SET_TX_ACK_POLICY_2_6	smac/hal/ssv6006c/ssv6006C_reg.h	10978;"	d
+SET_TX_ACK_POLICY_2_7	smac/hal/ssv6006c/ssv6006C_reg.h	10980;"	d
+SET_TX_ACK_POLICY_3_0	smac/hal/ssv6006c/ssv6006C_reg.h	10988;"	d
+SET_TX_ACK_POLICY_3_1	smac/hal/ssv6006c/ssv6006C_reg.h	10990;"	d
+SET_TX_ACK_POLICY_3_2	smac/hal/ssv6006c/ssv6006C_reg.h	10992;"	d
+SET_TX_ACK_POLICY_3_3	smac/hal/ssv6006c/ssv6006C_reg.h	10994;"	d
+SET_TX_ACK_POLICY_3_4	smac/hal/ssv6006c/ssv6006C_reg.h	10996;"	d
+SET_TX_ACK_POLICY_3_5	smac/hal/ssv6006c/ssv6006C_reg.h	10998;"	d
+SET_TX_ACK_POLICY_3_6	smac/hal/ssv6006c/ssv6006C_reg.h	11000;"	d
+SET_TX_ACK_POLICY_3_7	smac/hal/ssv6006c/ssv6006C_reg.h	11002;"	d
+SET_TX_ACK_POLICY_4_0	smac/hal/ssv6006c/ssv6006C_reg.h	11010;"	d
+SET_TX_ACK_POLICY_4_1	smac/hal/ssv6006c/ssv6006C_reg.h	11012;"	d
+SET_TX_ACK_POLICY_4_2	smac/hal/ssv6006c/ssv6006C_reg.h	11014;"	d
+SET_TX_ACK_POLICY_4_3	smac/hal/ssv6006c/ssv6006C_reg.h	11016;"	d
+SET_TX_ACK_POLICY_4_4	smac/hal/ssv6006c/ssv6006C_reg.h	11018;"	d
+SET_TX_ACK_POLICY_4_5	smac/hal/ssv6006c/ssv6006C_reg.h	11020;"	d
+SET_TX_ACK_POLICY_4_6	smac/hal/ssv6006c/ssv6006C_reg.h	11022;"	d
+SET_TX_ACK_POLICY_4_7	smac/hal/ssv6006c/ssv6006C_reg.h	11024;"	d
+SET_TX_ACK_POLICY_5_0	smac/hal/ssv6006c/ssv6006C_reg.h	11032;"	d
+SET_TX_ACK_POLICY_5_1	smac/hal/ssv6006c/ssv6006C_reg.h	11034;"	d
+SET_TX_ACK_POLICY_5_2	smac/hal/ssv6006c/ssv6006C_reg.h	11036;"	d
+SET_TX_ACK_POLICY_5_3	smac/hal/ssv6006c/ssv6006C_reg.h	11038;"	d
+SET_TX_ACK_POLICY_5_4	smac/hal/ssv6006c/ssv6006C_reg.h	11040;"	d
+SET_TX_ACK_POLICY_5_5	smac/hal/ssv6006c/ssv6006C_reg.h	11042;"	d
+SET_TX_ACK_POLICY_5_6	smac/hal/ssv6006c/ssv6006C_reg.h	11044;"	d
+SET_TX_ACK_POLICY_5_7	smac/hal/ssv6006c/ssv6006C_reg.h	11046;"	d
+SET_TX_ACK_POLICY_6_0	smac/hal/ssv6006c/ssv6006C_reg.h	11054;"	d
+SET_TX_ACK_POLICY_6_1	smac/hal/ssv6006c/ssv6006C_reg.h	11056;"	d
+SET_TX_ACK_POLICY_6_2	smac/hal/ssv6006c/ssv6006C_reg.h	11058;"	d
+SET_TX_ACK_POLICY_6_3	smac/hal/ssv6006c/ssv6006C_reg.h	11060;"	d
+SET_TX_ACK_POLICY_6_4	smac/hal/ssv6006c/ssv6006C_reg.h	11062;"	d
+SET_TX_ACK_POLICY_6_5	smac/hal/ssv6006c/ssv6006C_reg.h	11064;"	d
+SET_TX_ACK_POLICY_6_6	smac/hal/ssv6006c/ssv6006C_reg.h	11066;"	d
+SET_TX_ACK_POLICY_6_7	smac/hal/ssv6006c/ssv6006C_reg.h	11068;"	d
+SET_TX_ACK_POLICY_7_0	smac/hal/ssv6006c/ssv6006C_reg.h	11076;"	d
+SET_TX_ACK_POLICY_7_1	smac/hal/ssv6006c/ssv6006C_reg.h	11078;"	d
+SET_TX_ACK_POLICY_7_2	smac/hal/ssv6006c/ssv6006C_reg.h	11080;"	d
+SET_TX_ACK_POLICY_7_3	smac/hal/ssv6006c/ssv6006C_reg.h	11082;"	d
+SET_TX_ACK_POLICY_7_4	smac/hal/ssv6006c/ssv6006C_reg.h	11084;"	d
+SET_TX_ACK_POLICY_7_5	smac/hal/ssv6006c/ssv6006C_reg.h	11086;"	d
+SET_TX_ACK_POLICY_7_6	smac/hal/ssv6006c/ssv6006C_reg.h	11088;"	d
+SET_TX_ACK_POLICY_7_7	smac/hal/ssv6006c/ssv6006C_reg.h	11090;"	d
+SET_TX_CCA_DUR	include/ssv6200_reg.h	6460;"	d
+SET_TX_COMPLETE_INT	include/ssv6200_reg.h	5520;"	d
+SET_TX_COUNT_LIMIT	include/ssv6200_reg.h	7465;"	d
+SET_TX_COUNT_LIMIT	smac/hal/ssv6006c/ssv6006C_reg.h	15909;"	d
+SET_TX_DISCARD_CNT	include/ssv6200_reg.h	5718;"	d
+SET_TX_DISCARD_CNT_CLR	include/ssv6200_reg.h	5720;"	d
+SET_TX_DONE	include/ssv6200_reg.h	5548;"	d
+SET_TX_DONE_CNT	include/ssv6200_reg.h	5717;"	d
+SET_TX_DONE_CNT_CLR	include/ssv6200_reg.h	5721;"	d
+SET_TX_DONE_STATUS	include/ssv6200_reg.h	5605;"	d
+SET_TX_EMPTY	include/ssv6200_reg.h	5787;"	d
+SET_TX_EMPTY	smac/hal/ssv6006c/ssv6006C_reg.h	9778;"	d
+SET_TX_EMPTY2	smac/hal/ssv6006c/ssv6006C_reg.h	9801;"	d
+SET_TX_ERR_FIRST_4B_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10118;"	d
+SET_TX_ERR_RECOVER	smac/hal/ssv6006c/ssv6006C_reg.h	10117;"	d
+SET_TX_ETHER_TRAP_EN	include/ssv6200_reg.h	6123;"	d
+SET_TX_ETHER_TRAP_EN	smac/hal/ssv6006c/ssv6006C_reg.h	10102;"	d
+SET_TX_FIFO_FAIL	include/ssv6200_reg.h	5700;"	d
+SET_TX_FIFO_RESIDUE	include/ssv6200_reg.h	5724;"	d
+SET_TX_FLOW_CTRL	include/ssv6200_reg.h	6130;"	d
+SET_TX_FLOW_CTRL	smac/hal/ssv6006c/ssv6006C_reg.h	10110;"	d
+SET_TX_FLOW_DATA	include/ssv6200_reg.h	6132;"	d
+SET_TX_FLOW_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	10112;"	d
+SET_TX_FLOW_MGMT	include/ssv6200_reg.h	6131;"	d
+SET_TX_FLOW_MGMT	smac/hal/ssv6006c/ssv6006C_reg.h	10111;"	d
+SET_TX_H	smac/hal/ssv6006c/ssv6006C_reg.h	9800;"	d
+SET_TX_HOST_FAIL	include/ssv6200_reg.h	5701;"	d
+SET_TX_IDLE	smac/hal/ssv6006c/ssv6006C_reg.h	9793;"	d
+SET_TX_ID_ALC_LEN	include/ssv6200_reg.h	7454;"	d
+SET_TX_ID_ALC_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	15898;"	d
+SET_TX_ID_COUNT	include/ssv6200_reg.h	7430;"	d
+SET_TX_ID_COUNT	smac/hal/ssv6006c/ssv6006C_reg.h	15874;"	d
+SET_TX_ID_IFO_LEN	include/ssv6200_reg.h	7491;"	d
+SET_TX_ID_IFO_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	15937;"	d
+SET_TX_ID_LEN_THOLD	include/ssv6200_reg.h	5908;"	d
+SET_TX_ID_LEN_THOLD_INT	include/ssv6200_reg.h	7448;"	d
+SET_TX_ID_LEN_THOLD_INT	smac/hal/ssv6006c/ssv6006C_reg.h	15892;"	d
+SET_TX_ID_LEN_THOLD_SD	include/ssv6200_reg.h	5977;"	d
+SET_TX_ID_REMAIN	include/ssv6200_reg.h	7461;"	d
+SET_TX_ID_REMAIN	smac/hal/ssv6006c/ssv6006C_reg.h	15905;"	d
+SET_TX_ID_REMAIN2	include/ssv6200_reg.h	5631;"	d
+SET_TX_ID_REMAIN3	include/ssv6200_reg.h	5619;"	d
+SET_TX_ID_TB0	include/ssv6200_reg.h	7439;"	d
+SET_TX_ID_TB0	smac/hal/ssv6006c/ssv6006C_reg.h	15883;"	d
+SET_TX_ID_TB1	include/ssv6200_reg.h	7440;"	d
+SET_TX_ID_TB1	smac/hal/ssv6006c/ssv6006C_reg.h	15884;"	d
+SET_TX_ID_TB2	include/ssv6200_reg.h	7476;"	d
+SET_TX_ID_TB2	smac/hal/ssv6006c/ssv6006C_reg.h	15920;"	d
+SET_TX_ID_TB3	include/ssv6200_reg.h	7477;"	d
+SET_TX_ID_TB3	smac/hal/ssv6006c/ssv6006C_reg.h	15921;"	d
+SET_TX_ID_THOLD	include/ssv6200_reg.h	7432;"	d
+SET_TX_ID_THOLD	smac/hal/ssv6006c/ssv6006C_reg.h	15876;"	d
+SET_TX_ID_USE2	include/ssv6200_reg.h	7481;"	d
+SET_TX_ID_USE2	smac/hal/ssv6006c/ssv6006C_reg.h	15925;"	d
+SET_TX_ID_USE3	include/ssv6200_reg.h	7484;"	d
+SET_TX_ID_USE3	smac/hal/ssv6006c/ssv6006C_reg.h	15929;"	d
+SET_TX_ID_USE4	include/ssv6200_reg.h	7488;"	d
+SET_TX_ID_USE4	smac/hal/ssv6006c/ssv6006C_reg.h	15934;"	d
+SET_TX_ID_USE_5_0	include/ssv6200_reg.h	7469;"	d
+SET_TX_ID_USE_5_0	smac/hal/ssv6006c/ssv6006C_reg.h	15913;"	d
+SET_TX_INFO_CLEAR_ENABLE	include/ssv6200_reg.h	6141;"	d
+SET_TX_INFO_CLEAR_ENABLE	smac/hal/ssv6006c/ssv6006C_reg.h	10129;"	d
+SET_TX_INFO_CLEAR_SIZE	include/ssv6200_reg.h	6140;"	d
+SET_TX_INFO_CLEAR_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	10128;"	d
+SET_TX_INFO_SIZE	include/ssv6200_reg.h	6137;"	d
+SET_TX_INFO_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	10125;"	d
+SET_TX_INT_CH	include/ssv6200_reg.h	7437;"	d
+SET_TX_INT_CH	smac/hal/ssv6006c/ssv6006C_reg.h	15881;"	d
+SET_TX_IP_FALL_OFFSET_STEP	smac/hal/ssv6006c/ssv6006C_reg.h	10519;"	d
+SET_TX_L	smac/hal/ssv6006c/ssv6006C_reg.h	9799;"	d
+SET_TX_LIMIT_INT	include/ssv6200_reg.h	7466;"	d
+SET_TX_LIMIT_INT	smac/hal/ssv6006c/ssv6006C_reg.h	15910;"	d
+SET_TX_LIMIT_INT_EN	include/ssv6200_reg.h	7467;"	d
+SET_TX_LIMIT_INT_EN	smac/hal/ssv6006c/ssv6006C_reg.h	15911;"	d
+SET_TX_LIMIT_INT_IN	include/ssv6200_reg.h	5732;"	d
+SET_TX_LIMIT_INT_MASK	include/ssv6200_reg.h	5518;"	d
+SET_TX_LIMIT_INT_MASK	smac/hal/ssv6006c/ssv6006C_reg.h	9581;"	d
+SET_TX_LIMIT_INT_STS	include/ssv6200_reg.h	5526;"	d
+SET_TX_LIMIT_INT_STS	smac/hal/ssv6006c/ssv6006C_reg.h	9589;"	d
+SET_TX_MOUNT	include/ssv6200_reg.h	8498;"	d
+SET_TX_ON_DEMAND_ENA	include/ssv6200_reg.h	6114;"	d
+SET_TX_ON_DEMAND_ENA	smac/hal/ssv6006c/ssv6006C_reg.h	10093;"	d
+SET_TX_ON_DEMAND_LENGTH	include/ssv6200_reg.h	6158;"	d
+SET_TX_ON_DEMAND_LENGTH	smac/hal/ssv6006c/ssv6006C_reg.h	10161;"	d
+SET_TX_PAGE_LIMIT	include/ssv6200_reg.h	7464;"	d
+SET_TX_PAGE_LIMIT	smac/hal/ssv6006c/ssv6006C_reg.h	15908;"	d
+SET_TX_PAGE_REMAIN	include/ssv6200_reg.h	7462;"	d
+SET_TX_PAGE_REMAIN	smac/hal/ssv6006c/ssv6006C_reg.h	15906;"	d
+SET_TX_PAGE_REMAIN2	include/ssv6200_reg.h	5618;"	d
+SET_TX_PAGE_REMAIN3	include/ssv6200_reg.h	5632;"	d
+SET_TX_PAGE_USE2	include/ssv6200_reg.h	7480;"	d
+SET_TX_PAGE_USE2	smac/hal/ssv6006c/ssv6006C_reg.h	15924;"	d
+SET_TX_PAGE_USE3	include/ssv6200_reg.h	7483;"	d
+SET_TX_PAGE_USE3	smac/hal/ssv6006c/ssv6006C_reg.h	15928;"	d
+SET_TX_PAGE_USE4	include/ssv6200_reg.h	7487;"	d
+SET_TX_PAGE_USE4	smac/hal/ssv6006c/ssv6006C_reg.h	15933;"	d
+SET_TX_PAGE_USE_7_0	include/ssv6200_reg.h	7468;"	d
+SET_TX_PAGE_USE_7_0	smac/hal/ssv6006c/ssv6006C_reg.h	15912;"	d
+SET_TX_PBOFFSET	include/ssv6200_reg.h	6136;"	d
+SET_TX_PBOFFSET	smac/hal/ssv6006c/ssv6006C_reg.h	10124;"	d
+SET_TX_PKT_COUNTER	include/ssv6200_reg.h	6146;"	d
+SET_TX_PKT_COUNTER	smac/hal/ssv6006c/ssv6006C_reg.h	10171;"	d
+SET_TX_PKT_DROP_COUNTER	include/ssv6200_reg.h	6150;"	d
+SET_TX_PKT_DROP_COUNTER	smac/hal/ssv6006c/ssv6006C_reg.h	10167;"	d
+SET_TX_PKT_RSVD	include/ssv6200_reg.h	6734;"	d
+SET_TX_PKT_RSVD	smac/hal/ssv6006c/ssv6006C_reg.h	10830;"	d
+SET_TX_PKT_SEND_ID	smac/hal/ssv6006c/ssv6006C_reg.h	10144;"	d
+SET_TX_PKT_SEND_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	10142;"	d
+SET_TX_PKT_SEND_TO_RX	smac/hal/ssv6006c/ssv6006C_reg.h	10175;"	d
+SET_TX_PKT_TRAP_COUNTER	include/ssv6200_reg.h	6152;"	d
+SET_TX_PKT_TRAP_COUNTER	smac/hal/ssv6006c/ssv6006C_reg.h	10165;"	d
+SET_TX_RX_LOOP_BACK_TEST	include/ssv6200_reg.h	5540;"	d
+SET_TX_RX_TRAP_HW_ID_SELECT_ENABLE	smac/hal/ssv6006c/ssv6006C_reg.h	10178;"	d
+SET_TX_SCALE_11B	include/ssv6200_reg.h	8111;"	d
+SET_TX_SCALE_11B_P0D5	include/ssv6200_reg.h	8112;"	d
+SET_TX_SCALE_11G	include/ssv6200_reg.h	8113;"	d
+SET_TX_SCALE_11G_P0D5	include/ssv6200_reg.h	8114;"	d
+SET_TX_SDIO_PKT_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	10143;"	d
+SET_TX_SEG	include/ssv6200_reg.h	5692;"	d
+SET_TX_SEG	smac/hal/ssv6006c/ssv6006C_reg.h	9685;"	d
+SET_TX_SEQ_CTRL_0_0	include/ssv6200_reg.h	6569;"	d
+SET_TX_SEQ_CTRL_0_0	smac/hal/ssv6006c/ssv6006C_reg.h	10712;"	d
+SET_TX_SEQ_CTRL_0_1	include/ssv6200_reg.h	6571;"	d
+SET_TX_SEQ_CTRL_0_1	smac/hal/ssv6006c/ssv6006C_reg.h	10714;"	d
+SET_TX_SEQ_CTRL_0_2	include/ssv6200_reg.h	6573;"	d
+SET_TX_SEQ_CTRL_0_2	smac/hal/ssv6006c/ssv6006C_reg.h	10716;"	d
+SET_TX_SEQ_CTRL_0_3	include/ssv6200_reg.h	6575;"	d
+SET_TX_SEQ_CTRL_0_3	smac/hal/ssv6006c/ssv6006C_reg.h	10718;"	d
+SET_TX_SEQ_CTRL_0_4	include/ssv6200_reg.h	6577;"	d
+SET_TX_SEQ_CTRL_0_4	smac/hal/ssv6006c/ssv6006C_reg.h	10720;"	d
+SET_TX_SEQ_CTRL_0_5	include/ssv6200_reg.h	6579;"	d
+SET_TX_SEQ_CTRL_0_5	smac/hal/ssv6006c/ssv6006C_reg.h	10722;"	d
+SET_TX_SEQ_CTRL_0_6	include/ssv6200_reg.h	6581;"	d
+SET_TX_SEQ_CTRL_0_6	smac/hal/ssv6006c/ssv6006C_reg.h	10724;"	d
+SET_TX_SEQ_CTRL_0_7	include/ssv6200_reg.h	6583;"	d
+SET_TX_SEQ_CTRL_0_7	smac/hal/ssv6006c/ssv6006C_reg.h	10726;"	d
+SET_TX_SEQ_CTRL_1_0	include/ssv6200_reg.h	6591;"	d
+SET_TX_SEQ_CTRL_1_0	smac/hal/ssv6006c/ssv6006C_reg.h	10734;"	d
+SET_TX_SEQ_CTRL_1_1	include/ssv6200_reg.h	6593;"	d
+SET_TX_SEQ_CTRL_1_1	smac/hal/ssv6006c/ssv6006C_reg.h	10736;"	d
+SET_TX_SEQ_CTRL_1_2	include/ssv6200_reg.h	6595;"	d
+SET_TX_SEQ_CTRL_1_2	smac/hal/ssv6006c/ssv6006C_reg.h	10738;"	d
+SET_TX_SEQ_CTRL_1_3	include/ssv6200_reg.h	6597;"	d
+SET_TX_SEQ_CTRL_1_3	smac/hal/ssv6006c/ssv6006C_reg.h	10740;"	d
+SET_TX_SEQ_CTRL_1_4	include/ssv6200_reg.h	6599;"	d
+SET_TX_SEQ_CTRL_1_4	smac/hal/ssv6006c/ssv6006C_reg.h	10742;"	d
+SET_TX_SEQ_CTRL_1_5	include/ssv6200_reg.h	6601;"	d
+SET_TX_SEQ_CTRL_1_5	smac/hal/ssv6006c/ssv6006C_reg.h	10744;"	d
+SET_TX_SEQ_CTRL_1_6	include/ssv6200_reg.h	6603;"	d
+SET_TX_SEQ_CTRL_1_6	smac/hal/ssv6006c/ssv6006C_reg.h	10746;"	d
+SET_TX_SEQ_CTRL_1_7	include/ssv6200_reg.h	6605;"	d
+SET_TX_SEQ_CTRL_1_7	smac/hal/ssv6006c/ssv6006C_reg.h	10748;"	d
+SET_TX_SEQ_CTRL_2_0	smac/hal/ssv6006c/ssv6006C_reg.h	10967;"	d
+SET_TX_SEQ_CTRL_2_1	smac/hal/ssv6006c/ssv6006C_reg.h	10969;"	d
+SET_TX_SEQ_CTRL_2_2	smac/hal/ssv6006c/ssv6006C_reg.h	10971;"	d
+SET_TX_SEQ_CTRL_2_3	smac/hal/ssv6006c/ssv6006C_reg.h	10973;"	d
+SET_TX_SEQ_CTRL_2_4	smac/hal/ssv6006c/ssv6006C_reg.h	10975;"	d
+SET_TX_SEQ_CTRL_2_5	smac/hal/ssv6006c/ssv6006C_reg.h	10977;"	d
+SET_TX_SEQ_CTRL_2_6	smac/hal/ssv6006c/ssv6006C_reg.h	10979;"	d
+SET_TX_SEQ_CTRL_2_7	smac/hal/ssv6006c/ssv6006C_reg.h	10981;"	d
+SET_TX_SEQ_CTRL_3_0	smac/hal/ssv6006c/ssv6006C_reg.h	10989;"	d
+SET_TX_SEQ_CTRL_3_1	smac/hal/ssv6006c/ssv6006C_reg.h	10991;"	d
+SET_TX_SEQ_CTRL_3_2	smac/hal/ssv6006c/ssv6006C_reg.h	10993;"	d
+SET_TX_SEQ_CTRL_3_3	smac/hal/ssv6006c/ssv6006C_reg.h	10995;"	d
+SET_TX_SEQ_CTRL_3_4	smac/hal/ssv6006c/ssv6006C_reg.h	10997;"	d
+SET_TX_SEQ_CTRL_3_5	smac/hal/ssv6006c/ssv6006C_reg.h	10999;"	d
+SET_TX_SEQ_CTRL_3_6	smac/hal/ssv6006c/ssv6006C_reg.h	11001;"	d
+SET_TX_SEQ_CTRL_3_7	smac/hal/ssv6006c/ssv6006C_reg.h	11003;"	d
+SET_TX_SEQ_CTRL_4_0	smac/hal/ssv6006c/ssv6006C_reg.h	11011;"	d
+SET_TX_SEQ_CTRL_4_1	smac/hal/ssv6006c/ssv6006C_reg.h	11013;"	d
+SET_TX_SEQ_CTRL_4_2	smac/hal/ssv6006c/ssv6006C_reg.h	11015;"	d
+SET_TX_SEQ_CTRL_4_3	smac/hal/ssv6006c/ssv6006C_reg.h	11017;"	d
+SET_TX_SEQ_CTRL_4_4	smac/hal/ssv6006c/ssv6006C_reg.h	11019;"	d
+SET_TX_SEQ_CTRL_4_5	smac/hal/ssv6006c/ssv6006C_reg.h	11021;"	d
+SET_TX_SEQ_CTRL_4_6	smac/hal/ssv6006c/ssv6006C_reg.h	11023;"	d
+SET_TX_SEQ_CTRL_4_7	smac/hal/ssv6006c/ssv6006C_reg.h	11025;"	d
+SET_TX_SEQ_CTRL_5_0	smac/hal/ssv6006c/ssv6006C_reg.h	11033;"	d
+SET_TX_SEQ_CTRL_5_1	smac/hal/ssv6006c/ssv6006C_reg.h	11035;"	d
+SET_TX_SEQ_CTRL_5_2	smac/hal/ssv6006c/ssv6006C_reg.h	11037;"	d
+SET_TX_SEQ_CTRL_5_3	smac/hal/ssv6006c/ssv6006C_reg.h	11039;"	d
+SET_TX_SEQ_CTRL_5_4	smac/hal/ssv6006c/ssv6006C_reg.h	11041;"	d
+SET_TX_SEQ_CTRL_5_5	smac/hal/ssv6006c/ssv6006C_reg.h	11043;"	d
+SET_TX_SEQ_CTRL_5_6	smac/hal/ssv6006c/ssv6006C_reg.h	11045;"	d
+SET_TX_SEQ_CTRL_5_7	smac/hal/ssv6006c/ssv6006C_reg.h	11047;"	d
+SET_TX_SEQ_CTRL_6_0	smac/hal/ssv6006c/ssv6006C_reg.h	11055;"	d
+SET_TX_SEQ_CTRL_6_1	smac/hal/ssv6006c/ssv6006C_reg.h	11057;"	d
+SET_TX_SEQ_CTRL_6_2	smac/hal/ssv6006c/ssv6006C_reg.h	11059;"	d
+SET_TX_SEQ_CTRL_6_3	smac/hal/ssv6006c/ssv6006C_reg.h	11061;"	d
+SET_TX_SEQ_CTRL_6_4	smac/hal/ssv6006c/ssv6006C_reg.h	11063;"	d
+SET_TX_SEQ_CTRL_6_5	smac/hal/ssv6006c/ssv6006C_reg.h	11065;"	d
+SET_TX_SEQ_CTRL_6_6	smac/hal/ssv6006c/ssv6006C_reg.h	11067;"	d
+SET_TX_SEQ_CTRL_6_7	smac/hal/ssv6006c/ssv6006C_reg.h	11069;"	d
+SET_TX_SEQ_CTRL_7_0	smac/hal/ssv6006c/ssv6006C_reg.h	11077;"	d
+SET_TX_SEQ_CTRL_7_1	smac/hal/ssv6006c/ssv6006C_reg.h	11079;"	d
+SET_TX_SEQ_CTRL_7_2	smac/hal/ssv6006c/ssv6006C_reg.h	11081;"	d
+SET_TX_SEQ_CTRL_7_3	smac/hal/ssv6006c/ssv6006C_reg.h	11083;"	d
+SET_TX_SEQ_CTRL_7_4	smac/hal/ssv6006c/ssv6006C_reg.h	11085;"	d
+SET_TX_SEQ_CTRL_7_5	smac/hal/ssv6006c/ssv6006C_reg.h	11087;"	d
+SET_TX_SEQ_CTRL_7_6	smac/hal/ssv6006c/ssv6006C_reg.h	11089;"	d
+SET_TX_SEQ_CTRL_7_7	smac/hal/ssv6006c/ssv6006C_reg.h	11091;"	d
+SET_TX_SET_CNT	include/ssv6200_reg.h	5719;"	d
+SET_TX_SET_CNT_CLR	include/ssv6200_reg.h	5722;"	d
+SET_TX_SIZE_BEFORE_SHIFT	include/ssv6200_reg.h	5599;"	d
+SET_TX_SIZE_SHIFT_BITS	include/ssv6200_reg.h	5600;"	d
+SET_TX_THRH_IE	smac/hal/ssv6006c/ssv6006C_reg.h	9750;"	d
+SET_TX_THRL_IE	smac/hal/ssv6006c/ssv6006C_reg.h	9751;"	d
+SET_TX_TRAP_HW_ID	smac/hal/ssv6006c/ssv6006C_reg.h	10179;"	d
+SET_UART_CLK_EN	include/ssv6200_reg.h	4946;"	d
+SET_UART_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9305;"	d
+SET_UART_DATA	include/ssv6200_reg.h	5755;"	d
+SET_UART_DATA	smac/hal/ssv6006c/ssv6006C_reg.h	9745;"	d
+SET_UART_MULTI_IRQ	include/ssv6200_reg.h	5901;"	d
+SET_UART_MULTI_IRQ_SD	include/ssv6200_reg.h	5970;"	d
+SET_UART_NCTS	include/ssv6200_reg.h	5028;"	d
+SET_UART_NCTS	smac/hal/ssv6006c/ssv6006C_reg.h	9412;"	d
+SET_UART_NRTS	include/ssv6200_reg.h	5027;"	d
+SET_UART_NRTS	smac/hal/ssv6006c/ssv6006C_reg.h	9411;"	d
+SET_UART_RXD_SEL	include/ssv6200_reg.h	5495;"	d
+SET_UART_RX_TIMEOUT	include/ssv6200_reg.h	5900;"	d
+SET_UART_RX_TIMEOUT_SD	include/ssv6200_reg.h	5969;"	d
+SET_UART_SW_RST	include/ssv6200_reg.h	4912;"	d
+SET_UART_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	9272;"	d
+SET_UART_W2B_EN	include/ssv6200_reg.h	4991;"	d
+SET_UART_W2B_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9351;"	d
+SET_US0TMR_CLK_EN	include/ssv6200_reg.h	4953;"	d
+SET_US0TMR_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9312;"	d
+SET_US0TMR_SW_RST	include/ssv6200_reg.h	4919;"	d
+SET_US0TMR_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	9278;"	d
+SET_US1TMR_CLK_EN	include/ssv6200_reg.h	4954;"	d
+SET_US1TMR_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9313;"	d
+SET_US1TMR_SW_RST	include/ssv6200_reg.h	4920;"	d
+SET_US1TMR_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	9279;"	d
+SET_US2TMR_CLK_EN	include/ssv6200_reg.h	4955;"	d
+SET_US2TMR_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9314;"	d
+SET_US2TMR_SW_RST	include/ssv6200_reg.h	4921;"	d
+SET_US2TMR_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	9280;"	d
+SET_US3TMR_CLK_EN	include/ssv6200_reg.h	4956;"	d
+SET_US3TMR_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9315;"	d
+SET_US3TMR_SW_RST	include/ssv6200_reg.h	4922;"	d
+SET_US3TMR_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	9281;"	d
+SET_USB20_HOST_SELRW	smac/hal/ssv6006c/ssv6006C_reg.h	9400;"	d
+SET_USB_BULK_IN_LEN_INIT	smac/hal/ssv6006c/ssv6006C_reg.h	10148;"	d
+SET_USB_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9325;"	d
+SET_USB_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	9269;"	d
+SET_USB_WAKE_PMU_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9429;"	d
+SET_VALID0	include/ssv6200_reg.h	6562;"	d
+SET_VALID0	smac/hal/ssv6006c/ssv6006C_reg.h	10705;"	d
+SET_VALID1	include/ssv6200_reg.h	6584;"	d
+SET_VALID1	smac/hal/ssv6006c/ssv6006C_reg.h	10727;"	d
+SET_VALID2	smac/hal/ssv6006c/ssv6006C_reg.h	10960;"	d
+SET_VALID3	smac/hal/ssv6006c/ssv6006C_reg.h	10982;"	d
+SET_VALID4	smac/hal/ssv6006c/ssv6006C_reg.h	11004;"	d
+SET_VALID5	smac/hal/ssv6006c/ssv6006C_reg.h	11026;"	d
+SET_VALID6	smac/hal/ssv6006c/ssv6006C_reg.h	11048;"	d
+SET_VALID7	smac/hal/ssv6006c/ssv6006C_reg.h	11070;"	d
+SET_VERIFY_DATA	include/ssv6200_reg.h	6036;"	d
+SET_VIAROM_EMA	smac/hal/ssv6006c/ssv6006C_reg.h	9376;"	d
+SET_VT_MON_RDY	include/ssv6200_reg.h	8416;"	d
+SET_W0_T0_SEQ	include/ssv6200_reg.h	6355;"	d
+SET_W0_T1_SEQ	include/ssv6200_reg.h	6356;"	d
+SET_W0_T2_SEQ	include/ssv6200_reg.h	6357;"	d
+SET_W0_T3_SEQ	include/ssv6200_reg.h	6358;"	d
+SET_W0_T4_SEQ	include/ssv6200_reg.h	6359;"	d
+SET_W0_T5_SEQ	include/ssv6200_reg.h	6360;"	d
+SET_W0_T6_SEQ	include/ssv6200_reg.h	6361;"	d
+SET_W0_T7_SEQ	include/ssv6200_reg.h	6362;"	d
+SET_W1_T0_SEQ	include/ssv6200_reg.h	6363;"	d
+SET_W1_T1_SEQ	include/ssv6200_reg.h	6364;"	d
+SET_W1_T2_SEQ	include/ssv6200_reg.h	6365;"	d
+SET_W1_T3_SEQ	include/ssv6200_reg.h	6366;"	d
+SET_W1_T4_SEQ	include/ssv6200_reg.h	6367;"	d
+SET_W1_T5_SEQ	include/ssv6200_reg.h	6368;"	d
+SET_W1_T6_SEQ	include/ssv6200_reg.h	6369;"	d
+SET_W1_T7_SEQ	include/ssv6200_reg.h	6370;"	d
+SET_WAKE_SOON_WITH_SCK	include/ssv6200_reg.h	6129;"	d
+SET_WAKE_SOON_WITH_SCK	smac/hal/ssv6006c/ssv6006C_reg.h	9405;"	d
+SET_WDT_CLK_EN	include/ssv6200_reg.h	4948;"	d
+SET_WDT_CLK_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9307;"	d
+SET_WDT_INIT	include/ssv6200_reg.h	5024;"	d
+SET_WDT_MCU_RESET	smac/hal/ssv6006c/ssv6006C_reg.h	9407;"	d
+SET_WDT_SW_RST	include/ssv6200_reg.h	4914;"	d
+SET_WDT_SW_RST	smac/hal/ssv6006c/ssv6006C_reg.h	9274;"	d
+SET_WDT_SYS_RESET	smac/hal/ssv6006c/ssv6006C_reg.h	9408;"	d
+SET_WIFI_RX_SW_O_C	include/ssv6200_reg.h	5094;"	d
+SET_WIFI_RX_SW_O_OE	include/ssv6200_reg.h	5089;"	d
+SET_WIFI_RX_SW_O_PE	include/ssv6200_reg.h	5090;"	d
+SET_WIFI_RX_SW_POL	include/ssv6200_reg.h	6758;"	d
+SET_WIFI_RX_SW_POL	smac/hal/ssv6006c/ssv6006C_reg.h	10861;"	d
+SET_WIFI_TX_SW_O_C	include/ssv6200_reg.h	5088;"	d
+SET_WIFI_TX_SW_O_OE	include/ssv6200_reg.h	5082;"	d
+SET_WIFI_TX_SW_O_PE	include/ssv6200_reg.h	5083;"	d
+SET_WIFI_TX_SW_POL	include/ssv6200_reg.h	6757;"	d
+SET_WIFI_TX_SW_POL	smac/hal/ssv6006c/ssv6006C_reg.h	10860;"	d
+SET_WIRE_MODE	include/ssv6200_reg.h	6748;"	d
+SET_WIRE_MODE	smac/hal/ssv6006c/ssv6006C_reg.h	10851;"	d
+SET_WLAN_ACT_POL	include/ssv6200_reg.h	6754;"	d
+SET_WLAN_ACT_POL	smac/hal/ssv6006c/ssv6006C_reg.h	10857;"	d
+SET_WLAN_REMAIN_TIME	include/ssv6200_reg.h	6763;"	d
+SET_WLAN_REMAIN_TIME	smac/hal/ssv6006c/ssv6006C_reg.h	10866;"	d
+SET_WL_RX_PRI	include/ssv6200_reg.h	6749;"	d
+SET_WL_RX_PRI	smac/hal/ssv6006c/ssv6006C_reg.h	10852;"	d
+SET_WL_TX_PRI	include/ssv6200_reg.h	6750;"	d
+SET_WL_TX_PRI	smac/hal/ssv6006c/ssv6006C_reg.h	10853;"	d
+SET_WORD_LEN	include/ssv6200_reg.h	5769;"	d
+SET_WORD_LEN	smac/hal/ssv6006c/ssv6006C_reg.h	9759;"	d
+SET_WRAP_EN	smac/hal/ssv6006c/ssv6006C_reg.h	9885;"	d
+SET_WRITE_ADDRESS	include/ssv6200_reg.h	5577;"	d
+SET_WRITE_DATA	include/ssv6200_reg.h	5576;"	d
+SET_WR_ADDR	include/ssv6200_reg.h	6187;"	d
+SET_WR_ADDR	smac/hal/ssv6006c/ssv6006C_reg.h	10205;"	d
+SET_WR_ID	include/ssv6200_reg.h	6188;"	d
+SET_WR_ID	smac/hal/ssv6006c/ssv6006C_reg.h	10206;"	d
+SET_XLNA_EN_O_C	include/ssv6200_reg.h	5081;"	d
+SET_XLNA_EN_O_OE	include/ssv6200_reg.h	5075;"	d
+SET_XLNA_EN_O_PE	include/ssv6200_reg.h	5076;"	d
+SET_XPA_EN_O_C	include/ssv6200_reg.h	5108;"	d
+SET_XPA_EN_O_OE	include/ssv6200_reg.h	5102;"	d
+SET_XPA_EN_O_PE	include/ssv6200_reg.h	5103;"	d
+SFD_CNT_HI	include/ssv6200_aux.h	14599;"	d
+SFD_CNT_I_MSK	include/ssv6200_aux.h	14597;"	d
+SFD_CNT_MSK	include/ssv6200_aux.h	14596;"	d
+SFD_CNT_SFT	include/ssv6200_aux.h	14598;"	d
+SFD_CNT_SZ	include/ssv6200_aux.h	14600;"	d
+SFD_FIELD_HI	include/ssv6200_aux.h	14629;"	d
+SFD_FIELD_I_MSK	include/ssv6200_aux.h	14627;"	d
+SFD_FIELD_MSK	include/ssv6200_aux.h	14626;"	d
+SFD_FIELD_SFT	include/ssv6200_aux.h	14628;"	d
+SFD_FIELD_SZ	include/ssv6200_aux.h	14630;"	d
+SGI_DETECT_MCS67	smac/ssv_rc_minstrel_ht.h	/^ SGI_DETECT_MCS67,$/;"	e	enum:ssv6xxx_sgi_stat
+SGI_DETECT_SGI	smac/ssv_rc_minstrel_ht.h	/^ SGI_DETECT_SGI,$/;"	e	enum:ssv6xxx_sgi_stat
+SGI_ENABLE_SGI	smac/ssv_rc_minstrel_ht.h	/^ SGI_ENABLE_SGI,$/;"	e	enum:ssv6xxx_sgi_stat
+SGI_FORBID_SGI	smac/ssv_rc_minstrel_ht.h	/^ SGI_FORBID_SGI,$/;"	e	enum:ssv6xxx_sgi_stat
+SHA1_CTX	crypto/sha1_glue.c	/^struct SHA1_CTX {$/;"	s	file:
+SHA1_CTX::count	crypto/sha1_glue.c	/^ u64 count;$/;"	m	struct:SHA1_CTX	file:	access:public
+SHA1_CTX::data	crypto/sha1_glue.c	/^ u8 data[SHA1_BLOCK_SIZE];$/;"	m	struct:SHA1_CTX	file:	access:public
+SHA1_CTX::h0	crypto/sha1_glue.c	/^ uint32_t h0,h1,h2,h3,h4;$/;"	m	struct:SHA1_CTX	file:	access:public
+SHA1_CTX::h1	crypto/sha1_glue.c	/^ uint32_t h0,h1,h2,h3,h4;$/;"	m	struct:SHA1_CTX	file:	access:public
+SHA1_CTX::h2	crypto/sha1_glue.c	/^ uint32_t h0,h1,h2,h3,h4;$/;"	m	struct:SHA1_CTX	file:	access:public
+SHA1_CTX::h3	crypto/sha1_glue.c	/^ uint32_t h0,h1,h2,h3,h4;$/;"	m	struct:SHA1_CTX	file:	access:public
+SHA1_CTX::h4	crypto/sha1_glue.c	/^ uint32_t h0,h1,h2,h3,h4;$/;"	m	struct:SHA1_CTX	file:	access:public
+SHA256_BLOCK_SIZE	smac/wapi_sms4.c	18;"	d	file:
+SHA256_DIGEST_SIZE	smac/wapi_sms4.c	19;"	d	file:
+SHA_BUSY_HI	include/ssv6200_aux.h	6484;"	d
+SHA_BUSY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5729;"	d
+SHA_BUSY_I_MSK	include/ssv6200_aux.h	6482;"	d
+SHA_BUSY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5727;"	d
+SHA_BUSY_MSK	include/ssv6200_aux.h	6481;"	d
+SHA_BUSY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5726;"	d
+SHA_BUSY_SFT	include/ssv6200_aux.h	6483;"	d
+SHA_BUSY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5728;"	d
+SHA_BUSY_SZ	include/ssv6200_aux.h	6485;"	d
+SHA_BUSY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5730;"	d
+SHA_DST_ADDR_HI	include/ssv6200_aux.h	6474;"	d
+SHA_DST_ADDR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5719;"	d
+SHA_DST_ADDR_I_MSK	include/ssv6200_aux.h	6472;"	d
+SHA_DST_ADDR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5717;"	d
+SHA_DST_ADDR_MSK	include/ssv6200_aux.h	6471;"	d
+SHA_DST_ADDR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5716;"	d
+SHA_DST_ADDR_SFT	include/ssv6200_aux.h	6473;"	d
+SHA_DST_ADDR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5718;"	d
+SHA_DST_ADDR_SZ	include/ssv6200_aux.h	6475;"	d
+SHA_DST_ADDR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5720;"	d
+SHA_ENDIAN_HI	include/ssv6200_aux.h	6489;"	d
+SHA_ENDIAN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5734;"	d
+SHA_ENDIAN_I_MSK	include/ssv6200_aux.h	6487;"	d
+SHA_ENDIAN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5732;"	d
+SHA_ENDIAN_MSK	include/ssv6200_aux.h	6486;"	d
+SHA_ENDIAN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5731;"	d
+SHA_ENDIAN_SFT	include/ssv6200_aux.h	6488;"	d
+SHA_ENDIAN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5733;"	d
+SHA_ENDIAN_SZ	include/ssv6200_aux.h	6490;"	d
+SHA_ENDIAN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5735;"	d
+SHA_SRC_ADDR_HI	include/ssv6200_aux.h	6479;"	d
+SHA_SRC_ADDR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5724;"	d
+SHA_SRC_ADDR_I_MSK	include/ssv6200_aux.h	6477;"	d
+SHA_SRC_ADDR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5722;"	d
+SHA_SRC_ADDR_MSK	include/ssv6200_aux.h	6476;"	d
+SHA_SRC_ADDR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5721;"	d
+SHA_SRC_ADDR_SFT	include/ssv6200_aux.h	6478;"	d
+SHA_SRC_ADDR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5723;"	d
+SHA_SRC_ADDR_SZ	include/ssv6200_aux.h	6480;"	d
+SHA_SRC_ADDR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5725;"	d
+SHIFT_DR_HI	include/ssv6200_aux.h	379;"	d
+SHIFT_DR_I_MSK	include/ssv6200_aux.h	377;"	d
+SHIFT_DR_MSK	include/ssv6200_aux.h	376;"	d
+SHIFT_DR_SFT	include/ssv6200_aux.h	378;"	d
+SHIFT_DR_SZ	include/ssv6200_aux.h	380;"	d
+SHORT_TO_20_ID_HI	include/ssv6200_aux.h	1224;"	d
+SHORT_TO_20_ID_I_MSK	include/ssv6200_aux.h	1222;"	d
+SHORT_TO_20_ID_MSK	include/ssv6200_aux.h	1221;"	d
+SHORT_TO_20_ID_SFT	include/ssv6200_aux.h	1223;"	d
+SHORT_TO_20_ID_SZ	include/ssv6200_aux.h	1225;"	d
+SHPCHECK	smac/init.c	98;"	d	file:
+SHRT_GI_HI	include/ssv6200_aux.h	6449;"	d
+SHRT_GI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5694;"	d
+SHRT_GI_I_MSK	include/ssv6200_aux.h	6447;"	d
+SHRT_GI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5692;"	d
+SHRT_GI_MSK	include/ssv6200_aux.h	6446;"	d
+SHRT_GI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5691;"	d
+SHRT_GI_SFT	include/ssv6200_aux.h	6448;"	d
+SHRT_GI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5693;"	d
+SHRT_GI_SZ	include/ssv6200_aux.h	6450;"	d
+SHRT_GI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5695;"	d
+SHRT_PREAM_HI	include/ssv6200_aux.h	6444;"	d
+SHRT_PREAM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5689;"	d
+SHRT_PREAM_I_MSK	include/ssv6200_aux.h	6442;"	d
+SHRT_PREAM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5687;"	d
+SHRT_PREAM_MSK	include/ssv6200_aux.h	6441;"	d
+SHRT_PREAM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5686;"	d
+SHRT_PREAM_SFT	include/ssv6200_aux.h	6443;"	d
+SHRT_PREAM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5688;"	d
+SHRT_PREAM_SZ	include/ssv6200_aux.h	6445;"	d
+SHRT_PREAM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5690;"	d
+SIFS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7344;"	d
+SIFS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7342;"	d
+SIFS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7341;"	d
+SIFS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7343;"	d
+SIFS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7345;"	d
+SIGEXT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7364;"	d
+SIGEXT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7362;"	d
+SIGEXT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7361;"	d
+SIGEXT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7363;"	d
+SIGEXT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7365;"	d
+SIGNAL_FIELD0_HI	include/ssv6200_aux.h	15249;"	d
+SIGNAL_FIELD0_I_MSK	include/ssv6200_aux.h	15247;"	d
+SIGNAL_FIELD0_MSK	include/ssv6200_aux.h	15246;"	d
+SIGNAL_FIELD0_SFT	include/ssv6200_aux.h	15248;"	d
+SIGNAL_FIELD0_SZ	include/ssv6200_aux.h	15250;"	d
+SIGNAL_FIELD1_HI	include/ssv6200_aux.h	15254;"	d
+SIGNAL_FIELD1_I_MSK	include/ssv6200_aux.h	15252;"	d
+SIGNAL_FIELD1_MSK	include/ssv6200_aux.h	15251;"	d
+SIGNAL_FIELD1_SFT	include/ssv6200_aux.h	15253;"	d
+SIGNAL_FIELD1_SZ	include/ssv6200_aux.h	15255;"	d
+SIGNAL_FIELD_HI	include/ssv6200_aux.h	14634;"	d
+SIGNAL_FIELD_I_MSK	include/ssv6200_aux.h	14632;"	d
+SIGNAL_FIELD_MSK	include/ssv6200_aux.h	14631;"	d
+SIGNAL_FIELD_SFT	include/ssv6200_aux.h	14633;"	d
+SIGNAL_FIELD_SZ	include/ssv6200_aux.h	14635;"	d
+SIMULATION_MODE_HI	include/ssv6200_aux.h	389;"	d
+SIMULATION_MODE_I_MSK	include/ssv6200_aux.h	387;"	d
+SIMULATION_MODE_MSK	include/ssv6200_aux.h	386;"	d
+SIMULATION_MODE_SFT	include/ssv6200_aux.h	388;"	d
+SIMULATION_MODE_SZ	include/ssv6200_aux.h	390;"	d
+SINGLE_BAND_PATCH	smac/hal/ssv6006c/turismo_common.h	2817;"	d
+SIZE_A_BAND_GAIN	smac/hal/ssv6006c/ssv6006_common.c	634;"	d	file:
+SIZE_BAND_GAIN_TBL	smac/hal/ssv6006c/ssv6006_turismoC.c	2538;"	d	file:
+SIZE_BANK_SSV6200	include/ssv6200_reg_sim.h	/^static const u32 SIZE_BANK_SSV6200[] = {$/;"	v
+SIZE_BANK_SSV6200	smac/hal/ssv6006c/ssv6006C_reg_sim.h	/^static const u32 SIZE_BANK_SSV6200[] = {$/;"	v
+SIZE_B_RATE_GAIN_TBL	smac/hal/ssv6006c/ssv6006_turismoC.c	2461;"	d	file:
+SIZE_G_BAND_GAIN	smac/hal/ssv6006c/ssv6006_common.c	628;"	d	file:
+SIZE_RATE_DELTA	smac/hal/ssv6006c/ssv6006_common.c	640;"	d	file:
+SIZE_RATE_TBL	smac/hal/ssv6006c/ssv6006C_mac.c	1479;"	d	file:
+SIZE_RATE_TBL	smac/hal/ssv6006c/ssv6006_turismoC.c	2062;"	d	file:
+SI_ST_MAX	smac/kssvsmart.h	/^ SI_ST_MAX$/;"	e	enum:__anon8
+SI_ST_NG	smac/kssvsmart.h	/^ SI_ST_NG,$/;"	e	enum:__anon8
+SI_ST_OK	smac/kssvsmart.h	/^ SI_ST_OK,$/;"	e	enum:__anon8
+SI_ST_PROCESSING	smac/kssvsmart.h	/^ SI_ST_PROCESSING,$/;"	e	enum:__anon8
+SKB_DURATION_STAGE_END	include/ssv6xxx_common.h	/^ SKB_DURATION_STAGE_END$/;"	e	enum:ssv_debug_skb_timestamp
+SKB_DURATION_STAGE_IN_HWQ	include/ssv6xxx_common.h	/^ SKB_DURATION_STAGE_IN_HWQ,$/;"	e	enum:ssv_debug_skb_timestamp
+SKB_DURATION_STAGE_TO_SDIO	include/ssv6xxx_common.h	/^ SKB_DURATION_STAGE_TO_SDIO,$/;"	e	enum:ssv_debug_skb_timestamp
+SKB_DURATION_STAGE_TX_ENQ	include/ssv6xxx_common.h	/^ SKB_DURATION_STAGE_TX_ENQ,$/;"	e	enum:ssv_debug_skb_timestamp
+SKB_DURATION_TIMEOUT_MS	include/ssv6xxx_common.h	304;"	d
+SKB_info	smac/ssv_skb.h	/^typedef struct SKB_info_st SKB_info;$/;"	t	typeref:struct:SKB_info_st
+SKB_info_st	smac/ssv_skb.h	/^struct SKB_info_st$/;"	s
+SKB_info_st::aggr_timestamp	smac/ssv_skb.h	/^    unsigned long aggr_timestamp;$/;"	m	struct:SKB_info_st	access:public
+SKB_info_st::ampdu_tx_final_retry_count	smac/ssv_skb.h	/^    u16 ampdu_tx_final_retry_count;$/;"	m	struct:SKB_info_st	access:public
+SKB_info_st::ampdu_tx_status	smac/ssv_skb.h	/^    u16 ampdu_tx_status;$/;"	m	struct:SKB_info_st	access:public
+SKB_info_st::crypt_st	smac/ssv_skb.h	/^    volatile u8 crypt_st;$/;"	m	struct:SKB_info_st	access:public
+SKB_info_st::directly_ack	smac/ssv_skb.h	/^    bool directly_ack;$/;"	m	struct:SKB_info_st	access:public
+SKB_info_st::lowest_rate	smac/ssv_skb.h	/^    u16 lowest_rate;$/;"	m	struct:SKB_info_st	access:public
+SKB_info_st::mpdu_retry_counter	smac/ssv_skb.h	/^    u16 mpdu_retry_counter;$/;"	m	struct:SKB_info_st	access:public
+SKB_info_st::rates	smac/ssv_skb.h	/^    struct fw_rc_retry_params rates[SSV62XX_TX_MAX_RATES];$/;"	m	struct:SKB_info_st	typeref:struct:SKB_info_st::fw_rc_retry_params	access:public
+SKB_info_st::sta	smac/ssv_skb.h	/^    struct ieee80211_sta *sta;$/;"	m	struct:SKB_info_st	typeref:struct:SKB_info_st::ieee80211_sta	access:public
+SKB_info_st::timestamp	smac/ssv_skb.h	/^    ktime_t timestamp;$/;"	m	struct:SKB_info_st	access:public
+SLEEP_WAKE_CNT_HI	include/ssv6200_aux.h	5839;"	d
+SLEEP_WAKE_CNT_I_MSK	include/ssv6200_aux.h	5837;"	d
+SLEEP_WAKE_CNT_MSK	include/ssv6200_aux.h	5836;"	d
+SLEEP_WAKE_CNT_SFT	include/ssv6200_aux.h	5838;"	d
+SLEEP_WAKE_CNT_SZ	include/ssv6200_aux.h	5840;"	d
+SLOTTIME_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7339;"	d
+SLOTTIME_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7337;"	d
+SLOTTIME_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7336;"	d
+SLOTTIME_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7338;"	d
+SLOTTIME_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7340;"	d
+SMAC_BURST_REG_READ	smac/ssv_reg_acc.h	60;"	d
+SMAC_BURST_REG_SAFE_READ	smac/ssv_reg_acc.h	50;"	d
+SMAC_BURST_REG_SAFE_WRITE	smac/ssv_reg_acc.h	55;"	d
+SMAC_BURST_REG_WRITE	smac/ssv_reg_acc.h	65;"	d
+SMAC_IFC_RESET	smac/ssv_reg_acc.h	75;"	d
+SMAC_LOAD_FW	smac/ssv_reg_acc.h	70;"	d
+SMAC_REG_CONFIRM	smac/ssv_reg_acc.h	85;"	d
+SMAC_REG_CONFIRM_CHECK	smac/init.c	912;"	d	file:
+SMAC_REG_READ	hci_wrapper/ssv_huw.c	42;"	d	file:
+SMAC_REG_READ	smac/ssv_reg_acc.h	25;"	d
+SMAC_REG_READ_CHECK	smac/init.c	888;"	d	file:
+SMAC_REG_SAFE_READ	smac/ssv_reg_acc.h	35;"	d
+SMAC_REG_SAFE_SET_BITS	smac/ssv_reg_acc.h	108;"	d
+SMAC_REG_SAFE_WRITE	smac/ssv_reg_acc.h	30;"	d
+SMAC_REG_SET_BITS	smac/ssv_reg_acc.h	97;"	d
+SMAC_REG_SET_BITS_CHECK	smac/init.c	904;"	d	file:
+SMAC_REG_WRITE	hci_wrapper/ssv_huw.c	40;"	d	file:
+SMAC_REG_WRITE	smac/ssv_reg_acc.h	18;"	d
+SMAC_REG_WRITE_CHECK	smac/init.c	896;"	d	file:
+SMAC_RF_REG_READ	smac/ssv_reg_acc.h	41;"	d
+SMAC_RF_REG_READ	smac/ssv_reg_acc.h	43;"	d
+SMAC_RF_REG_SET_BITS	smac/ssv_reg_acc.h	120;"	d
+SMAC_RF_REG_SET_BITS	smac/ssv_reg_acc.h	122;"	d
+SMAC_SRAM_WRITE	hci_wrapper/ssv_huw.c	38;"	d	file:
+SMAC_SYSPLF_RESET	smac/ssv_reg_acc.h	80;"	d
+SMS4_BUSY_HI	include/ssv6200_aux.h	6749;"	d
+SMS4_BUSY_I_MSK	include/ssv6200_aux.h	6747;"	d
+SMS4_BUSY_MSK	include/ssv6200_aux.h	6746;"	d
+SMS4_BUSY_SFT	include/ssv6200_aux.h	6748;"	d
+SMS4_BUSY_SZ	include/ssv6200_aux.h	6750;"	d
+SMS4_CBC_EN_HI	include/ssv6200_aux.h	6729;"	d
+SMS4_CBC_EN_I_MSK	include/ssv6200_aux.h	6727;"	d
+SMS4_CBC_EN_MSK	include/ssv6200_aux.h	6726;"	d
+SMS4_CBC_EN_SFT	include/ssv6200_aux.h	6728;"	d
+SMS4_CBC_EN_SZ	include/ssv6200_aux.h	6730;"	d
+SMS4_CFB_EN_HI	include/ssv6200_aux.h	6734;"	d
+SMS4_CFB_EN_I_MSK	include/ssv6200_aux.h	6732;"	d
+SMS4_CFB_EN_MSK	include/ssv6200_aux.h	6731;"	d
+SMS4_CFB_EN_SFT	include/ssv6200_aux.h	6733;"	d
+SMS4_CFB_EN_SZ	include/ssv6200_aux.h	6735;"	d
+SMS4_DATAIN_0_HI	include/ssv6200_aux.h	6759;"	d
+SMS4_DATAIN_0_I_MSK	include/ssv6200_aux.h	6757;"	d
+SMS4_DATAIN_0_MSK	include/ssv6200_aux.h	6756;"	d
+SMS4_DATAIN_0_SFT	include/ssv6200_aux.h	6758;"	d
+SMS4_DATAIN_0_SZ	include/ssv6200_aux.h	6760;"	d
+SMS4_DATAIN_1_HI	include/ssv6200_aux.h	6764;"	d
+SMS4_DATAIN_1_I_MSK	include/ssv6200_aux.h	6762;"	d
+SMS4_DATAIN_1_MSK	include/ssv6200_aux.h	6761;"	d
+SMS4_DATAIN_1_SFT	include/ssv6200_aux.h	6763;"	d
+SMS4_DATAIN_1_SZ	include/ssv6200_aux.h	6765;"	d
+SMS4_DATAIN_2_HI	include/ssv6200_aux.h	6769;"	d
+SMS4_DATAIN_2_I_MSK	include/ssv6200_aux.h	6767;"	d
+SMS4_DATAIN_2_MSK	include/ssv6200_aux.h	6766;"	d
+SMS4_DATAIN_2_SFT	include/ssv6200_aux.h	6768;"	d
+SMS4_DATAIN_2_SZ	include/ssv6200_aux.h	6770;"	d
+SMS4_DATAIN_3_HI	include/ssv6200_aux.h	6774;"	d
+SMS4_DATAIN_3_I_MSK	include/ssv6200_aux.h	6772;"	d
+SMS4_DATAIN_3_MSK	include/ssv6200_aux.h	6771;"	d
+SMS4_DATAIN_3_SFT	include/ssv6200_aux.h	6773;"	d
+SMS4_DATAIN_3_SZ	include/ssv6200_aux.h	6775;"	d
+SMS4_DATAOUT_0_HI	include/ssv6200_aux.h	6779;"	d
+SMS4_DATAOUT_0_I_MSK	include/ssv6200_aux.h	6777;"	d
+SMS4_DATAOUT_0_MSK	include/ssv6200_aux.h	6776;"	d
+SMS4_DATAOUT_0_SFT	include/ssv6200_aux.h	6778;"	d
+SMS4_DATAOUT_0_SZ	include/ssv6200_aux.h	6780;"	d
+SMS4_DATAOUT_1_HI	include/ssv6200_aux.h	6784;"	d
+SMS4_DATAOUT_1_I_MSK	include/ssv6200_aux.h	6782;"	d
+SMS4_DATAOUT_1_MSK	include/ssv6200_aux.h	6781;"	d
+SMS4_DATAOUT_1_SFT	include/ssv6200_aux.h	6783;"	d
+SMS4_DATAOUT_1_SZ	include/ssv6200_aux.h	6785;"	d
+SMS4_DATAOUT_2_HI	include/ssv6200_aux.h	6789;"	d
+SMS4_DATAOUT_2_I_MSK	include/ssv6200_aux.h	6787;"	d
+SMS4_DATAOUT_2_MSK	include/ssv6200_aux.h	6786;"	d
+SMS4_DATAOUT_2_SFT	include/ssv6200_aux.h	6788;"	d
+SMS4_DATAOUT_2_SZ	include/ssv6200_aux.h	6790;"	d
+SMS4_DATAOUT_3_HI	include/ssv6200_aux.h	6794;"	d
+SMS4_DATAOUT_3_I_MSK	include/ssv6200_aux.h	6792;"	d
+SMS4_DATAOUT_3_MSK	include/ssv6200_aux.h	6791;"	d
+SMS4_DATAOUT_3_SFT	include/ssv6200_aux.h	6793;"	d
+SMS4_DATAOUT_3_SZ	include/ssv6200_aux.h	6795;"	d
+SMS4_DESCRY_EN_HI	include/ssv6200_aux.h	6699;"	d
+SMS4_DESCRY_EN_I_MSK	include/ssv6200_aux.h	6697;"	d
+SMS4_DESCRY_EN_MSK	include/ssv6200_aux.h	6696;"	d
+SMS4_DESCRY_EN_SFT	include/ssv6200_aux.h	6698;"	d
+SMS4_DESCRY_EN_SZ	include/ssv6200_aux.h	6700;"	d
+SMS4_DONE_HI	include/ssv6200_aux.h	6754;"	d
+SMS4_DONE_I_MSK	include/ssv6200_aux.h	6752;"	d
+SMS4_DONE_MSK	include/ssv6200_aux.h	6751;"	d
+SMS4_DONE_SFT	include/ssv6200_aux.h	6753;"	d
+SMS4_DONE_SZ	include/ssv6200_aux.h	6755;"	d
+SMS4_KEY_0_HI	include/ssv6200_aux.h	6799;"	d
+SMS4_KEY_0_I_MSK	include/ssv6200_aux.h	6797;"	d
+SMS4_KEY_0_MSK	include/ssv6200_aux.h	6796;"	d
+SMS4_KEY_0_SFT	include/ssv6200_aux.h	6798;"	d
+SMS4_KEY_0_SZ	include/ssv6200_aux.h	6800;"	d
+SMS4_KEY_1_HI	include/ssv6200_aux.h	6804;"	d
+SMS4_KEY_1_I_MSK	include/ssv6200_aux.h	6802;"	d
+SMS4_KEY_1_MSK	include/ssv6200_aux.h	6801;"	d
+SMS4_KEY_1_SFT	include/ssv6200_aux.h	6803;"	d
+SMS4_KEY_1_SZ	include/ssv6200_aux.h	6805;"	d
+SMS4_KEY_2_HI	include/ssv6200_aux.h	6809;"	d
+SMS4_KEY_2_I_MSK	include/ssv6200_aux.h	6807;"	d
+SMS4_KEY_2_MSK	include/ssv6200_aux.h	6806;"	d
+SMS4_KEY_2_SFT	include/ssv6200_aux.h	6808;"	d
+SMS4_KEY_2_SZ	include/ssv6200_aux.h	6810;"	d
+SMS4_KEY_3_HI	include/ssv6200_aux.h	6814;"	d
+SMS4_KEY_3_I_MSK	include/ssv6200_aux.h	6812;"	d
+SMS4_KEY_3_MSK	include/ssv6200_aux.h	6811;"	d
+SMS4_KEY_3_SFT	include/ssv6200_aux.h	6813;"	d
+SMS4_KEY_3_SZ	include/ssv6200_aux.h	6815;"	d
+SMS4_MODE_IV0_HI	include/ssv6200_aux.h	6819;"	d
+SMS4_MODE_IV0_I_MSK	include/ssv6200_aux.h	6817;"	d
+SMS4_MODE_IV0_MSK	include/ssv6200_aux.h	6816;"	d
+SMS4_MODE_IV0_SFT	include/ssv6200_aux.h	6818;"	d
+SMS4_MODE_IV0_SZ	include/ssv6200_aux.h	6820;"	d
+SMS4_MODE_IV1_HI	include/ssv6200_aux.h	6824;"	d
+SMS4_MODE_IV1_I_MSK	include/ssv6200_aux.h	6822;"	d
+SMS4_MODE_IV1_MSK	include/ssv6200_aux.h	6821;"	d
+SMS4_MODE_IV1_SFT	include/ssv6200_aux.h	6823;"	d
+SMS4_MODE_IV1_SZ	include/ssv6200_aux.h	6825;"	d
+SMS4_MODE_IV2_HI	include/ssv6200_aux.h	6829;"	d
+SMS4_MODE_IV2_I_MSK	include/ssv6200_aux.h	6827;"	d
+SMS4_MODE_IV2_MSK	include/ssv6200_aux.h	6826;"	d
+SMS4_MODE_IV2_SFT	include/ssv6200_aux.h	6828;"	d
+SMS4_MODE_IV2_SZ	include/ssv6200_aux.h	6830;"	d
+SMS4_MODE_IV3_HI	include/ssv6200_aux.h	6834;"	d
+SMS4_MODE_IV3_I_MSK	include/ssv6200_aux.h	6832;"	d
+SMS4_MODE_IV3_MSK	include/ssv6200_aux.h	6831;"	d
+SMS4_MODE_IV3_SFT	include/ssv6200_aux.h	6833;"	d
+SMS4_MODE_IV3_SZ	include/ssv6200_aux.h	6835;"	d
+SMS4_OFB_ENC0_HI	include/ssv6200_aux.h	6839;"	d
+SMS4_OFB_ENC0_I_MSK	include/ssv6200_aux.h	6837;"	d
+SMS4_OFB_ENC0_MSK	include/ssv6200_aux.h	6836;"	d
+SMS4_OFB_ENC0_SFT	include/ssv6200_aux.h	6838;"	d
+SMS4_OFB_ENC0_SZ	include/ssv6200_aux.h	6840;"	d
+SMS4_OFB_ENC1_HI	include/ssv6200_aux.h	6844;"	d
+SMS4_OFB_ENC1_I_MSK	include/ssv6200_aux.h	6842;"	d
+SMS4_OFB_ENC1_MSK	include/ssv6200_aux.h	6841;"	d
+SMS4_OFB_ENC1_SFT	include/ssv6200_aux.h	6843;"	d
+SMS4_OFB_ENC1_SZ	include/ssv6200_aux.h	6845;"	d
+SMS4_OFB_ENC2_HI	include/ssv6200_aux.h	6849;"	d
+SMS4_OFB_ENC2_I_MSK	include/ssv6200_aux.h	6847;"	d
+SMS4_OFB_ENC2_MSK	include/ssv6200_aux.h	6846;"	d
+SMS4_OFB_ENC2_SFT	include/ssv6200_aux.h	6848;"	d
+SMS4_OFB_ENC2_SZ	include/ssv6200_aux.h	6850;"	d
+SMS4_OFB_ENC3_HI	include/ssv6200_aux.h	6854;"	d
+SMS4_OFB_ENC3_I_MSK	include/ssv6200_aux.h	6852;"	d
+SMS4_OFB_ENC3_MSK	include/ssv6200_aux.h	6851;"	d
+SMS4_OFB_ENC3_SFT	include/ssv6200_aux.h	6853;"	d
+SMS4_OFB_ENC3_SZ	include/ssv6200_aux.h	6855;"	d
+SMS4_OFB_EN_HI	include/ssv6200_aux.h	6739;"	d
+SMS4_OFB_EN_I_MSK	include/ssv6200_aux.h	6737;"	d
+SMS4_OFB_EN_MSK	include/ssv6200_aux.h	6736;"	d
+SMS4_OFB_EN_SFT	include/ssv6200_aux.h	6738;"	d
+SMS4_OFB_EN_SZ	include/ssv6200_aux.h	6740;"	d
+SMS4_REG_BANK_SIZE	include/ssv6200_reg.h	94;"	d
+SMS4_REG_BASE	include/ssv6200_reg.h	45;"	d
+SMS4_Run	smac/wapi_sms4.c	/^static void SMS4_Run(u32 *Key_Store, u8 *PlainText, u8 *CipherText)$/;"	f	file:	signature:(u32 *Key_Store, u8 *PlainText, u8 *CipherText)
+SMS4_START_TRIG_HI	include/ssv6200_aux.h	6744;"	d
+SMS4_START_TRIG_I_MSK	include/ssv6200_aux.h	6742;"	d
+SMS4_START_TRIG_MSK	include/ssv6200_aux.h	6741;"	d
+SMS4_START_TRIG_SFT	include/ssv6200_aux.h	6743;"	d
+SMS4_START_TRIG_SZ	include/ssv6200_aux.h	6745;"	d
+SNIFFER_MODE_HI	include/ssv6200_aux.h	9144;"	d
+SNIFFER_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8899;"	d
+SNIFFER_MODE_I_MSK	include/ssv6200_aux.h	9142;"	d
+SNIFFER_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8897;"	d
+SNIFFER_MODE_MSK	include/ssv6200_aux.h	9141;"	d
+SNIFFER_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8896;"	d
+SNIFFER_MODE_SFT	include/ssv6200_aux.h	9143;"	d
+SNIFFER_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8898;"	d
+SNIFFER_MODE_SZ	include/ssv6200_aux.h	9145;"	d
+SNIFFER_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8900;"	d
+SOC_EVT_BEACON_LOSS	include/ssv6xxx_common.h	/^    SOC_EVT_BEACON_LOSS = 15,$/;"	e	enum:__anon45
+SOC_EVT_CMD_RESP	include/ssv6xxx_common.h	/^    SOC_EVT_CMD_RESP = 0,$/;"	e	enum:__anon45
+SOC_EVT_DEAUTH	include/ssv6xxx_common.h	/^    SOC_EVT_DEAUTH = 2,$/;"	e	enum:__anon45
+SOC_EVT_GET_REG_RESP	include/ssv6xxx_common.h	/^    SOC_EVT_GET_REG_RESP = 3,$/;"	e	enum:__anon45
+SOC_EVT_LOG	include/ssv6xxx_common.h	/^    SOC_EVT_LOG = 7,$/;"	e	enum:__anon45
+SOC_EVT_MAXID	include/ssv6xxx_common.h	/^    SOC_EVT_MAXID = 18,$/;"	e	enum:__anon45
+SOC_EVT_NOA	include/ssv6xxx_common.h	/^    SOC_EVT_NOA = 8,$/;"	e	enum:__anon45
+SOC_EVT_NO_BA	include/ssv6xxx_common.h	/^    SOC_EVT_NO_BA = 4,$/;"	e	enum:__anon45
+SOC_EVT_RC_AMPDU_REPORT	include/ssv6xxx_common.h	/^    SOC_EVT_RC_AMPDU_REPORT = 6,$/;"	e	enum:__anon45
+SOC_EVT_RC_MPDU_REPORT	include/ssv6xxx_common.h	/^    SOC_EVT_RC_MPDU_REPORT = 5,$/;"	e	enum:__anon45
+SOC_EVT_RESET_HOST	include/ssv6xxx_common.h	/^    SOC_EVT_RESET_HOST = 11,$/;"	e	enum:__anon45
+SOC_EVT_SCAN_RESULT	include/ssv6xxx_common.h	/^    SOC_EVT_SCAN_RESULT = 1,$/;"	e	enum:__anon45
+SOC_EVT_SDIO_TEST_COMMAND	include/ssv6xxx_common.h	/^    SOC_EVT_SDIO_TEST_COMMAND = 10,$/;"	e	enum:__anon45
+SOC_EVT_SDIO_TXTPUT_RESULT	include/ssv6xxx_common.h	/^    SOC_EVT_SDIO_TXTPUT_RESULT = 12,$/;"	e	enum:__anon45
+SOC_EVT_SMART_ICOMM	include/ssv6xxx_common.h	/^    SOC_EVT_SMART_ICOMM = 14,$/;"	e	enum:__anon45
+SOC_EVT_SW_BEACON_RESP	include/ssv6xxx_common.h	/^    SOC_EVT_SW_BEACON_RESP = 17,$/;"	e	enum:__anon45
+SOC_EVT_TXLOOPBK_RESULT	include/ssv6xxx_common.h	/^    SOC_EVT_TXLOOPBK_RESULT = 13,$/;"	e	enum:__anon45
+SOC_EVT_TX_STUCK_RESP	include/ssv6xxx_common.h	/^    SOC_EVT_TX_STUCK_RESP = 16,$/;"	e	enum:__anon45
+SOC_EVT_USER_END	include/ssv6xxx_common.h	/^    SOC_EVT_USER_END = 9,$/;"	e	enum:__anon45
+SOC_SYSTEM_INT_STATUS_HI	include/ssv6200_aux.h	3089;"	d
+SOC_SYSTEM_INT_STATUS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2559;"	d
+SOC_SYSTEM_INT_STATUS_I_MSK	include/ssv6200_aux.h	3087;"	d
+SOC_SYSTEM_INT_STATUS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2557;"	d
+SOC_SYSTEM_INT_STATUS_MSK	include/ssv6200_aux.h	3086;"	d
+SOC_SYSTEM_INT_STATUS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2556;"	d
+SOC_SYSTEM_INT_STATUS_SFT	include/ssv6200_aux.h	3088;"	d
+SOC_SYSTEM_INT_STATUS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2558;"	d
+SOC_SYSTEM_INT_STATUS_SZ	include/ssv6200_aux.h	3090;"	d
+SOC_SYSTEM_INT_STATUS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2560;"	d
+SOC_TRIGGER_RX_INT_HI	include/ssv6200_aux.h	3129;"	d
+SOC_TRIGGER_RX_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2599;"	d
+SOC_TRIGGER_RX_INT_I_MSK	include/ssv6200_aux.h	3127;"	d
+SOC_TRIGGER_RX_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2597;"	d
+SOC_TRIGGER_RX_INT_MSK	include/ssv6200_aux.h	3126;"	d
+SOC_TRIGGER_RX_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2596;"	d
+SOC_TRIGGER_RX_INT_SFT	include/ssv6200_aux.h	3128;"	d
+SOC_TRIGGER_RX_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2598;"	d
+SOC_TRIGGER_RX_INT_SZ	include/ssv6200_aux.h	3130;"	d
+SOC_TRIGGER_RX_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2600;"	d
+SOC_TRIGGER_TX_INT_HI	include/ssv6200_aux.h	3134;"	d
+SOC_TRIGGER_TX_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2604;"	d
+SOC_TRIGGER_TX_INT_I_MSK	include/ssv6200_aux.h	3132;"	d
+SOC_TRIGGER_TX_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2602;"	d
+SOC_TRIGGER_TX_INT_MSK	include/ssv6200_aux.h	3131;"	d
+SOC_TRIGGER_TX_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2601;"	d
+SOC_TRIGGER_TX_INT_SFT	include/ssv6200_aux.h	3133;"	d
+SOC_TRIGGER_TX_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2603;"	d
+SOC_TRIGGER_TX_INT_SZ	include/ssv6200_aux.h	3135;"	d
+SOC_TRIGGER_TX_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2605;"	d
+SPARE_MEM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3059;"	d
+SPARE_MEM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3057;"	d
+SPARE_MEM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3056;"	d
+SPARE_MEM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3058;"	d
+SPARE_MEM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3060;"	d
+SPIMAS_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1284;"	d
+SPIMAS_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1282;"	d
+SPIMAS_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1281;"	d
+SPIMAS_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1283;"	d
+SPIMAS_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1285;"	d
+SPIMAS_RX_BUF_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	113;"	d
+SPIMAS_RX_BUF_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	52;"	d
+SPIMAS_TX_BUF_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	112;"	d
+SPIMAS_TX_BUF_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	51;"	d
+SPIMST_CEN_ENABLE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	864;"	d
+SPIMST_CEN_ENABLE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	862;"	d
+SPIMST_CEN_ENABLE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	861;"	d
+SPIMST_CEN_ENABLE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	863;"	d
+SPIMST_CEN_ENABLE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	865;"	d
+SPIMST_CPHA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	839;"	d
+SPIMST_CPHA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	837;"	d
+SPIMST_CPHA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	836;"	d
+SPIMST_CPHA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	838;"	d
+SPIMST_CPHA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	840;"	d
+SPIMST_CPOL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	844;"	d
+SPIMST_CPOL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	842;"	d
+SPIMST_CPOL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	841;"	d
+SPIMST_CPOL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	843;"	d
+SPIMST_CPOL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	845;"	d
+SPIMST_DATA_LEN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	834;"	d
+SPIMST_DATA_LEN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	832;"	d
+SPIMST_DATA_LEN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	831;"	d
+SPIMST_DATA_LEN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	833;"	d
+SPIMST_DATA_LEN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	835;"	d
+SPIMST_ENABLE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	859;"	d
+SPIMST_ENABLE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	857;"	d
+SPIMST_ENABLE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	856;"	d
+SPIMST_ENABLE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	858;"	d
+SPIMST_ENABLE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	860;"	d
+SPIMST_REG_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	81;"	d
+SPIMST_REG_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	20;"	d
+SPIMST_RXFIFO_TH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	879;"	d
+SPIMST_RXFIFO_TH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	877;"	d
+SPIMST_RXFIFO_TH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	876;"	d
+SPIMST_RXFIFO_TH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	878;"	d
+SPIMST_RXFIFO_TH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	880;"	d
+SPIMST_RXF_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	959;"	d
+SPIMST_RXF_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	957;"	d
+SPIMST_RXF_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	956;"	d
+SPIMST_RXF_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	958;"	d
+SPIMST_RXF_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	960;"	d
+SPIMST_RXF_INT_UNMASK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	934;"	d
+SPIMST_RXF_INT_UNMASK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	932;"	d
+SPIMST_RXF_INT_UNMASK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	931;"	d
+SPIMST_RXF_INT_UNMASK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	933;"	d
+SPIMST_RXF_INT_UNMASK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	935;"	d
+SPIMST_RXO_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	954;"	d
+SPIMST_RXO_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	952;"	d
+SPIMST_RXO_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	951;"	d
+SPIMST_RXO_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	953;"	d
+SPIMST_RXO_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	955;"	d
+SPIMST_RXO_INT_UNMASK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	929;"	d
+SPIMST_RXO_INT_UNMASK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	927;"	d
+SPIMST_RXO_INT_UNMASK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	926;"	d
+SPIMST_RXO_INT_UNMASK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	928;"	d
+SPIMST_RXO_INT_UNMASK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	930;"	d
+SPIMST_RXU_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	949;"	d
+SPIMST_RXU_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	947;"	d
+SPIMST_RXU_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	946;"	d
+SPIMST_RXU_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	948;"	d
+SPIMST_RXU_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	950;"	d
+SPIMST_RXU_INT_UNMASK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	924;"	d
+SPIMST_RXU_INT_UNMASK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	922;"	d
+SPIMST_RXU_INT_UNMASK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	921;"	d
+SPIMST_RXU_INT_UNMASK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	923;"	d
+SPIMST_RXU_INT_UNMASK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	925;"	d
+SPIMST_RX_SAMPLE_DLY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	969;"	d
+SPIMST_RX_SAMPLE_DLY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	967;"	d
+SPIMST_RX_SAMPLE_DLY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	966;"	d
+SPIMST_RX_SAMPLE_DLY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	968;"	d
+SPIMST_RX_SAMPLE_DLY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	970;"	d
+SPIMST_SCLK_RATE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	869;"	d
+SPIMST_SCLK_RATE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	867;"	d
+SPIMST_SCLK_RATE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	866;"	d
+SPIMST_SCLK_RATE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	868;"	d
+SPIMST_SCLK_RATE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	870;"	d
+SPIMST_TRX_DATA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	964;"	d
+SPIMST_TRX_DATA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	962;"	d
+SPIMST_TRX_DATA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	961;"	d
+SPIMST_TRX_DATA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	963;"	d
+SPIMST_TRX_DATA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	965;"	d
+SPIMST_TXE_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	939;"	d
+SPIMST_TXE_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	937;"	d
+SPIMST_TXE_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	936;"	d
+SPIMST_TXE_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	938;"	d
+SPIMST_TXE_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	940;"	d
+SPIMST_TXE_INT_UNMASK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	914;"	d
+SPIMST_TXE_INT_UNMASK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	912;"	d
+SPIMST_TXE_INT_UNMASK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	911;"	d
+SPIMST_TXE_INT_UNMASK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	913;"	d
+SPIMST_TXE_INT_UNMASK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	915;"	d
+SPIMST_TXFIFO_TH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	874;"	d
+SPIMST_TXFIFO_TH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	872;"	d
+SPIMST_TXFIFO_TH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	871;"	d
+SPIMST_TXFIFO_TH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	873;"	d
+SPIMST_TXFIFO_TH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	875;"	d
+SPIMST_TXO_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	944;"	d
+SPIMST_TXO_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	942;"	d
+SPIMST_TXO_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	941;"	d
+SPIMST_TXO_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	943;"	d
+SPIMST_TXO_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	945;"	d
+SPIMST_TXO_INT_UNMASK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	919;"	d
+SPIMST_TXO_INT_UNMASK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	917;"	d
+SPIMST_TXO_INT_UNMASK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	916;"	d
+SPIMST_TXO_INT_UNMASK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	918;"	d
+SPIMST_TXO_INT_UNMASK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	920;"	d
+SPI_ALLOC_STATUS_HI	include/ssv6200_aux.h	4009;"	d
+SPI_ALLOC_STATUS_I_MSK	include/ssv6200_aux.h	4007;"	d
+SPI_ALLOC_STATUS_MSK	include/ssv6200_aux.h	4006;"	d
+SPI_ALLOC_STATUS_SFT	include/ssv6200_aux.h	4008;"	d
+SPI_ALLOC_STATUS_SZ	include/ssv6200_aux.h	4010;"	d
+SPI_BUSY_HI	include/ssv6200_aux.h	5719;"	d
+SPI_BUSY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4044;"	d
+SPI_BUSY_I_MSK	include/ssv6200_aux.h	5717;"	d
+SPI_BUSY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4042;"	d
+SPI_BUSY_MSK	include/ssv6200_aux.h	5716;"	d
+SPI_BUSY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4041;"	d
+SPI_BUSY_SFT	include/ssv6200_aux.h	5718;"	d
+SPI_BUSY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4043;"	d
+SPI_BUSY_SZ	include/ssv6200_aux.h	5720;"	d
+SPI_BUSY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4045;"	d
+SPI_CLK_DIV_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5964;"	d
+SPI_CLK_DIV_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5962;"	d
+SPI_CLK_DIV_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5961;"	d
+SPI_CLK_DIV_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5963;"	d
+SPI_CLK_DIV_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5965;"	d
+SPI_CLK_EN_INT_HI	include/ssv6200_aux.h	4154;"	d
+SPI_CLK_EN_INT_I_MSK	include/ssv6200_aux.h	4152;"	d
+SPI_CLK_EN_INT_MSK	include/ssv6200_aux.h	4151;"	d
+SPI_CLK_EN_INT_SFT	include/ssv6200_aux.h	4153;"	d
+SPI_CLK_EN_INT_SZ	include/ssv6200_aux.h	4155;"	d
+SPI_CLR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5974;"	d
+SPI_CLR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5972;"	d
+SPI_CLR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5971;"	d
+SPI_CLR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5973;"	d
+SPI_CLR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5975;"	d
+SPI_CSN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6024;"	d
+SPI_CSN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6022;"	d
+SPI_CSN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6021;"	d
+SPI_CSN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6023;"	d
+SPI_CSN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6025;"	d
+SPI_DBG_WR_FIFO_FULL_HI	include/ssv6200_aux.h	4014;"	d
+SPI_DBG_WR_FIFO_FULL_I_MSK	include/ssv6200_aux.h	4012;"	d
+SPI_DBG_WR_FIFO_FULL_MSK	include/ssv6200_aux.h	4011;"	d
+SPI_DBG_WR_FIFO_FULL_SFT	include/ssv6200_aux.h	4013;"	d
+SPI_DBG_WR_FIFO_FULL_SZ	include/ssv6200_aux.h	4015;"	d
+SPI_DI_SEL_HI	include/ssv6200_aux.h	3029;"	d
+SPI_DI_SEL_I_MSK	include/ssv6200_aux.h	3027;"	d
+SPI_DI_SEL_MSK	include/ssv6200_aux.h	3026;"	d
+SPI_DI_SEL_SFT	include/ssv6200_aux.h	3028;"	d
+SPI_DI_SEL_SZ	include/ssv6200_aux.h	3030;"	d
+SPI_DOUBLE_ALLOC_HI	include/ssv6200_aux.h	3994;"	d
+SPI_DOUBLE_ALLOC_I_MSK	include/ssv6200_aux.h	3992;"	d
+SPI_DOUBLE_ALLOC_MSK	include/ssv6200_aux.h	3991;"	d
+SPI_DOUBLE_ALLOC_SFT	include/ssv6200_aux.h	3993;"	d
+SPI_DOUBLE_ALLOC_SZ	include/ssv6200_aux.h	3995;"	d
+SPI_FLASH_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4049;"	d
+SPI_FLASH_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4047;"	d
+SPI_FLASH_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4046;"	d
+SPI_FLASH_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4048;"	d
+SPI_FLASH_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4050;"	d
+SPI_FN1_HI	include/ssv6200_aux.h	4149;"	d
+SPI_FN1_I_MSK	include/ssv6200_aux.h	4147;"	d
+SPI_FN1_MSK	include/ssv6200_aux.h	4146;"	d
+SPI_FN1_SFT	include/ssv6200_aux.h	4148;"	d
+SPI_FN1_SZ	include/ssv6200_aux.h	4150;"	d
+SPI_F_MISO_CLK_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4159;"	d
+SPI_F_MISO_CLK_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4157;"	d
+SPI_F_MISO_CLK_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4156;"	d
+SPI_F_MISO_CLK_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4158;"	d
+SPI_F_MISO_CLK_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4160;"	d
+SPI_HOST_MASK_HI	include/ssv6200_aux.h	4159;"	d
+SPI_HOST_MASK_I_MSK	include/ssv6200_aux.h	4157;"	d
+SPI_HOST_MASK_MSK	include/ssv6200_aux.h	4156;"	d
+SPI_HOST_MASK_SFT	include/ssv6200_aux.h	4158;"	d
+SPI_HOST_MASK_SZ	include/ssv6200_aux.h	4160;"	d
+SPI_HOST_TX_ALLOC_PKBUF_HI	include/ssv6200_aux.h	4029;"	d
+SPI_HOST_TX_ALLOC_PKBUF_I_MSK	include/ssv6200_aux.h	4027;"	d
+SPI_HOST_TX_ALLOC_PKBUF_MSK	include/ssv6200_aux.h	4026;"	d
+SPI_HOST_TX_ALLOC_PKBUF_SFT	include/ssv6200_aux.h	4028;"	d
+SPI_HOST_TX_ALLOC_PKBUF_SZ	include/ssv6200_aux.h	4030;"	d
+SPI_IPC_ADDR_HI	include/ssv6200_aux.h	5089;"	d
+SPI_IPC_ADDR_I_MSK	include/ssv6200_aux.h	5087;"	d
+SPI_IPC_ADDR_MSK	include/ssv6200_aux.h	5086;"	d
+SPI_IPC_ADDR_SFT	include/ssv6200_aux.h	5088;"	d
+SPI_IPC_ADDR_SZ	include/ssv6200_aux.h	5090;"	d
+SPI_MASTER_BUSY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5969;"	d
+SPI_MASTER_BUSY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5967;"	d
+SPI_MASTER_BUSY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5966;"	d
+SPI_MASTER_BUSY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5968;"	d
+SPI_MASTER_BUSY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5970;"	d
+SPI_MODE_HI	include/ssv6200_aux.h	3924;"	d
+SPI_MODE_I_MSK	include/ssv6200_aux.h	3922;"	d
+SPI_MODE_MSK	include/ssv6200_aux.h	3921;"	d
+SPI_MODE_SFT	include/ssv6200_aux.h	3923;"	d
+SPI_MODE_SZ	include/ssv6200_aux.h	3925;"	d
+SPI_MST2CBRA_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1239;"	d
+SPI_MST2CBRA_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1237;"	d
+SPI_MST2CBRA_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1236;"	d
+SPI_MST2CBRA_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1238;"	d
+SPI_MST2CBRA_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1240;"	d
+SPI_M_BACK_DLY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5959;"	d
+SPI_M_BACK_DLY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5957;"	d
+SPI_M_BACK_DLY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5956;"	d
+SPI_M_BACK_DLY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5958;"	d
+SPI_M_BACK_DLY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5960;"	d
+SPI_M_FRONT_DLY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5954;"	d
+SPI_M_FRONT_DLY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5952;"	d
+SPI_M_FRONT_DLY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5951;"	d
+SPI_M_FRONT_DLY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5953;"	d
+SPI_M_FRONT_DLY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5955;"	d
+SPI_RAW_DATA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2434;"	d
+SPI_RAW_DATA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2432;"	d
+SPI_RAW_DATA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2431;"	d
+SPI_RAW_DATA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2433;"	d
+SPI_RAW_DATA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2435;"	d
+SPI_REG_BANK_SIZE	include/ssv6200_reg.h	79;"	d
+SPI_REG_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	98;"	d
+SPI_REG_BASE	include/ssv6200_reg.h	30;"	d
+SPI_REG_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	37;"	d
+SPI_SLV_CLK_EN_HI	include/ssv6200_aux.h	209;"	d
+SPI_SLV_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1159;"	d
+SPI_SLV_CLK_EN_I_MSK	include/ssv6200_aux.h	207;"	d
+SPI_SLV_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1157;"	d
+SPI_SLV_CLK_EN_MSK	include/ssv6200_aux.h	206;"	d
+SPI_SLV_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1156;"	d
+SPI_SLV_CLK_EN_SFT	include/ssv6200_aux.h	208;"	d
+SPI_SLV_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1158;"	d
+SPI_SLV_CLK_EN_SZ	include/ssv6200_aux.h	210;"	d
+SPI_SLV_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1160;"	d
+SPI_SLV_SW_RST_HI	include/ssv6200_aux.h	39;"	d
+SPI_SLV_SW_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	994;"	d
+SPI_SLV_SW_RST_I_MSK	include/ssv6200_aux.h	37;"	d
+SPI_SLV_SW_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	992;"	d
+SPI_SLV_SW_RST_MSK	include/ssv6200_aux.h	36;"	d
+SPI_SLV_SW_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	991;"	d
+SPI_SLV_SW_RST_SFT	include/ssv6200_aux.h	38;"	d
+SPI_SLV_SW_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	993;"	d
+SPI_SLV_SW_RST_SZ	include/ssv6200_aux.h	40;"	d
+SPI_SLV_SW_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	995;"	d
+SPI_TX_ALLOC_SIZE_HI	include/ssv6200_aux.h	4034;"	d
+SPI_TX_ALLOC_SIZE_I_MSK	include/ssv6200_aux.h	4032;"	d
+SPI_TX_ALLOC_SIZE_MSK	include/ssv6200_aux.h	4031;"	d
+SPI_TX_ALLOC_SIZE_SFT	include/ssv6200_aux.h	4033;"	d
+SPI_TX_ALLOC_SIZE_SHIFT_BITS_HI	include/ssv6200_aux.h	4024;"	d
+SPI_TX_ALLOC_SIZE_SHIFT_BITS_I_MSK	include/ssv6200_aux.h	4022;"	d
+SPI_TX_ALLOC_SIZE_SHIFT_BITS_MSK	include/ssv6200_aux.h	4021;"	d
+SPI_TX_ALLOC_SIZE_SHIFT_BITS_SFT	include/ssv6200_aux.h	4023;"	d
+SPI_TX_ALLOC_SIZE_SHIFT_BITS_SZ	include/ssv6200_aux.h	4025;"	d
+SPI_TX_ALLOC_SIZE_SZ	include/ssv6200_aux.h	4035;"	d
+SPI_TX_NO_ALLOC_HI	include/ssv6200_aux.h	3999;"	d
+SPI_TX_NO_ALLOC_I_MSK	include/ssv6200_aux.h	3997;"	d
+SPI_TX_NO_ALLOC_MSK	include/ssv6200_aux.h	3996;"	d
+SPI_TX_NO_ALLOC_SFT	include/ssv6200_aux.h	3998;"	d
+SPI_TX_NO_ALLOC_SZ	include/ssv6200_aux.h	4000;"	d
+SRAM_ACCESS_MD_HI	include/ssv6200_aux.h	17684;"	d
+SRAM_ACCESS_MD_I_MSK	include/ssv6200_aux.h	17682;"	d
+SRAM_ACCESS_MD_MSK	include/ssv6200_aux.h	17681;"	d
+SRAM_ACCESS_MD_SFT	include/ssv6200_aux.h	17683;"	d
+SRAM_ACCESS_MD_SZ	include/ssv6200_aux.h	17685;"	d
+SRAM_ADDR_HI	include/ssv6200_aux.h	5694;"	d
+SRAM_ADDR_I_MSK	include/ssv6200_aux.h	5692;"	d
+SRAM_ADDR_MSK	include/ssv6200_aux.h	5691;"	d
+SRAM_ADDR_SFT	include/ssv6200_aux.h	5693;"	d
+SRAM_ADDR_SZ	include/ssv6200_aux.h	5695;"	d
+SRAM_MODE_ILM_160K_DLM_32K	include/ssv6xxx_common.h	/^    SRAM_MODE_ILM_160K_DLM_32K,$/;"	e	enum:SSV_SRAM_MODE
+SRAM_MODE_ILM_64K_DLM_128K	include/ssv6xxx_common.h	/^    SRAM_MODE_ILM_64K_DLM_128K = 0,$/;"	e	enum:SSV_SRAM_MODE
+SRAM_TAG_0_HI	include/ssv6200_aux.h	18144;"	d
+SRAM_TAG_0_I_MSK	include/ssv6200_aux.h	18142;"	d
+SRAM_TAG_0_MSK	include/ssv6200_aux.h	18141;"	d
+SRAM_TAG_0_SFT	include/ssv6200_aux.h	18143;"	d
+SRAM_TAG_0_SZ	include/ssv6200_aux.h	18145;"	d
+SRAM_TAG_10_HI	include/ssv6200_aux.h	18194;"	d
+SRAM_TAG_10_I_MSK	include/ssv6200_aux.h	18192;"	d
+SRAM_TAG_10_MSK	include/ssv6200_aux.h	18191;"	d
+SRAM_TAG_10_SFT	include/ssv6200_aux.h	18193;"	d
+SRAM_TAG_10_SZ	include/ssv6200_aux.h	18195;"	d
+SRAM_TAG_11_HI	include/ssv6200_aux.h	18199;"	d
+SRAM_TAG_11_I_MSK	include/ssv6200_aux.h	18197;"	d
+SRAM_TAG_11_MSK	include/ssv6200_aux.h	18196;"	d
+SRAM_TAG_11_SFT	include/ssv6200_aux.h	18198;"	d
+SRAM_TAG_11_SZ	include/ssv6200_aux.h	18200;"	d
+SRAM_TAG_12_HI	include/ssv6200_aux.h	18204;"	d
+SRAM_TAG_12_I_MSK	include/ssv6200_aux.h	18202;"	d
+SRAM_TAG_12_MSK	include/ssv6200_aux.h	18201;"	d
+SRAM_TAG_12_SFT	include/ssv6200_aux.h	18203;"	d
+SRAM_TAG_12_SZ	include/ssv6200_aux.h	18205;"	d
+SRAM_TAG_13_HI	include/ssv6200_aux.h	18209;"	d
+SRAM_TAG_13_I_MSK	include/ssv6200_aux.h	18207;"	d
+SRAM_TAG_13_MSK	include/ssv6200_aux.h	18206;"	d
+SRAM_TAG_13_SFT	include/ssv6200_aux.h	18208;"	d
+SRAM_TAG_13_SZ	include/ssv6200_aux.h	18210;"	d
+SRAM_TAG_14_HI	include/ssv6200_aux.h	18214;"	d
+SRAM_TAG_14_I_MSK	include/ssv6200_aux.h	18212;"	d
+SRAM_TAG_14_MSK	include/ssv6200_aux.h	18211;"	d
+SRAM_TAG_14_SFT	include/ssv6200_aux.h	18213;"	d
+SRAM_TAG_14_SZ	include/ssv6200_aux.h	18215;"	d
+SRAM_TAG_15_HI	include/ssv6200_aux.h	18219;"	d
+SRAM_TAG_15_I_MSK	include/ssv6200_aux.h	18217;"	d
+SRAM_TAG_15_MSK	include/ssv6200_aux.h	18216;"	d
+SRAM_TAG_15_SFT	include/ssv6200_aux.h	18218;"	d
+SRAM_TAG_15_SZ	include/ssv6200_aux.h	18220;"	d
+SRAM_TAG_1_HI	include/ssv6200_aux.h	18149;"	d
+SRAM_TAG_1_I_MSK	include/ssv6200_aux.h	18147;"	d
+SRAM_TAG_1_MSK	include/ssv6200_aux.h	18146;"	d
+SRAM_TAG_1_SFT	include/ssv6200_aux.h	18148;"	d
+SRAM_TAG_1_SZ	include/ssv6200_aux.h	18150;"	d
+SRAM_TAG_2_HI	include/ssv6200_aux.h	18154;"	d
+SRAM_TAG_2_I_MSK	include/ssv6200_aux.h	18152;"	d
+SRAM_TAG_2_MSK	include/ssv6200_aux.h	18151;"	d
+SRAM_TAG_2_SFT	include/ssv6200_aux.h	18153;"	d
+SRAM_TAG_2_SZ	include/ssv6200_aux.h	18155;"	d
+SRAM_TAG_3_HI	include/ssv6200_aux.h	18159;"	d
+SRAM_TAG_3_I_MSK	include/ssv6200_aux.h	18157;"	d
+SRAM_TAG_3_MSK	include/ssv6200_aux.h	18156;"	d
+SRAM_TAG_3_SFT	include/ssv6200_aux.h	18158;"	d
+SRAM_TAG_3_SZ	include/ssv6200_aux.h	18160;"	d
+SRAM_TAG_4_HI	include/ssv6200_aux.h	18164;"	d
+SRAM_TAG_4_I_MSK	include/ssv6200_aux.h	18162;"	d
+SRAM_TAG_4_MSK	include/ssv6200_aux.h	18161;"	d
+SRAM_TAG_4_SFT	include/ssv6200_aux.h	18163;"	d
+SRAM_TAG_4_SZ	include/ssv6200_aux.h	18165;"	d
+SRAM_TAG_5_HI	include/ssv6200_aux.h	18169;"	d
+SRAM_TAG_5_I_MSK	include/ssv6200_aux.h	18167;"	d
+SRAM_TAG_5_MSK	include/ssv6200_aux.h	18166;"	d
+SRAM_TAG_5_SFT	include/ssv6200_aux.h	18168;"	d
+SRAM_TAG_5_SZ	include/ssv6200_aux.h	18170;"	d
+SRAM_TAG_6_HI	include/ssv6200_aux.h	18174;"	d
+SRAM_TAG_6_I_MSK	include/ssv6200_aux.h	18172;"	d
+SRAM_TAG_6_MSK	include/ssv6200_aux.h	18171;"	d
+SRAM_TAG_6_SFT	include/ssv6200_aux.h	18173;"	d
+SRAM_TAG_6_SZ	include/ssv6200_aux.h	18175;"	d
+SRAM_TAG_7_HI	include/ssv6200_aux.h	18179;"	d
+SRAM_TAG_7_I_MSK	include/ssv6200_aux.h	18177;"	d
+SRAM_TAG_7_MSK	include/ssv6200_aux.h	18176;"	d
+SRAM_TAG_7_SFT	include/ssv6200_aux.h	18178;"	d
+SRAM_TAG_7_SZ	include/ssv6200_aux.h	18180;"	d
+SRAM_TAG_8_HI	include/ssv6200_aux.h	18184;"	d
+SRAM_TAG_8_I_MSK	include/ssv6200_aux.h	18182;"	d
+SRAM_TAG_8_MSK	include/ssv6200_aux.h	18181;"	d
+SRAM_TAG_8_SFT	include/ssv6200_aux.h	18183;"	d
+SRAM_TAG_8_SZ	include/ssv6200_aux.h	18185;"	d
+SRAM_TAG_9_HI	include/ssv6200_aux.h	18189;"	d
+SRAM_TAG_9_I_MSK	include/ssv6200_aux.h	18187;"	d
+SRAM_TAG_9_MSK	include/ssv6200_aux.h	18186;"	d
+SRAM_TAG_9_SFT	include/ssv6200_aux.h	18188;"	d
+SRAM_TAG_9_SZ	include/ssv6200_aux.h	18190;"	d
+SSC_CMD_STATE_IDLE	smac/p2p.h	/^    SSC_CMD_STATE_IDLE,$/;"	e	enum:ssv_cmd_state
+SSC_CMD_STATE_WAIT_RSP	smac/p2p.h	/^    SSC_CMD_STATE_WAIT_RSP,$/;"	e	enum:ssv_cmd_state
+SSV6006	include/ssv6xxx_common.h	315;"	d
+SSV6006MP	include/ssv6xxx_common.h	316;"	d
+SSV6006RC_20_40_MSK	smac/hal/ssv6006c/ssv6006_mac.h	48;"	d
+SSV6006RC_20_40_SFT	smac/hal/ssv6006c/ssv6006_mac.h	49;"	d
+SSV6006RC_B_11M	smac/hal/ssv6006c/ssv6006_mac.h	66;"	d
+SSV6006RC_B_1M	smac/hal/ssv6006c/ssv6006_mac.h	63;"	d
+SSV6006RC_B_2M	smac/hal/ssv6006c/ssv6006_mac.h	64;"	d
+SSV6006RC_B_5_5M	smac/hal/ssv6006c/ssv6006_mac.h	65;"	d
+SSV6006RC_B_MAX_RATE	smac/hal/ssv6006c/ssv6006_mac.h	67;"	d
+SSV6006RC_B_MODE	smac/hal/ssv6006c/ssv6006_mac.h	45;"	d
+SSV6006RC_B_RATE_MSK	smac/hal/ssv6006c/ssv6006_mac.h	60;"	d
+SSV6006RC_GREEN	smac/hal/ssv6006c/ssv6006_mac.h	59;"	d
+SSV6006RC_G_12M	smac/hal/ssv6006c/ssv6006_mac.h	71;"	d
+SSV6006RC_G_18M	smac/hal/ssv6006c/ssv6006_mac.h	72;"	d
+SSV6006RC_G_24M	smac/hal/ssv6006c/ssv6006_mac.h	73;"	d
+SSV6006RC_G_36M	smac/hal/ssv6006c/ssv6006_mac.h	74;"	d
+SSV6006RC_G_48M	smac/hal/ssv6006c/ssv6006_mac.h	75;"	d
+SSV6006RC_G_54M	smac/hal/ssv6006c/ssv6006_mac.h	76;"	d
+SSV6006RC_G_6M	smac/hal/ssv6006c/ssv6006_mac.h	69;"	d
+SSV6006RC_G_9M	smac/hal/ssv6006c/ssv6006_mac.h	70;"	d
+SSV6006RC_G_MODE	smac/hal/ssv6006c/ssv6006_mac.h	46;"	d
+SSV6006RC_HT20	smac/hal/ssv6006c/ssv6006_mac.h	50;"	d
+SSV6006RC_HT40	smac/hal/ssv6006c/ssv6006_mac.h	51;"	d
+SSV6006RC_LONG	smac/hal/ssv6006c/ssv6006_mac.h	54;"	d
+SSV6006RC_LONG_SHORT_MSK	smac/hal/ssv6006c/ssv6006_mac.h	52;"	d
+SSV6006RC_LONG_SHORT_SFT	smac/hal/ssv6006c/ssv6006_mac.h	53;"	d
+SSV6006RC_MAX_RATE	smac/hal/ssv6006c/ssv6006_mac.h	85;"	d
+SSV6006RC_MAX_RATE_RETRY	smac/hal/ssv6006c/ssv6006_mac.h	41;"	d
+SSV6006RC_MAX_RATE_SERIES	smac/hal/ssv6006c/ssv6006_mac.h	42;"	d
+SSV6006RC_MF_MSK	smac/hal/ssv6006c/ssv6006_mac.h	56;"	d
+SSV6006RC_MF_SFT	smac/hal/ssv6006c/ssv6006_mac.h	57;"	d
+SSV6006RC_MIX	smac/hal/ssv6006c/ssv6006_mac.h	58;"	d
+SSV6006RC_N_MCS0	smac/hal/ssv6006c/ssv6006_mac.h	77;"	d
+SSV6006RC_N_MCS1	smac/hal/ssv6006c/ssv6006_mac.h	78;"	d
+SSV6006RC_N_MCS2	smac/hal/ssv6006c/ssv6006_mac.h	79;"	d
+SSV6006RC_N_MCS3	smac/hal/ssv6006c/ssv6006_mac.h	80;"	d
+SSV6006RC_N_MCS4	smac/hal/ssv6006c/ssv6006_mac.h	81;"	d
+SSV6006RC_N_MCS5	smac/hal/ssv6006c/ssv6006_mac.h	82;"	d
+SSV6006RC_N_MCS6	smac/hal/ssv6006c/ssv6006_mac.h	83;"	d
+SSV6006RC_N_MCS7	smac/hal/ssv6006c/ssv6006_mac.h	84;"	d
+SSV6006RC_N_MODE	smac/hal/ssv6006c/ssv6006_mac.h	47;"	d
+SSV6006RC_PHY_MODE_MSK	smac/hal/ssv6006c/ssv6006_mac.h	43;"	d
+SSV6006RC_PHY_MODE_SFT	smac/hal/ssv6006c/ssv6006_mac.h	44;"	d
+SSV6006RC_RATE_MSK	smac/hal/ssv6006c/ssv6006_mac.h	61;"	d
+SSV6006RC_RATE_SFT	smac/hal/ssv6006c/ssv6006_mac.h	62;"	d
+SSV6006RC_SHORT	smac/hal/ssv6006c/ssv6006_mac.h	55;"	d
+SSV6006_ALLOC_RSVD	smac/hal/ssv6006c/ssv6006_cfg.h	75;"	d
+SSV6006_AMPDU_DIVIDER	smac/hal/ssv6006c/ssv6006_cfg.h	46;"	d
+SSV6006_BT_PRI_SMP_TIME	smac/hal/ssv6006c/ssv6006_cfg.h	76;"	d
+SSV6006_BT_STA_SMP_TIME	smac/hal/ssv6006c/ssv6006_cfg.h	77;"	d
+SSV6006_CMD_LPBK_SEC_AES	smac/hal/ssv6006c/ssv6006_mac.h	/^    SSV6006_CMD_LPBK_SEC_AES,$/;"	e	enum:ssv6006_lpbk_sec
+SSV6006_CMD_LPBK_SEC_AUTO	smac/hal/ssv6006c/ssv6006_mac.h	/^    SSV6006_CMD_LPBK_SEC_AUTO = 0,$/;"	e	enum:ssv6006_lpbk_sec
+SSV6006_CMD_LPBK_SEC_OPEN	smac/hal/ssv6006c/ssv6006_mac.h	/^    SSV6006_CMD_LPBK_SEC_OPEN,$/;"	e	enum:ssv6006_lpbk_sec
+SSV6006_CMD_LPBK_SEC_TKIP	smac/hal/ssv6006c/ssv6006_mac.h	/^    SSV6006_CMD_LPBK_SEC_TKIP,$/;"	e	enum:ssv6006_lpbk_sec
+SSV6006_CMD_LPBK_SEC_WEP128	smac/hal/ssv6006c/ssv6006_mac.h	/^    SSV6006_CMD_LPBK_SEC_WEP128,$/;"	e	enum:ssv6006_lpbk_sec
+SSV6006_CMD_LPBK_SEC_WEP64	smac/hal/ssv6006c/ssv6006_mac.h	/^    SSV6006_CMD_LPBK_SEC_WEP64,$/;"	e	enum:ssv6006_lpbk_sec
+SSV6006_CMD_LPBK_TYPE_2GRF	smac/hal/ssv6006c/ssv6006_mac.h	/^    SSV6006_CMD_LPBK_TYPE_2GRF,$/;"	e	enum:ssv6006_lpbk_type
+SSV6006_CMD_LPBK_TYPE_5GRF	smac/hal/ssv6006c/ssv6006_mac.h	/^    SSV6006_CMD_LPBK_TYPE_5GRF,$/;"	e	enum:ssv6006_lpbk_type
+SSV6006_CMD_LPBK_TYPE_HCI	smac/hal/ssv6006c/ssv6006_mac.h	/^    SSV6006_CMD_LPBK_TYPE_HCI,$/;"	e	enum:ssv6006_lpbk_type
+SSV6006_CMD_LPBK_TYPE_MAC	smac/hal/ssv6006c/ssv6006_mac.h	/^    SSV6006_CMD_LPBK_TYPE_MAC,$/;"	e	enum:ssv6006_lpbk_type
+SSV6006_CMD_LPBK_TYPE_PHY	smac/hal/ssv6006c/ssv6006_mac.h	/^    SSV6006_CMD_LPBK_TYPE_PHY = 0,$/;"	e	enum:ssv6006_lpbk_type
+SSV6006_EDCCA_AVG_T_102US	smac/hal/ssv6006c/ssv6006_mac.h	90;"	d
+SSV6006_EDCCA_AVG_T_12US	smac/hal/ssv6006c/ssv6006_mac.h	87;"	d
+SSV6006_EDCCA_AVG_T_204US	smac/hal/ssv6006c/ssv6006_mac.h	91;"	d
+SSV6006_EDCCA_AVG_T_25US	smac/hal/ssv6006c/ssv6006_mac.h	88;"	d
+SSV6006_EDCCA_AVG_T_409US	smac/hal/ssv6006c/ssv6006_mac.h	92;"	d
+SSV6006_EDCCA_AVG_T_51US	smac/hal/ssv6006c/ssv6006_mac.h	89;"	d
+SSV6006_EDCCA_AVG_T_6US	smac/hal/ssv6006c/ssv6006_mac.h	86;"	d
+SSV6006_EDCCA_AVG_T_819US	smac/hal/ssv6006c/ssv6006_mac.h	93;"	d
+SSV6006_GROUP_KEY_OFFSET	smac/hal/ssv6006c/ssv6006_mac.h	116;"	d
+SSV6006_HW_KEY_SIZE	smac/hal/ssv6006c/ssv6006_mac.h	114;"	d
+SSV6006_HW_SEC_TABLE_SIZE	smac/hal/ssv6006c/ssv6006_mac.h	113;"	d
+SSV6006_ID_AC_BE_OUT_QUEUE	smac/hal/ssv6006c/ssv6006_cfg.h	67;"	d
+SSV6006_ID_AC_BK_OUT_QUEUE	smac/hal/ssv6006c/ssv6006_cfg.h	66;"	d
+SSV6006_ID_AC_RESERVED	smac/hal/ssv6006c/ssv6006_cfg.h	65;"	d
+SSV6006_ID_AC_VI_OUT_QUEUE	smac/hal/ssv6006c/ssv6006_cfg.h	68;"	d
+SSV6006_ID_AC_VO_OUT_QUEUE	smac/hal/ssv6006c/ssv6006_cfg.h	69;"	d
+SSV6006_ID_MANAGER_QUEUE	smac/hal/ssv6006c/ssv6006_cfg.h	70;"	d
+SSV6006_ID_NUMBER	smac/hal/ssv6006c/ssv6006_cfg.h	63;"	d
+SSV6006_ID_RX_THRESHOLD	smac/hal/ssv6006c/ssv6006_cfg.h	38;"	d
+SSV6006_ID_RX_THRESHOLD	smac/hal/ssv6006c/ssv6006_cfg.h	51;"	d
+SSV6006_ID_RX_THRESHOLD	smac/hal/ssv6006c/ssv6006_cfg.h	57;"	d
+SSV6006_ID_SEC	smac/hal/ssv6006c/ssv6006_cfg.h	35;"	d
+SSV6006_ID_TX_THRESHOLD	smac/hal/ssv6006c/ssv6006_cfg.h	37;"	d
+SSV6006_ID_TX_THRESHOLD	smac/hal/ssv6006c/ssv6006_cfg.h	50;"	d
+SSV6006_ID_TX_THRESHOLD	smac/hal/ssv6006c/ssv6006_cfg.h	56;"	d
+SSV6006_ID_TX_USB	smac/hal/ssv6006c/ssv6006_cfg.h	36;"	d
+SSV6006_ID_USB_RX_THRESHOLD	smac/hal/ssv6006c/ssv6006_cfg.h	40;"	d
+SSV6006_ID_USB_TX_THRESHOLD	smac/hal/ssv6006c/ssv6006_cfg.h	39;"	d
+SSV6006_NUM_HW_BSSID	smac/hal/ssv6006c/ssv6006_mac.h	27;"	d
+SSV6006_NUM_HW_STA	smac/hal/ssv6006c/ssv6006_mac.h	26;"	d
+SSV6006_PAGE_RX_THRESHOLD	smac/hal/ssv6006c/ssv6006_cfg.h	45;"	d
+SSV6006_PAGE_RX_THRESHOLD	smac/hal/ssv6006c/ssv6006_cfg.h	53;"	d
+SSV6006_PAGE_RX_THRESHOLD	smac/hal/ssv6006c/ssv6006_cfg.h	59;"	d
+SSV6006_PAGE_TX_THRESHOLD	smac/hal/ssv6006c/ssv6006_cfg.h	44;"	d
+SSV6006_PAGE_TX_THRESHOLD	smac/hal/ssv6006c/ssv6006_cfg.h	52;"	d
+SSV6006_PAGE_TX_THRESHOLD	smac/hal/ssv6006c/ssv6006_cfg.h	58;"	d
+SSV6006_PAIRWISE_KEY_OFFSET	smac/hal/ssv6006c/ssv6006_mac.h	115;"	d
+SSV6006_RESERVED_SEC_PAGE	smac/hal/ssv6006c/ssv6006_cfg.h	42;"	d
+SSV6006_RESERVED_USB_PAGE	smac/hal/ssv6006c/ssv6006_cfg.h	43;"	d
+SSV6006_RX_BA_MAX_SESSIONS	smac/hal/ssv6006c/ssv6006_mac.h	28;"	d
+SSV6006_SECURITY_KEY_LEN	smac/hal/ssv6006c/ssv6006_mac.h	117;"	d
+SSV6006_TOTAL_ID	smac/hal/ssv6006c/ssv6006_cfg.h	33;"	d
+SSV6006_TOTAL_PAGE	smac/hal/ssv6006c/ssv6006_cfg.h	32;"	d
+SSV6006_TURISMOC_COMMON_CODE_VER	smac/hal/ssv6006c/turismo_common.h	18;"	d
+SSV6006_TURISMOC_PHY_TABLE_VER	smac/hal/ssv6006c/turismoC_wifi_phy_reg.c	16;"	d	file:
+SSV6006_TURISMOC_RF_TABLE_VER	smac/hal/ssv6006c/turismoC_rf_reg.c	16;"	d	file:
+SSV6006_TX_LOWTHRESHOLD_ID_TRIGGER	smac/hal/ssv6006c/ssv6006_cfg.h	48;"	d
+SSV6006_TX_LOWTHRESHOLD_ID_TRIGGER	smac/hal/ssv6006c/ssv6006_cfg.h	55;"	d
+SSV6006_TX_LOWTHRESHOLD_ID_TRIGGER	smac/hal/ssv6006c/ssv6006_cfg.h	61;"	d
+SSV6006_TX_LOWTHRESHOLD_PAGE_TRIGGER	smac/hal/ssv6006c/ssv6006_cfg.h	47;"	d
+SSV6006_TX_LOWTHRESHOLD_PAGE_TRIGGER	smac/hal/ssv6006c/ssv6006_cfg.h	54;"	d
+SSV6006_TX_LOWTHRESHOLD_PAGE_TRIGGER	smac/hal/ssv6006c/ssv6006_cfg.h	60;"	d
+SSV6006_TX_PKT_RSVD	smac/hal/ssv6006c/ssv6006_cfg.h	74;"	d
+SSV6006_TX_PKT_RSVD_SETTING	smac/hal/ssv6006c/ssv6006_cfg.h	73;"	d
+SSV6006_USB_FIFO	smac/hal/ssv6006c/ssv6006_cfg.h	41;"	d
+SSV6006_WLAN_REMAIN_TIME	smac/hal/ssv6006c/ssv6006_cfg.h	78;"	d
+SSV6051P	include/ssv6xxx_common.h	322;"	d
+SSV6051Q	include/ssv6xxx_common.h	321;"	d
+SSV6051Q_P1	include/ssv6xxx_common.h	318;"	d
+SSV6051Q_P2	include/ssv6xxx_common.h	319;"	d
+SSV6051Z	include/ssv6xxx_common.h	320;"	d
+SSV6051_CHIP	include/ssv6xxx_common.h	313;"	d
+SSV6051_CHIP_ECO3	include/ssv6xxx_common.h	314;"	d
+SSV6166	include/ssv6xxx_common.h	317;"	d
+SSV6200_ALLOC_RSVD	include/ssv6200_common.h	54;"	d
+SSV6200_AMPDU_DIVIDER	include/ssv6200.h	44;"	d
+SSV6200_AMPDU_TRIGGER_INDEX	smac/ampdu.h	61;"	d
+SSV6200_BT_PRI_SMP_TIME	include/ssv6200.h	92;"	d
+SSV6200_BT_PRI_SMP_TIME	include/ssv6xxx_cfg.h	90;"	d
+SSV6200_BT_STA_SMP_TIME	include/ssv6200.h	93;"	d
+SSV6200_BT_STA_SMP_TIME	include/ssv6xxx_cfg.h	91;"	d
+SSV6200_CMD_READ_REG	hwif/usb/usb.h	27;"	d
+SSV6200_CMD_WRITE_REG	hwif/usb/usb.h	26;"	d
+SSV6200_ECO	include/ssv_mod_conf.h	67;"	d
+SSV6200_HT_RX_STREAMS	smac/dev.h	290;"	d
+SSV6200_HT_TX_STREAMS	smac/dev.h	289;"	d
+SSV6200_HW_CAP_2GHZ	include/ssv_cfg.h	20;"	d
+SSV6200_HW_CAP_5GHZ	include/ssv_cfg.h	21;"	d
+SSV6200_HW_CAP_AMPDU_RX	include/ssv_cfg.h	27;"	d
+SSV6200_HW_CAP_AMPDU_TX	include/ssv_cfg.h	28;"	d
+SSV6200_HW_CAP_AP	include/ssv_cfg.h	25;"	d
+SSV6200_HW_CAP_BEACON	include/ssv_cfg.h	32;"	d
+SSV6200_HW_CAP_GF	include/ssv_cfg.h	19;"	d
+SSV6200_HW_CAP_HCI_RX_AGGR	include/ssv_cfg.h	31;"	d
+SSV6200_HW_CAP_HT	include/ssv_cfg.h	18;"	d
+SSV6200_HW_CAP_HT40	include/ssv_cfg.h	24;"	d
+SSV6200_HW_CAP_P2P	include/ssv_cfg.h	26;"	d
+SSV6200_HW_CAP_SECURITY	include/ssv_cfg.h	22;"	d
+SSV6200_HW_CAP_SGI	include/ssv_cfg.h	23;"	d
+SSV6200_HW_CAP_STBC	include/ssv_cfg.h	30;"	d
+SSV6200_HW_CAP_TDLS	include/ssv_cfg.h	29;"	d
+SSV6200_ID_AC_BE_OUT_QUEUE	include/ssv6200.h	86;"	d
+SSV6200_ID_AC_BE_OUT_QUEUE	include/ssv6xxx_cfg.h	84;"	d
+SSV6200_ID_AC_BK_OUT_QUEUE	include/ssv6200.h	85;"	d
+SSV6200_ID_AC_BK_OUT_QUEUE	include/ssv6xxx_cfg.h	83;"	d
+SSV6200_ID_AC_RESERVED	include/ssv6200.h	84;"	d
+SSV6200_ID_AC_RESERVED	include/ssv6xxx_cfg.h	82;"	d
+SSV6200_ID_AC_VI_OUT_QUEUE	include/ssv6200.h	87;"	d
+SSV6200_ID_AC_VI_OUT_QUEUE	include/ssv6xxx_cfg.h	85;"	d
+SSV6200_ID_AC_VO_OUT_QUEUE	include/ssv6200.h	88;"	d
+SSV6200_ID_AC_VO_OUT_QUEUE	include/ssv6xxx_cfg.h	86;"	d
+SSV6200_ID_MANAGER_QUEUE	include/ssv6200.h	89;"	d
+SSV6200_ID_MANAGER_QUEUE	include/ssv6xxx_cfg.h	87;"	d
+SSV6200_ID_NUMBER	hci_wrapper/ssv_huw.c	29;"	d	file:
+SSV6200_ID_NUMBER	include/ssv6200.h	82;"	d
+SSV6200_ID_NUMBER	include/ssv6xxx_cfg.h	80;"	d
+SSV6200_ID_RX_THRESHOLD	include/ssv6200.h	40;"	d
+SSV6200_ID_RX_THRESHOLD	include/ssv6200.h	49;"	d
+SSV6200_ID_RX_THRESHOLD	include/ssv6200.h	55;"	d
+SSV6200_ID_RX_THRESHOLD	include/ssv6200.h	63;"	d
+SSV6200_ID_RX_THRESHOLD	include/ssv6200.h	69;"	d
+SSV6200_ID_RX_THRESHOLD	include/ssv6xxx_cfg.h	39;"	d
+SSV6200_ID_RX_THRESHOLD	include/ssv6xxx_cfg.h	47;"	d
+SSV6200_ID_RX_THRESHOLD	include/ssv6xxx_cfg.h	53;"	d
+SSV6200_ID_RX_THRESHOLD	include/ssv6xxx_cfg.h	61;"	d
+SSV6200_ID_RX_THRESHOLD	include/ssv6xxx_cfg.h	67;"	d
+SSV6200_ID_TX_THRESHOLD	include/ssv6200.h	39;"	d
+SSV6200_ID_TX_THRESHOLD	include/ssv6200.h	48;"	d
+SSV6200_ID_TX_THRESHOLD	include/ssv6200.h	54;"	d
+SSV6200_ID_TX_THRESHOLD	include/ssv6200.h	62;"	d
+SSV6200_ID_TX_THRESHOLD	include/ssv6200.h	68;"	d
+SSV6200_ID_TX_THRESHOLD	include/ssv6xxx_cfg.h	38;"	d
+SSV6200_ID_TX_THRESHOLD	include/ssv6xxx_cfg.h	46;"	d
+SSV6200_ID_TX_THRESHOLD	include/ssv6xxx_cfg.h	52;"	d
+SSV6200_ID_TX_THRESHOLD	include/ssv6xxx_cfg.h	60;"	d
+SSV6200_ID_TX_THRESHOLD	include/ssv6xxx_cfg.h	66;"	d
+SSV6200_MAX_BCAST_QUEUE_LEN	smac/dev.h	806;"	d
+SSV6200_MAX_HW_MAC_ADDR	smac/dev.h	119;"	d
+SSV6200_MAX_VIF	smac/dev.h	120;"	d
+SSV6200_PAGE_RX_THRESHOLD	include/ssv6200.h	43;"	d
+SSV6200_PAGE_RX_THRESHOLD	include/ssv6200.h	51;"	d
+SSV6200_PAGE_RX_THRESHOLD	include/ssv6200.h	57;"	d
+SSV6200_PAGE_RX_THRESHOLD	include/ssv6200.h	65;"	d
+SSV6200_PAGE_RX_THRESHOLD	include/ssv6200.h	72;"	d
+SSV6200_PAGE_RX_THRESHOLD	include/ssv6200.h	75;"	d
+SSV6200_PAGE_RX_THRESHOLD	include/ssv6200.h	77;"	d
+SSV6200_PAGE_RX_THRESHOLD	include/ssv6xxx_cfg.h	41;"	d
+SSV6200_PAGE_RX_THRESHOLD	include/ssv6xxx_cfg.h	49;"	d
+SSV6200_PAGE_RX_THRESHOLD	include/ssv6xxx_cfg.h	55;"	d
+SSV6200_PAGE_RX_THRESHOLD	include/ssv6xxx_cfg.h	63;"	d
+SSV6200_PAGE_RX_THRESHOLD	include/ssv6xxx_cfg.h	70;"	d
+SSV6200_PAGE_RX_THRESHOLD	include/ssv6xxx_cfg.h	73;"	d
+SSV6200_PAGE_RX_THRESHOLD	include/ssv6xxx_cfg.h	75;"	d
+SSV6200_PAGE_TX_THRESHOLD	include/ssv6200.h	42;"	d
+SSV6200_PAGE_TX_THRESHOLD	include/ssv6200.h	50;"	d
+SSV6200_PAGE_TX_THRESHOLD	include/ssv6200.h	56;"	d
+SSV6200_PAGE_TX_THRESHOLD	include/ssv6200.h	64;"	d
+SSV6200_PAGE_TX_THRESHOLD	include/ssv6200.h	71;"	d
+SSV6200_PAGE_TX_THRESHOLD	include/ssv6200.h	74;"	d
+SSV6200_PAGE_TX_THRESHOLD	include/ssv6200.h	76;"	d
+SSV6200_PAGE_TX_THRESHOLD	include/ssv6xxx_cfg.h	40;"	d
+SSV6200_PAGE_TX_THRESHOLD	include/ssv6xxx_cfg.h	48;"	d
+SSV6200_PAGE_TX_THRESHOLD	include/ssv6xxx_cfg.h	54;"	d
+SSV6200_PAGE_TX_THRESHOLD	include/ssv6xxx_cfg.h	62;"	d
+SSV6200_PAGE_TX_THRESHOLD	include/ssv6xxx_cfg.h	69;"	d
+SSV6200_PAGE_TX_THRESHOLD	include/ssv6xxx_cfg.h	72;"	d
+SSV6200_PAGE_TX_THRESHOLD	include/ssv6xxx_cfg.h	74;"	d
+SSV6200_RESERVED_PAGE	include/ssv6200.h	41;"	d
+SSV6200_RX_BA_MAX_SESSIONS	smac/dev.h	121;"	d
+SSV6200_RX_HIGHEST_RATE	smac/dev.h	291;"	d
+SSV6200_TOTAL_ID	include/ssv6200.h	37;"	d
+SSV6200_TOTAL_ID	include/ssv6xxx_cfg.h	36;"	d
+SSV6200_TOTAL_PAGE	include/ssv6200.h	36;"	d
+SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER	include/ssv6200.h	46;"	d
+SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER	include/ssv6200.h	53;"	d
+SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER	include/ssv6200.h	59;"	d
+SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER	include/ssv6200.h	67;"	d
+SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER	include/ssv6200.h	80;"	d
+SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER	include/ssv6xxx_cfg.h	44;"	d
+SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER	include/ssv6xxx_cfg.h	51;"	d
+SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER	include/ssv6xxx_cfg.h	57;"	d
+SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER	include/ssv6xxx_cfg.h	65;"	d
+SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER	include/ssv6xxx_cfg.h	78;"	d
+SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER	include/ssv6200.h	45;"	d
+SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER	include/ssv6200.h	52;"	d
+SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER	include/ssv6200.h	58;"	d
+SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER	include/ssv6200.h	66;"	d
+SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER	include/ssv6200.h	79;"	d
+SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER	include/ssv6xxx_cfg.h	43;"	d
+SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER	include/ssv6xxx_cfg.h	50;"	d
+SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER	include/ssv6xxx_cfg.h	56;"	d
+SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER	include/ssv6xxx_cfg.h	64;"	d
+SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER	include/ssv6xxx_cfg.h	77;"	d
+SSV6200_TX_PKT_RSVD	include/ssv6200_common.h	53;"	d
+SSV6200_TX_PKT_RSVD_SETTING	include/ssv6200_common.h	52;"	d
+SSV6200_USE_HW_WSID	smac/dev.h	128;"	d
+SSV6200_WLAN_REMAIN_TIME	include/ssv6200.h	94;"	d
+SSV6200_WLAN_REMAIN_TIME	include/ssv6xxx_cfg.h	92;"	d
+SSV62XX_G_RATE_INDEX	smac/ssv_rc_common.h	42;"	d
+SSV62XX_RATE_MCS_GREENFIELD_INDEX	smac/ssv_rc_common.h	46;"	d
+SSV62XX_RATE_MCS_INDEX	smac/ssv_rc_common.h	43;"	d
+SSV62XX_RATE_MCS_LGI_INDEX	smac/ssv_rc_common.h	44;"	d
+SSV62XX_RATE_MCS_SGI_INDEX	smac/ssv_rc_common.h	45;"	d
+SSV62XX_TX_MAX_RATES	include/ssv6xxx_common.h	50;"	d
+SSV6XXX_AMPDU_DIVIDER	include/ssv6xxx_cfg.h	42;"	d
+SSV6XXX_CHIP_ID_LENGTH	include/ssv6xxx_common.h	62;"	d
+SSV6XXX_CHIP_ID_SHORT_LENGTH	include/ssv6xxx_common.h	63;"	d
+SSV6XXX_CMD_HEADER_SIZE	hwif/usb/usb.c	42;"	d	file:
+SSV6XXX_GET_STA_INFO	smac/dev.h	699;"	d
+SSV6XXX_HCI_OP_IFERR	hci/hctrl.h	19;"	d
+SSV6XXX_HCI_OP_INVALID	hci/hctrl.h	18;"	d
+SSV6XXX_HOST_CMD_INIT_CALI	include/ssv6xxx_common.h	/^    SSV6XXX_HOST_CMD_INIT_CALI = 3,$/;"	e	enum:__anon44
+SSV6XXX_HOST_CMD_LOG	include/ssv6xxx_common.h	/^    SSV6XXX_HOST_CMD_LOG = 1,$/;"	e	enum:__anon44
+SSV6XXX_HOST_CMD_MRX_MODE	include/ssv6xxx_common.h	/^    SSV6XXX_HOST_CMD_MRX_MODE = 11,$/;"	e	enum:__anon44
+SSV6XXX_HOST_CMD_PS	include/ssv6xxx_common.h	/^    SSV6XXX_HOST_CMD_PS = 2,$/;"	e	enum:__anon44
+SSV6XXX_HOST_CMD_RX_TPUT	include/ssv6xxx_common.h	/^    SSV6XXX_HOST_CMD_RX_TPUT = 4,$/;"	e	enum:__anon44
+SSV6XXX_HOST_CMD_SET_NOA	include/ssv6xxx_common.h	/^    SSV6XXX_HOST_CMD_SET_NOA = 8,$/;"	e	enum:__anon44
+SSV6XXX_HOST_CMD_SMART_ICOMM	include/ssv6xxx_common.h	/^    SSV6XXX_HOST_CMD_SMART_ICOMM = 6,$/;"	e	enum:__anon44
+SSV6XXX_HOST_CMD_SOFT_BEACON	include/ssv6xxx_common.h	/^    SSV6XXX_HOST_CMD_SOFT_BEACON = 10,$/;"	e	enum:__anon44
+SSV6XXX_HOST_CMD_START	include/ssv6xxx_common.h	/^    SSV6XXX_HOST_CMD_START = 0,$/;"	e	enum:__anon44
+SSV6XXX_HOST_CMD_TX_POLL	include/ssv6xxx_common.h	/^    SSV6XXX_HOST_CMD_TX_POLL = 9,$/;"	e	enum:__anon44
+SSV6XXX_HOST_CMD_TX_TPUT	include/ssv6xxx_common.h	/^    SSV6XXX_HOST_CMD_TX_TPUT = 5,$/;"	e	enum:__anon44
+SSV6XXX_HOST_CMD_WSID_OP	include/ssv6xxx_common.h	/^    SSV6XXX_HOST_CMD_WSID_OP = 7,$/;"	e	enum:__anon44
+SSV6XXX_HOST_SOC_CMD_MAXID	include/ssv6xxx_common.h	/^    SSV6XXX_HOST_SOC_CMD_MAXID = 12,$/;"	e	enum:__anon44
+SSV6XXX_ID_AC_BE_OUT_QUEUE	hci/ssv_hci.h	28;"	d
+SSV6XXX_ID_AC_BK_OUT_QUEUE	hci/ssv_hci.h	27;"	d
+SSV6XXX_ID_AC_VI_OUT_QUEUE	hci/ssv_hci.h	29;"	d
+SSV6XXX_ID_AC_VO_OUT_QUEUE	hci/ssv_hci.h	30;"	d
+SSV6XXX_ID_HCI_INPUT_QUEUE	hci/ssv_hci.h	37;"	d
+SSV6XXX_ID_MANAGER_QUEUE	hci/ssv_hci.h	31;"	d
+SSV6XXX_ID_TX_THRESHOLD	hci/ssv_hci.h	23;"	d
+SSV6XXX_ID_USB_AC_BE_OUT_QUEUE	hci/ssv_hci.h	33;"	d
+SSV6XXX_ID_USB_AC_BK_OUT_QUEUE	hci/ssv_hci.h	32;"	d
+SSV6XXX_ID_USB_AC_VI_OUT_QUEUE	hci/ssv_hci.h	34;"	d
+SSV6XXX_ID_USB_AC_VO_OUT_QUEUE	hci/ssv_hci.h	35;"	d
+SSV6XXX_ID_USB_MANAGER_QUEUE	hci/ssv_hci.h	36;"	d
+SSV6XXX_INT_LOW_EDCA_0	hci/hctrl.h	23;"	d
+SSV6XXX_INT_LOW_EDCA_1	hci/hctrl.h	24;"	d
+SSV6XXX_INT_LOW_EDCA_2	hci/hctrl.h	25;"	d
+SSV6XXX_INT_LOW_EDCA_3	hci/hctrl.h	26;"	d
+SSV6XXX_INT_RESOURCE_LOW	hci/hctrl.h	27;"	d
+SSV6XXX_INT_RX	hci/hctrl.h	20;"	d
+SSV6XXX_INT_SOC	hci/hctrl.h	22;"	d
+SSV6XXX_INT_TX	hci/hctrl.h	21;"	d
+SSV6XXX_IQK_CFG_PA_DEF	include/ssv6xxx_common.h	/^    SSV6XXX_IQK_CFG_PA_DEF = 0,$/;"	e	enum:__anon51
+SSV6XXX_IQK_CFG_PA_HP	include/ssv6xxx_common.h	/^    SSV6XXX_IQK_CFG_PA_HP,$/;"	e	enum:__anon51
+SSV6XXX_IQK_CFG_PA_LI_EVB	include/ssv6xxx_common.h	/^    SSV6XXX_IQK_CFG_PA_LI_EVB,$/;"	e	enum:__anon51
+SSV6XXX_IQK_CFG_PA_LI_MPB	include/ssv6xxx_common.h	/^    SSV6XXX_IQK_CFG_PA_LI_MPB,$/;"	e	enum:__anon51
+SSV6XXX_IQK_CFG_XTAL_12M	include/ssv6xxx_common.h	/^    SSV6XXX_IQK_CFG_XTAL_12M,$/;"	e	enum:__anon50
+SSV6XXX_IQK_CFG_XTAL_16M	include/ssv6xxx_common.h	/^    SSV6XXX_IQK_CFG_XTAL_16M,$/;"	e	enum:__anon50
+SSV6XXX_IQK_CFG_XTAL_20M	include/ssv6xxx_common.h	/^    SSV6XXX_IQK_CFG_XTAL_20M,$/;"	e	enum:__anon50
+SSV6XXX_IQK_CFG_XTAL_24M	include/ssv6xxx_common.h	/^    SSV6XXX_IQK_CFG_XTAL_24M,$/;"	e	enum:__anon50
+SSV6XXX_IQK_CFG_XTAL_25M	include/ssv6xxx_common.h	/^    SSV6XXX_IQK_CFG_XTAL_25M,$/;"	e	enum:__anon50
+SSV6XXX_IQK_CFG_XTAL_26M	include/ssv6xxx_common.h	/^    SSV6XXX_IQK_CFG_XTAL_26M = 0,$/;"	e	enum:__anon50
+SSV6XXX_IQK_CFG_XTAL_32M	include/ssv6xxx_common.h	/^    SSV6XXX_IQK_CFG_XTAL_32M,$/;"	e	enum:__anon50
+SSV6XXX_IQK_CFG_XTAL_40M	include/ssv6xxx_common.h	/^    SSV6XXX_IQK_CFG_XTAL_40M,$/;"	e	enum:__anon50
+SSV6XXX_IQK_CFG_XTAL_MAX	include/ssv6xxx_common.h	/^    SSV6XXX_IQK_CFG_XTAL_MAX,$/;"	e	enum:__anon50
+SSV6XXX_IQK_CMD_INIT_CALI	include/ssv6xxx_common.h	/^    SSV6XXX_IQK_CMD_INIT_CALI = 0,$/;"	e	enum:__anon52
+SSV6XXX_IQK_CMD_RTBL_EXPORT	include/ssv6xxx_common.h	/^    SSV6XXX_IQK_CMD_RTBL_EXPORT,$/;"	e	enum:__anon52
+SSV6XXX_IQK_CMD_RTBL_LOAD	include/ssv6xxx_common.h	/^    SSV6XXX_IQK_CMD_RTBL_LOAD,$/;"	e	enum:__anon52
+SSV6XXX_IQK_CMD_RTBL_LOAD_DEF	include/ssv6xxx_common.h	/^    SSV6XXX_IQK_CMD_RTBL_LOAD_DEF,$/;"	e	enum:__anon52
+SSV6XXX_IQK_CMD_RTBL_RESET	include/ssv6xxx_common.h	/^    SSV6XXX_IQK_CMD_RTBL_RESET,$/;"	e	enum:__anon52
+SSV6XXX_IQK_CMD_RTBL_SET	include/ssv6xxx_common.h	/^    SSV6XXX_IQK_CMD_RTBL_SET,$/;"	e	enum:__anon52
+SSV6XXX_IQK_CMD_TK_CHCH	include/ssv6xxx_common.h	/^    SSV6XXX_IQK_CMD_TK_CHCH,$/;"	e	enum:__anon52
+SSV6XXX_IQK_CMD_TK_EVM	include/ssv6xxx_common.h	/^    SSV6XXX_IQK_CMD_TK_EVM,$/;"	e	enum:__anon52
+SSV6XXX_IQK_CMD_TK_TONE	include/ssv6xxx_common.h	/^    SSV6XXX_IQK_CMD_TK_TONE,$/;"	e	enum:__anon52
+SSV6XXX_IQK_PAPD	include/ssv6xxx_common.h	287;"	d
+SSV6XXX_IQK_RXDC	include/ssv6xxx_common.h	281;"	d
+SSV6XXX_IQK_RXIQ	include/ssv6xxx_common.h	285;"	d
+SSV6XXX_IQK_RXRC	include/ssv6xxx_common.h	282;"	d
+SSV6XXX_IQK_TEMPERATURE	include/ssv6xxx_common.h	280;"	d
+SSV6XXX_IQK_TSSI	include/ssv6xxx_common.h	286;"	d
+SSV6XXX_IQK_TXDC	include/ssv6xxx_common.h	283;"	d
+SSV6XXX_IQK_TXIQ	include/ssv6xxx_common.h	284;"	d
+SSV6XXX_MAX_RXCMDSZ	hwif/usb/usb.c	41;"	d	file:
+SSV6XXX_MAX_TXCMDSZ	hwif/usb/usb.c	40;"	d	file:
+SSV6XXX_MRX_MODE_TYPE	include/ssv6xxx_common.h	/^enum SSV6XXX_MRX_MODE_TYPE$/;"	g
+SSV6XXX_MRX_NORMAL	include/ssv6xxx_common.h	/^    SSV6XXX_MRX_NORMAL = 0,$/;"	e	enum:SSV6XXX_MRX_MODE_TYPE
+SSV6XXX_MRX_PROMISCUOUS	include/ssv6xxx_common.h	/^    SSV6XXX_MRX_PROMISCUOUS = 1$/;"	e	enum:SSV6XXX_MRX_MODE_TYPE
+SSV6XXX_NOA_START	include/ssv6xxx_common.h	/^    SSV6XXX_NOA_START = 0 ,$/;"	e	enum:__anon46
+SSV6XXX_NOA_STOP	include/ssv6xxx_common.h	/^    SSV6XXX_NOA_STOP ,$/;"	e	enum:__anon46
+SSV6XXX_OPMODE	smac/dev.h	/^enum SSV6XXX_OPMODE {$/;"	g
+SSV6XXX_OPMODE_AP	smac/dev.h	/^    SSV6XXX_OPMODE_AP = 1,$/;"	e	enum:SSV6XXX_OPMODE
+SSV6XXX_OPMODE_IBSS	smac/dev.h	/^    SSV6XXX_OPMODE_IBSS = 2,$/;"	e	enum:SSV6XXX_OPMODE
+SSV6XXX_OPMODE_STA	smac/dev.h	/^    SSV6XXX_OPMODE_STA = 0,$/;"	e	enum:SSV6XXX_OPMODE
+SSV6XXX_OPMODE_WDS	smac/dev.h	/^    SSV6XXX_OPMODE_WDS = 3$/;"	e	enum:SSV6XXX_OPMODE
+SSV6XXX_PAGE_TX_THRESHOLD	hci/ssv_hci.h	24;"	d
+SSV6XXX_PKT_RUN_TYPE_AMPDU_END	include/ssv6xxx_common.h	81;"	d
+SSV6XXX_PKT_RUN_TYPE_AMPDU_START	include/ssv6xxx_common.h	80;"	d
+SSV6XXX_PKT_RUN_TYPE_NOTUSED	include/ssv6xxx_common.h	79;"	d
+SSV6XXX_PKT_RUN_TYPE_NULLFUN	include/ssv6xxx_common.h	82;"	d
+SSV6XXX_RC_COUNTER_CLEAR	include/ssv6200_common.h	/^    SSV6XXX_RC_COUNTER_CLEAR = 1 ,$/;"	e	enum:__anon42
+SSV6XXX_RC_REPORT	include/ssv6200_common.h	/^    SSV6XXX_RC_REPORT ,$/;"	e	enum:__anon42
+SSV6XXX_RETURN_STATE	include/ssv6xxx_common.h	/^enum SSV6XXX_RETURN_STATE$/;"	g
+SSV6XXX_RX_DESC_LEN	include/ssv6xxx_common.h	73;"	d
+SSV6XXX_SET_HW_TABLE	smac/dev.h	266;"	d
+SSV6XXX_SOFT_BEACON_START	include/ssv6xxx_common.h	/^    SSV6XXX_SOFT_BEACON_START = 0,$/;"	e	enum:SSV6XXX_SOFT_BEACON_TYPE
+SSV6XXX_SOFT_BEACON_STOP	include/ssv6xxx_common.h	/^    SSV6XXX_SOFT_BEACON_STOP = 1$/;"	e	enum:SSV6XXX_SOFT_BEACON_TYPE
+SSV6XXX_SOFT_BEACON_TYPE	include/ssv6xxx_common.h	/^enum SSV6XXX_SOFT_BEACON_TYPE$/;"	g
+SSV6XXX_STATE_MAX	include/ssv6xxx_common.h	/^    SSV6XXX_STATE_MAX$/;"	e	enum:SSV6XXX_RETURN_STATE
+SSV6XXX_STATE_NG	include/ssv6xxx_common.h	/^    SSV6XXX_STATE_NG,$/;"	e	enum:SSV6XXX_RETURN_STATE
+SSV6XXX_STATE_OK	include/ssv6xxx_common.h	/^    SSV6XXX_STATE_OK,$/;"	e	enum:SSV6XXX_RETURN_STATE
+SSV6XXX_TX_DESC_LEN	include/ssv6xxx_common.h	76;"	d
+SSV6XXX_TX_LOWTHRESHOLD_ID_TRIGGER	hci/ssv_hci.h	25;"	d
+SSV6XXX_TX_LOWTHRESHOLD_PAGE_TRIGGER	hci/ssv_hci.h	26;"	d
+SSV6XXX_TX_POLL_RESET	include/ssv6xxx_common.h	/^    SSV6XXX_TX_POLL_RESET = 1,$/;"	e	enum:SSV6XXX_TX_POLL_TYPE
+SSV6XXX_TX_POLL_START	include/ssv6xxx_common.h	/^    SSV6XXX_TX_POLL_START = 0,$/;"	e	enum:SSV6XXX_TX_POLL_TYPE
+SSV6XXX_TX_POLL_STOP	include/ssv6xxx_common.h	/^    SSV6XXX_TX_POLL_STOP = 2$/;"	e	enum:SSV6XXX_TX_POLL_TYPE
+SSV6XXX_TX_POLL_TYPE	include/ssv6xxx_common.h	/^enum SSV6XXX_TX_POLL_TYPE$/;"	g
+SSV6XXX_USE_HW_DECRYPT	smac/dev.h	276;"	d
+SSV6XXX_USE_LOCAL_SW_DECRYPT	smac/dev.h	278;"	d
+SSV6XXX_USE_MAC80211_DECRYPT	smac/dev.h	279;"	d
+SSV6XXX_USE_SW_DECRYPT	smac/dev.h	277;"	d
+SSV6XXX_VOLT_33V	include/ssv6xxx_common.h	/^    SSV6XXX_VOLT_33V = 0,$/;"	e	enum:__anon49
+SSV6XXX_VOLT_42V	include/ssv6xxx_common.h	/^    SSV6XXX_VOLT_42V,$/;"	e	enum:__anon49
+SSV6XXX_VOLT_DCDC_CONVERT	include/ssv6xxx_common.h	/^    SSV6XXX_VOLT_DCDC_CONVERT = 0,$/;"	e	enum:__anon48
+SSV6XXX_VOLT_LDO_CONVERT	include/ssv6xxx_common.h	/^    SSV6XXX_VOLT_LDO_CONVERT = 1,$/;"	e	enum:__anon48
+SSV6XXX_WSID_OPS	include/ssv6xxx_common.h	/^enum SSV6XXX_WSID_OPS$/;"	g
+SSV6XXX_WSID_OPS_ADD	include/ssv6xxx_common.h	/^    SSV6XXX_WSID_OPS_ADD,$/;"	e	enum:SSV6XXX_WSID_OPS
+SSV6XXX_WSID_OPS_DEL	include/ssv6xxx_common.h	/^    SSV6XXX_WSID_OPS_DEL,$/;"	e	enum:SSV6XXX_WSID_OPS
+SSV6XXX_WSID_OPS_DISABLE_CAPS	include/ssv6xxx_common.h	/^    SSV6XXX_WSID_OPS_DISABLE_CAPS,$/;"	e	enum:SSV6XXX_WSID_OPS
+SSV6XXX_WSID_OPS_ENABLE_CAPS	include/ssv6xxx_common.h	/^    SSV6XXX_WSID_OPS_ENABLE_CAPS,$/;"	e	enum:SSV6XXX_WSID_OPS
+SSV6XXX_WSID_OPS_HWWSID_GROUP_SET_TYPE	include/ssv6xxx_common.h	/^    SSV6XXX_WSID_OPS_HWWSID_GROUP_SET_TYPE,$/;"	e	enum:SSV6XXX_WSID_OPS
+SSV6XXX_WSID_OPS_HWWSID_PAIRWISE_SET_TYPE	include/ssv6xxx_common.h	/^    SSV6XXX_WSID_OPS_HWWSID_PAIRWISE_SET_TYPE,$/;"	e	enum:SSV6XXX_WSID_OPS
+SSV6XXX_WSID_OPS_MAX	include/ssv6xxx_common.h	/^    SSV6XXX_WSID_OPS_MAX$/;"	e	enum:SSV6XXX_WSID_OPS
+SSV6XXX_WSID_OPS_RESETALL	include/ssv6xxx_common.h	/^    SSV6XXX_WSID_OPS_RESETALL,$/;"	e	enum:SSV6XXX_WSID_OPS
+SSV6XXX_WSID_SEC	include/ssv6xxx_common.h	/^enum SSV6XXX_WSID_SEC$/;"	g
+SSV6XXX_WSID_SEC_GROUP	include/ssv6xxx_common.h	/^    SSV6XXX_WSID_SEC_GROUP = 1<<1,$/;"	e	enum:SSV6XXX_WSID_SEC
+SSV6XXX_WSID_SEC_HW	include/ssv6xxx_common.h	/^    SSV6XXX_WSID_SEC_HW,$/;"	e	enum:SSV6XXX_WSID_SEC_TYPE
+SSV6XXX_WSID_SEC_NONE	include/ssv6xxx_common.h	/^    SSV6XXX_WSID_SEC_NONE = 0,$/;"	e	enum:SSV6XXX_WSID_SEC
+SSV6XXX_WSID_SEC_PAIRWISE	include/ssv6xxx_common.h	/^    SSV6XXX_WSID_SEC_PAIRWISE = 1<<0,$/;"	e	enum:SSV6XXX_WSID_SEC
+SSV6XXX_WSID_SEC_SW	include/ssv6xxx_common.h	/^    SSV6XXX_WSID_SEC_SW,$/;"	e	enum:SSV6XXX_WSID_SEC_TYPE
+SSV6XXX_WSID_SEC_TYPE	include/ssv6xxx_common.h	/^enum SSV6XXX_WSID_SEC_TYPE$/;"	g
+SSV6XXX_WSID_SEC_TYPE_MAX	include/ssv6xxx_common.h	/^    SSV6XXX_WSID_SEC_TYPE_MAX$/;"	e	enum:SSV6XXX_WSID_SEC_TYPE
+SSV6xxx_BEACON_0	include/hal.h	/^ SSV6xxx_BEACON_0,$/;"	e	enum:ssv6xxx_beacon_type
+SSV6xxx_BEACON_0	smac/ap.c	/^ SSV6xxx_BEACON_0,$/;"	e	enum:ssv6xxx_beacon_type	file:
+SSV6xxx_BEACON_1	include/hal.h	/^ SSV6xxx_BEACON_1,$/;"	e	enum:ssv6xxx_beacon_type
+SSV6xxx_BEACON_1	smac/ap.c	/^ SSV6xxx_BEACON_1,$/;"	e	enum:ssv6xxx_beacon_type	file:
+SSV6xxx_BEACON_MAX_ALLOCATE_CNT	smac/ap.c	45;"	d	file:
+SSVCABRIO_INT_GPIO	bridge/sdiobridge.c	/^    SSVCABRIO_INT_GPIO = 0x00000004,$/;"	e	enum:ssvcabrio_int	file:
+SSVCABRIO_INT_RX	bridge/sdiobridge.c	/^    SSVCABRIO_INT_RX = 0x00000001,$/;"	e	enum:ssvcabrio_int	file:
+SSVCABRIO_INT_SYS	bridge/sdiobridge.c	/^    SSVCABRIO_INT_SYS = 0x00000008,$/;"	e	enum:ssvcabrio_int	file:
+SSVCABRIO_INT_TX	bridge/sdiobridge.c	/^    SSVCABRIO_INT_TX = 0x00000002,$/;"	e	enum:ssvcabrio_int	file:
+SSVCABRIO_NUM_CHANNELS	include/cabrio.h	26;"	d
+SSVCABRIO_PLAT_EEP_MAX_WORDS	hwif/hwif.h	25;"	d
+SSVCABRIO_RSSI_BAD	include/cabrio.h	25;"	d
+SSVSDIOBRIDGE_H	bridge/sdiobridge.h	17;"	d
+SSVSDIOBRIDGE_PUB_H	bridge/sdiobridge_pub.h	17;"	d
+SSV_ADD_AMPDU_TXINFO	smac/ampdu.h	238;"	d
+SSV_ADD_AMPDU_TXINFO	smac/ampdu.h	255;"	d
+SSV_ADD_FW_WSID	smac/dev.h	1205;"	d
+SSV_ADD_FW_WSID	smac/dev.h	1348;"	d
+SSV_ADD_TXINFO	smac/dev.h	1191;"	d
+SSV_ADD_TXINFO	smac/dev.h	1330;"	d
+SSV_ADJ_CONFIG	smac/dev.h	1229;"	d
+SSV_ADJ_CONFIG	smac/dev.h	1387;"	d
+SSV_ALLOC_PBUF	smac/ap.h	40;"	d
+SSV_ALLOC_PBUF	smac/ap.h	49;"	d
+SSV_AMPDU_AUTO_CRC_EN	smac/ampdu.h	235;"	d
+SSV_AMPDU_AUTO_CRC_EN	smac/ampdu.h	252;"	d
+SSV_AMPDU_BA_HANDLER	smac/ampdu.h	245;"	d
+SSV_AMPDU_BA_HANDLER	smac/ampdu.h	262;"	d
+SSV_AMPDU_BA_TIME	smac/ampdu.h	49;"	d
+SSV_AMPDU_BA_WINDOW_SIZE	smac/ampdu.h	40;"	d
+SSV_AMPDU_FLOW_CONTROL	smac/ampdu.h	30;"	d
+SSV_AMPDU_FLOW_CONTROL	smac/ampdu.h	33;"	d
+SSV_AMPDU_FLOW_CONTROL_LOWER_BOUND	smac/ampdu.h	45;"	d
+SSV_AMPDU_FLOW_CONTROL_UPPER_BOUND	smac/ampdu.h	44;"	d
+SSV_AMPDU_LIMIT_MAX	include/cabrio.h	23;"	d
+SSV_AMPDU_MAX_SSN	smac/ampdu.h	39;"	d
+SSV_AMPDU_MAX_TRANSMIT_LENGTH	smac/ampdu.h	249;"	d
+SSV_AMPDU_MAX_TRANSMIT_LENGTH	smac/ampdu.h	266;"	d
+SSV_AMPDU_MPDU_LIVE_TIME	smac/ampdu.h	48;"	d
+SSV_AMPDU_RX_START	smac/ampdu.h	243;"	d
+SSV_AMPDU_RX_START	smac/ampdu.h	260;"	d
+SSV_AMPDU_SIZE_1_2	smac/ampdu.h	42;"	d
+SSV_AMPDU_SIZE_3_7	smac/ampdu.h	43;"	d
+SSV_AMPDU_SN_a_minus_b	smac/ampdu.h	90;"	d
+SSV_AMPDU_TX_TIME_THRESHOLD	smac/ampdu.h	47;"	d
+SSV_AMPDU_WINDOW_SIZE	smac/ampdu.h	41;"	d
+SSV_AMPDU_aggr_num_max	smac/ampdu.h	35;"	d
+SSV_AMPDU_retry_counter_max	smac/ampdu.h	37;"	d
+SSV_AMPDU_seq_num_max	smac/ampdu.h	36;"	d
+SSV_AMPDU_timer_period	smac/ampdu.h	46;"	d
+SSV_AMPDU_tx_group_id_max	smac/ampdu.h	38;"	d
+SSV_AUTO_GEN_NULLPKT	ssvdevice/ssv_cmd.h	80;"	d
+SSV_AUTO_GEN_NULLPKT	ssvdevice/ssv_cmd.h	99;"	d
+SSV_BAR_CTRL_ACK_POLICY_NORMAL	smac/ampdu.h	70;"	d
+SSV_BAR_CTRL_CBMTID_COMPRESSED_BA	smac/ampdu.h	71;"	d
+SSV_BAR_CTRL_TID_INFO_SHIFT	smac/ampdu.h	72;"	d
+SSV_BEACON_ENABLE	smac/ap.h	41;"	d
+SSV_BEACON_ENABLE	smac/ap.h	50;"	d
+SSV_BEACON_ENABLE	smac/dev.h	1203;"	d
+SSV_BEACON_ENABLE	smac/dev.h	1346;"	d
+SSV_BEACON_GET_VALID_CFG	smac/ap.h	39;"	d
+SSV_BEACON_GET_VALID_CFG	smac/ap.h	48;"	d
+SSV_BEACON_LOSS_CONFIG	smac/dev.h	1232;"	d
+SSV_BEACON_LOSS_CONFIG	smac/dev.h	1380;"	d
+SSV_BEACON_LOSS_DISABLE	smac/dev.h	1231;"	d
+SSV_BEACON_LOSS_DISABLE	smac/dev.h	1379;"	d
+SSV_BEACON_LOSS_ENABLE	smac/dev.h	1230;"	d
+SSV_BEACON_LOSS_ENABLE	smac/dev.h	1378;"	d
+SSV_CABRIO_DEVID	hwif/sdio/sdio.c	46;"	d	file:
+SSV_CABRIO_DEVID	include/cabrio.h	19;"	d
+SSV_CABRIO_MAGIC	include/cabrio.h	22;"	d
+SSV_CHK_DUAL_VIF_CHG_RX_FLOW	smac/dev.h	1167;"	d
+SSV_CHK_DUAL_VIF_CHG_RX_FLOW	smac/dev.h	1307;"	d
+SSV_CHK_IF_SUPPORT_HW_BSSID	smac/dev.h	1165;"	d
+SSV_CHK_IF_SUPPORT_HW_BSSID	smac/dev.h	1305;"	d
+SSV_CHK_LPBK_RX_RATE_DESC	smac/dev.h	1239;"	d
+SSV_CHK_LPBK_RX_RATE_DESC	smac/dev.h	1371;"	d
+SSV_CIPHER_CCMP	smac/drv_comm.h	/^    SSV_CIPHER_CCMP,$/;"	e	enum:SSV_CIPHER_E
+SSV_CIPHER_E	smac/drv_comm.h	/^enum SSV_CIPHER_E {$/;"	g
+SSV_CIPHER_INVALID	smac/drv_comm.h	/^    SSV_CIPHER_INVALID = (-1)$/;"	e	enum:SSV_CIPHER_E
+SSV_CIPHER_NONE	smac/drv_comm.h	/^    SSV_CIPHER_NONE,$/;"	e	enum:SSV_CIPHER_E
+SSV_CIPHER_SMS4	smac/drv_comm.h	/^    SSV_CIPHER_SMS4,$/;"	e	enum:SSV_CIPHER_E
+SSV_CIPHER_TKIP	smac/drv_comm.h	/^    SSV_CIPHER_TKIP,$/;"	e	enum:SSV_CIPHER_E
+SSV_CIPHER_WEP104	smac/drv_comm.h	/^    SSV_CIPHER_WEP104,$/;"	e	enum:SSV_CIPHER_E
+SSV_CIPHER_WEP40	smac/drv_comm.h	/^    SSV_CIPHER_WEP40,$/;"	e	enum:SSV_CIPHER_E
+SSV_CLK_SRC	smac/dev.h	/^} SSV_CLK_SRC;$/;"	t	typeref:enum:__anon13
+SSV_CMD_MIB	ssvdevice/ssv_cmd.h	71;"	d
+SSV_CMD_MIB	ssvdevice/ssv_cmd.h	90;"	d
+SSV_CMD_POWER_SAVING	ssvdevice/ssv_cmd.h	72;"	d
+SSV_CMD_POWER_SAVING	ssvdevice/ssv_cmd.h	91;"	d
+SSV_CMD_PRINTF	ssvdevice/ssv_cmd.c	45;"	d	file:
+SSV_CRATE_IDX	smac/ssv_rc.h	31;"	d
+SSV_DEFAULT_NOISE_FLOOR	include/cabrio.h	24;"	d
+SSV_DEL_HW_WSID	smac/dev.h	1207;"	d
+SSV_DEL_HW_WSID	smac/dev.h	1350;"	d
+SSV_DISABLE_FW_WSID	smac/dev.h	1138;"	d
+SSV_DISABLE_FW_WSID	smac/dev.h	1279;"	d
+SSV_DISABLE_USB_ACC	smac/dev.h	1180;"	d
+SSV_DISABLE_USB_ACC	smac/dev.h	1320;"	d
+SSV_DO_IQ_CALIB	smac/init.h	33;"	d
+SSV_DO_IQ_CALIB	smac/init.h	44;"	d
+SSV_DO_IQ_CALIB	smac/init.h	46;"	d
+SSV_DO_TEMPERATURE_COMPENSATION	smac/dev.h	1242;"	d
+SSV_DO_TEMPERATURE_COMPENSATION	smac/dev.h	1374;"	d
+SSV_DRATE_IDX	smac/ssv_rc.h	30;"	d
+SSV_DRVER_NAME	smac/dev.h	38;"	d
+SSV_DUMP_DECISION	ssvdevice/ssv_cmd.h	64;"	d
+SSV_DUMP_DECISION	ssvdevice/ssv_cmd.h	83;"	d
+SSV_DUMP_WSID	ssvdevice/ssv_cmd.h	63;"	d
+SSV_DUMP_WSID	ssvdevice/ssv_cmd.h	82;"	d
+SSV_EDCA_ENABLE	smac/dev.h	1235;"	d
+SSV_EDCA_ENABLE	smac/dev.h	1367;"	d
+SSV_EDCA_FRAC	smac/dev.h	199;"	d
+SSV_EDCA_SCALE	smac/dev.h	198;"	d
+SSV_EDCA_STAT	smac/dev.h	1236;"	d
+SSV_EDCA_STAT	smac/dev.h	1368;"	d
+SSV_EDCA_TRUNC	smac/dev.h	200;"	d
+SSV_EFUSE_ID_RAW_DATA_BASE	smac/efuse.h	46;"	d
+SSV_EFUSE_ID_READ_SWITCH	smac/efuse.h	45;"	d
+SSV_EFUSE_RAW_DATA_BASE	smac/efuse.h	48;"	d
+SSV_EFUSE_READ_SWITCH	smac/efuse.h	47;"	d
+SSV_ENABLE_FW_WSID	smac/dev.h	1140;"	d
+SSV_ENABLE_FW_WSID	smac/dev.h	1281;"	d
+SSV_ENABLE_USB_ACC	smac/dev.h	1179;"	d
+SSV_ENABLE_USB_ACC	smac/dev.h	1319;"	d
+SSV_EP_CMD	hwif/usb/usb.h	22;"	d
+SSV_EP_RSP	hwif/usb/usb.h	23;"	d
+SSV_EP_RX	hwif/usb/usb.h	25;"	d
+SSV_EP_TX	hwif/usb/usb.h	24;"	d
+SSV_ERR_BASE	smartlink/ssv_smartlink.h	/^    SSV_ERR_BASE = -255,$/;"	e	enum:__anon35
+SSV_ERR_GET_CHANNEL	smartlink/ssv_smartlink.h	/^    SSV_ERR_GET_CHANNEL,$/;"	e	enum:__anon35
+SSV_ERR_GET_PROMISC	smartlink/ssv_smartlink.h	/^    SSV_ERR_GET_PROMISC,$/;"	e	enum:__anon35
+SSV_ERR_GET_SI_PASS	smartlink/ssv_smartlink.h	/^    SSV_ERR_GET_SI_PASS,$/;"	e	enum:__anon35
+SSV_ERR_GET_SI_SSID	smartlink/ssv_smartlink.h	/^    SSV_ERR_GET_SI_SSID,$/;"	e	enum:__anon35
+SSV_ERR_GET_SI_STATUS	smartlink/ssv_smartlink.h	/^    SSV_ERR_GET_SI_STATUS,$/;"	e	enum:__anon35
+SSV_ERR_NETLINK_BIND	smartlink/ssv_smartlink.h	/^    SSV_ERR_NETLINK_BIND,$/;"	e	enum:__anon35
+SSV_ERR_NETLINK_CORRUPTED	smartlink/ssv_smartlink.h	/^    SSV_ERR_NETLINK_CORRUPTED,$/;"	e	enum:__anon35
+SSV_ERR_NETLINK_RECVMSG	smartlink/ssv_smartlink.h	/^    SSV_ERR_NETLINK_RECVMSG,$/;"	e	enum:__anon35
+SSV_ERR_NETLINK_SENDMSG	smartlink/ssv_smartlink.h	/^    SSV_ERR_NETLINK_SENDMSG,$/;"	e	enum:__anon35
+SSV_ERR_NETLINK_SOCKET	smartlink/ssv_smartlink.h	/^    SSV_ERR_NETLINK_SOCKET,$/;"	e	enum:__anon35
+SSV_ERR_PARAMETER	smartlink/ssv_smartlink.h	/^    SSV_ERR_PARAMETER,$/;"	e	enum:__anon35
+SSV_ERR_SET_CHANNEL	smartlink/ssv_smartlink.h	/^    SSV_ERR_SET_CHANNEL,$/;"	e	enum:__anon35
+SSV_ERR_SET_PROMISC	smartlink/ssv_smartlink.h	/^    SSV_ERR_SET_PROMISC,$/;"	e	enum:__anon35
+SSV_ERR_SET_SI_CMD	smartlink/ssv_smartlink.h	/^    SSV_ERR_SET_SI_CMD,$/;"	e	enum:__anon35
+SSV_ERR_START_SMARTLINK	smartlink/ssv_smartlink.h	/^    SSV_ERR_START_SMARTLINK = -248,$/;"	e	enum:__anon35
+SSV_ERR_STOP_SMARTLINK	smartlink/ssv_smartlink.h	/^    SSV_ERR_STOP_SMARTLINK,$/;"	e	enum:__anon35
+SSV_FILL_BEACON_TX_DESC	smac/ap.h	45;"	d
+SSV_FILL_BEACON_TX_DESC	smac/ap.h	54;"	d
+SSV_FILL_LPBK_TX_DESC	smac/dev.h	1237;"	d
+SSV_FILL_LPBK_TX_DESC	smac/dev.h	1369;"	d
+SSV_FIRMWARE_MAX	include/ssv6xxx_common.h	328;"	d
+SSV_FIRMWARE_PATH_MAX	include/ssv6xxx_common.h	327;"	d
+SSV_FIRMWARE_URl	include/ssv_firmware_version.h	19;"	d
+SSV_FLASH_READ_ALL_MAP	smac/init.h	38;"	d
+SSV_FLASH_READ_ALL_MAP	smac/init.h	52;"	d
+SSV_FREE_PBUF	smac/dev.h	1214;"	d
+SSV_FREE_PBUF	smac/dev.h	1356;"	d
+SSV_GET_BCN_ONGOING	smac/ap.h	42;"	d
+SSV_GET_BCN_ONGOING	smac/ap.h	51;"	d
+SSV_GET_FFOUT_CNT	ssvdevice/ssv_cmd.h	78;"	d
+SSV_GET_FFOUT_CNT	ssvdevice/ssv_cmd.h	97;"	d
+SSV_GET_FW_NAME	smac/init.h	37;"	d
+SSV_GET_FW_NAME	smac/init.h	51;"	d
+SSV_GET_FW_VERSION	ssvdevice/ssv_cmd.h	73;"	d
+SSV_GET_FW_VERSION	ssvdevice/ssv_cmd.h	92;"	d
+SSV_GET_IC_TIME_TAG	smac/dev.h	1133;"	d
+SSV_GET_IC_TIME_TAG	smac/dev.h	1278;"	d
+SSV_GET_IN_FFCNT	ssvdevice/ssv_cmd.h	79;"	d
+SSV_GET_IN_FFCNT	ssvdevice/ssv_cmd.h	98;"	d
+SSV_GET_RD_ID_ADR	ssvdevice/ssv_cmd.h	77;"	d
+SSV_GET_RD_ID_ADR	ssvdevice/ssv_cmd.h	96;"	d
+SSV_GET_RX_DESC_HDR_OFFSET	smac/dev.h	1219;"	d
+SSV_GET_RX_DESC_HDR_OFFSET	smac/dev.h	1359;"	d
+SSV_GET_RX_DESC_INFO	smac/dev.h	1217;"	d
+SSV_GET_RX_DESC_INFO	smac/dev.h	1357;"	d
+SSV_GET_SEC_DECODE_ERR	smac/dev.h	1215;"	d
+SSV_GET_SEC_DECODE_ERR	smac/dev.h	1381;"	d
+SSV_GET_TX_DESC_CTYPE	smac/dev.h	1187;"	d
+SSV_GET_TX_DESC_CTYPE	smac/dev.h	1328;"	d
+SSV_GET_TX_DESC_SIZE	smac/dev.h	1188;"	d
+SSV_GET_TX_DESC_SIZE	smac/dev.h	1329;"	d
+SSV_GET_TX_DESC_TXQ_IDX	smac/dev.h	1192;"	d
+SSV_GET_TX_DESC_TXQ_IDX	smac/dev.h	1333;"	d
+SSV_GROUP_WPA_USE_HW_CIPHER	smac/dev.h	1147;"	d
+SSV_GROUP_WPA_USE_HW_CIPHER	smac/dev.h	1288;"	d
+SSV_HALT_MNGQ_UNTIL_DTIM	smac/dev.h	1197;"	d
+SSV_HALT_MNGQ_UNTIL_DTIM	smac/dev.h	1337;"	d
+SSV_HT_RATE_MAX	smac/ssv_rc_common.h	20;"	d
+SSV_HT_RATE_UPDATE	smac/ampdu.h	247;"	d
+SSV_HT_RATE_UPDATE	smac/ampdu.h	264;"	d
+SSV_HT_RC_CHANGE_CCK_RSSI_THRESHOLD	smac/ssv_rc_minstrel_ht.c	464;"	d	file:
+SSV_HW	smac/hal/ssv6006c/turismo_common.h	/^typedef struct ssv_hw SSV_HW;$/;"	t	typeref:struct:ssv_hw
+SSV_HW	smac/hal/ssv6006c/turismo_common.h	/^typedef void SSV_HW;$/;"	t
+SSV_HWIF_CAPABILITY_INTERRUPT	hwif/hwif.h	30;"	d
+SSV_HWIF_CAPABILITY_MASK	hwif/hwif.h	26;"	d
+SSV_HWIF_CAPABILITY_POLLING	hwif/hwif.h	31;"	d
+SSV_HWIF_CAPABILITY_SFT	hwif/hwif.h	28;"	d
+SSV_HWIF_INTERFACE_MASK	hwif/hwif.h	27;"	d
+SSV_HWIF_INTERFACE_SDIO	hwif/hwif.h	32;"	d
+SSV_HWIF_INTERFACE_SFT	hwif/hwif.h	29;"	d
+SSV_HWIF_INTERFACE_USB	hwif/hwif.h	33;"	d
+SSV_HW_CRYPTO_KEY_WRITE_WEP	smac/dev.h	1323;"	d
+SSV_HW_TXQ_MAX_SIZE	hci/ssv_hci.h	21;"	d
+SSV_HW_TXQ_NUM	hci/ssv_hci.h	20;"	d
+SSV_HW_TXQ_RESUME_THRES	hci/ssv_hci.h	22;"	d
+SSV_IF_CHK_MAC2	smac/dev.h	1132;"	d
+SSV_IF_CHK_MAC2	smac/dev.h	1275;"	d
+SSV_ILLEGAL_SN	smac/ampdu.h	50;"	d
+SSV_INIT_IQK	smac/dev.h	1130;"	d
+SSV_INIT_IQK	smac/dev.h	1273;"	d
+SSV_INIT_RX_CFG	smac/dev.h	1213;"	d
+SSV_INIT_TX_CFG	smac/dev.h	1212;"	d
+SSV_IS_LEGACY_RATE	smac/dev.h	1221;"	d
+SSV_IS_LEGACY_RATE	smac/dev.h	1361;"	d
+SSV_JUMP_TO_ROM	smac/dev.h	1182;"	d
+SSV_JUMP_TO_ROM	smac/dev.h	1322;"	d
+SSV_LOAD_FW_DISABLE_MCU	hci/ssv_hci.h	122;"	d
+SSV_LOAD_FW_DISABLE_MCU	hci/ssv_hci.h	140;"	d
+SSV_LOAD_FW_ENABLE_MCU	hci/ssv_hci.h	121;"	d
+SSV_LOAD_FW_ENABLE_MCU	hci/ssv_hci.h	139;"	d
+SSV_LOAD_FW_GET_STATUS	hci/ssv_hci.h	124;"	d
+SSV_LOAD_FW_GET_STATUS	hci/ssv_hci.h	142;"	d
+SSV_LOAD_FW_POST_CONFIG_DEVICE	hci/ssv_hci.h	128;"	d
+SSV_LOAD_FW_POST_CONFIG_DEVICE	hci/ssv_hci.h	146;"	d
+SSV_LOAD_FW_PRE_CONFIG_DEVICE	hci/ssv_hci.h	127;"	d
+SSV_LOAD_FW_PRE_CONFIG_DEVICE	hci/ssv_hci.h	145;"	d
+SSV_LOAD_FW_SET_STATUS	hci/ssv_hci.h	123;"	d
+SSV_LOAD_FW_SET_STATUS	hci/ssv_hci.h	141;"	d
+SSV_MAX_CHANNEL	smartlink/ssv_smartlink.h	47;"	d
+SSV_MINSTREL_ACK_LEN	smac/ssv_rc_minstrel.c	24;"	d	file:
+SSV_MINSTREL_AMPDU_RATE_RPTS	smac/ssv_rc_minstrel_ht.h	25;"	d
+SSV_MINSTREL_CCK_GROUP	smac/ssv_rc_minstrel_ht.c	87;"	d	file:
+SSV_MINSTREL_STA_GROUP	smac/ssv_rc_minstrel_ht.c	88;"	d	file:
+SSV_MIN_CHANNEL	smartlink/ssv_smartlink.h	46;"	d
+SSV_NEED_SW_CIPHER	smac/init.h	32;"	d
+SSV_NEED_SW_CIPHER	smac/init.h	41;"	d
+SSV_NULLFUN_FRAME_FILTER	smac/dev.h	1226;"	d
+SSV_NULLFUN_FRAME_FILTER	smac/dev.h	1366;"	d
+SSV_NUM_HW_STA	include/ssv6200_common.h	167;"	d
+SSV_NUM_HW_STA	smac/hal/ssv6006c/ssv6006_common.h	58;"	d
+SSV_NUM_STA	smac/drv_comm.h	24;"	d
+SSV_NUM_VIF	smac/drv_comm.h	25;"	d
+SSV_PAIRWISE_WPA_USE_HW_CIPHER	smac/dev.h	1143;"	d
+SSV_PAIRWISE_WPA_USE_HW_CIPHER	smac/dev.h	1284;"	d
+SSV_PHY_ENABLE	smac/dev.h	1234;"	d
+SSV_PHY_ENABLE	smac/dev.h	1365;"	d
+SSV_PLL_CHK	smac/dev.h	1243;"	d
+SSV_PLL_CHK	smac/dev.h	1375;"	d
+SSV_PMU_AWAKE	smac/dev.h	1177;"	d
+SSV_PMU_AWAKE	smac/dev.h	1317;"	d
+SSV_PROMISC_DISABLED	smartlink/ssv_smartlink.h	48;"	d
+SSV_PROMISC_ENABLED	smartlink/ssv_smartlink.h	49;"	d
+SSV_PUT_MIC_SPACE_FOR_HW_CCMP_ENCRYPT	smac/dev.h	1185;"	d
+SSV_PUT_MIC_SPACE_FOR_HW_CCMP_ENCRYPT	smac/dev.h	1327;"	d
+SSV_RATE_REPORT_HANDLER	smac/dev.h	1227;"	d
+SSV_RATE_REPORT_HANDLER	smac/dev.h	1376;"	d
+SSV_RC_ALGORITHM	smac/dev.h	1134;"	d
+SSV_RC_ALGORITHM	smac/dev.h	1276;"	d
+SSV_RC_HT_INTERVAL	smac/ssv_ht_rc.h	22;"	d
+SSV_RC_HT_STA_CURRENT_RATE_IS_CCK	smac/dev.h	1222;"	d
+SSV_RC_HT_STA_CURRENT_RATE_IS_CCK	smac/dev.h	1362;"	d
+SSV_RC_LEGACY_BITRATE_TO_RATE_DESC	smac/dev.h	1136;"	d
+SSV_RC_LEGACY_BITRATE_TO_RATE_DESC	smac/dev.h	1377;"	d
+SSV_RC_MAC80211_RATE_IDX	smac/dev.h	1210;"	d
+SSV_RC_MAC80211_RATE_IDX	smac/dev.h	1354;"	d
+SSV_RC_MAX_HARDWARE_SUPPORT	include/ssv6xxx_common.h	18;"	d
+SSV_RC_MAX_STA	smac/ssv_rc_common.h	18;"	d
+SSV_RC_RATE_MAX	include/ssv6200_common.h	189;"	d
+SSV_RC_UPDATE_BASIC_RATE	smac/dev.h	1224;"	d
+SSV_RC_UPDATE_BASIC_RATE	smac/dev.h	1363;"	d
+SSV_READRG_HCI_INQ_INFO	hci/ssv_hci.h	119;"	d
+SSV_READRG_HCI_INQ_INFO	hci/ssv_hci.h	137;"	d
+SSV_READRG_TXQ_INFO2	ssvdevice/ssv_cmd.h	75;"	d
+SSV_READRG_TXQ_INFO2	ssvdevice/ssv_cmd.h	94;"	d
+SSV_READ_EFUSE	smac/efuse.h	40;"	d
+SSV_READ_EFUSE	smac/efuse.h	51;"	d
+SSV_READ_FFOUT_CNT	ssvdevice/ssv_cmd.h	65;"	d
+SSV_READ_FFOUT_CNT	ssvdevice/ssv_cmd.h	84;"	d
+SSV_READ_ID_LEN_THRESHOLD	ssvdevice/ssv_cmd.h	68;"	d
+SSV_READ_ID_LEN_THRESHOLD	ssvdevice/ssv_cmd.h	87;"	d
+SSV_READ_IN_FFCNT	ssvdevice/ssv_cmd.h	67;"	d
+SSV_READ_IN_FFCNT	ssvdevice/ssv_cmd.h	86;"	d
+SSV_READ_TAG_STATUS	ssvdevice/ssv_cmd.h	70;"	d
+SSV_READ_TAG_STATUS	ssvdevice/ssv_cmd.h	89;"	d
+SSV_REG_READ	hwif/hwif.h	36;"	d
+SSV_REG_READ1	ssvdevice/ssv_cmd.h	45;"	d
+SSV_REG_SET_BITS1	ssvdevice/ssv_cmd.h	49;"	d
+SSV_REG_WRITE	hwif/hwif.h	34;"	d
+SSV_REG_WRITE1	ssvdevice/ssv_cmd.h	47;"	d
+SSV_RESET_CPU	hci/ssv_hci.h	125;"	d
+SSV_RESET_CPU	hci/ssv_hci.h	143;"	d
+SSV_RESET_SYSPLF	smac/dev.h	1129;"	d
+SSV_RESET_SYSPLF	smac/dev.h	1272;"	d
+SSV_RESTORE_RX_FLOW	smac/dev.h	1172;"	d
+SSV_RESTORE_RX_FLOW	smac/dev.h	1312;"	d
+SSV_RESTORE_TRAP_REASON	smac/dev.h	1176;"	d
+SSV_RESTORE_TRAP_REASON	smac/dev.h	1316;"	d
+SSV_RETRY_BIT_SHIFT	smac/ampdu.h	58;"	d
+SSV_ROOT_URl	include/ssv_version.h	6;"	d
+SSV_SAVE_CLEAR_TRAP_REASON	smac/dev.h	1175;"	d
+SSV_SAVE_CLEAR_TRAP_REASON	smac/dev.h	1315;"	d
+SSV_SAVE_DEFAULT_IPD_CHCFG	smac/dev.h	1193;"	d
+SSV_SAVE_DEFAULT_IPD_CHCFG	smac/dev.h	1383;"	d
+SSV_SAVE_DEFAULT_IPD_CHCFG	smac/dev.h	1385;"	d
+SSV_SAVE_HW_STATUS	smac/dev.h	1131;"	d
+SSV_SAVE_HW_STATUS	smac/dev.h	1274;"	d
+SSV_SC	hci/ssv_hci.h	18;"	d
+SSV_SEND_TX_POLL_CMD	smac/dev.h	1240;"	d
+SSV_SEND_TX_POLL_CMD	smac/dev.h	1372;"	d
+SSV_SEQ_NUM_SHIFT	smac/ampdu.h	57;"	d
+SSV_SET_80211HW_RATE_CONFIG	smac/dev.h	1135;"	d
+SSV_SET_80211HW_RATE_CONFIG	smac/dev.h	1277;"	d
+SSV_SET_AES_TKIP_HW_CRYPTO_GROUP_KEY	smac/dev.h	1149;"	d
+SSV_SET_AES_TKIP_HW_CRYPTO_GROUP_KEY	smac/dev.h	1290;"	d
+SSV_SET_BCN_IFNO	smac/ap.h	43;"	d
+SSV_SET_BCN_IFNO	smac/ap.h	52;"	d
+SSV_SET_BCN_IFNO	smac/dev.h	1201;"	d
+SSV_SET_BCN_IFNO	smac/dev.h	1344;"	d
+SSV_SET_BEACON_REG_LOCK	smac/ap.h	38;"	d
+SSV_SET_BEACON_REG_LOCK	smac/ap.h	47;"	d
+SSV_SET_BSSID	smac/dev.h	1195;"	d
+SSV_SET_BSSID	smac/dev.h	1335;"	d
+SSV_SET_DUR_BURST_SIFS_G	smac/dev.h	1199;"	d
+SSV_SET_DUR_BURST_SIFS_G	smac/dev.h	1342;"	d
+SSV_SET_DUR_SLOT	smac/dev.h	1200;"	d
+SSV_SET_DUR_SLOT	smac/dev.h	1343;"	d
+SSV_SET_FW_HWWSID_SEC_TYPE	smac/dev.h	1169;"	d
+SSV_SET_FW_HWWSID_SEC_TYPE	smac/dev.h	1309;"	d
+SSV_SET_GROUP_CIPHER_TYPE	smac/dev.h	1163;"	d
+SSV_SET_GROUP_CIPHER_TYPE	smac/dev.h	1303;"	d
+SSV_SET_HW_WSID	smac/dev.h	1204;"	d
+SSV_SET_HW_WSID	smac/dev.h	1347;"	d
+SSV_SET_MACADDR	smac/dev.h	1194;"	d
+SSV_SET_MACADDR	smac/dev.h	1334;"	d
+SSV_SET_ON3_ENABLE	smac/init.h	36;"	d
+SSV_SET_ON3_ENABLE	smac/init.h	50;"	d
+SSV_SET_OP_MODE	smac/dev.h	1196;"	d
+SSV_SET_OP_MODE	smac/dev.h	1336;"	d
+SSV_SET_PAIRWISE_CIPHER_TYPE	smac/dev.h	1161;"	d
+SSV_SET_PAIRWISE_CIPHER_TYPE	smac/dev.h	1301;"	d
+SSV_SET_QOS_ENABLE	smac/dev.h	1208;"	d
+SSV_SET_QOS_ENABLE	smac/dev.h	1351;"	d
+SSV_SET_RF_DISABLE	smac/init.h	35;"	d
+SSV_SET_RF_DISABLE	smac/init.h	49;"	d
+SSV_SET_RF_ENABLE	smac/init.h	34;"	d
+SSV_SET_RF_ENABLE	smac/init.h	48;"	d
+SSV_SET_RX_BA	smac/ampdu.h	241;"	d
+SSV_SET_RX_BA	smac/ampdu.h	258;"	d
+SSV_SET_RX_CTRL_FLOW	smac/dev.h	1171;"	d
+SSV_SET_RX_CTRL_FLOW	smac/dev.h	1311;"	d
+SSV_SET_SRAM_MODE	hci/ssv_hci.h	126;"	d
+SSV_SET_SRAM_MODE	hci/ssv_hci.h	144;"	d
+SSV_SET_USB_LPM	smac/dev.h	1181;"	d
+SSV_SET_USB_LPM	smac/dev.h	1321;"	d
+SSV_SET_WMM_PARAM	smac/dev.h	1209;"	d
+SSV_SET_WMM_PARAM	smac/dev.h	1353;"	d
+SSV_SKB_info_size	include/ssv6200.h	104;"	d
+SSV_SMARTLINK_VERSION	smartlink/ssv_smartlink.c	25;"	d	file:
+SSV_SN_STATUS_Discard	smac/ampdu.h	65;"	d
+SSV_SN_STATUS_Release	smac/ampdu.h	62;"	d
+SSV_SN_STATUS_Retry	smac/ampdu.h	63;"	d
+SSV_SN_STATUS_Wait_BA	smac/ampdu.h	64;"	d
+SSV_SRAM_MODE	include/ssv6xxx_common.h	/^enum SSV_SRAM_MODE{$/;"	g
+SSV_STORE_WEP_KEY	smac/dev.h	1183;"	d
+SSV_STORE_WEP_KEY	smac/dev.h	1325;"	d
+SSV_SUBVENDOR_ID_NEW_A	include/cabrio.h	21;"	d
+SSV_SUBVENDOR_ID_NOG	include/cabrio.h	20;"	d
+SSV_SUPPORT_HAL	include/ssv_mod_conf.h	10;"	d
+SSV_SUPPORT_SSV6006	include/ssv_mod_conf.h	13;"	d
+SSV_TEMPERATURE_HIGH	smac/dev.h	112;"	d
+SSV_TEMPERATURE_LOW	smac/dev.h	113;"	d
+SSV_TEMPERATURE_NORMAL	smac/dev.h	111;"	d
+SSV_TXTPUT_SET_DESC	ssvdevice/ssv_cmd.h	74;"	d
+SSV_TXTPUT_SET_DESC	ssvdevice/ssv_cmd.h	93;"	d
+SSV_UNHALT_MNGQ_UNTIL_DTIM	smac/dev.h	1198;"	d
+SSV_UNHALT_MNGQ_UNTIL_DTIM	smac/dev.h	1340;"	d
+SSV_UPDATE_AMPDU_TXINFO	smac/ampdu.h	236;"	d
+SSV_UPDATE_AMPDU_TXINFO	smac/ampdu.h	254;"	d
+SSV_UPDATE_EFUSE_SETTING	smac/dev.h	1241;"	d
+SSV_UPDATE_EFUSE_SETTING	smac/dev.h	1373;"	d
+SSV_UPDATE_NULL_FUNC_TXINFO	smac/dev.h	1189;"	d
+SSV_UPDATE_NULL_FUNC_TXINFO	smac/dev.h	1331;"	d
+SSV_UPDATE_PAGE_ID	smac/dev.h	1128;"	d
+SSV_UPDATE_PAGE_ID	smac/dev.h	1271;"	d
+SSV_UPDATE_TXINFO	smac/ampdu.h	239;"	d
+SSV_UPDATE_TXINFO	smac/ampdu.h	256;"	d
+SSV_USE_HW_ENCRYPT	smac/dev.h	1145;"	d
+SSV_USE_HW_ENCRYPT	smac/dev.h	1286;"	d
+SSV_VENDOR_ID	hwif/sdio/sdio.c	45;"	d	file:
+SSV_VENDOR_ID	include/cabrio.h	18;"	d
+SSV_WEP_USE_HW_CIPHER	smac/dev.h	1142;"	d
+SSV_WEP_USE_HW_CIPHER	smac/dev.h	1283;"	d
+SSV_WIRELESS_ATTR_CONFIG	umac/ssv6xxx_netlink_core.h	/^ SSV_WIRELESS_ATTR_CONFIG,$/;"	e	enum:__anon53
+SSV_WIRELESS_ATTR_MAX	umac/ssv6xxx_netlink_core.h	32;"	d
+SSV_WIRELESS_ATTR_REGISTER	umac/ssv6xxx_netlink_core.h	/^ SSV_WIRELESS_ATTR_REGISTER,$/;"	e	enum:__anon53
+SSV_WIRELESS_ATTR_RXFRAME	umac/ssv6xxx_netlink_core.h	/^ SSV_WIRELESS_ATTR_RXFRAME,$/;"	e	enum:__anon53
+SSV_WIRELESS_ATTR_START_HCI	umac/ssv6xxx_netlink_core.h	/^ SSV_WIRELESS_ATTR_START_HCI,$/;"	e	enum:__anon53
+SSV_WIRELESS_ATTR_TEST	umac/ssv6xxx_netlink_core.h	/^ SSV_WIRELESS_ATTR_TEST,$/;"	e	enum:__anon53
+SSV_WIRELESS_ATTR_TXFRAME	umac/ssv6xxx_netlink_core.h	/^ SSV_WIRELESS_ATTR_TXFRAME,$/;"	e	enum:__anon53
+SSV_WIRELESS_ATTR_UNSPEC	umac/ssv6xxx_netlink_core.h	/^ SSV_WIRELESS_ATTR_UNSPEC,$/;"	e	enum:__anon53
+SSV_WIRELESS_CMD_CONFIG	umac/ssv6xxx_netlink_core.h	/^ SSV_WIRELESS_CMD_CONFIG,$/;"	e	enum:__anon54
+SSV_WIRELESS_CMD_MAX	umac/ssv6xxx_netlink_core.h	44;"	d
+SSV_WIRELESS_CMD_READ_REG	umac/ssv6xxx_netlink_core.h	/^ SSV_WIRELESS_CMD_READ_REG,$/;"	e	enum:__anon54
+SSV_WIRELESS_CMD_RXFRAME	umac/ssv6xxx_netlink_core.h	/^ SSV_WIRELESS_CMD_RXFRAME,$/;"	e	enum:__anon54
+SSV_WIRELESS_CMD_START_HCI	umac/ssv6xxx_netlink_core.h	/^ SSV_WIRELESS_CMD_START_HCI,$/;"	e	enum:__anon54
+SSV_WIRELESS_CMD_TEST	umac/ssv6xxx_netlink_core.h	/^ SSV_WIRELESS_CMD_TEST,$/;"	e	enum:__anon54
+SSV_WIRELESS_CMD_TXFRAME	umac/ssv6xxx_netlink_core.h	/^ SSV_WIRELESS_CMD_TXFRAME,$/;"	e	enum:__anon54
+SSV_WIRELESS_CMD_UNSPEC	umac/ssv6xxx_netlink_core.h	/^ SSV_WIRELESS_CMD_UNSPEC,$/;"	e	enum:__anon54
+SSV_WIRELESS_CMD_WRITE_REG	umac/ssv6xxx_netlink_core.h	/^ SSV_WIRELESS_CMD_WRITE_REG,$/;"	e	enum:__anon54
+SSV_WRITE_EFUSE	smac/efuse.h	41;"	d
+SSV_WRITE_EFUSE	smac/efuse.h	52;"	d
+SSV_WRITE_GROUP_KEYIDX_TO_HW	smac/dev.h	1153;"	d
+SSV_WRITE_GROUP_KEYIDX_TO_HW	smac/dev.h	1294;"	d
+SSV_WRITE_GROUP_KEY_TO_HW	smac/dev.h	1157;"	d
+SSV_WRITE_GROUP_KEY_TO_HW	smac/dev.h	1297;"	d
+SSV_WRITE_KEY_TO_HW	smac/dev.h	1159;"	d
+SSV_WRITE_KEY_TO_HW	smac/dev.h	1299;"	d
+SSV_WRITE_PAIRWISE_KEYIDX_TO_HW	smac/dev.h	1151;"	d
+SSV_WRITE_PAIRWISE_KEYIDX_TO_HW	smac/dev.h	1292;"	d
+SSV_WRITE_PAIRWISE_KEY_TO_HW	smac/dev.h	1155;"	d
+SSV_WRITE_PAIRWISE_KEY_TO_HW	smac/dev.h	1295;"	d
+SSV_a_minus_b_in_c	smac/ampdu.h	83;"	d
+START_BYTE_VALUE2_HI	include/ssv6200_aux.h	3604;"	d
+START_BYTE_VALUE2_I_MSK	include/ssv6200_aux.h	3602;"	d
+START_BYTE_VALUE2_MSK	include/ssv6200_aux.h	3601;"	d
+START_BYTE_VALUE2_SFT	include/ssv6200_aux.h	3603;"	d
+START_BYTE_VALUE2_SZ	include/ssv6200_aux.h	3605;"	d
+START_BYTE_VALUE_HI	include/ssv6200_aux.h	3294;"	d
+START_BYTE_VALUE_I_MSK	include/ssv6200_aux.h	3292;"	d
+START_BYTE_VALUE_MSK	include/ssv6200_aux.h	3291;"	d
+START_BYTE_VALUE_SFT	include/ssv6200_aux.h	3293;"	d
+START_BYTE_VALUE_SZ	include/ssv6200_aux.h	3295;"	d
+START_IQK	smac/hal/ssv6006c/turismo_common.h	3442;"	d
+START_PADPD	smac/hal/ssv6006c/turismo_common.h	3218;"	d
+START_READ_CRYPTO_DATA	smac/dev.h	1106;"	d
+START_READ_CRYPTO_DATA	smac/dev.h	1119;"	d
+START_SMART_ICOMM	include/ssv6xxx_common.h	/^    START_SMART_ICOMM,$/;"	e	enum:ssv_smart_icomm_cmd
+START_SMART_ICOMM	smartlink/ssv_smartlink.h	/^    START_SMART_ICOMM,$/;"	e	enum:ssv_smart_icomm_cmd
+START_WRITE_CRYPTO_DATA	smac/dev.h	1098;"	d
+START_WRITE_CRYPTO_DATA	smac/dev.h	1117;"	d
+STAT_CLR_DONE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7104;"	d
+STAT_CLR_DONE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7102;"	d
+STAT_CLR_DONE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7101;"	d
+STAT_CLR_DONE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7103;"	d
+STAT_CLR_DONE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7105;"	d
+STAT_CLR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7099;"	d
+STAT_CLR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7097;"	d
+STAT_CLR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7096;"	d
+STAT_CLR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7098;"	d
+STAT_CLR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7100;"	d
+STAT_ENABLE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7084;"	d
+STAT_ENABLE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7082;"	d
+STAT_ENABLE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7081;"	d
+STAT_ENABLE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7083;"	d
+STAT_ENABLE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7085;"	d
+STAT_EN_MB_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7054;"	d
+STAT_EN_MB_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7052;"	d
+STAT_EN_MB_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7051;"	d
+STAT_EN_MB_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7053;"	d
+STAT_EN_MB_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7055;"	d
+STAT_FINISH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7069;"	d
+STAT_FINISH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7067;"	d
+STAT_FINISH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7066;"	d
+STAT_FINISH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7068;"	d
+STAT_FINISH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7070;"	d
+STAT_FREEZE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7094;"	d
+STAT_FREEZE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7092;"	d
+STAT_FREEZE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7091;"	d
+STAT_FREEZE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7093;"	d
+STAT_FREEZE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7095;"	d
+STAT_FSM_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7079;"	d
+STAT_FSM_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7077;"	d
+STAT_FSM_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7076;"	d
+STAT_FSM_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7078;"	d
+STAT_FSM_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7080;"	d
+STAT_MB_TARGET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7059;"	d
+STAT_MB_TARGET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7057;"	d
+STAT_MB_TARGET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7056;"	d
+STAT_MB_TARGET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7058;"	d
+STAT_MB_TARGET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7060;"	d
+STAT_PKT_ID_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7074;"	d
+STAT_PKT_ID_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7072;"	d
+STAT_PKT_ID_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7071;"	d
+STAT_PKT_ID_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7073;"	d
+STAT_PKT_ID_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7075;"	d
+STAT_UNEXPECT_WSID_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7064;"	d
+STAT_UNEXPECT_WSID_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7062;"	d
+STAT_UNEXPECT_WSID_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7061;"	d
+STAT_UNEXPECT_WSID_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7063;"	d
+STAT_UNEXPECT_WSID_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7065;"	d
+STAT_WSID_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7089;"	d
+STAT_WSID_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7087;"	d
+STAT_WSID_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7086;"	d
+STAT_WSID_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7088;"	d
+STAT_WSID_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7090;"	d
+STA_FLAG_AMPDU	smac/dev.h	703;"	d
+STA_FLAG_AMPDU_RX	smac/dev.h	705;"	d
+STA_FLAG_ENCRYPT	smac/dev.h	704;"	d
+STA_FLAG_QOS	smac/dev.h	702;"	d
+STA_FLAG_VALID	smac/dev.h	701;"	d
+STA_MAC1_31_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8994;"	d
+STA_MAC1_31_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8992;"	d
+STA_MAC1_31_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8991;"	d
+STA_MAC1_31_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8993;"	d
+STA_MAC1_31_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8995;"	d
+STA_MAC1_47_32_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8999;"	d
+STA_MAC1_47_32_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8997;"	d
+STA_MAC1_47_32_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8996;"	d
+STA_MAC1_47_32_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8998;"	d
+STA_MAC1_47_32_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9000;"	d
+STA_MAC_31_0_HI	include/ssv6200_aux.h	9189;"	d
+STA_MAC_31_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8949;"	d
+STA_MAC_31_0_I_MSK	include/ssv6200_aux.h	9187;"	d
+STA_MAC_31_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8947;"	d
+STA_MAC_31_0_MSK	include/ssv6200_aux.h	9186;"	d
+STA_MAC_31_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8946;"	d
+STA_MAC_31_0_SFT	include/ssv6200_aux.h	9188;"	d
+STA_MAC_31_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8948;"	d
+STA_MAC_31_0_SZ	include/ssv6200_aux.h	9190;"	d
+STA_MAC_31_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8950;"	d
+STA_MAC_47_32_HI	include/ssv6200_aux.h	9194;"	d
+STA_MAC_47_32_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8954;"	d
+STA_MAC_47_32_I_MSK	include/ssv6200_aux.h	9192;"	d
+STA_MAC_47_32_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8952;"	d
+STA_MAC_47_32_MSK	include/ssv6200_aux.h	9191;"	d
+STA_MAC_47_32_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8951;"	d
+STA_MAC_47_32_SFT	include/ssv6200_aux.h	9193;"	d
+STA_MAC_47_32_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8953;"	d
+STA_MAC_47_32_SZ	include/ssv6200_aux.h	9195;"	d
+STA_MAC_47_32_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8955;"	d
+STOP_BIT_HI	include/ssv6200_aux.h	4334;"	d
+STOP_BIT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3439;"	d
+STOP_BIT_I_MSK	include/ssv6200_aux.h	4332;"	d
+STOP_BIT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3437;"	d
+STOP_BIT_MSK	include/ssv6200_aux.h	4331;"	d
+STOP_BIT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3436;"	d
+STOP_BIT_SFT	include/ssv6200_aux.h	4333;"	d
+STOP_BIT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3438;"	d
+STOP_BIT_SZ	include/ssv6200_aux.h	4335;"	d
+STOP_BIT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3440;"	d
+STOP_MBOX_HI	include/ssv6200_aux.h	11694;"	d
+STOP_MBOX_IN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33279;"	d
+STOP_MBOX_IN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33277;"	d
+STOP_MBOX_IN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33276;"	d
+STOP_MBOX_IN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33278;"	d
+STOP_MBOX_IN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33280;"	d
+STOP_MBOX_I_MSK	include/ssv6200_aux.h	11692;"	d
+STOP_MBOX_MSK	include/ssv6200_aux.h	11691;"	d
+STOP_MBOX_OUT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33274;"	d
+STOP_MBOX_OUT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33272;"	d
+STOP_MBOX_OUT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33271;"	d
+STOP_MBOX_OUT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33273;"	d
+STOP_MBOX_OUT_SUCCESS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33359;"	d
+STOP_MBOX_OUT_SUCCESS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33357;"	d
+STOP_MBOX_OUT_SUCCESS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33356;"	d
+STOP_MBOX_OUT_SUCCESS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33358;"	d
+STOP_MBOX_OUT_SUCCESS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33360;"	d
+STOP_MBOX_OUT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33275;"	d
+STOP_MBOX_SFT	include/ssv6200_aux.h	11693;"	d
+STOP_MBOX_SZ	include/ssv6200_aux.h	11695;"	d
+STOP_SMART_ICOMM	include/ssv6xxx_common.h	/^    STOP_SMART_ICOMM,$/;"	e	enum:ssv_smart_icomm_cmd
+STOP_SMART_ICOMM	smartlink/ssv_smartlink.h	/^    STOP_SMART_ICOMM,$/;"	e	enum:ssv_smart_icomm_cmd
+STRAP0_HI	include/ssv6200_aux.h	1264;"	d
+STRAP0_I_MSK	include/ssv6200_aux.h	1262;"	d
+STRAP0_MSK	include/ssv6200_aux.h	1261;"	d
+STRAP0_SFT	include/ssv6200_aux.h	1263;"	d
+STRAP0_SZ	include/ssv6200_aux.h	1265;"	d
+STRAP1_HI	include/ssv6200_aux.h	1444;"	d
+STRAP1_I_MSK	include/ssv6200_aux.h	1442;"	d
+STRAP1_MSK	include/ssv6200_aux.h	1441;"	d
+STRAP1_SFT	include/ssv6200_aux.h	1443;"	d
+STRAP1_SZ	include/ssv6200_aux.h	1445;"	d
+STRAP2_HI	include/ssv6200_aux.h	2819;"	d
+STRAP2_I_MSK	include/ssv6200_aux.h	2817;"	d
+STRAP2_MSK	include/ssv6200_aux.h	2816;"	d
+STRAP2_SFT	include/ssv6200_aux.h	2818;"	d
+STRAP2_SZ	include/ssv6200_aux.h	2820;"	d
+STRAP3_HI	include/ssv6200_aux.h	1309;"	d
+STRAP3_I_MSK	include/ssv6200_aux.h	1307;"	d
+STRAP3_MSK	include/ssv6200_aux.h	1306;"	d
+STRAP3_SFT	include/ssv6200_aux.h	1308;"	d
+STRAP3_SZ	include/ssv6200_aux.h	1310;"	d
+STR_BANK_SSV6200	include/ssv6200_reg_sim.h	/^static const char* STR_BANK_SSV6200[] = {$/;"	v
+STR_BANK_SSV6200	smac/hal/ssv6006c/ssv6006C_reg_sim.h	/^static const char* STR_BANK_SSV6200[] = {$/;"	v
+SUMMARY_TYPHOST_INT_MAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4389;"	d
+SUMMARY_TYPHOST_INT_MAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4387;"	d
+SUMMARY_TYPHOST_INT_MAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4386;"	d
+SUMMARY_TYPHOST_INT_MAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4388;"	d
+SUMMARY_TYPHOST_INT_MAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4390;"	d
+SUMMARY_TYPMCU_INT_MAP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4454;"	d
+SUMMARY_TYPMCU_INT_MAP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4452;"	d
+SUMMARY_TYPMCU_INT_MAP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4451;"	d
+SUMMARY_TYPMCU_INT_MAP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4453;"	d
+SUMMARY_TYPMCU_INT_MAP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4455;"	d
+SUPPORTED_FILTERS	smac/dev.c	4116;"	d	file:
+SUPPORTED_FILTERS	smac/dev.c	4126;"	d	file:
+SUPPORT_BLOCK_GAP_INTERRUPT_HI	include/ssv6200_aux.h	3704;"	d
+SUPPORT_BLOCK_GAP_INTERRUPT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2829;"	d
+SUPPORT_BLOCK_GAP_INTERRUPT_I_MSK	include/ssv6200_aux.h	3702;"	d
+SUPPORT_BLOCK_GAP_INTERRUPT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2827;"	d
+SUPPORT_BLOCK_GAP_INTERRUPT_MSK	include/ssv6200_aux.h	3701;"	d
+SUPPORT_BLOCK_GAP_INTERRUPT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2826;"	d
+SUPPORT_BLOCK_GAP_INTERRUPT_SFT	include/ssv6200_aux.h	3703;"	d
+SUPPORT_BLOCK_GAP_INTERRUPT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2828;"	d
+SUPPORT_BLOCK_GAP_INTERRUPT_SZ	include/ssv6200_aux.h	3705;"	d
+SUPPORT_BLOCK_GAP_INTERRUPT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2830;"	d
+SUPPORT_BUS_CONTROL_HI	include/ssv6200_aux.h	3699;"	d
+SUPPORT_BUS_CONTROL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2824;"	d
+SUPPORT_BUS_CONTROL_I_MSK	include/ssv6200_aux.h	3697;"	d
+SUPPORT_BUS_CONTROL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2822;"	d
+SUPPORT_BUS_CONTROL_MSK	include/ssv6200_aux.h	3696;"	d
+SUPPORT_BUS_CONTROL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2821;"	d
+SUPPORT_BUS_CONTROL_SFT	include/ssv6200_aux.h	3698;"	d
+SUPPORT_BUS_CONTROL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2823;"	d
+SUPPORT_BUS_CONTROL_SZ	include/ssv6200_aux.h	3700;"	d
+SUPPORT_BUS_CONTROL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2825;"	d
+SUPPORT_DIRECT_COMMAND_SDIO_HI	include/ssv6200_aux.h	3684;"	d
+SUPPORT_DIRECT_COMMAND_SDIO_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2809;"	d
+SUPPORT_DIRECT_COMMAND_SDIO_I_MSK	include/ssv6200_aux.h	3682;"	d
+SUPPORT_DIRECT_COMMAND_SDIO_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2807;"	d
+SUPPORT_DIRECT_COMMAND_SDIO_MSK	include/ssv6200_aux.h	3681;"	d
+SUPPORT_DIRECT_COMMAND_SDIO_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2806;"	d
+SUPPORT_DIRECT_COMMAND_SDIO_SFT	include/ssv6200_aux.h	3683;"	d
+SUPPORT_DIRECT_COMMAND_SDIO_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2808;"	d
+SUPPORT_DIRECT_COMMAND_SDIO_SZ	include/ssv6200_aux.h	3685;"	d
+SUPPORT_DIRECT_COMMAND_SDIO_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2810;"	d
+SUPPORT_HIGH_SPEED_HI	include/ssv6200_aux.h	3729;"	d
+SUPPORT_HIGH_SPEED_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2864;"	d
+SUPPORT_HIGH_SPEED_I_MSK	include/ssv6200_aux.h	3727;"	d
+SUPPORT_HIGH_SPEED_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2862;"	d
+SUPPORT_HIGH_SPEED_MSK	include/ssv6200_aux.h	3726;"	d
+SUPPORT_HIGH_SPEED_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2861;"	d
+SUPPORT_HIGH_SPEED_SFT	include/ssv6200_aux.h	3728;"	d
+SUPPORT_HIGH_SPEED_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2863;"	d
+SUPPORT_HIGH_SPEED_SZ	include/ssv6200_aux.h	3730;"	d
+SUPPORT_HIGH_SPEED_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2865;"	d
+SUPPORT_MULTIPLE_BLOCK_TRANSFER_HI	include/ssv6200_aux.h	3689;"	d
+SUPPORT_MULTIPLE_BLOCK_TRANSFER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2814;"	d
+SUPPORT_MULTIPLE_BLOCK_TRANSFER_I_MSK	include/ssv6200_aux.h	3687;"	d
+SUPPORT_MULTIPLE_BLOCK_TRANSFER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2812;"	d
+SUPPORT_MULTIPLE_BLOCK_TRANSFER_MSK	include/ssv6200_aux.h	3686;"	d
+SUPPORT_MULTIPLE_BLOCK_TRANSFER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2811;"	d
+SUPPORT_MULTIPLE_BLOCK_TRANSFER_SFT	include/ssv6200_aux.h	3688;"	d
+SUPPORT_MULTIPLE_BLOCK_TRANSFER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2813;"	d
+SUPPORT_MULTIPLE_BLOCK_TRANSFER_SZ	include/ssv6200_aux.h	3690;"	d
+SUPPORT_MULTIPLE_BLOCK_TRANSFER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2815;"	d
+SUPPORT_READ_WAIT_HI	include/ssv6200_aux.h	3694;"	d
+SUPPORT_READ_WAIT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2819;"	d
+SUPPORT_READ_WAIT_I_MSK	include/ssv6200_aux.h	3692;"	d
+SUPPORT_READ_WAIT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2817;"	d
+SUPPORT_READ_WAIT_MSK	include/ssv6200_aux.h	3691;"	d
+SUPPORT_READ_WAIT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2816;"	d
+SUPPORT_READ_WAIT_SFT	include/ssv6200_aux.h	3693;"	d
+SUPPORT_READ_WAIT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2818;"	d
+SUPPORT_READ_WAIT_SZ	include/ssv6200_aux.h	3695;"	d
+SUPPORT_READ_WAIT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2820;"	d
+SUSPEND_PWR_ON1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1719;"	d
+SUSPEND_PWR_ON1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1717;"	d
+SUSPEND_PWR_ON1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1716;"	d
+SUSPEND_PWR_ON1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1718;"	d
+SUSPEND_PWR_ON1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1720;"	d
+SUSPEND_PWR_ON2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1724;"	d
+SUSPEND_PWR_ON2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1722;"	d
+SUSPEND_PWR_ON2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1721;"	d
+SUSPEND_PWR_ON2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1723;"	d
+SUSPEND_PWR_ON2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1725;"	d
+SUSPEND_PWR_ON3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1729;"	d
+SUSPEND_PWR_ON3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1727;"	d
+SUSPEND_PWR_ON3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1726;"	d
+SUSPEND_PWR_ON3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1728;"	d
+SUSPEND_PWR_ON3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1730;"	d
+SV6155P	include/ssv6xxx_common.h	323;"	d
+SV6155P_IC	smac/hal/ssv6006c/ssv6006_common.c	598;"	d	file:
+SV6156P	include/ssv6xxx_common.h	324;"	d
+SV6156P_IC	smac/hal/ssv6006c/ssv6006_common.c	599;"	d	file:
+SV6255P	include/ssv6xxx_common.h	325;"	d
+SV6255P_IC	smac/hal/ssv6006c/ssv6006_common.c	600;"	d	file:
+SV6256P	include/ssv6xxx_common.h	326;"	d
+SV6256P_IC	smac/hal/ssv6006c/ssv6006_common.c	601;"	d	file:
+SVN_VERSION_HI	include/ssv6200_aux.h	13129;"	d
+SVN_VERSION_HI	smac/hal/ssv6006c/ssv6006C_aux.h	30319;"	d
+SVN_VERSION_I_MSK	include/ssv6200_aux.h	13127;"	d
+SVN_VERSION_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30317;"	d
+SVN_VERSION_MSK	include/ssv6200_aux.h	13126;"	d
+SVN_VERSION_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	30316;"	d
+SVN_VERSION_SFT	include/ssv6200_aux.h	13128;"	d
+SVN_VERSION_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	30318;"	d
+SVN_VERSION_SZ	include/ssv6200_aux.h	13130;"	d
+SVN_VERSION_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	30320;"	d
+SWITCH_2WIRE_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9134;"	d
+SWITCH_2WIRE_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9132;"	d
+SWITCH_2WIRE_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9131;"	d
+SWITCH_2WIRE_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9133;"	d
+SWITCH_2WIRE_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9135;"	d
+SW_BT_TRX_HI	include/ssv6200_aux.h	9319;"	d
+SW_BT_TRX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9109;"	d
+SW_BT_TRX_I_MSK	include/ssv6200_aux.h	9317;"	d
+SW_BT_TRX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9107;"	d
+SW_BT_TRX_MSK	include/ssv6200_aux.h	9316;"	d
+SW_BT_TRX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9106;"	d
+SW_BT_TRX_SFT	include/ssv6200_aux.h	9318;"	d
+SW_BT_TRX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9108;"	d
+SW_BT_TRX_SZ	include/ssv6200_aux.h	9320;"	d
+SW_BT_TRX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9110;"	d
+SW_MANUAL_EN_HI	include/ssv6200_aux.h	9304;"	d
+SW_MANUAL_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9094;"	d
+SW_MANUAL_EN_I_MSK	include/ssv6200_aux.h	9302;"	d
+SW_MANUAL_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9092;"	d
+SW_MANUAL_EN_MSK	include/ssv6200_aux.h	9301;"	d
+SW_MANUAL_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9091;"	d
+SW_MANUAL_EN_SFT	include/ssv6200_aux.h	9303;"	d
+SW_MANUAL_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9093;"	d
+SW_MANUAL_EN_SZ	include/ssv6200_aux.h	9305;"	d
+SW_MANUAL_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9095;"	d
+SW_WL_RX_HI	include/ssv6200_aux.h	9314;"	d
+SW_WL_RX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9104;"	d
+SW_WL_RX_I_MSK	include/ssv6200_aux.h	9312;"	d
+SW_WL_RX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9102;"	d
+SW_WL_RX_MSK	include/ssv6200_aux.h	9311;"	d
+SW_WL_RX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9101;"	d
+SW_WL_RX_SFT	include/ssv6200_aux.h	9313;"	d
+SW_WL_RX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9103;"	d
+SW_WL_RX_SZ	include/ssv6200_aux.h	9315;"	d
+SW_WL_RX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9105;"	d
+SW_WL_TX_HI	include/ssv6200_aux.h	9309;"	d
+SW_WL_TX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9099;"	d
+SW_WL_TX_I_MSK	include/ssv6200_aux.h	9307;"	d
+SW_WL_TX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9097;"	d
+SW_WL_TX_MSK	include/ssv6200_aux.h	9306;"	d
+SW_WL_TX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9096;"	d
+SW_WL_TX_SFT	include/ssv6200_aux.h	9308;"	d
+SW_WL_TX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9098;"	d
+SW_WL_TX_SZ	include/ssv6200_aux.h	9310;"	d
+SW_WL_TX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9100;"	d
+SYMBOL_TIME	smac/dev.h	168;"	d
+SYMBOL_TIME_HALFGI	smac/dev.h	169;"	d
+SYSCTRL_CMD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1399;"	d
+SYSCTRL_CMD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1397;"	d
+SYSCTRL_CMD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1396;"	d
+SYSCTRL_CMD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1398;"	d
+SYSCTRL_CMD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1400;"	d
+SYSTEM_INT_HI	include/ssv6200_aux.h	3259;"	d
+SYSTEM_INT_I_MSK	include/ssv6200_aux.h	3257;"	d
+SYSTEM_INT_MSK	include/ssv6200_aux.h	3256;"	d
+SYSTEM_INT_SFT	include/ssv6200_aux.h	3258;"	d
+SYSTEM_INT_SZ	include/ssv6200_aux.h	3260;"	d
+SYS_ALL_RST_HI	include/ssv6200_aux.h	124;"	d
+SYS_ALL_RST_I_MSK	include/ssv6200_aux.h	122;"	d
+SYS_ALL_RST_MSK	include/ssv6200_aux.h	121;"	d
+SYS_ALL_RST_SFT	include/ssv6200_aux.h	123;"	d
+SYS_ALL_RST_SZ	include/ssv6200_aux.h	125;"	d
+SYS_CLK_EN_HI	include/ssv6200_aux.h	189;"	d
+SYS_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1139;"	d
+SYS_CLK_EN_I_MSK	include/ssv6200_aux.h	187;"	d
+SYS_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1137;"	d
+SYS_CLK_EN_MSK	include/ssv6200_aux.h	186;"	d
+SYS_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1136;"	d
+SYS_CLK_EN_SFT	include/ssv6200_aux.h	188;"	d
+SYS_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1138;"	d
+SYS_CLK_EN_SZ	include/ssv6200_aux.h	190;"	d
+SYS_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1140;"	d
+SYS_CLOCK_STATE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1354;"	d
+SYS_CLOCK_STATE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1352;"	d
+SYS_CLOCK_STATE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1351;"	d
+SYS_CLOCK_STATE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1353;"	d
+SYS_CLOCK_STATE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1355;"	d
+SYS_DPLL_ON_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1414;"	d
+SYS_DPLL_ON_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1412;"	d
+SYS_DPLL_ON_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1411;"	d
+SYS_DPLL_ON_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1413;"	d
+SYS_DPLL_ON_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1415;"	d
+SYS_N10_IVB_VAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1634;"	d
+SYS_N10_IVB_VAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1632;"	d
+SYS_N10_IVB_VAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1631;"	d
+SYS_N10_IVB_VAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1633;"	d
+SYS_N10_IVB_VAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1635;"	d
+SYS_PMU_MODE_TRAN_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1649;"	d
+SYS_PMU_MODE_TRAN_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1647;"	d
+SYS_PMU_MODE_TRAN_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1646;"	d
+SYS_PMU_MODE_TRAN_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1648;"	d
+SYS_PMU_MODE_TRAN_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1650;"	d
+SYS_REG_BANK_SIZE	include/ssv6200_reg.h	65;"	d
+SYS_REG_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	82;"	d
+SYS_REG_BASE	hwif/hwif.h	20;"	d
+SYS_REG_BASE	include/ssv6200_reg.h	16;"	d
+SYS_REG_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	21;"	d
+SYS_RST_INT_HI	include/ssv6200_aux.h	5084;"	d
+SYS_RST_INT_I_MSK	include/ssv6200_aux.h	5082;"	d
+SYS_RST_INT_MSK	include/ssv6200_aux.h	5081;"	d
+SYS_RST_INT_SFT	include/ssv6200_aux.h	5083;"	d
+SYS_RST_INT_SZ	include/ssv6200_aux.h	5085;"	d
+SYS_UTILS_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	106;"	d
+SYS_UTILS_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	45;"	d
+SYS_WDOG_ENA_HI	include/ssv6200_aux.h	854;"	d
+SYS_WDOG_ENA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2099;"	d
+SYS_WDOG_ENA_I_MSK	include/ssv6200_aux.h	852;"	d
+SYS_WDOG_ENA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2097;"	d
+SYS_WDOG_ENA_MSK	include/ssv6200_aux.h	851;"	d
+SYS_WDOG_ENA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2096;"	d
+SYS_WDOG_ENA_SFT	include/ssv6200_aux.h	853;"	d
+SYS_WDOG_ENA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2098;"	d
+SYS_WDOG_ENA_SZ	include/ssv6200_aux.h	855;"	d
+SYS_WDOG_ENA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2100;"	d
+SYS_WDT_INT_CNT_OFS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2089;"	d
+SYS_WDT_INT_CNT_OFS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2087;"	d
+SYS_WDT_INT_CNT_OFS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2086;"	d
+SYS_WDT_INT_CNT_OFS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2088;"	d
+SYS_WDT_INT_CNT_OFS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2090;"	d
+SYS_WDT_REG_BANK_SIZE	include/ssv6200_reg.h	76;"	d
+SYS_WDT_REG_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	93;"	d
+SYS_WDT_REG_BASE	include/ssv6200_reg.h	27;"	d
+SYS_WDT_REG_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	32;"	d
+SYS_WDT_STATUS_HI	include/ssv6200_aux.h	849;"	d
+SYS_WDT_STATUS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2094;"	d
+SYS_WDT_STATUS_I_MSK	include/ssv6200_aux.h	847;"	d
+SYS_WDT_STATUS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2092;"	d
+SYS_WDT_STATUS_MSK	include/ssv6200_aux.h	846;"	d
+SYS_WDT_STATUS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2091;"	d
+SYS_WDT_STATUS_SFT	include/ssv6200_aux.h	848;"	d
+SYS_WDT_STATUS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2093;"	d
+SYS_WDT_STATUS_SZ	include/ssv6200_aux.h	850;"	d
+SYS_WDT_STATUS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2095;"	d
+SYS_WDT_TIME_CNT_HI	include/ssv6200_aux.h	844;"	d
+SYS_WDT_TIME_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2084;"	d
+SYS_WDT_TIME_CNT_I_MSK	include/ssv6200_aux.h	842;"	d
+SYS_WDT_TIME_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2082;"	d
+SYS_WDT_TIME_CNT_MSK	include/ssv6200_aux.h	841;"	d
+SYS_WDT_TIME_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2081;"	d
+SYS_WDT_TIME_CNT_SFT	include/ssv6200_aux.h	843;"	d
+SYS_WDT_TIME_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2083;"	d
+SYS_WDT_TIME_CNT_SZ	include/ssv6200_aux.h	845;"	d
+SYS_WDT_TIME_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2085;"	d
+SYS_XOSC_ON_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1409;"	d
+SYS_XOSC_ON_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1407;"	d
+SYS_XOSC_ON_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1406;"	d
+SYS_XOSC_ON_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1408;"	d
+SYS_XOSC_ON_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1410;"	d
+S_Box	smac/wapi_sms4.c	/^static const u8 S_Box[] = {$/;"	v	file:
+S_XState	smac/wapi_sms4.c	/^static const u8 S_XState[] = {$/;"	v	file:
+Sbox	smac/sec_tkip.c	/^static const u16 Sbox[256] = {$/;"	v	file:
+TAG_INTERLEAVE_MD_HI	include/ssv6200_aux.h	17664;"	d
+TAG_INTERLEAVE_MD_I_MSK	include/ssv6200_aux.h	17662;"	d
+TAG_INTERLEAVE_MD_MSK	include/ssv6200_aux.h	17661;"	d
+TAG_INTERLEAVE_MD_SFT	include/ssv6200_aux.h	17663;"	d
+TAG_INTERLEAVE_MD_SZ	include/ssv6200_aux.h	17665;"	d
+TAG_SW_RST_N_HI	include/ssv6200_aux.h	17714;"	d
+TAG_SW_RST_N_I_MSK	include/ssv6200_aux.h	17712;"	d
+TAG_SW_RST_N_MSK	include/ssv6200_aux.h	17711;"	d
+TAG_SW_RST_N_SFT	include/ssv6200_aux.h	17713;"	d
+TAG_SW_RST_N_SZ	include/ssv6200_aux.h	17715;"	d
+TBLNEQ_MNGPKT_INT_IRQ_HI	include/ssv6200_aux.h	5064;"	d
+TBLNEQ_MNGPKT_INT_IRQ_I_MSK	include/ssv6200_aux.h	5062;"	d
+TBLNEQ_MNGPKT_INT_IRQ_MSK	include/ssv6200_aux.h	5061;"	d
+TBLNEQ_MNGPKT_INT_IRQ_SD_HI	include/ssv6200_aux.h	5409;"	d
+TBLNEQ_MNGPKT_INT_IRQ_SD_I_MSK	include/ssv6200_aux.h	5407;"	d
+TBLNEQ_MNGPKT_INT_IRQ_SD_MSK	include/ssv6200_aux.h	5406;"	d
+TBLNEQ_MNGPKT_INT_IRQ_SD_SFT	include/ssv6200_aux.h	5408;"	d
+TBLNEQ_MNGPKT_INT_IRQ_SD_SZ	include/ssv6200_aux.h	5410;"	d
+TBLNEQ_MNGPKT_INT_IRQ_SFT	include/ssv6200_aux.h	5063;"	d
+TBLNEQ_MNGPKT_INT_IRQ_SZ	include/ssv6200_aux.h	5065;"	d
+TB_ADR_SEL_HI	include/ssv6200_aux.h	424;"	d
+TB_ADR_SEL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1379;"	d
+TB_ADR_SEL_I_MSK	include/ssv6200_aux.h	422;"	d
+TB_ADR_SEL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1377;"	d
+TB_ADR_SEL_MSK	include/ssv6200_aux.h	421;"	d
+TB_ADR_SEL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1376;"	d
+TB_ADR_SEL_SFT	include/ssv6200_aux.h	423;"	d
+TB_ADR_SEL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1378;"	d
+TB_ADR_SEL_SZ	include/ssv6200_aux.h	425;"	d
+TB_ADR_SEL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1380;"	d
+TB_CS_HI	include/ssv6200_aux.h	429;"	d
+TB_CS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1384;"	d
+TB_CS_I_MSK	include/ssv6200_aux.h	427;"	d
+TB_CS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1382;"	d
+TB_CS_MSK	include/ssv6200_aux.h	426;"	d
+TB_CS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1381;"	d
+TB_CS_SFT	include/ssv6200_aux.h	428;"	d
+TB_CS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1383;"	d
+TB_CS_SZ	include/ssv6200_aux.h	430;"	d
+TB_CS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1385;"	d
+TB_RDATA_HI	include/ssv6200_aux.h	434;"	d
+TB_RDATA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1389;"	d
+TB_RDATA_I_MSK	include/ssv6200_aux.h	432;"	d
+TB_RDATA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1387;"	d
+TB_RDATA_MSK	include/ssv6200_aux.h	431;"	d
+TB_RDATA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1386;"	d
+TB_RDATA_SFT	include/ssv6200_aux.h	433;"	d
+TB_RDATA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1388;"	d
+TB_RDATA_SZ	include/ssv6200_aux.h	435;"	d
+TB_RDATA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1390;"	d
+TDIFS	smac/ssv_rc_common.h	21;"	d
+TEST_10_ID_HI	include/ssv6200_aux.h	1774;"	d
+TEST_10_ID_I_MSK	include/ssv6200_aux.h	1772;"	d
+TEST_10_ID_MSK	include/ssv6200_aux.h	1771;"	d
+TEST_10_ID_SFT	include/ssv6200_aux.h	1773;"	d
+TEST_10_ID_SZ	include/ssv6200_aux.h	1775;"	d
+TEST_11_ID_HI	include/ssv6200_aux.h	1814;"	d
+TEST_11_ID_I_MSK	include/ssv6200_aux.h	1812;"	d
+TEST_11_ID_MSK	include/ssv6200_aux.h	1811;"	d
+TEST_11_ID_SFT	include/ssv6200_aux.h	1813;"	d
+TEST_11_ID_SZ	include/ssv6200_aux.h	1815;"	d
+TEST_12_ID_HI	include/ssv6200_aux.h	1854;"	d
+TEST_12_ID_I_MSK	include/ssv6200_aux.h	1852;"	d
+TEST_12_ID_MSK	include/ssv6200_aux.h	1851;"	d
+TEST_12_ID_SFT	include/ssv6200_aux.h	1853;"	d
+TEST_12_ID_SZ	include/ssv6200_aux.h	1855;"	d
+TEST_13_ID_HI	include/ssv6200_aux.h	1894;"	d
+TEST_13_ID_I_MSK	include/ssv6200_aux.h	1892;"	d
+TEST_13_ID_MSK	include/ssv6200_aux.h	1891;"	d
+TEST_13_ID_SFT	include/ssv6200_aux.h	1893;"	d
+TEST_13_ID_SZ	include/ssv6200_aux.h	1895;"	d
+TEST_14_ID_HI	include/ssv6200_aux.h	1934;"	d
+TEST_14_ID_I_MSK	include/ssv6200_aux.h	1932;"	d
+TEST_14_ID_MSK	include/ssv6200_aux.h	1931;"	d
+TEST_14_ID_SFT	include/ssv6200_aux.h	1933;"	d
+TEST_14_ID_SZ	include/ssv6200_aux.h	1935;"	d
+TEST_15_ID_HI	include/ssv6200_aux.h	1974;"	d
+TEST_15_ID_I_MSK	include/ssv6200_aux.h	1972;"	d
+TEST_15_ID_MSK	include/ssv6200_aux.h	1971;"	d
+TEST_15_ID_SFT	include/ssv6200_aux.h	1973;"	d
+TEST_15_ID_SZ	include/ssv6200_aux.h	1975;"	d
+TEST_16_ID_HI	include/ssv6200_aux.h	2419;"	d
+TEST_16_ID_I_MSK	include/ssv6200_aux.h	2417;"	d
+TEST_16_ID_MSK	include/ssv6200_aux.h	2416;"	d
+TEST_16_ID_SFT	include/ssv6200_aux.h	2418;"	d
+TEST_16_ID_SZ	include/ssv6200_aux.h	2420;"	d
+TEST_17_ID_HI	include/ssv6200_aux.h	2459;"	d
+TEST_17_ID_I_MSK	include/ssv6200_aux.h	2457;"	d
+TEST_17_ID_MSK	include/ssv6200_aux.h	2456;"	d
+TEST_17_ID_SFT	include/ssv6200_aux.h	2458;"	d
+TEST_17_ID_SZ	include/ssv6200_aux.h	2460;"	d
+TEST_18_ID_HI	include/ssv6200_aux.h	2499;"	d
+TEST_18_ID_I_MSK	include/ssv6200_aux.h	2497;"	d
+TEST_18_ID_MSK	include/ssv6200_aux.h	2496;"	d
+TEST_18_ID_SFT	include/ssv6200_aux.h	2498;"	d
+TEST_18_ID_SZ	include/ssv6200_aux.h	2500;"	d
+TEST_19_ID_HI	include/ssv6200_aux.h	2539;"	d
+TEST_19_ID_I_MSK	include/ssv6200_aux.h	2537;"	d
+TEST_19_ID_MSK	include/ssv6200_aux.h	2536;"	d
+TEST_19_ID_SFT	include/ssv6200_aux.h	2538;"	d
+TEST_19_ID_SZ	include/ssv6200_aux.h	2540;"	d
+TEST_1_ID_HI	include/ssv6200_aux.h	1064;"	d
+TEST_1_ID_I_MSK	include/ssv6200_aux.h	1062;"	d
+TEST_1_ID_MSK	include/ssv6200_aux.h	1061;"	d
+TEST_1_ID_SFT	include/ssv6200_aux.h	1063;"	d
+TEST_1_ID_SZ	include/ssv6200_aux.h	1065;"	d
+TEST_20_ID_HI	include/ssv6200_aux.h	2579;"	d
+TEST_20_ID_I_MSK	include/ssv6200_aux.h	2577;"	d
+TEST_20_ID_MSK	include/ssv6200_aux.h	2576;"	d
+TEST_20_ID_SFT	include/ssv6200_aux.h	2578;"	d
+TEST_20_ID_SZ	include/ssv6200_aux.h	2580;"	d
+TEST_2_ID_HI	include/ssv6200_aux.h	1104;"	d
+TEST_2_ID_I_MSK	include/ssv6200_aux.h	1102;"	d
+TEST_2_ID_MSK	include/ssv6200_aux.h	1101;"	d
+TEST_2_ID_SFT	include/ssv6200_aux.h	1103;"	d
+TEST_2_ID_SZ	include/ssv6200_aux.h	1105;"	d
+TEST_3_ID_HI	include/ssv6200_aux.h	1144;"	d
+TEST_3_ID_I_MSK	include/ssv6200_aux.h	1142;"	d
+TEST_3_ID_MSK	include/ssv6200_aux.h	1141;"	d
+TEST_3_ID_SFT	include/ssv6200_aux.h	1143;"	d
+TEST_3_ID_SZ	include/ssv6200_aux.h	1145;"	d
+TEST_4_ID_HI	include/ssv6200_aux.h	1184;"	d
+TEST_4_ID_I_MSK	include/ssv6200_aux.h	1182;"	d
+TEST_4_ID_MSK	include/ssv6200_aux.h	1181;"	d
+TEST_4_ID_SFT	include/ssv6200_aux.h	1183;"	d
+TEST_4_ID_SZ	include/ssv6200_aux.h	1185;"	d
+TEST_6_ID_HI	include/ssv6200_aux.h	1614;"	d
+TEST_6_ID_I_MSK	include/ssv6200_aux.h	1612;"	d
+TEST_6_ID_MSK	include/ssv6200_aux.h	1611;"	d
+TEST_6_ID_SFT	include/ssv6200_aux.h	1613;"	d
+TEST_6_ID_SZ	include/ssv6200_aux.h	1615;"	d
+TEST_7_ID_HI	include/ssv6200_aux.h	1654;"	d
+TEST_7_ID_I_MSK	include/ssv6200_aux.h	1652;"	d
+TEST_7_ID_MSK	include/ssv6200_aux.h	1651;"	d
+TEST_7_ID_SFT	include/ssv6200_aux.h	1653;"	d
+TEST_7_ID_SZ	include/ssv6200_aux.h	1655;"	d
+TEST_8_ID_HI	include/ssv6200_aux.h	1694;"	d
+TEST_8_ID_I_MSK	include/ssv6200_aux.h	1692;"	d
+TEST_8_ID_MSK	include/ssv6200_aux.h	1691;"	d
+TEST_8_ID_SFT	include/ssv6200_aux.h	1693;"	d
+TEST_8_ID_SZ	include/ssv6200_aux.h	1695;"	d
+TEST_9_ID_HI	include/ssv6200_aux.h	1734;"	d
+TEST_9_ID_I_MSK	include/ssv6200_aux.h	1732;"	d
+TEST_9_ID_MSK	include/ssv6200_aux.h	1731;"	d
+TEST_9_ID_SFT	include/ssv6200_aux.h	1733;"	d
+TEST_9_ID_SZ	include/ssv6200_aux.h	1735;"	d
+TEST_MODE0_HI	include/ssv6200_aux.h	574;"	d
+TEST_MODE0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1524;"	d
+TEST_MODE0_I_MSK	include/ssv6200_aux.h	572;"	d
+TEST_MODE0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1522;"	d
+TEST_MODE0_MSK	include/ssv6200_aux.h	571;"	d
+TEST_MODE0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1521;"	d
+TEST_MODE0_SFT	include/ssv6200_aux.h	573;"	d
+TEST_MODE0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1523;"	d
+TEST_MODE0_SZ	include/ssv6200_aux.h	575;"	d
+TEST_MODE0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1525;"	d
+TEST_MODE1_HI	include/ssv6200_aux.h	579;"	d
+TEST_MODE1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1529;"	d
+TEST_MODE1_I_MSK	include/ssv6200_aux.h	577;"	d
+TEST_MODE1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1527;"	d
+TEST_MODE1_MSK	include/ssv6200_aux.h	576;"	d
+TEST_MODE1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1526;"	d
+TEST_MODE1_SFT	include/ssv6200_aux.h	578;"	d
+TEST_MODE1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1528;"	d
+TEST_MODE1_SZ	include/ssv6200_aux.h	580;"	d
+TEST_MODE1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1530;"	d
+TEST_MODE2_HI	include/ssv6200_aux.h	584;"	d
+TEST_MODE2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1534;"	d
+TEST_MODE2_I_MSK	include/ssv6200_aux.h	582;"	d
+TEST_MODE2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1532;"	d
+TEST_MODE2_MSK	include/ssv6200_aux.h	581;"	d
+TEST_MODE2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1531;"	d
+TEST_MODE2_SFT	include/ssv6200_aux.h	583;"	d
+TEST_MODE2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1533;"	d
+TEST_MODE2_SZ	include/ssv6200_aux.h	585;"	d
+TEST_MODE2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1535;"	d
+TEST_MODE3_HI	include/ssv6200_aux.h	589;"	d
+TEST_MODE3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1539;"	d
+TEST_MODE3_I_MSK	include/ssv6200_aux.h	587;"	d
+TEST_MODE3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1537;"	d
+TEST_MODE3_MSK	include/ssv6200_aux.h	586;"	d
+TEST_MODE3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1536;"	d
+TEST_MODE3_SFT	include/ssv6200_aux.h	588;"	d
+TEST_MODE3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1538;"	d
+TEST_MODE3_SZ	include/ssv6200_aux.h	590;"	d
+TEST_MODE3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1540;"	d
+TEST_MODE4_HI	include/ssv6200_aux.h	594;"	d
+TEST_MODE4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1544;"	d
+TEST_MODE4_I_MSK	include/ssv6200_aux.h	592;"	d
+TEST_MODE4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1542;"	d
+TEST_MODE4_MSK	include/ssv6200_aux.h	591;"	d
+TEST_MODE4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1541;"	d
+TEST_MODE4_SFT	include/ssv6200_aux.h	593;"	d
+TEST_MODE4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1543;"	d
+TEST_MODE4_SZ	include/ssv6200_aux.h	595;"	d
+TEST_MODE4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1545;"	d
+TEST_MODE_ALL_HI	include/ssv6200_aux.h	599;"	d
+TEST_MODE_ALL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1549;"	d
+TEST_MODE_ALL_I_MSK	include/ssv6200_aux.h	597;"	d
+TEST_MODE_ALL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1547;"	d
+TEST_MODE_ALL_MSK	include/ssv6200_aux.h	596;"	d
+TEST_MODE_ALL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1546;"	d
+TEST_MODE_ALL_SFT	include/ssv6200_aux.h	598;"	d
+TEST_MODE_ALL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1548;"	d
+TEST_MODE_ALL_SZ	include/ssv6200_aux.h	600;"	d
+TEST_MODE_ALL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1550;"	d
+TEXT_BYTES	smac/wapi_sms4.c	30;"	d	file:
+TEXT_LEN	smac/wapi_sms4.c	27;"	d	file:
+TEXT_MULTIPLIER	smac/wapi_sms4.c	33;"	d	file:
+THREE_WIRE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6009;"	d
+THREE_WIRE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6007;"	d
+THREE_WIRE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6006;"	d
+THREE_WIRE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6008;"	d
+THREE_WIRE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6010;"	d
+THR_EMPTY_HI	include/ssv6200_aux.h	4414;"	d
+THR_EMPTY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3524;"	d
+THR_EMPTY_IE_HI	include/ssv6200_aux.h	4269;"	d
+THR_EMPTY_IE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3374;"	d
+THR_EMPTY_IE_I_MSK	include/ssv6200_aux.h	4267;"	d
+THR_EMPTY_IE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3372;"	d
+THR_EMPTY_IE_MSK	include/ssv6200_aux.h	4266;"	d
+THR_EMPTY_IE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3371;"	d
+THR_EMPTY_IE_SFT	include/ssv6200_aux.h	4268;"	d
+THR_EMPTY_IE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3373;"	d
+THR_EMPTY_IE_SZ	include/ssv6200_aux.h	4270;"	d
+THR_EMPTY_IE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3375;"	d
+THR_EMPTY_I_MSK	include/ssv6200_aux.h	4412;"	d
+THR_EMPTY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3522;"	d
+THR_EMPTY_MSK	include/ssv6200_aux.h	4411;"	d
+THR_EMPTY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3521;"	d
+THR_EMPTY_SFT	include/ssv6200_aux.h	4413;"	d
+THR_EMPTY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3523;"	d
+THR_EMPTY_SZ	include/ssv6200_aux.h	4415;"	d
+THR_EMPTY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3525;"	d
+TIP_A_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3689;"	d
+TIP_A_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3687;"	d
+TIP_A_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3686;"	d
+TIP_A_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3688;"	d
+TIP_A_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3690;"	d
+TKIP_HDR_LEN	smac/sec_tkip.c	41;"	d	file:
+TKIP_KEY_LEN	smac/sec.h	26;"	d
+TM0_MS_REG_BANK_SIZE	include/ssv6200_reg.h	71;"	d
+TM0_MS_REG_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	88;"	d
+TM0_MS_REG_BASE	include/ssv6200_reg.h	22;"	d
+TM0_MS_REG_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	27;"	d
+TM0_PRESCALER_USTIMER_LOCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1969;"	d
+TM0_PRESCALER_USTIMER_LOCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1967;"	d
+TM0_PRESCALER_USTIMER_LOCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1966;"	d
+TM0_PRESCALER_USTIMER_LOCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1968;"	d
+TM0_PRESCALER_USTIMER_LOCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1970;"	d
+TM0_TM_CUR_VALUE_HI	include/ssv6200_aux.h	749;"	d
+TM0_TM_CUR_VALUE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1964;"	d
+TM0_TM_CUR_VALUE_I_MSK	include/ssv6200_aux.h	747;"	d
+TM0_TM_CUR_VALUE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1962;"	d
+TM0_TM_CUR_VALUE_MSK	include/ssv6200_aux.h	746;"	d
+TM0_TM_CUR_VALUE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1961;"	d
+TM0_TM_CUR_VALUE_SFT	include/ssv6200_aux.h	748;"	d
+TM0_TM_CUR_VALUE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1963;"	d
+TM0_TM_CUR_VALUE_SZ	include/ssv6200_aux.h	750;"	d
+TM0_TM_CUR_VALUE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1965;"	d
+TM0_TM_INIT_VALUE_HI	include/ssv6200_aux.h	729;"	d
+TM0_TM_INIT_VALUE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1944;"	d
+TM0_TM_INIT_VALUE_I_MSK	include/ssv6200_aux.h	727;"	d
+TM0_TM_INIT_VALUE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1942;"	d
+TM0_TM_INIT_VALUE_MSK	include/ssv6200_aux.h	726;"	d
+TM0_TM_INIT_VALUE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1941;"	d
+TM0_TM_INIT_VALUE_SFT	include/ssv6200_aux.h	728;"	d
+TM0_TM_INIT_VALUE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1943;"	d
+TM0_TM_INIT_VALUE_SZ	include/ssv6200_aux.h	730;"	d
+TM0_TM_INIT_VALUE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1945;"	d
+TM0_TM_INT_MASK_HI	include/ssv6200_aux.h	744;"	d
+TM0_TM_INT_MASK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1959;"	d
+TM0_TM_INT_MASK_I_MSK	include/ssv6200_aux.h	742;"	d
+TM0_TM_INT_MASK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1957;"	d
+TM0_TM_INT_MASK_MSK	include/ssv6200_aux.h	741;"	d
+TM0_TM_INT_MASK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1956;"	d
+TM0_TM_INT_MASK_SFT	include/ssv6200_aux.h	743;"	d
+TM0_TM_INT_MASK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1958;"	d
+TM0_TM_INT_MASK_SZ	include/ssv6200_aux.h	745;"	d
+TM0_TM_INT_MASK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1960;"	d
+TM0_TM_INT_STS_DONE_HI	include/ssv6200_aux.h	739;"	d
+TM0_TM_INT_STS_DONE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1954;"	d
+TM0_TM_INT_STS_DONE_I_MSK	include/ssv6200_aux.h	737;"	d
+TM0_TM_INT_STS_DONE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1952;"	d
+TM0_TM_INT_STS_DONE_MSK	include/ssv6200_aux.h	736;"	d
+TM0_TM_INT_STS_DONE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1951;"	d
+TM0_TM_INT_STS_DONE_SFT	include/ssv6200_aux.h	738;"	d
+TM0_TM_INT_STS_DONE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1953;"	d
+TM0_TM_INT_STS_DONE_SZ	include/ssv6200_aux.h	740;"	d
+TM0_TM_INT_STS_DONE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1955;"	d
+TM0_TM_MODE_HI	include/ssv6200_aux.h	734;"	d
+TM0_TM_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1949;"	d
+TM0_TM_MODE_I_MSK	include/ssv6200_aux.h	732;"	d
+TM0_TM_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1947;"	d
+TM0_TM_MODE_MSK	include/ssv6200_aux.h	731;"	d
+TM0_TM_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1946;"	d
+TM0_TM_MODE_SFT	include/ssv6200_aux.h	733;"	d
+TM0_TM_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1948;"	d
+TM0_TM_MODE_SZ	include/ssv6200_aux.h	735;"	d
+TM0_TM_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1950;"	d
+TM1_MS_REG_BANK_SIZE	include/ssv6200_reg.h	72;"	d
+TM1_MS_REG_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	89;"	d
+TM1_MS_REG_BASE	include/ssv6200_reg.h	23;"	d
+TM1_MS_REG_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	28;"	d
+TM1_PRESCALER_USTIMER_LOCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1999;"	d
+TM1_PRESCALER_USTIMER_LOCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1997;"	d
+TM1_PRESCALER_USTIMER_LOCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1996;"	d
+TM1_PRESCALER_USTIMER_LOCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1998;"	d
+TM1_PRESCALER_USTIMER_LOCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2000;"	d
+TM1_TM_CUR_VALUE_HI	include/ssv6200_aux.h	774;"	d
+TM1_TM_CUR_VALUE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1994;"	d
+TM1_TM_CUR_VALUE_I_MSK	include/ssv6200_aux.h	772;"	d
+TM1_TM_CUR_VALUE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1992;"	d
+TM1_TM_CUR_VALUE_MSK	include/ssv6200_aux.h	771;"	d
+TM1_TM_CUR_VALUE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1991;"	d
+TM1_TM_CUR_VALUE_SFT	include/ssv6200_aux.h	773;"	d
+TM1_TM_CUR_VALUE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1993;"	d
+TM1_TM_CUR_VALUE_SZ	include/ssv6200_aux.h	775;"	d
+TM1_TM_CUR_VALUE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1995;"	d
+TM1_TM_INIT_VALUE_HI	include/ssv6200_aux.h	754;"	d
+TM1_TM_INIT_VALUE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1974;"	d
+TM1_TM_INIT_VALUE_I_MSK	include/ssv6200_aux.h	752;"	d
+TM1_TM_INIT_VALUE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1972;"	d
+TM1_TM_INIT_VALUE_MSK	include/ssv6200_aux.h	751;"	d
+TM1_TM_INIT_VALUE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1971;"	d
+TM1_TM_INIT_VALUE_SFT	include/ssv6200_aux.h	753;"	d
+TM1_TM_INIT_VALUE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1973;"	d
+TM1_TM_INIT_VALUE_SZ	include/ssv6200_aux.h	755;"	d
+TM1_TM_INIT_VALUE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1975;"	d
+TM1_TM_INT_MASK_HI	include/ssv6200_aux.h	769;"	d
+TM1_TM_INT_MASK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1989;"	d
+TM1_TM_INT_MASK_I_MSK	include/ssv6200_aux.h	767;"	d
+TM1_TM_INT_MASK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1987;"	d
+TM1_TM_INT_MASK_MSK	include/ssv6200_aux.h	766;"	d
+TM1_TM_INT_MASK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1986;"	d
+TM1_TM_INT_MASK_SFT	include/ssv6200_aux.h	768;"	d
+TM1_TM_INT_MASK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1988;"	d
+TM1_TM_INT_MASK_SZ	include/ssv6200_aux.h	770;"	d
+TM1_TM_INT_MASK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1990;"	d
+TM1_TM_INT_STS_DONE_HI	include/ssv6200_aux.h	764;"	d
+TM1_TM_INT_STS_DONE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1984;"	d
+TM1_TM_INT_STS_DONE_I_MSK	include/ssv6200_aux.h	762;"	d
+TM1_TM_INT_STS_DONE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1982;"	d
+TM1_TM_INT_STS_DONE_MSK	include/ssv6200_aux.h	761;"	d
+TM1_TM_INT_STS_DONE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1981;"	d
+TM1_TM_INT_STS_DONE_SFT	include/ssv6200_aux.h	763;"	d
+TM1_TM_INT_STS_DONE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1983;"	d
+TM1_TM_INT_STS_DONE_SZ	include/ssv6200_aux.h	765;"	d
+TM1_TM_INT_STS_DONE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1985;"	d
+TM1_TM_MODE_HI	include/ssv6200_aux.h	759;"	d
+TM1_TM_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1979;"	d
+TM1_TM_MODE_I_MSK	include/ssv6200_aux.h	757;"	d
+TM1_TM_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1977;"	d
+TM1_TM_MODE_MSK	include/ssv6200_aux.h	756;"	d
+TM1_TM_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1976;"	d
+TM1_TM_MODE_SFT	include/ssv6200_aux.h	758;"	d
+TM1_TM_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1978;"	d
+TM1_TM_MODE_SZ	include/ssv6200_aux.h	760;"	d
+TM1_TM_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1980;"	d
+TM2_MS_REG_BANK_SIZE	include/ssv6200_reg.h	73;"	d
+TM2_MS_REG_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	90;"	d
+TM2_MS_REG_BASE	include/ssv6200_reg.h	24;"	d
+TM2_MS_REG_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	29;"	d
+TM2_PRESCALER_USTIMER_LOCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2029;"	d
+TM2_PRESCALER_USTIMER_LOCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2027;"	d
+TM2_PRESCALER_USTIMER_LOCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2026;"	d
+TM2_PRESCALER_USTIMER_LOCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2028;"	d
+TM2_PRESCALER_USTIMER_LOCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2030;"	d
+TM2_TM_CUR_VALUE_HI	include/ssv6200_aux.h	799;"	d
+TM2_TM_CUR_VALUE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2024;"	d
+TM2_TM_CUR_VALUE_I_MSK	include/ssv6200_aux.h	797;"	d
+TM2_TM_CUR_VALUE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2022;"	d
+TM2_TM_CUR_VALUE_MSK	include/ssv6200_aux.h	796;"	d
+TM2_TM_CUR_VALUE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2021;"	d
+TM2_TM_CUR_VALUE_SFT	include/ssv6200_aux.h	798;"	d
+TM2_TM_CUR_VALUE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2023;"	d
+TM2_TM_CUR_VALUE_SZ	include/ssv6200_aux.h	800;"	d
+TM2_TM_CUR_VALUE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2025;"	d
+TM2_TM_INIT_VALUE_HI	include/ssv6200_aux.h	779;"	d
+TM2_TM_INIT_VALUE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2004;"	d
+TM2_TM_INIT_VALUE_I_MSK	include/ssv6200_aux.h	777;"	d
+TM2_TM_INIT_VALUE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2002;"	d
+TM2_TM_INIT_VALUE_MSK	include/ssv6200_aux.h	776;"	d
+TM2_TM_INIT_VALUE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2001;"	d
+TM2_TM_INIT_VALUE_SFT	include/ssv6200_aux.h	778;"	d
+TM2_TM_INIT_VALUE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2003;"	d
+TM2_TM_INIT_VALUE_SZ	include/ssv6200_aux.h	780;"	d
+TM2_TM_INIT_VALUE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2005;"	d
+TM2_TM_INT_MASK_HI	include/ssv6200_aux.h	794;"	d
+TM2_TM_INT_MASK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2019;"	d
+TM2_TM_INT_MASK_I_MSK	include/ssv6200_aux.h	792;"	d
+TM2_TM_INT_MASK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2017;"	d
+TM2_TM_INT_MASK_MSK	include/ssv6200_aux.h	791;"	d
+TM2_TM_INT_MASK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2016;"	d
+TM2_TM_INT_MASK_SFT	include/ssv6200_aux.h	793;"	d
+TM2_TM_INT_MASK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2018;"	d
+TM2_TM_INT_MASK_SZ	include/ssv6200_aux.h	795;"	d
+TM2_TM_INT_MASK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2020;"	d
+TM2_TM_INT_STS_DONE_HI	include/ssv6200_aux.h	789;"	d
+TM2_TM_INT_STS_DONE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2014;"	d
+TM2_TM_INT_STS_DONE_I_MSK	include/ssv6200_aux.h	787;"	d
+TM2_TM_INT_STS_DONE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2012;"	d
+TM2_TM_INT_STS_DONE_MSK	include/ssv6200_aux.h	786;"	d
+TM2_TM_INT_STS_DONE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2011;"	d
+TM2_TM_INT_STS_DONE_SFT	include/ssv6200_aux.h	788;"	d
+TM2_TM_INT_STS_DONE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2013;"	d
+TM2_TM_INT_STS_DONE_SZ	include/ssv6200_aux.h	790;"	d
+TM2_TM_INT_STS_DONE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2015;"	d
+TM2_TM_MODE_HI	include/ssv6200_aux.h	784;"	d
+TM2_TM_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2009;"	d
+TM2_TM_MODE_I_MSK	include/ssv6200_aux.h	782;"	d
+TM2_TM_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2007;"	d
+TM2_TM_MODE_MSK	include/ssv6200_aux.h	781;"	d
+TM2_TM_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2006;"	d
+TM2_TM_MODE_SFT	include/ssv6200_aux.h	783;"	d
+TM2_TM_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2008;"	d
+TM2_TM_MODE_SZ	include/ssv6200_aux.h	785;"	d
+TM2_TM_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2010;"	d
+TM3_MS_REG_BANK_SIZE	include/ssv6200_reg.h	74;"	d
+TM3_MS_REG_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	91;"	d
+TM3_MS_REG_BASE	include/ssv6200_reg.h	25;"	d
+TM3_MS_REG_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	30;"	d
+TM3_PRESCALER_USTIMER_LOCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2059;"	d
+TM3_PRESCALER_USTIMER_LOCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2057;"	d
+TM3_PRESCALER_USTIMER_LOCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2056;"	d
+TM3_PRESCALER_USTIMER_LOCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2058;"	d
+TM3_PRESCALER_USTIMER_LOCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2060;"	d
+TM3_TM_CUR_VALUE_HI	include/ssv6200_aux.h	824;"	d
+TM3_TM_CUR_VALUE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2054;"	d
+TM3_TM_CUR_VALUE_I_MSK	include/ssv6200_aux.h	822;"	d
+TM3_TM_CUR_VALUE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2052;"	d
+TM3_TM_CUR_VALUE_MSK	include/ssv6200_aux.h	821;"	d
+TM3_TM_CUR_VALUE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2051;"	d
+TM3_TM_CUR_VALUE_SFT	include/ssv6200_aux.h	823;"	d
+TM3_TM_CUR_VALUE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2053;"	d
+TM3_TM_CUR_VALUE_SZ	include/ssv6200_aux.h	825;"	d
+TM3_TM_CUR_VALUE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2055;"	d
+TM3_TM_INIT_VALUE_HI	include/ssv6200_aux.h	804;"	d
+TM3_TM_INIT_VALUE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2034;"	d
+TM3_TM_INIT_VALUE_I_MSK	include/ssv6200_aux.h	802;"	d
+TM3_TM_INIT_VALUE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2032;"	d
+TM3_TM_INIT_VALUE_MSK	include/ssv6200_aux.h	801;"	d
+TM3_TM_INIT_VALUE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2031;"	d
+TM3_TM_INIT_VALUE_SFT	include/ssv6200_aux.h	803;"	d
+TM3_TM_INIT_VALUE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2033;"	d
+TM3_TM_INIT_VALUE_SZ	include/ssv6200_aux.h	805;"	d
+TM3_TM_INIT_VALUE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2035;"	d
+TM3_TM_INT_MASK_HI	include/ssv6200_aux.h	819;"	d
+TM3_TM_INT_MASK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2049;"	d
+TM3_TM_INT_MASK_I_MSK	include/ssv6200_aux.h	817;"	d
+TM3_TM_INT_MASK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2047;"	d
+TM3_TM_INT_MASK_MSK	include/ssv6200_aux.h	816;"	d
+TM3_TM_INT_MASK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2046;"	d
+TM3_TM_INT_MASK_SFT	include/ssv6200_aux.h	818;"	d
+TM3_TM_INT_MASK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2048;"	d
+TM3_TM_INT_MASK_SZ	include/ssv6200_aux.h	820;"	d
+TM3_TM_INT_MASK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2050;"	d
+TM3_TM_INT_STS_DONE_HI	include/ssv6200_aux.h	814;"	d
+TM3_TM_INT_STS_DONE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2044;"	d
+TM3_TM_INT_STS_DONE_I_MSK	include/ssv6200_aux.h	812;"	d
+TM3_TM_INT_STS_DONE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2042;"	d
+TM3_TM_INT_STS_DONE_MSK	include/ssv6200_aux.h	811;"	d
+TM3_TM_INT_STS_DONE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2041;"	d
+TM3_TM_INT_STS_DONE_SFT	include/ssv6200_aux.h	813;"	d
+TM3_TM_INT_STS_DONE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2043;"	d
+TM3_TM_INT_STS_DONE_SZ	include/ssv6200_aux.h	815;"	d
+TM3_TM_INT_STS_DONE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2045;"	d
+TM3_TM_MODE_HI	include/ssv6200_aux.h	809;"	d
+TM3_TM_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2039;"	d
+TM3_TM_MODE_I_MSK	include/ssv6200_aux.h	807;"	d
+TM3_TM_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2037;"	d
+TM3_TM_MODE_MSK	include/ssv6200_aux.h	806;"	d
+TM3_TM_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2036;"	d
+TM3_TM_MODE_SFT	include/ssv6200_aux.h	808;"	d
+TM3_TM_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2038;"	d
+TM3_TM_MODE_SZ	include/ssv6200_aux.h	810;"	d
+TM3_TM_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2040;"	d
+TOMAC_CS_CCA_MX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7409;"	d
+TOMAC_CS_CCA_MX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7407;"	d
+TOMAC_CS_CCA_MX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7406;"	d
+TOMAC_CS_CCA_MX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7408;"	d
+TOMAC_CS_CCA_MX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7410;"	d
+TOMAC_ED_CCA_PRIMARY_MX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7399;"	d
+TOMAC_ED_CCA_PRIMARY_MX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7397;"	d
+TOMAC_ED_CCA_PRIMARY_MX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7396;"	d
+TOMAC_ED_CCA_PRIMARY_MX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7398;"	d
+TOMAC_ED_CCA_PRIMARY_MX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7400;"	d
+TOMAC_ED_CCA_SECONDARY_MX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7404;"	d
+TOMAC_ED_CCA_SECONDARY_MX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7402;"	d
+TOMAC_ED_CCA_SECONDARY_MX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7401;"	d
+TOMAC_ED_CCA_SECONDARY_MX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7403;"	d
+TOMAC_ED_CCA_SECONDARY_MX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7405;"	d
+TOMAC_TX_IP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7394;"	d
+TOMAC_TX_IP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7392;"	d
+TOMAC_TX_IP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7391;"	d
+TOMAC_TX_IP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7393;"	d
+TOMAC_TX_IP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7395;"	d
+TOP_A_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3684;"	d
+TOP_A_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3682;"	d
+TOP_A_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3681;"	d
+TOP_A_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3683;"	d
+TOP_A_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3685;"	d
+TOP_ON1_RST_N_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1749;"	d
+TOP_ON1_RST_N_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1747;"	d
+TOP_ON1_RST_N_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1746;"	d
+TOP_ON1_RST_N_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1748;"	d
+TOP_ON1_RST_N_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1750;"	d
+TOP_ON2_RST_N_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1754;"	d
+TOP_ON2_RST_N_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1752;"	d
+TOP_ON2_RST_N_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1751;"	d
+TOP_ON2_RST_N_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1753;"	d
+TOP_ON2_RST_N_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1755;"	d
+TOP_ON3_RST_N_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1759;"	d
+TOP_ON3_RST_N_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1757;"	d
+TOP_ON3_RST_N_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1756;"	d
+TOP_ON3_RST_N_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1758;"	d
+TOP_ON3_RST_N_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1760;"	d
+TOP_SW_PWR_ON1_OUTPUT_PWR_ON1_1_0_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1504;"	d
+TOP_SW_PWR_ON1_OUTPUT_PWR_ON1_1_0_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1502;"	d
+TOP_SW_PWR_ON1_OUTPUT_PWR_ON1_1_0_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1501;"	d
+TOP_SW_PWR_ON1_OUTPUT_PWR_ON1_1_0_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1503;"	d
+TOP_SW_PWR_ON1_OUTPUT_PWR_ON1_1_0_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1505;"	d
+TOP_SW_PWR_ON2_OUTPUT_PWR_ON2_1_0_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1509;"	d
+TOP_SW_PWR_ON2_OUTPUT_PWR_ON2_1_0_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1507;"	d
+TOP_SW_PWR_ON2_OUTPUT_PWR_ON2_1_0_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1506;"	d
+TOP_SW_PWR_ON2_OUTPUT_PWR_ON2_1_0_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1508;"	d
+TOP_SW_PWR_ON2_OUTPUT_PWR_ON2_1_0_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1510;"	d
+TOP_SW_PWR_ON3_OUTPUT_PWR_ON3_1_0_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1514;"	d
+TOP_SW_PWR_ON3_OUTPUT_PWR_ON3_1_0_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1512;"	d
+TOP_SW_PWR_ON3_OUTPUT_PWR_ON3_1_0_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1511;"	d
+TOP_SW_PWR_ON3_OUTPUT_PWR_ON3_1_0_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1513;"	d
+TOP_SW_PWR_ON3_OUTPUT_PWR_ON3_1_0_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1515;"	d
+TOUT_AGN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7319;"	d
+TOUT_AGN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7317;"	d
+TOUT_AGN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7316;"	d
+TOUT_AGN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7318;"	d
+TOUT_AGN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7320;"	d
+TOUT_B_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7314;"	d
+TOUT_B_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7312;"	d
+TOUT_B_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7311;"	d
+TOUT_B_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7313;"	d
+TOUT_B_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7315;"	d
+TRAILEDGE_RI_HI	include/ssv6200_aux.h	4439;"	d
+TRAILEDGE_RI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3549;"	d
+TRAILEDGE_RI_I_MSK	include/ssv6200_aux.h	4437;"	d
+TRAILEDGE_RI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3547;"	d
+TRAILEDGE_RI_MSK	include/ssv6200_aux.h	4436;"	d
+TRAILEDGE_RI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3546;"	d
+TRAILEDGE_RI_SFT	include/ssv6200_aux.h	4438;"	d
+TRAILEDGE_RI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3548;"	d
+TRAILEDGE_RI_SZ	include/ssv6200_aux.h	4440;"	d
+TRAILEDGE_RI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3550;"	d
+TRANSACTION_TIMEOUT	hwif/usb/usb.c	39;"	d	file:
+TRANS_FULL_PKT_AMPDU1P2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5524;"	d
+TRANS_FULL_PKT_AMPDU1P2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5522;"	d
+TRANS_FULL_PKT_AMPDU1P2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5521;"	d
+TRANS_FULL_PKT_AMPDU1P2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5523;"	d
+TRANS_FULL_PKT_AMPDU1P2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5525;"	d
+TRAP_BOOT_FLS_HI	include/ssv6200_aux.h	154;"	d
+TRAP_BOOT_FLS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1104;"	d
+TRAP_BOOT_FLS_I_MSK	include/ssv6200_aux.h	152;"	d
+TRAP_BOOT_FLS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1102;"	d
+TRAP_BOOT_FLS_MSK	include/ssv6200_aux.h	151;"	d
+TRAP_BOOT_FLS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1101;"	d
+TRAP_BOOT_FLS_SFT	include/ssv6200_aux.h	153;"	d
+TRAP_BOOT_FLS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1103;"	d
+TRAP_BOOT_FLS_SZ	include/ssv6200_aux.h	155;"	d
+TRAP_BOOT_FLS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1105;"	d
+TRAP_HW_ID_HI	include/ssv6200_aux.h	7244;"	d
+TRAP_HW_ID_HI	smac/hal/ssv6006c/ssv6006C_aux.h	6419;"	d
+TRAP_HW_ID_I_MSK	include/ssv6200_aux.h	7242;"	d
+TRAP_HW_ID_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6417;"	d
+TRAP_HW_ID_MSK	include/ssv6200_aux.h	7241;"	d
+TRAP_HW_ID_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	6416;"	d
+TRAP_HW_ID_SFT	include/ssv6200_aux.h	7243;"	d
+TRAP_HW_ID_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	6418;"	d
+TRAP_HW_ID_SZ	include/ssv6200_aux.h	7245;"	d
+TRAP_HW_ID_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	6420;"	d
+TRAP_IMG_FLS_HI	include/ssv6200_aux.h	144;"	d
+TRAP_IMG_FLS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1094;"	d
+TRAP_IMG_FLS_I_MSK	include/ssv6200_aux.h	142;"	d
+TRAP_IMG_FLS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1092;"	d
+TRAP_IMG_FLS_MSK	include/ssv6200_aux.h	141;"	d
+TRAP_IMG_FLS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1091;"	d
+TRAP_IMG_FLS_SFT	include/ssv6200_aux.h	143;"	d
+TRAP_IMG_FLS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1093;"	d
+TRAP_IMG_FLS_SZ	include/ssv6200_aux.h	145;"	d
+TRAP_IMG_FLS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1095;"	d
+TRAP_REBOOT_HI	include/ssv6200_aux.h	149;"	d
+TRAP_REBOOT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1099;"	d
+TRAP_REBOOT_I_MSK	include/ssv6200_aux.h	147;"	d
+TRAP_REBOOT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1097;"	d
+TRAP_REBOOT_MSK	include/ssv6200_aux.h	146;"	d
+TRAP_REBOOT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1096;"	d
+TRAP_REBOOT_SFT	include/ssv6200_aux.h	148;"	d
+TRAP_REBOOT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1098;"	d
+TRAP_REBOOT_SZ	include/ssv6200_aux.h	150;"	d
+TRAP_REBOOT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1100;"	d
+TRAP_UNKNOWN_TYPE_HI	include/ssv6200_aux.h	6049;"	d
+TRAP_UNKNOWN_TYPE_I_MSK	include/ssv6200_aux.h	6047;"	d
+TRAP_UNKNOWN_TYPE_MSK	include/ssv6200_aux.h	6046;"	d
+TRAP_UNKNOWN_TYPE_SFT	include/ssv6200_aux.h	6048;"	d
+TRAP_UNKNOWN_TYPE_SZ	include/ssv6200_aux.h	6050;"	d
+TRASH_CAN_INT_HI	include/ssv6200_aux.h	12334;"	d
+TRASH_CAN_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33924;"	d
+TRASH_CAN_INT_I_MSK	include/ssv6200_aux.h	12332;"	d
+TRASH_CAN_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33922;"	d
+TRASH_CAN_INT_MSK	include/ssv6200_aux.h	12331;"	d
+TRASH_CAN_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33921;"	d
+TRASH_CAN_INT_SFT	include/ssv6200_aux.h	12333;"	d
+TRASH_CAN_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33923;"	d
+TRASH_CAN_INT_SZ	include/ssv6200_aux.h	12335;"	d
+TRASH_CAN_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33925;"	d
+TRASH_INT_ID_HI	include/ssv6200_aux.h	12339;"	d
+TRASH_INT_ID_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33929;"	d
+TRASH_INT_ID_I_MSK	include/ssv6200_aux.h	12337;"	d
+TRASH_INT_ID_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33927;"	d
+TRASH_INT_ID_MSK	include/ssv6200_aux.h	12336;"	d
+TRASH_INT_ID_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33926;"	d
+TRASH_INT_ID_SFT	include/ssv6200_aux.h	12338;"	d
+TRASH_INT_ID_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33928;"	d
+TRASH_INT_ID_SZ	include/ssv6200_aux.h	12340;"	d
+TRASH_INT_ID_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33930;"	d
+TRASH_TIMEOUT_EN_HI	include/ssv6200_aux.h	12329;"	d
+TRASH_TIMEOUT_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33919;"	d
+TRASH_TIMEOUT_EN_I_MSK	include/ssv6200_aux.h	12327;"	d
+TRASH_TIMEOUT_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33917;"	d
+TRASH_TIMEOUT_EN_MSK	include/ssv6200_aux.h	12326;"	d
+TRASH_TIMEOUT_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33916;"	d
+TRASH_TIMEOUT_EN_SFT	include/ssv6200_aux.h	12328;"	d
+TRASH_TIMEOUT_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33918;"	d
+TRASH_TIMEOUT_EN_SZ	include/ssv6200_aux.h	12330;"	d
+TRASH_TIMEOUT_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33920;"	d
+TRASH_TIMEOUT_HI	include/ssv6200_aux.h	12344;"	d
+TRASH_TIMEOUT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	33934;"	d
+TRASH_TIMEOUT_I_MSK	include/ssv6200_aux.h	12342;"	d
+TRASH_TIMEOUT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33932;"	d
+TRASH_TIMEOUT_MSK	include/ssv6200_aux.h	12341;"	d
+TRASH_TIMEOUT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	33931;"	d
+TRASH_TIMEOUT_SFT	include/ssv6200_aux.h	12343;"	d
+TRASH_TIMEOUT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	33933;"	d
+TRASH_TIMEOUT_SZ	include/ssv6200_aux.h	12345;"	d
+TRASH_TIMEOUT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	33935;"	d
+TRIGGER_FUNCTION_SETTING_HI	include/ssv6200_aux.h	3164;"	d
+TRIGGER_FUNCTION_SETTING_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2634;"	d
+TRIGGER_FUNCTION_SETTING_I_MSK	include/ssv6200_aux.h	3162;"	d
+TRIGGER_FUNCTION_SETTING_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2632;"	d
+TRIGGER_FUNCTION_SETTING_MSK	include/ssv6200_aux.h	3161;"	d
+TRIGGER_FUNCTION_SETTING_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2631;"	d
+TRIGGER_FUNCTION_SETTING_SFT	include/ssv6200_aux.h	3163;"	d
+TRIGGER_FUNCTION_SETTING_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2633;"	d
+TRIGGER_FUNCTION_SETTING_SZ	include/ssv6200_aux.h	3165;"	d
+TRIGGER_FUNCTION_SETTING_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2635;"	d
+TRSW_PHY_POL_HI	include/ssv6200_aux.h	9264;"	d
+TRSW_PHY_POL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9054;"	d
+TRSW_PHY_POL_I_MSK	include/ssv6200_aux.h	9262;"	d
+TRSW_PHY_POL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9052;"	d
+TRSW_PHY_POL_MSK	include/ssv6200_aux.h	9261;"	d
+TRSW_PHY_POL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9051;"	d
+TRSW_PHY_POL_SFT	include/ssv6200_aux.h	9263;"	d
+TRSW_PHY_POL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9053;"	d
+TRSW_PHY_POL_SZ	include/ssv6200_aux.h	9265;"	d
+TRSW_PHY_POL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9055;"	d
+TRUE	smac/wapi_sms4.c	/^    TRUE = 1$/;"	e	enum:__anon7	file:
+TRUTH_VALUE_T	smac/sec_wpi.h	/^} TRUTH_VALUE_T;$/;"	t	typeref:enum:__anon12
+TRXBUSYFLAG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	884;"	d
+TRXBUSYFLAG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	882;"	d
+TRXBUSYFLAG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	881;"	d
+TRXBUSYFLAG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	883;"	d
+TRXBUSYFLAG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	885;"	d
+TRX_DEBUG_CNT_ENA_HI	include/ssv6200_aux.h	6124;"	d
+TRX_DEBUG_CNT_ENA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5164;"	d
+TRX_DEBUG_CNT_ENA_I_MSK	include/ssv6200_aux.h	6122;"	d
+TRX_DEBUG_CNT_ENA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5162;"	d
+TRX_DEBUG_CNT_ENA_MSK	include/ssv6200_aux.h	6121;"	d
+TRX_DEBUG_CNT_ENA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5161;"	d
+TRX_DEBUG_CNT_ENA_SFT	include/ssv6200_aux.h	6123;"	d
+TRX_DEBUG_CNT_ENA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5163;"	d
+TRX_DEBUG_CNT_ENA_SZ	include/ssv6200_aux.h	6125;"	d
+TRX_DEBUG_CNT_ENA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5165;"	d
+TRX_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	849;"	d
+TRX_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	847;"	d
+TRX_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	846;"	d
+TRX_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	848;"	d
+TRX_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	850;"	d
+TSLOT	smac/ssv_rc_common.h	22;"	d
+TTHR_H_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3619;"	d
+TTHR_H_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3617;"	d
+TTHR_H_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3616;"	d
+TTHR_H_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3618;"	d
+TTHR_H_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3620;"	d
+TTHR_L_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3614;"	d
+TTHR_L_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3612;"	d
+TTHR_L_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3611;"	d
+TTHR_L_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3613;"	d
+TTHR_L_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3615;"	d
+TU0_PRESCALER_USTIMER_LOCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1849;"	d
+TU0_PRESCALER_USTIMER_LOCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1847;"	d
+TU0_PRESCALER_USTIMER_LOCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1846;"	d
+TU0_PRESCALER_USTIMER_LOCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1848;"	d
+TU0_PRESCALER_USTIMER_LOCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1850;"	d
+TU0_TM_CUR_VALUE_HI	include/ssv6200_aux.h	649;"	d
+TU0_TM_CUR_VALUE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1844;"	d
+TU0_TM_CUR_VALUE_I_MSK	include/ssv6200_aux.h	647;"	d
+TU0_TM_CUR_VALUE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1842;"	d
+TU0_TM_CUR_VALUE_MSK	include/ssv6200_aux.h	646;"	d
+TU0_TM_CUR_VALUE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1841;"	d
+TU0_TM_CUR_VALUE_SFT	include/ssv6200_aux.h	648;"	d
+TU0_TM_CUR_VALUE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1843;"	d
+TU0_TM_CUR_VALUE_SZ	include/ssv6200_aux.h	650;"	d
+TU0_TM_CUR_VALUE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1845;"	d
+TU0_TM_INIT_VALUE_HI	include/ssv6200_aux.h	629;"	d
+TU0_TM_INIT_VALUE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1824;"	d
+TU0_TM_INIT_VALUE_I_MSK	include/ssv6200_aux.h	627;"	d
+TU0_TM_INIT_VALUE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1822;"	d
+TU0_TM_INIT_VALUE_MSK	include/ssv6200_aux.h	626;"	d
+TU0_TM_INIT_VALUE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1821;"	d
+TU0_TM_INIT_VALUE_SFT	include/ssv6200_aux.h	628;"	d
+TU0_TM_INIT_VALUE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1823;"	d
+TU0_TM_INIT_VALUE_SZ	include/ssv6200_aux.h	630;"	d
+TU0_TM_INIT_VALUE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1825;"	d
+TU0_TM_INT_MASK_HI	include/ssv6200_aux.h	644;"	d
+TU0_TM_INT_MASK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1839;"	d
+TU0_TM_INT_MASK_I_MSK	include/ssv6200_aux.h	642;"	d
+TU0_TM_INT_MASK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1837;"	d
+TU0_TM_INT_MASK_MSK	include/ssv6200_aux.h	641;"	d
+TU0_TM_INT_MASK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1836;"	d
+TU0_TM_INT_MASK_SFT	include/ssv6200_aux.h	643;"	d
+TU0_TM_INT_MASK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1838;"	d
+TU0_TM_INT_MASK_SZ	include/ssv6200_aux.h	645;"	d
+TU0_TM_INT_MASK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1840;"	d
+TU0_TM_INT_STS_DONE_HI	include/ssv6200_aux.h	639;"	d
+TU0_TM_INT_STS_DONE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1834;"	d
+TU0_TM_INT_STS_DONE_I_MSK	include/ssv6200_aux.h	637;"	d
+TU0_TM_INT_STS_DONE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1832;"	d
+TU0_TM_INT_STS_DONE_MSK	include/ssv6200_aux.h	636;"	d
+TU0_TM_INT_STS_DONE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1831;"	d
+TU0_TM_INT_STS_DONE_SFT	include/ssv6200_aux.h	638;"	d
+TU0_TM_INT_STS_DONE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1833;"	d
+TU0_TM_INT_STS_DONE_SZ	include/ssv6200_aux.h	640;"	d
+TU0_TM_INT_STS_DONE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1835;"	d
+TU0_TM_MODE_HI	include/ssv6200_aux.h	634;"	d
+TU0_TM_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1829;"	d
+TU0_TM_MODE_I_MSK	include/ssv6200_aux.h	632;"	d
+TU0_TM_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1827;"	d
+TU0_TM_MODE_MSK	include/ssv6200_aux.h	631;"	d
+TU0_TM_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1826;"	d
+TU0_TM_MODE_SFT	include/ssv6200_aux.h	633;"	d
+TU0_TM_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1828;"	d
+TU0_TM_MODE_SZ	include/ssv6200_aux.h	635;"	d
+TU0_TM_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1830;"	d
+TU0_US_REG_BANK_SIZE	include/ssv6200_reg.h	67;"	d
+TU0_US_REG_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	84;"	d
+TU0_US_REG_BASE	include/ssv6200_reg.h	18;"	d
+TU0_US_REG_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	23;"	d
+TU1_PRESCALER_USTIMER_LOCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1879;"	d
+TU1_PRESCALER_USTIMER_LOCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1877;"	d
+TU1_PRESCALER_USTIMER_LOCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1876;"	d
+TU1_PRESCALER_USTIMER_LOCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1878;"	d
+TU1_PRESCALER_USTIMER_LOCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1880;"	d
+TU1_TM_CUR_VALUE_HI	include/ssv6200_aux.h	674;"	d
+TU1_TM_CUR_VALUE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1874;"	d
+TU1_TM_CUR_VALUE_I_MSK	include/ssv6200_aux.h	672;"	d
+TU1_TM_CUR_VALUE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1872;"	d
+TU1_TM_CUR_VALUE_MSK	include/ssv6200_aux.h	671;"	d
+TU1_TM_CUR_VALUE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1871;"	d
+TU1_TM_CUR_VALUE_SFT	include/ssv6200_aux.h	673;"	d
+TU1_TM_CUR_VALUE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1873;"	d
+TU1_TM_CUR_VALUE_SZ	include/ssv6200_aux.h	675;"	d
+TU1_TM_CUR_VALUE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1875;"	d
+TU1_TM_INIT_VALUE_HI	include/ssv6200_aux.h	654;"	d
+TU1_TM_INIT_VALUE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1854;"	d
+TU1_TM_INIT_VALUE_I_MSK	include/ssv6200_aux.h	652;"	d
+TU1_TM_INIT_VALUE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1852;"	d
+TU1_TM_INIT_VALUE_MSK	include/ssv6200_aux.h	651;"	d
+TU1_TM_INIT_VALUE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1851;"	d
+TU1_TM_INIT_VALUE_SFT	include/ssv6200_aux.h	653;"	d
+TU1_TM_INIT_VALUE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1853;"	d
+TU1_TM_INIT_VALUE_SZ	include/ssv6200_aux.h	655;"	d
+TU1_TM_INIT_VALUE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1855;"	d
+TU1_TM_INT_MASK_HI	include/ssv6200_aux.h	669;"	d
+TU1_TM_INT_MASK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1869;"	d
+TU1_TM_INT_MASK_I_MSK	include/ssv6200_aux.h	667;"	d
+TU1_TM_INT_MASK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1867;"	d
+TU1_TM_INT_MASK_MSK	include/ssv6200_aux.h	666;"	d
+TU1_TM_INT_MASK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1866;"	d
+TU1_TM_INT_MASK_SFT	include/ssv6200_aux.h	668;"	d
+TU1_TM_INT_MASK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1868;"	d
+TU1_TM_INT_MASK_SZ	include/ssv6200_aux.h	670;"	d
+TU1_TM_INT_MASK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1870;"	d
+TU1_TM_INT_STS_DONE_HI	include/ssv6200_aux.h	664;"	d
+TU1_TM_INT_STS_DONE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1864;"	d
+TU1_TM_INT_STS_DONE_I_MSK	include/ssv6200_aux.h	662;"	d
+TU1_TM_INT_STS_DONE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1862;"	d
+TU1_TM_INT_STS_DONE_MSK	include/ssv6200_aux.h	661;"	d
+TU1_TM_INT_STS_DONE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1861;"	d
+TU1_TM_INT_STS_DONE_SFT	include/ssv6200_aux.h	663;"	d
+TU1_TM_INT_STS_DONE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1863;"	d
+TU1_TM_INT_STS_DONE_SZ	include/ssv6200_aux.h	665;"	d
+TU1_TM_INT_STS_DONE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1865;"	d
+TU1_TM_MODE_HI	include/ssv6200_aux.h	659;"	d
+TU1_TM_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1859;"	d
+TU1_TM_MODE_I_MSK	include/ssv6200_aux.h	657;"	d
+TU1_TM_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1857;"	d
+TU1_TM_MODE_MSK	include/ssv6200_aux.h	656;"	d
+TU1_TM_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1856;"	d
+TU1_TM_MODE_SFT	include/ssv6200_aux.h	658;"	d
+TU1_TM_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1858;"	d
+TU1_TM_MODE_SZ	include/ssv6200_aux.h	660;"	d
+TU1_TM_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1860;"	d
+TU1_US_REG_BANK_SIZE	include/ssv6200_reg.h	68;"	d
+TU1_US_REG_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	85;"	d
+TU1_US_REG_BASE	include/ssv6200_reg.h	19;"	d
+TU1_US_REG_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	24;"	d
+TU2_PRESCALER_USTIMER_LOCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1909;"	d
+TU2_PRESCALER_USTIMER_LOCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1907;"	d
+TU2_PRESCALER_USTIMER_LOCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1906;"	d
+TU2_PRESCALER_USTIMER_LOCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1908;"	d
+TU2_PRESCALER_USTIMER_LOCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1910;"	d
+TU2_TM_CUR_VALUE_HI	include/ssv6200_aux.h	699;"	d
+TU2_TM_CUR_VALUE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1904;"	d
+TU2_TM_CUR_VALUE_I_MSK	include/ssv6200_aux.h	697;"	d
+TU2_TM_CUR_VALUE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1902;"	d
+TU2_TM_CUR_VALUE_MSK	include/ssv6200_aux.h	696;"	d
+TU2_TM_CUR_VALUE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1901;"	d
+TU2_TM_CUR_VALUE_SFT	include/ssv6200_aux.h	698;"	d
+TU2_TM_CUR_VALUE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1903;"	d
+TU2_TM_CUR_VALUE_SZ	include/ssv6200_aux.h	700;"	d
+TU2_TM_CUR_VALUE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1905;"	d
+TU2_TM_INIT_VALUE_HI	include/ssv6200_aux.h	679;"	d
+TU2_TM_INIT_VALUE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1884;"	d
+TU2_TM_INIT_VALUE_I_MSK	include/ssv6200_aux.h	677;"	d
+TU2_TM_INIT_VALUE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1882;"	d
+TU2_TM_INIT_VALUE_MSK	include/ssv6200_aux.h	676;"	d
+TU2_TM_INIT_VALUE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1881;"	d
+TU2_TM_INIT_VALUE_SFT	include/ssv6200_aux.h	678;"	d
+TU2_TM_INIT_VALUE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1883;"	d
+TU2_TM_INIT_VALUE_SZ	include/ssv6200_aux.h	680;"	d
+TU2_TM_INIT_VALUE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1885;"	d
+TU2_TM_INT_MASK_HI	include/ssv6200_aux.h	694;"	d
+TU2_TM_INT_MASK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1899;"	d
+TU2_TM_INT_MASK_I_MSK	include/ssv6200_aux.h	692;"	d
+TU2_TM_INT_MASK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1897;"	d
+TU2_TM_INT_MASK_MSK	include/ssv6200_aux.h	691;"	d
+TU2_TM_INT_MASK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1896;"	d
+TU2_TM_INT_MASK_SFT	include/ssv6200_aux.h	693;"	d
+TU2_TM_INT_MASK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1898;"	d
+TU2_TM_INT_MASK_SZ	include/ssv6200_aux.h	695;"	d
+TU2_TM_INT_MASK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1900;"	d
+TU2_TM_INT_STS_DONE_HI	include/ssv6200_aux.h	689;"	d
+TU2_TM_INT_STS_DONE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1894;"	d
+TU2_TM_INT_STS_DONE_I_MSK	include/ssv6200_aux.h	687;"	d
+TU2_TM_INT_STS_DONE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1892;"	d
+TU2_TM_INT_STS_DONE_MSK	include/ssv6200_aux.h	686;"	d
+TU2_TM_INT_STS_DONE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1891;"	d
+TU2_TM_INT_STS_DONE_SFT	include/ssv6200_aux.h	688;"	d
+TU2_TM_INT_STS_DONE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1893;"	d
+TU2_TM_INT_STS_DONE_SZ	include/ssv6200_aux.h	690;"	d
+TU2_TM_INT_STS_DONE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1895;"	d
+TU2_TM_MODE_HI	include/ssv6200_aux.h	684;"	d
+TU2_TM_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1889;"	d
+TU2_TM_MODE_I_MSK	include/ssv6200_aux.h	682;"	d
+TU2_TM_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1887;"	d
+TU2_TM_MODE_MSK	include/ssv6200_aux.h	681;"	d
+TU2_TM_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1886;"	d
+TU2_TM_MODE_SFT	include/ssv6200_aux.h	683;"	d
+TU2_TM_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1888;"	d
+TU2_TM_MODE_SZ	include/ssv6200_aux.h	685;"	d
+TU2_TM_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1890;"	d
+TU2_US_REG_BANK_SIZE	include/ssv6200_reg.h	69;"	d
+TU2_US_REG_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	86;"	d
+TU2_US_REG_BASE	include/ssv6200_reg.h	20;"	d
+TU2_US_REG_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	25;"	d
+TU3_PRESCALER_USTIMER_LOCAL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1939;"	d
+TU3_PRESCALER_USTIMER_LOCAL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1937;"	d
+TU3_PRESCALER_USTIMER_LOCAL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1936;"	d
+TU3_PRESCALER_USTIMER_LOCAL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1938;"	d
+TU3_PRESCALER_USTIMER_LOCAL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1940;"	d
+TU3_TM_CUR_VALUE_HI	include/ssv6200_aux.h	724;"	d
+TU3_TM_CUR_VALUE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1934;"	d
+TU3_TM_CUR_VALUE_I_MSK	include/ssv6200_aux.h	722;"	d
+TU3_TM_CUR_VALUE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1932;"	d
+TU3_TM_CUR_VALUE_MSK	include/ssv6200_aux.h	721;"	d
+TU3_TM_CUR_VALUE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1931;"	d
+TU3_TM_CUR_VALUE_SFT	include/ssv6200_aux.h	723;"	d
+TU3_TM_CUR_VALUE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1933;"	d
+TU3_TM_CUR_VALUE_SZ	include/ssv6200_aux.h	725;"	d
+TU3_TM_CUR_VALUE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1935;"	d
+TU3_TM_INIT_VALUE_HI	include/ssv6200_aux.h	704;"	d
+TU3_TM_INIT_VALUE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1914;"	d
+TU3_TM_INIT_VALUE_I_MSK	include/ssv6200_aux.h	702;"	d
+TU3_TM_INIT_VALUE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1912;"	d
+TU3_TM_INIT_VALUE_MSK	include/ssv6200_aux.h	701;"	d
+TU3_TM_INIT_VALUE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1911;"	d
+TU3_TM_INIT_VALUE_SFT	include/ssv6200_aux.h	703;"	d
+TU3_TM_INIT_VALUE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1913;"	d
+TU3_TM_INIT_VALUE_SZ	include/ssv6200_aux.h	705;"	d
+TU3_TM_INIT_VALUE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1915;"	d
+TU3_TM_INT_MASK_HI	include/ssv6200_aux.h	719;"	d
+TU3_TM_INT_MASK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1929;"	d
+TU3_TM_INT_MASK_I_MSK	include/ssv6200_aux.h	717;"	d
+TU3_TM_INT_MASK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1927;"	d
+TU3_TM_INT_MASK_MSK	include/ssv6200_aux.h	716;"	d
+TU3_TM_INT_MASK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1926;"	d
+TU3_TM_INT_MASK_SFT	include/ssv6200_aux.h	718;"	d
+TU3_TM_INT_MASK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1928;"	d
+TU3_TM_INT_MASK_SZ	include/ssv6200_aux.h	720;"	d
+TU3_TM_INT_MASK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1930;"	d
+TU3_TM_INT_STS_DONE_HI	include/ssv6200_aux.h	714;"	d
+TU3_TM_INT_STS_DONE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1924;"	d
+TU3_TM_INT_STS_DONE_I_MSK	include/ssv6200_aux.h	712;"	d
+TU3_TM_INT_STS_DONE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1922;"	d
+TU3_TM_INT_STS_DONE_MSK	include/ssv6200_aux.h	711;"	d
+TU3_TM_INT_STS_DONE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1921;"	d
+TU3_TM_INT_STS_DONE_SFT	include/ssv6200_aux.h	713;"	d
+TU3_TM_INT_STS_DONE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1923;"	d
+TU3_TM_INT_STS_DONE_SZ	include/ssv6200_aux.h	715;"	d
+TU3_TM_INT_STS_DONE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1925;"	d
+TU3_TM_MODE_HI	include/ssv6200_aux.h	709;"	d
+TU3_TM_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1919;"	d
+TU3_TM_MODE_I_MSK	include/ssv6200_aux.h	707;"	d
+TU3_TM_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1917;"	d
+TU3_TM_MODE_MSK	include/ssv6200_aux.h	706;"	d
+TU3_TM_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1916;"	d
+TU3_TM_MODE_SFT	include/ssv6200_aux.h	708;"	d
+TU3_TM_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1918;"	d
+TU3_TM_MODE_SZ	include/ssv6200_aux.h	710;"	d
+TU3_TM_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1920;"	d
+TU3_US_REG_BANK_SIZE	include/ssv6200_reg.h	70;"	d
+TU3_US_REG_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	87;"	d
+TU3_US_REG_BASE	include/ssv6200_reg.h	21;"	d
+TU3_US_REG_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	26;"	d
+TURISMOA_SET_2G_CHANNEL	smac/hal/ssv6006c/turismo_common.h	780;"	d
+TURISMOA_SET_2G_TXPWR	smac/hal/ssv6006c/turismo_common.h	767;"	d
+TURISMOA_SET_5G_CHANNEL	smac/hal/ssv6006c/turismo_common.h	735;"	d
+TURISMOA_SET_5G_TXPWR	smac/hal/ssv6006c/turismo_common.h	677;"	d
+TURISMOB_2P4G_RXDC_CAL	smac/hal/ssv6006c/turismo_common.h	1192;"	d
+TURISMOB_5G_RXDC_CAL	smac/hal/ssv6006c/turismo_common.h	1220;"	d
+TURISMOB_5G_RXIQ_CAL	smac/hal/ssv6006c/turismo_common.h	1568;"	d
+TURISMOB_5G_TXDC_CAL	smac/hal/ssv6006c/turismo_common.h	1475;"	d
+TURISMOB_5G_TXIQ_CAL	smac/hal/ssv6006c/turismo_common.h	1521;"	d
+TURISMOB_BW20_RXRC_CAL	smac/hal/ssv6006c/turismo_common.h	1249;"	d
+TURISMOB_BW40_RXRC_CAL	smac/hal/ssv6006c/turismo_common.h	1288;"	d
+TURISMOB_POST_CAL	smac/hal/ssv6006c/turismo_common.h	1169;"	d
+TURISMOB_PRE_CAL	smac/hal/ssv6006c/turismo_common.h	1158;"	d
+TURISMOB_RXIQ_CAL	smac/hal/ssv6006c/turismo_common.h	1426;"	d
+TURISMOB_SET_2G_CHANNEL	smac/hal/ssv6006c/turismo_common.h	1776;"	d
+TURISMOB_SET_5G_CHANNEL	smac/hal/ssv6006c/turismo_common.h	1752;"	d
+TURISMOB_TXDC_CAL	smac/hal/ssv6006c/turismo_common.h	1333;"	d
+TURISMOB_TXIQ_CAL	smac/hal/ssv6006c/turismo_common.h	1379;"	d
+TURISMOC_2P4G_RXDC_CAL	smac/hal/ssv6006c/turismo_common.h	1904;"	d
+TURISMOC_5G_RXDC_CAL	smac/hal/ssv6006c/turismo_common.h	1971;"	d
+TURISMOC_5G_RXIQ_CAL	smac/hal/ssv6006c/turismo_common.h	2547;"	d
+TURISMOC_5G_RXIQ_CAL_BAND	smac/hal/ssv6006c/turismo_common.h	2619;"	d
+TURISMOC_5G_TXDC_CAL	smac/hal/ssv6006c/turismo_common.h	2292;"	d
+TURISMOC_5G_TXIQ_CAL	smac/hal/ssv6006c/turismo_common.h	2341;"	d
+TURISMOC_5G_TXIQ_CAL_BAND	smac/hal/ssv6006c/turismo_common.h	2412;"	d
+TURISMOC_BW20_RXRC_CAL	smac/hal/ssv6006c/turismo_common.h	2008;"	d
+TURISMOC_BW40_RXRC_CAL	smac/hal/ssv6006c/turismo_common.h	2050;"	d
+TURISMOC_RXIQ_CAL	smac/hal/ssv6006c/turismo_common.h	2238;"	d
+TURISMOC_SET_2G_CHANNEL	smac/hal/ssv6006c/turismo_common.h	3049;"	d
+TURISMOC_SET_5G_CHANNEL	smac/hal/ssv6006c/turismo_common.h	3011;"	d
+TURISMOC_TXDC_CAL	smac/hal/ssv6006c/turismo_common.h	2091;"	d
+TURISMOC_TXIQ_CAL	smac/hal/ssv6006c/turismo_common.h	2143;"	d
+TURISMO_INTER_CAL	smac/hal/ssv6006c/turismo_common.h	1177;"	d
+TURISMO_TRX_SAR_ADC_FSM_RDY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	17974;"	d
+TURISMO_TRX_SAR_ADC_FSM_RDY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17972;"	d
+TURISMO_TRX_SAR_ADC_FSM_RDY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	17971;"	d
+TURISMO_TRX_SAR_ADC_FSM_RDY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	17973;"	d
+TURISMO_TRX_SAR_ADC_FSM_RDY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	17975;"	d
+TURN_OFF_PADPD	smac/hal/ssv6006c/turismo_common.h	3382;"	d
+TURN_ON_PADPD	smac/hal/ssv6006c/turismo_common.h	3389;"	d
+TU_CHANGE_GEMINIA_CHANNEL	smac/hal/ssv6006c/turismo_common.h	407;"	d
+TU_CHANGE_TURISMOA_CHANNEL	smac/hal/ssv6006c/turismo_common.h	812;"	d
+TU_CHANGE_TURISMOB_CHANNEL	smac/hal/ssv6006c/turismo_common.h	1799;"	d
+TU_CHANGE_TURISMOC_CHANNEL	smac/hal/ssv6006c/turismo_common.h	3557;"	d
+TU_COMMON_H	smac/hal/ssv6006c/turismo_common.h	17;"	d
+TU_DISABLE_TURISMOC_DPD	smac/hal/ssv6006c/turismo_common.h	3590;"	d
+TU_ENABLE_TURISMOC_DPD	smac/hal/ssv6006c/turismo_common.h	3602;"	d
+TU_ENABLE_TURISMOC_DPD	smac/hal/ssv6006c/turismo_common.h	3612;"	d
+TU_INIT_GEMINIA_CAL	smac/hal/ssv6006c/turismo_common.h	445;"	d
+TU_INIT_GEMINIA_TRX	smac/hal/ssv6006c/turismo_common.h	525;"	d
+TU_INIT_PLL	smac/hal/ssv6006c/turismo_common.h	418;"	d
+TU_INIT_TURISMOA_CALI	smac/hal/ssv6006c/turismo_common.h	850;"	d
+TU_INIT_TURISMOA_TRX	smac/hal/ssv6006c/turismo_common.h	950;"	d
+TU_INIT_TURISMOB_2G_CALI	smac/hal/ssv6006c/turismo_common.h	1644;"	d
+TU_INIT_TURISMOB_2G_CALI_ORG	smac/hal/ssv6006c/turismo_common.h	1119;"	d
+TU_INIT_TURISMOB_CALI	smac/hal/ssv6006c/turismo_common.h	1618;"	d
+TU_INIT_TURISMOB_CALI_ORG	smac/hal/ssv6006c/turismo_common.h	1055;"	d
+TU_INIT_TURISMOB_PLL	smac/hal/ssv6006c/turismo_common.h	1029;"	d
+TU_INIT_TURISMOC_2G_CALI	smac/hal/ssv6006c/turismo_common.h	2751;"	d
+TU_INIT_TURISMOC_2G_FAST_CALI	smac/hal/ssv6006c/turismo_common.h	2798;"	d
+TU_INIT_TURISMOC_CALI	smac/hal/ssv6006c/turismo_common.h	2716;"	d
+TU_INIT_TURISMOC_FAST_CALI	smac/hal/ssv6006c/turismo_common.h	2774;"	d
+TU_INIT_TURISMOC_PLL	smac/hal/ssv6006c/turismo_common.h	1822;"	d
+TU_RESTART_RF_PHY	smac/hal/ssv6006c/turismo_common.h	3624;"	d
+TU_RESTORE_DPD	smac/hal/ssv6006c/turismo_common.h	3309;"	d
+TU_SET_CHANNEL	smac/hal/ssv6006c/turismo_common.h	318;"	d
+TU_SET_GEMINIA_BW	smac/hal/ssv6006c/turismo_common.h	345;"	d
+TU_SET_TURISMOA_BW	smac/hal/ssv6006c/turismo_common.h	608;"	d
+TU_SET_TURISMOB_BW	smac/hal/ssv6006c/turismo_common.h	1697;"	d
+TU_SET_TURISMOC_BW	smac/hal/ssv6006c/turismo_common.h	2959;"	d
+TV_FALSE	smac/sec_wpi.h	/^              TV_FALSE = 2$/;"	e	enum:__anon12
+TV_TRUE	smac/sec_wpi.h	/^typedef enum {TV_TRUE = 1,$/;"	e	enum:__anon12
+TWI_DELAY_ACK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3259;"	d
+TWI_DELAY_ACK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3257;"	d
+TWI_DELAY_ACK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3256;"	d
+TWI_DELAY_ACK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3258;"	d
+TWI_DELAY_ACK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3260;"	d
+TWI_DEV_A10B_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3229;"	d
+TWI_DEV_A10B_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3227;"	d
+TWI_DEV_A10B_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3226;"	d
+TWI_DEV_A10B_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3228;"	d
+TWI_DEV_A10B_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3230;"	d
+TWI_DEV_A_10B_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3104;"	d
+TWI_DEV_A_10B_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3102;"	d
+TWI_DEV_A_10B_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3101;"	d
+TWI_DEV_A_10B_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3103;"	d
+TWI_DEV_A_10B_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3105;"	d
+TWI_INT_HOLD_BUS_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3149;"	d
+TWI_INT_HOLD_BUS_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3147;"	d
+TWI_INT_HOLD_BUS_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3146;"	d
+TWI_INT_HOLD_BUS_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3148;"	d
+TWI_INT_HOLD_BUS_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3150;"	d
+TWI_INT_HOLD_BUS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3179;"	d
+TWI_INT_HOLD_BUS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3177;"	d
+TWI_INT_HOLD_BUS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3176;"	d
+TWI_INT_HOLD_BUS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3178;"	d
+TWI_INT_HOLD_BUS_ST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3209;"	d
+TWI_INT_HOLD_BUS_ST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3207;"	d
+TWI_INT_HOLD_BUS_ST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3206;"	d
+TWI_INT_HOLD_BUS_ST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3208;"	d
+TWI_INT_HOLD_BUS_ST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3210;"	d
+TWI_INT_HOLD_BUS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3180;"	d
+TWI_INT_MISMATCH_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3139;"	d
+TWI_INT_MISMATCH_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3137;"	d
+TWI_INT_MISMATCH_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3136;"	d
+TWI_INT_MISMATCH_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3138;"	d
+TWI_INT_MISMATCH_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3140;"	d
+TWI_INT_MISMATCH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3169;"	d
+TWI_INT_MISMATCH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3167;"	d
+TWI_INT_MISMATCH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3166;"	d
+TWI_INT_MISMATCH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3168;"	d
+TWI_INT_MISMATCH_ST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3199;"	d
+TWI_INT_MISMATCH_ST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3197;"	d
+TWI_INT_MISMATCH_ST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3196;"	d
+TWI_INT_MISMATCH_ST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3198;"	d
+TWI_INT_MISMATCH_ST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3200;"	d
+TWI_INT_MISMATCH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3170;"	d
+TWI_INT_RXD_STALL_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3129;"	d
+TWI_INT_RXD_STALL_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3127;"	d
+TWI_INT_RXD_STALL_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3126;"	d
+TWI_INT_RXD_STALL_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3128;"	d
+TWI_INT_RXD_STALL_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3130;"	d
+TWI_INT_RXD_STALL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3159;"	d
+TWI_INT_RXD_STALL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3157;"	d
+TWI_INT_RXD_STALL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3156;"	d
+TWI_INT_RXD_STALL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3158;"	d
+TWI_INT_RXD_STALL_ST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3189;"	d
+TWI_INT_RXD_STALL_ST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3187;"	d
+TWI_INT_RXD_STALL_ST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3186;"	d
+TWI_INT_RXD_STALL_ST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3188;"	d
+TWI_INT_RXD_STALL_ST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3190;"	d
+TWI_INT_RXD_STALL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3160;"	d
+TWI_INT_TRANS_FAIL_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3144;"	d
+TWI_INT_TRANS_FAIL_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3142;"	d
+TWI_INT_TRANS_FAIL_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3141;"	d
+TWI_INT_TRANS_FAIL_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3143;"	d
+TWI_INT_TRANS_FAIL_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3145;"	d
+TWI_INT_TRANS_FAIL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3174;"	d
+TWI_INT_TRANS_FAIL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3172;"	d
+TWI_INT_TRANS_FAIL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3171;"	d
+TWI_INT_TRANS_FAIL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3173;"	d
+TWI_INT_TRANS_FAIL_ST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3204;"	d
+TWI_INT_TRANS_FAIL_ST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3202;"	d
+TWI_INT_TRANS_FAIL_ST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3201;"	d
+TWI_INT_TRANS_FAIL_ST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3203;"	d
+TWI_INT_TRANS_FAIL_ST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3205;"	d
+TWI_INT_TRANS_FAIL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3175;"	d
+TWI_INT_TRANS_FINISH_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3134;"	d
+TWI_INT_TRANS_FINISH_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3132;"	d
+TWI_INT_TRANS_FINISH_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3131;"	d
+TWI_INT_TRANS_FINISH_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3133;"	d
+TWI_INT_TRANS_FINISH_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3135;"	d
+TWI_INT_TRANS_FINISH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3164;"	d
+TWI_INT_TRANS_FINISH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3162;"	d
+TWI_INT_TRANS_FINISH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3161;"	d
+TWI_INT_TRANS_FINISH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3163;"	d
+TWI_INT_TRANS_FINISH_ST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3194;"	d
+TWI_INT_TRANS_FINISH_ST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3192;"	d
+TWI_INT_TRANS_FINISH_ST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3191;"	d
+TWI_INT_TRANS_FINISH_ST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3193;"	d
+TWI_INT_TRANS_FINISH_ST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3195;"	d
+TWI_INT_TRANS_FINISH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3165;"	d
+TWI_INT_TXD_STALL_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3124;"	d
+TWI_INT_TXD_STALL_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3122;"	d
+TWI_INT_TXD_STALL_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3121;"	d
+TWI_INT_TXD_STALL_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3123;"	d
+TWI_INT_TXD_STALL_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3125;"	d
+TWI_INT_TXD_STALL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3154;"	d
+TWI_INT_TXD_STALL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3152;"	d
+TWI_INT_TXD_STALL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3151;"	d
+TWI_INT_TXD_STALL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3153;"	d
+TWI_INT_TXD_STALL_ST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3184;"	d
+TWI_INT_TXD_STALL_ST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3182;"	d
+TWI_INT_TXD_STALL_ST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3181;"	d
+TWI_INT_TXD_STALL_ST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3183;"	d
+TWI_INT_TXD_STALL_ST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3185;"	d
+TWI_INT_TXD_STALL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3155;"	d
+TWI_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3109;"	d
+TWI_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3107;"	d
+TWI_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3106;"	d
+TWI_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3108;"	d
+TWI_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3110;"	d
+TWI_PSCL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3244;"	d
+TWI_PSCL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3242;"	d
+TWI_PSCL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3241;"	d
+TWI_PSCL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3243;"	d
+TWI_PSCL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3245;"	d
+TWI_RXD_DATA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3239;"	d
+TWI_RXD_DATA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3237;"	d
+TWI_RXD_DATA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3236;"	d
+TWI_RXD_DATA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3238;"	d
+TWI_RXD_DATA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3240;"	d
+TWI_RX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3224;"	d
+TWI_RX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3222;"	d
+TWI_RX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3221;"	d
+TWI_RX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3223;"	d
+TWI_RX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3225;"	d
+TWI_START_TRIG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3089;"	d
+TWI_START_TRIG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3087;"	d
+TWI_START_TRIG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3086;"	d
+TWI_START_TRIG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3088;"	d
+TWI_START_TRIG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3090;"	d
+TWI_STATUS_RECORD_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3214;"	d
+TWI_STATUS_RECORD_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3212;"	d
+TWI_STATUS_RECORD_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3211;"	d
+TWI_STATUS_RECORD_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3213;"	d
+TWI_STATUS_RECORD_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3215;"	d
+TWI_STATUS_RECORD_1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3219;"	d
+TWI_STATUS_RECORD_1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3217;"	d
+TWI_STATUS_RECORD_1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3216;"	d
+TWI_STATUS_RECORD_1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3218;"	d
+TWI_STATUS_RECORD_1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3220;"	d
+TWI_STA_STO_PSCL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3249;"	d
+TWI_STA_STO_PSCL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3247;"	d
+TWI_STA_STO_PSCL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3246;"	d
+TWI_STA_STO_PSCL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3248;"	d
+TWI_STA_STO_PSCL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3250;"	d
+TWI_STOP_TRIG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3094;"	d
+TWI_STOP_TRIG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3092;"	d
+TWI_STOP_TRIG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3091;"	d
+TWI_STOP_TRIG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3093;"	d
+TWI_STOP_TRIG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3095;"	d
+TWI_TRANS_CONTINUE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3099;"	d
+TWI_TRANS_CONTINUE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3097;"	d
+TWI_TRANS_CONTINUE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3096;"	d
+TWI_TRANS_CONTINUE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3098;"	d
+TWI_TRANS_CONTINUE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3100;"	d
+TWI_TRANS_PSDA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3254;"	d
+TWI_TRANS_PSDA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3252;"	d
+TWI_TRANS_PSDA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3251;"	d
+TWI_TRANS_PSDA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3253;"	d
+TWI_TRANS_PSDA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3255;"	d
+TWI_TXD_DATA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3234;"	d
+TWI_TXD_DATA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3232;"	d
+TWI_TXD_DATA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3231;"	d
+TWI_TXD_DATA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3233;"	d
+TWI_TXD_DATA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3235;"	d
+TXEMPTYFLAG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	894;"	d
+TXEMPTYFLAG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	892;"	d
+TXEMPTYFLAG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	891;"	d
+TXEMPTYFLAG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	893;"	d
+TXEMPTYFLAG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	895;"	d
+TXERRORFLAG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	909;"	d
+TXERRORFLAG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	907;"	d
+TXERRORFLAG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	906;"	d
+TXERRORFLAG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	908;"	d
+TXERRORFLAG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	910;"	d
+TXFIFO_RST_HI	include/ssv6200_aux.h	4304;"	d
+TXFIFO_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3409;"	d
+TXFIFO_RST_I_MSK	include/ssv6200_aux.h	4302;"	d
+TXFIFO_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3407;"	d
+TXFIFO_RST_MSK	include/ssv6200_aux.h	4301;"	d
+TXFIFO_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3406;"	d
+TXFIFO_RST_SFT	include/ssv6200_aux.h	4303;"	d
+TXFIFO_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3408;"	d
+TXFIFO_RST_SZ	include/ssv6200_aux.h	4305;"	d
+TXFIFO_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3410;"	d
+TXF_ID_HI	include/ssv6200_aux.h	6154;"	d
+TXF_ID_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5239;"	d
+TXF_ID_I_MSK	include/ssv6200_aux.h	6152;"	d
+TXF_ID_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5237;"	d
+TXF_ID_MSK	include/ssv6200_aux.h	6151;"	d
+TXF_ID_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5236;"	d
+TXF_ID_SFT	include/ssv6200_aux.h	6153;"	d
+TXF_ID_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5238;"	d
+TXF_ID_SZ	include/ssv6200_aux.h	6155;"	d
+TXF_ID_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5240;"	d
+TXNOTFULLFLAG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	889;"	d
+TXNOTFULLFLAG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	887;"	d
+TXNOTFULLFLAG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	886;"	d
+TXNOTFULLFLAG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	888;"	d
+TXNOTFULLFLAG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	890;"	d
+TXPB_OFFSET	include/ssv6200_common.h	50;"	d
+TXPB_OFFSET	include/ssv6xxx_common.h	60;"	d
+TXQ0_MTX_Q_AIFSN_HI	include/ssv6200_aux.h	7924;"	d
+TXQ0_MTX_Q_AIFSN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7479;"	d
+TXQ0_MTX_Q_AIFSN_I_MSK	include/ssv6200_aux.h	7922;"	d
+TXQ0_MTX_Q_AIFSN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7477;"	d
+TXQ0_MTX_Q_AIFSN_MSK	include/ssv6200_aux.h	7921;"	d
+TXQ0_MTX_Q_AIFSN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7476;"	d
+TXQ0_MTX_Q_AIFSN_SFT	include/ssv6200_aux.h	7923;"	d
+TXQ0_MTX_Q_AIFSN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7478;"	d
+TXQ0_MTX_Q_AIFSN_SZ	include/ssv6200_aux.h	7925;"	d
+TXQ0_MTX_Q_AIFSN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7480;"	d
+TXQ0_MTX_Q_BKF_CNT_FIXED_HI	include/ssv6200_aux.h	7899;"	d
+TXQ0_MTX_Q_BKF_CNT_FIXED_I_MSK	include/ssv6200_aux.h	7897;"	d
+TXQ0_MTX_Q_BKF_CNT_FIXED_MSK	include/ssv6200_aux.h	7896;"	d
+TXQ0_MTX_Q_BKF_CNT_FIXED_SFT	include/ssv6200_aux.h	7898;"	d
+TXQ0_MTX_Q_BKF_CNT_FIXED_SZ	include/ssv6200_aux.h	7900;"	d
+TXQ0_MTX_Q_BKF_CNT_FIX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7499;"	d
+TXQ0_MTX_Q_BKF_CNT_FIX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7497;"	d
+TXQ0_MTX_Q_BKF_CNT_FIX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7496;"	d
+TXQ0_MTX_Q_BKF_CNT_FIX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7498;"	d
+TXQ0_MTX_Q_BKF_CNT_FIX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7500;"	d
+TXQ0_MTX_Q_BKF_CNT_HI	include/ssv6200_aux.h	7944;"	d
+TXQ0_MTX_Q_BKF_CNT_I_MSK	include/ssv6200_aux.h	7942;"	d
+TXQ0_MTX_Q_BKF_CNT_MSK	include/ssv6200_aux.h	7941;"	d
+TXQ0_MTX_Q_BKF_CNT_SFT	include/ssv6200_aux.h	7943;"	d
+TXQ0_MTX_Q_BKF_CNT_SZ	include/ssv6200_aux.h	7945;"	d
+TXQ0_MTX_Q_ECWMAX_HI	include/ssv6200_aux.h	7934;"	d
+TXQ0_MTX_Q_ECWMAX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7489;"	d
+TXQ0_MTX_Q_ECWMAX_I_MSK	include/ssv6200_aux.h	7932;"	d
+TXQ0_MTX_Q_ECWMAX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7487;"	d
+TXQ0_MTX_Q_ECWMAX_MSK	include/ssv6200_aux.h	7931;"	d
+TXQ0_MTX_Q_ECWMAX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7486;"	d
+TXQ0_MTX_Q_ECWMAX_SFT	include/ssv6200_aux.h	7933;"	d
+TXQ0_MTX_Q_ECWMAX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7488;"	d
+TXQ0_MTX_Q_ECWMAX_SZ	include/ssv6200_aux.h	7935;"	d
+TXQ0_MTX_Q_ECWMAX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7490;"	d
+TXQ0_MTX_Q_ECWMIN_HI	include/ssv6200_aux.h	7929;"	d
+TXQ0_MTX_Q_ECWMIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7484;"	d
+TXQ0_MTX_Q_ECWMIN_I_MSK	include/ssv6200_aux.h	7927;"	d
+TXQ0_MTX_Q_ECWMIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7482;"	d
+TXQ0_MTX_Q_ECWMIN_MSK	include/ssv6200_aux.h	7926;"	d
+TXQ0_MTX_Q_ECWMIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7481;"	d
+TXQ0_MTX_Q_ECWMIN_SFT	include/ssv6200_aux.h	7928;"	d
+TXQ0_MTX_Q_ECWMIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7483;"	d
+TXQ0_MTX_Q_ECWMIN_SZ	include/ssv6200_aux.h	7930;"	d
+TXQ0_MTX_Q_ECWMIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7485;"	d
+TXQ0_MTX_Q_ID_MAP_L_HI	include/ssv6200_aux.h	7959;"	d
+TXQ0_MTX_Q_ID_MAP_L_I_MSK	include/ssv6200_aux.h	7957;"	d
+TXQ0_MTX_Q_ID_MAP_L_MSK	include/ssv6200_aux.h	7956;"	d
+TXQ0_MTX_Q_ID_MAP_L_SFT	include/ssv6200_aux.h	7958;"	d
+TXQ0_MTX_Q_ID_MAP_L_SZ	include/ssv6200_aux.h	7960;"	d
+TXQ0_MTX_Q_LRC_LIMIT_HI	include/ssv6200_aux.h	7954;"	d
+TXQ0_MTX_Q_LRC_LIMIT_I_MSK	include/ssv6200_aux.h	7952;"	d
+TXQ0_MTX_Q_LRC_LIMIT_MSK	include/ssv6200_aux.h	7951;"	d
+TXQ0_MTX_Q_LRC_LIMIT_SFT	include/ssv6200_aux.h	7953;"	d
+TXQ0_MTX_Q_LRC_LIMIT_SZ	include/ssv6200_aux.h	7955;"	d
+TXQ0_MTX_Q_MB_NO_RLS_HI	include/ssv6200_aux.h	7909;"	d
+TXQ0_MTX_Q_MB_NO_RLS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7469;"	d
+TXQ0_MTX_Q_MB_NO_RLS_I_MSK	include/ssv6200_aux.h	7907;"	d
+TXQ0_MTX_Q_MB_NO_RLS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7467;"	d
+TXQ0_MTX_Q_MB_NO_RLS_MSK	include/ssv6200_aux.h	7906;"	d
+TXQ0_MTX_Q_MB_NO_RLS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7466;"	d
+TXQ0_MTX_Q_MB_NO_RLS_SFT	include/ssv6200_aux.h	7908;"	d
+TXQ0_MTX_Q_MB_NO_RLS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7468;"	d
+TXQ0_MTX_Q_MB_NO_RLS_SZ	include/ssv6200_aux.h	7910;"	d
+TXQ0_MTX_Q_MB_NO_RLS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7470;"	d
+TXQ0_MTX_Q_PRE_LD_HI	include/ssv6200_aux.h	7894;"	d
+TXQ0_MTX_Q_PRE_LD_I_MSK	include/ssv6200_aux.h	7892;"	d
+TXQ0_MTX_Q_PRE_LD_MSK	include/ssv6200_aux.h	7891;"	d
+TXQ0_MTX_Q_PRE_LD_SFT	include/ssv6200_aux.h	7893;"	d
+TXQ0_MTX_Q_PRE_LD_SZ	include/ssv6200_aux.h	7895;"	d
+TXQ0_MTX_Q_RND_MODE_HI	include/ssv6200_aux.h	7919;"	d
+TXQ0_MTX_Q_RND_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7464;"	d
+TXQ0_MTX_Q_RND_MODE_I_MSK	include/ssv6200_aux.h	7917;"	d
+TXQ0_MTX_Q_RND_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7462;"	d
+TXQ0_MTX_Q_RND_MODE_MSK	include/ssv6200_aux.h	7916;"	d
+TXQ0_MTX_Q_RND_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7461;"	d
+TXQ0_MTX_Q_RND_MODE_SFT	include/ssv6200_aux.h	7918;"	d
+TXQ0_MTX_Q_RND_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7463;"	d
+TXQ0_MTX_Q_RND_MODE_SZ	include/ssv6200_aux.h	7920;"	d
+TXQ0_MTX_Q_RND_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7465;"	d
+TXQ0_MTX_Q_SRC_LIMIT_HI	include/ssv6200_aux.h	7949;"	d
+TXQ0_MTX_Q_SRC_LIMIT_I_MSK	include/ssv6200_aux.h	7947;"	d
+TXQ0_MTX_Q_SRC_LIMIT_MSK	include/ssv6200_aux.h	7946;"	d
+TXQ0_MTX_Q_SRC_LIMIT_SFT	include/ssv6200_aux.h	7948;"	d
+TXQ0_MTX_Q_SRC_LIMIT_SZ	include/ssv6200_aux.h	7950;"	d
+TXQ0_MTX_Q_TXOP_CH_THD_HI	include/ssv6200_aux.h	7964;"	d
+TXQ0_MTX_Q_TXOP_CH_THD_I_MSK	include/ssv6200_aux.h	7962;"	d
+TXQ0_MTX_Q_TXOP_CH_THD_MSK	include/ssv6200_aux.h	7961;"	d
+TXQ0_MTX_Q_TXOP_CH_THD_SFT	include/ssv6200_aux.h	7963;"	d
+TXQ0_MTX_Q_TXOP_CH_THD_SZ	include/ssv6200_aux.h	7965;"	d
+TXQ0_MTX_Q_TXOP_FRC_BUR_HI	include/ssv6200_aux.h	7914;"	d
+TXQ0_MTX_Q_TXOP_FRC_BUR_I_MSK	include/ssv6200_aux.h	7912;"	d
+TXQ0_MTX_Q_TXOP_FRC_BUR_MSK	include/ssv6200_aux.h	7911;"	d
+TXQ0_MTX_Q_TXOP_FRC_BUR_SFT	include/ssv6200_aux.h	7913;"	d
+TXQ0_MTX_Q_TXOP_FRC_BUR_SZ	include/ssv6200_aux.h	7915;"	d
+TXQ0_MTX_Q_TXOP_LIMIT_HI	include/ssv6200_aux.h	7939;"	d
+TXQ0_MTX_Q_TXOP_LIMIT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7494;"	d
+TXQ0_MTX_Q_TXOP_LIMIT_I_MSK	include/ssv6200_aux.h	7937;"	d
+TXQ0_MTX_Q_TXOP_LIMIT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7492;"	d
+TXQ0_MTX_Q_TXOP_LIMIT_MSK	include/ssv6200_aux.h	7936;"	d
+TXQ0_MTX_Q_TXOP_LIMIT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7491;"	d
+TXQ0_MTX_Q_TXOP_LIMIT_SFT	include/ssv6200_aux.h	7938;"	d
+TXQ0_MTX_Q_TXOP_LIMIT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7493;"	d
+TXQ0_MTX_Q_TXOP_LIMIT_SZ	include/ssv6200_aux.h	7940;"	d
+TXQ0_MTX_Q_TXOP_LIMIT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7495;"	d
+TXQ0_MTX_Q_TXOP_OV_THD_HI	include/ssv6200_aux.h	7969;"	d
+TXQ0_MTX_Q_TXOP_OV_THD_I_MSK	include/ssv6200_aux.h	7967;"	d
+TXQ0_MTX_Q_TXOP_OV_THD_MSK	include/ssv6200_aux.h	7966;"	d
+TXQ0_MTX_Q_TXOP_OV_THD_SFT	include/ssv6200_aux.h	7968;"	d
+TXQ0_MTX_Q_TXOP_OV_THD_SZ	include/ssv6200_aux.h	7970;"	d
+TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_HI	include/ssv6200_aux.h	7904;"	d
+TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK	include/ssv6200_aux.h	7902;"	d
+TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_MSK	include/ssv6200_aux.h	7901;"	d
+TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_SFT	include/ssv6200_aux.h	7903;"	d
+TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_SZ	include/ssv6200_aux.h	7905;"	d
+TXQ0_MT_Q_REG_CSR_BANK_SIZE	include/ssv6200_reg.h	98;"	d
+TXQ0_MT_Q_REG_CSR_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	117;"	d
+TXQ0_MT_Q_REG_CSR_BASE	include/ssv6200_reg.h	49;"	d
+TXQ0_MT_Q_REG_CSR_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	56;"	d
+TXQ0_Q_NULLDATAFRAME_GEN_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7474;"	d
+TXQ0_Q_NULLDATAFRAME_GEN_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7472;"	d
+TXQ0_Q_NULLDATAFRAME_GEN_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7471;"	d
+TXQ0_Q_NULLDATAFRAME_GEN_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7473;"	d
+TXQ0_Q_NULLDATAFRAME_GEN_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7475;"	d
+TXQ0_RO_AIFS_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7519;"	d
+TXQ0_RO_AIFS_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7517;"	d
+TXQ0_RO_AIFS_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7516;"	d
+TXQ0_RO_AIFS_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7518;"	d
+TXQ0_RO_AIFS_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7520;"	d
+TXQ0_RO_BKF_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7524;"	d
+TXQ0_RO_BKF_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7522;"	d
+TXQ0_RO_BKF_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7521;"	d
+TXQ0_RO_BKF_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7523;"	d
+TXQ0_RO_BKF_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7525;"	d
+TXQ0_RO_FSM_TXQ_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7504;"	d
+TXQ0_RO_FSM_TXQ_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7502;"	d
+TXQ0_RO_FSM_TXQ_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7501;"	d
+TXQ0_RO_FSM_TXQ_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7503;"	d
+TXQ0_RO_FSM_TXQ_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7505;"	d
+TXQ0_RO_PKTID_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7529;"	d
+TXQ0_RO_PKTID_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7527;"	d
+TXQ0_RO_PKTID_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7526;"	d
+TXQ0_RO_PKTID_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7528;"	d
+TXQ0_RO_PKTID_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7530;"	d
+TXQ0_RO_RATESET_IDX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7514;"	d
+TXQ0_RO_RATESET_IDX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7512;"	d
+TXQ0_RO_RATESET_IDX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7511;"	d
+TXQ0_RO_RATESET_IDX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7513;"	d
+TXQ0_RO_RATESET_IDX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7515;"	d
+TXQ0_RO_TRY_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7509;"	d
+TXQ0_RO_TRY_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7507;"	d
+TXQ0_RO_TRY_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7506;"	d
+TXQ0_RO_TRY_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7508;"	d
+TXQ0_RO_TRY_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7510;"	d
+TXQ1_MTX_Q_AIFSN_HI	include/ssv6200_aux.h	8004;"	d
+TXQ1_MTX_Q_AIFSN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7549;"	d
+TXQ1_MTX_Q_AIFSN_I_MSK	include/ssv6200_aux.h	8002;"	d
+TXQ1_MTX_Q_AIFSN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7547;"	d
+TXQ1_MTX_Q_AIFSN_MSK	include/ssv6200_aux.h	8001;"	d
+TXQ1_MTX_Q_AIFSN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7546;"	d
+TXQ1_MTX_Q_AIFSN_SFT	include/ssv6200_aux.h	8003;"	d
+TXQ1_MTX_Q_AIFSN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7548;"	d
+TXQ1_MTX_Q_AIFSN_SZ	include/ssv6200_aux.h	8005;"	d
+TXQ1_MTX_Q_AIFSN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7550;"	d
+TXQ1_MTX_Q_BKF_CNT_FIXED_HI	include/ssv6200_aux.h	7979;"	d
+TXQ1_MTX_Q_BKF_CNT_FIXED_I_MSK	include/ssv6200_aux.h	7977;"	d
+TXQ1_MTX_Q_BKF_CNT_FIXED_MSK	include/ssv6200_aux.h	7976;"	d
+TXQ1_MTX_Q_BKF_CNT_FIXED_SFT	include/ssv6200_aux.h	7978;"	d
+TXQ1_MTX_Q_BKF_CNT_FIXED_SZ	include/ssv6200_aux.h	7980;"	d
+TXQ1_MTX_Q_BKF_CNT_FIX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7569;"	d
+TXQ1_MTX_Q_BKF_CNT_FIX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7567;"	d
+TXQ1_MTX_Q_BKF_CNT_FIX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7566;"	d
+TXQ1_MTX_Q_BKF_CNT_FIX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7568;"	d
+TXQ1_MTX_Q_BKF_CNT_FIX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7570;"	d
+TXQ1_MTX_Q_BKF_CNT_HI	include/ssv6200_aux.h	8024;"	d
+TXQ1_MTX_Q_BKF_CNT_I_MSK	include/ssv6200_aux.h	8022;"	d
+TXQ1_MTX_Q_BKF_CNT_MSK	include/ssv6200_aux.h	8021;"	d
+TXQ1_MTX_Q_BKF_CNT_SFT	include/ssv6200_aux.h	8023;"	d
+TXQ1_MTX_Q_BKF_CNT_SZ	include/ssv6200_aux.h	8025;"	d
+TXQ1_MTX_Q_ECWMAX_HI	include/ssv6200_aux.h	8014;"	d
+TXQ1_MTX_Q_ECWMAX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7559;"	d
+TXQ1_MTX_Q_ECWMAX_I_MSK	include/ssv6200_aux.h	8012;"	d
+TXQ1_MTX_Q_ECWMAX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7557;"	d
+TXQ1_MTX_Q_ECWMAX_MSK	include/ssv6200_aux.h	8011;"	d
+TXQ1_MTX_Q_ECWMAX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7556;"	d
+TXQ1_MTX_Q_ECWMAX_SFT	include/ssv6200_aux.h	8013;"	d
+TXQ1_MTX_Q_ECWMAX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7558;"	d
+TXQ1_MTX_Q_ECWMAX_SZ	include/ssv6200_aux.h	8015;"	d
+TXQ1_MTX_Q_ECWMAX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7560;"	d
+TXQ1_MTX_Q_ECWMIN_HI	include/ssv6200_aux.h	8009;"	d
+TXQ1_MTX_Q_ECWMIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7554;"	d
+TXQ1_MTX_Q_ECWMIN_I_MSK	include/ssv6200_aux.h	8007;"	d
+TXQ1_MTX_Q_ECWMIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7552;"	d
+TXQ1_MTX_Q_ECWMIN_MSK	include/ssv6200_aux.h	8006;"	d
+TXQ1_MTX_Q_ECWMIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7551;"	d
+TXQ1_MTX_Q_ECWMIN_SFT	include/ssv6200_aux.h	8008;"	d
+TXQ1_MTX_Q_ECWMIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7553;"	d
+TXQ1_MTX_Q_ECWMIN_SZ	include/ssv6200_aux.h	8010;"	d
+TXQ1_MTX_Q_ECWMIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7555;"	d
+TXQ1_MTX_Q_ID_MAP_L_HI	include/ssv6200_aux.h	8039;"	d
+TXQ1_MTX_Q_ID_MAP_L_I_MSK	include/ssv6200_aux.h	8037;"	d
+TXQ1_MTX_Q_ID_MAP_L_MSK	include/ssv6200_aux.h	8036;"	d
+TXQ1_MTX_Q_ID_MAP_L_SFT	include/ssv6200_aux.h	8038;"	d
+TXQ1_MTX_Q_ID_MAP_L_SZ	include/ssv6200_aux.h	8040;"	d
+TXQ1_MTX_Q_LRC_LIMIT_HI	include/ssv6200_aux.h	8034;"	d
+TXQ1_MTX_Q_LRC_LIMIT_I_MSK	include/ssv6200_aux.h	8032;"	d
+TXQ1_MTX_Q_LRC_LIMIT_MSK	include/ssv6200_aux.h	8031;"	d
+TXQ1_MTX_Q_LRC_LIMIT_SFT	include/ssv6200_aux.h	8033;"	d
+TXQ1_MTX_Q_LRC_LIMIT_SZ	include/ssv6200_aux.h	8035;"	d
+TXQ1_MTX_Q_MB_NO_RLS_HI	include/ssv6200_aux.h	7989;"	d
+TXQ1_MTX_Q_MB_NO_RLS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7539;"	d
+TXQ1_MTX_Q_MB_NO_RLS_I_MSK	include/ssv6200_aux.h	7987;"	d
+TXQ1_MTX_Q_MB_NO_RLS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7537;"	d
+TXQ1_MTX_Q_MB_NO_RLS_MSK	include/ssv6200_aux.h	7986;"	d
+TXQ1_MTX_Q_MB_NO_RLS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7536;"	d
+TXQ1_MTX_Q_MB_NO_RLS_SFT	include/ssv6200_aux.h	7988;"	d
+TXQ1_MTX_Q_MB_NO_RLS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7538;"	d
+TXQ1_MTX_Q_MB_NO_RLS_SZ	include/ssv6200_aux.h	7990;"	d
+TXQ1_MTX_Q_MB_NO_RLS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7540;"	d
+TXQ1_MTX_Q_PRE_LD_HI	include/ssv6200_aux.h	7974;"	d
+TXQ1_MTX_Q_PRE_LD_I_MSK	include/ssv6200_aux.h	7972;"	d
+TXQ1_MTX_Q_PRE_LD_MSK	include/ssv6200_aux.h	7971;"	d
+TXQ1_MTX_Q_PRE_LD_SFT	include/ssv6200_aux.h	7973;"	d
+TXQ1_MTX_Q_PRE_LD_SZ	include/ssv6200_aux.h	7975;"	d
+TXQ1_MTX_Q_RND_MODE_HI	include/ssv6200_aux.h	7999;"	d
+TXQ1_MTX_Q_RND_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7534;"	d
+TXQ1_MTX_Q_RND_MODE_I_MSK	include/ssv6200_aux.h	7997;"	d
+TXQ1_MTX_Q_RND_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7532;"	d
+TXQ1_MTX_Q_RND_MODE_MSK	include/ssv6200_aux.h	7996;"	d
+TXQ1_MTX_Q_RND_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7531;"	d
+TXQ1_MTX_Q_RND_MODE_SFT	include/ssv6200_aux.h	7998;"	d
+TXQ1_MTX_Q_RND_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7533;"	d
+TXQ1_MTX_Q_RND_MODE_SZ	include/ssv6200_aux.h	8000;"	d
+TXQ1_MTX_Q_RND_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7535;"	d
+TXQ1_MTX_Q_SRC_LIMIT_HI	include/ssv6200_aux.h	8029;"	d
+TXQ1_MTX_Q_SRC_LIMIT_I_MSK	include/ssv6200_aux.h	8027;"	d
+TXQ1_MTX_Q_SRC_LIMIT_MSK	include/ssv6200_aux.h	8026;"	d
+TXQ1_MTX_Q_SRC_LIMIT_SFT	include/ssv6200_aux.h	8028;"	d
+TXQ1_MTX_Q_SRC_LIMIT_SZ	include/ssv6200_aux.h	8030;"	d
+TXQ1_MTX_Q_TXOP_CH_THD_HI	include/ssv6200_aux.h	8044;"	d
+TXQ1_MTX_Q_TXOP_CH_THD_I_MSK	include/ssv6200_aux.h	8042;"	d
+TXQ1_MTX_Q_TXOP_CH_THD_MSK	include/ssv6200_aux.h	8041;"	d
+TXQ1_MTX_Q_TXOP_CH_THD_SFT	include/ssv6200_aux.h	8043;"	d
+TXQ1_MTX_Q_TXOP_CH_THD_SZ	include/ssv6200_aux.h	8045;"	d
+TXQ1_MTX_Q_TXOP_FRC_BUR_HI	include/ssv6200_aux.h	7994;"	d
+TXQ1_MTX_Q_TXOP_FRC_BUR_I_MSK	include/ssv6200_aux.h	7992;"	d
+TXQ1_MTX_Q_TXOP_FRC_BUR_MSK	include/ssv6200_aux.h	7991;"	d
+TXQ1_MTX_Q_TXOP_FRC_BUR_SFT	include/ssv6200_aux.h	7993;"	d
+TXQ1_MTX_Q_TXOP_FRC_BUR_SZ	include/ssv6200_aux.h	7995;"	d
+TXQ1_MTX_Q_TXOP_LIMIT_HI	include/ssv6200_aux.h	8019;"	d
+TXQ1_MTX_Q_TXOP_LIMIT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7564;"	d
+TXQ1_MTX_Q_TXOP_LIMIT_I_MSK	include/ssv6200_aux.h	8017;"	d
+TXQ1_MTX_Q_TXOP_LIMIT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7562;"	d
+TXQ1_MTX_Q_TXOP_LIMIT_MSK	include/ssv6200_aux.h	8016;"	d
+TXQ1_MTX_Q_TXOP_LIMIT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7561;"	d
+TXQ1_MTX_Q_TXOP_LIMIT_SFT	include/ssv6200_aux.h	8018;"	d
+TXQ1_MTX_Q_TXOP_LIMIT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7563;"	d
+TXQ1_MTX_Q_TXOP_LIMIT_SZ	include/ssv6200_aux.h	8020;"	d
+TXQ1_MTX_Q_TXOP_LIMIT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7565;"	d
+TXQ1_MTX_Q_TXOP_OV_THD_HI	include/ssv6200_aux.h	8049;"	d
+TXQ1_MTX_Q_TXOP_OV_THD_I_MSK	include/ssv6200_aux.h	8047;"	d
+TXQ1_MTX_Q_TXOP_OV_THD_MSK	include/ssv6200_aux.h	8046;"	d
+TXQ1_MTX_Q_TXOP_OV_THD_SFT	include/ssv6200_aux.h	8048;"	d
+TXQ1_MTX_Q_TXOP_OV_THD_SZ	include/ssv6200_aux.h	8050;"	d
+TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_HI	include/ssv6200_aux.h	7984;"	d
+TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK	include/ssv6200_aux.h	7982;"	d
+TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_MSK	include/ssv6200_aux.h	7981;"	d
+TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_SFT	include/ssv6200_aux.h	7983;"	d
+TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_SZ	include/ssv6200_aux.h	7985;"	d
+TXQ1_MT_Q_REG_CSR_BANK_SIZE	include/ssv6200_reg.h	99;"	d
+TXQ1_MT_Q_REG_CSR_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	118;"	d
+TXQ1_MT_Q_REG_CSR_BASE	include/ssv6200_reg.h	50;"	d
+TXQ1_MT_Q_REG_CSR_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	57;"	d
+TXQ1_Q_NULLDATAFRAME_GEN_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7544;"	d
+TXQ1_Q_NULLDATAFRAME_GEN_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7542;"	d
+TXQ1_Q_NULLDATAFRAME_GEN_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7541;"	d
+TXQ1_Q_NULLDATAFRAME_GEN_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7543;"	d
+TXQ1_Q_NULLDATAFRAME_GEN_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7545;"	d
+TXQ1_RO_AIFS_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7589;"	d
+TXQ1_RO_AIFS_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7587;"	d
+TXQ1_RO_AIFS_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7586;"	d
+TXQ1_RO_AIFS_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7588;"	d
+TXQ1_RO_AIFS_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7590;"	d
+TXQ1_RO_BKF_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7594;"	d
+TXQ1_RO_BKF_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7592;"	d
+TXQ1_RO_BKF_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7591;"	d
+TXQ1_RO_BKF_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7593;"	d
+TXQ1_RO_BKF_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7595;"	d
+TXQ1_RO_FSM_TXQ_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7574;"	d
+TXQ1_RO_FSM_TXQ_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7572;"	d
+TXQ1_RO_FSM_TXQ_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7571;"	d
+TXQ1_RO_FSM_TXQ_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7573;"	d
+TXQ1_RO_FSM_TXQ_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7575;"	d
+TXQ1_RO_PKTID_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7599;"	d
+TXQ1_RO_PKTID_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7597;"	d
+TXQ1_RO_PKTID_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7596;"	d
+TXQ1_RO_PKTID_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7598;"	d
+TXQ1_RO_PKTID_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7600;"	d
+TXQ1_RO_RATESET_IDX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7584;"	d
+TXQ1_RO_RATESET_IDX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7582;"	d
+TXQ1_RO_RATESET_IDX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7581;"	d
+TXQ1_RO_RATESET_IDX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7583;"	d
+TXQ1_RO_RATESET_IDX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7585;"	d
+TXQ1_RO_TRY_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7579;"	d
+TXQ1_RO_TRY_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7577;"	d
+TXQ1_RO_TRY_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7576;"	d
+TXQ1_RO_TRY_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7578;"	d
+TXQ1_RO_TRY_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7580;"	d
+TXQ2_MTX_Q_AIFSN_HI	include/ssv6200_aux.h	8084;"	d
+TXQ2_MTX_Q_AIFSN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7619;"	d
+TXQ2_MTX_Q_AIFSN_I_MSK	include/ssv6200_aux.h	8082;"	d
+TXQ2_MTX_Q_AIFSN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7617;"	d
+TXQ2_MTX_Q_AIFSN_MSK	include/ssv6200_aux.h	8081;"	d
+TXQ2_MTX_Q_AIFSN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7616;"	d
+TXQ2_MTX_Q_AIFSN_SFT	include/ssv6200_aux.h	8083;"	d
+TXQ2_MTX_Q_AIFSN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7618;"	d
+TXQ2_MTX_Q_AIFSN_SZ	include/ssv6200_aux.h	8085;"	d
+TXQ2_MTX_Q_AIFSN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7620;"	d
+TXQ2_MTX_Q_BKF_CNT_FIXED_HI	include/ssv6200_aux.h	8059;"	d
+TXQ2_MTX_Q_BKF_CNT_FIXED_I_MSK	include/ssv6200_aux.h	8057;"	d
+TXQ2_MTX_Q_BKF_CNT_FIXED_MSK	include/ssv6200_aux.h	8056;"	d
+TXQ2_MTX_Q_BKF_CNT_FIXED_SFT	include/ssv6200_aux.h	8058;"	d
+TXQ2_MTX_Q_BKF_CNT_FIXED_SZ	include/ssv6200_aux.h	8060;"	d
+TXQ2_MTX_Q_BKF_CNT_FIX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7639;"	d
+TXQ2_MTX_Q_BKF_CNT_FIX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7637;"	d
+TXQ2_MTX_Q_BKF_CNT_FIX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7636;"	d
+TXQ2_MTX_Q_BKF_CNT_FIX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7638;"	d
+TXQ2_MTX_Q_BKF_CNT_FIX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7640;"	d
+TXQ2_MTX_Q_BKF_CNT_HI	include/ssv6200_aux.h	8104;"	d
+TXQ2_MTX_Q_BKF_CNT_I_MSK	include/ssv6200_aux.h	8102;"	d
+TXQ2_MTX_Q_BKF_CNT_MSK	include/ssv6200_aux.h	8101;"	d
+TXQ2_MTX_Q_BKF_CNT_SFT	include/ssv6200_aux.h	8103;"	d
+TXQ2_MTX_Q_BKF_CNT_SZ	include/ssv6200_aux.h	8105;"	d
+TXQ2_MTX_Q_ECWMAX_HI	include/ssv6200_aux.h	8094;"	d
+TXQ2_MTX_Q_ECWMAX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7629;"	d
+TXQ2_MTX_Q_ECWMAX_I_MSK	include/ssv6200_aux.h	8092;"	d
+TXQ2_MTX_Q_ECWMAX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7627;"	d
+TXQ2_MTX_Q_ECWMAX_MSK	include/ssv6200_aux.h	8091;"	d
+TXQ2_MTX_Q_ECWMAX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7626;"	d
+TXQ2_MTX_Q_ECWMAX_SFT	include/ssv6200_aux.h	8093;"	d
+TXQ2_MTX_Q_ECWMAX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7628;"	d
+TXQ2_MTX_Q_ECWMAX_SZ	include/ssv6200_aux.h	8095;"	d
+TXQ2_MTX_Q_ECWMAX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7630;"	d
+TXQ2_MTX_Q_ECWMIN_HI	include/ssv6200_aux.h	8089;"	d
+TXQ2_MTX_Q_ECWMIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7624;"	d
+TXQ2_MTX_Q_ECWMIN_I_MSK	include/ssv6200_aux.h	8087;"	d
+TXQ2_MTX_Q_ECWMIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7622;"	d
+TXQ2_MTX_Q_ECWMIN_MSK	include/ssv6200_aux.h	8086;"	d
+TXQ2_MTX_Q_ECWMIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7621;"	d
+TXQ2_MTX_Q_ECWMIN_SFT	include/ssv6200_aux.h	8088;"	d
+TXQ2_MTX_Q_ECWMIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7623;"	d
+TXQ2_MTX_Q_ECWMIN_SZ	include/ssv6200_aux.h	8090;"	d
+TXQ2_MTX_Q_ECWMIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7625;"	d
+TXQ2_MTX_Q_ID_MAP_L_HI	include/ssv6200_aux.h	8119;"	d
+TXQ2_MTX_Q_ID_MAP_L_I_MSK	include/ssv6200_aux.h	8117;"	d
+TXQ2_MTX_Q_ID_MAP_L_MSK	include/ssv6200_aux.h	8116;"	d
+TXQ2_MTX_Q_ID_MAP_L_SFT	include/ssv6200_aux.h	8118;"	d
+TXQ2_MTX_Q_ID_MAP_L_SZ	include/ssv6200_aux.h	8120;"	d
+TXQ2_MTX_Q_LRC_LIMIT_HI	include/ssv6200_aux.h	8114;"	d
+TXQ2_MTX_Q_LRC_LIMIT_I_MSK	include/ssv6200_aux.h	8112;"	d
+TXQ2_MTX_Q_LRC_LIMIT_MSK	include/ssv6200_aux.h	8111;"	d
+TXQ2_MTX_Q_LRC_LIMIT_SFT	include/ssv6200_aux.h	8113;"	d
+TXQ2_MTX_Q_LRC_LIMIT_SZ	include/ssv6200_aux.h	8115;"	d
+TXQ2_MTX_Q_MB_NO_RLS_HI	include/ssv6200_aux.h	8069;"	d
+TXQ2_MTX_Q_MB_NO_RLS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7609;"	d
+TXQ2_MTX_Q_MB_NO_RLS_I_MSK	include/ssv6200_aux.h	8067;"	d
+TXQ2_MTX_Q_MB_NO_RLS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7607;"	d
+TXQ2_MTX_Q_MB_NO_RLS_MSK	include/ssv6200_aux.h	8066;"	d
+TXQ2_MTX_Q_MB_NO_RLS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7606;"	d
+TXQ2_MTX_Q_MB_NO_RLS_SFT	include/ssv6200_aux.h	8068;"	d
+TXQ2_MTX_Q_MB_NO_RLS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7608;"	d
+TXQ2_MTX_Q_MB_NO_RLS_SZ	include/ssv6200_aux.h	8070;"	d
+TXQ2_MTX_Q_MB_NO_RLS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7610;"	d
+TXQ2_MTX_Q_PRE_LD_HI	include/ssv6200_aux.h	8054;"	d
+TXQ2_MTX_Q_PRE_LD_I_MSK	include/ssv6200_aux.h	8052;"	d
+TXQ2_MTX_Q_PRE_LD_MSK	include/ssv6200_aux.h	8051;"	d
+TXQ2_MTX_Q_PRE_LD_SFT	include/ssv6200_aux.h	8053;"	d
+TXQ2_MTX_Q_PRE_LD_SZ	include/ssv6200_aux.h	8055;"	d
+TXQ2_MTX_Q_RND_MODE_HI	include/ssv6200_aux.h	8079;"	d
+TXQ2_MTX_Q_RND_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7604;"	d
+TXQ2_MTX_Q_RND_MODE_I_MSK	include/ssv6200_aux.h	8077;"	d
+TXQ2_MTX_Q_RND_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7602;"	d
+TXQ2_MTX_Q_RND_MODE_MSK	include/ssv6200_aux.h	8076;"	d
+TXQ2_MTX_Q_RND_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7601;"	d
+TXQ2_MTX_Q_RND_MODE_SFT	include/ssv6200_aux.h	8078;"	d
+TXQ2_MTX_Q_RND_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7603;"	d
+TXQ2_MTX_Q_RND_MODE_SZ	include/ssv6200_aux.h	8080;"	d
+TXQ2_MTX_Q_RND_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7605;"	d
+TXQ2_MTX_Q_SRC_LIMIT_HI	include/ssv6200_aux.h	8109;"	d
+TXQ2_MTX_Q_SRC_LIMIT_I_MSK	include/ssv6200_aux.h	8107;"	d
+TXQ2_MTX_Q_SRC_LIMIT_MSK	include/ssv6200_aux.h	8106;"	d
+TXQ2_MTX_Q_SRC_LIMIT_SFT	include/ssv6200_aux.h	8108;"	d
+TXQ2_MTX_Q_SRC_LIMIT_SZ	include/ssv6200_aux.h	8110;"	d
+TXQ2_MTX_Q_TXOP_CH_THD_HI	include/ssv6200_aux.h	8124;"	d
+TXQ2_MTX_Q_TXOP_CH_THD_I_MSK	include/ssv6200_aux.h	8122;"	d
+TXQ2_MTX_Q_TXOP_CH_THD_MSK	include/ssv6200_aux.h	8121;"	d
+TXQ2_MTX_Q_TXOP_CH_THD_SFT	include/ssv6200_aux.h	8123;"	d
+TXQ2_MTX_Q_TXOP_CH_THD_SZ	include/ssv6200_aux.h	8125;"	d
+TXQ2_MTX_Q_TXOP_FRC_BUR_HI	include/ssv6200_aux.h	8074;"	d
+TXQ2_MTX_Q_TXOP_FRC_BUR_I_MSK	include/ssv6200_aux.h	8072;"	d
+TXQ2_MTX_Q_TXOP_FRC_BUR_MSK	include/ssv6200_aux.h	8071;"	d
+TXQ2_MTX_Q_TXOP_FRC_BUR_SFT	include/ssv6200_aux.h	8073;"	d
+TXQ2_MTX_Q_TXOP_FRC_BUR_SZ	include/ssv6200_aux.h	8075;"	d
+TXQ2_MTX_Q_TXOP_LIMIT_HI	include/ssv6200_aux.h	8099;"	d
+TXQ2_MTX_Q_TXOP_LIMIT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7634;"	d
+TXQ2_MTX_Q_TXOP_LIMIT_I_MSK	include/ssv6200_aux.h	8097;"	d
+TXQ2_MTX_Q_TXOP_LIMIT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7632;"	d
+TXQ2_MTX_Q_TXOP_LIMIT_MSK	include/ssv6200_aux.h	8096;"	d
+TXQ2_MTX_Q_TXOP_LIMIT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7631;"	d
+TXQ2_MTX_Q_TXOP_LIMIT_SFT	include/ssv6200_aux.h	8098;"	d
+TXQ2_MTX_Q_TXOP_LIMIT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7633;"	d
+TXQ2_MTX_Q_TXOP_LIMIT_SZ	include/ssv6200_aux.h	8100;"	d
+TXQ2_MTX_Q_TXOP_LIMIT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7635;"	d
+TXQ2_MTX_Q_TXOP_OV_THD_HI	include/ssv6200_aux.h	8129;"	d
+TXQ2_MTX_Q_TXOP_OV_THD_I_MSK	include/ssv6200_aux.h	8127;"	d
+TXQ2_MTX_Q_TXOP_OV_THD_MSK	include/ssv6200_aux.h	8126;"	d
+TXQ2_MTX_Q_TXOP_OV_THD_SFT	include/ssv6200_aux.h	8128;"	d
+TXQ2_MTX_Q_TXOP_OV_THD_SZ	include/ssv6200_aux.h	8130;"	d
+TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_HI	include/ssv6200_aux.h	8064;"	d
+TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK	include/ssv6200_aux.h	8062;"	d
+TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_MSK	include/ssv6200_aux.h	8061;"	d
+TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_SFT	include/ssv6200_aux.h	8063;"	d
+TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_SZ	include/ssv6200_aux.h	8065;"	d
+TXQ2_MT_Q_REG_CSR_BANK_SIZE	include/ssv6200_reg.h	100;"	d
+TXQ2_MT_Q_REG_CSR_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	119;"	d
+TXQ2_MT_Q_REG_CSR_BASE	include/ssv6200_reg.h	51;"	d
+TXQ2_MT_Q_REG_CSR_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	58;"	d
+TXQ2_Q_NULLDATAFRAME_GEN_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7614;"	d
+TXQ2_Q_NULLDATAFRAME_GEN_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7612;"	d
+TXQ2_Q_NULLDATAFRAME_GEN_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7611;"	d
+TXQ2_Q_NULLDATAFRAME_GEN_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7613;"	d
+TXQ2_Q_NULLDATAFRAME_GEN_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7615;"	d
+TXQ2_RO_AIFS_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7659;"	d
+TXQ2_RO_AIFS_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7657;"	d
+TXQ2_RO_AIFS_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7656;"	d
+TXQ2_RO_AIFS_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7658;"	d
+TXQ2_RO_AIFS_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7660;"	d
+TXQ2_RO_BKF_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7664;"	d
+TXQ2_RO_BKF_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7662;"	d
+TXQ2_RO_BKF_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7661;"	d
+TXQ2_RO_BKF_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7663;"	d
+TXQ2_RO_BKF_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7665;"	d
+TXQ2_RO_FSM_TXQ_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7644;"	d
+TXQ2_RO_FSM_TXQ_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7642;"	d
+TXQ2_RO_FSM_TXQ_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7641;"	d
+TXQ2_RO_FSM_TXQ_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7643;"	d
+TXQ2_RO_FSM_TXQ_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7645;"	d
+TXQ2_RO_PKTID_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7669;"	d
+TXQ2_RO_PKTID_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7667;"	d
+TXQ2_RO_PKTID_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7666;"	d
+TXQ2_RO_PKTID_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7668;"	d
+TXQ2_RO_PKTID_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7670;"	d
+TXQ2_RO_RATESET_IDX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7654;"	d
+TXQ2_RO_RATESET_IDX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7652;"	d
+TXQ2_RO_RATESET_IDX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7651;"	d
+TXQ2_RO_RATESET_IDX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7653;"	d
+TXQ2_RO_RATESET_IDX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7655;"	d
+TXQ2_RO_TRY_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7649;"	d
+TXQ2_RO_TRY_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7647;"	d
+TXQ2_RO_TRY_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7646;"	d
+TXQ2_RO_TRY_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7648;"	d
+TXQ2_RO_TRY_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7650;"	d
+TXQ3_MTX_Q_AIFSN_HI	include/ssv6200_aux.h	8164;"	d
+TXQ3_MTX_Q_AIFSN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7689;"	d
+TXQ3_MTX_Q_AIFSN_I_MSK	include/ssv6200_aux.h	8162;"	d
+TXQ3_MTX_Q_AIFSN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7687;"	d
+TXQ3_MTX_Q_AIFSN_MSK	include/ssv6200_aux.h	8161;"	d
+TXQ3_MTX_Q_AIFSN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7686;"	d
+TXQ3_MTX_Q_AIFSN_SFT	include/ssv6200_aux.h	8163;"	d
+TXQ3_MTX_Q_AIFSN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7688;"	d
+TXQ3_MTX_Q_AIFSN_SZ	include/ssv6200_aux.h	8165;"	d
+TXQ3_MTX_Q_AIFSN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7690;"	d
+TXQ3_MTX_Q_BKF_CNT_FIXED_HI	include/ssv6200_aux.h	8139;"	d
+TXQ3_MTX_Q_BKF_CNT_FIXED_I_MSK	include/ssv6200_aux.h	8137;"	d
+TXQ3_MTX_Q_BKF_CNT_FIXED_MSK	include/ssv6200_aux.h	8136;"	d
+TXQ3_MTX_Q_BKF_CNT_FIXED_SFT	include/ssv6200_aux.h	8138;"	d
+TXQ3_MTX_Q_BKF_CNT_FIXED_SZ	include/ssv6200_aux.h	8140;"	d
+TXQ3_MTX_Q_BKF_CNT_FIX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7709;"	d
+TXQ3_MTX_Q_BKF_CNT_FIX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7707;"	d
+TXQ3_MTX_Q_BKF_CNT_FIX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7706;"	d
+TXQ3_MTX_Q_BKF_CNT_FIX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7708;"	d
+TXQ3_MTX_Q_BKF_CNT_FIX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7710;"	d
+TXQ3_MTX_Q_BKF_CNT_HI	include/ssv6200_aux.h	8184;"	d
+TXQ3_MTX_Q_BKF_CNT_I_MSK	include/ssv6200_aux.h	8182;"	d
+TXQ3_MTX_Q_BKF_CNT_MSK	include/ssv6200_aux.h	8181;"	d
+TXQ3_MTX_Q_BKF_CNT_SFT	include/ssv6200_aux.h	8183;"	d
+TXQ3_MTX_Q_BKF_CNT_SZ	include/ssv6200_aux.h	8185;"	d
+TXQ3_MTX_Q_ECWMAX_HI	include/ssv6200_aux.h	8174;"	d
+TXQ3_MTX_Q_ECWMAX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7699;"	d
+TXQ3_MTX_Q_ECWMAX_I_MSK	include/ssv6200_aux.h	8172;"	d
+TXQ3_MTX_Q_ECWMAX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7697;"	d
+TXQ3_MTX_Q_ECWMAX_MSK	include/ssv6200_aux.h	8171;"	d
+TXQ3_MTX_Q_ECWMAX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7696;"	d
+TXQ3_MTX_Q_ECWMAX_SFT	include/ssv6200_aux.h	8173;"	d
+TXQ3_MTX_Q_ECWMAX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7698;"	d
+TXQ3_MTX_Q_ECWMAX_SZ	include/ssv6200_aux.h	8175;"	d
+TXQ3_MTX_Q_ECWMAX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7700;"	d
+TXQ3_MTX_Q_ECWMIN_HI	include/ssv6200_aux.h	8169;"	d
+TXQ3_MTX_Q_ECWMIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7694;"	d
+TXQ3_MTX_Q_ECWMIN_I_MSK	include/ssv6200_aux.h	8167;"	d
+TXQ3_MTX_Q_ECWMIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7692;"	d
+TXQ3_MTX_Q_ECWMIN_MSK	include/ssv6200_aux.h	8166;"	d
+TXQ3_MTX_Q_ECWMIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7691;"	d
+TXQ3_MTX_Q_ECWMIN_SFT	include/ssv6200_aux.h	8168;"	d
+TXQ3_MTX_Q_ECWMIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7693;"	d
+TXQ3_MTX_Q_ECWMIN_SZ	include/ssv6200_aux.h	8170;"	d
+TXQ3_MTX_Q_ECWMIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7695;"	d
+TXQ3_MTX_Q_ID_MAP_L_HI	include/ssv6200_aux.h	8199;"	d
+TXQ3_MTX_Q_ID_MAP_L_I_MSK	include/ssv6200_aux.h	8197;"	d
+TXQ3_MTX_Q_ID_MAP_L_MSK	include/ssv6200_aux.h	8196;"	d
+TXQ3_MTX_Q_ID_MAP_L_SFT	include/ssv6200_aux.h	8198;"	d
+TXQ3_MTX_Q_ID_MAP_L_SZ	include/ssv6200_aux.h	8200;"	d
+TXQ3_MTX_Q_LRC_LIMIT_HI	include/ssv6200_aux.h	8194;"	d
+TXQ3_MTX_Q_LRC_LIMIT_I_MSK	include/ssv6200_aux.h	8192;"	d
+TXQ3_MTX_Q_LRC_LIMIT_MSK	include/ssv6200_aux.h	8191;"	d
+TXQ3_MTX_Q_LRC_LIMIT_SFT	include/ssv6200_aux.h	8193;"	d
+TXQ3_MTX_Q_LRC_LIMIT_SZ	include/ssv6200_aux.h	8195;"	d
+TXQ3_MTX_Q_MB_NO_RLS_HI	include/ssv6200_aux.h	8149;"	d
+TXQ3_MTX_Q_MB_NO_RLS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7679;"	d
+TXQ3_MTX_Q_MB_NO_RLS_I_MSK	include/ssv6200_aux.h	8147;"	d
+TXQ3_MTX_Q_MB_NO_RLS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7677;"	d
+TXQ3_MTX_Q_MB_NO_RLS_MSK	include/ssv6200_aux.h	8146;"	d
+TXQ3_MTX_Q_MB_NO_RLS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7676;"	d
+TXQ3_MTX_Q_MB_NO_RLS_SFT	include/ssv6200_aux.h	8148;"	d
+TXQ3_MTX_Q_MB_NO_RLS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7678;"	d
+TXQ3_MTX_Q_MB_NO_RLS_SZ	include/ssv6200_aux.h	8150;"	d
+TXQ3_MTX_Q_MB_NO_RLS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7680;"	d
+TXQ3_MTX_Q_PRE_LD_HI	include/ssv6200_aux.h	8134;"	d
+TXQ3_MTX_Q_PRE_LD_I_MSK	include/ssv6200_aux.h	8132;"	d
+TXQ3_MTX_Q_PRE_LD_MSK	include/ssv6200_aux.h	8131;"	d
+TXQ3_MTX_Q_PRE_LD_SFT	include/ssv6200_aux.h	8133;"	d
+TXQ3_MTX_Q_PRE_LD_SZ	include/ssv6200_aux.h	8135;"	d
+TXQ3_MTX_Q_RND_MODE_HI	include/ssv6200_aux.h	8159;"	d
+TXQ3_MTX_Q_RND_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7674;"	d
+TXQ3_MTX_Q_RND_MODE_I_MSK	include/ssv6200_aux.h	8157;"	d
+TXQ3_MTX_Q_RND_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7672;"	d
+TXQ3_MTX_Q_RND_MODE_MSK	include/ssv6200_aux.h	8156;"	d
+TXQ3_MTX_Q_RND_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7671;"	d
+TXQ3_MTX_Q_RND_MODE_SFT	include/ssv6200_aux.h	8158;"	d
+TXQ3_MTX_Q_RND_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7673;"	d
+TXQ3_MTX_Q_RND_MODE_SZ	include/ssv6200_aux.h	8160;"	d
+TXQ3_MTX_Q_RND_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7675;"	d
+TXQ3_MTX_Q_SRC_LIMIT_HI	include/ssv6200_aux.h	8189;"	d
+TXQ3_MTX_Q_SRC_LIMIT_I_MSK	include/ssv6200_aux.h	8187;"	d
+TXQ3_MTX_Q_SRC_LIMIT_MSK	include/ssv6200_aux.h	8186;"	d
+TXQ3_MTX_Q_SRC_LIMIT_SFT	include/ssv6200_aux.h	8188;"	d
+TXQ3_MTX_Q_SRC_LIMIT_SZ	include/ssv6200_aux.h	8190;"	d
+TXQ3_MTX_Q_TXOP_CH_THD_HI	include/ssv6200_aux.h	8204;"	d
+TXQ3_MTX_Q_TXOP_CH_THD_I_MSK	include/ssv6200_aux.h	8202;"	d
+TXQ3_MTX_Q_TXOP_CH_THD_MSK	include/ssv6200_aux.h	8201;"	d
+TXQ3_MTX_Q_TXOP_CH_THD_SFT	include/ssv6200_aux.h	8203;"	d
+TXQ3_MTX_Q_TXOP_CH_THD_SZ	include/ssv6200_aux.h	8205;"	d
+TXQ3_MTX_Q_TXOP_FRC_BUR_HI	include/ssv6200_aux.h	8154;"	d
+TXQ3_MTX_Q_TXOP_FRC_BUR_I_MSK	include/ssv6200_aux.h	8152;"	d
+TXQ3_MTX_Q_TXOP_FRC_BUR_MSK	include/ssv6200_aux.h	8151;"	d
+TXQ3_MTX_Q_TXOP_FRC_BUR_SFT	include/ssv6200_aux.h	8153;"	d
+TXQ3_MTX_Q_TXOP_FRC_BUR_SZ	include/ssv6200_aux.h	8155;"	d
+TXQ3_MTX_Q_TXOP_LIMIT_HI	include/ssv6200_aux.h	8179;"	d
+TXQ3_MTX_Q_TXOP_LIMIT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7704;"	d
+TXQ3_MTX_Q_TXOP_LIMIT_I_MSK	include/ssv6200_aux.h	8177;"	d
+TXQ3_MTX_Q_TXOP_LIMIT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7702;"	d
+TXQ3_MTX_Q_TXOP_LIMIT_MSK	include/ssv6200_aux.h	8176;"	d
+TXQ3_MTX_Q_TXOP_LIMIT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7701;"	d
+TXQ3_MTX_Q_TXOP_LIMIT_SFT	include/ssv6200_aux.h	8178;"	d
+TXQ3_MTX_Q_TXOP_LIMIT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7703;"	d
+TXQ3_MTX_Q_TXOP_LIMIT_SZ	include/ssv6200_aux.h	8180;"	d
+TXQ3_MTX_Q_TXOP_LIMIT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7705;"	d
+TXQ3_MTX_Q_TXOP_OV_THD_HI	include/ssv6200_aux.h	8209;"	d
+TXQ3_MTX_Q_TXOP_OV_THD_I_MSK	include/ssv6200_aux.h	8207;"	d
+TXQ3_MTX_Q_TXOP_OV_THD_MSK	include/ssv6200_aux.h	8206;"	d
+TXQ3_MTX_Q_TXOP_OV_THD_SFT	include/ssv6200_aux.h	8208;"	d
+TXQ3_MTX_Q_TXOP_OV_THD_SZ	include/ssv6200_aux.h	8210;"	d
+TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_HI	include/ssv6200_aux.h	8144;"	d
+TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK	include/ssv6200_aux.h	8142;"	d
+TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_MSK	include/ssv6200_aux.h	8141;"	d
+TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_SFT	include/ssv6200_aux.h	8143;"	d
+TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_SZ	include/ssv6200_aux.h	8145;"	d
+TXQ3_MT_Q_REG_CSR_BANK_SIZE	include/ssv6200_reg.h	101;"	d
+TXQ3_MT_Q_REG_CSR_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	120;"	d
+TXQ3_MT_Q_REG_CSR_BASE	include/ssv6200_reg.h	52;"	d
+TXQ3_MT_Q_REG_CSR_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	59;"	d
+TXQ3_Q_NULLDATAFRAME_GEN_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7684;"	d
+TXQ3_Q_NULLDATAFRAME_GEN_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7682;"	d
+TXQ3_Q_NULLDATAFRAME_GEN_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7681;"	d
+TXQ3_Q_NULLDATAFRAME_GEN_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7683;"	d
+TXQ3_Q_NULLDATAFRAME_GEN_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7685;"	d
+TXQ3_RO_AIFS_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7729;"	d
+TXQ3_RO_AIFS_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7727;"	d
+TXQ3_RO_AIFS_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7726;"	d
+TXQ3_RO_AIFS_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7728;"	d
+TXQ3_RO_AIFS_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7730;"	d
+TXQ3_RO_BKF_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7734;"	d
+TXQ3_RO_BKF_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7732;"	d
+TXQ3_RO_BKF_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7731;"	d
+TXQ3_RO_BKF_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7733;"	d
+TXQ3_RO_BKF_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7735;"	d
+TXQ3_RO_FSM_TXQ_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7714;"	d
+TXQ3_RO_FSM_TXQ_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7712;"	d
+TXQ3_RO_FSM_TXQ_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7711;"	d
+TXQ3_RO_FSM_TXQ_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7713;"	d
+TXQ3_RO_FSM_TXQ_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7715;"	d
+TXQ3_RO_PKTID_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7739;"	d
+TXQ3_RO_PKTID_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7737;"	d
+TXQ3_RO_PKTID_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7736;"	d
+TXQ3_RO_PKTID_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7738;"	d
+TXQ3_RO_PKTID_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7740;"	d
+TXQ3_RO_RATESET_IDX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7724;"	d
+TXQ3_RO_RATESET_IDX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7722;"	d
+TXQ3_RO_RATESET_IDX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7721;"	d
+TXQ3_RO_RATESET_IDX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7723;"	d
+TXQ3_RO_RATESET_IDX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7725;"	d
+TXQ3_RO_TRY_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7719;"	d
+TXQ3_RO_TRY_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7717;"	d
+TXQ3_RO_TRY_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7716;"	d
+TXQ3_RO_TRY_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7718;"	d
+TXQ3_RO_TRY_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7720;"	d
+TXQ4_MTX_Q_AIFSN_HI	include/ssv6200_aux.h	8244;"	d
+TXQ4_MTX_Q_AIFSN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7759;"	d
+TXQ4_MTX_Q_AIFSN_I_MSK	include/ssv6200_aux.h	8242;"	d
+TXQ4_MTX_Q_AIFSN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7757;"	d
+TXQ4_MTX_Q_AIFSN_MSK	include/ssv6200_aux.h	8241;"	d
+TXQ4_MTX_Q_AIFSN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7756;"	d
+TXQ4_MTX_Q_AIFSN_SFT	include/ssv6200_aux.h	8243;"	d
+TXQ4_MTX_Q_AIFSN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7758;"	d
+TXQ4_MTX_Q_AIFSN_SZ	include/ssv6200_aux.h	8245;"	d
+TXQ4_MTX_Q_AIFSN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7760;"	d
+TXQ4_MTX_Q_BKF_CNT_FIXED_HI	include/ssv6200_aux.h	8219;"	d
+TXQ4_MTX_Q_BKF_CNT_FIXED_I_MSK	include/ssv6200_aux.h	8217;"	d
+TXQ4_MTX_Q_BKF_CNT_FIXED_MSK	include/ssv6200_aux.h	8216;"	d
+TXQ4_MTX_Q_BKF_CNT_FIXED_SFT	include/ssv6200_aux.h	8218;"	d
+TXQ4_MTX_Q_BKF_CNT_FIXED_SZ	include/ssv6200_aux.h	8220;"	d
+TXQ4_MTX_Q_BKF_CNT_FIX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7779;"	d
+TXQ4_MTX_Q_BKF_CNT_FIX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7777;"	d
+TXQ4_MTX_Q_BKF_CNT_FIX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7776;"	d
+TXQ4_MTX_Q_BKF_CNT_FIX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7778;"	d
+TXQ4_MTX_Q_BKF_CNT_FIX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7780;"	d
+TXQ4_MTX_Q_BKF_CNT_HI	include/ssv6200_aux.h	8264;"	d
+TXQ4_MTX_Q_BKF_CNT_I_MSK	include/ssv6200_aux.h	8262;"	d
+TXQ4_MTX_Q_BKF_CNT_MSK	include/ssv6200_aux.h	8261;"	d
+TXQ4_MTX_Q_BKF_CNT_SFT	include/ssv6200_aux.h	8263;"	d
+TXQ4_MTX_Q_BKF_CNT_SZ	include/ssv6200_aux.h	8265;"	d
+TXQ4_MTX_Q_ECWMAX_HI	include/ssv6200_aux.h	8254;"	d
+TXQ4_MTX_Q_ECWMAX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7769;"	d
+TXQ4_MTX_Q_ECWMAX_I_MSK	include/ssv6200_aux.h	8252;"	d
+TXQ4_MTX_Q_ECWMAX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7767;"	d
+TXQ4_MTX_Q_ECWMAX_MSK	include/ssv6200_aux.h	8251;"	d
+TXQ4_MTX_Q_ECWMAX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7766;"	d
+TXQ4_MTX_Q_ECWMAX_SFT	include/ssv6200_aux.h	8253;"	d
+TXQ4_MTX_Q_ECWMAX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7768;"	d
+TXQ4_MTX_Q_ECWMAX_SZ	include/ssv6200_aux.h	8255;"	d
+TXQ4_MTX_Q_ECWMAX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7770;"	d
+TXQ4_MTX_Q_ECWMIN_HI	include/ssv6200_aux.h	8249;"	d
+TXQ4_MTX_Q_ECWMIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7764;"	d
+TXQ4_MTX_Q_ECWMIN_I_MSK	include/ssv6200_aux.h	8247;"	d
+TXQ4_MTX_Q_ECWMIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7762;"	d
+TXQ4_MTX_Q_ECWMIN_MSK	include/ssv6200_aux.h	8246;"	d
+TXQ4_MTX_Q_ECWMIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7761;"	d
+TXQ4_MTX_Q_ECWMIN_SFT	include/ssv6200_aux.h	8248;"	d
+TXQ4_MTX_Q_ECWMIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7763;"	d
+TXQ4_MTX_Q_ECWMIN_SZ	include/ssv6200_aux.h	8250;"	d
+TXQ4_MTX_Q_ECWMIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7765;"	d
+TXQ4_MTX_Q_ID_MAP_L_HI	include/ssv6200_aux.h	8279;"	d
+TXQ4_MTX_Q_ID_MAP_L_I_MSK	include/ssv6200_aux.h	8277;"	d
+TXQ4_MTX_Q_ID_MAP_L_MSK	include/ssv6200_aux.h	8276;"	d
+TXQ4_MTX_Q_ID_MAP_L_SFT	include/ssv6200_aux.h	8278;"	d
+TXQ4_MTX_Q_ID_MAP_L_SZ	include/ssv6200_aux.h	8280;"	d
+TXQ4_MTX_Q_LRC_LIMIT_HI	include/ssv6200_aux.h	8274;"	d
+TXQ4_MTX_Q_LRC_LIMIT_I_MSK	include/ssv6200_aux.h	8272;"	d
+TXQ4_MTX_Q_LRC_LIMIT_MSK	include/ssv6200_aux.h	8271;"	d
+TXQ4_MTX_Q_LRC_LIMIT_SFT	include/ssv6200_aux.h	8273;"	d
+TXQ4_MTX_Q_LRC_LIMIT_SZ	include/ssv6200_aux.h	8275;"	d
+TXQ4_MTX_Q_MB_NO_RLS_HI	include/ssv6200_aux.h	8229;"	d
+TXQ4_MTX_Q_MB_NO_RLS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7749;"	d
+TXQ4_MTX_Q_MB_NO_RLS_I_MSK	include/ssv6200_aux.h	8227;"	d
+TXQ4_MTX_Q_MB_NO_RLS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7747;"	d
+TXQ4_MTX_Q_MB_NO_RLS_MSK	include/ssv6200_aux.h	8226;"	d
+TXQ4_MTX_Q_MB_NO_RLS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7746;"	d
+TXQ4_MTX_Q_MB_NO_RLS_SFT	include/ssv6200_aux.h	8228;"	d
+TXQ4_MTX_Q_MB_NO_RLS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7748;"	d
+TXQ4_MTX_Q_MB_NO_RLS_SZ	include/ssv6200_aux.h	8230;"	d
+TXQ4_MTX_Q_MB_NO_RLS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7750;"	d
+TXQ4_MTX_Q_PRE_LD_HI	include/ssv6200_aux.h	8214;"	d
+TXQ4_MTX_Q_PRE_LD_I_MSK	include/ssv6200_aux.h	8212;"	d
+TXQ4_MTX_Q_PRE_LD_MSK	include/ssv6200_aux.h	8211;"	d
+TXQ4_MTX_Q_PRE_LD_SFT	include/ssv6200_aux.h	8213;"	d
+TXQ4_MTX_Q_PRE_LD_SZ	include/ssv6200_aux.h	8215;"	d
+TXQ4_MTX_Q_RND_MODE_HI	include/ssv6200_aux.h	8239;"	d
+TXQ4_MTX_Q_RND_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7744;"	d
+TXQ4_MTX_Q_RND_MODE_I_MSK	include/ssv6200_aux.h	8237;"	d
+TXQ4_MTX_Q_RND_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7742;"	d
+TXQ4_MTX_Q_RND_MODE_MSK	include/ssv6200_aux.h	8236;"	d
+TXQ4_MTX_Q_RND_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7741;"	d
+TXQ4_MTX_Q_RND_MODE_SFT	include/ssv6200_aux.h	8238;"	d
+TXQ4_MTX_Q_RND_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7743;"	d
+TXQ4_MTX_Q_RND_MODE_SZ	include/ssv6200_aux.h	8240;"	d
+TXQ4_MTX_Q_RND_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7745;"	d
+TXQ4_MTX_Q_SRC_LIMIT_HI	include/ssv6200_aux.h	8269;"	d
+TXQ4_MTX_Q_SRC_LIMIT_I_MSK	include/ssv6200_aux.h	8267;"	d
+TXQ4_MTX_Q_SRC_LIMIT_MSK	include/ssv6200_aux.h	8266;"	d
+TXQ4_MTX_Q_SRC_LIMIT_SFT	include/ssv6200_aux.h	8268;"	d
+TXQ4_MTX_Q_SRC_LIMIT_SZ	include/ssv6200_aux.h	8270;"	d
+TXQ4_MTX_Q_TXOP_CH_THD_HI	include/ssv6200_aux.h	8284;"	d
+TXQ4_MTX_Q_TXOP_CH_THD_I_MSK	include/ssv6200_aux.h	8282;"	d
+TXQ4_MTX_Q_TXOP_CH_THD_MSK	include/ssv6200_aux.h	8281;"	d
+TXQ4_MTX_Q_TXOP_CH_THD_SFT	include/ssv6200_aux.h	8283;"	d
+TXQ4_MTX_Q_TXOP_CH_THD_SZ	include/ssv6200_aux.h	8285;"	d
+TXQ4_MTX_Q_TXOP_FRC_BUR_HI	include/ssv6200_aux.h	8234;"	d
+TXQ4_MTX_Q_TXOP_FRC_BUR_I_MSK	include/ssv6200_aux.h	8232;"	d
+TXQ4_MTX_Q_TXOP_FRC_BUR_MSK	include/ssv6200_aux.h	8231;"	d
+TXQ4_MTX_Q_TXOP_FRC_BUR_SFT	include/ssv6200_aux.h	8233;"	d
+TXQ4_MTX_Q_TXOP_FRC_BUR_SZ	include/ssv6200_aux.h	8235;"	d
+TXQ4_MTX_Q_TXOP_LIMIT_HI	include/ssv6200_aux.h	8259;"	d
+TXQ4_MTX_Q_TXOP_LIMIT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7774;"	d
+TXQ4_MTX_Q_TXOP_LIMIT_I_MSK	include/ssv6200_aux.h	8257;"	d
+TXQ4_MTX_Q_TXOP_LIMIT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7772;"	d
+TXQ4_MTX_Q_TXOP_LIMIT_MSK	include/ssv6200_aux.h	8256;"	d
+TXQ4_MTX_Q_TXOP_LIMIT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7771;"	d
+TXQ4_MTX_Q_TXOP_LIMIT_SFT	include/ssv6200_aux.h	8258;"	d
+TXQ4_MTX_Q_TXOP_LIMIT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7773;"	d
+TXQ4_MTX_Q_TXOP_LIMIT_SZ	include/ssv6200_aux.h	8260;"	d
+TXQ4_MTX_Q_TXOP_LIMIT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7775;"	d
+TXQ4_MTX_Q_TXOP_OV_THD_HI	include/ssv6200_aux.h	8289;"	d
+TXQ4_MTX_Q_TXOP_OV_THD_I_MSK	include/ssv6200_aux.h	8287;"	d
+TXQ4_MTX_Q_TXOP_OV_THD_MSK	include/ssv6200_aux.h	8286;"	d
+TXQ4_MTX_Q_TXOP_OV_THD_SFT	include/ssv6200_aux.h	8288;"	d
+TXQ4_MTX_Q_TXOP_OV_THD_SZ	include/ssv6200_aux.h	8290;"	d
+TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_HI	include/ssv6200_aux.h	8224;"	d
+TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK	include/ssv6200_aux.h	8222;"	d
+TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_MSK	include/ssv6200_aux.h	8221;"	d
+TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_SFT	include/ssv6200_aux.h	8223;"	d
+TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_SZ	include/ssv6200_aux.h	8225;"	d
+TXQ4_MT_Q_REG_CSR_BANK_SIZE	include/ssv6200_reg.h	102;"	d
+TXQ4_MT_Q_REG_CSR_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	121;"	d
+TXQ4_MT_Q_REG_CSR_BASE	include/ssv6200_reg.h	53;"	d
+TXQ4_MT_Q_REG_CSR_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	60;"	d
+TXQ4_Q_NULLDATAFRAME_GEN_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7754;"	d
+TXQ4_Q_NULLDATAFRAME_GEN_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7752;"	d
+TXQ4_Q_NULLDATAFRAME_GEN_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7751;"	d
+TXQ4_Q_NULLDATAFRAME_GEN_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7753;"	d
+TXQ4_Q_NULLDATAFRAME_GEN_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7755;"	d
+TXQ4_RO_AIFS_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7799;"	d
+TXQ4_RO_AIFS_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7797;"	d
+TXQ4_RO_AIFS_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7796;"	d
+TXQ4_RO_AIFS_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7798;"	d
+TXQ4_RO_AIFS_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7800;"	d
+TXQ4_RO_BKF_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7804;"	d
+TXQ4_RO_BKF_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7802;"	d
+TXQ4_RO_BKF_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7801;"	d
+TXQ4_RO_BKF_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7803;"	d
+TXQ4_RO_BKF_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7805;"	d
+TXQ4_RO_FSM_TXQ_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7784;"	d
+TXQ4_RO_FSM_TXQ_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7782;"	d
+TXQ4_RO_FSM_TXQ_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7781;"	d
+TXQ4_RO_FSM_TXQ_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7783;"	d
+TXQ4_RO_FSM_TXQ_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7785;"	d
+TXQ4_RO_PKTID_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7809;"	d
+TXQ4_RO_PKTID_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7807;"	d
+TXQ4_RO_PKTID_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7806;"	d
+TXQ4_RO_PKTID_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7808;"	d
+TXQ4_RO_PKTID_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7810;"	d
+TXQ4_RO_RATESET_IDX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7794;"	d
+TXQ4_RO_RATESET_IDX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7792;"	d
+TXQ4_RO_RATESET_IDX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7791;"	d
+TXQ4_RO_RATESET_IDX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7793;"	d
+TXQ4_RO_RATESET_IDX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7795;"	d
+TXQ4_RO_TRY_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7789;"	d
+TXQ4_RO_TRY_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7787;"	d
+TXQ4_RO_TRY_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7786;"	d
+TXQ4_RO_TRY_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7788;"	d
+TXQ4_RO_TRY_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7790;"	d
+TXQ5_DTIM_BEACON_BURST_MNG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7269;"	d
+TXQ5_DTIM_BEACON_BURST_MNG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7267;"	d
+TXQ5_DTIM_BEACON_BURST_MNG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7266;"	d
+TXQ5_DTIM_BEACON_BURST_MNG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7268;"	d
+TXQ5_DTIM_BEACON_BURST_MNG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7270;"	d
+TXQ5_MTX_Q_AIFSN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7829;"	d
+TXQ5_MTX_Q_AIFSN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7827;"	d
+TXQ5_MTX_Q_AIFSN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7826;"	d
+TXQ5_MTX_Q_AIFSN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7828;"	d
+TXQ5_MTX_Q_AIFSN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7830;"	d
+TXQ5_MTX_Q_BKF_CNT_FIX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7849;"	d
+TXQ5_MTX_Q_BKF_CNT_FIX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7847;"	d
+TXQ5_MTX_Q_BKF_CNT_FIX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7846;"	d
+TXQ5_MTX_Q_BKF_CNT_FIX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7848;"	d
+TXQ5_MTX_Q_BKF_CNT_FIX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7850;"	d
+TXQ5_MTX_Q_ECWMAX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7839;"	d
+TXQ5_MTX_Q_ECWMAX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7837;"	d
+TXQ5_MTX_Q_ECWMAX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7836;"	d
+TXQ5_MTX_Q_ECWMAX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7838;"	d
+TXQ5_MTX_Q_ECWMAX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7840;"	d
+TXQ5_MTX_Q_ECWMIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7834;"	d
+TXQ5_MTX_Q_ECWMIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7832;"	d
+TXQ5_MTX_Q_ECWMIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7831;"	d
+TXQ5_MTX_Q_ECWMIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7833;"	d
+TXQ5_MTX_Q_ECWMIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7835;"	d
+TXQ5_MTX_Q_MB_NO_RLS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7819;"	d
+TXQ5_MTX_Q_MB_NO_RLS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7817;"	d
+TXQ5_MTX_Q_MB_NO_RLS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7816;"	d
+TXQ5_MTX_Q_MB_NO_RLS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7818;"	d
+TXQ5_MTX_Q_MB_NO_RLS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7820;"	d
+TXQ5_MTX_Q_RND_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7814;"	d
+TXQ5_MTX_Q_RND_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7812;"	d
+TXQ5_MTX_Q_RND_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7811;"	d
+TXQ5_MTX_Q_RND_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7813;"	d
+TXQ5_MTX_Q_RND_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7815;"	d
+TXQ5_MTX_Q_TXOP_LIMIT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7844;"	d
+TXQ5_MTX_Q_TXOP_LIMIT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7842;"	d
+TXQ5_MTX_Q_TXOP_LIMIT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7841;"	d
+TXQ5_MTX_Q_TXOP_LIMIT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7843;"	d
+TXQ5_MTX_Q_TXOP_LIMIT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7845;"	d
+TXQ5_MT_Q_REG_CSR_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	122;"	d
+TXQ5_MT_Q_REG_CSR_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	61;"	d
+TXQ5_Q_NULLDATAFRAME_GEN_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7824;"	d
+TXQ5_Q_NULLDATAFRAME_GEN_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7822;"	d
+TXQ5_Q_NULLDATAFRAME_GEN_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7821;"	d
+TXQ5_Q_NULLDATAFRAME_GEN_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7823;"	d
+TXQ5_Q_NULLDATAFRAME_GEN_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7825;"	d
+TXQ5_RO_AIFS_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7869;"	d
+TXQ5_RO_AIFS_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7867;"	d
+TXQ5_RO_AIFS_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7866;"	d
+TXQ5_RO_AIFS_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7868;"	d
+TXQ5_RO_AIFS_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7870;"	d
+TXQ5_RO_BKF_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7874;"	d
+TXQ5_RO_BKF_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7872;"	d
+TXQ5_RO_BKF_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7871;"	d
+TXQ5_RO_BKF_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7873;"	d
+TXQ5_RO_BKF_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7875;"	d
+TXQ5_RO_FSM_TXQ_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7854;"	d
+TXQ5_RO_FSM_TXQ_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7852;"	d
+TXQ5_RO_FSM_TXQ_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7851;"	d
+TXQ5_RO_FSM_TXQ_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7853;"	d
+TXQ5_RO_FSM_TXQ_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7855;"	d
+TXQ5_RO_PKTID_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7879;"	d
+TXQ5_RO_PKTID_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7877;"	d
+TXQ5_RO_PKTID_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7876;"	d
+TXQ5_RO_PKTID_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7878;"	d
+TXQ5_RO_PKTID_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7880;"	d
+TXQ5_RO_RATESET_IDX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7864;"	d
+TXQ5_RO_RATESET_IDX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7862;"	d
+TXQ5_RO_RATESET_IDX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7861;"	d
+TXQ5_RO_RATESET_IDX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7863;"	d
+TXQ5_RO_RATESET_IDX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7865;"	d
+TXQ5_RO_TRY_CNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7859;"	d
+TXQ5_RO_TRY_CNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7857;"	d
+TXQ5_RO_TRY_CNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7856;"	d
+TXQ5_RO_TRY_CNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7858;"	d
+TXQ5_RO_TRY_CNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7860;"	d
+TXQ_EDCA_0	smac/dev.h	187;"	d
+TXQ_EDCA_1	smac/dev.h	188;"	d
+TXQ_EDCA_2	smac/dev.h	189;"	d
+TXQ_EDCA_3	smac/dev.h	190;"	d
+TXQ_ID0_HI	include/ssv6200_aux.h	6089;"	d
+TXQ_ID0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5139;"	d
+TXQ_ID0_I_MSK	include/ssv6200_aux.h	6087;"	d
+TXQ_ID0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5137;"	d
+TXQ_ID0_MSK	include/ssv6200_aux.h	6086;"	d
+TXQ_ID0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5136;"	d
+TXQ_ID0_SFT	include/ssv6200_aux.h	6088;"	d
+TXQ_ID0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5138;"	d
+TXQ_ID0_SZ	include/ssv6200_aux.h	6090;"	d
+TXQ_ID0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5140;"	d
+TXQ_ID1_HI	include/ssv6200_aux.h	6094;"	d
+TXQ_ID1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5144;"	d
+TXQ_ID1_I_MSK	include/ssv6200_aux.h	6092;"	d
+TXQ_ID1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5142;"	d
+TXQ_ID1_MSK	include/ssv6200_aux.h	6091;"	d
+TXQ_ID1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5141;"	d
+TXQ_ID1_SFT	include/ssv6200_aux.h	6093;"	d
+TXQ_ID1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5143;"	d
+TXQ_ID1_SZ	include/ssv6200_aux.h	6095;"	d
+TXQ_ID1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5145;"	d
+TXQ_MGMT	smac/dev.h	191;"	d
+TXSIFS_SUB_MAX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7334;"	d
+TXSIFS_SUB_MAX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7332;"	d
+TXSIFS_SUB_MAX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7331;"	d
+TXSIFS_SUB_MAX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7333;"	d
+TXSIFS_SUB_MAX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7335;"	d
+TXSIFS_SUB_MIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7329;"	d
+TXSIFS_SUB_MIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7327;"	d
+TXSIFS_SUB_MIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7326;"	d
+TXSIFS_SUB_MIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7328;"	d
+TXSIFS_SUB_MIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7330;"	d
+TXTRAP_ETHTYPE0_HI	include/ssv6200_aux.h	6199;"	d
+TXTRAP_ETHTYPE0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5334;"	d
+TXTRAP_ETHTYPE0_I_MSK	include/ssv6200_aux.h	6197;"	d
+TXTRAP_ETHTYPE0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5332;"	d
+TXTRAP_ETHTYPE0_MSK	include/ssv6200_aux.h	6196;"	d
+TXTRAP_ETHTYPE0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5331;"	d
+TXTRAP_ETHTYPE0_SFT	include/ssv6200_aux.h	6198;"	d
+TXTRAP_ETHTYPE0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5333;"	d
+TXTRAP_ETHTYPE0_SZ	include/ssv6200_aux.h	6200;"	d
+TXTRAP_ETHTYPE0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5335;"	d
+TXTRAP_ETHTYPE1_HI	include/ssv6200_aux.h	6194;"	d
+TXTRAP_ETHTYPE1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5329;"	d
+TXTRAP_ETHTYPE1_I_MSK	include/ssv6200_aux.h	6192;"	d
+TXTRAP_ETHTYPE1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5327;"	d
+TXTRAP_ETHTYPE1_MSK	include/ssv6200_aux.h	6191;"	d
+TXTRAP_ETHTYPE1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5326;"	d
+TXTRAP_ETHTYPE1_SFT	include/ssv6200_aux.h	6193;"	d
+TXTRAP_ETHTYPE1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5328;"	d
+TXTRAP_ETHTYPE1_SZ	include/ssv6200_aux.h	6195;"	d
+TXTRAP_ETHTYPE1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5330;"	d
+TX_ACK_POLICY_0_0_HI	include/ssv6200_aux.h	8324;"	d
+TX_ACK_POLICY_0_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8314;"	d
+TX_ACK_POLICY_0_0_I_MSK	include/ssv6200_aux.h	8322;"	d
+TX_ACK_POLICY_0_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8312;"	d
+TX_ACK_POLICY_0_0_MSK	include/ssv6200_aux.h	8321;"	d
+TX_ACK_POLICY_0_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8311;"	d
+TX_ACK_POLICY_0_0_SFT	include/ssv6200_aux.h	8323;"	d
+TX_ACK_POLICY_0_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8313;"	d
+TX_ACK_POLICY_0_0_SZ	include/ssv6200_aux.h	8325;"	d
+TX_ACK_POLICY_0_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8315;"	d
+TX_ACK_POLICY_0_1_HI	include/ssv6200_aux.h	8334;"	d
+TX_ACK_POLICY_0_1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8324;"	d
+TX_ACK_POLICY_0_1_I_MSK	include/ssv6200_aux.h	8332;"	d
+TX_ACK_POLICY_0_1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8322;"	d
+TX_ACK_POLICY_0_1_MSK	include/ssv6200_aux.h	8331;"	d
+TX_ACK_POLICY_0_1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8321;"	d
+TX_ACK_POLICY_0_1_SFT	include/ssv6200_aux.h	8333;"	d
+TX_ACK_POLICY_0_1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8323;"	d
+TX_ACK_POLICY_0_1_SZ	include/ssv6200_aux.h	8335;"	d
+TX_ACK_POLICY_0_1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8325;"	d
+TX_ACK_POLICY_0_2_HI	include/ssv6200_aux.h	8344;"	d
+TX_ACK_POLICY_0_2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8334;"	d
+TX_ACK_POLICY_0_2_I_MSK	include/ssv6200_aux.h	8342;"	d
+TX_ACK_POLICY_0_2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8332;"	d
+TX_ACK_POLICY_0_2_MSK	include/ssv6200_aux.h	8341;"	d
+TX_ACK_POLICY_0_2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8331;"	d
+TX_ACK_POLICY_0_2_SFT	include/ssv6200_aux.h	8343;"	d
+TX_ACK_POLICY_0_2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8333;"	d
+TX_ACK_POLICY_0_2_SZ	include/ssv6200_aux.h	8345;"	d
+TX_ACK_POLICY_0_2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8335;"	d
+TX_ACK_POLICY_0_3_HI	include/ssv6200_aux.h	8354;"	d
+TX_ACK_POLICY_0_3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8344;"	d
+TX_ACK_POLICY_0_3_I_MSK	include/ssv6200_aux.h	8352;"	d
+TX_ACK_POLICY_0_3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8342;"	d
+TX_ACK_POLICY_0_3_MSK	include/ssv6200_aux.h	8351;"	d
+TX_ACK_POLICY_0_3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8341;"	d
+TX_ACK_POLICY_0_3_SFT	include/ssv6200_aux.h	8353;"	d
+TX_ACK_POLICY_0_3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8343;"	d
+TX_ACK_POLICY_0_3_SZ	include/ssv6200_aux.h	8355;"	d
+TX_ACK_POLICY_0_3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8345;"	d
+TX_ACK_POLICY_0_4_HI	include/ssv6200_aux.h	8364;"	d
+TX_ACK_POLICY_0_4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8354;"	d
+TX_ACK_POLICY_0_4_I_MSK	include/ssv6200_aux.h	8362;"	d
+TX_ACK_POLICY_0_4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8352;"	d
+TX_ACK_POLICY_0_4_MSK	include/ssv6200_aux.h	8361;"	d
+TX_ACK_POLICY_0_4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8351;"	d
+TX_ACK_POLICY_0_4_SFT	include/ssv6200_aux.h	8363;"	d
+TX_ACK_POLICY_0_4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8353;"	d
+TX_ACK_POLICY_0_4_SZ	include/ssv6200_aux.h	8365;"	d
+TX_ACK_POLICY_0_4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8355;"	d
+TX_ACK_POLICY_0_5_HI	include/ssv6200_aux.h	8374;"	d
+TX_ACK_POLICY_0_5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8364;"	d
+TX_ACK_POLICY_0_5_I_MSK	include/ssv6200_aux.h	8372;"	d
+TX_ACK_POLICY_0_5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8362;"	d
+TX_ACK_POLICY_0_5_MSK	include/ssv6200_aux.h	8371;"	d
+TX_ACK_POLICY_0_5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8361;"	d
+TX_ACK_POLICY_0_5_SFT	include/ssv6200_aux.h	8373;"	d
+TX_ACK_POLICY_0_5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8363;"	d
+TX_ACK_POLICY_0_5_SZ	include/ssv6200_aux.h	8375;"	d
+TX_ACK_POLICY_0_5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8365;"	d
+TX_ACK_POLICY_0_6_HI	include/ssv6200_aux.h	8384;"	d
+TX_ACK_POLICY_0_6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8374;"	d
+TX_ACK_POLICY_0_6_I_MSK	include/ssv6200_aux.h	8382;"	d
+TX_ACK_POLICY_0_6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8372;"	d
+TX_ACK_POLICY_0_6_MSK	include/ssv6200_aux.h	8381;"	d
+TX_ACK_POLICY_0_6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8371;"	d
+TX_ACK_POLICY_0_6_SFT	include/ssv6200_aux.h	8383;"	d
+TX_ACK_POLICY_0_6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8373;"	d
+TX_ACK_POLICY_0_6_SZ	include/ssv6200_aux.h	8385;"	d
+TX_ACK_POLICY_0_6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8375;"	d
+TX_ACK_POLICY_0_7_HI	include/ssv6200_aux.h	8394;"	d
+TX_ACK_POLICY_0_7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8384;"	d
+TX_ACK_POLICY_0_7_I_MSK	include/ssv6200_aux.h	8392;"	d
+TX_ACK_POLICY_0_7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8382;"	d
+TX_ACK_POLICY_0_7_MSK	include/ssv6200_aux.h	8391;"	d
+TX_ACK_POLICY_0_7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8381;"	d
+TX_ACK_POLICY_0_7_SFT	include/ssv6200_aux.h	8393;"	d
+TX_ACK_POLICY_0_7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8383;"	d
+TX_ACK_POLICY_0_7_SZ	include/ssv6200_aux.h	8395;"	d
+TX_ACK_POLICY_0_7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8385;"	d
+TX_ACK_POLICY_1_0_HI	include/ssv6200_aux.h	8434;"	d
+TX_ACK_POLICY_1_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8424;"	d
+TX_ACK_POLICY_1_0_I_MSK	include/ssv6200_aux.h	8432;"	d
+TX_ACK_POLICY_1_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8422;"	d
+TX_ACK_POLICY_1_0_MSK	include/ssv6200_aux.h	8431;"	d
+TX_ACK_POLICY_1_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8421;"	d
+TX_ACK_POLICY_1_0_SFT	include/ssv6200_aux.h	8433;"	d
+TX_ACK_POLICY_1_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8423;"	d
+TX_ACK_POLICY_1_0_SZ	include/ssv6200_aux.h	8435;"	d
+TX_ACK_POLICY_1_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8425;"	d
+TX_ACK_POLICY_1_1_HI	include/ssv6200_aux.h	8444;"	d
+TX_ACK_POLICY_1_1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8434;"	d
+TX_ACK_POLICY_1_1_I_MSK	include/ssv6200_aux.h	8442;"	d
+TX_ACK_POLICY_1_1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8432;"	d
+TX_ACK_POLICY_1_1_MSK	include/ssv6200_aux.h	8441;"	d
+TX_ACK_POLICY_1_1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8431;"	d
+TX_ACK_POLICY_1_1_SFT	include/ssv6200_aux.h	8443;"	d
+TX_ACK_POLICY_1_1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8433;"	d
+TX_ACK_POLICY_1_1_SZ	include/ssv6200_aux.h	8445;"	d
+TX_ACK_POLICY_1_1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8435;"	d
+TX_ACK_POLICY_1_2_HI	include/ssv6200_aux.h	8454;"	d
+TX_ACK_POLICY_1_2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8444;"	d
+TX_ACK_POLICY_1_2_I_MSK	include/ssv6200_aux.h	8452;"	d
+TX_ACK_POLICY_1_2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8442;"	d
+TX_ACK_POLICY_1_2_MSK	include/ssv6200_aux.h	8451;"	d
+TX_ACK_POLICY_1_2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8441;"	d
+TX_ACK_POLICY_1_2_SFT	include/ssv6200_aux.h	8453;"	d
+TX_ACK_POLICY_1_2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8443;"	d
+TX_ACK_POLICY_1_2_SZ	include/ssv6200_aux.h	8455;"	d
+TX_ACK_POLICY_1_2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8445;"	d
+TX_ACK_POLICY_1_3_HI	include/ssv6200_aux.h	8464;"	d
+TX_ACK_POLICY_1_3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8454;"	d
+TX_ACK_POLICY_1_3_I_MSK	include/ssv6200_aux.h	8462;"	d
+TX_ACK_POLICY_1_3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8452;"	d
+TX_ACK_POLICY_1_3_MSK	include/ssv6200_aux.h	8461;"	d
+TX_ACK_POLICY_1_3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8451;"	d
+TX_ACK_POLICY_1_3_SFT	include/ssv6200_aux.h	8463;"	d
+TX_ACK_POLICY_1_3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8453;"	d
+TX_ACK_POLICY_1_3_SZ	include/ssv6200_aux.h	8465;"	d
+TX_ACK_POLICY_1_3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8455;"	d
+TX_ACK_POLICY_1_4_HI	include/ssv6200_aux.h	8474;"	d
+TX_ACK_POLICY_1_4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8464;"	d
+TX_ACK_POLICY_1_4_I_MSK	include/ssv6200_aux.h	8472;"	d
+TX_ACK_POLICY_1_4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8462;"	d
+TX_ACK_POLICY_1_4_MSK	include/ssv6200_aux.h	8471;"	d
+TX_ACK_POLICY_1_4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8461;"	d
+TX_ACK_POLICY_1_4_SFT	include/ssv6200_aux.h	8473;"	d
+TX_ACK_POLICY_1_4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8463;"	d
+TX_ACK_POLICY_1_4_SZ	include/ssv6200_aux.h	8475;"	d
+TX_ACK_POLICY_1_4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8465;"	d
+TX_ACK_POLICY_1_5_HI	include/ssv6200_aux.h	8484;"	d
+TX_ACK_POLICY_1_5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8474;"	d
+TX_ACK_POLICY_1_5_I_MSK	include/ssv6200_aux.h	8482;"	d
+TX_ACK_POLICY_1_5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8472;"	d
+TX_ACK_POLICY_1_5_MSK	include/ssv6200_aux.h	8481;"	d
+TX_ACK_POLICY_1_5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8471;"	d
+TX_ACK_POLICY_1_5_SFT	include/ssv6200_aux.h	8483;"	d
+TX_ACK_POLICY_1_5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8473;"	d
+TX_ACK_POLICY_1_5_SZ	include/ssv6200_aux.h	8485;"	d
+TX_ACK_POLICY_1_5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8475;"	d
+TX_ACK_POLICY_1_6_HI	include/ssv6200_aux.h	8494;"	d
+TX_ACK_POLICY_1_6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8484;"	d
+TX_ACK_POLICY_1_6_I_MSK	include/ssv6200_aux.h	8492;"	d
+TX_ACK_POLICY_1_6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8482;"	d
+TX_ACK_POLICY_1_6_MSK	include/ssv6200_aux.h	8491;"	d
+TX_ACK_POLICY_1_6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8481;"	d
+TX_ACK_POLICY_1_6_SFT	include/ssv6200_aux.h	8493;"	d
+TX_ACK_POLICY_1_6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8483;"	d
+TX_ACK_POLICY_1_6_SZ	include/ssv6200_aux.h	8495;"	d
+TX_ACK_POLICY_1_6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8485;"	d
+TX_ACK_POLICY_1_7_HI	include/ssv6200_aux.h	8504;"	d
+TX_ACK_POLICY_1_7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8494;"	d
+TX_ACK_POLICY_1_7_I_MSK	include/ssv6200_aux.h	8502;"	d
+TX_ACK_POLICY_1_7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8492;"	d
+TX_ACK_POLICY_1_7_MSK	include/ssv6200_aux.h	8501;"	d
+TX_ACK_POLICY_1_7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8491;"	d
+TX_ACK_POLICY_1_7_SFT	include/ssv6200_aux.h	8503;"	d
+TX_ACK_POLICY_1_7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8493;"	d
+TX_ACK_POLICY_1_7_SZ	include/ssv6200_aux.h	8505;"	d
+TX_ACK_POLICY_1_7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8495;"	d
+TX_ACK_POLICY_2_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9589;"	d
+TX_ACK_POLICY_2_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9587;"	d
+TX_ACK_POLICY_2_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9586;"	d
+TX_ACK_POLICY_2_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9588;"	d
+TX_ACK_POLICY_2_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9590;"	d
+TX_ACK_POLICY_2_1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9599;"	d
+TX_ACK_POLICY_2_1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9597;"	d
+TX_ACK_POLICY_2_1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9596;"	d
+TX_ACK_POLICY_2_1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9598;"	d
+TX_ACK_POLICY_2_1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9600;"	d
+TX_ACK_POLICY_2_2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9609;"	d
+TX_ACK_POLICY_2_2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9607;"	d
+TX_ACK_POLICY_2_2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9606;"	d
+TX_ACK_POLICY_2_2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9608;"	d
+TX_ACK_POLICY_2_2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9610;"	d
+TX_ACK_POLICY_2_3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9619;"	d
+TX_ACK_POLICY_2_3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9617;"	d
+TX_ACK_POLICY_2_3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9616;"	d
+TX_ACK_POLICY_2_3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9618;"	d
+TX_ACK_POLICY_2_3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9620;"	d
+TX_ACK_POLICY_2_4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9629;"	d
+TX_ACK_POLICY_2_4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9627;"	d
+TX_ACK_POLICY_2_4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9626;"	d
+TX_ACK_POLICY_2_4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9628;"	d
+TX_ACK_POLICY_2_4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9630;"	d
+TX_ACK_POLICY_2_5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9639;"	d
+TX_ACK_POLICY_2_5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9637;"	d
+TX_ACK_POLICY_2_5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9636;"	d
+TX_ACK_POLICY_2_5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9638;"	d
+TX_ACK_POLICY_2_5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9640;"	d
+TX_ACK_POLICY_2_6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9649;"	d
+TX_ACK_POLICY_2_6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9647;"	d
+TX_ACK_POLICY_2_6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9646;"	d
+TX_ACK_POLICY_2_6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9648;"	d
+TX_ACK_POLICY_2_6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9650;"	d
+TX_ACK_POLICY_2_7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9659;"	d
+TX_ACK_POLICY_2_7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9657;"	d
+TX_ACK_POLICY_2_7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9656;"	d
+TX_ACK_POLICY_2_7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9658;"	d
+TX_ACK_POLICY_2_7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9660;"	d
+TX_ACK_POLICY_3_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9699;"	d
+TX_ACK_POLICY_3_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9697;"	d
+TX_ACK_POLICY_3_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9696;"	d
+TX_ACK_POLICY_3_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9698;"	d
+TX_ACK_POLICY_3_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9700;"	d
+TX_ACK_POLICY_3_1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9709;"	d
+TX_ACK_POLICY_3_1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9707;"	d
+TX_ACK_POLICY_3_1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9706;"	d
+TX_ACK_POLICY_3_1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9708;"	d
+TX_ACK_POLICY_3_1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9710;"	d
+TX_ACK_POLICY_3_2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9719;"	d
+TX_ACK_POLICY_3_2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9717;"	d
+TX_ACK_POLICY_3_2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9716;"	d
+TX_ACK_POLICY_3_2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9718;"	d
+TX_ACK_POLICY_3_2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9720;"	d
+TX_ACK_POLICY_3_3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9729;"	d
+TX_ACK_POLICY_3_3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9727;"	d
+TX_ACK_POLICY_3_3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9726;"	d
+TX_ACK_POLICY_3_3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9728;"	d
+TX_ACK_POLICY_3_3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9730;"	d
+TX_ACK_POLICY_3_4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9739;"	d
+TX_ACK_POLICY_3_4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9737;"	d
+TX_ACK_POLICY_3_4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9736;"	d
+TX_ACK_POLICY_3_4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9738;"	d
+TX_ACK_POLICY_3_4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9740;"	d
+TX_ACK_POLICY_3_5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9749;"	d
+TX_ACK_POLICY_3_5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9747;"	d
+TX_ACK_POLICY_3_5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9746;"	d
+TX_ACK_POLICY_3_5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9748;"	d
+TX_ACK_POLICY_3_5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9750;"	d
+TX_ACK_POLICY_3_6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9759;"	d
+TX_ACK_POLICY_3_6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9757;"	d
+TX_ACK_POLICY_3_6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9756;"	d
+TX_ACK_POLICY_3_6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9758;"	d
+TX_ACK_POLICY_3_6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9760;"	d
+TX_ACK_POLICY_3_7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9769;"	d
+TX_ACK_POLICY_3_7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9767;"	d
+TX_ACK_POLICY_3_7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9766;"	d
+TX_ACK_POLICY_3_7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9768;"	d
+TX_ACK_POLICY_3_7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9770;"	d
+TX_ACK_POLICY_4_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9809;"	d
+TX_ACK_POLICY_4_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9807;"	d
+TX_ACK_POLICY_4_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9806;"	d
+TX_ACK_POLICY_4_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9808;"	d
+TX_ACK_POLICY_4_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9810;"	d
+TX_ACK_POLICY_4_1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9819;"	d
+TX_ACK_POLICY_4_1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9817;"	d
+TX_ACK_POLICY_4_1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9816;"	d
+TX_ACK_POLICY_4_1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9818;"	d
+TX_ACK_POLICY_4_1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9820;"	d
+TX_ACK_POLICY_4_2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9829;"	d
+TX_ACK_POLICY_4_2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9827;"	d
+TX_ACK_POLICY_4_2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9826;"	d
+TX_ACK_POLICY_4_2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9828;"	d
+TX_ACK_POLICY_4_2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9830;"	d
+TX_ACK_POLICY_4_3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9839;"	d
+TX_ACK_POLICY_4_3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9837;"	d
+TX_ACK_POLICY_4_3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9836;"	d
+TX_ACK_POLICY_4_3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9838;"	d
+TX_ACK_POLICY_4_3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9840;"	d
+TX_ACK_POLICY_4_4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9849;"	d
+TX_ACK_POLICY_4_4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9847;"	d
+TX_ACK_POLICY_4_4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9846;"	d
+TX_ACK_POLICY_4_4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9848;"	d
+TX_ACK_POLICY_4_4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9850;"	d
+TX_ACK_POLICY_4_5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9859;"	d
+TX_ACK_POLICY_4_5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9857;"	d
+TX_ACK_POLICY_4_5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9856;"	d
+TX_ACK_POLICY_4_5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9858;"	d
+TX_ACK_POLICY_4_5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9860;"	d
+TX_ACK_POLICY_4_6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9869;"	d
+TX_ACK_POLICY_4_6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9867;"	d
+TX_ACK_POLICY_4_6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9866;"	d
+TX_ACK_POLICY_4_6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9868;"	d
+TX_ACK_POLICY_4_6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9870;"	d
+TX_ACK_POLICY_4_7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9879;"	d
+TX_ACK_POLICY_4_7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9877;"	d
+TX_ACK_POLICY_4_7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9876;"	d
+TX_ACK_POLICY_4_7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9878;"	d
+TX_ACK_POLICY_4_7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9880;"	d
+TX_ACK_POLICY_5_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9919;"	d
+TX_ACK_POLICY_5_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9917;"	d
+TX_ACK_POLICY_5_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9916;"	d
+TX_ACK_POLICY_5_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9918;"	d
+TX_ACK_POLICY_5_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9920;"	d
+TX_ACK_POLICY_5_1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9929;"	d
+TX_ACK_POLICY_5_1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9927;"	d
+TX_ACK_POLICY_5_1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9926;"	d
+TX_ACK_POLICY_5_1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9928;"	d
+TX_ACK_POLICY_5_1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9930;"	d
+TX_ACK_POLICY_5_2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9939;"	d
+TX_ACK_POLICY_5_2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9937;"	d
+TX_ACK_POLICY_5_2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9936;"	d
+TX_ACK_POLICY_5_2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9938;"	d
+TX_ACK_POLICY_5_2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9940;"	d
+TX_ACK_POLICY_5_3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9949;"	d
+TX_ACK_POLICY_5_3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9947;"	d
+TX_ACK_POLICY_5_3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9946;"	d
+TX_ACK_POLICY_5_3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9948;"	d
+TX_ACK_POLICY_5_3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9950;"	d
+TX_ACK_POLICY_5_4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9959;"	d
+TX_ACK_POLICY_5_4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9957;"	d
+TX_ACK_POLICY_5_4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9956;"	d
+TX_ACK_POLICY_5_4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9958;"	d
+TX_ACK_POLICY_5_4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9960;"	d
+TX_ACK_POLICY_5_5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9969;"	d
+TX_ACK_POLICY_5_5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9967;"	d
+TX_ACK_POLICY_5_5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9966;"	d
+TX_ACK_POLICY_5_5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9968;"	d
+TX_ACK_POLICY_5_5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9970;"	d
+TX_ACK_POLICY_5_6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9979;"	d
+TX_ACK_POLICY_5_6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9977;"	d
+TX_ACK_POLICY_5_6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9976;"	d
+TX_ACK_POLICY_5_6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9978;"	d
+TX_ACK_POLICY_5_6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9980;"	d
+TX_ACK_POLICY_5_7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9989;"	d
+TX_ACK_POLICY_5_7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9987;"	d
+TX_ACK_POLICY_5_7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9986;"	d
+TX_ACK_POLICY_5_7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9988;"	d
+TX_ACK_POLICY_5_7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9990;"	d
+TX_ACK_POLICY_6_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10029;"	d
+TX_ACK_POLICY_6_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10027;"	d
+TX_ACK_POLICY_6_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10026;"	d
+TX_ACK_POLICY_6_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10028;"	d
+TX_ACK_POLICY_6_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10030;"	d
+TX_ACK_POLICY_6_1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10039;"	d
+TX_ACK_POLICY_6_1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10037;"	d
+TX_ACK_POLICY_6_1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10036;"	d
+TX_ACK_POLICY_6_1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10038;"	d
+TX_ACK_POLICY_6_1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10040;"	d
+TX_ACK_POLICY_6_2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10049;"	d
+TX_ACK_POLICY_6_2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10047;"	d
+TX_ACK_POLICY_6_2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10046;"	d
+TX_ACK_POLICY_6_2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10048;"	d
+TX_ACK_POLICY_6_2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10050;"	d
+TX_ACK_POLICY_6_3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10059;"	d
+TX_ACK_POLICY_6_3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10057;"	d
+TX_ACK_POLICY_6_3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10056;"	d
+TX_ACK_POLICY_6_3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10058;"	d
+TX_ACK_POLICY_6_3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10060;"	d
+TX_ACK_POLICY_6_4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10069;"	d
+TX_ACK_POLICY_6_4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10067;"	d
+TX_ACK_POLICY_6_4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10066;"	d
+TX_ACK_POLICY_6_4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10068;"	d
+TX_ACK_POLICY_6_4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10070;"	d
+TX_ACK_POLICY_6_5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10079;"	d
+TX_ACK_POLICY_6_5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10077;"	d
+TX_ACK_POLICY_6_5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10076;"	d
+TX_ACK_POLICY_6_5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10078;"	d
+TX_ACK_POLICY_6_5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10080;"	d
+TX_ACK_POLICY_6_6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10089;"	d
+TX_ACK_POLICY_6_6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10087;"	d
+TX_ACK_POLICY_6_6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10086;"	d
+TX_ACK_POLICY_6_6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10088;"	d
+TX_ACK_POLICY_6_6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10090;"	d
+TX_ACK_POLICY_6_7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10099;"	d
+TX_ACK_POLICY_6_7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10097;"	d
+TX_ACK_POLICY_6_7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10096;"	d
+TX_ACK_POLICY_6_7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10098;"	d
+TX_ACK_POLICY_6_7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10100;"	d
+TX_ACK_POLICY_7_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10139;"	d
+TX_ACK_POLICY_7_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10137;"	d
+TX_ACK_POLICY_7_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10136;"	d
+TX_ACK_POLICY_7_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10138;"	d
+TX_ACK_POLICY_7_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10140;"	d
+TX_ACK_POLICY_7_1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10149;"	d
+TX_ACK_POLICY_7_1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10147;"	d
+TX_ACK_POLICY_7_1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10146;"	d
+TX_ACK_POLICY_7_1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10148;"	d
+TX_ACK_POLICY_7_1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10150;"	d
+TX_ACK_POLICY_7_2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10159;"	d
+TX_ACK_POLICY_7_2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10157;"	d
+TX_ACK_POLICY_7_2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10156;"	d
+TX_ACK_POLICY_7_2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10158;"	d
+TX_ACK_POLICY_7_2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10160;"	d
+TX_ACK_POLICY_7_3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10169;"	d
+TX_ACK_POLICY_7_3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10167;"	d
+TX_ACK_POLICY_7_3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10166;"	d
+TX_ACK_POLICY_7_3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10168;"	d
+TX_ACK_POLICY_7_3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10170;"	d
+TX_ACK_POLICY_7_4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10179;"	d
+TX_ACK_POLICY_7_4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10177;"	d
+TX_ACK_POLICY_7_4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10176;"	d
+TX_ACK_POLICY_7_4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10178;"	d
+TX_ACK_POLICY_7_4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10180;"	d
+TX_ACK_POLICY_7_5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10189;"	d
+TX_ACK_POLICY_7_5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10187;"	d
+TX_ACK_POLICY_7_5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10186;"	d
+TX_ACK_POLICY_7_5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10188;"	d
+TX_ACK_POLICY_7_5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10190;"	d
+TX_ACK_POLICY_7_6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10199;"	d
+TX_ACK_POLICY_7_6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10197;"	d
+TX_ACK_POLICY_7_6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10196;"	d
+TX_ACK_POLICY_7_6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10198;"	d
+TX_ACK_POLICY_7_6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10200;"	d
+TX_ACK_POLICY_7_7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10209;"	d
+TX_ACK_POLICY_7_7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10207;"	d
+TX_ACK_POLICY_7_7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10206;"	d
+TX_ACK_POLICY_7_7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10208;"	d
+TX_ACK_POLICY_7_7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10210;"	d
+TX_BUF	include/ssv6xxx_common.h	/^    TX_BUF = 1,$/;"	e	enum:__PBuf_Type_E
+TX_CCA_DUR_HI	include/ssv6200_aux.h	7784;"	d
+TX_CCA_DUR_I_MSK	include/ssv6200_aux.h	7782;"	d
+TX_CCA_DUR_MSK	include/ssv6200_aux.h	7781;"	d
+TX_CCA_DUR_SFT	include/ssv6200_aux.h	7783;"	d
+TX_CCA_DUR_SZ	include/ssv6200_aux.h	7785;"	d
+TX_COMPLETE_INT_HI	include/ssv6200_aux.h	3084;"	d
+TX_COMPLETE_INT_I_MSK	include/ssv6200_aux.h	3082;"	d
+TX_COMPLETE_INT_MSK	include/ssv6200_aux.h	3081;"	d
+TX_COMPLETE_INT_SFT	include/ssv6200_aux.h	3083;"	d
+TX_COMPLETE_INT_SZ	include/ssv6200_aux.h	3085;"	d
+TX_COUNT_LIMIT_HI	include/ssv6200_aux.h	12809;"	d
+TX_COUNT_LIMIT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34334;"	d
+TX_COUNT_LIMIT_I_MSK	include/ssv6200_aux.h	12807;"	d
+TX_COUNT_LIMIT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34332;"	d
+TX_COUNT_LIMIT_MSK	include/ssv6200_aux.h	12806;"	d
+TX_COUNT_LIMIT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34331;"	d
+TX_COUNT_LIMIT_SFT	include/ssv6200_aux.h	12808;"	d
+TX_COUNT_LIMIT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34333;"	d
+TX_COUNT_LIMIT_SZ	include/ssv6200_aux.h	12810;"	d
+TX_COUNT_LIMIT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34335;"	d
+TX_DISCARD_CNT_CLR_HI	include/ssv6200_aux.h	4084;"	d
+TX_DISCARD_CNT_CLR_I_MSK	include/ssv6200_aux.h	4082;"	d
+TX_DISCARD_CNT_CLR_MSK	include/ssv6200_aux.h	4081;"	d
+TX_DISCARD_CNT_CLR_SFT	include/ssv6200_aux.h	4083;"	d
+TX_DISCARD_CNT_CLR_SZ	include/ssv6200_aux.h	4085;"	d
+TX_DISCARD_CNT_HI	include/ssv6200_aux.h	4074;"	d
+TX_DISCARD_CNT_I_MSK	include/ssv6200_aux.h	4072;"	d
+TX_DISCARD_CNT_MSK	include/ssv6200_aux.h	4071;"	d
+TX_DISCARD_CNT_SFT	include/ssv6200_aux.h	4073;"	d
+TX_DISCARD_CNT_SZ	include/ssv6200_aux.h	4075;"	d
+TX_DONE_CNT_CLR_HI	include/ssv6200_aux.h	4089;"	d
+TX_DONE_CNT_CLR_I_MSK	include/ssv6200_aux.h	4087;"	d
+TX_DONE_CNT_CLR_MSK	include/ssv6200_aux.h	4086;"	d
+TX_DONE_CNT_CLR_SFT	include/ssv6200_aux.h	4088;"	d
+TX_DONE_CNT_CLR_SZ	include/ssv6200_aux.h	4090;"	d
+TX_DONE_CNT_HI	include/ssv6200_aux.h	4069;"	d
+TX_DONE_CNT_I_MSK	include/ssv6200_aux.h	4067;"	d
+TX_DONE_CNT_MSK	include/ssv6200_aux.h	4066;"	d
+TX_DONE_CNT_SFT	include/ssv6200_aux.h	4068;"	d
+TX_DONE_CNT_SZ	include/ssv6200_aux.h	4070;"	d
+TX_DONE_HI	include/ssv6200_aux.h	3224;"	d
+TX_DONE_I_MSK	include/ssv6200_aux.h	3222;"	d
+TX_DONE_MSK	include/ssv6200_aux.h	3221;"	d
+TX_DONE_SFT	include/ssv6200_aux.h	3223;"	d
+TX_DONE_STATUS_HI	include/ssv6200_aux.h	3509;"	d
+TX_DONE_STATUS_I_MSK	include/ssv6200_aux.h	3507;"	d
+TX_DONE_STATUS_MSK	include/ssv6200_aux.h	3506;"	d
+TX_DONE_STATUS_SFT	include/ssv6200_aux.h	3508;"	d
+TX_DONE_STATUS_SZ	include/ssv6200_aux.h	3510;"	d
+TX_DONE_SZ	include/ssv6200_aux.h	3225;"	d
+TX_EMPTY2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3644;"	d
+TX_EMPTY2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3642;"	d
+TX_EMPTY2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3641;"	d
+TX_EMPTY2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3643;"	d
+TX_EMPTY2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3645;"	d
+TX_EMPTY_HI	include/ssv6200_aux.h	4419;"	d
+TX_EMPTY_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3529;"	d
+TX_EMPTY_I_MSK	include/ssv6200_aux.h	4417;"	d
+TX_EMPTY_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3527;"	d
+TX_EMPTY_MSK	include/ssv6200_aux.h	4416;"	d
+TX_EMPTY_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3526;"	d
+TX_EMPTY_SFT	include/ssv6200_aux.h	4418;"	d
+TX_EMPTY_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3528;"	d
+TX_EMPTY_SZ	include/ssv6200_aux.h	4420;"	d
+TX_EMPTY_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3530;"	d
+TX_ERR_FIRST_4B_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5229;"	d
+TX_ERR_FIRST_4B_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5227;"	d
+TX_ERR_FIRST_4B_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5226;"	d
+TX_ERR_FIRST_4B_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5228;"	d
+TX_ERR_FIRST_4B_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5230;"	d
+TX_ERR_RECOVER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5224;"	d
+TX_ERR_RECOVER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5222;"	d
+TX_ERR_RECOVER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5221;"	d
+TX_ERR_RECOVER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5223;"	d
+TX_ERR_RECOVER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5225;"	d
+TX_ETHER_TRAP_EN_HI	include/ssv6200_aux.h	6099;"	d
+TX_ETHER_TRAP_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5149;"	d
+TX_ETHER_TRAP_EN_I_MSK	include/ssv6200_aux.h	6097;"	d
+TX_ETHER_TRAP_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5147;"	d
+TX_ETHER_TRAP_EN_MSK	include/ssv6200_aux.h	6096;"	d
+TX_ETHER_TRAP_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5146;"	d
+TX_ETHER_TRAP_EN_SFT	include/ssv6200_aux.h	6098;"	d
+TX_ETHER_TRAP_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5148;"	d
+TX_ETHER_TRAP_EN_SZ	include/ssv6200_aux.h	6100;"	d
+TX_ETHER_TRAP_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5150;"	d
+TX_FIFO_FAIL_HI	include/ssv6200_aux.h	3984;"	d
+TX_FIFO_FAIL_I_MSK	include/ssv6200_aux.h	3982;"	d
+TX_FIFO_FAIL_MSK	include/ssv6200_aux.h	3981;"	d
+TX_FIFO_FAIL_SFT	include/ssv6200_aux.h	3983;"	d
+TX_FIFO_FAIL_SZ	include/ssv6200_aux.h	3985;"	d
+TX_FIFO_RESIDUE_HI	include/ssv6200_aux.h	4104;"	d
+TX_FIFO_RESIDUE_I_MSK	include/ssv6200_aux.h	4102;"	d
+TX_FIFO_RESIDUE_MSK	include/ssv6200_aux.h	4101;"	d
+TX_FIFO_RESIDUE_SFT	include/ssv6200_aux.h	4103;"	d
+TX_FIFO_RESIDUE_SZ	include/ssv6200_aux.h	4105;"	d
+TX_FLOW_CTRL_HI	include/ssv6200_aux.h	6134;"	d
+TX_FLOW_CTRL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5189;"	d
+TX_FLOW_CTRL_I_MSK	include/ssv6200_aux.h	6132;"	d
+TX_FLOW_CTRL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5187;"	d
+TX_FLOW_CTRL_MSK	include/ssv6200_aux.h	6131;"	d
+TX_FLOW_CTRL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5186;"	d
+TX_FLOW_CTRL_SFT	include/ssv6200_aux.h	6133;"	d
+TX_FLOW_CTRL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5188;"	d
+TX_FLOW_CTRL_SZ	include/ssv6200_aux.h	6135;"	d
+TX_FLOW_CTRL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5190;"	d
+TX_FLOW_DATA_HI	include/ssv6200_aux.h	6144;"	d
+TX_FLOW_DATA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5199;"	d
+TX_FLOW_DATA_I_MSK	include/ssv6200_aux.h	6142;"	d
+TX_FLOW_DATA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5197;"	d
+TX_FLOW_DATA_MSK	include/ssv6200_aux.h	6141;"	d
+TX_FLOW_DATA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5196;"	d
+TX_FLOW_DATA_SFT	include/ssv6200_aux.h	6143;"	d
+TX_FLOW_DATA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5198;"	d
+TX_FLOW_DATA_SZ	include/ssv6200_aux.h	6145;"	d
+TX_FLOW_DATA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5200;"	d
+TX_FLOW_MGMT_HI	include/ssv6200_aux.h	6139;"	d
+TX_FLOW_MGMT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5194;"	d
+TX_FLOW_MGMT_I_MSK	include/ssv6200_aux.h	6137;"	d
+TX_FLOW_MGMT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5192;"	d
+TX_FLOW_MGMT_MSK	include/ssv6200_aux.h	6136;"	d
+TX_FLOW_MGMT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5191;"	d
+TX_FLOW_MGMT_SFT	include/ssv6200_aux.h	6138;"	d
+TX_FLOW_MGMT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5193;"	d
+TX_FLOW_MGMT_SZ	include/ssv6200_aux.h	6140;"	d
+TX_FLOW_MGMT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5195;"	d
+TX_HOST_FAIL_HI	include/ssv6200_aux.h	3989;"	d
+TX_HOST_FAIL_I_MSK	include/ssv6200_aux.h	3987;"	d
+TX_HOST_FAIL_MSK	include/ssv6200_aux.h	3986;"	d
+TX_HOST_FAIL_SFT	include/ssv6200_aux.h	3988;"	d
+TX_HOST_FAIL_SZ	include/ssv6200_aux.h	3990;"	d
+TX_H_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3639;"	d
+TX_H_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3637;"	d
+TX_H_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3636;"	d
+TX_H_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3638;"	d
+TX_H_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3640;"	d
+TX_IDLE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3604;"	d
+TX_IDLE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3602;"	d
+TX_IDLE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3601;"	d
+TX_IDLE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3603;"	d
+TX_IDLE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3605;"	d
+TX_ID_ALC_LEN_HI	include/ssv6200_aux.h	12754;"	d
+TX_ID_ALC_LEN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34279;"	d
+TX_ID_ALC_LEN_I_MSK	include/ssv6200_aux.h	12752;"	d
+TX_ID_ALC_LEN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34277;"	d
+TX_ID_ALC_LEN_MSK	include/ssv6200_aux.h	12751;"	d
+TX_ID_ALC_LEN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34276;"	d
+TX_ID_ALC_LEN_SFT	include/ssv6200_aux.h	12753;"	d
+TX_ID_ALC_LEN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34278;"	d
+TX_ID_ALC_LEN_SZ	include/ssv6200_aux.h	12755;"	d
+TX_ID_ALC_LEN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34280;"	d
+TX_ID_COUNT_HI	include/ssv6200_aux.h	12634;"	d
+TX_ID_COUNT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34159;"	d
+TX_ID_COUNT_I_MSK	include/ssv6200_aux.h	12632;"	d
+TX_ID_COUNT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34157;"	d
+TX_ID_COUNT_MSK	include/ssv6200_aux.h	12631;"	d
+TX_ID_COUNT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34156;"	d
+TX_ID_COUNT_SFT	include/ssv6200_aux.h	12633;"	d
+TX_ID_COUNT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34158;"	d
+TX_ID_COUNT_SZ	include/ssv6200_aux.h	12635;"	d
+TX_ID_COUNT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34160;"	d
+TX_ID_IFO_LEN_HI	include/ssv6200_aux.h	12939;"	d
+TX_ID_IFO_LEN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34474;"	d
+TX_ID_IFO_LEN_I_MSK	include/ssv6200_aux.h	12937;"	d
+TX_ID_IFO_LEN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34472;"	d
+TX_ID_IFO_LEN_MSK	include/ssv6200_aux.h	12936;"	d
+TX_ID_IFO_LEN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34471;"	d
+TX_ID_IFO_LEN_SFT	include/ssv6200_aux.h	12938;"	d
+TX_ID_IFO_LEN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34473;"	d
+TX_ID_IFO_LEN_SZ	include/ssv6200_aux.h	12940;"	d
+TX_ID_IFO_LEN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34475;"	d
+TX_ID_LEN_THOLD_HI	include/ssv6200_aux.h	5024;"	d
+TX_ID_LEN_THOLD_INT_HI	include/ssv6200_aux.h	12724;"	d
+TX_ID_LEN_THOLD_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34249;"	d
+TX_ID_LEN_THOLD_INT_I_MSK	include/ssv6200_aux.h	12722;"	d
+TX_ID_LEN_THOLD_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34247;"	d
+TX_ID_LEN_THOLD_INT_MSK	include/ssv6200_aux.h	12721;"	d
+TX_ID_LEN_THOLD_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34246;"	d
+TX_ID_LEN_THOLD_INT_SFT	include/ssv6200_aux.h	12723;"	d
+TX_ID_LEN_THOLD_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34248;"	d
+TX_ID_LEN_THOLD_INT_SZ	include/ssv6200_aux.h	12725;"	d
+TX_ID_LEN_THOLD_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34250;"	d
+TX_ID_LEN_THOLD_I_MSK	include/ssv6200_aux.h	5022;"	d
+TX_ID_LEN_THOLD_MSK	include/ssv6200_aux.h	5021;"	d
+TX_ID_LEN_THOLD_SD_HI	include/ssv6200_aux.h	5369;"	d
+TX_ID_LEN_THOLD_SD_I_MSK	include/ssv6200_aux.h	5367;"	d
+TX_ID_LEN_THOLD_SD_MSK	include/ssv6200_aux.h	5366;"	d
+TX_ID_LEN_THOLD_SD_SFT	include/ssv6200_aux.h	5368;"	d
+TX_ID_LEN_THOLD_SD_SZ	include/ssv6200_aux.h	5370;"	d
+TX_ID_LEN_THOLD_SFT	include/ssv6200_aux.h	5023;"	d
+TX_ID_LEN_THOLD_SZ	include/ssv6200_aux.h	5025;"	d
+TX_ID_REMAIN2_HI	include/ssv6200_aux.h	3639;"	d
+TX_ID_REMAIN2_I_MSK	include/ssv6200_aux.h	3637;"	d
+TX_ID_REMAIN2_MSK	include/ssv6200_aux.h	3636;"	d
+TX_ID_REMAIN2_SFT	include/ssv6200_aux.h	3638;"	d
+TX_ID_REMAIN2_SZ	include/ssv6200_aux.h	3640;"	d
+TX_ID_REMAIN3_HI	include/ssv6200_aux.h	3579;"	d
+TX_ID_REMAIN3_I_MSK	include/ssv6200_aux.h	3577;"	d
+TX_ID_REMAIN3_MSK	include/ssv6200_aux.h	3576;"	d
+TX_ID_REMAIN3_SFT	include/ssv6200_aux.h	3578;"	d
+TX_ID_REMAIN3_SZ	include/ssv6200_aux.h	3580;"	d
+TX_ID_REMAIN_HI	include/ssv6200_aux.h	12789;"	d
+TX_ID_REMAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34314;"	d
+TX_ID_REMAIN_I_MSK	include/ssv6200_aux.h	12787;"	d
+TX_ID_REMAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34312;"	d
+TX_ID_REMAIN_MSK	include/ssv6200_aux.h	12786;"	d
+TX_ID_REMAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34311;"	d
+TX_ID_REMAIN_SFT	include/ssv6200_aux.h	12788;"	d
+TX_ID_REMAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34313;"	d
+TX_ID_REMAIN_SZ	include/ssv6200_aux.h	12790;"	d
+TX_ID_REMAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34315;"	d
+TX_ID_TB0_HI	include/ssv6200_aux.h	12679;"	d
+TX_ID_TB0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34204;"	d
+TX_ID_TB0_I_MSK	include/ssv6200_aux.h	12677;"	d
+TX_ID_TB0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34202;"	d
+TX_ID_TB0_MSK	include/ssv6200_aux.h	12676;"	d
+TX_ID_TB0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34201;"	d
+TX_ID_TB0_SFT	include/ssv6200_aux.h	12678;"	d
+TX_ID_TB0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34203;"	d
+TX_ID_TB0_SZ	include/ssv6200_aux.h	12680;"	d
+TX_ID_TB0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34205;"	d
+TX_ID_TB1_HI	include/ssv6200_aux.h	12684;"	d
+TX_ID_TB1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34209;"	d
+TX_ID_TB1_I_MSK	include/ssv6200_aux.h	12682;"	d
+TX_ID_TB1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34207;"	d
+TX_ID_TB1_MSK	include/ssv6200_aux.h	12681;"	d
+TX_ID_TB1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34206;"	d
+TX_ID_TB1_SFT	include/ssv6200_aux.h	12683;"	d
+TX_ID_TB1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34208;"	d
+TX_ID_TB1_SZ	include/ssv6200_aux.h	12685;"	d
+TX_ID_TB1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34210;"	d
+TX_ID_TB2_HI	include/ssv6200_aux.h	12864;"	d
+TX_ID_TB2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34389;"	d
+TX_ID_TB2_I_MSK	include/ssv6200_aux.h	12862;"	d
+TX_ID_TB2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34387;"	d
+TX_ID_TB2_MSK	include/ssv6200_aux.h	12861;"	d
+TX_ID_TB2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34386;"	d
+TX_ID_TB2_SFT	include/ssv6200_aux.h	12863;"	d
+TX_ID_TB2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34388;"	d
+TX_ID_TB2_SZ	include/ssv6200_aux.h	12865;"	d
+TX_ID_TB2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34390;"	d
+TX_ID_TB3_HI	include/ssv6200_aux.h	12869;"	d
+TX_ID_TB3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34394;"	d
+TX_ID_TB3_I_MSK	include/ssv6200_aux.h	12867;"	d
+TX_ID_TB3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34392;"	d
+TX_ID_TB3_MSK	include/ssv6200_aux.h	12866;"	d
+TX_ID_TB3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34391;"	d
+TX_ID_TB3_SFT	include/ssv6200_aux.h	12868;"	d
+TX_ID_TB3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34393;"	d
+TX_ID_TB3_SZ	include/ssv6200_aux.h	12870;"	d
+TX_ID_TB3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34395;"	d
+TX_ID_THOLD_HI	include/ssv6200_aux.h	12644;"	d
+TX_ID_THOLD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34169;"	d
+TX_ID_THOLD_I_MSK	include/ssv6200_aux.h	12642;"	d
+TX_ID_THOLD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34167;"	d
+TX_ID_THOLD_MSK	include/ssv6200_aux.h	12641;"	d
+TX_ID_THOLD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34166;"	d
+TX_ID_THOLD_SFT	include/ssv6200_aux.h	12643;"	d
+TX_ID_THOLD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34168;"	d
+TX_ID_THOLD_SZ	include/ssv6200_aux.h	12645;"	d
+TX_ID_THOLD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34170;"	d
+TX_ID_USE2_HI	include/ssv6200_aux.h	12889;"	d
+TX_ID_USE2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34414;"	d
+TX_ID_USE2_I_MSK	include/ssv6200_aux.h	12887;"	d
+TX_ID_USE2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34412;"	d
+TX_ID_USE2_MSK	include/ssv6200_aux.h	12886;"	d
+TX_ID_USE2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34411;"	d
+TX_ID_USE2_SFT	include/ssv6200_aux.h	12888;"	d
+TX_ID_USE2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34413;"	d
+TX_ID_USE2_SZ	include/ssv6200_aux.h	12890;"	d
+TX_ID_USE2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34415;"	d
+TX_ID_USE3_HI	include/ssv6200_aux.h	12904;"	d
+TX_ID_USE3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34434;"	d
+TX_ID_USE3_I_MSK	include/ssv6200_aux.h	12902;"	d
+TX_ID_USE3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34432;"	d
+TX_ID_USE3_MSK	include/ssv6200_aux.h	12901;"	d
+TX_ID_USE3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34431;"	d
+TX_ID_USE3_SFT	include/ssv6200_aux.h	12903;"	d
+TX_ID_USE3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34433;"	d
+TX_ID_USE3_SZ	include/ssv6200_aux.h	12905;"	d
+TX_ID_USE3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34435;"	d
+TX_ID_USE4_HI	include/ssv6200_aux.h	12924;"	d
+TX_ID_USE4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34459;"	d
+TX_ID_USE4_I_MSK	include/ssv6200_aux.h	12922;"	d
+TX_ID_USE4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34457;"	d
+TX_ID_USE4_MSK	include/ssv6200_aux.h	12921;"	d
+TX_ID_USE4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34456;"	d
+TX_ID_USE4_SFT	include/ssv6200_aux.h	12923;"	d
+TX_ID_USE4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34458;"	d
+TX_ID_USE4_SZ	include/ssv6200_aux.h	12925;"	d
+TX_ID_USE4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34460;"	d
+TX_ID_USE_5_0_HI	include/ssv6200_aux.h	12829;"	d
+TX_ID_USE_5_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34354;"	d
+TX_ID_USE_5_0_I_MSK	include/ssv6200_aux.h	12827;"	d
+TX_ID_USE_5_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34352;"	d
+TX_ID_USE_5_0_MSK	include/ssv6200_aux.h	12826;"	d
+TX_ID_USE_5_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34351;"	d
+TX_ID_USE_5_0_SFT	include/ssv6200_aux.h	12828;"	d
+TX_ID_USE_5_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34353;"	d
+TX_ID_USE_5_0_SZ	include/ssv6200_aux.h	12830;"	d
+TX_ID_USE_5_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34355;"	d
+TX_INFO_CLEAR_ENABLE_HI	include/ssv6200_aux.h	6189;"	d
+TX_INFO_CLEAR_ENABLE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5284;"	d
+TX_INFO_CLEAR_ENABLE_I_MSK	include/ssv6200_aux.h	6187;"	d
+TX_INFO_CLEAR_ENABLE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5282;"	d
+TX_INFO_CLEAR_ENABLE_MSK	include/ssv6200_aux.h	6186;"	d
+TX_INFO_CLEAR_ENABLE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5281;"	d
+TX_INFO_CLEAR_ENABLE_SFT	include/ssv6200_aux.h	6188;"	d
+TX_INFO_CLEAR_ENABLE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5283;"	d
+TX_INFO_CLEAR_ENABLE_SZ	include/ssv6200_aux.h	6190;"	d
+TX_INFO_CLEAR_ENABLE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5285;"	d
+TX_INFO_CLEAR_SIZE_HI	include/ssv6200_aux.h	6184;"	d
+TX_INFO_CLEAR_SIZE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5279;"	d
+TX_INFO_CLEAR_SIZE_I_MSK	include/ssv6200_aux.h	6182;"	d
+TX_INFO_CLEAR_SIZE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5277;"	d
+TX_INFO_CLEAR_SIZE_MSK	include/ssv6200_aux.h	6181;"	d
+TX_INFO_CLEAR_SIZE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5276;"	d
+TX_INFO_CLEAR_SIZE_SFT	include/ssv6200_aux.h	6183;"	d
+TX_INFO_CLEAR_SIZE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5278;"	d
+TX_INFO_CLEAR_SIZE_SZ	include/ssv6200_aux.h	6185;"	d
+TX_INFO_CLEAR_SIZE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5280;"	d
+TX_INFO_SIZE_HI	include/ssv6200_aux.h	6169;"	d
+TX_INFO_SIZE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5264;"	d
+TX_INFO_SIZE_I_MSK	include/ssv6200_aux.h	6167;"	d
+TX_INFO_SIZE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5262;"	d
+TX_INFO_SIZE_MSK	include/ssv6200_aux.h	6166;"	d
+TX_INFO_SIZE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5261;"	d
+TX_INFO_SIZE_SFT	include/ssv6200_aux.h	6168;"	d
+TX_INFO_SIZE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5263;"	d
+TX_INFO_SIZE_SZ	include/ssv6200_aux.h	6170;"	d
+TX_INFO_SIZE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5265;"	d
+TX_INT_CH_HI	include/ssv6200_aux.h	12669;"	d
+TX_INT_CH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34194;"	d
+TX_INT_CH_I_MSK	include/ssv6200_aux.h	12667;"	d
+TX_INT_CH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34192;"	d
+TX_INT_CH_MSK	include/ssv6200_aux.h	12666;"	d
+TX_INT_CH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34191;"	d
+TX_INT_CH_SFT	include/ssv6200_aux.h	12668;"	d
+TX_INT_CH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34193;"	d
+TX_INT_CH_SZ	include/ssv6200_aux.h	12670;"	d
+TX_INT_CH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34195;"	d
+TX_IP_FALL_OFFSET_STEP_HI	smac/hal/ssv6006c/ssv6006C_aux.h	7354;"	d
+TX_IP_FALL_OFFSET_STEP_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7352;"	d
+TX_IP_FALL_OFFSET_STEP_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	7351;"	d
+TX_IP_FALL_OFFSET_STEP_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	7353;"	d
+TX_IP_FALL_OFFSET_STEP_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	7355;"	d
+TX_LIMIT_INT_EN_HI	include/ssv6200_aux.h	12819;"	d
+TX_LIMIT_INT_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34344;"	d
+TX_LIMIT_INT_EN_I_MSK	include/ssv6200_aux.h	12817;"	d
+TX_LIMIT_INT_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34342;"	d
+TX_LIMIT_INT_EN_MSK	include/ssv6200_aux.h	12816;"	d
+TX_LIMIT_INT_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34341;"	d
+TX_LIMIT_INT_EN_SFT	include/ssv6200_aux.h	12818;"	d
+TX_LIMIT_INT_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34343;"	d
+TX_LIMIT_INT_EN_SZ	include/ssv6200_aux.h	12820;"	d
+TX_LIMIT_INT_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34345;"	d
+TX_LIMIT_INT_HI	include/ssv6200_aux.h	12814;"	d
+TX_LIMIT_INT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34339;"	d
+TX_LIMIT_INT_IN_HI	include/ssv6200_aux.h	4144;"	d
+TX_LIMIT_INT_IN_I_MSK	include/ssv6200_aux.h	4142;"	d
+TX_LIMIT_INT_IN_MSK	include/ssv6200_aux.h	4141;"	d
+TX_LIMIT_INT_IN_SFT	include/ssv6200_aux.h	4143;"	d
+TX_LIMIT_INT_IN_SZ	include/ssv6200_aux.h	4145;"	d
+TX_LIMIT_INT_I_MSK	include/ssv6200_aux.h	12812;"	d
+TX_LIMIT_INT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34337;"	d
+TX_LIMIT_INT_MASK_HI	include/ssv6200_aux.h	3074;"	d
+TX_LIMIT_INT_MASK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2544;"	d
+TX_LIMIT_INT_MASK_I_MSK	include/ssv6200_aux.h	3072;"	d
+TX_LIMIT_INT_MASK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2542;"	d
+TX_LIMIT_INT_MASK_MSK	include/ssv6200_aux.h	3071;"	d
+TX_LIMIT_INT_MASK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2541;"	d
+TX_LIMIT_INT_MASK_SFT	include/ssv6200_aux.h	3073;"	d
+TX_LIMIT_INT_MASK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2543;"	d
+TX_LIMIT_INT_MASK_SZ	include/ssv6200_aux.h	3075;"	d
+TX_LIMIT_INT_MASK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2545;"	d
+TX_LIMIT_INT_MSK	include/ssv6200_aux.h	12811;"	d
+TX_LIMIT_INT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34336;"	d
+TX_LIMIT_INT_SFT	include/ssv6200_aux.h	12813;"	d
+TX_LIMIT_INT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34338;"	d
+TX_LIMIT_INT_STS_HI	include/ssv6200_aux.h	3114;"	d
+TX_LIMIT_INT_STS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	2584;"	d
+TX_LIMIT_INT_STS_I_MSK	include/ssv6200_aux.h	3112;"	d
+TX_LIMIT_INT_STS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2582;"	d
+TX_LIMIT_INT_STS_MSK	include/ssv6200_aux.h	3111;"	d
+TX_LIMIT_INT_STS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	2581;"	d
+TX_LIMIT_INT_STS_SFT	include/ssv6200_aux.h	3113;"	d
+TX_LIMIT_INT_STS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	2583;"	d
+TX_LIMIT_INT_STS_SZ	include/ssv6200_aux.h	3115;"	d
+TX_LIMIT_INT_STS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	2585;"	d
+TX_LIMIT_INT_SZ	include/ssv6200_aux.h	12815;"	d
+TX_LIMIT_INT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34340;"	d
+TX_L_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3634;"	d
+TX_L_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3632;"	d
+TX_L_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3631;"	d
+TX_L_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3633;"	d
+TX_L_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3635;"	d
+TX_MOUNT_HI	include/ssv6200_aux.h	17974;"	d
+TX_MOUNT_I_MSK	include/ssv6200_aux.h	17972;"	d
+TX_MOUNT_MSK	include/ssv6200_aux.h	17971;"	d
+TX_MOUNT_SFT	include/ssv6200_aux.h	17973;"	d
+TX_MOUNT_SZ	include/ssv6200_aux.h	17975;"	d
+TX_ON_DEMAND_ENA_HI	include/ssv6200_aux.h	6054;"	d
+TX_ON_DEMAND_ENA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5104;"	d
+TX_ON_DEMAND_ENA_I_MSK	include/ssv6200_aux.h	6052;"	d
+TX_ON_DEMAND_ENA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5102;"	d
+TX_ON_DEMAND_ENA_MSK	include/ssv6200_aux.h	6051;"	d
+TX_ON_DEMAND_ENA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5101;"	d
+TX_ON_DEMAND_ENA_SFT	include/ssv6200_aux.h	6053;"	d
+TX_ON_DEMAND_ENA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5103;"	d
+TX_ON_DEMAND_ENA_SZ	include/ssv6200_aux.h	6055;"	d
+TX_ON_DEMAND_ENA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5105;"	d
+TX_ON_DEMAND_LENGTH_HI	include/ssv6200_aux.h	6274;"	d
+TX_ON_DEMAND_LENGTH_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5444;"	d
+TX_ON_DEMAND_LENGTH_I_MSK	include/ssv6200_aux.h	6272;"	d
+TX_ON_DEMAND_LENGTH_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5442;"	d
+TX_ON_DEMAND_LENGTH_MSK	include/ssv6200_aux.h	6271;"	d
+TX_ON_DEMAND_LENGTH_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5441;"	d
+TX_ON_DEMAND_LENGTH_SFT	include/ssv6200_aux.h	6273;"	d
+TX_ON_DEMAND_LENGTH_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5443;"	d
+TX_ON_DEMAND_LENGTH_SZ	include/ssv6200_aux.h	6275;"	d
+TX_ON_DEMAND_LENGTH_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5445;"	d
+TX_PAGE_LIMIT_HI	include/ssv6200_aux.h	12804;"	d
+TX_PAGE_LIMIT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34329;"	d
+TX_PAGE_LIMIT_I_MSK	include/ssv6200_aux.h	12802;"	d
+TX_PAGE_LIMIT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34327;"	d
+TX_PAGE_LIMIT_MSK	include/ssv6200_aux.h	12801;"	d
+TX_PAGE_LIMIT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34326;"	d
+TX_PAGE_LIMIT_SFT	include/ssv6200_aux.h	12803;"	d
+TX_PAGE_LIMIT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34328;"	d
+TX_PAGE_LIMIT_SZ	include/ssv6200_aux.h	12805;"	d
+TX_PAGE_LIMIT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34330;"	d
+TX_PAGE_NOT_LIMITED	hci/ssv_hci.h	19;"	d
+TX_PAGE_REMAIN2_HI	include/ssv6200_aux.h	3574;"	d
+TX_PAGE_REMAIN2_I_MSK	include/ssv6200_aux.h	3572;"	d
+TX_PAGE_REMAIN2_MSK	include/ssv6200_aux.h	3571;"	d
+TX_PAGE_REMAIN2_SFT	include/ssv6200_aux.h	3573;"	d
+TX_PAGE_REMAIN2_SZ	include/ssv6200_aux.h	3575;"	d
+TX_PAGE_REMAIN3_HI	include/ssv6200_aux.h	3644;"	d
+TX_PAGE_REMAIN3_I_MSK	include/ssv6200_aux.h	3642;"	d
+TX_PAGE_REMAIN3_MSK	include/ssv6200_aux.h	3641;"	d
+TX_PAGE_REMAIN3_SFT	include/ssv6200_aux.h	3643;"	d
+TX_PAGE_REMAIN3_SZ	include/ssv6200_aux.h	3645;"	d
+TX_PAGE_REMAIN_HI	include/ssv6200_aux.h	12794;"	d
+TX_PAGE_REMAIN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34319;"	d
+TX_PAGE_REMAIN_I_MSK	include/ssv6200_aux.h	12792;"	d
+TX_PAGE_REMAIN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34317;"	d
+TX_PAGE_REMAIN_MSK	include/ssv6200_aux.h	12791;"	d
+TX_PAGE_REMAIN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34316;"	d
+TX_PAGE_REMAIN_SFT	include/ssv6200_aux.h	12793;"	d
+TX_PAGE_REMAIN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34318;"	d
+TX_PAGE_REMAIN_SZ	include/ssv6200_aux.h	12795;"	d
+TX_PAGE_REMAIN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34320;"	d
+TX_PAGE_USE2_HI	include/ssv6200_aux.h	12884;"	d
+TX_PAGE_USE2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34409;"	d
+TX_PAGE_USE2_I_MSK	include/ssv6200_aux.h	12882;"	d
+TX_PAGE_USE2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34407;"	d
+TX_PAGE_USE2_MSK	include/ssv6200_aux.h	12881;"	d
+TX_PAGE_USE2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34406;"	d
+TX_PAGE_USE2_SFT	include/ssv6200_aux.h	12883;"	d
+TX_PAGE_USE2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34408;"	d
+TX_PAGE_USE2_SZ	include/ssv6200_aux.h	12885;"	d
+TX_PAGE_USE2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34410;"	d
+TX_PAGE_USE3_HI	include/ssv6200_aux.h	12899;"	d
+TX_PAGE_USE3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34429;"	d
+TX_PAGE_USE3_I_MSK	include/ssv6200_aux.h	12897;"	d
+TX_PAGE_USE3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34427;"	d
+TX_PAGE_USE3_MSK	include/ssv6200_aux.h	12896;"	d
+TX_PAGE_USE3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34426;"	d
+TX_PAGE_USE3_SFT	include/ssv6200_aux.h	12898;"	d
+TX_PAGE_USE3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34428;"	d
+TX_PAGE_USE3_SZ	include/ssv6200_aux.h	12900;"	d
+TX_PAGE_USE3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34430;"	d
+TX_PAGE_USE4_HI	include/ssv6200_aux.h	12919;"	d
+TX_PAGE_USE4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34454;"	d
+TX_PAGE_USE4_I_MSK	include/ssv6200_aux.h	12917;"	d
+TX_PAGE_USE4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34452;"	d
+TX_PAGE_USE4_MSK	include/ssv6200_aux.h	12916;"	d
+TX_PAGE_USE4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34451;"	d
+TX_PAGE_USE4_SFT	include/ssv6200_aux.h	12918;"	d
+TX_PAGE_USE4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34453;"	d
+TX_PAGE_USE4_SZ	include/ssv6200_aux.h	12920;"	d
+TX_PAGE_USE4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34455;"	d
+TX_PAGE_USE_7_0_HI	include/ssv6200_aux.h	12824;"	d
+TX_PAGE_USE_7_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	34349;"	d
+TX_PAGE_USE_7_0_I_MSK	include/ssv6200_aux.h	12822;"	d
+TX_PAGE_USE_7_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34347;"	d
+TX_PAGE_USE_7_0_MSK	include/ssv6200_aux.h	12821;"	d
+TX_PAGE_USE_7_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	34346;"	d
+TX_PAGE_USE_7_0_SFT	include/ssv6200_aux.h	12823;"	d
+TX_PAGE_USE_7_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	34348;"	d
+TX_PAGE_USE_7_0_SZ	include/ssv6200_aux.h	12825;"	d
+TX_PAGE_USE_7_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	34350;"	d
+TX_PBOFFSET_HI	include/ssv6200_aux.h	6164;"	d
+TX_PBOFFSET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5259;"	d
+TX_PBOFFSET_I_MSK	include/ssv6200_aux.h	6162;"	d
+TX_PBOFFSET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5257;"	d
+TX_PBOFFSET_MSK	include/ssv6200_aux.h	6161;"	d
+TX_PBOFFSET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5256;"	d
+TX_PBOFFSET_SFT	include/ssv6200_aux.h	6163;"	d
+TX_PBOFFSET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5258;"	d
+TX_PBOFFSET_SZ	include/ssv6200_aux.h	6165;"	d
+TX_PBOFFSET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5260;"	d
+TX_PKT_COUNTER_HI	include/ssv6200_aux.h	6214;"	d
+TX_PKT_COUNTER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5494;"	d
+TX_PKT_COUNTER_I_MSK	include/ssv6200_aux.h	6212;"	d
+TX_PKT_COUNTER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5492;"	d
+TX_PKT_COUNTER_MSK	include/ssv6200_aux.h	6211;"	d
+TX_PKT_COUNTER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5491;"	d
+TX_PKT_COUNTER_SFT	include/ssv6200_aux.h	6213;"	d
+TX_PKT_COUNTER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5493;"	d
+TX_PKT_COUNTER_SZ	include/ssv6200_aux.h	6215;"	d
+TX_PKT_COUNTER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5495;"	d
+TX_PKT_DROP_COUNTER_HI	include/ssv6200_aux.h	6234;"	d
+TX_PKT_DROP_COUNTER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5474;"	d
+TX_PKT_DROP_COUNTER_I_MSK	include/ssv6200_aux.h	6232;"	d
+TX_PKT_DROP_COUNTER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5472;"	d
+TX_PKT_DROP_COUNTER_MSK	include/ssv6200_aux.h	6231;"	d
+TX_PKT_DROP_COUNTER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5471;"	d
+TX_PKT_DROP_COUNTER_SFT	include/ssv6200_aux.h	6233;"	d
+TX_PKT_DROP_COUNTER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5473;"	d
+TX_PKT_DROP_COUNTER_SZ	include/ssv6200_aux.h	6235;"	d
+TX_PKT_DROP_COUNTER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5475;"	d
+TX_PKT_RSVD_HI	include/ssv6200_aux.h	9154;"	d
+TX_PKT_RSVD_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8909;"	d
+TX_PKT_RSVD_I_MSK	include/ssv6200_aux.h	9152;"	d
+TX_PKT_RSVD_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8907;"	d
+TX_PKT_RSVD_MSK	include/ssv6200_aux.h	9151;"	d
+TX_PKT_RSVD_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8906;"	d
+TX_PKT_RSVD_SFT	include/ssv6200_aux.h	9153;"	d
+TX_PKT_RSVD_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8908;"	d
+TX_PKT_RSVD_SZ	include/ssv6200_aux.h	9155;"	d
+TX_PKT_RSVD_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8910;"	d
+TX_PKT_SEND_ID_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5359;"	d
+TX_PKT_SEND_ID_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5357;"	d
+TX_PKT_SEND_ID_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5356;"	d
+TX_PKT_SEND_ID_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5358;"	d
+TX_PKT_SEND_ID_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5360;"	d
+TX_PKT_SEND_LEN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5349;"	d
+TX_PKT_SEND_LEN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5347;"	d
+TX_PKT_SEND_LEN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5346;"	d
+TX_PKT_SEND_LEN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5348;"	d
+TX_PKT_SEND_LEN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5350;"	d
+TX_PKT_SEND_TO_RX_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5514;"	d
+TX_PKT_SEND_TO_RX_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5512;"	d
+TX_PKT_SEND_TO_RX_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5511;"	d
+TX_PKT_SEND_TO_RX_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5513;"	d
+TX_PKT_SEND_TO_RX_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5515;"	d
+TX_PKT_TRAP_COUNTER_HI	include/ssv6200_aux.h	6244;"	d
+TX_PKT_TRAP_COUNTER_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5464;"	d
+TX_PKT_TRAP_COUNTER_I_MSK	include/ssv6200_aux.h	6242;"	d
+TX_PKT_TRAP_COUNTER_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5462;"	d
+TX_PKT_TRAP_COUNTER_MSK	include/ssv6200_aux.h	6241;"	d
+TX_PKT_TRAP_COUNTER_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5461;"	d
+TX_PKT_TRAP_COUNTER_SFT	include/ssv6200_aux.h	6243;"	d
+TX_PKT_TRAP_COUNTER_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5463;"	d
+TX_PKT_TRAP_COUNTER_SZ	include/ssv6200_aux.h	6245;"	d
+TX_PKT_TRAP_COUNTER_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5465;"	d
+TX_RX_LOOP_BACK_TEST_HI	include/ssv6200_aux.h	3184;"	d
+TX_RX_LOOP_BACK_TEST_I_MSK	include/ssv6200_aux.h	3182;"	d
+TX_RX_LOOP_BACK_TEST_MSK	include/ssv6200_aux.h	3181;"	d
+TX_RX_LOOP_BACK_TEST_SFT	include/ssv6200_aux.h	3183;"	d
+TX_RX_LOOP_BACK_TEST_SZ	include/ssv6200_aux.h	3185;"	d
+TX_RX_TRAP_HW_ID_SELECT_ENABLE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5529;"	d
+TX_RX_TRAP_HW_ID_SELECT_ENABLE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5527;"	d
+TX_RX_TRAP_HW_ID_SELECT_ENABLE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5526;"	d
+TX_RX_TRAP_HW_ID_SELECT_ENABLE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5528;"	d
+TX_RX_TRAP_HW_ID_SELECT_ENABLE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5530;"	d
+TX_SCALE_11B_HI	include/ssv6200_aux.h	16039;"	d
+TX_SCALE_11B_I_MSK	include/ssv6200_aux.h	16037;"	d
+TX_SCALE_11B_MSK	include/ssv6200_aux.h	16036;"	d
+TX_SCALE_11B_P0D5_HI	include/ssv6200_aux.h	16044;"	d
+TX_SCALE_11B_P0D5_I_MSK	include/ssv6200_aux.h	16042;"	d
+TX_SCALE_11B_P0D5_MSK	include/ssv6200_aux.h	16041;"	d
+TX_SCALE_11B_P0D5_SFT	include/ssv6200_aux.h	16043;"	d
+TX_SCALE_11B_P0D5_SZ	include/ssv6200_aux.h	16045;"	d
+TX_SCALE_11B_SFT	include/ssv6200_aux.h	16038;"	d
+TX_SCALE_11B_SZ	include/ssv6200_aux.h	16040;"	d
+TX_SCALE_11G_HI	include/ssv6200_aux.h	16049;"	d
+TX_SCALE_11G_I_MSK	include/ssv6200_aux.h	16047;"	d
+TX_SCALE_11G_MSK	include/ssv6200_aux.h	16046;"	d
+TX_SCALE_11G_P0D5_HI	include/ssv6200_aux.h	16054;"	d
+TX_SCALE_11G_P0D5_I_MSK	include/ssv6200_aux.h	16052;"	d
+TX_SCALE_11G_P0D5_MSK	include/ssv6200_aux.h	16051;"	d
+TX_SCALE_11G_P0D5_SFT	include/ssv6200_aux.h	16053;"	d
+TX_SCALE_11G_P0D5_SZ	include/ssv6200_aux.h	16055;"	d
+TX_SCALE_11G_SFT	include/ssv6200_aux.h	16048;"	d
+TX_SCALE_11G_SZ	include/ssv6200_aux.h	16050;"	d
+TX_SDIO_PKT_LEN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5354;"	d
+TX_SDIO_PKT_LEN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5352;"	d
+TX_SDIO_PKT_LEN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5351;"	d
+TX_SDIO_PKT_LEN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5353;"	d
+TX_SDIO_PKT_LEN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5355;"	d
+TX_SEG_HI	include/ssv6200_aux.h	3944;"	d
+TX_SEG_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3064;"	d
+TX_SEG_I_MSK	include/ssv6200_aux.h	3942;"	d
+TX_SEG_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3062;"	d
+TX_SEG_MSK	include/ssv6200_aux.h	3941;"	d
+TX_SEG_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3061;"	d
+TX_SEG_SFT	include/ssv6200_aux.h	3943;"	d
+TX_SEG_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3063;"	d
+TX_SEG_SZ	include/ssv6200_aux.h	3945;"	d
+TX_SEG_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3065;"	d
+TX_SEQ_CTRL_0_0_HI	include/ssv6200_aux.h	8329;"	d
+TX_SEQ_CTRL_0_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8319;"	d
+TX_SEQ_CTRL_0_0_I_MSK	include/ssv6200_aux.h	8327;"	d
+TX_SEQ_CTRL_0_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8317;"	d
+TX_SEQ_CTRL_0_0_MSK	include/ssv6200_aux.h	8326;"	d
+TX_SEQ_CTRL_0_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8316;"	d
+TX_SEQ_CTRL_0_0_SFT	include/ssv6200_aux.h	8328;"	d
+TX_SEQ_CTRL_0_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8318;"	d
+TX_SEQ_CTRL_0_0_SZ	include/ssv6200_aux.h	8330;"	d
+TX_SEQ_CTRL_0_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8320;"	d
+TX_SEQ_CTRL_0_1_HI	include/ssv6200_aux.h	8339;"	d
+TX_SEQ_CTRL_0_1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8329;"	d
+TX_SEQ_CTRL_0_1_I_MSK	include/ssv6200_aux.h	8337;"	d
+TX_SEQ_CTRL_0_1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8327;"	d
+TX_SEQ_CTRL_0_1_MSK	include/ssv6200_aux.h	8336;"	d
+TX_SEQ_CTRL_0_1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8326;"	d
+TX_SEQ_CTRL_0_1_SFT	include/ssv6200_aux.h	8338;"	d
+TX_SEQ_CTRL_0_1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8328;"	d
+TX_SEQ_CTRL_0_1_SZ	include/ssv6200_aux.h	8340;"	d
+TX_SEQ_CTRL_0_1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8330;"	d
+TX_SEQ_CTRL_0_2_HI	include/ssv6200_aux.h	8349;"	d
+TX_SEQ_CTRL_0_2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8339;"	d
+TX_SEQ_CTRL_0_2_I_MSK	include/ssv6200_aux.h	8347;"	d
+TX_SEQ_CTRL_0_2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8337;"	d
+TX_SEQ_CTRL_0_2_MSK	include/ssv6200_aux.h	8346;"	d
+TX_SEQ_CTRL_0_2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8336;"	d
+TX_SEQ_CTRL_0_2_SFT	include/ssv6200_aux.h	8348;"	d
+TX_SEQ_CTRL_0_2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8338;"	d
+TX_SEQ_CTRL_0_2_SZ	include/ssv6200_aux.h	8350;"	d
+TX_SEQ_CTRL_0_2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8340;"	d
+TX_SEQ_CTRL_0_3_HI	include/ssv6200_aux.h	8359;"	d
+TX_SEQ_CTRL_0_3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8349;"	d
+TX_SEQ_CTRL_0_3_I_MSK	include/ssv6200_aux.h	8357;"	d
+TX_SEQ_CTRL_0_3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8347;"	d
+TX_SEQ_CTRL_0_3_MSK	include/ssv6200_aux.h	8356;"	d
+TX_SEQ_CTRL_0_3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8346;"	d
+TX_SEQ_CTRL_0_3_SFT	include/ssv6200_aux.h	8358;"	d
+TX_SEQ_CTRL_0_3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8348;"	d
+TX_SEQ_CTRL_0_3_SZ	include/ssv6200_aux.h	8360;"	d
+TX_SEQ_CTRL_0_3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8350;"	d
+TX_SEQ_CTRL_0_4_HI	include/ssv6200_aux.h	8369;"	d
+TX_SEQ_CTRL_0_4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8359;"	d
+TX_SEQ_CTRL_0_4_I_MSK	include/ssv6200_aux.h	8367;"	d
+TX_SEQ_CTRL_0_4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8357;"	d
+TX_SEQ_CTRL_0_4_MSK	include/ssv6200_aux.h	8366;"	d
+TX_SEQ_CTRL_0_4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8356;"	d
+TX_SEQ_CTRL_0_4_SFT	include/ssv6200_aux.h	8368;"	d
+TX_SEQ_CTRL_0_4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8358;"	d
+TX_SEQ_CTRL_0_4_SZ	include/ssv6200_aux.h	8370;"	d
+TX_SEQ_CTRL_0_4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8360;"	d
+TX_SEQ_CTRL_0_5_HI	include/ssv6200_aux.h	8379;"	d
+TX_SEQ_CTRL_0_5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8369;"	d
+TX_SEQ_CTRL_0_5_I_MSK	include/ssv6200_aux.h	8377;"	d
+TX_SEQ_CTRL_0_5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8367;"	d
+TX_SEQ_CTRL_0_5_MSK	include/ssv6200_aux.h	8376;"	d
+TX_SEQ_CTRL_0_5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8366;"	d
+TX_SEQ_CTRL_0_5_SFT	include/ssv6200_aux.h	8378;"	d
+TX_SEQ_CTRL_0_5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8368;"	d
+TX_SEQ_CTRL_0_5_SZ	include/ssv6200_aux.h	8380;"	d
+TX_SEQ_CTRL_0_5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8370;"	d
+TX_SEQ_CTRL_0_6_HI	include/ssv6200_aux.h	8389;"	d
+TX_SEQ_CTRL_0_6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8379;"	d
+TX_SEQ_CTRL_0_6_I_MSK	include/ssv6200_aux.h	8387;"	d
+TX_SEQ_CTRL_0_6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8377;"	d
+TX_SEQ_CTRL_0_6_MSK	include/ssv6200_aux.h	8386;"	d
+TX_SEQ_CTRL_0_6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8376;"	d
+TX_SEQ_CTRL_0_6_SFT	include/ssv6200_aux.h	8388;"	d
+TX_SEQ_CTRL_0_6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8378;"	d
+TX_SEQ_CTRL_0_6_SZ	include/ssv6200_aux.h	8390;"	d
+TX_SEQ_CTRL_0_6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8380;"	d
+TX_SEQ_CTRL_0_7_HI	include/ssv6200_aux.h	8399;"	d
+TX_SEQ_CTRL_0_7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8389;"	d
+TX_SEQ_CTRL_0_7_I_MSK	include/ssv6200_aux.h	8397;"	d
+TX_SEQ_CTRL_0_7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8387;"	d
+TX_SEQ_CTRL_0_7_MSK	include/ssv6200_aux.h	8396;"	d
+TX_SEQ_CTRL_0_7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8386;"	d
+TX_SEQ_CTRL_0_7_SFT	include/ssv6200_aux.h	8398;"	d
+TX_SEQ_CTRL_0_7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8388;"	d
+TX_SEQ_CTRL_0_7_SZ	include/ssv6200_aux.h	8400;"	d
+TX_SEQ_CTRL_0_7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8390;"	d
+TX_SEQ_CTRL_1_0_HI	include/ssv6200_aux.h	8439;"	d
+TX_SEQ_CTRL_1_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8429;"	d
+TX_SEQ_CTRL_1_0_I_MSK	include/ssv6200_aux.h	8437;"	d
+TX_SEQ_CTRL_1_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8427;"	d
+TX_SEQ_CTRL_1_0_MSK	include/ssv6200_aux.h	8436;"	d
+TX_SEQ_CTRL_1_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8426;"	d
+TX_SEQ_CTRL_1_0_SFT	include/ssv6200_aux.h	8438;"	d
+TX_SEQ_CTRL_1_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8428;"	d
+TX_SEQ_CTRL_1_0_SZ	include/ssv6200_aux.h	8440;"	d
+TX_SEQ_CTRL_1_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8430;"	d
+TX_SEQ_CTRL_1_1_HI	include/ssv6200_aux.h	8449;"	d
+TX_SEQ_CTRL_1_1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8439;"	d
+TX_SEQ_CTRL_1_1_I_MSK	include/ssv6200_aux.h	8447;"	d
+TX_SEQ_CTRL_1_1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8437;"	d
+TX_SEQ_CTRL_1_1_MSK	include/ssv6200_aux.h	8446;"	d
+TX_SEQ_CTRL_1_1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8436;"	d
+TX_SEQ_CTRL_1_1_SFT	include/ssv6200_aux.h	8448;"	d
+TX_SEQ_CTRL_1_1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8438;"	d
+TX_SEQ_CTRL_1_1_SZ	include/ssv6200_aux.h	8450;"	d
+TX_SEQ_CTRL_1_1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8440;"	d
+TX_SEQ_CTRL_1_2_HI	include/ssv6200_aux.h	8459;"	d
+TX_SEQ_CTRL_1_2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8449;"	d
+TX_SEQ_CTRL_1_2_I_MSK	include/ssv6200_aux.h	8457;"	d
+TX_SEQ_CTRL_1_2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8447;"	d
+TX_SEQ_CTRL_1_2_MSK	include/ssv6200_aux.h	8456;"	d
+TX_SEQ_CTRL_1_2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8446;"	d
+TX_SEQ_CTRL_1_2_SFT	include/ssv6200_aux.h	8458;"	d
+TX_SEQ_CTRL_1_2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8448;"	d
+TX_SEQ_CTRL_1_2_SZ	include/ssv6200_aux.h	8460;"	d
+TX_SEQ_CTRL_1_2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8450;"	d
+TX_SEQ_CTRL_1_3_HI	include/ssv6200_aux.h	8469;"	d
+TX_SEQ_CTRL_1_3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8459;"	d
+TX_SEQ_CTRL_1_3_I_MSK	include/ssv6200_aux.h	8467;"	d
+TX_SEQ_CTRL_1_3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8457;"	d
+TX_SEQ_CTRL_1_3_MSK	include/ssv6200_aux.h	8466;"	d
+TX_SEQ_CTRL_1_3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8456;"	d
+TX_SEQ_CTRL_1_3_SFT	include/ssv6200_aux.h	8468;"	d
+TX_SEQ_CTRL_1_3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8458;"	d
+TX_SEQ_CTRL_1_3_SZ	include/ssv6200_aux.h	8470;"	d
+TX_SEQ_CTRL_1_3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8460;"	d
+TX_SEQ_CTRL_1_4_HI	include/ssv6200_aux.h	8479;"	d
+TX_SEQ_CTRL_1_4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8469;"	d
+TX_SEQ_CTRL_1_4_I_MSK	include/ssv6200_aux.h	8477;"	d
+TX_SEQ_CTRL_1_4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8467;"	d
+TX_SEQ_CTRL_1_4_MSK	include/ssv6200_aux.h	8476;"	d
+TX_SEQ_CTRL_1_4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8466;"	d
+TX_SEQ_CTRL_1_4_SFT	include/ssv6200_aux.h	8478;"	d
+TX_SEQ_CTRL_1_4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8468;"	d
+TX_SEQ_CTRL_1_4_SZ	include/ssv6200_aux.h	8480;"	d
+TX_SEQ_CTRL_1_4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8470;"	d
+TX_SEQ_CTRL_1_5_HI	include/ssv6200_aux.h	8489;"	d
+TX_SEQ_CTRL_1_5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8479;"	d
+TX_SEQ_CTRL_1_5_I_MSK	include/ssv6200_aux.h	8487;"	d
+TX_SEQ_CTRL_1_5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8477;"	d
+TX_SEQ_CTRL_1_5_MSK	include/ssv6200_aux.h	8486;"	d
+TX_SEQ_CTRL_1_5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8476;"	d
+TX_SEQ_CTRL_1_5_SFT	include/ssv6200_aux.h	8488;"	d
+TX_SEQ_CTRL_1_5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8478;"	d
+TX_SEQ_CTRL_1_5_SZ	include/ssv6200_aux.h	8490;"	d
+TX_SEQ_CTRL_1_5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8480;"	d
+TX_SEQ_CTRL_1_6_HI	include/ssv6200_aux.h	8499;"	d
+TX_SEQ_CTRL_1_6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8489;"	d
+TX_SEQ_CTRL_1_6_I_MSK	include/ssv6200_aux.h	8497;"	d
+TX_SEQ_CTRL_1_6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8487;"	d
+TX_SEQ_CTRL_1_6_MSK	include/ssv6200_aux.h	8496;"	d
+TX_SEQ_CTRL_1_6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8486;"	d
+TX_SEQ_CTRL_1_6_SFT	include/ssv6200_aux.h	8498;"	d
+TX_SEQ_CTRL_1_6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8488;"	d
+TX_SEQ_CTRL_1_6_SZ	include/ssv6200_aux.h	8500;"	d
+TX_SEQ_CTRL_1_6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8490;"	d
+TX_SEQ_CTRL_1_7_HI	include/ssv6200_aux.h	8509;"	d
+TX_SEQ_CTRL_1_7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8499;"	d
+TX_SEQ_CTRL_1_7_I_MSK	include/ssv6200_aux.h	8507;"	d
+TX_SEQ_CTRL_1_7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8497;"	d
+TX_SEQ_CTRL_1_7_MSK	include/ssv6200_aux.h	8506;"	d
+TX_SEQ_CTRL_1_7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8496;"	d
+TX_SEQ_CTRL_1_7_SFT	include/ssv6200_aux.h	8508;"	d
+TX_SEQ_CTRL_1_7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8498;"	d
+TX_SEQ_CTRL_1_7_SZ	include/ssv6200_aux.h	8510;"	d
+TX_SEQ_CTRL_1_7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8500;"	d
+TX_SEQ_CTRL_2_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9594;"	d
+TX_SEQ_CTRL_2_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9592;"	d
+TX_SEQ_CTRL_2_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9591;"	d
+TX_SEQ_CTRL_2_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9593;"	d
+TX_SEQ_CTRL_2_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9595;"	d
+TX_SEQ_CTRL_2_1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9604;"	d
+TX_SEQ_CTRL_2_1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9602;"	d
+TX_SEQ_CTRL_2_1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9601;"	d
+TX_SEQ_CTRL_2_1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9603;"	d
+TX_SEQ_CTRL_2_1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9605;"	d
+TX_SEQ_CTRL_2_2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9614;"	d
+TX_SEQ_CTRL_2_2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9612;"	d
+TX_SEQ_CTRL_2_2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9611;"	d
+TX_SEQ_CTRL_2_2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9613;"	d
+TX_SEQ_CTRL_2_2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9615;"	d
+TX_SEQ_CTRL_2_3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9624;"	d
+TX_SEQ_CTRL_2_3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9622;"	d
+TX_SEQ_CTRL_2_3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9621;"	d
+TX_SEQ_CTRL_2_3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9623;"	d
+TX_SEQ_CTRL_2_3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9625;"	d
+TX_SEQ_CTRL_2_4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9634;"	d
+TX_SEQ_CTRL_2_4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9632;"	d
+TX_SEQ_CTRL_2_4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9631;"	d
+TX_SEQ_CTRL_2_4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9633;"	d
+TX_SEQ_CTRL_2_4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9635;"	d
+TX_SEQ_CTRL_2_5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9644;"	d
+TX_SEQ_CTRL_2_5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9642;"	d
+TX_SEQ_CTRL_2_5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9641;"	d
+TX_SEQ_CTRL_2_5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9643;"	d
+TX_SEQ_CTRL_2_5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9645;"	d
+TX_SEQ_CTRL_2_6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9654;"	d
+TX_SEQ_CTRL_2_6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9652;"	d
+TX_SEQ_CTRL_2_6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9651;"	d
+TX_SEQ_CTRL_2_6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9653;"	d
+TX_SEQ_CTRL_2_6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9655;"	d
+TX_SEQ_CTRL_2_7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9664;"	d
+TX_SEQ_CTRL_2_7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9662;"	d
+TX_SEQ_CTRL_2_7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9661;"	d
+TX_SEQ_CTRL_2_7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9663;"	d
+TX_SEQ_CTRL_2_7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9665;"	d
+TX_SEQ_CTRL_3_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9704;"	d
+TX_SEQ_CTRL_3_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9702;"	d
+TX_SEQ_CTRL_3_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9701;"	d
+TX_SEQ_CTRL_3_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9703;"	d
+TX_SEQ_CTRL_3_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9705;"	d
+TX_SEQ_CTRL_3_1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9714;"	d
+TX_SEQ_CTRL_3_1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9712;"	d
+TX_SEQ_CTRL_3_1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9711;"	d
+TX_SEQ_CTRL_3_1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9713;"	d
+TX_SEQ_CTRL_3_1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9715;"	d
+TX_SEQ_CTRL_3_2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9724;"	d
+TX_SEQ_CTRL_3_2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9722;"	d
+TX_SEQ_CTRL_3_2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9721;"	d
+TX_SEQ_CTRL_3_2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9723;"	d
+TX_SEQ_CTRL_3_2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9725;"	d
+TX_SEQ_CTRL_3_3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9734;"	d
+TX_SEQ_CTRL_3_3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9732;"	d
+TX_SEQ_CTRL_3_3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9731;"	d
+TX_SEQ_CTRL_3_3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9733;"	d
+TX_SEQ_CTRL_3_3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9735;"	d
+TX_SEQ_CTRL_3_4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9744;"	d
+TX_SEQ_CTRL_3_4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9742;"	d
+TX_SEQ_CTRL_3_4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9741;"	d
+TX_SEQ_CTRL_3_4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9743;"	d
+TX_SEQ_CTRL_3_4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9745;"	d
+TX_SEQ_CTRL_3_5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9754;"	d
+TX_SEQ_CTRL_3_5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9752;"	d
+TX_SEQ_CTRL_3_5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9751;"	d
+TX_SEQ_CTRL_3_5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9753;"	d
+TX_SEQ_CTRL_3_5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9755;"	d
+TX_SEQ_CTRL_3_6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9764;"	d
+TX_SEQ_CTRL_3_6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9762;"	d
+TX_SEQ_CTRL_3_6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9761;"	d
+TX_SEQ_CTRL_3_6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9763;"	d
+TX_SEQ_CTRL_3_6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9765;"	d
+TX_SEQ_CTRL_3_7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9774;"	d
+TX_SEQ_CTRL_3_7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9772;"	d
+TX_SEQ_CTRL_3_7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9771;"	d
+TX_SEQ_CTRL_3_7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9773;"	d
+TX_SEQ_CTRL_3_7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9775;"	d
+TX_SEQ_CTRL_4_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9814;"	d
+TX_SEQ_CTRL_4_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9812;"	d
+TX_SEQ_CTRL_4_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9811;"	d
+TX_SEQ_CTRL_4_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9813;"	d
+TX_SEQ_CTRL_4_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9815;"	d
+TX_SEQ_CTRL_4_1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9824;"	d
+TX_SEQ_CTRL_4_1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9822;"	d
+TX_SEQ_CTRL_4_1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9821;"	d
+TX_SEQ_CTRL_4_1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9823;"	d
+TX_SEQ_CTRL_4_1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9825;"	d
+TX_SEQ_CTRL_4_2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9834;"	d
+TX_SEQ_CTRL_4_2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9832;"	d
+TX_SEQ_CTRL_4_2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9831;"	d
+TX_SEQ_CTRL_4_2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9833;"	d
+TX_SEQ_CTRL_4_2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9835;"	d
+TX_SEQ_CTRL_4_3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9844;"	d
+TX_SEQ_CTRL_4_3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9842;"	d
+TX_SEQ_CTRL_4_3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9841;"	d
+TX_SEQ_CTRL_4_3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9843;"	d
+TX_SEQ_CTRL_4_3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9845;"	d
+TX_SEQ_CTRL_4_4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9854;"	d
+TX_SEQ_CTRL_4_4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9852;"	d
+TX_SEQ_CTRL_4_4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9851;"	d
+TX_SEQ_CTRL_4_4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9853;"	d
+TX_SEQ_CTRL_4_4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9855;"	d
+TX_SEQ_CTRL_4_5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9864;"	d
+TX_SEQ_CTRL_4_5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9862;"	d
+TX_SEQ_CTRL_4_5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9861;"	d
+TX_SEQ_CTRL_4_5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9863;"	d
+TX_SEQ_CTRL_4_5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9865;"	d
+TX_SEQ_CTRL_4_6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9874;"	d
+TX_SEQ_CTRL_4_6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9872;"	d
+TX_SEQ_CTRL_4_6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9871;"	d
+TX_SEQ_CTRL_4_6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9873;"	d
+TX_SEQ_CTRL_4_6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9875;"	d
+TX_SEQ_CTRL_4_7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9884;"	d
+TX_SEQ_CTRL_4_7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9882;"	d
+TX_SEQ_CTRL_4_7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9881;"	d
+TX_SEQ_CTRL_4_7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9883;"	d
+TX_SEQ_CTRL_4_7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9885;"	d
+TX_SEQ_CTRL_5_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9924;"	d
+TX_SEQ_CTRL_5_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9922;"	d
+TX_SEQ_CTRL_5_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9921;"	d
+TX_SEQ_CTRL_5_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9923;"	d
+TX_SEQ_CTRL_5_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9925;"	d
+TX_SEQ_CTRL_5_1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9934;"	d
+TX_SEQ_CTRL_5_1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9932;"	d
+TX_SEQ_CTRL_5_1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9931;"	d
+TX_SEQ_CTRL_5_1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9933;"	d
+TX_SEQ_CTRL_5_1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9935;"	d
+TX_SEQ_CTRL_5_2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9944;"	d
+TX_SEQ_CTRL_5_2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9942;"	d
+TX_SEQ_CTRL_5_2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9941;"	d
+TX_SEQ_CTRL_5_2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9943;"	d
+TX_SEQ_CTRL_5_2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9945;"	d
+TX_SEQ_CTRL_5_3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9954;"	d
+TX_SEQ_CTRL_5_3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9952;"	d
+TX_SEQ_CTRL_5_3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9951;"	d
+TX_SEQ_CTRL_5_3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9953;"	d
+TX_SEQ_CTRL_5_3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9955;"	d
+TX_SEQ_CTRL_5_4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9964;"	d
+TX_SEQ_CTRL_5_4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9962;"	d
+TX_SEQ_CTRL_5_4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9961;"	d
+TX_SEQ_CTRL_5_4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9963;"	d
+TX_SEQ_CTRL_5_4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9965;"	d
+TX_SEQ_CTRL_5_5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9974;"	d
+TX_SEQ_CTRL_5_5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9972;"	d
+TX_SEQ_CTRL_5_5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9971;"	d
+TX_SEQ_CTRL_5_5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9973;"	d
+TX_SEQ_CTRL_5_5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9975;"	d
+TX_SEQ_CTRL_5_6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9984;"	d
+TX_SEQ_CTRL_5_6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9982;"	d
+TX_SEQ_CTRL_5_6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9981;"	d
+TX_SEQ_CTRL_5_6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9983;"	d
+TX_SEQ_CTRL_5_6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9985;"	d
+TX_SEQ_CTRL_5_7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9994;"	d
+TX_SEQ_CTRL_5_7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9992;"	d
+TX_SEQ_CTRL_5_7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9991;"	d
+TX_SEQ_CTRL_5_7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9993;"	d
+TX_SEQ_CTRL_5_7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9995;"	d
+TX_SEQ_CTRL_6_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10034;"	d
+TX_SEQ_CTRL_6_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10032;"	d
+TX_SEQ_CTRL_6_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10031;"	d
+TX_SEQ_CTRL_6_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10033;"	d
+TX_SEQ_CTRL_6_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10035;"	d
+TX_SEQ_CTRL_6_1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10044;"	d
+TX_SEQ_CTRL_6_1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10042;"	d
+TX_SEQ_CTRL_6_1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10041;"	d
+TX_SEQ_CTRL_6_1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10043;"	d
+TX_SEQ_CTRL_6_1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10045;"	d
+TX_SEQ_CTRL_6_2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10054;"	d
+TX_SEQ_CTRL_6_2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10052;"	d
+TX_SEQ_CTRL_6_2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10051;"	d
+TX_SEQ_CTRL_6_2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10053;"	d
+TX_SEQ_CTRL_6_2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10055;"	d
+TX_SEQ_CTRL_6_3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10064;"	d
+TX_SEQ_CTRL_6_3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10062;"	d
+TX_SEQ_CTRL_6_3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10061;"	d
+TX_SEQ_CTRL_6_3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10063;"	d
+TX_SEQ_CTRL_6_3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10065;"	d
+TX_SEQ_CTRL_6_4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10074;"	d
+TX_SEQ_CTRL_6_4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10072;"	d
+TX_SEQ_CTRL_6_4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10071;"	d
+TX_SEQ_CTRL_6_4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10073;"	d
+TX_SEQ_CTRL_6_4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10075;"	d
+TX_SEQ_CTRL_6_5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10084;"	d
+TX_SEQ_CTRL_6_5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10082;"	d
+TX_SEQ_CTRL_6_5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10081;"	d
+TX_SEQ_CTRL_6_5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10083;"	d
+TX_SEQ_CTRL_6_5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10085;"	d
+TX_SEQ_CTRL_6_6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10094;"	d
+TX_SEQ_CTRL_6_6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10092;"	d
+TX_SEQ_CTRL_6_6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10091;"	d
+TX_SEQ_CTRL_6_6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10093;"	d
+TX_SEQ_CTRL_6_6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10095;"	d
+TX_SEQ_CTRL_6_7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10104;"	d
+TX_SEQ_CTRL_6_7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10102;"	d
+TX_SEQ_CTRL_6_7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10101;"	d
+TX_SEQ_CTRL_6_7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10103;"	d
+TX_SEQ_CTRL_6_7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10105;"	d
+TX_SEQ_CTRL_7_0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10144;"	d
+TX_SEQ_CTRL_7_0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10142;"	d
+TX_SEQ_CTRL_7_0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10141;"	d
+TX_SEQ_CTRL_7_0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10143;"	d
+TX_SEQ_CTRL_7_0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10145;"	d
+TX_SEQ_CTRL_7_1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10154;"	d
+TX_SEQ_CTRL_7_1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10152;"	d
+TX_SEQ_CTRL_7_1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10151;"	d
+TX_SEQ_CTRL_7_1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10153;"	d
+TX_SEQ_CTRL_7_1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10155;"	d
+TX_SEQ_CTRL_7_2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10164;"	d
+TX_SEQ_CTRL_7_2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10162;"	d
+TX_SEQ_CTRL_7_2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10161;"	d
+TX_SEQ_CTRL_7_2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10163;"	d
+TX_SEQ_CTRL_7_2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10165;"	d
+TX_SEQ_CTRL_7_3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10174;"	d
+TX_SEQ_CTRL_7_3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10172;"	d
+TX_SEQ_CTRL_7_3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10171;"	d
+TX_SEQ_CTRL_7_3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10173;"	d
+TX_SEQ_CTRL_7_3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10175;"	d
+TX_SEQ_CTRL_7_4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10184;"	d
+TX_SEQ_CTRL_7_4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10182;"	d
+TX_SEQ_CTRL_7_4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10181;"	d
+TX_SEQ_CTRL_7_4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10183;"	d
+TX_SEQ_CTRL_7_4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10185;"	d
+TX_SEQ_CTRL_7_5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10194;"	d
+TX_SEQ_CTRL_7_5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10192;"	d
+TX_SEQ_CTRL_7_5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10191;"	d
+TX_SEQ_CTRL_7_5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10193;"	d
+TX_SEQ_CTRL_7_5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10195;"	d
+TX_SEQ_CTRL_7_6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10204;"	d
+TX_SEQ_CTRL_7_6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10202;"	d
+TX_SEQ_CTRL_7_6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10201;"	d
+TX_SEQ_CTRL_7_6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10203;"	d
+TX_SEQ_CTRL_7_6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10205;"	d
+TX_SEQ_CTRL_7_7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10214;"	d
+TX_SEQ_CTRL_7_7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10212;"	d
+TX_SEQ_CTRL_7_7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10211;"	d
+TX_SEQ_CTRL_7_7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10213;"	d
+TX_SEQ_CTRL_7_7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10215;"	d
+TX_SET_CNT_CLR_HI	include/ssv6200_aux.h	4094;"	d
+TX_SET_CNT_CLR_I_MSK	include/ssv6200_aux.h	4092;"	d
+TX_SET_CNT_CLR_MSK	include/ssv6200_aux.h	4091;"	d
+TX_SET_CNT_CLR_SFT	include/ssv6200_aux.h	4093;"	d
+TX_SET_CNT_CLR_SZ	include/ssv6200_aux.h	4095;"	d
+TX_SET_CNT_HI	include/ssv6200_aux.h	4079;"	d
+TX_SET_CNT_I_MSK	include/ssv6200_aux.h	4077;"	d
+TX_SET_CNT_MSK	include/ssv6200_aux.h	4076;"	d
+TX_SET_CNT_SFT	include/ssv6200_aux.h	4078;"	d
+TX_SET_CNT_SZ	include/ssv6200_aux.h	4080;"	d
+TX_SIZE_BEFORE_SHIFT_HI	include/ssv6200_aux.h	3479;"	d
+TX_SIZE_BEFORE_SHIFT_I_MSK	include/ssv6200_aux.h	3477;"	d
+TX_SIZE_BEFORE_SHIFT_MSK	include/ssv6200_aux.h	3476;"	d
+TX_SIZE_BEFORE_SHIFT_SFT	include/ssv6200_aux.h	3478;"	d
+TX_SIZE_BEFORE_SHIFT_SZ	include/ssv6200_aux.h	3480;"	d
+TX_SIZE_SHIFT_BITS_HI	include/ssv6200_aux.h	3484;"	d
+TX_SIZE_SHIFT_BITS_I_MSK	include/ssv6200_aux.h	3482;"	d
+TX_SIZE_SHIFT_BITS_MSK	include/ssv6200_aux.h	3481;"	d
+TX_SIZE_SHIFT_BITS_SFT	include/ssv6200_aux.h	3483;"	d
+TX_SIZE_SHIFT_BITS_SZ	include/ssv6200_aux.h	3485;"	d
+TX_THRH_IE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3389;"	d
+TX_THRH_IE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3387;"	d
+TX_THRH_IE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3386;"	d
+TX_THRH_IE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3388;"	d
+TX_THRH_IE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3390;"	d
+TX_THRL_IE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3394;"	d
+TX_THRL_IE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3392;"	d
+TX_THRL_IE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3391;"	d
+TX_THRL_IE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3393;"	d
+TX_THRL_IE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3395;"	d
+TX_TRAP_HW_ID_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5534;"	d
+TX_TRAP_HW_ID_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5532;"	d
+TX_TRAP_HW_ID_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5531;"	d
+TX_TRAP_HW_ID_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5533;"	d
+TX_TRAP_HW_ID_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5535;"	d
+T_Transform	smac/wapi_sms4.c	/^static u32 T_Transform(u32 Word)$/;"	f	file:	signature:(u32 Word)
+TxF_ID	include/ssv6200_common.h	/^    u32 TxF_ID:6;$/;"	m	struct:ssv6200_tx_desc	access:public
+TxF_ID	smac/hal/ssv6006c/turismo_common.h	/^    u32 TxF_ID:6;$/;"	m	struct:ssv6006_tx_desc	access:public
+UART_CLK_EN_HI	include/ssv6200_aux.h	214;"	d
+UART_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1164;"	d
+UART_CLK_EN_I_MSK	include/ssv6200_aux.h	212;"	d
+UART_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1162;"	d
+UART_CLK_EN_MSK	include/ssv6200_aux.h	211;"	d
+UART_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1161;"	d
+UART_CLK_EN_SFT	include/ssv6200_aux.h	213;"	d
+UART_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1163;"	d
+UART_CLK_EN_SZ	include/ssv6200_aux.h	215;"	d
+UART_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1165;"	d
+UART_DATA_HI	include/ssv6200_aux.h	4259;"	d
+UART_DATA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3364;"	d
+UART_DATA_I_MSK	include/ssv6200_aux.h	4257;"	d
+UART_DATA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3362;"	d
+UART_DATA_MSK	include/ssv6200_aux.h	4256;"	d
+UART_DATA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3361;"	d
+UART_DATA_SFT	include/ssv6200_aux.h	4258;"	d
+UART_DATA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3363;"	d
+UART_DATA_SZ	include/ssv6200_aux.h	4260;"	d
+UART_DATA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3365;"	d
+UART_MULTI_IRQ_HI	include/ssv6200_aux.h	4989;"	d
+UART_MULTI_IRQ_I_MSK	include/ssv6200_aux.h	4987;"	d
+UART_MULTI_IRQ_MSK	include/ssv6200_aux.h	4986;"	d
+UART_MULTI_IRQ_SD_HI	include/ssv6200_aux.h	5334;"	d
+UART_MULTI_IRQ_SD_I_MSK	include/ssv6200_aux.h	5332;"	d
+UART_MULTI_IRQ_SD_MSK	include/ssv6200_aux.h	5331;"	d
+UART_MULTI_IRQ_SD_SFT	include/ssv6200_aux.h	5333;"	d
+UART_MULTI_IRQ_SD_SZ	include/ssv6200_aux.h	5335;"	d
+UART_MULTI_IRQ_SFT	include/ssv6200_aux.h	4988;"	d
+UART_MULTI_IRQ_SZ	include/ssv6200_aux.h	4990;"	d
+UART_NCTS_HI	include/ssv6200_aux.h	624;"	d
+UART_NCTS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1699;"	d
+UART_NCTS_I_MSK	include/ssv6200_aux.h	622;"	d
+UART_NCTS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1697;"	d
+UART_NCTS_MSK	include/ssv6200_aux.h	621;"	d
+UART_NCTS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1696;"	d
+UART_NCTS_SFT	include/ssv6200_aux.h	623;"	d
+UART_NCTS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1698;"	d
+UART_NCTS_SZ	include/ssv6200_aux.h	625;"	d
+UART_NCTS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1700;"	d
+UART_NRTS_HI	include/ssv6200_aux.h	619;"	d
+UART_NRTS_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1694;"	d
+UART_NRTS_I_MSK	include/ssv6200_aux.h	617;"	d
+UART_NRTS_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1692;"	d
+UART_NRTS_MSK	include/ssv6200_aux.h	616;"	d
+UART_NRTS_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1691;"	d
+UART_NRTS_SFT	include/ssv6200_aux.h	618;"	d
+UART_NRTS_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1693;"	d
+UART_NRTS_SZ	include/ssv6200_aux.h	620;"	d
+UART_NRTS_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1695;"	d
+UART_REG_BANK_SIZE	include/ssv6200_reg.h	81;"	d
+UART_REG_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	100;"	d
+UART_REG_BASE	include/ssv6200_reg.h	32;"	d
+UART_REG_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	39;"	d
+UART_RXD_SEL_HI	include/ssv6200_aux.h	2959;"	d
+UART_RXD_SEL_I_MSK	include/ssv6200_aux.h	2957;"	d
+UART_RXD_SEL_MSK	include/ssv6200_aux.h	2956;"	d
+UART_RXD_SEL_SFT	include/ssv6200_aux.h	2958;"	d
+UART_RXD_SEL_SZ	include/ssv6200_aux.h	2960;"	d
+UART_RX_TIMEOUT_HI	include/ssv6200_aux.h	4984;"	d
+UART_RX_TIMEOUT_I_MSK	include/ssv6200_aux.h	4982;"	d
+UART_RX_TIMEOUT_MSK	include/ssv6200_aux.h	4981;"	d
+UART_RX_TIMEOUT_SD_HI	include/ssv6200_aux.h	5329;"	d
+UART_RX_TIMEOUT_SD_I_MSK	include/ssv6200_aux.h	5327;"	d
+UART_RX_TIMEOUT_SD_MSK	include/ssv6200_aux.h	5326;"	d
+UART_RX_TIMEOUT_SD_SFT	include/ssv6200_aux.h	5328;"	d
+UART_RX_TIMEOUT_SD_SZ	include/ssv6200_aux.h	5330;"	d
+UART_RX_TIMEOUT_SFT	include/ssv6200_aux.h	4983;"	d
+UART_RX_TIMEOUT_SZ	include/ssv6200_aux.h	4985;"	d
+UART_SW_RST_HI	include/ssv6200_aux.h	44;"	d
+UART_SW_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	999;"	d
+UART_SW_RST_I_MSK	include/ssv6200_aux.h	42;"	d
+UART_SW_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	997;"	d
+UART_SW_RST_MSK	include/ssv6200_aux.h	41;"	d
+UART_SW_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	996;"	d
+UART_SW_RST_SFT	include/ssv6200_aux.h	43;"	d
+UART_SW_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	998;"	d
+UART_SW_RST_SZ	include/ssv6200_aux.h	45;"	d
+UART_SW_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1000;"	d
+UART_W2B_EN_HI	include/ssv6200_aux.h	439;"	d
+UART_W2B_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1394;"	d
+UART_W2B_EN_I_MSK	include/ssv6200_aux.h	437;"	d
+UART_W2B_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1392;"	d
+UART_W2B_EN_MSK	include/ssv6200_aux.h	436;"	d
+UART_W2B_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1391;"	d
+UART_W2B_EN_SFT	include/ssv6200_aux.h	438;"	d
+UART_W2B_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1393;"	d
+UART_W2B_EN_SZ	include/ssv6200_aux.h	440;"	d
+UART_W2B_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1395;"	d
+UDELAY	smac/hal/ssv6006c/ssv6006_priv.h	27;"	d
+UDELAY	smac/hal/ssv6006c/turismo_common.h	308;"	d
+UPDATE_PHY_INFO_ACK_RATE	smac/ssv_rc.c	1564;"	d	file:
+US0TMR_CLK_EN_HI	include/ssv6200_aux.h	249;"	d
+US0TMR_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1199;"	d
+US0TMR_CLK_EN_I_MSK	include/ssv6200_aux.h	247;"	d
+US0TMR_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1197;"	d
+US0TMR_CLK_EN_MSK	include/ssv6200_aux.h	246;"	d
+US0TMR_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1196;"	d
+US0TMR_CLK_EN_SFT	include/ssv6200_aux.h	248;"	d
+US0TMR_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1198;"	d
+US0TMR_CLK_EN_SZ	include/ssv6200_aux.h	250;"	d
+US0TMR_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1200;"	d
+US0TMR_SW_RST_HI	include/ssv6200_aux.h	79;"	d
+US0TMR_SW_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1029;"	d
+US0TMR_SW_RST_I_MSK	include/ssv6200_aux.h	77;"	d
+US0TMR_SW_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1027;"	d
+US0TMR_SW_RST_MSK	include/ssv6200_aux.h	76;"	d
+US0TMR_SW_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1026;"	d
+US0TMR_SW_RST_SFT	include/ssv6200_aux.h	78;"	d
+US0TMR_SW_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1028;"	d
+US0TMR_SW_RST_SZ	include/ssv6200_aux.h	80;"	d
+US0TMR_SW_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1030;"	d
+US1TMR_CLK_EN_HI	include/ssv6200_aux.h	254;"	d
+US1TMR_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1204;"	d
+US1TMR_CLK_EN_I_MSK	include/ssv6200_aux.h	252;"	d
+US1TMR_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1202;"	d
+US1TMR_CLK_EN_MSK	include/ssv6200_aux.h	251;"	d
+US1TMR_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1201;"	d
+US1TMR_CLK_EN_SFT	include/ssv6200_aux.h	253;"	d
+US1TMR_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1203;"	d
+US1TMR_CLK_EN_SZ	include/ssv6200_aux.h	255;"	d
+US1TMR_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1205;"	d
+US1TMR_SW_RST_HI	include/ssv6200_aux.h	84;"	d
+US1TMR_SW_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1034;"	d
+US1TMR_SW_RST_I_MSK	include/ssv6200_aux.h	82;"	d
+US1TMR_SW_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1032;"	d
+US1TMR_SW_RST_MSK	include/ssv6200_aux.h	81;"	d
+US1TMR_SW_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1031;"	d
+US1TMR_SW_RST_SFT	include/ssv6200_aux.h	83;"	d
+US1TMR_SW_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1033;"	d
+US1TMR_SW_RST_SZ	include/ssv6200_aux.h	85;"	d
+US1TMR_SW_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1035;"	d
+US2TMR_CLK_EN_HI	include/ssv6200_aux.h	259;"	d
+US2TMR_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1209;"	d
+US2TMR_CLK_EN_I_MSK	include/ssv6200_aux.h	257;"	d
+US2TMR_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1207;"	d
+US2TMR_CLK_EN_MSK	include/ssv6200_aux.h	256;"	d
+US2TMR_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1206;"	d
+US2TMR_CLK_EN_SFT	include/ssv6200_aux.h	258;"	d
+US2TMR_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1208;"	d
+US2TMR_CLK_EN_SZ	include/ssv6200_aux.h	260;"	d
+US2TMR_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1210;"	d
+US2TMR_SW_RST_HI	include/ssv6200_aux.h	89;"	d
+US2TMR_SW_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1039;"	d
+US2TMR_SW_RST_I_MSK	include/ssv6200_aux.h	87;"	d
+US2TMR_SW_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1037;"	d
+US2TMR_SW_RST_MSK	include/ssv6200_aux.h	86;"	d
+US2TMR_SW_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1036;"	d
+US2TMR_SW_RST_SFT	include/ssv6200_aux.h	88;"	d
+US2TMR_SW_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1038;"	d
+US2TMR_SW_RST_SZ	include/ssv6200_aux.h	90;"	d
+US2TMR_SW_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1040;"	d
+US3TMR_CLK_EN_HI	include/ssv6200_aux.h	264;"	d
+US3TMR_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1214;"	d
+US3TMR_CLK_EN_I_MSK	include/ssv6200_aux.h	262;"	d
+US3TMR_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1212;"	d
+US3TMR_CLK_EN_MSK	include/ssv6200_aux.h	261;"	d
+US3TMR_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1211;"	d
+US3TMR_CLK_EN_SFT	include/ssv6200_aux.h	263;"	d
+US3TMR_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1213;"	d
+US3TMR_CLK_EN_SZ	include/ssv6200_aux.h	265;"	d
+US3TMR_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1215;"	d
+US3TMR_SW_RST_HI	include/ssv6200_aux.h	94;"	d
+US3TMR_SW_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1044;"	d
+US3TMR_SW_RST_I_MSK	include/ssv6200_aux.h	92;"	d
+US3TMR_SW_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1042;"	d
+US3TMR_SW_RST_MSK	include/ssv6200_aux.h	91;"	d
+US3TMR_SW_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1041;"	d
+US3TMR_SW_RST_SFT	include/ssv6200_aux.h	93;"	d
+US3TMR_SW_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1043;"	d
+US3TMR_SW_RST_SZ	include/ssv6200_aux.h	95;"	d
+US3TMR_SW_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1045;"	d
+USB20_HOST_SELRW_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1639;"	d
+USB20_HOST_SELRW_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1637;"	d
+USB20_HOST_SELRW_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1636;"	d
+USB20_HOST_SELRW_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1638;"	d
+USB20_HOST_SELRW_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1640;"	d
+USB_BULK_IN_LEN_INIT_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5379;"	d
+USB_BULK_IN_LEN_INIT_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5377;"	d
+USB_BULK_IN_LEN_INIT_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5376;"	d
+USB_BULK_IN_LEN_INIT_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5378;"	d
+USB_BULK_IN_LEN_INIT_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5380;"	d
+USB_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1264;"	d
+USB_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1262;"	d
+USB_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1261;"	d
+USB_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1263;"	d
+USB_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1265;"	d
+USB_CMD_SEQUENCE	hwif/usb/usb.c	43;"	d	file:
+USB_DBG	hwif/usb/usb.h	19;"	d
+USB_HW_RESOURCE_CHK_FORCE_OFF	include/ssv_cfg.h	38;"	d
+USB_HW_RESOURCE_CHK_NONE	include/ssv_cfg.h	34;"	d
+USB_HW_RESOURCE_CHK_SCAN	include/ssv_cfg.h	37;"	d
+USB_HW_RESOURCE_CHK_TXID	include/ssv_cfg.h	35;"	d
+USB_HW_RESOURCE_CHK_TXPAGE	include/ssv_cfg.h	36;"	d
+USB_SSV_PRODUCT_ID	hwif/usb/usb.c	38;"	d	file:
+USB_SSV_VENDOR_ID	hwif/usb/usb.c	37;"	d	file:
+USB_SW_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	984;"	d
+USB_SW_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	982;"	d
+USB_SW_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	981;"	d
+USB_SW_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	983;"	d
+USB_SW_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	985;"	d
+USB_WAKE_PMU_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1784;"	d
+USB_WAKE_PMU_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1782;"	d
+USB_WAKE_PMU_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1781;"	d
+USB_WAKE_PMU_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1783;"	d
+USB_WAKE_PMU_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1785;"	d
+USE_AMPDU_TX_STATUS_ARRAY	smac/ampdu.h	29;"	d
+USE_COMMON_MACRO	smac/hal/ssv6006c/ssv6006_turismoC.c	58;"	d	file:
+USE_FLUSH_RETRY	smac/ampdu.h	28;"	d
+USE_GENERIC_DECI_TBL	include/ssv_mod_conf.h	43;"	d
+USE_LOCAL_CCMP_CRYPTO	include/ssv_mod_conf.h	55;"	d
+USE_LOCAL_CRYPTO	include/ssv_mod_conf.h	46;"	d
+USE_LOCAL_SMS4_CRYPTO	include/ssv_mod_conf.h	58;"	d
+USE_LOCAL_TKIP_CRYPTO	include/ssv_mod_conf.h	52;"	d
+USE_LOCAL_WEP_CRYPTO	include/ssv_mod_conf.h	49;"	d
+USE_THREAD_RX	include/ssv_mod_conf.h	31;"	d
+USE_THREAD_TX	include/ssv_mod_conf.h	34;"	d
+VALID0_HI	include/ssv6200_aux.h	8294;"	d
+VALID0_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8284;"	d
+VALID0_I_MSK	include/ssv6200_aux.h	8292;"	d
+VALID0_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8282;"	d
+VALID0_MSK	include/ssv6200_aux.h	8291;"	d
+VALID0_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8281;"	d
+VALID0_SFT	include/ssv6200_aux.h	8293;"	d
+VALID0_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8283;"	d
+VALID0_SZ	include/ssv6200_aux.h	8295;"	d
+VALID0_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8285;"	d
+VALID1_HI	include/ssv6200_aux.h	8404;"	d
+VALID1_HI	smac/hal/ssv6006c/ssv6006C_aux.h	8394;"	d
+VALID1_I_MSK	include/ssv6200_aux.h	8402;"	d
+VALID1_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8392;"	d
+VALID1_MSK	include/ssv6200_aux.h	8401;"	d
+VALID1_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	8391;"	d
+VALID1_SFT	include/ssv6200_aux.h	8403;"	d
+VALID1_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	8393;"	d
+VALID1_SZ	include/ssv6200_aux.h	8405;"	d
+VALID1_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	8395;"	d
+VALID2_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9559;"	d
+VALID2_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9557;"	d
+VALID2_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9556;"	d
+VALID2_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9558;"	d
+VALID2_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9560;"	d
+VALID3_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9669;"	d
+VALID3_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9667;"	d
+VALID3_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9666;"	d
+VALID3_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9668;"	d
+VALID3_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9670;"	d
+VALID4_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9779;"	d
+VALID4_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9777;"	d
+VALID4_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9776;"	d
+VALID4_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9778;"	d
+VALID4_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9780;"	d
+VALID5_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9889;"	d
+VALID5_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9887;"	d
+VALID5_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9886;"	d
+VALID5_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9888;"	d
+VALID5_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9890;"	d
+VALID6_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9999;"	d
+VALID6_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9997;"	d
+VALID6_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9996;"	d
+VALID6_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9998;"	d
+VALID6_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10000;"	d
+VALID7_HI	smac/hal/ssv6006c/ssv6006C_aux.h	10109;"	d
+VALID7_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10107;"	d
+VALID7_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	10106;"	d
+VALID7_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	10108;"	d
+VALID7_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	10110;"	d
+VALID_PASS_LEN	smac/kssvsmart.c	30;"	d	file:
+VALID_SSID_LEN	smac/kssvsmart.c	29;"	d	file:
+VERIFY_DATA_HI	include/ssv6200_aux.h	5664;"	d
+VERIFY_DATA_I_MSK	include/ssv6200_aux.h	5662;"	d
+VERIFY_DATA_MSK	include/ssv6200_aux.h	5661;"	d
+VERIFY_DATA_SFT	include/ssv6200_aux.h	5663;"	d
+VERIFY_DATA_SZ	include/ssv6200_aux.h	5665;"	d
+VERIFY_DPD	smac/hal/ssv6006c/turismo_common.h	3346;"	d
+VIAROM_EMA_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1519;"	d
+VIAROM_EMA_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1517;"	d
+VIAROM_EMA_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1516;"	d
+VIAROM_EMA_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1518;"	d
+VIAROM_EMA_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1520;"	d
+VL_FUNC_NOTIFY	smartlink/qqlink-lib-mipsel/include/TXVoiceLink.h	/^typedef void (*VL_FUNC_NOTIFY)(tx_voicelink_param* pparam);$/;"	t
+VT_MON_RDY_HI	include/ssv6200_aux.h	17564;"	d
+VT_MON_RDY_I_MSK	include/ssv6200_aux.h	17562;"	d
+VT_MON_RDY_MSK	include/ssv6200_aux.h	17561;"	d
+VT_MON_RDY_SFT	include/ssv6200_aux.h	17563;"	d
+VT_MON_RDY_SZ	include/ssv6200_aux.h	17565;"	d
+W0_T0_SEQ_HI	include/ssv6200_aux.h	7259;"	d
+W0_T0_SEQ_I_MSK	include/ssv6200_aux.h	7257;"	d
+W0_T0_SEQ_MSK	include/ssv6200_aux.h	7256;"	d
+W0_T0_SEQ_SFT	include/ssv6200_aux.h	7258;"	d
+W0_T0_SEQ_SZ	include/ssv6200_aux.h	7260;"	d
+W0_T1_SEQ_HI	include/ssv6200_aux.h	7264;"	d
+W0_T1_SEQ_I_MSK	include/ssv6200_aux.h	7262;"	d
+W0_T1_SEQ_MSK	include/ssv6200_aux.h	7261;"	d
+W0_T1_SEQ_SFT	include/ssv6200_aux.h	7263;"	d
+W0_T1_SEQ_SZ	include/ssv6200_aux.h	7265;"	d
+W0_T2_SEQ_HI	include/ssv6200_aux.h	7269;"	d
+W0_T2_SEQ_I_MSK	include/ssv6200_aux.h	7267;"	d
+W0_T2_SEQ_MSK	include/ssv6200_aux.h	7266;"	d
+W0_T2_SEQ_SFT	include/ssv6200_aux.h	7268;"	d
+W0_T2_SEQ_SZ	include/ssv6200_aux.h	7270;"	d
+W0_T3_SEQ_HI	include/ssv6200_aux.h	7274;"	d
+W0_T3_SEQ_I_MSK	include/ssv6200_aux.h	7272;"	d
+W0_T3_SEQ_MSK	include/ssv6200_aux.h	7271;"	d
+W0_T3_SEQ_SFT	include/ssv6200_aux.h	7273;"	d
+W0_T3_SEQ_SZ	include/ssv6200_aux.h	7275;"	d
+W0_T4_SEQ_HI	include/ssv6200_aux.h	7279;"	d
+W0_T4_SEQ_I_MSK	include/ssv6200_aux.h	7277;"	d
+W0_T4_SEQ_MSK	include/ssv6200_aux.h	7276;"	d
+W0_T4_SEQ_SFT	include/ssv6200_aux.h	7278;"	d
+W0_T4_SEQ_SZ	include/ssv6200_aux.h	7280;"	d
+W0_T5_SEQ_HI	include/ssv6200_aux.h	7284;"	d
+W0_T5_SEQ_I_MSK	include/ssv6200_aux.h	7282;"	d
+W0_T5_SEQ_MSK	include/ssv6200_aux.h	7281;"	d
+W0_T5_SEQ_SFT	include/ssv6200_aux.h	7283;"	d
+W0_T5_SEQ_SZ	include/ssv6200_aux.h	7285;"	d
+W0_T6_SEQ_HI	include/ssv6200_aux.h	7289;"	d
+W0_T6_SEQ_I_MSK	include/ssv6200_aux.h	7287;"	d
+W0_T6_SEQ_MSK	include/ssv6200_aux.h	7286;"	d
+W0_T6_SEQ_SFT	include/ssv6200_aux.h	7288;"	d
+W0_T6_SEQ_SZ	include/ssv6200_aux.h	7290;"	d
+W0_T7_SEQ_HI	include/ssv6200_aux.h	7294;"	d
+W0_T7_SEQ_I_MSK	include/ssv6200_aux.h	7292;"	d
+W0_T7_SEQ_MSK	include/ssv6200_aux.h	7291;"	d
+W0_T7_SEQ_SFT	include/ssv6200_aux.h	7293;"	d
+W0_T7_SEQ_SZ	include/ssv6200_aux.h	7295;"	d
+W1_T0_SEQ_HI	include/ssv6200_aux.h	7299;"	d
+W1_T0_SEQ_I_MSK	include/ssv6200_aux.h	7297;"	d
+W1_T0_SEQ_MSK	include/ssv6200_aux.h	7296;"	d
+W1_T0_SEQ_SFT	include/ssv6200_aux.h	7298;"	d
+W1_T0_SEQ_SZ	include/ssv6200_aux.h	7300;"	d
+W1_T1_SEQ_HI	include/ssv6200_aux.h	7304;"	d
+W1_T1_SEQ_I_MSK	include/ssv6200_aux.h	7302;"	d
+W1_T1_SEQ_MSK	include/ssv6200_aux.h	7301;"	d
+W1_T1_SEQ_SFT	include/ssv6200_aux.h	7303;"	d
+W1_T1_SEQ_SZ	include/ssv6200_aux.h	7305;"	d
+W1_T2_SEQ_HI	include/ssv6200_aux.h	7309;"	d
+W1_T2_SEQ_I_MSK	include/ssv6200_aux.h	7307;"	d
+W1_T2_SEQ_MSK	include/ssv6200_aux.h	7306;"	d
+W1_T2_SEQ_SFT	include/ssv6200_aux.h	7308;"	d
+W1_T2_SEQ_SZ	include/ssv6200_aux.h	7310;"	d
+W1_T3_SEQ_HI	include/ssv6200_aux.h	7314;"	d
+W1_T3_SEQ_I_MSK	include/ssv6200_aux.h	7312;"	d
+W1_T3_SEQ_MSK	include/ssv6200_aux.h	7311;"	d
+W1_T3_SEQ_SFT	include/ssv6200_aux.h	7313;"	d
+W1_T3_SEQ_SZ	include/ssv6200_aux.h	7315;"	d
+W1_T4_SEQ_HI	include/ssv6200_aux.h	7319;"	d
+W1_T4_SEQ_I_MSK	include/ssv6200_aux.h	7317;"	d
+W1_T4_SEQ_MSK	include/ssv6200_aux.h	7316;"	d
+W1_T4_SEQ_SFT	include/ssv6200_aux.h	7318;"	d
+W1_T4_SEQ_SZ	include/ssv6200_aux.h	7320;"	d
+W1_T5_SEQ_HI	include/ssv6200_aux.h	7324;"	d
+W1_T5_SEQ_I_MSK	include/ssv6200_aux.h	7322;"	d
+W1_T5_SEQ_MSK	include/ssv6200_aux.h	7321;"	d
+W1_T5_SEQ_SFT	include/ssv6200_aux.h	7323;"	d
+W1_T5_SEQ_SZ	include/ssv6200_aux.h	7325;"	d
+W1_T6_SEQ_HI	include/ssv6200_aux.h	7329;"	d
+W1_T6_SEQ_I_MSK	include/ssv6200_aux.h	7327;"	d
+W1_T6_SEQ_MSK	include/ssv6200_aux.h	7326;"	d
+W1_T6_SEQ_SFT	include/ssv6200_aux.h	7328;"	d
+W1_T6_SEQ_SZ	include/ssv6200_aux.h	7330;"	d
+W1_T7_SEQ_HI	include/ssv6200_aux.h	7334;"	d
+W1_T7_SEQ_I_MSK	include/ssv6200_aux.h	7332;"	d
+W1_T7_SEQ_MSK	include/ssv6200_aux.h	7331;"	d
+W1_T7_SEQ_SFT	include/ssv6200_aux.h	7333;"	d
+W1_T7_SEQ_SZ	include/ssv6200_aux.h	7335;"	d
+WAKE_SOON_WITH_SCK_HI	include/ssv6200_aux.h	6129;"	d
+WAKE_SOON_WITH_SCK_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1664;"	d
+WAKE_SOON_WITH_SCK_I_MSK	include/ssv6200_aux.h	6127;"	d
+WAKE_SOON_WITH_SCK_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1662;"	d
+WAKE_SOON_WITH_SCK_MSK	include/ssv6200_aux.h	6126;"	d
+WAKE_SOON_WITH_SCK_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1661;"	d
+WAKE_SOON_WITH_SCK_SFT	include/ssv6200_aux.h	6128;"	d
+WAKE_SOON_WITH_SCK_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1663;"	d
+WAKE_SOON_WITH_SCK_SZ	include/ssv6200_aux.h	6130;"	d
+WAKE_SOON_WITH_SCK_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1665;"	d
+WAPI_IV_ICV_OFFSET	smac/sec_wpi.h	24;"	d
+WAPI_IV_LEN	smac/sec_wpi.h	21;"	d
+WAPI_KEYID_LEN	smac/sec_wpi.h	18;"	d
+WAPI_MIC_LEN	smac/sec_wpi.h	22;"	d
+WAPI_PN_LEN	smac/sec_wpi.h	20;"	d
+WAPI_RESERVD_LEN	smac/sec_wpi.h	19;"	d
+WAPI_SMS4_H	smac/wapi_sms4.h	17;"	d
+WAPI_WPI_H	smac/sec_wpi.h	17;"	d
+WBOOT_REG_BANK_SIZE	include/ssv6200_reg.h	66;"	d
+WBOOT_REG_BASE	include/ssv6200_reg.h	17;"	d
+WCT_MTK7601	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	/^ WCT_MTK7601,$/;"	e	enum:__anon40
+WCT_REALTEK8188	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	/^ WCT_REALTEK8188,$/;"	e	enum:__anon40
+WDT_CLK_EN_HI	include/ssv6200_aux.h	224;"	d
+WDT_CLK_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1174;"	d
+WDT_CLK_EN_I_MSK	include/ssv6200_aux.h	222;"	d
+WDT_CLK_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1172;"	d
+WDT_CLK_EN_MSK	include/ssv6200_aux.h	221;"	d
+WDT_CLK_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1171;"	d
+WDT_CLK_EN_SFT	include/ssv6200_aux.h	223;"	d
+WDT_CLK_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1173;"	d
+WDT_CLK_EN_SZ	include/ssv6200_aux.h	225;"	d
+WDT_CLK_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1175;"	d
+WDT_INIT_HI	include/ssv6200_aux.h	604;"	d
+WDT_INIT_I_MSK	include/ssv6200_aux.h	602;"	d
+WDT_INIT_MSK	include/ssv6200_aux.h	601;"	d
+WDT_INIT_SFT	include/ssv6200_aux.h	603;"	d
+WDT_INIT_SZ	include/ssv6200_aux.h	605;"	d
+WDT_MCU_RESET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1674;"	d
+WDT_MCU_RESET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1672;"	d
+WDT_MCU_RESET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1671;"	d
+WDT_MCU_RESET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1673;"	d
+WDT_MCU_RESET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1675;"	d
+WDT_SW_RST_HI	include/ssv6200_aux.h	54;"	d
+WDT_SW_RST_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1009;"	d
+WDT_SW_RST_I_MSK	include/ssv6200_aux.h	52;"	d
+WDT_SW_RST_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1007;"	d
+WDT_SW_RST_MSK	include/ssv6200_aux.h	51;"	d
+WDT_SW_RST_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1006;"	d
+WDT_SW_RST_SFT	include/ssv6200_aux.h	53;"	d
+WDT_SW_RST_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1008;"	d
+WDT_SW_RST_SZ	include/ssv6200_aux.h	55;"	d
+WDT_SW_RST_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1010;"	d
+WDT_SYS_RESET_HI	smac/hal/ssv6006c/ssv6006C_aux.h	1679;"	d
+WDT_SYS_RESET_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1677;"	d
+WDT_SYS_RESET_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	1676;"	d
+WDT_SYS_RESET_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	1678;"	d
+WDT_SYS_RESET_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	1680;"	d
+WEP_KEY_LEN	smac/sec.h	27;"	d
+WID_WAPI_KEY	smac/sec_wpi.c	30;"	d	file:
+WIFI_HOST_WAKE	platforms/a33-generic-wlan.c	64;"	d	file:
+WIFI_HOST_WAKE	platforms/atm7039-action-generic-wlan.c	75;"	d	file:
+WIFI_HOST_WAKE	platforms/h3-generic-wlan.c	55;"	d	file:
+WIFI_HOST_WAKE	platforms/h8-generic-wlan.c	55;"	d	file:
+WIFI_HOST_WAKE	platforms/t10-generic-wlan.c	54;"	d	file:
+WIFI_HOST_WAKE	platforms/x1000-generic-wlan.c	54;"	d	file:
+WIFI_RX_SW_O_C_HI	include/ssv6200_aux.h	954;"	d
+WIFI_RX_SW_O_C_I_MSK	include/ssv6200_aux.h	952;"	d
+WIFI_RX_SW_O_C_MSK	include/ssv6200_aux.h	951;"	d
+WIFI_RX_SW_O_C_SFT	include/ssv6200_aux.h	953;"	d
+WIFI_RX_SW_O_C_SZ	include/ssv6200_aux.h	955;"	d
+WIFI_RX_SW_O_OE_HI	include/ssv6200_aux.h	929;"	d
+WIFI_RX_SW_O_OE_I_MSK	include/ssv6200_aux.h	927;"	d
+WIFI_RX_SW_O_OE_MSK	include/ssv6200_aux.h	926;"	d
+WIFI_RX_SW_O_OE_SFT	include/ssv6200_aux.h	928;"	d
+WIFI_RX_SW_O_OE_SZ	include/ssv6200_aux.h	930;"	d
+WIFI_RX_SW_O_PE_HI	include/ssv6200_aux.h	934;"	d
+WIFI_RX_SW_O_PE_I_MSK	include/ssv6200_aux.h	932;"	d
+WIFI_RX_SW_O_PE_MSK	include/ssv6200_aux.h	931;"	d
+WIFI_RX_SW_O_PE_SFT	include/ssv6200_aux.h	933;"	d
+WIFI_RX_SW_O_PE_SZ	include/ssv6200_aux.h	935;"	d
+WIFI_RX_SW_POL_HI	include/ssv6200_aux.h	9274;"	d
+WIFI_RX_SW_POL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9064;"	d
+WIFI_RX_SW_POL_I_MSK	include/ssv6200_aux.h	9272;"	d
+WIFI_RX_SW_POL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9062;"	d
+WIFI_RX_SW_POL_MSK	include/ssv6200_aux.h	9271;"	d
+WIFI_RX_SW_POL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9061;"	d
+WIFI_RX_SW_POL_SFT	include/ssv6200_aux.h	9273;"	d
+WIFI_RX_SW_POL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9063;"	d
+WIFI_RX_SW_POL_SZ	include/ssv6200_aux.h	9275;"	d
+WIFI_RX_SW_POL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9065;"	d
+WIFI_TX_SW_O_C_HI	include/ssv6200_aux.h	924;"	d
+WIFI_TX_SW_O_C_I_MSK	include/ssv6200_aux.h	922;"	d
+WIFI_TX_SW_O_C_MSK	include/ssv6200_aux.h	921;"	d
+WIFI_TX_SW_O_C_SFT	include/ssv6200_aux.h	923;"	d
+WIFI_TX_SW_O_C_SZ	include/ssv6200_aux.h	925;"	d
+WIFI_TX_SW_O_OE_HI	include/ssv6200_aux.h	894;"	d
+WIFI_TX_SW_O_OE_I_MSK	include/ssv6200_aux.h	892;"	d
+WIFI_TX_SW_O_OE_MSK	include/ssv6200_aux.h	891;"	d
+WIFI_TX_SW_O_OE_SFT	include/ssv6200_aux.h	893;"	d
+WIFI_TX_SW_O_OE_SZ	include/ssv6200_aux.h	895;"	d
+WIFI_TX_SW_O_PE_HI	include/ssv6200_aux.h	899;"	d
+WIFI_TX_SW_O_PE_I_MSK	include/ssv6200_aux.h	897;"	d
+WIFI_TX_SW_O_PE_MSK	include/ssv6200_aux.h	896;"	d
+WIFI_TX_SW_O_PE_SFT	include/ssv6200_aux.h	898;"	d
+WIFI_TX_SW_O_PE_SZ	include/ssv6200_aux.h	900;"	d
+WIFI_TX_SW_POL_HI	include/ssv6200_aux.h	9269;"	d
+WIFI_TX_SW_POL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9059;"	d
+WIFI_TX_SW_POL_I_MSK	include/ssv6200_aux.h	9267;"	d
+WIFI_TX_SW_POL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9057;"	d
+WIFI_TX_SW_POL_MSK	include/ssv6200_aux.h	9266;"	d
+WIFI_TX_SW_POL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9056;"	d
+WIFI_TX_SW_POL_SFT	include/ssv6200_aux.h	9268;"	d
+WIFI_TX_SW_POL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9058;"	d
+WIFI_TX_SW_POL_SZ	include/ssv6200_aux.h	9270;"	d
+WIFI_TX_SW_POL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9060;"	d
+WIRE_MODE_HI	include/ssv6200_aux.h	9224;"	d
+WIRE_MODE_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9014;"	d
+WIRE_MODE_I_MSK	include/ssv6200_aux.h	9222;"	d
+WIRE_MODE_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9012;"	d
+WIRE_MODE_MSK	include/ssv6200_aux.h	9221;"	d
+WIRE_MODE_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9011;"	d
+WIRE_MODE_SFT	include/ssv6200_aux.h	9223;"	d
+WIRE_MODE_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9013;"	d
+WIRE_MODE_SZ	include/ssv6200_aux.h	9225;"	d
+WIRE_MODE_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9015;"	d
+WLAN_ACT_POL_HI	include/ssv6200_aux.h	9254;"	d
+WLAN_ACT_POL_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9044;"	d
+WLAN_ACT_POL_I_MSK	include/ssv6200_aux.h	9252;"	d
+WLAN_ACT_POL_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9042;"	d
+WLAN_ACT_POL_MSK	include/ssv6200_aux.h	9251;"	d
+WLAN_ACT_POL_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9041;"	d
+WLAN_ACT_POL_SFT	include/ssv6200_aux.h	9253;"	d
+WLAN_ACT_POL_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9043;"	d
+WLAN_ACT_POL_SZ	include/ssv6200_aux.h	9255;"	d
+WLAN_ACT_POL_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9045;"	d
+WLAN_CIPHER_SUITE_SMS4	smac/dev.c	54;"	d	file:
+WLAN_CIPHER_SUITE_SMS4	smac/init.c	96;"	d	file:
+WLAN_RC_PHY_CCK	smac/ssv_rc_common.h	/^    WLAN_RC_PHY_CCK,$/;"	e	enum:ssv6xxx_rc_phy_type
+WLAN_RC_PHY_HT_20_SS_GF	smac/ssv_rc_common.h	/^    WLAN_RC_PHY_HT_20_SS_GF,$/;"	e	enum:ssv6xxx_rc_phy_type
+WLAN_RC_PHY_HT_20_SS_LGI	smac/ssv_rc_common.h	/^    WLAN_RC_PHY_HT_20_SS_LGI,$/;"	e	enum:ssv6xxx_rc_phy_type
+WLAN_RC_PHY_HT_20_SS_SGI	smac/ssv_rc_common.h	/^    WLAN_RC_PHY_HT_20_SS_SGI,$/;"	e	enum:ssv6xxx_rc_phy_type
+WLAN_RC_PHY_OFDM	smac/ssv_rc_common.h	/^    WLAN_RC_PHY_OFDM,$/;"	e	enum:ssv6xxx_rc_phy_type
+WLAN_REMAIN_TIME_HI	include/ssv6200_aux.h	9299;"	d
+WLAN_REMAIN_TIME_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9089;"	d
+WLAN_REMAIN_TIME_I_MSK	include/ssv6200_aux.h	9297;"	d
+WLAN_REMAIN_TIME_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9087;"	d
+WLAN_REMAIN_TIME_MSK	include/ssv6200_aux.h	9296;"	d
+WLAN_REMAIN_TIME_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9086;"	d
+WLAN_REMAIN_TIME_SFT	include/ssv6200_aux.h	9298;"	d
+WLAN_REMAIN_TIME_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9088;"	d
+WLAN_REMAIN_TIME_SZ	include/ssv6200_aux.h	9300;"	d
+WLAN_REMAIN_TIME_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9090;"	d
+WL_RX_PRI_HI	include/ssv6200_aux.h	9229;"	d
+WL_RX_PRI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9019;"	d
+WL_RX_PRI_I_MSK	include/ssv6200_aux.h	9227;"	d
+WL_RX_PRI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9017;"	d
+WL_RX_PRI_MSK	include/ssv6200_aux.h	9226;"	d
+WL_RX_PRI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9016;"	d
+WL_RX_PRI_SFT	include/ssv6200_aux.h	9228;"	d
+WL_RX_PRI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9018;"	d
+WL_RX_PRI_SZ	include/ssv6200_aux.h	9230;"	d
+WL_RX_PRI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9020;"	d
+WL_TX_PRI_HI	include/ssv6200_aux.h	9234;"	d
+WL_TX_PRI_HI	smac/hal/ssv6006c/ssv6006C_aux.h	9024;"	d
+WL_TX_PRI_I_MSK	include/ssv6200_aux.h	9232;"	d
+WL_TX_PRI_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9022;"	d
+WL_TX_PRI_MSK	include/ssv6200_aux.h	9231;"	d
+WL_TX_PRI_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	9021;"	d
+WL_TX_PRI_SFT	include/ssv6200_aux.h	9233;"	d
+WL_TX_PRI_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	9023;"	d
+WL_TX_PRI_SZ	include/ssv6200_aux.h	9235;"	d
+WL_TX_PRI_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	9025;"	d
+WMM_AC_BE	smac/dev.h	183;"	d
+WMM_AC_BK	smac/dev.h	184;"	d
+WMM_AC_VI	smac/dev.h	182;"	d
+WMM_AC_VO	smac/dev.h	181;"	d
+WMM_NUM_AC	smac/dev.h	185;"	d
+WMM_TID_NUM	smac/dev.h	186;"	d
+WORD_LEN	smac/wapi_sms4.c	26;"	d	file:
+WORD_LEN_HI	include/ssv6200_aux.h	4329;"	d
+WORD_LEN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	3434;"	d
+WORD_LEN_I_MSK	include/ssv6200_aux.h	4327;"	d
+WORD_LEN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3432;"	d
+WORD_LEN_MSK	include/ssv6200_aux.h	4326;"	d
+WORD_LEN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	3431;"	d
+WORD_LEN_SFT	include/ssv6200_aux.h	4328;"	d
+WORD_LEN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	3433;"	d
+WORD_LEN_SZ	include/ssv6200_aux.h	4330;"	d
+WORD_LEN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	3435;"	d
+WPA_GET_BE32	smac/p2p.c	/^static inline u32 WPA_GET_BE32(const u8 *a)$/;"	f	file:	signature:(const u8 *a)
+WPA_GET_LE16	smac/p2p.c	/^static inline u16 WPA_GET_LE16(const u8 *a)$/;"	f	file:	signature:(const u8 *a)
+WPA_GET_LE32	smac/p2p.c	/^static inline u32 WPA_GET_LE32(const u8 *a)$/;"	f	file:	signature:(const u8 *a)
+WRAP_EN_HI	smac/hal/ssv6006c/ssv6006C_aux.h	4064;"	d
+WRAP_EN_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4062;"	d
+WRAP_EN_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	4061;"	d
+WRAP_EN_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	4063;"	d
+WRAP_EN_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	4065;"	d
+WRITE_ADDRESS_HI	include/ssv6200_aux.h	3369;"	d
+WRITE_ADDRESS_I_MSK	include/ssv6200_aux.h	3367;"	d
+WRITE_ADDRESS_MSK	include/ssv6200_aux.h	3366;"	d
+WRITE_ADDRESS_SFT	include/ssv6200_aux.h	3368;"	d
+WRITE_ADDRESS_SZ	include/ssv6200_aux.h	3370;"	d
+WRITE_DATA_HI	include/ssv6200_aux.h	3364;"	d
+WRITE_DATA_I_MSK	include/ssv6200_aux.h	3362;"	d
+WRITE_DATA_MSK	include/ssv6200_aux.h	3361;"	d
+WRITE_DATA_SFT	include/ssv6200_aux.h	3363;"	d
+WRITE_DATA_SZ	include/ssv6200_aux.h	3365;"	d
+WR_ADDR_HI	include/ssv6200_aux.h	6419;"	d
+WR_ADDR_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5664;"	d
+WR_ADDR_I_MSK	include/ssv6200_aux.h	6417;"	d
+WR_ADDR_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5662;"	d
+WR_ADDR_MSK	include/ssv6200_aux.h	6416;"	d
+WR_ADDR_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5661;"	d
+WR_ADDR_SFT	include/ssv6200_aux.h	6418;"	d
+WR_ADDR_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5663;"	d
+WR_ADDR_SZ	include/ssv6200_aux.h	6420;"	d
+WR_ADDR_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5665;"	d
+WR_ID_HI	include/ssv6200_aux.h	6424;"	d
+WR_ID_HI	smac/hal/ssv6006c/ssv6006C_aux.h	5669;"	d
+WR_ID_I_MSK	include/ssv6200_aux.h	6422;"	d
+WR_ID_I_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5667;"	d
+WR_ID_MSK	include/ssv6200_aux.h	6421;"	d
+WR_ID_MSK	smac/hal/ssv6006c/ssv6006C_aux.h	5666;"	d
+WR_ID_SFT	include/ssv6200_aux.h	6423;"	d
+WR_ID_SFT	smac/hal/ssv6006c/ssv6006C_aux.h	5668;"	d
+WR_ID_SZ	include/ssv6200_aux.h	6425;"	d
+WR_ID_SZ	smac/hal/ssv6006c/ssv6006C_aux.h	5670;"	d
+WSID_EXT_BANK_SIZE	smac/hal/ssv6006c/ssv6006C_reg.h	129;"	d
+WSID_EXT_BASE	smac/hal/ssv6006c/ssv6006C_reg.h	68;"	d
+WapiCryptoSms4	smac/wapi_sms4.c	/^void WapiCryptoSms4(u8 *iv, u8 *key, u8 *input, u32 length, u8 *output)$/;"	f	signature:(u8 *iv, u8 *key, u8 *input, u32 length, u8 *output)
+WapiCryptoSms4	smac/wapi_sms4.h	/^void WapiCryptoSms4(u8 *iv, u8 *key, u8 *input, u16 length, u8 *output);$/;"	p	signature:(u8 *iv, u8 *key, u8 *input, u16 length, u8 *output)
+WapiCryptoSms4Mic	smac/wapi_sms4.c	/^void WapiCryptoSms4Mic(u8 *iv, u8 *key, u8 *header, u32 headerLength,$/;"	f	signature:(u8 *iv, u8 *key, u8 *header, u32 headerLength, const u8 *input, u32 dataLength, u8 *mic)
+WapiCryptoSms4Mic	smac/wapi_sms4.h	/^void WapiCryptoSms4Mic(u8 *iv, u8 *Key, u8 *header, u16 headerLength,$/;"	p	signature:(u8 *iv, u8 *Key, u8 *header, u16 headerLength, const u8 *input, u16 dataLength, u8 *output)
+WifiChipType	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	/^} WifiChipType;$/;"	t	typeref:enum:__anon40
+XLNA_EN_O_C_HI	include/ssv6200_aux.h	889;"	d
+XLNA_EN_O_C_I_MSK	include/ssv6200_aux.h	887;"	d
+XLNA_EN_O_C_MSK	include/ssv6200_aux.h	886;"	d
+XLNA_EN_O_C_SFT	include/ssv6200_aux.h	888;"	d
+XLNA_EN_O_C_SZ	include/ssv6200_aux.h	890;"	d
+XLNA_EN_O_OE_HI	include/ssv6200_aux.h	859;"	d
+XLNA_EN_O_OE_I_MSK	include/ssv6200_aux.h	857;"	d
+XLNA_EN_O_OE_MSK	include/ssv6200_aux.h	856;"	d
+XLNA_EN_O_OE_SFT	include/ssv6200_aux.h	858;"	d
+XLNA_EN_O_OE_SZ	include/ssv6200_aux.h	860;"	d
+XLNA_EN_O_PE_HI	include/ssv6200_aux.h	864;"	d
+XLNA_EN_O_PE_I_MSK	include/ssv6200_aux.h	862;"	d
+XLNA_EN_O_PE_MSK	include/ssv6200_aux.h	861;"	d
+XLNA_EN_O_PE_SFT	include/ssv6200_aux.h	863;"	d
+XLNA_EN_O_PE_SZ	include/ssv6200_aux.h	865;"	d
+XOR_MACRO	smac/wapi_sms4.c	93;"	d	file:
+XPA_EN_O_C_HI	include/ssv6200_aux.h	1024;"	d
+XPA_EN_O_C_I_MSK	include/ssv6200_aux.h	1022;"	d
+XPA_EN_O_C_MSK	include/ssv6200_aux.h	1021;"	d
+XPA_EN_O_C_SFT	include/ssv6200_aux.h	1023;"	d
+XPA_EN_O_C_SZ	include/ssv6200_aux.h	1025;"	d
+XPA_EN_O_OE_HI	include/ssv6200_aux.h	994;"	d
+XPA_EN_O_OE_I_MSK	include/ssv6200_aux.h	992;"	d
+XPA_EN_O_OE_MSK	include/ssv6200_aux.h	991;"	d
+XPA_EN_O_OE_SFT	include/ssv6200_aux.h	993;"	d
+XPA_EN_O_OE_SZ	include/ssv6200_aux.h	995;"	d
+XPA_EN_O_PE_HI	include/ssv6200_aux.h	999;"	d
+XPA_EN_O_PE_I_MSK	include/ssv6200_aux.h	997;"	d
+XPA_EN_O_PE_MSK	include/ssv6200_aux.h	996;"	d
+XPA_EN_O_PE_SFT	include/ssv6200_aux.h	998;"	d
+XPA_EN_O_PE_SZ	include/ssv6200_aux.h	1000;"	d
+XTAL12M	smac/hal/ssv6006c/turismo_common.h	/^    XTAL12M,$/;"	e	enum:__anon2
+XTAL16M	smac/hal/ssv6006c/turismo_common.h	/^    XTAL16M = 0,$/;"	e	enum:__anon2
+XTAL19P2M	smac/hal/ssv6006c/turismo_common.h	/^    XTAL19P2M,$/;"	e	enum:__anon2
+XTAL20M	smac/hal/ssv6006c/turismo_common.h	/^    XTAL20M,$/;"	e	enum:__anon2
+XTAL24M	smac/hal/ssv6006c/turismo_common.h	/^    XTAL24M,$/;"	e	enum:__anon2
+XTAL25M	smac/hal/ssv6006c/turismo_common.h	/^    XTAL25M,$/;"	e	enum:__anon2
+XTAL26M	smac/hal/ssv6006c/turismo_common.h	/^    XTAL26M,$/;"	e	enum:__anon2
+XTAL32M	smac/hal/ssv6006c/turismo_common.h	/^    XTAL32M,$/;"	e	enum:__anon2
+XTAL38P4M	smac/hal/ssv6006c/turismo_common.h	/^    XTAL38P4M,$/;"	e	enum:__anon2
+XTAL40M	smac/hal/ssv6006c/turismo_common.h	/^    XTAL40M,$/;"	e	enum:__anon2
+XTAL52M	smac/hal/ssv6006c/turismo_common.h	/^    XTAL52M,$/;"	e	enum:__anon2
+XTALMAX	smac/hal/ssv6006c/turismo_common.h	/^    XTALMAX,$/;"	e	enum:__anon2
+_AMPDU_H_	smac/ampdu.h	17;"	d
+_AP_H_	smac/ap.h	17;"	d
+_Bool	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	27;"	d
+_DEV_H_	smac/dev.h	17;"	d
+_DEV_TBL_H_	smac/dev_tbl.h	17;"	d
+_DRV_COMM_H_	smac/drv_comm.h	17;"	d
+_GetTickCount	smartlink/qqlink-lib-mipsel/case/ipcamera/audiovideo.c	/^unsigned long _GetTickCount() {$/;"	f
+_GetTickCount	smartlink/qqlink-lib-mipsel/demo_video.c	/^unsigned long _GetTickCount() {$/;"	f
+_HAL_H_	include/hal.h	17;"	d
+_HCTRL_H_	hci/hctrl.h	17;"	d
+_INIT_H_	smac/init.h	17;"	d
+_INIT_TURISMOC_SYS	smac/hal/ssv6006c/turismo_common.h	2891;"	d
+_LIB_H_	smac/lib.h	17;"	d
+_LINUX_2_6_35_H_	smac/linux_2_6_35.h	17;"	d
+_LINUX_3_0_0_H_	smac/linux_3_0_0.h	17;"	d
+_LINUX_80211_H_	include/linux_80211.h	17;"	d
+_P2P_H_	smac/p2p.h	17;"	d
+_RESTORE_CAL	smac/hal/ssv6006c/turismo_common.h	2828;"	d
+_SDIO_DEF_H_	hwif/sdio/sdio_def.h	17;"	d
+_SDIO_H_	hwif/sdio/sdio.h	17;"	d
+_SSV6006_MAC_H_	smac/hal/ssv6006c/ssv6006_mac.h	17;"	d
+_SSV6006_PRIV_H_	smac/hal/ssv6006c/ssv6006_priv.h	17;"	d
+_SSV6006_PRIV_MAC_H_	smac/hal/ssv6006c/ssv6006_priv_normal.h	17;"	d
+_SSV6006_PRIV_RF_H_	smac/hal/ssv6006c/ssv6006_priv_safe.h	17;"	d
+_SSV6200_COMMON_H_	include/ssv6200_common.h	17;"	d
+_SSV6200_H_	include/ssv6200.h	17;"	d
+_SSV6XXX_H_	include/ssv6xxx_cfg.h	17;"	d
+_SSV6XXX_NETLINK_CORE_H_	umac/ssv6xxx_netlink_core.h	17;"	d
+_SSVSMART_CONFIG_H	smac/kssvsmart.h	17;"	d
+_SSV_CFG_H_	include/ssv_cfg.h	17;"	d
+_SSV_CMD_H_	ssvdevice/ssv_cmd.h	17;"	d
+_SSV_DATA_STRUCT_H_	include/ssv_data_struct.h	17;"	d
+_SSV_EFUSE_H_	smac/efuse.h	17;"	d
+_SSV_FRIMWARE_VERSION_H_	include/ssv_firmware_version.h	17;"	d
+_SSV_HCI_H_	hci/ssv_hci.h	17;"	d
+_SSV_HUW_H_	hci_wrapper/ssv_huw.h	17;"	d
+_SSV_PM_H_	smac/ssv_pm.h	17;"	d
+_SSV_RC_COM_H_	smac/ssv_rc_common.h	17;"	d
+_SSV_RC_HT_H_	smac/ssv_ht_rc.h	17;"	d
+_SSV_RC_H_	smac/ssv_rc.h	17;"	d
+_SSV_RC_MINSTREL_HT_H_	smac/ssv_rc_minstrel_ht.h	17;"	d
+_SSV_RC_MINSTREL_H_	smac/ssv_rc_minstrel.h	17;"	d
+_SSV_REG_ACC_H_	smac/ssv_reg_acc.h	17;"	d
+_SSV_SKB_H_	smac/ssv_skb.h	17;"	d
+_SSV_SMARTLINK_H	smartlink/ssv_smartlink.h	17;"	d
+_SSV_VERSION_H_	include/ssv_version.h	2;"	d
+_S_	smac/sec_tkip.c	/^static inline u16 _S_(u16 v)$/;"	f	file:	signature:(u16 v)
+_USB_DEF_H_	hwif/usb/usb.h	17;"	d
+_VERIFY_DPD	smac/hal/ssv6006c/turismo_common.h	3378;"	d
+_VERIFY_DPD	smac/hal/ssv6006c/turismo_common.h	3380;"	d
+__ARM_ARCH__	crypto/aes-armv4.S	/^#define __ARM_ARCH__ __LINUX_ARM_ARCH__$/;"	d
+__ARM_ARCH__	crypto/sha1-armv4-large.S	/^#define __ARM_ARCH__ __LINUX_ARM_ARCH__$/;"	d
+__CHECK_ENDIAN__	include/ssv_mod_conf.h	4;"	d
+__HWIF_H__	hwif/hwif.h	17;"	d
+__IPCAMERA_H__	smartlink/qqlink-lib-mipsel/include/TXIPCAM.h	17;"	d
+__KSMARTLINK_ATTR_MAX	smac/ksmartlink.c	/^    __KSMARTLINK_ATTR_MAX,$/;"	e	enum:__anon9	file:
+__KSMARTLINK_ATTR_MAX	smartlink/ssv_smartlink.c	/^    __KSMARTLINK_ATTR_MAX,$/;"	e	enum:__anon36	file:
+__KSMARTLINK_CMD_MAX	smac/ksmartlink.c	/^    __KSMARTLINK_CMD_MAX,$/;"	e	enum:__anon10	file:
+__KSMARTLINK_CMD_MAX	smartlink/ssv_smartlink.c	/^    __KSMARTLINK_CMD_MAX,$/;"	e	enum:__anon37	file:
+__OTA_H__	smartlink/qqlink-lib-mipsel/include/TXOTA.h	17;"	d
+__PBuf_Type_E	include/ssv6xxx_common.h	/^typedef enum __PBuf_Type_E {$/;"	g
+__SSV6006_COMMON_H__	smac/hal/ssv6006c/ssv6006_common.h	17;"	d
+__SSV6006_H__	smac/hal/ssv6006c/ssv6006_cfg.h	17;"	d
+__SSV6XXX_COMMON_H__	include/ssv6xxx_common.h	17;"	d
+__SSV6XXX_DBGFS_H__	smac/ssv6xxx_debugfs.h	17;"	d
+__SSV_CLI_H__	smac/ssv_cli.h	17;"	d
+__SSV_CONF_PARSER_H__	include/ssv_conf_parser.h	17;"	d
+__SSV_MOD_CONF_H__	include/ssv_mod_conf.h	2;"	d
+__SSV_WIRELESS_ATTR_MAX	umac/ssv6xxx_netlink_core.h	/^ __SSV_WIRELESS_ATTR_MAX,$/;"	e	enum:__anon53
+__SSV_WIRELESS_CMD_MAX	umac/ssv6xxx_netlink_core.h	/^ __SSV_WIRELESS_CMD_MAX,$/;"	e	enum:__anon54
+__TX_AUDIO_VIDEO_H__	smartlink/qqlink-lib-mipsel/include/TXAudioVideo.h	17;"	d
+__TX_DATA_POINT_H__	smartlink/qqlink-lib-mipsel/include/TXDataPoint.h	17;"	d
+__TX_DECODE_ENGINE__H__	smartlink/qqlink-lib-mipsel/include/TXVoiceLink.h	17;"	d
+__TX_DEVICE_SDK_H__	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	17;"	d
+__TX_FILE_TRANSFER_H__	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	17;"	d
+__TX_MSG_H__	smartlink/qqlink-lib-mipsel/include/TXMsg.h	17;"	d
+__TX_OLD_INTERFACE_H__	smartlink/qqlink-lib-mipsel/include/TXOldInf.h	17;"	d
+__TX_SDK_COMMON_DEF_H__	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	17;"	d
+__TX_TV_BARRAGE_H__	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	17;"	d
+__TX_TV_SDK_H__	smartlink/qqlink-lib-mipsel/include/TXTVSDK.h	17;"	d
+__TX_WIFI_SYNC_H__	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	17;"	d
+__anon17::memcmp	smartlink/airkiss-lib/mipsel/airkiss.h	/^ airkiss_memcmp_fn memcmp;$/;"	m	struct:__anon17	access:public
+__anon17::memcpy	smartlink/airkiss-lib/mipsel/airkiss.h	/^ airkiss_memcpy_fn memcpy;$/;"	m	struct:__anon17	access:public
+__anon17::memset	smartlink/airkiss-lib/mipsel/airkiss.h	/^ airkiss_memset_fn memset;$/;"	m	struct:__anon17	access:public
+__anon17::printf	smartlink/airkiss-lib/mipsel/airkiss.h	/^ airkiss_printf_fn printf;$/;"	m	struct:__anon17	access:public
+__anon18::dummy	smartlink/airkiss-lib/mipsel/airkiss.h	/^ int dummy[32];$/;"	m	struct:__anon18	access:public
+__anon18::dummyap	smartlink/airkiss-lib/mipsel/airkiss.h	/^ int dummyap[26];$/;"	m	struct:__anon18	access:public
+__anon19::pwd	smartlink/airkiss-lib/mipsel/airkiss.h	/^ char* pwd;$/;"	m	struct:__anon19	access:public
+__anon19::pwd_length	smartlink/airkiss-lib/mipsel/airkiss.h	/^ unsigned char pwd_length;$/;"	m	struct:__anon19	access:public
+__anon19::random	smartlink/airkiss-lib/mipsel/airkiss.h	/^ unsigned char random;$/;"	m	struct:__anon19	access:public
+__anon19::reserved	smartlink/airkiss-lib/mipsel/airkiss.h	/^ unsigned char reserved;$/;"	m	struct:__anon19	access:public
+__anon19::ssid	smartlink/airkiss-lib/mipsel/airkiss.h	/^ char* ssid;$/;"	m	struct:__anon19	access:public
+__anon19::ssid_length	smartlink/airkiss-lib/mipsel/airkiss.h	/^ unsigned char ssid_length;$/;"	m	struct:__anon19	access:public
+__anon23::memcmp	smartlink/airkiss-lib/airkiss.h	/^ airkiss_memcmp_fn memcmp;$/;"	m	struct:__anon23	access:public
+__anon23::memcpy	smartlink/airkiss-lib/airkiss.h	/^ airkiss_memcpy_fn memcpy;$/;"	m	struct:__anon23	access:public
+__anon23::memset	smartlink/airkiss-lib/airkiss.h	/^ airkiss_memset_fn memset;$/;"	m	struct:__anon23	access:public
+__anon23::printf	smartlink/airkiss-lib/airkiss.h	/^ airkiss_printf_fn printf;$/;"	m	struct:__anon23	access:public
+__anon24::dummy	smartlink/airkiss-lib/airkiss.h	/^ int dummy[32];$/;"	m	struct:__anon24	access:public
+__anon24::dummyap	smartlink/airkiss-lib/airkiss.h	/^ int dummyap[26];$/;"	m	struct:__anon24	access:public
+__anon25::pwd	smartlink/airkiss-lib/airkiss.h	/^ char* pwd;$/;"	m	struct:__anon25	access:public
+__anon25::pwd_length	smartlink/airkiss-lib/airkiss.h	/^ unsigned char pwd_length;$/;"	m	struct:__anon25	access:public
+__anon25::random	smartlink/airkiss-lib/airkiss.h	/^ unsigned char random;$/;"	m	struct:__anon25	access:public
+__anon25::reserved	smartlink/airkiss-lib/airkiss.h	/^ unsigned char reserved;$/;"	m	struct:__anon25	access:public
+__anon25::ssid	smartlink/airkiss-lib/airkiss.h	/^ char* ssid;$/;"	m	struct:__anon25	access:public
+__anon25::ssid_length	smartlink/airkiss-lib/airkiss.h	/^ unsigned char ssid_length;$/;"	m	struct:__anon25	access:public
+__anon29::memcmp	smartlink/airkiss-lib/x64/airkiss.h	/^ airkiss_memcmp_fn memcmp;$/;"	m	struct:__anon29	access:public
+__anon29::memcpy	smartlink/airkiss-lib/x64/airkiss.h	/^ airkiss_memcpy_fn memcpy;$/;"	m	struct:__anon29	access:public
+__anon29::memset	smartlink/airkiss-lib/x64/airkiss.h	/^ airkiss_memset_fn memset;$/;"	m	struct:__anon29	access:public
+__anon29::printf	smartlink/airkiss-lib/x64/airkiss.h	/^ airkiss_printf_fn printf;$/;"	m	struct:__anon29	access:public
+__anon30::dummy	smartlink/airkiss-lib/x64/airkiss.h	/^ int dummy[32];$/;"	m	struct:__anon30	access:public
+__anon30::dummyap	smartlink/airkiss-lib/x64/airkiss.h	/^ int dummyap[26];$/;"	m	struct:__anon30	access:public
+__anon31::pwd	smartlink/airkiss-lib/x64/airkiss.h	/^ char* pwd;$/;"	m	struct:__anon31	access:public
+__anon31::pwd_length	smartlink/airkiss-lib/x64/airkiss.h	/^ unsigned char pwd_length;$/;"	m	struct:__anon31	access:public
+__anon31::random	smartlink/airkiss-lib/x64/airkiss.h	/^ unsigned char random;$/;"	m	struct:__anon31	access:public
+__anon31::reserved	smartlink/airkiss-lib/x64/airkiss.h	/^ unsigned char reserved;$/;"	m	struct:__anon31	access:public
+__anon31::ssid	smartlink/airkiss-lib/x64/airkiss.h	/^ char* ssid;$/;"	m	struct:__anon31	access:public
+__anon31::ssid_length	smartlink/airkiss-lib/x64/airkiss.h	/^ unsigned char ssid_length;$/;"	m	struct:__anon31	access:public
+__anon38::sh_port	smartlink/qqlink-lib-mipsel/include/TXVoiceLink.h	/^    unsigned short sh_port;$/;"	m	struct:__anon38	access:public
+__anon38::sz_ip	smartlink/qqlink-lib-mipsel/include/TXVoiceLink.h	/^    char sz_ip[MAX_IP_LEN];$/;"	m	struct:__anon38	access:public
+__anon38::sz_password	smartlink/qqlink-lib-mipsel/include/TXVoiceLink.h	/^ char sz_password[MAX_PSWD_LEN];$/;"	m	struct:__anon38	access:public
+__anon38::sz_ssid	smartlink/qqlink-lib-mipsel/include/TXVoiceLink.h	/^ char sz_ssid[MAX_SSID_LEN];$/;"	m	struct:__anon38	access:public
+__anon39::sh_port	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	/^    unsigned short sh_port;$/;"	m	struct:__anon39	access:public
+__anon39::sz_ip	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	/^    char sz_ip[QLMAX_IP_LEN];$/;"	m	struct:__anon39	access:public
+__anon39::sz_password	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	/^ char sz_password[QLMAX_PSWD_LEN];$/;"	m	struct:__anon39	access:public
+__anon39::sz_ssid	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	/^ char sz_ssid[QLMAX_SSID_LEN];$/;"	m	struct:__anon39	access:public
+__anon41::rd_key	crypto/aes_glue.c	/^ unsigned int rd_key[4 *(AES_MAXNR + 1)];$/;"	m	struct:__anon41	file:	access:public
+__anon41::rounds	crypto/aes_glue.c	/^ int rounds;$/;"	m	struct:__anon41	file:	access:public
+__devexit	include/ssv_mod_conf.h	83;"	d
+__devinit	include/ssv_mod_conf.h	82;"	d
+__devinitconst	hwif/sdio/sdio.c	/^static const struct sdio_device_id ssv6xxx_sdio_devices[] __devinitconst =$/;"	v	typeref:struct:ssv6xxx_sdio_devices	file:
+__exit	include/ssv_mod_conf.h	85;"	d
+__init	include/ssv_mod_conf.h	84;"	d
+__must_check	include/ssv_mod_conf.h	81;"	d
+__sha1_update	crypto/sha1_glue.c	/^static int __sha1_update(struct SHA1_CTX *sctx, const u8 *data,$/;"	f	file:	signature:(struct SHA1_CTX *sctx, const u8 *data, unsigned int len, unsigned int partial)
+__ssv6xxx_sdio_read_reg	hwif/sdio/sdio.c	/^static int __must_check __ssv6xxx_sdio_read_reg (struct ssv6xxx_sdio_glue *glue, u32 addr,$/;"	f	file:	signature:(struct ssv6xxx_sdio_glue *glue, u32 addr, u32 *buf)
+__ssv6xxx_sdio_safe_read_reg	hwif/sdio/sdio.c	/^static int __must_check __ssv6xxx_sdio_safe_read_reg (struct ssv6xxx_sdio_glue *glue, u32 addr,$/;"	f	file:	signature:(struct ssv6xxx_sdio_glue *glue, u32 addr, u32 *buf)
+__ssv6xxx_sdio_safe_write_reg	hwif/sdio/sdio.c	/^static int __must_check __ssv6xxx_sdio_safe_write_reg (struct ssv6xxx_sdio_glue *glue, u32 addr,$/;"	f	file:	signature:(struct ssv6xxx_sdio_glue *glue, u32 addr, u32 buf)
+__ssv6xxx_sdio_write_reg	hwif/sdio/sdio.c	/^static int __must_check __ssv6xxx_sdio_write_reg (struct ssv6xxx_sdio_glue *glue, u32 addr,$/;"	f	file:	signature:(struct ssv6xxx_sdio_glue *glue, u32 addr, u32 buf)
+__ssv6xxx_usb_read_reg	hwif/usb/usb.c	/^static int __must_check __ssv6xxx_usb_read_reg(struct ssv6xxx_usb_glue *glue, u32 addr,$/;"	f	file:	signature:(struct ssv6xxx_usb_glue *glue, u32 addr, u32 *buf)
+__ssv6xxx_usb_write_reg	hwif/usb/usb.c	/^static int __must_check __ssv6xxx_usb_write_reg(struct ssv6xxx_usb_glue *glue, u32 addr,$/;"	f	file:	signature:(struct ssv6xxx_usb_glue *glue, u32 addr, u32 buf)
+__ssv_procfs	ssvdevice/ssvdevice.c	/^static struct proc_dir_entry *__ssv_procfs;$/;"	v	typeref:struct:proc_dir_entry	file:
+__string2bool	ssvdevice/ssv_cmd.c	/^static int __string2bool(u8 *u8str, void *val, u32 arg)$/;"	f	file:	signature:(u8 *u8str, void *val, u32 arg)
+__string2configuration	ssvdevice/ssv_cmd.c	/^static int __string2configuration(u8 *mac_str, void *val, u32 arg)$/;"	f	file:	signature:(u8 *mac_str, void *val, u32 arg)
+__string2flag32	ssvdevice/ssv_cmd.c	/^static int __string2flag32(u8 *flag_str, void *flag, u32 arg)$/;"	f	file:	signature:(u8 *flag_str, void *flag, u32 arg)
+__string2mac	ssvdevice/ssv_cmd.c	/^static int __string2mac(u8 *mac_str, void *val, u32 arg)$/;"	f	file:	signature:(u8 *mac_str, void *val, u32 arg)
+__string2str	ssvdevice/ssv_cmd.c	/^static int __string2str(u8 *path, void *val, u32 arg)$/;"	f	file:	signature:(u8 *path, void *val, u32 arg)
+__string2u32	ssvdevice/ssv_cmd.c	/^static int __string2u32(u8 *u8str, void *val, u32 arg)$/;"	f	file:	signature:(u8 *u8str, void *val, u32 arg)
+__this_module	hci/ssv6200_hci.mod.c	/^__visible struct module __this_module$/;"	v	typeref:struct:module
+__this_module	hwif/sdio/ssv6200_sdio.mod.c	/^__visible struct module __this_module$/;"	v	typeref:struct:module
+__this_module	hwif/usb/ssv6200_usb.mod.c	/^__visible struct module __this_module$/;"	v	typeref:struct:module
+__this_module	ssvdevice/ssvdevicetype.mod.c	/^__visible struct module __this_module$/;"	v	typeref:struct:module
+__used	hci/ssv6200_hci.mod.c	/^__used$/;"	v	file:
+__used	hci/ssv6200_hci.mod.c	/^__used$/;"	v	typeref:struct:____versions	file:
+__used	hwif/sdio/ssv6200_sdio.mod.c	/^__used$/;"	v	file:
+__used	hwif/sdio/ssv6200_sdio.mod.c	/^__used$/;"	v	typeref:struct:____versions	file:
+__used	hwif/usb/ssv6200_usb.mod.c	/^__used$/;"	v	file:
+__used	hwif/usb/ssv6200_usb.mod.c	/^__used$/;"	v	typeref:struct:____versions	file:
+__used	ssvdevice/ssvdevicetype.mod.c	/^__used$/;"	v	file:
+__used	ssvdevice/ssvdevicetype.mod.c	/^__used$/;"	v	typeref:struct:____versions	file:
+_acquire_new_ampdu_ssn_slot	smac/ampdu.c	/^static int _acquire_new_ampdu_ssn_slot(struct ssv_softc *sc, struct sk_buff *ampdu)$/;"	f	file:	signature:(struct ssv_softc *sc, struct sk_buff *ampdu)
+_acquire_new_ampdu_ssn_slot	smac/ampdu.c	/^static int _acquire_new_ampdu_ssn_slot(struct ssv_softc *sc, struct sk_buff *ampdu);$/;"	p	file:	signature:(struct ssv_softc *sc, struct sk_buff *ampdu)
+_add_ampdu_txinfo	smac/ampdu.c	/^static void _add_ampdu_txinfo (struct ssv_softc *sc, struct sk_buff *ampdu_skb)$/;"	f	file:	signature:(struct ssv_softc *sc, struct sk_buff *ampdu_skb)
+_aggr_ampdu_tx_q	smac/ampdu.c	/^static void _aggr_ampdu_tx_q (struct ieee80211_hw *hw,$/;"	p	file:	signature:(struct ieee80211_hw *hw, struct AMPDU_TID_st *ampdu_tid)
+_aggr_ampdu_tx_q	smac/ampdu.c	/^void _aggr_ampdu_tx_q (struct ieee80211_hw *hw, struct AMPDU_TID_st *ampdu_tid)$/;"	f	signature:(struct ieee80211_hw *hw, struct AMPDU_TID_st *ampdu_tid)
+_aggr_retry_mpdu	smac/ampdu.c	/^static struct sk_buff* _aggr_retry_mpdu (struct ssv_softc *sc,$/;"	p	file:	signature:(struct ssv_softc *sc, struct AMPDU_TID_st *cur_AMPDU_TID, struct sk_buff_head *retry_queue, u32 max_aggr_len)
+_aggr_retry_mpdu	smac/ampdu.c	/^struct sk_buff* _aggr_retry_mpdu (struct ssv_softc *sc,$/;"	f	signature:(struct ssv_softc *sc, struct AMPDU_TID_st *ampdu_tid, struct sk_buff_head *retry_queue, u32 max_aggr_len)
+_alloc_ampdu_skb	smac/ampdu.c	/^static struct sk_buff *_alloc_ampdu_skb (struct ssv_softc *sc,$/;"	p	file:	signature:(struct ssv_softc *sc, struct AMPDU_TID_st *ampdu_tid, u32 len)
+_alloc_ampdu_skb	smac/ampdu.c	/^struct sk_buff *_alloc_ampdu_skb (struct ssv_softc *sc, struct AMPDU_TID_st *ampdu_tid, u32 len)$/;"	f	signature:(struct ssv_softc *sc, struct AMPDU_TID_st *ampdu_tid, u32 len)
+_alloc_sh	smac/init.c	/^static int _alloc_sh (struct ssv_softc *sc)$/;"	f	file:	signature:(struct ssv_softc *sc)
+_armv4_AES_decrypt	crypto/aes-armv4.S	/^_armv4_AES_decrypt:$/;"	l
+_armv4_AES_encrypt	crypto/aes-armv4.S	/^_armv4_AES_encrypt:$/;"	l
+_armv4_AES_set_encrypt_key	crypto/aes-armv4.S	/^_armv4_AES_set_encrypt_key:$/;"	l
+_cal_ampdu_delm_crc	smac/ampdu.c	/^static u8 _cal_ampdu_delm_crc (u8 *pointer)$/;"	f	file:	signature:(u8 *pointer)
+_cal_ampdu_delm_half_crc	smac/ampdu.c	/^static u8 _cal_ampdu_delm_half_crc (u8 value)$/;"	f	file:	signature:(u8 value)
+_check_iqk	smac/hal/ssv6006c/ssv6006_turismoC.c	/^void _check_iqk(struct ssv_hw *sh, struct ssv6006_cal_result *cal, int pa_band)$/;"	f	signature:(struct ssv_hw *sh, struct ssv6006_cal_result *cal, int pa_band)
+_check_padpd	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void _check_padpd(struct ssv_hw *sh, struct ssv6006_padpd *dpd, int pa_band)$/;"	f	file:	signature:(struct ssv_hw *sh, struct ssv6006_padpd *dpd, int pa_band)
+_check_padpd_gain	smac/hal/ssv6006c/ssv6006_turismoC.c	/^void _check_padpd_gain(struct ssv_hw *sh, int pa_band, int init_gain, int *ret)$/;"	f	signature:(struct ssv_hw *sh, int pa_band, int init_gain, int *ret)
+_check_padpd_iqk	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void _check_padpd_iqk(struct ssv_hw *sh, struct ssv6006_padpd *dpd,$/;"	f	file:	signature:(struct ssv_hw *sh, struct ssv6006_padpd *dpd, struct ssv6006_cal_result *cal, int ch)
+_check_sgi	smac/ssv_rc_minstrel_ht.c	/^static void _check_sgi(struct ssv_softc *sc, struct ssv_minstrel_ht_sta *mhs, int ampdu_len, int ampdu_ack_len, int short_gi){$/;"	f	file:	signature:(struct ssv_softc *sc, struct ssv_minstrel_ht_sta *mhs, int ampdu_len, int ampdu_ack_len, int short_gi)
+_check_spur	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void _check_spur(struct ssv_hw *sh, struct ssv6006_padpd *dpd,$/;"	f	file:	signature:(struct ssv_hw *sh, struct ssv6006_padpd *dpd, struct ssv6006_cal_result *cal, int ch, int channel_type)
+_check_timeout	smac/ampdu.c	/^static u32 _check_timeout (struct AMPDU_TID_st *ampdu_tid, u32 *has_drop)$/;"	f	file:	signature:(struct AMPDU_TID_st *ampdu_tid, u32 *has_drop)
+_clean_up_crypto_skb	smac/dev.c	/^void _clean_up_crypto_skb (struct ssv_softc *sc, struct ieee80211_sta *sta)$/;"	f	signature:(struct ssv_softc *sc, struct ieee80211_sta *sta)
+_clear_mpdu_q	smac/ampdu.c	/^static void _clear_mpdu_q (struct ieee80211_hw *hw, struct sk_buff_head *q,$/;"	f	file:	signature:(struct ieee80211_hw *hw, struct sk_buff_head *q, bool aggregated_mpdu)
+_cmd_autosgi	smac/hal/ssv6006c/ssv6006_phy.c	/^static void _cmd_autosgi(struct ssv_hw *sh, int argc, char *argv[]){$/;"	f	file:	signature:(struct ssv_hw *sh, int argc, char *argv[])
+_cmd_rc_setting	smac/hal/ssv6006c/ssv6006_phy.c	/^static void _cmd_rc_setting(struct ssv_hw *sh, int argc, char *argv[]){$/;"	f	file:	signature:(struct ssv_hw *sh, int argc, char *argv[])
+_cmd_rxstats	smac/hal/ssv6006c/ssv6006_phy.c	/^static void _cmd_rxstats(struct ssv_softc *sc){$/;"	f	file:	signature:(struct ssv_softc *sc)
+_cmd_txstats	smac/hal/ssv6006c/ssv6006_phy.c	/^static void _cmd_txstats(struct ssv_softc *sc){$/;"	f	file:	signature:(struct ssv_softc *sc)
+_collect_retry_frames	smac/ampdu.c	/^static int _collect_retry_frames (struct AMPDU_TID_st *ampdu_tid)$/;"	f	file:	signature:(struct AMPDU_TID_st *ampdu_tid)
+_debug_5g_rxdc_cal	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void _debug_5g_rxdc_cal(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+_debug_5g_rxiq_cal	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void _debug_5g_rxiq_cal(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+_debug__2p4g_rxdc_cal	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void _debug__2p4g_rxdc_cal(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+_debug_rxiq_cal	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void _debug_rxiq_cal(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+_do_force_tx	hci/ssv_hci.c	/^static int _do_force_tx (struct ssv6xxx_hci_ctrl *hctl, int *err)$/;"	f	file:	signature:(struct ssv6xxx_hci_ctrl *hctl, int *err)
+_do_rx	hci/ssv_hci.c	/^static int _do_rx (struct ssv6xxx_hci_ctrl *hctl, u32 isr_status)$/;"	f	file:	signature:(struct ssv6xxx_hci_ctrl *hctl, u32 isr_status)
+_do_tx	hci/ssv_hci.c	/^static int _do_tx (struct ssv6xxx_hci_ctrl *hctl, u32 status)$/;"	f	file:	signature:(struct ssv6xxx_hci_ctrl *hctl, u32 status)
+_dpd_set_txscale_get_result	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void _dpd_set_txscale_get_result(struct ssv_hw *sh, int rg_tx_scale, int *am, int *pm)$/;"	f	file:	signature:(struct ssv_hw *sh, int rg_tx_scale, int *am, int *pm)
+_dump_ba_skb	smac/ampdu.c	/^int _dump_ba_skb (struct ssv_softc *sc, char *buf, int buf_size, struct sk_buff *ba_skb)$/;"	f	signature:(struct ssv_softc *sc, char *buf, int buf_size, struct sk_buff *ba_skb)
+_dump_ba_skb	smac/ampdu.c	/^static int _dump_ba_skb (struct ssv_softc *sc, char *buf, int buf_size, struct sk_buff *ba_skb);$/;"	p	file:	signature:(struct ssv_softc *sc, char *buf, int buf_size, struct sk_buff *ba_skb)
+_dump_sta_info	ssvdevice/ssv_cmd.c	/^static void _dump_sta_info (struct ssv_softc *sc,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ssv_vif_info *vif_info, struct ssv_sta_info *sta_info, int sta_idx)
+_fill_txinfo_rates	smac/ssv_ht_rc.c	/^static void _fill_txinfo_rates (struct ssv_rate_ctrl *ssv_rc, struct sk_buff *skb, struct fw_rc_retry_params *ar)$/;"	f	file:	signature:(struct ssv_rate_ctrl *ssv_rc, struct sk_buff *skb, struct fw_rc_retry_params *ar)
+_flush_early_ampdu_q	smac/ampdu.c	/^static u32 _flush_early_ampdu_q (struct ssv_softc *sc,$/;"	p	file:	signature:(struct ssv_softc *sc, struct AMPDU_TID_st *ampdu_tid)
+_flush_early_ampdu_q	smac/ampdu.c	/^u32 _flush_early_ampdu_q (struct ssv_softc *sc, struct AMPDU_TID_st *ampdu_tid)$/;"	f	signature:(struct ssv_softc *sc, struct AMPDU_TID_st *ampdu_tid)
+_flush_mpdu	smac/ampdu.c	/^void _flush_mpdu (struct ssv_softc *sc, struct ieee80211_sta *sta)$/;"	f	signature:(struct ssv_softc *sc, struct ieee80211_sta *sta)
+_flush_release_queue	smac/ampdu.c	/^static void _flush_release_queue (struct ieee80211_hw *hw,$/;"	f	file:	signature:(struct ieee80211_hw *hw, struct sk_buff_head *release_queue)
+_if_set_apmode	smac/dev.c	/^static void _if_set_apmode(struct ieee80211_hw *hw,$/;"	f	file:	signature:(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
+_import_default_cfg	ssvdevice/ssvdevice.c	/^static void _import_default_cfg (char *stacfgpath)$/;"	f	file:	signature:(char *stacfgpath)
+_is_encrypt_needed	smac/dev.c	/^bool _is_encrypt_needed(struct sk_buff *skb)$/;"	f	signature:(struct sk_buff *skb)
+_is_skb_q_empty	smac/ampdu.c	/^bool _is_skb_q_empty (struct ssv_softc *sc, struct sk_buff *skb)$/;"	f	signature:(struct ssv_softc *sc, struct sk_buff *skb)
+_is_skb_q_empty	smac/ampdu.c	/^static bool _is_skb_q_empty (struct ssv_softc *sc, struct sk_buff *skb);$/;"	p	file:	signature:(struct ssv_softc *sc, struct sk_buff *skb)
+_isr_do_rx	hci/ssv_hci.c	/^static int _isr_do_rx (struct ssv6xxx_hci_ctrl *hctl, u32 isr_status)$/;"	f	file:	signature:(struct ssv6xxx_hci_ctrl *hctl, u32 isr_status)
+_post_padpd	smac/hal/ssv6006c/ssv6006_turismoC.c	/^void _post_padpd(struct ssv_hw *sh)$/;"	f	signature:(struct ssv_hw *sh)
+_postprocess_BA	smac/ampdu.c	/^static void _postprocess_BA (struct ssv_softc *sc, struct ssv_sta_info *sta_info, void *param)$/;"	f	file:	signature:(struct ssv_softc *sc, struct ssv_sta_info *sta_info, void *param)
+_pre_padpd	smac/hal/ssv6006c/ssv6006_turismoC.c	/^void _pre_padpd(struct ssv_hw *sh, int pa_band, int init_gain)$/;"	f	signature:(struct ssv_hw *sh, int pa_band, int init_gain)
+_prepare_key	smac/dev.c	/^static enum SSV_CIPHER_E _prepare_key (struct ieee80211_key_conf *key, struct ssv_softc *sc)$/;"	f	file:	signature:(struct ieee80211_key_conf *key, struct ssv_softc *sc)
+_print_BA	smac/ampdu.c	/^static void _print_BA(struct AMPDU_TID_st *ampdu_tid)$/;"	f	file:	signature:(struct AMPDU_TID_st *ampdu_tid)
+_print_BA	smac/ampdu.c	/^static void _print_BA(struct AMPDU_TID_st *ampdu_tid);$/;"	p	file:	signature:(struct AMPDU_TID_st *ampdu_tid)
+_proc_data_rx_skb	smac/dev.c	/^static void _proc_data_rx_skb (struct ssv_softc *sc, struct sk_buff *rx_skb)$/;"	f	file:	signature:(struct ssv_softc *sc, struct sk_buff *rx_skb)
+_proc_rx_skb	smac/dev.c	/^static struct sk_buff *_proc_rx_skb (struct ssv_softc *sc, struct sk_buff *rx_skb)$/;"	f	file:	signature:(struct ssv_softc *sc, struct sk_buff *rx_skb)
+_process_host_event	smac/dev.c	/^static bool _process_host_event(struct ssv_softc *sc, struct sk_buff *skb, bool *has_ba_processed)$/;"	f	file:	signature:(struct ssv_softc *sc, struct sk_buff *skb, bool *has_ba_processed)
+_process_rx_q	smac/dev.c	/^static void _process_rx_q (struct ssv_softc *sc, struct sk_buff_head *rx_q, spinlock_t *rx_q_lock);$/;"	p	file:	signature:(struct ssv_softc *sc, struct sk_buff_head *rx_q, spinlock_t *rx_q_lock)
+_process_rx_q	smac/dev.c	/^void _process_rx_q (struct ssv_softc *sc, struct sk_buff_head *rx_q, spinlock_t *rx_q_lock)$/;"	f	signature:(struct ssv_softc *sc, struct sk_buff_head *rx_q, spinlock_t *rx_q_lock)
+_process_rx_umac	smac/dev.c	/^int _process_rx_umac(struct ssv6xxx_umac_ops *umac, struct sk_buff *skb)$/;"	f	signature:(struct ssv6xxx_umac_ops *umac, struct sk_buff *skb)
+_process_tx_done	smac/dev.c	/^static u32 _process_tx_done (struct ssv_softc *sc);$/;"	p	file:	signature:(struct ssv_softc *sc)
+_process_tx_done	smac/dev.c	/^u32 _process_tx_done (struct ssv_softc *sc)$/;"	f	signature:(struct ssv_softc *sc)
+_put_mpdu_to_ampdu	smac/ampdu.c	/^static void _put_mpdu_to_ampdu (struct ssv_softc *sc, struct sk_buff *ampdu,$/;"	p	file:	signature:(struct ssv_softc *sc, struct sk_buff *ampdu, struct sk_buff *mpdu)
+_put_mpdu_to_ampdu	smac/ampdu.c	/^void _put_mpdu_to_ampdu (struct ssv_softc *sc, struct sk_buff *ampdu, struct sk_buff *mpdu)$/;"	f	signature:(struct ssv_softc *sc, struct sk_buff *ampdu, struct sk_buff *mpdu)
+_queue_early_ampdu	smac/ampdu.c	/^static void _queue_early_ampdu (struct ssv_softc *sc,$/;"	p	file:	signature:(struct ssv_softc *sc, struct AMPDU_TID_st *ampdu_tid, struct sk_buff *ampdu_skb)
+_queue_early_ampdu	smac/ampdu.c	/^void _queue_early_ampdu (struct ssv_softc *sc, struct AMPDU_TID_st *ampdu_tid,$/;"	f	signature:(struct ssv_softc *sc, struct AMPDU_TID_st *ampdu_tid, struct sk_buff *ampdu_skb)
+_read_chip_id	hwif/sdio/sdio.c	/^static void _read_chip_id (struct ssv6xxx_sdio_glue *glue)$/;"	f	file:	signature:(struct ssv6xxx_sdio_glue *glue)
+_read_chip_id	hwif/usb/usb.c	/^static void _read_chip_id (struct ssv6xxx_usb_glue *glue)$/;"	f	file:	signature:(struct ssv6xxx_usb_glue *glue)
+_remove_spur_patch	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void _remove_spur_patch(struct ssv_hw *sh, struct ssv6006_padpd *dpd,$/;"	f	file:	signature:(struct ssv_hw *sh, struct ssv6006_padpd *dpd, struct ssv6006_cal_result *cal)
+_remove_sta_skb_from_q	smac/dev.c	/^static u32 _remove_sta_skb_from_q (struct ssv_softc *sc, struct sk_buff_head *q,$/;"	p	file:	signature:(struct ssv_softc *sc, struct sk_buff_head *q, u32 addr0_3, u32 addr4_5)
+_remove_sta_skb_from_q	smac/dev.c	/^u32 _remove_sta_skb_from_q (struct ssv_softc *sc, struct sk_buff_head *q,$/;"	f	signature:(struct ssv_softc *sc, struct sk_buff_head *q, u32 addr0_3, u32 addr4_5)
+_reset_ampdu_mib	smac/ampdu.c	/^static void _reset_ampdu_mib (struct ssv_softc *sc, struct ssv_sta_info *sta_info, void *param)$/;"	f	file:	signature:(struct ssv_softc *sc, struct ssv_sta_info *sta_info, void *param)
+_restore_cal	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void _restore_cal (struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+_restore_dpd	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void _restore_dpd(struct ssv_hw *sh, struct ssv6006_padpd *dpd)$/;"	f	file:	signature:(struct ssv_hw *sh, struct ssv6006_padpd *dpd)
+_resume_crypto_task	smac/dev.c	/^void _resume_crypto_task (struct ssv_softc *sc)$/;"	f	signature:(struct ssv_softc *sc)
+_send_hci_skb	smac/ampdu.c	/^void _send_hci_skb (struct ssv_softc *sc, struct sk_buff *skb, u32 tx_flag)$/;"	f	signature:(struct ssv_softc *sc, struct sk_buff *skb, u32 tx_flag)
+_set_2g_channel	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void _set_2g_channel(struct ssv_hw *sh, int ch)$/;"	f	file:	signature:(struct ssv_hw *sh, int ch)
+_set_5g_channel	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void _set_5g_channel(struct ssv_hw *sh, int ch)$/;"	f	file:	signature:(struct ssv_hw *sh, int ch)
+_set_aes_tkip_hw_crypto_group_key	smac/dev.c	/^static void _set_aes_tkip_hw_crypto_group_key (struct ssv_softc *sc,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ssv_vif_info *vif_info, struct ssv_sta_info *sta_info, void *param)
+_set_group_key_sms4	smac/dev.c	/^static int _set_group_key_sms4 (struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv, struct ssv_sta_priv_data *sta_priv, enum SSV_CIPHER_E cipher, struct ieee80211_key_conf *key)
+_set_group_key_tkip_ccmp	smac/dev.c	/^static int _set_group_key_tkip_ccmp (struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv, struct ssv_sta_priv_data *sta_priv, enum SSV_CIPHER_E cipher, struct ieee80211_key_conf *key)
+_set_ht20_g_resp_rate	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void _set_ht20_g_resp_rate(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+_set_ht40_g_resp_rate	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void _set_ht40_g_resp_rate(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+_set_initial_cfg_default	ssvdevice/ssvdevice.c	/^static void _set_initial_cfg_default(void)$/;"	f	file:	signature:(void)
+_set_key_sms4	smac/dev.c	/^static int _set_key_sms4 (struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv, struct ssv_sta_priv_data *sta_priv, enum SSV_CIPHER_E cipher, struct ieee80211_key_conf *key)
+_set_key_tkip_ccmp	smac/dev.c	/^static int _set_key_tkip_ccmp (struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv, struct ssv_sta_priv_data *sta_priv, enum SSV_CIPHER_E cipher, struct ieee80211_key_conf *key)
+_set_key_wep	smac/dev.c	/^int _set_key_wep (struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv,$/;"	f	signature:(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv, struct ssv_sta_priv_data *sta_priv, enum SSV_CIPHER_E cipher, struct ieee80211_key_conf *key)
+_set_pairwise_key_sms4	smac/dev.c	/^static int _set_pairwise_key_sms4 (struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv, struct ssv_sta_priv_data *sta_priv, enum SSV_CIPHER_E cipher, struct ieee80211_key_conf *key)
+_set_pairwise_key_tkip_ccmp	smac/dev.c	/^static int _set_pairwise_key_tkip_ccmp (struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv, struct ssv_sta_priv_data *sta_priv, enum SSV_CIPHER_E cipher, struct ieee80211_key_conf *key)
+_set_turismoC_BW	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void _set_turismoC_BW(struct ssv_hw *sh, enum nl80211_channel_type channel_type)$/;"	f	file:	signature:(struct ssv_hw *sh, enum nl80211_channel_type channel_type)
+_set_tx_pwr	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void _set_tx_pwr(struct ssv_softc *sc, u32 pa_band, u32 txpwr)$/;"	f	file:	signature:(struct ssv_softc *sc, u32 pa_band, u32 txpwr)
+_set_tx_pwr	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void _set_tx_pwr(struct ssv_softc *sc, u32 pa_band, u32 txpwr);$/;"	p	file:	signature:(struct ssv_softc *sc, u32 pa_band, u32 txpwr)
+_set_wep_hw_crypto_group_key	smac/dev.c	/^static void _set_wep_hw_crypto_group_key (struct ssv_softc *sc,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ssv_vif_info *vif_info, struct ssv_sta_info *sta_info, void *param)
+_set_wep_hw_crypto_pair_key	smac/dev.c	/^static void _set_wep_hw_crypto_pair_key (struct ssv_softc *sc,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ssv_vif_info *vif_info, struct ssv_sta_info *sta_info, void *param)
+_set_wep_sw_crypto_key	smac/dev.c	/^void _set_wep_sw_crypto_key (struct ssv_softc *sc,$/;"	f	signature:(struct ssv_softc *sc, struct ssv_vif_info *vif_info, struct ssv_sta_info *sta_info, void *param)
+_set_wep_sw_crypto_key	smac/dev.h	/^void _set_wep_sw_crypto_key(struct ssv_softc *sc, struct ssv_vif_info *vif_info,$/;"	p	signature:(struct ssv_softc *sc, struct ssv_vif_info *vif_info, struct ssv_sta_info *sta_info, void *param)
+_ssv6006_get_ic_time_tag	smac/hal/ssv6006c/ssv6006C_mac.c	/^static u64 _ssv6006_get_ic_time_tag(struct ssv_softc *sc)$/;"	f	file:	signature:(struct ssv_softc *sc)
+_ssv6xxx_hexdump	smac/dev.c	/^void _ssv6xxx_hexdump(const char *title, const u8 *buf,$/;"	f	signature:(const char *title, const u8 *buf, size_t len)
+_ssv6xxx_hexdump	smac/dev.h	/^void _ssv6xxx_hexdump(const char *title, const u8 *buf, size_t len);$/;"	p	signature:(const char *title, const u8 *buf, size_t len)
+_ssv6xxx_tx	smac/dev.c	/^static void _ssv6xxx_tx (struct ieee80211_hw *hw, struct sk_buff *skb)$/;"	f	file:	signature:(struct ieee80211_hw *hw, struct sk_buff *skb)
+_ssv6xxx_txtput	smac/dev.h	/^struct _ssv6xxx_txtput{$/;"	s
+_ssv6xxx_txtput::loop_times	smac/dev.h	/^    u32 loop_times;$/;"	m	struct:_ssv6xxx_txtput	access:public
+_ssv6xxx_txtput::occupied_tx_pages	smac/dev.h	/^    u32 occupied_tx_pages;$/;"	m	struct:_ssv6xxx_txtput	access:public
+_ssv6xxx_txtput::size_per_frame	smac/dev.h	/^    u32 size_per_frame;$/;"	m	struct:_ssv6xxx_txtput	access:public
+_ssv6xxx_txtput::skb	smac/dev.h	/^    struct sk_buff *skb;$/;"	m	struct:_ssv6xxx_txtput	typeref:struct:_ssv6xxx_txtput::sk_buff	access:public
+_ssv6xxx_txtput::txtput_tsk	smac/dev.h	/^    struct task_struct *txtput_tsk;$/;"	m	struct:_ssv6xxx_txtput	typeref:struct:_ssv6xxx_txtput::task_struct	access:public
+_ssv_airkiss_disable_setchannel_timer	smartlink/airkiss.c	/^static int _ssv_airkiss_disable_setchannel_timer(void)$/;"	f	file:	signature:(void)
+_ssv_airkiss_enable_setchannel_timer	smartlink/airkiss.c	/^static int _ssv_airkiss_enable_setchannel_timer(void)$/;"	f	file:	signature:(void)
+_ssv_airkiss_finish	smartlink/airkiss.c	/^static void _ssv_airkiss_finish(void)$/;"	f	file:	signature:(void)
+_ssv_airkiss_setchannel_callback	smartlink/airkiss.c	/^static void _ssv_airkiss_setchannel_callback(int signum)$/;"	f	file:	signature:(int signum)
+_ssv_airkiss_write_wpa_config_file	smartlink/airkiss.c	/^static int _ssv_airkiss_write_wpa_config_file(char *pFileName, char *pSSID, char *pPWD)$/;"	f	file:	signature:(char *pFileName, char *pSSID, char *pPWD)
+_ssv_get_channel	smartlink/ssv_smartlink.c	/^static int _ssv_get_channel(unsigned int *pch)$/;"	f	file:	signature:(unsigned int *pch)
+_ssv_get_promisc	smartlink/ssv_smartlink.c	/^static int _ssv_get_promisc(int sock_fd, unsigned int *promisc)$/;"	f	file:	signature:(int sock_fd, unsigned int *promisc)
+_ssv_get_si_pass	smartlink/ssv_smartlink.c	/^static int _ssv_get_si_pass(uint8_t *pass)$/;"	f	file:	signature:(uint8_t *pass)
+_ssv_get_si_ssid	smartlink/ssv_smartlink.c	/^static int _ssv_get_si_ssid(uint8_t *ssid)$/;"	f	file:	signature:(uint8_t *ssid)
+_ssv_get_si_status	smartlink/ssv_smartlink.c	/^static int _ssv_get_si_status(uint8_t *status)$/;"	f	file:	signature:(uint8_t *status)
+_ssv_netlink_close	smartlink/ssv_smartlink.c	/^static int _ssv_netlink_close(int *psock_fd)$/;"	f	file:	signature:(int *psock_fd)
+_ssv_netlink_init	smartlink/ssv_smartlink.c	/^static int _ssv_netlink_init(void)$/;"	f	file:	signature:(void)
+_ssv_qqlink_disable_setchannel_timer	smartlink/qqlink.c	/^static int _ssv_qqlink_disable_setchannel_timer(void)$/;"	f	file:	signature:(void)
+_ssv_qqlink_enable_setchannel_timer	smartlink/qqlink.c	/^static int _ssv_qqlink_enable_setchannel_timer(void)$/;"	f	file:	signature:(void)
+_ssv_qqlink_setchannel_callback	smartlink/qqlink.c	/^static void _ssv_qqlink_setchannel_callback(int signum)$/;"	f	file:	signature:(int signum)
+_ssv_qqlink_write_wpa_config_file	smartlink/qqlink.c	/^static int _ssv_qqlink_write_wpa_config_file(char *pFileName, char *pSSID, char *pPWD)$/;"	f	file:	signature:(char *pFileName, char *pSSID, char *pPWD)
+_ssv_set_channel	smartlink/ssv_smartlink.c	/^static int _ssv_set_channel(unsigned int ch)$/;"	f	file:	signature:(unsigned int ch)
+_ssv_set_promisc	smartlink/ssv_smartlink.c	/^static int _ssv_set_promisc(unsigned int promisc)$/;"	f	file:	signature:(unsigned int promisc)
+_ssv_set_si_cmd	smartlink/ssv_smartlink.c	/^static int _ssv_set_si_cmd(int sock_fd, unsigned int command)$/;"	f	file:	signature:(int sock_fd, unsigned int command)
+_ssv_sig_int	smartlink/airkiss.c	/^static void _ssv_sig_int(int signum)$/;"	f	file:	signature:(int signum)
+_ssv_sig_int	smartlink/qqlink.c	/^static void _ssv_sig_int(int signum)$/;"	f	file:	signature:(int signum)
+_ssv_trigger_smarticomm	smartlink/ssv_smartlink.c	/^static int _ssv_trigger_smarticomm(unsigned int enable)$/;"	f	file:	signature:(unsigned int enable)
+_ssv_trigger_smartlink	smartlink/ssv_smartlink.c	/^static int _ssv_trigger_smartlink(unsigned int enable)$/;"	f	file:	signature:(unsigned int enable)
+_sta_rxstats	smac/hal/ssv6006c/ssv6006_phy.c	/^static void _sta_rxstats(struct ssv_softc *sc, struct ssv_sta_priv_data *sta_priv) {$/;"	f	file:	signature:(struct ssv_softc *sc, struct ssv_sta_priv_data *sta_priv)
+_sta_txstats	smac/hal/ssv6006c/ssv6006_phy.c	/^static void _sta_txstats(struct ssv_softc *sc, struct ssv_sta_priv_data *sta_priv) {$/;"	f	file:	signature:(struct ssv_softc *sc, struct ssv_sta_priv_data *sta_priv)
+_start_padpd	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void _start_padpd(struct ssv_hw *sh, struct ssv6006dpd *val, int pa_band, int init_gain, u8 dpd_bbscale, int *ret)$/;"	f	file:	signature:(struct ssv_hw *sh, struct ssv6006dpd *val, int pa_band, int init_gain, u8 dpd_bbscale, int *ret)
+_stop_crypto_task	smac/dev.c	/^void _stop_crypto_task (struct ssv_softc *sc)$/;"	f	signature:(struct ssv_softc *sc)
+_store_wep_key	smac/dev.c	/^static void _store_wep_key(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv, struct ssv_sta_priv_data *sta_priv, enum SSV_CIPHER_E cipher, struct ieee80211_key_conf *key)
+_sync_ampdu_pkt_arr	smac/ampdu.c	/^bool _sync_ampdu_pkt_arr (struct ssv_softc *sc, struct AMPDU_TID_st *ampdu_tid$/;"	f	signature:(struct ssv_softc *sc, struct AMPDU_TID_st *ampdu_tid , struct sk_buff *ampdu, bool retry)
+_sync_ampdu_pkt_arr	smac/ampdu.c	/^static bool _sync_ampdu_pkt_arr (struct ssv_softc *sc, struct AMPDU_TID_st *ampdu_tid,$/;"	p	file:	signature:(struct ssv_softc *sc, struct AMPDU_TID_st *ampdu_tid, struct sk_buff *ampdu_skb, bool retry)
+_sz_password	smartlink/qqlink.c	/^static char _sz_password[QLMAX_PSWD_LEN];$/;"	v	file:
+_sz_ssid	smartlink/qqlink.c	/^static char _sz_ssid[QLMAX_SSID_LEN];$/;"	v	file:
+_turismoC_2p4g_rxdc_cal	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void _turismoC_2p4g_rxdc_cal(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+_turismoC_5g_rxdc_cal	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void _turismoC_5g_rxdc_cal(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+_turismoC_5g_rxiq_cal	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void _turismoC_5g_rxiq_cal(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+_turismoC_5g_rxiq_cal_band	smac/hal/ssv6006c/ssv6006_turismoC.c	/^void _turismoC_5g_rxiq_cal_band(struct ssv_hw *sh, int pa_band)$/;"	f	signature:(struct ssv_hw *sh, int pa_band)
+_turismoC_5g_txdc_cal	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void _turismoC_5g_txdc_cal(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+_turismoC_5g_txiq_cal	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void _turismoC_5g_txiq_cal(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+_turismoC_5g_txiq_cal_band	smac/hal/ssv6006c/ssv6006_turismoC.c	/^void _turismoC_5g_txiq_cal_band(struct ssv_hw *sh, int pa_band)$/;"	f	signature:(struct ssv_hw *sh, int pa_band)
+_turismoC_bw20_rxrc_cal	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void _turismoC_bw20_rxrc_cal(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+_turismoC_bw40_rxrc_cal	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void _turismoC_bw40_rxrc_cal(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+_turismoC_inter_cal	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void _turismoC_inter_cal(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+_turismoC_post_cal	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void _turismoC_post_cal(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+_turismoC_pre_cal	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void _turismoC_pre_cal(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+_turismoC_rxiq_cal	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void _turismoC_rxiq_cal(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+_turismoC_txdc_cal	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void _turismoC_txdc_cal(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+_turismoC_txiq_cal	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void _turismoC_txiq_cal(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+_tx_audio_encode_param	smartlink/qqlink-lib-mipsel/include/TXAudioVideo.h	/^typedef struct _tx_audio_encode_param$/;"	s
+_tx_audio_encode_param::audio_format	smartlink/qqlink-lib-mipsel/include/TXAudioVideo.h	/^ unsigned char audio_format;$/;"	m	struct:_tx_audio_encode_param	access:public
+_tx_audio_encode_param::encode_param	smartlink/qqlink-lib-mipsel/include/TXAudioVideo.h	/^ unsigned char encode_param;$/;"	m	struct:_tx_audio_encode_param	access:public
+_tx_audio_encode_param::frame_per_pkg	smartlink/qqlink-lib-mipsel/include/TXAudioVideo.h	/^ unsigned char frame_per_pkg;$/;"	m	struct:_tx_audio_encode_param	access:public
+_tx_audio_encode_param::head_length	smartlink/qqlink-lib-mipsel/include/TXAudioVideo.h	/^ unsigned char head_length;$/;"	m	struct:_tx_audio_encode_param	access:public
+_tx_audio_encode_param::reserved	smartlink/qqlink-lib-mipsel/include/TXAudioVideo.h	/^ unsigned int reserved;$/;"	m	struct:_tx_audio_encode_param	access:public
+_tx_audio_encode_param::sampling_info	smartlink/qqlink-lib-mipsel/include/TXAudioVideo.h	/^ unsigned int sampling_info;$/;"	m	struct:_tx_audio_encode_param	access:public
+_tx_av_callback	smartlink/qqlink-lib-mipsel/include/TXAudioVideo.h	/^typedef struct _tx_av_callback$/;"	s
+_tx_av_callback::on_recv_audiodata	smartlink/qqlink-lib-mipsel/include/TXAudioVideo.h	/^    void (*on_recv_audiodata)(tx_audio_encode_param *param, unsigned char *pcEncData, int nEncDataLen);$/;"	m	struct:_tx_av_callback	access:public
+_tx_av_callback::on_set_bitrate	smartlink/qqlink-lib-mipsel/include/TXAudioVideo.h	/^    bool (*on_set_bitrate)(int bit_rate);$/;"	m	struct:_tx_av_callback	access:public
+_tx_av_callback::on_start_camera	smartlink/qqlink-lib-mipsel/include/TXAudioVideo.h	/^    bool (*on_start_camera)();$/;"	m	struct:_tx_av_callback	access:public
+_tx_av_callback::on_start_mic	smartlink/qqlink-lib-mipsel/include/TXAudioVideo.h	/^    bool (*on_start_mic)();$/;"	m	struct:_tx_av_callback	access:public
+_tx_av_callback::on_stop_camera	smartlink/qqlink-lib-mipsel/include/TXAudioVideo.h	/^    bool (*on_stop_camera)();$/;"	m	struct:_tx_av_callback	access:public
+_tx_av_callback::on_stop_mic	smartlink/qqlink-lib-mipsel/include/TXAudioVideo.h	/^    bool (*on_stop_mic)();$/;"	m	struct:_tx_av_callback	access:public
+_tx_device_info	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^typedef struct _tx_device_info$/;"	s
+_tx_device_info::device_license	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    char * device_license;$/;"	m	struct:_tx_device_info	access:public
+_tx_device_info::device_name	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    char * device_name;$/;"	m	struct:_tx_device_info	access:public
+_tx_device_info::device_serial_number	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    char * device_serial_number;$/;"	m	struct:_tx_device_info	access:public
+_tx_device_info::network_type	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    int network_type;$/;"	m	struct:_tx_device_info	access:public
+_tx_device_info::os_platform	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    char * os_platform;$/;"	m	struct:_tx_device_info	access:public
+_tx_device_info::product_id	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    int product_id;$/;"	m	struct:_tx_device_info	access:public
+_tx_device_info::product_version	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    int product_version;$/;"	m	struct:_tx_device_info	access:public
+_tx_device_info::server_pub_key	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    char * server_pub_key;$/;"	m	struct:_tx_device_info	access:public
+_tx_device_info::test_mode	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    unsigned int test_mode;$/;"	m	struct:_tx_device_info	access:public
+_tx_device_notify	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^typedef struct _tx_device_notify$/;"	s
+_tx_device_notify::on_binder_list_change	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    void (*on_binder_list_change)(int error_code, tx_binder_info * pBinderList, int nCount);$/;"	m	struct:_tx_device_notify	access:public
+_tx_device_notify::on_login_complete	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    void (*on_login_complete)(int error_code);$/;"	m	struct:_tx_device_notify	access:public
+_tx_device_notify::on_online_status	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    void (*on_online_status)(int old_status, int new_status);$/;"	m	struct:_tx_device_notify	access:public
+_tx_history_video_notify	smartlink/qqlink-lib-mipsel/include/TXIPCAM.h	/^typedef struct _tx_history_video_notify$/;"	s
+_tx_history_video_notify::on_fetch_history_video	smartlink/qqlink-lib-mipsel/include/TXIPCAM.h	/^ void (*on_fetch_history_video)(unsigned int last_time, int max_count, int *count, tx_history_video_range * range_list);$/;"	m	struct:_tx_history_video_notify	access:public
+_tx_history_video_notify::on_play_history_video	smartlink/qqlink-lib-mipsel/include/TXIPCAM.h	/^ void (*on_play_history_video)(unsigned int play_time);$/;"	m	struct:_tx_history_video_notify	access:public
+_tx_history_video_range	smartlink/qqlink-lib-mipsel/include/TXIPCAM.h	/^typedef struct _tx_history_video_range$/;"	s
+_tx_history_video_range::end_time	smartlink/qqlink-lib-mipsel/include/TXIPCAM.h	/^ unsigned int end_time;$/;"	m	struct:_tx_history_video_range	access:public
+_tx_history_video_range::start_time	smartlink/qqlink-lib-mipsel/include/TXIPCAM.h	/^ unsigned int start_time;$/;"	m	struct:_tx_history_video_range	access:public
+_tx_init_path	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^typedef struct _tx_init_path$/;"	s
+_tx_init_path::app_path	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    char * app_path;$/;"	m	struct:_tx_init_path	access:public
+_tx_init_path::app_path_capicity	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    unsigned int app_path_capicity;$/;"	m	struct:_tx_init_path	access:public
+_tx_init_path::system_path	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    char * system_path;$/;"	m	struct:_tx_init_path	access:public
+_tx_init_path::system_path_capicity	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    unsigned int system_path_capicity;$/;"	m	struct:_tx_init_path	access:public
+_tx_init_path::temp_path	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    char * temp_path;$/;"	m	struct:_tx_init_path	access:public
+_tx_init_path::temp_path_capicity	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    unsigned int temp_path_capicity;$/;"	m	struct:_tx_init_path	access:public
+_tx_ipcamera_notify	smartlink/qqlink-lib-mipsel/include/TXIPCAM.h	/^typedef struct _tx_ipcamera_notify {$/;"	s
+_tx_ipcamera_notify::on_control_rotate	smartlink/qqlink-lib-mipsel/include/TXIPCAM.h	/^ int (*on_control_rotate)(int rotate_direction, int rotate_degree);$/;"	m	struct:_tx_ipcamera_notify	access:public
+_tx_ipcamera_notify::on_set_definition	smartlink/qqlink-lib-mipsel/include/TXIPCAM.h	/^ int (*on_set_definition)(int definition, char *cur_definition, int cur_definition_length);$/;"	m	struct:_tx_ipcamera_notify	access:public
+_tx_ota_notify	smartlink/qqlink-lib-mipsel/include/TXOTA.h	/^typedef struct _tx_ota_notify$/;"	s
+_tx_ota_notify::on_download_complete	smartlink/qqlink-lib-mipsel/include/TXOTA.h	/^ void (*on_download_complete)(int ret_code);$/;"	m	struct:_tx_ota_notify	access:public
+_tx_ota_notify::on_download_progress	smartlink/qqlink-lib-mipsel/include/TXOTA.h	/^ void (*on_download_progress)(unsigned long long download_size, unsigned long long total_size);$/;"	m	struct:_tx_ota_notify	access:public
+_tx_ota_notify::on_new_pkg_come	smartlink/qqlink-lib-mipsel/include/TXOTA.h	/^ int (*on_new_pkg_come)(unsigned long long from, unsigned long long pkg_size, const char * title, const char * desc, unsigned int target_version);$/;"	m	struct:_tx_ota_notify	access:public
+_tx_ota_notify::on_update_confirm	smartlink/qqlink-lib-mipsel/include/TXOTA.h	/^ void (*on_update_confirm)();$/;"	m	struct:_tx_ota_notify	access:public
+_tx_send_msg_notify	smartlink/qqlink-lib-mipsel/include/TXMsg.h	/^typedef struct _tx_send_msg_notify$/;"	s
+_tx_send_msg_notify::on_file_transfer_progress	smartlink/qqlink-lib-mipsel/include/TXMsg.h	/^    void (*on_file_transfer_progress)(const unsigned int cookie, unsigned long long transfer_progress, unsigned long long max_transfer_progress);$/;"	m	struct:_tx_send_msg_notify	access:public
+_tx_send_msg_notify::on_send_structuring_msg_ret	smartlink/qqlink-lib-mipsel/include/TXMsg.h	/^    void (*on_send_structuring_msg_ret)(const unsigned int cookie, int err_code);$/;"	m	struct:_tx_send_msg_notify	access:public
+_update_green_tx	smac/hal/ssv6006c/ssv6006_phy.c	/^void _update_green_tx(struct ssv_softc *sc, u16 rssi)$/;"	f	signature:(struct ssv_softc *sc, u16 rssi)
+_update_ht_rpt	smac/hal/ssv6006c/ssv6006_phy.c	/^static void _update_ht_rpt(struct ssv_softc *sc, struct ssv6006_tx_desc *tx_desc,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ssv6006_tx_desc *tx_desc, struct ssv_minstrel_ht_rpt *ht_rpt)
+_update_rf_patch	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void _update_rf_patch(struct ssv_hw *sh, int xtal)$/;"	f	file:	signature:(struct ssv_hw *sh, int xtal)
+_verify_dpd	smac/hal/ssv6006c/ssv6006_turismoC.c	/^void _verify_dpd(struct ssv_hw *sh, struct ssv6006_padpd *dpd, int pa_band)$/;"	f	signature:(struct ssv_hw *sh, struct ssv6006_padpd *dpd, int pa_band)
+_write_group_key_to_hw	smac/dev.c	/^static int _write_group_key_to_hw (struct ssv_softc *sc,$/;"	f	file:	signature:(struct ssv_softc *sc, int index, u8 algorithm, const u8 *key, int key_len, struct ieee80211_key_conf *keyconf, struct ssv_vif_priv_data *vif_priv, struct ssv_sta_priv_data *sta_priv)
+_write_pairwise_key_to_hw	smac/dev.c	/^static int _write_pairwise_key_to_hw (struct ssv_softc *sc,$/;"	f	file:	signature:(struct ssv_softc *sc, int index, u8 algorithm, const u8 *key, int key_len, struct ieee80211_key_conf *keyconf, struct ssv_vif_priv_data *vif_priv, struct ssv_sta_priv_data *sta_priv)
+a_band_gain	smac/dev.h	/^    u8 a_band_gain[4];$/;"	m	struct:ssv_tempe_table	access:public
+a_band_gain_ht	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 a_band_gain_ht[4];$/;"	m	struct:ssv6006_flash_layout_table	access:public
+a_band_gain_lt	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 a_band_gain_lt[4];$/;"	m	struct:ssv6006_flash_layout_table	access:public
+a_band_gain_rt	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 a_band_gain_rt[4];$/;"	m	struct:ssv6006_flash_layout_table	access:public
+a_band_pa_bias0	smac/dev.h	/^    u32 a_band_pa_bias0;$/;"	m	struct:ssv_flash_config	access:public
+a_band_pa_bias0	smac/hal/ssv6006c/ssv6006_mac.h	/^    u32 a_band_pa_bias0;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+a_band_pa_bias1	smac/dev.h	/^    u32 a_band_pa_bias1;$/;"	m	struct:ssv_flash_config	access:public
+a_band_pa_bias1	smac/hal/ssv6006c/ssv6006_mac.h	/^    u32 a_band_pa_bias1;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+ac	smac/ampdu.h	/^    u16 ac;$/;"	m	struct:AMPDU_TID_st	access:public
+ac_txqid	smac/dev.h	/^    int ac_txqid[WMM_NUM_AC];$/;"	m	struct:ssv_tx	access:public
+accu_rx_len	include/ssv6xxx_common.h	/^    u32 accu_rx_len:16;$/;"	m	struct:hci_rx_aggr_info	access:public
+ack_counter	smac/dev.h	/^    u8 ack_counter;$/;"	m	struct:ssv_softc	access:public
+ack_policy	include/ssv6200_common.h	/^    u32 ack_policy:2;$/;"	m	struct:ssv6200_tx_desc	access:public
+ack_policy0	smac/hal/ssv6006c/turismo_common.h	/^    u32 ack_policy0:2;$/;"	m	struct:ssv6006_tx_desc	access:public
+ack_policy1	smac/hal/ssv6006c/turismo_common.h	/^    u32 ack_policy1:2;$/;"	m	struct:ssv6006_tx_desc	access:public
+ack_policy2	smac/hal/ssv6006c/turismo_common.h	/^    u32 ack_policy2:2;$/;"	m	struct:ssv6006_tx_desc	access:public
+ack_policy3	smac/hal/ssv6006c/turismo_common.h	/^    u32 ack_policy3:2;$/;"	m	struct:ssv6006_tx_desc	access:public
+ack_policy_obsolete	smac/hal/ssv6006c/turismo_common.h	/^    u32 ack_policy_obsolete:2;$/;"	m	struct:ssv6006_tx_desc	access:public
+ack_signal	include/ssv6200_common.h	/^    int ack_signal;$/;"	m	struct:firmware_rate_control_report_data	access:public
+ack_time	smac/ssv_rc_minstrel.h	/^ unsigned int ack_time;$/;"	m	struct:ssv_minstrel_rate	access:public
+active_noa_vif	smac/p2p.h	/^    u8 active_noa_vif;$/;"	m	struct:ssv_p2p_noa	access:public
+acts_wifi_cleanup	platforms/atm7039-action-generic-wlan.c	/^extern void acts_wifi_cleanup(void);$/;"	p	file:	signature:(void)
+acts_wifi_init	platforms/atm7039-action-generic-wlan.c	/^extern int acts_wifi_init(int type);$/;"	p	file:	signature:(int type)
+add_ampdu_txinfo	smac/dev.h	/^    void (*add_ampdu_txinfo)(struct ssv_softc *sc, struct sk_buff *ampdu_skb);$/;"	m	struct:ssv_hal_ops	access:public
+add_fw_wsid	smac/dev.h	/^    void (*add_fw_wsid)(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv,$/;"	m	struct:ssv_hal_ops	access:public
+add_txinfo	smac/dev.h	/^    void (*add_txinfo) (struct ssv_softc *sc, struct sk_buff *skb);$/;"	m	struct:ssv_hal_ops	access:public
+addr	hwif/usb/usb.h	/^ u32 addr;$/;"	m	struct:ssv6xxx_read_reg	access:public
+addr	hwif/usb/usb.h	/^ u32 addr;$/;"	m	struct:ssv6xxx_write_reg	access:public
+addr	smac/dev.h	/^    u32 addr;$/;"	m	struct:ssv_hw_cfg	access:public
+addr	smac/hal/ssv6006c/turismo_common.h	/^    u32 addr;$/;"	m	struct:padpd_table	access:public
+addr_increase_copy	smac/efuse.c	/^void addr_increase_copy(u8 *dst, u8 *src)$/;"	f	signature:(u8 *dst, u8 *src)
+address	hwif/usb/usb.h	/^ u8 address;$/;"	m	struct:ssv6xxx_cmd_endpoint	access:public
+address	hwif/usb/usb.h	/^ u8 address;$/;"	m	struct:ssv6xxx_rx_endpoint	access:public
+address	hwif/usb/usb.h	/^ u8 address;$/;"	m	struct:ssv6xxx_tx_endpoint	access:public
+address	include/ssv6xxx_common.h	/^    u32 address;$/;"	m	struct:ssv_cabrio_reg_st	access:public
+address	ssvdevice/ssv_cmd.c	/^    u32 address;$/;"	m	struct:ssv6xxx_dev_table	file:	access:public
+address	umac/ssv6xxx_netlink_core.h	/^ u32 address;$/;"	m	struct:ssv_wireless_register	access:public
+adj_config	smac/dev.h	/^ void (*adj_config)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+adjust_cca_1	smac/dev.h	/^    u32 adjust_cca_1;$/;"	m	struct:ssv6xxx_b_cca_control	access:public
+adjust_cca_control	smac/dev.h	/^    u32 adjust_cca_control;$/;"	m	struct:ssv6xxx_b_cca_control	access:public
+adjust_cci	smac/dev.c	/^struct ssv6xxx_b_cca_control adjust_cci[] = {$/;"	v	typeref:struct:ssv6xxx_b_cca_control
+adjust_cci	smac/hal/ssv6006c/ssv6006_phy.c	/^static struct ssv6xxx_cca_control adjust_cci[] = {$/;"	v	typeref:struct:ssv6xxx_cca_control	file:
+adjust_cck_cca_control	smac/dev.h	/^    u32 adjust_cck_cca_control;$/;"	m	struct:ssv6xxx_cca_control	access:public
+adjust_ofdm_cca_control	smac/dev.h	/^    u32 adjust_ofdm_cca_control;$/;"	m	struct:ssv6xxx_cca_control	access:public
+adjusted_retry_count	smac/ssv_rc_minstrel.h	/^ unsigned int adjusted_retry_count;$/;"	m	struct:ssv_minstrel_rate	access:public
+aes_alg	crypto/aes_glue.c	/^static struct crypto_alg aes_alg = {$/;"	v	typeref:struct:crypto_alg	file:
+aes_decrypt	crypto/aes_glue.c	/^static void aes_decrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)$/;"	f	file:	signature:(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
+aes_encrypt	crypto/aes_glue.c	/^static void aes_encrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)$/;"	f	file:	signature:(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
+aes_fini	crypto/aes_glue.c	/^void aes_fini(void)$/;"	f	signature:(void)
+aes_fini	platforms/a33-generic-wlan.c	/^extern void aes_fini(void);$/;"	p	file:	signature:(void)
+aes_fini	platforms/aml-s805-generic-wlan.c	/^extern void aes_fini(void);$/;"	p	file:	signature:(void)
+aes_fini	platforms/aml-s905-generic-wlan.c	/^extern void aes_fini(void);$/;"	p	file:	signature:(void)
+aes_fini	platforms/atm7039-action-generic-wlan.c	/^extern void aes_fini(void);$/;"	p	file:	signature:(void)
+aes_fini	platforms/h3-generic-wlan.c	/^extern void aes_fini(void);$/;"	p	file:	signature:(void)
+aes_fini	platforms/h8-generic-wlan.c	/^extern void aes_fini(void);$/;"	p	file:	signature:(void)
+aes_fini	platforms/rk3036-generic-wlan.c	/^extern void aes_fini(void);$/;"	p	file:	signature:(void)
+aes_fini	platforms/rk3126-generic-wlan.c	/^extern void aes_fini(void);$/;"	p	file:	signature:(void)
+aes_fini	platforms/rk3128-generic-wlan.c	/^extern void aes_fini(void);$/;"	p	file:	signature:(void)
+aes_fini	platforms/rk322x-generic-wlan.c	/^extern void aes_fini(void);$/;"	p	file:	signature:(void)
+aes_fini	platforms/t10-generic-wlan.c	/^extern void aes_fini(void);$/;"	p	file:	signature:(void)
+aes_fini	platforms/x1000-generic-wlan.c	/^extern void aes_fini(void);$/;"	p	file:	signature:(void)
+aes_fini	platforms/xm-hi3518-generic-wlan.c	/^extern void aes_fini(void);$/;"	p	file:	signature:(void)
+aes_init	crypto/aes_glue.c	/^int aes_init(void)$/;"	f	signature:(void)
+aes_init	platforms/a33-generic-wlan.c	/^extern int aes_init(void);$/;"	p	file:	signature:(void)
+aes_init	platforms/aml-s805-generic-wlan.c	/^extern int aes_init(void);$/;"	p	file:	signature:(void)
+aes_init	platforms/aml-s905-generic-wlan.c	/^extern int aes_init(void);$/;"	p	file:	signature:(void)
+aes_init	platforms/atm7039-action-generic-wlan.c	/^extern int aes_init(void);$/;"	p	file:	signature:(void)
+aes_init	platforms/h3-generic-wlan.c	/^extern int aes_init(void);$/;"	p	file:	signature:(void)
+aes_init	platforms/h8-generic-wlan.c	/^extern int aes_init(void);$/;"	p	file:	signature:(void)
+aes_init	platforms/rk3036-generic-wlan.c	/^extern int aes_init(void);$/;"	p	file:	signature:(void)
+aes_init	platforms/rk3126-generic-wlan.c	/^extern int aes_init(void);$/;"	p	file:	signature:(void)
+aes_init	platforms/rk3128-generic-wlan.c	/^extern int aes_init(void);$/;"	p	file:	signature:(void)
+aes_init	platforms/rk322x-generic-wlan.c	/^extern int aes_init(void);$/;"	p	file:	signature:(void)
+aes_init	platforms/t10-generic-wlan.c	/^extern int aes_init(void);$/;"	p	file:	signature:(void)
+aes_init	platforms/x1000-generic-wlan.c	/^extern int aes_init(void);$/;"	p	file:	signature:(void)
+aes_init	platforms/xm-hi3518-generic-wlan.c	/^extern int aes_init(void);$/;"	p	file:	signature:(void)
+aes_set_key	crypto/aes_glue.c	/^static int aes_set_key(struct crypto_tfm *tfm, const u8 *in_key,$/;"	f	file:	signature:(struct crypto_tfm *tfm, const u8 *in_key, unsigned int key_len)
+agg_num_max	smac/ampdu.h	/^    u8 agg_num_max;$/;"	m	struct:AMPDU_TID_st	access:public
+aggr	smac/hal/ssv6006c/turismo_common.h	/^    u32 aggr:2;$/;"	m	struct:ssv6006_tx_desc	access:public
+aggr_pkt_num	smac/ampdu.h	/^    volatile u32 aggr_pkt_num;$/;"	m	struct:AMPDU_TID_st	access:public
+aggr_pkts	smac/ampdu.h	/^    struct sk_buff *aggr_pkts[SSV_AMPDU_BA_WINDOW_SIZE];$/;"	m	struct:AMPDU_TID_st	typeref:struct:AMPDU_TID_st::sk_buff	access:public
+aggr_size_sel_pr	include/ssv_cfg.h	/^    u32 aggr_size_sel_pr;$/;"	m	struct:ssv6xxx_cfg	access:public
+aggr_ssn	smac/dev.h	/^struct aggr_ssn{$/;"	s
+aggr_ssn::mpdu_num	smac/dev.h	/^    u16 mpdu_num;$/;"	m	struct:aggr_ssn	access:public
+aggr_ssn::ssn	smac/dev.h	/^    u16 ssn[MAX_AGGR_NUM];$/;"	m	struct:aggr_ssn	access:public
+aggr_ssn::tid_no	smac/dev.h	/^ u8 tid_no;$/;"	m	struct:aggr_ssn	access:public
+aggr_ssn::tx_pkt_run_no	smac/dev.h	/^    u16 tx_pkt_run_no;$/;"	m	struct:aggr_ssn	access:public
+aggr_timestamp	smac/ssv_skb.h	/^    unsigned long aggr_timestamp;$/;"	m	struct:SKB_info_st	access:public
+aggregate	include/ssv6200_common.h	/^    u32 aggregate:1;$/;"	m	struct:ssv6200_rxphy_info	access:public
+aggregate	smac/hal/ssv6006c/turismo_common.h	/^    u32 aggregate:1;$/;"	m	struct:ssv6006_rxphy_info	access:public
+aggregation	include/ssv6200_common.h	/^    u32 aggregation:1;$/;"	m	struct:ssv6200_tx_desc	access:public
+aging_period	include/ssv_cfg.h	/^    u16 aging_period;$/;"	m	struct:rc_setting	access:public
+aid	smac/dev.h	/^    u16 aid;$/;"	m	struct:ssv_sta_info	access:public
+aid0_bit_set	smac/dev.h	/^    bool aid0_bit_set;$/;"	m	struct:ssv_softc	access:public
+airkiss_change_channel	smartlink/airkiss-lib/airkiss.h	/^int airkiss_change_channel(airkiss_context_t* context);$/;"	p	signature:(airkiss_context_t* context)
+airkiss_change_channel	smartlink/airkiss-lib/mipsel/airkiss.h	/^int airkiss_change_channel(airkiss_context_t* context);$/;"	p	signature:(airkiss_context_t* context)
+airkiss_change_channel	smartlink/airkiss-lib/x64/airkiss.h	/^int airkiss_change_channel(airkiss_context_t* context);$/;"	p	signature:(airkiss_context_t* context)
+airkiss_config_t	smartlink/airkiss-lib/airkiss.h	/^} airkiss_config_t;$/;"	t	typeref:struct:__anon23
+airkiss_config_t	smartlink/airkiss-lib/mipsel/airkiss.h	/^} airkiss_config_t;$/;"	t	typeref:struct:__anon17
+airkiss_config_t	smartlink/airkiss-lib/x64/airkiss.h	/^} airkiss_config_t;$/;"	t	typeref:struct:__anon29
+airkiss_context_t	smartlink/airkiss-lib/airkiss.h	/^} airkiss_context_t;$/;"	t	typeref:struct:__anon24
+airkiss_context_t	smartlink/airkiss-lib/mipsel/airkiss.h	/^} airkiss_context_t;$/;"	t	typeref:struct:__anon18
+airkiss_context_t	smartlink/airkiss-lib/x64/airkiss.h	/^} airkiss_context_t;$/;"	t	typeref:struct:__anon30
+airkiss_get_result	smartlink/airkiss-lib/airkiss.h	/^int airkiss_get_result(airkiss_context_t* context, airkiss_result_t* result);$/;"	p	signature:(airkiss_context_t* context, airkiss_result_t* result)
+airkiss_get_result	smartlink/airkiss-lib/mipsel/airkiss.h	/^int airkiss_get_result(airkiss_context_t* context, airkiss_result_t* result);$/;"	p	signature:(airkiss_context_t* context, airkiss_result_t* result)
+airkiss_get_result	smartlink/airkiss-lib/x64/airkiss.h	/^int airkiss_get_result(airkiss_context_t* context, airkiss_result_t* result);$/;"	p	signature:(airkiss_context_t* context, airkiss_result_t* result)
+airkiss_init	smartlink/airkiss-lib/airkiss.h	/^int airkiss_init(airkiss_context_t* context, const airkiss_config_t* config);$/;"	p	signature:(airkiss_context_t* context, const airkiss_config_t* config)
+airkiss_init	smartlink/airkiss-lib/mipsel/airkiss.h	/^int airkiss_init(airkiss_context_t* context, const airkiss_config_t* config);$/;"	p	signature:(airkiss_context_t* context, const airkiss_config_t* config)
+airkiss_init	smartlink/airkiss-lib/x64/airkiss.h	/^int airkiss_init(airkiss_context_t* context, const airkiss_config_t* config);$/;"	p	signature:(airkiss_context_t* context, const airkiss_config_t* config)
+airkiss_lan_cmdid_t	smartlink/airkiss-lib/airkiss.h	/^} airkiss_lan_cmdid_t;$/;"	t	typeref:enum:__anon28
+airkiss_lan_cmdid_t	smartlink/airkiss-lib/mipsel/airkiss.h	/^} airkiss_lan_cmdid_t;$/;"	t	typeref:enum:__anon22
+airkiss_lan_cmdid_t	smartlink/airkiss-lib/x64/airkiss.h	/^} airkiss_lan_cmdid_t;$/;"	t	typeref:enum:__anon34
+airkiss_lan_pack	smartlink/airkiss-lib/airkiss.h	/^int airkiss_lan_pack(airkiss_lan_cmdid_t ak_lan_cmdid, void* appid, void* deviceid, void* _datain, unsigned short inlength, void* _dataout, unsigned short* outlength, const airkiss_config_t* config);$/;"	p	signature:(airkiss_lan_cmdid_t ak_lan_cmdid, void* appid, void* deviceid, void* _datain, unsigned short inlength, void* _dataout, unsigned short* outlength, const airkiss_config_t* config)
+airkiss_lan_pack	smartlink/airkiss-lib/mipsel/airkiss.h	/^int airkiss_lan_pack(airkiss_lan_cmdid_t ak_lan_cmdid, void* appid, void* deviceid, void* _datain, unsigned short inlength, void* _dataout, unsigned short* outlength, const airkiss_config_t* config);$/;"	p	signature:(airkiss_lan_cmdid_t ak_lan_cmdid, void* appid, void* deviceid, void* _datain, unsigned short inlength, void* _dataout, unsigned short* outlength, const airkiss_config_t* config)
+airkiss_lan_pack	smartlink/airkiss-lib/x64/airkiss.h	/^int airkiss_lan_pack(airkiss_lan_cmdid_t ak_lan_cmdid, void* appid, void* deviceid, void* _datain, unsigned short inlength, void* _dataout, unsigned short* outlength, const airkiss_config_t* config);$/;"	p	signature:(airkiss_lan_cmdid_t ak_lan_cmdid, void* appid, void* deviceid, void* _datain, unsigned short inlength, void* _dataout, unsigned short* outlength, const airkiss_config_t* config)
+airkiss_lan_recv	smartlink/airkiss-lib/airkiss.h	/^int airkiss_lan_recv(const void* body, unsigned short length, const airkiss_config_t* config);$/;"	p	signature:(const void* body, unsigned short length, const airkiss_config_t* config)
+airkiss_lan_recv	smartlink/airkiss-lib/mipsel/airkiss.h	/^int airkiss_lan_recv(const void* body, unsigned short length, const airkiss_config_t* config);$/;"	p	signature:(const void* body, unsigned short length, const airkiss_config_t* config)
+airkiss_lan_recv	smartlink/airkiss-lib/x64/airkiss.h	/^int airkiss_lan_recv(const void* body, unsigned short length, const airkiss_config_t* config);$/;"	p	signature:(const void* body, unsigned short length, const airkiss_config_t* config)
+airkiss_lan_ret_t	smartlink/airkiss-lib/airkiss.h	/^} airkiss_lan_ret_t;$/;"	t	typeref:enum:__anon27
+airkiss_lan_ret_t	smartlink/airkiss-lib/mipsel/airkiss.h	/^} airkiss_lan_ret_t;$/;"	t	typeref:enum:__anon21
+airkiss_lan_ret_t	smartlink/airkiss-lib/x64/airkiss.h	/^} airkiss_lan_ret_t;$/;"	t	typeref:enum:__anon33
+airkiss_memcmp_fn	smartlink/airkiss-lib/airkiss.h	/^typedef int (*airkiss_memcmp_fn) (const void* ptr1, const void* ptr2, unsigned int num);$/;"	t
+airkiss_memcmp_fn	smartlink/airkiss-lib/mipsel/airkiss.h	/^typedef int (*airkiss_memcmp_fn) (const void* ptr1, const void* ptr2, unsigned int num);$/;"	t
+airkiss_memcmp_fn	smartlink/airkiss-lib/x64/airkiss.h	/^typedef int (*airkiss_memcmp_fn) (const void* ptr1, const void* ptr2, unsigned int num);$/;"	t
+airkiss_memcpy_fn	smartlink/airkiss-lib/airkiss.h	/^typedef void* (*airkiss_memcpy_fn) (void* dst, const void* src, unsigned int num);$/;"	t
+airkiss_memcpy_fn	smartlink/airkiss-lib/mipsel/airkiss.h	/^typedef void* (*airkiss_memcpy_fn) (void* dst, const void* src, unsigned int num);$/;"	t
+airkiss_memcpy_fn	smartlink/airkiss-lib/x64/airkiss.h	/^typedef void* (*airkiss_memcpy_fn) (void* dst, const void* src, unsigned int num);$/;"	t
+airkiss_memset_fn	smartlink/airkiss-lib/airkiss.h	/^typedef void* (*airkiss_memset_fn) (void* ptr, int value, unsigned int num);$/;"	t
+airkiss_memset_fn	smartlink/airkiss-lib/mipsel/airkiss.h	/^typedef void* (*airkiss_memset_fn) (void* ptr, int value, unsigned int num);$/;"	t
+airkiss_memset_fn	smartlink/airkiss-lib/x64/airkiss.h	/^typedef void* (*airkiss_memset_fn) (void* ptr, int value, unsigned int num);$/;"	t
+airkiss_printf_fn	smartlink/airkiss-lib/airkiss.h	/^typedef int (*airkiss_printf_fn) (const char* format, ...);$/;"	t
+airkiss_printf_fn	smartlink/airkiss-lib/mipsel/airkiss.h	/^typedef int (*airkiss_printf_fn) (const char* format, ...);$/;"	t
+airkiss_printf_fn	smartlink/airkiss-lib/x64/airkiss.h	/^typedef int (*airkiss_printf_fn) (const char* format, ...);$/;"	t
+airkiss_recv	smartlink/airkiss-lib/airkiss.h	/^int airkiss_recv(airkiss_context_t* context, const void* frame, unsigned short length);$/;"	p	signature:(airkiss_context_t* context, const void* frame, unsigned short length)
+airkiss_recv	smartlink/airkiss-lib/mipsel/airkiss.h	/^int airkiss_recv(airkiss_context_t* context, const void* frame, unsigned short length);$/;"	p	signature:(airkiss_context_t* context, const void* frame, unsigned short length)
+airkiss_recv	smartlink/airkiss-lib/x64/airkiss.h	/^int airkiss_recv(airkiss_context_t* context, const void* frame, unsigned short length);$/;"	p	signature:(airkiss_context_t* context, const void* frame, unsigned short length)
+airkiss_result_t	smartlink/airkiss-lib/airkiss.h	/^} airkiss_result_t;$/;"	t	typeref:struct:__anon25
+airkiss_result_t	smartlink/airkiss-lib/mipsel/airkiss.h	/^} airkiss_result_t;$/;"	t	typeref:struct:__anon19
+airkiss_result_t	smartlink/airkiss-lib/x64/airkiss.h	/^} airkiss_result_t;$/;"	t	typeref:struct:__anon31
+airkiss_set_key	smartlink/airkiss-lib/airkiss.h	/^int airkiss_set_key(airkiss_context_t* context, const unsigned char* key, unsigned int length);$/;"	p	signature:(airkiss_context_t* context, const unsigned char* key, unsigned int length)
+airkiss_set_key	smartlink/airkiss-lib/mipsel/airkiss.h	/^int airkiss_set_key(airkiss_context_t* context, const unsigned char* key, unsigned int length);$/;"	p	signature:(airkiss_context_t* context, const unsigned char* key, unsigned int length)
+airkiss_set_key	smartlink/airkiss-lib/x64/airkiss.h	/^int airkiss_set_key(airkiss_context_t* context, const unsigned char* key, unsigned int length);$/;"	p	signature:(airkiss_context_t* context, const unsigned char* key, unsigned int length)
+airkiss_status_t	smartlink/airkiss-lib/airkiss.h	/^} airkiss_status_t;$/;"	t	typeref:enum:__anon26
+airkiss_status_t	smartlink/airkiss-lib/mipsel/airkiss.h	/^} airkiss_status_t;$/;"	t	typeref:enum:__anon20
+airkiss_status_t	smartlink/airkiss-lib/x64/airkiss.h	/^} airkiss_status_t;$/;"	t	typeref:enum:__anon32
+airkiss_version	smartlink/airkiss-lib/airkiss.h	/^const char* airkiss_version(void);$/;"	p	signature:(void)
+airkiss_version	smartlink/airkiss-lib/mipsel/airkiss.h	/^const char* airkiss_version(void);$/;"	p	signature:(void)
+airkiss_version	smartlink/airkiss-lib/x64/airkiss.h	/^const char* airkiss_version(void);$/;"	p	signature:(void)
+akconf	smartlink/airkiss.c	/^const airkiss_config_t akconf =$/;"	v
+akcontex	smartlink/airkiss.c	/^airkiss_context_t akcontex;$/;"	v
+alg	crypto/sha1_glue.c	/^static struct shash_alg alg = {$/;"	v	typeref:struct:shash_alg	file:
+align2	include/ssv6200_common.h	/^    u32 align2:1;$/;"	m	struct:ssv6200_rx_desc	access:public
+alloc_hw	smac/dev.h	/^    struct ssv_hw * (*alloc_hw)(void);$/;"	m	struct:ssv_hal_ops	typeref:struct:ssv_hal_ops::alloc_hw	access:public
+alloc_pbuf	smac/dev.h	/^    u32 (*alloc_pbuf)(struct ssv_softc *sc, int size, int type);$/;"	m	struct:ssv_hal_ops	access:public
+am	smac/dev.h	/^    u32 am[MAX_PADPD_TONE\/2];$/;"	m	struct:ssv6006dpd	access:public
+am	smac/hal/ssv6006c/turismo_common.h	/^    u32 am[MAX_PADPD_TONE\/2];$/;"	m	struct:ssv6006dpd	access:public
+am_mask	smac/hal/ssv6006c/turismo_common.c	/^const u32 am_mask[2] = {0xfffffc00,0xfc00ffff};$/;"	v
+ampdu_ack_len	include/ssv6200_common.h	/^    u16 ampdu_ack_len;$/;"	m	struct:firmware_rate_control_report_data	access:public
+ampdu_ack_len	smac/ssv_rc_minstrel_ht.h	/^ int ampdu_ack_len;$/;"	m	struct:ssv_minstrel_ampdu_rate_rpt	access:public
+ampdu_auto_crc_en	smac/dev.h	/^    void (*ampdu_auto_crc_en)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ampdu_ba_handler	smac/dev.h	/^    void (*ampdu_ba_handler)(struct ieee80211_hw *hw, struct sk_buff *skb, u32 tx_pkt_run_no);$/;"	m	struct:ssv_hal_ops	access:public
+ampdu_ba_notify_data	include/ssv6200_common.h	/^struct ampdu_ba_notify_data {$/;"	s
+ampdu_ba_notify_data::seq_no	include/ssv6200_common.h	/^    u16 seq_no[MAX_AGGR_NUM];$/;"	m	struct:ampdu_ba_notify_data	access:public
+ampdu_ba_notify_data::tried_rates	include/ssv6200_common.h	/^    struct ssv62xx_tx_rate tried_rates[SSV62XX_TX_MAX_RATES];$/;"	m	struct:ampdu_ba_notify_data	typeref:struct:ampdu_ba_notify_data::ssv62xx_tx_rate	access:public
+ampdu_ba_notify_data::wsid	include/ssv6200_common.h	/^    u8 wsid;$/;"	m	struct:ampdu_ba_notify_data	access:public
+ampdu_db_log	smac/ampdu.h	193;"	d
+ampdu_db_log	smac/ampdu.h	196;"	d
+ampdu_db_log_simple	smac/ampdu.h	194;"	d
+ampdu_db_log_simple	smac/ampdu.h	197;"	d
+ampdu_divider	smac/dev.h	/^    u32 ampdu_divider;$/;"	m	struct:ssv_hw	access:public
+ampdu_dmydelimiter_num	smac/hal/ssv6006c/turismo_common.h	/^    u32 ampdu_dmydelimiter_num:4;$/;"	m	struct:ssv6006_tx_desc	access:public
+ampdu_fw_rate_info_status_in_use	smac/drv_comm.h	22;"	d
+ampdu_fw_rate_info_status_no_use	smac/drv_comm.h	21;"	d
+ampdu_fw_rate_info_status_reset	smac/drv_comm.h	23;"	d
+ampdu_hdr_ssn	smac/dev.h	93;"	d
+ampdu_hdr_st	smac/ssv_skb.h	/^struct ampdu_hdr_st$/;"	s
+ampdu_hdr_st::ampdu_tid	smac/ssv_skb.h	/^    struct AMPDU_TID_st *ampdu_tid;$/;"	m	struct:ampdu_hdr_st	typeref:struct:ampdu_hdr_st::AMPDU_TID_st	access:public
+ampdu_hdr_st::first_sn	smac/ssv_skb.h	/^    u32 first_sn;$/;"	m	struct:ampdu_hdr_st	access:public
+ampdu_hdr_st::max_size	smac/ssv_skb.h	/^    u32 max_size;$/;"	m	struct:ampdu_hdr_st	access:public
+ampdu_hdr_st::mpdu_num	smac/ssv_skb.h	/^    u16 mpdu_num;$/;"	m	struct:ampdu_hdr_st	access:public
+ampdu_hdr_st::mpdu_q	smac/ssv_skb.h	/^    struct sk_buff_head mpdu_q;$/;"	m	struct:ampdu_hdr_st	typeref:struct:ampdu_hdr_st::sk_buff_head	access:public
+ampdu_hdr_st::rates	smac/ssv_skb.h	/^    struct fw_rc_retry_params rates[SSV62XX_TX_MAX_RATES];$/;"	m	struct:ampdu_hdr_st	typeref:struct:ampdu_hdr_st::fw_rc_retry_params	access:public
+ampdu_hdr_st::size	smac/ssv_skb.h	/^    u32 size;$/;"	m	struct:ampdu_hdr_st	access:public
+ampdu_hdr_st::ssn	smac/ssv_skb.h	/^    u16 ssn[MAX_AGGR_NUM];$/;"	m	struct:ampdu_hdr_st	access:public
+ampdu_hdr_st::sta	smac/ssv_skb.h	/^    struct ieee80211_sta *sta;$/;"	m	struct:ampdu_hdr_st	typeref:struct:ampdu_hdr_st::ieee80211_sta	access:public
+ampdu_last_pkt	smac/hal/ssv6006c/turismo_common.h	/^    u32 ampdu_last_pkt:1;$/;"	m	struct:ssv6006_tx_desc	access:public
+ampdu_len	include/ssv6200_common.h	/^    u16 ampdu_len;$/;"	m	struct:firmware_rate_control_report_data	access:public
+ampdu_len	smac/ssv_rc_common.h	/^    unsigned int ampdu_len;$/;"	m	struct:ssv62xx_ht	access:public
+ampdu_len	smac/ssv_rc_minstrel_ht.h	/^ int ampdu_len;$/;"	m	struct:ssv_minstrel_ampdu_rate_rpt	access:public
+ampdu_len	smac/ssv_rc_minstrel_ht.h	/^ unsigned int ampdu_len;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+ampdu_max_transmit_length	smac/ampdu.c	/^const u16 ampdu_max_transmit_length[RATE_TABLE_SIZE] =$/;"	v
+ampdu_max_transmit_length	smac/dev.h	/^    int (*ampdu_max_transmit_length)(struct ssv_softc *sc, struct sk_buff *skb, int rate_idx);$/;"	m	struct:ssv_hal_ops	access:public
+ampdu_mib_BA_counter	smac/ampdu.h	/^    u32 ampdu_mib_BA_counter;$/;"	m	struct:AMPDU_MIB_st	access:public
+ampdu_mib_aggr_retry_counter	smac/ampdu.h	/^    u32 ampdu_mib_aggr_retry_counter;$/;"	m	struct:AMPDU_MIB_st	access:public
+ampdu_mib_ampdu_counter	smac/ampdu.h	/^    u32 ampdu_mib_ampdu_counter;$/;"	m	struct:AMPDU_MIB_st	access:public
+ampdu_mib_bar_counter	smac/ampdu.h	/^    u32 ampdu_mib_bar_counter;$/;"	m	struct:AMPDU_MIB_st	access:public
+ampdu_mib_discard_counter	smac/ampdu.h	/^    u32 ampdu_mib_discard_counter;$/;"	m	struct:AMPDU_MIB_st	access:public
+ampdu_mib_dist	smac/ampdu.h	/^    u32 ampdu_mib_dist[SSV_AMPDU_aggr_num_max + 1];$/;"	m	struct:AMPDU_MIB_st	access:public
+ampdu_mib_mpdu_counter	smac/ampdu.h	/^    u32 ampdu_mib_mpdu_counter;$/;"	m	struct:AMPDU_MIB_st	access:public
+ampdu_mib_pass_counter	smac/ampdu.h	/^    u32 ampdu_mib_pass_counter;$/;"	m	struct:AMPDU_MIB_st	access:public
+ampdu_mib_reset	smac/ampdu.h	/^    u32 ampdu_mib_reset;$/;"	m	struct:AMPDU_TID_st	access:public
+ampdu_mib_retry_counter	smac/ampdu.h	/^    u32 ampdu_mib_retry_counter;$/;"	m	struct:AMPDU_MIB_st	access:public
+ampdu_mib_total_BA_counter	smac/ampdu.h	/^    u32 ampdu_mib_total_BA_counter;$/;"	m	struct:AMPDU_MIB_st	access:public
+ampdu_mib_total_BA_counter	smac/dev.h	/^    u32 ampdu_mib_total_BA_counter;$/;"	m	struct:ssv_sta_priv_data	access:public
+ampdu_next_pkt	smac/hal/ssv6006c/turismo_common.h	/^    u32 ampdu_next_pkt:8;$/;"	m	struct:ssv6006_tx_desc	access:public
+ampdu_packets	smac/ssv_rc_common.h	/^    unsigned int ampdu_packets;$/;"	m	struct:ssv62xx_ht	access:public
+ampdu_packets	smac/ssv_rc_minstrel_ht.h	/^ unsigned int ampdu_packets;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+ampdu_rpt_list	smac/ssv_rc_minstrel_ht.h	/^ struct ssv_minstrel_ampdu_rate_rpt ampdu_rpt_list[SSV_MINSTREL_AMPDU_RATE_RPTS];$/;"	m	struct:ssv_minstrel_ht_sta	typeref:struct:ssv_minstrel_ht_sta::ssv_minstrel_ampdu_rate_rpt	access:public
+ampdu_rx_start	smac/dev.h	/^    int (*ampdu_rx_start)(struct ieee80211_hw *hw, struct ieee80211_vif *vif, struct ieee80211_sta *sta,$/;"	m	struct:ssv_hal_ops	access:public
+ampdu_skb_hdr	smac/dev.h	91;"	d
+ampdu_skb_ssn	smac/dev.h	92;"	d
+ampdu_skb_tx_queue	smac/ampdu.h	/^    struct sk_buff_head ampdu_skb_tx_queue;$/;"	m	struct:AMPDU_TID_st	typeref:struct:AMPDU_TID_st::sk_buff_head	access:public
+ampdu_skb_tx_queue_lock	smac/ampdu.h	/^    spinlock_t ampdu_skb_tx_queue_lock;$/;"	m	struct:AMPDU_TID_st	access:public
+ampdu_skb_wait_encry_queue	smac/ampdu.h	/^    struct sk_buff_head ampdu_skb_wait_encry_queue;$/;"	m	struct:AMPDU_TID_st	typeref:struct:AMPDU_TID_st::sk_buff_head	access:public
+ampdu_ssn	smac/dev.h	/^    struct aggr_ssn ampdu_ssn[MAX_CONCUR_AMPDU];$/;"	m	struct:ssv_sta_priv_data	typeref:struct:ssv_sta_priv_data::aggr_ssn	access:public
+ampdu_tid	smac/dev.h	/^    AMPDU_TID ampdu_tid[WMM_TID_NUM];$/;"	m	struct:ssv_sta_priv_data	access:public
+ampdu_tid	smac/ssv_skb.h	/^    struct AMPDU_TID_st *ampdu_tid;$/;"	m	struct:ampdu_hdr_st	typeref:struct:ampdu_hdr_st::AMPDU_TID_st	access:public
+ampdu_tx_bitmap_hw	smac/hal/ssv6006c/turismo_common.h	/^    u32 ampdu_tx_bitmap_hw;$/;"	m	struct:ssv6006_tx_desc	access:public
+ampdu_tx_bitmap_lw	smac/hal/ssv6006c/turismo_common.h	/^    u32 ampdu_tx_bitmap_lw;$/;"	m	struct:ssv6006_tx_desc	access:public
+ampdu_tx_final_retry_count	smac/ssv_skb.h	/^    u16 ampdu_tx_final_retry_count;$/;"	m	struct:SKB_info_st	access:public
+ampdu_tx_frame	smac/dev.h	/^    atomic_t ampdu_tx_frame;$/;"	m	struct:ssv_softc	access:public
+ampdu_tx_group_id	smac/dev.h	/^    u16 ampdu_tx_group_id;$/;"	m	struct:ssv_tx	access:public
+ampdu_tx_mib_dump	smac/ampdu.c	/^ssize_t ampdu_tx_mib_dump (struct ssv_sta_priv_data *ssv_sta_priv,$/;"	f	signature:(struct ssv_sta_priv_data *ssv_sta_priv, char *mib_str, ssize_t length)
+ampdu_tx_mib_dump	smac/ampdu.c	/^static ssize_t ampdu_tx_mib_dump (struct ssv_sta_priv_data *ssv_sta_priv,$/;"	p	file:	signature:(struct ssv_sta_priv_data *ssv_sta_priv, char *mib_str, ssize_t length)
+ampdu_tx_mib_reset_open	smac/ampdu.c	/^static int ampdu_tx_mib_reset_open (struct inode *inode, struct file *file)$/;"	f	file:	signature:(struct inode *inode, struct file *file)
+ampdu_tx_mib_reset_read	smac/ampdu.c	/^static ssize_t ampdu_tx_mib_reset_read (struct file *file,$/;"	f	file:	signature:(struct file *file, char __user *user_buf, size_t count, loff_t *ppos)
+ampdu_tx_mib_reset_write	smac/ampdu.c	/^static ssize_t ampdu_tx_mib_reset_write (struct file *file,$/;"	f	file:	signature:(struct file *file, const char __user *buffer, size_t count, loff_t *pos)
+ampdu_tx_mib_summary_open	smac/ampdu.c	/^static int ampdu_tx_mib_summary_open (struct inode *inode, struct file *file)$/;"	f	file:	signature:(struct inode *inode, struct file *file)
+ampdu_tx_mib_summary_read	smac/ampdu.c	/^static ssize_t ampdu_tx_mib_summary_read (struct file *file,$/;"	f	file:	signature:(struct file *file, char __user *user_buf, size_t count, loff_t *ppos)
+ampdu_tx_que	smac/dev.h	/^    struct list_head ampdu_tx_que;$/;"	m	struct:ssv_tx	typeref:struct:ssv_tx::list_head	access:public
+ampdu_tx_que_lock	smac/dev.h	/^    spinlock_t ampdu_tx_que_lock;$/;"	m	struct:ssv_tx	access:public
+ampdu_tx_ssn	smac/hal/ssv6006c/turismo_common.h	/^    u32 ampdu_tx_ssn:12;$/;"	m	struct:ssv6006_tx_desc	access:public
+ampdu_tx_status	smac/ssv_skb.h	/^    u16 ampdu_tx_status;$/;"	m	struct:SKB_info_st	access:public
+ampdu_tx_tid_window_open	smac/ampdu.c	/^static int ampdu_tx_tid_window_open (struct inode *inode, struct file *file)$/;"	f	file:	signature:(struct inode *inode, struct file *file)
+ampdu_tx_tid_window_read	smac/ampdu.c	/^static ssize_t ampdu_tx_tid_window_read (struct file *file,$/;"	f	file:	signature:(struct file *file, char __user *user_buf, size_t count, loff_t *ppos)
+ampdu_whole_length	smac/hal/ssv6006c/turismo_common.h	/^    u32 ampdu_whole_length:16;$/;"	m	struct:ssv6006_tx_desc	access:public
+ap_address	smac/sec_wpi.c	/^ u8 ap_address[ETH_ALEN];$/;"	m	struct:lib80211_wpi_data	file:	access:public
+ap_deci_tbl	smac/dev.h	151;"	d
+ap_deci_tbl	smac/dev_tbl.h	/^ u16 ap_deci_tbl[] =$/;"	v
+ap_vif	smac/dev.h	/^    struct ieee80211_vif *ap_vif;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::ieee80211_vif	access:public
+app_path	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    char * app_path;$/;"	m	struct:_tx_init_path	access:public
+app_path_capicity	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    unsigned int app_path_capicity;$/;"	m	struct:_tx_init_path	access:public
+appid	smartlink/qqlink-lib-mipsel/include/TXOldInf.h	/^    unsigned int appid;$/;"	m	struct:tag_tx_ccmsg_inst_info	access:public
+arg	ssvdevice/ssv_cmd.h	/^    u32 arg;$/;"	m	struct:ssv6xxx_cfg_cmd_table	access:public
+argv	include/ssv6xxx_common.h	/^        u32 argv;$/;"	m	union:ssv6xxx_iqk_cfg::__anon47	access:public
+arith_shift	smac/ssv_rc_common.h	/^    u8 arith_shift;$/;"	m	struct:ssv_rc_rate	access:public
+asic_rf_setting	include/ssv6200_configuration.h	/^static ssv_cabrio_reg asic_rf_setting[]={$/;"	v
+att_hist	smac/ssv_rc_common.h	/^    u64 att_hist, succ_hist;$/;"	m	struct:minstrel_rate_stats	access:public
+att_hist	smac/ssv_rc_minstrel.h	/^ u64 att_hist;$/;"	m	struct:ssv_minstrel_rate	access:public
+att_hist	smac/ssv_rc_minstrel_ht.h	/^ u64 att_hist, succ_hist;$/;"	m	struct:ssv_minstrel_ht_rate_stats	access:public
+attach_device_name	umac/ssv6xxx_netlink_core.c	/^static char *attach_device_name = "SSV6XXX";$/;"	v	file:
+attach_driver_name	umac/ssv6xxx_netlink_core.c	/^static char *attach_driver_name = "SSV WLAN driver";$/;"	v	file:
+attempt	smac/ssv_rc_common.h	/^ u64 attempt;$/;"	m	struct:rc_pid_rateinfo	access:public
+attempts	smac/ssv_rc_common.h	/^    unsigned int attempts, last_attempts;$/;"	m	struct:minstrel_rate_stats	access:public
+attempts	smac/ssv_rc_minstrel.h	/^ u32 attempts;$/;"	m	struct:ssv_minstrel_rate	access:public
+attempts	smac/ssv_rc_minstrel_ht.h	/^ unsigned int attempts, last_attempts;$/;"	m	struct:ssv_minstrel_ht_rate_stats	access:public
+audio_format	smartlink/qqlink-lib-mipsel/include/TXAudioVideo.h	/^ unsigned char audio_format;$/;"	m	struct:_tx_audio_encode_param	access:public
+audio_msg_url	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^    char * audio_msg_url;$/;"	m	struct:tag_tx_audio_msg_element	access:public
+autoAckInt	bridge/sdiobridge.h	/^ u8 autoAckInt;$/;"	m	struct:ssv_sdiobridge_glue	access:public
+auto_gen_nullpkt	smac/dev.h	/^    int (*auto_gen_nullpkt)(struct ssv_hw *sh, int hwq);$/;"	m	struct:ssv_hal_ops	access:public
+auto_rate_enable	include/ssv_cfg.h	/^    u32 auto_rate_enable;$/;"	m	struct:ssv6xxx_cfg	access:public
+auto_sgi	include/ssv_cfg.h	/^    u32 auto_sgi;$/;"	m	struct:ssv6xxx_cfg	access:public
+avg_ampdu_len	smac/ssv_rc_common.h	/^    unsigned int avg_ampdu_len;$/;"	m	struct:ssv62xx_ht	access:public
+avg_ampdu_len	smac/ssv_rc_minstrel_ht.h	/^ unsigned int avg_ampdu_len;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+bScanning	smac/dev.h	/^    bool bScanning;$/;"	m	struct:ssv_softc	access:public
+ba_q	smac/ampdu.h	/^    struct sk_buff_head ba_q;$/;"	m	struct:AMPDU_TID_st	typeref:struct:AMPDU_TID_st::sk_buff_head	access:public
+ba_ra_addr	smac/dev.h	/^    u8 ba_ra_addr[ETH_ALEN];$/;"	m	struct:ssv_softc	access:public
+ba_ssn	smac/dev.h	/^    u16 ba_ssn;$/;"	m	struct:ssv_softc	access:public
+ba_tid	smac/dev.h	/^    u16 ba_tid;$/;"	m	struct:ssv_softc	access:public
+band_gain_high_boundary	smac/dev.h	/^    u8 band_gain_high_boundary;$/;"	m	struct:ssv_flash_config	access:public
+band_gain_high_boundary	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 band_gain_high_boundary;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+band_gain_low_boundary	smac/dev.h	/^    u8 band_gain_low_boundary;$/;"	m	struct:ssv_flash_config	access:public
+band_gain_low_boundary	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 band_gain_low_boundary;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+band_gain_tempe_state	smac/dev.h	/^    u8 band_gain_tempe_state;$/;"	m	struct:ssv_flash_config	access:public
+bbscale	smac/dev.h	/^    u8 bbscale[PADPDBAND];$/;"	m	struct:ssv6006_padpd	access:public
+bbscale	smac/hal/ssv6006c/turismo_common.h	/^    u8 bbscale[PADPDBAND];$/;"	m	struct:ssv6006_padpd	access:public
+bc_que	include/ssv6200_common.h	/^    u32 bc_que:1;$/;"	m	struct:ssv6200_tx_desc	access:public
+bc_que	smac/hal/ssv6006c/turismo_common.h	/^    u32 bc_que:1;$/;"	m	struct:ssv6006_tx_desc	access:public
+bcast_interval	smac/dev.h	/^    int bcast_interval;$/;"	m	struct:ssv_softc	access:public
+bcast_start_work	smac/dev.h	/^    struct work_struct bcast_start_work;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::work_struct	access:public
+bcast_stop_work	smac/dev.h	/^    struct delayed_work bcast_stop_work;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::delayed_work	access:public
+bcast_tx_work	smac/dev.h	/^    struct delayed_work bcast_tx_work;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::delayed_work	access:public
+bcast_txq	smac/dev.h	/^    struct ssv6xxx_bcast_txq bcast_txq;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::ssv6xxx_bcast_txq	access:public
+be_txq_size	include/ssv6xxx_common.h	/^ u32 be_txq_size;$/;"	m	struct:ssv6xxx_tx_hw_info	access:public
+be_txq_size	include/ssv_cfg.h	/^    u32 be_txq_size;$/;"	m	struct:ssv6xxx_cfg	access:public
+beacon_buf	smac/dev.h	/^    struct sk_buff *beacon_buf;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::sk_buff	access:public
+beacon_container	smac/dev.h	/^    struct sk_buff *beacon_container;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::sk_buff	access:public
+beacon_container_update_time	smac/dev.h	/^    unsigned long beacon_container_update_time;$/;"	m	struct:ssv_softc	access:public
+beacon_dtim_cnt	smac/dev.h	/^    u8 beacon_dtim_cnt;$/;"	m	struct:ssv_softc	access:public
+beacon_enable	smac/dev.h	/^    bool (*beacon_enable)(struct ssv_softc *sc, bool bEnable);$/;"	m	struct:ssv_hal_ops	access:public
+beacon_get_valid_cfg	smac/dev.h	/^    enum ssv6xxx_beacon_type (*beacon_get_valid_cfg)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	typeref:enum:ssv_hal_ops::beacon_get_valid_cfg	access:public
+beacon_info	smac/dev.h	/^    struct ssv6xxx_beacon_info beacon_info[2];$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::ssv6xxx_beacon_info	access:public
+beacon_interval	smac/dev.h	/^    u8 beacon_interval;$/;"	m	struct:ssv_softc	access:public
+beacon_loss_config	smac/dev.h	/^ void (*beacon_loss_config)(struct ssv_hw *sh, u16 beacon_interval, const u8 *bssid);$/;"	m	struct:ssv_hal_ops	access:public
+beacon_loss_disable	smac/dev.h	/^ void (*beacon_loss_disable)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+beacon_loss_enable	smac/dev.h	/^ void (*beacon_loss_enable)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+beacon_miss_work	smac/dev.h	/^    struct work_struct beacon_miss_work;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::work_struct	access:public
+beacon_rssi	smac/dev.h	/^    u32 beacon_rssi;$/;"	m	struct:ssv_sta_priv_data	access:public
+beacon_rssi_minimal	include/ssv_cfg.h	/^    u32 beacon_rssi_minimal;$/;"	m	struct:ssv6xxx_cfg	access:public
+beacon_usage	smac/dev.h	/^    u8 beacon_usage;$/;"	m	struct:ssv_softc	access:public
+binder_gender_female	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^ binder_gender_female = 1,$/;"	e	enum:tx_binder_gender
+binder_gender_male	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^ binder_gender_male = 0,$/;"	e	enum:tx_binder_gender
+binder_gender_unknown	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^ binder_gender_unknown = -1,$/;"	e	enum:tx_binder_gender
+binder_type_owner	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^ binder_type_owner = 1,$/;"	e	enum:tx_binder_type
+binder_type_sharer	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^ binder_type_sharer = 2,$/;"	e	enum:tx_binder_type
+binder_type_unknown	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^ binder_type_unknown = 0,$/;"	e	enum:tx_binder_type
+bitrate	smac/ssv_rc_minstrel.h	/^ int bitrate;$/;"	m	struct:ssv_minstrel_rate	access:public
+bits_per_symbol	smac/dev.c	/^static u16 bits_per_symbol[][2] =$/;"	v	file:
+bk_txq_size	include/ssv6xxx_common.h	/^ u32 bk_txq_size;$/;"	m	struct:ssv6xxx_tx_hw_info	access:public
+bk_txq_size	include/ssv_cfg.h	/^    u32 bk_txq_size;$/;"	m	struct:ssv6xxx_cfg	access:public
+blockMode	bridge/sdiobridge.h	/^ u8 blockMode;$/;"	m	struct:ssv_sdiobridge_glue	access:public
+blockSize	bridge/sdiobridge.h	/^ u16 blockSize;$/;"	m	struct:ssv_sdiobridge_glue	access:public
+bool	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	20;"	d
+bq4_dtim	smac/dev.h	/^    bool bq4_dtim;$/;"	m	struct:ssv_softc	access:public
+bss_group	smac/hal/ssv6006c/ssv6006_mac.h	/^    struct ssv6006_bss bss_group[2];$/;"	m	struct:ssv6006_hw_sec	typeref:struct:ssv6006_hw_sec::ssv6006_bss	access:public
+bssid	smac/dev.h	/^    u8 bssid[2][6];$/;"	m	struct:ssv_softc	access:public
+bssid	smac/hal/ssv6006c/turismo_common.h	/^    u32 bssid:2;$/;"	m	struct:ssv6006_rx_desc	access:public
+bssidx	smac/hal/ssv6006c/turismo_common.h	/^    u32 bssidx:2;$/;"	m	struct:ssv6006_tx_desc	access:public
+buf	hwif/sdio/sdio_def.h	/^ u8 *buf;$/;"	m	struct:sdio_scatter_item	access:public
+buf	smac/ssv_rc_minstrel.h	/^ char buf[];$/;"	m	struct:ssv_minstrel_debugfs_info	access:public
+buf	smartlink/ssv_smartlink.c	/^    char buf[MAX_PAYLOAD];$/;"	m	struct:netlink_msg	file:	access:public
+bufaddr	bridge/sdiobridge.h	/^    void *bufaddr;$/;"	m	struct:ssv_sdiobridge_glue	access:public
+bufaddr	hci_wrapper/ssv_huw.c	/^    void *bufaddr;$/;"	m	struct:ssv_huw_dev	file:	access:public
+buff	hwif/usb/usb.h	/^ void *buff;$/;"	m	struct:ssv6xxx_cmd_endpoint	access:public
+buff_length	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^    int buff_length;$/;"	m	struct:tag_tx_file_transfer_info	access:public
+buff_size	smac/ampdu.c	/^    size_t buff_size;$/;"	m	struct:mib_dump_data	file:	access:public
+buff_with_file	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^    char * buff_with_file;$/;"	m	struct:tag_tx_file_transfer_info	access:public
+buffer_key	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^    char buffer_key[512];$/;"	m	struct:tag_tx_file_transfer_info	access:public
+buffer_key_len	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^    int buffer_key_len;$/;"	m	struct:tag_tx_file_transfer_info	access:public
+buffer_raw	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^    char * buffer_raw;$/;"	m	struct:tag_tx_file_transfer_info	access:public
+buffer_raw_len	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^    unsigned long long buffer_raw_len;$/;"	m	struct:tag_tx_file_transfer_info	access:public
+burst_read_reg	smac/dev.h	/^    int (*burst_read_reg)(struct ssv_hw *sh, u32 *addr, u32 *buf, u8 reg_amount);$/;"	m	struct:ssv_hal_ops	access:public
+burst_readreg	hwif/hwif.h	/^    int __must_check (*burst_readreg)(struct device *child, u32 *addr, u32 *buf, u8 reg_amount);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+burst_safe_readreg	hwif/hwif.h	/^    int __must_check (*burst_safe_readreg)(struct device *child, u32 *addr, u32 *buf, u8 reg_amount);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+burst_safe_writereg	hwif/hwif.h	/^    int __must_check (*burst_safe_writereg)(struct device *child, u32 *addr, u32 *buf, u8 reg_amount);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+burst_write_reg	smac/dev.h	/^    int (*burst_write_reg)(struct ssv_hw *sh, u32 *addr, u32 *buf, u8 reg_amount);$/;"	m	struct:ssv_hal_ops	access:public
+burst_writereg	hwif/hwif.h	/^    int __must_check (*burst_writereg)(struct device *child, u32 *addr, u32 *buf, u8 reg_amount);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+bussiness_name	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^    char bussiness_name[64];$/;"	m	struct:tag_tx_file_transfer_info	access:public
+byte_cnts	smac/efuse.h	/^    u8 byte_cnts;$/;"	m	struct:efuse_map	access:public
+c_flags	smac/ssv_rc_common.h	/^    u32 c_flags;$/;"	m	struct:ssv_rate_info	access:public
+c_type	include/ssv6200_common.h	/^    u32 c_type:3;$/;"	m	struct:ssv6200_rx_desc	access:public
+c_type	include/ssv6200_common.h	/^    u32 c_type:3;$/;"	m	struct:ssv6200_tx_desc	access:public
+c_type	include/ssv6xxx_common.h	/^    u32 c_type :3;$/;"	m	struct:cfg_host_event	access:public
+c_type	include/ssv6xxx_common.h	/^    u32 c_type:3;$/;"	m	struct:cfg_host_cmd	access:public
+c_type	smac/hal/ssv6006c/turismo_common.h	/^    u32 c_type:3;$/;"	m	struct:ssv6006_rx_desc	access:public
+c_type	smac/hal/ssv6006c/turismo_common.h	/^    u32 c_type:3;$/;"	m	struct:ssv6006_tx_desc	access:public
+cabrio_sdio_pm_check	hwif/sdio/sdio.c	/^static int cabrio_sdio_pm_check(struct sdio_func *func)$/;"	f	file:	signature:(struct sdio_func *func)
+cal	smac/dev.h	/^    struct ssv6006_cal_result cal;$/;"	m	struct:ssv_hw	typeref:struct:ssv_hw::ssv6006_cal_result	access:public
+cal_ch_5g	smac/hal/ssv6006c/turismo_common.c	/^const int cal_ch_5g[4] = { 36, 40, 100, 140};$/;"	v
+cal_done	smac/dev.h	/^    bool cal_done;$/;"	m	struct:ssv6006_cal_result	access:public
+cal_done	smac/hal/ssv6006c/turismo_common.h	/^    bool cal_done;$/;"	m	struct:ssv6006_cal_result	access:public
+cal_duration_of_ampdu	smac/ampdu.c	/^unsigned int cal_duration_of_ampdu(struct sk_buff *ampdu_skb, int stage)$/;"	f	signature:(struct sk_buff *ampdu_skb, int stage)
+cal_duration_of_ampdu	smac/dev.c	/^extern unsigned int cal_duration_of_ampdu(struct sk_buff *ampdu_skb, int stage);$/;"	p	file:	signature:(struct sk_buff *ampdu_skb, int stage)
+cal_duration_of_mpdu	smac/dev.c	/^unsigned int cal_duration_of_mpdu(struct sk_buff *mpdu_skb)$/;"	f	signature:(struct sk_buff *mpdu_skb)
+cal_iq_done	smac/dev.h	/^    bool cal_iq_done[PADPDBAND];$/;"	m	struct:ssv6006_cal_result	access:public
+cal_iq_done	smac/hal/ssv6006c/turismo_common.h	/^    bool cal_iq_done[PADPDBAND];$/;"	m	struct:ssv6006_cal_result	access:public
+cb_on_control_rotate	smartlink/qqlink-lib-mipsel/case/ipcamera/ipcrotate.c	/^int cb_on_control_rotate(int rotate_direction, int rotate_degree)$/;"	f	signature:(int rotate_direction, int rotate_degree)
+cb_on_control_rotate	smartlink/qqlink-lib-mipsel/case/ipcamera/main.c	/^extern int cb_on_control_rotate(int rotate_direction, int rotate_degree);$/;"	p	file:	signature:(int rotate_direction, int rotate_degree)
+cb_on_download_complete	smartlink/qqlink-lib-mipsel/case/ipcamera/main.c	/^extern void cb_on_download_complete(int ret_code);$/;"	p	file:	signature:(int ret_code)
+cb_on_download_complete	smartlink/qqlink-lib-mipsel/case/ipcamera/ota.c	/^void cb_on_download_complete(int ret_code)$/;"	f	signature:(int ret_code)
+cb_on_download_progress	smartlink/qqlink-lib-mipsel/case/ipcamera/main.c	/^extern void cb_on_download_progress(unsigned long long download_size, unsigned long long total_size);$/;"	p	file:	signature:(unsigned long long download_size, unsigned long long total_size)
+cb_on_download_progress	smartlink/qqlink-lib-mipsel/case/ipcamera/ota.c	/^void cb_on_download_progress(unsigned long long download_size, unsigned long long total_size)$/;"	f	signature:(unsigned long long download_size, unsigned long long total_size)
+cb_on_new_pkg_come	smartlink/qqlink-lib-mipsel/case/ipcamera/main.c	/^extern int cb_on_new_pkg_come(unsigned long long from, unsigned long long pkg_size, const char * title, const char * desc, unsigned int target_version);$/;"	p	file:	signature:(unsigned long long from, unsigned long long pkg_size, const char * title, const char * desc, unsigned int target_version)
+cb_on_new_pkg_come	smartlink/qqlink-lib-mipsel/case/ipcamera/ota.c	/^int cb_on_new_pkg_come(unsigned long long from, unsigned long long pkg_size, const char * title, const char * desc, unsigned int target_version)$/;"	f	signature:(unsigned long long from, unsigned long long pkg_size, const char * title, const char * desc, unsigned int target_version)
+cb_on_recv_file	smartlink/qqlink-lib-mipsel/case/ipcamera/audiofile.c	/^void cb_on_recv_file(unsigned long long transfer_cookie, const tx_ccmsg_inst_info * inst_info, const tx_file_transfer_info * tran_info)$/;"	f	signature:(unsigned long long transfer_cookie, const tx_ccmsg_inst_info * inst_info, const tx_file_transfer_info * tran_info)
+cb_on_recv_file	smartlink/qqlink-lib-mipsel/case/ipcamera/main.c	/^extern void cb_on_recv_file(unsigned long long transfer_cookie, const tx_ccmsg_inst_info * inst_info, const tx_file_transfer_info * tran_info);$/;"	p	file:	signature:(unsigned long long transfer_cookie, const tx_ccmsg_inst_info * inst_info, const tx_file_transfer_info * tran_info)
+cb_on_set_definition	smartlink/qqlink-lib-mipsel/case/ipcamera/ipcrotate.c	/^int cb_on_set_definition(int definition, char *cur_definition, int cur_definition_length)$/;"	f	signature:(int definition, char *cur_definition, int cur_definition_length)
+cb_on_set_definition	smartlink/qqlink-lib-mipsel/case/ipcamera/main.c	/^extern int cb_on_set_definition(int definition, char *cur_definition, int cur_definition_length);$/;"	p	file:	signature:(int definition, char *cur_definition, int cur_definition_length)
+cb_on_transfer_complete	smartlink/qqlink-lib-mipsel/case/ipcamera/audiofile.c	/^void cb_on_transfer_complete(unsigned long long transfer_cookie, int err_code, tx_file_transfer_info* tran_info)$/;"	f	signature:(unsigned long long transfer_cookie, int err_code, tx_file_transfer_info* tran_info)
+cb_on_transfer_complete	smartlink/qqlink-lib-mipsel/case/ipcamera/main.c	/^extern void cb_on_transfer_complete(unsigned long long transfer_cookie, int err_code, tx_file_transfer_info* tran_info);$/;"	p	file:	signature:(unsigned long long transfer_cookie, int err_code, tx_file_transfer_info* tran_info)
+cb_on_transfer_progress	smartlink/qqlink-lib-mipsel/case/ipcamera/audiofile.c	/^void cb_on_transfer_progress(unsigned long long transfer_cookie, unsigned long long transfer_progress, unsigned long long max_transfer_progress)$/;"	f	signature:(unsigned long long transfer_cookie, unsigned long long transfer_progress, unsigned long long max_transfer_progress)
+cb_on_transfer_progress	smartlink/qqlink-lib-mipsel/case/ipcamera/main.c	/^extern void cb_on_transfer_progress(unsigned long long transfer_cookie, unsigned long long transfer_progress, unsigned long long max_transfer_progress);$/;"	p	file:	signature:(unsigned long long transfer_cookie, unsigned long long transfer_progress, unsigned long long max_transfer_progress)
+cb_on_update_confirm	smartlink/qqlink-lib-mipsel/case/ipcamera/main.c	/^extern void cb_on_update_confirm();$/;"	p	file:
+cb_on_update_confirm	smartlink/qqlink-lib-mipsel/case/ipcamera/ota.c	/^void cb_on_update_confirm()$/;"	f
+cci	include/ssv_cfg.h	/^    u32 cci;$/;"	m	struct:ssv6xxx_cfg	access:public
+cci_clean_work	smac/dev.h	/^    struct work_struct cci_clean_work;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::work_struct	access:public
+cci_current_gate	smac/dev.h	/^    u32 cci_current_gate;$/;"	m	struct:ssv_softc	access:public
+cci_current_level	smac/dev.h	/^    u32 cci_current_level;$/;"	m	struct:ssv_softc	access:public
+cci_last_jiffies	smac/dev.h	/^    unsigned long cci_last_jiffies;$/;"	m	struct:ssv_softc	access:public
+cci_modified	smac/dev.h	/^    bool cci_modified;$/;"	m	struct:ssv_softc	access:public
+cci_rx_unavailable_counter	smac/dev.h	/^    u8 cci_rx_unavailable_counter;$/;"	m	struct:ssv_softc	access:public
+cci_set	smac/dev.h	/^    bool cci_set;$/;"	m	struct:ssv_softc	access:public
+cci_set_work	smac/dev.h	/^    struct work_struct cci_set_work;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::work_struct	access:public
+cci_start	smac/dev.h	/^    bool cci_start;$/;"	m	struct:ssv_softc	access:public
+cck_pkts	smac/dev.h	/^    u64 cck_pkts[4];$/;"	m	struct:rx_stats	access:public
+cck_rates	smac/ssv_rc_minstrel.h	/^    u8 cck_rates[4];$/;"	m	struct:ssv_minstrel_priv	access:public
+cck_supported	smac/ssv_rc_minstrel_ht.h	/^    u8 cck_supported;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+cck_supported_short	smac/ssv_rc_minstrel_ht.h	/^    u8 cck_supported_short;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+ccmp_h_sel	smac/dev.h	/^    bool ccmp_h_sel;$/;"	m	struct:ssv_softc	access:public
+ccmp_init_blocks	smac/sec_ccmp.c	/^static void ccmp_init_blocks(struct crypto_cipher *tfm,$/;"	f	file:	signature:(struct crypto_cipher *tfm, struct ieee80211_hdr *hdr, u8 * pn, size_t dlen, u8 * b0, u8 * auth, u8 * s0)
+ccmp_replay_check	smac/sec_ccmp.c	/^static inline int ccmp_replay_check(u8 *pn_n, u8 *pn_o)$/;"	f	file:	signature:(u8 *pn_n, u8 *pn_o)
+cfg	smac/dev.h	/^    struct ssv6xxx_cfg cfg;$/;"	m	struct:ssv_hw	typeref:struct:ssv_hw::ssv6xxx_cfg	access:public
+cfg_cmd	ssvdevice/ssv_cmd.h	/^    u8 *cfg_cmd;$/;"	m	struct:ssv6xxx_cfg_cmd_table	access:public
+cfg_cmds	ssvdevice/ssv_cmd.c	/^EXPORT_SYMBOL(cfg_cmds);$/;"	v
+cfg_cmds	ssvdevice/ssv_cmd.c	/^struct ssv6xxx_cfg_cmd_table cfg_cmds[] = {$/;"	v	typeref:struct:ssv6xxx_cfg_cmd_table
+cfg_def_tx_scale_11b	include/ssv6xxx_common.h	/^    u32 cfg_def_tx_scale_11b :8;$/;"	m	struct:ssv6xxx_iqk_cfg	access:public
+cfg_def_tx_scale_11b_p0d5	include/ssv6xxx_common.h	/^    u32 cfg_def_tx_scale_11b_p0d5 :8;$/;"	m	struct:ssv6xxx_iqk_cfg	access:public
+cfg_def_tx_scale_11g	include/ssv6xxx_common.h	/^    u32 cfg_def_tx_scale_11g :8;$/;"	m	struct:ssv6xxx_iqk_cfg	access:public
+cfg_def_tx_scale_11g_p0d5	include/ssv6xxx_common.h	/^    u32 cfg_def_tx_scale_11g_p0d5 :8;$/;"	m	struct:ssv6xxx_iqk_cfg	access:public
+cfg_host_cmd	include/ssv6xxx_common.h	/^typedef struct cfg_host_cmd {$/;"	s
+cfg_host_cmd::RSVD0	include/ssv6xxx_common.h	/^    u32 RSVD0:5;$/;"	m	struct:cfg_host_cmd	access:public
+cfg_host_cmd::__anon43::dat16	include/ssv6xxx_common.h	/^    u16 dat16[0];$/;"	m	union:cfg_host_cmd::__anon43	access:public
+cfg_host_cmd::__anon43::dat32	include/ssv6xxx_common.h	/^    u32 dat32[0];$/;"	m	union:cfg_host_cmd::__anon43	access:public
+cfg_host_cmd::__anon43::dat8	include/ssv6xxx_common.h	/^    u8 dat8[0];$/;"	m	union:cfg_host_cmd::__anon43	access:public
+cfg_host_cmd::__anon43::dummy	include/ssv6xxx_common.h	/^    u32 dummy;$/;"	m	union:cfg_host_cmd::__anon43	access:public
+cfg_host_cmd::c_type	include/ssv6xxx_common.h	/^    u32 c_type:3;$/;"	m	struct:cfg_host_cmd	access:public
+cfg_host_cmd::cmd_seq_no	include/ssv6xxx_common.h	/^    u32 cmd_seq_no;$/;"	m	struct:cfg_host_cmd	access:public
+cfg_host_cmd::h_cmd	include/ssv6xxx_common.h	/^    u32 h_cmd:8;$/;"	m	struct:cfg_host_cmd	access:public
+cfg_host_cmd::len	include/ssv6xxx_common.h	/^    u32 len:16;$/;"	m	struct:cfg_host_cmd	access:public
+cfg_host_event	include/ssv6xxx_common.h	/^typedef struct cfg_host_event {$/;"	s
+cfg_host_event::RSVD0	include/ssv6xxx_common.h	/^    u32 RSVD0 :5;$/;"	m	struct:cfg_host_event	access:public
+cfg_host_event::c_type	include/ssv6xxx_common.h	/^    u32 c_type :3;$/;"	m	struct:cfg_host_event	access:public
+cfg_host_event::dat	include/ssv6xxx_common.h	/^    u8 dat[0];$/;"	m	struct:cfg_host_event	access:public
+cfg_host_event::evt_seq_no	include/ssv6xxx_common.h	/^    u32 evt_seq_no;$/;"	m	struct:cfg_host_event	access:public
+cfg_host_event::h_event	include/ssv6xxx_common.h	/^    u32 h_event :8;$/;"	m	struct:cfg_host_event	access:public
+cfg_host_event::len	include/ssv6xxx_common.h	/^    u32 len :16;$/;"	m	struct:cfg_host_event	access:public
+cfg_pa	include/ssv6xxx_common.h	/^    u32 cfg_pa :8;$/;"	m	struct:ssv6xxx_iqk_cfg	access:public
+cfg_pabias_ctrl	include/ssv6xxx_common.h	/^    u32 cfg_pabias_ctrl :8;$/;"	m	struct:ssv6xxx_iqk_cfg	access:public
+cfg_pacascode_ctrl	include/ssv6xxx_common.h	/^    u32 cfg_pacascode_ctrl :8;$/;"	m	struct:ssv6xxx_iqk_cfg	access:public
+cfg_tssi_div	include/ssv6xxx_common.h	/^    u32 cfg_tssi_div :8;$/;"	m	struct:ssv6xxx_iqk_cfg	access:public
+cfg_tssi_trgt	include/ssv6xxx_common.h	/^    u32 cfg_tssi_trgt :8;$/;"	m	struct:ssv6xxx_iqk_cfg	access:public
+cfg_xtal	include/ssv6xxx_common.h	/^    u32 cfg_xtal :8;$/;"	m	struct:ssv6xxx_iqk_cfg	access:public
+cfgfirmwarepath	ssvdevice/ssvdevice.c	/^EXPORT_SYMBOL(cfgfirmwarepath);$/;"	v
+cfgfirmwarepath	ssvdevice/ssvdevice.c	/^char *cfgfirmwarepath = NULL;$/;"	v
+cflags	Makefile	/^	env ccflags="$(ccflags-y)" .\/genconf.sh $@$/;"	m
+ch13_14_value	include/ssv6xxx_common.h	/^ u32 ch13_14_value;$/;"	m	struct:ssv6xxx_ch_cfg	access:public
+ch1_12_value	include/ssv6xxx_common.h	/^ u32 ch1_12_value;$/;"	m	struct:ssv6xxx_ch_cfg	access:public
+ch_bw	include/ssv6200_common.h	/^    u32 ch_bw:3;$/;"	m	struct:ssv6200_rxphy_info	access:public
+ch_cfg_p	smac/init.c	/^struct ssv6xxx_ch_cfg ch_cfg_p[] = {$/;"	v	typeref:struct:ssv6xxx_ch_cfg
+ch_cfg_size	smac/dev.h	/^    u32 ch_cfg_size;$/;"	m	struct:ssv_hw	access:public
+ch_cfg_z	smac/init.c	/^struct ssv6xxx_ch_cfg ch_cfg_z[] = {$/;"	v	typeref:struct:ssv6xxx_ch_cfg
+chan	smac/dev.h	/^    int chan;$/;"	m	struct:ssv_flash_config	access:public
+channel	smac/hal/ssv6006c/turismo_common.h	/^    u32 channel:8;$/;"	m	struct:ssv6006_rx_desc	access:public
+channel_center_freq	smac/dev.h	/^    u16 channel_center_freq;$/;"	m	struct:ssv_softc	access:public
+channel_id	smac/dev.h	/^    u16 channel_id;$/;"	m	struct:ssv6xxx_calib_table	access:public
+channel_type	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^    int channel_type;$/;"	m	struct:tag_tx_file_transfer_info	access:public
+check	ap_check.sh	/^check()$/;"	f
+check_dhcp_server_config	ap_check.sh	/^check_dhcp_server_config(){$/;"	f
+check_package	ap_check.sh	/^check_package(){	$/;"	f
+chg_clk_src	smac/dev.h	/^    int (*chg_clk_src)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+chg_ipd_phyinfo	smac/dev.h	/^    void (*chg_ipd_phyinfo)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+chg_pad_setting	smac/dev.h	/^    int (*chg_pad_setting)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+chip_id	hci_wrapper/ssv_huw.c	/^    char chip_id[24];$/;"	m	struct:ssv_huw_dev	file:	access:public
+chip_id	hwif/hwif.h	/^    u8 chip_id[SSV6XXX_CHIP_ID_LENGTH];$/;"	m	struct:ssv6xxx_platform_data	access:public
+chip_id	smac/dev.h	/^    char chip_id[SSV6XXX_CHIP_ID_LENGTH];$/;"	m	struct:ssv_hw	access:public
+chip_identity	include/ssv_cfg.h	/^    u32 chip_identity;$/;"	m	struct:ssv6xxx_cfg	access:public
+chip_tag	hci_wrapper/ssv_huw.c	/^    u64 chip_tag;$/;"	m	struct:ssv_huw_dev	file:	access:public
+chip_tag	smac/dev.h	/^    u64 chip_tag;$/;"	m	struct:ssv_hw	access:public
+chk_dual_vif_chg_rx_flow	smac/dev.h	/^    void (*chk_dual_vif_chg_rx_flow)(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv);$/;"	m	struct:ssv_hal_ops	access:public
+chk_if_support_hw_bssid	smac/dev.h	/^    bool (*chk_if_support_hw_bssid)(struct ssv_softc *sc, int vif_idx);$/;"	m	struct:ssv_hal_ops	access:public
+chk_lpbk_rx_rate_desc	smac/dev.h	/^    int (*chk_lpbk_rx_rate_desc)(struct ssv_hw *sh, struct sk_buff *skb);$/;"	m	struct:ssv_hal_ops	access:public
+cli_count	smac/dev.h	/^ atomic_t cli_count;$/;"	m	struct:ssv_cmd_data	access:public
+clk_src_80m	include/ssv_cfg.h	/^    bool clk_src_80m;$/;"	m	struct:ssv6xxx_cfg	access:public
+closeFile	smac/efuse.c	/^int closeFile(struct file *fp)$/;"	f	signature:(struct file *fp)
+cmd	hwif/usb/usb.h	/^ u8 cmd;$/;"	m	struct:ssv6xxx_cmd_hdr	access:public
+cmd	include/ssv6xxx_common.h	/^    u8 cmd;$/;"	m	struct:ssv6xxx_wsid_params	access:public
+cmd	ssvdevice/ssv_cmd.h	/^    const char *cmd;$/;"	m	struct:ssv_cmd_table	access:public
+cmd52_read	hwif/hwif.h	/^    int (*cmd52_read)(struct device *child, u32 addr, u32 *value);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+cmd52_write	hwif/hwif.h	/^    int (*cmd52_write)(struct device *child, u32 addr, u32 value);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+cmd_cali	smac/dev.h	/^    void (*cmd_cali)(struct ssv_hw *sh, int argc, char *argv[]);$/;"	m	struct:ssv_hal_ops	access:public
+cmd_cci	smac/dev.h	/^    void (*cmd_cci)(struct ssv_hw *sh, int argc, char *argv[]);$/;"	m	struct:ssv_hal_ops	access:public
+cmd_data	smac/dev.h	/^    struct ssv_cmd_data cmd_data;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::ssv_cmd_data	access:public
+cmd_efuse	smac/dev.h	/^    void (*cmd_efuse)(struct ssv_hw *sh, int argc, char *argv[]);$/;"	m	struct:ssv_hal_ops	access:public
+cmd_endpoint	hwif/usb/usb.c	/^ struct ssv6xxx_cmd_endpoint cmd_endpoint;$/;"	m	struct:ssv6xxx_usb_glue	typeref:struct:ssv6xxx_usb_glue::ssv6xxx_cmd_endpoint	file:	access:public
+cmd_func_ptr	ssvdevice/ssv_cmd.h	/^    int (*cmd_func_ptr)(struct ssv_softc *sc, int, char **);$/;"	m	struct:ssv_cmd_table	access:public
+cmd_hwinfo	smac/dev.h	/^    void (*cmd_hwinfo)(struct ssv_hw *sh, int argc, char *argv[]);$/;"	m	struct:ssv_hal_ops	access:public
+cmd_hwq_limit	smac/dev.h	/^    void (*cmd_hwq_limit)(struct ssv_hw *sh, int argc, char *argv[]);$/;"	m	struct:ssv_hal_ops	access:public
+cmd_in_proc	smac/dev.h	/^    bool cmd_in_proc;$/;"	m	struct:ssv_cmd_data	access:public
+cmd_iqk_cfg	ssvdevice/ssv_cmd.c	/^static struct ssv6xxx_iqk_cfg cmd_iqk_cfg = {$/;"	v	typeref:struct:ssv6xxx_iqk_cfg	file:
+cmd_loopback	smac/dev.h	/^    void (*cmd_loopback)(struct ssv_hw *sh, int argc, char *argv[]);$/;"	m	struct:ssv_hal_ops	access:public
+cmd_loopback_setup_env	smac/dev.h	/^    void (*cmd_loopback_setup_env)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+cmd_loopback_start	smac/dev.h	/^    void (*cmd_loopback_start)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+cmd_mib	smac/dev.h	/^    void (*cmd_mib)(struct ssv_softc *sc, int argc, char *argv[]);$/;"	m	struct:ssv_hal_ops	access:public
+cmd_mutex	hwif/usb/usb.c	/^ struct mutex cmd_mutex;$/;"	m	struct:ssv6xxx_usb_glue	typeref:struct:ssv6xxx_usb_glue::mutex	file:	access:public
+cmd_noa_param	ssvdevice/ssv_cmd.c	/^static struct ssv6xxx_p2p_noa_param cmd_noa_param = {$/;"	v	typeref:struct:ssv6xxx_p2p_noa_param	file:
+cmd_power_saving	smac/dev.h	/^    void (*cmd_power_saving)(struct ssv_softc *sc, int argc, char *argv[]);$/;"	m	struct:ssv_hal_ops	access:public
+cmd_que	smac/p2p.h	/^    struct sk_buff_head cmd_que;$/;"	m	struct:ssv_cmd_Info	typeref:struct:ssv_cmd_Info::sk_buff_head	access:public
+cmd_rc	smac/dev.h	/^    void (*cmd_rc)(struct ssv_hw *sh, int argc, char *argv[]);$/;"	m	struct:ssv_hal_ops	access:public
+cmd_rf	smac/dev.h	/^    void (*cmd_rf)(struct ssv_hw *sh, int argc, char *argv[]);$/;"	m	struct:ssv_hal_ops	access:public
+cmd_sel	include/ssv6xxx_common.h	/^    u32 cmd_sel;$/;"	m	struct:ssv6xxx_iqk_cfg	access:public
+cmd_seq_no	include/ssv6xxx_common.h	/^    u32 cmd_seq_no;$/;"	m	struct:cfg_host_cmd	access:public
+cmd_spectrum	smac/dev.h	/^    void (*cmd_spectrum)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+cmd_table	ssvdevice/ssv_cmd.c	/^struct ssv_cmd_table cmd_table[] = {$/;"	v	typeref:struct:ssv_cmd_table
+cmd_txgen	smac/dev.h	/^    void (*cmd_txgen)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+column	smac/ssv_rc_common.h	/^    u8 column;$/;"	m	struct:minstrel_mcs_group_data	access:public
+column	smac/ssv_rc_minstrel_ht.h	/^ u8 column;$/;"	m	struct:ssv_minstrel_ht_mcs_group_data	access:public
+compress_bitmap	smac/ampdu.h	/^    u16 compress_bitmap:1;$/;"	m	struct:AMPDU_BLOCKACK_st	access:public
+concurrent_deci_tbl	smac/dev_tbl.h	/^u16 concurrent_deci_tbl[] =$/;"	v
+conf_parser	include/ssv_conf_parser.h	/^char const *conf_parser[] = {$/;"	v
+config_wq	smac/dev.h	/^    struct workqueue_struct *config_wq;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::workqueue_struct	access:public
+configuration	include/ssv_cfg.h	/^    u32 configuration[EXTERNEL_CONFIG_SUPPORT+1][2];$/;"	m	struct:ssv6xxx_cfg	access:public
+connect_ap	script/scan_conn.sh	/^connect_ap ( )$/;"	f
+control	smac/ampdu.h	/^ unsigned short control;$/;"	m	struct:ssv_bar	access:public
+core	hwif/sdio/sdio.c	/^    struct platform_device *core;$/;"	m	struct:ssv6xxx_sdio_glue	typeref:struct:ssv6xxx_sdio_glue::platform_device	file:	access:public
+core	hwif/usb/usb.c	/^ struct platform_device *core;$/;"	m	struct:ssv6xxx_usb_glue	typeref:struct:ssv6xxx_usb_glue::platform_device	file:	access:public
+count	crypto/sha1_glue.c	/^ u64 count;$/;"	m	struct:SHA1_CTX	file:	access:public
+count	include/ssv6200_common.h	/^    u8 count;$/;"	m	struct:ssv62xx_tx_rate	access:public
+count	include/ssv6xxx_common.h	/^    u32 count:4;$/;"	m	struct:fw_rc_retry_params	access:public
+count	smac/ssv_rc_minstrel_ht.h	/^ u8 count;$/;"	m	struct:ssv_minstrel_ht_rpt	access:public
+cpu_clk	smac/hal/ssv6006c/turismo_common.h	/^    u16 cpu_clk;$/;"	m	struct:ssv6006_patch	access:public
+cpu_nfb	smac/dev.h	/^    struct notifier_block cpu_nfb;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::notifier_block	access:public
+cpu_no	smac/dev.h	/^    u32 cpu_no;$/;"	m	struct:ssv_encrypt_task_list	access:public
+cpu_offline	smac/dev.h	/^    volatile int cpu_offline;$/;"	m	struct:ssv_encrypt_task_list	access:public
+crate	include/ssv6xxx_common.h	/^    u32 crate:6;$/;"	m	struct:fw_rc_retry_params	access:public
+crate_hw_idx	smac/ssv_rc_common.h	/^    int crate_hw_idx;$/;"	m	struct:ssv_rate_info	access:public
+crate_idx	include/ssv6200_common.h	/^    u32 crate_idx:6;$/;"	m	struct:ssv6200_tx_desc	access:public
+crate_idx0	smac/hal/ssv6006c/turismo_common.h	/^    u32 crate_idx0:8;$/;"	m	struct:ssv6006_tx_desc	access:public
+crate_idx1	smac/hal/ssv6006c/turismo_common.h	/^    u32 crate_idx1:8;$/;"	m	struct:ssv6006_tx_desc	access:public
+crate_idx2	smac/hal/ssv6006c/turismo_common.h	/^    u32 crate_idx2:8;$/;"	m	struct:ssv6006_tx_desc	access:public
+crate_idx3	smac/hal/ssv6006c/turismo_common.h	/^    u32 crate_idx3:8;$/;"	m	struct:ssv6006_tx_desc	access:public
+crate_kbps	smac/ssv_rc_common.h	/^    int crate_kbps;$/;"	m	struct:ssv_rate_info	access:public
+crc	smac/ampdu.h	/^    u8 crc;$/;"	m	struct:AMPDU_DELIMITER_st	access:public
+crypt_st	smac/ssv_skb.h	/^    volatile u8 crypt_st;$/;"	m	struct:SKB_info_st	access:public
+crypt_st_lock	smac/dev.h	/^    spinlock_t crypt_st_lock;$/;"	m	struct:ssv_softc	access:public
+crypted_q	smac/dev.h	/^    struct sk_buff_head crypted_q;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::sk_buff_head	access:public
+crypto_data	smac/dev.h	/^    struct ssv_crypto_data crypto_data;$/;"	m	struct:ssv_sta_priv_data	typeref:struct:ssv_sta_priv_data::ssv_crypto_data	access:public
+crypto_data	smac/dev.h	/^    struct ssv_crypto_data crypto_data;$/;"	m	struct:ssv_vif_priv_data	typeref:struct:ssv_vif_priv_data::ssv_crypto_data	access:public
+crystal_frequency_offset	include/ssv_cfg.h	/^    u32 crystal_frequency_offset;$/;"	m	struct:ssv6xxx_cfg	access:public
+crystal_type	include/ssv_cfg.h	/^    u32 crystal_type;$/;"	m	struct:ssv6xxx_cfg	access:public
+ctrl_rate_idx	smac/ssv_rc_common.h	/^    u8 ctrl_rate_idx;$/;"	m	struct:ssv_rc_rate	access:public
+ctwindows_oppps	smac/p2p.c	/^    u16 ctwindows_oppps;$/;"	m	struct:ssv6xxx_p2p_noa_attribute	file:	access:public
+cur_ampdu_pkt	smac/ampdu.h	/^    struct sk_buff *cur_ampdu_pkt;$/;"	m	struct:AMPDU_TID_st	typeref:struct:AMPDU_TID_st::sk_buff	access:public
+cur_channel	smac/dev.h	/^    struct ieee80211_channel *cur_channel;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::ieee80211_channel	access:public
+cur_prob	smac/ssv_rc_common.h	/^    unsigned int cur_prob, probability;$/;"	m	struct:minstrel_rate_stats	access:public
+cur_prob	smac/ssv_rc_minstrel.h	/^ u32 cur_prob;$/;"	m	struct:ssv_minstrel_rate	access:public
+cur_prob	smac/ssv_rc_minstrel_ht.h	/^ unsigned int cur_prob, probability;$/;"	m	struct:ssv_minstrel_ht_rate_stats	access:public
+cur_qsize	smac/dev.h	/^    int cur_qsize;$/;"	m	struct:ssv6xxx_bcast_txq	access:public
+cur_tp	smac/ssv_rc_common.h	/^    unsigned int cur_tp;$/;"	m	struct:minstrel_rate_stats	access:public
+cur_tp	smac/ssv_rc_minstrel.h	/^ u32 cur_tp;$/;"	m	struct:ssv_minstrel_rate	access:public
+cur_tp	smac/ssv_rc_minstrel_ht.h	/^ unsigned int cur_tp;$/;"	m	struct:ssv_minstrel_ht_rate_stats	access:public
+current_band	smac/dev.h	/^    u8 current_band;$/;"	m	struct:ssv6006_padpd	access:public
+current_band	smac/hal/ssv6006c/turismo_common.h	/^    u8 current_band;$/;"	m	struct:ssv6006_padpd	access:public
+current_pwr	smac/dev.h	/^    u8 current_pwr;$/;"	m	struct:ssv_softc	access:public
+cw_max	smac/ssv_rc_minstrel.h	/^ unsigned int cw_max;$/;"	m	struct:ssv_minstrel_priv	access:public
+cw_min	smac/ssv_rc_minstrel.h	/^ unsigned int cw_min;$/;"	m	struct:ssv_minstrel_priv	access:public
+d_flags	smac/ssv_rc_common.h	/^    u32 d_flags;$/;"	m	struct:ssv_rate_info	access:public
+dat	include/ssv6xxx_common.h	/^    u8 dat[0];$/;"	m	struct:cfg_host_event	access:public
+dat16	include/ssv6xxx_common.h	/^    u16 dat16[0];$/;"	m	union:cfg_host_cmd::__anon43	access:public
+dat32	include/ssv6xxx_common.h	/^    u32 dat32[0];$/;"	m	union:cfg_host_cmd::__anon43	access:public
+dat8	include/ssv6xxx_common.h	/^    u8 dat8[0];$/;"	m	union:cfg_host_cmd::__anon43	access:public
+data	crypto/sha1_glue.c	/^ u8 data[SHA1_BLOCK_SIZE];$/;"	m	struct:SHA1_CTX	file:	access:public
+data	include/ssv6xxx_common.h	/^    u32 data;$/;"	m	struct:ssv_cabrio_reg_st	access:public
+data	smac/dev.h	/^ char *data;$/;"	m	struct:ssv_dbg_log	access:public
+dataIOPort	bridge/sdiobridge.h	/^    unsigned int dataIOPort;$/;"	m	struct:ssv_sdiobridge_glue	access:public
+dataIOPort	hwif/sdio/sdio.c	/^    unsigned int dataIOPort;$/;"	m	struct:ssv6xxx_sdio_glue	file:	access:public
+data_rate	include/ssv6200_common.h	/^    s8 data_rate;$/;"	m	struct:ssv62xx_tx_rate	access:public
+date	smac/hal/ssv6006c/ssv6006_mac.h	/^    u32 date;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+dbg_control	hwif/hwif.h	/^ bool dbg_control;$/;"	m	struct:ssv6xxx_platform_data	access:public
+dbg_log	smac/dev.h	/^ struct ssv_dbg_log dbg_log;$/;"	m	struct:ssv_cmd_data	typeref:struct:ssv_cmd_data::ssv_dbg_log	access:public
+dbg_rx_frame	smac/dev.h	/^    bool dbg_rx_frame;$/;"	m	struct:ssv_softc	access:public
+dbg_stats	smac/ssv_rc_minstrel.h	/^ struct dentry *dbg_stats;$/;"	m	struct:ssv_minstrel_sta_priv	typeref:struct:ssv_minstrel_sta_priv::dentry	access:public
+dbg_tx_frame	smac/dev.h	/^    bool dbg_tx_frame;$/;"	m	struct:ssv_softc	access:public
+dbgprint	hci/ssv_hci.h	/^ void (*dbgprint)(void *, u32 log_id, const char *fmt,...);$/;"	m	struct:ssv6xxx_hci_info	access:public
+dbgprint	smac/dev.c	/^void dbgprint(struct ssv_cmd_data *cmd_data, u32 log_ctrl, u32 log_id, const char *fmt,...)$/;"	f	signature:(struct ssv_cmd_data *cmd_data, u32 log_ctrl, u32 log_id, const char *fmt,...)
+dbgprint	smac/dev.h	/^void dbgprint(struct ssv_cmd_data *cmd_data, u32 log_ctrl, u32 log_id, const char *fmt,...);$/;"	p	signature:(struct ssv_cmd_data *cmd_data, u32 log_ctrl, u32 log_id, const char *fmt,...)
+dcdc	smac/dev.h	/^    u16 dcdc;$/;"	m	struct:ssv_flash_config	access:public
+dcdc	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 dcdc;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+dcdc	smac/hal/ssv6006c/turismo_common.h	/^    bool dcdc;$/;"	m	struct:ssv6006_patch	access:public
+debugfs	bridge/sdiobridge.h	/^    struct dentry *debugfs;$/;"	m	struct:ssv_sdiobridge_glue	typeref:struct:ssv_sdiobridge_glue::dentry	access:public
+debugfs_dir	hci/hctrl.h	/^ struct dentry *debugfs_dir;$/;"	m	struct:ssv6xxx_hci_ctrl	typeref:struct:ssv6xxx_hci_ctrl::dentry	access:public
+debugfs_dir	smac/ampdu.h	/^    struct dentry *debugfs_dir;$/;"	m	struct:AMPDU_TID_st	typeref:struct:AMPDU_TID_st::dentry	access:public
+debugfs_dir	smac/dev.h	/^    struct dentry *debugfs_dir;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::dentry	access:public
+debugfs_dir	smac/dev.h	/^    struct dentry *debugfs_dir;$/;"	m	struct:ssv_sta_info	typeref:struct:ssv_sta_info::dentry	access:public
+debugfs_dir	smac/dev.h	/^    struct dentry *debugfs_dir;$/;"	m	struct:ssv_vif_info	typeref:struct:ssv_vif_info::dentry	access:public
+dec_key	crypto/aes_glue.c	/^ AES_KEY dec_key;$/;"	m	struct:AES_CTX	file:	access:public
+decrypt_mpdu	smac/sec.h	/^ int (*decrypt_mpdu) (struct sk_buff * skb, int hdr_len, void *priv);$/;"	m	struct:ssv_crypto_ops	access:public
+decrypt_msdu	smac/sec.h	/^ int (*decrypt_msdu) (struct sk_buff * skb, int keyidx, int hdr_len,$/;"	m	struct:ssv_crypto_ops	access:public
+decrypt_prepare	smac/sec.h	/^ int (*decrypt_prepare) (struct sk_buff * skb, int hdr_len, void *priv);$/;"	m	struct:ssv_crypto_ops	access:public
+def_chan	include/ssv_cfg.h	/^    u32 def_chan;$/;"	m	struct:ssv6xxx_cfg	access:public
+def_high	smartlink/qqlink-lib-mipsel/include/TXIPCAM.h	/^ def_high = 3,$/;"	e	enum:definition
+def_low	smartlink/qqlink-lib-mipsel/include/TXIPCAM.h	/^ def_low = 1,$/;"	e	enum:definition
+def_middle	smartlink/qqlink-lib-mipsel/include/TXIPCAM.h	/^ def_middle = 2,$/;"	e	enum:definition
+def_val	ssvdevice/ssv_cmd.h	/^    u8 *def_val;$/;"	m	struct:ssv6xxx_cfg_cmd_table	access:public
+default_pwr	smac/dev.h	/^    u8 default_pwr;$/;"	m	struct:ssv_softc	access:public
+default_txgain	smac/dev.h	/^    u8 default_txgain[PADPDBAND];$/;"	m	struct:ssv_hw	access:public
+definition	smartlink/qqlink-lib-mipsel/include/TXIPCAM.h	/^enum definition {$/;"	g
+deinit	smac/sec.h	/^ void (*deinit) (void *priv);$/;"	m	struct:ssv_crypto_ops	access:public
+del_fw_wsid	smac/dev.h	/^    void (*del_fw_wsid)(struct ssv_softc *sc, struct ieee80211_sta *sta,$/;"	m	struct:ssv_hal_ops	access:public
+del_hw_wsid	smac/dev.h	/^    void (*del_hw_wsid)(struct ssv_softc *sc, int hw_wsid);$/;"	m	struct:ssv_hal_ops	access:public
+delay_ms	include/ssv6xxx_common.h	/^    u8 delay_ms;$/;"	m	struct:ssv6xxx_tx_loopback	access:public
+destory_wifi_sync	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	/^SDK_API void destory_wifi_sync();$/;"	p	signature:()
+detach_usb_hci	smac/dev.h	/^    void (*detach_usb_hci)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+dev	bridge/sdiobridge.h	/^    struct device *dev;$/;"	m	struct:ssv_sdiobridge_glue	typeref:struct:ssv_sdiobridge_glue::device	access:public
+dev	hci/ssv_hci.h	/^    struct device *dev;$/;"	m	struct:ssv6xxx_hci_info	typeref:struct:ssv6xxx_hci_info::device	access:public
+dev	hci_wrapper/ssv_huw.c	/^    struct device *dev;$/;"	m	struct:ssv_huw_dev	typeref:struct:ssv_huw_dev::device	file:	access:public
+dev	hwif/sdio/sdio.c	/^    struct device *dev;$/;"	m	struct:ssv6xxx_sdio_glue	typeref:struct:ssv6xxx_sdio_glue::device	file:	access:public
+dev	hwif/usb/usb.c	/^ struct device *dev;$/;"	m	struct:ssv6xxx_usb_glue	typeref:struct:ssv6xxx_usb_glue::device	file:	access:public
+dev	smac/dev.h	/^    struct device *dev;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::device	access:public
+dev_ready	hwif/sdio/sdio.c	/^    bool dev_ready;$/;"	m	struct:ssv6xxx_sdio_glue	file:	access:public
+dev_ready	hwif/usb/usb.c	/^ bool dev_ready;$/;"	m	struct:ssv6xxx_usb_glue	file:	access:public
+device	hwif/hwif.h	/^    unsigned short device;$/;"	m	struct:ssv6xxx_platform_data	access:public
+device_license	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    char * device_license;$/;"	m	struct:_tx_device_info	access:public
+device_match_by_alias	smac/init.c	/^static int device_match_by_alias(struct device *dev, void *data)$/;"	f	file:	signature:(struct device *dev, void *data)
+device_name	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    char * device_name;$/;"	m	struct:_tx_device_info	access:public
+device_serial_number	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    char * device_serial_number;$/;"	m	struct:_tx_device_info	access:public
+diff	smac/ssv_rc_common.h	/^ s32 diff;$/;"	m	struct:rc_pid_rateinfo	access:public
+digest	smartlink/qqlink-lib-mipsel/include/TXMsg.h	/^    char* digest;$/;"	m	struct:tag_structuring_msg	access:public
+directly_ack	smac/ssv_skb.h	/^    bool directly_ack;$/;"	m	struct:SKB_info_st	access:public
+directly_ack_high_threshold	include/ssv_cfg.h	/^    u32 directly_ack_high_threshold;$/;"	m	struct:ssv6xxx_cfg	access:public
+directly_ack_high_threshold	smac/dev.h	/^    int directly_ack_high_threshold;$/;"	m	struct:ssv_softc	access:public
+directly_ack_low_threshold	include/ssv_cfg.h	/^    u32 directly_ack_low_threshold;$/;"	m	struct:ssv6xxx_cfg	access:public
+directly_ack_low_threshold	smac/dev.h	/^    int directly_ack_low_threshold;$/;"	m	struct:ssv_softc	access:public
+disable_dpd	include/ssv_cfg.h	/^    u32 disable_dpd;$/;"	m	struct:ssv6xxx_cfg	access:public
+disable_fw_wsid	smac/dev.h	/^    void (*disable_fw_wsid)(struct ssv_softc *sc, int key_idx,$/;"	m	struct:ssv_hal_ops	access:public
+disable_usb_acc	hwif/hwif.h	/^    void (*disable_usb_acc)(void *param, u8 epnum);$/;"	m	struct:ssv6xxx_platform_data	access:public
+disable_usb_acc	smac/dev.h	/^    void (*disable_usb_acc)(struct ssv_softc *sc, u8 epnum);$/;"	m	struct:ssv_hal_ops	access:public
+disable_wakeup_src	platforms/a33-generic-wlan.c	/^extern int disable_wakeup_src(cpu_wakeup_src_e src, int para);$/;"	p	file:	signature:(cpu_wakeup_src_e src, int para)
+dl_length	include/ssv6200_common.h	/^    u32 dl_length:12;$/;"	m	struct:ssv6200_tx_desc	access:public
+dl_length	include/ssv6xxx_common.h	/^    u32 dl_length:12;$/;"	m	struct:fw_rc_retry_params	access:public
+dl_length0	smac/hal/ssv6006c/turismo_common.h	/^    u32 dl_length0:12;$/;"	m	struct:ssv6006_tx_desc	access:public
+dl_length1	smac/hal/ssv6006c/turismo_common.h	/^    u32 dl_length1:12;$/;"	m	struct:ssv6006_tx_desc	access:public
+dl_length2	smac/hal/ssv6006c/turismo_common.h	/^    u32 dl_length2:12;$/;"	m	struct:ssv6006_tx_desc	access:public
+dl_length3	smac/hal/ssv6006c/turismo_common.h	/^    u32 dl_length3:12;$/;"	m	struct:ssv6006_tx_desc	access:public
+dmaSkb	hwif/sdio/sdio.c	/^    struct sk_buff *dmaSkb;$/;"	m	struct:ssv6xxx_sdio_glue	typeref:struct:ssv6xxx_sdio_glue::sk_buff	file:	access:public
+do_iq_cal	smac/dev.h	/^    int (*do_iq_cal)(struct ssv_hw *sh, struct ssv6xxx_iqk_cfg *p_cfg);$/;"	m	struct:ssv_hal_ops	access:public
+do_rts_cts	include/ssv6200_common.h	/^    u32 do_rts_cts:2;$/;"	m	struct:ssv6200_tx_desc	access:public
+do_rts_cts0	smac/hal/ssv6006c/turismo_common.h	/^    u32 do_rts_cts0:2;$/;"	m	struct:ssv6006_tx_desc	access:public
+do_rts_cts1	smac/hal/ssv6006c/turismo_common.h	/^    u32 do_rts_cts1:2;$/;"	m	struct:ssv6006_tx_desc	access:public
+do_rts_cts2	smac/hal/ssv6006c/turismo_common.h	/^    u32 do_rts_cts2:2;$/;"	m	struct:ssv6006_tx_desc	access:public
+do_rts_cts3	smac/hal/ssv6006c/turismo_common.h	/^    u32 do_rts_cts3:2;$/;"	m	struct:ssv6006_tx_desc	access:public
+do_temperature_compensation	smac/dev.h	/^    void (*do_temperature_compensation)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+dot11RSNAStatsCCMPDecryptErrors	smac/sec_ccmp.c	/^ u32 dot11RSNAStatsCCMPDecryptErrors;$/;"	m	struct:lib80211_ccmp_data	file:	access:public
+dot11RSNAStatsCCMPFormatErrors	smac/sec_ccmp.c	/^ u32 dot11RSNAStatsCCMPFormatErrors;$/;"	m	struct:lib80211_ccmp_data	file:	access:public
+dot11RSNAStatsCCMPReplays	smac/sec_ccmp.c	/^ u32 dot11RSNAStatsCCMPReplays;$/;"	m	struct:lib80211_ccmp_data	file:	access:public
+dot11RSNAStatsTKIPICVErrors	smac/sec_tkip.c	/^ u32 dot11RSNAStatsTKIPICVErrors;$/;"	m	struct:lib80211_tkip_data	file:	access:public
+dot11RSNAStatsTKIPLocalMICFailures	smac/sec_tkip.c	/^ u32 dot11RSNAStatsTKIPLocalMICFailures;$/;"	m	struct:lib80211_tkip_data	file:	access:public
+dot11RSNAStatsTKIPReplays	smac/sec_tkip.c	/^ u32 dot11RSNAStatsTKIPReplays;$/;"	m	struct:lib80211_tkip_data	file:	access:public
+dot11_rate_idx	smac/ssv_rc_common.h	/^    u8 dot11_rate_idx;$/;"	m	struct:ssv_rc_rate	access:public
+down_level	smac/dev.h	/^    u32 down_level;$/;"	m	struct:ssv6xxx_b_cca_control	access:public
+down_level	smac/dev.h	/^    u32 down_level;$/;"	m	struct:ssv6xxx_cca_control	access:public
+dpd	smac/dev.h	/^    struct ssv6006_padpd dpd;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::ssv6006_padpd	access:public
+dpd_disable	smac/dev.h	/^    bool dpd_disable[PADPDBAND];$/;"	m	struct:ssv6006_padpd	access:public
+dpd_disable	smac/hal/ssv6006c/turismo_common.h	/^    bool dpd_disable[PADPDBAND];$/;"	m	struct:ssv6006_padpd	access:public
+dpd_done	smac/dev.h	/^    bool dpd_done[PADPDBAND];$/;"	m	struct:ssv6006_padpd	access:public
+dpd_done	smac/hal/ssv6006c/turismo_common.h	/^    bool dpd_done[PADPDBAND];$/;"	m	struct:ssv6006_padpd	access:public
+dpd_enable	smac/dev.h	/^    void (*dpd_enable)(struct ssv_hw *sh, bool val);$/;"	m	struct:ssv_hal_ops	access:public
+drate	include/ssv6xxx_common.h	/^    u32 drate:6;$/;"	m	struct:fw_rc_retry_params	access:public
+drate_hw_idx	smac/ssv_rc_common.h	/^    int drate_hw_idx;$/;"	m	struct:ssv_rate_info	access:public
+drate_idx	include/ssv6200_common.h	/^    u32 drate_idx:6;$/;"	m	struct:ssv6200_tx_desc	access:public
+drate_idx0	smac/hal/ssv6006c/turismo_common.h	/^    u32 drate_idx0:8;$/;"	m	struct:ssv6006_tx_desc	access:public
+drate_idx1	smac/hal/ssv6006c/turismo_common.h	/^    u32 drate_idx1:8;$/;"	m	struct:ssv6006_tx_desc	access:public
+drate_idx2	smac/hal/ssv6006c/turismo_common.h	/^    u32 drate_idx2:8;$/;"	m	struct:ssv6006_tx_desc	access:public
+drate_idx3	smac/hal/ssv6006c/turismo_common.h	/^    u32 drate_idx3:8;$/;"	m	struct:ssv6006_tx_desc	access:public
+drate_kbps	smac/ssv_rc_common.h	/^    int drate_kbps;$/;"	m	struct:ssv_rate_info	access:public
+dummy	include/ssv6xxx_common.h	/^    u32 dummy;$/;"	m	union:cfg_host_cmd::__anon43	access:public
+dummy	smartlink/airkiss-lib/airkiss.h	/^ int dummy[32];$/;"	m	struct:__anon24	access:public
+dummy	smartlink/airkiss-lib/mipsel/airkiss.h	/^ int dummy[32];$/;"	m	struct:__anon18	access:public
+dummy	smartlink/airkiss-lib/x64/airkiss.h	/^ int dummy[32];$/;"	m	struct:__anon30	access:public
+dummy0	smac/hal/ssv6006c/turismo_common.h	/^    u32 dummy0;$/;"	m	struct:ssv6006_tx_desc	access:public
+dummy1	smac/hal/ssv6006c/turismo_common.h	/^    u32 dummy1;$/;"	m	struct:ssv6006_tx_desc	access:public
+dummy2	smac/hal/ssv6006c/turismo_common.h	/^    u32 dummy2;$/;"	m	struct:ssv6006_tx_desc	access:public
+dummyap	smartlink/airkiss-lib/airkiss.h	/^ int dummyap[26];$/;"	m	struct:__anon24	access:public
+dummyap	smartlink/airkiss-lib/mipsel/airkiss.h	/^ int dummyap[26];$/;"	m	struct:__anon18	access:public
+dummyap	smartlink/airkiss-lib/x64/airkiss.h	/^ int dummyap[26];$/;"	m	struct:__anon30	access:public
+dump	bridge/sdiobridge.h	/^    u32 dump;$/;"	m	struct:ssv_sdiobridge_glue	access:public
+dump_decision	smac/dev.h	/^    bool (*dump_decision)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+dump_entry	bridge/sdiobridge.h	/^    struct dentry *dump_entry;$/;"	m	struct:ssv_sdiobridge_glue	typeref:struct:ssv_sdiobridge_glue::dentry	access:public
+dump_mib_rx_phy	smac/dev.h	/^    void (*dump_mib_rx_phy)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+dump_phy_reg	smac/dev.h	/^    bool (*dump_phy_reg)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+dump_rf_reg	smac/dev.h	/^    bool (*dump_rf_reg)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+dump_wsid	smac/dev.h	/^    bool (*dump_wsid)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+duration	smac/ampdu.h	/^ u16 duration;$/;"	m	struct:AMPDU_BLOCKACK_st	access:public
+duration	smac/ampdu.h	/^ unsigned short duration;$/;"	m	struct:ssv_bar	access:public
+duration	smac/ssv_rc_common.h	/^    unsigned int duration[MCS_GROUP_RATES];$/;"	m	struct:mcs_group	access:public
+duration	smac/ssv_rc_minstrel_ht.h	/^ unsigned int duration[MCS_GROUP_RATES];$/;"	m	struct:ssv_mcs_ht_group	access:public
+duration	smartlink/qqlink-lib-mipsel/include/TXMsg.h	/^ unsigned int duration;$/;"	m	struct:tag_structuring_msg	access:public
+dword	smac/ssv_rc_minstrel_ht.h	/^ u8 dword;$/;"	m	struct:ssv_minstrel_ht_rpt	access:public
+early_aggr_ampdu_q	smac/ampdu.h	/^    struct sk_buff_head early_aggr_ampdu_q;$/;"	m	struct:AMPDU_TID_st	typeref:struct:AMPDU_TID_st::sk_buff_head	access:public
+early_aggr_skb_num	smac/ampdu.h	/^    u32 early_aggr_skb_num;$/;"	m	struct:AMPDU_TID_st	access:public
+early_suspend	smac/dev.h	/^    struct early_suspend early_suspend;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::early_suspend	access:public
+edca0	include/ssv6200.h	/^    u32 edca0:4;$/;"	m	struct:txResourceControl	access:public
+edca0	include/ssv6xxx_cfg.h	/^    u32 edca0:4;$/;"	m	struct:txResourceControl	access:public
+edca0	include/ssv6xxx_common.h	/^    u32 edca0:4;$/;"	m	struct:hci_rx_aggr_info	access:public
+edca0_used	include/ssv6200_common.h	/^    u32 edca0_used:4;$/;"	m	struct:ssv6200_rx_desc	access:public
+edca1	include/ssv6200.h	/^    u32 edca1:4;$/;"	m	struct:txResourceControl	access:public
+edca1	include/ssv6xxx_cfg.h	/^    u32 edca1:4;$/;"	m	struct:txResourceControl	access:public
+edca1	include/ssv6xxx_common.h	/^    u32 edca1:5;$/;"	m	struct:hci_rx_aggr_info	access:public
+edca1_used	include/ssv6200_common.h	/^    u32 edca1_used:5;$/;"	m	struct:ssv6200_rx_desc	access:public
+edca2	include/ssv6200.h	/^    u32 edca2:5;$/;"	m	struct:txResourceControl	access:public
+edca2	include/ssv6xxx_cfg.h	/^    u32 edca2:5;$/;"	m	struct:txResourceControl	access:public
+edca2	include/ssv6xxx_common.h	/^    u32 edca2:5;$/;"	m	struct:hci_rx_aggr_info	access:public
+edca2_used	include/ssv6200_common.h	/^    u32 edca2_used:5;$/;"	m	struct:ssv6200_rx_desc	access:public
+edca3	include/ssv6200.h	/^    u32 edca3:5;$/;"	m	struct:txResourceControl	access:public
+edca3	include/ssv6xxx_cfg.h	/^    u32 edca3:5;$/;"	m	struct:txResourceControl	access:public
+edca3	include/ssv6xxx_common.h	/^    u32 edca3:5;$/;"	m	struct:hci_rx_aggr_info	access:public
+edca3_used	include/ssv6200_common.h	/^    u32 edca3_used:5;$/;"	m	struct:ssv6200_rx_desc	access:public
+edca4	include/ssv6xxx_common.h	/^    u32 edca4:4;$/;"	m	struct:hci_rx_aggr_info	access:public
+edca5	include/ssv6xxx_common.h	/^    u32 edca5:5;$/;"	m	struct:hci_rx_aggr_info	access:public
+edca_enable	smac/dev.h	/^ void (*edca_enable)(struct ssv_hw *sh, bool val);$/;"	m	struct:ssv_hal_ops	access:public
+edca_stat	smac/dev.h	/^ void (*edca_stat)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+efuse_bitmap	smac/dev.h	/^    u32 efuse_bitmap;$/;"	m	struct:ssv_hw	access:public
+efuse_data_item	smac/efuse.h	/^enum efuse_data_item {$/;"	g
+efuse_map	smac/efuse.h	/^struct efuse_map {$/;"	s
+efuse_map::byte_cnts	smac/efuse.h	/^    u8 byte_cnts;$/;"	m	struct:efuse_map	access:public
+efuse_map::offset	smac/efuse.h	/^    u8 offset;$/;"	m	struct:efuse_map	access:public
+efuse_map::value	smac/efuse.h	/^    u16 value;$/;"	m	struct:efuse_map	access:public
+efuse_read_all_map	smac/efuse.c	/^void efuse_read_all_map(struct ssv_hw *sh)$/;"	f	signature:(struct ssv_hw *sh)
+efuse_read_all_map	smac/efuse.h	/^void efuse_read_all_map(struct ssv_hw *sh);$/;"	p	signature:(struct ssv_hw *sh)
+element_audio	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^    element_audio = 4,$/;"	e	enum:tx_barrage_msg_element_type
+element_face	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^    element_face = 2,$/;"	e	enum:tx_barrage_msg_element_type
+element_image	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^    element_image = 3,$/;"	e	enum:tx_barrage_msg_element_type
+element_none	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^    element_none = 0,$/;"	e	enum:tx_barrage_msg_element_type
+element_text	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^    element_text = 1,$/;"	e	enum:tx_barrage_msg_element_type
+enable_beacon	smac/dev.h	/^    u8 enable_beacon;$/;"	m	struct:ssv_softc	access:public
+enable_fw_wsid	smac/dev.h	/^    void (*enable_fw_wsid)(struct ssv_softc *sc, struct ieee80211_sta *sta,$/;"	m	struct:ssv_hal_ops	access:public
+enable_usb_acc	hwif/hwif.h	/^    void (*enable_usb_acc)(void *param, u8 epnum);$/;"	m	struct:ssv6xxx_platform_data	access:public
+enable_usb_acc	smac/dev.h	/^    void (*enable_usb_acc)(struct ssv_softc *sc, u8 epnum);$/;"	m	struct:ssv_hal_ops	access:public
+enable_wakeup_src	platforms/a33-generic-wlan.c	/^extern int enable_wakeup_src(cpu_wakeup_src_e src, int para);$/;"	p	file:	signature:(cpu_wakeup_src_e src, int para)
+enc_key	crypto/aes_glue.c	/^ AES_KEY enc_key;$/;"	m	struct:AES_CTX	file:	access:public
+encode_param	smartlink/qqlink-lib-mipsel/include/TXAudioVideo.h	/^ unsigned char encode_param;$/;"	m	struct:_tx_audio_encode_param	access:public
+encry_work	smac/ampdu.h	/^void encry_work(struct work_struct *work);$/;"	p	signature:(struct work_struct *work)
+encrypt_mpdu	smac/sec.h	/^ int (*encrypt_mpdu) (struct sk_buff * skb, int hdr_len, void *priv);$/;"	m	struct:ssv_crypto_ops	access:public
+encrypt_msdu	smac/sec.h	/^ int (*encrypt_msdu) (struct sk_buff * skb, int hdr_len, void *priv);$/;"	m	struct:ssv_crypto_ops	access:public
+encrypt_prepare	smac/sec.h	/^ int (*encrypt_prepare) (struct sk_buff * skb, int hdr_len, void *priv);$/;"	m	struct:ssv_crypto_ops	access:public
+encrypt_task	smac/dev.h	/^    struct task_struct* encrypt_task;$/;"	m	struct:ssv_encrypt_task_list	typeref:struct:ssv_encrypt_task_list::task_struct	access:public
+encrypt_task_head	smac/dev.h	/^    struct list_head encrypt_task_head;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::list_head	access:public
+encrypt_wait_q	smac/dev.h	/^    wait_queue_head_t encrypt_wait_q;$/;"	m	struct:ssv_encrypt_task_list	access:public
+end	smac/dev.h	/^ char *end;$/;"	m	struct:ssv_dbg_log	access:public
+end_time	smartlink/qqlink-lib-mipsel/include/TXIPCAM.h	/^ unsigned int end_time;$/;"	m	struct:_tx_history_video_range	access:public
+err_av_service_started	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	/^    err_av_service_started = 0x00000008,$/;"	e	enum:error_code
+err_av_unlogin	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	/^    err_av_unlogin = 0x00030001,$/;"	e	enum:error_code
+err_avg_sc	smac/ssv_rc_common.h	/^    s32 err_avg_sc;$/;"	m	struct:rc_pid_sta_info	access:public
+err_buffer_notenough	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	/^    err_buffer_notenough = 0x00000004,$/;"	e	enum:error_code
+err_call_too_frequently	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	/^    err_call_too_frequently = 0x0000001C,$/;"	e	enum:error_code
+err_cnt	hwif/usb/usb.c	/^ u16 err_cnt;$/;"	m	struct:ssv6xxx_usb_glue	file:	access:public
+err_connect_failed	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	/^    err_connect_failed = 0x0000001B,$/;"	e	enum:error_code
+err_count	hwif/sdio/sdio.c	/^    unsigned int err_count;$/;"	m	struct:ssv6xxx_sdio_glue	file:	access:public
+err_device_inited	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	/^    err_device_inited = 0x00000007,$/;"	e	enum:error_code
+err_failed	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	/^    err_failed = 0x00000001,$/;"	e	enum:error_code
+err_fetching	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	/^    err_fetching = 0x00000012,$/;"	e	enum:error_code
+err_fetching_buff_not_enough	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	/^    err_fetching_buff_not_enough = 0x00000013,$/;"	e	enum:error_code
+err_ft_file_too_large	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	/^    err_ft_file_too_large = 0x00040002,$/;"	e	enum:error_code
+err_ft_transfer_failed	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	/^    err_ft_transfer_failed = 0x00040001,$/;"	e	enum:error_code
+err_internal	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	/^    err_internal = 0x00000006,$/;"	e	enum:error_code
+err_invalid_app_path	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	/^    err_invalid_app_path = 0x0000000F,$/;"	e	enum:error_code
+err_invalid_av_callback	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	/^    err_invalid_av_callback = 0x0000000D,$/;"	e	enum:error_code
+err_invalid_device_info	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	/^    err_invalid_device_info = 0x00000009,$/;"	e	enum:error_code
+err_invalid_device_name	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	/^    err_invalid_device_name = 0x00000015,$/;"	e	enum:error_code
+err_invalid_device_notify	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	/^    err_invalid_device_notify = 0x0000000C,$/;"	e	enum:error_code
+err_invalid_fs_handler	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	/^    err_invalid_fs_handler = 0x0000000B,$/;"	e	enum:error_code
+err_invalid_license	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	/^    err_invalid_license = 0x00000017,$/;"	e	enum:error_code
+err_invalid_network_type	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	/^    err_invalid_network_type = 0x0000001E,$/;"	e	enum:error_code
+err_invalid_os_platform	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	/^    err_invalid_os_platform = 0x00000016,$/;"	e	enum:error_code
+err_invalid_param	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	/^    err_invalid_param = 0x00000003,$/;"	e	enum:error_code
+err_invalid_product_id	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	/^    err_invalid_product_id = 0x0000001A,$/;"	e	enum:error_code
+err_invalid_product_version	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	/^    err_invalid_product_version = 0x00000019,$/;"	e	enum:error_code
+err_invalid_serial_number	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	/^    err_invalid_serial_number = 0x0000000A,$/;"	e	enum:error_code
+err_invalid_server_pub_key	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	/^    err_invalid_server_pub_key = 0x00000018,$/;"	e	enum:error_code
+err_invalid_system_path	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	/^    err_invalid_system_path = 0x0000000E,$/;"	e	enum:error_code
+err_invalid_temp_path	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	/^    err_invalid_temp_path = 0x00000010,$/;"	e	enum:error_code
+err_login_connect_failed	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	/^    err_login_connect_failed = 0x00010003,$/;"	e	enum:error_code
+err_login_eraseinfo	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	/^    err_login_eraseinfo = 0x00010005,$/;"	e	enum:error_code
+err_login_failed	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	/^    err_login_failed = 0x00010001,$/;"	e	enum:error_code
+err_login_invalid_deviceinfo	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	/^    err_login_invalid_deviceinfo = 0x00010002,$/;"	e	enum:error_code
+err_login_servererror	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	/^    err_login_servererror = 0x00010006,$/;"	e	enum:error_code
+err_login_timeout	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	/^    err_login_timeout = 0x00010004,$/;"	e	enum:error_code
+err_mem_alloc	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	/^    err_mem_alloc = 0x00000005,$/;"	e	enum:error_code
+err_msg_sendfailed	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	/^    err_msg_sendfailed = 0x00020001,$/;"	e	enum:error_code
+err_msg_sendtimeout	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	/^    err_msg_sendtimeout = 0x00020002,$/;"	e	enum:error_code
+err_not_impl	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	/^    err_not_impl = 0x00000011,$/;"	e	enum:error_code
+err_null	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	/^    err_null = 0x00000000,$/;"	e	enum:error_code
+err_off_line	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	/^    err_off_line = 0x00000014,$/;"	e	enum:error_code
+err_sys_path_access_permission	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	/^    err_sys_path_access_permission = 0x0000001D,$/;"	e	enum:error_code
+err_unknown	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	/^    err_unknown = 0x00000002,$/;"	e	enum:error_code
+error_code	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	/^enum error_code$/;"	g
+evt_id	include/ssv6xxx_common.h	/^    u8 evt_id;$/;"	m	struct:ssv62xx_noa_evt	access:public
+evt_que	smac/p2p.h	/^    struct sk_buff_head evt_que;$/;"	m	struct:ssv_cmd_Info	typeref:struct:ssv_cmd_Info::sk_buff_head	access:public
+evt_seq_no	include/ssv6xxx_common.h	/^    u32 evt_seq_no;$/;"	m	struct:cfg_host_event	access:public
+exist	smac/dev.h	/^    bool exist;$/;"	m	struct:ssv_flash_config	access:public
+exitWlan	platforms/a33-generic-wlan.c	/^void exitWlan(void)$/;"	f	signature:(void)
+exitWlan	platforms/ak3916-generic-wlan.c	/^void exitWlan(void)$/;"	f	signature:(void)
+exitWlan	platforms/aml-s805-generic-wlan.c	/^void exitWlan(void)$/;"	f	signature:(void)
+exitWlan	platforms/aml-s905-generic-wlan.c	/^void exitWlan(void)$/;"	f	signature:(void)
+exitWlan	platforms/atm7039-action-generic-wlan.c	/^void exitWlan(void)$/;"	f	signature:(void)
+exitWlan	platforms/h3-generic-wlan.c	/^void exitWlan(void)$/;"	f	signature:(void)
+exitWlan	platforms/h8-generic-wlan.c	/^void exitWlan(void)$/;"	f	signature:(void)
+exitWlan	platforms/rk3036-generic-wlan.c	/^void exitWlan(void)$/;"	f	signature:(void)
+exitWlan	platforms/rk3126-generic-wlan.c	/^void exitWlan(void)$/;"	f	signature:(void)
+exitWlan	platforms/rk3128-generic-wlan.c	/^void exitWlan(void)$/;"	f	signature:(void)
+exitWlan	platforms/rk322x-generic-wlan.c	/^void exitWlan(void)$/;"	f	signature:(void)
+exitWlan	platforms/t10-generic-wlan.c	/^void exitWlan(void)$/;"	f	signature:(void)
+exitWlan	platforms/t20-generic-wlan.c	/^void exitWlan(void)$/;"	f	signature:(void)
+exitWlan	platforms/x1000-generic-wlan.c	/^void exitWlan(void)$/;"	f	signature:(void)
+exitWlan	platforms/xm-hi3518-generic-wlan.c	/^void exitWlan(void)$/;"	f	signature:(void)
+extern_wifi_set_enable	platforms/aml-s805-generic-wlan.c	/^extern void extern_wifi_set_enable(int is_on);$/;"	p	file:	signature:(int is_on)
+extern_wifi_set_enable	platforms/aml-s905-generic-wlan.c	/^extern void extern_wifi_set_enable(int is_on);$/;"	p	file:	signature:(int is_on)
+external_firmware_name	include/ssv_cfg.h	/^    u8 external_firmware_name[128];$/;"	m	struct:ssv6xxx_cfg	access:public
+extra_info	include/ssv6200_common.h	/^    u32 extra_info:1;$/;"	m	struct:ssv6200_rx_desc	access:public
+extra_info	include/ssv6200_common.h	/^    u32 extra_info:1;$/;"	m	struct:ssv6200_tx_desc	access:public
+extra_info	smac/hal/ssv6006c/turismo_common.h	/^    u32 extra_info:1;$/;"	m	struct:ssv6006_tx_desc	access:public
+extra_mpdu_postfix_len	smac/sec.h	/^ int extra_mpdu_prefix_len, extra_mpdu_postfix_len;$/;"	m	struct:ssv_crypto_ops	access:public
+extra_mpdu_prefix_len	smac/sec.h	/^ int extra_mpdu_prefix_len, extra_mpdu_postfix_len;$/;"	m	struct:ssv_crypto_ops	access:public
+extra_msdu_postfix_len	smac/sec.h	/^ int extra_msdu_prefix_len, extra_msdu_postfix_len;$/;"	m	struct:ssv_crypto_ops	access:public
+extra_msdu_prefix_len	smac/sec.h	/^ int extra_msdu_prefix_len, extra_msdu_postfix_len;$/;"	m	struct:ssv_crypto_ops	access:public
+f80211	include/ssv6200_common.h	/^    u32 f80211:1;$/;"	m	struct:ssv6200_rx_desc	access:public
+f80211	include/ssv6200_common.h	/^    u32 f80211:1;$/;"	m	struct:ssv6200_tx_desc	access:public
+f80211	smac/hal/ssv6006c/turismo_common.h	/^    u32 f80211:1;$/;"	m	struct:ssv6006_rx_desc	access:public
+f80211	smac/hal/ssv6006c/turismo_common.h	/^    u32 f80211:1;$/;"	m	struct:ssv6006_tx_desc	access:public
+fCmd	include/ssv6200_common.h	/^    u32 fCmd;$/;"	m	struct:ssv6200_tx_desc	access:public
+fCmd	smac/hal/ssv6006c/turismo_common.h	/^        u32 fCmd;$/;"	m	union:ssv6006_rx_desc::__anon1	access:public
+fCmd	smac/hal/ssv6006c/turismo_common.h	/^    u32 fCmd;$/;"	m	struct:ssv6006_tx_desc	access:public
+fCmdIdx	include/ssv6200_common.h	/^    u32 fCmdIdx:3;$/;"	m	struct:ssv6200_rx_desc	access:public
+fCmdIdx	include/ssv6200_common.h	/^    u32 fCmdIdx:3;$/;"	m	struct:ssv6200_tx_desc	access:public
+fCmdIdx	smac/hal/ssv6006c/turismo_common.h	/^    u32 fCmdIdx:3;$/;"	m	struct:ssv6006_rx_desc	access:public
+fCmdIdx	smac/hal/ssv6006c/turismo_common.h	/^    u32 fCmdIdx:3;$/;"	m	struct:ssv6006_tx_desc	access:public
+face_index	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^    unsigned int face_index;$/;"	m	struct:tag_tx_face_msg_element	access:public
+fail	smac/ssv_rc_common.h	/^ u64 fail;$/;"	m	struct:rc_pid_rateinfo	access:public
+false	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	22;"	d
+fc	bridge/sdiobridge.c	/^static struct class *fc;$/;"	v	typeref:struct:class	file:
+fc	hci_wrapper/ssv_huw.c	/^static struct class *fc;$/;"	v	typeref:struct:class	file:
+fec	include/ssv6200_common.h	/^    u32 fec:1;$/;"	m	struct:ssv6200_rxphy_info	access:public
+fec	smac/hal/ssv6006c/turismo_common.h	/^    u32 fec:1;$/;"	m	struct:ssv6006_rxphy_info	access:public
+feedback_probes	smac/ssv_rc_common.h	/^    u8 feedback_probes;$/;"	m	struct:rc_pid_sta_info	access:public
+file_key	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^    char file_key[512];$/;"	m	struct:tag_tx_file_transfer_info	access:public
+file_path	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^    char file_path[1024];$/;"	m	struct:tag_tx_file_transfer_info	access:public
+file_path	smartlink/qqlink-lib-mipsel/include/TXMsg.h	/^    char* file_path;$/;"	m	struct:tag_structuring_msg	access:public
+file_size	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^    unsigned long long file_size;$/;"	m	struct:tag_tx_file_transfer_info	access:public
+file_type	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^    int file_type;$/;"	m	struct:tag_tx_file_transfer_info	access:public
+fill80211relust	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	/^enum fill80211relust {$/;"	g
+fill_80211_frame	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	/^SDK_API int fill_80211_frame(const unsigned char *buff, int nlen, int npackoffset, int* pChannel);$/;"	p	signature:(const unsigned char *buff, int nlen, int npackoffset, int* pChannel)
+fill_beacon	smac/dev.h	/^    void (*fill_beacon)(struct ssv_softc *sc, u32 regaddr, struct sk_buff *skb);$/;"	m	struct:ssv_hal_ops	access:public
+fill_beacon_tx_desc	smac/dev.h	/^    void (*fill_beacon_tx_desc)(struct ssv_softc *sc, struct sk_buff* beacon_skb);$/;"	m	struct:ssv_hal_ops	access:public
+fill_lpbk_tx_desc	smac/dev.h	/^    void (*fill_lpbk_tx_desc)(struct sk_buff *skb, int security, unsigned char rate);$/;"	m	struct:ssv_hal_ops	access:public
+firmware_path	include/ssv_cfg.h	/^    u8 firmware_path[128];$/;"	m	struct:ssv6xxx_cfg	access:public
+firmware_rate_control_report_data	include/ssv6200_common.h	/^struct firmware_rate_control_report_data{$/;"	s
+firmware_rate_control_report_data::ack_signal	include/ssv6200_common.h	/^    int ack_signal;$/;"	m	struct:firmware_rate_control_report_data	access:public
+firmware_rate_control_report_data::ampdu_ack_len	include/ssv6200_common.h	/^    u16 ampdu_ack_len;$/;"	m	struct:firmware_rate_control_report_data	access:public
+firmware_rate_control_report_data::ampdu_len	include/ssv6200_common.h	/^    u16 ampdu_len;$/;"	m	struct:firmware_rate_control_report_data	access:public
+firmware_rate_control_report_data::rates	include/ssv6200_common.h	/^    struct ssv62xx_tx_rate rates[SSV62XX_TX_MAX_RATES];$/;"	m	struct:firmware_rate_control_report_data	typeref:struct:firmware_rate_control_report_data::ssv62xx_tx_rate	access:public
+firmware_rate_control_report_data::wsid	include/ssv6200_common.h	/^    u8 wsid;$/;"	m	struct:firmware_rate_control_report_data	access:public
+first_sn	smac/ssv_skb.h	/^    u32 first_sn;$/;"	m	struct:ampdu_hdr_st	access:public
+first_try_count	smac/ssv_rc_common.h	/^    int first_try_count;$/;"	m	struct:ssv62xx_ht	access:public
+flags	smac/sec_tkip.c	/^ unsigned long flags;$/;"	m	struct:lib80211_tkip_data	file:	access:public
+flags	smac/ssv_rc_minstrel.h	/^ u32 flags;$/;"	m	struct:ssv_minstrel_rate	access:public
+flags	smac/ssv_rc_minstrel_ht.h	/^ u32 flags;$/;"	m	struct:ssv_mcs_ht_group	access:public
+flash_bin_path	include/ssv_cfg.h	/^    u8 flash_bin_path[128];$/;"	m	struct:ssv6xxx_cfg	access:public
+flash_config	smac/dev.h	/^    struct ssv_flash_config flash_config;$/;"	m	struct:ssv_hw	typeref:struct:ssv_hw::ssv_flash_config	access:public
+flash_read_all_map	smac/dev.h	/^    void (*flash_read_all_map)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+flow_ctrl_status	smac/dev.h	/^    u32 flow_ctrl_status;$/;"	m	struct:ssv_tx	access:public
+fops	bridge/sdiobridge.c	/^struct file_operations fops =$/;"	v	typeref:struct:file_operations
+forbid	include/ssv_cfg.h	/^    u16 forbid;$/;"	m	struct:rc_setting	access:public
+forbid3	include/ssv_cfg.h	/^    u16 forbid3;$/;"	m	struct:rc_setting	access:public
+forbid4	include/ssv_cfg.h	/^    u16 forbid4;$/;"	m	struct:rc_setting	access:public
+forbid5	include/ssv_cfg.h	/^    u16 forbid5;$/;"	m	struct:rc_setting	access:public
+forbid6	include/ssv_cfg.h	/^    u16 forbid6;$/;"	m	struct:rc_setting	access:public
+force_chip_identity	include/ssv_cfg.h	/^    u32 force_chip_identity;$/;"	m	struct:ssv6xxx_cfg	access:public
+force_disable_directly_ack_tx	smac/dev.h	/^    bool force_disable_directly_ack_tx;$/;"	m	struct:ssv_softc	access:public
+force_sample_pr	include/ssv_cfg.h	/^    u16 force_sample_pr;$/;"	m	struct:rc_setting	access:public
+force_sw_encrypt	smac/dev.h	/^    bool force_sw_encrypt;$/;"	m	struct:ssv_vif_priv_data	access:public
+force_triger_reset	smac/dev.h	/^    bool force_triger_reset;$/;"	m	struct:ssv_softc	access:public
+force_xtal_fo	include/ssv_cfg.h	/^    bool force_xtal_fo;$/;"	m	struct:ssv6xxx_cfg	access:public
+fpga_rf_setting	include/ssv6200_configuration.h	/^static ssv_cabrio_reg fpga_rf_setting[]=$/;"	v
+frag	include/ssv6200_common.h	/^    u32 frag:1;$/;"	m	struct:ssv6200_rx_desc	access:public
+frag	include/ssv6200_common.h	/^    u32 frag:1;$/;"	m	struct:ssv6200_tx_desc	access:public
+frag	smac/hal/ssv6006c/turismo_common.h	/^    u32 frag:1;$/;"	m	struct:ssv6006_rx_desc	access:public
+frag	smac/hal/ssv6006c/turismo_common.h	/^    u32 frag:1;$/;"	m	struct:ssv6006_tx_desc	access:public
+frame_cntl_mask	smac/sec_wpi.c	/^const u16 frame_cntl_mask = 0x8FC7;$/;"	v
+frame_consume_time	include/ssv6200_common.h	/^    u32 frame_consume_time:10;$/;"	m	struct:ssv6200_tx_desc	access:public
+frame_consume_time	include/ssv6xxx_common.h	/^    u32 frame_consume_time:10;$/;"	m	struct:fw_rc_retry_params	access:public
+frame_control	smac/ampdu.h	/^ u16 frame_control;$/;"	m	struct:AMPDU_BLOCKACK_st	access:public
+frame_control	smac/ampdu.h	/^ unsigned short frame_control;$/;"	m	struct:ssv_bar	access:public
+frame_per_pkg	smartlink/qqlink-lib-mipsel/include/TXAudioVideo.h	/^ unsigned char frame_per_pkg;$/;"	m	struct:_tx_audio_encode_param	access:public
+free_pbuf	smac/dev.h	/^    bool (*free_pbuf)(struct ssv_softc *sc, u32 pbuf_addr);$/;"	m	struct:ssv_hal_ops	access:public
+free_tx_id	hci/hctrl.h	/^ int free_tx_id;$/;"	m	struct:ssv6xxx_hw_resource	access:public
+free_tx_page	hci/hctrl.h	/^ int free_tx_page;$/;"	m	struct:ssv6xxx_hw_resource	access:public
+free_wifi_wakeup_BB	platforms/rk3126-generic-wlan.c	/^void free_wifi_wakeup_BB(void)$/;"	f	signature:(void)
+from_group_card	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^    char * from_group_card;$/;"	m	struct:tag_tx_barrage_msg	access:public
+from_head_url	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^    char * from_head_url;$/;"	m	struct:tag_tx_barrage_msg	access:public
+from_nick	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^    char * from_nick;$/;"	m	struct:tag_tx_barrage_msg	access:public
+from_target_appid	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^    unsigned int from_target_appid;$/;"	m	struct:tag_tx_barrage_msg	access:public
+from_target_id	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^    unsigned long long from_target_id;$/;"	m	struct:tag_tx_barrage_msg	access:public
+from_target_instid	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^    unsigned int from_target_instid;$/;"	m	struct:tag_tx_barrage_msg	access:public
+fstream	smartlink/qqlink-lib-mipsel/case/ipcamera/audiovideo.c	/^static FILE *fstream = NULL;$/;"	v	file:
+fstream	smartlink/qqlink-lib-mipsel/demo_video.c	/^static FILE *fstream = NULL;$/;"	v	file:
+funcFocus	bridge/sdiobridge.h	/^    u8 funcFocus;$/;"	m	struct:ssv_sdiobridge_glue	access:public
+funcFocus	hci_wrapper/ssv_huw.c	/^    u8 funcFocus;$/;"	m	struct:ssv_huw_dev	file:	access:public
+fw_rc_retry_params	include/ssv6xxx_common.h	/^struct fw_rc_retry_params {$/;"	s
+fw_rc_retry_params::RSVD	include/ssv6xxx_common.h	/^    u32 RSVD:10;$/;"	m	struct:fw_rc_retry_params	access:public
+fw_rc_retry_params::count	include/ssv6xxx_common.h	/^    u32 count:4;$/;"	m	struct:fw_rc_retry_params	access:public
+fw_rc_retry_params::crate	include/ssv6xxx_common.h	/^    u32 crate:6;$/;"	m	struct:fw_rc_retry_params	access:public
+fw_rc_retry_params::dl_length	include/ssv6xxx_common.h	/^    u32 dl_length:12;$/;"	m	struct:fw_rc_retry_params	access:public
+fw_rc_retry_params::drate	include/ssv6xxx_common.h	/^    u32 drate:6;$/;"	m	struct:fw_rc_retry_params	access:public
+fw_rc_retry_params::frame_consume_time	include/ssv6xxx_common.h	/^    u32 frame_consume_time:10;$/;"	m	struct:fw_rc_retry_params	access:public
+fw_rc_retry_params::rts_cts_nav	include/ssv6xxx_common.h	/^    u32 rts_cts_nav:16;$/;"	m	struct:fw_rc_retry_params	access:public
+fw_wait_q	smac/dev.h	/^    wait_queue_head_t fw_wait_q;$/;"	m	struct:ssv_softc	access:public
+fx_sel	include/ssv6xxx_common.h	/^        u32 fx_sel;$/;"	m	union:ssv6xxx_iqk_cfg::__anon47	access:public
+g	smartlink/ssv_smartlink.c	/^    struct genlmsghdr g;$/;"	m	struct:netlink_msg	typeref:struct:netlink_msg::genlmsghdr	file:	access:public
+gBuf	smartlink/airkiss.c	/^static uint8_t gBuf[MAX_PAYLOAD]={0};$/;"	v	file:
+gBuf	smartlink/qqlink.c	/^static uint8_t gBuf[MAX_PAYLOAD]={0};$/;"	v	file:
+gBufLen	smartlink/airkiss.c	/^static uint32_t gBufLen=0;$/;"	v	file:
+gBufLen	smartlink/qqlink.c	/^static uint32_t gBufLen=0;$/;"	v	file:
+gChan	smartlink/airkiss.c	/^static uint32_t gChan=SSV_MIN_CHANNEL;$/;"	v	file:
+gChan	smartlink/qqlink.c	/^static uint32_t gChan=SSV_MIN_CHANNEL;$/;"	v	file:
+g_NextInputTable	smac/wapi_sms4.c	/^static const u32 g_NextInputTable[RK_LEN] =$/;"	v	file:
+g_band_gain	smac/dev.h	/^    u8 g_band_gain[7];$/;"	m	struct:ssv_tempe_table	access:public
+g_band_gain_ht	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 g_band_gain_ht[7];$/;"	m	struct:ssv6006_flash_layout_table	access:public
+g_band_gain_lt	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 g_band_gain_lt[7];$/;"	m	struct:ssv6006_flash_layout_table	access:public
+g_band_gain_rt	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 g_band_gain_rt[7];$/;"	m	struct:ssv6006_flash_layout_table	access:public
+g_band_pa_bias0	smac/dev.h	/^    u32 g_band_pa_bias0;$/;"	m	struct:ssv_flash_config	access:public
+g_band_pa_bias0	smac/hal/ssv6006c/ssv6006_mac.h	/^    u32 g_band_pa_bias0;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+g_band_pa_bias1	smac/dev.h	/^    u32 g_band_pa_bias1;$/;"	m	struct:ssv_flash_config	access:public
+g_band_pa_bias1	smac/hal/ssv6006c/ssv6006_mac.h	/^    u32 g_band_pa_bias1;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+g_huw_dev	hci_wrapper/ssv_huw.c	/^struct ssv_huw_dev g_huw_dev;$/;"	v	typeref:struct:ssv_huw_dev
+g_pkts	smac/dev.h	/^    u64 g_pkts[8];$/;"	m	struct:rx_stats	access:public
+g_rates_offset	smac/ssv_rc_minstrel.h	/^ int g_rates_offset;$/;"	m	struct:ssv_minstrel_sta_info	access:public
+g_start_av_service	smartlink/qqlink-lib-mipsel/case/ipcamera/main.c	/^static bool g_start_av_service = false;$/;"	v	file:
+g_start_av_service	smartlink/qqlink-lib-mipsel/demo_video.c	/^static bool g_start_av_service = false;$/;"	v	file:
+g_wapi_oui	smac/sec_wpi.c	/^u8 g_wapi_oui[3] = {0x00,0x14,0x72};$/;"	v
+g_wifi_irq_rc	platforms/a33-generic-wlan.c	/^static unsigned int g_wifi_irq_rc = 0;$/;"	v	file:
+g_wifi_irq_rc	platforms/atm7039-action-generic-wlan.c	/^static int g_wifi_irq_rc = 0;$/;"	v	file:
+g_wifi_irq_rc	platforms/h3-generic-wlan.c	/^static int g_wifi_irq_rc=0;$/;"	v	file:
+g_wifi_irq_rc	platforms/h8-generic-wlan.c	/^static int g_wifi_irq_rc=0;$/;"	v	file:
+g_wifi_irq_rc	platforms/t10-generic-wlan.c	/^static int g_wifi_irq_rc=0;$/;"	v	file:
+g_wifi_irq_rc	platforms/x1000-generic-wlan.c	/^static int g_wifi_irq_rc=0;$/;"	v	file:
+g_wifidev_registered	platforms/a33-generic-wlan.c	/^static int g_wifidev_registered = 0;$/;"	v	file:
+g_wifidev_registered	platforms/aml-s805-generic-wlan.c	/^static int g_wifidev_registered = 0;$/;"	v	file:
+g_wifidev_registered	platforms/aml-s905-generic-wlan.c	/^static int g_wifidev_registered = 0;$/;"	v	file:
+g_wifidev_registered	platforms/atm7039-action-generic-wlan.c	/^static int g_wifidev_registered = 0;$/;"	v	file:
+g_wifidev_registered	platforms/h3-generic-wlan.c	/^static int g_wifidev_registered = 0;$/;"	v	file:
+g_wifidev_registered	platforms/h8-generic-wlan.c	/^static int g_wifidev_registered = 0;$/;"	v	file:
+g_wifidev_registered	platforms/rk3036-generic-wlan.c	/^static int g_wifidev_registered = 0;$/;"	v	file:
+g_wifidev_registered	platforms/rk3126-generic-wlan.c	/^static int g_wifidev_registered = 0;$/;"	v	file:
+g_wifidev_registered	platforms/rk3128-generic-wlan.c	/^static int g_wifidev_registered = 0;$/;"	v	file:
+g_wifidev_registered	platforms/rk322x-generic-wlan.c	/^static int g_wifidev_registered = 0;$/;"	v	file:
+g_wifidev_registered	platforms/t10-generic-wlan.c	/^static int g_wifidev_registered = 0;$/;"	v	file:
+g_wifidev_registered	platforms/x1000-generic-wlan.c	/^static int g_wifidev_registered = 0;$/;"	v	file:
+g_wifidev_registered	platforms/xm-hi3518-generic-wlan.c	/^static int g_wifidev_registered = 0;$/;"	v	file:
+gender	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    int gender;$/;"	m	struct:tag_tx_binder_info	access:public
+generic_deci_tbl	smac/dev_tbl.h	/^u16 generic_deci_tbl[] =$/;"	v
+generic_wifi_exit_module	platforms/a33-generic-wlan.c	/^EXPORT_SYMBOL(generic_wifi_exit_module);$/;"	v
+generic_wifi_exit_module	platforms/a33-generic-wlan.c	/^module_exit(generic_wifi_exit_module);$/;"	v
+generic_wifi_exit_module	platforms/a33-generic-wlan.c	/^static void generic_wifi_exit_module(void)$/;"	f	file:	signature:(void)
+generic_wifi_exit_module	platforms/ak3916-generic-wlan.c	/^EXPORT_SYMBOL(generic_wifi_exit_module);$/;"	v
+generic_wifi_exit_module	platforms/ak3916-generic-wlan.c	/^module_exit(generic_wifi_exit_module);$/;"	v
+generic_wifi_exit_module	platforms/ak3916-generic-wlan.c	/^static void generic_wifi_exit_module(void)$/;"	f	file:	signature:(void)
+generic_wifi_exit_module	platforms/aml-s805-generic-wlan.c	/^EXPORT_SYMBOL(generic_wifi_exit_module);$/;"	v
+generic_wifi_exit_module	platforms/aml-s805-generic-wlan.c	/^module_exit(generic_wifi_exit_module);$/;"	v
+generic_wifi_exit_module	platforms/aml-s805-generic-wlan.c	/^static __exit void generic_wifi_exit_module(void)$/;"	f	file:	signature:(void)
+generic_wifi_exit_module	platforms/aml-s905-generic-wlan.c	/^EXPORT_SYMBOL(generic_wifi_exit_module);$/;"	v
+generic_wifi_exit_module	platforms/aml-s905-generic-wlan.c	/^module_exit(generic_wifi_exit_module);$/;"	v
+generic_wifi_exit_module	platforms/aml-s905-generic-wlan.c	/^static __exit void generic_wifi_exit_module(void)$/;"	f	file:	signature:(void)
+generic_wifi_exit_module	platforms/atm7039-action-generic-wlan.c	/^EXPORT_SYMBOL(generic_wifi_exit_module);$/;"	v
+generic_wifi_exit_module	platforms/atm7039-action-generic-wlan.c	/^module_exit(generic_wifi_exit_module);$/;"	v
+generic_wifi_exit_module	platforms/atm7039-action-generic-wlan.c	/^static void generic_wifi_exit_module(void)$/;"	f	file:	signature:(void)
+generic_wifi_exit_module	platforms/h3-generic-wlan.c	/^EXPORT_SYMBOL(generic_wifi_exit_module);$/;"	v
+generic_wifi_exit_module	platforms/h3-generic-wlan.c	/^module_exit(generic_wifi_exit_module);$/;"	v
+generic_wifi_exit_module	platforms/h3-generic-wlan.c	/^static void generic_wifi_exit_module(void)$/;"	f	file:	signature:(void)
+generic_wifi_exit_module	platforms/h8-generic-wlan.c	/^EXPORT_SYMBOL(generic_wifi_exit_module);$/;"	v
+generic_wifi_exit_module	platforms/h8-generic-wlan.c	/^module_exit(generic_wifi_exit_module);$/;"	v
+generic_wifi_exit_module	platforms/h8-generic-wlan.c	/^static void generic_wifi_exit_module(void)$/;"	f	file:	signature:(void)
+generic_wifi_exit_module	platforms/rk3036-generic-wlan.c	/^EXPORT_SYMBOL(generic_wifi_exit_module);$/;"	v
+generic_wifi_exit_module	platforms/rk3036-generic-wlan.c	/^module_exit(generic_wifi_exit_module);$/;"	v
+generic_wifi_exit_module	platforms/rk3036-generic-wlan.c	/^static __exit void generic_wifi_exit_module(void)$/;"	f	file:	signature:(void)
+generic_wifi_exit_module	platforms/rk3126-generic-wlan.c	/^EXPORT_SYMBOL(generic_wifi_exit_module);$/;"	v
+generic_wifi_exit_module	platforms/rk3126-generic-wlan.c	/^module_exit(generic_wifi_exit_module);$/;"	v
+generic_wifi_exit_module	platforms/rk3126-generic-wlan.c	/^static __exit void generic_wifi_exit_module(void)$/;"	f	file:	signature:(void)
+generic_wifi_exit_module	platforms/rk3128-generic-wlan.c	/^EXPORT_SYMBOL(generic_wifi_exit_module);$/;"	v
+generic_wifi_exit_module	platforms/rk3128-generic-wlan.c	/^module_exit(generic_wifi_exit_module);$/;"	v
+generic_wifi_exit_module	platforms/rk3128-generic-wlan.c	/^static __exit void generic_wifi_exit_module(void)$/;"	f	file:	signature:(void)
+generic_wifi_exit_module	platforms/rk322x-generic-wlan.c	/^EXPORT_SYMBOL(generic_wifi_exit_module);$/;"	v
+generic_wifi_exit_module	platforms/rk322x-generic-wlan.c	/^module_exit(generic_wifi_exit_module);$/;"	v
+generic_wifi_exit_module	platforms/rk322x-generic-wlan.c	/^static __exit void generic_wifi_exit_module(void)$/;"	f	file:	signature:(void)
+generic_wifi_exit_module	platforms/t10-generic-wlan.c	/^EXPORT_SYMBOL(generic_wifi_exit_module);$/;"	v
+generic_wifi_exit_module	platforms/t10-generic-wlan.c	/^module_exit(generic_wifi_exit_module);$/;"	v
+generic_wifi_exit_module	platforms/t10-generic-wlan.c	/^static void generic_wifi_exit_module(void)$/;"	f	file:	signature:(void)
+generic_wifi_exit_module	platforms/t20-generic-wlan.c	/^EXPORT_SYMBOL(generic_wifi_exit_module);$/;"	v
+generic_wifi_exit_module	platforms/t20-generic-wlan.c	/^module_exit(generic_wifi_exit_module);$/;"	v
+generic_wifi_exit_module	platforms/t20-generic-wlan.c	/^static void generic_wifi_exit_module(void)$/;"	f	file:	signature:(void)
+generic_wifi_exit_module	platforms/x1000-generic-wlan.c	/^EXPORT_SYMBOL(generic_wifi_exit_module);$/;"	v
+generic_wifi_exit_module	platforms/x1000-generic-wlan.c	/^module_exit(generic_wifi_exit_module);$/;"	v
+generic_wifi_exit_module	platforms/x1000-generic-wlan.c	/^static void generic_wifi_exit_module(void)$/;"	f	file:	signature:(void)
+generic_wifi_exit_module	platforms/xm-hi3518-generic-wlan.c	/^EXPORT_SYMBOL(generic_wifi_exit_module);$/;"	v
+generic_wifi_exit_module	platforms/xm-hi3518-generic-wlan.c	/^module_exit(generic_wifi_exit_module);$/;"	v
+generic_wifi_exit_module	platforms/xm-hi3518-generic-wlan.c	/^static __exit void generic_wifi_exit_module(void)$/;"	f	file:	signature:(void)
+generic_wifi_init_module	platforms/a33-generic-wlan.c	/^EXPORT_SYMBOL(generic_wifi_init_module);$/;"	v
+generic_wifi_init_module	platforms/a33-generic-wlan.c	/^module_init(generic_wifi_init_module);$/;"	v
+generic_wifi_init_module	platforms/a33-generic-wlan.c	/^static int generic_wifi_init_module(void)$/;"	f	file:	signature:(void)
+generic_wifi_init_module	platforms/ak3916-generic-wlan.c	/^EXPORT_SYMBOL(generic_wifi_init_module);$/;"	v
+generic_wifi_init_module	platforms/ak3916-generic-wlan.c	/^late_initcall(generic_wifi_init_module);$/;"	v
+generic_wifi_init_module	platforms/ak3916-generic-wlan.c	/^module_init(generic_wifi_init_module);$/;"	v
+generic_wifi_init_module	platforms/ak3916-generic-wlan.c	/^static int generic_wifi_init_module(void)$/;"	f	file:	signature:(void)
+generic_wifi_init_module	platforms/aml-s805-generic-wlan.c	/^EXPORT_SYMBOL(generic_wifi_init_module);$/;"	v
+generic_wifi_init_module	platforms/aml-s805-generic-wlan.c	/^module_init(generic_wifi_init_module);$/;"	v
+generic_wifi_init_module	platforms/aml-s805-generic-wlan.c	/^static __init int generic_wifi_init_module(void)$/;"	f	file:	signature:(void)
+generic_wifi_init_module	platforms/aml-s905-generic-wlan.c	/^EXPORT_SYMBOL(generic_wifi_init_module);$/;"	v
+generic_wifi_init_module	platforms/aml-s905-generic-wlan.c	/^module_init(generic_wifi_init_module);$/;"	v
+generic_wifi_init_module	platforms/aml-s905-generic-wlan.c	/^static __init int generic_wifi_init_module(void)$/;"	f	file:	signature:(void)
+generic_wifi_init_module	platforms/atm7039-action-generic-wlan.c	/^EXPORT_SYMBOL(generic_wifi_init_module);$/;"	v
+generic_wifi_init_module	platforms/atm7039-action-generic-wlan.c	/^module_init(generic_wifi_init_module);$/;"	v
+generic_wifi_init_module	platforms/atm7039-action-generic-wlan.c	/^static int generic_wifi_init_module(void)$/;"	f	file:	signature:(void)
+generic_wifi_init_module	platforms/h3-generic-wlan.c	/^EXPORT_SYMBOL(generic_wifi_init_module);$/;"	v
+generic_wifi_init_module	platforms/h3-generic-wlan.c	/^module_init(generic_wifi_init_module);$/;"	v
+generic_wifi_init_module	platforms/h3-generic-wlan.c	/^static int generic_wifi_init_module(void)$/;"	f	file:	signature:(void)
+generic_wifi_init_module	platforms/h8-generic-wlan.c	/^EXPORT_SYMBOL(generic_wifi_init_module);$/;"	v
+generic_wifi_init_module	platforms/h8-generic-wlan.c	/^module_init(generic_wifi_init_module);$/;"	v
+generic_wifi_init_module	platforms/h8-generic-wlan.c	/^static int generic_wifi_init_module(void)$/;"	f	file:	signature:(void)
+generic_wifi_init_module	platforms/rk3036-generic-wlan.c	/^EXPORT_SYMBOL(generic_wifi_init_module);$/;"	v
+generic_wifi_init_module	platforms/rk3036-generic-wlan.c	/^module_init(generic_wifi_init_module);$/;"	v
+generic_wifi_init_module	platforms/rk3036-generic-wlan.c	/^static __init int generic_wifi_init_module(void)$/;"	f	file:	signature:(void)
+generic_wifi_init_module	platforms/rk3126-generic-wlan.c	/^EXPORT_SYMBOL(generic_wifi_init_module);$/;"	v
+generic_wifi_init_module	platforms/rk3126-generic-wlan.c	/^module_init(generic_wifi_init_module);$/;"	v
+generic_wifi_init_module	platforms/rk3126-generic-wlan.c	/^static __init int generic_wifi_init_module(void)$/;"	f	file:	signature:(void)
+generic_wifi_init_module	platforms/rk3128-generic-wlan.c	/^EXPORT_SYMBOL(generic_wifi_init_module);$/;"	v
+generic_wifi_init_module	platforms/rk3128-generic-wlan.c	/^module_init(generic_wifi_init_module);$/;"	v
+generic_wifi_init_module	platforms/rk3128-generic-wlan.c	/^static __init int generic_wifi_init_module(void)$/;"	f	file:	signature:(void)
+generic_wifi_init_module	platforms/rk322x-generic-wlan.c	/^EXPORT_SYMBOL(generic_wifi_init_module);$/;"	v
+generic_wifi_init_module	platforms/rk322x-generic-wlan.c	/^module_init(generic_wifi_init_module);$/;"	v
+generic_wifi_init_module	platforms/rk322x-generic-wlan.c	/^static __init int generic_wifi_init_module(void)$/;"	f	file:	signature:(void)
+generic_wifi_init_module	platforms/t10-generic-wlan.c	/^EXPORT_SYMBOL(generic_wifi_init_module);$/;"	v
+generic_wifi_init_module	platforms/t10-generic-wlan.c	/^late_initcall(generic_wifi_init_module);$/;"	v
+generic_wifi_init_module	platforms/t10-generic-wlan.c	/^module_init(generic_wifi_init_module);$/;"	v
+generic_wifi_init_module	platforms/t10-generic-wlan.c	/^static int generic_wifi_init_module(void)$/;"	f	file:	signature:(void)
+generic_wifi_init_module	platforms/t20-generic-wlan.c	/^EXPORT_SYMBOL(generic_wifi_init_module);$/;"	v
+generic_wifi_init_module	platforms/t20-generic-wlan.c	/^late_initcall(generic_wifi_init_module);$/;"	v
+generic_wifi_init_module	platforms/t20-generic-wlan.c	/^module_init(generic_wifi_init_module);$/;"	v
+generic_wifi_init_module	platforms/t20-generic-wlan.c	/^static int generic_wifi_init_module(void)$/;"	f	file:	signature:(void)
+generic_wifi_init_module	platforms/x1000-generic-wlan.c	/^EXPORT_SYMBOL(generic_wifi_init_module);$/;"	v
+generic_wifi_init_module	platforms/x1000-generic-wlan.c	/^late_initcall(generic_wifi_init_module);$/;"	v
+generic_wifi_init_module	platforms/x1000-generic-wlan.c	/^module_init(generic_wifi_init_module);$/;"	v
+generic_wifi_init_module	platforms/x1000-generic-wlan.c	/^static int generic_wifi_init_module(void)$/;"	f	file:	signature:(void)
+generic_wifi_init_module	platforms/xm-hi3518-generic-wlan.c	/^EXPORT_SYMBOL(generic_wifi_init_module);$/;"	v
+generic_wifi_init_module	platforms/xm-hi3518-generic-wlan.c	/^module_init(generic_wifi_init_module);$/;"	v
+generic_wifi_init_module	platforms/xm-hi3518-generic-wlan.c	/^static __init int generic_wifi_init_module(void)$/;"	f	file:	signature:(void)
+get_bcn_ongoing	smac/dev.h	/^    bool (*get_bcn_ongoing)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+get_chip_id	smac/dev.h	/^    void (*get_chip_id)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+get_country_code	platforms/a33-generic-wlan.c	/^    void *(*get_country_code)(char *ccode);$/;"	m	struct:wifi_platform_data	file:	access:public
+get_country_code	platforms/atm7039-action-generic-wlan.c	/^ void *(*get_country_code)(char *ccode);$/;"	m	struct:wifi_platform_data	file:	access:public
+get_country_code	platforms/h3-generic-wlan.c	/^ void *(*get_country_code)(char *ccode);$/;"	m	struct:wifi_platform_data	file:	access:public
+get_country_code	platforms/h8-generic-wlan.c	/^ void *(*get_country_code)(char *ccode);$/;"	m	struct:wifi_platform_data	file:	access:public
+get_country_code	platforms/rk3126-generic-wlan.c	/^    void *(*get_country_code)(char *ccode);$/;"	m	struct:wifi_platform_data	file:	access:public
+get_country_code	platforms/t10-generic-wlan.c	/^ void *(*get_country_code)(char *ccode);$/;"	m	struct:wifi_platform_data	file:	access:public
+get_country_code	platforms/x1000-generic-wlan.c	/^ void *(*get_country_code)(char *ccode);$/;"	m	struct:wifi_platform_data	file:	access:public
+get_crypto_ccmp_ops	smac/sec.h	/^struct ssv_crypto_ops *get_crypto_ccmp_ops(void);$/;"	p	signature:(void)
+get_crypto_ccmp_ops	smac/sec_ccmp.c	/^struct ssv_crypto_ops *get_crypto_ccmp_ops(void)$/;"	f	signature:(void)
+get_crypto_tkip_ops	smac/sec.h	/^struct ssv_crypto_ops *get_crypto_tkip_ops(void);$/;"	p	signature:(void)
+get_crypto_tkip_ops	smac/sec_tkip.c	/^struct ssv_crypto_ops *get_crypto_tkip_ops(void)$/;"	f	signature:(void)
+get_crypto_wep_ops	smac/sec.h	/^struct ssv_crypto_ops *get_crypto_wep_ops(void);$/;"	p	signature:(void)
+get_crypto_wep_ops	smac/sec_wep.c	/^struct ssv_crypto_ops *get_crypto_wep_ops (void)$/;"	f	signature:(void)
+get_crypto_wpi_ops	smac/sec.h	/^struct ssv_crypto_ops *get_crypto_wpi_ops(void);$/;"	p	signature:(void)
+get_crypto_wpi_ops	smac/sec_wpi.c	/^struct ssv_crypto_ops *get_crypto_wpi_ops(void)$/;"	f	signature:(void)
+get_ffout_cnt	smac/dev.h	/^ u32 (*get_ffout_cnt)(u32 value, int tag);$/;"	m	struct:ssv_hal_ops	access:public
+get_flags	smac/sec.h	/^ unsigned long (*get_flags) (void *priv);$/;"	m	struct:ssv_crypto_ops	access:public
+get_fw_name	smac/dev.h	/^    void (*get_fw_name)(u8 *fw_name);$/;"	m	struct:ssv_hal_ops	access:public
+get_fw_version	smac/dev.h	/^    void (*get_fw_version)(struct ssv_hw *sh, u32 *regval);$/;"	m	struct:ssv_hal_ops	access:public
+get_ic_time_tag	smac/dev.h	/^    u64 (*get_ic_time_tag)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+get_in_ffcnt	smac/dev.h	/^ u32 (*get_in_ffcnt)(u32 value, int tag);$/;"	m	struct:ssv_hal_ops	access:public
+get_key	smac/sec.h	/^ int (*get_key) (void *key, int len, u8 * seq, void *priv);$/;"	m	struct:ssv_crypto_ops	access:public
+get_mac_addr	platforms/a33-generic-wlan.c	/^    int (*get_mac_addr)(unsigned char *buf);$/;"	m	struct:wifi_platform_data	file:	access:public
+get_mac_addr	platforms/atm7039-action-generic-wlan.c	/^ int (*get_mac_addr)(unsigned char *buf);$/;"	m	struct:wifi_platform_data	file:	access:public
+get_mac_addr	platforms/h3-generic-wlan.c	/^ int (*get_mac_addr)(unsigned char *buf);$/;"	m	struct:wifi_platform_data	file:	access:public
+get_mac_addr	platforms/h8-generic-wlan.c	/^ int (*get_mac_addr)(unsigned char *buf);$/;"	m	struct:wifi_platform_data	file:	access:public
+get_mac_addr	platforms/rk3126-generic-wlan.c	/^    int (*get_mac_addr)(unsigned char *buf);$/;"	m	struct:wifi_platform_data	file:	access:public
+get_mac_addr	platforms/t10-generic-wlan.c	/^ int (*get_mac_addr)(unsigned char *buf);$/;"	m	struct:wifi_platform_data	file:	access:public
+get_mac_addr	platforms/x1000-generic-wlan.c	/^ int (*get_mac_addr)(unsigned char *buf);$/;"	m	struct:wifi_platform_data	file:	access:public
+get_mrx_mode	smac/dev.h	/^    void (*get_mrx_mode)(struct ssv_hw *sh, u32 *regval);$/;"	m	struct:ssv_hal_ops	access:public
+get_phy_table_size	smac/dev.h	/^    u32 (*get_phy_table_size)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+get_rd_id_adr	smac/dev.h	/^    void (*get_rd_id_adr)(u32 *id_base_address);$/;"	m	struct:ssv_hal_ops	access:public
+get_rf_table_size	smac/dev.h	/^    u32 (*get_rf_table_size)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+get_rx_desc_ctype	smac/dev.h	/^    u32 (*get_rx_desc_ctype)(struct sk_buff *skb);$/;"	m	struct:ssv_hal_ops	access:public
+get_rx_desc_hdr_offset	smac/dev.h	/^    int (*get_rx_desc_hdr_offset)(struct sk_buff *skb);$/;"	m	struct:ssv_hal_ops	access:public
+get_rx_desc_info	smac/dev.h	/^    void (*get_rx_desc_info)(struct sk_buff *skb, u32 *packet_len, u32 *ctype,$/;"	m	struct:ssv_hal_ops	access:public
+get_rx_desc_length	smac/dev.h	/^    int (*get_rx_desc_length)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+get_rx_desc_mng_used	smac/dev.h	/^    u32 (*get_rx_desc_mng_used)(struct sk_buff *skb);$/;"	m	struct:ssv_hal_ops	access:public
+get_rx_desc_rate_idx	smac/dev.h	/^    u32 (*get_rx_desc_rate_idx)(struct sk_buff *skb);$/;"	m	struct:ssv_hal_ops	access:public
+get_rx_desc_size	smac/dev.h	/^    int (*get_rx_desc_size)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+get_rx_desc_wsid	smac/dev.h	/^    u32 (*get_rx_desc_wsid)(struct sk_buff *skb);$/;"	m	struct:ssv_hal_ops	access:public
+get_sec_decode_err	smac/dev.h	/^    int (*get_sec_decode_err)(struct sk_buff *skb, bool *mic_err, bool *decode_err);$/;"	m	struct:ssv_hal_ops	access:public
+get_si_pass	smac/kssvsmart.c	/^int get_si_pass(char *input)$/;"	f	signature:(char *input)
+get_si_pass	smac/kssvsmart.h	/^int get_si_pass(char *input);$/;"	p	signature:(char *input)
+get_si_ssid	smac/kssvsmart.c	/^int get_si_ssid(char *input)$/;"	f	signature:(char *input)
+get_si_ssid	smac/kssvsmart.h	/^int get_si_ssid(char *input);$/;"	p	signature:(char *input)
+get_si_status	smac/kssvsmart.c	/^int get_si_status(char *input)$/;"	f	signature:(char *input)
+get_si_status	smac/kssvsmart.h	/^int get_si_status(char *input);$/;"	p	signature:(char *input)
+get_tid_aggr_len	smac/ampdu.c	36;"	d	file:
+get_tx_desc_ctype	smac/dev.h	/^    int (*get_tx_desc_ctype)(struct sk_buff *skb );$/;"	m	struct:ssv_hal_ops	access:public
+get_tx_desc_reason	smac/dev.h	/^    int (*get_tx_desc_reason)(struct sk_buff *skb );$/;"	m	struct:ssv_hal_ops	access:public
+get_tx_desc_size	smac/dev.h	/^    int (*get_tx_desc_size)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+get_tx_desc_txq_idx	smac/dev.h	/^    int (*get_tx_desc_txq_idx)(struct sk_buff *skb );$/;"	m	struct:ssv_hal_ops	access:public
+get_url	ver_info.pl	/^sub get_url {$/;"	s
+get_version	ver_info.pl	/^sub get_version {$/;"	s
+get_wsid	smac/dev.h	/^    int (*get_wsid)(struct ssv_softc *sc, struct ieee80211_vif *vif,$/;"	m	struct:ssv_hal_ops	access:public
+glue	bridge/sdiobridge.c	/^static struct ssv_sdiobridge_glue *glue;$/;"	v	typeref:struct:ssv_sdiobridge_glue	file:
+glue	hwif/usb/usb.h	/^    struct ssv6xxx_usb_glue *glue;$/;"	m	struct:ssv6xxx_rx_buf	typeref:struct:ssv6xxx_rx_buf::ssv6xxx_usb_glue	access:public
+glue	hwif/usb/usb.h	/^    struct ssv6xxx_usb_glue *glue;$/;"	m	struct:ssv6xxx_usb_work_struct	typeref:struct:ssv6xxx_usb_work_struct::ssv6xxx_usb_glue	access:public
+gnl_fd	smartlink/ssv_smartlink.c	/^static int gnl_fd=-1;$/;"	v	file:
+gnl_id	smartlink/ssv_smartlink.c	/^static int gnl_id=GLOBAL_NL_ID;$/;"	v	file:
+green_pwr	smac/dev.h	/^    u8 green_pwr;$/;"	m	struct:ssv_softc	access:public
+greentx	include/ssv_cfg.h	/^    u32 greentx;$/;"	m	struct:ssv6xxx_cfg	access:public
+group_cipher	smac/dev.h	/^    u32 group_cipher;$/;"	m	struct:ssv_vif_priv_data	access:public
+group_cipher_type	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 group_cipher_type;$/;"	m	struct:ssv6006_bss	access:public
+group_id	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^    unsigned long long group_id;$/;"	m	struct:tag_tx_barrage_msg	access:public
+group_idx	smac/ssv_rc_minstrel_ht.h	/^ u8 group_idx;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+group_key	smac/drv_comm.h	/^    struct ssv6xxx_hw_key group_key[3];$/;"	m	struct:ssv6xxx_hw_sec	typeref:struct:ssv6xxx_hw_sec::ssv6xxx_hw_key	access:public
+group_key	smac/hal/ssv6006c/ssv6006_mac.h	/^ struct ssv6006_hw_key group_key[4];$/;"	m	struct:ssv6006_bss	typeref:struct:ssv6006_bss::ssv6006_hw_key	access:public
+group_key_idx	smac/dev.h	/^    u8 group_key_idx;$/;"	m	struct:ssv_sta_priv_data	access:public
+group_key_idx	smac/dev.h	/^    u8 group_key_idx;$/;"	m	struct:ssv_vif_priv_data	access:public
+group_key_idx	smac/drv_comm.h	/^ u8 group_key_idx:4;$/;"	m	struct:ssv6xxx_hw_sta_key	access:public
+group_key_idx	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 group_key_idx;$/;"	m	struct:ssv6006_bss	access:public
+group_name	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^    char * group_name;$/;"	m	struct:tag_tx_barrage_msg	access:public
+group_wpa_use_hw_cipher	smac/dev.h	/^    bool (*group_wpa_use_hw_cipher)(struct ssv_softc *sc,$/;"	m	struct:ssv_hal_ops	access:public
+groups	smac/ssv_rc_common.h	/^    struct minstrel_mcs_group_data groups;$/;"	m	struct:ssv62xx_ht	typeref:struct:ssv62xx_ht::minstrel_mcs_group_data	access:public
+groups	smac/ssv_rc_minstrel_ht.h	/^  struct ssv_minstrel_ht_mcs_group_data groups[MINSTREL_MAX_STREAMS * MINSTREL_STREAM_GROUPS + 1];$/;"	m	struct:ssv_minstrel_ht_sta	typeref:struct:ssv_minstrel_ht_sta::ssv_minstrel_ht_mcs_group_data	access:public
+gt_channel	smac/dev.h	/^    u8 gt_channel;$/;"	m	struct:ssv_softc	access:public
+gt_enabled	smac/dev.h	/^    bool gt_enabled;$/;"	m	struct:ssv_softc	access:public
+gt_max_attenuation	include/ssv_cfg.h	/^    u32 gt_max_attenuation;$/;"	m	struct:ssv6xxx_cfg	access:public
+gt_stepsize	include/ssv_cfg.h	/^    u32 gt_stepsize;$/;"	m	struct:ssv6xxx_cfg	access:public
+guid	smartlink/qqlink-lib-mipsel/include/TXOldInf.h	/^    char * guid;$/;"	m	struct:tag_tx_ccmsg_inst_info	access:public
+guid_len	smartlink/qqlink-lib-mipsel/include/TXOldInf.h	/^    int guid_len;$/;"	m	struct:tag_tx_ccmsg_inst_info	access:public
+guid_length	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^    int guid_length;$/;"	m	struct:tag_tx_image_msg_element	access:public
+guide_words	smartlink/qqlink-lib-mipsel/include/TXMsg.h	/^    char* guide_words;$/;"	m	struct:tag_structuring_msg	access:public
+h0	crypto/sha1_glue.c	/^ uint32_t h0,h1,h2,h3,h4;$/;"	m	struct:SHA1_CTX	file:	access:public
+h1	crypto/sha1_glue.c	/^ uint32_t h0,h1,h2,h3,h4;$/;"	m	struct:SHA1_CTX	file:	access:public
+h2	crypto/sha1_glue.c	/^ uint32_t h0,h1,h2,h3,h4;$/;"	m	struct:SHA1_CTX	file:	access:public
+h3	crypto/sha1_glue.c	/^ uint32_t h0,h1,h2,h3,h4;$/;"	m	struct:SHA1_CTX	file:	access:public
+h4	crypto/sha1_glue.c	/^ uint32_t h0,h1,h2,h3,h4;$/;"	m	struct:SHA1_CTX	file:	access:public
+h_cmd	include/ssv6xxx_common.h	/^    u32 h_cmd:8;$/;"	m	struct:cfg_host_cmd	access:public
+h_event	include/ssv6xxx_common.h	/^    u32 h_event :8;$/;"	m	struct:cfg_host_event	access:public
+hal_ops	smac/dev.h	/^    struct ssv_hal_ops hal_ops;$/;"	m	struct:ssv_hw	typeref:struct:ssv_hw::ssv_hal_ops	access:public
+handle_stop	ap_launch.sh	/^function handle_stop() {$/;"	f
+handle_stop	launch_ap_sta.sh	/^function handle_stop() {$/;"	f
+handle_stop	launch_sta_ap.sh	/^function handle_stop() {$/;"	f
+handle_stop	script/ap-aes.sh	/^function handle_stop() {$/;"	f
+handle_stop	script/ap-tkip.sh	/^function handle_stop() {$/;"	f
+handle_stop	script/load_ap_sta.sh	/^function handle_stop() {$/;"	f
+has_hw_decrypt	smac/dev.h	/^    bool has_hw_decrypt;$/;"	m	struct:ssv_sta_priv_data	access:public
+has_hw_decrypt	smac/dev.h	/^    bool has_hw_decrypt;$/;"	m	struct:ssv_vif_priv_data	access:public
+has_hw_encrypt	smac/dev.h	/^    bool has_hw_encrypt;$/;"	m	struct:ssv_sta_priv_data	access:public
+has_hw_encrypt	smac/dev.h	/^    bool has_hw_encrypt;$/;"	m	struct:ssv_vif_priv_data	access:public
+has_mrr	smac/ssv_rc_minstrel.h	/^ bool has_mrr;$/;"	m	struct:ssv_minstrel_priv	access:public
+hci	hci_wrapper/ssv_huw.c	/^    struct ssv6xxx_hci_info hci;$/;"	m	struct:ssv_huw_dev	typeref:struct:ssv_huw_dev::ssv6xxx_hci_info	file:	access:public
+hci	smac/dev.h	/^    struct ssv6xxx_hci_info hci;$/;"	m	struct:ssv_hw	typeref:struct:ssv_hw::ssv6xxx_hci_info	access:public
+hci_burst_read_word	hci/ssv_hci.h	/^    int (*hci_burst_read_word)(struct ssv6xxx_hci_ctrl *hctrl, u32 *addr, u32 *regval, u8 reg_amount);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+hci_burst_safe_read_word	hci/ssv_hci.h	/^    int (*hci_burst_safe_read_word)(struct ssv6xxx_hci_ctrl *hctrl, u32 *addr, u32 *regval, u8 reg_amount);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+hci_burst_safe_write_word	hci/ssv_hci.h	/^    int (*hci_burst_safe_write_word)(struct ssv6xxx_hci_ctrl *hctrl, u32 *addr, u32 *regval, u8 reg_amount);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+hci_burst_write_word	hci/ssv_hci.h	/^    int (*hci_burst_write_word)(struct ssv6xxx_hci_ctrl *hctrl, u32 *addr, u32 *regval, u8 reg_amount);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+hci_ctrl	hci/ssv_hci.h	/^    struct ssv6xxx_hci_ctrl *hci_ctrl;$/;"	m	struct:ssv6xxx_hci_info	typeref:struct:ssv6xxx_hci_info::ssv6xxx_hci_ctrl	access:public
+hci_deinit_debugfs	hci/ssv_hci.h	/^    void (*hci_deinit_debugfs)(struct ssv6xxx_hci_ctrl *hctrl);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+hci_flags	hci/hctrl.h	/^    u32 hci_flags;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+hci_init_debugfs	hci/ssv_hci.h	/^    bool (*hci_init_debugfs)(struct ssv6xxx_hci_ctrl *hctrl, struct dentry *dev_deugfs_dir);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+hci_interface_reset	hci/ssv_hci.h	/^    int (*hci_interface_reset)(struct ssv6xxx_hci_ctrl *hctrl);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+hci_is_rx_q_full	hci/ssv_hci.h	/^    int (*hci_is_rx_q_full)(void *);$/;"	m	struct:ssv6xxx_hci_info	access:public
+hci_load_fw	hci/ssv_hci.h	/^    int (*hci_load_fw)(struct ssv6xxx_hci_ctrl *hctrl, u8 *firmware_name, u8 openfile);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+hci_mutex	hci/hctrl.h	/^    struct mutex hci_mutex;$/;"	m	struct:ssv6xxx_hci_ctrl	typeref:struct:ssv6xxx_hci_ctrl::mutex	access:public
+hci_ops	hci/ssv_hci.c	/^static struct ssv6xxx_hci_ops hci_ops =$/;"	v	typeref:struct:ssv6xxx_hci_ops	file:
+hci_ops	hci/ssv_hci.h	/^    struct ssv6xxx_hci_ops *hci_ops;$/;"	m	struct:ssv6xxx_hci_info	typeref:struct:ssv6xxx_hci_info::ssv6xxx_hci_ops	access:public
+hci_peek_next_pkt_len_cb	hci/ssv_hci.h	/^    int (*hci_peek_next_pkt_len_cb)(struct sk_buff *, void *);$/;"	m	struct:ssv6xxx_hci_info	access:public
+hci_pmu_wakeup	hci/ssv_hci.h	/^    int (*hci_pmu_wakeup)(struct ssv6xxx_hci_ctrl *hctrl);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+hci_post_tx_cb	hci/ssv_hci.h	/^    void (*hci_post_tx_cb)(struct sk_buff_head *, void *);$/;"	m	struct:ssv6xxx_hci_info	access:public
+hci_pre_tx_cb	hci/ssv_hci.h	/^    void (*hci_pre_tx_cb)(struct sk_buff *, void *);$/;"	m	struct:ssv6xxx_hci_info	access:public
+hci_read_word	hci/ssv_hci.h	/^    int (*hci_read_word)(struct ssv6xxx_hci_ctrl *hctrl, u32 addr, u32 *regval);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+hci_rx_aggr_info	include/ssv6xxx_common.h	/^struct hci_rx_aggr_info {$/;"	s
+hci_rx_aggr_info::RSVD0	include/ssv6xxx_common.h	/^    u32 RSVD0:15;$/;"	m	struct:hci_rx_aggr_info	access:public
+hci_rx_aggr_info::RSVD1	include/ssv6xxx_common.h	/^    u32 RSVD1:4;$/;"	m	struct:hci_rx_aggr_info	access:public
+hci_rx_aggr_info::accu_rx_len	include/ssv6xxx_common.h	/^    u32 accu_rx_len:16;$/;"	m	struct:hci_rx_aggr_info	access:public
+hci_rx_aggr_info::edca0	include/ssv6xxx_common.h	/^    u32 edca0:4;$/;"	m	struct:hci_rx_aggr_info	access:public
+hci_rx_aggr_info::edca1	include/ssv6xxx_common.h	/^    u32 edca1:5;$/;"	m	struct:hci_rx_aggr_info	access:public
+hci_rx_aggr_info::edca2	include/ssv6xxx_common.h	/^    u32 edca2:5;$/;"	m	struct:hci_rx_aggr_info	access:public
+hci_rx_aggr_info::edca3	include/ssv6xxx_common.h	/^    u32 edca3:5;$/;"	m	struct:hci_rx_aggr_info	access:public
+hci_rx_aggr_info::edca4	include/ssv6xxx_common.h	/^    u32 edca4:4;$/;"	m	struct:hci_rx_aggr_info	access:public
+hci_rx_aggr_info::edca5	include/ssv6xxx_common.h	/^    u32 edca5:5;$/;"	m	struct:hci_rx_aggr_info	access:public
+hci_rx_aggr_info::jmp_mpdu_len	include/ssv6xxx_common.h	/^    u32 jmp_mpdu_len:16;$/;"	m	struct:hci_rx_aggr_info	access:public
+hci_rx_aggr_info::tx_id_remain	include/ssv6xxx_common.h	/^    u32 tx_id_remain:8;$/;"	m	struct:hci_rx_aggr_info	access:public
+hci_rx_aggr_info::tx_page_remain	include/ssv6xxx_common.h	/^    u32 tx_page_remain:9;$/;"	m	struct:hci_rx_aggr_info	access:public
+hci_rx_cb	hci/ssv_hci.h	/^    int (*hci_rx_cb)(struct sk_buff *, void *);$/;"	m	struct:ssv6xxx_hci_info	access:public
+hci_rx_cb	hci/ssv_hci.h	/^    int (*hci_rx_cb)(struct sk_buff_head *, void *);$/;"	m	struct:ssv6xxx_hci_info	access:public
+hci_rx_mode_cb	hci/ssv_hci.h	/^    int (*hci_rx_mode_cb)(void *);$/;"	m	struct:ssv6xxx_hci_info	access:public
+hci_rx_work	hci/hctrl.h	/^    struct work_struct hci_rx_work;$/;"	m	struct:ssv6xxx_hci_ctrl	typeref:struct:ssv6xxx_hci_ctrl::work_struct	access:public
+hci_safe_read_word	hci/ssv_hci.h	/^    int (*hci_safe_read_word)(struct ssv6xxx_hci_ctrl *hctrl, u32 addr, u32 *regval);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+hci_safe_write_word	hci/ssv_hci.h	/^    int (*hci_safe_write_word)(struct ssv6xxx_hci_ctrl *hctrl, u32 addr, u32 regval);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+hci_send_cmd	hci/ssv_hci.h	/^    int (*hci_send_cmd)(struct ssv6xxx_hci_ctrl *hctrl, struct sk_buff *);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+hci_skb_update_cb	hci/ssv_hci.h	/^    void (*hci_skb_update_cb)(struct sk_buff *, void *);$/;"	m	struct:ssv6xxx_hci_info	access:public
+hci_start	hci/hctrl.h	/^    bool hci_start;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+hci_start	hci/ssv_hci.h	/^    int (*hci_start)(struct ssv6xxx_hci_ctrl *hctrl);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+hci_stop	hci/ssv_hci.h	/^    int (*hci_stop)(struct ssv6xxx_hci_ctrl *hctrl);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+hci_sysplf_reset	hci/ssv_hci.h	/^    int (*hci_sysplf_reset)(struct ssv6xxx_hci_ctrl *hctrl, u32 addr, u32 value);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+hci_tx	hci/ssv_hci.h	/^    int (*hci_tx)(struct ssv6xxx_hci_ctrl *hctrl, struct sk_buff *, int, u32);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+hci_tx_buf_free_cb	hci/ssv_hci.h	/^    void (*hci_tx_buf_free_cb)(struct sk_buff *, void *);$/;"	m	struct:ssv6xxx_hci_info	access:public
+hci_tx_flow_ctrl_cb	hci/ssv_hci.h	/^    int (*hci_tx_flow_ctrl_cb)(void *, int, bool, int debug);$/;"	m	struct:ssv6xxx_hci_info	access:public
+hci_tx_pause	hci/ssv_hci.h	/^    int (*hci_tx_pause)(struct ssv6xxx_hci_ctrl *hctrl, u32 txq_mask);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+hci_tx_q_empty_cb	hci/ssv_hci.h	/^    void (*hci_tx_q_empty_cb)(u32 txq_no, void *);$/;"	m	struct:ssv6xxx_hci_info	access:public
+hci_tx_resume	hci/ssv_hci.h	/^    int (*hci_tx_resume)(struct ssv6xxx_hci_ctrl *hctrl, u32 txq_mask);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+hci_tx_task	hci/hctrl.h	/^ struct task_struct *hci_tx_task;$/;"	m	struct:ssv6xxx_hci_ctrl	typeref:struct:ssv6xxx_hci_ctrl::task_struct	access:public
+hci_tx_work	hci/hctrl.h	/^    struct work_struct hci_tx_work;$/;"	m	struct:ssv6xxx_hci_ctrl	typeref:struct:ssv6xxx_hci_ctrl::work_struct	access:public
+hci_tx_work	hci/hctrl.h	/^    struct work_struct hci_tx_work[SSV_HW_TXQ_NUM];$/;"	m	struct:ssv6xxx_hci_ctrl	typeref:struct:ssv6xxx_hci_ctrl::work_struct	access:public
+hci_txq_empty	hci/ssv_hci.h	/^    bool (*hci_txq_empty)(struct ssv6xxx_hci_ctrl *hctrl, int txqid);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+hci_txq_flush	hci/ssv_hci.h	/^    int (*hci_txq_flush)(struct ssv6xxx_hci_ctrl *hctrl, u32 txq_mask);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+hci_txq_flush_by_sta	hci/ssv_hci.h	/^    int (*hci_txq_flush_by_sta)(struct ssv6xxx_hci_ctrl *hctrl, int aid);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+hci_work_queue	hci/hctrl.h	/^    struct workqueue_struct *hci_work_queue;$/;"	m	struct:ssv6xxx_hci_ctrl	typeref:struct:ssv6xxx_hci_ctrl::workqueue_struct	access:public
+hci_write_hw_config	hci/ssv_hci.h	/^    void (*hci_write_hw_config)(struct ssv6xxx_hci_ctrl *hctrl, int val);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+hci_write_sram	hci/ssv_hci.h	/^    int (*hci_write_sram)(struct ssv6xxx_hci_ctrl *hctrl, u32 addr, u8* data, u32 size);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+hci_write_word	hci/ssv_hci.h	/^    int (*hci_write_word)(struct ssv6xxx_hci_ctrl *hctrl, u32 addr, u32 regval);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+hdr_len	include/ssv6200_common.h	/^    u32 hdr_len:6;$/;"	m	struct:ssv6200_rx_desc	access:public
+hdr_len	include/ssv6200_common.h	/^    u32 hdr_len:6;$/;"	m	struct:ssv6200_tx_desc	access:public
+hdr_len	smac/hal/ssv6006c/turismo_common.h	/^    u32 hdr_len:6;$/;"	m	struct:ssv6006_rx_desc	access:public
+hdr_len	smac/hal/ssv6006c/turismo_common.h	/^    u32 hdr_len:6;$/;"	m	struct:ssv6006_tx_desc	access:public
+hdr_offset	include/ssv6200_common.h	/^    u32 hdr_offset:8;$/;"	m	struct:ssv6200_rx_desc	access:public
+hdr_offset	include/ssv6200_common.h	/^    u32 hdr_offset:8;$/;"	m	struct:ssv6200_tx_desc	access:public
+hdr_offset	smac/hal/ssv6006c/turismo_common.h	/^    u32 hdr_offset:8;$/;"	m	struct:ssv6006_rx_desc	access:public
+hdr_offset	smac/hal/ssv6006c/turismo_common.h	/^    u32 hdr_offset:8;$/;"	m	struct:ssv6006_tx_desc	access:public
+head_length	smartlink/qqlink-lib-mipsel/include/TXAudioVideo.h	/^ unsigned char head_length;$/;"	m	struct:_tx_audio_encode_param	access:public
+head_url	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    char head_url[1024];$/;"	m	struct:tag_tx_binder_info	access:public
+hexdump	smartlink/ssv_smartlink.c	/^void hexdump(unsigned char *buf, int len)$/;"	f	signature:(unsigned char *buf, int len)
+house_keeping	smac/dev.h	/^    struct timer_list house_keeping;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::timer_list	access:public
+house_keeping_wq	smac/dev.h	/^    struct workqueue_struct *house_keeping_wq;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::workqueue_struct	access:public
+ht	include/ssv6200_common.h	/^    u32 ht:1;$/;"	m	struct:ssv6200_rx_desc	access:public
+ht	include/ssv6200_common.h	/^    u32 ht:1;$/;"	m	struct:ssv6200_tx_desc	access:public
+ht	smac/hal/ssv6006c/turismo_common.h	/^    u32 ht:1;$/;"	m	struct:ssv6006_rx_desc	access:public
+ht	smac/hal/ssv6006c/turismo_common.h	/^    u32 ht:1;$/;"	m	struct:ssv6006_tx_desc	access:public
+ht	smac/ssv_rc_common.h	/^    struct ssv62xx_ht ht;$/;"	m	struct:ssv_sta_rc_info	typeref:struct:ssv_sta_rc_info::ssv62xx_ht	access:public
+ht	smac/ssv_rc_minstrel.h	/^  struct ssv_minstrel_ht_sta ht;$/;"	m	union:ssv_minstrel_sta_priv::__anon16	typeref:struct:ssv_minstrel_sta_priv::__anon16::ssv_minstrel_ht_sta	access:public
+ht40	smac/dev.h	/^    u8 ht40;$/;"	m	struct:rx_stats	access:public
+ht40	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 ht40:1;$/;"	m	struct:ssv6006_rc_idx	access:public
+ht_config	smac/dev.h	/^    struct ssv_tempe_table ht_config;$/;"	m	struct:ssv_flash_config	typeref:struct:ssv_flash_config::ssv_tempe_table	access:public
+ht_rc_type	smac/ssv_rc_common.h	/^    u8 ht_rc_type;$/;"	m	struct:ssv_sta_rc_info	access:public
+ht_short_gi	include/ssv6200_common.h	/^    u32 ht_short_gi:1;$/;"	m	struct:ssv6200_rxphy_info	access:public
+ht_supp_rates	smac/ssv_rc_common.h	/^    u32 ht_supp_rates;$/;"	m	struct:ssv_sta_rc_info	access:public
+huw_id_table	hci_wrapper/ssv_huw.c	/^static const struct platform_device_id huw_id_table[] = {$/;"	v	typeref:struct:platform_device_id	file:
+hw	smac/dev.h	/^    struct ieee80211_hw *hw;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::ieee80211_hw	access:public
+hw_buf_ptr	smac/dev.h	/^    u32 hw_buf_ptr;$/;"	m	struct:ssv_hw	access:public
+hw_buf_ptr	smac/dev.h	/^    u32 hw_buf_ptr[SSV_RC_MAX_STA];$/;"	m	struct:ssv_hw	access:public
+hw_caps	include/ssv_cfg.h	/^    u32 hw_caps;$/;"	m	struct:ssv6xxx_cfg	access:public
+hw_cfg	smac/dev.h	/^    struct list_head hw_cfg;$/;"	m	struct:ssv_hw	typeref:struct:ssv_hw::list_head	access:public
+hw_cfg_mutex	smac/dev.h	/^    struct mutex hw_cfg_mutex;$/;"	m	struct:ssv_hw	typeref:struct:ssv_hw::mutex	access:public
+hw_chan	smac/dev.h	/^    u16 hw_chan;$/;"	m	struct:ssv_softc	access:public
+hw_chan_type	smac/dev.h	/^    u16 hw_chan_type;$/;"	m	struct:ssv_softc	access:public
+hw_crypto_key_clear	smac/dev.c	/^static void hw_crypto_key_clear(struct ieee80211_hw *hw, int index, struct ieee80211_key_conf *key,$/;"	f	file:	signature:(struct ieee80211_hw *hw, int index, struct ieee80211_key_conf *key, struct ssv_vif_priv_data *vif_priv, struct ssv_sta_priv_data *sta_priv)
+hw_crypto_key_write_wep	smac/dev.c	/^static int hw_crypto_key_write_wep(struct ssv_softc *sc,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ieee80211_key_conf *keyconf, u8 algorithm, struct ssv_vif_info *vif_info)
+hw_crypto_key_write_wep	smac/dev.h	/^    int (*hw_crypto_key_write_wep) (struct ssv_softc *sc, struct ieee80211_key_conf *keyconf, u8 algorithm, struct ssv_vif_info *vif_info);$/;"	m	struct:ssv_hal_ops	access:public
+hw_mng_used	smac/dev.h	/^    u8 hw_mng_used;$/;"	m	struct:ssv_softc	access:public
+hw_pinfo	smac/dev.h	/^    u32 hw_pinfo;$/;"	m	struct:ssv_hw	access:public
+hw_rate_desc	smac/ssv_rc_minstrel.h	/^ u8 hw_rate_desc;$/;"	m	struct:ssv_minstrel_rate	access:public
+hw_rate_idx	smac/ssv_rc_common.h	/^    u8 hw_rate_idx;$/;"	m	struct:ssv_rc_rate	access:public
+hw_restart_work	smac/dev.h	/^    struct work_struct hw_restart_work;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::work_struct	access:public
+hw_retry_acc	smac/ssv_rc_minstrel_ht.h	/^ u32 hw_retry_acc;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+hw_rx_agg_cnt	include/ssv_cfg.h	/^    u32 hw_rx_agg_cnt;$/;"	m	struct:ssv6xxx_cfg	access:public
+hw_rx_agg_method_3	include/ssv_cfg.h	/^    bool hw_rx_agg_method_3;$/;"	m	struct:ssv6xxx_cfg	access:public
+hw_rx_agg_timer_reload	include/ssv_cfg.h	/^    u32 hw_rx_agg_timer_reload;$/;"	m	struct:ssv6xxx_cfg	access:public
+hw_sec_key	smac/dev.h	/^    u32 hw_sec_key;$/;"	m	struct:ssv_hw	access:public
+hw_sec_key	smac/dev.h	/^    u32 hw_sec_key[SSV_RC_MAX_STA];$/;"	m	struct:ssv_hw	access:public
+hw_security	include/ssv6xxx_common.h	/^    u8 hw_security;$/;"	m	struct:ssv6xxx_wsid_params	access:public
+hw_success_acc	smac/ssv_rc_minstrel_ht.h	/^    u32 hw_success_acc;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+hw_txq	hci/hctrl.h	/^    struct ssv_hw_txq hw_txq[SSV_HW_TXQ_NUM];$/;"	m	struct:ssv6xxx_hci_ctrl	typeref:struct:ssv6xxx_hci_ctrl::ssv_hw_txq	access:public
+hw_txq_len_fops	hci/ssv_hci.c	/^struct file_operations hw_txq_len_fops = {$/;"	v	typeref:struct:file_operations
+hw_txq_len_open	hci/ssv_hci.c	/^static int hw_txq_len_open(struct inode *inode, struct file *filp)$/;"	f	file:	signature:(struct inode *inode, struct file *filp)
+hw_txq_len_read	hci/ssv_hci.c	/^static ssize_t hw_txq_len_read(struct file *filp, char __user *buffer, size_t count, loff_t *ppos)$/;"	f	file:	signature:(struct file *filp, char __user *buffer, size_t count, loff_t *ppos)
+hw_txqid	smac/dev.h	/^    int hw_txqid[WMM_NUM_AC];$/;"	m	struct:ssv_tx	access:public
+hw_update_watch_wsid	smac/dev.c	/^int hw_update_watch_wsid(struct ssv_softc *sc, struct ieee80211_sta *sta,$/;"	f	signature:(struct ssv_softc *sc, struct ieee80211_sta *sta, struct ssv_sta_info *sta_info, int sta_idx, int rx_hw_sec, int ops)
+hw_update_watch_wsid	smac/dev.h	/^int hw_update_watch_wsid(struct ssv_softc *sc, struct ieee80211_sta *sta,$/;"	p	signature:(struct ssv_softc *sc, struct ieee80211_sta *sta, struct ssv_sta_info *sta_info, int sta_idx, int rx_hw_sec, int ops)
+hw_wsid	smac/dev.h	/^    int hw_wsid;$/;"	m	struct:ssv_sta_info	access:public
+hw_wsid_bit	smac/dev.h	/^    u8 hw_wsid_bit;$/;"	m	struct:ssv_softc	access:public
+hwif_rx_task	hwif/hwif.h	/^    void (*hwif_rx_task)(struct device *child, int (*rx_cb)(struct sk_buff *rx_skb, void *args), int (*is_rx_q_full)(void *args), void *args, u32 *pkt);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+hwif_rx_task	hwif/hwif.h	/^    void (*hwif_rx_task)(struct device *child, int (*rx_cb)(struct sk_buff_head *rxq, void *args), int (*is_rx_q_full)(void *args), void *args, u32 *pkt);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+ic	smac/hal/ssv6006c/ssv6006_mac.h	/^    u16 ic;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+icomm_chipup_sem	platforms/aml-s805-generic-wlan.c	/^struct semaphore icomm_chipup_sem;$/;"	v	typeref:struct:semaphore
+icomm_chipup_sem	platforms/aml-s905-generic-wlan.c	/^struct semaphore icomm_chipup_sem;$/;"	v	typeref:struct:semaphore
+icomm_wake_lock	platforms/a33-generic-wlan.c	/^struct wake_lock icomm_wake_lock;$/;"	v	typeref:struct:wake_lock
+icomm_wake_lock	platforms/rk3126-generic-wlan.c	/^struct wake_lock icomm_wake_lock;$/;"	v	typeref:struct:wake_lock
+icomm_wifi_control	platforms/rk3126-generic-wlan.c	/^static struct wifi_platform_data icomm_wifi_control = {$/;"	v	typeref:struct:wifi_platform_data	file:
+icomm_wifi_device	platforms/rk3126-generic-wlan.c	/^static struct platform_device icomm_wifi_device = {$/;"	v	typeref:struct:platform_device	file:
+icomm_wifi_device_release	platforms/rk3126-generic-wlan.c	/^void icomm_wifi_device_release(struct device *dev)$/;"	f	signature:(struct device *dev)
+icomm_wifi_power	platforms/rk3126-generic-wlan.c	/^static int icomm_wifi_power(int on)$/;"	f	file:	signature:(int on)
+icomm_wifi_set_carddetect	platforms/rk3126-generic-wlan.c	/^int icomm_wifi_set_carddetect(int val)$/;"	f	signature:(int val)
+id	smartlink/qqlink-lib-mipsel/include/TXDataPoint.h	/^    unsigned int id;$/;"	m	struct:tag_tx_data_point	access:public
+ieee80211_ac_numbers	smac/linux_2_6_35.h	/^enum ieee80211_ac_numbers {$/;"	g
+ieee80211_frame_duration	smac/ssv_rc_minstrel.c	/^int ieee80211_frame_duration(enum nl80211_band band, size_t len,$/;"	f	signature:(enum nl80211_band band, size_t len, int rate, int erp, int short_preamble)
+ieee80211_frame_duration	smac/ssv_rc_minstrel.h	/^int ieee80211_frame_duration(enum ieee80211_band band, size_t len,$/;"	p	signature:(enum ieee80211_band band, size_t len, int rate, int erp, int short_preamble)
+ieee80211_frame_duration	smac/ssv_rc_minstrel.h	/^int ieee80211_frame_duration(enum nl80211_band band, size_t len,$/;"	p	signature:(enum nl80211_band band, size_t len, int rate, int erp, int short_preamble)
+if_chk_mac2	smac/dev.h	/^    bool (*if_chk_mac2)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+if_ops	hci/ssv_hci.h	/^    struct ssv6xxx_hwif_ops *if_ops;$/;"	m	struct:ssv6xxx_hci_info	typeref:struct:ssv6xxx_hci_info::ssv6xxx_hwif_ops	access:public
+if_type	smac/dev.h	/^    enum nl80211_iftype if_type;$/;"	m	struct:ssv_vif_info	typeref:enum:ssv_vif_info::nl80211_iftype	access:public
+ignore_efuse_mac	include/ssv_cfg.h	/^    u32 ignore_efuse_mac;$/;"	m	struct:ssv6xxx_cfg	access:public
+ignore_firmware_version	include/ssv_cfg.h	/^    u32 ignore_firmware_version;$/;"	m	struct:ssv6xxx_cfg	access:public
+image_guid	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^    char * image_guid;$/;"	m	struct:tag_tx_image_msg_element	access:public
+image_thumb_url	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^    char * image_thumb_url;$/;"	m	struct:tag_tx_image_msg_element	access:public
+image_url	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^    char * image_url;$/;"	m	struct:tag_tx_image_msg_element	access:public
+in_data	bridge/sdiobridge_pub.h	/^    u8* in_data;$/;"	m	struct:ssv_sdiobridge_cmd	access:public
+in_data	hci_wrapper/ssv_huw.h	/^    u8* in_data;$/;"	m	struct:ssv_huw_cmd	access:public
+in_data_len	bridge/sdiobridge_pub.h	/^    __u32 in_data_len;$/;"	m	struct:ssv_sdiobridge_cmd	access:public
+in_data_len	hci_wrapper/ssv_huw.h	/^    __u32 in_data_len;$/;"	m	struct:ssv_huw_cmd	access:public
+inc_pn_key	smac/sec_wpi.c	/^u8 *inc_pn_key(void *priv)$/;"	f	signature:(void *priv)
+index	smac/p2p.c	/^    u8 index;$/;"	m	struct:ssv6xxx_p2p_noa_attribute	file:	access:public
+index	smac/ssv_rc_common.h	/^    u16 index;$/;"	m	struct:rc_pid_rateinfo	access:public
+index	smac/ssv_rc_common.h	/^    u8 index;$/;"	m	struct:minstrel_mcs_group_data	access:public
+index	smac/ssv_rc_minstrel_ht.h	/^ u8 index;$/;"	m	struct:ssv_minstrel_ht_mcs_group_data	access:public
+init	smac/sec.h	/^ void *(*init) (int keyidx);$/;"	m	struct:ssv_crypto_ops	access:public
+initDevice	smartlink/qqlink-lib-mipsel/case/ipcamera/main.c	/^bool initDevice() {$/;"	f
+initDevice	smartlink/qqlink-lib-mipsel/demo_bind.c	/^bool initDevice() {$/;"	f
+initDevice	smartlink/qqlink-lib-mipsel/demo_filetransfer.c	/^bool initDevice() {$/;"	f
+initDevice	smartlink/qqlink-lib-mipsel/demo_video.c	/^bool initDevice() {$/;"	f
+initKernelEnv	smac/efuse.c	/^void initKernelEnv(void)$/;"	f	signature:(void)
+initWlan	platforms/a33-generic-wlan.c	/^int initWlan(void)$/;"	f	signature:(void)
+initWlan	platforms/ak3916-generic-wlan.c	/^int initWlan(void)$/;"	f	signature:(void)
+initWlan	platforms/aml-s805-generic-wlan.c	/^int initWlan(void)$/;"	f	signature:(void)
+initWlan	platforms/aml-s905-generic-wlan.c	/^int initWlan(void)$/;"	f	signature:(void)
+initWlan	platforms/atm7039-action-generic-wlan.c	/^int initWlan(void)$/;"	f	signature:(void)
+initWlan	platforms/h3-generic-wlan.c	/^int initWlan(void)$/;"	f	signature:(void)
+initWlan	platforms/h8-generic-wlan.c	/^int initWlan(void)$/;"	f	signature:(void)
+initWlan	platforms/rk3036-generic-wlan.c	/^int initWlan(void)$/;"	f	signature:(void)
+initWlan	platforms/rk3126-generic-wlan.c	/^int initWlan(void)$/;"	f	signature:(void)
+initWlan	platforms/rk3128-generic-wlan.c	/^int initWlan(void)$/;"	f	signature:(void)
+initWlan	platforms/rk322x-generic-wlan.c	/^int initWlan(void)$/;"	f	signature:(void)
+initWlan	platforms/t10-generic-wlan.c	/^int initWlan(void)$/;"	f	signature:(void)
+initWlan	platforms/t20-generic-wlan.c	/^int initWlan(void)$/;"	f	signature:(void)
+initWlan	platforms/x1000-generic-wlan.c	/^int initWlan(void)$/;"	f	signature:(void)
+initWlan	platforms/xm-hi3518-generic-wlan.c	/^int initWlan(void)$/;"	f	signature:(void)
+init_ch_cfg	smac/dev.h	/^    void (*init_ch_cfg)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+init_gpio_cfg	smac/dev.h	/^    void (*init_gpio_cfg)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+init_hw_sec_phy_table	smac/dev.h	/^    int (*init_hw_sec_phy_table)(struct ssv_softc *sc);$/;"	m	struct:ssv_hal_ops	access:public
+init_iqk	smac/dev.h	/^    void (*init_iqk)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+init_mac	smac/dev.h	/^    int (*init_mac)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+init_pll	smac/dev.h	/^    void (*init_pll)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+init_rx_cfg	smac/dev.h	/^    void (*init_rx_cfg)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+init_sample_table	smac/ssv_ht_rc.c	/^static void init_sample_table(void)$/;"	f	file:	signature:(void)
+init_tx_cfg	smac/dev.h	/^    void (*init_tx_cfg)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+init_wifi_sync	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	/^SDK_API int init_wifi_sync(FUNC_NOTIFY fNotify, char *szSN, void *puserdata);$/;"	p	signature:(FUNC_NOTIFY fNotify, char *szSN, void *puserdata)
+instid	smartlink/qqlink-lib-mipsel/include/TXOldInf.h	/^    unsigned int instid;$/;"	m	struct:tag_tx_ccmsg_inst_info	access:public
+int_lock	hci/hctrl.h	/^    spinlock_t int_lock;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+int_mask	hci/hctrl.h	/^    u32 int_mask;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+int_status	hci/hctrl.h	/^    u32 int_status;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+interface	hwif/usb/usb.c	/^ struct usb_interface *interface;$/;"	m	struct:ssv6xxx_usb_glue	typeref:struct:ssv6xxx_usb_glue::usb_interface	file:	access:public
+interface_reset	hwif/hwif.h	/^    void (*interface_reset)(struct device *child);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+invalid_irq_count	hci/hctrl.h	/^    u32 invalid_irq_count;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+io_mutex	hwif/usb/usb.c	/^ struct mutex io_mutex;$/;"	m	struct:ssv6xxx_usb_glue	typeref:struct:ssv6xxx_usb_glue::mutex	file:	access:public
+ipd_channel_touch	smac/dev.h	/^    u8 ipd_channel_touch;$/;"	m	struct:ssv_hw	access:public
+iq_cali_done	smac/dev.h	/^    u32 iq_cali_done;$/;"	m	struct:ssv_softc	access:public
+iqk_cfg	smac/dev.h	/^    struct ssv6xxx_iqk_cfg iqk_cfg;$/;"	m	struct:ssv_hw	typeref:struct:ssv_hw::ssv6xxx_iqk_cfg	access:public
+irq_count	hci/hctrl.h	/^    u32 irq_count;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+irq_dev	hwif/sdio/sdio.c	/^    void *irq_dev;$/;"	m	struct:ssv6xxx_sdio_glue	file:	access:public
+irq_disable	hwif/hwif.h	/^    void (*irq_disable)(struct device *child,bool iswaitirq);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+irq_enable	hci/hctrl.h	/^    bool irq_enable;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+irq_enable	hwif/hwif.h	/^    void (*irq_enable)(struct device *child);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+irq_getmask	hwif/hwif.h	/^    int (*irq_getmask)(struct device *child, u32 *mask);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+irq_getstatus	hwif/hwif.h	/^    int (*irq_getstatus)(struct device *child,int *status);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+irq_handler	hwif/sdio/sdio.c	/^    irq_handler_t irq_handler;$/;"	m	struct:ssv6xxx_sdio_glue	file:	access:public
+irq_handling	bridge/sdiobridge.h	/^    atomic_t irq_handling;$/;"	m	struct:ssv_sdiobridge_glue	access:public
+irq_handling	hwif/hwif.h	/^    atomic_t irq_handling;$/;"	m	struct:ssv6xxx_platform_data	access:public
+irq_request	hwif/hwif.h	/^    void (*irq_request)(struct device *child,irq_handler_t irq_handler,void *irq_dev);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+irq_rx_pkt_count	hci/hctrl.h	/^    u32 irq_rx_pkt_count;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+irq_setmask	hwif/hwif.h	/^    void (*irq_setmask)(struct device *child,int mask);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+irq_trigger	hwif/hwif.h	/^    void (*irq_trigger)(struct device *child);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+irq_tx_pkt_count	hci/hctrl.h	/^    u32 irq_tx_pkt_count;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+irq_wq	bridge/sdiobridge.h	/^    wait_queue_head_t irq_wq;$/;"	m	struct:ssv_sdiobridge_glue	access:public
+isAssoc	smac/dev.h	/^    bool isAssoc;$/;"	m	struct:ssv_softc	access:public
+is_enabled	hwif/hwif.h	/^    bool is_enabled;$/;"	m	struct:ssv6xxx_platform_data	access:public
+is_group	smac/sec_wpi.c	/^BOOL_T is_group(u8* addr)$/;"	f	signature:(u8* addr)
+is_ht	smac/ssv_rc_common.h	/^    u8 is_ht;$/;"	m	struct:ssv_sta_rc_info	access:public
+is_ht	smac/ssv_rc_minstrel.h	/^ bool is_ht;$/;"	m	struct:ssv_minstrel_sta_priv	access:public
+is_last_rate0	smac/hal/ssv6006c/turismo_common.h	/^    u32 is_last_rate0:1;$/;"	m	struct:ssv6006_tx_desc	access:public
+is_last_rate1	smac/hal/ssv6006c/turismo_common.h	/^    u32 is_last_rate1:1;$/;"	m	struct:ssv6006_tx_desc	access:public
+is_last_rate2	smac/hal/ssv6006c/turismo_common.h	/^    u32 is_last_rate2:1;$/;"	m	struct:ssv6006_tx_desc	access:public
+is_last_rate3	smac/hal/ssv6006c/turismo_common.h	/^    u32 is_last_rate3:1;$/;"	m	struct:ssv6006_tx_desc	access:public
+is_legacy_rate	smac/dev.h	/^    bool (*is_legacy_rate)(struct ssv_softc *sc, struct sk_buff *skb);$/;"	m	struct:ssv_hal_ops	access:public
+is_rate_stat_sample_pkt	smac/hal/ssv6006c/turismo_common.h	/^    u32 is_rate_stat_sample_pkt:1;$/;"	m	struct:ssv6006_tx_desc	access:public
+is_ready	hwif/hwif.h	/^    bool (*is_ready)(struct device *child);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+is_rx_aggr	smac/dev.h	/^    bool (*is_rx_aggr)(struct sk_buff *skb);$/;"	m	struct:ssv_hal_ops	access:public
+is_rx_q_full	hwif/usb/usb.c	/^    int (*is_rx_q_full)(void *);$/;"	m	struct:ssv6xxx_usb_glue	file:	access:public
+is_sample	smac/ssv_rc_minstrel_ht.h	/^ bool is_sample;$/;"	m	struct:ssv_minstrel_ampdu_rate_rpt	access:public
+is_security_valid	smac/dev.h	/^    bool is_security_valid;$/;"	m	struct:ssv_vif_priv_data	access:public
+is_smartlink_running	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	/^SDK_API int is_smartlink_running();$/;"	p	signature:()
+ischar	ssvdevice/ssvdevice.c	/^int ischar(char *c)$/;"	f	signature:(char *c)
+isr_disable	hci/hctrl.h	/^ u32 isr_disable;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+isr_idle_time	hci/hctrl.h	/^    u32 isr_idle_time;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+isr_mib_enable	hci/hctrl.h	/^ u32 isr_mib_enable;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+isr_mib_reset	hci/hctrl.h	/^ u32 isr_mib_reset;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+isr_miss_cnt	hci/hctrl.h	/^    u32 isr_miss_cnt;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+isr_reset_work	hci/hctrl.h	/^ struct work_struct isr_reset_work;$/;"	m	struct:ssv6xxx_hci_ctrl	typeref:struct:ssv6xxx_hci_ctrl::work_struct	access:public
+isr_routine_time	hci/hctrl.h	/^    u32 isr_routine_time;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+isr_running	hci/hctrl.h	/^    u32 isr_running;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+isr_rx_idle_time	hci/hctrl.h	/^    u32 isr_rx_idle_time;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+isr_rx_io_count	hci/hctrl.h	/^ u32 isr_rx_io_count;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+isr_rx_io_time	hci/hctrl.h	/^ long long isr_rx_io_time;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+isr_rx_proc_time	hci/hctrl.h	/^ long long isr_rx_proc_time;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+isr_rx_time	hci/hctrl.h	/^    u32 isr_rx_time;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+isr_summary_eable	hci/hctrl.h	/^    u32 isr_summary_eable;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+isr_total_time	hci/hctrl.h	/^ long long isr_total_time;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+isr_tx_io_count	hci/hctrl.h	/^ u32 isr_tx_io_count;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+isr_tx_io_time	hci/hctrl.h	/^ long long isr_tx_io_time;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+isr_tx_time	hci/hctrl.h	/^    u32 isr_tx_time;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+iv	smac/sec_wep.c	/^    u32 iv;$/;"	m	struct:lib80211_wep_data	file:	access:public
+jmp_mpdu_len	include/ssv6xxx_common.h	/^    u32 jmp_mpdu_len:16;$/;"	m	struct:hci_rx_aggr_info	access:public
+jump_to_rom	hwif/hwif.h	/^    int (*jump_to_rom)(struct device *child);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+jump_to_rom	hwif/hwif.h	/^    void (*jump_to_rom)(void *param);$/;"	m	struct:ssv6xxx_platform_data	access:public
+jump_to_rom	smac/dev.h	/^    int (*jump_to_rom)(struct ssv_softc *sc);$/;"	m	struct:ssv_hal_ops	access:public
+key	smac/dev.h	/^    u8 key[SECURITY_KEY_LEN];$/;"	m	struct:wep_hw_key	access:public
+key	smac/drv_comm.h	/^    u8 key[SECURITY_KEY_LEN];$/;"	m	struct:ssv6xxx_hw_key	access:public
+key	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 key[SSV6006_SECURITY_KEY_LEN];$/;"	m	struct:ssv6006_hw_key	access:public
+key	smac/sec_ccmp.c	/^ u8 key[CCMP_TK_LEN];$/;"	m	struct:lib80211_ccmp_data	file:	access:public
+key	smac/sec_tkip.c	/^ u8 key[TKIP_KEY_LEN];$/;"	m	struct:lib80211_tkip_data	file:	access:public
+key	smac/sec_wep.c	/^    u8 key[WEP_KEY_LEN + 1];$/;"	m	struct:lib80211_wep_data	file:	access:public
+key_2char2num	smac/efuse.c	/^u8 key_2char2num(u8 hch, u8 lch)$/;"	f	signature:(u8 hch, u8 lch)
+key_char2num	smac/efuse.c	/^static u8 key_char2num(u8 ch)$/;"	f	file:	signature:(u8 ch)
+key_idx	smac/sec_ccmp.c	/^ int key_idx;$/;"	m	struct:lib80211_ccmp_data	file:	access:public
+key_idx	smac/sec_tkip.c	/^ int key_idx;$/;"	m	struct:lib80211_tkip_data	file:	access:public
+key_idx	smac/sec_wep.c	/^    u8 key_idx;$/;"	m	struct:lib80211_wep_data	file:	access:public
+key_index	smac/sec_wpi.c	/^ u8 key_index;$/;"	m	struct:lib80211_wpi_data	file:	access:public
+key_len	smac/sec_wep.c	/^    u8 key_len;$/;"	m	struct:lib80211_wep_data	file:	access:public
+key_length	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^    int key_length;$/;"	m	struct:tag_tx_file_transfer_info	access:public
+key_set	smac/sec_ccmp.c	/^ int key_set;$/;"	m	struct:lib80211_ccmp_data	file:	access:public
+key_set	smac/sec_tkip.c	/^ int key_set;$/;"	m	struct:lib80211_tkip_data	file:	access:public
+keylen	smac/dev.h	/^    u8 keylen;$/;"	m	struct:wep_hw_key	access:public
+kill_daemon	script/p2p-action.sh	/^kill_daemon() {$/;"	f
+kref	hwif/usb/usb.c	/^ struct kref kref;$/;"	m	struct:ssv6xxx_usb_glue	typeref:struct:ssv6xxx_usb_glue::kref	file:	access:public
+ksmartlink_cmd_smartlink	smac/ksmartlink.c	/^int ksmartlink_cmd_smartlink(struct sk_buff *skb, struct genl_info *info)$/;"	f	signature:(struct sk_buff *skb, struct genl_info *info)
+ksmartlink_exit	smac/ksmartlink.c	/^EXPORT_SYMBOL(ksmartlink_exit);$/;"	v
+ksmartlink_exit	smac/ksmartlink.c	/^int ksmartlink_exit(void)$/;"	f	signature:(void)
+ksmartlink_genl_policy	smac/ksmartlink.c	/^static struct nla_policy ksmartlink_genl_policy[KSMARTLINK_ATTR_MAX + 1] = {$/;"	v	typeref:struct:nla_policy	file:
+ksmartlink_get_channel	smac/ksmartlink.c	/^static int ksmartlink_get_channel(struct sk_buff *skb, struct genl_info *info)$/;"	f	file:	signature:(struct sk_buff *skb, struct genl_info *info)
+ksmartlink_get_promisc	smac/ksmartlink.c	/^static int ksmartlink_get_promisc(struct sk_buff *skb, struct genl_info *info)$/;"	f	file:	signature:(struct sk_buff *skb, struct genl_info *info)
+ksmartlink_get_si_pass	smac/ksmartlink.c	/^static int ksmartlink_get_si_pass(struct sk_buff *skb, struct genl_info *info)$/;"	f	file:	signature:(struct sk_buff *skb, struct genl_info *info)
+ksmartlink_get_si_ssid	smac/ksmartlink.c	/^static int ksmartlink_get_si_ssid(struct sk_buff *skb, struct genl_info *info)$/;"	f	file:	signature:(struct sk_buff *skb, struct genl_info *info)
+ksmartlink_get_si_status	smac/ksmartlink.c	/^static int ksmartlink_get_si_status(struct sk_buff *skb, struct genl_info *info)$/;"	f	file:	signature:(struct sk_buff *skb, struct genl_info *info)
+ksmartlink_gnl_family	smac/ksmartlink.c	/^static struct genl_family ksmartlink_gnl_family = {$/;"	v	typeref:struct:genl_family	file:
+ksmartlink_gnl_ops	smac/ksmartlink.c	/^struct genl_ops ksmartlink_gnl_ops[] = {$/;"	v	typeref:struct:genl_ops
+ksmartlink_init	smac/ksmartlink.c	/^EXPORT_SYMBOL(ksmartlink_init);$/;"	v
+ksmartlink_init	smac/ksmartlink.c	/^int ksmartlink_init(void)$/;"	f	signature:(void)
+ksmartlink_set_channel	smac/ksmartlink.c	/^static int ksmartlink_set_channel(struct sk_buff *skb, struct genl_info *info)$/;"	f	file:	signature:(struct sk_buff *skb, struct genl_info *info)
+ksmartlink_set_promisc	smac/ksmartlink.c	/^static int ksmartlink_set_promisc(struct sk_buff *skb, struct genl_info *info)$/;"	f	file:	signature:(struct sk_buff *skb, struct genl_info *info)
+ksmartlink_set_si_cmd	smac/ksmartlink.c	/^static int ksmartlink_set_si_cmd(struct sk_buff *skb, struct genl_info *info)$/;"	f	file:	signature:(struct sk_buff *skb, struct genl_info *info)
+ksmartlink_start_smarticomm	smac/ksmartlink.c	/^static int ksmartlink_start_smarticomm(struct sk_buff *skb, struct genl_info *info)$/;"	f	file:	signature:(struct sk_buff *skb, struct genl_info *info)
+l3cs_err	include/ssv6200_common.h	/^    u32 l3cs_err:1;$/;"	m	struct:ssv6200_rx_desc	access:public
+l4cs_err	include/ssv6200_common.h	/^    u32 l4cs_err:1;$/;"	m	struct:ssv6200_rx_desc	access:public
+l_length	include/ssv6200_common.h	/^    u32 l_length:12;$/;"	m	struct:ssv6200_rxphy_info	access:public
+l_length	smac/hal/ssv6006c/turismo_common.h	/^    u32 l_length:12;$/;"	m	struct:ssv6006_rxphy_info	access:public
+l_rate	include/ssv6200_common.h	/^    u32 l_rate:3;$/;"	m	struct:ssv6200_rxphy_info	access:public
+l_rate	smac/hal/ssv6006c/turismo_common.h	/^    u32 l_rate:3;$/;"	m	struct:ssv6006_rxphy_info	access:public
+last	smac/ssv_rc_minstrel_ht.h	/^ int last;$/;"	m	struct:ssv_minstrel_ht_rpt	access:public
+last_attempts	smac/ssv_rc_common.h	/^    unsigned int attempts, last_attempts;$/;"	m	struct:minstrel_rate_stats	access:public
+last_attempts	smac/ssv_rc_minstrel.h	/^ u32 last_attempts;$/;"	m	struct:ssv_minstrel_rate	access:public
+last_attempts	smac/ssv_rc_minstrel_ht.h	/^ unsigned int attempts, last_attempts;$/;"	m	struct:ssv_minstrel_ht_rate_stats	access:public
+last_dlr	smac/ssv_rc_common.h	/^    int last_dlr;$/;"	m	struct:rc_pid_sta_info	access:public
+last_jiffies	smac/ssv_rc_minstrel.h	/^ unsigned long last_jiffies;$/;"	m	struct:ssv_minstrel_rate	access:public
+last_jiffies	smac/ssv_rc_minstrel_ht.h	/^ unsigned long last_jiffies;$/;"	m	struct:ssv_minstrel_ht_rate_stats	access:public
+last_pf	smac/ssv_rc_common.h	/^    u8 last_pf;$/;"	m	struct:rc_pid_sta_info	access:public
+last_report	smac/ssv_rc_common.h	/^    unsigned long last_report;$/;"	m	struct:rc_pid_sta_info	access:public
+last_rx	smac/p2p.h	/^    unsigned long last_rx;$/;"	m	struct:ssv_p2p_noa_detect	access:public
+last_sample	smac/ssv_rc_common.h	/^    unsigned long last_sample;$/;"	m	struct:rc_pid_sta_info	access:public
+last_seqno	smac/ampdu.h	/^    u32 last_seqno;$/;"	m	struct:AMPDU_TID_st	access:public
+last_success	smac/ssv_rc_common.h	/^    unsigned int success, last_success;$/;"	m	struct:minstrel_rate_stats	access:public
+last_success	smac/ssv_rc_minstrel.h	/^ u32 last_success;$/;"	m	struct:ssv_minstrel_rate	access:public
+last_success	smac/ssv_rc_minstrel_ht.h	/^ unsigned int success, last_success;$/;"	m	struct:ssv_minstrel_ht_rate_stats	access:public
+legacy	smac/ssv_rc_minstrel.h	/^  struct ssv_minstrel_sta_info legacy;$/;"	m	union:ssv_minstrel_sta_priv::__anon16	typeref:struct:ssv_minstrel_sta_priv::__anon16::ssv_minstrel_sta_info	access:public
+len	hwif/sdio/sdio_def.h	/^ int len;$/;"	m	struct:sdio_scatter_item	access:public
+len	hwif/sdio/sdio_def.h	/^ u32 len;$/;"	m	struct:sdio_scatter_req	access:public
+len	include/ssv6200_common.h	/^    u32 len:16;$/;"	m	struct:ssv6200_rx_desc	access:public
+len	include/ssv6200_common.h	/^    u32 len:16;$/;"	m	struct:ssv6200_rxphy_info	access:public
+len	include/ssv6200_common.h	/^    u32 len:16;$/;"	m	struct:ssv6200_tx_desc	access:public
+len	include/ssv6xxx_common.h	/^    u32 len :16;$/;"	m	struct:cfg_host_event	access:public
+len	include/ssv6xxx_common.h	/^    u32 len:16;$/;"	m	struct:cfg_host_cmd	access:public
+len	smac/dev.h	/^ u16 len;$/;"	m	struct:ssv6xxx_beacon_info	access:public
+len	smac/hal/ssv6006c/turismo_common.h	/^    u32 len:16;$/;"	m	struct:ssv6006_rx_desc	access:public
+len	smac/hal/ssv6006c/turismo_common.h	/^    u32 len:16;$/;"	m	struct:ssv6006_rxphy_info	access:public
+len	smac/hal/ssv6006c/turismo_common.h	/^    u32 len:16;$/;"	m	struct:ssv6006_tx_desc	access:public
+len	smac/ssv_rc_minstrel.h	/^ size_t len;$/;"	m	struct:ssv_minstrel_debugfs_info	access:public
+length	smac/ampdu.h	/^    u16 length:12;$/;"	m	struct:AMPDU_DELIMITER_st	access:public
+lib80211_ccmp_aes_encrypt	smac/sec_ccmp.c	/^static inline void lib80211_ccmp_aes_encrypt(struct crypto_cipher *tfm,$/;"	f	file:	signature:(struct crypto_cipher *tfm, const u8 pt[16], u8 ct[16])
+lib80211_ccmp_data	smac/sec_ccmp.c	/^struct lib80211_ccmp_data {$/;"	s	file:
+lib80211_ccmp_data::dot11RSNAStatsCCMPDecryptErrors	smac/sec_ccmp.c	/^ u32 dot11RSNAStatsCCMPDecryptErrors;$/;"	m	struct:lib80211_ccmp_data	file:	access:public
+lib80211_ccmp_data::dot11RSNAStatsCCMPFormatErrors	smac/sec_ccmp.c	/^ u32 dot11RSNAStatsCCMPFormatErrors;$/;"	m	struct:lib80211_ccmp_data	file:	access:public
+lib80211_ccmp_data::dot11RSNAStatsCCMPReplays	smac/sec_ccmp.c	/^ u32 dot11RSNAStatsCCMPReplays;$/;"	m	struct:lib80211_ccmp_data	file:	access:public
+lib80211_ccmp_data::key	smac/sec_ccmp.c	/^ u8 key[CCMP_TK_LEN];$/;"	m	struct:lib80211_ccmp_data	file:	access:public
+lib80211_ccmp_data::key_idx	smac/sec_ccmp.c	/^ int key_idx;$/;"	m	struct:lib80211_ccmp_data	file:	access:public
+lib80211_ccmp_data::key_set	smac/sec_ccmp.c	/^ int key_set;$/;"	m	struct:lib80211_ccmp_data	file:	access:public
+lib80211_ccmp_data::pre_rx_pn	smac/sec_ccmp.c	/^    u8 pre_rx_pn[CCMP_PN_LEN];$/;"	m	struct:lib80211_ccmp_data	file:	access:public
+lib80211_ccmp_data::rx_a	smac/sec_ccmp.c	/^    u8 *rx_b0, *rx_b, *rx_a;$/;"	m	struct:lib80211_ccmp_data	file:	access:public
+lib80211_ccmp_data::rx_a	smac/sec_ccmp.c	/^    u8 rx_b0[AES_BLOCK_LEN], rx_b[AES_BLOCK_LEN], rx_a[AES_BLOCK_LEN];$/;"	m	struct:lib80211_ccmp_data	file:	access:public
+lib80211_ccmp_data::rx_b	smac/sec_ccmp.c	/^    u8 *rx_b0, *rx_b, *rx_a;$/;"	m	struct:lib80211_ccmp_data	file:	access:public
+lib80211_ccmp_data::rx_b	smac/sec_ccmp.c	/^    u8 rx_b0[AES_BLOCK_LEN], rx_b[AES_BLOCK_LEN], rx_a[AES_BLOCK_LEN];$/;"	m	struct:lib80211_ccmp_data	file:	access:public
+lib80211_ccmp_data::rx_b0	smac/sec_ccmp.c	/^    u8 *rx_b0, *rx_b, *rx_a;$/;"	m	struct:lib80211_ccmp_data	file:	access:public
+lib80211_ccmp_data::rx_b0	smac/sec_ccmp.c	/^    u8 rx_b0[AES_BLOCK_LEN], rx_b[AES_BLOCK_LEN], rx_a[AES_BLOCK_LEN];$/;"	m	struct:lib80211_ccmp_data	file:	access:public
+lib80211_ccmp_data::rx_pn	smac/sec_ccmp.c	/^ u8 rx_pn[CCMP_PN_LEN];$/;"	m	struct:lib80211_ccmp_data	file:	access:public
+lib80211_ccmp_data::tfm	smac/sec_ccmp.c	/^ struct crypto_cipher *tfm;$/;"	m	struct:lib80211_ccmp_data	typeref:struct:lib80211_ccmp_data::crypto_cipher	file:	access:public
+lib80211_ccmp_data::tx_b	smac/sec_ccmp.c	/^ u8 *tx_b0, *tx_b, *tx_e, *tx_s0;$/;"	m	struct:lib80211_ccmp_data	file:	access:public
+lib80211_ccmp_data::tx_b	smac/sec_ccmp.c	/^ u8 tx_b0[AES_BLOCK_LEN], tx_b[AES_BLOCK_LEN],$/;"	m	struct:lib80211_ccmp_data	file:	access:public
+lib80211_ccmp_data::tx_b0	smac/sec_ccmp.c	/^ u8 *tx_b0, *tx_b, *tx_e, *tx_s0;$/;"	m	struct:lib80211_ccmp_data	file:	access:public
+lib80211_ccmp_data::tx_b0	smac/sec_ccmp.c	/^ u8 tx_b0[AES_BLOCK_LEN], tx_b[AES_BLOCK_LEN],$/;"	m	struct:lib80211_ccmp_data	file:	access:public
+lib80211_ccmp_data::tx_e	smac/sec_ccmp.c	/^     tx_e[AES_BLOCK_LEN], tx_s0[AES_BLOCK_LEN];$/;"	m	struct:lib80211_ccmp_data	file:	access:public
+lib80211_ccmp_data::tx_e	smac/sec_ccmp.c	/^ u8 *tx_b0, *tx_b, *tx_e, *tx_s0;$/;"	m	struct:lib80211_ccmp_data	file:	access:public
+lib80211_ccmp_data::tx_pn	smac/sec_ccmp.c	/^ u8 tx_pn[CCMP_PN_LEN];$/;"	m	struct:lib80211_ccmp_data	file:	access:public
+lib80211_ccmp_data::tx_s0	smac/sec_ccmp.c	/^     tx_e[AES_BLOCK_LEN], tx_s0[AES_BLOCK_LEN];$/;"	m	struct:lib80211_ccmp_data	file:	access:public
+lib80211_ccmp_data::tx_s0	smac/sec_ccmp.c	/^ u8 *tx_b0, *tx_b, *tx_e, *tx_s0;$/;"	m	struct:lib80211_ccmp_data	file:	access:public
+lib80211_ccmp_decrypt	smac/sec_ccmp.c	/^static int lib80211_ccmp_decrypt(struct sk_buff *skb, int hdr_len, void *priv)$/;"	f	file:	signature:(struct sk_buff *skb, int hdr_len, void *priv)
+lib80211_ccmp_decrypt_prepare	smac/sec_ccmp.c	/^static int lib80211_ccmp_decrypt_prepare (struct sk_buff * skb, int hdr_len, void *priv)$/;"	f	file:	signature:(struct sk_buff * skb, int hdr_len, void *priv)
+lib80211_ccmp_deinit	smac/sec_ccmp.c	/^static void lib80211_ccmp_deinit(void *priv)$/;"	f	file:	signature:(void *priv)
+lib80211_ccmp_encrypt	smac/sec_ccmp.c	/^static int lib80211_ccmp_encrypt(struct sk_buff *skb, int hdr_len, void *priv)$/;"	f	file:	signature:(struct sk_buff *skb, int hdr_len, void *priv)
+lib80211_ccmp_encrypt_prepare	smac/sec_ccmp.c	/^static int lib80211_ccmp_encrypt_prepare (struct sk_buff * skb, int hdr_len, void *priv)$/;"	f	file:	signature:(struct sk_buff * skb, int hdr_len, void *priv)
+lib80211_ccmp_get_key	smac/sec_ccmp.c	/^static int lib80211_ccmp_get_key(void *key, int len, u8 * seq, void *priv)$/;"	f	file:	signature:(void *key, int len, u8 * seq, void *priv)
+lib80211_ccmp_hdr	smac/sec_ccmp.c	/^static int lib80211_ccmp_hdr(struct sk_buff *skb, int hdr_len,$/;"	f	file:	signature:(struct sk_buff *skb, int hdr_len, u8 *aeskey, int keylen, void *priv)
+lib80211_ccmp_init	smac/sec_ccmp.c	/^static void *lib80211_ccmp_init(int key_idx)$/;"	f	file:	signature:(int key_idx)
+lib80211_ccmp_print_stats	smac/sec_ccmp.c	/^static char *lib80211_ccmp_print_stats(char *p, void *priv)$/;"	f	file:	signature:(char *p, void *priv)
+lib80211_ccmp_set_key	smac/sec_ccmp.c	/^static int lib80211_ccmp_set_key(void *key, int len, u8 * seq, void *priv)$/;"	f	file:	signature:(void *key, int len, u8 * seq, void *priv)
+lib80211_ccmp_set_tx_pn	smac/sec_ccmp.c	/^static int lib80211_ccmp_set_tx_pn(u8 * seq, void *priv)$/;"	f	file:	signature:(u8 * seq, void *priv)
+lib80211_michael_mic_add	smac/sec_tkip.c	/^static int lib80211_michael_mic_add(struct sk_buff *skb, int hdr_len,$/;"	f	file:	signature:(struct sk_buff *skb, int hdr_len, void *priv)
+lib80211_michael_mic_failure	smac/sec_tkip.c	/^static void lib80211_michael_mic_failure(struct net_device *dev,$/;"	f	file:	signature:(struct net_device *dev, struct ieee80211_hdr *hdr, int keyidx)
+lib80211_michael_mic_verify	smac/sec_tkip.c	/^static int lib80211_michael_mic_verify(struct sk_buff *skb, int keyidx,$/;"	f	file:	signature:(struct sk_buff *skb, int keyidx, int hdr_len, void *priv)
+lib80211_tkip_data	smac/sec_tkip.c	/^struct lib80211_tkip_data {$/;"	s	file:
+lib80211_tkip_data::dot11RSNAStatsTKIPICVErrors	smac/sec_tkip.c	/^ u32 dot11RSNAStatsTKIPICVErrors;$/;"	m	struct:lib80211_tkip_data	file:	access:public
+lib80211_tkip_data::dot11RSNAStatsTKIPLocalMICFailures	smac/sec_tkip.c	/^ u32 dot11RSNAStatsTKIPLocalMICFailures;$/;"	m	struct:lib80211_tkip_data	file:	access:public
+lib80211_tkip_data::dot11RSNAStatsTKIPReplays	smac/sec_tkip.c	/^ u32 dot11RSNAStatsTKIPReplays;$/;"	m	struct:lib80211_tkip_data	file:	access:public
+lib80211_tkip_data::flags	smac/sec_tkip.c	/^ unsigned long flags;$/;"	m	struct:lib80211_tkip_data	file:	access:public
+lib80211_tkip_data::key	smac/sec_tkip.c	/^ u8 key[TKIP_KEY_LEN];$/;"	m	struct:lib80211_tkip_data	file:	access:public
+lib80211_tkip_data::key_idx	smac/sec_tkip.c	/^ int key_idx;$/;"	m	struct:lib80211_tkip_data	file:	access:public
+lib80211_tkip_data::key_set	smac/sec_tkip.c	/^ int key_set;$/;"	m	struct:lib80211_tkip_data	file:	access:public
+lib80211_tkip_data::rx_hdr	smac/sec_tkip.c	/^ u8 rx_hdr[16], tx_hdr[16];$/;"	m	struct:lib80211_tkip_data	file:	access:public
+lib80211_tkip_data::rx_iv16	smac/sec_tkip.c	/^ u16 rx_iv16;$/;"	m	struct:lib80211_tkip_data	file:	access:public
+lib80211_tkip_data::rx_iv16_new	smac/sec_tkip.c	/^ u16 rx_iv16_new;$/;"	m	struct:lib80211_tkip_data	file:	access:public
+lib80211_tkip_data::rx_iv32	smac/sec_tkip.c	/^ u32 rx_iv32;$/;"	m	struct:lib80211_tkip_data	file:	access:public
+lib80211_tkip_data::rx_iv32_new	smac/sec_tkip.c	/^ u32 rx_iv32_new;$/;"	m	struct:lib80211_tkip_data	file:	access:public
+lib80211_tkip_data::rx_phase1_done	smac/sec_tkip.c	/^ int rx_phase1_done;$/;"	m	struct:lib80211_tkip_data	file:	access:public
+lib80211_tkip_data::rx_tfm_arc4	smac/sec_tkip.c	/^ struct crypto_blkcipher *rx_tfm_arc4;$/;"	m	struct:lib80211_tkip_data	typeref:struct:lib80211_tkip_data::crypto_blkcipher	file:	access:public
+lib80211_tkip_data::rx_tfm_arc4	smac/sec_tkip.c	/^ struct crypto_skcipher *rx_tfm_arc4;$/;"	m	struct:lib80211_tkip_data	typeref:struct:lib80211_tkip_data::crypto_skcipher	file:	access:public
+lib80211_tkip_data::rx_tfm_michael	smac/sec_tkip.c	/^ struct crypto_ahash *rx_tfm_michael;$/;"	m	struct:lib80211_tkip_data	typeref:struct:lib80211_tkip_data::crypto_ahash	file:	access:public
+lib80211_tkip_data::rx_tfm_michael	smac/sec_tkip.c	/^ struct crypto_hash *rx_tfm_michael;$/;"	m	struct:lib80211_tkip_data	typeref:struct:lib80211_tkip_data::crypto_hash	file:	access:public
+lib80211_tkip_data::rx_ttak	smac/sec_tkip.c	/^ u16 rx_ttak[5];$/;"	m	struct:lib80211_tkip_data	file:	access:public
+lib80211_tkip_data::tx_hdr	smac/sec_tkip.c	/^ u8 rx_hdr[16], tx_hdr[16];$/;"	m	struct:lib80211_tkip_data	file:	access:public
+lib80211_tkip_data::tx_iv16	smac/sec_tkip.c	/^ u16 tx_iv16;$/;"	m	struct:lib80211_tkip_data	file:	access:public
+lib80211_tkip_data::tx_iv32	smac/sec_tkip.c	/^ u32 tx_iv32;$/;"	m	struct:lib80211_tkip_data	file:	access:public
+lib80211_tkip_data::tx_phase1_done	smac/sec_tkip.c	/^ int tx_phase1_done;$/;"	m	struct:lib80211_tkip_data	file:	access:public
+lib80211_tkip_data::tx_tfm_arc4	smac/sec_tkip.c	/^ struct crypto_blkcipher *tx_tfm_arc4;$/;"	m	struct:lib80211_tkip_data	typeref:struct:lib80211_tkip_data::crypto_blkcipher	file:	access:public
+lib80211_tkip_data::tx_tfm_arc4	smac/sec_tkip.c	/^ struct crypto_skcipher *tx_tfm_arc4;$/;"	m	struct:lib80211_tkip_data	typeref:struct:lib80211_tkip_data::crypto_skcipher	file:	access:public
+lib80211_tkip_data::tx_tfm_michael	smac/sec_tkip.c	/^ struct crypto_ahash *tx_tfm_michael;$/;"	m	struct:lib80211_tkip_data	typeref:struct:lib80211_tkip_data::crypto_ahash	file:	access:public
+lib80211_tkip_data::tx_tfm_michael	smac/sec_tkip.c	/^ struct crypto_hash *tx_tfm_michael;$/;"	m	struct:lib80211_tkip_data	typeref:struct:lib80211_tkip_data::crypto_hash	file:	access:public
+lib80211_tkip_data::tx_ttak	smac/sec_tkip.c	/^ u16 tx_ttak[5];$/;"	m	struct:lib80211_tkip_data	file:	access:public
+lib80211_tkip_decrypt	smac/sec_tkip.c	/^static int lib80211_tkip_decrypt(struct sk_buff *skb, int hdr_len, void *priv)$/;"	f	file:	signature:(struct sk_buff *skb, int hdr_len, void *priv)
+lib80211_tkip_deinit	smac/sec_tkip.c	/^static void lib80211_tkip_deinit(void *priv)$/;"	f	file:	signature:(void *priv)
+lib80211_tkip_encrypt	smac/sec_tkip.c	/^static int lib80211_tkip_encrypt(struct sk_buff *skb, int hdr_len, void *priv)$/;"	f	file:	signature:(struct sk_buff *skb, int hdr_len, void *priv)
+lib80211_tkip_get_flags	smac/sec_tkip.c	/^static unsigned long lib80211_tkip_get_flags(void *priv)$/;"	f	file:	signature:(void *priv)
+lib80211_tkip_get_key	smac/sec_tkip.c	/^static int lib80211_tkip_get_key(void *key, int len, u8 * seq, void *priv)$/;"	f	file:	signature:(void *key, int len, u8 * seq, void *priv)
+lib80211_tkip_hdr	smac/sec_tkip.c	/^static int lib80211_tkip_hdr(struct sk_buff *skb, int hdr_len,$/;"	f	file:	signature:(struct sk_buff *skb, int hdr_len, u8 * rc4key, int keylen, void *priv)
+lib80211_tkip_init	smac/sec_tkip.c	/^static void *lib80211_tkip_init(int key_idx)$/;"	f	file:	signature:(int key_idx)
+lib80211_tkip_print_stats	smac/sec_tkip.c	/^static char *lib80211_tkip_print_stats(char *p, void *priv)$/;"	f	file:	signature:(char *p, void *priv)
+lib80211_tkip_set_flags	smac/sec_tkip.c	/^static unsigned long lib80211_tkip_set_flags(unsigned long flags, void *priv)$/;"	f	file:	signature:(unsigned long flags, void *priv)
+lib80211_tkip_set_key	smac/sec_tkip.c	/^static int lib80211_tkip_set_key(void *key, int len, u8 * seq, void *priv)$/;"	f	file:	signature:(void *key, int len, u8 * seq, void *priv)
+lib80211_wep_build_iv	smac/sec_wep.c	/^static int lib80211_wep_build_iv (struct sk_buff *skb, int hdr_len,$/;"	f	file:	signature:(struct sk_buff *skb, int hdr_len, u8 *key, int keylen, void *priv)
+lib80211_wep_data	smac/sec_wep.c	/^struct lib80211_wep_data$/;"	s	file:
+lib80211_wep_data::iv	smac/sec_wep.c	/^    u32 iv;$/;"	m	struct:lib80211_wep_data	file:	access:public
+lib80211_wep_data::key	smac/sec_wep.c	/^    u8 key[WEP_KEY_LEN + 1];$/;"	m	struct:lib80211_wep_data	file:	access:public
+lib80211_wep_data::key_idx	smac/sec_wep.c	/^    u8 key_idx;$/;"	m	struct:lib80211_wep_data	file:	access:public
+lib80211_wep_data::key_len	smac/sec_wep.c	/^    u8 key_len;$/;"	m	struct:lib80211_wep_data	file:	access:public
+lib80211_wep_data::rx_tfm	smac/sec_wep.c	/^    struct crypto_blkcipher *rx_tfm;$/;"	m	struct:lib80211_wep_data	typeref:struct:lib80211_wep_data::crypto_blkcipher	file:	access:public
+lib80211_wep_data::tx_tfm	smac/sec_wep.c	/^    struct crypto_blkcipher *tx_tfm;$/;"	m	struct:lib80211_wep_data	typeref:struct:lib80211_wep_data::crypto_blkcipher	file:	access:public
+lib80211_wep_decrypt	smac/sec_wep.c	/^static int lib80211_wep_decrypt (struct sk_buff *skb, int hdr_len, void *priv)$/;"	f	file:	signature:(struct sk_buff *skb, int hdr_len, void *priv)
+lib80211_wep_deinit	smac/sec_wep.c	/^static void lib80211_wep_deinit (void *priv)$/;"	f	file:	signature:(void *priv)
+lib80211_wep_encrypt	smac/sec_wep.c	/^static int lib80211_wep_encrypt (struct sk_buff *skb, int hdr_len, void *priv)$/;"	f	file:	signature:(struct sk_buff *skb, int hdr_len, void *priv)
+lib80211_wep_get_key	smac/sec_wep.c	/^static int lib80211_wep_get_key (void *key, int len, u8 * seq, void *priv)$/;"	f	file:	signature:(void *key, int len, u8 * seq, void *priv)
+lib80211_wep_init	smac/sec_wep.c	/^static void *lib80211_wep_init (int keyidx)$/;"	f	file:	signature:(int keyidx)
+lib80211_wep_print_stats	smac/sec_wep.c	/^static char *lib80211_wep_print_stats (char *p, void *priv)$/;"	f	file:	signature:(char *p, void *priv)
+lib80211_wep_set_key	smac/sec_wep.c	/^static int lib80211_wep_set_key (void *key, int len, u8 * seq, void *priv)$/;"	f	file:	signature:(void *key, int len, u8 * seq, void *priv)
+lib80211_wpi_data	smac/sec_wpi.c	/^struct lib80211_wpi_data {$/;"	s	file:
+lib80211_wpi_data::ap_address	smac/sec_wpi.c	/^ u8 ap_address[ETH_ALEN];$/;"	m	struct:lib80211_wpi_data	file:	access:public
+lib80211_wpi_data::key_index	smac/sec_wpi.c	/^ u8 key_index;$/;"	m	struct:lib80211_wpi_data	file:	access:public
+lib80211_wpi_data::mic_key	smac/sec_wpi.c	/^ u8 mic_key[3][WAPI_PN_LEN];$/;"	m	struct:lib80211_wpi_data	file:	access:public
+lib80211_wpi_data::pmsk_key	smac/sec_wpi.c	/^ u8 pmsk_key[3][WAPI_PN_LEN];$/;"	m	struct:lib80211_wpi_data	file:	access:public
+lib80211_wpi_data::pn_key	smac/sec_wpi.c	/^ u8 pn_key[WAPI_PN_LEN];$/;"	m	struct:lib80211_wpi_data	file:	access:public
+lib80211_wpi_data::wapi_enable	smac/sec_wpi.c	/^ TRUTH_VALUE_T wapi_enable;$/;"	m	struct:lib80211_wpi_data	file:	access:public
+lib80211_wpi_data::wapi_key_ok	smac/sec_wpi.c	/^ TRUTH_VALUE_T wapi_key_ok;$/;"	m	struct:lib80211_wpi_data	file:	access:public
+lib80211_wpi_data::wapi_version	smac/sec_wpi.c	/^ u8 wapi_version[2];$/;"	m	struct:lib80211_wpi_data	file:	access:public
+lib80211_wpi_decrypt	smac/sec_wpi.c	/^int lib80211_wpi_decrypt(struct sk_buff *rx_skb, int hdr_len, void *priv)$/;"	f	signature:(struct sk_buff *rx_skb, int hdr_len, void *priv)
+lib80211_wpi_decrypt	smac/sec_wpi.h	/^int lib80211_wpi_decrypt(struct sk_buff *mpdu, int hdr_len, void *priv);$/;"	p	signature:(struct sk_buff *mpdu, int hdr_len, void *priv)
+lib80211_wpi_deinit	smac/sec_wpi.c	/^void lib80211_wpi_deinit(void *priv)$/;"	f	signature:(void *priv)
+lib80211_wpi_deinit	smac/sec_wpi.h	/^void lib80211_wpi_deinit(void *priv);$/;"	p	signature:(void *priv)
+lib80211_wpi_encrypt	smac/sec_wpi.c	/^int lib80211_wpi_encrypt(struct sk_buff *mpdu, int hdr_len, void *priv)$/;"	f	signature:(struct sk_buff *mpdu, int hdr_len, void *priv)
+lib80211_wpi_encrypt	smac/sec_wpi.h	/^int lib80211_wpi_encrypt(struct sk_buff *mpdu, int hdr_len, void *priv);$/;"	p	signature:(struct sk_buff *mpdu, int hdr_len, void *priv)
+lib80211_wpi_encrypt_prepare	smac/sec_wpi.c	/^int lib80211_wpi_encrypt_prepare(struct sk_buff *mpdu, int hdr_len, void *priv)$/;"	f	signature:(struct sk_buff *mpdu, int hdr_len, void *priv)
+lib80211_wpi_encrypt_prepare	smac/sec_wpi.h	/^int lib80211_wpi_encrypt_prepare(struct sk_buff *mpdu, int hdr_len, void *priv);$/;"	p	signature:(struct sk_buff *mpdu, int hdr_len, void *priv)
+lib80211_wpi_init	smac/sec_wpi.c	/^void *lib80211_wpi_init(int key_idx)$/;"	f	signature:(int key_idx)
+lib80211_wpi_init	smac/sec_wpi.h	/^void *lib80211_wpi_init(int key_idx);$/;"	p	signature:(int key_idx)
+lib80211_wpi_set_key	smac/sec_wpi.c	/^int lib80211_wpi_set_key(void *key, int len, u8 *seq, void *priv)$/;"	f	signature:(void *key, int len, u8 *seq, void *priv)
+lib80211_wpi_set_key	smac/sec_wpi.h	/^int lib80211_wpi_set_key(void *key, int len, u8 *seq, void *priv);$/;"	p	signature:(void *key, int len, u8 *seq, void *priv)
+list	bridge/sdiobridge.c	/^    struct list_head list;$/;"	m	struct:ssv_rxbuf	typeref:struct:ssv_rxbuf::list_head	file:	access:public
+list	hci_wrapper/ssv_huw.c	/^    struct list_head list;$/;"	m	struct:ssv_rxbuf	typeref:struct:ssv_rxbuf::list_head	file:	access:public
+list	include/ssv_data_struct.h	/^    struct list_head list;$/;"	m	struct:ssv6xxx_list_node	typeref:struct:ssv6xxx_list_node::list_head	access:public
+list	smac/ampdu.h	/^    struct list_head list;$/;"	m	struct:AMPDU_TID_st	typeref:struct:AMPDU_TID_st::list_head	access:public
+list	smac/dev.h	/^    struct list_head list;$/;"	m	struct:ssv_encrypt_task_list	typeref:struct:ssv_encrypt_task_list::list_head	access:public
+list	smac/dev.h	/^    struct list_head list;$/;"	m	struct:ssv_hw_cfg	typeref:struct:ssv_hw_cfg::list_head	access:public
+list	smac/dev.h	/^    struct list_head list;$/;"	m	struct:ssv_sta_priv_data	typeref:struct:ssv_sta_priv_data::list_head	access:public
+list	smac/sec.h	/^ struct list_head list;$/;"	m	struct:ssv_crypto_ops	typeref:struct:ssv_crypto_ops::list_head	access:public
+load_fw	hwif/hwif.h	/^    int __must_check (*load_fw)(struct device *child, u32 start_addr, u8 *data, int data_length);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+load_fw_disable_mcu	smac/dev.h	/^ int (*load_fw_disable_mcu)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+load_fw_enable_mcu	smac/dev.h	/^ void (*load_fw_enable_mcu)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+load_fw_get_status	smac/dev.h	/^ int (*load_fw_get_status)(struct ssv_hw *sh, u32 *status);$/;"	m	struct:ssv_hal_ops	access:public
+load_fw_post_config_device	hwif/hwif.h	/^    void (*load_fw_post_config_device)(struct device *child);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+load_fw_post_config_device	smac/dev.h	/^ void (*load_fw_post_config_device)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+load_fw_pre_config_device	hwif/hwif.h	/^    void (*load_fw_pre_config_device)(struct device *child);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+load_fw_pre_config_device	smac/dev.h	/^ void (*load_fw_pre_config_device)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+load_fw_set_status	smac/dev.h	/^ int (*load_fw_set_status)(struct ssv_hw *sh, u32 status);$/;"	m	struct:ssv_hal_ops	access:public
+load_phy_table	smac/dev.h	/^    void (*load_phy_table)(ssv_cabrio_reg **phy_table);$/;"	m	struct:ssv_hal_ops	access:public
+load_rf_table	smac/dev.h	/^    void (*load_rf_table)(ssv_cabrio_reg **rf_table);$/;"	m	struct:ssv_hal_ops	access:public
+lock	include/ssv_data_struct.h	/^    spinlock_t lock;$/;"	m	struct:ssv6xxx_queue	access:public
+lock	smac/sec.h	/^    rwlock_t lock;$/;"	m	struct:ssv_crypto_data	access:public
+log_ctrl	smac/dev.h	/^    u32 log_ctrl;$/;"	m	struct:ssv_softc	access:public
+log_func	smartlink/qqlink-lib-mipsel/case/ipcamera/main.c	/^void log_func(int level, const char* module, int line, const char* message)$/;"	f	signature:(int level, const char* module, int line, const char* message)
+log_func	smartlink/qqlink-lib-mipsel/demo_bind.c	/^void log_func(int level, const char* module, int line, const char* message)$/;"	f	signature:(int level, const char* module, int line, const char* message)
+log_func	smartlink/qqlink-lib-mipsel/demo_filetransfer.c	/^void log_func(int level, const char* module, int line, const char* message)$/;"	f	signature:(int level, const char* module, int line, const char* message)
+log_func	smartlink/qqlink-lib-mipsel/demo_video.c	/^void log_func(int level, const char* module, int line, const char* message)$/;"	f	signature:(int level, const char* module, int line, const char* message)
+log_to_ram	smac/dev.h	/^ bool log_to_ram;$/;"	m	struct:ssv_cmd_data	access:public
+long_short	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 long_short:1;$/;"	m	struct:ssv6006_rc_idx	access:public
+lookaround_rate	smac/ssv_rc_minstrel.h	/^ unsigned int lookaround_rate;$/;"	m	struct:ssv_minstrel_priv	access:public
+lookaround_rate_mrr	smac/ssv_rc_minstrel.h	/^ unsigned int lookaround_rate_mrr;$/;"	m	struct:ssv_minstrel_priv	access:public
+loop_times	smac/dev.h	/^    u32 loop_times;$/;"	m	struct:_ssv6xxx_txtput	access:public
+lowest_rate	smac/ssv_skb.h	/^    u16 lowest_rate;$/;"	m	struct:SKB_info_st	access:public
+lowest_rix	smac/ssv_rc_minstrel.h	/^ unsigned int lowest_rix;$/;"	m	struct:ssv_minstrel_sta_info	access:public
+lpbk_enable	smac/dev.h	/^    bool lpbk_enable;$/;"	m	struct:ssv_softc	access:public
+lpbk_err_cnt	smac/dev.h	/^    int lpbk_err_cnt;$/;"	m	struct:ssv_softc	access:public
+lpbk_mode	include/ssv_cfg.h	/^    u32 lpbk_mode;$/;"	m	struct:ssv6xxx_cfg	access:public
+lpbk_pkt_cnt	include/ssv_cfg.h	/^    u32 lpbk_pkt_cnt;$/;"	m	struct:ssv6xxx_cfg	access:public
+lpbk_rx_pkt_cnt	smac/dev.h	/^    int lpbk_rx_pkt_cnt;$/;"	m	struct:ssv_softc	access:public
+lpbk_sec	include/ssv_cfg.h	/^    u32 lpbk_sec;$/;"	m	struct:ssv6xxx_cfg	access:public
+lpbk_tx_pkt_cnt	smac/dev.h	/^    int lpbk_tx_pkt_cnt;$/;"	m	struct:ssv_softc	access:public
+lpbk_type	include/ssv_cfg.h	/^    u32 lpbk_type;$/;"	m	struct:ssv6xxx_cfg	access:public
+lt_config	smac/dev.h	/^    struct ssv_tempe_table lt_config;$/;"	m	struct:ssv_flash_config	typeref:struct:ssv_flash_config::ssv_tempe_table	access:public
+mac80211_dev_started	smac/dev.h	/^    bool mac80211_dev_started;$/;"	m	struct:ssv_softc	access:public
+mac_address_mode	include/ssv_cfg.h	/^    u32 mac_address_mode;$/;"	m	struct:ssv6xxx_cfg	access:public
+mac_address_path	include/ssv_cfg.h	/^    u8 mac_address_path[128];$/;"	m	struct:ssv6xxx_cfg	access:public
+mac_deci_tbl	smac/dev.h	/^    u16 *mac_deci_tbl;$/;"	m	struct:ssv_softc	access:public
+mac_output_path	include/ssv_cfg.h	/^    u8 mac_output_path[128];$/;"	m	struct:ssv6xxx_cfg	access:public
+maddr	include/ssv_cfg.h	/^    u8 maddr[2][6];$/;"	m	struct:ssv6xxx_cfg	access:public
+maddr	smac/dev.h	/^    struct mac_address maddr[SSV6200_MAX_HW_MAC_ADDR];$/;"	m	struct:ssv_hw	typeref:struct:ssv_hw::mac_address	access:public
+main	smartlink/airkiss.c	/^int main(int argc, char *argv[])$/;"	f	signature:(int argc, char *argv[])
+main	smartlink/qqlink-lib-mipsel/case/ipcamera/main.c	/^int main(int argc, char* argv[]) {$/;"	f	signature:(int argc, char* argv[])
+main	smartlink/qqlink-lib-mipsel/demo_bind.c	/^int main(int argc, char* argv[]) {$/;"	f	signature:(int argc, char* argv[])
+main	smartlink/qqlink-lib-mipsel/demo_filetransfer.c	/^int main(int argc, char* argv[]) {$/;"	f	signature:(int argc, char* argv[])
+main	smartlink/qqlink-lib-mipsel/demo_video.c	/^int main(int argc, char* argv[]) {$/;"	f	signature:(int argc, char* argv[])
+main	smartlink/qqlink.c	/^int main(int argc, char *argv[])$/;"	f	signature:(int argc, char *argv[])
+main	smartlink/smarticomm.c	/^void main(void)$/;"	f	signature:(void)
+manage_txq_size	include/ssv6xxx_common.h	/^ u32 manage_txq_size;$/;"	m	struct:ssv6xxx_tx_hw_info	access:public
+manage_txq_size	include/ssv_cfg.h	/^    u32 manage_txq_size;$/;"	m	struct:ssv6xxx_cfg	access:public
+mask0	smac/hal/ssv6006c/turismo_common.h	/^    u32 mask0;$/;"	m	struct:padpd_table	access:public
+mask1	smac/hal/ssv6006c/turismo_common.h	/^    u32 mask1;$/;"	m	struct:padpd_table	access:public
+max_ampdu_size	smac/dev.h	/^    u16 max_ampdu_size;$/;"	m	struct:ssv_sta_priv_data	access:public
+max_crypted_q_len	smac/dev.h	/^    u32 max_crypted_q_len;$/;"	m	struct:ssv_softc	access:public
+max_preprocess_q_len	smac/dev.h	/^    u32 max_preprocess_q_len;$/;"	m	struct:ssv_softc	access:public
+max_prob_rate	smac/ssv_rc_common.h	/^    unsigned int max_prob_rate;$/;"	m	struct:minstrel_mcs_group_data	access:public
+max_prob_rate	smac/ssv_rc_common.h	/^    unsigned int max_prob_rate;$/;"	m	struct:ssv62xx_ht	access:public
+max_prob_rate	smac/ssv_rc_minstrel.h	/^ unsigned int max_prob_rate;$/;"	m	struct:ssv_minstrel_sta_info	access:public
+max_prob_rate	smac/ssv_rc_minstrel_ht.h	/^ unsigned int max_prob_rate;$/;"	m	struct:ssv_minstrel_ht_mcs_group_data	access:public
+max_prob_rate	smac/ssv_rc_minstrel_ht.h	/^ unsigned int max_prob_rate;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+max_qsize	hci/ssv_hci.h	/^    int max_qsize;$/;"	m	struct:ssv_hw_txq	access:public
+max_rate_idx	smac/dev.h	/^    int max_rate_idx;$/;"	m	struct:ssv_softc	access:public
+max_rates	smac/ssv_rc_minstrel.h	/^ unsigned int max_rates;$/;"	m	struct:ssv_minstrel_priv	access:public
+max_retry	smac/ssv_rc_minstrel.h	/^ unsigned int max_retry;$/;"	m	struct:ssv_minstrel_priv	access:public
+max_rx_aggr_size	include/ssv_cfg.h	/^ u32 max_rx_aggr_size;$/;"	m	struct:ssv6xxx_cfg	access:public
+max_size	smac/ssv_skb.h	/^    u32 max_size;$/;"	m	struct:ampdu_hdr_st	access:public
+max_tp_rate	smac/ssv_rc_common.h	/^    unsigned int max_tp_rate;$/;"	m	struct:minstrel_mcs_group_data	access:public
+max_tp_rate	smac/ssv_rc_common.h	/^    unsigned int max_tp_rate;$/;"	m	struct:ssv62xx_ht	access:public
+max_tp_rate	smac/ssv_rc_minstrel.h	/^ unsigned int max_tp_rate;$/;"	m	struct:ssv_minstrel_sta_info	access:public
+max_tp_rate	smac/ssv_rc_minstrel_ht.h	/^ unsigned int max_tp_rate;$/;"	m	struct:ssv_minstrel_ht_mcs_group_data	access:public
+max_tp_rate	smac/ssv_rc_minstrel_ht.h	/^ unsigned int max_tp_rate;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+max_tp_rate2	smac/ssv_rc_common.h	/^    unsigned int max_tp_rate2;$/;"	m	struct:minstrel_mcs_group_data	access:public
+max_tp_rate2	smac/ssv_rc_common.h	/^    unsigned int max_tp_rate2;$/;"	m	struct:ssv62xx_ht	access:public
+max_tp_rate2	smac/ssv_rc_minstrel.h	/^ unsigned int max_tp_rate2;$/;"	m	struct:ssv_minstrel_sta_info	access:public
+max_tp_rate2	smac/ssv_rc_minstrel_ht.h	/^ unsigned int max_tp_rate2;$/;"	m	struct:ssv_minstrel_ht_mcs_group_data	access:public
+max_tp_rate2	smac/ssv_rc_minstrel_ht.h	/^ unsigned int max_tp_rate2;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+max_tx_frame	hci/hctrl.h	/^ int max_tx_frame[SSV_HW_TXQ_NUM];$/;"	m	struct:ssv6xxx_hw_resource	access:public
+max_tx_skb_q_len	smac/dev.h	/^    u32 max_tx_skb_q_len;$/;"	m	struct:ssv_softc	access:public
+mcs_group	smac/ssv_rc_common.h	/^struct mcs_group {$/;"	s
+mcs_group::duration	smac/ssv_rc_common.h	/^    unsigned int duration[MCS_GROUP_RATES];$/;"	m	struct:mcs_group	access:public
+mem_mutex	smac/dev.h	/^    struct mutex mem_mutex;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::mutex	access:public
+mem_prealloc	platforms/a33-generic-wlan.c	/^    void *(*mem_prealloc)(int section, unsigned long size);$/;"	m	struct:wifi_platform_data	file:	access:public
+mem_prealloc	platforms/atm7039-action-generic-wlan.c	/^ void *(*mem_prealloc)(int section, unsigned long size);$/;"	m	struct:wifi_platform_data	file:	access:public
+mem_prealloc	platforms/h3-generic-wlan.c	/^ void *(*mem_prealloc)(int section, unsigned long size);$/;"	m	struct:wifi_platform_data	file:	access:public
+mem_prealloc	platforms/h8-generic-wlan.c	/^ void *(*mem_prealloc)(int section, unsigned long size);$/;"	m	struct:wifi_platform_data	file:	access:public
+mem_prealloc	platforms/rk3126-generic-wlan.c	/^    void *(*mem_prealloc)(int section, unsigned long size);$/;"	m	struct:wifi_platform_data	file:	access:public
+mem_prealloc	platforms/t10-generic-wlan.c	/^ void *(*mem_prealloc)(int section, unsigned long size);$/;"	m	struct:wifi_platform_data	file:	access:public
+mem_prealloc	platforms/x1000-generic-wlan.c	/^ void *(*mem_prealloc)(int section, unsigned long size);$/;"	m	struct:wifi_platform_data	file:	access:public
+memcmp	smartlink/airkiss-lib/airkiss.h	/^ airkiss_memcmp_fn memcmp;$/;"	m	struct:__anon23	access:public
+memcmp	smartlink/airkiss-lib/mipsel/airkiss.h	/^ airkiss_memcmp_fn memcmp;$/;"	m	struct:__anon17	access:public
+memcmp	smartlink/airkiss-lib/x64/airkiss.h	/^ airkiss_memcmp_fn memcmp;$/;"	m	struct:__anon29	access:public
+memcpy	smartlink/airkiss-lib/airkiss.h	/^ airkiss_memcpy_fn memcpy;$/;"	m	struct:__anon23	access:public
+memcpy	smartlink/airkiss-lib/mipsel/airkiss.h	/^ airkiss_memcpy_fn memcpy;$/;"	m	struct:__anon17	access:public
+memcpy	smartlink/airkiss-lib/x64/airkiss.h	/^ airkiss_memcpy_fn memcpy;$/;"	m	struct:__anon29	access:public
+memset	smartlink/airkiss-lib/airkiss.h	/^ airkiss_memset_fn memset;$/;"	m	struct:__anon23	access:public
+memset	smartlink/airkiss-lib/mipsel/airkiss.h	/^ airkiss_memset_fn memset;$/;"	m	struct:__anon17	access:public
+memset	smartlink/airkiss-lib/x64/airkiss.h	/^ airkiss_memset_fn memset;$/;"	m	struct:__anon29	access:public
+mf	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 mf:1;$/;"	m	struct:ssv6006_rc_idx	access:public
+mget_key_index	smac/sec_wpi.c	/^u8 mget_key_index(void *priv)$/;"	f	signature:(void *priv)
+mget_mic_key	smac/sec_wpi.c	/^u8* mget_mic_key(int index, void *priv)$/;"	f	signature:(int index, void *priv)
+mget_pmsk_key	smac/sec_wpi.c	/^u8 *mget_pmsk_key(int index, void *priv)$/;"	f	signature:(int index, void *priv)
+mget_pn_key	smac/sec_wpi.c	/^u8* mget_pn_key(void *priv)$/;"	f	signature:(void *priv)
+mget_wapi_address	smac/sec_wpi.c	/^u8* mget_wapi_address(void *priv)$/;"	f	signature:(void *priv)
+mget_wapi_enable	smac/sec_wpi.c	/^TRUTH_VALUE_T mget_wapi_enable(void *priv)$/;"	f	signature:(void *priv)
+mget_wapi_key_ok	smac/sec_wpi.c	/^TRUTH_VALUE_T mget_wapi_key_ok(void *priv)$/;"	f	signature:(void *priv)
+mget_wapi_version	smac/sec_wpi.c	/^u8* mget_wapi_version(void *priv)$/;"	f	signature:(void *priv)
+mib	smac/ampdu.h	/^    struct AMPDU_MIB_st mib;$/;"	m	struct:AMPDU_TID_st	typeref:struct:AMPDU_TID_st::AMPDU_MIB_st	access:public
+mib_dump_data	smac/ampdu.c	/^struct mib_dump_data {$/;"	s	file:
+mib_dump_data::buff_size	smac/ampdu.c	/^    size_t buff_size;$/;"	m	struct:mib_dump_data	file:	access:public
+mib_dump_data::prt_buff	smac/ampdu.c	/^    char *prt_buff;$/;"	m	struct:mib_dump_data	file:	access:public
+mib_dump_data::prt_len	smac/ampdu.c	/^    size_t prt_len;$/;"	m	struct:mib_dump_data	file:	access:public
+mib_edca_work	smac/dev.h	/^    struct work_struct mib_edca_work;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::work_struct	access:public
+mib_reset_fops	smac/ampdu.c	/^static const struct file_operations mib_reset_fops$/;"	v	typeref:struct:file_operations	file:
+mib_summary_fops	smac/ampdu.c	/^static const struct file_operations mib_summary_fops = { .read =$/;"	v	typeref:struct:file_operations	file:
+mic_err_notify	include/ssv_cfg.h	/^    u32 mic_err_notify;$/;"	m	struct:ssv6xxx_cfg	access:public
+mic_key	smac/sec_wpi.c	/^ u8 mic_key[3][WAPI_PN_LEN];$/;"	m	struct:lib80211_wpi_data	file:	access:public
+michael_mic	smac/sec_tkip.c	/^static int michael_mic(struct crypto_ahash *tfm_michael, u8 * key, u8 * hdr,$/;"	f	file:	signature:(struct crypto_ahash *tfm_michael, u8 * key, u8 * hdr, u8 * data, size_t data_len, u8 * mic)
+michael_mic	smac/sec_tkip.c	/^static int michael_mic(struct crypto_hash *tfm_michael, u8 * key, u8 * hdr,$/;"	f	file:	signature:(struct crypto_hash *tfm_michael, u8 * key, u8 * hdr, u8 * data, size_t data_len, u8 * mic)
+michael_mic_hdr	smac/sec_tkip.c	/^static void michael_mic_hdr(struct sk_buff *skb, u8 * hdr)$/;"	f	file:	signature:(struct sk_buff *skb, u8 * hdr)
+minstrel_calc_rate_ewma	smac/ssv_ht_rc.c	/^static void minstrel_calc_rate_ewma(struct minstrel_rate_stats *mr)$/;"	f	file:	signature:(struct minstrel_rate_stats *mr)
+minstrel_ewma	smac/ssv_ht_rc.c	/^static int minstrel_ewma(int old, int new, int weight)$/;"	f	file:	signature:(int old, int new, int weight)
+minstrel_ewma	smac/ssv_rc_minstrel.c	/^int minstrel_ewma(int old, int new, int weight)$/;"	f	signature:(int old, int new, int weight)
+minstrel_ewma	smac/ssv_rc_minstrel.h	/^int minstrel_ewma(int old, int new, int weight);$/;"	p	signature:(int old, int new, int weight)
+minstrel_get_duration	smac/ssv_ht_rc.c	/^static inline int minstrel_get_duration(int index, struct ssv_sta_rc_info *rc_sta)$/;"	f	file:	signature:(int index, struct ssv_sta_rc_info *rc_sta)
+minstrel_get_next_sample	smac/ssv_rc_minstrel.c	/^static int minstrel_get_next_sample(struct ssv_minstrel_sta_priv *minstrel_sta_priv)$/;"	f	file:	signature:(struct ssv_minstrel_sta_priv *minstrel_sta_priv)
+minstrel_get_ratestats	smac/ssv_ht_rc.c	/^static inline struct minstrel_rate_stats *minstrel_get_ratestats(struct ssv62xx_ht *mi, int index)$/;"	f	file:	signature:(struct ssv62xx_ht *mi, int index)
+minstrel_get_retry_count	smac/ssv_rc_minstrel.c	/^static inline unsigned int minstrel_get_retry_count(struct ssv_minstrel_rate *mr,$/;"	f	file:	signature:(struct ssv_minstrel_rate *mr, struct ieee80211_tx_info *info)
+minstrel_get_sample_rate	smac/ssv_ht_rc.c	/^static int minstrel_get_sample_rate(struct ssv62xx_ht *mi, struct ssv_sta_rc_info *rc_sta)$/;"	f	file:	signature:(struct ssv62xx_ht *mi, struct ssv_sta_rc_info *rc_sta)
+minstrel_ht_calc_tp	smac/ssv_ht_rc.c	/^static void minstrel_ht_calc_tp(struct ssv62xx_ht *mi, struct ssv_sta_rc_info *rc_sta, int rate)$/;"	f	file:	signature:(struct ssv62xx_ht *mi, struct ssv_sta_rc_info *rc_sta, int rate)
+minstrel_ht_set_rate	smac/ssv_ht_rc.c	/^static void minstrel_ht_set_rate(struct ssv62xx_ht *mi,$/;"	f	file:	signature:(struct ssv62xx_ht *mi, struct fw_rc_retry_params *rate, int index, bool sample, bool rtscts, struct ssv_sta_rc_info *rc_sta, struct ssv_rate_ctrl *ssv_rc)
+minstrel_ht_txstat_valid	smac/ssv_ht_rc.c	/^static bool minstrel_ht_txstat_valid(struct ssv62xx_tx_rate *rate)$/;"	f	file:	signature:(struct ssv62xx_tx_rate *rate)
+minstrel_mcs_group_data	smac/ssv_rc_common.h	/^struct minstrel_mcs_group_data {$/;"	s
+minstrel_mcs_group_data::column	smac/ssv_rc_common.h	/^    u8 column;$/;"	m	struct:minstrel_mcs_group_data	access:public
+minstrel_mcs_group_data::index	smac/ssv_rc_common.h	/^    u8 index;$/;"	m	struct:minstrel_mcs_group_data	access:public
+minstrel_mcs_group_data::max_prob_rate	smac/ssv_rc_common.h	/^    unsigned int max_prob_rate;$/;"	m	struct:minstrel_mcs_group_data	access:public
+minstrel_mcs_group_data::max_tp_rate	smac/ssv_rc_common.h	/^    unsigned int max_tp_rate;$/;"	m	struct:minstrel_mcs_group_data	access:public
+minstrel_mcs_group_data::max_tp_rate2	smac/ssv_rc_common.h	/^    unsigned int max_tp_rate2;$/;"	m	struct:minstrel_mcs_group_data	access:public
+minstrel_mcs_group_data::rates	smac/ssv_rc_common.h	/^    struct minstrel_rate_stats rates[MCS_GROUP_RATES];$/;"	m	struct:minstrel_mcs_group_data	typeref:struct:minstrel_mcs_group_data::minstrel_rate_stats	access:public
+minstrel_mcs_groups	smac/ssv_ht_rc.c	/^const struct mcs_group minstrel_mcs_groups[] = {$/;"	v	typeref:struct:mcs_group
+minstrel_next_sample_idx	smac/ssv_ht_rc.c	/^static void minstrel_next_sample_idx(struct ssv62xx_ht *mi)$/;"	f	file:	signature:(struct ssv62xx_ht *mi)
+minstrel_rate_stats	smac/ssv_rc_common.h	/^struct minstrel_rate_stats {$/;"	s
+minstrel_rate_stats::att_hist	smac/ssv_rc_common.h	/^    u64 att_hist, succ_hist;$/;"	m	struct:minstrel_rate_stats	access:public
+minstrel_rate_stats::attempts	smac/ssv_rc_common.h	/^    unsigned int attempts, last_attempts;$/;"	m	struct:minstrel_rate_stats	access:public
+minstrel_rate_stats::cur_prob	smac/ssv_rc_common.h	/^    unsigned int cur_prob, probability;$/;"	m	struct:minstrel_rate_stats	access:public
+minstrel_rate_stats::cur_tp	smac/ssv_rc_common.h	/^    unsigned int cur_tp;$/;"	m	struct:minstrel_rate_stats	access:public
+minstrel_rate_stats::last_attempts	smac/ssv_rc_common.h	/^    unsigned int attempts, last_attempts;$/;"	m	struct:minstrel_rate_stats	access:public
+minstrel_rate_stats::last_success	smac/ssv_rc_common.h	/^    unsigned int success, last_success;$/;"	m	struct:minstrel_rate_stats	access:public
+minstrel_rate_stats::probability	smac/ssv_rc_common.h	/^    unsigned int cur_prob, probability;$/;"	m	struct:minstrel_rate_stats	access:public
+minstrel_rate_stats::rc_index	smac/ssv_rc_common.h	/^    u16 rc_index;$/;"	m	struct:minstrel_rate_stats	access:public
+minstrel_rate_stats::retry_count	smac/ssv_rc_common.h	/^    unsigned int retry_count;$/;"	m	struct:minstrel_rate_stats	access:public
+minstrel_rate_stats::retry_count_rtscts	smac/ssv_rc_common.h	/^    unsigned int retry_count_rtscts;$/;"	m	struct:minstrel_rate_stats	access:public
+minstrel_rate_stats::sample_skipped	smac/ssv_rc_common.h	/^    u8 sample_skipped;$/;"	m	struct:minstrel_rate_stats	access:public
+minstrel_rate_stats::succ_hist	smac/ssv_rc_common.h	/^    u64 att_hist, succ_hist;$/;"	m	struct:minstrel_rate_stats	access:public
+minstrel_rate_stats::success	smac/ssv_rc_common.h	/^    unsigned int success, last_success;$/;"	m	struct:minstrel_rate_stats	access:public
+mitigate_cci	smac/dev.c	/^void mitigate_cci(struct ssv_softc *sc, struct ssv_sta_priv_data *sta_priv, u32 input_level)$/;"	f	signature:(struct ssv_softc *sc, struct ssv_sta_priv_data *sta_priv, u32 input_level)
+mmc_rescan_sdio	platforms/xm-hi3518-generic-wlan.c	/^extern void mmc_rescan_sdio(void);$/;"	p	file:	signature:(void)
+mng_used	include/ssv6200_common.h	/^    u32 mng_used:4;$/;"	m	struct:ssv6200_rx_desc	access:public
+mode	include/ssv6200_common.h	/^    u32 mode:3;$/;"	m	struct:ssv6200_rxphy_info	access:public
+monitor_noa_vif	smac/p2p.h	/^    u8 monitor_noa_vif;$/;"	m	struct:ssv_p2p_noa	access:public
+monitoring	smac/ssv_rc_common.h	/^    u8 monitoring;$/;"	m	struct:rc_pid_sta_info	access:public
+more_data	include/ssv6200_common.h	/^    u32 more_data:1;$/;"	m	struct:ssv6200_tx_desc	access:public
+more_data	smac/hal/ssv6006c/turismo_common.h	/^    u32 more_data:1;$/;"	m	struct:ssv6006_tx_desc	access:public
+mpdu_num	smac/dev.h	/^    u16 mpdu_num;$/;"	m	struct:aggr_ssn	access:public
+mpdu_num	smac/ssv_skb.h	/^    u16 mpdu_num;$/;"	m	struct:ampdu_hdr_st	access:public
+mpdu_q	smac/ssv_skb.h	/^    struct sk_buff_head mpdu_q;$/;"	m	struct:ampdu_hdr_st	typeref:struct:ampdu_hdr_st::sk_buff_head	access:public
+mpdu_retry_counter	smac/ssv_skb.h	/^    u16 mpdu_retry_counter;$/;"	m	struct:SKB_info_st	access:public
+mrx_seqn	smac/hal/ssv6006c/turismo_common.h	/^    u32 mrx_seqn:1;$/;"	m	struct:ssv6006_rxphy_info	access:public
+mset_key_index	smac/sec_wpi.c	/^void mset_key_index(int index, void *priv)$/;"	f	signature:(int index, void *priv)
+mset_mic_key	smac/sec_wpi.c	/^void mset_mic_key(int index,u8* val, void *priv)$/;"	f	signature:(int index,u8* val, void *priv)
+mset_pmsk_key	smac/sec_wpi.c	/^void mset_pmsk_key(int index,u8* val, void *priv)$/;"	f	signature:(int index,u8* val, void *priv)
+mset_pn_key	smac/sec_wpi.c	/^void mset_pn_key(u8* val, void *priv)$/;"	f	signature:(u8* val, void *priv)
+mset_wapi_address	smac/sec_wpi.c	/^void mset_wapi_address(u8* val, void *priv)$/;"	f	signature:(u8* val, void *priv)
+mset_wapi_enable	smac/sec_wpi.c	/^void mset_wapi_enable(TRUTH_VALUE_T val, void *priv)$/;"	f	signature:(TRUTH_VALUE_T val, void *priv)
+mset_wapi_key_ok	smac/sec_wpi.c	/^void mset_wapi_key_ok(TRUTH_VALUE_T val, void *priv)$/;"	f	signature:(TRUTH_VALUE_T val, void *priv)
+mset_wapi_version	smac/sec_wpi.c	/^void mset_wapi_version(u8* val, void *priv)$/;"	f	signature:(u8* val, void *priv)
+msg_ele_array	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^    tx_barrage_msg_element * msg_ele_array;$/;"	m	struct:tag_tx_barrage_msg	access:public
+msg_ele_count	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^    int msg_ele_count;$/;"	m	struct:tag_tx_barrage_msg	access:public
+msg_ele_point	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^    void * msg_ele_point;$/;"	m	struct:tag_tx_barrage_msg_element	access:public
+msg_ele_type	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^    int msg_ele_type;$/;"	m	struct:tag_tx_barrage_msg_element	access:public
+msg_id	smartlink/qqlink-lib-mipsel/include/TXMsg.h	/^ int msg_id;$/;"	m	struct:tag_structuring_msg	access:public
+msg_text	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^    char * msg_text;$/;"	m	struct:tag_tx_text_msg_element	access:public
+multi_tid	smac/ampdu.h	/^    u16 multi_tid:1;$/;"	m	struct:AMPDU_BLOCKACK_st	access:public
+mutex	smac/dev.h	/^    struct mutex mutex;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::mutex	access:public
+n	smartlink/ssv_smartlink.c	/^    struct nlmsghdr n;$/;"	m	struct:netlink_msg	typeref:struct:netlink_msg::nlmsghdr	file:	access:public
+n_addresses	smac/dev.h	/^    u32 n_addresses;$/;"	m	struct:ssv_hw	access:public
+n_ess	include/ssv6200_common.h	/^    u32 n_ess:2;$/;"	m	struct:ssv6200_rxphy_info	access:public
+n_ess	smac/hal/ssv6006c/turismo_common.h	/^    u32 n_ess:2;$/;"	m	struct:ssv6006_rxphy_info	access:public
+n_maddr	include/ssv_cfg.h	/^    u32 n_maddr;$/;"	m	struct:ssv6xxx_cfg	access:public
+n_pkts	smac/dev.h	/^    u64 n_pkts[8];$/;"	m	struct:rx_stats	access:public
+n_rates	smac/ssv_rc_minstrel.h	/^ int n_rates;$/;"	m	struct:ssv_minstrel_sta_info	access:public
+name	smac/sec.h	/^ const char *name;$/;"	m	struct:ssv_crypto_ops	access:public
+need_sw_cipher	smac/dev.h	/^ bool (*need_sw_cipher)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+need_sw_decrypt	smac/dev.h	/^    bool need_sw_decrypt;$/;"	m	struct:ssv_sta_priv_data	access:public
+need_sw_decrypt	smac/dev.h	/^    bool need_sw_decrypt;$/;"	m	struct:ssv_vif_priv_data	access:public
+need_sw_encrypt	smac/dev.h	/^    bool need_sw_encrypt;$/;"	m	struct:ssv_sta_priv_data	access:public
+need_sw_encrypt	smac/dev.h	/^    bool need_sw_encrypt;$/;"	m	struct:ssv_vif_priv_data	access:public
+netlink_msg	smartlink/ssv_smartlink.c	/^struct netlink_msg {$/;"	s	file:
+netlink_msg::buf	smartlink/ssv_smartlink.c	/^    char buf[MAX_PAYLOAD];$/;"	m	struct:netlink_msg	file:	access:public
+netlink_msg::g	smartlink/ssv_smartlink.c	/^    struct genlmsghdr g;$/;"	m	struct:netlink_msg	typeref:struct:netlink_msg::genlmsghdr	file:	access:public
+netlink_msg::n	smartlink/ssv_smartlink.c	/^    struct nlmsghdr n;$/;"	m	struct:netlink_msg	typeref:struct:netlink_msg::nlmsghdr	file:	access:public
+network_type	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    int network_type;$/;"	m	struct:_tx_device_info	access:public
+network_type_hongkong	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^ network_type_hongkong = 5,$/;"	e	enum:tx_network_type
+network_type_mobile	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^ network_type_mobile = 2,$/;"	e	enum:tx_network_type
+network_type_none	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^ network_type_none = 0,$/;"	e	enum:tx_network_type
+network_type_telecom	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^ network_type_telecom = 4,$/;"	e	enum:tx_network_type
+network_type_unicom	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^ network_type_unicom = 3,$/;"	e	enum:tx_network_type
+network_type_wifi	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^ network_type_wifi = 1,$/;"	e	enum:tx_network_type
+nick_name	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    char nick_name[128];$/;"	m	struct:tag_tx_binder_info	access:public
+no_pkt_buf_reduction	smac/hal/ssv6006c/turismo_common.h	/^    u32 no_pkt_buf_reduction:1;$/;"	m	struct:ssv6006_tx_desc	access:public
+no_sounding	include/ssv6200_common.h	/^    u32 no_sounding:1;$/;"	m	struct:ssv6200_rxphy_info	access:public
+no_sounding	smac/hal/ssv6006c/turismo_common.h	/^    u32 no_sounding:1;$/;"	m	struct:ssv6006_rxphy_info	access:public
+noa_addr	smac/p2p.h	/^    const u8 *noa_addr;$/;"	m	struct:ssv_p2p_noa_detect	access:public
+noa_detect	smac/p2p.h	/^    struct ssv_p2p_noa_detect noa_detect[SSV_NUM_VIF];$/;"	m	struct:ssv_p2p_noa	typeref:struct:ssv_p2p_noa::ssv_p2p_noa_detect	access:public
+noa_dump	ssvdevice/ssv_cmd.c	/^void noa_dump(struct ssv_cmd_data *cmd_data)$/;"	f	signature:(struct ssv_cmd_data *cmd_data)
+noa_param	smac/p2p.c	/^    struct ssv6xxx_p2p_noa_param noa_param;$/;"	m	struct:ssv6xxx_p2p_noa_attribute	typeref:struct:ssv6xxx_p2p_noa_attribute::ssv6xxx_p2p_noa_param	file:	access:public
+noa_param_cmd	smac/p2p.h	/^    struct ssv6xxx_p2p_noa_param noa_param_cmd;$/;"	m	struct:ssv_p2p_noa_detect	typeref:struct:ssv_p2p_noa_detect::ssv6xxx_p2p_noa_param	access:public
+node	hwif/usb/usb.h	/^    struct ssv6xxx_list_node node;$/;"	m	struct:ssv6xxx_rx_buf	typeref:struct:ssv6xxx_rx_buf::ssv6xxx_list_node	access:public
+nullfun_frame_filter	smac/dev.h	/^    bool (*nullfun_frame_filter)(struct sk_buff *skb);$/;"	m	struct:ssv_hal_ops	access:public
+num_of_dev	bridge/sdiobridge.c	/^static unsigned int num_of_dev = 1;$/;"	v	file:
+num_of_dev	hci_wrapper/ssv_huw.c	/^static unsigned int num_of_dev = 1;$/;"	v	file:
+nvif	smac/dev.h	/^    u8 nvif;$/;"	m	struct:ssv_softc	access:public
+occupied_tx_pages	smac/dev.h	/^    u32 occupied_tx_pages;$/;"	m	struct:_ssv6xxx_txtput	access:public
+offset	smac/efuse.h	/^    u8 offset;$/;"	m	struct:efuse_map	access:public
+oldfs	smac/efuse.c	/^mm_segment_t oldfs;$/;"	v
+oldrate	smac/ssv_rc_common.h	/^    u8 oldrate;$/;"	m	struct:rc_pid_sta_info	access:public
+oldrate	smac/ssv_rc_common.h	/^ int oldrate;$/;"	m	struct:rc_pid_info	access:public
+on_ack_data_point_ret	smartlink/qqlink-lib-mipsel/include/TXDataPoint.h	/^typedef void (*on_ack_data_point_ret)(unsigned int cookie, unsigned long long from_client, int err_code);$/;"	t
+on_bind_complete	smartlink/qqlink-lib-mipsel/include/TXTVSDK.h	/^ void (*on_bind_complete)(unsigned long long ddwID, int error);$/;"	m	struct:tag_tx_tv_notify	access:public
+on_binder_list_change	smartlink/qqlink-lib-mipsel/case/ipcamera/main.c	/^void on_binder_list_change(int error_code, tx_binder_info * pBinderList, int nCount)$/;"	f	signature:(int error_code, tx_binder_info * pBinderList, int nCount)
+on_binder_list_change	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    void (*on_binder_list_change)(int error_code, tx_binder_info * pBinderList, int nCount);$/;"	m	struct:_tx_device_notify	access:public
+on_control_rotate	smartlink/qqlink-lib-mipsel/include/TXIPCAM.h	/^ int (*on_control_rotate)(int rotate_direction, int rotate_degree);$/;"	m	struct:_tx_ipcamera_notify	access:public
+on_download_complete	smartlink/qqlink-lib-mipsel/include/TXOTA.h	/^ void (*on_download_complete)(int ret_code);$/;"	m	struct:_tx_ota_notify	access:public
+on_download_progress	smartlink/qqlink-lib-mipsel/include/TXOTA.h	/^ void (*on_download_progress)(unsigned long long download_size, unsigned long long total_size);$/;"	m	struct:_tx_ota_notify	access:public
+on_erase_all_binders	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^typedef void (*on_erase_all_binders)(int error_code);$/;"	t
+on_fetch_history_video	smartlink/qqlink-lib-mipsel/include/TXIPCAM.h	/^ void (*on_fetch_history_video)(unsigned int last_time, int max_count, int *count, tx_history_video_range * range_list);$/;"	m	struct:_tx_history_video_notify	access:public
+on_file_in_come	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^    void (*on_file_in_come)(unsigned long long transfer_cookie, const tx_ccmsg_inst_info * inst_info, const tx_file_transfer_info * tran_info);$/;"	m	struct:tag_tx_file_transfer_notify	access:public
+on_file_transfer_progress	smartlink/qqlink-lib-mipsel/include/TXMsg.h	/^    void (*on_file_transfer_progress)(const unsigned int cookie, unsigned long long transfer_progress, unsigned long long max_transfer_progress);$/;"	m	struct:_tx_send_msg_notify	access:public
+on_get_binder_list_result	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^typedef void (*on_get_binder_list_result)(tx_binder_info * pBinderList, int nCount);$/;"	t
+on_login_complete	smartlink/qqlink-lib-mipsel/case/ipcamera/main.c	/^void on_login_complete(int errcode) {$/;"	f	signature:(int errcode)
+on_login_complete	smartlink/qqlink-lib-mipsel/demo_bind.c	/^void on_login_complete(int errcode) {$/;"	f	signature:(int errcode)
+on_login_complete	smartlink/qqlink-lib-mipsel/demo_filetransfer.c	/^void on_login_complete(int errcode) {$/;"	f	signature:(int errcode)
+on_login_complete	smartlink/qqlink-lib-mipsel/demo_video.c	/^void on_login_complete(int errcode) {$/;"	f	signature:(int errcode)
+on_login_complete	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    void (*on_login_complete)(int error_code);$/;"	m	struct:_tx_device_notify	access:public
+on_new_pkg_come	smartlink/qqlink-lib-mipsel/include/TXOTA.h	/^ int (*on_new_pkg_come)(unsigned long long from, unsigned long long pkg_size, const char * title, const char * desc, unsigned int target_version);$/;"	m	struct:_tx_ota_notify	access:public
+on_online_status	smartlink/qqlink-lib-mipsel/case/ipcamera/main.c	/^void on_online_status(int old, int new) {$/;"	f	signature:(int old, int new)
+on_online_status	smartlink/qqlink-lib-mipsel/demo_bind.c	/^void on_online_status(int old, int new) {$/;"	f	signature:(int old, int new)
+on_online_status	smartlink/qqlink-lib-mipsel/demo_filetransfer.c	/^void on_online_status(int old, int new) {$/;"	f	signature:(int old, int new)
+on_online_status	smartlink/qqlink-lib-mipsel/demo_video.c	/^void on_online_status(int old, int new) {$/;"	f	signature:(int old, int new)
+on_online_status	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    void (*on_online_status)(int old_status, int new_status);$/;"	m	struct:_tx_device_notify	access:public
+on_play_history_video	smartlink/qqlink-lib-mipsel/include/TXIPCAM.h	/^ void (*on_play_history_video)(unsigned int play_time);$/;"	m	struct:_tx_history_video_notify	access:public
+on_receive_barrage_msg	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^ void (*on_receive_barrage_msg)(tx_barrage_msg * pMsg);$/;"	m	struct:tag_tx_barrage_notify	access:public
+on_receive_data_point	smartlink/qqlink-lib-mipsel/include/TXDataPoint.h	/^    void (*on_receive_data_point)(unsigned long long from_client, tx_data_point * data_points, int data_points_count);$/;"	m	struct:tag_tx_data_point_notify	access:public
+on_receive_video_push	smartlink/qqlink-lib-mipsel/include/TXTVSDK.h	/^ void (*on_receive_video_push)(char * pBufReply, int nLenReply);$/;"	m	struct:tag_tx_tv_notify	access:public
+on_receive_video_reply	smartlink/qqlink-lib-mipsel/include/TXTVSDK.h	/^typedef void (*on_receive_video_reply)(char * pBufReply, int nLenReply);$/;"	t
+on_recv_audiodata	smartlink/qqlink-lib-mipsel/include/TXAudioVideo.h	/^    void (*on_recv_audiodata)(tx_audio_encode_param *param, unsigned char *pcEncData, int nEncDataLen);$/;"	m	struct:_tx_av_callback	access:public
+on_report_data_point_ret	smartlink/qqlink-lib-mipsel/include/TXDataPoint.h	/^typedef void (*on_report_data_point_ret)(unsigned int cookie, int err_code);$/;"	t
+on_send_alarm_file_progress	smartlink/qqlink-lib-mipsel/case/ipcamera/alarm.c	/^void on_send_alarm_file_progress(const unsigned int cookie, unsigned long long transfer_progress, unsigned long long max_transfer_progress)$/;"	f	signature:(const unsigned int cookie, unsigned long long transfer_progress, unsigned long long max_transfer_progress)
+on_send_alarm_msg_ret	smartlink/qqlink-lib-mipsel/case/ipcamera/alarm.c	/^void on_send_alarm_msg_ret(const unsigned int cookie, int err_code)$/;"	f	signature:(const unsigned int cookie, int err_code)
+on_send_cc_data_point_ret	smartlink/qqlink-lib-mipsel/include/TXOldInf.h	/^typedef void (*on_send_cc_data_point_ret)(unsigned int cookie, unsigned long long to_client, int err_code);$/;"	t
+on_send_notify_msg_ret	smartlink/qqlink-lib-mipsel/include/TXMsg.h	/^typedef void (*on_send_notify_msg_ret)(unsigned int cookie, int err_code);$/;"	t
+on_send_structuring_msg_ret	smartlink/qqlink-lib-mipsel/include/TXMsg.h	/^    void (*on_send_structuring_msg_ret)(const unsigned int cookie, int err_code);$/;"	m	struct:_tx_send_msg_notify	access:public
+on_send_text_msg_ret	smartlink/qqlink-lib-mipsel/include/TXMsg.h	/^typedef void (*on_send_text_msg_ret)(unsigned int cookie, int err_code);$/;"	t
+on_set_bitrate	smartlink/qqlink-lib-mipsel/include/TXAudioVideo.h	/^    bool (*on_set_bitrate)(int bit_rate);$/;"	m	struct:_tx_av_callback	access:public
+on_set_definition	smartlink/qqlink-lib-mipsel/include/TXIPCAM.h	/^ int (*on_set_definition)(int definition, char *cur_definition, int cur_definition_length);$/;"	m	struct:_tx_ipcamera_notify	access:public
+on_start_camera	smartlink/qqlink-lib-mipsel/include/TXAudioVideo.h	/^    bool (*on_start_camera)();$/;"	m	struct:_tx_av_callback	access:public
+on_start_mic	smartlink/qqlink-lib-mipsel/include/TXAudioVideo.h	/^    bool (*on_start_mic)();$/;"	m	struct:_tx_av_callback	access:public
+on_stop_camera	smartlink/qqlink-lib-mipsel/include/TXAudioVideo.h	/^    bool (*on_stop_camera)();$/;"	m	struct:_tx_av_callback	access:public
+on_stop_mic	smartlink/qqlink-lib-mipsel/include/TXAudioVideo.h	/^    bool (*on_stop_mic)();$/;"	m	struct:_tx_av_callback	access:public
+on_transfer_complete	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^    void (*on_transfer_complete)(unsigned long long transfer_cookie, int err_code, tx_file_transfer_info* tran_info);$/;"	m	struct:tag_tx_file_transfer_notify	access:public
+on_transfer_progress	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^    void (*on_transfer_progress)(unsigned long long transfer_cookie, unsigned long long transfer_progress, unsigned long long max_transfer_progress);$/;"	m	struct:tag_tx_file_transfer_notify	access:public
+on_update_confirm	smartlink/qqlink-lib-mipsel/include/TXOTA.h	/^ void (*on_update_confirm)();$/;"	m	struct:_tx_ota_notify	access:public
+on_wifi_sync_notify	smartlink/qqlink.c	/^void on_wifi_sync_notify(tx_wifi_sync_param *pwifi_sync_param, void *puserdata)$/;"	f	signature:(tx_wifi_sync_param *pwifi_sync_param, void *puserdata)
+online_reset	include/ssv_cfg.h	/^    u32 online_reset;$/;"	m	struct:ssv6xxx_cfg	access:public
+ontransfercomplete	smartlink/qqlink-lib-mipsel/demo_filetransfer.c	/^void ontransfercomplete(unsigned long long transfer_cookie, int err_code, tx_file_transfer_info tran_info) {$/;"	f	signature:(unsigned long long transfer_cookie, int err_code, tx_file_transfer_info tran_info)
+oob_irq	platforms/rk3126-generic-wlan.c	/^unsigned int oob_irq = 0;$/;"	v
+openFile	smac/efuse.c	/^struct file *openFile(char *path,int flag,int mode)$/;"	f	signature:(char *path,int flag,int mode)
+open_appid	smartlink/qqlink-lib-mipsel/include/TXOldInf.h	/^    unsigned int open_appid;$/;"	m	struct:tag_tx_ccmsg_inst_info	access:public
+ops	hwif/hwif.h	/^    struct ssv6xxx_hwif_ops *ops;$/;"	m	struct:ssv6xxx_platform_data	typeref:struct:ssv6xxx_platform_data::ssv6xxx_hwif_ops	access:public
+ops	smac/sec.h	/^    struct ssv_crypto_ops *ops;$/;"	m	struct:ssv_crypto_data	typeref:struct:ssv_crypto_data::ssv_crypto_ops	access:public
+os_platform	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    char * os_platform;$/;"	m	struct:_tx_device_info	access:public
+other_try_count	smac/ssv_rc_common.h	/^    int other_try_count;$/;"	m	struct:ssv62xx_ht	access:public
+out_data	bridge/sdiobridge_pub.h	/^    u8* out_data;$/;"	m	struct:ssv_sdiobridge_cmd	access:public
+out_data	hci_wrapper/ssv_huw.h	/^    u8* out_data;$/;"	m	struct:ssv_huw_cmd	access:public
+out_data_len	bridge/sdiobridge_pub.h	/^    __u32 out_data_len;$/;"	m	struct:ssv_sdiobridge_cmd	access:public
+out_data_len	hci_wrapper/ssv_huw.h	/^    __u32 out_data_len;$/;"	m	struct:ssv_huw_cmd	access:public
+overhead	smac/ssv_rc_common.h	/^    unsigned int overhead;$/;"	m	struct:ssv62xx_ht	access:public
+overhead	smac/ssv_rc_minstrel_ht.h	/^ unsigned int overhead;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+overhead_rtscts	smac/ssv_rc_common.h	/^    unsigned int overhead_rtscts;$/;"	m	struct:ssv62xx_ht	access:public
+overhead_rtscts	smac/ssv_rc_minstrel_ht.h	/^ unsigned int overhead_rtscts;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+p2pStatus	ssvdevice/ssvdevice.c	/^static char *p2pStatus = "0";$/;"	v	file:
+p2p_attr_id	smac/p2p.c	/^enum p2p_attr_id {$/;"	g	file:
+p2p_config_lock	smac/p2p.h	/^    spinlock_t p2p_config_lock;$/;"	m	struct:ssv_p2p_noa	access:public
+p2p_find_noa	smac/p2p.c	/^bool p2p_find_noa(const u8 *ies, struct ssv6xxx_p2p_noa_attribute *noa_attr)$/;"	f	signature:(const u8 *ies, struct ssv6xxx_p2p_noa_attribute *noa_attr)
+p2p_get_attribute_noa	smac/p2p.c	/^bool p2p_get_attribute_noa(const u8 *ies, u32 oui_type, struct ssv6xxx_p2p_noa_attribute *noa_attr)$/;"	f	signature:(const u8 *ies, u32 oui_type, struct ssv6xxx_p2p_noa_attribute *noa_attr)
+p2p_noa	smac/dev.h	/^    struct ssv_p2p_noa p2p_noa;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::ssv_p2p_noa	access:public
+p2p_noa_index	smac/p2p.h	/^    s16 p2p_noa_index;$/;"	m	struct:ssv_p2p_noa_detect	access:public
+p2p_status	smac/dev.h	/^    u8 p2p_status;$/;"	m	struct:ssv_softc	access:public
+p_AMPDU_BLOCKACK	smac/ampdu.h	/^} AMPDU_BLOCKACK, *p_AMPDU_BLOCKACK;$/;"	t	typeref:struct:AMPDU_BLOCKACK_st
+p_AMPDU_DELIMITER	smac/ampdu.h	/^} AMPDU_DELIMITER, *p_AMPDU_DELIMITER;$/;"	t	typeref:struct:AMPDU_DELIMITER_st
+p_AMPDU_TID	smac/ampdu.h	/^} AMPDU_TID, *p_AMPDU_TID;$/;"	t	typeref:struct:AMPDU_TID_st
+p_SKB_info	smac/ssv_skb.h	/^typedef struct SKB_info_st *p_SKB_info;$/;"	t	typeref:struct:SKB_info_st
+p_ch_cfg	smac/dev.h	/^    struct ssv6xxx_ch_cfg *p_ch_cfg;$/;"	m	struct:ssv_hw	typeref:struct:ssv_hw::ssv6xxx_ch_cfg	access:public
+p_wlan_data	hwif/sdio/sdio.c	/^    struct ssv6xxx_platform_data *p_wlan_data;$/;"	m	struct:ssv6xxx_sdio_glue	typeref:struct:ssv6xxx_sdio_glue::ssv6xxx_platform_data	file:	access:public
+p_wlan_data	hwif/usb/usb.c	/^    struct ssv6xxx_platform_data *p_wlan_data;$/;"	m	struct:ssv6xxx_usb_glue	typeref:struct:ssv6xxx_usb_glue::ssv6xxx_platform_data	file:	access:public
+packet_count	smac/ssv_rc_minstrel.h	/^ u64 packet_count;$/;"	m	struct:ssv_minstrel_sta_info	access:public
+packet_size	hwif/usb/usb.h	/^ u16 packet_size;$/;"	m	struct:ssv6xxx_cmd_endpoint	access:public
+packet_size	hwif/usb/usb.h	/^ u16 packet_size;$/;"	m	struct:ssv6xxx_rx_endpoint	access:public
+packet_size	hwif/usb/usb.h	/^ u16 packet_size;$/;"	m	struct:ssv6xxx_tx_endpoint	access:public
+padding1	bridge/sdiobridge_pub.h	/^    __u32 padding1;$/;"	m	struct:ssv_sdiobridge_cmd	access:public
+padding1	hci_wrapper/ssv_huw.h	/^    __u32 padding1;$/;"	m	struct:ssv_huw_cmd	access:public
+padding2	bridge/sdiobridge_pub.h	/^        __u32 padding2;$/;"	m	struct:ssv_sdiobridge_cmd	access:public
+padding2	hci_wrapper/ssv_huw.h	/^        __u32 padding2;$/;"	m	struct:ssv_huw_cmd	access:public
+padpd	smac/dev.h	/^    u16 padpd;$/;"	m	struct:ssv_flash_config	access:public
+padpd	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 padpd;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+padpd_am_addr_table	smac/hal/ssv6006c/turismo_common.c	/^const u32 padpd_am_addr_table[5][13]=$/;"	v
+padpd_pm_addr_table	smac/hal/ssv6006c/turismo_common.c	/^const u32 padpd_pm_addr_table[5][13]=$/;"	v
+padpd_table	smac/hal/ssv6006c/turismo_common.h	/^struct padpd_table{$/;"	s
+padpd_table::addr	smac/hal/ssv6006c/turismo_common.h	/^    u32 addr;$/;"	m	struct:padpd_table	access:public
+padpd_table::mask0	smac/hal/ssv6006c/turismo_common.h	/^    u32 mask0;$/;"	m	struct:padpd_table	access:public
+padpd_table::mask1	smac/hal/ssv6006c/turismo_common.h	/^    u32 mask1;$/;"	m	struct:padpd_table	access:public
+page_count	smac/dev.h	/^    u8 *page_count;$/;"	m	struct:ssv_hw	access:public
+pair	smac/drv_comm.h	/^ struct ssv6xxx_hw_key pair;$/;"	m	struct:ssv6xxx_hw_sta_key	typeref:struct:ssv6xxx_hw_sta_key::ssv6xxx_hw_key	access:public
+pair	smac/hal/ssv6006c/ssv6006_mac.h	/^    struct ssv6006_hw_key pair;$/;"	m	struct:ssv6006_hw_sta_key	typeref:struct:ssv6006_hw_sta_key::ssv6006_hw_key	access:public
+pair_cipher	smac/dev.h	/^    u32 pair_cipher;$/;"	m	struct:ssv_vif_priv_data	access:public
+pair_cipher_type	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 pair_cipher_type;$/;"	m	struct:ssv6006_hw_sta_key	access:public
+pair_key_idx	smac/drv_comm.h	/^ u8 pair_key_idx:4;$/;"	m	struct:ssv6xxx_hw_sta_key	access:public
+pair_key_idx	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 pair_key_idx;$/;"	m	struct:ssv6006_hw_sta_key	access:public
+pairwise_wpa_use_hw_cipher	smac/dev.h	/^    bool (*pairwise_wpa_use_hw_cipher)(struct ssv_softc *sc,$/;"	m	struct:ssv_hal_ops	access:public
+parseMac	smac/efuse.c	/^void parseMac(char* mac, u_int8_t addr[])$/;"	f	signature:(char* mac, u_int8_t addr[])
+parser_efuse	smac/efuse.c	/^u16 parser_efuse(struct ssv_hw *sh, u8 *pbuf, u8 *mac_addr, u8 *new_mac_addr, struct efuse_map *efuse_tbl)$/;"	f	signature:(struct ssv_hw *sh, u8 *pbuf, u8 *mac_addr, u8 *new_mac_addr, struct efuse_map *efuse_tbl)
+parser_efuse	smac/efuse.h	/^u16 parser_efuse(struct ssv_hw *sh, u8 *pbuf, u8 *mac_addr, u8 *new_mac_addr, struct efuse_map *efuse_tbl);$/;"	p	signature:(struct ssv_hw *sh, u8 *pbuf, u8 *mac_addr, u8 *new_mac_addr, struct efuse_map *efuse_tbl)
+password	include/ssv6xxx_common.h	/^    u8 password[64];$/;"	m	struct:ssv6xxx_si_cfg	access:public
+password_len	include/ssv6xxx_common.h	/^    s32 password_len;$/;"	m	struct:ssv6xxx_si_cfg	access:public
+paused	hci/ssv_hci.h	/^    bool paused;$/;"	m	struct:ssv_hw_txq	access:public
+paused	smac/dev.h	/^    volatile int paused;$/;"	m	struct:ssv_encrypt_task_list	access:public
+payload	hwif/usb/usb.h	/^ union ssv6xxx_payload payload;$/;"	m	struct:ssv6xxx_cmd_hdr	typeref:union:ssv6xxx_cmd_hdr::ssv6xxx_payload	access:public
+payload_offset	include/ssv6200_common.h	/^    u32 payload_offset:8;$/;"	m	struct:ssv6200_rx_desc	access:public
+payload_offset	include/ssv6200_common.h	/^    u32 payload_offset:8;$/;"	m	struct:ssv6200_tx_desc	access:public
+payload_offset_obsolete	smac/hal/ssv6006c/turismo_common.h	/^    u32 payload_offset_obsolete:8;$/;"	m	struct:ssv6006_tx_desc	access:public
+percentage	smac/ssv_rc.c	/^int percentage = 0;$/;"	v
+percentageCounter	smac/ssv_rc.c	/^int percentageCounter = 0;$/;"	v
+perfect_tx_time	smac/ssv_rc_common.h	/^ u16 perfect_tx_time;$/;"	m	struct:rc_pid_rateinfo	access:public
+perfect_tx_time	smac/ssv_rc_minstrel.h	/^ unsigned int perfect_tx_time;$/;"	m	struct:ssv_minstrel_rate	access:public
+phy_enable	smac/dev.h	/^    void (*phy_enable)(struct ssv_hw *sh, bool val);$/;"	m	struct:ssv_hal_ops	access:public
+phy_info_6051z	smac/dev_tbl.h	/^static u32 phy_info_6051z[] =$/;"	v
+phy_info_tbl	smac/dev_tbl.h	/^u32 phy_info_tbl[] =$/;"	v
+phy_info_tbl_size	smac/dev_tbl.h	/^size_t phy_info_tbl_size = sizeof(phy_info_tbl);$/;"	v
+phy_mode	smac/dev.h	/^    u8 phy_mode;$/;"	m	struct:rx_stats	access:public
+phy_mode	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 phy_mode:2;$/;"	m	struct:ssv6006_rc_idx	access:public
+phy_rate	smac/hal/ssv6006c/turismo_common.h	/^    u32 phy_rate:8;$/;"	m	struct:ssv6006_rxphy_info	access:public
+phy_setting	include/ssv6200_configuration.h	/^ssv_cabrio_reg phy_setting[]={$/;"	v
+phy_tbl_size	include/ssv6xxx_common.h	/^    u32 phy_tbl_size;$/;"	m	struct:ssv6xxx_iqk_cfg	access:public
+phy_type	smac/ssv_rc_common.h	/^    u16 phy_type;$/;"	m	struct:ssv_rc_rate	access:public
+pide_frame_duration	smac/ssv_rc.c	/^int pide_frame_duration(size_t len,$/;"	f	signature:(size_t len, int rate, int short_preamble, int flags)
+pide_frame_duration	smac/ssv_rc.h	/^int pide_frame_duration(size_t len, int rate, int short_preamble, int flags);$/;"	p	signature:(size_t len, int rate, int short_preamble, int flags)
+pinfo	smac/ssv_rc_common.h	/^    struct rc_pid_info pinfo;$/;"	m	struct:ssv_sta_rc_info	typeref:struct:ssv_sta_rc_info::rc_pid_info	access:public
+pkt1614	smac/hal/ssv6006c/turismo_common.c	/^ const u8 pkt1614[] ={$/;"	v
+pkt_array_lock	smac/ampdu.h	/^    spinlock_t pkt_array_lock;$/;"	m	struct:AMPDU_TID_st	access:public
+pkt_no	smac/ssv_rc_minstrel_ht.h	/^ int pkt_no;$/;"	m	struct:ssv_minstrel_ampdu_rate_rpt	access:public
+platform	smartlink/qqlink-lib-mipsel/include/TXOldInf.h	/^    unsigned int platform;$/;"	m	struct:tag_tx_ccmsg_inst_info	access:public
+platform_dev	smac/dev.h	/^    struct platform_device *platform_dev;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::platform_device	access:public
+platform_wifi_power_off	platforms/atm7039-action-generic-wlan.c	/^void platform_wifi_power_off(void)$/;"	f	signature:(void)
+platform_wifi_power_on	platforms/atm7039-action-generic-wlan.c	/^int platform_wifi_power_on(void)$/;"	f	signature:(void)
+plen	hwif/usb/usb.h	/^ u8 plen;$/;"	m	struct:ssv6xxx_cmd_hdr	access:public
+pll_chk	smac/dev.h	/^    void (*pll_chk)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+pm	smac/dev.h	/^    u32 pm[MAX_PADPD_TONE\/2];$/;"	m	struct:ssv6006dpd	access:public
+pm	smac/hal/ssv6006c/turismo_common.h	/^    u32 pm[MAX_PADPD_TONE\/2];$/;"	m	struct:ssv6006dpd	access:public
+pm_mask	smac/hal/ssv6006c/turismo_common.c	/^const u32 pm_mask[2] = {0xffffe000,0xe000ffff};$/;"	v
+pm_param	hwif/hwif.h	/^ void *pm_param;$/;"	m	struct:ssv6xxx_platform_data	access:public
+pmsk_key	smac/sec_wpi.c	/^ u8 pmsk_key[3][WAPI_PN_LEN];$/;"	m	struct:lib80211_wpi_data	file:	access:public
+pmu_awake	smac/dev.h	/^ void (*pmu_awake)(struct ssv_softc *sc);$/;"	m	struct:ssv_hal_ops	access:public
+pmu_wakeup	hwif/hwif.h	/^    void (*pmu_wakeup)(struct device *child);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+pn_key	smac/sec_wpi.c	/^ u8 pn_key[WAPI_PN_LEN];$/;"	m	struct:lib80211_wpi_data	file:	access:public
+pre_11b_cca_1	smac/dev.h	/^    u32 pre_11b_cca_1;$/;"	m	struct:ssv_softc	access:public
+pre_11b_cca_control	smac/dev.h	/^    u32 pre_11b_cca_control;$/;"	m	struct:ssv_softc	access:public
+pre_11b_rx_abbctune	smac/dev.h	/^    u32 pre_11b_rx_abbctune;$/;"	m	struct:ssv_softc	access:public
+pre_rx_pn	smac/sec_ccmp.c	/^    u8 pre_rx_pn[CCMP_PN_LEN];$/;"	m	struct:lib80211_ccmp_data	file:	access:public
+preamble	include/ssv6200_common.h	/^    u32 preamble:1;$/;"	m	struct:ssv6200_rxphy_info	access:public
+prepare_mask	smac/sec_ccmp.c	/^int prepare_mask = 0x0b0e0e0f;$/;"	v
+preprocess_q	smac/dev.h	/^    struct sk_buff_head preprocess_q;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::sk_buff_head	access:public
+prev_isr_jiffes	hci/hctrl.h	/^    unsigned long prev_isr_jiffes;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+prev_rx_isr_jiffes	hci/hctrl.h	/^    unsigned long prev_rx_isr_jiffes;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+prev_sample	smac/ssv_rc_minstrel.h	/^ bool prev_sample;$/;"	m	struct:ssv_minstrel_sta_info	access:public
+primary_edca_mib	smac/dev.h	/^    int primary_edca_mib;$/;"	m	struct:ssv_softc	access:public
+print_irq_count	ssvdevice/ssv_cmd.c	/^void print_irq_count(struct ssv6xxx_hci_ctrl *hci_ctrl)$/;"	f	signature:(struct ssv6xxx_hci_ctrl *hci_ctrl)
+print_isr_info	ssvdevice/ssv_cmd.c	/^void print_isr_info(struct ssv_cmd_data *cmd_data, struct ssv6xxx_hci_ctrl *hci_ctrl)$/;"	f	signature:(struct ssv_cmd_data *cmd_data, struct ssv6xxx_hci_ctrl *hci_ctrl)
+print_null	smac/hal/ssv6006c/ssv6006_priv.h	/^static void inline print_null(const char *fmt, ...)$/;"	f	signature:(const char *fmt, ...)
+print_stats	smac/sec.h	/^ char *(*print_stats) (char *p, void *priv);$/;"	m	struct:ssv_crypto_ops	access:public
+printf	smartlink/airkiss-lib/airkiss.h	/^ airkiss_printf_fn printf;$/;"	m	struct:__anon23	access:public
+printf	smartlink/airkiss-lib/mipsel/airkiss.h	/^ airkiss_printf_fn printf;$/;"	m	struct:__anon17	access:public
+printf	smartlink/airkiss-lib/x64/airkiss.h	/^ airkiss_printf_fn printf;$/;"	m	struct:__anon29	access:public
+printf_null	smac/hal/ssv6006c/turismo_common.h	/^extern int printf_null(const char *fmt, ...);$/;"	p	signature:(const char *fmt, ...)
+printf_null	smac/hal/ssv6006c/turismo_common.h	/^extern void printf_null(const char *fmt, ...);$/;"	p	signature:(const char *fmt, ...)
+priv	hci_wrapper/ssv_huw.c	/^    struct ssv6xxx_platform_data *priv;$/;"	m	struct:ssv_huw_dev	typeref:struct:ssv_huw_dev::ssv6xxx_platform_data	file:	access:public
+priv	smac/dev.h	/^    struct ssv6xxx_platform_data *priv;$/;"	m	struct:ssv_hw	typeref:struct:ssv_hw::ssv6xxx_platform_data	access:public
+priv	smac/sec.h	/^    void *priv;$/;"	m	struct:ssv_crypto_data	access:public
+private_AES_set_decrypt_key	crypto/aes-armv4.S	/^private_AES_set_decrypt_key:$/;"	l
+private_AES_set_decrypt_key	crypto/aes_glue.c	/^asmlinkage int private_AES_set_decrypt_key(const unsigned char *userKey, const int bits, AES_KEY *key);$/;"	p	file:	signature:(const unsigned char *userKey, const int bits, AES_KEY *key)
+private_AES_set_encrypt_key	crypto/aes-armv4.S	/^private_AES_set_encrypt_key:$/;"	l
+private_AES_set_encrypt_key	crypto/aes_glue.c	/^asmlinkage int private_AES_set_encrypt_key(const unsigned char *userKey, const int bits, AES_KEY *key);$/;"	p	file:	signature:(const unsigned char *userKey, const int bits, AES_KEY *key)
+prn_aggr_dbg	smac/dev.h	100;"	d
+prn_aggr_dbg	smac/dev.h	101;"	d
+prn_aggr_dbg	smac/dev.h	95;"	d
+prn_aggr_err	smac/dev.h	104;"	d
+prn_aggr_err	smac/dev.h	109;"	d
+probability	smac/ssv_rc_common.h	/^    unsigned int cur_prob, probability;$/;"	m	struct:minstrel_rate_stats	access:public
+probability	smac/ssv_rc_minstrel.h	/^ u32 probability;$/;"	m	struct:ssv_minstrel_rate	access:public
+probability	smac/ssv_rc_minstrel_ht.h	/^ unsigned int cur_prob, probability;$/;"	m	struct:ssv_minstrel_ht_rate_stats	access:public
+probe_cnt	smac/ssv_rc_common.h	/^    u8 probe_cnt;$/;"	m	struct:rc_pid_sta_info	access:public
+probe_report_flag	smac/ssv_rc_common.h	/^    u8 probe_report_flag;$/;"	m	struct:rc_pid_sta_info	access:public
+probe_wating_times	smac/ssv_rc_common.h	/^    u8 probe_wating_times;$/;"	m	struct:rc_pid_sta_info	access:public
+proc_dev_entry	smac/dev.h	/^ struct proc_dir_entry *proc_dev_entry;$/;"	m	struct:ssv_cmd_data	typeref:struct:ssv_cmd_data::proc_dir_entry	access:public
+product_id	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    int product_id;$/;"	m	struct:_tx_device_info	access:public
+product_version	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    int product_version;$/;"	m	struct:_tx_device_info	access:public
+productid	smartlink/qqlink-lib-mipsel/include/TXOldInf.h	/^    unsigned int productid;$/;"	m	struct:tag_tx_ccmsg_inst_info	access:public
+property	hwif/hwif.h	/^    int (*property)(struct device *child);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+prt_buff	smac/ampdu.c	/^    char *prt_buff;$/;"	m	struct:mib_dump_data	file:	access:public
+prt_len	smac/ampdu.c	/^    size_t prt_len;$/;"	m	struct:mib_dump_data	file:	access:public
+ps_aid	smac/dev.h	/^    u16 ps_aid;$/;"	m	struct:ssv_softc	access:public
+ps_state_lock	smac/dev.h	/^    spinlock_t ps_state_lock;$/;"	m	struct:ssv_softc	access:public
+ps_status	smac/dev.h	/^    int ps_status;$/;"	m	struct:ssv_softc	access:public
+psm	include/ssv6200_common.h	/^    u32 psm:1;$/;"	m	struct:ssv6200_rx_desc	access:public
+psm	smac/hal/ssv6006c/turismo_common.h	/^    u32 psm:1;$/;"	m	struct:ssv6006_rx_desc	access:public
+pubf_addr	smac/dev.h	/^ u32 pubf_addr;$/;"	m	struct:ssv6xxx_beacon_info	access:public
+put_mic_space_for_hw_ccmp_encrypt	smac/dev.h	/^    bool (*put_mic_space_for_hw_ccmp_encrypt) (struct ssv_softc *sc, struct sk_buff *skb);$/;"	m	struct:ssv_hal_ops	access:public
+pwd	smartlink/airkiss-lib/airkiss.h	/^ char* pwd;$/;"	m	struct:__anon25	access:public
+pwd	smartlink/airkiss-lib/mipsel/airkiss.h	/^ char* pwd;$/;"	m	struct:__anon19	access:public
+pwd	smartlink/airkiss-lib/x64/airkiss.h	/^ char* pwd;$/;"	m	struct:__anon31	access:public
+pwd_length	smartlink/airkiss-lib/airkiss.h	/^ unsigned char pwd_length;$/;"	m	struct:__anon25	access:public
+pwd_length	smartlink/airkiss-lib/mipsel/airkiss.h	/^ unsigned char pwd_length;$/;"	m	struct:__anon19	access:public
+pwd_length	smartlink/airkiss-lib/x64/airkiss.h	/^ unsigned char pwd_length;$/;"	m	struct:__anon31	access:public
+pwr_mode	smac/dev.h	/^    bool pwr_mode;$/;"	m	struct:ssv6006_padpd	access:public
+pwr_mode	smac/hal/ssv6006c/turismo_common.h	/^    bool pwr_mode;$/;"	m	struct:ssv6006_padpd	access:public
+qhead	hci/ssv_hci.h	/^    struct sk_buff_head qhead;$/;"	m	struct:ssv_hw_txq	typeref:struct:ssv_hw_txq::sk_buff_head	access:public
+qhead	smac/dev.h	/^    struct sk_buff_head qhead;$/;"	m	struct:ssv6xxx_bcast_txq	typeref:struct:ssv6xxx_bcast_txq::sk_buff_head	access:public
+qos	include/ssv6200_common.h	/^    u32 qos:1;$/;"	m	struct:ssv6200_rx_desc	access:public
+qos	include/ssv6200_common.h	/^    u32 qos:1;$/;"	m	struct:ssv6200_tx_desc	access:public
+qos	smac/hal/ssv6006c/turismo_common.h	/^    u32 qos:1;$/;"	m	struct:ssv6006_rx_desc	access:public
+qos	smac/hal/ssv6006c/turismo_common.h	/^    u32 qos:1;$/;"	m	struct:ssv6006_tx_desc	access:public
+queue	include/ssv_data_struct.h	/^    struct list_head queue;$/;"	m	struct:ssv6xxx_queue	typeref:struct:ssv6xxx_queue::list_head	access:public
+queue_block_cnt	smac/ap.c	/^static int queue_block_cnt = 0;$/;"	v	file:
+queue_status_fops	smac/ssv6xxx_debugfs.c	/^static const struct file_operations queue_status_fops$/;"	v	typeref:struct:file_operations	file:
+queue_status_open	smac/ssv6xxx_debugfs.c	/^static int queue_status_open (struct inode *inode, struct file *file)$/;"	f	file:	signature:(struct inode *inode, struct file *file)
+queue_status_read	smac/ssv6xxx_debugfs.c	/^static ssize_t queue_status_read (struct file *file,$/;"	f	file:	signature:(struct file *file, char __user *user_buf, size_t count, loff_t *ppos)
+r_calbration_result	include/ssv_cfg.h	/^    u32 r_calbration_result;$/;"	m	struct:ssv6xxx_cfg	access:public
+ra	smac/ampdu.h	/^ unsigned char ra[6];$/;"	m	struct:ssv_bar	access:public
+ra_addr	smac/ampdu.h	/^ u8 ra_addr[ETH_ALEN];$/;"	m	struct:AMPDU_BLOCKACK_st	access:public
+random	smartlink/airkiss-lib/airkiss.h	/^ unsigned char random;$/;"	m	struct:__anon25	access:public
+random	smartlink/airkiss-lib/mipsel/airkiss.h	/^ unsigned char random;$/;"	m	struct:__anon19	access:public
+random	smartlink/airkiss-lib/x64/airkiss.h	/^ unsigned char random;$/;"	m	struct:__anon31	access:public
+rate	include/ssv6200_common.h	/^    u32 rate:7;$/;"	m	struct:ssv6200_rxphy_info	access:public
+rateControlGetRate	smac/ssv_rc.c	/^static void rateControlGetRate(u8 rateIndex, char * pointer)$/;"	f	file:	signature:(u8 rateIndex, char * pointer)
+rate_avg	smac/ssv_rc_minstrel.h	/^ unsigned int rate_avg;$/;"	m	struct:ssv_minstrel_sta_info	access:public
+rate_control_ht_sample	smac/ssv_ht_rc.c	/^static void rate_control_ht_sample(struct ssv62xx_ht *mi,struct ssv_sta_rc_info *rc_sta)$/;"	f	file:	signature:(struct ssv62xx_ht *mi,struct ssv_sta_rc_info *rc_sta)
+rate_control_pid_adjust_rate	smac/ssv_rc.c	/^static void rate_control_pid_adjust_rate(struct ssv_sta_rc_info *rc_sta,$/;"	f	file:	signature:(struct ssv_sta_rc_info *rc_sta, struct rc_pid_sta_info *spinfo, int adj,struct rc_pid_rateinfo *rinfo)
+rate_control_pid_normalize	smac/ssv_rc.c	/^static void rate_control_pid_normalize(struct rc_pid_info *pinfo, int l)$/;"	f	file:	signature:(struct rc_pid_info *pinfo, int l)
+rate_control_pid_sample	smac/ssv_rc.c	/^static void rate_control_pid_sample(struct ssv_rate_ctrl* ssv_rc,struct rc_pid_info *pinfo,$/;"	f	file:	signature:(struct ssv_rate_ctrl* ssv_rc,struct rc_pid_info *pinfo, struct ssv_sta_rc_info *rc_sta, struct rc_pid_sta_info *spinfo)
+rate_delta	smac/dev.h	/^    u8 rate_delta[13];$/;"	m	struct:ssv_flash_config	access:public
+rate_delta	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 rate_delta[13];$/;"	m	struct:ssv6006_flash_layout_table	access:public
+rate_idx	include/ssv6200_common.h	/^    u32 rate_idx:6;$/;"	m	struct:ssv6200_rx_desc	access:public
+rate_idx	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 rate_idx:3;$/;"	m	struct:ssv6006_rc_idx	access:public
+rate_kbps	smac/ssv_rc_common.h	/^    u32 rate_kbps;$/;"	m	struct:ssv_rc_rate	access:public
+rate_report_handler	smac/dev.h	/^ void (*rate_report_handler)(struct ssv_softc *sc, struct sk_buff *skb, bool *no_ba_result);$/;"	m	struct:ssv_hal_ops	access:public
+rate_rpt	smac/ssv_rc_minstrel_ht.h	/^ struct ssv_minstrel_ht_rpt rate_rpt[4];$/;"	m	struct:ssv_minstrel_ampdu_rate_rpt	typeref:struct:ssv_minstrel_ampdu_rate_rpt::ssv_minstrel_ht_rpt	access:public
+rate_rpt_mode	smac/hal/ssv6006c/turismo_common.h	/^    u32 rate_rpt_mode:2;$/;"	m	struct:ssv6006_tx_desc	access:public
+rate_table_1	include/ssv_cfg.h	/^    u32 rate_table_1;$/;"	m	struct:ssv6xxx_cfg	access:public
+rate_table_2	include/ssv_cfg.h	/^    u32 rate_table_2;$/;"	m	struct:ssv6xxx_cfg	access:public
+rateidx1_data_duration	smac/hal/ssv6006c/turismo_common.h	/^    u32 rateidx1_data_duration:16;$/;"	m	struct:ssv6006_tx_desc	access:public
+rateidx2_data_duration	smac/hal/ssv6006c/turismo_common.h	/^    u32 rateidx2_data_duration:16;$/;"	m	struct:ssv6006_tx_desc	access:public
+rateidx3_data_duration	smac/hal/ssv6006c/turismo_common.h	/^    u32 rateidx3_data_duration:16;$/;"	m	struct:ssv6006_tx_desc	access:public
+ratelist	smac/ssv_rc_minstrel.h	/^ struct ssv_minstrel_rate *ratelist;$/;"	m	struct:ssv_minstrel_sta_priv	typeref:struct:ssv_minstrel_sta_priv::ssv_minstrel_rate	access:public
+rates	include/ssv6200_common.h	/^    struct ssv62xx_tx_rate rates[SSV62XX_TX_MAX_RATES];$/;"	m	struct:firmware_rate_control_report_data	typeref:struct:firmware_rate_control_report_data::ssv62xx_tx_rate	access:public
+rates	smac/ssv_rc_common.h	/^    struct minstrel_rate_stats rates[MCS_GROUP_RATES];$/;"	m	struct:minstrel_mcs_group_data	typeref:struct:minstrel_mcs_group_data::minstrel_rate_stats	access:public
+rates	smac/ssv_rc_minstrel_ht.h	/^ struct ssv_minstrel_ht_rate_stats rates[MCS_GROUP_RATES];$/;"	m	struct:ssv_minstrel_ht_mcs_group_data	typeref:struct:ssv_minstrel_ht_mcs_group_data::ssv_minstrel_ht_rate_stats	access:public
+rates	smac/ssv_skb.h	/^    struct fw_rc_retry_params rates[SSV62XX_TX_MAX_RATES];$/;"	m	struct:SKB_info_st	typeref:struct:SKB_info_st::fw_rc_retry_params	access:public
+rates	smac/ssv_skb.h	/^    struct fw_rc_retry_params rates[SSV62XX_TX_MAX_RATES];$/;"	m	struct:ampdu_hdr_st	typeref:struct:ampdu_hdr_st::fw_rc_retry_params	access:public
+rc	smac/dev.h	/^    void *rc;$/;"	m	struct:ssv_softc	access:public
+rc_algorithm	smac/dev.h	/^ void (*rc_algorithm)(struct ssv_softc *sc);$/;"	m	struct:ssv_hal_ops	access:public
+rc_b_data_rate	smac/hal/ssv6006c/ssv6006_phy.c	/^static const u32 rc_b_data_rate[4] = {1000, 2000, 5500, 11000};$/;"	v	file:
+rc_flags	smac/ssv_rc_common.h	/^    u32 rc_flags;$/;"	m	struct:ssv_rc_rate	access:public
+rc_g_data_rate	smac/hal/ssv6006c/ssv6006_phy.c	/^static const u32 rc_g_data_rate[8] = {6000, 9000, 12000, 18000, 24000, 36000, 48000, 54000};$/;"	v	file:
+rc_ht40	include/ssv_cfg.h	/^    u32 rc_ht40;$/;"	m	struct:ssv6xxx_cfg	access:public
+rc_ht_sta_current_rate_is_cck	smac/dev.h	/^ bool (*rc_ht_sta_current_rate_is_cck)(struct ieee80211_sta *sta);$/;"	m	struct:ssv_hal_ops	access:public
+rc_ht_support_cck	include/ssv_cfg.h	/^    u32 rc_ht_support_cck;$/;"	m	struct:ssv6xxx_cfg	access:public
+rc_ht_update_rate	smac/dev.h	/^ s32 (*rc_ht_update_rate)(struct sk_buff *skb, struct ssv_softc *sc, struct fw_rc_retry_params *ar);$/;"	m	struct:ssv_hal_ops	access:public
+rc_idx	smac/dev.h	/^    int rc_idx;$/;"	m	struct:ssv_sta_priv_data	access:public
+rc_index	smac/ssv_rc_common.h	/^    u16 rc_index;$/;"	m	struct:minstrel_rate_stats	access:public
+rc_index	smac/ssv_rc_common.h	/^    u16 rc_index;$/;"	m	struct:rc_pid_rateinfo	access:public
+rc_info	smac/dev.h	/^ void *rc_info;$/;"	m	struct:ssv_sta_priv_data	access:public
+rc_legacy_bitrate_to_rate_desc	smac/dev.h	/^ void (*rc_legacy_bitrate_to_rate_desc)(int bitrate, u8 *drate);$/;"	m	struct:ssv_hal_ops	access:public
+rc_log	include/ssv_cfg.h	/^ u32 rc_log;$/;"	m	struct:ssv6xxx_cfg	access:public
+rc_long_short	include/ssv_cfg.h	/^    u32 rc_long_short;$/;"	m	struct:ssv6xxx_cfg	access:public
+rc_mac80211_rate_idx	smac/dev.h	/^    void (*rc_mac80211_rate_idx)(struct ssv_softc *sc,$/;"	m	struct:ssv_hal_ops	access:public
+rc_mf	include/ssv_cfg.h	/^    u32 rc_mf;$/;"	m	struct:ssv6xxx_cfg	access:public
+rc_n_ht20_lgi_data_rate	smac/hal/ssv6006c/ssv6006_phy.c	/^static const u32 rc_n_ht20_lgi_data_rate[8] = { 6500, 13000, 19500, 26000, 39000, 52000, 58500, 65000};$/;"	v	file:
+rc_n_ht20_sgi_data_rate	smac/hal/ssv6006c/ssv6006_phy.c	/^static const u32 rc_n_ht20_sgi_data_rate[8] = { 7200, 14400, 21700, 28900, 43300, 57800, 65000, 72200};$/;"	v	file:
+rc_n_ht40_lgi_data_rate	smac/hal/ssv6006c/ssv6006_phy.c	/^static const u32 rc_n_ht40_lgi_data_rate[8] = {13500, 27000, 40500, 54000, 81000, 108000, 121500, 135000};$/;"	v	file:
+rc_n_ht40_sgi_data_rate	smac/hal/ssv6006c/ssv6006_phy.c	/^static const u32 rc_n_ht40_sgi_data_rate[8] = {15000, 30000, 45000, 60000, 90000, 120000, 135000, 150000};$/;"	v	file:
+rc_num_rate	smac/ssv_rc_common.h	/^    u8 rc_num_rate;$/;"	m	struct:ssv_sta_rc_info	access:public
+rc_params	include/ssv6200_common.h	/^    struct fw_rc_retry_params rc_params[SSV62XX_TX_MAX_RATES];$/;"	m	struct:ssv6200_tx_desc	typeref:struct:ssv6200_tx_desc::fw_rc_retry_params	access:public
+rc_phy_mode	include/ssv_cfg.h	/^    u32 rc_phy_mode;$/;"	m	struct:ssv6xxx_cfg	access:public
+rc_pid_info	smac/ssv_rc_common.h	/^struct rc_pid_info {$/;"	s
+rc_pid_info::oldrate	smac/ssv_rc_common.h	/^ int oldrate;$/;"	m	struct:rc_pid_info	access:public
+rc_pid_info::rinfo	smac/ssv_rc_common.h	/^ struct rc_pid_rateinfo rinfo[12];$/;"	m	struct:rc_pid_info	typeref:struct:rc_pid_info::rc_pid_rateinfo	access:public
+rc_pid_info::target	smac/ssv_rc_common.h	/^ unsigned int target;$/;"	m	struct:rc_pid_info	access:public
+rc_pid_rateinfo	smac/ssv_rc_common.h	/^struct rc_pid_rateinfo {$/;"	s
+rc_pid_rateinfo::attempt	smac/ssv_rc_common.h	/^ u64 attempt;$/;"	m	struct:rc_pid_rateinfo	access:public
+rc_pid_rateinfo::diff	smac/ssv_rc_common.h	/^ s32 diff;$/;"	m	struct:rc_pid_rateinfo	access:public
+rc_pid_rateinfo::fail	smac/ssv_rc_common.h	/^ u64 fail;$/;"	m	struct:rc_pid_rateinfo	access:public
+rc_pid_rateinfo::index	smac/ssv_rc_common.h	/^    u16 index;$/;"	m	struct:rc_pid_rateinfo	access:public
+rc_pid_rateinfo::perfect_tx_time	smac/ssv_rc_common.h	/^ u16 perfect_tx_time;$/;"	m	struct:rc_pid_rateinfo	access:public
+rc_pid_rateinfo::rc_index	smac/ssv_rc_common.h	/^    u16 rc_index;$/;"	m	struct:rc_pid_rateinfo	access:public
+rc_pid_rateinfo::success	smac/ssv_rc_common.h	/^ u64 success;$/;"	m	struct:rc_pid_rateinfo	access:public
+rc_pid_rateinfo::this_attempt	smac/ssv_rc_common.h	/^ unsigned long this_attempt;$/;"	m	struct:rc_pid_rateinfo	access:public
+rc_pid_rateinfo::this_fail	smac/ssv_rc_common.h	/^ unsigned long this_fail;$/;"	m	struct:rc_pid_rateinfo	access:public
+rc_pid_rateinfo::this_success	smac/ssv_rc_common.h	/^ unsigned long this_success;$/;"	m	struct:rc_pid_rateinfo	access:public
+rc_pid_rateinfo::throughput	smac/ssv_rc_common.h	/^ u32 throughput;$/;"	m	struct:rc_pid_rateinfo	access:public
+rc_pid_sta_info	smac/ssv_rc_common.h	/^struct rc_pid_sta_info {$/;"	s
+rc_pid_sta_info::err_avg_sc	smac/ssv_rc_common.h	/^    s32 err_avg_sc;$/;"	m	struct:rc_pid_sta_info	access:public
+rc_pid_sta_info::feedback_probes	smac/ssv_rc_common.h	/^    u8 feedback_probes;$/;"	m	struct:rc_pid_sta_info	access:public
+rc_pid_sta_info::last_dlr	smac/ssv_rc_common.h	/^    int last_dlr;$/;"	m	struct:rc_pid_sta_info	access:public
+rc_pid_sta_info::last_pf	smac/ssv_rc_common.h	/^    u8 last_pf;$/;"	m	struct:rc_pid_sta_info	access:public
+rc_pid_sta_info::last_report	smac/ssv_rc_common.h	/^    unsigned long last_report;$/;"	m	struct:rc_pid_sta_info	access:public
+rc_pid_sta_info::last_sample	smac/ssv_rc_common.h	/^    unsigned long last_sample;$/;"	m	struct:rc_pid_sta_info	access:public
+rc_pid_sta_info::monitoring	smac/ssv_rc_common.h	/^    u8 monitoring;$/;"	m	struct:rc_pid_sta_info	access:public
+rc_pid_sta_info::oldrate	smac/ssv_rc_common.h	/^    u8 oldrate;$/;"	m	struct:rc_pid_sta_info	access:public
+rc_pid_sta_info::probe_cnt	smac/ssv_rc_common.h	/^    u8 probe_cnt;$/;"	m	struct:rc_pid_sta_info	access:public
+rc_pid_sta_info::probe_report_flag	smac/ssv_rc_common.h	/^    u8 probe_report_flag;$/;"	m	struct:rc_pid_sta_info	access:public
+rc_pid_sta_info::probe_wating_times	smac/ssv_rc_common.h	/^    u8 probe_wating_times;$/;"	m	struct:rc_pid_sta_info	access:public
+rc_pid_sta_info::real_hw_index	smac/ssv_rc_common.h	/^    u8 real_hw_index;$/;"	m	struct:rc_pid_sta_info	access:public
+rc_pid_sta_info::tmp_rate_idx	smac/ssv_rc_common.h	/^    u8 tmp_rate_idx;$/;"	m	struct:rc_pid_sta_info	access:public
+rc_pid_sta_info::tx_num_failed	smac/ssv_rc_common.h	/^    u16 tx_num_failed;$/;"	m	struct:rc_pid_sta_info	access:public
+rc_pid_sta_info::tx_num_xmit	smac/ssv_rc_common.h	/^    u16 tx_num_xmit;$/;"	m	struct:rc_pid_sta_info	access:public
+rc_pid_sta_info::txrate_idx	smac/ssv_rc_common.h	/^    int txrate_idx;$/;"	m	struct:rc_pid_sta_info	access:public
+rc_process_rate_report	smac/dev.h	/^ void (*rc_process_rate_report)(struct ssv_softc *sc, struct sk_buff *skb);$/;"	m	struct:ssv_hal_ops	access:public
+rc_rate_idx_set	include/ssv_cfg.h	/^    u32 rc_rate_idx_set;$/;"	m	struct:ssv6xxx_cfg	access:public
+rc_report_queue	smac/dev.h	/^    struct sk_buff_head rc_report_queue;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::sk_buff_head	access:public
+rc_report_sechedule	smac/dev.h	/^    u16 rc_report_sechedule;$/;"	m	struct:ssv_softc	access:public
+rc_report_work	smac/dev.h	/^    struct work_struct rc_report_work;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::work_struct	access:public
+rc_report_workqueue	smac/dev.h	/^    struct workqueue_struct *rc_report_workqueue;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::workqueue_struct	access:public
+rc_retry_set	include/ssv_cfg.h	/^    u32 rc_retry_set;$/;"	m	struct:ssv6xxx_cfg	access:public
+rc_rx_data_handler	smac/dev.h	/^ void (*rc_rx_data_handler)(struct ssv_softc *sc, struct sk_buff *skb, u32 rate_index);$/;"	m	struct:ssv_hal_ops	access:public
+rc_setting	include/ssv_cfg.h	/^    struct rc_setting rc_setting;$/;"	m	struct:ssv6xxx_cfg	typeref:struct:ssv6xxx_cfg::rc_setting	access:public
+rc_setting	include/ssv_cfg.h	/^struct rc_setting{$/;"	s
+rc_setting::aging_period	include/ssv_cfg.h	/^    u16 aging_period;$/;"	m	struct:rc_setting	access:public
+rc_setting::forbid	include/ssv_cfg.h	/^    u16 forbid;$/;"	m	struct:rc_setting	access:public
+rc_setting::forbid3	include/ssv_cfg.h	/^    u16 forbid3;$/;"	m	struct:rc_setting	access:public
+rc_setting::forbid4	include/ssv_cfg.h	/^    u16 forbid4;$/;"	m	struct:rc_setting	access:public
+rc_setting::forbid5	include/ssv_cfg.h	/^    u16 forbid5;$/;"	m	struct:rc_setting	access:public
+rc_setting::forbid6	include/ssv_cfg.h	/^    u16 forbid6;$/;"	m	struct:rc_setting	access:public
+rc_setting::force_sample_pr	include/ssv_cfg.h	/^    u16 force_sample_pr;$/;"	m	struct:rc_setting	access:public
+rc_setting::sample_pr_4	include/ssv_cfg.h	/^    u16 sample_pr_4;$/;"	m	struct:rc_setting	access:public
+rc_setting::sample_pr_5	include/ssv_cfg.h	/^    u16 sample_pr_5;$/;"	m	struct:rc_setting	access:public
+rc_setting::target_success	include/ssv_cfg.h	/^    u16 target_success;$/;"	m	struct:rc_setting	access:public
+rc_setting::target_success_4	include/ssv_cfg.h	/^    u16 target_success_4;$/;"	m	struct:rc_setting	access:public
+rc_setting::target_success_5	include/ssv_cfg.h	/^    u16 target_success_5;$/;"	m	struct:rc_setting	access:public
+rc_setting::target_success_67	include/ssv_cfg.h	/^    u16 target_success_67;$/;"	m	struct:rc_setting	access:public
+rc_setting::up_pr	include/ssv_cfg.h	/^    u16 up_pr;$/;"	m	struct:rc_setting	access:public
+rc_setting::up_pr3	include/ssv_cfg.h	/^    u16 up_pr3;$/;"	m	struct:rc_setting	access:public
+rc_setting::up_pr4	include/ssv_cfg.h	/^    u16 up_pr4;$/;"	m	struct:rc_setting	access:public
+rc_setting::up_pr5	include/ssv_cfg.h	/^    u16 up_pr5;$/;"	m	struct:rc_setting	access:public
+rc_setting::up_pr6	include/ssv_cfg.h	/^    u16 up_pr6;$/;"	m	struct:rc_setting	access:public
+rc_supp_rates	smac/ssv_rc_common.h	/^    u32 rc_supp_rates;$/;"	m	struct:ssv_sta_rc_info	access:public
+rc_table	smac/ssv_rc_common.h	/^    struct ssv_rc_rate *rc_table;$/;"	m	struct:ssv_rate_ctrl	typeref:struct:ssv_rate_ctrl::ssv_rc_rate	access:public
+rc_type	smac/ssv_rc_common.h	/^    u8 rc_type;$/;"	m	struct:ssv_sta_rc_info	access:public
+rc_update_basic_rate	smac/dev.h	/^ void (*rc_update_basic_rate)(struct ssv_softc *sc, u32 basic_rates);$/;"	m	struct:ssv_hal_ops	access:public
+rc_valid	smac/ssv_rc_common.h	/^    u8 rc_valid;$/;"	m	struct:ssv_sta_rc_info	access:public
+rc_wsid	smac/ssv_rc_common.h	/^    s8 rc_wsid;$/;"	m	struct:ssv_sta_rc_info	access:public
+rd_key	crypto/aes_glue.c	/^ unsigned int rd_key[4 *(AES_MAXNR + 1)];$/;"	m	struct:__anon41	file:	access:public
+read	hwif/hwif.h	/^    int __must_check (*read)(struct device *child, void *buf,size_t *size, int mode);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+readBufferFromFile	smartlink/qqlink-lib-mipsel/case/ipcamera/main.c	/^bool readBufferFromFile(char *pPath, unsigned char *pBuffer, int nInSize, int *pSizeUsed) {$/;"	f	signature:(char *pPath, unsigned char *pBuffer, int nInSize, int *pSizeUsed)
+readBufferFromFile	smartlink/qqlink-lib-mipsel/demo_bind.c	/^bool readBufferFromFile(char *pPath, unsigned char *pBuffer, int nInSize, int *pSizeUsed) {$/;"	f	signature:(char *pPath, unsigned char *pBuffer, int nInSize, int *pSizeUsed)
+readBufferFromFile	smartlink/qqlink-lib-mipsel/demo_filetransfer.c	/^bool readBufferFromFile(char *pPath, unsigned char *pBuffer, int nInSize, int *pSizeUsed) {$/;"	f	signature:(char *pPath, unsigned char *pBuffer, int nInSize, int *pSizeUsed)
+readBufferFromFile	smartlink/qqlink-lib-mipsel/demo_video.c	/^bool readBufferFromFile(char *pPath, unsigned char *pBuffer, int nInSize, int *pSizeUsed) {$/;"	f	signature:(char *pPath, unsigned char *pBuffer, int nInSize, int *pSizeUsed)
+readFile	smac/efuse.c	/^int readFile(struct file *fp,char *buf,int readlen)$/;"	f	signature:(struct file *fp,char *buf,int readlen)
+read_cfg	script/scan_test.sh	/^read_cfg( )$/;"	f
+read_efuse	smac/dev.h	/^    u8 (*read_efuse)(struct ssv_hw *sh, u8 *pbuf);$/;"	m	struct:ssv_hal_ops	access:public
+read_efuse	smac/efuse.c	/^u8 read_efuse(struct ssv_hw *sh, u8 *pbuf)$/;"	f	signature:(struct ssv_hw *sh, u8 *pbuf)
+read_efuse	smac/efuse.h	/^u8 read_efuse(struct ssv_hw *sh, u8 *pbuf);$/;"	p	signature:(struct ssv_hw *sh, u8 *pbuf)
+read_ffout_cnt	smac/dev.h	/^    void (*read_ffout_cnt)(struct ssv_hw *sh, u32 *value, u32 *value1, u32 *value2);$/;"	m	struct:ssv_hal_ops	access:public
+read_id_len_threshold	smac/dev.h	/^    void (*read_id_len_threshold)(struct ssv_hw *sh, u32 *tx_len, u32 *rx_len);$/;"	m	struct:ssv_hal_ops	access:public
+read_in_ffcnt	smac/dev.h	/^    void (*read_in_ffcnt)(struct ssv_hw *sh, u32 *value, u32 *value1);$/;"	m	struct:ssv_hal_ops	access:public
+read_line	ssvdevice/ssvdevice.c	/^size_t read_line(struct file *fp, char *buf, size_t size)$/;"	f	signature:(struct file *fp, char *buf, size_t size)
+read_rs0_info_fail	hci/hctrl.h	/^    u32 read_rs0_info_fail;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+read_rs1_info_fail	hci/hctrl.h	/^    u32 read_rs1_info_fail;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+read_tag_status	smac/dev.h	/^    void (*read_tag_status)(struct ssv_hw *sh, u32 *ava_status);$/;"	m	struct:ssv_hal_ops	access:public
+read_wq	bridge/sdiobridge.h	/^    wait_queue_head_t read_wq;$/;"	m	struct:ssv_sdiobridge_glue	access:public
+read_wq	hci_wrapper/ssv_huw.c	/^    wait_queue_head_t read_wq;$/;"	m	struct:ssv_huw_dev	file:	access:public
+readfile_mac	smac/efuse.c	/^static int readfile_mac(u8 *path,u8 *mac_addr)$/;"	f	file:	signature:(u8 *path,u8 *mac_addr)
+readreg	hwif/hwif.h	/^    int __must_check (*readreg)(struct device *child, u32 addr, u32 *buf);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+readrg_hci_inq_info	smac/dev.h	/^    void (*readrg_hci_inq_info)(struct ssv_hw *sh, int *hci_used_id, int *tx_use_page);$/;"	m	struct:ssv_hal_ops	access:public
+readrg_txq_info	smac/dev.h	/^    bool (*readrg_txq_info)(struct ssv_hw *sh, u32 *txq_info, int *hci_used_id);$/;"	m	struct:ssv_hal_ops	access:public
+readrg_txq_info2	smac/dev.h	/^    bool (*readrg_txq_info2)(struct ssv_hw *sh, u32 *txq_info2, int *hci_used_id);$/;"	m	struct:ssv_hal_ops	access:public
+real_hw_index	smac/ssv_rc_common.h	/^    u8 real_hw_index;$/;"	m	struct:rc_pid_sta_info	access:public
+real_tx_irq_count	hci/hctrl.h	/^    u32 real_tx_irq_count;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+reason	include/ssv6200_common.h	/^    u32 reason:6;$/;"	m	struct:ssv6200_rx_desc	access:public
+reason	include/ssv6200_common.h	/^    u32 reason:6;$/;"	m	struct:ssv6200_tx_desc	access:public
+reason	smac/hal/ssv6006c/turismo_common.h	/^    u32 reason:6;$/;"	m	struct:ssv6006_rx_desc	access:public
+reason	smac/hal/ssv6006c/turismo_common.h	/^    u32 reason:6;$/;"	m	struct:ssv6006_tx_desc	access:public
+reason_trap0	smac/dev.h	/^ u32 reason_trap0;$/;"	m	struct:ssv_trap_data	access:public
+reason_trap1	smac/dev.h	/^ u32 reason_trap1;$/;"	m	struct:ssv_trap_data	access:public
+recover_scan_cci_setting	smac/dev.h	/^    void (*recover_scan_cci_setting)(struct ssv_softc *sc);$/;"	m	struct:ssv_hal_ops	access:public
+redownload	hci/hctrl.h	/^    bool redownload;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+reg	include/ssv6xxx_common.h	/^    u32 reg;$/;"	m	struct:ssv6xxx_tx_loopback	access:public
+regIOPort	bridge/sdiobridge.h	/^    unsigned int regIOPort;$/;"	m	struct:ssv_sdiobridge_glue	access:public
+regIOPort	hwif/sdio/sdio.c	/^    unsigned int regIOPort;$/;"	m	struct:ssv6xxx_sdio_glue	file:	access:public
+reg_addr	include/ssv6xxx_common.h	/^ u32 reg_addr;$/;"	m	struct:ssv6xxx_ch_cfg	access:public
+reg_wsid	smac/hal/ssv6006c/ssv6006C_mac.c	/^static const u32 reg_wsid[] = {ADR_WSID0, ADR_WSID1, ADR_WSID2, ADR_WSID3,$/;"	v	file:
+release_queue	smac/ampdu.h	/^    struct sk_buff_head release_queue;$/;"	m	struct:AMPDU_TID_st	typeref:struct:AMPDU_TID_st::sk_buff_head	access:public
+req	hwif/sdio/sdio_def.h	/^ u32 req;$/;"	m	struct:sdio_scatter_req	access:public
+reserve	smac/drv_comm.h	/^ u8 reserve[2];$/;"	m	struct:ssv6xxx_hw_sta_key	access:public
+reserve	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 reserve[1];$/;"	m	struct:ssv6006_hw_sta_key	access:public
+reserve	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 reserve[2];$/;"	m	struct:ssv6006_bss	access:public
+reserved	smac/ampdu.h	/^    u16 reserved:4;$/;"	m	struct:AMPDU_DELIMITER_st	access:public
+reserved	smac/ampdu.h	/^    u16 reserved:9;$/;"	m	struct:AMPDU_BLOCKACK_st	access:public
+reserved	smartlink/airkiss-lib/airkiss.h	/^ unsigned char reserved;$/;"	m	struct:__anon25	access:public
+reserved	smartlink/airkiss-lib/mipsel/airkiss.h	/^ unsigned char reserved;$/;"	m	struct:__anon19	access:public
+reserved	smartlink/airkiss-lib/x64/airkiss.h	/^ unsigned char reserved;$/;"	m	struct:__anon31	access:public
+reserved	smartlink/qqlink-lib-mipsel/include/TXAudioVideo.h	/^ unsigned int reserved;$/;"	m	struct:_tx_audio_encode_param	access:public
+reset_cpu	smac/dev.h	/^ int (*reset_cpu)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+reset_mib_phy	smac/dev.h	/^    void (*reset_mib_phy)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+reset_sysplf	smac/dev.h	/^    void (*reset_sysplf)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+resources	platforms/a33-generic-wlan.c	/^static struct resource resources[] = {$/;"	v	typeref:struct:resource	file:
+resources	platforms/atm7039-action-generic-wlan.c	/^static struct resource resources[] = { { .start = WIFI_HOST_WAKE,$/;"	v	typeref:struct:resource	file:
+resources	platforms/h3-generic-wlan.c	/^static struct resource resources[] = {$/;"	v	typeref:struct:resource	file:
+resources	platforms/h8-generic-wlan.c	/^static struct resource resources[] = {$/;"	v	typeref:struct:resource	file:
+resources	platforms/t10-generic-wlan.c	/^static struct resource resources[] = {$/;"	v	typeref:struct:resource	file:
+resources	platforms/x1000-generic-wlan.c	/^static struct resource resources[] = {$/;"	v	typeref:struct:resource	file:
+response	bridge/sdiobridge_pub.h	/^    __u32 response;$/;"	m	struct:ssv_sdiobridge_cmd	access:public
+response	hci_wrapper/ssv_huw.h	/^    __u32 response;$/;"	m	struct:ssv_huw_cmd	access:public
+restart_counter	smac/dev.h	/^    u32 restart_counter;$/;"	m	struct:ssv_softc	access:public
+restore	include/ssv6xxx_common.h	/^    u8 restore;$/;"	m	struct:ssv6xxx_tx_loopback	access:public
+restore_rx_flow	smac/dev.h	/^    void (*restore_rx_flow)(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv, struct ieee80211_sta *sta);$/;"	m	struct:ssv_hal_ops	access:public
+restore_trap_reason	smac/dev.h	/^ void (*restore_trap_reason)(struct ssv_softc *sc);$/;"	m	struct:ssv_hal_ops	access:public
+restore_val	include/ssv6xxx_common.h	/^    u32 restore_val;$/;"	m	struct:ssv6xxx_tx_loopback	access:public
+result_buffer_size	ssvdevice/ssv_cmd.h	/^    const int result_buffer_size;$/;"	m	struct:ssv_cmd_table	access:public
+resum_thres	hci/ssv_hci.h	/^    int resum_thres;$/;"	m	struct:ssv_hw_txq	access:public
+resume	hwif/hwif.h	/^ void (*resume)(void *param);$/;"	m	struct:ssv6xxx_platform_data	access:public
+ret_code	smartlink/qqlink-lib-mipsel/include/TXDataPoint.h	/^    unsigned int ret_code;$/;"	m	struct:tag_tx_data_point	access:public
+retry_count	smac/ssv_rc_common.h	/^    unsigned int retry_count;$/;"	m	struct:minstrel_rate_stats	access:public
+retry_count	smac/ssv_rc_minstrel.h	/^ unsigned int retry_count;$/;"	m	struct:ssv_minstrel_rate	access:public
+retry_count	smac/ssv_rc_minstrel_ht.h	/^ unsigned int retry_count;$/;"	m	struct:ssv_minstrel_ht_rate_stats	access:public
+retry_count_cts	smac/ssv_rc_minstrel.h	/^ unsigned int retry_count_cts;$/;"	m	struct:ssv_minstrel_rate	access:public
+retry_count_rtscts	smac/ssv_rc_common.h	/^    unsigned int retry_count_rtscts;$/;"	m	struct:minstrel_rate_stats	access:public
+retry_count_rtscts	smac/ssv_rc_minstrel.h	/^ unsigned int retry_count_rtscts;$/;"	m	struct:ssv_minstrel_rate	access:public
+retry_count_rtscts	smac/ssv_rc_minstrel_ht.h	/^ unsigned int retry_count_rtscts;$/;"	m	struct:ssv_minstrel_ht_rate_stats	access:public
+retry_queue	smac/ampdu.h	/^    struct sk_buff_head retry_queue;$/;"	m	struct:AMPDU_TID_st	typeref:struct:AMPDU_TID_st::sk_buff_head	access:public
+retry_samples	smac/dev.h	/^    u32 retry_samples[16];$/;"	m	struct:ssv_sta_priv_data	access:public
+retry_updated	smac/ssv_rc_minstrel_ht.h	/^ bool retry_updated;$/;"	m	struct:ssv_minstrel_ht_rate_stats	access:public
+rf_ctrl_F	smac/dev.h	/^    u32 rf_ctrl_F;$/;"	m	struct:ssv6xxx_calib_table	access:public
+rf_ctrl_N	smac/dev.h	/^    u32 rf_ctrl_N;$/;"	m	struct:ssv6xxx_calib_table	access:public
+rf_precision_default	smac/dev.h	/^    u16 rf_precision_default;$/;"	m	struct:ssv6xxx_calib_table	access:public
+rf_rc	smac/dev.h	/^    u8 rf_rc;$/;"	m	struct:ssv_softc	access:public
+rf_tbl_size	include/ssv6xxx_common.h	/^    u32 rf_tbl_size;$/;"	m	struct:ssv6xxx_iqk_cfg	access:public
+rinfo	smac/ssv_rc_common.h	/^ struct rc_pid_rateinfo rinfo[12];$/;"	m	struct:rc_pid_info	typeref:struct:rc_pid_info::rc_pid_rateinfo	access:public
+rix	smac/ssv_rc_minstrel.h	/^ int rix;$/;"	m	struct:ssv_minstrel_rate	access:public
+rockchip_wifi_get_oob_irq	platforms/rk3126-generic-wlan.c	/^extern int rockchip_wifi_get_oob_irq(void);$/;"	p	file:	signature:(void)
+rockchip_wifi_mac_addr	smac/efuse.c	/^extern int rockchip_wifi_mac_addr(unsigned char *buf);$/;"	p	file:	signature:(unsigned char *buf)
+rockchip_wifi_power	platforms/rk3036-generic-wlan.c	/^extern int rockchip_wifi_power(int on);$/;"	p	file:	signature:(int on)
+rockchip_wifi_power	platforms/rk3126-generic-wlan.c	/^extern int rockchip_wifi_power(int on);$/;"	p	file:	signature:(int on)
+rockchip_wifi_power	platforms/rk3128-generic-wlan.c	/^extern int rockchip_wifi_power(int on);$/;"	p	file:	signature:(int on)
+rockchip_wifi_power	platforms/rk322x-generic-wlan.c	/^extern int rockchip_wifi_power(int on);$/;"	p	file:	signature:(int on)
+rockchip_wifi_set_carddetect	platforms/rk3036-generic-wlan.c	/^extern int rockchip_wifi_set_carddetect(int val);$/;"	p	file:	signature:(int val)
+rockchip_wifi_set_carddetect	platforms/rk3126-generic-wlan.c	/^extern int rockchip_wifi_set_carddetect(int val);$/;"	p	file:	signature:(int val)
+rockchip_wifi_set_carddetect	platforms/rk3128-generic-wlan.c	/^extern int rockchip_wifi_set_carddetect(int val);$/;"	p	file:	signature:(int val)
+rockchip_wifi_set_carddetect	platforms/rk322x-generic-wlan.c	/^extern int rockchip_wifi_set_carddetect(int val);$/;"	p	file:	signature:(int val)
+rotate_degree	smartlink/qqlink-lib-mipsel/include/TXIPCAM.h	/^enum rotate_degree {$/;"	g
+rotate_degree_h_max	smartlink/qqlink-lib-mipsel/include/TXIPCAM.h	/^ rotate_degree_h_max = 360,$/;"	e	enum:rotate_degree
+rotate_degree_h_min	smartlink/qqlink-lib-mipsel/include/TXIPCAM.h	/^ rotate_degree_h_min = 0,$/;"	e	enum:rotate_degree
+rotate_degree_v_max	smartlink/qqlink-lib-mipsel/include/TXIPCAM.h	/^ rotate_degree_v_max = 180,$/;"	e	enum:rotate_degree
+rotate_degree_v_min	smartlink/qqlink-lib-mipsel/include/TXIPCAM.h	/^ rotate_degree_v_min = 0,$/;"	e	enum:rotate_degree
+rotate_direction	smartlink/qqlink-lib-mipsel/include/TXIPCAM.h	/^enum rotate_direction {$/;"	g
+rotate_direction_down	smartlink/qqlink-lib-mipsel/include/TXIPCAM.h	/^ rotate_direction_down = 4,$/;"	e	enum:rotate_direction
+rotate_direction_left	smartlink/qqlink-lib-mipsel/include/TXIPCAM.h	/^ rotate_direction_left = 1,$/;"	e	enum:rotate_direction
+rotate_direction_right	smartlink/qqlink-lib-mipsel/include/TXIPCAM.h	/^ rotate_direction_right = 2,$/;"	e	enum:rotate_direction
+rotate_direction_up	smartlink/qqlink-lib-mipsel/include/TXIPCAM.h	/^ rotate_direction_up = 3,$/;"	e	enum:rotate_direction
+rounds	crypto/aes_glue.c	/^ int rounds;$/;"	m	struct:__anon41	file:	access:public
+rpci	include/ssv6200_common.h	/^    u32 rpci:8;$/;"	m	struct:ssv6200_rxphy_info	access:public
+rpci	include/ssv6200_common.h	/^u32 rpci:8;$/;"	m	struct:ssv6200_rxphy_info_padding	access:public
+rpt_noctstrycnt0	smac/hal/ssv6006c/turismo_common.h	/^    u32 rpt_noctstrycnt0:4;$/;"	m	struct:ssv6006_tx_desc	access:public
+rpt_noctstrycnt1	smac/hal/ssv6006c/turismo_common.h	/^    u32 rpt_noctstrycnt1:4;$/;"	m	struct:ssv6006_tx_desc	access:public
+rpt_noctstrycnt2	smac/hal/ssv6006c/turismo_common.h	/^    u32 rpt_noctstrycnt2:4;$/;"	m	struct:ssv6006_tx_desc	access:public
+rpt_noctstrycnt3	smac/hal/ssv6006c/turismo_common.h	/^    u32 rpt_noctstrycnt3:4;$/;"	m	struct:ssv6006_tx_desc	access:public
+rpt_result0	smac/hal/ssv6006c/turismo_common.h	/^    u32 rpt_result0:2;$/;"	m	struct:ssv6006_tx_desc	access:public
+rpt_result1	smac/hal/ssv6006c/turismo_common.h	/^    u32 rpt_result1:2;$/;"	m	struct:ssv6006_tx_desc	access:public
+rpt_result2	smac/hal/ssv6006c/turismo_common.h	/^    u32 rpt_result2:2;$/;"	m	struct:ssv6006_tx_desc	access:public
+rpt_result3	smac/hal/ssv6006c/turismo_common.h	/^    u32 rpt_result3:2;$/;"	m	struct:ssv6006_tx_desc	access:public
+rpt_trycnt0	smac/hal/ssv6006c/turismo_common.h	/^    u32 rpt_trycnt0:4;$/;"	m	struct:ssv6006_tx_desc	access:public
+rpt_trycnt1	smac/hal/ssv6006c/turismo_common.h	/^    u32 rpt_trycnt1:4;$/;"	m	struct:ssv6006_tx_desc	access:public
+rpt_trycnt2	smac/hal/ssv6006c/turismo_common.h	/^    u32 rpt_trycnt2:4;$/;"	m	struct:ssv6006_tx_desc	access:public
+rpt_trycnt3	smac/hal/ssv6006c/turismo_common.h	/^    u32 rpt_trycnt3:4;$/;"	m	struct:ssv6006_tx_desc	access:public
+rreg	hwif/usb/usb.h	/^ struct ssv6xxx_read_reg rreg;$/;"	m	union:ssv6xxx_payload	typeref:struct:ssv6xxx_payload::ssv6xxx_read_reg	access:public
+rreg_res	hwif/usb/usb.h	/^ struct ssv6xxx_read_reg_result rreg_res;$/;"	m	union:ssv6xxx_payload	typeref:struct:ssv6xxx_payload::ssv6xxx_read_reg_result	access:public
+rsbuf_len	smac/dev.h	/^    u32 rsbuf_len;$/;"	m	struct:ssv_cmd_data	access:public
+rsbuf_size	smac/dev.h	/^    u32 rsbuf_size;$/;"	m	struct:ssv_cmd_data	access:public
+rsp_endpoint	hwif/usb/usb.c	/^ struct ssv6xxx_cmd_endpoint rsp_endpoint;$/;"	m	struct:ssv6xxx_usb_glue	typeref:struct:ssv6xxx_usb_glue::ssv6xxx_cmd_endpoint	file:	access:public
+rssi	smac/hal/ssv6006c/turismo_common.h	/^    u32 rssi:8;$/;"	m	struct:ssv6006_rxphy_info	access:public
+rsvd	hci/hctrl.h	/^    u32 rsvd:11;$/;"	m	struct:ssv6xxx_hci_txq_info2	access:public
+rsvd	include/ssv6200_common.h	/^    u32 rsvd[7];$/;"	m	struct:ssv6200_txphy_info	access:public
+rsvd0	include/ssv6200_common.h	/^    u32 rsvd0:16;$/;"	m	struct:ssv6200_rxphy_info	access:public
+rsvd1	include/ssv6200_common.h	/^    u32 rsvd1:1;$/;"	m	struct:ssv6200_rxphy_info	access:public
+rsvd2	include/ssv6200_common.h	/^    u32 rsvd2:8;$/;"	m	struct:ssv6200_rxphy_info	access:public
+rsvd3	include/ssv6200_common.h	/^    u32 rsvd3:17;$/;"	m	struct:ssv6200_rxphy_info	access:public
+rsvd4	include/ssv6200_common.h	/^    u32 rsvd4;$/;"	m	struct:ssv6200_rxphy_info	access:public
+rsvd_rx_3b	smac/hal/ssv6006c/turismo_common.h	/^    u32 rsvd_rx_3b:8;$/;"	m	struct:ssv6006_rx_desc	access:public
+rsvd_tx05	smac/hal/ssv6006c/turismo_common.h	/^    u32 rsvd_tx05 :2;$/;"	m	struct:ssv6006_tx_desc	access:public
+rsvdrx0_1	smac/hal/ssv6006c/turismo_common.h	/^    u32 rsvdrx0_1:1;$/;"	m	struct:ssv6006_rx_desc	access:public
+rsvdtx_07b	smac/hal/ssv6006c/turismo_common.h	/^    u32 rsvdtx_07b:1;$/;"	m	struct:ssv6006_tx_desc	access:public
+rsvdtx_09b	smac/hal/ssv6006c/turismo_common.h	/^    u32 rsvdtx_09b:1;$/;"	m	struct:ssv6006_tx_desc	access:public
+rsvdtx_1	smac/hal/ssv6006c/turismo_common.h	/^    u32 rsvdtx_1:1;$/;"	m	struct:ssv6006_tx_desc	access:public
+rsvdtx_11b	smac/hal/ssv6006c/turismo_common.h	/^    u32 rsvdtx_11b:1;$/;"	m	struct:ssv6006_tx_desc	access:public
+rsvdtx_13b	smac/hal/ssv6006c/turismo_common.h	/^    u32 rsvdtx_13b:1;$/;"	m	struct:ssv6006_tx_desc	access:public
+rsvdtx_14a	smac/hal/ssv6006c/turismo_common.h	/^    u32 rsvdtx_14a:3;$/;"	m	struct:ssv6006_tx_desc	access:public
+rt_config	smac/dev.h	/^    struct ssv_tempe_table rt_config;$/;"	m	struct:ssv_flash_config	typeref:struct:ssv_flash_config::ssv_tempe_table	access:public
+rts_cts_nav	include/ssv6200_common.h	/^    u32 rts_cts_nav:16;$/;"	m	struct:ssv6200_tx_desc	access:public
+rts_cts_nav	include/ssv6xxx_common.h	/^    u32 rts_cts_nav:16;$/;"	m	struct:fw_rc_retry_params	access:public
+rts_cts_nav0	smac/hal/ssv6006c/turismo_common.h	/^    u32 rts_cts_nav0:16;$/;"	m	struct:ssv6006_tx_desc	access:public
+rts_cts_nav1	smac/hal/ssv6006c/turismo_common.h	/^    u32 rts_cts_nav1:16;$/;"	m	struct:ssv6006_tx_desc	access:public
+rts_cts_nav2	smac/hal/ssv6006c/turismo_common.h	/^    u32 rts_cts_nav2:16;$/;"	m	struct:ssv6006_tx_desc	access:public
+rts_cts_nav3	smac/hal/ssv6006c/turismo_common.h	/^    u32 rts_cts_nav3:16;$/;"	m	struct:ssv6006_tx_desc	access:public
+rts_thres_len	include/ssv_cfg.h	/^    u32 rts_thres_len;$/;"	m	struct:ssv6xxx_cfg	access:public
+running	smac/dev.h	/^    volatile int running;$/;"	m	struct:ssv_encrypt_task_list	access:public
+running_no	smac/hal/ssv6006c/turismo_common.h	/^    u32 running_no:4;$/;"	m	struct:ssv6006_rx_desc	access:public
+rvdtx_0	smac/hal/ssv6006c/turismo_common.h	/^    u32 rvdtx_0:3;$/;"	m	struct:ssv6006_tx_desc	access:public
+rw_scatter	hwif/hwif.h	/^    int (*rw_scatter)(struct device *child, struct sdio_scatter_req *scat_req);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+rx	smac/dev.h	/^    struct ssv_rx rx;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::ssv_rx	access:public
+rx_a	smac/sec_ccmp.c	/^    u8 *rx_b0, *rx_b, *rx_a;$/;"	m	struct:lib80211_ccmp_data	file:	access:public
+rx_a	smac/sec_ccmp.c	/^    u8 rx_b0[AES_BLOCK_LEN], rx_b[AES_BLOCK_LEN], rx_a[AES_BLOCK_LEN];$/;"	m	struct:lib80211_ccmp_data	file:	access:public
+rx_b	smac/sec_ccmp.c	/^    u8 *rx_b0, *rx_b, *rx_a;$/;"	m	struct:lib80211_ccmp_data	file:	access:public
+rx_b	smac/sec_ccmp.c	/^    u8 rx_b0[AES_BLOCK_LEN], rx_b[AES_BLOCK_LEN], rx_a[AES_BLOCK_LEN];$/;"	m	struct:lib80211_ccmp_data	file:	access:public
+rx_b0	smac/sec_ccmp.c	/^    u8 *rx_b0, *rx_b, *rx_a;$/;"	m	struct:lib80211_ccmp_data	file:	access:public
+rx_b0	smac/sec_ccmp.c	/^    u8 rx_b0[AES_BLOCK_LEN], rx_b[AES_BLOCK_LEN], rx_a[AES_BLOCK_LEN];$/;"	m	struct:lib80211_ccmp_data	file:	access:public
+rx_ba_bitmap	smac/dev.h	/^    u8 rx_ba_bitmap;$/;"	m	struct:ssv_softc	access:public
+rx_ba_ma_sessions	include/ssv6xxx_common.h	/^ u32 rx_ba_ma_sessions;$/;"	m	struct:ssv6xxx_rx_hw_info	access:public
+rx_ba_session_count	smac/dev.h	/^    int rx_ba_session_count;$/;"	m	struct:ssv_softc	access:public
+rx_ba_sta	smac/dev.h	/^    struct ieee80211_sta *rx_ba_sta;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::ieee80211_sta	access:public
+rx_buf	hci/hctrl.h	/^    struct sk_buff *rx_buf;$/;"	m	struct:ssv6xxx_hci_ctrl	typeref:struct:ssv6xxx_hci_ctrl::sk_buff	access:public
+rx_buf	hwif/usb/usb.h	/^    void *rx_buf;$/;"	m	struct:ssv6xxx_rx_buf	access:public
+rx_buf	smac/dev.h	/^    struct sk_buff *rx_buf;$/;"	m	struct:ssv_rx	typeref:struct:ssv_rx::sk_buff	access:public
+rx_burstread	include/ssv_cfg.h	/^    bool rx_burstread;$/;"	m	struct:ssv6xxx_cfg	access:public
+rx_burstread_cnt	smac/dev.h	/^    int rx_burstread_cnt;$/;"	m	struct:ssv_hw	access:public
+rx_burstread_param	hwif/hwif.h	/^    void *rx_burstread_param;$/;"	m	struct:ssv6xxx_platform_data	access:public
+rx_burstread_size	hwif/hwif.h	/^    int (*rx_burstread_size)(void *param);$/;"	m	struct:ssv6xxx_platform_data	access:public
+rx_burstread_size_type	smac/dev.h	/^    int rx_burstread_size_type;$/;"	m	struct:ssv_hw	access:public
+rx_cb	hwif/usb/usb.c	/^    int (*rx_cb)(struct sk_buff *rx_skb, void *args);$/;"	m	struct:ssv6xxx_usb_glue	file:	access:public
+rx_cb	hwif/usb/usb.c	/^    int (*rx_cb)(struct sk_buff_head *rxq, void *args);$/;"	m	struct:ssv6xxx_usb_glue	file:	access:public
+rx_cb_args	hwif/usb/usb.c	/^ void *rx_cb_args;$/;"	m	struct:ssv6xxx_usb_glue	file:	access:public
+rx_data_exist	smac/dev.h	/^    bool rx_data_exist;$/;"	m	struct:ssv_softc	access:public
+rx_data_rate	smac/dev.h	/^    int rx_data_rate;$/;"	m	struct:ssv_sta_priv_data	access:public
+rx_desc_len	smac/dev.h	/^    u32 rx_desc_len;$/;"	m	struct:ssv_hw	access:public
+rx_endpoint	hwif/usb/usb.c	/^ struct ssv6xxx_rx_endpoint rx_endpoint;$/;"	m	struct:ssv6xxx_usb_glue	typeref:struct:ssv6xxx_usb_glue::ssv6xxx_rx_endpoint	file:	access:public
+rx_filled	hwif/usb/usb.h	/^    unsigned int rx_filled;$/;"	m	struct:ssv6xxx_rx_buf	access:public
+rx_freq_offset	smac/hal/ssv6006c/turismo_common.h	/^    u32 rx_freq_offset:16;$/;"	m	struct:ssv6006_rxphy_info	access:public
+rx_hdr	smac/sec_tkip.c	/^ u8 rx_hdr[16], tx_hdr[16];$/;"	m	struct:lib80211_tkip_data	file:	access:public
+rx_id_threshold	include/ssv6xxx_common.h	/^ u32 rx_id_threshold;$/;"	m	struct:ssv6xxx_rx_hw_info	access:public
+rx_info	hci/hctrl.h	/^ struct ssv6xxx_rx_hw_info rx_info;$/;"	m	struct:ssv6xxx_hci_ctrl	typeref:struct:ssv6xxx_hci_ctrl::ssv6xxx_rx_hw_info	access:public
+rx_info	smac/dev.h	/^ struct ssv6xxx_rx_hw_info rx_info;$/;"	m	struct:ssv_hw	typeref:struct:ssv_hw::ssv6xxx_rx_hw_info	access:public
+rx_irq_count	hci/hctrl.h	/^    u32 rx_irq_count;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+rx_iv16	smac/sec_tkip.c	/^ u16 rx_iv16;$/;"	m	struct:lib80211_tkip_data	file:	access:public
+rx_iv16_new	smac/sec_tkip.c	/^ u16 rx_iv16_new;$/;"	m	struct:lib80211_tkip_data	file:	access:public
+rx_iv32	smac/sec_tkip.c	/^ u32 rx_iv32;$/;"	m	struct:lib80211_tkip_data	file:	access:public
+rx_iv32_new	smac/sec_tkip.c	/^ u32 rx_iv32_new;$/;"	m	struct:lib80211_tkip_data	file:	access:public
+rx_mode	smac/dev.h	/^    int rx_mode;$/;"	m	struct:ssv_hw	access:public
+rx_page_threshold	include/ssv6xxx_common.h	/^ u32 rx_page_threshold;$/;"	m	struct:ssv6xxx_rx_hw_info	access:public
+rx_phase1_done	smac/sec_tkip.c	/^ int rx_phase1_done;$/;"	m	struct:lib80211_tkip_data	file:	access:public
+rx_pinfo_pad	smac/dev.h	/^    u32 rx_pinfo_pad;$/;"	m	struct:ssv_hw	access:public
+rx_pkt	hci/hctrl.h	/^    u32 rx_pkt;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+rx_pkt	hwif/usb/usb.c	/^ u32 *rx_pkt;$/;"	m	struct:ssv6xxx_usb_glue	file:	access:public
+rx_pkt_run_no	smac/hal/ssv6006c/turismo_common.h	/^    u32 rx_pkt_run_no:8;$/;"	m	struct:ssv6006_rx_desc	access:public
+rx_pn	smac/sec_ccmp.c	/^ u8 rx_pn[CCMP_PN_LEN];$/;"	m	struct:lib80211_ccmp_data	file:	access:public
+rx_pn_h	smac/drv_comm.h	/^    u32 rx_pn_h;$/;"	m	struct:ssv6xxx_hw_key	access:public
+rx_pn_l	smac/drv_comm.h	/^ u32 rx_pn_l;$/;"	m	struct:ssv6xxx_hw_key	access:public
+rx_res	hwif/usb/usb.h	/^    int rx_res;$/;"	m	struct:ssv6xxx_rx_buf	access:public
+rx_skb_q	hci_wrapper/ssv_huw.c	/^ struct sk_buff_head rx_skb_q;$/;"	m	struct:ssv_huw_dev	typeref:struct:ssv_huw_dev::sk_buff_head	file:	access:public
+rx_skb_q	smac/dev.h	/^    struct sk_buff_head rx_skb_q;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::sk_buff_head	access:public
+rx_stats	smac/dev.h	/^struct rx_stats {$/;"	s
+rx_stats::cck_pkts	smac/dev.h	/^    u64 cck_pkts[4];$/;"	m	struct:rx_stats	access:public
+rx_stats::g_pkts	smac/dev.h	/^    u64 g_pkts[8];$/;"	m	struct:rx_stats	access:public
+rx_stats::ht40	smac/dev.h	/^    u8 ht40;$/;"	m	struct:rx_stats	access:public
+rx_stats::n_pkts	smac/dev.h	/^    u64 n_pkts[8];$/;"	m	struct:rx_stats	access:public
+rx_stats::phy_mode	smac/dev.h	/^    u8 phy_mode;$/;"	m	struct:rx_stats	access:public
+rx_stuck_idle_time	smac/dev.h	/^    int rx_stuck_idle_time;$/;"	m	struct:ssv_softc	access:public
+rx_stuck_reset_time	smac/dev.h	/^    unsigned long rx_stuck_reset_time;$/;"	m	struct:ssv_softc	access:public
+rx_stuck_work	smac/dev.h	/^    struct work_struct rx_stuck_work;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::work_struct	access:public
+rx_task	smac/dev.h	/^    struct task_struct *rx_task;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::task_struct	access:public
+rx_tasklet	hwif/usb/usb.c	/^ struct tasklet_struct rx_tasklet;$/;"	m	struct:ssv6xxx_usb_glue	typeref:struct:ssv6xxx_usb_glue::tasklet_struct	file:	access:public
+rx_tfm	smac/sec_wep.c	/^    struct crypto_blkcipher *rx_tfm;$/;"	m	struct:lib80211_wep_data	typeref:struct:lib80211_wep_data::crypto_blkcipher	file:	access:public
+rx_tfm_arc4	smac/sec_tkip.c	/^ struct crypto_blkcipher *rx_tfm_arc4;$/;"	m	struct:lib80211_tkip_data	typeref:struct:lib80211_tkip_data::crypto_blkcipher	file:	access:public
+rx_tfm_arc4	smac/sec_tkip.c	/^ struct crypto_skcipher *rx_tfm_arc4;$/;"	m	struct:lib80211_tkip_data	typeref:struct:lib80211_tkip_data::crypto_skcipher	file:	access:public
+rx_tfm_michael	smac/sec_tkip.c	/^ struct crypto_ahash *rx_tfm_michael;$/;"	m	struct:lib80211_tkip_data	typeref:struct:lib80211_tkip_data::crypto_ahash	file:	access:public
+rx_tfm_michael	smac/sec_tkip.c	/^ struct crypto_hash *rx_tfm_michael;$/;"	m	struct:lib80211_tkip_data	typeref:struct:lib80211_tkip_data::crypto_hash	file:	access:public
+rx_threshold	include/ssv_cfg.h	/^    u32 rx_threshold;$/;"	m	struct:ssv6xxx_cfg	access:public
+rx_time_stamp	smac/hal/ssv6006c/turismo_common.h	/^    u32 rx_time_stamp;$/;"	m	struct:ssv6006_rxphy_info	access:public
+rx_ttak	smac/sec_tkip.c	/^ u16 rx_ttak[5];$/;"	m	struct:lib80211_tkip_data	file:	access:public
+rx_urb	hwif/usb/usb.h	/^    struct urb *rx_urb;$/;"	m	struct:ssv6xxx_rx_buf	typeref:struct:ssv6xxx_rx_buf::urb	access:public
+rx_wait_q	smac/dev.h	/^    wait_queue_head_t rx_wait_q;$/;"	m	struct:ssv_softc	access:public
+rx_wait_q_woken	smac/dev.h	/^    u16 rx_wait_q_woken;$/;"	m	struct:ssv_softc	access:public
+rx_work	hwif/usb/usb.c	/^ struct ssv6xxx_usb_work_struct rx_work;$/;"	m	struct:ssv6xxx_usb_glue	typeref:struct:ssv6xxx_usb_glue::ssv6xxx_usb_work_struct	file:	access:public
+rx_work_running	hci/hctrl.h	/^    u32 rx_work_running;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+rxbuf	bridge/sdiobridge.h	/^ struct list_head rxbuf;$/;"	m	struct:ssv_sdiobridge_glue	typeref:struct:ssv_sdiobridge_glue::list_head	access:public
+rxbuflock	bridge/sdiobridge.h	/^    spinlock_t rxbuflock;$/;"	m	struct:ssv_sdiobridge_glue	access:public
+rxdata	bridge/sdiobridge.c	/^    u8 rxdata[RXBUFLENGTH];$/;"	m	struct:ssv_rxbuf	file:	access:public
+rxdata	hci_wrapper/ssv_huw.c	/^    u8 rxdata[RXBUFLENGTH];$/;"	m	struct:ssv_rxbuf	file:	access:public
+rxdc_2g	smac/dev.h	/^    u32 rxdc_2g[21];$/;"	m	struct:ssv6006_cal_result	access:public
+rxdc_2g	smac/hal/ssv6006c/turismo_common.h	/^    u32 rxdc_2g[21];$/;"	m	struct:ssv6006_cal_result	access:public
+rxdc_5g	smac/dev.h	/^    u32 rxdc_5g[21];$/;"	m	struct:ssv6006_cal_result	access:public
+rxdc_5g	smac/hal/ssv6006c/turismo_common.h	/^    u32 rxdc_5g[21];$/;"	m	struct:ssv6006_cal_result	access:public
+rxiq_alpha	smac/dev.h	/^    u8 rxiq_alpha[PADPDBAND];$/;"	m	struct:ssv6006_cal_result	access:public
+rxiq_alpha	smac/hal/ssv6006c/turismo_common.h	/^    u8 rxiq_alpha[PADPDBAND];$/;"	m	struct:ssv6006_cal_result	access:public
+rxiq_theta	smac/dev.h	/^    u8 rxiq_theta[PADPDBAND];$/;"	m	struct:ssv6006_cal_result	access:public
+rxiq_theta	smac/hal/ssv6006c/turismo_common.h	/^    u8 rxiq_theta[PADPDBAND];$/;"	m	struct:ssv6006_cal_result	access:public
+rxlock	hci_wrapper/ssv_huw.c	/^    spinlock_t rxlock;$/;"	m	struct:ssv_huw_dev	file:	access:public
+rxq_count	smac/dev.h	/^    u32 rxq_count;$/;"	m	struct:ssv_rx	access:public
+rxq_head	smac/dev.h	/^    struct sk_buff_head rxq_head;$/;"	m	struct:ssv_rx	typeref:struct:ssv_rx::sk_buff_head	access:public
+rxq_lock	smac/dev.h	/^    spinlock_t rxq_lock;$/;"	m	struct:ssv_rx	access:public
+rxrc_bw20	smac/dev.h	/^    u8 rxrc_bw20;$/;"	m	struct:ssv6006_cal_result	access:public
+rxrc_bw20	smac/hal/ssv6006c/turismo_common.h	/^    u8 rxrc_bw20;$/;"	m	struct:ssv6006_cal_result	access:public
+rxrc_bw40	smac/dev.h	/^    u8 rxrc_bw40;$/;"	m	struct:ssv6006_cal_result	access:public
+rxrc_bw40	smac/hal/ssv6006c/turismo_common.h	/^    u8 rxrc_bw40;$/;"	m	struct:ssv6006_cal_result	access:public
+rxreadybuf	bridge/sdiobridge.h	/^    struct list_head rxreadybuf;$/;"	m	struct:ssv_sdiobridge_glue	typeref:struct:ssv_sdiobridge_glue::list_head	access:public
+rxsize	bridge/sdiobridge.c	/^    u32 rxsize;$/;"	m	struct:ssv_rxbuf	file:	access:public
+rxsize	hci_wrapper/ssv_huw.c	/^    u32 rxsize;$/;"	m	struct:ssv_rxbuf	file:	access:public
+rxstats	smac/dev.h	/^    struct rx_stats rxstats;$/;"	m	struct:ssv_sta_priv_data	typeref:struct:ssv_sta_priv_data::rx_stats	access:public
+s_bstart	smartlink/qqlink-lib-mipsel/case/ipcamera/audiovideo.c	/^static bool s_bstart = false;$/;"	v	file:
+s_bstart	smartlink/qqlink-lib-mipsel/demo_video.c	/^static bool s_bstart = false;$/;"	v	file:
+s_cData	smartlink/qqlink-lib-mipsel/case/ipcamera/audiovideo.c	/^static char* s_cData = NULL;$/;"	v	file:
+s_cData	smartlink/qqlink-lib-mipsel/demo_video.c	/^static char* s_cData = NULL;$/;"	v	file:
+s_dwTotalFrameIndex	smartlink/qqlink-lib-mipsel/case/ipcamera/audiovideo.c	/^static unsigned long s_dwTotalFrameIndex = 0;$/;"	v	file:
+s_dwTotalFrameIndex	smartlink/qqlink-lib-mipsel/demo_video.c	/^static unsigned long s_dwTotalFrameIndex = 0;$/;"	v	file:
+s_flags	smac/dev.h	/^    u16 s_flags;$/;"	m	struct:ssv_sta_info	access:public
+s_huw_ops	hci_wrapper/ssv_huw.c	/^struct file_operations s_huw_ops =$/;"	v	typeref:struct:file_operations
+safe_readreg	hwif/hwif.h	/^    int __must_check (*safe_readreg)(struct device *child, u32 addr, u32 *buf);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+safe_writereg	hwif/hwif.h	/^    int __must_check (*safe_writereg)(struct device *child, u32 addr, u32 buf);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+sample_column	smac/ssv_rc_minstrel.h	/^ unsigned int sample_column;$/;"	m	struct:ssv_minstrel_sta_info	access:public
+sample_count	smac/ssv_rc_common.h	/^    u8 sample_count;$/;"	m	struct:ssv62xx_ht	access:public
+sample_count	smac/ssv_rc_minstrel.h	/^ u64 sample_count;$/;"	m	struct:ssv_minstrel_sta_info	access:public
+sample_count	smac/ssv_rc_minstrel_ht.h	/^ u8 sample_count;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+sample_deferred	smac/ssv_rc_minstrel.h	/^ int sample_deferred;$/;"	m	struct:ssv_minstrel_sta_info	access:public
+sample_group	smac/ssv_rc_minstrel_ht.h	/^ u8 sample_group;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+sample_idx	smac/ssv_rc_minstrel.h	/^ unsigned int sample_idx;$/;"	m	struct:ssv_minstrel_sta_info	access:public
+sample_limit	smac/ssv_rc_minstrel.h	/^ int sample_limit;$/;"	m	struct:ssv_minstrel_rate	access:public
+sample_packets	smac/ssv_rc_common.h	/^    unsigned int sample_packets;$/;"	m	struct:ssv62xx_ht	access:public
+sample_packets	smac/ssv_rc_minstrel_ht.h	/^ u64 sample_packets;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+sample_pr_4	include/ssv_cfg.h	/^    u16 sample_pr_4;$/;"	m	struct:rc_setting	access:public
+sample_pr_5	include/ssv_cfg.h	/^    u16 sample_pr_5;$/;"	m	struct:rc_setting	access:public
+sample_skipped	smac/ssv_rc_common.h	/^    u8 sample_skipped;$/;"	m	struct:minstrel_rate_stats	access:public
+sample_skipped	smac/ssv_rc_minstrel_ht.h	/^ u16 sample_skipped;$/;"	m	struct:ssv_minstrel_ht_rate_stats	access:public
+sample_slow	smac/ssv_rc_common.h	/^    u8 sample_slow;$/;"	m	struct:ssv62xx_ht	access:public
+sample_slow	smac/ssv_rc_minstrel_ht.h	/^ u8 sample_slow;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+sample_table	smac/ssv_ht_rc.c	/^static u8 sample_table[SAMPLE_COLUMNS][MCS_GROUP_RATES];$/;"	v	file:
+sample_table	smac/ssv_rc_minstrel.h	/^ u8 *sample_table;$/;"	m	struct:ssv_minstrel_sta_priv	access:public
+sample_tries	smac/ssv_rc_common.h	/^    u8 sample_tries;$/;"	m	struct:ssv62xx_ht	access:public
+sample_tries	smac/ssv_rc_minstrel_ht.h	/^ u8 sample_tries;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+sample_wait	smac/ssv_rc_common.h	/^    u8 sample_wait;$/;"	m	struct:ssv62xx_ht	access:public
+sample_wait	smac/ssv_rc_minstrel_ht.h	/^ u8 sample_wait;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+sampling_info	smartlink/qqlink-lib-mipsel/include/TXAudioVideo.h	/^ unsigned int sampling_info;$/;"	m	struct:_tx_audio_encode_param	access:public
+sar_result	include/ssv_cfg.h	/^    u32 sar_result;$/;"	m	struct:ssv6xxx_cfg	access:public
+save_clear_trap_reason	smac/dev.h	/^ void (*save_clear_trap_reason)(struct ssv_softc *sc);$/;"	m	struct:ssv_hal_ops	access:public
+save_default_ipd_chcfg	smac/dev.h	/^    void (*save_default_ipd_chcfg)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+save_hw_status	smac/dev.h	/^    void (*save_hw_status)(struct ssv_softc *sc);$/;"	m	struct:ssv_hal_ops	access:public
+sbands	smac/dev.h	/^    struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::ieee80211_supported_band	access:public
+sbands	smac/dev.h	/^    struct ieee80211_supported_band sbands[NUM_NL80211_BANDS];$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::ieee80211_supported_band	access:public
+sc	hci/ssv_hci.h	/^    struct ssv_softc *sc;$/;"	m	struct:ssv6xxx_hci_info	typeref:struct:ssv6xxx_hci_info::ssv_softc	access:public
+sc	smac/dev.h	/^    struct ssv_softc *sc;$/;"	m	struct:ssv_hw	typeref:struct:ssv_hw::ssv_softc	access:public
+sc_flags	smac/dev.h	/^    u32 sc_flags;$/;"	m	struct:ssv_softc	access:public
+scat_entries	hwif/sdio/sdio_def.h	/^ int scat_entries;$/;"	m	struct:sdio_scatter_req	access:public
+scat_list	hwif/sdio/sdio_def.h	/^ struct sdio_scatter_item scat_list[MAX_SCATTER_ENTRIES_PER_REQ];$/;"	m	struct:sdio_scatter_req	typeref:struct:sdio_scatter_req::sdio_scatter_item	access:public
+sdc_id	platforms/a33-generic-wlan.c	/^static int sdc_id = -1;$/;"	v	file:
+sdio_ops	hwif/sdio/sdio.c	/^static struct ssv6xxx_hwif_ops sdio_ops =$/;"	v	typeref:struct:ssv6xxx_hwif_ops	file:
+sdio_reinit	platforms/aml-s805-generic-wlan.c	/^extern void sdio_reinit(void);$/;"	p	file:	signature:(void)
+sdio_reinit	platforms/aml-s905-generic-wlan.c	/^extern void sdio_reinit(void);$/;"	p	file:	signature:(void)
+sdio_rx_evt_size	smac/dev.h	/^    unsigned long sdio_rx_evt_size;$/;"	m	struct:ssv_softc	access:public
+sdio_rxtput_cfg	include/ssv6xxx_common.h	/^struct sdio_rxtput_cfg {$/;"	s
+sdio_rxtput_cfg::size_per_frame	include/ssv6xxx_common.h	/^    u32 size_per_frame;$/;"	m	struct:sdio_rxtput_cfg	access:public
+sdio_rxtput_cfg::total_frames	include/ssv6xxx_common.h	/^ u32 total_frames;$/;"	m	struct:sdio_rxtput_cfg	access:public
+sdio_scatter_item	hwif/sdio/sdio_def.h	/^struct sdio_scatter_item {$/;"	s
+sdio_scatter_item::buf	hwif/sdio/sdio_def.h	/^ u8 *buf;$/;"	m	struct:sdio_scatter_item	access:public
+sdio_scatter_item::len	hwif/sdio/sdio_def.h	/^ int len;$/;"	m	struct:sdio_scatter_item	access:public
+sdio_scatter_req	hwif/sdio/sdio_def.h	/^struct sdio_scatter_req {$/;"	s
+sdio_scatter_req::len	hwif/sdio/sdio_def.h	/^ u32 len;$/;"	m	struct:sdio_scatter_req	access:public
+sdio_scatter_req::req	hwif/sdio/sdio_def.h	/^ u32 req;$/;"	m	struct:sdio_scatter_req	access:public
+sdio_scatter_req::scat_entries	hwif/sdio/sdio_def.h	/^ int scat_entries;$/;"	m	struct:sdio_scatter_req	access:public
+sdio_scatter_req::scat_list	hwif/sdio/sdio_def.h	/^ struct sdio_scatter_item scat_list[MAX_SCATTER_ENTRIES_PER_REQ];$/;"	m	struct:sdio_scatter_req	typeref:struct:sdio_scatter_req::sdio_scatter_item	access:public
+sdio_scatter_req::sgentries	hwif/sdio/sdio_def.h	/^ struct scatterlist sgentries[MAX_SCATTER_ENTRIES_PER_REQ];$/;"	m	struct:sdio_scatter_req	typeref:struct:sdio_scatter_req::scatterlist	access:public
+sdio_throughput_timestamp	smac/dev.h	/^    unsigned long sdio_throughput_timestamp;$/;"	m	struct:ssv_softc	access:public
+sec_decode_err	smac/hal/ssv6006c/turismo_common.h	/^    u32 sec_decode_err:1;$/;"	m	struct:ssv6006_rx_desc	access:public
+second_try_count	smac/ssv_rc_common.h	/^    int second_try_count;$/;"	m	struct:ssv62xx_ht	access:public
+secondary_channel_clear	smac/ssv_rc_minstrel_ht.h	/^ u32 secondary_channel_clear;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+secondary_edca_mib	smac/dev.h	/^    int secondary_edca_mib;$/;"	m	struct:ssv_softc	access:public
+security	include/ssv6200_common.h	/^    u32 security:1;$/;"	m	struct:ssv6200_tx_desc	access:public
+security	smac/hal/ssv6006c/turismo_common.h	/^    u32 security:1;$/;"	m	struct:ssv6006_tx_desc	access:public
+segment_size	smac/ssv_rc_minstrel.h	/^ unsigned int segment_size;$/;"	m	struct:ssv_minstrel_priv	access:public
+send_tx_poll_cmd	smac/dev.h	/^    void (*send_tx_poll_cmd)(struct ssv_hw *sh, u32 type);$/;"	m	struct:ssv_hal_ops	access:public
+seq	hwif/usb/usb.h	/^ u16 seq;$/;"	m	struct:ssv6xxx_cmd_hdr	access:public
+seq	smartlink/qqlink-lib-mipsel/include/TXDataPoint.h	/^    unsigned int seq;$/;"	m	struct:tag_tx_data_point	access:public
+seq_cntl_mask	smac/sec_wpi.c	/^const u16 seq_cntl_mask = 0x0F00;$/;"	v
+seq_no	include/ssv6200_common.h	/^    u16 seq_no[MAX_AGGR_NUM];$/;"	m	struct:ampdu_ba_notify_data	access:public
+seq_no	smac/dev.h	/^    u16 seq_no;$/;"	m	struct:ssv_tx	access:public
+sequence	hwif/usb/usb.c	/^ u16 sequence;$/;"	m	struct:ssv6xxx_usb_glue	file:	access:public
+server_pub_key	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    char * server_pub_key;$/;"	m	struct:_tx_device_info	access:public
+service	include/ssv6200_common.h	/^    u32 service:16;$/;"	m	struct:ssv6200_rxphy_info	access:public
+service	smac/hal/ssv6006c/turismo_common.h	/^    u32 service:16;$/;"	m	struct:ssv6006_rxphy_info	access:public
+set_80211_hw_rate_config	smac/dev.h	/^ void (*set_80211_hw_rate_config)(struct ssv_softc *sc);$/;"	m	struct:ssv_hal_ops	access:public
+set_aes_tkip_hw_crypto_group_key	smac/dev.h	/^    void (*set_aes_tkip_hw_crypto_group_key) (struct ssv_softc *sc, struct ssv_vif_info *vif_info,$/;"	m	struct:ssv_hal_ops	access:public
+set_ampdu_rx_add_work	smac/dev.h	/^    struct work_struct set_ampdu_rx_add_work;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::work_struct	access:public
+set_ampdu_rx_del_work	smac/dev.h	/^ struct work_struct set_ampdu_rx_del_work;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::work_struct	access:public
+set_beacon_id_dtim	smac/dev.h	/^    void (*set_beacon_id_dtim)(struct ssv_softc *sc,$/;"	m	struct:ssv_hal_ops	access:public
+set_beacon_info	smac/dev.h	/^    void (*set_beacon_info)(struct ssv_hw *sh, u8 beacon_interval, u8 dtim_cnt);$/;"	m	struct:ssv_hal_ops	access:public
+set_beacon_reg_lock	smac/dev.h	/^    void (*set_beacon_reg_lock)(struct ssv_hw *sh, bool val);$/;"	m	struct:ssv_hal_ops	access:public
+set_bssid	smac/dev.h	/^    int (*set_bssid)(struct ssv_hw *sh, u8 *bssid, int vif_idx);$/;"	m	struct:ssv_hal_ops	access:public
+set_carddetect	platforms/a33-generic-wlan.c	/^    int (*set_carddetect)(int val);$/;"	m	struct:wifi_platform_data	file:	access:public
+set_carddetect	platforms/atm7039-action-generic-wlan.c	/^ int (*set_carddetect)(int val);$/;"	m	struct:wifi_platform_data	file:	access:public
+set_carddetect	platforms/h3-generic-wlan.c	/^ int (*set_carddetect)(int val);$/;"	m	struct:wifi_platform_data	file:	access:public
+set_carddetect	platforms/h8-generic-wlan.c	/^ int (*set_carddetect)(int val);$/;"	m	struct:wifi_platform_data	file:	access:public
+set_carddetect	platforms/rk3126-generic-wlan.c	/^    int (*set_carddetect)(int val);$/;"	m	struct:wifi_platform_data	file:	access:public
+set_carddetect	platforms/t10-generic-wlan.c	/^ int (*set_carddetect)(int val);$/;"	m	struct:wifi_platform_data	file:	access:public
+set_carddetect	platforms/x1000-generic-wlan.c	/^ int (*set_carddetect)(int val);$/;"	m	struct:wifi_platform_data	file:	access:public
+set_channel	smac/dev.h	/^    int (*set_channel)(struct ssv_softc *sc, struct ieee80211_channel *channel, enum nl80211_channel_type);$/;"	m	struct:ssv_hal_ops	access:public
+set_dur_burst_sifs_g	smac/dev.h	/^    void (*set_dur_burst_sifs_g)(struct ssv_hw *sh, u32 val);$/;"	m	struct:ssv_hal_ops	access:public
+set_dur_slot	smac/dev.h	/^    void (*set_dur_slot)(struct ssv_hw *sh, u32 val);$/;"	m	struct:ssv_hal_ops	access:public
+set_flags	smac/sec.h	/^ unsigned long (*set_flags) (unsigned long flags, void *priv);$/;"	m	struct:ssv_crypto_ops	access:public
+set_fw_hwwsid_sec_type	smac/dev.h	/^    void (*set_fw_hwwsid_sec_type)(struct ssv_softc *sc, struct ieee80211_sta *sta,$/;"	m	struct:ssv_hal_ops	access:public
+set_group_cipher_type	smac/dev.h	/^    void (*set_group_cipher_type)(struct ssv_hw *sh, struct ssv_vif_priv_data *vif_priv, u8 cipher);$/;"	m	struct:ssv_hal_ops	access:public
+set_halt_mngq_util_dtim	smac/dev.h	/^    void (*set_halt_mngq_util_dtim)(struct ssv_hw *sh, bool val);$/;"	m	struct:ssv_hal_ops	access:public
+set_hw_wsid	smac/dev.h	/^    void (*set_hw_wsid)(struct ssv_softc *sc, struct ieee80211_vif *vif,$/;"	m	struct:ssv_hal_ops	access:public
+set_key	smac/sec.h	/^ int (*set_key) (void *key, int len, u8 * seq, void *priv);$/;"	m	struct:ssv_crypto_ops	access:public
+set_macaddr	smac/dev.h	/^    int (*set_macaddr)(struct ssv_hw *sh, int vif_idx);$/;"	m	struct:ssv_hal_ops	access:public
+set_mrx_mode	smac/dev.h	/^    void (*set_mrx_mode)(struct ssv_hw *sh, u32 regval);$/;"	m	struct:ssv_hal_ops	access:public
+set_on3_enable	smac/dev.h	/^    void (*set_on3_enable)(struct ssv_hw *sh, bool val);$/;"	m	struct:ssv_hal_ops	access:public
+set_op_mode	smac/dev.h	/^    void (*set_op_mode)(struct ssv_hw *sh, u32 opmode, int vif_idx);$/;"	m	struct:ssv_hal_ops	access:public
+set_pairwise_cipher_type	smac/dev.h	/^    void (*set_pairwise_cipher_type)(struct ssv_hw *sh, u8 cipher, u8 wsid);$/;"	m	struct:ssv_hal_ops	access:public
+set_phy_mode	smac/dev.h	/^    void (*set_phy_mode)(struct ssv_hw *sh, bool val);$/;"	m	struct:ssv_hal_ops	access:public
+set_pll_phy_rf	smac/dev.h	/^    int (*set_pll_phy_rf)(struct ssv_hw *sh, ssv_cabrio_reg *rf_tbl, ssv_cabrio_reg *phy_tbl);$/;"	m	struct:ssv_hal_ops	access:public
+set_power	platforms/a33-generic-wlan.c	/^    int (*set_power)(int val);$/;"	m	struct:wifi_platform_data	file:	access:public
+set_power	platforms/atm7039-action-generic-wlan.c	/^ int (*set_power)(int val);$/;"	m	struct:wifi_platform_data	file:	access:public
+set_power	platforms/h3-generic-wlan.c	/^ int (*set_power)(int val);$/;"	m	struct:wifi_platform_data	file:	access:public
+set_power	platforms/h8-generic-wlan.c	/^ int (*set_power)(int val);$/;"	m	struct:wifi_platform_data	file:	access:public
+set_power	platforms/rk3126-generic-wlan.c	/^    int (*set_power)(int val);$/;"	m	struct:wifi_platform_data	file:	access:public
+set_power	platforms/t10-generic-wlan.c	/^ int (*set_power)(int val);$/;"	m	struct:wifi_platform_data	file:	access:public
+set_power	platforms/x1000-generic-wlan.c	/^ int (*set_power)(int val);$/;"	m	struct:wifi_platform_data	file:	access:public
+set_qos_enable	smac/dev.h	/^    void (*set_qos_enable)(struct ssv_hw *sh, bool val);$/;"	m	struct:ssv_hal_ops	access:public
+set_replay_ignore	smac/dev.h	/^    void (*set_replay_ignore)(struct ssv_hw *sh, u8 ignore);$/;"	m	struct:ssv_hal_ops	access:public
+set_reset	platforms/a33-generic-wlan.c	/^    int (*set_reset)(int val);$/;"	m	struct:wifi_platform_data	file:	access:public
+set_reset	platforms/atm7039-action-generic-wlan.c	/^ int (*set_reset)(int val);$/;"	m	struct:wifi_platform_data	file:	access:public
+set_reset	platforms/h3-generic-wlan.c	/^ int (*set_reset)(int val);$/;"	m	struct:wifi_platform_data	file:	access:public
+set_reset	platforms/h8-generic-wlan.c	/^ int (*set_reset)(int val);$/;"	m	struct:wifi_platform_data	file:	access:public
+set_reset	platforms/rk3126-generic-wlan.c	/^    int (*set_reset)(int val);$/;"	m	struct:wifi_platform_data	file:	access:public
+set_reset	platforms/t10-generic-wlan.c	/^ int (*set_reset)(int val);$/;"	m	struct:wifi_platform_data	file:	access:public
+set_reset	platforms/x1000-generic-wlan.c	/^ int (*set_reset)(int val);$/;"	m	struct:wifi_platform_data	file:	access:public
+set_rf_enable	smac/dev.h	/^    bool (*set_rf_enable)(struct ssv_hw *sh, bool val);$/;"	m	struct:ssv_hal_ops	access:public
+set_rx_ba	smac/dev.h	/^    void (*set_rx_ba)(struct ssv_hw *sh, bool on, u8 *ta,$/;"	m	struct:ssv_hal_ops	access:public
+set_rx_ctrl_flow	smac/dev.h	/^    int (*set_rx_ctrl_flow)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+set_rx_flow	smac/dev.h	/^    int (*set_rx_flow)(struct ssv_hw *sh, enum ssv_rx_flow type, u32 rxflow);$/;"	m	struct:ssv_hal_ops	access:public
+set_si_status	smac/kssvsmart.c	/^inline void set_si_status(u32 st)$/;"	f	signature:(u32 st)
+set_si_status	smac/kssvsmart.h	/^inline void set_si_status(u32 st);$/;"	p	signature:(u32 st)
+set_sifs	smac/dev.h	/^    void (*set_sifs)(struct ssv_hw *sh, int band);$/;"	m	struct:ssv_hal_ops	access:public
+set_sram_mode	smac/dev.h	/^ void (*set_sram_mode)(struct ssv_hw *sh, enum SSV_SRAM_MODE mode);$/;"	m	struct:ssv_hal_ops	access:public
+set_tim_work	smac/dev.h	/^    struct work_struct set_tim_work;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::work_struct	access:public
+set_tx_pn	smac/sec.h	/^ int (*set_tx_pn) (u8 * seq, void *priv);$/;"	m	struct:ssv_crypto_ops	access:public
+set_txpwr_work	smac/dev.h	/^    struct work_struct set_txpwr_work;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::work_struct	access:public
+set_usb_lpm	smac/dev.h	/^    void (*set_usb_lpm)(struct ssv_softc *sc, u8 enable);$/;"	m	struct:ssv_hal_ops	access:public
+set_wep_hw_crypto_key	smac/dev.h	/^    void (*set_wep_hw_crypto_key)(struct ssv_softc *sc, struct ssv_sta_info *sta_info, struct ssv_vif_priv_data *vif_priv);$/;"	m	struct:ssv_hal_ops	access:public
+set_wmm_param	smac/dev.h	/^    void (*set_wmm_param)(struct ssv_softc *sc,$/;"	m	struct:ssv_hal_ops	access:public
+setup_wifi_wakeup_BB	platforms/a33-generic-wlan.c	/^void setup_wifi_wakeup_BB(struct platform_device *pdev, bool bEnable)$/;"	f	signature:(struct platform_device *pdev, bool bEnable)
+setup_wifi_wakeup_BB	platforms/atm7039-action-generic-wlan.c	/^void setup_wifi_wakeup_BB(struct platform_device *pdev, bool bEnable)$/;"	f	signature:(struct platform_device *pdev, bool bEnable)
+setup_wifi_wakeup_BB	platforms/h3-generic-wlan.c	/^void setup_wifi_wakeup_BB(struct platform_device *pdev, bool bEnable)$/;"	f	signature:(struct platform_device *pdev, bool bEnable)
+setup_wifi_wakeup_BB	platforms/h8-generic-wlan.c	/^void setup_wifi_wakeup_BB(struct platform_device *pdev, bool bEnable)$/;"	f	signature:(struct platform_device *pdev, bool bEnable)
+setup_wifi_wakeup_BB	platforms/rk3126-generic-wlan.c	/^void setup_wifi_wakeup_BB(void)$/;"	f	signature:(void)
+setup_wifi_wakeup_BB	platforms/t10-generic-wlan.c	/^void setup_wifi_wakeup_BB(struct platform_device *pdev, bool bEnable)$/;"	f	signature:(struct platform_device *pdev, bool bEnable)
+setup_wifi_wakeup_BB	platforms/x1000-generic-wlan.c	/^void setup_wifi_wakeup_BB(struct platform_device *pdev, bool bEnable)$/;"	f	signature:(struct platform_device *pdev, bool bEnable)
+sgentries	hwif/sdio/sdio_def.h	/^ struct scatterlist sgentries[MAX_SCATTER_ENTRIES_PER_REQ];$/;"	m	struct:sdio_scatter_req	typeref:struct:sdio_scatter_req::scatterlist	access:public
+sgi_state	smac/ssv_rc_minstrel_ht.h	/^ u8 sgi_state;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+sgi_state_count	smac/ssv_rc_minstrel_ht.h	/^ u8 sgi_state_count;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+sgi_state_lgi_success	smac/ssv_rc_minstrel_ht.h	/^ u32 sgi_state_lgi_success;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+sgi_state_success	smac/ssv_rc_minstrel_ht.h	/^ u32 sgi_state_success;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+sgi_state_total	smac/ssv_rc_minstrel_ht.h	/^ u32 sgi_state_total;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+sh	hci/ssv_hci.h	/^    struct ssv_hw *sh;$/;"	m	struct:ssv6xxx_hci_info	typeref:struct:ssv6xxx_hci_info::ssv_hw	access:public
+sh	smac/dev.h	/^    struct ssv_hw *sh;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::ssv_hw	access:public
+sh_port	smartlink/qqlink-lib-mipsel/include/TXVoiceLink.h	/^    unsigned short sh_port;$/;"	m	struct:__anon38	access:public
+sh_port	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	/^    unsigned short sh_port;$/;"	m	struct:__anon39	access:public
+sha1_block_data_order	crypto/sha1-armv4-large.S	/^sha1_block_data_order:$/;"	l
+sha1_block_data_order	crypto/sha1_glue.c	/^asmlinkage void sha1_block_data_order(struct SHA1_CTX *digest,$/;"	p	file:	signature:(struct SHA1_CTX *digest, const unsigned char *data, unsigned int rounds)
+sha1_export	crypto/sha1_glue.c	/^static int sha1_export(struct shash_desc *desc, void *out)$/;"	f	file:	signature:(struct shash_desc *desc, void *out)
+sha1_final	crypto/sha1_glue.c	/^static int sha1_final(struct shash_desc *desc, u8 *out)$/;"	f	file:	signature:(struct shash_desc *desc, u8 *out)
+sha1_import	crypto/sha1_glue.c	/^static int sha1_import(struct shash_desc *desc, const void *in)$/;"	f	file:	signature:(struct shash_desc *desc, const void *in)
+sha1_init	crypto/sha1_glue.c	/^static int sha1_init(struct shash_desc *desc)$/;"	f	file:	signature:(struct shash_desc *desc)
+sha1_mod_fini	crypto/sha1_glue.c	/^void sha1_mod_fini(void)$/;"	f	signature:(void)
+sha1_mod_fini	platforms/a33-generic-wlan.c	/^extern void sha1_mod_fini(void);$/;"	p	file:	signature:(void)
+sha1_mod_fini	platforms/aml-s805-generic-wlan.c	/^extern void sha1_mod_fini(void);$/;"	p	file:	signature:(void)
+sha1_mod_fini	platforms/aml-s905-generic-wlan.c	/^extern void sha1_mod_fini(void);$/;"	p	file:	signature:(void)
+sha1_mod_fini	platforms/atm7039-action-generic-wlan.c	/^extern void sha1_mod_fini(void);$/;"	p	file:	signature:(void)
+sha1_mod_fini	platforms/h3-generic-wlan.c	/^extern void sha1_mod_fini(void);$/;"	p	file:	signature:(void)
+sha1_mod_fini	platforms/h8-generic-wlan.c	/^extern void sha1_mod_fini(void);$/;"	p	file:	signature:(void)
+sha1_mod_fini	platforms/rk3036-generic-wlan.c	/^extern void sha1_mod_fini(void);$/;"	p	file:	signature:(void)
+sha1_mod_fini	platforms/rk3126-generic-wlan.c	/^extern void sha1_mod_fini(void);$/;"	p	file:	signature:(void)
+sha1_mod_fini	platforms/rk3128-generic-wlan.c	/^extern void sha1_mod_fini(void);$/;"	p	file:	signature:(void)
+sha1_mod_fini	platforms/rk322x-generic-wlan.c	/^extern void sha1_mod_fini(void);$/;"	p	file:	signature:(void)
+sha1_mod_fini	platforms/t10-generic-wlan.c	/^extern void sha1_mod_fini(void);$/;"	p	file:	signature:(void)
+sha1_mod_fini	platforms/x1000-generic-wlan.c	/^extern void sha1_mod_fini(void);$/;"	p	file:	signature:(void)
+sha1_mod_fini	platforms/xm-hi3518-generic-wlan.c	/^extern void sha1_mod_fini(void);$/;"	p	file:	signature:(void)
+sha1_mod_init	crypto/sha1_glue.c	/^int sha1_mod_init(void)$/;"	f	signature:(void)
+sha1_mod_init	platforms/a33-generic-wlan.c	/^extern int sha1_mod_init(void);$/;"	p	file:	signature:(void)
+sha1_mod_init	platforms/aml-s805-generic-wlan.c	/^extern int sha1_mod_init(void);$/;"	p	file:	signature:(void)
+sha1_mod_init	platforms/aml-s905-generic-wlan.c	/^extern int sha1_mod_init(void);$/;"	p	file:	signature:(void)
+sha1_mod_init	platforms/atm7039-action-generic-wlan.c	/^extern int sha1_mod_init(void);$/;"	p	file:	signature:(void)
+sha1_mod_init	platforms/h3-generic-wlan.c	/^extern int sha1_mod_init(void);$/;"	p	file:	signature:(void)
+sha1_mod_init	platforms/h8-generic-wlan.c	/^extern int sha1_mod_init(void);$/;"	p	file:	signature:(void)
+sha1_mod_init	platforms/rk3036-generic-wlan.c	/^extern int sha1_mod_init(void);$/;"	p	file:	signature:(void)
+sha1_mod_init	platforms/rk3126-generic-wlan.c	/^extern int sha1_mod_init(void);$/;"	p	file:	signature:(void)
+sha1_mod_init	platforms/rk3128-generic-wlan.c	/^extern int sha1_mod_init(void);$/;"	p	file:	signature:(void)
+sha1_mod_init	platforms/rk322x-generic-wlan.c	/^extern int sha1_mod_init(void);$/;"	p	file:	signature:(void)
+sha1_mod_init	platforms/t10-generic-wlan.c	/^extern int sha1_mod_init(void);$/;"	p	file:	signature:(void)
+sha1_mod_init	platforms/x1000-generic-wlan.c	/^extern int sha1_mod_init(void);$/;"	p	file:	signature:(void)
+sha1_mod_init	platforms/xm-hi3518-generic-wlan.c	/^extern int sha1_mod_init(void);$/;"	p	file:	signature:(void)
+sha1_update	crypto/sha1_glue.c	/^static int sha1_update(struct shash_desc *desc, const u8 *data,$/;"	f	file:	signature:(struct shash_desc *desc, const u8 *data, unsigned int len)
+shi	hci/hctrl.h	/^    struct ssv6xxx_hci_info *shi;$/;"	m	struct:ssv6xxx_hci_ctrl	typeref:struct:ssv6xxx_hci_ctrl::ssv6xxx_hci_info	access:public
+short_chip_id	hwif/hwif.h	/^    u8 short_chip_id[SSV6XXX_CHIP_ID_SHORT_LENGTH+1];$/;"	m	struct:ssv6xxx_platform_data	access:public
+si_cfg	smac/kssvsmart.c	/^struct ssv6xxx_si_cfg si_cfg;$/;"	v	typeref:struct:ssv6xxx_si_cfg
+si_st	smac/kssvsmart.c	/^int si_st;$/;"	v
+si_status_st	smac/kssvsmart.c	/^char si_status_st[][16] = {$/;"	v
+sid	smac/hal/ssv6006c/ssv6006_mac.h	/^    u16 sid;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+signature	smac/ampdu.h	/^    u8 signature;$/;"	m	struct:AMPDU_DELIMITER_st	access:public
+single_band_patch	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void single_band_patch(struct ssv_hw *sh, int xtal){$/;"	f	file:	signature:(struct ssv_hw *sh, int xtal)
+size	smac/dev.h	/^ int size;$/;"	m	struct:ssv_dbg_log	access:public
+size	smac/ssv_skb.h	/^    u32 size;$/;"	m	struct:ampdu_hdr_st	access:public
+size_per_frame	include/ssv6xxx_common.h	/^    u32 size_per_frame;$/;"	m	struct:sdio_rxtput_cfg	access:public
+size_per_frame	smac/dev.h	/^    u32 size_per_frame;$/;"	m	struct:_ssv6xxx_txtput	access:public
+skb	smac/dev.h	/^    struct sk_buff *skb;$/;"	m	struct:_ssv6xxx_txtput	typeref:struct:_ssv6xxx_txtput::sk_buff	access:public
+skb_alloc	hci/ssv_hci.h	/^    struct sk_buff *(*skb_alloc) (void *app_param, s32 len);$/;"	m	struct:ssv6xxx_hci_info	typeref:struct:ssv6xxx_hci_info::skb_alloc	access:public
+skb_alloc	hwif/hwif.h	/^    struct sk_buff *(*skb_alloc) (void *param, s32 len, gfp_t gfp_mask);$/;"	m	struct:ssv6xxx_platform_data	typeref:struct:ssv6xxx_platform_data::skb_alloc	access:public
+skb_free	hci/ssv_hci.h	/^    void (*skb_free) (void *app_param, struct sk_buff *skb);$/;"	m	struct:ssv6xxx_hci_info	access:public
+skb_free	hwif/hwif.h	/^    void (*skb_free) (void *param, struct sk_buff *skb);$/;"	m	struct:ssv6xxx_platform_data	access:public
+skb_param	hwif/hwif.h	/^    void *skb_param;$/;"	m	struct:ssv6xxx_platform_data	access:public
+skb_queue_len_bhsafe	hci_wrapper/ssv_huw.c	/^unsigned int skb_queue_len_bhsafe(struct sk_buff_head *head, spinlock_t *plock)$/;"	f	signature:(struct sk_buff_head *head, spinlock_t *plock)
+skb_queue_len_safe	smac/dev.c	/^unsigned int skb_queue_len_safe(struct sk_buff_head *list)$/;"	f	signature:(struct sk_buff_head *list)
+smaricomm_start	smartlink/ssv_smartlink.c	/^int smaricomm_start(void)$/;"	f	signature:(void)
+smaricomm_start	smartlink/ssv_smartlink.h	/^int smaricomm_start(void);$/;"	p	signature:(void)
+smarticomm_get_si_pass	smartlink/ssv_smartlink.c	/^int smarticomm_get_si_pass(uint8_t *pass)$/;"	f	signature:(uint8_t *pass)
+smarticomm_get_si_pass	smartlink/ssv_smartlink.h	/^int smarticomm_get_si_pass(uint8_t *pass);$/;"	p	signature:(uint8_t *pass)
+smarticomm_get_si_ssid	smartlink/ssv_smartlink.c	/^int smarticomm_get_si_ssid(uint8_t *ssid)$/;"	f	signature:(uint8_t *ssid)
+smarticomm_get_si_ssid	smartlink/ssv_smartlink.h	/^int smarticomm_get_si_ssid(uint8_t *ssid);$/;"	p	signature:(uint8_t *ssid)
+smarticomm_get_si_status	smartlink/ssv_smartlink.c	/^int smarticomm_get_si_status(uint8_t *status)$/;"	f	signature:(uint8_t *status)
+smarticomm_get_si_status	smartlink/ssv_smartlink.h	/^int smarticomm_get_si_status(uint8_t *status);$/;"	p	signature:(uint8_t *status)
+smarticomm_set_si_cmd	smartlink/ssv_smartlink.c	/^int smarticomm_set_si_cmd(unsigned int command)$/;"	f	signature:(unsigned int command)
+smarticomm_set_si_cmd	smartlink/ssv_smartlink.h	/^int smarticomm_set_si_cmd(uint32_t command);$/;"	p	signature:(uint32_t command)
+smarticomm_stop	smartlink/ssv_smartlink.c	/^int smarticomm_stop(void)$/;"	f	signature:(void)
+smarticomm_stop	smartlink/ssv_smartlink.h	/^int smarticomm_stop(void);$/;"	p	signature:(void)
+smartlink_nl_send_msg	smac/ksmartlink.c	/^EXPORT_SYMBOL(smartlink_nl_send_msg);$/;"	v
+smartlink_nl_send_msg	smac/ksmartlink.c	/^int smartlink_nl_send_msg(struct sk_buff *skb_in)$/;"	f	signature:(struct sk_buff *skb_in)
+smoothing	include/ssv6200_common.h	/^    u32 smoothing:1;$/;"	m	struct:ssv6200_rxphy_info	access:public
+smoothing	smac/hal/ssv6006c/turismo_common.h	/^    u32 smoothing:1;$/;"	m	struct:ssv6006_rxphy_info	access:public
+snprintf_res	ssvdevice/ssv_cmd.c	/^EXPORT_SYMBOL(snprintf_res);$/;"	v
+snprintf_res	ssvdevice/ssv_cmd.c	/^void snprintf_res(struct ssv_cmd_data *cmd_data, const char *fmt, ... )$/;"	f	signature:(struct ssv_cmd_data *cmd_data, const char *fmt, ... )
+snprintf_res	ssvdevice/ssv_cmd.h	/^void snprintf_res(struct ssv_cmd_data *cmd_data, const char *fmt, ... );$/;"	p	signature:(struct ssv_cmd_data *cmd_data, const char *fmt, ... )
+snr	include/ssv6200_common.h	/^    u32 snr:8;$/;"	m	struct:ssv6200_rxphy_info	access:public
+snr	include/ssv6200_common.h	/^u32 snr:8;$/;"	m	struct:ssv6200_rxphy_info_padding	access:public
+snr	smac/hal/ssv6006c/turismo_common.h	/^    u32 snr:8;$/;"	m	struct:ssv6006_rxphy_info	access:public
+sp_ack_dur	smac/ssv_rc_minstrel.h	/^ unsigned int sp_ack_dur;$/;"	m	struct:ssv_minstrel_sta_info	access:public
+spinfo	smac/ssv_rc_common.h	/^    struct rc_pid_sta_info spinfo;$/;"	m	struct:ssv_sta_rc_info	typeref:struct:ssv_sta_rc_info::rc_pid_sta_info	access:public
+spur_patched	smac/dev.h	/^    bool spur_patched;$/;"	m	struct:ssv6006_padpd	access:public
+spur_patched	smac/hal/ssv6006c/turismo_common.h	/^    u8 spur_patched;$/;"	m	struct:ssv6006_padpd	access:public
+sramKey	smac/dev.h	/^    struct ssv6xxx_hw_sec sramKey;$/;"	m	struct:ssv_vif_info	typeref:struct:ssv_vif_info::ssv6xxx_hw_sec	access:public
+ssid	include/ssv6xxx_common.h	/^    u8 ssid[32];$/;"	m	struct:ssv6xxx_si_cfg	access:public
+ssid	smartlink/airkiss-lib/airkiss.h	/^ char* ssid;$/;"	m	struct:__anon25	access:public
+ssid	smartlink/airkiss-lib/mipsel/airkiss.h	/^ char* ssid;$/;"	m	struct:__anon19	access:public
+ssid	smartlink/airkiss-lib/x64/airkiss.h	/^ char* ssid;$/;"	m	struct:__anon31	access:public
+ssid_len	include/ssv6xxx_common.h	/^    s32 ssid_len;$/;"	m	struct:ssv6xxx_si_cfg	access:public
+ssid_length	smartlink/airkiss-lib/airkiss.h	/^ unsigned char ssid_length;$/;"	m	struct:__anon25	access:public
+ssid_length	smartlink/airkiss-lib/mipsel/airkiss.h	/^ unsigned char ssid_length;$/;"	m	struct:__anon19	access:public
+ssid_length	smartlink/airkiss-lib/x64/airkiss.h	/^ unsigned char ssid_length;$/;"	m	struct:__anon31	access:public
+ssn	smac/dev.h	/^    u16 ssn[MAX_AGGR_NUM];$/;"	m	struct:aggr_ssn	access:public
+ssn	smac/ssv_skb.h	/^    u16 ssn[MAX_AGGR_NUM];$/;"	m	struct:ampdu_hdr_st	access:public
+sso_bid	smartlink/qqlink-lib-mipsel/include/TXOldInf.h	/^    unsigned int sso_bid;$/;"	m	struct:tag_tx_ccmsg_inst_info	access:public
+ssv6006_add_ampdu_txinfo	smac/hal/ssv6006c/ssv6006_phy.c	/^static void ssv6006_add_ampdu_txinfo(struct ssv_softc *sc, struct sk_buff *ampdu_skb)$/;"	f	file:	signature:(struct ssv_softc *sc, struct sk_buff *ampdu_skb)
+ssv6006_add_fw_wsid	smac/hal/ssv6006c/ssv6006_common.c	/^static void ssv6006_add_fw_wsid(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv, struct ieee80211_sta *sta, struct ssv_sta_info *sta_info)
+ssv6006_add_txinfo	smac/hal/ssv6006c/ssv6006_phy.c	/^static void ssv6006_add_txinfo (struct ssv_softc *sc, struct sk_buff *skb)$/;"	f	file:	signature:(struct ssv_softc *sc, struct sk_buff *skb)
+ssv6006_adj_config	smac/hal/ssv6006c/ssv6006_common.c	/^static void ssv6006_adj_config(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006_alloc_hw	smac/hal/ssv6006c/ssv6006_common.c	/^static struct ssv_hw * ssv6006_alloc_hw (void)$/;"	f	file:	signature:(void)
+ssv6006_ampdu_ba_handler	smac/hal/ssv6006c/ssv6006_common.c	/^static void ssv6006_ampdu_ba_handler (struct ieee80211_hw *hw, struct sk_buff *skb,$/;"	f	file:	signature:(struct ieee80211_hw *hw, struct sk_buff *skb, u32 tx_pkt_run_no)
+ssv6006_ampdu_ba_notify	smac/hal/ssv6006c/ssv6006_common.c	/^static void ssv6006_ampdu_ba_notify(struct ssv_softc *sc, struct ieee80211_sta *sta,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ieee80211_sta *sta, u32 pkt_no, int ampdu_len, int ampdu_ack_len)
+ssv6006_ampdu_max_transmit_length	smac/hal/ssv6006c/ssv6006_phy.c	/^int ssv6006_ampdu_max_transmit_length(struct ssv_softc *sc, struct sk_buff *skb, int rate_idx)$/;"	f	signature:(struct ssv_softc *sc, struct sk_buff *skb, int rate_idx)
+ssv6006_ampdu_rx_start	smac/hal/ssv6006c/ssv6006_common.c	/^int ssv6006_ampdu_rx_start(struct ieee80211_hw *hw, struct ieee80211_vif *vif, struct ieee80211_sta *sta,$/;"	f	signature:(struct ieee80211_hw *hw, struct ieee80211_vif *vif, struct ieee80211_sta *sta, u16 tid, u16 *ssn, u8 buf_size)
+ssv6006_ba_map_walker	smac/hal/ssv6006c/ssv6006_common.c	/^static u32 ssv6006_ba_map_walker (struct AMPDU_TID_st *ampdu_tid, u32 start_ssn,$/;"	f	file:	signature:(struct AMPDU_TID_st *ampdu_tid, u32 start_ssn, u32 sn_bit_map[2], u32 *p_acked_num, struct aggr_ssn *ampdu_ssn, struct ssv_softc *sc)
+ssv6006_bss	smac/hal/ssv6006c/ssv6006_mac.h	/^struct ssv6006_bss {$/;"	s
+ssv6006_bss::group_cipher_type	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 group_cipher_type;$/;"	m	struct:ssv6006_bss	access:public
+ssv6006_bss::group_key	smac/hal/ssv6006c/ssv6006_mac.h	/^ struct ssv6006_hw_key group_key[4];$/;"	m	struct:ssv6006_bss	typeref:struct:ssv6006_bss::ssv6006_hw_key	access:public
+ssv6006_bss::group_key_idx	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 group_key_idx;$/;"	m	struct:ssv6006_bss	access:public
+ssv6006_bss::reserve	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 reserve[2];$/;"	m	struct:ssv6006_bss	access:public
+ssv6006_bss::tx_pn_h	smac/hal/ssv6006c/ssv6006_mac.h	/^    u32 tx_pn_h;$/;"	m	struct:ssv6006_bss	access:public
+ssv6006_bss::tx_pn_l	smac/hal/ssv6006c/ssv6006_mac.h	/^    u32 tx_pn_l;$/;"	m	struct:ssv6006_bss	access:public
+ssv6006_cal_result	smac/dev.h	/^struct ssv6006_cal_result{$/;"	s
+ssv6006_cal_result	smac/hal/ssv6006c/turismo_common.h	/^struct ssv6006_cal_result{$/;"	s
+ssv6006_cal_result::cal_done	smac/dev.h	/^    bool cal_done;$/;"	m	struct:ssv6006_cal_result	access:public
+ssv6006_cal_result::cal_done	smac/hal/ssv6006c/turismo_common.h	/^    bool cal_done;$/;"	m	struct:ssv6006_cal_result	access:public
+ssv6006_cal_result::cal_iq_done	smac/dev.h	/^    bool cal_iq_done[PADPDBAND];$/;"	m	struct:ssv6006_cal_result	access:public
+ssv6006_cal_result::cal_iq_done	smac/hal/ssv6006c/turismo_common.h	/^    bool cal_iq_done[PADPDBAND];$/;"	m	struct:ssv6006_cal_result	access:public
+ssv6006_cal_result::rxdc_2g	smac/dev.h	/^    u32 rxdc_2g[21];$/;"	m	struct:ssv6006_cal_result	access:public
+ssv6006_cal_result::rxdc_2g	smac/hal/ssv6006c/turismo_common.h	/^    u32 rxdc_2g[21];$/;"	m	struct:ssv6006_cal_result	access:public
+ssv6006_cal_result::rxdc_5g	smac/dev.h	/^    u32 rxdc_5g[21];$/;"	m	struct:ssv6006_cal_result	access:public
+ssv6006_cal_result::rxdc_5g	smac/hal/ssv6006c/turismo_common.h	/^    u32 rxdc_5g[21];$/;"	m	struct:ssv6006_cal_result	access:public
+ssv6006_cal_result::rxiq_alpha	smac/dev.h	/^    u8 rxiq_alpha[PADPDBAND];$/;"	m	struct:ssv6006_cal_result	access:public
+ssv6006_cal_result::rxiq_alpha	smac/hal/ssv6006c/turismo_common.h	/^    u8 rxiq_alpha[PADPDBAND];$/;"	m	struct:ssv6006_cal_result	access:public
+ssv6006_cal_result::rxiq_theta	smac/dev.h	/^    u8 rxiq_theta[PADPDBAND];$/;"	m	struct:ssv6006_cal_result	access:public
+ssv6006_cal_result::rxiq_theta	smac/hal/ssv6006c/turismo_common.h	/^    u8 rxiq_theta[PADPDBAND];$/;"	m	struct:ssv6006_cal_result	access:public
+ssv6006_cal_result::rxrc_bw20	smac/dev.h	/^    u8 rxrc_bw20;$/;"	m	struct:ssv6006_cal_result	access:public
+ssv6006_cal_result::rxrc_bw20	smac/hal/ssv6006c/turismo_common.h	/^    u8 rxrc_bw20;$/;"	m	struct:ssv6006_cal_result	access:public
+ssv6006_cal_result::rxrc_bw40	smac/dev.h	/^    u8 rxrc_bw40;$/;"	m	struct:ssv6006_cal_result	access:public
+ssv6006_cal_result::rxrc_bw40	smac/hal/ssv6006c/turismo_common.h	/^    u8 rxrc_bw40;$/;"	m	struct:ssv6006_cal_result	access:public
+ssv6006_cal_result::txdc_i_2g	smac/dev.h	/^    u8 txdc_i_2g;$/;"	m	struct:ssv6006_cal_result	access:public
+ssv6006_cal_result::txdc_i_2g	smac/hal/ssv6006c/turismo_common.h	/^    u8 txdc_i_2g;$/;"	m	struct:ssv6006_cal_result	access:public
+ssv6006_cal_result::txdc_i_5g	smac/dev.h	/^    u8 txdc_i_5g;$/;"	m	struct:ssv6006_cal_result	access:public
+ssv6006_cal_result::txdc_i_5g	smac/hal/ssv6006c/turismo_common.h	/^    u8 txdc_i_5g;$/;"	m	struct:ssv6006_cal_result	access:public
+ssv6006_cal_result::txdc_q_2g	smac/dev.h	/^    u8 txdc_q_2g;$/;"	m	struct:ssv6006_cal_result	access:public
+ssv6006_cal_result::txdc_q_2g	smac/hal/ssv6006c/turismo_common.h	/^    u8 txdc_q_2g;$/;"	m	struct:ssv6006_cal_result	access:public
+ssv6006_cal_result::txdc_q_5g	smac/dev.h	/^    u8 txdc_q_5g;$/;"	m	struct:ssv6006_cal_result	access:public
+ssv6006_cal_result::txdc_q_5g	smac/hal/ssv6006c/turismo_common.h	/^    u8 txdc_q_5g;$/;"	m	struct:ssv6006_cal_result	access:public
+ssv6006_cal_result::txiq_alpha	smac/dev.h	/^    u8 txiq_alpha[PADPDBAND];$/;"	m	struct:ssv6006_cal_result	access:public
+ssv6006_cal_result::txiq_alpha	smac/hal/ssv6006c/turismo_common.h	/^    u8 txiq_alpha[PADPDBAND];$/;"	m	struct:ssv6006_cal_result	access:public
+ssv6006_cal_result::txiq_theta	smac/dev.h	/^    u8 txiq_theta[PADPDBAND];$/;"	m	struct:ssv6006_cal_result	access:public
+ssv6006_cal_result::txiq_theta	smac/hal/ssv6006c/turismo_common.h	/^    u8 txiq_theta[PADPDBAND];$/;"	m	struct:ssv6006_cal_result	access:public
+ssv6006_chk_dual_vif_chg_rx_flow	smac/hal/ssv6006c/ssv6006_common.c	/^static void ssv6006_chk_dual_vif_chg_rx_flow(struct ssv_softc *sc,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv)
+ssv6006_chk_if_support_hw_bssid	smac/hal/ssv6006c/ssv6006_common.c	/^static bool ssv6006_chk_if_support_hw_bssid(struct ssv_softc *sc,$/;"	f	file:	signature:(struct ssv_softc *sc, int vif_idx)
+ssv6006_chk_lpbk_rx_rate_desc	smac/hal/ssv6006c/ssv6006_phy.c	/^static int ssv6006_chk_lpbk_rx_rate_desc(struct ssv_hw *sh, struct sk_buff *skb)$/;"	f	file:	signature:(struct ssv_hw *sh, struct sk_buff *skb)
+ssv6006_cmd_cci	smac/hal/ssv6006c/ssv6006_phy.c	/^static void ssv6006_cmd_cci(struct ssv_hw *sh, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_hw *sh, int argc, char *argv[])
+ssv6006_cmd_rc	smac/hal/ssv6006c/ssv6006_phy.c	/^static void ssv6006_cmd_rc(struct ssv_hw *sh, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_hw *sh, int argc, char *argv[])
+ssv6006_cmd_set_hwq_limit	smac/hal/ssv6006c/ssv6006_common.c	/^static void ssv6006_cmd_set_hwq_limit(struct ssv_hw *sh, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_hw *sh, int argc, char *argv[])
+ssv6006_cmd_turismoC_cali	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void ssv6006_cmd_turismoC_cali(struct ssv_hw *sh, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_hw *sh, int argc, char *argv[])
+ssv6006_cmd_turismoC_loopback	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void ssv6006_cmd_turismoC_loopback(struct ssv_hw *sh, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_hw *sh, int argc, char *argv[])
+ssv6006_cmd_turismoC_rf	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void ssv6006_cmd_turismoC_rf(struct ssv_hw *sh, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_hw *sh, int argc, char *argv[])
+ssv6006_cmd_turismoC_txgen	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void ssv6006_cmd_turismoC_txgen(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006_del_fw_wsid	smac/hal/ssv6006c/ssv6006_common.c	/^static void ssv6006_del_fw_wsid(struct ssv_softc *sc, struct ieee80211_sta *sta,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ieee80211_sta *sta, struct ssv_sta_info *sta_info)
+ssv6006_disable_fw_wsid	smac/hal/ssv6006c/ssv6006_common.c	/^static void ssv6006_disable_fw_wsid(struct ssv_softc *sc, int key_idx,$/;"	f	file:	signature:(struct ssv_softc *sc, int key_idx, struct ssv_sta_priv_data *sta_priv, struct ssv_vif_priv_data *vif_priv)
+ssv6006_drword_to_crword	smac/hal/ssv6006c/ssv6006_phy.c	/^static u8 ssv6006_drword_to_crword(struct ssv6006_tx_desc *tx_desc, int idx, enum nl80211_band band)$/;"	f	file:	signature:(struct ssv6006_tx_desc *tx_desc, int idx, enum nl80211_band band)
+ssv6006_dump_mib_rx_phy	smac/hal/ssv6006c/ssv6006_phy.c	/^static void ssv6006_dump_mib_rx_phy(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006_dump_rx_desc	smac/hal/ssv6006c/ssv6006_phy.c	/^static void ssv6006_dump_rx_desc(struct sk_buff *skb)$/;"	f	file:	signature:(struct sk_buff *skb)
+ssv6006_dump_ssv6006_txdesc	smac/hal/ssv6006c/ssv6006_phy.c	/^static void ssv6006_dump_ssv6006_txdesc(struct sk_buff *skb)$/;"	f	file:	signature:(struct sk_buff *skb)
+ssv6006_dump_ssv6006_txframe	smac/hal/ssv6006c/ssv6006_phy.c	/^static void ssv6006_dump_ssv6006_txframe(struct sk_buff *skb)$/;"	f	file:	signature:(struct sk_buff *skb)
+ssv6006_dump_tx_desc	smac/hal/ssv6006c/ssv6006_phy.c	/^static void ssv6006_dump_tx_desc(struct sk_buff *skb)$/;"	f	file:	signature:(struct sk_buff *skb)
+ssv6006_edca_enable	smac/hal/ssv6006c/ssv6006_phy.c	/^static void ssv6006_edca_enable(struct ssv_hw *sh, bool val)$/;"	f	file:	signature:(struct ssv_hw *sh, bool val)
+ssv6006_edca_ewma	smac/hal/ssv6006c/ssv6006_phy.c	/^static u32 ssv6006_edca_ewma(int old, int new)$/;"	f	file:	signature:(int old, int new)
+ssv6006_edca_stat	smac/hal/ssv6006c/ssv6006_phy.c	/^static void ssv6006_edca_stat(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006_enable_fw_wsid	smac/hal/ssv6006c/ssv6006_common.c	/^static void ssv6006_enable_fw_wsid(struct ssv_softc *sc, struct ieee80211_sta *sta,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ieee80211_sta *sta, struct ssv_sta_info *sta_info, enum SSV6XXX_WSID_SEC key_type)
+ssv6006_fill_beacon_tx_desc	smac/hal/ssv6006c/ssv6006_phy.c	/^static void ssv6006_fill_beacon_tx_desc(struct ssv_softc *sc, struct sk_buff* beacon_skb)$/;"	f	file:	signature:(struct ssv_softc *sc, struct sk_buff* beacon_skb)
+ssv6006_fill_lpbk_tx_desc	smac/hal/ssv6006c/ssv6006_phy.c	/^void ssv6006_fill_lpbk_tx_desc(struct sk_buff *skb, int security, unsigned char rate)$/;"	f	signature:(struct sk_buff *skb, int security, unsigned char rate)
+ssv6006_flash_layout_table	smac/hal/ssv6006c/ssv6006_mac.h	/^struct ssv6006_flash_layout_table$/;"	s
+ssv6006_flash_layout_table::RSVD0	smac/hal/ssv6006c/ssv6006_mac.h	/^    u32 RSVD0:8;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+ssv6006_flash_layout_table::RSVD1	smac/hal/ssv6006c/ssv6006_mac.h	/^    u16 RSVD1;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+ssv6006_flash_layout_table::RSVD10	smac/hal/ssv6006c/ssv6006_mac.h	/^    u32 RSVD10;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+ssv6006_flash_layout_table::RSVD11	smac/hal/ssv6006c/ssv6006_mac.h	/^    u32 RSVD11;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+ssv6006_flash_layout_table::RSVD2	smac/hal/ssv6006c/ssv6006_mac.h	/^    u16 RSVD2;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+ssv6006_flash_layout_table::RSVD3	smac/hal/ssv6006c/ssv6006_mac.h	/^    u32 RSVD3;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+ssv6006_flash_layout_table::RSVD4	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 RSVD4;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+ssv6006_flash_layout_table::RSVD5	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 RSVD5;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+ssv6006_flash_layout_table::RSVD6	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 RSVD6;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+ssv6006_flash_layout_table::RSVD7	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 RSVD7;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+ssv6006_flash_layout_table::RSVD8	smac/hal/ssv6006c/ssv6006_mac.h	/^    u16 RSVD8;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+ssv6006_flash_layout_table::RSVD9	smac/hal/ssv6006c/ssv6006_mac.h	/^    u32 RSVD9;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+ssv6006_flash_layout_table::a_band_gain_ht	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 a_band_gain_ht[4];$/;"	m	struct:ssv6006_flash_layout_table	access:public
+ssv6006_flash_layout_table::a_band_gain_lt	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 a_band_gain_lt[4];$/;"	m	struct:ssv6006_flash_layout_table	access:public
+ssv6006_flash_layout_table::a_band_gain_rt	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 a_band_gain_rt[4];$/;"	m	struct:ssv6006_flash_layout_table	access:public
+ssv6006_flash_layout_table::a_band_pa_bias0	smac/hal/ssv6006c/ssv6006_mac.h	/^    u32 a_band_pa_bias0;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+ssv6006_flash_layout_table::a_band_pa_bias1	smac/hal/ssv6006c/ssv6006_mac.h	/^    u32 a_band_pa_bias1;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+ssv6006_flash_layout_table::band_gain_high_boundary	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 band_gain_high_boundary;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+ssv6006_flash_layout_table::band_gain_low_boundary	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 band_gain_low_boundary;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+ssv6006_flash_layout_table::date	smac/hal/ssv6006c/ssv6006_mac.h	/^    u32 date;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+ssv6006_flash_layout_table::dcdc	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 dcdc;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+ssv6006_flash_layout_table::g_band_gain_ht	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 g_band_gain_ht[7];$/;"	m	struct:ssv6006_flash_layout_table	access:public
+ssv6006_flash_layout_table::g_band_gain_lt	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 g_band_gain_lt[7];$/;"	m	struct:ssv6006_flash_layout_table	access:public
+ssv6006_flash_layout_table::g_band_gain_rt	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 g_band_gain_rt[7];$/;"	m	struct:ssv6006_flash_layout_table	access:public
+ssv6006_flash_layout_table::g_band_pa_bias0	smac/hal/ssv6006c/ssv6006_mac.h	/^    u32 g_band_pa_bias0;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+ssv6006_flash_layout_table::g_band_pa_bias1	smac/hal/ssv6006c/ssv6006_mac.h	/^    u32 g_band_pa_bias1;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+ssv6006_flash_layout_table::ic	smac/hal/ssv6006c/ssv6006_mac.h	/^    u16 ic;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+ssv6006_flash_layout_table::padpd	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 padpd;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+ssv6006_flash_layout_table::rate_delta	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 rate_delta[13];$/;"	m	struct:ssv6006_flash_layout_table	access:public
+ssv6006_flash_layout_table::sid	smac/hal/ssv6006c/ssv6006_mac.h	/^    u16 sid;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+ssv6006_flash_layout_table::version	smac/hal/ssv6006c/ssv6006_mac.h	/^    u32 version:24;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+ssv6006_flash_layout_table::xtal_offset_high_boundary	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 xtal_offset_high_boundary;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+ssv6006_flash_layout_table::xtal_offset_ht_config	smac/hal/ssv6006c/ssv6006_mac.h	/^    u16 xtal_offset_ht_config;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+ssv6006_flash_layout_table::xtal_offset_low_boundary	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 xtal_offset_low_boundary;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+ssv6006_flash_layout_table::xtal_offset_lt_config	smac/hal/ssv6006c/ssv6006_mac.h	/^    u16 xtal_offset_lt_config;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+ssv6006_flash_layout_table::xtal_offset_rt_config	smac/hal/ssv6006c/ssv6006_mac.h	/^    u16 xtal_offset_rt_config;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+ssv6006_flash_read_all_map	smac/hal/ssv6006c/ssv6006_common.c	/^static void ssv6006_flash_read_all_map(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006_force_lowest_rate	smac/hal/ssv6006c/ssv6006_phy.c	/^static void ssv6006_force_lowest_rate(struct ieee80211_tx_info *info,$/;"	f	file:	signature:(struct ieee80211_tx_info *info, struct ssv6006_tx_desc *tx_desc, struct ssv6006_rc_idx *drate_idx)
+ssv6006_get_data_rates	smac/hal/ssv6006c/ssv6006_phy.c	/^static u32 ssv6006_get_data_rates(struct ssv6006_rc_idx *rc_word)$/;"	f	file:	signature:(struct ssv6006_rc_idx *rc_word)
+ssv6006_get_fw_name	smac/hal/ssv6006c/ssv6006_common.c	/^static void ssv6006_get_fw_name(u8 *fw_name)$/;"	f	file:	signature:(u8 *fw_name)
+ssv6006_get_pa_band	smac/hal/ssv6006c/ssv6006_priv.h	/^int ssv6006_get_pa_band(int ch);$/;"	p	signature:(int ch)
+ssv6006_get_pa_band	smac/hal/ssv6006c/turismo_common.c	/^int ssv6006_get_pa_band(int ch)$/;"	f	signature:(int ch)
+ssv6006_get_pa_band	smac/hal/ssv6006c/turismo_common.h	/^extern int ssv6006_get_pa_band(int ch);$/;"	p	signature:(int ch)
+ssv6006_get_rx_desc_ctype	smac/hal/ssv6006c/ssv6006_phy.c	/^static u32 ssv6006_get_rx_desc_ctype(struct sk_buff *skb)$/;"	f	file:	signature:(struct sk_buff *skb)
+ssv6006_get_rx_desc_hdr_offset	smac/hal/ssv6006c/ssv6006_phy.c	/^static int ssv6006_get_rx_desc_hdr_offset(struct sk_buff *skb)$/;"	f	file:	signature:(struct sk_buff *skb)
+ssv6006_get_rx_desc_info	smac/hal/ssv6006c/ssv6006_phy.c	/^static void ssv6006_get_rx_desc_info(struct sk_buff *skb, u32 *packet_len, u32 *c_type,$/;"	f	file:	signature:(struct sk_buff *skb, u32 *packet_len, u32 *c_type, u32 *tx_pkt_run_no)
+ssv6006_get_rx_desc_length	smac/hal/ssv6006c/ssv6006_phy.c	/^static int ssv6006_get_rx_desc_length(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006_get_rx_desc_mng_used	smac/hal/ssv6006c/ssv6006_phy.c	/^static u32 ssv6006_get_rx_desc_mng_used(struct sk_buff *skb)$/;"	f	file:	signature:(struct sk_buff *skb)
+ssv6006_get_rx_desc_rate_idx	smac/hal/ssv6006c/ssv6006_phy.c	/^static u32 ssv6006_get_rx_desc_rate_idx(struct sk_buff *skb)$/;"	f	file:	signature:(struct sk_buff *skb)
+ssv6006_get_rx_desc_size	smac/hal/ssv6006c/ssv6006_phy.c	/^static int ssv6006_get_rx_desc_size(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006_get_rx_desc_wsid	smac/hal/ssv6006c/ssv6006_phy.c	/^static u32 ssv6006_get_rx_desc_wsid(struct sk_buff *skb)$/;"	f	file:	signature:(struct sk_buff *skb)
+ssv6006_get_sec_decode_err	smac/hal/ssv6006c/ssv6006_phy.c	/^static int ssv6006_get_sec_decode_err(struct sk_buff *skb, bool *mic_err, bool *decode_err)$/;"	f	file:	signature:(struct sk_buff *skb, bool *mic_err, bool *decode_err)
+ssv6006_get_tx_desc_ctype	smac/hal/ssv6006c/ssv6006_phy.c	/^static int ssv6006_get_tx_desc_ctype(struct sk_buff *skb)$/;"	f	file:	signature:(struct sk_buff *skb)
+ssv6006_get_tx_desc_drate	smac/hal/ssv6006c/ssv6006_phy.c	/^static u8 ssv6006_get_tx_desc_drate(struct ssv6006_tx_desc *tx_desc, int idx)$/;"	f	file:	signature:(struct ssv6006_tx_desc *tx_desc, int idx)
+ssv6006_get_tx_desc_last_rate	smac/hal/ssv6006c/ssv6006_phy.c	/^static bool ssv6006_get_tx_desc_last_rate(struct ssv6006_tx_desc *tx_desc, int idx)$/;"	f	file:	signature:(struct ssv6006_tx_desc *tx_desc, int idx)
+ssv6006_get_tx_desc_rate_rpt	smac/hal/ssv6006c/ssv6006_phy.c	/^static int ssv6006_get_tx_desc_rate_rpt(struct ssv_softc *sc, struct ssv6006_tx_desc *tx_desc,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ssv6006_tx_desc *tx_desc, int idx, u8 *drate, u8 *success, u8 *trycnt)
+ssv6006_get_tx_desc_reason	smac/hal/ssv6006c/ssv6006_phy.c	/^static int ssv6006_get_tx_desc_reason(struct sk_buff *skb)$/;"	f	file:	signature:(struct sk_buff *skb)
+ssv6006_get_tx_desc_size	smac/hal/ssv6006c/ssv6006_phy.c	/^static int ssv6006_get_tx_desc_size(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006_get_tx_desc_txq_idx	smac/hal/ssv6006c/ssv6006_phy.c	/^static int ssv6006_get_tx_desc_txq_idx(struct sk_buff *skb)$/;"	f	file:	signature:(struct sk_buff *skb)
+ssv6006_get_wsid	smac/hal/ssv6006c/ssv6006_common.c	/^static int ssv6006_get_wsid(struct ssv_softc *sc, struct ieee80211_vif *vif,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ieee80211_vif *vif, struct ieee80211_sta *sta)
+ssv6006_group_wpa_use_hw_cipher	smac/hal/ssv6006c/ssv6006_common.c	/^static bool ssv6006_group_wpa_use_hw_cipher(struct ssv_softc *sc,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv, enum SSV_CIPHER_E cipher)
+ssv6006_hw_crypto_key_write_wep	smac/hal/ssv6006c/ssv6006_common.c	/^static int ssv6006_hw_crypto_key_write_wep(struct ssv_softc *sc,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ieee80211_key_conf *keyconf, u8 algorithm, struct ssv_vif_info *vif_info)
+ssv6006_hw_key	smac/hal/ssv6006c/ssv6006_mac.h	/^struct ssv6006_hw_key {$/;"	s
+ssv6006_hw_key::key	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 key[SSV6006_SECURITY_KEY_LEN];$/;"	m	struct:ssv6006_hw_key	access:public
+ssv6006_hw_sec	smac/hal/ssv6006c/ssv6006_mac.h	/^struct ssv6006_hw_sec {$/;"	s
+ssv6006_hw_sec::bss_group	smac/hal/ssv6006c/ssv6006_mac.h	/^    struct ssv6006_bss bss_group[2];$/;"	m	struct:ssv6006_hw_sec	typeref:struct:ssv6006_hw_sec::ssv6006_bss	access:public
+ssv6006_hw_sec::sta_key	smac/hal/ssv6006c/ssv6006_mac.h	/^    struct ssv6006_hw_sta_key sta_key[8];$/;"	m	struct:ssv6006_hw_sec	typeref:struct:ssv6006_hw_sec::ssv6006_hw_sta_key	access:public
+ssv6006_hw_sta_key	smac/hal/ssv6006c/ssv6006_mac.h	/^struct ssv6006_hw_sta_key {$/;"	s
+ssv6006_hw_sta_key::pair	smac/hal/ssv6006c/ssv6006_mac.h	/^    struct ssv6006_hw_key pair;$/;"	m	struct:ssv6006_hw_sta_key	typeref:struct:ssv6006_hw_sta_key::ssv6006_hw_key	access:public
+ssv6006_hw_sta_key::pair_cipher_type	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 pair_cipher_type;$/;"	m	struct:ssv6006_hw_sta_key	access:public
+ssv6006_hw_sta_key::pair_key_idx	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 pair_key_idx;$/;"	m	struct:ssv6006_hw_sta_key	access:public
+ssv6006_hw_sta_key::reserve	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 reserve[1];$/;"	m	struct:ssv6006_hw_sta_key	access:public
+ssv6006_hw_sta_key::tx_pn_h	smac/hal/ssv6006c/ssv6006_mac.h	/^    u32 tx_pn_h;$/;"	m	struct:ssv6006_hw_sta_key	access:public
+ssv6006_hw_sta_key::tx_pn_l	smac/hal/ssv6006c/ssv6006_mac.h	/^    u32 tx_pn_l;$/;"	m	struct:ssv6006_hw_sta_key	access:public
+ssv6006_hw_sta_key::valid	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 valid;$/;"	m	struct:ssv6006_hw_sta_key	access:public
+ssv6006_if_chk_mac2	smac/hal/ssv6006c/ssv6006_common.c	/^static bool ssv6006_if_chk_mac2(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006_init_rx_cfg	smac/hal/ssv6006c/ssv6006_common.c	/^static void ssv6006_init_rx_cfg(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006_init_tx_cfg	smac/hal/ssv6006c/ssv6006_common.c	/^static void ssv6006_init_tx_cfg(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006_is_legacy_rate	smac/hal/ssv6006c/ssv6006_phy.c	/^bool ssv6006_is_legacy_rate(struct ssv_softc *sc, struct sk_buff *skb)$/;"	f	signature:(struct ssv_softc *sc, struct sk_buff *skb)
+ssv6006_is_rx_aggr	smac/hal/ssv6006c/ssv6006_phy.c	/^static bool ssv6006_is_rx_aggr(struct sk_buff *skb)$/;"	f	file:	signature:(struct sk_buff *skb)
+ssv6006_lpbk_sec	smac/hal/ssv6006c/ssv6006_mac.h	/^enum ssv6006_lpbk_sec {$/;"	g
+ssv6006_lpbk_type	smac/hal/ssv6006c/ssv6006_mac.h	/^enum ssv6006_lpbk_type {$/;"	g
+ssv6006_need_sw_cipher	smac/hal/ssv6006c/ssv6006_common.c	/^static bool ssv6006_need_sw_cipher(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006_nullfun_frame_filter	smac/hal/ssv6006c/ssv6006_phy.c	/^static bool ssv6006_nullfun_frame_filter(struct sk_buff *skb)$/;"	f	file:	signature:(struct sk_buff *skb)
+ssv6006_padpd	smac/dev.h	/^struct ssv6006_padpd{$/;"	s
+ssv6006_padpd	smac/hal/ssv6006c/turismo_common.h	/^struct ssv6006_padpd{$/;"	s
+ssv6006_padpd::bbscale	smac/dev.h	/^    u8 bbscale[PADPDBAND];$/;"	m	struct:ssv6006_padpd	access:public
+ssv6006_padpd::bbscale	smac/hal/ssv6006c/turismo_common.h	/^    u8 bbscale[PADPDBAND];$/;"	m	struct:ssv6006_padpd	access:public
+ssv6006_padpd::current_band	smac/dev.h	/^    u8 current_band;$/;"	m	struct:ssv6006_padpd	access:public
+ssv6006_padpd::current_band	smac/hal/ssv6006c/turismo_common.h	/^    u8 current_band;$/;"	m	struct:ssv6006_padpd	access:public
+ssv6006_padpd::dpd_disable	smac/dev.h	/^    bool dpd_disable[PADPDBAND];$/;"	m	struct:ssv6006_padpd	access:public
+ssv6006_padpd::dpd_disable	smac/hal/ssv6006c/turismo_common.h	/^    bool dpd_disable[PADPDBAND];$/;"	m	struct:ssv6006_padpd	access:public
+ssv6006_padpd::dpd_done	smac/dev.h	/^    bool dpd_done[PADPDBAND];$/;"	m	struct:ssv6006_padpd	access:public
+ssv6006_padpd::dpd_done	smac/hal/ssv6006c/turismo_common.h	/^    bool dpd_done[PADPDBAND];$/;"	m	struct:ssv6006_padpd	access:public
+ssv6006_padpd::pwr_mode	smac/dev.h	/^    bool pwr_mode;$/;"	m	struct:ssv6006_padpd	access:public
+ssv6006_padpd::pwr_mode	smac/hal/ssv6006c/turismo_common.h	/^    bool pwr_mode;$/;"	m	struct:ssv6006_padpd	access:public
+ssv6006_padpd::spur_patched	smac/dev.h	/^    bool spur_patched;$/;"	m	struct:ssv6006_padpd	access:public
+ssv6006_padpd::spur_patched	smac/hal/ssv6006c/turismo_common.h	/^    u8 spur_patched;$/;"	m	struct:ssv6006_padpd	access:public
+ssv6006_padpd::val	smac/dev.h	/^    struct ssv6006dpd val[PADPDBAND];$/;"	m	struct:ssv6006_padpd	typeref:struct:ssv6006_padpd::ssv6006dpd	access:public
+ssv6006_padpd::val	smac/hal/ssv6006c/turismo_common.h	/^    struct ssv6006dpd val[PADPDBAND];$/;"	m	struct:ssv6006_padpd	typeref:struct:ssv6006_padpd::ssv6006dpd	access:public
+ssv6006_pairwise_wpa_use_hw_cipher	smac/hal/ssv6006c/ssv6006_common.c	/^static bool ssv6006_pairwise_wpa_use_hw_cipher(struct ssv_softc *sc,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv, enum SSV_CIPHER_E cipher, struct ssv_sta_priv_data *sta_priv)
+ssv6006_patch	smac/hal/ssv6006c/turismo_common.h	/^struct ssv6006_patch{$/;"	s
+ssv6006_patch::cpu_clk	smac/hal/ssv6006c/turismo_common.h	/^    u16 cpu_clk;$/;"	m	struct:ssv6006_patch	access:public
+ssv6006_patch::dcdc	smac/hal/ssv6006c/turismo_common.h	/^    bool dcdc;$/;"	m	struct:ssv6006_patch	access:public
+ssv6006_patch::xtal	smac/hal/ssv6006c/turismo_common.h	/^    u16 xtal;$/;"	m	struct:ssv6006_patch	access:public
+ssv6006_phy_enable	smac/hal/ssv6006c/ssv6006_phy.c	/^static void ssv6006_phy_enable(struct ssv_hw *sh, bool val)$/;"	f	file:	signature:(struct ssv_hw *sh, bool val)
+ssv6006_put_mic_space_for_hw_ccmp_encrypt	smac/hal/ssv6006c/ssv6006_common.c	/^static bool ssv6006_put_mic_space_for_hw_ccmp_encrypt(struct ssv_softc *sc, struct sk_buff *skb)$/;"	f	file:	signature:(struct ssv_softc *sc, struct sk_buff *skb)
+ssv6006_rate_report_filter	smac/hal/ssv6006c/ssv6006_phy.c	/^static bool ssv6006_rate_report_filter(struct ssv_softc *sc, struct sk_buff *skb)$/;"	f	file:	signature:(struct ssv_softc *sc, struct sk_buff *skb)
+ssv6006_rate_report_handler	smac/hal/ssv6006c/ssv6006_phy.c	/^static void ssv6006_rate_report_handler(struct ssv_softc *sc, struct sk_buff *skb, bool *no_ba_result)$/;"	f	file:	signature:(struct ssv_softc *sc, struct sk_buff *skb, bool *no_ba_result)
+ssv6006_rate_report_nullfunc_handler	smac/hal/ssv6006c/ssv6006_phy.c	/^static void ssv6006_rate_report_nullfunc_handler(struct ssv_softc *sc, struct sk_buff *skb)$/;"	f	file:	signature:(struct ssv_softc *sc, struct sk_buff *skb)
+ssv6006_rc_add_ampdu_rpt_to_list	smac/hal/ssv6006c/ssv6006_phy.c	/^void ssv6006_rc_add_ampdu_rpt_to_list(struct ssv_softc *sc, struct ssv_minstrel_ht_sta *mhs, void *rate_rpt,$/;"	f	signature:(struct ssv_softc *sc, struct ssv_minstrel_ht_sta *mhs, void *rate_rpt, int pkt_no, int ampdu_len, int ampdu_ack_len)
+ssv6006_rc_add_ampdu_rpt_to_list	smac/hal/ssv6006c/ssv6006_priv.h	/^void ssv6006_rc_add_ampdu_rpt_to_list(struct ssv_softc *sc, struct ssv_minstrel_ht_sta *mhs, void *rate_rpt,$/;"	p	signature:(struct ssv_softc *sc, struct ssv_minstrel_ht_sta *mhs, void *rate_rpt, int pkt_no, int ampdu_len, int ampdu_ack_len)
+ssv6006_rc_algorithm	smac/hal/ssv6006c/ssv6006_phy.c	/^static void ssv6006_rc_algorithm(struct ssv_softc *sc)$/;"	f	file:	signature:(struct ssv_softc *sc)
+ssv6006_rc_ba_handler	smac/hal/ssv6006c/ssv6006_phy.c	/^static void ssv6006_rc_ba_handler(struct ssv_softc *sc, void *rate_rpt, u32 wsid)$/;"	f	file:	signature:(struct ssv_softc *sc, void *rate_rpt, u32 wsid)
+ssv6006_rc_get_previous_ampdu_rpt	smac/hal/ssv6006c/ssv6006_phy.c	/^bool ssv6006_rc_get_previous_ampdu_rpt(struct ssv_minstrel_ht_sta *mhs, int pkt_no, int *rpt_idx)$/;"	f	signature:(struct ssv_minstrel_ht_sta *mhs, int pkt_no, int *rpt_idx)
+ssv6006_rc_get_previous_ampdu_rpt	smac/hal/ssv6006c/ssv6006_priv.h	/^bool ssv6006_rc_get_previous_ampdu_rpt(struct ssv_minstrel_ht_sta *mhs, int pkt_no, int *rpt_idx);$/;"	p	signature:(struct ssv_minstrel_ht_sta *mhs, int pkt_no, int *rpt_idx)
+ssv6006_rc_ht_sta_current_rate_is_cck	smac/hal/ssv6006c/ssv6006_phy.c	/^bool ssv6006_rc_ht_sta_current_rate_is_cck(struct ieee80211_sta *sta)$/;"	f	signature:(struct ieee80211_sta *sta)
+ssv6006_rc_ht_update_rate	smac/hal/ssv6006c/ssv6006_phy.c	/^s32 ssv6006_rc_ht_update_rate(struct sk_buff *skb, struct ssv_softc *sc, struct fw_rc_retry_params *ar)$/;"	f	signature:(struct sk_buff *skb, struct ssv_softc *sc, struct fw_rc_retry_params *ar)
+ssv6006_rc_idx	smac/hal/ssv6006c/ssv6006_mac.h	/^struct ssv6006_rc_idx$/;"	s
+ssv6006_rc_idx::ht40	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 ht40:1;$/;"	m	struct:ssv6006_rc_idx	access:public
+ssv6006_rc_idx::long_short	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 long_short:1;$/;"	m	struct:ssv6006_rc_idx	access:public
+ssv6006_rc_idx::mf	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 mf:1;$/;"	m	struct:ssv6006_rc_idx	access:public
+ssv6006_rc_idx::phy_mode	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 phy_mode:2;$/;"	m	struct:ssv6006_rc_idx	access:public
+ssv6006_rc_idx::rate_idx	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 rate_idx:3;$/;"	m	struct:ssv6006_rc_idx	access:public
+ssv6006_rc_legacy_bitrate_to_rate_desc	smac/hal/ssv6006c/ssv6006_phy.c	/^void ssv6006_rc_legacy_bitrate_to_rate_desc(int bitrate, u8 *drate)$/;"	f	signature:(int bitrate, u8 *drate)
+ssv6006_rc_legacy_drate_to_ndx	smac/hal/ssv6006c/ssv6006_phy.c	/^static int ssv6006_rc_legacy_drate_to_ndx(struct ssv_minstrel_sta_priv *minstrel_sta_priv, u8 drate)$/;"	f	file:	signature:(struct ssv_minstrel_sta_priv *minstrel_sta_priv, u8 drate)
+ssv6006_rc_mac80211_rate_idx	smac/hal/ssv6006c/ssv6006_phy.c	/^void ssv6006_rc_mac80211_rate_idx(struct ssv_softc *sc,$/;"	f	signature:(struct ssv_softc *sc, int hw_rate_idx, struct ieee80211_rx_status *rxs)
+ssv6006_rc_no_ba_handler	smac/hal/ssv6006c/ssv6006_phy.c	/^static void ssv6006_rc_no_ba_handler(struct ssv_softc *sc, struct sk_buff *report)$/;"	f	file:	signature:(struct ssv_softc *sc, struct sk_buff *report)
+ssv6006_rc_process_rate_report	smac/hal/ssv6006c/ssv6006_phy.c	/^static void ssv6006_rc_process_rate_report(struct ssv_softc *sc, struct sk_buff *skb)$/;"	f	file:	signature:(struct ssv_softc *sc, struct sk_buff *skb)
+ssv6006_rc_rx_data_handler	smac/hal/ssv6006c/ssv6006_phy.c	/^static void ssv6006_rc_rx_data_handler(struct ssv_softc *sc, struct sk_buff *skb, u32 rate_index)$/;"	f	file:	signature:(struct ssv_softc *sc, struct sk_buff *skb, u32 rate_index)
+ssv6006_rc_update_basic_rate	smac/hal/ssv6006c/ssv6006_phy.c	/^static void ssv6006_rc_update_basic_rate(struct ssv_softc *sc, u32 basic_rates)$/;"	f	file:	signature:(struct ssv_softc *sc, u32 basic_rates)
+ssv6006_recover_scan_cci_setting	smac/hal/ssv6006c/ssv6006_phy.c	/^void ssv6006_recover_scan_cci_setting(struct ssv_softc *sc)$/;"	f	signature:(struct ssv_softc *sc)
+ssv6006_reset_mib_phy	smac/hal/ssv6006c/ssv6006_phy.c	/^static void ssv6006_reset_mib_phy(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006_restore_rx_flow	smac/hal/ssv6006c/ssv6006_common.c	/^static void ssv6006_restore_rx_flow(struct ssv_softc *sc,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv, struct ieee80211_sta *sta)
+ssv6006_rx_desc	smac/hal/ssv6006c/turismo_common.h	/^struct ssv6006_rx_desc$/;"	s
+ssv6006_rx_desc::RxResult	smac/hal/ssv6006c/turismo_common.h	/^    u32 RxResult:8;$/;"	m	struct:ssv6006_rx_desc	access:public
+ssv6006_rx_desc::__anon1::fCmd	smac/hal/ssv6006c/turismo_common.h	/^        u32 fCmd;$/;"	m	union:ssv6006_rx_desc::__anon1	access:public
+ssv6006_rx_desc::bssid	smac/hal/ssv6006c/turismo_common.h	/^    u32 bssid:2;$/;"	m	struct:ssv6006_rx_desc	access:public
+ssv6006_rx_desc::c_type	smac/hal/ssv6006c/turismo_common.h	/^    u32 c_type:3;$/;"	m	struct:ssv6006_rx_desc	access:public
+ssv6006_rx_desc::channel	smac/hal/ssv6006c/turismo_common.h	/^    u32 channel:8;$/;"	m	struct:ssv6006_rx_desc	access:public
+ssv6006_rx_desc::f80211	smac/hal/ssv6006c/turismo_common.h	/^    u32 f80211:1;$/;"	m	struct:ssv6006_rx_desc	access:public
+ssv6006_rx_desc::fCmdIdx	smac/hal/ssv6006c/turismo_common.h	/^    u32 fCmdIdx:3;$/;"	m	struct:ssv6006_rx_desc	access:public
+ssv6006_rx_desc::frag	smac/hal/ssv6006c/turismo_common.h	/^    u32 frag:1;$/;"	m	struct:ssv6006_rx_desc	access:public
+ssv6006_rx_desc::hdr_len	smac/hal/ssv6006c/turismo_common.h	/^    u32 hdr_len:6;$/;"	m	struct:ssv6006_rx_desc	access:public
+ssv6006_rx_desc::hdr_offset	smac/hal/ssv6006c/turismo_common.h	/^    u32 hdr_offset:8;$/;"	m	struct:ssv6006_rx_desc	access:public
+ssv6006_rx_desc::ht	smac/hal/ssv6006c/turismo_common.h	/^    u32 ht:1;$/;"	m	struct:ssv6006_rx_desc	access:public
+ssv6006_rx_desc::len	smac/hal/ssv6006c/turismo_common.h	/^    u32 len:16;$/;"	m	struct:ssv6006_rx_desc	access:public
+ssv6006_rx_desc::psm	smac/hal/ssv6006c/turismo_common.h	/^    u32 psm:1;$/;"	m	struct:ssv6006_rx_desc	access:public
+ssv6006_rx_desc::qos	smac/hal/ssv6006c/turismo_common.h	/^    u32 qos:1;$/;"	m	struct:ssv6006_rx_desc	access:public
+ssv6006_rx_desc::reason	smac/hal/ssv6006c/turismo_common.h	/^    u32 reason:6;$/;"	m	struct:ssv6006_rx_desc	access:public
+ssv6006_rx_desc::rsvd_rx_3b	smac/hal/ssv6006c/turismo_common.h	/^    u32 rsvd_rx_3b:8;$/;"	m	struct:ssv6006_rx_desc	access:public
+ssv6006_rx_desc::rsvdrx0_1	smac/hal/ssv6006c/turismo_common.h	/^    u32 rsvdrx0_1:1;$/;"	m	struct:ssv6006_rx_desc	access:public
+ssv6006_rx_desc::running_no	smac/hal/ssv6006c/turismo_common.h	/^    u32 running_no:4;$/;"	m	struct:ssv6006_rx_desc	access:public
+ssv6006_rx_desc::rx_pkt_run_no	smac/hal/ssv6006c/turismo_common.h	/^    u32 rx_pkt_run_no:8;$/;"	m	struct:ssv6006_rx_desc	access:public
+ssv6006_rx_desc::sec_decode_err	smac/hal/ssv6006c/turismo_common.h	/^    u32 sec_decode_err:1;$/;"	m	struct:ssv6006_rx_desc	access:public
+ssv6006_rx_desc::stype_b5b4	smac/hal/ssv6006c/turismo_common.h	/^    u32 stype_b5b4:2;$/;"	m	struct:ssv6006_rx_desc	access:public
+ssv6006_rx_desc::tkip_mmic_err	smac/hal/ssv6006c/turismo_common.h	/^    u32 tkip_mmic_err:1;$/;"	m	struct:ssv6006_rx_desc	access:public
+ssv6006_rx_desc::unicast	smac/hal/ssv6006c/turismo_common.h	/^    u32 unicast:1;$/;"	m	struct:ssv6006_rx_desc	access:public
+ssv6006_rx_desc::use_4addr	smac/hal/ssv6006c/turismo_common.h	/^    u32 use_4addr:1;$/;"	m	struct:ssv6006_rx_desc	access:public
+ssv6006_rx_desc::wsid	smac/hal/ssv6006c/turismo_common.h	/^    u32 wsid:4;$/;"	m	struct:ssv6006_rx_desc	access:public
+ssv6006_rx_desc_length	smac/hal/ssv6006c/ssv6006_phy.c	/^const size_t ssv6006_rx_desc_length = sizeof(struct ssv6006_rx_desc) + sizeof (struct ssv6006_rxphy_info);$/;"	v
+ssv6006_rxphy_info	smac/hal/ssv6006c/turismo_common.h	/^struct ssv6006_rxphy_info {$/;"	s
+ssv6006_rxphy_info::aggregate	smac/hal/ssv6006c/turismo_common.h	/^    u32 aggregate:1;$/;"	m	struct:ssv6006_rxphy_info	access:public
+ssv6006_rxphy_info::fec	smac/hal/ssv6006c/turismo_common.h	/^    u32 fec:1;$/;"	m	struct:ssv6006_rxphy_info	access:public
+ssv6006_rxphy_info::l_length	smac/hal/ssv6006c/turismo_common.h	/^    u32 l_length:12;$/;"	m	struct:ssv6006_rxphy_info	access:public
+ssv6006_rxphy_info::l_rate	smac/hal/ssv6006c/turismo_common.h	/^    u32 l_rate:3;$/;"	m	struct:ssv6006_rxphy_info	access:public
+ssv6006_rxphy_info::len	smac/hal/ssv6006c/turismo_common.h	/^    u32 len:16;$/;"	m	struct:ssv6006_rxphy_info	access:public
+ssv6006_rxphy_info::mrx_seqn	smac/hal/ssv6006c/turismo_common.h	/^    u32 mrx_seqn:1;$/;"	m	struct:ssv6006_rxphy_info	access:public
+ssv6006_rxphy_info::n_ess	smac/hal/ssv6006c/turismo_common.h	/^    u32 n_ess:2;$/;"	m	struct:ssv6006_rxphy_info	access:public
+ssv6006_rxphy_info::no_sounding	smac/hal/ssv6006c/turismo_common.h	/^    u32 no_sounding:1;$/;"	m	struct:ssv6006_rxphy_info	access:public
+ssv6006_rxphy_info::phy_rate	smac/hal/ssv6006c/turismo_common.h	/^    u32 phy_rate:8;$/;"	m	struct:ssv6006_rxphy_info	access:public
+ssv6006_rxphy_info::rssi	smac/hal/ssv6006c/turismo_common.h	/^    u32 rssi:8;$/;"	m	struct:ssv6006_rxphy_info	access:public
+ssv6006_rxphy_info::rx_freq_offset	smac/hal/ssv6006c/turismo_common.h	/^    u32 rx_freq_offset:16;$/;"	m	struct:ssv6006_rxphy_info	access:public
+ssv6006_rxphy_info::rx_time_stamp	smac/hal/ssv6006c/turismo_common.h	/^    u32 rx_time_stamp;$/;"	m	struct:ssv6006_rxphy_info	access:public
+ssv6006_rxphy_info::service	smac/hal/ssv6006c/turismo_common.h	/^    u32 service:16;$/;"	m	struct:ssv6006_rxphy_info	access:public
+ssv6006_rxphy_info::smoothing	smac/hal/ssv6006c/turismo_common.h	/^    u32 smoothing:1;$/;"	m	struct:ssv6006_rxphy_info	access:public
+ssv6006_rxphy_info::snr	smac/hal/ssv6006c/turismo_common.h	/^    u32 snr:8;$/;"	m	struct:ssv6006_rxphy_info	access:public
+ssv6006_rxphy_info::stbc	smac/hal/ssv6006c/turismo_common.h	/^    u32 stbc:2;$/;"	m	struct:ssv6006_rxphy_info	access:public
+ssv6006_send_soft_beacon_cmd	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006_send_soft_beacon_cmd(struct ssv_hw *sh, bool bEnable)$/;"	f	file:	signature:(struct ssv_hw *sh, bool bEnable)
+ssv6006_send_tx_poll_cmd	smac/hal/ssv6006c/ssv6006_common.c	/^static void ssv6006_send_tx_poll_cmd(struct ssv_hw *sh, u32 type)$/;"	f	file:	signature:(struct ssv_hw *sh, u32 type)
+ssv6006_set_80211_hw_rate_config	smac/hal/ssv6006c/ssv6006_phy.c	/^static void ssv6006_set_80211_hw_rate_config(struct ssv_softc *sc)$/;"	f	file:	signature:(struct ssv_softc *sc)
+ssv6006_set_data_rcword	smac/hal/ssv6006c/ssv6006_phy.c	/^static void ssv6006_set_data_rcword(struct ssv_softc *sc, struct ssv_sta_priv_data *ssv_sta_priv,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ssv_sta_priv_data *ssv_sta_priv, struct ssv6006_tx_desc *tx_desc, struct ieee80211_tx_info *info, struct ssv6006_rc_idx *drate_idx, bool is_mgmt, bool is_nullfunc, enum nl80211_band band)
+ssv6006_set_frame_duration	smac/hal/ssv6006c/ssv6006_phy.c	/^static void ssv6006_set_frame_duration(struct ssv_softc *sc, struct ieee80211_tx_info *info,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ieee80211_tx_info *info, struct ssv6006_rc_idx *drate_idx, struct ssv6006_rc_idx *crate_idx, u16 len, struct ssv6006_tx_desc *tx_desc, u32 *nav)
+ssv6006_set_fw_hwwsid_sec_type	smac/hal/ssv6006c/ssv6006_common.c	/^static void ssv6006_set_fw_hwwsid_sec_type(struct ssv_softc *sc, struct ieee80211_sta *sta,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ieee80211_sta *sta, struct ssv_sta_info *sta_info, struct ssv_vif_priv_data *vif_priv)
+ssv6006_set_phy_mode	smac/hal/ssv6006c/ssv6006_phy.c	/^static void ssv6006_set_phy_mode(struct ssv_hw *sh, bool val)$/;"	f	file:	signature:(struct ssv_hw *sh, bool val)
+ssv6006_set_tx_desc_crate	smac/hal/ssv6006c/ssv6006_phy.c	/^static void ssv6006_set_tx_desc_crate(struct ssv6006_tx_desc *tx_desc, int idx, u8 crate)$/;"	f	file:	signature:(struct ssv6006_tx_desc *tx_desc, int idx, u8 crate)
+ssv6006_set_tx_desc_drate	smac/hal/ssv6006c/ssv6006_phy.c	/^static void ssv6006_set_tx_desc_drate(struct ssv6006_tx_desc *tx_desc, int idx, u8 drate)$/;"	f	file:	signature:(struct ssv6006_tx_desc *tx_desc, int idx, u8 drate)
+ssv6006_set_tx_desc_trycnt	smac/hal/ssv6006c/ssv6006_phy.c	/^static void ssv6006_set_tx_desc_trycnt(struct ssv6006_tx_desc *tx_desc, int idx, u8 trycnt)$/;"	f	file:	signature:(struct ssv6006_tx_desc *tx_desc, int idx, u8 trycnt)
+ssv6006_set_wep_hw_crypto_key	smac/hal/ssv6006c/ssv6006_common.c	/^static void ssv6006_set_wep_hw_crypto_key(struct ssv_softc *sc,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ssv_sta_info *sta_info, struct ssv_vif_priv_data *vif_priv)
+ssv6006_turismoC_apply_flash_setting_to_rf	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void ssv6006_turismoC_apply_flash_setting_to_rf(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006_turismoC_chg_bbscale	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static int ssv6006_turismoC_chg_bbscale(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006_turismoC_chg_cck_bbscale	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void ssv6006_turismoC_chg_cck_bbscale(struct ssv_hw *sh, int cck)$/;"	f	file:	signature:(struct ssv_hw *sh, int cck)
+ssv6006_turismoC_chg_dpd_bbscale	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static int ssv6006_turismoC_chg_dpd_bbscale(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006_turismoC_chg_ht20_bbscale	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void ssv6006_turismoC_chg_ht20_bbscale(struct ssv_hw *sh, int bpsk, int qpsk, int qam16, int qam64)$/;"	f	file:	signature:(struct ssv_hw *sh, int bpsk, int qpsk, int qam16, int qam64)
+ssv6006_turismoC_chg_ht40_bbscale	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void ssv6006_turismoC_chg_ht40_bbscale(struct ssv_hw *sh, int bpsk, int qpsk, int qam16, int qam64)$/;"	f	file:	signature:(struct ssv_hw *sh, int bpsk, int qpsk, int qam16, int qam64)
+ssv6006_turismoC_chg_legacy_bbscale	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void ssv6006_turismoC_chg_legacy_bbscale(struct ssv_hw *sh, int bpsk, int qpsk, int qam16, int qam64)$/;"	f	file:	signature:(struct ssv_hw *sh, int bpsk, int qpsk, int qam16, int qam64)
+ssv6006_turismoC_chg_xtal_freq_offset	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static int ssv6006_turismoC_chg_xtal_freq_offset(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006_turismoC_do_temperature_compensation	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void ssv6006_turismoC_do_temperature_compensation(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006_turismoC_do_temperature_dpd_bbscale_compensation	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void ssv6006_turismoC_do_temperature_dpd_bbscale_compensation(struct ssv_hw *sh,$/;"	f	file:	signature:(struct ssv_hw *sh, int chan, struct ssv_tempe_table *tempe_table)
+ssv6006_turismoC_dump_phy_reg	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static bool ssv6006_turismoC_dump_phy_reg(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006_turismoC_dump_rf_reg	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static bool ssv6006_turismoC_dump_rf_reg(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006_turismoC_get_current_tempe_state	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static int ssv6006_turismoC_get_current_tempe_state(struct ssv_hw *sh, char low_boundary, char high_boundary)$/;"	f	file:	signature:(struct ssv_hw *sh, char low_boundary, char high_boundary)
+ssv6006_turismoC_get_current_temperature	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static int ssv6006_turismoC_get_current_temperature(struct ssv_hw *sh, int *pvalue)$/;"	f	file:	signature:(struct ssv_hw *sh, int *pvalue)
+ssv6006_turismoC_get_phy_table_size	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static u32 ssv6006_turismoC_get_phy_table_size(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006_turismoC_get_rf_table_size	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static u32 ssv6006_turismoC_get_rf_table_size(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006_turismoC_init_PLL	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void ssv6006_turismoC_init_PLL(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006_turismoC_init_cali	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void ssv6006_turismoC_init_cali (struct ssv_hw *sh, struct ssv6006_cal_result *cal)$/;"	f	file:	signature:(struct ssv_hw *sh, struct ssv6006_cal_result *cal)
+ssv6006_turismoC_init_cali	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void ssv6006_turismoC_init_cali (struct ssv_hw *sh, struct ssv6006_cal_result *cal);$/;"	p	file:	signature:(struct ssv_hw *sh, struct ssv6006_cal_result *cal)
+ssv6006_turismoC_init_fast_cali	smac/hal/ssv6006c/ssv6006_turismoC.c	/^void ssv6006_turismoC_init_fast_cali (struct ssv_hw *sh, struct ssv6006_cal_result *cal)$/;"	f	signature:(struct ssv_hw *sh, struct ssv6006_cal_result *cal)
+ssv6006_turismoC_init_iqk	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void ssv6006_turismoC_init_iqk (struct ssv_hw *sh, struct ssv6006_cal_result *cal)$/;"	f	file:	signature:(struct ssv_hw *sh, struct ssv6006_cal_result *cal)
+ssv6006_turismoC_init_iqk	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void ssv6006_turismoC_init_iqk (struct ssv_hw *sh, struct ssv6006_cal_result *cal);$/;"	p	file:	signature:(struct ssv_hw *sh, struct ssv6006_cal_result *cal)
+ssv6006_turismoC_load_phy_table	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void ssv6006_turismoC_load_phy_table(ssv_cabrio_reg **phy_table)$/;"	f	file:	signature:(ssv_cabrio_reg **phy_table)
+ssv6006_turismoC_load_rf_table	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void ssv6006_turismoC_load_rf_table(ssv_cabrio_reg **rf_table)$/;"	f	file:	signature:(ssv_cabrio_reg **rf_table)
+ssv6006_turismoC_phy_setting	smac/hal/ssv6006c/turismoC_wifi_phy_reg.c	/^ssv_cabrio_reg ssv6006_turismoC_phy_setting[]={$/;"	v
+ssv6006_turismoC_phy_tbl_size	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static const size_t ssv6006_turismoC_phy_tbl_size = sizeof(ssv6006_turismoC_phy_setting);$/;"	v	file:
+ssv6006_turismoC_rf_setting	smac/hal/ssv6006c/turismoC_rf_reg.c	/^ssv_cabrio_reg ssv6006_turismoC_rf_setting[]={$/;"	v
+ssv6006_turismoC_rf_tbl_size	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static const size_t ssv6006_turismoC_rf_tbl_size = sizeof(ssv6006_turismoC_rf_setting);$/;"	v	file:
+ssv6006_turismoC_set_channel	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static int ssv6006_turismoC_set_channel(struct ssv_softc *sc, struct ieee80211_channel *chan,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ieee80211_channel *chan, enum nl80211_channel_type channel_type)
+ssv6006_turismoC_set_pll_phy_rf	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static int ssv6006_turismoC_set_pll_phy_rf(struct ssv_hw *sh$/;"	f	file:	signature:(struct ssv_hw *sh , ssv_cabrio_reg *rf_tbl, ssv_cabrio_reg *phy_tbl)
+ssv6006_turismoC_set_rf_enable	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static bool ssv6006_turismoC_set_rf_enable(struct ssv_hw *sh, bool val)$/;"	f	file:	signature:(struct ssv_hw *sh, bool val)
+ssv6006_turismoC_set_rf_enable	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static bool ssv6006_turismoC_set_rf_enable(struct ssv_hw *sh, bool val);$/;"	p	file:	signature:(struct ssv_hw *sh, bool val)
+ssv6006_turismoC_set_xtal_freq_offset_compensation	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void ssv6006_turismoC_set_xtal_freq_offset_compensation(struct ssv_hw *sh, int xi, int xo)$/;"	f	file:	signature:(struct ssv_hw *sh, int xi, int xo)
+ssv6006_turismoC_support_iqk_cmd	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static bool ssv6006_turismoC_support_iqk_cmd(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006_turismoC_update_channel_dpd_bbscale	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void ssv6006_turismoC_update_channel_dpd_bbscale(struct ssv_softc *sc, int ch)$/;"	f	file:	signature:(struct ssv_softc *sc, int ch)
+ssv6006_turismoC_update_efuse_setting	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static int ssv6006_turismoC_update_efuse_setting(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006_turismoC_update_rf_pwr	smac/hal/ssv6006c/ssv6006_turismoC.c	/^void ssv6006_turismoC_update_rf_pwr(struct ssv_softc *sc){$/;"	f	signature:(struct ssv_softc *sc)
+ssv6006_tx_desc	smac/hal/ssv6006c/turismo_common.h	/^struct ssv6006_tx_desc$/;"	s
+ssv6006_tx_desc::TxF_ID	smac/hal/ssv6006c/turismo_common.h	/^    u32 TxF_ID:6;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::ack_policy0	smac/hal/ssv6006c/turismo_common.h	/^    u32 ack_policy0:2;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::ack_policy1	smac/hal/ssv6006c/turismo_common.h	/^    u32 ack_policy1:2;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::ack_policy2	smac/hal/ssv6006c/turismo_common.h	/^    u32 ack_policy2:2;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::ack_policy3	smac/hal/ssv6006c/turismo_common.h	/^    u32 ack_policy3:2;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::ack_policy_obsolete	smac/hal/ssv6006c/turismo_common.h	/^    u32 ack_policy_obsolete:2;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::aggr	smac/hal/ssv6006c/turismo_common.h	/^    u32 aggr:2;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::ampdu_dmydelimiter_num	smac/hal/ssv6006c/turismo_common.h	/^    u32 ampdu_dmydelimiter_num:4;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::ampdu_last_pkt	smac/hal/ssv6006c/turismo_common.h	/^    u32 ampdu_last_pkt:1;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::ampdu_next_pkt	smac/hal/ssv6006c/turismo_common.h	/^    u32 ampdu_next_pkt:8;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::ampdu_tx_bitmap_hw	smac/hal/ssv6006c/turismo_common.h	/^    u32 ampdu_tx_bitmap_hw;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::ampdu_tx_bitmap_lw	smac/hal/ssv6006c/turismo_common.h	/^    u32 ampdu_tx_bitmap_lw;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::ampdu_tx_ssn	smac/hal/ssv6006c/turismo_common.h	/^    u32 ampdu_tx_ssn:12;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::ampdu_whole_length	smac/hal/ssv6006c/turismo_common.h	/^    u32 ampdu_whole_length:16;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::bc_que	smac/hal/ssv6006c/turismo_common.h	/^    u32 bc_que:1;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::bssidx	smac/hal/ssv6006c/turismo_common.h	/^    u32 bssidx:2;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::c_type	smac/hal/ssv6006c/turismo_common.h	/^    u32 c_type:3;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::crate_idx0	smac/hal/ssv6006c/turismo_common.h	/^    u32 crate_idx0:8;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::crate_idx1	smac/hal/ssv6006c/turismo_common.h	/^    u32 crate_idx1:8;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::crate_idx2	smac/hal/ssv6006c/turismo_common.h	/^    u32 crate_idx2:8;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::crate_idx3	smac/hal/ssv6006c/turismo_common.h	/^    u32 crate_idx3:8;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::dl_length0	smac/hal/ssv6006c/turismo_common.h	/^    u32 dl_length0:12;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::dl_length1	smac/hal/ssv6006c/turismo_common.h	/^    u32 dl_length1:12;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::dl_length2	smac/hal/ssv6006c/turismo_common.h	/^    u32 dl_length2:12;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::dl_length3	smac/hal/ssv6006c/turismo_common.h	/^    u32 dl_length3:12;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::do_rts_cts0	smac/hal/ssv6006c/turismo_common.h	/^    u32 do_rts_cts0:2;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::do_rts_cts1	smac/hal/ssv6006c/turismo_common.h	/^    u32 do_rts_cts1:2;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::do_rts_cts2	smac/hal/ssv6006c/turismo_common.h	/^    u32 do_rts_cts2:2;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::do_rts_cts3	smac/hal/ssv6006c/turismo_common.h	/^    u32 do_rts_cts3:2;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::drate_idx0	smac/hal/ssv6006c/turismo_common.h	/^    u32 drate_idx0:8;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::drate_idx1	smac/hal/ssv6006c/turismo_common.h	/^    u32 drate_idx1:8;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::drate_idx2	smac/hal/ssv6006c/turismo_common.h	/^    u32 drate_idx2:8;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::drate_idx3	smac/hal/ssv6006c/turismo_common.h	/^    u32 drate_idx3:8;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::dummy0	smac/hal/ssv6006c/turismo_common.h	/^    u32 dummy0;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::dummy1	smac/hal/ssv6006c/turismo_common.h	/^    u32 dummy1;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::dummy2	smac/hal/ssv6006c/turismo_common.h	/^    u32 dummy2;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::extra_info	smac/hal/ssv6006c/turismo_common.h	/^    u32 extra_info:1;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::f80211	smac/hal/ssv6006c/turismo_common.h	/^    u32 f80211:1;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::fCmd	smac/hal/ssv6006c/turismo_common.h	/^    u32 fCmd;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::fCmdIdx	smac/hal/ssv6006c/turismo_common.h	/^    u32 fCmdIdx:3;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::frag	smac/hal/ssv6006c/turismo_common.h	/^    u32 frag:1;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::hdr_len	smac/hal/ssv6006c/turismo_common.h	/^    u32 hdr_len:6;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::hdr_offset	smac/hal/ssv6006c/turismo_common.h	/^    u32 hdr_offset:8;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::ht	smac/hal/ssv6006c/turismo_common.h	/^    u32 ht:1;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::is_last_rate0	smac/hal/ssv6006c/turismo_common.h	/^    u32 is_last_rate0:1;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::is_last_rate1	smac/hal/ssv6006c/turismo_common.h	/^    u32 is_last_rate1:1;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::is_last_rate2	smac/hal/ssv6006c/turismo_common.h	/^    u32 is_last_rate2:1;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::is_last_rate3	smac/hal/ssv6006c/turismo_common.h	/^    u32 is_last_rate3:1;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::is_rate_stat_sample_pkt	smac/hal/ssv6006c/turismo_common.h	/^    u32 is_rate_stat_sample_pkt:1;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::len	smac/hal/ssv6006c/turismo_common.h	/^    u32 len:16;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::more_data	smac/hal/ssv6006c/turismo_common.h	/^    u32 more_data:1;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::no_pkt_buf_reduction	smac/hal/ssv6006c/turismo_common.h	/^    u32 no_pkt_buf_reduction:1;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::payload_offset_obsolete	smac/hal/ssv6006c/turismo_common.h	/^    u32 payload_offset_obsolete:8;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::qos	smac/hal/ssv6006c/turismo_common.h	/^    u32 qos:1;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::rate_rpt_mode	smac/hal/ssv6006c/turismo_common.h	/^    u32 rate_rpt_mode:2;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::rateidx1_data_duration	smac/hal/ssv6006c/turismo_common.h	/^    u32 rateidx1_data_duration:16;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::rateidx2_data_duration	smac/hal/ssv6006c/turismo_common.h	/^    u32 rateidx2_data_duration:16;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::rateidx3_data_duration	smac/hal/ssv6006c/turismo_common.h	/^    u32 rateidx3_data_duration:16;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::reason	smac/hal/ssv6006c/turismo_common.h	/^    u32 reason:6;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::rpt_noctstrycnt0	smac/hal/ssv6006c/turismo_common.h	/^    u32 rpt_noctstrycnt0:4;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::rpt_noctstrycnt1	smac/hal/ssv6006c/turismo_common.h	/^    u32 rpt_noctstrycnt1:4;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::rpt_noctstrycnt2	smac/hal/ssv6006c/turismo_common.h	/^    u32 rpt_noctstrycnt2:4;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::rpt_noctstrycnt3	smac/hal/ssv6006c/turismo_common.h	/^    u32 rpt_noctstrycnt3:4;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::rpt_result0	smac/hal/ssv6006c/turismo_common.h	/^    u32 rpt_result0:2;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::rpt_result1	smac/hal/ssv6006c/turismo_common.h	/^    u32 rpt_result1:2;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::rpt_result2	smac/hal/ssv6006c/turismo_common.h	/^    u32 rpt_result2:2;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::rpt_result3	smac/hal/ssv6006c/turismo_common.h	/^    u32 rpt_result3:2;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::rpt_trycnt0	smac/hal/ssv6006c/turismo_common.h	/^    u32 rpt_trycnt0:4;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::rpt_trycnt1	smac/hal/ssv6006c/turismo_common.h	/^    u32 rpt_trycnt1:4;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::rpt_trycnt2	smac/hal/ssv6006c/turismo_common.h	/^    u32 rpt_trycnt2:4;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::rpt_trycnt3	smac/hal/ssv6006c/turismo_common.h	/^    u32 rpt_trycnt3:4;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::rsvd_tx05	smac/hal/ssv6006c/turismo_common.h	/^    u32 rsvd_tx05 :2;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::rsvdtx_07b	smac/hal/ssv6006c/turismo_common.h	/^    u32 rsvdtx_07b:1;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::rsvdtx_09b	smac/hal/ssv6006c/turismo_common.h	/^    u32 rsvdtx_09b:1;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::rsvdtx_1	smac/hal/ssv6006c/turismo_common.h	/^    u32 rsvdtx_1:1;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::rsvdtx_11b	smac/hal/ssv6006c/turismo_common.h	/^    u32 rsvdtx_11b:1;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::rsvdtx_13b	smac/hal/ssv6006c/turismo_common.h	/^    u32 rsvdtx_13b:1;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::rsvdtx_14a	smac/hal/ssv6006c/turismo_common.h	/^    u32 rsvdtx_14a:3;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::rts_cts_nav0	smac/hal/ssv6006c/turismo_common.h	/^    u32 rts_cts_nav0:16;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::rts_cts_nav1	smac/hal/ssv6006c/turismo_common.h	/^    u32 rts_cts_nav1:16;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::rts_cts_nav2	smac/hal/ssv6006c/turismo_common.h	/^    u32 rts_cts_nav2:16;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::rts_cts_nav3	smac/hal/ssv6006c/turismo_common.h	/^    u32 rts_cts_nav3:16;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::rvdtx_0	smac/hal/ssv6006c/turismo_common.h	/^    u32 rvdtx_0:3;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::security	smac/hal/ssv6006c/turismo_common.h	/^    u32 security:1;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::stype_b5b4	smac/hal/ssv6006c/turismo_common.h	/^    u32 stype_b5b4:2;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::try_cnt0	smac/hal/ssv6006c/turismo_common.h	/^    u32 try_cnt0:4;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::try_cnt1	smac/hal/ssv6006c/turismo_common.h	/^    u32 try_cnt1:4;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::try_cnt2	smac/hal/ssv6006c/turismo_common.h	/^    u32 try_cnt2:4;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::try_cnt3	smac/hal/ssv6006c/turismo_common.h	/^    u32 try_cnt3:4;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::tx_burst_obsolete	smac/hal/ssv6006c/turismo_common.h	/^    u32 tx_burst_obsolete:1;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::tx_pkt_run_no	smac/hal/ssv6006c/turismo_common.h	/^    u32 tx_pkt_run_no:8;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::txq_idx	smac/hal/ssv6006c/turismo_common.h	/^    u32 txq_idx:3;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::unicast	smac/hal/ssv6006c/turismo_common.h	/^    u32 unicast:1;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::use_4addr	smac/hal/ssv6006c/turismo_common.h	/^    u32 use_4addr:1;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc::wsid	smac/hal/ssv6006c/turismo_common.h	/^    u32 wsid:4;$/;"	m	struct:ssv6006_tx_desc	access:public
+ssv6006_tx_desc_length	smac/hal/ssv6006c/ssv6006_phy.c	/^const size_t ssv6006_tx_desc_length = sizeof(struct ssv6006_tx_desc);$/;"	v
+ssv6006_tx_rate_update	smac/hal/ssv6006c/ssv6006_phy.c	/^static void ssv6006_tx_rate_update( struct ssv_softc *sc, struct sk_buff *skb)$/;"	f	file:	signature:( struct ssv_softc *sc, struct sk_buff *skb)
+ssv6006_txtput_set_desc	smac/hal/ssv6006c/ssv6006_phy.c	/^static void ssv6006_txtput_set_desc(struct ssv_hw *sh, struct sk_buff *skb )$/;"	f	file:	signature:(struct ssv_hw *sh, struct sk_buff *skb )
+ssv6006_update_ampdu_txinfo	smac/hal/ssv6006c/ssv6006_phy.c	/^static void ssv6006_update_ampdu_txinfo(struct ssv_softc *sc, struct sk_buff *ampdu_skb)$/;"	f	file:	signature:(struct ssv_softc *sc, struct sk_buff *ampdu_skb)
+ssv6006_update_data_cci_setting	smac/hal/ssv6006c/ssv6006_phy.c	/^void ssv6006_update_data_cci_setting$/;"	f	signature:(struct ssv_softc *sc, struct ssv_sta_priv_data *sta_priv, u32 input_level)
+ssv6006_update_null_func_txinfo	smac/hal/ssv6006c/ssv6006_phy.c	/^static int ssv6006_update_null_func_txinfo(struct ssv_softc *sc, struct ieee80211_sta *sta, struct sk_buff *skb)$/;"	f	file:	signature:(struct ssv_softc *sc, struct ieee80211_sta *sta, struct sk_buff *skb)
+ssv6006_update_rxstatus	smac/hal/ssv6006c/ssv6006_phy.c	/^void ssv6006_update_rxstatus(struct ssv_softc *sc,$/;"	f	signature:(struct ssv_softc *sc, struct sk_buff *rx_skb, struct ieee80211_rx_status *rxs)
+ssv6006_update_scan_cci_setting	smac/hal/ssv6006c/ssv6006_phy.c	/^void ssv6006_update_scan_cci_setting(struct ssv_softc *sc)$/;"	f	signature:(struct ssv_softc *sc)
+ssv6006_update_txinfo	smac/hal/ssv6006c/ssv6006_phy.c	/^static void ssv6006_update_txinfo (struct ssv_softc *sc, struct sk_buff *skb)$/;"	f	file:	signature:(struct ssv_softc *sc, struct sk_buff *skb)
+ssv6006_use_hw_encrypt	smac/hal/ssv6006c/ssv6006_common.c	/^static bool ssv6006_use_hw_encrypt(int cipher, struct ssv_softc *sc,$/;"	f	file:	signature:(int cipher, struct ssv_softc *sc, struct ssv_sta_priv_data *sta_priv, struct ssv_vif_priv_data *vif_priv )
+ssv6006_wep_use_hw_cipher	smac/hal/ssv6006c/ssv6006_common.c	/^static bool ssv6006_wep_use_hw_cipher(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv)$/;"	f	file:	signature:(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv)
+ssv6006c_alloc_pbuf	smac/hal/ssv6006c/ssv6006C_mac.c	/^static u32 ssv6006c_alloc_pbuf(struct ssv_softc *sc, int size, int type)$/;"	f	file:	signature:(struct ssv_softc *sc, int size, int type)
+ssv6006c_alloc_pbuf	smac/hal/ssv6006c/ssv6006C_mac.c	/^static u32 ssv6006c_alloc_pbuf(struct ssv_softc *sc, int size, int type);$/;"	p	file:	signature:(struct ssv_softc *sc, int size, int type)
+ssv6006c_ampdu_auto_crc_en	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_ampdu_auto_crc_en(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_auto_gen_nullpkt	smac/hal/ssv6006c/ssv6006C_mac.c	/^static int ssv6006c_auto_gen_nullpkt(struct ssv_hw *sh, int hwq)$/;"	f	file:	signature:(struct ssv_hw *sh, int hwq)
+ssv6006c_beacon_enable	smac/hal/ssv6006c/ssv6006C_mac.c	/^static bool ssv6006c_beacon_enable(struct ssv_softc *sc, bool bEnable)$/;"	f	file:	signature:(struct ssv_softc *sc, bool bEnable)
+ssv6006c_beacon_get_valid_cfg	smac/hal/ssv6006c/ssv6006C_mac.c	/^static enum ssv6xxx_beacon_type ssv6006c_beacon_get_valid_cfg(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_beacon_loss_config	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_beacon_loss_config(struct ssv_hw *sh, u16 beacon_int, const u8 *bssid)$/;"	f	file:	signature:(struct ssv_hw *sh, u16 beacon_int, const u8 *bssid)
+ssv6006c_beacon_loss_disable	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_beacon_loss_disable(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_beacon_loss_enable	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_beacon_loss_enable(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_burst_read_reg	smac/hal/ssv6006c/ssv6006C_mac.c	/^static int ssv6006c_burst_read_reg(struct ssv_hw *sh, u32 *addr, u32 *buf, u8 reg_amount)$/;"	f	file:	signature:(struct ssv_hw *sh, u32 *addr, u32 *buf, u8 reg_amount)
+ssv6006c_burst_write_reg	smac/hal/ssv6006c/ssv6006C_mac.c	/^static int ssv6006c_burst_write_reg(struct ssv_hw *sh, u32 *addr, u32 *buf, u8 reg_amount)$/;"	f	file:	signature:(struct ssv_hw *sh, u32 *addr, u32 *buf, u8 reg_amount)
+ssv6006c_chg_clk_src	smac/hal/ssv6006c/ssv6006C_mac.c	/^static int ssv6006c_chg_clk_src(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_cmd_efuse	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_cmd_efuse(struct ssv_hw *sh, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_hw *sh, int argc, char *argv[])
+ssv6006c_cmd_hwinfo	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_cmd_hwinfo(struct ssv_hw *sh, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_hw *sh, int argc, char *argv[])
+ssv6006c_cmd_hwinfo_lookup_fsm_mtxdma	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_cmd_hwinfo_lookup_fsm_mtxdma(u32 value, char *mtxstr)$/;"	f	file:	signature:(u32 value, char *mtxstr)
+ssv6006c_cmd_hwinfo_lookup_mac_tx_mtxptc	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_cmd_hwinfo_lookup_mac_tx_mtxptc(u32 value, char *mtxstr)$/;"	f	file:	signature:(u32 value, char *mtxstr)
+ssv6006c_cmd_hwinfo_lookup_mac_tx_ptc_schedule	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_cmd_hwinfo_lookup_mac_tx_ptc_schedule(u32 value, char *mtxstr)$/;"	f	file:	signature:(u32 value, char *mtxstr)
+ssv6006c_cmd_hwinfo_lookup_mac_tx_wait_response_phase	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_cmd_hwinfo_lookup_mac_tx_wait_response_phase(u32 value, char *mtxstr)$/;"	f	file:	signature:(u32 value, char *mtxstr)
+ssv6006c_cmd_hwinfo_lookup_mtxdma_cmd	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_cmd_hwinfo_lookup_mtxdma_cmd(u32 value, char *mtxstr)$/;"	f	file:	signature:(u32 value, char *mtxstr)
+ssv6006c_cmd_hwinfo_mac_beacon	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_cmd_hwinfo_mac_beacon(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_cmd_hwinfo_mac_edca	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_cmd_hwinfo_mac_edca(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_cmd_hwinfo_mac_fixrate	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_cmd_hwinfo_mac_fixrate(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_cmd_hwinfo_mac_hci_stat	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_cmd_hwinfo_mac_hci_stat(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_cmd_hwinfo_mac_peer_stat	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_cmd_hwinfo_mac_peer_stat(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_cmd_hwinfo_mac_scrt_stat	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_cmd_hwinfo_mac_scrt_stat(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_cmd_hwinfo_mac_stat	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_cmd_hwinfo_mac_stat(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_cmd_hwinfo_mac_tx2phy	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_cmd_hwinfo_mac_tx2phy(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_cmd_hwinfo_mac_tx2ptc	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_cmd_hwinfo_mac_tx2ptc(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_cmd_hwinfo_mac_txbase	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_cmd_hwinfo_mac_txbase(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_cmd_hwinfo_mac_txfsm	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_cmd_hwinfo_mac_txfsm(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_cmd_hwinfo_mac_txifs	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_cmd_hwinfo_mac_txifs(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_cmd_hwinfo_mac_txq	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_cmd_hwinfo_mac_txq(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_cmd_hwinfo_mac_txstat	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_cmd_hwinfo_mac_txstat(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_cmd_hwinfo_page_id	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_cmd_hwinfo_page_id(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_cmd_hwinfo_phy_cali	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_cmd_hwinfo_phy_cali(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_cmd_hwinfo_phy_pmu	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_cmd_hwinfo_phy_pmu(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_cmd_hwinfo_phy_sx	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_cmd_hwinfo_phy_sx(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_cmd_hwinfo_phy_txband	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_cmd_hwinfo_phy_txband(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_cmd_hwinfo_phy_txgain	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_cmd_hwinfo_phy_txgain(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_cmd_hwinfo_phy_xtal	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_cmd_hwinfo_phy_xtal(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_cmd_loopback_setup_env	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void ssv6006c_cmd_loopback_setup_env(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_cmd_loopback_start	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_cmd_loopback_start(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_cmd_lpbk_setup_env_sec_talbe	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void ssv6006c_cmd_lpbk_setup_env_sec_talbe(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_cmd_mib	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_cmd_mib(struct ssv_softc *sc, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_softc *sc, int argc, char *argv[])
+ssv6006c_cmd_mtx_lpbk_mac80211_hdr	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_cmd_mtx_lpbk_mac80211_hdr(struct ssv_hw *sh, struct sk_buff *skb, u8 seq)$/;"	f	file:	signature:(struct ssv_hw *sh, struct sk_buff *skb, u8 seq)
+ssv6006c_cmd_power_saving	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_cmd_power_saving(struct ssv_softc *sc, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_softc *sc, int argc, char *argv[])
+ssv6006c_cmd_spectrum	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void ssv6006c_cmd_spectrum(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_del_hw_wsid	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_del_hw_wsid(struct ssv_softc *sc, int hw_wsid)$/;"	f	file:	signature:(struct ssv_softc *sc, int hw_wsid)
+ssv6006c_detach_usb_hci	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_detach_usb_hci(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_disable_usb_acc	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_disable_usb_acc(struct ssv_softc *sc, u8 epnum)$/;"	f	file:	signature:(struct ssv_softc *sc, u8 epnum)
+ssv6006c_dump_decision	smac/hal/ssv6006c/ssv6006C_mac.c	/^static bool ssv6006c_dump_decision(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_dump_mib_rx	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_dump_mib_rx(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_dump_mib_tx	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_dump_mib_tx(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_dump_wsid	smac/hal/ssv6006c/ssv6006C_mac.c	/^static bool ssv6006c_dump_wsid(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_enable_usb_acc	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_enable_usb_acc(struct ssv_softc *sc, u8 epnum)$/;"	f	file:	signature:(struct ssv_softc *sc, u8 epnum)
+ssv6006c_fill_beacon	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_fill_beacon(struct ssv_softc *sc, u32 regaddr, struct sk_buff *skb)$/;"	f	file:	signature:(struct ssv_softc *sc, u32 regaddr, struct sk_buff *skb)
+ssv6006c_free_pbuf	smac/hal/ssv6006c/ssv6006C_mac.c	/^static bool ssv6006c_free_pbuf(struct ssv_softc *sc, u32 pbuf_addr)$/;"	f	file:	signature:(struct ssv_softc *sc, u32 pbuf_addr)
+ssv6006c_get_bcn_ongoing	smac/hal/ssv6006c/ssv6006C_mac.c	/^static bool ssv6006c_get_bcn_ongoing(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_get_chip_id	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_get_chip_id(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_get_ffout_cnt	smac/hal/ssv6006c/ssv6006C_mac.c	/^static u32 ssv6006c_get_ffout_cnt(u32 value, int tag)$/;"	f	file:	signature:(u32 value, int tag)
+ssv6006c_get_fw_version	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_get_fw_version(struct ssv_hw *sh, u32 *regval)$/;"	f	file:	signature:(struct ssv_hw *sh, u32 *regval)
+ssv6006c_get_ic_time_tag	smac/hal/ssv6006c/ssv6006C_mac.c	/^static u64 ssv6006c_get_ic_time_tag(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_get_in_ffcnt	smac/hal/ssv6006c/ssv6006C_mac.c	/^static u32 ssv6006c_get_in_ffcnt(u32 value, int tag)$/;"	f	file:	signature:(u32 value, int tag)
+ssv6006c_get_mrx_mode	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_get_mrx_mode(struct ssv_hw *sh, u32 *val)$/;"	f	file:	signature:(struct ssv_hw *sh, u32 *val)
+ssv6006c_get_rd_id_adr	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_get_rd_id_adr(u32 *id_base_address)$/;"	f	file:	signature:(u32 *id_base_address)
+ssv6006c_init_gpio_cfg	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_init_gpio_cfg(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_init_hw_sec_phy_table	smac/hal/ssv6006c/ssv6006C_mac.c	/^static int ssv6006c_init_hw_sec_phy_table(struct ssv_softc *sc)$/;"	f	file:	signature:(struct ssv_softc *sc)
+ssv6006c_init_mac	smac/hal/ssv6006c/ssv6006C_mac.c	/^static int ssv6006c_init_mac(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_jump_to_rom	smac/hal/ssv6006c/ssv6006C_mac.c	/^static int ssv6006c_jump_to_rom(struct ssv_softc *sc)$/;"	f	file:	signature:(struct ssv_softc *sc)
+ssv6006c_list_mib	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_list_mib(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_load_fw_disable_mcu	smac/hal/ssv6006c/ssv6006C_mac.c	/^static int ssv6006c_load_fw_disable_mcu(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_load_fw_enable_mcu	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_load_fw_enable_mcu(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_load_fw_get_status	smac/hal/ssv6006c/ssv6006C_mac.c	/^static int ssv6006c_load_fw_get_status(struct ssv_hw *sh, u32 *status)$/;"	f	file:	signature:(struct ssv_hw *sh, u32 *status)
+ssv6006c_load_fw_post_config_device	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_load_fw_post_config_device(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_load_fw_pre_config_device	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_load_fw_pre_config_device(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_load_fw_set_status	smac/hal/ssv6006c/ssv6006C_mac.c	/^static int ssv6006c_load_fw_set_status(struct ssv_hw *sh, u32 status)$/;"	f	file:	signature:(struct ssv_hw *sh, u32 status)
+ssv6006c_mac_ini_table	smac/hal/ssv6006c/ssv6006C_mac.c	/^static const ssv_cabrio_reg ssv6006c_mac_ini_table[]=$/;"	v	file:
+ssv6006c_mcu_input_full	smac/hal/ssv6006c/ssv6006C_mac.c	/^static inline bool ssv6006c_mcu_input_full(struct ssv_softc *sc)$/;"	f	file:	signature:(struct ssv_softc *sc)
+ssv6006c_pll_chk	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_pll_chk(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_pmu_awake	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_pmu_awake(struct ssv_softc *sc)$/;"	f	file:	signature:(struct ssv_softc *sc)
+ssv6006c_read_efuse	smac/hal/ssv6006c/ssv6006C_mac.c	/^static u8 ssv6006c_read_efuse(struct ssv_hw *sh, u8 *pbuf)$/;"	f	file:	signature:(struct ssv_hw *sh, u8 *pbuf)
+ssv6006c_read_ffout_cnt	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_read_ffout_cnt(struct ssv_hw *sh,$/;"	f	file:	signature:(struct ssv_hw *sh, u32 *value, u32 *value1, u32 *value2)
+ssv6006c_read_id_len_threshold	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_read_id_len_threshold(struct ssv_hw *sh,$/;"	f	file:	signature:(struct ssv_hw *sh, u32 *tx_len, u32 *rx_len)
+ssv6006c_read_in_ffcnt	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_read_in_ffcnt(struct ssv_hw *sh,$/;"	f	file:	signature:(struct ssv_hw *sh, u32 *value, u32 *value1)
+ssv6006c_read_tag_status	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_read_tag_status(struct ssv_hw *sh,$/;"	f	file:	signature:(struct ssv_hw *sh, u32 *ava_status)
+ssv6006c_readrg_hci_inq_info	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_readrg_hci_inq_info(struct ssv_hw *sh, int *hci_used_id, int *tx_use_page)$/;"	f	file:	signature:(struct ssv_hw *sh, int *hci_used_id, int *tx_use_page)
+ssv6006c_readrg_txq_info	smac/hal/ssv6006c/ssv6006C_mac.c	/^static bool ssv6006c_readrg_txq_info(struct ssv_hw *sh, u32 *txq_info, int *hci_used_id)$/;"	f	file:	signature:(struct ssv_hw *sh, u32 *txq_info, int *hci_used_id)
+ssv6006c_readrg_txq_info2	smac/hal/ssv6006c/ssv6006C_mac.c	/^static bool ssv6006c_readrg_txq_info2(struct ssv_hw *sh, u32 *txq_info2, int *hci_used_id)$/;"	f	file:	signature:(struct ssv_hw *sh, u32 *txq_info2, int *hci_used_id)
+ssv6006c_reset_cpu	smac/hal/ssv6006c/ssv6006C_mac.c	/^static int ssv6006c_reset_cpu(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_reset_cpu	smac/hal/ssv6006c/ssv6006C_mac.c	/^static int ssv6006c_reset_cpu(struct ssv_hw *sh);$/;"	p	file:	signature:(struct ssv_hw *sh)
+ssv6006c_reset_mib	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_reset_mib(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_reset_mib_mac	smac/hal/ssv6006c/ssv6006C_mac.c	/^void ssv6006c_reset_mib_mac(struct ssv_hw *sh)$/;"	f	signature:(struct ssv_hw *sh)
+ssv6006c_reset_mib_mac	smac/hal/ssv6006c/ssv6006_priv.h	/^void ssv6006c_reset_mib_mac(struct ssv_hw *sh);$/;"	p	signature:(struct ssv_hw *sh)
+ssv6006c_reset_sysplf	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_reset_sysplf(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_restore_trap_reason	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_restore_trap_reason(struct ssv_softc *sc)$/;"	f	file:	signature:(struct ssv_softc *sc)
+ssv6006c_rx_spectrum	smac/hal/ssv6006c/ssv6006_turismoC.c	/^static void ssv6006c_rx_spectrum(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_save_clear_trap_reason	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_save_clear_trap_reason(struct ssv_softc *sc)$/;"	f	file:	signature:(struct ssv_softc *sc)
+ssv6006c_save_hw_status	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_save_hw_status(struct ssv_softc *sc)$/;"	f	file:	signature:(struct ssv_softc *sc)
+ssv6006c_sec_lut_setting	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_sec_lut_setting(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_set_aes_tkip_hw_crypto_group_key	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_set_aes_tkip_hw_crypto_group_key (struct ssv_softc *sc,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ssv_vif_info *vif_info, struct ssv_sta_info *sta_info, void *param)
+ssv6006c_set_beacon_id_dtim	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_set_beacon_id_dtim(struct ssv_softc *sc,$/;"	f	file:	signature:(struct ssv_softc *sc, enum ssv6xxx_beacon_type avl_bcn_type, int dtim_offset)
+ssv6006c_set_beacon_info	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_set_beacon_info(struct ssv_hw *sh, u8 beacon_interval, u8 dtim_cnt)$/;"	f	file:	signature:(struct ssv_hw *sh, u8 beacon_interval, u8 dtim_cnt)
+ssv6006c_set_beacon_reg_lock	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_set_beacon_reg_lock(struct ssv_hw *sh, bool val)$/;"	f	file:	signature:(struct ssv_hw *sh, bool val)
+ssv6006c_set_bssid	smac/hal/ssv6006c/ssv6006C_mac.c	/^static int ssv6006c_set_bssid(struct ssv_hw *sh, u8 *bssid, int vif_idx)$/;"	f	file:	signature:(struct ssv_hw *sh, u8 *bssid, int vif_idx)
+ssv6006c_set_bssid	smac/hal/ssv6006c/ssv6006C_mac.c	/^static int ssv6006c_set_bssid(struct ssv_hw *sh, u8 *bssid, int vif_idx);$/;"	p	file:	signature:(struct ssv_hw *sh, u8 *bssid, int vif_idx)
+ssv6006c_set_dur_burst_sifs_g	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_set_dur_burst_sifs_g(struct ssv_hw *sh, u32 val)$/;"	f	file:	signature:(struct ssv_hw *sh, u32 val)
+ssv6006c_set_dur_slot	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_set_dur_slot(struct ssv_hw *sh, u32 val)$/;"	f	file:	signature:(struct ssv_hw *sh, u32 val)
+ssv6006c_set_group_cipher_type	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_set_group_cipher_type(struct ssv_hw *sh, struct ssv_vif_priv_data *vif_priv, u8 cipher)$/;"	f	file:	signature:(struct ssv_hw *sh, struct ssv_vif_priv_data *vif_priv, u8 cipher)
+ssv6006c_set_halt_mngq_util_dtim	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_set_halt_mngq_util_dtim(struct ssv_hw *sh, bool val)$/;"	f	file:	signature:(struct ssv_hw *sh, bool val)
+ssv6006c_set_hw_wsid	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_set_hw_wsid(struct ssv_softc *sc, struct ieee80211_vif *vif,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ieee80211_vif *vif, struct ieee80211_sta *sta, int wsid)
+ssv6006c_set_macaddr	smac/hal/ssv6006c/ssv6006C_mac.c	/^static int ssv6006c_set_macaddr(struct ssv_hw *sh, int vif_idx)$/;"	f	file:	signature:(struct ssv_hw *sh, int vif_idx)
+ssv6006c_set_macaddr	smac/hal/ssv6006c/ssv6006C_mac.c	/^static int ssv6006c_set_macaddr(struct ssv_hw *sh, int vif_idx);$/;"	p	file:	signature:(struct ssv_hw *sh, int vif_idx)
+ssv6006c_set_mrx_mode	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_set_mrx_mode(struct ssv_hw *sh, u32 val)$/;"	f	file:	signature:(struct ssv_hw *sh, u32 val)
+ssv6006c_set_on3_enable	smac/hal/ssv6006c/ssv6006C_mac.c	/^void ssv6006c_set_on3_enable(struct ssv_hw *sh, bool val)$/;"	f	signature:(struct ssv_hw *sh, bool val)
+ssv6006c_set_op_mode	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_set_op_mode(struct ssv_hw *sh, u32 op_mode, int vif_idx)$/;"	f	file:	signature:(struct ssv_hw *sh, u32 op_mode, int vif_idx)
+ssv6006c_set_page_id	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_set_page_id(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_set_pairwise_cipher_type	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_set_pairwise_cipher_type(struct ssv_hw *sh, u8 cipher, u8 wsid)$/;"	f	file:	signature:(struct ssv_hw *sh, u8 cipher, u8 wsid)
+ssv6006c_set_qos_enable	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_set_qos_enable(struct ssv_hw *sh, bool val)$/;"	f	file:	signature:(struct ssv_hw *sh, bool val)
+ssv6006c_set_replay_ignore	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_set_replay_ignore(struct ssv_hw *sh,u8 ignore)$/;"	f	file:	signature:(struct ssv_hw *sh,u8 ignore)
+ssv6006c_set_rx_ba	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_set_rx_ba(struct ssv_hw *sh, bool on, u8 *ta,$/;"	f	file:	signature:(struct ssv_hw *sh, bool on, u8 *ta, u16 tid, u16 ssn, u8 buf_size)
+ssv6006c_set_rx_ctrl_flow	smac/hal/ssv6006c/ssv6006C_mac.c	/^static int ssv6006c_set_rx_ctrl_flow(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_set_rx_flow	smac/hal/ssv6006c/ssv6006C_mac.c	/^static int ssv6006c_set_rx_flow(struct ssv_hw *sh, enum ssv_rx_flow type, u32 rxflow)$/;"	f	file:	signature:(struct ssv_hw *sh, enum ssv_rx_flow type, u32 rxflow)
+ssv6006c_set_sifs	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_set_sifs(struct ssv_hw *sh, int band)$/;"	f	file:	signature:(struct ssv_hw *sh, int band)
+ssv6006c_set_sram_mode	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_set_sram_mode(struct ssv_hw *sh, enum SSV_SRAM_MODE mode)$/;"	f	file:	signature:(struct ssv_hw *sh, enum SSV_SRAM_MODE mode)
+ssv6006c_set_usb_lpm	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_set_usb_lpm(struct ssv_softc *sc, u8 enable)$/;"	f	file:	signature:(struct ssv_softc *sc, u8 enable)
+ssv6006c_set_wep_hw_crypto_setting	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_set_wep_hw_crypto_setting (struct ssv_softc *sc,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ssv_vif_info *vif_info, struct ssv_sta_info *sta_info, void *param)
+ssv6006c_set_wmm_param	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_set_wmm_param(struct ssv_softc *sc,$/;"	f	file:	signature:(struct ssv_softc *sc, const struct ieee80211_tx_queue_params *params, u16 queue)
+ssv6006c_store_wep_key	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_store_wep_key(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv, struct ssv_sta_priv_data *sta_priv, enum SSV_CIPHER_E cipher, struct ieee80211_key_conf *key)
+ssv6006c_update_decision_table	smac/hal/ssv6006c/ssv6006C_mac.c	/^static int ssv6006c_update_decision_table(struct ssv_softc *sc)$/;"	f	file:	signature:(struct ssv_softc *sc)
+ssv6006c_update_decision_table_6	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_update_decision_table_6(struct ssv_hw *sh, u32 value)$/;"	f	file:	signature:(struct ssv_hw *sh, u32 value)
+ssv6006c_update_page_id	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_update_page_id(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_update_product_hw_setting	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_update_product_hw_setting(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_update_txq_mask	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_update_txq_mask(struct ssv_hw *sh, u32 txq_mask)$/;"	f	file:	signature:(struct ssv_hw *sh, u32 txq_mask)
+ssv6006c_wait_usb_rom_ready	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_wait_usb_rom_ready(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_write_efuse	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_write_efuse(struct ssv_hw *sh, u8 *data, u8 data_length)$/;"	f	file:	signature:(struct ssv_hw *sh, u8 *data, u8 data_length)
+ssv6006c_write_group_key_to_hw	smac/hal/ssv6006c/ssv6006C_mac.c	/^static int ssv6006c_write_group_key_to_hw (struct ssv_softc *sc,$/;"	f	file:	signature:(struct ssv_softc *sc, int index, u8 algorithm, const u8 *key, int key_len, struct ieee80211_key_conf *keyconf, struct ssv_vif_priv_data *vif_priv, struct ssv_sta_priv_data *sta_priv)
+ssv6006c_write_hw_group_keyidx	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_write_hw_group_keyidx(struct ssv_hw *sh, struct ssv_vif_priv_data *vif_priv, int key_idx)$/;"	f	file:	signature:(struct ssv_hw *sh, struct ssv_vif_priv_data *vif_priv, int key_idx)
+ssv6006c_write_hw_group_keyidx	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_write_hw_group_keyidx(struct ssv_hw *sh, struct ssv_vif_priv_data *vif_priv, int key_idx);$/;"	p	file:	signature:(struct ssv_hw *sh, struct ssv_vif_priv_data *vif_priv, int key_idx)
+ssv6006c_write_key_to_hw	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_write_key_to_hw(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv, void *key, int wsid, int key_idx, enum SSV6XXX_WSID_SEC key_type)
+ssv6006c_write_key_to_hw	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_write_key_to_hw(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv,$/;"	p	file:	signature:(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv, void *key, int wsid, int key_idx, enum SSV6XXX_WSID_SEC key_type)
+ssv6006c_write_mac_ini	smac/hal/ssv6006c/ssv6006C_mac.c	/^static int ssv6006c_write_mac_ini(struct ssv_hw *sh){$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6006c_write_pairwise_key_to_hw	smac/hal/ssv6006c/ssv6006C_mac.c	/^static int ssv6006c_write_pairwise_key_to_hw (struct ssv_softc *sc,$/;"	f	file:	signature:(struct ssv_softc *sc, int index, u8 algorithm, const u8 *key, int key_len, struct ieee80211_key_conf *keyconf, struct ssv_vif_priv_data *vif_priv, struct ssv_sta_priv_data *sta_priv)
+ssv6006c_write_pairwise_keyidx_to_hw	smac/hal/ssv6006c/ssv6006C_mac.c	/^static void ssv6006c_write_pairwise_keyidx_to_hw(struct ssv_hw *sh, int key_idx, int wsid)$/;"	f	file:	signature:(struct ssv_hw *sh, int key_idx, int wsid)
+ssv6006dpd	smac/dev.h	/^struct ssv6006dpd{$/;"	s
+ssv6006dpd	smac/hal/ssv6006c/turismo_common.h	/^struct ssv6006dpd{$/;"	s
+ssv6006dpd::am	smac/dev.h	/^    u32 am[MAX_PADPD_TONE\/2];$/;"	m	struct:ssv6006dpd	access:public
+ssv6006dpd::am	smac/hal/ssv6006c/turismo_common.h	/^    u32 am[MAX_PADPD_TONE\/2];$/;"	m	struct:ssv6006dpd	access:public
+ssv6006dpd::pm	smac/dev.h	/^    u32 pm[MAX_PADPD_TONE\/2];$/;"	m	struct:ssv6006dpd	access:public
+ssv6006dpd::pm	smac/hal/ssv6006c/turismo_common.h	/^    u32 pm[MAX_PADPD_TONE\/2];$/;"	m	struct:ssv6006dpd	access:public
+ssv6200_2ghz_chantable	smac/init.c	/^static const struct ieee80211_channel ssv6200_2ghz_chantable[] =$/;"	v	typeref:struct:ieee80211_channel	file:
+ssv6200_5ghz_chantable	smac/init.c	/^static struct ieee80211_channel ssv6200_5ghz_chantable[] = {$/;"	v	typeref:struct:ieee80211_channel	file:
+ssv6200_add_interface	smac/dev.c	/^static int ssv6200_add_interface(struct ieee80211_hw *hw,$/;"	f	file:	signature:(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
+ssv6200_ampdu_BA_handler	smac/ampdu.c	/^void ssv6200_ampdu_BA_handler (struct ieee80211_hw *hw, struct sk_buff *skb)$/;"	f	signature:(struct ieee80211_hw *hw, struct sk_buff *skb)
+ssv6200_ampdu_BA_handler	smac/ampdu.h	/^void ssv6200_ampdu_BA_handler(struct ieee80211_hw *hw, struct sk_buff *skb);$/;"	p	signature:(struct ieee80211_hw *hw, struct sk_buff *skb)
+ssv6200_ampdu_action	smac/dev.c	/^static int ssv6200_ampdu_action(struct ieee80211_hw *hw,$/;"	f	file:	signature:(struct ieee80211_hw *hw, struct ieee80211_vif *vif, enum ieee80211_ampdu_mlme_action action, struct ieee80211_sta *sta, u16 tid, u16 *ssn)
+ssv6200_ampdu_add_delimiter_and_crc32	smac/ampdu.c	/^static bool ssv6200_ampdu_add_delimiter_and_crc32 (struct sk_buff *mpdu)$/;"	f	file:	signature:(struct sk_buff *mpdu)
+ssv6200_ampdu_add_txinfo_and_send_HCI	smac/ampdu.c	/^static void ssv6200_ampdu_add_txinfo_and_send_HCI (struct ssv_softc *sc,$/;"	f	file:	signature:(struct ssv_softc *sc, struct sk_buff *ampdu_skb, u32 tx_flag)
+ssv6200_ampdu_change_retry_frame_rate	smac/ampdu.c	/^static void ssv6200_ampdu_change_retry_frame_rate(struct sk_buff_head *ampdu_skb_retry_queue_p)$/;"	f	file:	signature:(struct sk_buff_head *ampdu_skb_retry_queue_p)
+ssv6200_ampdu_deinit	smac/ampdu.c	/^void ssv6200_ampdu_deinit (struct ieee80211_hw *hw)$/;"	f	signature:(struct ieee80211_hw *hw)
+ssv6200_ampdu_deinit	smac/ampdu.h	/^void ssv6200_ampdu_deinit(struct ieee80211_hw *hw);$/;"	p	signature:(struct ieee80211_hw *hw)
+ssv6200_ampdu_delayed_work_callback_func	smac/ampdu.h	/^void ssv6200_ampdu_delayed_work_callback_func(struct work_struct *work);$/;"	p	signature:(struct work_struct *work)
+ssv6200_ampdu_hw_init	smac/ampdu.c	/^static void ssv6200_ampdu_hw_init (struct ieee80211_hw *hw)$/;"	f	file:	signature:(struct ieee80211_hw *hw)
+ssv6200_ampdu_init	smac/ampdu.c	/^void ssv6200_ampdu_init (struct ieee80211_hw *hw)$/;"	f	signature:(struct ieee80211_hw *hw)
+ssv6200_ampdu_init	smac/ampdu.h	/^void ssv6200_ampdu_init(struct ieee80211_hw *hw);$/;"	p	signature:(struct ieee80211_hw *hw)
+ssv6200_ampdu_no_BA_handler	smac/ampdu.c	/^void ssv6200_ampdu_no_BA_handler (struct ieee80211_hw *hw, struct sk_buff *skb)$/;"	f	signature:(struct ieee80211_hw *hw, struct sk_buff *skb)
+ssv6200_ampdu_no_BA_handler	smac/ampdu.h	/^void ssv6200_ampdu_no_BA_handler(struct ieee80211_hw *hw, struct sk_buff *skb);$/;"	p	signature:(struct ieee80211_hw *hw, struct sk_buff *skb)
+ssv6200_ampdu_release_skb	smac/ampdu.c	/^void ssv6200_ampdu_release_skb (struct sk_buff *skb, struct ieee80211_hw *hw)$/;"	f	signature:(struct sk_buff *skb, struct ieee80211_hw *hw)
+ssv6200_ampdu_release_skb	smac/ampdu.h	/^void ssv6200_ampdu_release_skb(struct sk_buff *skb, struct ieee80211_hw *hw);$/;"	p	signature:(struct sk_buff *skb, struct ieee80211_hw *hw)
+ssv6200_ampdu_rx_start	smac/ampdu.c	/^int ssv6200_ampdu_rx_start(struct ieee80211_hw *hw, struct ieee80211_vif *vif, struct ieee80211_sta *sta,$/;"	f	signature:(struct ieee80211_hw *hw, struct ieee80211_vif *vif, struct ieee80211_sta *sta, u16 tid, u16 *ssn, u8 buf_size)
+ssv6200_ampdu_rx_start	smac/ampdu.h	/^int ssv6200_ampdu_rx_start(struct ieee80211_hw *hw, struct ieee80211_vif *vif, struct ieee80211_sta *sta,$/;"	p	signature:(struct ieee80211_hw *hw, struct ieee80211_vif *vif, struct ieee80211_sta *sta, u16 tid, u16 *ssn, u8 buf_size)
+ssv6200_ampdu_send_retry	smac/ampdu.c	/^static void ssv6200_ampdu_send_retry ($/;"	f	file:	signature:( struct ieee80211_hw *hw, AMPDU_TID *cur_ampdu_tid, struct sk_buff_head *ampdu_skb_retry_queue_p, bool send_aggr_tx)
+ssv6200_ampdu_timeout_tx	smac/ampdu.h	/^void ssv6200_ampdu_timeout_tx (struct ieee80211_hw *hw);$/;"	p	signature:(struct ieee80211_hw *hw)
+ssv6200_ampdu_timer_callback_func	smac/ampdu.h	/^void ssv6200_ampdu_timer_callback_func(unsigned long data);$/;"	p	signature:(unsigned long data)
+ssv6200_ampdu_tx_add_sta	smac/ampdu.c	/^void ssv6200_ampdu_tx_add_sta (struct ieee80211_hw *hw,$/;"	f	signature:(struct ieee80211_hw *hw, struct ieee80211_sta *sta)
+ssv6200_ampdu_tx_add_sta	smac/ampdu.h	/^void ssv6200_ampdu_tx_add_sta(struct ieee80211_hw *hw, struct ieee80211_sta *sta);$/;"	p	signature:(struct ieee80211_hw *hw, struct ieee80211_sta *sta)
+ssv6200_ampdu_tx_handler	smac/ampdu.c	/^bool ssv6200_ampdu_tx_handler (struct ieee80211_hw *hw, struct sk_buff *skb)$/;"	f	signature:(struct ieee80211_hw *hw, struct sk_buff *skb)
+ssv6200_ampdu_tx_handler	smac/ampdu.h	/^bool ssv6200_ampdu_tx_handler(struct ieee80211_hw *hw, struct sk_buff *skb);$/;"	p	signature:(struct ieee80211_hw *hw, struct sk_buff *skb)
+ssv6200_ampdu_tx_init_debugfs	smac/ampdu.c	/^static void ssv6200_ampdu_tx_init_debugfs ($/;"	f	file:	signature:( struct ssv_softc *sc, struct ssv_sta_priv_data *ssv_sta_priv)
+ssv6200_ampdu_tx_operation	smac/ampdu.c	/^void ssv6200_ampdu_tx_operation (u16 tid, struct ieee80211_sta *sta,$/;"	f	signature:(u16 tid, struct ieee80211_sta *sta, struct ieee80211_hw *hw, u8 buffer_size)
+ssv6200_ampdu_tx_operation	smac/ampdu.h	/^void ssv6200_ampdu_tx_operation(u16 tid, struct ieee80211_sta *sta, struct ieee80211_hw *hw, u8 buffer_size);$/;"	p	signature:(u16 tid, struct ieee80211_sta *sta, struct ieee80211_hw *hw, u8 buffer_size)
+ssv6200_ampdu_tx_start	smac/ampdu.c	/^void ssv6200_ampdu_tx_start (u16 tid, struct ieee80211_sta *sta,$/;"	f	signature:(u16 tid, struct ieee80211_sta *sta, struct ieee80211_hw *hw, u16 *ssn)
+ssv6200_ampdu_tx_start	smac/ampdu.h	/^void ssv6200_ampdu_tx_start(u16 tid, struct ieee80211_sta *sta, struct ieee80211_hw *hw, u16 *ssn);$/;"	p	signature:(u16 tid, struct ieee80211_sta *sta, struct ieee80211_hw *hw, u16 *ssn)
+ssv6200_ampdu_tx_state_operation_func	smac/ampdu.c	/^static void ssv6200_ampdu_tx_state_operation_func ($/;"	f	file:	signature:( struct ssv_softc *sc, struct ieee80211_sta *sta, struct sk_buff *skb, struct AMPDU_TID_st *cur_AMPDU_TID)
+ssv6200_ampdu_tx_state_stop_func	smac/ampdu.c	/^static void ssv6200_ampdu_tx_state_stop_func ($/;"	f	file:	signature:( struct ssv_softc *sc, struct ieee80211_sta *sta, struct sk_buff *skb, struct AMPDU_TID_st *cur_AMPDU_TID)
+ssv6200_ampdu_tx_stop	smac/ampdu.c	/^void ssv6200_ampdu_tx_stop (u16 tid, struct ieee80211_sta *sta,$/;"	f	signature:(u16 tid, struct ieee80211_sta *sta, struct ieee80211_hw *hw)
+ssv6200_ampdu_tx_stop	smac/ampdu.h	/^void ssv6200_ampdu_tx_stop(u16 tid, struct ieee80211_sta *sta, struct ieee80211_hw *hw);$/;"	p	signature:(u16 tid, struct ieee80211_sta *sta, struct ieee80211_hw *hw)
+ssv6200_ampdu_tx_update_state	smac/ampdu.c	/^void ssv6200_ampdu_tx_update_state (void *priv, struct ieee80211_sta *sta,$/;"	f	signature:(void *priv, struct ieee80211_sta *sta, struct sk_buff *skb)
+ssv6200_ampdu_tx_update_state	smac/ampdu.h	/^void ssv6200_ampdu_tx_update_state(void *priv, struct ieee80211_sta *sta, struct sk_buff *skb);$/;"	p	signature:(void *priv, struct ieee80211_sta *sta, struct sk_buff *skb)
+ssv6200_ba_map_walker	smac/ampdu.c	/^u32 ssv6200_ba_map_walker (struct AMPDU_TID_st *ampdu_tid, u32 start_ssn,$/;"	f	signature:(struct AMPDU_TID_st *ampdu_tid, u32 start_ssn, u32 sn_bit_map[2], struct ampdu_ba_notify_data *ba_notify_data, u32 *p_acked_num)
+ssv6200_ba_map_walker	smac/dev.h	/^u32 ssv6200_ba_map_walker (struct AMPDU_TID_st *ampdu_tid, u32 start_ssn,$/;"	p	signature:(struct AMPDU_TID_st *ampdu_tid, u32 start_ssn, u32 sn_bit_map[2], struct ampdu_ba_notify_data *ba_notify_data, u32 *p_acked_num)
+ssv6200_bcast_dequeue	smac/ap.c	/^struct sk_buff* ssv6200_bcast_dequeue(struct ssv6xxx_bcast_txq *bcast_txq, u8 *remain_len)$/;"	f	signature:(struct ssv6xxx_bcast_txq *bcast_txq, u8 *remain_len)
+ssv6200_bcast_dequeue	smac/ap.h	/^struct sk_buff* ssv6200_bcast_dequeue(struct ssv6xxx_bcast_txq *bcast_txq, u8 *remain_len);$/;"	p	signature:(struct ssv6xxx_bcast_txq *bcast_txq, u8 *remain_len)
+ssv6200_bcast_enqueue	smac/ap.c	/^int ssv6200_bcast_enqueue(struct ssv_softc *sc, struct ssv6xxx_bcast_txq *bcast_txq,$/;"	f	signature:(struct ssv_softc *sc, struct ssv6xxx_bcast_txq *bcast_txq, struct sk_buff *skb)
+ssv6200_bcast_enqueue	smac/ap.h	/^int ssv6200_bcast_enqueue(struct ssv_softc *sc, struct ssv6xxx_bcast_txq *bcast_txq, struct sk_buff *skb);$/;"	p	signature:(struct ssv_softc *sc, struct ssv6xxx_bcast_txq *bcast_txq, struct sk_buff *skb)
+ssv6200_bcast_flush	smac/ap.c	/^void ssv6200_bcast_flush(struct ssv_softc *sc, struct ssv6xxx_bcast_txq *bcast_txq)$/;"	f	signature:(struct ssv_softc *sc, struct ssv6xxx_bcast_txq *bcast_txq)
+ssv6200_bcast_queue_len	smac/ap.c	/^int ssv6200_bcast_queue_len(struct ssv6xxx_bcast_txq *bcast_txq)$/;"	f	signature:(struct ssv6xxx_bcast_txq *bcast_txq)
+ssv6200_bcast_queue_len	smac/ap.c	/^int ssv6200_bcast_queue_len(struct ssv6xxx_bcast_txq *bcast_txq);$/;"	p	file:	signature:(struct ssv6xxx_bcast_txq *bcast_txq)
+ssv6200_bcast_queue_len	smac/ap.h	/^int ssv6200_bcast_queue_len(struct ssv6xxx_bcast_txq *bcast_txq);$/;"	p	signature:(struct ssv6xxx_bcast_txq *bcast_txq)
+ssv6200_bcast_start	smac/ap.c	/^void ssv6200_bcast_start(struct ssv_softc *sc)$/;"	f	signature:(struct ssv_softc *sc)
+ssv6200_bcast_start	smac/ap.h	/^void ssv6200_bcast_start(struct ssv_softc *sc);$/;"	p	signature:(struct ssv_softc *sc)
+ssv6200_bcast_start_work	smac/ap.c	/^void ssv6200_bcast_start_work(struct work_struct *work)$/;"	f	signature:(struct work_struct *work)
+ssv6200_bcast_start_work	smac/ap.h	/^void ssv6200_bcast_start_work(struct work_struct *work);$/;"	p	signature:(struct work_struct *work)
+ssv6200_bcast_stop	smac/ap.c	/^void ssv6200_bcast_stop(struct ssv_softc *sc)$/;"	f	signature:(struct ssv_softc *sc)
+ssv6200_bcast_stop	smac/ap.h	/^void ssv6200_bcast_stop(struct ssv_softc *sc);$/;"	p	signature:(struct ssv_softc *sc)
+ssv6200_bcast_stop_work	smac/ap.c	/^void ssv6200_bcast_stop_work(struct work_struct *work)$/;"	f	signature:(struct work_struct *work)
+ssv6200_bcast_stop_work	smac/ap.h	/^void ssv6200_bcast_stop_work(struct work_struct *work);$/;"	p	signature:(struct work_struct *work)
+ssv6200_bcast_tx_work	smac/ap.c	/^void ssv6200_bcast_tx_work(struct work_struct *work)$/;"	f	signature:(struct work_struct *work)
+ssv6200_bcast_tx_work	smac/ap.h	/^void ssv6200_bcast_tx_work(struct work_struct *work);$/;"	p	signature:(struct work_struct *work)
+ssv6200_bss_info_changed	smac/dev.c	/^static void ssv6200_bss_info_changed(struct ieee80211_hw *hw,$/;"	f	file:	signature:(struct ieee80211_hw *hw, struct ieee80211_vif *vif, struct ieee80211_bss_conf *info, u32 changed)
+ssv6200_change_interface	smac/dev.c	/^static int ssv6200_change_interface(struct ieee80211_hw *hw,$/;"	f	file:	signature:(struct ieee80211_hw *hw, struct ieee80211_vif *vif, enum nl80211_iftype new_type, bool p2p)
+ssv6200_conf_tx	smac/dev.c	/^static int ssv6200_conf_tx(struct ieee80211_hw *hw, u16 queue,$/;"	f	file:	signature:(struct ieee80211_hw *hw, u16 queue, const struct ieee80211_tx_queue_params *params)
+ssv6200_config	smac/dev.c	/^static int ssv6200_config(struct ieee80211_hw *hw, u32 changed)$/;"	f	file:	signature:(struct ieee80211_hw *hw, u32 changed)
+ssv6200_config_filter	smac/dev.c	/^static void ssv6200_config_filter(struct ieee80211_hw *hw,$/;"	f	file:	signature:(struct ieee80211_hw *hw, unsigned int changed_flags, unsigned int *total_flags, u64 multicast)
+ssv6200_dump_BA_notification	smac/ampdu.c	/^int ssv6200_dump_BA_notification (char *buf,$/;"	f	signature:(char *buf, struct ampdu_ba_notify_data *ba_notification)
+ssv6200_dump_BA_notification	smac/ampdu.c	/^int ssv6200_dump_BA_notification (char *buf,$/;"	p	file:	signature:(char *buf, struct ampdu_ba_notify_data *ba_notification)
+ssv6200_dump_BA_notification	smac/dev.h	/^int ssv6200_dump_BA_notification (char *buf, struct ampdu_ba_notify_data *ba_notification);$/;"	p	signature:(char *buf, struct ampdu_ba_notify_data *ba_notification)
+ssv6200_get_ampdu_max_transmit_length	smac/ampdu.c	/^int ssv6200_get_ampdu_max_transmit_length(int rate_idx)$/;"	f	signature:(int rate_idx)
+ssv6200_get_tsf	smac/dev.c	/^static u64 ssv6200_get_tsf(struct ieee80211_hw *hw)$/;"	f	file:	signature:(struct ieee80211_hw *hw)
+ssv6200_hw_get_pair_type	smac/dev.c	/^static u32 ssv6200_hw_get_pair_type(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6200_hw_set_group_type	smac/dev.c	/^static void ssv6200_hw_set_group_type(struct ssv_hw *sh,u8 type)$/;"	f	file:	signature:(struct ssv_hw *sh,u8 type)
+ssv6200_hw_set_pair_type	smac/dev.c	/^static void ssv6200_hw_set_pair_type(struct ssv_hw *sh,u8 type)$/;"	f	file:	signature:(struct ssv_hw *sh,u8 type)
+ssv6200_hw_set_rx_ba_session	smac/ampdu.c	/^static void ssv6200_hw_set_rx_ba_session (struct ssv_hw *sh, bool on, u8 *ta,$/;"	f	file:	signature:(struct ssv_hw *sh, bool on, u8 *ta, u16 tid, u16 ssn, u8 buf_size)
+ssv6200_is_rx_q_full	smac/dev.c	/^int ssv6200_is_rx_q_full(void *args)$/;"	f	signature:(void *args)
+ssv6200_is_rx_q_full	smac/dev.h	/^int ssv6200_is_rx_q_full(void *args);$/;"	p	signature:(void *args)
+ssv6200_legacy_rates	smac/init.c	/^static struct ieee80211_rate ssv6200_legacy_rates[] =$/;"	v	typeref:struct:ieee80211_rate	file:
+ssv6200_not_dual_intf_on_line	smac/dev.c	/^static bool ssv6200_not_dual_intf_on_line(struct ssv_softc *sc)$/;"	f	file:	signature:(struct ssv_softc *sc)
+ssv6200_ops	smac/dev.c	/^struct ieee80211_ops ssv6200_ops =$/;"	v	typeref:struct:ieee80211_ops
+ssv6200_phy_tbl	smac/dev_tbl.h	22;"	d
+ssv6200_release_bcast_frame_res	smac/ap.c	/^void ssv6200_release_bcast_frame_res(struct ssv_softc *sc, struct ieee80211_vif *vif)$/;"	f	signature:(struct ssv_softc *sc, struct ieee80211_vif *vif)
+ssv6200_release_bcast_frame_res	smac/ap.h	/^void ssv6200_release_bcast_frame_res(struct ssv_softc *sc, struct ieee80211_vif *vif);$/;"	p	signature:(struct ssv_softc *sc, struct ieee80211_vif *vif)
+ssv6200_remove_interface	smac/dev.c	/^static void ssv6200_remove_interface(struct ieee80211_hw *hw,$/;"	f	file:	signature:(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
+ssv6200_rf_tbl	smac/dev_tbl.h	24;"	d
+ssv6200_rf_tbl	smac/dev_tbl.h	26;"	d
+ssv6200_rf_tbl	smac/dev_tbl.h	27;"	d
+ssv6200_rx	smac/dev.c	/^int ssv6200_rx(struct sk_buff_head *rx_skb_q, void *args)$/;"	f	signature:(struct sk_buff_head *rx_skb_q, void *args)
+ssv6200_rx	smac/dev.h	/^int ssv6200_rx(struct sk_buff *rx_skb, void *args);$/;"	p	signature:(struct sk_buff *rx_skb, void *args)
+ssv6200_rx	smac/dev.h	/^int ssv6200_rx(struct sk_buff_head *rx_skb_q, void *args);$/;"	p	signature:(struct sk_buff_head *rx_skb_q, void *args)
+ssv6200_rx_desc	include/ssv6200_common.h	/^struct ssv6200_rx_desc$/;"	s
+ssv6200_rx_desc::RSVD_0	include/ssv6200_common.h	/^    u32 RSVD_0:2;$/;"	m	struct:ssv6200_rx_desc	access:public
+ssv6200_rx_desc::RSVD_1	include/ssv6200_common.h	/^    u32 RSVD_1:1;$/;"	m	struct:ssv6200_rx_desc	access:public
+ssv6200_rx_desc::RSVD_3	include/ssv6200_common.h	/^    u32 RSVD_3:3;$/;"	m	struct:ssv6200_rx_desc	access:public
+ssv6200_rx_desc::RxResult	include/ssv6200_common.h	/^    u32 RxResult:8;$/;"	m	struct:ssv6200_rx_desc	access:public
+ssv6200_rx_desc::align2	include/ssv6200_common.h	/^    u32 align2:1;$/;"	m	struct:ssv6200_rx_desc	access:public
+ssv6200_rx_desc::c_type	include/ssv6200_common.h	/^    u32 c_type:3;$/;"	m	struct:ssv6200_rx_desc	access:public
+ssv6200_rx_desc::edca0_used	include/ssv6200_common.h	/^    u32 edca0_used:4;$/;"	m	struct:ssv6200_rx_desc	access:public
+ssv6200_rx_desc::edca1_used	include/ssv6200_common.h	/^    u32 edca1_used:5;$/;"	m	struct:ssv6200_rx_desc	access:public
+ssv6200_rx_desc::edca2_used	include/ssv6200_common.h	/^    u32 edca2_used:5;$/;"	m	struct:ssv6200_rx_desc	access:public
+ssv6200_rx_desc::edca3_used	include/ssv6200_common.h	/^    u32 edca3_used:5;$/;"	m	struct:ssv6200_rx_desc	access:public
+ssv6200_rx_desc::extra_info	include/ssv6200_common.h	/^    u32 extra_info:1;$/;"	m	struct:ssv6200_rx_desc	access:public
+ssv6200_rx_desc::f80211	include/ssv6200_common.h	/^    u32 f80211:1;$/;"	m	struct:ssv6200_rx_desc	access:public
+ssv6200_rx_desc::fCmdIdx	include/ssv6200_common.h	/^    u32 fCmdIdx:3;$/;"	m	struct:ssv6200_rx_desc	access:public
+ssv6200_rx_desc::frag	include/ssv6200_common.h	/^    u32 frag:1;$/;"	m	struct:ssv6200_rx_desc	access:public
+ssv6200_rx_desc::hdr_len	include/ssv6200_common.h	/^    u32 hdr_len:6;$/;"	m	struct:ssv6200_rx_desc	access:public
+ssv6200_rx_desc::hdr_offset	include/ssv6200_common.h	/^    u32 hdr_offset:8;$/;"	m	struct:ssv6200_rx_desc	access:public
+ssv6200_rx_desc::ht	include/ssv6200_common.h	/^    u32 ht:1;$/;"	m	struct:ssv6200_rx_desc	access:public
+ssv6200_rx_desc::l3cs_err	include/ssv6200_common.h	/^    u32 l3cs_err:1;$/;"	m	struct:ssv6200_rx_desc	access:public
+ssv6200_rx_desc::l4cs_err	include/ssv6200_common.h	/^    u32 l4cs_err:1;$/;"	m	struct:ssv6200_rx_desc	access:public
+ssv6200_rx_desc::len	include/ssv6200_common.h	/^    u32 len:16;$/;"	m	struct:ssv6200_rx_desc	access:public
+ssv6200_rx_desc::mng_used	include/ssv6200_common.h	/^    u32 mng_used:4;$/;"	m	struct:ssv6200_rx_desc	access:public
+ssv6200_rx_desc::payload_offset	include/ssv6200_common.h	/^    u32 payload_offset:8;$/;"	m	struct:ssv6200_rx_desc	access:public
+ssv6200_rx_desc::psm	include/ssv6200_common.h	/^    u32 psm:1;$/;"	m	struct:ssv6200_rx_desc	access:public
+ssv6200_rx_desc::qos	include/ssv6200_common.h	/^    u32 qos:1;$/;"	m	struct:ssv6200_rx_desc	access:public
+ssv6200_rx_desc::rate_idx	include/ssv6200_common.h	/^    u32 rate_idx:6;$/;"	m	struct:ssv6200_rx_desc	access:public
+ssv6200_rx_desc::reason	include/ssv6200_common.h	/^    u32 reason:6;$/;"	m	struct:ssv6200_rx_desc	access:public
+ssv6200_rx_desc::stype_b5b4	include/ssv6200_common.h	/^    u32 stype_b5b4:2;$/;"	m	struct:ssv6200_rx_desc	access:public
+ssv6200_rx_desc::tx_id_used	include/ssv6200_common.h	/^    u32 tx_id_used:8;$/;"	m	struct:ssv6200_rx_desc	access:public
+ssv6200_rx_desc::tx_page_used	include/ssv6200_common.h	/^    u32 tx_page_used:9;$/;"	m	struct:ssv6200_rx_desc	access:public
+ssv6200_rx_desc::unicast	include/ssv6200_common.h	/^    u32 unicast:1;$/;"	m	struct:ssv6200_rx_desc	access:public
+ssv6200_rx_desc::use_4addr	include/ssv6200_common.h	/^    u32 use_4addr:1;$/;"	m	struct:ssv6200_rx_desc	access:public
+ssv6200_rx_desc::wildcard_bssid	include/ssv6200_common.h	/^    u32 wildcard_bssid:1;$/;"	m	struct:ssv6200_rx_desc	access:public
+ssv6200_rx_desc::wsid	include/ssv6200_common.h	/^    u32 wsid:4;$/;"	m	struct:ssv6200_rx_desc	access:public
+ssv6200_rx_flow_check	smac/dev.c	/^void ssv6200_rx_flow_check(struct ssv_sta_priv_data *sta_priv_dat,$/;"	f	signature:(struct ssv_sta_priv_data *sta_priv_dat, struct ssv_softc *sc)
+ssv6200_rx_process	smac/dev.h	/^void ssv6200_rx_process(struct work_struct *work);$/;"	p	signature:(struct work_struct *work)
+ssv6200_rxphy_info	include/ssv6200_common.h	/^struct ssv6200_rxphy_info {$/;"	s
+ssv6200_rxphy_info::aggregate	include/ssv6200_common.h	/^    u32 aggregate:1;$/;"	m	struct:ssv6200_rxphy_info	access:public
+ssv6200_rxphy_info::ch_bw	include/ssv6200_common.h	/^    u32 ch_bw:3;$/;"	m	struct:ssv6200_rxphy_info	access:public
+ssv6200_rxphy_info::fec	include/ssv6200_common.h	/^    u32 fec:1;$/;"	m	struct:ssv6200_rxphy_info	access:public
+ssv6200_rxphy_info::ht_short_gi	include/ssv6200_common.h	/^    u32 ht_short_gi:1;$/;"	m	struct:ssv6200_rxphy_info	access:public
+ssv6200_rxphy_info::l_length	include/ssv6200_common.h	/^    u32 l_length:12;$/;"	m	struct:ssv6200_rxphy_info	access:public
+ssv6200_rxphy_info::l_rate	include/ssv6200_common.h	/^    u32 l_rate:3;$/;"	m	struct:ssv6200_rxphy_info	access:public
+ssv6200_rxphy_info::len	include/ssv6200_common.h	/^    u32 len:16;$/;"	m	struct:ssv6200_rxphy_info	access:public
+ssv6200_rxphy_info::mode	include/ssv6200_common.h	/^    u32 mode:3;$/;"	m	struct:ssv6200_rxphy_info	access:public
+ssv6200_rxphy_info::n_ess	include/ssv6200_common.h	/^    u32 n_ess:2;$/;"	m	struct:ssv6200_rxphy_info	access:public
+ssv6200_rxphy_info::no_sounding	include/ssv6200_common.h	/^    u32 no_sounding:1;$/;"	m	struct:ssv6200_rxphy_info	access:public
+ssv6200_rxphy_info::preamble	include/ssv6200_common.h	/^    u32 preamble:1;$/;"	m	struct:ssv6200_rxphy_info	access:public
+ssv6200_rxphy_info::rate	include/ssv6200_common.h	/^    u32 rate:7;$/;"	m	struct:ssv6200_rxphy_info	access:public
+ssv6200_rxphy_info::rpci	include/ssv6200_common.h	/^    u32 rpci:8;$/;"	m	struct:ssv6200_rxphy_info	access:public
+ssv6200_rxphy_info::rsvd0	include/ssv6200_common.h	/^    u32 rsvd0:16;$/;"	m	struct:ssv6200_rxphy_info	access:public
+ssv6200_rxphy_info::rsvd1	include/ssv6200_common.h	/^    u32 rsvd1:1;$/;"	m	struct:ssv6200_rxphy_info	access:public
+ssv6200_rxphy_info::rsvd2	include/ssv6200_common.h	/^    u32 rsvd2:8;$/;"	m	struct:ssv6200_rxphy_info	access:public
+ssv6200_rxphy_info::rsvd3	include/ssv6200_common.h	/^    u32 rsvd3:17;$/;"	m	struct:ssv6200_rxphy_info	access:public
+ssv6200_rxphy_info::rsvd4	include/ssv6200_common.h	/^    u32 rsvd4;$/;"	m	struct:ssv6200_rxphy_info	access:public
+ssv6200_rxphy_info::service	include/ssv6200_common.h	/^    u32 service:16;$/;"	m	struct:ssv6200_rxphy_info	access:public
+ssv6200_rxphy_info::smoothing	include/ssv6200_common.h	/^    u32 smoothing:1;$/;"	m	struct:ssv6200_rxphy_info	access:public
+ssv6200_rxphy_info::snr	include/ssv6200_common.h	/^    u32 snr:8;$/;"	m	struct:ssv6200_rxphy_info	access:public
+ssv6200_rxphy_info::stbc	include/ssv6200_common.h	/^    u32 stbc:2;$/;"	m	struct:ssv6200_rxphy_info	access:public
+ssv6200_rxphy_info_padding	include/ssv6200_common.h	/^struct ssv6200_rxphy_info_padding {$/;"	s
+ssv6200_rxphy_info_padding::RSVD	include/ssv6200_common.h	/^u32 RSVD:16;$/;"	m	struct:ssv6200_rxphy_info_padding	access:public
+ssv6200_rxphy_info_padding::rpci	include/ssv6200_common.h	/^u32 rpci:8;$/;"	m	struct:ssv6200_rxphy_info_padding	access:public
+ssv6200_rxphy_info_padding::snr	include/ssv6200_common.h	/^u32 snr:8;$/;"	m	struct:ssv6200_rxphy_info_padding	access:public
+ssv6200_set_default_unicast_key	smac/dev.c	/^void ssv6200_set_default_unicast_key(struct ieee80211_hw *hw,$/;"	f	signature:(struct ieee80211_hw *hw, struct ieee80211_vif *vif, int idx)
+ssv6200_set_key	smac/dev.c	/^static int ssv6200_set_key(struct ieee80211_hw *hw,$/;"	f	file:	signature:(struct ieee80211_hw *hw, enum set_key_cmd cmd, struct ieee80211_vif *vif, struct ieee80211_sta *sta, struct ieee80211_key_conf *key)
+ssv6200_set_tim	smac/dev.c	/^static int ssv6200_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta,$/;"	f	file:	signature:(struct ieee80211_hw *hw, struct ieee80211_sta *sta, bool set)
+ssv6200_set_tim_work	smac/ap.c	/^void ssv6200_set_tim_work(struct work_struct *work)$/;"	f	signature:(struct work_struct *work)
+ssv6200_set_tim_work	smac/ap.h	/^void ssv6200_set_tim_work(struct work_struct *work);$/;"	p	signature:(struct work_struct *work)
+ssv6200_sta_add	smac/dev.c	/^static int ssv6200_sta_add(struct ieee80211_hw *hw,$/;"	f	file:	signature:(struct ieee80211_hw *hw, struct ieee80211_vif *vif, struct ieee80211_sta *sta)
+ssv6200_sta_notify	smac/dev.c	/^static void ssv6200_sta_notify(struct ieee80211_hw *hw,$/;"	f	file:	signature:(struct ieee80211_hw *hw, struct ieee80211_vif *vif, enum sta_notify_cmd cmd, struct ieee80211_sta *sta)
+ssv6200_sta_remove	smac/dev.c	/^static int ssv6200_sta_remove(struct ieee80211_hw *hw,$/;"	f	file:	signature:(struct ieee80211_hw *hw, struct ieee80211_vif *vif, struct ieee80211_sta *sta)
+ssv6200_start	smac/dev.c	/^static int ssv6200_start(struct ieee80211_hw *hw)$/;"	f	file:	signature:(struct ieee80211_hw *hw)
+ssv6200_stop	smac/dev.c	/^static void ssv6200_stop(struct ieee80211_hw *hw)$/;"	f	file:	signature:(struct ieee80211_hw *hw)
+ssv6200_sw_scan_complete	smac/dev.c	/^static void ssv6200_sw_scan_complete(struct ieee80211_hw *hw,$/;"	f	file:	signature:(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
+ssv6200_sw_scan_start	smac/dev.c	/^static void ssv6200_sw_scan_start(struct ieee80211_hw *hw,$/;"	f	file:	signature:(struct ieee80211_hw *hw, struct ieee80211_vif *vif, const u8 *mac_addr)
+ssv6200_sync_hw_key_sequence	smac/dev.h	/^void ssv6200_sync_hw_key_sequence(struct ssv_softc *sc, struct ssv_sta_info* sta_info, bool bWrite);$/;"	p	signature:(struct ssv_softc *sc, struct ssv_sta_info* sta_info, bool bWrite)
+ssv6200_tx	smac/dev.c	/^static int ssv6200_tx(struct ieee80211_hw *hw, struct sk_buff *skb)$/;"	f	file:	signature:(struct ieee80211_hw *hw, struct sk_buff *skb)
+ssv6200_tx_desc	include/ssv6200_common.h	/^struct ssv6200_tx_desc$/;"	s
+ssv6200_tx_desc::RESERVED	include/ssv6200_common.h	/^    u32 RESERVED[8];$/;"	m	struct:ssv6200_tx_desc	access:public
+ssv6200_tx_desc::RSVD_0	include/ssv6200_common.h	/^    u32 RSVD_0:3;$/;"	m	struct:ssv6200_tx_desc	access:public
+ssv6200_tx_desc::RSVD_1	include/ssv6200_common.h	/^    u32 RSVD_1:3;$/;"	m	struct:ssv6200_tx_desc	access:public
+ssv6200_tx_desc::RSVD_2	include/ssv6200_common.h	/^    u32 RSVD_2:1;$/;"	m	struct:ssv6200_tx_desc	access:public
+ssv6200_tx_desc::RSVD_3	include/ssv6200_common.h	/^    u32 RSVD_3:14;$/;"	m	struct:ssv6200_tx_desc	access:public
+ssv6200_tx_desc::RSVD_4	include/ssv6200_common.h	/^    u32 RSVD_4:7;$/;"	m	struct:ssv6200_tx_desc	access:public
+ssv6200_tx_desc::TxF_ID	include/ssv6200_common.h	/^    u32 TxF_ID:6;$/;"	m	struct:ssv6200_tx_desc	access:public
+ssv6200_tx_desc::ack_policy	include/ssv6200_common.h	/^    u32 ack_policy:2;$/;"	m	struct:ssv6200_tx_desc	access:public
+ssv6200_tx_desc::aggregation	include/ssv6200_common.h	/^    u32 aggregation:1;$/;"	m	struct:ssv6200_tx_desc	access:public
+ssv6200_tx_desc::bc_que	include/ssv6200_common.h	/^    u32 bc_que:1;$/;"	m	struct:ssv6200_tx_desc	access:public
+ssv6200_tx_desc::c_type	include/ssv6200_common.h	/^    u32 c_type:3;$/;"	m	struct:ssv6200_tx_desc	access:public
+ssv6200_tx_desc::crate_idx	include/ssv6200_common.h	/^    u32 crate_idx:6;$/;"	m	struct:ssv6200_tx_desc	access:public
+ssv6200_tx_desc::dl_length	include/ssv6200_common.h	/^    u32 dl_length:12;$/;"	m	struct:ssv6200_tx_desc	access:public
+ssv6200_tx_desc::do_rts_cts	include/ssv6200_common.h	/^    u32 do_rts_cts:2;$/;"	m	struct:ssv6200_tx_desc	access:public
+ssv6200_tx_desc::drate_idx	include/ssv6200_common.h	/^    u32 drate_idx:6;$/;"	m	struct:ssv6200_tx_desc	access:public
+ssv6200_tx_desc::extra_info	include/ssv6200_common.h	/^    u32 extra_info:1;$/;"	m	struct:ssv6200_tx_desc	access:public
+ssv6200_tx_desc::f80211	include/ssv6200_common.h	/^    u32 f80211:1;$/;"	m	struct:ssv6200_tx_desc	access:public
+ssv6200_tx_desc::fCmd	include/ssv6200_common.h	/^    u32 fCmd;$/;"	m	struct:ssv6200_tx_desc	access:public
+ssv6200_tx_desc::fCmdIdx	include/ssv6200_common.h	/^    u32 fCmdIdx:3;$/;"	m	struct:ssv6200_tx_desc	access:public
+ssv6200_tx_desc::frag	include/ssv6200_common.h	/^    u32 frag:1;$/;"	m	struct:ssv6200_tx_desc	access:public
+ssv6200_tx_desc::frame_consume_time	include/ssv6200_common.h	/^    u32 frame_consume_time:10;$/;"	m	struct:ssv6200_tx_desc	access:public
+ssv6200_tx_desc::hdr_len	include/ssv6200_common.h	/^    u32 hdr_len:6;$/;"	m	struct:ssv6200_tx_desc	access:public
+ssv6200_tx_desc::hdr_offset	include/ssv6200_common.h	/^    u32 hdr_offset:8;$/;"	m	struct:ssv6200_tx_desc	access:public
+ssv6200_tx_desc::ht	include/ssv6200_common.h	/^    u32 ht:1;$/;"	m	struct:ssv6200_tx_desc	access:public
+ssv6200_tx_desc::len	include/ssv6200_common.h	/^    u32 len:16;$/;"	m	struct:ssv6200_tx_desc	access:public
+ssv6200_tx_desc::more_data	include/ssv6200_common.h	/^    u32 more_data:1;$/;"	m	struct:ssv6200_tx_desc	access:public
+ssv6200_tx_desc::payload_offset	include/ssv6200_common.h	/^    u32 payload_offset:8;$/;"	m	struct:ssv6200_tx_desc	access:public
+ssv6200_tx_desc::qos	include/ssv6200_common.h	/^    u32 qos:1;$/;"	m	struct:ssv6200_tx_desc	access:public
+ssv6200_tx_desc::rc_params	include/ssv6200_common.h	/^    struct fw_rc_retry_params rc_params[SSV62XX_TX_MAX_RATES];$/;"	m	struct:ssv6200_tx_desc	typeref:struct:ssv6200_tx_desc::fw_rc_retry_params	access:public
+ssv6200_tx_desc::reason	include/ssv6200_common.h	/^    u32 reason:6;$/;"	m	struct:ssv6200_tx_desc	access:public
+ssv6200_tx_desc::rts_cts_nav	include/ssv6200_common.h	/^    u32 rts_cts_nav:16;$/;"	m	struct:ssv6200_tx_desc	access:public
+ssv6200_tx_desc::security	include/ssv6200_common.h	/^    u32 security:1;$/;"	m	struct:ssv6200_tx_desc	access:public
+ssv6200_tx_desc::stype_b5b4	include/ssv6200_common.h	/^    u32 stype_b5b4:2;$/;"	m	struct:ssv6200_tx_desc	access:public
+ssv6200_tx_desc::tx_burst	include/ssv6200_common.h	/^    u32 tx_burst:1;$/;"	m	struct:ssv6200_tx_desc	access:public
+ssv6200_tx_desc::tx_report	include/ssv6200_common.h	/^    u32 tx_report:1;$/;"	m	struct:ssv6200_tx_desc	access:public
+ssv6200_tx_desc::txq_idx	include/ssv6200_common.h	/^    u32 txq_idx:3;$/;"	m	struct:ssv6200_tx_desc	access:public
+ssv6200_tx_desc::unicast	include/ssv6200_common.h	/^    u32 unicast:1;$/;"	m	struct:ssv6200_tx_desc	access:public
+ssv6200_tx_desc::use_4addr	include/ssv6200_common.h	/^    u32 use_4addr:1;$/;"	m	struct:ssv6200_tx_desc	access:public
+ssv6200_tx_desc::wsid	include/ssv6200_common.h	/^    u32 wsid:4;$/;"	m	struct:ssv6200_tx_desc	access:public
+ssv6200_tx_flow_control	smac/dev.c	/^int ssv6200_tx_flow_control(void *dev, int hw_txqid, bool fc_en,int debug)$/;"	f	signature:(void *dev, int hw_txqid, bool fc_en,int debug)
+ssv6200_tx_flow_control	smac/dev.h	/^int ssv6200_tx_flow_control(void *dev, int hw_txqid, bool fc_en, int debug);$/;"	p	signature:(void *dev, int hw_txqid, bool fc_en, int debug)
+ssv6200_txphy_info	include/ssv6200_common.h	/^struct ssv6200_txphy_info {$/;"	s
+ssv6200_txphy_info::rsvd	include/ssv6200_common.h	/^    u32 rsvd[7];$/;"	m	struct:ssv6200_txphy_info	access:public
+ssv62xx_ht	smac/ssv_rc_common.h	/^struct ssv62xx_ht {$/;"	s
+ssv62xx_ht::ampdu_len	smac/ssv_rc_common.h	/^    unsigned int ampdu_len;$/;"	m	struct:ssv62xx_ht	access:public
+ssv62xx_ht::ampdu_packets	smac/ssv_rc_common.h	/^    unsigned int ampdu_packets;$/;"	m	struct:ssv62xx_ht	access:public
+ssv62xx_ht::avg_ampdu_len	smac/ssv_rc_common.h	/^    unsigned int avg_ampdu_len;$/;"	m	struct:ssv62xx_ht	access:public
+ssv62xx_ht::first_try_count	smac/ssv_rc_common.h	/^    int first_try_count;$/;"	m	struct:ssv62xx_ht	access:public
+ssv62xx_ht::groups	smac/ssv_rc_common.h	/^    struct minstrel_mcs_group_data groups;$/;"	m	struct:ssv62xx_ht	typeref:struct:ssv62xx_ht::minstrel_mcs_group_data	access:public
+ssv62xx_ht::max_prob_rate	smac/ssv_rc_common.h	/^    unsigned int max_prob_rate;$/;"	m	struct:ssv62xx_ht	access:public
+ssv62xx_ht::max_tp_rate	smac/ssv_rc_common.h	/^    unsigned int max_tp_rate;$/;"	m	struct:ssv62xx_ht	access:public
+ssv62xx_ht::max_tp_rate2	smac/ssv_rc_common.h	/^    unsigned int max_tp_rate2;$/;"	m	struct:ssv62xx_ht	access:public
+ssv62xx_ht::other_try_count	smac/ssv_rc_common.h	/^    int other_try_count;$/;"	m	struct:ssv62xx_ht	access:public
+ssv62xx_ht::overhead	smac/ssv_rc_common.h	/^    unsigned int overhead;$/;"	m	struct:ssv62xx_ht	access:public
+ssv62xx_ht::overhead_rtscts	smac/ssv_rc_common.h	/^    unsigned int overhead_rtscts;$/;"	m	struct:ssv62xx_ht	access:public
+ssv62xx_ht::sample_count	smac/ssv_rc_common.h	/^    u8 sample_count;$/;"	m	struct:ssv62xx_ht	access:public
+ssv62xx_ht::sample_packets	smac/ssv_rc_common.h	/^    unsigned int sample_packets;$/;"	m	struct:ssv62xx_ht	access:public
+ssv62xx_ht::sample_slow	smac/ssv_rc_common.h	/^    u8 sample_slow;$/;"	m	struct:ssv62xx_ht	access:public
+ssv62xx_ht::sample_tries	smac/ssv_rc_common.h	/^    u8 sample_tries;$/;"	m	struct:ssv62xx_ht	access:public
+ssv62xx_ht::sample_wait	smac/ssv_rc_common.h	/^    u8 sample_wait;$/;"	m	struct:ssv62xx_ht	access:public
+ssv62xx_ht::second_try_count	smac/ssv_rc_common.h	/^    int second_try_count;$/;"	m	struct:ssv62xx_ht	access:public
+ssv62xx_ht::stats_update	smac/ssv_rc_common.h	/^    unsigned long stats_update;$/;"	m	struct:ssv62xx_ht	access:public
+ssv62xx_ht::total_packets	smac/ssv_rc_common.h	/^    unsigned int total_packets;$/;"	m	struct:ssv62xx_ht	access:public
+ssv62xx_ht_rate_update	smac/ssv_ht_rc.c	/^s32 ssv62xx_ht_rate_update(struct sk_buff *skb, struct ssv_softc *sc, struct fw_rc_retry_params *ar)$/;"	f	signature:(struct sk_buff *skb, struct ssv_softc *sc, struct fw_rc_retry_params *ar)
+ssv62xx_ht_rate_update	smac/ssv_ht_rc.h	/^s32 ssv62xx_ht_rate_update(struct sk_buff *skb, struct ssv_softc *sc, struct fw_rc_retry_params *ar);$/;"	p	signature:(struct sk_buff *skb, struct ssv_softc *sc, struct fw_rc_retry_params *ar)
+ssv62xx_ht_rc_caps	smac/ssv_ht_rc.c	/^void ssv62xx_ht_rc_caps(const u16 ssv6xxx_rc_rate_set[RC_TYPE_MAX][13],struct ssv_sta_rc_info *rc_sta)$/;"	f	signature:(const u16 ssv6xxx_rc_rate_set[RC_TYPE_MAX][13],struct ssv_sta_rc_info *rc_sta)
+ssv62xx_ht_rc_caps	smac/ssv_ht_rc.h	/^void ssv62xx_ht_rc_caps(const u16 ssv6xxx_rc_rate_set[RC_TYPE_MAX][13],struct ssv_sta_rc_info *rc_sta);$/;"	p	signature:(const u16 ssv6xxx_rc_rate_set[RC_TYPE_MAX][13],struct ssv_sta_rc_info *rc_sta)
+ssv62xx_noa_evt	include/ssv6xxx_common.h	/^struct ssv62xx_noa_evt {$/;"	s
+ssv62xx_noa_evt::evt_id	include/ssv6xxx_common.h	/^    u8 evt_id;$/;"	m	struct:ssv62xx_noa_evt	access:public
+ssv62xx_noa_evt::vif	include/ssv6xxx_common.h	/^    u8 vif;$/;"	m	struct:ssv62xx_noa_evt	access:public
+ssv62xx_rc_caps	smac/ssv_rc.c	/^static void ssv62xx_rc_caps(struct ssv_sta_rc_info *rc_sta)$/;"	f	file:	signature:(struct ssv_sta_rc_info *rc_sta)
+ssv62xx_tx_rate	include/ssv6200_common.h	/^struct ssv62xx_tx_rate {$/;"	s
+ssv62xx_tx_rate::count	include/ssv6200_common.h	/^    u8 count;$/;"	m	struct:ssv62xx_tx_rate	access:public
+ssv62xx_tx_rate::data_rate	include/ssv6200_common.h	/^    s8 data_rate;$/;"	m	struct:ssv62xx_tx_rate	access:public
+ssv6xxx_add_fw_wsid	smac/dev.c	/^static void ssv6xxx_add_fw_wsid(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv, struct ieee80211_sta *sta, struct ssv_sta_info *sta_info)
+ssv6xxx_add_txinfo	smac/dev.c	/^void ssv6xxx_add_txinfo (struct ssv_softc *sc, struct sk_buff *skb)$/;"	f	signature:(struct ssv_softc *sc, struct sk_buff *skb)
+ssv6xxx_add_txinfo	smac/dev.h	/^void ssv6xxx_add_txinfo(struct ssv_softc *sc, struct sk_buff *skb);$/;"	p	signature:(struct ssv_softc *sc, struct sk_buff *skb)
+ssv6xxx_adjust_rx_burstread_sztype	smac/dev.c	/^static void ssv6xxx_adjust_rx_burstread_sztype(struct ssv_softc *sc, struct sk_buff *skb)$/;"	f	file:	signature:(struct ssv_softc *sc, struct sk_buff *skb)
+ssv6xxx_aggr_frame_is_last	smac/dev.c	/^static bool ssv6xxx_aggr_frame_is_last(unsigned char *data, int offset, int length)$/;"	f	file:	signature:(unsigned char *data, int offset, int length)
+ssv6xxx_ampdu2mpdu	smac/ampdu.c	/^void ssv6xxx_ampdu2mpdu(struct ieee80211_hw *hw, struct ieee80211_vif *vif, struct sk_buff *skb)$/;"	f	signature:(struct ieee80211_hw *hw, struct ieee80211_vif *vif, struct sk_buff *skb)
+ssv6xxx_ampdu2mpdu	smac/ampdu.h	/^void ssv6xxx_ampdu2mpdu(struct ieee80211_hw *hw, struct ieee80211_vif *vif, struct sk_buff *skb);$/;"	p	signature:(struct ieee80211_hw *hw, struct ieee80211_vif *vif, struct sk_buff *skb)
+ssv6xxx_ampdu_check_timeout	smac/ampdu.c	/^void ssv6xxx_ampdu_check_timeout (struct ieee80211_hw *hw)$/;"	f	signature:(struct ieee80211_hw *hw)
+ssv6xxx_ampdu_check_timeout	smac/ampdu.h	/^void ssv6xxx_ampdu_check_timeout (struct ieee80211_hw *hw);$/;"	p	signature:(struct ieee80211_hw *hw)
+ssv6xxx_ampdu_flush	smac/ampdu.c	/^u32 ssv6xxx_ampdu_flush (struct ieee80211_hw *hw)$/;"	f	signature:(struct ieee80211_hw *hw)
+ssv6xxx_ampdu_flush	smac/ampdu.h	/^u32 ssv6xxx_ampdu_flush(struct ieee80211_hw *hw);$/;"	p	signature:(struct ieee80211_hw *hw)
+ssv6xxx_ampdu_mib_reset	smac/ampdu.c	/^void ssv6xxx_ampdu_mib_reset (struct ieee80211_hw *hw)$/;"	f	signature:(struct ieee80211_hw *hw)
+ssv6xxx_ampdu_postprocess_BA	smac/ampdu.c	/^void ssv6xxx_ampdu_postprocess_BA (struct ieee80211_hw *hw)$/;"	f	signature:(struct ieee80211_hw *hw)
+ssv6xxx_ampdu_postprocess_BA	smac/ampdu.h	/^void ssv6xxx_ampdu_postprocess_BA (struct ieee80211_hw *hw);$/;"	p	signature:(struct ieee80211_hw *hw)
+ssv6xxx_ampdu_sent	smac/ampdu.c	/^void ssv6xxx_ampdu_sent(struct ieee80211_hw *hw, struct sk_buff *ampdu)$/;"	f	signature:(struct ieee80211_hw *hw, struct sk_buff *ampdu)
+ssv6xxx_ampdu_sent	smac/ampdu.h	/^void ssv6xxx_ampdu_sent (struct ieee80211_hw *hw, struct sk_buff *ampdu);$/;"	p	signature:(struct ieee80211_hw *hw, struct sk_buff *ampdu)
+ssv6xxx_attach_common_hal	smac/hal/hal.c	/^static void ssv6xxx_attach_common_hal (struct ssv_hal_ops *hal_ops)$/;"	f	file:	signature:(struct ssv_hal_ops *hal_ops)
+ssv6xxx_auto_bcn_ongoing	smac/ap.c	/^inline bool ssv6xxx_auto_bcn_ongoing(struct ssv_hw *sh)$/;"	f	signature:(struct ssv_hw *sh)
+ssv6xxx_auto_gen_nullpkt	ssvdevice/ssv_cmd.c	/^static int ssv6xxx_auto_gen_nullpkt(struct ssv_hw *sh, int hwq)$/;"	f	file:	signature:(struct ssv_hw *sh, int hwq)
+ssv6xxx_b_cca_control	smac/dev.h	/^struct ssv6xxx_b_cca_control {$/;"	s
+ssv6xxx_b_cca_control::adjust_cca_1	smac/dev.h	/^    u32 adjust_cca_1;$/;"	m	struct:ssv6xxx_b_cca_control	access:public
+ssv6xxx_b_cca_control::adjust_cca_control	smac/dev.h	/^    u32 adjust_cca_control;$/;"	m	struct:ssv6xxx_b_cca_control	access:public
+ssv6xxx_b_cca_control::down_level	smac/dev.h	/^    u32 down_level;$/;"	m	struct:ssv6xxx_b_cca_control	access:public
+ssv6xxx_b_cca_control::upper_level	smac/dev.h	/^    u32 upper_level;$/;"	m	struct:ssv6xxx_b_cca_control	access:public
+ssv6xxx_bcast_txq	smac/dev.h	/^struct ssv6xxx_bcast_txq {$/;"	s
+ssv6xxx_bcast_txq::cur_qsize	smac/dev.h	/^    int cur_qsize;$/;"	m	struct:ssv6xxx_bcast_txq	access:public
+ssv6xxx_bcast_txq::qhead	smac/dev.h	/^    struct sk_buff_head qhead;$/;"	m	struct:ssv6xxx_bcast_txq	typeref:struct:ssv6xxx_bcast_txq::sk_buff_head	access:public
+ssv6xxx_bcast_txq::txq_lock	smac/dev.h	/^    spinlock_t txq_lock;$/;"	m	struct:ssv6xxx_bcast_txq	access:public
+ssv6xxx_beacon_change	smac/ap.c	/^void ssv6xxx_beacon_change(struct ssv_softc *sc, struct ieee80211_hw *hw, struct ieee80211_vif *vif, bool aid0_bit_set)$/;"	f	signature:(struct ssv_softc *sc, struct ieee80211_hw *hw, struct ieee80211_vif *vif, bool aid0_bit_set)
+ssv6xxx_beacon_change	smac/ap.h	/^void ssv6xxx_beacon_change(struct ssv_softc *sc, struct ieee80211_hw *hw, struct ieee80211_vif *vif, bool aid0_bit_set);$/;"	p	signature:(struct ssv_softc *sc, struct ieee80211_hw *hw, struct ieee80211_vif *vif, bool aid0_bit_set)
+ssv6xxx_beacon_enable	smac/ap.c	/^bool ssv6xxx_beacon_enable(struct ssv_softc *sc, bool bEnable)$/;"	f	signature:(struct ssv_softc *sc, bool bEnable)
+ssv6xxx_beacon_enable	smac/ap.h	/^bool ssv6xxx_beacon_enable(struct ssv_softc *sc, bool bEnable);$/;"	p	signature:(struct ssv_softc *sc, bool bEnable)
+ssv6xxx_beacon_fill_content	smac/ap.c	/^int ssv6xxx_beacon_fill_content(struct ssv_softc *sc, u32 regaddr, u8 *beacon, int size)$/;"	f	signature:(struct ssv_softc *sc, u32 regaddr, u8 *beacon, int size)
+ssv6xxx_beacon_fill_tx_desc	smac/ap.c	/^void ssv6xxx_beacon_fill_tx_desc(struct ssv_softc *sc, struct sk_buff* beacon_skb)$/;"	f	signature:(struct ssv_softc *sc, struct sk_buff* beacon_skb)
+ssv6xxx_beacon_fill_tx_desc	smac/ap.h	/^void ssv6xxx_beacon_fill_tx_desc(struct ssv_softc *sc, struct sk_buff* beacon_skb);$/;"	p	signature:(struct ssv_softc *sc, struct sk_buff* beacon_skb)
+ssv6xxx_beacon_get_valid_reg	smac/ap.c	/^inline enum ssv6xxx_beacon_type ssv6xxx_beacon_get_valid_reg(struct ssv_hw *sh)$/;"	f	signature:(struct ssv_hw *sh)
+ssv6xxx_beacon_info	smac/dev.h	/^struct ssv6xxx_beacon_info {$/;"	s
+ssv6xxx_beacon_info::len	smac/dev.h	/^ u16 len;$/;"	m	struct:ssv6xxx_beacon_info	access:public
+ssv6xxx_beacon_info::pubf_addr	smac/dev.h	/^ u32 pubf_addr;$/;"	m	struct:ssv6xxx_beacon_info	access:public
+ssv6xxx_beacon_info::tim_cnt	smac/dev.h	/^ u8 tim_cnt;$/;"	m	struct:ssv6xxx_beacon_info	access:public
+ssv6xxx_beacon_info::tim_offset	smac/dev.h	/^ u8 tim_offset;$/;"	m	struct:ssv6xxx_beacon_info	access:public
+ssv6xxx_beacon_miss_work	smac/dev.c	/^void ssv6xxx_beacon_miss_work(struct work_struct *work)$/;"	f	signature:(struct work_struct *work)
+ssv6xxx_beacon_miss_work	smac/dev.h	/^void ssv6xxx_beacon_miss_work(struct work_struct *work);$/;"	p	signature:(struct work_struct *work)
+ssv6xxx_beacon_reg_lock	smac/ap.c	/^void ssv6xxx_beacon_reg_lock(struct ssv_hw *sh, bool block)$/;"	f	signature:(struct ssv_hw *sh, bool block)
+ssv6xxx_beacon_release	smac/ap.c	/^void ssv6xxx_beacon_release(struct ssv_softc *sc)$/;"	f	signature:(struct ssv_softc *sc)
+ssv6xxx_beacon_release	smac/ap.h	/^void ssv6xxx_beacon_release(struct ssv_softc *sc);$/;"	p	signature:(struct ssv_softc *sc)
+ssv6xxx_beacon_set	smac/ap.c	/^bool ssv6xxx_beacon_set(struct ssv_softc *sc, struct sk_buff *beacon_skb, int dtim_offset)$/;"	f	signature:(struct ssv_softc *sc, struct sk_buff *beacon_skb, int dtim_offset)
+ssv6xxx_beacon_set_info	smac/ap.c	/^void ssv6xxx_beacon_set_info(struct ssv_hw *sh, u8 beacon_interval, u8 dtim_cnt)$/;"	f	signature:(struct ssv_hw *sh, u8 beacon_interval, u8 dtim_cnt)
+ssv6xxx_beacon_set_info	smac/ap.h	/^void ssv6xxx_beacon_set_info(struct ssv_hw *sh, u8 beacon_interval, u8 dtim_cnt);$/;"	p	signature:(struct ssv_hw *sh, u8 beacon_interval, u8 dtim_cnt)
+ssv6xxx_beacon_type	include/hal.h	/^enum ssv6xxx_beacon_type{$/;"	g
+ssv6xxx_beacon_type	smac/ap.c	/^enum ssv6xxx_beacon_type{$/;"	g	file:
+ssv6xxx_calib_table	smac/dev.h	/^struct ssv6xxx_calib_table {$/;"	s
+ssv6xxx_calib_table::channel_id	smac/dev.h	/^    u16 channel_id;$/;"	m	struct:ssv6xxx_calib_table	access:public
+ssv6xxx_calib_table::rf_ctrl_F	smac/dev.h	/^    u32 rf_ctrl_F;$/;"	m	struct:ssv6xxx_calib_table	access:public
+ssv6xxx_calib_table::rf_ctrl_N	smac/dev.h	/^    u32 rf_ctrl_N;$/;"	m	struct:ssv6xxx_calib_table	access:public
+ssv6xxx_calib_table::rf_precision_default	smac/dev.h	/^    u16 rf_precision_default;$/;"	m	struct:ssv6xxx_calib_table	access:public
+ssv6xxx_cca_control	smac/dev.h	/^struct ssv6xxx_cca_control {$/;"	s
+ssv6xxx_cca_control::adjust_cck_cca_control	smac/dev.h	/^    u32 adjust_cck_cca_control;$/;"	m	struct:ssv6xxx_cca_control	access:public
+ssv6xxx_cca_control::adjust_ofdm_cca_control	smac/dev.h	/^    u32 adjust_ofdm_cca_control;$/;"	m	struct:ssv6xxx_cca_control	access:public
+ssv6xxx_cca_control::down_level	smac/dev.h	/^    u32 down_level;$/;"	m	struct:ssv6xxx_cca_control	access:public
+ssv6xxx_cca_control::upper_level	smac/dev.h	/^    u32 upper_level;$/;"	m	struct:ssv6xxx_cca_control	access:public
+ssv6xxx_cci_clean_process	smac/dev.c	/^void ssv6xxx_cci_clean_process(struct work_struct *work)$/;"	f	signature:(struct work_struct *work)
+ssv6xxx_cci_clean_process	smac/dev.h	/^void ssv6xxx_cci_clean_process(struct work_struct *work);$/;"	p	signature:(struct work_struct *work)
+ssv6xxx_cci_set_process	smac/dev.c	/^void ssv6xxx_cci_set_process(struct work_struct *work)$/;"	f	signature:(struct work_struct *work)
+ssv6xxx_cci_set_process	smac/dev.h	/^void ssv6xxx_cci_set_process(struct work_struct *work);$/;"	p	signature:(struct work_struct *work)
+ssv6xxx_cfg	include/ssv_cfg.h	/^struct ssv6xxx_cfg {$/;"	s
+ssv6xxx_cfg::aggr_size_sel_pr	include/ssv_cfg.h	/^    u32 aggr_size_sel_pr;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::auto_rate_enable	include/ssv_cfg.h	/^    u32 auto_rate_enable;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::auto_sgi	include/ssv_cfg.h	/^    u32 auto_sgi;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::be_txq_size	include/ssv_cfg.h	/^    u32 be_txq_size;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::beacon_rssi_minimal	include/ssv_cfg.h	/^    u32 beacon_rssi_minimal;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::bk_txq_size	include/ssv_cfg.h	/^    u32 bk_txq_size;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::cci	include/ssv_cfg.h	/^    u32 cci;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::chip_identity	include/ssv_cfg.h	/^    u32 chip_identity;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::clk_src_80m	include/ssv_cfg.h	/^    bool clk_src_80m;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::configuration	include/ssv_cfg.h	/^    u32 configuration[EXTERNEL_CONFIG_SUPPORT+1][2];$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::crystal_frequency_offset	include/ssv_cfg.h	/^    u32 crystal_frequency_offset;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::crystal_type	include/ssv_cfg.h	/^    u32 crystal_type;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::def_chan	include/ssv_cfg.h	/^    u32 def_chan;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::directly_ack_high_threshold	include/ssv_cfg.h	/^    u32 directly_ack_high_threshold;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::directly_ack_low_threshold	include/ssv_cfg.h	/^    u32 directly_ack_low_threshold;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::disable_dpd	include/ssv_cfg.h	/^    u32 disable_dpd;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::external_firmware_name	include/ssv_cfg.h	/^    u8 external_firmware_name[128];$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::firmware_path	include/ssv_cfg.h	/^    u8 firmware_path[128];$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::flash_bin_path	include/ssv_cfg.h	/^    u8 flash_bin_path[128];$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::force_chip_identity	include/ssv_cfg.h	/^    u32 force_chip_identity;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::force_xtal_fo	include/ssv_cfg.h	/^    bool force_xtal_fo;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::greentx	include/ssv_cfg.h	/^    u32 greentx;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::gt_max_attenuation	include/ssv_cfg.h	/^    u32 gt_max_attenuation;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::gt_stepsize	include/ssv_cfg.h	/^    u32 gt_stepsize;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::hw_caps	include/ssv_cfg.h	/^    u32 hw_caps;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::hw_rx_agg_cnt	include/ssv_cfg.h	/^    u32 hw_rx_agg_cnt;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::hw_rx_agg_method_3	include/ssv_cfg.h	/^    bool hw_rx_agg_method_3;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::hw_rx_agg_timer_reload	include/ssv_cfg.h	/^    u32 hw_rx_agg_timer_reload;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::ignore_efuse_mac	include/ssv_cfg.h	/^    u32 ignore_efuse_mac;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::ignore_firmware_version	include/ssv_cfg.h	/^    u32 ignore_firmware_version;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::lpbk_mode	include/ssv_cfg.h	/^    u32 lpbk_mode;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::lpbk_pkt_cnt	include/ssv_cfg.h	/^    u32 lpbk_pkt_cnt;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::lpbk_sec	include/ssv_cfg.h	/^    u32 lpbk_sec;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::lpbk_type	include/ssv_cfg.h	/^    u32 lpbk_type;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::mac_address_mode	include/ssv_cfg.h	/^    u32 mac_address_mode;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::mac_address_path	include/ssv_cfg.h	/^    u8 mac_address_path[128];$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::mac_output_path	include/ssv_cfg.h	/^    u8 mac_output_path[128];$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::maddr	include/ssv_cfg.h	/^    u8 maddr[2][6];$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::manage_txq_size	include/ssv_cfg.h	/^    u32 manage_txq_size;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::max_rx_aggr_size	include/ssv_cfg.h	/^ u32 max_rx_aggr_size;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::mic_err_notify	include/ssv_cfg.h	/^    u32 mic_err_notify;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::n_maddr	include/ssv_cfg.h	/^    u32 n_maddr;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::online_reset	include/ssv_cfg.h	/^    u32 online_reset;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::r_calbration_result	include/ssv_cfg.h	/^    u32 r_calbration_result;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::rate_table_1	include/ssv_cfg.h	/^    u32 rate_table_1;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::rate_table_2	include/ssv_cfg.h	/^    u32 rate_table_2;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::rc_ht40	include/ssv_cfg.h	/^    u32 rc_ht40;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::rc_ht_support_cck	include/ssv_cfg.h	/^    u32 rc_ht_support_cck;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::rc_log	include/ssv_cfg.h	/^ u32 rc_log;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::rc_long_short	include/ssv_cfg.h	/^    u32 rc_long_short;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::rc_mf	include/ssv_cfg.h	/^    u32 rc_mf;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::rc_phy_mode	include/ssv_cfg.h	/^    u32 rc_phy_mode;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::rc_rate_idx_set	include/ssv_cfg.h	/^    u32 rc_rate_idx_set;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::rc_retry_set	include/ssv_cfg.h	/^    u32 rc_retry_set;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::rc_setting	include/ssv_cfg.h	/^    struct rc_setting rc_setting;$/;"	m	struct:ssv6xxx_cfg	typeref:struct:ssv6xxx_cfg::rc_setting	access:public
+ssv6xxx_cfg::rts_thres_len	include/ssv_cfg.h	/^    u32 rts_thres_len;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::rx_burstread	include/ssv_cfg.h	/^    bool rx_burstread;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::rx_threshold	include/ssv_cfg.h	/^    u32 rx_threshold;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::sar_result	include/ssv_cfg.h	/^    u32 sar_result;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::tx_id_threshold	include/ssv_cfg.h	/^ u32 tx_id_threshold;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::tx_page_threshold	include/ssv_cfg.h	/^ u32 tx_page_threshold;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::tx_power_index_1	include/ssv_cfg.h	/^    u32 tx_power_index_1;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::tx_power_index_2	include/ssv_cfg.h	/^    u32 tx_power_index_2;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::tx_stuck_detect	include/ssv_cfg.h	/^    bool tx_stuck_detect;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::txrxboost_high_threshold	include/ssv_cfg.h	/^    u32 txrxboost_high_threshold;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::txrxboost_low_threshold	include/ssv_cfg.h	/^    u32 txrxboost_low_threshold;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::txrxboost_prio	include/ssv_cfg.h	/^    u32 txrxboost_prio;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::usb_hw_resource	include/ssv_cfg.h	/^    u32 usb_hw_resource;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::use_sw_cipher	include/ssv_cfg.h	/^    u32 use_sw_cipher;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::use_wpa2_only	include/ssv_cfg.h	/^    u32 use_wpa2_only;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::vi_txq_size	include/ssv_cfg.h	/^    u32 vi_txq_size;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::vo_txq_size	include/ssv_cfg.h	/^    u32 vo_txq_size;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::volt_regulator	include/ssv_cfg.h	/^    u32 volt_regulator;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::wifi_tx_gain_level_b	include/ssv_cfg.h	/^    u32 wifi_tx_gain_level_b;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg::wifi_tx_gain_level_gn	include/ssv_cfg.h	/^    u32 wifi_tx_gain_level_gn;$/;"	m	struct:ssv6xxx_cfg	access:public
+ssv6xxx_cfg_cmd_table	ssvdevice/ssv_cmd.h	/^struct ssv6xxx_cfg_cmd_table {$/;"	s
+ssv6xxx_cfg_cmd_table::arg	ssvdevice/ssv_cmd.h	/^    u32 arg;$/;"	m	struct:ssv6xxx_cfg_cmd_table	access:public
+ssv6xxx_cfg_cmd_table::cfg_cmd	ssvdevice/ssv_cmd.h	/^    u8 *cfg_cmd;$/;"	m	struct:ssv6xxx_cfg_cmd_table	access:public
+ssv6xxx_cfg_cmd_table::def_val	ssvdevice/ssv_cmd.h	/^    u8 *def_val;$/;"	m	struct:ssv6xxx_cfg_cmd_table	access:public
+ssv6xxx_cfg_cmd_table::translate_func	ssvdevice/ssv_cmd.h	/^    int (*translate_func)(u8 *, void *, u32);$/;"	m	struct:ssv6xxx_cfg_cmd_table	access:public
+ssv6xxx_cfg_cmd_table::var	ssvdevice/ssv_cmd.h	/^    void *var;$/;"	m	struct:ssv6xxx_cfg_cmd_table	access:public
+ssv6xxx_cfg_volt	include/ssv6xxx_common.h	/^} ssv6xxx_cfg_volt;$/;"	t	typeref:enum:__anon48
+ssv6xxx_cfg_volt_value	include/ssv6xxx_common.h	/^} ssv6xxx_cfg_volt_value;$/;"	t	typeref:enum:__anon49
+ssv6xxx_ch_cfg	include/ssv6xxx_common.h	/^struct ssv6xxx_ch_cfg {$/;"	s
+ssv6xxx_ch_cfg::ch13_14_value	include/ssv6xxx_common.h	/^ u32 ch13_14_value;$/;"	m	struct:ssv6xxx_ch_cfg	access:public
+ssv6xxx_ch_cfg::ch1_12_value	include/ssv6xxx_common.h	/^ u32 ch1_12_value;$/;"	m	struct:ssv6xxx_ch_cfg	access:public
+ssv6xxx_ch_cfg::reg_addr	include/ssv6xxx_common.h	/^ u32 reg_addr;$/;"	m	struct:ssv6xxx_ch_cfg	access:public
+ssv6xxx_check_mac2	smac/init.c	/^static void ssv6xxx_check_mac2(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6xxx_chg_ipd_phyinfo	smac/hal/hal.c	/^static void ssv6xxx_chg_ipd_phyinfo(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6xxx_chg_pad_setting	smac/hal/hal.c	/^static int ssv6xxx_chg_pad_setting(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6xxx_chk_dual_vif_chg_rx_flow	smac/dev.c	/^static void ssv6xxx_chk_dual_vif_chg_rx_flow(struct ssv_softc *sc,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv)
+ssv6xxx_chk_if_support_hw_bssid	smac/dev.c	/^static bool ssv6xxx_chk_if_support_hw_bssid(struct ssv_softc *sc,$/;"	f	file:	signature:(struct ssv_softc *sc, int vif_idx)
+ssv6xxx_chk_lpbk_rx_rate_desc	smac/hal/hal.c	/^static int ssv6xxx_chk_lpbk_rx_rate_desc(struct ssv_hw *sh, struct sk_buff *skb)$/;"	f	file:	signature:(struct ssv_hw *sh, struct sk_buff *skb)
+ssv6xxx_chk_rx_rate_desc	smac/dev.c	/^int ssv6xxx_chk_rx_rate_desc(struct ssv_hw *sh, struct sk_buff *skb);$/;"	p	file:	signature:(struct ssv_hw *sh, struct sk_buff *skb)
+ssv6xxx_chk_rx_rate_desc	smac/dev.h	/^int ssv6xxx_chk_rx_rate_desc(struct ssv_hw *sh, struct sk_buff *skb);$/;"	p	signature:(struct ssv_hw *sh, struct sk_buff *skb)
+ssv6xxx_chk_usb_speed	hwif/usb/usb.c	/^static int ssv6xxx_chk_usb_speed(struct ssv6xxx_usb_glue *glue)$/;"	f	file:	signature:(struct ssv6xxx_usb_glue *glue)
+ssv6xxx_cipher_suites	smac/init.c	/^static const u32 ssv6xxx_cipher_suites[] = {$/;"	v	file:
+ssv6xxx_cmd_cali	smac/hal/hal.c	/^static void ssv6xxx_cmd_cali(struct ssv_hw *sh, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_hw *sh, int argc, char *argv[])
+ssv6xxx_cmd_cci	smac/hal/hal.c	/^static void ssv6xxx_cmd_cci(struct ssv_hw *sh, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_hw *sh, int argc, char *argv[])
+ssv6xxx_cmd_efuse	smac/hal/hal.c	/^static void ssv6xxx_cmd_efuse(struct ssv_hw *sh, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_hw *sh, int argc, char *argv[])
+ssv6xxx_cmd_endpoint	hwif/usb/usb.h	/^struct ssv6xxx_cmd_endpoint {$/;"	s
+ssv6xxx_cmd_endpoint::address	hwif/usb/usb.h	/^ u8 address;$/;"	m	struct:ssv6xxx_cmd_endpoint	access:public
+ssv6xxx_cmd_endpoint::buff	hwif/usb/usb.h	/^ void *buff;$/;"	m	struct:ssv6xxx_cmd_endpoint	access:public
+ssv6xxx_cmd_endpoint::packet_size	hwif/usb/usb.h	/^ u16 packet_size;$/;"	m	struct:ssv6xxx_cmd_endpoint	access:public
+ssv6xxx_cmd_file_open	ssvdevice/ssvdevice.c	/^static int ssv6xxx_cmd_file_open(struct inode *inode, struct file *filp)$/;"	f	file:	signature:(struct inode *inode, struct file *filp)
+ssv6xxx_cmd_file_read	ssvdevice/ssvdevice.c	/^static ssize_t ssv6xxx_cmd_file_read(struct file *filp, char __user *buffer,$/;"	f	file:	signature:(struct file *filp, char __user *buffer, size_t count, loff_t *ppos)
+ssv6xxx_cmd_file_write	ssvdevice/ssvdevice.c	/^static ssize_t ssv6xxx_cmd_file_write(struct file *filp, const char __user *buffer,$/;"	f	file:	signature:(struct file *filp, const char __user *buffer, size_t count, loff_t *ppos)
+ssv6xxx_cmd_fops	ssvdevice/ssvdevice.c	/^static struct file_operations ssv6xxx_cmd_fops = {$/;"	v	typeref:struct:file_operations	file:
+ssv6xxx_cmd_hdr	hwif/usb/usb.h	/^struct ssv6xxx_cmd_hdr {$/;"	s
+ssv6xxx_cmd_hdr::cmd	hwif/usb/usb.h	/^ u8 cmd;$/;"	m	struct:ssv6xxx_cmd_hdr	access:public
+ssv6xxx_cmd_hdr::payload	hwif/usb/usb.h	/^ union ssv6xxx_payload payload;$/;"	m	struct:ssv6xxx_cmd_hdr	typeref:union:ssv6xxx_cmd_hdr::ssv6xxx_payload	access:public
+ssv6xxx_cmd_hdr::plen	hwif/usb/usb.h	/^ u8 plen;$/;"	m	struct:ssv6xxx_cmd_hdr	access:public
+ssv6xxx_cmd_hdr::seq	hwif/usb/usb.h	/^ u16 seq;$/;"	m	struct:ssv6xxx_cmd_hdr	access:public
+ssv6xxx_cmd_hwinfo	smac/hal/hal.c	/^static void ssv6xxx_cmd_hwinfo(struct ssv_hw *sh, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_hw *sh, int argc, char *argv[])
+ssv6xxx_cmd_hwq_limit	smac/hal/hal.c	/^static void ssv6xxx_cmd_hwq_limit(struct ssv_hw *sh, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_hw *sh, int argc, char *argv[])
+ssv6xxx_cmd_loopback	smac/hal/hal.c	/^static void ssv6xxx_cmd_loopback(struct ssv_hw *sh, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_hw *sh, int argc, char *argv[])
+ssv6xxx_cmd_loopback_setup_env	smac/hal/hal.c	/^static void ssv6xxx_cmd_loopback_setup_env(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6xxx_cmd_loopback_start	smac/hal/hal.c	/^static void ssv6xxx_cmd_loopback_start(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6xxx_cmd_mib	ssvdevice/ssv_cmd.c	/^static void ssv6xxx_cmd_mib(struct ssv_softc *sc, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_softc *sc, int argc, char *argv[])
+ssv6xxx_cmd_power_saving	ssvdevice/ssv_cmd.c	/^static void ssv6xxx_cmd_power_saving(struct ssv_softc *sc, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_softc *sc, int argc, char *argv[])
+ssv6xxx_cmd_rc	smac/hal/hal.c	/^static void ssv6xxx_cmd_rc(struct ssv_hw *sh, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_hw *sh, int argc, char *argv[])
+ssv6xxx_cmd_rf	smac/hal/hal.c	/^static void ssv6xxx_cmd_rf(struct ssv_hw *sh, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_hw *sh, int argc, char *argv[])
+ssv6xxx_cmd_spectrum	smac/hal/hal.c	/^static void ssv6xxx_cmd_spectrum(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6xxx_cmd_txgen	smac/hal/hal.c	/^static void ssv6xxx_cmd_txgen(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6xxx_config_vif_res	smac/dev.c	/^struct ssv_vif_priv_data * ssv6xxx_config_vif_res(struct ssv_softc *sc,$/;"	f	signature:(struct ssv_softc *sc, struct ieee80211_vif *vif)
+ssv6xxx_cpu_callback	smac/init.c	/^int ssv6xxx_cpu_callback(struct notifier_block *nfb,$/;"	f	signature:(struct notifier_block *nfb, unsigned long action, void *hcpu)
+ssv6xxx_dbg_file_open	ssvdevice/ssvdevice.c	/^static int ssv6xxx_dbg_file_open(struct inode *inode, struct file *filp)$/;"	f	file:	signature:(struct inode *inode, struct file *filp)
+ssv6xxx_dbg_fops	ssvdevice/ssvdevice.c	/^static struct file_operations ssv6xxx_dbg_fops = {$/;"	v	typeref:struct:file_operations	file:
+ssv6xxx_dbg_seq_fops	ssvdevice/ssvdevice.c	/^static struct seq_operations ssv6xxx_dbg_seq_fops = {$/;"	v	typeref:struct:seq_operations	file:
+ssv6xxx_dbg_seq_next	ssvdevice/ssvdevice.c	/^static void *ssv6xxx_dbg_seq_next(struct seq_file *s, void *v, loff_t *pos)$/;"	f	file:	signature:(struct seq_file *s, void *v, loff_t *pos)
+ssv6xxx_dbg_seq_show	ssvdevice/ssvdevice.c	/^static int ssv6xxx_dbg_seq_show(struct seq_file *s, void *v)$/;"	f	file:	signature:(struct seq_file *s, void *v)
+ssv6xxx_dbg_seq_start	ssvdevice/ssvdevice.c	/^static void *ssv6xxx_dbg_seq_start(struct seq_file *s, loff_t *pos)$/;"	f	file:	signature:(struct seq_file *s, loff_t *pos)
+ssv6xxx_dbg_seq_stop	ssvdevice/ssvdevice.c	/^static void ssv6xxx_dbg_seq_stop(struct seq_file *s, void *v)$/;"	f	file:	signature:(struct seq_file *s, void *v)
+ssv6xxx_debugfs_add_interface	smac/ssv6xxx_debugfs.c	/^int ssv6xxx_debugfs_add_interface(struct ssv_softc *sc, struct ieee80211_vif *vif)$/;"	f	signature:(struct ssv_softc *sc, struct ieee80211_vif *vif)
+ssv6xxx_debugfs_add_interface	smac/ssv6xxx_debugfs.h	/^int ssv6xxx_debugfs_add_interface(struct ssv_softc *sc, struct ieee80211_vif *vif);$/;"	p	signature:(struct ssv_softc *sc, struct ieee80211_vif *vif)
+ssv6xxx_debugfs_add_sta	smac/ssv6xxx_debugfs.c	/^int ssv6xxx_debugfs_add_sta(struct ssv_softc *sc, struct ssv_sta_info *sta)$/;"	f	signature:(struct ssv_softc *sc, struct ssv_sta_info *sta)
+ssv6xxx_debugfs_add_sta	smac/ssv6xxx_debugfs.h	/^int ssv6xxx_debugfs_add_sta(struct ssv_softc *sc, struct ssv_sta_info *sta);$/;"	p	signature:(struct ssv_softc *sc, struct ssv_sta_info *sta)
+ssv6xxx_debugfs_remove_interface	smac/ssv6xxx_debugfs.c	/^int ssv6xxx_debugfs_remove_interface(struct ssv_softc *sc, struct ieee80211_vif *vif)$/;"	f	signature:(struct ssv_softc *sc, struct ieee80211_vif *vif)
+ssv6xxx_debugfs_remove_interface	smac/ssv6xxx_debugfs.h	/^int ssv6xxx_debugfs_remove_interface(struct ssv_softc *sc, struct ieee80211_vif *vif);$/;"	p	signature:(struct ssv_softc *sc, struct ieee80211_vif *vif)
+ssv6xxx_debugfs_remove_sta	smac/ssv6xxx_debugfs.c	/^int ssv6xxx_debugfs_remove_sta(struct ssv_softc *sc, struct ssv_sta_info *sta)$/;"	f	signature:(struct ssv_softc *sc, struct ssv_sta_info *sta)
+ssv6xxx_debugfs_remove_sta	smac/ssv6xxx_debugfs.h	/^int ssv6xxx_debugfs_remove_sta(struct ssv_softc *sc, struct ssv_sta_info *sta);$/;"	p	signature:(struct ssv_softc *sc, struct ssv_sta_info *sta)
+ssv6xxx_deinit_debugfs	smac/ssv6xxx_debugfs.c	/^void ssv6xxx_deinit_debugfs (struct ssv_softc *sc)$/;"	f	signature:(struct ssv_softc *sc)
+ssv6xxx_deinit_debugfs	smac/ssv6xxx_debugfs.h	/^void ssv6xxx_deinit_debugfs (struct ssv_softc *sc);$/;"	p	signature:(struct ssv_softc *sc)
+ssv6xxx_deinit_device	smac/init.c	/^static void ssv6xxx_deinit_device(struct ssv_softc *sc)$/;"	f	file:	signature:(struct ssv_softc *sc)
+ssv6xxx_deinit_hw	smac/init.c	/^void inline ssv6xxx_deinit_hw(struct ssv_softc *sc)$/;"	f	signature:(struct ssv_softc *sc)
+ssv6xxx_deinit_hwsh	smac/init.c	/^static void ssv6xxx_deinit_hwsh(struct ssv_softc *sc)$/;"	f	file:	signature:(struct ssv_softc *sc)
+ssv6xxx_deinit_mac	smac/init.c	/^void ssv6xxx_deinit_mac(struct ssv_softc *sc)$/;"	f	signature:(struct ssv_softc *sc)
+ssv6xxx_deinit_mac	smac/init.h	/^void ssv6xxx_deinit_mac(struct ssv_softc *sc);$/;"	p	signature:(struct ssv_softc *sc)
+ssv6xxx_deinit_softc	smac/init.c	/^static int ssv6xxx_deinit_softc(struct ssv_softc *sc)$/;"	f	file:	signature:(struct ssv_softc *sc)
+ssv6xxx_del_hw_wsid	smac/dev.c	/^static void ssv6xxx_del_hw_wsid(struct ssv_softc *sc, int hw_wsid)$/;"	f	file:	signature:(struct ssv_softc *sc, int hw_wsid)
+ssv6xxx_dequeue_list_node	include/ssv_data_struct.h	/^static inline struct ssv6xxx_list_node *ssv6xxx_dequeue_list_node(struct ssv6xxx_queue *ssv_queue) {$/;"	f	signature:(struct ssv6xxx_queue *ssv_queue)
+ssv6xxx_detach_usb_hci	smac/hal/hal.c	/^static void ssv6xxx_detach_usb_hci(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6xxx_dev_probe	smac/init.c	/^EXPORT_SYMBOL(ssv6xxx_dev_probe);$/;"	v
+ssv6xxx_dev_probe	smac/init.c	/^int ssv6xxx_dev_probe(struct platform_device *pdev)$/;"	f	signature:(struct platform_device *pdev)
+ssv6xxx_dev_remove	smac/init.c	/^EXPORT_SYMBOL(ssv6xxx_dev_remove);$/;"	v
+ssv6xxx_dev_remove	smac/init.c	/^int ssv6xxx_dev_remove(struct platform_device *pdev)$/;"	f	signature:(struct platform_device *pdev)
+ssv6xxx_dev_table	ssvdevice/ssv_cmd.c	/^struct ssv6xxx_dev_table {$/;"	s	file:
+ssv6xxx_dev_table::address	ssvdevice/ssv_cmd.c	/^    u32 address;$/;"	m	struct:ssv6xxx_dev_table	file:	access:public
+ssv6xxx_dev_table::val	ssvdevice/ssv_cmd.c	/^    u32 val;$/;"	m	struct:ssv6xxx_dev_table	file:	access:public
+ssv6xxx_disable_fw_wsid	smac/dev.c	/^static void ssv6xxx_disable_fw_wsid(struct ssv_softc *sc, int key_idx,$/;"	f	file:	signature:(struct ssv_softc *sc, int key_idx, struct ssv_sta_priv_data *sta_priv, struct ssv_vif_priv_data *vif_priv)
+ssv6xxx_disable_ps	smac/dev.c	/^void ssv6xxx_disable_ps(struct ssv_softc *sc)$/;"	f	signature:(struct ssv_softc *sc)
+ssv6xxx_disable_ps	smac/dev.h	/^void ssv6xxx_disable_ps(struct ssv_softc *sc);$/;"	p	signature:(struct ssv_softc *sc)
+ssv6xxx_disable_usb_acc	smac/dev.c	/^void ssv6xxx_disable_usb_acc(void *param, u8 epnum)$/;"	f	signature:(void *param, u8 epnum)
+ssv6xxx_disable_usb_acc	smac/dev.h	/^void ssv6xxx_disable_usb_acc(void *param, u8 epnum);$/;"	p	signature:(void *param, u8 epnum)
+ssv6xxx_do_iq_cal	smac/hal/hal.c	/^static int ssv6xxx_do_iq_cal(struct ssv_hw *sh, struct ssv6xxx_iqk_cfg *p_cfg)$/;"	f	file:	signature:(struct ssv_hw *sh, struct ssv6xxx_iqk_cfg *p_cfg)
+ssv6xxx_do_iq_calib	smac/init.c	/^int ssv6xxx_do_iq_calib(struct ssv_hw *sh, struct ssv6xxx_iqk_cfg *p_cfg)$/;"	f	signature:(struct ssv_hw *sh, struct ssv6xxx_iqk_cfg *p_cfg)
+ssv6xxx_do_iq_calib	smac/init.h	/^        int ssv6xxx_do_iq_calib(struct ssv_hw *sh, struct ssv6xxx_iqk_cfg *p_cfg);$/;"	p	signature:(struct ssv_hw *sh, struct ssv6xxx_iqk_cfg *p_cfg)
+ssv6xxx_do_sdio_init_seq_5537	hwif/sdio/sdio.c	/^static int ssv6xxx_do_sdio_init_seq_5537(struct sdio_func *func) {$/;"	f	file:	signature:(struct sdio_func *func)
+ssv6xxx_do_sdio_reset_reinit	hwif/sdio/sdio.c	/^static void ssv6xxx_do_sdio_reset_reinit(struct ssv6xxx_platform_data *pwlan_data,$/;"	f	file:	signature:(struct ssv6xxx_platform_data *pwlan_data, struct sdio_func *func, struct ssv6xxx_sdio_glue *glue)
+ssv6xxx_do_sdio_reset_reinit	hwif/sdio/sdio.c	/^static void ssv6xxx_do_sdio_reset_reinit(struct ssv6xxx_platform_data *pwlan_data,$/;"	p	file:	signature:(struct ssv6xxx_platform_data *pwlan_data, struct sdio_func *func, struct ssv6xxx_sdio_glue *glue)
+ssv6xxx_do_sdio_wakeup	hwif/sdio/sdio.c	/^static void ssv6xxx_do_sdio_wakeup(struct sdio_func *func)$/;"	f	file:	signature:(struct sdio_func *func)
+ssv6xxx_do_temperature_compensation	smac/dev.c	/^void ssv6xxx_do_temperature_compensation(struct ssv_hw *sh);$/;"	p	file:	signature:(struct ssv_hw *sh)
+ssv6xxx_do_temperature_compensation	smac/dev.h	/^void ssv6xxx_do_temperature_compensation(struct ssv_hw *sh);$/;"	p	signature:(struct ssv_hw *sh)
+ssv6xxx_do_temperature_compensation	smac/hal/hal.c	/^static void ssv6xxx_do_temperature_compensation(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6xxx_dpd_enable	smac/hal/hal.c	/^static void ssv6xxx_dpd_enable(struct ssv_hw *sh, bool val)$/;"	f	file:	signature:(struct ssv_hw *sh, bool val)
+ssv6xxx_driver	smac/init.c	/^static struct platform_driver ssv6xxx_driver =$/;"	v	typeref:struct:platform_driver	file:
+ssv6xxx_driver_attach	smac/init.c	/^struct ssv_softc *ssv6xxx_driver_attach(char *driver_name)$/;"	f	signature:(char *driver_name)
+ssv6xxx_driver_attach	smac/init.h	/^struct ssv_softc *ssv6xxx_driver_attach(char *driver_name);$/;"	p	signature:(char *driver_name)
+ssv6xxx_dump_cfg	ssvdevice/ssv_cmd.c	/^static bool ssv6xxx_dump_cfg(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6xxx_dump_decision	ssvdevice/ssv_cmd.c	/^static bool ssv6xxx_dump_decision(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6xxx_dump_mib_rx	ssvdevice/ssv_cmd.c	/^static void ssv6xxx_dump_mib_rx(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6xxx_dump_mib_rx_phy	ssvdevice/ssv_cmd.c	/^static void ssv6xxx_dump_mib_rx_phy(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6xxx_dump_sta_info	ssvdevice/ssv_cmd.c	/^void ssv6xxx_dump_sta_info (struct ssv_softc *sc)$/;"	f	signature:(struct ssv_softc *sc)
+ssv6xxx_dump_wsid	ssvdevice/ssv_cmd.c	/^static bool ssv6xxx_dump_wsid(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6xxx_early_suspend	smac/dev.h	/^void ssv6xxx_early_suspend(struct early_suspend *h);$/;"	p	signature:(struct early_suspend *h)
+ssv6xxx_early_suspend	smac/ssv_pm.c	/^void ssv6xxx_early_suspend(struct early_suspend *h)$/;"	f	signature:(struct early_suspend *h)
+ssv6xxx_early_suspend	smac/ssv_pm.h	/^void ssv6xxx_early_suspend(struct early_suspend *h);$/;"	p	signature:(struct early_suspend *h)
+ssv6xxx_early_suspend	smac/ssv_pm.h	/^void ssv6xxx_early_suspend(void);$/;"	p	signature:(void)
+ssv6xxx_edca_enable	smac/dev.c	/^void ssv6xxx_edca_enable(struct ssv_hw *sh, bool val)$/;"	f	signature:(struct ssv_hw *sh, bool val)
+ssv6xxx_edca_enable	smac/dev.h	/^void ssv6xxx_edca_enable(struct ssv_hw *sh, bool val);$/;"	p	signature:(struct ssv_hw *sh, bool val)
+ssv6xxx_edca_stat	smac/dev.c	/^void ssv6xxx_edca_stat(struct ssv_hw *sh)$/;"	f	signature:(struct ssv_hw *sh)
+ssv6xxx_edca_stat	smac/dev.h	/^void ssv6xxx_edca_stat(struct ssv_hw *sh);$/;"	p	signature:(struct ssv_hw *sh)
+ssv6xxx_enable_fw_wsid	smac/dev.c	/^static void ssv6xxx_enable_fw_wsid(struct ssv_softc *sc, struct ieee80211_sta *sta,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ieee80211_sta *sta, struct ssv_sta_info *sta_info, enum SSV6XXX_WSID_SEC key_type)
+ssv6xxx_enable_ps	smac/dev.c	/^void ssv6xxx_enable_ps(struct ssv_softc *sc)$/;"	f	signature:(struct ssv_softc *sc)
+ssv6xxx_enable_ps	smac/dev.h	/^void ssv6xxx_enable_ps(struct ssv_softc *sc);$/;"	p	signature:(struct ssv_softc *sc)
+ssv6xxx_enable_usb_acc	smac/dev.c	/^void ssv6xxx_enable_usb_acc(void *param, u8 epnum)$/;"	f	signature:(void *param, u8 epnum)
+ssv6xxx_enable_usb_acc	smac/dev.h	/^void ssv6xxx_enable_usb_acc(void *param, u8 epnum);$/;"	p	signature:(void *param, u8 epnum)
+ssv6xxx_encrypt_task	smac/dev.c	/^int ssv6xxx_encrypt_task (void *data)$/;"	f	signature:(void *data)
+ssv6xxx_encrypt_task	smac/dev.h	/^int ssv6xxx_encrypt_task (void *data);$/;"	p	signature:(void *data)
+ssv6xxx_enqueue_list_node	include/ssv_data_struct.h	/^static inline void ssv6xxx_enqueue_list_node(struct ssv6xxx_list_node *node, struct ssv6xxx_queue *ssv_queue) {$/;"	f	signature:(struct ssv6xxx_list_node *node, struct ssv6xxx_queue *ssv_queue)
+ssv6xxx_exit	smac/init.c	/^EXPORT_SYMBOL(ssv6xxx_exit);$/;"	v
+ssv6xxx_exit	smac/init.c	/^module_exit(ssv6xxx_exit);$/;"	v
+ssv6xxx_exit	smac/init.c	/^void ssv6xxx_exit(void)$/;"	f	signature:(void)
+ssv6xxx_exit	smac/init.h	/^void ssv6xxx_exit(void);$/;"	p	signature:(void)
+ssv6xxx_fill_lpbk_tx_desc	smac/dev.c	/^void ssv6xxx_fill_lpbk_tx_desc(struct sk_buff *skb, int security, unsigned char rate)$/;"	f	signature:(struct sk_buff *skb, int security, unsigned char rate)
+ssv6xxx_fill_lpbk_tx_desc	smac/dev.h	/^void ssv6xxx_fill_lpbk_tx_desc(struct sk_buff *skb, int security, unsigned char rate);$/;"	p	signature:(struct sk_buff *skb, int security, unsigned char rate)
+ssv6xxx_find_sta_by_addr	smac/dev.c	/^struct ieee80211_sta *ssv6xxx_find_sta_by_addr (struct ssv_softc *sc, u8 addr[6])$/;"	f	signature:(struct ssv_softc *sc, u8 addr[6])
+ssv6xxx_find_sta_by_addr	smac/dev.h	/^struct ieee80211_sta *ssv6xxx_find_sta_by_addr (struct ssv_softc *sc, u8 addr[6]);$/;"	p	signature:(struct ssv_softc *sc, u8 addr[6])
+ssv6xxx_find_sta_by_rx_skb	smac/dev.c	/^struct ieee80211_sta *ssv6xxx_find_sta_by_rx_skb (struct ssv_softc *sc, struct sk_buff *skb)$/;"	f	signature:(struct ssv_softc *sc, struct sk_buff *skb)
+ssv6xxx_find_sta_by_rx_skb	smac/dev.h	/^struct ieee80211_sta *ssv6xxx_find_sta_by_rx_skb (struct ssv_softc *sc, struct sk_buff *skb);$/;"	p	signature:(struct ssv_softc *sc, struct sk_buff *skb)
+ssv6xxx_find_txpktrun_no_from_BA	smac/dev.h	/^void ssv6xxx_find_txpktrun_no_from_BA(struct ssv_softc *sc, u32 start_ssn, u32 sn_bit_map[2]$/;"	p	signature:(struct ssv_softc *sc, u32 start_ssn, u32 sn_bit_map[2] , struct ssv_sta_priv_data *ssv_sta_priv)
+ssv6xxx_find_txpktrun_no_from_ssn	smac/ampdu.c	/^void ssv6xxx_find_txpktrun_no_from_ssn(struct ssv_softc *sc, u32 ssn,$/;"	f	signature:(struct ssv_softc *sc, u32 ssn, struct ssv_sta_priv_data *ssv_sta_priv)
+ssv6xxx_find_txpktrun_no_from_ssn	smac/dev.h	/^void ssv6xxx_find_txpktrun_no_from_ssn(struct ssv_softc *sc, u32 ssn,$/;"	p	signature:(struct ssv_softc *sc, u32 ssn, struct ssv_sta_priv_data *ssv_sta_priv)
+ssv6xxx_flash_read_all_map	smac/hal/hal.c	/^static void ssv6xxx_flash_read_all_map(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6xxx_flash_read_all_map	smac/init.c	/^void ssv6xxx_flash_read_all_map(struct ssv_hw *sh)$/;"	f	signature:(struct ssv_hw *sh)
+ssv6xxx_flash_read_all_map	smac/init.h	/^void ssv6xxx_flash_read_all_map(struct ssv_hw *sh);$/;"	p	signature:(struct ssv_hw *sh)
+ssv6xxx_foreach_sta	smac/dev.c	/^void ssv6xxx_foreach_sta (struct ssv_softc *sc, void (*sta_func)(struct ssv_softc *, struct ssv_sta_info *, void *), void *param)$/;"	f	signature:(struct ssv_softc *sc, void (*sta_func)(struct ssv_softc *, struct ssv_sta_info *, void *), void *param)
+ssv6xxx_foreach_sta	smac/dev.h	/^void ssv6xxx_foreach_sta (struct ssv_softc *sc,$/;"	p	signature:(struct ssv_softc *sc, void (*sta_func)(struct ssv_softc *, struct ssv_sta_info *, void *), void *param)
+ssv6xxx_foreach_vif_sta	smac/dev.c	/^void ssv6xxx_foreach_vif_sta (struct ssv_softc *sc,$/;"	f	signature:(struct ssv_softc *sc, struct ssv_vif_info *vif_info, void (*sta_func)(struct ssv_softc *, struct ssv_vif_info *, struct ssv_sta_info *, void *), void *param)
+ssv6xxx_foreach_vif_sta	smac/dev.h	/^void ssv6xxx_foreach_vif_sta (struct ssv_softc *sc,$/;"	p	signature:(struct ssv_softc *sc, struct ssv_vif_info *vif_info, void (*sta_func)(struct ssv_softc *, struct ssv_vif_info *, struct ssv_sta_info *, void *), void *param)
+ssv6xxx_frame_hdrlen	smac/dev.c	/^int ssv6xxx_frame_hdrlen(struct ieee80211_hdr *hdr, bool is_ht)$/;"	f	signature:(struct ieee80211_hdr *hdr, bool is_ht)
+ssv6xxx_frame_hdrlen	smac/dev.h	/^int ssv6xxx_frame_hdrlen(struct ieee80211_hdr *hdr, bool is_ht);$/;"	p	signature:(struct ieee80211_hdr *hdr, bool is_ht)
+ssv6xxx_freq_fops	ssvdevice/ssvdevice.c	/^static struct file_operations ssv6xxx_freq_fops = {$/;"	v	typeref:struct:file_operations	file:
+ssv6xxx_freq_open	ssvdevice/ssvdevice.c	/^static int ssv6xxx_freq_open(struct inode *inode, struct file *filp)$/;"	f	file:	signature:(struct inode *inode, struct file *filp)
+ssv6xxx_freq_read	ssvdevice/ssvdevice.c	/^static ssize_t ssv6xxx_freq_read(struct file *filp, char __user *buffer,$/;"	f	file:	signature:(struct file *filp, char __user *buffer, size_t count, loff_t *ppos)
+ssv6xxx_get_channel	smac/dev.c	/^int ssv6xxx_get_channel(struct ssv_softc *sc, int *pch)$/;"	f	signature:(struct ssv_softc *sc, int *pch)
+ssv6xxx_get_channel	smac/dev.h	/^int ssv6xxx_get_channel(struct ssv_softc *sc, int *pch);$/;"	p	signature:(struct ssv_softc *sc, int *pch)
+ssv6xxx_get_cmd_sequence	hwif/usb/usb.c	/^static u16 ssv6xxx_get_cmd_sequence(struct ssv6xxx_usb_glue *glue)$/;"	f	file:	signature:(struct ssv6xxx_usb_glue *glue)
+ssv6xxx_get_dev_status	platforms/rk3126-generic-wlan.c	/^extern int ssv6xxx_get_dev_status(void);$/;"	p	file:	signature:(void)
+ssv6xxx_get_dev_status	platforms/rk322x-generic-wlan.c	/^extern int ssv6xxx_get_dev_status(void);$/;"	p	file:	signature:(void)
+ssv6xxx_get_ffout_cnt	ssvdevice/ssv_cmd.c	/^static u32 ssv6xxx_get_ffout_cnt(u32 value, int tag)$/;"	f	file:	signature:(u32 value, int tag)
+ssv6xxx_get_fw_version	ssvdevice/ssv_cmd.c	/^static void ssv6xxx_get_fw_version(struct ssv_hw *sh, u32 *regval)$/;"	f	file:	signature:(struct ssv_hw *sh, u32 *regval)
+ssv6xxx_get_ic_time_tag	smac/dev.c	/^u64 ssv6xxx_get_ic_time_tag(struct ssv_hw *sh)$/;"	f	signature:(struct ssv_hw *sh)
+ssv6xxx_get_ic_time_tag	smac/dev.h	/^u64 ssv6xxx_get_ic_time_tag(struct ssv_hw *sh);$/;"	p	signature:(struct ssv_hw *sh)
+ssv6xxx_get_in_ffcnt	ssvdevice/ssv_cmd.c	/^static u32 ssv6xxx_get_in_ffcnt(u32 value, int tag)$/;"	f	file:	signature:(u32 value, int tag)
+ssv6xxx_get_promisc	smac/dev.c	/^int ssv6xxx_get_promisc(struct ssv_softc *sc, int *paccept)$/;"	f	signature:(struct ssv_softc *sc, int *paccept)
+ssv6xxx_get_promisc	smac/dev.h	/^int ssv6xxx_get_promisc(struct ssv_softc *sc, int *paccept);$/;"	p	signature:(struct ssv_softc *sc, int *paccept)
+ssv6xxx_get_rate	smac/ssv_rc.c	/^static void ssv6xxx_get_rate(void *priv, struct ieee80211_sta *sta, void *priv_sta,$/;"	f	file:	signature:(void *priv, struct ieee80211_sta *sta, void *priv_sta, struct ieee80211_tx_rate_control *txrc)
+ssv6xxx_get_rd_id_adr	ssvdevice/ssv_cmd.c	/^static void ssv6xxx_get_rd_id_adr(u32 *id_base_address)$/;"	f	file:	signature:(u32 *id_base_address)
+ssv6xxx_get_real_index	smac/dev.c	/^int ssv6xxx_get_real_index(struct ssv_softc *sc, struct sk_buff *skb)$/;"	f	signature:(struct ssv_softc *sc, struct sk_buff *skb)
+ssv6xxx_get_real_index	smac/dev.h	/^int ssv6xxx_get_real_index(struct ssv_softc *sc, struct sk_buff *skb);$/;"	p	signature:(struct ssv_softc *sc, struct sk_buff *skb)
+ssv6xxx_get_rx_desc_hdr_offset	smac/dev.c	/^int ssv6xxx_get_rx_desc_hdr_offset(struct sk_buff *skb)$/;"	f	signature:(struct sk_buff *skb)
+ssv6xxx_get_rx_desc_hdr_offset	smac/dev.h	/^int ssv6xxx_get_rx_desc_hdr_offset(struct sk_buff *skb);$/;"	p	signature:(struct sk_buff *skb)
+ssv6xxx_get_rx_desc_info	smac/dev.c	/^static void ssv6xxx_get_rx_desc_info(struct sk_buff *skb, u32 *packet_len, u32 *c_type,$/;"	f	file:	signature:(struct sk_buff *skb, u32 *packet_len, u32 *c_type, u32 *tx_pkt_run_no)
+ssv6xxx_get_sec_decode_err	smac/hal/hal.c	/^static int ssv6xxx_get_sec_decode_err(struct sk_buff *skb, bool *mic_err, bool *decode_err)$/;"	f	file:	signature:(struct sk_buff *skb, bool *mic_err, bool *decode_err)
+ssv6xxx_get_tx_desc_ctype	smac/dev.c	/^int ssv6xxx_get_tx_desc_ctype(struct sk_buff *skb)$/;"	f	signature:(struct sk_buff *skb)
+ssv6xxx_get_tx_desc_ctype	smac/dev.h	/^int ssv6xxx_get_tx_desc_ctype(struct sk_buff *skb);$/;"	p	signature:(struct sk_buff *skb)
+ssv6xxx_get_tx_desc_txq_idx	smac/dev.c	/^int ssv6xxx_get_tx_desc_txq_idx(struct sk_buff *skb)$/;"	f	signature:(struct sk_buff *skb)
+ssv6xxx_get_tx_desc_txq_idx	smac/dev.h	/^int ssv6xxx_get_tx_desc_txq_idx(struct sk_buff *skb);$/;"	p	signature:(struct sk_buff *skb)
+ssv6xxx_group_wpa_use_hw_cipher	smac/dev.c	/^static bool ssv6xxx_group_wpa_use_hw_cipher(struct ssv_softc *sc,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv, enum SSV_CIPHER_E cipher)
+ssv6xxx_hci_burst_read_word	hci/ssv_hci.c	/^static int ssv6xxx_hci_burst_read_word(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 *addr, u32 *regval, u8 reg_amount)$/;"	f	file:	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 *addr, u32 *regval, u8 reg_amount)
+ssv6xxx_hci_burst_safe_read_word	hci/ssv_hci.c	/^static int ssv6xxx_hci_burst_safe_read_word(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 *addr, u32 *regval, u8 reg_amount)$/;"	f	file:	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 *addr, u32 *regval, u8 reg_amount)
+ssv6xxx_hci_burst_safe_write_word	hci/ssv_hci.c	/^static int ssv6xxx_hci_burst_safe_write_word(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 *addr, u32 *regval, u8 reg_amount)$/;"	f	file:	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 *addr, u32 *regval, u8 reg_amount)
+ssv6xxx_hci_burst_write_word	hci/ssv_hci.c	/^static int ssv6xxx_hci_burst_write_word(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 *addr, u32 *regval, u8 reg_amount)$/;"	f	file:	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 *addr, u32 *regval, u8 reg_amount)
+ssv6xxx_hci_close_firmware	hci/ssv_hci.c	/^static void ssv6xxx_hci_close_firmware(void *image)$/;"	f	file:	signature:(void *image)
+ssv6xxx_hci_ctrl	hci/hctrl.h	/^struct ssv6xxx_hci_ctrl {$/;"	s
+ssv6xxx_hci_ctrl::debugfs_dir	hci/hctrl.h	/^ struct dentry *debugfs_dir;$/;"	m	struct:ssv6xxx_hci_ctrl	typeref:struct:ssv6xxx_hci_ctrl::dentry	access:public
+ssv6xxx_hci_ctrl::hci_flags	hci/hctrl.h	/^    u32 hci_flags;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+ssv6xxx_hci_ctrl::hci_mutex	hci/hctrl.h	/^    struct mutex hci_mutex;$/;"	m	struct:ssv6xxx_hci_ctrl	typeref:struct:ssv6xxx_hci_ctrl::mutex	access:public
+ssv6xxx_hci_ctrl::hci_rx_work	hci/hctrl.h	/^    struct work_struct hci_rx_work;$/;"	m	struct:ssv6xxx_hci_ctrl	typeref:struct:ssv6xxx_hci_ctrl::work_struct	access:public
+ssv6xxx_hci_ctrl::hci_start	hci/hctrl.h	/^    bool hci_start;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+ssv6xxx_hci_ctrl::hci_tx_task	hci/hctrl.h	/^ struct task_struct *hci_tx_task;$/;"	m	struct:ssv6xxx_hci_ctrl	typeref:struct:ssv6xxx_hci_ctrl::task_struct	access:public
+ssv6xxx_hci_ctrl::hci_tx_work	hci/hctrl.h	/^    struct work_struct hci_tx_work;$/;"	m	struct:ssv6xxx_hci_ctrl	typeref:struct:ssv6xxx_hci_ctrl::work_struct	access:public
+ssv6xxx_hci_ctrl::hci_tx_work	hci/hctrl.h	/^    struct work_struct hci_tx_work[SSV_HW_TXQ_NUM];$/;"	m	struct:ssv6xxx_hci_ctrl	typeref:struct:ssv6xxx_hci_ctrl::work_struct	access:public
+ssv6xxx_hci_ctrl::hci_work_queue	hci/hctrl.h	/^    struct workqueue_struct *hci_work_queue;$/;"	m	struct:ssv6xxx_hci_ctrl	typeref:struct:ssv6xxx_hci_ctrl::workqueue_struct	access:public
+ssv6xxx_hci_ctrl::hw_txq	hci/hctrl.h	/^    struct ssv_hw_txq hw_txq[SSV_HW_TXQ_NUM];$/;"	m	struct:ssv6xxx_hci_ctrl	typeref:struct:ssv6xxx_hci_ctrl::ssv_hw_txq	access:public
+ssv6xxx_hci_ctrl::int_lock	hci/hctrl.h	/^    spinlock_t int_lock;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+ssv6xxx_hci_ctrl::int_mask	hci/hctrl.h	/^    u32 int_mask;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+ssv6xxx_hci_ctrl::int_status	hci/hctrl.h	/^    u32 int_status;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+ssv6xxx_hci_ctrl::invalid_irq_count	hci/hctrl.h	/^    u32 invalid_irq_count;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+ssv6xxx_hci_ctrl::irq_count	hci/hctrl.h	/^    u32 irq_count;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+ssv6xxx_hci_ctrl::irq_enable	hci/hctrl.h	/^    bool irq_enable;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+ssv6xxx_hci_ctrl::irq_rx_pkt_count	hci/hctrl.h	/^    u32 irq_rx_pkt_count;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+ssv6xxx_hci_ctrl::irq_tx_pkt_count	hci/hctrl.h	/^    u32 irq_tx_pkt_count;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+ssv6xxx_hci_ctrl::isr_disable	hci/hctrl.h	/^ u32 isr_disable;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+ssv6xxx_hci_ctrl::isr_idle_time	hci/hctrl.h	/^    u32 isr_idle_time;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+ssv6xxx_hci_ctrl::isr_mib_enable	hci/hctrl.h	/^ u32 isr_mib_enable;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+ssv6xxx_hci_ctrl::isr_mib_reset	hci/hctrl.h	/^ u32 isr_mib_reset;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+ssv6xxx_hci_ctrl::isr_miss_cnt	hci/hctrl.h	/^    u32 isr_miss_cnt;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+ssv6xxx_hci_ctrl::isr_reset_work	hci/hctrl.h	/^ struct work_struct isr_reset_work;$/;"	m	struct:ssv6xxx_hci_ctrl	typeref:struct:ssv6xxx_hci_ctrl::work_struct	access:public
+ssv6xxx_hci_ctrl::isr_routine_time	hci/hctrl.h	/^    u32 isr_routine_time;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+ssv6xxx_hci_ctrl::isr_running	hci/hctrl.h	/^    u32 isr_running;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+ssv6xxx_hci_ctrl::isr_rx_idle_time	hci/hctrl.h	/^    u32 isr_rx_idle_time;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+ssv6xxx_hci_ctrl::isr_rx_io_count	hci/hctrl.h	/^ u32 isr_rx_io_count;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+ssv6xxx_hci_ctrl::isr_rx_io_time	hci/hctrl.h	/^ long long isr_rx_io_time;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+ssv6xxx_hci_ctrl::isr_rx_proc_time	hci/hctrl.h	/^ long long isr_rx_proc_time;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+ssv6xxx_hci_ctrl::isr_rx_time	hci/hctrl.h	/^    u32 isr_rx_time;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+ssv6xxx_hci_ctrl::isr_summary_eable	hci/hctrl.h	/^    u32 isr_summary_eable;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+ssv6xxx_hci_ctrl::isr_total_time	hci/hctrl.h	/^ long long isr_total_time;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+ssv6xxx_hci_ctrl::isr_tx_io_count	hci/hctrl.h	/^ u32 isr_tx_io_count;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+ssv6xxx_hci_ctrl::isr_tx_io_time	hci/hctrl.h	/^ long long isr_tx_io_time;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+ssv6xxx_hci_ctrl::isr_tx_time	hci/hctrl.h	/^    u32 isr_tx_time;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+ssv6xxx_hci_ctrl::prev_isr_jiffes	hci/hctrl.h	/^    unsigned long prev_isr_jiffes;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+ssv6xxx_hci_ctrl::prev_rx_isr_jiffes	hci/hctrl.h	/^    unsigned long prev_rx_isr_jiffes;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+ssv6xxx_hci_ctrl::read_rs0_info_fail	hci/hctrl.h	/^    u32 read_rs0_info_fail;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+ssv6xxx_hci_ctrl::read_rs1_info_fail	hci/hctrl.h	/^    u32 read_rs1_info_fail;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+ssv6xxx_hci_ctrl::real_tx_irq_count	hci/hctrl.h	/^    u32 real_tx_irq_count;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+ssv6xxx_hci_ctrl::redownload	hci/hctrl.h	/^    bool redownload;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+ssv6xxx_hci_ctrl::rx_buf	hci/hctrl.h	/^    struct sk_buff *rx_buf;$/;"	m	struct:ssv6xxx_hci_ctrl	typeref:struct:ssv6xxx_hci_ctrl::sk_buff	access:public
+ssv6xxx_hci_ctrl::rx_info	hci/hctrl.h	/^ struct ssv6xxx_rx_hw_info rx_info;$/;"	m	struct:ssv6xxx_hci_ctrl	typeref:struct:ssv6xxx_hci_ctrl::ssv6xxx_rx_hw_info	access:public
+ssv6xxx_hci_ctrl::rx_irq_count	hci/hctrl.h	/^    u32 rx_irq_count;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+ssv6xxx_hci_ctrl::rx_pkt	hci/hctrl.h	/^    u32 rx_pkt;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+ssv6xxx_hci_ctrl::rx_work_running	hci/hctrl.h	/^    u32 rx_work_running;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+ssv6xxx_hci_ctrl::shi	hci/hctrl.h	/^    struct ssv6xxx_hci_info *shi;$/;"	m	struct:ssv6xxx_hci_ctrl	typeref:struct:ssv6xxx_hci_ctrl::ssv6xxx_hci_info	access:public
+ssv6xxx_hci_ctrl::tx_info	hci/hctrl.h	/^ struct ssv6xxx_tx_hw_info tx_info;$/;"	m	struct:ssv6xxx_hci_ctrl	typeref:struct:ssv6xxx_hci_ctrl::ssv6xxx_tx_hw_info	access:public
+ssv6xxx_hci_ctrl::tx_irq_count	hci/hctrl.h	/^    u32 tx_irq_count;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+ssv6xxx_hci_ctrl::tx_wait_q	hci/hctrl.h	/^ wait_queue_head_t tx_wait_q;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+ssv6xxx_hci_ctrl::txq_mask	hci/hctrl.h	/^    u32 txq_mask;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+ssv6xxx_hci_ctrl::txq_mask_lock	hci/hctrl.h	/^    struct mutex txq_mask_lock;$/;"	m	struct:ssv6xxx_hci_ctrl	typeref:struct:ssv6xxx_hci_ctrl::mutex	access:public
+ssv6xxx_hci_ctrl::write_hw_config	hci/hctrl.h	/^    int write_hw_config;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+ssv6xxx_hci_ctrl::xmit_running	hci/hctrl.h	/^    u32 xmit_running;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+ssv6xxx_hci_dbgprint	smac/dev.c	/^void ssv6xxx_hci_dbgprint(void *argc, u32 log_id, const char *fmt,...)$/;"	f	signature:(void *argc, u32 log_id, const char *fmt,...)
+ssv6xxx_hci_dbgprint	smac/dev.h	/^void ssv6xxx_hci_dbgprint(void *argc, u32 log_id, const char *fmt,...);$/;"	p	signature:(void *argc, u32 log_id, const char *fmt,...)
+ssv6xxx_hci_deinit_debugfs	hci/ssv_hci.c	/^void ssv6xxx_hci_deinit_debugfs(struct ssv6xxx_hci_ctrl *ctrl_hci)$/;"	f	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci)
+ssv6xxx_hci_deregister	hci/ssv_hci.c	/^EXPORT_SYMBOL(ssv6xxx_hci_deregister);$/;"	v
+ssv6xxx_hci_deregister	hci/ssv_hci.c	/^int ssv6xxx_hci_deregister(struct ssv6xxx_hci_info *shi)$/;"	f	signature:(struct ssv6xxx_hci_info *shi)
+ssv6xxx_hci_deregister	hci/ssv_hci.h	/^int ssv6xxx_hci_deregister(struct ssv6xxx_hci_info *);$/;"	p	signature:(struct ssv6xxx_hci_info *)
+ssv6xxx_hci_enqueue	hci/ssv_hci.c	/^static int ssv6xxx_hci_enqueue(struct ssv6xxx_hci_ctrl *ctrl_hci, struct sk_buff *skb, int txqid, u32 tx_flags)$/;"	f	file:	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci, struct sk_buff *skb, int txqid, u32 tx_flags)
+ssv6xxx_hci_exit	hci/ssv_hci.c	/^EXPORT_SYMBOL(ssv6xxx_hci_exit);$/;"	v
+ssv6xxx_hci_exit	hci/ssv_hci.c	/^module_exit(ssv6xxx_hci_exit);$/;"	v
+ssv6xxx_hci_exit	hci/ssv_hci.c	/^void ssv6xxx_hci_exit(void)$/;"	f	signature:(void)
+ssv6xxx_hci_exit	hci/ssv_hci.h	/^void ssv6xxx_hci_exit(void);$/;"	p	signature:(void)
+ssv6xxx_hci_force_tx_handler	hci/ssv_hci.c	/^static int ssv6xxx_hci_force_tx_handler(struct ssv6xxx_hci_ctrl *hci_ctrl, void *dev,$/;"	f	file:	signature:(struct ssv6xxx_hci_ctrl *hci_ctrl, void *dev, int max_count, int *err)
+ssv6xxx_hci_force_xmit	hci/ssv_hci.c	/^static int ssv6xxx_hci_force_xmit(struct ssv6xxx_hci_ctrl *hci_ctrl, struct ssv_hw_txq *hw_txq,$/;"	f	file:	signature:(struct ssv6xxx_hci_ctrl *hci_ctrl, struct ssv_hw_txq *hw_txq, int max_count, int *err, int free_tx_page)
+ssv6xxx_hci_get_firmware	hci/ssv_hci.c	/^static int ssv6xxx_hci_get_firmware(struct device *dev, char *user_mainfw, const struct firmware **mainfw)$/;"	f	file:	signature:(struct device *dev, char *user_mainfw, const struct firmware **mainfw)
+ssv6xxx_hci_get_int_bitno	hci/ssv_hci.c	/^static inline u32 ssv6xxx_hci_get_int_bitno(struct ssv6xxx_hci_ctrl *ctrl_hci, int txqid)$/;"	f	file:	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci, int txqid)
+ssv6xxx_hci_hci_inq_info	hci/ssv_hci.c	/^void ssv6xxx_hci_hci_inq_info(struct ssv6xxx_hci_ctrl *ctrl_hci, int *used_id)$/;"	f	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci, int *used_id)
+ssv6xxx_hci_hci_inq_info	hci/ssv_hci.h	/^void ssv6xxx_hci_hci_inq_info(struct ssv6xxx_hci_ctrl *ctrl_hci, int *used_id);$/;"	p	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci, int *used_id)
+ssv6xxx_hci_info	hci/ssv_hci.h	/^struct ssv6xxx_hci_info {$/;"	s
+ssv6xxx_hci_info::dbgprint	hci/ssv_hci.h	/^ void (*dbgprint)(void *, u32 log_id, const char *fmt,...);$/;"	m	struct:ssv6xxx_hci_info	access:public
+ssv6xxx_hci_info::dev	hci/ssv_hci.h	/^    struct device *dev;$/;"	m	struct:ssv6xxx_hci_info	typeref:struct:ssv6xxx_hci_info::device	access:public
+ssv6xxx_hci_info::hci_ctrl	hci/ssv_hci.h	/^    struct ssv6xxx_hci_ctrl *hci_ctrl;$/;"	m	struct:ssv6xxx_hci_info	typeref:struct:ssv6xxx_hci_info::ssv6xxx_hci_ctrl	access:public
+ssv6xxx_hci_info::hci_is_rx_q_full	hci/ssv_hci.h	/^    int (*hci_is_rx_q_full)(void *);$/;"	m	struct:ssv6xxx_hci_info	access:public
+ssv6xxx_hci_info::hci_ops	hci/ssv_hci.h	/^    struct ssv6xxx_hci_ops *hci_ops;$/;"	m	struct:ssv6xxx_hci_info	typeref:struct:ssv6xxx_hci_info::ssv6xxx_hci_ops	access:public
+ssv6xxx_hci_info::hci_peek_next_pkt_len_cb	hci/ssv_hci.h	/^    int (*hci_peek_next_pkt_len_cb)(struct sk_buff *, void *);$/;"	m	struct:ssv6xxx_hci_info	access:public
+ssv6xxx_hci_info::hci_post_tx_cb	hci/ssv_hci.h	/^    void (*hci_post_tx_cb)(struct sk_buff_head *, void *);$/;"	m	struct:ssv6xxx_hci_info	access:public
+ssv6xxx_hci_info::hci_pre_tx_cb	hci/ssv_hci.h	/^    void (*hci_pre_tx_cb)(struct sk_buff *, void *);$/;"	m	struct:ssv6xxx_hci_info	access:public
+ssv6xxx_hci_info::hci_rx_cb	hci/ssv_hci.h	/^    int (*hci_rx_cb)(struct sk_buff *, void *);$/;"	m	struct:ssv6xxx_hci_info	access:public
+ssv6xxx_hci_info::hci_rx_cb	hci/ssv_hci.h	/^    int (*hci_rx_cb)(struct sk_buff_head *, void *);$/;"	m	struct:ssv6xxx_hci_info	access:public
+ssv6xxx_hci_info::hci_rx_mode_cb	hci/ssv_hci.h	/^    int (*hci_rx_mode_cb)(void *);$/;"	m	struct:ssv6xxx_hci_info	access:public
+ssv6xxx_hci_info::hci_skb_update_cb	hci/ssv_hci.h	/^    void (*hci_skb_update_cb)(struct sk_buff *, void *);$/;"	m	struct:ssv6xxx_hci_info	access:public
+ssv6xxx_hci_info::hci_tx_buf_free_cb	hci/ssv_hci.h	/^    void (*hci_tx_buf_free_cb)(struct sk_buff *, void *);$/;"	m	struct:ssv6xxx_hci_info	access:public
+ssv6xxx_hci_info::hci_tx_flow_ctrl_cb	hci/ssv_hci.h	/^    int (*hci_tx_flow_ctrl_cb)(void *, int, bool, int debug);$/;"	m	struct:ssv6xxx_hci_info	access:public
+ssv6xxx_hci_info::hci_tx_q_empty_cb	hci/ssv_hci.h	/^    void (*hci_tx_q_empty_cb)(u32 txq_no, void *);$/;"	m	struct:ssv6xxx_hci_info	access:public
+ssv6xxx_hci_info::if_ops	hci/ssv_hci.h	/^    struct ssv6xxx_hwif_ops *if_ops;$/;"	m	struct:ssv6xxx_hci_info	typeref:struct:ssv6xxx_hci_info::ssv6xxx_hwif_ops	access:public
+ssv6xxx_hci_info::sc	hci/ssv_hci.h	/^    struct ssv_softc *sc;$/;"	m	struct:ssv6xxx_hci_info	typeref:struct:ssv6xxx_hci_info::ssv_softc	access:public
+ssv6xxx_hci_info::sh	hci/ssv_hci.h	/^    struct ssv_hw *sh;$/;"	m	struct:ssv6xxx_hci_info	typeref:struct:ssv6xxx_hci_info::ssv_hw	access:public
+ssv6xxx_hci_info::skb_alloc	hci/ssv_hci.h	/^    struct sk_buff *(*skb_alloc) (void *app_param, s32 len);$/;"	m	struct:ssv6xxx_hci_info	typeref:struct:ssv6xxx_hci_info::skb_alloc	access:public
+ssv6xxx_hci_info::skb_free	hci/ssv_hci.h	/^    void (*skb_free) (void *app_param, struct sk_buff *skb);$/;"	m	struct:ssv6xxx_hci_info	access:public
+ssv6xxx_hci_info::write_hw_config_cb	hci/ssv_hci.h	/^    void (*write_hw_config_cb)(void *param, u32 addr, u32 value);$/;"	m	struct:ssv6xxx_hci_info	access:public
+ssv6xxx_hci_init	hci/ssv_hci.c	/^EXPORT_SYMBOL(ssv6xxx_hci_init);$/;"	v
+ssv6xxx_hci_init	hci/ssv_hci.c	/^int ssv6xxx_hci_init(void)$/;"	f	signature:(void)
+ssv6xxx_hci_init	hci/ssv_hci.c	/^module_init(ssv6xxx_hci_init);$/;"	v
+ssv6xxx_hci_init	hci/ssv_hci.h	/^int ssv6xxx_hci_init(void);$/;"	p	signature:(void)
+ssv6xxx_hci_init_debugfs	hci/ssv_hci.c	/^bool ssv6xxx_hci_init_debugfs(struct ssv6xxx_hci_ctrl *ctrl_hci, struct dentry *dev_deugfs_dir)$/;"	f	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci, struct dentry *dev_deugfs_dir)
+ssv6xxx_hci_interface_reset	hci/ssv_hci.c	/^static int ssv6xxx_hci_interface_reset(struct ssv6xxx_hci_ctrl *ctrl_hci)$/;"	f	file:	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci)
+ssv6xxx_hci_irq_disable	hci/ssv_hci.c	/^static int ssv6xxx_hci_irq_disable(struct ssv6xxx_hci_ctrl *ctrl_hci)$/;"	f	file:	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci)
+ssv6xxx_hci_irq_enable	hci/ssv_hci.c	/^static int ssv6xxx_hci_irq_enable(struct ssv6xxx_hci_ctrl *ctrl_hci)$/;"	f	file:	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci)
+ssv6xxx_hci_irq_register	hci/ssv_hci.c	/^static void ssv6xxx_hci_irq_register(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 irq_mask)$/;"	f	file:	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 irq_mask)
+ssv6xxx_hci_is_frame_send	hci/ssv_hci.c	/^static bool ssv6xxx_hci_is_frame_send(struct ssv6xxx_hci_ctrl *hci_ctrl)$/;"	f	file:	signature:(struct ssv6xxx_hci_ctrl *hci_ctrl)
+ssv6xxx_hci_is_txq_empty	hci/ssv_hci.c	/^static bool ssv6xxx_hci_is_txq_empty(struct ssv6xxx_hci_ctrl *ctrl_hci, int txqid)$/;"	f	file:	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci, int txqid)
+ssv6xxx_hci_isr	hci/ssv_hci.c	/^irqreturn_t ssv6xxx_hci_isr(int irq, void *args)$/;"	f	signature:(int irq, void *args)
+ssv6xxx_hci_isr_reset	hci/ssv_hci.c	/^static void ssv6xxx_hci_isr_reset(struct work_struct *work)$/;"	f	file:	signature:(struct work_struct *work)
+ssv6xxx_hci_load_firmware_openfile	hci/ssv_hci.c	/^static int ssv6xxx_hci_load_firmware_openfile(struct ssv6xxx_hci_ctrl *hci_ctrl, u8 *firmware_name)$/;"	f	file:	signature:(struct ssv6xxx_hci_ctrl *hci_ctrl, u8 *firmware_name)
+ssv6xxx_hci_load_firmware_request	hci/ssv_hci.c	/^static int ssv6xxx_hci_load_firmware_request(struct ssv6xxx_hci_ctrl *hci_ctrl, u8 *firmware_name)$/;"	f	file:	signature:(struct ssv6xxx_hci_ctrl *hci_ctrl, u8 *firmware_name)
+ssv6xxx_hci_load_fw	hci/ssv_hci.c	/^static int ssv6xxx_hci_load_fw(struct ssv6xxx_hci_ctrl *hci_ctrl, u8 *firmware_name, u8 openfile)$/;"	f	file:	signature:(struct ssv6xxx_hci_ctrl *hci_ctrl, u8 *firmware_name, u8 openfile)
+ssv6xxx_hci_load_fw_disable_mcu	hci/ssv_hci.c	/^int ssv6xxx_hci_load_fw_disable_mcu(struct ssv6xxx_hci_ctrl *ctrl_hci)$/;"	f	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci)
+ssv6xxx_hci_load_fw_disable_mcu	hci/ssv_hci.h	/^int ssv6xxx_hci_load_fw_disable_mcu(struct ssv6xxx_hci_ctrl *ctrl_hci);$/;"	p	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci)
+ssv6xxx_hci_load_fw_enable_mcu	hci/ssv_hci.c	/^void ssv6xxx_hci_load_fw_enable_mcu(struct ssv6xxx_hci_ctrl *ctrl_hci)$/;"	f	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci)
+ssv6xxx_hci_load_fw_enable_mcu	hci/ssv_hci.h	/^void ssv6xxx_hci_load_fw_enable_mcu(struct ssv6xxx_hci_ctrl *ctrl_hci);$/;"	p	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci)
+ssv6xxx_hci_load_fw_get_status	hci/ssv_hci.c	/^int ssv6xxx_hci_load_fw_get_status(struct ssv6xxx_hci_ctrl *ctrl_hci, int *status)$/;"	f	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci, int *status)
+ssv6xxx_hci_load_fw_get_status	hci/ssv_hci.h	/^int ssv6xxx_hci_load_fw_get_status(struct ssv6xxx_hci_ctrl *ctrl_hci, int *status);$/;"	p	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci, int *status)
+ssv6xxx_hci_load_fw_post_config_device	hci/ssv_hci.c	/^void ssv6xxx_hci_load_fw_post_config_device(struct ssv6xxx_hci_ctrl *ctrl_hci)$/;"	f	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci)
+ssv6xxx_hci_load_fw_post_config_device	hci/ssv_hci.h	/^void ssv6xxx_hci_load_fw_post_config_device(struct ssv6xxx_hci_ctrl *ctrl_hci);$/;"	p	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci)
+ssv6xxx_hci_load_fw_pre_config_device	hci/ssv_hci.c	/^void ssv6xxx_hci_load_fw_pre_config_device(struct ssv6xxx_hci_ctrl *ctrl_hci)$/;"	f	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci)
+ssv6xxx_hci_load_fw_pre_config_device	hci/ssv_hci.h	/^void ssv6xxx_hci_load_fw_pre_config_device(struct ssv6xxx_hci_ctrl *ctrl_hci);$/;"	p	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci)
+ssv6xxx_hci_load_fw_set_status	hci/ssv_hci.c	/^int ssv6xxx_hci_load_fw_set_status(struct ssv6xxx_hci_ctrl *ctrl_hci, int status)$/;"	f	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci, int status)
+ssv6xxx_hci_load_fw_set_status	hci/ssv_hci.h	/^int ssv6xxx_hci_load_fw_set_status(struct ssv6xxx_hci_ctrl *ctrl_hci, int status);$/;"	p	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci, int status)
+ssv6xxx_hci_open_firmware	hci/ssv_hci.c	/^static void *ssv6xxx_hci_open_firmware(char *user_mainfw)$/;"	f	file:	signature:(char *user_mainfw)
+ssv6xxx_hci_ops	hci/ssv_hci.h	/^struct ssv6xxx_hci_ops {$/;"	s
+ssv6xxx_hci_ops::hci_burst_read_word	hci/ssv_hci.h	/^    int (*hci_burst_read_word)(struct ssv6xxx_hci_ctrl *hctrl, u32 *addr, u32 *regval, u8 reg_amount);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+ssv6xxx_hci_ops::hci_burst_safe_read_word	hci/ssv_hci.h	/^    int (*hci_burst_safe_read_word)(struct ssv6xxx_hci_ctrl *hctrl, u32 *addr, u32 *regval, u8 reg_amount);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+ssv6xxx_hci_ops::hci_burst_safe_write_word	hci/ssv_hci.h	/^    int (*hci_burst_safe_write_word)(struct ssv6xxx_hci_ctrl *hctrl, u32 *addr, u32 *regval, u8 reg_amount);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+ssv6xxx_hci_ops::hci_burst_write_word	hci/ssv_hci.h	/^    int (*hci_burst_write_word)(struct ssv6xxx_hci_ctrl *hctrl, u32 *addr, u32 *regval, u8 reg_amount);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+ssv6xxx_hci_ops::hci_deinit_debugfs	hci/ssv_hci.h	/^    void (*hci_deinit_debugfs)(struct ssv6xxx_hci_ctrl *hctrl);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+ssv6xxx_hci_ops::hci_init_debugfs	hci/ssv_hci.h	/^    bool (*hci_init_debugfs)(struct ssv6xxx_hci_ctrl *hctrl, struct dentry *dev_deugfs_dir);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+ssv6xxx_hci_ops::hci_interface_reset	hci/ssv_hci.h	/^    int (*hci_interface_reset)(struct ssv6xxx_hci_ctrl *hctrl);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+ssv6xxx_hci_ops::hci_load_fw	hci/ssv_hci.h	/^    int (*hci_load_fw)(struct ssv6xxx_hci_ctrl *hctrl, u8 *firmware_name, u8 openfile);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+ssv6xxx_hci_ops::hci_pmu_wakeup	hci/ssv_hci.h	/^    int (*hci_pmu_wakeup)(struct ssv6xxx_hci_ctrl *hctrl);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+ssv6xxx_hci_ops::hci_read_word	hci/ssv_hci.h	/^    int (*hci_read_word)(struct ssv6xxx_hci_ctrl *hctrl, u32 addr, u32 *regval);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+ssv6xxx_hci_ops::hci_safe_read_word	hci/ssv_hci.h	/^    int (*hci_safe_read_word)(struct ssv6xxx_hci_ctrl *hctrl, u32 addr, u32 *regval);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+ssv6xxx_hci_ops::hci_safe_write_word	hci/ssv_hci.h	/^    int (*hci_safe_write_word)(struct ssv6xxx_hci_ctrl *hctrl, u32 addr, u32 regval);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+ssv6xxx_hci_ops::hci_send_cmd	hci/ssv_hci.h	/^    int (*hci_send_cmd)(struct ssv6xxx_hci_ctrl *hctrl, struct sk_buff *);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+ssv6xxx_hci_ops::hci_start	hci/ssv_hci.h	/^    int (*hci_start)(struct ssv6xxx_hci_ctrl *hctrl);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+ssv6xxx_hci_ops::hci_stop	hci/ssv_hci.h	/^    int (*hci_stop)(struct ssv6xxx_hci_ctrl *hctrl);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+ssv6xxx_hci_ops::hci_sysplf_reset	hci/ssv_hci.h	/^    int (*hci_sysplf_reset)(struct ssv6xxx_hci_ctrl *hctrl, u32 addr, u32 value);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+ssv6xxx_hci_ops::hci_tx	hci/ssv_hci.h	/^    int (*hci_tx)(struct ssv6xxx_hci_ctrl *hctrl, struct sk_buff *, int, u32);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+ssv6xxx_hci_ops::hci_tx_pause	hci/ssv_hci.h	/^    int (*hci_tx_pause)(struct ssv6xxx_hci_ctrl *hctrl, u32 txq_mask);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+ssv6xxx_hci_ops::hci_tx_resume	hci/ssv_hci.h	/^    int (*hci_tx_resume)(struct ssv6xxx_hci_ctrl *hctrl, u32 txq_mask);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+ssv6xxx_hci_ops::hci_txq_empty	hci/ssv_hci.h	/^    bool (*hci_txq_empty)(struct ssv6xxx_hci_ctrl *hctrl, int txqid);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+ssv6xxx_hci_ops::hci_txq_flush	hci/ssv_hci.h	/^    int (*hci_txq_flush)(struct ssv6xxx_hci_ctrl *hctrl, u32 txq_mask);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+ssv6xxx_hci_ops::hci_txq_flush_by_sta	hci/ssv_hci.h	/^    int (*hci_txq_flush_by_sta)(struct ssv6xxx_hci_ctrl *hctrl, int aid);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+ssv6xxx_hci_ops::hci_write_hw_config	hci/ssv_hci.h	/^    void (*hci_write_hw_config)(struct ssv6xxx_hci_ctrl *hctrl, int val);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+ssv6xxx_hci_ops::hci_write_sram	hci/ssv_hci.h	/^    int (*hci_write_sram)(struct ssv6xxx_hci_ctrl *hctrl, u32 addr, u8* data, u32 size);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+ssv6xxx_hci_ops::hci_write_word	hci/ssv_hci.h	/^    int (*hci_write_word)(struct ssv6xxx_hci_ctrl *hctrl, u32 addr, u32 regval);$/;"	m	struct:ssv6xxx_hci_ops	access:public
+ssv6xxx_hci_pmu_wakeup	hci/ssv_hci.c	/^static int ssv6xxx_hci_pmu_wakeup(struct ssv6xxx_hci_ctrl *ctrl_hci)$/;"	f	file:	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci)
+ssv6xxx_hci_read_fw_block	hci/ssv_hci.c	/^static int ssv6xxx_hci_read_fw_block(char *buf, int len, void *image)$/;"	f	file:	signature:(char *buf, int len, void *image)
+ssv6xxx_hci_read_word	hci/ssv_hci.c	/^static int ssv6xxx_hci_read_word(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 addr, u32 *regval)$/;"	f	file:	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 addr, u32 *regval)
+ssv6xxx_hci_register	hci/ssv_hci.c	/^EXPORT_SYMBOL(ssv6xxx_hci_register);$/;"	v
+ssv6xxx_hci_register	hci/ssv_hci.c	/^int ssv6xxx_hci_register(struct ssv6xxx_hci_info *shi)$/;"	f	signature:(struct ssv6xxx_hci_info *shi)
+ssv6xxx_hci_register	hci/ssv_hci.h	/^int ssv6xxx_hci_register(struct ssv6xxx_hci_info *);$/;"	p	signature:(struct ssv6xxx_hci_info *)
+ssv6xxx_hci_reset_cpu	hci/ssv_hci.c	/^int ssv6xxx_hci_reset_cpu(struct ssv6xxx_hci_ctrl *ctrl_hci)$/;"	f	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci)
+ssv6xxx_hci_rx_mode	smac/init.c	/^static int ssv6xxx_hci_rx_mode(void *args)$/;"	f	file:	signature:(void *args)
+ssv6xxx_hci_rx_work	hci/ssv_hci.c	/^static void ssv6xxx_hci_rx_work(struct work_struct *work)$/;"	f	file:	signature:(struct work_struct *work)
+ssv6xxx_hci_safe_read_word	hci/ssv_hci.c	/^static int ssv6xxx_hci_safe_read_word(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 addr, u32 *regval)$/;"	f	file:	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 addr, u32 *regval)
+ssv6xxx_hci_safe_write_word	hci/ssv_hci.c	/^static int ssv6xxx_hci_safe_write_word(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 addr, u32 regval)$/;"	f	file:	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 addr, u32 regval)
+ssv6xxx_hci_send_cmd	hci/ssv_hci.c	/^static int ssv6xxx_hci_send_cmd(struct ssv6xxx_hci_ctrl *ctrl_hci, struct sk_buff *skb)$/;"	f	file:	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci, struct sk_buff *skb)
+ssv6xxx_hci_start	hci/ssv_hci.c	/^static int ssv6xxx_hci_start(struct ssv6xxx_hci_ctrl *ctrl_hci)$/;"	f	file:	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci)
+ssv6xxx_hci_start_acc	hci/ssv_hci.c	/^static int ssv6xxx_hci_start_acc(struct ssv6xxx_hci_ctrl *ctrl_hci)$/;"	f	file:	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci)
+ssv6xxx_hci_stop	hci/ssv_hci.c	/^static int ssv6xxx_hci_stop(struct ssv6xxx_hci_ctrl *ctrl_hci)$/;"	f	file:	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci)
+ssv6xxx_hci_stop_acc	hci/ssv_hci.c	/^static int ssv6xxx_hci_stop_acc(struct ssv6xxx_hci_ctrl *ctrl_hci)$/;"	f	file:	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci)
+ssv6xxx_hci_sysplf_reset	hci/ssv_hci.c	/^static int ssv6xxx_hci_sysplf_reset(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 addr, u32 value)$/;"	f	file:	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 addr, u32 value)
+ssv6xxx_hci_trigger_tx	hci/ssv_hci.c	/^static void ssv6xxx_hci_trigger_tx(struct ssv6xxx_hci_ctrl *ctrl_hci)$/;"	f	file:	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci)
+ssv6xxx_hci_tx_handler	hci/ssv_hci.c	/^static int ssv6xxx_hci_tx_handler(struct ssv6xxx_hci_ctrl *ctrl_hci, void *dev, int max_count)$/;"	f	file:	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci, void *dev, int max_count)
+ssv6xxx_hci_tx_task	hci/ssv_hci.c	/^static int ssv6xxx_hci_tx_task (void *data)$/;"	f	file:	signature:(void *data)
+ssv6xxx_hci_tx_work	hci/ssv_hci.c	/^void ssv6xxx_hci_tx_work(struct work_struct *work)$/;"	f	signature:(struct work_struct *work)
+ssv6xxx_hci_txq_flush	hci/ssv_hci.c	/^static int ssv6xxx_hci_txq_flush(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 txq_mask)$/;"	f	file:	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 txq_mask)
+ssv6xxx_hci_txq_flush_by_sta	hci/ssv_hci.c	/^static int ssv6xxx_hci_txq_flush_by_sta(struct ssv6xxx_hci_ctrl *ctrl_hci, int aid)$/;"	f	file:	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci, int aid)
+ssv6xxx_hci_txq_info	hci/hctrl.h	/^struct ssv6xxx_hci_txq_info {$/;"	s
+ssv6xxx_hci_txq_info2	hci/hctrl.h	/^struct ssv6xxx_hci_txq_info2 {$/;"	s
+ssv6xxx_hci_txq_info2::rsvd	hci/hctrl.h	/^    u32 rsvd:11;$/;"	m	struct:ssv6xxx_hci_txq_info2	access:public
+ssv6xxx_hci_txq_info2::tx_use_id	hci/hctrl.h	/^    u32 tx_use_id:8;$/;"	m	struct:ssv6xxx_hci_txq_info2	access:public
+ssv6xxx_hci_txq_info2::tx_use_page	hci/hctrl.h	/^ u32 tx_use_page:9;$/;"	m	struct:ssv6xxx_hci_txq_info2	access:public
+ssv6xxx_hci_txq_info2::txq4_size	hci/hctrl.h	/^ u32 txq4_size:4;$/;"	m	struct:ssv6xxx_hci_txq_info2	access:public
+ssv6xxx_hci_txq_info::tx_use_id	hci/hctrl.h	/^    u32 tx_use_id:6;$/;"	m	struct:ssv6xxx_hci_txq_info	access:public
+ssv6xxx_hci_txq_info::tx_use_page	hci/hctrl.h	/^ u32 tx_use_page:8;$/;"	m	struct:ssv6xxx_hci_txq_info	access:public
+ssv6xxx_hci_txq_info::txq0_size	hci/hctrl.h	/^    u32 txq0_size:4;$/;"	m	struct:ssv6xxx_hci_txq_info	access:public
+ssv6xxx_hci_txq_info::txq1_size	hci/hctrl.h	/^ u32 txq1_size:4;$/;"	m	struct:ssv6xxx_hci_txq_info	access:public
+ssv6xxx_hci_txq_info::txq2_size	hci/hctrl.h	/^ u32 txq2_size:5;$/;"	m	struct:ssv6xxx_hci_txq_info	access:public
+ssv6xxx_hci_txq_info::txq3_size	hci/hctrl.h	/^ u32 txq3_size:5;$/;"	m	struct:ssv6xxx_hci_txq_info	access:public
+ssv6xxx_hci_txq_pause	hci/ssv_hci.c	/^static int ssv6xxx_hci_txq_pause(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 txq_mask)$/;"	f	file:	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 txq_mask)
+ssv6xxx_hci_txq_resume	hci/ssv_hci.c	/^static int ssv6xxx_hci_txq_resume(struct ssv6xxx_hci_ctrl *hci_ctrl, u32 txq_mask)$/;"	f	file:	signature:(struct ssv6xxx_hci_ctrl *hci_ctrl, u32 txq_mask)
+ssv6xxx_hci_usb_tx_handler	hci/ssv_hci.c	/^static int ssv6xxx_hci_usb_tx_handler(struct ssv6xxx_hci_ctrl *ctrl_hci, void *dev, int max_count, int *err)$/;"	f	file:	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci, void *dev, int max_count, int *err)
+ssv6xxx_hci_usb_tx_handler	hci/ssv_hci.c	/^static int ssv6xxx_hci_usb_tx_handler(struct ssv6xxx_hci_ctrl *ctrl_hci, void *dev, int max_count, int *err);$/;"	p	file:	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci, void *dev, int max_count, int *err)
+ssv6xxx_hci_write_hw_config	hci/ssv_hci.c	/^static void ssv6xxx_hci_write_hw_config(struct ssv6xxx_hci_ctrl *ctrl_hci, int val)$/;"	f	file:	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci, int val)
+ssv6xxx_hci_write_sram	hci/ssv_hci.c	/^static int ssv6xxx_hci_write_sram(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 addr, u8 *data, u32 size)$/;"	f	file:	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 addr, u8 *data, u32 size)
+ssv6xxx_hci_write_word	hci/ssv_hci.c	/^static int ssv6xxx_hci_write_word(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 addr, u32 regval)$/;"	f	file:	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci, u32 addr, u32 regval)
+ssv6xxx_hci_xmit	hci/ssv_hci.c	/^static int ssv6xxx_hci_xmit(struct ssv6xxx_hci_ctrl *hci_ctrl, struct ssv_hw_txq *hw_txq, int max_count, struct ssv6xxx_hw_resource *phw_resource)$/;"	f	file:	signature:(struct ssv6xxx_hci_ctrl *hci_ctrl, struct ssv_hw_txq *hw_txq, int max_count, struct ssv6xxx_hw_resource *phw_resource)
+ssv6xxx_high_sdio_clk	hwif/sdio/sdio.c	/^static void ssv6xxx_high_sdio_clk(struct sdio_func *func)$/;"	f	file:	signature:(struct sdio_func *func)
+ssv6xxx_high_sdio_clk	hwif/sdio/sdio.c	/^static void ssv6xxx_high_sdio_clk(struct sdio_func *func);$/;"	p	file:	signature:(struct sdio_func *func)
+ssv6xxx_host_cmd_id	include/ssv6xxx_common.h	/^} ssv6xxx_host_cmd_id;$/;"	t	typeref:enum:__anon44
+ssv6xxx_host_noa_event	include/ssv6xxx_common.h	/^} ssv6xxx_host_noa_event;$/;"	t	typeref:enum:__anon46
+ssv6xxx_host_rate_control_event	include/ssv6200_common.h	/^} ssv6xxx_host_rate_control_event;$/;"	t	typeref:enum:__anon42
+ssv6xxx_house_keeping	smac/dev.c	/^void ssv6xxx_house_keeping(unsigned long argv)$/;"	f	signature:(unsigned long argv)
+ssv6xxx_house_keeping	smac/dev.h	/^void ssv6xxx_house_keeping(unsigned long argv);$/;"	p	signature:(unsigned long argv)
+ssv6xxx_ht_report_handler	smac/ssv_ht_rc.c	/^void ssv6xxx_ht_report_handler(struct ssv_softc *sc,struct sk_buff *skb,struct ssv_sta_rc_info *rc_sta)$/;"	f	signature:(struct ssv_softc *sc,struct sk_buff *skb,struct ssv_sta_rc_info *rc_sta)
+ssv6xxx_ht_report_handler	smac/ssv_ht_rc.h	/^void ssv6xxx_ht_report_handler(struct ssv_softc *sc,struct sk_buff *skb,struct ssv_sta_rc_info *rc_sta);$/;"	p	signature:(struct ssv_softc *sc,struct sk_buff *skb,struct ssv_sta_rc_info *rc_sta)
+ssv6xxx_ht_txtime	smac/dev.c	/^u32 ssv6xxx_ht_txtime(u8 rix, int pktlen, int width,$/;"	f	signature:(u8 rix, int pktlen, int width, int half_gi, bool is_gf)
+ssv6xxx_ht_txtime	smac/dev.h	/^u32 ssv6xxx_ht_txtime(u8 rix, int pktlen, int width, int half_gi, bool is_gf);$/;"	p	signature:(u8 rix, int pktlen, int width, int half_gi, bool is_gf)
+ssv6xxx_hw_key	smac/drv_comm.h	/^struct ssv6xxx_hw_key {$/;"	s
+ssv6xxx_hw_key::key	smac/drv_comm.h	/^    u8 key[SECURITY_KEY_LEN];$/;"	m	struct:ssv6xxx_hw_key	access:public
+ssv6xxx_hw_key::rx_pn_h	smac/drv_comm.h	/^    u32 rx_pn_h;$/;"	m	struct:ssv6xxx_hw_key	access:public
+ssv6xxx_hw_key::rx_pn_l	smac/drv_comm.h	/^ u32 rx_pn_l;$/;"	m	struct:ssv6xxx_hw_key	access:public
+ssv6xxx_hw_key::tx_pn_h	smac/drv_comm.h	/^    u32 tx_pn_h;$/;"	m	struct:ssv6xxx_hw_key	access:public
+ssv6xxx_hw_key::tx_pn_l	smac/drv_comm.h	/^ u32 tx_pn_l;$/;"	m	struct:ssv6xxx_hw_key	access:public
+ssv6xxx_hw_resource	hci/hctrl.h	/^struct ssv6xxx_hw_resource$/;"	s
+ssv6xxx_hw_resource::free_tx_id	hci/hctrl.h	/^ int free_tx_id;$/;"	m	struct:ssv6xxx_hw_resource	access:public
+ssv6xxx_hw_resource::free_tx_page	hci/hctrl.h	/^ int free_tx_page;$/;"	m	struct:ssv6xxx_hw_resource	access:public
+ssv6xxx_hw_resource::max_tx_frame	hci/hctrl.h	/^ int max_tx_frame[SSV_HW_TXQ_NUM];$/;"	m	struct:ssv6xxx_hw_resource	access:public
+ssv6xxx_hw_sec	smac/drv_comm.h	/^struct ssv6xxx_hw_sec {$/;"	s
+ssv6xxx_hw_sec::group_key	smac/drv_comm.h	/^    struct ssv6xxx_hw_key group_key[3];$/;"	m	struct:ssv6xxx_hw_sec	typeref:struct:ssv6xxx_hw_sec::ssv6xxx_hw_key	access:public
+ssv6xxx_hw_sec::sta_key	smac/drv_comm.h	/^    struct ssv6xxx_hw_sta_key sta_key[8];$/;"	m	struct:ssv6xxx_hw_sec	typeref:struct:ssv6xxx_hw_sec::ssv6xxx_hw_sta_key	access:public
+ssv6xxx_hw_set_replay_ignore	smac/init.c	/^void ssv6xxx_hw_set_replay_ignore(struct ssv_hw *sh,u8 ignore)$/;"	f	signature:(struct ssv_hw *sh,u8 ignore)
+ssv6xxx_hw_sta_key	smac/drv_comm.h	/^struct ssv6xxx_hw_sta_key {$/;"	s
+ssv6xxx_hw_sta_key::group_key_idx	smac/drv_comm.h	/^ u8 group_key_idx:4;$/;"	m	struct:ssv6xxx_hw_sta_key	access:public
+ssv6xxx_hw_sta_key::pair	smac/drv_comm.h	/^ struct ssv6xxx_hw_key pair;$/;"	m	struct:ssv6xxx_hw_sta_key	typeref:struct:ssv6xxx_hw_sta_key::ssv6xxx_hw_key	access:public
+ssv6xxx_hw_sta_key::pair_key_idx	smac/drv_comm.h	/^ u8 pair_key_idx:4;$/;"	m	struct:ssv6xxx_hw_sta_key	access:public
+ssv6xxx_hw_sta_key::reserve	smac/drv_comm.h	/^ u8 reserve[2];$/;"	m	struct:ssv6xxx_hw_sta_key	access:public
+ssv6xxx_hw_sta_key::valid	smac/drv_comm.h	/^    u8 valid;$/;"	m	struct:ssv6xxx_hw_sta_key	access:public
+ssv6xxx_hwif_interface_reset	hci/hctrl.h	/^static inline void ssv6xxx_hwif_interface_reset(struct ssv6xxx_hci_ctrl *hctrl)$/;"	f	signature:(struct ssv6xxx_hci_ctrl *hctrl)
+ssv6xxx_hwif_irq_disable	hci/hctrl.h	/^static inline void ssv6xxx_hwif_irq_disable(struct ssv6xxx_hci_ctrl *hctrl)$/;"	f	signature:(struct ssv6xxx_hci_ctrl *hctrl)
+ssv6xxx_hwif_irq_enable	hci/hctrl.h	/^static inline void ssv6xxx_hwif_irq_enable(struct ssv6xxx_hci_ctrl *hctrl)$/;"	f	signature:(struct ssv6xxx_hci_ctrl *hctrl)
+ssv6xxx_hwif_irq_getstatus	hci/hctrl.h	/^static inline int ssv6xxx_hwif_irq_getstatus(struct ssv6xxx_hci_ctrl *hctrl, int *status)$/;"	f	signature:(struct ssv6xxx_hci_ctrl *hctrl, int *status)
+ssv6xxx_hwif_irq_request	hci/hctrl.h	/^static inline void ssv6xxx_hwif_irq_request(struct ssv6xxx_hci_ctrl *hctrl, irq_handler_t irq_handler)$/;"	f	signature:(struct ssv6xxx_hci_ctrl *hctrl, irq_handler_t irq_handler)
+ssv6xxx_hwif_irq_setmask	hci/hctrl.h	/^static inline void ssv6xxx_hwif_irq_setmask(struct ssv6xxx_hci_ctrl *hctrl, int mask)$/;"	f	signature:(struct ssv6xxx_hci_ctrl *hctrl, int mask)
+ssv6xxx_hwif_irq_trigger	hci/hctrl.h	/^static inline void ssv6xxx_hwif_irq_trigger(struct ssv6xxx_hci_ctrl *hctrl)$/;"	f	signature:(struct ssv6xxx_hci_ctrl *hctrl)
+ssv6xxx_hwif_jump_to_rom	hci/hctrl.h	/^static inline int ssv6xxx_hwif_jump_to_rom(struct ssv6xxx_hci_ctrl *hctrl)$/;"	f	signature:(struct ssv6xxx_hci_ctrl *hctrl)
+ssv6xxx_hwif_load_fw_post_config_device	hci/hctrl.h	/^static inline void ssv6xxx_hwif_load_fw_post_config_device(struct ssv6xxx_hci_ctrl *hctrl)$/;"	f	signature:(struct ssv6xxx_hci_ctrl *hctrl)
+ssv6xxx_hwif_load_fw_pre_config_device	hci/hctrl.h	/^static inline void ssv6xxx_hwif_load_fw_pre_config_device(struct ssv6xxx_hci_ctrl *hctrl)$/;"	f	signature:(struct ssv6xxx_hci_ctrl *hctrl)
+ssv6xxx_hwif_ops	hwif/hwif.h	/^struct ssv6xxx_hwif_ops {$/;"	s
+ssv6xxx_hwif_ops::burst_readreg	hwif/hwif.h	/^    int __must_check (*burst_readreg)(struct device *child, u32 *addr, u32 *buf, u8 reg_amount);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+ssv6xxx_hwif_ops::burst_safe_readreg	hwif/hwif.h	/^    int __must_check (*burst_safe_readreg)(struct device *child, u32 *addr, u32 *buf, u8 reg_amount);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+ssv6xxx_hwif_ops::burst_safe_writereg	hwif/hwif.h	/^    int __must_check (*burst_safe_writereg)(struct device *child, u32 *addr, u32 *buf, u8 reg_amount);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+ssv6xxx_hwif_ops::burst_writereg	hwif/hwif.h	/^    int __must_check (*burst_writereg)(struct device *child, u32 *addr, u32 *buf, u8 reg_amount);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+ssv6xxx_hwif_ops::cmd52_read	hwif/hwif.h	/^    int (*cmd52_read)(struct device *child, u32 addr, u32 *value);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+ssv6xxx_hwif_ops::cmd52_write	hwif/hwif.h	/^    int (*cmd52_write)(struct device *child, u32 addr, u32 value);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+ssv6xxx_hwif_ops::hwif_rx_task	hwif/hwif.h	/^    void (*hwif_rx_task)(struct device *child, int (*rx_cb)(struct sk_buff *rx_skb, void *args), int (*is_rx_q_full)(void *args), void *args, u32 *pkt);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+ssv6xxx_hwif_ops::hwif_rx_task	hwif/hwif.h	/^    void (*hwif_rx_task)(struct device *child, int (*rx_cb)(struct sk_buff_head *rxq, void *args), int (*is_rx_q_full)(void *args), void *args, u32 *pkt);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+ssv6xxx_hwif_ops::interface_reset	hwif/hwif.h	/^    void (*interface_reset)(struct device *child);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+ssv6xxx_hwif_ops::irq_disable	hwif/hwif.h	/^    void (*irq_disable)(struct device *child,bool iswaitirq);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+ssv6xxx_hwif_ops::irq_enable	hwif/hwif.h	/^    void (*irq_enable)(struct device *child);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+ssv6xxx_hwif_ops::irq_getmask	hwif/hwif.h	/^    int (*irq_getmask)(struct device *child, u32 *mask);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+ssv6xxx_hwif_ops::irq_getstatus	hwif/hwif.h	/^    int (*irq_getstatus)(struct device *child,int *status);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+ssv6xxx_hwif_ops::irq_request	hwif/hwif.h	/^    void (*irq_request)(struct device *child,irq_handler_t irq_handler,void *irq_dev);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+ssv6xxx_hwif_ops::irq_setmask	hwif/hwif.h	/^    void (*irq_setmask)(struct device *child,int mask);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+ssv6xxx_hwif_ops::irq_trigger	hwif/hwif.h	/^    void (*irq_trigger)(struct device *child);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+ssv6xxx_hwif_ops::is_ready	hwif/hwif.h	/^    bool (*is_ready)(struct device *child);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+ssv6xxx_hwif_ops::jump_to_rom	hwif/hwif.h	/^    int (*jump_to_rom)(struct device *child);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+ssv6xxx_hwif_ops::load_fw	hwif/hwif.h	/^    int __must_check (*load_fw)(struct device *child, u32 start_addr, u8 *data, int data_length);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+ssv6xxx_hwif_ops::load_fw_post_config_device	hwif/hwif.h	/^    void (*load_fw_post_config_device)(struct device *child);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+ssv6xxx_hwif_ops::load_fw_pre_config_device	hwif/hwif.h	/^    void (*load_fw_pre_config_device)(struct device *child);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+ssv6xxx_hwif_ops::pmu_wakeup	hwif/hwif.h	/^    void (*pmu_wakeup)(struct device *child);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+ssv6xxx_hwif_ops::property	hwif/hwif.h	/^    int (*property)(struct device *child);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+ssv6xxx_hwif_ops::read	hwif/hwif.h	/^    int __must_check (*read)(struct device *child, void *buf,size_t *size, int mode);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+ssv6xxx_hwif_ops::readreg	hwif/hwif.h	/^    int __must_check (*readreg)(struct device *child, u32 addr, u32 *buf);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+ssv6xxx_hwif_ops::rw_scatter	hwif/hwif.h	/^    int (*rw_scatter)(struct device *child, struct sdio_scatter_req *scat_req);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+ssv6xxx_hwif_ops::safe_readreg	hwif/hwif.h	/^    int __must_check (*safe_readreg)(struct device *child, u32 addr, u32 *buf);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+ssv6xxx_hwif_ops::safe_writereg	hwif/hwif.h	/^    int __must_check (*safe_writereg)(struct device *child, u32 addr, u32 buf);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+ssv6xxx_hwif_ops::start_usb_acc	hwif/hwif.h	/^    int (*start_usb_acc)(struct device *child, u8 epnum);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+ssv6xxx_hwif_ops::stop_usb_acc	hwif/hwif.h	/^    int (*stop_usb_acc)(struct device *child, u8 epnum);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+ssv6xxx_hwif_ops::support_scatter	hwif/hwif.h	/^    bool (*support_scatter)(struct device *child);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+ssv6xxx_hwif_ops::sysplf_reset	hwif/hwif.h	/^    void (*sysplf_reset)(struct device *child, u32 addr, u32 value);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+ssv6xxx_hwif_ops::trigger_tx_rx	hwif/hwif.h	/^    int (*trigger_tx_rx)(struct device *child);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+ssv6xxx_hwif_ops::write	hwif/hwif.h	/^    int __must_check (*write)(struct device *child, void *buf, size_t len,u8 queue_num);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+ssv6xxx_hwif_ops::write_sram	hwif/hwif.h	/^    int (*write_sram)(struct device *child, u32 addr, u8 *data, u32 size);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+ssv6xxx_hwif_ops::writereg	hwif/hwif.h	/^    int __must_check (*writereg)(struct device *child, u32 addr, u32 buf);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+ssv6xxx_hwif_pmu_wakeup	hci/hctrl.h	/^static inline void ssv6xxx_hwif_pmu_wakeup(struct ssv6xxx_hci_ctrl *hctrl)$/;"	f	signature:(struct ssv6xxx_hci_ctrl *hctrl)
+ssv6xxx_hwif_property	hci/hctrl.h	/^static inline int ssv6xxx_hwif_property(struct ssv6xxx_hci_ctrl *hctrl)$/;"	f	signature:(struct ssv6xxx_hci_ctrl *hctrl)
+ssv6xxx_hwif_ready	hci/hctrl.h	/^static inline bool ssv6xxx_hwif_ready(struct ssv6xxx_hci_ctrl *hctrl)$/;"	f	signature:(struct ssv6xxx_hci_ctrl *hctrl)
+ssv6xxx_hwif_rx_task	hci/hctrl.h	/^static inline void ssv6xxx_hwif_rx_task(struct ssv6xxx_hci_ctrl *hctrl, int (*rx_cb)(struct sk_buff_head *rxq, void *args),$/;"	f	signature:(struct ssv6xxx_hci_ctrl *hctrl, int (*rx_cb)(struct sk_buff_head *rxq, void *args), int (*is_rx_q_full)(void *args), void *args, u32 *pkt)
+ssv6xxx_hwif_start_usb_acc	hci/hctrl.h	/^static inline int ssv6xxx_hwif_start_usb_acc(struct ssv6xxx_hci_ctrl *hctrl, u8 epnum)$/;"	f	signature:(struct ssv6xxx_hci_ctrl *hctrl, u8 epnum)
+ssv6xxx_hwif_stop_usb_acc	hci/hctrl.h	/^static inline int ssv6xxx_hwif_stop_usb_acc(struct ssv6xxx_hci_ctrl *hctrl, u8 epnum)$/;"	f	signature:(struct ssv6xxx_hci_ctrl *hctrl, u8 epnum)
+ssv6xxx_hwif_sysplf_reset	hci/hctrl.h	/^static inline void ssv6xxx_hwif_sysplf_reset(struct ssv6xxx_hci_ctrl *hctrl, u32 addr, u32 value)$/;"	f	signature:(struct ssv6xxx_hci_ctrl *hctrl, u32 addr, u32 value)
+ssv6xxx_hwif_write_sram	hci/hctrl.h	/^static inline int ssv6xxx_hwif_write_sram(struct ssv6xxx_hci_ctrl *hctrl, u32 addr, u8 *data, u32 size)$/;"	f	signature:(struct ssv6xxx_hci_ctrl *hctrl, u32 addr, u8 *data, u32 size)
+ssv6xxx_id_table	smac/init.c	/^static const struct platform_device_id ssv6xxx_id_table[] = {$/;"	v	typeref:struct:platform_device_id	file:
+ssv6xxx_iface_combinations_p2p	smac/init.c	/^ssv6xxx_iface_combinations_p2p[] = {$/;"	v	typeref:struct:ieee80211_iface_combination	file:
+ssv6xxx_inc_bit_idx	smac/ampdu.c	/^bool ssv6xxx_inc_bit_idx (struct ssv_softc *sc, u32 ssn_1st, u32 ssn_next,$/;"	f	signature:(struct ssv_softc *sc, u32 ssn_1st, u32 ssn_next, u32 *word_idx, u32 *bit_idx)
+ssv6xxx_inc_bit_idx	smac/dev.h	/^bool ssv6xxx_inc_bit_idx (struct ssv_softc *sc, u32 ssn_1st, u32 ssn_next, u32 *word_idx,$/;"	p	signature:(struct ssv_softc *sc, u32 ssn_1st, u32 ssn_next, u32 *word_idx, u32 *bit_idx)
+ssv6xxx_init	smac/init.c	/^EXPORT_SYMBOL(ssv6xxx_init);$/;"	v
+ssv6xxx_init	smac/init.c	/^int ssv6xxx_init(void)$/;"	f	signature:(void)
+ssv6xxx_init	smac/init.c	/^module_init(ssv6xxx_init);$/;"	v
+ssv6xxx_init	smac/init.h	/^int ssv6xxx_init(void);$/;"	p	signature:(void)
+ssv6xxx_init_ch_cfg	smac/hal/hal.c	/^static void ssv6xxx_init_ch_cfg(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6xxx_init_debugfs	smac/ssv6xxx_debugfs.c	/^int ssv6xxx_init_debugfs (struct ssv_softc *sc, const char *name)$/;"	f	signature:(struct ssv_softc *sc, const char *name)
+ssv6xxx_init_debugfs	smac/ssv6xxx_debugfs.h	/^int ssv6xxx_init_debugfs (struct ssv_softc *sc, const char *name);$/;"	p	signature:(struct ssv_softc *sc, const char *name)
+ssv6xxx_init_device	smac/init.c	/^static int ssv6xxx_init_device(struct ssv_softc *sc, const char *name)$/;"	f	file:	signature:(struct ssv_softc *sc, const char *name)
+ssv6xxx_init_gpio_cfg	smac/hal/hal.c	/^static void ssv6xxx_init_gpio_cfg(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6xxx_init_hal	include/hal.h	/^int ssv6xxx_init_hal(struct ssv_softc *sc);$/;"	p	signature:(struct ssv_softc *sc)
+ssv6xxx_init_hal	smac/hal/hal.c	/^int ssv6xxx_init_hal(struct ssv_softc *sc)$/;"	f	signature:(struct ssv_softc *sc)
+ssv6xxx_init_hw	smac/init.c	/^static int ssv6xxx_init_hw(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6xxx_init_iqk	smac/dev.c	/^void ssv6xxx_init_iqk(struct ssv_hw *sh)$/;"	f	signature:(struct ssv_hw *sh)
+ssv6xxx_init_iqk	smac/dev.h	/^void ssv6xxx_init_iqk(struct ssv_hw *sh);$/;"	p	signature:(struct ssv_hw *sh)
+ssv6xxx_init_iqk	smac/hal/hal.c	/^static void ssv6xxx_init_iqk(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6xxx_init_list_node	include/ssv_data_struct.h	/^static inline void ssv6xxx_init_list_node(struct ssv6xxx_list_node *node) {$/;"	f	signature:(struct ssv6xxx_list_node *node)
+ssv6xxx_init_mac	smac/init.c	/^int ssv6xxx_init_mac(struct ssv_hw *sh)$/;"	f	signature:(struct ssv_hw *sh)
+ssv6xxx_init_mac	smac/init.h	/^int ssv6xxx_init_mac(struct ssv_hw *sh);$/;"	p	signature:(struct ssv_hw *sh)
+ssv6xxx_init_queue	include/ssv_data_struct.h	/^static inline void ssv6xxx_init_queue(struct ssv6xxx_queue *ssv_queue) {$/;"	f	signature:(struct ssv6xxx_queue *ssv_queue)
+ssv6xxx_init_softc	smac/init.c	/^static int ssv6xxx_init_softc(struct ssv_softc *sc)$/;"	f	file:	signature:(struct ssv_softc *sc)
+ssv6xxx_iqk_cfg	include/ssv6xxx_common.h	/^struct ssv6xxx_iqk_cfg {$/;"	s
+ssv6xxx_iqk_cfg::__anon47::argv	include/ssv6xxx_common.h	/^        u32 argv;$/;"	m	union:ssv6xxx_iqk_cfg::__anon47	access:public
+ssv6xxx_iqk_cfg::__anon47::fx_sel	include/ssv6xxx_common.h	/^        u32 fx_sel;$/;"	m	union:ssv6xxx_iqk_cfg::__anon47	access:public
+ssv6xxx_iqk_cfg::cfg_def_tx_scale_11b	include/ssv6xxx_common.h	/^    u32 cfg_def_tx_scale_11b :8;$/;"	m	struct:ssv6xxx_iqk_cfg	access:public
+ssv6xxx_iqk_cfg::cfg_def_tx_scale_11b_p0d5	include/ssv6xxx_common.h	/^    u32 cfg_def_tx_scale_11b_p0d5 :8;$/;"	m	struct:ssv6xxx_iqk_cfg	access:public
+ssv6xxx_iqk_cfg::cfg_def_tx_scale_11g	include/ssv6xxx_common.h	/^    u32 cfg_def_tx_scale_11g :8;$/;"	m	struct:ssv6xxx_iqk_cfg	access:public
+ssv6xxx_iqk_cfg::cfg_def_tx_scale_11g_p0d5	include/ssv6xxx_common.h	/^    u32 cfg_def_tx_scale_11g_p0d5 :8;$/;"	m	struct:ssv6xxx_iqk_cfg	access:public
+ssv6xxx_iqk_cfg::cfg_pa	include/ssv6xxx_common.h	/^    u32 cfg_pa :8;$/;"	m	struct:ssv6xxx_iqk_cfg	access:public
+ssv6xxx_iqk_cfg::cfg_pabias_ctrl	include/ssv6xxx_common.h	/^    u32 cfg_pabias_ctrl :8;$/;"	m	struct:ssv6xxx_iqk_cfg	access:public
+ssv6xxx_iqk_cfg::cfg_pacascode_ctrl	include/ssv6xxx_common.h	/^    u32 cfg_pacascode_ctrl :8;$/;"	m	struct:ssv6xxx_iqk_cfg	access:public
+ssv6xxx_iqk_cfg::cfg_tssi_div	include/ssv6xxx_common.h	/^    u32 cfg_tssi_div :8;$/;"	m	struct:ssv6xxx_iqk_cfg	access:public
+ssv6xxx_iqk_cfg::cfg_tssi_trgt	include/ssv6xxx_common.h	/^    u32 cfg_tssi_trgt :8;$/;"	m	struct:ssv6xxx_iqk_cfg	access:public
+ssv6xxx_iqk_cfg::cfg_xtal	include/ssv6xxx_common.h	/^    u32 cfg_xtal :8;$/;"	m	struct:ssv6xxx_iqk_cfg	access:public
+ssv6xxx_iqk_cfg::cmd_sel	include/ssv6xxx_common.h	/^    u32 cmd_sel;$/;"	m	struct:ssv6xxx_iqk_cfg	access:public
+ssv6xxx_iqk_cfg::phy_tbl_size	include/ssv6xxx_common.h	/^    u32 phy_tbl_size;$/;"	m	struct:ssv6xxx_iqk_cfg	access:public
+ssv6xxx_iqk_cfg::rf_tbl_size	include/ssv6xxx_common.h	/^    u32 rf_tbl_size;$/;"	m	struct:ssv6xxx_iqk_cfg	access:public
+ssv6xxx_iqk_cfg_pa	include/ssv6xxx_common.h	/^} ssv6xxx_iqk_cfg_pa;$/;"	t	typeref:enum:__anon51
+ssv6xxx_iqk_cfg_xtal	include/ssv6xxx_common.h	/^} ssv6xxx_iqk_cfg_xtal;$/;"	t	typeref:enum:__anon50
+ssv6xxx_iqk_cmd_sel	include/ssv6xxx_common.h	/^} ssv6xxx_iqk_cmd_sel;$/;"	t	typeref:enum:__anon52
+ssv6xxx_is_ampdu_rx_sta	smac/dev.c	/^static bool ssv6xxx_is_ampdu_rx_sta(struct ssv_softc *sc, struct ieee80211_sta *sta)$/;"	f	file:	signature:(struct ssv_softc *sc, struct ieee80211_sta *sta)
+ssv6xxx_is_ready	hwif/sdio/sdio.c	/^static bool ssv6xxx_is_ready (struct device *child)$/;"	f	file:	signature:(struct device *child)
+ssv6xxx_isr_mib_reset	hci/ssv_hci.c	/^static void ssv6xxx_isr_mib_reset (struct ssv6xxx_hci_ctrl *ctrl_hci)$/;"	f	file:	signature:(struct ssv6xxx_hci_ctrl *ctrl_hci)
+ssv6xxx_jump_to_rom	smac/dev.c	/^void ssv6xxx_jump_to_rom(void *param)$/;"	f	signature:(void *param)
+ssv6xxx_jump_to_rom	smac/dev.h	/^void ssv6xxx_jump_to_rom(void *param);$/;"	p	signature:(void *param)
+ssv6xxx_late_resume	smac/dev.h	/^void ssv6xxx_late_resume(struct early_suspend *h);$/;"	p	signature:(struct early_suspend *h)
+ssv6xxx_late_resume	smac/ssv_pm.c	/^void ssv6xxx_late_resume(struct early_suspend *h)$/;"	f	signature:(struct early_suspend *h)
+ssv6xxx_late_resume	smac/ssv_pm.h	/^void ssv6xxx_late_resume(struct early_suspend *h);$/;"	p	signature:(struct early_suspend *h)
+ssv6xxx_late_resume	smac/ssv_pm.h	/^void ssv6xxx_late_resume(void);$/;"	p	signature:(void)
+ssv6xxx_legacy_report_handler	smac/ssv_rc.c	/^void ssv6xxx_legacy_report_handler(struct ssv_softc *sc,struct sk_buff *skb,struct ssv_sta_rc_info *rc_sta)$/;"	f	signature:(struct ssv_softc *sc,struct sk_buff *skb,struct ssv_sta_rc_info *rc_sta)
+ssv6xxx_legacy_report_handler	smac/ssv_rc.h	/^void ssv6xxx_legacy_report_handler(struct ssv_softc *sc,struct sk_buff *skb,struct ssv_sta_rc_info *rc_sta);$/;"	p	signature:(struct ssv_softc *sc,struct sk_buff *skb,struct ssv_sta_rc_info *rc_sta)
+ssv6xxx_list_mib	ssvdevice/ssv_cmd.c	/^static void ssv6xxx_list_mib(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6xxx_list_node	include/ssv_data_struct.h	/^struct ssv6xxx_list_node {$/;"	s
+ssv6xxx_list_node::list	include/ssv_data_struct.h	/^    struct list_head list;$/;"	m	struct:ssv6xxx_list_node	typeref:struct:ssv6xxx_list_node::list_head	access:public
+ssv6xxx_load_firmware	smac/init.c	/^int ssv6xxx_load_firmware(struct ssv_hw *sh)$/;"	f	signature:(struct ssv_hw *sh)
+ssv6xxx_low_sdio_clk	hwif/sdio/sdio.c	/^static void ssv6xxx_low_sdio_clk(struct sdio_func *func)$/;"	f	file:	signature:(struct sdio_func *func)
+ssv6xxx_low_sdio_clk	hwif/sdio/sdio.c	/^static void ssv6xxx_low_sdio_clk(struct sdio_func *func);$/;"	p	file:	signature:(struct sdio_func *func)
+ssv6xxx_mark_skb_retry	smac/ampdu.c	/^void ssv6xxx_mark_skb_retry (struct ssv_softc *sc, struct SKB_info_st *skb_info, struct sk_buff *skb)$/;"	f	signature:(struct ssv_softc *sc, struct SKB_info_st *skb_info, struct sk_buff *skb)
+ssv6xxx_mark_skb_retry	smac/ampdu.c	/^void ssv6xxx_mark_skb_retry (struct ssv_softc *sc, struct SKB_info_st *skb_info,$/;"	p	file:	signature:(struct ssv_softc *sc, struct SKB_info_st *skb_info, struct sk_buff *skb)
+ssv6xxx_mark_skb_retry	smac/dev.h	/^void ssv6xxx_mark_skb_retry (struct ssv_softc *sc, struct SKB_info_st *skb_info, struct sk_buff *skb);$/;"	p	signature:(struct ssv_softc *sc, struct SKB_info_st *skb_info, struct sk_buff *skb)
+ssv6xxx_mcu_input_full	smac/dev.c	/^static inline bool ssv6xxx_mcu_input_full(struct ssv_softc *sc)$/;"	f	file:	signature:(struct ssv_softc *sc)
+ssv6xxx_mib_dump	smac/ampdu.h	/^ssize_t ssv6xxx_mib_dump (struct ieee80211_hw *hw, char *mib_str, ssize_t length);$/;"	p	signature:(struct ieee80211_hw *hw, char *mib_str, ssize_t length)
+ssv6xxx_mib_edca_process	smac/dev.c	/^void ssv6xxx_mib_edca_process(struct work_struct *work)$/;"	f	signature:(struct work_struct *work)
+ssv6xxx_mib_edca_process	smac/dev.h	/^void ssv6xxx_mib_edca_process(struct work_struct *work);$/;"	p	signature:(struct work_struct *work)
+ssv6xxx_mib_reset	smac/ampdu.h	/^void ssv6xxx_mib_reset (struct ieee80211_hw *hw);$/;"	p	signature:(struct ieee80211_hw *hw)
+ssv6xxx_minstrel_rate_control_register	smac/ssv_rc_minstrel.c	/^int ssv6xxx_minstrel_rate_control_register(void)$/;"	f	signature:(void)
+ssv6xxx_minstrel_rate_control_register	smac/ssv_rc_minstrel.h	/^int ssv6xxx_minstrel_rate_control_register(void);$/;"	p	signature:(void)
+ssv6xxx_minstrel_rate_control_unregister	smac/ssv_rc_minstrel.c	/^void ssv6xxx_minstrel_rate_control_unregister(void)$/;"	f	signature:(void)
+ssv6xxx_minstrel_rate_control_unregister	smac/ssv_rc_minstrel.h	/^void ssv6xxx_minstrel_rate_control_unregister(void);$/;"	p	signature:(void)
+ssv6xxx_noa_conf	smac/p2p.h	/^enum ssv6xxx_noa_conf {$/;"	g
+ssv6xxx_noa_detect	smac/p2p.c	/^void ssv6xxx_noa_detect(struct ssv_softc *sc, struct ieee80211_hdr * hdr, u32 len){$/;"	f	signature:(struct ssv_softc *sc, struct ieee80211_hdr * hdr, u32 len)
+ssv6xxx_noa_detect	smac/p2p.h	/^void ssv6xxx_noa_detect(struct ssv_softc *sc, struct ieee80211_hdr * hdr, u32 len);$/;"	p	signature:(struct ssv_softc *sc, struct ieee80211_hdr * hdr, u32 len)
+ssv6xxx_noa_hdl_bss_change	smac/p2p.c	/^void ssv6xxx_noa_hdl_bss_change(struct ssv_softc *sc, enum ssv6xxx_noa_conf conf, u8 vif_idx){$/;"	f	signature:(struct ssv_softc *sc, enum ssv6xxx_noa_conf conf, u8 vif_idx)
+ssv6xxx_noa_hdl_bss_change	smac/p2p.h	/^void ssv6xxx_noa_hdl_bss_change(struct ssv_softc *sc, enum ssv6xxx_noa_conf conf, u8 vif_idx);$/;"	p	signature:(struct ssv_softc *sc, enum ssv6xxx_noa_conf conf, u8 vif_idx)
+ssv6xxx_noa_host_stop_noa	smac/p2p.c	/^void ssv6xxx_noa_host_stop_noa(struct ssv_softc *sc, u8 vif_id){$/;"	f	signature:(struct ssv_softc *sc, u8 vif_id)
+ssv6xxx_noa_reset	smac/p2p.c	/^void ssv6xxx_noa_reset(struct ssv_softc *sc){$/;"	f	signature:(struct ssv_softc *sc)
+ssv6xxx_noa_reset	smac/p2p.h	/^void ssv6xxx_noa_reset(struct ssv_softc *sc);$/;"	p	signature:(struct ssv_softc *sc)
+ssv6xxx_non_ht_txtime	smac/dev.c	/^u32 ssv6xxx_non_ht_txtime(u8 phy, int kbps,$/;"	f	signature:(u8 phy, int kbps, u32 frameLen, bool shortPreamble)
+ssv6xxx_non_ht_txtime	smac/dev.h	/^u32 ssv6xxx_non_ht_txtime(u8 phy, int kbps, u32 frameLen, bool shortPreamble);$/;"	p	signature:(u8 phy, int kbps, u32 frameLen, bool shortPreamble)
+ssv6xxx_none_func	smac/dev.c	/^void ssv6xxx_none_func(struct ssv_softc *sc)$/;"	f	signature:(struct ssv_softc *sc)
+ssv6xxx_nullfun_frame_filter	smac/dev.c	/^bool ssv6xxx_nullfun_frame_filter(struct ssv_hw *sh, struct sk_buff *skb)$/;"	f	signature:(struct ssv_hw *sh, struct sk_buff *skb)
+ssv6xxx_nullfun_frame_filter	smac/dev.h	/^bool ssv6xxx_nullfun_frame_filter(struct ssv_hw *sh, struct sk_buff *skb);$/;"	p	signature:(struct ssv_hw *sh, struct sk_buff *skb)
+ssv6xxx_p2p_fops	ssvdevice/ssvdevice.c	/^static struct file_operations ssv6xxx_p2p_fops = {$/;"	v	typeref:struct:file_operations	file:
+ssv6xxx_p2p_limits	smac/init.c	/^static const struct ieee80211_iface_limit ssv6xxx_p2p_limits[] = {$/;"	v	typeref:struct:ieee80211_iface_limit	file:
+ssv6xxx_p2p_noa_attribute	smac/p2p.c	/^struct ssv6xxx_p2p_noa_attribute {$/;"	s	file:
+ssv6xxx_p2p_noa_attribute::ctwindows_oppps	smac/p2p.c	/^    u16 ctwindows_oppps;$/;"	m	struct:ssv6xxx_p2p_noa_attribute	file:	access:public
+ssv6xxx_p2p_noa_attribute::index	smac/p2p.c	/^    u8 index;$/;"	m	struct:ssv6xxx_p2p_noa_attribute	file:	access:public
+ssv6xxx_p2p_noa_attribute::noa_param	smac/p2p.c	/^    struct ssv6xxx_p2p_noa_param noa_param;$/;"	m	struct:ssv6xxx_p2p_noa_attribute	typeref:struct:ssv6xxx_p2p_noa_attribute::ssv6xxx_p2p_noa_param	file:	access:public
+ssv6xxx_p2p_open	ssvdevice/ssvdevice.c	/^static int ssv6xxx_p2p_open(struct inode *inode, struct file *filp)$/;"	f	file:	signature:(struct inode *inode, struct file *filp)
+ssv6xxx_p2p_read	ssvdevice/ssvdevice.c	/^static ssize_t ssv6xxx_p2p_read(struct file *filp, char __user *buffer,$/;"	f	file:	signature:(struct file *filp, char __user *buffer, size_t count, loff_t *ppos)
+ssv6xxx_p2p_write	ssvdevice/ssvdevice.c	/^static ssize_t ssv6xxx_p2p_write(struct file *filp, const char __user *buffer,$/;"	f	file:	signature:(struct file *filp, const char __user *buffer, size_t count, loff_t *ppos)
+ssv6xxx_pairwise_wpa_use_hw_cipher	smac/dev.c	/^static bool ssv6xxx_pairwise_wpa_use_hw_cipher(struct ssv_softc *sc,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv, enum SSV_CIPHER_E cipher, struct ssv_sta_priv_data *sta_priv)
+ssv6xxx_payload	hwif/usb/usb.h	/^union ssv6xxx_payload {$/;"	u
+ssv6xxx_payload::rreg	hwif/usb/usb.h	/^ struct ssv6xxx_read_reg rreg;$/;"	m	union:ssv6xxx_payload	typeref:struct:ssv6xxx_payload::ssv6xxx_read_reg	access:public
+ssv6xxx_payload::rreg_res	hwif/usb/usb.h	/^ struct ssv6xxx_read_reg_result rreg_res;$/;"	m	union:ssv6xxx_payload	typeref:struct:ssv6xxx_payload::ssv6xxx_read_reg_result	access:public
+ssv6xxx_payload::wreg	hwif/usb/usb.h	/^ struct ssv6xxx_write_reg wreg;$/;"	m	union:ssv6xxx_payload	typeref:struct:ssv6xxx_payload::ssv6xxx_write_reg	access:public
+ssv6xxx_pbuf_alloc	smac/dev.c	/^u32 ssv6xxx_pbuf_alloc(struct ssv_softc *sc, int size, int type)$/;"	f	signature:(struct ssv_softc *sc, int size, int type)
+ssv6xxx_pbuf_alloc	smac/dev.h	/^u32 ssv6xxx_pbuf_alloc(struct ssv_softc *sc, int size, int type);$/;"	p	signature:(struct ssv_softc *sc, int size, int type)
+ssv6xxx_pbuf_free	smac/dev.c	/^bool ssv6xxx_pbuf_free(struct ssv_softc *sc, u32 pbuf_addr)$/;"	f	signature:(struct ssv_softc *sc, u32 pbuf_addr)
+ssv6xxx_pbuf_free	smac/dev.h	/^bool ssv6xxx_pbuf_free(struct ssv_softc *sc, u32 pbuf_addr);$/;"	p	signature:(struct ssv_softc *sc, u32 pbuf_addr)
+ssv6xxx_peek_next_pkt_len	smac/dev.c	/^int ssv6xxx_peek_next_pkt_len(struct sk_buff *skb, void *param)$/;"	f	signature:(struct sk_buff *skb, void *param)
+ssv6xxx_peek_next_pkt_len	smac/dev.h	/^int ssv6xxx_peek_next_pkt_len(struct sk_buff *skb, void *param);$/;"	p	signature:(struct sk_buff *skb, void *param)
+ssv6xxx_phy_enable	smac/dev.c	/^void ssv6xxx_phy_enable(struct ssv_hw *sh, bool val)$/;"	f	signature:(struct ssv_hw *sh, bool val)
+ssv6xxx_phy_enable	smac/dev.h	/^void ssv6xxx_phy_enable(struct ssv_hw *sh, bool enable);$/;"	p	signature:(struct ssv_hw *sh, bool enable)
+ssv6xxx_pid_rate_control_register	smac/ssv_rc.c	/^int ssv6xxx_pid_rate_control_register(void)$/;"	f	signature:(void)
+ssv6xxx_pid_rate_control_register	smac/ssv_rc.h	/^int ssv6xxx_pid_rate_control_register(void);$/;"	p	signature:(void)
+ssv6xxx_pid_rate_control_unregister	smac/ssv_rc.c	/^void ssv6xxx_pid_rate_control_unregister(void)$/;"	f	signature:(void)
+ssv6xxx_pid_rate_control_unregister	smac/ssv_rc.h	/^void ssv6xxx_pid_rate_control_unregister(void);$/;"	p	signature:(void)
+ssv6xxx_platform_data	hwif/hwif.h	/^struct ssv6xxx_platform_data {$/;"	s
+ssv6xxx_platform_data::chip_id	hwif/hwif.h	/^    u8 chip_id[SSV6XXX_CHIP_ID_LENGTH];$/;"	m	struct:ssv6xxx_platform_data	access:public
+ssv6xxx_platform_data::dbg_control	hwif/hwif.h	/^ bool dbg_control;$/;"	m	struct:ssv6xxx_platform_data	access:public
+ssv6xxx_platform_data::device	hwif/hwif.h	/^    unsigned short device;$/;"	m	struct:ssv6xxx_platform_data	access:public
+ssv6xxx_platform_data::disable_usb_acc	hwif/hwif.h	/^    void (*disable_usb_acc)(void *param, u8 epnum);$/;"	m	struct:ssv6xxx_platform_data	access:public
+ssv6xxx_platform_data::enable_usb_acc	hwif/hwif.h	/^    void (*enable_usb_acc)(void *param, u8 epnum);$/;"	m	struct:ssv6xxx_platform_data	access:public
+ssv6xxx_platform_data::irq_handling	hwif/hwif.h	/^    atomic_t irq_handling;$/;"	m	struct:ssv6xxx_platform_data	access:public
+ssv6xxx_platform_data::is_enabled	hwif/hwif.h	/^    bool is_enabled;$/;"	m	struct:ssv6xxx_platform_data	access:public
+ssv6xxx_platform_data::jump_to_rom	hwif/hwif.h	/^    void (*jump_to_rom)(void *param);$/;"	m	struct:ssv6xxx_platform_data	access:public
+ssv6xxx_platform_data::ops	hwif/hwif.h	/^    struct ssv6xxx_hwif_ops *ops;$/;"	m	struct:ssv6xxx_platform_data	typeref:struct:ssv6xxx_platform_data::ssv6xxx_hwif_ops	access:public
+ssv6xxx_platform_data::pm_param	hwif/hwif.h	/^ void *pm_param;$/;"	m	struct:ssv6xxx_platform_data	access:public
+ssv6xxx_platform_data::resume	hwif/hwif.h	/^ void (*resume)(void *param);$/;"	m	struct:ssv6xxx_platform_data	access:public
+ssv6xxx_platform_data::rx_burstread_param	hwif/hwif.h	/^    void *rx_burstread_param;$/;"	m	struct:ssv6xxx_platform_data	access:public
+ssv6xxx_platform_data::rx_burstread_size	hwif/hwif.h	/^    int (*rx_burstread_size)(void *param);$/;"	m	struct:ssv6xxx_platform_data	access:public
+ssv6xxx_platform_data::short_chip_id	hwif/hwif.h	/^    u8 short_chip_id[SSV6XXX_CHIP_ID_SHORT_LENGTH+1];$/;"	m	struct:ssv6xxx_platform_data	access:public
+ssv6xxx_platform_data::skb_alloc	hwif/hwif.h	/^    struct sk_buff *(*skb_alloc) (void *param, s32 len, gfp_t gfp_mask);$/;"	m	struct:ssv6xxx_platform_data	typeref:struct:ssv6xxx_platform_data::skb_alloc	access:public
+ssv6xxx_platform_data::skb_free	hwif/hwif.h	/^    void (*skb_free) (void *param, struct sk_buff *skb);$/;"	m	struct:ssv6xxx_platform_data	access:public
+ssv6xxx_platform_data::skb_param	hwif/hwif.h	/^    void *skb_param;$/;"	m	struct:ssv6xxx_platform_data	access:public
+ssv6xxx_platform_data::suspend	hwif/hwif.h	/^ void (*suspend)(void *param);$/;"	m	struct:ssv6xxx_platform_data	access:public
+ssv6xxx_platform_data::usb_param	hwif/hwif.h	/^    void *usb_param;$/;"	m	struct:ssv6xxx_platform_data	access:public
+ssv6xxx_platform_data::vendor	hwif/hwif.h	/^    unsigned short vendor;$/;"	m	struct:ssv6xxx_platform_data	access:public
+ssv6xxx_pll_chk	smac/dev.c	/^void ssv6xxx_pll_chk(struct ssv_hw *sh);$/;"	p	file:	signature:(struct ssv_hw *sh)
+ssv6xxx_pll_chk	smac/dev.h	/^void ssv6xxx_pll_chk(struct ssv_hw *sh);$/;"	p	signature:(struct ssv_hw *sh)
+ssv6xxx_pll_chk	smac/hal/hal.c	/^static void ssv6xxx_pll_chk(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6xxx_pmu_awake	smac/dev.c	/^void ssv6xxx_pmu_awake(struct ssv_softc *sc)$/;"	f	signature:(struct ssv_softc *sc)
+ssv6xxx_pmu_awake	smac/dev.h	/^void ssv6xxx_pmu_awake(struct ssv_softc *sc);$/;"	p	signature:(struct ssv_softc *sc)
+ssv6xxx_post_tx_cb	smac/dev.c	/^void ssv6xxx_post_tx_cb(struct sk_buff_head *skb_head, void *args)$/;"	f	signature:(struct sk_buff_head *skb_head, void *args)
+ssv6xxx_post_tx_cb	smac/dev.h	/^void ssv6xxx_post_tx_cb(struct sk_buff_head *skb_head, void *args);$/;"	p	signature:(struct sk_buff_head *skb_head, void *args)
+ssv6xxx_power_awake	smac/dev.c	/^void ssv6xxx_power_awake(void *param)$/;"	f	signature:(void *param)
+ssv6xxx_power_awake	smac/dev.h	/^void ssv6xxx_power_awake(void *param);$/;"	p	signature:(void *param)
+ssv6xxx_power_sleep	smac/dev.c	/^void ssv6xxx_power_sleep(void *param)$/;"	f	signature:(void *param)
+ssv6xxx_power_sleep	smac/dev.h	/^void ssv6xxx_power_sleep(void *param);$/;"	p	signature:(void *param)
+ssv6xxx_pre_tx_cb	smac/dev.c	/^void ssv6xxx_pre_tx_cb(struct sk_buff *skb, void *args)$/;"	f	signature:(struct sk_buff *skb, void *args)
+ssv6xxx_pre_tx_cb	smac/dev.h	/^void ssv6xxx_pre_tx_cb(struct sk_buff *skb, void *args);$/;"	p	signature:(struct sk_buff *skb, void *args)
+ssv6xxx_preload_sw_cipher	smac/init.c	/^static void ssv6xxx_preload_sw_cipher(void)$/;"	f	file:	signature:(void)
+ssv6xxx_process_noa_event	smac/p2p.c	/^void ssv6xxx_process_noa_event(struct ssv_softc *sc, struct sk_buff *skb)$/;"	f	signature:(struct ssv_softc *sc, struct sk_buff *skb)
+ssv6xxx_process_noa_event	smac/p2p.h	/^void ssv6xxx_process_noa_event(struct ssv_softc *sc, struct sk_buff *skb);$/;"	p	signature:(struct ssv_softc *sc, struct sk_buff *skb)
+ssv6xxx_process_rx_lpbk_ptk	smac/dev.c	/^static void ssv6xxx_process_rx_lpbk_ptk(struct ssv_softc *sc, struct sk_buff *skb)$/;"	f	file:	signature:(struct ssv_softc *sc, struct sk_buff *skb)
+ssv6xxx_process_si_event	smac/kssvsmart.c	/^EXPORT_SYMBOL(ssv6xxx_process_si_event);$/;"	v
+ssv6xxx_process_si_event	smac/kssvsmart.c	/^void ssv6xxx_process_si_event(struct ssv_softc *sc, struct sk_buff *skb)$/;"	f	signature:(struct ssv_softc *sc, struct sk_buff *skb)
+ssv6xxx_process_si_event	smac/kssvsmart.h	/^void ssv6xxx_process_si_event(struct ssv_softc *sc, struct sk_buff *skb);$/;"	p	signature:(struct ssv_softc *sc, struct sk_buff *skb)
+ssv6xxx_ps_callback_func	smac/dev.h	/^void ssv6xxx_ps_callback_func(unsigned long data);$/;"	p	signature:(unsigned long data)
+ssv6xxx_push_log_to_circbuf	smac/dev.c	/^static int ssv6xxx_push_log_to_circbuf(struct ssv_dbg_log *dbg_log, const char *src, unsigned int len)$/;"	f	file:	signature:(struct ssv_dbg_log *dbg_log, const char *src, unsigned int len)
+ssv6xxx_queue	include/ssv_data_struct.h	/^struct ssv6xxx_queue {$/;"	s
+ssv6xxx_queue::lock	include/ssv_data_struct.h	/^    spinlock_t lock;$/;"	m	struct:ssv6xxx_queue	access:public
+ssv6xxx_queue::queue	include/ssv_data_struct.h	/^    struct list_head queue;$/;"	m	struct:ssv6xxx_queue	typeref:struct:ssv6xxx_queue::list_head	access:public
+ssv6xxx_rate_alloc	smac/ssv_rc.c	/^static void *ssv6xxx_rate_alloc(struct ieee80211_hw *hw, struct dentry *debugfsdir)$/;"	f	file:	signature:(struct ieee80211_hw *hw, struct dentry *debugfsdir)
+ssv6xxx_rate_alloc_sta	smac/ssv_rc.c	/^static void *ssv6xxx_rate_alloc_sta(void *priv, struct ieee80211_sta *sta, gfp_t gfp)$/;"	f	file:	signature:(void *priv, struct ieee80211_sta *sta, gfp_t gfp)
+ssv6xxx_rate_control_register	smac/init.c	/^int ssv6xxx_rate_control_register(void)$/;"	f	signature:(void)
+ssv6xxx_rate_control_unregister	smac/init.c	/^void ssv6xxx_rate_control_unregister(void)$/;"	f	signature:(void)
+ssv6xxx_rate_free	smac/ssv_rc.c	/^static void ssv6xxx_rate_free(void *priv)$/;"	f	file:	signature:(void *priv)
+ssv6xxx_rate_free_sta	smac/ssv_rc.c	/^static void ssv6xxx_rate_free_sta(void *priv, struct ieee80211_sta *sta,$/;"	f	file:	signature:(void *priv, struct ieee80211_sta *sta, void *priv_sta)
+ssv6xxx_rate_highest_index	smac/ssv_rc.c	/^static u8 ssv6xxx_rate_highest_index(struct ssv_sta_rc_info *rc_sta)$/;"	f	file:	signature:(struct ssv_sta_rc_info *rc_sta)
+ssv6xxx_rate_init	smac/ssv_rc.c	/^static void ssv6xxx_rate_init(void *priv, struct ieee80211_supported_band *sband,$/;"	f	file:	signature:(void *priv, struct ieee80211_supported_band *sband, struct cfg80211_chan_def *chandef, struct ieee80211_sta *sta, void *priv_sta)
+ssv6xxx_rate_lowest_index	smac/ssv_rc.c	/^static u8 ssv6xxx_rate_lowest_index(struct ssv_sta_rc_info *rc_sta)$/;"	f	file:	signature:(struct ssv_sta_rc_info *rc_sta)
+ssv6xxx_rate_supported	smac/ssv_rc.c	/^static u32 ssv6xxx_rate_supported(struct ssv_sta_rc_info *rc_sta, u32 index)$/;"	f	file:	signature:(struct ssv_sta_rc_info *rc_sta, u32 index)
+ssv6xxx_rate_update	smac/ssv_rc.c	/^static void ssv6xxx_rate_update(void *priv, struct ieee80211_supported_band *sband,$/;"	f	file:	signature:(void *priv, struct ieee80211_supported_band *sband, struct cfg80211_chan_def *chandef, struct ieee80211_sta *sta, void *priv_sta, u32 changed)
+ssv6xxx_rate_update_minstrel_type	smac/ssv_rc_minstrel.c	/^static void ssv6xxx_rate_update_minstrel_type(void *priv, struct ieee80211_supported_band *sband,$/;"	f	file:	signature:(void *priv, struct ieee80211_supported_band *sband, struct ieee80211_sta *sta, void *priv_sta, enum nl80211_channel_type oper_chan_type)
+ssv6xxx_rate_update_rc_type	smac/ssv_rc.c	/^static void ssv6xxx_rate_update_rc_type(void *priv, struct ieee80211_supported_band *sband,$/;"	f	file:	signature:(void *priv, struct ieee80211_supported_band *sband, struct ieee80211_sta *sta, void *priv_sta)
+ssv6xxx_rc_algorithm	smac/dev.h	/^void ssv6xxx_rc_algorithm(struct ssv_softc *sc);$/;"	p	signature:(struct ssv_softc *sc)
+ssv6xxx_rc_algorithm	smac/init.c	/^void ssv6xxx_rc_algorithm(struct ssv_softc *sc)$/;"	f	signature:(struct ssv_softc *sc)
+ssv6xxx_rc_get_rate	smac/ssv_rc.h	/^struct ssv_rc_rate *ssv6xxx_rc_get_rate(int rc_index);$/;"	p	signature:(int rc_index)
+ssv6xxx_rc_hw_rate_idx	smac/ssv_rc.c	/^void ssv6xxx_rc_hw_rate_idx(struct ssv_softc *sc,$/;"	f	signature:(struct ssv_softc *sc, struct ieee80211_tx_info *info, struct ssv_rate_info *sr)
+ssv6xxx_rc_hw_rate_idx	smac/ssv_rc.h	/^void ssv6xxx_rc_hw_rate_idx(struct ssv_softc *sc,$/;"	p	signature:(struct ssv_softc *sc, struct ieee80211_tx_info *info, struct ssv_rate_info *sr)
+ssv6xxx_rc_hw_rate_update_check	smac/ssv_rc.c	/^u8 ssv6xxx_rc_hw_rate_update_check(struct sk_buff *skb, struct ssv_softc *sc, u32 do_rts_cts)$/;"	f	signature:(struct sk_buff *skb, struct ssv_softc *sc, u32 do_rts_cts)
+ssv6xxx_rc_hw_rate_update_check	smac/ssv_rc.h	/^u8 ssv6xxx_rc_hw_rate_update_check(struct sk_buff *skb, struct ssv_softc *sc, u32 do_rts_cts);$/;"	p	signature:(struct sk_buff *skb, struct ssv_softc *sc, u32 do_rts_cts)
+ssv6xxx_rc_hw_reset	smac/ssv_rc.c	/^void ssv6xxx_rc_hw_reset(struct ssv_softc *sc, int rc_idx, int hwidx)$/;"	f	signature:(struct ssv_softc *sc, int rc_idx, int hwidx)
+ssv6xxx_rc_hw_reset	smac/ssv_rc.h	/^void ssv6xxx_rc_hw_reset(struct ssv_softc *sc, int rc_idx, int hwidx);$/;"	p	signature:(struct ssv_softc *sc, int rc_idx, int hwidx)
+ssv6xxx_rc_mac80211_rate_idx	smac/ssv_rc.c	/^void ssv6xxx_rc_mac80211_rate_idx(struct ssv_softc *sc,$/;"	f	signature:(struct ssv_softc *sc, int hw_rate_idx, struct ieee80211_rx_status *rxs)
+ssv6xxx_rc_mac80211_rate_idx	smac/ssv_rc.h	/^void ssv6xxx_rc_mac80211_rate_idx(struct ssv_softc *sc, int hw_rate_idx,$/;"	p	signature:(struct ssv_softc *sc, int hw_rate_idx, struct ieee80211_rx_status *rxs)
+ssv6xxx_rc_phy_type	smac/ssv_rc_common.h	/^enum ssv6xxx_rc_phy_type {$/;"	g
+ssv6xxx_rc_rate_set	smac/ssv_rc.c	/^const u16 ssv6xxx_rc_rate_set[RC_TYPE_MAX][13] =$/;"	v
+ssv6xxx_rc_report_work	smac/dev.c	/^void ssv6xxx_rc_report_work(struct work_struct *work)$/;"	f	signature:(struct work_struct *work)
+ssv6xxx_rc_report_work	smac/dev.h	/^void ssv6xxx_rc_report_work(struct work_struct *work);$/;"	p	signature:(struct work_struct *work)
+ssv6xxx_rc_rx_data_handler	smac/ssv_rc.c	/^void ssv6xxx_rc_rx_data_handler(struct ieee80211_hw *hw, struct sk_buff *skb, u32 rate_index)$/;"	f	signature:(struct ieee80211_hw *hw, struct sk_buff *skb, u32 rate_index)
+ssv6xxx_rc_rx_data_handler	smac/ssv_rc.h	/^void ssv6xxx_rc_rx_data_handler(struct ieee80211_hw *hw, struct sk_buff *skb, u32 rate_index);$/;"	p	signature:(struct ieee80211_hw *hw, struct sk_buff *skb, u32 rate_index)
+ssv6xxx_rc_update_basic_rate	smac/ssv_rc.c	/^void ssv6xxx_rc_update_basic_rate(struct ssv_softc *sc, u32 basic_rates)$/;"	f	signature:(struct ssv_softc *sc, u32 basic_rates)
+ssv6xxx_rc_update_basic_rate	smac/ssv_rc.h	/^void ssv6xxx_rc_update_basic_rate(struct ssv_softc *sc, u32 basic_rates);$/;"	p	signature:(struct ssv_softc *sc, u32 basic_rates)
+ssv6xxx_rc_update_bmode_ctrl_rate	smac/ssv_rc.c	/^int ssv6xxx_rc_update_bmode_ctrl_rate(struct ssv_softc *sc, int rate_tbl_idx, int ctrl_rate_idx)$/;"	f	signature:(struct ssv_softc *sc, int rate_tbl_idx, int ctrl_rate_idx)
+ssv6xxx_read_configuration	smac/init.c	/^static int ssv6xxx_read_configuration(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6xxx_read_ffout_cnt	ssvdevice/ssv_cmd.c	/^static void ssv6xxx_read_ffout_cnt(struct ssv_hw *sh,$/;"	f	file:	signature:(struct ssv_hw *sh, u32 *value, u32 *value1, u32 *value2)
+ssv6xxx_read_hw_info	smac/init.c	/^static int ssv6xxx_read_hw_info(struct ssv_softc *sc)$/;"	f	file:	signature:(struct ssv_softc *sc)
+ssv6xxx_read_id_len_threshold	ssvdevice/ssv_cmd.c	/^static void ssv6xxx_read_id_len_threshold(struct ssv_hw *sh,$/;"	f	file:	signature:(struct ssv_hw *sh, u32 *tx_len, u32 *rx_len)
+ssv6xxx_read_in_ffcnt	ssvdevice/ssv_cmd.c	/^static void ssv6xxx_read_in_ffcnt(struct ssv_hw *sh,$/;"	f	file:	signature:(struct ssv_hw *sh, u32 *value, u32 *value1)
+ssv6xxx_read_reg	hwif/usb/usb.h	/^struct ssv6xxx_read_reg {$/;"	s
+ssv6xxx_read_reg::addr	hwif/usb/usb.h	/^ u32 addr;$/;"	m	struct:ssv6xxx_read_reg	access:public
+ssv6xxx_read_reg::value	hwif/usb/usb.h	/^ u32 value;$/;"	m	struct:ssv6xxx_read_reg	access:public
+ssv6xxx_read_reg_result	hwif/usb/usb.h	/^struct ssv6xxx_read_reg_result {$/;"	s
+ssv6xxx_read_reg_result::value	hwif/usb/usb.h	/^ u32 value;$/;"	m	struct:ssv6xxx_read_reg_result	access:public
+ssv6xxx_read_tag_status	ssvdevice/ssv_cmd.c	/^static void ssv6xxx_read_tag_status(struct ssv_hw *sh,$/;"	f	file:	signature:(struct ssv_hw *sh, u32 *ava_status)
+ssv6xxx_release_frames	smac/ampdu.c	/^void ssv6xxx_release_frames (struct AMPDU_TID_st *ampdu_tid)$/;"	f	signature:(struct AMPDU_TID_st *ampdu_tid)
+ssv6xxx_release_frames	smac/dev.h	/^void ssv6xxx_release_frames (struct AMPDU_TID_st *ampdu_tid);$/;"	p	signature:(struct AMPDU_TID_st *ampdu_tid)
+ssv6xxx_reset_mib	ssvdevice/ssv_cmd.c	/^static void ssv6xxx_reset_mib(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6xxx_reset_mib_phy	ssvdevice/ssv_cmd.c	/^static void ssv6xxx_reset_mib_phy(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6xxx_reset_sec_module	smac/dev.c	/^void ssv6xxx_reset_sec_module(struct ssv_softc *sc)$/;"	f	signature:(struct ssv_softc *sc)
+ssv6xxx_reset_sysplf	smac/dev.c	/^void ssv6xxx_reset_sysplf(struct ssv_hw *sh)$/;"	f	signature:(struct ssv_hw *sh)
+ssv6xxx_reset_sysplf	smac/dev.h	/^void ssv6xxx_reset_sysplf(struct ssv_hw *sh);$/;"	p	signature:(struct ssv_hw *sh)
+ssv6xxx_restart_hw	smac/init.c	/^void ssv6xxx_restart_hw(struct work_struct *work)$/;"	f	signature:(struct work_struct *work)
+ssv6xxx_restart_hw	smac/init.h	/^void ssv6xxx_restart_hw(struct work_struct *work);$/;"	p	signature:(struct work_struct *work)
+ssv6xxx_restore_hw_config	smac/init.c	/^static void ssv6xxx_restore_hw_config(struct ssv_softc *sc)$/;"	f	file:	signature:(struct ssv_softc *sc)
+ssv6xxx_restore_rx_flow	smac/dev.c	/^static void ssv6xxx_restore_rx_flow(struct ssv_softc *sc,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv, struct ieee80211_sta *sta)
+ssv6xxx_restore_trap_reason	smac/dev.c	/^void ssv6xxx_restore_trap_reason(struct ssv_softc *sc)$/;"	f	signature:(struct ssv_softc *sc)
+ssv6xxx_restore_trap_reason	smac/dev.h	/^void ssv6xxx_restore_trap_reason(struct ssv_softc *sc);$/;"	p	signature:(struct ssv_softc *sc)
+ssv6xxx_result_buf	smac/dev.h	/^    char *ssv6xxx_result_buf;$/;"	m	struct:ssv_cmd_data	access:public
+ssv6xxx_resume	smac/dev.c	/^int ssv6xxx_resume (struct ieee80211_hw *hw)$/;"	f	signature:(struct ieee80211_hw *hw)
+ssv6xxx_rf_disable	smac/dev.c	/^int ssv6xxx_rf_disable(struct ssv_hw *sh)$/;"	f	signature:(struct ssv_hw *sh)
+ssv6xxx_rf_disable	smac/dev.h	/^int ssv6xxx_rf_disable(struct ssv_hw *sh);$/;"	p	signature:(struct ssv_hw *sh)
+ssv6xxx_rf_enable	smac/dev.c	/^int ssv6xxx_rf_enable(struct ssv_hw *sh)$/;"	f	signature:(struct ssv_hw *sh)
+ssv6xxx_rf_enable	smac/dev.h	/^int ssv6xxx_rf_enable(struct ssv_hw *sh);$/;"	p	signature:(struct ssv_hw *sh)
+ssv6xxx_rx_buf	hwif/usb/usb.h	/^struct ssv6xxx_rx_buf {$/;"	s
+ssv6xxx_rx_buf::glue	hwif/usb/usb.h	/^    struct ssv6xxx_usb_glue *glue;$/;"	m	struct:ssv6xxx_rx_buf	typeref:struct:ssv6xxx_rx_buf::ssv6xxx_usb_glue	access:public
+ssv6xxx_rx_buf::node	hwif/usb/usb.h	/^    struct ssv6xxx_list_node node;$/;"	m	struct:ssv6xxx_rx_buf	typeref:struct:ssv6xxx_rx_buf::ssv6xxx_list_node	access:public
+ssv6xxx_rx_buf::rx_buf	hwif/usb/usb.h	/^    void *rx_buf;$/;"	m	struct:ssv6xxx_rx_buf	access:public
+ssv6xxx_rx_buf::rx_filled	hwif/usb/usb.h	/^    unsigned int rx_filled;$/;"	m	struct:ssv6xxx_rx_buf	access:public
+ssv6xxx_rx_buf::rx_res	hwif/usb/usb.h	/^    int rx_res;$/;"	m	struct:ssv6xxx_rx_buf	access:public
+ssv6xxx_rx_buf::rx_urb	hwif/usb/usb.h	/^    struct urb *rx_urb;$/;"	m	struct:ssv6xxx_rx_buf	typeref:struct:ssv6xxx_rx_buf::urb	access:public
+ssv6xxx_rx_burstread_size	smac/dev.c	/^int ssv6xxx_rx_burstread_size(void *param)$/;"	f	signature:(void *param)
+ssv6xxx_rx_burstread_size	smac/dev.h	/^int ssv6xxx_rx_burstread_size(void *param);$/;"	p	signature:(void *param)
+ssv6xxx_rx_endpoint	hwif/usb/usb.h	/^struct ssv6xxx_rx_endpoint {$/;"	s
+ssv6xxx_rx_endpoint::address	hwif/usb/usb.h	/^ u8 address;$/;"	m	struct:ssv6xxx_rx_endpoint	access:public
+ssv6xxx_rx_endpoint::packet_size	hwif/usb/usb.h	/^ u16 packet_size;$/;"	m	struct:ssv6xxx_rx_endpoint	access:public
+ssv6xxx_rx_hw_info	include/ssv6xxx_common.h	/^struct ssv6xxx_rx_hw_info {$/;"	s
+ssv6xxx_rx_hw_info::rx_ba_ma_sessions	include/ssv6xxx_common.h	/^ u32 rx_ba_ma_sessions;$/;"	m	struct:ssv6xxx_rx_hw_info	access:public
+ssv6xxx_rx_hw_info::rx_id_threshold	include/ssv6xxx_common.h	/^ u32 rx_id_threshold;$/;"	m	struct:ssv6xxx_rx_hw_info	access:public
+ssv6xxx_rx_hw_info::rx_page_threshold	include/ssv6xxx_common.h	/^ u32 rx_page_threshold;$/;"	m	struct:ssv6xxx_rx_hw_info	access:public
+ssv6xxx_rx_stuck_process	smac/dev.c	/^void ssv6xxx_rx_stuck_process(struct work_struct *work)$/;"	f	signature:(struct work_struct *work)
+ssv6xxx_rx_stuck_process	smac/dev.h	/^void ssv6xxx_rx_stuck_process(struct work_struct *work);$/;"	p	signature:(struct work_struct *work)
+ssv6xxx_rx_task	smac/dev.c	/^int ssv6xxx_rx_task (void *data)$/;"	f	signature:(void *data)
+ssv6xxx_rx_task	smac/dev.h	/^int ssv6xxx_rx_task (void *data);$/;"	p	signature:(void *data)
+ssv6xxx_save_clear_trap_reason	smac/dev.c	/^void ssv6xxx_save_clear_trap_reason(struct ssv_softc *sc)$/;"	f	signature:(struct ssv_softc *sc)
+ssv6xxx_save_clear_trap_reason	smac/dev.h	/^void ssv6xxx_save_clear_trap_reason(struct ssv_softc *sc);$/;"	p	signature:(struct ssv_softc *sc)
+ssv6xxx_save_default_ipd_chcfg	smac/dev.c	/^static void ssv6xxx_save_default_ipd_chcfg(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6xxx_save_default_ipd_chcfg	smac/hal/hal.c	/^static void ssv6xxx_save_default_ipd_chcfg(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6xxx_save_hw_config	smac/init.c	/^static void ssv6xxx_save_hw_config(void *param, u32 addr, u32 value)$/;"	f	file:	signature:(void *param, u32 addr, u32 value)
+ssv6xxx_save_hw_status	smac/dev.c	/^void ssv6xxx_save_hw_status(struct ssv_softc *sc)$/;"	f	signature:(struct ssv_softc *sc)
+ssv6xxx_save_hw_status	smac/dev.h	/^void ssv6xxx_save_hw_status(struct ssv_softc *sc);$/;"	p	signature:(struct ssv_softc *sc)
+ssv6xxx_sdio_burst_read_reg	hwif/sdio/sdio.c	/^static int __must_check ssv6xxx_sdio_burst_read_reg(struct device *child, u32 *addr,$/;"	f	file:	signature:(struct device *child, u32 *addr, u32 *buf, u8 reg_amount)
+ssv6xxx_sdio_burst_safe_read_reg	hwif/sdio/sdio.c	/^static int __must_check ssv6xxx_sdio_burst_safe_read_reg(struct device *child, u32 *addr,$/;"	f	file:	signature:(struct device *child, u32 *addr, u32 *buf, u8 reg_amount)
+ssv6xxx_sdio_burst_safe_write_reg	hwif/sdio/sdio.c	/^static int __must_check ssv6xxx_sdio_burst_safe_write_reg(struct device *child, u32 *addr,$/;"	f	file:	signature:(struct device *child, u32 *addr, u32 *buf, u8 reg_amount)
+ssv6xxx_sdio_burst_write_reg	hwif/sdio/sdio.c	/^static int __must_check ssv6xxx_sdio_burst_write_reg(struct device *child, u32 *addr,$/;"	f	file:	signature:(struct device *child, u32 *addr, u32 *buf, u8 reg_amount)
+ssv6xxx_sdio_cmd52_read	hwif/sdio/sdio.c	/^static int ssv6xxx_sdio_cmd52_read(struct device *child, u32 addr,$/;"	f	file:	signature:(struct device *child, u32 addr, u32 *value)
+ssv6xxx_sdio_cmd52_write	hwif/sdio/sdio.c	/^static int ssv6xxx_sdio_cmd52_write(struct device *child, u32 addr,$/;"	f	file:	signature:(struct device *child, u32 addr, u32 value)
+ssv6xxx_sdio_delay_chain	hwif/sdio/sdio.c	/^static void ssv6xxx_sdio_delay_chain(struct sdio_func *func, u32 input_delay, u32 output_delay)$/;"	f	file:	signature:(struct sdio_func *func, u32 input_delay, u32 output_delay)
+ssv6xxx_sdio_direct_int_mux_mode	hwif/sdio/sdio.c	/^static void ssv6xxx_sdio_direct_int_mux_mode(struct ssv6xxx_sdio_glue *glue, bool enable)$/;"	f	file:	signature:(struct ssv6xxx_sdio_glue *glue, bool enable)
+ssv6xxx_sdio_driver	hwif/sdio/sdio.c	/^EXPORT_SYMBOL(ssv6xxx_sdio_driver);$/;"	v
+ssv6xxx_sdio_driver	hwif/sdio/sdio.c	/^struct sdio_driver ssv6xxx_sdio_driver =$/;"	v	typeref:struct:sdio_driver
+ssv6xxx_sdio_exit	hwif/sdio/sdio.c	/^EXPORT_SYMBOL(ssv6xxx_sdio_exit);$/;"	v
+ssv6xxx_sdio_exit	hwif/sdio/sdio.c	/^module_exit(ssv6xxx_sdio_exit);$/;"	v
+ssv6xxx_sdio_exit	hwif/sdio/sdio.c	/^void ssv6xxx_sdio_exit(void)$/;"	f	signature:(void)
+ssv6xxx_sdio_exit	hwif/sdio/sdio.h	/^void ssv6xxx_sdio_exit(void);$/;"	p	signature:(void)
+ssv6xxx_sdio_get_aggr_readsz	hwif/sdio/sdio.c	/^static size_t ssv6xxx_sdio_get_aggr_readsz(struct device *child, int mode)$/;"	f	file:	signature:(struct device *child, int mode)
+ssv6xxx_sdio_get_readsz	hwif/sdio/sdio.c	/^static size_t ssv6xxx_sdio_get_readsz(struct device *child)$/;"	f	file:	signature:(struct device *child)
+ssv6xxx_sdio_glue	hwif/sdio/sdio.c	/^struct ssv6xxx_sdio_glue$/;"	s	file:
+ssv6xxx_sdio_glue::core	hwif/sdio/sdio.c	/^    struct platform_device *core;$/;"	m	struct:ssv6xxx_sdio_glue	typeref:struct:ssv6xxx_sdio_glue::platform_device	file:	access:public
+ssv6xxx_sdio_glue::dataIOPort	hwif/sdio/sdio.c	/^    unsigned int dataIOPort;$/;"	m	struct:ssv6xxx_sdio_glue	file:	access:public
+ssv6xxx_sdio_glue::dev	hwif/sdio/sdio.c	/^    struct device *dev;$/;"	m	struct:ssv6xxx_sdio_glue	typeref:struct:ssv6xxx_sdio_glue::device	file:	access:public
+ssv6xxx_sdio_glue::dev_ready	hwif/sdio/sdio.c	/^    bool dev_ready;$/;"	m	struct:ssv6xxx_sdio_glue	file:	access:public
+ssv6xxx_sdio_glue::dmaSkb	hwif/sdio/sdio.c	/^    struct sk_buff *dmaSkb;$/;"	m	struct:ssv6xxx_sdio_glue	typeref:struct:ssv6xxx_sdio_glue::sk_buff	file:	access:public
+ssv6xxx_sdio_glue::err_count	hwif/sdio/sdio.c	/^    unsigned int err_count;$/;"	m	struct:ssv6xxx_sdio_glue	file:	access:public
+ssv6xxx_sdio_glue::irq_dev	hwif/sdio/sdio.c	/^    void *irq_dev;$/;"	m	struct:ssv6xxx_sdio_glue	file:	access:public
+ssv6xxx_sdio_glue::irq_handler	hwif/sdio/sdio.c	/^    irq_handler_t irq_handler;$/;"	m	struct:ssv6xxx_sdio_glue	file:	access:public
+ssv6xxx_sdio_glue::p_wlan_data	hwif/sdio/sdio.c	/^    struct ssv6xxx_platform_data *p_wlan_data;$/;"	m	struct:ssv6xxx_sdio_glue	typeref:struct:ssv6xxx_sdio_glue::ssv6xxx_platform_data	file:	access:public
+ssv6xxx_sdio_glue::regIOPort	hwif/sdio/sdio.c	/^    unsigned int regIOPort;$/;"	m	struct:ssv6xxx_sdio_glue	file:	access:public
+ssv6xxx_sdio_glue::tmp_data	hwif/sdio/sdio.c	/^    struct ssv6xxx_platform_data tmp_data;$/;"	m	struct:ssv6xxx_sdio_glue	typeref:struct:ssv6xxx_sdio_glue::ssv6xxx_platform_data	file:	access:public
+ssv6xxx_sdio_init	hwif/sdio/sdio.c	/^EXPORT_SYMBOL(ssv6xxx_sdio_init);$/;"	v
+ssv6xxx_sdio_init	hwif/sdio/sdio.c	/^int ssv6xxx_sdio_init(void)$/;"	f	signature:(void)
+ssv6xxx_sdio_init	hwif/sdio/sdio.c	/^module_init(ssv6xxx_sdio_init);$/;"	v
+ssv6xxx_sdio_init	hwif/sdio/sdio.h	/^int ssv6xxx_sdio_init(void);$/;"	p	signature:(void)
+ssv6xxx_sdio_irq_disable	hwif/sdio/sdio.c	/^static void ssv6xxx_sdio_irq_disable(struct device *child, bool iswaitirq)$/;"	f	file:	signature:(struct device *child, bool iswaitirq)
+ssv6xxx_sdio_irq_enable	hwif/sdio/sdio.c	/^static void ssv6xxx_sdio_irq_enable(struct device *child)$/;"	f	file:	signature:(struct device *child)
+ssv6xxx_sdio_irq_getmask	hwif/sdio/sdio.c	/^static int ssv6xxx_sdio_irq_getmask(struct device *child, u32 *mask)$/;"	f	file:	signature:(struct device *child, u32 *mask)
+ssv6xxx_sdio_irq_getstatus	hwif/sdio/sdio.c	/^static int ssv6xxx_sdio_irq_getstatus(struct device *child,int *status)$/;"	f	file:	signature:(struct device *child,int *status)
+ssv6xxx_sdio_irq_handler	hwif/sdio/sdio.c	/^static void ssv6xxx_sdio_irq_handler(struct sdio_func *func)$/;"	f	file:	signature:(struct sdio_func *func)
+ssv6xxx_sdio_irq_request	hwif/sdio/sdio.c	/^static void ssv6xxx_sdio_irq_request(struct device *child,irq_handler_t irq_handler,void *irq_dev)$/;"	f	file:	signature:(struct device *child,irq_handler_t irq_handler,void *irq_dev)
+ssv6xxx_sdio_irq_setmask	hwif/sdio/sdio.c	/^static void ssv6xxx_sdio_irq_setmask(struct device *child,int mask)$/;"	f	file:	signature:(struct device *child,int mask)
+ssv6xxx_sdio_irq_trigger	hwif/sdio/sdio.c	/^static void ssv6xxx_sdio_irq_trigger(struct device *child)$/;"	f	file:	signature:(struct device *child)
+ssv6xxx_sdio_load_firmware	hwif/sdio/sdio.c	/^static int ssv6xxx_sdio_load_firmware(struct device *child, u32 start_addr, u8 *data, int data_length)$/;"	f	file:	signature:(struct device *child, u32 start_addr, u8 *data, int data_length)
+ssv6xxx_sdio_load_fw_post_config_hwif	hwif/sdio/sdio.c	/^static void ssv6xxx_sdio_load_fw_post_config_hwif(struct device *child)$/;"	f	file:	signature:(struct device *child)
+ssv6xxx_sdio_load_fw_pre_config_hwif	hwif/sdio/sdio.c	/^static void ssv6xxx_sdio_load_fw_pre_config_hwif(struct device *child)$/;"	f	file:	signature:(struct device *child)
+ssv6xxx_sdio_pm_ops	hwif/sdio/sdio.c	/^static const struct dev_pm_ops ssv6xxx_sdio_pm_ops =$/;"	v	typeref:struct:dev_pm_ops	file:
+ssv6xxx_sdio_pmu_wakeup	hwif/sdio/sdio.c	/^static void ssv6xxx_sdio_pmu_wakeup(struct device *child)$/;"	f	file:	signature:(struct device *child)
+ssv6xxx_sdio_power_off	hwif/sdio/sdio.c	/^static int ssv6xxx_sdio_power_off(struct ssv6xxx_platform_data * pdata, struct sdio_func *func)$/;"	f	file:	signature:(struct ssv6xxx_platform_data * pdata, struct sdio_func *func)
+ssv6xxx_sdio_power_on	hwif/sdio/sdio.c	/^static int ssv6xxx_sdio_power_on(struct ssv6xxx_platform_data * pdata, struct sdio_func *func)$/;"	f	file:	signature:(struct ssv6xxx_platform_data * pdata, struct sdio_func *func)
+ssv6xxx_sdio_probe	hwif/sdio/sdio.c	/^static int __devinit ssv6xxx_sdio_probe(struct sdio_func *func,$/;"	f	file:	signature:(struct sdio_func *func, const struct sdio_device_id *id)
+ssv6xxx_sdio_property	hwif/sdio/sdio.c	/^static int ssv6xxx_sdio_property(struct device *child)$/;"	f	file:	signature:(struct device *child)
+ssv6xxx_sdio_read	hwif/sdio/sdio.c	/^static int __must_check ssv6xxx_sdio_read(struct device *child,$/;"	f	file:	signature:(struct device *child, void *buf, size_t *size, int mode)
+ssv6xxx_sdio_read_parameter	hwif/sdio/sdio.c	/^static void ssv6xxx_sdio_read_parameter(struct sdio_func *func,$/;"	f	file:	signature:(struct sdio_func *func, struct ssv6xxx_sdio_glue *glue)
+ssv6xxx_sdio_read_reg	hwif/sdio/sdio.c	/^static int __must_check ssv6xxx_sdio_read_reg(struct device *child, u32 addr,$/;"	f	file:	signature:(struct device *child, u32 addr, u32 *buf)
+ssv6xxx_sdio_remove	hwif/sdio/sdio.c	/^static void __devexit ssv6xxx_sdio_remove(struct sdio_func *func)$/;"	f	file:	signature:(struct sdio_func *func)
+ssv6xxx_sdio_reset	hwif/sdio/sdio.c	/^static void ssv6xxx_sdio_reset(struct device *child)$/;"	f	file:	signature:(struct device *child)
+ssv6xxx_sdio_resume	hwif/sdio/sdio.c	/^static int ssv6xxx_sdio_resume(struct device *dev)$/;"	f	file:	signature:(struct device *dev)
+ssv6xxx_sdio_rw_scatter	hwif/sdio/sdio.c	/^static int ssv6xxx_sdio_rw_scatter(struct device *child,$/;"	f	file:	signature:(struct device *child, struct sdio_scatter_req *scat_req)
+ssv6xxx_sdio_safe_read_reg	hwif/sdio/sdio.c	/^static int __must_check ssv6xxx_sdio_safe_read_reg(struct device *child, u32 addr,$/;"	f	file:	signature:(struct device *child, u32 addr, u32 *buf)
+ssv6xxx_sdio_safe_write_reg	hwif/sdio/sdio.c	/^static int __must_check ssv6xxx_sdio_safe_write_reg(struct device *child, u32 addr,$/;"	f	file:	signature:(struct device *child, u32 addr, u32 buf)
+ssv6xxx_sdio_set_cmd53_arg	hwif/sdio/sdio.c	/^static inline void ssv6xxx_sdio_set_cmd53_arg(u32 *arg, u8 rw, u8 func,$/;"	f	file:	signature:(u32 *arg, u8 rw, u8 func, u8 mode, u8 opcode, u32 addr, u16 blksz)
+ssv6xxx_sdio_setup_scat_data	hwif/sdio/sdio.c	/^static void ssv6xxx_sdio_setup_scat_data(struct sdio_scatter_req *scat_req,$/;"	f	file:	signature:(struct sdio_scatter_req *scat_req, struct mmc_data *data)
+ssv6xxx_sdio_support_scatter	hwif/sdio/sdio.c	/^static bool ssv6xxx_sdio_support_scatter(struct device *child)$/;"	f	file:	signature:(struct device *child)
+ssv6xxx_sdio_suspend	hwif/sdio/sdio.c	/^static int ssv6xxx_sdio_suspend(struct device *dev)$/;"	f	file:	signature:(struct device *dev)
+ssv6xxx_sdio_sysplf_reset	hwif/sdio/sdio.c	/^static void ssv6xxx_sdio_sysplf_reset(struct device *child, u32 addr, u32 value)$/;"	f	file:	signature:(struct device *child, u32 addr, u32 value)
+ssv6xxx_sdio_trigger_tx_rx	hwif/sdio/sdio.c	/^static int ssv6xxx_sdio_trigger_tx_rx (struct device *child)$/;"	f	file:	signature:(struct device *child)
+ssv6xxx_sdio_write	hwif/sdio/sdio.c	/^static int __must_check ssv6xxx_sdio_write(struct device *child,$/;"	f	file:	signature:(struct device *child, void *buf, size_t len,u8 queue_num)
+ssv6xxx_sdio_write_reg	hwif/sdio/sdio.c	/^static int __must_check ssv6xxx_sdio_write_reg(struct device *child, u32 addr,$/;"	f	file:	signature:(struct device *child, u32 addr, u32 buf)
+ssv6xxx_sdio_write_sram	hwif/sdio/sdio.c	/^static int ssv6xxx_sdio_write_sram(struct device *child, u32 addr, u8 *data, u32 size)$/;"	f	file:	signature:(struct device *child, u32 addr, u8 *data, u32 size)
+ssv6xxx_send_deauth_toself	smac/ssv_pm.c	/^void ssv6xxx_send_deauth_toself(struct ssv_softc *sc,const u8 *bssid,const u8 *self_addr)$/;"	f	signature:(struct ssv_softc *sc,const u8 *bssid,const u8 *self_addr)
+ssv6xxx_send_noa_cmd	smac/p2p.c	/^void ssv6xxx_send_noa_cmd(struct ssv_softc *sc, struct ssv6xxx_p2p_noa_param *p2p_noa_param)$/;"	f	signature:(struct ssv_softc *sc, struct ssv6xxx_p2p_noa_param *p2p_noa_param)
+ssv6xxx_send_noa_cmd	smac/p2p.c	/^void ssv6xxx_send_noa_cmd(struct ssv_softc *sc, struct ssv6xxx_p2p_noa_param *p2p_noa_param);$/;"	p	file:	signature:(struct ssv_softc *sc, struct ssv6xxx_p2p_noa_param *p2p_noa_param)
+ssv6xxx_send_noa_cmd	ssvdevice/ssv_cmd.c	/^void ssv6xxx_send_noa_cmd(struct ssv_softc *sc, struct ssv6xxx_p2p_noa_param *p2p_noa_param)$/;"	f	signature:(struct ssv_softc *sc, struct ssv6xxx_p2p_noa_param *p2p_noa_param)
+ssv6xxx_send_si_cmd	smac/kssvsmart.c	/^EXPORT_SYMBOL(ssv6xxx_send_si_cmd);$/;"	v
+ssv6xxx_send_si_cmd	smac/kssvsmart.c	/^int ssv6xxx_send_si_cmd(u32 smart_icomm_cmd)$/;"	f	signature:(u32 smart_icomm_cmd)
+ssv6xxx_send_si_cmd	smac/kssvsmart.h	/^int ssv6xxx_send_si_cmd(u32 smart_icomm_cmd);$/;"	p	signature:(u32 smart_icomm_cmd)
+ssv6xxx_send_tx_poll_cmd	smac/dev.c	/^void ssv6xxx_send_tx_poll_cmd(struct ssv_hw *sh, u32 type)$/;"	f	signature:(struct ssv_hw *sh, u32 type)
+ssv6xxx_send_tx_poll_cmd	smac/dev.h	/^void ssv6xxx_send_tx_poll_cmd(struct ssv_hw *sh, u32 type);$/;"	p	signature:(struct ssv_hw *sh, u32 type)
+ssv6xxx_set_80211_hw_capab	smac/init.c	/^static void ssv6xxx_set_80211_hw_capab(struct ssv_softc *sc)$/;"	f	file:	signature:(struct ssv_softc *sc)
+ssv6xxx_set_80211_hw_rate_config	smac/dev.h	/^void ssv6xxx_set_80211_hw_rate_config(struct ssv_softc *sc);$/;"	p	signature:(struct ssv_softc *sc)
+ssv6xxx_set_80211_hw_rate_config	smac/init.c	/^void ssv6xxx_set_80211_hw_rate_config(struct ssv_softc *sc)$/;"	f	signature:(struct ssv_softc *sc)
+ssv6xxx_set_ampdu_rx_add_work	smac/ampdu.c	/^void ssv6xxx_set_ampdu_rx_add_work (struct work_struct *work)$/;"	f	signature:(struct work_struct *work)
+ssv6xxx_set_ampdu_rx_add_work	smac/ampdu.h	/^extern void ssv6xxx_set_ampdu_rx_add_work(struct work_struct *work);$/;"	p	signature:(struct work_struct *work)
+ssv6xxx_set_ampdu_rx_del_work	smac/ampdu.c	/^void ssv6xxx_set_ampdu_rx_del_work (struct work_struct *work)$/;"	f	signature:(struct work_struct *work)
+ssv6xxx_set_ampdu_rx_del_work	smac/ampdu.h	/^extern void ssv6xxx_set_ampdu_rx_del_work(struct work_struct *work);$/;"	p	signature:(struct work_struct *work)
+ssv6xxx_set_bssid	smac/dev.c	/^static int ssv6xxx_set_bssid(struct ssv_hw *sh, u8 *bssid)$/;"	f	file:	signature:(struct ssv_hw *sh, u8 *bssid)
+ssv6xxx_set_channel	smac/dev.c	/^int ssv6xxx_set_channel(struct ssv_softc *sc, struct ieee80211_channel *chan, enum nl80211_channel_type channel_type)$/;"	f	signature:(struct ssv_softc *sc, struct ieee80211_channel *chan, enum nl80211_channel_type channel_type)
+ssv6xxx_set_channel	smac/dev.c	/^int ssv6xxx_set_channel(struct ssv_softc *sc, struct ieee80211_channel *channel, enum nl80211_channel_type)$/;"	f	signature:(struct ssv_softc *sc, struct ieee80211_channel *channel, enum nl80211_channel_type)
+ssv6xxx_set_channel	smac/dev.h	/^int ssv6xxx_set_channel(struct ssv_softc *sc, struct ieee80211_channel *channel, enum nl80211_channel_type);$/;"	p	signature:(struct ssv_softc *sc, struct ieee80211_channel *channel, enum nl80211_channel_type)
+ssv6xxx_set_dur_burst_sifs_g	smac/dev.c	/^static void ssv6xxx_set_dur_burst_sifs_g(struct ssv_hw *sh, u32 val)$/;"	f	file:	signature:(struct ssv_hw *sh, u32 val)
+ssv6xxx_set_dur_slot	smac/dev.c	/^static void ssv6xxx_set_dur_slot(struct ssv_hw *sh, u32 val)$/;"	f	file:	signature:(struct ssv_hw *sh, u32 val)
+ssv6xxx_set_frame_duration	smac/dev.c	/^static u32 ssv6xxx_set_frame_duration(struct ieee80211_tx_info *info,$/;"	f	file:	signature:(struct ieee80211_tx_info *info, struct ssv_rate_info *ssv_rate, u16 len, struct ssv6200_tx_desc *tx_desc, struct fw_rc_retry_params *rc_params, struct ssv_softc *sc)
+ssv6xxx_set_fw_hwwsid_sec_type	smac/dev.c	/^static void ssv6xxx_set_fw_hwwsid_sec_type(struct ssv_softc *sc, struct ieee80211_sta *sta,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ieee80211_sta *sta, struct ssv_sta_info *sta_info, struct ssv_vif_priv_data *vif_priv)
+ssv6xxx_set_hw_wsid	smac/dev.c	/^static void ssv6xxx_set_hw_wsid(struct ssv_softc *sc, struct ieee80211_vif *vif,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ieee80211_vif *vif, struct ieee80211_sta *sta, int wsid)
+ssv6xxx_set_macaddr	smac/dev.c	/^static int ssv6xxx_set_macaddr(struct ssv_hw *sh, int vif_idx)$/;"	f	file:	signature:(struct ssv_hw *sh, int vif_idx)
+ssv6xxx_set_on3_enable	smac/dev.c	/^void ssv6xxx_set_on3_enable(struct ssv_hw *sh, bool val)$/;"	f	signature:(struct ssv_hw *sh, bool val)
+ssv6xxx_set_on3_enable	smac/dev.h	/^int ssv6xxx_set_on3_enable(struct ssv_hw *sh, bool val);$/;"	p	signature:(struct ssv_hw *sh, bool val)
+ssv6xxx_set_on3_enable	smac/hal/hal.c	/^void ssv6xxx_set_on3_enable(struct ssv_hw *sh, bool val)$/;"	f	signature:(struct ssv_hw *sh, bool val)
+ssv6xxx_set_op_mode	smac/dev.c	/^static void ssv6xxx_set_op_mode(struct ssv_hw *sh, u32 op_mode)$/;"	f	file:	signature:(struct ssv_hw *sh, u32 op_mode)
+ssv6xxx_set_promisc	smac/dev.c	/^int ssv6xxx_set_promisc(struct ssv_softc *sc, int accept)$/;"	f	signature:(struct ssv_softc *sc, int accept)
+ssv6xxx_set_promisc	smac/dev.h	/^int ssv6xxx_set_promisc(struct ssv_softc *sc, int accept);$/;"	p	signature:(struct ssv_softc *sc, int accept)
+ssv6xxx_set_rx_ctrl_flow	smac/dev.c	/^int ssv6xxx_set_rx_ctrl_flow(struct ssv_hw *sh)$/;"	f	signature:(struct ssv_hw *sh)
+ssv6xxx_set_rx_ctrl_flow	smac/dev.h	/^int ssv6xxx_set_rx_ctrl_flow(struct ssv_hw *sh);$/;"	p	signature:(struct ssv_hw *sh)
+ssv6xxx_set_rx_flow	smac/dev.c	/^static int ssv6xxx_set_rx_flow(struct ssv_hw *sh, enum ssv_rx_flow type, u32 rxflow)$/;"	f	file:	signature:(struct ssv_hw *sh, enum ssv_rx_flow type, u32 rxflow)
+ssv6xxx_set_sdio_clk	hwif/sdio/sdio.c	/^static void ssv6xxx_set_sdio_clk(struct sdio_func *func, u32 sdio_hz)$/;"	f	file:	signature:(struct sdio_func *func, u32 sdio_hz)
+ssv6xxx_set_sifs	smac/hal/hal.c	/^static void ssv6xxx_set_sifs(struct ssv_hw *sh, int band)$/;"	f	file:	signature:(struct ssv_hw *sh, int band)
+ssv6xxx_set_txpwr_process	smac/dev.c	/^void ssv6xxx_set_txpwr_process(struct work_struct *work)$/;"	f	signature:(struct work_struct *work)
+ssv6xxx_set_txpwr_process	smac/dev.h	/^void ssv6xxx_set_txpwr_process(struct work_struct *work);$/;"	p	signature:(struct work_struct *work)
+ssv6xxx_set_wmm_param	smac/dev.c	/^static void ssv6xxx_set_wmm_param(struct ssv_softc *sc,$/;"	f	file:	signature:(struct ssv_softc *sc, const struct ieee80211_tx_queue_params *params, u16 queue)
+ssv6xxx_sgi_stat	smac/ssv_rc_minstrel_ht.h	/^enum ssv6xxx_sgi_stat{$/;"	g
+ssv6xxx_si_cfg	include/ssv6xxx_common.h	/^struct ssv6xxx_si_cfg {$/;"	s
+ssv6xxx_si_cfg::password	include/ssv6xxx_common.h	/^    u8 password[64];$/;"	m	struct:ssv6xxx_si_cfg	access:public
+ssv6xxx_si_cfg::password_len	include/ssv6xxx_common.h	/^    s32 password_len;$/;"	m	struct:ssv6xxx_si_cfg	access:public
+ssv6xxx_si_cfg::ssid	include/ssv6xxx_common.h	/^    u8 ssid[32];$/;"	m	struct:ssv6xxx_si_cfg	access:public
+ssv6xxx_si_cfg::ssid_len	include/ssv6xxx_common.h	/^    s32 ssid_len;$/;"	m	struct:ssv6xxx_si_cfg	access:public
+ssv6xxx_skb_decrypt	smac/dev.c	/^int ssv6xxx_skb_decrypt(struct sk_buff *mpdu, struct ieee80211_sta *sta, struct ssv_softc *sc)$/;"	f	signature:(struct sk_buff *mpdu, struct ieee80211_sta *sta, struct ssv_softc *sc)
+ssv6xxx_skb_decrypt	smac/dev.h	/^int ssv6xxx_skb_decrypt(struct sk_buff *mpdu, struct ieee80211_sta *sta,struct ssv_softc *sc);$/;"	p	signature:(struct sk_buff *mpdu, struct ieee80211_sta *sta,struct ssv_softc *sc)
+ssv6xxx_skb_encrypt	smac/dev.c	/^int ssv6xxx_skb_encrypt(struct sk_buff *mpdu, struct ssv_softc *sc)$/;"	f	signature:(struct sk_buff *mpdu, struct ssv_softc *sc)
+ssv6xxx_skb_encrypt	smac/dev.h	/^int ssv6xxx_skb_encrypt(struct sk_buff *mpdu,struct ssv_softc *sc);$/;"	p	signature:(struct sk_buff *mpdu,struct ssv_softc *sc)
+ssv6xxx_skb_get_rx_cryptops	smac/dev.c	/^struct ssv_crypto_data *ssv6xxx_skb_get_rx_cryptops(struct ssv_softc *sc, struct ieee80211_sta *sta, struct sk_buff *mpdu)$/;"	f	signature:(struct ssv_softc *sc, struct ieee80211_sta *sta, struct sk_buff *mpdu)
+ssv6xxx_skb_get_rx_cryptops	smac/dev.h	/^struct ssv_crypto_data *ssv6xxx_skb_get_rx_cryptops(struct ssv_softc *sc,$/;"	p	signature:(struct ssv_softc *sc, struct ieee80211_sta *sta, struct sk_buff *mpdu)
+ssv6xxx_skb_get_tx_cryptops	smac/dev.c	/^struct ssv_crypto_data * ssv6xxx_skb_get_tx_cryptops(struct sk_buff *mpdu)$/;"	f	signature:(struct sk_buff *mpdu)
+ssv6xxx_skb_get_tx_cryptops	smac/dev.h	/^struct ssv_crypto_data *ssv6xxx_skb_get_tx_cryptops(struct sk_buff *mpdu);$/;"	p	signature:(struct sk_buff *mpdu)
+ssv6xxx_skb_pre_decrypt	smac/dev.c	/^int ssv6xxx_skb_pre_decrypt(struct sk_buff *mpdu, struct ieee80211_sta *sta, struct ssv_softc *sc)$/;"	f	signature:(struct sk_buff *mpdu, struct ieee80211_sta *sta, struct ssv_softc *sc)
+ssv6xxx_skb_pre_decrypt	smac/dev.h	/^int ssv6xxx_skb_pre_decrypt(struct sk_buff *mpdu, struct ieee80211_sta *sta, struct ssv_softc *sc);$/;"	p	signature:(struct sk_buff *mpdu, struct ieee80211_sta *sta, struct ssv_softc *sc)
+ssv6xxx_skb_pre_encrypt	smac/dev.c	/^int ssv6xxx_skb_pre_encrypt(struct sk_buff *mpdu, struct ssv_softc *sc)$/;"	f	signature:(struct sk_buff *mpdu, struct ssv_softc *sc)
+ssv6xxx_skb_pre_encrypt	smac/dev.h	/^int ssv6xxx_skb_pre_encrypt(struct sk_buff *mpdu, struct ssv_softc *sc);$/;"	p	signature:(struct sk_buff *mpdu, struct ssv_softc *sc)
+ssv6xxx_soc_event	include/ssv6xxx_common.h	/^} ssv6xxx_soc_event;$/;"	t	typeref:enum:__anon45
+ssv6xxx_ssn_to_bit_idx	smac/ampdu.c	/^bool ssv6xxx_ssn_to_bit_idx (u32 start_ssn, u32 mpdu_ssn, u32 *word_idx,$/;"	f	signature:(u32 start_ssn, u32 mpdu_ssn, u32 *word_idx, u32 *bit_idx)
+ssv6xxx_ssn_to_bit_idx	smac/dev.h	/^bool ssv6xxx_ssn_to_bit_idx (u32 start_ssn, u32 mpdu_ssn, u32 *word_idx,$/;"	p	signature:(u32 start_ssn, u32 mpdu_ssn, u32 *word_idx, u32 *bit_idx)
+ssv6xxx_stop_all_running_threads	smac/init.c	/^static void ssv6xxx_stop_all_running_threads(struct ssv_softc *sc) ;$/;"	p	file:	signature:(struct ssv_softc *sc)
+ssv6xxx_stop_all_running_threads	smac/init.c	/^static void ssv6xxx_stop_all_running_threads(struct ssv_softc *sc) {$/;"	f	file:	signature:(struct ssv_softc *sc)
+ssv6xxx_suspend	smac/dev.c	/^int ssv6xxx_suspend (struct ieee80211_hw *hw, struct cfg80211_wowlan *wowlan)$/;"	f	signature:(struct ieee80211_hw *hw, struct cfg80211_wowlan *wowlan)
+ssv6xxx_thermal_monitor_process	smac/dev.c	/^void ssv6xxx_thermal_monitor_process(struct work_struct *work)$/;"	f	signature:(struct work_struct *work)
+ssv6xxx_thermal_monitor_process	smac/dev.h	/^void ssv6xxx_thermal_monitor_process(struct work_struct *work);$/;"	p	signature:(struct work_struct *work)
+ssv6xxx_trigger_pmu	smac/dev.c	/^int ssv6xxx_trigger_pmu(struct ssv_softc *sc)$/;"	f	signature:(struct ssv_softc *sc)
+ssv6xxx_trigger_pmu	smac/dev.h	/^int ssv6xxx_trigger_pmu(struct ssv_softc *sc);$/;"	p	signature:(struct ssv_softc *sc)
+ssv6xxx_tx_endpoint	hwif/usb/usb.h	/^struct ssv6xxx_tx_endpoint {$/;"	s
+ssv6xxx_tx_endpoint::address	hwif/usb/usb.h	/^ u8 address;$/;"	m	struct:ssv6xxx_tx_endpoint	access:public
+ssv6xxx_tx_endpoint::packet_size	hwif/usb/usb.h	/^ u16 packet_size;$/;"	m	struct:ssv6xxx_tx_endpoint	access:public
+ssv6xxx_tx_endpoint::tx_res	hwif/usb/usb.h	/^ int tx_res;$/;"	m	struct:ssv6xxx_tx_endpoint	access:public
+ssv6xxx_tx_hw_info	include/ssv6xxx_common.h	/^struct ssv6xxx_tx_hw_info {$/;"	s
+ssv6xxx_tx_hw_info::be_txq_size	include/ssv6xxx_common.h	/^ u32 be_txq_size;$/;"	m	struct:ssv6xxx_tx_hw_info	access:public
+ssv6xxx_tx_hw_info::bk_txq_size	include/ssv6xxx_common.h	/^ u32 bk_txq_size;$/;"	m	struct:ssv6xxx_tx_hw_info	access:public
+ssv6xxx_tx_hw_info::manage_txq_size	include/ssv6xxx_common.h	/^ u32 manage_txq_size;$/;"	m	struct:ssv6xxx_tx_hw_info	access:public
+ssv6xxx_tx_hw_info::tx_id_threshold	include/ssv6xxx_common.h	/^ u32 tx_id_threshold;$/;"	m	struct:ssv6xxx_tx_hw_info	access:public
+ssv6xxx_tx_hw_info::tx_lowthreshold_id_trigger	include/ssv6xxx_common.h	/^ u32 tx_lowthreshold_id_trigger;$/;"	m	struct:ssv6xxx_tx_hw_info	access:public
+ssv6xxx_tx_hw_info::tx_lowthreshold_page_trigger	include/ssv6xxx_common.h	/^ u32 tx_lowthreshold_page_trigger;$/;"	m	struct:ssv6xxx_tx_hw_info	access:public
+ssv6xxx_tx_hw_info::tx_page_threshold	include/ssv6xxx_common.h	/^ u32 tx_page_threshold;$/;"	m	struct:ssv6xxx_tx_hw_info	access:public
+ssv6xxx_tx_hw_info::vi_txq_size	include/ssv6xxx_common.h	/^ u32 vi_txq_size;$/;"	m	struct:ssv6xxx_tx_hw_info	access:public
+ssv6xxx_tx_hw_info::vo_txq_size	include/ssv6xxx_common.h	/^ u32 vo_txq_size;$/;"	m	struct:ssv6xxx_tx_hw_info	access:public
+ssv6xxx_tx_loopback	include/ssv6xxx_common.h	/^struct ssv6xxx_tx_loopback {$/;"	s
+ssv6xxx_tx_loopback::delay_ms	include/ssv6xxx_common.h	/^    u8 delay_ms;$/;"	m	struct:ssv6xxx_tx_loopback	access:public
+ssv6xxx_tx_loopback::reg	include/ssv6xxx_common.h	/^    u32 reg;$/;"	m	struct:ssv6xxx_tx_loopback	access:public
+ssv6xxx_tx_loopback::restore	include/ssv6xxx_common.h	/^    u8 restore;$/;"	m	struct:ssv6xxx_tx_loopback	access:public
+ssv6xxx_tx_loopback::restore_val	include/ssv6xxx_common.h	/^    u32 restore_val;$/;"	m	struct:ssv6xxx_tx_loopback	access:public
+ssv6xxx_tx_loopback::val	include/ssv6xxx_common.h	/^    u32 val;$/;"	m	struct:ssv6xxx_tx_loopback	access:public
+ssv6xxx_tx_poll_process	smac/dev.c	/^void ssv6xxx_tx_poll_process(struct work_struct *work)$/;"	f	signature:(struct work_struct *work)
+ssv6xxx_tx_poll_process	smac/dev.h	/^void ssv6xxx_tx_poll_process(struct work_struct *work);$/;"	p	signature:(struct work_struct *work)
+ssv6xxx_tx_q_empty_cb	smac/dev.c	/^void ssv6xxx_tx_q_empty_cb (u32 txq_no, void *cb_data)$/;"	f	signature:(u32 txq_no, void *cb_data)
+ssv6xxx_tx_q_empty_cb	smac/dev.h	/^void ssv6xxx_tx_q_empty_cb (u32 txq_no, void *);$/;"	p	signature:(u32 txq_no, void *)
+ssv6xxx_tx_queue_status_dump	smac/dev.c	/^ssize_t ssv6xxx_tx_queue_status_dump (struct ssv_softc *sc, char *status_buf,$/;"	f	signature:(struct ssv_softc *sc, char *status_buf, ssize_t length)
+ssv6xxx_tx_queue_status_dump	smac/dev.h	/^ssize_t ssv6xxx_tx_queue_status_dump (struct ssv_softc *sc, char *status_buf,$/;"	p	signature:(struct ssv_softc *sc, char *status_buf, ssize_t buf_size)
+ssv6xxx_tx_rate_update	smac/dev.c	/^void ssv6xxx_tx_rate_update(struct sk_buff *skb, void *args)$/;"	f	signature:(struct sk_buff *skb, void *args)
+ssv6xxx_tx_rate_update	smac/dev.h	/^void ssv6xxx_tx_rate_update(struct sk_buff *skb, void *args);$/;"	p	signature:(struct sk_buff *skb, void *args)
+ssv6xxx_tx_status	smac/ssv_rc.c	/^static void ssv6xxx_tx_status(void *priv, struct ieee80211_supported_band *sband,$/;"	f	file:	signature:(void *priv, struct ieee80211_supported_band *sband, struct ieee80211_sta *sta, void *priv_sta, struct sk_buff *skb)
+ssv6xxx_tx_task	smac/dev.c	/^int ssv6xxx_tx_task (void *data)$/;"	f	signature:(void *data)
+ssv6xxx_tx_task	smac/dev.h	/^int ssv6xxx_tx_task (void *data);$/;"	p	signature:(void *data)
+ssv6xxx_txbuf_free_skb	smac/dev.c	/^void ssv6xxx_txbuf_free_skb(struct sk_buff *skb, void *args)$/;"	f	signature:(struct sk_buff *skb, void *args)
+ssv6xxx_txbuf_free_skb	smac/dev.h	/^void ssv6xxx_txbuf_free_skb(struct sk_buff *skb , void *args);$/;"	p	signature:(struct sk_buff *skb , void *args)
+ssv6xxx_txtput_set_desc	ssvdevice/ssv_cmd.c	/^static void ssv6xxx_txtput_set_desc(struct ssv_hw *sh, struct sk_buff *skb )$/;"	f	file:	signature:(struct ssv_hw *sh, struct sk_buff *skb )
+ssv6xxx_umac_attach	smac/init.c	/^EXPORT_SYMBOL(ssv6xxx_umac_attach);$/;"	v
+ssv6xxx_umac_attach	smac/init.c	/^int ssv6xxx_umac_attach(char *driver_name, char *device_name, struct ssv6xxx_umac_ops *umac_ops)$/;"	f	signature:(char *driver_name, char *device_name, struct ssv6xxx_umac_ops *umac_ops)
+ssv6xxx_umac_attach	smac/init.h	/^int ssv6xxx_umac_attach(char *driver_name, char *device_name, struct ssv6xxx_umac_ops *umac_ops);$/;"	p	signature:(char *driver_name, char *device_name, struct ssv6xxx_umac_ops *umac_ops)
+ssv6xxx_umac_deattach	smac/init.c	/^EXPORT_SYMBOL(ssv6xxx_umac_deattach);$/;"	v
+ssv6xxx_umac_deattach	smac/init.c	/^int ssv6xxx_umac_deattach(char *driver_name, char *device_name)$/;"	f	signature:(char *driver_name, char *device_name)
+ssv6xxx_umac_deattach	smac/init.h	/^int ssv6xxx_umac_deattach(char *driver_name, char *device_name);$/;"	p	signature:(char *driver_name, char *device_name)
+ssv6xxx_umac_hci_start	smac/init.c	/^EXPORT_SYMBOL(ssv6xxx_umac_hci_start);$/;"	v
+ssv6xxx_umac_hci_start	smac/init.c	/^void ssv6xxx_umac_hci_start(char *driver_name, char *device_name)$/;"	f	signature:(char *driver_name, char *device_name)
+ssv6xxx_umac_hci_start	smac/init.h	/^void ssv6xxx_umac_hci_start(char *driver_name, char *device_name);$/;"	p	signature:(char *driver_name, char *device_name)
+ssv6xxx_umac_ops	smac/dev.h	/^struct ssv6xxx_umac_ops {$/;"	s
+ssv6xxx_umac_ops::umac_rx_raw	smac/dev.h	/^    int (*umac_rx_raw)(struct sk_buff *);$/;"	m	struct:ssv6xxx_umac_ops	access:public
+ssv6xxx_umac_reg_read	smac/init.c	/^EXPORT_SYMBOL(ssv6xxx_umac_reg_read);$/;"	v
+ssv6xxx_umac_reg_read	smac/init.c	/^void ssv6xxx_umac_reg_read(char *driver_name, char *device_name, u32 addr, u32 *regval)$/;"	f	signature:(char *driver_name, char *device_name, u32 addr, u32 *regval)
+ssv6xxx_umac_reg_read	smac/init.h	/^void ssv6xxx_umac_reg_read(char *driver_name, char *device_name, u32 addr, u32 *regval);$/;"	p	signature:(char *driver_name, char *device_name, u32 addr, u32 *regval)
+ssv6xxx_umac_reg_write	smac/init.c	/^EXPORT_SYMBOL(ssv6xxx_umac_reg_write);$/;"	v
+ssv6xxx_umac_reg_write	smac/init.c	/^void ssv6xxx_umac_reg_write(char *driver_name, char *device_name, u32 addr, u32 value)$/;"	f	signature:(char *driver_name, char *device_name, u32 addr, u32 value)
+ssv6xxx_umac_reg_write	smac/init.h	/^void ssv6xxx_umac_reg_write(char *driver_name, char *device_name, u32 addr, u32 value);$/;"	p	signature:(char *driver_name, char *device_name, u32 addr, u32 value)
+ssv6xxx_umac_test	smac/init.c	/^EXPORT_SYMBOL(ssv6xxx_umac_test);$/;"	v
+ssv6xxx_umac_test	smac/init.c	/^void ssv6xxx_umac_test(char *driver_name, char *device_name, struct sk_buff *skb, int size)$/;"	f	signature:(char *driver_name, char *device_name, struct sk_buff *skb, int size)
+ssv6xxx_umac_test	smac/init.h	/^void ssv6xxx_umac_test(char *driver_name, char *device_name, struct sk_buff *skb, int size);$/;"	p	signature:(char *driver_name, char *device_name, struct sk_buff *skb, int size)
+ssv6xxx_umac_tx_frame	smac/init.c	/^EXPORT_SYMBOL(ssv6xxx_umac_tx_frame);$/;"	v
+ssv6xxx_umac_tx_frame	smac/init.c	/^void ssv6xxx_umac_tx_frame(char *driver_name, char *device_name, struct sk_buff *skb)$/;"	f	signature:(char *driver_name, char *device_name, struct sk_buff *skb)
+ssv6xxx_umac_tx_frame	smac/init.h	/^void ssv6xxx_umac_tx_frame(char *driver_name, char *device_name, struct sk_buff *skb);$/;"	p	signature:(char *driver_name, char *device_name, struct sk_buff *skb)
+ssv6xxx_update_cfg_hw_patch	smac/hal/hal.c	/^static void ssv6xxx_update_cfg_hw_patch(struct ssv_hw *sh,$/;"	f	file:	signature:(struct ssv_hw *sh, ssv_cabrio_reg *rf_table, ssv_cabrio_reg *phy_table)
+ssv6xxx_update_decision_table	smac/dev.c	/^int ssv6xxx_update_decision_table(struct ssv_softc *sc)$/;"	f	signature:(struct ssv_softc *sc)
+ssv6xxx_update_decision_table	smac/dev.h	/^int ssv6xxx_update_decision_table(struct ssv_softc *sc);$/;"	p	signature:(struct ssv_softc *sc)
+ssv6xxx_update_efuse_setting	smac/dev.c	/^int ssv6xxx_update_efuse_setting(struct ssv_hw *sh)$/;"	f	signature:(struct ssv_hw *sh)
+ssv6xxx_update_efuse_setting	smac/dev.h	/^int ssv6xxx_update_efuse_setting(struct ssv_hw *sh);$/;"	p	signature:(struct ssv_hw *sh)
+ssv6xxx_update_efuse_setting	smac/hal/hal.c	/^static int ssv6xxx_update_efuse_setting(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6xxx_update_hw_config	smac/hal/hal.c	/^static void ssv6xxx_update_hw_config(struct ssv_hw *sh,$/;"	f	file:	signature:(struct ssv_hw *sh, ssv_cabrio_reg *rf_table, ssv_cabrio_reg *phy_table)
+ssv6xxx_update_null_func_txinfo	smac/dev.c	/^int ssv6xxx_update_null_func_txinfo(struct ssv_softc *sc, struct ieee80211_sta *sta, struct sk_buff *skb)$/;"	f	signature:(struct ssv_softc *sc, struct ieee80211_sta *sta, struct sk_buff *skb)
+ssv6xxx_update_null_func_txinfo	smac/dev.h	/^int ssv6xxx_update_null_func_txinfo(struct ssv_softc *sc, struct ieee80211_sta *sta, struct sk_buff *skb);$/;"	p	signature:(struct ssv_softc *sc, struct ieee80211_sta *sta, struct sk_buff *skb)
+ssv6xxx_update_product_hw_setting	smac/hal/hal.c	/^static void ssv6xxx_update_product_hw_setting(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6xxx_update_rf_pwr	smac/hal/hal.c	/^static void ssv6xxx_update_rf_pwr(struct ssv_softc *sc){$/;"	f	file:	signature:(struct ssv_softc *sc)
+ssv6xxx_update_txinfo	smac/dev.c	/^void ssv6xxx_update_txinfo (struct ssv_softc *sc, struct sk_buff *skb)$/;"	f	signature:(struct ssv_softc *sc, struct sk_buff *skb)
+ssv6xxx_update_txinfo	smac/dev.h	/^void ssv6xxx_update_txinfo (struct ssv_softc *sc, struct sk_buff *skb);$/;"	p	signature:(struct ssv_softc *sc, struct sk_buff *skb)
+ssv6xxx_update_wep_hw_security_setting	smac/dev.c	/^static void ssv6xxx_update_wep_hw_security_setting(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv, struct ieee80211_key_conf *hw_key)$/;"	f	file:	signature:(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv, struct ieee80211_key_conf *hw_key)
+ssv6xxx_usb_burst_read_reg	hwif/usb/usb.c	/^static int __must_check ssv6xxx_usb_burst_read_reg(struct device *child, u32 *addr,$/;"	f	file:	signature:(struct device *child, u32 *addr, u32 *buf, u8 reg_amount)
+ssv6xxx_usb_burst_write_reg	hwif/usb/usb.c	/^static int __must_check ssv6xxx_usb_burst_write_reg(struct device *child, u32 *addr,$/;"	f	file:	signature:(struct device *child, u32 *addr, u32 *buf, u8 reg_amount)
+ssv6xxx_usb_cmd	hwif/usb/usb.c	/^static int ssv6xxx_usb_cmd(struct ssv6xxx_usb_glue *glue, u8 cmd, void *data, u32 data_len, void *result)$/;"	f	file:	signature:(struct ssv6xxx_usb_glue *glue, u8 cmd, void *data, u32 data_len, void *result)
+ssv6xxx_usb_delete	hwif/usb/usb.c	/^static void ssv6xxx_usb_delete(struct kref *kref)$/;"	f	file:	signature:(struct kref *kref)
+ssv6xxx_usb_exit	hwif/usb/usb.c	/^EXPORT_SYMBOL(ssv6xxx_usb_exit);$/;"	v
+ssv6xxx_usb_exit	hwif/usb/usb.c	/^module_exit(ssv6xxx_usb_exit);$/;"	v
+ssv6xxx_usb_exit	hwif/usb/usb.c	/^void ssv6xxx_usb_exit(void)$/;"	f	signature:(void)
+ssv6xxx_usb_exit	hwif/usb/usb.h	/^void ssv6xxx_usb_exit(void);$/;"	p	signature:(void)
+ssv6xxx_usb_glue	hwif/usb/usb.c	/^struct ssv6xxx_usb_glue {$/;"	s	file:
+ssv6xxx_usb_glue::cmd_endpoint	hwif/usb/usb.c	/^ struct ssv6xxx_cmd_endpoint cmd_endpoint;$/;"	m	struct:ssv6xxx_usb_glue	typeref:struct:ssv6xxx_usb_glue::ssv6xxx_cmd_endpoint	file:	access:public
+ssv6xxx_usb_glue::cmd_mutex	hwif/usb/usb.c	/^ struct mutex cmd_mutex;$/;"	m	struct:ssv6xxx_usb_glue	typeref:struct:ssv6xxx_usb_glue::mutex	file:	access:public
+ssv6xxx_usb_glue::core	hwif/usb/usb.c	/^ struct platform_device *core;$/;"	m	struct:ssv6xxx_usb_glue	typeref:struct:ssv6xxx_usb_glue::platform_device	file:	access:public
+ssv6xxx_usb_glue::dev	hwif/usb/usb.c	/^ struct device *dev;$/;"	m	struct:ssv6xxx_usb_glue	typeref:struct:ssv6xxx_usb_glue::device	file:	access:public
+ssv6xxx_usb_glue::dev_ready	hwif/usb/usb.c	/^ bool dev_ready;$/;"	m	struct:ssv6xxx_usb_glue	file:	access:public
+ssv6xxx_usb_glue::err_cnt	hwif/usb/usb.c	/^ u16 err_cnt;$/;"	m	struct:ssv6xxx_usb_glue	file:	access:public
+ssv6xxx_usb_glue::interface	hwif/usb/usb.c	/^ struct usb_interface *interface;$/;"	m	struct:ssv6xxx_usb_glue	typeref:struct:ssv6xxx_usb_glue::usb_interface	file:	access:public
+ssv6xxx_usb_glue::io_mutex	hwif/usb/usb.c	/^ struct mutex io_mutex;$/;"	m	struct:ssv6xxx_usb_glue	typeref:struct:ssv6xxx_usb_glue::mutex	file:	access:public
+ssv6xxx_usb_glue::is_rx_q_full	hwif/usb/usb.c	/^    int (*is_rx_q_full)(void *);$/;"	m	struct:ssv6xxx_usb_glue	file:	access:public
+ssv6xxx_usb_glue::kref	hwif/usb/usb.c	/^ struct kref kref;$/;"	m	struct:ssv6xxx_usb_glue	typeref:struct:ssv6xxx_usb_glue::kref	file:	access:public
+ssv6xxx_usb_glue::p_wlan_data	hwif/usb/usb.c	/^    struct ssv6xxx_platform_data *p_wlan_data;$/;"	m	struct:ssv6xxx_usb_glue	typeref:struct:ssv6xxx_usb_glue::ssv6xxx_platform_data	file:	access:public
+ssv6xxx_usb_glue::rsp_endpoint	hwif/usb/usb.c	/^ struct ssv6xxx_cmd_endpoint rsp_endpoint;$/;"	m	struct:ssv6xxx_usb_glue	typeref:struct:ssv6xxx_usb_glue::ssv6xxx_cmd_endpoint	file:	access:public
+ssv6xxx_usb_glue::rx_cb	hwif/usb/usb.c	/^    int (*rx_cb)(struct sk_buff *rx_skb, void *args);$/;"	m	struct:ssv6xxx_usb_glue	file:	access:public
+ssv6xxx_usb_glue::rx_cb	hwif/usb/usb.c	/^    int (*rx_cb)(struct sk_buff_head *rxq, void *args);$/;"	m	struct:ssv6xxx_usb_glue	file:	access:public
+ssv6xxx_usb_glue::rx_cb_args	hwif/usb/usb.c	/^ void *rx_cb_args;$/;"	m	struct:ssv6xxx_usb_glue	file:	access:public
+ssv6xxx_usb_glue::rx_endpoint	hwif/usb/usb.c	/^ struct ssv6xxx_rx_endpoint rx_endpoint;$/;"	m	struct:ssv6xxx_usb_glue	typeref:struct:ssv6xxx_usb_glue::ssv6xxx_rx_endpoint	file:	access:public
+ssv6xxx_usb_glue::rx_pkt	hwif/usb/usb.c	/^ u32 *rx_pkt;$/;"	m	struct:ssv6xxx_usb_glue	file:	access:public
+ssv6xxx_usb_glue::rx_tasklet	hwif/usb/usb.c	/^ struct tasklet_struct rx_tasklet;$/;"	m	struct:ssv6xxx_usb_glue	typeref:struct:ssv6xxx_usb_glue::tasklet_struct	file:	access:public
+ssv6xxx_usb_glue::rx_work	hwif/usb/usb.c	/^ struct ssv6xxx_usb_work_struct rx_work;$/;"	m	struct:ssv6xxx_usb_glue	typeref:struct:ssv6xxx_usb_glue::ssv6xxx_usb_work_struct	file:	access:public
+ssv6xxx_usb_glue::sequence	hwif/usb/usb.c	/^ u16 sequence;$/;"	m	struct:ssv6xxx_usb_glue	file:	access:public
+ssv6xxx_usb_glue::ssv_rx_buf	hwif/usb/usb.c	/^ struct ssv6xxx_rx_buf ssv_rx_buf[MAX_NR_RECVBUFF];$/;"	m	struct:ssv6xxx_usb_glue	typeref:struct:ssv6xxx_usb_glue::ssv6xxx_rx_buf	file:	access:public
+ssv6xxx_usb_glue::ssv_rx_queue	hwif/usb/usb.c	/^ struct ssv6xxx_queue ssv_rx_queue;$/;"	m	struct:ssv6xxx_usb_glue	typeref:struct:ssv6xxx_usb_glue::ssv6xxx_queue	file:	access:public
+ssv6xxx_usb_glue::tmp_data	hwif/usb/usb.c	/^ struct ssv6xxx_platform_data tmp_data;$/;"	m	struct:ssv6xxx_usb_glue	typeref:struct:ssv6xxx_usb_glue::ssv6xxx_platform_data	file:	access:public
+ssv6xxx_usb_glue::tx_endpoint	hwif/usb/usb.c	/^ struct ssv6xxx_tx_endpoint tx_endpoint;$/;"	m	struct:ssv6xxx_usb_glue	typeref:struct:ssv6xxx_usb_glue::ssv6xxx_tx_endpoint	file:	access:public
+ssv6xxx_usb_glue::udev	hwif/usb/usb.c	/^ struct usb_device *udev;$/;"	m	struct:ssv6xxx_usb_glue	typeref:struct:ssv6xxx_usb_glue::usb_device	file:	access:public
+ssv6xxx_usb_glue::wq	hwif/usb/usb.c	/^ struct workqueue_struct *wq;$/;"	m	struct:ssv6xxx_usb_glue	typeref:struct:ssv6xxx_usb_glue::workqueue_struct	file:	access:public
+ssv6xxx_usb_init	hwif/usb/usb.c	/^EXPORT_SYMBOL(ssv6xxx_usb_init);$/;"	v
+ssv6xxx_usb_init	hwif/usb/usb.c	/^int ssv6xxx_usb_init(void)$/;"	f	signature:(void)
+ssv6xxx_usb_init	hwif/usb/usb.c	/^module_init(ssv6xxx_usb_init);$/;"	v
+ssv6xxx_usb_init	hwif/usb/usb.h	/^int ssv6xxx_usb_init(void);$/;"	p	signature:(void)
+ssv6xxx_usb_jump_to_rom	hwif/usb/usb.c	/^static int ssv6xxx_usb_jump_to_rom(struct device *child)$/;"	f	file:	signature:(struct device *child)
+ssv6xxx_usb_load_firmware	hwif/usb/usb.c	/^static int ssv6xxx_usb_load_firmware(struct device *child, u32 start_addr, u8 *data, int data_length)$/;"	f	file:	signature:(struct device *child, u32 start_addr, u8 *data, int data_length)
+ssv6xxx_usb_power_off	hwif/usb/usb.c	/^static void ssv6xxx_usb_power_off(struct ssv6xxx_platform_data * pdata, struct usb_interface *interface)$/;"	f	file:	signature:(struct ssv6xxx_platform_data * pdata, struct usb_interface *interface)
+ssv6xxx_usb_power_on	hwif/usb/usb.c	/^static void ssv6xxx_usb_power_on(struct ssv6xxx_platform_data * pdata, struct usb_interface *interface)$/;"	f	file:	signature:(struct ssv6xxx_platform_data * pdata, struct usb_interface *interface)
+ssv6xxx_usb_property	hwif/usb/usb.c	/^static int ssv6xxx_usb_property(struct device *child)$/;"	f	file:	signature:(struct device *child)
+ssv6xxx_usb_read	hwif/usb/usb.c	/^static int __must_check ssv6xxx_usb_read(struct device *child,$/;"	f	file:	signature:(struct device *child, void *buf, size_t *size, int mode)
+ssv6xxx_usb_read_reg	hwif/usb/usb.c	/^static int __must_check ssv6xxx_usb_read_reg(struct device *child, u32 addr,$/;"	f	file:	signature:(struct device *child, u32 addr, u32 *buf)
+ssv6xxx_usb_recv_rsp	hwif/usb/usb.c	/^static int ssv6xxx_usb_recv_rsp(struct ssv6xxx_usb_glue *glue, int size, int *rsp_len)$/;"	f	file:	signature:(struct ssv6xxx_usb_glue *glue, int size, int *rsp_len)
+ssv6xxx_usb_recv_rx	hwif/usb/usb.c	/^static void ssv6xxx_usb_recv_rx(struct ssv6xxx_usb_glue *glue, struct ssv6xxx_rx_buf *ssv_rx_buf)$/;"	f	file:	signature:(struct ssv6xxx_usb_glue *glue, struct ssv6xxx_rx_buf *ssv_rx_buf)
+ssv6xxx_usb_recv_rx	hwif/usb/usb.c	/^static void ssv6xxx_usb_recv_rx(struct ssv6xxx_usb_glue *glue, struct ssv6xxx_rx_buf *ssv_rx_buf);$/;"	p	file:	signature:(struct ssv6xxx_usb_glue *glue, struct ssv6xxx_rx_buf *ssv_rx_buf)
+ssv6xxx_usb_recv_rx_complete	hwif/usb/usb.c	/^static void ssv6xxx_usb_recv_rx_complete(struct urb *urb)$/;"	f	file:	signature:(struct urb *urb)
+ssv6xxx_usb_recv_rx_tasklet	hwif/usb/usb.c	/^static void ssv6xxx_usb_recv_rx_tasklet(unsigned long priv)$/;"	f	file:	signature:(unsigned long priv)
+ssv6xxx_usb_recv_rx_work	hwif/usb/usb.c	/^static void ssv6xxx_usb_recv_rx_work(struct work_struct *work)$/;"	f	file:	signature:(struct work_struct *work)
+ssv6xxx_usb_rx_task	hwif/usb/usb.c	/^static void ssv6xxx_usb_rx_task(struct device *child,$/;"	f	file:	signature:(struct device *child, int (*rx_cb)(struct sk_buff_head *rxq, void *args), int (*is_rx_q_full)(void *args), void *args, u32 *pkt)
+ssv6xxx_usb_send_cmd	hwif/usb/usb.c	/^static int ssv6xxx_usb_send_cmd(struct ssv6xxx_usb_glue *glue, u8 cmd, u16 seq, const void *data, u32 data_len)$/;"	f	file:	signature:(struct ssv6xxx_usb_glue *glue, u8 cmd, u16 seq, const void *data, u32 data_len)
+ssv6xxx_usb_send_tx	hwif/usb/usb.c	/^static int ssv6xxx_usb_send_tx(struct ssv6xxx_usb_glue *glue, struct sk_buff *skb, size_t size)$/;"	f	file:	signature:(struct ssv6xxx_usb_glue *glue, struct sk_buff *skb, size_t size)
+ssv6xxx_usb_start_acc	hwif/usb/usb.c	/^static int ssv6xxx_usb_start_acc(struct device *child, u8 epnum)$/;"	f	file:	signature:(struct device *child, u8 epnum)
+ssv6xxx_usb_stop_acc	hwif/usb/usb.c	/^static int ssv6xxx_usb_stop_acc(struct device *child, u8 epnum)$/;"	f	file:	signature:(struct device *child, u8 epnum)
+ssv6xxx_usb_sysplf_reset	hwif/usb/usb.c	/^static void ssv6xxx_usb_sysplf_reset(struct device *child, u32 addr, u32 value)$/;"	f	file:	signature:(struct device *child, u32 addr, u32 value)
+ssv6xxx_usb_work_struct	hwif/usb/usb.h	/^struct ssv6xxx_usb_work_struct {$/;"	s
+ssv6xxx_usb_work_struct::glue	hwif/usb/usb.h	/^    struct ssv6xxx_usb_glue *glue;$/;"	m	struct:ssv6xxx_usb_work_struct	typeref:struct:ssv6xxx_usb_work_struct::ssv6xxx_usb_glue	access:public
+ssv6xxx_usb_work_struct::work	hwif/usb/usb.h	/^    struct work_struct work;$/;"	m	struct:ssv6xxx_usb_work_struct	typeref:struct:ssv6xxx_usb_work_struct::work_struct	access:public
+ssv6xxx_usb_write	hwif/usb/usb.c	/^static int __must_check ssv6xxx_usb_write(struct device *child,$/;"	f	file:	signature:(struct device *child, void *buf, size_t len, u8 queue_num)
+ssv6xxx_usb_write_reg	hwif/usb/usb.c	/^static int __must_check ssv6xxx_usb_write_reg(struct device *child, u32 addr,$/;"	f	file:	signature:(struct device *child, u32 addr, u32 buf)
+ssv6xxx_use_hw_encrypt	smac/dev.c	/^static bool ssv6xxx_use_hw_encrypt(int cipher, struct ssv_softc *sc,$/;"	f	file:	signature:(int cipher, struct ssv_softc *sc, struct ssv_sta_priv_data *sta_priv, struct ssv_vif_priv_data *vif_priv )
+ssv6xxx_user_app_pid	umac/ssv6xxx_netlink_core.c	/^static u32 ssv6xxx_user_app_pid = 0;$/;"	v	file:
+ssv6xxx_wait_usb_rom_ready	smac/hal/hal.c	/^static void ssv6xxx_wait_usb_rom_ready(struct ssv_hw *sh)$/;"	f	file:	signature:(struct ssv_hw *sh)
+ssv6xxx_wep_use_hw_cipher	smac/dev.c	/^static bool ssv6xxx_wep_use_hw_cipher(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv)$/;"	f	file:	signature:(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv)
+ssv6xxx_write_efuse	smac/hal/hal.c	/^static void ssv6xxx_write_efuse(struct ssv_hw *sh, u8 *data, u8 data_length)$/;"	f	file:	signature:(struct ssv_hw *sh, u8 *data, u8 data_length)
+ssv6xxx_write_key_to_hw	smac/dev.c	/^static void ssv6xxx_write_key_to_hw(struct ssv_softc *sc, struct ssv6xxx_hw_sec *sram_key,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ssv6xxx_hw_sec *sram_key, int wsid, int key_idx, enum SSV6XXX_WSID_SEC key_type)
+ssv6xxx_write_pairwise_keyidx_to_hw	smac/dev.c	/^void ssv6xxx_write_pairwise_keyidx_to_hw(struct ssv_hw *sh, int key_idx, int wsid)$/;"	f	signature:(struct ssv_hw *sh, int key_idx, int wsid)
+ssv6xxx_write_reg	hwif/usb/usb.h	/^struct ssv6xxx_write_reg {$/;"	s
+ssv6xxx_write_reg::addr	hwif/usb/usb.h	/^ u32 addr;$/;"	m	struct:ssv6xxx_write_reg	access:public
+ssv6xxx_write_reg::value	hwif/usb/usb.h	/^ u32 value;$/;"	m	struct:ssv6xxx_write_reg	access:public
+ssv6xxx_wsid_params	include/ssv6xxx_common.h	/^struct ssv6xxx_wsid_params$/;"	s
+ssv6xxx_wsid_params::cmd	include/ssv6xxx_common.h	/^    u8 cmd;$/;"	m	struct:ssv6xxx_wsid_params	access:public
+ssv6xxx_wsid_params::hw_security	include/ssv6xxx_common.h	/^    u8 hw_security;$/;"	m	struct:ssv6xxx_wsid_params	access:public
+ssv6xxx_wsid_params::target_wsid	include/ssv6xxx_common.h	/^    u8 target_wsid[6];$/;"	m	struct:ssv6xxx_wsid_params	access:public
+ssv6xxx_wsid_params::wsid_idx	include/ssv6xxx_common.h	/^    u8 wsid_idx;$/;"	m	struct:ssv6xxx_wsid_params	access:public
+ssv_11bgn_rate_table	smac/ssv_rc.c	/^static struct ssv_rc_rate ssv_11bgn_rate_table[] =$/;"	v	typeref:struct:ssv_rc_rate	file:
+ssv_6xxx_wlan_init	platforms/t10-generic-wlan.c	/^extern int ssv_6xxx_wlan_init(void);$/;"	p	file:	signature:(void)
+ssv_6xxx_wlan_init	platforms/x1000-generic-wlan.c	/^extern int ssv_6xxx_wlan_init(void);$/;"	p	file:	signature:(void)
+ssv_airkiss_result	smartlink/airkiss.c	/^static airkiss_result_t ssv_airkiss_result;$/;"	v	file:
+ssv_attach_ssv6006	smac/hal/ssv6006c/ssv6006C_mac.c	/^void ssv_attach_ssv6006(struct ssv_softc *sc, struct ssv_hal_ops *hal_ops)$/;"	f	signature:(struct ssv_softc *sc, struct ssv_hal_ops *hal_ops)
+ssv_attach_ssv6006_cabrioA_BBRF	smac/hal/ssv6006c/ssv6006_priv.h	/^void ssv_attach_ssv6006_cabrioA_BBRF(struct ssv_hal_ops *hal_ops);$/;"	p	signature:(struct ssv_hal_ops *hal_ops)
+ssv_attach_ssv6006_common	smac/hal/ssv6006c/ssv6006_common.c	/^void ssv_attach_ssv6006_common(struct ssv_hal_ops *hal_ops)$/;"	f	signature:(struct ssv_hal_ops *hal_ops)
+ssv_attach_ssv6006_common	smac/hal/ssv6006c/ssv6006_priv.h	/^void ssv_attach_ssv6006_common(struct ssv_hal_ops *hal_ops);$/;"	p	signature:(struct ssv_hal_ops *hal_ops)
+ssv_attach_ssv6006_geminiA_BBRF	smac/hal/ssv6006c/ssv6006_priv.h	/^void ssv_attach_ssv6006_geminiA_BBRF(struct ssv_hal_ops *hal_ops);$/;"	p	signature:(struct ssv_hal_ops *hal_ops)
+ssv_attach_ssv6006_mac	smac/hal/ssv6006c/ssv6006_priv.h	/^void ssv_attach_ssv6006_mac(struct ssv_hal_ops *hal_ops);$/;"	p	signature:(struct ssv_hal_ops *hal_ops)
+ssv_attach_ssv6006_phy	smac/hal/ssv6006c/ssv6006_phy.c	/^void ssv_attach_ssv6006_phy(struct ssv_hal_ops *hal_ops)$/;"	f	signature:(struct ssv_hal_ops *hal_ops)
+ssv_attach_ssv6006_phy	smac/hal/ssv6006c/ssv6006_priv.h	/^void ssv_attach_ssv6006_phy(struct ssv_hal_ops *hal_ops);$/;"	p	signature:(struct ssv_hal_ops *hal_ops)
+ssv_attach_ssv6006_turismoA_BBRF	smac/hal/ssv6006c/ssv6006_priv.h	/^void ssv_attach_ssv6006_turismoA_BBRF(struct ssv_hal_ops *hal_ops);$/;"	p	signature:(struct ssv_hal_ops *hal_ops)
+ssv_attach_ssv6006_turismoB_BBRF	smac/hal/ssv6006c/ssv6006_priv.h	/^void ssv_attach_ssv6006_turismoB_BBRF(struct ssv_hal_ops *hal_ops);$/;"	p	signature:(struct ssv_hal_ops *hal_ops)
+ssv_attach_ssv6006_turismoC_BBRF	smac/hal/ssv6006c/ssv6006_priv.h	/^void ssv_attach_ssv6006_turismoC_BBRF(struct ssv_hal_ops *hal_ops);$/;"	p	signature:(struct ssv_hal_ops *hal_ops)
+ssv_attach_ssv6006_turismoC_BBRF	smac/hal/ssv6006c/ssv6006_turismoC.c	/^void ssv_attach_ssv6006_turismoC_BBRF(struct ssv_hal_ops *hal_ops)$/;"	f	signature:(struct ssv_hal_ops *hal_ops)
+ssv_attach_ssv6006c_mac	smac/hal/ssv6006c/ssv6006C_mac.c	/^void ssv_attach_ssv6006c_mac(struct ssv_hal_ops *hal_ops)$/;"	f	signature:(struct ssv_hal_ops *hal_ops)
+ssv_attach_ssv6006c_mac	smac/hal/ssv6006c/ssv6006_priv.h	/^void ssv_attach_ssv6006c_mac(struct ssv_hal_ops *hal_ops);$/;"	p	signature:(struct ssv_hal_ops *hal_ops)
+ssv_attach_ssv6006c_phy	smac/hal/ssv6006c/ssv6006_priv.h	/^void ssv_attach_ssv6006c_phy(struct ssv_hal_ops *hal_ops);$/;"	p	signature:(struct ssv_hal_ops *hal_ops)
+ssv_attach_ssv6051_cabrioA_BBRF	smac/hal/ssv6006c/ssv6006_priv.h	/^void ssv_attach_ssv6051_cabrioA_BBRF(struct ssv_hal_ops *hal_ops);$/;"	p	signature:(struct ssv_hal_ops *hal_ops)
+ssv_attach_ssv6051_phy	smac/hal/ssv6006c/ssv6006_priv.h	/^void ssv_attach_ssv6051_phy(struct ssv_hal_ops *hal_ops);$/;"	p	signature:(struct ssv_hal_ops *hal_ops)
+ssv_bar	smac/ampdu.h	/^struct ssv_bar {$/;"	s
+ssv_bar::control	smac/ampdu.h	/^ unsigned short control;$/;"	m	struct:ssv_bar	access:public
+ssv_bar::duration	smac/ampdu.h	/^ unsigned short duration;$/;"	m	struct:ssv_bar	access:public
+ssv_bar::frame_control	smac/ampdu.h	/^ unsigned short frame_control;$/;"	m	struct:ssv_bar	access:public
+ssv_bar::ra	smac/ampdu.h	/^ unsigned char ra[6];$/;"	m	struct:ssv_bar	access:public
+ssv_bar::start_seq_num	smac/ampdu.h	/^ unsigned short start_seq_num;$/;"	m	struct:ssv_bar	access:public
+ssv_bar::ta	smac/ampdu.h	/^ unsigned char ta[6];$/;"	m	struct:ssv_bar	access:public
+ssv_baw_head	smac/ampdu.h	/^    volatile u16 ssv_baw_head;$/;"	m	struct:AMPDU_TID_st	access:public
+ssv_baw_size	smac/ampdu.h	/^    u16 ssv_baw_size;$/;"	m	struct:AMPDU_TID_st	access:public
+ssv_cabrio_reg	include/ssv6xxx_common.h	/^} ssv_cabrio_reg;$/;"	t	typeref:struct:ssv_cabrio_reg_st
+ssv_cabrio_reg_st	include/ssv6xxx_common.h	/^typedef struct ssv_cabrio_reg_st {$/;"	s
+ssv_cabrio_reg_st::address	include/ssv6xxx_common.h	/^    u32 address;$/;"	m	struct:ssv_cabrio_reg_st	access:public
+ssv_cabrio_reg_st::data	include/ssv6xxx_common.h	/^    u32 data;$/;"	m	struct:ssv_cabrio_reg_st	access:public
+ssv_calc_rate_durations	smac/ssv_rc_minstrel.c	/^static void ssv_calc_rate_durations(enum nl80211_band band, struct ssv_minstrel_rate *d,$/;"	f	file:	signature:(enum nl80211_band band, struct ssv_minstrel_rate *d, struct ieee80211_rate *rate, int use_short_preamble)
+ssv_cfg	ssvdevice/ssv_cmd.c	/^EXPORT_SYMBOL(ssv_cfg);$/;"	v
+ssv_cfg	ssvdevice/ssv_cmd.c	/^struct ssv6xxx_cfg ssv_cfg;$/;"	v	typeref:struct:ssv6xxx_cfg
+ssv_cmd_Info	smac/p2p.h	/^struct ssv_cmd_Info{$/;"	s
+ssv_cmd_Info::cmd_que	smac/p2p.h	/^    struct sk_buff_head cmd_que;$/;"	m	struct:ssv_cmd_Info	typeref:struct:ssv_cmd_Info::sk_buff_head	access:public
+ssv_cmd_Info::evt_que	smac/p2p.h	/^    struct sk_buff_head evt_que;$/;"	m	struct:ssv_cmd_Info	typeref:struct:ssv_cmd_Info::sk_buff_head	access:public
+ssv_cmd_Info::state	smac/p2p.h	/^    enum ssv_cmd_state state;$/;"	m	struct:ssv_cmd_Info	typeref:enum:ssv_cmd_Info::ssv_cmd_state	access:public
+ssv_cmd_cali	ssvdevice/ssv_cmd.c	/^static int ssv_cmd_cali(struct ssv_softc *sc, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_softc *sc, int argc, char *argv[])
+ssv_cmd_cci	ssvdevice/ssv_cmd.c	/^static int ssv_cmd_cci(struct ssv_softc *sc, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_softc *sc, int argc, char *argv[])
+ssv_cmd_cfg	ssvdevice/ssv_cmd.c	/^static int ssv_cmd_cfg(struct ssv_softc *sc, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_softc *sc, int argc, char *argv[])
+ssv_cmd_chan	ssvdevice/ssv_cmd.c	/^static int ssv_cmd_chan(struct ssv_softc *sc, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_softc *sc, int argc, char *argv[])
+ssv_cmd_check	ssvdevice/ssv_cmd.c	/^static int ssv_cmd_check(struct ssv_softc *sc, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_softc *sc, int argc, char *argv[])
+ssv_cmd_data	smac/dev.h	/^struct ssv_cmd_data{$/;"	s
+ssv_cmd_data::cli_count	smac/dev.h	/^ atomic_t cli_count;$/;"	m	struct:ssv_cmd_data	access:public
+ssv_cmd_data::cmd_in_proc	smac/dev.h	/^    bool cmd_in_proc;$/;"	m	struct:ssv_cmd_data	access:public
+ssv_cmd_data::dbg_log	smac/dev.h	/^ struct ssv_dbg_log dbg_log;$/;"	m	struct:ssv_cmd_data	typeref:struct:ssv_cmd_data::ssv_dbg_log	access:public
+ssv_cmd_data::log_to_ram	smac/dev.h	/^ bool log_to_ram;$/;"	m	struct:ssv_cmd_data	access:public
+ssv_cmd_data::proc_dev_entry	smac/dev.h	/^ struct proc_dir_entry *proc_dev_entry;$/;"	m	struct:ssv_cmd_data	typeref:struct:ssv_cmd_data::proc_dir_entry	access:public
+ssv_cmd_data::rsbuf_len	smac/dev.h	/^    u32 rsbuf_len;$/;"	m	struct:ssv_cmd_data	access:public
+ssv_cmd_data::rsbuf_size	smac/dev.h	/^    u32 rsbuf_size;$/;"	m	struct:ssv_cmd_data	access:public
+ssv_cmd_data::ssv6xxx_result_buf	smac/dev.h	/^    char *ssv6xxx_result_buf;$/;"	m	struct:ssv_cmd_data	access:public
+ssv_cmd_directack	ssvdevice/ssv_cmd.c	/^static int ssv_cmd_directack(struct ssv_softc *sc, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_softc *sc, int argc, char *argv[])
+ssv_cmd_dump	ssvdevice/ssv_cmd.c	/^static int ssv_cmd_dump(struct ssv_softc *sc, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_softc *sc, int argc, char *argv[])
+ssv_cmd_efuse	ssvdevice/ssv_cmd.c	/^static int ssv_cmd_efuse(struct ssv_softc *sc, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_softc *sc, int argc, char *argv[])
+ssv_cmd_get_chip_id	ssvdevice/ssv_cmd.c	/^static void ssv_cmd_get_chip_id(struct ssv_softc *sc, char *chip_id)$/;"	f	file:	signature:(struct ssv_softc *sc, char *chip_id)
+ssv_cmd_hci	ssvdevice/ssv_cmd.c	/^static int ssv_cmd_hci(struct ssv_softc *sc, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_softc *sc, int argc, char *argv[])
+ssv_cmd_help	ssvdevice/ssv_cmd.c	/^static int ssv_cmd_help(struct ssv_softc *sc, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_softc *sc, int argc, char *argv[])
+ssv_cmd_hwinfo	ssvdevice/ssv_cmd.c	/^static int ssv_cmd_hwinfo(struct ssv_softc *sc, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_softc *sc, int argc, char *argv[])
+ssv_cmd_hwq	ssvdevice/ssv_cmd.c	/^static int ssv_cmd_hwq(struct ssv_softc *sc, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_softc *sc, int argc, char *argv[])
+ssv_cmd_hwq_limit	ssvdevice/ssv_cmd.c	/^static int ssv_cmd_hwq_limit(struct ssv_softc *sc, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_softc *sc, int argc, char *argv[])
+ssv_cmd_init	ssvdevice/ssv_cmd.c	/^static int ssv_cmd_init(struct ssv_softc *sc, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_softc *sc, int argc, char *argv[])
+ssv_cmd_iqk	ssvdevice/ssv_cmd.c	/^static int ssv_cmd_iqk (struct ssv_softc *sc, int argc, char *argv[]) {$/;"	f	file:	signature:(struct ssv_softc *sc, int argc, char *argv[])
+ssv_cmd_irq	ssvdevice/ssv_cmd.c	/^static int ssv_cmd_irq(struct ssv_softc *sc, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_softc *sc, int argc, char *argv[])
+ssv_cmd_log	ssvdevice/ssv_cmd.c	/^static int ssv_cmd_log(struct ssv_softc *sc, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_softc *sc, int argc, char *argv[])
+ssv_cmd_lpbk	ssvdevice/ssv_cmd.c	/^static int ssv_cmd_lpbk(struct ssv_softc *sc, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_softc *sc, int argc, char *argv[])
+ssv_cmd_mac	ssvdevice/ssv_cmd.c	/^static int ssv_cmd_mac(struct ssv_softc *sc, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_softc *sc, int argc, char *argv[])
+ssv_cmd_mib	ssvdevice/ssv_cmd.c	/^static int ssv_cmd_mib(struct ssv_softc *sc, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_softc *sc, int argc, char *argv[])
+ssv_cmd_noa	ssvdevice/ssv_cmd.c	/^static int ssv_cmd_noa(struct ssv_softc *sc, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_softc *sc, int argc, char *argv[])
+ssv_cmd_power_saving	ssvdevice/ssv_cmd.c	/^static int ssv_cmd_power_saving(struct ssv_softc *sc, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_softc *sc, int argc, char *argv[])
+ssv_cmd_rawpkt	ssvdevice/ssv_cmd.c	/^static int ssv_cmd_rawpkt(struct ssv_softc *sc, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_softc *sc, int argc, char *argv[])
+ssv_cmd_rawpkt_context	ssvdevice/ssv_cmd.c	/^static int ssv_cmd_rawpkt_context(char *buf, int len, void *file)$/;"	f	file:	signature:(char *buf, int len, void *file)
+ssv_cmd_rawpkt_send	ssvdevice/ssv_cmd.c	/^static void ssv_cmd_rawpkt_send(struct ssv_hw *sh, char *filename)$/;"	f	file:	signature:(struct ssv_hw *sh, char *filename)
+ssv_cmd_rc	ssvdevice/ssv_cmd.c	/^static int ssv_cmd_rc(struct ssv_softc *sc, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_softc *sc, int argc, char *argv[])
+ssv_cmd_reg	ssvdevice/ssv_cmd.c	/^static int ssv_cmd_reg(struct ssv_softc *sc, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_softc *sc, int argc, char *argv[])
+ssv_cmd_rf	ssvdevice/ssv_cmd.c	/^static int ssv_cmd_rf(struct ssv_softc *sc, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_softc *sc, int argc, char *argv[])
+ssv_cmd_rxtput	ssvdevice/ssv_cmd.c	/^static int ssv_cmd_rxtput(struct ssv_softc *sc, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_softc *sc, int argc, char *argv[])
+ssv_cmd_sdio	ssvdevice/ssv_cmd.c	/^static int ssv_cmd_sdio(struct ssv_softc *sc, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_softc *sc, int argc, char *argv[])
+ssv_cmd_sta	ssvdevice/ssv_cmd.c	/^static int ssv_cmd_sta(struct ssv_softc *sc, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_softc *sc, int argc, char *argv[])
+ssv_cmd_state	smac/p2p.h	/^enum ssv_cmd_state{$/;"	g
+ssv_cmd_submit	ssvdevice/ssv_cmd.c	/^int ssv_cmd_submit(struct ssv_cmd_data *cmd_data, char *cmd)$/;"	f	signature:(struct ssv_cmd_data *cmd_data, char *cmd)
+ssv_cmd_submit	ssvdevice/ssv_cmd.h	/^int ssv_cmd_submit(struct ssv_cmd_data *cmd_data, char *cmd);$/;"	p	signature:(struct ssv_cmd_data *cmd_data, char *cmd)
+ssv_cmd_table	ssvdevice/ssv_cmd.h	/^struct ssv_cmd_table {$/;"	s
+ssv_cmd_table::cmd	ssvdevice/ssv_cmd.h	/^    const char *cmd;$/;"	m	struct:ssv_cmd_table	access:public
+ssv_cmd_table::cmd_func_ptr	ssvdevice/ssv_cmd.h	/^    int (*cmd_func_ptr)(struct ssv_softc *sc, int, char **);$/;"	m	struct:ssv_cmd_table	access:public
+ssv_cmd_table::result_buffer_size	ssvdevice/ssv_cmd.h	/^    const int result_buffer_size;$/;"	m	struct:ssv_cmd_table	access:public
+ssv_cmd_table::usage	ssvdevice/ssv_cmd.h	/^    const char *usage;$/;"	m	struct:ssv_cmd_table	access:public
+ssv_cmd_tool	ssvdevice/ssv_cmd.c	/^static int ssv_cmd_tool(struct ssv_softc *sc, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_softc *sc, int argc, char *argv[])
+ssv_cmd_txgen	ssvdevice/ssv_cmd.c	/^static int ssv_cmd_txgen(struct ssv_softc *sc, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_softc *sc, int argc, char *argv[])
+ssv_cmd_txrx_skb_q	ssvdevice/ssv_cmd.c	/^static int ssv_cmd_txrx_skb_q(struct ssv_softc *sc, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_softc *sc, int argc, char *argv[])
+ssv_cmd_txrxboost	ssvdevice/ssv_cmd.c	/^static int ssv_cmd_txrxboost(struct ssv_softc *sc, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_softc *sc, int argc, char *argv[])
+ssv_cmd_txtput	ssvdevice/ssv_cmd.c	/^static int ssv_cmd_txtput(struct ssv_softc *sc, int argc, char *argv[])$/;"	f	file:	signature:(struct ssv_softc *sc, int argc, char *argv[])
+ssv_cmd_version	ssvdevice/ssv_cmd.c	/^static int ssv_cmd_version (struct ssv_softc *sc, int argc, char *argv[]) {$/;"	f	file:	signature:(struct ssv_softc *sc, int argc, char *argv[])
+ssv_crypt_ccmp	smac/sec_ccmp.c	/^static struct ssv_crypto_ops ssv_crypt_ccmp = {$/;"	v	typeref:struct:ssv_crypto_ops	file:
+ssv_crypt_tkip	smac/sec_tkip.c	/^static struct ssv_crypto_ops ssv_crypt_tkip = {$/;"	v	typeref:struct:ssv_crypto_ops	file:
+ssv_crypt_wep	smac/sec_wep.c	/^static struct ssv_crypto_ops ssv_crypt_wep = {$/;"	v	typeref:struct:ssv_crypto_ops	file:
+ssv_crypto_data	smac/sec.h	/^struct ssv_crypto_data {$/;"	s
+ssv_crypto_data::lock	smac/sec.h	/^    rwlock_t lock;$/;"	m	struct:ssv_crypto_data	access:public
+ssv_crypto_data::ops	smac/sec.h	/^    struct ssv_crypto_ops *ops;$/;"	m	struct:ssv_crypto_data	typeref:struct:ssv_crypto_data::ssv_crypto_ops	access:public
+ssv_crypto_data::priv	smac/sec.h	/^    void *priv;$/;"	m	struct:ssv_crypto_data	access:public
+ssv_crypto_ops	smac/sec.h	/^struct ssv_crypto_ops {$/;"	s
+ssv_crypto_ops::decrypt_mpdu	smac/sec.h	/^ int (*decrypt_mpdu) (struct sk_buff * skb, int hdr_len, void *priv);$/;"	m	struct:ssv_crypto_ops	access:public
+ssv_crypto_ops::decrypt_msdu	smac/sec.h	/^ int (*decrypt_msdu) (struct sk_buff * skb, int keyidx, int hdr_len,$/;"	m	struct:ssv_crypto_ops	access:public
+ssv_crypto_ops::decrypt_prepare	smac/sec.h	/^ int (*decrypt_prepare) (struct sk_buff * skb, int hdr_len, void *priv);$/;"	m	struct:ssv_crypto_ops	access:public
+ssv_crypto_ops::deinit	smac/sec.h	/^ void (*deinit) (void *priv);$/;"	m	struct:ssv_crypto_ops	access:public
+ssv_crypto_ops::encrypt_mpdu	smac/sec.h	/^ int (*encrypt_mpdu) (struct sk_buff * skb, int hdr_len, void *priv);$/;"	m	struct:ssv_crypto_ops	access:public
+ssv_crypto_ops::encrypt_msdu	smac/sec.h	/^ int (*encrypt_msdu) (struct sk_buff * skb, int hdr_len, void *priv);$/;"	m	struct:ssv_crypto_ops	access:public
+ssv_crypto_ops::encrypt_prepare	smac/sec.h	/^ int (*encrypt_prepare) (struct sk_buff * skb, int hdr_len, void *priv);$/;"	m	struct:ssv_crypto_ops	access:public
+ssv_crypto_ops::extra_mpdu_postfix_len	smac/sec.h	/^ int extra_mpdu_prefix_len, extra_mpdu_postfix_len;$/;"	m	struct:ssv_crypto_ops	access:public
+ssv_crypto_ops::extra_mpdu_prefix_len	smac/sec.h	/^ int extra_mpdu_prefix_len, extra_mpdu_postfix_len;$/;"	m	struct:ssv_crypto_ops	access:public
+ssv_crypto_ops::extra_msdu_postfix_len	smac/sec.h	/^ int extra_msdu_prefix_len, extra_msdu_postfix_len;$/;"	m	struct:ssv_crypto_ops	access:public
+ssv_crypto_ops::extra_msdu_prefix_len	smac/sec.h	/^ int extra_msdu_prefix_len, extra_msdu_postfix_len;$/;"	m	struct:ssv_crypto_ops	access:public
+ssv_crypto_ops::get_flags	smac/sec.h	/^ unsigned long (*get_flags) (void *priv);$/;"	m	struct:ssv_crypto_ops	access:public
+ssv_crypto_ops::get_key	smac/sec.h	/^ int (*get_key) (void *key, int len, u8 * seq, void *priv);$/;"	m	struct:ssv_crypto_ops	access:public
+ssv_crypto_ops::init	smac/sec.h	/^ void *(*init) (int keyidx);$/;"	m	struct:ssv_crypto_ops	access:public
+ssv_crypto_ops::list	smac/sec.h	/^ struct list_head list;$/;"	m	struct:ssv_crypto_ops	typeref:struct:ssv_crypto_ops::list_head	access:public
+ssv_crypto_ops::name	smac/sec.h	/^ const char *name;$/;"	m	struct:ssv_crypto_ops	access:public
+ssv_crypto_ops::print_stats	smac/sec.h	/^ char *(*print_stats) (char *p, void *priv);$/;"	m	struct:ssv_crypto_ops	access:public
+ssv_crypto_ops::set_flags	smac/sec.h	/^ unsigned long (*set_flags) (unsigned long flags, void *priv);$/;"	m	struct:ssv_crypto_ops	access:public
+ssv_crypto_ops::set_key	smac/sec.h	/^ int (*set_key) (void *key, int len, u8 * seq, void *priv);$/;"	m	struct:ssv_crypto_ops	access:public
+ssv_crypto_ops::set_tx_pn	smac/sec.h	/^ int (*set_tx_pn) (u8 * seq, void *priv);$/;"	m	struct:ssv_crypto_ops	access:public
+ssv_crypto_wpi	smac/sec_wpi.c	/^static struct ssv_crypto_ops ssv_crypto_wpi = {$/;"	v	typeref:struct:ssv_crypto_ops	file:
+ssv_dbg_log	smac/dev.h	/^struct ssv_dbg_log {$/;"	s
+ssv_dbg_log::data	smac/dev.h	/^ char *data;$/;"	m	struct:ssv_dbg_log	access:public
+ssv_dbg_log::end	smac/dev.h	/^ char *end;$/;"	m	struct:ssv_dbg_log	access:public
+ssv_dbg_log::size	smac/dev.h	/^ int size;$/;"	m	struct:ssv_dbg_log	access:public
+ssv_dbg_log::tail	smac/dev.h	/^ char *tail;$/;"	m	struct:ssv_dbg_log	access:public
+ssv_dbg_log::top	smac/dev.h	/^ char *top;$/;"	m	struct:ssv_dbg_log	access:public
+ssv_dbg_log::totalsize	smac/dev.h	/^ int totalsize;$/;"	m	struct:ssv_dbg_log	access:public
+ssv_dbg_phy_len	ssvdevice/ssv_cmd.c	/^EXPORT_SYMBOL(ssv_dbg_phy_len);$/;"	v
+ssv_dbg_phy_len	ssvdevice/ssv_cmd.c	/^u32 ssv_dbg_phy_len = 0;$/;"	v
+ssv_dbg_phy_table	ssvdevice/ssv_cmd.c	/^EXPORT_SYMBOL(ssv_dbg_phy_table);$/;"	v
+ssv_dbg_phy_table	ssvdevice/ssv_cmd.c	/^void *ssv_dbg_phy_table = NULL;$/;"	v
+ssv_dbg_rf_len	ssvdevice/ssv_cmd.c	/^EXPORT_SYMBOL(ssv_dbg_rf_len);$/;"	v
+ssv_dbg_rf_len	ssvdevice/ssv_cmd.c	/^u32 ssv_dbg_rf_len = 0;$/;"	v
+ssv_dbg_rf_table	ssvdevice/ssv_cmd.c	/^EXPORT_SYMBOL(ssv_dbg_rf_table);$/;"	v
+ssv_dbg_rf_table	ssvdevice/ssv_cmd.c	/^void *ssv_dbg_rf_table = NULL;$/;"	v
+ssv_debug_skb_timestamp	include/ssv6xxx_common.h	/^enum ssv_debug_skb_timestamp$/;"	g
+ssv_deinit_cli	smac/ssv_cli.h	/^int ssv_deinit_cli (const char *dev_name, struct ssv_cmd_data *cmd_data);$/;"	p	signature:(const char *dev_name, struct ssv_cmd_data *cmd_data)
+ssv_deinit_cli	ssvdevice/ssvdevice.c	/^EXPORT_SYMBOL(ssv_deinit_cli);$/;"	v
+ssv_deinit_cli	ssvdevice/ssvdevice.c	/^int ssv_deinit_cli (const char *dev_name, struct ssv_cmd_data *cmd_data)$/;"	f	signature:(const char *dev_name, struct ssv_cmd_data *cmd_data)
+ssv_devicetype	ssvdevice/ssvdevice.c	/^EXPORT_SYMBOL(ssv_devicetype);$/;"	v
+ssv_devicetype	ssvdevice/ssvdevice.c	/^u32 ssv_devicetype = 0;$/;"	v
+ssv_encrypt_task_list	smac/dev.h	/^struct ssv_encrypt_task_list {$/;"	s
+ssv_encrypt_task_list::cpu_no	smac/dev.h	/^    u32 cpu_no;$/;"	m	struct:ssv_encrypt_task_list	access:public
+ssv_encrypt_task_list::cpu_offline	smac/dev.h	/^    volatile int cpu_offline;$/;"	m	struct:ssv_encrypt_task_list	access:public
+ssv_encrypt_task_list::encrypt_task	smac/dev.h	/^    struct task_struct* encrypt_task;$/;"	m	struct:ssv_encrypt_task_list	typeref:struct:ssv_encrypt_task_list::task_struct	access:public
+ssv_encrypt_task_list::encrypt_wait_q	smac/dev.h	/^    wait_queue_head_t encrypt_wait_q;$/;"	m	struct:ssv_encrypt_task_list	access:public
+ssv_encrypt_task_list::list	smac/dev.h	/^    struct list_head list;$/;"	m	struct:ssv_encrypt_task_list	typeref:struct:ssv_encrypt_task_list::list_head	access:public
+ssv_encrypt_task_list::paused	smac/dev.h	/^    volatile int paused;$/;"	m	struct:ssv_encrypt_task_list	access:public
+ssv_encrypt_task_list::running	smac/dev.h	/^    volatile int running;$/;"	m	struct:ssv_encrypt_task_list	access:public
+ssv_encrypt_task_list::started	smac/dev.h	/^    volatile int started;$/;"	m	struct:ssv_encrypt_task_list	access:public
+ssv_enter_airkiss_mode	smartlink/airkiss.c	/^static char *ssv_enter_airkiss_mode = "cd %s\/scripts\/ && .\/startsmartlink.sh";$/;"	v	file:
+ssv_enter_qqlink_mode	smartlink/qqlink.c	/^static char *ssv_enter_qqlink_mode = "cd %s\/scripts\/ && .\/startsmartlink.sh";$/;"	v	file:
+ssv_firmware_version	include/ssv_firmware_version.h	/^static u32 ssv_firmware_version = 17215;$/;"	v
+ssv_flash_config	smac/dev.h	/^struct ssv_flash_config {$/;"	s
+ssv_flash_config::a_band_pa_bias0	smac/dev.h	/^    u32 a_band_pa_bias0;$/;"	m	struct:ssv_flash_config	access:public
+ssv_flash_config::a_band_pa_bias1	smac/dev.h	/^    u32 a_band_pa_bias1;$/;"	m	struct:ssv_flash_config	access:public
+ssv_flash_config::band_gain_high_boundary	smac/dev.h	/^    u8 band_gain_high_boundary;$/;"	m	struct:ssv_flash_config	access:public
+ssv_flash_config::band_gain_low_boundary	smac/dev.h	/^    u8 band_gain_low_boundary;$/;"	m	struct:ssv_flash_config	access:public
+ssv_flash_config::band_gain_tempe_state	smac/dev.h	/^    u8 band_gain_tempe_state;$/;"	m	struct:ssv_flash_config	access:public
+ssv_flash_config::chan	smac/dev.h	/^    int chan;$/;"	m	struct:ssv_flash_config	access:public
+ssv_flash_config::dcdc	smac/dev.h	/^    u16 dcdc;$/;"	m	struct:ssv_flash_config	access:public
+ssv_flash_config::exist	smac/dev.h	/^    bool exist;$/;"	m	struct:ssv_flash_config	access:public
+ssv_flash_config::g_band_pa_bias0	smac/dev.h	/^    u32 g_band_pa_bias0;$/;"	m	struct:ssv_flash_config	access:public
+ssv_flash_config::g_band_pa_bias1	smac/dev.h	/^    u32 g_band_pa_bias1;$/;"	m	struct:ssv_flash_config	access:public
+ssv_flash_config::ht_config	smac/dev.h	/^    struct ssv_tempe_table ht_config;$/;"	m	struct:ssv_flash_config	typeref:struct:ssv_flash_config::ssv_tempe_table	access:public
+ssv_flash_config::lt_config	smac/dev.h	/^    struct ssv_tempe_table lt_config;$/;"	m	struct:ssv_flash_config	typeref:struct:ssv_flash_config::ssv_tempe_table	access:public
+ssv_flash_config::padpd	smac/dev.h	/^    u16 padpd;$/;"	m	struct:ssv_flash_config	access:public
+ssv_flash_config::rate_delta	smac/dev.h	/^    u8 rate_delta[13];$/;"	m	struct:ssv_flash_config	access:public
+ssv_flash_config::rt_config	smac/dev.h	/^    struct ssv_tempe_table rt_config;$/;"	m	struct:ssv_flash_config	typeref:struct:ssv_flash_config::ssv_tempe_table	access:public
+ssv_flash_config::xtal_offset_high_boundary	smac/dev.h	/^    u8 xtal_offset_high_boundary;$/;"	m	struct:ssv_flash_config	access:public
+ssv_flash_config::xtal_offset_low_boundary	smac/dev.h	/^    u8 xtal_offset_low_boundary;$/;"	m	struct:ssv_flash_config	access:public
+ssv_flash_config::xtal_offset_tempe_state	smac/dev.h	/^    u8 xtal_offset_tempe_state;$/;"	m	struct:ssv_flash_config	access:public
+ssv_hal_ops	smac/dev.h	/^struct ssv_hal_ops {$/;"	s
+ssv_hal_ops::add_ampdu_txinfo	smac/dev.h	/^    void (*add_ampdu_txinfo)(struct ssv_softc *sc, struct sk_buff *ampdu_skb);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::add_fw_wsid	smac/dev.h	/^    void (*add_fw_wsid)(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv,$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::add_txinfo	smac/dev.h	/^    void (*add_txinfo) (struct ssv_softc *sc, struct sk_buff *skb);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::adj_config	smac/dev.h	/^ void (*adj_config)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::alloc_hw	smac/dev.h	/^    struct ssv_hw * (*alloc_hw)(void);$/;"	m	struct:ssv_hal_ops	typeref:struct:ssv_hal_ops::alloc_hw	access:public
+ssv_hal_ops::alloc_pbuf	smac/dev.h	/^    u32 (*alloc_pbuf)(struct ssv_softc *sc, int size, int type);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::ampdu_auto_crc_en	smac/dev.h	/^    void (*ampdu_auto_crc_en)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::ampdu_ba_handler	smac/dev.h	/^    void (*ampdu_ba_handler)(struct ieee80211_hw *hw, struct sk_buff *skb, u32 tx_pkt_run_no);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::ampdu_max_transmit_length	smac/dev.h	/^    int (*ampdu_max_transmit_length)(struct ssv_softc *sc, struct sk_buff *skb, int rate_idx);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::ampdu_rx_start	smac/dev.h	/^    int (*ampdu_rx_start)(struct ieee80211_hw *hw, struct ieee80211_vif *vif, struct ieee80211_sta *sta,$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::auto_gen_nullpkt	smac/dev.h	/^    int (*auto_gen_nullpkt)(struct ssv_hw *sh, int hwq);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::beacon_enable	smac/dev.h	/^    bool (*beacon_enable)(struct ssv_softc *sc, bool bEnable);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::beacon_get_valid_cfg	smac/dev.h	/^    enum ssv6xxx_beacon_type (*beacon_get_valid_cfg)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	typeref:enum:ssv_hal_ops::beacon_get_valid_cfg	access:public
+ssv_hal_ops::beacon_loss_config	smac/dev.h	/^ void (*beacon_loss_config)(struct ssv_hw *sh, u16 beacon_interval, const u8 *bssid);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::beacon_loss_disable	smac/dev.h	/^ void (*beacon_loss_disable)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::beacon_loss_enable	smac/dev.h	/^ void (*beacon_loss_enable)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::burst_read_reg	smac/dev.h	/^    int (*burst_read_reg)(struct ssv_hw *sh, u32 *addr, u32 *buf, u8 reg_amount);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::burst_write_reg	smac/dev.h	/^    int (*burst_write_reg)(struct ssv_hw *sh, u32 *addr, u32 *buf, u8 reg_amount);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::chg_clk_src	smac/dev.h	/^    int (*chg_clk_src)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::chg_ipd_phyinfo	smac/dev.h	/^    void (*chg_ipd_phyinfo)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::chg_pad_setting	smac/dev.h	/^    int (*chg_pad_setting)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::chk_dual_vif_chg_rx_flow	smac/dev.h	/^    void (*chk_dual_vif_chg_rx_flow)(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::chk_if_support_hw_bssid	smac/dev.h	/^    bool (*chk_if_support_hw_bssid)(struct ssv_softc *sc, int vif_idx);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::chk_lpbk_rx_rate_desc	smac/dev.h	/^    int (*chk_lpbk_rx_rate_desc)(struct ssv_hw *sh, struct sk_buff *skb);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::cmd_cali	smac/dev.h	/^    void (*cmd_cali)(struct ssv_hw *sh, int argc, char *argv[]);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::cmd_cci	smac/dev.h	/^    void (*cmd_cci)(struct ssv_hw *sh, int argc, char *argv[]);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::cmd_efuse	smac/dev.h	/^    void (*cmd_efuse)(struct ssv_hw *sh, int argc, char *argv[]);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::cmd_hwinfo	smac/dev.h	/^    void (*cmd_hwinfo)(struct ssv_hw *sh, int argc, char *argv[]);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::cmd_hwq_limit	smac/dev.h	/^    void (*cmd_hwq_limit)(struct ssv_hw *sh, int argc, char *argv[]);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::cmd_loopback	smac/dev.h	/^    void (*cmd_loopback)(struct ssv_hw *sh, int argc, char *argv[]);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::cmd_loopback_setup_env	smac/dev.h	/^    void (*cmd_loopback_setup_env)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::cmd_loopback_start	smac/dev.h	/^    void (*cmd_loopback_start)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::cmd_mib	smac/dev.h	/^    void (*cmd_mib)(struct ssv_softc *sc, int argc, char *argv[]);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::cmd_power_saving	smac/dev.h	/^    void (*cmd_power_saving)(struct ssv_softc *sc, int argc, char *argv[]);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::cmd_rc	smac/dev.h	/^    void (*cmd_rc)(struct ssv_hw *sh, int argc, char *argv[]);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::cmd_rf	smac/dev.h	/^    void (*cmd_rf)(struct ssv_hw *sh, int argc, char *argv[]);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::cmd_spectrum	smac/dev.h	/^    void (*cmd_spectrum)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::cmd_txgen	smac/dev.h	/^    void (*cmd_txgen)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::del_fw_wsid	smac/dev.h	/^    void (*del_fw_wsid)(struct ssv_softc *sc, struct ieee80211_sta *sta,$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::del_hw_wsid	smac/dev.h	/^    void (*del_hw_wsid)(struct ssv_softc *sc, int hw_wsid);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::detach_usb_hci	smac/dev.h	/^    void (*detach_usb_hci)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::disable_fw_wsid	smac/dev.h	/^    void (*disable_fw_wsid)(struct ssv_softc *sc, int key_idx,$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::disable_usb_acc	smac/dev.h	/^    void (*disable_usb_acc)(struct ssv_softc *sc, u8 epnum);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::do_iq_cal	smac/dev.h	/^    int (*do_iq_cal)(struct ssv_hw *sh, struct ssv6xxx_iqk_cfg *p_cfg);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::do_temperature_compensation	smac/dev.h	/^    void (*do_temperature_compensation)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::dpd_enable	smac/dev.h	/^    void (*dpd_enable)(struct ssv_hw *sh, bool val);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::dump_decision	smac/dev.h	/^    bool (*dump_decision)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::dump_mib_rx_phy	smac/dev.h	/^    void (*dump_mib_rx_phy)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::dump_phy_reg	smac/dev.h	/^    bool (*dump_phy_reg)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::dump_rf_reg	smac/dev.h	/^    bool (*dump_rf_reg)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::dump_wsid	smac/dev.h	/^    bool (*dump_wsid)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::edca_enable	smac/dev.h	/^ void (*edca_enable)(struct ssv_hw *sh, bool val);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::edca_stat	smac/dev.h	/^ void (*edca_stat)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::enable_fw_wsid	smac/dev.h	/^    void (*enable_fw_wsid)(struct ssv_softc *sc, struct ieee80211_sta *sta,$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::enable_usb_acc	smac/dev.h	/^    void (*enable_usb_acc)(struct ssv_softc *sc, u8 epnum);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::fill_beacon	smac/dev.h	/^    void (*fill_beacon)(struct ssv_softc *sc, u32 regaddr, struct sk_buff *skb);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::fill_beacon_tx_desc	smac/dev.h	/^    void (*fill_beacon_tx_desc)(struct ssv_softc *sc, struct sk_buff* beacon_skb);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::fill_lpbk_tx_desc	smac/dev.h	/^    void (*fill_lpbk_tx_desc)(struct sk_buff *skb, int security, unsigned char rate);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::flash_read_all_map	smac/dev.h	/^    void (*flash_read_all_map)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::free_pbuf	smac/dev.h	/^    bool (*free_pbuf)(struct ssv_softc *sc, u32 pbuf_addr);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::get_bcn_ongoing	smac/dev.h	/^    bool (*get_bcn_ongoing)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::get_chip_id	smac/dev.h	/^    void (*get_chip_id)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::get_ffout_cnt	smac/dev.h	/^ u32 (*get_ffout_cnt)(u32 value, int tag);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::get_fw_name	smac/dev.h	/^    void (*get_fw_name)(u8 *fw_name);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::get_fw_version	smac/dev.h	/^    void (*get_fw_version)(struct ssv_hw *sh, u32 *regval);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::get_ic_time_tag	smac/dev.h	/^    u64 (*get_ic_time_tag)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::get_in_ffcnt	smac/dev.h	/^ u32 (*get_in_ffcnt)(u32 value, int tag);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::get_mrx_mode	smac/dev.h	/^    void (*get_mrx_mode)(struct ssv_hw *sh, u32 *regval);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::get_phy_table_size	smac/dev.h	/^    u32 (*get_phy_table_size)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::get_rd_id_adr	smac/dev.h	/^    void (*get_rd_id_adr)(u32 *id_base_address);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::get_rf_table_size	smac/dev.h	/^    u32 (*get_rf_table_size)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::get_rx_desc_ctype	smac/dev.h	/^    u32 (*get_rx_desc_ctype)(struct sk_buff *skb);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::get_rx_desc_hdr_offset	smac/dev.h	/^    int (*get_rx_desc_hdr_offset)(struct sk_buff *skb);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::get_rx_desc_info	smac/dev.h	/^    void (*get_rx_desc_info)(struct sk_buff *skb, u32 *packet_len, u32 *ctype,$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::get_rx_desc_length	smac/dev.h	/^    int (*get_rx_desc_length)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::get_rx_desc_mng_used	smac/dev.h	/^    u32 (*get_rx_desc_mng_used)(struct sk_buff *skb);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::get_rx_desc_rate_idx	smac/dev.h	/^    u32 (*get_rx_desc_rate_idx)(struct sk_buff *skb);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::get_rx_desc_size	smac/dev.h	/^    int (*get_rx_desc_size)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::get_rx_desc_wsid	smac/dev.h	/^    u32 (*get_rx_desc_wsid)(struct sk_buff *skb);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::get_sec_decode_err	smac/dev.h	/^    int (*get_sec_decode_err)(struct sk_buff *skb, bool *mic_err, bool *decode_err);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::get_tx_desc_ctype	smac/dev.h	/^    int (*get_tx_desc_ctype)(struct sk_buff *skb );$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::get_tx_desc_reason	smac/dev.h	/^    int (*get_tx_desc_reason)(struct sk_buff *skb );$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::get_tx_desc_size	smac/dev.h	/^    int (*get_tx_desc_size)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::get_tx_desc_txq_idx	smac/dev.h	/^    int (*get_tx_desc_txq_idx)(struct sk_buff *skb );$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::get_wsid	smac/dev.h	/^    int (*get_wsid)(struct ssv_softc *sc, struct ieee80211_vif *vif,$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::group_wpa_use_hw_cipher	smac/dev.h	/^    bool (*group_wpa_use_hw_cipher)(struct ssv_softc *sc,$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::hw_crypto_key_write_wep	smac/dev.h	/^    int (*hw_crypto_key_write_wep) (struct ssv_softc *sc, struct ieee80211_key_conf *keyconf, u8 algorithm, struct ssv_vif_info *vif_info);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::if_chk_mac2	smac/dev.h	/^    bool (*if_chk_mac2)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::init_ch_cfg	smac/dev.h	/^    void (*init_ch_cfg)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::init_gpio_cfg	smac/dev.h	/^    void (*init_gpio_cfg)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::init_hw_sec_phy_table	smac/dev.h	/^    int (*init_hw_sec_phy_table)(struct ssv_softc *sc);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::init_iqk	smac/dev.h	/^    void (*init_iqk)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::init_mac	smac/dev.h	/^    int (*init_mac)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::init_pll	smac/dev.h	/^    void (*init_pll)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::init_rx_cfg	smac/dev.h	/^    void (*init_rx_cfg)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::init_tx_cfg	smac/dev.h	/^    void (*init_tx_cfg)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::is_legacy_rate	smac/dev.h	/^    bool (*is_legacy_rate)(struct ssv_softc *sc, struct sk_buff *skb);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::is_rx_aggr	smac/dev.h	/^    bool (*is_rx_aggr)(struct sk_buff *skb);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::jump_to_rom	smac/dev.h	/^    int (*jump_to_rom)(struct ssv_softc *sc);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::load_fw_disable_mcu	smac/dev.h	/^ int (*load_fw_disable_mcu)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::load_fw_enable_mcu	smac/dev.h	/^ void (*load_fw_enable_mcu)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::load_fw_get_status	smac/dev.h	/^ int (*load_fw_get_status)(struct ssv_hw *sh, u32 *status);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::load_fw_post_config_device	smac/dev.h	/^ void (*load_fw_post_config_device)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::load_fw_pre_config_device	smac/dev.h	/^ void (*load_fw_pre_config_device)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::load_fw_set_status	smac/dev.h	/^ int (*load_fw_set_status)(struct ssv_hw *sh, u32 status);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::load_phy_table	smac/dev.h	/^    void (*load_phy_table)(ssv_cabrio_reg **phy_table);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::load_rf_table	smac/dev.h	/^    void (*load_rf_table)(ssv_cabrio_reg **rf_table);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::need_sw_cipher	smac/dev.h	/^ bool (*need_sw_cipher)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::nullfun_frame_filter	smac/dev.h	/^    bool (*nullfun_frame_filter)(struct sk_buff *skb);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::pairwise_wpa_use_hw_cipher	smac/dev.h	/^    bool (*pairwise_wpa_use_hw_cipher)(struct ssv_softc *sc,$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::phy_enable	smac/dev.h	/^    void (*phy_enable)(struct ssv_hw *sh, bool val);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::pll_chk	smac/dev.h	/^    void (*pll_chk)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::pmu_awake	smac/dev.h	/^ void (*pmu_awake)(struct ssv_softc *sc);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::put_mic_space_for_hw_ccmp_encrypt	smac/dev.h	/^    bool (*put_mic_space_for_hw_ccmp_encrypt) (struct ssv_softc *sc, struct sk_buff *skb);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::rate_report_handler	smac/dev.h	/^ void (*rate_report_handler)(struct ssv_softc *sc, struct sk_buff *skb, bool *no_ba_result);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::rc_algorithm	smac/dev.h	/^ void (*rc_algorithm)(struct ssv_softc *sc);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::rc_ht_sta_current_rate_is_cck	smac/dev.h	/^ bool (*rc_ht_sta_current_rate_is_cck)(struct ieee80211_sta *sta);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::rc_ht_update_rate	smac/dev.h	/^ s32 (*rc_ht_update_rate)(struct sk_buff *skb, struct ssv_softc *sc, struct fw_rc_retry_params *ar);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::rc_legacy_bitrate_to_rate_desc	smac/dev.h	/^ void (*rc_legacy_bitrate_to_rate_desc)(int bitrate, u8 *drate);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::rc_mac80211_rate_idx	smac/dev.h	/^    void (*rc_mac80211_rate_idx)(struct ssv_softc *sc,$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::rc_process_rate_report	smac/dev.h	/^ void (*rc_process_rate_report)(struct ssv_softc *sc, struct sk_buff *skb);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::rc_rx_data_handler	smac/dev.h	/^ void (*rc_rx_data_handler)(struct ssv_softc *sc, struct sk_buff *skb, u32 rate_index);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::rc_update_basic_rate	smac/dev.h	/^ void (*rc_update_basic_rate)(struct ssv_softc *sc, u32 basic_rates);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::read_efuse	smac/dev.h	/^    u8 (*read_efuse)(struct ssv_hw *sh, u8 *pbuf);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::read_ffout_cnt	smac/dev.h	/^    void (*read_ffout_cnt)(struct ssv_hw *sh, u32 *value, u32 *value1, u32 *value2);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::read_id_len_threshold	smac/dev.h	/^    void (*read_id_len_threshold)(struct ssv_hw *sh, u32 *tx_len, u32 *rx_len);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::read_in_ffcnt	smac/dev.h	/^    void (*read_in_ffcnt)(struct ssv_hw *sh, u32 *value, u32 *value1);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::read_tag_status	smac/dev.h	/^    void (*read_tag_status)(struct ssv_hw *sh, u32 *ava_status);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::readrg_hci_inq_info	smac/dev.h	/^    void (*readrg_hci_inq_info)(struct ssv_hw *sh, int *hci_used_id, int *tx_use_page);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::readrg_txq_info	smac/dev.h	/^    bool (*readrg_txq_info)(struct ssv_hw *sh, u32 *txq_info, int *hci_used_id);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::readrg_txq_info2	smac/dev.h	/^    bool (*readrg_txq_info2)(struct ssv_hw *sh, u32 *txq_info2, int *hci_used_id);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::recover_scan_cci_setting	smac/dev.h	/^    void (*recover_scan_cci_setting)(struct ssv_softc *sc);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::reset_cpu	smac/dev.h	/^ int (*reset_cpu)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::reset_mib_phy	smac/dev.h	/^    void (*reset_mib_phy)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::reset_sysplf	smac/dev.h	/^    void (*reset_sysplf)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::restore_rx_flow	smac/dev.h	/^    void (*restore_rx_flow)(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv, struct ieee80211_sta *sta);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::restore_trap_reason	smac/dev.h	/^ void (*restore_trap_reason)(struct ssv_softc *sc);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::save_clear_trap_reason	smac/dev.h	/^ void (*save_clear_trap_reason)(struct ssv_softc *sc);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::save_default_ipd_chcfg	smac/dev.h	/^    void (*save_default_ipd_chcfg)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::save_hw_status	smac/dev.h	/^    void (*save_hw_status)(struct ssv_softc *sc);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::send_tx_poll_cmd	smac/dev.h	/^    void (*send_tx_poll_cmd)(struct ssv_hw *sh, u32 type);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::set_80211_hw_rate_config	smac/dev.h	/^ void (*set_80211_hw_rate_config)(struct ssv_softc *sc);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::set_aes_tkip_hw_crypto_group_key	smac/dev.h	/^    void (*set_aes_tkip_hw_crypto_group_key) (struct ssv_softc *sc, struct ssv_vif_info *vif_info,$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::set_beacon_id_dtim	smac/dev.h	/^    void (*set_beacon_id_dtim)(struct ssv_softc *sc,$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::set_beacon_info	smac/dev.h	/^    void (*set_beacon_info)(struct ssv_hw *sh, u8 beacon_interval, u8 dtim_cnt);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::set_beacon_reg_lock	smac/dev.h	/^    void (*set_beacon_reg_lock)(struct ssv_hw *sh, bool val);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::set_bssid	smac/dev.h	/^    int (*set_bssid)(struct ssv_hw *sh, u8 *bssid, int vif_idx);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::set_channel	smac/dev.h	/^    int (*set_channel)(struct ssv_softc *sc, struct ieee80211_channel *channel, enum nl80211_channel_type);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::set_dur_burst_sifs_g	smac/dev.h	/^    void (*set_dur_burst_sifs_g)(struct ssv_hw *sh, u32 val);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::set_dur_slot	smac/dev.h	/^    void (*set_dur_slot)(struct ssv_hw *sh, u32 val);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::set_fw_hwwsid_sec_type	smac/dev.h	/^    void (*set_fw_hwwsid_sec_type)(struct ssv_softc *sc, struct ieee80211_sta *sta,$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::set_group_cipher_type	smac/dev.h	/^    void (*set_group_cipher_type)(struct ssv_hw *sh, struct ssv_vif_priv_data *vif_priv, u8 cipher);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::set_halt_mngq_util_dtim	smac/dev.h	/^    void (*set_halt_mngq_util_dtim)(struct ssv_hw *sh, bool val);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::set_hw_wsid	smac/dev.h	/^    void (*set_hw_wsid)(struct ssv_softc *sc, struct ieee80211_vif *vif,$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::set_macaddr	smac/dev.h	/^    int (*set_macaddr)(struct ssv_hw *sh, int vif_idx);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::set_mrx_mode	smac/dev.h	/^    void (*set_mrx_mode)(struct ssv_hw *sh, u32 regval);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::set_on3_enable	smac/dev.h	/^    void (*set_on3_enable)(struct ssv_hw *sh, bool val);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::set_op_mode	smac/dev.h	/^    void (*set_op_mode)(struct ssv_hw *sh, u32 opmode, int vif_idx);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::set_pairwise_cipher_type	smac/dev.h	/^    void (*set_pairwise_cipher_type)(struct ssv_hw *sh, u8 cipher, u8 wsid);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::set_phy_mode	smac/dev.h	/^    void (*set_phy_mode)(struct ssv_hw *sh, bool val);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::set_pll_phy_rf	smac/dev.h	/^    int (*set_pll_phy_rf)(struct ssv_hw *sh, ssv_cabrio_reg *rf_tbl, ssv_cabrio_reg *phy_tbl);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::set_qos_enable	smac/dev.h	/^    void (*set_qos_enable)(struct ssv_hw *sh, bool val);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::set_replay_ignore	smac/dev.h	/^    void (*set_replay_ignore)(struct ssv_hw *sh, u8 ignore);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::set_rf_enable	smac/dev.h	/^    bool (*set_rf_enable)(struct ssv_hw *sh, bool val);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::set_rx_ba	smac/dev.h	/^    void (*set_rx_ba)(struct ssv_hw *sh, bool on, u8 *ta,$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::set_rx_ctrl_flow	smac/dev.h	/^    int (*set_rx_ctrl_flow)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::set_rx_flow	smac/dev.h	/^    int (*set_rx_flow)(struct ssv_hw *sh, enum ssv_rx_flow type, u32 rxflow);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::set_sifs	smac/dev.h	/^    void (*set_sifs)(struct ssv_hw *sh, int band);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::set_sram_mode	smac/dev.h	/^ void (*set_sram_mode)(struct ssv_hw *sh, enum SSV_SRAM_MODE mode);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::set_usb_lpm	smac/dev.h	/^    void (*set_usb_lpm)(struct ssv_softc *sc, u8 enable);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::set_wep_hw_crypto_key	smac/dev.h	/^    void (*set_wep_hw_crypto_key)(struct ssv_softc *sc, struct ssv_sta_info *sta_info, struct ssv_vif_priv_data *vif_priv);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::set_wmm_param	smac/dev.h	/^    void (*set_wmm_param)(struct ssv_softc *sc,$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::store_wep_key	smac/dev.h	/^    void (*store_wep_key) (struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv, struct ssv_sta_priv_data *sta_priv,$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::support_iqk_cmd	smac/dev.h	/^    bool (*support_iqk_cmd)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::tx_rate_update	smac/dev.h	/^    void (*tx_rate_update)(struct ssv_softc *sc, struct sk_buff *skb);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::txtput_set_desc	smac/dev.h	/^    void (*txtput_set_desc)(struct ssv_hw *sh, struct sk_buff *skb );$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::update_ampdu_txinfo	smac/dev.h	/^    void (*update_ampdu_txinfo)(struct ssv_softc *sc, struct sk_buff *ampdu_skb);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::update_cfg_hw_patch	smac/dev.h	/^    void (*update_cfg_hw_patch)(struct ssv_hw *sh, ssv_cabrio_reg *rf_table,$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::update_decision_table	smac/dev.h	/^    int (*update_decision_table)(struct ssv_softc *sc);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::update_decision_table_6	smac/dev.h	/^    void (*update_decision_table_6)(struct ssv_hw *sh, u32 val);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::update_efuse_setting	smac/dev.h	/^    int (*update_efuse_setting)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::update_hw_config	smac/dev.h	/^    void (*update_hw_config)(struct ssv_hw *sh, ssv_cabrio_reg *rf_table,$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::update_null_func_txinfo	smac/dev.h	/^    int (*update_null_func_txinfo)(struct ssv_softc *sc, struct ieee80211_sta *sta, struct sk_buff *skb);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::update_page_id	smac/dev.h	/^    void (*update_page_id)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::update_product_hw_setting	smac/dev.h	/^    void (*update_product_hw_setting)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::update_rf_pwr	smac/dev.h	/^    void (*update_rf_pwr)(struct ssv_softc *sc);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::update_rxstatus	smac/dev.h	/^    void (*update_rxstatus)(struct ssv_softc *sc,$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::update_scan_cci_setting	smac/dev.h	/^    void (*update_scan_cci_setting)(struct ssv_softc *sc);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::update_txinfo	smac/dev.h	/^    void (*update_txinfo)(struct ssv_softc *sc, struct sk_buff *skb);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::update_txq_mask	smac/dev.h	/^    void (*update_txq_mask)(struct ssv_hw *sh, u32 txq_mask);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::use_hw_encrypt	smac/dev.h	/^    bool (*use_hw_encrypt)(int cipher, struct ssv_softc *sc,$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::wait_usb_rom_ready	smac/dev.h	/^    void (*wait_usb_rom_ready)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::wep_use_hw_cipher	smac/dev.h	/^    bool (*wep_use_hw_cipher)(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::write_efuse	smac/dev.h	/^    void (*write_efuse)(struct ssv_hw *sh, u8 *data, u8 data_length);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::write_group_key_to_hw	smac/dev.h	/^    int (*write_group_key_to_hw) (struct ssv_softc *sc, int index, u8 algorithm, const u8 *key, int key_len,$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::write_group_keyidx_to_hw	smac/dev.h	/^    void (*write_group_keyidx_to_hw)(struct ssv_hw *sh, struct ssv_vif_priv_data *vif_priv, int key_idx);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::write_key_to_hw	smac/dev.h	/^    void (*write_key_to_hw)(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv,$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::write_mac_ini	smac/dev.h	/^    int (*write_mac_ini)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::write_pairwise_key_to_hw	smac/dev.h	/^    int (*write_pairwise_key_to_hw) (struct ssv_softc *sc, int index, u8 algorithm, const u8 *key, int key_len,$/;"	m	struct:ssv_hal_ops	access:public
+ssv_hal_ops::write_pairwise_keyidx_to_hw	smac/dev.h	/^    void (*write_pairwise_keyidx_to_hw)(struct ssv_hw *sh, int key_idx, int wsid);$/;"	m	struct:ssv_hal_ops	access:public
+ssv_huw_cmd	hci_wrapper/ssv_huw.h	/^struct ssv_huw_cmd {$/;"	s
+ssv_huw_cmd::in_data	hci_wrapper/ssv_huw.h	/^    u8* in_data;$/;"	m	struct:ssv_huw_cmd	access:public
+ssv_huw_cmd::in_data_len	hci_wrapper/ssv_huw.h	/^    __u32 in_data_len;$/;"	m	struct:ssv_huw_cmd	access:public
+ssv_huw_cmd::out_data	hci_wrapper/ssv_huw.h	/^    u8* out_data;$/;"	m	struct:ssv_huw_cmd	access:public
+ssv_huw_cmd::out_data_len	hci_wrapper/ssv_huw.h	/^    __u32 out_data_len;$/;"	m	struct:ssv_huw_cmd	access:public
+ssv_huw_cmd::padding1	hci_wrapper/ssv_huw.h	/^    __u32 padding1;$/;"	m	struct:ssv_huw_cmd	access:public
+ssv_huw_cmd::padding2	hci_wrapper/ssv_huw.h	/^        __u32 padding2;$/;"	m	struct:ssv_huw_cmd	access:public
+ssv_huw_cmd::response	hci_wrapper/ssv_huw.h	/^    __u32 response;$/;"	m	struct:ssv_huw_cmd	access:public
+ssv_huw_compat_ioctl	hci_wrapper/ssv_huw.c	/^static long ssv_huw_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)$/;"	f	file:	signature:(struct file *filp, unsigned int cmd, unsigned long arg)
+ssv_huw_dev	hci_wrapper/ssv_huw.c	/^struct ssv_huw_dev {$/;"	s	file:
+ssv_huw_dev::bufaddr	hci_wrapper/ssv_huw.c	/^    void *bufaddr;$/;"	m	struct:ssv_huw_dev	file:	access:public
+ssv_huw_dev::chip_id	hci_wrapper/ssv_huw.c	/^    char chip_id[24];$/;"	m	struct:ssv_huw_dev	file:	access:public
+ssv_huw_dev::chip_tag	hci_wrapper/ssv_huw.c	/^    u64 chip_tag;$/;"	m	struct:ssv_huw_dev	file:	access:public
+ssv_huw_dev::dev	hci_wrapper/ssv_huw.c	/^    struct device *dev;$/;"	m	struct:ssv_huw_dev	typeref:struct:ssv_huw_dev::device	file:	access:public
+ssv_huw_dev::funcFocus	hci_wrapper/ssv_huw.c	/^    u8 funcFocus;$/;"	m	struct:ssv_huw_dev	file:	access:public
+ssv_huw_dev::hci	hci_wrapper/ssv_huw.c	/^    struct ssv6xxx_hci_info hci;$/;"	m	struct:ssv_huw_dev	typeref:struct:ssv_huw_dev::ssv6xxx_hci_info	file:	access:public
+ssv_huw_dev::priv	hci_wrapper/ssv_huw.c	/^    struct ssv6xxx_platform_data *priv;$/;"	m	struct:ssv_huw_dev	typeref:struct:ssv_huw_dev::ssv6xxx_platform_data	file:	access:public
+ssv_huw_dev::read_wq	hci_wrapper/ssv_huw.c	/^    wait_queue_head_t read_wq;$/;"	m	struct:ssv_huw_dev	file:	access:public
+ssv_huw_dev::rx_skb_q	hci_wrapper/ssv_huw.c	/^ struct sk_buff_head rx_skb_q;$/;"	m	struct:ssv_huw_dev	typeref:struct:ssv_huw_dev::sk_buff_head	file:	access:public
+ssv_huw_dev::rxlock	hci_wrapper/ssv_huw.c	/^    spinlock_t rxlock;$/;"	m	struct:ssv_huw_dev	file:	access:public
+ssv_huw_devnode	hci_wrapper/ssv_huw.c	/^static char *ssv_huw_devnode(struct device *dev, umode_t *mode)$/;"	f	file:	signature:(struct device *dev, umode_t *mode)
+ssv_huw_driver	hci_wrapper/ssv_huw.c	/^static struct platform_driver ssv_huw_driver =$/;"	v	typeref:struct:platform_driver	file:
+ssv_huw_exit	hci_wrapper/ssv_huw.c	/^EXPORT_SYMBOL(ssv_huw_exit);$/;"	v
+ssv_huw_exit	hci_wrapper/ssv_huw.c	/^module_exit(ssv_huw_exit);$/;"	v
+ssv_huw_exit	hci_wrapper/ssv_huw.c	/^void ssv_huw_exit(void)$/;"	f	signature:(void)
+ssv_huw_init	hci_wrapper/ssv_huw.c	/^EXPORT_SYMBOL(ssv_huw_init);$/;"	v
+ssv_huw_init	hci_wrapper/ssv_huw.c	/^int ssv_huw_init(void)$/;"	f	signature:(void)
+ssv_huw_init	hci_wrapper/ssv_huw.c	/^module_init(ssv_huw_init);$/;"	v
+ssv_huw_init_buf	hci_wrapper/ssv_huw.c	/^static int ssv_huw_init_buf(struct ssv_huw_dev *hdev)$/;"	f	file:	signature:(struct ssv_huw_dev *hdev)
+ssv_huw_ioctl	hci_wrapper/ssv_huw.c	/^static long ssv_huw_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)$/;"	f	file:	signature:(struct file *filp, unsigned int cmd, unsigned long arg)
+ssv_huw_ioctl_process	hci_wrapper/ssv_huw.c	/^static long ssv_huw_ioctl_process(struct ssv_huw_dev *glue, unsigned int cmd, struct ssv_huw_cmd *pucmd_data, bool isCompat)$/;"	f	file:	signature:(struct ssv_huw_dev *glue, unsigned int cmd, struct ssv_huw_cmd *pucmd_data, bool isCompat)
+ssv_huw_ioctl_readReg	hci_wrapper/ssv_huw.c	/^static long ssv_huw_ioctl_readReg(struct ssv_huw_dev *phuw_dev,unsigned int cmd, struct ssv_huw_cmd *pcmd_data,struct ssv_huw_cmd *pucmd_data,bool isCompat)$/;"	f	file:	signature:(struct ssv_huw_dev *phuw_dev,unsigned int cmd, struct ssv_huw_cmd *pcmd_data,struct ssv_huw_cmd *pucmd_data,bool isCompat)
+ssv_huw_ioctl_writeReg	hci_wrapper/ssv_huw.c	/^static long ssv_huw_ioctl_writeReg(struct ssv_huw_dev *phuw_dev,unsigned int cmd, struct ssv_huw_cmd *pcmd_data,struct ssv_huw_cmd *pucmd_data,bool isCompat)$/;"	f	file:	signature:(struct ssv_huw_dev *phuw_dev,unsigned int cmd, struct ssv_huw_cmd *pcmd_data,struct ssv_huw_cmd *pucmd_data,bool isCompat)
+ssv_huw_ioctl_writeSram	hci_wrapper/ssv_huw.c	/^static long ssv_huw_ioctl_writeSram(struct ssv_huw_dev *phuw_dev,unsigned int cmd, struct ssv_huw_cmd *pcmd_data,struct ssv_huw_cmd *pucmd_data,bool isCompat)$/;"	f	file:	signature:(struct ssv_huw_dev *phuw_dev,unsigned int cmd, struct ssv_huw_cmd *pcmd_data,struct ssv_huw_cmd *pucmd_data,bool isCompat)
+ssv_huw_open	hci_wrapper/ssv_huw.c	/^static int ssv_huw_open(struct inode *inode, struct file *fp)$/;"	f	file:	signature:(struct inode *inode, struct file *fp)
+ssv_huw_probe	hci_wrapper/ssv_huw.c	/^EXPORT_SYMBOL(ssv_huw_probe);$/;"	v
+ssv_huw_probe	hci_wrapper/ssv_huw.c	/^int ssv_huw_probe(struct platform_device *pdev)$/;"	f	signature:(struct platform_device *pdev)
+ssv_huw_read	hci_wrapper/ssv_huw.c	/^static ssize_t ssv_huw_read(struct file *fp, char __user * buf, size_t length, loff_t * offset)$/;"	f	file:	signature:(struct file *fp, char __user * buf, size_t length, loff_t * offset)
+ssv_huw_read_hci_info	hci_wrapper/ssv_huw.c	/^int ssv_huw_read_hci_info(struct ssv_huw_dev *phuw_dev)$/;"	f	signature:(struct ssv_huw_dev *phuw_dev)
+ssv_huw_release	hci_wrapper/ssv_huw.c	/^static int ssv_huw_release(struct inode *inode, struct file *fp)$/;"	f	file:	signature:(struct inode *inode, struct file *fp)
+ssv_huw_remove	hci_wrapper/ssv_huw.c	/^EXPORT_SYMBOL(ssv_huw_remove);$/;"	v
+ssv_huw_remove	hci_wrapper/ssv_huw.c	/^int ssv_huw_remove(struct platform_device *pdev)$/;"	f	signature:(struct platform_device *pdev)
+ssv_huw_rx	hci_wrapper/ssv_huw.c	/^int ssv_huw_rx(struct sk_buff_head *rx_skb_q, void *args)$/;"	f	signature:(struct sk_buff_head *rx_skb_q, void *args)
+ssv_huw_tx_cb	hci_wrapper/ssv_huw.c	/^void ssv_huw_tx_cb(struct sk_buff_head *skb_head, void *args)$/;"	f	signature:(struct sk_buff_head *skb_head, void *args)
+ssv_huw_txbuf_free_skb	hci_wrapper/ssv_huw.c	/^void ssv_huw_txbuf_free_skb(struct sk_buff *skb, void *args)$/;"	f	signature:(struct sk_buff *skb, void *args)
+ssv_huw_write	hci_wrapper/ssv_huw.c	/^static ssize_t ssv_huw_write(struct file *fp, const char __user * buf, size_t length, loff_t * offset)$/;"	f	file:	signature:(struct file *fp, const char __user * buf, size_t length, loff_t * offset)
+ssv_hw	smac/dev.h	/^struct ssv_hw {$/;"	s
+ssv_hw::ampdu_divider	smac/dev.h	/^    u32 ampdu_divider;$/;"	m	struct:ssv_hw	access:public
+ssv_hw::cal	smac/dev.h	/^    struct ssv6006_cal_result cal;$/;"	m	struct:ssv_hw	typeref:struct:ssv_hw::ssv6006_cal_result	access:public
+ssv_hw::cfg	smac/dev.h	/^    struct ssv6xxx_cfg cfg;$/;"	m	struct:ssv_hw	typeref:struct:ssv_hw::ssv6xxx_cfg	access:public
+ssv_hw::ch_cfg_size	smac/dev.h	/^    u32 ch_cfg_size;$/;"	m	struct:ssv_hw	access:public
+ssv_hw::chip_id	smac/dev.h	/^    char chip_id[SSV6XXX_CHIP_ID_LENGTH];$/;"	m	struct:ssv_hw	access:public
+ssv_hw::chip_tag	smac/dev.h	/^    u64 chip_tag;$/;"	m	struct:ssv_hw	access:public
+ssv_hw::default_txgain	smac/dev.h	/^    u8 default_txgain[PADPDBAND];$/;"	m	struct:ssv_hw	access:public
+ssv_hw::efuse_bitmap	smac/dev.h	/^    u32 efuse_bitmap;$/;"	m	struct:ssv_hw	access:public
+ssv_hw::flash_config	smac/dev.h	/^    struct ssv_flash_config flash_config;$/;"	m	struct:ssv_hw	typeref:struct:ssv_hw::ssv_flash_config	access:public
+ssv_hw::hal_ops	smac/dev.h	/^    struct ssv_hal_ops hal_ops;$/;"	m	struct:ssv_hw	typeref:struct:ssv_hw::ssv_hal_ops	access:public
+ssv_hw::hci	smac/dev.h	/^    struct ssv6xxx_hci_info hci;$/;"	m	struct:ssv_hw	typeref:struct:ssv_hw::ssv6xxx_hci_info	access:public
+ssv_hw::hw_buf_ptr	smac/dev.h	/^    u32 hw_buf_ptr;$/;"	m	struct:ssv_hw	access:public
+ssv_hw::hw_buf_ptr	smac/dev.h	/^    u32 hw_buf_ptr[SSV_RC_MAX_STA];$/;"	m	struct:ssv_hw	access:public
+ssv_hw::hw_cfg	smac/dev.h	/^    struct list_head hw_cfg;$/;"	m	struct:ssv_hw	typeref:struct:ssv_hw::list_head	access:public
+ssv_hw::hw_cfg_mutex	smac/dev.h	/^    struct mutex hw_cfg_mutex;$/;"	m	struct:ssv_hw	typeref:struct:ssv_hw::mutex	access:public
+ssv_hw::hw_pinfo	smac/dev.h	/^    u32 hw_pinfo;$/;"	m	struct:ssv_hw	access:public
+ssv_hw::hw_sec_key	smac/dev.h	/^    u32 hw_sec_key;$/;"	m	struct:ssv_hw	access:public
+ssv_hw::hw_sec_key	smac/dev.h	/^    u32 hw_sec_key[SSV_RC_MAX_STA];$/;"	m	struct:ssv_hw	access:public
+ssv_hw::ipd_channel_touch	smac/dev.h	/^    u8 ipd_channel_touch;$/;"	m	struct:ssv_hw	access:public
+ssv_hw::iqk_cfg	smac/dev.h	/^    struct ssv6xxx_iqk_cfg iqk_cfg;$/;"	m	struct:ssv_hw	typeref:struct:ssv_hw::ssv6xxx_iqk_cfg	access:public
+ssv_hw::maddr	smac/dev.h	/^    struct mac_address maddr[SSV6200_MAX_HW_MAC_ADDR];$/;"	m	struct:ssv_hw	typeref:struct:ssv_hw::mac_address	access:public
+ssv_hw::n_addresses	smac/dev.h	/^    u32 n_addresses;$/;"	m	struct:ssv_hw	access:public
+ssv_hw::p_ch_cfg	smac/dev.h	/^    struct ssv6xxx_ch_cfg *p_ch_cfg;$/;"	m	struct:ssv_hw	typeref:struct:ssv_hw::ssv6xxx_ch_cfg	access:public
+ssv_hw::page_count	smac/dev.h	/^    u8 *page_count;$/;"	m	struct:ssv_hw	access:public
+ssv_hw::priv	smac/dev.h	/^    struct ssv6xxx_platform_data *priv;$/;"	m	struct:ssv_hw	typeref:struct:ssv_hw::ssv6xxx_platform_data	access:public
+ssv_hw::rx_burstread_cnt	smac/dev.h	/^    int rx_burstread_cnt;$/;"	m	struct:ssv_hw	access:public
+ssv_hw::rx_burstread_size_type	smac/dev.h	/^    int rx_burstread_size_type;$/;"	m	struct:ssv_hw	access:public
+ssv_hw::rx_desc_len	smac/dev.h	/^    u32 rx_desc_len;$/;"	m	struct:ssv_hw	access:public
+ssv_hw::rx_info	smac/dev.h	/^ struct ssv6xxx_rx_hw_info rx_info;$/;"	m	struct:ssv_hw	typeref:struct:ssv_hw::ssv6xxx_rx_hw_info	access:public
+ssv_hw::rx_mode	smac/dev.h	/^    int rx_mode;$/;"	m	struct:ssv_hw	access:public
+ssv_hw::rx_pinfo_pad	smac/dev.h	/^    u32 rx_pinfo_pad;$/;"	m	struct:ssv_hw	access:public
+ssv_hw::sc	smac/dev.h	/^    struct ssv_softc *sc;$/;"	m	struct:ssv_hw	typeref:struct:ssv_hw::ssv_softc	access:public
+ssv_hw::tx_desc_len	smac/dev.h	/^    u32 tx_desc_len;$/;"	m	struct:ssv_hw	access:public
+ssv_hw::tx_info	smac/dev.h	/^ struct ssv6xxx_tx_hw_info tx_info;$/;"	m	struct:ssv_hw	typeref:struct:ssv_hw::ssv6xxx_tx_hw_info	access:public
+ssv_hw::tx_page_available	smac/dev.h	/^    u32 tx_page_available;$/;"	m	struct:ssv_hw	access:public
+ssv_hw::write_hw_config_args	smac/dev.h	/^    void *write_hw_config_args;$/;"	m	struct:ssv_hw	access:public
+ssv_hw::write_hw_config_cb	smac/dev.h	/^    void (*write_hw_config_cb)(void *param, u32 addr, u32 value);$/;"	m	struct:ssv_hw	access:public
+ssv_hw_cfg	smac/dev.h	/^struct ssv_hw_cfg {$/;"	s
+ssv_hw_cfg::addr	smac/dev.h	/^    u32 addr;$/;"	m	struct:ssv_hw_cfg	access:public
+ssv_hw_cfg::list	smac/dev.h	/^    struct list_head list;$/;"	m	struct:ssv_hw_cfg	typeref:struct:ssv_hw_cfg::list_head	access:public
+ssv_hw_cfg::value	smac/dev.h	/^    u32 value;$/;"	m	struct:ssv_hw_cfg	access:public
+ssv_hw_txq	hci/ssv_hci.h	/^struct ssv_hw_txq {$/;"	s
+ssv_hw_txq::max_qsize	hci/ssv_hci.h	/^    int max_qsize;$/;"	m	struct:ssv_hw_txq	access:public
+ssv_hw_txq::paused	hci/ssv_hci.h	/^    bool paused;$/;"	m	struct:ssv_hw_txq	access:public
+ssv_hw_txq::qhead	hci/ssv_hci.h	/^    struct sk_buff_head qhead;$/;"	m	struct:ssv_hw_txq	typeref:struct:ssv_hw_txq::sk_buff_head	access:public
+ssv_hw_txq::resum_thres	hci/ssv_hci.h	/^    int resum_thres;$/;"	m	struct:ssv_hw_txq	access:public
+ssv_hw_txq::tx_flags	hci/ssv_hci.h	/^    u32 tx_flags;$/;"	m	struct:ssv_hw_txq	access:public
+ssv_hw_txq::tx_pkt	hci/ssv_hci.h	/^    u32 tx_pkt;$/;"	m	struct:ssv_hw_txq	access:public
+ssv_hw_txq::txq_no	hci/ssv_hci.h	/^    u32 txq_no;$/;"	m	struct:ssv_hw_txq	access:public
+ssv_hwif_read_reg	smac/hal/ssv6006c/ssv6006C_mac.c	/^static int ssv_hwif_read_reg (struct ssv_softc *sc, u32 addr, u32 *val)$/;"	f	file:	signature:(struct ssv_softc *sc, u32 addr, u32 *val)
+ssv_init_cli	smac/ssv_cli.h	/^int ssv_init_cli (const char *dev_name, struct ssv_cmd_data *cmd_data);$/;"	p	signature:(const char *dev_name, struct ssv_cmd_data *cmd_data)
+ssv_init_cli	ssvdevice/ssvdevice.c	/^EXPORT_SYMBOL(ssv_init_cli);$/;"	v
+ssv_init_cli	ssvdevice/ssvdevice.c	/^int ssv_init_cli (const char *dev_name, struct ssv_cmd_data *cmd_data)$/;"	f	signature:(const char *dev_name, struct ssv_cmd_data *cmd_data)
+ssv_init_sample_table	smac/ssv_rc_minstrel.c	/^static void ssv_init_sample_table(struct ssv_minstrel_sta_priv *minstrel_sta_priv)$/;"	f	file:	signature:(struct ssv_minstrel_sta_priv *minstrel_sta_priv)
+ssv_initmac	ssvdevice/ssvdevice.c	/^EXPORT_SYMBOL(ssv_initmac);$/;"	v
+ssv_initmac	ssvdevice/ssvdevice.c	/^char* ssv_initmac = NULL;$/;"	v
+ssv_mcs_ht_group	smac/ssv_rc_minstrel_ht.h	/^struct ssv_mcs_ht_group {$/;"	s
+ssv_mcs_ht_group::duration	smac/ssv_rc_minstrel_ht.h	/^ unsigned int duration[MCS_GROUP_RATES];$/;"	m	struct:ssv_mcs_ht_group	access:public
+ssv_mcs_ht_group::flags	smac/ssv_rc_minstrel_ht.h	/^ u32 flags;$/;"	m	struct:ssv_mcs_ht_group	access:public
+ssv_mcs_ht_group::streams	smac/ssv_rc_minstrel_ht.h	/^ unsigned int streams;$/;"	m	struct:ssv_mcs_ht_group	access:public
+ssv_minstrel	smac/ssv_rc_minstrel.c	/^struct rate_control_ops ssv_minstrel = {$/;"	v	typeref:struct:rate_control_ops
+ssv_minstrel_add_sta_debugfs	smac/ssv_rc_minstrel.c	/^static void ssv_minstrel_add_sta_debugfs(void *priv, void *priv_sta, struct dentry *dir)$/;"	f	file:	signature:(void *priv, void *priv_sta, struct dentry *dir)
+ssv_minstrel_alloc	smac/ssv_rc_minstrel.c	/^static void *ssv_minstrel_alloc(struct ieee80211_hw *hw, struct dentry *debugfsdir)$/;"	f	file:	signature:(struct ieee80211_hw *hw, struct dentry *debugfsdir)
+ssv_minstrel_alloc_sta	smac/ssv_rc_minstrel.c	/^static void *ssv_minstrel_alloc_sta(void *priv, struct ieee80211_sta *sta, gfp_t gfp)$/;"	f	file:	signature:(void *priv, struct ieee80211_sta *sta, gfp_t gfp)
+ssv_minstrel_ampdu_rate_rpt	smac/ssv_rc_minstrel_ht.h	/^struct ssv_minstrel_ampdu_rate_rpt {$/;"	s
+ssv_minstrel_ampdu_rate_rpt::ampdu_ack_len	smac/ssv_rc_minstrel_ht.h	/^ int ampdu_ack_len;$/;"	m	struct:ssv_minstrel_ampdu_rate_rpt	access:public
+ssv_minstrel_ampdu_rate_rpt::ampdu_len	smac/ssv_rc_minstrel_ht.h	/^ int ampdu_len;$/;"	m	struct:ssv_minstrel_ampdu_rate_rpt	access:public
+ssv_minstrel_ampdu_rate_rpt::is_sample	smac/ssv_rc_minstrel_ht.h	/^ bool is_sample;$/;"	m	struct:ssv_minstrel_ampdu_rate_rpt	access:public
+ssv_minstrel_ampdu_rate_rpt::pkt_no	smac/ssv_rc_minstrel_ht.h	/^ int pkt_no;$/;"	m	struct:ssv_minstrel_ampdu_rate_rpt	access:public
+ssv_minstrel_ampdu_rate_rpt::rate_rpt	smac/ssv_rc_minstrel_ht.h	/^ struct ssv_minstrel_ht_rpt rate_rpt[4];$/;"	m	struct:ssv_minstrel_ampdu_rate_rpt	typeref:struct:ssv_minstrel_ampdu_rate_rpt::ssv_minstrel_ht_rpt	access:public
+ssv_minstrel_ampdu_rate_rpt::used	smac/ssv_rc_minstrel_ht.h	/^ bool used;$/;"	m	struct:ssv_minstrel_ampdu_rate_rpt	access:public
+ssv_minstrel_debugfs_info	smac/ssv_rc_minstrel.h	/^struct ssv_minstrel_debugfs_info {$/;"	s
+ssv_minstrel_debugfs_info::buf	smac/ssv_rc_minstrel.h	/^ char buf[];$/;"	m	struct:ssv_minstrel_debugfs_info	access:public
+ssv_minstrel_debugfs_info::len	smac/ssv_rc_minstrel.h	/^ size_t len;$/;"	m	struct:ssv_minstrel_debugfs_info	access:public
+ssv_minstrel_free	smac/ssv_rc_minstrel.c	/^static void ssv_minstrel_free(void *priv)$/;"	f	file:	signature:(void *priv)
+ssv_minstrel_free_sta	smac/ssv_rc_minstrel.c	/^static void ssv_minstrel_free_sta(void *priv, struct ieee80211_sta *sta, void *priv_sta)$/;"	f	file:	signature:(void *priv, struct ieee80211_sta *sta, void *priv_sta)
+ssv_minstrel_get_rate	smac/ssv_rc_minstrel.c	/^static void ssv_minstrel_get_rate(void *priv, struct ieee80211_sta *sta,$/;"	f	file:	signature:(void *priv, struct ieee80211_sta *sta, void *priv_sta, struct ieee80211_tx_rate_control *txrc)
+ssv_minstrel_ht_calc_rate_ewma	smac/ssv_rc_minstrel_ht.c	/^static void ssv_minstrel_ht_calc_rate_ewma(struct ssv_softc *sc, struct ssv_minstrel_ht_rate_stats *mr)$/;"	f	file:	signature:(struct ssv_softc *sc, struct ssv_minstrel_ht_rate_stats *mr)
+ssv_minstrel_ht_calc_retransmit	smac/ssv_rc_minstrel_ht.c	/^static void ssv_minstrel_ht_calc_retransmit(struct ssv_minstrel_priv *smp,$/;"	f	file:	signature:(struct ssv_minstrel_priv *smp, struct ssv_minstrel_ht_sta *mhs, int index)
+ssv_minstrel_ht_calc_tp	smac/ssv_rc_minstrel_ht.c	/^static void ssv_minstrel_ht_calc_tp(struct ssv_minstrel_ht_sta *mhs, int group, int rate)$/;"	f	file:	signature:(struct ssv_minstrel_ht_sta *mhs, int group, int rate)
+ssv_minstrel_ht_get_duration	smac/ssv_rc_minstrel_ht.c	/^static inline int ssv_minstrel_ht_get_duration(int index)$/;"	f	file:	signature:(int index)
+ssv_minstrel_ht_get_rate	smac/ssv_rc_minstrel_ht.c	/^void ssv_minstrel_ht_get_rate(void *priv, struct ieee80211_sta *sta, void *priv_sta,$/;"	f	signature:(void *priv, struct ieee80211_sta *sta, void *priv_sta, struct ieee80211_tx_rate_control *txrc)
+ssv_minstrel_ht_get_rate	smac/ssv_rc_minstrel_ht.h	/^void ssv_minstrel_ht_get_rate(void *priv, struct ieee80211_sta *sta, void *priv_sta,$/;"	p	signature:(void *priv, struct ieee80211_sta *sta, void *priv_sta, struct ieee80211_tx_rate_control *txrc)
+ssv_minstrel_ht_get_ratestats	smac/ssv_rc_minstrel_ht.c	/^   ssv_minstrel_ht_get_ratestats(struct ssv_minstrel_ht_sta *mhs, int index)$/;"	f	file:	signature:(struct ssv_minstrel_ht_sta *mhs, int index)
+ssv_minstrel_ht_get_sample_rate	smac/ssv_rc_minstrel_ht.c	/^static int ssv_minstrel_ht_get_sample_rate(struct ssv_softc *sc,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ssv_minstrel_priv *smp, struct ssv_minstrel_ht_sta *mhs)
+ssv_minstrel_ht_init_sample_table	smac/ssv_rc_minstrel_ht.c	/^void ssv_minstrel_ht_init_sample_table(void)$/;"	f	signature:(void)
+ssv_minstrel_ht_init_sample_table	smac/ssv_rc_minstrel_ht.h	/^void ssv_minstrel_ht_init_sample_table(void);$/;"	p	signature:(void)
+ssv_minstrel_ht_mcs_group_data	smac/ssv_rc_minstrel_ht.h	/^struct ssv_minstrel_ht_mcs_group_data {$/;"	s
+ssv_minstrel_ht_mcs_group_data::column	smac/ssv_rc_minstrel_ht.h	/^ u8 column;$/;"	m	struct:ssv_minstrel_ht_mcs_group_data	access:public
+ssv_minstrel_ht_mcs_group_data::index	smac/ssv_rc_minstrel_ht.h	/^ u8 index;$/;"	m	struct:ssv_minstrel_ht_mcs_group_data	access:public
+ssv_minstrel_ht_mcs_group_data::max_prob_rate	smac/ssv_rc_minstrel_ht.h	/^ unsigned int max_prob_rate;$/;"	m	struct:ssv_minstrel_ht_mcs_group_data	access:public
+ssv_minstrel_ht_mcs_group_data::max_tp_rate	smac/ssv_rc_minstrel_ht.h	/^ unsigned int max_tp_rate;$/;"	m	struct:ssv_minstrel_ht_mcs_group_data	access:public
+ssv_minstrel_ht_mcs_group_data::max_tp_rate2	smac/ssv_rc_minstrel_ht.h	/^ unsigned int max_tp_rate2;$/;"	m	struct:ssv_minstrel_ht_mcs_group_data	access:public
+ssv_minstrel_ht_mcs_group_data::rates	smac/ssv_rc_minstrel_ht.h	/^ struct ssv_minstrel_ht_rate_stats rates[MCS_GROUP_RATES];$/;"	m	struct:ssv_minstrel_ht_mcs_group_data	typeref:struct:ssv_minstrel_ht_mcs_group_data::ssv_minstrel_ht_rate_stats	access:public
+ssv_minstrel_ht_mcs_group_data::supported	smac/ssv_rc_minstrel_ht.h	/^ u8 supported;$/;"	m	struct:ssv_minstrel_ht_mcs_group_data	access:public
+ssv_minstrel_ht_next_sample_idx	smac/ssv_rc_minstrel_ht.c	/^static void ssv_minstrel_ht_next_sample_idx(struct ssv_minstrel_ht_sta *mhs)$/;"	f	file:	signature:(struct ssv_minstrel_ht_sta *mhs)
+ssv_minstrel_ht_rate_stats	smac/ssv_rc_minstrel_ht.h	/^struct ssv_minstrel_ht_rate_stats {$/;"	s
+ssv_minstrel_ht_rate_stats::att_hist	smac/ssv_rc_minstrel_ht.h	/^ u64 att_hist, succ_hist;$/;"	m	struct:ssv_minstrel_ht_rate_stats	access:public
+ssv_minstrel_ht_rate_stats::attempts	smac/ssv_rc_minstrel_ht.h	/^ unsigned int attempts, last_attempts;$/;"	m	struct:ssv_minstrel_ht_rate_stats	access:public
+ssv_minstrel_ht_rate_stats::cur_prob	smac/ssv_rc_minstrel_ht.h	/^ unsigned int cur_prob, probability;$/;"	m	struct:ssv_minstrel_ht_rate_stats	access:public
+ssv_minstrel_ht_rate_stats::cur_tp	smac/ssv_rc_minstrel_ht.h	/^ unsigned int cur_tp;$/;"	m	struct:ssv_minstrel_ht_rate_stats	access:public
+ssv_minstrel_ht_rate_stats::last_attempts	smac/ssv_rc_minstrel_ht.h	/^ unsigned int attempts, last_attempts;$/;"	m	struct:ssv_minstrel_ht_rate_stats	access:public
+ssv_minstrel_ht_rate_stats::last_jiffies	smac/ssv_rc_minstrel_ht.h	/^ unsigned long last_jiffies;$/;"	m	struct:ssv_minstrel_ht_rate_stats	access:public
+ssv_minstrel_ht_rate_stats::last_success	smac/ssv_rc_minstrel_ht.h	/^ unsigned int success, last_success;$/;"	m	struct:ssv_minstrel_ht_rate_stats	access:public
+ssv_minstrel_ht_rate_stats::probability	smac/ssv_rc_minstrel_ht.h	/^ unsigned int cur_prob, probability;$/;"	m	struct:ssv_minstrel_ht_rate_stats	access:public
+ssv_minstrel_ht_rate_stats::retry_count	smac/ssv_rc_minstrel_ht.h	/^ unsigned int retry_count;$/;"	m	struct:ssv_minstrel_ht_rate_stats	access:public
+ssv_minstrel_ht_rate_stats::retry_count_rtscts	smac/ssv_rc_minstrel_ht.h	/^ unsigned int retry_count_rtscts;$/;"	m	struct:ssv_minstrel_ht_rate_stats	access:public
+ssv_minstrel_ht_rate_stats::retry_updated	smac/ssv_rc_minstrel_ht.h	/^ bool retry_updated;$/;"	m	struct:ssv_minstrel_ht_rate_stats	access:public
+ssv_minstrel_ht_rate_stats::sample_skipped	smac/ssv_rc_minstrel_ht.h	/^ u16 sample_skipped;$/;"	m	struct:ssv_minstrel_ht_rate_stats	access:public
+ssv_minstrel_ht_rate_stats::succ_hist	smac/ssv_rc_minstrel_ht.h	/^ u64 att_hist, succ_hist;$/;"	m	struct:ssv_minstrel_ht_rate_stats	access:public
+ssv_minstrel_ht_rate_stats::success	smac/ssv_rc_minstrel_ht.h	/^ unsigned int success, last_success;$/;"	m	struct:ssv_minstrel_ht_rate_stats	access:public
+ssv_minstrel_ht_rpt	smac/ssv_rc_minstrel_ht.h	/^struct ssv_minstrel_ht_rpt {$/;"	s
+ssv_minstrel_ht_rpt::count	smac/ssv_rc_minstrel_ht.h	/^ u8 count;$/;"	m	struct:ssv_minstrel_ht_rpt	access:public
+ssv_minstrel_ht_rpt::dword	smac/ssv_rc_minstrel_ht.h	/^ u8 dword;$/;"	m	struct:ssv_minstrel_ht_rpt	access:public
+ssv_minstrel_ht_rpt::last	smac/ssv_rc_minstrel_ht.h	/^ int last;$/;"	m	struct:ssv_minstrel_ht_rpt	access:public
+ssv_minstrel_ht_rpt::success	smac/ssv_rc_minstrel_ht.h	/^ int success;$/;"	m	struct:ssv_minstrel_ht_rpt	access:public
+ssv_minstrel_ht_sample_table	smac/ssv_rc_minstrel_ht.c	/^static u8 ssv_minstrel_ht_sample_table[SAMPLE_COLUMNS][MCS_GROUP_RATES];$/;"	v	file:
+ssv_minstrel_ht_set_rate	smac/ssv_rc_minstrel_ht.c	/^static void ssv_minstrel_ht_set_rate(struct ssv_softc *sc, struct ssv_minstrel_priv *smp, struct ssv_minstrel_ht_sta *mhs,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ssv_minstrel_priv *smp, struct ssv_minstrel_ht_sta *mhs, struct ieee80211_tx_rate *rate, int rate_series, int index, enum nl80211_band band, bool sample, bool rtscts)
+ssv_minstrel_ht_sta	smac/ssv_rc_minstrel_ht.h	/^struct ssv_minstrel_ht_sta {$/;"	s
+ssv_minstrel_ht_sta::ampdu_len	smac/ssv_rc_minstrel_ht.h	/^ unsigned int ampdu_len;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+ssv_minstrel_ht_sta::ampdu_packets	smac/ssv_rc_minstrel_ht.h	/^ unsigned int ampdu_packets;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+ssv_minstrel_ht_sta::ampdu_rpt_list	smac/ssv_rc_minstrel_ht.h	/^ struct ssv_minstrel_ampdu_rate_rpt ampdu_rpt_list[SSV_MINSTREL_AMPDU_RATE_RPTS];$/;"	m	struct:ssv_minstrel_ht_sta	typeref:struct:ssv_minstrel_ht_sta::ssv_minstrel_ampdu_rate_rpt	access:public
+ssv_minstrel_ht_sta::avg_ampdu_len	smac/ssv_rc_minstrel_ht.h	/^ unsigned int avg_ampdu_len;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+ssv_minstrel_ht_sta::cck_supported	smac/ssv_rc_minstrel_ht.h	/^    u8 cck_supported;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+ssv_minstrel_ht_sta::cck_supported_short	smac/ssv_rc_minstrel_ht.h	/^    u8 cck_supported_short;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+ssv_minstrel_ht_sta::group_idx	smac/ssv_rc_minstrel_ht.h	/^ u8 group_idx;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+ssv_minstrel_ht_sta::groups	smac/ssv_rc_minstrel_ht.h	/^  struct ssv_minstrel_ht_mcs_group_data groups[MINSTREL_MAX_STREAMS * MINSTREL_STREAM_GROUPS + 1];$/;"	m	struct:ssv_minstrel_ht_sta	typeref:struct:ssv_minstrel_ht_sta::ssv_minstrel_ht_mcs_group_data	access:public
+ssv_minstrel_ht_sta::hw_retry_acc	smac/ssv_rc_minstrel_ht.h	/^ u32 hw_retry_acc;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+ssv_minstrel_ht_sta::hw_success_acc	smac/ssv_rc_minstrel_ht.h	/^    u32 hw_success_acc;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+ssv_minstrel_ht_sta::max_prob_rate	smac/ssv_rc_minstrel_ht.h	/^ unsigned int max_prob_rate;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+ssv_minstrel_ht_sta::max_tp_rate	smac/ssv_rc_minstrel_ht.h	/^ unsigned int max_tp_rate;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+ssv_minstrel_ht_sta::max_tp_rate2	smac/ssv_rc_minstrel_ht.h	/^ unsigned int max_tp_rate2;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+ssv_minstrel_ht_sta::overhead	smac/ssv_rc_minstrel_ht.h	/^ unsigned int overhead;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+ssv_minstrel_ht_sta::overhead_rtscts	smac/ssv_rc_minstrel_ht.h	/^ unsigned int overhead_rtscts;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+ssv_minstrel_ht_sta::sample_count	smac/ssv_rc_minstrel_ht.h	/^ u8 sample_count;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+ssv_minstrel_ht_sta::sample_group	smac/ssv_rc_minstrel_ht.h	/^ u8 sample_group;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+ssv_minstrel_ht_sta::sample_packets	smac/ssv_rc_minstrel_ht.h	/^ u64 sample_packets;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+ssv_minstrel_ht_sta::sample_slow	smac/ssv_rc_minstrel_ht.h	/^ u8 sample_slow;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+ssv_minstrel_ht_sta::sample_tries	smac/ssv_rc_minstrel_ht.h	/^ u8 sample_tries;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+ssv_minstrel_ht_sta::sample_wait	smac/ssv_rc_minstrel_ht.h	/^ u8 sample_wait;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+ssv_minstrel_ht_sta::secondary_channel_clear	smac/ssv_rc_minstrel_ht.h	/^ u32 secondary_channel_clear;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+ssv_minstrel_ht_sta::sgi_state	smac/ssv_rc_minstrel_ht.h	/^ u8 sgi_state;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+ssv_minstrel_ht_sta::sgi_state_count	smac/ssv_rc_minstrel_ht.h	/^ u8 sgi_state_count;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+ssv_minstrel_ht_sta::sgi_state_lgi_success	smac/ssv_rc_minstrel_ht.h	/^ u32 sgi_state_lgi_success;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+ssv_minstrel_ht_sta::sgi_state_success	smac/ssv_rc_minstrel_ht.h	/^ u32 sgi_state_success;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+ssv_minstrel_ht_sta::sgi_state_total	smac/ssv_rc_minstrel_ht.h	/^ u32 sgi_state_total;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+ssv_minstrel_ht_sta::stats_update	smac/ssv_rc_minstrel_ht.h	/^ unsigned long stats_update;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+ssv_minstrel_ht_sta::total_packets	smac/ssv_rc_minstrel_ht.h	/^ u64 total_packets;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+ssv_minstrel_ht_sta::tx_flags	smac/ssv_rc_minstrel_ht.h	/^ u32 tx_flags;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+ssv_minstrel_ht_sta_is_cck_rates	smac/ssv_rc_minstrel_ht.c	/^bool ssv_minstrel_ht_sta_is_cck_rates(struct ieee80211_sta *sta)$/;"	f	signature:(struct ieee80211_sta *sta)
+ssv_minstrel_ht_sta_is_cck_rates	smac/ssv_rc_minstrel_ht.h	/^bool ssv_minstrel_ht_sta_is_cck_rates(struct ieee80211_sta *sta);$/;"	p	signature:(struct ieee80211_sta *sta)
+ssv_minstrel_ht_tx_status	smac/ssv_rc_minstrel_ht.c	/^void ssv_minstrel_ht_tx_status(struct ssv_softc *sc, void *rc_info,$/;"	f	signature:(struct ssv_softc *sc, void *rc_info, struct ssv_minstrel_ht_rpt ht_rpt[], int ht_rpt_num, int ampdu_len, int ampdu_ack_len, bool is_sample)
+ssv_minstrel_ht_tx_status	smac/ssv_rc_minstrel_ht.h	/^void ssv_minstrel_ht_tx_status(struct ssv_softc *sc, void *rc_info,$/;"	p	signature:(struct ssv_softc *sc, void *rc_info, struct ssv_minstrel_ht_rpt ht_rpt[], int ht_rpt_num, int ampdu_len, int ampdu_ack_len, bool is_sample)
+ssv_minstrel_ht_update_caps	smac/ssv_rc_minstrel_ht.c	/^void ssv_minstrel_ht_update_caps(void *priv, struct ieee80211_supported_band *sband,$/;"	f	signature:(void *priv, struct ieee80211_supported_band *sband, struct ieee80211_sta *sta, void *priv_sta, enum nl80211_channel_type oper_chan_type)
+ssv_minstrel_ht_update_caps	smac/ssv_rc_minstrel_ht.h	/^void ssv_minstrel_ht_update_caps(void *priv, struct ieee80211_supported_band *sband,$/;"	p	signature:(void *priv, struct ieee80211_supported_band *sband, struct ieee80211_sta *sta, void *priv_sta, enum nl80211_channel_type oper_chan_type)
+ssv_minstrel_ht_update_cck	smac/ssv_rc_minstrel_ht.c	/^static void ssv_minstrel_ht_update_cck(struct ssv_softc *sc, struct ssv_minstrel_priv *smp,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ssv_minstrel_priv *smp, struct ssv_minstrel_ht_sta *mhs, struct ieee80211_supported_band *sband, struct ieee80211_sta *sta)
+ssv_minstrel_ht_update_rate	smac/ssv_rc_minstrel_ht.c	/^int ssv_minstrel_ht_update_rate(struct ssv_softc *sc, struct sk_buff *skb)$/;"	f	signature:(struct ssv_softc *sc, struct sk_buff *skb)
+ssv_minstrel_ht_update_rate	smac/ssv_rc_minstrel_ht.h	/^int ssv_minstrel_ht_update_rate(struct ssv_softc *sc, struct sk_buff *skb);$/;"	p	signature:(struct ssv_softc *sc, struct sk_buff *skb)
+ssv_minstrel_ht_update_secondary_edcca_stats	smac/ssv_rc_minstrel_ht.c	/^static void ssv_minstrel_ht_update_secondary_edcca_stats(struct ssv_softc *sc, struct ssv_minstrel_ht_sta *mhs)$/;"	f	file:	signature:(struct ssv_softc *sc, struct ssv_minstrel_ht_sta *mhs)
+ssv_minstrel_ht_update_stats	smac/ssv_rc_minstrel_ht.c	/^static void ssv_minstrel_ht_update_stats(struct ssv_softc *sc, struct ssv_minstrel_priv *smp,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ssv_minstrel_priv *smp, struct ssv_minstrel_sta_priv *minstrel_sta_priv, struct ssv_minstrel_ht_sta *mhs)
+ssv_minstrel_mcs_groups	smac/ssv_rc_minstrel_ht.c	/^const struct ssv_mcs_ht_group ssv_minstrel_mcs_groups[] = {$/;"	v	typeref:struct:ssv_mcs_ht_group
+ssv_minstrel_priv	smac/ssv_rc_minstrel.h	/^struct ssv_minstrel_priv {$/;"	s
+ssv_minstrel_priv::cck_rates	smac/ssv_rc_minstrel.h	/^    u8 cck_rates[4];$/;"	m	struct:ssv_minstrel_priv	access:public
+ssv_minstrel_priv::cw_max	smac/ssv_rc_minstrel.h	/^ unsigned int cw_max;$/;"	m	struct:ssv_minstrel_priv	access:public
+ssv_minstrel_priv::cw_min	smac/ssv_rc_minstrel.h	/^ unsigned int cw_min;$/;"	m	struct:ssv_minstrel_priv	access:public
+ssv_minstrel_priv::has_mrr	smac/ssv_rc_minstrel.h	/^ bool has_mrr;$/;"	m	struct:ssv_minstrel_priv	access:public
+ssv_minstrel_priv::lookaround_rate	smac/ssv_rc_minstrel.h	/^ unsigned int lookaround_rate;$/;"	m	struct:ssv_minstrel_priv	access:public
+ssv_minstrel_priv::lookaround_rate_mrr	smac/ssv_rc_minstrel.h	/^ unsigned int lookaround_rate_mrr;$/;"	m	struct:ssv_minstrel_priv	access:public
+ssv_minstrel_priv::max_rates	smac/ssv_rc_minstrel.h	/^ unsigned int max_rates;$/;"	m	struct:ssv_minstrel_priv	access:public
+ssv_minstrel_priv::max_retry	smac/ssv_rc_minstrel.h	/^ unsigned int max_retry;$/;"	m	struct:ssv_minstrel_priv	access:public
+ssv_minstrel_priv::segment_size	smac/ssv_rc_minstrel.h	/^ unsigned int segment_size;$/;"	m	struct:ssv_minstrel_priv	access:public
+ssv_minstrel_priv::update_interval	smac/ssv_rc_minstrel.h	/^ unsigned int update_interval;$/;"	m	struct:ssv_minstrel_priv	access:public
+ssv_minstrel_rate	smac/ssv_rc_minstrel.h	/^struct ssv_minstrel_rate {$/;"	s
+ssv_minstrel_rate::ack_time	smac/ssv_rc_minstrel.h	/^ unsigned int ack_time;$/;"	m	struct:ssv_minstrel_rate	access:public
+ssv_minstrel_rate::adjusted_retry_count	smac/ssv_rc_minstrel.h	/^ unsigned int adjusted_retry_count;$/;"	m	struct:ssv_minstrel_rate	access:public
+ssv_minstrel_rate::att_hist	smac/ssv_rc_minstrel.h	/^ u64 att_hist;$/;"	m	struct:ssv_minstrel_rate	access:public
+ssv_minstrel_rate::attempts	smac/ssv_rc_minstrel.h	/^ u32 attempts;$/;"	m	struct:ssv_minstrel_rate	access:public
+ssv_minstrel_rate::bitrate	smac/ssv_rc_minstrel.h	/^ int bitrate;$/;"	m	struct:ssv_minstrel_rate	access:public
+ssv_minstrel_rate::cur_prob	smac/ssv_rc_minstrel.h	/^ u32 cur_prob;$/;"	m	struct:ssv_minstrel_rate	access:public
+ssv_minstrel_rate::cur_tp	smac/ssv_rc_minstrel.h	/^ u32 cur_tp;$/;"	m	struct:ssv_minstrel_rate	access:public
+ssv_minstrel_rate::flags	smac/ssv_rc_minstrel.h	/^ u32 flags;$/;"	m	struct:ssv_minstrel_rate	access:public
+ssv_minstrel_rate::hw_rate_desc	smac/ssv_rc_minstrel.h	/^ u8 hw_rate_desc;$/;"	m	struct:ssv_minstrel_rate	access:public
+ssv_minstrel_rate::last_attempts	smac/ssv_rc_minstrel.h	/^ u32 last_attempts;$/;"	m	struct:ssv_minstrel_rate	access:public
+ssv_minstrel_rate::last_jiffies	smac/ssv_rc_minstrel.h	/^ unsigned long last_jiffies;$/;"	m	struct:ssv_minstrel_rate	access:public
+ssv_minstrel_rate::last_success	smac/ssv_rc_minstrel.h	/^ u32 last_success;$/;"	m	struct:ssv_minstrel_rate	access:public
+ssv_minstrel_rate::perfect_tx_time	smac/ssv_rc_minstrel.h	/^ unsigned int perfect_tx_time;$/;"	m	struct:ssv_minstrel_rate	access:public
+ssv_minstrel_rate::probability	smac/ssv_rc_minstrel.h	/^ u32 probability;$/;"	m	struct:ssv_minstrel_rate	access:public
+ssv_minstrel_rate::retry_count	smac/ssv_rc_minstrel.h	/^ unsigned int retry_count;$/;"	m	struct:ssv_minstrel_rate	access:public
+ssv_minstrel_rate::retry_count_cts	smac/ssv_rc_minstrel.h	/^ unsigned int retry_count_cts;$/;"	m	struct:ssv_minstrel_rate	access:public
+ssv_minstrel_rate::retry_count_rtscts	smac/ssv_rc_minstrel.h	/^ unsigned int retry_count_rtscts;$/;"	m	struct:ssv_minstrel_rate	access:public
+ssv_minstrel_rate::rix	smac/ssv_rc_minstrel.h	/^ int rix;$/;"	m	struct:ssv_minstrel_rate	access:public
+ssv_minstrel_rate::sample_limit	smac/ssv_rc_minstrel.h	/^ int sample_limit;$/;"	m	struct:ssv_minstrel_rate	access:public
+ssv_minstrel_rate::succ_hist	smac/ssv_rc_minstrel.h	/^ u64 succ_hist;$/;"	m	struct:ssv_minstrel_rate	access:public
+ssv_minstrel_rate::success	smac/ssv_rc_minstrel.h	/^ u32 success;$/;"	m	struct:ssv_minstrel_rate	access:public
+ssv_minstrel_rate_init	smac/ssv_rc_minstrel.c	/^static void ssv_minstrel_rate_init(void *priv, struct ieee80211_supported_band *sband,$/;"	f	file:	signature:(void *priv, struct ieee80211_supported_band *sband, struct cfg80211_chan_def *chandef, struct ieee80211_sta *sta, void *priv_sta)
+ssv_minstrel_rate_update	smac/ssv_rc_minstrel.c	/^static void ssv_minstrel_rate_update(void *priv, struct ieee80211_supported_band *sband,$/;"	f	file:	signature:(void *priv, struct ieee80211_supported_band *sband, struct cfg80211_chan_def *chandef, struct ieee80211_sta *sta, void *priv_sta, u32 changed)
+ssv_minstrel_remove_sta_debugfs	smac/ssv_rc_minstrel.c	/^static void ssv_minstrel_remove_sta_debugfs(void *priv, void *priv_sta)$/;"	f	file:	signature:(void *priv, void *priv_sta)
+ssv_minstrel_set_fix_data_rate	smac/ssv_rc_minstrel.c	/^void ssv_minstrel_set_fix_data_rate(struct ssv_softc *sc,$/;"	f	signature:(struct ssv_softc *sc, struct ssv_minstrel_sta_priv *minstrel_sta_priv, struct ieee80211_tx_rate *ar)
+ssv_minstrel_set_fix_data_rate	smac/ssv_rc_minstrel.h	/^void ssv_minstrel_set_fix_data_rate(struct ssv_softc *sc,$/;"	p	signature:(struct ssv_softc *sc, struct ssv_minstrel_sta_priv *minstrel_sta_priv, struct ieee80211_tx_rate *ar)
+ssv_minstrel_sta_info	smac/ssv_rc_minstrel.h	/^struct ssv_minstrel_sta_info {$/;"	s
+ssv_minstrel_sta_info::g_rates_offset	smac/ssv_rc_minstrel.h	/^ int g_rates_offset;$/;"	m	struct:ssv_minstrel_sta_info	access:public
+ssv_minstrel_sta_info::lowest_rix	smac/ssv_rc_minstrel.h	/^ unsigned int lowest_rix;$/;"	m	struct:ssv_minstrel_sta_info	access:public
+ssv_minstrel_sta_info::max_prob_rate	smac/ssv_rc_minstrel.h	/^ unsigned int max_prob_rate;$/;"	m	struct:ssv_minstrel_sta_info	access:public
+ssv_minstrel_sta_info::max_tp_rate	smac/ssv_rc_minstrel.h	/^ unsigned int max_tp_rate;$/;"	m	struct:ssv_minstrel_sta_info	access:public
+ssv_minstrel_sta_info::max_tp_rate2	smac/ssv_rc_minstrel.h	/^ unsigned int max_tp_rate2;$/;"	m	struct:ssv_minstrel_sta_info	access:public
+ssv_minstrel_sta_info::n_rates	smac/ssv_rc_minstrel.h	/^ int n_rates;$/;"	m	struct:ssv_minstrel_sta_info	access:public
+ssv_minstrel_sta_info::packet_count	smac/ssv_rc_minstrel.h	/^ u64 packet_count;$/;"	m	struct:ssv_minstrel_sta_info	access:public
+ssv_minstrel_sta_info::prev_sample	smac/ssv_rc_minstrel.h	/^ bool prev_sample;$/;"	m	struct:ssv_minstrel_sta_info	access:public
+ssv_minstrel_sta_info::rate_avg	smac/ssv_rc_minstrel.h	/^ unsigned int rate_avg;$/;"	m	struct:ssv_minstrel_sta_info	access:public
+ssv_minstrel_sta_info::sample_column	smac/ssv_rc_minstrel.h	/^ unsigned int sample_column;$/;"	m	struct:ssv_minstrel_sta_info	access:public
+ssv_minstrel_sta_info::sample_count	smac/ssv_rc_minstrel.h	/^ u64 sample_count;$/;"	m	struct:ssv_minstrel_sta_info	access:public
+ssv_minstrel_sta_info::sample_deferred	smac/ssv_rc_minstrel.h	/^ int sample_deferred;$/;"	m	struct:ssv_minstrel_sta_info	access:public
+ssv_minstrel_sta_info::sample_idx	smac/ssv_rc_minstrel.h	/^ unsigned int sample_idx;$/;"	m	struct:ssv_minstrel_sta_info	access:public
+ssv_minstrel_sta_info::sp_ack_dur	smac/ssv_rc_minstrel.h	/^ unsigned int sp_ack_dur;$/;"	m	struct:ssv_minstrel_sta_info	access:public
+ssv_minstrel_sta_info::stats_update	smac/ssv_rc_minstrel.h	/^ unsigned long stats_update;$/;"	m	struct:ssv_minstrel_sta_info	access:public
+ssv_minstrel_sta_priv	smac/ssv_rc_minstrel.h	/^struct ssv_minstrel_sta_priv {$/;"	s
+ssv_minstrel_sta_priv::__anon16::ht	smac/ssv_rc_minstrel.h	/^  struct ssv_minstrel_ht_sta ht;$/;"	m	union:ssv_minstrel_sta_priv::__anon16	typeref:struct:ssv_minstrel_sta_priv::__anon16::ssv_minstrel_ht_sta	access:public
+ssv_minstrel_sta_priv::__anon16::legacy	smac/ssv_rc_minstrel.h	/^  struct ssv_minstrel_sta_info legacy;$/;"	m	union:ssv_minstrel_sta_priv::__anon16	typeref:struct:ssv_minstrel_sta_priv::__anon16::ssv_minstrel_sta_info	access:public
+ssv_minstrel_sta_priv::dbg_stats	smac/ssv_rc_minstrel.h	/^ struct dentry *dbg_stats;$/;"	m	struct:ssv_minstrel_sta_priv	typeref:struct:ssv_minstrel_sta_priv::dentry	access:public
+ssv_minstrel_sta_priv::is_ht	smac/ssv_rc_minstrel.h	/^ bool is_ht;$/;"	m	struct:ssv_minstrel_sta_priv	access:public
+ssv_minstrel_sta_priv::ratelist	smac/ssv_rc_minstrel.h	/^ struct ssv_minstrel_rate *ratelist;$/;"	m	struct:ssv_minstrel_sta_priv	typeref:struct:ssv_minstrel_sta_priv::ssv_minstrel_rate	access:public
+ssv_minstrel_sta_priv::sample_table	smac/ssv_rc_minstrel.h	/^ u8 *sample_table;$/;"	m	struct:ssv_minstrel_sta_priv	access:public
+ssv_minstrel_sta_priv::sta	smac/ssv_rc_minstrel.h	/^ struct ieee80211_sta *sta;$/;"	m	struct:ssv_minstrel_sta_priv	typeref:struct:ssv_minstrel_sta_priv::ieee80211_sta	access:public
+ssv_minstrel_sta_priv::update_aggr_check	smac/ssv_rc_minstrel.h	/^    bool update_aggr_check;$/;"	m	struct:ssv_minstrel_sta_priv	access:public
+ssv_minstrel_stat_fops	smac/ssv_rc_minstrel.c	/^static const struct file_operations ssv_minstrel_stat_fops = {$/;"	v	typeref:struct:file_operations	file:
+ssv_minstrel_stats_open	smac/ssv_rc_minstrel.c	/^static int ssv_minstrel_stats_open(struct inode *inode, struct file *file)$/;"	f	file:	signature:(struct inode *inode, struct file *file)
+ssv_minstrel_stats_read	smac/ssv_rc_minstrel.c	/^static ssize_t ssv_minstrel_stats_read(struct file *file, char __user *buf, size_t len, loff_t *ppos)$/;"	f	file:	signature:(struct file *file, char __user *buf, size_t len, loff_t *ppos)
+ssv_minstrel_stats_release	smac/ssv_rc_minstrel.c	/^static int ssv_minstrel_stats_release(struct inode *inode, struct file *file)$/;"	f	file:	signature:(struct inode *inode, struct file *file)
+ssv_minstrel_tx_status	smac/ssv_rc_minstrel.c	/^static void ssv_minstrel_tx_status(void *priv, struct ieee80211_supported_band *sband,$/;"	f	file:	signature:(void *priv, struct ieee80211_supported_band *sband, struct ieee80211_sta *sta, void *priv_sta, struct sk_buff *skb)
+ssv_minstrel_update_stats	smac/ssv_rc_minstrel.c	/^static void ssv_minstrel_update_stats(struct ssv_softc *sc, struct ssv_minstrel_priv *smp,$/;"	f	file:	signature:(struct ssv_softc *sc, struct ssv_minstrel_priv *smp, struct ssv_minstrel_sta_priv *minstrel_sta_priv)
+ssv_netlink_exit	umac/ssv6xxx_netlink_core.c	/^module_exit(ssv_netlink_exit);$/;"	v
+ssv_netlink_exit	umac/ssv6xxx_netlink_core.c	/^static void __exit ssv_netlink_exit(void)$/;"	f	file:	signature:(void)
+ssv_netlink_init	umac/ssv6xxx_netlink_core.c	/^module_init(ssv_netlink_init);$/;"	v
+ssv_netlink_init	umac/ssv6xxx_netlink_core.c	/^static int __init ssv_netlink_init(void)$/;"	f	file:	signature:(void)
+ssv_p2p_noa	smac/p2p.h	/^struct ssv_p2p_noa {$/;"	s
+ssv_p2p_noa::active_noa_vif	smac/p2p.h	/^    u8 active_noa_vif;$/;"	m	struct:ssv_p2p_noa	access:public
+ssv_p2p_noa::monitor_noa_vif	smac/p2p.h	/^    u8 monitor_noa_vif;$/;"	m	struct:ssv_p2p_noa	access:public
+ssv_p2p_noa::noa_detect	smac/p2p.h	/^    struct ssv_p2p_noa_detect noa_detect[SSV_NUM_VIF];$/;"	m	struct:ssv_p2p_noa	typeref:struct:ssv_p2p_noa::ssv_p2p_noa_detect	access:public
+ssv_p2p_noa::p2p_config_lock	smac/p2p.h	/^    spinlock_t p2p_config_lock;$/;"	m	struct:ssv_p2p_noa	access:public
+ssv_p2p_noa_detect	smac/p2p.h	/^struct ssv_p2p_noa_detect {$/;"	s
+ssv_p2p_noa_detect::last_rx	smac/p2p.h	/^    unsigned long last_rx;$/;"	m	struct:ssv_p2p_noa_detect	access:public
+ssv_p2p_noa_detect::noa_addr	smac/p2p.h	/^    const u8 *noa_addr;$/;"	m	struct:ssv_p2p_noa_detect	access:public
+ssv_p2p_noa_detect::noa_param_cmd	smac/p2p.h	/^    struct ssv6xxx_p2p_noa_param noa_param_cmd;$/;"	m	struct:ssv_p2p_noa_detect	typeref:struct:ssv_p2p_noa_detect::ssv6xxx_p2p_noa_param	access:public
+ssv_p2p_noa_detect::p2p_noa_index	smac/p2p.h	/^    s16 p2p_noa_index;$/;"	m	struct:ssv_p2p_noa_detect	access:public
+ssv_pkt_crypt_status	include/ssv6xxx_common.h	/^enum ssv_pkt_crypt_status$/;"	g
+ssv_rate_ctrl	smac/ssv_rc_common.h	/^struct ssv_rate_ctrl {$/;"	s
+ssv_rate_ctrl::rc_table	smac/ssv_rc_common.h	/^    struct ssv_rc_rate *rc_table;$/;"	m	struct:ssv_rate_ctrl	typeref:struct:ssv_rate_ctrl::ssv_rc_rate	access:public
+ssv_rate_ctrl::sta_rc_info	smac/ssv_rc_common.h	/^    struct ssv_sta_rc_info sta_rc_info[SSV_RC_MAX_STA];$/;"	m	struct:ssv_rate_ctrl	typeref:struct:ssv_rate_ctrl::ssv_sta_rc_info	access:public
+ssv_rate_info	smac/ssv_rc_common.h	/^struct ssv_rate_info {$/;"	s
+ssv_rate_info::c_flags	smac/ssv_rc_common.h	/^    u32 c_flags;$/;"	m	struct:ssv_rate_info	access:public
+ssv_rate_info::crate_hw_idx	smac/ssv_rc_common.h	/^    int crate_hw_idx;$/;"	m	struct:ssv_rate_info	access:public
+ssv_rate_info::crate_kbps	smac/ssv_rc_common.h	/^    int crate_kbps;$/;"	m	struct:ssv_rate_info	access:public
+ssv_rate_info::d_flags	smac/ssv_rc_common.h	/^    u32 d_flags;$/;"	m	struct:ssv_rate_info	access:public
+ssv_rate_info::drate_hw_idx	smac/ssv_rc_common.h	/^    int drate_hw_idx;$/;"	m	struct:ssv_rate_info	access:public
+ssv_rate_info::drate_kbps	smac/ssv_rc_common.h	/^    int drate_kbps;$/;"	m	struct:ssv_rate_info	access:public
+ssv_rate_ops	smac/ssv_rc.c	/^static struct rate_control_ops ssv_rate_ops =$/;"	v	typeref:struct:rate_control_ops	file:
+ssv_rc_rate	smac/ssv_rc_common.h	/^struct ssv_rc_rate {$/;"	s
+ssv_rc_rate::arith_shift	smac/ssv_rc_common.h	/^    u8 arith_shift;$/;"	m	struct:ssv_rc_rate	access:public
+ssv_rc_rate::ctrl_rate_idx	smac/ssv_rc_common.h	/^    u8 ctrl_rate_idx;$/;"	m	struct:ssv_rc_rate	access:public
+ssv_rc_rate::dot11_rate_idx	smac/ssv_rc_common.h	/^    u8 dot11_rate_idx;$/;"	m	struct:ssv_rc_rate	access:public
+ssv_rc_rate::hw_rate_idx	smac/ssv_rc_common.h	/^    u8 hw_rate_idx;$/;"	m	struct:ssv_rc_rate	access:public
+ssv_rc_rate::phy_type	smac/ssv_rc_common.h	/^    u16 phy_type;$/;"	m	struct:ssv_rc_rate	access:public
+ssv_rc_rate::rate_kbps	smac/ssv_rc_common.h	/^    u32 rate_kbps;$/;"	m	struct:ssv_rc_rate	access:public
+ssv_rc_rate::rc_flags	smac/ssv_rc_common.h	/^    u32 rc_flags;$/;"	m	struct:ssv_rc_rate	access:public
+ssv_rc_rate::target_pf	smac/ssv_rc_common.h	/^    u8 target_pf;$/;"	m	struct:ssv_rc_rate	access:public
+ssv_rc_rate_type	smac/ssv_rc_common.h	/^enum ssv_rc_rate_type {$/;"	g
+ssv_root_version	include/ssv_version.h	/^static u32 ssv_root_version = 17680;$/;"	v
+ssv_rx	smac/dev.h	/^struct ssv_rx {$/;"	s
+ssv_rx::rx_buf	smac/dev.h	/^    struct sk_buff *rx_buf;$/;"	m	struct:ssv_rx	typeref:struct:ssv_rx::sk_buff	access:public
+ssv_rx::rxq_count	smac/dev.h	/^    u32 rxq_count;$/;"	m	struct:ssv_rx	access:public
+ssv_rx::rxq_head	smac/dev.h	/^    struct sk_buff_head rxq_head;$/;"	m	struct:ssv_rx	typeref:struct:ssv_rx::sk_buff_head	access:public
+ssv_rx::rxq_lock	smac/dev.h	/^    spinlock_t rxq_lock;$/;"	m	struct:ssv_rx	access:public
+ssv_rx_buf	hwif/usb/usb.c	/^ struct ssv6xxx_rx_buf ssv_rx_buf[MAX_NR_RECVBUFF];$/;"	m	struct:ssv6xxx_usb_glue	typeref:struct:ssv6xxx_usb_glue::ssv6xxx_rx_buf	file:	access:public
+ssv_rx_flow	smac/dev.h	/^enum ssv_rx_flow{$/;"	g
+ssv_rx_nr_recvbuff	ssvdevice/ssvdevice.c	/^EXPORT_SYMBOL(ssv_rx_nr_recvbuff);$/;"	v
+ssv_rx_nr_recvbuff	ssvdevice/ssvdevice.c	/^int ssv_rx_nr_recvbuff = 2;$/;"	v
+ssv_rx_queue	hwif/usb/usb.c	/^ struct ssv6xxx_queue ssv_rx_queue;$/;"	m	struct:ssv6xxx_usb_glue	typeref:struct:ssv6xxx_usb_glue::ssv6xxx_queue	file:	access:public
+ssv_rx_use_wq	ssvdevice/ssvdevice.c	/^EXPORT_SYMBOL(ssv_rx_use_wq);$/;"	v
+ssv_rx_use_wq	ssvdevice/ssvdevice.c	/^int ssv_rx_use_wq = 0;$/;"	v
+ssv_rxbuf	bridge/sdiobridge.c	/^struct ssv_rxbuf$/;"	s	file:
+ssv_rxbuf	hci_wrapper/ssv_huw.c	/^struct ssv_rxbuf$/;"	s	file:
+ssv_rxbuf::list	bridge/sdiobridge.c	/^    struct list_head list;$/;"	m	struct:ssv_rxbuf	typeref:struct:ssv_rxbuf::list_head	file:	access:public
+ssv_rxbuf::list	hci_wrapper/ssv_huw.c	/^    struct list_head list;$/;"	m	struct:ssv_rxbuf	typeref:struct:ssv_rxbuf::list_head	file:	access:public
+ssv_rxbuf::rxdata	bridge/sdiobridge.c	/^    u8 rxdata[RXBUFLENGTH];$/;"	m	struct:ssv_rxbuf	file:	access:public
+ssv_rxbuf::rxdata	hci_wrapper/ssv_huw.c	/^    u8 rxdata[RXBUFLENGTH];$/;"	m	struct:ssv_rxbuf	file:	access:public
+ssv_rxbuf::rxsize	bridge/sdiobridge.c	/^    u32 rxsize;$/;"	m	struct:ssv_rxbuf	file:	access:public
+ssv_rxbuf::rxsize	hci_wrapper/ssv_huw.c	/^    u32 rxsize;$/;"	m	struct:ssv_rxbuf	file:	access:public
+ssv_sdio_bridge_driver	bridge/sdiobridge.c	/^EXPORT_SYMBOL(ssv_sdio_bridge_driver);$/;"	v
+ssv_sdio_bridge_driver	bridge/sdiobridge.c	/^static struct sdio_driver ssv_sdio_bridge_driver =$/;"	v	typeref:struct:sdio_driver	file:
+ssv_sdiobridge_cmd	bridge/sdiobridge_pub.h	/^struct ssv_sdiobridge_cmd {$/;"	s
+ssv_sdiobridge_cmd::in_data	bridge/sdiobridge_pub.h	/^    u8* in_data;$/;"	m	struct:ssv_sdiobridge_cmd	access:public
+ssv_sdiobridge_cmd::in_data_len	bridge/sdiobridge_pub.h	/^    __u32 in_data_len;$/;"	m	struct:ssv_sdiobridge_cmd	access:public
+ssv_sdiobridge_cmd::out_data	bridge/sdiobridge_pub.h	/^    u8* out_data;$/;"	m	struct:ssv_sdiobridge_cmd	access:public
+ssv_sdiobridge_cmd::out_data_len	bridge/sdiobridge_pub.h	/^    __u32 out_data_len;$/;"	m	struct:ssv_sdiobridge_cmd	access:public
+ssv_sdiobridge_cmd::padding1	bridge/sdiobridge_pub.h	/^    __u32 padding1;$/;"	m	struct:ssv_sdiobridge_cmd	access:public
+ssv_sdiobridge_cmd::padding2	bridge/sdiobridge_pub.h	/^        __u32 padding2;$/;"	m	struct:ssv_sdiobridge_cmd	access:public
+ssv_sdiobridge_cmd::response	bridge/sdiobridge_pub.h	/^    __u32 response;$/;"	m	struct:ssv_sdiobridge_cmd	access:public
+ssv_sdiobridge_deinit_debug	bridge/debug.c	/^void ssv_sdiobridge_deinit_debug(struct ssv_sdiobridge_glue *glue)$/;"	f	signature:(struct ssv_sdiobridge_glue *glue)
+ssv_sdiobridge_deinit_debug	bridge/debug.h	/^void ssv_sdiobridge_deinit_debug(struct ssv_sdiobridge_glue *glue);$/;"	p	signature:(struct ssv_sdiobridge_glue *glue)
+ssv_sdiobridge_device_close	bridge/sdiobridge.c	/^static int ssv_sdiobridge_device_close(struct inode *inode, struct file *filp)$/;"	f	file:	signature:(struct inode *inode, struct file *filp)
+ssv_sdiobridge_device_compat_ioctl	bridge/sdiobridge.c	/^static long ssv_sdiobridge_device_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)$/;"	f	file:	signature:(struct file *filp, unsigned int cmd, unsigned long arg)
+ssv_sdiobridge_device_ioctl	bridge/sdiobridge.c	/^static long ssv_sdiobridge_device_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)$/;"	f	file:	signature:(struct file *filp, unsigned int cmd, unsigned long arg)
+ssv_sdiobridge_device_ioctl_process	bridge/sdiobridge.c	/^static long ssv_sdiobridge_device_ioctl_process(struct ssv_sdiobridge_glue *glue, unsigned int cmd, struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)$/;"	f	file:	signature:(struct ssv_sdiobridge_glue *glue, unsigned int cmd, struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+ssv_sdiobridge_device_open	bridge/sdiobridge.c	/^static int ssv_sdiobridge_device_open(struct inode *inode, struct file *filp)$/;"	f	file:	signature:(struct inode *inode, struct file *filp)
+ssv_sdiobridge_device_read	bridge/sdiobridge.c	/^static ssize_t ssv_sdiobridge_device_read(struct file *filp,$/;"	f	file:	signature:(struct file *filp, char *buffer, size_t length, loff_t *offset)
+ssv_sdiobridge_device_write	bridge/sdiobridge.c	/^static ssize_t ssv_sdiobridge_device_write(struct file *filp,$/;"	f	file:	signature:(struct file *filp, const char *buff, size_t len, loff_t *off)
+ssv_sdiobridge_devices	bridge/sdiobridge.c	/^static const struct sdio_device_id ssv_sdiobridge_devices[] =$/;"	v	typeref:struct:sdio_device_id	file:
+ssv_sdiobridge_devnode	bridge/sdiobridge.c	/^static char *ssv_sdiobridge_devnode(struct device *dev, umode_t *mode)$/;"	f	file:	signature:(struct device *dev, umode_t *mode)
+ssv_sdiobridge_exit	bridge/sdiobridge.c	/^module_exit(ssv_sdiobridge_exit);$/;"	v
+ssv_sdiobridge_exit	bridge/sdiobridge.c	/^static void __exit ssv_sdiobridge_exit(void)$/;"	f	file:	signature:(void)
+ssv_sdiobridge_glue	bridge/sdiobridge.h	/^struct ssv_sdiobridge_glue$/;"	s
+ssv_sdiobridge_glue::autoAckInt	bridge/sdiobridge.h	/^ u8 autoAckInt;$/;"	m	struct:ssv_sdiobridge_glue	access:public
+ssv_sdiobridge_glue::blockMode	bridge/sdiobridge.h	/^ u8 blockMode;$/;"	m	struct:ssv_sdiobridge_glue	access:public
+ssv_sdiobridge_glue::blockSize	bridge/sdiobridge.h	/^ u16 blockSize;$/;"	m	struct:ssv_sdiobridge_glue	access:public
+ssv_sdiobridge_glue::bufaddr	bridge/sdiobridge.h	/^    void *bufaddr;$/;"	m	struct:ssv_sdiobridge_glue	access:public
+ssv_sdiobridge_glue::dataIOPort	bridge/sdiobridge.h	/^    unsigned int dataIOPort;$/;"	m	struct:ssv_sdiobridge_glue	access:public
+ssv_sdiobridge_glue::debugfs	bridge/sdiobridge.h	/^    struct dentry *debugfs;$/;"	m	struct:ssv_sdiobridge_glue	typeref:struct:ssv_sdiobridge_glue::dentry	access:public
+ssv_sdiobridge_glue::dev	bridge/sdiobridge.h	/^    struct device *dev;$/;"	m	struct:ssv_sdiobridge_glue	typeref:struct:ssv_sdiobridge_glue::device	access:public
+ssv_sdiobridge_glue::dump	bridge/sdiobridge.h	/^    u32 dump;$/;"	m	struct:ssv_sdiobridge_glue	access:public
+ssv_sdiobridge_glue::dump_entry	bridge/sdiobridge.h	/^    struct dentry *dump_entry;$/;"	m	struct:ssv_sdiobridge_glue	typeref:struct:ssv_sdiobridge_glue::dentry	access:public
+ssv_sdiobridge_glue::funcFocus	bridge/sdiobridge.h	/^    u8 funcFocus;$/;"	m	struct:ssv_sdiobridge_glue	access:public
+ssv_sdiobridge_glue::irq_handling	bridge/sdiobridge.h	/^    atomic_t irq_handling;$/;"	m	struct:ssv_sdiobridge_glue	access:public
+ssv_sdiobridge_glue::irq_wq	bridge/sdiobridge.h	/^    wait_queue_head_t irq_wq;$/;"	m	struct:ssv_sdiobridge_glue	access:public
+ssv_sdiobridge_glue::read_wq	bridge/sdiobridge.h	/^    wait_queue_head_t read_wq;$/;"	m	struct:ssv_sdiobridge_glue	access:public
+ssv_sdiobridge_glue::regIOPort	bridge/sdiobridge.h	/^    unsigned int regIOPort;$/;"	m	struct:ssv_sdiobridge_glue	access:public
+ssv_sdiobridge_glue::rxbuf	bridge/sdiobridge.h	/^ struct list_head rxbuf;$/;"	m	struct:ssv_sdiobridge_glue	typeref:struct:ssv_sdiobridge_glue::list_head	access:public
+ssv_sdiobridge_glue::rxbuflock	bridge/sdiobridge.h	/^    spinlock_t rxbuflock;$/;"	m	struct:ssv_sdiobridge_glue	access:public
+ssv_sdiobridge_glue::rxreadybuf	bridge/sdiobridge.h	/^    struct list_head rxreadybuf;$/;"	m	struct:ssv_sdiobridge_glue	typeref:struct:ssv_sdiobridge_glue::list_head	access:public
+ssv_sdiobridge_have_data	bridge/sdiobridge.c	/^static bool ssv_sdiobridge_have_data(struct ssv_sdiobridge_glue *glue)$/;"	f	file:	signature:(struct ssv_sdiobridge_glue *glue)
+ssv_sdiobridge_init	bridge/sdiobridge.c	/^module_init(ssv_sdiobridge_init);$/;"	v
+ssv_sdiobridge_init	bridge/sdiobridge.c	/^static int __init ssv_sdiobridge_init(void)$/;"	f	file:	signature:(void)
+ssv_sdiobridge_init_buf	bridge/sdiobridge.c	/^static int ssv_sdiobridge_init_buf(struct ssv_sdiobridge_glue *glue)$/;"	f	file:	signature:(struct ssv_sdiobridge_glue *glue)
+ssv_sdiobridge_init_debug	bridge/debug.c	/^int ssv_sdiobridge_init_debug(struct ssv_sdiobridge_glue *glue)$/;"	f	signature:(struct ssv_sdiobridge_glue *glue)
+ssv_sdiobridge_init_debug	bridge/debug.h	/^int ssv_sdiobridge_init_debug(struct ssv_sdiobridge_glue *glue);$/;"	p	signature:(struct ssv_sdiobridge_glue *glue)
+ssv_sdiobridge_ioctl_cdev	bridge/sdiobridge.c	/^static struct cdev ssv_sdiobridge_ioctl_cdev;$/;"	v	typeref:struct:cdev	file:
+ssv_sdiobridge_ioctl_cdev	hci_wrapper/ssv_huw.c	/^static struct cdev ssv_sdiobridge_ioctl_cdev;$/;"	v	typeref:struct:cdev	file:
+ssv_sdiobridge_ioctl_getBlockSize	bridge/sdiobridge.c	/^static long ssv_sdiobridge_ioctl_getBlockSize(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)$/;"	f	file:	signature:(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+ssv_sdiobridge_ioctl_getBusWidth	bridge/sdiobridge.c	/^static long ssv_sdiobridge_ioctl_getBusWidth(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)$/;"	f	file:	signature:(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+ssv_sdiobridge_ioctl_getFuncfocus	bridge/sdiobridge.c	/^static long ssv_sdiobridge_ioctl_getFuncfocus(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)$/;"	f	file:	signature:(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+ssv_sdiobridge_ioctl_getMultiByteIOPort	bridge/sdiobridge.c	/^static long ssv_sdiobridge_ioctl_getMultiByteIOPort(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)$/;"	f	file:	signature:(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+ssv_sdiobridge_ioctl_getMultiByteRegIOPort	bridge/sdiobridge.c	/^static long ssv_sdiobridge_ioctl_getMultiByteRegIOPort(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)$/;"	f	file:	signature:(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+ssv_sdiobridge_ioctl_major	bridge/sdiobridge.c	/^static unsigned int ssv_sdiobridge_ioctl_major = 0;$/;"	v	file:
+ssv_sdiobridge_ioctl_major	hci_wrapper/ssv_huw.c	/^static unsigned int ssv_sdiobridge_ioctl_major = 0;$/;"	v	file:
+ssv_sdiobridge_ioctl_readByte	bridge/sdiobridge.c	/^static long ssv_sdiobridge_ioctl_readByte(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)$/;"	f	file:	signature:(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+ssv_sdiobridge_ioctl_readMultiByte	bridge/sdiobridge.c	/^static long ssv_sdiobridge_ioctl_readMultiByte(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)$/;"	f	file:	signature:(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+ssv_sdiobridge_ioctl_readReg	bridge/sdiobridge.c	/^static long ssv_sdiobridge_ioctl_readReg(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)$/;"	f	file:	signature:(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+ssv_sdiobridge_ioctl_setBlockSize	bridge/sdiobridge.c	/^static long ssv_sdiobridge_ioctl_setBlockSize(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)$/;"	f	file:	signature:(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+ssv_sdiobridge_ioctl_setFuncfocus	bridge/sdiobridge.c	/^static long ssv_sdiobridge_ioctl_setFuncfocus(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)$/;"	f	file:	signature:(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+ssv_sdiobridge_ioctl_setMultiByteIOPort	bridge/sdiobridge.c	/^static long ssv_sdiobridge_ioctl_setMultiByteIOPort(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)$/;"	f	file:	signature:(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+ssv_sdiobridge_ioctl_setMultiByteRegIOPort	bridge/sdiobridge.c	/^static long ssv_sdiobridge_ioctl_setMultiByteRegIOPort(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)$/;"	f	file:	signature:(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+ssv_sdiobridge_ioctl_writeByte	bridge/sdiobridge.c	/^static long ssv_sdiobridge_ioctl_writeByte(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)$/;"	f	file:	signature:(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+ssv_sdiobridge_ioctl_writeMultiByte	bridge/sdiobridge.c	/^static long ssv_sdiobridge_ioctl_writeMultiByte(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)$/;"	f	file:	signature:(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+ssv_sdiobridge_ioctl_writeReg	bridge/sdiobridge.c	/^static long ssv_sdiobridge_ioctl_writeReg(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)$/;"	f	file:	signature:(struct ssv_sdiobridge_glue *glue,unsigned int cmd, struct ssv_sdiobridge_cmd *pcmd_data,struct ssv_sdiobridge_cmd *pucmd_data,bool isCompat)
+ssv_sdiobridge_irq_disable	bridge/sdiobridge.c	/^static void ssv_sdiobridge_irq_disable(struct ssv_sdiobridge_glue *glue,bool iswaitirq)$/;"	f	file:	signature:(struct ssv_sdiobridge_glue *glue,bool iswaitirq)
+ssv_sdiobridge_irq_enable	bridge/sdiobridge.c	/^static void ssv_sdiobridge_irq_enable(struct sdio_func *func,$/;"	f	file:	signature:(struct sdio_func *func, struct ssv_sdiobridge_glue *glue)
+ssv_sdiobridge_irq_handler	bridge/sdiobridge.c	/^static void ssv_sdiobridge_irq_handler(struct sdio_func *func)$/;"	f	file:	signature:(struct sdio_func *func)
+ssv_sdiobridge_irq_process	bridge/sdiobridge.c	/^static void ssv_sdiobridge_irq_process(struct sdio_func *func,$/;"	f	file:	signature:(struct sdio_func *func, struct ssv_sdiobridge_glue *glue)
+ssv_sdiobridge_is_on_irq	bridge/sdiobridge.c	/^static bool ssv_sdiobridge_is_on_irq(struct ssv_sdiobridge_glue *glue)$/;"	f	file:	signature:(struct ssv_sdiobridge_glue *glue)
+ssv_sdiobridge_pm_ops	bridge/sdiobridge.c	/^static const struct dev_pm_ops ssv_sdiobridge_pm_ops =$/;"	v	typeref:struct:dev_pm_ops	file:
+ssv_sdiobridge_probe	bridge/sdiobridge.c	/^static int __devinit ssv_sdiobridge_probe(struct sdio_func *func,$/;"	f	file:	signature:(struct sdio_func *func, const struct sdio_device_id *id)
+ssv_sdiobridge_read_parameter	bridge/sdiobridge.c	/^static void ssv_sdiobridge_read_parameter(struct sdio_func *func,$/;"	f	file:	signature:(struct sdio_func *func, struct ssv_sdiobridge_glue *glue)
+ssv_sdiobridge_remove	bridge/sdiobridge.c	/^static void __devexit ssv_sdiobridge_remove(struct sdio_func *func)$/;"	f	file:	signature:(struct sdio_func *func)
+ssv_sdiobridge_resume	bridge/sdiobridge.c	/^static int ssv_sdiobridge_resume(struct device *dev)$/;"	f	file:	signature:(struct device *dev)
+ssv_sdiobridge_suspend	bridge/sdiobridge.c	/^static int ssv_sdiobridge_suspend(struct device *dev)$/;"	f	file:	signature:(struct device *dev)
+ssv_skb_alloc	smac/ssv_skb.c	/^struct sk_buff *ssv_skb_alloc(void *app_param, s32 len)$/;"	f	signature:(void *app_param, s32 len)
+ssv_skb_alloc	smac/ssv_skb.h	/^struct sk_buff *ssv_skb_alloc(void *app_param, s32 len);$/;"	p	signature:(void *app_param, s32 len)
+ssv_skb_alloc_ex	smac/ssv_skb.c	/^struct sk_buff *ssv_skb_alloc_ex(void *app_param, s32 len, gfp_t gfp_mask)$/;"	f	signature:(void *app_param, s32 len, gfp_t gfp_mask)
+ssv_skb_alloc_ex	smac/ssv_skb.h	/^struct sk_buff *ssv_skb_alloc_ex(void *app_param, s32 len, gfp_t gfp_mask);$/;"	p	signature:(void *app_param, s32 len, gfp_t gfp_mask)
+ssv_skb_free	smac/ssv_skb.c	/^void ssv_skb_free(void *app_param, struct sk_buff *skb)$/;"	f	signature:(void *app_param, struct sk_buff *skb)
+ssv_skb_free	smac/ssv_skb.h	/^void ssv_skb_free(void *app_param, struct sk_buff *skb);$/;"	p	signature:(void *app_param, struct sk_buff *skb)
+ssv_smart_icomm_cmd	include/ssv6xxx_common.h	/^enum ssv_smart_icomm_cmd$/;"	g
+ssv_smart_icomm_cmd	smartlink/ssv_smartlink.h	/^enum ssv_smart_icomm_cmd$/;"	g
+ssv_smartlink_get_channel	smartlink/ssv_smartlink.c	/^int ssv_smartlink_get_channel(unsigned int *pch)$/;"	f	signature:(unsigned int *pch)
+ssv_smartlink_get_channel	smartlink/ssv_smartlink.h	/^int ssv_smartlink_get_channel(uint32_t *pch);$/;"	p	signature:(uint32_t *pch)
+ssv_smartlink_get_promisc	smartlink/ssv_smartlink.c	/^int ssv_smartlink_get_promisc(unsigned int *paccept)$/;"	f	signature:(unsigned int *paccept)
+ssv_smartlink_get_promisc	smartlink/ssv_smartlink.h	/^int ssv_smartlink_get_promisc(uint32_t *promisc);$/;"	p	signature:(uint32_t *promisc)
+ssv_smartlink_recv_packet	smartlink/ssv_smartlink.c	/^int ssv_smartlink_recv_packet(uint8_t *pOutBuf, unsigned int *pOutBufLen)$/;"	f	signature:(uint8_t *pOutBuf, unsigned int *pOutBufLen)
+ssv_smartlink_recv_packet	smartlink/ssv_smartlink.h	/^int ssv_smartlink_recv_packet(uint8_t *pOutBuf, uint32_t *pOutBufLen);$/;"	p	signature:(uint8_t *pOutBuf, uint32_t *pOutBufLen)
+ssv_smartlink_set_channel	smartlink/ssv_smartlink.c	/^int ssv_smartlink_set_channel(unsigned int ch)$/;"	f	signature:(unsigned int ch)
+ssv_smartlink_set_channel	smartlink/ssv_smartlink.h	/^int ssv_smartlink_set_channel(uint32_t ch);$/;"	p	signature:(uint32_t ch)
+ssv_smartlink_set_promisc	smartlink/ssv_smartlink.c	/^int ssv_smartlink_set_promisc(unsigned int promisc)$/;"	f	signature:(unsigned int promisc)
+ssv_smartlink_set_promisc	smartlink/ssv_smartlink.h	/^int ssv_smartlink_set_promisc(uint32_t promisc);$/;"	p	signature:(uint32_t promisc)
+ssv_smartlink_start	smartlink/ssv_smartlink.c	/^int ssv_smartlink_start(void)$/;"	f	signature:(void)
+ssv_smartlink_start	smartlink/ssv_smartlink.h	/^int ssv_smartlink_start(void);$/;"	p	signature:(void)
+ssv_smartlink_status	smac/dev.h	/^    u32 ssv_smartlink_status;$/;"	m	struct:ssv_softc	access:public
+ssv_smartlink_stop	smartlink/ssv_smartlink.c	/^int ssv_smartlink_stop(void)$/;"	f	signature:(void)
+ssv_smartlink_stop	smartlink/ssv_smartlink.h	/^int ssv_smartlink_stop(void);$/;"	p	signature:(void)
+ssv_smartlink_version	smartlink/ssv_smartlink.c	/^char *ssv_smartlink_version(void)$/;"	f	signature:(void)
+ssv_smartlink_version	smartlink/ssv_smartlink.h	/^char *ssv_smartlink_version(void);$/;"	p	signature:(void)
+ssv_softc	smac/dev.h	/^struct ssv_softc {$/;"	s
+ssv_softc::ack_counter	smac/dev.h	/^    u8 ack_counter;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::aid0_bit_set	smac/dev.h	/^    bool aid0_bit_set;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::ampdu_tx_frame	smac/dev.h	/^    atomic_t ampdu_tx_frame;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::ap_vif	smac/dev.h	/^    struct ieee80211_vif *ap_vif;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::ieee80211_vif	access:public
+ssv_softc::bScanning	smac/dev.h	/^    bool bScanning;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::ba_ra_addr	smac/dev.h	/^    u8 ba_ra_addr[ETH_ALEN];$/;"	m	struct:ssv_softc	access:public
+ssv_softc::ba_ssn	smac/dev.h	/^    u16 ba_ssn;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::ba_tid	smac/dev.h	/^    u16 ba_tid;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::bcast_interval	smac/dev.h	/^    int bcast_interval;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::bcast_start_work	smac/dev.h	/^    struct work_struct bcast_start_work;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::work_struct	access:public
+ssv_softc::bcast_stop_work	smac/dev.h	/^    struct delayed_work bcast_stop_work;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::delayed_work	access:public
+ssv_softc::bcast_tx_work	smac/dev.h	/^    struct delayed_work bcast_tx_work;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::delayed_work	access:public
+ssv_softc::bcast_txq	smac/dev.h	/^    struct ssv6xxx_bcast_txq bcast_txq;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::ssv6xxx_bcast_txq	access:public
+ssv_softc::beacon_buf	smac/dev.h	/^    struct sk_buff *beacon_buf;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::sk_buff	access:public
+ssv_softc::beacon_container	smac/dev.h	/^    struct sk_buff *beacon_container;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::sk_buff	access:public
+ssv_softc::beacon_container_update_time	smac/dev.h	/^    unsigned long beacon_container_update_time;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::beacon_dtim_cnt	smac/dev.h	/^    u8 beacon_dtim_cnt;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::beacon_info	smac/dev.h	/^    struct ssv6xxx_beacon_info beacon_info[2];$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::ssv6xxx_beacon_info	access:public
+ssv_softc::beacon_interval	smac/dev.h	/^    u8 beacon_interval;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::beacon_miss_work	smac/dev.h	/^    struct work_struct beacon_miss_work;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::work_struct	access:public
+ssv_softc::beacon_usage	smac/dev.h	/^    u8 beacon_usage;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::bq4_dtim	smac/dev.h	/^    bool bq4_dtim;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::bssid	smac/dev.h	/^    u8 bssid[2][6];$/;"	m	struct:ssv_softc	access:public
+ssv_softc::cci_clean_work	smac/dev.h	/^    struct work_struct cci_clean_work;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::work_struct	access:public
+ssv_softc::cci_current_gate	smac/dev.h	/^    u32 cci_current_gate;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::cci_current_level	smac/dev.h	/^    u32 cci_current_level;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::cci_last_jiffies	smac/dev.h	/^    unsigned long cci_last_jiffies;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::cci_modified	smac/dev.h	/^    bool cci_modified;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::cci_rx_unavailable_counter	smac/dev.h	/^    u8 cci_rx_unavailable_counter;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::cci_set	smac/dev.h	/^    bool cci_set;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::cci_set_work	smac/dev.h	/^    struct work_struct cci_set_work;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::work_struct	access:public
+ssv_softc::cci_start	smac/dev.h	/^    bool cci_start;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::ccmp_h_sel	smac/dev.h	/^    bool ccmp_h_sel;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::channel_center_freq	smac/dev.h	/^    u16 channel_center_freq;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::cmd_data	smac/dev.h	/^    struct ssv_cmd_data cmd_data;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::ssv_cmd_data	access:public
+ssv_softc::config_wq	smac/dev.h	/^    struct workqueue_struct *config_wq;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::workqueue_struct	access:public
+ssv_softc::cpu_nfb	smac/dev.h	/^    struct notifier_block cpu_nfb;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::notifier_block	access:public
+ssv_softc::crypt_st_lock	smac/dev.h	/^    spinlock_t crypt_st_lock;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::crypted_q	smac/dev.h	/^    struct sk_buff_head crypted_q;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::sk_buff_head	access:public
+ssv_softc::cur_channel	smac/dev.h	/^    struct ieee80211_channel *cur_channel;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::ieee80211_channel	access:public
+ssv_softc::current_pwr	smac/dev.h	/^    u8 current_pwr;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::dbg_rx_frame	smac/dev.h	/^    bool dbg_rx_frame;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::dbg_tx_frame	smac/dev.h	/^    bool dbg_tx_frame;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::debugfs_dir	smac/dev.h	/^    struct dentry *debugfs_dir;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::dentry	access:public
+ssv_softc::default_pwr	smac/dev.h	/^    u8 default_pwr;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::dev	smac/dev.h	/^    struct device *dev;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::device	access:public
+ssv_softc::directly_ack_high_threshold	smac/dev.h	/^    int directly_ack_high_threshold;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::directly_ack_low_threshold	smac/dev.h	/^    int directly_ack_low_threshold;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::dpd	smac/dev.h	/^    struct ssv6006_padpd dpd;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::ssv6006_padpd	access:public
+ssv_softc::early_suspend	smac/dev.h	/^    struct early_suspend early_suspend;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::early_suspend	access:public
+ssv_softc::enable_beacon	smac/dev.h	/^    u8 enable_beacon;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::encrypt_task_head	smac/dev.h	/^    struct list_head encrypt_task_head;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::list_head	access:public
+ssv_softc::force_disable_directly_ack_tx	smac/dev.h	/^    bool force_disable_directly_ack_tx;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::force_triger_reset	smac/dev.h	/^    bool force_triger_reset;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::fw_wait_q	smac/dev.h	/^    wait_queue_head_t fw_wait_q;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::green_pwr	smac/dev.h	/^    u8 green_pwr;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::gt_channel	smac/dev.h	/^    u8 gt_channel;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::gt_enabled	smac/dev.h	/^    bool gt_enabled;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::house_keeping	smac/dev.h	/^    struct timer_list house_keeping;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::timer_list	access:public
+ssv_softc::house_keeping_wq	smac/dev.h	/^    struct workqueue_struct *house_keeping_wq;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::workqueue_struct	access:public
+ssv_softc::hw	smac/dev.h	/^    struct ieee80211_hw *hw;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::ieee80211_hw	access:public
+ssv_softc::hw_chan	smac/dev.h	/^    u16 hw_chan;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::hw_chan_type	smac/dev.h	/^    u16 hw_chan_type;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::hw_mng_used	smac/dev.h	/^    u8 hw_mng_used;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::hw_restart_work	smac/dev.h	/^    struct work_struct hw_restart_work;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::work_struct	access:public
+ssv_softc::hw_wsid_bit	smac/dev.h	/^    u8 hw_wsid_bit;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::iq_cali_done	smac/dev.h	/^    u32 iq_cali_done;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::isAssoc	smac/dev.h	/^    bool isAssoc;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::log_ctrl	smac/dev.h	/^    u32 log_ctrl;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::lpbk_enable	smac/dev.h	/^    bool lpbk_enable;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::lpbk_err_cnt	smac/dev.h	/^    int lpbk_err_cnt;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::lpbk_rx_pkt_cnt	smac/dev.h	/^    int lpbk_rx_pkt_cnt;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::lpbk_tx_pkt_cnt	smac/dev.h	/^    int lpbk_tx_pkt_cnt;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::mac80211_dev_started	smac/dev.h	/^    bool mac80211_dev_started;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::mac_deci_tbl	smac/dev.h	/^    u16 *mac_deci_tbl;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::max_crypted_q_len	smac/dev.h	/^    u32 max_crypted_q_len;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::max_preprocess_q_len	smac/dev.h	/^    u32 max_preprocess_q_len;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::max_rate_idx	smac/dev.h	/^    int max_rate_idx;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::max_tx_skb_q_len	smac/dev.h	/^    u32 max_tx_skb_q_len;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::mem_mutex	smac/dev.h	/^    struct mutex mem_mutex;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::mutex	access:public
+ssv_softc::mib_edca_work	smac/dev.h	/^    struct work_struct mib_edca_work;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::work_struct	access:public
+ssv_softc::mutex	smac/dev.h	/^    struct mutex mutex;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::mutex	access:public
+ssv_softc::nvif	smac/dev.h	/^    u8 nvif;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::p2p_noa	smac/dev.h	/^    struct ssv_p2p_noa p2p_noa;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::ssv_p2p_noa	access:public
+ssv_softc::p2p_status	smac/dev.h	/^    u8 p2p_status;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::platform_dev	smac/dev.h	/^    struct platform_device *platform_dev;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::platform_device	access:public
+ssv_softc::pre_11b_cca_1	smac/dev.h	/^    u32 pre_11b_cca_1;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::pre_11b_cca_control	smac/dev.h	/^    u32 pre_11b_cca_control;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::pre_11b_rx_abbctune	smac/dev.h	/^    u32 pre_11b_rx_abbctune;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::preprocess_q	smac/dev.h	/^    struct sk_buff_head preprocess_q;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::sk_buff_head	access:public
+ssv_softc::primary_edca_mib	smac/dev.h	/^    int primary_edca_mib;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::ps_aid	smac/dev.h	/^    u16 ps_aid;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::ps_state_lock	smac/dev.h	/^    spinlock_t ps_state_lock;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::ps_status	smac/dev.h	/^    int ps_status;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::rc	smac/dev.h	/^    void *rc;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::rc_report_queue	smac/dev.h	/^    struct sk_buff_head rc_report_queue;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::sk_buff_head	access:public
+ssv_softc::rc_report_sechedule	smac/dev.h	/^    u16 rc_report_sechedule;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::rc_report_work	smac/dev.h	/^    struct work_struct rc_report_work;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::work_struct	access:public
+ssv_softc::rc_report_workqueue	smac/dev.h	/^    struct workqueue_struct *rc_report_workqueue;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::workqueue_struct	access:public
+ssv_softc::restart_counter	smac/dev.h	/^    u32 restart_counter;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::rf_rc	smac/dev.h	/^    u8 rf_rc;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::rx	smac/dev.h	/^    struct ssv_rx rx;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::ssv_rx	access:public
+ssv_softc::rx_ba_bitmap	smac/dev.h	/^    u8 rx_ba_bitmap;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::rx_ba_session_count	smac/dev.h	/^    int rx_ba_session_count;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::rx_ba_sta	smac/dev.h	/^    struct ieee80211_sta *rx_ba_sta;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::ieee80211_sta	access:public
+ssv_softc::rx_data_exist	smac/dev.h	/^    bool rx_data_exist;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::rx_skb_q	smac/dev.h	/^    struct sk_buff_head rx_skb_q;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::sk_buff_head	access:public
+ssv_softc::rx_stuck_idle_time	smac/dev.h	/^    int rx_stuck_idle_time;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::rx_stuck_reset_time	smac/dev.h	/^    unsigned long rx_stuck_reset_time;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::rx_stuck_work	smac/dev.h	/^    struct work_struct rx_stuck_work;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::work_struct	access:public
+ssv_softc::rx_task	smac/dev.h	/^    struct task_struct *rx_task;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::task_struct	access:public
+ssv_softc::rx_wait_q	smac/dev.h	/^    wait_queue_head_t rx_wait_q;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::rx_wait_q_woken	smac/dev.h	/^    u16 rx_wait_q_woken;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::sbands	smac/dev.h	/^    struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::ieee80211_supported_band	access:public
+ssv_softc::sbands	smac/dev.h	/^    struct ieee80211_supported_band sbands[NUM_NL80211_BANDS];$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::ieee80211_supported_band	access:public
+ssv_softc::sc_flags	smac/dev.h	/^    u32 sc_flags;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::sdio_rx_evt_size	smac/dev.h	/^    unsigned long sdio_rx_evt_size;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::sdio_throughput_timestamp	smac/dev.h	/^    unsigned long sdio_throughput_timestamp;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::secondary_edca_mib	smac/dev.h	/^    int secondary_edca_mib;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::set_ampdu_rx_add_work	smac/dev.h	/^    struct work_struct set_ampdu_rx_add_work;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::work_struct	access:public
+ssv_softc::set_ampdu_rx_del_work	smac/dev.h	/^ struct work_struct set_ampdu_rx_del_work;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::work_struct	access:public
+ssv_softc::set_tim_work	smac/dev.h	/^    struct work_struct set_tim_work;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::work_struct	access:public
+ssv_softc::set_txpwr_work	smac/dev.h	/^    struct work_struct set_txpwr_work;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::work_struct	access:public
+ssv_softc::sh	smac/dev.h	/^    struct ssv_hw *sh;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::ssv_hw	access:public
+ssv_softc::ssv_smartlink_status	smac/dev.h	/^    u32 ssv_smartlink_status;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::ssv_txtput	smac/dev.h	/^    struct _ssv6xxx_txtput ssv_txtput;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::_ssv6xxx_txtput	access:public
+ssv_softc::ssv_usr_pid	smac/dev.h	/^    u32 ssv_usr_pid;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::ssv_wake_lock_	smac/dev.h	/^    struct wake_lock ssv_wake_lock_;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::wake_lock	access:public
+ssv_softc::sta_info	smac/dev.h	/^    struct ssv_sta_info sta_info[SSV_NUM_STA];$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::ssv_sta_info	access:public
+ssv_softc::sta_info_sem	smac/dev.h	/^    struct rw_semaphore sta_info_sem;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::rw_semaphore	access:public
+ssv_softc::thermal_monitor	smac/dev.h	/^    bool thermal_monitor;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::thermal_monitor_counter	smac/dev.h	/^    int thermal_monitor_counter;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::thermal_monitor_work	smac/dev.h	/^    struct work_struct thermal_monitor_work;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::work_struct	access:public
+ssv_softc::tid	smac/dev.h	/^    struct AMPDU_TID_st *tid[MAX_TID];$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::AMPDU_TID_st	access:public
+ssv_softc::trap_data	smac/dev.h	/^ struct ssv_trap_data trap_data;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::ssv_trap_data	access:public
+ssv_softc::tx	smac/dev.h	/^    struct ssv_tx tx;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::ssv_tx	access:public
+ssv_softc::tx_done_q	smac/dev.h	/^    struct sk_buff_head tx_done_q;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::sk_buff_head	access:public
+ssv_softc::tx_pkt_run_no	smac/dev.h	/^    u8 tx_pkt_run_no;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::tx_pkt_run_no_lock	smac/dev.h	/^    spinlock_t tx_pkt_run_no_lock;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::tx_poll_work	smac/dev.h	/^    struct work_struct tx_poll_work;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::work_struct	access:public
+ssv_softc::tx_q_empty	smac/dev.h	/^    bool tx_q_empty;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::tx_skb_q	smac/dev.h	/^    struct sk_buff_head tx_skb_q;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::sk_buff_head	access:public
+ssv_softc::tx_task	smac/dev.h	/^    struct task_struct *tx_task;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::task_struct	access:public
+ssv_softc::tx_wait_q	smac/dev.h	/^    wait_queue_head_t tx_wait_q;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::tx_wait_q_woken	smac/dev.h	/^    u16 tx_wait_q_woken;$/;"	m	struct:ssv_softc	access:public
+ssv_softc::umac	smac/dev.h	/^    struct ssv6xxx_umac_ops *umac;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::ssv6xxx_umac_ops	access:public
+ssv_softc::vif_info	smac/dev.h	/^    struct ssv_vif_info vif_info[SSV_NUM_VIF];$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::ssv_vif_info	access:public
+ssv_sta_info	smac/dev.h	/^struct ssv_sta_info {$/;"	s
+ssv_sta_info::aid	smac/dev.h	/^    u16 aid;$/;"	m	struct:ssv_sta_info	access:public
+ssv_sta_info::debugfs_dir	smac/dev.h	/^    struct dentry *debugfs_dir;$/;"	m	struct:ssv_sta_info	typeref:struct:ssv_sta_info::dentry	access:public
+ssv_sta_info::hw_wsid	smac/dev.h	/^    int hw_wsid;$/;"	m	struct:ssv_sta_info	access:public
+ssv_sta_info::s_flags	smac/dev.h	/^    u16 s_flags;$/;"	m	struct:ssv_sta_info	access:public
+ssv_sta_info::sta	smac/dev.h	/^    struct ieee80211_sta *sta;$/;"	m	struct:ssv_sta_info	typeref:struct:ssv_sta_info::ieee80211_sta	access:public
+ssv_sta_info::tim_set	smac/dev.h	/^    bool tim_set;$/;"	m	struct:ssv_sta_info	access:public
+ssv_sta_info::vif	smac/dev.h	/^    struct ieee80211_vif *vif;$/;"	m	struct:ssv_sta_info	typeref:struct:ssv_sta_info::ieee80211_vif	access:public
+ssv_sta_priv_data	smac/dev.h	/^struct ssv_sta_priv_data {$/;"	s
+ssv_sta_priv_data::ampdu_mib_total_BA_counter	smac/dev.h	/^    u32 ampdu_mib_total_BA_counter;$/;"	m	struct:ssv_sta_priv_data	access:public
+ssv_sta_priv_data::ampdu_ssn	smac/dev.h	/^    struct aggr_ssn ampdu_ssn[MAX_CONCUR_AMPDU];$/;"	m	struct:ssv_sta_priv_data	typeref:struct:ssv_sta_priv_data::aggr_ssn	access:public
+ssv_sta_priv_data::ampdu_tid	smac/dev.h	/^    AMPDU_TID ampdu_tid[WMM_TID_NUM];$/;"	m	struct:ssv_sta_priv_data	access:public
+ssv_sta_priv_data::beacon_rssi	smac/dev.h	/^    u32 beacon_rssi;$/;"	m	struct:ssv_sta_priv_data	access:public
+ssv_sta_priv_data::crypto_data	smac/dev.h	/^    struct ssv_crypto_data crypto_data;$/;"	m	struct:ssv_sta_priv_data	typeref:struct:ssv_sta_priv_data::ssv_crypto_data	access:public
+ssv_sta_priv_data::group_key_idx	smac/dev.h	/^    u8 group_key_idx;$/;"	m	struct:ssv_sta_priv_data	access:public
+ssv_sta_priv_data::has_hw_decrypt	smac/dev.h	/^    bool has_hw_decrypt;$/;"	m	struct:ssv_sta_priv_data	access:public
+ssv_sta_priv_data::has_hw_encrypt	smac/dev.h	/^    bool has_hw_encrypt;$/;"	m	struct:ssv_sta_priv_data	access:public
+ssv_sta_priv_data::list	smac/dev.h	/^    struct list_head list;$/;"	m	struct:ssv_sta_priv_data	typeref:struct:ssv_sta_priv_data::list_head	access:public
+ssv_sta_priv_data::max_ampdu_size	smac/dev.h	/^    u16 max_ampdu_size;$/;"	m	struct:ssv_sta_priv_data	access:public
+ssv_sta_priv_data::need_sw_decrypt	smac/dev.h	/^    bool need_sw_decrypt;$/;"	m	struct:ssv_sta_priv_data	access:public
+ssv_sta_priv_data::need_sw_encrypt	smac/dev.h	/^    bool need_sw_encrypt;$/;"	m	struct:ssv_sta_priv_data	access:public
+ssv_sta_priv_data::rc_idx	smac/dev.h	/^    int rc_idx;$/;"	m	struct:ssv_sta_priv_data	access:public
+ssv_sta_priv_data::rc_info	smac/dev.h	/^ void *rc_info;$/;"	m	struct:ssv_sta_priv_data	access:public
+ssv_sta_priv_data::retry_samples	smac/dev.h	/^    u32 retry_samples[16];$/;"	m	struct:ssv_sta_priv_data	access:public
+ssv_sta_priv_data::rx_data_rate	smac/dev.h	/^    int rx_data_rate;$/;"	m	struct:ssv_sta_priv_data	access:public
+ssv_sta_priv_data::rxstats	smac/dev.h	/^    struct rx_stats rxstats;$/;"	m	struct:ssv_sta_priv_data	typeref:struct:ssv_sta_priv_data::rx_stats	access:public
+ssv_sta_priv_data::sta_idx	smac/dev.h	/^    int sta_idx;$/;"	m	struct:ssv_sta_priv_data	access:public
+ssv_sta_priv_data::sta_info	smac/dev.h	/^    struct ssv_sta_info *sta_info;$/;"	m	struct:ssv_sta_priv_data	typeref:struct:ssv_sta_priv_data::ssv_sta_info	access:public
+ssv_sta_priv_data::use_mac80211_decrypt	smac/dev.h	/^    bool use_mac80211_decrypt;$/;"	m	struct:ssv_sta_priv_data	access:public
+ssv_sta_rc_info	smac/ssv_rc_common.h	/^struct ssv_sta_rc_info {$/;"	s
+ssv_sta_rc_info::ht	smac/ssv_rc_common.h	/^    struct ssv62xx_ht ht;$/;"	m	struct:ssv_sta_rc_info	typeref:struct:ssv_sta_rc_info::ssv62xx_ht	access:public
+ssv_sta_rc_info::ht_rc_type	smac/ssv_rc_common.h	/^    u8 ht_rc_type;$/;"	m	struct:ssv_sta_rc_info	access:public
+ssv_sta_rc_info::ht_supp_rates	smac/ssv_rc_common.h	/^    u32 ht_supp_rates;$/;"	m	struct:ssv_sta_rc_info	access:public
+ssv_sta_rc_info::is_ht	smac/ssv_rc_common.h	/^    u8 is_ht;$/;"	m	struct:ssv_sta_rc_info	access:public
+ssv_sta_rc_info::pinfo	smac/ssv_rc_common.h	/^    struct rc_pid_info pinfo;$/;"	m	struct:ssv_sta_rc_info	typeref:struct:ssv_sta_rc_info::rc_pid_info	access:public
+ssv_sta_rc_info::rc_num_rate	smac/ssv_rc_common.h	/^    u8 rc_num_rate;$/;"	m	struct:ssv_sta_rc_info	access:public
+ssv_sta_rc_info::rc_supp_rates	smac/ssv_rc_common.h	/^    u32 rc_supp_rates;$/;"	m	struct:ssv_sta_rc_info	access:public
+ssv_sta_rc_info::rc_type	smac/ssv_rc_common.h	/^    u8 rc_type;$/;"	m	struct:ssv_sta_rc_info	access:public
+ssv_sta_rc_info::rc_valid	smac/ssv_rc_common.h	/^    u8 rc_valid;$/;"	m	struct:ssv_sta_rc_info	access:public
+ssv_sta_rc_info::rc_wsid	smac/ssv_rc_common.h	/^    s8 rc_wsid;$/;"	m	struct:ssv_sta_rc_info	access:public
+ssv_sta_rc_info::spinfo	smac/ssv_rc_common.h	/^    struct rc_pid_sta_info spinfo;$/;"	m	struct:ssv_sta_rc_info	typeref:struct:ssv_sta_rc_info::rc_pid_sta_info	access:public
+ssv_start_sta_mode	smartlink/airkiss.c	/^static char *ssv_start_sta_mode = "cd %s\/         && .\/sta.sh";$/;"	v	file:
+ssv_start_sta_mode	smartlink/qqlink.c	/^static char *ssv_start_sta_mode = "cd %s\/         && .\/sta.sh";$/;"	v	file:
+ssv_tempe_table	smac/dev.h	/^struct ssv_tempe_table {$/;"	s
+ssv_tempe_table::a_band_gain	smac/dev.h	/^    u8 a_band_gain[4];$/;"	m	struct:ssv_tempe_table	access:public
+ssv_tempe_table::g_band_gain	smac/dev.h	/^    u8 g_band_gain[7];$/;"	m	struct:ssv_tempe_table	access:public
+ssv_tempe_table::xtal_offset	smac/dev.h	/^    u16 xtal_offset;$/;"	m	struct:ssv_tempe_table	access:public
+ssv_trap_data	smac/dev.h	/^struct ssv_trap_data {$/;"	s
+ssv_trap_data::reason_trap0	smac/dev.h	/^ u32 reason_trap0;$/;"	m	struct:ssv_trap_data	access:public
+ssv_trap_data::reason_trap1	smac/dev.h	/^ u32 reason_trap1;$/;"	m	struct:ssv_trap_data	access:public
+ssv_tx	smac/dev.h	/^struct ssv_tx {$/;"	s
+ssv_tx::ac_txqid	smac/dev.h	/^    int ac_txqid[WMM_NUM_AC];$/;"	m	struct:ssv_tx	access:public
+ssv_tx::ampdu_tx_group_id	smac/dev.h	/^    u16 ampdu_tx_group_id;$/;"	m	struct:ssv_tx	access:public
+ssv_tx::ampdu_tx_que	smac/dev.h	/^    struct list_head ampdu_tx_que;$/;"	m	struct:ssv_tx	typeref:struct:ssv_tx::list_head	access:public
+ssv_tx::ampdu_tx_que_lock	smac/dev.h	/^    spinlock_t ampdu_tx_que_lock;$/;"	m	struct:ssv_tx	access:public
+ssv_tx::flow_ctrl_status	smac/dev.h	/^    u32 flow_ctrl_status;$/;"	m	struct:ssv_tx	access:public
+ssv_tx::hw_txqid	smac/dev.h	/^    int hw_txqid[WMM_NUM_AC];$/;"	m	struct:ssv_tx	access:public
+ssv_tx::seq_no	smac/dev.h	/^    u16 seq_no;$/;"	m	struct:ssv_tx	access:public
+ssv_tx::tx_frag	smac/dev.h	/^    u32 tx_frag[SSV_HW_TXQ_NUM];$/;"	m	struct:ssv_tx	access:public
+ssv_tx::tx_pkt	smac/dev.h	/^    u32 tx_pkt[SSV_HW_TXQ_NUM];$/;"	m	struct:ssv_tx	access:public
+ssv_txtput	smac/dev.h	/^    struct _ssv6xxx_txtput ssv_txtput;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::_ssv6xxx_txtput	access:public
+ssv_umac	umac/ssv6xxx_netlink_core.c	/^struct ssv6xxx_umac_ops ssv_umac = {$/;"	v	typeref:struct:ssv6xxx_umac_ops
+ssv_usb_disconnect	hwif/usb/usb.c	/^static void ssv_usb_disconnect(struct usb_interface *interface)$/;"	f	file:	signature:(struct usb_interface *interface)
+ssv_usb_do_device_exit	hwif/usb/usb.c	/^static int ssv_usb_do_device_exit(struct device *d, void *arg)$/;"	f	file:	signature:(struct device *d, void *arg)
+ssv_usb_driver	hwif/usb/usb.c	/^static struct usb_driver ssv_usb_driver = {$/;"	v	typeref:struct:usb_driver	file:
+ssv_usb_driver	hwif/usb/usb.c	/^static struct usb_driver ssv_usb_driver;$/;"	v	typeref:struct:usb_driver	file:
+ssv_usb_probe	hwif/usb/usb.c	/^static int ssv_usb_probe(struct usb_interface *interface,$/;"	f	file:	signature:(struct usb_interface *interface, const struct usb_device_id *id)
+ssv_usb_resume	hwif/usb/usb.c	/^static int ssv_usb_resume(struct usb_interface *interface)$/;"	f	file:	signature:(struct usb_interface *interface)
+ssv_usb_suspend	hwif/usb/usb.c	/^static int ssv_usb_suspend(struct usb_interface *interface, pm_message_t message)$/;"	f	file:	signature:(struct usb_interface *interface, pm_message_t message)
+ssv_usb_table	hwif/usb/usb.c	/^static const struct usb_device_id ssv_usb_table[] = {$/;"	v	typeref:struct:usb_device_id	file:
+ssv_usr_pid	smac/dev.h	/^    u32 ssv_usr_pid;$/;"	m	struct:ssv_softc	access:public
+ssv_vif_info	smac/dev.h	/^struct ssv_vif_info {$/;"	s
+ssv_vif_info::debugfs_dir	smac/dev.h	/^    struct dentry *debugfs_dir;$/;"	m	struct:ssv_vif_info	typeref:struct:ssv_vif_info::dentry	access:public
+ssv_vif_info::if_type	smac/dev.h	/^    enum nl80211_iftype if_type;$/;"	m	struct:ssv_vif_info	typeref:enum:ssv_vif_info::nl80211_iftype	access:public
+ssv_vif_info::sramKey	smac/dev.h	/^    struct ssv6xxx_hw_sec sramKey;$/;"	m	struct:ssv_vif_info	typeref:struct:ssv_vif_info::ssv6xxx_hw_sec	access:public
+ssv_vif_info::vif	smac/dev.h	/^    struct ieee80211_vif *vif;$/;"	m	struct:ssv_vif_info	typeref:struct:ssv_vif_info::ieee80211_vif	access:public
+ssv_vif_info::vif_priv	smac/dev.h	/^    struct ssv_vif_priv_data *vif_priv;$/;"	m	struct:ssv_vif_info	typeref:struct:ssv_vif_info::ssv_vif_priv_data	access:public
+ssv_vif_priv_data	smac/dev.h	/^struct ssv_vif_priv_data {$/;"	s
+ssv_vif_priv_data::crypto_data	smac/dev.h	/^    struct ssv_crypto_data crypto_data;$/;"	m	struct:ssv_vif_priv_data	typeref:struct:ssv_vif_priv_data::ssv_crypto_data	access:public
+ssv_vif_priv_data::force_sw_encrypt	smac/dev.h	/^    bool force_sw_encrypt;$/;"	m	struct:ssv_vif_priv_data	access:public
+ssv_vif_priv_data::group_cipher	smac/dev.h	/^    u32 group_cipher;$/;"	m	struct:ssv_vif_priv_data	access:public
+ssv_vif_priv_data::group_key_idx	smac/dev.h	/^    u8 group_key_idx;$/;"	m	struct:ssv_vif_priv_data	access:public
+ssv_vif_priv_data::has_hw_decrypt	smac/dev.h	/^    bool has_hw_decrypt;$/;"	m	struct:ssv_vif_priv_data	access:public
+ssv_vif_priv_data::has_hw_encrypt	smac/dev.h	/^    bool has_hw_encrypt;$/;"	m	struct:ssv_vif_priv_data	access:public
+ssv_vif_priv_data::is_security_valid	smac/dev.h	/^    bool is_security_valid;$/;"	m	struct:ssv_vif_priv_data	access:public
+ssv_vif_priv_data::need_sw_decrypt	smac/dev.h	/^    bool need_sw_decrypt;$/;"	m	struct:ssv_vif_priv_data	access:public
+ssv_vif_priv_data::need_sw_encrypt	smac/dev.h	/^    bool need_sw_encrypt;$/;"	m	struct:ssv_vif_priv_data	access:public
+ssv_vif_priv_data::pair_cipher	smac/dev.h	/^    u32 pair_cipher;$/;"	m	struct:ssv_vif_priv_data	access:public
+ssv_vif_priv_data::sta_asleep_mask	smac/dev.h	/^    u32 sta_asleep_mask;$/;"	m	struct:ssv_vif_priv_data	access:public
+ssv_vif_priv_data::sta_list	smac/dev.h	/^    struct list_head sta_list;$/;"	m	struct:ssv_vif_priv_data	typeref:struct:ssv_vif_priv_data::list_head	access:public
+ssv_vif_priv_data::use_mac80211_decrypt	smac/dev.h	/^    bool use_mac80211_decrypt;$/;"	m	struct:ssv_vif_priv_data	access:public
+ssv_vif_priv_data::vif_idx	smac/dev.h	/^    int vif_idx;$/;"	m	struct:ssv_vif_priv_data	access:public
+ssv_vif_priv_data::wep_cipher	smac/dev.h	/^    int wep_cipher;$/;"	m	struct:ssv_vif_priv_data	access:public
+ssv_vif_priv_data::wep_idx	smac/dev.h	/^    s8 wep_idx;$/;"	m	struct:ssv_vif_priv_data	access:public
+ssv_wake_lock	smac/ssv_pm.c	/^void ssv_wake_lock(struct ssv_softc *sc)$/;"	f	signature:(struct ssv_softc *sc)
+ssv_wake_lock	smac/ssv_pm.h	/^void ssv_wake_lock(struct ssv_softc *sc);$/;"	p	signature:(struct ssv_softc *sc)
+ssv_wake_lock_	smac/dev.h	/^    struct wake_lock ssv_wake_lock_;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::wake_lock	access:public
+ssv_wake_timeout	smac/ssv_pm.c	/^void ssv_wake_timeout(struct ssv_softc *sc, int secs)$/;"	f	signature:(struct ssv_softc *sc, int secs)
+ssv_wake_timeout	smac/ssv_pm.h	/^void ssv_wake_timeout(struct ssv_softc *sc, int secs);$/;"	p	signature:(struct ssv_softc *sc, int secs)
+ssv_wake_unlock	smac/ssv_pm.c	/^void ssv_wake_unlock(struct ssv_softc *sc)$/;"	f	signature:(struct ssv_softc *sc)
+ssv_wake_unlock	smac/ssv_pm.h	/^void ssv_wake_unlock(struct ssv_softc *sc);$/;"	p	signature:(struct ssv_softc *sc)
+ssv_wakelock_destroy	smac/ssv_pm.c	/^void ssv_wakelock_destroy(struct ssv_softc *sc)$/;"	f	signature:(struct ssv_softc *sc)
+ssv_wakelock_destroy	smac/ssv_pm.h	/^void ssv_wakelock_destroy(struct ssv_softc *sc);$/;"	p	signature:(struct ssv_softc *sc)
+ssv_wakelock_init	smac/ssv_pm.c	/^void ssv_wakelock_init(struct ssv_softc *sc)$/;"	f	signature:(struct ssv_softc *sc)
+ssv_wakelock_init	smac/ssv_pm.h	/^void ssv_wakelock_init(struct ssv_softc *sc);$/;"	p	signature:(struct ssv_softc *sc)
+ssv_wifi_control	platforms/a33-generic-wlan.c	/^static struct wifi_platform_data ssv_wifi_control = {$/;"	v	typeref:struct:wifi_platform_data	file:
+ssv_wifi_control	platforms/atm7039-action-generic-wlan.c	/^static struct wifi_platform_data ssv_wifi_control = {$/;"	v	typeref:struct:wifi_platform_data	file:
+ssv_wifi_control	platforms/h3-generic-wlan.c	/^static struct wifi_platform_data ssv_wifi_control = {$/;"	v	typeref:struct:wifi_platform_data	file:
+ssv_wifi_control	platforms/h8-generic-wlan.c	/^static struct wifi_platform_data ssv_wifi_control = {$/;"	v	typeref:struct:wifi_platform_data	file:
+ssv_wifi_control	platforms/t10-generic-wlan.c	/^static struct wifi_platform_data ssv_wifi_control = {$/;"	v	typeref:struct:wifi_platform_data	file:
+ssv_wifi_control	platforms/x1000-generic-wlan.c	/^static struct wifi_platform_data ssv_wifi_control = {$/;"	v	typeref:struct:wifi_platform_data	file:
+ssv_wifi_device	platforms/a33-generic-wlan.c	/^static struct platform_device ssv_wifi_device = {$/;"	v	typeref:struct:platform_device	file:
+ssv_wifi_device	platforms/atm7039-action-generic-wlan.c	/^static struct platform_device ssv_wifi_device = {$/;"	v	typeref:struct:platform_device	file:
+ssv_wifi_device	platforms/h3-generic-wlan.c	/^static struct platform_device ssv_wifi_device = {$/;"	v	typeref:struct:platform_device	file:
+ssv_wifi_device	platforms/h8-generic-wlan.c	/^static struct platform_device ssv_wifi_device = {$/;"	v	typeref:struct:platform_device	file:
+ssv_wifi_device	platforms/t10-generic-wlan.c	/^static struct platform_device ssv_wifi_device = {$/;"	v	typeref:struct:platform_device	file:
+ssv_wifi_device	platforms/x1000-generic-wlan.c	/^static struct platform_device ssv_wifi_device = {$/;"	v	typeref:struct:platform_device	file:
+ssv_wifi_device_release	platforms/a33-generic-wlan.c	/^void ssv_wifi_device_release(struct device *dev)$/;"	f	signature:(struct device *dev)
+ssv_wifi_device_release	platforms/atm7039-action-generic-wlan.c	/^void ssv_wifi_device_release(struct device *dev)$/;"	f	signature:(struct device *dev)
+ssv_wifi_device_release	platforms/h3-generic-wlan.c	/^void ssv_wifi_device_release(struct device *dev)$/;"	f	signature:(struct device *dev)
+ssv_wifi_device_release	platforms/h8-generic-wlan.c	/^void ssv_wifi_device_release(struct device *dev)$/;"	f	signature:(struct device *dev)
+ssv_wifi_device_release	platforms/t10-generic-wlan.c	/^void ssv_wifi_device_release(struct device *dev)$/;"	f	signature:(struct device *dev)
+ssv_wifi_device_release	platforms/x1000-generic-wlan.c	/^void ssv_wifi_device_release(struct device *dev)$/;"	f	signature:(struct device *dev)
+ssv_wifi_power	platforms/a33-generic-wlan.c	/^static int ssv_wifi_power(int on)$/;"	f	file:	signature:(int on)
+ssv_wifi_power	platforms/atm7039-action-generic-wlan.c	/^static int ssv_wifi_power(int on)$/;"	f	file:	signature:(int on)
+ssv_wifi_power	platforms/h3-generic-wlan.c	/^static int ssv_wifi_power(int on)$/;"	f	file:	signature:(int on)
+ssv_wifi_power	platforms/h8-generic-wlan.c	/^static int ssv_wifi_power(int on)$/;"	f	file:	signature:(int on)
+ssv_wifi_power	platforms/rk3036-generic-wlan.c	/^void ssv_wifi_power(void)$/;"	f	signature:(void)
+ssv_wifi_power	platforms/rk322x-generic-wlan.c	/^void ssv_wifi_power(void)$/;"	f	signature:(void)
+ssv_wifi_power	platforms/t10-generic-wlan.c	/^static int ssv_wifi_power(int on)$/;"	f	file:	signature:(int on)
+ssv_wifi_power	platforms/x1000-generic-wlan.c	/^static int ssv_wifi_power(int on)$/;"	f	file:	signature:(int on)
+ssv_wifi_reset	platforms/a33-generic-wlan.c	/^static int ssv_wifi_reset(int on)$/;"	f	file:	signature:(int on)
+ssv_wifi_reset	platforms/atm7039-action-generic-wlan.c	/^static int ssv_wifi_reset(int on)$/;"	f	file:	signature:(int on)
+ssv_wifi_reset	platforms/h3-generic-wlan.c	/^static int ssv_wifi_reset(int on)$/;"	f	file:	signature:(int on)
+ssv_wifi_reset	platforms/h8-generic-wlan.c	/^static int ssv_wifi_reset(int on)$/;"	f	file:	signature:(int on)
+ssv_wifi_reset	platforms/t10-generic-wlan.c	/^static int ssv_wifi_reset(int on)$/;"	f	file:	signature:(int on)
+ssv_wifi_reset	platforms/x1000-generic-wlan.c	/^static int ssv_wifi_reset(int on)$/;"	f	file:	signature:(int on)
+ssv_wifi_set_carddetect	platforms/a33-generic-wlan.c	/^int ssv_wifi_set_carddetect(int val)$/;"	f	signature:(int val)
+ssv_wifi_set_carddetect	platforms/atm7039-action-generic-wlan.c	/^int ssv_wifi_set_carddetect(int val)$/;"	f	signature:(int val)
+ssv_wifi_set_carddetect	platforms/h3-generic-wlan.c	/^int ssv_wifi_set_carddetect(int val)$/;"	f	signature:(int val)
+ssv_wifi_set_carddetect	platforms/h8-generic-wlan.c	/^int ssv_wifi_set_carddetect(int val)$/;"	f	signature:(int val)
+ssv_wifi_set_carddetect	platforms/t10-generic-wlan.c	/^int ssv_wifi_set_carddetect(int val)$/;"	f	signature:(int val)
+ssv_wifi_set_carddetect	platforms/x1000-generic-wlan.c	/^int ssv_wifi_set_carddetect(int val)$/;"	f	signature:(int val)
+ssv_wireless_config	umac/ssv6xxx_netlink_core.c	/^int ssv_wireless_config(struct sk_buff *skb, struct genl_info *info)$/;"	f	signature:(struct sk_buff *skb, struct genl_info *info)
+ssv_wireless_genl_policy	umac/ssv6xxx_netlink_core.c	/^static struct nla_policy ssv_wireless_genl_policy[SSV_WIRELESS_ATTR_MAX + 1] = {$/;"	v	typeref:struct:nla_policy	file:
+ssv_wireless_gnl_family	umac/ssv6xxx_netlink_core.c	/^static struct genl_family ssv_wireless_gnl_family = {$/;"	v	typeref:struct:genl_family	file:
+ssv_wireless_gnl_ops	umac/ssv6xxx_netlink_core.c	/^struct genl_ops ssv_wireless_gnl_ops[] = {$/;"	v	typeref:struct:genl_ops
+ssv_wireless_read_register	umac/ssv6xxx_netlink_core.c	/^int ssv_wireless_read_register(struct sk_buff *skb, struct genl_info *info)$/;"	f	signature:(struct sk_buff *skb, struct genl_info *info)
+ssv_wireless_register	umac/ssv6xxx_netlink_core.h	/^struct ssv_wireless_register {$/;"	s
+ssv_wireless_register::address	umac/ssv6xxx_netlink_core.h	/^ u32 address;$/;"	m	struct:ssv_wireless_register	access:public
+ssv_wireless_register::value	umac/ssv6xxx_netlink_core.h	/^ u32 value;$/;"	m	struct:ssv_wireless_register	access:public
+ssv_wireless_start_hci	umac/ssv6xxx_netlink_core.c	/^int ssv_wireless_start_hci(struct sk_buff *skb, struct genl_info *info)$/;"	f	signature:(struct sk_buff *skb, struct genl_info *info)
+ssv_wireless_test	umac/ssv6xxx_netlink_core.c	/^int ssv_wireless_test(struct sk_buff *skb, struct genl_info *info)$/;"	f	signature:(struct sk_buff *skb, struct genl_info *info)
+ssv_wireless_tx_frame	umac/ssv6xxx_netlink_core.c	/^int ssv_wireless_tx_frame(struct sk_buff *skb, struct genl_info *info)$/;"	f	signature:(struct sk_buff *skb, struct genl_info *info)
+ssv_wireless_umac_rx_raw	umac/ssv6xxx_netlink_core.c	/^static int ssv_wireless_umac_rx_raw(struct sk_buff *skb)$/;"	f	file:	signature:(struct sk_buff *skb)
+ssv_wireless_write_register	umac/ssv6xxx_netlink_core.c	/^int ssv_wireless_write_register(struct sk_buff *skb, struct genl_info *info)$/;"	f	signature:(struct sk_buff *skb, struct genl_info *info)
+ssv_wlan_fb_event_notify	smac/ssv_pm.c	/^static int ssv_wlan_fb_event_notify(struct notifier_block *self,$/;"	f	file:	signature:(struct notifier_block *self, unsigned long action, void *data)
+ssv_wlan_fb_notifier	smac/ssv_pm.c	/^struct notifier_block ssv_wlan_fb_notifier = {$/;"	v	typeref:struct:notifier_block
+ssv_wlan_power_off	platforms/t10-generic-wlan.c	/^extern int ssv_wlan_power_off(int flag);$/;"	p	file:	signature:(int flag)
+ssv_wlan_power_off	platforms/x1000-generic-wlan.c	/^extern int ssv_wlan_power_off(int flag);$/;"	p	file:	signature:(int flag)
+ssv_wlan_power_on	platforms/t10-generic-wlan.c	/^extern int ssv_wlan_power_on(int flag);$/;"	p	file:	signature:(int flag)
+ssv_wlan_power_on	platforms/x1000-generic-wlan.c	/^extern int ssv_wlan_power_on(int flag);$/;"	p	file:	signature:(int flag)
+ssv_wpa_conf_file	smartlink/airkiss.c	/^static char *ssv_wpa_conf_file = "%s\/conf\/wpa_supplicant.conf";$/;"	v	file:
+ssv_wpa_conf_file	smartlink/qqlink.c	/^static char *ssv_wpa_conf_file = "%s\/conf\/wpa_supplicant.conf";$/;"	v	file:
+ssvcabrio_fw_name	platforms/aml-s805-generic-wlan.c	/^char ssvcabrio_fw_name[50] = "ssv6051-sw.bin";$/;"	v
+ssvcabrio_fw_name	platforms/aml-s905-generic-wlan.c	/^char ssvcabrio_fw_name[50] = "ssv6051-sw.bin";$/;"	v
+ssvcabrio_int	bridge/sdiobridge.c	/^enum ssvcabrio_int$/;"	g	file:
+ssvdevice_exit	platforms/a33-generic-wlan.c	/^extern void ssvdevice_exit(void);$/;"	p	file:	signature:(void)
+ssvdevice_exit	platforms/ak3916-generic-wlan.c	/^extern void ssvdevice_exit(void);$/;"	p	file:	signature:(void)
+ssvdevice_exit	platforms/aml-s805-generic-wlan.c	/^extern void ssvdevice_exit(void);$/;"	p	file:	signature:(void)
+ssvdevice_exit	platforms/aml-s905-generic-wlan.c	/^extern void ssvdevice_exit(void);$/;"	p	file:	signature:(void)
+ssvdevice_exit	platforms/atm7039-action-generic-wlan.c	/^extern void ssvdevice_exit(void);$/;"	p	file:	signature:(void)
+ssvdevice_exit	platforms/h3-generic-wlan.c	/^extern void ssvdevice_exit(void);$/;"	p	file:	signature:(void)
+ssvdevice_exit	platforms/h8-generic-wlan.c	/^extern void ssvdevice_exit(void);$/;"	p	file:	signature:(void)
+ssvdevice_exit	platforms/rk3036-generic-wlan.c	/^extern void ssvdevice_exit(void);$/;"	p	file:	signature:(void)
+ssvdevice_exit	platforms/rk3126-generic-wlan.c	/^extern void ssvdevice_exit(void);$/;"	p	file:	signature:(void)
+ssvdevice_exit	platforms/rk3128-generic-wlan.c	/^extern void ssvdevice_exit(void);$/;"	p	file:	signature:(void)
+ssvdevice_exit	platforms/rk322x-generic-wlan.c	/^extern void ssvdevice_exit(void);$/;"	p	file:	signature:(void)
+ssvdevice_exit	platforms/t10-generic-wlan.c	/^extern void ssvdevice_exit(void);$/;"	p	file:	signature:(void)
+ssvdevice_exit	platforms/t20-generic-wlan.c	/^extern void ssvdevice_exit(void);$/;"	p	file:	signature:(void)
+ssvdevice_exit	platforms/x1000-generic-wlan.c	/^extern void ssvdevice_exit(void);$/;"	p	file:	signature:(void)
+ssvdevice_exit	platforms/xm-hi3518-generic-wlan.c	/^extern void ssvdevice_exit(void);$/;"	p	file:	signature:(void)
+ssvdevice_exit	ssvdevice/ssvdevice.c	/^EXPORT_SYMBOL(ssvdevice_exit);$/;"	v
+ssvdevice_exit	ssvdevice/ssvdevice.c	/^module_exit(ssvdevice_exit);$/;"	v
+ssvdevice_exit	ssvdevice/ssvdevice.c	/^void ssvdevice_exit(void)$/;"	f	signature:(void)
+ssvdevice_init	platforms/a33-generic-wlan.c	/^extern int ssvdevice_init(void);$/;"	p	file:	signature:(void)
+ssvdevice_init	platforms/ak3916-generic-wlan.c	/^extern int ssvdevice_init(void);$/;"	p	file:	signature:(void)
+ssvdevice_init	platforms/aml-s805-generic-wlan.c	/^extern int ssvdevice_init(void);$/;"	p	file:	signature:(void)
+ssvdevice_init	platforms/aml-s905-generic-wlan.c	/^extern int ssvdevice_init(void);$/;"	p	file:	signature:(void)
+ssvdevice_init	platforms/atm7039-action-generic-wlan.c	/^extern int ssvdevice_init(void);$/;"	p	file:	signature:(void)
+ssvdevice_init	platforms/h3-generic-wlan.c	/^extern int ssvdevice_init(void);$/;"	p	file:	signature:(void)
+ssvdevice_init	platforms/h8-generic-wlan.c	/^extern int ssvdevice_init(void);$/;"	p	file:	signature:(void)
+ssvdevice_init	platforms/rk3036-generic-wlan.c	/^extern int ssvdevice_init(void);$/;"	p	file:	signature:(void)
+ssvdevice_init	platforms/rk3126-generic-wlan.c	/^extern int ssvdevice_init(void);$/;"	p	file:	signature:(void)
+ssvdevice_init	platforms/rk3128-generic-wlan.c	/^extern int ssvdevice_init(void);$/;"	p	file:	signature:(void)
+ssvdevice_init	platforms/rk322x-generic-wlan.c	/^extern int ssvdevice_init(void);$/;"	p	file:	signature:(void)
+ssvdevice_init	platforms/t10-generic-wlan.c	/^extern int ssvdevice_init(void);$/;"	p	file:	signature:(void)
+ssvdevice_init	platforms/t20-generic-wlan.c	/^extern int ssvdevice_init(void);$/;"	p	file:	signature:(void)
+ssvdevice_init	platforms/x1000-generic-wlan.c	/^extern int ssvdevice_init(void);$/;"	p	file:	signature:(void)
+ssvdevice_init	platforms/xm-hi3518-generic-wlan.c	/^extern int ssvdevice_init(void);$/;"	p	file:	signature:(void)
+ssvdevice_init	ssvdevice/ssvdevice.c	/^EXPORT_SYMBOL(ssvdevice_init);$/;"	v
+ssvdevice_init	ssvdevice/ssvdevice.c	/^int ssvdevice_init(void)$/;"	f	signature:(void)
+ssvdevice_init	ssvdevice/ssvdevice.c	/^module_init(ssvdevice_init);$/;"	v
+ssvdevice_skb_alloc	ssvdevice/ssv_cmd.c	/^struct sk_buff *ssvdevice_skb_alloc(s32 len)$/;"	f	signature:(s32 len)
+ssvdevice_skb_alloc	ssvdevice/ssv_cmd.h	/^struct sk_buff *ssvdevice_skb_alloc(s32 len);$/;"	p	signature:(s32 len)
+ssvdevice_skb_free	ssvdevice/ssv_cmd.c	/^void ssvdevice_skb_free(struct sk_buff *skb)$/;"	f	signature:(struct sk_buff *skb)
+ssvdevice_skb_free	ssvdevice/ssv_cmd.h	/^void ssvdevice_skb_free(struct sk_buff *skb);$/;"	p	signature:(struct sk_buff *skb)
+ssvxxx_get_sta_assco_cnt	include/hal.h	/^int ssvxxx_get_sta_assco_cnt(struct ssv_softc *sc);$/;"	p	signature:(struct ssv_softc *sc)
+ssvxxx_get_sta_assco_cnt	smac/dev.c	/^int ssvxxx_get_sta_assco_cnt(struct ssv_softc *sc)$/;"	f	signature:(struct ssv_softc *sc)
+sta	smac/ampdu.h	/^    struct ieee80211_sta *sta;$/;"	m	struct:AMPDU_TID_st	typeref:struct:AMPDU_TID_st::ieee80211_sta	access:public
+sta	smac/dev.h	/^    struct ieee80211_sta *sta;$/;"	m	struct:ssv_sta_info	typeref:struct:ssv_sta_info::ieee80211_sta	access:public
+sta	smac/ssv_rc_minstrel.h	/^ struct ieee80211_sta *sta;$/;"	m	struct:ssv_minstrel_sta_priv	typeref:struct:ssv_minstrel_sta_priv::ieee80211_sta	access:public
+sta	smac/ssv_skb.h	/^    struct ieee80211_sta *sta;$/;"	m	struct:SKB_info_st	typeref:struct:SKB_info_st::ieee80211_sta	access:public
+sta	smac/ssv_skb.h	/^    struct ieee80211_sta *sta;$/;"	m	struct:ampdu_hdr_st	typeref:struct:ampdu_hdr_st::ieee80211_sta	access:public
+sta_asleep_mask	smac/dev.h	/^    u32 sta_asleep_mask;$/;"	m	struct:ssv_vif_priv_data	access:public
+sta_deci_tbl	smac/dev.h	152;"	d
+sta_deci_tbl	smac/dev_tbl.h	/^ u16 sta_deci_tbl[] =$/;"	v
+sta_idx	smac/dev.h	/^    int sta_idx;$/;"	m	struct:ssv_sta_priv_data	access:public
+sta_info	smac/dev.h	/^    struct ssv_sta_info *sta_info;$/;"	m	struct:ssv_sta_priv_data	typeref:struct:ssv_sta_priv_data::ssv_sta_info	access:public
+sta_info	smac/dev.h	/^    struct ssv_sta_info sta_info[SSV_NUM_STA];$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::ssv_sta_info	access:public
+sta_info_sem	smac/dev.h	/^    struct rw_semaphore sta_info_sem;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::rw_semaphore	access:public
+sta_key	smac/drv_comm.h	/^    struct ssv6xxx_hw_sta_key sta_key[8];$/;"	m	struct:ssv6xxx_hw_sec	typeref:struct:ssv6xxx_hw_sec::ssv6xxx_hw_sta_key	access:public
+sta_key	smac/hal/ssv6006c/ssv6006_mac.h	/^    struct ssv6006_hw_sta_key sta_key[8];$/;"	m	struct:ssv6006_hw_sec	typeref:struct:ssv6006_hw_sec::ssv6006_hw_sta_key	access:public
+sta_list	smac/dev.h	/^    struct list_head sta_list;$/;"	m	struct:ssv_vif_priv_data	typeref:struct:ssv_vif_priv_data::list_head	access:public
+sta_rc_info	smac/ssv_rc_common.h	/^    struct ssv_sta_rc_info sta_rc_info[SSV_RC_MAX_STA];$/;"	m	struct:ssv_rate_ctrl	typeref:struct:ssv_rate_ctrl::ssv_sta_rc_info	access:public
+stacfgpath	ssvdevice/ssvdevice.c	/^EXPORT_SYMBOL(stacfgpath);$/;"	v
+stacfgpath	ssvdevice/ssvdevice.c	/^static char *stacfgpath = NULL;$/;"	v	file:
+start_seq_num	smac/ampdu.h	/^ unsigned short start_seq_num;$/;"	m	struct:ssv_bar	access:public
+start_smartlink	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	/^SDK_API int start_smartlink($/;"	p	signature:( FUNC_HOP fHopping, char* szifName, FUNC_NOTIFY fNotify, char* szSN, WifiChipType chipType, int hoppingTime, int snifferTime, void* pUserData )
+start_time	smartlink/qqlink-lib-mipsel/include/TXIPCAM.h	/^ unsigned int start_time;$/;"	m	struct:_tx_history_video_range	access:public
+start_usb_acc	hwif/hwif.h	/^    int (*start_usb_acc)(struct device *child, u8 epnum);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+started	smac/dev.h	/^    volatile int started;$/;"	m	struct:ssv_encrypt_task_list	access:public
+state	smac/ampdu.h	/^    u8 state;$/;"	m	struct:AMPDU_TID_st	access:public
+state	smac/p2p.h	/^    enum ssv_cmd_state state;$/;"	m	struct:ssv_cmd_Info	typeref:enum:ssv_cmd_Info::ssv_cmd_state	access:public
+stats_update	smac/ssv_rc_common.h	/^    unsigned long stats_update;$/;"	m	struct:ssv62xx_ht	access:public
+stats_update	smac/ssv_rc_minstrel.h	/^ unsigned long stats_update;$/;"	m	struct:ssv_minstrel_sta_info	access:public
+stats_update	smac/ssv_rc_minstrel_ht.h	/^ unsigned long stats_update;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+stbc	include/ssv6200_common.h	/^    u32 stbc:2;$/;"	m	struct:ssv6200_rxphy_info	access:public
+stbc	smac/hal/ssv6006c/turismo_common.h	/^    u32 stbc:2;$/;"	m	struct:ssv6006_rxphy_info	access:public
+stop_smartlink	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	/^SDK_API void stop_smartlink();$/;"	p	signature:()
+stop_usb_acc	hwif/hwif.h	/^    int (*stop_usb_acc)(struct device *child, u8 epnum);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+store_wep_key	smac/dev.h	/^    void (*store_wep_key) (struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv, struct ssv_sta_priv_data *sta_priv,$/;"	m	struct:ssv_hal_ops	access:public
+streams	smac/ssv_rc_minstrel_ht.h	/^ unsigned int streams;$/;"	m	struct:ssv_mcs_ht_group	access:public
+structuring_msg	smartlink/qqlink-lib-mipsel/include/TXMsg.h	/^} structuring_msg;$/;"	t	typeref:struct:tag_structuring_msg
+stype_b5b4	include/ssv6200_common.h	/^    u32 stype_b5b4:2;$/;"	m	struct:ssv6200_rx_desc	access:public
+stype_b5b4	include/ssv6200_common.h	/^    u32 stype_b5b4:2;$/;"	m	struct:ssv6200_tx_desc	access:public
+stype_b5b4	smac/hal/ssv6006c/turismo_common.h	/^    u32 stype_b5b4:2;$/;"	m	struct:ssv6006_rx_desc	access:public
+stype_b5b4	smac/hal/ssv6006c/turismo_common.h	/^    u32 stype_b5b4:2;$/;"	m	struct:ssv6006_tx_desc	access:public
+succ_hist	smac/ssv_rc_common.h	/^    u64 att_hist, succ_hist;$/;"	m	struct:minstrel_rate_stats	access:public
+succ_hist	smac/ssv_rc_minstrel.h	/^ u64 succ_hist;$/;"	m	struct:ssv_minstrel_rate	access:public
+succ_hist	smac/ssv_rc_minstrel_ht.h	/^ u64 att_hist, succ_hist;$/;"	m	struct:ssv_minstrel_ht_rate_stats	access:public
+success	smac/ssv_rc_common.h	/^    unsigned int success, last_success;$/;"	m	struct:minstrel_rate_stats	access:public
+success	smac/ssv_rc_common.h	/^ u64 success;$/;"	m	struct:rc_pid_rateinfo	access:public
+success	smac/ssv_rc_minstrel.h	/^ u32 success;$/;"	m	struct:ssv_minstrel_rate	access:public
+success	smac/ssv_rc_minstrel_ht.h	/^ int success;$/;"	m	struct:ssv_minstrel_ht_rpt	access:public
+success	smac/ssv_rc_minstrel_ht.h	/^ unsigned int success, last_success;$/;"	m	struct:ssv_minstrel_ht_rate_stats	access:public
+sunxi_mci_rescan_card	platforms/a33-generic-wlan.c	/^extern void sunxi_mci_rescan_card(unsigned id, unsigned insert);$/;"	p	file:	signature:(unsigned id, unsigned insert)
+sunxi_mci_rescan_card	platforms/h3-generic-wlan.c	/^extern void sunxi_mci_rescan_card(unsigned id, unsigned insert);$/;"	p	file:	signature:(unsigned id, unsigned insert)
+sunxi_mci_rescan_card	platforms/h8-generic-wlan.c	/^extern void sunxi_mci_rescan_card(unsigned id, unsigned insert);$/;"	p	file:	signature:(unsigned id, unsigned insert)
+support_iqk_cmd	smac/dev.h	/^    bool (*support_iqk_cmd)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+support_scatter	hwif/hwif.h	/^    bool (*support_scatter)(struct device *child);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+supported	smac/ssv_rc_minstrel_ht.h	/^ u8 supported;$/;"	m	struct:ssv_minstrel_ht_mcs_group_data	access:public
+suspend	hwif/hwif.h	/^ void (*suspend)(void *param);$/;"	m	struct:ssv6xxx_platform_data	access:public
+sync_hw_key_work	smac/ampdu.h	/^void sync_hw_key_work(struct work_struct *work);$/;"	p	signature:(struct work_struct *work)
+sysplf_reset	hwif/hwif.h	/^    void (*sysplf_reset)(struct device *child, u32 addr, u32 value);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+system_path	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    char * system_path;$/;"	m	struct:_tx_init_path	access:public
+system_path_capicity	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    unsigned int system_path_capicity;$/;"	m	struct:_tx_init_path	access:public
+sz_ip	smartlink/qqlink-lib-mipsel/include/TXVoiceLink.h	/^    char sz_ip[MAX_IP_LEN];$/;"	m	struct:__anon38	access:public
+sz_ip	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	/^    char sz_ip[QLMAX_IP_LEN];$/;"	m	struct:__anon39	access:public
+sz_password	smartlink/qqlink-lib-mipsel/include/TXVoiceLink.h	/^ char sz_password[MAX_PSWD_LEN];$/;"	m	struct:__anon38	access:public
+sz_password	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	/^ char sz_password[QLMAX_PSWD_LEN];$/;"	m	struct:__anon39	access:public
+sz_ssid	smartlink/qqlink-lib-mipsel/include/TXVoiceLink.h	/^ char sz_ssid[MAX_SSID_LEN];$/;"	m	struct:__anon38	access:public
+sz_ssid	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	/^ char sz_ssid[QLMAX_SSID_LEN];$/;"	m	struct:__anon39	access:public
+ta	smac/ampdu.h	/^ unsigned char ta[6];$/;"	m	struct:ssv_bar	access:public
+ta_addr	smac/ampdu.h	/^ u8 ta_addr[ETH_ALEN];$/;"	m	struct:AMPDU_BLOCKACK_st	access:public
+tag_structuring_msg	smartlink/qqlink-lib-mipsel/include/TXMsg.h	/^typedef struct tag_structuring_msg$/;"	s
+tag_structuring_msg::digest	smartlink/qqlink-lib-mipsel/include/TXMsg.h	/^    char* digest;$/;"	m	struct:tag_structuring_msg	access:public
+tag_structuring_msg::duration	smartlink/qqlink-lib-mipsel/include/TXMsg.h	/^ unsigned int duration;$/;"	m	struct:tag_structuring_msg	access:public
+tag_structuring_msg::file_path	smartlink/qqlink-lib-mipsel/include/TXMsg.h	/^    char* file_path;$/;"	m	struct:tag_structuring_msg	access:public
+tag_structuring_msg::guide_words	smartlink/qqlink-lib-mipsel/include/TXMsg.h	/^    char* guide_words;$/;"	m	struct:tag_structuring_msg	access:public
+tag_structuring_msg::msg_id	smartlink/qqlink-lib-mipsel/include/TXMsg.h	/^ int msg_id;$/;"	m	struct:tag_structuring_msg	access:public
+tag_structuring_msg::thumb_path	smartlink/qqlink-lib-mipsel/include/TXMsg.h	/^    char* thumb_path;$/;"	m	struct:tag_structuring_msg	access:public
+tag_structuring_msg::title	smartlink/qqlink-lib-mipsel/include/TXMsg.h	/^    char* title;$/;"	m	struct:tag_structuring_msg	access:public
+tag_structuring_msg::to_targetids	smartlink/qqlink-lib-mipsel/include/TXMsg.h	/^ unsigned long long* to_targetids;$/;"	m	struct:tag_structuring_msg	access:public
+tag_structuring_msg::to_targetids_count	smartlink/qqlink-lib-mipsel/include/TXMsg.h	/^ unsigned int to_targetids_count;$/;"	m	struct:tag_structuring_msg	access:public
+tag_tx_audio_msg_element	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^typedef struct tag_tx_audio_msg_element$/;"	s
+tag_tx_audio_msg_element::audio_msg_url	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^    char * audio_msg_url;$/;"	m	struct:tag_tx_audio_msg_element	access:public
+tag_tx_audio_msg_element::voice_switch	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^    unsigned int voice_switch;$/;"	m	struct:tag_tx_audio_msg_element	access:public
+tag_tx_barrage_msg	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^typedef struct tag_tx_barrage_msg$/;"	s
+tag_tx_barrage_msg::from_group_card	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^    char * from_group_card;$/;"	m	struct:tag_tx_barrage_msg	access:public
+tag_tx_barrage_msg::from_head_url	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^    char * from_head_url;$/;"	m	struct:tag_tx_barrage_msg	access:public
+tag_tx_barrage_msg::from_nick	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^    char * from_nick;$/;"	m	struct:tag_tx_barrage_msg	access:public
+tag_tx_barrage_msg::from_target_appid	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^    unsigned int from_target_appid;$/;"	m	struct:tag_tx_barrage_msg	access:public
+tag_tx_barrage_msg::from_target_id	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^    unsigned long long from_target_id;$/;"	m	struct:tag_tx_barrage_msg	access:public
+tag_tx_barrage_msg::from_target_instid	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^    unsigned int from_target_instid;$/;"	m	struct:tag_tx_barrage_msg	access:public
+tag_tx_barrage_msg::group_id	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^    unsigned long long group_id;$/;"	m	struct:tag_tx_barrage_msg	access:public
+tag_tx_barrage_msg::group_name	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^    char * group_name;$/;"	m	struct:tag_tx_barrage_msg	access:public
+tag_tx_barrage_msg::msg_ele_array	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^    tx_barrage_msg_element * msg_ele_array;$/;"	m	struct:tag_tx_barrage_msg	access:public
+tag_tx_barrage_msg::msg_ele_count	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^    int msg_ele_count;$/;"	m	struct:tag_tx_barrage_msg	access:public
+tag_tx_barrage_msg_element	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^typedef struct tag_tx_barrage_msg_element$/;"	s
+tag_tx_barrage_msg_element::msg_ele_point	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^    void * msg_ele_point;$/;"	m	struct:tag_tx_barrage_msg_element	access:public
+tag_tx_barrage_msg_element::msg_ele_type	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^    int msg_ele_type;$/;"	m	struct:tag_tx_barrage_msg_element	access:public
+tag_tx_barrage_notify	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^typedef struct tag_tx_barrage_notify$/;"	s
+tag_tx_barrage_notify::on_receive_barrage_msg	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^ void (*on_receive_barrage_msg)(tx_barrage_msg * pMsg);$/;"	m	struct:tag_tx_barrage_notify	access:public
+tag_tx_binder_info	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^typedef struct tag_tx_binder_info$/;"	s
+tag_tx_binder_info::gender	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    int gender;$/;"	m	struct:tag_tx_binder_info	access:public
+tag_tx_binder_info::head_url	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    char head_url[1024];$/;"	m	struct:tag_tx_binder_info	access:public
+tag_tx_binder_info::nick_name	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    char nick_name[128];$/;"	m	struct:tag_tx_binder_info	access:public
+tag_tx_binder_info::tinyid	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    unsigned long long tinyid;$/;"	m	struct:tag_tx_binder_info	access:public
+tag_tx_binder_info::type	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    int type;$/;"	m	struct:tag_tx_binder_info	access:public
+tag_tx_binder_info::uin	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    unsigned long long uin;$/;"	m	struct:tag_tx_binder_info	access:public
+tag_tx_ccmsg_inst_info	smartlink/qqlink-lib-mipsel/include/TXOldInf.h	/^typedef struct tag_tx_ccmsg_inst_info$/;"	s
+tag_tx_ccmsg_inst_info::appid	smartlink/qqlink-lib-mipsel/include/TXOldInf.h	/^    unsigned int appid;$/;"	m	struct:tag_tx_ccmsg_inst_info	access:public
+tag_tx_ccmsg_inst_info::guid	smartlink/qqlink-lib-mipsel/include/TXOldInf.h	/^    char * guid;$/;"	m	struct:tag_tx_ccmsg_inst_info	access:public
+tag_tx_ccmsg_inst_info::guid_len	smartlink/qqlink-lib-mipsel/include/TXOldInf.h	/^    int guid_len;$/;"	m	struct:tag_tx_ccmsg_inst_info	access:public
+tag_tx_ccmsg_inst_info::instid	smartlink/qqlink-lib-mipsel/include/TXOldInf.h	/^    unsigned int instid;$/;"	m	struct:tag_tx_ccmsg_inst_info	access:public
+tag_tx_ccmsg_inst_info::open_appid	smartlink/qqlink-lib-mipsel/include/TXOldInf.h	/^    unsigned int open_appid;$/;"	m	struct:tag_tx_ccmsg_inst_info	access:public
+tag_tx_ccmsg_inst_info::platform	smartlink/qqlink-lib-mipsel/include/TXOldInf.h	/^    unsigned int platform;$/;"	m	struct:tag_tx_ccmsg_inst_info	access:public
+tag_tx_ccmsg_inst_info::productid	smartlink/qqlink-lib-mipsel/include/TXOldInf.h	/^    unsigned int productid;$/;"	m	struct:tag_tx_ccmsg_inst_info	access:public
+tag_tx_ccmsg_inst_info::sso_bid	smartlink/qqlink-lib-mipsel/include/TXOldInf.h	/^    unsigned int sso_bid;$/;"	m	struct:tag_tx_ccmsg_inst_info	access:public
+tag_tx_ccmsg_inst_info::target_id	smartlink/qqlink-lib-mipsel/include/TXOldInf.h	/^    unsigned long long target_id;$/;"	m	struct:tag_tx_ccmsg_inst_info	access:public
+tag_tx_data_point	smartlink/qqlink-lib-mipsel/include/TXDataPoint.h	/^typedef struct tag_tx_data_point$/;"	s
+tag_tx_data_point::id	smartlink/qqlink-lib-mipsel/include/TXDataPoint.h	/^    unsigned int id;$/;"	m	struct:tag_tx_data_point	access:public
+tag_tx_data_point::ret_code	smartlink/qqlink-lib-mipsel/include/TXDataPoint.h	/^    unsigned int ret_code;$/;"	m	struct:tag_tx_data_point	access:public
+tag_tx_data_point::seq	smartlink/qqlink-lib-mipsel/include/TXDataPoint.h	/^    unsigned int seq;$/;"	m	struct:tag_tx_data_point	access:public
+tag_tx_data_point::value	smartlink/qqlink-lib-mipsel/include/TXDataPoint.h	/^    char * value;$/;"	m	struct:tag_tx_data_point	access:public
+tag_tx_data_point_notify	smartlink/qqlink-lib-mipsel/include/TXDataPoint.h	/^typedef struct tag_tx_data_point_notify$/;"	s
+tag_tx_data_point_notify::on_receive_data_point	smartlink/qqlink-lib-mipsel/include/TXDataPoint.h	/^    void (*on_receive_data_point)(unsigned long long from_client, tx_data_point * data_points, int data_points_count);$/;"	m	struct:tag_tx_data_point_notify	access:public
+tag_tx_face_msg_element	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^typedef struct tag_tx_face_msg_element$/;"	s
+tag_tx_face_msg_element::face_index	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^    unsigned int face_index;$/;"	m	struct:tag_tx_face_msg_element	access:public
+tag_tx_file_transfer_info	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^typedef struct tag_tx_file_transfer_info$/;"	s
+tag_tx_file_transfer_info::buff_length	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^    int buff_length;$/;"	m	struct:tag_tx_file_transfer_info	access:public
+tag_tx_file_transfer_info::buff_with_file	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^    char * buff_with_file;$/;"	m	struct:tag_tx_file_transfer_info	access:public
+tag_tx_file_transfer_info::buffer_key	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^    char buffer_key[512];$/;"	m	struct:tag_tx_file_transfer_info	access:public
+tag_tx_file_transfer_info::buffer_key_len	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^    int buffer_key_len;$/;"	m	struct:tag_tx_file_transfer_info	access:public
+tag_tx_file_transfer_info::buffer_raw	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^    char * buffer_raw;$/;"	m	struct:tag_tx_file_transfer_info	access:public
+tag_tx_file_transfer_info::buffer_raw_len	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^    unsigned long long buffer_raw_len;$/;"	m	struct:tag_tx_file_transfer_info	access:public
+tag_tx_file_transfer_info::bussiness_name	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^    char bussiness_name[64];$/;"	m	struct:tag_tx_file_transfer_info	access:public
+tag_tx_file_transfer_info::channel_type	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^    int channel_type;$/;"	m	struct:tag_tx_file_transfer_info	access:public
+tag_tx_file_transfer_info::file_key	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^    char file_key[512];$/;"	m	struct:tag_tx_file_transfer_info	access:public
+tag_tx_file_transfer_info::file_path	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^    char file_path[1024];$/;"	m	struct:tag_tx_file_transfer_info	access:public
+tag_tx_file_transfer_info::file_size	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^    unsigned long long file_size;$/;"	m	struct:tag_tx_file_transfer_info	access:public
+tag_tx_file_transfer_info::file_type	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^    int file_type;$/;"	m	struct:tag_tx_file_transfer_info	access:public
+tag_tx_file_transfer_info::key_length	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^    int key_length;$/;"	m	struct:tag_tx_file_transfer_info	access:public
+tag_tx_file_transfer_info::transfer_type	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^    int transfer_type;$/;"	m	struct:tag_tx_file_transfer_info	access:public
+tag_tx_file_transfer_notify	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^typedef struct tag_tx_file_transfer_notify$/;"	s
+tag_tx_file_transfer_notify::on_file_in_come	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^    void (*on_file_in_come)(unsigned long long transfer_cookie, const tx_ccmsg_inst_info * inst_info, const tx_file_transfer_info * tran_info);$/;"	m	struct:tag_tx_file_transfer_notify	access:public
+tag_tx_file_transfer_notify::on_transfer_complete	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^    void (*on_transfer_complete)(unsigned long long transfer_cookie, int err_code, tx_file_transfer_info* tran_info);$/;"	m	struct:tag_tx_file_transfer_notify	access:public
+tag_tx_file_transfer_notify::on_transfer_progress	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^    void (*on_transfer_progress)(unsigned long long transfer_cookie, unsigned long long transfer_progress, unsigned long long max_transfer_progress);$/;"	m	struct:tag_tx_file_transfer_notify	access:public
+tag_tx_image_msg_element	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^typedef struct tag_tx_image_msg_element$/;"	s
+tag_tx_image_msg_element::guid_length	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^    int guid_length;$/;"	m	struct:tag_tx_image_msg_element	access:public
+tag_tx_image_msg_element::image_guid	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^    char * image_guid;$/;"	m	struct:tag_tx_image_msg_element	access:public
+tag_tx_image_msg_element::image_thumb_url	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^    char * image_thumb_url;$/;"	m	struct:tag_tx_image_msg_element	access:public
+tag_tx_image_msg_element::image_url	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^    char * image_url;$/;"	m	struct:tag_tx_image_msg_element	access:public
+tag_tx_text_msg_element	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^typedef struct tag_tx_text_msg_element$/;"	s
+tag_tx_text_msg_element::msg_text	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^    char * msg_text;$/;"	m	struct:tag_tx_text_msg_element	access:public
+tag_tx_tv_notify	smartlink/qqlink-lib-mipsel/include/TXTVSDK.h	/^typedef struct tag_tx_tv_notify$/;"	s
+tag_tx_tv_notify::on_bind_complete	smartlink/qqlink-lib-mipsel/include/TXTVSDK.h	/^ void (*on_bind_complete)(unsigned long long ddwID, int error);$/;"	m	struct:tag_tx_tv_notify	access:public
+tag_tx_tv_notify::on_receive_video_push	smartlink/qqlink-lib-mipsel/include/TXTVSDK.h	/^ void (*on_receive_video_push)(char * pBufReply, int nLenReply);$/;"	m	struct:tag_tx_tv_notify	access:public
+tail	smac/dev.h	/^ char *tail;$/;"	m	struct:ssv_dbg_log	access:public
+target	smac/ssv_rc_common.h	/^ unsigned int target;$/;"	m	struct:rc_pid_info	access:public
+target_id	smartlink/qqlink-lib-mipsel/include/TXOldInf.h	/^    unsigned long long target_id;$/;"	m	struct:tag_tx_ccmsg_inst_info	access:public
+target_pf	smac/ssv_rc_common.h	/^    u8 target_pf;$/;"	m	struct:ssv_rc_rate	access:public
+target_success	include/ssv_cfg.h	/^    u16 target_success;$/;"	m	struct:rc_setting	access:public
+target_success_4	include/ssv_cfg.h	/^    u16 target_success_4;$/;"	m	struct:rc_setting	access:public
+target_success_5	include/ssv_cfg.h	/^    u16 target_success_5;$/;"	m	struct:rc_setting	access:public
+target_success_67	include/ssv_cfg.h	/^    u16 target_success_67;$/;"	m	struct:rc_setting	access:public
+target_wsid	include/ssv6xxx_common.h	/^    u8 target_wsid[6];$/;"	m	struct:ssv6xxx_wsid_params	access:public
+temp_path	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    char * temp_path;$/;"	m	struct:_tx_init_path	access:public
+temp_path_capicity	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    unsigned int temp_path_capicity;$/;"	m	struct:_tx_init_path	access:public
+test_mode	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    unsigned int test_mode;$/;"	m	struct:_tx_device_info	access:public
+test_mode_default	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    test_mode_default = 0,$/;"	e	enum:tx_test_mode_enum
+test_mode_test_env	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    test_mode_test_env = 1,$/;"	e	enum:tx_test_mode_enum
+test_recv_audiodata	smartlink/qqlink-lib-mipsel/case/ipcamera/audiovideo.c	/^void test_recv_audiodata(tx_audio_encode_param *param, unsigned char *pcEncData, int nEncDataLen)$/;"	f	signature:(tx_audio_encode_param *param, unsigned char *pcEncData, int nEncDataLen)
+test_recv_audiodata	smartlink/qqlink-lib-mipsel/case/ipcamera/main.c	/^extern void test_recv_audiodata(tx_audio_encode_param *param, unsigned char *pcEncData, int nEncDataLen);$/;"	p	file:	signature:(tx_audio_encode_param *param, unsigned char *pcEncData, int nEncDataLen)
+test_restart_gop	smartlink/qqlink-lib-mipsel/case/ipcamera/audiovideo.c	/^bool test_restart_gop() {$/;"	f
+test_restart_gop	smartlink/qqlink-lib-mipsel/demo_video.c	/^bool test_restart_gop() {$/;"	f
+test_send_audio_alarm	smartlink/qqlink-lib-mipsel/case/ipcamera/alarm.c	/^void test_send_audio_alarm()$/;"	f
+test_send_audio_alarm	smartlink/qqlink-lib-mipsel/case/ipcamera/main.c	/^extern void test_send_audio_alarm();$/;"	p	file:
+test_send_pic_alarm	smartlink/qqlink-lib-mipsel/case/ipcamera/alarm.c	/^void test_send_pic_alarm()$/;"	f
+test_send_pic_alarm	smartlink/qqlink-lib-mipsel/case/ipcamera/main.c	/^extern void test_send_pic_alarm();$/;"	p	file:
+test_set_bitrate	smartlink/qqlink-lib-mipsel/case/ipcamera/audiovideo.c	/^bool test_set_bitrate(int bit_rate) {$/;"	f	signature:(int bit_rate)
+test_set_bitrate	smartlink/qqlink-lib-mipsel/case/ipcamera/main.c	/^extern bool test_set_bitrate(int bit_rate);$/;"	p	file:	signature:(int bit_rate)
+test_set_bitrate	smartlink/qqlink-lib-mipsel/demo_video.c	/^bool test_set_bitrate(int bit_rate) {$/;"	f	signature:(int bit_rate)
+test_start_camera	smartlink/qqlink-lib-mipsel/case/ipcamera/audiovideo.c	/^bool test_start_camera() {$/;"	f
+test_start_camera	smartlink/qqlink-lib-mipsel/case/ipcamera/main.c	/^extern bool test_start_camera();$/;"	p	file:
+test_start_camera	smartlink/qqlink-lib-mipsel/demo_video.c	/^bool test_start_camera() {$/;"	f
+test_start_mic	smartlink/qqlink-lib-mipsel/case/ipcamera/audiovideo.c	/^bool test_start_mic() {$/;"	f
+test_start_mic	smartlink/qqlink-lib-mipsel/case/ipcamera/main.c	/^extern bool test_start_mic();$/;"	p	file:
+test_start_mic	smartlink/qqlink-lib-mipsel/demo_video.c	/^bool test_start_mic() {$/;"	f
+test_stop_camera	smartlink/qqlink-lib-mipsel/case/ipcamera/audiovideo.c	/^bool test_stop_camera() {$/;"	f
+test_stop_camera	smartlink/qqlink-lib-mipsel/case/ipcamera/main.c	/^extern bool test_stop_camera();$/;"	p	file:
+test_stop_camera	smartlink/qqlink-lib-mipsel/demo_video.c	/^bool test_stop_camera() {$/;"	f
+test_stop_mic	smartlink/qqlink-lib-mipsel/case/ipcamera/audiovideo.c	/^bool test_stop_mic() {$/;"	f
+test_stop_mic	smartlink/qqlink-lib-mipsel/case/ipcamera/main.c	/^extern bool test_stop_mic();$/;"	p	file:
+test_stop_mic	smartlink/qqlink-lib-mipsel/demo_video.c	/^bool test_stop_mic() {$/;"	f
+tfm	smac/sec_ccmp.c	/^ struct crypto_cipher *tfm;$/;"	m	struct:lib80211_ccmp_data	typeref:struct:lib80211_ccmp_data::crypto_cipher	file:	access:public
+thermal_monitor	smac/dev.h	/^    bool thermal_monitor;$/;"	m	struct:ssv_softc	access:public
+thermal_monitor_counter	smac/dev.h	/^    int thermal_monitor_counter;$/;"	m	struct:ssv_softc	access:public
+thermal_monitor_work	smac/dev.h	/^    struct work_struct thermal_monitor_work;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::work_struct	access:public
+this_attempt	smac/ssv_rc_common.h	/^ unsigned long this_attempt;$/;"	m	struct:rc_pid_rateinfo	access:public
+this_fail	smac/ssv_rc_common.h	/^ unsigned long this_fail;$/;"	m	struct:rc_pid_rateinfo	access:public
+this_success	smac/ssv_rc_common.h	/^ unsigned long this_success;$/;"	m	struct:rc_pid_rateinfo	access:public
+thread_enc_id	smartlink/qqlink-lib-mipsel/case/ipcamera/audiovideo.c	/^static pthread_t thread_enc_id = 0;$/;"	v	file:
+thread_enc_id	smartlink/qqlink-lib-mipsel/demo_video.c	/^static pthread_t thread_enc_id = 0;$/;"	v	file:
+throughput	smac/ssv_rc_common.h	/^ u32 throughput;$/;"	m	struct:rc_pid_rateinfo	access:public
+thumb_path	smartlink/qqlink-lib-mipsel/include/TXMsg.h	/^    char* thumb_path;$/;"	m	struct:tag_structuring_msg	access:public
+tid	smac/dev.h	/^    struct AMPDU_TID_st *tid[MAX_TID];$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::AMPDU_TID_st	access:public
+tid_info	smac/ampdu.h	/^    u16 tid_info:4;$/;"	m	struct:AMPDU_BLOCKACK_st	access:public
+tid_no	smac/dev.h	/^ u8 tid_no;$/;"	m	struct:aggr_ssn	access:public
+tid_window_fops	smac/ampdu.c	/^static const struct file_operations tid_window_fops = { .read =$/;"	v	typeref:struct:file_operations	file:
+tidno	smac/ampdu.h	/^    u32 tidno;$/;"	m	struct:AMPDU_TID_st	access:public
+tim_cnt	smac/dev.h	/^ u8 tim_cnt;$/;"	m	struct:ssv6xxx_beacon_info	access:public
+tim_offset	smac/dev.h	/^ u8 tim_offset;$/;"	m	struct:ssv6xxx_beacon_info	access:public
+tim_set	smac/dev.h	/^    bool tim_set;$/;"	m	struct:ssv_sta_info	access:public
+timestamp	smac/ampdu.h	/^    volatile unsigned long timestamp;$/;"	m	struct:AMPDU_TID_st	access:public
+timestamp	smac/ssv_skb.h	/^    ktime_t timestamp;$/;"	m	struct:SKB_info_st	access:public
+tinyid	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    unsigned long long tinyid;$/;"	m	struct:tag_tx_binder_info	access:public
+title	smartlink/qqlink-lib-mipsel/include/TXMsg.h	/^    char* title;$/;"	m	struct:tag_structuring_msg	access:public
+tkip_mixing_phase1	smac/sec_tkip.c	/^static void tkip_mixing_phase1(u16 * TTAK, const u8 * TK, const u8 * TA,$/;"	f	file:	signature:(u16 * TTAK, const u8 * TK, const u8 * TA, u32 IV32)
+tkip_mixing_phase2	smac/sec_tkip.c	/^static void tkip_mixing_phase2(u8 * WEPSeed, const u8 * TK, const u16 * TTAK,$/;"	f	file:	signature:(u8 * WEPSeed, const u8 * TK, const u16 * TTAK, u16 IV16)
+tkip_mmic_err	smac/hal/ssv6006c/turismo_common.h	/^    u32 tkip_mmic_err:1;$/;"	m	struct:ssv6006_rx_desc	access:public
+tkip_replay_check	smac/sec_tkip.c	/^static inline int tkip_replay_check(u32 iv32_n, u16 iv16_n,$/;"	f	file:	signature:(u32 iv32_n, u16 iv16_n, u32 iv32_o, u16 iv16_o)
+tmp_data	hwif/sdio/sdio.c	/^    struct ssv6xxx_platform_data tmp_data;$/;"	m	struct:ssv6xxx_sdio_glue	typeref:struct:ssv6xxx_sdio_glue::ssv6xxx_platform_data	file:	access:public
+tmp_data	hwif/usb/usb.c	/^ struct ssv6xxx_platform_data tmp_data;$/;"	m	struct:ssv6xxx_usb_glue	typeref:struct:ssv6xxx_usb_glue::ssv6xxx_platform_data	file:	access:public
+tmp_rate_idx	smac/ssv_rc_common.h	/^    u8 tmp_rate_idx;$/;"	m	struct:rc_pid_sta_info	access:public
+to_ssv6xxx_usb_dev	hwif/usb/usb.c	90;"	d	file:
+to_targetids	smartlink/qqlink-lib-mipsel/include/TXMsg.h	/^ unsigned long long* to_targetids;$/;"	m	struct:tag_structuring_msg	access:public
+to_targetids_count	smartlink/qqlink-lib-mipsel/include/TXMsg.h	/^ unsigned int to_targetids_count;$/;"	m	struct:tag_structuring_msg	access:public
+top	smac/dev.h	/^ char *top;$/;"	m	struct:ssv_dbg_log	access:public
+total_frames	include/ssv6xxx_common.h	/^ u32 total_frames;$/;"	m	struct:sdio_rxtput_cfg	access:public
+total_packets	smac/ssv_rc_common.h	/^    unsigned int total_packets;$/;"	m	struct:ssv62xx_ht	access:public
+total_packets	smac/ssv_rc_minstrel_ht.h	/^ u64 total_packets;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+totalsize	smac/dev.h	/^ int totalsize;$/;"	m	struct:ssv_dbg_log	access:public
+transfer_channeltype_FTN	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^    transfer_channeltype_FTN = 1,$/;"	e	enum:tx_file_transfer_channeltype
+transfer_channeltype_MINI	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^    transfer_channeltype_MINI = 2,$/;"	e	enum:tx_file_transfer_channeltype
+transfer_filetype_audio	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^    transfer_filetype_audio = 3,$/;"	e	enum:tx_file_transfer_filetype
+transfer_filetype_image	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^    transfer_filetype_image = 1,$/;"	e	enum:tx_file_transfer_filetype
+transfer_filetype_other	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^    transfer_filetype_other = 4,$/;"	e	enum:tx_file_transfer_filetype
+transfer_filetype_video	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^    transfer_filetype_video = 2,$/;"	e	enum:tx_file_transfer_filetype
+transfer_type	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^    int transfer_type;$/;"	m	struct:tag_tx_file_transfer_info	access:public
+transfer_type_c2c_in	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^    transfer_type_c2c_in = 3,$/;"	e	enum:tx_file_transfer_type
+transfer_type_c2c_out	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^    transfer_type_c2c_out = 4,$/;"	e	enum:tx_file_transfer_type
+transfer_type_download	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^    transfer_type_download = 2,$/;"	e	enum:tx_file_transfer_type
+transfer_type_upload	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^    transfer_type_upload = 1,$/;"	e	enum:tx_file_transfer_type
+transfet_type_none	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^    transfet_type_none = 0,$/;"	e	enum:tx_file_transfer_type
+translate_func	ssvdevice/ssv_cmd.h	/^    int (*translate_func)(u8 *, void *, u32);$/;"	m	struct:ssv6xxx_cfg_cmd_table	access:public
+trap_data	smac/dev.h	/^ struct ssv_trap_data trap_data;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::ssv_trap_data	access:public
+tried_rates	include/ssv6200_common.h	/^    struct ssv62xx_tx_rate tried_rates[SSV62XX_TX_MAX_RATES];$/;"	m	struct:ampdu_ba_notify_data	typeref:struct:ampdu_ba_notify_data::ssv62xx_tx_rate	access:public
+trigger_tx_rx	hwif/hwif.h	/^    int (*trigger_tx_rx)(struct device *child);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+true	smartlink/qqlink-lib-mipsel/include/TXSDKCommonDef.h	21;"	d
+try_cnt0	smac/hal/ssv6006c/turismo_common.h	/^    u32 try_cnt0:4;$/;"	m	struct:ssv6006_tx_desc	access:public
+try_cnt1	smac/hal/ssv6006c/turismo_common.h	/^    u32 try_cnt1:4;$/;"	m	struct:ssv6006_tx_desc	access:public
+try_cnt2	smac/hal/ssv6006c/turismo_common.h	/^    u32 try_cnt2:4;$/;"	m	struct:ssv6006_tx_desc	access:public
+try_cnt3	smac/hal/ssv6006c/turismo_common.h	/^    u32 try_cnt3:4;$/;"	m	struct:ssv6006_tx_desc	access:public
+turismo_inter_cal	smac/hal/ssv6006c/turismo_common.c	/^void turismo_inter_cal(SSV_HW *sh)$/;"	f	signature:(SSV_HW *sh)
+turismo_inter_cal	smac/hal/ssv6006c/turismo_common.h	/^extern void turismo_inter_cal(SSV_HW *sh);$/;"	p	signature:(SSV_HW *sh)
+turismo_post_cal	smac/hal/ssv6006c/turismo_common.c	/^void turismo_post_cal(SSV_HW *sh)$/;"	f	signature:(SSV_HW *sh)
+turismo_post_cal	smac/hal/ssv6006c/turismo_common.h	/^extern void turismo_post_cal(SSV_HW *sh);$/;"	p	signature:(SSV_HW *sh)
+turismo_pre_cal	smac/hal/ssv6006c/turismo_common.c	/^void turismo_pre_cal(SSV_HW *sh)$/;"	f	signature:(SSV_HW *sh)
+turismo_pre_cal	smac/hal/ssv6006c/turismo_common.h	/^extern void turismo_pre_cal(SSV_HW *sh);$/;"	p	signature:(SSV_HW *sh)
+tx	smac/dev.h	/^    struct ssv_tx tx;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::ssv_tx	access:public
+txResourceControl	include/ssv6200.h	/^struct txResourceControl {$/;"	s
+txResourceControl	include/ssv6xxx_cfg.h	/^struct txResourceControl {$/;"	s
+txResourceControl::edca0	include/ssv6200.h	/^    u32 edca0:4;$/;"	m	struct:txResourceControl	access:public
+txResourceControl::edca0	include/ssv6xxx_cfg.h	/^    u32 edca0:4;$/;"	m	struct:txResourceControl	access:public
+txResourceControl::edca1	include/ssv6200.h	/^    u32 edca1:4;$/;"	m	struct:txResourceControl	access:public
+txResourceControl::edca1	include/ssv6xxx_cfg.h	/^    u32 edca1:4;$/;"	m	struct:txResourceControl	access:public
+txResourceControl::edca2	include/ssv6200.h	/^    u32 edca2:5;$/;"	m	struct:txResourceControl	access:public
+txResourceControl::edca2	include/ssv6xxx_cfg.h	/^    u32 edca2:5;$/;"	m	struct:txResourceControl	access:public
+txResourceControl::edca3	include/ssv6200.h	/^    u32 edca3:5;$/;"	m	struct:txResourceControl	access:public
+txResourceControl::edca3	include/ssv6xxx_cfg.h	/^    u32 edca3:5;$/;"	m	struct:txResourceControl	access:public
+txResourceControl::txUseID	include/ssv6200.h	/^    u32 txUseID:6;$/;"	m	struct:txResourceControl	access:public
+txResourceControl::txUseID	include/ssv6xxx_cfg.h	/^    u32 txUseID:6;$/;"	m	struct:txResourceControl	access:public
+txResourceControl::txUsePage	include/ssv6200.h	/^    u32 txUsePage:8;$/;"	m	struct:txResourceControl	access:public
+txResourceControl::txUsePage	include/ssv6xxx_cfg.h	/^    u32 txUsePage:8;$/;"	m	struct:txResourceControl	access:public
+txUseID	include/ssv6200.h	/^    u32 txUseID:6;$/;"	m	struct:txResourceControl	access:public
+txUseID	include/ssv6xxx_cfg.h	/^    u32 txUseID:6;$/;"	m	struct:txResourceControl	access:public
+txUsePage	include/ssv6200.h	/^    u32 txUsePage:8;$/;"	m	struct:txResourceControl	access:public
+txUsePage	include/ssv6xxx_cfg.h	/^    u32 txUsePage:8;$/;"	m	struct:txResourceControl	access:public
+tx_ack_app	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^SDK_API int tx_ack_app(unsigned int ip, unsigned int port);$/;"	p	signature:(unsigned int ip, unsigned int port)
+tx_ack_data_point	smartlink/qqlink-lib-mipsel/include/TXDataPoint.h	/^SDK_API int tx_ack_data_point(unsigned long long from_client, unsigned int id, char * value, unsigned int seq, unsigned int ret_code, unsigned int * cookie, on_ack_data_point_ret ret_callback);$/;"	p	signature:(unsigned long long from_client, unsigned int id, char * value, unsigned int seq, unsigned int ret_code, unsigned int * cookie, on_ack_data_point_ret ret_callback)
+tx_ack_data_points	smartlink/qqlink-lib-mipsel/include/TXDataPoint.h	/^SDK_API int tx_ack_data_points(unsigned long long from_client, tx_data_point * data_points, int data_points_count, unsigned int * cookie, on_ack_data_point_ret ret_callback);$/;"	p	signature:(unsigned long long from_client, tx_data_point * data_points, int data_points_count, unsigned int * cookie, on_ack_data_point_ret ret_callback)
+tx_ack_ota_result	smartlink/qqlink-lib-mipsel/include/TXOTA.h	/^SDK_API void tx_ack_ota_result(int ret_code, char* err_msg);$/;"	p	signature:(int ret_code, char* err_msg)
+tx_audio_encode_param	smartlink/qqlink-lib-mipsel/include/TXAudioVideo.h	/^} tx_audio_encode_param;$/;"	t	typeref:struct:_tx_audio_encode_param
+tx_audio_msg_element	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^}tx_audio_msg_element;$/;"	t	typeref:struct:tag_tx_audio_msg_element
+tx_av_callback	smartlink/qqlink-lib-mipsel/include/TXAudioVideo.h	/^} tx_av_callback;$/;"	t	typeref:struct:_tx_av_callback
+tx_b	smac/sec_ccmp.c	/^ u8 *tx_b0, *tx_b, *tx_e, *tx_s0;$/;"	m	struct:lib80211_ccmp_data	file:	access:public
+tx_b	smac/sec_ccmp.c	/^ u8 tx_b0[AES_BLOCK_LEN], tx_b[AES_BLOCK_LEN],$/;"	m	struct:lib80211_ccmp_data	file:	access:public
+tx_b0	smac/sec_ccmp.c	/^ u8 *tx_b0, *tx_b, *tx_e, *tx_s0;$/;"	m	struct:lib80211_ccmp_data	file:	access:public
+tx_b0	smac/sec_ccmp.c	/^ u8 tx_b0[AES_BLOCK_LEN], tx_b[AES_BLOCK_LEN],$/;"	m	struct:lib80211_ccmp_data	file:	access:public
+tx_barrage_msg	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^}tx_barrage_msg;$/;"	t	typeref:struct:tag_tx_barrage_msg
+tx_barrage_msg_element	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^}tx_barrage_msg_element;$/;"	t	typeref:struct:tag_tx_barrage_msg_element
+tx_barrage_msg_element_type	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^enum tx_barrage_msg_element_type$/;"	g
+tx_barrage_notify	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^}tx_barrage_notify;$/;"	t	typeref:struct:tag_tx_barrage_notify
+tx_binder_gender	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^enum tx_binder_gender$/;"	g
+tx_binder_info	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^}tx_binder_info;$/;"	t	typeref:struct:tag_tx_binder_info
+tx_binder_type	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^enum tx_binder_type$/;"	g
+tx_burst	include/ssv6200_common.h	/^    u32 tx_burst:1;$/;"	m	struct:ssv6200_tx_desc	access:public
+tx_burst_obsolete	smac/hal/ssv6006c/turismo_common.h	/^    u32 tx_burst_obsolete:1;$/;"	m	struct:ssv6006_tx_desc	access:public
+tx_cancel_transfer	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^SDK_API int tx_cancel_transfer(unsigned long long transfer_cookie);$/;"	p	signature:(unsigned long long transfer_cookie)
+tx_ccmsg_inst_info	smartlink/qqlink-lib-mipsel/include/TXOldInf.h	/^}tx_ccmsg_inst_info;$/;"	t	typeref:struct:tag_tx_ccmsg_inst_info
+tx_data_point	smartlink/qqlink-lib-mipsel/include/TXDataPoint.h	/^}tx_data_point;$/;"	t	typeref:struct:tag_tx_data_point
+tx_data_point_notify	smartlink/qqlink-lib-mipsel/include/TXDataPoint.h	/^} tx_data_point_notify;$/;"	t	typeref:struct:tag_tx_data_point_notify
+tx_desc_len	smac/dev.h	/^    u32 tx_desc_len;$/;"	m	struct:ssv_hw	access:public
+tx_device_info	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^} tx_device_info;$/;"	t	typeref:struct:_tx_device_info
+tx_device_notify	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^} tx_device_notify;$/;"	t	typeref:struct:_tx_device_notify
+tx_device_relogin	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^SDK_API int tx_device_relogin();$/;"	p	signature:()
+tx_done_q	smac/dev.h	/^    struct sk_buff_head tx_done_q;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::sk_buff_head	access:public
+tx_download_file	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^SDK_API int tx_download_file(int channeltype, int filetype, char * file_key, int key_length, unsigned long long * transfer_cookie);$/;"	p	signature:(int channeltype, int filetype, char * file_key, int key_length, unsigned long long * transfer_cookie)
+tx_e	smac/sec_ccmp.c	/^     tx_e[AES_BLOCK_LEN], tx_s0[AES_BLOCK_LEN];$/;"	m	struct:lib80211_ccmp_data	file:	access:public
+tx_e	smac/sec_ccmp.c	/^ u8 *tx_b0, *tx_b, *tx_e, *tx_s0;$/;"	m	struct:lib80211_ccmp_data	file:	access:public
+tx_endpoint	hwif/usb/usb.c	/^ struct ssv6xxx_tx_endpoint tx_endpoint;$/;"	m	struct:ssv6xxx_usb_glue	typeref:struct:ssv6xxx_usb_glue::ssv6xxx_tx_endpoint	file:	access:public
+tx_erase_all_binders	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^SDK_API int tx_erase_all_binders(on_erase_all_binders callback);$/;"	p	signature:(on_erase_all_binders callback)
+tx_exit_device	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^SDK_API int tx_exit_device();$/;"	p	signature:()
+tx_face_msg_element	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^}tx_face_msg_element;$/;"	t	typeref:struct:tag_tx_face_msg_element
+tx_file_transfer_channeltype	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^enum tx_file_transfer_channeltype$/;"	g
+tx_file_transfer_filetype	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^enum tx_file_transfer_filetype$/;"	g
+tx_file_transfer_info	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^}tx_file_transfer_info;$/;"	t	typeref:struct:tag_tx_file_transfer_info
+tx_file_transfer_notify	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^}tx_file_transfer_notify;$/;"	t	typeref:struct:tag_tx_file_transfer_notify
+tx_file_transfer_type	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^enum tx_file_transfer_type$/;"	g
+tx_fill_audio	smartlink/qqlink-lib-mipsel/include/TXVoiceLink.h	/^SDK_API void tx_fill_audio(signed short* audio, int nlen);$/;"	p	signature:(signed short* audio, int nlen)
+tx_flags	hci/ssv_hci.h	/^    u32 tx_flags;$/;"	m	struct:ssv_hw_txq	access:public
+tx_flags	smac/ssv_rc_minstrel_ht.h	/^ u32 tx_flags;$/;"	m	struct:ssv_minstrel_ht_sta	access:public
+tx_frag	smac/dev.h	/^    u32 tx_frag[SSV_HW_TXQ_NUM];$/;"	m	struct:ssv_tx	access:public
+tx_get_binder_list	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^SDK_API int tx_get_binder_list(tx_binder_info * pBinderList, int* nCount, on_get_binder_list_result callback);$/;"	p	signature:(tx_binder_info * pBinderList, int* nCount, on_get_binder_list_result callback)
+tx_get_minidownload_url	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^SDK_API int tx_get_minidownload_url(char* fileId, int fileType, char* downloadUrl);$/;"	p	signature:(char* fileId, int fileType, char* downloadUrl)
+tx_get_sdk_version	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^SDK_API int tx_get_sdk_version(unsigned int *main_ver, unsigned int *sub_ver, unsigned int *build_no);$/;"	p	signature:(unsigned int *main_ver, unsigned int *sub_ver, unsigned int *build_no)
+tx_get_self_din	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^SDK_API unsigned long long tx_get_self_din();$/;"	p	signature:()
+tx_get_server_time	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^SDK_API int tx_get_server_time();$/;"	p	signature:()
+tx_get_tinyid_by_uin	smartlink/qqlink-lib-mipsel/include/TXTVSDK.h	/^SDK_API unsigned long long tx_get_tinyid_by_uin(unsigned long long ddwID);$/;"	p	signature:(unsigned long long ddwID)
+tx_get_uin_by_tinyid	smartlink/qqlink-lib-mipsel/include/TXTVSDK.h	/^SDK_API unsigned long long tx_get_uin_by_tinyid(unsigned long long ddwID);$/;"	p	signature:(unsigned long long ddwID)
+tx_hdr	smac/sec_tkip.c	/^ u8 rx_hdr[16], tx_hdr[16];$/;"	m	struct:lib80211_tkip_data	file:	access:public
+tx_history_video_notify	smartlink/qqlink-lib-mipsel/include/TXIPCAM.h	/^} tx_history_video_notify;$/;"	t	typeref:struct:_tx_history_video_notify
+tx_history_video_range	smartlink/qqlink-lib-mipsel/include/TXIPCAM.h	/^} tx_history_video_range;$/;"	t	typeref:struct:_tx_history_video_range
+tx_id_remain	include/ssv6xxx_common.h	/^    u32 tx_id_remain:8;$/;"	m	struct:hci_rx_aggr_info	access:public
+tx_id_threshold	include/ssv6xxx_common.h	/^ u32 tx_id_threshold;$/;"	m	struct:ssv6xxx_tx_hw_info	access:public
+tx_id_threshold	include/ssv_cfg.h	/^ u32 tx_id_threshold;$/;"	m	struct:ssv6xxx_cfg	access:public
+tx_id_used	include/ssv6200_common.h	/^    u32 tx_id_used:8;$/;"	m	struct:ssv6200_rx_desc	access:public
+tx_image_msg_element	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^}tx_image_msg_element;$/;"	t	typeref:struct:tag_tx_image_msg_element
+tx_info	hci/hctrl.h	/^ struct ssv6xxx_tx_hw_info tx_info;$/;"	m	struct:ssv6xxx_hci_ctrl	typeref:struct:ssv6xxx_hci_ctrl::ssv6xxx_tx_hw_info	access:public
+tx_info	smac/dev.h	/^ struct ssv6xxx_tx_hw_info tx_info;$/;"	m	struct:ssv_hw	typeref:struct:ssv_hw::ssv6xxx_tx_hw_info	access:public
+tx_init_data_point	smartlink/qqlink-lib-mipsel/include/TXDataPoint.h	/^SDK_API int tx_init_data_point(const tx_data_point_notify *notify);$/;"	p	signature:(const tx_data_point_notify *notify)
+tx_init_decoder	smartlink/qqlink-lib-mipsel/include/TXVoiceLink.h	/^SDK_API int tx_init_decoder(VL_FUNC_NOTIFY func, int samplerate);$/;"	p	signature:(VL_FUNC_NOTIFY func, int samplerate)
+tx_init_device	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^SDK_API int tx_init_device(tx_device_info *info, tx_device_notify *notify, tx_init_path* init_path);$/;"	p	signature:(tx_device_info *info, tx_device_notify *notify, tx_init_path* init_path)
+tx_init_file_transfer	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^SDK_API int tx_init_file_transfer(tx_file_transfer_notify notify, char * path_recv_file);$/;"	p	signature:(tx_file_transfer_notify notify, char * path_recv_file)
+tx_init_history_video_notify	smartlink/qqlink-lib-mipsel/include/TXIPCAM.h	/^SDK_API void tx_init_history_video_notify(tx_history_video_notify *notify);$/;"	p	signature:(tx_history_video_notify *notify)
+tx_init_ota	smartlink/qqlink-lib-mipsel/include/TXOTA.h	/^SDK_API int tx_init_ota(tx_ota_notify * notify, int replace_timeout , char* target_pathname);$/;"	p	signature:(tx_ota_notify * notify, int replace_timeout , char* target_pathname)
+tx_init_path	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^} tx_init_path;$/;"	t	typeref:struct:_tx_init_path
+tx_ipcamera_notify	smartlink/qqlink-lib-mipsel/include/TXIPCAM.h	/^} tx_ipcamera_notify;$/;"	t	typeref:struct:_tx_ipcamera_notify
+tx_ipcamera_set_callback	smartlink/qqlink-lib-mipsel/include/TXIPCAM.h	/^SDK_API int tx_ipcamera_set_callback(tx_ipcamera_notify *notify);$/;"	p	signature:(tx_ipcamera_notify *notify)
+tx_irq_count	hci/hctrl.h	/^    u32 tx_irq_count;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+tx_iv16	smac/sec_tkip.c	/^ u16 tx_iv16;$/;"	m	struct:lib80211_tkip_data	file:	access:public
+tx_iv32	smac/sec_tkip.c	/^ u32 tx_iv32;$/;"	m	struct:lib80211_tkip_data	file:	access:public
+tx_log_func	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^typedef void (*tx_log_func)(int level, const char* module, int line, const char* message);$/;"	t
+tx_lowthreshold_id_trigger	include/ssv6xxx_common.h	/^ u32 tx_lowthreshold_id_trigger;$/;"	m	struct:ssv6xxx_tx_hw_info	access:public
+tx_lowthreshold_page_trigger	include/ssv6xxx_common.h	/^ u32 tx_lowthreshold_page_trigger;$/;"	m	struct:ssv6xxx_tx_hw_info	access:public
+tx_network_type	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^enum tx_network_type$/;"	g
+tx_num_failed	smac/ssv_rc_common.h	/^    u16 tx_num_failed;$/;"	m	struct:rc_pid_sta_info	access:public
+tx_num_xmit	smac/ssv_rc_common.h	/^    u16 tx_num_xmit;$/;"	m	struct:rc_pid_sta_info	access:public
+tx_ota_notify	smartlink/qqlink-lib-mipsel/include/TXOTA.h	/^} tx_ota_notify;$/;"	t	typeref:struct:_tx_ota_notify
+tx_page_available	smac/dev.h	/^    u32 tx_page_available;$/;"	m	struct:ssv_hw	access:public
+tx_page_remain	include/ssv6xxx_common.h	/^    u32 tx_page_remain:9;$/;"	m	struct:hci_rx_aggr_info	access:public
+tx_page_threshold	include/ssv6xxx_common.h	/^ u32 tx_page_threshold;$/;"	m	struct:ssv6xxx_tx_hw_info	access:public
+tx_page_threshold	include/ssv_cfg.h	/^ u32 tx_page_threshold;$/;"	m	struct:ssv6xxx_cfg	access:public
+tx_page_used	include/ssv6200_common.h	/^    u32 tx_page_used:9;$/;"	m	struct:ssv6200_rx_desc	access:public
+tx_phase1_done	smac/sec_tkip.c	/^ int tx_phase1_done;$/;"	m	struct:lib80211_tkip_data	file:	access:public
+tx_pkt	hci/ssv_hci.h	/^    u32 tx_pkt;$/;"	m	struct:ssv_hw_txq	access:public
+tx_pkt	smac/dev.h	/^    u32 tx_pkt[SSV_HW_TXQ_NUM];$/;"	m	struct:ssv_tx	access:public
+tx_pkt_run_no	smac/dev.h	/^    u16 tx_pkt_run_no;$/;"	m	struct:aggr_ssn	access:public
+tx_pkt_run_no	smac/dev.h	/^    u8 tx_pkt_run_no;$/;"	m	struct:ssv_softc	access:public
+tx_pkt_run_no	smac/hal/ssv6006c/turismo_common.h	/^    u32 tx_pkt_run_no:8;$/;"	m	struct:ssv6006_tx_desc	access:public
+tx_pkt_run_no_lock	smac/dev.h	/^    spinlock_t tx_pkt_run_no_lock;$/;"	m	struct:ssv_softc	access:public
+tx_pn	smac/sec_ccmp.c	/^ u8 tx_pn[CCMP_PN_LEN];$/;"	m	struct:lib80211_ccmp_data	file:	access:public
+tx_pn_h	smac/drv_comm.h	/^    u32 tx_pn_h;$/;"	m	struct:ssv6xxx_hw_key	access:public
+tx_pn_h	smac/hal/ssv6006c/ssv6006_mac.h	/^    u32 tx_pn_h;$/;"	m	struct:ssv6006_bss	access:public
+tx_pn_h	smac/hal/ssv6006c/ssv6006_mac.h	/^    u32 tx_pn_h;$/;"	m	struct:ssv6006_hw_sta_key	access:public
+tx_pn_l	smac/drv_comm.h	/^ u32 tx_pn_l;$/;"	m	struct:ssv6xxx_hw_key	access:public
+tx_pn_l	smac/hal/ssv6006c/ssv6006_mac.h	/^    u32 tx_pn_l;$/;"	m	struct:ssv6006_bss	access:public
+tx_pn_l	smac/hal/ssv6006c/ssv6006_mac.h	/^    u32 tx_pn_l;$/;"	m	struct:ssv6006_hw_sta_key	access:public
+tx_poll_work	smac/dev.h	/^    struct work_struct tx_poll_work;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::work_struct	access:public
+tx_power_index_1	include/ssv_cfg.h	/^    u32 tx_power_index_1;$/;"	m	struct:ssv6xxx_cfg	access:public
+tx_power_index_2	include/ssv_cfg.h	/^    u32 tx_power_index_2;$/;"	m	struct:ssv6xxx_cfg	access:public
+tx_q_empty	smac/dev.h	/^    bool tx_q_empty;$/;"	m	struct:ssv_softc	access:public
+tx_rate_update	smac/dev.h	/^    void (*tx_rate_update)(struct ssv_softc *sc, struct sk_buff *skb);$/;"	m	struct:ssv_hal_ops	access:public
+tx_reg_file_transfer_filter	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^SDK_API int tx_reg_file_transfer_filter(char * bussiness_name, tx_file_transfer_notify notify);$/;"	p	signature:(char * bussiness_name, tx_file_transfer_notify notify)
+tx_report	include/ssv6200_common.h	/^    u32 tx_report:1;$/;"	m	struct:ssv6200_tx_desc	access:public
+tx_report_data_point	smartlink/qqlink-lib-mipsel/include/TXDataPoint.h	/^SDK_API int tx_report_data_point(unsigned int id, char * value, unsigned int * cookie, on_report_data_point_ret ret_callback);$/;"	p	signature:(unsigned int id, char * value, unsigned int * cookie, on_report_data_point_ret ret_callback)
+tx_report_data_points	smartlink/qqlink-lib-mipsel/include/TXDataPoint.h	/^SDK_API int tx_report_data_points(tx_data_point * data_points, int data_points_count, unsigned int * cookie, on_report_data_point_ret ret_callback);$/;"	p	signature:(tx_data_point * data_points, int data_points_count, unsigned int * cookie, on_report_data_point_ret ret_callback)
+tx_res	hwif/usb/usb.h	/^ int tx_res;$/;"	m	struct:ssv6xxx_tx_endpoint	access:public
+tx_s0	smac/sec_ccmp.c	/^     tx_e[AES_BLOCK_LEN], tx_s0[AES_BLOCK_LEN];$/;"	m	struct:lib80211_ccmp_data	file:	access:public
+tx_s0	smac/sec_ccmp.c	/^ u8 *tx_b0, *tx_b, *tx_e, *tx_s0;$/;"	m	struct:lib80211_ccmp_data	file:	access:public
+tx_send_cc_data_point	smartlink/qqlink-lib-mipsel/include/TXOldInf.h	/^SDK_API int tx_send_cc_data_point(unsigned long long to_client, unsigned int id, char * value, unsigned int * cookie, on_send_cc_data_point_ret ret_callback);$/;"	p	signature:(unsigned long long to_client, unsigned int id, char * value, unsigned int * cookie, on_send_cc_data_point_ret ret_callback)
+tx_send_cc_data_points	smartlink/qqlink-lib-mipsel/include/TXOldInf.h	/^SDK_API int tx_send_cc_data_points(unsigned long long to_client, tx_data_point * data_points, int data_points_count, unsigned int * cookie, on_send_cc_data_point_ret ret_callback);$/;"	p	signature:(unsigned long long to_client, tx_data_point * data_points, int data_points_count, unsigned int * cookie, on_send_cc_data_point_ret ret_callback)
+tx_send_file_to	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^SDK_API int tx_send_file_to(unsigned long long target_id, char * file_path, unsigned long long * transfer_cookie, char * buff_with_file, int buff_length, char * bussiness_name);$/;"	p	signature:(unsigned long long target_id, char * file_path, unsigned long long * transfer_cookie, char * buff_with_file, int buff_length, char * bussiness_name)
+tx_send_msg_notify	smartlink/qqlink-lib-mipsel/include/TXMsg.h	/^} tx_send_msg_notify;$/;"	t	typeref:struct:_tx_send_msg_notify
+tx_send_notify_msg	smartlink/qqlink-lib-mipsel/include/TXMsg.h	/^SDK_API void tx_send_notify_msg(int msg_id, char* digest, on_send_notify_msg_ret ret_callback, unsigned int *cookie, unsigned long long* to_targetids, unsigned int to_targetids_count);$/;"	p	signature:(int msg_id, char* digest, on_send_notify_msg_ret ret_callback, unsigned int *cookie, unsigned long long* to_targetids, unsigned int to_targetids_count)
+tx_send_structuring_msg	smartlink/qqlink-lib-mipsel/include/TXMsg.h	/^SDK_API void tx_send_structuring_msg(const structuring_msg *msg, tx_send_msg_notify *notify, unsigned int *cookie);$/;"	p	signature:(const structuring_msg *msg, tx_send_msg_notify *notify, unsigned int *cookie)
+tx_send_text_msg	smartlink/qqlink-lib-mipsel/include/TXMsg.h	/^SDK_API void tx_send_text_msg(int msg_id, char *text, on_send_text_msg_ret ret_callback, unsigned int *cookie, unsigned long long* to_targetids, unsigned int to_targetids_count);$/;"	p	signature:(int msg_id, char *text, on_send_text_msg_ret ret_callback, unsigned int *cookie, unsigned long long* to_targetids, unsigned int to_targetids_count)
+tx_send_video_request	smartlink/qqlink-lib-mipsel/include/TXTVSDK.h	/^SDK_API void tx_send_video_request(int type, unsigned long long toDin, const char * pBuff, unsigned int uLen, on_receive_video_reply callback);$/;"	p	signature:(int type, unsigned long long toDin, const char * pBuff, unsigned int uLen, on_receive_video_reply callback)
+tx_set_audio_data	smartlink/qqlink-lib-mipsel/include/TXAudioVideo.h	/^SDK_API void tx_set_audio_data(tx_audio_encode_param *param, unsigned char *pcEncData, int nEncDataLen);$/;"	p	signature:(tx_audio_encode_param *param, unsigned char *pcEncData, int nEncDataLen)
+tx_set_barrage_notify	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^SDK_API void tx_set_barrage_notify(tx_barrage_notify * notify);$/;"	p	signature:(tx_barrage_notify * notify)
+tx_set_log_func	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^SDK_API void tx_set_log_func(tx_log_func log_func);$/;"	p	signature:(tx_log_func log_func)
+tx_set_tv_notify	smartlink/qqlink-lib-mipsel/include/TXTVSDK.h	/^SDK_API void tx_set_tv_notify(tx_tv_notify * notify);$/;"	p	signature:(tx_tv_notify * notify)
+tx_set_video_data	smartlink/qqlink-lib-mipsel/include/TXAudioVideo.h	/^SDK_API void tx_set_video_data(unsigned char *pcEncData, int nEncDataLen,$/;"	p	signature:(unsigned char *pcEncData, int nEncDataLen, int nFrameType, int nTimeStamps, int nGopIndex, int nFrameIndex, int nTotalIndex, int nAvgQP)
+tx_skb_q	smac/dev.h	/^    struct sk_buff_head tx_skb_q;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::sk_buff_head	access:public
+tx_start_av_service	smartlink/qqlink-lib-mipsel/include/TXAudioVideo.h	/^SDK_API int tx_start_av_service( tx_av_callback *callback);$/;"	p	signature:( tx_av_callback *callback)
+tx_stop_av_service	smartlink/qqlink-lib-mipsel/include/TXAudioVideo.h	/^SDK_API int tx_stop_av_service();$/;"	p	signature:()
+tx_stuck_detect	include/ssv_cfg.h	/^    bool tx_stuck_detect;$/;"	m	struct:ssv6xxx_cfg	access:public
+tx_task	smac/dev.h	/^    struct task_struct *tx_task;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::task_struct	access:public
+tx_test_mode_enum	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^enum tx_test_mode_enum$/;"	g
+tx_text_msg_element	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^}tx_text_msg_element;$/;"	t	typeref:struct:tag_tx_text_msg_element
+tx_tfm	smac/sec_wep.c	/^    struct crypto_blkcipher *tx_tfm;$/;"	m	struct:lib80211_wep_data	typeref:struct:lib80211_wep_data::crypto_blkcipher	file:	access:public
+tx_tfm_arc4	smac/sec_tkip.c	/^ struct crypto_blkcipher *tx_tfm_arc4;$/;"	m	struct:lib80211_tkip_data	typeref:struct:lib80211_tkip_data::crypto_blkcipher	file:	access:public
+tx_tfm_arc4	smac/sec_tkip.c	/^ struct crypto_skcipher *tx_tfm_arc4;$/;"	m	struct:lib80211_tkip_data	typeref:struct:lib80211_tkip_data::crypto_skcipher	file:	access:public
+tx_tfm_michael	smac/sec_tkip.c	/^ struct crypto_ahash *tx_tfm_michael;$/;"	m	struct:lib80211_tkip_data	typeref:struct:lib80211_tkip_data::crypto_ahash	file:	access:public
+tx_tfm_michael	smac/sec_tkip.c	/^ struct crypto_hash *tx_tfm_michael;$/;"	m	struct:lib80211_tkip_data	typeref:struct:lib80211_tkip_data::crypto_hash	file:	access:public
+tx_ttak	smac/sec_tkip.c	/^ u16 tx_ttak[5];$/;"	m	struct:lib80211_tkip_data	file:	access:public
+tx_tv_notify	smartlink/qqlink-lib-mipsel/include/TXTVSDK.h	/^}tx_tv_notify;$/;"	t	typeref:struct:tag_tx_tv_notify
+tx_uninit_decoder	smartlink/qqlink-lib-mipsel/include/TXVoiceLink.h	/^SDK_API void tx_uninit_decoder();$/;"	p	signature:()
+tx_upload_file	smartlink/qqlink-lib-mipsel/include/TXFileTransfer.h	/^SDK_API int tx_upload_file(int channeltype, int filetype, char * file_path, unsigned long long * transfer_cookie);$/;"	p	signature:(int channeltype, int filetype, char * file_path, unsigned long long * transfer_cookie)
+tx_use_id	hci/hctrl.h	/^    u32 tx_use_id:6;$/;"	m	struct:ssv6xxx_hci_txq_info	access:public
+tx_use_id	hci/hctrl.h	/^    u32 tx_use_id:8;$/;"	m	struct:ssv6xxx_hci_txq_info2	access:public
+tx_use_page	hci/hctrl.h	/^ u32 tx_use_page:8;$/;"	m	struct:ssv6xxx_hci_txq_info	access:public
+tx_use_page	hci/hctrl.h	/^ u32 tx_use_page:9;$/;"	m	struct:ssv6xxx_hci_txq_info2	access:public
+tx_voicelink_param	smartlink/qqlink-lib-mipsel/include/TXVoiceLink.h	/^} tx_voicelink_param;$/;"	t	typeref:struct:__anon38
+tx_wait_q	hci/hctrl.h	/^ wait_queue_head_t tx_wait_q;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+tx_wait_q	smac/dev.h	/^    wait_queue_head_t tx_wait_q;$/;"	m	struct:ssv_softc	access:public
+tx_wait_q_woken	smac/dev.h	/^    u16 tx_wait_q_woken;$/;"	m	struct:ssv_softc	access:public
+tx_wifi_sync_param	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	/^} tx_wifi_sync_param;$/;"	t	typeref:struct:__anon39
+txdc_i_2g	smac/dev.h	/^    u8 txdc_i_2g;$/;"	m	struct:ssv6006_cal_result	access:public
+txdc_i_2g	smac/hal/ssv6006c/turismo_common.h	/^    u8 txdc_i_2g;$/;"	m	struct:ssv6006_cal_result	access:public
+txdc_i_5g	smac/dev.h	/^    u8 txdc_i_5g;$/;"	m	struct:ssv6006_cal_result	access:public
+txdc_i_5g	smac/hal/ssv6006c/turismo_common.h	/^    u8 txdc_i_5g;$/;"	m	struct:ssv6006_cal_result	access:public
+txdc_q_2g	smac/dev.h	/^    u8 txdc_q_2g;$/;"	m	struct:ssv6006_cal_result	access:public
+txdc_q_2g	smac/hal/ssv6006c/turismo_common.h	/^    u8 txdc_q_2g;$/;"	m	struct:ssv6006_cal_result	access:public
+txdc_q_5g	smac/dev.h	/^    u8 txdc_q_5g;$/;"	m	struct:ssv6006_cal_result	access:public
+txdc_q_5g	smac/hal/ssv6006c/turismo_common.h	/^    u8 txdc_q_5g;$/;"	m	struct:ssv6006_cal_result	access:public
+txiq_alpha	smac/dev.h	/^    u8 txiq_alpha[PADPDBAND];$/;"	m	struct:ssv6006_cal_result	access:public
+txiq_alpha	smac/hal/ssv6006c/turismo_common.h	/^    u8 txiq_alpha[PADPDBAND];$/;"	m	struct:ssv6006_cal_result	access:public
+txiq_theta	smac/dev.h	/^    u8 txiq_theta[PADPDBAND];$/;"	m	struct:ssv6006_cal_result	access:public
+txiq_theta	smac/hal/ssv6006c/turismo_common.h	/^    u8 txiq_theta[PADPDBAND];$/;"	m	struct:ssv6006_cal_result	access:public
+txq0_size	hci/hctrl.h	/^    u32 txq0_size:4;$/;"	m	struct:ssv6xxx_hci_txq_info	access:public
+txq1_size	hci/hctrl.h	/^ u32 txq1_size:4;$/;"	m	struct:ssv6xxx_hci_txq_info	access:public
+txq2_size	hci/hctrl.h	/^ u32 txq2_size:5;$/;"	m	struct:ssv6xxx_hci_txq_info	access:public
+txq3_size	hci/hctrl.h	/^ u32 txq3_size:5;$/;"	m	struct:ssv6xxx_hci_txq_info	access:public
+txq4_size	hci/hctrl.h	/^ u32 txq4_size:4;$/;"	m	struct:ssv6xxx_hci_txq_info2	access:public
+txq_idx	include/ssv6200_common.h	/^    u32 txq_idx:3;$/;"	m	struct:ssv6200_tx_desc	access:public
+txq_idx	smac/hal/ssv6006c/turismo_common.h	/^    u32 txq_idx:3;$/;"	m	struct:ssv6006_tx_desc	access:public
+txq_lock	smac/dev.h	/^    spinlock_t txq_lock;$/;"	m	struct:ssv6xxx_bcast_txq	access:public
+txq_mask	hci/hctrl.h	/^    u32 txq_mask;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+txq_mask_lock	hci/hctrl.h	/^    struct mutex txq_mask_lock;$/;"	m	struct:ssv6xxx_hci_ctrl	typeref:struct:ssv6xxx_hci_ctrl::mutex	access:public
+txq_no	hci/ssv_hci.h	/^    u32 txq_no;$/;"	m	struct:ssv_hw_txq	access:public
+txrate_dlr	smac/ssv_rc.c	/^    unsigned int txrate_dlr=0;$/;"	v
+txrate_idx	smac/ssv_rc_common.h	/^    int txrate_idx;$/;"	m	struct:rc_pid_sta_info	access:public
+txrxboost_change	include/ssv6200.h	/^static inline void txrxboost_change(u32 tx_frame_qlen, u32 low_threshold, u32 high_threshold, u32 prio) {$/;"	f	signature:(u32 tx_frame_qlen, u32 low_threshold, u32 high_threshold, u32 prio)
+txrxboost_high_threshold	include/ssv_cfg.h	/^    u32 txrxboost_high_threshold;$/;"	m	struct:ssv6xxx_cfg	access:public
+txrxboost_init	include/ssv6200.h	/^static inline void txrxboost_init(void) {$/;"	f	signature:(void)
+txrxboost_low_threshold	include/ssv_cfg.h	/^    u32 txrxboost_low_threshold;$/;"	m	struct:ssv6xxx_cfg	access:public
+txrxboost_prio	include/ssv_cfg.h	/^    u32 txrxboost_prio;$/;"	m	struct:ssv6xxx_cfg	access:public
+txtput_generate_m2	ssvdevice/ssv_cmd.c	/^int txtput_generate_m2(struct ssv_softc *sc, u32 size_per_frame, u32 loop_times)$/;"	f	signature:(struct ssv_softc *sc, u32 size_per_frame, u32 loop_times)
+txtput_set_desc	smac/dev.h	/^    void (*txtput_set_desc)(struct ssv_hw *sh, struct sk_buff *skb );$/;"	m	struct:ssv_hal_ops	access:public
+txtput_thread_m2	ssvdevice/ssv_cmd.c	/^static int txtput_thread_m2(void *data)$/;"	f	file:	signature:(void *data)
+txtput_tsk	smac/dev.h	/^    struct task_struct *txtput_tsk;$/;"	m	struct:_ssv6xxx_txtput	typeref:struct:_ssv6xxx_txtput::task_struct	access:public
+txtput_tsk_cleanup	ssvdevice/ssv_cmd.c	/^static int txtput_tsk_cleanup(struct ssv_softc *sc)$/;"	f	file:	signature:(struct ssv_softc *sc)
+type	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    int type;$/;"	m	struct:tag_tx_binder_info	access:public
+udev	hwif/usb/usb.c	/^ struct usb_device *udev;$/;"	m	struct:ssv6xxx_usb_glue	typeref:struct:ssv6xxx_usb_glue::usb_device	file:	access:public
+uin	smartlink/qqlink-lib-mipsel/include/TXDeviceSDK.h	/^    unsigned long long uin;$/;"	m	struct:tag_tx_binder_info	access:public
+umac	smac/dev.h	/^    struct ssv6xxx_umac_ops *umac;$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::ssv6xxx_umac_ops	access:public
+umac_rx_raw	smac/dev.h	/^    int (*umac_rx_raw)(struct sk_buff *);$/;"	m	struct:ssv6xxx_umac_ops	access:public
+unicast	include/ssv6200_common.h	/^    u32 unicast:1;$/;"	m	struct:ssv6200_rx_desc	access:public
+unicast	include/ssv6200_common.h	/^    u32 unicast:1;$/;"	m	struct:ssv6200_tx_desc	access:public
+unicast	smac/hal/ssv6006c/turismo_common.h	/^    u32 unicast:1;$/;"	m	struct:ssv6006_rx_desc	access:public
+unicast	smac/hal/ssv6006c/turismo_common.h	/^    u32 unicast:1;$/;"	m	struct:ssv6006_tx_desc	access:public
+up_pr	include/ssv_cfg.h	/^    u16 up_pr;$/;"	m	struct:rc_setting	access:public
+up_pr3	include/ssv_cfg.h	/^    u16 up_pr3;$/;"	m	struct:rc_setting	access:public
+up_pr4	include/ssv_cfg.h	/^    u16 up_pr4;$/;"	m	struct:rc_setting	access:public
+up_pr5	include/ssv_cfg.h	/^    u16 up_pr5;$/;"	m	struct:rc_setting	access:public
+up_pr6	include/ssv_cfg.h	/^    u16 up_pr6;$/;"	m	struct:rc_setting	access:public
+update_aggr_check	smac/ssv_rc_minstrel.h	/^    bool update_aggr_check;$/;"	m	struct:ssv_minstrel_sta_priv	access:public
+update_ampdu_txinfo	smac/dev.h	/^    void (*update_ampdu_txinfo)(struct ssv_softc *sc, struct sk_buff *ampdu_skb);$/;"	m	struct:ssv_hal_ops	access:public
+update_cfg_hw_patch	smac/dev.h	/^    void (*update_cfg_hw_patch)(struct ssv_hw *sh, ssv_cabrio_reg *rf_table,$/;"	m	struct:ssv_hal_ops	access:public
+update_decision_table	smac/dev.h	/^    int (*update_decision_table)(struct ssv_softc *sc);$/;"	m	struct:ssv_hal_ops	access:public
+update_decision_table_6	smac/dev.h	/^    void (*update_decision_table_6)(struct ssv_hw *sh, u32 val);$/;"	m	struct:ssv_hal_ops	access:public
+update_efuse_setting	smac/dev.h	/^    int (*update_efuse_setting)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+update_hw_config	smac/dev.h	/^    void (*update_hw_config)(struct ssv_hw *sh, ssv_cabrio_reg *rf_table,$/;"	m	struct:ssv_hal_ops	access:public
+update_interval	smac/ssv_rc_minstrel.h	/^ unsigned int update_interval;$/;"	m	struct:ssv_minstrel_priv	access:public
+update_null_func_txinfo	smac/dev.h	/^    int (*update_null_func_txinfo)(struct ssv_softc *sc, struct ieee80211_sta *sta, struct sk_buff *skb);$/;"	m	struct:ssv_hal_ops	access:public
+update_page_id	smac/dev.h	/^    void (*update_page_id)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+update_product_hw_setting	smac/dev.h	/^    void (*update_product_hw_setting)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+update_rf_pwr	smac/dev.h	/^    void (*update_rf_pwr)(struct ssv_softc *sc);$/;"	m	struct:ssv_hal_ops	access:public
+update_rxstatus	smac/dev.h	/^    void (*update_rxstatus)(struct ssv_softc *sc,$/;"	m	struct:ssv_hal_ops	access:public
+update_scan_cci_setting	smac/dev.h	/^    void (*update_scan_cci_setting)(struct ssv_softc *sc);$/;"	m	struct:ssv_hal_ops	access:public
+update_txinfo	smac/dev.h	/^    void (*update_txinfo)(struct ssv_softc *sc, struct sk_buff *skb);$/;"	m	struct:ssv_hal_ops	access:public
+update_txq_mask	smac/dev.h	/^    void (*update_txq_mask)(struct ssv_hw *sh, u32 txq_mask);$/;"	m	struct:ssv_hal_ops	access:public
+upper_level	smac/dev.h	/^    u32 upper_level;$/;"	m	struct:ssv6xxx_b_cca_control	access:public
+upper_level	smac/dev.h	/^    u32 upper_level;$/;"	m	struct:ssv6xxx_cca_control	access:public
+usage	ssvdevice/ssv_cmd.h	/^    const char *usage;$/;"	m	struct:ssv_cmd_table	access:public
+usb_hw_resource	include/ssv_cfg.h	/^    u32 usb_hw_resource;$/;"	m	struct:ssv6xxx_cfg	access:public
+usb_ops	hwif/usb/usb.c	/^static struct ssv6xxx_hwif_ops usb_ops =$/;"	v	typeref:struct:ssv6xxx_hwif_ops	file:
+usb_param	hwif/hwif.h	/^    void *usb_param;$/;"	m	struct:ssv6xxx_platform_data	access:public
+use_4addr	include/ssv6200_common.h	/^    u32 use_4addr:1;$/;"	m	struct:ssv6200_rx_desc	access:public
+use_4addr	include/ssv6200_common.h	/^    u32 use_4addr:1;$/;"	m	struct:ssv6200_tx_desc	access:public
+use_4addr	smac/hal/ssv6006c/turismo_common.h	/^    u32 use_4addr:1;$/;"	m	struct:ssv6006_rx_desc	access:public
+use_4addr	smac/hal/ssv6006c/turismo_common.h	/^    u32 use_4addr:1;$/;"	m	struct:ssv6006_tx_desc	access:public
+use_hw_encrypt	smac/dev.h	/^    bool (*use_hw_encrypt)(int cipher, struct ssv_softc *sc,$/;"	m	struct:ssv_hal_ops	access:public
+use_mac80211_decrypt	smac/dev.h	/^    bool use_mac80211_decrypt;$/;"	m	struct:ssv_sta_priv_data	access:public
+use_mac80211_decrypt	smac/dev.h	/^    bool use_mac80211_decrypt;$/;"	m	struct:ssv_vif_priv_data	access:public
+use_sw_cipher	include/ssv_cfg.h	/^    u32 use_sw_cipher;$/;"	m	struct:ssv6xxx_cfg	access:public
+use_wpa2_only	include/ssv_cfg.h	/^    u32 use_wpa2_only;$/;"	m	struct:ssv6xxx_cfg	access:public
+used	smac/ssv_rc_minstrel_ht.h	/^ bool used;$/;"	m	struct:ssv_minstrel_ampdu_rate_rpt	access:public
+val	include/ssv6xxx_common.h	/^    u32 val;$/;"	m	struct:ssv6xxx_tx_loopback	access:public
+val	smac/dev.h	/^    struct ssv6006dpd val[PADPDBAND];$/;"	m	struct:ssv6006_padpd	typeref:struct:ssv6006_padpd::ssv6006dpd	access:public
+val	smac/hal/ssv6006c/turismo_common.h	/^    struct ssv6006dpd val[PADPDBAND];$/;"	m	struct:ssv6006_padpd	typeref:struct:ssv6006_padpd::ssv6006dpd	access:public
+val	ssvdevice/ssv_cmd.c	/^    u32 val;$/;"	m	struct:ssv6xxx_dev_table	file:	access:public
+valid	smac/drv_comm.h	/^    u8 valid;$/;"	m	struct:ssv6xxx_hw_sta_key	access:public
+valid	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 valid;$/;"	m	struct:ssv6006_hw_sta_key	access:public
+value	hwif/usb/usb.h	/^ u32 value;$/;"	m	struct:ssv6xxx_read_reg	access:public
+value	hwif/usb/usb.h	/^ u32 value;$/;"	m	struct:ssv6xxx_read_reg_result	access:public
+value	hwif/usb/usb.h	/^ u32 value;$/;"	m	struct:ssv6xxx_write_reg	access:public
+value	smac/dev.h	/^    u32 value;$/;"	m	struct:ssv_hw_cfg	access:public
+value	smac/efuse.h	/^    u16 value;$/;"	m	struct:efuse_map	access:public
+value	smartlink/qqlink-lib-mipsel/include/TXDataPoint.h	/^    char * value;$/;"	m	struct:tag_tx_data_point	access:public
+value	umac/ssv6xxx_netlink_core.h	/^ u32 value;$/;"	m	struct:ssv_wireless_register	access:public
+var	ssvdevice/ssv_cmd.h	/^    void *var;$/;"	m	struct:ssv6xxx_cfg_cmd_table	access:public
+vendor	hwif/hwif.h	/^    unsigned short vendor;$/;"	m	struct:ssv6xxx_platform_data	access:public
+version	smac/hal/ssv6006c/ssv6006_mac.h	/^    u32 version:24;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+version	smartlink/ssv_smartlink.c	/^static char version[64]="SSV SmartLink Verison: " SSV_SMARTLINK_VERSION;$/;"	v	file:
+version_great	ap_launch.sh	/^function version_great() { test "$(printf '%s\\n' "$@" | sort -V | head -n 1)" != "$1"; }$/;"	f
+version_great	launch_ap_sta.sh	/^function version_great() { test "$(printf '%s\\n' "$@" | sort -V | head -n 1)" != "$1"; }$/;"	f
+version_great	launch_sta_ap.sh	/^function version_great() { test "$(printf '%s\\n' "$@" | sort -V | head -n 1)" != "$1"; }$/;"	f
+vi_txq_size	include/ssv6xxx_common.h	/^ u32 vi_txq_size;$/;"	m	struct:ssv6xxx_tx_hw_info	access:public
+vi_txq_size	include/ssv_cfg.h	/^    u32 vi_txq_size;$/;"	m	struct:ssv6xxx_cfg	access:public
+vif	include/ssv6xxx_common.h	/^    u8 vif;$/;"	m	struct:ssv62xx_noa_evt	access:public
+vif	smac/dev.h	/^    struct ieee80211_vif *vif;$/;"	m	struct:ssv_sta_info	typeref:struct:ssv_sta_info::ieee80211_vif	access:public
+vif	smac/dev.h	/^    struct ieee80211_vif *vif;$/;"	m	struct:ssv_vif_info	typeref:struct:ssv_vif_info::ieee80211_vif	access:public
+vif_idx	smac/dev.h	/^    int vif_idx;$/;"	m	struct:ssv_vif_priv_data	access:public
+vif_info	smac/dev.h	/^    struct ssv_vif_info vif_info[SSV_NUM_VIF];$/;"	m	struct:ssv_softc	typeref:struct:ssv_softc::ssv_vif_info	access:public
+vif_priv	smac/dev.h	/^    struct ssv_vif_priv_data *vif_priv;$/;"	m	struct:ssv_vif_info	typeref:struct:ssv_vif_info::ssv_vif_priv_data	access:public
+vo_txq_size	include/ssv6xxx_common.h	/^ u32 vo_txq_size;$/;"	m	struct:ssv6xxx_tx_hw_info	access:public
+vo_txq_size	include/ssv_cfg.h	/^    u32 vo_txq_size;$/;"	m	struct:ssv6xxx_cfg	access:public
+voice_switch	smartlink/qqlink-lib-mipsel/include/TXTVBarrage.h	/^    unsigned int voice_switch;$/;"	m	struct:tag_tx_audio_msg_element	access:public
+volt_regulator	include/ssv_cfg.h	/^    u32 volt_regulator;$/;"	m	struct:ssv6xxx_cfg	access:public
+vt_tbl	smac/dev.c	/^static const struct ssv6xxx_calib_table vt_tbl[SSV6XXX_IQK_CFG_XTAL_MAX][14]=$/;"	v	typeref:struct:ssv6xxx_calib_table	file:
+vt_tbl	smac/dev.c	/^static const struct ssv6xxx_calib_table vt_tbl[] =$/;"	v	typeref:struct:ssv6xxx_calib_table	file:
+wait_usb_rom_ready	smac/dev.h	/^    void (*wait_usb_rom_ready)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+wapi_enable	smac/sec_wpi.c	/^ TRUTH_VALUE_T wapi_enable;$/;"	m	struct:lib80211_wpi_data	file:	access:public
+wapi_key_ok	smac/sec_wpi.c	/^ TRUTH_VALUE_T wapi_key_ok;$/;"	m	struct:lib80211_wpi_data	file:	access:public
+wapi_version	smac/sec_wpi.c	/^ u8 wapi_version[2];$/;"	m	struct:lib80211_wpi_data	file:	access:public
+wep_cipher	smac/dev.h	/^    int wep_cipher;$/;"	m	struct:ssv_vif_priv_data	access:public
+wep_hw_key	smac/dev.h	/^struct wep_hw_key {$/;"	s
+wep_hw_key::key	smac/dev.h	/^    u8 key[SECURITY_KEY_LEN];$/;"	m	struct:wep_hw_key	access:public
+wep_hw_key::keylen	smac/dev.h	/^    u8 keylen;$/;"	m	struct:wep_hw_key	access:public
+wep_idx	smac/dev.h	/^    s8 wep_idx;$/;"	m	struct:ssv_vif_priv_data	access:public
+wep_use_hw_cipher	smac/dev.h	/^    bool (*wep_use_hw_cipher)(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv);$/;"	m	struct:ssv_hal_ops	access:public
+wifi_control_data	platforms/a33-generic-wlan.c	/^static struct wifi_platform_data *wifi_control_data = NULL;$/;"	v	typeref:struct:wifi_platform_data	file:
+wifi_control_data	platforms/atm7039-action-generic-wlan.c	/^static struct wifi_platform_data *wifi_control_data = NULL;$/;"	v	typeref:struct:wifi_platform_data	file:
+wifi_control_data	platforms/h3-generic-wlan.c	/^static struct wifi_platform_data *wifi_control_data = NULL;$/;"	v	typeref:struct:wifi_platform_data	file:
+wifi_control_data	platforms/h8-generic-wlan.c	/^static struct wifi_platform_data *wifi_control_data = NULL;$/;"	v	typeref:struct:wifi_platform_data	file:
+wifi_control_data	platforms/rk3126-generic-wlan.c	/^static struct wifi_platform_data *wifi_control_data = NULL;$/;"	v	typeref:struct:wifi_platform_data	file:
+wifi_control_data	platforms/t10-generic-wlan.c	/^static struct wifi_platform_data *wifi_control_data = NULL;$/;"	v	typeref:struct:wifi_platform_data	file:
+wifi_control_data	platforms/x1000-generic-wlan.c	/^static struct wifi_platform_data *wifi_control_data = NULL;$/;"	v	typeref:struct:wifi_platform_data	file:
+wifi_control_sem	platforms/a33-generic-wlan.c	/^static struct semaphore wifi_control_sem;$/;"	v	typeref:struct:semaphore	file:
+wifi_control_sem	platforms/atm7039-action-generic-wlan.c	/^static struct semaphore wifi_control_sem;$/;"	v	typeref:struct:semaphore	file:
+wifi_control_sem	platforms/h3-generic-wlan.c	/^static struct semaphore wifi_control_sem;$/;"	v	typeref:struct:semaphore	file:
+wifi_control_sem	platforms/h8-generic-wlan.c	/^static struct semaphore wifi_control_sem;$/;"	v	typeref:struct:semaphore	file:
+wifi_control_sem	platforms/rk3126-generic-wlan.c	/^static struct semaphore wifi_control_sem;$/;"	v	typeref:struct:semaphore	file:
+wifi_control_sem	platforms/t10-generic-wlan.c	/^static struct semaphore wifi_control_sem;$/;"	v	typeref:struct:semaphore	file:
+wifi_control_sem	platforms/x1000-generic-wlan.c	/^static struct semaphore wifi_control_sem;$/;"	v	typeref:struct:semaphore	file:
+wifi_driver	platforms/a33-generic-wlan.c	/^static struct platform_driver wifi_driver = {$/;"	v	typeref:struct:platform_driver	file:
+wifi_driver	platforms/atm7039-action-generic-wlan.c	/^static struct platform_driver wifi_driver = { .probe = wifi_probe,$/;"	v	typeref:struct:platform_driver	file:
+wifi_driver	platforms/h3-generic-wlan.c	/^static struct platform_driver wifi_driver = {$/;"	v	typeref:struct:platform_driver	file:
+wifi_driver	platforms/h8-generic-wlan.c	/^static struct platform_driver wifi_driver = {$/;"	v	typeref:struct:platform_driver	file:
+wifi_driver	platforms/rk3126-generic-wlan.c	/^static struct platform_driver wifi_driver = {$/;"	v	typeref:struct:platform_driver	file:
+wifi_driver	platforms/t10-generic-wlan.c	/^static struct platform_driver wifi_driver = {$/;"	v	typeref:struct:platform_driver	file:
+wifi_driver	platforms/x1000-generic-wlan.c	/^static struct platform_driver wifi_driver = {$/;"	v	typeref:struct:platform_driver	file:
+wifi_irqres	platforms/atm7039-action-generic-wlan.c	/^static struct resource *wifi_irqres = NULL;$/;"	v	typeref:struct:resource	file:
+wifi_irqres	platforms/h3-generic-wlan.c	/^static struct resource *wifi_irqres = NULL;$/;"	v	typeref:struct:resource	file:
+wifi_irqres	platforms/h8-generic-wlan.c	/^static struct resource *wifi_irqres = NULL;$/;"	v	typeref:struct:resource	file:
+wifi_irqres	platforms/t10-generic-wlan.c	/^static struct resource *wifi_irqres = NULL;$/;"	v	typeref:struct:resource	file:
+wifi_irqres	platforms/x1000-generic-wlan.c	/^static struct resource *wifi_irqres = NULL;$/;"	v	typeref:struct:resource	file:
+wifi_platform_data	platforms/a33-generic-wlan.c	/^struct wifi_platform_data {$/;"	s	file:
+wifi_platform_data	platforms/atm7039-action-generic-wlan.c	/^struct wifi_platform_data$/;"	s	file:
+wifi_platform_data	platforms/h3-generic-wlan.c	/^struct wifi_platform_data {$/;"	s	file:
+wifi_platform_data	platforms/h8-generic-wlan.c	/^struct wifi_platform_data {$/;"	s	file:
+wifi_platform_data	platforms/rk3126-generic-wlan.c	/^struct wifi_platform_data {$/;"	s	file:
+wifi_platform_data	platforms/t10-generic-wlan.c	/^struct wifi_platform_data {$/;"	s	file:
+wifi_platform_data	platforms/x1000-generic-wlan.c	/^struct wifi_platform_data {$/;"	s	file:
+wifi_platform_data::get_country_code	platforms/a33-generic-wlan.c	/^    void *(*get_country_code)(char *ccode);$/;"	m	struct:wifi_platform_data	file:	access:public
+wifi_platform_data::get_country_code	platforms/atm7039-action-generic-wlan.c	/^ void *(*get_country_code)(char *ccode);$/;"	m	struct:wifi_platform_data	file:	access:public
+wifi_platform_data::get_country_code	platforms/h3-generic-wlan.c	/^ void *(*get_country_code)(char *ccode);$/;"	m	struct:wifi_platform_data	file:	access:public
+wifi_platform_data::get_country_code	platforms/h8-generic-wlan.c	/^ void *(*get_country_code)(char *ccode);$/;"	m	struct:wifi_platform_data	file:	access:public
+wifi_platform_data::get_country_code	platforms/rk3126-generic-wlan.c	/^    void *(*get_country_code)(char *ccode);$/;"	m	struct:wifi_platform_data	file:	access:public
+wifi_platform_data::get_country_code	platforms/t10-generic-wlan.c	/^ void *(*get_country_code)(char *ccode);$/;"	m	struct:wifi_platform_data	file:	access:public
+wifi_platform_data::get_country_code	platforms/x1000-generic-wlan.c	/^ void *(*get_country_code)(char *ccode);$/;"	m	struct:wifi_platform_data	file:	access:public
+wifi_platform_data::get_mac_addr	platforms/a33-generic-wlan.c	/^    int (*get_mac_addr)(unsigned char *buf);$/;"	m	struct:wifi_platform_data	file:	access:public
+wifi_platform_data::get_mac_addr	platforms/atm7039-action-generic-wlan.c	/^ int (*get_mac_addr)(unsigned char *buf);$/;"	m	struct:wifi_platform_data	file:	access:public
+wifi_platform_data::get_mac_addr	platforms/h3-generic-wlan.c	/^ int (*get_mac_addr)(unsigned char *buf);$/;"	m	struct:wifi_platform_data	file:	access:public
+wifi_platform_data::get_mac_addr	platforms/h8-generic-wlan.c	/^ int (*get_mac_addr)(unsigned char *buf);$/;"	m	struct:wifi_platform_data	file:	access:public
+wifi_platform_data::get_mac_addr	platforms/rk3126-generic-wlan.c	/^    int (*get_mac_addr)(unsigned char *buf);$/;"	m	struct:wifi_platform_data	file:	access:public
+wifi_platform_data::get_mac_addr	platforms/t10-generic-wlan.c	/^ int (*get_mac_addr)(unsigned char *buf);$/;"	m	struct:wifi_platform_data	file:	access:public
+wifi_platform_data::get_mac_addr	platforms/x1000-generic-wlan.c	/^ int (*get_mac_addr)(unsigned char *buf);$/;"	m	struct:wifi_platform_data	file:	access:public
+wifi_platform_data::mem_prealloc	platforms/a33-generic-wlan.c	/^    void *(*mem_prealloc)(int section, unsigned long size);$/;"	m	struct:wifi_platform_data	file:	access:public
+wifi_platform_data::mem_prealloc	platforms/atm7039-action-generic-wlan.c	/^ void *(*mem_prealloc)(int section, unsigned long size);$/;"	m	struct:wifi_platform_data	file:	access:public
+wifi_platform_data::mem_prealloc	platforms/h3-generic-wlan.c	/^ void *(*mem_prealloc)(int section, unsigned long size);$/;"	m	struct:wifi_platform_data	file:	access:public
+wifi_platform_data::mem_prealloc	platforms/h8-generic-wlan.c	/^ void *(*mem_prealloc)(int section, unsigned long size);$/;"	m	struct:wifi_platform_data	file:	access:public
+wifi_platform_data::mem_prealloc	platforms/rk3126-generic-wlan.c	/^    void *(*mem_prealloc)(int section, unsigned long size);$/;"	m	struct:wifi_platform_data	file:	access:public
+wifi_platform_data::mem_prealloc	platforms/t10-generic-wlan.c	/^ void *(*mem_prealloc)(int section, unsigned long size);$/;"	m	struct:wifi_platform_data	file:	access:public
+wifi_platform_data::mem_prealloc	platforms/x1000-generic-wlan.c	/^ void *(*mem_prealloc)(int section, unsigned long size);$/;"	m	struct:wifi_platform_data	file:	access:public
+wifi_platform_data::set_carddetect	platforms/a33-generic-wlan.c	/^    int (*set_carddetect)(int val);$/;"	m	struct:wifi_platform_data	file:	access:public
+wifi_platform_data::set_carddetect	platforms/atm7039-action-generic-wlan.c	/^ int (*set_carddetect)(int val);$/;"	m	struct:wifi_platform_data	file:	access:public
+wifi_platform_data::set_carddetect	platforms/h3-generic-wlan.c	/^ int (*set_carddetect)(int val);$/;"	m	struct:wifi_platform_data	file:	access:public
+wifi_platform_data::set_carddetect	platforms/h8-generic-wlan.c	/^ int (*set_carddetect)(int val);$/;"	m	struct:wifi_platform_data	file:	access:public
+wifi_platform_data::set_carddetect	platforms/rk3126-generic-wlan.c	/^    int (*set_carddetect)(int val);$/;"	m	struct:wifi_platform_data	file:	access:public
+wifi_platform_data::set_carddetect	platforms/t10-generic-wlan.c	/^ int (*set_carddetect)(int val);$/;"	m	struct:wifi_platform_data	file:	access:public
+wifi_platform_data::set_carddetect	platforms/x1000-generic-wlan.c	/^ int (*set_carddetect)(int val);$/;"	m	struct:wifi_platform_data	file:	access:public
+wifi_platform_data::set_power	platforms/a33-generic-wlan.c	/^    int (*set_power)(int val);$/;"	m	struct:wifi_platform_data	file:	access:public
+wifi_platform_data::set_power	platforms/atm7039-action-generic-wlan.c	/^ int (*set_power)(int val);$/;"	m	struct:wifi_platform_data	file:	access:public
+wifi_platform_data::set_power	platforms/h3-generic-wlan.c	/^ int (*set_power)(int val);$/;"	m	struct:wifi_platform_data	file:	access:public
+wifi_platform_data::set_power	platforms/h8-generic-wlan.c	/^ int (*set_power)(int val);$/;"	m	struct:wifi_platform_data	file:	access:public
+wifi_platform_data::set_power	platforms/rk3126-generic-wlan.c	/^    int (*set_power)(int val);$/;"	m	struct:wifi_platform_data	file:	access:public
+wifi_platform_data::set_power	platforms/t10-generic-wlan.c	/^ int (*set_power)(int val);$/;"	m	struct:wifi_platform_data	file:	access:public
+wifi_platform_data::set_power	platforms/x1000-generic-wlan.c	/^ int (*set_power)(int val);$/;"	m	struct:wifi_platform_data	file:	access:public
+wifi_platform_data::set_reset	platforms/a33-generic-wlan.c	/^    int (*set_reset)(int val);$/;"	m	struct:wifi_platform_data	file:	access:public
+wifi_platform_data::set_reset	platforms/atm7039-action-generic-wlan.c	/^ int (*set_reset)(int val);$/;"	m	struct:wifi_platform_data	file:	access:public
+wifi_platform_data::set_reset	platforms/h3-generic-wlan.c	/^ int (*set_reset)(int val);$/;"	m	struct:wifi_platform_data	file:	access:public
+wifi_platform_data::set_reset	platforms/h8-generic-wlan.c	/^ int (*set_reset)(int val);$/;"	m	struct:wifi_platform_data	file:	access:public
+wifi_platform_data::set_reset	platforms/rk3126-generic-wlan.c	/^    int (*set_reset)(int val);$/;"	m	struct:wifi_platform_data	file:	access:public
+wifi_platform_data::set_reset	platforms/t10-generic-wlan.c	/^ int (*set_reset)(int val);$/;"	m	struct:wifi_platform_data	file:	access:public
+wifi_platform_data::set_reset	platforms/x1000-generic-wlan.c	/^ int (*set_reset)(int val);$/;"	m	struct:wifi_platform_data	file:	access:public
+wifi_pm_gpio_ctrl	platforms/a33-generic-wlan.c	/^extern int wifi_pm_gpio_ctrl(char *name, int level);$/;"	p	file:	signature:(char *name, int level)
+wifi_pm_gpio_ctrl	platforms/h3-generic-wlan.c	/^extern int wifi_pm_gpio_ctrl(char* name, int level);$/;"	p	file:	signature:(char* name, int level)
+wifi_pm_gpio_ctrl	platforms/h8-generic-wlan.c	/^extern int wifi_pm_gpio_ctrl(char* name, int level);$/;"	p	file:	signature:(char* name, int level)
+wifi_pm_gpio_ctrl	platforms/t10-generic-wlan.c	/^static int wifi_pm_gpio_ctrl(char* name, int level)$/;"	f	file:	signature:(char* name, int level)
+wifi_pm_gpio_ctrl	platforms/x1000-generic-wlan.c	/^static int wifi_pm_gpio_ctrl(char* name, int level)$/;"	f	file:	signature:(char* name, int level)
+wifi_pm_power	platforms/a33-generic-wlan.c	/^extern void wifi_pm_power(int on);$/;"	p	file:	signature:(int on)
+wifi_power	platforms/xm-hi3518-generic-wlan.c	/^extern void wifi_power(int on);$/;"	p	file:	signature:(int on)
+wifi_probe	platforms/a33-generic-wlan.c	/^static int wifi_probe(struct platform_device *pdev)$/;"	f	file:	signature:(struct platform_device *pdev)
+wifi_probe	platforms/atm7039-action-generic-wlan.c	/^static int wifi_probe(struct platform_device *pdev)$/;"	f	file:	signature:(struct platform_device *pdev)
+wifi_probe	platforms/h3-generic-wlan.c	/^static int wifi_probe(struct platform_device *pdev)$/;"	f	file:	signature:(struct platform_device *pdev)
+wifi_probe	platforms/h8-generic-wlan.c	/^static int wifi_probe(struct platform_device *pdev)$/;"	f	file:	signature:(struct platform_device *pdev)
+wifi_probe	platforms/rk3126-generic-wlan.c	/^static int wifi_probe(struct platform_device *pdev)$/;"	f	file:	signature:(struct platform_device *pdev)
+wifi_probe	platforms/t10-generic-wlan.c	/^static int wifi_probe(struct platform_device *pdev)$/;"	f	file:	signature:(struct platform_device *pdev)
+wifi_probe	platforms/x1000-generic-wlan.c	/^static int wifi_probe(struct platform_device *pdev)$/;"	f	file:	signature:(struct platform_device *pdev)
+wifi_remove	platforms/a33-generic-wlan.c	/^static int wifi_remove(struct platform_device *pdev)$/;"	f	file:	signature:(struct platform_device *pdev)
+wifi_remove	platforms/atm7039-action-generic-wlan.c	/^static int wifi_remove(struct platform_device *pdev)$/;"	f	file:	signature:(struct platform_device *pdev)
+wifi_remove	platforms/h3-generic-wlan.c	/^static int wifi_remove(struct platform_device *pdev)$/;"	f	file:	signature:(struct platform_device *pdev)
+wifi_remove	platforms/h8-generic-wlan.c	/^static int wifi_remove(struct platform_device *pdev)$/;"	f	file:	signature:(struct platform_device *pdev)
+wifi_remove	platforms/rk3126-generic-wlan.c	/^static int wifi_remove(struct platform_device *pdev)$/;"	f	file:	signature:(struct platform_device *pdev)
+wifi_remove	platforms/t10-generic-wlan.c	/^static int wifi_remove(struct platform_device *pdev)$/;"	f	file:	signature:(struct platform_device *pdev)
+wifi_remove	platforms/x1000-generic-wlan.c	/^static int wifi_remove(struct platform_device *pdev)$/;"	f	file:	signature:(struct platform_device *pdev)
+wifi_resume	platforms/a33-generic-wlan.c	/^static int wifi_resume(struct platform_device *pdev)$/;"	f	file:	signature:(struct platform_device *pdev)
+wifi_resume	platforms/atm7039-action-generic-wlan.c	/^static int wifi_resume(struct platform_device *pdev)$/;"	f	file:	signature:(struct platform_device *pdev)
+wifi_resume	platforms/h3-generic-wlan.c	/^static int wifi_resume(struct platform_device *pdev)$/;"	f	file:	signature:(struct platform_device *pdev)
+wifi_resume	platforms/h8-generic-wlan.c	/^static int wifi_resume(struct platform_device *pdev)$/;"	f	file:	signature:(struct platform_device *pdev)
+wifi_resume	platforms/rk3126-generic-wlan.c	/^static int wifi_resume(struct platform_device *pdev)$/;"	f	file:	signature:(struct platform_device *pdev)
+wifi_resume	platforms/t10-generic-wlan.c	/^static int wifi_resume(struct platform_device *pdev)$/;"	f	file:	signature:(struct platform_device *pdev)
+wifi_resume	platforms/x1000-generic-wlan.c	/^static int wifi_resume(struct platform_device *pdev)$/;"	f	file:	signature:(struct platform_device *pdev)
+wifi_set_carddetect	platforms/a33-generic-wlan.c	/^static int wifi_set_carddetect(int on)$/;"	f	file:	signature:(int on)
+wifi_set_carddetect	platforms/atm7039-action-generic-wlan.c	/^static int wifi_set_carddetect(int on)$/;"	f	file:	signature:(int on)
+wifi_set_carddetect	platforms/h3-generic-wlan.c	/^static int wifi_set_carddetect(int on)$/;"	f	file:	signature:(int on)
+wifi_set_carddetect	platforms/h8-generic-wlan.c	/^static int wifi_set_carddetect(int on)$/;"	f	file:	signature:(int on)
+wifi_set_carddetect	platforms/rk3126-generic-wlan.c	/^static int wifi_set_carddetect(int on)$/;"	f	file:	signature:(int on)
+wifi_set_carddetect	platforms/t10-generic-wlan.c	/^static int wifi_set_carddetect(int on)$/;"	f	file:	signature:(int on)
+wifi_set_carddetect	platforms/x1000-generic-wlan.c	/^static int wifi_set_carddetect(int on)$/;"	f	file:	signature:(int on)
+wifi_set_power	platforms/a33-generic-wlan.c	/^int wifi_set_power(int on, unsigned long msec)$/;"	f	signature:(int on, unsigned long msec)
+wifi_set_power	platforms/atm7039-action-generic-wlan.c	/^int wifi_set_power(int on, unsigned long msec)$/;"	f	signature:(int on, unsigned long msec)
+wifi_set_power	platforms/h3-generic-wlan.c	/^int wifi_set_power(int on, unsigned long msec)$/;"	f	signature:(int on, unsigned long msec)
+wifi_set_power	platforms/h8-generic-wlan.c	/^int wifi_set_power(int on, unsigned long msec)$/;"	f	signature:(int on, unsigned long msec)
+wifi_set_power	platforms/rk3126-generic-wlan.c	/^int wifi_set_power(int on, unsigned long msec)$/;"	f	signature:(int on, unsigned long msec)
+wifi_set_power	platforms/t10-generic-wlan.c	/^int wifi_set_power(int on, unsigned long msec)$/;"	f	signature:(int on, unsigned long msec)
+wifi_set_power	platforms/x1000-generic-wlan.c	/^int wifi_set_power(int on, unsigned long msec)$/;"	f	signature:(int on, unsigned long msec)
+wifi_set_reset	platforms/a33-generic-wlan.c	/^int wifi_set_reset(int on, unsigned long msec)$/;"	f	signature:(int on, unsigned long msec)
+wifi_set_reset	platforms/atm7039-action-generic-wlan.c	/^int wifi_set_reset(int on, unsigned long msec)$/;"	f	signature:(int on, unsigned long msec)
+wifi_set_reset	platforms/h3-generic-wlan.c	/^int wifi_set_reset(int on, unsigned long msec)$/;"	f	signature:(int on, unsigned long msec)
+wifi_set_reset	platforms/h8-generic-wlan.c	/^int wifi_set_reset(int on, unsigned long msec)$/;"	f	signature:(int on, unsigned long msec)
+wifi_set_reset	platforms/t10-generic-wlan.c	/^int wifi_set_reset(int on, unsigned long msec)$/;"	f	signature:(int on, unsigned long msec)
+wifi_set_reset	platforms/x1000-generic-wlan.c	/^int wifi_set_reset(int on, unsigned long msec)$/;"	f	signature:(int on, unsigned long msec)
+wifi_setup_dt	platforms/aml-s805-generic-wlan.c	/^extern int wifi_setup_dt(void);$/;"	p	file:	signature:(void)
+wifi_setup_dt	platforms/aml-s905-generic-wlan.c	/^extern int wifi_setup_dt(void);$/;"	p	file:	signature:(void)
+wifi_suspend	platforms/a33-generic-wlan.c	/^static int wifi_suspend(struct platform_device *pdev, pm_message_t state)$/;"	f	file:	signature:(struct platform_device *pdev, pm_message_t state)
+wifi_suspend	platforms/atm7039-action-generic-wlan.c	/^static int wifi_suspend(struct platform_device *pdev, pm_message_t state)$/;"	f	file:	signature:(struct platform_device *pdev, pm_message_t state)
+wifi_suspend	platforms/h3-generic-wlan.c	/^static int wifi_suspend(struct platform_device *pdev, pm_message_t state)$/;"	f	file:	signature:(struct platform_device *pdev, pm_message_t state)
+wifi_suspend	platforms/h8-generic-wlan.c	/^static int wifi_suspend(struct platform_device *pdev, pm_message_t state)$/;"	f	file:	signature:(struct platform_device *pdev, pm_message_t state)
+wifi_suspend	platforms/rk3126-generic-wlan.c	/^static int wifi_suspend(struct platform_device *pdev, pm_message_t state)$/;"	f	file:	signature:(struct platform_device *pdev, pm_message_t state)
+wifi_suspend	platforms/t10-generic-wlan.c	/^static int wifi_suspend(struct platform_device *pdev, pm_message_t state)$/;"	f	file:	signature:(struct platform_device *pdev, pm_message_t state)
+wifi_suspend	platforms/x1000-generic-wlan.c	/^static int wifi_suspend(struct platform_device *pdev, pm_message_t state)$/;"	f	file:	signature:(struct platform_device *pdev, pm_message_t state)
+wifi_sync_notify_hop	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	/^SDK_API void wifi_sync_notify_hop(int channel);$/;"	p	signature:(int channel)
+wifi_tx_gain	include/ssv6200_configuration.h	/^static const u32 wifi_tx_gain[]={$/;"	v
+wifi_tx_gain_level_b	include/ssv_cfg.h	/^    u32 wifi_tx_gain_level_b;$/;"	m	struct:ssv6xxx_cfg	access:public
+wifi_tx_gain_level_gn	include/ssv_cfg.h	/^    u32 wifi_tx_gain_level_gn;$/;"	m	struct:ssv6xxx_cfg	access:public
+wifi_wakeup_irq_handler	platforms/a33-generic-wlan.c	/^static irqreturn_t wifi_wakeup_irq_handler(int irq, void *dev)$/;"	f	file:	signature:(int irq, void *dev)
+wifi_wakeup_irq_handler	platforms/atm7039-action-generic-wlan.c	/^static irqreturn_t wifi_wakeup_irq_handler(int irq, void *dev)$/;"	f	file:	signature:(int irq, void *dev)
+wifi_wakeup_irq_handler	platforms/h3-generic-wlan.c	/^static irqreturn_t wifi_wakeup_irq_handler(int irq, void *dev){$/;"	f	file:	signature:(int irq, void *dev)
+wifi_wakeup_irq_handler	platforms/h8-generic-wlan.c	/^static irqreturn_t wifi_wakeup_irq_handler(int irq, void *dev){$/;"	f	file:	signature:(int irq, void *dev)
+wifi_wakeup_irq_handler	platforms/rk3126-generic-wlan.c	/^static irqreturn_t wifi_wakeup_irq_handler(int irq, void *dev)$/;"	f	file:	signature:(int irq, void *dev)
+wifi_wakeup_irq_handler	platforms/t10-generic-wlan.c	/^static irqreturn_t wifi_wakeup_irq_handler(int irq, void *dev){$/;"	f	file:	signature:(int irq, void *dev)
+wifi_wakeup_irq_handler	platforms/x1000-generic-wlan.c	/^static irqreturn_t wifi_wakeup_irq_handler(int irq, void *dev){$/;"	f	file:	signature:(int irq, void *dev)
+wifisyncerror	smartlink/qqlink-lib-mipsel/include/TXWifisync.h	/^enum wifisyncerror {$/;"	g
+wildcard_bssid	include/ssv6200_common.h	/^    u32 wildcard_bssid:1;$/;"	m	struct:ssv6200_rx_desc	access:public
+wiphy_info	smac/linux_2_6_35.h	30;"	d
+wlan_rx_wapi_decryption	smac/sec_wpi.c	/^u16 wlan_rx_wapi_decryption(u8 * input_ptk,u16 header_len,u16 data_len,$/;"	f	signature:(u8 * input_ptk,u16 header_len,u16 data_len, u8 * output_buf, void *priv)
+wlan_tx_wapi_encryption	smac/sec_wpi.c	/^u16 wlan_tx_wapi_encryption(u8 * header,$/;"	f	signature:(u8 * header, u8 * data,u16 data_len, u8 * mic_pos, void *priv)
+work	hwif/usb/usb.h	/^    struct work_struct work;$/;"	m	struct:ssv6xxx_usb_work_struct	typeref:struct:ssv6xxx_usb_work_struct::work_struct	access:public
+wowlan_support	smac/init.c	/^static const struct wiphy_wowlan_support wowlan_support = {$/;"	v	typeref:struct:wiphy_wowlan_support	file:
+wpa_ret	script/scan_conn.sh	/^wpa_ret ( )$/;"	f
+wq	hwif/usb/usb.c	/^ struct workqueue_struct *wq;$/;"	m	struct:ssv6xxx_usb_glue	typeref:struct:ssv6xxx_usb_glue::workqueue_struct	file:	access:public
+wreg	hwif/usb/usb.h	/^ struct ssv6xxx_write_reg wreg;$/;"	m	union:ssv6xxx_payload	typeref:struct:ssv6xxx_payload::ssv6xxx_write_reg	access:public
+write	hwif/hwif.h	/^    int __must_check (*write)(struct device *child, void *buf, size_t len,u8 queue_num);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+write_efuse	smac/dev.h	/^    void (*write_efuse)(struct ssv_hw *sh, u8 *data, u8 data_length);$/;"	m	struct:ssv_hal_ops	access:public
+write_efuse	smac/efuse.c	/^void write_efuse(struct ssv_hw *sh, u8 *data, u8 data_length)$/;"	f	signature:(struct ssv_hw *sh, u8 *data, u8 data_length)
+write_efuse	smac/efuse.h	/^void write_efuse(struct ssv_hw *sh, u8 *data, u8 data_length);$/;"	p	signature:(struct ssv_hw *sh, u8 *data, u8 data_length)
+write_group_key_to_hw	smac/dev.h	/^    int (*write_group_key_to_hw) (struct ssv_softc *sc, int index, u8 algorithm, const u8 *key, int key_len,$/;"	m	struct:ssv_hal_ops	access:public
+write_group_keyidx_to_hw	smac/dev.h	/^    void (*write_group_keyidx_to_hw)(struct ssv_hw *sh, struct ssv_vif_priv_data *vif_priv, int key_idx);$/;"	m	struct:ssv_hal_ops	access:public
+write_hw_config	hci/hctrl.h	/^    int write_hw_config;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+write_hw_config_args	smac/dev.h	/^    void *write_hw_config_args;$/;"	m	struct:ssv_hw	access:public
+write_hw_config_cb	hci/ssv_hci.h	/^    void (*write_hw_config_cb)(void *param, u32 addr, u32 value);$/;"	m	struct:ssv6xxx_hci_info	access:public
+write_hw_config_cb	smac/dev.h	/^    void (*write_hw_config_cb)(void *param, u32 addr, u32 value);$/;"	m	struct:ssv_hw	access:public
+write_key_to_hw	smac/dev.h	/^    void (*write_key_to_hw)(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv,$/;"	m	struct:ssv_hal_ops	access:public
+write_mac_ini	smac/dev.h	/^    int (*write_mac_ini)(struct ssv_hw *sh);$/;"	m	struct:ssv_hal_ops	access:public
+write_mac_to_file	smac/efuse.c	/^static int write_mac_to_file(u8 *mac_path,u8 *mac_addr)$/;"	f	file:	signature:(u8 *mac_path,u8 *mac_addr)
+write_pairwise_key_to_hw	smac/dev.h	/^    int (*write_pairwise_key_to_hw) (struct ssv_softc *sc, int index, u8 algorithm, const u8 *key, int key_len,$/;"	m	struct:ssv_hal_ops	access:public
+write_pairwise_keyidx_to_hw	smac/dev.h	/^    void (*write_pairwise_keyidx_to_hw)(struct ssv_hw *sh, int key_idx, int wsid);$/;"	m	struct:ssv_hal_ops	access:public
+write_sram	hwif/hwif.h	/^    int (*write_sram)(struct device *child, u32 addr, u8 *data, u32 size);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+writereg	hwif/hwif.h	/^    int __must_check (*writereg)(struct device *child, u32 addr, u32 buf);$/;"	m	struct:ssv6xxx_hwif_ops	access:public
+wsid	include/ssv6200_common.h	/^    u32 wsid:4;$/;"	m	struct:ssv6200_rx_desc	access:public
+wsid	include/ssv6200_common.h	/^    u32 wsid:4;$/;"	m	struct:ssv6200_tx_desc	access:public
+wsid	include/ssv6200_common.h	/^    u8 wsid;$/;"	m	struct:ampdu_ba_notify_data	access:public
+wsid	include/ssv6200_common.h	/^    u8 wsid;$/;"	m	struct:firmware_rate_control_report_data	access:public
+wsid	smac/hal/ssv6006c/turismo_common.h	/^    u32 wsid:4;$/;"	m	struct:ssv6006_rx_desc	access:public
+wsid	smac/hal/ssv6006c/turismo_common.h	/^    u32 wsid:4;$/;"	m	struct:ssv6006_tx_desc	access:public
+wsid_idx	include/ssv6xxx_common.h	/^    u8 wsid_idx;$/;"	m	struct:ssv6xxx_wsid_params	access:public
+xmit_running	hci/hctrl.h	/^    u32 xmit_running;$/;"	m	struct:ssv6xxx_hci_ctrl	access:public
+xor_block	smac/sec_ccmp.c	/^static inline void xor_block(u8 * b, u8 * a, size_t len)$/;"	f	file:	signature:(u8 * b, u8 * a, size_t len)
+xtal	smac/hal/ssv6006c/turismo_common.h	/^    u16 xtal;$/;"	m	struct:ssv6006_patch	access:public
+xtal_offset	smac/dev.h	/^    u16 xtal_offset;$/;"	m	struct:ssv_tempe_table	access:public
+xtal_offset_high_boundary	smac/dev.h	/^    u8 xtal_offset_high_boundary;$/;"	m	struct:ssv_flash_config	access:public
+xtal_offset_high_boundary	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 xtal_offset_high_boundary;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+xtal_offset_ht_config	smac/hal/ssv6006c/ssv6006_mac.h	/^    u16 xtal_offset_ht_config;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+xtal_offset_low_boundary	smac/dev.h	/^    u8 xtal_offset_low_boundary;$/;"	m	struct:ssv_flash_config	access:public
+xtal_offset_low_boundary	smac/hal/ssv6006c/ssv6006_mac.h	/^    u8 xtal_offset_low_boundary;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+xtal_offset_lt_config	smac/hal/ssv6006c/ssv6006_mac.h	/^    u16 xtal_offset_lt_config;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+xtal_offset_rt_config	smac/hal/ssv6006c/ssv6006_mac.h	/^    u16 xtal_offset_rt_config;$/;"	m	struct:ssv6006_flash_layout_table	access:public
+xtal_offset_tempe_state	smac/dev.h	/^    u8 xtal_offset_tempe_state;$/;"	m	struct:ssv_flash_config	access:public
+xtal_sx_cp_isel_wf	smac/hal/ssv6006c/turismo_common.c	/^const u8 xtal_sx_cp_isel_wf[11] = { 0x8, 0x5, 0x5, 0x7, 0xb, 0x7, 0x5, 0x8, 0x7, 0x7, 0x5};$/;"	v
+xtal_type	smac/hal/ssv6006c/turismo_common.c	/^const char* xtal_type[XTALMAX]= { "16", "24", "26", "40", "12", "20", "25", "32", "19.2", "38.4", "52"};$/;"	v
diff --git a/drivers/net/wireless/ssv6x5x/umac/Makefile b/drivers/net/wireless/ssv6x5x/umac/Makefile
new file mode 100755
index 000000000..4c0bf1bf2
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/umac/Makefile
@@ -0,0 +1,18 @@
+ifeq ($(KBUILD_TOP),)
+    ifneq ($(KBUILD_EXTMOD),)
+    KBUILD_DIR := $(KBUILD_EXTMOD)
+    else
+    KBUILD_DIR := $(PWD)
+    endif
+KBUILD_TOP := $(KBUILD_DIR)/../
+endif
+
+include $(KBUILD_TOP)/config.mak
+
+KBUILD_EXTRA_SYMBOLS += $(KBUILD_TOP)/ssvdevice/Module.symvers
+KBUILD_EXTRA_SYMBOLS += $(KBUILD_TOP)/smac/Module.symvers
+
+KMODULE_NAME=ssv6xxx_umac_core
+KERN_SRCS := ssv6xxx_netlink_core.c
+
+include $(KBUILD_TOP)/rules.mak
diff --git a/drivers/net/wireless/ssv6x5x/umac/ssv6xxx_netlink_core.c b/drivers/net/wireless/ssv6x5x/umac/ssv6xxx_netlink_core.c
new file mode 100644
index 000000000..597d77062
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/umac/ssv6xxx_netlink_core.c
@@ -0,0 +1,321 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/version.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <net/genetlink.h>
+#include <linux/skbuff.h>
+#include <linux/platform_device.h>
+#include <linux/pid.h>
+#include <linux/sched.h>
+#include <linux/pid_namespace.h>
+#include <ssv6200_reg.h>
+#include <ssv6200.h>
+#include <hci/hctrl.h>
+#include <smac/dev.h>
+#include <smac/init.h>
+#include "ssv6xxx_netlink_core.h"
+static char *attach_driver_name = "TU SSV WLAN driver";
+module_param(attach_driver_name, charp, S_IRUGO|S_IWUSR);
+static char *attach_device_name = "SSV6XXX";
+module_param(attach_device_name, charp, S_IRUGO|S_IWUSR);
+#define MAX_SSV_WIRELESS_PATTERN 32767
+static struct nla_policy ssv_wireless_genl_policy[SSV_WIRELESS_ATTR_MAX + 1] = {
+    [SSV_WIRELESS_ATTR_CONFIG] = { .type = NLA_U32 },
+    [SSV_WIRELESS_ATTR_REGISTER] = { .len = sizeof(struct ssv_wireless_register) },
+    [SSV_WIRELESS_ATTR_TXFRAME] = { .type = NLA_BINARY, .len = MAX_SSV_WIRELESS_PATTERN },
+    [SSV_WIRELESS_ATTR_RXFRAME] = { .type = NLA_BINARY, .len = MAX_SSV_WIRELESS_PATTERN },
+    [SSV_WIRELESS_ATTR_START_HCI] = { .type = NLA_U32 },
+    [SSV_WIRELESS_ATTR_TEST] = { .type = NLA_BINARY, .len = MAX_SSV_WIRELESS_PATTERN },
+};
+static struct genl_family ssv_wireless_gnl_family = {
+    .id = GENL_ID_GENERATE,
+    .hdrsize = 0,
+    .name = "SSV_WIRELESS",
+    .version = 1,
+    .maxattr = SSV_WIRELESS_ATTR_MAX,
+};
+static u32 ssv6xxx_user_app_pid = 0;
+int ssv_wireless_config(struct sk_buff *skb, struct genl_info *info)
+{
+    if (info == NULL)
+        return -EINVAL;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,7,0)
+    ssv6xxx_user_app_pid = info->snd_portid;
+#else
+    ssv6xxx_user_app_pid = info->snd_pid;
+#endif
+    printk("config ssv6xxx user application pid[%d]\n", ssv6xxx_user_app_pid);
+    return 0;
+}
+int ssv_wireless_start_hci(struct sk_buff *skb, struct genl_info *info)
+{
+    if (info == NULL)
+        return -EINVAL;
+    printk("start HCI\n");
+    ssv6xxx_umac_hci_start(attach_driver_name, attach_device_name);
+    return 0;
+}
+int ssv_wireless_test(struct sk_buff *skb, struct genl_info *info)
+{
+    struct nlattr *na;
+    int sdio_dma_data_len;
+    char *data;
+    struct sk_buff *sdio_dma_frame;
+    if (info == NULL)
+        return -EINVAL;
+    na = info->attrs[SSV_WIRELESS_ATTR_TEST];
+    if (na) {
+        if ((data = (char *)nla_data(na)) == NULL)
+            return -EINVAL;
+        sdio_dma_data_len = na->nla_len - NLA_HDRLEN;
+    } else
+        return -EINVAL;
+    sdio_dma_frame = alloc_skb(sdio_dma_data_len, GFP_ATOMIC);
+    if (sdio_dma_frame == NULL)
+        return -EINVAL;
+    skb_put(sdio_dma_frame, sdio_dma_data_len);
+    memcpy(sdio_dma_frame->data, data, sdio_dma_data_len);
+    ssv6xxx_umac_test(attach_driver_name, attach_device_name, sdio_dma_frame, sdio_dma_data_len);
+    kfree_skb(sdio_dma_frame);
+    return 0;
+}
+int ssv_wireless_read_register(struct sk_buff *skb, struct genl_info *info)
+{
+    struct nlattr *na;
+    struct sk_buff *msg;
+    int retval;
+    void *msg_head;
+    struct ssv_wireless_register *reg;
+    if (info == NULL)
+        return -EINVAL;
+    na = info->attrs[SSV_WIRELESS_ATTR_REGISTER];
+    if (na) {
+        if ((reg = (struct ssv_wireless_register *)nla_data(na)) == NULL)
+            return -EINVAL;
+    } else
+        return -EINVAL;
+    ssv6xxx_umac_reg_read(attach_driver_name, attach_device_name, reg->address, &reg->value);
+    msg = genlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL);
+    if (msg == NULL)
+        return -ENOMEM;
+    msg_head = genlmsg_put(msg, 0, info->snd_seq+1, &ssv_wireless_gnl_family, 0, SSV_WIRELESS_CMD_READ_REG);
+    if (msg_head == NULL) {
+        retval = -ENOMEM;
+        printk("Fail to create the netlink message header\n");
+        goto free_msg;
+    }
+    retval = nla_put(msg, SSV_WIRELESS_ATTR_REGISTER, sizeof(struct ssv_wireless_register), reg);
+    if (retval != 0) {
+        printk("Fail to add attribute in message\n");
+        goto free_msg;
+    }
+    genlmsg_end(msg, msg_head);
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,7,0)
+    return genlmsg_unicast(genl_info_net(info), msg, info->snd_portid);
+#else
+    return genlmsg_unicast(genl_info_net(info), msg, info->snd_pid);
+#endif
+free_msg:
+    nlmsg_free(msg);
+    return retval;
+}
+int ssv_wireless_write_register(struct sk_buff *skb, struct genl_info *info)
+{
+    struct nlattr *na;
+    struct sk_buff *msg;
+    int retval;
+    void *msg_head;
+    struct ssv_wireless_register *reg;
+    if (info == NULL)
+        return -EINVAL;
+    na = info->attrs[SSV_WIRELESS_ATTR_REGISTER];
+    if (na) {
+        if ((reg = (struct ssv_wireless_register *)nla_data(na)) == NULL)
+            return -EINVAL;
+    } else
+        return -EINVAL;
+    ssv6xxx_umac_reg_write(attach_driver_name, attach_device_name, reg->address, reg->value);
+    msg = genlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL);
+    if (msg == NULL)
+        return -ENOMEM;
+    msg_head = genlmsg_put(msg, 0, info->snd_seq+1, &ssv_wireless_gnl_family, 0, SSV_WIRELESS_CMD_WRITE_REG);
+    if (msg_head == NULL) {
+        retval = -ENOMEM;
+        printk("Fail to create the netlink message header\n");
+        goto free_msg;
+    }
+    retval = nla_put(msg, SSV_WIRELESS_ATTR_REGISTER, sizeof(struct ssv_wireless_register), reg);
+    if (retval != 0) {
+        printk("Fail to add attribute in message\n");
+        goto free_msg;
+    }
+    genlmsg_end(msg, msg_head);
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,7,0)
+    return genlmsg_unicast(genl_info_net(info), msg, info->snd_portid);
+#else
+    return genlmsg_unicast(genl_info_net(info), msg, info->snd_pid);
+#endif
+free_msg:
+    nlmsg_free(msg);
+    return retval;
+}
+int ssv_wireless_tx_frame(struct sk_buff *skb, struct genl_info *info)
+{
+    struct nlattr *na;
+    int tx_data_len;
+    char *data;
+    struct sk_buff *tx_frame;
+    if (info == NULL)
+        return -EINVAL;
+    na = info->attrs[SSV_WIRELESS_ATTR_TXFRAME];
+    if (na) {
+        if ((data = (char *)nla_data(na)) == NULL)
+            return -EINVAL;
+        tx_data_len = na->nla_len - NLA_HDRLEN;
+        printk("tx_data_len=%x\n",tx_data_len);
+    } else
+        return -EINVAL;
+    tx_frame = alloc_skb(tx_data_len, GFP_ATOMIC);
+    if (tx_frame == NULL)
+        return -EINVAL;
+    skb_put(tx_frame, tx_data_len);
+    memcpy(tx_frame->data, data, tx_data_len);
+    ssv6xxx_umac_tx_frame(attach_driver_name, attach_device_name, tx_frame);
+    kfree_skb(tx_frame);
+    return 0;
+}
+static int ssv_wireless_umac_rx_raw(struct sk_buff *skb)
+{
+    struct sk_buff *msg;
+    int retval;
+    void *msg_head;
+    struct pid *pid_struct;
+    struct task_struct *task;
+    u32 pid = ssv6xxx_user_app_pid;
+    if (pid == 0) {
+        printk("The destination is not ready!");
+        return 0;
+    }
+    pid_struct = find_get_pid(pid);
+    if ((task = pid_task(pid_struct, PIDTYPE_PID)) == NULL) {
+        printk("Userspace appllication is not existed!");
+        return 0;
+    }
+    msg = genlmsg_new(MAX_SSV_WIRELESS_PATTERN, GFP_KERNEL);
+    if (msg == NULL)
+        return -ENOMEM;
+    msg_head = genlmsg_put(msg, 0, 0, &ssv_wireless_gnl_family, 0, SSV_WIRELESS_CMD_RXFRAME);
+    if (msg_head == NULL) {
+        retval = -ENOMEM;
+        printk("Fail to create the netlink message header\n");
+        goto free_msg;
+    }
+    retval = nla_put(msg, SSV_WIRELESS_ATTR_RXFRAME, skb->len, skb->data);
+    if (retval != 0) {
+        printk("Fail to add attribute in message\n");
+        goto free_msg;
+    }
+    genlmsg_end(msg, msg_head);
+    return genlmsg_unicast(&init_net, msg, pid);
+free_msg:
+    nlmsg_free(msg);
+    return retval;
+}
+struct ssv6xxx_umac_ops ssv_umac = {
+    .umac_rx_raw = ssv_wireless_umac_rx_raw,
+};
+struct genl_ops ssv_wireless_gnl_ops[] = {
+    {
+        .cmd = SSV_WIRELESS_CMD_CONFIG,
+        .flags = 0,
+        .policy = ssv_wireless_genl_policy,
+        .doit = ssv_wireless_config,
+        .dumpit = NULL,
+    },
+    {
+        .cmd = SSV_WIRELESS_CMD_READ_REG,
+        .flags = 0,
+        .policy = ssv_wireless_genl_policy,
+        .doit = ssv_wireless_read_register,
+        .dumpit = NULL,
+    },
+    {
+        .cmd = SSV_WIRELESS_CMD_WRITE_REG,
+        .flags = 0,
+        .policy = ssv_wireless_genl_policy,
+        .doit = ssv_wireless_write_register,
+        .dumpit = NULL,
+    },
+    {
+        .cmd = SSV_WIRELESS_CMD_TXFRAME,
+        .flags = 0,
+        .policy = ssv_wireless_genl_policy,
+        .doit = ssv_wireless_tx_frame,
+        .dumpit = NULL,
+    },
+    {
+        .cmd = SSV_WIRELESS_CMD_START_HCI,
+        .flags = 0,
+        .policy = ssv_wireless_genl_policy,
+        .doit = ssv_wireless_start_hci,
+        .dumpit = NULL,
+    },
+    {
+        .cmd = SSV_WIRELESS_CMD_TEST,
+        .flags = 0,
+        .policy = ssv_wireless_genl_policy,
+        .doit = ssv_wireless_test,
+        .dumpit = NULL,
+    },
+};
+static int __init ssv_netlink_init(void)
+{
+    int rc;
+    printk("INIT SSV WIRELESS GENERIC NETLINK MODULE\n");
+    rc = ssv6xxx_umac_attach(attach_driver_name, attach_device_name, &ssv_umac);
+    if (rc != 0)
+        return -1;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,13,0)
+    rc = genl_register_family_with_ops(&ssv_wireless_gnl_family,
+                                       ssv_wireless_gnl_ops);
+#else
+    rc = genl_register_family_with_ops(&ssv_wireless_gnl_family,
+                                       ssv_wireless_gnl_ops, ARRAY_SIZE(ssv_wireless_gnl_ops));
+#endif
+    if (rc != 0) {
+        printk("Fail to insert SSV WIRELESS NETLINK MODULE\n");
+        return -1;
+    }
+    return 0;
+}
+static void __exit ssv_netlink_exit(void)
+{
+    int rc;
+    printk("EXIT SSV WIRELESS GENERIC NETLINK MODULE\n");
+    rc = genl_unregister_family(&ssv_wireless_gnl_family);
+    if (rc != 0)
+        printk("unregister family %d\n", rc);
+    rc = ssv6xxx_umac_deattach(attach_driver_name, attach_device_name);
+    if (rc != 0)
+        printk("Fail to deattach ssv wlan umac\n");
+}
+module_init(ssv_netlink_init);
+module_exit(ssv_netlink_exit);
+MODULE_AUTHOR("iComm-semi, Ltd");
+MODULE_DESCRIPTION("Support for SSV6xxx wireless LAN cards.");
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/drivers/net/wireless/ssv6x5x/umac/ssv6xxx_netlink_core.h b/drivers/net/wireless/ssv6x5x/umac/ssv6xxx_netlink_core.h
new file mode 100644
index 000000000..e60fa1b38
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/umac/ssv6xxx_netlink_core.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2015 iComm-semi Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV6XXX_NETLINK_CORE_H_
+#define _SSV6XXX_NETLINK_CORE_H_
+struct ssv_wireless_register {
+    u32 address;
+    u32 value;
+};
+enum {
+    SSV_WIRELESS_ATTR_UNSPEC,
+    SSV_WIRELESS_ATTR_CONFIG,
+    SSV_WIRELESS_ATTR_REGISTER,
+    SSV_WIRELESS_ATTR_TXFRAME,
+    SSV_WIRELESS_ATTR_RXFRAME,
+    SSV_WIRELESS_ATTR_START_HCI,
+    SSV_WIRELESS_ATTR_TEST,
+    __SSV_WIRELESS_ATTR_MAX,
+};
+#define SSV_WIRELESS_ATTR_MAX (__SSV_WIRELESS_ATTR_MAX - 1)
+enum {
+    SSV_WIRELESS_CMD_UNSPEC,
+    SSV_WIRELESS_CMD_CONFIG,
+    SSV_WIRELESS_CMD_READ_REG,
+    SSV_WIRELESS_CMD_WRITE_REG,
+    SSV_WIRELESS_CMD_TXFRAME,
+    SSV_WIRELESS_CMD_RXFRAME,
+    SSV_WIRELESS_CMD_START_HCI,
+    SSV_WIRELESS_CMD_TEST,
+    __SSV_WIRELESS_CMD_MAX,
+};
+#define SSV_WIRELESS_CMD_MAX (__SSV_WIRELESS_CMD_MAX - 1)
+#endif
diff --git a/drivers/net/wireless/ssv6x5x/unload.sh b/drivers/net/wireless/ssv6x5x/unload.sh
new file mode 100755
index 000000000..189ee3fe0
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/unload.sh
@@ -0,0 +1,19 @@
+#/bin/bash
+
+rmmod ssv6200s_core
+rmmod hci_wrapper
+rmmod ssv6200_hci
+rmmod ssvdevicetype
+
+rmmod ssv_mac80211
+
+rmmod ssv6200_sdiobridge
+rmmod ssv6200_sdio
+rmmod ssv6200_usb
+
+rmmod mmc_core
+rmmod mmc_block
+
+rmmod sdhci
+rmmod sdhci_pci
+
diff --git a/drivers/net/wireless/ssv6x5x/vars.sh b/drivers/net/wireless/ssv6x5x/vars.sh
new file mode 100755
index 000000000..6897f6476
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/vars.sh
@@ -0,0 +1,3 @@
+export KSRC=/lib/modules/$(uname -r)/build
+export CROSS_COMPILE=arm-linux-gnueabihf-
+export ARCH=arm
diff --git a/drivers/net/wireless/ssv6x5x/ver_info.pl b/drivers/net/wireless/ssv6x5x/ver_info.pl
new file mode 100755
index 000000000..7d5b997cf
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/ver_info.pl
@@ -0,0 +1,87 @@
+#!/usr/bin/perl
+
+use strict;
+
+my @tmp_string;
+my $svn_status;
+my $svn_filename;
+my $svn_version;
+
+my $svn_root = ".";
+my $svn_root_version;
+my $svn_root_url;
+
+my @header_defines = (
+    "#ifndef _SSV_VERSION_H_",
+    "#define _SSV_VERSION_H_",
+    "",
+);
+
+sub get_version {
+    foreach (@_) {
+        if($_ =~ m/^Last Changed Rev: (\d*)/) {
+            return $1;
+        }
+    } 
+    # file doesn't exist on svn
+    return -1;
+}
+
+sub get_url {
+    foreach (@_) {
+        if($_ =~ m/^URL: (.*)/) {
+            return $1;
+        }
+    } 
+    # file doesn't exist on svn
+    return -1;
+}
+
+printf("## script to generate version infomation header ##\n");
+
+# step-0: get root svn number 
+$svn_root_version = get_version(qx(svn info $svn_root));
+
+if ($svn_root_version == -1) {
+    exit 0;
+}
+
+# step-1: get root svn url 
+$svn_root_url = get_url(qx(svn info $svn_root));
+
+OUTPUT_HEADER:
+# step-3: output header files
+if (defined($ARGV[0])) {
+    open HEADER, ">", $ARGV[0];
+    select HEADER;
+}
+else {
+    print "Error! Please specify header file\n";
+}
+
+
+foreach (@header_defines) {
+    printf("%s\n", $_);
+}
+
+##
+printf("static u32 ssv_root_version = %d;\n\n", $svn_root_version);
+printf("#define SSV_ROOT_URl \"$svn_root_url\"\n");
+
+use Sys::Hostname;
+my $host = hostname();
+
+printf("#define COMPILERHOST \"$host\"\n");
+
+use POSIX qw(strftime);
+my $date = strftime "%m-%d-%Y-%H:%M:%S", localtime;
+printf("#define COMPILERDATE \"$date\"\n");
+##
+
+use Config;
+printf("#define COMPILEROS \"$Config{osname}\"\n");
+printf("#define COMPILEROSARCH \"$Config{archname}\"\n");
+
+printf("\n#endif\n\n");
+
+exit 1;
diff --git a/drivers/net/wireless/ssv6x5x/wpa_supplicant.conf b/drivers/net/wireless/ssv6x5x/wpa_supplicant.conf
new file mode 100755
index 000000000..982f14eb6
--- /dev/null
+++ b/drivers/net/wireless/ssv6x5x/wpa_supplicant.conf
@@ -0,0 +1,36 @@
+ctrl_interface=DIR=/var/run/wpa_supplicants
+
+#open config
+#network={
+#    ssid="myssid"
+#    key_mgmt=NONE
+#}
+
+#wep config
+#network={
+#    ssid="myssid"
+#    key_mgmt=NONE
+#    auth_alg=OPEN
+#  	wep_key0="12345"
+#	  wep_tx_keyidx=0
+#}
+#
+#tkip config
+network={
+    ssid="testQAAP"
+    proto=WPA
+    key_mgmt=WPA-PSK
+    pairwise=TKIP
+  	group=TKIP
+	  psk="12345678"
+}
+
+#network={
+#    ssid="Liam_2G"
+#    psk="1234567890" 
+#    proto=WPA2
+#    key_mgmt=WPA-PSK 
+#    pairwise=CCMP 
+#    group=CCMP
+#}
+#
diff --git a/drivers/net/wireless/Kconfig b/drivers/net/wireless/Kconfig
index 760c0ed71..3554a54e5 100644
--- a/drivers/net/wireless/Kconfig
+++ b/drivers/net/wireless/Kconfig
@@ -294,5 +294,6 @@ source "drivers/net/wireless/mwifiex/Kconfig"
 source "drivers/net/wireless/cw1200/Kconfig"
 source "drivers/net/wireless/rsi/Kconfig"
 source "drivers/net/wireless/esp8089/Kconfig"
+source "drivers/net/wireless/ssv6x5x/Kconfig"
 
 endif # WLAN
diff --git a/drivers/net/wireless/Makefile b/drivers/net/wireless/Makefile
index 81587dce2..f5742603f 100644
--- a/drivers/net/wireless/Makefile
+++ b/drivers/net/wireless/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_B43LEGACY)		+= b43legacy/
 obj-$(CONFIG_ZD1211RW)		+= zd1211rw/
 obj-$(CONFIG_WLAN)		+= realtek/
 obj-$(CONFIG_ESP8089)           += esp8089/
+obj-$(CONFIG_SSV6X5X)           += ssv6x5x/
 
 # 16-bit wireless PCMCIA client drivers
 obj-$(CONFIG_PCMCIA_RAYCS)	+= ray_cs.o

